2006.285.05:21:19.78;Log Opened: Mark IV Field System Version 9.7.7 2006.285.05:21:19.78;location,TSUKUB32,-140.09,36.10,61.0 2006.285.05:21:19.78;horizon1,0.,5.,360. 2006.285.05:21:19.78;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.285.05:21:19.78;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.285.05:21:19.78;drivev11,330,270,no 2006.285.05:21:19.78;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.285.05:21:19.78;drivev13,15.000,268,10.000,10.000,10.000 2006.285.05:21:19.78;drivev21,330,270,no 2006.285.05:21:19.78;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.285.05:21:19.78;drivev23,15.000,268,10.000,10.000,10.000 2006.285.05:21:19.78;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.285.05:21:19.78;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.285.05:21:19.78;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.285.05:21:19.78;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.285.05:21:19.78;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.285.05:21:19.78;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.285.05:21:19.78;time,-0.364,101.533,rate 2006.285.05:21:19.78;flagr,200 2006.285.05:21:19.78:" JD0610 2006 TSUKUB32 T Ts 2006.285.05:21:19.78:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.285.05:21:19.78:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.285.05:21:19.78:" 108 K4-TSUKB 0 9149 2006.285.05:21:19.78:" drudg version 050216 compiled under FS 9.7.07 2006.285.05:21:19.78:" Rack=K4-2/M4 Recorder 1=K4-2 Recorder 2=none 2006.285.05:21:19.78:exper_initi 2006.285.05:21:19.78&exper_initi/proc_library 2006.285.05:21:19.78&exper_initi/sched_initi 2006.285.05:21:19.78:scan_name=285-0600,jd0610,90 2006.285.05:21:19.78:source=3c274,123049.42,122328.0,2000.0,ccw 2006.285.05:21:19.78#antcn#PM 1 00019 2005 228 00 22 31 00 2006.285.05:21:19.78#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.285.05:21:19.78#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.285.05:21:19.78#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.285.05:21:19.78#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.285.05:21:19.78#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.285.05:21:20.14#flagr#flagr/antenna,new-source 2006.285.05:21:20.14:ready_k5 2006.285.05:21:20.14&ready_k5/obsinfo=st 2006.285.05:21:20.14&ready_k5/autoobs=1 2006.285.05:21:20.14&ready_k5/autoobs=2 2006.285.05:21:20.14&ready_k5/autoobs=3 2006.285.05:21:20.14&ready_k5/autoobs=4 2006.285.05:21:20.14&ready_k5/obsinfo 2006.285.05:21:20.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.285.05:21:23.85/autoobs//k5ts1/ autoobs started! 2006.285.05:21:27.50/autoobs//k5ts2/ autoobs started! 2006.285.05:21:30.92/autoobs//k5ts3/ autoobs started! 2006.285.05:21:34.43/autoobs//k5ts4/ autoobs started! 2006.285.05:21:34.46/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.05:21:34.46:setupk4=1 2006.285.05:21:34.46&setupk4/xlog=on 2006.285.05:21:34.46&setupk4/echo=on 2006.285.05:21:34.46&setupk4/pcalon 2006.285.05:21:34.46&setupk4/"tpicd=stop 2006.285.05:21:34.46&setupk4/"rec=synch_on 2006.285.05:21:34.46&setupk4/"rec_mode=128 2006.285.05:21:34.46&setupk4/!* 2006.285.05:21:34.46&setupk4/recpk4 2006.285.05:21:34.46&setupk4/vck44 2006.285.05:21:34.46&setupk4/ifdk4 2006.285.05:21:34.46&setupk4/!*+20s 2006.285.05:21:34.46&setupk4/"tpicd 2006.285.05:21:34.46&setupk4/echo=off 2006.285.05:21:34.46&setupk4/xlog=off 2006.285.05:21:34.46$setupk4/echo=on 2006.285.05:21:34.46$setupk4/pcalon 2006.285.05:21:34.46&pcalon/"no phase cal control is implemented here 2006.285.05:21:34.46$pcalon/"no phase cal control is implemented here 2006.285.05:21:34.46$setupk4/"tpicd=stop 2006.285.05:21:34.46$setupk4/"rec=synch_on 2006.285.05:21:34.46$setupk4/"rec_mode=128 2006.285.05:21:34.46$setupk4/!* 2006.285.05:21:34.46$setupk4/recpk4 2006.285.05:21:34.46&recpk4/recpatch= 2006.285.05:21:34.46&recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.05:21:34.46&recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.05:21:34.46$recpk4/recpatch= 2006.285.05:21:34.57$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.05:21:34.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.05:21:34.59$setupk4/vck44 2006.285.05:21:34.59&vck44/valo=1,524.99 2006.285.05:21:34.59&vck44/va=1,7 2006.285.05:21:34.59&vck44/valo=2,534.99 2006.285.05:21:34.59&vck44/va=2,6 2006.285.05:21:34.59&vck44/valo=3,564.99 2006.285.05:21:34.59&vck44/va=3,7 2006.285.05:21:34.59&vck44/valo=4,624.99 2006.285.05:21:34.59&vck44/va=4,6 2006.285.05:21:34.59&vck44/valo=5,734.99 2006.285.05:21:34.59&vck44/va=5,3 2006.285.05:21:34.59&vck44/valo=6,814.99 2006.285.05:21:34.59&vck44/va=6,4 2006.285.05:21:34.59&vck44/valo=7,864.99 2006.285.05:21:34.59&vck44/va=7,4 2006.285.05:21:34.59&vck44/valo=8,884.99 2006.285.05:21:34.59&vck44/va=8,3 2006.285.05:21:34.59&vck44/vblo=1,629.99 2006.285.05:21:34.59&vck44/vb=1,4 2006.285.05:21:34.59&vck44/vblo=2,634.99 2006.285.05:21:34.59&vck44/vb=2,5 2006.285.05:21:34.59&vck44/vblo=3,649.99 2006.285.05:21:34.59&vck44/vb=3,4 2006.285.05:21:34.59&vck44/vblo=4,679.99 2006.285.05:21:34.59&vck44/vb=4,5 2006.285.05:21:34.59&vck44/vblo=5,709.99 2006.285.05:21:34.59&vck44/vb=5,4 2006.285.05:21:34.59&vck44/vblo=6,719.99 2006.285.05:21:34.59&vck44/vb=6,3 2006.285.05:21:34.59&vck44/vblo=7,734.99 2006.285.05:21:34.59&vck44/vb=7,4 2006.285.05:21:34.59&vck44/vblo=8,744.99 2006.285.05:21:34.59&vck44/vb=8,4 2006.285.05:21:34.59&vck44/vabw=wide 2006.285.05:21:34.59&vck44/vbbw=wide 2006.285.05:21:34.59$vck44/valo=1,524.99 2006.285.05:21:34.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.05:21:34.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:34.59#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:34.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.05:21:34.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.05:21:34.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.05:21:34.59#ibcon#enter wrdev, iclass 16, count 0 2006.285.05:21:34.59#ibcon#first serial, iclass 16, count 0 2006.285.05:21:34.59#ibcon#enter sib2, iclass 16, count 0 2006.285.05:21:34.59#ibcon#flushed, iclass 16, count 0 2006.285.05:21:34.59#ibcon#about to write, iclass 16, count 0 2006.285.05:21:34.59#ibcon#wrote, iclass 16, count 0 2006.285.05:21:34.59#ibcon#about to read 3, iclass 16, count 0 2006.285.05:21:34.60#ibcon#read 3, iclass 16, count 0 2006.285.05:21:34.60#ibcon#about to read 4, iclass 16, count 0 2006.285.05:21:34.60#ibcon#read 4, iclass 16, count 0 2006.285.05:21:34.60#ibcon#about to read 5, iclass 16, count 0 2006.285.05:21:34.60#ibcon#read 5, iclass 16, count 0 2006.285.05:21:34.60#ibcon#about to read 6, iclass 16, count 0 2006.285.05:21:34.60#ibcon#read 6, iclass 16, count 0 2006.285.05:21:34.60#ibcon#end of sib2, iclass 16, count 0 2006.285.05:21:34.60#ibcon#*mode == 0, iclass 16, count 0 2006.285.05:21:34.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.05:21:34.60#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.05:21:34.60#ibcon#*before write, iclass 16, count 0 2006.285.05:21:34.60#ibcon#enter sib2, iclass 16, count 0 2006.285.05:21:34.60#ibcon#flushed, iclass 16, count 0 2006.285.05:21:34.60#ibcon#about to write, iclass 16, count 0 2006.285.05:21:34.60#ibcon#wrote, iclass 16, count 0 2006.285.05:21:34.60#ibcon#about to read 3, iclass 16, count 0 2006.285.05:21:34.66#ibcon#read 3, iclass 16, count 0 2006.285.05:21:34.73#ibcon#about to read 4, iclass 16, count 0 2006.285.05:21:34.73#ibcon#read 4, iclass 16, count 0 2006.285.05:21:34.73#ibcon#about to read 5, iclass 16, count 0 2006.285.05:21:34.73#ibcon#read 5, iclass 16, count 0 2006.285.05:21:34.73#ibcon#about to read 6, iclass 16, count 0 2006.285.05:21:34.73#ibcon#read 6, iclass 16, count 0 2006.285.05:21:34.73#ibcon#end of sib2, iclass 16, count 0 2006.285.05:21:34.73#ibcon#*after write, iclass 16, count 0 2006.285.05:21:34.73#ibcon#*before return 0, iclass 16, count 0 2006.285.05:21:34.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.05:21:34.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.05:21:34.73#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.05:21:34.73#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.05:21:34.73$vck44/va=1,7 2006.285.05:21:34.73#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.05:21:34.73#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.05:21:34.73#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:34.73#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:34.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:34.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:34.73#ibcon#enter wrdev, iclass 18, count 2 2006.285.05:21:34.73#ibcon#first serial, iclass 18, count 2 2006.285.05:21:34.73#ibcon#enter sib2, iclass 18, count 2 2006.285.05:21:34.73#ibcon#flushed, iclass 18, count 2 2006.285.05:21:34.73#ibcon#about to write, iclass 18, count 2 2006.285.05:21:34.73#ibcon#wrote, iclass 18, count 2 2006.285.05:21:34.73#ibcon#about to read 3, iclass 18, count 2 2006.285.05:21:34.74#ibcon#read 3, iclass 18, count 2 2006.285.05:21:34.74#ibcon#about to read 4, iclass 18, count 2 2006.285.05:21:34.74#ibcon#read 4, iclass 18, count 2 2006.285.05:21:34.74#ibcon#about to read 5, iclass 18, count 2 2006.285.05:21:34.74#ibcon#read 5, iclass 18, count 2 2006.285.05:21:34.74#ibcon#about to read 6, iclass 18, count 2 2006.285.05:21:34.74#ibcon#read 6, iclass 18, count 2 2006.285.05:21:34.74#ibcon#end of sib2, iclass 18, count 2 2006.285.05:21:34.74#ibcon#*mode == 0, iclass 18, count 2 2006.285.05:21:34.74#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.05:21:34.74#ibcon#[25=AT01-07\r\n] 2006.285.05:21:34.74#ibcon#*before write, iclass 18, count 2 2006.285.05:21:34.74#ibcon#enter sib2, iclass 18, count 2 2006.285.05:21:34.74#ibcon#flushed, iclass 18, count 2 2006.285.05:21:34.74#ibcon#about to write, iclass 18, count 2 2006.285.05:21:34.74#ibcon#wrote, iclass 18, count 2 2006.285.05:21:34.74#ibcon#about to read 3, iclass 18, count 2 2006.285.05:21:34.78#ibcon#read 3, iclass 18, count 2 2006.285.05:21:34.87#ibcon#about to read 4, iclass 18, count 2 2006.285.05:21:34.87#ibcon#read 4, iclass 18, count 2 2006.285.05:21:34.87#ibcon#about to read 5, iclass 18, count 2 2006.285.05:21:34.87#ibcon#read 5, iclass 18, count 2 2006.285.05:21:34.87#ibcon#about to read 6, iclass 18, count 2 2006.285.05:21:34.87#ibcon#read 6, iclass 18, count 2 2006.285.05:21:34.87#ibcon#end of sib2, iclass 18, count 2 2006.285.05:21:34.87#ibcon#*after write, iclass 18, count 2 2006.285.05:21:34.87#ibcon#*before return 0, iclass 18, count 2 2006.285.05:21:34.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:34.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:34.87#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.05:21:34.87#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:34.87#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.05:21:34.99#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.05:21:34.99#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.05:21:34.99#ibcon#enter wrdev, iclass 18, count 0 2006.285.05:21:34.99#ibcon#first serial, iclass 18, count 0 2006.285.05:21:34.99#ibcon#enter sib2, iclass 18, count 0 2006.285.05:21:34.99#ibcon#flushed, iclass 18, count 0 2006.285.05:21:34.99#ibcon#about to write, iclass 18, count 0 2006.285.05:21:34.99#ibcon#wrote, iclass 18, count 0 2006.285.05:21:34.99#ibcon#about to read 3, iclass 18, count 0 2006.285.05:21:35.01#ibcon#read 3, iclass 18, count 0 2006.285.05:21:35.01#ibcon#about to read 4, iclass 18, count 0 2006.285.05:21:35.01#ibcon#read 4, iclass 18, count 0 2006.285.05:21:35.01#ibcon#about to read 5, iclass 18, count 0 2006.285.05:21:35.01#ibcon#read 5, iclass 18, count 0 2006.285.05:21:35.01#ibcon#about to read 6, iclass 18, count 0 2006.285.05:21:35.01#ibcon#read 6, iclass 18, count 0 2006.285.05:21:35.01#ibcon#end of sib2, iclass 18, count 0 2006.285.05:21:35.01#ibcon#*mode == 0, iclass 18, count 0 2006.285.05:21:35.01#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.05:21:35.01#ibcon#[25=USB\r\n] 2006.285.05:21:35.01#ibcon#*before write, iclass 18, count 0 2006.285.05:21:35.01#ibcon#enter sib2, iclass 18, count 0 2006.285.05:21:35.01#ibcon#flushed, iclass 18, count 0 2006.285.05:21:35.01#ibcon#about to write, iclass 18, count 0 2006.285.05:21:35.01#ibcon#wrote, iclass 18, count 0 2006.285.05:21:35.01#ibcon#about to read 3, iclass 18, count 0 2006.285.05:21:35.04#ibcon#read 3, iclass 18, count 0 2006.285.05:21:35.04#ibcon#about to read 4, iclass 18, count 0 2006.285.05:21:35.04#ibcon#read 4, iclass 18, count 0 2006.285.05:21:35.04#ibcon#about to read 5, iclass 18, count 0 2006.285.05:21:35.04#ibcon#read 5, iclass 18, count 0 2006.285.05:21:35.04#ibcon#about to read 6, iclass 18, count 0 2006.285.05:21:35.04#ibcon#read 6, iclass 18, count 0 2006.285.05:21:35.04#ibcon#end of sib2, iclass 18, count 0 2006.285.05:21:35.04#ibcon#*after write, iclass 18, count 0 2006.285.05:21:35.04#ibcon#*before return 0, iclass 18, count 0 2006.285.05:21:35.04#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.05:21:35.04#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.05:21:35.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.05:21:35.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.05:21:35.04$vck44/valo=2,534.99 2006.285.05:21:35.04#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.05:21:35.04#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:35.04#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:35.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.05:21:35.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.05:21:35.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.05:21:35.04#ibcon#enter wrdev, iclass 20, count 0 2006.285.05:21:35.04#ibcon#first serial, iclass 20, count 0 2006.285.05:21:35.04#ibcon#enter sib2, iclass 20, count 0 2006.285.05:21:35.04#ibcon#flushed, iclass 20, count 0 2006.285.05:21:35.04#ibcon#about to write, iclass 20, count 0 2006.285.05:21:35.04#ibcon#wrote, iclass 20, count 0 2006.285.05:21:35.04#ibcon#about to read 3, iclass 20, count 0 2006.285.05:21:35.06#ibcon#read 3, iclass 20, count 0 2006.285.05:21:35.08#ibcon#about to read 4, iclass 20, count 0 2006.285.05:21:35.08#ibcon#read 4, iclass 20, count 0 2006.285.05:21:35.08#ibcon#about to read 5, iclass 20, count 0 2006.285.05:21:35.08#ibcon#read 5, iclass 20, count 0 2006.285.05:21:35.08#ibcon#about to read 6, iclass 20, count 0 2006.285.05:21:35.08#ibcon#read 6, iclass 20, count 0 2006.285.05:21:35.08#ibcon#end of sib2, iclass 20, count 0 2006.285.05:21:35.08#ibcon#*mode == 0, iclass 20, count 0 2006.285.05:21:35.08#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.05:21:35.08#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.05:21:35.08#ibcon#*before write, iclass 20, count 0 2006.285.05:21:35.08#ibcon#enter sib2, iclass 20, count 0 2006.285.05:21:35.08#ibcon#flushed, iclass 20, count 0 2006.285.05:21:35.08#ibcon#about to write, iclass 20, count 0 2006.285.05:21:35.08#ibcon#wrote, iclass 20, count 0 2006.285.05:21:35.08#ibcon#about to read 3, iclass 20, count 0 2006.285.05:21:35.12#ibcon#read 3, iclass 20, count 0 2006.285.05:21:35.20#ibcon#about to read 4, iclass 20, count 0 2006.285.05:21:35.20#ibcon#read 4, iclass 20, count 0 2006.285.05:21:35.20#ibcon#about to read 5, iclass 20, count 0 2006.285.05:21:35.20#ibcon#read 5, iclass 20, count 0 2006.285.05:21:35.20#ibcon#about to read 6, iclass 20, count 0 2006.285.05:21:35.20#ibcon#read 6, iclass 20, count 0 2006.285.05:21:35.20#ibcon#end of sib2, iclass 20, count 0 2006.285.05:21:35.20#ibcon#*after write, iclass 20, count 0 2006.285.05:21:35.20#ibcon#*before return 0, iclass 20, count 0 2006.285.05:21:35.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.05:21:35.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.05:21:35.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.05:21:35.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.05:21:35.20$vck44/va=2,6 2006.285.05:21:35.20#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.05:21:35.20#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.05:21:35.20#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:35.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:35.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:35.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:35.20#ibcon#enter wrdev, iclass 22, count 2 2006.285.05:21:35.20#ibcon#first serial, iclass 22, count 2 2006.285.05:21:35.20#ibcon#enter sib2, iclass 22, count 2 2006.285.05:21:35.20#ibcon#flushed, iclass 22, count 2 2006.285.05:21:35.20#ibcon#about to write, iclass 22, count 2 2006.285.05:21:35.20#ibcon#wrote, iclass 22, count 2 2006.285.05:21:35.20#ibcon#about to read 3, iclass 22, count 2 2006.285.05:21:35.21#ibcon#read 3, iclass 22, count 2 2006.285.05:21:35.32#ibcon#about to read 4, iclass 22, count 2 2006.285.05:21:35.32#ibcon#read 4, iclass 22, count 2 2006.285.05:21:35.32#ibcon#about to read 5, iclass 22, count 2 2006.285.05:21:35.32#ibcon#read 5, iclass 22, count 2 2006.285.05:21:35.32#ibcon#about to read 6, iclass 22, count 2 2006.285.05:21:35.32#ibcon#read 6, iclass 22, count 2 2006.285.05:21:35.32#ibcon#end of sib2, iclass 22, count 2 2006.285.05:21:35.32#ibcon#*mode == 0, iclass 22, count 2 2006.285.05:21:35.32#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.05:21:35.32#ibcon#[25=AT02-06\r\n] 2006.285.05:21:35.32#ibcon#*before write, iclass 22, count 2 2006.285.05:21:35.32#ibcon#enter sib2, iclass 22, count 2 2006.285.05:21:35.32#ibcon#flushed, iclass 22, count 2 2006.285.05:21:35.32#ibcon#about to write, iclass 22, count 2 2006.285.05:21:35.32#ibcon#wrote, iclass 22, count 2 2006.285.05:21:35.32#ibcon#about to read 3, iclass 22, count 2 2006.285.05:21:35.35#ibcon#read 3, iclass 22, count 2 2006.285.05:21:35.40#ibcon#about to read 4, iclass 22, count 2 2006.285.05:21:35.40#ibcon#read 4, iclass 22, count 2 2006.285.05:21:35.40#ibcon#about to read 5, iclass 22, count 2 2006.285.05:21:35.40#ibcon#read 5, iclass 22, count 2 2006.285.05:21:35.40#ibcon#about to read 6, iclass 22, count 2 2006.285.05:21:35.40#ibcon#read 6, iclass 22, count 2 2006.285.05:21:35.40#ibcon#end of sib2, iclass 22, count 2 2006.285.05:21:35.40#ibcon#*after write, iclass 22, count 2 2006.285.05:21:35.40#ibcon#*before return 0, iclass 22, count 2 2006.285.05:21:35.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:35.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:35.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.05:21:35.40#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:35.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.05:21:35.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.05:21:35.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.05:21:35.51#ibcon#enter wrdev, iclass 22, count 0 2006.285.05:21:35.51#ibcon#first serial, iclass 22, count 0 2006.285.05:21:35.51#ibcon#enter sib2, iclass 22, count 0 2006.285.05:21:35.51#ibcon#flushed, iclass 22, count 0 2006.285.05:21:35.51#ibcon#about to write, iclass 22, count 0 2006.285.05:21:35.51#ibcon#wrote, iclass 22, count 0 2006.285.05:21:35.51#ibcon#about to read 3, iclass 22, count 0 2006.285.05:21:35.53#ibcon#read 3, iclass 22, count 0 2006.285.05:21:35.53#ibcon#about to read 4, iclass 22, count 0 2006.285.05:21:35.53#ibcon#read 4, iclass 22, count 0 2006.285.05:21:35.53#ibcon#about to read 5, iclass 22, count 0 2006.285.05:21:35.53#ibcon#read 5, iclass 22, count 0 2006.285.05:21:35.53#ibcon#about to read 6, iclass 22, count 0 2006.285.05:21:35.53#ibcon#read 6, iclass 22, count 0 2006.285.05:21:35.53#ibcon#end of sib2, iclass 22, count 0 2006.285.05:21:35.53#ibcon#*mode == 0, iclass 22, count 0 2006.285.05:21:35.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.05:21:35.53#ibcon#[25=USB\r\n] 2006.285.05:21:35.53#ibcon#*before write, iclass 22, count 0 2006.285.05:21:35.53#ibcon#enter sib2, iclass 22, count 0 2006.285.05:21:35.53#ibcon#flushed, iclass 22, count 0 2006.285.05:21:35.53#ibcon#about to write, iclass 22, count 0 2006.285.05:21:35.53#ibcon#wrote, iclass 22, count 0 2006.285.05:21:35.53#ibcon#about to read 3, iclass 22, count 0 2006.285.05:21:35.56#ibcon#read 3, iclass 22, count 0 2006.285.05:21:35.56#ibcon#about to read 4, iclass 22, count 0 2006.285.05:21:35.56#ibcon#read 4, iclass 22, count 0 2006.285.05:21:35.56#ibcon#about to read 5, iclass 22, count 0 2006.285.05:21:35.56#ibcon#read 5, iclass 22, count 0 2006.285.05:21:35.56#ibcon#about to read 6, iclass 22, count 0 2006.285.05:21:35.56#ibcon#read 6, iclass 22, count 0 2006.285.05:21:35.56#ibcon#end of sib2, iclass 22, count 0 2006.285.05:21:35.56#ibcon#*after write, iclass 22, count 0 2006.285.05:21:35.56#ibcon#*before return 0, iclass 22, count 0 2006.285.05:21:35.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.05:21:35.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.05:21:35.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.05:21:35.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.05:21:35.56$vck44/valo=3,564.99 2006.285.05:21:35.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.05:21:35.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:35.56#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:35.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.05:21:35.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.05:21:35.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.05:21:35.56#ibcon#enter wrdev, iclass 24, count 0 2006.285.05:21:35.56#ibcon#first serial, iclass 24, count 0 2006.285.05:21:35.56#ibcon#enter sib2, iclass 24, count 0 2006.285.05:21:35.56#ibcon#flushed, iclass 24, count 0 2006.285.05:21:35.66#ibcon#about to write, iclass 24, count 0 2006.285.05:21:35.66#ibcon#wrote, iclass 24, count 0 2006.285.05:21:35.66#ibcon#about to read 3, iclass 24, count 0 2006.285.05:21:35.67#ibcon#read 3, iclass 24, count 0 2006.285.05:21:35.73#ibcon#about to read 4, iclass 24, count 0 2006.285.05:21:35.73#ibcon#read 4, iclass 24, count 0 2006.285.05:21:35.73#ibcon#about to read 5, iclass 24, count 0 2006.285.05:21:35.73#ibcon#read 5, iclass 24, count 0 2006.285.05:21:35.73#ibcon#about to read 6, iclass 24, count 0 2006.285.05:21:35.73#ibcon#read 6, iclass 24, count 0 2006.285.05:21:35.73#ibcon#end of sib2, iclass 24, count 0 2006.285.05:21:35.73#ibcon#*mode == 0, iclass 24, count 0 2006.285.05:21:35.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.05:21:35.73#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.05:21:35.73#ibcon#*before write, iclass 24, count 0 2006.285.05:21:35.73#ibcon#enter sib2, iclass 24, count 0 2006.285.05:21:35.73#ibcon#flushed, iclass 24, count 0 2006.285.05:21:35.73#ibcon#about to write, iclass 24, count 0 2006.285.05:21:35.73#ibcon#wrote, iclass 24, count 0 2006.285.05:21:35.73#ibcon#about to read 3, iclass 24, count 0 2006.285.05:21:35.77#ibcon#read 3, iclass 24, count 0 2006.285.05:21:35.79#ibcon#about to read 4, iclass 24, count 0 2006.285.05:21:35.79#ibcon#read 4, iclass 24, count 0 2006.285.05:21:35.79#ibcon#about to read 5, iclass 24, count 0 2006.285.05:21:35.79#ibcon#read 5, iclass 24, count 0 2006.285.05:21:35.79#ibcon#about to read 6, iclass 24, count 0 2006.285.05:21:35.79#ibcon#read 6, iclass 24, count 0 2006.285.05:21:35.79#ibcon#end of sib2, iclass 24, count 0 2006.285.05:21:35.79#ibcon#*after write, iclass 24, count 0 2006.285.05:21:35.79#ibcon#*before return 0, iclass 24, count 0 2006.285.05:21:35.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.05:21:35.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.05:21:35.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.05:21:35.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.05:21:35.79$vck44/va=3,7 2006.285.05:21:35.79#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.05:21:35.79#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.05:21:35.79#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:35.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:35.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:35.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:35.79#ibcon#enter wrdev, iclass 26, count 2 2006.285.05:21:35.79#ibcon#first serial, iclass 26, count 2 2006.285.05:21:35.79#ibcon#enter sib2, iclass 26, count 2 2006.285.05:21:35.79#ibcon#flushed, iclass 26, count 2 2006.285.05:21:35.79#ibcon#about to write, iclass 26, count 2 2006.285.05:21:35.79#ibcon#wrote, iclass 26, count 2 2006.285.05:21:35.79#ibcon#about to read 3, iclass 26, count 2 2006.285.05:21:35.80#ibcon#read 3, iclass 26, count 2 2006.285.05:21:35.80#ibcon#about to read 4, iclass 26, count 2 2006.285.05:21:35.80#ibcon#read 4, iclass 26, count 2 2006.285.05:21:35.80#ibcon#about to read 5, iclass 26, count 2 2006.285.05:21:35.80#ibcon#read 5, iclass 26, count 2 2006.285.05:21:35.80#ibcon#about to read 6, iclass 26, count 2 2006.285.05:21:35.80#ibcon#read 6, iclass 26, count 2 2006.285.05:21:35.80#ibcon#end of sib2, iclass 26, count 2 2006.285.05:21:35.80#ibcon#*mode == 0, iclass 26, count 2 2006.285.05:21:35.80#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.05:21:35.80#ibcon#[25=AT03-07\r\n] 2006.285.05:21:35.80#ibcon#*before write, iclass 26, count 2 2006.285.05:21:35.80#ibcon#enter sib2, iclass 26, count 2 2006.285.05:21:35.80#ibcon#flushed, iclass 26, count 2 2006.285.05:21:35.80#ibcon#about to write, iclass 26, count 2 2006.285.05:21:35.80#ibcon#wrote, iclass 26, count 2 2006.285.05:21:35.80#ibcon#about to read 3, iclass 26, count 2 2006.285.05:21:35.83#ibcon#read 3, iclass 26, count 2 2006.285.05:21:35.89#ibcon#about to read 4, iclass 26, count 2 2006.285.05:21:35.89#ibcon#read 4, iclass 26, count 2 2006.285.05:21:35.89#ibcon#about to read 5, iclass 26, count 2 2006.285.05:21:35.89#ibcon#read 5, iclass 26, count 2 2006.285.05:21:35.89#ibcon#about to read 6, iclass 26, count 2 2006.285.05:21:35.89#ibcon#read 6, iclass 26, count 2 2006.285.05:21:35.89#ibcon#end of sib2, iclass 26, count 2 2006.285.05:21:35.89#ibcon#*after write, iclass 26, count 2 2006.285.05:21:35.89#ibcon#*before return 0, iclass 26, count 2 2006.285.05:21:35.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:35.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:35.89#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.05:21:35.89#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:35.89#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.05:21:36.00#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.05:21:36.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.05:21:36.00#ibcon#enter wrdev, iclass 26, count 0 2006.285.05:21:36.00#ibcon#first serial, iclass 26, count 0 2006.285.05:21:36.00#ibcon#enter sib2, iclass 26, count 0 2006.285.05:21:36.00#ibcon#flushed, iclass 26, count 0 2006.285.05:21:36.00#ibcon#about to write, iclass 26, count 0 2006.285.05:21:36.00#ibcon#wrote, iclass 26, count 0 2006.285.05:21:36.00#ibcon#about to read 3, iclass 26, count 0 2006.285.05:21:36.02#ibcon#read 3, iclass 26, count 0 2006.285.05:21:36.02#ibcon#about to read 4, iclass 26, count 0 2006.285.05:21:36.02#ibcon#read 4, iclass 26, count 0 2006.285.05:21:36.02#ibcon#about to read 5, iclass 26, count 0 2006.285.05:21:36.02#ibcon#read 5, iclass 26, count 0 2006.285.05:21:36.02#ibcon#about to read 6, iclass 26, count 0 2006.285.05:21:36.02#ibcon#read 6, iclass 26, count 0 2006.285.05:21:36.02#ibcon#end of sib2, iclass 26, count 0 2006.285.05:21:36.02#ibcon#*mode == 0, iclass 26, count 0 2006.285.05:21:36.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.05:21:36.02#ibcon#[25=USB\r\n] 2006.285.05:21:36.02#ibcon#*before write, iclass 26, count 0 2006.285.05:21:36.02#ibcon#enter sib2, iclass 26, count 0 2006.285.05:21:36.02#ibcon#flushed, iclass 26, count 0 2006.285.05:21:36.02#ibcon#about to write, iclass 26, count 0 2006.285.05:21:36.02#ibcon#wrote, iclass 26, count 0 2006.285.05:21:36.02#ibcon#about to read 3, iclass 26, count 0 2006.285.05:21:36.05#ibcon#read 3, iclass 26, count 0 2006.285.05:21:36.05#ibcon#about to read 4, iclass 26, count 0 2006.285.05:21:36.05#ibcon#read 4, iclass 26, count 0 2006.285.05:21:36.05#ibcon#about to read 5, iclass 26, count 0 2006.285.05:21:36.05#ibcon#read 5, iclass 26, count 0 2006.285.05:21:36.05#ibcon#about to read 6, iclass 26, count 0 2006.285.05:21:36.05#ibcon#read 6, iclass 26, count 0 2006.285.05:21:36.05#ibcon#end of sib2, iclass 26, count 0 2006.285.05:21:36.05#ibcon#*after write, iclass 26, count 0 2006.285.05:21:36.05#ibcon#*before return 0, iclass 26, count 0 2006.285.05:21:36.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.05:21:36.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.05:21:36.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.05:21:36.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.05:21:36.05$vck44/valo=4,624.99 2006.285.05:21:36.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.05:21:36.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:36.05#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:36.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.05:21:36.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.05:21:36.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.05:21:36.05#ibcon#enter wrdev, iclass 28, count 0 2006.285.05:21:36.05#ibcon#first serial, iclass 28, count 0 2006.285.05:21:36.05#ibcon#enter sib2, iclass 28, count 0 2006.285.05:21:36.05#ibcon#flushed, iclass 28, count 0 2006.285.05:21:36.05#ibcon#about to write, iclass 28, count 0 2006.285.05:21:36.12#ibcon#wrote, iclass 28, count 0 2006.285.05:21:36.12#ibcon#about to read 3, iclass 28, count 0 2006.285.05:21:36.13#ibcon#read 3, iclass 28, count 0 2006.285.05:21:36.19#ibcon#about to read 4, iclass 28, count 0 2006.285.05:21:36.19#ibcon#read 4, iclass 28, count 0 2006.285.05:21:36.19#ibcon#about to read 5, iclass 28, count 0 2006.285.05:21:36.19#ibcon#read 5, iclass 28, count 0 2006.285.05:21:36.19#ibcon#about to read 6, iclass 28, count 0 2006.285.05:21:36.19#ibcon#read 6, iclass 28, count 0 2006.285.05:21:36.19#ibcon#end of sib2, iclass 28, count 0 2006.285.05:21:36.19#ibcon#*mode == 0, iclass 28, count 0 2006.285.05:21:36.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.05:21:36.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.05:21:36.19#ibcon#*before write, iclass 28, count 0 2006.285.05:21:36.19#ibcon#enter sib2, iclass 28, count 0 2006.285.05:21:36.19#ibcon#flushed, iclass 28, count 0 2006.285.05:21:36.19#ibcon#about to write, iclass 28, count 0 2006.285.05:21:36.19#ibcon#wrote, iclass 28, count 0 2006.285.05:21:36.19#ibcon#about to read 3, iclass 28, count 0 2006.285.05:21:36.23#ibcon#read 3, iclass 28, count 0 2006.285.05:21:36.23#ibcon#about to read 4, iclass 28, count 0 2006.285.05:21:36.23#ibcon#read 4, iclass 28, count 0 2006.285.05:21:36.23#ibcon#about to read 5, iclass 28, count 0 2006.285.05:21:36.23#ibcon#read 5, iclass 28, count 0 2006.285.05:21:36.23#ibcon#about to read 6, iclass 28, count 0 2006.285.05:21:36.23#ibcon#read 6, iclass 28, count 0 2006.285.05:21:36.23#ibcon#end of sib2, iclass 28, count 0 2006.285.05:21:36.23#ibcon#*after write, iclass 28, count 0 2006.285.05:21:36.23#ibcon#*before return 0, iclass 28, count 0 2006.285.05:21:36.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.05:21:36.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.05:21:36.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.05:21:36.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.05:21:36.23$vck44/va=4,6 2006.285.05:21:36.23#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.05:21:36.23#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.05:21:36.23#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:36.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:36.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:36.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:36.23#ibcon#enter wrdev, iclass 30, count 2 2006.285.05:21:36.23#ibcon#first serial, iclass 30, count 2 2006.285.05:21:36.23#ibcon#enter sib2, iclass 30, count 2 2006.285.05:21:36.23#ibcon#flushed, iclass 30, count 2 2006.285.05:21:36.23#ibcon#about to write, iclass 30, count 2 2006.285.05:21:36.23#ibcon#wrote, iclass 30, count 2 2006.285.05:21:36.23#ibcon#about to read 3, iclass 30, count 2 2006.285.05:21:36.25#ibcon#read 3, iclass 30, count 2 2006.285.05:21:36.25#ibcon#about to read 4, iclass 30, count 2 2006.285.05:21:36.25#ibcon#read 4, iclass 30, count 2 2006.285.05:21:36.25#ibcon#about to read 5, iclass 30, count 2 2006.285.05:21:36.33#ibcon#read 5, iclass 30, count 2 2006.285.05:21:36.33#ibcon#about to read 6, iclass 30, count 2 2006.285.05:21:36.33#ibcon#read 6, iclass 30, count 2 2006.285.05:21:36.33#ibcon#end of sib2, iclass 30, count 2 2006.285.05:21:36.33#ibcon#*mode == 0, iclass 30, count 2 2006.285.05:21:36.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.05:21:36.33#ibcon#[25=AT04-06\r\n] 2006.285.05:21:36.33#ibcon#*before write, iclass 30, count 2 2006.285.05:21:36.33#ibcon#enter sib2, iclass 30, count 2 2006.285.05:21:36.33#ibcon#flushed, iclass 30, count 2 2006.285.05:21:36.33#ibcon#about to write, iclass 30, count 2 2006.285.05:21:36.33#ibcon#wrote, iclass 30, count 2 2006.285.05:21:36.33#ibcon#about to read 3, iclass 30, count 2 2006.285.05:21:36.36#ibcon#read 3, iclass 30, count 2 2006.285.05:21:36.36#ibcon#about to read 4, iclass 30, count 2 2006.285.05:21:36.36#ibcon#read 4, iclass 30, count 2 2006.285.05:21:36.36#ibcon#about to read 5, iclass 30, count 2 2006.285.05:21:36.36#ibcon#read 5, iclass 30, count 2 2006.285.05:21:36.36#ibcon#about to read 6, iclass 30, count 2 2006.285.05:21:36.36#ibcon#read 6, iclass 30, count 2 2006.285.05:21:36.36#ibcon#end of sib2, iclass 30, count 2 2006.285.05:21:36.36#ibcon#*after write, iclass 30, count 2 2006.285.05:21:36.36#ibcon#*before return 0, iclass 30, count 2 2006.285.05:21:36.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:36.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:36.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.05:21:36.36#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:36.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.05:21:36.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.05:21:36.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.05:21:36.48#ibcon#enter wrdev, iclass 30, count 0 2006.285.05:21:36.48#ibcon#first serial, iclass 30, count 0 2006.285.05:21:36.48#ibcon#enter sib2, iclass 30, count 0 2006.285.05:21:36.48#ibcon#flushed, iclass 30, count 0 2006.285.05:21:36.48#ibcon#about to write, iclass 30, count 0 2006.285.05:21:36.48#ibcon#wrote, iclass 30, count 0 2006.285.05:21:36.48#ibcon#about to read 3, iclass 30, count 0 2006.285.05:21:36.52#ibcon#read 3, iclass 30, count 0 2006.285.05:21:36.52#ibcon#about to read 4, iclass 30, count 0 2006.285.05:21:36.52#ibcon#read 4, iclass 30, count 0 2006.285.05:21:36.52#ibcon#about to read 5, iclass 30, count 0 2006.285.05:21:36.52#ibcon#read 5, iclass 30, count 0 2006.285.05:21:36.52#ibcon#about to read 6, iclass 30, count 0 2006.285.05:21:36.52#ibcon#read 6, iclass 30, count 0 2006.285.05:21:36.52#ibcon#end of sib2, iclass 30, count 0 2006.285.05:21:36.52#ibcon#*mode == 0, iclass 30, count 0 2006.285.05:21:36.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.05:21:36.52#ibcon#[25=USB\r\n] 2006.285.05:21:36.52#ibcon#*before write, iclass 30, count 0 2006.285.05:21:36.52#ibcon#enter sib2, iclass 30, count 0 2006.285.05:21:36.52#ibcon#flushed, iclass 30, count 0 2006.285.05:21:36.52#ibcon#about to write, iclass 30, count 0 2006.285.05:21:36.52#ibcon#wrote, iclass 30, count 0 2006.285.05:21:36.52#ibcon#about to read 3, iclass 30, count 0 2006.285.05:21:36.55#ibcon#read 3, iclass 30, count 0 2006.285.05:21:36.55#ibcon#about to read 4, iclass 30, count 0 2006.285.05:21:36.55#ibcon#read 4, iclass 30, count 0 2006.285.05:21:36.55#ibcon#about to read 5, iclass 30, count 0 2006.285.05:21:36.55#ibcon#read 5, iclass 30, count 0 2006.285.05:21:36.55#ibcon#about to read 6, iclass 30, count 0 2006.285.05:21:36.55#ibcon#read 6, iclass 30, count 0 2006.285.05:21:36.55#ibcon#end of sib2, iclass 30, count 0 2006.285.05:21:36.55#ibcon#*after write, iclass 30, count 0 2006.285.05:21:36.55#ibcon#*before return 0, iclass 30, count 0 2006.285.05:21:36.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.05:21:36.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.05:21:36.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.05:21:36.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.05:21:36.55$vck44/valo=5,734.99 2006.285.05:21:36.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.05:21:36.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:36.55#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:36.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.05:21:36.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.05:21:36.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.05:21:36.55#ibcon#enter wrdev, iclass 32, count 0 2006.285.05:21:36.55#ibcon#first serial, iclass 32, count 0 2006.285.05:21:36.55#ibcon#enter sib2, iclass 32, count 0 2006.285.05:21:36.55#ibcon#flushed, iclass 32, count 0 2006.285.05:21:36.55#ibcon#about to write, iclass 32, count 0 2006.285.05:21:36.55#ibcon#wrote, iclass 32, count 0 2006.285.05:21:36.55#ibcon#about to read 3, iclass 32, count 0 2006.285.05:21:36.57#ibcon#read 3, iclass 32, count 0 2006.285.05:21:36.64#ibcon#about to read 4, iclass 32, count 0 2006.285.05:21:36.64#ibcon#read 4, iclass 32, count 0 2006.285.05:21:36.64#ibcon#about to read 5, iclass 32, count 0 2006.285.05:21:36.64#ibcon#read 5, iclass 32, count 0 2006.285.05:21:36.64#ibcon#about to read 6, iclass 32, count 0 2006.285.05:21:36.64#ibcon#read 6, iclass 32, count 0 2006.285.05:21:36.64#ibcon#end of sib2, iclass 32, count 0 2006.285.05:21:36.64#ibcon#*mode == 0, iclass 32, count 0 2006.285.05:21:36.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.05:21:36.64#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.05:21:36.64#ibcon#*before write, iclass 32, count 0 2006.285.05:21:36.64#ibcon#enter sib2, iclass 32, count 0 2006.285.05:21:36.64#ibcon#flushed, iclass 32, count 0 2006.285.05:21:36.64#ibcon#about to write, iclass 32, count 0 2006.285.05:21:36.64#ibcon#wrote, iclass 32, count 0 2006.285.05:21:36.64#ibcon#about to read 3, iclass 32, count 0 2006.285.05:21:36.67#ibcon#read 3, iclass 32, count 0 2006.285.05:21:36.67#ibcon#about to read 4, iclass 32, count 0 2006.285.05:21:36.79#ibcon#read 4, iclass 32, count 0 2006.285.05:21:36.79#ibcon#about to read 5, iclass 32, count 0 2006.285.05:21:36.79#ibcon#read 5, iclass 32, count 0 2006.285.05:21:36.79#ibcon#about to read 6, iclass 32, count 0 2006.285.05:21:36.79#ibcon#read 6, iclass 32, count 0 2006.285.05:21:36.79#ibcon#end of sib2, iclass 32, count 0 2006.285.05:21:36.79#ibcon#*after write, iclass 32, count 0 2006.285.05:21:36.79#ibcon#*before return 0, iclass 32, count 0 2006.285.05:21:36.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.05:21:36.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.05:21:36.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.05:21:36.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.05:21:36.79$vck44/va=5,3 2006.285.05:21:36.79#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.05:21:36.79#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.05:21:36.79#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:36.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:36.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:36.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:36.79#ibcon#enter wrdev, iclass 34, count 2 2006.285.05:21:36.79#ibcon#first serial, iclass 34, count 2 2006.285.05:21:36.79#ibcon#enter sib2, iclass 34, count 2 2006.285.05:21:36.79#ibcon#flushed, iclass 34, count 2 2006.285.05:21:36.79#ibcon#about to write, iclass 34, count 2 2006.285.05:21:36.79#ibcon#wrote, iclass 34, count 2 2006.285.05:21:36.79#ibcon#about to read 3, iclass 34, count 2 2006.285.05:21:36.81#ibcon#read 3, iclass 34, count 2 2006.285.05:21:36.82#ibcon#about to read 4, iclass 34, count 2 2006.285.05:21:36.82#ibcon#read 4, iclass 34, count 2 2006.285.05:21:36.82#ibcon#about to read 5, iclass 34, count 2 2006.285.05:21:36.82#ibcon#read 5, iclass 34, count 2 2006.285.05:21:36.82#ibcon#about to read 6, iclass 34, count 2 2006.285.05:21:36.82#ibcon#read 6, iclass 34, count 2 2006.285.05:21:36.82#ibcon#end of sib2, iclass 34, count 2 2006.285.05:21:36.82#ibcon#*mode == 0, iclass 34, count 2 2006.285.05:21:36.83#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.05:21:36.83#ibcon#[25=AT05-03\r\n] 2006.285.05:21:36.83#ibcon#*before write, iclass 34, count 2 2006.285.05:21:36.83#ibcon#enter sib2, iclass 34, count 2 2006.285.05:21:36.83#ibcon#flushed, iclass 34, count 2 2006.285.05:21:36.83#ibcon#about to write, iclass 34, count 2 2006.285.05:21:36.83#ibcon#wrote, iclass 34, count 2 2006.285.05:21:36.83#ibcon#about to read 3, iclass 34, count 2 2006.285.05:21:36.85#ibcon#read 3, iclass 34, count 2 2006.285.05:21:36.87#ibcon#about to read 4, iclass 34, count 2 2006.285.05:21:36.87#ibcon#read 4, iclass 34, count 2 2006.285.05:21:36.87#ibcon#about to read 5, iclass 34, count 2 2006.285.05:21:36.87#ibcon#read 5, iclass 34, count 2 2006.285.05:21:36.87#ibcon#about to read 6, iclass 34, count 2 2006.285.05:21:36.87#ibcon#read 6, iclass 34, count 2 2006.285.05:21:36.87#ibcon#end of sib2, iclass 34, count 2 2006.285.05:21:36.87#ibcon#*after write, iclass 34, count 2 2006.285.05:21:36.87#ibcon#*before return 0, iclass 34, count 2 2006.285.05:21:36.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:36.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:36.87#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.05:21:36.87#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:36.87#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.05:21:37.01#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.05:21:37.01#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.05:21:37.01#ibcon#enter wrdev, iclass 34, count 0 2006.285.05:21:37.01#ibcon#first serial, iclass 34, count 0 2006.285.05:21:37.01#ibcon#enter sib2, iclass 34, count 0 2006.285.05:21:37.01#ibcon#flushed, iclass 34, count 0 2006.285.05:21:37.01#ibcon#about to write, iclass 34, count 0 2006.285.05:21:37.01#ibcon#wrote, iclass 34, count 0 2006.285.05:21:37.01#ibcon#about to read 3, iclass 34, count 0 2006.285.05:21:37.02#ibcon#read 3, iclass 34, count 0 2006.285.05:21:37.02#ibcon#about to read 4, iclass 34, count 0 2006.285.05:21:37.02#ibcon#read 4, iclass 34, count 0 2006.285.05:21:37.02#ibcon#about to read 5, iclass 34, count 0 2006.285.05:21:37.02#ibcon#read 5, iclass 34, count 0 2006.285.05:21:37.02#ibcon#about to read 6, iclass 34, count 0 2006.285.05:21:37.02#ibcon#read 6, iclass 34, count 0 2006.285.05:21:37.02#ibcon#end of sib2, iclass 34, count 0 2006.285.05:21:37.02#ibcon#*mode == 0, iclass 34, count 0 2006.285.05:21:37.02#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.05:21:37.02#ibcon#[25=USB\r\n] 2006.285.05:21:37.02#ibcon#*before write, iclass 34, count 0 2006.285.05:21:37.02#ibcon#enter sib2, iclass 34, count 0 2006.285.05:21:37.02#ibcon#flushed, iclass 34, count 0 2006.285.05:21:37.02#ibcon#about to write, iclass 34, count 0 2006.285.05:21:37.02#ibcon#wrote, iclass 34, count 0 2006.285.05:21:37.02#ibcon#about to read 3, iclass 34, count 0 2006.285.05:21:37.05#ibcon#read 3, iclass 34, count 0 2006.285.05:21:37.05#ibcon#about to read 4, iclass 34, count 0 2006.285.05:21:37.05#ibcon#read 4, iclass 34, count 0 2006.285.05:21:37.05#ibcon#about to read 5, iclass 34, count 0 2006.285.05:21:37.05#ibcon#read 5, iclass 34, count 0 2006.285.05:21:37.05#ibcon#about to read 6, iclass 34, count 0 2006.285.05:21:37.05#ibcon#read 6, iclass 34, count 0 2006.285.05:21:37.05#ibcon#end of sib2, iclass 34, count 0 2006.285.05:21:37.05#ibcon#*after write, iclass 34, count 0 2006.285.05:21:37.05#ibcon#*before return 0, iclass 34, count 0 2006.285.05:21:37.05#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.05:21:37.05#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.05:21:37.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.05:21:37.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.05:21:37.05$vck44/valo=6,814.99 2006.285.05:21:37.05#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.05:21:37.05#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:37.05#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:37.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.05:21:37.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.05:21:37.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.05:21:37.05#ibcon#enter wrdev, iclass 36, count 0 2006.285.05:21:37.05#ibcon#first serial, iclass 36, count 0 2006.285.05:21:37.05#ibcon#enter sib2, iclass 36, count 0 2006.285.05:21:37.05#ibcon#flushed, iclass 36, count 0 2006.285.05:21:37.05#ibcon#about to write, iclass 36, count 0 2006.285.05:21:37.05#ibcon#wrote, iclass 36, count 0 2006.285.05:21:37.05#ibcon#about to read 3, iclass 36, count 0 2006.285.05:21:37.07#ibcon#read 3, iclass 36, count 0 2006.285.05:21:37.07#ibcon#about to read 4, iclass 36, count 0 2006.285.05:21:37.07#ibcon#read 4, iclass 36, count 0 2006.285.05:21:37.07#ibcon#about to read 5, iclass 36, count 0 2006.285.05:21:37.07#ibcon#read 5, iclass 36, count 0 2006.285.05:21:37.07#ibcon#about to read 6, iclass 36, count 0 2006.285.05:21:37.07#ibcon#read 6, iclass 36, count 0 2006.285.05:21:37.07#ibcon#end of sib2, iclass 36, count 0 2006.285.05:21:37.07#ibcon#*mode == 0, iclass 36, count 0 2006.285.05:21:37.07#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.05:21:37.07#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.05:21:37.07#ibcon#*before write, iclass 36, count 0 2006.285.05:21:37.07#ibcon#enter sib2, iclass 36, count 0 2006.285.05:21:37.07#ibcon#flushed, iclass 36, count 0 2006.285.05:21:37.07#ibcon#about to write, iclass 36, count 0 2006.285.05:21:37.07#ibcon#wrote, iclass 36, count 0 2006.285.05:21:37.07#ibcon#about to read 3, iclass 36, count 0 2006.285.05:21:37.11#ibcon#read 3, iclass 36, count 0 2006.285.05:21:37.11#ibcon#about to read 4, iclass 36, count 0 2006.285.05:21:37.11#ibcon#read 4, iclass 36, count 0 2006.285.05:21:37.11#ibcon#about to read 5, iclass 36, count 0 2006.285.05:21:37.11#ibcon#read 5, iclass 36, count 0 2006.285.05:21:37.11#ibcon#about to read 6, iclass 36, count 0 2006.285.05:21:37.11#ibcon#read 6, iclass 36, count 0 2006.285.05:21:37.11#ibcon#end of sib2, iclass 36, count 0 2006.285.05:21:37.11#ibcon#*after write, iclass 36, count 0 2006.285.05:21:37.11#ibcon#*before return 0, iclass 36, count 0 2006.285.05:21:37.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.05:21:37.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.05:21:37.11#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.05:21:37.11#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.05:21:37.11$vck44/va=6,4 2006.285.05:21:37.11#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.05:21:37.11#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.05:21:37.11#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:37.11#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:37.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:37.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:37.17#ibcon#enter wrdev, iclass 38, count 2 2006.285.05:21:37.17#ibcon#first serial, iclass 38, count 2 2006.285.05:21:37.17#ibcon#enter sib2, iclass 38, count 2 2006.285.05:21:37.17#ibcon#flushed, iclass 38, count 2 2006.285.05:21:37.17#ibcon#about to write, iclass 38, count 2 2006.285.05:21:37.17#ibcon#wrote, iclass 38, count 2 2006.285.05:21:37.17#ibcon#about to read 3, iclass 38, count 2 2006.285.05:21:37.19#ibcon#read 3, iclass 38, count 2 2006.285.05:21:37.19#ibcon#about to read 4, iclass 38, count 2 2006.285.05:21:37.19#ibcon#read 4, iclass 38, count 2 2006.285.05:21:37.19#ibcon#about to read 5, iclass 38, count 2 2006.285.05:21:37.19#ibcon#read 5, iclass 38, count 2 2006.285.05:21:37.19#ibcon#about to read 6, iclass 38, count 2 2006.285.05:21:37.19#ibcon#read 6, iclass 38, count 2 2006.285.05:21:37.19#ibcon#end of sib2, iclass 38, count 2 2006.285.05:21:37.19#ibcon#*mode == 0, iclass 38, count 2 2006.285.05:21:37.19#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.05:21:37.19#ibcon#[25=AT06-04\r\n] 2006.285.05:21:37.19#ibcon#*before write, iclass 38, count 2 2006.285.05:21:37.19#ibcon#enter sib2, iclass 38, count 2 2006.285.05:21:37.19#ibcon#flushed, iclass 38, count 2 2006.285.05:21:37.19#ibcon#about to write, iclass 38, count 2 2006.285.05:21:37.19#ibcon#wrote, iclass 38, count 2 2006.285.05:21:37.19#ibcon#about to read 3, iclass 38, count 2 2006.285.05:21:37.22#ibcon#read 3, iclass 38, count 2 2006.285.05:21:37.26#ibcon#about to read 4, iclass 38, count 2 2006.285.05:21:37.26#ibcon#read 4, iclass 38, count 2 2006.285.05:21:37.26#ibcon#about to read 5, iclass 38, count 2 2006.285.05:21:37.26#ibcon#read 5, iclass 38, count 2 2006.285.05:21:37.26#ibcon#about to read 6, iclass 38, count 2 2006.285.05:21:37.26#ibcon#read 6, iclass 38, count 2 2006.285.05:21:37.26#ibcon#end of sib2, iclass 38, count 2 2006.285.05:21:37.26#ibcon#*after write, iclass 38, count 2 2006.285.05:21:37.26#ibcon#*before return 0, iclass 38, count 2 2006.285.05:21:37.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:37.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:37.26#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.05:21:37.26#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:37.26#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.05:21:37.38#abcon#<5=/05 4.5 7.1 25.62 541013.8\r\n> 2006.285.05:21:37.38#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.05:21:37.38#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.05:21:37.38#ibcon#enter wrdev, iclass 38, count 0 2006.285.05:21:37.38#ibcon#first serial, iclass 38, count 0 2006.285.05:21:37.38#ibcon#enter sib2, iclass 38, count 0 2006.285.05:21:37.38#ibcon#flushed, iclass 38, count 0 2006.285.05:21:37.38#ibcon#about to write, iclass 38, count 0 2006.285.05:21:37.38#ibcon#wrote, iclass 38, count 0 2006.285.05:21:37.38#ibcon#about to read 3, iclass 38, count 0 2006.285.05:21:37.40#ibcon#read 3, iclass 38, count 0 2006.285.05:21:37.40#ibcon#about to read 4, iclass 38, count 0 2006.285.05:21:37.40#ibcon#read 4, iclass 38, count 0 2006.285.05:21:37.40#ibcon#about to read 5, iclass 38, count 0 2006.285.05:21:37.40#ibcon#read 5, iclass 38, count 0 2006.285.05:21:37.40#ibcon#about to read 6, iclass 38, count 0 2006.285.05:21:37.40#ibcon#read 6, iclass 38, count 0 2006.285.05:21:37.40#ibcon#end of sib2, iclass 38, count 0 2006.285.05:21:37.40#ibcon#*mode == 0, iclass 38, count 0 2006.285.05:21:37.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.05:21:37.40#ibcon#[25=USB\r\n] 2006.285.05:21:37.40#ibcon#*before write, iclass 38, count 0 2006.285.05:21:37.40#ibcon#enter sib2, iclass 38, count 0 2006.285.05:21:37.40#ibcon#flushed, iclass 38, count 0 2006.285.05:21:37.40#ibcon#about to write, iclass 38, count 0 2006.285.05:21:37.40#ibcon#wrote, iclass 38, count 0 2006.285.05:21:37.40#ibcon#about to read 3, iclass 38, count 0 2006.285.05:21:37.40#abcon#{5=INTERFACE CLEAR} 2006.285.05:21:37.43#ibcon#read 3, iclass 38, count 0 2006.285.05:21:37.43#ibcon#about to read 4, iclass 38, count 0 2006.285.05:21:37.43#ibcon#read 4, iclass 38, count 0 2006.285.05:21:37.43#ibcon#about to read 5, iclass 38, count 0 2006.285.05:21:37.43#ibcon#read 5, iclass 38, count 0 2006.285.05:21:37.43#ibcon#about to read 6, iclass 38, count 0 2006.285.05:21:37.43#ibcon#read 6, iclass 38, count 0 2006.285.05:21:37.43#ibcon#end of sib2, iclass 38, count 0 2006.285.05:21:37.43#ibcon#*after write, iclass 38, count 0 2006.285.05:21:37.43#ibcon#*before return 0, iclass 38, count 0 2006.285.05:21:37.43#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.05:21:37.43#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.05:21:37.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.05:21:37.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.05:21:37.43$vck44/valo=7,864.99 2006.285.05:21:37.43#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.05:21:37.43#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.05:21:37.43#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:37.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.05:21:37.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.05:21:37.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.05:21:37.43#ibcon#enter wrdev, iclass 5, count 0 2006.285.05:21:37.43#ibcon#first serial, iclass 5, count 0 2006.285.05:21:37.43#ibcon#enter sib2, iclass 5, count 0 2006.285.05:21:37.43#ibcon#flushed, iclass 5, count 0 2006.285.05:21:37.43#ibcon#about to write, iclass 5, count 0 2006.285.05:21:37.43#ibcon#wrote, iclass 5, count 0 2006.285.05:21:37.43#ibcon#about to read 3, iclass 5, count 0 2006.285.05:21:37.45#ibcon#read 3, iclass 5, count 0 2006.285.05:21:37.46#ibcon#about to read 4, iclass 5, count 0 2006.285.05:21:37.46#ibcon#read 4, iclass 5, count 0 2006.285.05:21:37.46#ibcon#about to read 5, iclass 5, count 0 2006.285.05:21:37.46#ibcon#read 5, iclass 5, count 0 2006.285.05:21:37.46#ibcon#about to read 6, iclass 5, count 0 2006.285.05:21:37.46#ibcon#read 6, iclass 5, count 0 2006.285.05:21:37.46#ibcon#end of sib2, iclass 5, count 0 2006.285.05:21:37.46#ibcon#*mode == 0, iclass 5, count 0 2006.285.05:21:37.46#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.05:21:37.46#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.05:21:37.46#ibcon#*before write, iclass 5, count 0 2006.285.05:21:37.46#ibcon#enter sib2, iclass 5, count 0 2006.285.05:21:37.46#ibcon#flushed, iclass 5, count 0 2006.285.05:21:37.46#ibcon#about to write, iclass 5, count 0 2006.285.05:21:37.46#ibcon#wrote, iclass 5, count 0 2006.285.05:21:37.46#ibcon#about to read 3, iclass 5, count 0 2006.285.05:21:37.47#abcon#[5=S1D000X0/0*\r\n] 2006.285.05:21:37.50#ibcon#read 3, iclass 5, count 0 2006.285.05:21:37.50#ibcon#about to read 4, iclass 5, count 0 2006.285.05:21:37.50#ibcon#read 4, iclass 5, count 0 2006.285.05:21:37.50#ibcon#about to read 5, iclass 5, count 0 2006.285.05:21:37.50#ibcon#read 5, iclass 5, count 0 2006.285.05:21:37.50#ibcon#about to read 6, iclass 5, count 0 2006.285.05:21:37.50#ibcon#read 6, iclass 5, count 0 2006.285.05:21:37.50#ibcon#end of sib2, iclass 5, count 0 2006.285.05:21:37.50#ibcon#*after write, iclass 5, count 0 2006.285.05:21:37.50#ibcon#*before return 0, iclass 5, count 0 2006.285.05:21:37.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.05:21:37.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.05:21:37.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.05:21:37.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.05:21:37.50$vck44/va=7,4 2006.285.05:21:37.50#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.05:21:37.50#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.05:21:37.50#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:37.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:37.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:37.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:37.55#ibcon#enter wrdev, iclass 10, count 2 2006.285.05:21:37.55#ibcon#first serial, iclass 10, count 2 2006.285.05:21:37.55#ibcon#enter sib2, iclass 10, count 2 2006.285.05:21:37.55#ibcon#flushed, iclass 10, count 2 2006.285.05:21:37.55#ibcon#about to write, iclass 10, count 2 2006.285.05:21:37.55#ibcon#wrote, iclass 10, count 2 2006.285.05:21:37.55#ibcon#about to read 3, iclass 10, count 2 2006.285.05:21:37.57#ibcon#read 3, iclass 10, count 2 2006.285.05:21:37.57#ibcon#about to read 4, iclass 10, count 2 2006.285.05:21:37.57#ibcon#read 4, iclass 10, count 2 2006.285.05:21:37.57#ibcon#about to read 5, iclass 10, count 2 2006.285.05:21:37.57#ibcon#read 5, iclass 10, count 2 2006.285.05:21:37.57#ibcon#about to read 6, iclass 10, count 2 2006.285.05:21:37.57#ibcon#read 6, iclass 10, count 2 2006.285.05:21:37.57#ibcon#end of sib2, iclass 10, count 2 2006.285.05:21:37.57#ibcon#*mode == 0, iclass 10, count 2 2006.285.05:21:37.57#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.05:21:37.58#ibcon#[25=AT07-04\r\n] 2006.285.05:21:37.58#ibcon#*before write, iclass 10, count 2 2006.285.05:21:37.58#ibcon#enter sib2, iclass 10, count 2 2006.285.05:21:37.58#ibcon#flushed, iclass 10, count 2 2006.285.05:21:37.58#ibcon#about to write, iclass 10, count 2 2006.285.05:21:37.58#ibcon#wrote, iclass 10, count 2 2006.285.05:21:37.58#ibcon#about to read 3, iclass 10, count 2 2006.285.05:21:37.61#ibcon#read 3, iclass 10, count 2 2006.285.05:21:37.61#ibcon#about to read 4, iclass 10, count 2 2006.285.05:21:37.61#ibcon#read 4, iclass 10, count 2 2006.285.05:21:37.61#ibcon#about to read 5, iclass 10, count 2 2006.285.05:21:37.61#ibcon#read 5, iclass 10, count 2 2006.285.05:21:37.61#ibcon#about to read 6, iclass 10, count 2 2006.285.05:21:37.61#ibcon#read 6, iclass 10, count 2 2006.285.05:21:37.61#ibcon#end of sib2, iclass 10, count 2 2006.285.05:21:37.61#ibcon#*after write, iclass 10, count 2 2006.285.05:21:37.61#ibcon#*before return 0, iclass 10, count 2 2006.285.05:21:37.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:37.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:37.61#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.05:21:37.61#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:37.61#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.05:21:37.73#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.05:21:37.73#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.05:21:37.73#ibcon#enter wrdev, iclass 10, count 0 2006.285.05:21:37.73#ibcon#first serial, iclass 10, count 0 2006.285.05:21:37.73#ibcon#enter sib2, iclass 10, count 0 2006.285.05:21:37.73#ibcon#flushed, iclass 10, count 0 2006.285.05:21:37.73#ibcon#about to write, iclass 10, count 0 2006.285.05:21:37.73#ibcon#wrote, iclass 10, count 0 2006.285.05:21:37.73#ibcon#about to read 3, iclass 10, count 0 2006.285.05:21:37.75#ibcon#read 3, iclass 10, count 0 2006.285.05:21:37.75#ibcon#about to read 4, iclass 10, count 0 2006.285.05:21:37.75#ibcon#read 4, iclass 10, count 0 2006.285.05:21:37.75#ibcon#about to read 5, iclass 10, count 0 2006.285.05:21:37.75#ibcon#read 5, iclass 10, count 0 2006.285.05:21:37.75#ibcon#about to read 6, iclass 10, count 0 2006.285.05:21:37.75#ibcon#read 6, iclass 10, count 0 2006.285.05:21:37.75#ibcon#end of sib2, iclass 10, count 0 2006.285.05:21:37.75#ibcon#*mode == 0, iclass 10, count 0 2006.285.05:21:37.75#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.05:21:37.75#ibcon#[25=USB\r\n] 2006.285.05:21:37.75#ibcon#*before write, iclass 10, count 0 2006.285.05:21:37.75#ibcon#enter sib2, iclass 10, count 0 2006.285.05:21:37.75#ibcon#flushed, iclass 10, count 0 2006.285.05:21:37.75#ibcon#about to write, iclass 10, count 0 2006.285.05:21:37.75#ibcon#wrote, iclass 10, count 0 2006.285.05:21:37.75#ibcon#about to read 3, iclass 10, count 0 2006.285.05:21:37.78#ibcon#read 3, iclass 10, count 0 2006.285.05:21:37.78#ibcon#about to read 4, iclass 10, count 0 2006.285.05:21:37.78#ibcon#read 4, iclass 10, count 0 2006.285.05:21:37.78#ibcon#about to read 5, iclass 10, count 0 2006.285.05:21:37.78#ibcon#read 5, iclass 10, count 0 2006.285.05:21:37.78#ibcon#about to read 6, iclass 10, count 0 2006.285.05:21:37.78#ibcon#read 6, iclass 10, count 0 2006.285.05:21:37.78#ibcon#end of sib2, iclass 10, count 0 2006.285.05:21:37.78#ibcon#*after write, iclass 10, count 0 2006.285.05:21:37.78#ibcon#*before return 0, iclass 10, count 0 2006.285.05:21:37.78#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.05:21:37.78#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.05:21:37.78#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.05:21:37.78#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.05:21:37.78$vck44/valo=8,884.99 2006.285.05:21:37.78#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.05:21:37.78#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.05:21:37.78#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:37.78#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.05:21:37.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.05:21:37.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.05:21:37.78#ibcon#enter wrdev, iclass 12, count 0 2006.285.05:21:37.78#ibcon#first serial, iclass 12, count 0 2006.285.05:21:37.78#ibcon#enter sib2, iclass 12, count 0 2006.285.05:21:37.78#ibcon#flushed, iclass 12, count 0 2006.285.05:21:37.78#ibcon#about to write, iclass 12, count 0 2006.285.05:21:37.78#ibcon#wrote, iclass 12, count 0 2006.285.05:21:37.78#ibcon#about to read 3, iclass 12, count 0 2006.285.05:21:37.80#ibcon#read 3, iclass 12, count 0 2006.285.05:21:37.81#ibcon#about to read 4, iclass 12, count 0 2006.285.05:21:37.81#ibcon#read 4, iclass 12, count 0 2006.285.05:21:37.81#ibcon#about to read 5, iclass 12, count 0 2006.285.05:21:37.81#ibcon#read 5, iclass 12, count 0 2006.285.05:21:37.81#ibcon#about to read 6, iclass 12, count 0 2006.285.05:21:37.81#ibcon#read 6, iclass 12, count 0 2006.285.05:21:37.81#ibcon#end of sib2, iclass 12, count 0 2006.285.05:21:37.81#ibcon#*mode == 0, iclass 12, count 0 2006.285.05:21:37.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.05:21:37.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.05:21:37.81#ibcon#*before write, iclass 12, count 0 2006.285.05:21:37.81#ibcon#enter sib2, iclass 12, count 0 2006.285.05:21:37.81#ibcon#flushed, iclass 12, count 0 2006.285.05:21:37.81#ibcon#about to write, iclass 12, count 0 2006.285.05:21:37.81#ibcon#wrote, iclass 12, count 0 2006.285.05:21:37.81#ibcon#about to read 3, iclass 12, count 0 2006.285.05:21:37.85#ibcon#read 3, iclass 12, count 0 2006.285.05:21:37.85#ibcon#about to read 4, iclass 12, count 0 2006.285.05:21:37.85#ibcon#read 4, iclass 12, count 0 2006.285.05:21:37.85#ibcon#about to read 5, iclass 12, count 0 2006.285.05:21:37.85#ibcon#read 5, iclass 12, count 0 2006.285.05:21:37.85#ibcon#about to read 6, iclass 12, count 0 2006.285.05:21:37.85#ibcon#read 6, iclass 12, count 0 2006.285.05:21:37.85#ibcon#end of sib2, iclass 12, count 0 2006.285.05:21:37.85#ibcon#*after write, iclass 12, count 0 2006.285.05:21:37.85#ibcon#*before return 0, iclass 12, count 0 2006.285.05:21:37.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.05:21:37.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.05:21:37.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.05:21:37.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.05:21:37.85$vck44/va=8,3 2006.285.05:21:37.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.05:21:37.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.05:21:37.91#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:37.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.05:21:37.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.05:21:37.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.05:21:37.91#ibcon#enter wrdev, iclass 14, count 2 2006.285.05:21:37.91#ibcon#first serial, iclass 14, count 2 2006.285.05:21:37.91#ibcon#enter sib2, iclass 14, count 2 2006.285.05:21:37.91#ibcon#flushed, iclass 14, count 2 2006.285.05:21:37.91#ibcon#about to write, iclass 14, count 2 2006.285.05:21:37.91#ibcon#wrote, iclass 14, count 2 2006.285.05:21:37.91#ibcon#about to read 3, iclass 14, count 2 2006.285.05:21:37.92#ibcon#read 3, iclass 14, count 2 2006.285.05:21:37.92#ibcon#about to read 4, iclass 14, count 2 2006.285.05:21:37.92#ibcon#read 4, iclass 14, count 2 2006.285.05:21:37.92#ibcon#about to read 5, iclass 14, count 2 2006.285.05:21:37.92#ibcon#read 5, iclass 14, count 2 2006.285.05:21:37.92#ibcon#about to read 6, iclass 14, count 2 2006.285.05:21:37.92#ibcon#read 6, iclass 14, count 2 2006.285.05:21:37.92#ibcon#end of sib2, iclass 14, count 2 2006.285.05:21:37.92#ibcon#*mode == 0, iclass 14, count 2 2006.285.05:21:37.92#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.05:21:37.92#ibcon#[25=AT08-03\r\n] 2006.285.05:21:37.92#ibcon#*before write, iclass 14, count 2 2006.285.05:21:37.92#ibcon#enter sib2, iclass 14, count 2 2006.285.05:21:37.92#ibcon#flushed, iclass 14, count 2 2006.285.05:21:37.92#ibcon#about to write, iclass 14, count 2 2006.285.05:21:37.92#ibcon#wrote, iclass 14, count 2 2006.285.05:21:37.92#ibcon#about to read 3, iclass 14, count 2 2006.285.05:21:37.98#ibcon#read 3, iclass 14, count 2 2006.285.05:21:37.98#ibcon#about to read 4, iclass 14, count 2 2006.285.05:21:37.98#ibcon#read 4, iclass 14, count 2 2006.285.05:21:37.98#ibcon#about to read 5, iclass 14, count 2 2006.285.05:21:37.98#ibcon#read 5, iclass 14, count 2 2006.285.05:21:37.98#ibcon#about to read 6, iclass 14, count 2 2006.285.05:21:37.98#ibcon#read 6, iclass 14, count 2 2006.285.05:21:37.98#ibcon#end of sib2, iclass 14, count 2 2006.285.05:21:37.98#ibcon#*after write, iclass 14, count 2 2006.285.05:21:37.98#ibcon#*before return 0, iclass 14, count 2 2006.285.05:21:37.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.05:21:37.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.05:21:37.98#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.05:21:37.98#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:37.98#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.05:21:38.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.05:21:38.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.05:21:38.09#ibcon#enter wrdev, iclass 14, count 0 2006.285.05:21:38.09#ibcon#first serial, iclass 14, count 0 2006.285.05:21:38.09#ibcon#enter sib2, iclass 14, count 0 2006.285.05:21:38.09#ibcon#flushed, iclass 14, count 0 2006.285.05:21:38.09#ibcon#about to write, iclass 14, count 0 2006.285.05:21:38.09#ibcon#wrote, iclass 14, count 0 2006.285.05:21:38.09#ibcon#about to read 3, iclass 14, count 0 2006.285.05:21:38.13#ibcon#read 3, iclass 14, count 0 2006.285.05:21:38.13#ibcon#about to read 4, iclass 14, count 0 2006.285.05:21:38.13#ibcon#read 4, iclass 14, count 0 2006.285.05:21:38.13#ibcon#about to read 5, iclass 14, count 0 2006.285.05:21:38.13#ibcon#read 5, iclass 14, count 0 2006.285.05:21:38.13#ibcon#about to read 6, iclass 14, count 0 2006.285.05:21:38.13#ibcon#read 6, iclass 14, count 0 2006.285.05:21:38.13#ibcon#end of sib2, iclass 14, count 0 2006.285.05:21:38.13#ibcon#*mode == 0, iclass 14, count 0 2006.285.05:21:38.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.05:21:38.13#ibcon#[25=USB\r\n] 2006.285.05:21:38.13#ibcon#*before write, iclass 14, count 0 2006.285.05:21:38.13#ibcon#enter sib2, iclass 14, count 0 2006.285.05:21:38.13#ibcon#flushed, iclass 14, count 0 2006.285.05:21:38.13#ibcon#about to write, iclass 14, count 0 2006.285.05:21:38.13#ibcon#wrote, iclass 14, count 0 2006.285.05:21:38.13#ibcon#about to read 3, iclass 14, count 0 2006.285.05:21:38.16#ibcon#read 3, iclass 14, count 0 2006.285.05:21:38.16#ibcon#about to read 4, iclass 14, count 0 2006.285.05:21:38.16#ibcon#read 4, iclass 14, count 0 2006.285.05:21:38.16#ibcon#about to read 5, iclass 14, count 0 2006.285.05:21:38.16#ibcon#read 5, iclass 14, count 0 2006.285.05:21:38.16#ibcon#about to read 6, iclass 14, count 0 2006.285.05:21:38.16#ibcon#read 6, iclass 14, count 0 2006.285.05:21:38.16#ibcon#end of sib2, iclass 14, count 0 2006.285.05:21:38.16#ibcon#*after write, iclass 14, count 0 2006.285.05:21:38.16#ibcon#*before return 0, iclass 14, count 0 2006.285.05:21:38.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.05:21:38.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.05:21:38.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.05:21:38.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.05:21:38.16$vck44/vblo=1,629.99 2006.285.05:21:38.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.05:21:38.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:38.16#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:38.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.05:21:38.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.05:21:38.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.05:21:38.16#ibcon#enter wrdev, iclass 16, count 0 2006.285.05:21:38.16#ibcon#first serial, iclass 16, count 0 2006.285.05:21:38.16#ibcon#enter sib2, iclass 16, count 0 2006.285.05:21:38.16#ibcon#flushed, iclass 16, count 0 2006.285.05:21:38.16#ibcon#about to write, iclass 16, count 0 2006.285.05:21:38.16#ibcon#wrote, iclass 16, count 0 2006.285.05:21:38.16#ibcon#about to read 3, iclass 16, count 0 2006.285.05:21:38.18#ibcon#read 3, iclass 16, count 0 2006.285.05:21:38.22#ibcon#about to read 4, iclass 16, count 0 2006.285.05:21:38.22#ibcon#read 4, iclass 16, count 0 2006.285.05:21:38.23#ibcon#about to read 5, iclass 16, count 0 2006.285.05:21:38.23#ibcon#read 5, iclass 16, count 0 2006.285.05:21:38.23#ibcon#about to read 6, iclass 16, count 0 2006.285.05:21:38.23#ibcon#read 6, iclass 16, count 0 2006.285.05:21:38.23#ibcon#end of sib2, iclass 16, count 0 2006.285.05:21:38.23#ibcon#*mode == 0, iclass 16, count 0 2006.285.05:21:38.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.05:21:38.23#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.05:21:38.23#ibcon#*before write, iclass 16, count 0 2006.285.05:21:38.23#ibcon#enter sib2, iclass 16, count 0 2006.285.05:21:38.23#ibcon#flushed, iclass 16, count 0 2006.285.05:21:38.23#ibcon#about to write, iclass 16, count 0 2006.285.05:21:38.23#ibcon#wrote, iclass 16, count 0 2006.285.05:21:38.23#ibcon#about to read 3, iclass 16, count 0 2006.285.05:21:38.28#ibcon#read 3, iclass 16, count 0 2006.285.05:21:38.30#ibcon#about to read 4, iclass 16, count 0 2006.285.05:21:38.30#ibcon#read 4, iclass 16, count 0 2006.285.05:21:38.30#ibcon#about to read 5, iclass 16, count 0 2006.285.05:21:38.30#ibcon#read 5, iclass 16, count 0 2006.285.05:21:38.30#ibcon#about to read 6, iclass 16, count 0 2006.285.05:21:38.30#ibcon#read 6, iclass 16, count 0 2006.285.05:21:38.30#ibcon#end of sib2, iclass 16, count 0 2006.285.05:21:38.30#ibcon#*after write, iclass 16, count 0 2006.285.05:21:38.30#ibcon#*before return 0, iclass 16, count 0 2006.285.05:21:38.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.05:21:38.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.05:21:38.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.05:21:38.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.05:21:38.30$vck44/vb=1,4 2006.285.05:21:38.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.05:21:38.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.05:21:38.30#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:38.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:38.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:38.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:38.30#ibcon#enter wrdev, iclass 18, count 2 2006.285.05:21:38.30#ibcon#first serial, iclass 18, count 2 2006.285.05:21:38.30#ibcon#enter sib2, iclass 18, count 2 2006.285.05:21:38.30#ibcon#flushed, iclass 18, count 2 2006.285.05:21:38.30#ibcon#about to write, iclass 18, count 2 2006.285.05:21:38.30#ibcon#wrote, iclass 18, count 2 2006.285.05:21:38.30#ibcon#about to read 3, iclass 18, count 2 2006.285.05:21:38.31#ibcon#read 3, iclass 18, count 2 2006.285.05:21:38.31#ibcon#about to read 4, iclass 18, count 2 2006.285.05:21:38.31#ibcon#read 4, iclass 18, count 2 2006.285.05:21:38.31#ibcon#about to read 5, iclass 18, count 2 2006.285.05:21:38.31#ibcon#read 5, iclass 18, count 2 2006.285.05:21:38.31#ibcon#about to read 6, iclass 18, count 2 2006.285.05:21:38.31#ibcon#read 6, iclass 18, count 2 2006.285.05:21:38.32#ibcon#end of sib2, iclass 18, count 2 2006.285.05:21:38.32#ibcon#*mode == 0, iclass 18, count 2 2006.285.05:21:38.32#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.05:21:38.32#ibcon#[27=AT01-04\r\n] 2006.285.05:21:38.32#ibcon#*before write, iclass 18, count 2 2006.285.05:21:38.32#ibcon#enter sib2, iclass 18, count 2 2006.285.05:21:38.32#ibcon#flushed, iclass 18, count 2 2006.285.05:21:38.32#ibcon#about to write, iclass 18, count 2 2006.285.05:21:38.32#ibcon#wrote, iclass 18, count 2 2006.285.05:21:38.32#ibcon#about to read 3, iclass 18, count 2 2006.285.05:21:38.36#ibcon#read 3, iclass 18, count 2 2006.285.05:21:38.36#ibcon#about to read 4, iclass 18, count 2 2006.285.05:21:38.36#ibcon#read 4, iclass 18, count 2 2006.285.05:21:38.36#ibcon#about to read 5, iclass 18, count 2 2006.285.05:21:38.36#ibcon#read 5, iclass 18, count 2 2006.285.05:21:38.36#ibcon#about to read 6, iclass 18, count 2 2006.285.05:21:38.36#ibcon#read 6, iclass 18, count 2 2006.285.05:21:38.36#ibcon#end of sib2, iclass 18, count 2 2006.285.05:21:38.36#ibcon#*after write, iclass 18, count 2 2006.285.05:21:38.36#ibcon#*before return 0, iclass 18, count 2 2006.285.05:21:38.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:38.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:38.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.05:21:38.36#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:38.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.05:21:38.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.05:21:38.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.05:21:38.48#ibcon#enter wrdev, iclass 18, count 0 2006.285.05:21:38.48#ibcon#first serial, iclass 18, count 0 2006.285.05:21:38.48#ibcon#enter sib2, iclass 18, count 0 2006.285.05:21:38.48#ibcon#flushed, iclass 18, count 0 2006.285.05:21:38.48#ibcon#about to write, iclass 18, count 0 2006.285.05:21:38.48#ibcon#wrote, iclass 18, count 0 2006.285.05:21:38.48#ibcon#about to read 3, iclass 18, count 0 2006.285.05:21:38.50#ibcon#read 3, iclass 18, count 0 2006.285.05:21:38.50#ibcon#about to read 4, iclass 18, count 0 2006.285.05:21:38.50#ibcon#read 4, iclass 18, count 0 2006.285.05:21:38.50#ibcon#about to read 5, iclass 18, count 0 2006.285.05:21:38.50#ibcon#read 5, iclass 18, count 0 2006.285.05:21:38.50#ibcon#about to read 6, iclass 18, count 0 2006.285.05:21:38.50#ibcon#read 6, iclass 18, count 0 2006.285.05:21:38.50#ibcon#end of sib2, iclass 18, count 0 2006.285.05:21:38.50#ibcon#*mode == 0, iclass 18, count 0 2006.285.05:21:38.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.05:21:38.50#ibcon#[27=USB\r\n] 2006.285.05:21:38.50#ibcon#*before write, iclass 18, count 0 2006.285.05:21:38.50#ibcon#enter sib2, iclass 18, count 0 2006.285.05:21:38.50#ibcon#flushed, iclass 18, count 0 2006.285.05:21:38.50#ibcon#about to write, iclass 18, count 0 2006.285.05:21:38.50#ibcon#wrote, iclass 18, count 0 2006.285.05:21:38.50#ibcon#about to read 3, iclass 18, count 0 2006.285.05:21:38.53#ibcon#read 3, iclass 18, count 0 2006.285.05:21:38.53#ibcon#about to read 4, iclass 18, count 0 2006.285.05:21:38.53#ibcon#read 4, iclass 18, count 0 2006.285.05:21:38.53#ibcon#about to read 5, iclass 18, count 0 2006.285.05:21:38.53#ibcon#read 5, iclass 18, count 0 2006.285.05:21:38.53#ibcon#about to read 6, iclass 18, count 0 2006.285.05:21:38.53#ibcon#read 6, iclass 18, count 0 2006.285.05:21:38.53#ibcon#end of sib2, iclass 18, count 0 2006.285.05:21:38.53#ibcon#*after write, iclass 18, count 0 2006.285.05:21:38.53#ibcon#*before return 0, iclass 18, count 0 2006.285.05:21:38.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.05:21:38.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.05:21:38.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.05:21:38.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.05:21:38.53$vck44/vblo=2,634.99 2006.285.05:21:38.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.05:21:38.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:38.53#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:38.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.05:21:38.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.05:21:38.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.05:21:38.53#ibcon#enter wrdev, iclass 20, count 0 2006.285.05:21:38.53#ibcon#first serial, iclass 20, count 0 2006.285.05:21:38.53#ibcon#enter sib2, iclass 20, count 0 2006.285.05:21:38.53#ibcon#flushed, iclass 20, count 0 2006.285.05:21:38.53#ibcon#about to write, iclass 20, count 0 2006.285.05:21:38.53#ibcon#wrote, iclass 20, count 0 2006.285.05:21:38.53#ibcon#about to read 3, iclass 20, count 0 2006.285.05:21:38.55#ibcon#read 3, iclass 20, count 0 2006.285.05:21:38.55#ibcon#about to read 4, iclass 20, count 0 2006.285.05:21:38.55#ibcon#read 4, iclass 20, count 0 2006.285.05:21:38.55#ibcon#about to read 5, iclass 20, count 0 2006.285.05:21:38.55#ibcon#read 5, iclass 20, count 0 2006.285.05:21:38.55#ibcon#about to read 6, iclass 20, count 0 2006.285.05:21:38.55#ibcon#read 6, iclass 20, count 0 2006.285.05:21:38.55#ibcon#end of sib2, iclass 20, count 0 2006.285.05:21:38.55#ibcon#*mode == 0, iclass 20, count 0 2006.285.05:21:38.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.05:21:38.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.05:21:38.59#ibcon#*before write, iclass 20, count 0 2006.285.05:21:38.59#ibcon#enter sib2, iclass 20, count 0 2006.285.05:21:38.59#ibcon#flushed, iclass 20, count 0 2006.285.05:21:38.59#ibcon#about to write, iclass 20, count 0 2006.285.05:21:38.59#ibcon#wrote, iclass 20, count 0 2006.285.05:21:38.59#ibcon#about to read 3, iclass 20, count 0 2006.285.05:21:38.63#ibcon#read 3, iclass 20, count 0 2006.285.05:21:38.63#ibcon#about to read 4, iclass 20, count 0 2006.285.05:21:38.63#ibcon#read 4, iclass 20, count 0 2006.285.05:21:38.63#ibcon#about to read 5, iclass 20, count 0 2006.285.05:21:38.63#ibcon#read 5, iclass 20, count 0 2006.285.05:21:38.63#ibcon#about to read 6, iclass 20, count 0 2006.285.05:21:38.63#ibcon#read 6, iclass 20, count 0 2006.285.05:21:38.63#ibcon#end of sib2, iclass 20, count 0 2006.285.05:21:38.63#ibcon#*after write, iclass 20, count 0 2006.285.05:21:38.63#ibcon#*before return 0, iclass 20, count 0 2006.285.05:21:38.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.05:21:38.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.05:21:38.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.05:21:38.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.05:21:38.63$vck44/vb=2,5 2006.285.05:21:38.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.05:21:38.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.05:21:38.63#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:38.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:38.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:38.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:38.66#ibcon#enter wrdev, iclass 22, count 2 2006.285.05:21:38.66#ibcon#first serial, iclass 22, count 2 2006.285.05:21:38.66#ibcon#enter sib2, iclass 22, count 2 2006.285.05:21:38.66#ibcon#flushed, iclass 22, count 2 2006.285.05:21:38.66#ibcon#about to write, iclass 22, count 2 2006.285.05:21:38.66#ibcon#wrote, iclass 22, count 2 2006.285.05:21:38.66#ibcon#about to read 3, iclass 22, count 2 2006.285.05:21:38.68#ibcon#read 3, iclass 22, count 2 2006.285.05:21:38.68#ibcon#about to read 4, iclass 22, count 2 2006.285.05:21:38.68#ibcon#read 4, iclass 22, count 2 2006.285.05:21:38.68#ibcon#about to read 5, iclass 22, count 2 2006.285.05:21:38.68#ibcon#read 5, iclass 22, count 2 2006.285.05:21:38.68#ibcon#about to read 6, iclass 22, count 2 2006.285.05:21:38.68#ibcon#read 6, iclass 22, count 2 2006.285.05:21:38.68#ibcon#end of sib2, iclass 22, count 2 2006.285.05:21:38.68#ibcon#*mode == 0, iclass 22, count 2 2006.285.05:21:38.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.05:21:38.68#ibcon#[27=AT02-05\r\n] 2006.285.05:21:38.68#ibcon#*before write, iclass 22, count 2 2006.285.05:21:38.68#ibcon#enter sib2, iclass 22, count 2 2006.285.05:21:38.68#ibcon#flushed, iclass 22, count 2 2006.285.05:21:38.68#ibcon#about to write, iclass 22, count 2 2006.285.05:21:38.68#ibcon#wrote, iclass 22, count 2 2006.285.05:21:38.68#ibcon#about to read 3, iclass 22, count 2 2006.285.05:21:38.71#ibcon#read 3, iclass 22, count 2 2006.285.05:21:38.71#ibcon#about to read 4, iclass 22, count 2 2006.285.05:21:38.71#ibcon#read 4, iclass 22, count 2 2006.285.05:21:38.71#ibcon#about to read 5, iclass 22, count 2 2006.285.05:21:38.71#ibcon#read 5, iclass 22, count 2 2006.285.05:21:38.71#ibcon#about to read 6, iclass 22, count 2 2006.285.05:21:38.71#ibcon#read 6, iclass 22, count 2 2006.285.05:21:38.71#ibcon#end of sib2, iclass 22, count 2 2006.285.05:21:38.71#ibcon#*after write, iclass 22, count 2 2006.285.05:21:38.71#ibcon#*before return 0, iclass 22, count 2 2006.285.05:21:38.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:38.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:38.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.05:21:38.71#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:38.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.05:21:38.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.05:21:38.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.05:21:38.83#ibcon#enter wrdev, iclass 22, count 0 2006.285.05:21:38.83#ibcon#first serial, iclass 22, count 0 2006.285.05:21:38.83#ibcon#enter sib2, iclass 22, count 0 2006.285.05:21:38.83#ibcon#flushed, iclass 22, count 0 2006.285.05:21:38.83#ibcon#about to write, iclass 22, count 0 2006.285.05:21:38.83#ibcon#wrote, iclass 22, count 0 2006.285.05:21:38.83#ibcon#about to read 3, iclass 22, count 0 2006.285.05:21:38.85#ibcon#read 3, iclass 22, count 0 2006.285.05:21:38.85#ibcon#about to read 4, iclass 22, count 0 2006.285.05:21:38.85#ibcon#read 4, iclass 22, count 0 2006.285.05:21:38.85#ibcon#about to read 5, iclass 22, count 0 2006.285.05:21:38.85#ibcon#read 5, iclass 22, count 0 2006.285.05:21:38.85#ibcon#about to read 6, iclass 22, count 0 2006.285.05:21:38.85#ibcon#read 6, iclass 22, count 0 2006.285.05:21:38.85#ibcon#end of sib2, iclass 22, count 0 2006.285.05:21:38.85#ibcon#*mode == 0, iclass 22, count 0 2006.285.05:21:38.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.05:21:38.85#ibcon#[27=USB\r\n] 2006.285.05:21:38.85#ibcon#*before write, iclass 22, count 0 2006.285.05:21:38.85#ibcon#enter sib2, iclass 22, count 0 2006.285.05:21:38.85#ibcon#flushed, iclass 22, count 0 2006.285.05:21:38.85#ibcon#about to write, iclass 22, count 0 2006.285.05:21:38.85#ibcon#wrote, iclass 22, count 0 2006.285.05:21:38.85#ibcon#about to read 3, iclass 22, count 0 2006.285.05:21:38.88#ibcon#read 3, iclass 22, count 0 2006.285.05:21:38.88#ibcon#about to read 4, iclass 22, count 0 2006.285.05:21:38.88#ibcon#read 4, iclass 22, count 0 2006.285.05:21:38.88#ibcon#about to read 5, iclass 22, count 0 2006.285.05:21:38.88#ibcon#read 5, iclass 22, count 0 2006.285.05:21:38.88#ibcon#about to read 6, iclass 22, count 0 2006.285.05:21:38.88#ibcon#read 6, iclass 22, count 0 2006.285.05:21:38.88#ibcon#end of sib2, iclass 22, count 0 2006.285.05:21:38.88#ibcon#*after write, iclass 22, count 0 2006.285.05:21:38.88#ibcon#*before return 0, iclass 22, count 0 2006.285.05:21:38.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.05:21:38.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.05:21:38.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.05:21:38.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.05:21:38.89$vck44/vblo=3,649.99 2006.285.05:21:38.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.05:21:38.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:38.89#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:38.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.05:21:38.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.05:21:38.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.05:21:38.89#ibcon#enter wrdev, iclass 24, count 0 2006.285.05:21:38.89#ibcon#first serial, iclass 24, count 0 2006.285.05:21:38.89#ibcon#enter sib2, iclass 24, count 0 2006.285.05:21:38.89#ibcon#flushed, iclass 24, count 0 2006.285.05:21:38.89#ibcon#about to write, iclass 24, count 0 2006.285.05:21:38.89#ibcon#wrote, iclass 24, count 0 2006.285.05:21:38.89#ibcon#about to read 3, iclass 24, count 0 2006.285.05:21:38.90#ibcon#read 3, iclass 24, count 0 2006.285.05:21:38.91#ibcon#about to read 4, iclass 24, count 0 2006.285.05:21:38.91#ibcon#read 4, iclass 24, count 0 2006.285.05:21:38.91#ibcon#about to read 5, iclass 24, count 0 2006.285.05:21:38.91#ibcon#read 5, iclass 24, count 0 2006.285.05:21:38.91#ibcon#about to read 6, iclass 24, count 0 2006.285.05:21:38.91#ibcon#read 6, iclass 24, count 0 2006.285.05:21:38.91#ibcon#end of sib2, iclass 24, count 0 2006.285.05:21:38.91#ibcon#*mode == 0, iclass 24, count 0 2006.285.05:21:38.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.05:21:38.91#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.05:21:38.91#ibcon#*before write, iclass 24, count 0 2006.285.05:21:38.91#ibcon#enter sib2, iclass 24, count 0 2006.285.05:21:38.91#ibcon#flushed, iclass 24, count 0 2006.285.05:21:38.91#ibcon#about to write, iclass 24, count 0 2006.285.05:21:38.91#ibcon#wrote, iclass 24, count 0 2006.285.05:21:38.91#ibcon#about to read 3, iclass 24, count 0 2006.285.05:21:38.95#ibcon#read 3, iclass 24, count 0 2006.285.05:21:39.00#ibcon#about to read 4, iclass 24, count 0 2006.285.05:21:39.00#ibcon#read 4, iclass 24, count 0 2006.285.05:21:39.00#ibcon#about to read 5, iclass 24, count 0 2006.285.05:21:39.00#ibcon#read 5, iclass 24, count 0 2006.285.05:21:39.00#ibcon#about to read 6, iclass 24, count 0 2006.285.05:21:39.00#ibcon#read 6, iclass 24, count 0 2006.285.05:21:39.00#ibcon#end of sib2, iclass 24, count 0 2006.285.05:21:39.00#ibcon#*after write, iclass 24, count 0 2006.285.05:21:39.00#ibcon#*before return 0, iclass 24, count 0 2006.285.05:21:39.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.05:21:39.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.05:21:39.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.05:21:39.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.05:21:39.00$vck44/vb=3,4 2006.285.05:21:39.00#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.05:21:39.00#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.05:21:39.00#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:39.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:39.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:39.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:39.00#ibcon#enter wrdev, iclass 26, count 2 2006.285.05:21:39.00#ibcon#first serial, iclass 26, count 2 2006.285.05:21:39.00#ibcon#enter sib2, iclass 26, count 2 2006.285.05:21:39.00#ibcon#flushed, iclass 26, count 2 2006.285.05:21:39.00#ibcon#about to write, iclass 26, count 2 2006.285.05:21:39.00#ibcon#wrote, iclass 26, count 2 2006.285.05:21:39.00#ibcon#about to read 3, iclass 26, count 2 2006.285.05:21:39.02#ibcon#read 3, iclass 26, count 2 2006.285.05:21:39.05#ibcon#about to read 4, iclass 26, count 2 2006.285.05:21:39.05#ibcon#read 4, iclass 26, count 2 2006.285.05:21:39.05#ibcon#about to read 5, iclass 26, count 2 2006.285.05:21:39.05#ibcon#read 5, iclass 26, count 2 2006.285.05:21:39.05#ibcon#about to read 6, iclass 26, count 2 2006.285.05:21:39.05#ibcon#read 6, iclass 26, count 2 2006.285.05:21:39.05#ibcon#end of sib2, iclass 26, count 2 2006.285.05:21:39.05#ibcon#*mode == 0, iclass 26, count 2 2006.285.05:21:39.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.05:21:39.05#ibcon#[27=AT03-04\r\n] 2006.285.05:21:39.05#ibcon#*before write, iclass 26, count 2 2006.285.05:21:39.05#ibcon#enter sib2, iclass 26, count 2 2006.285.05:21:39.05#ibcon#flushed, iclass 26, count 2 2006.285.05:21:39.05#ibcon#about to write, iclass 26, count 2 2006.285.05:21:39.05#ibcon#wrote, iclass 26, count 2 2006.285.05:21:39.05#ibcon#about to read 3, iclass 26, count 2 2006.285.05:21:39.08#ibcon#read 3, iclass 26, count 2 2006.285.05:21:39.12#ibcon#about to read 4, iclass 26, count 2 2006.285.05:21:39.12#ibcon#read 4, iclass 26, count 2 2006.285.05:21:39.12#ibcon#about to read 5, iclass 26, count 2 2006.285.05:21:39.12#ibcon#read 5, iclass 26, count 2 2006.285.05:21:39.12#ibcon#about to read 6, iclass 26, count 2 2006.285.05:21:39.12#ibcon#read 6, iclass 26, count 2 2006.285.05:21:39.12#ibcon#end of sib2, iclass 26, count 2 2006.285.05:21:39.12#ibcon#*after write, iclass 26, count 2 2006.285.05:21:39.12#ibcon#*before return 0, iclass 26, count 2 2006.285.05:21:39.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:39.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:39.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.05:21:39.12#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:39.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.05:21:39.23#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.05:21:39.23#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.05:21:39.23#ibcon#enter wrdev, iclass 26, count 0 2006.285.05:21:39.23#ibcon#first serial, iclass 26, count 0 2006.285.05:21:39.23#ibcon#enter sib2, iclass 26, count 0 2006.285.05:21:39.23#ibcon#flushed, iclass 26, count 0 2006.285.05:21:39.23#ibcon#about to write, iclass 26, count 0 2006.285.05:21:39.23#ibcon#wrote, iclass 26, count 0 2006.285.05:21:39.23#ibcon#about to read 3, iclass 26, count 0 2006.285.05:21:39.25#ibcon#read 3, iclass 26, count 0 2006.285.05:21:39.25#ibcon#about to read 4, iclass 26, count 0 2006.285.05:21:39.25#ibcon#read 4, iclass 26, count 0 2006.285.05:21:39.25#ibcon#about to read 5, iclass 26, count 0 2006.285.05:21:39.25#ibcon#read 5, iclass 26, count 0 2006.285.05:21:39.25#ibcon#about to read 6, iclass 26, count 0 2006.285.05:21:39.25#ibcon#read 6, iclass 26, count 0 2006.285.05:21:39.25#ibcon#end of sib2, iclass 26, count 0 2006.285.05:21:39.25#ibcon#*mode == 0, iclass 26, count 0 2006.285.05:21:39.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.05:21:39.25#ibcon#[27=USB\r\n] 2006.285.05:21:39.25#ibcon#*before write, iclass 26, count 0 2006.285.05:21:39.25#ibcon#enter sib2, iclass 26, count 0 2006.285.05:21:39.25#ibcon#flushed, iclass 26, count 0 2006.285.05:21:39.25#ibcon#about to write, iclass 26, count 0 2006.285.05:21:39.25#ibcon#wrote, iclass 26, count 0 2006.285.05:21:39.25#ibcon#about to read 3, iclass 26, count 0 2006.285.05:21:39.28#ibcon#read 3, iclass 26, count 0 2006.285.05:21:39.28#ibcon#about to read 4, iclass 26, count 0 2006.285.05:21:39.28#ibcon#read 4, iclass 26, count 0 2006.285.05:21:39.28#ibcon#about to read 5, iclass 26, count 0 2006.285.05:21:39.28#ibcon#read 5, iclass 26, count 0 2006.285.05:21:39.28#ibcon#about to read 6, iclass 26, count 0 2006.285.05:21:39.28#ibcon#read 6, iclass 26, count 0 2006.285.05:21:39.28#ibcon#end of sib2, iclass 26, count 0 2006.285.05:21:39.28#ibcon#*after write, iclass 26, count 0 2006.285.05:21:39.28#ibcon#*before return 0, iclass 26, count 0 2006.285.05:21:39.28#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.05:21:39.28#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.05:21:39.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.05:21:39.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.05:21:39.28$vck44/vblo=4,679.99 2006.285.05:21:39.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.05:21:39.28#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:39.28#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:39.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.05:21:39.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.05:21:39.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.05:21:39.28#ibcon#enter wrdev, iclass 28, count 0 2006.285.05:21:39.28#ibcon#first serial, iclass 28, count 0 2006.285.05:21:39.28#ibcon#enter sib2, iclass 28, count 0 2006.285.05:21:39.28#ibcon#flushed, iclass 28, count 0 2006.285.05:21:39.28#ibcon#about to write, iclass 28, count 0 2006.285.05:21:39.28#ibcon#wrote, iclass 28, count 0 2006.285.05:21:39.28#ibcon#about to read 3, iclass 28, count 0 2006.285.05:21:39.30#ibcon#read 3, iclass 28, count 0 2006.285.05:21:39.32#ibcon#about to read 4, iclass 28, count 0 2006.285.05:21:39.32#ibcon#read 4, iclass 28, count 0 2006.285.05:21:39.32#ibcon#about to read 5, iclass 28, count 0 2006.285.05:21:39.32#ibcon#read 5, iclass 28, count 0 2006.285.05:21:39.32#ibcon#about to read 6, iclass 28, count 0 2006.285.05:21:39.32#ibcon#read 6, iclass 28, count 0 2006.285.05:21:39.32#ibcon#end of sib2, iclass 28, count 0 2006.285.05:21:39.32#ibcon#*mode == 0, iclass 28, count 0 2006.285.05:21:39.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.05:21:39.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.05:21:39.32#ibcon#*before write, iclass 28, count 0 2006.285.05:21:39.32#ibcon#enter sib2, iclass 28, count 0 2006.285.05:21:39.32#ibcon#flushed, iclass 28, count 0 2006.285.05:21:39.32#ibcon#about to write, iclass 28, count 0 2006.285.05:21:39.32#ibcon#wrote, iclass 28, count 0 2006.285.05:21:39.32#ibcon#about to read 3, iclass 28, count 0 2006.285.05:21:39.36#ibcon#read 3, iclass 28, count 0 2006.285.05:21:39.36#ibcon#about to read 4, iclass 28, count 0 2006.285.05:21:39.36#ibcon#read 4, iclass 28, count 0 2006.285.05:21:39.36#ibcon#about to read 5, iclass 28, count 0 2006.285.05:21:39.36#ibcon#read 5, iclass 28, count 0 2006.285.05:21:39.36#ibcon#about to read 6, iclass 28, count 0 2006.285.05:21:39.36#ibcon#read 6, iclass 28, count 0 2006.285.05:21:39.36#ibcon#end of sib2, iclass 28, count 0 2006.285.05:21:39.36#ibcon#*after write, iclass 28, count 0 2006.285.05:21:39.36#ibcon#*before return 0, iclass 28, count 0 2006.285.05:21:39.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.05:21:39.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.05:21:39.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.05:21:39.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.05:21:39.36$vck44/vb=4,5 2006.285.05:21:39.36#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.05:21:39.36#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.05:21:39.36#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:39.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:39.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:39.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:39.40#ibcon#enter wrdev, iclass 30, count 2 2006.285.05:21:39.40#ibcon#first serial, iclass 30, count 2 2006.285.05:21:39.40#ibcon#enter sib2, iclass 30, count 2 2006.285.05:21:39.40#ibcon#flushed, iclass 30, count 2 2006.285.05:21:39.40#ibcon#about to write, iclass 30, count 2 2006.285.05:21:39.40#ibcon#wrote, iclass 30, count 2 2006.285.05:21:39.40#ibcon#about to read 3, iclass 30, count 2 2006.285.05:21:39.42#ibcon#read 3, iclass 30, count 2 2006.285.05:21:39.42#ibcon#about to read 4, iclass 30, count 2 2006.285.05:21:39.42#ibcon#read 4, iclass 30, count 2 2006.285.05:21:39.42#ibcon#about to read 5, iclass 30, count 2 2006.285.05:21:39.42#ibcon#read 5, iclass 30, count 2 2006.285.05:21:39.42#ibcon#about to read 6, iclass 30, count 2 2006.285.05:21:39.42#ibcon#read 6, iclass 30, count 2 2006.285.05:21:39.42#ibcon#end of sib2, iclass 30, count 2 2006.285.05:21:39.42#ibcon#*mode == 0, iclass 30, count 2 2006.285.05:21:39.42#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.05:21:39.42#ibcon#[27=AT04-05\r\n] 2006.285.05:21:39.42#ibcon#*before write, iclass 30, count 2 2006.285.05:21:39.42#ibcon#enter sib2, iclass 30, count 2 2006.285.05:21:39.42#ibcon#flushed, iclass 30, count 2 2006.285.05:21:39.42#ibcon#about to write, iclass 30, count 2 2006.285.05:21:39.42#ibcon#wrote, iclass 30, count 2 2006.285.05:21:39.42#ibcon#about to read 3, iclass 30, count 2 2006.285.05:21:39.45#ibcon#read 3, iclass 30, count 2 2006.285.05:21:39.45#ibcon#about to read 4, iclass 30, count 2 2006.285.05:21:39.45#ibcon#read 4, iclass 30, count 2 2006.285.05:21:39.45#ibcon#about to read 5, iclass 30, count 2 2006.285.05:21:39.45#ibcon#read 5, iclass 30, count 2 2006.285.05:21:39.45#ibcon#about to read 6, iclass 30, count 2 2006.285.05:21:39.45#ibcon#read 6, iclass 30, count 2 2006.285.05:21:39.45#ibcon#end of sib2, iclass 30, count 2 2006.285.05:21:39.45#ibcon#*after write, iclass 30, count 2 2006.285.05:21:39.45#ibcon#*before return 0, iclass 30, count 2 2006.285.05:21:39.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:39.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:39.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.05:21:39.45#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:39.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.05:21:39.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.05:21:39.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.05:21:39.57#ibcon#enter wrdev, iclass 30, count 0 2006.285.05:21:39.57#ibcon#first serial, iclass 30, count 0 2006.285.05:21:39.57#ibcon#enter sib2, iclass 30, count 0 2006.285.05:21:39.57#ibcon#flushed, iclass 30, count 0 2006.285.05:21:39.57#ibcon#about to write, iclass 30, count 0 2006.285.05:21:39.57#ibcon#wrote, iclass 30, count 0 2006.285.05:21:39.57#ibcon#about to read 3, iclass 30, count 0 2006.285.05:21:39.59#ibcon#read 3, iclass 30, count 0 2006.285.05:21:39.59#ibcon#about to read 4, iclass 30, count 0 2006.285.05:21:39.59#ibcon#read 4, iclass 30, count 0 2006.285.05:21:39.59#ibcon#about to read 5, iclass 30, count 0 2006.285.05:21:39.59#ibcon#read 5, iclass 30, count 0 2006.285.05:21:39.59#ibcon#about to read 6, iclass 30, count 0 2006.285.05:21:39.59#ibcon#read 6, iclass 30, count 0 2006.285.05:21:39.59#ibcon#end of sib2, iclass 30, count 0 2006.285.05:21:39.59#ibcon#*mode == 0, iclass 30, count 0 2006.285.05:21:39.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.05:21:39.59#ibcon#[27=USB\r\n] 2006.285.05:21:39.59#ibcon#*before write, iclass 30, count 0 2006.285.05:21:39.59#ibcon#enter sib2, iclass 30, count 0 2006.285.05:21:39.59#ibcon#flushed, iclass 30, count 0 2006.285.05:21:39.59#ibcon#about to write, iclass 30, count 0 2006.285.05:21:39.59#ibcon#wrote, iclass 30, count 0 2006.285.05:21:39.59#ibcon#about to read 3, iclass 30, count 0 2006.285.05:21:39.62#ibcon#read 3, iclass 30, count 0 2006.285.05:21:39.62#ibcon#about to read 4, iclass 30, count 0 2006.285.05:21:39.62#ibcon#read 4, iclass 30, count 0 2006.285.05:21:39.62#ibcon#about to read 5, iclass 30, count 0 2006.285.05:21:39.62#ibcon#read 5, iclass 30, count 0 2006.285.05:21:39.62#ibcon#about to read 6, iclass 30, count 0 2006.285.05:21:39.62#ibcon#read 6, iclass 30, count 0 2006.285.05:21:39.62#ibcon#end of sib2, iclass 30, count 0 2006.285.05:21:39.62#ibcon#*after write, iclass 30, count 0 2006.285.05:21:39.62#ibcon#*before return 0, iclass 30, count 0 2006.285.05:21:39.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.05:21:39.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.05:21:39.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.05:21:39.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.05:21:39.62$vck44/vblo=5,709.99 2006.285.05:21:39.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.05:21:39.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:39.62#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:39.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.05:21:39.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.05:21:39.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.05:21:39.62#ibcon#enter wrdev, iclass 32, count 0 2006.285.05:21:39.62#ibcon#first serial, iclass 32, count 0 2006.285.05:21:39.62#ibcon#enter sib2, iclass 32, count 0 2006.285.05:21:39.62#ibcon#flushed, iclass 32, count 0 2006.285.05:21:39.62#ibcon#about to write, iclass 32, count 0 2006.285.05:21:39.62#ibcon#wrote, iclass 32, count 0 2006.285.05:21:39.62#ibcon#about to read 3, iclass 32, count 0 2006.285.05:21:39.64#ibcon#read 3, iclass 32, count 0 2006.285.05:21:39.64#ibcon#about to read 4, iclass 32, count 0 2006.285.05:21:39.64#ibcon#read 4, iclass 32, count 0 2006.285.05:21:39.64#ibcon#about to read 5, iclass 32, count 0 2006.285.05:21:39.64#ibcon#read 5, iclass 32, count 0 2006.285.05:21:39.64#ibcon#about to read 6, iclass 32, count 0 2006.285.05:21:39.64#ibcon#read 6, iclass 32, count 0 2006.285.05:21:39.64#ibcon#end of sib2, iclass 32, count 0 2006.285.05:21:39.64#ibcon#*mode == 0, iclass 32, count 0 2006.285.05:21:39.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.05:21:39.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.05:21:39.64#ibcon#*before write, iclass 32, count 0 2006.285.05:21:39.64#ibcon#enter sib2, iclass 32, count 0 2006.285.05:21:39.64#ibcon#flushed, iclass 32, count 0 2006.285.05:21:39.64#ibcon#about to write, iclass 32, count 0 2006.285.05:21:39.64#ibcon#wrote, iclass 32, count 0 2006.285.05:21:39.64#ibcon#about to read 3, iclass 32, count 0 2006.285.05:21:39.68#ibcon#read 3, iclass 32, count 0 2006.285.05:21:39.68#ibcon#about to read 4, iclass 32, count 0 2006.285.05:21:39.68#ibcon#read 4, iclass 32, count 0 2006.285.05:21:39.68#ibcon#about to read 5, iclass 32, count 0 2006.285.05:21:39.68#ibcon#read 5, iclass 32, count 0 2006.285.05:21:39.68#ibcon#about to read 6, iclass 32, count 0 2006.285.05:21:39.68#ibcon#read 6, iclass 32, count 0 2006.285.05:21:39.68#ibcon#end of sib2, iclass 32, count 0 2006.285.05:21:39.68#ibcon#*after write, iclass 32, count 0 2006.285.05:21:39.68#ibcon#*before return 0, iclass 32, count 0 2006.285.05:21:39.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.05:21:39.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.05:21:39.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.05:21:39.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.05:21:39.68$vck44/vb=5,4 2006.285.05:21:39.72#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.05:21:39.72#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.05:21:39.72#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:39.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:39.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:39.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:39.73#ibcon#enter wrdev, iclass 34, count 2 2006.285.05:21:39.73#ibcon#first serial, iclass 34, count 2 2006.285.05:21:39.73#ibcon#enter sib2, iclass 34, count 2 2006.285.05:21:39.73#ibcon#flushed, iclass 34, count 2 2006.285.05:21:39.73#ibcon#about to write, iclass 34, count 2 2006.285.05:21:39.73#ibcon#wrote, iclass 34, count 2 2006.285.05:21:39.74#ibcon#about to read 3, iclass 34, count 2 2006.285.05:21:39.75#ibcon#read 3, iclass 34, count 2 2006.285.05:21:39.75#ibcon#about to read 4, iclass 34, count 2 2006.285.05:21:39.75#ibcon#read 4, iclass 34, count 2 2006.285.05:21:39.75#ibcon#about to read 5, iclass 34, count 2 2006.285.05:21:39.75#ibcon#read 5, iclass 34, count 2 2006.285.05:21:39.75#ibcon#about to read 6, iclass 34, count 2 2006.285.05:21:39.75#ibcon#read 6, iclass 34, count 2 2006.285.05:21:39.75#ibcon#end of sib2, iclass 34, count 2 2006.285.05:21:39.75#ibcon#*mode == 0, iclass 34, count 2 2006.285.05:21:39.75#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.05:21:39.75#ibcon#[27=AT05-04\r\n] 2006.285.05:21:39.75#ibcon#*before write, iclass 34, count 2 2006.285.05:21:39.75#ibcon#enter sib2, iclass 34, count 2 2006.285.05:21:39.75#ibcon#flushed, iclass 34, count 2 2006.285.05:21:39.75#ibcon#about to write, iclass 34, count 2 2006.285.05:21:39.75#ibcon#wrote, iclass 34, count 2 2006.285.05:21:39.75#ibcon#about to read 3, iclass 34, count 2 2006.285.05:21:39.78#ibcon#read 3, iclass 34, count 2 2006.285.05:21:39.78#ibcon#about to read 4, iclass 34, count 2 2006.285.05:21:39.78#ibcon#read 4, iclass 34, count 2 2006.285.05:21:39.78#ibcon#about to read 5, iclass 34, count 2 2006.285.05:21:39.78#ibcon#read 5, iclass 34, count 2 2006.285.05:21:39.78#ibcon#about to read 6, iclass 34, count 2 2006.285.05:21:39.78#ibcon#read 6, iclass 34, count 2 2006.285.05:21:39.78#ibcon#end of sib2, iclass 34, count 2 2006.285.05:21:39.78#ibcon#*after write, iclass 34, count 2 2006.285.05:21:39.78#ibcon#*before return 0, iclass 34, count 2 2006.285.05:21:39.78#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:39.78#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:39.78#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.05:21:39.78#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:39.78#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.05:21:39.90#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.05:21:39.90#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.05:21:39.90#ibcon#enter wrdev, iclass 34, count 0 2006.285.05:21:39.90#ibcon#first serial, iclass 34, count 0 2006.285.05:21:39.90#ibcon#enter sib2, iclass 34, count 0 2006.285.05:21:39.90#ibcon#flushed, iclass 34, count 0 2006.285.05:21:39.90#ibcon#about to write, iclass 34, count 0 2006.285.05:21:39.90#ibcon#wrote, iclass 34, count 0 2006.285.05:21:39.90#ibcon#about to read 3, iclass 34, count 0 2006.285.05:21:39.92#ibcon#read 3, iclass 34, count 0 2006.285.05:21:39.92#ibcon#about to read 4, iclass 34, count 0 2006.285.05:21:39.92#ibcon#read 4, iclass 34, count 0 2006.285.05:21:39.92#ibcon#about to read 5, iclass 34, count 0 2006.285.05:21:39.92#ibcon#read 5, iclass 34, count 0 2006.285.05:21:39.92#ibcon#about to read 6, iclass 34, count 0 2006.285.05:21:39.92#ibcon#read 6, iclass 34, count 0 2006.285.05:21:39.92#ibcon#end of sib2, iclass 34, count 0 2006.285.05:21:39.92#ibcon#*mode == 0, iclass 34, count 0 2006.285.05:21:39.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.05:21:39.92#ibcon#[27=USB\r\n] 2006.285.05:21:39.92#ibcon#*before write, iclass 34, count 0 2006.285.05:21:39.92#ibcon#enter sib2, iclass 34, count 0 2006.285.05:21:39.92#ibcon#flushed, iclass 34, count 0 2006.285.05:21:39.92#ibcon#about to write, iclass 34, count 0 2006.285.05:21:39.92#ibcon#wrote, iclass 34, count 0 2006.285.05:21:39.92#ibcon#about to read 3, iclass 34, count 0 2006.285.05:21:39.95#ibcon#read 3, iclass 34, count 0 2006.285.05:21:39.95#ibcon#about to read 4, iclass 34, count 0 2006.285.05:21:39.95#ibcon#read 4, iclass 34, count 0 2006.285.05:21:39.95#ibcon#about to read 5, iclass 34, count 0 2006.285.05:21:39.95#ibcon#read 5, iclass 34, count 0 2006.285.05:21:39.95#ibcon#about to read 6, iclass 34, count 0 2006.285.05:21:39.95#ibcon#read 6, iclass 34, count 0 2006.285.05:21:39.95#ibcon#end of sib2, iclass 34, count 0 2006.285.05:21:39.95#ibcon#*after write, iclass 34, count 0 2006.285.05:21:39.95#ibcon#*before return 0, iclass 34, count 0 2006.285.05:21:39.95#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.05:21:39.95#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.05:21:39.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.05:21:39.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.05:21:39.95$vck44/vblo=6,719.99 2006.285.05:21:39.95#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.05:21:39.95#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:39.95#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:39.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.05:21:39.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.05:21:39.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.05:21:39.95#ibcon#enter wrdev, iclass 36, count 0 2006.285.05:21:39.95#ibcon#first serial, iclass 36, count 0 2006.285.05:21:39.95#ibcon#enter sib2, iclass 36, count 0 2006.285.05:21:39.95#ibcon#flushed, iclass 36, count 0 2006.285.05:21:39.95#ibcon#about to write, iclass 36, count 0 2006.285.05:21:39.95#ibcon#wrote, iclass 36, count 0 2006.285.05:21:39.95#ibcon#about to read 3, iclass 36, count 0 2006.285.05:21:39.97#ibcon#read 3, iclass 36, count 0 2006.285.05:21:40.00#ibcon#about to read 4, iclass 36, count 0 2006.285.05:21:40.00#ibcon#read 4, iclass 36, count 0 2006.285.05:21:40.00#ibcon#about to read 5, iclass 36, count 0 2006.285.05:21:40.00#ibcon#read 5, iclass 36, count 0 2006.285.05:21:40.00#ibcon#about to read 6, iclass 36, count 0 2006.285.05:21:40.00#ibcon#read 6, iclass 36, count 0 2006.285.05:21:40.00#ibcon#end of sib2, iclass 36, count 0 2006.285.05:21:40.00#ibcon#*mode == 0, iclass 36, count 0 2006.285.05:21:40.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.05:21:40.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.05:21:40.00#ibcon#*before write, iclass 36, count 0 2006.285.05:21:40.00#ibcon#enter sib2, iclass 36, count 0 2006.285.05:21:40.00#ibcon#flushed, iclass 36, count 0 2006.285.05:21:40.00#ibcon#about to write, iclass 36, count 0 2006.285.05:21:40.00#ibcon#wrote, iclass 36, count 0 2006.285.05:21:40.00#ibcon#about to read 3, iclass 36, count 0 2006.285.05:21:40.04#ibcon#read 3, iclass 36, count 0 2006.285.05:21:40.04#ibcon#about to read 4, iclass 36, count 0 2006.285.05:21:40.04#ibcon#read 4, iclass 36, count 0 2006.285.05:21:40.04#ibcon#about to read 5, iclass 36, count 0 2006.285.05:21:40.04#ibcon#read 5, iclass 36, count 0 2006.285.05:21:40.04#ibcon#about to read 6, iclass 36, count 0 2006.285.05:21:40.04#ibcon#read 6, iclass 36, count 0 2006.285.05:21:40.04#ibcon#end of sib2, iclass 36, count 0 2006.285.05:21:40.04#ibcon#*after write, iclass 36, count 0 2006.285.05:21:40.04#ibcon#*before return 0, iclass 36, count 0 2006.285.05:21:40.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.05:21:40.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.05:21:40.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.05:21:40.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.05:21:40.04$vck44/vb=6,3 2006.285.05:21:40.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.05:21:40.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.05:21:40.04#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:40.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:40.07#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:40.07#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:40.07#ibcon#enter wrdev, iclass 38, count 2 2006.285.05:21:40.07#ibcon#first serial, iclass 38, count 2 2006.285.05:21:40.07#ibcon#enter sib2, iclass 38, count 2 2006.285.05:21:40.07#ibcon#flushed, iclass 38, count 2 2006.285.05:21:40.07#ibcon#about to write, iclass 38, count 2 2006.285.05:21:40.07#ibcon#wrote, iclass 38, count 2 2006.285.05:21:40.07#ibcon#about to read 3, iclass 38, count 2 2006.285.05:21:40.09#ibcon#read 3, iclass 38, count 2 2006.285.05:21:40.09#ibcon#about to read 4, iclass 38, count 2 2006.285.05:21:40.09#ibcon#read 4, iclass 38, count 2 2006.285.05:21:40.09#ibcon#about to read 5, iclass 38, count 2 2006.285.05:21:40.09#ibcon#read 5, iclass 38, count 2 2006.285.05:21:40.09#ibcon#about to read 6, iclass 38, count 2 2006.285.05:21:40.15#ibcon#read 6, iclass 38, count 2 2006.285.05:21:40.15#ibcon#end of sib2, iclass 38, count 2 2006.285.05:21:40.15#ibcon#*mode == 0, iclass 38, count 2 2006.285.05:21:40.15#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.05:21:40.15#ibcon#[27=AT06-03\r\n] 2006.285.05:21:40.15#ibcon#*before write, iclass 38, count 2 2006.285.05:21:40.15#ibcon#enter sib2, iclass 38, count 2 2006.285.05:21:40.15#ibcon#flushed, iclass 38, count 2 2006.285.05:21:40.15#ibcon#about to write, iclass 38, count 2 2006.285.05:21:40.15#ibcon#wrote, iclass 38, count 2 2006.285.05:21:40.15#ibcon#about to read 3, iclass 38, count 2 2006.285.05:21:40.18#ibcon#read 3, iclass 38, count 2 2006.285.05:21:40.18#ibcon#about to read 4, iclass 38, count 2 2006.285.05:21:40.18#ibcon#read 4, iclass 38, count 2 2006.285.05:21:40.18#ibcon#about to read 5, iclass 38, count 2 2006.285.05:21:40.18#ibcon#read 5, iclass 38, count 2 2006.285.05:21:40.18#ibcon#about to read 6, iclass 38, count 2 2006.285.05:21:40.18#ibcon#read 6, iclass 38, count 2 2006.285.05:21:40.18#ibcon#end of sib2, iclass 38, count 2 2006.285.05:21:40.18#ibcon#*after write, iclass 38, count 2 2006.285.05:21:40.18#ibcon#*before return 0, iclass 38, count 2 2006.285.05:21:40.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:40.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:40.18#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.05:21:40.18#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:40.18#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.05:21:40.30#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.05:21:40.30#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.05:21:40.30#ibcon#enter wrdev, iclass 38, count 0 2006.285.05:21:40.30#ibcon#first serial, iclass 38, count 0 2006.285.05:21:40.30#ibcon#enter sib2, iclass 38, count 0 2006.285.05:21:40.30#ibcon#flushed, iclass 38, count 0 2006.285.05:21:40.30#ibcon#about to write, iclass 38, count 0 2006.285.05:21:40.30#ibcon#wrote, iclass 38, count 0 2006.285.05:21:40.30#ibcon#about to read 3, iclass 38, count 0 2006.285.05:21:40.32#ibcon#read 3, iclass 38, count 0 2006.285.05:21:40.32#ibcon#about to read 4, iclass 38, count 0 2006.285.05:21:40.32#ibcon#read 4, iclass 38, count 0 2006.285.05:21:40.32#ibcon#about to read 5, iclass 38, count 0 2006.285.05:21:40.32#ibcon#read 5, iclass 38, count 0 2006.285.05:21:40.32#ibcon#about to read 6, iclass 38, count 0 2006.285.05:21:40.32#ibcon#read 6, iclass 38, count 0 2006.285.05:21:40.32#ibcon#end of sib2, iclass 38, count 0 2006.285.05:21:40.32#ibcon#*mode == 0, iclass 38, count 0 2006.285.05:21:40.32#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.05:21:40.32#ibcon#[27=USB\r\n] 2006.285.05:21:40.32#ibcon#*before write, iclass 38, count 0 2006.285.05:21:40.32#ibcon#enter sib2, iclass 38, count 0 2006.285.05:21:40.32#ibcon#flushed, iclass 38, count 0 2006.285.05:21:40.32#ibcon#about to write, iclass 38, count 0 2006.285.05:21:40.32#ibcon#wrote, iclass 38, count 0 2006.285.05:21:40.32#ibcon#about to read 3, iclass 38, count 0 2006.285.05:21:40.35#ibcon#read 3, iclass 38, count 0 2006.285.05:21:40.35#ibcon#about to read 4, iclass 38, count 0 2006.285.05:21:40.35#ibcon#read 4, iclass 38, count 0 2006.285.05:21:40.35#ibcon#about to read 5, iclass 38, count 0 2006.285.05:21:40.35#ibcon#read 5, iclass 38, count 0 2006.285.05:21:40.35#ibcon#about to read 6, iclass 38, count 0 2006.285.05:21:40.35#ibcon#read 6, iclass 38, count 0 2006.285.05:21:40.35#ibcon#end of sib2, iclass 38, count 0 2006.285.05:21:40.35#ibcon#*after write, iclass 38, count 0 2006.285.05:21:40.35#ibcon#*before return 0, iclass 38, count 0 2006.285.05:21:40.35#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.05:21:40.35#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.05:21:40.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.05:21:40.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.05:21:40.35$vck44/vblo=7,734.99 2006.285.05:21:40.35#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.05:21:40.35#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.05:21:40.35#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:40.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.05:21:40.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.05:21:40.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.05:21:40.35#ibcon#enter wrdev, iclass 40, count 0 2006.285.05:21:40.35#ibcon#first serial, iclass 40, count 0 2006.285.05:21:40.35#ibcon#enter sib2, iclass 40, count 0 2006.285.05:21:40.35#ibcon#flushed, iclass 40, count 0 2006.285.05:21:40.35#ibcon#about to write, iclass 40, count 0 2006.285.05:21:40.35#ibcon#wrote, iclass 40, count 0 2006.285.05:21:40.35#ibcon#about to read 3, iclass 40, count 0 2006.285.05:21:40.37#ibcon#read 3, iclass 40, count 0 2006.285.05:21:40.37#ibcon#about to read 4, iclass 40, count 0 2006.285.05:21:40.37#ibcon#read 4, iclass 40, count 0 2006.285.05:21:40.37#ibcon#about to read 5, iclass 40, count 0 2006.285.05:21:40.37#ibcon#read 5, iclass 40, count 0 2006.285.05:21:40.37#ibcon#about to read 6, iclass 40, count 0 2006.285.05:21:40.37#ibcon#read 6, iclass 40, count 0 2006.285.05:21:40.37#ibcon#end of sib2, iclass 40, count 0 2006.285.05:21:40.37#ibcon#*mode == 0, iclass 40, count 0 2006.285.05:21:40.37#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.05:21:40.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.05:21:40.37#ibcon#*before write, iclass 40, count 0 2006.285.05:21:40.37#ibcon#enter sib2, iclass 40, count 0 2006.285.05:21:40.37#ibcon#flushed, iclass 40, count 0 2006.285.05:21:40.37#ibcon#about to write, iclass 40, count 0 2006.285.05:21:40.37#ibcon#wrote, iclass 40, count 0 2006.285.05:21:40.37#ibcon#about to read 3, iclass 40, count 0 2006.285.05:21:40.41#ibcon#read 3, iclass 40, count 0 2006.285.05:21:40.41#ibcon#about to read 4, iclass 40, count 0 2006.285.05:21:40.41#ibcon#read 4, iclass 40, count 0 2006.285.05:21:40.41#ibcon#about to read 5, iclass 40, count 0 2006.285.05:21:40.41#ibcon#read 5, iclass 40, count 0 2006.285.05:21:40.41#ibcon#about to read 6, iclass 40, count 0 2006.285.05:21:40.41#ibcon#read 6, iclass 40, count 0 2006.285.05:21:40.41#ibcon#end of sib2, iclass 40, count 0 2006.285.05:21:40.41#ibcon#*after write, iclass 40, count 0 2006.285.05:21:40.41#ibcon#*before return 0, iclass 40, count 0 2006.285.05:21:40.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.05:21:40.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.05:21:40.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.05:21:40.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.05:21:40.41$vck44/vb=7,4 2006.285.05:21:40.41#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.05:21:40.41#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.05:21:40.41#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:40.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.05:21:40.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.05:21:40.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.05:21:40.47#ibcon#enter wrdev, iclass 4, count 2 2006.285.05:21:40.47#ibcon#first serial, iclass 4, count 2 2006.285.05:21:40.47#ibcon#enter sib2, iclass 4, count 2 2006.285.05:21:40.47#ibcon#flushed, iclass 4, count 2 2006.285.05:21:40.47#ibcon#about to write, iclass 4, count 2 2006.285.05:21:40.47#ibcon#wrote, iclass 4, count 2 2006.285.05:21:40.47#ibcon#about to read 3, iclass 4, count 2 2006.285.05:21:40.49#ibcon#read 3, iclass 4, count 2 2006.285.05:21:40.49#ibcon#about to read 4, iclass 4, count 2 2006.285.05:21:40.49#ibcon#read 4, iclass 4, count 2 2006.285.05:21:40.49#ibcon#about to read 5, iclass 4, count 2 2006.285.05:21:40.49#ibcon#read 5, iclass 4, count 2 2006.285.05:21:40.49#ibcon#about to read 6, iclass 4, count 2 2006.285.05:21:40.49#ibcon#read 6, iclass 4, count 2 2006.285.05:21:40.49#ibcon#end of sib2, iclass 4, count 2 2006.285.05:21:40.49#ibcon#*mode == 0, iclass 4, count 2 2006.285.05:21:40.49#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.05:21:40.49#ibcon#[27=AT07-04\r\n] 2006.285.05:21:40.49#ibcon#*before write, iclass 4, count 2 2006.285.05:21:40.49#ibcon#enter sib2, iclass 4, count 2 2006.285.05:21:40.49#ibcon#flushed, iclass 4, count 2 2006.285.05:21:40.49#ibcon#about to write, iclass 4, count 2 2006.285.05:21:40.49#ibcon#wrote, iclass 4, count 2 2006.285.05:21:40.49#ibcon#about to read 3, iclass 4, count 2 2006.285.05:21:40.52#ibcon#read 3, iclass 4, count 2 2006.285.05:21:40.52#ibcon#about to read 4, iclass 4, count 2 2006.285.05:21:40.52#ibcon#read 4, iclass 4, count 2 2006.285.05:21:40.52#ibcon#about to read 5, iclass 4, count 2 2006.285.05:21:40.52#ibcon#read 5, iclass 4, count 2 2006.285.05:21:40.52#ibcon#about to read 6, iclass 4, count 2 2006.285.05:21:40.52#ibcon#read 6, iclass 4, count 2 2006.285.05:21:40.52#ibcon#end of sib2, iclass 4, count 2 2006.285.05:21:40.52#ibcon#*after write, iclass 4, count 2 2006.285.05:21:40.52#ibcon#*before return 0, iclass 4, count 2 2006.285.05:21:40.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.05:21:40.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.05:21:40.52#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.05:21:40.52#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:40.52#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.05:21:40.64#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.05:21:40.64#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.05:21:40.64#ibcon#enter wrdev, iclass 4, count 0 2006.285.05:21:40.64#ibcon#first serial, iclass 4, count 0 2006.285.05:21:40.64#ibcon#enter sib2, iclass 4, count 0 2006.285.05:21:40.64#ibcon#flushed, iclass 4, count 0 2006.285.05:21:40.64#ibcon#about to write, iclass 4, count 0 2006.285.05:21:40.64#ibcon#wrote, iclass 4, count 0 2006.285.05:21:40.64#ibcon#about to read 3, iclass 4, count 0 2006.285.05:21:40.66#ibcon#read 3, iclass 4, count 0 2006.285.05:21:40.66#ibcon#about to read 4, iclass 4, count 0 2006.285.05:21:40.66#ibcon#read 4, iclass 4, count 0 2006.285.05:21:40.66#ibcon#about to read 5, iclass 4, count 0 2006.285.05:21:40.66#ibcon#read 5, iclass 4, count 0 2006.285.05:21:40.66#ibcon#about to read 6, iclass 4, count 0 2006.285.05:21:40.66#ibcon#read 6, iclass 4, count 0 2006.285.05:21:40.66#ibcon#end of sib2, iclass 4, count 0 2006.285.05:21:40.66#ibcon#*mode == 0, iclass 4, count 0 2006.285.05:21:40.66#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.05:21:40.66#ibcon#[27=USB\r\n] 2006.285.05:21:40.66#ibcon#*before write, iclass 4, count 0 2006.285.05:21:40.66#ibcon#enter sib2, iclass 4, count 0 2006.285.05:21:40.66#ibcon#flushed, iclass 4, count 0 2006.285.05:21:40.66#ibcon#about to write, iclass 4, count 0 2006.285.05:21:40.66#ibcon#wrote, iclass 4, count 0 2006.285.05:21:40.66#ibcon#about to read 3, iclass 4, count 0 2006.285.05:21:40.69#ibcon#read 3, iclass 4, count 0 2006.285.05:21:40.69#ibcon#about to read 4, iclass 4, count 0 2006.285.05:21:40.69#ibcon#read 4, iclass 4, count 0 2006.285.05:21:40.69#ibcon#about to read 5, iclass 4, count 0 2006.285.05:21:40.69#ibcon#read 5, iclass 4, count 0 2006.285.05:21:40.69#ibcon#about to read 6, iclass 4, count 0 2006.285.05:21:40.69#ibcon#read 6, iclass 4, count 0 2006.285.05:21:40.69#ibcon#end of sib2, iclass 4, count 0 2006.285.05:21:40.69#ibcon#*after write, iclass 4, count 0 2006.285.05:21:40.69#ibcon#*before return 0, iclass 4, count 0 2006.285.05:21:40.69#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.05:21:40.69#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.05:21:40.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.05:21:40.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.05:21:40.69$vck44/vblo=8,744.99 2006.285.05:21:40.69#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.05:21:40.69#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:40.69#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:40.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.05:21:40.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.05:21:40.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.05:21:40.69#ibcon#enter wrdev, iclass 6, count 0 2006.285.05:21:40.69#ibcon#first serial, iclass 6, count 0 2006.285.05:21:40.69#ibcon#enter sib2, iclass 6, count 0 2006.285.05:21:40.69#ibcon#flushed, iclass 6, count 0 2006.285.05:21:40.69#ibcon#about to write, iclass 6, count 0 2006.285.05:21:40.69#ibcon#wrote, iclass 6, count 0 2006.285.05:21:40.69#ibcon#about to read 3, iclass 6, count 0 2006.285.05:21:40.71#ibcon#read 3, iclass 6, count 0 2006.285.05:21:40.71#ibcon#about to read 4, iclass 6, count 0 2006.285.05:21:40.71#ibcon#read 4, iclass 6, count 0 2006.285.05:21:40.71#ibcon#about to read 5, iclass 6, count 0 2006.285.05:21:40.71#ibcon#read 5, iclass 6, count 0 2006.285.05:21:40.71#ibcon#about to read 6, iclass 6, count 0 2006.285.05:21:40.71#ibcon#read 6, iclass 6, count 0 2006.285.05:21:40.71#ibcon#end of sib2, iclass 6, count 0 2006.285.05:21:40.71#ibcon#*mode == 0, iclass 6, count 0 2006.285.05:21:40.71#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.05:21:40.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.05:21:40.71#ibcon#*before write, iclass 6, count 0 2006.285.05:21:40.71#ibcon#enter sib2, iclass 6, count 0 2006.285.05:21:40.71#ibcon#flushed, iclass 6, count 0 2006.285.05:21:40.71#ibcon#about to write, iclass 6, count 0 2006.285.05:21:40.71#ibcon#wrote, iclass 6, count 0 2006.285.05:21:40.71#ibcon#about to read 3, iclass 6, count 0 2006.285.05:21:40.75#ibcon#read 3, iclass 6, count 0 2006.285.05:21:40.75#ibcon#about to read 4, iclass 6, count 0 2006.285.05:21:40.75#ibcon#read 4, iclass 6, count 0 2006.285.05:21:40.75#ibcon#about to read 5, iclass 6, count 0 2006.285.05:21:40.75#ibcon#read 5, iclass 6, count 0 2006.285.05:21:40.75#ibcon#about to read 6, iclass 6, count 0 2006.285.05:21:40.75#ibcon#read 6, iclass 6, count 0 2006.285.05:21:40.75#ibcon#end of sib2, iclass 6, count 0 2006.285.05:21:40.75#ibcon#*after write, iclass 6, count 0 2006.285.05:21:40.75#ibcon#*before return 0, iclass 6, count 0 2006.285.05:21:40.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.05:21:40.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.05:21:40.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.05:21:40.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.05:21:40.75$vck44/vb=8,4 2006.285.05:21:40.75#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.05:21:40.75#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.05:21:40.75#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:40.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:40.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:40.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:40.81#ibcon#enter wrdev, iclass 10, count 2 2006.285.05:21:40.81#ibcon#first serial, iclass 10, count 2 2006.285.05:21:40.81#ibcon#enter sib2, iclass 10, count 2 2006.285.05:21:40.81#ibcon#flushed, iclass 10, count 2 2006.285.05:21:40.81#ibcon#about to write, iclass 10, count 2 2006.285.05:21:40.81#ibcon#wrote, iclass 10, count 2 2006.285.05:21:40.81#ibcon#about to read 3, iclass 10, count 2 2006.285.05:21:40.83#ibcon#read 3, iclass 10, count 2 2006.285.05:21:40.83#ibcon#about to read 4, iclass 10, count 2 2006.285.05:21:40.83#ibcon#read 4, iclass 10, count 2 2006.285.05:21:40.83#ibcon#about to read 5, iclass 10, count 2 2006.285.05:21:40.83#ibcon#read 5, iclass 10, count 2 2006.285.05:21:40.83#ibcon#about to read 6, iclass 10, count 2 2006.285.05:21:40.83#ibcon#read 6, iclass 10, count 2 2006.285.05:21:40.83#ibcon#end of sib2, iclass 10, count 2 2006.285.05:21:40.83#ibcon#*mode == 0, iclass 10, count 2 2006.285.05:21:40.83#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.05:21:40.83#ibcon#[27=AT08-04\r\n] 2006.285.05:21:40.83#ibcon#*before write, iclass 10, count 2 2006.285.05:21:40.83#ibcon#enter sib2, iclass 10, count 2 2006.285.05:21:40.83#ibcon#flushed, iclass 10, count 2 2006.285.05:21:40.83#ibcon#about to write, iclass 10, count 2 2006.285.05:21:40.83#ibcon#wrote, iclass 10, count 2 2006.285.05:21:40.83#ibcon#about to read 3, iclass 10, count 2 2006.285.05:21:40.86#ibcon#read 3, iclass 10, count 2 2006.285.05:21:40.86#ibcon#about to read 4, iclass 10, count 2 2006.285.05:21:40.86#ibcon#read 4, iclass 10, count 2 2006.285.05:21:40.86#ibcon#about to read 5, iclass 10, count 2 2006.285.05:21:40.86#ibcon#read 5, iclass 10, count 2 2006.285.05:21:40.86#ibcon#about to read 6, iclass 10, count 2 2006.285.05:21:40.86#ibcon#read 6, iclass 10, count 2 2006.285.05:21:40.86#ibcon#end of sib2, iclass 10, count 2 2006.285.05:21:40.86#ibcon#*after write, iclass 10, count 2 2006.285.05:21:40.86#ibcon#*before return 0, iclass 10, count 2 2006.285.05:21:40.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:40.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:40.86#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.05:21:40.86#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:40.86#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.05:21:40.98#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.05:21:40.98#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.05:21:40.98#ibcon#enter wrdev, iclass 10, count 0 2006.285.05:21:40.98#ibcon#first serial, iclass 10, count 0 2006.285.05:21:40.98#ibcon#enter sib2, iclass 10, count 0 2006.285.05:21:40.98#ibcon#flushed, iclass 10, count 0 2006.285.05:21:40.98#ibcon#about to write, iclass 10, count 0 2006.285.05:21:40.98#ibcon#wrote, iclass 10, count 0 2006.285.05:21:40.98#ibcon#about to read 3, iclass 10, count 0 2006.285.05:21:41.00#ibcon#read 3, iclass 10, count 0 2006.285.05:21:41.00#ibcon#about to read 4, iclass 10, count 0 2006.285.05:21:41.00#ibcon#read 4, iclass 10, count 0 2006.285.05:21:41.00#ibcon#about to read 5, iclass 10, count 0 2006.285.05:21:41.00#ibcon#read 5, iclass 10, count 0 2006.285.05:21:41.00#ibcon#about to read 6, iclass 10, count 0 2006.285.05:21:41.00#ibcon#read 6, iclass 10, count 0 2006.285.05:21:41.00#ibcon#end of sib2, iclass 10, count 0 2006.285.05:21:41.00#ibcon#*mode == 0, iclass 10, count 0 2006.285.05:21:41.00#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.05:21:41.00#ibcon#[27=USB\r\n] 2006.285.05:21:41.00#ibcon#*before write, iclass 10, count 0 2006.285.05:21:41.00#ibcon#enter sib2, iclass 10, count 0 2006.285.05:21:41.00#ibcon#flushed, iclass 10, count 0 2006.285.05:21:41.00#ibcon#about to write, iclass 10, count 0 2006.285.05:21:41.00#ibcon#wrote, iclass 10, count 0 2006.285.05:21:41.00#ibcon#about to read 3, iclass 10, count 0 2006.285.05:21:41.03#ibcon#read 3, iclass 10, count 0 2006.285.05:21:41.03#ibcon#about to read 4, iclass 10, count 0 2006.285.05:21:41.03#ibcon#read 4, iclass 10, count 0 2006.285.05:21:41.03#ibcon#about to read 5, iclass 10, count 0 2006.285.05:21:41.03#ibcon#read 5, iclass 10, count 0 2006.285.05:21:41.03#ibcon#about to read 6, iclass 10, count 0 2006.285.05:21:41.03#ibcon#read 6, iclass 10, count 0 2006.285.05:21:41.03#ibcon#end of sib2, iclass 10, count 0 2006.285.05:21:41.03#ibcon#*after write, iclass 10, count 0 2006.285.05:21:41.03#ibcon#*before return 0, iclass 10, count 0 2006.285.05:21:41.03#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.05:21:41.03#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.05:21:41.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.05:21:41.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.05:21:41.03$vck44/vabw=wide 2006.285.05:21:41.03#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.05:21:41.03#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.05:21:41.03#ibcon#ireg 8 cls_cnt 0 2006.285.05:21:41.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.05:21:41.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.05:21:41.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.05:21:41.03#ibcon#enter wrdev, iclass 12, count 0 2006.285.05:21:41.03#ibcon#first serial, iclass 12, count 0 2006.285.05:21:41.03#ibcon#enter sib2, iclass 12, count 0 2006.285.05:21:41.03#ibcon#flushed, iclass 12, count 0 2006.285.05:21:41.03#ibcon#about to write, iclass 12, count 0 2006.285.05:21:41.03#ibcon#wrote, iclass 12, count 0 2006.285.05:21:41.03#ibcon#about to read 3, iclass 12, count 0 2006.285.05:21:41.05#ibcon#read 3, iclass 12, count 0 2006.285.05:21:41.05#ibcon#about to read 4, iclass 12, count 0 2006.285.05:21:41.05#ibcon#read 4, iclass 12, count 0 2006.285.05:21:41.05#ibcon#about to read 5, iclass 12, count 0 2006.285.05:21:41.05#ibcon#read 5, iclass 12, count 0 2006.285.05:21:41.05#ibcon#about to read 6, iclass 12, count 0 2006.285.05:21:41.05#ibcon#read 6, iclass 12, count 0 2006.285.05:21:41.05#ibcon#end of sib2, iclass 12, count 0 2006.285.05:21:41.05#ibcon#*mode == 0, iclass 12, count 0 2006.285.05:21:41.05#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.05:21:41.05#ibcon#[25=BW32\r\n] 2006.285.05:21:41.05#ibcon#*before write, iclass 12, count 0 2006.285.05:21:41.05#ibcon#enter sib2, iclass 12, count 0 2006.285.05:21:41.05#ibcon#flushed, iclass 12, count 0 2006.285.05:21:41.05#ibcon#about to write, iclass 12, count 0 2006.285.05:21:41.05#ibcon#wrote, iclass 12, count 0 2006.285.05:21:41.05#ibcon#about to read 3, iclass 12, count 0 2006.285.05:21:41.08#ibcon#read 3, iclass 12, count 0 2006.285.05:21:41.08#ibcon#about to read 4, iclass 12, count 0 2006.285.05:21:41.08#ibcon#read 4, iclass 12, count 0 2006.285.05:21:41.08#ibcon#about to read 5, iclass 12, count 0 2006.285.05:21:41.08#ibcon#read 5, iclass 12, count 0 2006.285.05:21:41.08#ibcon#about to read 6, iclass 12, count 0 2006.285.05:21:41.08#ibcon#read 6, iclass 12, count 0 2006.285.05:21:41.08#ibcon#end of sib2, iclass 12, count 0 2006.285.05:21:41.08#ibcon#*after write, iclass 12, count 0 2006.285.05:21:41.08#ibcon#*before return 0, iclass 12, count 0 2006.285.05:21:41.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.05:21:41.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.05:21:41.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.05:21:41.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.05:21:41.08$vck44/vbbw=wide 2006.285.05:21:41.08#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.05:21:41.08#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.05:21:41.08#ibcon#ireg 8 cls_cnt 0 2006.285.05:21:41.08#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.05:21:41.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.05:21:41.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.05:21:41.15#ibcon#enter wrdev, iclass 14, count 0 2006.285.05:21:41.15#ibcon#first serial, iclass 14, count 0 2006.285.05:21:41.15#ibcon#enter sib2, iclass 14, count 0 2006.285.05:21:41.15#ibcon#flushed, iclass 14, count 0 2006.285.05:21:41.15#ibcon#about to write, iclass 14, count 0 2006.285.05:21:41.15#ibcon#wrote, iclass 14, count 0 2006.285.05:21:41.15#ibcon#about to read 3, iclass 14, count 0 2006.285.05:21:41.17#ibcon#read 3, iclass 14, count 0 2006.285.05:21:41.17#ibcon#about to read 4, iclass 14, count 0 2006.285.05:21:41.17#ibcon#read 4, iclass 14, count 0 2006.285.05:21:41.17#ibcon#about to read 5, iclass 14, count 0 2006.285.05:21:41.17#ibcon#read 5, iclass 14, count 0 2006.285.05:21:41.17#ibcon#about to read 6, iclass 14, count 0 2006.285.05:21:41.17#ibcon#read 6, iclass 14, count 0 2006.285.05:21:41.17#ibcon#end of sib2, iclass 14, count 0 2006.285.05:21:41.17#ibcon#*mode == 0, iclass 14, count 0 2006.285.05:21:41.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.05:21:41.17#ibcon#[27=BW32\r\n] 2006.285.05:21:41.17#ibcon#*before write, iclass 14, count 0 2006.285.05:21:41.17#ibcon#enter sib2, iclass 14, count 0 2006.285.05:21:41.17#ibcon#flushed, iclass 14, count 0 2006.285.05:21:41.17#ibcon#about to write, iclass 14, count 0 2006.285.05:21:41.17#ibcon#wrote, iclass 14, count 0 2006.285.05:21:41.17#ibcon#about to read 3, iclass 14, count 0 2006.285.05:21:41.20#ibcon#read 3, iclass 14, count 0 2006.285.05:21:41.20#ibcon#about to read 4, iclass 14, count 0 2006.285.05:21:41.20#ibcon#read 4, iclass 14, count 0 2006.285.05:21:41.20#ibcon#about to read 5, iclass 14, count 0 2006.285.05:21:41.20#ibcon#read 5, iclass 14, count 0 2006.285.05:21:41.20#ibcon#about to read 6, iclass 14, count 0 2006.285.05:21:41.20#ibcon#read 6, iclass 14, count 0 2006.285.05:21:41.20#ibcon#end of sib2, iclass 14, count 0 2006.285.05:21:41.20#ibcon#*after write, iclass 14, count 0 2006.285.05:21:41.20#ibcon#*before return 0, iclass 14, count 0 2006.285.05:21:41.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.05:21:41.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.05:21:41.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.05:21:41.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.05:21:41.20$setupk4/ifdk4 2006.285.05:21:41.20&ifdk4/lo= 2006.285.05:21:41.20&ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.05:21:41.20&ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.05:21:41.20&ifdk4/patch= 2006.285.05:21:41.20&ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.05:21:41.20&ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.05:21:41.20$ifdk4/lo= 2006.285.05:21:41.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.05:21:41.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.05:21:41.20$ifdk4/patch= 2006.285.05:21:41.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.05:21:41.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.05:21:41.20$setupk4/!*+20s 2006.285.05:21:41.21$exper_initi/proc_library 2006.285.05:21:41.21&proc_library/" jd0610 tsukub32 ts 2006.285.05:21:41.21&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.285.05:21:41.21&proc_library/"< k4-2/m4 rack >< k4-2 recorder 1> 2006.285.05:21:41.21$proc_library/" jd0610 tsukub32 ts 2006.285.05:21:41.21$proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.285.05:21:41.21$proc_library/"< k4-2/m4 rack >< k4-2 recorder 1> 2006.285.05:21:41.21$exper_initi/sched_initi 2006.285.05:21:41.21&sched_initi/startcheck 2006.285.05:21:41.21$sched_initi/startcheck 2006.285.05:21:41.21&startcheck/sy=check_fsrun.pl & 2006.285.05:21:41.21&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.285.05:21:41.21$startcheck/sy=check_fsrun.pl & 2006.285.05:21:41.25$startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.285.05:21:47.56#abcon#<5=/05 4.5 7.1 25.62 551013.8\r\n> 2006.285.05:21:47.58#abcon#{5=INTERFACE CLEAR} 2006.285.05:21:47.64#abcon#[5=S1D000X0/0*\r\n] 2006.285.05:21:54.48$setupk4/"tpicd 2006.285.05:21:54.48$setupk4/echo=off 2006.285.05:21:54.48$setupk4/xlog=off 2006.285.05:21:54.48:"ready=1 2006.285.05:21:54.48:setupk4=1 2006.285.05:21:54.48$setupk4/echo=on 2006.285.05:21:54.48$setupk4/pcalon 2006.285.05:21:54.48$pcalon/"no phase cal control is implemented here 2006.285.05:21:54.48$setupk4/"tpicd=stop 2006.285.05:21:54.48$setupk4/"rec=synch_on 2006.285.05:21:54.48$setupk4/"rec_mode=128 2006.285.05:21:54.48$setupk4/!* 2006.285.05:21:54.48$setupk4/recpk4 2006.285.05:21:54.48$recpk4/recpatch= 2006.285.05:21:54.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.05:21:54.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.05:21:54.49$setupk4/vck44 2006.285.05:21:54.49$vck44/valo=1,524.99 2006.285.05:21:54.49#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.05:21:54.49#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.05:21:54.49#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:54.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.05:21:54.49#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.05:21:54.49#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.05:21:54.49#ibcon#enter wrdev, iclass 4, count 0 2006.285.05:21:54.49#ibcon#first serial, iclass 4, count 0 2006.285.05:21:54.49#ibcon#enter sib2, iclass 4, count 0 2006.285.05:21:54.49#ibcon#flushed, iclass 4, count 0 2006.285.05:21:54.49#ibcon#about to write, iclass 4, count 0 2006.285.05:21:54.49#ibcon#wrote, iclass 4, count 0 2006.285.05:21:54.49#ibcon#about to read 3, iclass 4, count 0 2006.285.05:21:54.50#ibcon#read 3, iclass 4, count 0 2006.285.05:21:54.50#ibcon#about to read 4, iclass 4, count 0 2006.285.05:21:54.50#ibcon#read 4, iclass 4, count 0 2006.285.05:21:54.50#ibcon#about to read 5, iclass 4, count 0 2006.285.05:21:54.50#ibcon#read 5, iclass 4, count 0 2006.285.05:21:54.50#ibcon#about to read 6, iclass 4, count 0 2006.285.05:21:54.50#ibcon#read 6, iclass 4, count 0 2006.285.05:21:54.50#ibcon#end of sib2, iclass 4, count 0 2006.285.05:21:54.50#ibcon#*mode == 0, iclass 4, count 0 2006.285.05:21:54.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.05:21:54.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.05:21:54.50#ibcon#*before write, iclass 4, count 0 2006.285.05:21:54.50#ibcon#enter sib2, iclass 4, count 0 2006.285.05:21:54.50#ibcon#flushed, iclass 4, count 0 2006.285.05:21:54.50#ibcon#about to write, iclass 4, count 0 2006.285.05:21:54.50#ibcon#wrote, iclass 4, count 0 2006.285.05:21:54.50#ibcon#about to read 3, iclass 4, count 0 2006.285.05:21:54.54#ibcon#read 3, iclass 4, count 0 2006.285.05:21:54.54#ibcon#about to read 4, iclass 4, count 0 2006.285.05:21:54.54#ibcon#read 4, iclass 4, count 0 2006.285.05:21:54.54#ibcon#about to read 5, iclass 4, count 0 2006.285.05:21:54.54#ibcon#read 5, iclass 4, count 0 2006.285.05:21:54.54#ibcon#about to read 6, iclass 4, count 0 2006.285.05:21:54.54#ibcon#read 6, iclass 4, count 0 2006.285.05:21:54.54#ibcon#end of sib2, iclass 4, count 0 2006.285.05:21:54.54#ibcon#*after write, iclass 4, count 0 2006.285.05:21:54.54#ibcon#*before return 0, iclass 4, count 0 2006.285.05:21:54.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.05:21:54.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.05:21:54.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.05:21:54.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.05:21:54.54$vck44/va=1,7 2006.285.05:21:54.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.05:21:54.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.05:21:54.54#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:54.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:54.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:54.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:54.54#ibcon#enter wrdev, iclass 6, count 2 2006.285.05:21:54.54#ibcon#first serial, iclass 6, count 2 2006.285.05:21:54.54#ibcon#enter sib2, iclass 6, count 2 2006.285.05:21:54.54#ibcon#flushed, iclass 6, count 2 2006.285.05:21:54.54#ibcon#about to write, iclass 6, count 2 2006.285.05:21:54.54#ibcon#wrote, iclass 6, count 2 2006.285.05:21:54.54#ibcon#about to read 3, iclass 6, count 2 2006.285.05:21:54.56#ibcon#read 3, iclass 6, count 2 2006.285.05:21:54.56#ibcon#about to read 4, iclass 6, count 2 2006.285.05:21:54.56#ibcon#read 4, iclass 6, count 2 2006.285.05:21:54.56#ibcon#about to read 5, iclass 6, count 2 2006.285.05:21:54.56#ibcon#read 5, iclass 6, count 2 2006.285.05:21:54.56#ibcon#about to read 6, iclass 6, count 2 2006.285.05:21:54.56#ibcon#read 6, iclass 6, count 2 2006.285.05:21:54.56#ibcon#end of sib2, iclass 6, count 2 2006.285.05:21:54.56#ibcon#*mode == 0, iclass 6, count 2 2006.285.05:21:54.56#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.05:21:54.56#ibcon#[25=AT01-07\r\n] 2006.285.05:21:54.56#ibcon#*before write, iclass 6, count 2 2006.285.05:21:54.56#ibcon#enter sib2, iclass 6, count 2 2006.285.05:21:54.56#ibcon#flushed, iclass 6, count 2 2006.285.05:21:54.56#ibcon#about to write, iclass 6, count 2 2006.285.05:21:54.56#ibcon#wrote, iclass 6, count 2 2006.285.05:21:54.56#ibcon#about to read 3, iclass 6, count 2 2006.285.05:21:54.59#ibcon#read 3, iclass 6, count 2 2006.285.05:21:54.59#ibcon#about to read 4, iclass 6, count 2 2006.285.05:21:54.59#ibcon#read 4, iclass 6, count 2 2006.285.05:21:54.59#ibcon#about to read 5, iclass 6, count 2 2006.285.05:21:54.59#ibcon#read 5, iclass 6, count 2 2006.285.05:21:54.59#ibcon#about to read 6, iclass 6, count 2 2006.285.05:21:54.59#ibcon#read 6, iclass 6, count 2 2006.285.05:21:54.59#ibcon#end of sib2, iclass 6, count 2 2006.285.05:21:54.59#ibcon#*after write, iclass 6, count 2 2006.285.05:21:54.59#ibcon#*before return 0, iclass 6, count 2 2006.285.05:21:54.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:54.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:54.59#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.05:21:54.59#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:54.59#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.05:21:54.71#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.05:21:54.71#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.05:21:54.71#ibcon#enter wrdev, iclass 6, count 0 2006.285.05:21:54.71#ibcon#first serial, iclass 6, count 0 2006.285.05:21:54.71#ibcon#enter sib2, iclass 6, count 0 2006.285.05:21:54.71#ibcon#flushed, iclass 6, count 0 2006.285.05:21:54.71#ibcon#about to write, iclass 6, count 0 2006.285.05:21:54.71#ibcon#wrote, iclass 6, count 0 2006.285.05:21:54.71#ibcon#about to read 3, iclass 6, count 0 2006.285.05:21:54.73#ibcon#read 3, iclass 6, count 0 2006.285.05:21:54.73#ibcon#about to read 4, iclass 6, count 0 2006.285.05:21:54.73#ibcon#read 4, iclass 6, count 0 2006.285.05:21:54.73#ibcon#about to read 5, iclass 6, count 0 2006.285.05:21:54.73#ibcon#read 5, iclass 6, count 0 2006.285.05:21:54.73#ibcon#about to read 6, iclass 6, count 0 2006.285.05:21:54.73#ibcon#read 6, iclass 6, count 0 2006.285.05:21:54.73#ibcon#end of sib2, iclass 6, count 0 2006.285.05:21:54.73#ibcon#*mode == 0, iclass 6, count 0 2006.285.05:21:54.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.05:21:54.73#ibcon#[25=USB\r\n] 2006.285.05:21:54.73#ibcon#*before write, iclass 6, count 0 2006.285.05:21:54.73#ibcon#enter sib2, iclass 6, count 0 2006.285.05:21:54.73#ibcon#flushed, iclass 6, count 0 2006.285.05:21:54.73#ibcon#about to write, iclass 6, count 0 2006.285.05:21:54.73#ibcon#wrote, iclass 6, count 0 2006.285.05:21:54.73#ibcon#about to read 3, iclass 6, count 0 2006.285.05:21:54.76#ibcon#read 3, iclass 6, count 0 2006.285.05:21:54.76#ibcon#about to read 4, iclass 6, count 0 2006.285.05:21:54.76#ibcon#read 4, iclass 6, count 0 2006.285.05:21:54.76#ibcon#about to read 5, iclass 6, count 0 2006.285.05:21:54.76#ibcon#read 5, iclass 6, count 0 2006.285.05:21:54.76#ibcon#about to read 6, iclass 6, count 0 2006.285.05:21:54.76#ibcon#read 6, iclass 6, count 0 2006.285.05:21:54.76#ibcon#end of sib2, iclass 6, count 0 2006.285.05:21:54.76#ibcon#*after write, iclass 6, count 0 2006.285.05:21:54.76#ibcon#*before return 0, iclass 6, count 0 2006.285.05:21:54.76#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.05:21:54.76#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.05:21:54.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.05:21:54.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.05:21:54.76$vck44/valo=2,534.99 2006.285.05:21:54.76#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.05:21:54.76#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.05:21:54.76#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:54.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.05:21:54.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.05:21:54.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.05:21:54.76#ibcon#enter wrdev, iclass 10, count 0 2006.285.05:21:54.76#ibcon#first serial, iclass 10, count 0 2006.285.05:21:54.76#ibcon#enter sib2, iclass 10, count 0 2006.285.05:21:54.76#ibcon#flushed, iclass 10, count 0 2006.285.05:21:54.76#ibcon#about to write, iclass 10, count 0 2006.285.05:21:54.76#ibcon#wrote, iclass 10, count 0 2006.285.05:21:54.76#ibcon#about to read 3, iclass 10, count 0 2006.285.05:21:54.78#ibcon#read 3, iclass 10, count 0 2006.285.05:21:54.78#ibcon#about to read 4, iclass 10, count 0 2006.285.05:21:54.78#ibcon#read 4, iclass 10, count 0 2006.285.05:21:54.78#ibcon#about to read 5, iclass 10, count 0 2006.285.05:21:54.78#ibcon#read 5, iclass 10, count 0 2006.285.05:21:54.78#ibcon#about to read 6, iclass 10, count 0 2006.285.05:21:54.78#ibcon#read 6, iclass 10, count 0 2006.285.05:21:54.78#ibcon#end of sib2, iclass 10, count 0 2006.285.05:21:54.78#ibcon#*mode == 0, iclass 10, count 0 2006.285.05:21:54.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.05:21:54.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.05:21:54.78#ibcon#*before write, iclass 10, count 0 2006.285.05:21:54.78#ibcon#enter sib2, iclass 10, count 0 2006.285.05:21:54.78#ibcon#flushed, iclass 10, count 0 2006.285.05:21:54.78#ibcon#about to write, iclass 10, count 0 2006.285.05:21:54.78#ibcon#wrote, iclass 10, count 0 2006.285.05:21:54.78#ibcon#about to read 3, iclass 10, count 0 2006.285.05:21:54.82#ibcon#read 3, iclass 10, count 0 2006.285.05:21:54.82#ibcon#about to read 4, iclass 10, count 0 2006.285.05:21:54.82#ibcon#read 4, iclass 10, count 0 2006.285.05:21:54.82#ibcon#about to read 5, iclass 10, count 0 2006.285.05:21:54.82#ibcon#read 5, iclass 10, count 0 2006.285.05:21:54.82#ibcon#about to read 6, iclass 10, count 0 2006.285.05:21:54.82#ibcon#read 6, iclass 10, count 0 2006.285.05:21:54.82#ibcon#end of sib2, iclass 10, count 0 2006.285.05:21:54.82#ibcon#*after write, iclass 10, count 0 2006.285.05:21:54.82#ibcon#*before return 0, iclass 10, count 0 2006.285.05:21:54.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.05:21:54.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.05:21:54.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.05:21:54.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.05:21:54.82$vck44/va=2,6 2006.285.05:21:54.82#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.05:21:54.82#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.05:21:54.82#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:54.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.05:21:54.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.05:21:54.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.05:21:54.88#ibcon#enter wrdev, iclass 12, count 2 2006.285.05:21:54.88#ibcon#first serial, iclass 12, count 2 2006.285.05:21:54.88#ibcon#enter sib2, iclass 12, count 2 2006.285.05:21:54.88#ibcon#flushed, iclass 12, count 2 2006.285.05:21:54.88#ibcon#about to write, iclass 12, count 2 2006.285.05:21:54.88#ibcon#wrote, iclass 12, count 2 2006.285.05:21:54.88#ibcon#about to read 3, iclass 12, count 2 2006.285.05:21:54.90#ibcon#read 3, iclass 12, count 2 2006.285.05:21:54.90#ibcon#about to read 4, iclass 12, count 2 2006.285.05:21:54.90#ibcon#read 4, iclass 12, count 2 2006.285.05:21:54.90#ibcon#about to read 5, iclass 12, count 2 2006.285.05:21:54.90#ibcon#read 5, iclass 12, count 2 2006.285.05:21:54.90#ibcon#about to read 6, iclass 12, count 2 2006.285.05:21:54.90#ibcon#read 6, iclass 12, count 2 2006.285.05:21:54.90#ibcon#end of sib2, iclass 12, count 2 2006.285.05:21:54.90#ibcon#*mode == 0, iclass 12, count 2 2006.285.05:21:54.90#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.05:21:54.90#ibcon#[25=AT02-06\r\n] 2006.285.05:21:54.90#ibcon#*before write, iclass 12, count 2 2006.285.05:21:54.90#ibcon#enter sib2, iclass 12, count 2 2006.285.05:21:54.90#ibcon#flushed, iclass 12, count 2 2006.285.05:21:54.90#ibcon#about to write, iclass 12, count 2 2006.285.05:21:54.90#ibcon#wrote, iclass 12, count 2 2006.285.05:21:54.90#ibcon#about to read 3, iclass 12, count 2 2006.285.05:21:54.93#ibcon#read 3, iclass 12, count 2 2006.285.05:21:54.93#ibcon#about to read 4, iclass 12, count 2 2006.285.05:21:54.93#ibcon#read 4, iclass 12, count 2 2006.285.05:21:54.93#ibcon#about to read 5, iclass 12, count 2 2006.285.05:21:54.93#ibcon#read 5, iclass 12, count 2 2006.285.05:21:54.93#ibcon#about to read 6, iclass 12, count 2 2006.285.05:21:54.93#ibcon#read 6, iclass 12, count 2 2006.285.05:21:54.93#ibcon#end of sib2, iclass 12, count 2 2006.285.05:21:54.93#ibcon#*after write, iclass 12, count 2 2006.285.05:21:54.93#ibcon#*before return 0, iclass 12, count 2 2006.285.05:21:54.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.05:21:54.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.05:21:54.93#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.05:21:54.93#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:54.93#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.05:21:55.05#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.05:21:55.05#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.05:21:55.05#ibcon#enter wrdev, iclass 12, count 0 2006.285.05:21:55.05#ibcon#first serial, iclass 12, count 0 2006.285.05:21:55.05#ibcon#enter sib2, iclass 12, count 0 2006.285.05:21:55.05#ibcon#flushed, iclass 12, count 0 2006.285.05:21:55.05#ibcon#about to write, iclass 12, count 0 2006.285.05:21:55.05#ibcon#wrote, iclass 12, count 0 2006.285.05:21:55.05#ibcon#about to read 3, iclass 12, count 0 2006.285.05:21:55.07#ibcon#read 3, iclass 12, count 0 2006.285.05:21:55.07#ibcon#about to read 4, iclass 12, count 0 2006.285.05:21:55.07#ibcon#read 4, iclass 12, count 0 2006.285.05:21:55.07#ibcon#about to read 5, iclass 12, count 0 2006.285.05:21:55.07#ibcon#read 5, iclass 12, count 0 2006.285.05:21:55.07#ibcon#about to read 6, iclass 12, count 0 2006.285.05:21:55.07#ibcon#read 6, iclass 12, count 0 2006.285.05:21:55.07#ibcon#end of sib2, iclass 12, count 0 2006.285.05:21:55.07#ibcon#*mode == 0, iclass 12, count 0 2006.285.05:21:55.07#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.05:21:55.07#ibcon#[25=USB\r\n] 2006.285.05:21:55.07#ibcon#*before write, iclass 12, count 0 2006.285.05:21:55.07#ibcon#enter sib2, iclass 12, count 0 2006.285.05:21:55.07#ibcon#flushed, iclass 12, count 0 2006.285.05:21:55.07#ibcon#about to write, iclass 12, count 0 2006.285.05:21:55.07#ibcon#wrote, iclass 12, count 0 2006.285.05:21:55.07#ibcon#about to read 3, iclass 12, count 0 2006.285.05:21:55.10#ibcon#read 3, iclass 12, count 0 2006.285.05:21:55.10#ibcon#about to read 4, iclass 12, count 0 2006.285.05:21:55.10#ibcon#read 4, iclass 12, count 0 2006.285.05:21:55.10#ibcon#about to read 5, iclass 12, count 0 2006.285.05:21:55.10#ibcon#read 5, iclass 12, count 0 2006.285.05:21:55.10#ibcon#about to read 6, iclass 12, count 0 2006.285.05:21:55.10#ibcon#read 6, iclass 12, count 0 2006.285.05:21:55.10#ibcon#end of sib2, iclass 12, count 0 2006.285.05:21:55.10#ibcon#*after write, iclass 12, count 0 2006.285.05:21:55.10#ibcon#*before return 0, iclass 12, count 0 2006.285.05:21:55.10#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.05:21:55.10#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.05:21:55.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.05:21:55.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.05:21:55.10$vck44/valo=3,564.99 2006.285.05:21:55.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.05:21:55.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.05:21:55.10#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:55.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.05:21:55.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.05:21:55.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.05:21:55.10#ibcon#enter wrdev, iclass 14, count 0 2006.285.05:21:55.10#ibcon#first serial, iclass 14, count 0 2006.285.05:21:55.10#ibcon#enter sib2, iclass 14, count 0 2006.285.05:21:55.10#ibcon#flushed, iclass 14, count 0 2006.285.05:21:55.10#ibcon#about to write, iclass 14, count 0 2006.285.05:21:55.10#ibcon#wrote, iclass 14, count 0 2006.285.05:21:55.10#ibcon#about to read 3, iclass 14, count 0 2006.285.05:21:55.12#ibcon#read 3, iclass 14, count 0 2006.285.05:21:55.12#ibcon#about to read 4, iclass 14, count 0 2006.285.05:21:55.12#ibcon#read 4, iclass 14, count 0 2006.285.05:21:55.12#ibcon#about to read 5, iclass 14, count 0 2006.285.05:21:55.12#ibcon#read 5, iclass 14, count 0 2006.285.05:21:55.12#ibcon#about to read 6, iclass 14, count 0 2006.285.05:21:55.12#ibcon#read 6, iclass 14, count 0 2006.285.05:21:55.12#ibcon#end of sib2, iclass 14, count 0 2006.285.05:21:55.12#ibcon#*mode == 0, iclass 14, count 0 2006.285.05:21:55.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.05:21:55.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.05:21:55.12#ibcon#*before write, iclass 14, count 0 2006.285.05:21:55.12#ibcon#enter sib2, iclass 14, count 0 2006.285.05:21:55.12#ibcon#flushed, iclass 14, count 0 2006.285.05:21:55.12#ibcon#about to write, iclass 14, count 0 2006.285.05:21:55.12#ibcon#wrote, iclass 14, count 0 2006.285.05:21:55.12#ibcon#about to read 3, iclass 14, count 0 2006.285.05:21:55.16#ibcon#read 3, iclass 14, count 0 2006.285.05:21:55.16#ibcon#about to read 4, iclass 14, count 0 2006.285.05:21:55.16#ibcon#read 4, iclass 14, count 0 2006.285.05:21:55.16#ibcon#about to read 5, iclass 14, count 0 2006.285.05:21:55.16#ibcon#read 5, iclass 14, count 0 2006.285.05:21:55.16#ibcon#about to read 6, iclass 14, count 0 2006.285.05:21:55.16#ibcon#read 6, iclass 14, count 0 2006.285.05:21:55.16#ibcon#end of sib2, iclass 14, count 0 2006.285.05:21:55.16#ibcon#*after write, iclass 14, count 0 2006.285.05:21:55.16#ibcon#*before return 0, iclass 14, count 0 2006.285.05:21:55.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.05:21:55.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.05:21:55.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.05:21:55.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.05:21:55.16$vck44/va=3,7 2006.285.05:21:55.16#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.05:21:55.16#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.05:21:55.16#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:55.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:55.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:55.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:55.22#ibcon#enter wrdev, iclass 16, count 2 2006.285.05:21:55.22#ibcon#first serial, iclass 16, count 2 2006.285.05:21:55.22#ibcon#enter sib2, iclass 16, count 2 2006.285.05:21:55.22#ibcon#flushed, iclass 16, count 2 2006.285.05:21:55.22#ibcon#about to write, iclass 16, count 2 2006.285.05:21:55.22#ibcon#wrote, iclass 16, count 2 2006.285.05:21:55.22#ibcon#about to read 3, iclass 16, count 2 2006.285.05:21:55.24#ibcon#read 3, iclass 16, count 2 2006.285.05:21:55.24#ibcon#about to read 4, iclass 16, count 2 2006.285.05:21:55.24#ibcon#read 4, iclass 16, count 2 2006.285.05:21:55.24#ibcon#about to read 5, iclass 16, count 2 2006.285.05:21:55.24#ibcon#read 5, iclass 16, count 2 2006.285.05:21:55.24#ibcon#about to read 6, iclass 16, count 2 2006.285.05:21:55.24#ibcon#read 6, iclass 16, count 2 2006.285.05:21:55.24#ibcon#end of sib2, iclass 16, count 2 2006.285.05:21:55.24#ibcon#*mode == 0, iclass 16, count 2 2006.285.05:21:55.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.05:21:55.24#ibcon#[25=AT03-07\r\n] 2006.285.05:21:55.24#ibcon#*before write, iclass 16, count 2 2006.285.05:21:55.24#ibcon#enter sib2, iclass 16, count 2 2006.285.05:21:55.24#ibcon#flushed, iclass 16, count 2 2006.285.05:21:55.24#ibcon#about to write, iclass 16, count 2 2006.285.05:21:55.24#ibcon#wrote, iclass 16, count 2 2006.285.05:21:55.24#ibcon#about to read 3, iclass 16, count 2 2006.285.05:21:55.27#ibcon#read 3, iclass 16, count 2 2006.285.05:21:55.27#ibcon#about to read 4, iclass 16, count 2 2006.285.05:21:55.27#ibcon#read 4, iclass 16, count 2 2006.285.05:21:55.27#ibcon#about to read 5, iclass 16, count 2 2006.285.05:21:55.27#ibcon#read 5, iclass 16, count 2 2006.285.05:21:55.27#ibcon#about to read 6, iclass 16, count 2 2006.285.05:21:55.27#ibcon#read 6, iclass 16, count 2 2006.285.05:21:55.27#ibcon#end of sib2, iclass 16, count 2 2006.285.05:21:55.27#ibcon#*after write, iclass 16, count 2 2006.285.05:21:55.27#ibcon#*before return 0, iclass 16, count 2 2006.285.05:21:55.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:55.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:55.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.05:21:55.27#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:55.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.05:21:55.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.05:21:55.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.05:21:55.39#ibcon#enter wrdev, iclass 16, count 0 2006.285.05:21:55.39#ibcon#first serial, iclass 16, count 0 2006.285.05:21:55.39#ibcon#enter sib2, iclass 16, count 0 2006.285.05:21:55.39#ibcon#flushed, iclass 16, count 0 2006.285.05:21:55.39#ibcon#about to write, iclass 16, count 0 2006.285.05:21:55.39#ibcon#wrote, iclass 16, count 0 2006.285.05:21:55.39#ibcon#about to read 3, iclass 16, count 0 2006.285.05:21:55.41#ibcon#read 3, iclass 16, count 0 2006.285.05:21:55.41#ibcon#about to read 4, iclass 16, count 0 2006.285.05:21:55.41#ibcon#read 4, iclass 16, count 0 2006.285.05:21:55.41#ibcon#about to read 5, iclass 16, count 0 2006.285.05:21:55.41#ibcon#read 5, iclass 16, count 0 2006.285.05:21:55.41#ibcon#about to read 6, iclass 16, count 0 2006.285.05:21:55.41#ibcon#read 6, iclass 16, count 0 2006.285.05:21:55.41#ibcon#end of sib2, iclass 16, count 0 2006.285.05:21:55.41#ibcon#*mode == 0, iclass 16, count 0 2006.285.05:21:55.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.05:21:55.41#ibcon#[25=USB\r\n] 2006.285.05:21:55.41#ibcon#*before write, iclass 16, count 0 2006.285.05:21:55.41#ibcon#enter sib2, iclass 16, count 0 2006.285.05:21:55.41#ibcon#flushed, iclass 16, count 0 2006.285.05:21:55.41#ibcon#about to write, iclass 16, count 0 2006.285.05:21:55.41#ibcon#wrote, iclass 16, count 0 2006.285.05:21:55.41#ibcon#about to read 3, iclass 16, count 0 2006.285.05:21:55.44#ibcon#read 3, iclass 16, count 0 2006.285.05:21:55.44#ibcon#about to read 4, iclass 16, count 0 2006.285.05:21:55.44#ibcon#read 4, iclass 16, count 0 2006.285.05:21:55.44#ibcon#about to read 5, iclass 16, count 0 2006.285.05:21:55.44#ibcon#read 5, iclass 16, count 0 2006.285.05:21:55.44#ibcon#about to read 6, iclass 16, count 0 2006.285.05:21:55.44#ibcon#read 6, iclass 16, count 0 2006.285.05:21:55.44#ibcon#end of sib2, iclass 16, count 0 2006.285.05:21:55.44#ibcon#*after write, iclass 16, count 0 2006.285.05:21:55.44#ibcon#*before return 0, iclass 16, count 0 2006.285.05:21:55.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.05:21:55.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.05:21:55.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.05:21:55.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.05:21:55.44$vck44/valo=4,624.99 2006.285.05:21:55.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.05:21:55.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:55.44#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:55.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.05:21:55.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.05:21:55.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.05:21:55.44#ibcon#enter wrdev, iclass 18, count 0 2006.285.05:21:55.44#ibcon#first serial, iclass 18, count 0 2006.285.05:21:55.44#ibcon#enter sib2, iclass 18, count 0 2006.285.05:21:55.44#ibcon#flushed, iclass 18, count 0 2006.285.05:21:55.44#ibcon#about to write, iclass 18, count 0 2006.285.05:21:55.44#ibcon#wrote, iclass 18, count 0 2006.285.05:21:55.44#ibcon#about to read 3, iclass 18, count 0 2006.285.05:21:55.46#ibcon#read 3, iclass 18, count 0 2006.285.05:21:55.46#ibcon#about to read 4, iclass 18, count 0 2006.285.05:21:55.46#ibcon#read 4, iclass 18, count 0 2006.285.05:21:55.46#ibcon#about to read 5, iclass 18, count 0 2006.285.05:21:55.46#ibcon#read 5, iclass 18, count 0 2006.285.05:21:55.46#ibcon#about to read 6, iclass 18, count 0 2006.285.05:21:55.46#ibcon#read 6, iclass 18, count 0 2006.285.05:21:55.46#ibcon#end of sib2, iclass 18, count 0 2006.285.05:21:55.46#ibcon#*mode == 0, iclass 18, count 0 2006.285.05:21:55.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.05:21:55.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.05:21:55.46#ibcon#*before write, iclass 18, count 0 2006.285.05:21:55.46#ibcon#enter sib2, iclass 18, count 0 2006.285.05:21:55.46#ibcon#flushed, iclass 18, count 0 2006.285.05:21:55.46#ibcon#about to write, iclass 18, count 0 2006.285.05:21:55.46#ibcon#wrote, iclass 18, count 0 2006.285.05:21:55.46#ibcon#about to read 3, iclass 18, count 0 2006.285.05:21:55.50#ibcon#read 3, iclass 18, count 0 2006.285.05:21:55.50#ibcon#about to read 4, iclass 18, count 0 2006.285.05:21:55.50#ibcon#read 4, iclass 18, count 0 2006.285.05:21:55.50#ibcon#about to read 5, iclass 18, count 0 2006.285.05:21:55.50#ibcon#read 5, iclass 18, count 0 2006.285.05:21:55.50#ibcon#about to read 6, iclass 18, count 0 2006.285.05:21:55.50#ibcon#read 6, iclass 18, count 0 2006.285.05:21:55.50#ibcon#end of sib2, iclass 18, count 0 2006.285.05:21:55.50#ibcon#*after write, iclass 18, count 0 2006.285.05:21:55.50#ibcon#*before return 0, iclass 18, count 0 2006.285.05:21:55.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.05:21:55.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.05:21:55.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.05:21:55.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.05:21:55.50$vck44/va=4,6 2006.285.05:21:55.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.05:21:55.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.05:21:55.50#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:55.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:55.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:55.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:55.56#ibcon#enter wrdev, iclass 20, count 2 2006.285.05:21:55.56#ibcon#first serial, iclass 20, count 2 2006.285.05:21:55.56#ibcon#enter sib2, iclass 20, count 2 2006.285.05:21:55.56#ibcon#flushed, iclass 20, count 2 2006.285.05:21:55.56#ibcon#about to write, iclass 20, count 2 2006.285.05:21:55.56#ibcon#wrote, iclass 20, count 2 2006.285.05:21:55.56#ibcon#about to read 3, iclass 20, count 2 2006.285.05:21:55.58#ibcon#read 3, iclass 20, count 2 2006.285.05:21:55.58#ibcon#about to read 4, iclass 20, count 2 2006.285.05:21:55.58#ibcon#read 4, iclass 20, count 2 2006.285.05:21:55.58#ibcon#about to read 5, iclass 20, count 2 2006.285.05:21:55.58#ibcon#read 5, iclass 20, count 2 2006.285.05:21:55.58#ibcon#about to read 6, iclass 20, count 2 2006.285.05:21:55.58#ibcon#read 6, iclass 20, count 2 2006.285.05:21:55.58#ibcon#end of sib2, iclass 20, count 2 2006.285.05:21:55.58#ibcon#*mode == 0, iclass 20, count 2 2006.285.05:21:55.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.05:21:55.58#ibcon#[25=AT04-06\r\n] 2006.285.05:21:55.58#ibcon#*before write, iclass 20, count 2 2006.285.05:21:55.58#ibcon#enter sib2, iclass 20, count 2 2006.285.05:21:55.58#ibcon#flushed, iclass 20, count 2 2006.285.05:21:55.58#ibcon#about to write, iclass 20, count 2 2006.285.05:21:55.58#ibcon#wrote, iclass 20, count 2 2006.285.05:21:55.58#ibcon#about to read 3, iclass 20, count 2 2006.285.05:21:55.61#ibcon#read 3, iclass 20, count 2 2006.285.05:21:55.61#ibcon#about to read 4, iclass 20, count 2 2006.285.05:21:55.61#ibcon#read 4, iclass 20, count 2 2006.285.05:21:55.61#ibcon#about to read 5, iclass 20, count 2 2006.285.05:21:55.61#ibcon#read 5, iclass 20, count 2 2006.285.05:21:55.61#ibcon#about to read 6, iclass 20, count 2 2006.285.05:21:55.61#ibcon#read 6, iclass 20, count 2 2006.285.05:21:55.61#ibcon#end of sib2, iclass 20, count 2 2006.285.05:21:55.61#ibcon#*after write, iclass 20, count 2 2006.285.05:21:55.61#ibcon#*before return 0, iclass 20, count 2 2006.285.05:21:55.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:55.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:55.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.05:21:55.61#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:55.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.05:21:55.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.05:21:55.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.05:21:55.73#ibcon#enter wrdev, iclass 20, count 0 2006.285.05:21:55.73#ibcon#first serial, iclass 20, count 0 2006.285.05:21:55.73#ibcon#enter sib2, iclass 20, count 0 2006.285.05:21:55.73#ibcon#flushed, iclass 20, count 0 2006.285.05:21:55.73#ibcon#about to write, iclass 20, count 0 2006.285.05:21:55.73#ibcon#wrote, iclass 20, count 0 2006.285.05:21:55.73#ibcon#about to read 3, iclass 20, count 0 2006.285.05:21:55.75#ibcon#read 3, iclass 20, count 0 2006.285.05:21:55.75#ibcon#about to read 4, iclass 20, count 0 2006.285.05:21:55.75#ibcon#read 4, iclass 20, count 0 2006.285.05:21:55.75#ibcon#about to read 5, iclass 20, count 0 2006.285.05:21:55.75#ibcon#read 5, iclass 20, count 0 2006.285.05:21:55.75#ibcon#about to read 6, iclass 20, count 0 2006.285.05:21:55.75#ibcon#read 6, iclass 20, count 0 2006.285.05:21:55.75#ibcon#end of sib2, iclass 20, count 0 2006.285.05:21:55.75#ibcon#*mode == 0, iclass 20, count 0 2006.285.05:21:55.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.05:21:55.75#ibcon#[25=USB\r\n] 2006.285.05:21:55.75#ibcon#*before write, iclass 20, count 0 2006.285.05:21:55.75#ibcon#enter sib2, iclass 20, count 0 2006.285.05:21:55.75#ibcon#flushed, iclass 20, count 0 2006.285.05:21:55.75#ibcon#about to write, iclass 20, count 0 2006.285.05:21:55.75#ibcon#wrote, iclass 20, count 0 2006.285.05:21:55.75#ibcon#about to read 3, iclass 20, count 0 2006.285.05:21:55.78#ibcon#read 3, iclass 20, count 0 2006.285.05:21:55.78#ibcon#about to read 4, iclass 20, count 0 2006.285.05:21:55.78#ibcon#read 4, iclass 20, count 0 2006.285.05:21:55.78#ibcon#about to read 5, iclass 20, count 0 2006.285.05:21:55.78#ibcon#read 5, iclass 20, count 0 2006.285.05:21:55.78#ibcon#about to read 6, iclass 20, count 0 2006.285.05:21:55.78#ibcon#read 6, iclass 20, count 0 2006.285.05:21:55.78#ibcon#end of sib2, iclass 20, count 0 2006.285.05:21:55.78#ibcon#*after write, iclass 20, count 0 2006.285.05:21:55.78#ibcon#*before return 0, iclass 20, count 0 2006.285.05:21:55.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.05:21:55.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.05:21:55.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.05:21:55.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.05:21:55.78$vck44/valo=5,734.99 2006.285.05:21:55.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.05:21:55.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:55.78#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:55.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.05:21:55.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.05:21:55.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.05:21:55.78#ibcon#enter wrdev, iclass 22, count 0 2006.285.05:21:55.78#ibcon#first serial, iclass 22, count 0 2006.285.05:21:55.78#ibcon#enter sib2, iclass 22, count 0 2006.285.05:21:55.78#ibcon#flushed, iclass 22, count 0 2006.285.05:21:55.78#ibcon#about to write, iclass 22, count 0 2006.285.05:21:55.78#ibcon#wrote, iclass 22, count 0 2006.285.05:21:55.78#ibcon#about to read 3, iclass 22, count 0 2006.285.05:21:55.80#ibcon#read 3, iclass 22, count 0 2006.285.05:21:55.80#ibcon#about to read 4, iclass 22, count 0 2006.285.05:21:55.80#ibcon#read 4, iclass 22, count 0 2006.285.05:21:55.80#ibcon#about to read 5, iclass 22, count 0 2006.285.05:21:55.80#ibcon#read 5, iclass 22, count 0 2006.285.05:21:55.80#ibcon#about to read 6, iclass 22, count 0 2006.285.05:21:55.80#ibcon#read 6, iclass 22, count 0 2006.285.05:21:55.80#ibcon#end of sib2, iclass 22, count 0 2006.285.05:21:55.80#ibcon#*mode == 0, iclass 22, count 0 2006.285.05:21:55.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.05:21:55.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.05:21:55.80#ibcon#*before write, iclass 22, count 0 2006.285.05:21:55.80#ibcon#enter sib2, iclass 22, count 0 2006.285.05:21:55.80#ibcon#flushed, iclass 22, count 0 2006.285.05:21:55.80#ibcon#about to write, iclass 22, count 0 2006.285.05:21:55.80#ibcon#wrote, iclass 22, count 0 2006.285.05:21:55.80#ibcon#about to read 3, iclass 22, count 0 2006.285.05:21:55.84#ibcon#read 3, iclass 22, count 0 2006.285.05:21:55.84#ibcon#about to read 4, iclass 22, count 0 2006.285.05:21:55.84#ibcon#read 4, iclass 22, count 0 2006.285.05:21:55.84#ibcon#about to read 5, iclass 22, count 0 2006.285.05:21:55.84#ibcon#read 5, iclass 22, count 0 2006.285.05:21:55.84#ibcon#about to read 6, iclass 22, count 0 2006.285.05:21:55.84#ibcon#read 6, iclass 22, count 0 2006.285.05:21:55.84#ibcon#end of sib2, iclass 22, count 0 2006.285.05:21:55.84#ibcon#*after write, iclass 22, count 0 2006.285.05:21:55.84#ibcon#*before return 0, iclass 22, count 0 2006.285.05:21:55.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.05:21:55.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.05:21:55.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.05:21:55.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.05:21:55.84$vck44/va=5,3 2006.285.05:21:55.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.05:21:55.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.05:21:55.84#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:55.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:55.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:55.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:55.90#ibcon#enter wrdev, iclass 24, count 2 2006.285.05:21:55.90#ibcon#first serial, iclass 24, count 2 2006.285.05:21:55.90#ibcon#enter sib2, iclass 24, count 2 2006.285.05:21:55.90#ibcon#flushed, iclass 24, count 2 2006.285.05:21:55.90#ibcon#about to write, iclass 24, count 2 2006.285.05:21:55.90#ibcon#wrote, iclass 24, count 2 2006.285.05:21:55.90#ibcon#about to read 3, iclass 24, count 2 2006.285.05:21:55.92#ibcon#read 3, iclass 24, count 2 2006.285.05:21:55.92#ibcon#about to read 4, iclass 24, count 2 2006.285.05:21:55.92#ibcon#read 4, iclass 24, count 2 2006.285.05:21:55.92#ibcon#about to read 5, iclass 24, count 2 2006.285.05:21:55.92#ibcon#read 5, iclass 24, count 2 2006.285.05:21:55.92#ibcon#about to read 6, iclass 24, count 2 2006.285.05:21:55.92#ibcon#read 6, iclass 24, count 2 2006.285.05:21:55.92#ibcon#end of sib2, iclass 24, count 2 2006.285.05:21:55.92#ibcon#*mode == 0, iclass 24, count 2 2006.285.05:21:55.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.05:21:55.92#ibcon#[25=AT05-03\r\n] 2006.285.05:21:55.92#ibcon#*before write, iclass 24, count 2 2006.285.05:21:55.92#ibcon#enter sib2, iclass 24, count 2 2006.285.05:21:55.92#ibcon#flushed, iclass 24, count 2 2006.285.05:21:55.92#ibcon#about to write, iclass 24, count 2 2006.285.05:21:55.92#ibcon#wrote, iclass 24, count 2 2006.285.05:21:55.92#ibcon#about to read 3, iclass 24, count 2 2006.285.05:21:55.95#ibcon#read 3, iclass 24, count 2 2006.285.05:21:55.95#ibcon#about to read 4, iclass 24, count 2 2006.285.05:21:55.95#ibcon#read 4, iclass 24, count 2 2006.285.05:21:55.95#ibcon#about to read 5, iclass 24, count 2 2006.285.05:21:55.95#ibcon#read 5, iclass 24, count 2 2006.285.05:21:55.95#ibcon#about to read 6, iclass 24, count 2 2006.285.05:21:55.95#ibcon#read 6, iclass 24, count 2 2006.285.05:21:55.95#ibcon#end of sib2, iclass 24, count 2 2006.285.05:21:55.95#ibcon#*after write, iclass 24, count 2 2006.285.05:21:55.95#ibcon#*before return 0, iclass 24, count 2 2006.285.05:21:55.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:55.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:55.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.05:21:55.95#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:55.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.05:21:56.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.05:21:56.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.05:21:56.07#ibcon#enter wrdev, iclass 24, count 0 2006.285.05:21:56.07#ibcon#first serial, iclass 24, count 0 2006.285.05:21:56.07#ibcon#enter sib2, iclass 24, count 0 2006.285.05:21:56.07#ibcon#flushed, iclass 24, count 0 2006.285.05:21:56.07#ibcon#about to write, iclass 24, count 0 2006.285.05:21:56.07#ibcon#wrote, iclass 24, count 0 2006.285.05:21:56.07#ibcon#about to read 3, iclass 24, count 0 2006.285.05:21:56.09#ibcon#read 3, iclass 24, count 0 2006.285.05:21:56.09#ibcon#about to read 4, iclass 24, count 0 2006.285.05:21:56.09#ibcon#read 4, iclass 24, count 0 2006.285.05:21:56.09#ibcon#about to read 5, iclass 24, count 0 2006.285.05:21:56.09#ibcon#read 5, iclass 24, count 0 2006.285.05:21:56.09#ibcon#about to read 6, iclass 24, count 0 2006.285.05:21:56.09#ibcon#read 6, iclass 24, count 0 2006.285.05:21:56.09#ibcon#end of sib2, iclass 24, count 0 2006.285.05:21:56.09#ibcon#*mode == 0, iclass 24, count 0 2006.285.05:21:56.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.05:21:56.09#ibcon#[25=USB\r\n] 2006.285.05:21:56.09#ibcon#*before write, iclass 24, count 0 2006.285.05:21:56.09#ibcon#enter sib2, iclass 24, count 0 2006.285.05:21:56.09#ibcon#flushed, iclass 24, count 0 2006.285.05:21:56.09#ibcon#about to write, iclass 24, count 0 2006.285.05:21:56.09#ibcon#wrote, iclass 24, count 0 2006.285.05:21:56.09#ibcon#about to read 3, iclass 24, count 0 2006.285.05:21:56.12#ibcon#read 3, iclass 24, count 0 2006.285.05:21:56.12#ibcon#about to read 4, iclass 24, count 0 2006.285.05:21:56.12#ibcon#read 4, iclass 24, count 0 2006.285.05:21:56.12#ibcon#about to read 5, iclass 24, count 0 2006.285.05:21:56.12#ibcon#read 5, iclass 24, count 0 2006.285.05:21:56.12#ibcon#about to read 6, iclass 24, count 0 2006.285.05:21:56.12#ibcon#read 6, iclass 24, count 0 2006.285.05:21:56.12#ibcon#end of sib2, iclass 24, count 0 2006.285.05:21:56.12#ibcon#*after write, iclass 24, count 0 2006.285.05:21:56.12#ibcon#*before return 0, iclass 24, count 0 2006.285.05:21:56.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.05:21:56.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.05:21:56.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.05:21:56.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.05:21:56.12$vck44/valo=6,814.99 2006.285.05:21:56.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.05:21:56.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:56.12#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:56.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.05:21:56.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.05:21:56.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.05:21:56.12#ibcon#enter wrdev, iclass 26, count 0 2006.285.05:21:56.12#ibcon#first serial, iclass 26, count 0 2006.285.05:21:56.12#ibcon#enter sib2, iclass 26, count 0 2006.285.05:21:56.12#ibcon#flushed, iclass 26, count 0 2006.285.05:21:56.12#ibcon#about to write, iclass 26, count 0 2006.285.05:21:56.12#ibcon#wrote, iclass 26, count 0 2006.285.05:21:56.12#ibcon#about to read 3, iclass 26, count 0 2006.285.05:21:56.14#ibcon#read 3, iclass 26, count 0 2006.285.05:21:56.14#ibcon#about to read 4, iclass 26, count 0 2006.285.05:21:56.14#ibcon#read 4, iclass 26, count 0 2006.285.05:21:56.14#ibcon#about to read 5, iclass 26, count 0 2006.285.05:21:56.14#ibcon#read 5, iclass 26, count 0 2006.285.05:21:56.14#ibcon#about to read 6, iclass 26, count 0 2006.285.05:21:56.14#ibcon#read 6, iclass 26, count 0 2006.285.05:21:56.14#ibcon#end of sib2, iclass 26, count 0 2006.285.05:21:56.14#ibcon#*mode == 0, iclass 26, count 0 2006.285.05:21:56.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.05:21:56.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.05:21:56.14#ibcon#*before write, iclass 26, count 0 2006.285.05:21:56.14#ibcon#enter sib2, iclass 26, count 0 2006.285.05:21:56.14#ibcon#flushed, iclass 26, count 0 2006.285.05:21:56.14#ibcon#about to write, iclass 26, count 0 2006.285.05:21:56.14#ibcon#wrote, iclass 26, count 0 2006.285.05:21:56.14#ibcon#about to read 3, iclass 26, count 0 2006.285.05:21:56.18#ibcon#read 3, iclass 26, count 0 2006.285.05:21:56.18#ibcon#about to read 4, iclass 26, count 0 2006.285.05:21:56.18#ibcon#read 4, iclass 26, count 0 2006.285.05:21:56.18#ibcon#about to read 5, iclass 26, count 0 2006.285.05:21:56.18#ibcon#read 5, iclass 26, count 0 2006.285.05:21:56.18#ibcon#about to read 6, iclass 26, count 0 2006.285.05:21:56.18#ibcon#read 6, iclass 26, count 0 2006.285.05:21:56.18#ibcon#end of sib2, iclass 26, count 0 2006.285.05:21:56.18#ibcon#*after write, iclass 26, count 0 2006.285.05:21:56.18#ibcon#*before return 0, iclass 26, count 0 2006.285.05:21:56.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.05:21:56.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.05:21:56.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.05:21:56.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.05:21:56.18$vck44/va=6,4 2006.285.05:21:56.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.05:21:56.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.05:21:56.18#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:56.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:56.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:56.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:56.24#ibcon#enter wrdev, iclass 28, count 2 2006.285.05:21:56.24#ibcon#first serial, iclass 28, count 2 2006.285.05:21:56.24#ibcon#enter sib2, iclass 28, count 2 2006.285.05:21:56.24#ibcon#flushed, iclass 28, count 2 2006.285.05:21:56.24#ibcon#about to write, iclass 28, count 2 2006.285.05:21:56.24#ibcon#wrote, iclass 28, count 2 2006.285.05:21:56.24#ibcon#about to read 3, iclass 28, count 2 2006.285.05:21:56.26#ibcon#read 3, iclass 28, count 2 2006.285.05:21:56.26#ibcon#about to read 4, iclass 28, count 2 2006.285.05:21:56.26#ibcon#read 4, iclass 28, count 2 2006.285.05:21:56.26#ibcon#about to read 5, iclass 28, count 2 2006.285.05:21:56.26#ibcon#read 5, iclass 28, count 2 2006.285.05:21:56.26#ibcon#about to read 6, iclass 28, count 2 2006.285.05:21:56.26#ibcon#read 6, iclass 28, count 2 2006.285.05:21:56.26#ibcon#end of sib2, iclass 28, count 2 2006.285.05:21:56.26#ibcon#*mode == 0, iclass 28, count 2 2006.285.05:21:56.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.05:21:56.26#ibcon#[25=AT06-04\r\n] 2006.285.05:21:56.26#ibcon#*before write, iclass 28, count 2 2006.285.05:21:56.26#ibcon#enter sib2, iclass 28, count 2 2006.285.05:21:56.26#ibcon#flushed, iclass 28, count 2 2006.285.05:21:56.26#ibcon#about to write, iclass 28, count 2 2006.285.05:21:56.26#ibcon#wrote, iclass 28, count 2 2006.285.05:21:56.26#ibcon#about to read 3, iclass 28, count 2 2006.285.05:21:56.29#ibcon#read 3, iclass 28, count 2 2006.285.05:21:56.29#ibcon#about to read 4, iclass 28, count 2 2006.285.05:21:56.29#ibcon#read 4, iclass 28, count 2 2006.285.05:21:56.29#ibcon#about to read 5, iclass 28, count 2 2006.285.05:21:56.29#ibcon#read 5, iclass 28, count 2 2006.285.05:21:56.29#ibcon#about to read 6, iclass 28, count 2 2006.285.05:21:56.29#ibcon#read 6, iclass 28, count 2 2006.285.05:21:56.29#ibcon#end of sib2, iclass 28, count 2 2006.285.05:21:56.29#ibcon#*after write, iclass 28, count 2 2006.285.05:21:56.29#ibcon#*before return 0, iclass 28, count 2 2006.285.05:21:56.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:56.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:56.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.05:21:56.29#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:56.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.05:21:56.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.05:21:56.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.05:21:56.41#ibcon#enter wrdev, iclass 28, count 0 2006.285.05:21:56.41#ibcon#first serial, iclass 28, count 0 2006.285.05:21:56.41#ibcon#enter sib2, iclass 28, count 0 2006.285.05:21:56.41#ibcon#flushed, iclass 28, count 0 2006.285.05:21:56.41#ibcon#about to write, iclass 28, count 0 2006.285.05:21:56.41#ibcon#wrote, iclass 28, count 0 2006.285.05:21:56.41#ibcon#about to read 3, iclass 28, count 0 2006.285.05:21:56.43#ibcon#read 3, iclass 28, count 0 2006.285.05:21:56.43#ibcon#about to read 4, iclass 28, count 0 2006.285.05:21:56.43#ibcon#read 4, iclass 28, count 0 2006.285.05:21:56.43#ibcon#about to read 5, iclass 28, count 0 2006.285.05:21:56.43#ibcon#read 5, iclass 28, count 0 2006.285.05:21:56.43#ibcon#about to read 6, iclass 28, count 0 2006.285.05:21:56.43#ibcon#read 6, iclass 28, count 0 2006.285.05:21:56.43#ibcon#end of sib2, iclass 28, count 0 2006.285.05:21:56.43#ibcon#*mode == 0, iclass 28, count 0 2006.285.05:21:56.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.05:21:56.43#ibcon#[25=USB\r\n] 2006.285.05:21:56.43#ibcon#*before write, iclass 28, count 0 2006.285.05:21:56.43#ibcon#enter sib2, iclass 28, count 0 2006.285.05:21:56.43#ibcon#flushed, iclass 28, count 0 2006.285.05:21:56.43#ibcon#about to write, iclass 28, count 0 2006.285.05:21:56.43#ibcon#wrote, iclass 28, count 0 2006.285.05:21:56.43#ibcon#about to read 3, iclass 28, count 0 2006.285.05:21:56.46#ibcon#read 3, iclass 28, count 0 2006.285.05:21:56.46#ibcon#about to read 4, iclass 28, count 0 2006.285.05:21:56.46#ibcon#read 4, iclass 28, count 0 2006.285.05:21:56.46#ibcon#about to read 5, iclass 28, count 0 2006.285.05:21:56.46#ibcon#read 5, iclass 28, count 0 2006.285.05:21:56.46#ibcon#about to read 6, iclass 28, count 0 2006.285.05:21:56.46#ibcon#read 6, iclass 28, count 0 2006.285.05:21:56.46#ibcon#end of sib2, iclass 28, count 0 2006.285.05:21:56.46#ibcon#*after write, iclass 28, count 0 2006.285.05:21:56.46#ibcon#*before return 0, iclass 28, count 0 2006.285.05:21:56.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.05:21:56.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.05:21:56.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.05:21:56.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.05:21:56.46$vck44/valo=7,864.99 2006.285.05:21:56.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.05:21:56.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:56.46#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:56.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.05:21:56.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.05:21:56.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.05:21:56.46#ibcon#enter wrdev, iclass 30, count 0 2006.285.05:21:56.46#ibcon#first serial, iclass 30, count 0 2006.285.05:21:56.46#ibcon#enter sib2, iclass 30, count 0 2006.285.05:21:56.46#ibcon#flushed, iclass 30, count 0 2006.285.05:21:56.46#ibcon#about to write, iclass 30, count 0 2006.285.05:21:56.46#ibcon#wrote, iclass 30, count 0 2006.285.05:21:56.46#ibcon#about to read 3, iclass 30, count 0 2006.285.05:21:56.48#ibcon#read 3, iclass 30, count 0 2006.285.05:21:56.48#ibcon#about to read 4, iclass 30, count 0 2006.285.05:21:56.48#ibcon#read 4, iclass 30, count 0 2006.285.05:21:56.48#ibcon#about to read 5, iclass 30, count 0 2006.285.05:21:56.48#ibcon#read 5, iclass 30, count 0 2006.285.05:21:56.48#ibcon#about to read 6, iclass 30, count 0 2006.285.05:21:56.48#ibcon#read 6, iclass 30, count 0 2006.285.05:21:56.48#ibcon#end of sib2, iclass 30, count 0 2006.285.05:21:56.48#ibcon#*mode == 0, iclass 30, count 0 2006.285.05:21:56.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.05:21:56.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.05:21:56.48#ibcon#*before write, iclass 30, count 0 2006.285.05:21:56.48#ibcon#enter sib2, iclass 30, count 0 2006.285.05:21:56.48#ibcon#flushed, iclass 30, count 0 2006.285.05:21:56.48#ibcon#about to write, iclass 30, count 0 2006.285.05:21:56.48#ibcon#wrote, iclass 30, count 0 2006.285.05:21:56.48#ibcon#about to read 3, iclass 30, count 0 2006.285.05:21:56.52#ibcon#read 3, iclass 30, count 0 2006.285.05:21:56.52#ibcon#about to read 4, iclass 30, count 0 2006.285.05:21:56.52#ibcon#read 4, iclass 30, count 0 2006.285.05:21:56.52#ibcon#about to read 5, iclass 30, count 0 2006.285.05:21:56.52#ibcon#read 5, iclass 30, count 0 2006.285.05:21:56.52#ibcon#about to read 6, iclass 30, count 0 2006.285.05:21:56.52#ibcon#read 6, iclass 30, count 0 2006.285.05:21:56.52#ibcon#end of sib2, iclass 30, count 0 2006.285.05:21:56.52#ibcon#*after write, iclass 30, count 0 2006.285.05:21:56.52#ibcon#*before return 0, iclass 30, count 0 2006.285.05:21:56.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.05:21:56.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.05:21:56.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.05:21:56.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.05:21:56.52$vck44/va=7,4 2006.285.05:21:56.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.05:21:56.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.05:21:56.52#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:56.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:56.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:56.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:56.58#ibcon#enter wrdev, iclass 32, count 2 2006.285.05:21:56.58#ibcon#first serial, iclass 32, count 2 2006.285.05:21:56.58#ibcon#enter sib2, iclass 32, count 2 2006.285.05:21:56.58#ibcon#flushed, iclass 32, count 2 2006.285.05:21:56.58#ibcon#about to write, iclass 32, count 2 2006.285.05:21:56.58#ibcon#wrote, iclass 32, count 2 2006.285.05:21:56.58#ibcon#about to read 3, iclass 32, count 2 2006.285.05:21:56.60#ibcon#read 3, iclass 32, count 2 2006.285.05:21:56.60#ibcon#about to read 4, iclass 32, count 2 2006.285.05:21:56.60#ibcon#read 4, iclass 32, count 2 2006.285.05:21:56.60#ibcon#about to read 5, iclass 32, count 2 2006.285.05:21:56.60#ibcon#read 5, iclass 32, count 2 2006.285.05:21:56.60#ibcon#about to read 6, iclass 32, count 2 2006.285.05:21:56.60#ibcon#read 6, iclass 32, count 2 2006.285.05:21:56.60#ibcon#end of sib2, iclass 32, count 2 2006.285.05:21:56.60#ibcon#*mode == 0, iclass 32, count 2 2006.285.05:21:56.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.05:21:56.60#ibcon#[25=AT07-04\r\n] 2006.285.05:21:56.60#ibcon#*before write, iclass 32, count 2 2006.285.05:21:56.60#ibcon#enter sib2, iclass 32, count 2 2006.285.05:21:56.60#ibcon#flushed, iclass 32, count 2 2006.285.05:21:56.60#ibcon#about to write, iclass 32, count 2 2006.285.05:21:56.60#ibcon#wrote, iclass 32, count 2 2006.285.05:21:56.60#ibcon#about to read 3, iclass 32, count 2 2006.285.05:21:56.63#ibcon#read 3, iclass 32, count 2 2006.285.05:21:56.63#ibcon#about to read 4, iclass 32, count 2 2006.285.05:21:56.63#ibcon#read 4, iclass 32, count 2 2006.285.05:21:56.63#ibcon#about to read 5, iclass 32, count 2 2006.285.05:21:56.63#ibcon#read 5, iclass 32, count 2 2006.285.05:21:56.63#ibcon#about to read 6, iclass 32, count 2 2006.285.05:21:56.63#ibcon#read 6, iclass 32, count 2 2006.285.05:21:56.63#ibcon#end of sib2, iclass 32, count 2 2006.285.05:21:56.63#ibcon#*after write, iclass 32, count 2 2006.285.05:21:56.63#ibcon#*before return 0, iclass 32, count 2 2006.285.05:21:56.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:56.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:56.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.05:21:56.63#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:56.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.05:21:56.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.05:21:56.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.05:21:56.75#ibcon#enter wrdev, iclass 32, count 0 2006.285.05:21:56.75#ibcon#first serial, iclass 32, count 0 2006.285.05:21:56.75#ibcon#enter sib2, iclass 32, count 0 2006.285.05:21:56.75#ibcon#flushed, iclass 32, count 0 2006.285.05:21:56.75#ibcon#about to write, iclass 32, count 0 2006.285.05:21:56.75#ibcon#wrote, iclass 32, count 0 2006.285.05:21:56.75#ibcon#about to read 3, iclass 32, count 0 2006.285.05:21:56.77#ibcon#read 3, iclass 32, count 0 2006.285.05:21:56.77#ibcon#about to read 4, iclass 32, count 0 2006.285.05:21:56.77#ibcon#read 4, iclass 32, count 0 2006.285.05:21:56.77#ibcon#about to read 5, iclass 32, count 0 2006.285.05:21:56.77#ibcon#read 5, iclass 32, count 0 2006.285.05:21:56.77#ibcon#about to read 6, iclass 32, count 0 2006.285.05:21:56.77#ibcon#read 6, iclass 32, count 0 2006.285.05:21:56.77#ibcon#end of sib2, iclass 32, count 0 2006.285.05:21:56.77#ibcon#*mode == 0, iclass 32, count 0 2006.285.05:21:56.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.05:21:56.77#ibcon#[25=USB\r\n] 2006.285.05:21:56.77#ibcon#*before write, iclass 32, count 0 2006.285.05:21:56.77#ibcon#enter sib2, iclass 32, count 0 2006.285.05:21:56.77#ibcon#flushed, iclass 32, count 0 2006.285.05:21:56.77#ibcon#about to write, iclass 32, count 0 2006.285.05:21:56.77#ibcon#wrote, iclass 32, count 0 2006.285.05:21:56.77#ibcon#about to read 3, iclass 32, count 0 2006.285.05:21:56.80#ibcon#read 3, iclass 32, count 0 2006.285.05:21:56.80#ibcon#about to read 4, iclass 32, count 0 2006.285.05:21:56.80#ibcon#read 4, iclass 32, count 0 2006.285.05:21:56.80#ibcon#about to read 5, iclass 32, count 0 2006.285.05:21:56.80#ibcon#read 5, iclass 32, count 0 2006.285.05:21:56.80#ibcon#about to read 6, iclass 32, count 0 2006.285.05:21:56.80#ibcon#read 6, iclass 32, count 0 2006.285.05:21:56.80#ibcon#end of sib2, iclass 32, count 0 2006.285.05:21:56.80#ibcon#*after write, iclass 32, count 0 2006.285.05:21:56.80#ibcon#*before return 0, iclass 32, count 0 2006.285.05:21:56.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.05:21:56.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.05:21:56.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.05:21:56.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.05:21:56.80$vck44/valo=8,884.99 2006.285.05:21:56.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.05:21:56.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:56.80#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:56.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.05:21:56.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.05:21:56.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.05:21:56.80#ibcon#enter wrdev, iclass 34, count 0 2006.285.05:21:56.80#ibcon#first serial, iclass 34, count 0 2006.285.05:21:56.80#ibcon#enter sib2, iclass 34, count 0 2006.285.05:21:56.80#ibcon#flushed, iclass 34, count 0 2006.285.05:21:56.80#ibcon#about to write, iclass 34, count 0 2006.285.05:21:56.80#ibcon#wrote, iclass 34, count 0 2006.285.05:21:56.80#ibcon#about to read 3, iclass 34, count 0 2006.285.05:21:56.82#ibcon#read 3, iclass 34, count 0 2006.285.05:21:56.82#ibcon#about to read 4, iclass 34, count 0 2006.285.05:21:56.82#ibcon#read 4, iclass 34, count 0 2006.285.05:21:56.82#ibcon#about to read 5, iclass 34, count 0 2006.285.05:21:56.82#ibcon#read 5, iclass 34, count 0 2006.285.05:21:56.82#ibcon#about to read 6, iclass 34, count 0 2006.285.05:21:56.82#ibcon#read 6, iclass 34, count 0 2006.285.05:21:56.82#ibcon#end of sib2, iclass 34, count 0 2006.285.05:21:56.82#ibcon#*mode == 0, iclass 34, count 0 2006.285.05:21:56.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.05:21:56.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.05:21:56.82#ibcon#*before write, iclass 34, count 0 2006.285.05:21:56.82#ibcon#enter sib2, iclass 34, count 0 2006.285.05:21:56.82#ibcon#flushed, iclass 34, count 0 2006.285.05:21:56.82#ibcon#about to write, iclass 34, count 0 2006.285.05:21:56.82#ibcon#wrote, iclass 34, count 0 2006.285.05:21:56.82#ibcon#about to read 3, iclass 34, count 0 2006.285.05:21:56.86#ibcon#read 3, iclass 34, count 0 2006.285.05:21:56.86#ibcon#about to read 4, iclass 34, count 0 2006.285.05:21:56.86#ibcon#read 4, iclass 34, count 0 2006.285.05:21:56.86#ibcon#about to read 5, iclass 34, count 0 2006.285.05:21:56.86#ibcon#read 5, iclass 34, count 0 2006.285.05:21:56.86#ibcon#about to read 6, iclass 34, count 0 2006.285.05:21:56.86#ibcon#read 6, iclass 34, count 0 2006.285.05:21:56.86#ibcon#end of sib2, iclass 34, count 0 2006.285.05:21:56.86#ibcon#*after write, iclass 34, count 0 2006.285.05:21:56.86#ibcon#*before return 0, iclass 34, count 0 2006.285.05:21:56.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.05:21:56.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.05:21:56.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.05:21:56.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.05:21:56.86$vck44/va=8,3 2006.285.05:21:56.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.05:21:56.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.05:21:56.86#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:56.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:56.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:56.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:56.92#ibcon#enter wrdev, iclass 36, count 2 2006.285.05:21:56.92#ibcon#first serial, iclass 36, count 2 2006.285.05:21:56.92#ibcon#enter sib2, iclass 36, count 2 2006.285.05:21:56.92#ibcon#flushed, iclass 36, count 2 2006.285.05:21:56.92#ibcon#about to write, iclass 36, count 2 2006.285.05:21:56.92#ibcon#wrote, iclass 36, count 2 2006.285.05:21:56.92#ibcon#about to read 3, iclass 36, count 2 2006.285.05:21:56.94#ibcon#read 3, iclass 36, count 2 2006.285.05:21:56.94#ibcon#about to read 4, iclass 36, count 2 2006.285.05:21:56.94#ibcon#read 4, iclass 36, count 2 2006.285.05:21:56.94#ibcon#about to read 5, iclass 36, count 2 2006.285.05:21:56.94#ibcon#read 5, iclass 36, count 2 2006.285.05:21:56.94#ibcon#about to read 6, iclass 36, count 2 2006.285.05:21:56.94#ibcon#read 6, iclass 36, count 2 2006.285.05:21:56.94#ibcon#end of sib2, iclass 36, count 2 2006.285.05:21:56.94#ibcon#*mode == 0, iclass 36, count 2 2006.285.05:21:56.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.05:21:56.94#ibcon#[25=AT08-03\r\n] 2006.285.05:21:56.94#ibcon#*before write, iclass 36, count 2 2006.285.05:21:56.94#ibcon#enter sib2, iclass 36, count 2 2006.285.05:21:56.94#ibcon#flushed, iclass 36, count 2 2006.285.05:21:56.94#ibcon#about to write, iclass 36, count 2 2006.285.05:21:56.94#ibcon#wrote, iclass 36, count 2 2006.285.05:21:56.94#ibcon#about to read 3, iclass 36, count 2 2006.285.05:21:56.97#ibcon#read 3, iclass 36, count 2 2006.285.05:21:56.97#ibcon#about to read 4, iclass 36, count 2 2006.285.05:21:56.97#ibcon#read 4, iclass 36, count 2 2006.285.05:21:56.97#ibcon#about to read 5, iclass 36, count 2 2006.285.05:21:56.97#ibcon#read 5, iclass 36, count 2 2006.285.05:21:56.97#ibcon#about to read 6, iclass 36, count 2 2006.285.05:21:56.97#ibcon#read 6, iclass 36, count 2 2006.285.05:21:56.97#ibcon#end of sib2, iclass 36, count 2 2006.285.05:21:56.97#ibcon#*after write, iclass 36, count 2 2006.285.05:21:56.97#ibcon#*before return 0, iclass 36, count 2 2006.285.05:21:56.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:56.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:56.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.05:21:56.97#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:56.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.05:21:57.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.05:21:57.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.05:21:57.09#ibcon#enter wrdev, iclass 36, count 0 2006.285.05:21:57.09#ibcon#first serial, iclass 36, count 0 2006.285.05:21:57.09#ibcon#enter sib2, iclass 36, count 0 2006.285.05:21:57.09#ibcon#flushed, iclass 36, count 0 2006.285.05:21:57.09#ibcon#about to write, iclass 36, count 0 2006.285.05:21:57.09#ibcon#wrote, iclass 36, count 0 2006.285.05:21:57.09#ibcon#about to read 3, iclass 36, count 0 2006.285.05:21:57.11#ibcon#read 3, iclass 36, count 0 2006.285.05:21:57.11#ibcon#about to read 4, iclass 36, count 0 2006.285.05:21:57.11#ibcon#read 4, iclass 36, count 0 2006.285.05:21:57.11#ibcon#about to read 5, iclass 36, count 0 2006.285.05:21:57.11#ibcon#read 5, iclass 36, count 0 2006.285.05:21:57.11#ibcon#about to read 6, iclass 36, count 0 2006.285.05:21:57.11#ibcon#read 6, iclass 36, count 0 2006.285.05:21:57.11#ibcon#end of sib2, iclass 36, count 0 2006.285.05:21:57.11#ibcon#*mode == 0, iclass 36, count 0 2006.285.05:21:57.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.05:21:57.11#ibcon#[25=USB\r\n] 2006.285.05:21:57.11#ibcon#*before write, iclass 36, count 0 2006.285.05:21:57.11#ibcon#enter sib2, iclass 36, count 0 2006.285.05:21:57.11#ibcon#flushed, iclass 36, count 0 2006.285.05:21:57.11#ibcon#about to write, iclass 36, count 0 2006.285.05:21:57.11#ibcon#wrote, iclass 36, count 0 2006.285.05:21:57.11#ibcon#about to read 3, iclass 36, count 0 2006.285.05:21:57.14#ibcon#read 3, iclass 36, count 0 2006.285.05:21:57.14#ibcon#about to read 4, iclass 36, count 0 2006.285.05:21:57.14#ibcon#read 4, iclass 36, count 0 2006.285.05:21:57.14#ibcon#about to read 5, iclass 36, count 0 2006.285.05:21:57.14#ibcon#read 5, iclass 36, count 0 2006.285.05:21:57.14#ibcon#about to read 6, iclass 36, count 0 2006.285.05:21:57.14#ibcon#read 6, iclass 36, count 0 2006.285.05:21:57.14#ibcon#end of sib2, iclass 36, count 0 2006.285.05:21:57.14#ibcon#*after write, iclass 36, count 0 2006.285.05:21:57.14#ibcon#*before return 0, iclass 36, count 0 2006.285.05:21:57.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.05:21:57.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.05:21:57.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.05:21:57.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.05:21:57.14$vck44/vblo=1,629.99 2006.285.05:21:57.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.05:21:57.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:57.14#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:57.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.05:21:57.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.05:21:57.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.05:21:57.14#ibcon#enter wrdev, iclass 38, count 0 2006.285.05:21:57.14#ibcon#first serial, iclass 38, count 0 2006.285.05:21:57.14#ibcon#enter sib2, iclass 38, count 0 2006.285.05:21:57.14#ibcon#flushed, iclass 38, count 0 2006.285.05:21:57.14#ibcon#about to write, iclass 38, count 0 2006.285.05:21:57.14#ibcon#wrote, iclass 38, count 0 2006.285.05:21:57.14#ibcon#about to read 3, iclass 38, count 0 2006.285.05:21:57.16#ibcon#read 3, iclass 38, count 0 2006.285.05:21:57.16#ibcon#about to read 4, iclass 38, count 0 2006.285.05:21:57.16#ibcon#read 4, iclass 38, count 0 2006.285.05:21:57.16#ibcon#about to read 5, iclass 38, count 0 2006.285.05:21:57.16#ibcon#read 5, iclass 38, count 0 2006.285.05:21:57.16#ibcon#about to read 6, iclass 38, count 0 2006.285.05:21:57.16#ibcon#read 6, iclass 38, count 0 2006.285.05:21:57.16#ibcon#end of sib2, iclass 38, count 0 2006.285.05:21:57.16#ibcon#*mode == 0, iclass 38, count 0 2006.285.05:21:57.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.05:21:57.16#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.05:21:57.16#ibcon#*before write, iclass 38, count 0 2006.285.05:21:57.16#ibcon#enter sib2, iclass 38, count 0 2006.285.05:21:57.16#ibcon#flushed, iclass 38, count 0 2006.285.05:21:57.16#ibcon#about to write, iclass 38, count 0 2006.285.05:21:57.16#ibcon#wrote, iclass 38, count 0 2006.285.05:21:57.16#ibcon#about to read 3, iclass 38, count 0 2006.285.05:21:57.20#ibcon#read 3, iclass 38, count 0 2006.285.05:21:57.20#ibcon#about to read 4, iclass 38, count 0 2006.285.05:21:57.20#ibcon#read 4, iclass 38, count 0 2006.285.05:21:57.20#ibcon#about to read 5, iclass 38, count 0 2006.285.05:21:57.20#ibcon#read 5, iclass 38, count 0 2006.285.05:21:57.20#ibcon#about to read 6, iclass 38, count 0 2006.285.05:21:57.20#ibcon#read 6, iclass 38, count 0 2006.285.05:21:57.20#ibcon#end of sib2, iclass 38, count 0 2006.285.05:21:57.20#ibcon#*after write, iclass 38, count 0 2006.285.05:21:57.20#ibcon#*before return 0, iclass 38, count 0 2006.285.05:21:57.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.05:21:57.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.05:21:57.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.05:21:57.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.05:21:57.20$vck44/vb=1,4 2006.285.05:21:57.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.05:21:57.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.05:21:57.20#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:57.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.05:21:57.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.05:21:57.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.05:21:57.20#ibcon#enter wrdev, iclass 40, count 2 2006.285.05:21:57.20#ibcon#first serial, iclass 40, count 2 2006.285.05:21:57.20#ibcon#enter sib2, iclass 40, count 2 2006.285.05:21:57.20#ibcon#flushed, iclass 40, count 2 2006.285.05:21:57.20#ibcon#about to write, iclass 40, count 2 2006.285.05:21:57.20#ibcon#wrote, iclass 40, count 2 2006.285.05:21:57.20#ibcon#about to read 3, iclass 40, count 2 2006.285.05:21:57.22#ibcon#read 3, iclass 40, count 2 2006.285.05:21:57.22#ibcon#about to read 4, iclass 40, count 2 2006.285.05:21:57.22#ibcon#read 4, iclass 40, count 2 2006.285.05:21:57.22#ibcon#about to read 5, iclass 40, count 2 2006.285.05:21:57.22#ibcon#read 5, iclass 40, count 2 2006.285.05:21:57.22#ibcon#about to read 6, iclass 40, count 2 2006.285.05:21:57.22#ibcon#read 6, iclass 40, count 2 2006.285.05:21:57.22#ibcon#end of sib2, iclass 40, count 2 2006.285.05:21:57.22#ibcon#*mode == 0, iclass 40, count 2 2006.285.05:21:57.22#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.05:21:57.22#ibcon#[27=AT01-04\r\n] 2006.285.05:21:57.22#ibcon#*before write, iclass 40, count 2 2006.285.05:21:57.22#ibcon#enter sib2, iclass 40, count 2 2006.285.05:21:57.22#ibcon#flushed, iclass 40, count 2 2006.285.05:21:57.22#ibcon#about to write, iclass 40, count 2 2006.285.05:21:57.22#ibcon#wrote, iclass 40, count 2 2006.285.05:21:57.22#ibcon#about to read 3, iclass 40, count 2 2006.285.05:21:57.25#ibcon#read 3, iclass 40, count 2 2006.285.05:21:57.25#ibcon#about to read 4, iclass 40, count 2 2006.285.05:21:57.25#ibcon#read 4, iclass 40, count 2 2006.285.05:21:57.25#ibcon#about to read 5, iclass 40, count 2 2006.285.05:21:57.25#ibcon#read 5, iclass 40, count 2 2006.285.05:21:57.25#ibcon#about to read 6, iclass 40, count 2 2006.285.05:21:57.25#ibcon#read 6, iclass 40, count 2 2006.285.05:21:57.25#ibcon#end of sib2, iclass 40, count 2 2006.285.05:21:57.25#ibcon#*after write, iclass 40, count 2 2006.285.05:21:57.25#ibcon#*before return 0, iclass 40, count 2 2006.285.05:21:57.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.05:21:57.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.05:21:57.25#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.05:21:57.25#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:57.25#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.05:21:57.37#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.05:21:57.37#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.05:21:57.37#ibcon#enter wrdev, iclass 40, count 0 2006.285.05:21:57.37#ibcon#first serial, iclass 40, count 0 2006.285.05:21:57.37#ibcon#enter sib2, iclass 40, count 0 2006.285.05:21:57.37#ibcon#flushed, iclass 40, count 0 2006.285.05:21:57.37#ibcon#about to write, iclass 40, count 0 2006.285.05:21:57.37#ibcon#wrote, iclass 40, count 0 2006.285.05:21:57.37#ibcon#about to read 3, iclass 40, count 0 2006.285.05:21:57.39#ibcon#read 3, iclass 40, count 0 2006.285.05:21:57.39#ibcon#about to read 4, iclass 40, count 0 2006.285.05:21:57.39#ibcon#read 4, iclass 40, count 0 2006.285.05:21:57.39#ibcon#about to read 5, iclass 40, count 0 2006.285.05:21:57.39#ibcon#read 5, iclass 40, count 0 2006.285.05:21:57.39#ibcon#about to read 6, iclass 40, count 0 2006.285.05:21:57.39#ibcon#read 6, iclass 40, count 0 2006.285.05:21:57.39#ibcon#end of sib2, iclass 40, count 0 2006.285.05:21:57.39#ibcon#*mode == 0, iclass 40, count 0 2006.285.05:21:57.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.05:21:57.39#ibcon#[27=USB\r\n] 2006.285.05:21:57.39#ibcon#*before write, iclass 40, count 0 2006.285.05:21:57.39#ibcon#enter sib2, iclass 40, count 0 2006.285.05:21:57.39#ibcon#flushed, iclass 40, count 0 2006.285.05:21:57.39#ibcon#about to write, iclass 40, count 0 2006.285.05:21:57.39#ibcon#wrote, iclass 40, count 0 2006.285.05:21:57.39#ibcon#about to read 3, iclass 40, count 0 2006.285.05:21:57.42#ibcon#read 3, iclass 40, count 0 2006.285.05:21:57.42#ibcon#about to read 4, iclass 40, count 0 2006.285.05:21:57.42#ibcon#read 4, iclass 40, count 0 2006.285.05:21:57.42#ibcon#about to read 5, iclass 40, count 0 2006.285.05:21:57.42#ibcon#read 5, iclass 40, count 0 2006.285.05:21:57.42#ibcon#about to read 6, iclass 40, count 0 2006.285.05:21:57.42#ibcon#read 6, iclass 40, count 0 2006.285.05:21:57.42#ibcon#end of sib2, iclass 40, count 0 2006.285.05:21:57.42#ibcon#*after write, iclass 40, count 0 2006.285.05:21:57.42#ibcon#*before return 0, iclass 40, count 0 2006.285.05:21:57.42#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.05:21:57.42#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.05:21:57.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.05:21:57.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.05:21:57.42$vck44/vblo=2,634.99 2006.285.05:21:57.42#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.05:21:57.42#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.05:21:57.42#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:57.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.05:21:57.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.05:21:57.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.05:21:57.42#ibcon#enter wrdev, iclass 4, count 0 2006.285.05:21:57.42#ibcon#first serial, iclass 4, count 0 2006.285.05:21:57.42#ibcon#enter sib2, iclass 4, count 0 2006.285.05:21:57.42#ibcon#flushed, iclass 4, count 0 2006.285.05:21:57.42#ibcon#about to write, iclass 4, count 0 2006.285.05:21:57.42#ibcon#wrote, iclass 4, count 0 2006.285.05:21:57.42#ibcon#about to read 3, iclass 4, count 0 2006.285.05:21:57.44#ibcon#read 3, iclass 4, count 0 2006.285.05:21:57.44#ibcon#about to read 4, iclass 4, count 0 2006.285.05:21:57.44#ibcon#read 4, iclass 4, count 0 2006.285.05:21:57.44#ibcon#about to read 5, iclass 4, count 0 2006.285.05:21:57.44#ibcon#read 5, iclass 4, count 0 2006.285.05:21:57.44#ibcon#about to read 6, iclass 4, count 0 2006.285.05:21:57.44#ibcon#read 6, iclass 4, count 0 2006.285.05:21:57.44#ibcon#end of sib2, iclass 4, count 0 2006.285.05:21:57.44#ibcon#*mode == 0, iclass 4, count 0 2006.285.05:21:57.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.05:21:57.44#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.05:21:57.44#ibcon#*before write, iclass 4, count 0 2006.285.05:21:57.44#ibcon#enter sib2, iclass 4, count 0 2006.285.05:21:57.44#ibcon#flushed, iclass 4, count 0 2006.285.05:21:57.44#ibcon#about to write, iclass 4, count 0 2006.285.05:21:57.44#ibcon#wrote, iclass 4, count 0 2006.285.05:21:57.44#ibcon#about to read 3, iclass 4, count 0 2006.285.05:21:57.48#ibcon#read 3, iclass 4, count 0 2006.285.05:21:57.48#ibcon#about to read 4, iclass 4, count 0 2006.285.05:21:57.48#ibcon#read 4, iclass 4, count 0 2006.285.05:21:57.48#ibcon#about to read 5, iclass 4, count 0 2006.285.05:21:57.48#ibcon#read 5, iclass 4, count 0 2006.285.05:21:57.48#ibcon#about to read 6, iclass 4, count 0 2006.285.05:21:57.48#ibcon#read 6, iclass 4, count 0 2006.285.05:21:57.48#ibcon#end of sib2, iclass 4, count 0 2006.285.05:21:57.48#ibcon#*after write, iclass 4, count 0 2006.285.05:21:57.48#ibcon#*before return 0, iclass 4, count 0 2006.285.05:21:57.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.05:21:57.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.05:21:57.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.05:21:57.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.05:21:57.48$vck44/vb=2,5 2006.285.05:21:57.48#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.05:21:57.48#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.05:21:57.48#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:57.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:57.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:57.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:57.54#ibcon#enter wrdev, iclass 6, count 2 2006.285.05:21:57.54#ibcon#first serial, iclass 6, count 2 2006.285.05:21:57.54#ibcon#enter sib2, iclass 6, count 2 2006.285.05:21:57.54#ibcon#flushed, iclass 6, count 2 2006.285.05:21:57.54#ibcon#about to write, iclass 6, count 2 2006.285.05:21:57.54#ibcon#wrote, iclass 6, count 2 2006.285.05:21:57.54#ibcon#about to read 3, iclass 6, count 2 2006.285.05:21:57.56#ibcon#read 3, iclass 6, count 2 2006.285.05:21:57.56#ibcon#about to read 4, iclass 6, count 2 2006.285.05:21:57.56#ibcon#read 4, iclass 6, count 2 2006.285.05:21:57.56#ibcon#about to read 5, iclass 6, count 2 2006.285.05:21:57.56#ibcon#read 5, iclass 6, count 2 2006.285.05:21:57.56#ibcon#about to read 6, iclass 6, count 2 2006.285.05:21:57.56#ibcon#read 6, iclass 6, count 2 2006.285.05:21:57.56#ibcon#end of sib2, iclass 6, count 2 2006.285.05:21:57.56#ibcon#*mode == 0, iclass 6, count 2 2006.285.05:21:57.56#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.05:21:57.56#ibcon#[27=AT02-05\r\n] 2006.285.05:21:57.56#ibcon#*before write, iclass 6, count 2 2006.285.05:21:57.56#ibcon#enter sib2, iclass 6, count 2 2006.285.05:21:57.56#ibcon#flushed, iclass 6, count 2 2006.285.05:21:57.56#ibcon#about to write, iclass 6, count 2 2006.285.05:21:57.56#ibcon#wrote, iclass 6, count 2 2006.285.05:21:57.56#ibcon#about to read 3, iclass 6, count 2 2006.285.05:21:57.59#ibcon#read 3, iclass 6, count 2 2006.285.05:21:57.59#ibcon#about to read 4, iclass 6, count 2 2006.285.05:21:57.59#ibcon#read 4, iclass 6, count 2 2006.285.05:21:57.59#ibcon#about to read 5, iclass 6, count 2 2006.285.05:21:57.59#ibcon#read 5, iclass 6, count 2 2006.285.05:21:57.59#ibcon#about to read 6, iclass 6, count 2 2006.285.05:21:57.59#ibcon#read 6, iclass 6, count 2 2006.285.05:21:57.59#ibcon#end of sib2, iclass 6, count 2 2006.285.05:21:57.59#ibcon#*after write, iclass 6, count 2 2006.285.05:21:57.59#ibcon#*before return 0, iclass 6, count 2 2006.285.05:21:57.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:57.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.05:21:57.59#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.05:21:57.59#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:57.59#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.05:21:57.71#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.05:21:57.71#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.05:21:57.71#ibcon#enter wrdev, iclass 6, count 0 2006.285.05:21:57.71#ibcon#first serial, iclass 6, count 0 2006.285.05:21:57.71#ibcon#enter sib2, iclass 6, count 0 2006.285.05:21:57.71#ibcon#flushed, iclass 6, count 0 2006.285.05:21:57.71#ibcon#about to write, iclass 6, count 0 2006.285.05:21:57.71#ibcon#wrote, iclass 6, count 0 2006.285.05:21:57.71#ibcon#about to read 3, iclass 6, count 0 2006.285.05:21:57.73#ibcon#read 3, iclass 6, count 0 2006.285.05:21:57.73#ibcon#about to read 4, iclass 6, count 0 2006.285.05:21:57.73#ibcon#read 4, iclass 6, count 0 2006.285.05:21:57.73#ibcon#about to read 5, iclass 6, count 0 2006.285.05:21:57.73#ibcon#read 5, iclass 6, count 0 2006.285.05:21:57.73#ibcon#about to read 6, iclass 6, count 0 2006.285.05:21:57.73#ibcon#read 6, iclass 6, count 0 2006.285.05:21:57.73#ibcon#end of sib2, iclass 6, count 0 2006.285.05:21:57.73#ibcon#*mode == 0, iclass 6, count 0 2006.285.05:21:57.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.05:21:57.73#ibcon#[27=USB\r\n] 2006.285.05:21:57.73#ibcon#*before write, iclass 6, count 0 2006.285.05:21:57.73#ibcon#enter sib2, iclass 6, count 0 2006.285.05:21:57.73#ibcon#flushed, iclass 6, count 0 2006.285.05:21:57.73#ibcon#about to write, iclass 6, count 0 2006.285.05:21:57.73#ibcon#wrote, iclass 6, count 0 2006.285.05:21:57.73#ibcon#about to read 3, iclass 6, count 0 2006.285.05:21:57.73#abcon#<5=/05 4.4 7.1 25.62 551013.8\r\n> 2006.285.05:21:57.75#abcon#{5=INTERFACE CLEAR} 2006.285.05:21:57.76#ibcon#read 3, iclass 6, count 0 2006.285.05:21:57.76#ibcon#about to read 4, iclass 6, count 0 2006.285.05:21:57.76#ibcon#read 4, iclass 6, count 0 2006.285.05:21:57.76#ibcon#about to read 5, iclass 6, count 0 2006.285.05:21:57.76#ibcon#read 5, iclass 6, count 0 2006.285.05:21:57.76#ibcon#about to read 6, iclass 6, count 0 2006.285.05:21:57.76#ibcon#read 6, iclass 6, count 0 2006.285.05:21:57.76#ibcon#end of sib2, iclass 6, count 0 2006.285.05:21:57.76#ibcon#*after write, iclass 6, count 0 2006.285.05:21:57.76#ibcon#*before return 0, iclass 6, count 0 2006.285.05:21:57.76#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.05:21:57.76#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.05:21:57.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.05:21:57.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.05:21:57.76$vck44/vblo=3,649.99 2006.285.05:21:57.76#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.05:21:57.76#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.05:21:57.76#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:57.76#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.05:21:57.76#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.05:21:57.76#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.05:21:57.76#ibcon#enter wrdev, iclass 13, count 0 2006.285.05:21:57.76#ibcon#first serial, iclass 13, count 0 2006.285.05:21:57.76#ibcon#enter sib2, iclass 13, count 0 2006.285.05:21:57.76#ibcon#flushed, iclass 13, count 0 2006.285.05:21:57.76#ibcon#about to write, iclass 13, count 0 2006.285.05:21:57.76#ibcon#wrote, iclass 13, count 0 2006.285.05:21:57.76#ibcon#about to read 3, iclass 13, count 0 2006.285.05:21:57.78#ibcon#read 3, iclass 13, count 0 2006.285.05:21:57.78#ibcon#about to read 4, iclass 13, count 0 2006.285.05:21:57.78#ibcon#read 4, iclass 13, count 0 2006.285.05:21:57.78#ibcon#about to read 5, iclass 13, count 0 2006.285.05:21:57.78#ibcon#read 5, iclass 13, count 0 2006.285.05:21:57.78#ibcon#about to read 6, iclass 13, count 0 2006.285.05:21:57.78#ibcon#read 6, iclass 13, count 0 2006.285.05:21:57.78#ibcon#end of sib2, iclass 13, count 0 2006.285.05:21:57.78#ibcon#*mode == 0, iclass 13, count 0 2006.285.05:21:57.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.05:21:57.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.05:21:57.78#ibcon#*before write, iclass 13, count 0 2006.285.05:21:57.78#ibcon#enter sib2, iclass 13, count 0 2006.285.05:21:57.78#ibcon#flushed, iclass 13, count 0 2006.285.05:21:57.78#ibcon#about to write, iclass 13, count 0 2006.285.05:21:57.78#ibcon#wrote, iclass 13, count 0 2006.285.05:21:57.78#ibcon#about to read 3, iclass 13, count 0 2006.285.05:21:57.81#abcon#[5=S1D000X0/0*\r\n] 2006.285.05:21:57.82#ibcon#read 3, iclass 13, count 0 2006.285.05:21:57.82#ibcon#about to read 4, iclass 13, count 0 2006.285.05:21:57.82#ibcon#read 4, iclass 13, count 0 2006.285.05:21:57.82#ibcon#about to read 5, iclass 13, count 0 2006.285.05:21:57.82#ibcon#read 5, iclass 13, count 0 2006.285.05:21:57.82#ibcon#about to read 6, iclass 13, count 0 2006.285.05:21:57.82#ibcon#read 6, iclass 13, count 0 2006.285.05:21:57.82#ibcon#end of sib2, iclass 13, count 0 2006.285.05:21:57.82#ibcon#*after write, iclass 13, count 0 2006.285.05:21:57.82#ibcon#*before return 0, iclass 13, count 0 2006.285.05:21:57.82#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.05:21:57.82#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.05:21:57.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.05:21:57.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.05:21:57.82$vck44/vb=3,4 2006.285.05:21:57.82#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.05:21:57.82#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.05:21:57.82#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:57.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:57.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:57.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:57.88#ibcon#enter wrdev, iclass 16, count 2 2006.285.05:21:57.88#ibcon#first serial, iclass 16, count 2 2006.285.05:21:57.88#ibcon#enter sib2, iclass 16, count 2 2006.285.05:21:57.88#ibcon#flushed, iclass 16, count 2 2006.285.05:21:57.88#ibcon#about to write, iclass 16, count 2 2006.285.05:21:57.88#ibcon#wrote, iclass 16, count 2 2006.285.05:21:57.88#ibcon#about to read 3, iclass 16, count 2 2006.285.05:21:57.90#ibcon#read 3, iclass 16, count 2 2006.285.05:21:57.90#ibcon#about to read 4, iclass 16, count 2 2006.285.05:21:57.90#ibcon#read 4, iclass 16, count 2 2006.285.05:21:57.90#ibcon#about to read 5, iclass 16, count 2 2006.285.05:21:57.90#ibcon#read 5, iclass 16, count 2 2006.285.05:21:57.90#ibcon#about to read 6, iclass 16, count 2 2006.285.05:21:57.90#ibcon#read 6, iclass 16, count 2 2006.285.05:21:57.90#ibcon#end of sib2, iclass 16, count 2 2006.285.05:21:57.90#ibcon#*mode == 0, iclass 16, count 2 2006.285.05:21:57.90#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.05:21:57.90#ibcon#[27=AT03-04\r\n] 2006.285.05:21:57.90#ibcon#*before write, iclass 16, count 2 2006.285.05:21:57.90#ibcon#enter sib2, iclass 16, count 2 2006.285.05:21:57.90#ibcon#flushed, iclass 16, count 2 2006.285.05:21:57.90#ibcon#about to write, iclass 16, count 2 2006.285.05:21:57.90#ibcon#wrote, iclass 16, count 2 2006.285.05:21:57.90#ibcon#about to read 3, iclass 16, count 2 2006.285.05:21:57.93#ibcon#read 3, iclass 16, count 2 2006.285.05:21:57.93#ibcon#about to read 4, iclass 16, count 2 2006.285.05:21:57.93#ibcon#read 4, iclass 16, count 2 2006.285.05:21:57.93#ibcon#about to read 5, iclass 16, count 2 2006.285.05:21:57.93#ibcon#read 5, iclass 16, count 2 2006.285.05:21:57.93#ibcon#about to read 6, iclass 16, count 2 2006.285.05:21:57.93#ibcon#read 6, iclass 16, count 2 2006.285.05:21:57.93#ibcon#end of sib2, iclass 16, count 2 2006.285.05:21:57.93#ibcon#*after write, iclass 16, count 2 2006.285.05:21:57.93#ibcon#*before return 0, iclass 16, count 2 2006.285.05:21:57.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:57.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.05:21:57.93#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.05:21:57.93#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:57.93#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.05:21:58.05#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.05:21:58.05#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.05:21:58.05#ibcon#enter wrdev, iclass 16, count 0 2006.285.05:21:58.05#ibcon#first serial, iclass 16, count 0 2006.285.05:21:58.05#ibcon#enter sib2, iclass 16, count 0 2006.285.05:21:58.05#ibcon#flushed, iclass 16, count 0 2006.285.05:21:58.05#ibcon#about to write, iclass 16, count 0 2006.285.05:21:58.05#ibcon#wrote, iclass 16, count 0 2006.285.05:21:58.05#ibcon#about to read 3, iclass 16, count 0 2006.285.05:21:58.07#ibcon#read 3, iclass 16, count 0 2006.285.05:21:58.07#ibcon#about to read 4, iclass 16, count 0 2006.285.05:21:58.07#ibcon#read 4, iclass 16, count 0 2006.285.05:21:58.07#ibcon#about to read 5, iclass 16, count 0 2006.285.05:21:58.07#ibcon#read 5, iclass 16, count 0 2006.285.05:21:58.07#ibcon#about to read 6, iclass 16, count 0 2006.285.05:21:58.07#ibcon#read 6, iclass 16, count 0 2006.285.05:21:58.07#ibcon#end of sib2, iclass 16, count 0 2006.285.05:21:58.07#ibcon#*mode == 0, iclass 16, count 0 2006.285.05:21:58.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.05:21:58.07#ibcon#[27=USB\r\n] 2006.285.05:21:58.07#ibcon#*before write, iclass 16, count 0 2006.285.05:21:58.07#ibcon#enter sib2, iclass 16, count 0 2006.285.05:21:58.07#ibcon#flushed, iclass 16, count 0 2006.285.05:21:58.07#ibcon#about to write, iclass 16, count 0 2006.285.05:21:58.07#ibcon#wrote, iclass 16, count 0 2006.285.05:21:58.07#ibcon#about to read 3, iclass 16, count 0 2006.285.05:21:58.10#ibcon#read 3, iclass 16, count 0 2006.285.05:21:58.10#ibcon#about to read 4, iclass 16, count 0 2006.285.05:21:58.10#ibcon#read 4, iclass 16, count 0 2006.285.05:21:58.10#ibcon#about to read 5, iclass 16, count 0 2006.285.05:21:58.10#ibcon#read 5, iclass 16, count 0 2006.285.05:21:58.10#ibcon#about to read 6, iclass 16, count 0 2006.285.05:21:58.10#ibcon#read 6, iclass 16, count 0 2006.285.05:21:58.10#ibcon#end of sib2, iclass 16, count 0 2006.285.05:21:58.10#ibcon#*after write, iclass 16, count 0 2006.285.05:21:58.10#ibcon#*before return 0, iclass 16, count 0 2006.285.05:21:58.10#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.05:21:58.10#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.05:21:58.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.05:21:58.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.05:21:58.10$vck44/vblo=4,679.99 2006.285.05:21:58.10#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.05:21:58.10#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.05:21:58.10#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:58.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.05:21:58.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.05:21:58.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.05:21:58.10#ibcon#enter wrdev, iclass 18, count 0 2006.285.05:21:58.10#ibcon#first serial, iclass 18, count 0 2006.285.05:21:58.10#ibcon#enter sib2, iclass 18, count 0 2006.285.05:21:58.10#ibcon#flushed, iclass 18, count 0 2006.285.05:21:58.10#ibcon#about to write, iclass 18, count 0 2006.285.05:21:58.10#ibcon#wrote, iclass 18, count 0 2006.285.05:21:58.10#ibcon#about to read 3, iclass 18, count 0 2006.285.05:21:58.12#ibcon#read 3, iclass 18, count 0 2006.285.05:21:58.12#ibcon#about to read 4, iclass 18, count 0 2006.285.05:21:58.12#ibcon#read 4, iclass 18, count 0 2006.285.05:21:58.12#ibcon#about to read 5, iclass 18, count 0 2006.285.05:21:58.12#ibcon#read 5, iclass 18, count 0 2006.285.05:21:58.12#ibcon#about to read 6, iclass 18, count 0 2006.285.05:21:58.12#ibcon#read 6, iclass 18, count 0 2006.285.05:21:58.12#ibcon#end of sib2, iclass 18, count 0 2006.285.05:21:58.12#ibcon#*mode == 0, iclass 18, count 0 2006.285.05:21:58.12#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.05:21:58.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.05:21:58.12#ibcon#*before write, iclass 18, count 0 2006.285.05:21:58.12#ibcon#enter sib2, iclass 18, count 0 2006.285.05:21:58.12#ibcon#flushed, iclass 18, count 0 2006.285.05:21:58.12#ibcon#about to write, iclass 18, count 0 2006.285.05:21:58.12#ibcon#wrote, iclass 18, count 0 2006.285.05:21:58.12#ibcon#about to read 3, iclass 18, count 0 2006.285.05:21:58.16#ibcon#read 3, iclass 18, count 0 2006.285.05:21:58.16#ibcon#about to read 4, iclass 18, count 0 2006.285.05:21:58.16#ibcon#read 4, iclass 18, count 0 2006.285.05:21:58.16#ibcon#about to read 5, iclass 18, count 0 2006.285.05:21:58.16#ibcon#read 5, iclass 18, count 0 2006.285.05:21:58.16#ibcon#about to read 6, iclass 18, count 0 2006.285.05:21:58.16#ibcon#read 6, iclass 18, count 0 2006.285.05:21:58.16#ibcon#end of sib2, iclass 18, count 0 2006.285.05:21:58.16#ibcon#*after write, iclass 18, count 0 2006.285.05:21:58.16#ibcon#*before return 0, iclass 18, count 0 2006.285.05:21:58.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.05:21:58.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.05:21:58.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.05:21:58.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.05:21:58.16$vck44/vb=4,5 2006.285.05:21:58.16#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.05:21:58.16#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.05:21:58.16#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:58.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:58.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:58.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:58.23#ibcon#enter wrdev, iclass 20, count 2 2006.285.05:21:58.23#ibcon#first serial, iclass 20, count 2 2006.285.05:21:58.23#ibcon#enter sib2, iclass 20, count 2 2006.285.05:21:58.23#ibcon#flushed, iclass 20, count 2 2006.285.05:21:58.23#ibcon#about to write, iclass 20, count 2 2006.285.05:21:58.23#ibcon#wrote, iclass 20, count 2 2006.285.05:21:58.23#ibcon#about to read 3, iclass 20, count 2 2006.285.05:21:58.24#ibcon#read 3, iclass 20, count 2 2006.285.05:21:58.24#ibcon#about to read 4, iclass 20, count 2 2006.285.05:21:58.24#ibcon#read 4, iclass 20, count 2 2006.285.05:21:58.24#ibcon#about to read 5, iclass 20, count 2 2006.285.05:21:58.24#ibcon#read 5, iclass 20, count 2 2006.285.05:21:58.24#ibcon#about to read 6, iclass 20, count 2 2006.285.05:21:58.24#ibcon#read 6, iclass 20, count 2 2006.285.05:21:58.24#ibcon#end of sib2, iclass 20, count 2 2006.285.05:21:58.24#ibcon#*mode == 0, iclass 20, count 2 2006.285.05:21:58.24#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.05:21:58.24#ibcon#[27=AT04-05\r\n] 2006.285.05:21:58.24#ibcon#*before write, iclass 20, count 2 2006.285.05:21:58.24#ibcon#enter sib2, iclass 20, count 2 2006.285.05:21:58.24#ibcon#flushed, iclass 20, count 2 2006.285.05:21:58.24#ibcon#about to write, iclass 20, count 2 2006.285.05:21:58.24#ibcon#wrote, iclass 20, count 2 2006.285.05:21:58.24#ibcon#about to read 3, iclass 20, count 2 2006.285.05:21:58.27#ibcon#read 3, iclass 20, count 2 2006.285.05:21:58.27#ibcon#about to read 4, iclass 20, count 2 2006.285.05:21:58.27#ibcon#read 4, iclass 20, count 2 2006.285.05:21:58.27#ibcon#about to read 5, iclass 20, count 2 2006.285.05:21:58.27#ibcon#read 5, iclass 20, count 2 2006.285.05:21:58.27#ibcon#about to read 6, iclass 20, count 2 2006.285.05:21:58.27#ibcon#read 6, iclass 20, count 2 2006.285.05:21:58.27#ibcon#end of sib2, iclass 20, count 2 2006.285.05:21:58.27#ibcon#*after write, iclass 20, count 2 2006.285.05:21:58.27#ibcon#*before return 0, iclass 20, count 2 2006.285.05:21:58.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:58.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.05:21:58.27#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.05:21:58.27#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:58.27#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.05:21:58.39#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.05:21:58.39#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.05:21:58.39#ibcon#enter wrdev, iclass 20, count 0 2006.285.05:21:58.39#ibcon#first serial, iclass 20, count 0 2006.285.05:21:58.39#ibcon#enter sib2, iclass 20, count 0 2006.285.05:21:58.39#ibcon#flushed, iclass 20, count 0 2006.285.05:21:58.39#ibcon#about to write, iclass 20, count 0 2006.285.05:21:58.39#ibcon#wrote, iclass 20, count 0 2006.285.05:21:58.39#ibcon#about to read 3, iclass 20, count 0 2006.285.05:21:58.41#ibcon#read 3, iclass 20, count 0 2006.285.05:21:58.41#ibcon#about to read 4, iclass 20, count 0 2006.285.05:21:58.41#ibcon#read 4, iclass 20, count 0 2006.285.05:21:58.41#ibcon#about to read 5, iclass 20, count 0 2006.285.05:21:58.41#ibcon#read 5, iclass 20, count 0 2006.285.05:21:58.41#ibcon#about to read 6, iclass 20, count 0 2006.285.05:21:58.41#ibcon#read 6, iclass 20, count 0 2006.285.05:21:58.41#ibcon#end of sib2, iclass 20, count 0 2006.285.05:21:58.41#ibcon#*mode == 0, iclass 20, count 0 2006.285.05:21:58.41#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.05:21:58.41#ibcon#[27=USB\r\n] 2006.285.05:21:58.41#ibcon#*before write, iclass 20, count 0 2006.285.05:21:58.41#ibcon#enter sib2, iclass 20, count 0 2006.285.05:21:58.41#ibcon#flushed, iclass 20, count 0 2006.285.05:21:58.41#ibcon#about to write, iclass 20, count 0 2006.285.05:21:58.41#ibcon#wrote, iclass 20, count 0 2006.285.05:21:58.41#ibcon#about to read 3, iclass 20, count 0 2006.285.05:21:58.44#ibcon#read 3, iclass 20, count 0 2006.285.05:21:58.44#ibcon#about to read 4, iclass 20, count 0 2006.285.05:21:58.44#ibcon#read 4, iclass 20, count 0 2006.285.05:21:58.44#ibcon#about to read 5, iclass 20, count 0 2006.285.05:21:58.44#ibcon#read 5, iclass 20, count 0 2006.285.05:21:58.44#ibcon#about to read 6, iclass 20, count 0 2006.285.05:21:58.44#ibcon#read 6, iclass 20, count 0 2006.285.05:21:58.44#ibcon#end of sib2, iclass 20, count 0 2006.285.05:21:58.44#ibcon#*after write, iclass 20, count 0 2006.285.05:21:58.44#ibcon#*before return 0, iclass 20, count 0 2006.285.05:21:58.44#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.05:21:58.44#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.05:21:58.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.05:21:58.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.05:21:58.44$vck44/vblo=5,709.99 2006.285.05:21:58.44#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.05:21:58.44#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.05:21:58.44#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:58.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.05:21:58.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.05:21:58.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.05:21:58.44#ibcon#enter wrdev, iclass 22, count 0 2006.285.05:21:58.44#ibcon#first serial, iclass 22, count 0 2006.285.05:21:58.44#ibcon#enter sib2, iclass 22, count 0 2006.285.05:21:58.44#ibcon#flushed, iclass 22, count 0 2006.285.05:21:58.44#ibcon#about to write, iclass 22, count 0 2006.285.05:21:58.44#ibcon#wrote, iclass 22, count 0 2006.285.05:21:58.44#ibcon#about to read 3, iclass 22, count 0 2006.285.05:21:58.46#ibcon#read 3, iclass 22, count 0 2006.285.05:21:58.46#ibcon#about to read 4, iclass 22, count 0 2006.285.05:21:58.46#ibcon#read 4, iclass 22, count 0 2006.285.05:21:58.46#ibcon#about to read 5, iclass 22, count 0 2006.285.05:21:58.46#ibcon#read 5, iclass 22, count 0 2006.285.05:21:58.46#ibcon#about to read 6, iclass 22, count 0 2006.285.05:21:58.46#ibcon#read 6, iclass 22, count 0 2006.285.05:21:58.46#ibcon#end of sib2, iclass 22, count 0 2006.285.05:21:58.46#ibcon#*mode == 0, iclass 22, count 0 2006.285.05:21:58.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.05:21:58.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.05:21:58.46#ibcon#*before write, iclass 22, count 0 2006.285.05:21:58.46#ibcon#enter sib2, iclass 22, count 0 2006.285.05:21:58.46#ibcon#flushed, iclass 22, count 0 2006.285.05:21:58.46#ibcon#about to write, iclass 22, count 0 2006.285.05:21:58.46#ibcon#wrote, iclass 22, count 0 2006.285.05:21:58.46#ibcon#about to read 3, iclass 22, count 0 2006.285.05:21:58.50#ibcon#read 3, iclass 22, count 0 2006.285.05:21:58.50#ibcon#about to read 4, iclass 22, count 0 2006.285.05:21:58.50#ibcon#read 4, iclass 22, count 0 2006.285.05:21:58.50#ibcon#about to read 5, iclass 22, count 0 2006.285.05:21:58.50#ibcon#read 5, iclass 22, count 0 2006.285.05:21:58.50#ibcon#about to read 6, iclass 22, count 0 2006.285.05:21:58.50#ibcon#read 6, iclass 22, count 0 2006.285.05:21:58.50#ibcon#end of sib2, iclass 22, count 0 2006.285.05:21:58.50#ibcon#*after write, iclass 22, count 0 2006.285.05:21:58.50#ibcon#*before return 0, iclass 22, count 0 2006.285.05:21:58.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.05:21:58.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.05:21:58.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.05:21:58.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.05:21:58.50$vck44/vb=5,4 2006.285.05:21:58.50#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.05:21:58.50#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.05:21:58.50#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:58.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:58.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:58.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:58.56#ibcon#enter wrdev, iclass 24, count 2 2006.285.05:21:58.56#ibcon#first serial, iclass 24, count 2 2006.285.05:21:58.56#ibcon#enter sib2, iclass 24, count 2 2006.285.05:21:58.56#ibcon#flushed, iclass 24, count 2 2006.285.05:21:58.56#ibcon#about to write, iclass 24, count 2 2006.285.05:21:58.56#ibcon#wrote, iclass 24, count 2 2006.285.05:21:58.56#ibcon#about to read 3, iclass 24, count 2 2006.285.05:21:58.58#ibcon#read 3, iclass 24, count 2 2006.285.05:21:58.58#ibcon#about to read 4, iclass 24, count 2 2006.285.05:21:58.58#ibcon#read 4, iclass 24, count 2 2006.285.05:21:58.58#ibcon#about to read 5, iclass 24, count 2 2006.285.05:21:58.58#ibcon#read 5, iclass 24, count 2 2006.285.05:21:58.58#ibcon#about to read 6, iclass 24, count 2 2006.285.05:21:58.58#ibcon#read 6, iclass 24, count 2 2006.285.05:21:58.58#ibcon#end of sib2, iclass 24, count 2 2006.285.05:21:58.58#ibcon#*mode == 0, iclass 24, count 2 2006.285.05:21:58.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.05:21:58.58#ibcon#[27=AT05-04\r\n] 2006.285.05:21:58.58#ibcon#*before write, iclass 24, count 2 2006.285.05:21:58.58#ibcon#enter sib2, iclass 24, count 2 2006.285.05:21:58.58#ibcon#flushed, iclass 24, count 2 2006.285.05:21:58.58#ibcon#about to write, iclass 24, count 2 2006.285.05:21:58.58#ibcon#wrote, iclass 24, count 2 2006.285.05:21:58.58#ibcon#about to read 3, iclass 24, count 2 2006.285.05:21:58.61#ibcon#read 3, iclass 24, count 2 2006.285.05:21:58.61#ibcon#about to read 4, iclass 24, count 2 2006.285.05:21:58.61#ibcon#read 4, iclass 24, count 2 2006.285.05:21:58.61#ibcon#about to read 5, iclass 24, count 2 2006.285.05:21:58.61#ibcon#read 5, iclass 24, count 2 2006.285.05:21:58.61#ibcon#about to read 6, iclass 24, count 2 2006.285.05:21:58.61#ibcon#read 6, iclass 24, count 2 2006.285.05:21:58.61#ibcon#end of sib2, iclass 24, count 2 2006.285.05:21:58.61#ibcon#*after write, iclass 24, count 2 2006.285.05:21:58.61#ibcon#*before return 0, iclass 24, count 2 2006.285.05:21:58.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:58.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.05:21:58.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.05:21:58.61#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:58.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.05:21:58.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.05:21:58.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.05:21:58.73#ibcon#enter wrdev, iclass 24, count 0 2006.285.05:21:58.73#ibcon#first serial, iclass 24, count 0 2006.285.05:21:58.73#ibcon#enter sib2, iclass 24, count 0 2006.285.05:21:58.73#ibcon#flushed, iclass 24, count 0 2006.285.05:21:58.73#ibcon#about to write, iclass 24, count 0 2006.285.05:21:58.73#ibcon#wrote, iclass 24, count 0 2006.285.05:21:58.73#ibcon#about to read 3, iclass 24, count 0 2006.285.05:21:58.75#ibcon#read 3, iclass 24, count 0 2006.285.05:21:58.75#ibcon#about to read 4, iclass 24, count 0 2006.285.05:21:58.75#ibcon#read 4, iclass 24, count 0 2006.285.05:21:58.75#ibcon#about to read 5, iclass 24, count 0 2006.285.05:21:58.75#ibcon#read 5, iclass 24, count 0 2006.285.05:21:58.75#ibcon#about to read 6, iclass 24, count 0 2006.285.05:21:58.75#ibcon#read 6, iclass 24, count 0 2006.285.05:21:58.75#ibcon#end of sib2, iclass 24, count 0 2006.285.05:21:58.75#ibcon#*mode == 0, iclass 24, count 0 2006.285.05:21:58.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.05:21:58.75#ibcon#[27=USB\r\n] 2006.285.05:21:58.75#ibcon#*before write, iclass 24, count 0 2006.285.05:21:58.75#ibcon#enter sib2, iclass 24, count 0 2006.285.05:21:58.75#ibcon#flushed, iclass 24, count 0 2006.285.05:21:58.75#ibcon#about to write, iclass 24, count 0 2006.285.05:21:58.75#ibcon#wrote, iclass 24, count 0 2006.285.05:21:58.75#ibcon#about to read 3, iclass 24, count 0 2006.285.05:21:58.78#ibcon#read 3, iclass 24, count 0 2006.285.05:21:58.78#ibcon#about to read 4, iclass 24, count 0 2006.285.05:21:58.78#ibcon#read 4, iclass 24, count 0 2006.285.05:21:58.78#ibcon#about to read 5, iclass 24, count 0 2006.285.05:21:58.78#ibcon#read 5, iclass 24, count 0 2006.285.05:21:58.78#ibcon#about to read 6, iclass 24, count 0 2006.285.05:21:58.78#ibcon#read 6, iclass 24, count 0 2006.285.05:21:58.78#ibcon#end of sib2, iclass 24, count 0 2006.285.05:21:58.78#ibcon#*after write, iclass 24, count 0 2006.285.05:21:58.78#ibcon#*before return 0, iclass 24, count 0 2006.285.05:21:58.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.05:21:58.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.05:21:58.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.05:21:58.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.05:21:58.78$vck44/vblo=6,719.99 2006.285.05:21:58.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.05:21:58.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.05:21:58.78#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:58.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.05:21:58.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.05:21:58.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.05:21:58.78#ibcon#enter wrdev, iclass 26, count 0 2006.285.05:21:58.78#ibcon#first serial, iclass 26, count 0 2006.285.05:21:58.78#ibcon#enter sib2, iclass 26, count 0 2006.285.05:21:58.78#ibcon#flushed, iclass 26, count 0 2006.285.05:21:58.78#ibcon#about to write, iclass 26, count 0 2006.285.05:21:58.78#ibcon#wrote, iclass 26, count 0 2006.285.05:21:58.78#ibcon#about to read 3, iclass 26, count 0 2006.285.05:21:58.80#ibcon#read 3, iclass 26, count 0 2006.285.05:21:58.80#ibcon#about to read 4, iclass 26, count 0 2006.285.05:21:58.80#ibcon#read 4, iclass 26, count 0 2006.285.05:21:58.80#ibcon#about to read 5, iclass 26, count 0 2006.285.05:21:58.80#ibcon#read 5, iclass 26, count 0 2006.285.05:21:58.80#ibcon#about to read 6, iclass 26, count 0 2006.285.05:21:58.80#ibcon#read 6, iclass 26, count 0 2006.285.05:21:58.80#ibcon#end of sib2, iclass 26, count 0 2006.285.05:21:58.80#ibcon#*mode == 0, iclass 26, count 0 2006.285.05:21:58.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.05:21:58.80#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.05:21:58.80#ibcon#*before write, iclass 26, count 0 2006.285.05:21:58.80#ibcon#enter sib2, iclass 26, count 0 2006.285.05:21:58.80#ibcon#flushed, iclass 26, count 0 2006.285.05:21:58.80#ibcon#about to write, iclass 26, count 0 2006.285.05:21:58.80#ibcon#wrote, iclass 26, count 0 2006.285.05:21:58.80#ibcon#about to read 3, iclass 26, count 0 2006.285.05:21:58.84#ibcon#read 3, iclass 26, count 0 2006.285.05:21:58.84#ibcon#about to read 4, iclass 26, count 0 2006.285.05:21:58.84#ibcon#read 4, iclass 26, count 0 2006.285.05:21:58.84#ibcon#about to read 5, iclass 26, count 0 2006.285.05:21:58.84#ibcon#read 5, iclass 26, count 0 2006.285.05:21:58.84#ibcon#about to read 6, iclass 26, count 0 2006.285.05:21:58.84#ibcon#read 6, iclass 26, count 0 2006.285.05:21:58.84#ibcon#end of sib2, iclass 26, count 0 2006.285.05:21:58.84#ibcon#*after write, iclass 26, count 0 2006.285.05:21:58.84#ibcon#*before return 0, iclass 26, count 0 2006.285.05:21:58.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.05:21:58.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.05:21:58.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.05:21:58.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.05:21:58.84$vck44/vb=6,3 2006.285.05:21:58.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.05:21:58.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.05:21:58.84#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:58.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:58.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:58.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:58.90#ibcon#enter wrdev, iclass 28, count 2 2006.285.05:21:58.90#ibcon#first serial, iclass 28, count 2 2006.285.05:21:58.90#ibcon#enter sib2, iclass 28, count 2 2006.285.05:21:58.90#ibcon#flushed, iclass 28, count 2 2006.285.05:21:58.90#ibcon#about to write, iclass 28, count 2 2006.285.05:21:58.90#ibcon#wrote, iclass 28, count 2 2006.285.05:21:58.90#ibcon#about to read 3, iclass 28, count 2 2006.285.05:21:58.92#ibcon#read 3, iclass 28, count 2 2006.285.05:21:58.92#ibcon#about to read 4, iclass 28, count 2 2006.285.05:21:58.92#ibcon#read 4, iclass 28, count 2 2006.285.05:21:58.92#ibcon#about to read 5, iclass 28, count 2 2006.285.05:21:58.92#ibcon#read 5, iclass 28, count 2 2006.285.05:21:58.92#ibcon#about to read 6, iclass 28, count 2 2006.285.05:21:58.92#ibcon#read 6, iclass 28, count 2 2006.285.05:21:58.92#ibcon#end of sib2, iclass 28, count 2 2006.285.05:21:58.92#ibcon#*mode == 0, iclass 28, count 2 2006.285.05:21:58.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.05:21:58.92#ibcon#[27=AT06-03\r\n] 2006.285.05:21:58.92#ibcon#*before write, iclass 28, count 2 2006.285.05:21:58.92#ibcon#enter sib2, iclass 28, count 2 2006.285.05:21:58.92#ibcon#flushed, iclass 28, count 2 2006.285.05:21:58.92#ibcon#about to write, iclass 28, count 2 2006.285.05:21:58.92#ibcon#wrote, iclass 28, count 2 2006.285.05:21:58.92#ibcon#about to read 3, iclass 28, count 2 2006.285.05:21:58.95#ibcon#read 3, iclass 28, count 2 2006.285.05:21:58.95#ibcon#about to read 4, iclass 28, count 2 2006.285.05:21:58.95#ibcon#read 4, iclass 28, count 2 2006.285.05:21:58.95#ibcon#about to read 5, iclass 28, count 2 2006.285.05:21:58.95#ibcon#read 5, iclass 28, count 2 2006.285.05:21:58.95#ibcon#about to read 6, iclass 28, count 2 2006.285.05:21:58.95#ibcon#read 6, iclass 28, count 2 2006.285.05:21:58.95#ibcon#end of sib2, iclass 28, count 2 2006.285.05:21:58.95#ibcon#*after write, iclass 28, count 2 2006.285.05:21:58.95#ibcon#*before return 0, iclass 28, count 2 2006.285.05:21:58.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:58.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.05:21:58.95#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.05:21:58.95#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:58.95#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.05:21:59.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.05:21:59.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.05:21:59.07#ibcon#enter wrdev, iclass 28, count 0 2006.285.05:21:59.07#ibcon#first serial, iclass 28, count 0 2006.285.05:21:59.07#ibcon#enter sib2, iclass 28, count 0 2006.285.05:21:59.07#ibcon#flushed, iclass 28, count 0 2006.285.05:21:59.07#ibcon#about to write, iclass 28, count 0 2006.285.05:21:59.07#ibcon#wrote, iclass 28, count 0 2006.285.05:21:59.07#ibcon#about to read 3, iclass 28, count 0 2006.285.05:21:59.09#ibcon#read 3, iclass 28, count 0 2006.285.05:21:59.09#ibcon#about to read 4, iclass 28, count 0 2006.285.05:21:59.09#ibcon#read 4, iclass 28, count 0 2006.285.05:21:59.09#ibcon#about to read 5, iclass 28, count 0 2006.285.05:21:59.09#ibcon#read 5, iclass 28, count 0 2006.285.05:21:59.09#ibcon#about to read 6, iclass 28, count 0 2006.285.05:21:59.09#ibcon#read 6, iclass 28, count 0 2006.285.05:21:59.09#ibcon#end of sib2, iclass 28, count 0 2006.285.05:21:59.09#ibcon#*mode == 0, iclass 28, count 0 2006.285.05:21:59.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.05:21:59.09#ibcon#[27=USB\r\n] 2006.285.05:21:59.09#ibcon#*before write, iclass 28, count 0 2006.285.05:21:59.09#ibcon#enter sib2, iclass 28, count 0 2006.285.05:21:59.09#ibcon#flushed, iclass 28, count 0 2006.285.05:21:59.09#ibcon#about to write, iclass 28, count 0 2006.285.05:21:59.09#ibcon#wrote, iclass 28, count 0 2006.285.05:21:59.09#ibcon#about to read 3, iclass 28, count 0 2006.285.05:21:59.12#ibcon#read 3, iclass 28, count 0 2006.285.05:21:59.12#ibcon#about to read 4, iclass 28, count 0 2006.285.05:21:59.12#ibcon#read 4, iclass 28, count 0 2006.285.05:21:59.12#ibcon#about to read 5, iclass 28, count 0 2006.285.05:21:59.12#ibcon#read 5, iclass 28, count 0 2006.285.05:21:59.12#ibcon#about to read 6, iclass 28, count 0 2006.285.05:21:59.12#ibcon#read 6, iclass 28, count 0 2006.285.05:21:59.12#ibcon#end of sib2, iclass 28, count 0 2006.285.05:21:59.12#ibcon#*after write, iclass 28, count 0 2006.285.05:21:59.12#ibcon#*before return 0, iclass 28, count 0 2006.285.05:21:59.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.05:21:59.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.05:21:59.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.05:21:59.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.05:21:59.12$vck44/vblo=7,734.99 2006.285.05:21:59.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.05:21:59.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.05:21:59.12#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:59.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.05:21:59.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.05:21:59.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.05:21:59.12#ibcon#enter wrdev, iclass 30, count 0 2006.285.05:21:59.12#ibcon#first serial, iclass 30, count 0 2006.285.05:21:59.12#ibcon#enter sib2, iclass 30, count 0 2006.285.05:21:59.12#ibcon#flushed, iclass 30, count 0 2006.285.05:21:59.12#ibcon#about to write, iclass 30, count 0 2006.285.05:21:59.12#ibcon#wrote, iclass 30, count 0 2006.285.05:21:59.12#ibcon#about to read 3, iclass 30, count 0 2006.285.05:21:59.14#ibcon#read 3, iclass 30, count 0 2006.285.05:21:59.14#ibcon#about to read 4, iclass 30, count 0 2006.285.05:21:59.14#ibcon#read 4, iclass 30, count 0 2006.285.05:21:59.14#ibcon#about to read 5, iclass 30, count 0 2006.285.05:21:59.14#ibcon#read 5, iclass 30, count 0 2006.285.05:21:59.14#ibcon#about to read 6, iclass 30, count 0 2006.285.05:21:59.14#ibcon#read 6, iclass 30, count 0 2006.285.05:21:59.14#ibcon#end of sib2, iclass 30, count 0 2006.285.05:21:59.14#ibcon#*mode == 0, iclass 30, count 0 2006.285.05:21:59.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.05:21:59.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.05:21:59.14#ibcon#*before write, iclass 30, count 0 2006.285.05:21:59.14#ibcon#enter sib2, iclass 30, count 0 2006.285.05:21:59.14#ibcon#flushed, iclass 30, count 0 2006.285.05:21:59.14#ibcon#about to write, iclass 30, count 0 2006.285.05:21:59.14#ibcon#wrote, iclass 30, count 0 2006.285.05:21:59.14#ibcon#about to read 3, iclass 30, count 0 2006.285.05:21:59.18#ibcon#read 3, iclass 30, count 0 2006.285.05:21:59.18#ibcon#about to read 4, iclass 30, count 0 2006.285.05:21:59.18#ibcon#read 4, iclass 30, count 0 2006.285.05:21:59.18#ibcon#about to read 5, iclass 30, count 0 2006.285.05:21:59.18#ibcon#read 5, iclass 30, count 0 2006.285.05:21:59.18#ibcon#about to read 6, iclass 30, count 0 2006.285.05:21:59.18#ibcon#read 6, iclass 30, count 0 2006.285.05:21:59.18#ibcon#end of sib2, iclass 30, count 0 2006.285.05:21:59.18#ibcon#*after write, iclass 30, count 0 2006.285.05:21:59.18#ibcon#*before return 0, iclass 30, count 0 2006.285.05:21:59.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.05:21:59.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.05:21:59.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.05:21:59.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.05:21:59.18$vck44/vb=7,4 2006.285.05:21:59.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.05:21:59.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.05:21:59.18#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:59.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:59.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:59.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:59.24#ibcon#enter wrdev, iclass 32, count 2 2006.285.05:21:59.24#ibcon#first serial, iclass 32, count 2 2006.285.05:21:59.24#ibcon#enter sib2, iclass 32, count 2 2006.285.05:21:59.24#ibcon#flushed, iclass 32, count 2 2006.285.05:21:59.24#ibcon#about to write, iclass 32, count 2 2006.285.05:21:59.24#ibcon#wrote, iclass 32, count 2 2006.285.05:21:59.24#ibcon#about to read 3, iclass 32, count 2 2006.285.05:21:59.26#ibcon#read 3, iclass 32, count 2 2006.285.05:21:59.26#ibcon#about to read 4, iclass 32, count 2 2006.285.05:21:59.26#ibcon#read 4, iclass 32, count 2 2006.285.05:21:59.26#ibcon#about to read 5, iclass 32, count 2 2006.285.05:21:59.26#ibcon#read 5, iclass 32, count 2 2006.285.05:21:59.26#ibcon#about to read 6, iclass 32, count 2 2006.285.05:21:59.26#ibcon#read 6, iclass 32, count 2 2006.285.05:21:59.26#ibcon#end of sib2, iclass 32, count 2 2006.285.05:21:59.26#ibcon#*mode == 0, iclass 32, count 2 2006.285.05:21:59.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.05:21:59.26#ibcon#[27=AT07-04\r\n] 2006.285.05:21:59.26#ibcon#*before write, iclass 32, count 2 2006.285.05:21:59.26#ibcon#enter sib2, iclass 32, count 2 2006.285.05:21:59.26#ibcon#flushed, iclass 32, count 2 2006.285.05:21:59.26#ibcon#about to write, iclass 32, count 2 2006.285.05:21:59.26#ibcon#wrote, iclass 32, count 2 2006.285.05:21:59.26#ibcon#about to read 3, iclass 32, count 2 2006.285.05:21:59.29#ibcon#read 3, iclass 32, count 2 2006.285.05:21:59.29#ibcon#about to read 4, iclass 32, count 2 2006.285.05:21:59.29#ibcon#read 4, iclass 32, count 2 2006.285.05:21:59.29#ibcon#about to read 5, iclass 32, count 2 2006.285.05:21:59.29#ibcon#read 5, iclass 32, count 2 2006.285.05:21:59.29#ibcon#about to read 6, iclass 32, count 2 2006.285.05:21:59.29#ibcon#read 6, iclass 32, count 2 2006.285.05:21:59.29#ibcon#end of sib2, iclass 32, count 2 2006.285.05:21:59.29#ibcon#*after write, iclass 32, count 2 2006.285.05:21:59.29#ibcon#*before return 0, iclass 32, count 2 2006.285.05:21:59.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:59.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.05:21:59.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.05:21:59.29#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:59.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.05:21:59.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.05:21:59.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.05:21:59.41#ibcon#enter wrdev, iclass 32, count 0 2006.285.05:21:59.41#ibcon#first serial, iclass 32, count 0 2006.285.05:21:59.41#ibcon#enter sib2, iclass 32, count 0 2006.285.05:21:59.41#ibcon#flushed, iclass 32, count 0 2006.285.05:21:59.41#ibcon#about to write, iclass 32, count 0 2006.285.05:21:59.41#ibcon#wrote, iclass 32, count 0 2006.285.05:21:59.41#ibcon#about to read 3, iclass 32, count 0 2006.285.05:21:59.43#ibcon#read 3, iclass 32, count 0 2006.285.05:21:59.43#ibcon#about to read 4, iclass 32, count 0 2006.285.05:21:59.43#ibcon#read 4, iclass 32, count 0 2006.285.05:21:59.43#ibcon#about to read 5, iclass 32, count 0 2006.285.05:21:59.43#ibcon#read 5, iclass 32, count 0 2006.285.05:21:59.43#ibcon#about to read 6, iclass 32, count 0 2006.285.05:21:59.43#ibcon#read 6, iclass 32, count 0 2006.285.05:21:59.43#ibcon#end of sib2, iclass 32, count 0 2006.285.05:21:59.43#ibcon#*mode == 0, iclass 32, count 0 2006.285.05:21:59.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.05:21:59.43#ibcon#[27=USB\r\n] 2006.285.05:21:59.43#ibcon#*before write, iclass 32, count 0 2006.285.05:21:59.43#ibcon#enter sib2, iclass 32, count 0 2006.285.05:21:59.43#ibcon#flushed, iclass 32, count 0 2006.285.05:21:59.43#ibcon#about to write, iclass 32, count 0 2006.285.05:21:59.43#ibcon#wrote, iclass 32, count 0 2006.285.05:21:59.43#ibcon#about to read 3, iclass 32, count 0 2006.285.05:21:59.46#ibcon#read 3, iclass 32, count 0 2006.285.05:21:59.46#ibcon#about to read 4, iclass 32, count 0 2006.285.05:21:59.46#ibcon#read 4, iclass 32, count 0 2006.285.05:21:59.46#ibcon#about to read 5, iclass 32, count 0 2006.285.05:21:59.46#ibcon#read 5, iclass 32, count 0 2006.285.05:21:59.46#ibcon#about to read 6, iclass 32, count 0 2006.285.05:21:59.46#ibcon#read 6, iclass 32, count 0 2006.285.05:21:59.46#ibcon#end of sib2, iclass 32, count 0 2006.285.05:21:59.46#ibcon#*after write, iclass 32, count 0 2006.285.05:21:59.46#ibcon#*before return 0, iclass 32, count 0 2006.285.05:21:59.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.05:21:59.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.05:21:59.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.05:21:59.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.05:21:59.46$vck44/vblo=8,744.99 2006.285.05:21:59.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.05:21:59.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.05:21:59.46#ibcon#ireg 17 cls_cnt 0 2006.285.05:21:59.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.05:21:59.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.05:21:59.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.05:21:59.46#ibcon#enter wrdev, iclass 34, count 0 2006.285.05:21:59.46#ibcon#first serial, iclass 34, count 0 2006.285.05:21:59.46#ibcon#enter sib2, iclass 34, count 0 2006.285.05:21:59.46#ibcon#flushed, iclass 34, count 0 2006.285.05:21:59.46#ibcon#about to write, iclass 34, count 0 2006.285.05:21:59.46#ibcon#wrote, iclass 34, count 0 2006.285.05:21:59.46#ibcon#about to read 3, iclass 34, count 0 2006.285.05:21:59.49#ibcon#read 3, iclass 34, count 0 2006.285.05:21:59.49#ibcon#about to read 4, iclass 34, count 0 2006.285.05:21:59.49#ibcon#read 4, iclass 34, count 0 2006.285.05:21:59.49#ibcon#about to read 5, iclass 34, count 0 2006.285.05:21:59.49#ibcon#read 5, iclass 34, count 0 2006.285.05:21:59.49#ibcon#about to read 6, iclass 34, count 0 2006.285.05:21:59.49#ibcon#read 6, iclass 34, count 0 2006.285.05:21:59.49#ibcon#end of sib2, iclass 34, count 0 2006.285.05:21:59.49#ibcon#*mode == 0, iclass 34, count 0 2006.285.05:21:59.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.05:21:59.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.05:21:59.49#ibcon#*before write, iclass 34, count 0 2006.285.05:21:59.49#ibcon#enter sib2, iclass 34, count 0 2006.285.05:21:59.49#ibcon#flushed, iclass 34, count 0 2006.285.05:21:59.49#ibcon#about to write, iclass 34, count 0 2006.285.05:21:59.49#ibcon#wrote, iclass 34, count 0 2006.285.05:21:59.49#ibcon#about to read 3, iclass 34, count 0 2006.285.05:21:59.53#ibcon#read 3, iclass 34, count 0 2006.285.05:21:59.53#ibcon#about to read 4, iclass 34, count 0 2006.285.05:21:59.53#ibcon#read 4, iclass 34, count 0 2006.285.05:21:59.53#ibcon#about to read 5, iclass 34, count 0 2006.285.05:21:59.53#ibcon#read 5, iclass 34, count 0 2006.285.05:21:59.53#ibcon#about to read 6, iclass 34, count 0 2006.285.05:21:59.53#ibcon#read 6, iclass 34, count 0 2006.285.05:21:59.53#ibcon#end of sib2, iclass 34, count 0 2006.285.05:21:59.53#ibcon#*after write, iclass 34, count 0 2006.285.05:21:59.53#ibcon#*before return 0, iclass 34, count 0 2006.285.05:21:59.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.05:21:59.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.05:21:59.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.05:21:59.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.05:21:59.53$vck44/vb=8,4 2006.285.05:21:59.53#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.05:21:59.53#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.05:21:59.53#ibcon#ireg 11 cls_cnt 2 2006.285.05:21:59.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:59.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:59.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:59.58#ibcon#enter wrdev, iclass 36, count 2 2006.285.05:21:59.58#ibcon#first serial, iclass 36, count 2 2006.285.05:21:59.58#ibcon#enter sib2, iclass 36, count 2 2006.285.05:21:59.58#ibcon#flushed, iclass 36, count 2 2006.285.05:21:59.58#ibcon#about to write, iclass 36, count 2 2006.285.05:21:59.58#ibcon#wrote, iclass 36, count 2 2006.285.05:21:59.58#ibcon#about to read 3, iclass 36, count 2 2006.285.05:21:59.60#ibcon#read 3, iclass 36, count 2 2006.285.05:21:59.60#ibcon#about to read 4, iclass 36, count 2 2006.285.05:21:59.60#ibcon#read 4, iclass 36, count 2 2006.285.05:21:59.60#ibcon#about to read 5, iclass 36, count 2 2006.285.05:21:59.60#ibcon#read 5, iclass 36, count 2 2006.285.05:21:59.60#ibcon#about to read 6, iclass 36, count 2 2006.285.05:21:59.60#ibcon#read 6, iclass 36, count 2 2006.285.05:21:59.60#ibcon#end of sib2, iclass 36, count 2 2006.285.05:21:59.60#ibcon#*mode == 0, iclass 36, count 2 2006.285.05:21:59.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.05:21:59.60#ibcon#[27=AT08-04\r\n] 2006.285.05:21:59.60#ibcon#*before write, iclass 36, count 2 2006.285.05:21:59.60#ibcon#enter sib2, iclass 36, count 2 2006.285.05:21:59.60#ibcon#flushed, iclass 36, count 2 2006.285.05:21:59.60#ibcon#about to write, iclass 36, count 2 2006.285.05:21:59.60#ibcon#wrote, iclass 36, count 2 2006.285.05:21:59.60#ibcon#about to read 3, iclass 36, count 2 2006.285.05:21:59.63#ibcon#read 3, iclass 36, count 2 2006.285.05:21:59.63#ibcon#about to read 4, iclass 36, count 2 2006.285.05:21:59.63#ibcon#read 4, iclass 36, count 2 2006.285.05:21:59.63#ibcon#about to read 5, iclass 36, count 2 2006.285.05:21:59.63#ibcon#read 5, iclass 36, count 2 2006.285.05:21:59.63#ibcon#about to read 6, iclass 36, count 2 2006.285.05:21:59.63#ibcon#read 6, iclass 36, count 2 2006.285.05:21:59.63#ibcon#end of sib2, iclass 36, count 2 2006.285.05:21:59.63#ibcon#*after write, iclass 36, count 2 2006.285.05:21:59.63#ibcon#*before return 0, iclass 36, count 2 2006.285.05:21:59.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:59.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.05:21:59.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.05:21:59.63#ibcon#ireg 7 cls_cnt 0 2006.285.05:21:59.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.05:21:59.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.05:21:59.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.05:21:59.75#ibcon#enter wrdev, iclass 36, count 0 2006.285.05:21:59.75#ibcon#first serial, iclass 36, count 0 2006.285.05:21:59.75#ibcon#enter sib2, iclass 36, count 0 2006.285.05:21:59.75#ibcon#flushed, iclass 36, count 0 2006.285.05:21:59.75#ibcon#about to write, iclass 36, count 0 2006.285.05:21:59.75#ibcon#wrote, iclass 36, count 0 2006.285.05:21:59.75#ibcon#about to read 3, iclass 36, count 0 2006.285.05:21:59.77#ibcon#read 3, iclass 36, count 0 2006.285.05:21:59.77#ibcon#about to read 4, iclass 36, count 0 2006.285.05:21:59.77#ibcon#read 4, iclass 36, count 0 2006.285.05:21:59.77#ibcon#about to read 5, iclass 36, count 0 2006.285.05:21:59.77#ibcon#read 5, iclass 36, count 0 2006.285.05:21:59.77#ibcon#about to read 6, iclass 36, count 0 2006.285.05:21:59.77#ibcon#read 6, iclass 36, count 0 2006.285.05:21:59.77#ibcon#end of sib2, iclass 36, count 0 2006.285.05:21:59.77#ibcon#*mode == 0, iclass 36, count 0 2006.285.05:21:59.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.05:21:59.77#ibcon#[27=USB\r\n] 2006.285.05:21:59.77#ibcon#*before write, iclass 36, count 0 2006.285.05:21:59.77#ibcon#enter sib2, iclass 36, count 0 2006.285.05:21:59.77#ibcon#flushed, iclass 36, count 0 2006.285.05:21:59.77#ibcon#about to write, iclass 36, count 0 2006.285.05:21:59.77#ibcon#wrote, iclass 36, count 0 2006.285.05:21:59.77#ibcon#about to read 3, iclass 36, count 0 2006.285.05:21:59.80#ibcon#read 3, iclass 36, count 0 2006.285.05:21:59.80#ibcon#about to read 4, iclass 36, count 0 2006.285.05:21:59.80#ibcon#read 4, iclass 36, count 0 2006.285.05:21:59.80#ibcon#about to read 5, iclass 36, count 0 2006.285.05:21:59.80#ibcon#read 5, iclass 36, count 0 2006.285.05:21:59.80#ibcon#about to read 6, iclass 36, count 0 2006.285.05:21:59.80#ibcon#read 6, iclass 36, count 0 2006.285.05:21:59.80#ibcon#end of sib2, iclass 36, count 0 2006.285.05:21:59.80#ibcon#*after write, iclass 36, count 0 2006.285.05:21:59.80#ibcon#*before return 0, iclass 36, count 0 2006.285.05:21:59.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.05:21:59.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.05:21:59.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.05:21:59.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.05:21:59.80$vck44/vabw=wide 2006.285.05:21:59.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.05:21:59.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.05:21:59.80#ibcon#ireg 8 cls_cnt 0 2006.285.05:21:59.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.05:21:59.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.05:21:59.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.05:21:59.80#ibcon#enter wrdev, iclass 38, count 0 2006.285.05:21:59.80#ibcon#first serial, iclass 38, count 0 2006.285.05:21:59.80#ibcon#enter sib2, iclass 38, count 0 2006.285.05:21:59.80#ibcon#flushed, iclass 38, count 0 2006.285.05:21:59.80#ibcon#about to write, iclass 38, count 0 2006.285.05:21:59.80#ibcon#wrote, iclass 38, count 0 2006.285.05:21:59.80#ibcon#about to read 3, iclass 38, count 0 2006.285.05:21:59.82#ibcon#read 3, iclass 38, count 0 2006.285.05:21:59.82#ibcon#about to read 4, iclass 38, count 0 2006.285.05:21:59.82#ibcon#read 4, iclass 38, count 0 2006.285.05:21:59.82#ibcon#about to read 5, iclass 38, count 0 2006.285.05:21:59.82#ibcon#read 5, iclass 38, count 0 2006.285.05:21:59.82#ibcon#about to read 6, iclass 38, count 0 2006.285.05:21:59.82#ibcon#read 6, iclass 38, count 0 2006.285.05:21:59.82#ibcon#end of sib2, iclass 38, count 0 2006.285.05:21:59.82#ibcon#*mode == 0, iclass 38, count 0 2006.285.05:21:59.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.05:21:59.82#ibcon#[25=BW32\r\n] 2006.285.05:21:59.82#ibcon#*before write, iclass 38, count 0 2006.285.05:21:59.82#ibcon#enter sib2, iclass 38, count 0 2006.285.05:21:59.82#ibcon#flushed, iclass 38, count 0 2006.285.05:21:59.82#ibcon#about to write, iclass 38, count 0 2006.285.05:21:59.82#ibcon#wrote, iclass 38, count 0 2006.285.05:21:59.82#ibcon#about to read 3, iclass 38, count 0 2006.285.05:21:59.85#ibcon#read 3, iclass 38, count 0 2006.285.05:21:59.85#ibcon#about to read 4, iclass 38, count 0 2006.285.05:21:59.85#ibcon#read 4, iclass 38, count 0 2006.285.05:21:59.85#ibcon#about to read 5, iclass 38, count 0 2006.285.05:21:59.85#ibcon#read 5, iclass 38, count 0 2006.285.05:21:59.85#ibcon#about to read 6, iclass 38, count 0 2006.285.05:21:59.85#ibcon#read 6, iclass 38, count 0 2006.285.05:21:59.85#ibcon#end of sib2, iclass 38, count 0 2006.285.05:21:59.85#ibcon#*after write, iclass 38, count 0 2006.285.05:21:59.85#ibcon#*before return 0, iclass 38, count 0 2006.285.05:21:59.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.05:21:59.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.05:21:59.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.05:21:59.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.05:21:59.85$vck44/vbbw=wide 2006.285.05:21:59.85#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.05:21:59.85#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.05:21:59.85#ibcon#ireg 8 cls_cnt 0 2006.285.05:21:59.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.05:21:59.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.05:21:59.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.05:21:59.92#ibcon#enter wrdev, iclass 40, count 0 2006.285.05:21:59.92#ibcon#first serial, iclass 40, count 0 2006.285.05:21:59.92#ibcon#enter sib2, iclass 40, count 0 2006.285.05:21:59.92#ibcon#flushed, iclass 40, count 0 2006.285.05:21:59.92#ibcon#about to write, iclass 40, count 0 2006.285.05:21:59.92#ibcon#wrote, iclass 40, count 0 2006.285.05:21:59.92#ibcon#about to read 3, iclass 40, count 0 2006.285.05:21:59.94#ibcon#read 3, iclass 40, count 0 2006.285.05:21:59.94#ibcon#about to read 4, iclass 40, count 0 2006.285.05:21:59.94#ibcon#read 4, iclass 40, count 0 2006.285.05:21:59.94#ibcon#about to read 5, iclass 40, count 0 2006.285.05:21:59.94#ibcon#read 5, iclass 40, count 0 2006.285.05:21:59.94#ibcon#about to read 6, iclass 40, count 0 2006.285.05:21:59.94#ibcon#read 6, iclass 40, count 0 2006.285.05:21:59.94#ibcon#end of sib2, iclass 40, count 0 2006.285.05:21:59.94#ibcon#*mode == 0, iclass 40, count 0 2006.285.05:21:59.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.05:21:59.94#ibcon#[27=BW32\r\n] 2006.285.05:21:59.94#ibcon#*before write, iclass 40, count 0 2006.285.05:21:59.94#ibcon#enter sib2, iclass 40, count 0 2006.285.05:21:59.94#ibcon#flushed, iclass 40, count 0 2006.285.05:21:59.94#ibcon#about to write, iclass 40, count 0 2006.285.05:21:59.94#ibcon#wrote, iclass 40, count 0 2006.285.05:21:59.94#ibcon#about to read 3, iclass 40, count 0 2006.285.05:21:59.97#ibcon#read 3, iclass 40, count 0 2006.285.05:21:59.97#ibcon#about to read 4, iclass 40, count 0 2006.285.05:21:59.97#ibcon#read 4, iclass 40, count 0 2006.285.05:21:59.97#ibcon#about to read 5, iclass 40, count 0 2006.285.05:21:59.97#ibcon#read 5, iclass 40, count 0 2006.285.05:21:59.97#ibcon#about to read 6, iclass 40, count 0 2006.285.05:21:59.97#ibcon#read 6, iclass 40, count 0 2006.285.05:21:59.97#ibcon#end of sib2, iclass 40, count 0 2006.285.05:21:59.97#ibcon#*after write, iclass 40, count 0 2006.285.05:21:59.97#ibcon#*before return 0, iclass 40, count 0 2006.285.05:21:59.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.05:21:59.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.05:21:59.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.05:21:59.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.05:21:59.97$setupk4/ifdk4 2006.285.05:21:59.97$ifdk4/lo= 2006.285.05:21:59.97$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.05:21:59.97$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.05:21:59.97$ifdk4/patch= 2006.285.05:21:59.97$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.05:21:59.97$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.05:21:59.97$setupk4/!*+20s 2006.285.05:22:02.14#trakl#Source acquired 2006.285.05:22:04.14#flagr#flagr/antenna,acquired 2006.285.05:22:07.90#abcon#<5=/05 4.4 7.1 25.61 541013.8\r\n> 2006.285.05:22:07.92#abcon#{5=INTERFACE CLEAR} 2006.285.05:22:07.98#abcon#[5=S1D000X0/0*\r\n] 2006.285.05:22:14.49$setupk4/"tpicd 2006.285.05:22:14.49$setupk4/echo=off 2006.285.05:22:14.49$setupk4/xlog=off 2006.285.05:22:14.49:!2006.285.05:59:50 2006.285.05:25:07.94;cable 2006.285.05:25:08.02/cable/+6.4793E-03 2006.285.05:26:16.31;cablelong 2006.285.05:26:16.50/cablelong/+7.0358E-03 2006.285.05:26:20.53;cablediff 2006.285.05:26:20.53/cablediff/556.5e-6,+ 2006.285.05:27:29.68;cable 2006.285.05:27:29.78/cable/+6.4803E-03 2006.285.05:27:36.78;wx 2006.285.05:27:36.78/wx/25.49,1013.8,56 2006.285.05:27:47.24;"Sky is fine. 2006.285.05:28:03.20;xfe 2006.285.05:28:03.28/xfe/off,on,12.5 2006.285.05:28:10.67;clockoff 2006.285.05:28:10.67&clockoff/"gps-fmout=1p 2006.285.05:28:10.67&clockoff/fmout-gps=1p 2006.285.05:28:11.08/fmout-gps/S +2.69E-07 2006.285.05:59:50.00:preob 2006.285.05:59:50.00&preob/onsource 2006.285.05:59:50.14/onsource/TRACKING 2006.285.05:59:50.14:!2006.285.06:00:00 2006.285.06:00:00.00:"tape 2006.285.06:00:00.00:"st=record 2006.285.06:00:00.00:data_valid=on 2006.285.06:00:00.00:midob 2006.285.06:00:00.00&midob/onsource 2006.285.06:00:00.00&midob/wx 2006.285.06:00:00.00&midob/cable 2006.285.06:00:00.00&midob/va 2006.285.06:00:00.00&midob/valo 2006.285.06:00:00.00&midob/vb 2006.285.06:00:00.00&midob/vblo 2006.285.06:00:00.00&midob/vabw 2006.285.06:00:00.00&midob/vbbw 2006.285.06:00:00.00&midob/"form 2006.285.06:00:00.00&midob/xfe 2006.285.06:00:00.00&midob/ifatt 2006.285.06:00:00.00&midob/clockoff 2006.285.06:00:00.00&midob/sy=logmail 2006.285.06:00:00.00&midob/"sy=run setcl adapt & 2006.285.06:00:01.14/onsource/TRACKING 2006.285.06:00:01.14/wx/25.14,1014.0,65 2006.285.06:00:01.27/cable/+6.4766E-03 2006.285.06:00:02.36/va/01,07,usb,yes,35,38 2006.285.06:00:02.36/va/02,06,usb,yes,35,36 2006.285.06:00:02.36/va/03,07,usb,yes,35,37 2006.285.06:00:02.36/va/04,06,usb,yes,36,38 2006.285.06:00:02.36/va/05,03,usb,yes,36,36 2006.285.06:00:02.36/va/06,04,usb,yes,32,32 2006.285.06:00:02.36/va/07,04,usb,yes,33,34 2006.285.06:00:02.36/va/08,03,usb,yes,33,41 2006.285.06:00:02.59/valo/01,524.99,yes,locked 2006.285.06:00:02.59/valo/02,534.99,yes,locked 2006.285.06:00:02.59/valo/03,564.99,yes,locked 2006.285.06:00:02.59/valo/04,624.99,yes,locked 2006.285.06:00:02.59/valo/05,734.99,yes,locked 2006.285.06:00:02.59/valo/06,814.99,yes,locked 2006.285.06:00:02.59/valo/07,864.99,yes,locked 2006.285.06:00:02.59/valo/08,884.99,yes,locked 2006.285.06:00:03.68/vb/01,04,usb,yes,39,36 2006.285.06:00:03.68/vb/02,05,usb,yes,37,36 2006.285.06:00:03.68/vb/03,04,usb,yes,38,42 2006.285.06:00:03.68/vb/04,05,usb,yes,38,37 2006.285.06:00:03.68/vb/05,04,usb,yes,34,37 2006.285.06:00:03.68/vb/06,03,usb,yes,47,43 2006.285.06:00:03.68/vb/07,04,usb,yes,38,39 2006.285.06:00:03.68/vb/08,04,usb,yes,35,39 2006.285.06:00:03.93/vblo/01,629.99,yes,locked 2006.285.06:00:03.93/vblo/02,634.99,yes,locked 2006.285.06:00:03.93/vblo/03,649.99,yes,locked 2006.285.06:00:03.93/vblo/04,679.99,yes,locked 2006.285.06:00:03.93/vblo/05,709.99,yes,locked 2006.285.06:00:03.93/vblo/06,719.99,yes,locked 2006.285.06:00:03.93/vblo/07,734.99,yes,locked 2006.285.06:00:03.93/vblo/08,744.99,yes,locked 2006.285.06:00:04.07/vabw/8 2006.285.06:00:04.22/vbbw/8 2006.285.06:00:04.31/xfe/off,on,12.5 2006.285.06:00:04.68/ifatt/23,28,28,28 2006.285.06:00:05.07/fmout-gps/S +2.68E-07 2006.285.06:00:05.09:!2006.285.06:01:30 2006.285.06:01:30.00:data_valid=off 2006.285.06:01:30.00:"et 2006.285.06:01:30.00:!+3s 2006.285.06:01:33.01:"tape 2006.285.06:01:33.01:postob 2006.285.06:01:33.01&postob/cable 2006.285.06:01:33.01&postob/wx 2006.285.06:01:33.01&postob/clockoff 2006.285.06:01:33.07/cable/+6.4768E-03 2006.285.06:01:33.07/wx/25.12,1014.0,66 2006.285.06:01:34.07/fmout-gps/S +2.70E-07 2006.285.06:01:34.07:scan_name=285-0604,jd0610,40 2006.285.06:01:34.07:source=2134+00,213638.59,004154.2,2000.0,ccw 2006.285.06:01:34.14#flagr#flagr/antenna,new-source 2006.285.06:01:35.14:checkk5 2006.285.06:01:35.14&checkk5/chk_autoobs=1 2006.285.06:01:35.14&checkk5/chk_autoobs=2 2006.285.06:01:35.14&checkk5/chk_autoobs=3 2006.285.06:01:35.14&checkk5/chk_autoobs=4 2006.285.06:01:35.14&checkk5/chk_obsdata=1 2006.285.06:01:35.14&checkk5/chk_obsdata=2 2006.285.06:01:35.14&checkk5/chk_obsdata=3 2006.285.06:01:35.14&checkk5/chk_obsdata=4 2006.285.06:01:35.14&checkk5/k5log=1 2006.285.06:01:35.14&checkk5/k5log=2 2006.285.06:01:35.14&checkk5/k5log=3 2006.285.06:01:35.14&checkk5/k5log=4 2006.285.06:01:35.14&checkk5/obsinfo 2006.285.06:01:35.86/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:01:36.29/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:01:36.67/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:01:37.03/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:01:37.65/chk_obsdata//k5ts1/T2850600??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.285.06:01:38.32/chk_obsdata//k5ts2/T2850600??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.285.06:01:38.74/chk_obsdata//k5ts3/T2850600??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.285.06:01:39.20/chk_obsdata//k5ts4/T2850600??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.285.06:01:39.92/k5log//k5ts1_log_newline 2006.285.06:01:40.71/k5log//k5ts2_log_newline 2006.285.06:01:41.56/k5log//k5ts3_log_newline 2006.285.06:01:42.33/k5log//k5ts4_log_newline 2006.285.06:01:42.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:01:42.35:setupk4=1 2006.285.06:01:42.35$setupk4/echo=on 2006.285.06:01:42.35$setupk4/pcalon 2006.285.06:01:42.35$pcalon/"no phase cal control is implemented here 2006.285.06:01:42.35$setupk4/"tpicd=stop 2006.285.06:01:42.35$setupk4/"rec=synch_on 2006.285.06:01:42.35$setupk4/"rec_mode=128 2006.285.06:01:42.35$setupk4/!* 2006.285.06:01:42.35$setupk4/recpk4 2006.285.06:01:42.35$recpk4/recpatch= 2006.285.06:01:42.36$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:01:42.36$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:01:42.36$setupk4/vck44 2006.285.06:01:42.36$vck44/valo=1,524.99 2006.285.06:01:42.36#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.06:01:42.36#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.06:01:42.36#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:42.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:01:42.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:01:42.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:01:42.36#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:01:42.36#ibcon#first serial, iclass 29, count 0 2006.285.06:01:42.36#ibcon#enter sib2, iclass 29, count 0 2006.285.06:01:42.36#ibcon#flushed, iclass 29, count 0 2006.285.06:01:42.36#ibcon#about to write, iclass 29, count 0 2006.285.06:01:42.36#ibcon#wrote, iclass 29, count 0 2006.285.06:01:42.36#ibcon#about to read 3, iclass 29, count 0 2006.285.06:01:42.37#ibcon#read 3, iclass 29, count 0 2006.285.06:01:42.37#ibcon#about to read 4, iclass 29, count 0 2006.285.06:01:42.37#ibcon#read 4, iclass 29, count 0 2006.285.06:01:42.37#ibcon#about to read 5, iclass 29, count 0 2006.285.06:01:42.37#ibcon#read 5, iclass 29, count 0 2006.285.06:01:42.37#ibcon#about to read 6, iclass 29, count 0 2006.285.06:01:42.37#ibcon#read 6, iclass 29, count 0 2006.285.06:01:42.37#ibcon#end of sib2, iclass 29, count 0 2006.285.06:01:42.37#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:01:42.37#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:01:42.37#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:01:42.37#ibcon#*before write, iclass 29, count 0 2006.285.06:01:42.37#ibcon#enter sib2, iclass 29, count 0 2006.285.06:01:42.37#ibcon#flushed, iclass 29, count 0 2006.285.06:01:42.37#ibcon#about to write, iclass 29, count 0 2006.285.06:01:42.37#ibcon#wrote, iclass 29, count 0 2006.285.06:01:42.37#ibcon#about to read 3, iclass 29, count 0 2006.285.06:01:42.42#ibcon#read 3, iclass 29, count 0 2006.285.06:01:42.42#ibcon#about to read 4, iclass 29, count 0 2006.285.06:01:42.42#ibcon#read 4, iclass 29, count 0 2006.285.06:01:42.42#ibcon#about to read 5, iclass 29, count 0 2006.285.06:01:42.42#ibcon#read 5, iclass 29, count 0 2006.285.06:01:42.42#ibcon#about to read 6, iclass 29, count 0 2006.285.06:01:42.42#ibcon#read 6, iclass 29, count 0 2006.285.06:01:42.42#ibcon#end of sib2, iclass 29, count 0 2006.285.06:01:42.42#ibcon#*after write, iclass 29, count 0 2006.285.06:01:42.42#ibcon#*before return 0, iclass 29, count 0 2006.285.06:01:42.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:01:42.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:01:42.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:01:42.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:01:42.42$vck44/va=1,7 2006.285.06:01:42.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.06:01:42.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.06:01:42.42#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:42.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:01:42.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:01:42.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:01:42.42#ibcon#enter wrdev, iclass 31, count 2 2006.285.06:01:42.42#ibcon#first serial, iclass 31, count 2 2006.285.06:01:42.42#ibcon#enter sib2, iclass 31, count 2 2006.285.06:01:42.42#ibcon#flushed, iclass 31, count 2 2006.285.06:01:42.42#ibcon#about to write, iclass 31, count 2 2006.285.06:01:42.42#ibcon#wrote, iclass 31, count 2 2006.285.06:01:42.42#ibcon#about to read 3, iclass 31, count 2 2006.285.06:01:42.44#ibcon#read 3, iclass 31, count 2 2006.285.06:01:42.44#ibcon#about to read 4, iclass 31, count 2 2006.285.06:01:42.44#ibcon#read 4, iclass 31, count 2 2006.285.06:01:42.44#ibcon#about to read 5, iclass 31, count 2 2006.285.06:01:42.44#ibcon#read 5, iclass 31, count 2 2006.285.06:01:42.44#ibcon#about to read 6, iclass 31, count 2 2006.285.06:01:42.44#ibcon#read 6, iclass 31, count 2 2006.285.06:01:42.44#ibcon#end of sib2, iclass 31, count 2 2006.285.06:01:42.44#ibcon#*mode == 0, iclass 31, count 2 2006.285.06:01:42.44#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.06:01:42.44#ibcon#[25=AT01-07\r\n] 2006.285.06:01:42.44#ibcon#*before write, iclass 31, count 2 2006.285.06:01:42.44#ibcon#enter sib2, iclass 31, count 2 2006.285.06:01:42.44#ibcon#flushed, iclass 31, count 2 2006.285.06:01:42.44#ibcon#about to write, iclass 31, count 2 2006.285.06:01:42.44#ibcon#wrote, iclass 31, count 2 2006.285.06:01:42.44#ibcon#about to read 3, iclass 31, count 2 2006.285.06:01:42.47#ibcon#read 3, iclass 31, count 2 2006.285.06:01:42.47#ibcon#about to read 4, iclass 31, count 2 2006.285.06:01:42.47#ibcon#read 4, iclass 31, count 2 2006.285.06:01:42.47#ibcon#about to read 5, iclass 31, count 2 2006.285.06:01:42.47#ibcon#read 5, iclass 31, count 2 2006.285.06:01:42.47#ibcon#about to read 6, iclass 31, count 2 2006.285.06:01:42.47#ibcon#read 6, iclass 31, count 2 2006.285.06:01:42.47#ibcon#end of sib2, iclass 31, count 2 2006.285.06:01:42.47#ibcon#*after write, iclass 31, count 2 2006.285.06:01:42.47#ibcon#*before return 0, iclass 31, count 2 2006.285.06:01:42.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:01:42.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:01:42.47#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.06:01:42.47#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:42.47#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:01:42.59#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:01:42.59#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:01:42.59#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:01:42.59#ibcon#first serial, iclass 31, count 0 2006.285.06:01:42.59#ibcon#enter sib2, iclass 31, count 0 2006.285.06:01:42.59#ibcon#flushed, iclass 31, count 0 2006.285.06:01:42.59#ibcon#about to write, iclass 31, count 0 2006.285.06:01:42.59#ibcon#wrote, iclass 31, count 0 2006.285.06:01:42.59#ibcon#about to read 3, iclass 31, count 0 2006.285.06:01:42.61#ibcon#read 3, iclass 31, count 0 2006.285.06:01:42.61#ibcon#about to read 4, iclass 31, count 0 2006.285.06:01:42.61#ibcon#read 4, iclass 31, count 0 2006.285.06:01:42.61#ibcon#about to read 5, iclass 31, count 0 2006.285.06:01:42.61#ibcon#read 5, iclass 31, count 0 2006.285.06:01:42.61#ibcon#about to read 6, iclass 31, count 0 2006.285.06:01:42.61#ibcon#read 6, iclass 31, count 0 2006.285.06:01:42.61#ibcon#end of sib2, iclass 31, count 0 2006.285.06:01:42.61#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:01:42.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:01:42.61#ibcon#[25=USB\r\n] 2006.285.06:01:42.61#ibcon#*before write, iclass 31, count 0 2006.285.06:01:42.61#ibcon#enter sib2, iclass 31, count 0 2006.285.06:01:42.61#ibcon#flushed, iclass 31, count 0 2006.285.06:01:42.61#ibcon#about to write, iclass 31, count 0 2006.285.06:01:42.61#ibcon#wrote, iclass 31, count 0 2006.285.06:01:42.61#ibcon#about to read 3, iclass 31, count 0 2006.285.06:01:42.64#ibcon#read 3, iclass 31, count 0 2006.285.06:01:42.64#ibcon#about to read 4, iclass 31, count 0 2006.285.06:01:42.64#ibcon#read 4, iclass 31, count 0 2006.285.06:01:42.64#ibcon#about to read 5, iclass 31, count 0 2006.285.06:01:42.64#ibcon#read 5, iclass 31, count 0 2006.285.06:01:42.64#ibcon#about to read 6, iclass 31, count 0 2006.285.06:01:42.64#ibcon#read 6, iclass 31, count 0 2006.285.06:01:42.64#ibcon#end of sib2, iclass 31, count 0 2006.285.06:01:42.64#ibcon#*after write, iclass 31, count 0 2006.285.06:01:42.64#ibcon#*before return 0, iclass 31, count 0 2006.285.06:01:42.64#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:01:42.64#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:01:42.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:01:42.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:01:42.64$vck44/valo=2,534.99 2006.285.06:01:42.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.06:01:42.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.06:01:42.64#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:42.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:01:42.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:01:42.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:01:42.64#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:01:42.64#ibcon#first serial, iclass 33, count 0 2006.285.06:01:42.64#ibcon#enter sib2, iclass 33, count 0 2006.285.06:01:42.64#ibcon#flushed, iclass 33, count 0 2006.285.06:01:42.64#ibcon#about to write, iclass 33, count 0 2006.285.06:01:42.64#ibcon#wrote, iclass 33, count 0 2006.285.06:01:42.64#ibcon#about to read 3, iclass 33, count 0 2006.285.06:01:42.66#ibcon#read 3, iclass 33, count 0 2006.285.06:01:42.66#ibcon#about to read 4, iclass 33, count 0 2006.285.06:01:42.66#ibcon#read 4, iclass 33, count 0 2006.285.06:01:42.66#ibcon#about to read 5, iclass 33, count 0 2006.285.06:01:42.66#ibcon#read 5, iclass 33, count 0 2006.285.06:01:42.66#ibcon#about to read 6, iclass 33, count 0 2006.285.06:01:42.66#ibcon#read 6, iclass 33, count 0 2006.285.06:01:42.66#ibcon#end of sib2, iclass 33, count 0 2006.285.06:01:42.66#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:01:42.66#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:01:42.66#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:01:42.66#ibcon#*before write, iclass 33, count 0 2006.285.06:01:42.66#ibcon#enter sib2, iclass 33, count 0 2006.285.06:01:42.66#ibcon#flushed, iclass 33, count 0 2006.285.06:01:42.66#ibcon#about to write, iclass 33, count 0 2006.285.06:01:42.66#ibcon#wrote, iclass 33, count 0 2006.285.06:01:42.66#ibcon#about to read 3, iclass 33, count 0 2006.285.06:01:42.70#ibcon#read 3, iclass 33, count 0 2006.285.06:01:42.70#ibcon#about to read 4, iclass 33, count 0 2006.285.06:01:42.70#ibcon#read 4, iclass 33, count 0 2006.285.06:01:42.70#ibcon#about to read 5, iclass 33, count 0 2006.285.06:01:42.70#ibcon#read 5, iclass 33, count 0 2006.285.06:01:42.70#ibcon#about to read 6, iclass 33, count 0 2006.285.06:01:42.70#ibcon#read 6, iclass 33, count 0 2006.285.06:01:42.70#ibcon#end of sib2, iclass 33, count 0 2006.285.06:01:42.70#ibcon#*after write, iclass 33, count 0 2006.285.06:01:42.70#ibcon#*before return 0, iclass 33, count 0 2006.285.06:01:42.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:01:42.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:01:42.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:01:42.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:01:42.70$vck44/va=2,6 2006.285.06:01:42.70#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.06:01:42.70#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.06:01:42.70#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:42.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:01:42.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:01:42.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:01:42.76#ibcon#enter wrdev, iclass 35, count 2 2006.285.06:01:42.76#ibcon#first serial, iclass 35, count 2 2006.285.06:01:42.76#ibcon#enter sib2, iclass 35, count 2 2006.285.06:01:42.76#ibcon#flushed, iclass 35, count 2 2006.285.06:01:42.76#ibcon#about to write, iclass 35, count 2 2006.285.06:01:42.76#ibcon#wrote, iclass 35, count 2 2006.285.06:01:42.76#ibcon#about to read 3, iclass 35, count 2 2006.285.06:01:42.78#ibcon#read 3, iclass 35, count 2 2006.285.06:01:42.78#ibcon#about to read 4, iclass 35, count 2 2006.285.06:01:42.78#ibcon#read 4, iclass 35, count 2 2006.285.06:01:42.78#ibcon#about to read 5, iclass 35, count 2 2006.285.06:01:42.78#ibcon#read 5, iclass 35, count 2 2006.285.06:01:42.78#ibcon#about to read 6, iclass 35, count 2 2006.285.06:01:42.78#ibcon#read 6, iclass 35, count 2 2006.285.06:01:42.78#ibcon#end of sib2, iclass 35, count 2 2006.285.06:01:42.78#ibcon#*mode == 0, iclass 35, count 2 2006.285.06:01:42.78#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.06:01:42.78#ibcon#[25=AT02-06\r\n] 2006.285.06:01:42.78#ibcon#*before write, iclass 35, count 2 2006.285.06:01:42.78#ibcon#enter sib2, iclass 35, count 2 2006.285.06:01:42.78#ibcon#flushed, iclass 35, count 2 2006.285.06:01:42.78#ibcon#about to write, iclass 35, count 2 2006.285.06:01:42.78#ibcon#wrote, iclass 35, count 2 2006.285.06:01:42.78#ibcon#about to read 3, iclass 35, count 2 2006.285.06:01:42.81#ibcon#read 3, iclass 35, count 2 2006.285.06:01:42.81#ibcon#about to read 4, iclass 35, count 2 2006.285.06:01:42.81#ibcon#read 4, iclass 35, count 2 2006.285.06:01:42.81#ibcon#about to read 5, iclass 35, count 2 2006.285.06:01:42.81#ibcon#read 5, iclass 35, count 2 2006.285.06:01:42.81#ibcon#about to read 6, iclass 35, count 2 2006.285.06:01:42.81#ibcon#read 6, iclass 35, count 2 2006.285.06:01:42.81#ibcon#end of sib2, iclass 35, count 2 2006.285.06:01:42.81#ibcon#*after write, iclass 35, count 2 2006.285.06:01:42.81#ibcon#*before return 0, iclass 35, count 2 2006.285.06:01:42.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:01:42.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:01:42.81#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.06:01:42.81#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:42.81#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:01:42.93#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:01:42.93#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:01:42.93#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:01:42.93#ibcon#first serial, iclass 35, count 0 2006.285.06:01:42.93#ibcon#enter sib2, iclass 35, count 0 2006.285.06:01:42.93#ibcon#flushed, iclass 35, count 0 2006.285.06:01:42.93#ibcon#about to write, iclass 35, count 0 2006.285.06:01:42.93#ibcon#wrote, iclass 35, count 0 2006.285.06:01:42.93#ibcon#about to read 3, iclass 35, count 0 2006.285.06:01:42.95#ibcon#read 3, iclass 35, count 0 2006.285.06:01:42.95#ibcon#about to read 4, iclass 35, count 0 2006.285.06:01:42.95#ibcon#read 4, iclass 35, count 0 2006.285.06:01:42.95#ibcon#about to read 5, iclass 35, count 0 2006.285.06:01:42.95#ibcon#read 5, iclass 35, count 0 2006.285.06:01:42.95#ibcon#about to read 6, iclass 35, count 0 2006.285.06:01:42.95#ibcon#read 6, iclass 35, count 0 2006.285.06:01:42.95#ibcon#end of sib2, iclass 35, count 0 2006.285.06:01:42.95#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:01:42.95#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:01:42.95#ibcon#[25=USB\r\n] 2006.285.06:01:42.95#ibcon#*before write, iclass 35, count 0 2006.285.06:01:42.95#ibcon#enter sib2, iclass 35, count 0 2006.285.06:01:42.95#ibcon#flushed, iclass 35, count 0 2006.285.06:01:42.95#ibcon#about to write, iclass 35, count 0 2006.285.06:01:42.95#ibcon#wrote, iclass 35, count 0 2006.285.06:01:42.95#ibcon#about to read 3, iclass 35, count 0 2006.285.06:01:43.00#ibcon#read 3, iclass 35, count 0 2006.285.06:01:43.00#ibcon#about to read 4, iclass 35, count 0 2006.285.06:01:43.00#ibcon#read 4, iclass 35, count 0 2006.285.06:01:43.00#ibcon#about to read 5, iclass 35, count 0 2006.285.06:01:43.00#ibcon#read 5, iclass 35, count 0 2006.285.06:01:43.00#ibcon#about to read 6, iclass 35, count 0 2006.285.06:01:43.00#ibcon#read 6, iclass 35, count 0 2006.285.06:01:43.00#ibcon#end of sib2, iclass 35, count 0 2006.285.06:01:43.00#ibcon#*after write, iclass 35, count 0 2006.285.06:01:43.00#ibcon#*before return 0, iclass 35, count 0 2006.285.06:01:43.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:01:43.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:01:43.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:01:43.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:01:43.00$vck44/valo=3,564.99 2006.285.06:01:43.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.06:01:43.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.06:01:43.00#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:43.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:01:43.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:01:43.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:01:43.00#ibcon#enter wrdev, iclass 37, count 0 2006.285.06:01:43.00#ibcon#first serial, iclass 37, count 0 2006.285.06:01:43.00#ibcon#enter sib2, iclass 37, count 0 2006.285.06:01:43.00#ibcon#flushed, iclass 37, count 0 2006.285.06:01:43.00#ibcon#about to write, iclass 37, count 0 2006.285.06:01:43.00#ibcon#wrote, iclass 37, count 0 2006.285.06:01:43.00#ibcon#about to read 3, iclass 37, count 0 2006.285.06:01:43.01#ibcon#read 3, iclass 37, count 0 2006.285.06:01:43.01#ibcon#about to read 4, iclass 37, count 0 2006.285.06:01:43.01#ibcon#read 4, iclass 37, count 0 2006.285.06:01:43.01#ibcon#about to read 5, iclass 37, count 0 2006.285.06:01:43.01#ibcon#read 5, iclass 37, count 0 2006.285.06:01:43.01#ibcon#about to read 6, iclass 37, count 0 2006.285.06:01:43.01#ibcon#read 6, iclass 37, count 0 2006.285.06:01:43.01#ibcon#end of sib2, iclass 37, count 0 2006.285.06:01:43.01#ibcon#*mode == 0, iclass 37, count 0 2006.285.06:01:43.01#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.06:01:43.01#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:01:43.01#ibcon#*before write, iclass 37, count 0 2006.285.06:01:43.01#ibcon#enter sib2, iclass 37, count 0 2006.285.06:01:43.01#ibcon#flushed, iclass 37, count 0 2006.285.06:01:43.01#ibcon#about to write, iclass 37, count 0 2006.285.06:01:43.01#ibcon#wrote, iclass 37, count 0 2006.285.06:01:43.01#ibcon#about to read 3, iclass 37, count 0 2006.285.06:01:43.05#ibcon#read 3, iclass 37, count 0 2006.285.06:01:43.05#ibcon#about to read 4, iclass 37, count 0 2006.285.06:01:43.05#ibcon#read 4, iclass 37, count 0 2006.285.06:01:43.05#ibcon#about to read 5, iclass 37, count 0 2006.285.06:01:43.05#ibcon#read 5, iclass 37, count 0 2006.285.06:01:43.05#ibcon#about to read 6, iclass 37, count 0 2006.285.06:01:43.05#ibcon#read 6, iclass 37, count 0 2006.285.06:01:43.05#ibcon#end of sib2, iclass 37, count 0 2006.285.06:01:43.05#ibcon#*after write, iclass 37, count 0 2006.285.06:01:43.05#ibcon#*before return 0, iclass 37, count 0 2006.285.06:01:43.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:01:43.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:01:43.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.06:01:43.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.06:01:43.05$vck44/va=3,7 2006.285.06:01:43.05#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.06:01:43.05#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.06:01:43.05#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:43.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:01:43.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:01:43.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:01:43.12#ibcon#enter wrdev, iclass 39, count 2 2006.285.06:01:43.12#ibcon#first serial, iclass 39, count 2 2006.285.06:01:43.12#ibcon#enter sib2, iclass 39, count 2 2006.285.06:01:43.12#ibcon#flushed, iclass 39, count 2 2006.285.06:01:43.12#ibcon#about to write, iclass 39, count 2 2006.285.06:01:43.12#ibcon#wrote, iclass 39, count 2 2006.285.06:01:43.12#ibcon#about to read 3, iclass 39, count 2 2006.285.06:01:43.14#ibcon#read 3, iclass 39, count 2 2006.285.06:01:43.14#ibcon#about to read 4, iclass 39, count 2 2006.285.06:01:43.14#ibcon#read 4, iclass 39, count 2 2006.285.06:01:43.14#ibcon#about to read 5, iclass 39, count 2 2006.285.06:01:43.14#ibcon#read 5, iclass 39, count 2 2006.285.06:01:43.14#ibcon#about to read 6, iclass 39, count 2 2006.285.06:01:43.14#ibcon#read 6, iclass 39, count 2 2006.285.06:01:43.14#ibcon#end of sib2, iclass 39, count 2 2006.285.06:01:43.14#ibcon#*mode == 0, iclass 39, count 2 2006.285.06:01:43.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.06:01:43.14#ibcon#[25=AT03-07\r\n] 2006.285.06:01:43.14#ibcon#*before write, iclass 39, count 2 2006.285.06:01:43.14#ibcon#enter sib2, iclass 39, count 2 2006.285.06:01:43.14#ibcon#flushed, iclass 39, count 2 2006.285.06:01:43.14#ibcon#about to write, iclass 39, count 2 2006.285.06:01:43.14#ibcon#wrote, iclass 39, count 2 2006.285.06:01:43.14#ibcon#about to read 3, iclass 39, count 2 2006.285.06:01:43.17#ibcon#read 3, iclass 39, count 2 2006.285.06:01:43.17#ibcon#about to read 4, iclass 39, count 2 2006.285.06:01:43.17#ibcon#read 4, iclass 39, count 2 2006.285.06:01:43.17#ibcon#about to read 5, iclass 39, count 2 2006.285.06:01:43.17#ibcon#read 5, iclass 39, count 2 2006.285.06:01:43.17#ibcon#about to read 6, iclass 39, count 2 2006.285.06:01:43.17#ibcon#read 6, iclass 39, count 2 2006.285.06:01:43.17#ibcon#end of sib2, iclass 39, count 2 2006.285.06:01:43.17#ibcon#*after write, iclass 39, count 2 2006.285.06:01:43.17#ibcon#*before return 0, iclass 39, count 2 2006.285.06:01:43.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:01:43.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:01:43.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.06:01:43.17#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:43.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:01:43.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:01:43.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:01:43.29#ibcon#enter wrdev, iclass 39, count 0 2006.285.06:01:43.29#ibcon#first serial, iclass 39, count 0 2006.285.06:01:43.29#ibcon#enter sib2, iclass 39, count 0 2006.285.06:01:43.29#ibcon#flushed, iclass 39, count 0 2006.285.06:01:43.29#ibcon#about to write, iclass 39, count 0 2006.285.06:01:43.29#ibcon#wrote, iclass 39, count 0 2006.285.06:01:43.29#ibcon#about to read 3, iclass 39, count 0 2006.285.06:01:43.31#ibcon#read 3, iclass 39, count 0 2006.285.06:01:43.31#ibcon#about to read 4, iclass 39, count 0 2006.285.06:01:43.31#ibcon#read 4, iclass 39, count 0 2006.285.06:01:43.31#ibcon#about to read 5, iclass 39, count 0 2006.285.06:01:43.31#ibcon#read 5, iclass 39, count 0 2006.285.06:01:43.31#ibcon#about to read 6, iclass 39, count 0 2006.285.06:01:43.31#ibcon#read 6, iclass 39, count 0 2006.285.06:01:43.31#ibcon#end of sib2, iclass 39, count 0 2006.285.06:01:43.31#ibcon#*mode == 0, iclass 39, count 0 2006.285.06:01:43.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.06:01:43.31#ibcon#[25=USB\r\n] 2006.285.06:01:43.31#ibcon#*before write, iclass 39, count 0 2006.285.06:01:43.31#ibcon#enter sib2, iclass 39, count 0 2006.285.06:01:43.31#ibcon#flushed, iclass 39, count 0 2006.285.06:01:43.31#ibcon#about to write, iclass 39, count 0 2006.285.06:01:43.31#ibcon#wrote, iclass 39, count 0 2006.285.06:01:43.31#ibcon#about to read 3, iclass 39, count 0 2006.285.06:01:43.34#ibcon#read 3, iclass 39, count 0 2006.285.06:01:43.34#ibcon#about to read 4, iclass 39, count 0 2006.285.06:01:43.34#ibcon#read 4, iclass 39, count 0 2006.285.06:01:43.34#ibcon#about to read 5, iclass 39, count 0 2006.285.06:01:43.34#ibcon#read 5, iclass 39, count 0 2006.285.06:01:43.34#ibcon#about to read 6, iclass 39, count 0 2006.285.06:01:43.34#ibcon#read 6, iclass 39, count 0 2006.285.06:01:43.34#ibcon#end of sib2, iclass 39, count 0 2006.285.06:01:43.34#ibcon#*after write, iclass 39, count 0 2006.285.06:01:43.34#ibcon#*before return 0, iclass 39, count 0 2006.285.06:01:43.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:01:43.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:01:43.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.06:01:43.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.06:01:43.34$vck44/valo=4,624.99 2006.285.06:01:43.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.06:01:43.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.06:01:43.34#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:43.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:01:43.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:01:43.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:01:43.34#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:01:43.34#ibcon#first serial, iclass 3, count 0 2006.285.06:01:43.34#ibcon#enter sib2, iclass 3, count 0 2006.285.06:01:43.34#ibcon#flushed, iclass 3, count 0 2006.285.06:01:43.34#ibcon#about to write, iclass 3, count 0 2006.285.06:01:43.34#ibcon#wrote, iclass 3, count 0 2006.285.06:01:43.34#ibcon#about to read 3, iclass 3, count 0 2006.285.06:01:43.36#ibcon#read 3, iclass 3, count 0 2006.285.06:01:43.36#ibcon#about to read 4, iclass 3, count 0 2006.285.06:01:43.36#ibcon#read 4, iclass 3, count 0 2006.285.06:01:43.36#ibcon#about to read 5, iclass 3, count 0 2006.285.06:01:43.36#ibcon#read 5, iclass 3, count 0 2006.285.06:01:43.36#ibcon#about to read 6, iclass 3, count 0 2006.285.06:01:43.36#ibcon#read 6, iclass 3, count 0 2006.285.06:01:43.36#ibcon#end of sib2, iclass 3, count 0 2006.285.06:01:43.36#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:01:43.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:01:43.36#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:01:43.36#ibcon#*before write, iclass 3, count 0 2006.285.06:01:43.36#ibcon#enter sib2, iclass 3, count 0 2006.285.06:01:43.36#ibcon#flushed, iclass 3, count 0 2006.285.06:01:43.36#ibcon#about to write, iclass 3, count 0 2006.285.06:01:43.36#ibcon#wrote, iclass 3, count 0 2006.285.06:01:43.36#ibcon#about to read 3, iclass 3, count 0 2006.285.06:01:43.40#ibcon#read 3, iclass 3, count 0 2006.285.06:01:43.40#ibcon#about to read 4, iclass 3, count 0 2006.285.06:01:43.40#ibcon#read 4, iclass 3, count 0 2006.285.06:01:43.40#ibcon#about to read 5, iclass 3, count 0 2006.285.06:01:43.40#ibcon#read 5, iclass 3, count 0 2006.285.06:01:43.40#ibcon#about to read 6, iclass 3, count 0 2006.285.06:01:43.40#ibcon#read 6, iclass 3, count 0 2006.285.06:01:43.40#ibcon#end of sib2, iclass 3, count 0 2006.285.06:01:43.40#ibcon#*after write, iclass 3, count 0 2006.285.06:01:43.40#ibcon#*before return 0, iclass 3, count 0 2006.285.06:01:43.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:01:43.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:01:43.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:01:43.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:01:43.40$vck44/va=4,6 2006.285.06:01:43.40#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.06:01:43.40#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.06:01:43.40#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:43.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:01:43.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:01:43.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:01:43.46#ibcon#enter wrdev, iclass 5, count 2 2006.285.06:01:43.46#ibcon#first serial, iclass 5, count 2 2006.285.06:01:43.46#ibcon#enter sib2, iclass 5, count 2 2006.285.06:01:43.46#ibcon#flushed, iclass 5, count 2 2006.285.06:01:43.46#ibcon#about to write, iclass 5, count 2 2006.285.06:01:43.46#ibcon#wrote, iclass 5, count 2 2006.285.06:01:43.46#ibcon#about to read 3, iclass 5, count 2 2006.285.06:01:43.48#ibcon#read 3, iclass 5, count 2 2006.285.06:01:43.48#ibcon#about to read 4, iclass 5, count 2 2006.285.06:01:43.48#ibcon#read 4, iclass 5, count 2 2006.285.06:01:43.48#ibcon#about to read 5, iclass 5, count 2 2006.285.06:01:43.48#ibcon#read 5, iclass 5, count 2 2006.285.06:01:43.48#ibcon#about to read 6, iclass 5, count 2 2006.285.06:01:43.48#ibcon#read 6, iclass 5, count 2 2006.285.06:01:43.48#ibcon#end of sib2, iclass 5, count 2 2006.285.06:01:43.48#ibcon#*mode == 0, iclass 5, count 2 2006.285.06:01:43.48#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.06:01:43.48#ibcon#[25=AT04-06\r\n] 2006.285.06:01:43.48#ibcon#*before write, iclass 5, count 2 2006.285.06:01:43.48#ibcon#enter sib2, iclass 5, count 2 2006.285.06:01:43.48#ibcon#flushed, iclass 5, count 2 2006.285.06:01:43.48#ibcon#about to write, iclass 5, count 2 2006.285.06:01:43.48#ibcon#wrote, iclass 5, count 2 2006.285.06:01:43.48#ibcon#about to read 3, iclass 5, count 2 2006.285.06:01:43.51#ibcon#read 3, iclass 5, count 2 2006.285.06:01:43.51#ibcon#about to read 4, iclass 5, count 2 2006.285.06:01:43.51#ibcon#read 4, iclass 5, count 2 2006.285.06:01:43.51#ibcon#about to read 5, iclass 5, count 2 2006.285.06:01:43.51#ibcon#read 5, iclass 5, count 2 2006.285.06:01:43.51#ibcon#about to read 6, iclass 5, count 2 2006.285.06:01:43.51#ibcon#read 6, iclass 5, count 2 2006.285.06:01:43.51#ibcon#end of sib2, iclass 5, count 2 2006.285.06:01:43.51#ibcon#*after write, iclass 5, count 2 2006.285.06:01:43.51#ibcon#*before return 0, iclass 5, count 2 2006.285.06:01:43.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:01:43.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:01:43.51#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.06:01:43.51#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:43.51#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:01:43.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:01:43.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:01:43.63#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:01:43.63#ibcon#first serial, iclass 5, count 0 2006.285.06:01:43.63#ibcon#enter sib2, iclass 5, count 0 2006.285.06:01:43.63#ibcon#flushed, iclass 5, count 0 2006.285.06:01:43.63#ibcon#about to write, iclass 5, count 0 2006.285.06:01:43.63#ibcon#wrote, iclass 5, count 0 2006.285.06:01:43.63#ibcon#about to read 3, iclass 5, count 0 2006.285.06:01:43.65#ibcon#read 3, iclass 5, count 0 2006.285.06:01:43.65#ibcon#about to read 4, iclass 5, count 0 2006.285.06:01:43.65#ibcon#read 4, iclass 5, count 0 2006.285.06:01:43.65#ibcon#about to read 5, iclass 5, count 0 2006.285.06:01:43.65#ibcon#read 5, iclass 5, count 0 2006.285.06:01:43.65#ibcon#about to read 6, iclass 5, count 0 2006.285.06:01:43.65#ibcon#read 6, iclass 5, count 0 2006.285.06:01:43.65#ibcon#end of sib2, iclass 5, count 0 2006.285.06:01:43.65#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:01:43.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:01:43.65#ibcon#[25=USB\r\n] 2006.285.06:01:43.65#ibcon#*before write, iclass 5, count 0 2006.285.06:01:43.65#ibcon#enter sib2, iclass 5, count 0 2006.285.06:01:43.65#ibcon#flushed, iclass 5, count 0 2006.285.06:01:43.65#ibcon#about to write, iclass 5, count 0 2006.285.06:01:43.65#ibcon#wrote, iclass 5, count 0 2006.285.06:01:43.65#ibcon#about to read 3, iclass 5, count 0 2006.285.06:01:43.68#ibcon#read 3, iclass 5, count 0 2006.285.06:01:43.68#ibcon#about to read 4, iclass 5, count 0 2006.285.06:01:43.68#ibcon#read 4, iclass 5, count 0 2006.285.06:01:43.68#ibcon#about to read 5, iclass 5, count 0 2006.285.06:01:43.68#ibcon#read 5, iclass 5, count 0 2006.285.06:01:43.68#ibcon#about to read 6, iclass 5, count 0 2006.285.06:01:43.68#ibcon#read 6, iclass 5, count 0 2006.285.06:01:43.68#ibcon#end of sib2, iclass 5, count 0 2006.285.06:01:43.68#ibcon#*after write, iclass 5, count 0 2006.285.06:01:43.68#ibcon#*before return 0, iclass 5, count 0 2006.285.06:01:43.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:01:43.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:01:43.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:01:43.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:01:43.68$vck44/valo=5,734.99 2006.285.06:01:43.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.06:01:43.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.06:01:43.68#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:43.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:01:43.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:01:43.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:01:43.68#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:01:43.68#ibcon#first serial, iclass 7, count 0 2006.285.06:01:43.68#ibcon#enter sib2, iclass 7, count 0 2006.285.06:01:43.68#ibcon#flushed, iclass 7, count 0 2006.285.06:01:43.68#ibcon#about to write, iclass 7, count 0 2006.285.06:01:43.68#ibcon#wrote, iclass 7, count 0 2006.285.06:01:43.68#ibcon#about to read 3, iclass 7, count 0 2006.285.06:01:43.70#ibcon#read 3, iclass 7, count 0 2006.285.06:01:43.70#ibcon#about to read 4, iclass 7, count 0 2006.285.06:01:43.70#ibcon#read 4, iclass 7, count 0 2006.285.06:01:43.70#ibcon#about to read 5, iclass 7, count 0 2006.285.06:01:43.70#ibcon#read 5, iclass 7, count 0 2006.285.06:01:43.70#ibcon#about to read 6, iclass 7, count 0 2006.285.06:01:43.70#ibcon#read 6, iclass 7, count 0 2006.285.06:01:43.70#ibcon#end of sib2, iclass 7, count 0 2006.285.06:01:43.70#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:01:43.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:01:43.70#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:01:43.70#ibcon#*before write, iclass 7, count 0 2006.285.06:01:43.70#ibcon#enter sib2, iclass 7, count 0 2006.285.06:01:43.70#ibcon#flushed, iclass 7, count 0 2006.285.06:01:43.70#ibcon#about to write, iclass 7, count 0 2006.285.06:01:43.70#ibcon#wrote, iclass 7, count 0 2006.285.06:01:43.70#ibcon#about to read 3, iclass 7, count 0 2006.285.06:01:43.74#ibcon#read 3, iclass 7, count 0 2006.285.06:01:43.74#ibcon#about to read 4, iclass 7, count 0 2006.285.06:01:43.74#ibcon#read 4, iclass 7, count 0 2006.285.06:01:43.74#ibcon#about to read 5, iclass 7, count 0 2006.285.06:01:43.74#ibcon#read 5, iclass 7, count 0 2006.285.06:01:43.74#ibcon#about to read 6, iclass 7, count 0 2006.285.06:01:43.74#ibcon#read 6, iclass 7, count 0 2006.285.06:01:43.74#ibcon#end of sib2, iclass 7, count 0 2006.285.06:01:43.74#ibcon#*after write, iclass 7, count 0 2006.285.06:01:43.74#ibcon#*before return 0, iclass 7, count 0 2006.285.06:01:43.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:01:43.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:01:43.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:01:43.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:01:43.74$vck44/va=5,3 2006.285.06:01:43.74#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.06:01:43.74#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.06:01:43.74#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:43.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:01:43.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:01:43.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:01:43.80#ibcon#enter wrdev, iclass 11, count 2 2006.285.06:01:43.80#ibcon#first serial, iclass 11, count 2 2006.285.06:01:43.80#ibcon#enter sib2, iclass 11, count 2 2006.285.06:01:43.80#ibcon#flushed, iclass 11, count 2 2006.285.06:01:43.80#ibcon#about to write, iclass 11, count 2 2006.285.06:01:43.80#ibcon#wrote, iclass 11, count 2 2006.285.06:01:43.80#ibcon#about to read 3, iclass 11, count 2 2006.285.06:01:43.82#ibcon#read 3, iclass 11, count 2 2006.285.06:01:43.82#ibcon#about to read 4, iclass 11, count 2 2006.285.06:01:43.82#ibcon#read 4, iclass 11, count 2 2006.285.06:01:43.82#ibcon#about to read 5, iclass 11, count 2 2006.285.06:01:43.82#ibcon#read 5, iclass 11, count 2 2006.285.06:01:43.82#ibcon#about to read 6, iclass 11, count 2 2006.285.06:01:43.82#ibcon#read 6, iclass 11, count 2 2006.285.06:01:43.82#ibcon#end of sib2, iclass 11, count 2 2006.285.06:01:43.82#ibcon#*mode == 0, iclass 11, count 2 2006.285.06:01:43.82#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.06:01:43.82#ibcon#[25=AT05-03\r\n] 2006.285.06:01:43.82#ibcon#*before write, iclass 11, count 2 2006.285.06:01:43.82#ibcon#enter sib2, iclass 11, count 2 2006.285.06:01:43.82#ibcon#flushed, iclass 11, count 2 2006.285.06:01:43.82#ibcon#about to write, iclass 11, count 2 2006.285.06:01:43.82#ibcon#wrote, iclass 11, count 2 2006.285.06:01:43.82#ibcon#about to read 3, iclass 11, count 2 2006.285.06:01:43.85#ibcon#read 3, iclass 11, count 2 2006.285.06:01:43.85#ibcon#about to read 4, iclass 11, count 2 2006.285.06:01:43.85#ibcon#read 4, iclass 11, count 2 2006.285.06:01:43.85#ibcon#about to read 5, iclass 11, count 2 2006.285.06:01:43.85#ibcon#read 5, iclass 11, count 2 2006.285.06:01:43.85#ibcon#about to read 6, iclass 11, count 2 2006.285.06:01:43.85#ibcon#read 6, iclass 11, count 2 2006.285.06:01:43.85#ibcon#end of sib2, iclass 11, count 2 2006.285.06:01:43.85#ibcon#*after write, iclass 11, count 2 2006.285.06:01:43.85#ibcon#*before return 0, iclass 11, count 2 2006.285.06:01:43.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:01:43.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:01:43.85#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.06:01:43.85#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:43.85#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:01:43.97#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:01:43.97#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:01:43.97#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:01:43.97#ibcon#first serial, iclass 11, count 0 2006.285.06:01:43.97#ibcon#enter sib2, iclass 11, count 0 2006.285.06:01:43.97#ibcon#flushed, iclass 11, count 0 2006.285.06:01:43.97#ibcon#about to write, iclass 11, count 0 2006.285.06:01:43.97#ibcon#wrote, iclass 11, count 0 2006.285.06:01:43.97#ibcon#about to read 3, iclass 11, count 0 2006.285.06:01:43.99#ibcon#read 3, iclass 11, count 0 2006.285.06:01:43.99#ibcon#about to read 4, iclass 11, count 0 2006.285.06:01:43.99#ibcon#read 4, iclass 11, count 0 2006.285.06:01:43.99#ibcon#about to read 5, iclass 11, count 0 2006.285.06:01:43.99#ibcon#read 5, iclass 11, count 0 2006.285.06:01:43.99#ibcon#about to read 6, iclass 11, count 0 2006.285.06:01:43.99#ibcon#read 6, iclass 11, count 0 2006.285.06:01:43.99#ibcon#end of sib2, iclass 11, count 0 2006.285.06:01:43.99#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:01:43.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:01:43.99#ibcon#[25=USB\r\n] 2006.285.06:01:43.99#ibcon#*before write, iclass 11, count 0 2006.285.06:01:43.99#ibcon#enter sib2, iclass 11, count 0 2006.285.06:01:43.99#ibcon#flushed, iclass 11, count 0 2006.285.06:01:43.99#ibcon#about to write, iclass 11, count 0 2006.285.06:01:43.99#ibcon#wrote, iclass 11, count 0 2006.285.06:01:43.99#ibcon#about to read 3, iclass 11, count 0 2006.285.06:01:44.02#ibcon#read 3, iclass 11, count 0 2006.285.06:01:44.02#ibcon#about to read 4, iclass 11, count 0 2006.285.06:01:44.02#ibcon#read 4, iclass 11, count 0 2006.285.06:01:44.02#ibcon#about to read 5, iclass 11, count 0 2006.285.06:01:44.02#ibcon#read 5, iclass 11, count 0 2006.285.06:01:44.02#ibcon#about to read 6, iclass 11, count 0 2006.285.06:01:44.02#ibcon#read 6, iclass 11, count 0 2006.285.06:01:44.02#ibcon#end of sib2, iclass 11, count 0 2006.285.06:01:44.02#ibcon#*after write, iclass 11, count 0 2006.285.06:01:44.02#ibcon#*before return 0, iclass 11, count 0 2006.285.06:01:44.02#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:01:44.02#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:01:44.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:01:44.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:01:44.02$vck44/valo=6,814.99 2006.285.06:01:44.02#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.06:01:44.02#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.06:01:44.02#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:44.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:01:44.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:01:44.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:01:44.02#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:01:44.02#ibcon#first serial, iclass 13, count 0 2006.285.06:01:44.02#ibcon#enter sib2, iclass 13, count 0 2006.285.06:01:44.02#ibcon#flushed, iclass 13, count 0 2006.285.06:01:44.02#ibcon#about to write, iclass 13, count 0 2006.285.06:01:44.02#ibcon#wrote, iclass 13, count 0 2006.285.06:01:44.02#ibcon#about to read 3, iclass 13, count 0 2006.285.06:01:44.04#ibcon#read 3, iclass 13, count 0 2006.285.06:01:44.04#ibcon#about to read 4, iclass 13, count 0 2006.285.06:01:44.04#ibcon#read 4, iclass 13, count 0 2006.285.06:01:44.04#ibcon#about to read 5, iclass 13, count 0 2006.285.06:01:44.04#ibcon#read 5, iclass 13, count 0 2006.285.06:01:44.04#ibcon#about to read 6, iclass 13, count 0 2006.285.06:01:44.04#ibcon#read 6, iclass 13, count 0 2006.285.06:01:44.04#ibcon#end of sib2, iclass 13, count 0 2006.285.06:01:44.04#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:01:44.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:01:44.04#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:01:44.04#ibcon#*before write, iclass 13, count 0 2006.285.06:01:44.04#ibcon#enter sib2, iclass 13, count 0 2006.285.06:01:44.04#ibcon#flushed, iclass 13, count 0 2006.285.06:01:44.04#ibcon#about to write, iclass 13, count 0 2006.285.06:01:44.04#ibcon#wrote, iclass 13, count 0 2006.285.06:01:44.04#ibcon#about to read 3, iclass 13, count 0 2006.285.06:01:44.08#ibcon#read 3, iclass 13, count 0 2006.285.06:01:44.08#ibcon#about to read 4, iclass 13, count 0 2006.285.06:01:44.08#ibcon#read 4, iclass 13, count 0 2006.285.06:01:44.08#ibcon#about to read 5, iclass 13, count 0 2006.285.06:01:44.08#ibcon#read 5, iclass 13, count 0 2006.285.06:01:44.08#ibcon#about to read 6, iclass 13, count 0 2006.285.06:01:44.08#ibcon#read 6, iclass 13, count 0 2006.285.06:01:44.08#ibcon#end of sib2, iclass 13, count 0 2006.285.06:01:44.08#ibcon#*after write, iclass 13, count 0 2006.285.06:01:44.08#ibcon#*before return 0, iclass 13, count 0 2006.285.06:01:44.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:01:44.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:01:44.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:01:44.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:01:44.08$vck44/va=6,4 2006.285.06:01:44.08#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.06:01:44.08#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.06:01:44.08#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:44.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:01:44.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:01:44.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:01:44.14#ibcon#enter wrdev, iclass 15, count 2 2006.285.06:01:44.14#ibcon#first serial, iclass 15, count 2 2006.285.06:01:44.14#ibcon#enter sib2, iclass 15, count 2 2006.285.06:01:44.14#ibcon#flushed, iclass 15, count 2 2006.285.06:01:44.14#ibcon#about to write, iclass 15, count 2 2006.285.06:01:44.14#ibcon#wrote, iclass 15, count 2 2006.285.06:01:44.14#ibcon#about to read 3, iclass 15, count 2 2006.285.06:01:44.16#ibcon#read 3, iclass 15, count 2 2006.285.06:01:44.16#ibcon#about to read 4, iclass 15, count 2 2006.285.06:01:44.16#ibcon#read 4, iclass 15, count 2 2006.285.06:01:44.16#ibcon#about to read 5, iclass 15, count 2 2006.285.06:01:44.16#ibcon#read 5, iclass 15, count 2 2006.285.06:01:44.16#ibcon#about to read 6, iclass 15, count 2 2006.285.06:01:44.16#ibcon#read 6, iclass 15, count 2 2006.285.06:01:44.16#ibcon#end of sib2, iclass 15, count 2 2006.285.06:01:44.16#ibcon#*mode == 0, iclass 15, count 2 2006.285.06:01:44.16#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.06:01:44.16#ibcon#[25=AT06-04\r\n] 2006.285.06:01:44.16#ibcon#*before write, iclass 15, count 2 2006.285.06:01:44.16#ibcon#enter sib2, iclass 15, count 2 2006.285.06:01:44.16#ibcon#flushed, iclass 15, count 2 2006.285.06:01:44.16#ibcon#about to write, iclass 15, count 2 2006.285.06:01:44.16#ibcon#wrote, iclass 15, count 2 2006.285.06:01:44.16#ibcon#about to read 3, iclass 15, count 2 2006.285.06:01:44.19#ibcon#read 3, iclass 15, count 2 2006.285.06:01:44.19#ibcon#about to read 4, iclass 15, count 2 2006.285.06:01:44.19#ibcon#read 4, iclass 15, count 2 2006.285.06:01:44.19#ibcon#about to read 5, iclass 15, count 2 2006.285.06:01:44.19#ibcon#read 5, iclass 15, count 2 2006.285.06:01:44.19#ibcon#about to read 6, iclass 15, count 2 2006.285.06:01:44.19#ibcon#read 6, iclass 15, count 2 2006.285.06:01:44.19#ibcon#end of sib2, iclass 15, count 2 2006.285.06:01:44.19#ibcon#*after write, iclass 15, count 2 2006.285.06:01:44.19#ibcon#*before return 0, iclass 15, count 2 2006.285.06:01:44.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:01:44.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:01:44.19#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.06:01:44.19#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:44.19#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:01:44.31#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:01:44.31#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:01:44.31#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:01:44.31#ibcon#first serial, iclass 15, count 0 2006.285.06:01:44.31#ibcon#enter sib2, iclass 15, count 0 2006.285.06:01:44.31#ibcon#flushed, iclass 15, count 0 2006.285.06:01:44.31#ibcon#about to write, iclass 15, count 0 2006.285.06:01:44.31#ibcon#wrote, iclass 15, count 0 2006.285.06:01:44.31#ibcon#about to read 3, iclass 15, count 0 2006.285.06:01:44.33#ibcon#read 3, iclass 15, count 0 2006.285.06:01:44.33#ibcon#about to read 4, iclass 15, count 0 2006.285.06:01:44.33#ibcon#read 4, iclass 15, count 0 2006.285.06:01:44.33#ibcon#about to read 5, iclass 15, count 0 2006.285.06:01:44.33#ibcon#read 5, iclass 15, count 0 2006.285.06:01:44.33#ibcon#about to read 6, iclass 15, count 0 2006.285.06:01:44.33#ibcon#read 6, iclass 15, count 0 2006.285.06:01:44.33#ibcon#end of sib2, iclass 15, count 0 2006.285.06:01:44.33#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:01:44.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:01:44.33#ibcon#[25=USB\r\n] 2006.285.06:01:44.33#ibcon#*before write, iclass 15, count 0 2006.285.06:01:44.33#ibcon#enter sib2, iclass 15, count 0 2006.285.06:01:44.33#ibcon#flushed, iclass 15, count 0 2006.285.06:01:44.33#ibcon#about to write, iclass 15, count 0 2006.285.06:01:44.33#ibcon#wrote, iclass 15, count 0 2006.285.06:01:44.33#ibcon#about to read 3, iclass 15, count 0 2006.285.06:01:44.36#ibcon#read 3, iclass 15, count 0 2006.285.06:01:44.36#ibcon#about to read 4, iclass 15, count 0 2006.285.06:01:44.36#ibcon#read 4, iclass 15, count 0 2006.285.06:01:44.36#ibcon#about to read 5, iclass 15, count 0 2006.285.06:01:44.36#ibcon#read 5, iclass 15, count 0 2006.285.06:01:44.36#ibcon#about to read 6, iclass 15, count 0 2006.285.06:01:44.36#ibcon#read 6, iclass 15, count 0 2006.285.06:01:44.36#ibcon#end of sib2, iclass 15, count 0 2006.285.06:01:44.36#ibcon#*after write, iclass 15, count 0 2006.285.06:01:44.36#ibcon#*before return 0, iclass 15, count 0 2006.285.06:01:44.36#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:01:44.36#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:01:44.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:01:44.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:01:44.36$vck44/valo=7,864.99 2006.285.06:01:44.36#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.06:01:44.36#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.06:01:44.36#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:44.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:01:44.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:01:44.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:01:44.36#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:01:44.36#ibcon#first serial, iclass 17, count 0 2006.285.06:01:44.36#ibcon#enter sib2, iclass 17, count 0 2006.285.06:01:44.36#ibcon#flushed, iclass 17, count 0 2006.285.06:01:44.36#ibcon#about to write, iclass 17, count 0 2006.285.06:01:44.36#ibcon#wrote, iclass 17, count 0 2006.285.06:01:44.36#ibcon#about to read 3, iclass 17, count 0 2006.285.06:01:44.38#ibcon#read 3, iclass 17, count 0 2006.285.06:01:44.38#ibcon#about to read 4, iclass 17, count 0 2006.285.06:01:44.38#ibcon#read 4, iclass 17, count 0 2006.285.06:01:44.38#ibcon#about to read 5, iclass 17, count 0 2006.285.06:01:44.38#ibcon#read 5, iclass 17, count 0 2006.285.06:01:44.38#ibcon#about to read 6, iclass 17, count 0 2006.285.06:01:44.38#ibcon#read 6, iclass 17, count 0 2006.285.06:01:44.38#ibcon#end of sib2, iclass 17, count 0 2006.285.06:01:44.38#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:01:44.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:01:44.38#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:01:44.38#ibcon#*before write, iclass 17, count 0 2006.285.06:01:44.38#ibcon#enter sib2, iclass 17, count 0 2006.285.06:01:44.38#ibcon#flushed, iclass 17, count 0 2006.285.06:01:44.38#ibcon#about to write, iclass 17, count 0 2006.285.06:01:44.38#ibcon#wrote, iclass 17, count 0 2006.285.06:01:44.38#ibcon#about to read 3, iclass 17, count 0 2006.285.06:01:44.42#ibcon#read 3, iclass 17, count 0 2006.285.06:01:44.42#ibcon#about to read 4, iclass 17, count 0 2006.285.06:01:44.42#ibcon#read 4, iclass 17, count 0 2006.285.06:01:44.42#ibcon#about to read 5, iclass 17, count 0 2006.285.06:01:44.42#ibcon#read 5, iclass 17, count 0 2006.285.06:01:44.42#ibcon#about to read 6, iclass 17, count 0 2006.285.06:01:44.42#ibcon#read 6, iclass 17, count 0 2006.285.06:01:44.42#ibcon#end of sib2, iclass 17, count 0 2006.285.06:01:44.42#ibcon#*after write, iclass 17, count 0 2006.285.06:01:44.42#ibcon#*before return 0, iclass 17, count 0 2006.285.06:01:44.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:01:44.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:01:44.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:01:44.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:01:44.42$vck44/va=7,4 2006.285.06:01:44.42#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.06:01:44.42#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.06:01:44.42#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:44.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:01:44.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:01:44.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:01:44.48#ibcon#enter wrdev, iclass 19, count 2 2006.285.06:01:44.48#ibcon#first serial, iclass 19, count 2 2006.285.06:01:44.48#ibcon#enter sib2, iclass 19, count 2 2006.285.06:01:44.48#ibcon#flushed, iclass 19, count 2 2006.285.06:01:44.48#ibcon#about to write, iclass 19, count 2 2006.285.06:01:44.48#ibcon#wrote, iclass 19, count 2 2006.285.06:01:44.48#ibcon#about to read 3, iclass 19, count 2 2006.285.06:01:44.50#ibcon#read 3, iclass 19, count 2 2006.285.06:01:44.50#ibcon#about to read 4, iclass 19, count 2 2006.285.06:01:44.50#ibcon#read 4, iclass 19, count 2 2006.285.06:01:44.50#ibcon#about to read 5, iclass 19, count 2 2006.285.06:01:44.50#ibcon#read 5, iclass 19, count 2 2006.285.06:01:44.50#ibcon#about to read 6, iclass 19, count 2 2006.285.06:01:44.50#ibcon#read 6, iclass 19, count 2 2006.285.06:01:44.50#ibcon#end of sib2, iclass 19, count 2 2006.285.06:01:44.50#ibcon#*mode == 0, iclass 19, count 2 2006.285.06:01:44.50#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.06:01:44.50#ibcon#[25=AT07-04\r\n] 2006.285.06:01:44.50#ibcon#*before write, iclass 19, count 2 2006.285.06:01:44.50#ibcon#enter sib2, iclass 19, count 2 2006.285.06:01:44.50#ibcon#flushed, iclass 19, count 2 2006.285.06:01:44.50#ibcon#about to write, iclass 19, count 2 2006.285.06:01:44.50#ibcon#wrote, iclass 19, count 2 2006.285.06:01:44.50#ibcon#about to read 3, iclass 19, count 2 2006.285.06:01:44.53#ibcon#read 3, iclass 19, count 2 2006.285.06:01:44.53#ibcon#about to read 4, iclass 19, count 2 2006.285.06:01:44.53#ibcon#read 4, iclass 19, count 2 2006.285.06:01:44.53#ibcon#about to read 5, iclass 19, count 2 2006.285.06:01:44.53#ibcon#read 5, iclass 19, count 2 2006.285.06:01:44.53#ibcon#about to read 6, iclass 19, count 2 2006.285.06:01:44.53#ibcon#read 6, iclass 19, count 2 2006.285.06:01:44.53#ibcon#end of sib2, iclass 19, count 2 2006.285.06:01:44.53#ibcon#*after write, iclass 19, count 2 2006.285.06:01:44.53#ibcon#*before return 0, iclass 19, count 2 2006.285.06:01:44.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:01:44.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:01:44.53#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.06:01:44.53#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:44.53#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:01:44.65#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:01:44.65#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:01:44.65#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:01:44.65#ibcon#first serial, iclass 19, count 0 2006.285.06:01:44.65#ibcon#enter sib2, iclass 19, count 0 2006.285.06:01:44.65#ibcon#flushed, iclass 19, count 0 2006.285.06:01:44.65#ibcon#about to write, iclass 19, count 0 2006.285.06:01:44.65#ibcon#wrote, iclass 19, count 0 2006.285.06:01:44.65#ibcon#about to read 3, iclass 19, count 0 2006.285.06:01:44.67#ibcon#read 3, iclass 19, count 0 2006.285.06:01:44.67#ibcon#about to read 4, iclass 19, count 0 2006.285.06:01:44.67#ibcon#read 4, iclass 19, count 0 2006.285.06:01:44.67#ibcon#about to read 5, iclass 19, count 0 2006.285.06:01:44.67#ibcon#read 5, iclass 19, count 0 2006.285.06:01:44.67#ibcon#about to read 6, iclass 19, count 0 2006.285.06:01:44.67#ibcon#read 6, iclass 19, count 0 2006.285.06:01:44.67#ibcon#end of sib2, iclass 19, count 0 2006.285.06:01:44.67#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:01:44.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:01:44.67#ibcon#[25=USB\r\n] 2006.285.06:01:44.67#ibcon#*before write, iclass 19, count 0 2006.285.06:01:44.67#ibcon#enter sib2, iclass 19, count 0 2006.285.06:01:44.67#ibcon#flushed, iclass 19, count 0 2006.285.06:01:44.67#ibcon#about to write, iclass 19, count 0 2006.285.06:01:44.67#ibcon#wrote, iclass 19, count 0 2006.285.06:01:44.67#ibcon#about to read 3, iclass 19, count 0 2006.285.06:01:44.70#ibcon#read 3, iclass 19, count 0 2006.285.06:01:44.70#ibcon#about to read 4, iclass 19, count 0 2006.285.06:01:44.70#ibcon#read 4, iclass 19, count 0 2006.285.06:01:44.70#ibcon#about to read 5, iclass 19, count 0 2006.285.06:01:44.70#ibcon#read 5, iclass 19, count 0 2006.285.06:01:44.70#ibcon#about to read 6, iclass 19, count 0 2006.285.06:01:44.70#ibcon#read 6, iclass 19, count 0 2006.285.06:01:44.70#ibcon#end of sib2, iclass 19, count 0 2006.285.06:01:44.70#ibcon#*after write, iclass 19, count 0 2006.285.06:01:44.70#ibcon#*before return 0, iclass 19, count 0 2006.285.06:01:44.70#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:01:44.70#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:01:44.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:01:44.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:01:44.70$vck44/valo=8,884.99 2006.285.06:01:44.70#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.06:01:44.70#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.06:01:44.70#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:44.70#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:01:44.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:01:44.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:01:44.70#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:01:44.70#ibcon#first serial, iclass 21, count 0 2006.285.06:01:44.70#ibcon#enter sib2, iclass 21, count 0 2006.285.06:01:44.70#ibcon#flushed, iclass 21, count 0 2006.285.06:01:44.70#ibcon#about to write, iclass 21, count 0 2006.285.06:01:44.70#ibcon#wrote, iclass 21, count 0 2006.285.06:01:44.70#ibcon#about to read 3, iclass 21, count 0 2006.285.06:01:44.72#ibcon#read 3, iclass 21, count 0 2006.285.06:01:44.72#ibcon#about to read 4, iclass 21, count 0 2006.285.06:01:44.72#ibcon#read 4, iclass 21, count 0 2006.285.06:01:44.72#ibcon#about to read 5, iclass 21, count 0 2006.285.06:01:44.72#ibcon#read 5, iclass 21, count 0 2006.285.06:01:44.72#ibcon#about to read 6, iclass 21, count 0 2006.285.06:01:44.72#ibcon#read 6, iclass 21, count 0 2006.285.06:01:44.72#ibcon#end of sib2, iclass 21, count 0 2006.285.06:01:44.72#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:01:44.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:01:44.72#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:01:44.72#ibcon#*before write, iclass 21, count 0 2006.285.06:01:44.72#ibcon#enter sib2, iclass 21, count 0 2006.285.06:01:44.72#ibcon#flushed, iclass 21, count 0 2006.285.06:01:44.72#ibcon#about to write, iclass 21, count 0 2006.285.06:01:44.72#ibcon#wrote, iclass 21, count 0 2006.285.06:01:44.72#ibcon#about to read 3, iclass 21, count 0 2006.285.06:01:44.76#ibcon#read 3, iclass 21, count 0 2006.285.06:01:44.76#ibcon#about to read 4, iclass 21, count 0 2006.285.06:01:44.76#ibcon#read 4, iclass 21, count 0 2006.285.06:01:44.76#ibcon#about to read 5, iclass 21, count 0 2006.285.06:01:44.76#ibcon#read 5, iclass 21, count 0 2006.285.06:01:44.76#ibcon#about to read 6, iclass 21, count 0 2006.285.06:01:44.76#ibcon#read 6, iclass 21, count 0 2006.285.06:01:44.76#ibcon#end of sib2, iclass 21, count 0 2006.285.06:01:44.76#ibcon#*after write, iclass 21, count 0 2006.285.06:01:44.76#ibcon#*before return 0, iclass 21, count 0 2006.285.06:01:44.76#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:01:44.76#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:01:44.76#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:01:44.76#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:01:44.76$vck44/va=8,3 2006.285.06:01:44.76#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.06:01:44.76#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.06:01:44.76#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:44.76#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:01:44.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:01:44.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:01:44.82#ibcon#enter wrdev, iclass 23, count 2 2006.285.06:01:44.82#ibcon#first serial, iclass 23, count 2 2006.285.06:01:44.82#ibcon#enter sib2, iclass 23, count 2 2006.285.06:01:44.82#ibcon#flushed, iclass 23, count 2 2006.285.06:01:44.82#ibcon#about to write, iclass 23, count 2 2006.285.06:01:44.82#ibcon#wrote, iclass 23, count 2 2006.285.06:01:44.82#ibcon#about to read 3, iclass 23, count 2 2006.285.06:01:44.84#ibcon#read 3, iclass 23, count 2 2006.285.06:01:44.84#ibcon#about to read 4, iclass 23, count 2 2006.285.06:01:44.84#ibcon#read 4, iclass 23, count 2 2006.285.06:01:44.84#ibcon#about to read 5, iclass 23, count 2 2006.285.06:01:44.84#ibcon#read 5, iclass 23, count 2 2006.285.06:01:44.84#ibcon#about to read 6, iclass 23, count 2 2006.285.06:01:44.84#ibcon#read 6, iclass 23, count 2 2006.285.06:01:44.84#ibcon#end of sib2, iclass 23, count 2 2006.285.06:01:44.84#ibcon#*mode == 0, iclass 23, count 2 2006.285.06:01:44.84#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.06:01:44.84#ibcon#[25=AT08-03\r\n] 2006.285.06:01:44.84#ibcon#*before write, iclass 23, count 2 2006.285.06:01:44.84#ibcon#enter sib2, iclass 23, count 2 2006.285.06:01:44.84#ibcon#flushed, iclass 23, count 2 2006.285.06:01:44.84#ibcon#about to write, iclass 23, count 2 2006.285.06:01:44.84#ibcon#wrote, iclass 23, count 2 2006.285.06:01:44.84#ibcon#about to read 3, iclass 23, count 2 2006.285.06:01:44.87#ibcon#read 3, iclass 23, count 2 2006.285.06:01:44.87#ibcon#about to read 4, iclass 23, count 2 2006.285.06:01:44.87#ibcon#read 4, iclass 23, count 2 2006.285.06:01:44.87#ibcon#about to read 5, iclass 23, count 2 2006.285.06:01:44.87#ibcon#read 5, iclass 23, count 2 2006.285.06:01:44.87#ibcon#about to read 6, iclass 23, count 2 2006.285.06:01:44.87#ibcon#read 6, iclass 23, count 2 2006.285.06:01:44.87#ibcon#end of sib2, iclass 23, count 2 2006.285.06:01:44.87#ibcon#*after write, iclass 23, count 2 2006.285.06:01:44.87#ibcon#*before return 0, iclass 23, count 2 2006.285.06:01:44.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:01:44.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:01:44.87#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.06:01:44.87#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:44.87#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:01:44.99#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:01:44.99#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:01:44.99#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:01:44.99#ibcon#first serial, iclass 23, count 0 2006.285.06:01:44.99#ibcon#enter sib2, iclass 23, count 0 2006.285.06:01:44.99#ibcon#flushed, iclass 23, count 0 2006.285.06:01:44.99#ibcon#about to write, iclass 23, count 0 2006.285.06:01:44.99#ibcon#wrote, iclass 23, count 0 2006.285.06:01:44.99#ibcon#about to read 3, iclass 23, count 0 2006.285.06:01:45.01#ibcon#read 3, iclass 23, count 0 2006.285.06:01:45.01#ibcon#about to read 4, iclass 23, count 0 2006.285.06:01:45.01#ibcon#read 4, iclass 23, count 0 2006.285.06:01:45.01#ibcon#about to read 5, iclass 23, count 0 2006.285.06:01:45.01#ibcon#read 5, iclass 23, count 0 2006.285.06:01:45.01#ibcon#about to read 6, iclass 23, count 0 2006.285.06:01:45.01#ibcon#read 6, iclass 23, count 0 2006.285.06:01:45.01#ibcon#end of sib2, iclass 23, count 0 2006.285.06:01:45.01#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:01:45.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:01:45.01#ibcon#[25=USB\r\n] 2006.285.06:01:45.01#ibcon#*before write, iclass 23, count 0 2006.285.06:01:45.01#ibcon#enter sib2, iclass 23, count 0 2006.285.06:01:45.01#ibcon#flushed, iclass 23, count 0 2006.285.06:01:45.01#ibcon#about to write, iclass 23, count 0 2006.285.06:01:45.01#ibcon#wrote, iclass 23, count 0 2006.285.06:01:45.01#ibcon#about to read 3, iclass 23, count 0 2006.285.06:01:45.04#ibcon#read 3, iclass 23, count 0 2006.285.06:01:45.04#ibcon#about to read 4, iclass 23, count 0 2006.285.06:01:45.04#ibcon#read 4, iclass 23, count 0 2006.285.06:01:45.04#ibcon#about to read 5, iclass 23, count 0 2006.285.06:01:45.04#ibcon#read 5, iclass 23, count 0 2006.285.06:01:45.04#ibcon#about to read 6, iclass 23, count 0 2006.285.06:01:45.04#ibcon#read 6, iclass 23, count 0 2006.285.06:01:45.04#ibcon#end of sib2, iclass 23, count 0 2006.285.06:01:45.04#ibcon#*after write, iclass 23, count 0 2006.285.06:01:45.04#ibcon#*before return 0, iclass 23, count 0 2006.285.06:01:45.04#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:01:45.04#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:01:45.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:01:45.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:01:45.04$vck44/vblo=1,629.99 2006.285.06:01:45.04#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.06:01:45.04#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.06:01:45.04#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:45.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:01:45.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:01:45.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:01:45.04#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:01:45.04#ibcon#first serial, iclass 25, count 0 2006.285.06:01:45.04#ibcon#enter sib2, iclass 25, count 0 2006.285.06:01:45.04#ibcon#flushed, iclass 25, count 0 2006.285.06:01:45.04#ibcon#about to write, iclass 25, count 0 2006.285.06:01:45.04#ibcon#wrote, iclass 25, count 0 2006.285.06:01:45.04#ibcon#about to read 3, iclass 25, count 0 2006.285.06:01:45.06#ibcon#read 3, iclass 25, count 0 2006.285.06:01:45.06#ibcon#about to read 4, iclass 25, count 0 2006.285.06:01:45.06#ibcon#read 4, iclass 25, count 0 2006.285.06:01:45.06#ibcon#about to read 5, iclass 25, count 0 2006.285.06:01:45.06#ibcon#read 5, iclass 25, count 0 2006.285.06:01:45.06#ibcon#about to read 6, iclass 25, count 0 2006.285.06:01:45.06#ibcon#read 6, iclass 25, count 0 2006.285.06:01:45.06#ibcon#end of sib2, iclass 25, count 0 2006.285.06:01:45.06#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:01:45.06#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:01:45.06#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:01:45.06#ibcon#*before write, iclass 25, count 0 2006.285.06:01:45.06#ibcon#enter sib2, iclass 25, count 0 2006.285.06:01:45.06#ibcon#flushed, iclass 25, count 0 2006.285.06:01:45.06#ibcon#about to write, iclass 25, count 0 2006.285.06:01:45.06#ibcon#wrote, iclass 25, count 0 2006.285.06:01:45.06#ibcon#about to read 3, iclass 25, count 0 2006.285.06:01:45.10#ibcon#read 3, iclass 25, count 0 2006.285.06:01:45.10#ibcon#about to read 4, iclass 25, count 0 2006.285.06:01:45.10#ibcon#read 4, iclass 25, count 0 2006.285.06:01:45.10#ibcon#about to read 5, iclass 25, count 0 2006.285.06:01:45.10#ibcon#read 5, iclass 25, count 0 2006.285.06:01:45.10#ibcon#about to read 6, iclass 25, count 0 2006.285.06:01:45.10#ibcon#read 6, iclass 25, count 0 2006.285.06:01:45.10#ibcon#end of sib2, iclass 25, count 0 2006.285.06:01:45.10#ibcon#*after write, iclass 25, count 0 2006.285.06:01:45.10#ibcon#*before return 0, iclass 25, count 0 2006.285.06:01:45.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:01:45.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:01:45.10#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:01:45.10#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:01:45.10$vck44/vb=1,4 2006.285.06:01:45.10#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.06:01:45.10#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.06:01:45.10#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:45.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:01:45.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:01:45.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:01:45.10#ibcon#enter wrdev, iclass 27, count 2 2006.285.06:01:45.10#ibcon#first serial, iclass 27, count 2 2006.285.06:01:45.10#ibcon#enter sib2, iclass 27, count 2 2006.285.06:01:45.10#ibcon#flushed, iclass 27, count 2 2006.285.06:01:45.10#ibcon#about to write, iclass 27, count 2 2006.285.06:01:45.10#ibcon#wrote, iclass 27, count 2 2006.285.06:01:45.10#ibcon#about to read 3, iclass 27, count 2 2006.285.06:01:45.12#ibcon#read 3, iclass 27, count 2 2006.285.06:01:45.12#ibcon#about to read 4, iclass 27, count 2 2006.285.06:01:45.12#ibcon#read 4, iclass 27, count 2 2006.285.06:01:45.12#ibcon#about to read 5, iclass 27, count 2 2006.285.06:01:45.12#ibcon#read 5, iclass 27, count 2 2006.285.06:01:45.12#ibcon#about to read 6, iclass 27, count 2 2006.285.06:01:45.12#ibcon#read 6, iclass 27, count 2 2006.285.06:01:45.12#ibcon#end of sib2, iclass 27, count 2 2006.285.06:01:45.12#ibcon#*mode == 0, iclass 27, count 2 2006.285.06:01:45.12#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.06:01:45.12#ibcon#[27=AT01-04\r\n] 2006.285.06:01:45.12#ibcon#*before write, iclass 27, count 2 2006.285.06:01:45.12#ibcon#enter sib2, iclass 27, count 2 2006.285.06:01:45.12#ibcon#flushed, iclass 27, count 2 2006.285.06:01:45.12#ibcon#about to write, iclass 27, count 2 2006.285.06:01:45.12#ibcon#wrote, iclass 27, count 2 2006.285.06:01:45.12#ibcon#about to read 3, iclass 27, count 2 2006.285.06:01:45.15#ibcon#read 3, iclass 27, count 2 2006.285.06:01:45.15#ibcon#about to read 4, iclass 27, count 2 2006.285.06:01:45.15#ibcon#read 4, iclass 27, count 2 2006.285.06:01:45.15#ibcon#about to read 5, iclass 27, count 2 2006.285.06:01:45.15#ibcon#read 5, iclass 27, count 2 2006.285.06:01:45.15#ibcon#about to read 6, iclass 27, count 2 2006.285.06:01:45.15#ibcon#read 6, iclass 27, count 2 2006.285.06:01:45.15#ibcon#end of sib2, iclass 27, count 2 2006.285.06:01:45.15#ibcon#*after write, iclass 27, count 2 2006.285.06:01:45.15#ibcon#*before return 0, iclass 27, count 2 2006.285.06:01:45.15#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:01:45.15#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:01:45.15#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.06:01:45.15#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:45.15#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:01:45.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:01:45.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:01:45.27#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:01:45.27#ibcon#first serial, iclass 27, count 0 2006.285.06:01:45.27#ibcon#enter sib2, iclass 27, count 0 2006.285.06:01:45.27#ibcon#flushed, iclass 27, count 0 2006.285.06:01:45.27#ibcon#about to write, iclass 27, count 0 2006.285.06:01:45.27#ibcon#wrote, iclass 27, count 0 2006.285.06:01:45.27#ibcon#about to read 3, iclass 27, count 0 2006.285.06:01:45.29#ibcon#read 3, iclass 27, count 0 2006.285.06:01:45.29#ibcon#about to read 4, iclass 27, count 0 2006.285.06:01:45.29#ibcon#read 4, iclass 27, count 0 2006.285.06:01:45.29#ibcon#about to read 5, iclass 27, count 0 2006.285.06:01:45.29#ibcon#read 5, iclass 27, count 0 2006.285.06:01:45.29#ibcon#about to read 6, iclass 27, count 0 2006.285.06:01:45.29#ibcon#read 6, iclass 27, count 0 2006.285.06:01:45.29#ibcon#end of sib2, iclass 27, count 0 2006.285.06:01:45.29#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:01:45.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:01:45.29#ibcon#[27=USB\r\n] 2006.285.06:01:45.29#ibcon#*before write, iclass 27, count 0 2006.285.06:01:45.29#ibcon#enter sib2, iclass 27, count 0 2006.285.06:01:45.29#ibcon#flushed, iclass 27, count 0 2006.285.06:01:45.29#ibcon#about to write, iclass 27, count 0 2006.285.06:01:45.29#ibcon#wrote, iclass 27, count 0 2006.285.06:01:45.29#ibcon#about to read 3, iclass 27, count 0 2006.285.06:01:45.32#ibcon#read 3, iclass 27, count 0 2006.285.06:01:45.32#ibcon#about to read 4, iclass 27, count 0 2006.285.06:01:45.32#ibcon#read 4, iclass 27, count 0 2006.285.06:01:45.32#ibcon#about to read 5, iclass 27, count 0 2006.285.06:01:45.32#ibcon#read 5, iclass 27, count 0 2006.285.06:01:45.32#ibcon#about to read 6, iclass 27, count 0 2006.285.06:01:45.32#ibcon#read 6, iclass 27, count 0 2006.285.06:01:45.32#ibcon#end of sib2, iclass 27, count 0 2006.285.06:01:45.32#ibcon#*after write, iclass 27, count 0 2006.285.06:01:45.32#ibcon#*before return 0, iclass 27, count 0 2006.285.06:01:45.32#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:01:45.32#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:01:45.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:01:45.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:01:45.32$vck44/vblo=2,634.99 2006.285.06:01:45.32#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.06:01:45.32#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.06:01:45.32#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:45.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:01:45.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:01:45.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:01:45.32#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:01:45.32#ibcon#first serial, iclass 29, count 0 2006.285.06:01:45.32#ibcon#enter sib2, iclass 29, count 0 2006.285.06:01:45.32#ibcon#flushed, iclass 29, count 0 2006.285.06:01:45.32#ibcon#about to write, iclass 29, count 0 2006.285.06:01:45.32#ibcon#wrote, iclass 29, count 0 2006.285.06:01:45.32#ibcon#about to read 3, iclass 29, count 0 2006.285.06:01:45.34#ibcon#read 3, iclass 29, count 0 2006.285.06:01:45.34#ibcon#about to read 4, iclass 29, count 0 2006.285.06:01:45.34#ibcon#read 4, iclass 29, count 0 2006.285.06:01:45.34#ibcon#about to read 5, iclass 29, count 0 2006.285.06:01:45.34#ibcon#read 5, iclass 29, count 0 2006.285.06:01:45.34#ibcon#about to read 6, iclass 29, count 0 2006.285.06:01:45.34#ibcon#read 6, iclass 29, count 0 2006.285.06:01:45.34#ibcon#end of sib2, iclass 29, count 0 2006.285.06:01:45.34#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:01:45.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:01:45.34#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:01:45.34#ibcon#*before write, iclass 29, count 0 2006.285.06:01:45.34#ibcon#enter sib2, iclass 29, count 0 2006.285.06:01:45.34#ibcon#flushed, iclass 29, count 0 2006.285.06:01:45.34#ibcon#about to write, iclass 29, count 0 2006.285.06:01:45.34#ibcon#wrote, iclass 29, count 0 2006.285.06:01:45.34#ibcon#about to read 3, iclass 29, count 0 2006.285.06:01:45.38#ibcon#read 3, iclass 29, count 0 2006.285.06:01:45.38#ibcon#about to read 4, iclass 29, count 0 2006.285.06:01:45.38#ibcon#read 4, iclass 29, count 0 2006.285.06:01:45.38#ibcon#about to read 5, iclass 29, count 0 2006.285.06:01:45.38#ibcon#read 5, iclass 29, count 0 2006.285.06:01:45.38#ibcon#about to read 6, iclass 29, count 0 2006.285.06:01:45.38#ibcon#read 6, iclass 29, count 0 2006.285.06:01:45.38#ibcon#end of sib2, iclass 29, count 0 2006.285.06:01:45.38#ibcon#*after write, iclass 29, count 0 2006.285.06:01:45.38#ibcon#*before return 0, iclass 29, count 0 2006.285.06:01:45.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:01:45.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:01:45.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:01:45.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:01:45.38$vck44/vb=2,5 2006.285.06:01:45.38#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.06:01:45.38#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.06:01:45.38#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:45.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:01:45.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:01:45.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:01:45.44#ibcon#enter wrdev, iclass 31, count 2 2006.285.06:01:45.44#ibcon#first serial, iclass 31, count 2 2006.285.06:01:45.44#ibcon#enter sib2, iclass 31, count 2 2006.285.06:01:45.44#ibcon#flushed, iclass 31, count 2 2006.285.06:01:45.44#ibcon#about to write, iclass 31, count 2 2006.285.06:01:45.44#ibcon#wrote, iclass 31, count 2 2006.285.06:01:45.44#ibcon#about to read 3, iclass 31, count 2 2006.285.06:01:45.46#ibcon#read 3, iclass 31, count 2 2006.285.06:01:45.46#ibcon#about to read 4, iclass 31, count 2 2006.285.06:01:45.46#ibcon#read 4, iclass 31, count 2 2006.285.06:01:45.46#ibcon#about to read 5, iclass 31, count 2 2006.285.06:01:45.46#ibcon#read 5, iclass 31, count 2 2006.285.06:01:45.46#ibcon#about to read 6, iclass 31, count 2 2006.285.06:01:45.46#ibcon#read 6, iclass 31, count 2 2006.285.06:01:45.46#ibcon#end of sib2, iclass 31, count 2 2006.285.06:01:45.46#ibcon#*mode == 0, iclass 31, count 2 2006.285.06:01:45.46#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.06:01:45.46#ibcon#[27=AT02-05\r\n] 2006.285.06:01:45.46#ibcon#*before write, iclass 31, count 2 2006.285.06:01:45.46#ibcon#enter sib2, iclass 31, count 2 2006.285.06:01:45.46#ibcon#flushed, iclass 31, count 2 2006.285.06:01:45.46#ibcon#about to write, iclass 31, count 2 2006.285.06:01:45.46#ibcon#wrote, iclass 31, count 2 2006.285.06:01:45.46#ibcon#about to read 3, iclass 31, count 2 2006.285.06:01:45.49#ibcon#read 3, iclass 31, count 2 2006.285.06:01:45.49#ibcon#about to read 4, iclass 31, count 2 2006.285.06:01:45.49#ibcon#read 4, iclass 31, count 2 2006.285.06:01:45.49#ibcon#about to read 5, iclass 31, count 2 2006.285.06:01:45.49#ibcon#read 5, iclass 31, count 2 2006.285.06:01:45.49#ibcon#about to read 6, iclass 31, count 2 2006.285.06:01:45.49#ibcon#read 6, iclass 31, count 2 2006.285.06:01:45.49#ibcon#end of sib2, iclass 31, count 2 2006.285.06:01:45.49#ibcon#*after write, iclass 31, count 2 2006.285.06:01:45.49#ibcon#*before return 0, iclass 31, count 2 2006.285.06:01:45.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:01:45.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:01:45.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.06:01:45.49#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:45.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:01:45.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:01:45.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:01:45.61#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:01:45.61#ibcon#first serial, iclass 31, count 0 2006.285.06:01:45.61#ibcon#enter sib2, iclass 31, count 0 2006.285.06:01:45.61#ibcon#flushed, iclass 31, count 0 2006.285.06:01:45.61#ibcon#about to write, iclass 31, count 0 2006.285.06:01:45.61#ibcon#wrote, iclass 31, count 0 2006.285.06:01:45.61#ibcon#about to read 3, iclass 31, count 0 2006.285.06:01:45.63#ibcon#read 3, iclass 31, count 0 2006.285.06:01:45.63#ibcon#about to read 4, iclass 31, count 0 2006.285.06:01:45.63#ibcon#read 4, iclass 31, count 0 2006.285.06:01:45.63#ibcon#about to read 5, iclass 31, count 0 2006.285.06:01:45.63#ibcon#read 5, iclass 31, count 0 2006.285.06:01:45.63#ibcon#about to read 6, iclass 31, count 0 2006.285.06:01:45.63#ibcon#read 6, iclass 31, count 0 2006.285.06:01:45.63#ibcon#end of sib2, iclass 31, count 0 2006.285.06:01:45.63#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:01:45.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:01:45.63#ibcon#[27=USB\r\n] 2006.285.06:01:45.63#ibcon#*before write, iclass 31, count 0 2006.285.06:01:45.63#ibcon#enter sib2, iclass 31, count 0 2006.285.06:01:45.63#ibcon#flushed, iclass 31, count 0 2006.285.06:01:45.63#ibcon#about to write, iclass 31, count 0 2006.285.06:01:45.63#ibcon#wrote, iclass 31, count 0 2006.285.06:01:45.63#ibcon#about to read 3, iclass 31, count 0 2006.285.06:01:45.66#ibcon#read 3, iclass 31, count 0 2006.285.06:01:45.66#ibcon#about to read 4, iclass 31, count 0 2006.285.06:01:45.66#ibcon#read 4, iclass 31, count 0 2006.285.06:01:45.66#ibcon#about to read 5, iclass 31, count 0 2006.285.06:01:45.66#ibcon#read 5, iclass 31, count 0 2006.285.06:01:45.66#ibcon#about to read 6, iclass 31, count 0 2006.285.06:01:45.66#ibcon#read 6, iclass 31, count 0 2006.285.06:01:45.66#ibcon#end of sib2, iclass 31, count 0 2006.285.06:01:45.66#ibcon#*after write, iclass 31, count 0 2006.285.06:01:45.66#ibcon#*before return 0, iclass 31, count 0 2006.285.06:01:45.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:01:45.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:01:45.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:01:45.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:01:45.66$vck44/vblo=3,649.99 2006.285.06:01:45.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.06:01:45.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.06:01:45.66#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:45.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:01:45.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:01:45.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:01:45.66#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:01:45.66#ibcon#first serial, iclass 33, count 0 2006.285.06:01:45.66#ibcon#enter sib2, iclass 33, count 0 2006.285.06:01:45.66#ibcon#flushed, iclass 33, count 0 2006.285.06:01:45.66#ibcon#about to write, iclass 33, count 0 2006.285.06:01:45.66#ibcon#wrote, iclass 33, count 0 2006.285.06:01:45.66#ibcon#about to read 3, iclass 33, count 0 2006.285.06:01:45.68#ibcon#read 3, iclass 33, count 0 2006.285.06:01:45.68#ibcon#about to read 4, iclass 33, count 0 2006.285.06:01:45.68#ibcon#read 4, iclass 33, count 0 2006.285.06:01:45.68#ibcon#about to read 5, iclass 33, count 0 2006.285.06:01:45.68#ibcon#read 5, iclass 33, count 0 2006.285.06:01:45.68#ibcon#about to read 6, iclass 33, count 0 2006.285.06:01:45.68#ibcon#read 6, iclass 33, count 0 2006.285.06:01:45.68#ibcon#end of sib2, iclass 33, count 0 2006.285.06:01:45.68#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:01:45.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:01:45.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:01:45.68#ibcon#*before write, iclass 33, count 0 2006.285.06:01:45.68#ibcon#enter sib2, iclass 33, count 0 2006.285.06:01:45.68#ibcon#flushed, iclass 33, count 0 2006.285.06:01:45.68#ibcon#about to write, iclass 33, count 0 2006.285.06:01:45.68#ibcon#wrote, iclass 33, count 0 2006.285.06:01:45.68#ibcon#about to read 3, iclass 33, count 0 2006.285.06:01:45.72#ibcon#read 3, iclass 33, count 0 2006.285.06:01:45.72#ibcon#about to read 4, iclass 33, count 0 2006.285.06:01:45.72#ibcon#read 4, iclass 33, count 0 2006.285.06:01:45.72#ibcon#about to read 5, iclass 33, count 0 2006.285.06:01:45.72#ibcon#read 5, iclass 33, count 0 2006.285.06:01:45.72#ibcon#about to read 6, iclass 33, count 0 2006.285.06:01:45.72#ibcon#read 6, iclass 33, count 0 2006.285.06:01:45.72#ibcon#end of sib2, iclass 33, count 0 2006.285.06:01:45.72#ibcon#*after write, iclass 33, count 0 2006.285.06:01:45.72#ibcon#*before return 0, iclass 33, count 0 2006.285.06:01:45.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:01:45.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:01:45.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:01:45.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:01:45.72$vck44/vb=3,4 2006.285.06:01:45.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.06:01:45.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.06:01:45.72#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:45.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:01:45.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:01:45.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:01:45.78#ibcon#enter wrdev, iclass 35, count 2 2006.285.06:01:45.78#ibcon#first serial, iclass 35, count 2 2006.285.06:01:45.78#ibcon#enter sib2, iclass 35, count 2 2006.285.06:01:45.78#ibcon#flushed, iclass 35, count 2 2006.285.06:01:45.78#ibcon#about to write, iclass 35, count 2 2006.285.06:01:45.78#ibcon#wrote, iclass 35, count 2 2006.285.06:01:45.78#ibcon#about to read 3, iclass 35, count 2 2006.285.06:01:45.80#ibcon#read 3, iclass 35, count 2 2006.285.06:01:45.80#ibcon#about to read 4, iclass 35, count 2 2006.285.06:01:45.80#ibcon#read 4, iclass 35, count 2 2006.285.06:01:45.80#ibcon#about to read 5, iclass 35, count 2 2006.285.06:01:45.80#ibcon#read 5, iclass 35, count 2 2006.285.06:01:45.80#ibcon#about to read 6, iclass 35, count 2 2006.285.06:01:45.80#ibcon#read 6, iclass 35, count 2 2006.285.06:01:45.80#ibcon#end of sib2, iclass 35, count 2 2006.285.06:01:45.80#ibcon#*mode == 0, iclass 35, count 2 2006.285.06:01:45.80#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.06:01:45.80#ibcon#[27=AT03-04\r\n] 2006.285.06:01:45.80#ibcon#*before write, iclass 35, count 2 2006.285.06:01:45.80#ibcon#enter sib2, iclass 35, count 2 2006.285.06:01:45.80#ibcon#flushed, iclass 35, count 2 2006.285.06:01:45.80#ibcon#about to write, iclass 35, count 2 2006.285.06:01:45.80#ibcon#wrote, iclass 35, count 2 2006.285.06:01:45.80#ibcon#about to read 3, iclass 35, count 2 2006.285.06:01:45.83#ibcon#read 3, iclass 35, count 2 2006.285.06:01:45.83#ibcon#about to read 4, iclass 35, count 2 2006.285.06:01:45.83#ibcon#read 4, iclass 35, count 2 2006.285.06:01:45.83#ibcon#about to read 5, iclass 35, count 2 2006.285.06:01:45.83#ibcon#read 5, iclass 35, count 2 2006.285.06:01:45.83#ibcon#about to read 6, iclass 35, count 2 2006.285.06:01:45.83#ibcon#read 6, iclass 35, count 2 2006.285.06:01:45.83#ibcon#end of sib2, iclass 35, count 2 2006.285.06:01:45.83#ibcon#*after write, iclass 35, count 2 2006.285.06:01:45.83#ibcon#*before return 0, iclass 35, count 2 2006.285.06:01:45.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:01:45.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:01:45.83#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.06:01:45.83#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:45.83#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:01:45.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:01:45.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:01:45.95#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:01:45.95#ibcon#first serial, iclass 35, count 0 2006.285.06:01:45.95#ibcon#enter sib2, iclass 35, count 0 2006.285.06:01:45.95#ibcon#flushed, iclass 35, count 0 2006.285.06:01:45.95#ibcon#about to write, iclass 35, count 0 2006.285.06:01:45.95#ibcon#wrote, iclass 35, count 0 2006.285.06:01:45.95#ibcon#about to read 3, iclass 35, count 0 2006.285.06:01:45.97#ibcon#read 3, iclass 35, count 0 2006.285.06:01:45.97#ibcon#about to read 4, iclass 35, count 0 2006.285.06:01:45.97#ibcon#read 4, iclass 35, count 0 2006.285.06:01:45.97#ibcon#about to read 5, iclass 35, count 0 2006.285.06:01:45.97#ibcon#read 5, iclass 35, count 0 2006.285.06:01:45.97#ibcon#about to read 6, iclass 35, count 0 2006.285.06:01:45.97#ibcon#read 6, iclass 35, count 0 2006.285.06:01:45.97#ibcon#end of sib2, iclass 35, count 0 2006.285.06:01:45.97#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:01:45.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:01:45.97#ibcon#[27=USB\r\n] 2006.285.06:01:45.97#ibcon#*before write, iclass 35, count 0 2006.285.06:01:45.97#ibcon#enter sib2, iclass 35, count 0 2006.285.06:01:45.97#ibcon#flushed, iclass 35, count 0 2006.285.06:01:45.97#ibcon#about to write, iclass 35, count 0 2006.285.06:01:45.97#ibcon#wrote, iclass 35, count 0 2006.285.06:01:45.97#ibcon#about to read 3, iclass 35, count 0 2006.285.06:01:46.00#ibcon#read 3, iclass 35, count 0 2006.285.06:01:46.00#ibcon#about to read 4, iclass 35, count 0 2006.285.06:01:46.00#ibcon#read 4, iclass 35, count 0 2006.285.06:01:46.00#ibcon#about to read 5, iclass 35, count 0 2006.285.06:01:46.00#ibcon#read 5, iclass 35, count 0 2006.285.06:01:46.00#ibcon#about to read 6, iclass 35, count 0 2006.285.06:01:46.00#ibcon#read 6, iclass 35, count 0 2006.285.06:01:46.00#ibcon#end of sib2, iclass 35, count 0 2006.285.06:01:46.00#ibcon#*after write, iclass 35, count 0 2006.285.06:01:46.00#ibcon#*before return 0, iclass 35, count 0 2006.285.06:01:46.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:01:46.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:01:46.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:01:46.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:01:46.00$vck44/vblo=4,679.99 2006.285.06:01:46.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.06:01:46.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.06:01:46.00#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:46.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:01:46.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:01:46.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:01:46.00#ibcon#enter wrdev, iclass 37, count 0 2006.285.06:01:46.00#ibcon#first serial, iclass 37, count 0 2006.285.06:01:46.00#ibcon#enter sib2, iclass 37, count 0 2006.285.06:01:46.00#ibcon#flushed, iclass 37, count 0 2006.285.06:01:46.00#ibcon#about to write, iclass 37, count 0 2006.285.06:01:46.00#ibcon#wrote, iclass 37, count 0 2006.285.06:01:46.00#ibcon#about to read 3, iclass 37, count 0 2006.285.06:01:46.02#ibcon#read 3, iclass 37, count 0 2006.285.06:01:46.02#ibcon#about to read 4, iclass 37, count 0 2006.285.06:01:46.02#ibcon#read 4, iclass 37, count 0 2006.285.06:01:46.02#ibcon#about to read 5, iclass 37, count 0 2006.285.06:01:46.02#ibcon#read 5, iclass 37, count 0 2006.285.06:01:46.02#ibcon#about to read 6, iclass 37, count 0 2006.285.06:01:46.02#ibcon#read 6, iclass 37, count 0 2006.285.06:01:46.02#ibcon#end of sib2, iclass 37, count 0 2006.285.06:01:46.02#ibcon#*mode == 0, iclass 37, count 0 2006.285.06:01:46.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.06:01:46.02#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:01:46.02#ibcon#*before write, iclass 37, count 0 2006.285.06:01:46.02#ibcon#enter sib2, iclass 37, count 0 2006.285.06:01:46.02#ibcon#flushed, iclass 37, count 0 2006.285.06:01:46.02#ibcon#about to write, iclass 37, count 0 2006.285.06:01:46.02#ibcon#wrote, iclass 37, count 0 2006.285.06:01:46.02#ibcon#about to read 3, iclass 37, count 0 2006.285.06:01:46.06#ibcon#read 3, iclass 37, count 0 2006.285.06:01:46.06#ibcon#about to read 4, iclass 37, count 0 2006.285.06:01:46.06#ibcon#read 4, iclass 37, count 0 2006.285.06:01:46.06#ibcon#about to read 5, iclass 37, count 0 2006.285.06:01:46.06#ibcon#read 5, iclass 37, count 0 2006.285.06:01:46.06#ibcon#about to read 6, iclass 37, count 0 2006.285.06:01:46.06#ibcon#read 6, iclass 37, count 0 2006.285.06:01:46.06#ibcon#end of sib2, iclass 37, count 0 2006.285.06:01:46.06#ibcon#*after write, iclass 37, count 0 2006.285.06:01:46.06#ibcon#*before return 0, iclass 37, count 0 2006.285.06:01:46.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:01:46.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:01:46.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.06:01:46.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.06:01:46.06$vck44/vb=4,5 2006.285.06:01:46.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.06:01:46.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.06:01:46.06#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:46.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:01:46.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:01:46.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:01:46.12#ibcon#enter wrdev, iclass 39, count 2 2006.285.06:01:46.12#ibcon#first serial, iclass 39, count 2 2006.285.06:01:46.12#ibcon#enter sib2, iclass 39, count 2 2006.285.06:01:46.12#ibcon#flushed, iclass 39, count 2 2006.285.06:01:46.12#ibcon#about to write, iclass 39, count 2 2006.285.06:01:46.12#ibcon#wrote, iclass 39, count 2 2006.285.06:01:46.12#ibcon#about to read 3, iclass 39, count 2 2006.285.06:01:46.14#ibcon#read 3, iclass 39, count 2 2006.285.06:01:46.14#ibcon#about to read 4, iclass 39, count 2 2006.285.06:01:46.14#ibcon#read 4, iclass 39, count 2 2006.285.06:01:46.14#ibcon#about to read 5, iclass 39, count 2 2006.285.06:01:46.14#ibcon#read 5, iclass 39, count 2 2006.285.06:01:46.14#ibcon#about to read 6, iclass 39, count 2 2006.285.06:01:46.14#ibcon#read 6, iclass 39, count 2 2006.285.06:01:46.14#ibcon#end of sib2, iclass 39, count 2 2006.285.06:01:46.14#ibcon#*mode == 0, iclass 39, count 2 2006.285.06:01:46.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.06:01:46.14#ibcon#[27=AT04-05\r\n] 2006.285.06:01:46.14#ibcon#*before write, iclass 39, count 2 2006.285.06:01:46.14#ibcon#enter sib2, iclass 39, count 2 2006.285.06:01:46.14#ibcon#flushed, iclass 39, count 2 2006.285.06:01:46.14#ibcon#about to write, iclass 39, count 2 2006.285.06:01:46.14#ibcon#wrote, iclass 39, count 2 2006.285.06:01:46.14#ibcon#about to read 3, iclass 39, count 2 2006.285.06:01:46.17#ibcon#read 3, iclass 39, count 2 2006.285.06:01:46.17#ibcon#about to read 4, iclass 39, count 2 2006.285.06:01:46.17#ibcon#read 4, iclass 39, count 2 2006.285.06:01:46.17#ibcon#about to read 5, iclass 39, count 2 2006.285.06:01:46.17#ibcon#read 5, iclass 39, count 2 2006.285.06:01:46.17#ibcon#about to read 6, iclass 39, count 2 2006.285.06:01:46.17#ibcon#read 6, iclass 39, count 2 2006.285.06:01:46.17#ibcon#end of sib2, iclass 39, count 2 2006.285.06:01:46.17#ibcon#*after write, iclass 39, count 2 2006.285.06:01:46.17#ibcon#*before return 0, iclass 39, count 2 2006.285.06:01:46.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:01:46.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:01:46.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.06:01:46.17#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:46.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:01:46.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:01:46.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:01:46.29#ibcon#enter wrdev, iclass 39, count 0 2006.285.06:01:46.29#ibcon#first serial, iclass 39, count 0 2006.285.06:01:46.29#ibcon#enter sib2, iclass 39, count 0 2006.285.06:01:46.29#ibcon#flushed, iclass 39, count 0 2006.285.06:01:46.29#ibcon#about to write, iclass 39, count 0 2006.285.06:01:46.29#ibcon#wrote, iclass 39, count 0 2006.285.06:01:46.29#ibcon#about to read 3, iclass 39, count 0 2006.285.06:01:46.31#ibcon#read 3, iclass 39, count 0 2006.285.06:01:46.31#ibcon#about to read 4, iclass 39, count 0 2006.285.06:01:46.31#ibcon#read 4, iclass 39, count 0 2006.285.06:01:46.31#ibcon#about to read 5, iclass 39, count 0 2006.285.06:01:46.31#ibcon#read 5, iclass 39, count 0 2006.285.06:01:46.31#ibcon#about to read 6, iclass 39, count 0 2006.285.06:01:46.31#ibcon#read 6, iclass 39, count 0 2006.285.06:01:46.31#ibcon#end of sib2, iclass 39, count 0 2006.285.06:01:46.31#ibcon#*mode == 0, iclass 39, count 0 2006.285.06:01:46.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.06:01:46.31#ibcon#[27=USB\r\n] 2006.285.06:01:46.31#ibcon#*before write, iclass 39, count 0 2006.285.06:01:46.31#ibcon#enter sib2, iclass 39, count 0 2006.285.06:01:46.31#ibcon#flushed, iclass 39, count 0 2006.285.06:01:46.31#ibcon#about to write, iclass 39, count 0 2006.285.06:01:46.31#ibcon#wrote, iclass 39, count 0 2006.285.06:01:46.31#ibcon#about to read 3, iclass 39, count 0 2006.285.06:01:46.34#ibcon#read 3, iclass 39, count 0 2006.285.06:01:46.34#ibcon#about to read 4, iclass 39, count 0 2006.285.06:01:46.34#ibcon#read 4, iclass 39, count 0 2006.285.06:01:46.34#ibcon#about to read 5, iclass 39, count 0 2006.285.06:01:46.34#ibcon#read 5, iclass 39, count 0 2006.285.06:01:46.34#ibcon#about to read 6, iclass 39, count 0 2006.285.06:01:46.34#ibcon#read 6, iclass 39, count 0 2006.285.06:01:46.34#ibcon#end of sib2, iclass 39, count 0 2006.285.06:01:46.34#ibcon#*after write, iclass 39, count 0 2006.285.06:01:46.34#ibcon#*before return 0, iclass 39, count 0 2006.285.06:01:46.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:01:46.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:01:46.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.06:01:46.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.06:01:46.34$vck44/vblo=5,709.99 2006.285.06:01:46.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.06:01:46.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.06:01:46.34#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:46.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:01:46.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:01:46.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:01:46.34#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:01:46.34#ibcon#first serial, iclass 3, count 0 2006.285.06:01:46.34#ibcon#enter sib2, iclass 3, count 0 2006.285.06:01:46.34#ibcon#flushed, iclass 3, count 0 2006.285.06:01:46.34#ibcon#about to write, iclass 3, count 0 2006.285.06:01:46.34#ibcon#wrote, iclass 3, count 0 2006.285.06:01:46.34#ibcon#about to read 3, iclass 3, count 0 2006.285.06:01:46.36#ibcon#read 3, iclass 3, count 0 2006.285.06:01:46.36#ibcon#about to read 4, iclass 3, count 0 2006.285.06:01:46.36#ibcon#read 4, iclass 3, count 0 2006.285.06:01:46.36#ibcon#about to read 5, iclass 3, count 0 2006.285.06:01:46.36#ibcon#read 5, iclass 3, count 0 2006.285.06:01:46.36#ibcon#about to read 6, iclass 3, count 0 2006.285.06:01:46.36#ibcon#read 6, iclass 3, count 0 2006.285.06:01:46.36#ibcon#end of sib2, iclass 3, count 0 2006.285.06:01:46.36#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:01:46.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:01:46.36#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:01:46.36#ibcon#*before write, iclass 3, count 0 2006.285.06:01:46.36#ibcon#enter sib2, iclass 3, count 0 2006.285.06:01:46.36#ibcon#flushed, iclass 3, count 0 2006.285.06:01:46.36#ibcon#about to write, iclass 3, count 0 2006.285.06:01:46.36#ibcon#wrote, iclass 3, count 0 2006.285.06:01:46.36#ibcon#about to read 3, iclass 3, count 0 2006.285.06:01:46.40#ibcon#read 3, iclass 3, count 0 2006.285.06:01:46.40#ibcon#about to read 4, iclass 3, count 0 2006.285.06:01:46.40#ibcon#read 4, iclass 3, count 0 2006.285.06:01:46.40#ibcon#about to read 5, iclass 3, count 0 2006.285.06:01:46.40#ibcon#read 5, iclass 3, count 0 2006.285.06:01:46.40#ibcon#about to read 6, iclass 3, count 0 2006.285.06:01:46.40#ibcon#read 6, iclass 3, count 0 2006.285.06:01:46.40#ibcon#end of sib2, iclass 3, count 0 2006.285.06:01:46.40#ibcon#*after write, iclass 3, count 0 2006.285.06:01:46.40#ibcon#*before return 0, iclass 3, count 0 2006.285.06:01:46.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:01:46.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:01:46.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:01:46.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:01:46.40$vck44/vb=5,4 2006.285.06:01:46.40#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.06:01:46.40#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.06:01:46.40#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:46.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:01:46.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:01:46.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:01:46.46#ibcon#enter wrdev, iclass 5, count 2 2006.285.06:01:46.46#ibcon#first serial, iclass 5, count 2 2006.285.06:01:46.46#ibcon#enter sib2, iclass 5, count 2 2006.285.06:01:46.46#ibcon#flushed, iclass 5, count 2 2006.285.06:01:46.46#ibcon#about to write, iclass 5, count 2 2006.285.06:01:46.46#ibcon#wrote, iclass 5, count 2 2006.285.06:01:46.46#ibcon#about to read 3, iclass 5, count 2 2006.285.06:01:46.48#ibcon#read 3, iclass 5, count 2 2006.285.06:01:46.48#ibcon#about to read 4, iclass 5, count 2 2006.285.06:01:46.48#ibcon#read 4, iclass 5, count 2 2006.285.06:01:46.48#ibcon#about to read 5, iclass 5, count 2 2006.285.06:01:46.48#ibcon#read 5, iclass 5, count 2 2006.285.06:01:46.48#ibcon#about to read 6, iclass 5, count 2 2006.285.06:01:46.48#ibcon#read 6, iclass 5, count 2 2006.285.06:01:46.48#ibcon#end of sib2, iclass 5, count 2 2006.285.06:01:46.48#ibcon#*mode == 0, iclass 5, count 2 2006.285.06:01:46.48#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.06:01:46.48#ibcon#[27=AT05-04\r\n] 2006.285.06:01:46.48#ibcon#*before write, iclass 5, count 2 2006.285.06:01:46.48#ibcon#enter sib2, iclass 5, count 2 2006.285.06:01:46.48#ibcon#flushed, iclass 5, count 2 2006.285.06:01:46.48#ibcon#about to write, iclass 5, count 2 2006.285.06:01:46.48#ibcon#wrote, iclass 5, count 2 2006.285.06:01:46.48#ibcon#about to read 3, iclass 5, count 2 2006.285.06:01:46.51#ibcon#read 3, iclass 5, count 2 2006.285.06:01:46.51#ibcon#about to read 4, iclass 5, count 2 2006.285.06:01:46.51#ibcon#read 4, iclass 5, count 2 2006.285.06:01:46.51#ibcon#about to read 5, iclass 5, count 2 2006.285.06:01:46.51#ibcon#read 5, iclass 5, count 2 2006.285.06:01:46.51#ibcon#about to read 6, iclass 5, count 2 2006.285.06:01:46.51#ibcon#read 6, iclass 5, count 2 2006.285.06:01:46.51#ibcon#end of sib2, iclass 5, count 2 2006.285.06:01:46.51#ibcon#*after write, iclass 5, count 2 2006.285.06:01:46.51#ibcon#*before return 0, iclass 5, count 2 2006.285.06:01:46.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:01:46.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:01:46.51#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.06:01:46.51#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:46.51#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:01:46.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:01:46.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:01:46.63#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:01:46.63#ibcon#first serial, iclass 5, count 0 2006.285.06:01:46.63#ibcon#enter sib2, iclass 5, count 0 2006.285.06:01:46.63#ibcon#flushed, iclass 5, count 0 2006.285.06:01:46.63#ibcon#about to write, iclass 5, count 0 2006.285.06:01:46.63#ibcon#wrote, iclass 5, count 0 2006.285.06:01:46.63#ibcon#about to read 3, iclass 5, count 0 2006.285.06:01:46.65#ibcon#read 3, iclass 5, count 0 2006.285.06:01:46.65#ibcon#about to read 4, iclass 5, count 0 2006.285.06:01:46.65#ibcon#read 4, iclass 5, count 0 2006.285.06:01:46.65#ibcon#about to read 5, iclass 5, count 0 2006.285.06:01:46.65#ibcon#read 5, iclass 5, count 0 2006.285.06:01:46.65#ibcon#about to read 6, iclass 5, count 0 2006.285.06:01:46.65#ibcon#read 6, iclass 5, count 0 2006.285.06:01:46.65#ibcon#end of sib2, iclass 5, count 0 2006.285.06:01:46.65#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:01:46.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:01:46.65#ibcon#[27=USB\r\n] 2006.285.06:01:46.65#ibcon#*before write, iclass 5, count 0 2006.285.06:01:46.65#ibcon#enter sib2, iclass 5, count 0 2006.285.06:01:46.65#ibcon#flushed, iclass 5, count 0 2006.285.06:01:46.65#ibcon#about to write, iclass 5, count 0 2006.285.06:01:46.65#ibcon#wrote, iclass 5, count 0 2006.285.06:01:46.65#ibcon#about to read 3, iclass 5, count 0 2006.285.06:01:46.68#ibcon#read 3, iclass 5, count 0 2006.285.06:01:46.68#ibcon#about to read 4, iclass 5, count 0 2006.285.06:01:46.68#ibcon#read 4, iclass 5, count 0 2006.285.06:01:46.68#ibcon#about to read 5, iclass 5, count 0 2006.285.06:01:46.68#ibcon#read 5, iclass 5, count 0 2006.285.06:01:46.68#ibcon#about to read 6, iclass 5, count 0 2006.285.06:01:46.68#ibcon#read 6, iclass 5, count 0 2006.285.06:01:46.68#ibcon#end of sib2, iclass 5, count 0 2006.285.06:01:46.68#ibcon#*after write, iclass 5, count 0 2006.285.06:01:46.68#ibcon#*before return 0, iclass 5, count 0 2006.285.06:01:46.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:01:46.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:01:46.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:01:46.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:01:46.68$vck44/vblo=6,719.99 2006.285.06:01:46.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.06:01:46.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.06:01:46.68#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:46.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:01:46.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:01:46.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:01:46.68#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:01:46.68#ibcon#first serial, iclass 7, count 0 2006.285.06:01:46.68#ibcon#enter sib2, iclass 7, count 0 2006.285.06:01:46.68#ibcon#flushed, iclass 7, count 0 2006.285.06:01:46.68#ibcon#about to write, iclass 7, count 0 2006.285.06:01:46.68#ibcon#wrote, iclass 7, count 0 2006.285.06:01:46.68#ibcon#about to read 3, iclass 7, count 0 2006.285.06:01:46.70#ibcon#read 3, iclass 7, count 0 2006.285.06:01:46.70#ibcon#about to read 4, iclass 7, count 0 2006.285.06:01:46.70#ibcon#read 4, iclass 7, count 0 2006.285.06:01:46.70#ibcon#about to read 5, iclass 7, count 0 2006.285.06:01:46.70#ibcon#read 5, iclass 7, count 0 2006.285.06:01:46.70#ibcon#about to read 6, iclass 7, count 0 2006.285.06:01:46.70#ibcon#read 6, iclass 7, count 0 2006.285.06:01:46.70#ibcon#end of sib2, iclass 7, count 0 2006.285.06:01:46.70#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:01:46.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:01:46.70#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:01:46.70#ibcon#*before write, iclass 7, count 0 2006.285.06:01:46.70#ibcon#enter sib2, iclass 7, count 0 2006.285.06:01:46.70#ibcon#flushed, iclass 7, count 0 2006.285.06:01:46.70#ibcon#about to write, iclass 7, count 0 2006.285.06:01:46.70#ibcon#wrote, iclass 7, count 0 2006.285.06:01:46.70#ibcon#about to read 3, iclass 7, count 0 2006.285.06:01:46.74#ibcon#read 3, iclass 7, count 0 2006.285.06:01:46.74#ibcon#about to read 4, iclass 7, count 0 2006.285.06:01:46.74#ibcon#read 4, iclass 7, count 0 2006.285.06:01:46.74#ibcon#about to read 5, iclass 7, count 0 2006.285.06:01:46.74#ibcon#read 5, iclass 7, count 0 2006.285.06:01:46.74#ibcon#about to read 6, iclass 7, count 0 2006.285.06:01:46.74#ibcon#read 6, iclass 7, count 0 2006.285.06:01:46.74#ibcon#end of sib2, iclass 7, count 0 2006.285.06:01:46.74#ibcon#*after write, iclass 7, count 0 2006.285.06:01:46.74#ibcon#*before return 0, iclass 7, count 0 2006.285.06:01:46.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:01:46.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:01:46.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:01:46.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:01:46.74$vck44/vb=6,3 2006.285.06:01:46.74#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.06:01:46.74#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.06:01:46.74#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:46.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:01:46.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:01:46.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:01:46.80#ibcon#enter wrdev, iclass 11, count 2 2006.285.06:01:46.80#ibcon#first serial, iclass 11, count 2 2006.285.06:01:46.80#ibcon#enter sib2, iclass 11, count 2 2006.285.06:01:46.80#ibcon#flushed, iclass 11, count 2 2006.285.06:01:46.80#ibcon#about to write, iclass 11, count 2 2006.285.06:01:46.80#ibcon#wrote, iclass 11, count 2 2006.285.06:01:46.80#ibcon#about to read 3, iclass 11, count 2 2006.285.06:01:46.82#ibcon#read 3, iclass 11, count 2 2006.285.06:01:46.82#ibcon#about to read 4, iclass 11, count 2 2006.285.06:01:46.82#ibcon#read 4, iclass 11, count 2 2006.285.06:01:46.82#ibcon#about to read 5, iclass 11, count 2 2006.285.06:01:46.82#ibcon#read 5, iclass 11, count 2 2006.285.06:01:46.82#ibcon#about to read 6, iclass 11, count 2 2006.285.06:01:46.82#ibcon#read 6, iclass 11, count 2 2006.285.06:01:46.82#ibcon#end of sib2, iclass 11, count 2 2006.285.06:01:46.82#ibcon#*mode == 0, iclass 11, count 2 2006.285.06:01:46.82#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.06:01:46.82#ibcon#[27=AT06-03\r\n] 2006.285.06:01:46.82#ibcon#*before write, iclass 11, count 2 2006.285.06:01:46.82#ibcon#enter sib2, iclass 11, count 2 2006.285.06:01:46.82#ibcon#flushed, iclass 11, count 2 2006.285.06:01:46.82#ibcon#about to write, iclass 11, count 2 2006.285.06:01:46.82#ibcon#wrote, iclass 11, count 2 2006.285.06:01:46.82#ibcon#about to read 3, iclass 11, count 2 2006.285.06:01:46.85#ibcon#read 3, iclass 11, count 2 2006.285.06:01:46.85#ibcon#about to read 4, iclass 11, count 2 2006.285.06:01:46.85#ibcon#read 4, iclass 11, count 2 2006.285.06:01:46.85#ibcon#about to read 5, iclass 11, count 2 2006.285.06:01:46.85#ibcon#read 5, iclass 11, count 2 2006.285.06:01:46.85#ibcon#about to read 6, iclass 11, count 2 2006.285.06:01:46.85#ibcon#read 6, iclass 11, count 2 2006.285.06:01:46.85#ibcon#end of sib2, iclass 11, count 2 2006.285.06:01:46.85#ibcon#*after write, iclass 11, count 2 2006.285.06:01:46.85#ibcon#*before return 0, iclass 11, count 2 2006.285.06:01:46.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:01:46.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:01:46.85#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.06:01:46.85#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:46.85#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:01:46.97#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:01:46.97#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:01:46.97#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:01:46.97#ibcon#first serial, iclass 11, count 0 2006.285.06:01:46.97#ibcon#enter sib2, iclass 11, count 0 2006.285.06:01:46.97#ibcon#flushed, iclass 11, count 0 2006.285.06:01:46.97#ibcon#about to write, iclass 11, count 0 2006.285.06:01:46.97#ibcon#wrote, iclass 11, count 0 2006.285.06:01:46.97#ibcon#about to read 3, iclass 11, count 0 2006.285.06:01:46.99#ibcon#read 3, iclass 11, count 0 2006.285.06:01:46.99#ibcon#about to read 4, iclass 11, count 0 2006.285.06:01:46.99#ibcon#read 4, iclass 11, count 0 2006.285.06:01:46.99#ibcon#about to read 5, iclass 11, count 0 2006.285.06:01:46.99#ibcon#read 5, iclass 11, count 0 2006.285.06:01:46.99#ibcon#about to read 6, iclass 11, count 0 2006.285.06:01:46.99#ibcon#read 6, iclass 11, count 0 2006.285.06:01:46.99#ibcon#end of sib2, iclass 11, count 0 2006.285.06:01:46.99#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:01:46.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:01:46.99#ibcon#[27=USB\r\n] 2006.285.06:01:46.99#ibcon#*before write, iclass 11, count 0 2006.285.06:01:46.99#ibcon#enter sib2, iclass 11, count 0 2006.285.06:01:46.99#ibcon#flushed, iclass 11, count 0 2006.285.06:01:46.99#ibcon#about to write, iclass 11, count 0 2006.285.06:01:46.99#ibcon#wrote, iclass 11, count 0 2006.285.06:01:46.99#ibcon#about to read 3, iclass 11, count 0 2006.285.06:01:47.02#ibcon#read 3, iclass 11, count 0 2006.285.06:01:47.02#ibcon#about to read 4, iclass 11, count 0 2006.285.06:01:47.02#ibcon#read 4, iclass 11, count 0 2006.285.06:01:47.02#ibcon#about to read 5, iclass 11, count 0 2006.285.06:01:47.02#ibcon#read 5, iclass 11, count 0 2006.285.06:01:47.02#ibcon#about to read 6, iclass 11, count 0 2006.285.06:01:47.02#ibcon#read 6, iclass 11, count 0 2006.285.06:01:47.02#ibcon#end of sib2, iclass 11, count 0 2006.285.06:01:47.02#ibcon#*after write, iclass 11, count 0 2006.285.06:01:47.02#ibcon#*before return 0, iclass 11, count 0 2006.285.06:01:47.02#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:01:47.02#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:01:47.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:01:47.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:01:47.02$vck44/vblo=7,734.99 2006.285.06:01:47.02#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.06:01:47.02#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.06:01:47.02#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:47.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:01:47.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:01:47.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:01:47.02#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:01:47.02#ibcon#first serial, iclass 13, count 0 2006.285.06:01:47.02#ibcon#enter sib2, iclass 13, count 0 2006.285.06:01:47.02#ibcon#flushed, iclass 13, count 0 2006.285.06:01:47.02#ibcon#about to write, iclass 13, count 0 2006.285.06:01:47.02#ibcon#wrote, iclass 13, count 0 2006.285.06:01:47.02#ibcon#about to read 3, iclass 13, count 0 2006.285.06:01:47.04#ibcon#read 3, iclass 13, count 0 2006.285.06:01:47.04#ibcon#about to read 4, iclass 13, count 0 2006.285.06:01:47.04#ibcon#read 4, iclass 13, count 0 2006.285.06:01:47.04#ibcon#about to read 5, iclass 13, count 0 2006.285.06:01:47.04#ibcon#read 5, iclass 13, count 0 2006.285.06:01:47.04#ibcon#about to read 6, iclass 13, count 0 2006.285.06:01:47.04#ibcon#read 6, iclass 13, count 0 2006.285.06:01:47.04#ibcon#end of sib2, iclass 13, count 0 2006.285.06:01:47.04#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:01:47.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:01:47.04#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:01:47.04#ibcon#*before write, iclass 13, count 0 2006.285.06:01:47.04#ibcon#enter sib2, iclass 13, count 0 2006.285.06:01:47.04#ibcon#flushed, iclass 13, count 0 2006.285.06:01:47.04#ibcon#about to write, iclass 13, count 0 2006.285.06:01:47.04#ibcon#wrote, iclass 13, count 0 2006.285.06:01:47.04#ibcon#about to read 3, iclass 13, count 0 2006.285.06:01:47.08#ibcon#read 3, iclass 13, count 0 2006.285.06:01:47.08#ibcon#about to read 4, iclass 13, count 0 2006.285.06:01:47.08#ibcon#read 4, iclass 13, count 0 2006.285.06:01:47.08#ibcon#about to read 5, iclass 13, count 0 2006.285.06:01:47.08#ibcon#read 5, iclass 13, count 0 2006.285.06:01:47.08#ibcon#about to read 6, iclass 13, count 0 2006.285.06:01:47.08#ibcon#read 6, iclass 13, count 0 2006.285.06:01:47.08#ibcon#end of sib2, iclass 13, count 0 2006.285.06:01:47.08#ibcon#*after write, iclass 13, count 0 2006.285.06:01:47.08#ibcon#*before return 0, iclass 13, count 0 2006.285.06:01:47.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:01:47.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:01:47.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:01:47.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:01:47.08$vck44/vb=7,4 2006.285.06:01:47.08#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.06:01:47.08#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.06:01:47.08#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:47.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:01:47.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:01:47.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:01:47.14#ibcon#enter wrdev, iclass 15, count 2 2006.285.06:01:47.14#ibcon#first serial, iclass 15, count 2 2006.285.06:01:47.14#ibcon#enter sib2, iclass 15, count 2 2006.285.06:01:47.14#ibcon#flushed, iclass 15, count 2 2006.285.06:01:47.14#ibcon#about to write, iclass 15, count 2 2006.285.06:01:47.14#ibcon#wrote, iclass 15, count 2 2006.285.06:01:47.14#ibcon#about to read 3, iclass 15, count 2 2006.285.06:01:47.16#ibcon#read 3, iclass 15, count 2 2006.285.06:01:47.16#ibcon#about to read 4, iclass 15, count 2 2006.285.06:01:47.16#ibcon#read 4, iclass 15, count 2 2006.285.06:01:47.16#ibcon#about to read 5, iclass 15, count 2 2006.285.06:01:47.16#ibcon#read 5, iclass 15, count 2 2006.285.06:01:47.16#ibcon#about to read 6, iclass 15, count 2 2006.285.06:01:47.16#ibcon#read 6, iclass 15, count 2 2006.285.06:01:47.16#ibcon#end of sib2, iclass 15, count 2 2006.285.06:01:47.16#ibcon#*mode == 0, iclass 15, count 2 2006.285.06:01:47.16#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.06:01:47.16#ibcon#[27=AT07-04\r\n] 2006.285.06:01:47.16#ibcon#*before write, iclass 15, count 2 2006.285.06:01:47.16#ibcon#enter sib2, iclass 15, count 2 2006.285.06:01:47.16#ibcon#flushed, iclass 15, count 2 2006.285.06:01:47.16#ibcon#about to write, iclass 15, count 2 2006.285.06:01:47.16#ibcon#wrote, iclass 15, count 2 2006.285.06:01:47.16#ibcon#about to read 3, iclass 15, count 2 2006.285.06:01:47.19#ibcon#read 3, iclass 15, count 2 2006.285.06:01:47.19#ibcon#about to read 4, iclass 15, count 2 2006.285.06:01:47.19#ibcon#read 4, iclass 15, count 2 2006.285.06:01:47.19#ibcon#about to read 5, iclass 15, count 2 2006.285.06:01:47.19#ibcon#read 5, iclass 15, count 2 2006.285.06:01:47.19#ibcon#about to read 6, iclass 15, count 2 2006.285.06:01:47.19#ibcon#read 6, iclass 15, count 2 2006.285.06:01:47.19#ibcon#end of sib2, iclass 15, count 2 2006.285.06:01:47.19#ibcon#*after write, iclass 15, count 2 2006.285.06:01:47.19#ibcon#*before return 0, iclass 15, count 2 2006.285.06:01:47.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:01:47.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:01:47.19#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.06:01:47.19#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:47.19#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:01:47.31#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:01:47.31#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:01:47.31#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:01:47.31#ibcon#first serial, iclass 15, count 0 2006.285.06:01:47.31#ibcon#enter sib2, iclass 15, count 0 2006.285.06:01:47.31#ibcon#flushed, iclass 15, count 0 2006.285.06:01:47.31#ibcon#about to write, iclass 15, count 0 2006.285.06:01:47.31#ibcon#wrote, iclass 15, count 0 2006.285.06:01:47.31#ibcon#about to read 3, iclass 15, count 0 2006.285.06:01:47.33#ibcon#read 3, iclass 15, count 0 2006.285.06:01:47.33#ibcon#about to read 4, iclass 15, count 0 2006.285.06:01:47.33#ibcon#read 4, iclass 15, count 0 2006.285.06:01:47.33#ibcon#about to read 5, iclass 15, count 0 2006.285.06:01:47.33#ibcon#read 5, iclass 15, count 0 2006.285.06:01:47.33#ibcon#about to read 6, iclass 15, count 0 2006.285.06:01:47.33#ibcon#read 6, iclass 15, count 0 2006.285.06:01:47.33#ibcon#end of sib2, iclass 15, count 0 2006.285.06:01:47.33#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:01:47.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:01:47.33#ibcon#[27=USB\r\n] 2006.285.06:01:47.33#ibcon#*before write, iclass 15, count 0 2006.285.06:01:47.33#ibcon#enter sib2, iclass 15, count 0 2006.285.06:01:47.33#ibcon#flushed, iclass 15, count 0 2006.285.06:01:47.33#ibcon#about to write, iclass 15, count 0 2006.285.06:01:47.33#ibcon#wrote, iclass 15, count 0 2006.285.06:01:47.33#ibcon#about to read 3, iclass 15, count 0 2006.285.06:01:47.36#ibcon#read 3, iclass 15, count 0 2006.285.06:01:47.36#ibcon#about to read 4, iclass 15, count 0 2006.285.06:01:47.36#ibcon#read 4, iclass 15, count 0 2006.285.06:01:47.36#ibcon#about to read 5, iclass 15, count 0 2006.285.06:01:47.36#ibcon#read 5, iclass 15, count 0 2006.285.06:01:47.36#ibcon#about to read 6, iclass 15, count 0 2006.285.06:01:47.36#ibcon#read 6, iclass 15, count 0 2006.285.06:01:47.36#ibcon#end of sib2, iclass 15, count 0 2006.285.06:01:47.36#ibcon#*after write, iclass 15, count 0 2006.285.06:01:47.36#ibcon#*before return 0, iclass 15, count 0 2006.285.06:01:47.36#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:01:47.36#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:01:47.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:01:47.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:01:47.36$vck44/vblo=8,744.99 2006.285.06:01:47.36#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.06:01:47.36#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.06:01:47.36#ibcon#ireg 17 cls_cnt 0 2006.285.06:01:47.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:01:47.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:01:47.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:01:47.36#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:01:47.36#ibcon#first serial, iclass 17, count 0 2006.285.06:01:47.36#ibcon#enter sib2, iclass 17, count 0 2006.285.06:01:47.36#ibcon#flushed, iclass 17, count 0 2006.285.06:01:47.36#ibcon#about to write, iclass 17, count 0 2006.285.06:01:47.36#ibcon#wrote, iclass 17, count 0 2006.285.06:01:47.36#ibcon#about to read 3, iclass 17, count 0 2006.285.06:01:47.38#ibcon#read 3, iclass 17, count 0 2006.285.06:01:47.38#ibcon#about to read 4, iclass 17, count 0 2006.285.06:01:47.38#ibcon#read 4, iclass 17, count 0 2006.285.06:01:47.38#ibcon#about to read 5, iclass 17, count 0 2006.285.06:01:47.38#ibcon#read 5, iclass 17, count 0 2006.285.06:01:47.38#ibcon#about to read 6, iclass 17, count 0 2006.285.06:01:47.38#ibcon#read 6, iclass 17, count 0 2006.285.06:01:47.38#ibcon#end of sib2, iclass 17, count 0 2006.285.06:01:47.38#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:01:47.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:01:47.38#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:01:47.38#ibcon#*before write, iclass 17, count 0 2006.285.06:01:47.38#ibcon#enter sib2, iclass 17, count 0 2006.285.06:01:47.38#ibcon#flushed, iclass 17, count 0 2006.285.06:01:47.38#ibcon#about to write, iclass 17, count 0 2006.285.06:01:47.38#ibcon#wrote, iclass 17, count 0 2006.285.06:01:47.38#ibcon#about to read 3, iclass 17, count 0 2006.285.06:01:47.42#ibcon#read 3, iclass 17, count 0 2006.285.06:01:47.42#ibcon#about to read 4, iclass 17, count 0 2006.285.06:01:47.42#ibcon#read 4, iclass 17, count 0 2006.285.06:01:47.42#ibcon#about to read 5, iclass 17, count 0 2006.285.06:01:47.42#ibcon#read 5, iclass 17, count 0 2006.285.06:01:47.42#ibcon#about to read 6, iclass 17, count 0 2006.285.06:01:47.42#ibcon#read 6, iclass 17, count 0 2006.285.06:01:47.42#ibcon#end of sib2, iclass 17, count 0 2006.285.06:01:47.42#ibcon#*after write, iclass 17, count 0 2006.285.06:01:47.42#ibcon#*before return 0, iclass 17, count 0 2006.285.06:01:47.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:01:47.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:01:47.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:01:47.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:01:47.42$vck44/vb=8,4 2006.285.06:01:47.42#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.06:01:47.42#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.06:01:47.42#ibcon#ireg 11 cls_cnt 2 2006.285.06:01:47.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:01:47.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:01:47.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:01:47.48#ibcon#enter wrdev, iclass 19, count 2 2006.285.06:01:47.48#ibcon#first serial, iclass 19, count 2 2006.285.06:01:47.48#ibcon#enter sib2, iclass 19, count 2 2006.285.06:01:47.48#ibcon#flushed, iclass 19, count 2 2006.285.06:01:47.48#ibcon#about to write, iclass 19, count 2 2006.285.06:01:47.48#ibcon#wrote, iclass 19, count 2 2006.285.06:01:47.48#ibcon#about to read 3, iclass 19, count 2 2006.285.06:01:47.50#ibcon#read 3, iclass 19, count 2 2006.285.06:01:47.50#ibcon#about to read 4, iclass 19, count 2 2006.285.06:01:47.50#ibcon#read 4, iclass 19, count 2 2006.285.06:01:47.50#ibcon#about to read 5, iclass 19, count 2 2006.285.06:01:47.50#ibcon#read 5, iclass 19, count 2 2006.285.06:01:47.50#ibcon#about to read 6, iclass 19, count 2 2006.285.06:01:47.50#ibcon#read 6, iclass 19, count 2 2006.285.06:01:47.50#ibcon#end of sib2, iclass 19, count 2 2006.285.06:01:47.50#ibcon#*mode == 0, iclass 19, count 2 2006.285.06:01:47.50#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.06:01:47.50#ibcon#[27=AT08-04\r\n] 2006.285.06:01:47.50#ibcon#*before write, iclass 19, count 2 2006.285.06:01:47.50#ibcon#enter sib2, iclass 19, count 2 2006.285.06:01:47.50#ibcon#flushed, iclass 19, count 2 2006.285.06:01:47.50#ibcon#about to write, iclass 19, count 2 2006.285.06:01:47.50#ibcon#wrote, iclass 19, count 2 2006.285.06:01:47.50#ibcon#about to read 3, iclass 19, count 2 2006.285.06:01:47.53#ibcon#read 3, iclass 19, count 2 2006.285.06:01:47.53#ibcon#about to read 4, iclass 19, count 2 2006.285.06:01:47.53#ibcon#read 4, iclass 19, count 2 2006.285.06:01:47.53#ibcon#about to read 5, iclass 19, count 2 2006.285.06:01:47.53#ibcon#read 5, iclass 19, count 2 2006.285.06:01:47.53#ibcon#about to read 6, iclass 19, count 2 2006.285.06:01:47.53#ibcon#read 6, iclass 19, count 2 2006.285.06:01:47.53#ibcon#end of sib2, iclass 19, count 2 2006.285.06:01:47.53#ibcon#*after write, iclass 19, count 2 2006.285.06:01:47.53#ibcon#*before return 0, iclass 19, count 2 2006.285.06:01:47.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:01:47.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:01:47.53#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.06:01:47.53#ibcon#ireg 7 cls_cnt 0 2006.285.06:01:47.53#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:01:47.65#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:01:47.65#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:01:47.65#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:01:47.65#ibcon#first serial, iclass 19, count 0 2006.285.06:01:47.65#ibcon#enter sib2, iclass 19, count 0 2006.285.06:01:47.65#ibcon#flushed, iclass 19, count 0 2006.285.06:01:47.65#ibcon#about to write, iclass 19, count 0 2006.285.06:01:47.65#ibcon#wrote, iclass 19, count 0 2006.285.06:01:47.65#ibcon#about to read 3, iclass 19, count 0 2006.285.06:01:47.67#ibcon#read 3, iclass 19, count 0 2006.285.06:01:47.67#ibcon#about to read 4, iclass 19, count 0 2006.285.06:01:47.67#ibcon#read 4, iclass 19, count 0 2006.285.06:01:47.67#ibcon#about to read 5, iclass 19, count 0 2006.285.06:01:47.67#ibcon#read 5, iclass 19, count 0 2006.285.06:01:47.67#ibcon#about to read 6, iclass 19, count 0 2006.285.06:01:47.67#ibcon#read 6, iclass 19, count 0 2006.285.06:01:47.67#ibcon#end of sib2, iclass 19, count 0 2006.285.06:01:47.67#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:01:47.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:01:47.67#ibcon#[27=USB\r\n] 2006.285.06:01:47.67#ibcon#*before write, iclass 19, count 0 2006.285.06:01:47.67#ibcon#enter sib2, iclass 19, count 0 2006.285.06:01:47.67#ibcon#flushed, iclass 19, count 0 2006.285.06:01:47.67#ibcon#about to write, iclass 19, count 0 2006.285.06:01:47.67#ibcon#wrote, iclass 19, count 0 2006.285.06:01:47.67#ibcon#about to read 3, iclass 19, count 0 2006.285.06:01:47.70#ibcon#read 3, iclass 19, count 0 2006.285.06:01:47.70#ibcon#about to read 4, iclass 19, count 0 2006.285.06:01:47.70#ibcon#read 4, iclass 19, count 0 2006.285.06:01:47.70#ibcon#about to read 5, iclass 19, count 0 2006.285.06:01:47.70#ibcon#read 5, iclass 19, count 0 2006.285.06:01:47.70#ibcon#about to read 6, iclass 19, count 0 2006.285.06:01:47.70#ibcon#read 6, iclass 19, count 0 2006.285.06:01:47.70#ibcon#end of sib2, iclass 19, count 0 2006.285.06:01:47.70#ibcon#*after write, iclass 19, count 0 2006.285.06:01:47.70#ibcon#*before return 0, iclass 19, count 0 2006.285.06:01:47.70#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:01:47.70#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:01:47.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:01:47.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:01:47.70$vck44/vabw=wide 2006.285.06:01:47.70#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.06:01:47.70#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.06:01:47.70#ibcon#ireg 8 cls_cnt 0 2006.285.06:01:47.70#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:01:47.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:01:47.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:01:47.70#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:01:47.70#ibcon#first serial, iclass 21, count 0 2006.285.06:01:47.70#ibcon#enter sib2, iclass 21, count 0 2006.285.06:01:47.70#ibcon#flushed, iclass 21, count 0 2006.285.06:01:47.70#ibcon#about to write, iclass 21, count 0 2006.285.06:01:47.70#ibcon#wrote, iclass 21, count 0 2006.285.06:01:47.70#ibcon#about to read 3, iclass 21, count 0 2006.285.06:01:47.72#ibcon#read 3, iclass 21, count 0 2006.285.06:01:47.72#ibcon#about to read 4, iclass 21, count 0 2006.285.06:01:47.72#ibcon#read 4, iclass 21, count 0 2006.285.06:01:47.72#ibcon#about to read 5, iclass 21, count 0 2006.285.06:01:47.72#ibcon#read 5, iclass 21, count 0 2006.285.06:01:47.72#ibcon#about to read 6, iclass 21, count 0 2006.285.06:01:47.72#ibcon#read 6, iclass 21, count 0 2006.285.06:01:47.72#ibcon#end of sib2, iclass 21, count 0 2006.285.06:01:47.72#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:01:47.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:01:47.72#ibcon#[25=BW32\r\n] 2006.285.06:01:47.72#ibcon#*before write, iclass 21, count 0 2006.285.06:01:47.72#ibcon#enter sib2, iclass 21, count 0 2006.285.06:01:47.72#ibcon#flushed, iclass 21, count 0 2006.285.06:01:47.72#ibcon#about to write, iclass 21, count 0 2006.285.06:01:47.72#ibcon#wrote, iclass 21, count 0 2006.285.06:01:47.72#ibcon#about to read 3, iclass 21, count 0 2006.285.06:01:47.75#ibcon#read 3, iclass 21, count 0 2006.285.06:01:47.75#ibcon#about to read 4, iclass 21, count 0 2006.285.06:01:47.75#ibcon#read 4, iclass 21, count 0 2006.285.06:01:47.75#ibcon#about to read 5, iclass 21, count 0 2006.285.06:01:47.75#ibcon#read 5, iclass 21, count 0 2006.285.06:01:47.75#ibcon#about to read 6, iclass 21, count 0 2006.285.06:01:47.75#ibcon#read 6, iclass 21, count 0 2006.285.06:01:47.75#ibcon#end of sib2, iclass 21, count 0 2006.285.06:01:47.75#ibcon#*after write, iclass 21, count 0 2006.285.06:01:47.75#ibcon#*before return 0, iclass 21, count 0 2006.285.06:01:47.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:01:47.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:01:47.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:01:47.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:01:47.75$vck44/vbbw=wide 2006.285.06:01:47.75#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.06:01:47.75#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.06:01:47.75#ibcon#ireg 8 cls_cnt 0 2006.285.06:01:47.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:01:47.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:01:47.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:01:47.82#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:01:47.82#ibcon#first serial, iclass 23, count 0 2006.285.06:01:47.82#ibcon#enter sib2, iclass 23, count 0 2006.285.06:01:47.82#ibcon#flushed, iclass 23, count 0 2006.285.06:01:47.82#ibcon#about to write, iclass 23, count 0 2006.285.06:01:47.82#ibcon#wrote, iclass 23, count 0 2006.285.06:01:47.82#ibcon#about to read 3, iclass 23, count 0 2006.285.06:01:47.84#ibcon#read 3, iclass 23, count 0 2006.285.06:01:47.84#ibcon#about to read 4, iclass 23, count 0 2006.285.06:01:47.84#ibcon#read 4, iclass 23, count 0 2006.285.06:01:47.84#ibcon#about to read 5, iclass 23, count 0 2006.285.06:01:47.84#ibcon#read 5, iclass 23, count 0 2006.285.06:01:47.84#ibcon#about to read 6, iclass 23, count 0 2006.285.06:01:47.84#ibcon#read 6, iclass 23, count 0 2006.285.06:01:47.84#ibcon#end of sib2, iclass 23, count 0 2006.285.06:01:47.84#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:01:47.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:01:47.84#ibcon#[27=BW32\r\n] 2006.285.06:01:47.84#ibcon#*before write, iclass 23, count 0 2006.285.06:01:47.84#ibcon#enter sib2, iclass 23, count 0 2006.285.06:01:47.84#ibcon#flushed, iclass 23, count 0 2006.285.06:01:47.84#ibcon#about to write, iclass 23, count 0 2006.285.06:01:47.84#ibcon#wrote, iclass 23, count 0 2006.285.06:01:47.84#ibcon#about to read 3, iclass 23, count 0 2006.285.06:01:47.87#ibcon#read 3, iclass 23, count 0 2006.285.06:01:47.87#ibcon#about to read 4, iclass 23, count 0 2006.285.06:01:47.87#ibcon#read 4, iclass 23, count 0 2006.285.06:01:47.87#ibcon#about to read 5, iclass 23, count 0 2006.285.06:01:47.87#ibcon#read 5, iclass 23, count 0 2006.285.06:01:47.87#ibcon#about to read 6, iclass 23, count 0 2006.285.06:01:47.87#ibcon#read 6, iclass 23, count 0 2006.285.06:01:47.87#ibcon#end of sib2, iclass 23, count 0 2006.285.06:01:47.87#ibcon#*after write, iclass 23, count 0 2006.285.06:01:47.87#ibcon#*before return 0, iclass 23, count 0 2006.285.06:01:47.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:01:47.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:01:47.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:01:47.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:01:47.87$setupk4/ifdk4 2006.285.06:01:47.87$ifdk4/lo= 2006.285.06:01:47.87$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:01:47.87$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:01:47.87$ifdk4/patch= 2006.285.06:01:47.87$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:01:47.87$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:01:47.87$setupk4/!*+20s 2006.285.06:01:51.28#abcon#<5=/04 4.1 6.8 25.12 661014.0\r\n> 2006.285.06:01:51.30#abcon#{5=INTERFACE CLEAR} 2006.285.06:01:51.36#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:02:01.45#abcon#<5=/04 4.1 6.8 25.12 661014.0\r\n> 2006.285.06:02:01.47#abcon#{5=INTERFACE CLEAR} 2006.285.06:02:01.53#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:02:02.36$setupk4/"tpicd 2006.285.06:02:02.36$setupk4/echo=off 2006.285.06:02:02.36$setupk4/xlog=off 2006.285.06:02:02.36:!2006.285.06:04:25 2006.285.06:02:38.14#trakl#Source acquired 2006.285.06:02:40.14#flagr#flagr/antenna,acquired 2006.285.06:04:25.00:preob 2006.285.06:04:26.14/onsource/TRACKING 2006.285.06:04:26.14:!2006.285.06:04:35 2006.285.06:04:35.00:"tape 2006.285.06:04:35.00:"st=record 2006.285.06:04:35.00:data_valid=on 2006.285.06:04:35.00:midob 2006.285.06:04:35.14/onsource/TRACKING 2006.285.06:04:35.14/wx/25.09,1014.0,66 2006.285.06:04:35.22/cable/+6.4762E-03 2006.285.06:04:36.31/va/01,07,usb,yes,35,38 2006.285.06:04:36.31/va/02,06,usb,yes,35,36 2006.285.06:04:36.31/va/03,07,usb,yes,35,37 2006.285.06:04:36.31/va/04,06,usb,yes,36,38 2006.285.06:04:36.31/va/05,03,usb,yes,36,36 2006.285.06:04:36.31/va/06,04,usb,yes,32,32 2006.285.06:04:36.31/va/07,04,usb,yes,33,34 2006.285.06:04:36.31/va/08,03,usb,yes,34,41 2006.285.06:04:36.54/valo/01,524.99,yes,locked 2006.285.06:04:36.54/valo/02,534.99,yes,locked 2006.285.06:04:36.54/valo/03,564.99,yes,locked 2006.285.06:04:36.54/valo/04,624.99,yes,locked 2006.285.06:04:36.54/valo/05,734.99,yes,locked 2006.285.06:04:36.54/valo/06,814.99,yes,locked 2006.285.06:04:36.54/valo/07,864.99,yes,locked 2006.285.06:04:36.54/valo/08,884.99,yes,locked 2006.285.06:04:37.63/vb/01,04,usb,yes,33,30 2006.285.06:04:37.63/vb/02,05,usb,yes,31,31 2006.285.06:04:37.63/vb/03,04,usb,yes,32,35 2006.285.06:04:37.63/vb/04,05,usb,yes,32,31 2006.285.06:04:37.63/vb/05,04,usb,yes,29,31 2006.285.06:04:37.63/vb/06,03,usb,yes,41,37 2006.285.06:04:37.63/vb/07,04,usb,yes,33,33 2006.285.06:04:37.63/vb/08,04,usb,yes,30,34 2006.285.06:04:37.86/vblo/01,629.99,yes,locked 2006.285.06:04:37.86/vblo/02,634.99,yes,locked 2006.285.06:04:37.86/vblo/03,649.99,yes,locked 2006.285.06:04:37.86/vblo/04,679.99,yes,locked 2006.285.06:04:37.86/vblo/05,709.99,yes,locked 2006.285.06:04:37.86/vblo/06,719.99,yes,locked 2006.285.06:04:37.86/vblo/07,734.99,yes,locked 2006.285.06:04:37.86/vblo/08,744.99,yes,locked 2006.285.06:04:38.01/vabw/8 2006.285.06:04:38.16/vbbw/8 2006.285.06:04:38.25/xfe/off,on,12.2 2006.285.06:04:38.63/ifatt/23,28,28,28 2006.285.06:04:39.07/fmout-gps/S +2.75E-07 2006.285.06:04:39.09:!2006.285.06:05:15 2006.285.06:05:15.00:data_valid=off 2006.285.06:05:15.00:"et 2006.285.06:05:15.00:!+3s 2006.285.06:05:18.02:"tape 2006.285.06:05:18.02:postob 2006.285.06:05:18.11/cable/+6.4747E-03 2006.285.06:05:18.11/wx/25.08,1014.0,66 2006.285.06:05:18.17/fmout-gps/S +2.75E-07 2006.285.06:05:18.17:scan_name=285-0607,jd0610,280 2006.285.06:05:18.17:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.285.06:05:20.13#flagr#flagr/antenna,new-source 2006.285.06:05:20.13:checkk5 2006.285.06:05:20.50/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:05:20.85/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:05:21.24/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:05:21.64/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:05:22.19/chk_obsdata//k5ts1/T2850604??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:05:22.55/chk_obsdata//k5ts2/T2850604??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:05:22.94/chk_obsdata//k5ts3/T2850604??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:05:23.35/chk_obsdata//k5ts4/T2850604??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:05:24.18/k5log//k5ts1_log_newline 2006.285.06:05:29.99/k5log//k5ts2_log_newline 2006.285.06:05:30.78/k5log//k5ts3_log_newline 2006.285.06:05:31.75/k5log//k5ts4_log_newline 2006.285.06:05:31.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:05:31.77:setupk4=1 2006.285.06:05:31.77$setupk4/echo=on 2006.285.06:05:31.77$setupk4/pcalon 2006.285.06:05:31.77$pcalon/"no phase cal control is implemented here 2006.285.06:05:31.77$setupk4/"tpicd=stop 2006.285.06:05:31.77$setupk4/"rec=synch_on 2006.285.06:05:31.77$setupk4/"rec_mode=128 2006.285.06:05:31.77$setupk4/!* 2006.285.06:05:31.77$setupk4/recpk4 2006.285.06:05:31.77$recpk4/recpatch= 2006.285.06:05:31.77$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:05:31.77$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:05:31.77$setupk4/vck44 2006.285.06:05:31.77$vck44/valo=1,524.99 2006.285.06:05:31.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.06:05:31.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.06:05:31.77#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:31.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:05:31.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:05:31.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:05:31.77#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:05:31.77#ibcon#first serial, iclass 6, count 0 2006.285.06:05:31.77#ibcon#enter sib2, iclass 6, count 0 2006.285.06:05:31.77#ibcon#flushed, iclass 6, count 0 2006.285.06:05:31.77#ibcon#about to write, iclass 6, count 0 2006.285.06:05:31.77#ibcon#wrote, iclass 6, count 0 2006.285.06:05:31.77#ibcon#about to read 3, iclass 6, count 0 2006.285.06:05:31.79#ibcon#read 3, iclass 6, count 0 2006.285.06:05:31.79#ibcon#about to read 4, iclass 6, count 0 2006.285.06:05:31.79#ibcon#read 4, iclass 6, count 0 2006.285.06:05:31.79#ibcon#about to read 5, iclass 6, count 0 2006.285.06:05:31.79#ibcon#read 5, iclass 6, count 0 2006.285.06:05:31.79#ibcon#about to read 6, iclass 6, count 0 2006.285.06:05:31.79#ibcon#read 6, iclass 6, count 0 2006.285.06:05:31.79#ibcon#end of sib2, iclass 6, count 0 2006.285.06:05:31.79#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:05:31.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:05:31.79#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:05:31.79#ibcon#*before write, iclass 6, count 0 2006.285.06:05:31.79#ibcon#enter sib2, iclass 6, count 0 2006.285.06:05:31.79#ibcon#flushed, iclass 6, count 0 2006.285.06:05:31.79#ibcon#about to write, iclass 6, count 0 2006.285.06:05:31.79#ibcon#wrote, iclass 6, count 0 2006.285.06:05:31.79#ibcon#about to read 3, iclass 6, count 0 2006.285.06:05:31.84#ibcon#read 3, iclass 6, count 0 2006.285.06:05:31.84#ibcon#about to read 4, iclass 6, count 0 2006.285.06:05:31.84#ibcon#read 4, iclass 6, count 0 2006.285.06:05:31.84#ibcon#about to read 5, iclass 6, count 0 2006.285.06:05:31.84#ibcon#read 5, iclass 6, count 0 2006.285.06:05:31.84#ibcon#about to read 6, iclass 6, count 0 2006.285.06:05:31.84#ibcon#read 6, iclass 6, count 0 2006.285.06:05:31.84#ibcon#end of sib2, iclass 6, count 0 2006.285.06:05:31.84#ibcon#*after write, iclass 6, count 0 2006.285.06:05:31.84#ibcon#*before return 0, iclass 6, count 0 2006.285.06:05:31.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:05:31.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:05:31.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:05:31.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:05:31.84$vck44/va=1,7 2006.285.06:05:31.84#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.06:05:31.84#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.06:05:31.84#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:31.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:05:31.84#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:05:31.84#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:05:31.84#ibcon#enter wrdev, iclass 10, count 2 2006.285.06:05:31.84#ibcon#first serial, iclass 10, count 2 2006.285.06:05:31.84#ibcon#enter sib2, iclass 10, count 2 2006.285.06:05:31.84#ibcon#flushed, iclass 10, count 2 2006.285.06:05:31.84#ibcon#about to write, iclass 10, count 2 2006.285.06:05:31.84#ibcon#wrote, iclass 10, count 2 2006.285.06:05:31.84#ibcon#about to read 3, iclass 10, count 2 2006.285.06:05:31.86#ibcon#read 3, iclass 10, count 2 2006.285.06:05:31.86#ibcon#about to read 4, iclass 10, count 2 2006.285.06:05:31.86#ibcon#read 4, iclass 10, count 2 2006.285.06:05:31.86#ibcon#about to read 5, iclass 10, count 2 2006.285.06:05:31.86#ibcon#read 5, iclass 10, count 2 2006.285.06:05:31.86#ibcon#about to read 6, iclass 10, count 2 2006.285.06:05:31.86#ibcon#read 6, iclass 10, count 2 2006.285.06:05:31.86#ibcon#end of sib2, iclass 10, count 2 2006.285.06:05:31.86#ibcon#*mode == 0, iclass 10, count 2 2006.285.06:05:31.86#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.06:05:31.86#ibcon#[25=AT01-07\r\n] 2006.285.06:05:31.86#ibcon#*before write, iclass 10, count 2 2006.285.06:05:31.86#ibcon#enter sib2, iclass 10, count 2 2006.285.06:05:31.86#ibcon#flushed, iclass 10, count 2 2006.285.06:05:31.86#ibcon#about to write, iclass 10, count 2 2006.285.06:05:31.86#ibcon#wrote, iclass 10, count 2 2006.285.06:05:31.86#ibcon#about to read 3, iclass 10, count 2 2006.285.06:05:31.89#ibcon#read 3, iclass 10, count 2 2006.285.06:05:31.89#ibcon#about to read 4, iclass 10, count 2 2006.285.06:05:31.89#ibcon#read 4, iclass 10, count 2 2006.285.06:05:31.89#ibcon#about to read 5, iclass 10, count 2 2006.285.06:05:31.89#ibcon#read 5, iclass 10, count 2 2006.285.06:05:31.89#ibcon#about to read 6, iclass 10, count 2 2006.285.06:05:31.89#ibcon#read 6, iclass 10, count 2 2006.285.06:05:31.89#ibcon#end of sib2, iclass 10, count 2 2006.285.06:05:31.89#ibcon#*after write, iclass 10, count 2 2006.285.06:05:31.89#ibcon#*before return 0, iclass 10, count 2 2006.285.06:05:31.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:05:31.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:05:31.89#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.06:05:31.89#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:31.89#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:05:32.01#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:05:32.01#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:05:32.01#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:05:32.01#ibcon#first serial, iclass 10, count 0 2006.285.06:05:32.01#ibcon#enter sib2, iclass 10, count 0 2006.285.06:05:32.01#ibcon#flushed, iclass 10, count 0 2006.285.06:05:32.01#ibcon#about to write, iclass 10, count 0 2006.285.06:05:32.01#ibcon#wrote, iclass 10, count 0 2006.285.06:05:32.01#ibcon#about to read 3, iclass 10, count 0 2006.285.06:05:32.03#ibcon#read 3, iclass 10, count 0 2006.285.06:05:32.03#ibcon#about to read 4, iclass 10, count 0 2006.285.06:05:32.03#ibcon#read 4, iclass 10, count 0 2006.285.06:05:32.03#ibcon#about to read 5, iclass 10, count 0 2006.285.06:05:32.03#ibcon#read 5, iclass 10, count 0 2006.285.06:05:32.03#ibcon#about to read 6, iclass 10, count 0 2006.285.06:05:32.03#ibcon#read 6, iclass 10, count 0 2006.285.06:05:32.03#ibcon#end of sib2, iclass 10, count 0 2006.285.06:05:32.03#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:05:32.03#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:05:32.03#ibcon#[25=USB\r\n] 2006.285.06:05:32.03#ibcon#*before write, iclass 10, count 0 2006.285.06:05:32.03#ibcon#enter sib2, iclass 10, count 0 2006.285.06:05:32.03#ibcon#flushed, iclass 10, count 0 2006.285.06:05:32.03#ibcon#about to write, iclass 10, count 0 2006.285.06:05:32.03#ibcon#wrote, iclass 10, count 0 2006.285.06:05:32.03#ibcon#about to read 3, iclass 10, count 0 2006.285.06:05:32.06#ibcon#read 3, iclass 10, count 0 2006.285.06:05:32.06#ibcon#about to read 4, iclass 10, count 0 2006.285.06:05:32.06#ibcon#read 4, iclass 10, count 0 2006.285.06:05:32.06#ibcon#about to read 5, iclass 10, count 0 2006.285.06:05:32.06#ibcon#read 5, iclass 10, count 0 2006.285.06:05:32.06#ibcon#about to read 6, iclass 10, count 0 2006.285.06:05:32.06#ibcon#read 6, iclass 10, count 0 2006.285.06:05:32.06#ibcon#end of sib2, iclass 10, count 0 2006.285.06:05:32.06#ibcon#*after write, iclass 10, count 0 2006.285.06:05:32.06#ibcon#*before return 0, iclass 10, count 0 2006.285.06:05:32.06#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:05:32.06#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:05:32.06#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:05:32.06#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:05:32.06$vck44/valo=2,534.99 2006.285.06:05:32.06#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.06:05:32.06#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.06:05:32.06#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:32.06#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:05:32.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:05:32.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:05:32.06#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:05:32.06#ibcon#first serial, iclass 12, count 0 2006.285.06:05:32.06#ibcon#enter sib2, iclass 12, count 0 2006.285.06:05:32.06#ibcon#flushed, iclass 12, count 0 2006.285.06:05:32.06#ibcon#about to write, iclass 12, count 0 2006.285.06:05:32.06#ibcon#wrote, iclass 12, count 0 2006.285.06:05:32.06#ibcon#about to read 3, iclass 12, count 0 2006.285.06:05:32.08#ibcon#read 3, iclass 12, count 0 2006.285.06:05:32.08#ibcon#about to read 4, iclass 12, count 0 2006.285.06:05:32.08#ibcon#read 4, iclass 12, count 0 2006.285.06:05:32.08#ibcon#about to read 5, iclass 12, count 0 2006.285.06:05:32.08#ibcon#read 5, iclass 12, count 0 2006.285.06:05:32.08#ibcon#about to read 6, iclass 12, count 0 2006.285.06:05:32.08#ibcon#read 6, iclass 12, count 0 2006.285.06:05:32.08#ibcon#end of sib2, iclass 12, count 0 2006.285.06:05:32.08#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:05:32.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:05:32.08#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:05:32.08#ibcon#*before write, iclass 12, count 0 2006.285.06:05:32.08#ibcon#enter sib2, iclass 12, count 0 2006.285.06:05:32.08#ibcon#flushed, iclass 12, count 0 2006.285.06:05:32.08#ibcon#about to write, iclass 12, count 0 2006.285.06:05:32.08#ibcon#wrote, iclass 12, count 0 2006.285.06:05:32.08#ibcon#about to read 3, iclass 12, count 0 2006.285.06:05:32.12#ibcon#read 3, iclass 12, count 0 2006.285.06:05:32.12#ibcon#about to read 4, iclass 12, count 0 2006.285.06:05:32.12#ibcon#read 4, iclass 12, count 0 2006.285.06:05:32.12#ibcon#about to read 5, iclass 12, count 0 2006.285.06:05:32.12#ibcon#read 5, iclass 12, count 0 2006.285.06:05:32.12#ibcon#about to read 6, iclass 12, count 0 2006.285.06:05:32.12#ibcon#read 6, iclass 12, count 0 2006.285.06:05:32.12#ibcon#end of sib2, iclass 12, count 0 2006.285.06:05:32.12#ibcon#*after write, iclass 12, count 0 2006.285.06:05:32.12#ibcon#*before return 0, iclass 12, count 0 2006.285.06:05:32.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:05:32.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:05:32.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:05:32.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:05:32.14$vck44/va=2,6 2006.285.06:05:32.14#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.06:05:32.14#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.06:05:32.14#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:32.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:05:32.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:05:32.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:05:32.18#ibcon#enter wrdev, iclass 14, count 2 2006.285.06:05:32.18#ibcon#first serial, iclass 14, count 2 2006.285.06:05:32.18#ibcon#enter sib2, iclass 14, count 2 2006.285.06:05:32.18#ibcon#flushed, iclass 14, count 2 2006.285.06:05:32.18#ibcon#about to write, iclass 14, count 2 2006.285.06:05:32.18#ibcon#wrote, iclass 14, count 2 2006.285.06:05:32.18#ibcon#about to read 3, iclass 14, count 2 2006.285.06:05:32.20#ibcon#read 3, iclass 14, count 2 2006.285.06:05:32.20#ibcon#about to read 4, iclass 14, count 2 2006.285.06:05:32.20#ibcon#read 4, iclass 14, count 2 2006.285.06:05:32.20#ibcon#about to read 5, iclass 14, count 2 2006.285.06:05:32.20#ibcon#read 5, iclass 14, count 2 2006.285.06:05:32.20#ibcon#about to read 6, iclass 14, count 2 2006.285.06:05:32.20#ibcon#read 6, iclass 14, count 2 2006.285.06:05:32.20#ibcon#end of sib2, iclass 14, count 2 2006.285.06:05:32.20#ibcon#*mode == 0, iclass 14, count 2 2006.285.06:05:32.20#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.06:05:32.20#ibcon#[25=AT02-06\r\n] 2006.285.06:05:32.20#ibcon#*before write, iclass 14, count 2 2006.285.06:05:32.20#ibcon#enter sib2, iclass 14, count 2 2006.285.06:05:32.20#ibcon#flushed, iclass 14, count 2 2006.285.06:05:32.20#ibcon#about to write, iclass 14, count 2 2006.285.06:05:32.20#ibcon#wrote, iclass 14, count 2 2006.285.06:05:32.20#ibcon#about to read 3, iclass 14, count 2 2006.285.06:05:32.23#ibcon#read 3, iclass 14, count 2 2006.285.06:05:32.23#ibcon#about to read 4, iclass 14, count 2 2006.285.06:05:32.23#ibcon#read 4, iclass 14, count 2 2006.285.06:05:32.23#ibcon#about to read 5, iclass 14, count 2 2006.285.06:05:32.23#ibcon#read 5, iclass 14, count 2 2006.285.06:05:32.23#ibcon#about to read 6, iclass 14, count 2 2006.285.06:05:32.23#ibcon#read 6, iclass 14, count 2 2006.285.06:05:32.23#ibcon#end of sib2, iclass 14, count 2 2006.285.06:05:32.23#ibcon#*after write, iclass 14, count 2 2006.285.06:05:32.23#ibcon#*before return 0, iclass 14, count 2 2006.285.06:05:32.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:05:32.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:05:32.23#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.06:05:32.23#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:32.23#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:05:32.35#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:05:32.35#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:05:32.35#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:05:32.35#ibcon#first serial, iclass 14, count 0 2006.285.06:05:32.35#ibcon#enter sib2, iclass 14, count 0 2006.285.06:05:32.35#ibcon#flushed, iclass 14, count 0 2006.285.06:05:32.35#ibcon#about to write, iclass 14, count 0 2006.285.06:05:32.35#ibcon#wrote, iclass 14, count 0 2006.285.06:05:32.35#ibcon#about to read 3, iclass 14, count 0 2006.285.06:05:32.37#ibcon#read 3, iclass 14, count 0 2006.285.06:05:32.37#ibcon#about to read 4, iclass 14, count 0 2006.285.06:05:32.37#ibcon#read 4, iclass 14, count 0 2006.285.06:05:32.37#ibcon#about to read 5, iclass 14, count 0 2006.285.06:05:32.37#ibcon#read 5, iclass 14, count 0 2006.285.06:05:32.37#ibcon#about to read 6, iclass 14, count 0 2006.285.06:05:32.37#ibcon#read 6, iclass 14, count 0 2006.285.06:05:32.37#ibcon#end of sib2, iclass 14, count 0 2006.285.06:05:32.37#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:05:32.37#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:05:32.37#ibcon#[25=USB\r\n] 2006.285.06:05:32.37#ibcon#*before write, iclass 14, count 0 2006.285.06:05:32.37#ibcon#enter sib2, iclass 14, count 0 2006.285.06:05:32.37#ibcon#flushed, iclass 14, count 0 2006.285.06:05:32.37#ibcon#about to write, iclass 14, count 0 2006.285.06:05:32.37#ibcon#wrote, iclass 14, count 0 2006.285.06:05:32.37#ibcon#about to read 3, iclass 14, count 0 2006.285.06:05:32.40#ibcon#read 3, iclass 14, count 0 2006.285.06:05:32.40#ibcon#about to read 4, iclass 14, count 0 2006.285.06:05:32.40#ibcon#read 4, iclass 14, count 0 2006.285.06:05:32.40#ibcon#about to read 5, iclass 14, count 0 2006.285.06:05:32.40#ibcon#read 5, iclass 14, count 0 2006.285.06:05:32.40#ibcon#about to read 6, iclass 14, count 0 2006.285.06:05:32.40#ibcon#read 6, iclass 14, count 0 2006.285.06:05:32.40#ibcon#end of sib2, iclass 14, count 0 2006.285.06:05:32.40#ibcon#*after write, iclass 14, count 0 2006.285.06:05:32.40#ibcon#*before return 0, iclass 14, count 0 2006.285.06:05:32.40#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:05:32.40#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:05:32.40#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:05:32.40#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:05:32.40$vck44/valo=3,564.99 2006.285.06:05:32.40#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.06:05:32.40#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.06:05:32.40#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:32.40#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:05:32.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:05:32.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:05:32.40#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:05:32.40#ibcon#first serial, iclass 16, count 0 2006.285.06:05:32.40#ibcon#enter sib2, iclass 16, count 0 2006.285.06:05:32.40#ibcon#flushed, iclass 16, count 0 2006.285.06:05:32.40#ibcon#about to write, iclass 16, count 0 2006.285.06:05:32.40#ibcon#wrote, iclass 16, count 0 2006.285.06:05:32.40#ibcon#about to read 3, iclass 16, count 0 2006.285.06:05:32.42#ibcon#read 3, iclass 16, count 0 2006.285.06:05:32.42#ibcon#about to read 4, iclass 16, count 0 2006.285.06:05:32.42#ibcon#read 4, iclass 16, count 0 2006.285.06:05:32.42#ibcon#about to read 5, iclass 16, count 0 2006.285.06:05:32.42#ibcon#read 5, iclass 16, count 0 2006.285.06:05:32.42#ibcon#about to read 6, iclass 16, count 0 2006.285.06:05:32.42#ibcon#read 6, iclass 16, count 0 2006.285.06:05:32.42#ibcon#end of sib2, iclass 16, count 0 2006.285.06:05:32.42#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:05:32.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:05:32.42#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:05:32.42#ibcon#*before write, iclass 16, count 0 2006.285.06:05:32.42#ibcon#enter sib2, iclass 16, count 0 2006.285.06:05:32.42#ibcon#flushed, iclass 16, count 0 2006.285.06:05:32.42#ibcon#about to write, iclass 16, count 0 2006.285.06:05:32.42#ibcon#wrote, iclass 16, count 0 2006.285.06:05:32.42#ibcon#about to read 3, iclass 16, count 0 2006.285.06:05:32.46#ibcon#read 3, iclass 16, count 0 2006.285.06:05:32.46#ibcon#about to read 4, iclass 16, count 0 2006.285.06:05:32.46#ibcon#read 4, iclass 16, count 0 2006.285.06:05:32.46#ibcon#about to read 5, iclass 16, count 0 2006.285.06:05:32.46#ibcon#read 5, iclass 16, count 0 2006.285.06:05:32.46#ibcon#about to read 6, iclass 16, count 0 2006.285.06:05:32.46#ibcon#read 6, iclass 16, count 0 2006.285.06:05:32.46#ibcon#end of sib2, iclass 16, count 0 2006.285.06:05:32.46#ibcon#*after write, iclass 16, count 0 2006.285.06:05:32.46#ibcon#*before return 0, iclass 16, count 0 2006.285.06:05:32.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:05:32.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:05:32.46#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:05:32.46#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:05:32.46$vck44/va=3,7 2006.285.06:05:32.46#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.06:05:32.46#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.06:05:32.46#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:32.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:05:32.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:05:32.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:05:32.52#ibcon#enter wrdev, iclass 18, count 2 2006.285.06:05:32.52#ibcon#first serial, iclass 18, count 2 2006.285.06:05:32.52#ibcon#enter sib2, iclass 18, count 2 2006.285.06:05:32.52#ibcon#flushed, iclass 18, count 2 2006.285.06:05:32.52#ibcon#about to write, iclass 18, count 2 2006.285.06:05:32.52#ibcon#wrote, iclass 18, count 2 2006.285.06:05:32.52#ibcon#about to read 3, iclass 18, count 2 2006.285.06:05:32.54#ibcon#read 3, iclass 18, count 2 2006.285.06:05:32.54#ibcon#about to read 4, iclass 18, count 2 2006.285.06:05:32.54#ibcon#read 4, iclass 18, count 2 2006.285.06:05:32.54#ibcon#about to read 5, iclass 18, count 2 2006.285.06:05:32.54#ibcon#read 5, iclass 18, count 2 2006.285.06:05:32.54#ibcon#about to read 6, iclass 18, count 2 2006.285.06:05:32.54#ibcon#read 6, iclass 18, count 2 2006.285.06:05:32.54#ibcon#end of sib2, iclass 18, count 2 2006.285.06:05:32.54#ibcon#*mode == 0, iclass 18, count 2 2006.285.06:05:32.54#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.06:05:32.54#ibcon#[25=AT03-07\r\n] 2006.285.06:05:32.54#ibcon#*before write, iclass 18, count 2 2006.285.06:05:32.54#ibcon#enter sib2, iclass 18, count 2 2006.285.06:05:32.54#ibcon#flushed, iclass 18, count 2 2006.285.06:05:32.54#ibcon#about to write, iclass 18, count 2 2006.285.06:05:32.54#ibcon#wrote, iclass 18, count 2 2006.285.06:05:32.54#ibcon#about to read 3, iclass 18, count 2 2006.285.06:05:32.57#ibcon#read 3, iclass 18, count 2 2006.285.06:05:32.57#ibcon#about to read 4, iclass 18, count 2 2006.285.06:05:32.57#ibcon#read 4, iclass 18, count 2 2006.285.06:05:32.57#ibcon#about to read 5, iclass 18, count 2 2006.285.06:05:32.57#ibcon#read 5, iclass 18, count 2 2006.285.06:05:32.57#ibcon#about to read 6, iclass 18, count 2 2006.285.06:05:32.57#ibcon#read 6, iclass 18, count 2 2006.285.06:05:32.57#ibcon#end of sib2, iclass 18, count 2 2006.285.06:05:32.57#ibcon#*after write, iclass 18, count 2 2006.285.06:05:32.57#ibcon#*before return 0, iclass 18, count 2 2006.285.06:05:32.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:05:32.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:05:32.57#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.06:05:32.57#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:32.57#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:05:32.69#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:05:32.69#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:05:32.69#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:05:32.69#ibcon#first serial, iclass 18, count 0 2006.285.06:05:32.69#ibcon#enter sib2, iclass 18, count 0 2006.285.06:05:32.69#ibcon#flushed, iclass 18, count 0 2006.285.06:05:32.69#ibcon#about to write, iclass 18, count 0 2006.285.06:05:32.69#ibcon#wrote, iclass 18, count 0 2006.285.06:05:32.69#ibcon#about to read 3, iclass 18, count 0 2006.285.06:05:32.71#ibcon#read 3, iclass 18, count 0 2006.285.06:05:32.71#ibcon#about to read 4, iclass 18, count 0 2006.285.06:05:32.71#ibcon#read 4, iclass 18, count 0 2006.285.06:05:32.71#ibcon#about to read 5, iclass 18, count 0 2006.285.06:05:32.71#ibcon#read 5, iclass 18, count 0 2006.285.06:05:32.71#ibcon#about to read 6, iclass 18, count 0 2006.285.06:05:32.71#ibcon#read 6, iclass 18, count 0 2006.285.06:05:32.71#ibcon#end of sib2, iclass 18, count 0 2006.285.06:05:32.71#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:05:32.71#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:05:32.71#ibcon#[25=USB\r\n] 2006.285.06:05:32.71#ibcon#*before write, iclass 18, count 0 2006.285.06:05:32.71#ibcon#enter sib2, iclass 18, count 0 2006.285.06:05:32.71#ibcon#flushed, iclass 18, count 0 2006.285.06:05:32.71#ibcon#about to write, iclass 18, count 0 2006.285.06:05:32.71#ibcon#wrote, iclass 18, count 0 2006.285.06:05:32.71#ibcon#about to read 3, iclass 18, count 0 2006.285.06:05:32.74#ibcon#read 3, iclass 18, count 0 2006.285.06:05:32.74#ibcon#about to read 4, iclass 18, count 0 2006.285.06:05:32.74#ibcon#read 4, iclass 18, count 0 2006.285.06:05:32.74#ibcon#about to read 5, iclass 18, count 0 2006.285.06:05:32.74#ibcon#read 5, iclass 18, count 0 2006.285.06:05:32.74#ibcon#about to read 6, iclass 18, count 0 2006.285.06:05:32.74#ibcon#read 6, iclass 18, count 0 2006.285.06:05:32.74#ibcon#end of sib2, iclass 18, count 0 2006.285.06:05:32.74#ibcon#*after write, iclass 18, count 0 2006.285.06:05:32.74#ibcon#*before return 0, iclass 18, count 0 2006.285.06:05:32.74#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:05:32.74#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:05:32.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:05:32.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:05:32.74$vck44/valo=4,624.99 2006.285.06:05:32.74#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.06:05:32.74#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.06:05:32.74#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:32.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:05:32.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:05:32.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:05:32.74#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:05:32.74#ibcon#first serial, iclass 20, count 0 2006.285.06:05:32.74#ibcon#enter sib2, iclass 20, count 0 2006.285.06:05:32.74#ibcon#flushed, iclass 20, count 0 2006.285.06:05:32.74#ibcon#about to write, iclass 20, count 0 2006.285.06:05:32.74#ibcon#wrote, iclass 20, count 0 2006.285.06:05:32.74#ibcon#about to read 3, iclass 20, count 0 2006.285.06:05:32.76#ibcon#read 3, iclass 20, count 0 2006.285.06:05:32.76#ibcon#about to read 4, iclass 20, count 0 2006.285.06:05:32.76#ibcon#read 4, iclass 20, count 0 2006.285.06:05:32.76#ibcon#about to read 5, iclass 20, count 0 2006.285.06:05:32.76#ibcon#read 5, iclass 20, count 0 2006.285.06:05:32.76#ibcon#about to read 6, iclass 20, count 0 2006.285.06:05:32.76#ibcon#read 6, iclass 20, count 0 2006.285.06:05:32.76#ibcon#end of sib2, iclass 20, count 0 2006.285.06:05:32.76#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:05:32.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:05:32.76#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:05:32.76#ibcon#*before write, iclass 20, count 0 2006.285.06:05:32.76#ibcon#enter sib2, iclass 20, count 0 2006.285.06:05:32.76#ibcon#flushed, iclass 20, count 0 2006.285.06:05:32.76#ibcon#about to write, iclass 20, count 0 2006.285.06:05:32.76#ibcon#wrote, iclass 20, count 0 2006.285.06:05:32.76#ibcon#about to read 3, iclass 20, count 0 2006.285.06:05:32.80#ibcon#read 3, iclass 20, count 0 2006.285.06:05:32.80#ibcon#about to read 4, iclass 20, count 0 2006.285.06:05:32.80#ibcon#read 4, iclass 20, count 0 2006.285.06:05:32.80#ibcon#about to read 5, iclass 20, count 0 2006.285.06:05:32.80#ibcon#read 5, iclass 20, count 0 2006.285.06:05:32.80#ibcon#about to read 6, iclass 20, count 0 2006.285.06:05:32.80#ibcon#read 6, iclass 20, count 0 2006.285.06:05:32.80#ibcon#end of sib2, iclass 20, count 0 2006.285.06:05:32.80#ibcon#*after write, iclass 20, count 0 2006.285.06:05:32.80#ibcon#*before return 0, iclass 20, count 0 2006.285.06:05:32.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:05:32.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:05:32.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:05:32.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:05:32.80$vck44/va=4,6 2006.285.06:05:32.80#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.06:05:32.80#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.06:05:32.80#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:32.80#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:05:32.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:05:32.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:05:32.86#ibcon#enter wrdev, iclass 22, count 2 2006.285.06:05:32.86#ibcon#first serial, iclass 22, count 2 2006.285.06:05:32.86#ibcon#enter sib2, iclass 22, count 2 2006.285.06:05:32.86#ibcon#flushed, iclass 22, count 2 2006.285.06:05:32.86#ibcon#about to write, iclass 22, count 2 2006.285.06:05:32.86#ibcon#wrote, iclass 22, count 2 2006.285.06:05:32.86#ibcon#about to read 3, iclass 22, count 2 2006.285.06:05:32.88#ibcon#read 3, iclass 22, count 2 2006.285.06:05:32.88#ibcon#about to read 4, iclass 22, count 2 2006.285.06:05:32.88#ibcon#read 4, iclass 22, count 2 2006.285.06:05:32.88#ibcon#about to read 5, iclass 22, count 2 2006.285.06:05:32.88#ibcon#read 5, iclass 22, count 2 2006.285.06:05:32.88#ibcon#about to read 6, iclass 22, count 2 2006.285.06:05:32.88#ibcon#read 6, iclass 22, count 2 2006.285.06:05:32.88#ibcon#end of sib2, iclass 22, count 2 2006.285.06:05:32.88#ibcon#*mode == 0, iclass 22, count 2 2006.285.06:05:32.88#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.06:05:32.88#ibcon#[25=AT04-06\r\n] 2006.285.06:05:32.88#ibcon#*before write, iclass 22, count 2 2006.285.06:05:32.88#ibcon#enter sib2, iclass 22, count 2 2006.285.06:05:32.88#ibcon#flushed, iclass 22, count 2 2006.285.06:05:32.88#ibcon#about to write, iclass 22, count 2 2006.285.06:05:32.88#ibcon#wrote, iclass 22, count 2 2006.285.06:05:32.88#ibcon#about to read 3, iclass 22, count 2 2006.285.06:05:32.91#ibcon#read 3, iclass 22, count 2 2006.285.06:05:32.91#ibcon#about to read 4, iclass 22, count 2 2006.285.06:05:32.91#ibcon#read 4, iclass 22, count 2 2006.285.06:05:32.91#ibcon#about to read 5, iclass 22, count 2 2006.285.06:05:32.91#ibcon#read 5, iclass 22, count 2 2006.285.06:05:32.91#ibcon#about to read 6, iclass 22, count 2 2006.285.06:05:32.91#ibcon#read 6, iclass 22, count 2 2006.285.06:05:32.91#ibcon#end of sib2, iclass 22, count 2 2006.285.06:05:32.91#ibcon#*after write, iclass 22, count 2 2006.285.06:05:32.91#ibcon#*before return 0, iclass 22, count 2 2006.285.06:05:32.91#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:05:32.91#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:05:32.91#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.06:05:32.91#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:32.91#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:05:33.03#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:05:33.03#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:05:33.03#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:05:33.03#ibcon#first serial, iclass 22, count 0 2006.285.06:05:33.03#ibcon#enter sib2, iclass 22, count 0 2006.285.06:05:33.03#ibcon#flushed, iclass 22, count 0 2006.285.06:05:33.03#ibcon#about to write, iclass 22, count 0 2006.285.06:05:33.03#ibcon#wrote, iclass 22, count 0 2006.285.06:05:33.03#ibcon#about to read 3, iclass 22, count 0 2006.285.06:05:33.05#ibcon#read 3, iclass 22, count 0 2006.285.06:05:33.05#ibcon#about to read 4, iclass 22, count 0 2006.285.06:05:33.05#ibcon#read 4, iclass 22, count 0 2006.285.06:05:33.05#ibcon#about to read 5, iclass 22, count 0 2006.285.06:05:33.05#ibcon#read 5, iclass 22, count 0 2006.285.06:05:33.05#ibcon#about to read 6, iclass 22, count 0 2006.285.06:05:33.05#ibcon#read 6, iclass 22, count 0 2006.285.06:05:33.05#ibcon#end of sib2, iclass 22, count 0 2006.285.06:05:33.05#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:05:33.05#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:05:33.05#ibcon#[25=USB\r\n] 2006.285.06:05:33.05#ibcon#*before write, iclass 22, count 0 2006.285.06:05:33.05#ibcon#enter sib2, iclass 22, count 0 2006.285.06:05:33.05#ibcon#flushed, iclass 22, count 0 2006.285.06:05:33.05#ibcon#about to write, iclass 22, count 0 2006.285.06:05:33.05#ibcon#wrote, iclass 22, count 0 2006.285.06:05:33.05#ibcon#about to read 3, iclass 22, count 0 2006.285.06:05:33.08#ibcon#read 3, iclass 22, count 0 2006.285.06:05:33.08#ibcon#about to read 4, iclass 22, count 0 2006.285.06:05:33.08#ibcon#read 4, iclass 22, count 0 2006.285.06:05:33.08#ibcon#about to read 5, iclass 22, count 0 2006.285.06:05:33.08#ibcon#read 5, iclass 22, count 0 2006.285.06:05:33.08#ibcon#about to read 6, iclass 22, count 0 2006.285.06:05:33.08#ibcon#read 6, iclass 22, count 0 2006.285.06:05:33.08#ibcon#end of sib2, iclass 22, count 0 2006.285.06:05:33.08#ibcon#*after write, iclass 22, count 0 2006.285.06:05:33.08#ibcon#*before return 0, iclass 22, count 0 2006.285.06:05:33.08#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:05:33.08#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:05:33.08#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:05:33.08#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:05:33.08$vck44/valo=5,734.99 2006.285.06:05:33.08#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.06:05:33.08#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.06:05:33.08#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:33.08#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:05:33.08#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:05:33.08#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:05:33.08#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:05:33.08#ibcon#first serial, iclass 24, count 0 2006.285.06:05:33.08#ibcon#enter sib2, iclass 24, count 0 2006.285.06:05:33.08#ibcon#flushed, iclass 24, count 0 2006.285.06:05:33.08#ibcon#about to write, iclass 24, count 0 2006.285.06:05:33.08#ibcon#wrote, iclass 24, count 0 2006.285.06:05:33.08#ibcon#about to read 3, iclass 24, count 0 2006.285.06:05:33.10#ibcon#read 3, iclass 24, count 0 2006.285.06:05:33.10#ibcon#about to read 4, iclass 24, count 0 2006.285.06:05:33.10#ibcon#read 4, iclass 24, count 0 2006.285.06:05:33.10#ibcon#about to read 5, iclass 24, count 0 2006.285.06:05:33.10#ibcon#read 5, iclass 24, count 0 2006.285.06:05:33.10#ibcon#about to read 6, iclass 24, count 0 2006.285.06:05:33.10#ibcon#read 6, iclass 24, count 0 2006.285.06:05:33.10#ibcon#end of sib2, iclass 24, count 0 2006.285.06:05:33.10#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:05:33.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:05:33.10#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:05:33.10#ibcon#*before write, iclass 24, count 0 2006.285.06:05:33.10#ibcon#enter sib2, iclass 24, count 0 2006.285.06:05:33.10#ibcon#flushed, iclass 24, count 0 2006.285.06:05:33.10#ibcon#about to write, iclass 24, count 0 2006.285.06:05:33.10#ibcon#wrote, iclass 24, count 0 2006.285.06:05:33.10#ibcon#about to read 3, iclass 24, count 0 2006.285.06:05:33.14#ibcon#read 3, iclass 24, count 0 2006.285.06:05:33.14#ibcon#about to read 4, iclass 24, count 0 2006.285.06:05:33.14#ibcon#read 4, iclass 24, count 0 2006.285.06:05:33.14#ibcon#about to read 5, iclass 24, count 0 2006.285.06:05:33.14#ibcon#read 5, iclass 24, count 0 2006.285.06:05:33.14#ibcon#about to read 6, iclass 24, count 0 2006.285.06:05:33.14#ibcon#read 6, iclass 24, count 0 2006.285.06:05:33.14#ibcon#end of sib2, iclass 24, count 0 2006.285.06:05:33.14#ibcon#*after write, iclass 24, count 0 2006.285.06:05:33.14#ibcon#*before return 0, iclass 24, count 0 2006.285.06:05:33.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:05:33.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:05:33.14#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:05:33.14#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:05:33.14$vck44/va=5,3 2006.285.06:05:33.14#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.06:05:33.14#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.06:05:33.14#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:33.14#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:05:33.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:05:33.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:05:33.21#ibcon#enter wrdev, iclass 26, count 2 2006.285.06:05:33.21#ibcon#first serial, iclass 26, count 2 2006.285.06:05:33.21#ibcon#enter sib2, iclass 26, count 2 2006.285.06:05:33.21#ibcon#flushed, iclass 26, count 2 2006.285.06:05:33.21#ibcon#about to write, iclass 26, count 2 2006.285.06:05:33.21#ibcon#wrote, iclass 26, count 2 2006.285.06:05:33.21#ibcon#about to read 3, iclass 26, count 2 2006.285.06:05:33.22#ibcon#read 3, iclass 26, count 2 2006.285.06:05:33.22#ibcon#about to read 4, iclass 26, count 2 2006.285.06:05:33.22#ibcon#read 4, iclass 26, count 2 2006.285.06:05:33.22#ibcon#about to read 5, iclass 26, count 2 2006.285.06:05:33.22#ibcon#read 5, iclass 26, count 2 2006.285.06:05:33.22#ibcon#about to read 6, iclass 26, count 2 2006.285.06:05:33.22#ibcon#read 6, iclass 26, count 2 2006.285.06:05:33.22#ibcon#end of sib2, iclass 26, count 2 2006.285.06:05:33.22#ibcon#*mode == 0, iclass 26, count 2 2006.285.06:05:33.22#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.06:05:33.22#ibcon#[25=AT05-03\r\n] 2006.285.06:05:33.22#ibcon#*before write, iclass 26, count 2 2006.285.06:05:33.22#ibcon#enter sib2, iclass 26, count 2 2006.285.06:05:33.22#ibcon#flushed, iclass 26, count 2 2006.285.06:05:33.22#ibcon#about to write, iclass 26, count 2 2006.285.06:05:33.22#ibcon#wrote, iclass 26, count 2 2006.285.06:05:33.22#ibcon#about to read 3, iclass 26, count 2 2006.285.06:05:33.25#ibcon#read 3, iclass 26, count 2 2006.285.06:05:33.25#ibcon#about to read 4, iclass 26, count 2 2006.285.06:05:33.25#ibcon#read 4, iclass 26, count 2 2006.285.06:05:33.25#ibcon#about to read 5, iclass 26, count 2 2006.285.06:05:33.25#ibcon#read 5, iclass 26, count 2 2006.285.06:05:33.25#ibcon#about to read 6, iclass 26, count 2 2006.285.06:05:33.25#ibcon#read 6, iclass 26, count 2 2006.285.06:05:33.25#ibcon#end of sib2, iclass 26, count 2 2006.285.06:05:33.25#ibcon#*after write, iclass 26, count 2 2006.285.06:05:33.25#ibcon#*before return 0, iclass 26, count 2 2006.285.06:05:33.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:05:33.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:05:33.25#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.06:05:33.25#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:33.25#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:05:33.37#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:05:33.37#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:05:33.37#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:05:33.37#ibcon#first serial, iclass 26, count 0 2006.285.06:05:33.37#ibcon#enter sib2, iclass 26, count 0 2006.285.06:05:33.37#ibcon#flushed, iclass 26, count 0 2006.285.06:05:33.37#ibcon#about to write, iclass 26, count 0 2006.285.06:05:33.37#ibcon#wrote, iclass 26, count 0 2006.285.06:05:33.37#ibcon#about to read 3, iclass 26, count 0 2006.285.06:05:33.39#ibcon#read 3, iclass 26, count 0 2006.285.06:05:33.39#ibcon#about to read 4, iclass 26, count 0 2006.285.06:05:33.39#ibcon#read 4, iclass 26, count 0 2006.285.06:05:33.39#ibcon#about to read 5, iclass 26, count 0 2006.285.06:05:33.39#ibcon#read 5, iclass 26, count 0 2006.285.06:05:33.39#ibcon#about to read 6, iclass 26, count 0 2006.285.06:05:33.39#ibcon#read 6, iclass 26, count 0 2006.285.06:05:33.39#ibcon#end of sib2, iclass 26, count 0 2006.285.06:05:33.39#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:05:33.39#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:05:33.39#ibcon#[25=USB\r\n] 2006.285.06:05:33.39#ibcon#*before write, iclass 26, count 0 2006.285.06:05:33.39#ibcon#enter sib2, iclass 26, count 0 2006.285.06:05:33.39#ibcon#flushed, iclass 26, count 0 2006.285.06:05:33.39#ibcon#about to write, iclass 26, count 0 2006.285.06:05:33.39#ibcon#wrote, iclass 26, count 0 2006.285.06:05:33.39#ibcon#about to read 3, iclass 26, count 0 2006.285.06:05:33.42#ibcon#read 3, iclass 26, count 0 2006.285.06:05:33.42#ibcon#about to read 4, iclass 26, count 0 2006.285.06:05:33.42#ibcon#read 4, iclass 26, count 0 2006.285.06:05:33.42#ibcon#about to read 5, iclass 26, count 0 2006.285.06:05:33.42#ibcon#read 5, iclass 26, count 0 2006.285.06:05:33.42#ibcon#about to read 6, iclass 26, count 0 2006.285.06:05:33.42#ibcon#read 6, iclass 26, count 0 2006.285.06:05:33.42#ibcon#end of sib2, iclass 26, count 0 2006.285.06:05:33.42#ibcon#*after write, iclass 26, count 0 2006.285.06:05:33.42#ibcon#*before return 0, iclass 26, count 0 2006.285.06:05:33.42#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:05:33.42#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:05:33.42#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:05:33.42#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:05:33.42$vck44/valo=6,814.99 2006.285.06:05:33.42#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.06:05:33.42#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.06:05:33.42#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:33.42#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:05:33.42#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:05:33.42#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:05:33.42#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:05:33.42#ibcon#first serial, iclass 28, count 0 2006.285.06:05:33.42#ibcon#enter sib2, iclass 28, count 0 2006.285.06:05:33.42#ibcon#flushed, iclass 28, count 0 2006.285.06:05:33.42#ibcon#about to write, iclass 28, count 0 2006.285.06:05:33.42#ibcon#wrote, iclass 28, count 0 2006.285.06:05:33.42#ibcon#about to read 3, iclass 28, count 0 2006.285.06:05:33.44#ibcon#read 3, iclass 28, count 0 2006.285.06:05:33.44#ibcon#about to read 4, iclass 28, count 0 2006.285.06:05:33.44#ibcon#read 4, iclass 28, count 0 2006.285.06:05:33.44#ibcon#about to read 5, iclass 28, count 0 2006.285.06:05:33.44#ibcon#read 5, iclass 28, count 0 2006.285.06:05:33.44#ibcon#about to read 6, iclass 28, count 0 2006.285.06:05:33.44#ibcon#read 6, iclass 28, count 0 2006.285.06:05:33.44#ibcon#end of sib2, iclass 28, count 0 2006.285.06:05:33.44#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:05:33.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:05:33.44#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:05:33.44#ibcon#*before write, iclass 28, count 0 2006.285.06:05:33.44#ibcon#enter sib2, iclass 28, count 0 2006.285.06:05:33.44#ibcon#flushed, iclass 28, count 0 2006.285.06:05:33.44#ibcon#about to write, iclass 28, count 0 2006.285.06:05:33.44#ibcon#wrote, iclass 28, count 0 2006.285.06:05:33.44#ibcon#about to read 3, iclass 28, count 0 2006.285.06:05:33.48#ibcon#read 3, iclass 28, count 0 2006.285.06:05:33.48#ibcon#about to read 4, iclass 28, count 0 2006.285.06:05:33.48#ibcon#read 4, iclass 28, count 0 2006.285.06:05:33.48#ibcon#about to read 5, iclass 28, count 0 2006.285.06:05:33.48#ibcon#read 5, iclass 28, count 0 2006.285.06:05:33.48#ibcon#about to read 6, iclass 28, count 0 2006.285.06:05:33.48#ibcon#read 6, iclass 28, count 0 2006.285.06:05:33.48#ibcon#end of sib2, iclass 28, count 0 2006.285.06:05:33.48#ibcon#*after write, iclass 28, count 0 2006.285.06:05:33.48#ibcon#*before return 0, iclass 28, count 0 2006.285.06:05:33.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:05:33.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:05:33.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:05:33.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:05:33.48$vck44/va=6,4 2006.285.06:05:33.48#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.06:05:33.48#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.06:05:33.48#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:33.48#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:05:33.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:05:33.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:05:33.54#ibcon#enter wrdev, iclass 30, count 2 2006.285.06:05:33.54#ibcon#first serial, iclass 30, count 2 2006.285.06:05:33.54#ibcon#enter sib2, iclass 30, count 2 2006.285.06:05:33.54#ibcon#flushed, iclass 30, count 2 2006.285.06:05:33.54#ibcon#about to write, iclass 30, count 2 2006.285.06:05:33.54#ibcon#wrote, iclass 30, count 2 2006.285.06:05:33.54#ibcon#about to read 3, iclass 30, count 2 2006.285.06:05:33.56#ibcon#read 3, iclass 30, count 2 2006.285.06:05:33.56#ibcon#about to read 4, iclass 30, count 2 2006.285.06:05:33.56#ibcon#read 4, iclass 30, count 2 2006.285.06:05:33.56#ibcon#about to read 5, iclass 30, count 2 2006.285.06:05:33.56#ibcon#read 5, iclass 30, count 2 2006.285.06:05:33.56#ibcon#about to read 6, iclass 30, count 2 2006.285.06:05:33.56#ibcon#read 6, iclass 30, count 2 2006.285.06:05:33.56#ibcon#end of sib2, iclass 30, count 2 2006.285.06:05:33.56#ibcon#*mode == 0, iclass 30, count 2 2006.285.06:05:33.56#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.06:05:33.56#ibcon#[25=AT06-04\r\n] 2006.285.06:05:33.56#ibcon#*before write, iclass 30, count 2 2006.285.06:05:33.56#ibcon#enter sib2, iclass 30, count 2 2006.285.06:05:33.56#ibcon#flushed, iclass 30, count 2 2006.285.06:05:33.56#ibcon#about to write, iclass 30, count 2 2006.285.06:05:33.56#ibcon#wrote, iclass 30, count 2 2006.285.06:05:33.56#ibcon#about to read 3, iclass 30, count 2 2006.285.06:05:33.59#ibcon#read 3, iclass 30, count 2 2006.285.06:05:33.59#ibcon#about to read 4, iclass 30, count 2 2006.285.06:05:33.59#ibcon#read 4, iclass 30, count 2 2006.285.06:05:33.59#ibcon#about to read 5, iclass 30, count 2 2006.285.06:05:33.59#ibcon#read 5, iclass 30, count 2 2006.285.06:05:33.59#ibcon#about to read 6, iclass 30, count 2 2006.285.06:05:33.59#ibcon#read 6, iclass 30, count 2 2006.285.06:05:33.59#ibcon#end of sib2, iclass 30, count 2 2006.285.06:05:33.59#ibcon#*after write, iclass 30, count 2 2006.285.06:05:33.59#ibcon#*before return 0, iclass 30, count 2 2006.285.06:05:33.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:05:33.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:05:33.59#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.06:05:33.59#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:33.59#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:05:33.71#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:05:33.71#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:05:33.71#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:05:33.71#ibcon#first serial, iclass 30, count 0 2006.285.06:05:33.71#ibcon#enter sib2, iclass 30, count 0 2006.285.06:05:33.71#ibcon#flushed, iclass 30, count 0 2006.285.06:05:33.71#ibcon#about to write, iclass 30, count 0 2006.285.06:05:33.71#ibcon#wrote, iclass 30, count 0 2006.285.06:05:33.71#ibcon#about to read 3, iclass 30, count 0 2006.285.06:05:33.73#ibcon#read 3, iclass 30, count 0 2006.285.06:05:33.73#ibcon#about to read 4, iclass 30, count 0 2006.285.06:05:33.73#ibcon#read 4, iclass 30, count 0 2006.285.06:05:33.73#ibcon#about to read 5, iclass 30, count 0 2006.285.06:05:33.73#ibcon#read 5, iclass 30, count 0 2006.285.06:05:33.73#ibcon#about to read 6, iclass 30, count 0 2006.285.06:05:33.73#ibcon#read 6, iclass 30, count 0 2006.285.06:05:33.73#ibcon#end of sib2, iclass 30, count 0 2006.285.06:05:33.73#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:05:33.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:05:33.73#ibcon#[25=USB\r\n] 2006.285.06:05:33.73#ibcon#*before write, iclass 30, count 0 2006.285.06:05:33.73#ibcon#enter sib2, iclass 30, count 0 2006.285.06:05:33.73#ibcon#flushed, iclass 30, count 0 2006.285.06:05:33.73#ibcon#about to write, iclass 30, count 0 2006.285.06:05:33.73#ibcon#wrote, iclass 30, count 0 2006.285.06:05:33.73#ibcon#about to read 3, iclass 30, count 0 2006.285.06:05:33.76#ibcon#read 3, iclass 30, count 0 2006.285.06:05:33.76#ibcon#about to read 4, iclass 30, count 0 2006.285.06:05:33.76#ibcon#read 4, iclass 30, count 0 2006.285.06:05:33.76#ibcon#about to read 5, iclass 30, count 0 2006.285.06:05:33.76#ibcon#read 5, iclass 30, count 0 2006.285.06:05:33.76#ibcon#about to read 6, iclass 30, count 0 2006.285.06:05:33.76#ibcon#read 6, iclass 30, count 0 2006.285.06:05:33.76#ibcon#end of sib2, iclass 30, count 0 2006.285.06:05:33.76#ibcon#*after write, iclass 30, count 0 2006.285.06:05:33.76#ibcon#*before return 0, iclass 30, count 0 2006.285.06:05:33.76#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:05:33.76#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:05:33.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:05:33.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:05:33.76$vck44/valo=7,864.99 2006.285.06:05:33.76#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.06:05:33.76#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.06:05:33.76#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:33.76#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:05:33.76#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:05:33.76#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:05:33.76#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:05:33.76#ibcon#first serial, iclass 32, count 0 2006.285.06:05:33.76#ibcon#enter sib2, iclass 32, count 0 2006.285.06:05:33.76#ibcon#flushed, iclass 32, count 0 2006.285.06:05:33.76#ibcon#about to write, iclass 32, count 0 2006.285.06:05:33.76#ibcon#wrote, iclass 32, count 0 2006.285.06:05:33.76#ibcon#about to read 3, iclass 32, count 0 2006.285.06:05:33.78#ibcon#read 3, iclass 32, count 0 2006.285.06:05:33.78#ibcon#about to read 4, iclass 32, count 0 2006.285.06:05:33.78#ibcon#read 4, iclass 32, count 0 2006.285.06:05:33.78#ibcon#about to read 5, iclass 32, count 0 2006.285.06:05:33.78#ibcon#read 5, iclass 32, count 0 2006.285.06:05:33.78#ibcon#about to read 6, iclass 32, count 0 2006.285.06:05:33.78#ibcon#read 6, iclass 32, count 0 2006.285.06:05:33.78#ibcon#end of sib2, iclass 32, count 0 2006.285.06:05:33.78#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:05:33.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:05:33.78#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:05:33.78#ibcon#*before write, iclass 32, count 0 2006.285.06:05:33.78#ibcon#enter sib2, iclass 32, count 0 2006.285.06:05:33.78#ibcon#flushed, iclass 32, count 0 2006.285.06:05:33.78#ibcon#about to write, iclass 32, count 0 2006.285.06:05:33.78#ibcon#wrote, iclass 32, count 0 2006.285.06:05:33.78#ibcon#about to read 3, iclass 32, count 0 2006.285.06:05:33.82#ibcon#read 3, iclass 32, count 0 2006.285.06:05:33.82#ibcon#about to read 4, iclass 32, count 0 2006.285.06:05:33.82#ibcon#read 4, iclass 32, count 0 2006.285.06:05:33.82#ibcon#about to read 5, iclass 32, count 0 2006.285.06:05:33.82#ibcon#read 5, iclass 32, count 0 2006.285.06:05:33.82#ibcon#about to read 6, iclass 32, count 0 2006.285.06:05:33.82#ibcon#read 6, iclass 32, count 0 2006.285.06:05:33.82#ibcon#end of sib2, iclass 32, count 0 2006.285.06:05:33.82#ibcon#*after write, iclass 32, count 0 2006.285.06:05:33.82#ibcon#*before return 0, iclass 32, count 0 2006.285.06:05:33.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:05:33.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:05:33.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:05:33.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:05:33.82$vck44/va=7,4 2006.285.06:05:33.82#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.06:05:33.82#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.06:05:33.82#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:33.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:05:33.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:05:33.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:05:33.88#ibcon#enter wrdev, iclass 34, count 2 2006.285.06:05:33.88#ibcon#first serial, iclass 34, count 2 2006.285.06:05:33.88#ibcon#enter sib2, iclass 34, count 2 2006.285.06:05:33.88#ibcon#flushed, iclass 34, count 2 2006.285.06:05:33.88#ibcon#about to write, iclass 34, count 2 2006.285.06:05:33.88#ibcon#wrote, iclass 34, count 2 2006.285.06:05:33.88#ibcon#about to read 3, iclass 34, count 2 2006.285.06:05:33.90#ibcon#read 3, iclass 34, count 2 2006.285.06:05:33.90#ibcon#about to read 4, iclass 34, count 2 2006.285.06:05:33.90#ibcon#read 4, iclass 34, count 2 2006.285.06:05:33.90#ibcon#about to read 5, iclass 34, count 2 2006.285.06:05:33.90#ibcon#read 5, iclass 34, count 2 2006.285.06:05:33.90#ibcon#about to read 6, iclass 34, count 2 2006.285.06:05:33.90#ibcon#read 6, iclass 34, count 2 2006.285.06:05:33.90#ibcon#end of sib2, iclass 34, count 2 2006.285.06:05:33.90#ibcon#*mode == 0, iclass 34, count 2 2006.285.06:05:33.90#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.06:05:33.90#ibcon#[25=AT07-04\r\n] 2006.285.06:05:33.90#ibcon#*before write, iclass 34, count 2 2006.285.06:05:33.90#ibcon#enter sib2, iclass 34, count 2 2006.285.06:05:33.90#ibcon#flushed, iclass 34, count 2 2006.285.06:05:33.90#ibcon#about to write, iclass 34, count 2 2006.285.06:05:33.90#ibcon#wrote, iclass 34, count 2 2006.285.06:05:33.90#ibcon#about to read 3, iclass 34, count 2 2006.285.06:05:33.93#ibcon#read 3, iclass 34, count 2 2006.285.06:05:33.93#ibcon#about to read 4, iclass 34, count 2 2006.285.06:05:33.93#ibcon#read 4, iclass 34, count 2 2006.285.06:05:33.93#ibcon#about to read 5, iclass 34, count 2 2006.285.06:05:33.93#ibcon#read 5, iclass 34, count 2 2006.285.06:05:33.93#ibcon#about to read 6, iclass 34, count 2 2006.285.06:05:33.93#ibcon#read 6, iclass 34, count 2 2006.285.06:05:33.93#ibcon#end of sib2, iclass 34, count 2 2006.285.06:05:33.93#ibcon#*after write, iclass 34, count 2 2006.285.06:05:33.93#ibcon#*before return 0, iclass 34, count 2 2006.285.06:05:33.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:05:33.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:05:33.93#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.06:05:33.93#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:33.93#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:05:34.05#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:05:34.05#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:05:34.05#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:05:34.05#ibcon#first serial, iclass 34, count 0 2006.285.06:05:34.05#ibcon#enter sib2, iclass 34, count 0 2006.285.06:05:34.05#ibcon#flushed, iclass 34, count 0 2006.285.06:05:34.05#ibcon#about to write, iclass 34, count 0 2006.285.06:05:34.05#ibcon#wrote, iclass 34, count 0 2006.285.06:05:34.05#ibcon#about to read 3, iclass 34, count 0 2006.285.06:05:34.07#ibcon#read 3, iclass 34, count 0 2006.285.06:05:34.07#ibcon#about to read 4, iclass 34, count 0 2006.285.06:05:34.07#ibcon#read 4, iclass 34, count 0 2006.285.06:05:34.07#ibcon#about to read 5, iclass 34, count 0 2006.285.06:05:34.07#ibcon#read 5, iclass 34, count 0 2006.285.06:05:34.07#ibcon#about to read 6, iclass 34, count 0 2006.285.06:05:34.07#ibcon#read 6, iclass 34, count 0 2006.285.06:05:34.07#ibcon#end of sib2, iclass 34, count 0 2006.285.06:05:34.07#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:05:34.07#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:05:34.07#ibcon#[25=USB\r\n] 2006.285.06:05:34.07#ibcon#*before write, iclass 34, count 0 2006.285.06:05:34.07#ibcon#enter sib2, iclass 34, count 0 2006.285.06:05:34.07#ibcon#flushed, iclass 34, count 0 2006.285.06:05:34.07#ibcon#about to write, iclass 34, count 0 2006.285.06:05:34.07#ibcon#wrote, iclass 34, count 0 2006.285.06:05:34.07#ibcon#about to read 3, iclass 34, count 0 2006.285.06:05:34.10#ibcon#read 3, iclass 34, count 0 2006.285.06:05:34.10#ibcon#about to read 4, iclass 34, count 0 2006.285.06:05:34.10#ibcon#read 4, iclass 34, count 0 2006.285.06:05:34.10#ibcon#about to read 5, iclass 34, count 0 2006.285.06:05:34.10#ibcon#read 5, iclass 34, count 0 2006.285.06:05:34.10#ibcon#about to read 6, iclass 34, count 0 2006.285.06:05:34.10#ibcon#read 6, iclass 34, count 0 2006.285.06:05:34.10#ibcon#end of sib2, iclass 34, count 0 2006.285.06:05:34.10#ibcon#*after write, iclass 34, count 0 2006.285.06:05:34.10#ibcon#*before return 0, iclass 34, count 0 2006.285.06:05:34.10#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:05:34.10#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:05:34.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:05:34.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:05:34.10$vck44/valo=8,884.99 2006.285.06:05:34.10#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.06:05:34.10#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.06:05:34.10#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:34.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:05:34.10#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:05:34.10#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:05:34.10#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:05:34.10#ibcon#first serial, iclass 36, count 0 2006.285.06:05:34.10#ibcon#enter sib2, iclass 36, count 0 2006.285.06:05:34.10#ibcon#flushed, iclass 36, count 0 2006.285.06:05:34.10#ibcon#about to write, iclass 36, count 0 2006.285.06:05:34.10#ibcon#wrote, iclass 36, count 0 2006.285.06:05:34.10#ibcon#about to read 3, iclass 36, count 0 2006.285.06:05:34.12#ibcon#read 3, iclass 36, count 0 2006.285.06:05:34.12#ibcon#about to read 4, iclass 36, count 0 2006.285.06:05:34.12#ibcon#read 4, iclass 36, count 0 2006.285.06:05:34.12#ibcon#about to read 5, iclass 36, count 0 2006.285.06:05:34.12#ibcon#read 5, iclass 36, count 0 2006.285.06:05:34.12#ibcon#about to read 6, iclass 36, count 0 2006.285.06:05:34.12#ibcon#read 6, iclass 36, count 0 2006.285.06:05:34.12#ibcon#end of sib2, iclass 36, count 0 2006.285.06:05:34.12#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:05:34.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:05:34.12#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:05:34.12#ibcon#*before write, iclass 36, count 0 2006.285.06:05:34.12#ibcon#enter sib2, iclass 36, count 0 2006.285.06:05:34.12#ibcon#flushed, iclass 36, count 0 2006.285.06:05:34.12#ibcon#about to write, iclass 36, count 0 2006.285.06:05:34.12#ibcon#wrote, iclass 36, count 0 2006.285.06:05:34.12#ibcon#about to read 3, iclass 36, count 0 2006.285.06:05:34.16#ibcon#read 3, iclass 36, count 0 2006.285.06:05:34.16#ibcon#about to read 4, iclass 36, count 0 2006.285.06:05:34.16#ibcon#read 4, iclass 36, count 0 2006.285.06:05:34.16#ibcon#about to read 5, iclass 36, count 0 2006.285.06:05:34.16#ibcon#read 5, iclass 36, count 0 2006.285.06:05:34.16#ibcon#about to read 6, iclass 36, count 0 2006.285.06:05:34.16#ibcon#read 6, iclass 36, count 0 2006.285.06:05:34.16#ibcon#end of sib2, iclass 36, count 0 2006.285.06:05:34.16#ibcon#*after write, iclass 36, count 0 2006.285.06:05:34.16#ibcon#*before return 0, iclass 36, count 0 2006.285.06:05:34.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:05:34.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:05:34.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:05:34.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:05:34.16$vck44/va=8,3 2006.285.06:05:34.16#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.06:05:34.16#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.06:05:34.16#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:34.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:05:34.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:05:34.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:05:34.22#ibcon#enter wrdev, iclass 38, count 2 2006.285.06:05:34.22#ibcon#first serial, iclass 38, count 2 2006.285.06:05:34.22#ibcon#enter sib2, iclass 38, count 2 2006.285.06:05:34.22#ibcon#flushed, iclass 38, count 2 2006.285.06:05:34.22#ibcon#about to write, iclass 38, count 2 2006.285.06:05:34.22#ibcon#wrote, iclass 38, count 2 2006.285.06:05:34.22#ibcon#about to read 3, iclass 38, count 2 2006.285.06:05:34.24#ibcon#read 3, iclass 38, count 2 2006.285.06:05:34.24#ibcon#about to read 4, iclass 38, count 2 2006.285.06:05:34.24#ibcon#read 4, iclass 38, count 2 2006.285.06:05:34.24#ibcon#about to read 5, iclass 38, count 2 2006.285.06:05:34.24#ibcon#read 5, iclass 38, count 2 2006.285.06:05:34.24#ibcon#about to read 6, iclass 38, count 2 2006.285.06:05:34.24#ibcon#read 6, iclass 38, count 2 2006.285.06:05:34.24#ibcon#end of sib2, iclass 38, count 2 2006.285.06:05:34.24#ibcon#*mode == 0, iclass 38, count 2 2006.285.06:05:34.24#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.06:05:34.24#ibcon#[25=AT08-03\r\n] 2006.285.06:05:34.24#ibcon#*before write, iclass 38, count 2 2006.285.06:05:34.24#ibcon#enter sib2, iclass 38, count 2 2006.285.06:05:34.24#ibcon#flushed, iclass 38, count 2 2006.285.06:05:34.24#ibcon#about to write, iclass 38, count 2 2006.285.06:05:34.24#ibcon#wrote, iclass 38, count 2 2006.285.06:05:34.24#ibcon#about to read 3, iclass 38, count 2 2006.285.06:05:34.27#ibcon#read 3, iclass 38, count 2 2006.285.06:05:34.27#ibcon#about to read 4, iclass 38, count 2 2006.285.06:05:34.27#ibcon#read 4, iclass 38, count 2 2006.285.06:05:34.27#ibcon#about to read 5, iclass 38, count 2 2006.285.06:05:34.27#ibcon#read 5, iclass 38, count 2 2006.285.06:05:34.27#ibcon#about to read 6, iclass 38, count 2 2006.285.06:05:34.27#ibcon#read 6, iclass 38, count 2 2006.285.06:05:34.27#ibcon#end of sib2, iclass 38, count 2 2006.285.06:05:34.27#ibcon#*after write, iclass 38, count 2 2006.285.06:05:34.27#ibcon#*before return 0, iclass 38, count 2 2006.285.06:05:34.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:05:34.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:05:34.27#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.06:05:34.27#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:34.27#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:05:34.39#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:05:34.39#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:05:34.39#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:05:34.39#ibcon#first serial, iclass 38, count 0 2006.285.06:05:34.39#ibcon#enter sib2, iclass 38, count 0 2006.285.06:05:34.39#ibcon#flushed, iclass 38, count 0 2006.285.06:05:34.39#ibcon#about to write, iclass 38, count 0 2006.285.06:05:34.39#ibcon#wrote, iclass 38, count 0 2006.285.06:05:34.39#ibcon#about to read 3, iclass 38, count 0 2006.285.06:05:34.41#ibcon#read 3, iclass 38, count 0 2006.285.06:05:34.41#ibcon#about to read 4, iclass 38, count 0 2006.285.06:05:34.41#ibcon#read 4, iclass 38, count 0 2006.285.06:05:34.41#ibcon#about to read 5, iclass 38, count 0 2006.285.06:05:34.41#ibcon#read 5, iclass 38, count 0 2006.285.06:05:34.41#ibcon#about to read 6, iclass 38, count 0 2006.285.06:05:34.41#ibcon#read 6, iclass 38, count 0 2006.285.06:05:34.41#ibcon#end of sib2, iclass 38, count 0 2006.285.06:05:34.41#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:05:34.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:05:34.41#ibcon#[25=USB\r\n] 2006.285.06:05:34.41#ibcon#*before write, iclass 38, count 0 2006.285.06:05:34.41#ibcon#enter sib2, iclass 38, count 0 2006.285.06:05:34.41#ibcon#flushed, iclass 38, count 0 2006.285.06:05:34.41#ibcon#about to write, iclass 38, count 0 2006.285.06:05:34.41#ibcon#wrote, iclass 38, count 0 2006.285.06:05:34.41#ibcon#about to read 3, iclass 38, count 0 2006.285.06:05:34.44#ibcon#read 3, iclass 38, count 0 2006.285.06:05:34.44#ibcon#about to read 4, iclass 38, count 0 2006.285.06:05:34.44#ibcon#read 4, iclass 38, count 0 2006.285.06:05:34.44#ibcon#about to read 5, iclass 38, count 0 2006.285.06:05:34.44#ibcon#read 5, iclass 38, count 0 2006.285.06:05:34.44#ibcon#about to read 6, iclass 38, count 0 2006.285.06:05:34.44#ibcon#read 6, iclass 38, count 0 2006.285.06:05:34.44#ibcon#end of sib2, iclass 38, count 0 2006.285.06:05:34.44#ibcon#*after write, iclass 38, count 0 2006.285.06:05:34.44#ibcon#*before return 0, iclass 38, count 0 2006.285.06:05:34.44#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:05:34.44#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:05:34.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:05:34.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:05:34.44$vck44/vblo=1,629.99 2006.285.06:05:34.44#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.06:05:34.44#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.06:05:34.44#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:34.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:05:34.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:05:34.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:05:34.44#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:05:34.44#ibcon#first serial, iclass 40, count 0 2006.285.06:05:34.44#ibcon#enter sib2, iclass 40, count 0 2006.285.06:05:34.44#ibcon#flushed, iclass 40, count 0 2006.285.06:05:34.44#ibcon#about to write, iclass 40, count 0 2006.285.06:05:34.44#ibcon#wrote, iclass 40, count 0 2006.285.06:05:34.44#ibcon#about to read 3, iclass 40, count 0 2006.285.06:05:34.46#ibcon#read 3, iclass 40, count 0 2006.285.06:05:34.46#ibcon#about to read 4, iclass 40, count 0 2006.285.06:05:34.46#ibcon#read 4, iclass 40, count 0 2006.285.06:05:34.46#ibcon#about to read 5, iclass 40, count 0 2006.285.06:05:34.46#ibcon#read 5, iclass 40, count 0 2006.285.06:05:34.46#ibcon#about to read 6, iclass 40, count 0 2006.285.06:05:34.46#ibcon#read 6, iclass 40, count 0 2006.285.06:05:34.46#ibcon#end of sib2, iclass 40, count 0 2006.285.06:05:34.46#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:05:34.46#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:05:34.46#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:05:34.46#ibcon#*before write, iclass 40, count 0 2006.285.06:05:34.46#ibcon#enter sib2, iclass 40, count 0 2006.285.06:05:34.46#ibcon#flushed, iclass 40, count 0 2006.285.06:05:34.46#ibcon#about to write, iclass 40, count 0 2006.285.06:05:34.46#ibcon#wrote, iclass 40, count 0 2006.285.06:05:34.46#ibcon#about to read 3, iclass 40, count 0 2006.285.06:05:34.50#ibcon#read 3, iclass 40, count 0 2006.285.06:05:34.50#ibcon#about to read 4, iclass 40, count 0 2006.285.06:05:34.50#ibcon#read 4, iclass 40, count 0 2006.285.06:05:34.50#ibcon#about to read 5, iclass 40, count 0 2006.285.06:05:34.50#ibcon#read 5, iclass 40, count 0 2006.285.06:05:34.50#ibcon#about to read 6, iclass 40, count 0 2006.285.06:05:34.50#ibcon#read 6, iclass 40, count 0 2006.285.06:05:34.50#ibcon#end of sib2, iclass 40, count 0 2006.285.06:05:34.50#ibcon#*after write, iclass 40, count 0 2006.285.06:05:34.50#ibcon#*before return 0, iclass 40, count 0 2006.285.06:05:34.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:05:34.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:05:34.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:05:34.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:05:34.50$vck44/vb=1,4 2006.285.06:05:34.50#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.06:05:34.50#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.06:05:34.50#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:34.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:05:34.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:05:34.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:05:34.50#ibcon#enter wrdev, iclass 4, count 2 2006.285.06:05:34.50#ibcon#first serial, iclass 4, count 2 2006.285.06:05:34.50#ibcon#enter sib2, iclass 4, count 2 2006.285.06:05:34.50#ibcon#flushed, iclass 4, count 2 2006.285.06:05:34.50#ibcon#about to write, iclass 4, count 2 2006.285.06:05:34.50#ibcon#wrote, iclass 4, count 2 2006.285.06:05:34.50#ibcon#about to read 3, iclass 4, count 2 2006.285.06:05:34.52#ibcon#read 3, iclass 4, count 2 2006.285.06:05:34.52#ibcon#about to read 4, iclass 4, count 2 2006.285.06:05:34.52#ibcon#read 4, iclass 4, count 2 2006.285.06:05:34.52#ibcon#about to read 5, iclass 4, count 2 2006.285.06:05:34.52#ibcon#read 5, iclass 4, count 2 2006.285.06:05:34.52#ibcon#about to read 6, iclass 4, count 2 2006.285.06:05:34.52#ibcon#read 6, iclass 4, count 2 2006.285.06:05:34.52#ibcon#end of sib2, iclass 4, count 2 2006.285.06:05:34.52#ibcon#*mode == 0, iclass 4, count 2 2006.285.06:05:34.52#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.06:05:34.52#ibcon#[27=AT01-04\r\n] 2006.285.06:05:34.52#ibcon#*before write, iclass 4, count 2 2006.285.06:05:34.52#ibcon#enter sib2, iclass 4, count 2 2006.285.06:05:34.52#ibcon#flushed, iclass 4, count 2 2006.285.06:05:34.52#ibcon#about to write, iclass 4, count 2 2006.285.06:05:34.52#ibcon#wrote, iclass 4, count 2 2006.285.06:05:34.52#ibcon#about to read 3, iclass 4, count 2 2006.285.06:05:34.55#ibcon#read 3, iclass 4, count 2 2006.285.06:05:34.55#ibcon#about to read 4, iclass 4, count 2 2006.285.06:05:34.55#ibcon#read 4, iclass 4, count 2 2006.285.06:05:34.55#ibcon#about to read 5, iclass 4, count 2 2006.285.06:05:34.55#ibcon#read 5, iclass 4, count 2 2006.285.06:05:34.55#ibcon#about to read 6, iclass 4, count 2 2006.285.06:05:34.55#ibcon#read 6, iclass 4, count 2 2006.285.06:05:34.55#ibcon#end of sib2, iclass 4, count 2 2006.285.06:05:34.55#ibcon#*after write, iclass 4, count 2 2006.285.06:05:34.55#ibcon#*before return 0, iclass 4, count 2 2006.285.06:05:34.55#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:05:34.55#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:05:34.55#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.06:05:34.55#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:34.55#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:05:34.67#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:05:34.67#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:05:34.67#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:05:34.67#ibcon#first serial, iclass 4, count 0 2006.285.06:05:34.67#ibcon#enter sib2, iclass 4, count 0 2006.285.06:05:34.67#ibcon#flushed, iclass 4, count 0 2006.285.06:05:34.67#ibcon#about to write, iclass 4, count 0 2006.285.06:05:34.67#ibcon#wrote, iclass 4, count 0 2006.285.06:05:34.67#ibcon#about to read 3, iclass 4, count 0 2006.285.06:05:34.69#ibcon#read 3, iclass 4, count 0 2006.285.06:05:34.69#ibcon#about to read 4, iclass 4, count 0 2006.285.06:05:34.69#ibcon#read 4, iclass 4, count 0 2006.285.06:05:34.69#ibcon#about to read 5, iclass 4, count 0 2006.285.06:05:34.69#ibcon#read 5, iclass 4, count 0 2006.285.06:05:34.69#ibcon#about to read 6, iclass 4, count 0 2006.285.06:05:34.69#ibcon#read 6, iclass 4, count 0 2006.285.06:05:34.69#ibcon#end of sib2, iclass 4, count 0 2006.285.06:05:34.69#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:05:34.69#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:05:34.69#ibcon#[27=USB\r\n] 2006.285.06:05:34.69#ibcon#*before write, iclass 4, count 0 2006.285.06:05:34.69#ibcon#enter sib2, iclass 4, count 0 2006.285.06:05:34.69#ibcon#flushed, iclass 4, count 0 2006.285.06:05:34.69#ibcon#about to write, iclass 4, count 0 2006.285.06:05:34.69#ibcon#wrote, iclass 4, count 0 2006.285.06:05:34.69#ibcon#about to read 3, iclass 4, count 0 2006.285.06:05:34.72#ibcon#read 3, iclass 4, count 0 2006.285.06:05:34.72#ibcon#about to read 4, iclass 4, count 0 2006.285.06:05:34.72#ibcon#read 4, iclass 4, count 0 2006.285.06:05:34.72#ibcon#about to read 5, iclass 4, count 0 2006.285.06:05:34.72#ibcon#read 5, iclass 4, count 0 2006.285.06:05:34.72#ibcon#about to read 6, iclass 4, count 0 2006.285.06:05:34.72#ibcon#read 6, iclass 4, count 0 2006.285.06:05:34.72#ibcon#end of sib2, iclass 4, count 0 2006.285.06:05:34.72#ibcon#*after write, iclass 4, count 0 2006.285.06:05:34.72#ibcon#*before return 0, iclass 4, count 0 2006.285.06:05:34.72#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:05:34.72#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:05:34.72#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:05:34.72#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:05:34.72$vck44/vblo=2,634.99 2006.285.06:05:34.72#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.06:05:34.72#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.06:05:34.72#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:34.72#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:05:34.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:05:34.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:05:34.72#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:05:34.72#ibcon#first serial, iclass 6, count 0 2006.285.06:05:34.72#ibcon#enter sib2, iclass 6, count 0 2006.285.06:05:34.72#ibcon#flushed, iclass 6, count 0 2006.285.06:05:34.72#ibcon#about to write, iclass 6, count 0 2006.285.06:05:34.72#ibcon#wrote, iclass 6, count 0 2006.285.06:05:34.72#ibcon#about to read 3, iclass 6, count 0 2006.285.06:05:34.74#ibcon#read 3, iclass 6, count 0 2006.285.06:05:34.74#ibcon#about to read 4, iclass 6, count 0 2006.285.06:05:34.74#ibcon#read 4, iclass 6, count 0 2006.285.06:05:34.74#ibcon#about to read 5, iclass 6, count 0 2006.285.06:05:34.74#ibcon#read 5, iclass 6, count 0 2006.285.06:05:34.74#ibcon#about to read 6, iclass 6, count 0 2006.285.06:05:34.74#ibcon#read 6, iclass 6, count 0 2006.285.06:05:34.74#ibcon#end of sib2, iclass 6, count 0 2006.285.06:05:34.74#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:05:34.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:05:34.74#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:05:34.74#ibcon#*before write, iclass 6, count 0 2006.285.06:05:34.74#ibcon#enter sib2, iclass 6, count 0 2006.285.06:05:34.74#ibcon#flushed, iclass 6, count 0 2006.285.06:05:34.74#ibcon#about to write, iclass 6, count 0 2006.285.06:05:34.74#ibcon#wrote, iclass 6, count 0 2006.285.06:05:34.74#ibcon#about to read 3, iclass 6, count 0 2006.285.06:05:34.78#ibcon#read 3, iclass 6, count 0 2006.285.06:05:34.78#ibcon#about to read 4, iclass 6, count 0 2006.285.06:05:34.78#ibcon#read 4, iclass 6, count 0 2006.285.06:05:34.78#ibcon#about to read 5, iclass 6, count 0 2006.285.06:05:34.78#ibcon#read 5, iclass 6, count 0 2006.285.06:05:34.78#ibcon#about to read 6, iclass 6, count 0 2006.285.06:05:34.78#ibcon#read 6, iclass 6, count 0 2006.285.06:05:34.78#ibcon#end of sib2, iclass 6, count 0 2006.285.06:05:34.78#ibcon#*after write, iclass 6, count 0 2006.285.06:05:34.78#ibcon#*before return 0, iclass 6, count 0 2006.285.06:05:34.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:05:34.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:05:34.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:05:34.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:05:34.78$vck44/vb=2,5 2006.285.06:05:34.78#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.06:05:34.78#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.06:05:34.78#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:34.78#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:05:34.84#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:05:34.84#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:05:34.84#ibcon#enter wrdev, iclass 10, count 2 2006.285.06:05:34.84#ibcon#first serial, iclass 10, count 2 2006.285.06:05:34.84#ibcon#enter sib2, iclass 10, count 2 2006.285.06:05:34.84#ibcon#flushed, iclass 10, count 2 2006.285.06:05:34.84#ibcon#about to write, iclass 10, count 2 2006.285.06:05:34.84#ibcon#wrote, iclass 10, count 2 2006.285.06:05:34.84#ibcon#about to read 3, iclass 10, count 2 2006.285.06:05:34.86#ibcon#read 3, iclass 10, count 2 2006.285.06:05:34.86#ibcon#about to read 4, iclass 10, count 2 2006.285.06:05:34.86#ibcon#read 4, iclass 10, count 2 2006.285.06:05:34.86#ibcon#about to read 5, iclass 10, count 2 2006.285.06:05:34.86#ibcon#read 5, iclass 10, count 2 2006.285.06:05:34.86#ibcon#about to read 6, iclass 10, count 2 2006.285.06:05:34.86#ibcon#read 6, iclass 10, count 2 2006.285.06:05:34.86#ibcon#end of sib2, iclass 10, count 2 2006.285.06:05:34.86#ibcon#*mode == 0, iclass 10, count 2 2006.285.06:05:34.86#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.06:05:34.86#ibcon#[27=AT02-05\r\n] 2006.285.06:05:34.86#ibcon#*before write, iclass 10, count 2 2006.285.06:05:34.86#ibcon#enter sib2, iclass 10, count 2 2006.285.06:05:34.86#ibcon#flushed, iclass 10, count 2 2006.285.06:05:34.86#ibcon#about to write, iclass 10, count 2 2006.285.06:05:34.86#ibcon#wrote, iclass 10, count 2 2006.285.06:05:34.86#ibcon#about to read 3, iclass 10, count 2 2006.285.06:05:34.89#ibcon#read 3, iclass 10, count 2 2006.285.06:05:34.89#ibcon#about to read 4, iclass 10, count 2 2006.285.06:05:34.89#ibcon#read 4, iclass 10, count 2 2006.285.06:05:34.89#ibcon#about to read 5, iclass 10, count 2 2006.285.06:05:34.89#ibcon#read 5, iclass 10, count 2 2006.285.06:05:34.89#ibcon#about to read 6, iclass 10, count 2 2006.285.06:05:34.89#ibcon#read 6, iclass 10, count 2 2006.285.06:05:34.89#ibcon#end of sib2, iclass 10, count 2 2006.285.06:05:34.89#ibcon#*after write, iclass 10, count 2 2006.285.06:05:34.89#ibcon#*before return 0, iclass 10, count 2 2006.285.06:05:34.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:05:34.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:05:34.89#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.06:05:34.89#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:34.89#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:05:35.01#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:05:35.01#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:05:35.01#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:05:35.01#ibcon#first serial, iclass 10, count 0 2006.285.06:05:35.01#ibcon#enter sib2, iclass 10, count 0 2006.285.06:05:35.01#ibcon#flushed, iclass 10, count 0 2006.285.06:05:35.01#ibcon#about to write, iclass 10, count 0 2006.285.06:05:35.01#ibcon#wrote, iclass 10, count 0 2006.285.06:05:35.01#ibcon#about to read 3, iclass 10, count 0 2006.285.06:05:35.02#abcon#<5=/04 4.1 6.8 25.08 671014.0\r\n> 2006.285.06:05:35.03#ibcon#read 3, iclass 10, count 0 2006.285.06:05:35.03#ibcon#about to read 4, iclass 10, count 0 2006.285.06:05:35.03#ibcon#read 4, iclass 10, count 0 2006.285.06:05:35.03#ibcon#about to read 5, iclass 10, count 0 2006.285.06:05:35.03#ibcon#read 5, iclass 10, count 0 2006.285.06:05:35.03#ibcon#about to read 6, iclass 10, count 0 2006.285.06:05:35.03#ibcon#read 6, iclass 10, count 0 2006.285.06:05:35.03#ibcon#end of sib2, iclass 10, count 0 2006.285.06:05:35.03#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:05:35.03#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:05:35.03#ibcon#[27=USB\r\n] 2006.285.06:05:35.03#ibcon#*before write, iclass 10, count 0 2006.285.06:05:35.03#ibcon#enter sib2, iclass 10, count 0 2006.285.06:05:35.03#ibcon#flushed, iclass 10, count 0 2006.285.06:05:35.03#ibcon#about to write, iclass 10, count 0 2006.285.06:05:35.03#ibcon#wrote, iclass 10, count 0 2006.285.06:05:35.03#ibcon#about to read 3, iclass 10, count 0 2006.285.06:05:35.04#abcon#{5=INTERFACE CLEAR} 2006.285.06:05:35.06#ibcon#read 3, iclass 10, count 0 2006.285.06:05:35.06#ibcon#about to read 4, iclass 10, count 0 2006.285.06:05:35.06#ibcon#read 4, iclass 10, count 0 2006.285.06:05:35.06#ibcon#about to read 5, iclass 10, count 0 2006.285.06:05:35.06#ibcon#read 5, iclass 10, count 0 2006.285.06:05:35.06#ibcon#about to read 6, iclass 10, count 0 2006.285.06:05:35.06#ibcon#read 6, iclass 10, count 0 2006.285.06:05:35.06#ibcon#end of sib2, iclass 10, count 0 2006.285.06:05:35.06#ibcon#*after write, iclass 10, count 0 2006.285.06:05:35.06#ibcon#*before return 0, iclass 10, count 0 2006.285.06:05:35.06#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:05:35.06#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:05:35.06#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:05:35.06#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:05:35.06$vck44/vblo=3,649.99 2006.285.06:05:35.06#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.06:05:35.06#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.06:05:35.06#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:35.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:05:35.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:05:35.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:05:35.06#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:05:35.06#ibcon#first serial, iclass 15, count 0 2006.285.06:05:35.06#ibcon#enter sib2, iclass 15, count 0 2006.285.06:05:35.06#ibcon#flushed, iclass 15, count 0 2006.285.06:05:35.06#ibcon#about to write, iclass 15, count 0 2006.285.06:05:35.06#ibcon#wrote, iclass 15, count 0 2006.285.06:05:35.06#ibcon#about to read 3, iclass 15, count 0 2006.285.06:05:35.08#ibcon#read 3, iclass 15, count 0 2006.285.06:05:35.08#ibcon#about to read 4, iclass 15, count 0 2006.285.06:05:35.08#ibcon#read 4, iclass 15, count 0 2006.285.06:05:35.08#ibcon#about to read 5, iclass 15, count 0 2006.285.06:05:35.08#ibcon#read 5, iclass 15, count 0 2006.285.06:05:35.08#ibcon#about to read 6, iclass 15, count 0 2006.285.06:05:35.08#ibcon#read 6, iclass 15, count 0 2006.285.06:05:35.08#ibcon#end of sib2, iclass 15, count 0 2006.285.06:05:35.08#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:05:35.08#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:05:35.08#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:05:35.08#ibcon#*before write, iclass 15, count 0 2006.285.06:05:35.08#ibcon#enter sib2, iclass 15, count 0 2006.285.06:05:35.08#ibcon#flushed, iclass 15, count 0 2006.285.06:05:35.08#ibcon#about to write, iclass 15, count 0 2006.285.06:05:35.08#ibcon#wrote, iclass 15, count 0 2006.285.06:05:35.08#ibcon#about to read 3, iclass 15, count 0 2006.285.06:05:35.10#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:05:35.12#ibcon#read 3, iclass 15, count 0 2006.285.06:05:35.12#ibcon#about to read 4, iclass 15, count 0 2006.285.06:05:35.12#ibcon#read 4, iclass 15, count 0 2006.285.06:05:35.12#ibcon#about to read 5, iclass 15, count 0 2006.285.06:05:35.12#ibcon#read 5, iclass 15, count 0 2006.285.06:05:35.12#ibcon#about to read 6, iclass 15, count 0 2006.285.06:05:35.12#ibcon#read 6, iclass 15, count 0 2006.285.06:05:35.12#ibcon#end of sib2, iclass 15, count 0 2006.285.06:05:35.12#ibcon#*after write, iclass 15, count 0 2006.285.06:05:35.12#ibcon#*before return 0, iclass 15, count 0 2006.285.06:05:35.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:05:35.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:05:35.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:05:35.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:05:35.12$vck44/vb=3,4 2006.285.06:05:35.12#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.06:05:35.12#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.06:05:35.12#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:35.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:05:35.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:05:35.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:05:35.20#ibcon#enter wrdev, iclass 18, count 2 2006.285.06:05:35.20#ibcon#first serial, iclass 18, count 2 2006.285.06:05:35.20#ibcon#enter sib2, iclass 18, count 2 2006.285.06:05:35.20#ibcon#flushed, iclass 18, count 2 2006.285.06:05:35.20#ibcon#about to write, iclass 18, count 2 2006.285.06:05:35.20#ibcon#wrote, iclass 18, count 2 2006.285.06:05:35.20#ibcon#about to read 3, iclass 18, count 2 2006.285.06:05:35.22#ibcon#read 3, iclass 18, count 2 2006.285.06:05:35.22#ibcon#about to read 4, iclass 18, count 2 2006.285.06:05:35.22#ibcon#read 4, iclass 18, count 2 2006.285.06:05:35.22#ibcon#about to read 5, iclass 18, count 2 2006.285.06:05:35.22#ibcon#read 5, iclass 18, count 2 2006.285.06:05:35.22#ibcon#about to read 6, iclass 18, count 2 2006.285.06:05:35.22#ibcon#read 6, iclass 18, count 2 2006.285.06:05:35.22#ibcon#end of sib2, iclass 18, count 2 2006.285.06:05:35.22#ibcon#*mode == 0, iclass 18, count 2 2006.285.06:05:35.22#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.06:05:35.22#ibcon#[27=AT03-04\r\n] 2006.285.06:05:35.22#ibcon#*before write, iclass 18, count 2 2006.285.06:05:35.22#ibcon#enter sib2, iclass 18, count 2 2006.285.06:05:35.22#ibcon#flushed, iclass 18, count 2 2006.285.06:05:35.22#ibcon#about to write, iclass 18, count 2 2006.285.06:05:35.22#ibcon#wrote, iclass 18, count 2 2006.285.06:05:35.22#ibcon#about to read 3, iclass 18, count 2 2006.285.06:05:35.25#ibcon#read 3, iclass 18, count 2 2006.285.06:05:35.25#ibcon#about to read 4, iclass 18, count 2 2006.285.06:05:35.25#ibcon#read 4, iclass 18, count 2 2006.285.06:05:35.25#ibcon#about to read 5, iclass 18, count 2 2006.285.06:05:35.25#ibcon#read 5, iclass 18, count 2 2006.285.06:05:35.25#ibcon#about to read 6, iclass 18, count 2 2006.285.06:05:35.25#ibcon#read 6, iclass 18, count 2 2006.285.06:05:35.25#ibcon#end of sib2, iclass 18, count 2 2006.285.06:05:35.25#ibcon#*after write, iclass 18, count 2 2006.285.06:05:35.25#ibcon#*before return 0, iclass 18, count 2 2006.285.06:05:35.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:05:35.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:05:35.25#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.06:05:35.25#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:35.25#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:05:35.37#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:05:35.37#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:05:35.37#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:05:35.37#ibcon#first serial, iclass 18, count 0 2006.285.06:05:35.37#ibcon#enter sib2, iclass 18, count 0 2006.285.06:05:35.37#ibcon#flushed, iclass 18, count 0 2006.285.06:05:35.37#ibcon#about to write, iclass 18, count 0 2006.285.06:05:35.37#ibcon#wrote, iclass 18, count 0 2006.285.06:05:35.37#ibcon#about to read 3, iclass 18, count 0 2006.285.06:05:35.39#ibcon#read 3, iclass 18, count 0 2006.285.06:05:35.39#ibcon#about to read 4, iclass 18, count 0 2006.285.06:05:35.39#ibcon#read 4, iclass 18, count 0 2006.285.06:05:35.39#ibcon#about to read 5, iclass 18, count 0 2006.285.06:05:35.39#ibcon#read 5, iclass 18, count 0 2006.285.06:05:35.39#ibcon#about to read 6, iclass 18, count 0 2006.285.06:05:35.39#ibcon#read 6, iclass 18, count 0 2006.285.06:05:35.39#ibcon#end of sib2, iclass 18, count 0 2006.285.06:05:35.39#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:05:35.39#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:05:35.39#ibcon#[27=USB\r\n] 2006.285.06:05:35.39#ibcon#*before write, iclass 18, count 0 2006.285.06:05:35.39#ibcon#enter sib2, iclass 18, count 0 2006.285.06:05:35.39#ibcon#flushed, iclass 18, count 0 2006.285.06:05:35.39#ibcon#about to write, iclass 18, count 0 2006.285.06:05:35.39#ibcon#wrote, iclass 18, count 0 2006.285.06:05:35.39#ibcon#about to read 3, iclass 18, count 0 2006.285.06:05:35.42#ibcon#read 3, iclass 18, count 0 2006.285.06:05:35.42#ibcon#about to read 4, iclass 18, count 0 2006.285.06:05:35.42#ibcon#read 4, iclass 18, count 0 2006.285.06:05:35.42#ibcon#about to read 5, iclass 18, count 0 2006.285.06:05:35.42#ibcon#read 5, iclass 18, count 0 2006.285.06:05:35.42#ibcon#about to read 6, iclass 18, count 0 2006.285.06:05:35.42#ibcon#read 6, iclass 18, count 0 2006.285.06:05:35.42#ibcon#end of sib2, iclass 18, count 0 2006.285.06:05:35.42#ibcon#*after write, iclass 18, count 0 2006.285.06:05:35.42#ibcon#*before return 0, iclass 18, count 0 2006.285.06:05:35.42#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:05:35.42#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:05:35.42#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:05:35.42#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:05:35.42$vck44/vblo=4,679.99 2006.285.06:05:35.42#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.06:05:35.42#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.06:05:35.42#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:35.42#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:05:35.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:05:35.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:05:35.42#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:05:35.42#ibcon#first serial, iclass 20, count 0 2006.285.06:05:35.42#ibcon#enter sib2, iclass 20, count 0 2006.285.06:05:35.42#ibcon#flushed, iclass 20, count 0 2006.285.06:05:35.42#ibcon#about to write, iclass 20, count 0 2006.285.06:05:35.42#ibcon#wrote, iclass 20, count 0 2006.285.06:05:35.42#ibcon#about to read 3, iclass 20, count 0 2006.285.06:05:35.44#ibcon#read 3, iclass 20, count 0 2006.285.06:05:35.44#ibcon#about to read 4, iclass 20, count 0 2006.285.06:05:35.44#ibcon#read 4, iclass 20, count 0 2006.285.06:05:35.44#ibcon#about to read 5, iclass 20, count 0 2006.285.06:05:35.44#ibcon#read 5, iclass 20, count 0 2006.285.06:05:35.44#ibcon#about to read 6, iclass 20, count 0 2006.285.06:05:35.44#ibcon#read 6, iclass 20, count 0 2006.285.06:05:35.44#ibcon#end of sib2, iclass 20, count 0 2006.285.06:05:35.44#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:05:35.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:05:35.44#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:05:35.44#ibcon#*before write, iclass 20, count 0 2006.285.06:05:35.44#ibcon#enter sib2, iclass 20, count 0 2006.285.06:05:35.44#ibcon#flushed, iclass 20, count 0 2006.285.06:05:35.44#ibcon#about to write, iclass 20, count 0 2006.285.06:05:35.44#ibcon#wrote, iclass 20, count 0 2006.285.06:05:35.44#ibcon#about to read 3, iclass 20, count 0 2006.285.06:05:35.48#ibcon#read 3, iclass 20, count 0 2006.285.06:05:35.48#ibcon#about to read 4, iclass 20, count 0 2006.285.06:05:35.48#ibcon#read 4, iclass 20, count 0 2006.285.06:05:35.48#ibcon#about to read 5, iclass 20, count 0 2006.285.06:05:35.48#ibcon#read 5, iclass 20, count 0 2006.285.06:05:35.48#ibcon#about to read 6, iclass 20, count 0 2006.285.06:05:35.48#ibcon#read 6, iclass 20, count 0 2006.285.06:05:35.48#ibcon#end of sib2, iclass 20, count 0 2006.285.06:05:35.48#ibcon#*after write, iclass 20, count 0 2006.285.06:05:35.48#ibcon#*before return 0, iclass 20, count 0 2006.285.06:05:35.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:05:35.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:05:35.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:05:35.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:05:35.48$vck44/vb=4,5 2006.285.06:05:35.48#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.06:05:35.48#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.06:05:35.48#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:35.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:05:35.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:05:35.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:05:35.54#ibcon#enter wrdev, iclass 22, count 2 2006.285.06:05:35.54#ibcon#first serial, iclass 22, count 2 2006.285.06:05:35.54#ibcon#enter sib2, iclass 22, count 2 2006.285.06:05:35.54#ibcon#flushed, iclass 22, count 2 2006.285.06:05:35.54#ibcon#about to write, iclass 22, count 2 2006.285.06:05:35.54#ibcon#wrote, iclass 22, count 2 2006.285.06:05:35.54#ibcon#about to read 3, iclass 22, count 2 2006.285.06:05:35.56#ibcon#read 3, iclass 22, count 2 2006.285.06:05:35.56#ibcon#about to read 4, iclass 22, count 2 2006.285.06:05:35.56#ibcon#read 4, iclass 22, count 2 2006.285.06:05:35.56#ibcon#about to read 5, iclass 22, count 2 2006.285.06:05:35.56#ibcon#read 5, iclass 22, count 2 2006.285.06:05:35.56#ibcon#about to read 6, iclass 22, count 2 2006.285.06:05:35.56#ibcon#read 6, iclass 22, count 2 2006.285.06:05:35.56#ibcon#end of sib2, iclass 22, count 2 2006.285.06:05:35.56#ibcon#*mode == 0, iclass 22, count 2 2006.285.06:05:35.56#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.06:05:35.56#ibcon#[27=AT04-05\r\n] 2006.285.06:05:35.56#ibcon#*before write, iclass 22, count 2 2006.285.06:05:35.56#ibcon#enter sib2, iclass 22, count 2 2006.285.06:05:35.56#ibcon#flushed, iclass 22, count 2 2006.285.06:05:35.56#ibcon#about to write, iclass 22, count 2 2006.285.06:05:35.56#ibcon#wrote, iclass 22, count 2 2006.285.06:05:35.56#ibcon#about to read 3, iclass 22, count 2 2006.285.06:05:35.59#ibcon#read 3, iclass 22, count 2 2006.285.06:05:35.59#ibcon#about to read 4, iclass 22, count 2 2006.285.06:05:35.59#ibcon#read 4, iclass 22, count 2 2006.285.06:05:35.59#ibcon#about to read 5, iclass 22, count 2 2006.285.06:05:35.59#ibcon#read 5, iclass 22, count 2 2006.285.06:05:35.59#ibcon#about to read 6, iclass 22, count 2 2006.285.06:05:35.59#ibcon#read 6, iclass 22, count 2 2006.285.06:05:35.59#ibcon#end of sib2, iclass 22, count 2 2006.285.06:05:35.59#ibcon#*after write, iclass 22, count 2 2006.285.06:05:35.59#ibcon#*before return 0, iclass 22, count 2 2006.285.06:05:35.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:05:35.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:05:35.59#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.06:05:35.59#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:35.59#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:05:35.71#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:05:35.71#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:05:35.71#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:05:35.71#ibcon#first serial, iclass 22, count 0 2006.285.06:05:35.71#ibcon#enter sib2, iclass 22, count 0 2006.285.06:05:35.71#ibcon#flushed, iclass 22, count 0 2006.285.06:05:35.71#ibcon#about to write, iclass 22, count 0 2006.285.06:05:35.71#ibcon#wrote, iclass 22, count 0 2006.285.06:05:35.71#ibcon#about to read 3, iclass 22, count 0 2006.285.06:05:35.73#ibcon#read 3, iclass 22, count 0 2006.285.06:05:35.73#ibcon#about to read 4, iclass 22, count 0 2006.285.06:05:35.73#ibcon#read 4, iclass 22, count 0 2006.285.06:05:35.73#ibcon#about to read 5, iclass 22, count 0 2006.285.06:05:35.73#ibcon#read 5, iclass 22, count 0 2006.285.06:05:35.73#ibcon#about to read 6, iclass 22, count 0 2006.285.06:05:35.73#ibcon#read 6, iclass 22, count 0 2006.285.06:05:35.73#ibcon#end of sib2, iclass 22, count 0 2006.285.06:05:35.73#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:05:35.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:05:35.73#ibcon#[27=USB\r\n] 2006.285.06:05:35.73#ibcon#*before write, iclass 22, count 0 2006.285.06:05:35.73#ibcon#enter sib2, iclass 22, count 0 2006.285.06:05:35.73#ibcon#flushed, iclass 22, count 0 2006.285.06:05:35.73#ibcon#about to write, iclass 22, count 0 2006.285.06:05:35.73#ibcon#wrote, iclass 22, count 0 2006.285.06:05:35.73#ibcon#about to read 3, iclass 22, count 0 2006.285.06:05:35.76#ibcon#read 3, iclass 22, count 0 2006.285.06:05:35.76#ibcon#about to read 4, iclass 22, count 0 2006.285.06:05:35.76#ibcon#read 4, iclass 22, count 0 2006.285.06:05:35.76#ibcon#about to read 5, iclass 22, count 0 2006.285.06:05:35.76#ibcon#read 5, iclass 22, count 0 2006.285.06:05:35.76#ibcon#about to read 6, iclass 22, count 0 2006.285.06:05:35.76#ibcon#read 6, iclass 22, count 0 2006.285.06:05:35.76#ibcon#end of sib2, iclass 22, count 0 2006.285.06:05:35.76#ibcon#*after write, iclass 22, count 0 2006.285.06:05:35.76#ibcon#*before return 0, iclass 22, count 0 2006.285.06:05:35.76#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:05:35.76#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:05:35.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:05:35.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:05:35.76$vck44/vblo=5,709.99 2006.285.06:05:35.76#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.06:05:35.76#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.06:05:35.76#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:35.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:05:35.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:05:35.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:05:35.76#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:05:35.76#ibcon#first serial, iclass 24, count 0 2006.285.06:05:35.76#ibcon#enter sib2, iclass 24, count 0 2006.285.06:05:35.76#ibcon#flushed, iclass 24, count 0 2006.285.06:05:35.76#ibcon#about to write, iclass 24, count 0 2006.285.06:05:35.76#ibcon#wrote, iclass 24, count 0 2006.285.06:05:35.76#ibcon#about to read 3, iclass 24, count 0 2006.285.06:05:35.78#ibcon#read 3, iclass 24, count 0 2006.285.06:05:35.78#ibcon#about to read 4, iclass 24, count 0 2006.285.06:05:35.78#ibcon#read 4, iclass 24, count 0 2006.285.06:05:35.78#ibcon#about to read 5, iclass 24, count 0 2006.285.06:05:35.78#ibcon#read 5, iclass 24, count 0 2006.285.06:05:35.78#ibcon#about to read 6, iclass 24, count 0 2006.285.06:05:35.78#ibcon#read 6, iclass 24, count 0 2006.285.06:05:35.78#ibcon#end of sib2, iclass 24, count 0 2006.285.06:05:35.78#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:05:35.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:05:35.78#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:05:35.78#ibcon#*before write, iclass 24, count 0 2006.285.06:05:35.78#ibcon#enter sib2, iclass 24, count 0 2006.285.06:05:35.78#ibcon#flushed, iclass 24, count 0 2006.285.06:05:35.78#ibcon#about to write, iclass 24, count 0 2006.285.06:05:35.78#ibcon#wrote, iclass 24, count 0 2006.285.06:05:35.78#ibcon#about to read 3, iclass 24, count 0 2006.285.06:05:35.82#ibcon#read 3, iclass 24, count 0 2006.285.06:05:35.82#ibcon#about to read 4, iclass 24, count 0 2006.285.06:05:35.82#ibcon#read 4, iclass 24, count 0 2006.285.06:05:35.82#ibcon#about to read 5, iclass 24, count 0 2006.285.06:05:35.82#ibcon#read 5, iclass 24, count 0 2006.285.06:05:35.82#ibcon#about to read 6, iclass 24, count 0 2006.285.06:05:35.82#ibcon#read 6, iclass 24, count 0 2006.285.06:05:35.82#ibcon#end of sib2, iclass 24, count 0 2006.285.06:05:35.82#ibcon#*after write, iclass 24, count 0 2006.285.06:05:35.82#ibcon#*before return 0, iclass 24, count 0 2006.285.06:05:35.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:05:35.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:05:35.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:05:35.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:05:35.82$vck44/vb=5,4 2006.285.06:05:35.82#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.06:05:35.82#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.06:05:35.82#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:35.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:05:35.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:05:35.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:05:35.88#ibcon#enter wrdev, iclass 26, count 2 2006.285.06:05:35.88#ibcon#first serial, iclass 26, count 2 2006.285.06:05:35.88#ibcon#enter sib2, iclass 26, count 2 2006.285.06:05:35.88#ibcon#flushed, iclass 26, count 2 2006.285.06:05:35.88#ibcon#about to write, iclass 26, count 2 2006.285.06:05:35.88#ibcon#wrote, iclass 26, count 2 2006.285.06:05:35.88#ibcon#about to read 3, iclass 26, count 2 2006.285.06:05:35.90#ibcon#read 3, iclass 26, count 2 2006.285.06:05:35.90#ibcon#about to read 4, iclass 26, count 2 2006.285.06:05:35.90#ibcon#read 4, iclass 26, count 2 2006.285.06:05:35.90#ibcon#about to read 5, iclass 26, count 2 2006.285.06:05:35.90#ibcon#read 5, iclass 26, count 2 2006.285.06:05:35.90#ibcon#about to read 6, iclass 26, count 2 2006.285.06:05:35.90#ibcon#read 6, iclass 26, count 2 2006.285.06:05:35.90#ibcon#end of sib2, iclass 26, count 2 2006.285.06:05:35.90#ibcon#*mode == 0, iclass 26, count 2 2006.285.06:05:35.90#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.06:05:35.90#ibcon#[27=AT05-04\r\n] 2006.285.06:05:35.90#ibcon#*before write, iclass 26, count 2 2006.285.06:05:35.90#ibcon#enter sib2, iclass 26, count 2 2006.285.06:05:35.90#ibcon#flushed, iclass 26, count 2 2006.285.06:05:35.90#ibcon#about to write, iclass 26, count 2 2006.285.06:05:35.90#ibcon#wrote, iclass 26, count 2 2006.285.06:05:35.90#ibcon#about to read 3, iclass 26, count 2 2006.285.06:05:35.93#ibcon#read 3, iclass 26, count 2 2006.285.06:05:35.93#ibcon#about to read 4, iclass 26, count 2 2006.285.06:05:35.93#ibcon#read 4, iclass 26, count 2 2006.285.06:05:35.93#ibcon#about to read 5, iclass 26, count 2 2006.285.06:05:35.93#ibcon#read 5, iclass 26, count 2 2006.285.06:05:35.93#ibcon#about to read 6, iclass 26, count 2 2006.285.06:05:35.93#ibcon#read 6, iclass 26, count 2 2006.285.06:05:35.93#ibcon#end of sib2, iclass 26, count 2 2006.285.06:05:35.93#ibcon#*after write, iclass 26, count 2 2006.285.06:05:35.93#ibcon#*before return 0, iclass 26, count 2 2006.285.06:05:35.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:05:35.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:05:35.93#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.06:05:35.93#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:35.93#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:05:36.05#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:05:36.05#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:05:36.05#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:05:36.05#ibcon#first serial, iclass 26, count 0 2006.285.06:05:36.05#ibcon#enter sib2, iclass 26, count 0 2006.285.06:05:36.05#ibcon#flushed, iclass 26, count 0 2006.285.06:05:36.05#ibcon#about to write, iclass 26, count 0 2006.285.06:05:36.05#ibcon#wrote, iclass 26, count 0 2006.285.06:05:36.05#ibcon#about to read 3, iclass 26, count 0 2006.285.06:05:36.07#ibcon#read 3, iclass 26, count 0 2006.285.06:05:36.07#ibcon#about to read 4, iclass 26, count 0 2006.285.06:05:36.07#ibcon#read 4, iclass 26, count 0 2006.285.06:05:36.07#ibcon#about to read 5, iclass 26, count 0 2006.285.06:05:36.07#ibcon#read 5, iclass 26, count 0 2006.285.06:05:36.07#ibcon#about to read 6, iclass 26, count 0 2006.285.06:05:36.07#ibcon#read 6, iclass 26, count 0 2006.285.06:05:36.07#ibcon#end of sib2, iclass 26, count 0 2006.285.06:05:36.07#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:05:36.07#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:05:36.07#ibcon#[27=USB\r\n] 2006.285.06:05:36.07#ibcon#*before write, iclass 26, count 0 2006.285.06:05:36.07#ibcon#enter sib2, iclass 26, count 0 2006.285.06:05:36.07#ibcon#flushed, iclass 26, count 0 2006.285.06:05:36.07#ibcon#about to write, iclass 26, count 0 2006.285.06:05:36.07#ibcon#wrote, iclass 26, count 0 2006.285.06:05:36.07#ibcon#about to read 3, iclass 26, count 0 2006.285.06:05:36.10#ibcon#read 3, iclass 26, count 0 2006.285.06:05:36.10#ibcon#about to read 4, iclass 26, count 0 2006.285.06:05:36.10#ibcon#read 4, iclass 26, count 0 2006.285.06:05:36.10#ibcon#about to read 5, iclass 26, count 0 2006.285.06:05:36.10#ibcon#read 5, iclass 26, count 0 2006.285.06:05:36.10#ibcon#about to read 6, iclass 26, count 0 2006.285.06:05:36.10#ibcon#read 6, iclass 26, count 0 2006.285.06:05:36.10#ibcon#end of sib2, iclass 26, count 0 2006.285.06:05:36.10#ibcon#*after write, iclass 26, count 0 2006.285.06:05:36.10#ibcon#*before return 0, iclass 26, count 0 2006.285.06:05:36.10#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:05:36.10#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:05:36.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:05:36.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:05:36.10$vck44/vblo=6,719.99 2006.285.06:05:36.10#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.06:05:36.10#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.06:05:36.10#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:36.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:05:36.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:05:36.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:05:36.10#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:05:36.10#ibcon#first serial, iclass 28, count 0 2006.285.06:05:36.10#ibcon#enter sib2, iclass 28, count 0 2006.285.06:05:36.10#ibcon#flushed, iclass 28, count 0 2006.285.06:05:36.10#ibcon#about to write, iclass 28, count 0 2006.285.06:05:36.10#ibcon#wrote, iclass 28, count 0 2006.285.06:05:36.10#ibcon#about to read 3, iclass 28, count 0 2006.285.06:05:36.12#ibcon#read 3, iclass 28, count 0 2006.285.06:05:36.12#ibcon#about to read 4, iclass 28, count 0 2006.285.06:05:36.12#ibcon#read 4, iclass 28, count 0 2006.285.06:05:36.12#ibcon#about to read 5, iclass 28, count 0 2006.285.06:05:36.12#ibcon#read 5, iclass 28, count 0 2006.285.06:05:36.12#ibcon#about to read 6, iclass 28, count 0 2006.285.06:05:36.12#ibcon#read 6, iclass 28, count 0 2006.285.06:05:36.12#ibcon#end of sib2, iclass 28, count 0 2006.285.06:05:36.12#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:05:36.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:05:36.12#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:05:36.12#ibcon#*before write, iclass 28, count 0 2006.285.06:05:36.12#ibcon#enter sib2, iclass 28, count 0 2006.285.06:05:36.12#ibcon#flushed, iclass 28, count 0 2006.285.06:05:36.12#ibcon#about to write, iclass 28, count 0 2006.285.06:05:36.12#ibcon#wrote, iclass 28, count 0 2006.285.06:05:36.12#ibcon#about to read 3, iclass 28, count 0 2006.285.06:05:36.16#ibcon#read 3, iclass 28, count 0 2006.285.06:05:36.16#ibcon#about to read 4, iclass 28, count 0 2006.285.06:05:36.16#ibcon#read 4, iclass 28, count 0 2006.285.06:05:36.16#ibcon#about to read 5, iclass 28, count 0 2006.285.06:05:36.16#ibcon#read 5, iclass 28, count 0 2006.285.06:05:36.16#ibcon#about to read 6, iclass 28, count 0 2006.285.06:05:36.16#ibcon#read 6, iclass 28, count 0 2006.285.06:05:36.16#ibcon#end of sib2, iclass 28, count 0 2006.285.06:05:36.16#ibcon#*after write, iclass 28, count 0 2006.285.06:05:36.16#ibcon#*before return 0, iclass 28, count 0 2006.285.06:05:36.16#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:05:36.16#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:05:36.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:05:36.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:05:36.16$vck44/vb=6,3 2006.285.06:05:36.16#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.06:05:36.16#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.06:05:36.16#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:36.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:05:36.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:05:36.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:05:36.22#ibcon#enter wrdev, iclass 30, count 2 2006.285.06:05:36.22#ibcon#first serial, iclass 30, count 2 2006.285.06:05:36.22#ibcon#enter sib2, iclass 30, count 2 2006.285.06:05:36.22#ibcon#flushed, iclass 30, count 2 2006.285.06:05:36.22#ibcon#about to write, iclass 30, count 2 2006.285.06:05:36.22#ibcon#wrote, iclass 30, count 2 2006.285.06:05:36.22#ibcon#about to read 3, iclass 30, count 2 2006.285.06:05:36.24#ibcon#read 3, iclass 30, count 2 2006.285.06:05:36.24#ibcon#about to read 4, iclass 30, count 2 2006.285.06:05:36.24#ibcon#read 4, iclass 30, count 2 2006.285.06:05:36.24#ibcon#about to read 5, iclass 30, count 2 2006.285.06:05:36.24#ibcon#read 5, iclass 30, count 2 2006.285.06:05:36.24#ibcon#about to read 6, iclass 30, count 2 2006.285.06:05:36.24#ibcon#read 6, iclass 30, count 2 2006.285.06:05:36.24#ibcon#end of sib2, iclass 30, count 2 2006.285.06:05:36.24#ibcon#*mode == 0, iclass 30, count 2 2006.285.06:05:36.24#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.06:05:36.24#ibcon#[27=AT06-03\r\n] 2006.285.06:05:36.24#ibcon#*before write, iclass 30, count 2 2006.285.06:05:36.24#ibcon#enter sib2, iclass 30, count 2 2006.285.06:05:36.24#ibcon#flushed, iclass 30, count 2 2006.285.06:05:36.24#ibcon#about to write, iclass 30, count 2 2006.285.06:05:36.24#ibcon#wrote, iclass 30, count 2 2006.285.06:05:36.24#ibcon#about to read 3, iclass 30, count 2 2006.285.06:05:36.28#ibcon#read 3, iclass 30, count 2 2006.285.06:05:36.28#ibcon#about to read 4, iclass 30, count 2 2006.285.06:05:36.28#ibcon#read 4, iclass 30, count 2 2006.285.06:05:36.28#ibcon#about to read 5, iclass 30, count 2 2006.285.06:05:36.28#ibcon#read 5, iclass 30, count 2 2006.285.06:05:36.28#ibcon#about to read 6, iclass 30, count 2 2006.285.06:05:36.28#ibcon#read 6, iclass 30, count 2 2006.285.06:05:36.28#ibcon#end of sib2, iclass 30, count 2 2006.285.06:05:36.28#ibcon#*after write, iclass 30, count 2 2006.285.06:05:36.28#ibcon#*before return 0, iclass 30, count 2 2006.285.06:05:36.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:05:36.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:05:36.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.06:05:36.28#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:36.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:05:36.39#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:05:36.39#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:05:36.39#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:05:36.39#ibcon#first serial, iclass 30, count 0 2006.285.06:05:36.39#ibcon#enter sib2, iclass 30, count 0 2006.285.06:05:36.39#ibcon#flushed, iclass 30, count 0 2006.285.06:05:36.39#ibcon#about to write, iclass 30, count 0 2006.285.06:05:36.39#ibcon#wrote, iclass 30, count 0 2006.285.06:05:36.39#ibcon#about to read 3, iclass 30, count 0 2006.285.06:05:36.41#ibcon#read 3, iclass 30, count 0 2006.285.06:05:36.41#ibcon#about to read 4, iclass 30, count 0 2006.285.06:05:36.41#ibcon#read 4, iclass 30, count 0 2006.285.06:05:36.41#ibcon#about to read 5, iclass 30, count 0 2006.285.06:05:36.41#ibcon#read 5, iclass 30, count 0 2006.285.06:05:36.41#ibcon#about to read 6, iclass 30, count 0 2006.285.06:05:36.41#ibcon#read 6, iclass 30, count 0 2006.285.06:05:36.41#ibcon#end of sib2, iclass 30, count 0 2006.285.06:05:36.41#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:05:36.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:05:36.41#ibcon#[27=USB\r\n] 2006.285.06:05:36.41#ibcon#*before write, iclass 30, count 0 2006.285.06:05:36.41#ibcon#enter sib2, iclass 30, count 0 2006.285.06:05:36.41#ibcon#flushed, iclass 30, count 0 2006.285.06:05:36.41#ibcon#about to write, iclass 30, count 0 2006.285.06:05:36.41#ibcon#wrote, iclass 30, count 0 2006.285.06:05:36.41#ibcon#about to read 3, iclass 30, count 0 2006.285.06:05:36.44#ibcon#read 3, iclass 30, count 0 2006.285.06:05:36.44#ibcon#about to read 4, iclass 30, count 0 2006.285.06:05:36.44#ibcon#read 4, iclass 30, count 0 2006.285.06:05:36.44#ibcon#about to read 5, iclass 30, count 0 2006.285.06:05:36.44#ibcon#read 5, iclass 30, count 0 2006.285.06:05:36.44#ibcon#about to read 6, iclass 30, count 0 2006.285.06:05:36.44#ibcon#read 6, iclass 30, count 0 2006.285.06:05:36.44#ibcon#end of sib2, iclass 30, count 0 2006.285.06:05:36.44#ibcon#*after write, iclass 30, count 0 2006.285.06:05:36.44#ibcon#*before return 0, iclass 30, count 0 2006.285.06:05:36.44#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:05:36.44#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:05:36.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:05:36.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:05:36.44$vck44/vblo=7,734.99 2006.285.06:05:36.44#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.06:05:36.44#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.06:05:36.44#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:36.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:05:36.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:05:36.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:05:36.44#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:05:36.44#ibcon#first serial, iclass 32, count 0 2006.285.06:05:36.44#ibcon#enter sib2, iclass 32, count 0 2006.285.06:05:36.44#ibcon#flushed, iclass 32, count 0 2006.285.06:05:36.44#ibcon#about to write, iclass 32, count 0 2006.285.06:05:36.44#ibcon#wrote, iclass 32, count 0 2006.285.06:05:36.44#ibcon#about to read 3, iclass 32, count 0 2006.285.06:05:36.46#ibcon#read 3, iclass 32, count 0 2006.285.06:05:36.46#ibcon#about to read 4, iclass 32, count 0 2006.285.06:05:36.46#ibcon#read 4, iclass 32, count 0 2006.285.06:05:36.46#ibcon#about to read 5, iclass 32, count 0 2006.285.06:05:36.46#ibcon#read 5, iclass 32, count 0 2006.285.06:05:36.46#ibcon#about to read 6, iclass 32, count 0 2006.285.06:05:36.46#ibcon#read 6, iclass 32, count 0 2006.285.06:05:36.46#ibcon#end of sib2, iclass 32, count 0 2006.285.06:05:36.46#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:05:36.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:05:36.46#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:05:36.46#ibcon#*before write, iclass 32, count 0 2006.285.06:05:36.46#ibcon#enter sib2, iclass 32, count 0 2006.285.06:05:36.46#ibcon#flushed, iclass 32, count 0 2006.285.06:05:36.46#ibcon#about to write, iclass 32, count 0 2006.285.06:05:36.46#ibcon#wrote, iclass 32, count 0 2006.285.06:05:36.46#ibcon#about to read 3, iclass 32, count 0 2006.285.06:05:36.50#ibcon#read 3, iclass 32, count 0 2006.285.06:05:36.50#ibcon#about to read 4, iclass 32, count 0 2006.285.06:05:36.50#ibcon#read 4, iclass 32, count 0 2006.285.06:05:36.50#ibcon#about to read 5, iclass 32, count 0 2006.285.06:05:36.50#ibcon#read 5, iclass 32, count 0 2006.285.06:05:36.50#ibcon#about to read 6, iclass 32, count 0 2006.285.06:05:36.50#ibcon#read 6, iclass 32, count 0 2006.285.06:05:36.50#ibcon#end of sib2, iclass 32, count 0 2006.285.06:05:36.50#ibcon#*after write, iclass 32, count 0 2006.285.06:05:36.50#ibcon#*before return 0, iclass 32, count 0 2006.285.06:05:36.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:05:36.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:05:36.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:05:36.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:05:36.50$vck44/vb=7,4 2006.285.06:05:36.50#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.06:05:36.50#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.06:05:36.50#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:36.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:05:36.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:05:36.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:05:36.56#ibcon#enter wrdev, iclass 34, count 2 2006.285.06:05:36.56#ibcon#first serial, iclass 34, count 2 2006.285.06:05:36.56#ibcon#enter sib2, iclass 34, count 2 2006.285.06:05:36.56#ibcon#flushed, iclass 34, count 2 2006.285.06:05:36.56#ibcon#about to write, iclass 34, count 2 2006.285.06:05:36.56#ibcon#wrote, iclass 34, count 2 2006.285.06:05:36.56#ibcon#about to read 3, iclass 34, count 2 2006.285.06:05:36.58#ibcon#read 3, iclass 34, count 2 2006.285.06:05:36.58#ibcon#about to read 4, iclass 34, count 2 2006.285.06:05:36.58#ibcon#read 4, iclass 34, count 2 2006.285.06:05:36.58#ibcon#about to read 5, iclass 34, count 2 2006.285.06:05:36.58#ibcon#read 5, iclass 34, count 2 2006.285.06:05:36.58#ibcon#about to read 6, iclass 34, count 2 2006.285.06:05:36.58#ibcon#read 6, iclass 34, count 2 2006.285.06:05:36.58#ibcon#end of sib2, iclass 34, count 2 2006.285.06:05:36.58#ibcon#*mode == 0, iclass 34, count 2 2006.285.06:05:36.58#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.06:05:36.58#ibcon#[27=AT07-04\r\n] 2006.285.06:05:36.58#ibcon#*before write, iclass 34, count 2 2006.285.06:05:36.58#ibcon#enter sib2, iclass 34, count 2 2006.285.06:05:36.58#ibcon#flushed, iclass 34, count 2 2006.285.06:05:36.58#ibcon#about to write, iclass 34, count 2 2006.285.06:05:36.58#ibcon#wrote, iclass 34, count 2 2006.285.06:05:36.58#ibcon#about to read 3, iclass 34, count 2 2006.285.06:05:36.61#ibcon#read 3, iclass 34, count 2 2006.285.06:05:36.61#ibcon#about to read 4, iclass 34, count 2 2006.285.06:05:36.61#ibcon#read 4, iclass 34, count 2 2006.285.06:05:36.61#ibcon#about to read 5, iclass 34, count 2 2006.285.06:05:36.61#ibcon#read 5, iclass 34, count 2 2006.285.06:05:36.61#ibcon#about to read 6, iclass 34, count 2 2006.285.06:05:36.61#ibcon#read 6, iclass 34, count 2 2006.285.06:05:36.61#ibcon#end of sib2, iclass 34, count 2 2006.285.06:05:36.61#ibcon#*after write, iclass 34, count 2 2006.285.06:05:36.61#ibcon#*before return 0, iclass 34, count 2 2006.285.06:05:36.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:05:36.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:05:36.61#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.06:05:36.61#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:36.61#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:05:36.73#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:05:36.73#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:05:36.73#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:05:36.73#ibcon#first serial, iclass 34, count 0 2006.285.06:05:36.73#ibcon#enter sib2, iclass 34, count 0 2006.285.06:05:36.73#ibcon#flushed, iclass 34, count 0 2006.285.06:05:36.73#ibcon#about to write, iclass 34, count 0 2006.285.06:05:36.73#ibcon#wrote, iclass 34, count 0 2006.285.06:05:36.73#ibcon#about to read 3, iclass 34, count 0 2006.285.06:05:36.75#ibcon#read 3, iclass 34, count 0 2006.285.06:05:36.75#ibcon#about to read 4, iclass 34, count 0 2006.285.06:05:36.75#ibcon#read 4, iclass 34, count 0 2006.285.06:05:36.75#ibcon#about to read 5, iclass 34, count 0 2006.285.06:05:36.75#ibcon#read 5, iclass 34, count 0 2006.285.06:05:36.75#ibcon#about to read 6, iclass 34, count 0 2006.285.06:05:36.75#ibcon#read 6, iclass 34, count 0 2006.285.06:05:36.75#ibcon#end of sib2, iclass 34, count 0 2006.285.06:05:36.75#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:05:36.75#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:05:36.75#ibcon#[27=USB\r\n] 2006.285.06:05:36.75#ibcon#*before write, iclass 34, count 0 2006.285.06:05:36.75#ibcon#enter sib2, iclass 34, count 0 2006.285.06:05:36.75#ibcon#flushed, iclass 34, count 0 2006.285.06:05:36.75#ibcon#about to write, iclass 34, count 0 2006.285.06:05:36.75#ibcon#wrote, iclass 34, count 0 2006.285.06:05:36.75#ibcon#about to read 3, iclass 34, count 0 2006.285.06:05:36.78#ibcon#read 3, iclass 34, count 0 2006.285.06:05:36.78#ibcon#about to read 4, iclass 34, count 0 2006.285.06:05:36.78#ibcon#read 4, iclass 34, count 0 2006.285.06:05:36.78#ibcon#about to read 5, iclass 34, count 0 2006.285.06:05:36.78#ibcon#read 5, iclass 34, count 0 2006.285.06:05:36.78#ibcon#about to read 6, iclass 34, count 0 2006.285.06:05:36.78#ibcon#read 6, iclass 34, count 0 2006.285.06:05:36.78#ibcon#end of sib2, iclass 34, count 0 2006.285.06:05:36.78#ibcon#*after write, iclass 34, count 0 2006.285.06:05:36.78#ibcon#*before return 0, iclass 34, count 0 2006.285.06:05:36.78#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:05:36.78#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:05:36.78#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:05:36.78#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:05:36.78$vck44/vblo=8,744.99 2006.285.06:05:36.78#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.06:05:36.78#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.06:05:36.78#ibcon#ireg 17 cls_cnt 0 2006.285.06:05:36.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:05:36.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:05:36.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:05:36.78#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:05:36.78#ibcon#first serial, iclass 36, count 0 2006.285.06:05:36.78#ibcon#enter sib2, iclass 36, count 0 2006.285.06:05:36.78#ibcon#flushed, iclass 36, count 0 2006.285.06:05:36.78#ibcon#about to write, iclass 36, count 0 2006.285.06:05:36.78#ibcon#wrote, iclass 36, count 0 2006.285.06:05:36.78#ibcon#about to read 3, iclass 36, count 0 2006.285.06:05:36.80#ibcon#read 3, iclass 36, count 0 2006.285.06:05:36.80#ibcon#about to read 4, iclass 36, count 0 2006.285.06:05:36.80#ibcon#read 4, iclass 36, count 0 2006.285.06:05:36.80#ibcon#about to read 5, iclass 36, count 0 2006.285.06:05:36.80#ibcon#read 5, iclass 36, count 0 2006.285.06:05:36.80#ibcon#about to read 6, iclass 36, count 0 2006.285.06:05:36.80#ibcon#read 6, iclass 36, count 0 2006.285.06:05:36.80#ibcon#end of sib2, iclass 36, count 0 2006.285.06:05:36.80#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:05:36.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:05:36.80#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:05:36.80#ibcon#*before write, iclass 36, count 0 2006.285.06:05:36.80#ibcon#enter sib2, iclass 36, count 0 2006.285.06:05:36.80#ibcon#flushed, iclass 36, count 0 2006.285.06:05:36.80#ibcon#about to write, iclass 36, count 0 2006.285.06:05:36.80#ibcon#wrote, iclass 36, count 0 2006.285.06:05:36.80#ibcon#about to read 3, iclass 36, count 0 2006.285.06:05:36.84#ibcon#read 3, iclass 36, count 0 2006.285.06:05:36.84#ibcon#about to read 4, iclass 36, count 0 2006.285.06:05:36.84#ibcon#read 4, iclass 36, count 0 2006.285.06:05:36.84#ibcon#about to read 5, iclass 36, count 0 2006.285.06:05:36.84#ibcon#read 5, iclass 36, count 0 2006.285.06:05:36.84#ibcon#about to read 6, iclass 36, count 0 2006.285.06:05:36.84#ibcon#read 6, iclass 36, count 0 2006.285.06:05:36.84#ibcon#end of sib2, iclass 36, count 0 2006.285.06:05:36.84#ibcon#*after write, iclass 36, count 0 2006.285.06:05:36.84#ibcon#*before return 0, iclass 36, count 0 2006.285.06:05:36.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:05:36.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:05:36.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:05:36.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:05:36.84$vck44/vb=8,4 2006.285.06:05:36.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.06:05:36.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.06:05:36.84#ibcon#ireg 11 cls_cnt 2 2006.285.06:05:36.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:05:36.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:05:36.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:05:36.90#ibcon#enter wrdev, iclass 38, count 2 2006.285.06:05:36.90#ibcon#first serial, iclass 38, count 2 2006.285.06:05:36.90#ibcon#enter sib2, iclass 38, count 2 2006.285.06:05:36.90#ibcon#flushed, iclass 38, count 2 2006.285.06:05:36.90#ibcon#about to write, iclass 38, count 2 2006.285.06:05:36.90#ibcon#wrote, iclass 38, count 2 2006.285.06:05:36.90#ibcon#about to read 3, iclass 38, count 2 2006.285.06:05:36.92#ibcon#read 3, iclass 38, count 2 2006.285.06:05:36.92#ibcon#about to read 4, iclass 38, count 2 2006.285.06:05:36.92#ibcon#read 4, iclass 38, count 2 2006.285.06:05:36.92#ibcon#about to read 5, iclass 38, count 2 2006.285.06:05:36.92#ibcon#read 5, iclass 38, count 2 2006.285.06:05:36.92#ibcon#about to read 6, iclass 38, count 2 2006.285.06:05:36.92#ibcon#read 6, iclass 38, count 2 2006.285.06:05:36.92#ibcon#end of sib2, iclass 38, count 2 2006.285.06:05:36.92#ibcon#*mode == 0, iclass 38, count 2 2006.285.06:05:36.92#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.06:05:36.92#ibcon#[27=AT08-04\r\n] 2006.285.06:05:36.92#ibcon#*before write, iclass 38, count 2 2006.285.06:05:36.92#ibcon#enter sib2, iclass 38, count 2 2006.285.06:05:36.92#ibcon#flushed, iclass 38, count 2 2006.285.06:05:36.92#ibcon#about to write, iclass 38, count 2 2006.285.06:05:36.92#ibcon#wrote, iclass 38, count 2 2006.285.06:05:36.92#ibcon#about to read 3, iclass 38, count 2 2006.285.06:05:36.95#ibcon#read 3, iclass 38, count 2 2006.285.06:05:36.95#ibcon#about to read 4, iclass 38, count 2 2006.285.06:05:36.95#ibcon#read 4, iclass 38, count 2 2006.285.06:05:36.95#ibcon#about to read 5, iclass 38, count 2 2006.285.06:05:36.95#ibcon#read 5, iclass 38, count 2 2006.285.06:05:36.95#ibcon#about to read 6, iclass 38, count 2 2006.285.06:05:36.95#ibcon#read 6, iclass 38, count 2 2006.285.06:05:36.95#ibcon#end of sib2, iclass 38, count 2 2006.285.06:05:36.95#ibcon#*after write, iclass 38, count 2 2006.285.06:05:36.95#ibcon#*before return 0, iclass 38, count 2 2006.285.06:05:36.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:05:36.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:05:36.95#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.06:05:36.95#ibcon#ireg 7 cls_cnt 0 2006.285.06:05:36.95#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:05:37.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:05:37.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:05:37.07#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:05:37.07#ibcon#first serial, iclass 38, count 0 2006.285.06:05:37.07#ibcon#enter sib2, iclass 38, count 0 2006.285.06:05:37.07#ibcon#flushed, iclass 38, count 0 2006.285.06:05:37.07#ibcon#about to write, iclass 38, count 0 2006.285.06:05:37.07#ibcon#wrote, iclass 38, count 0 2006.285.06:05:37.07#ibcon#about to read 3, iclass 38, count 0 2006.285.06:05:37.09#ibcon#read 3, iclass 38, count 0 2006.285.06:05:37.09#ibcon#about to read 4, iclass 38, count 0 2006.285.06:05:37.09#ibcon#read 4, iclass 38, count 0 2006.285.06:05:37.09#ibcon#about to read 5, iclass 38, count 0 2006.285.06:05:37.09#ibcon#read 5, iclass 38, count 0 2006.285.06:05:37.09#ibcon#about to read 6, iclass 38, count 0 2006.285.06:05:37.09#ibcon#read 6, iclass 38, count 0 2006.285.06:05:37.09#ibcon#end of sib2, iclass 38, count 0 2006.285.06:05:37.09#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:05:37.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:05:37.09#ibcon#[27=USB\r\n] 2006.285.06:05:37.09#ibcon#*before write, iclass 38, count 0 2006.285.06:05:37.09#ibcon#enter sib2, iclass 38, count 0 2006.285.06:05:37.09#ibcon#flushed, iclass 38, count 0 2006.285.06:05:37.09#ibcon#about to write, iclass 38, count 0 2006.285.06:05:37.09#ibcon#wrote, iclass 38, count 0 2006.285.06:05:37.09#ibcon#about to read 3, iclass 38, count 0 2006.285.06:05:37.12#ibcon#read 3, iclass 38, count 0 2006.285.06:05:37.12#ibcon#about to read 4, iclass 38, count 0 2006.285.06:05:37.12#ibcon#read 4, iclass 38, count 0 2006.285.06:05:37.12#ibcon#about to read 5, iclass 38, count 0 2006.285.06:05:37.12#ibcon#read 5, iclass 38, count 0 2006.285.06:05:37.12#ibcon#about to read 6, iclass 38, count 0 2006.285.06:05:37.12#ibcon#read 6, iclass 38, count 0 2006.285.06:05:37.12#ibcon#end of sib2, iclass 38, count 0 2006.285.06:05:37.12#ibcon#*after write, iclass 38, count 0 2006.285.06:05:37.12#ibcon#*before return 0, iclass 38, count 0 2006.285.06:05:37.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:05:37.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:05:37.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:05:37.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:05:37.12$vck44/vabw=wide 2006.285.06:05:37.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.06:05:37.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.06:05:37.12#ibcon#ireg 8 cls_cnt 0 2006.285.06:05:37.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:05:37.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:05:37.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:05:37.12#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:05:37.12#ibcon#first serial, iclass 40, count 0 2006.285.06:05:37.12#ibcon#enter sib2, iclass 40, count 0 2006.285.06:05:37.12#ibcon#flushed, iclass 40, count 0 2006.285.06:05:37.12#ibcon#about to write, iclass 40, count 0 2006.285.06:05:37.12#ibcon#wrote, iclass 40, count 0 2006.285.06:05:37.12#ibcon#about to read 3, iclass 40, count 0 2006.285.06:05:37.14#ibcon#read 3, iclass 40, count 0 2006.285.06:05:37.14#ibcon#about to read 4, iclass 40, count 0 2006.285.06:05:37.14#ibcon#read 4, iclass 40, count 0 2006.285.06:05:37.14#ibcon#about to read 5, iclass 40, count 0 2006.285.06:05:37.14#ibcon#read 5, iclass 40, count 0 2006.285.06:05:37.14#ibcon#about to read 6, iclass 40, count 0 2006.285.06:05:37.14#ibcon#read 6, iclass 40, count 0 2006.285.06:05:37.14#ibcon#end of sib2, iclass 40, count 0 2006.285.06:05:37.14#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:05:37.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:05:37.14#ibcon#[25=BW32\r\n] 2006.285.06:05:37.14#ibcon#*before write, iclass 40, count 0 2006.285.06:05:37.14#ibcon#enter sib2, iclass 40, count 0 2006.285.06:05:37.14#ibcon#flushed, iclass 40, count 0 2006.285.06:05:37.14#ibcon#about to write, iclass 40, count 0 2006.285.06:05:37.14#ibcon#wrote, iclass 40, count 0 2006.285.06:05:37.14#ibcon#about to read 3, iclass 40, count 0 2006.285.06:05:37.17#ibcon#read 3, iclass 40, count 0 2006.285.06:05:37.17#ibcon#about to read 4, iclass 40, count 0 2006.285.06:05:37.17#ibcon#read 4, iclass 40, count 0 2006.285.06:05:37.17#ibcon#about to read 5, iclass 40, count 0 2006.285.06:05:37.17#ibcon#read 5, iclass 40, count 0 2006.285.06:05:37.17#ibcon#about to read 6, iclass 40, count 0 2006.285.06:05:37.17#ibcon#read 6, iclass 40, count 0 2006.285.06:05:37.17#ibcon#end of sib2, iclass 40, count 0 2006.285.06:05:37.17#ibcon#*after write, iclass 40, count 0 2006.285.06:05:37.17#ibcon#*before return 0, iclass 40, count 0 2006.285.06:05:37.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:05:37.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:05:37.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:05:37.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:05:37.17$vck44/vbbw=wide 2006.285.06:05:37.17#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.06:05:37.17#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.06:05:37.17#ibcon#ireg 8 cls_cnt 0 2006.285.06:05:37.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:05:37.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:05:37.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:05:37.25#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:05:37.25#ibcon#first serial, iclass 4, count 0 2006.285.06:05:37.25#ibcon#enter sib2, iclass 4, count 0 2006.285.06:05:37.25#ibcon#flushed, iclass 4, count 0 2006.285.06:05:37.25#ibcon#about to write, iclass 4, count 0 2006.285.06:05:37.25#ibcon#wrote, iclass 4, count 0 2006.285.06:05:37.25#ibcon#about to read 3, iclass 4, count 0 2006.285.06:05:37.26#ibcon#read 3, iclass 4, count 0 2006.285.06:05:37.26#ibcon#about to read 4, iclass 4, count 0 2006.285.06:05:37.26#ibcon#read 4, iclass 4, count 0 2006.285.06:05:37.26#ibcon#about to read 5, iclass 4, count 0 2006.285.06:05:37.26#ibcon#read 5, iclass 4, count 0 2006.285.06:05:37.26#ibcon#about to read 6, iclass 4, count 0 2006.285.06:05:37.26#ibcon#read 6, iclass 4, count 0 2006.285.06:05:37.26#ibcon#end of sib2, iclass 4, count 0 2006.285.06:05:37.26#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:05:37.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:05:37.26#ibcon#[27=BW32\r\n] 2006.285.06:05:37.26#ibcon#*before write, iclass 4, count 0 2006.285.06:05:37.26#ibcon#enter sib2, iclass 4, count 0 2006.285.06:05:37.26#ibcon#flushed, iclass 4, count 0 2006.285.06:05:37.26#ibcon#about to write, iclass 4, count 0 2006.285.06:05:37.26#ibcon#wrote, iclass 4, count 0 2006.285.06:05:37.26#ibcon#about to read 3, iclass 4, count 0 2006.285.06:05:37.29#ibcon#read 3, iclass 4, count 0 2006.285.06:05:37.29#ibcon#about to read 4, iclass 4, count 0 2006.285.06:05:37.29#ibcon#read 4, iclass 4, count 0 2006.285.06:05:37.29#ibcon#about to read 5, iclass 4, count 0 2006.285.06:05:37.29#ibcon#read 5, iclass 4, count 0 2006.285.06:05:37.29#ibcon#about to read 6, iclass 4, count 0 2006.285.06:05:37.29#ibcon#read 6, iclass 4, count 0 2006.285.06:05:37.29#ibcon#end of sib2, iclass 4, count 0 2006.285.06:05:37.29#ibcon#*after write, iclass 4, count 0 2006.285.06:05:37.29#ibcon#*before return 0, iclass 4, count 0 2006.285.06:05:37.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:05:37.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:05:37.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:05:37.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:05:37.29$setupk4/ifdk4 2006.285.06:05:37.29$ifdk4/lo= 2006.285.06:05:37.29$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:05:37.29$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:05:37.29$ifdk4/patch= 2006.285.06:05:37.29$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:05:37.29$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:05:37.29$setupk4/!*+20s 2006.285.06:05:45.19#abcon#<5=/04 4.1 6.8 25.07 681014.0\r\n> 2006.285.06:05:45.21#abcon#{5=INTERFACE CLEAR} 2006.285.06:05:45.27#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:05:51.78$setupk4/"tpicd 2006.285.06:05:51.78$setupk4/echo=off 2006.285.06:05:51.78$setupk4/xlog=off 2006.285.06:05:51.78:!2006.285.06:06:56 2006.285.06:05:56.13#trakl#Source acquired 2006.285.06:05:57.13#flagr#flagr/antenna,acquired 2006.285.06:06:56.00:preob 2006.285.06:06:56.13/onsource/TRACKING 2006.285.06:06:56.13:!2006.285.06:07:06 2006.285.06:07:06.00:"tape 2006.285.06:07:06.00:"st=record 2006.285.06:07:06.00:data_valid=on 2006.285.06:07:06.00:midob 2006.285.06:07:06.13/onsource/TRACKING 2006.285.06:07:06.13/wx/25.07,1014.0,68 2006.285.06:07:06.19/cable/+6.4761E-03 2006.285.06:07:07.28/va/01,07,usb,yes,32,35 2006.285.06:07:07.28/va/02,06,usb,yes,33,33 2006.285.06:07:07.28/va/03,07,usb,yes,32,34 2006.285.06:07:07.28/va/04,06,usb,yes,33,35 2006.285.06:07:07.28/va/05,03,usb,yes,33,33 2006.285.06:07:07.28/va/06,04,usb,yes,30,29 2006.285.06:07:07.28/va/07,04,usb,yes,30,31 2006.285.06:07:07.28/va/08,03,usb,yes,31,38 2006.285.06:07:07.51/valo/01,524.99,yes,locked 2006.285.06:07:07.51/valo/02,534.99,yes,locked 2006.285.06:07:07.51/valo/03,564.99,yes,locked 2006.285.06:07:07.51/valo/04,624.99,yes,locked 2006.285.06:07:07.51/valo/05,734.99,yes,locked 2006.285.06:07:07.51/valo/06,814.99,yes,locked 2006.285.06:07:07.51/valo/07,864.99,yes,locked 2006.285.06:07:07.51/valo/08,884.99,yes,locked 2006.285.06:07:08.60/vb/01,04,usb,yes,31,29 2006.285.06:07:08.60/vb/02,05,usb,yes,30,29 2006.285.06:07:08.60/vb/03,04,usb,yes,31,34 2006.285.06:07:08.60/vb/04,05,usb,yes,31,30 2006.285.06:07:08.60/vb/05,04,usb,yes,27,30 2006.285.06:07:08.60/vb/06,03,usb,yes,39,35 2006.285.06:07:08.60/vb/07,04,usb,yes,32,32 2006.285.06:07:08.60/vb/08,04,usb,yes,29,32 2006.285.06:07:08.84/vblo/01,629.99,yes,locked 2006.285.06:07:08.84/vblo/02,634.99,yes,locked 2006.285.06:07:08.84/vblo/03,649.99,yes,locked 2006.285.06:07:08.84/vblo/04,679.99,yes,locked 2006.285.06:07:08.84/vblo/05,709.99,yes,locked 2006.285.06:07:08.84/vblo/06,719.99,yes,locked 2006.285.06:07:08.84/vblo/07,734.99,yes,locked 2006.285.06:07:08.84/vblo/08,744.99,yes,locked 2006.285.06:07:08.99/vabw/8 2006.285.06:07:09.14/vbbw/8 2006.285.06:07:09.23/xfe/off,on,12.2 2006.285.06:07:09.60/ifatt/23,28,28,28 2006.285.06:07:10.07/fmout-gps/S +2.74E-07 2006.285.06:07:10.09:!2006.285.06:11:46 2006.285.06:11:00.14#trakl#Off source 2006.285.06:11:00.14?ERROR st -7 Antenna off-source! 2006.285.06:11:00.14#trakl#az 187.123 el 28.053 azerr*cos(el) 0.0168 elerr -0.0042 2006.285.06:11:02.14#flagr#flagr/antenna,off-source 2006.285.06:11:06.14#trakl#Source re-acquired 2006.285.06:11:08.14#flagr#flagr/antenna,re-acquired 2006.285.06:11:46.00:data_valid=off 2006.285.06:11:46.00:"et 2006.285.06:11:46.00:!+3s 2006.285.06:11:49.01:"tape 2006.285.06:11:49.01:postob 2006.285.06:11:49.07/cable/+6.4765E-03 2006.285.06:11:49.07/wx/25.06,1014.0,67 2006.285.06:11:50.07/fmout-gps/S +2.70E-07 2006.285.06:11:50.07:scan_name=285-0615,jd0610,40 2006.285.06:11:50.07:source=3c345,164258.81,394837.0,2000.0,ccw 2006.285.06:11:51.14#flagr#flagr/antenna,new-source 2006.285.06:11:51.14:checkk5 2006.285.06:11:51.50/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:11:51.87/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:11:52.30/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:11:52.91/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:11:53.30/chk_obsdata//k5ts1/T2850607??a.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.285.06:11:53.66/chk_obsdata//k5ts2/T2850607??b.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.285.06:11:54.09/chk_obsdata//k5ts3/T2850607??c.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.285.06:11:54.52/chk_obsdata//k5ts4/T2850607??d.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.285.06:11:55.21/k5log//k5ts1_log_newline 2006.285.06:11:56.01/k5log//k5ts2_log_newline 2006.285.06:11:56.98/k5log//k5ts3_log_newline 2006.285.06:11:57.73/k5log//k5ts4_log_newline 2006.285.06:11:57.76/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:11:57.76:setupk4=1 2006.285.06:11:57.76$setupk4/echo=on 2006.285.06:11:57.76$setupk4/pcalon 2006.285.06:11:57.76$pcalon/"no phase cal control is implemented here 2006.285.06:11:57.76$setupk4/"tpicd=stop 2006.285.06:11:57.76$setupk4/"rec=synch_on 2006.285.06:11:57.76$setupk4/"rec_mode=128 2006.285.06:11:57.76$setupk4/!* 2006.285.06:11:57.76$setupk4/recpk4 2006.285.06:11:57.76$recpk4/recpatch= 2006.285.06:11:57.76$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:11:57.76$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:11:57.76$setupk4/vck44 2006.285.06:11:57.76$vck44/valo=1,524.99 2006.285.06:11:57.76#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.06:11:57.76#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.06:11:57.76#ibcon#ireg 17 cls_cnt 0 2006.285.06:11:57.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:11:57.76#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:11:57.76#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:11:57.76#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:11:57.76#ibcon#first serial, iclass 17, count 0 2006.285.06:11:57.76#ibcon#enter sib2, iclass 17, count 0 2006.285.06:11:57.76#ibcon#flushed, iclass 17, count 0 2006.285.06:11:57.76#ibcon#about to write, iclass 17, count 0 2006.285.06:11:57.76#ibcon#wrote, iclass 17, count 0 2006.285.06:11:57.76#ibcon#about to read 3, iclass 17, count 0 2006.285.06:11:57.78#ibcon#read 3, iclass 17, count 0 2006.285.06:11:57.78#ibcon#about to read 4, iclass 17, count 0 2006.285.06:11:57.78#ibcon#read 4, iclass 17, count 0 2006.285.06:11:57.78#ibcon#about to read 5, iclass 17, count 0 2006.285.06:11:57.78#ibcon#read 5, iclass 17, count 0 2006.285.06:11:57.78#ibcon#about to read 6, iclass 17, count 0 2006.285.06:11:57.78#ibcon#read 6, iclass 17, count 0 2006.285.06:11:57.78#ibcon#end of sib2, iclass 17, count 0 2006.285.06:11:57.78#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:11:57.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:11:57.78#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:11:57.78#ibcon#*before write, iclass 17, count 0 2006.285.06:11:57.78#ibcon#enter sib2, iclass 17, count 0 2006.285.06:11:57.78#ibcon#flushed, iclass 17, count 0 2006.285.06:11:57.78#ibcon#about to write, iclass 17, count 0 2006.285.06:11:57.78#ibcon#wrote, iclass 17, count 0 2006.285.06:11:57.78#ibcon#about to read 3, iclass 17, count 0 2006.285.06:11:57.83#ibcon#read 3, iclass 17, count 0 2006.285.06:11:57.83#ibcon#about to read 4, iclass 17, count 0 2006.285.06:11:57.83#ibcon#read 4, iclass 17, count 0 2006.285.06:11:57.83#ibcon#about to read 5, iclass 17, count 0 2006.285.06:11:57.83#ibcon#read 5, iclass 17, count 0 2006.285.06:11:57.83#ibcon#about to read 6, iclass 17, count 0 2006.285.06:11:57.83#ibcon#read 6, iclass 17, count 0 2006.285.06:11:57.83#ibcon#end of sib2, iclass 17, count 0 2006.285.06:11:57.83#ibcon#*after write, iclass 17, count 0 2006.285.06:11:57.83#ibcon#*before return 0, iclass 17, count 0 2006.285.06:11:57.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:11:57.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:11:57.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:11:57.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:11:57.83$vck44/va=1,7 2006.285.06:11:57.83#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.06:11:57.83#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.06:11:57.83#ibcon#ireg 11 cls_cnt 2 2006.285.06:11:57.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:11:57.83#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:11:57.83#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:11:57.83#ibcon#enter wrdev, iclass 19, count 2 2006.285.06:11:57.83#ibcon#first serial, iclass 19, count 2 2006.285.06:11:57.83#ibcon#enter sib2, iclass 19, count 2 2006.285.06:11:57.83#ibcon#flushed, iclass 19, count 2 2006.285.06:11:57.83#ibcon#about to write, iclass 19, count 2 2006.285.06:11:57.83#ibcon#wrote, iclass 19, count 2 2006.285.06:11:57.83#ibcon#about to read 3, iclass 19, count 2 2006.285.06:11:57.85#ibcon#read 3, iclass 19, count 2 2006.285.06:11:57.85#ibcon#about to read 4, iclass 19, count 2 2006.285.06:11:57.85#ibcon#read 4, iclass 19, count 2 2006.285.06:11:57.85#ibcon#about to read 5, iclass 19, count 2 2006.285.06:11:57.85#ibcon#read 5, iclass 19, count 2 2006.285.06:11:57.85#ibcon#about to read 6, iclass 19, count 2 2006.285.06:11:57.85#ibcon#read 6, iclass 19, count 2 2006.285.06:11:57.85#ibcon#end of sib2, iclass 19, count 2 2006.285.06:11:57.85#ibcon#*mode == 0, iclass 19, count 2 2006.285.06:11:57.85#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.06:11:57.85#ibcon#[25=AT01-07\r\n] 2006.285.06:11:57.85#ibcon#*before write, iclass 19, count 2 2006.285.06:11:57.85#ibcon#enter sib2, iclass 19, count 2 2006.285.06:11:57.85#ibcon#flushed, iclass 19, count 2 2006.285.06:11:57.85#ibcon#about to write, iclass 19, count 2 2006.285.06:11:57.85#ibcon#wrote, iclass 19, count 2 2006.285.06:11:57.85#ibcon#about to read 3, iclass 19, count 2 2006.285.06:11:57.88#ibcon#read 3, iclass 19, count 2 2006.285.06:11:57.88#ibcon#about to read 4, iclass 19, count 2 2006.285.06:11:57.88#ibcon#read 4, iclass 19, count 2 2006.285.06:11:57.88#ibcon#about to read 5, iclass 19, count 2 2006.285.06:11:57.88#ibcon#read 5, iclass 19, count 2 2006.285.06:11:57.88#ibcon#about to read 6, iclass 19, count 2 2006.285.06:11:57.88#ibcon#read 6, iclass 19, count 2 2006.285.06:11:57.88#ibcon#end of sib2, iclass 19, count 2 2006.285.06:11:57.88#ibcon#*after write, iclass 19, count 2 2006.285.06:11:57.88#ibcon#*before return 0, iclass 19, count 2 2006.285.06:11:57.88#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:11:57.88#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:11:57.88#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.06:11:57.88#ibcon#ireg 7 cls_cnt 0 2006.285.06:11:57.88#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:11:58.01#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:11:58.01#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:11:58.01#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:11:58.01#ibcon#first serial, iclass 19, count 0 2006.285.06:11:58.01#ibcon#enter sib2, iclass 19, count 0 2006.285.06:11:58.01#ibcon#flushed, iclass 19, count 0 2006.285.06:11:58.01#ibcon#about to write, iclass 19, count 0 2006.285.06:11:58.01#ibcon#wrote, iclass 19, count 0 2006.285.06:11:58.01#ibcon#about to read 3, iclass 19, count 0 2006.285.06:11:58.02#ibcon#read 3, iclass 19, count 0 2006.285.06:11:58.02#ibcon#about to read 4, iclass 19, count 0 2006.285.06:11:58.02#ibcon#read 4, iclass 19, count 0 2006.285.06:11:58.02#ibcon#about to read 5, iclass 19, count 0 2006.285.06:11:58.02#ibcon#read 5, iclass 19, count 0 2006.285.06:11:58.02#ibcon#about to read 6, iclass 19, count 0 2006.285.06:11:58.02#ibcon#read 6, iclass 19, count 0 2006.285.06:11:58.02#ibcon#end of sib2, iclass 19, count 0 2006.285.06:11:58.02#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:11:58.02#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:11:58.02#ibcon#[25=USB\r\n] 2006.285.06:11:58.02#ibcon#*before write, iclass 19, count 0 2006.285.06:11:58.02#ibcon#enter sib2, iclass 19, count 0 2006.285.06:11:58.02#ibcon#flushed, iclass 19, count 0 2006.285.06:11:58.02#ibcon#about to write, iclass 19, count 0 2006.285.06:11:58.02#ibcon#wrote, iclass 19, count 0 2006.285.06:11:58.02#ibcon#about to read 3, iclass 19, count 0 2006.285.06:11:58.05#ibcon#read 3, iclass 19, count 0 2006.285.06:11:58.05#ibcon#about to read 4, iclass 19, count 0 2006.285.06:11:58.05#ibcon#read 4, iclass 19, count 0 2006.285.06:11:58.05#ibcon#about to read 5, iclass 19, count 0 2006.285.06:11:58.05#ibcon#read 5, iclass 19, count 0 2006.285.06:11:58.05#ibcon#about to read 6, iclass 19, count 0 2006.285.06:11:58.05#ibcon#read 6, iclass 19, count 0 2006.285.06:11:58.05#ibcon#end of sib2, iclass 19, count 0 2006.285.06:11:58.05#ibcon#*after write, iclass 19, count 0 2006.285.06:11:58.05#ibcon#*before return 0, iclass 19, count 0 2006.285.06:11:58.05#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:11:58.05#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:11:58.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:11:58.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:11:58.05$vck44/valo=2,534.99 2006.285.06:11:58.05#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.06:11:58.05#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.06:11:58.05#ibcon#ireg 17 cls_cnt 0 2006.285.06:11:58.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:11:58.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:11:58.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:11:58.05#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:11:58.05#ibcon#first serial, iclass 21, count 0 2006.285.06:11:58.05#ibcon#enter sib2, iclass 21, count 0 2006.285.06:11:58.05#ibcon#flushed, iclass 21, count 0 2006.285.06:11:58.05#ibcon#about to write, iclass 21, count 0 2006.285.06:11:58.05#ibcon#wrote, iclass 21, count 0 2006.285.06:11:58.05#ibcon#about to read 3, iclass 21, count 0 2006.285.06:11:58.07#ibcon#read 3, iclass 21, count 0 2006.285.06:11:58.07#ibcon#about to read 4, iclass 21, count 0 2006.285.06:11:58.07#ibcon#read 4, iclass 21, count 0 2006.285.06:11:58.07#ibcon#about to read 5, iclass 21, count 0 2006.285.06:11:58.07#ibcon#read 5, iclass 21, count 0 2006.285.06:11:58.07#ibcon#about to read 6, iclass 21, count 0 2006.285.06:11:58.07#ibcon#read 6, iclass 21, count 0 2006.285.06:11:58.07#ibcon#end of sib2, iclass 21, count 0 2006.285.06:11:58.07#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:11:58.07#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:11:58.07#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:11:58.07#ibcon#*before write, iclass 21, count 0 2006.285.06:11:58.07#ibcon#enter sib2, iclass 21, count 0 2006.285.06:11:58.07#ibcon#flushed, iclass 21, count 0 2006.285.06:11:58.07#ibcon#about to write, iclass 21, count 0 2006.285.06:11:58.07#ibcon#wrote, iclass 21, count 0 2006.285.06:11:58.07#ibcon#about to read 3, iclass 21, count 0 2006.285.06:11:58.11#ibcon#read 3, iclass 21, count 0 2006.285.06:11:58.11#ibcon#about to read 4, iclass 21, count 0 2006.285.06:11:58.11#ibcon#read 4, iclass 21, count 0 2006.285.06:11:58.11#ibcon#about to read 5, iclass 21, count 0 2006.285.06:11:58.11#ibcon#read 5, iclass 21, count 0 2006.285.06:11:58.11#ibcon#about to read 6, iclass 21, count 0 2006.285.06:11:58.11#ibcon#read 6, iclass 21, count 0 2006.285.06:11:58.11#ibcon#end of sib2, iclass 21, count 0 2006.285.06:11:58.11#ibcon#*after write, iclass 21, count 0 2006.285.06:11:58.11#ibcon#*before return 0, iclass 21, count 0 2006.285.06:11:58.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:11:58.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:11:58.11#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:11:58.11#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:11:58.11$vck44/va=2,6 2006.285.06:11:58.11#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.06:11:58.11#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.06:11:58.11#ibcon#ireg 11 cls_cnt 2 2006.285.06:11:58.11#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:11:58.17#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:11:58.17#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:11:58.17#ibcon#enter wrdev, iclass 23, count 2 2006.285.06:11:58.17#ibcon#first serial, iclass 23, count 2 2006.285.06:11:58.17#ibcon#enter sib2, iclass 23, count 2 2006.285.06:11:58.17#ibcon#flushed, iclass 23, count 2 2006.285.06:11:58.17#ibcon#about to write, iclass 23, count 2 2006.285.06:11:58.17#ibcon#wrote, iclass 23, count 2 2006.285.06:11:58.17#ibcon#about to read 3, iclass 23, count 2 2006.285.06:11:58.19#ibcon#read 3, iclass 23, count 2 2006.285.06:11:58.19#ibcon#about to read 4, iclass 23, count 2 2006.285.06:11:58.19#ibcon#read 4, iclass 23, count 2 2006.285.06:11:58.19#ibcon#about to read 5, iclass 23, count 2 2006.285.06:11:58.19#ibcon#read 5, iclass 23, count 2 2006.285.06:11:58.19#ibcon#about to read 6, iclass 23, count 2 2006.285.06:11:58.19#ibcon#read 6, iclass 23, count 2 2006.285.06:11:58.19#ibcon#end of sib2, iclass 23, count 2 2006.285.06:11:58.19#ibcon#*mode == 0, iclass 23, count 2 2006.285.06:11:58.19#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.06:11:58.19#ibcon#[25=AT02-06\r\n] 2006.285.06:11:58.19#ibcon#*before write, iclass 23, count 2 2006.285.06:11:58.19#ibcon#enter sib2, iclass 23, count 2 2006.285.06:11:58.19#ibcon#flushed, iclass 23, count 2 2006.285.06:11:58.19#ibcon#about to write, iclass 23, count 2 2006.285.06:11:58.19#ibcon#wrote, iclass 23, count 2 2006.285.06:11:58.19#ibcon#about to read 3, iclass 23, count 2 2006.285.06:11:58.22#ibcon#read 3, iclass 23, count 2 2006.285.06:11:58.22#ibcon#about to read 4, iclass 23, count 2 2006.285.06:11:58.22#ibcon#read 4, iclass 23, count 2 2006.285.06:11:58.22#ibcon#about to read 5, iclass 23, count 2 2006.285.06:11:58.22#ibcon#read 5, iclass 23, count 2 2006.285.06:11:58.22#ibcon#about to read 6, iclass 23, count 2 2006.285.06:11:58.22#ibcon#read 6, iclass 23, count 2 2006.285.06:11:58.22#ibcon#end of sib2, iclass 23, count 2 2006.285.06:11:58.22#ibcon#*after write, iclass 23, count 2 2006.285.06:11:58.22#ibcon#*before return 0, iclass 23, count 2 2006.285.06:11:58.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:11:58.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:11:58.22#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.06:11:58.22#ibcon#ireg 7 cls_cnt 0 2006.285.06:11:58.22#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:11:58.34#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:11:58.34#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:11:58.34#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:11:58.34#ibcon#first serial, iclass 23, count 0 2006.285.06:11:58.34#ibcon#enter sib2, iclass 23, count 0 2006.285.06:11:58.34#ibcon#flushed, iclass 23, count 0 2006.285.06:11:58.34#ibcon#about to write, iclass 23, count 0 2006.285.06:11:58.34#ibcon#wrote, iclass 23, count 0 2006.285.06:11:58.34#ibcon#about to read 3, iclass 23, count 0 2006.285.06:11:58.36#ibcon#read 3, iclass 23, count 0 2006.285.06:11:58.36#ibcon#about to read 4, iclass 23, count 0 2006.285.06:11:58.36#ibcon#read 4, iclass 23, count 0 2006.285.06:11:58.36#ibcon#about to read 5, iclass 23, count 0 2006.285.06:11:58.36#ibcon#read 5, iclass 23, count 0 2006.285.06:11:58.36#ibcon#about to read 6, iclass 23, count 0 2006.285.06:11:58.36#ibcon#read 6, iclass 23, count 0 2006.285.06:11:58.36#ibcon#end of sib2, iclass 23, count 0 2006.285.06:11:58.36#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:11:58.36#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:11:58.36#ibcon#[25=USB\r\n] 2006.285.06:11:58.36#ibcon#*before write, iclass 23, count 0 2006.285.06:11:58.36#ibcon#enter sib2, iclass 23, count 0 2006.285.06:11:58.36#ibcon#flushed, iclass 23, count 0 2006.285.06:11:58.36#ibcon#about to write, iclass 23, count 0 2006.285.06:11:58.36#ibcon#wrote, iclass 23, count 0 2006.285.06:11:58.36#ibcon#about to read 3, iclass 23, count 0 2006.285.06:11:58.39#ibcon#read 3, iclass 23, count 0 2006.285.06:11:58.39#ibcon#about to read 4, iclass 23, count 0 2006.285.06:11:58.39#ibcon#read 4, iclass 23, count 0 2006.285.06:11:58.39#ibcon#about to read 5, iclass 23, count 0 2006.285.06:11:58.39#ibcon#read 5, iclass 23, count 0 2006.285.06:11:58.39#ibcon#about to read 6, iclass 23, count 0 2006.285.06:11:58.39#ibcon#read 6, iclass 23, count 0 2006.285.06:11:58.39#ibcon#end of sib2, iclass 23, count 0 2006.285.06:11:58.39#ibcon#*after write, iclass 23, count 0 2006.285.06:11:58.39#ibcon#*before return 0, iclass 23, count 0 2006.285.06:11:58.39#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:11:58.39#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:11:58.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:11:58.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:11:58.39$vck44/valo=3,564.99 2006.285.06:11:58.39#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.06:11:58.39#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.06:11:58.39#ibcon#ireg 17 cls_cnt 0 2006.285.06:11:58.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:11:58.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:11:58.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:11:58.39#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:11:58.39#ibcon#first serial, iclass 25, count 0 2006.285.06:11:58.39#ibcon#enter sib2, iclass 25, count 0 2006.285.06:11:58.39#ibcon#flushed, iclass 25, count 0 2006.285.06:11:58.39#ibcon#about to write, iclass 25, count 0 2006.285.06:11:58.39#ibcon#wrote, iclass 25, count 0 2006.285.06:11:58.39#ibcon#about to read 3, iclass 25, count 0 2006.285.06:11:58.41#ibcon#read 3, iclass 25, count 0 2006.285.06:11:58.41#ibcon#about to read 4, iclass 25, count 0 2006.285.06:11:58.41#ibcon#read 4, iclass 25, count 0 2006.285.06:11:58.41#ibcon#about to read 5, iclass 25, count 0 2006.285.06:11:58.41#ibcon#read 5, iclass 25, count 0 2006.285.06:11:58.41#ibcon#about to read 6, iclass 25, count 0 2006.285.06:11:58.41#ibcon#read 6, iclass 25, count 0 2006.285.06:11:58.41#ibcon#end of sib2, iclass 25, count 0 2006.285.06:11:58.41#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:11:58.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:11:58.41#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:11:58.41#ibcon#*before write, iclass 25, count 0 2006.285.06:11:58.41#ibcon#enter sib2, iclass 25, count 0 2006.285.06:11:58.41#ibcon#flushed, iclass 25, count 0 2006.285.06:11:58.41#ibcon#about to write, iclass 25, count 0 2006.285.06:11:58.41#ibcon#wrote, iclass 25, count 0 2006.285.06:11:58.41#ibcon#about to read 3, iclass 25, count 0 2006.285.06:11:58.45#ibcon#read 3, iclass 25, count 0 2006.285.06:11:58.45#ibcon#about to read 4, iclass 25, count 0 2006.285.06:11:58.45#ibcon#read 4, iclass 25, count 0 2006.285.06:11:58.45#ibcon#about to read 5, iclass 25, count 0 2006.285.06:11:58.45#ibcon#read 5, iclass 25, count 0 2006.285.06:11:58.45#ibcon#about to read 6, iclass 25, count 0 2006.285.06:11:58.45#ibcon#read 6, iclass 25, count 0 2006.285.06:11:58.45#ibcon#end of sib2, iclass 25, count 0 2006.285.06:11:58.45#ibcon#*after write, iclass 25, count 0 2006.285.06:11:58.45#ibcon#*before return 0, iclass 25, count 0 2006.285.06:11:58.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:11:58.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:11:58.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:11:58.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:11:58.45$vck44/va=3,7 2006.285.06:11:58.45#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.06:11:58.45#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.06:11:58.45#ibcon#ireg 11 cls_cnt 2 2006.285.06:11:58.45#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:11:58.51#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:11:58.51#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:11:58.51#ibcon#enter wrdev, iclass 27, count 2 2006.285.06:11:58.51#ibcon#first serial, iclass 27, count 2 2006.285.06:11:58.51#ibcon#enter sib2, iclass 27, count 2 2006.285.06:11:58.51#ibcon#flushed, iclass 27, count 2 2006.285.06:11:58.51#ibcon#about to write, iclass 27, count 2 2006.285.06:11:58.51#ibcon#wrote, iclass 27, count 2 2006.285.06:11:58.51#ibcon#about to read 3, iclass 27, count 2 2006.285.06:11:58.53#ibcon#read 3, iclass 27, count 2 2006.285.06:11:58.53#ibcon#about to read 4, iclass 27, count 2 2006.285.06:11:58.53#ibcon#read 4, iclass 27, count 2 2006.285.06:11:58.53#ibcon#about to read 5, iclass 27, count 2 2006.285.06:11:58.53#ibcon#read 5, iclass 27, count 2 2006.285.06:11:58.53#ibcon#about to read 6, iclass 27, count 2 2006.285.06:11:58.53#ibcon#read 6, iclass 27, count 2 2006.285.06:11:58.53#ibcon#end of sib2, iclass 27, count 2 2006.285.06:11:58.53#ibcon#*mode == 0, iclass 27, count 2 2006.285.06:11:58.53#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.06:11:58.53#ibcon#[25=AT03-07\r\n] 2006.285.06:11:58.53#ibcon#*before write, iclass 27, count 2 2006.285.06:11:58.53#ibcon#enter sib2, iclass 27, count 2 2006.285.06:11:58.53#ibcon#flushed, iclass 27, count 2 2006.285.06:11:58.53#ibcon#about to write, iclass 27, count 2 2006.285.06:11:58.53#ibcon#wrote, iclass 27, count 2 2006.285.06:11:58.53#ibcon#about to read 3, iclass 27, count 2 2006.285.06:11:58.56#ibcon#read 3, iclass 27, count 2 2006.285.06:11:58.56#ibcon#about to read 4, iclass 27, count 2 2006.285.06:11:58.56#ibcon#read 4, iclass 27, count 2 2006.285.06:11:58.56#ibcon#about to read 5, iclass 27, count 2 2006.285.06:11:58.56#ibcon#read 5, iclass 27, count 2 2006.285.06:11:58.56#ibcon#about to read 6, iclass 27, count 2 2006.285.06:11:58.56#ibcon#read 6, iclass 27, count 2 2006.285.06:11:58.56#ibcon#end of sib2, iclass 27, count 2 2006.285.06:11:58.56#ibcon#*after write, iclass 27, count 2 2006.285.06:11:58.56#ibcon#*before return 0, iclass 27, count 2 2006.285.06:11:58.56#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:11:58.56#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:11:58.56#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.06:11:58.56#ibcon#ireg 7 cls_cnt 0 2006.285.06:11:58.56#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:11:58.68#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:11:58.68#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:11:58.68#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:11:58.68#ibcon#first serial, iclass 27, count 0 2006.285.06:11:58.68#ibcon#enter sib2, iclass 27, count 0 2006.285.06:11:58.68#ibcon#flushed, iclass 27, count 0 2006.285.06:11:58.68#ibcon#about to write, iclass 27, count 0 2006.285.06:11:58.68#ibcon#wrote, iclass 27, count 0 2006.285.06:11:58.68#ibcon#about to read 3, iclass 27, count 0 2006.285.06:11:58.70#ibcon#read 3, iclass 27, count 0 2006.285.06:11:58.70#ibcon#about to read 4, iclass 27, count 0 2006.285.06:11:58.70#ibcon#read 4, iclass 27, count 0 2006.285.06:11:58.70#ibcon#about to read 5, iclass 27, count 0 2006.285.06:11:58.70#ibcon#read 5, iclass 27, count 0 2006.285.06:11:58.70#ibcon#about to read 6, iclass 27, count 0 2006.285.06:11:58.70#ibcon#read 6, iclass 27, count 0 2006.285.06:11:58.70#ibcon#end of sib2, iclass 27, count 0 2006.285.06:11:58.70#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:11:58.70#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:11:58.70#ibcon#[25=USB\r\n] 2006.285.06:11:58.70#ibcon#*before write, iclass 27, count 0 2006.285.06:11:58.70#ibcon#enter sib2, iclass 27, count 0 2006.285.06:11:58.70#ibcon#flushed, iclass 27, count 0 2006.285.06:11:58.70#ibcon#about to write, iclass 27, count 0 2006.285.06:11:58.70#ibcon#wrote, iclass 27, count 0 2006.285.06:11:58.70#ibcon#about to read 3, iclass 27, count 0 2006.285.06:11:58.73#ibcon#read 3, iclass 27, count 0 2006.285.06:11:58.73#ibcon#about to read 4, iclass 27, count 0 2006.285.06:11:58.73#ibcon#read 4, iclass 27, count 0 2006.285.06:11:58.73#ibcon#about to read 5, iclass 27, count 0 2006.285.06:11:58.73#ibcon#read 5, iclass 27, count 0 2006.285.06:11:58.73#ibcon#about to read 6, iclass 27, count 0 2006.285.06:11:58.73#ibcon#read 6, iclass 27, count 0 2006.285.06:11:58.73#ibcon#end of sib2, iclass 27, count 0 2006.285.06:11:58.73#ibcon#*after write, iclass 27, count 0 2006.285.06:11:58.73#ibcon#*before return 0, iclass 27, count 0 2006.285.06:11:58.73#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:11:58.73#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:11:58.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:11:58.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:11:58.73$vck44/valo=4,624.99 2006.285.06:11:58.73#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.06:11:58.73#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.06:11:58.73#ibcon#ireg 17 cls_cnt 0 2006.285.06:11:58.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:11:58.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:11:58.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:11:58.73#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:11:58.73#ibcon#first serial, iclass 29, count 0 2006.285.06:11:58.73#ibcon#enter sib2, iclass 29, count 0 2006.285.06:11:58.73#ibcon#flushed, iclass 29, count 0 2006.285.06:11:58.73#ibcon#about to write, iclass 29, count 0 2006.285.06:11:58.73#ibcon#wrote, iclass 29, count 0 2006.285.06:11:58.73#ibcon#about to read 3, iclass 29, count 0 2006.285.06:11:58.75#ibcon#read 3, iclass 29, count 0 2006.285.06:11:58.75#ibcon#about to read 4, iclass 29, count 0 2006.285.06:11:58.75#ibcon#read 4, iclass 29, count 0 2006.285.06:11:58.75#ibcon#about to read 5, iclass 29, count 0 2006.285.06:11:58.75#ibcon#read 5, iclass 29, count 0 2006.285.06:11:58.75#ibcon#about to read 6, iclass 29, count 0 2006.285.06:11:58.75#ibcon#read 6, iclass 29, count 0 2006.285.06:11:58.75#ibcon#end of sib2, iclass 29, count 0 2006.285.06:11:58.75#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:11:58.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:11:58.75#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:11:58.75#ibcon#*before write, iclass 29, count 0 2006.285.06:11:58.75#ibcon#enter sib2, iclass 29, count 0 2006.285.06:11:58.75#ibcon#flushed, iclass 29, count 0 2006.285.06:11:58.75#ibcon#about to write, iclass 29, count 0 2006.285.06:11:58.75#ibcon#wrote, iclass 29, count 0 2006.285.06:11:58.75#ibcon#about to read 3, iclass 29, count 0 2006.285.06:11:58.79#ibcon#read 3, iclass 29, count 0 2006.285.06:11:58.79#ibcon#about to read 4, iclass 29, count 0 2006.285.06:11:58.79#ibcon#read 4, iclass 29, count 0 2006.285.06:11:58.79#ibcon#about to read 5, iclass 29, count 0 2006.285.06:11:58.79#ibcon#read 5, iclass 29, count 0 2006.285.06:11:58.79#ibcon#about to read 6, iclass 29, count 0 2006.285.06:11:58.79#ibcon#read 6, iclass 29, count 0 2006.285.06:11:58.79#ibcon#end of sib2, iclass 29, count 0 2006.285.06:11:58.79#ibcon#*after write, iclass 29, count 0 2006.285.06:11:58.79#ibcon#*before return 0, iclass 29, count 0 2006.285.06:11:58.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:11:58.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:11:58.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:11:58.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:11:58.79$vck44/va=4,6 2006.285.06:11:58.79#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.06:11:58.79#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.06:11:58.79#ibcon#ireg 11 cls_cnt 2 2006.285.06:11:58.79#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:11:58.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:11:58.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:11:58.85#ibcon#enter wrdev, iclass 31, count 2 2006.285.06:11:58.85#ibcon#first serial, iclass 31, count 2 2006.285.06:11:58.85#ibcon#enter sib2, iclass 31, count 2 2006.285.06:11:58.85#ibcon#flushed, iclass 31, count 2 2006.285.06:11:58.85#ibcon#about to write, iclass 31, count 2 2006.285.06:11:58.85#ibcon#wrote, iclass 31, count 2 2006.285.06:11:58.85#ibcon#about to read 3, iclass 31, count 2 2006.285.06:11:58.87#ibcon#read 3, iclass 31, count 2 2006.285.06:11:58.87#ibcon#about to read 4, iclass 31, count 2 2006.285.06:11:58.87#ibcon#read 4, iclass 31, count 2 2006.285.06:11:58.87#ibcon#about to read 5, iclass 31, count 2 2006.285.06:11:58.87#ibcon#read 5, iclass 31, count 2 2006.285.06:11:58.87#ibcon#about to read 6, iclass 31, count 2 2006.285.06:11:58.87#ibcon#read 6, iclass 31, count 2 2006.285.06:11:58.87#ibcon#end of sib2, iclass 31, count 2 2006.285.06:11:58.87#ibcon#*mode == 0, iclass 31, count 2 2006.285.06:11:58.87#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.06:11:58.87#ibcon#[25=AT04-06\r\n] 2006.285.06:11:58.87#ibcon#*before write, iclass 31, count 2 2006.285.06:11:58.87#ibcon#enter sib2, iclass 31, count 2 2006.285.06:11:58.87#ibcon#flushed, iclass 31, count 2 2006.285.06:11:58.87#ibcon#about to write, iclass 31, count 2 2006.285.06:11:58.87#ibcon#wrote, iclass 31, count 2 2006.285.06:11:58.87#ibcon#about to read 3, iclass 31, count 2 2006.285.06:11:58.90#ibcon#read 3, iclass 31, count 2 2006.285.06:11:58.90#ibcon#about to read 4, iclass 31, count 2 2006.285.06:11:58.90#ibcon#read 4, iclass 31, count 2 2006.285.06:11:58.90#ibcon#about to read 5, iclass 31, count 2 2006.285.06:11:58.90#ibcon#read 5, iclass 31, count 2 2006.285.06:11:58.90#ibcon#about to read 6, iclass 31, count 2 2006.285.06:11:58.90#ibcon#read 6, iclass 31, count 2 2006.285.06:11:58.90#ibcon#end of sib2, iclass 31, count 2 2006.285.06:11:58.90#ibcon#*after write, iclass 31, count 2 2006.285.06:11:58.90#ibcon#*before return 0, iclass 31, count 2 2006.285.06:11:58.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:11:58.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:11:58.90#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.06:11:58.90#ibcon#ireg 7 cls_cnt 0 2006.285.06:11:58.90#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:11:59.03#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:11:59.04#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:11:59.04#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:11:59.04#ibcon#first serial, iclass 31, count 0 2006.285.06:11:59.04#ibcon#enter sib2, iclass 31, count 0 2006.285.06:11:59.04#ibcon#flushed, iclass 31, count 0 2006.285.06:11:59.04#ibcon#about to write, iclass 31, count 0 2006.285.06:11:59.04#ibcon#wrote, iclass 31, count 0 2006.285.06:11:59.04#ibcon#about to read 3, iclass 31, count 0 2006.285.06:11:59.05#ibcon#read 3, iclass 31, count 0 2006.285.06:11:59.05#ibcon#about to read 4, iclass 31, count 0 2006.285.06:11:59.05#ibcon#read 4, iclass 31, count 0 2006.285.06:11:59.05#ibcon#about to read 5, iclass 31, count 0 2006.285.06:11:59.05#ibcon#read 5, iclass 31, count 0 2006.285.06:11:59.05#ibcon#about to read 6, iclass 31, count 0 2006.285.06:11:59.05#ibcon#read 6, iclass 31, count 0 2006.285.06:11:59.05#ibcon#end of sib2, iclass 31, count 0 2006.285.06:11:59.05#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:11:59.05#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:11:59.05#ibcon#[25=USB\r\n] 2006.285.06:11:59.05#ibcon#*before write, iclass 31, count 0 2006.285.06:11:59.05#ibcon#enter sib2, iclass 31, count 0 2006.285.06:11:59.05#ibcon#flushed, iclass 31, count 0 2006.285.06:11:59.05#ibcon#about to write, iclass 31, count 0 2006.285.06:11:59.05#ibcon#wrote, iclass 31, count 0 2006.285.06:11:59.05#ibcon#about to read 3, iclass 31, count 0 2006.285.06:11:59.08#ibcon#read 3, iclass 31, count 0 2006.285.06:11:59.08#ibcon#about to read 4, iclass 31, count 0 2006.285.06:11:59.08#ibcon#read 4, iclass 31, count 0 2006.285.06:11:59.08#ibcon#about to read 5, iclass 31, count 0 2006.285.06:11:59.08#ibcon#read 5, iclass 31, count 0 2006.285.06:11:59.08#ibcon#about to read 6, iclass 31, count 0 2006.285.06:11:59.08#ibcon#read 6, iclass 31, count 0 2006.285.06:11:59.08#ibcon#end of sib2, iclass 31, count 0 2006.285.06:11:59.08#ibcon#*after write, iclass 31, count 0 2006.285.06:11:59.08#ibcon#*before return 0, iclass 31, count 0 2006.285.06:11:59.08#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:11:59.08#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:11:59.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:11:59.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:11:59.08$vck44/valo=5,734.99 2006.285.06:11:59.08#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.06:11:59.08#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.06:11:59.08#ibcon#ireg 17 cls_cnt 0 2006.285.06:11:59.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:11:59.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:11:59.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:11:59.08#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:11:59.08#ibcon#first serial, iclass 33, count 0 2006.285.06:11:59.08#ibcon#enter sib2, iclass 33, count 0 2006.285.06:11:59.08#ibcon#flushed, iclass 33, count 0 2006.285.06:11:59.08#ibcon#about to write, iclass 33, count 0 2006.285.06:11:59.08#ibcon#wrote, iclass 33, count 0 2006.285.06:11:59.08#ibcon#about to read 3, iclass 33, count 0 2006.285.06:11:59.10#ibcon#read 3, iclass 33, count 0 2006.285.06:11:59.10#ibcon#about to read 4, iclass 33, count 0 2006.285.06:11:59.10#ibcon#read 4, iclass 33, count 0 2006.285.06:11:59.10#ibcon#about to read 5, iclass 33, count 0 2006.285.06:11:59.10#ibcon#read 5, iclass 33, count 0 2006.285.06:11:59.10#ibcon#about to read 6, iclass 33, count 0 2006.285.06:11:59.10#ibcon#read 6, iclass 33, count 0 2006.285.06:11:59.10#ibcon#end of sib2, iclass 33, count 0 2006.285.06:11:59.10#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:11:59.10#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:11:59.10#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:11:59.10#ibcon#*before write, iclass 33, count 0 2006.285.06:11:59.10#ibcon#enter sib2, iclass 33, count 0 2006.285.06:11:59.10#ibcon#flushed, iclass 33, count 0 2006.285.06:11:59.10#ibcon#about to write, iclass 33, count 0 2006.285.06:11:59.10#ibcon#wrote, iclass 33, count 0 2006.285.06:11:59.10#ibcon#about to read 3, iclass 33, count 0 2006.285.06:11:59.14#ibcon#read 3, iclass 33, count 0 2006.285.06:11:59.14#ibcon#about to read 4, iclass 33, count 0 2006.285.06:11:59.14#ibcon#read 4, iclass 33, count 0 2006.285.06:11:59.14#ibcon#about to read 5, iclass 33, count 0 2006.285.06:11:59.14#ibcon#read 5, iclass 33, count 0 2006.285.06:11:59.14#ibcon#about to read 6, iclass 33, count 0 2006.285.06:11:59.14#ibcon#read 6, iclass 33, count 0 2006.285.06:11:59.14#ibcon#end of sib2, iclass 33, count 0 2006.285.06:11:59.14#ibcon#*after write, iclass 33, count 0 2006.285.06:11:59.14#ibcon#*before return 0, iclass 33, count 0 2006.285.06:11:59.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:11:59.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:11:59.14#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:11:59.14#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:11:59.14$vck44/va=5,3 2006.285.06:11:59.14#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.06:11:59.14#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.06:11:59.14#ibcon#ireg 11 cls_cnt 2 2006.285.06:11:59.14#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:11:59.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:11:59.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:11:59.20#ibcon#enter wrdev, iclass 35, count 2 2006.285.06:11:59.20#ibcon#first serial, iclass 35, count 2 2006.285.06:11:59.20#ibcon#enter sib2, iclass 35, count 2 2006.285.06:11:59.20#ibcon#flushed, iclass 35, count 2 2006.285.06:11:59.20#ibcon#about to write, iclass 35, count 2 2006.285.06:11:59.20#ibcon#wrote, iclass 35, count 2 2006.285.06:11:59.20#ibcon#about to read 3, iclass 35, count 2 2006.285.06:11:59.22#ibcon#read 3, iclass 35, count 2 2006.285.06:11:59.22#ibcon#about to read 4, iclass 35, count 2 2006.285.06:11:59.22#ibcon#read 4, iclass 35, count 2 2006.285.06:11:59.22#ibcon#about to read 5, iclass 35, count 2 2006.285.06:11:59.22#ibcon#read 5, iclass 35, count 2 2006.285.06:11:59.22#ibcon#about to read 6, iclass 35, count 2 2006.285.06:11:59.22#ibcon#read 6, iclass 35, count 2 2006.285.06:11:59.22#ibcon#end of sib2, iclass 35, count 2 2006.285.06:11:59.22#ibcon#*mode == 0, iclass 35, count 2 2006.285.06:11:59.22#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.06:11:59.22#ibcon#[25=AT05-03\r\n] 2006.285.06:11:59.22#ibcon#*before write, iclass 35, count 2 2006.285.06:11:59.22#ibcon#enter sib2, iclass 35, count 2 2006.285.06:11:59.22#ibcon#flushed, iclass 35, count 2 2006.285.06:11:59.22#ibcon#about to write, iclass 35, count 2 2006.285.06:11:59.22#ibcon#wrote, iclass 35, count 2 2006.285.06:11:59.22#ibcon#about to read 3, iclass 35, count 2 2006.285.06:11:59.25#ibcon#read 3, iclass 35, count 2 2006.285.06:11:59.25#ibcon#about to read 4, iclass 35, count 2 2006.285.06:11:59.25#ibcon#read 4, iclass 35, count 2 2006.285.06:11:59.25#ibcon#about to read 5, iclass 35, count 2 2006.285.06:11:59.25#ibcon#read 5, iclass 35, count 2 2006.285.06:11:59.25#ibcon#about to read 6, iclass 35, count 2 2006.285.06:11:59.25#ibcon#read 6, iclass 35, count 2 2006.285.06:11:59.25#ibcon#end of sib2, iclass 35, count 2 2006.285.06:11:59.25#ibcon#*after write, iclass 35, count 2 2006.285.06:11:59.25#ibcon#*before return 0, iclass 35, count 2 2006.285.06:11:59.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:11:59.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:11:59.25#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.06:11:59.25#ibcon#ireg 7 cls_cnt 0 2006.285.06:11:59.25#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:11:59.37#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:11:59.37#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:11:59.37#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:11:59.37#ibcon#first serial, iclass 35, count 0 2006.285.06:11:59.37#ibcon#enter sib2, iclass 35, count 0 2006.285.06:11:59.37#ibcon#flushed, iclass 35, count 0 2006.285.06:11:59.37#ibcon#about to write, iclass 35, count 0 2006.285.06:11:59.37#ibcon#wrote, iclass 35, count 0 2006.285.06:11:59.37#ibcon#about to read 3, iclass 35, count 0 2006.285.06:11:59.39#ibcon#read 3, iclass 35, count 0 2006.285.06:11:59.39#ibcon#about to read 4, iclass 35, count 0 2006.285.06:11:59.39#ibcon#read 4, iclass 35, count 0 2006.285.06:11:59.39#ibcon#about to read 5, iclass 35, count 0 2006.285.06:11:59.39#ibcon#read 5, iclass 35, count 0 2006.285.06:11:59.39#ibcon#about to read 6, iclass 35, count 0 2006.285.06:11:59.39#ibcon#read 6, iclass 35, count 0 2006.285.06:11:59.39#ibcon#end of sib2, iclass 35, count 0 2006.285.06:11:59.39#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:11:59.39#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:11:59.39#ibcon#[25=USB\r\n] 2006.285.06:11:59.39#ibcon#*before write, iclass 35, count 0 2006.285.06:11:59.39#ibcon#enter sib2, iclass 35, count 0 2006.285.06:11:59.39#ibcon#flushed, iclass 35, count 0 2006.285.06:11:59.39#ibcon#about to write, iclass 35, count 0 2006.285.06:11:59.39#ibcon#wrote, iclass 35, count 0 2006.285.06:11:59.39#ibcon#about to read 3, iclass 35, count 0 2006.285.06:11:59.42#ibcon#read 3, iclass 35, count 0 2006.285.06:11:59.42#ibcon#about to read 4, iclass 35, count 0 2006.285.06:11:59.42#ibcon#read 4, iclass 35, count 0 2006.285.06:11:59.42#ibcon#about to read 5, iclass 35, count 0 2006.285.06:11:59.42#ibcon#read 5, iclass 35, count 0 2006.285.06:11:59.42#ibcon#about to read 6, iclass 35, count 0 2006.285.06:11:59.42#ibcon#read 6, iclass 35, count 0 2006.285.06:11:59.42#ibcon#end of sib2, iclass 35, count 0 2006.285.06:11:59.42#ibcon#*after write, iclass 35, count 0 2006.285.06:11:59.42#ibcon#*before return 0, iclass 35, count 0 2006.285.06:11:59.42#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:11:59.42#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:11:59.42#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:11:59.42#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:11:59.42$vck44/valo=6,814.99 2006.285.06:11:59.42#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.06:11:59.42#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.06:11:59.42#ibcon#ireg 17 cls_cnt 0 2006.285.06:11:59.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:11:59.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:11:59.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:11:59.42#ibcon#enter wrdev, iclass 37, count 0 2006.285.06:11:59.42#ibcon#first serial, iclass 37, count 0 2006.285.06:11:59.42#ibcon#enter sib2, iclass 37, count 0 2006.285.06:11:59.42#ibcon#flushed, iclass 37, count 0 2006.285.06:11:59.42#ibcon#about to write, iclass 37, count 0 2006.285.06:11:59.42#ibcon#wrote, iclass 37, count 0 2006.285.06:11:59.42#ibcon#about to read 3, iclass 37, count 0 2006.285.06:11:59.44#ibcon#read 3, iclass 37, count 0 2006.285.06:11:59.44#ibcon#about to read 4, iclass 37, count 0 2006.285.06:11:59.44#ibcon#read 4, iclass 37, count 0 2006.285.06:11:59.44#ibcon#about to read 5, iclass 37, count 0 2006.285.06:11:59.44#ibcon#read 5, iclass 37, count 0 2006.285.06:11:59.44#ibcon#about to read 6, iclass 37, count 0 2006.285.06:11:59.44#ibcon#read 6, iclass 37, count 0 2006.285.06:11:59.44#ibcon#end of sib2, iclass 37, count 0 2006.285.06:11:59.44#ibcon#*mode == 0, iclass 37, count 0 2006.285.06:11:59.44#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.06:11:59.44#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:11:59.44#ibcon#*before write, iclass 37, count 0 2006.285.06:11:59.44#ibcon#enter sib2, iclass 37, count 0 2006.285.06:11:59.44#ibcon#flushed, iclass 37, count 0 2006.285.06:11:59.44#ibcon#about to write, iclass 37, count 0 2006.285.06:11:59.44#ibcon#wrote, iclass 37, count 0 2006.285.06:11:59.44#ibcon#about to read 3, iclass 37, count 0 2006.285.06:11:59.48#ibcon#read 3, iclass 37, count 0 2006.285.06:11:59.48#ibcon#about to read 4, iclass 37, count 0 2006.285.06:11:59.48#ibcon#read 4, iclass 37, count 0 2006.285.06:11:59.48#ibcon#about to read 5, iclass 37, count 0 2006.285.06:11:59.48#ibcon#read 5, iclass 37, count 0 2006.285.06:11:59.48#ibcon#about to read 6, iclass 37, count 0 2006.285.06:11:59.48#ibcon#read 6, iclass 37, count 0 2006.285.06:11:59.48#ibcon#end of sib2, iclass 37, count 0 2006.285.06:11:59.48#ibcon#*after write, iclass 37, count 0 2006.285.06:11:59.48#ibcon#*before return 0, iclass 37, count 0 2006.285.06:11:59.48#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:11:59.48#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:11:59.48#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.06:11:59.48#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.06:11:59.48$vck44/va=6,4 2006.285.06:11:59.48#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.06:11:59.48#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.06:11:59.48#ibcon#ireg 11 cls_cnt 2 2006.285.06:11:59.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:11:59.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:11:59.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:11:59.54#ibcon#enter wrdev, iclass 39, count 2 2006.285.06:11:59.54#ibcon#first serial, iclass 39, count 2 2006.285.06:11:59.54#ibcon#enter sib2, iclass 39, count 2 2006.285.06:11:59.54#ibcon#flushed, iclass 39, count 2 2006.285.06:11:59.54#ibcon#about to write, iclass 39, count 2 2006.285.06:11:59.54#ibcon#wrote, iclass 39, count 2 2006.285.06:11:59.54#ibcon#about to read 3, iclass 39, count 2 2006.285.06:11:59.56#ibcon#read 3, iclass 39, count 2 2006.285.06:11:59.56#ibcon#about to read 4, iclass 39, count 2 2006.285.06:11:59.56#ibcon#read 4, iclass 39, count 2 2006.285.06:11:59.56#ibcon#about to read 5, iclass 39, count 2 2006.285.06:11:59.56#ibcon#read 5, iclass 39, count 2 2006.285.06:11:59.56#ibcon#about to read 6, iclass 39, count 2 2006.285.06:11:59.56#ibcon#read 6, iclass 39, count 2 2006.285.06:11:59.56#ibcon#end of sib2, iclass 39, count 2 2006.285.06:11:59.56#ibcon#*mode == 0, iclass 39, count 2 2006.285.06:11:59.56#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.06:11:59.56#ibcon#[25=AT06-04\r\n] 2006.285.06:11:59.56#ibcon#*before write, iclass 39, count 2 2006.285.06:11:59.56#ibcon#enter sib2, iclass 39, count 2 2006.285.06:11:59.56#ibcon#flushed, iclass 39, count 2 2006.285.06:11:59.56#ibcon#about to write, iclass 39, count 2 2006.285.06:11:59.56#ibcon#wrote, iclass 39, count 2 2006.285.06:11:59.56#ibcon#about to read 3, iclass 39, count 2 2006.285.06:11:59.59#ibcon#read 3, iclass 39, count 2 2006.285.06:11:59.59#ibcon#about to read 4, iclass 39, count 2 2006.285.06:11:59.59#ibcon#read 4, iclass 39, count 2 2006.285.06:11:59.59#ibcon#about to read 5, iclass 39, count 2 2006.285.06:11:59.59#ibcon#read 5, iclass 39, count 2 2006.285.06:11:59.59#ibcon#about to read 6, iclass 39, count 2 2006.285.06:11:59.59#ibcon#read 6, iclass 39, count 2 2006.285.06:11:59.59#ibcon#end of sib2, iclass 39, count 2 2006.285.06:11:59.59#ibcon#*after write, iclass 39, count 2 2006.285.06:11:59.59#ibcon#*before return 0, iclass 39, count 2 2006.285.06:11:59.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:11:59.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:11:59.59#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.06:11:59.59#ibcon#ireg 7 cls_cnt 0 2006.285.06:11:59.59#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:11:59.71#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:11:59.71#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:11:59.71#ibcon#enter wrdev, iclass 39, count 0 2006.285.06:11:59.71#ibcon#first serial, iclass 39, count 0 2006.285.06:11:59.71#ibcon#enter sib2, iclass 39, count 0 2006.285.06:11:59.71#ibcon#flushed, iclass 39, count 0 2006.285.06:11:59.71#ibcon#about to write, iclass 39, count 0 2006.285.06:11:59.71#ibcon#wrote, iclass 39, count 0 2006.285.06:11:59.71#ibcon#about to read 3, iclass 39, count 0 2006.285.06:11:59.73#ibcon#read 3, iclass 39, count 0 2006.285.06:11:59.73#ibcon#about to read 4, iclass 39, count 0 2006.285.06:11:59.73#ibcon#read 4, iclass 39, count 0 2006.285.06:11:59.73#ibcon#about to read 5, iclass 39, count 0 2006.285.06:11:59.73#ibcon#read 5, iclass 39, count 0 2006.285.06:11:59.73#ibcon#about to read 6, iclass 39, count 0 2006.285.06:11:59.73#ibcon#read 6, iclass 39, count 0 2006.285.06:11:59.73#ibcon#end of sib2, iclass 39, count 0 2006.285.06:11:59.73#ibcon#*mode == 0, iclass 39, count 0 2006.285.06:11:59.73#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.06:11:59.73#ibcon#[25=USB\r\n] 2006.285.06:11:59.73#ibcon#*before write, iclass 39, count 0 2006.285.06:11:59.73#ibcon#enter sib2, iclass 39, count 0 2006.285.06:11:59.73#ibcon#flushed, iclass 39, count 0 2006.285.06:11:59.73#ibcon#about to write, iclass 39, count 0 2006.285.06:11:59.73#ibcon#wrote, iclass 39, count 0 2006.285.06:11:59.73#ibcon#about to read 3, iclass 39, count 0 2006.285.06:11:59.76#ibcon#read 3, iclass 39, count 0 2006.285.06:11:59.76#ibcon#about to read 4, iclass 39, count 0 2006.285.06:11:59.76#ibcon#read 4, iclass 39, count 0 2006.285.06:11:59.76#ibcon#about to read 5, iclass 39, count 0 2006.285.06:11:59.76#ibcon#read 5, iclass 39, count 0 2006.285.06:11:59.76#ibcon#about to read 6, iclass 39, count 0 2006.285.06:11:59.76#ibcon#read 6, iclass 39, count 0 2006.285.06:11:59.76#ibcon#end of sib2, iclass 39, count 0 2006.285.06:11:59.76#ibcon#*after write, iclass 39, count 0 2006.285.06:11:59.76#ibcon#*before return 0, iclass 39, count 0 2006.285.06:11:59.76#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:11:59.76#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:11:59.76#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.06:11:59.76#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.06:11:59.76$vck44/valo=7,864.99 2006.285.06:11:59.76#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.06:11:59.76#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.06:11:59.76#ibcon#ireg 17 cls_cnt 0 2006.285.06:11:59.76#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:11:59.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:11:59.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:11:59.76#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:11:59.76#ibcon#first serial, iclass 3, count 0 2006.285.06:11:59.76#ibcon#enter sib2, iclass 3, count 0 2006.285.06:11:59.76#ibcon#flushed, iclass 3, count 0 2006.285.06:11:59.76#ibcon#about to write, iclass 3, count 0 2006.285.06:11:59.76#ibcon#wrote, iclass 3, count 0 2006.285.06:11:59.76#ibcon#about to read 3, iclass 3, count 0 2006.285.06:11:59.78#ibcon#read 3, iclass 3, count 0 2006.285.06:11:59.78#ibcon#about to read 4, iclass 3, count 0 2006.285.06:11:59.78#ibcon#read 4, iclass 3, count 0 2006.285.06:11:59.78#ibcon#about to read 5, iclass 3, count 0 2006.285.06:11:59.78#ibcon#read 5, iclass 3, count 0 2006.285.06:11:59.78#ibcon#about to read 6, iclass 3, count 0 2006.285.06:11:59.78#ibcon#read 6, iclass 3, count 0 2006.285.06:11:59.78#ibcon#end of sib2, iclass 3, count 0 2006.285.06:11:59.78#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:11:59.78#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:11:59.78#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:11:59.78#ibcon#*before write, iclass 3, count 0 2006.285.06:11:59.78#ibcon#enter sib2, iclass 3, count 0 2006.285.06:11:59.78#ibcon#flushed, iclass 3, count 0 2006.285.06:11:59.78#ibcon#about to write, iclass 3, count 0 2006.285.06:11:59.78#ibcon#wrote, iclass 3, count 0 2006.285.06:11:59.78#ibcon#about to read 3, iclass 3, count 0 2006.285.06:11:59.82#ibcon#read 3, iclass 3, count 0 2006.285.06:11:59.82#ibcon#about to read 4, iclass 3, count 0 2006.285.06:11:59.82#ibcon#read 4, iclass 3, count 0 2006.285.06:11:59.82#ibcon#about to read 5, iclass 3, count 0 2006.285.06:11:59.82#ibcon#read 5, iclass 3, count 0 2006.285.06:11:59.82#ibcon#about to read 6, iclass 3, count 0 2006.285.06:11:59.82#ibcon#read 6, iclass 3, count 0 2006.285.06:11:59.82#ibcon#end of sib2, iclass 3, count 0 2006.285.06:11:59.82#ibcon#*after write, iclass 3, count 0 2006.285.06:11:59.82#ibcon#*before return 0, iclass 3, count 0 2006.285.06:11:59.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:11:59.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:11:59.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:11:59.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:11:59.82$vck44/va=7,4 2006.285.06:11:59.82#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.06:11:59.82#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.06:11:59.82#ibcon#ireg 11 cls_cnt 2 2006.285.06:11:59.82#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:11:59.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:11:59.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:11:59.88#ibcon#enter wrdev, iclass 5, count 2 2006.285.06:11:59.88#ibcon#first serial, iclass 5, count 2 2006.285.06:11:59.88#ibcon#enter sib2, iclass 5, count 2 2006.285.06:11:59.88#ibcon#flushed, iclass 5, count 2 2006.285.06:11:59.88#ibcon#about to write, iclass 5, count 2 2006.285.06:11:59.88#ibcon#wrote, iclass 5, count 2 2006.285.06:11:59.88#ibcon#about to read 3, iclass 5, count 2 2006.285.06:11:59.90#ibcon#read 3, iclass 5, count 2 2006.285.06:11:59.90#ibcon#about to read 4, iclass 5, count 2 2006.285.06:11:59.90#ibcon#read 4, iclass 5, count 2 2006.285.06:11:59.90#ibcon#about to read 5, iclass 5, count 2 2006.285.06:11:59.90#ibcon#read 5, iclass 5, count 2 2006.285.06:11:59.90#ibcon#about to read 6, iclass 5, count 2 2006.285.06:11:59.90#ibcon#read 6, iclass 5, count 2 2006.285.06:11:59.90#ibcon#end of sib2, iclass 5, count 2 2006.285.06:11:59.90#ibcon#*mode == 0, iclass 5, count 2 2006.285.06:11:59.90#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.06:11:59.90#ibcon#[25=AT07-04\r\n] 2006.285.06:11:59.90#ibcon#*before write, iclass 5, count 2 2006.285.06:11:59.90#ibcon#enter sib2, iclass 5, count 2 2006.285.06:11:59.90#ibcon#flushed, iclass 5, count 2 2006.285.06:11:59.90#ibcon#about to write, iclass 5, count 2 2006.285.06:11:59.90#ibcon#wrote, iclass 5, count 2 2006.285.06:11:59.90#ibcon#about to read 3, iclass 5, count 2 2006.285.06:11:59.93#ibcon#read 3, iclass 5, count 2 2006.285.06:11:59.93#ibcon#about to read 4, iclass 5, count 2 2006.285.06:11:59.93#ibcon#read 4, iclass 5, count 2 2006.285.06:11:59.93#ibcon#about to read 5, iclass 5, count 2 2006.285.06:11:59.93#ibcon#read 5, iclass 5, count 2 2006.285.06:11:59.93#ibcon#about to read 6, iclass 5, count 2 2006.285.06:11:59.93#ibcon#read 6, iclass 5, count 2 2006.285.06:11:59.93#ibcon#end of sib2, iclass 5, count 2 2006.285.06:11:59.93#ibcon#*after write, iclass 5, count 2 2006.285.06:11:59.93#ibcon#*before return 0, iclass 5, count 2 2006.285.06:11:59.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:11:59.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:11:59.93#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.06:11:59.93#ibcon#ireg 7 cls_cnt 0 2006.285.06:11:59.93#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:12:00.05#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:12:00.05#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:12:00.05#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:12:00.05#ibcon#first serial, iclass 5, count 0 2006.285.06:12:00.05#ibcon#enter sib2, iclass 5, count 0 2006.285.06:12:00.05#ibcon#flushed, iclass 5, count 0 2006.285.06:12:00.05#ibcon#about to write, iclass 5, count 0 2006.285.06:12:00.05#ibcon#wrote, iclass 5, count 0 2006.285.06:12:00.05#ibcon#about to read 3, iclass 5, count 0 2006.285.06:12:00.07#ibcon#read 3, iclass 5, count 0 2006.285.06:12:00.07#ibcon#about to read 4, iclass 5, count 0 2006.285.06:12:00.07#ibcon#read 4, iclass 5, count 0 2006.285.06:12:00.07#ibcon#about to read 5, iclass 5, count 0 2006.285.06:12:00.07#ibcon#read 5, iclass 5, count 0 2006.285.06:12:00.07#ibcon#about to read 6, iclass 5, count 0 2006.285.06:12:00.07#ibcon#read 6, iclass 5, count 0 2006.285.06:12:00.07#ibcon#end of sib2, iclass 5, count 0 2006.285.06:12:00.07#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:12:00.07#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:12:00.07#ibcon#[25=USB\r\n] 2006.285.06:12:00.07#ibcon#*before write, iclass 5, count 0 2006.285.06:12:00.07#ibcon#enter sib2, iclass 5, count 0 2006.285.06:12:00.07#ibcon#flushed, iclass 5, count 0 2006.285.06:12:00.07#ibcon#about to write, iclass 5, count 0 2006.285.06:12:00.07#ibcon#wrote, iclass 5, count 0 2006.285.06:12:00.07#ibcon#about to read 3, iclass 5, count 0 2006.285.06:12:00.10#ibcon#read 3, iclass 5, count 0 2006.285.06:12:00.10#ibcon#about to read 4, iclass 5, count 0 2006.285.06:12:00.10#ibcon#read 4, iclass 5, count 0 2006.285.06:12:00.10#ibcon#about to read 5, iclass 5, count 0 2006.285.06:12:00.10#ibcon#read 5, iclass 5, count 0 2006.285.06:12:00.10#ibcon#about to read 6, iclass 5, count 0 2006.285.06:12:00.10#ibcon#read 6, iclass 5, count 0 2006.285.06:12:00.10#ibcon#end of sib2, iclass 5, count 0 2006.285.06:12:00.10#ibcon#*after write, iclass 5, count 0 2006.285.06:12:00.10#ibcon#*before return 0, iclass 5, count 0 2006.285.06:12:00.10#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:12:00.10#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:12:00.10#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:12:00.10#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:12:00.10$vck44/valo=8,884.99 2006.285.06:12:00.10#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.06:12:00.10#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.06:12:00.10#ibcon#ireg 17 cls_cnt 0 2006.285.06:12:00.10#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:12:00.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:12:00.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:12:00.10#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:12:00.10#ibcon#first serial, iclass 7, count 0 2006.285.06:12:00.10#ibcon#enter sib2, iclass 7, count 0 2006.285.06:12:00.10#ibcon#flushed, iclass 7, count 0 2006.285.06:12:00.10#ibcon#about to write, iclass 7, count 0 2006.285.06:12:00.10#ibcon#wrote, iclass 7, count 0 2006.285.06:12:00.10#ibcon#about to read 3, iclass 7, count 0 2006.285.06:12:00.12#ibcon#read 3, iclass 7, count 0 2006.285.06:12:00.12#ibcon#about to read 4, iclass 7, count 0 2006.285.06:12:00.12#ibcon#read 4, iclass 7, count 0 2006.285.06:12:00.12#ibcon#about to read 5, iclass 7, count 0 2006.285.06:12:00.12#ibcon#read 5, iclass 7, count 0 2006.285.06:12:00.12#ibcon#about to read 6, iclass 7, count 0 2006.285.06:12:00.12#ibcon#read 6, iclass 7, count 0 2006.285.06:12:00.12#ibcon#end of sib2, iclass 7, count 0 2006.285.06:12:00.12#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:12:00.12#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:12:00.12#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:12:00.12#ibcon#*before write, iclass 7, count 0 2006.285.06:12:00.12#ibcon#enter sib2, iclass 7, count 0 2006.285.06:12:00.12#ibcon#flushed, iclass 7, count 0 2006.285.06:12:00.12#ibcon#about to write, iclass 7, count 0 2006.285.06:12:00.12#ibcon#wrote, iclass 7, count 0 2006.285.06:12:00.12#ibcon#about to read 3, iclass 7, count 0 2006.285.06:12:00.16#ibcon#read 3, iclass 7, count 0 2006.285.06:12:00.16#ibcon#about to read 4, iclass 7, count 0 2006.285.06:12:00.16#ibcon#read 4, iclass 7, count 0 2006.285.06:12:00.16#ibcon#about to read 5, iclass 7, count 0 2006.285.06:12:00.16#ibcon#read 5, iclass 7, count 0 2006.285.06:12:00.16#ibcon#about to read 6, iclass 7, count 0 2006.285.06:12:00.16#ibcon#read 6, iclass 7, count 0 2006.285.06:12:00.16#ibcon#end of sib2, iclass 7, count 0 2006.285.06:12:00.16#ibcon#*after write, iclass 7, count 0 2006.285.06:12:00.16#ibcon#*before return 0, iclass 7, count 0 2006.285.06:12:00.16#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:12:00.16#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:12:00.16#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:12:00.16#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:12:00.16$vck44/va=8,3 2006.285.06:12:00.16#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.06:12:00.16#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.06:12:00.16#ibcon#ireg 11 cls_cnt 2 2006.285.06:12:00.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:12:00.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:12:00.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:12:00.22#ibcon#enter wrdev, iclass 11, count 2 2006.285.06:12:00.22#ibcon#first serial, iclass 11, count 2 2006.285.06:12:00.22#ibcon#enter sib2, iclass 11, count 2 2006.285.06:12:00.22#ibcon#flushed, iclass 11, count 2 2006.285.06:12:00.22#ibcon#about to write, iclass 11, count 2 2006.285.06:12:00.22#ibcon#wrote, iclass 11, count 2 2006.285.06:12:00.22#ibcon#about to read 3, iclass 11, count 2 2006.285.06:12:00.24#ibcon#read 3, iclass 11, count 2 2006.285.06:12:00.24#ibcon#about to read 4, iclass 11, count 2 2006.285.06:12:00.24#ibcon#read 4, iclass 11, count 2 2006.285.06:12:00.24#ibcon#about to read 5, iclass 11, count 2 2006.285.06:12:00.24#ibcon#read 5, iclass 11, count 2 2006.285.06:12:00.24#ibcon#about to read 6, iclass 11, count 2 2006.285.06:12:00.24#ibcon#read 6, iclass 11, count 2 2006.285.06:12:00.24#ibcon#end of sib2, iclass 11, count 2 2006.285.06:12:00.24#ibcon#*mode == 0, iclass 11, count 2 2006.285.06:12:00.24#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.06:12:00.24#ibcon#[25=AT08-03\r\n] 2006.285.06:12:00.24#ibcon#*before write, iclass 11, count 2 2006.285.06:12:00.24#ibcon#enter sib2, iclass 11, count 2 2006.285.06:12:00.24#ibcon#flushed, iclass 11, count 2 2006.285.06:12:00.24#ibcon#about to write, iclass 11, count 2 2006.285.06:12:00.24#ibcon#wrote, iclass 11, count 2 2006.285.06:12:00.24#ibcon#about to read 3, iclass 11, count 2 2006.285.06:12:00.27#ibcon#read 3, iclass 11, count 2 2006.285.06:12:00.27#ibcon#about to read 4, iclass 11, count 2 2006.285.06:12:00.27#ibcon#read 4, iclass 11, count 2 2006.285.06:12:00.27#ibcon#about to read 5, iclass 11, count 2 2006.285.06:12:00.27#ibcon#read 5, iclass 11, count 2 2006.285.06:12:00.27#ibcon#about to read 6, iclass 11, count 2 2006.285.06:12:00.27#ibcon#read 6, iclass 11, count 2 2006.285.06:12:00.27#ibcon#end of sib2, iclass 11, count 2 2006.285.06:12:00.27#ibcon#*after write, iclass 11, count 2 2006.285.06:12:00.27#ibcon#*before return 0, iclass 11, count 2 2006.285.06:12:00.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:12:00.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:12:00.27#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.06:12:00.27#ibcon#ireg 7 cls_cnt 0 2006.285.06:12:00.27#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:12:00.39#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:12:00.39#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:12:00.39#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:12:00.39#ibcon#first serial, iclass 11, count 0 2006.285.06:12:00.39#ibcon#enter sib2, iclass 11, count 0 2006.285.06:12:00.39#ibcon#flushed, iclass 11, count 0 2006.285.06:12:00.39#ibcon#about to write, iclass 11, count 0 2006.285.06:12:00.39#ibcon#wrote, iclass 11, count 0 2006.285.06:12:00.39#ibcon#about to read 3, iclass 11, count 0 2006.285.06:12:00.41#ibcon#read 3, iclass 11, count 0 2006.285.06:12:00.41#ibcon#about to read 4, iclass 11, count 0 2006.285.06:12:00.41#ibcon#read 4, iclass 11, count 0 2006.285.06:12:00.41#ibcon#about to read 5, iclass 11, count 0 2006.285.06:12:00.41#ibcon#read 5, iclass 11, count 0 2006.285.06:12:00.41#ibcon#about to read 6, iclass 11, count 0 2006.285.06:12:00.41#ibcon#read 6, iclass 11, count 0 2006.285.06:12:00.41#ibcon#end of sib2, iclass 11, count 0 2006.285.06:12:00.41#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:12:00.41#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:12:00.41#ibcon#[25=USB\r\n] 2006.285.06:12:00.41#ibcon#*before write, iclass 11, count 0 2006.285.06:12:00.41#ibcon#enter sib2, iclass 11, count 0 2006.285.06:12:00.41#ibcon#flushed, iclass 11, count 0 2006.285.06:12:00.41#ibcon#about to write, iclass 11, count 0 2006.285.06:12:00.41#ibcon#wrote, iclass 11, count 0 2006.285.06:12:00.41#ibcon#about to read 3, iclass 11, count 0 2006.285.06:12:00.44#ibcon#read 3, iclass 11, count 0 2006.285.06:12:00.44#ibcon#about to read 4, iclass 11, count 0 2006.285.06:12:00.44#ibcon#read 4, iclass 11, count 0 2006.285.06:12:00.44#ibcon#about to read 5, iclass 11, count 0 2006.285.06:12:00.44#ibcon#read 5, iclass 11, count 0 2006.285.06:12:00.44#ibcon#about to read 6, iclass 11, count 0 2006.285.06:12:00.44#ibcon#read 6, iclass 11, count 0 2006.285.06:12:00.44#ibcon#end of sib2, iclass 11, count 0 2006.285.06:12:00.44#ibcon#*after write, iclass 11, count 0 2006.285.06:12:00.44#ibcon#*before return 0, iclass 11, count 0 2006.285.06:12:00.44#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:12:00.44#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:12:00.44#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:12:00.44#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:12:00.44$vck44/vblo=1,629.99 2006.285.06:12:00.44#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.06:12:00.44#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.06:12:00.44#ibcon#ireg 17 cls_cnt 0 2006.285.06:12:00.44#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:12:00.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:12:00.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:12:00.44#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:12:00.44#ibcon#first serial, iclass 13, count 0 2006.285.06:12:00.44#ibcon#enter sib2, iclass 13, count 0 2006.285.06:12:00.44#ibcon#flushed, iclass 13, count 0 2006.285.06:12:00.44#ibcon#about to write, iclass 13, count 0 2006.285.06:12:00.44#ibcon#wrote, iclass 13, count 0 2006.285.06:12:00.44#ibcon#about to read 3, iclass 13, count 0 2006.285.06:12:00.46#ibcon#read 3, iclass 13, count 0 2006.285.06:12:00.46#ibcon#about to read 4, iclass 13, count 0 2006.285.06:12:00.46#ibcon#read 4, iclass 13, count 0 2006.285.06:12:00.46#ibcon#about to read 5, iclass 13, count 0 2006.285.06:12:00.46#ibcon#read 5, iclass 13, count 0 2006.285.06:12:00.46#ibcon#about to read 6, iclass 13, count 0 2006.285.06:12:00.46#ibcon#read 6, iclass 13, count 0 2006.285.06:12:00.46#ibcon#end of sib2, iclass 13, count 0 2006.285.06:12:00.46#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:12:00.46#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:12:00.46#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:12:00.46#ibcon#*before write, iclass 13, count 0 2006.285.06:12:00.46#ibcon#enter sib2, iclass 13, count 0 2006.285.06:12:00.46#ibcon#flushed, iclass 13, count 0 2006.285.06:12:00.46#ibcon#about to write, iclass 13, count 0 2006.285.06:12:00.46#ibcon#wrote, iclass 13, count 0 2006.285.06:12:00.46#ibcon#about to read 3, iclass 13, count 0 2006.285.06:12:00.50#ibcon#read 3, iclass 13, count 0 2006.285.06:12:00.50#ibcon#about to read 4, iclass 13, count 0 2006.285.06:12:00.50#ibcon#read 4, iclass 13, count 0 2006.285.06:12:00.50#ibcon#about to read 5, iclass 13, count 0 2006.285.06:12:00.50#ibcon#read 5, iclass 13, count 0 2006.285.06:12:00.50#ibcon#about to read 6, iclass 13, count 0 2006.285.06:12:00.50#ibcon#read 6, iclass 13, count 0 2006.285.06:12:00.50#ibcon#end of sib2, iclass 13, count 0 2006.285.06:12:00.50#ibcon#*after write, iclass 13, count 0 2006.285.06:12:00.50#ibcon#*before return 0, iclass 13, count 0 2006.285.06:12:00.50#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:12:00.50#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:12:00.50#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:12:00.50#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:12:00.50$vck44/vb=1,4 2006.285.06:12:00.50#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.06:12:00.50#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.06:12:00.50#ibcon#ireg 11 cls_cnt 2 2006.285.06:12:00.50#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:12:00.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:12:00.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:12:00.50#ibcon#enter wrdev, iclass 15, count 2 2006.285.06:12:00.50#ibcon#first serial, iclass 15, count 2 2006.285.06:12:00.50#ibcon#enter sib2, iclass 15, count 2 2006.285.06:12:00.50#ibcon#flushed, iclass 15, count 2 2006.285.06:12:00.50#ibcon#about to write, iclass 15, count 2 2006.285.06:12:00.50#ibcon#wrote, iclass 15, count 2 2006.285.06:12:00.50#ibcon#about to read 3, iclass 15, count 2 2006.285.06:12:00.52#ibcon#read 3, iclass 15, count 2 2006.285.06:12:00.52#ibcon#about to read 4, iclass 15, count 2 2006.285.06:12:00.52#ibcon#read 4, iclass 15, count 2 2006.285.06:12:00.52#ibcon#about to read 5, iclass 15, count 2 2006.285.06:12:00.52#ibcon#read 5, iclass 15, count 2 2006.285.06:12:00.52#ibcon#about to read 6, iclass 15, count 2 2006.285.06:12:00.52#ibcon#read 6, iclass 15, count 2 2006.285.06:12:00.52#ibcon#end of sib2, iclass 15, count 2 2006.285.06:12:00.52#ibcon#*mode == 0, iclass 15, count 2 2006.285.06:12:00.52#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.06:12:00.52#ibcon#[27=AT01-04\r\n] 2006.285.06:12:00.52#ibcon#*before write, iclass 15, count 2 2006.285.06:12:00.52#ibcon#enter sib2, iclass 15, count 2 2006.285.06:12:00.52#ibcon#flushed, iclass 15, count 2 2006.285.06:12:00.52#ibcon#about to write, iclass 15, count 2 2006.285.06:12:00.52#ibcon#wrote, iclass 15, count 2 2006.285.06:12:00.52#ibcon#about to read 3, iclass 15, count 2 2006.285.06:12:00.55#ibcon#read 3, iclass 15, count 2 2006.285.06:12:00.55#ibcon#about to read 4, iclass 15, count 2 2006.285.06:12:00.55#ibcon#read 4, iclass 15, count 2 2006.285.06:12:00.55#ibcon#about to read 5, iclass 15, count 2 2006.285.06:12:00.55#ibcon#read 5, iclass 15, count 2 2006.285.06:12:00.55#ibcon#about to read 6, iclass 15, count 2 2006.285.06:12:00.55#ibcon#read 6, iclass 15, count 2 2006.285.06:12:00.55#ibcon#end of sib2, iclass 15, count 2 2006.285.06:12:00.55#ibcon#*after write, iclass 15, count 2 2006.285.06:12:00.55#ibcon#*before return 0, iclass 15, count 2 2006.285.06:12:00.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:12:00.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:12:00.55#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.06:12:00.55#ibcon#ireg 7 cls_cnt 0 2006.285.06:12:00.55#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:12:00.67#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:12:00.67#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:12:00.67#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:12:00.67#ibcon#first serial, iclass 15, count 0 2006.285.06:12:00.67#ibcon#enter sib2, iclass 15, count 0 2006.285.06:12:00.67#ibcon#flushed, iclass 15, count 0 2006.285.06:12:00.67#ibcon#about to write, iclass 15, count 0 2006.285.06:12:00.67#ibcon#wrote, iclass 15, count 0 2006.285.06:12:00.67#ibcon#about to read 3, iclass 15, count 0 2006.285.06:12:00.69#ibcon#read 3, iclass 15, count 0 2006.285.06:12:00.69#ibcon#about to read 4, iclass 15, count 0 2006.285.06:12:00.69#ibcon#read 4, iclass 15, count 0 2006.285.06:12:00.69#ibcon#about to read 5, iclass 15, count 0 2006.285.06:12:00.69#ibcon#read 5, iclass 15, count 0 2006.285.06:12:00.69#ibcon#about to read 6, iclass 15, count 0 2006.285.06:12:00.69#ibcon#read 6, iclass 15, count 0 2006.285.06:12:00.69#ibcon#end of sib2, iclass 15, count 0 2006.285.06:12:00.69#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:12:00.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:12:00.69#ibcon#[27=USB\r\n] 2006.285.06:12:00.69#ibcon#*before write, iclass 15, count 0 2006.285.06:12:00.69#ibcon#enter sib2, iclass 15, count 0 2006.285.06:12:00.69#ibcon#flushed, iclass 15, count 0 2006.285.06:12:00.69#ibcon#about to write, iclass 15, count 0 2006.285.06:12:00.69#ibcon#wrote, iclass 15, count 0 2006.285.06:12:00.69#ibcon#about to read 3, iclass 15, count 0 2006.285.06:12:00.72#ibcon#read 3, iclass 15, count 0 2006.285.06:12:00.72#ibcon#about to read 4, iclass 15, count 0 2006.285.06:12:00.72#ibcon#read 4, iclass 15, count 0 2006.285.06:12:00.72#ibcon#about to read 5, iclass 15, count 0 2006.285.06:12:00.72#ibcon#read 5, iclass 15, count 0 2006.285.06:12:00.72#ibcon#about to read 6, iclass 15, count 0 2006.285.06:12:00.72#ibcon#read 6, iclass 15, count 0 2006.285.06:12:00.72#ibcon#end of sib2, iclass 15, count 0 2006.285.06:12:00.72#ibcon#*after write, iclass 15, count 0 2006.285.06:12:00.72#ibcon#*before return 0, iclass 15, count 0 2006.285.06:12:00.72#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:12:00.72#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:12:00.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:12:00.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:12:00.72$vck44/vblo=2,634.99 2006.285.06:12:00.72#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.06:12:00.72#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.06:12:00.72#ibcon#ireg 17 cls_cnt 0 2006.285.06:12:00.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:12:00.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:12:00.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:12:00.72#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:12:00.72#ibcon#first serial, iclass 17, count 0 2006.285.06:12:00.72#ibcon#enter sib2, iclass 17, count 0 2006.285.06:12:00.72#ibcon#flushed, iclass 17, count 0 2006.285.06:12:00.72#ibcon#about to write, iclass 17, count 0 2006.285.06:12:00.72#ibcon#wrote, iclass 17, count 0 2006.285.06:12:00.72#ibcon#about to read 3, iclass 17, count 0 2006.285.06:12:00.74#ibcon#read 3, iclass 17, count 0 2006.285.06:12:00.74#ibcon#about to read 4, iclass 17, count 0 2006.285.06:12:00.74#ibcon#read 4, iclass 17, count 0 2006.285.06:12:00.74#ibcon#about to read 5, iclass 17, count 0 2006.285.06:12:00.74#ibcon#read 5, iclass 17, count 0 2006.285.06:12:00.74#ibcon#about to read 6, iclass 17, count 0 2006.285.06:12:00.74#ibcon#read 6, iclass 17, count 0 2006.285.06:12:00.74#ibcon#end of sib2, iclass 17, count 0 2006.285.06:12:00.74#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:12:00.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:12:00.74#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:12:00.74#ibcon#*before write, iclass 17, count 0 2006.285.06:12:00.74#ibcon#enter sib2, iclass 17, count 0 2006.285.06:12:00.74#ibcon#flushed, iclass 17, count 0 2006.285.06:12:00.74#ibcon#about to write, iclass 17, count 0 2006.285.06:12:00.74#ibcon#wrote, iclass 17, count 0 2006.285.06:12:00.74#ibcon#about to read 3, iclass 17, count 0 2006.285.06:12:00.78#ibcon#read 3, iclass 17, count 0 2006.285.06:12:00.78#ibcon#about to read 4, iclass 17, count 0 2006.285.06:12:00.78#ibcon#read 4, iclass 17, count 0 2006.285.06:12:00.78#ibcon#about to read 5, iclass 17, count 0 2006.285.06:12:00.78#ibcon#read 5, iclass 17, count 0 2006.285.06:12:00.78#ibcon#about to read 6, iclass 17, count 0 2006.285.06:12:00.78#ibcon#read 6, iclass 17, count 0 2006.285.06:12:00.78#ibcon#end of sib2, iclass 17, count 0 2006.285.06:12:00.78#ibcon#*after write, iclass 17, count 0 2006.285.06:12:00.78#ibcon#*before return 0, iclass 17, count 0 2006.285.06:12:00.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:12:00.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:12:00.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:12:00.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:12:00.78$vck44/vb=2,5 2006.285.06:12:00.78#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.06:12:00.78#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.06:12:00.78#ibcon#ireg 11 cls_cnt 2 2006.285.06:12:00.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:12:00.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:12:00.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:12:00.84#ibcon#enter wrdev, iclass 19, count 2 2006.285.06:12:00.84#ibcon#first serial, iclass 19, count 2 2006.285.06:12:00.84#ibcon#enter sib2, iclass 19, count 2 2006.285.06:12:00.84#ibcon#flushed, iclass 19, count 2 2006.285.06:12:00.84#ibcon#about to write, iclass 19, count 2 2006.285.06:12:00.84#ibcon#wrote, iclass 19, count 2 2006.285.06:12:00.84#ibcon#about to read 3, iclass 19, count 2 2006.285.06:12:00.86#ibcon#read 3, iclass 19, count 2 2006.285.06:12:00.86#ibcon#about to read 4, iclass 19, count 2 2006.285.06:12:00.86#ibcon#read 4, iclass 19, count 2 2006.285.06:12:00.86#ibcon#about to read 5, iclass 19, count 2 2006.285.06:12:00.86#ibcon#read 5, iclass 19, count 2 2006.285.06:12:00.86#ibcon#about to read 6, iclass 19, count 2 2006.285.06:12:00.86#ibcon#read 6, iclass 19, count 2 2006.285.06:12:00.86#ibcon#end of sib2, iclass 19, count 2 2006.285.06:12:00.86#ibcon#*mode == 0, iclass 19, count 2 2006.285.06:12:00.86#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.06:12:00.86#ibcon#[27=AT02-05\r\n] 2006.285.06:12:00.86#ibcon#*before write, iclass 19, count 2 2006.285.06:12:00.86#ibcon#enter sib2, iclass 19, count 2 2006.285.06:12:00.86#ibcon#flushed, iclass 19, count 2 2006.285.06:12:00.86#ibcon#about to write, iclass 19, count 2 2006.285.06:12:00.86#ibcon#wrote, iclass 19, count 2 2006.285.06:12:00.86#ibcon#about to read 3, iclass 19, count 2 2006.285.06:12:00.89#ibcon#read 3, iclass 19, count 2 2006.285.06:12:00.89#ibcon#about to read 4, iclass 19, count 2 2006.285.06:12:00.89#ibcon#read 4, iclass 19, count 2 2006.285.06:12:00.89#ibcon#about to read 5, iclass 19, count 2 2006.285.06:12:00.89#ibcon#read 5, iclass 19, count 2 2006.285.06:12:00.89#ibcon#about to read 6, iclass 19, count 2 2006.285.06:12:00.89#ibcon#read 6, iclass 19, count 2 2006.285.06:12:00.89#ibcon#end of sib2, iclass 19, count 2 2006.285.06:12:00.89#ibcon#*after write, iclass 19, count 2 2006.285.06:12:00.89#ibcon#*before return 0, iclass 19, count 2 2006.285.06:12:00.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:12:00.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:12:00.89#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.06:12:00.89#ibcon#ireg 7 cls_cnt 0 2006.285.06:12:00.89#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:12:01.01#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:12:01.01#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:12:01.01#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:12:01.01#ibcon#first serial, iclass 19, count 0 2006.285.06:12:01.01#ibcon#enter sib2, iclass 19, count 0 2006.285.06:12:01.01#ibcon#flushed, iclass 19, count 0 2006.285.06:12:01.01#ibcon#about to write, iclass 19, count 0 2006.285.06:12:01.01#ibcon#wrote, iclass 19, count 0 2006.285.06:12:01.01#ibcon#about to read 3, iclass 19, count 0 2006.285.06:12:01.03#ibcon#read 3, iclass 19, count 0 2006.285.06:12:01.03#ibcon#about to read 4, iclass 19, count 0 2006.285.06:12:01.03#ibcon#read 4, iclass 19, count 0 2006.285.06:12:01.03#ibcon#about to read 5, iclass 19, count 0 2006.285.06:12:01.03#ibcon#read 5, iclass 19, count 0 2006.285.06:12:01.03#ibcon#about to read 6, iclass 19, count 0 2006.285.06:12:01.03#ibcon#read 6, iclass 19, count 0 2006.285.06:12:01.03#ibcon#end of sib2, iclass 19, count 0 2006.285.06:12:01.03#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:12:01.03#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:12:01.03#ibcon#[27=USB\r\n] 2006.285.06:12:01.03#ibcon#*before write, iclass 19, count 0 2006.285.06:12:01.03#ibcon#enter sib2, iclass 19, count 0 2006.285.06:12:01.03#ibcon#flushed, iclass 19, count 0 2006.285.06:12:01.03#ibcon#about to write, iclass 19, count 0 2006.285.06:12:01.03#ibcon#wrote, iclass 19, count 0 2006.285.06:12:01.03#ibcon#about to read 3, iclass 19, count 0 2006.285.06:12:01.06#ibcon#read 3, iclass 19, count 0 2006.285.06:12:01.06#ibcon#about to read 4, iclass 19, count 0 2006.285.06:12:01.06#ibcon#read 4, iclass 19, count 0 2006.285.06:12:01.06#ibcon#about to read 5, iclass 19, count 0 2006.285.06:12:01.06#ibcon#read 5, iclass 19, count 0 2006.285.06:12:01.06#ibcon#about to read 6, iclass 19, count 0 2006.285.06:12:01.06#ibcon#read 6, iclass 19, count 0 2006.285.06:12:01.06#ibcon#end of sib2, iclass 19, count 0 2006.285.06:12:01.06#ibcon#*after write, iclass 19, count 0 2006.285.06:12:01.06#ibcon#*before return 0, iclass 19, count 0 2006.285.06:12:01.06#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:12:01.06#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:12:01.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:12:01.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:12:01.06$vck44/vblo=3,649.99 2006.285.06:12:01.06#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.06:12:01.06#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.06:12:01.06#ibcon#ireg 17 cls_cnt 0 2006.285.06:12:01.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:12:01.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:12:01.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:12:01.06#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:12:01.06#ibcon#first serial, iclass 21, count 0 2006.285.06:12:01.06#ibcon#enter sib2, iclass 21, count 0 2006.285.06:12:01.06#ibcon#flushed, iclass 21, count 0 2006.285.06:12:01.06#ibcon#about to write, iclass 21, count 0 2006.285.06:12:01.06#ibcon#wrote, iclass 21, count 0 2006.285.06:12:01.06#ibcon#about to read 3, iclass 21, count 0 2006.285.06:12:01.08#ibcon#read 3, iclass 21, count 0 2006.285.06:12:01.08#ibcon#about to read 4, iclass 21, count 0 2006.285.06:12:01.08#ibcon#read 4, iclass 21, count 0 2006.285.06:12:01.08#ibcon#about to read 5, iclass 21, count 0 2006.285.06:12:01.08#ibcon#read 5, iclass 21, count 0 2006.285.06:12:01.08#ibcon#about to read 6, iclass 21, count 0 2006.285.06:12:01.08#ibcon#read 6, iclass 21, count 0 2006.285.06:12:01.08#ibcon#end of sib2, iclass 21, count 0 2006.285.06:12:01.08#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:12:01.08#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:12:01.08#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:12:01.08#ibcon#*before write, iclass 21, count 0 2006.285.06:12:01.08#ibcon#enter sib2, iclass 21, count 0 2006.285.06:12:01.08#ibcon#flushed, iclass 21, count 0 2006.285.06:12:01.08#ibcon#about to write, iclass 21, count 0 2006.285.06:12:01.08#ibcon#wrote, iclass 21, count 0 2006.285.06:12:01.08#ibcon#about to read 3, iclass 21, count 0 2006.285.06:12:01.12#ibcon#read 3, iclass 21, count 0 2006.285.06:12:01.12#ibcon#about to read 4, iclass 21, count 0 2006.285.06:12:01.12#ibcon#read 4, iclass 21, count 0 2006.285.06:12:01.12#ibcon#about to read 5, iclass 21, count 0 2006.285.06:12:01.12#ibcon#read 5, iclass 21, count 0 2006.285.06:12:01.12#ibcon#about to read 6, iclass 21, count 0 2006.285.06:12:01.12#ibcon#read 6, iclass 21, count 0 2006.285.06:12:01.12#ibcon#end of sib2, iclass 21, count 0 2006.285.06:12:01.12#ibcon#*after write, iclass 21, count 0 2006.285.06:12:01.12#ibcon#*before return 0, iclass 21, count 0 2006.285.06:12:01.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:12:01.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:12:01.12#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:12:01.12#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:12:01.12$vck44/vb=3,4 2006.285.06:12:01.12#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.06:12:01.12#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.06:12:01.12#ibcon#ireg 11 cls_cnt 2 2006.285.06:12:01.12#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:12:01.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:12:01.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:12:01.18#ibcon#enter wrdev, iclass 23, count 2 2006.285.06:12:01.18#ibcon#first serial, iclass 23, count 2 2006.285.06:12:01.18#ibcon#enter sib2, iclass 23, count 2 2006.285.06:12:01.18#ibcon#flushed, iclass 23, count 2 2006.285.06:12:01.18#ibcon#about to write, iclass 23, count 2 2006.285.06:12:01.18#ibcon#wrote, iclass 23, count 2 2006.285.06:12:01.18#ibcon#about to read 3, iclass 23, count 2 2006.285.06:12:01.20#ibcon#read 3, iclass 23, count 2 2006.285.06:12:01.20#ibcon#about to read 4, iclass 23, count 2 2006.285.06:12:01.20#ibcon#read 4, iclass 23, count 2 2006.285.06:12:01.20#ibcon#about to read 5, iclass 23, count 2 2006.285.06:12:01.20#ibcon#read 5, iclass 23, count 2 2006.285.06:12:01.20#ibcon#about to read 6, iclass 23, count 2 2006.285.06:12:01.20#ibcon#read 6, iclass 23, count 2 2006.285.06:12:01.20#ibcon#end of sib2, iclass 23, count 2 2006.285.06:12:01.20#ibcon#*mode == 0, iclass 23, count 2 2006.285.06:12:01.20#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.06:12:01.20#ibcon#[27=AT03-04\r\n] 2006.285.06:12:01.20#ibcon#*before write, iclass 23, count 2 2006.285.06:12:01.20#ibcon#enter sib2, iclass 23, count 2 2006.285.06:12:01.20#ibcon#flushed, iclass 23, count 2 2006.285.06:12:01.20#ibcon#about to write, iclass 23, count 2 2006.285.06:12:01.20#ibcon#wrote, iclass 23, count 2 2006.285.06:12:01.20#ibcon#about to read 3, iclass 23, count 2 2006.285.06:12:01.23#ibcon#read 3, iclass 23, count 2 2006.285.06:12:01.23#ibcon#about to read 4, iclass 23, count 2 2006.285.06:12:01.23#ibcon#read 4, iclass 23, count 2 2006.285.06:12:01.23#ibcon#about to read 5, iclass 23, count 2 2006.285.06:12:01.23#ibcon#read 5, iclass 23, count 2 2006.285.06:12:01.23#ibcon#about to read 6, iclass 23, count 2 2006.285.06:12:01.23#ibcon#read 6, iclass 23, count 2 2006.285.06:12:01.23#ibcon#end of sib2, iclass 23, count 2 2006.285.06:12:01.23#ibcon#*after write, iclass 23, count 2 2006.285.06:12:01.23#ibcon#*before return 0, iclass 23, count 2 2006.285.06:12:01.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:12:01.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:12:01.23#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.06:12:01.23#ibcon#ireg 7 cls_cnt 0 2006.285.06:12:01.23#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:12:01.35#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:12:01.35#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:12:01.35#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:12:01.35#ibcon#first serial, iclass 23, count 0 2006.285.06:12:01.35#ibcon#enter sib2, iclass 23, count 0 2006.285.06:12:01.35#ibcon#flushed, iclass 23, count 0 2006.285.06:12:01.35#ibcon#about to write, iclass 23, count 0 2006.285.06:12:01.35#ibcon#wrote, iclass 23, count 0 2006.285.06:12:01.35#ibcon#about to read 3, iclass 23, count 0 2006.285.06:12:01.37#ibcon#read 3, iclass 23, count 0 2006.285.06:12:01.37#ibcon#about to read 4, iclass 23, count 0 2006.285.06:12:01.37#ibcon#read 4, iclass 23, count 0 2006.285.06:12:01.37#ibcon#about to read 5, iclass 23, count 0 2006.285.06:12:01.37#ibcon#read 5, iclass 23, count 0 2006.285.06:12:01.37#ibcon#about to read 6, iclass 23, count 0 2006.285.06:12:01.37#ibcon#read 6, iclass 23, count 0 2006.285.06:12:01.37#ibcon#end of sib2, iclass 23, count 0 2006.285.06:12:01.37#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:12:01.37#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:12:01.37#ibcon#[27=USB\r\n] 2006.285.06:12:01.37#ibcon#*before write, iclass 23, count 0 2006.285.06:12:01.37#ibcon#enter sib2, iclass 23, count 0 2006.285.06:12:01.37#ibcon#flushed, iclass 23, count 0 2006.285.06:12:01.37#ibcon#about to write, iclass 23, count 0 2006.285.06:12:01.37#ibcon#wrote, iclass 23, count 0 2006.285.06:12:01.37#ibcon#about to read 3, iclass 23, count 0 2006.285.06:12:01.40#ibcon#read 3, iclass 23, count 0 2006.285.06:12:01.40#ibcon#about to read 4, iclass 23, count 0 2006.285.06:12:01.40#ibcon#read 4, iclass 23, count 0 2006.285.06:12:01.40#ibcon#about to read 5, iclass 23, count 0 2006.285.06:12:01.40#ibcon#read 5, iclass 23, count 0 2006.285.06:12:01.40#ibcon#about to read 6, iclass 23, count 0 2006.285.06:12:01.40#ibcon#read 6, iclass 23, count 0 2006.285.06:12:01.40#ibcon#end of sib2, iclass 23, count 0 2006.285.06:12:01.40#ibcon#*after write, iclass 23, count 0 2006.285.06:12:01.40#ibcon#*before return 0, iclass 23, count 0 2006.285.06:12:01.40#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:12:01.40#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:12:01.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:12:01.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:12:01.40$vck44/vblo=4,679.99 2006.285.06:12:01.40#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.06:12:01.40#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.06:12:01.40#ibcon#ireg 17 cls_cnt 0 2006.285.06:12:01.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:12:01.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:12:01.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:12:01.40#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:12:01.40#ibcon#first serial, iclass 25, count 0 2006.285.06:12:01.40#ibcon#enter sib2, iclass 25, count 0 2006.285.06:12:01.40#ibcon#flushed, iclass 25, count 0 2006.285.06:12:01.40#ibcon#about to write, iclass 25, count 0 2006.285.06:12:01.40#ibcon#wrote, iclass 25, count 0 2006.285.06:12:01.40#ibcon#about to read 3, iclass 25, count 0 2006.285.06:12:01.42#ibcon#read 3, iclass 25, count 0 2006.285.06:12:01.42#ibcon#about to read 4, iclass 25, count 0 2006.285.06:12:01.42#ibcon#read 4, iclass 25, count 0 2006.285.06:12:01.42#ibcon#about to read 5, iclass 25, count 0 2006.285.06:12:01.42#ibcon#read 5, iclass 25, count 0 2006.285.06:12:01.42#ibcon#about to read 6, iclass 25, count 0 2006.285.06:12:01.42#ibcon#read 6, iclass 25, count 0 2006.285.06:12:01.42#ibcon#end of sib2, iclass 25, count 0 2006.285.06:12:01.42#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:12:01.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:12:01.42#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:12:01.42#ibcon#*before write, iclass 25, count 0 2006.285.06:12:01.42#ibcon#enter sib2, iclass 25, count 0 2006.285.06:12:01.42#ibcon#flushed, iclass 25, count 0 2006.285.06:12:01.42#ibcon#about to write, iclass 25, count 0 2006.285.06:12:01.42#ibcon#wrote, iclass 25, count 0 2006.285.06:12:01.42#ibcon#about to read 3, iclass 25, count 0 2006.285.06:12:01.46#ibcon#read 3, iclass 25, count 0 2006.285.06:12:01.46#ibcon#about to read 4, iclass 25, count 0 2006.285.06:12:01.46#ibcon#read 4, iclass 25, count 0 2006.285.06:12:01.46#ibcon#about to read 5, iclass 25, count 0 2006.285.06:12:01.46#ibcon#read 5, iclass 25, count 0 2006.285.06:12:01.46#ibcon#about to read 6, iclass 25, count 0 2006.285.06:12:01.46#ibcon#read 6, iclass 25, count 0 2006.285.06:12:01.46#ibcon#end of sib2, iclass 25, count 0 2006.285.06:12:01.46#ibcon#*after write, iclass 25, count 0 2006.285.06:12:01.46#ibcon#*before return 0, iclass 25, count 0 2006.285.06:12:01.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:12:01.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:12:01.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:12:01.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:12:01.46$vck44/vb=4,5 2006.285.06:12:01.46#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.06:12:01.46#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.06:12:01.46#ibcon#ireg 11 cls_cnt 2 2006.285.06:12:01.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:12:01.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:12:01.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:12:01.52#ibcon#enter wrdev, iclass 27, count 2 2006.285.06:12:01.52#ibcon#first serial, iclass 27, count 2 2006.285.06:12:01.52#ibcon#enter sib2, iclass 27, count 2 2006.285.06:12:01.52#ibcon#flushed, iclass 27, count 2 2006.285.06:12:01.52#ibcon#about to write, iclass 27, count 2 2006.285.06:12:01.52#ibcon#wrote, iclass 27, count 2 2006.285.06:12:01.52#ibcon#about to read 3, iclass 27, count 2 2006.285.06:12:01.54#ibcon#read 3, iclass 27, count 2 2006.285.06:12:01.54#ibcon#about to read 4, iclass 27, count 2 2006.285.06:12:01.54#ibcon#read 4, iclass 27, count 2 2006.285.06:12:01.54#ibcon#about to read 5, iclass 27, count 2 2006.285.06:12:01.54#ibcon#read 5, iclass 27, count 2 2006.285.06:12:01.54#ibcon#about to read 6, iclass 27, count 2 2006.285.06:12:01.54#ibcon#read 6, iclass 27, count 2 2006.285.06:12:01.54#ibcon#end of sib2, iclass 27, count 2 2006.285.06:12:01.54#ibcon#*mode == 0, iclass 27, count 2 2006.285.06:12:01.54#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.06:12:01.54#ibcon#[27=AT04-05\r\n] 2006.285.06:12:01.54#ibcon#*before write, iclass 27, count 2 2006.285.06:12:01.54#ibcon#enter sib2, iclass 27, count 2 2006.285.06:12:01.54#ibcon#flushed, iclass 27, count 2 2006.285.06:12:01.54#ibcon#about to write, iclass 27, count 2 2006.285.06:12:01.54#ibcon#wrote, iclass 27, count 2 2006.285.06:12:01.54#ibcon#about to read 3, iclass 27, count 2 2006.285.06:12:01.57#ibcon#read 3, iclass 27, count 2 2006.285.06:12:01.57#ibcon#about to read 4, iclass 27, count 2 2006.285.06:12:01.57#ibcon#read 4, iclass 27, count 2 2006.285.06:12:01.57#ibcon#about to read 5, iclass 27, count 2 2006.285.06:12:01.57#ibcon#read 5, iclass 27, count 2 2006.285.06:12:01.57#ibcon#about to read 6, iclass 27, count 2 2006.285.06:12:01.57#ibcon#read 6, iclass 27, count 2 2006.285.06:12:01.57#ibcon#end of sib2, iclass 27, count 2 2006.285.06:12:01.57#ibcon#*after write, iclass 27, count 2 2006.285.06:12:01.57#ibcon#*before return 0, iclass 27, count 2 2006.285.06:12:01.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:12:01.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:12:01.57#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.06:12:01.57#ibcon#ireg 7 cls_cnt 0 2006.285.06:12:01.57#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:12:01.69#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:12:01.69#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:12:01.69#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:12:01.69#ibcon#first serial, iclass 27, count 0 2006.285.06:12:01.69#ibcon#enter sib2, iclass 27, count 0 2006.285.06:12:01.69#ibcon#flushed, iclass 27, count 0 2006.285.06:12:01.69#ibcon#about to write, iclass 27, count 0 2006.285.06:12:01.69#ibcon#wrote, iclass 27, count 0 2006.285.06:12:01.69#ibcon#about to read 3, iclass 27, count 0 2006.285.06:12:01.71#ibcon#read 3, iclass 27, count 0 2006.285.06:12:01.71#ibcon#about to read 4, iclass 27, count 0 2006.285.06:12:01.71#ibcon#read 4, iclass 27, count 0 2006.285.06:12:01.71#ibcon#about to read 5, iclass 27, count 0 2006.285.06:12:01.71#ibcon#read 5, iclass 27, count 0 2006.285.06:12:01.71#ibcon#about to read 6, iclass 27, count 0 2006.285.06:12:01.71#ibcon#read 6, iclass 27, count 0 2006.285.06:12:01.71#ibcon#end of sib2, iclass 27, count 0 2006.285.06:12:01.71#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:12:01.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:12:01.71#ibcon#[27=USB\r\n] 2006.285.06:12:01.71#ibcon#*before write, iclass 27, count 0 2006.285.06:12:01.71#ibcon#enter sib2, iclass 27, count 0 2006.285.06:12:01.71#ibcon#flushed, iclass 27, count 0 2006.285.06:12:01.71#ibcon#about to write, iclass 27, count 0 2006.285.06:12:01.71#ibcon#wrote, iclass 27, count 0 2006.285.06:12:01.71#ibcon#about to read 3, iclass 27, count 0 2006.285.06:12:01.72#abcon#<5=/04 3.8 7.1 25.06 671014.0\r\n> 2006.285.06:12:01.74#abcon#{5=INTERFACE CLEAR} 2006.285.06:12:01.74#ibcon#read 3, iclass 27, count 0 2006.285.06:12:01.74#ibcon#about to read 4, iclass 27, count 0 2006.285.06:12:01.74#ibcon#read 4, iclass 27, count 0 2006.285.06:12:01.74#ibcon#about to read 5, iclass 27, count 0 2006.285.06:12:01.74#ibcon#read 5, iclass 27, count 0 2006.285.06:12:01.74#ibcon#about to read 6, iclass 27, count 0 2006.285.06:12:01.74#ibcon#read 6, iclass 27, count 0 2006.285.06:12:01.74#ibcon#end of sib2, iclass 27, count 0 2006.285.06:12:01.74#ibcon#*after write, iclass 27, count 0 2006.285.06:12:01.74#ibcon#*before return 0, iclass 27, count 0 2006.285.06:12:01.74#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:12:01.74#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:12:01.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:12:01.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:12:01.74$vck44/vblo=5,709.99 2006.285.06:12:01.74#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.06:12:01.74#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.06:12:01.74#ibcon#ireg 17 cls_cnt 0 2006.285.06:12:01.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:12:01.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:12:01.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:12:01.74#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:12:01.74#ibcon#first serial, iclass 32, count 0 2006.285.06:12:01.74#ibcon#enter sib2, iclass 32, count 0 2006.285.06:12:01.74#ibcon#flushed, iclass 32, count 0 2006.285.06:12:01.74#ibcon#about to write, iclass 32, count 0 2006.285.06:12:01.74#ibcon#wrote, iclass 32, count 0 2006.285.06:12:01.74#ibcon#about to read 3, iclass 32, count 0 2006.285.06:12:01.76#ibcon#read 3, iclass 32, count 0 2006.285.06:12:01.76#ibcon#about to read 4, iclass 32, count 0 2006.285.06:12:01.76#ibcon#read 4, iclass 32, count 0 2006.285.06:12:01.76#ibcon#about to read 5, iclass 32, count 0 2006.285.06:12:01.76#ibcon#read 5, iclass 32, count 0 2006.285.06:12:01.76#ibcon#about to read 6, iclass 32, count 0 2006.285.06:12:01.76#ibcon#read 6, iclass 32, count 0 2006.285.06:12:01.76#ibcon#end of sib2, iclass 32, count 0 2006.285.06:12:01.76#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:12:01.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:12:01.76#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:12:01.76#ibcon#*before write, iclass 32, count 0 2006.285.06:12:01.76#ibcon#enter sib2, iclass 32, count 0 2006.285.06:12:01.76#ibcon#flushed, iclass 32, count 0 2006.285.06:12:01.76#ibcon#about to write, iclass 32, count 0 2006.285.06:12:01.76#ibcon#wrote, iclass 32, count 0 2006.285.06:12:01.76#ibcon#about to read 3, iclass 32, count 0 2006.285.06:12:01.80#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:12:01.80#ibcon#read 3, iclass 32, count 0 2006.285.06:12:01.80#ibcon#about to read 4, iclass 32, count 0 2006.285.06:12:01.80#ibcon#read 4, iclass 32, count 0 2006.285.06:12:01.80#ibcon#about to read 5, iclass 32, count 0 2006.285.06:12:01.80#ibcon#read 5, iclass 32, count 0 2006.285.06:12:01.80#ibcon#about to read 6, iclass 32, count 0 2006.285.06:12:01.80#ibcon#read 6, iclass 32, count 0 2006.285.06:12:01.80#ibcon#end of sib2, iclass 32, count 0 2006.285.06:12:01.80#ibcon#*after write, iclass 32, count 0 2006.285.06:12:01.80#ibcon#*before return 0, iclass 32, count 0 2006.285.06:12:01.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:12:01.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:12:01.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:12:01.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:12:01.80$vck44/vb=5,4 2006.285.06:12:01.80#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.06:12:01.80#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.06:12:01.80#ibcon#ireg 11 cls_cnt 2 2006.285.06:12:01.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:12:01.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:12:01.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:12:01.86#ibcon#enter wrdev, iclass 35, count 2 2006.285.06:12:01.86#ibcon#first serial, iclass 35, count 2 2006.285.06:12:01.86#ibcon#enter sib2, iclass 35, count 2 2006.285.06:12:01.86#ibcon#flushed, iclass 35, count 2 2006.285.06:12:01.86#ibcon#about to write, iclass 35, count 2 2006.285.06:12:01.86#ibcon#wrote, iclass 35, count 2 2006.285.06:12:01.86#ibcon#about to read 3, iclass 35, count 2 2006.285.06:12:01.88#ibcon#read 3, iclass 35, count 2 2006.285.06:12:01.88#ibcon#about to read 4, iclass 35, count 2 2006.285.06:12:01.88#ibcon#read 4, iclass 35, count 2 2006.285.06:12:01.88#ibcon#about to read 5, iclass 35, count 2 2006.285.06:12:01.88#ibcon#read 5, iclass 35, count 2 2006.285.06:12:01.88#ibcon#about to read 6, iclass 35, count 2 2006.285.06:12:01.88#ibcon#read 6, iclass 35, count 2 2006.285.06:12:01.88#ibcon#end of sib2, iclass 35, count 2 2006.285.06:12:01.88#ibcon#*mode == 0, iclass 35, count 2 2006.285.06:12:01.88#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.06:12:01.88#ibcon#[27=AT05-04\r\n] 2006.285.06:12:01.88#ibcon#*before write, iclass 35, count 2 2006.285.06:12:01.88#ibcon#enter sib2, iclass 35, count 2 2006.285.06:12:01.88#ibcon#flushed, iclass 35, count 2 2006.285.06:12:01.88#ibcon#about to write, iclass 35, count 2 2006.285.06:12:01.88#ibcon#wrote, iclass 35, count 2 2006.285.06:12:01.88#ibcon#about to read 3, iclass 35, count 2 2006.285.06:12:01.91#ibcon#read 3, iclass 35, count 2 2006.285.06:12:01.91#ibcon#about to read 4, iclass 35, count 2 2006.285.06:12:01.91#ibcon#read 4, iclass 35, count 2 2006.285.06:12:01.91#ibcon#about to read 5, iclass 35, count 2 2006.285.06:12:01.91#ibcon#read 5, iclass 35, count 2 2006.285.06:12:01.91#ibcon#about to read 6, iclass 35, count 2 2006.285.06:12:01.91#ibcon#read 6, iclass 35, count 2 2006.285.06:12:01.91#ibcon#end of sib2, iclass 35, count 2 2006.285.06:12:01.91#ibcon#*after write, iclass 35, count 2 2006.285.06:12:01.91#ibcon#*before return 0, iclass 35, count 2 2006.285.06:12:01.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:12:01.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:12:01.91#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.06:12:01.91#ibcon#ireg 7 cls_cnt 0 2006.285.06:12:01.91#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:12:02.03#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:12:02.03#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:12:02.03#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:12:02.03#ibcon#first serial, iclass 35, count 0 2006.285.06:12:02.03#ibcon#enter sib2, iclass 35, count 0 2006.285.06:12:02.03#ibcon#flushed, iclass 35, count 0 2006.285.06:12:02.03#ibcon#about to write, iclass 35, count 0 2006.285.06:12:02.03#ibcon#wrote, iclass 35, count 0 2006.285.06:12:02.03#ibcon#about to read 3, iclass 35, count 0 2006.285.06:12:02.06#ibcon#read 3, iclass 35, count 0 2006.285.06:12:02.06#ibcon#about to read 4, iclass 35, count 0 2006.285.06:12:02.06#ibcon#read 4, iclass 35, count 0 2006.285.06:12:02.06#ibcon#about to read 5, iclass 35, count 0 2006.285.06:12:02.06#ibcon#read 5, iclass 35, count 0 2006.285.06:12:02.06#ibcon#about to read 6, iclass 35, count 0 2006.285.06:12:02.06#ibcon#read 6, iclass 35, count 0 2006.285.06:12:02.06#ibcon#end of sib2, iclass 35, count 0 2006.285.06:12:02.06#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:12:02.06#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:12:02.06#ibcon#[27=USB\r\n] 2006.285.06:12:02.06#ibcon#*before write, iclass 35, count 0 2006.285.06:12:02.06#ibcon#enter sib2, iclass 35, count 0 2006.285.06:12:02.06#ibcon#flushed, iclass 35, count 0 2006.285.06:12:02.06#ibcon#about to write, iclass 35, count 0 2006.285.06:12:02.06#ibcon#wrote, iclass 35, count 0 2006.285.06:12:02.06#ibcon#about to read 3, iclass 35, count 0 2006.285.06:12:02.09#ibcon#read 3, iclass 35, count 0 2006.285.06:12:02.09#ibcon#about to read 4, iclass 35, count 0 2006.285.06:12:02.09#ibcon#read 4, iclass 35, count 0 2006.285.06:12:02.09#ibcon#about to read 5, iclass 35, count 0 2006.285.06:12:02.09#ibcon#read 5, iclass 35, count 0 2006.285.06:12:02.09#ibcon#about to read 6, iclass 35, count 0 2006.285.06:12:02.09#ibcon#read 6, iclass 35, count 0 2006.285.06:12:02.09#ibcon#end of sib2, iclass 35, count 0 2006.285.06:12:02.09#ibcon#*after write, iclass 35, count 0 2006.285.06:12:02.09#ibcon#*before return 0, iclass 35, count 0 2006.285.06:12:02.09#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:12:02.09#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:12:02.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:12:02.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:12:02.09$vck44/vblo=6,719.99 2006.285.06:12:02.09#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.06:12:02.09#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.06:12:02.09#ibcon#ireg 17 cls_cnt 0 2006.285.06:12:02.09#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:12:02.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:12:02.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:12:02.09#ibcon#enter wrdev, iclass 37, count 0 2006.285.06:12:02.09#ibcon#first serial, iclass 37, count 0 2006.285.06:12:02.09#ibcon#enter sib2, iclass 37, count 0 2006.285.06:12:02.09#ibcon#flushed, iclass 37, count 0 2006.285.06:12:02.09#ibcon#about to write, iclass 37, count 0 2006.285.06:12:02.09#ibcon#wrote, iclass 37, count 0 2006.285.06:12:02.09#ibcon#about to read 3, iclass 37, count 0 2006.285.06:12:02.11#ibcon#read 3, iclass 37, count 0 2006.285.06:12:02.11#ibcon#about to read 4, iclass 37, count 0 2006.285.06:12:02.11#ibcon#read 4, iclass 37, count 0 2006.285.06:12:02.11#ibcon#about to read 5, iclass 37, count 0 2006.285.06:12:02.11#ibcon#read 5, iclass 37, count 0 2006.285.06:12:02.11#ibcon#about to read 6, iclass 37, count 0 2006.285.06:12:02.11#ibcon#read 6, iclass 37, count 0 2006.285.06:12:02.11#ibcon#end of sib2, iclass 37, count 0 2006.285.06:12:02.11#ibcon#*mode == 0, iclass 37, count 0 2006.285.06:12:02.11#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.06:12:02.11#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:12:02.11#ibcon#*before write, iclass 37, count 0 2006.285.06:12:02.11#ibcon#enter sib2, iclass 37, count 0 2006.285.06:12:02.11#ibcon#flushed, iclass 37, count 0 2006.285.06:12:02.11#ibcon#about to write, iclass 37, count 0 2006.285.06:12:02.11#ibcon#wrote, iclass 37, count 0 2006.285.06:12:02.11#ibcon#about to read 3, iclass 37, count 0 2006.285.06:12:02.15#ibcon#read 3, iclass 37, count 0 2006.285.06:12:02.15#ibcon#about to read 4, iclass 37, count 0 2006.285.06:12:02.15#ibcon#read 4, iclass 37, count 0 2006.285.06:12:02.15#ibcon#about to read 5, iclass 37, count 0 2006.285.06:12:02.15#ibcon#read 5, iclass 37, count 0 2006.285.06:12:02.15#ibcon#about to read 6, iclass 37, count 0 2006.285.06:12:02.15#ibcon#read 6, iclass 37, count 0 2006.285.06:12:02.15#ibcon#end of sib2, iclass 37, count 0 2006.285.06:12:02.15#ibcon#*after write, iclass 37, count 0 2006.285.06:12:02.15#ibcon#*before return 0, iclass 37, count 0 2006.285.06:12:02.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:12:02.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:12:02.15#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.06:12:02.15#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.06:12:02.15$vck44/vb=6,3 2006.285.06:12:02.15#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.06:12:02.15#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.06:12:02.15#ibcon#ireg 11 cls_cnt 2 2006.285.06:12:02.15#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:12:02.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:12:02.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:12:02.21#ibcon#enter wrdev, iclass 39, count 2 2006.285.06:12:02.21#ibcon#first serial, iclass 39, count 2 2006.285.06:12:02.21#ibcon#enter sib2, iclass 39, count 2 2006.285.06:12:02.21#ibcon#flushed, iclass 39, count 2 2006.285.06:12:02.21#ibcon#about to write, iclass 39, count 2 2006.285.06:12:02.21#ibcon#wrote, iclass 39, count 2 2006.285.06:12:02.21#ibcon#about to read 3, iclass 39, count 2 2006.285.06:12:02.23#ibcon#read 3, iclass 39, count 2 2006.285.06:12:02.23#ibcon#about to read 4, iclass 39, count 2 2006.285.06:12:02.23#ibcon#read 4, iclass 39, count 2 2006.285.06:12:02.23#ibcon#about to read 5, iclass 39, count 2 2006.285.06:12:02.23#ibcon#read 5, iclass 39, count 2 2006.285.06:12:02.23#ibcon#about to read 6, iclass 39, count 2 2006.285.06:12:02.23#ibcon#read 6, iclass 39, count 2 2006.285.06:12:02.23#ibcon#end of sib2, iclass 39, count 2 2006.285.06:12:02.23#ibcon#*mode == 0, iclass 39, count 2 2006.285.06:12:02.23#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.06:12:02.23#ibcon#[27=AT06-03\r\n] 2006.285.06:12:02.23#ibcon#*before write, iclass 39, count 2 2006.285.06:12:02.23#ibcon#enter sib2, iclass 39, count 2 2006.285.06:12:02.23#ibcon#flushed, iclass 39, count 2 2006.285.06:12:02.23#ibcon#about to write, iclass 39, count 2 2006.285.06:12:02.23#ibcon#wrote, iclass 39, count 2 2006.285.06:12:02.23#ibcon#about to read 3, iclass 39, count 2 2006.285.06:12:02.26#ibcon#read 3, iclass 39, count 2 2006.285.06:12:02.26#ibcon#about to read 4, iclass 39, count 2 2006.285.06:12:02.26#ibcon#read 4, iclass 39, count 2 2006.285.06:12:02.26#ibcon#about to read 5, iclass 39, count 2 2006.285.06:12:02.26#ibcon#read 5, iclass 39, count 2 2006.285.06:12:02.26#ibcon#about to read 6, iclass 39, count 2 2006.285.06:12:02.26#ibcon#read 6, iclass 39, count 2 2006.285.06:12:02.26#ibcon#end of sib2, iclass 39, count 2 2006.285.06:12:02.26#ibcon#*after write, iclass 39, count 2 2006.285.06:12:02.26#ibcon#*before return 0, iclass 39, count 2 2006.285.06:12:02.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:12:02.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:12:02.26#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.06:12:02.26#ibcon#ireg 7 cls_cnt 0 2006.285.06:12:02.26#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:12:02.38#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:12:02.38#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:12:02.38#ibcon#enter wrdev, iclass 39, count 0 2006.285.06:12:02.38#ibcon#first serial, iclass 39, count 0 2006.285.06:12:02.38#ibcon#enter sib2, iclass 39, count 0 2006.285.06:12:02.38#ibcon#flushed, iclass 39, count 0 2006.285.06:12:02.38#ibcon#about to write, iclass 39, count 0 2006.285.06:12:02.38#ibcon#wrote, iclass 39, count 0 2006.285.06:12:02.38#ibcon#about to read 3, iclass 39, count 0 2006.285.06:12:02.40#ibcon#read 3, iclass 39, count 0 2006.285.06:12:02.40#ibcon#about to read 4, iclass 39, count 0 2006.285.06:12:02.40#ibcon#read 4, iclass 39, count 0 2006.285.06:12:02.40#ibcon#about to read 5, iclass 39, count 0 2006.285.06:12:02.40#ibcon#read 5, iclass 39, count 0 2006.285.06:12:02.40#ibcon#about to read 6, iclass 39, count 0 2006.285.06:12:02.40#ibcon#read 6, iclass 39, count 0 2006.285.06:12:02.40#ibcon#end of sib2, iclass 39, count 0 2006.285.06:12:02.40#ibcon#*mode == 0, iclass 39, count 0 2006.285.06:12:02.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.06:12:02.40#ibcon#[27=USB\r\n] 2006.285.06:12:02.40#ibcon#*before write, iclass 39, count 0 2006.285.06:12:02.40#ibcon#enter sib2, iclass 39, count 0 2006.285.06:12:02.40#ibcon#flushed, iclass 39, count 0 2006.285.06:12:02.40#ibcon#about to write, iclass 39, count 0 2006.285.06:12:02.40#ibcon#wrote, iclass 39, count 0 2006.285.06:12:02.40#ibcon#about to read 3, iclass 39, count 0 2006.285.06:12:02.43#ibcon#read 3, iclass 39, count 0 2006.285.06:12:02.43#ibcon#about to read 4, iclass 39, count 0 2006.285.06:12:02.43#ibcon#read 4, iclass 39, count 0 2006.285.06:12:02.43#ibcon#about to read 5, iclass 39, count 0 2006.285.06:12:02.43#ibcon#read 5, iclass 39, count 0 2006.285.06:12:02.43#ibcon#about to read 6, iclass 39, count 0 2006.285.06:12:02.43#ibcon#read 6, iclass 39, count 0 2006.285.06:12:02.43#ibcon#end of sib2, iclass 39, count 0 2006.285.06:12:02.43#ibcon#*after write, iclass 39, count 0 2006.285.06:12:02.43#ibcon#*before return 0, iclass 39, count 0 2006.285.06:12:02.43#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:12:02.43#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:12:02.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.06:12:02.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.06:12:02.43$vck44/vblo=7,734.99 2006.285.06:12:02.43#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.06:12:02.43#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.06:12:02.43#ibcon#ireg 17 cls_cnt 0 2006.285.06:12:02.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:12:02.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:12:02.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:12:02.43#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:12:02.43#ibcon#first serial, iclass 3, count 0 2006.285.06:12:02.43#ibcon#enter sib2, iclass 3, count 0 2006.285.06:12:02.43#ibcon#flushed, iclass 3, count 0 2006.285.06:12:02.43#ibcon#about to write, iclass 3, count 0 2006.285.06:12:02.43#ibcon#wrote, iclass 3, count 0 2006.285.06:12:02.43#ibcon#about to read 3, iclass 3, count 0 2006.285.06:12:02.45#ibcon#read 3, iclass 3, count 0 2006.285.06:12:02.45#ibcon#about to read 4, iclass 3, count 0 2006.285.06:12:02.45#ibcon#read 4, iclass 3, count 0 2006.285.06:12:02.45#ibcon#about to read 5, iclass 3, count 0 2006.285.06:12:02.45#ibcon#read 5, iclass 3, count 0 2006.285.06:12:02.45#ibcon#about to read 6, iclass 3, count 0 2006.285.06:12:02.45#ibcon#read 6, iclass 3, count 0 2006.285.06:12:02.45#ibcon#end of sib2, iclass 3, count 0 2006.285.06:12:02.45#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:12:02.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:12:02.45#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:12:02.45#ibcon#*before write, iclass 3, count 0 2006.285.06:12:02.45#ibcon#enter sib2, iclass 3, count 0 2006.285.06:12:02.45#ibcon#flushed, iclass 3, count 0 2006.285.06:12:02.45#ibcon#about to write, iclass 3, count 0 2006.285.06:12:02.45#ibcon#wrote, iclass 3, count 0 2006.285.06:12:02.45#ibcon#about to read 3, iclass 3, count 0 2006.285.06:12:02.49#ibcon#read 3, iclass 3, count 0 2006.285.06:12:02.49#ibcon#about to read 4, iclass 3, count 0 2006.285.06:12:02.49#ibcon#read 4, iclass 3, count 0 2006.285.06:12:02.49#ibcon#about to read 5, iclass 3, count 0 2006.285.06:12:02.49#ibcon#read 5, iclass 3, count 0 2006.285.06:12:02.49#ibcon#about to read 6, iclass 3, count 0 2006.285.06:12:02.49#ibcon#read 6, iclass 3, count 0 2006.285.06:12:02.49#ibcon#end of sib2, iclass 3, count 0 2006.285.06:12:02.49#ibcon#*after write, iclass 3, count 0 2006.285.06:12:02.49#ibcon#*before return 0, iclass 3, count 0 2006.285.06:12:02.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:12:02.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:12:02.49#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:12:02.49#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:12:02.49$vck44/vb=7,4 2006.285.06:12:02.49#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.06:12:02.49#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.06:12:02.49#ibcon#ireg 11 cls_cnt 2 2006.285.06:12:02.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:12:02.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:12:02.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:12:02.55#ibcon#enter wrdev, iclass 5, count 2 2006.285.06:12:02.55#ibcon#first serial, iclass 5, count 2 2006.285.06:12:02.55#ibcon#enter sib2, iclass 5, count 2 2006.285.06:12:02.55#ibcon#flushed, iclass 5, count 2 2006.285.06:12:02.55#ibcon#about to write, iclass 5, count 2 2006.285.06:12:02.55#ibcon#wrote, iclass 5, count 2 2006.285.06:12:02.55#ibcon#about to read 3, iclass 5, count 2 2006.285.06:12:02.57#ibcon#read 3, iclass 5, count 2 2006.285.06:12:02.57#ibcon#about to read 4, iclass 5, count 2 2006.285.06:12:02.57#ibcon#read 4, iclass 5, count 2 2006.285.06:12:02.57#ibcon#about to read 5, iclass 5, count 2 2006.285.06:12:02.57#ibcon#read 5, iclass 5, count 2 2006.285.06:12:02.57#ibcon#about to read 6, iclass 5, count 2 2006.285.06:12:02.57#ibcon#read 6, iclass 5, count 2 2006.285.06:12:02.57#ibcon#end of sib2, iclass 5, count 2 2006.285.06:12:02.57#ibcon#*mode == 0, iclass 5, count 2 2006.285.06:12:02.57#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.06:12:02.57#ibcon#[27=AT07-04\r\n] 2006.285.06:12:02.57#ibcon#*before write, iclass 5, count 2 2006.285.06:12:02.57#ibcon#enter sib2, iclass 5, count 2 2006.285.06:12:02.57#ibcon#flushed, iclass 5, count 2 2006.285.06:12:02.57#ibcon#about to write, iclass 5, count 2 2006.285.06:12:02.57#ibcon#wrote, iclass 5, count 2 2006.285.06:12:02.57#ibcon#about to read 3, iclass 5, count 2 2006.285.06:12:02.60#ibcon#read 3, iclass 5, count 2 2006.285.06:12:02.60#ibcon#about to read 4, iclass 5, count 2 2006.285.06:12:02.60#ibcon#read 4, iclass 5, count 2 2006.285.06:12:02.60#ibcon#about to read 5, iclass 5, count 2 2006.285.06:12:02.60#ibcon#read 5, iclass 5, count 2 2006.285.06:12:02.60#ibcon#about to read 6, iclass 5, count 2 2006.285.06:12:02.60#ibcon#read 6, iclass 5, count 2 2006.285.06:12:02.60#ibcon#end of sib2, iclass 5, count 2 2006.285.06:12:02.60#ibcon#*after write, iclass 5, count 2 2006.285.06:12:02.60#ibcon#*before return 0, iclass 5, count 2 2006.285.06:12:02.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:12:02.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:12:02.60#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.06:12:02.60#ibcon#ireg 7 cls_cnt 0 2006.285.06:12:02.60#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:12:02.72#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:12:02.72#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:12:02.72#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:12:02.72#ibcon#first serial, iclass 5, count 0 2006.285.06:12:02.72#ibcon#enter sib2, iclass 5, count 0 2006.285.06:12:02.72#ibcon#flushed, iclass 5, count 0 2006.285.06:12:02.72#ibcon#about to write, iclass 5, count 0 2006.285.06:12:02.72#ibcon#wrote, iclass 5, count 0 2006.285.06:12:02.72#ibcon#about to read 3, iclass 5, count 0 2006.285.06:12:02.74#ibcon#read 3, iclass 5, count 0 2006.285.06:12:02.74#ibcon#about to read 4, iclass 5, count 0 2006.285.06:12:02.74#ibcon#read 4, iclass 5, count 0 2006.285.06:12:02.74#ibcon#about to read 5, iclass 5, count 0 2006.285.06:12:02.74#ibcon#read 5, iclass 5, count 0 2006.285.06:12:02.74#ibcon#about to read 6, iclass 5, count 0 2006.285.06:12:02.74#ibcon#read 6, iclass 5, count 0 2006.285.06:12:02.74#ibcon#end of sib2, iclass 5, count 0 2006.285.06:12:02.74#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:12:02.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:12:02.74#ibcon#[27=USB\r\n] 2006.285.06:12:02.74#ibcon#*before write, iclass 5, count 0 2006.285.06:12:02.74#ibcon#enter sib2, iclass 5, count 0 2006.285.06:12:02.74#ibcon#flushed, iclass 5, count 0 2006.285.06:12:02.74#ibcon#about to write, iclass 5, count 0 2006.285.06:12:02.74#ibcon#wrote, iclass 5, count 0 2006.285.06:12:02.74#ibcon#about to read 3, iclass 5, count 0 2006.285.06:12:02.77#ibcon#read 3, iclass 5, count 0 2006.285.06:12:02.77#ibcon#about to read 4, iclass 5, count 0 2006.285.06:12:02.77#ibcon#read 4, iclass 5, count 0 2006.285.06:12:02.77#ibcon#about to read 5, iclass 5, count 0 2006.285.06:12:02.77#ibcon#read 5, iclass 5, count 0 2006.285.06:12:02.77#ibcon#about to read 6, iclass 5, count 0 2006.285.06:12:02.77#ibcon#read 6, iclass 5, count 0 2006.285.06:12:02.77#ibcon#end of sib2, iclass 5, count 0 2006.285.06:12:02.77#ibcon#*after write, iclass 5, count 0 2006.285.06:12:02.77#ibcon#*before return 0, iclass 5, count 0 2006.285.06:12:02.77#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:12:02.77#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:12:02.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:12:02.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:12:02.77$vck44/vblo=8,744.99 2006.285.06:12:02.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.06:12:02.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.06:12:02.77#ibcon#ireg 17 cls_cnt 0 2006.285.06:12:02.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:12:02.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:12:02.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:12:02.77#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:12:02.77#ibcon#first serial, iclass 7, count 0 2006.285.06:12:02.77#ibcon#enter sib2, iclass 7, count 0 2006.285.06:12:02.77#ibcon#flushed, iclass 7, count 0 2006.285.06:12:02.77#ibcon#about to write, iclass 7, count 0 2006.285.06:12:02.77#ibcon#wrote, iclass 7, count 0 2006.285.06:12:02.77#ibcon#about to read 3, iclass 7, count 0 2006.285.06:12:02.79#ibcon#read 3, iclass 7, count 0 2006.285.06:12:02.79#ibcon#about to read 4, iclass 7, count 0 2006.285.06:12:02.79#ibcon#read 4, iclass 7, count 0 2006.285.06:12:02.79#ibcon#about to read 5, iclass 7, count 0 2006.285.06:12:02.79#ibcon#read 5, iclass 7, count 0 2006.285.06:12:02.79#ibcon#about to read 6, iclass 7, count 0 2006.285.06:12:02.79#ibcon#read 6, iclass 7, count 0 2006.285.06:12:02.79#ibcon#end of sib2, iclass 7, count 0 2006.285.06:12:02.79#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:12:02.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:12:02.79#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:12:02.79#ibcon#*before write, iclass 7, count 0 2006.285.06:12:02.79#ibcon#enter sib2, iclass 7, count 0 2006.285.06:12:02.79#ibcon#flushed, iclass 7, count 0 2006.285.06:12:02.79#ibcon#about to write, iclass 7, count 0 2006.285.06:12:02.79#ibcon#wrote, iclass 7, count 0 2006.285.06:12:02.79#ibcon#about to read 3, iclass 7, count 0 2006.285.06:12:02.83#ibcon#read 3, iclass 7, count 0 2006.285.06:12:02.83#ibcon#about to read 4, iclass 7, count 0 2006.285.06:12:02.83#ibcon#read 4, iclass 7, count 0 2006.285.06:12:02.83#ibcon#about to read 5, iclass 7, count 0 2006.285.06:12:02.83#ibcon#read 5, iclass 7, count 0 2006.285.06:12:02.83#ibcon#about to read 6, iclass 7, count 0 2006.285.06:12:02.83#ibcon#read 6, iclass 7, count 0 2006.285.06:12:02.83#ibcon#end of sib2, iclass 7, count 0 2006.285.06:12:02.83#ibcon#*after write, iclass 7, count 0 2006.285.06:12:02.83#ibcon#*before return 0, iclass 7, count 0 2006.285.06:12:02.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:12:02.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:12:02.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:12:02.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:12:02.83$vck44/vb=8,4 2006.285.06:12:02.83#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.06:12:02.83#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.06:12:02.83#ibcon#ireg 11 cls_cnt 2 2006.285.06:12:02.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:12:02.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:12:02.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:12:02.89#ibcon#enter wrdev, iclass 11, count 2 2006.285.06:12:02.89#ibcon#first serial, iclass 11, count 2 2006.285.06:12:02.89#ibcon#enter sib2, iclass 11, count 2 2006.285.06:12:02.89#ibcon#flushed, iclass 11, count 2 2006.285.06:12:02.89#ibcon#about to write, iclass 11, count 2 2006.285.06:12:02.89#ibcon#wrote, iclass 11, count 2 2006.285.06:12:02.89#ibcon#about to read 3, iclass 11, count 2 2006.285.06:12:02.91#ibcon#read 3, iclass 11, count 2 2006.285.06:12:02.91#ibcon#about to read 4, iclass 11, count 2 2006.285.06:12:02.91#ibcon#read 4, iclass 11, count 2 2006.285.06:12:02.91#ibcon#about to read 5, iclass 11, count 2 2006.285.06:12:02.91#ibcon#read 5, iclass 11, count 2 2006.285.06:12:02.91#ibcon#about to read 6, iclass 11, count 2 2006.285.06:12:02.91#ibcon#read 6, iclass 11, count 2 2006.285.06:12:02.91#ibcon#end of sib2, iclass 11, count 2 2006.285.06:12:02.91#ibcon#*mode == 0, iclass 11, count 2 2006.285.06:12:02.91#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.06:12:02.91#ibcon#[27=AT08-04\r\n] 2006.285.06:12:02.91#ibcon#*before write, iclass 11, count 2 2006.285.06:12:02.91#ibcon#enter sib2, iclass 11, count 2 2006.285.06:12:02.91#ibcon#flushed, iclass 11, count 2 2006.285.06:12:02.91#ibcon#about to write, iclass 11, count 2 2006.285.06:12:02.91#ibcon#wrote, iclass 11, count 2 2006.285.06:12:02.91#ibcon#about to read 3, iclass 11, count 2 2006.285.06:12:02.94#ibcon#read 3, iclass 11, count 2 2006.285.06:12:02.94#ibcon#about to read 4, iclass 11, count 2 2006.285.06:12:02.94#ibcon#read 4, iclass 11, count 2 2006.285.06:12:02.94#ibcon#about to read 5, iclass 11, count 2 2006.285.06:12:02.94#ibcon#read 5, iclass 11, count 2 2006.285.06:12:02.94#ibcon#about to read 6, iclass 11, count 2 2006.285.06:12:02.94#ibcon#read 6, iclass 11, count 2 2006.285.06:12:02.94#ibcon#end of sib2, iclass 11, count 2 2006.285.06:12:02.94#ibcon#*after write, iclass 11, count 2 2006.285.06:12:02.94#ibcon#*before return 0, iclass 11, count 2 2006.285.06:12:02.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:12:02.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:12:02.94#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.06:12:02.94#ibcon#ireg 7 cls_cnt 0 2006.285.06:12:02.94#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:12:03.06#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:12:03.06#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:12:03.06#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:12:03.06#ibcon#first serial, iclass 11, count 0 2006.285.06:12:03.06#ibcon#enter sib2, iclass 11, count 0 2006.285.06:12:03.06#ibcon#flushed, iclass 11, count 0 2006.285.06:12:03.06#ibcon#about to write, iclass 11, count 0 2006.285.06:12:03.06#ibcon#wrote, iclass 11, count 0 2006.285.06:12:03.06#ibcon#about to read 3, iclass 11, count 0 2006.285.06:12:03.09#ibcon#read 3, iclass 11, count 0 2006.285.06:12:03.09#ibcon#about to read 4, iclass 11, count 0 2006.285.06:12:03.09#ibcon#read 4, iclass 11, count 0 2006.285.06:12:03.09#ibcon#about to read 5, iclass 11, count 0 2006.285.06:12:03.09#ibcon#read 5, iclass 11, count 0 2006.285.06:12:03.09#ibcon#about to read 6, iclass 11, count 0 2006.285.06:12:03.09#ibcon#read 6, iclass 11, count 0 2006.285.06:12:03.09#ibcon#end of sib2, iclass 11, count 0 2006.285.06:12:03.09#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:12:03.09#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:12:03.09#ibcon#[27=USB\r\n] 2006.285.06:12:03.09#ibcon#*before write, iclass 11, count 0 2006.285.06:12:03.09#ibcon#enter sib2, iclass 11, count 0 2006.285.06:12:03.09#ibcon#flushed, iclass 11, count 0 2006.285.06:12:03.09#ibcon#about to write, iclass 11, count 0 2006.285.06:12:03.09#ibcon#wrote, iclass 11, count 0 2006.285.06:12:03.09#ibcon#about to read 3, iclass 11, count 0 2006.285.06:12:03.12#ibcon#read 3, iclass 11, count 0 2006.285.06:12:03.12#ibcon#about to read 4, iclass 11, count 0 2006.285.06:12:03.12#ibcon#read 4, iclass 11, count 0 2006.285.06:12:03.12#ibcon#about to read 5, iclass 11, count 0 2006.285.06:12:03.12#ibcon#read 5, iclass 11, count 0 2006.285.06:12:03.12#ibcon#about to read 6, iclass 11, count 0 2006.285.06:12:03.12#ibcon#read 6, iclass 11, count 0 2006.285.06:12:03.12#ibcon#end of sib2, iclass 11, count 0 2006.285.06:12:03.12#ibcon#*after write, iclass 11, count 0 2006.285.06:12:03.12#ibcon#*before return 0, iclass 11, count 0 2006.285.06:12:03.12#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:12:03.12#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:12:03.12#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:12:03.12#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:12:03.12$vck44/vabw=wide 2006.285.06:12:03.12#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.06:12:03.12#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.06:12:03.12#ibcon#ireg 8 cls_cnt 0 2006.285.06:12:03.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:12:03.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:12:03.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:12:03.12#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:12:03.12#ibcon#first serial, iclass 13, count 0 2006.285.06:12:03.12#ibcon#enter sib2, iclass 13, count 0 2006.285.06:12:03.12#ibcon#flushed, iclass 13, count 0 2006.285.06:12:03.12#ibcon#about to write, iclass 13, count 0 2006.285.06:12:03.12#ibcon#wrote, iclass 13, count 0 2006.285.06:12:03.12#ibcon#about to read 3, iclass 13, count 0 2006.285.06:12:03.14#ibcon#read 3, iclass 13, count 0 2006.285.06:12:03.14#ibcon#about to read 4, iclass 13, count 0 2006.285.06:12:03.14#ibcon#read 4, iclass 13, count 0 2006.285.06:12:03.14#ibcon#about to read 5, iclass 13, count 0 2006.285.06:12:03.14#ibcon#read 5, iclass 13, count 0 2006.285.06:12:03.14#ibcon#about to read 6, iclass 13, count 0 2006.285.06:12:03.14#ibcon#read 6, iclass 13, count 0 2006.285.06:12:03.14#ibcon#end of sib2, iclass 13, count 0 2006.285.06:12:03.14#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:12:03.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:12:03.14#ibcon#[25=BW32\r\n] 2006.285.06:12:03.14#ibcon#*before write, iclass 13, count 0 2006.285.06:12:03.14#ibcon#enter sib2, iclass 13, count 0 2006.285.06:12:03.14#ibcon#flushed, iclass 13, count 0 2006.285.06:12:03.14#ibcon#about to write, iclass 13, count 0 2006.285.06:12:03.14#ibcon#wrote, iclass 13, count 0 2006.285.06:12:03.14#ibcon#about to read 3, iclass 13, count 0 2006.285.06:12:03.17#ibcon#read 3, iclass 13, count 0 2006.285.06:12:03.17#ibcon#about to read 4, iclass 13, count 0 2006.285.06:12:03.17#ibcon#read 4, iclass 13, count 0 2006.285.06:12:03.17#ibcon#about to read 5, iclass 13, count 0 2006.285.06:12:03.17#ibcon#read 5, iclass 13, count 0 2006.285.06:12:03.17#ibcon#about to read 6, iclass 13, count 0 2006.285.06:12:03.17#ibcon#read 6, iclass 13, count 0 2006.285.06:12:03.17#ibcon#end of sib2, iclass 13, count 0 2006.285.06:12:03.17#ibcon#*after write, iclass 13, count 0 2006.285.06:12:03.17#ibcon#*before return 0, iclass 13, count 0 2006.285.06:12:03.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:12:03.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:12:03.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:12:03.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:12:03.17$vck44/vbbw=wide 2006.285.06:12:03.17#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.06:12:03.17#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.06:12:03.17#ibcon#ireg 8 cls_cnt 0 2006.285.06:12:03.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:12:03.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:12:03.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:12:03.24#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:12:03.24#ibcon#first serial, iclass 15, count 0 2006.285.06:12:03.24#ibcon#enter sib2, iclass 15, count 0 2006.285.06:12:03.24#ibcon#flushed, iclass 15, count 0 2006.285.06:12:03.24#ibcon#about to write, iclass 15, count 0 2006.285.06:12:03.24#ibcon#wrote, iclass 15, count 0 2006.285.06:12:03.24#ibcon#about to read 3, iclass 15, count 0 2006.285.06:12:03.26#ibcon#read 3, iclass 15, count 0 2006.285.06:12:03.26#ibcon#about to read 4, iclass 15, count 0 2006.285.06:12:03.26#ibcon#read 4, iclass 15, count 0 2006.285.06:12:03.26#ibcon#about to read 5, iclass 15, count 0 2006.285.06:12:03.26#ibcon#read 5, iclass 15, count 0 2006.285.06:12:03.26#ibcon#about to read 6, iclass 15, count 0 2006.285.06:12:03.26#ibcon#read 6, iclass 15, count 0 2006.285.06:12:03.26#ibcon#end of sib2, iclass 15, count 0 2006.285.06:12:03.26#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:12:03.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:12:03.26#ibcon#[27=BW32\r\n] 2006.285.06:12:03.26#ibcon#*before write, iclass 15, count 0 2006.285.06:12:03.26#ibcon#enter sib2, iclass 15, count 0 2006.285.06:12:03.26#ibcon#flushed, iclass 15, count 0 2006.285.06:12:03.26#ibcon#about to write, iclass 15, count 0 2006.285.06:12:03.26#ibcon#wrote, iclass 15, count 0 2006.285.06:12:03.26#ibcon#about to read 3, iclass 15, count 0 2006.285.06:12:03.29#ibcon#read 3, iclass 15, count 0 2006.285.06:12:03.29#ibcon#about to read 4, iclass 15, count 0 2006.285.06:12:03.29#ibcon#read 4, iclass 15, count 0 2006.285.06:12:03.29#ibcon#about to read 5, iclass 15, count 0 2006.285.06:12:03.29#ibcon#read 5, iclass 15, count 0 2006.285.06:12:03.29#ibcon#about to read 6, iclass 15, count 0 2006.285.06:12:03.29#ibcon#read 6, iclass 15, count 0 2006.285.06:12:03.29#ibcon#end of sib2, iclass 15, count 0 2006.285.06:12:03.29#ibcon#*after write, iclass 15, count 0 2006.285.06:12:03.29#ibcon#*before return 0, iclass 15, count 0 2006.285.06:12:03.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:12:03.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:12:03.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:12:03.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:12:03.29$setupk4/ifdk4 2006.285.06:12:03.29$ifdk4/lo= 2006.285.06:12:03.29$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:12:03.29$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:12:03.29$ifdk4/patch= 2006.285.06:12:03.29$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:12:03.29$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:12:03.29$setupk4/!*+20s 2006.285.06:12:11.89#abcon#<5=/04 3.9 7.1 25.05 671014.1\r\n> 2006.285.06:12:11.91#abcon#{5=INTERFACE CLEAR} 2006.285.06:12:11.97#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:12:17.77$setupk4/"tpicd 2006.285.06:12:17.77$setupk4/echo=off 2006.285.06:12:17.77$setupk4/xlog=off 2006.285.06:12:17.77:!2006.285.06:15:32 2006.285.06:12:44.14#trakl#Source acquired 2006.285.06:12:46.14#flagr#flagr/antenna,acquired 2006.285.06:15:32.00:preob 2006.285.06:15:32.13/onsource/TRACKING 2006.285.06:15:32.13:!2006.285.06:15:42 2006.285.06:15:42.00:"tape 2006.285.06:15:42.00:"st=record 2006.285.06:15:42.00:data_valid=on 2006.285.06:15:42.00:midob 2006.285.06:15:43.13/onsource/TRACKING 2006.285.06:15:43.13/wx/25.03,1014.1,68 2006.285.06:15:43.35/cable/+6.4754E-03 2006.285.06:15:44.44/va/01,07,usb,yes,31,34 2006.285.06:15:44.44/va/02,06,usb,yes,32,32 2006.285.06:15:44.44/va/03,07,usb,yes,31,33 2006.285.06:15:44.44/va/04,06,usb,yes,32,34 2006.285.06:15:44.44/va/05,03,usb,yes,32,33 2006.285.06:15:44.44/va/06,04,usb,yes,29,28 2006.285.06:15:44.44/va/07,04,usb,yes,29,30 2006.285.06:15:44.44/va/08,03,usb,yes,30,37 2006.285.06:15:44.67/valo/01,524.99,yes,locked 2006.285.06:15:44.67/valo/02,534.99,yes,locked 2006.285.06:15:44.67/valo/03,564.99,yes,locked 2006.285.06:15:44.67/valo/04,624.99,yes,locked 2006.285.06:15:44.67/valo/05,734.99,yes,locked 2006.285.06:15:44.67/valo/06,814.99,yes,locked 2006.285.06:15:44.67/valo/07,864.99,yes,locked 2006.285.06:15:44.67/valo/08,884.99,yes,locked 2006.285.06:15:45.76/vb/01,04,usb,yes,31,29 2006.285.06:15:45.76/vb/02,05,usb,yes,29,29 2006.285.06:15:45.76/vb/03,04,usb,yes,30,33 2006.285.06:15:45.76/vb/04,05,usb,yes,30,29 2006.285.06:15:45.76/vb/05,04,usb,yes,27,29 2006.285.06:15:45.76/vb/06,03,usb,yes,38,34 2006.285.06:15:45.76/vb/07,04,usb,yes,31,31 2006.285.06:15:45.76/vb/08,04,usb,yes,28,32 2006.285.06:15:45.99/vblo/01,629.99,yes,locked 2006.285.06:15:45.99/vblo/02,634.99,yes,locked 2006.285.06:15:45.99/vblo/03,649.99,yes,locked 2006.285.06:15:45.99/vblo/04,679.99,yes,locked 2006.285.06:15:45.99/vblo/05,709.99,yes,locked 2006.285.06:15:45.99/vblo/06,719.99,yes,locked 2006.285.06:15:45.99/vblo/07,734.99,yes,locked 2006.285.06:15:45.99/vblo/08,744.99,yes,locked 2006.285.06:15:46.14/vabw/8 2006.285.06:15:46.29/vbbw/8 2006.285.06:15:46.45/xfe/off,on,12.2 2006.285.06:15:46.82/ifatt/23,28,28,28 2006.285.06:15:47.07/fmout-gps/S +2.61E-07 2006.285.06:15:47.09:!2006.285.06:16:22 2006.285.06:16:22.00:data_valid=off 2006.285.06:16:22.00:"et 2006.285.06:16:22.00:!+3s 2006.285.06:16:25.01:"tape 2006.285.06:16:25.01:postob 2006.285.06:16:25.19/cable/+6.4752E-03 2006.285.06:16:25.19/wx/25.02,1014.0,68 2006.285.06:16:26.07/fmout-gps/S +2.60E-07 2006.285.06:16:26.07:scan_name=285-0618,jd0610,40 2006.285.06:16:26.07:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.285.06:16:27.14#flagr#flagr/antenna,new-source 2006.285.06:16:27.14:checkk5 2006.285.06:16:27.49/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:16:28.03/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:16:28.38/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:16:28.81/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:16:29.21/chk_obsdata//k5ts1/T2850615??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:16:29.60/chk_obsdata//k5ts2/T2850615??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:16:29.98/chk_obsdata//k5ts3/T2850615??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:16:30.58/chk_obsdata//k5ts4/T2850615??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:16:31.35/k5log//k5ts1_log_newline 2006.285.06:16:32.11/k5log//k5ts2_log_newline 2006.285.06:16:32.91/k5log//k5ts3_log_newline 2006.285.06:16:33.68/k5log//k5ts4_log_newline 2006.285.06:16:33.71/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:16:33.71:setupk4=1 2006.285.06:16:33.71$setupk4/echo=on 2006.285.06:16:33.71$setupk4/pcalon 2006.285.06:16:33.71$pcalon/"no phase cal control is implemented here 2006.285.06:16:33.71$setupk4/"tpicd=stop 2006.285.06:16:33.71$setupk4/"rec=synch_on 2006.285.06:16:33.71$setupk4/"rec_mode=128 2006.285.06:16:33.71$setupk4/!* 2006.285.06:16:33.71$setupk4/recpk4 2006.285.06:16:33.71$recpk4/recpatch= 2006.285.06:16:33.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:16:33.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:16:33.71$setupk4/vck44 2006.285.06:16:33.71$vck44/valo=1,524.99 2006.285.06:16:33.71#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.06:16:33.71#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.06:16:33.71#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:33.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:16:33.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:16:33.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:16:33.71#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:16:33.71#ibcon#first serial, iclass 16, count 0 2006.285.06:16:33.71#ibcon#enter sib2, iclass 16, count 0 2006.285.06:16:33.71#ibcon#flushed, iclass 16, count 0 2006.285.06:16:33.71#ibcon#about to write, iclass 16, count 0 2006.285.06:16:33.71#ibcon#wrote, iclass 16, count 0 2006.285.06:16:33.71#ibcon#about to read 3, iclass 16, count 0 2006.285.06:16:33.73#ibcon#read 3, iclass 16, count 0 2006.285.06:16:33.73#ibcon#about to read 4, iclass 16, count 0 2006.285.06:16:33.73#ibcon#read 4, iclass 16, count 0 2006.285.06:16:33.73#ibcon#about to read 5, iclass 16, count 0 2006.285.06:16:33.73#ibcon#read 5, iclass 16, count 0 2006.285.06:16:33.73#ibcon#about to read 6, iclass 16, count 0 2006.285.06:16:33.73#ibcon#read 6, iclass 16, count 0 2006.285.06:16:33.73#ibcon#end of sib2, iclass 16, count 0 2006.285.06:16:33.73#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:16:33.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:16:33.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:16:33.73#ibcon#*before write, iclass 16, count 0 2006.285.06:16:33.73#ibcon#enter sib2, iclass 16, count 0 2006.285.06:16:33.73#ibcon#flushed, iclass 16, count 0 2006.285.06:16:33.73#ibcon#about to write, iclass 16, count 0 2006.285.06:16:33.73#ibcon#wrote, iclass 16, count 0 2006.285.06:16:33.73#ibcon#about to read 3, iclass 16, count 0 2006.285.06:16:33.78#ibcon#read 3, iclass 16, count 0 2006.285.06:16:33.78#ibcon#about to read 4, iclass 16, count 0 2006.285.06:16:33.78#ibcon#read 4, iclass 16, count 0 2006.285.06:16:33.78#ibcon#about to read 5, iclass 16, count 0 2006.285.06:16:33.78#ibcon#read 5, iclass 16, count 0 2006.285.06:16:33.78#ibcon#about to read 6, iclass 16, count 0 2006.285.06:16:33.78#ibcon#read 6, iclass 16, count 0 2006.285.06:16:33.78#ibcon#end of sib2, iclass 16, count 0 2006.285.06:16:33.78#ibcon#*after write, iclass 16, count 0 2006.285.06:16:33.78#ibcon#*before return 0, iclass 16, count 0 2006.285.06:16:33.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:16:33.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:16:33.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:16:33.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:16:33.78$vck44/va=1,7 2006.285.06:16:33.78#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.06:16:33.78#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.06:16:33.78#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:33.78#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:16:33.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:16:33.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:16:33.78#ibcon#enter wrdev, iclass 18, count 2 2006.285.06:16:33.78#ibcon#first serial, iclass 18, count 2 2006.285.06:16:33.78#ibcon#enter sib2, iclass 18, count 2 2006.285.06:16:33.78#ibcon#flushed, iclass 18, count 2 2006.285.06:16:33.78#ibcon#about to write, iclass 18, count 2 2006.285.06:16:33.78#ibcon#wrote, iclass 18, count 2 2006.285.06:16:33.78#ibcon#about to read 3, iclass 18, count 2 2006.285.06:16:33.80#ibcon#read 3, iclass 18, count 2 2006.285.06:16:33.80#ibcon#about to read 4, iclass 18, count 2 2006.285.06:16:33.80#ibcon#read 4, iclass 18, count 2 2006.285.06:16:33.80#ibcon#about to read 5, iclass 18, count 2 2006.285.06:16:33.80#ibcon#read 5, iclass 18, count 2 2006.285.06:16:33.80#ibcon#about to read 6, iclass 18, count 2 2006.285.06:16:33.80#ibcon#read 6, iclass 18, count 2 2006.285.06:16:33.80#ibcon#end of sib2, iclass 18, count 2 2006.285.06:16:33.80#ibcon#*mode == 0, iclass 18, count 2 2006.285.06:16:33.80#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.06:16:33.80#ibcon#[25=AT01-07\r\n] 2006.285.06:16:33.80#ibcon#*before write, iclass 18, count 2 2006.285.06:16:33.80#ibcon#enter sib2, iclass 18, count 2 2006.285.06:16:33.80#ibcon#flushed, iclass 18, count 2 2006.285.06:16:33.80#ibcon#about to write, iclass 18, count 2 2006.285.06:16:33.80#ibcon#wrote, iclass 18, count 2 2006.285.06:16:33.80#ibcon#about to read 3, iclass 18, count 2 2006.285.06:16:33.83#ibcon#read 3, iclass 18, count 2 2006.285.06:16:33.83#ibcon#about to read 4, iclass 18, count 2 2006.285.06:16:33.83#ibcon#read 4, iclass 18, count 2 2006.285.06:16:33.83#ibcon#about to read 5, iclass 18, count 2 2006.285.06:16:33.83#ibcon#read 5, iclass 18, count 2 2006.285.06:16:33.83#ibcon#about to read 6, iclass 18, count 2 2006.285.06:16:33.83#ibcon#read 6, iclass 18, count 2 2006.285.06:16:33.83#ibcon#end of sib2, iclass 18, count 2 2006.285.06:16:33.83#ibcon#*after write, iclass 18, count 2 2006.285.06:16:33.83#ibcon#*before return 0, iclass 18, count 2 2006.285.06:16:33.83#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:16:33.83#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:16:33.83#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.06:16:33.83#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:33.83#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:16:33.95#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:16:33.95#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:16:33.95#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:16:33.95#ibcon#first serial, iclass 18, count 0 2006.285.06:16:33.95#ibcon#enter sib2, iclass 18, count 0 2006.285.06:16:33.95#ibcon#flushed, iclass 18, count 0 2006.285.06:16:33.95#ibcon#about to write, iclass 18, count 0 2006.285.06:16:33.95#ibcon#wrote, iclass 18, count 0 2006.285.06:16:33.95#ibcon#about to read 3, iclass 18, count 0 2006.285.06:16:33.97#ibcon#read 3, iclass 18, count 0 2006.285.06:16:33.97#ibcon#about to read 4, iclass 18, count 0 2006.285.06:16:33.97#ibcon#read 4, iclass 18, count 0 2006.285.06:16:33.97#ibcon#about to read 5, iclass 18, count 0 2006.285.06:16:33.97#ibcon#read 5, iclass 18, count 0 2006.285.06:16:33.97#ibcon#about to read 6, iclass 18, count 0 2006.285.06:16:33.97#ibcon#read 6, iclass 18, count 0 2006.285.06:16:33.97#ibcon#end of sib2, iclass 18, count 0 2006.285.06:16:33.97#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:16:33.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:16:33.97#ibcon#[25=USB\r\n] 2006.285.06:16:33.97#ibcon#*before write, iclass 18, count 0 2006.285.06:16:33.97#ibcon#enter sib2, iclass 18, count 0 2006.285.06:16:33.97#ibcon#flushed, iclass 18, count 0 2006.285.06:16:33.97#ibcon#about to write, iclass 18, count 0 2006.285.06:16:33.97#ibcon#wrote, iclass 18, count 0 2006.285.06:16:33.97#ibcon#about to read 3, iclass 18, count 0 2006.285.06:16:34.00#ibcon#read 3, iclass 18, count 0 2006.285.06:16:34.00#ibcon#about to read 4, iclass 18, count 0 2006.285.06:16:34.00#ibcon#read 4, iclass 18, count 0 2006.285.06:16:34.00#ibcon#about to read 5, iclass 18, count 0 2006.285.06:16:34.00#ibcon#read 5, iclass 18, count 0 2006.285.06:16:34.00#ibcon#about to read 6, iclass 18, count 0 2006.285.06:16:34.00#ibcon#read 6, iclass 18, count 0 2006.285.06:16:34.00#ibcon#end of sib2, iclass 18, count 0 2006.285.06:16:34.00#ibcon#*after write, iclass 18, count 0 2006.285.06:16:34.00#ibcon#*before return 0, iclass 18, count 0 2006.285.06:16:34.00#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:16:34.00#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:16:34.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:16:34.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:16:34.00$vck44/valo=2,534.99 2006.285.06:16:34.00#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.06:16:34.00#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.06:16:34.00#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:34.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:16:34.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:16:34.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:16:34.00#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:16:34.00#ibcon#first serial, iclass 20, count 0 2006.285.06:16:34.00#ibcon#enter sib2, iclass 20, count 0 2006.285.06:16:34.00#ibcon#flushed, iclass 20, count 0 2006.285.06:16:34.00#ibcon#about to write, iclass 20, count 0 2006.285.06:16:34.00#ibcon#wrote, iclass 20, count 0 2006.285.06:16:34.00#ibcon#about to read 3, iclass 20, count 0 2006.285.06:16:34.02#ibcon#read 3, iclass 20, count 0 2006.285.06:16:34.02#ibcon#about to read 4, iclass 20, count 0 2006.285.06:16:34.02#ibcon#read 4, iclass 20, count 0 2006.285.06:16:34.02#ibcon#about to read 5, iclass 20, count 0 2006.285.06:16:34.02#ibcon#read 5, iclass 20, count 0 2006.285.06:16:34.02#ibcon#about to read 6, iclass 20, count 0 2006.285.06:16:34.02#ibcon#read 6, iclass 20, count 0 2006.285.06:16:34.02#ibcon#end of sib2, iclass 20, count 0 2006.285.06:16:34.02#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:16:34.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:16:34.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:16:34.02#ibcon#*before write, iclass 20, count 0 2006.285.06:16:34.02#ibcon#enter sib2, iclass 20, count 0 2006.285.06:16:34.02#ibcon#flushed, iclass 20, count 0 2006.285.06:16:34.02#ibcon#about to write, iclass 20, count 0 2006.285.06:16:34.02#ibcon#wrote, iclass 20, count 0 2006.285.06:16:34.02#ibcon#about to read 3, iclass 20, count 0 2006.285.06:16:34.06#ibcon#read 3, iclass 20, count 0 2006.285.06:16:34.06#ibcon#about to read 4, iclass 20, count 0 2006.285.06:16:34.06#ibcon#read 4, iclass 20, count 0 2006.285.06:16:34.06#ibcon#about to read 5, iclass 20, count 0 2006.285.06:16:34.06#ibcon#read 5, iclass 20, count 0 2006.285.06:16:34.06#ibcon#about to read 6, iclass 20, count 0 2006.285.06:16:34.06#ibcon#read 6, iclass 20, count 0 2006.285.06:16:34.06#ibcon#end of sib2, iclass 20, count 0 2006.285.06:16:34.06#ibcon#*after write, iclass 20, count 0 2006.285.06:16:34.06#ibcon#*before return 0, iclass 20, count 0 2006.285.06:16:34.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:16:34.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:16:34.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:16:34.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:16:34.06$vck44/va=2,6 2006.285.06:16:34.06#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.06:16:34.06#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.06:16:34.06#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:34.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:16:34.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:16:34.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:16:34.12#ibcon#enter wrdev, iclass 22, count 2 2006.285.06:16:34.12#ibcon#first serial, iclass 22, count 2 2006.285.06:16:34.12#ibcon#enter sib2, iclass 22, count 2 2006.285.06:16:34.12#ibcon#flushed, iclass 22, count 2 2006.285.06:16:34.12#ibcon#about to write, iclass 22, count 2 2006.285.06:16:34.12#ibcon#wrote, iclass 22, count 2 2006.285.06:16:34.12#ibcon#about to read 3, iclass 22, count 2 2006.285.06:16:34.14#ibcon#read 3, iclass 22, count 2 2006.285.06:16:34.14#ibcon#about to read 4, iclass 22, count 2 2006.285.06:16:34.14#ibcon#read 4, iclass 22, count 2 2006.285.06:16:34.14#ibcon#about to read 5, iclass 22, count 2 2006.285.06:16:34.14#ibcon#read 5, iclass 22, count 2 2006.285.06:16:34.14#ibcon#about to read 6, iclass 22, count 2 2006.285.06:16:34.14#ibcon#read 6, iclass 22, count 2 2006.285.06:16:34.14#ibcon#end of sib2, iclass 22, count 2 2006.285.06:16:34.14#ibcon#*mode == 0, iclass 22, count 2 2006.285.06:16:34.14#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.06:16:34.14#ibcon#[25=AT02-06\r\n] 2006.285.06:16:34.14#ibcon#*before write, iclass 22, count 2 2006.285.06:16:34.14#ibcon#enter sib2, iclass 22, count 2 2006.285.06:16:34.14#ibcon#flushed, iclass 22, count 2 2006.285.06:16:34.14#ibcon#about to write, iclass 22, count 2 2006.285.06:16:34.14#ibcon#wrote, iclass 22, count 2 2006.285.06:16:34.14#ibcon#about to read 3, iclass 22, count 2 2006.285.06:16:34.17#ibcon#read 3, iclass 22, count 2 2006.285.06:16:34.17#ibcon#about to read 4, iclass 22, count 2 2006.285.06:16:34.17#ibcon#read 4, iclass 22, count 2 2006.285.06:16:34.17#ibcon#about to read 5, iclass 22, count 2 2006.285.06:16:34.17#ibcon#read 5, iclass 22, count 2 2006.285.06:16:34.17#ibcon#about to read 6, iclass 22, count 2 2006.285.06:16:34.17#ibcon#read 6, iclass 22, count 2 2006.285.06:16:34.17#ibcon#end of sib2, iclass 22, count 2 2006.285.06:16:34.17#ibcon#*after write, iclass 22, count 2 2006.285.06:16:34.17#ibcon#*before return 0, iclass 22, count 2 2006.285.06:16:34.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:16:34.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:16:34.17#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.06:16:34.17#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:34.17#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:16:34.29#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:16:34.29#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:16:34.29#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:16:34.29#ibcon#first serial, iclass 22, count 0 2006.285.06:16:34.29#ibcon#enter sib2, iclass 22, count 0 2006.285.06:16:34.29#ibcon#flushed, iclass 22, count 0 2006.285.06:16:34.29#ibcon#about to write, iclass 22, count 0 2006.285.06:16:34.29#ibcon#wrote, iclass 22, count 0 2006.285.06:16:34.29#ibcon#about to read 3, iclass 22, count 0 2006.285.06:16:34.31#ibcon#read 3, iclass 22, count 0 2006.285.06:16:34.31#ibcon#about to read 4, iclass 22, count 0 2006.285.06:16:34.31#ibcon#read 4, iclass 22, count 0 2006.285.06:16:34.31#ibcon#about to read 5, iclass 22, count 0 2006.285.06:16:34.31#ibcon#read 5, iclass 22, count 0 2006.285.06:16:34.31#ibcon#about to read 6, iclass 22, count 0 2006.285.06:16:34.31#ibcon#read 6, iclass 22, count 0 2006.285.06:16:34.31#ibcon#end of sib2, iclass 22, count 0 2006.285.06:16:34.31#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:16:34.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:16:34.31#ibcon#[25=USB\r\n] 2006.285.06:16:34.31#ibcon#*before write, iclass 22, count 0 2006.285.06:16:34.31#ibcon#enter sib2, iclass 22, count 0 2006.285.06:16:34.31#ibcon#flushed, iclass 22, count 0 2006.285.06:16:34.31#ibcon#about to write, iclass 22, count 0 2006.285.06:16:34.31#ibcon#wrote, iclass 22, count 0 2006.285.06:16:34.31#ibcon#about to read 3, iclass 22, count 0 2006.285.06:16:34.34#ibcon#read 3, iclass 22, count 0 2006.285.06:16:34.34#ibcon#about to read 4, iclass 22, count 0 2006.285.06:16:34.34#ibcon#read 4, iclass 22, count 0 2006.285.06:16:34.34#ibcon#about to read 5, iclass 22, count 0 2006.285.06:16:34.34#ibcon#read 5, iclass 22, count 0 2006.285.06:16:34.34#ibcon#about to read 6, iclass 22, count 0 2006.285.06:16:34.34#ibcon#read 6, iclass 22, count 0 2006.285.06:16:34.34#ibcon#end of sib2, iclass 22, count 0 2006.285.06:16:34.34#ibcon#*after write, iclass 22, count 0 2006.285.06:16:34.34#ibcon#*before return 0, iclass 22, count 0 2006.285.06:16:34.34#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:16:34.34#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:16:34.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:16:34.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:16:34.34$vck44/valo=3,564.99 2006.285.06:16:34.34#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.06:16:34.34#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.06:16:34.34#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:34.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:16:34.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:16:34.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:16:34.34#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:16:34.34#ibcon#first serial, iclass 24, count 0 2006.285.06:16:34.34#ibcon#enter sib2, iclass 24, count 0 2006.285.06:16:34.34#ibcon#flushed, iclass 24, count 0 2006.285.06:16:34.34#ibcon#about to write, iclass 24, count 0 2006.285.06:16:34.34#ibcon#wrote, iclass 24, count 0 2006.285.06:16:34.34#ibcon#about to read 3, iclass 24, count 0 2006.285.06:16:34.36#ibcon#read 3, iclass 24, count 0 2006.285.06:16:34.36#ibcon#about to read 4, iclass 24, count 0 2006.285.06:16:34.36#ibcon#read 4, iclass 24, count 0 2006.285.06:16:34.36#ibcon#about to read 5, iclass 24, count 0 2006.285.06:16:34.36#ibcon#read 5, iclass 24, count 0 2006.285.06:16:34.36#ibcon#about to read 6, iclass 24, count 0 2006.285.06:16:34.36#ibcon#read 6, iclass 24, count 0 2006.285.06:16:34.36#ibcon#end of sib2, iclass 24, count 0 2006.285.06:16:34.36#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:16:34.36#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:16:34.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:16:34.36#ibcon#*before write, iclass 24, count 0 2006.285.06:16:34.36#ibcon#enter sib2, iclass 24, count 0 2006.285.06:16:34.36#ibcon#flushed, iclass 24, count 0 2006.285.06:16:34.36#ibcon#about to write, iclass 24, count 0 2006.285.06:16:34.36#ibcon#wrote, iclass 24, count 0 2006.285.06:16:34.36#ibcon#about to read 3, iclass 24, count 0 2006.285.06:16:34.40#ibcon#read 3, iclass 24, count 0 2006.285.06:16:34.40#ibcon#about to read 4, iclass 24, count 0 2006.285.06:16:34.40#ibcon#read 4, iclass 24, count 0 2006.285.06:16:34.40#ibcon#about to read 5, iclass 24, count 0 2006.285.06:16:34.40#ibcon#read 5, iclass 24, count 0 2006.285.06:16:34.40#ibcon#about to read 6, iclass 24, count 0 2006.285.06:16:34.40#ibcon#read 6, iclass 24, count 0 2006.285.06:16:34.40#ibcon#end of sib2, iclass 24, count 0 2006.285.06:16:34.40#ibcon#*after write, iclass 24, count 0 2006.285.06:16:34.40#ibcon#*before return 0, iclass 24, count 0 2006.285.06:16:34.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:16:34.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:16:34.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:16:34.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:16:34.40$vck44/va=3,7 2006.285.06:16:34.40#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.06:16:34.40#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.06:16:34.40#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:34.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:16:34.46#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:16:34.46#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:16:34.46#ibcon#enter wrdev, iclass 26, count 2 2006.285.06:16:34.46#ibcon#first serial, iclass 26, count 2 2006.285.06:16:34.46#ibcon#enter sib2, iclass 26, count 2 2006.285.06:16:34.46#ibcon#flushed, iclass 26, count 2 2006.285.06:16:34.46#ibcon#about to write, iclass 26, count 2 2006.285.06:16:34.46#ibcon#wrote, iclass 26, count 2 2006.285.06:16:34.46#ibcon#about to read 3, iclass 26, count 2 2006.285.06:16:34.48#ibcon#read 3, iclass 26, count 2 2006.285.06:16:34.48#ibcon#about to read 4, iclass 26, count 2 2006.285.06:16:34.48#ibcon#read 4, iclass 26, count 2 2006.285.06:16:34.48#ibcon#about to read 5, iclass 26, count 2 2006.285.06:16:34.48#ibcon#read 5, iclass 26, count 2 2006.285.06:16:34.48#ibcon#about to read 6, iclass 26, count 2 2006.285.06:16:34.48#ibcon#read 6, iclass 26, count 2 2006.285.06:16:34.48#ibcon#end of sib2, iclass 26, count 2 2006.285.06:16:34.48#ibcon#*mode == 0, iclass 26, count 2 2006.285.06:16:34.48#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.06:16:34.48#ibcon#[25=AT03-07\r\n] 2006.285.06:16:34.48#ibcon#*before write, iclass 26, count 2 2006.285.06:16:34.48#ibcon#enter sib2, iclass 26, count 2 2006.285.06:16:34.48#ibcon#flushed, iclass 26, count 2 2006.285.06:16:34.48#ibcon#about to write, iclass 26, count 2 2006.285.06:16:34.48#ibcon#wrote, iclass 26, count 2 2006.285.06:16:34.48#ibcon#about to read 3, iclass 26, count 2 2006.285.06:16:34.51#ibcon#read 3, iclass 26, count 2 2006.285.06:16:34.51#ibcon#about to read 4, iclass 26, count 2 2006.285.06:16:34.51#ibcon#read 4, iclass 26, count 2 2006.285.06:16:34.51#ibcon#about to read 5, iclass 26, count 2 2006.285.06:16:34.51#ibcon#read 5, iclass 26, count 2 2006.285.06:16:34.51#ibcon#about to read 6, iclass 26, count 2 2006.285.06:16:34.51#ibcon#read 6, iclass 26, count 2 2006.285.06:16:34.51#ibcon#end of sib2, iclass 26, count 2 2006.285.06:16:34.51#ibcon#*after write, iclass 26, count 2 2006.285.06:16:34.51#ibcon#*before return 0, iclass 26, count 2 2006.285.06:16:34.51#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:16:34.51#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:16:34.51#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.06:16:34.51#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:34.51#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:16:34.63#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:16:34.63#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:16:34.63#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:16:34.63#ibcon#first serial, iclass 26, count 0 2006.285.06:16:34.63#ibcon#enter sib2, iclass 26, count 0 2006.285.06:16:34.63#ibcon#flushed, iclass 26, count 0 2006.285.06:16:34.63#ibcon#about to write, iclass 26, count 0 2006.285.06:16:34.63#ibcon#wrote, iclass 26, count 0 2006.285.06:16:34.63#ibcon#about to read 3, iclass 26, count 0 2006.285.06:16:34.65#ibcon#read 3, iclass 26, count 0 2006.285.06:16:34.65#ibcon#about to read 4, iclass 26, count 0 2006.285.06:16:34.65#ibcon#read 4, iclass 26, count 0 2006.285.06:16:34.65#ibcon#about to read 5, iclass 26, count 0 2006.285.06:16:34.65#ibcon#read 5, iclass 26, count 0 2006.285.06:16:34.65#ibcon#about to read 6, iclass 26, count 0 2006.285.06:16:34.65#ibcon#read 6, iclass 26, count 0 2006.285.06:16:34.65#ibcon#end of sib2, iclass 26, count 0 2006.285.06:16:34.65#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:16:34.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:16:34.65#ibcon#[25=USB\r\n] 2006.285.06:16:34.65#ibcon#*before write, iclass 26, count 0 2006.285.06:16:34.65#ibcon#enter sib2, iclass 26, count 0 2006.285.06:16:34.65#ibcon#flushed, iclass 26, count 0 2006.285.06:16:34.65#ibcon#about to write, iclass 26, count 0 2006.285.06:16:34.65#ibcon#wrote, iclass 26, count 0 2006.285.06:16:34.65#ibcon#about to read 3, iclass 26, count 0 2006.285.06:16:34.68#ibcon#read 3, iclass 26, count 0 2006.285.06:16:34.68#ibcon#about to read 4, iclass 26, count 0 2006.285.06:16:34.68#ibcon#read 4, iclass 26, count 0 2006.285.06:16:34.68#ibcon#about to read 5, iclass 26, count 0 2006.285.06:16:34.68#ibcon#read 5, iclass 26, count 0 2006.285.06:16:34.68#ibcon#about to read 6, iclass 26, count 0 2006.285.06:16:34.68#ibcon#read 6, iclass 26, count 0 2006.285.06:16:34.68#ibcon#end of sib2, iclass 26, count 0 2006.285.06:16:34.68#ibcon#*after write, iclass 26, count 0 2006.285.06:16:34.68#ibcon#*before return 0, iclass 26, count 0 2006.285.06:16:34.68#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:16:34.68#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:16:34.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:16:34.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:16:34.68$vck44/valo=4,624.99 2006.285.06:16:34.68#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.06:16:34.68#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.06:16:34.68#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:34.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:16:34.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:16:34.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:16:34.68#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:16:34.68#ibcon#first serial, iclass 28, count 0 2006.285.06:16:34.68#ibcon#enter sib2, iclass 28, count 0 2006.285.06:16:34.68#ibcon#flushed, iclass 28, count 0 2006.285.06:16:34.68#ibcon#about to write, iclass 28, count 0 2006.285.06:16:34.68#ibcon#wrote, iclass 28, count 0 2006.285.06:16:34.68#ibcon#about to read 3, iclass 28, count 0 2006.285.06:16:34.70#ibcon#read 3, iclass 28, count 0 2006.285.06:16:34.70#ibcon#about to read 4, iclass 28, count 0 2006.285.06:16:34.70#ibcon#read 4, iclass 28, count 0 2006.285.06:16:34.70#ibcon#about to read 5, iclass 28, count 0 2006.285.06:16:34.70#ibcon#read 5, iclass 28, count 0 2006.285.06:16:34.70#ibcon#about to read 6, iclass 28, count 0 2006.285.06:16:34.70#ibcon#read 6, iclass 28, count 0 2006.285.06:16:34.70#ibcon#end of sib2, iclass 28, count 0 2006.285.06:16:34.70#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:16:34.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:16:34.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:16:34.70#ibcon#*before write, iclass 28, count 0 2006.285.06:16:34.70#ibcon#enter sib2, iclass 28, count 0 2006.285.06:16:34.70#ibcon#flushed, iclass 28, count 0 2006.285.06:16:34.70#ibcon#about to write, iclass 28, count 0 2006.285.06:16:34.70#ibcon#wrote, iclass 28, count 0 2006.285.06:16:34.70#ibcon#about to read 3, iclass 28, count 0 2006.285.06:16:34.74#ibcon#read 3, iclass 28, count 0 2006.285.06:16:34.74#ibcon#about to read 4, iclass 28, count 0 2006.285.06:16:34.74#ibcon#read 4, iclass 28, count 0 2006.285.06:16:34.74#ibcon#about to read 5, iclass 28, count 0 2006.285.06:16:34.74#ibcon#read 5, iclass 28, count 0 2006.285.06:16:34.74#ibcon#about to read 6, iclass 28, count 0 2006.285.06:16:34.74#ibcon#read 6, iclass 28, count 0 2006.285.06:16:34.74#ibcon#end of sib2, iclass 28, count 0 2006.285.06:16:34.74#ibcon#*after write, iclass 28, count 0 2006.285.06:16:34.74#ibcon#*before return 0, iclass 28, count 0 2006.285.06:16:34.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:16:34.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:16:34.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:16:34.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:16:34.74$vck44/va=4,6 2006.285.06:16:34.74#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.06:16:34.74#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.06:16:34.74#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:34.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:16:34.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:16:34.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:16:34.80#ibcon#enter wrdev, iclass 30, count 2 2006.285.06:16:34.80#ibcon#first serial, iclass 30, count 2 2006.285.06:16:34.80#ibcon#enter sib2, iclass 30, count 2 2006.285.06:16:34.80#ibcon#flushed, iclass 30, count 2 2006.285.06:16:34.80#ibcon#about to write, iclass 30, count 2 2006.285.06:16:34.80#ibcon#wrote, iclass 30, count 2 2006.285.06:16:34.80#ibcon#about to read 3, iclass 30, count 2 2006.285.06:16:34.82#ibcon#read 3, iclass 30, count 2 2006.285.06:16:34.82#ibcon#about to read 4, iclass 30, count 2 2006.285.06:16:34.82#ibcon#read 4, iclass 30, count 2 2006.285.06:16:34.82#ibcon#about to read 5, iclass 30, count 2 2006.285.06:16:34.82#ibcon#read 5, iclass 30, count 2 2006.285.06:16:34.82#ibcon#about to read 6, iclass 30, count 2 2006.285.06:16:34.82#ibcon#read 6, iclass 30, count 2 2006.285.06:16:34.82#ibcon#end of sib2, iclass 30, count 2 2006.285.06:16:34.82#ibcon#*mode == 0, iclass 30, count 2 2006.285.06:16:34.82#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.06:16:34.82#ibcon#[25=AT04-06\r\n] 2006.285.06:16:34.82#ibcon#*before write, iclass 30, count 2 2006.285.06:16:34.82#ibcon#enter sib2, iclass 30, count 2 2006.285.06:16:34.82#ibcon#flushed, iclass 30, count 2 2006.285.06:16:34.82#ibcon#about to write, iclass 30, count 2 2006.285.06:16:34.82#ibcon#wrote, iclass 30, count 2 2006.285.06:16:34.82#ibcon#about to read 3, iclass 30, count 2 2006.285.06:16:34.85#ibcon#read 3, iclass 30, count 2 2006.285.06:16:34.85#ibcon#about to read 4, iclass 30, count 2 2006.285.06:16:34.85#ibcon#read 4, iclass 30, count 2 2006.285.06:16:34.85#ibcon#about to read 5, iclass 30, count 2 2006.285.06:16:34.85#ibcon#read 5, iclass 30, count 2 2006.285.06:16:34.85#ibcon#about to read 6, iclass 30, count 2 2006.285.06:16:34.85#ibcon#read 6, iclass 30, count 2 2006.285.06:16:34.85#ibcon#end of sib2, iclass 30, count 2 2006.285.06:16:34.85#ibcon#*after write, iclass 30, count 2 2006.285.06:16:34.85#ibcon#*before return 0, iclass 30, count 2 2006.285.06:16:34.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:16:34.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:16:34.85#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.06:16:34.85#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:34.85#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:16:34.97#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:16:34.97#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:16:34.97#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:16:34.97#ibcon#first serial, iclass 30, count 0 2006.285.06:16:34.97#ibcon#enter sib2, iclass 30, count 0 2006.285.06:16:34.97#ibcon#flushed, iclass 30, count 0 2006.285.06:16:34.97#ibcon#about to write, iclass 30, count 0 2006.285.06:16:34.97#ibcon#wrote, iclass 30, count 0 2006.285.06:16:34.97#ibcon#about to read 3, iclass 30, count 0 2006.285.06:16:34.99#ibcon#read 3, iclass 30, count 0 2006.285.06:16:34.99#ibcon#about to read 4, iclass 30, count 0 2006.285.06:16:34.99#ibcon#read 4, iclass 30, count 0 2006.285.06:16:34.99#ibcon#about to read 5, iclass 30, count 0 2006.285.06:16:34.99#ibcon#read 5, iclass 30, count 0 2006.285.06:16:34.99#ibcon#about to read 6, iclass 30, count 0 2006.285.06:16:34.99#ibcon#read 6, iclass 30, count 0 2006.285.06:16:34.99#ibcon#end of sib2, iclass 30, count 0 2006.285.06:16:34.99#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:16:34.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:16:34.99#ibcon#[25=USB\r\n] 2006.285.06:16:34.99#ibcon#*before write, iclass 30, count 0 2006.285.06:16:34.99#ibcon#enter sib2, iclass 30, count 0 2006.285.06:16:34.99#ibcon#flushed, iclass 30, count 0 2006.285.06:16:34.99#ibcon#about to write, iclass 30, count 0 2006.285.06:16:34.99#ibcon#wrote, iclass 30, count 0 2006.285.06:16:34.99#ibcon#about to read 3, iclass 30, count 0 2006.285.06:16:35.02#ibcon#read 3, iclass 30, count 0 2006.285.06:16:35.02#ibcon#about to read 4, iclass 30, count 0 2006.285.06:16:35.02#ibcon#read 4, iclass 30, count 0 2006.285.06:16:35.02#ibcon#about to read 5, iclass 30, count 0 2006.285.06:16:35.02#ibcon#read 5, iclass 30, count 0 2006.285.06:16:35.02#ibcon#about to read 6, iclass 30, count 0 2006.285.06:16:35.02#ibcon#read 6, iclass 30, count 0 2006.285.06:16:35.02#ibcon#end of sib2, iclass 30, count 0 2006.285.06:16:35.02#ibcon#*after write, iclass 30, count 0 2006.285.06:16:35.02#ibcon#*before return 0, iclass 30, count 0 2006.285.06:16:35.02#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:16:35.02#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:16:35.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:16:35.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:16:35.02$vck44/valo=5,734.99 2006.285.06:16:35.02#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.06:16:35.02#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.06:16:35.02#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:35.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:16:35.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:16:35.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:16:35.02#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:16:35.02#ibcon#first serial, iclass 32, count 0 2006.285.06:16:35.02#ibcon#enter sib2, iclass 32, count 0 2006.285.06:16:35.02#ibcon#flushed, iclass 32, count 0 2006.285.06:16:35.02#ibcon#about to write, iclass 32, count 0 2006.285.06:16:35.02#ibcon#wrote, iclass 32, count 0 2006.285.06:16:35.02#ibcon#about to read 3, iclass 32, count 0 2006.285.06:16:35.04#ibcon#read 3, iclass 32, count 0 2006.285.06:16:35.04#ibcon#about to read 4, iclass 32, count 0 2006.285.06:16:35.04#ibcon#read 4, iclass 32, count 0 2006.285.06:16:35.04#ibcon#about to read 5, iclass 32, count 0 2006.285.06:16:35.04#ibcon#read 5, iclass 32, count 0 2006.285.06:16:35.04#ibcon#about to read 6, iclass 32, count 0 2006.285.06:16:35.04#ibcon#read 6, iclass 32, count 0 2006.285.06:16:35.04#ibcon#end of sib2, iclass 32, count 0 2006.285.06:16:35.04#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:16:35.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:16:35.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:16:35.04#ibcon#*before write, iclass 32, count 0 2006.285.06:16:35.04#ibcon#enter sib2, iclass 32, count 0 2006.285.06:16:35.04#ibcon#flushed, iclass 32, count 0 2006.285.06:16:35.04#ibcon#about to write, iclass 32, count 0 2006.285.06:16:35.04#ibcon#wrote, iclass 32, count 0 2006.285.06:16:35.04#ibcon#about to read 3, iclass 32, count 0 2006.285.06:16:35.08#ibcon#read 3, iclass 32, count 0 2006.285.06:16:35.08#ibcon#about to read 4, iclass 32, count 0 2006.285.06:16:35.08#ibcon#read 4, iclass 32, count 0 2006.285.06:16:35.08#ibcon#about to read 5, iclass 32, count 0 2006.285.06:16:35.08#ibcon#read 5, iclass 32, count 0 2006.285.06:16:35.08#ibcon#about to read 6, iclass 32, count 0 2006.285.06:16:35.08#ibcon#read 6, iclass 32, count 0 2006.285.06:16:35.08#ibcon#end of sib2, iclass 32, count 0 2006.285.06:16:35.08#ibcon#*after write, iclass 32, count 0 2006.285.06:16:35.08#ibcon#*before return 0, iclass 32, count 0 2006.285.06:16:35.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:16:35.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:16:35.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:16:35.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:16:35.08$vck44/va=5,3 2006.285.06:16:35.08#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.06:16:35.08#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.06:16:35.08#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:35.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:16:35.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:16:35.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:16:35.14#ibcon#enter wrdev, iclass 34, count 2 2006.285.06:16:35.14#ibcon#first serial, iclass 34, count 2 2006.285.06:16:35.14#ibcon#enter sib2, iclass 34, count 2 2006.285.06:16:35.14#ibcon#flushed, iclass 34, count 2 2006.285.06:16:35.14#ibcon#about to write, iclass 34, count 2 2006.285.06:16:35.14#ibcon#wrote, iclass 34, count 2 2006.285.06:16:35.14#ibcon#about to read 3, iclass 34, count 2 2006.285.06:16:35.16#ibcon#read 3, iclass 34, count 2 2006.285.06:16:35.16#ibcon#about to read 4, iclass 34, count 2 2006.285.06:16:35.16#ibcon#read 4, iclass 34, count 2 2006.285.06:16:35.16#ibcon#about to read 5, iclass 34, count 2 2006.285.06:16:35.16#ibcon#read 5, iclass 34, count 2 2006.285.06:16:35.16#ibcon#about to read 6, iclass 34, count 2 2006.285.06:16:35.16#ibcon#read 6, iclass 34, count 2 2006.285.06:16:35.16#ibcon#end of sib2, iclass 34, count 2 2006.285.06:16:35.16#ibcon#*mode == 0, iclass 34, count 2 2006.285.06:16:35.16#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.06:16:35.16#ibcon#[25=AT05-03\r\n] 2006.285.06:16:35.16#ibcon#*before write, iclass 34, count 2 2006.285.06:16:35.16#ibcon#enter sib2, iclass 34, count 2 2006.285.06:16:35.16#ibcon#flushed, iclass 34, count 2 2006.285.06:16:35.16#ibcon#about to write, iclass 34, count 2 2006.285.06:16:35.16#ibcon#wrote, iclass 34, count 2 2006.285.06:16:35.16#ibcon#about to read 3, iclass 34, count 2 2006.285.06:16:35.19#ibcon#read 3, iclass 34, count 2 2006.285.06:16:35.19#ibcon#about to read 4, iclass 34, count 2 2006.285.06:16:35.19#ibcon#read 4, iclass 34, count 2 2006.285.06:16:35.19#ibcon#about to read 5, iclass 34, count 2 2006.285.06:16:35.19#ibcon#read 5, iclass 34, count 2 2006.285.06:16:35.19#ibcon#about to read 6, iclass 34, count 2 2006.285.06:16:35.19#ibcon#read 6, iclass 34, count 2 2006.285.06:16:35.19#ibcon#end of sib2, iclass 34, count 2 2006.285.06:16:35.19#ibcon#*after write, iclass 34, count 2 2006.285.06:16:35.19#ibcon#*before return 0, iclass 34, count 2 2006.285.06:16:35.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:16:35.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:16:35.19#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.06:16:35.19#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:35.19#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:16:35.31#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:16:35.31#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:16:35.31#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:16:35.31#ibcon#first serial, iclass 34, count 0 2006.285.06:16:35.31#ibcon#enter sib2, iclass 34, count 0 2006.285.06:16:35.31#ibcon#flushed, iclass 34, count 0 2006.285.06:16:35.31#ibcon#about to write, iclass 34, count 0 2006.285.06:16:35.31#ibcon#wrote, iclass 34, count 0 2006.285.06:16:35.31#ibcon#about to read 3, iclass 34, count 0 2006.285.06:16:35.33#ibcon#read 3, iclass 34, count 0 2006.285.06:16:35.33#ibcon#about to read 4, iclass 34, count 0 2006.285.06:16:35.33#ibcon#read 4, iclass 34, count 0 2006.285.06:16:35.33#ibcon#about to read 5, iclass 34, count 0 2006.285.06:16:35.33#ibcon#read 5, iclass 34, count 0 2006.285.06:16:35.33#ibcon#about to read 6, iclass 34, count 0 2006.285.06:16:35.33#ibcon#read 6, iclass 34, count 0 2006.285.06:16:35.33#ibcon#end of sib2, iclass 34, count 0 2006.285.06:16:35.33#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:16:35.33#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:16:35.33#ibcon#[25=USB\r\n] 2006.285.06:16:35.33#ibcon#*before write, iclass 34, count 0 2006.285.06:16:35.33#ibcon#enter sib2, iclass 34, count 0 2006.285.06:16:35.33#ibcon#flushed, iclass 34, count 0 2006.285.06:16:35.33#ibcon#about to write, iclass 34, count 0 2006.285.06:16:35.33#ibcon#wrote, iclass 34, count 0 2006.285.06:16:35.33#ibcon#about to read 3, iclass 34, count 0 2006.285.06:16:35.36#ibcon#read 3, iclass 34, count 0 2006.285.06:16:35.36#ibcon#about to read 4, iclass 34, count 0 2006.285.06:16:35.36#ibcon#read 4, iclass 34, count 0 2006.285.06:16:35.36#ibcon#about to read 5, iclass 34, count 0 2006.285.06:16:35.36#ibcon#read 5, iclass 34, count 0 2006.285.06:16:35.36#ibcon#about to read 6, iclass 34, count 0 2006.285.06:16:35.36#ibcon#read 6, iclass 34, count 0 2006.285.06:16:35.36#ibcon#end of sib2, iclass 34, count 0 2006.285.06:16:35.36#ibcon#*after write, iclass 34, count 0 2006.285.06:16:35.36#ibcon#*before return 0, iclass 34, count 0 2006.285.06:16:35.36#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:16:35.36#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:16:35.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:16:35.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:16:35.36$vck44/valo=6,814.99 2006.285.06:16:35.36#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.06:16:35.36#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.06:16:35.36#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:35.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:16:35.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:16:35.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:16:35.36#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:16:35.36#ibcon#first serial, iclass 36, count 0 2006.285.06:16:35.36#ibcon#enter sib2, iclass 36, count 0 2006.285.06:16:35.36#ibcon#flushed, iclass 36, count 0 2006.285.06:16:35.36#ibcon#about to write, iclass 36, count 0 2006.285.06:16:35.36#ibcon#wrote, iclass 36, count 0 2006.285.06:16:35.36#ibcon#about to read 3, iclass 36, count 0 2006.285.06:16:35.38#ibcon#read 3, iclass 36, count 0 2006.285.06:16:35.38#ibcon#about to read 4, iclass 36, count 0 2006.285.06:16:35.38#ibcon#read 4, iclass 36, count 0 2006.285.06:16:35.38#ibcon#about to read 5, iclass 36, count 0 2006.285.06:16:35.38#ibcon#read 5, iclass 36, count 0 2006.285.06:16:35.38#ibcon#about to read 6, iclass 36, count 0 2006.285.06:16:35.38#ibcon#read 6, iclass 36, count 0 2006.285.06:16:35.38#ibcon#end of sib2, iclass 36, count 0 2006.285.06:16:35.38#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:16:35.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:16:35.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:16:35.38#ibcon#*before write, iclass 36, count 0 2006.285.06:16:35.38#ibcon#enter sib2, iclass 36, count 0 2006.285.06:16:35.38#ibcon#flushed, iclass 36, count 0 2006.285.06:16:35.38#ibcon#about to write, iclass 36, count 0 2006.285.06:16:35.38#ibcon#wrote, iclass 36, count 0 2006.285.06:16:35.38#ibcon#about to read 3, iclass 36, count 0 2006.285.06:16:35.42#ibcon#read 3, iclass 36, count 0 2006.285.06:16:35.42#ibcon#about to read 4, iclass 36, count 0 2006.285.06:16:35.42#ibcon#read 4, iclass 36, count 0 2006.285.06:16:35.42#ibcon#about to read 5, iclass 36, count 0 2006.285.06:16:35.42#ibcon#read 5, iclass 36, count 0 2006.285.06:16:35.42#ibcon#about to read 6, iclass 36, count 0 2006.285.06:16:35.42#ibcon#read 6, iclass 36, count 0 2006.285.06:16:35.42#ibcon#end of sib2, iclass 36, count 0 2006.285.06:16:35.42#ibcon#*after write, iclass 36, count 0 2006.285.06:16:35.42#ibcon#*before return 0, iclass 36, count 0 2006.285.06:16:35.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:16:35.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:16:35.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:16:35.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:16:35.42$vck44/va=6,4 2006.285.06:16:35.42#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.06:16:35.42#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.06:16:35.42#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:35.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:16:35.48#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:16:35.48#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:16:35.48#ibcon#enter wrdev, iclass 38, count 2 2006.285.06:16:35.48#ibcon#first serial, iclass 38, count 2 2006.285.06:16:35.48#ibcon#enter sib2, iclass 38, count 2 2006.285.06:16:35.48#ibcon#flushed, iclass 38, count 2 2006.285.06:16:35.48#ibcon#about to write, iclass 38, count 2 2006.285.06:16:35.48#ibcon#wrote, iclass 38, count 2 2006.285.06:16:35.48#ibcon#about to read 3, iclass 38, count 2 2006.285.06:16:35.50#ibcon#read 3, iclass 38, count 2 2006.285.06:16:35.50#ibcon#about to read 4, iclass 38, count 2 2006.285.06:16:35.50#ibcon#read 4, iclass 38, count 2 2006.285.06:16:35.50#ibcon#about to read 5, iclass 38, count 2 2006.285.06:16:35.50#ibcon#read 5, iclass 38, count 2 2006.285.06:16:35.50#ibcon#about to read 6, iclass 38, count 2 2006.285.06:16:35.50#ibcon#read 6, iclass 38, count 2 2006.285.06:16:35.50#ibcon#end of sib2, iclass 38, count 2 2006.285.06:16:35.50#ibcon#*mode == 0, iclass 38, count 2 2006.285.06:16:35.50#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.06:16:35.50#ibcon#[25=AT06-04\r\n] 2006.285.06:16:35.50#ibcon#*before write, iclass 38, count 2 2006.285.06:16:35.50#ibcon#enter sib2, iclass 38, count 2 2006.285.06:16:35.50#ibcon#flushed, iclass 38, count 2 2006.285.06:16:35.50#ibcon#about to write, iclass 38, count 2 2006.285.06:16:35.50#ibcon#wrote, iclass 38, count 2 2006.285.06:16:35.50#ibcon#about to read 3, iclass 38, count 2 2006.285.06:16:35.53#ibcon#read 3, iclass 38, count 2 2006.285.06:16:35.53#ibcon#about to read 4, iclass 38, count 2 2006.285.06:16:35.53#ibcon#read 4, iclass 38, count 2 2006.285.06:16:35.53#ibcon#about to read 5, iclass 38, count 2 2006.285.06:16:35.53#ibcon#read 5, iclass 38, count 2 2006.285.06:16:35.53#ibcon#about to read 6, iclass 38, count 2 2006.285.06:16:35.53#ibcon#read 6, iclass 38, count 2 2006.285.06:16:35.53#ibcon#end of sib2, iclass 38, count 2 2006.285.06:16:35.53#ibcon#*after write, iclass 38, count 2 2006.285.06:16:35.53#ibcon#*before return 0, iclass 38, count 2 2006.285.06:16:35.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:16:35.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:16:35.53#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.06:16:35.53#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:35.53#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:16:35.65#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:16:35.65#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:16:35.65#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:16:35.65#ibcon#first serial, iclass 38, count 0 2006.285.06:16:35.65#ibcon#enter sib2, iclass 38, count 0 2006.285.06:16:35.65#ibcon#flushed, iclass 38, count 0 2006.285.06:16:35.65#ibcon#about to write, iclass 38, count 0 2006.285.06:16:35.65#ibcon#wrote, iclass 38, count 0 2006.285.06:16:35.65#ibcon#about to read 3, iclass 38, count 0 2006.285.06:16:35.67#ibcon#read 3, iclass 38, count 0 2006.285.06:16:35.67#ibcon#about to read 4, iclass 38, count 0 2006.285.06:16:35.67#ibcon#read 4, iclass 38, count 0 2006.285.06:16:35.67#ibcon#about to read 5, iclass 38, count 0 2006.285.06:16:35.67#ibcon#read 5, iclass 38, count 0 2006.285.06:16:35.67#ibcon#about to read 6, iclass 38, count 0 2006.285.06:16:35.67#ibcon#read 6, iclass 38, count 0 2006.285.06:16:35.67#ibcon#end of sib2, iclass 38, count 0 2006.285.06:16:35.67#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:16:35.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:16:35.67#ibcon#[25=USB\r\n] 2006.285.06:16:35.67#ibcon#*before write, iclass 38, count 0 2006.285.06:16:35.67#ibcon#enter sib2, iclass 38, count 0 2006.285.06:16:35.67#ibcon#flushed, iclass 38, count 0 2006.285.06:16:35.67#ibcon#about to write, iclass 38, count 0 2006.285.06:16:35.67#ibcon#wrote, iclass 38, count 0 2006.285.06:16:35.67#ibcon#about to read 3, iclass 38, count 0 2006.285.06:16:35.70#ibcon#read 3, iclass 38, count 0 2006.285.06:16:35.70#ibcon#about to read 4, iclass 38, count 0 2006.285.06:16:35.70#ibcon#read 4, iclass 38, count 0 2006.285.06:16:35.70#ibcon#about to read 5, iclass 38, count 0 2006.285.06:16:35.70#ibcon#read 5, iclass 38, count 0 2006.285.06:16:35.70#ibcon#about to read 6, iclass 38, count 0 2006.285.06:16:35.70#ibcon#read 6, iclass 38, count 0 2006.285.06:16:35.70#ibcon#end of sib2, iclass 38, count 0 2006.285.06:16:35.70#ibcon#*after write, iclass 38, count 0 2006.285.06:16:35.70#ibcon#*before return 0, iclass 38, count 0 2006.285.06:16:35.70#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:16:35.70#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:16:35.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:16:35.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:16:35.70$vck44/valo=7,864.99 2006.285.06:16:35.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.06:16:35.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.06:16:35.70#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:35.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:16:35.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:16:35.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:16:35.70#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:16:35.70#ibcon#first serial, iclass 40, count 0 2006.285.06:16:35.70#ibcon#enter sib2, iclass 40, count 0 2006.285.06:16:35.70#ibcon#flushed, iclass 40, count 0 2006.285.06:16:35.70#ibcon#about to write, iclass 40, count 0 2006.285.06:16:35.70#ibcon#wrote, iclass 40, count 0 2006.285.06:16:35.70#ibcon#about to read 3, iclass 40, count 0 2006.285.06:16:35.72#ibcon#read 3, iclass 40, count 0 2006.285.06:16:35.72#ibcon#about to read 4, iclass 40, count 0 2006.285.06:16:35.72#ibcon#read 4, iclass 40, count 0 2006.285.06:16:35.72#ibcon#about to read 5, iclass 40, count 0 2006.285.06:16:35.72#ibcon#read 5, iclass 40, count 0 2006.285.06:16:35.72#ibcon#about to read 6, iclass 40, count 0 2006.285.06:16:35.72#ibcon#read 6, iclass 40, count 0 2006.285.06:16:35.72#ibcon#end of sib2, iclass 40, count 0 2006.285.06:16:35.72#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:16:35.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:16:35.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:16:35.72#ibcon#*before write, iclass 40, count 0 2006.285.06:16:35.72#ibcon#enter sib2, iclass 40, count 0 2006.285.06:16:35.72#ibcon#flushed, iclass 40, count 0 2006.285.06:16:35.72#ibcon#about to write, iclass 40, count 0 2006.285.06:16:35.72#ibcon#wrote, iclass 40, count 0 2006.285.06:16:35.72#ibcon#about to read 3, iclass 40, count 0 2006.285.06:16:35.77#ibcon#read 3, iclass 40, count 0 2006.285.06:16:35.77#ibcon#about to read 4, iclass 40, count 0 2006.285.06:16:35.77#ibcon#read 4, iclass 40, count 0 2006.285.06:16:35.77#ibcon#about to read 5, iclass 40, count 0 2006.285.06:16:35.77#ibcon#read 5, iclass 40, count 0 2006.285.06:16:35.77#ibcon#about to read 6, iclass 40, count 0 2006.285.06:16:35.77#ibcon#read 6, iclass 40, count 0 2006.285.06:16:35.77#ibcon#end of sib2, iclass 40, count 0 2006.285.06:16:35.77#ibcon#*after write, iclass 40, count 0 2006.285.06:16:35.77#ibcon#*before return 0, iclass 40, count 0 2006.285.06:16:35.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:16:35.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:16:35.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:16:35.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:16:35.77$vck44/va=7,4 2006.285.06:16:35.77#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.06:16:35.77#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.06:16:35.77#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:35.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:16:35.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:16:35.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:16:35.82#ibcon#enter wrdev, iclass 4, count 2 2006.285.06:16:35.82#ibcon#first serial, iclass 4, count 2 2006.285.06:16:35.82#ibcon#enter sib2, iclass 4, count 2 2006.285.06:16:35.82#ibcon#flushed, iclass 4, count 2 2006.285.06:16:35.82#ibcon#about to write, iclass 4, count 2 2006.285.06:16:35.82#ibcon#wrote, iclass 4, count 2 2006.285.06:16:35.82#ibcon#about to read 3, iclass 4, count 2 2006.285.06:16:35.84#ibcon#read 3, iclass 4, count 2 2006.285.06:16:35.84#ibcon#about to read 4, iclass 4, count 2 2006.285.06:16:35.84#ibcon#read 4, iclass 4, count 2 2006.285.06:16:35.84#ibcon#about to read 5, iclass 4, count 2 2006.285.06:16:35.84#ibcon#read 5, iclass 4, count 2 2006.285.06:16:35.84#ibcon#about to read 6, iclass 4, count 2 2006.285.06:16:35.84#ibcon#read 6, iclass 4, count 2 2006.285.06:16:35.84#ibcon#end of sib2, iclass 4, count 2 2006.285.06:16:35.84#ibcon#*mode == 0, iclass 4, count 2 2006.285.06:16:35.84#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.06:16:35.84#ibcon#[25=AT07-04\r\n] 2006.285.06:16:35.84#ibcon#*before write, iclass 4, count 2 2006.285.06:16:35.84#ibcon#enter sib2, iclass 4, count 2 2006.285.06:16:35.84#ibcon#flushed, iclass 4, count 2 2006.285.06:16:35.84#ibcon#about to write, iclass 4, count 2 2006.285.06:16:35.84#ibcon#wrote, iclass 4, count 2 2006.285.06:16:35.84#ibcon#about to read 3, iclass 4, count 2 2006.285.06:16:35.87#ibcon#read 3, iclass 4, count 2 2006.285.06:16:35.87#ibcon#about to read 4, iclass 4, count 2 2006.285.06:16:35.87#ibcon#read 4, iclass 4, count 2 2006.285.06:16:35.87#ibcon#about to read 5, iclass 4, count 2 2006.285.06:16:35.87#ibcon#read 5, iclass 4, count 2 2006.285.06:16:35.87#ibcon#about to read 6, iclass 4, count 2 2006.285.06:16:35.87#ibcon#read 6, iclass 4, count 2 2006.285.06:16:35.87#ibcon#end of sib2, iclass 4, count 2 2006.285.06:16:35.87#ibcon#*after write, iclass 4, count 2 2006.285.06:16:35.87#ibcon#*before return 0, iclass 4, count 2 2006.285.06:16:35.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:16:35.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:16:35.87#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.06:16:35.87#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:35.87#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:16:35.99#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:16:35.99#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:16:35.99#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:16:35.99#ibcon#first serial, iclass 4, count 0 2006.285.06:16:35.99#ibcon#enter sib2, iclass 4, count 0 2006.285.06:16:35.99#ibcon#flushed, iclass 4, count 0 2006.285.06:16:35.99#ibcon#about to write, iclass 4, count 0 2006.285.06:16:35.99#ibcon#wrote, iclass 4, count 0 2006.285.06:16:35.99#ibcon#about to read 3, iclass 4, count 0 2006.285.06:16:36.01#ibcon#read 3, iclass 4, count 0 2006.285.06:16:36.01#ibcon#about to read 4, iclass 4, count 0 2006.285.06:16:36.01#ibcon#read 4, iclass 4, count 0 2006.285.06:16:36.01#ibcon#about to read 5, iclass 4, count 0 2006.285.06:16:36.01#ibcon#read 5, iclass 4, count 0 2006.285.06:16:36.01#ibcon#about to read 6, iclass 4, count 0 2006.285.06:16:36.01#ibcon#read 6, iclass 4, count 0 2006.285.06:16:36.01#ibcon#end of sib2, iclass 4, count 0 2006.285.06:16:36.01#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:16:36.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:16:36.01#ibcon#[25=USB\r\n] 2006.285.06:16:36.01#ibcon#*before write, iclass 4, count 0 2006.285.06:16:36.01#ibcon#enter sib2, iclass 4, count 0 2006.285.06:16:36.01#ibcon#flushed, iclass 4, count 0 2006.285.06:16:36.01#ibcon#about to write, iclass 4, count 0 2006.285.06:16:36.01#ibcon#wrote, iclass 4, count 0 2006.285.06:16:36.01#ibcon#about to read 3, iclass 4, count 0 2006.285.06:16:36.04#ibcon#read 3, iclass 4, count 0 2006.285.06:16:36.04#ibcon#about to read 4, iclass 4, count 0 2006.285.06:16:36.04#ibcon#read 4, iclass 4, count 0 2006.285.06:16:36.04#ibcon#about to read 5, iclass 4, count 0 2006.285.06:16:36.04#ibcon#read 5, iclass 4, count 0 2006.285.06:16:36.04#ibcon#about to read 6, iclass 4, count 0 2006.285.06:16:36.04#ibcon#read 6, iclass 4, count 0 2006.285.06:16:36.04#ibcon#end of sib2, iclass 4, count 0 2006.285.06:16:36.04#ibcon#*after write, iclass 4, count 0 2006.285.06:16:36.04#ibcon#*before return 0, iclass 4, count 0 2006.285.06:16:36.04#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:16:36.04#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:16:36.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:16:36.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:16:36.04$vck44/valo=8,884.99 2006.285.06:16:36.04#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.06:16:36.04#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.06:16:36.04#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:36.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:16:36.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:16:36.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:16:36.04#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:16:36.04#ibcon#first serial, iclass 6, count 0 2006.285.06:16:36.04#ibcon#enter sib2, iclass 6, count 0 2006.285.06:16:36.04#ibcon#flushed, iclass 6, count 0 2006.285.06:16:36.04#ibcon#about to write, iclass 6, count 0 2006.285.06:16:36.04#ibcon#wrote, iclass 6, count 0 2006.285.06:16:36.04#ibcon#about to read 3, iclass 6, count 0 2006.285.06:16:36.06#ibcon#read 3, iclass 6, count 0 2006.285.06:16:36.06#ibcon#about to read 4, iclass 6, count 0 2006.285.06:16:36.06#ibcon#read 4, iclass 6, count 0 2006.285.06:16:36.06#ibcon#about to read 5, iclass 6, count 0 2006.285.06:16:36.06#ibcon#read 5, iclass 6, count 0 2006.285.06:16:36.06#ibcon#about to read 6, iclass 6, count 0 2006.285.06:16:36.06#ibcon#read 6, iclass 6, count 0 2006.285.06:16:36.06#ibcon#end of sib2, iclass 6, count 0 2006.285.06:16:36.06#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:16:36.06#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:16:36.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:16:36.06#ibcon#*before write, iclass 6, count 0 2006.285.06:16:36.06#ibcon#enter sib2, iclass 6, count 0 2006.285.06:16:36.06#ibcon#flushed, iclass 6, count 0 2006.285.06:16:36.06#ibcon#about to write, iclass 6, count 0 2006.285.06:16:36.06#ibcon#wrote, iclass 6, count 0 2006.285.06:16:36.06#ibcon#about to read 3, iclass 6, count 0 2006.285.06:16:36.10#ibcon#read 3, iclass 6, count 0 2006.285.06:16:36.10#ibcon#about to read 4, iclass 6, count 0 2006.285.06:16:36.10#ibcon#read 4, iclass 6, count 0 2006.285.06:16:36.10#ibcon#about to read 5, iclass 6, count 0 2006.285.06:16:36.10#ibcon#read 5, iclass 6, count 0 2006.285.06:16:36.10#ibcon#about to read 6, iclass 6, count 0 2006.285.06:16:36.10#ibcon#read 6, iclass 6, count 0 2006.285.06:16:36.10#ibcon#end of sib2, iclass 6, count 0 2006.285.06:16:36.10#ibcon#*after write, iclass 6, count 0 2006.285.06:16:36.10#ibcon#*before return 0, iclass 6, count 0 2006.285.06:16:36.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:16:36.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:16:36.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:16:36.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:16:36.10$vck44/va=8,3 2006.285.06:16:36.10#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.06:16:36.10#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.06:16:36.10#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:36.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:16:36.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:16:36.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:16:36.16#ibcon#enter wrdev, iclass 10, count 2 2006.285.06:16:36.16#ibcon#first serial, iclass 10, count 2 2006.285.06:16:36.16#ibcon#enter sib2, iclass 10, count 2 2006.285.06:16:36.16#ibcon#flushed, iclass 10, count 2 2006.285.06:16:36.16#ibcon#about to write, iclass 10, count 2 2006.285.06:16:36.16#ibcon#wrote, iclass 10, count 2 2006.285.06:16:36.16#ibcon#about to read 3, iclass 10, count 2 2006.285.06:16:36.18#ibcon#read 3, iclass 10, count 2 2006.285.06:16:36.18#ibcon#about to read 4, iclass 10, count 2 2006.285.06:16:36.18#ibcon#read 4, iclass 10, count 2 2006.285.06:16:36.18#ibcon#about to read 5, iclass 10, count 2 2006.285.06:16:36.18#ibcon#read 5, iclass 10, count 2 2006.285.06:16:36.18#ibcon#about to read 6, iclass 10, count 2 2006.285.06:16:36.18#ibcon#read 6, iclass 10, count 2 2006.285.06:16:36.18#ibcon#end of sib2, iclass 10, count 2 2006.285.06:16:36.18#ibcon#*mode == 0, iclass 10, count 2 2006.285.06:16:36.18#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.06:16:36.18#ibcon#[25=AT08-03\r\n] 2006.285.06:16:36.18#ibcon#*before write, iclass 10, count 2 2006.285.06:16:36.18#ibcon#enter sib2, iclass 10, count 2 2006.285.06:16:36.18#ibcon#flushed, iclass 10, count 2 2006.285.06:16:36.18#ibcon#about to write, iclass 10, count 2 2006.285.06:16:36.18#ibcon#wrote, iclass 10, count 2 2006.285.06:16:36.18#ibcon#about to read 3, iclass 10, count 2 2006.285.06:16:36.21#ibcon#read 3, iclass 10, count 2 2006.285.06:16:36.21#ibcon#about to read 4, iclass 10, count 2 2006.285.06:16:36.21#ibcon#read 4, iclass 10, count 2 2006.285.06:16:36.21#ibcon#about to read 5, iclass 10, count 2 2006.285.06:16:36.21#ibcon#read 5, iclass 10, count 2 2006.285.06:16:36.21#ibcon#about to read 6, iclass 10, count 2 2006.285.06:16:36.21#ibcon#read 6, iclass 10, count 2 2006.285.06:16:36.21#ibcon#end of sib2, iclass 10, count 2 2006.285.06:16:36.21#ibcon#*after write, iclass 10, count 2 2006.285.06:16:36.21#ibcon#*before return 0, iclass 10, count 2 2006.285.06:16:36.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:16:36.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:16:36.21#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.06:16:36.21#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:36.21#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:16:36.33#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:16:36.33#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:16:36.33#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:16:36.33#ibcon#first serial, iclass 10, count 0 2006.285.06:16:36.33#ibcon#enter sib2, iclass 10, count 0 2006.285.06:16:36.33#ibcon#flushed, iclass 10, count 0 2006.285.06:16:36.33#ibcon#about to write, iclass 10, count 0 2006.285.06:16:36.33#ibcon#wrote, iclass 10, count 0 2006.285.06:16:36.33#ibcon#about to read 3, iclass 10, count 0 2006.285.06:16:36.35#ibcon#read 3, iclass 10, count 0 2006.285.06:16:36.35#ibcon#about to read 4, iclass 10, count 0 2006.285.06:16:36.35#ibcon#read 4, iclass 10, count 0 2006.285.06:16:36.35#ibcon#about to read 5, iclass 10, count 0 2006.285.06:16:36.35#ibcon#read 5, iclass 10, count 0 2006.285.06:16:36.35#ibcon#about to read 6, iclass 10, count 0 2006.285.06:16:36.35#ibcon#read 6, iclass 10, count 0 2006.285.06:16:36.35#ibcon#end of sib2, iclass 10, count 0 2006.285.06:16:36.35#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:16:36.35#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:16:36.35#ibcon#[25=USB\r\n] 2006.285.06:16:36.35#ibcon#*before write, iclass 10, count 0 2006.285.06:16:36.35#ibcon#enter sib2, iclass 10, count 0 2006.285.06:16:36.35#ibcon#flushed, iclass 10, count 0 2006.285.06:16:36.35#ibcon#about to write, iclass 10, count 0 2006.285.06:16:36.35#ibcon#wrote, iclass 10, count 0 2006.285.06:16:36.35#ibcon#about to read 3, iclass 10, count 0 2006.285.06:16:36.36#abcon#<5=/04 4.3 7.1 25.02 681014.1\r\n> 2006.285.06:16:36.38#abcon#{5=INTERFACE CLEAR} 2006.285.06:16:36.38#ibcon#read 3, iclass 10, count 0 2006.285.06:16:36.38#ibcon#about to read 4, iclass 10, count 0 2006.285.06:16:36.38#ibcon#read 4, iclass 10, count 0 2006.285.06:16:36.38#ibcon#about to read 5, iclass 10, count 0 2006.285.06:16:36.38#ibcon#read 5, iclass 10, count 0 2006.285.06:16:36.38#ibcon#about to read 6, iclass 10, count 0 2006.285.06:16:36.38#ibcon#read 6, iclass 10, count 0 2006.285.06:16:36.38#ibcon#end of sib2, iclass 10, count 0 2006.285.06:16:36.38#ibcon#*after write, iclass 10, count 0 2006.285.06:16:36.38#ibcon#*before return 0, iclass 10, count 0 2006.285.06:16:36.38#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:16:36.38#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:16:36.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:16:36.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:16:36.38$vck44/vblo=1,629.99 2006.285.06:16:36.38#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.06:16:36.38#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.06:16:36.38#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:36.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:16:36.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:16:36.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:16:36.38#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:16:36.38#ibcon#first serial, iclass 15, count 0 2006.285.06:16:36.38#ibcon#enter sib2, iclass 15, count 0 2006.285.06:16:36.38#ibcon#flushed, iclass 15, count 0 2006.285.06:16:36.38#ibcon#about to write, iclass 15, count 0 2006.285.06:16:36.38#ibcon#wrote, iclass 15, count 0 2006.285.06:16:36.38#ibcon#about to read 3, iclass 15, count 0 2006.285.06:16:36.40#ibcon#read 3, iclass 15, count 0 2006.285.06:16:36.40#ibcon#about to read 4, iclass 15, count 0 2006.285.06:16:36.40#ibcon#read 4, iclass 15, count 0 2006.285.06:16:36.40#ibcon#about to read 5, iclass 15, count 0 2006.285.06:16:36.40#ibcon#read 5, iclass 15, count 0 2006.285.06:16:36.40#ibcon#about to read 6, iclass 15, count 0 2006.285.06:16:36.40#ibcon#read 6, iclass 15, count 0 2006.285.06:16:36.40#ibcon#end of sib2, iclass 15, count 0 2006.285.06:16:36.40#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:16:36.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:16:36.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:16:36.40#ibcon#*before write, iclass 15, count 0 2006.285.06:16:36.40#ibcon#enter sib2, iclass 15, count 0 2006.285.06:16:36.40#ibcon#flushed, iclass 15, count 0 2006.285.06:16:36.40#ibcon#about to write, iclass 15, count 0 2006.285.06:16:36.40#ibcon#wrote, iclass 15, count 0 2006.285.06:16:36.40#ibcon#about to read 3, iclass 15, count 0 2006.285.06:16:36.44#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:16:36.44#ibcon#read 3, iclass 15, count 0 2006.285.06:16:36.44#ibcon#about to read 4, iclass 15, count 0 2006.285.06:16:36.44#ibcon#read 4, iclass 15, count 0 2006.285.06:16:36.44#ibcon#about to read 5, iclass 15, count 0 2006.285.06:16:36.44#ibcon#read 5, iclass 15, count 0 2006.285.06:16:36.44#ibcon#about to read 6, iclass 15, count 0 2006.285.06:16:36.44#ibcon#read 6, iclass 15, count 0 2006.285.06:16:36.44#ibcon#end of sib2, iclass 15, count 0 2006.285.06:16:36.44#ibcon#*after write, iclass 15, count 0 2006.285.06:16:36.44#ibcon#*before return 0, iclass 15, count 0 2006.285.06:16:36.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:16:36.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:16:36.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:16:36.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:16:36.44$vck44/vb=1,4 2006.285.06:16:36.44#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.06:16:36.44#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.06:16:36.44#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:36.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:16:36.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:16:36.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:16:36.44#ibcon#enter wrdev, iclass 18, count 2 2006.285.06:16:36.44#ibcon#first serial, iclass 18, count 2 2006.285.06:16:36.44#ibcon#enter sib2, iclass 18, count 2 2006.285.06:16:36.44#ibcon#flushed, iclass 18, count 2 2006.285.06:16:36.44#ibcon#about to write, iclass 18, count 2 2006.285.06:16:36.44#ibcon#wrote, iclass 18, count 2 2006.285.06:16:36.44#ibcon#about to read 3, iclass 18, count 2 2006.285.06:16:36.46#ibcon#read 3, iclass 18, count 2 2006.285.06:16:36.46#ibcon#about to read 4, iclass 18, count 2 2006.285.06:16:36.46#ibcon#read 4, iclass 18, count 2 2006.285.06:16:36.46#ibcon#about to read 5, iclass 18, count 2 2006.285.06:16:36.46#ibcon#read 5, iclass 18, count 2 2006.285.06:16:36.46#ibcon#about to read 6, iclass 18, count 2 2006.285.06:16:36.46#ibcon#read 6, iclass 18, count 2 2006.285.06:16:36.46#ibcon#end of sib2, iclass 18, count 2 2006.285.06:16:36.46#ibcon#*mode == 0, iclass 18, count 2 2006.285.06:16:36.46#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.06:16:36.46#ibcon#[27=AT01-04\r\n] 2006.285.06:16:36.46#ibcon#*before write, iclass 18, count 2 2006.285.06:16:36.46#ibcon#enter sib2, iclass 18, count 2 2006.285.06:16:36.46#ibcon#flushed, iclass 18, count 2 2006.285.06:16:36.46#ibcon#about to write, iclass 18, count 2 2006.285.06:16:36.46#ibcon#wrote, iclass 18, count 2 2006.285.06:16:36.46#ibcon#about to read 3, iclass 18, count 2 2006.285.06:16:36.49#ibcon#read 3, iclass 18, count 2 2006.285.06:16:36.49#ibcon#about to read 4, iclass 18, count 2 2006.285.06:16:36.49#ibcon#read 4, iclass 18, count 2 2006.285.06:16:36.49#ibcon#about to read 5, iclass 18, count 2 2006.285.06:16:36.49#ibcon#read 5, iclass 18, count 2 2006.285.06:16:36.49#ibcon#about to read 6, iclass 18, count 2 2006.285.06:16:36.49#ibcon#read 6, iclass 18, count 2 2006.285.06:16:36.49#ibcon#end of sib2, iclass 18, count 2 2006.285.06:16:36.49#ibcon#*after write, iclass 18, count 2 2006.285.06:16:36.49#ibcon#*before return 0, iclass 18, count 2 2006.285.06:16:36.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:16:36.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:16:36.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.06:16:36.49#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:36.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:16:36.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:16:36.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:16:36.61#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:16:36.61#ibcon#first serial, iclass 18, count 0 2006.285.06:16:36.61#ibcon#enter sib2, iclass 18, count 0 2006.285.06:16:36.61#ibcon#flushed, iclass 18, count 0 2006.285.06:16:36.61#ibcon#about to write, iclass 18, count 0 2006.285.06:16:36.61#ibcon#wrote, iclass 18, count 0 2006.285.06:16:36.61#ibcon#about to read 3, iclass 18, count 0 2006.285.06:16:36.63#ibcon#read 3, iclass 18, count 0 2006.285.06:16:36.63#ibcon#about to read 4, iclass 18, count 0 2006.285.06:16:36.63#ibcon#read 4, iclass 18, count 0 2006.285.06:16:36.63#ibcon#about to read 5, iclass 18, count 0 2006.285.06:16:36.63#ibcon#read 5, iclass 18, count 0 2006.285.06:16:36.63#ibcon#about to read 6, iclass 18, count 0 2006.285.06:16:36.63#ibcon#read 6, iclass 18, count 0 2006.285.06:16:36.63#ibcon#end of sib2, iclass 18, count 0 2006.285.06:16:36.63#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:16:36.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:16:36.63#ibcon#[27=USB\r\n] 2006.285.06:16:36.63#ibcon#*before write, iclass 18, count 0 2006.285.06:16:36.63#ibcon#enter sib2, iclass 18, count 0 2006.285.06:16:36.63#ibcon#flushed, iclass 18, count 0 2006.285.06:16:36.63#ibcon#about to write, iclass 18, count 0 2006.285.06:16:36.63#ibcon#wrote, iclass 18, count 0 2006.285.06:16:36.63#ibcon#about to read 3, iclass 18, count 0 2006.285.06:16:36.66#ibcon#read 3, iclass 18, count 0 2006.285.06:16:36.66#ibcon#about to read 4, iclass 18, count 0 2006.285.06:16:36.66#ibcon#read 4, iclass 18, count 0 2006.285.06:16:36.66#ibcon#about to read 5, iclass 18, count 0 2006.285.06:16:36.66#ibcon#read 5, iclass 18, count 0 2006.285.06:16:36.66#ibcon#about to read 6, iclass 18, count 0 2006.285.06:16:36.66#ibcon#read 6, iclass 18, count 0 2006.285.06:16:36.66#ibcon#end of sib2, iclass 18, count 0 2006.285.06:16:36.66#ibcon#*after write, iclass 18, count 0 2006.285.06:16:36.66#ibcon#*before return 0, iclass 18, count 0 2006.285.06:16:36.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:16:36.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:16:36.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:16:36.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:16:36.66$vck44/vblo=2,634.99 2006.285.06:16:36.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.06:16:36.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.06:16:36.66#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:36.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:16:36.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:16:36.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:16:36.66#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:16:36.66#ibcon#first serial, iclass 20, count 0 2006.285.06:16:36.66#ibcon#enter sib2, iclass 20, count 0 2006.285.06:16:36.66#ibcon#flushed, iclass 20, count 0 2006.285.06:16:36.66#ibcon#about to write, iclass 20, count 0 2006.285.06:16:36.66#ibcon#wrote, iclass 20, count 0 2006.285.06:16:36.66#ibcon#about to read 3, iclass 20, count 0 2006.285.06:16:36.68#ibcon#read 3, iclass 20, count 0 2006.285.06:16:36.68#ibcon#about to read 4, iclass 20, count 0 2006.285.06:16:36.68#ibcon#read 4, iclass 20, count 0 2006.285.06:16:36.68#ibcon#about to read 5, iclass 20, count 0 2006.285.06:16:36.68#ibcon#read 5, iclass 20, count 0 2006.285.06:16:36.68#ibcon#about to read 6, iclass 20, count 0 2006.285.06:16:36.68#ibcon#read 6, iclass 20, count 0 2006.285.06:16:36.68#ibcon#end of sib2, iclass 20, count 0 2006.285.06:16:36.68#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:16:36.68#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:16:36.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:16:36.68#ibcon#*before write, iclass 20, count 0 2006.285.06:16:36.68#ibcon#enter sib2, iclass 20, count 0 2006.285.06:16:36.68#ibcon#flushed, iclass 20, count 0 2006.285.06:16:36.68#ibcon#about to write, iclass 20, count 0 2006.285.06:16:36.68#ibcon#wrote, iclass 20, count 0 2006.285.06:16:36.68#ibcon#about to read 3, iclass 20, count 0 2006.285.06:16:36.72#ibcon#read 3, iclass 20, count 0 2006.285.06:16:36.72#ibcon#about to read 4, iclass 20, count 0 2006.285.06:16:36.72#ibcon#read 4, iclass 20, count 0 2006.285.06:16:36.72#ibcon#about to read 5, iclass 20, count 0 2006.285.06:16:36.72#ibcon#read 5, iclass 20, count 0 2006.285.06:16:36.72#ibcon#about to read 6, iclass 20, count 0 2006.285.06:16:36.72#ibcon#read 6, iclass 20, count 0 2006.285.06:16:36.72#ibcon#end of sib2, iclass 20, count 0 2006.285.06:16:36.72#ibcon#*after write, iclass 20, count 0 2006.285.06:16:36.72#ibcon#*before return 0, iclass 20, count 0 2006.285.06:16:36.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:16:36.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:16:36.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:16:36.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:16:36.72$vck44/vb=2,5 2006.285.06:16:36.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.06:16:36.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.06:16:36.72#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:36.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:16:36.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:16:36.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:16:36.79#ibcon#enter wrdev, iclass 22, count 2 2006.285.06:16:36.79#ibcon#first serial, iclass 22, count 2 2006.285.06:16:36.79#ibcon#enter sib2, iclass 22, count 2 2006.285.06:16:36.79#ibcon#flushed, iclass 22, count 2 2006.285.06:16:36.79#ibcon#about to write, iclass 22, count 2 2006.285.06:16:36.79#ibcon#wrote, iclass 22, count 2 2006.285.06:16:36.79#ibcon#about to read 3, iclass 22, count 2 2006.285.06:16:36.81#ibcon#read 3, iclass 22, count 2 2006.285.06:16:36.81#ibcon#about to read 4, iclass 22, count 2 2006.285.06:16:36.81#ibcon#read 4, iclass 22, count 2 2006.285.06:16:36.81#ibcon#about to read 5, iclass 22, count 2 2006.285.06:16:36.81#ibcon#read 5, iclass 22, count 2 2006.285.06:16:36.81#ibcon#about to read 6, iclass 22, count 2 2006.285.06:16:36.81#ibcon#read 6, iclass 22, count 2 2006.285.06:16:36.81#ibcon#end of sib2, iclass 22, count 2 2006.285.06:16:36.81#ibcon#*mode == 0, iclass 22, count 2 2006.285.06:16:36.81#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.06:16:36.81#ibcon#[27=AT02-05\r\n] 2006.285.06:16:36.81#ibcon#*before write, iclass 22, count 2 2006.285.06:16:36.81#ibcon#enter sib2, iclass 22, count 2 2006.285.06:16:36.81#ibcon#flushed, iclass 22, count 2 2006.285.06:16:36.81#ibcon#about to write, iclass 22, count 2 2006.285.06:16:36.81#ibcon#wrote, iclass 22, count 2 2006.285.06:16:36.81#ibcon#about to read 3, iclass 22, count 2 2006.285.06:16:36.84#ibcon#read 3, iclass 22, count 2 2006.285.06:16:36.84#ibcon#about to read 4, iclass 22, count 2 2006.285.06:16:36.84#ibcon#read 4, iclass 22, count 2 2006.285.06:16:36.84#ibcon#about to read 5, iclass 22, count 2 2006.285.06:16:36.84#ibcon#read 5, iclass 22, count 2 2006.285.06:16:36.84#ibcon#about to read 6, iclass 22, count 2 2006.285.06:16:36.84#ibcon#read 6, iclass 22, count 2 2006.285.06:16:36.84#ibcon#end of sib2, iclass 22, count 2 2006.285.06:16:36.84#ibcon#*after write, iclass 22, count 2 2006.285.06:16:36.84#ibcon#*before return 0, iclass 22, count 2 2006.285.06:16:36.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:16:36.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:16:36.84#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.06:16:36.84#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:36.84#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:16:36.96#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:16:36.96#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:16:36.96#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:16:36.96#ibcon#first serial, iclass 22, count 0 2006.285.06:16:36.96#ibcon#enter sib2, iclass 22, count 0 2006.285.06:16:36.96#ibcon#flushed, iclass 22, count 0 2006.285.06:16:36.96#ibcon#about to write, iclass 22, count 0 2006.285.06:16:36.96#ibcon#wrote, iclass 22, count 0 2006.285.06:16:36.96#ibcon#about to read 3, iclass 22, count 0 2006.285.06:16:36.98#ibcon#read 3, iclass 22, count 0 2006.285.06:16:36.98#ibcon#about to read 4, iclass 22, count 0 2006.285.06:16:36.98#ibcon#read 4, iclass 22, count 0 2006.285.06:16:36.98#ibcon#about to read 5, iclass 22, count 0 2006.285.06:16:36.98#ibcon#read 5, iclass 22, count 0 2006.285.06:16:36.98#ibcon#about to read 6, iclass 22, count 0 2006.285.06:16:36.98#ibcon#read 6, iclass 22, count 0 2006.285.06:16:36.98#ibcon#end of sib2, iclass 22, count 0 2006.285.06:16:36.98#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:16:36.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:16:36.98#ibcon#[27=USB\r\n] 2006.285.06:16:36.98#ibcon#*before write, iclass 22, count 0 2006.285.06:16:36.98#ibcon#enter sib2, iclass 22, count 0 2006.285.06:16:36.98#ibcon#flushed, iclass 22, count 0 2006.285.06:16:36.98#ibcon#about to write, iclass 22, count 0 2006.285.06:16:36.98#ibcon#wrote, iclass 22, count 0 2006.285.06:16:36.98#ibcon#about to read 3, iclass 22, count 0 2006.285.06:16:37.01#ibcon#read 3, iclass 22, count 0 2006.285.06:16:37.01#ibcon#about to read 4, iclass 22, count 0 2006.285.06:16:37.01#ibcon#read 4, iclass 22, count 0 2006.285.06:16:37.01#ibcon#about to read 5, iclass 22, count 0 2006.285.06:16:37.01#ibcon#read 5, iclass 22, count 0 2006.285.06:16:37.01#ibcon#about to read 6, iclass 22, count 0 2006.285.06:16:37.01#ibcon#read 6, iclass 22, count 0 2006.285.06:16:37.01#ibcon#end of sib2, iclass 22, count 0 2006.285.06:16:37.01#ibcon#*after write, iclass 22, count 0 2006.285.06:16:37.01#ibcon#*before return 0, iclass 22, count 0 2006.285.06:16:37.01#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:16:37.01#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:16:37.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:16:37.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:16:37.01$vck44/vblo=3,649.99 2006.285.06:16:37.01#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.06:16:37.01#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.06:16:37.01#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:37.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:16:37.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:16:37.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:16:37.01#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:16:37.01#ibcon#first serial, iclass 24, count 0 2006.285.06:16:37.01#ibcon#enter sib2, iclass 24, count 0 2006.285.06:16:37.01#ibcon#flushed, iclass 24, count 0 2006.285.06:16:37.01#ibcon#about to write, iclass 24, count 0 2006.285.06:16:37.01#ibcon#wrote, iclass 24, count 0 2006.285.06:16:37.01#ibcon#about to read 3, iclass 24, count 0 2006.285.06:16:37.03#ibcon#read 3, iclass 24, count 0 2006.285.06:16:37.03#ibcon#about to read 4, iclass 24, count 0 2006.285.06:16:37.03#ibcon#read 4, iclass 24, count 0 2006.285.06:16:37.03#ibcon#about to read 5, iclass 24, count 0 2006.285.06:16:37.03#ibcon#read 5, iclass 24, count 0 2006.285.06:16:37.03#ibcon#about to read 6, iclass 24, count 0 2006.285.06:16:37.03#ibcon#read 6, iclass 24, count 0 2006.285.06:16:37.03#ibcon#end of sib2, iclass 24, count 0 2006.285.06:16:37.03#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:16:37.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:16:37.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:16:37.03#ibcon#*before write, iclass 24, count 0 2006.285.06:16:37.03#ibcon#enter sib2, iclass 24, count 0 2006.285.06:16:37.03#ibcon#flushed, iclass 24, count 0 2006.285.06:16:37.03#ibcon#about to write, iclass 24, count 0 2006.285.06:16:37.03#ibcon#wrote, iclass 24, count 0 2006.285.06:16:37.03#ibcon#about to read 3, iclass 24, count 0 2006.285.06:16:37.07#ibcon#read 3, iclass 24, count 0 2006.285.06:16:37.07#ibcon#about to read 4, iclass 24, count 0 2006.285.06:16:37.07#ibcon#read 4, iclass 24, count 0 2006.285.06:16:37.07#ibcon#about to read 5, iclass 24, count 0 2006.285.06:16:37.07#ibcon#read 5, iclass 24, count 0 2006.285.06:16:37.07#ibcon#about to read 6, iclass 24, count 0 2006.285.06:16:37.07#ibcon#read 6, iclass 24, count 0 2006.285.06:16:37.07#ibcon#end of sib2, iclass 24, count 0 2006.285.06:16:37.07#ibcon#*after write, iclass 24, count 0 2006.285.06:16:37.07#ibcon#*before return 0, iclass 24, count 0 2006.285.06:16:37.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:16:37.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:16:37.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:16:37.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:16:37.07$vck44/vb=3,4 2006.285.06:16:37.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.06:16:37.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.06:16:37.07#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:37.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:16:37.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:16:37.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:16:37.13#ibcon#enter wrdev, iclass 26, count 2 2006.285.06:16:37.13#ibcon#first serial, iclass 26, count 2 2006.285.06:16:37.13#ibcon#enter sib2, iclass 26, count 2 2006.285.06:16:37.13#ibcon#flushed, iclass 26, count 2 2006.285.06:16:37.13#ibcon#about to write, iclass 26, count 2 2006.285.06:16:37.13#ibcon#wrote, iclass 26, count 2 2006.285.06:16:37.13#ibcon#about to read 3, iclass 26, count 2 2006.285.06:16:37.15#ibcon#read 3, iclass 26, count 2 2006.285.06:16:37.15#ibcon#about to read 4, iclass 26, count 2 2006.285.06:16:37.15#ibcon#read 4, iclass 26, count 2 2006.285.06:16:37.15#ibcon#about to read 5, iclass 26, count 2 2006.285.06:16:37.15#ibcon#read 5, iclass 26, count 2 2006.285.06:16:37.15#ibcon#about to read 6, iclass 26, count 2 2006.285.06:16:37.15#ibcon#read 6, iclass 26, count 2 2006.285.06:16:37.15#ibcon#end of sib2, iclass 26, count 2 2006.285.06:16:37.15#ibcon#*mode == 0, iclass 26, count 2 2006.285.06:16:37.15#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.06:16:37.15#ibcon#[27=AT03-04\r\n] 2006.285.06:16:37.15#ibcon#*before write, iclass 26, count 2 2006.285.06:16:37.15#ibcon#enter sib2, iclass 26, count 2 2006.285.06:16:37.15#ibcon#flushed, iclass 26, count 2 2006.285.06:16:37.15#ibcon#about to write, iclass 26, count 2 2006.285.06:16:37.15#ibcon#wrote, iclass 26, count 2 2006.285.06:16:37.15#ibcon#about to read 3, iclass 26, count 2 2006.285.06:16:37.18#ibcon#read 3, iclass 26, count 2 2006.285.06:16:37.18#ibcon#about to read 4, iclass 26, count 2 2006.285.06:16:37.18#ibcon#read 4, iclass 26, count 2 2006.285.06:16:37.18#ibcon#about to read 5, iclass 26, count 2 2006.285.06:16:37.18#ibcon#read 5, iclass 26, count 2 2006.285.06:16:37.18#ibcon#about to read 6, iclass 26, count 2 2006.285.06:16:37.18#ibcon#read 6, iclass 26, count 2 2006.285.06:16:37.18#ibcon#end of sib2, iclass 26, count 2 2006.285.06:16:37.18#ibcon#*after write, iclass 26, count 2 2006.285.06:16:37.18#ibcon#*before return 0, iclass 26, count 2 2006.285.06:16:37.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:16:37.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:16:37.18#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.06:16:37.18#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:37.18#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:16:37.30#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:16:37.30#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:16:37.30#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:16:37.30#ibcon#first serial, iclass 26, count 0 2006.285.06:16:37.30#ibcon#enter sib2, iclass 26, count 0 2006.285.06:16:37.30#ibcon#flushed, iclass 26, count 0 2006.285.06:16:37.30#ibcon#about to write, iclass 26, count 0 2006.285.06:16:37.30#ibcon#wrote, iclass 26, count 0 2006.285.06:16:37.30#ibcon#about to read 3, iclass 26, count 0 2006.285.06:16:37.32#ibcon#read 3, iclass 26, count 0 2006.285.06:16:37.32#ibcon#about to read 4, iclass 26, count 0 2006.285.06:16:37.32#ibcon#read 4, iclass 26, count 0 2006.285.06:16:37.32#ibcon#about to read 5, iclass 26, count 0 2006.285.06:16:37.32#ibcon#read 5, iclass 26, count 0 2006.285.06:16:37.32#ibcon#about to read 6, iclass 26, count 0 2006.285.06:16:37.32#ibcon#read 6, iclass 26, count 0 2006.285.06:16:37.32#ibcon#end of sib2, iclass 26, count 0 2006.285.06:16:37.32#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:16:37.32#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:16:37.32#ibcon#[27=USB\r\n] 2006.285.06:16:37.32#ibcon#*before write, iclass 26, count 0 2006.285.06:16:37.32#ibcon#enter sib2, iclass 26, count 0 2006.285.06:16:37.32#ibcon#flushed, iclass 26, count 0 2006.285.06:16:37.32#ibcon#about to write, iclass 26, count 0 2006.285.06:16:37.32#ibcon#wrote, iclass 26, count 0 2006.285.06:16:37.32#ibcon#about to read 3, iclass 26, count 0 2006.285.06:16:37.35#ibcon#read 3, iclass 26, count 0 2006.285.06:16:37.35#ibcon#about to read 4, iclass 26, count 0 2006.285.06:16:37.35#ibcon#read 4, iclass 26, count 0 2006.285.06:16:37.35#ibcon#about to read 5, iclass 26, count 0 2006.285.06:16:37.35#ibcon#read 5, iclass 26, count 0 2006.285.06:16:37.35#ibcon#about to read 6, iclass 26, count 0 2006.285.06:16:37.35#ibcon#read 6, iclass 26, count 0 2006.285.06:16:37.35#ibcon#end of sib2, iclass 26, count 0 2006.285.06:16:37.35#ibcon#*after write, iclass 26, count 0 2006.285.06:16:37.35#ibcon#*before return 0, iclass 26, count 0 2006.285.06:16:37.35#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:16:37.35#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:16:37.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:16:37.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:16:37.35$vck44/vblo=4,679.99 2006.285.06:16:37.35#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.06:16:37.35#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.06:16:37.35#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:37.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:16:37.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:16:37.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:16:37.35#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:16:37.35#ibcon#first serial, iclass 28, count 0 2006.285.06:16:37.35#ibcon#enter sib2, iclass 28, count 0 2006.285.06:16:37.35#ibcon#flushed, iclass 28, count 0 2006.285.06:16:37.35#ibcon#about to write, iclass 28, count 0 2006.285.06:16:37.35#ibcon#wrote, iclass 28, count 0 2006.285.06:16:37.35#ibcon#about to read 3, iclass 28, count 0 2006.285.06:16:37.37#ibcon#read 3, iclass 28, count 0 2006.285.06:16:37.37#ibcon#about to read 4, iclass 28, count 0 2006.285.06:16:37.37#ibcon#read 4, iclass 28, count 0 2006.285.06:16:37.37#ibcon#about to read 5, iclass 28, count 0 2006.285.06:16:37.37#ibcon#read 5, iclass 28, count 0 2006.285.06:16:37.37#ibcon#about to read 6, iclass 28, count 0 2006.285.06:16:37.37#ibcon#read 6, iclass 28, count 0 2006.285.06:16:37.37#ibcon#end of sib2, iclass 28, count 0 2006.285.06:16:37.37#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:16:37.37#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:16:37.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:16:37.37#ibcon#*before write, iclass 28, count 0 2006.285.06:16:37.37#ibcon#enter sib2, iclass 28, count 0 2006.285.06:16:37.37#ibcon#flushed, iclass 28, count 0 2006.285.06:16:37.37#ibcon#about to write, iclass 28, count 0 2006.285.06:16:37.37#ibcon#wrote, iclass 28, count 0 2006.285.06:16:37.37#ibcon#about to read 3, iclass 28, count 0 2006.285.06:16:37.41#ibcon#read 3, iclass 28, count 0 2006.285.06:16:37.41#ibcon#about to read 4, iclass 28, count 0 2006.285.06:16:37.41#ibcon#read 4, iclass 28, count 0 2006.285.06:16:37.41#ibcon#about to read 5, iclass 28, count 0 2006.285.06:16:37.41#ibcon#read 5, iclass 28, count 0 2006.285.06:16:37.41#ibcon#about to read 6, iclass 28, count 0 2006.285.06:16:37.41#ibcon#read 6, iclass 28, count 0 2006.285.06:16:37.41#ibcon#end of sib2, iclass 28, count 0 2006.285.06:16:37.41#ibcon#*after write, iclass 28, count 0 2006.285.06:16:37.41#ibcon#*before return 0, iclass 28, count 0 2006.285.06:16:37.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:16:37.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:16:37.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:16:37.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:16:37.41$vck44/vb=4,5 2006.285.06:16:37.41#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.06:16:37.41#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.06:16:37.41#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:37.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:16:37.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:16:37.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:16:37.47#ibcon#enter wrdev, iclass 30, count 2 2006.285.06:16:37.47#ibcon#first serial, iclass 30, count 2 2006.285.06:16:37.47#ibcon#enter sib2, iclass 30, count 2 2006.285.06:16:37.47#ibcon#flushed, iclass 30, count 2 2006.285.06:16:37.47#ibcon#about to write, iclass 30, count 2 2006.285.06:16:37.47#ibcon#wrote, iclass 30, count 2 2006.285.06:16:37.47#ibcon#about to read 3, iclass 30, count 2 2006.285.06:16:37.49#ibcon#read 3, iclass 30, count 2 2006.285.06:16:37.49#ibcon#about to read 4, iclass 30, count 2 2006.285.06:16:37.49#ibcon#read 4, iclass 30, count 2 2006.285.06:16:37.49#ibcon#about to read 5, iclass 30, count 2 2006.285.06:16:37.49#ibcon#read 5, iclass 30, count 2 2006.285.06:16:37.49#ibcon#about to read 6, iclass 30, count 2 2006.285.06:16:37.49#ibcon#read 6, iclass 30, count 2 2006.285.06:16:37.49#ibcon#end of sib2, iclass 30, count 2 2006.285.06:16:37.49#ibcon#*mode == 0, iclass 30, count 2 2006.285.06:16:37.49#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.06:16:37.49#ibcon#[27=AT04-05\r\n] 2006.285.06:16:37.49#ibcon#*before write, iclass 30, count 2 2006.285.06:16:37.49#ibcon#enter sib2, iclass 30, count 2 2006.285.06:16:37.49#ibcon#flushed, iclass 30, count 2 2006.285.06:16:37.49#ibcon#about to write, iclass 30, count 2 2006.285.06:16:37.49#ibcon#wrote, iclass 30, count 2 2006.285.06:16:37.49#ibcon#about to read 3, iclass 30, count 2 2006.285.06:16:37.52#ibcon#read 3, iclass 30, count 2 2006.285.06:16:37.52#ibcon#about to read 4, iclass 30, count 2 2006.285.06:16:37.52#ibcon#read 4, iclass 30, count 2 2006.285.06:16:37.52#ibcon#about to read 5, iclass 30, count 2 2006.285.06:16:37.52#ibcon#read 5, iclass 30, count 2 2006.285.06:16:37.52#ibcon#about to read 6, iclass 30, count 2 2006.285.06:16:37.52#ibcon#read 6, iclass 30, count 2 2006.285.06:16:37.52#ibcon#end of sib2, iclass 30, count 2 2006.285.06:16:37.52#ibcon#*after write, iclass 30, count 2 2006.285.06:16:37.52#ibcon#*before return 0, iclass 30, count 2 2006.285.06:16:37.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:16:37.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:16:37.52#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.06:16:37.52#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:37.52#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:16:37.64#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:16:37.64#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:16:37.64#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:16:37.64#ibcon#first serial, iclass 30, count 0 2006.285.06:16:37.64#ibcon#enter sib2, iclass 30, count 0 2006.285.06:16:37.64#ibcon#flushed, iclass 30, count 0 2006.285.06:16:37.64#ibcon#about to write, iclass 30, count 0 2006.285.06:16:37.64#ibcon#wrote, iclass 30, count 0 2006.285.06:16:37.64#ibcon#about to read 3, iclass 30, count 0 2006.285.06:16:37.66#ibcon#read 3, iclass 30, count 0 2006.285.06:16:37.66#ibcon#about to read 4, iclass 30, count 0 2006.285.06:16:37.66#ibcon#read 4, iclass 30, count 0 2006.285.06:16:37.66#ibcon#about to read 5, iclass 30, count 0 2006.285.06:16:37.66#ibcon#read 5, iclass 30, count 0 2006.285.06:16:37.66#ibcon#about to read 6, iclass 30, count 0 2006.285.06:16:37.66#ibcon#read 6, iclass 30, count 0 2006.285.06:16:37.66#ibcon#end of sib2, iclass 30, count 0 2006.285.06:16:37.66#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:16:37.66#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:16:37.66#ibcon#[27=USB\r\n] 2006.285.06:16:37.66#ibcon#*before write, iclass 30, count 0 2006.285.06:16:37.66#ibcon#enter sib2, iclass 30, count 0 2006.285.06:16:37.66#ibcon#flushed, iclass 30, count 0 2006.285.06:16:37.66#ibcon#about to write, iclass 30, count 0 2006.285.06:16:37.66#ibcon#wrote, iclass 30, count 0 2006.285.06:16:37.66#ibcon#about to read 3, iclass 30, count 0 2006.285.06:16:37.69#ibcon#read 3, iclass 30, count 0 2006.285.06:16:37.69#ibcon#about to read 4, iclass 30, count 0 2006.285.06:16:37.69#ibcon#read 4, iclass 30, count 0 2006.285.06:16:37.69#ibcon#about to read 5, iclass 30, count 0 2006.285.06:16:37.69#ibcon#read 5, iclass 30, count 0 2006.285.06:16:37.69#ibcon#about to read 6, iclass 30, count 0 2006.285.06:16:37.69#ibcon#read 6, iclass 30, count 0 2006.285.06:16:37.69#ibcon#end of sib2, iclass 30, count 0 2006.285.06:16:37.69#ibcon#*after write, iclass 30, count 0 2006.285.06:16:37.69#ibcon#*before return 0, iclass 30, count 0 2006.285.06:16:37.69#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:16:37.69#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:16:37.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:16:37.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:16:37.69$vck44/vblo=5,709.99 2006.285.06:16:37.69#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.06:16:37.69#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.06:16:37.69#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:37.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:16:37.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:16:37.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:16:37.69#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:16:37.69#ibcon#first serial, iclass 32, count 0 2006.285.06:16:37.69#ibcon#enter sib2, iclass 32, count 0 2006.285.06:16:37.69#ibcon#flushed, iclass 32, count 0 2006.285.06:16:37.69#ibcon#about to write, iclass 32, count 0 2006.285.06:16:37.69#ibcon#wrote, iclass 32, count 0 2006.285.06:16:37.69#ibcon#about to read 3, iclass 32, count 0 2006.285.06:16:37.71#ibcon#read 3, iclass 32, count 0 2006.285.06:16:37.71#ibcon#about to read 4, iclass 32, count 0 2006.285.06:16:37.71#ibcon#read 4, iclass 32, count 0 2006.285.06:16:37.71#ibcon#about to read 5, iclass 32, count 0 2006.285.06:16:37.71#ibcon#read 5, iclass 32, count 0 2006.285.06:16:37.71#ibcon#about to read 6, iclass 32, count 0 2006.285.06:16:37.71#ibcon#read 6, iclass 32, count 0 2006.285.06:16:37.71#ibcon#end of sib2, iclass 32, count 0 2006.285.06:16:37.71#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:16:37.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:16:37.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:16:37.71#ibcon#*before write, iclass 32, count 0 2006.285.06:16:37.71#ibcon#enter sib2, iclass 32, count 0 2006.285.06:16:37.71#ibcon#flushed, iclass 32, count 0 2006.285.06:16:37.71#ibcon#about to write, iclass 32, count 0 2006.285.06:16:37.71#ibcon#wrote, iclass 32, count 0 2006.285.06:16:37.71#ibcon#about to read 3, iclass 32, count 0 2006.285.06:16:37.75#ibcon#read 3, iclass 32, count 0 2006.285.06:16:37.75#ibcon#about to read 4, iclass 32, count 0 2006.285.06:16:37.75#ibcon#read 4, iclass 32, count 0 2006.285.06:16:37.75#ibcon#about to read 5, iclass 32, count 0 2006.285.06:16:37.75#ibcon#read 5, iclass 32, count 0 2006.285.06:16:37.75#ibcon#about to read 6, iclass 32, count 0 2006.285.06:16:37.75#ibcon#read 6, iclass 32, count 0 2006.285.06:16:37.75#ibcon#end of sib2, iclass 32, count 0 2006.285.06:16:37.75#ibcon#*after write, iclass 32, count 0 2006.285.06:16:37.75#ibcon#*before return 0, iclass 32, count 0 2006.285.06:16:37.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:16:37.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:16:37.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:16:37.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:16:37.75$vck44/vb=5,4 2006.285.06:16:37.75#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.06:16:37.75#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.06:16:37.75#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:37.75#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:16:37.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:16:37.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:16:37.81#ibcon#enter wrdev, iclass 34, count 2 2006.285.06:16:37.81#ibcon#first serial, iclass 34, count 2 2006.285.06:16:37.81#ibcon#enter sib2, iclass 34, count 2 2006.285.06:16:37.81#ibcon#flushed, iclass 34, count 2 2006.285.06:16:37.81#ibcon#about to write, iclass 34, count 2 2006.285.06:16:37.81#ibcon#wrote, iclass 34, count 2 2006.285.06:16:37.81#ibcon#about to read 3, iclass 34, count 2 2006.285.06:16:37.83#ibcon#read 3, iclass 34, count 2 2006.285.06:16:37.83#ibcon#about to read 4, iclass 34, count 2 2006.285.06:16:37.83#ibcon#read 4, iclass 34, count 2 2006.285.06:16:37.83#ibcon#about to read 5, iclass 34, count 2 2006.285.06:16:37.83#ibcon#read 5, iclass 34, count 2 2006.285.06:16:37.83#ibcon#about to read 6, iclass 34, count 2 2006.285.06:16:37.83#ibcon#read 6, iclass 34, count 2 2006.285.06:16:37.83#ibcon#end of sib2, iclass 34, count 2 2006.285.06:16:37.83#ibcon#*mode == 0, iclass 34, count 2 2006.285.06:16:37.83#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.06:16:37.83#ibcon#[27=AT05-04\r\n] 2006.285.06:16:37.83#ibcon#*before write, iclass 34, count 2 2006.285.06:16:37.83#ibcon#enter sib2, iclass 34, count 2 2006.285.06:16:37.83#ibcon#flushed, iclass 34, count 2 2006.285.06:16:37.83#ibcon#about to write, iclass 34, count 2 2006.285.06:16:37.83#ibcon#wrote, iclass 34, count 2 2006.285.06:16:37.83#ibcon#about to read 3, iclass 34, count 2 2006.285.06:16:37.86#ibcon#read 3, iclass 34, count 2 2006.285.06:16:37.86#ibcon#about to read 4, iclass 34, count 2 2006.285.06:16:37.86#ibcon#read 4, iclass 34, count 2 2006.285.06:16:37.86#ibcon#about to read 5, iclass 34, count 2 2006.285.06:16:37.86#ibcon#read 5, iclass 34, count 2 2006.285.06:16:37.86#ibcon#about to read 6, iclass 34, count 2 2006.285.06:16:37.86#ibcon#read 6, iclass 34, count 2 2006.285.06:16:37.86#ibcon#end of sib2, iclass 34, count 2 2006.285.06:16:37.86#ibcon#*after write, iclass 34, count 2 2006.285.06:16:37.86#ibcon#*before return 0, iclass 34, count 2 2006.285.06:16:37.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:16:37.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:16:37.86#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.06:16:37.86#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:37.86#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:16:37.98#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:16:37.98#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:16:37.98#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:16:37.98#ibcon#first serial, iclass 34, count 0 2006.285.06:16:37.98#ibcon#enter sib2, iclass 34, count 0 2006.285.06:16:37.98#ibcon#flushed, iclass 34, count 0 2006.285.06:16:37.98#ibcon#about to write, iclass 34, count 0 2006.285.06:16:37.98#ibcon#wrote, iclass 34, count 0 2006.285.06:16:37.98#ibcon#about to read 3, iclass 34, count 0 2006.285.06:16:38.00#ibcon#read 3, iclass 34, count 0 2006.285.06:16:38.00#ibcon#about to read 4, iclass 34, count 0 2006.285.06:16:38.00#ibcon#read 4, iclass 34, count 0 2006.285.06:16:38.00#ibcon#about to read 5, iclass 34, count 0 2006.285.06:16:38.00#ibcon#read 5, iclass 34, count 0 2006.285.06:16:38.00#ibcon#about to read 6, iclass 34, count 0 2006.285.06:16:38.00#ibcon#read 6, iclass 34, count 0 2006.285.06:16:38.00#ibcon#end of sib2, iclass 34, count 0 2006.285.06:16:38.00#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:16:38.00#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:16:38.00#ibcon#[27=USB\r\n] 2006.285.06:16:38.00#ibcon#*before write, iclass 34, count 0 2006.285.06:16:38.00#ibcon#enter sib2, iclass 34, count 0 2006.285.06:16:38.00#ibcon#flushed, iclass 34, count 0 2006.285.06:16:38.00#ibcon#about to write, iclass 34, count 0 2006.285.06:16:38.00#ibcon#wrote, iclass 34, count 0 2006.285.06:16:38.00#ibcon#about to read 3, iclass 34, count 0 2006.285.06:16:38.03#ibcon#read 3, iclass 34, count 0 2006.285.06:16:38.03#ibcon#about to read 4, iclass 34, count 0 2006.285.06:16:38.03#ibcon#read 4, iclass 34, count 0 2006.285.06:16:38.03#ibcon#about to read 5, iclass 34, count 0 2006.285.06:16:38.03#ibcon#read 5, iclass 34, count 0 2006.285.06:16:38.03#ibcon#about to read 6, iclass 34, count 0 2006.285.06:16:38.03#ibcon#read 6, iclass 34, count 0 2006.285.06:16:38.03#ibcon#end of sib2, iclass 34, count 0 2006.285.06:16:38.03#ibcon#*after write, iclass 34, count 0 2006.285.06:16:38.03#ibcon#*before return 0, iclass 34, count 0 2006.285.06:16:38.03#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:16:38.03#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:16:38.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:16:38.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:16:38.03$vck44/vblo=6,719.99 2006.285.06:16:38.03#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.06:16:38.03#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.06:16:38.03#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:38.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:16:38.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:16:38.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:16:38.03#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:16:38.03#ibcon#first serial, iclass 36, count 0 2006.285.06:16:38.03#ibcon#enter sib2, iclass 36, count 0 2006.285.06:16:38.03#ibcon#flushed, iclass 36, count 0 2006.285.06:16:38.03#ibcon#about to write, iclass 36, count 0 2006.285.06:16:38.03#ibcon#wrote, iclass 36, count 0 2006.285.06:16:38.03#ibcon#about to read 3, iclass 36, count 0 2006.285.06:16:38.05#ibcon#read 3, iclass 36, count 0 2006.285.06:16:38.05#ibcon#about to read 4, iclass 36, count 0 2006.285.06:16:38.05#ibcon#read 4, iclass 36, count 0 2006.285.06:16:38.05#ibcon#about to read 5, iclass 36, count 0 2006.285.06:16:38.05#ibcon#read 5, iclass 36, count 0 2006.285.06:16:38.05#ibcon#about to read 6, iclass 36, count 0 2006.285.06:16:38.05#ibcon#read 6, iclass 36, count 0 2006.285.06:16:38.05#ibcon#end of sib2, iclass 36, count 0 2006.285.06:16:38.05#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:16:38.05#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:16:38.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:16:38.05#ibcon#*before write, iclass 36, count 0 2006.285.06:16:38.05#ibcon#enter sib2, iclass 36, count 0 2006.285.06:16:38.05#ibcon#flushed, iclass 36, count 0 2006.285.06:16:38.05#ibcon#about to write, iclass 36, count 0 2006.285.06:16:38.05#ibcon#wrote, iclass 36, count 0 2006.285.06:16:38.05#ibcon#about to read 3, iclass 36, count 0 2006.285.06:16:38.09#ibcon#read 3, iclass 36, count 0 2006.285.06:16:38.09#ibcon#about to read 4, iclass 36, count 0 2006.285.06:16:38.09#ibcon#read 4, iclass 36, count 0 2006.285.06:16:38.09#ibcon#about to read 5, iclass 36, count 0 2006.285.06:16:38.09#ibcon#read 5, iclass 36, count 0 2006.285.06:16:38.09#ibcon#about to read 6, iclass 36, count 0 2006.285.06:16:38.09#ibcon#read 6, iclass 36, count 0 2006.285.06:16:38.09#ibcon#end of sib2, iclass 36, count 0 2006.285.06:16:38.09#ibcon#*after write, iclass 36, count 0 2006.285.06:16:38.09#ibcon#*before return 0, iclass 36, count 0 2006.285.06:16:38.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:16:38.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:16:38.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:16:38.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:16:38.09$vck44/vb=6,3 2006.285.06:16:38.09#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.06:16:38.09#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.06:16:38.09#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:38.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:16:38.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:16:38.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:16:38.15#ibcon#enter wrdev, iclass 38, count 2 2006.285.06:16:38.15#ibcon#first serial, iclass 38, count 2 2006.285.06:16:38.15#ibcon#enter sib2, iclass 38, count 2 2006.285.06:16:38.15#ibcon#flushed, iclass 38, count 2 2006.285.06:16:38.15#ibcon#about to write, iclass 38, count 2 2006.285.06:16:38.15#ibcon#wrote, iclass 38, count 2 2006.285.06:16:38.15#ibcon#about to read 3, iclass 38, count 2 2006.285.06:16:38.17#ibcon#read 3, iclass 38, count 2 2006.285.06:16:38.17#ibcon#about to read 4, iclass 38, count 2 2006.285.06:16:38.17#ibcon#read 4, iclass 38, count 2 2006.285.06:16:38.17#ibcon#about to read 5, iclass 38, count 2 2006.285.06:16:38.17#ibcon#read 5, iclass 38, count 2 2006.285.06:16:38.17#ibcon#about to read 6, iclass 38, count 2 2006.285.06:16:38.17#ibcon#read 6, iclass 38, count 2 2006.285.06:16:38.17#ibcon#end of sib2, iclass 38, count 2 2006.285.06:16:38.17#ibcon#*mode == 0, iclass 38, count 2 2006.285.06:16:38.17#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.06:16:38.17#ibcon#[27=AT06-03\r\n] 2006.285.06:16:38.17#ibcon#*before write, iclass 38, count 2 2006.285.06:16:38.17#ibcon#enter sib2, iclass 38, count 2 2006.285.06:16:38.17#ibcon#flushed, iclass 38, count 2 2006.285.06:16:38.17#ibcon#about to write, iclass 38, count 2 2006.285.06:16:38.17#ibcon#wrote, iclass 38, count 2 2006.285.06:16:38.17#ibcon#about to read 3, iclass 38, count 2 2006.285.06:16:38.20#ibcon#read 3, iclass 38, count 2 2006.285.06:16:38.20#ibcon#about to read 4, iclass 38, count 2 2006.285.06:16:38.20#ibcon#read 4, iclass 38, count 2 2006.285.06:16:38.20#ibcon#about to read 5, iclass 38, count 2 2006.285.06:16:38.20#ibcon#read 5, iclass 38, count 2 2006.285.06:16:38.20#ibcon#about to read 6, iclass 38, count 2 2006.285.06:16:38.20#ibcon#read 6, iclass 38, count 2 2006.285.06:16:38.20#ibcon#end of sib2, iclass 38, count 2 2006.285.06:16:38.20#ibcon#*after write, iclass 38, count 2 2006.285.06:16:38.20#ibcon#*before return 0, iclass 38, count 2 2006.285.06:16:38.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:16:38.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:16:38.20#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.06:16:38.20#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:38.20#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:16:38.32#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:16:38.32#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:16:38.32#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:16:38.32#ibcon#first serial, iclass 38, count 0 2006.285.06:16:38.32#ibcon#enter sib2, iclass 38, count 0 2006.285.06:16:38.32#ibcon#flushed, iclass 38, count 0 2006.285.06:16:38.32#ibcon#about to write, iclass 38, count 0 2006.285.06:16:38.32#ibcon#wrote, iclass 38, count 0 2006.285.06:16:38.32#ibcon#about to read 3, iclass 38, count 0 2006.285.06:16:38.34#ibcon#read 3, iclass 38, count 0 2006.285.06:16:38.34#ibcon#about to read 4, iclass 38, count 0 2006.285.06:16:38.34#ibcon#read 4, iclass 38, count 0 2006.285.06:16:38.34#ibcon#about to read 5, iclass 38, count 0 2006.285.06:16:38.34#ibcon#read 5, iclass 38, count 0 2006.285.06:16:38.34#ibcon#about to read 6, iclass 38, count 0 2006.285.06:16:38.34#ibcon#read 6, iclass 38, count 0 2006.285.06:16:38.34#ibcon#end of sib2, iclass 38, count 0 2006.285.06:16:38.34#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:16:38.34#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:16:38.34#ibcon#[27=USB\r\n] 2006.285.06:16:38.34#ibcon#*before write, iclass 38, count 0 2006.285.06:16:38.34#ibcon#enter sib2, iclass 38, count 0 2006.285.06:16:38.34#ibcon#flushed, iclass 38, count 0 2006.285.06:16:38.34#ibcon#about to write, iclass 38, count 0 2006.285.06:16:38.34#ibcon#wrote, iclass 38, count 0 2006.285.06:16:38.34#ibcon#about to read 3, iclass 38, count 0 2006.285.06:16:38.37#ibcon#read 3, iclass 38, count 0 2006.285.06:16:38.37#ibcon#about to read 4, iclass 38, count 0 2006.285.06:16:38.37#ibcon#read 4, iclass 38, count 0 2006.285.06:16:38.37#ibcon#about to read 5, iclass 38, count 0 2006.285.06:16:38.37#ibcon#read 5, iclass 38, count 0 2006.285.06:16:38.37#ibcon#about to read 6, iclass 38, count 0 2006.285.06:16:38.37#ibcon#read 6, iclass 38, count 0 2006.285.06:16:38.37#ibcon#end of sib2, iclass 38, count 0 2006.285.06:16:38.37#ibcon#*after write, iclass 38, count 0 2006.285.06:16:38.37#ibcon#*before return 0, iclass 38, count 0 2006.285.06:16:38.37#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:16:38.37#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:16:38.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:16:38.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:16:38.37$vck44/vblo=7,734.99 2006.285.06:16:38.37#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.06:16:38.37#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.06:16:38.37#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:38.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:16:38.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:16:38.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:16:38.37#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:16:38.37#ibcon#first serial, iclass 40, count 0 2006.285.06:16:38.37#ibcon#enter sib2, iclass 40, count 0 2006.285.06:16:38.37#ibcon#flushed, iclass 40, count 0 2006.285.06:16:38.37#ibcon#about to write, iclass 40, count 0 2006.285.06:16:38.37#ibcon#wrote, iclass 40, count 0 2006.285.06:16:38.37#ibcon#about to read 3, iclass 40, count 0 2006.285.06:16:38.39#ibcon#read 3, iclass 40, count 0 2006.285.06:16:38.39#ibcon#about to read 4, iclass 40, count 0 2006.285.06:16:38.39#ibcon#read 4, iclass 40, count 0 2006.285.06:16:38.39#ibcon#about to read 5, iclass 40, count 0 2006.285.06:16:38.39#ibcon#read 5, iclass 40, count 0 2006.285.06:16:38.39#ibcon#about to read 6, iclass 40, count 0 2006.285.06:16:38.39#ibcon#read 6, iclass 40, count 0 2006.285.06:16:38.39#ibcon#end of sib2, iclass 40, count 0 2006.285.06:16:38.39#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:16:38.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:16:38.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:16:38.39#ibcon#*before write, iclass 40, count 0 2006.285.06:16:38.39#ibcon#enter sib2, iclass 40, count 0 2006.285.06:16:38.39#ibcon#flushed, iclass 40, count 0 2006.285.06:16:38.39#ibcon#about to write, iclass 40, count 0 2006.285.06:16:38.39#ibcon#wrote, iclass 40, count 0 2006.285.06:16:38.39#ibcon#about to read 3, iclass 40, count 0 2006.285.06:16:38.43#ibcon#read 3, iclass 40, count 0 2006.285.06:16:38.43#ibcon#about to read 4, iclass 40, count 0 2006.285.06:16:38.43#ibcon#read 4, iclass 40, count 0 2006.285.06:16:38.43#ibcon#about to read 5, iclass 40, count 0 2006.285.06:16:38.43#ibcon#read 5, iclass 40, count 0 2006.285.06:16:38.43#ibcon#about to read 6, iclass 40, count 0 2006.285.06:16:38.43#ibcon#read 6, iclass 40, count 0 2006.285.06:16:38.43#ibcon#end of sib2, iclass 40, count 0 2006.285.06:16:38.43#ibcon#*after write, iclass 40, count 0 2006.285.06:16:38.43#ibcon#*before return 0, iclass 40, count 0 2006.285.06:16:38.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:16:38.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:16:38.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:16:38.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:16:38.43$vck44/vb=7,4 2006.285.06:16:38.43#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.06:16:38.43#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.06:16:38.43#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:38.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:16:38.49#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:16:38.49#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:16:38.49#ibcon#enter wrdev, iclass 4, count 2 2006.285.06:16:38.49#ibcon#first serial, iclass 4, count 2 2006.285.06:16:38.49#ibcon#enter sib2, iclass 4, count 2 2006.285.06:16:38.49#ibcon#flushed, iclass 4, count 2 2006.285.06:16:38.49#ibcon#about to write, iclass 4, count 2 2006.285.06:16:38.49#ibcon#wrote, iclass 4, count 2 2006.285.06:16:38.49#ibcon#about to read 3, iclass 4, count 2 2006.285.06:16:38.51#ibcon#read 3, iclass 4, count 2 2006.285.06:16:38.51#ibcon#about to read 4, iclass 4, count 2 2006.285.06:16:38.51#ibcon#read 4, iclass 4, count 2 2006.285.06:16:38.51#ibcon#about to read 5, iclass 4, count 2 2006.285.06:16:38.51#ibcon#read 5, iclass 4, count 2 2006.285.06:16:38.51#ibcon#about to read 6, iclass 4, count 2 2006.285.06:16:38.51#ibcon#read 6, iclass 4, count 2 2006.285.06:16:38.51#ibcon#end of sib2, iclass 4, count 2 2006.285.06:16:38.51#ibcon#*mode == 0, iclass 4, count 2 2006.285.06:16:38.51#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.06:16:38.51#ibcon#[27=AT07-04\r\n] 2006.285.06:16:38.51#ibcon#*before write, iclass 4, count 2 2006.285.06:16:38.51#ibcon#enter sib2, iclass 4, count 2 2006.285.06:16:38.51#ibcon#flushed, iclass 4, count 2 2006.285.06:16:38.51#ibcon#about to write, iclass 4, count 2 2006.285.06:16:38.51#ibcon#wrote, iclass 4, count 2 2006.285.06:16:38.51#ibcon#about to read 3, iclass 4, count 2 2006.285.06:16:38.54#ibcon#read 3, iclass 4, count 2 2006.285.06:16:38.54#ibcon#about to read 4, iclass 4, count 2 2006.285.06:16:38.54#ibcon#read 4, iclass 4, count 2 2006.285.06:16:38.54#ibcon#about to read 5, iclass 4, count 2 2006.285.06:16:38.54#ibcon#read 5, iclass 4, count 2 2006.285.06:16:38.54#ibcon#about to read 6, iclass 4, count 2 2006.285.06:16:38.54#ibcon#read 6, iclass 4, count 2 2006.285.06:16:38.54#ibcon#end of sib2, iclass 4, count 2 2006.285.06:16:38.54#ibcon#*after write, iclass 4, count 2 2006.285.06:16:38.54#ibcon#*before return 0, iclass 4, count 2 2006.285.06:16:38.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:16:38.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:16:38.54#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.06:16:38.54#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:38.54#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:16:38.66#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:16:38.66#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:16:38.66#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:16:38.66#ibcon#first serial, iclass 4, count 0 2006.285.06:16:38.66#ibcon#enter sib2, iclass 4, count 0 2006.285.06:16:38.66#ibcon#flushed, iclass 4, count 0 2006.285.06:16:38.66#ibcon#about to write, iclass 4, count 0 2006.285.06:16:38.66#ibcon#wrote, iclass 4, count 0 2006.285.06:16:38.66#ibcon#about to read 3, iclass 4, count 0 2006.285.06:16:38.68#ibcon#read 3, iclass 4, count 0 2006.285.06:16:38.68#ibcon#about to read 4, iclass 4, count 0 2006.285.06:16:38.68#ibcon#read 4, iclass 4, count 0 2006.285.06:16:38.68#ibcon#about to read 5, iclass 4, count 0 2006.285.06:16:38.68#ibcon#read 5, iclass 4, count 0 2006.285.06:16:38.68#ibcon#about to read 6, iclass 4, count 0 2006.285.06:16:38.68#ibcon#read 6, iclass 4, count 0 2006.285.06:16:38.68#ibcon#end of sib2, iclass 4, count 0 2006.285.06:16:38.68#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:16:38.68#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:16:38.68#ibcon#[27=USB\r\n] 2006.285.06:16:38.68#ibcon#*before write, iclass 4, count 0 2006.285.06:16:38.68#ibcon#enter sib2, iclass 4, count 0 2006.285.06:16:38.68#ibcon#flushed, iclass 4, count 0 2006.285.06:16:38.68#ibcon#about to write, iclass 4, count 0 2006.285.06:16:38.68#ibcon#wrote, iclass 4, count 0 2006.285.06:16:38.68#ibcon#about to read 3, iclass 4, count 0 2006.285.06:16:38.71#ibcon#read 3, iclass 4, count 0 2006.285.06:16:38.71#ibcon#about to read 4, iclass 4, count 0 2006.285.06:16:38.71#ibcon#read 4, iclass 4, count 0 2006.285.06:16:38.71#ibcon#about to read 5, iclass 4, count 0 2006.285.06:16:38.71#ibcon#read 5, iclass 4, count 0 2006.285.06:16:38.71#ibcon#about to read 6, iclass 4, count 0 2006.285.06:16:38.71#ibcon#read 6, iclass 4, count 0 2006.285.06:16:38.71#ibcon#end of sib2, iclass 4, count 0 2006.285.06:16:38.71#ibcon#*after write, iclass 4, count 0 2006.285.06:16:38.71#ibcon#*before return 0, iclass 4, count 0 2006.285.06:16:38.71#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:16:38.71#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:16:38.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:16:38.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:16:38.71$vck44/vblo=8,744.99 2006.285.06:16:38.71#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.06:16:38.71#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.06:16:38.71#ibcon#ireg 17 cls_cnt 0 2006.285.06:16:38.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:16:38.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:16:38.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:16:38.71#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:16:38.71#ibcon#first serial, iclass 6, count 0 2006.285.06:16:38.71#ibcon#enter sib2, iclass 6, count 0 2006.285.06:16:38.71#ibcon#flushed, iclass 6, count 0 2006.285.06:16:38.71#ibcon#about to write, iclass 6, count 0 2006.285.06:16:38.71#ibcon#wrote, iclass 6, count 0 2006.285.06:16:38.71#ibcon#about to read 3, iclass 6, count 0 2006.285.06:16:38.73#ibcon#read 3, iclass 6, count 0 2006.285.06:16:38.73#ibcon#about to read 4, iclass 6, count 0 2006.285.06:16:38.73#ibcon#read 4, iclass 6, count 0 2006.285.06:16:38.73#ibcon#about to read 5, iclass 6, count 0 2006.285.06:16:38.73#ibcon#read 5, iclass 6, count 0 2006.285.06:16:38.73#ibcon#about to read 6, iclass 6, count 0 2006.285.06:16:38.73#ibcon#read 6, iclass 6, count 0 2006.285.06:16:38.73#ibcon#end of sib2, iclass 6, count 0 2006.285.06:16:38.73#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:16:38.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:16:38.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:16:38.73#ibcon#*before write, iclass 6, count 0 2006.285.06:16:38.73#ibcon#enter sib2, iclass 6, count 0 2006.285.06:16:38.73#ibcon#flushed, iclass 6, count 0 2006.285.06:16:38.73#ibcon#about to write, iclass 6, count 0 2006.285.06:16:38.73#ibcon#wrote, iclass 6, count 0 2006.285.06:16:38.73#ibcon#about to read 3, iclass 6, count 0 2006.285.06:16:38.77#ibcon#read 3, iclass 6, count 0 2006.285.06:16:38.77#ibcon#about to read 4, iclass 6, count 0 2006.285.06:16:38.77#ibcon#read 4, iclass 6, count 0 2006.285.06:16:38.77#ibcon#about to read 5, iclass 6, count 0 2006.285.06:16:38.77#ibcon#read 5, iclass 6, count 0 2006.285.06:16:38.77#ibcon#about to read 6, iclass 6, count 0 2006.285.06:16:38.77#ibcon#read 6, iclass 6, count 0 2006.285.06:16:38.77#ibcon#end of sib2, iclass 6, count 0 2006.285.06:16:38.77#ibcon#*after write, iclass 6, count 0 2006.285.06:16:38.77#ibcon#*before return 0, iclass 6, count 0 2006.285.06:16:38.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:16:38.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:16:38.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:16:38.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:16:38.77$vck44/vb=8,4 2006.285.06:16:38.77#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.06:16:38.77#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.06:16:38.77#ibcon#ireg 11 cls_cnt 2 2006.285.06:16:38.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:16:38.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:16:38.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:16:38.83#ibcon#enter wrdev, iclass 10, count 2 2006.285.06:16:38.83#ibcon#first serial, iclass 10, count 2 2006.285.06:16:38.83#ibcon#enter sib2, iclass 10, count 2 2006.285.06:16:38.83#ibcon#flushed, iclass 10, count 2 2006.285.06:16:38.83#ibcon#about to write, iclass 10, count 2 2006.285.06:16:38.83#ibcon#wrote, iclass 10, count 2 2006.285.06:16:38.83#ibcon#about to read 3, iclass 10, count 2 2006.285.06:16:38.85#ibcon#read 3, iclass 10, count 2 2006.285.06:16:38.85#ibcon#about to read 4, iclass 10, count 2 2006.285.06:16:38.85#ibcon#read 4, iclass 10, count 2 2006.285.06:16:38.85#ibcon#about to read 5, iclass 10, count 2 2006.285.06:16:38.85#ibcon#read 5, iclass 10, count 2 2006.285.06:16:38.85#ibcon#about to read 6, iclass 10, count 2 2006.285.06:16:38.85#ibcon#read 6, iclass 10, count 2 2006.285.06:16:38.85#ibcon#end of sib2, iclass 10, count 2 2006.285.06:16:38.85#ibcon#*mode == 0, iclass 10, count 2 2006.285.06:16:38.85#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.06:16:38.85#ibcon#[27=AT08-04\r\n] 2006.285.06:16:38.85#ibcon#*before write, iclass 10, count 2 2006.285.06:16:38.85#ibcon#enter sib2, iclass 10, count 2 2006.285.06:16:38.85#ibcon#flushed, iclass 10, count 2 2006.285.06:16:38.85#ibcon#about to write, iclass 10, count 2 2006.285.06:16:38.85#ibcon#wrote, iclass 10, count 2 2006.285.06:16:38.85#ibcon#about to read 3, iclass 10, count 2 2006.285.06:16:38.88#ibcon#read 3, iclass 10, count 2 2006.285.06:16:38.88#ibcon#about to read 4, iclass 10, count 2 2006.285.06:16:38.88#ibcon#read 4, iclass 10, count 2 2006.285.06:16:38.88#ibcon#about to read 5, iclass 10, count 2 2006.285.06:16:38.88#ibcon#read 5, iclass 10, count 2 2006.285.06:16:38.88#ibcon#about to read 6, iclass 10, count 2 2006.285.06:16:38.88#ibcon#read 6, iclass 10, count 2 2006.285.06:16:38.88#ibcon#end of sib2, iclass 10, count 2 2006.285.06:16:38.88#ibcon#*after write, iclass 10, count 2 2006.285.06:16:38.88#ibcon#*before return 0, iclass 10, count 2 2006.285.06:16:38.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:16:38.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:16:38.88#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.06:16:38.88#ibcon#ireg 7 cls_cnt 0 2006.285.06:16:38.88#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:16:39.00#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:16:39.00#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:16:39.00#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:16:39.00#ibcon#first serial, iclass 10, count 0 2006.285.06:16:39.00#ibcon#enter sib2, iclass 10, count 0 2006.285.06:16:39.00#ibcon#flushed, iclass 10, count 0 2006.285.06:16:39.00#ibcon#about to write, iclass 10, count 0 2006.285.06:16:39.00#ibcon#wrote, iclass 10, count 0 2006.285.06:16:39.00#ibcon#about to read 3, iclass 10, count 0 2006.285.06:16:39.02#ibcon#read 3, iclass 10, count 0 2006.285.06:16:39.02#ibcon#about to read 4, iclass 10, count 0 2006.285.06:16:39.02#ibcon#read 4, iclass 10, count 0 2006.285.06:16:39.02#ibcon#about to read 5, iclass 10, count 0 2006.285.06:16:39.02#ibcon#read 5, iclass 10, count 0 2006.285.06:16:39.02#ibcon#about to read 6, iclass 10, count 0 2006.285.06:16:39.02#ibcon#read 6, iclass 10, count 0 2006.285.06:16:39.02#ibcon#end of sib2, iclass 10, count 0 2006.285.06:16:39.02#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:16:39.02#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:16:39.02#ibcon#[27=USB\r\n] 2006.285.06:16:39.02#ibcon#*before write, iclass 10, count 0 2006.285.06:16:39.02#ibcon#enter sib2, iclass 10, count 0 2006.285.06:16:39.02#ibcon#flushed, iclass 10, count 0 2006.285.06:16:39.02#ibcon#about to write, iclass 10, count 0 2006.285.06:16:39.02#ibcon#wrote, iclass 10, count 0 2006.285.06:16:39.02#ibcon#about to read 3, iclass 10, count 0 2006.285.06:16:39.05#ibcon#read 3, iclass 10, count 0 2006.285.06:16:39.05#ibcon#about to read 4, iclass 10, count 0 2006.285.06:16:39.05#ibcon#read 4, iclass 10, count 0 2006.285.06:16:39.05#ibcon#about to read 5, iclass 10, count 0 2006.285.06:16:39.05#ibcon#read 5, iclass 10, count 0 2006.285.06:16:39.05#ibcon#about to read 6, iclass 10, count 0 2006.285.06:16:39.05#ibcon#read 6, iclass 10, count 0 2006.285.06:16:39.05#ibcon#end of sib2, iclass 10, count 0 2006.285.06:16:39.05#ibcon#*after write, iclass 10, count 0 2006.285.06:16:39.05#ibcon#*before return 0, iclass 10, count 0 2006.285.06:16:39.05#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:16:39.05#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:16:39.05#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:16:39.05#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:16:39.05$vck44/vabw=wide 2006.285.06:16:39.05#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.06:16:39.05#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.06:16:39.05#ibcon#ireg 8 cls_cnt 0 2006.285.06:16:39.05#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:16:39.05#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:16:39.05#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:16:39.05#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:16:39.05#ibcon#first serial, iclass 12, count 0 2006.285.06:16:39.05#ibcon#enter sib2, iclass 12, count 0 2006.285.06:16:39.05#ibcon#flushed, iclass 12, count 0 2006.285.06:16:39.05#ibcon#about to write, iclass 12, count 0 2006.285.06:16:39.05#ibcon#wrote, iclass 12, count 0 2006.285.06:16:39.05#ibcon#about to read 3, iclass 12, count 0 2006.285.06:16:39.07#ibcon#read 3, iclass 12, count 0 2006.285.06:16:39.07#ibcon#about to read 4, iclass 12, count 0 2006.285.06:16:39.07#ibcon#read 4, iclass 12, count 0 2006.285.06:16:39.07#ibcon#about to read 5, iclass 12, count 0 2006.285.06:16:39.07#ibcon#read 5, iclass 12, count 0 2006.285.06:16:39.07#ibcon#about to read 6, iclass 12, count 0 2006.285.06:16:39.07#ibcon#read 6, iclass 12, count 0 2006.285.06:16:39.07#ibcon#end of sib2, iclass 12, count 0 2006.285.06:16:39.07#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:16:39.07#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:16:39.07#ibcon#[25=BW32\r\n] 2006.285.06:16:39.07#ibcon#*before write, iclass 12, count 0 2006.285.06:16:39.07#ibcon#enter sib2, iclass 12, count 0 2006.285.06:16:39.07#ibcon#flushed, iclass 12, count 0 2006.285.06:16:39.07#ibcon#about to write, iclass 12, count 0 2006.285.06:16:39.07#ibcon#wrote, iclass 12, count 0 2006.285.06:16:39.07#ibcon#about to read 3, iclass 12, count 0 2006.285.06:16:39.10#ibcon#read 3, iclass 12, count 0 2006.285.06:16:39.10#ibcon#about to read 4, iclass 12, count 0 2006.285.06:16:39.10#ibcon#read 4, iclass 12, count 0 2006.285.06:16:39.10#ibcon#about to read 5, iclass 12, count 0 2006.285.06:16:39.10#ibcon#read 5, iclass 12, count 0 2006.285.06:16:39.10#ibcon#about to read 6, iclass 12, count 0 2006.285.06:16:39.10#ibcon#read 6, iclass 12, count 0 2006.285.06:16:39.10#ibcon#end of sib2, iclass 12, count 0 2006.285.06:16:39.10#ibcon#*after write, iclass 12, count 0 2006.285.06:16:39.10#ibcon#*before return 0, iclass 12, count 0 2006.285.06:16:39.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:16:39.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:16:39.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:16:39.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:16:39.10$vck44/vbbw=wide 2006.285.06:16:39.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.06:16:39.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.06:16:39.10#ibcon#ireg 8 cls_cnt 0 2006.285.06:16:39.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:16:39.17#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:16:39.17#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:16:39.17#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:16:39.17#ibcon#first serial, iclass 14, count 0 2006.285.06:16:39.17#ibcon#enter sib2, iclass 14, count 0 2006.285.06:16:39.17#ibcon#flushed, iclass 14, count 0 2006.285.06:16:39.17#ibcon#about to write, iclass 14, count 0 2006.285.06:16:39.17#ibcon#wrote, iclass 14, count 0 2006.285.06:16:39.17#ibcon#about to read 3, iclass 14, count 0 2006.285.06:16:39.19#ibcon#read 3, iclass 14, count 0 2006.285.06:16:39.19#ibcon#about to read 4, iclass 14, count 0 2006.285.06:16:39.19#ibcon#read 4, iclass 14, count 0 2006.285.06:16:39.19#ibcon#about to read 5, iclass 14, count 0 2006.285.06:16:39.19#ibcon#read 5, iclass 14, count 0 2006.285.06:16:39.19#ibcon#about to read 6, iclass 14, count 0 2006.285.06:16:39.19#ibcon#read 6, iclass 14, count 0 2006.285.06:16:39.19#ibcon#end of sib2, iclass 14, count 0 2006.285.06:16:39.19#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:16:39.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:16:39.19#ibcon#[27=BW32\r\n] 2006.285.06:16:39.19#ibcon#*before write, iclass 14, count 0 2006.285.06:16:39.19#ibcon#enter sib2, iclass 14, count 0 2006.285.06:16:39.19#ibcon#flushed, iclass 14, count 0 2006.285.06:16:39.19#ibcon#about to write, iclass 14, count 0 2006.285.06:16:39.19#ibcon#wrote, iclass 14, count 0 2006.285.06:16:39.19#ibcon#about to read 3, iclass 14, count 0 2006.285.06:16:39.22#ibcon#read 3, iclass 14, count 0 2006.285.06:16:39.22#ibcon#about to read 4, iclass 14, count 0 2006.285.06:16:39.22#ibcon#read 4, iclass 14, count 0 2006.285.06:16:39.22#ibcon#about to read 5, iclass 14, count 0 2006.285.06:16:39.22#ibcon#read 5, iclass 14, count 0 2006.285.06:16:39.22#ibcon#about to read 6, iclass 14, count 0 2006.285.06:16:39.22#ibcon#read 6, iclass 14, count 0 2006.285.06:16:39.22#ibcon#end of sib2, iclass 14, count 0 2006.285.06:16:39.22#ibcon#*after write, iclass 14, count 0 2006.285.06:16:39.22#ibcon#*before return 0, iclass 14, count 0 2006.285.06:16:39.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:16:39.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:16:39.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:16:39.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:16:39.22$setupk4/ifdk4 2006.285.06:16:39.22$ifdk4/lo= 2006.285.06:16:39.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:16:39.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:16:39.22$ifdk4/patch= 2006.285.06:16:39.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:16:39.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:16:39.22$setupk4/!*+20s 2006.285.06:16:46.53#abcon#<5=/04 4.3 7.1 25.02 671014.0\r\n> 2006.285.06:16:46.55#abcon#{5=INTERFACE CLEAR} 2006.285.06:16:46.61#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:16:53.72$setupk4/"tpicd 2006.285.06:16:53.72$setupk4/echo=off 2006.285.06:16:53.72$setupk4/xlog=off 2006.285.06:16:53.72:!2006.285.06:18:33 2006.285.06:17:04.14#trakl#Source acquired 2006.285.06:17:04.14#flagr#flagr/antenna,acquired 2006.285.06:18:33.00:preob 2006.285.06:18:33.14/onsource/TRACKING 2006.285.06:18:33.14:!2006.285.06:18:43 2006.285.06:18:43.00:"tape 2006.285.06:18:43.00:"st=record 2006.285.06:18:43.00:data_valid=on 2006.285.06:18:43.00:midob 2006.285.06:18:43.14/onsource/TRACKING 2006.285.06:18:43.14/wx/24.99,1014.0,68 2006.285.06:18:43.19/cable/+6.4746E-03 2006.285.06:18:44.28/va/01,07,usb,yes,53,57 2006.285.06:18:44.28/va/02,06,usb,yes,53,54 2006.285.06:18:44.28/va/03,07,usb,yes,53,55 2006.285.06:18:44.28/va/04,06,usb,yes,55,58 2006.285.06:18:44.28/va/05,03,usb,yes,54,55 2006.285.06:18:44.28/va/06,04,usb,yes,49,48 2006.285.06:18:44.28/va/07,04,usb,yes,49,50 2006.285.06:18:44.28/va/08,03,usb,yes,50,60 2006.285.06:18:44.51/valo/01,524.99,yes,locked 2006.285.06:18:44.51/valo/02,534.99,yes,locked 2006.285.06:18:44.51/valo/03,564.99,yes,locked 2006.285.06:18:44.51/valo/04,624.99,yes,locked 2006.285.06:18:44.51/valo/05,734.99,yes,locked 2006.285.06:18:44.51/valo/06,814.99,yes,locked 2006.285.06:18:44.51/valo/07,864.99,yes,locked 2006.285.06:18:44.51/valo/08,884.99,yes,locked 2006.285.06:18:45.60/vb/01,04,usb,yes,47,43 2006.285.06:18:45.60/vb/02,05,usb,yes,44,43 2006.285.06:18:45.60/vb/03,04,usb,yes,46,50 2006.285.06:18:45.60/vb/04,05,usb,yes,46,44 2006.285.06:18:45.60/vb/05,04,usb,yes,41,45 2006.285.06:18:45.60/vb/06,03,usb,yes,58,52 2006.285.06:18:45.60/vb/07,04,usb,yes,47,47 2006.285.06:18:45.60/vb/08,04,usb,yes,42,48 2006.285.06:18:45.83/vblo/01,629.99,yes,locked 2006.285.06:18:45.83/vblo/02,634.99,yes,locked 2006.285.06:18:45.83/vblo/03,649.99,yes,locked 2006.285.06:18:45.83/vblo/04,679.99,yes,locked 2006.285.06:18:45.83/vblo/05,709.99,yes,locked 2006.285.06:18:45.83/vblo/06,719.99,yes,locked 2006.285.06:18:45.83/vblo/07,734.99,yes,locked 2006.285.06:18:45.83/vblo/08,744.99,yes,locked 2006.285.06:18:45.98/vabw/8 2006.285.06:18:46.13/vbbw/8 2006.285.06:18:46.22/xfe/off,on,12.2 2006.285.06:18:46.60/ifatt/23,28,28,28 2006.285.06:18:47.08/fmout-gps/S +2.56E-07 2006.285.06:18:47.11:!2006.285.06:19:23 2006.285.06:19:23.01:data_valid=off 2006.285.06:19:23.01:"et 2006.285.06:19:23.01:!+3s 2006.285.06:19:26.02:"tape 2006.285.06:19:26.02:postob 2006.285.06:19:26.11/cable/+6.4753E-03 2006.285.06:19:26.11/wx/24.98,1014.0,69 2006.285.06:19:27.08/fmout-gps/S +2.55E-07 2006.285.06:19:27.08:scan_name=285-0620,jd0610,210 2006.285.06:19:27.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.285.06:19:28.14#flagr#flagr/antenna,new-source 2006.285.06:19:28.14:checkk5 2006.285.06:19:28.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:19:28.96/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:19:29.35/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:19:29.75/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:19:30.15/chk_obsdata//k5ts1/T2850618??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:19:30.54/chk_obsdata//k5ts2/T2850618??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:19:30.88/chk_obsdata//k5ts3/T2850618??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:19:31.28/chk_obsdata//k5ts4/T2850618??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:19:32.05/k5log//k5ts1_log_newline 2006.285.06:19:32.81/k5log//k5ts2_log_newline 2006.285.06:19:33.58/k5log//k5ts3_log_newline 2006.285.06:19:34.81/k5log//k5ts4_log_newline 2006.285.06:19:34.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:19:34.84:setupk4=1 2006.285.06:19:34.84$setupk4/echo=on 2006.285.06:19:34.84$setupk4/pcalon 2006.285.06:19:34.84$pcalon/"no phase cal control is implemented here 2006.285.06:19:34.84$setupk4/"tpicd=stop 2006.285.06:19:34.84$setupk4/"rec=synch_on 2006.285.06:19:34.84$setupk4/"rec_mode=128 2006.285.06:19:34.84$setupk4/!* 2006.285.06:19:34.84$setupk4/recpk4 2006.285.06:19:34.84$recpk4/recpatch= 2006.285.06:19:34.84$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:19:34.84$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:19:34.84$setupk4/vck44 2006.285.06:19:34.84$vck44/valo=1,524.99 2006.285.06:19:34.84#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.06:19:34.84#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.06:19:34.84#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:34.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:19:34.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:19:34.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:19:34.84#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:19:34.84#ibcon#first serial, iclass 15, count 0 2006.285.06:19:34.84#ibcon#enter sib2, iclass 15, count 0 2006.285.06:19:34.84#ibcon#flushed, iclass 15, count 0 2006.285.06:19:34.84#ibcon#about to write, iclass 15, count 0 2006.285.06:19:34.84#ibcon#wrote, iclass 15, count 0 2006.285.06:19:34.84#ibcon#about to read 3, iclass 15, count 0 2006.285.06:19:34.86#ibcon#read 3, iclass 15, count 0 2006.285.06:19:34.86#ibcon#about to read 4, iclass 15, count 0 2006.285.06:19:34.86#ibcon#read 4, iclass 15, count 0 2006.285.06:19:34.86#ibcon#about to read 5, iclass 15, count 0 2006.285.06:19:34.86#ibcon#read 5, iclass 15, count 0 2006.285.06:19:34.86#ibcon#about to read 6, iclass 15, count 0 2006.285.06:19:34.86#ibcon#read 6, iclass 15, count 0 2006.285.06:19:34.86#ibcon#end of sib2, iclass 15, count 0 2006.285.06:19:34.86#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:19:34.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:19:34.86#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:19:34.86#ibcon#*before write, iclass 15, count 0 2006.285.06:19:34.86#ibcon#enter sib2, iclass 15, count 0 2006.285.06:19:34.86#ibcon#flushed, iclass 15, count 0 2006.285.06:19:34.86#ibcon#about to write, iclass 15, count 0 2006.285.06:19:34.86#ibcon#wrote, iclass 15, count 0 2006.285.06:19:34.86#ibcon#about to read 3, iclass 15, count 0 2006.285.06:19:34.91#ibcon#read 3, iclass 15, count 0 2006.285.06:19:34.91#ibcon#about to read 4, iclass 15, count 0 2006.285.06:19:34.91#ibcon#read 4, iclass 15, count 0 2006.285.06:19:34.91#ibcon#about to read 5, iclass 15, count 0 2006.285.06:19:34.91#ibcon#read 5, iclass 15, count 0 2006.285.06:19:34.91#ibcon#about to read 6, iclass 15, count 0 2006.285.06:19:34.91#ibcon#read 6, iclass 15, count 0 2006.285.06:19:34.91#ibcon#end of sib2, iclass 15, count 0 2006.285.06:19:34.91#ibcon#*after write, iclass 15, count 0 2006.285.06:19:34.91#ibcon#*before return 0, iclass 15, count 0 2006.285.06:19:34.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:19:34.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:19:34.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:19:34.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:19:34.91$vck44/va=1,7 2006.285.06:19:34.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.06:19:34.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.06:19:34.91#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:34.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:19:34.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:19:34.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:19:34.91#ibcon#enter wrdev, iclass 17, count 2 2006.285.06:19:34.91#ibcon#first serial, iclass 17, count 2 2006.285.06:19:34.91#ibcon#enter sib2, iclass 17, count 2 2006.285.06:19:34.91#ibcon#flushed, iclass 17, count 2 2006.285.06:19:34.91#ibcon#about to write, iclass 17, count 2 2006.285.06:19:34.91#ibcon#wrote, iclass 17, count 2 2006.285.06:19:34.91#ibcon#about to read 3, iclass 17, count 2 2006.285.06:19:34.93#ibcon#read 3, iclass 17, count 2 2006.285.06:19:34.93#ibcon#about to read 4, iclass 17, count 2 2006.285.06:19:34.93#ibcon#read 4, iclass 17, count 2 2006.285.06:19:34.93#ibcon#about to read 5, iclass 17, count 2 2006.285.06:19:34.93#ibcon#read 5, iclass 17, count 2 2006.285.06:19:34.93#ibcon#about to read 6, iclass 17, count 2 2006.285.06:19:34.93#ibcon#read 6, iclass 17, count 2 2006.285.06:19:34.93#ibcon#end of sib2, iclass 17, count 2 2006.285.06:19:34.93#ibcon#*mode == 0, iclass 17, count 2 2006.285.06:19:34.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.06:19:34.93#ibcon#[25=AT01-07\r\n] 2006.285.06:19:34.93#ibcon#*before write, iclass 17, count 2 2006.285.06:19:34.93#ibcon#enter sib2, iclass 17, count 2 2006.285.06:19:34.93#ibcon#flushed, iclass 17, count 2 2006.285.06:19:34.93#ibcon#about to write, iclass 17, count 2 2006.285.06:19:34.93#ibcon#wrote, iclass 17, count 2 2006.285.06:19:34.93#ibcon#about to read 3, iclass 17, count 2 2006.285.06:19:34.96#ibcon#read 3, iclass 17, count 2 2006.285.06:19:34.96#ibcon#about to read 4, iclass 17, count 2 2006.285.06:19:34.96#ibcon#read 4, iclass 17, count 2 2006.285.06:19:34.96#ibcon#about to read 5, iclass 17, count 2 2006.285.06:19:34.96#ibcon#read 5, iclass 17, count 2 2006.285.06:19:34.96#ibcon#about to read 6, iclass 17, count 2 2006.285.06:19:34.96#ibcon#read 6, iclass 17, count 2 2006.285.06:19:34.96#ibcon#end of sib2, iclass 17, count 2 2006.285.06:19:34.96#ibcon#*after write, iclass 17, count 2 2006.285.06:19:34.96#ibcon#*before return 0, iclass 17, count 2 2006.285.06:19:34.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:19:34.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:19:34.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.06:19:34.96#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:34.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:19:35.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:19:35.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:19:35.08#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:19:35.08#ibcon#first serial, iclass 17, count 0 2006.285.06:19:35.08#ibcon#enter sib2, iclass 17, count 0 2006.285.06:19:35.08#ibcon#flushed, iclass 17, count 0 2006.285.06:19:35.08#ibcon#about to write, iclass 17, count 0 2006.285.06:19:35.08#ibcon#wrote, iclass 17, count 0 2006.285.06:19:35.08#ibcon#about to read 3, iclass 17, count 0 2006.285.06:19:35.10#ibcon#read 3, iclass 17, count 0 2006.285.06:19:35.10#ibcon#about to read 4, iclass 17, count 0 2006.285.06:19:35.10#ibcon#read 4, iclass 17, count 0 2006.285.06:19:35.10#ibcon#about to read 5, iclass 17, count 0 2006.285.06:19:35.10#ibcon#read 5, iclass 17, count 0 2006.285.06:19:35.10#ibcon#about to read 6, iclass 17, count 0 2006.285.06:19:35.10#ibcon#read 6, iclass 17, count 0 2006.285.06:19:35.10#ibcon#end of sib2, iclass 17, count 0 2006.285.06:19:35.10#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:19:35.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:19:35.10#ibcon#[25=USB\r\n] 2006.285.06:19:35.10#ibcon#*before write, iclass 17, count 0 2006.285.06:19:35.10#ibcon#enter sib2, iclass 17, count 0 2006.285.06:19:35.10#ibcon#flushed, iclass 17, count 0 2006.285.06:19:35.10#ibcon#about to write, iclass 17, count 0 2006.285.06:19:35.10#ibcon#wrote, iclass 17, count 0 2006.285.06:19:35.10#ibcon#about to read 3, iclass 17, count 0 2006.285.06:19:35.13#ibcon#read 3, iclass 17, count 0 2006.285.06:19:35.13#ibcon#about to read 4, iclass 17, count 0 2006.285.06:19:35.13#ibcon#read 4, iclass 17, count 0 2006.285.06:19:35.13#ibcon#about to read 5, iclass 17, count 0 2006.285.06:19:35.13#ibcon#read 5, iclass 17, count 0 2006.285.06:19:35.13#ibcon#about to read 6, iclass 17, count 0 2006.285.06:19:35.13#ibcon#read 6, iclass 17, count 0 2006.285.06:19:35.13#ibcon#end of sib2, iclass 17, count 0 2006.285.06:19:35.13#ibcon#*after write, iclass 17, count 0 2006.285.06:19:35.13#ibcon#*before return 0, iclass 17, count 0 2006.285.06:19:35.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:19:35.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:19:35.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:19:35.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:19:35.13$vck44/valo=2,534.99 2006.285.06:19:35.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.06:19:35.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.06:19:35.13#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:35.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:19:35.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:19:35.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:19:35.13#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:19:35.13#ibcon#first serial, iclass 19, count 0 2006.285.06:19:35.13#ibcon#enter sib2, iclass 19, count 0 2006.285.06:19:35.13#ibcon#flushed, iclass 19, count 0 2006.285.06:19:35.13#ibcon#about to write, iclass 19, count 0 2006.285.06:19:35.13#ibcon#wrote, iclass 19, count 0 2006.285.06:19:35.13#ibcon#about to read 3, iclass 19, count 0 2006.285.06:19:35.15#ibcon#read 3, iclass 19, count 0 2006.285.06:19:35.15#ibcon#about to read 4, iclass 19, count 0 2006.285.06:19:35.15#ibcon#read 4, iclass 19, count 0 2006.285.06:19:35.15#ibcon#about to read 5, iclass 19, count 0 2006.285.06:19:35.15#ibcon#read 5, iclass 19, count 0 2006.285.06:19:35.15#ibcon#about to read 6, iclass 19, count 0 2006.285.06:19:35.15#ibcon#read 6, iclass 19, count 0 2006.285.06:19:35.15#ibcon#end of sib2, iclass 19, count 0 2006.285.06:19:35.15#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:19:35.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:19:35.15#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:19:35.15#ibcon#*before write, iclass 19, count 0 2006.285.06:19:35.15#ibcon#enter sib2, iclass 19, count 0 2006.285.06:19:35.15#ibcon#flushed, iclass 19, count 0 2006.285.06:19:35.15#ibcon#about to write, iclass 19, count 0 2006.285.06:19:35.15#ibcon#wrote, iclass 19, count 0 2006.285.06:19:35.15#ibcon#about to read 3, iclass 19, count 0 2006.285.06:19:35.19#ibcon#read 3, iclass 19, count 0 2006.285.06:19:35.19#ibcon#about to read 4, iclass 19, count 0 2006.285.06:19:35.19#ibcon#read 4, iclass 19, count 0 2006.285.06:19:35.19#ibcon#about to read 5, iclass 19, count 0 2006.285.06:19:35.19#ibcon#read 5, iclass 19, count 0 2006.285.06:19:35.19#ibcon#about to read 6, iclass 19, count 0 2006.285.06:19:35.19#ibcon#read 6, iclass 19, count 0 2006.285.06:19:35.19#ibcon#end of sib2, iclass 19, count 0 2006.285.06:19:35.19#ibcon#*after write, iclass 19, count 0 2006.285.06:19:35.19#ibcon#*before return 0, iclass 19, count 0 2006.285.06:19:35.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:19:35.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:19:35.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:19:35.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:19:35.19$vck44/va=2,6 2006.285.06:19:35.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.06:19:35.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.06:19:35.19#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:35.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:19:35.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:19:35.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:19:35.25#ibcon#enter wrdev, iclass 21, count 2 2006.285.06:19:35.25#ibcon#first serial, iclass 21, count 2 2006.285.06:19:35.25#ibcon#enter sib2, iclass 21, count 2 2006.285.06:19:35.25#ibcon#flushed, iclass 21, count 2 2006.285.06:19:35.25#ibcon#about to write, iclass 21, count 2 2006.285.06:19:35.25#ibcon#wrote, iclass 21, count 2 2006.285.06:19:35.25#ibcon#about to read 3, iclass 21, count 2 2006.285.06:19:35.27#ibcon#read 3, iclass 21, count 2 2006.285.06:19:35.27#ibcon#about to read 4, iclass 21, count 2 2006.285.06:19:35.27#ibcon#read 4, iclass 21, count 2 2006.285.06:19:35.27#ibcon#about to read 5, iclass 21, count 2 2006.285.06:19:35.27#ibcon#read 5, iclass 21, count 2 2006.285.06:19:35.27#ibcon#about to read 6, iclass 21, count 2 2006.285.06:19:35.27#ibcon#read 6, iclass 21, count 2 2006.285.06:19:35.27#ibcon#end of sib2, iclass 21, count 2 2006.285.06:19:35.27#ibcon#*mode == 0, iclass 21, count 2 2006.285.06:19:35.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.06:19:35.27#ibcon#[25=AT02-06\r\n] 2006.285.06:19:35.27#ibcon#*before write, iclass 21, count 2 2006.285.06:19:35.27#ibcon#enter sib2, iclass 21, count 2 2006.285.06:19:35.27#ibcon#flushed, iclass 21, count 2 2006.285.06:19:35.27#ibcon#about to write, iclass 21, count 2 2006.285.06:19:35.27#ibcon#wrote, iclass 21, count 2 2006.285.06:19:35.27#ibcon#about to read 3, iclass 21, count 2 2006.285.06:19:35.30#ibcon#read 3, iclass 21, count 2 2006.285.06:19:35.30#ibcon#about to read 4, iclass 21, count 2 2006.285.06:19:35.30#ibcon#read 4, iclass 21, count 2 2006.285.06:19:35.30#ibcon#about to read 5, iclass 21, count 2 2006.285.06:19:35.30#ibcon#read 5, iclass 21, count 2 2006.285.06:19:35.30#ibcon#about to read 6, iclass 21, count 2 2006.285.06:19:35.30#ibcon#read 6, iclass 21, count 2 2006.285.06:19:35.30#ibcon#end of sib2, iclass 21, count 2 2006.285.06:19:35.30#ibcon#*after write, iclass 21, count 2 2006.285.06:19:35.30#ibcon#*before return 0, iclass 21, count 2 2006.285.06:19:35.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:19:35.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:19:35.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.06:19:35.30#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:35.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:19:35.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:19:35.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:19:35.42#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:19:35.42#ibcon#first serial, iclass 21, count 0 2006.285.06:19:35.42#ibcon#enter sib2, iclass 21, count 0 2006.285.06:19:35.42#ibcon#flushed, iclass 21, count 0 2006.285.06:19:35.42#ibcon#about to write, iclass 21, count 0 2006.285.06:19:35.42#ibcon#wrote, iclass 21, count 0 2006.285.06:19:35.42#ibcon#about to read 3, iclass 21, count 0 2006.285.06:19:35.44#ibcon#read 3, iclass 21, count 0 2006.285.06:19:35.44#ibcon#about to read 4, iclass 21, count 0 2006.285.06:19:35.44#ibcon#read 4, iclass 21, count 0 2006.285.06:19:35.44#ibcon#about to read 5, iclass 21, count 0 2006.285.06:19:35.44#ibcon#read 5, iclass 21, count 0 2006.285.06:19:35.44#ibcon#about to read 6, iclass 21, count 0 2006.285.06:19:35.44#ibcon#read 6, iclass 21, count 0 2006.285.06:19:35.44#ibcon#end of sib2, iclass 21, count 0 2006.285.06:19:35.44#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:19:35.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:19:35.44#ibcon#[25=USB\r\n] 2006.285.06:19:35.44#ibcon#*before write, iclass 21, count 0 2006.285.06:19:35.44#ibcon#enter sib2, iclass 21, count 0 2006.285.06:19:35.44#ibcon#flushed, iclass 21, count 0 2006.285.06:19:35.44#ibcon#about to write, iclass 21, count 0 2006.285.06:19:35.44#ibcon#wrote, iclass 21, count 0 2006.285.06:19:35.44#ibcon#about to read 3, iclass 21, count 0 2006.285.06:19:35.47#ibcon#read 3, iclass 21, count 0 2006.285.06:19:35.47#ibcon#about to read 4, iclass 21, count 0 2006.285.06:19:35.47#ibcon#read 4, iclass 21, count 0 2006.285.06:19:35.47#ibcon#about to read 5, iclass 21, count 0 2006.285.06:19:35.47#ibcon#read 5, iclass 21, count 0 2006.285.06:19:35.47#ibcon#about to read 6, iclass 21, count 0 2006.285.06:19:35.47#ibcon#read 6, iclass 21, count 0 2006.285.06:19:35.47#ibcon#end of sib2, iclass 21, count 0 2006.285.06:19:35.47#ibcon#*after write, iclass 21, count 0 2006.285.06:19:35.47#ibcon#*before return 0, iclass 21, count 0 2006.285.06:19:35.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:19:35.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:19:35.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:19:35.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:19:35.47$vck44/valo=3,564.99 2006.285.06:19:35.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.06:19:35.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.06:19:35.47#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:35.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:19:35.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:19:35.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:19:35.47#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:19:35.47#ibcon#first serial, iclass 23, count 0 2006.285.06:19:35.47#ibcon#enter sib2, iclass 23, count 0 2006.285.06:19:35.47#ibcon#flushed, iclass 23, count 0 2006.285.06:19:35.47#ibcon#about to write, iclass 23, count 0 2006.285.06:19:35.47#ibcon#wrote, iclass 23, count 0 2006.285.06:19:35.47#ibcon#about to read 3, iclass 23, count 0 2006.285.06:19:35.49#ibcon#read 3, iclass 23, count 0 2006.285.06:19:35.49#ibcon#about to read 4, iclass 23, count 0 2006.285.06:19:35.49#ibcon#read 4, iclass 23, count 0 2006.285.06:19:35.49#ibcon#about to read 5, iclass 23, count 0 2006.285.06:19:35.49#ibcon#read 5, iclass 23, count 0 2006.285.06:19:35.49#ibcon#about to read 6, iclass 23, count 0 2006.285.06:19:35.49#ibcon#read 6, iclass 23, count 0 2006.285.06:19:35.49#ibcon#end of sib2, iclass 23, count 0 2006.285.06:19:35.49#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:19:35.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:19:35.49#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:19:35.49#ibcon#*before write, iclass 23, count 0 2006.285.06:19:35.49#ibcon#enter sib2, iclass 23, count 0 2006.285.06:19:35.49#ibcon#flushed, iclass 23, count 0 2006.285.06:19:35.49#ibcon#about to write, iclass 23, count 0 2006.285.06:19:35.49#ibcon#wrote, iclass 23, count 0 2006.285.06:19:35.49#ibcon#about to read 3, iclass 23, count 0 2006.285.06:19:35.53#ibcon#read 3, iclass 23, count 0 2006.285.06:19:35.53#ibcon#about to read 4, iclass 23, count 0 2006.285.06:19:35.53#ibcon#read 4, iclass 23, count 0 2006.285.06:19:35.53#ibcon#about to read 5, iclass 23, count 0 2006.285.06:19:35.53#ibcon#read 5, iclass 23, count 0 2006.285.06:19:35.53#ibcon#about to read 6, iclass 23, count 0 2006.285.06:19:35.53#ibcon#read 6, iclass 23, count 0 2006.285.06:19:35.53#ibcon#end of sib2, iclass 23, count 0 2006.285.06:19:35.53#ibcon#*after write, iclass 23, count 0 2006.285.06:19:35.53#ibcon#*before return 0, iclass 23, count 0 2006.285.06:19:35.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:19:35.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:19:35.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:19:35.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:19:35.53$vck44/va=3,7 2006.285.06:19:35.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.06:19:35.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.06:19:35.53#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:35.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:19:35.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:19:35.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:19:35.59#ibcon#enter wrdev, iclass 25, count 2 2006.285.06:19:35.59#ibcon#first serial, iclass 25, count 2 2006.285.06:19:35.59#ibcon#enter sib2, iclass 25, count 2 2006.285.06:19:35.59#ibcon#flushed, iclass 25, count 2 2006.285.06:19:35.59#ibcon#about to write, iclass 25, count 2 2006.285.06:19:35.59#ibcon#wrote, iclass 25, count 2 2006.285.06:19:35.59#ibcon#about to read 3, iclass 25, count 2 2006.285.06:19:35.61#ibcon#read 3, iclass 25, count 2 2006.285.06:19:35.61#ibcon#about to read 4, iclass 25, count 2 2006.285.06:19:35.61#ibcon#read 4, iclass 25, count 2 2006.285.06:19:35.61#ibcon#about to read 5, iclass 25, count 2 2006.285.06:19:35.61#ibcon#read 5, iclass 25, count 2 2006.285.06:19:35.61#ibcon#about to read 6, iclass 25, count 2 2006.285.06:19:35.61#ibcon#read 6, iclass 25, count 2 2006.285.06:19:35.61#ibcon#end of sib2, iclass 25, count 2 2006.285.06:19:35.61#ibcon#*mode == 0, iclass 25, count 2 2006.285.06:19:35.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.06:19:35.61#ibcon#[25=AT03-07\r\n] 2006.285.06:19:35.61#ibcon#*before write, iclass 25, count 2 2006.285.06:19:35.61#ibcon#enter sib2, iclass 25, count 2 2006.285.06:19:35.61#ibcon#flushed, iclass 25, count 2 2006.285.06:19:35.61#ibcon#about to write, iclass 25, count 2 2006.285.06:19:35.61#ibcon#wrote, iclass 25, count 2 2006.285.06:19:35.61#ibcon#about to read 3, iclass 25, count 2 2006.285.06:19:35.64#ibcon#read 3, iclass 25, count 2 2006.285.06:19:35.64#ibcon#about to read 4, iclass 25, count 2 2006.285.06:19:35.64#ibcon#read 4, iclass 25, count 2 2006.285.06:19:35.64#ibcon#about to read 5, iclass 25, count 2 2006.285.06:19:35.64#ibcon#read 5, iclass 25, count 2 2006.285.06:19:35.64#ibcon#about to read 6, iclass 25, count 2 2006.285.06:19:35.64#ibcon#read 6, iclass 25, count 2 2006.285.06:19:35.64#ibcon#end of sib2, iclass 25, count 2 2006.285.06:19:35.64#ibcon#*after write, iclass 25, count 2 2006.285.06:19:35.64#ibcon#*before return 0, iclass 25, count 2 2006.285.06:19:35.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:19:35.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:19:35.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.06:19:35.64#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:35.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:19:35.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:19:35.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:19:35.76#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:19:35.76#ibcon#first serial, iclass 25, count 0 2006.285.06:19:35.76#ibcon#enter sib2, iclass 25, count 0 2006.285.06:19:35.76#ibcon#flushed, iclass 25, count 0 2006.285.06:19:35.76#ibcon#about to write, iclass 25, count 0 2006.285.06:19:35.76#ibcon#wrote, iclass 25, count 0 2006.285.06:19:35.76#ibcon#about to read 3, iclass 25, count 0 2006.285.06:19:35.78#ibcon#read 3, iclass 25, count 0 2006.285.06:19:35.78#ibcon#about to read 4, iclass 25, count 0 2006.285.06:19:35.78#ibcon#read 4, iclass 25, count 0 2006.285.06:19:35.78#ibcon#about to read 5, iclass 25, count 0 2006.285.06:19:35.78#ibcon#read 5, iclass 25, count 0 2006.285.06:19:35.78#ibcon#about to read 6, iclass 25, count 0 2006.285.06:19:35.78#ibcon#read 6, iclass 25, count 0 2006.285.06:19:35.78#ibcon#end of sib2, iclass 25, count 0 2006.285.06:19:35.78#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:19:35.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:19:35.78#ibcon#[25=USB\r\n] 2006.285.06:19:35.78#ibcon#*before write, iclass 25, count 0 2006.285.06:19:35.78#ibcon#enter sib2, iclass 25, count 0 2006.285.06:19:35.78#ibcon#flushed, iclass 25, count 0 2006.285.06:19:35.78#ibcon#about to write, iclass 25, count 0 2006.285.06:19:35.78#ibcon#wrote, iclass 25, count 0 2006.285.06:19:35.78#ibcon#about to read 3, iclass 25, count 0 2006.285.06:19:35.81#ibcon#read 3, iclass 25, count 0 2006.285.06:19:35.81#ibcon#about to read 4, iclass 25, count 0 2006.285.06:19:35.81#ibcon#read 4, iclass 25, count 0 2006.285.06:19:35.81#ibcon#about to read 5, iclass 25, count 0 2006.285.06:19:35.81#ibcon#read 5, iclass 25, count 0 2006.285.06:19:35.81#ibcon#about to read 6, iclass 25, count 0 2006.285.06:19:35.81#ibcon#read 6, iclass 25, count 0 2006.285.06:19:35.81#ibcon#end of sib2, iclass 25, count 0 2006.285.06:19:35.81#ibcon#*after write, iclass 25, count 0 2006.285.06:19:35.81#ibcon#*before return 0, iclass 25, count 0 2006.285.06:19:35.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:19:35.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:19:35.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:19:35.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:19:35.81$vck44/valo=4,624.99 2006.285.06:19:35.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.06:19:35.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.06:19:35.81#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:35.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:19:35.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:19:35.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:19:35.81#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:19:35.81#ibcon#first serial, iclass 27, count 0 2006.285.06:19:35.81#ibcon#enter sib2, iclass 27, count 0 2006.285.06:19:35.81#ibcon#flushed, iclass 27, count 0 2006.285.06:19:35.81#ibcon#about to write, iclass 27, count 0 2006.285.06:19:35.81#ibcon#wrote, iclass 27, count 0 2006.285.06:19:35.81#ibcon#about to read 3, iclass 27, count 0 2006.285.06:19:35.83#ibcon#read 3, iclass 27, count 0 2006.285.06:19:35.83#ibcon#about to read 4, iclass 27, count 0 2006.285.06:19:35.83#ibcon#read 4, iclass 27, count 0 2006.285.06:19:35.83#ibcon#about to read 5, iclass 27, count 0 2006.285.06:19:35.83#ibcon#read 5, iclass 27, count 0 2006.285.06:19:35.83#ibcon#about to read 6, iclass 27, count 0 2006.285.06:19:35.83#ibcon#read 6, iclass 27, count 0 2006.285.06:19:35.83#ibcon#end of sib2, iclass 27, count 0 2006.285.06:19:35.83#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:19:35.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:19:35.83#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:19:35.83#ibcon#*before write, iclass 27, count 0 2006.285.06:19:35.83#ibcon#enter sib2, iclass 27, count 0 2006.285.06:19:35.83#ibcon#flushed, iclass 27, count 0 2006.285.06:19:35.83#ibcon#about to write, iclass 27, count 0 2006.285.06:19:35.83#ibcon#wrote, iclass 27, count 0 2006.285.06:19:35.83#ibcon#about to read 3, iclass 27, count 0 2006.285.06:19:35.87#ibcon#read 3, iclass 27, count 0 2006.285.06:19:35.87#ibcon#about to read 4, iclass 27, count 0 2006.285.06:19:35.87#ibcon#read 4, iclass 27, count 0 2006.285.06:19:35.87#ibcon#about to read 5, iclass 27, count 0 2006.285.06:19:35.87#ibcon#read 5, iclass 27, count 0 2006.285.06:19:35.87#ibcon#about to read 6, iclass 27, count 0 2006.285.06:19:35.87#ibcon#read 6, iclass 27, count 0 2006.285.06:19:35.87#ibcon#end of sib2, iclass 27, count 0 2006.285.06:19:35.87#ibcon#*after write, iclass 27, count 0 2006.285.06:19:35.87#ibcon#*before return 0, iclass 27, count 0 2006.285.06:19:35.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:19:35.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:19:35.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:19:35.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:19:35.87$vck44/va=4,6 2006.285.06:19:35.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.06:19:35.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.06:19:35.87#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:35.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:19:35.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:19:35.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:19:35.93#ibcon#enter wrdev, iclass 29, count 2 2006.285.06:19:35.93#ibcon#first serial, iclass 29, count 2 2006.285.06:19:35.93#ibcon#enter sib2, iclass 29, count 2 2006.285.06:19:35.93#ibcon#flushed, iclass 29, count 2 2006.285.06:19:35.93#ibcon#about to write, iclass 29, count 2 2006.285.06:19:35.93#ibcon#wrote, iclass 29, count 2 2006.285.06:19:35.93#ibcon#about to read 3, iclass 29, count 2 2006.285.06:19:35.95#ibcon#read 3, iclass 29, count 2 2006.285.06:19:35.95#ibcon#about to read 4, iclass 29, count 2 2006.285.06:19:35.95#ibcon#read 4, iclass 29, count 2 2006.285.06:19:35.95#ibcon#about to read 5, iclass 29, count 2 2006.285.06:19:35.95#ibcon#read 5, iclass 29, count 2 2006.285.06:19:35.95#ibcon#about to read 6, iclass 29, count 2 2006.285.06:19:35.95#ibcon#read 6, iclass 29, count 2 2006.285.06:19:35.95#ibcon#end of sib2, iclass 29, count 2 2006.285.06:19:35.95#ibcon#*mode == 0, iclass 29, count 2 2006.285.06:19:35.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.06:19:35.95#ibcon#[25=AT04-06\r\n] 2006.285.06:19:35.95#ibcon#*before write, iclass 29, count 2 2006.285.06:19:35.95#ibcon#enter sib2, iclass 29, count 2 2006.285.06:19:35.95#ibcon#flushed, iclass 29, count 2 2006.285.06:19:35.95#ibcon#about to write, iclass 29, count 2 2006.285.06:19:35.95#ibcon#wrote, iclass 29, count 2 2006.285.06:19:35.95#ibcon#about to read 3, iclass 29, count 2 2006.285.06:19:35.98#ibcon#read 3, iclass 29, count 2 2006.285.06:19:35.98#ibcon#about to read 4, iclass 29, count 2 2006.285.06:19:35.98#ibcon#read 4, iclass 29, count 2 2006.285.06:19:35.98#ibcon#about to read 5, iclass 29, count 2 2006.285.06:19:35.98#ibcon#read 5, iclass 29, count 2 2006.285.06:19:35.98#ibcon#about to read 6, iclass 29, count 2 2006.285.06:19:35.98#ibcon#read 6, iclass 29, count 2 2006.285.06:19:35.98#ibcon#end of sib2, iclass 29, count 2 2006.285.06:19:35.98#ibcon#*after write, iclass 29, count 2 2006.285.06:19:35.98#ibcon#*before return 0, iclass 29, count 2 2006.285.06:19:35.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:19:35.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:19:35.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.06:19:35.98#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:35.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:19:36.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:19:36.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:19:36.10#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:19:36.10#ibcon#first serial, iclass 29, count 0 2006.285.06:19:36.10#ibcon#enter sib2, iclass 29, count 0 2006.285.06:19:36.10#ibcon#flushed, iclass 29, count 0 2006.285.06:19:36.10#ibcon#about to write, iclass 29, count 0 2006.285.06:19:36.10#ibcon#wrote, iclass 29, count 0 2006.285.06:19:36.10#ibcon#about to read 3, iclass 29, count 0 2006.285.06:19:36.12#ibcon#read 3, iclass 29, count 0 2006.285.06:19:36.12#ibcon#about to read 4, iclass 29, count 0 2006.285.06:19:36.12#ibcon#read 4, iclass 29, count 0 2006.285.06:19:36.12#ibcon#about to read 5, iclass 29, count 0 2006.285.06:19:36.12#ibcon#read 5, iclass 29, count 0 2006.285.06:19:36.12#ibcon#about to read 6, iclass 29, count 0 2006.285.06:19:36.12#ibcon#read 6, iclass 29, count 0 2006.285.06:19:36.12#ibcon#end of sib2, iclass 29, count 0 2006.285.06:19:36.12#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:19:36.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:19:36.12#ibcon#[25=USB\r\n] 2006.285.06:19:36.12#ibcon#*before write, iclass 29, count 0 2006.285.06:19:36.12#ibcon#enter sib2, iclass 29, count 0 2006.285.06:19:36.12#ibcon#flushed, iclass 29, count 0 2006.285.06:19:36.12#ibcon#about to write, iclass 29, count 0 2006.285.06:19:36.12#ibcon#wrote, iclass 29, count 0 2006.285.06:19:36.12#ibcon#about to read 3, iclass 29, count 0 2006.285.06:19:36.15#ibcon#read 3, iclass 29, count 0 2006.285.06:19:36.15#ibcon#about to read 4, iclass 29, count 0 2006.285.06:19:36.15#ibcon#read 4, iclass 29, count 0 2006.285.06:19:36.15#ibcon#about to read 5, iclass 29, count 0 2006.285.06:19:36.15#ibcon#read 5, iclass 29, count 0 2006.285.06:19:36.15#ibcon#about to read 6, iclass 29, count 0 2006.285.06:19:36.15#ibcon#read 6, iclass 29, count 0 2006.285.06:19:36.15#ibcon#end of sib2, iclass 29, count 0 2006.285.06:19:36.15#ibcon#*after write, iclass 29, count 0 2006.285.06:19:36.15#ibcon#*before return 0, iclass 29, count 0 2006.285.06:19:36.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:19:36.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:19:36.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:19:36.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:19:36.15$vck44/valo=5,734.99 2006.285.06:19:36.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.06:19:36.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.06:19:36.15#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:36.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:19:36.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:19:36.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:19:36.15#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:19:36.15#ibcon#first serial, iclass 31, count 0 2006.285.06:19:36.15#ibcon#enter sib2, iclass 31, count 0 2006.285.06:19:36.15#ibcon#flushed, iclass 31, count 0 2006.285.06:19:36.15#ibcon#about to write, iclass 31, count 0 2006.285.06:19:36.15#ibcon#wrote, iclass 31, count 0 2006.285.06:19:36.15#ibcon#about to read 3, iclass 31, count 0 2006.285.06:19:36.17#ibcon#read 3, iclass 31, count 0 2006.285.06:19:36.17#ibcon#about to read 4, iclass 31, count 0 2006.285.06:19:36.17#ibcon#read 4, iclass 31, count 0 2006.285.06:19:36.17#ibcon#about to read 5, iclass 31, count 0 2006.285.06:19:36.17#ibcon#read 5, iclass 31, count 0 2006.285.06:19:36.17#ibcon#about to read 6, iclass 31, count 0 2006.285.06:19:36.17#ibcon#read 6, iclass 31, count 0 2006.285.06:19:36.17#ibcon#end of sib2, iclass 31, count 0 2006.285.06:19:36.17#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:19:36.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:19:36.17#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:19:36.17#ibcon#*before write, iclass 31, count 0 2006.285.06:19:36.17#ibcon#enter sib2, iclass 31, count 0 2006.285.06:19:36.17#ibcon#flushed, iclass 31, count 0 2006.285.06:19:36.17#ibcon#about to write, iclass 31, count 0 2006.285.06:19:36.17#ibcon#wrote, iclass 31, count 0 2006.285.06:19:36.17#ibcon#about to read 3, iclass 31, count 0 2006.285.06:19:36.21#ibcon#read 3, iclass 31, count 0 2006.285.06:19:36.21#ibcon#about to read 4, iclass 31, count 0 2006.285.06:19:36.21#ibcon#read 4, iclass 31, count 0 2006.285.06:19:36.21#ibcon#about to read 5, iclass 31, count 0 2006.285.06:19:36.21#ibcon#read 5, iclass 31, count 0 2006.285.06:19:36.21#ibcon#about to read 6, iclass 31, count 0 2006.285.06:19:36.21#ibcon#read 6, iclass 31, count 0 2006.285.06:19:36.21#ibcon#end of sib2, iclass 31, count 0 2006.285.06:19:36.21#ibcon#*after write, iclass 31, count 0 2006.285.06:19:36.21#ibcon#*before return 0, iclass 31, count 0 2006.285.06:19:36.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:19:36.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:19:36.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:19:36.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:19:36.21$vck44/va=5,3 2006.285.06:19:36.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.06:19:36.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.06:19:36.21#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:36.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:19:36.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:19:36.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:19:36.27#ibcon#enter wrdev, iclass 33, count 2 2006.285.06:19:36.27#ibcon#first serial, iclass 33, count 2 2006.285.06:19:36.27#ibcon#enter sib2, iclass 33, count 2 2006.285.06:19:36.27#ibcon#flushed, iclass 33, count 2 2006.285.06:19:36.27#ibcon#about to write, iclass 33, count 2 2006.285.06:19:36.27#ibcon#wrote, iclass 33, count 2 2006.285.06:19:36.27#ibcon#about to read 3, iclass 33, count 2 2006.285.06:19:36.29#ibcon#read 3, iclass 33, count 2 2006.285.06:19:36.29#ibcon#about to read 4, iclass 33, count 2 2006.285.06:19:36.29#ibcon#read 4, iclass 33, count 2 2006.285.06:19:36.29#ibcon#about to read 5, iclass 33, count 2 2006.285.06:19:36.29#ibcon#read 5, iclass 33, count 2 2006.285.06:19:36.29#ibcon#about to read 6, iclass 33, count 2 2006.285.06:19:36.29#ibcon#read 6, iclass 33, count 2 2006.285.06:19:36.29#ibcon#end of sib2, iclass 33, count 2 2006.285.06:19:36.29#ibcon#*mode == 0, iclass 33, count 2 2006.285.06:19:36.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.06:19:36.29#ibcon#[25=AT05-03\r\n] 2006.285.06:19:36.29#ibcon#*before write, iclass 33, count 2 2006.285.06:19:36.29#ibcon#enter sib2, iclass 33, count 2 2006.285.06:19:36.29#ibcon#flushed, iclass 33, count 2 2006.285.06:19:36.29#ibcon#about to write, iclass 33, count 2 2006.285.06:19:36.29#ibcon#wrote, iclass 33, count 2 2006.285.06:19:36.29#ibcon#about to read 3, iclass 33, count 2 2006.285.06:19:36.32#ibcon#read 3, iclass 33, count 2 2006.285.06:19:36.32#ibcon#about to read 4, iclass 33, count 2 2006.285.06:19:36.32#ibcon#read 4, iclass 33, count 2 2006.285.06:19:36.32#ibcon#about to read 5, iclass 33, count 2 2006.285.06:19:36.32#ibcon#read 5, iclass 33, count 2 2006.285.06:19:36.32#ibcon#about to read 6, iclass 33, count 2 2006.285.06:19:36.32#ibcon#read 6, iclass 33, count 2 2006.285.06:19:36.32#ibcon#end of sib2, iclass 33, count 2 2006.285.06:19:36.32#ibcon#*after write, iclass 33, count 2 2006.285.06:19:36.32#ibcon#*before return 0, iclass 33, count 2 2006.285.06:19:36.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:19:36.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:19:36.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.06:19:36.32#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:36.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:19:36.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:19:36.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:19:36.44#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:19:36.44#ibcon#first serial, iclass 33, count 0 2006.285.06:19:36.44#ibcon#enter sib2, iclass 33, count 0 2006.285.06:19:36.44#ibcon#flushed, iclass 33, count 0 2006.285.06:19:36.44#ibcon#about to write, iclass 33, count 0 2006.285.06:19:36.44#ibcon#wrote, iclass 33, count 0 2006.285.06:19:36.44#ibcon#about to read 3, iclass 33, count 0 2006.285.06:19:36.46#ibcon#read 3, iclass 33, count 0 2006.285.06:19:36.46#ibcon#about to read 4, iclass 33, count 0 2006.285.06:19:36.46#ibcon#read 4, iclass 33, count 0 2006.285.06:19:36.46#ibcon#about to read 5, iclass 33, count 0 2006.285.06:19:36.46#ibcon#read 5, iclass 33, count 0 2006.285.06:19:36.46#ibcon#about to read 6, iclass 33, count 0 2006.285.06:19:36.46#ibcon#read 6, iclass 33, count 0 2006.285.06:19:36.46#ibcon#end of sib2, iclass 33, count 0 2006.285.06:19:36.46#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:19:36.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:19:36.46#ibcon#[25=USB\r\n] 2006.285.06:19:36.46#ibcon#*before write, iclass 33, count 0 2006.285.06:19:36.46#ibcon#enter sib2, iclass 33, count 0 2006.285.06:19:36.46#ibcon#flushed, iclass 33, count 0 2006.285.06:19:36.46#ibcon#about to write, iclass 33, count 0 2006.285.06:19:36.46#ibcon#wrote, iclass 33, count 0 2006.285.06:19:36.46#ibcon#about to read 3, iclass 33, count 0 2006.285.06:19:36.49#ibcon#read 3, iclass 33, count 0 2006.285.06:19:36.49#ibcon#about to read 4, iclass 33, count 0 2006.285.06:19:36.49#ibcon#read 4, iclass 33, count 0 2006.285.06:19:36.49#ibcon#about to read 5, iclass 33, count 0 2006.285.06:19:36.49#ibcon#read 5, iclass 33, count 0 2006.285.06:19:36.49#ibcon#about to read 6, iclass 33, count 0 2006.285.06:19:36.49#ibcon#read 6, iclass 33, count 0 2006.285.06:19:36.49#ibcon#end of sib2, iclass 33, count 0 2006.285.06:19:36.49#ibcon#*after write, iclass 33, count 0 2006.285.06:19:36.49#ibcon#*before return 0, iclass 33, count 0 2006.285.06:19:36.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:19:36.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:19:36.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:19:36.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:19:36.49$vck44/valo=6,814.99 2006.285.06:19:36.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.06:19:36.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.06:19:36.49#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:36.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:19:36.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:19:36.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:19:36.49#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:19:36.49#ibcon#first serial, iclass 35, count 0 2006.285.06:19:36.49#ibcon#enter sib2, iclass 35, count 0 2006.285.06:19:36.49#ibcon#flushed, iclass 35, count 0 2006.285.06:19:36.49#ibcon#about to write, iclass 35, count 0 2006.285.06:19:36.49#ibcon#wrote, iclass 35, count 0 2006.285.06:19:36.49#ibcon#about to read 3, iclass 35, count 0 2006.285.06:19:36.51#ibcon#read 3, iclass 35, count 0 2006.285.06:19:36.51#ibcon#about to read 4, iclass 35, count 0 2006.285.06:19:36.51#ibcon#read 4, iclass 35, count 0 2006.285.06:19:36.51#ibcon#about to read 5, iclass 35, count 0 2006.285.06:19:36.51#ibcon#read 5, iclass 35, count 0 2006.285.06:19:36.51#ibcon#about to read 6, iclass 35, count 0 2006.285.06:19:36.51#ibcon#read 6, iclass 35, count 0 2006.285.06:19:36.51#ibcon#end of sib2, iclass 35, count 0 2006.285.06:19:36.51#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:19:36.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:19:36.51#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:19:36.51#ibcon#*before write, iclass 35, count 0 2006.285.06:19:36.51#ibcon#enter sib2, iclass 35, count 0 2006.285.06:19:36.51#ibcon#flushed, iclass 35, count 0 2006.285.06:19:36.51#ibcon#about to write, iclass 35, count 0 2006.285.06:19:36.51#ibcon#wrote, iclass 35, count 0 2006.285.06:19:36.51#ibcon#about to read 3, iclass 35, count 0 2006.285.06:19:36.55#ibcon#read 3, iclass 35, count 0 2006.285.06:19:36.55#ibcon#about to read 4, iclass 35, count 0 2006.285.06:19:36.55#ibcon#read 4, iclass 35, count 0 2006.285.06:19:36.55#ibcon#about to read 5, iclass 35, count 0 2006.285.06:19:36.55#ibcon#read 5, iclass 35, count 0 2006.285.06:19:36.55#ibcon#about to read 6, iclass 35, count 0 2006.285.06:19:36.55#ibcon#read 6, iclass 35, count 0 2006.285.06:19:36.55#ibcon#end of sib2, iclass 35, count 0 2006.285.06:19:36.55#ibcon#*after write, iclass 35, count 0 2006.285.06:19:36.55#ibcon#*before return 0, iclass 35, count 0 2006.285.06:19:36.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:19:36.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:19:36.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:19:36.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:19:36.55$vck44/va=6,4 2006.285.06:19:36.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.06:19:36.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.06:19:36.55#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:36.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:19:36.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:19:36.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:19:36.61#ibcon#enter wrdev, iclass 37, count 2 2006.285.06:19:36.61#ibcon#first serial, iclass 37, count 2 2006.285.06:19:36.61#ibcon#enter sib2, iclass 37, count 2 2006.285.06:19:36.61#ibcon#flushed, iclass 37, count 2 2006.285.06:19:36.61#ibcon#about to write, iclass 37, count 2 2006.285.06:19:36.61#ibcon#wrote, iclass 37, count 2 2006.285.06:19:36.61#ibcon#about to read 3, iclass 37, count 2 2006.285.06:19:36.63#ibcon#read 3, iclass 37, count 2 2006.285.06:19:36.63#ibcon#about to read 4, iclass 37, count 2 2006.285.06:19:36.63#ibcon#read 4, iclass 37, count 2 2006.285.06:19:36.63#ibcon#about to read 5, iclass 37, count 2 2006.285.06:19:36.63#ibcon#read 5, iclass 37, count 2 2006.285.06:19:36.63#ibcon#about to read 6, iclass 37, count 2 2006.285.06:19:36.63#ibcon#read 6, iclass 37, count 2 2006.285.06:19:36.63#ibcon#end of sib2, iclass 37, count 2 2006.285.06:19:36.63#ibcon#*mode == 0, iclass 37, count 2 2006.285.06:19:36.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.06:19:36.63#ibcon#[25=AT06-04\r\n] 2006.285.06:19:36.63#ibcon#*before write, iclass 37, count 2 2006.285.06:19:36.63#ibcon#enter sib2, iclass 37, count 2 2006.285.06:19:36.63#ibcon#flushed, iclass 37, count 2 2006.285.06:19:36.63#ibcon#about to write, iclass 37, count 2 2006.285.06:19:36.63#ibcon#wrote, iclass 37, count 2 2006.285.06:19:36.63#ibcon#about to read 3, iclass 37, count 2 2006.285.06:19:36.66#ibcon#read 3, iclass 37, count 2 2006.285.06:19:36.66#ibcon#about to read 4, iclass 37, count 2 2006.285.06:19:36.66#ibcon#read 4, iclass 37, count 2 2006.285.06:19:36.66#ibcon#about to read 5, iclass 37, count 2 2006.285.06:19:36.66#ibcon#read 5, iclass 37, count 2 2006.285.06:19:36.66#ibcon#about to read 6, iclass 37, count 2 2006.285.06:19:36.66#ibcon#read 6, iclass 37, count 2 2006.285.06:19:36.66#ibcon#end of sib2, iclass 37, count 2 2006.285.06:19:36.66#ibcon#*after write, iclass 37, count 2 2006.285.06:19:36.66#ibcon#*before return 0, iclass 37, count 2 2006.285.06:19:36.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:19:36.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:19:36.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.06:19:36.66#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:36.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:19:36.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:19:36.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:19:36.78#ibcon#enter wrdev, iclass 37, count 0 2006.285.06:19:36.78#ibcon#first serial, iclass 37, count 0 2006.285.06:19:36.78#ibcon#enter sib2, iclass 37, count 0 2006.285.06:19:36.78#ibcon#flushed, iclass 37, count 0 2006.285.06:19:36.78#ibcon#about to write, iclass 37, count 0 2006.285.06:19:36.78#ibcon#wrote, iclass 37, count 0 2006.285.06:19:36.78#ibcon#about to read 3, iclass 37, count 0 2006.285.06:19:36.80#ibcon#read 3, iclass 37, count 0 2006.285.06:19:36.80#ibcon#about to read 4, iclass 37, count 0 2006.285.06:19:36.80#ibcon#read 4, iclass 37, count 0 2006.285.06:19:36.80#ibcon#about to read 5, iclass 37, count 0 2006.285.06:19:36.80#ibcon#read 5, iclass 37, count 0 2006.285.06:19:36.80#ibcon#about to read 6, iclass 37, count 0 2006.285.06:19:36.80#ibcon#read 6, iclass 37, count 0 2006.285.06:19:36.80#ibcon#end of sib2, iclass 37, count 0 2006.285.06:19:36.80#ibcon#*mode == 0, iclass 37, count 0 2006.285.06:19:36.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.06:19:36.80#ibcon#[25=USB\r\n] 2006.285.06:19:36.80#ibcon#*before write, iclass 37, count 0 2006.285.06:19:36.80#ibcon#enter sib2, iclass 37, count 0 2006.285.06:19:36.80#ibcon#flushed, iclass 37, count 0 2006.285.06:19:36.80#ibcon#about to write, iclass 37, count 0 2006.285.06:19:36.80#ibcon#wrote, iclass 37, count 0 2006.285.06:19:36.80#ibcon#about to read 3, iclass 37, count 0 2006.285.06:19:36.83#ibcon#read 3, iclass 37, count 0 2006.285.06:19:36.83#ibcon#about to read 4, iclass 37, count 0 2006.285.06:19:36.83#ibcon#read 4, iclass 37, count 0 2006.285.06:19:36.83#ibcon#about to read 5, iclass 37, count 0 2006.285.06:19:36.83#ibcon#read 5, iclass 37, count 0 2006.285.06:19:36.83#ibcon#about to read 6, iclass 37, count 0 2006.285.06:19:36.83#ibcon#read 6, iclass 37, count 0 2006.285.06:19:36.83#ibcon#end of sib2, iclass 37, count 0 2006.285.06:19:36.83#ibcon#*after write, iclass 37, count 0 2006.285.06:19:36.83#ibcon#*before return 0, iclass 37, count 0 2006.285.06:19:36.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:19:36.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:19:36.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.06:19:36.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.06:19:36.83$vck44/valo=7,864.99 2006.285.06:19:36.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.06:19:36.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.06:19:36.83#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:36.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:19:36.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:19:36.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:19:36.83#ibcon#enter wrdev, iclass 39, count 0 2006.285.06:19:36.83#ibcon#first serial, iclass 39, count 0 2006.285.06:19:36.83#ibcon#enter sib2, iclass 39, count 0 2006.285.06:19:36.83#ibcon#flushed, iclass 39, count 0 2006.285.06:19:36.83#ibcon#about to write, iclass 39, count 0 2006.285.06:19:36.83#ibcon#wrote, iclass 39, count 0 2006.285.06:19:36.83#ibcon#about to read 3, iclass 39, count 0 2006.285.06:19:36.85#ibcon#read 3, iclass 39, count 0 2006.285.06:19:36.85#ibcon#about to read 4, iclass 39, count 0 2006.285.06:19:36.85#ibcon#read 4, iclass 39, count 0 2006.285.06:19:36.85#ibcon#about to read 5, iclass 39, count 0 2006.285.06:19:36.85#ibcon#read 5, iclass 39, count 0 2006.285.06:19:36.85#ibcon#about to read 6, iclass 39, count 0 2006.285.06:19:36.85#ibcon#read 6, iclass 39, count 0 2006.285.06:19:36.85#ibcon#end of sib2, iclass 39, count 0 2006.285.06:19:36.85#ibcon#*mode == 0, iclass 39, count 0 2006.285.06:19:36.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.06:19:36.85#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:19:36.85#ibcon#*before write, iclass 39, count 0 2006.285.06:19:36.85#ibcon#enter sib2, iclass 39, count 0 2006.285.06:19:36.85#ibcon#flushed, iclass 39, count 0 2006.285.06:19:36.85#ibcon#about to write, iclass 39, count 0 2006.285.06:19:36.85#ibcon#wrote, iclass 39, count 0 2006.285.06:19:36.85#ibcon#about to read 3, iclass 39, count 0 2006.285.06:19:36.89#ibcon#read 3, iclass 39, count 0 2006.285.06:19:36.89#ibcon#about to read 4, iclass 39, count 0 2006.285.06:19:36.89#ibcon#read 4, iclass 39, count 0 2006.285.06:19:36.89#ibcon#about to read 5, iclass 39, count 0 2006.285.06:19:36.89#ibcon#read 5, iclass 39, count 0 2006.285.06:19:36.89#ibcon#about to read 6, iclass 39, count 0 2006.285.06:19:36.89#ibcon#read 6, iclass 39, count 0 2006.285.06:19:36.89#ibcon#end of sib2, iclass 39, count 0 2006.285.06:19:36.89#ibcon#*after write, iclass 39, count 0 2006.285.06:19:36.89#ibcon#*before return 0, iclass 39, count 0 2006.285.06:19:36.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:19:36.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:19:36.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.06:19:36.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.06:19:36.89$vck44/va=7,4 2006.285.06:19:36.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.06:19:36.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.06:19:36.89#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:36.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:19:36.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:19:36.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:19:36.95#ibcon#enter wrdev, iclass 3, count 2 2006.285.06:19:36.95#ibcon#first serial, iclass 3, count 2 2006.285.06:19:36.95#ibcon#enter sib2, iclass 3, count 2 2006.285.06:19:36.95#ibcon#flushed, iclass 3, count 2 2006.285.06:19:36.95#ibcon#about to write, iclass 3, count 2 2006.285.06:19:36.95#ibcon#wrote, iclass 3, count 2 2006.285.06:19:36.95#ibcon#about to read 3, iclass 3, count 2 2006.285.06:19:36.97#ibcon#read 3, iclass 3, count 2 2006.285.06:19:36.97#ibcon#about to read 4, iclass 3, count 2 2006.285.06:19:36.97#ibcon#read 4, iclass 3, count 2 2006.285.06:19:36.97#ibcon#about to read 5, iclass 3, count 2 2006.285.06:19:36.97#ibcon#read 5, iclass 3, count 2 2006.285.06:19:36.97#ibcon#about to read 6, iclass 3, count 2 2006.285.06:19:36.97#ibcon#read 6, iclass 3, count 2 2006.285.06:19:36.97#ibcon#end of sib2, iclass 3, count 2 2006.285.06:19:36.97#ibcon#*mode == 0, iclass 3, count 2 2006.285.06:19:36.97#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.06:19:36.97#ibcon#[25=AT07-04\r\n] 2006.285.06:19:36.97#ibcon#*before write, iclass 3, count 2 2006.285.06:19:36.97#ibcon#enter sib2, iclass 3, count 2 2006.285.06:19:36.97#ibcon#flushed, iclass 3, count 2 2006.285.06:19:36.97#ibcon#about to write, iclass 3, count 2 2006.285.06:19:36.97#ibcon#wrote, iclass 3, count 2 2006.285.06:19:36.97#ibcon#about to read 3, iclass 3, count 2 2006.285.06:19:37.00#ibcon#read 3, iclass 3, count 2 2006.285.06:19:37.00#ibcon#about to read 4, iclass 3, count 2 2006.285.06:19:37.00#ibcon#read 4, iclass 3, count 2 2006.285.06:19:37.00#ibcon#about to read 5, iclass 3, count 2 2006.285.06:19:37.00#ibcon#read 5, iclass 3, count 2 2006.285.06:19:37.00#ibcon#about to read 6, iclass 3, count 2 2006.285.06:19:37.00#ibcon#read 6, iclass 3, count 2 2006.285.06:19:37.00#ibcon#end of sib2, iclass 3, count 2 2006.285.06:19:37.00#ibcon#*after write, iclass 3, count 2 2006.285.06:19:37.00#ibcon#*before return 0, iclass 3, count 2 2006.285.06:19:37.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:19:37.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:19:37.00#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.06:19:37.00#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:37.00#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:19:37.12#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:19:37.12#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:19:37.12#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:19:37.12#ibcon#first serial, iclass 3, count 0 2006.285.06:19:37.12#ibcon#enter sib2, iclass 3, count 0 2006.285.06:19:37.12#ibcon#flushed, iclass 3, count 0 2006.285.06:19:37.12#ibcon#about to write, iclass 3, count 0 2006.285.06:19:37.12#ibcon#wrote, iclass 3, count 0 2006.285.06:19:37.12#ibcon#about to read 3, iclass 3, count 0 2006.285.06:19:37.14#ibcon#read 3, iclass 3, count 0 2006.285.06:19:37.14#ibcon#about to read 4, iclass 3, count 0 2006.285.06:19:37.14#ibcon#read 4, iclass 3, count 0 2006.285.06:19:37.14#ibcon#about to read 5, iclass 3, count 0 2006.285.06:19:37.14#ibcon#read 5, iclass 3, count 0 2006.285.06:19:37.14#ibcon#about to read 6, iclass 3, count 0 2006.285.06:19:37.14#ibcon#read 6, iclass 3, count 0 2006.285.06:19:37.14#ibcon#end of sib2, iclass 3, count 0 2006.285.06:19:37.14#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:19:37.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:19:37.14#ibcon#[25=USB\r\n] 2006.285.06:19:37.14#ibcon#*before write, iclass 3, count 0 2006.285.06:19:37.14#ibcon#enter sib2, iclass 3, count 0 2006.285.06:19:37.14#ibcon#flushed, iclass 3, count 0 2006.285.06:19:37.14#ibcon#about to write, iclass 3, count 0 2006.285.06:19:37.14#ibcon#wrote, iclass 3, count 0 2006.285.06:19:37.14#ibcon#about to read 3, iclass 3, count 0 2006.285.06:19:37.17#ibcon#read 3, iclass 3, count 0 2006.285.06:19:37.17#ibcon#about to read 4, iclass 3, count 0 2006.285.06:19:37.17#ibcon#read 4, iclass 3, count 0 2006.285.06:19:37.17#ibcon#about to read 5, iclass 3, count 0 2006.285.06:19:37.17#ibcon#read 5, iclass 3, count 0 2006.285.06:19:37.17#ibcon#about to read 6, iclass 3, count 0 2006.285.06:19:37.17#ibcon#read 6, iclass 3, count 0 2006.285.06:19:37.17#ibcon#end of sib2, iclass 3, count 0 2006.285.06:19:37.17#ibcon#*after write, iclass 3, count 0 2006.285.06:19:37.17#ibcon#*before return 0, iclass 3, count 0 2006.285.06:19:37.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:19:37.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:19:37.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:19:37.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:19:37.17$vck44/valo=8,884.99 2006.285.06:19:37.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.06:19:37.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.06:19:37.17#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:37.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:19:37.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:19:37.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:19:37.17#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:19:37.17#ibcon#first serial, iclass 5, count 0 2006.285.06:19:37.17#ibcon#enter sib2, iclass 5, count 0 2006.285.06:19:37.17#ibcon#flushed, iclass 5, count 0 2006.285.06:19:37.17#ibcon#about to write, iclass 5, count 0 2006.285.06:19:37.17#ibcon#wrote, iclass 5, count 0 2006.285.06:19:37.17#ibcon#about to read 3, iclass 5, count 0 2006.285.06:19:37.19#ibcon#read 3, iclass 5, count 0 2006.285.06:19:37.19#ibcon#about to read 4, iclass 5, count 0 2006.285.06:19:37.19#ibcon#read 4, iclass 5, count 0 2006.285.06:19:37.19#ibcon#about to read 5, iclass 5, count 0 2006.285.06:19:37.19#ibcon#read 5, iclass 5, count 0 2006.285.06:19:37.19#ibcon#about to read 6, iclass 5, count 0 2006.285.06:19:37.19#ibcon#read 6, iclass 5, count 0 2006.285.06:19:37.19#ibcon#end of sib2, iclass 5, count 0 2006.285.06:19:37.19#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:19:37.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:19:37.19#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:19:37.19#ibcon#*before write, iclass 5, count 0 2006.285.06:19:37.19#ibcon#enter sib2, iclass 5, count 0 2006.285.06:19:37.19#ibcon#flushed, iclass 5, count 0 2006.285.06:19:37.19#ibcon#about to write, iclass 5, count 0 2006.285.06:19:37.19#ibcon#wrote, iclass 5, count 0 2006.285.06:19:37.19#ibcon#about to read 3, iclass 5, count 0 2006.285.06:19:37.23#ibcon#read 3, iclass 5, count 0 2006.285.06:19:37.23#ibcon#about to read 4, iclass 5, count 0 2006.285.06:19:37.23#ibcon#read 4, iclass 5, count 0 2006.285.06:19:37.23#ibcon#about to read 5, iclass 5, count 0 2006.285.06:19:37.23#ibcon#read 5, iclass 5, count 0 2006.285.06:19:37.23#ibcon#about to read 6, iclass 5, count 0 2006.285.06:19:37.23#ibcon#read 6, iclass 5, count 0 2006.285.06:19:37.23#ibcon#end of sib2, iclass 5, count 0 2006.285.06:19:37.23#ibcon#*after write, iclass 5, count 0 2006.285.06:19:37.23#ibcon#*before return 0, iclass 5, count 0 2006.285.06:19:37.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:19:37.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:19:37.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:19:37.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:19:37.23$vck44/va=8,3 2006.285.06:19:37.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.06:19:37.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.06:19:37.23#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:37.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:19:37.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:19:37.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:19:37.29#ibcon#enter wrdev, iclass 7, count 2 2006.285.06:19:37.29#ibcon#first serial, iclass 7, count 2 2006.285.06:19:37.29#ibcon#enter sib2, iclass 7, count 2 2006.285.06:19:37.29#ibcon#flushed, iclass 7, count 2 2006.285.06:19:37.29#ibcon#about to write, iclass 7, count 2 2006.285.06:19:37.29#ibcon#wrote, iclass 7, count 2 2006.285.06:19:37.29#ibcon#about to read 3, iclass 7, count 2 2006.285.06:19:37.31#ibcon#read 3, iclass 7, count 2 2006.285.06:19:37.31#ibcon#about to read 4, iclass 7, count 2 2006.285.06:19:37.31#ibcon#read 4, iclass 7, count 2 2006.285.06:19:37.31#ibcon#about to read 5, iclass 7, count 2 2006.285.06:19:37.31#ibcon#read 5, iclass 7, count 2 2006.285.06:19:37.31#ibcon#about to read 6, iclass 7, count 2 2006.285.06:19:37.31#ibcon#read 6, iclass 7, count 2 2006.285.06:19:37.31#ibcon#end of sib2, iclass 7, count 2 2006.285.06:19:37.31#ibcon#*mode == 0, iclass 7, count 2 2006.285.06:19:37.31#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.06:19:37.31#ibcon#[25=AT08-03\r\n] 2006.285.06:19:37.31#ibcon#*before write, iclass 7, count 2 2006.285.06:19:37.31#ibcon#enter sib2, iclass 7, count 2 2006.285.06:19:37.31#ibcon#flushed, iclass 7, count 2 2006.285.06:19:37.31#ibcon#about to write, iclass 7, count 2 2006.285.06:19:37.31#ibcon#wrote, iclass 7, count 2 2006.285.06:19:37.31#ibcon#about to read 3, iclass 7, count 2 2006.285.06:19:37.34#ibcon#read 3, iclass 7, count 2 2006.285.06:19:37.34#ibcon#about to read 4, iclass 7, count 2 2006.285.06:19:37.34#ibcon#read 4, iclass 7, count 2 2006.285.06:19:37.34#ibcon#about to read 5, iclass 7, count 2 2006.285.06:19:37.34#ibcon#read 5, iclass 7, count 2 2006.285.06:19:37.34#ibcon#about to read 6, iclass 7, count 2 2006.285.06:19:37.34#ibcon#read 6, iclass 7, count 2 2006.285.06:19:37.34#ibcon#end of sib2, iclass 7, count 2 2006.285.06:19:37.34#ibcon#*after write, iclass 7, count 2 2006.285.06:19:37.34#ibcon#*before return 0, iclass 7, count 2 2006.285.06:19:37.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:19:37.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:19:37.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.06:19:37.34#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:37.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:19:37.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:19:37.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:19:37.46#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:19:37.46#ibcon#first serial, iclass 7, count 0 2006.285.06:19:37.46#ibcon#enter sib2, iclass 7, count 0 2006.285.06:19:37.46#ibcon#flushed, iclass 7, count 0 2006.285.06:19:37.46#ibcon#about to write, iclass 7, count 0 2006.285.06:19:37.46#ibcon#wrote, iclass 7, count 0 2006.285.06:19:37.46#ibcon#about to read 3, iclass 7, count 0 2006.285.06:19:37.48#ibcon#read 3, iclass 7, count 0 2006.285.06:19:37.48#ibcon#about to read 4, iclass 7, count 0 2006.285.06:19:37.48#ibcon#read 4, iclass 7, count 0 2006.285.06:19:37.48#ibcon#about to read 5, iclass 7, count 0 2006.285.06:19:37.48#ibcon#read 5, iclass 7, count 0 2006.285.06:19:37.48#ibcon#about to read 6, iclass 7, count 0 2006.285.06:19:37.48#ibcon#read 6, iclass 7, count 0 2006.285.06:19:37.48#ibcon#end of sib2, iclass 7, count 0 2006.285.06:19:37.48#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:19:37.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:19:37.48#ibcon#[25=USB\r\n] 2006.285.06:19:37.48#ibcon#*before write, iclass 7, count 0 2006.285.06:19:37.48#ibcon#enter sib2, iclass 7, count 0 2006.285.06:19:37.48#ibcon#flushed, iclass 7, count 0 2006.285.06:19:37.48#ibcon#about to write, iclass 7, count 0 2006.285.06:19:37.48#ibcon#wrote, iclass 7, count 0 2006.285.06:19:37.48#ibcon#about to read 3, iclass 7, count 0 2006.285.06:19:37.51#ibcon#read 3, iclass 7, count 0 2006.285.06:19:37.51#ibcon#about to read 4, iclass 7, count 0 2006.285.06:19:37.51#ibcon#read 4, iclass 7, count 0 2006.285.06:19:37.51#ibcon#about to read 5, iclass 7, count 0 2006.285.06:19:37.51#ibcon#read 5, iclass 7, count 0 2006.285.06:19:37.51#ibcon#about to read 6, iclass 7, count 0 2006.285.06:19:37.51#ibcon#read 6, iclass 7, count 0 2006.285.06:19:37.51#ibcon#end of sib2, iclass 7, count 0 2006.285.06:19:37.51#ibcon#*after write, iclass 7, count 0 2006.285.06:19:37.51#ibcon#*before return 0, iclass 7, count 0 2006.285.06:19:37.51#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:19:37.51#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:19:37.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:19:37.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:19:37.51$vck44/vblo=1,629.99 2006.285.06:19:37.51#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.06:19:37.51#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.06:19:37.51#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:37.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:19:37.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:19:37.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:19:37.51#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:19:37.51#ibcon#first serial, iclass 11, count 0 2006.285.06:19:37.51#ibcon#enter sib2, iclass 11, count 0 2006.285.06:19:37.51#ibcon#flushed, iclass 11, count 0 2006.285.06:19:37.51#ibcon#about to write, iclass 11, count 0 2006.285.06:19:37.51#ibcon#wrote, iclass 11, count 0 2006.285.06:19:37.51#ibcon#about to read 3, iclass 11, count 0 2006.285.06:19:37.53#ibcon#read 3, iclass 11, count 0 2006.285.06:19:37.53#ibcon#about to read 4, iclass 11, count 0 2006.285.06:19:37.53#ibcon#read 4, iclass 11, count 0 2006.285.06:19:37.53#ibcon#about to read 5, iclass 11, count 0 2006.285.06:19:37.53#ibcon#read 5, iclass 11, count 0 2006.285.06:19:37.53#ibcon#about to read 6, iclass 11, count 0 2006.285.06:19:37.53#ibcon#read 6, iclass 11, count 0 2006.285.06:19:37.53#ibcon#end of sib2, iclass 11, count 0 2006.285.06:19:37.53#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:19:37.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:19:37.53#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:19:37.53#ibcon#*before write, iclass 11, count 0 2006.285.06:19:37.53#ibcon#enter sib2, iclass 11, count 0 2006.285.06:19:37.53#ibcon#flushed, iclass 11, count 0 2006.285.06:19:37.53#ibcon#about to write, iclass 11, count 0 2006.285.06:19:37.53#ibcon#wrote, iclass 11, count 0 2006.285.06:19:37.53#ibcon#about to read 3, iclass 11, count 0 2006.285.06:19:37.58#ibcon#read 3, iclass 11, count 0 2006.285.06:19:37.58#ibcon#about to read 4, iclass 11, count 0 2006.285.06:19:37.58#ibcon#read 4, iclass 11, count 0 2006.285.06:19:37.58#ibcon#about to read 5, iclass 11, count 0 2006.285.06:19:37.58#ibcon#read 5, iclass 11, count 0 2006.285.06:19:37.58#ibcon#about to read 6, iclass 11, count 0 2006.285.06:19:37.58#ibcon#read 6, iclass 11, count 0 2006.285.06:19:37.58#ibcon#end of sib2, iclass 11, count 0 2006.285.06:19:37.58#ibcon#*after write, iclass 11, count 0 2006.285.06:19:37.58#ibcon#*before return 0, iclass 11, count 0 2006.285.06:19:37.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:19:37.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:19:37.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:19:37.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:19:37.58$vck44/vb=1,4 2006.285.06:19:37.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.06:19:37.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.06:19:37.58#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:37.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:19:37.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:19:37.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:19:37.58#ibcon#enter wrdev, iclass 13, count 2 2006.285.06:19:37.58#ibcon#first serial, iclass 13, count 2 2006.285.06:19:37.58#ibcon#enter sib2, iclass 13, count 2 2006.285.06:19:37.58#ibcon#flushed, iclass 13, count 2 2006.285.06:19:37.58#ibcon#about to write, iclass 13, count 2 2006.285.06:19:37.58#ibcon#wrote, iclass 13, count 2 2006.285.06:19:37.58#ibcon#about to read 3, iclass 13, count 2 2006.285.06:19:37.60#ibcon#read 3, iclass 13, count 2 2006.285.06:19:37.60#ibcon#about to read 4, iclass 13, count 2 2006.285.06:19:37.60#ibcon#read 4, iclass 13, count 2 2006.285.06:19:37.60#ibcon#about to read 5, iclass 13, count 2 2006.285.06:19:37.60#ibcon#read 5, iclass 13, count 2 2006.285.06:19:37.60#ibcon#about to read 6, iclass 13, count 2 2006.285.06:19:37.60#ibcon#read 6, iclass 13, count 2 2006.285.06:19:37.60#ibcon#end of sib2, iclass 13, count 2 2006.285.06:19:37.60#ibcon#*mode == 0, iclass 13, count 2 2006.285.06:19:37.60#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.06:19:37.60#ibcon#[27=AT01-04\r\n] 2006.285.06:19:37.60#ibcon#*before write, iclass 13, count 2 2006.285.06:19:37.60#ibcon#enter sib2, iclass 13, count 2 2006.285.06:19:37.60#ibcon#flushed, iclass 13, count 2 2006.285.06:19:37.60#ibcon#about to write, iclass 13, count 2 2006.285.06:19:37.60#ibcon#wrote, iclass 13, count 2 2006.285.06:19:37.60#ibcon#about to read 3, iclass 13, count 2 2006.285.06:19:37.63#ibcon#read 3, iclass 13, count 2 2006.285.06:19:37.63#ibcon#about to read 4, iclass 13, count 2 2006.285.06:19:37.63#ibcon#read 4, iclass 13, count 2 2006.285.06:19:37.63#ibcon#about to read 5, iclass 13, count 2 2006.285.06:19:37.63#ibcon#read 5, iclass 13, count 2 2006.285.06:19:37.63#ibcon#about to read 6, iclass 13, count 2 2006.285.06:19:37.63#ibcon#read 6, iclass 13, count 2 2006.285.06:19:37.63#ibcon#end of sib2, iclass 13, count 2 2006.285.06:19:37.63#ibcon#*after write, iclass 13, count 2 2006.285.06:19:37.63#ibcon#*before return 0, iclass 13, count 2 2006.285.06:19:37.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:19:37.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:19:37.63#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.06:19:37.63#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:37.63#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:19:37.75#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:19:37.75#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:19:37.75#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:19:37.75#ibcon#first serial, iclass 13, count 0 2006.285.06:19:37.75#ibcon#enter sib2, iclass 13, count 0 2006.285.06:19:37.75#ibcon#flushed, iclass 13, count 0 2006.285.06:19:37.75#ibcon#about to write, iclass 13, count 0 2006.285.06:19:37.75#ibcon#wrote, iclass 13, count 0 2006.285.06:19:37.75#ibcon#about to read 3, iclass 13, count 0 2006.285.06:19:37.77#ibcon#read 3, iclass 13, count 0 2006.285.06:19:37.77#ibcon#about to read 4, iclass 13, count 0 2006.285.06:19:37.77#ibcon#read 4, iclass 13, count 0 2006.285.06:19:37.77#ibcon#about to read 5, iclass 13, count 0 2006.285.06:19:37.77#ibcon#read 5, iclass 13, count 0 2006.285.06:19:37.77#ibcon#about to read 6, iclass 13, count 0 2006.285.06:19:37.77#ibcon#read 6, iclass 13, count 0 2006.285.06:19:37.77#ibcon#end of sib2, iclass 13, count 0 2006.285.06:19:37.77#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:19:37.77#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:19:37.77#ibcon#[27=USB\r\n] 2006.285.06:19:37.77#ibcon#*before write, iclass 13, count 0 2006.285.06:19:37.77#ibcon#enter sib2, iclass 13, count 0 2006.285.06:19:37.77#ibcon#flushed, iclass 13, count 0 2006.285.06:19:37.77#ibcon#about to write, iclass 13, count 0 2006.285.06:19:37.77#ibcon#wrote, iclass 13, count 0 2006.285.06:19:37.77#ibcon#about to read 3, iclass 13, count 0 2006.285.06:19:37.80#ibcon#read 3, iclass 13, count 0 2006.285.06:19:37.80#ibcon#about to read 4, iclass 13, count 0 2006.285.06:19:37.80#ibcon#read 4, iclass 13, count 0 2006.285.06:19:37.80#ibcon#about to read 5, iclass 13, count 0 2006.285.06:19:37.80#ibcon#read 5, iclass 13, count 0 2006.285.06:19:37.80#ibcon#about to read 6, iclass 13, count 0 2006.285.06:19:37.80#ibcon#read 6, iclass 13, count 0 2006.285.06:19:37.80#ibcon#end of sib2, iclass 13, count 0 2006.285.06:19:37.80#ibcon#*after write, iclass 13, count 0 2006.285.06:19:37.80#ibcon#*before return 0, iclass 13, count 0 2006.285.06:19:37.80#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:19:37.80#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:19:37.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:19:37.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:19:37.80$vck44/vblo=2,634.99 2006.285.06:19:37.80#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.06:19:37.80#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.06:19:37.80#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:37.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:19:37.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:19:37.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:19:37.80#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:19:37.80#ibcon#first serial, iclass 15, count 0 2006.285.06:19:37.80#ibcon#enter sib2, iclass 15, count 0 2006.285.06:19:37.80#ibcon#flushed, iclass 15, count 0 2006.285.06:19:37.80#ibcon#about to write, iclass 15, count 0 2006.285.06:19:37.80#ibcon#wrote, iclass 15, count 0 2006.285.06:19:37.80#ibcon#about to read 3, iclass 15, count 0 2006.285.06:19:37.82#ibcon#read 3, iclass 15, count 0 2006.285.06:19:37.82#ibcon#about to read 4, iclass 15, count 0 2006.285.06:19:37.82#ibcon#read 4, iclass 15, count 0 2006.285.06:19:37.82#ibcon#about to read 5, iclass 15, count 0 2006.285.06:19:37.82#ibcon#read 5, iclass 15, count 0 2006.285.06:19:37.82#ibcon#about to read 6, iclass 15, count 0 2006.285.06:19:37.82#ibcon#read 6, iclass 15, count 0 2006.285.06:19:37.82#ibcon#end of sib2, iclass 15, count 0 2006.285.06:19:37.82#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:19:37.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:19:37.82#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:19:37.82#ibcon#*before write, iclass 15, count 0 2006.285.06:19:37.82#ibcon#enter sib2, iclass 15, count 0 2006.285.06:19:37.82#ibcon#flushed, iclass 15, count 0 2006.285.06:19:37.82#ibcon#about to write, iclass 15, count 0 2006.285.06:19:37.82#ibcon#wrote, iclass 15, count 0 2006.285.06:19:37.82#ibcon#about to read 3, iclass 15, count 0 2006.285.06:19:37.86#ibcon#read 3, iclass 15, count 0 2006.285.06:19:37.86#ibcon#about to read 4, iclass 15, count 0 2006.285.06:19:37.86#ibcon#read 4, iclass 15, count 0 2006.285.06:19:37.86#ibcon#about to read 5, iclass 15, count 0 2006.285.06:19:37.86#ibcon#read 5, iclass 15, count 0 2006.285.06:19:37.86#ibcon#about to read 6, iclass 15, count 0 2006.285.06:19:37.86#ibcon#read 6, iclass 15, count 0 2006.285.06:19:37.86#ibcon#end of sib2, iclass 15, count 0 2006.285.06:19:37.86#ibcon#*after write, iclass 15, count 0 2006.285.06:19:37.86#ibcon#*before return 0, iclass 15, count 0 2006.285.06:19:37.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:19:37.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:19:37.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:19:37.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:19:37.86$vck44/vb=2,5 2006.285.06:19:37.86#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.06:19:37.86#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.06:19:37.86#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:37.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:19:37.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:19:37.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:19:37.92#ibcon#enter wrdev, iclass 17, count 2 2006.285.06:19:37.92#ibcon#first serial, iclass 17, count 2 2006.285.06:19:37.92#ibcon#enter sib2, iclass 17, count 2 2006.285.06:19:37.92#ibcon#flushed, iclass 17, count 2 2006.285.06:19:37.92#ibcon#about to write, iclass 17, count 2 2006.285.06:19:37.92#ibcon#wrote, iclass 17, count 2 2006.285.06:19:37.92#ibcon#about to read 3, iclass 17, count 2 2006.285.06:19:37.94#ibcon#read 3, iclass 17, count 2 2006.285.06:19:37.94#ibcon#about to read 4, iclass 17, count 2 2006.285.06:19:37.94#ibcon#read 4, iclass 17, count 2 2006.285.06:19:37.94#ibcon#about to read 5, iclass 17, count 2 2006.285.06:19:37.94#ibcon#read 5, iclass 17, count 2 2006.285.06:19:37.94#ibcon#about to read 6, iclass 17, count 2 2006.285.06:19:37.94#ibcon#read 6, iclass 17, count 2 2006.285.06:19:37.94#ibcon#end of sib2, iclass 17, count 2 2006.285.06:19:37.94#ibcon#*mode == 0, iclass 17, count 2 2006.285.06:19:37.94#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.06:19:37.94#ibcon#[27=AT02-05\r\n] 2006.285.06:19:37.94#ibcon#*before write, iclass 17, count 2 2006.285.06:19:37.94#ibcon#enter sib2, iclass 17, count 2 2006.285.06:19:37.94#ibcon#flushed, iclass 17, count 2 2006.285.06:19:37.94#ibcon#about to write, iclass 17, count 2 2006.285.06:19:37.94#ibcon#wrote, iclass 17, count 2 2006.285.06:19:37.94#ibcon#about to read 3, iclass 17, count 2 2006.285.06:19:37.97#ibcon#read 3, iclass 17, count 2 2006.285.06:19:37.97#ibcon#about to read 4, iclass 17, count 2 2006.285.06:19:37.97#ibcon#read 4, iclass 17, count 2 2006.285.06:19:37.97#ibcon#about to read 5, iclass 17, count 2 2006.285.06:19:37.97#ibcon#read 5, iclass 17, count 2 2006.285.06:19:37.97#ibcon#about to read 6, iclass 17, count 2 2006.285.06:19:37.97#ibcon#read 6, iclass 17, count 2 2006.285.06:19:37.97#ibcon#end of sib2, iclass 17, count 2 2006.285.06:19:37.97#ibcon#*after write, iclass 17, count 2 2006.285.06:19:37.97#ibcon#*before return 0, iclass 17, count 2 2006.285.06:19:37.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:19:37.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:19:37.97#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.06:19:37.97#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:37.97#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:19:38.09#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:19:38.09#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:19:38.09#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:19:38.09#ibcon#first serial, iclass 17, count 0 2006.285.06:19:38.09#ibcon#enter sib2, iclass 17, count 0 2006.285.06:19:38.09#ibcon#flushed, iclass 17, count 0 2006.285.06:19:38.09#ibcon#about to write, iclass 17, count 0 2006.285.06:19:38.09#ibcon#wrote, iclass 17, count 0 2006.285.06:19:38.09#ibcon#about to read 3, iclass 17, count 0 2006.285.06:19:38.11#ibcon#read 3, iclass 17, count 0 2006.285.06:19:38.11#ibcon#about to read 4, iclass 17, count 0 2006.285.06:19:38.11#ibcon#read 4, iclass 17, count 0 2006.285.06:19:38.11#ibcon#about to read 5, iclass 17, count 0 2006.285.06:19:38.11#ibcon#read 5, iclass 17, count 0 2006.285.06:19:38.11#ibcon#about to read 6, iclass 17, count 0 2006.285.06:19:38.11#ibcon#read 6, iclass 17, count 0 2006.285.06:19:38.11#ibcon#end of sib2, iclass 17, count 0 2006.285.06:19:38.11#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:19:38.11#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:19:38.11#ibcon#[27=USB\r\n] 2006.285.06:19:38.11#ibcon#*before write, iclass 17, count 0 2006.285.06:19:38.11#ibcon#enter sib2, iclass 17, count 0 2006.285.06:19:38.11#ibcon#flushed, iclass 17, count 0 2006.285.06:19:38.11#ibcon#about to write, iclass 17, count 0 2006.285.06:19:38.11#ibcon#wrote, iclass 17, count 0 2006.285.06:19:38.11#ibcon#about to read 3, iclass 17, count 0 2006.285.06:19:38.14#ibcon#read 3, iclass 17, count 0 2006.285.06:19:38.14#ibcon#about to read 4, iclass 17, count 0 2006.285.06:19:38.14#ibcon#read 4, iclass 17, count 0 2006.285.06:19:38.14#ibcon#about to read 5, iclass 17, count 0 2006.285.06:19:38.14#ibcon#read 5, iclass 17, count 0 2006.285.06:19:38.14#ibcon#about to read 6, iclass 17, count 0 2006.285.06:19:38.14#ibcon#read 6, iclass 17, count 0 2006.285.06:19:38.14#ibcon#end of sib2, iclass 17, count 0 2006.285.06:19:38.14#ibcon#*after write, iclass 17, count 0 2006.285.06:19:38.14#ibcon#*before return 0, iclass 17, count 0 2006.285.06:19:38.14#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:19:38.14#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:19:38.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:19:38.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:19:38.14$vck44/vblo=3,649.99 2006.285.06:19:38.14#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.06:19:38.14#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.06:19:38.14#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:38.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:19:38.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:19:38.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:19:38.14#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:19:38.14#ibcon#first serial, iclass 19, count 0 2006.285.06:19:38.14#ibcon#enter sib2, iclass 19, count 0 2006.285.06:19:38.14#ibcon#flushed, iclass 19, count 0 2006.285.06:19:38.14#ibcon#about to write, iclass 19, count 0 2006.285.06:19:38.14#ibcon#wrote, iclass 19, count 0 2006.285.06:19:38.14#ibcon#about to read 3, iclass 19, count 0 2006.285.06:19:38.16#ibcon#read 3, iclass 19, count 0 2006.285.06:19:38.16#ibcon#about to read 4, iclass 19, count 0 2006.285.06:19:38.16#ibcon#read 4, iclass 19, count 0 2006.285.06:19:38.16#ibcon#about to read 5, iclass 19, count 0 2006.285.06:19:38.16#ibcon#read 5, iclass 19, count 0 2006.285.06:19:38.16#ibcon#about to read 6, iclass 19, count 0 2006.285.06:19:38.16#ibcon#read 6, iclass 19, count 0 2006.285.06:19:38.16#ibcon#end of sib2, iclass 19, count 0 2006.285.06:19:38.16#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:19:38.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:19:38.16#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:19:38.16#ibcon#*before write, iclass 19, count 0 2006.285.06:19:38.16#ibcon#enter sib2, iclass 19, count 0 2006.285.06:19:38.16#ibcon#flushed, iclass 19, count 0 2006.285.06:19:38.16#ibcon#about to write, iclass 19, count 0 2006.285.06:19:38.16#ibcon#wrote, iclass 19, count 0 2006.285.06:19:38.16#ibcon#about to read 3, iclass 19, count 0 2006.285.06:19:38.20#ibcon#read 3, iclass 19, count 0 2006.285.06:19:38.20#ibcon#about to read 4, iclass 19, count 0 2006.285.06:19:38.20#ibcon#read 4, iclass 19, count 0 2006.285.06:19:38.20#ibcon#about to read 5, iclass 19, count 0 2006.285.06:19:38.20#ibcon#read 5, iclass 19, count 0 2006.285.06:19:38.20#ibcon#about to read 6, iclass 19, count 0 2006.285.06:19:38.20#ibcon#read 6, iclass 19, count 0 2006.285.06:19:38.20#ibcon#end of sib2, iclass 19, count 0 2006.285.06:19:38.20#ibcon#*after write, iclass 19, count 0 2006.285.06:19:38.20#ibcon#*before return 0, iclass 19, count 0 2006.285.06:19:38.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:19:38.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:19:38.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:19:38.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:19:38.20$vck44/vb=3,4 2006.285.06:19:38.20#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.06:19:38.20#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.06:19:38.20#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:38.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:19:38.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:19:38.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:19:38.26#ibcon#enter wrdev, iclass 21, count 2 2006.285.06:19:38.26#ibcon#first serial, iclass 21, count 2 2006.285.06:19:38.26#ibcon#enter sib2, iclass 21, count 2 2006.285.06:19:38.26#ibcon#flushed, iclass 21, count 2 2006.285.06:19:38.26#ibcon#about to write, iclass 21, count 2 2006.285.06:19:38.26#ibcon#wrote, iclass 21, count 2 2006.285.06:19:38.26#ibcon#about to read 3, iclass 21, count 2 2006.285.06:19:38.28#ibcon#read 3, iclass 21, count 2 2006.285.06:19:38.28#ibcon#about to read 4, iclass 21, count 2 2006.285.06:19:38.28#ibcon#read 4, iclass 21, count 2 2006.285.06:19:38.28#ibcon#about to read 5, iclass 21, count 2 2006.285.06:19:38.28#ibcon#read 5, iclass 21, count 2 2006.285.06:19:38.28#ibcon#about to read 6, iclass 21, count 2 2006.285.06:19:38.28#ibcon#read 6, iclass 21, count 2 2006.285.06:19:38.28#ibcon#end of sib2, iclass 21, count 2 2006.285.06:19:38.28#ibcon#*mode == 0, iclass 21, count 2 2006.285.06:19:38.28#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.06:19:38.28#ibcon#[27=AT03-04\r\n] 2006.285.06:19:38.28#ibcon#*before write, iclass 21, count 2 2006.285.06:19:38.28#ibcon#enter sib2, iclass 21, count 2 2006.285.06:19:38.28#ibcon#flushed, iclass 21, count 2 2006.285.06:19:38.28#ibcon#about to write, iclass 21, count 2 2006.285.06:19:38.28#ibcon#wrote, iclass 21, count 2 2006.285.06:19:38.28#ibcon#about to read 3, iclass 21, count 2 2006.285.06:19:38.31#ibcon#read 3, iclass 21, count 2 2006.285.06:19:38.31#ibcon#about to read 4, iclass 21, count 2 2006.285.06:19:38.31#ibcon#read 4, iclass 21, count 2 2006.285.06:19:38.31#ibcon#about to read 5, iclass 21, count 2 2006.285.06:19:38.31#ibcon#read 5, iclass 21, count 2 2006.285.06:19:38.31#ibcon#about to read 6, iclass 21, count 2 2006.285.06:19:38.31#ibcon#read 6, iclass 21, count 2 2006.285.06:19:38.31#ibcon#end of sib2, iclass 21, count 2 2006.285.06:19:38.31#ibcon#*after write, iclass 21, count 2 2006.285.06:19:38.31#ibcon#*before return 0, iclass 21, count 2 2006.285.06:19:38.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:19:38.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:19:38.31#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.06:19:38.31#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:38.31#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:19:38.43#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:19:38.43#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:19:38.43#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:19:38.43#ibcon#first serial, iclass 21, count 0 2006.285.06:19:38.43#ibcon#enter sib2, iclass 21, count 0 2006.285.06:19:38.43#ibcon#flushed, iclass 21, count 0 2006.285.06:19:38.43#ibcon#about to write, iclass 21, count 0 2006.285.06:19:38.43#ibcon#wrote, iclass 21, count 0 2006.285.06:19:38.43#ibcon#about to read 3, iclass 21, count 0 2006.285.06:19:38.45#ibcon#read 3, iclass 21, count 0 2006.285.06:19:38.45#ibcon#about to read 4, iclass 21, count 0 2006.285.06:19:38.45#ibcon#read 4, iclass 21, count 0 2006.285.06:19:38.45#ibcon#about to read 5, iclass 21, count 0 2006.285.06:19:38.45#ibcon#read 5, iclass 21, count 0 2006.285.06:19:38.45#ibcon#about to read 6, iclass 21, count 0 2006.285.06:19:38.45#ibcon#read 6, iclass 21, count 0 2006.285.06:19:38.45#ibcon#end of sib2, iclass 21, count 0 2006.285.06:19:38.45#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:19:38.45#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:19:38.45#ibcon#[27=USB\r\n] 2006.285.06:19:38.45#ibcon#*before write, iclass 21, count 0 2006.285.06:19:38.45#ibcon#enter sib2, iclass 21, count 0 2006.285.06:19:38.45#ibcon#flushed, iclass 21, count 0 2006.285.06:19:38.45#ibcon#about to write, iclass 21, count 0 2006.285.06:19:38.45#ibcon#wrote, iclass 21, count 0 2006.285.06:19:38.45#ibcon#about to read 3, iclass 21, count 0 2006.285.06:19:38.48#ibcon#read 3, iclass 21, count 0 2006.285.06:19:38.48#ibcon#about to read 4, iclass 21, count 0 2006.285.06:19:38.48#ibcon#read 4, iclass 21, count 0 2006.285.06:19:38.48#ibcon#about to read 5, iclass 21, count 0 2006.285.06:19:38.48#ibcon#read 5, iclass 21, count 0 2006.285.06:19:38.48#ibcon#about to read 6, iclass 21, count 0 2006.285.06:19:38.48#ibcon#read 6, iclass 21, count 0 2006.285.06:19:38.48#ibcon#end of sib2, iclass 21, count 0 2006.285.06:19:38.48#ibcon#*after write, iclass 21, count 0 2006.285.06:19:38.48#ibcon#*before return 0, iclass 21, count 0 2006.285.06:19:38.48#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:19:38.48#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:19:38.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:19:38.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:19:38.48$vck44/vblo=4,679.99 2006.285.06:19:38.48#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.06:19:38.48#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.06:19:38.48#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:38.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:19:38.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:19:38.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:19:38.48#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:19:38.48#ibcon#first serial, iclass 23, count 0 2006.285.06:19:38.48#ibcon#enter sib2, iclass 23, count 0 2006.285.06:19:38.48#ibcon#flushed, iclass 23, count 0 2006.285.06:19:38.48#ibcon#about to write, iclass 23, count 0 2006.285.06:19:38.48#ibcon#wrote, iclass 23, count 0 2006.285.06:19:38.48#ibcon#about to read 3, iclass 23, count 0 2006.285.06:19:38.50#ibcon#read 3, iclass 23, count 0 2006.285.06:19:38.50#ibcon#about to read 4, iclass 23, count 0 2006.285.06:19:38.50#ibcon#read 4, iclass 23, count 0 2006.285.06:19:38.50#ibcon#about to read 5, iclass 23, count 0 2006.285.06:19:38.50#ibcon#read 5, iclass 23, count 0 2006.285.06:19:38.50#ibcon#about to read 6, iclass 23, count 0 2006.285.06:19:38.50#ibcon#read 6, iclass 23, count 0 2006.285.06:19:38.50#ibcon#end of sib2, iclass 23, count 0 2006.285.06:19:38.50#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:19:38.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:19:38.50#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:19:38.50#ibcon#*before write, iclass 23, count 0 2006.285.06:19:38.50#ibcon#enter sib2, iclass 23, count 0 2006.285.06:19:38.50#ibcon#flushed, iclass 23, count 0 2006.285.06:19:38.50#ibcon#about to write, iclass 23, count 0 2006.285.06:19:38.50#ibcon#wrote, iclass 23, count 0 2006.285.06:19:38.50#ibcon#about to read 3, iclass 23, count 0 2006.285.06:19:38.54#ibcon#read 3, iclass 23, count 0 2006.285.06:19:38.54#ibcon#about to read 4, iclass 23, count 0 2006.285.06:19:38.54#ibcon#read 4, iclass 23, count 0 2006.285.06:19:38.54#ibcon#about to read 5, iclass 23, count 0 2006.285.06:19:38.54#ibcon#read 5, iclass 23, count 0 2006.285.06:19:38.54#ibcon#about to read 6, iclass 23, count 0 2006.285.06:19:38.54#ibcon#read 6, iclass 23, count 0 2006.285.06:19:38.54#ibcon#end of sib2, iclass 23, count 0 2006.285.06:19:38.54#ibcon#*after write, iclass 23, count 0 2006.285.06:19:38.54#ibcon#*before return 0, iclass 23, count 0 2006.285.06:19:38.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:19:38.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:19:38.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:19:38.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:19:38.54$vck44/vb=4,5 2006.285.06:19:38.54#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.06:19:38.54#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.06:19:38.54#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:38.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:19:38.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:19:38.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:19:38.60#ibcon#enter wrdev, iclass 25, count 2 2006.285.06:19:38.60#ibcon#first serial, iclass 25, count 2 2006.285.06:19:38.60#ibcon#enter sib2, iclass 25, count 2 2006.285.06:19:38.60#ibcon#flushed, iclass 25, count 2 2006.285.06:19:38.60#ibcon#about to write, iclass 25, count 2 2006.285.06:19:38.60#ibcon#wrote, iclass 25, count 2 2006.285.06:19:38.60#ibcon#about to read 3, iclass 25, count 2 2006.285.06:19:38.62#ibcon#read 3, iclass 25, count 2 2006.285.06:19:38.62#ibcon#about to read 4, iclass 25, count 2 2006.285.06:19:38.62#ibcon#read 4, iclass 25, count 2 2006.285.06:19:38.62#ibcon#about to read 5, iclass 25, count 2 2006.285.06:19:38.62#ibcon#read 5, iclass 25, count 2 2006.285.06:19:38.62#ibcon#about to read 6, iclass 25, count 2 2006.285.06:19:38.62#ibcon#read 6, iclass 25, count 2 2006.285.06:19:38.62#ibcon#end of sib2, iclass 25, count 2 2006.285.06:19:38.62#ibcon#*mode == 0, iclass 25, count 2 2006.285.06:19:38.62#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.06:19:38.62#ibcon#[27=AT04-05\r\n] 2006.285.06:19:38.62#ibcon#*before write, iclass 25, count 2 2006.285.06:19:38.62#ibcon#enter sib2, iclass 25, count 2 2006.285.06:19:38.62#ibcon#flushed, iclass 25, count 2 2006.285.06:19:38.62#ibcon#about to write, iclass 25, count 2 2006.285.06:19:38.62#ibcon#wrote, iclass 25, count 2 2006.285.06:19:38.62#ibcon#about to read 3, iclass 25, count 2 2006.285.06:19:38.65#ibcon#read 3, iclass 25, count 2 2006.285.06:19:38.65#ibcon#about to read 4, iclass 25, count 2 2006.285.06:19:38.65#ibcon#read 4, iclass 25, count 2 2006.285.06:19:38.65#ibcon#about to read 5, iclass 25, count 2 2006.285.06:19:38.65#ibcon#read 5, iclass 25, count 2 2006.285.06:19:38.65#ibcon#about to read 6, iclass 25, count 2 2006.285.06:19:38.65#ibcon#read 6, iclass 25, count 2 2006.285.06:19:38.65#ibcon#end of sib2, iclass 25, count 2 2006.285.06:19:38.65#ibcon#*after write, iclass 25, count 2 2006.285.06:19:38.65#ibcon#*before return 0, iclass 25, count 2 2006.285.06:19:38.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:19:38.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:19:38.65#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.06:19:38.65#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:38.65#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:19:38.77#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:19:38.77#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:19:38.77#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:19:38.77#ibcon#first serial, iclass 25, count 0 2006.285.06:19:38.77#ibcon#enter sib2, iclass 25, count 0 2006.285.06:19:38.77#ibcon#flushed, iclass 25, count 0 2006.285.06:19:38.77#ibcon#about to write, iclass 25, count 0 2006.285.06:19:38.77#ibcon#wrote, iclass 25, count 0 2006.285.06:19:38.77#ibcon#about to read 3, iclass 25, count 0 2006.285.06:19:38.79#ibcon#read 3, iclass 25, count 0 2006.285.06:19:38.79#ibcon#about to read 4, iclass 25, count 0 2006.285.06:19:38.79#ibcon#read 4, iclass 25, count 0 2006.285.06:19:38.79#ibcon#about to read 5, iclass 25, count 0 2006.285.06:19:38.79#ibcon#read 5, iclass 25, count 0 2006.285.06:19:38.79#ibcon#about to read 6, iclass 25, count 0 2006.285.06:19:38.79#ibcon#read 6, iclass 25, count 0 2006.285.06:19:38.79#ibcon#end of sib2, iclass 25, count 0 2006.285.06:19:38.79#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:19:38.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:19:38.79#ibcon#[27=USB\r\n] 2006.285.06:19:38.79#ibcon#*before write, iclass 25, count 0 2006.285.06:19:38.79#ibcon#enter sib2, iclass 25, count 0 2006.285.06:19:38.79#ibcon#flushed, iclass 25, count 0 2006.285.06:19:38.79#ibcon#about to write, iclass 25, count 0 2006.285.06:19:38.79#ibcon#wrote, iclass 25, count 0 2006.285.06:19:38.79#ibcon#about to read 3, iclass 25, count 0 2006.285.06:19:38.82#ibcon#read 3, iclass 25, count 0 2006.285.06:19:38.82#ibcon#about to read 4, iclass 25, count 0 2006.285.06:19:38.82#ibcon#read 4, iclass 25, count 0 2006.285.06:19:38.82#ibcon#about to read 5, iclass 25, count 0 2006.285.06:19:38.82#ibcon#read 5, iclass 25, count 0 2006.285.06:19:38.82#ibcon#about to read 6, iclass 25, count 0 2006.285.06:19:38.82#ibcon#read 6, iclass 25, count 0 2006.285.06:19:38.82#ibcon#end of sib2, iclass 25, count 0 2006.285.06:19:38.82#ibcon#*after write, iclass 25, count 0 2006.285.06:19:38.82#ibcon#*before return 0, iclass 25, count 0 2006.285.06:19:38.82#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:19:38.82#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:19:38.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:19:38.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:19:38.82$vck44/vblo=5,709.99 2006.285.06:19:38.82#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.06:19:38.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.06:19:38.82#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:38.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:19:38.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:19:38.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:19:38.82#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:19:38.82#ibcon#first serial, iclass 27, count 0 2006.285.06:19:38.82#ibcon#enter sib2, iclass 27, count 0 2006.285.06:19:38.82#ibcon#flushed, iclass 27, count 0 2006.285.06:19:38.82#ibcon#about to write, iclass 27, count 0 2006.285.06:19:38.82#ibcon#wrote, iclass 27, count 0 2006.285.06:19:38.82#ibcon#about to read 3, iclass 27, count 0 2006.285.06:19:38.84#ibcon#read 3, iclass 27, count 0 2006.285.06:19:38.84#ibcon#about to read 4, iclass 27, count 0 2006.285.06:19:38.84#ibcon#read 4, iclass 27, count 0 2006.285.06:19:38.84#ibcon#about to read 5, iclass 27, count 0 2006.285.06:19:38.84#ibcon#read 5, iclass 27, count 0 2006.285.06:19:38.84#ibcon#about to read 6, iclass 27, count 0 2006.285.06:19:38.84#ibcon#read 6, iclass 27, count 0 2006.285.06:19:38.84#ibcon#end of sib2, iclass 27, count 0 2006.285.06:19:38.84#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:19:38.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:19:38.84#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:19:38.84#ibcon#*before write, iclass 27, count 0 2006.285.06:19:38.84#ibcon#enter sib2, iclass 27, count 0 2006.285.06:19:38.84#ibcon#flushed, iclass 27, count 0 2006.285.06:19:38.84#ibcon#about to write, iclass 27, count 0 2006.285.06:19:38.84#ibcon#wrote, iclass 27, count 0 2006.285.06:19:38.84#ibcon#about to read 3, iclass 27, count 0 2006.285.06:19:38.88#ibcon#read 3, iclass 27, count 0 2006.285.06:19:38.88#ibcon#about to read 4, iclass 27, count 0 2006.285.06:19:38.88#ibcon#read 4, iclass 27, count 0 2006.285.06:19:38.88#ibcon#about to read 5, iclass 27, count 0 2006.285.06:19:38.88#ibcon#read 5, iclass 27, count 0 2006.285.06:19:38.88#ibcon#about to read 6, iclass 27, count 0 2006.285.06:19:38.88#ibcon#read 6, iclass 27, count 0 2006.285.06:19:38.88#ibcon#end of sib2, iclass 27, count 0 2006.285.06:19:38.88#ibcon#*after write, iclass 27, count 0 2006.285.06:19:38.88#ibcon#*before return 0, iclass 27, count 0 2006.285.06:19:38.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:19:38.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:19:38.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:19:38.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:19:38.88$vck44/vb=5,4 2006.285.06:19:38.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.06:19:38.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.06:19:38.88#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:38.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:19:38.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:19:38.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:19:38.94#ibcon#enter wrdev, iclass 29, count 2 2006.285.06:19:38.94#ibcon#first serial, iclass 29, count 2 2006.285.06:19:38.94#ibcon#enter sib2, iclass 29, count 2 2006.285.06:19:38.94#ibcon#flushed, iclass 29, count 2 2006.285.06:19:38.94#ibcon#about to write, iclass 29, count 2 2006.285.06:19:38.94#ibcon#wrote, iclass 29, count 2 2006.285.06:19:38.94#ibcon#about to read 3, iclass 29, count 2 2006.285.06:19:38.96#ibcon#read 3, iclass 29, count 2 2006.285.06:19:38.96#ibcon#about to read 4, iclass 29, count 2 2006.285.06:19:38.96#ibcon#read 4, iclass 29, count 2 2006.285.06:19:38.96#ibcon#about to read 5, iclass 29, count 2 2006.285.06:19:38.96#ibcon#read 5, iclass 29, count 2 2006.285.06:19:38.96#ibcon#about to read 6, iclass 29, count 2 2006.285.06:19:38.96#ibcon#read 6, iclass 29, count 2 2006.285.06:19:38.96#ibcon#end of sib2, iclass 29, count 2 2006.285.06:19:38.96#ibcon#*mode == 0, iclass 29, count 2 2006.285.06:19:38.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.06:19:38.96#ibcon#[27=AT05-04\r\n] 2006.285.06:19:38.96#ibcon#*before write, iclass 29, count 2 2006.285.06:19:38.96#ibcon#enter sib2, iclass 29, count 2 2006.285.06:19:38.96#ibcon#flushed, iclass 29, count 2 2006.285.06:19:38.96#ibcon#about to write, iclass 29, count 2 2006.285.06:19:38.96#ibcon#wrote, iclass 29, count 2 2006.285.06:19:38.96#ibcon#about to read 3, iclass 29, count 2 2006.285.06:19:38.99#ibcon#read 3, iclass 29, count 2 2006.285.06:19:38.99#ibcon#about to read 4, iclass 29, count 2 2006.285.06:19:38.99#ibcon#read 4, iclass 29, count 2 2006.285.06:19:38.99#ibcon#about to read 5, iclass 29, count 2 2006.285.06:19:38.99#ibcon#read 5, iclass 29, count 2 2006.285.06:19:38.99#ibcon#about to read 6, iclass 29, count 2 2006.285.06:19:38.99#ibcon#read 6, iclass 29, count 2 2006.285.06:19:38.99#ibcon#end of sib2, iclass 29, count 2 2006.285.06:19:38.99#ibcon#*after write, iclass 29, count 2 2006.285.06:19:38.99#ibcon#*before return 0, iclass 29, count 2 2006.285.06:19:38.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:19:38.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:19:38.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.06:19:38.99#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:38.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:19:39.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:19:39.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:19:39.11#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:19:39.11#ibcon#first serial, iclass 29, count 0 2006.285.06:19:39.11#ibcon#enter sib2, iclass 29, count 0 2006.285.06:19:39.11#ibcon#flushed, iclass 29, count 0 2006.285.06:19:39.11#ibcon#about to write, iclass 29, count 0 2006.285.06:19:39.11#ibcon#wrote, iclass 29, count 0 2006.285.06:19:39.11#ibcon#about to read 3, iclass 29, count 0 2006.285.06:19:39.13#ibcon#read 3, iclass 29, count 0 2006.285.06:19:39.13#ibcon#about to read 4, iclass 29, count 0 2006.285.06:19:39.13#ibcon#read 4, iclass 29, count 0 2006.285.06:19:39.13#ibcon#about to read 5, iclass 29, count 0 2006.285.06:19:39.13#ibcon#read 5, iclass 29, count 0 2006.285.06:19:39.13#ibcon#about to read 6, iclass 29, count 0 2006.285.06:19:39.13#ibcon#read 6, iclass 29, count 0 2006.285.06:19:39.13#ibcon#end of sib2, iclass 29, count 0 2006.285.06:19:39.13#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:19:39.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:19:39.13#ibcon#[27=USB\r\n] 2006.285.06:19:39.13#ibcon#*before write, iclass 29, count 0 2006.285.06:19:39.13#ibcon#enter sib2, iclass 29, count 0 2006.285.06:19:39.13#ibcon#flushed, iclass 29, count 0 2006.285.06:19:39.13#ibcon#about to write, iclass 29, count 0 2006.285.06:19:39.13#ibcon#wrote, iclass 29, count 0 2006.285.06:19:39.13#ibcon#about to read 3, iclass 29, count 0 2006.285.06:19:39.16#ibcon#read 3, iclass 29, count 0 2006.285.06:19:39.16#ibcon#about to read 4, iclass 29, count 0 2006.285.06:19:39.16#ibcon#read 4, iclass 29, count 0 2006.285.06:19:39.16#ibcon#about to read 5, iclass 29, count 0 2006.285.06:19:39.16#ibcon#read 5, iclass 29, count 0 2006.285.06:19:39.16#ibcon#about to read 6, iclass 29, count 0 2006.285.06:19:39.16#ibcon#read 6, iclass 29, count 0 2006.285.06:19:39.16#ibcon#end of sib2, iclass 29, count 0 2006.285.06:19:39.16#ibcon#*after write, iclass 29, count 0 2006.285.06:19:39.16#ibcon#*before return 0, iclass 29, count 0 2006.285.06:19:39.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:19:39.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:19:39.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:19:39.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:19:39.16$vck44/vblo=6,719.99 2006.285.06:19:39.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.06:19:39.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.06:19:39.16#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:39.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:19:39.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:19:39.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:19:39.16#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:19:39.16#ibcon#first serial, iclass 31, count 0 2006.285.06:19:39.16#ibcon#enter sib2, iclass 31, count 0 2006.285.06:19:39.16#ibcon#flushed, iclass 31, count 0 2006.285.06:19:39.16#ibcon#about to write, iclass 31, count 0 2006.285.06:19:39.16#ibcon#wrote, iclass 31, count 0 2006.285.06:19:39.16#ibcon#about to read 3, iclass 31, count 0 2006.285.06:19:39.18#ibcon#read 3, iclass 31, count 0 2006.285.06:19:39.18#ibcon#about to read 4, iclass 31, count 0 2006.285.06:19:39.18#ibcon#read 4, iclass 31, count 0 2006.285.06:19:39.18#ibcon#about to read 5, iclass 31, count 0 2006.285.06:19:39.18#ibcon#read 5, iclass 31, count 0 2006.285.06:19:39.18#ibcon#about to read 6, iclass 31, count 0 2006.285.06:19:39.18#ibcon#read 6, iclass 31, count 0 2006.285.06:19:39.18#ibcon#end of sib2, iclass 31, count 0 2006.285.06:19:39.18#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:19:39.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:19:39.18#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:19:39.18#ibcon#*before write, iclass 31, count 0 2006.285.06:19:39.18#ibcon#enter sib2, iclass 31, count 0 2006.285.06:19:39.18#ibcon#flushed, iclass 31, count 0 2006.285.06:19:39.18#ibcon#about to write, iclass 31, count 0 2006.285.06:19:39.18#ibcon#wrote, iclass 31, count 0 2006.285.06:19:39.18#ibcon#about to read 3, iclass 31, count 0 2006.285.06:19:39.22#ibcon#read 3, iclass 31, count 0 2006.285.06:19:39.22#ibcon#about to read 4, iclass 31, count 0 2006.285.06:19:39.22#ibcon#read 4, iclass 31, count 0 2006.285.06:19:39.22#ibcon#about to read 5, iclass 31, count 0 2006.285.06:19:39.22#ibcon#read 5, iclass 31, count 0 2006.285.06:19:39.22#ibcon#about to read 6, iclass 31, count 0 2006.285.06:19:39.22#ibcon#read 6, iclass 31, count 0 2006.285.06:19:39.22#ibcon#end of sib2, iclass 31, count 0 2006.285.06:19:39.22#ibcon#*after write, iclass 31, count 0 2006.285.06:19:39.22#ibcon#*before return 0, iclass 31, count 0 2006.285.06:19:39.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:19:39.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:19:39.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:19:39.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:19:39.22$vck44/vb=6,3 2006.285.06:19:39.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.06:19:39.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.06:19:39.22#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:39.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:19:39.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:19:39.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:19:39.28#ibcon#enter wrdev, iclass 33, count 2 2006.285.06:19:39.28#ibcon#first serial, iclass 33, count 2 2006.285.06:19:39.28#ibcon#enter sib2, iclass 33, count 2 2006.285.06:19:39.28#ibcon#flushed, iclass 33, count 2 2006.285.06:19:39.28#ibcon#about to write, iclass 33, count 2 2006.285.06:19:39.28#ibcon#wrote, iclass 33, count 2 2006.285.06:19:39.28#ibcon#about to read 3, iclass 33, count 2 2006.285.06:19:39.30#ibcon#read 3, iclass 33, count 2 2006.285.06:19:39.30#ibcon#about to read 4, iclass 33, count 2 2006.285.06:19:39.30#ibcon#read 4, iclass 33, count 2 2006.285.06:19:39.30#ibcon#about to read 5, iclass 33, count 2 2006.285.06:19:39.30#ibcon#read 5, iclass 33, count 2 2006.285.06:19:39.30#ibcon#about to read 6, iclass 33, count 2 2006.285.06:19:39.30#ibcon#read 6, iclass 33, count 2 2006.285.06:19:39.30#ibcon#end of sib2, iclass 33, count 2 2006.285.06:19:39.30#ibcon#*mode == 0, iclass 33, count 2 2006.285.06:19:39.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.06:19:39.30#ibcon#[27=AT06-03\r\n] 2006.285.06:19:39.30#ibcon#*before write, iclass 33, count 2 2006.285.06:19:39.30#ibcon#enter sib2, iclass 33, count 2 2006.285.06:19:39.30#ibcon#flushed, iclass 33, count 2 2006.285.06:19:39.30#ibcon#about to write, iclass 33, count 2 2006.285.06:19:39.30#ibcon#wrote, iclass 33, count 2 2006.285.06:19:39.30#ibcon#about to read 3, iclass 33, count 2 2006.285.06:19:39.33#ibcon#read 3, iclass 33, count 2 2006.285.06:19:39.33#ibcon#about to read 4, iclass 33, count 2 2006.285.06:19:39.33#ibcon#read 4, iclass 33, count 2 2006.285.06:19:39.33#ibcon#about to read 5, iclass 33, count 2 2006.285.06:19:39.33#ibcon#read 5, iclass 33, count 2 2006.285.06:19:39.33#ibcon#about to read 6, iclass 33, count 2 2006.285.06:19:39.33#ibcon#read 6, iclass 33, count 2 2006.285.06:19:39.33#ibcon#end of sib2, iclass 33, count 2 2006.285.06:19:39.33#ibcon#*after write, iclass 33, count 2 2006.285.06:19:39.33#ibcon#*before return 0, iclass 33, count 2 2006.285.06:19:39.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:19:39.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:19:39.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.06:19:39.33#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:39.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:19:39.42#abcon#<5=/05 4.5 7.1 24.98 691014.0\r\n> 2006.285.06:19:39.44#abcon#{5=INTERFACE CLEAR} 2006.285.06:19:39.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:19:39.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:19:39.45#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:19:39.45#ibcon#first serial, iclass 33, count 0 2006.285.06:19:39.45#ibcon#enter sib2, iclass 33, count 0 2006.285.06:19:39.45#ibcon#flushed, iclass 33, count 0 2006.285.06:19:39.45#ibcon#about to write, iclass 33, count 0 2006.285.06:19:39.45#ibcon#wrote, iclass 33, count 0 2006.285.06:19:39.45#ibcon#about to read 3, iclass 33, count 0 2006.285.06:19:39.47#ibcon#read 3, iclass 33, count 0 2006.285.06:19:39.47#ibcon#about to read 4, iclass 33, count 0 2006.285.06:19:39.47#ibcon#read 4, iclass 33, count 0 2006.285.06:19:39.47#ibcon#about to read 5, iclass 33, count 0 2006.285.06:19:39.47#ibcon#read 5, iclass 33, count 0 2006.285.06:19:39.47#ibcon#about to read 6, iclass 33, count 0 2006.285.06:19:39.47#ibcon#read 6, iclass 33, count 0 2006.285.06:19:39.47#ibcon#end of sib2, iclass 33, count 0 2006.285.06:19:39.47#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:19:39.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:19:39.47#ibcon#[27=USB\r\n] 2006.285.06:19:39.47#ibcon#*before write, iclass 33, count 0 2006.285.06:19:39.47#ibcon#enter sib2, iclass 33, count 0 2006.285.06:19:39.47#ibcon#flushed, iclass 33, count 0 2006.285.06:19:39.47#ibcon#about to write, iclass 33, count 0 2006.285.06:19:39.47#ibcon#wrote, iclass 33, count 0 2006.285.06:19:39.47#ibcon#about to read 3, iclass 33, count 0 2006.285.06:19:39.50#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:19:39.50#ibcon#read 3, iclass 33, count 0 2006.285.06:19:39.50#ibcon#about to read 4, iclass 33, count 0 2006.285.06:19:39.50#ibcon#read 4, iclass 33, count 0 2006.285.06:19:39.50#ibcon#about to read 5, iclass 33, count 0 2006.285.06:19:39.50#ibcon#read 5, iclass 33, count 0 2006.285.06:19:39.50#ibcon#about to read 6, iclass 33, count 0 2006.285.06:19:39.50#ibcon#read 6, iclass 33, count 0 2006.285.06:19:39.50#ibcon#end of sib2, iclass 33, count 0 2006.285.06:19:39.50#ibcon#*after write, iclass 33, count 0 2006.285.06:19:39.50#ibcon#*before return 0, iclass 33, count 0 2006.285.06:19:39.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:19:39.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:19:39.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:19:39.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:19:39.50$vck44/vblo=7,734.99 2006.285.06:19:39.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.06:19:39.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.06:19:39.50#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:39.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:19:39.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:19:39.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:19:39.50#ibcon#enter wrdev, iclass 39, count 0 2006.285.06:19:39.50#ibcon#first serial, iclass 39, count 0 2006.285.06:19:39.50#ibcon#enter sib2, iclass 39, count 0 2006.285.06:19:39.50#ibcon#flushed, iclass 39, count 0 2006.285.06:19:39.50#ibcon#about to write, iclass 39, count 0 2006.285.06:19:39.50#ibcon#wrote, iclass 39, count 0 2006.285.06:19:39.50#ibcon#about to read 3, iclass 39, count 0 2006.285.06:19:39.52#ibcon#read 3, iclass 39, count 0 2006.285.06:19:39.52#ibcon#about to read 4, iclass 39, count 0 2006.285.06:19:39.52#ibcon#read 4, iclass 39, count 0 2006.285.06:19:39.52#ibcon#about to read 5, iclass 39, count 0 2006.285.06:19:39.52#ibcon#read 5, iclass 39, count 0 2006.285.06:19:39.52#ibcon#about to read 6, iclass 39, count 0 2006.285.06:19:39.52#ibcon#read 6, iclass 39, count 0 2006.285.06:19:39.52#ibcon#end of sib2, iclass 39, count 0 2006.285.06:19:39.52#ibcon#*mode == 0, iclass 39, count 0 2006.285.06:19:39.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.06:19:39.52#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:19:39.52#ibcon#*before write, iclass 39, count 0 2006.285.06:19:39.52#ibcon#enter sib2, iclass 39, count 0 2006.285.06:19:39.52#ibcon#flushed, iclass 39, count 0 2006.285.06:19:39.52#ibcon#about to write, iclass 39, count 0 2006.285.06:19:39.52#ibcon#wrote, iclass 39, count 0 2006.285.06:19:39.52#ibcon#about to read 3, iclass 39, count 0 2006.285.06:19:39.56#ibcon#read 3, iclass 39, count 0 2006.285.06:19:39.56#ibcon#about to read 4, iclass 39, count 0 2006.285.06:19:39.56#ibcon#read 4, iclass 39, count 0 2006.285.06:19:39.56#ibcon#about to read 5, iclass 39, count 0 2006.285.06:19:39.56#ibcon#read 5, iclass 39, count 0 2006.285.06:19:39.56#ibcon#about to read 6, iclass 39, count 0 2006.285.06:19:39.56#ibcon#read 6, iclass 39, count 0 2006.285.06:19:39.56#ibcon#end of sib2, iclass 39, count 0 2006.285.06:19:39.56#ibcon#*after write, iclass 39, count 0 2006.285.06:19:39.56#ibcon#*before return 0, iclass 39, count 0 2006.285.06:19:39.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:19:39.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:19:39.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.06:19:39.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.06:19:39.56$vck44/vb=7,4 2006.285.06:19:39.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.06:19:39.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.06:19:39.56#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:39.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:19:39.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:19:39.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:19:39.62#ibcon#enter wrdev, iclass 3, count 2 2006.285.06:19:39.62#ibcon#first serial, iclass 3, count 2 2006.285.06:19:39.62#ibcon#enter sib2, iclass 3, count 2 2006.285.06:19:39.62#ibcon#flushed, iclass 3, count 2 2006.285.06:19:39.62#ibcon#about to write, iclass 3, count 2 2006.285.06:19:39.62#ibcon#wrote, iclass 3, count 2 2006.285.06:19:39.62#ibcon#about to read 3, iclass 3, count 2 2006.285.06:19:39.64#ibcon#read 3, iclass 3, count 2 2006.285.06:19:39.64#ibcon#about to read 4, iclass 3, count 2 2006.285.06:19:39.64#ibcon#read 4, iclass 3, count 2 2006.285.06:19:39.64#ibcon#about to read 5, iclass 3, count 2 2006.285.06:19:39.64#ibcon#read 5, iclass 3, count 2 2006.285.06:19:39.64#ibcon#about to read 6, iclass 3, count 2 2006.285.06:19:39.64#ibcon#read 6, iclass 3, count 2 2006.285.06:19:39.64#ibcon#end of sib2, iclass 3, count 2 2006.285.06:19:39.64#ibcon#*mode == 0, iclass 3, count 2 2006.285.06:19:39.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.06:19:39.64#ibcon#[27=AT07-04\r\n] 2006.285.06:19:39.64#ibcon#*before write, iclass 3, count 2 2006.285.06:19:39.64#ibcon#enter sib2, iclass 3, count 2 2006.285.06:19:39.64#ibcon#flushed, iclass 3, count 2 2006.285.06:19:39.64#ibcon#about to write, iclass 3, count 2 2006.285.06:19:39.64#ibcon#wrote, iclass 3, count 2 2006.285.06:19:39.64#ibcon#about to read 3, iclass 3, count 2 2006.285.06:19:39.67#ibcon#read 3, iclass 3, count 2 2006.285.06:19:39.67#ibcon#about to read 4, iclass 3, count 2 2006.285.06:19:39.67#ibcon#read 4, iclass 3, count 2 2006.285.06:19:39.67#ibcon#about to read 5, iclass 3, count 2 2006.285.06:19:39.67#ibcon#read 5, iclass 3, count 2 2006.285.06:19:39.67#ibcon#about to read 6, iclass 3, count 2 2006.285.06:19:39.67#ibcon#read 6, iclass 3, count 2 2006.285.06:19:39.67#ibcon#end of sib2, iclass 3, count 2 2006.285.06:19:39.67#ibcon#*after write, iclass 3, count 2 2006.285.06:19:39.67#ibcon#*before return 0, iclass 3, count 2 2006.285.06:19:39.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:19:39.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:19:39.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.06:19:39.67#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:39.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:19:39.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:19:39.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:19:39.79#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:19:39.79#ibcon#first serial, iclass 3, count 0 2006.285.06:19:39.79#ibcon#enter sib2, iclass 3, count 0 2006.285.06:19:39.79#ibcon#flushed, iclass 3, count 0 2006.285.06:19:39.79#ibcon#about to write, iclass 3, count 0 2006.285.06:19:39.79#ibcon#wrote, iclass 3, count 0 2006.285.06:19:39.79#ibcon#about to read 3, iclass 3, count 0 2006.285.06:19:39.81#ibcon#read 3, iclass 3, count 0 2006.285.06:19:39.81#ibcon#about to read 4, iclass 3, count 0 2006.285.06:19:39.81#ibcon#read 4, iclass 3, count 0 2006.285.06:19:39.81#ibcon#about to read 5, iclass 3, count 0 2006.285.06:19:39.81#ibcon#read 5, iclass 3, count 0 2006.285.06:19:39.81#ibcon#about to read 6, iclass 3, count 0 2006.285.06:19:39.81#ibcon#read 6, iclass 3, count 0 2006.285.06:19:39.81#ibcon#end of sib2, iclass 3, count 0 2006.285.06:19:39.81#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:19:39.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:19:39.81#ibcon#[27=USB\r\n] 2006.285.06:19:39.81#ibcon#*before write, iclass 3, count 0 2006.285.06:19:39.81#ibcon#enter sib2, iclass 3, count 0 2006.285.06:19:39.81#ibcon#flushed, iclass 3, count 0 2006.285.06:19:39.81#ibcon#about to write, iclass 3, count 0 2006.285.06:19:39.81#ibcon#wrote, iclass 3, count 0 2006.285.06:19:39.81#ibcon#about to read 3, iclass 3, count 0 2006.285.06:19:39.84#ibcon#read 3, iclass 3, count 0 2006.285.06:19:39.84#ibcon#about to read 4, iclass 3, count 0 2006.285.06:19:39.84#ibcon#read 4, iclass 3, count 0 2006.285.06:19:39.84#ibcon#about to read 5, iclass 3, count 0 2006.285.06:19:39.84#ibcon#read 5, iclass 3, count 0 2006.285.06:19:39.84#ibcon#about to read 6, iclass 3, count 0 2006.285.06:19:39.84#ibcon#read 6, iclass 3, count 0 2006.285.06:19:39.84#ibcon#end of sib2, iclass 3, count 0 2006.285.06:19:39.84#ibcon#*after write, iclass 3, count 0 2006.285.06:19:39.84#ibcon#*before return 0, iclass 3, count 0 2006.285.06:19:39.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:19:39.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:19:39.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:19:39.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:19:39.84$vck44/vblo=8,744.99 2006.285.06:19:39.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.06:19:39.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.06:19:39.84#ibcon#ireg 17 cls_cnt 0 2006.285.06:19:39.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:19:39.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:19:39.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:19:39.84#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:19:39.84#ibcon#first serial, iclass 5, count 0 2006.285.06:19:39.84#ibcon#enter sib2, iclass 5, count 0 2006.285.06:19:39.84#ibcon#flushed, iclass 5, count 0 2006.285.06:19:39.84#ibcon#about to write, iclass 5, count 0 2006.285.06:19:39.84#ibcon#wrote, iclass 5, count 0 2006.285.06:19:39.84#ibcon#about to read 3, iclass 5, count 0 2006.285.06:19:39.86#ibcon#read 3, iclass 5, count 0 2006.285.06:19:39.86#ibcon#about to read 4, iclass 5, count 0 2006.285.06:19:39.86#ibcon#read 4, iclass 5, count 0 2006.285.06:19:39.86#ibcon#about to read 5, iclass 5, count 0 2006.285.06:19:39.86#ibcon#read 5, iclass 5, count 0 2006.285.06:19:39.86#ibcon#about to read 6, iclass 5, count 0 2006.285.06:19:39.86#ibcon#read 6, iclass 5, count 0 2006.285.06:19:39.86#ibcon#end of sib2, iclass 5, count 0 2006.285.06:19:39.86#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:19:39.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:19:39.86#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:19:39.86#ibcon#*before write, iclass 5, count 0 2006.285.06:19:39.86#ibcon#enter sib2, iclass 5, count 0 2006.285.06:19:39.86#ibcon#flushed, iclass 5, count 0 2006.285.06:19:39.86#ibcon#about to write, iclass 5, count 0 2006.285.06:19:39.86#ibcon#wrote, iclass 5, count 0 2006.285.06:19:39.86#ibcon#about to read 3, iclass 5, count 0 2006.285.06:19:39.90#ibcon#read 3, iclass 5, count 0 2006.285.06:19:39.90#ibcon#about to read 4, iclass 5, count 0 2006.285.06:19:39.90#ibcon#read 4, iclass 5, count 0 2006.285.06:19:39.90#ibcon#about to read 5, iclass 5, count 0 2006.285.06:19:39.90#ibcon#read 5, iclass 5, count 0 2006.285.06:19:39.90#ibcon#about to read 6, iclass 5, count 0 2006.285.06:19:39.90#ibcon#read 6, iclass 5, count 0 2006.285.06:19:39.90#ibcon#end of sib2, iclass 5, count 0 2006.285.06:19:39.90#ibcon#*after write, iclass 5, count 0 2006.285.06:19:39.90#ibcon#*before return 0, iclass 5, count 0 2006.285.06:19:39.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:19:39.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:19:39.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:19:39.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:19:39.90$vck44/vb=8,4 2006.285.06:19:39.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.06:19:39.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.06:19:39.90#ibcon#ireg 11 cls_cnt 2 2006.285.06:19:39.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:19:39.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:19:39.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:19:39.96#ibcon#enter wrdev, iclass 7, count 2 2006.285.06:19:39.96#ibcon#first serial, iclass 7, count 2 2006.285.06:19:39.96#ibcon#enter sib2, iclass 7, count 2 2006.285.06:19:39.96#ibcon#flushed, iclass 7, count 2 2006.285.06:19:39.96#ibcon#about to write, iclass 7, count 2 2006.285.06:19:39.96#ibcon#wrote, iclass 7, count 2 2006.285.06:19:39.96#ibcon#about to read 3, iclass 7, count 2 2006.285.06:19:39.98#ibcon#read 3, iclass 7, count 2 2006.285.06:19:39.98#ibcon#about to read 4, iclass 7, count 2 2006.285.06:19:39.98#ibcon#read 4, iclass 7, count 2 2006.285.06:19:39.98#ibcon#about to read 5, iclass 7, count 2 2006.285.06:19:39.98#ibcon#read 5, iclass 7, count 2 2006.285.06:19:39.98#ibcon#about to read 6, iclass 7, count 2 2006.285.06:19:39.98#ibcon#read 6, iclass 7, count 2 2006.285.06:19:39.98#ibcon#end of sib2, iclass 7, count 2 2006.285.06:19:39.98#ibcon#*mode == 0, iclass 7, count 2 2006.285.06:19:39.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.06:19:39.98#ibcon#[27=AT08-04\r\n] 2006.285.06:19:39.98#ibcon#*before write, iclass 7, count 2 2006.285.06:19:39.98#ibcon#enter sib2, iclass 7, count 2 2006.285.06:19:39.98#ibcon#flushed, iclass 7, count 2 2006.285.06:19:39.98#ibcon#about to write, iclass 7, count 2 2006.285.06:19:39.98#ibcon#wrote, iclass 7, count 2 2006.285.06:19:39.98#ibcon#about to read 3, iclass 7, count 2 2006.285.06:19:40.01#ibcon#read 3, iclass 7, count 2 2006.285.06:19:40.01#ibcon#about to read 4, iclass 7, count 2 2006.285.06:19:40.01#ibcon#read 4, iclass 7, count 2 2006.285.06:19:40.01#ibcon#about to read 5, iclass 7, count 2 2006.285.06:19:40.01#ibcon#read 5, iclass 7, count 2 2006.285.06:19:40.01#ibcon#about to read 6, iclass 7, count 2 2006.285.06:19:40.01#ibcon#read 6, iclass 7, count 2 2006.285.06:19:40.01#ibcon#end of sib2, iclass 7, count 2 2006.285.06:19:40.01#ibcon#*after write, iclass 7, count 2 2006.285.06:19:40.01#ibcon#*before return 0, iclass 7, count 2 2006.285.06:19:40.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:19:40.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:19:40.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.06:19:40.01#ibcon#ireg 7 cls_cnt 0 2006.285.06:19:40.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:19:40.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:19:40.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:19:40.13#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:19:40.13#ibcon#first serial, iclass 7, count 0 2006.285.06:19:40.13#ibcon#enter sib2, iclass 7, count 0 2006.285.06:19:40.13#ibcon#flushed, iclass 7, count 0 2006.285.06:19:40.13#ibcon#about to write, iclass 7, count 0 2006.285.06:19:40.13#ibcon#wrote, iclass 7, count 0 2006.285.06:19:40.13#ibcon#about to read 3, iclass 7, count 0 2006.285.06:19:40.15#ibcon#read 3, iclass 7, count 0 2006.285.06:19:40.15#ibcon#about to read 4, iclass 7, count 0 2006.285.06:19:40.15#ibcon#read 4, iclass 7, count 0 2006.285.06:19:40.15#ibcon#about to read 5, iclass 7, count 0 2006.285.06:19:40.15#ibcon#read 5, iclass 7, count 0 2006.285.06:19:40.15#ibcon#about to read 6, iclass 7, count 0 2006.285.06:19:40.15#ibcon#read 6, iclass 7, count 0 2006.285.06:19:40.15#ibcon#end of sib2, iclass 7, count 0 2006.285.06:19:40.15#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:19:40.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:19:40.15#ibcon#[27=USB\r\n] 2006.285.06:19:40.15#ibcon#*before write, iclass 7, count 0 2006.285.06:19:40.15#ibcon#enter sib2, iclass 7, count 0 2006.285.06:19:40.15#ibcon#flushed, iclass 7, count 0 2006.285.06:19:40.15#ibcon#about to write, iclass 7, count 0 2006.285.06:19:40.15#ibcon#wrote, iclass 7, count 0 2006.285.06:19:40.15#ibcon#about to read 3, iclass 7, count 0 2006.285.06:19:40.18#ibcon#read 3, iclass 7, count 0 2006.285.06:19:40.18#ibcon#about to read 4, iclass 7, count 0 2006.285.06:19:40.18#ibcon#read 4, iclass 7, count 0 2006.285.06:19:40.18#ibcon#about to read 5, iclass 7, count 0 2006.285.06:19:40.18#ibcon#read 5, iclass 7, count 0 2006.285.06:19:40.18#ibcon#about to read 6, iclass 7, count 0 2006.285.06:19:40.18#ibcon#read 6, iclass 7, count 0 2006.285.06:19:40.18#ibcon#end of sib2, iclass 7, count 0 2006.285.06:19:40.18#ibcon#*after write, iclass 7, count 0 2006.285.06:19:40.18#ibcon#*before return 0, iclass 7, count 0 2006.285.06:19:40.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:19:40.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:19:40.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:19:40.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:19:40.18$vck44/vabw=wide 2006.285.06:19:40.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.06:19:40.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.06:19:40.18#ibcon#ireg 8 cls_cnt 0 2006.285.06:19:40.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:19:40.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:19:40.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:19:40.18#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:19:40.18#ibcon#first serial, iclass 11, count 0 2006.285.06:19:40.18#ibcon#enter sib2, iclass 11, count 0 2006.285.06:19:40.18#ibcon#flushed, iclass 11, count 0 2006.285.06:19:40.18#ibcon#about to write, iclass 11, count 0 2006.285.06:19:40.18#ibcon#wrote, iclass 11, count 0 2006.285.06:19:40.18#ibcon#about to read 3, iclass 11, count 0 2006.285.06:19:40.20#ibcon#read 3, iclass 11, count 0 2006.285.06:19:40.20#ibcon#about to read 4, iclass 11, count 0 2006.285.06:19:40.20#ibcon#read 4, iclass 11, count 0 2006.285.06:19:40.20#ibcon#about to read 5, iclass 11, count 0 2006.285.06:19:40.20#ibcon#read 5, iclass 11, count 0 2006.285.06:19:40.20#ibcon#about to read 6, iclass 11, count 0 2006.285.06:19:40.20#ibcon#read 6, iclass 11, count 0 2006.285.06:19:40.20#ibcon#end of sib2, iclass 11, count 0 2006.285.06:19:40.20#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:19:40.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:19:40.20#ibcon#[25=BW32\r\n] 2006.285.06:19:40.20#ibcon#*before write, iclass 11, count 0 2006.285.06:19:40.20#ibcon#enter sib2, iclass 11, count 0 2006.285.06:19:40.20#ibcon#flushed, iclass 11, count 0 2006.285.06:19:40.20#ibcon#about to write, iclass 11, count 0 2006.285.06:19:40.20#ibcon#wrote, iclass 11, count 0 2006.285.06:19:40.20#ibcon#about to read 3, iclass 11, count 0 2006.285.06:19:40.23#ibcon#read 3, iclass 11, count 0 2006.285.06:19:40.23#ibcon#about to read 4, iclass 11, count 0 2006.285.06:19:40.23#ibcon#read 4, iclass 11, count 0 2006.285.06:19:40.23#ibcon#about to read 5, iclass 11, count 0 2006.285.06:19:40.23#ibcon#read 5, iclass 11, count 0 2006.285.06:19:40.23#ibcon#about to read 6, iclass 11, count 0 2006.285.06:19:40.23#ibcon#read 6, iclass 11, count 0 2006.285.06:19:40.23#ibcon#end of sib2, iclass 11, count 0 2006.285.06:19:40.23#ibcon#*after write, iclass 11, count 0 2006.285.06:19:40.23#ibcon#*before return 0, iclass 11, count 0 2006.285.06:19:40.23#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:19:40.23#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:19:40.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:19:40.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:19:40.23$vck44/vbbw=wide 2006.285.06:19:40.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.06:19:40.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.06:19:40.23#ibcon#ireg 8 cls_cnt 0 2006.285.06:19:40.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:19:40.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:19:40.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:19:40.30#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:19:40.30#ibcon#first serial, iclass 13, count 0 2006.285.06:19:40.30#ibcon#enter sib2, iclass 13, count 0 2006.285.06:19:40.30#ibcon#flushed, iclass 13, count 0 2006.285.06:19:40.30#ibcon#about to write, iclass 13, count 0 2006.285.06:19:40.30#ibcon#wrote, iclass 13, count 0 2006.285.06:19:40.30#ibcon#about to read 3, iclass 13, count 0 2006.285.06:19:40.32#ibcon#read 3, iclass 13, count 0 2006.285.06:19:40.32#ibcon#about to read 4, iclass 13, count 0 2006.285.06:19:40.32#ibcon#read 4, iclass 13, count 0 2006.285.06:19:40.32#ibcon#about to read 5, iclass 13, count 0 2006.285.06:19:40.32#ibcon#read 5, iclass 13, count 0 2006.285.06:19:40.32#ibcon#about to read 6, iclass 13, count 0 2006.285.06:19:40.32#ibcon#read 6, iclass 13, count 0 2006.285.06:19:40.32#ibcon#end of sib2, iclass 13, count 0 2006.285.06:19:40.32#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:19:40.32#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:19:40.32#ibcon#[27=BW32\r\n] 2006.285.06:19:40.32#ibcon#*before write, iclass 13, count 0 2006.285.06:19:40.32#ibcon#enter sib2, iclass 13, count 0 2006.285.06:19:40.32#ibcon#flushed, iclass 13, count 0 2006.285.06:19:40.32#ibcon#about to write, iclass 13, count 0 2006.285.06:19:40.32#ibcon#wrote, iclass 13, count 0 2006.285.06:19:40.32#ibcon#about to read 3, iclass 13, count 0 2006.285.06:19:40.35#ibcon#read 3, iclass 13, count 0 2006.285.06:19:40.35#ibcon#about to read 4, iclass 13, count 0 2006.285.06:19:40.35#ibcon#read 4, iclass 13, count 0 2006.285.06:19:40.35#ibcon#about to read 5, iclass 13, count 0 2006.285.06:19:40.35#ibcon#read 5, iclass 13, count 0 2006.285.06:19:40.35#ibcon#about to read 6, iclass 13, count 0 2006.285.06:19:40.35#ibcon#read 6, iclass 13, count 0 2006.285.06:19:40.35#ibcon#end of sib2, iclass 13, count 0 2006.285.06:19:40.35#ibcon#*after write, iclass 13, count 0 2006.285.06:19:40.35#ibcon#*before return 0, iclass 13, count 0 2006.285.06:19:40.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:19:40.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:19:40.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:19:40.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:19:40.35$setupk4/ifdk4 2006.285.06:19:40.35$ifdk4/lo= 2006.285.06:19:40.35$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:19:40.35$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:19:40.35$ifdk4/patch= 2006.285.06:19:40.35$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:19:40.35$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:19:40.35$setupk4/!*+20s 2006.285.06:19:47.14#trakl#Source acquired 2006.285.06:19:47.14#flagr#flagr/antenna,acquired 2006.285.06:19:49.59#abcon#<5=/05 4.5 7.1 24.98 701014.0\r\n> 2006.285.06:19:49.61#abcon#{5=INTERFACE CLEAR} 2006.285.06:19:49.67#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:19:54.85$setupk4/"tpicd 2006.285.06:19:54.85$setupk4/echo=off 2006.285.06:19:54.85$setupk4/xlog=off 2006.285.06:19:54.85:!2006.285.06:20:08 2006.285.06:20:08.00:preob 2006.285.06:20:09.14/onsource/TRACKING 2006.285.06:20:09.14:!2006.285.06:20:18 2006.285.06:20:18.00:"tape 2006.285.06:20:18.00:"st=record 2006.285.06:20:18.00:data_valid=on 2006.285.06:20:18.00:midob 2006.285.06:20:18.14/onsource/TRACKING 2006.285.06:20:18.14/wx/24.98,1014.0,69 2006.285.06:20:18.27/cable/+6.4749E-03 2006.285.06:20:19.36/va/01,07,usb,yes,32,35 2006.285.06:20:19.36/va/02,06,usb,yes,32,33 2006.285.06:20:19.36/va/03,07,usb,yes,32,34 2006.285.06:20:19.36/va/04,06,usb,yes,33,35 2006.285.06:20:19.36/va/05,03,usb,yes,33,33 2006.285.06:20:19.36/va/06,04,usb,yes,30,29 2006.285.06:20:19.36/va/07,04,usb,yes,30,31 2006.285.06:20:19.36/va/08,03,usb,yes,31,38 2006.285.06:20:19.59/valo/01,524.99,yes,locked 2006.285.06:20:19.59/valo/02,534.99,yes,locked 2006.285.06:20:19.59/valo/03,564.99,yes,locked 2006.285.06:20:19.59/valo/04,624.99,yes,locked 2006.285.06:20:19.59/valo/05,734.99,yes,locked 2006.285.06:20:19.59/valo/06,814.99,yes,locked 2006.285.06:20:19.59/valo/07,864.99,yes,locked 2006.285.06:20:19.59/valo/08,884.99,yes,locked 2006.285.06:20:20.68/vb/01,04,usb,yes,31,29 2006.285.06:20:20.68/vb/02,05,usb,yes,29,29 2006.285.06:20:20.68/vb/03,04,usb,yes,30,33 2006.285.06:20:20.68/vb/04,05,usb,yes,30,29 2006.285.06:20:20.68/vb/05,04,usb,yes,27,29 2006.285.06:20:20.68/vb/06,03,usb,yes,39,34 2006.285.06:20:20.68/vb/07,04,usb,yes,31,31 2006.285.06:20:20.68/vb/08,04,usb,yes,28,32 2006.285.06:20:20.92/vblo/01,629.99,yes,locked 2006.285.06:20:20.92/vblo/02,634.99,yes,locked 2006.285.06:20:20.92/vblo/03,649.99,yes,locked 2006.285.06:20:20.92/vblo/04,679.99,yes,locked 2006.285.06:20:20.92/vblo/05,709.99,yes,locked 2006.285.06:20:20.92/vblo/06,719.99,yes,locked 2006.285.06:20:20.92/vblo/07,734.99,yes,locked 2006.285.06:20:20.92/vblo/08,744.99,yes,locked 2006.285.06:20:21.07/vabw/8 2006.285.06:20:21.22/vbbw/8 2006.285.06:20:21.31/xfe/off,on,12.2 2006.285.06:20:21.70/ifatt/23,28,28,28 2006.285.06:20:22.08/fmout-gps/S +2.53E-07 2006.285.06:20:22.10:!2006.285.06:23:48 2006.285.06:23:48.01:data_valid=off 2006.285.06:23:48.01:"et 2006.285.06:23:48.01:!+3s 2006.285.06:23:51.02:"tape 2006.285.06:23:51.02:postob 2006.285.06:23:51.10/cable/+6.4734E-03 2006.285.06:23:51.10/wx/24.96,1014.0,70 2006.285.06:23:52.08/fmout-gps/S +2.51E-07 2006.285.06:23:52.08:scan_name=285-0627,jd0610,130 2006.285.06:23:52.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.285.06:23:52.13#flagr#flagr/antenna,new-source 2006.285.06:23:53.13:checkk5 2006.285.06:23:53.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:23:53.86/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:23:54.28/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:23:54.66/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:23:55.03/chk_obsdata//k5ts1/T2850620??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.285.06:23:55.41/chk_obsdata//k5ts2/T2850620??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.285.06:23:55.77/chk_obsdata//k5ts3/T2850620??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.285.06:23:56.28/chk_obsdata//k5ts4/T2850620??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.285.06:23:56.99/k5log//k5ts1_log_newline 2006.285.06:23:57.76/k5log//k5ts2_log_newline 2006.285.06:23:58.55/k5log//k5ts3_log_newline 2006.285.06:23:59.30/k5log//k5ts4_log_newline 2006.285.06:23:59.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:23:59.32:setupk4=1 2006.285.06:23:59.32$setupk4/echo=on 2006.285.06:23:59.32$setupk4/pcalon 2006.285.06:23:59.32$pcalon/"no phase cal control is implemented here 2006.285.06:23:59.32$setupk4/"tpicd=stop 2006.285.06:23:59.32$setupk4/"rec=synch_on 2006.285.06:23:59.32$setupk4/"rec_mode=128 2006.285.06:23:59.32$setupk4/!* 2006.285.06:23:59.32$setupk4/recpk4 2006.285.06:23:59.32$recpk4/recpatch= 2006.285.06:23:59.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:23:59.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:23:59.32$setupk4/vck44 2006.285.06:23:59.32$vck44/valo=1,524.99 2006.285.06:23:59.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.06:23:59.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.06:23:59.32#ibcon#ireg 17 cls_cnt 0 2006.285.06:23:59.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:23:59.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:23:59.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:23:59.32#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:23:59.32#ibcon#first serial, iclass 10, count 0 2006.285.06:23:59.32#ibcon#enter sib2, iclass 10, count 0 2006.285.06:23:59.32#ibcon#flushed, iclass 10, count 0 2006.285.06:23:59.32#ibcon#about to write, iclass 10, count 0 2006.285.06:23:59.32#ibcon#wrote, iclass 10, count 0 2006.285.06:23:59.32#ibcon#about to read 3, iclass 10, count 0 2006.285.06:23:59.34#ibcon#read 3, iclass 10, count 0 2006.285.06:23:59.34#ibcon#about to read 4, iclass 10, count 0 2006.285.06:23:59.34#ibcon#read 4, iclass 10, count 0 2006.285.06:23:59.34#ibcon#about to read 5, iclass 10, count 0 2006.285.06:23:59.34#ibcon#read 5, iclass 10, count 0 2006.285.06:23:59.34#ibcon#about to read 6, iclass 10, count 0 2006.285.06:23:59.34#ibcon#read 6, iclass 10, count 0 2006.285.06:23:59.34#ibcon#end of sib2, iclass 10, count 0 2006.285.06:23:59.34#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:23:59.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:23:59.34#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:23:59.34#ibcon#*before write, iclass 10, count 0 2006.285.06:23:59.34#ibcon#enter sib2, iclass 10, count 0 2006.285.06:23:59.34#ibcon#flushed, iclass 10, count 0 2006.285.06:23:59.34#ibcon#about to write, iclass 10, count 0 2006.285.06:23:59.34#ibcon#wrote, iclass 10, count 0 2006.285.06:23:59.34#ibcon#about to read 3, iclass 10, count 0 2006.285.06:23:59.39#ibcon#read 3, iclass 10, count 0 2006.285.06:23:59.39#ibcon#about to read 4, iclass 10, count 0 2006.285.06:23:59.39#ibcon#read 4, iclass 10, count 0 2006.285.06:23:59.39#ibcon#about to read 5, iclass 10, count 0 2006.285.06:23:59.39#ibcon#read 5, iclass 10, count 0 2006.285.06:23:59.39#ibcon#about to read 6, iclass 10, count 0 2006.285.06:23:59.39#ibcon#read 6, iclass 10, count 0 2006.285.06:23:59.39#ibcon#end of sib2, iclass 10, count 0 2006.285.06:23:59.39#ibcon#*after write, iclass 10, count 0 2006.285.06:23:59.39#ibcon#*before return 0, iclass 10, count 0 2006.285.06:23:59.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:23:59.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:23:59.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:23:59.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:23:59.39$vck44/va=1,7 2006.285.06:23:59.39#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.06:23:59.39#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.06:23:59.39#ibcon#ireg 11 cls_cnt 2 2006.285.06:23:59.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:23:59.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:23:59.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:23:59.39#ibcon#enter wrdev, iclass 12, count 2 2006.285.06:23:59.39#ibcon#first serial, iclass 12, count 2 2006.285.06:23:59.39#ibcon#enter sib2, iclass 12, count 2 2006.285.06:23:59.39#ibcon#flushed, iclass 12, count 2 2006.285.06:23:59.39#ibcon#about to write, iclass 12, count 2 2006.285.06:23:59.39#ibcon#wrote, iclass 12, count 2 2006.285.06:23:59.39#ibcon#about to read 3, iclass 12, count 2 2006.285.06:23:59.41#ibcon#read 3, iclass 12, count 2 2006.285.06:23:59.41#ibcon#about to read 4, iclass 12, count 2 2006.285.06:23:59.41#ibcon#read 4, iclass 12, count 2 2006.285.06:23:59.41#ibcon#about to read 5, iclass 12, count 2 2006.285.06:23:59.41#ibcon#read 5, iclass 12, count 2 2006.285.06:23:59.41#ibcon#about to read 6, iclass 12, count 2 2006.285.06:23:59.41#ibcon#read 6, iclass 12, count 2 2006.285.06:23:59.41#ibcon#end of sib2, iclass 12, count 2 2006.285.06:23:59.41#ibcon#*mode == 0, iclass 12, count 2 2006.285.06:23:59.41#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.06:23:59.41#ibcon#[25=AT01-07\r\n] 2006.285.06:23:59.41#ibcon#*before write, iclass 12, count 2 2006.285.06:23:59.41#ibcon#enter sib2, iclass 12, count 2 2006.285.06:23:59.41#ibcon#flushed, iclass 12, count 2 2006.285.06:23:59.41#ibcon#about to write, iclass 12, count 2 2006.285.06:23:59.41#ibcon#wrote, iclass 12, count 2 2006.285.06:23:59.41#ibcon#about to read 3, iclass 12, count 2 2006.285.06:23:59.44#ibcon#read 3, iclass 12, count 2 2006.285.06:23:59.44#ibcon#about to read 4, iclass 12, count 2 2006.285.06:23:59.44#ibcon#read 4, iclass 12, count 2 2006.285.06:23:59.44#ibcon#about to read 5, iclass 12, count 2 2006.285.06:23:59.44#ibcon#read 5, iclass 12, count 2 2006.285.06:23:59.44#ibcon#about to read 6, iclass 12, count 2 2006.285.06:23:59.44#ibcon#read 6, iclass 12, count 2 2006.285.06:23:59.44#ibcon#end of sib2, iclass 12, count 2 2006.285.06:23:59.44#ibcon#*after write, iclass 12, count 2 2006.285.06:23:59.44#ibcon#*before return 0, iclass 12, count 2 2006.285.06:23:59.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:23:59.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:23:59.44#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.06:23:59.44#ibcon#ireg 7 cls_cnt 0 2006.285.06:23:59.44#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:23:59.56#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:23:59.56#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:23:59.56#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:23:59.56#ibcon#first serial, iclass 12, count 0 2006.285.06:23:59.56#ibcon#enter sib2, iclass 12, count 0 2006.285.06:23:59.56#ibcon#flushed, iclass 12, count 0 2006.285.06:23:59.56#ibcon#about to write, iclass 12, count 0 2006.285.06:23:59.56#ibcon#wrote, iclass 12, count 0 2006.285.06:23:59.56#ibcon#about to read 3, iclass 12, count 0 2006.285.06:23:59.58#ibcon#read 3, iclass 12, count 0 2006.285.06:23:59.58#ibcon#about to read 4, iclass 12, count 0 2006.285.06:23:59.58#ibcon#read 4, iclass 12, count 0 2006.285.06:23:59.58#ibcon#about to read 5, iclass 12, count 0 2006.285.06:23:59.58#ibcon#read 5, iclass 12, count 0 2006.285.06:23:59.58#ibcon#about to read 6, iclass 12, count 0 2006.285.06:23:59.58#ibcon#read 6, iclass 12, count 0 2006.285.06:23:59.58#ibcon#end of sib2, iclass 12, count 0 2006.285.06:23:59.58#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:23:59.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:23:59.58#ibcon#[25=USB\r\n] 2006.285.06:23:59.58#ibcon#*before write, iclass 12, count 0 2006.285.06:23:59.58#ibcon#enter sib2, iclass 12, count 0 2006.285.06:23:59.58#ibcon#flushed, iclass 12, count 0 2006.285.06:23:59.58#ibcon#about to write, iclass 12, count 0 2006.285.06:23:59.58#ibcon#wrote, iclass 12, count 0 2006.285.06:23:59.58#ibcon#about to read 3, iclass 12, count 0 2006.285.06:23:59.61#ibcon#read 3, iclass 12, count 0 2006.285.06:23:59.61#ibcon#about to read 4, iclass 12, count 0 2006.285.06:23:59.61#ibcon#read 4, iclass 12, count 0 2006.285.06:23:59.61#ibcon#about to read 5, iclass 12, count 0 2006.285.06:23:59.61#ibcon#read 5, iclass 12, count 0 2006.285.06:23:59.61#ibcon#about to read 6, iclass 12, count 0 2006.285.06:23:59.61#ibcon#read 6, iclass 12, count 0 2006.285.06:23:59.61#ibcon#end of sib2, iclass 12, count 0 2006.285.06:23:59.61#ibcon#*after write, iclass 12, count 0 2006.285.06:23:59.61#ibcon#*before return 0, iclass 12, count 0 2006.285.06:23:59.61#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:23:59.61#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:23:59.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:23:59.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:23:59.61$vck44/valo=2,534.99 2006.285.06:23:59.61#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.06:23:59.61#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.06:23:59.61#ibcon#ireg 17 cls_cnt 0 2006.285.06:23:59.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:23:59.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:23:59.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:23:59.61#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:23:59.61#ibcon#first serial, iclass 14, count 0 2006.285.06:23:59.61#ibcon#enter sib2, iclass 14, count 0 2006.285.06:23:59.61#ibcon#flushed, iclass 14, count 0 2006.285.06:23:59.61#ibcon#about to write, iclass 14, count 0 2006.285.06:23:59.61#ibcon#wrote, iclass 14, count 0 2006.285.06:23:59.61#ibcon#about to read 3, iclass 14, count 0 2006.285.06:23:59.63#ibcon#read 3, iclass 14, count 0 2006.285.06:23:59.63#ibcon#about to read 4, iclass 14, count 0 2006.285.06:23:59.63#ibcon#read 4, iclass 14, count 0 2006.285.06:23:59.63#ibcon#about to read 5, iclass 14, count 0 2006.285.06:23:59.63#ibcon#read 5, iclass 14, count 0 2006.285.06:23:59.63#ibcon#about to read 6, iclass 14, count 0 2006.285.06:23:59.63#ibcon#read 6, iclass 14, count 0 2006.285.06:23:59.63#ibcon#end of sib2, iclass 14, count 0 2006.285.06:23:59.63#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:23:59.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:23:59.63#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:23:59.63#ibcon#*before write, iclass 14, count 0 2006.285.06:23:59.63#ibcon#enter sib2, iclass 14, count 0 2006.285.06:23:59.63#ibcon#flushed, iclass 14, count 0 2006.285.06:23:59.63#ibcon#about to write, iclass 14, count 0 2006.285.06:23:59.63#ibcon#wrote, iclass 14, count 0 2006.285.06:23:59.63#ibcon#about to read 3, iclass 14, count 0 2006.285.06:23:59.67#ibcon#read 3, iclass 14, count 0 2006.285.06:23:59.67#ibcon#about to read 4, iclass 14, count 0 2006.285.06:23:59.67#ibcon#read 4, iclass 14, count 0 2006.285.06:23:59.67#ibcon#about to read 5, iclass 14, count 0 2006.285.06:23:59.67#ibcon#read 5, iclass 14, count 0 2006.285.06:23:59.67#ibcon#about to read 6, iclass 14, count 0 2006.285.06:23:59.67#ibcon#read 6, iclass 14, count 0 2006.285.06:23:59.67#ibcon#end of sib2, iclass 14, count 0 2006.285.06:23:59.67#ibcon#*after write, iclass 14, count 0 2006.285.06:23:59.67#ibcon#*before return 0, iclass 14, count 0 2006.285.06:23:59.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:23:59.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:23:59.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:23:59.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:23:59.67$vck44/va=2,6 2006.285.06:23:59.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.06:23:59.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.06:23:59.67#ibcon#ireg 11 cls_cnt 2 2006.285.06:23:59.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:23:59.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:23:59.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:23:59.73#ibcon#enter wrdev, iclass 16, count 2 2006.285.06:23:59.73#ibcon#first serial, iclass 16, count 2 2006.285.06:23:59.73#ibcon#enter sib2, iclass 16, count 2 2006.285.06:23:59.73#ibcon#flushed, iclass 16, count 2 2006.285.06:23:59.73#ibcon#about to write, iclass 16, count 2 2006.285.06:23:59.73#ibcon#wrote, iclass 16, count 2 2006.285.06:23:59.73#ibcon#about to read 3, iclass 16, count 2 2006.285.06:23:59.75#ibcon#read 3, iclass 16, count 2 2006.285.06:23:59.75#ibcon#about to read 4, iclass 16, count 2 2006.285.06:23:59.75#ibcon#read 4, iclass 16, count 2 2006.285.06:23:59.75#ibcon#about to read 5, iclass 16, count 2 2006.285.06:23:59.75#ibcon#read 5, iclass 16, count 2 2006.285.06:23:59.75#ibcon#about to read 6, iclass 16, count 2 2006.285.06:23:59.75#ibcon#read 6, iclass 16, count 2 2006.285.06:23:59.75#ibcon#end of sib2, iclass 16, count 2 2006.285.06:23:59.75#ibcon#*mode == 0, iclass 16, count 2 2006.285.06:23:59.75#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.06:23:59.75#ibcon#[25=AT02-06\r\n] 2006.285.06:23:59.75#ibcon#*before write, iclass 16, count 2 2006.285.06:23:59.75#ibcon#enter sib2, iclass 16, count 2 2006.285.06:23:59.75#ibcon#flushed, iclass 16, count 2 2006.285.06:23:59.75#ibcon#about to write, iclass 16, count 2 2006.285.06:23:59.75#ibcon#wrote, iclass 16, count 2 2006.285.06:23:59.75#ibcon#about to read 3, iclass 16, count 2 2006.285.06:23:59.78#ibcon#read 3, iclass 16, count 2 2006.285.06:23:59.78#ibcon#about to read 4, iclass 16, count 2 2006.285.06:23:59.78#ibcon#read 4, iclass 16, count 2 2006.285.06:23:59.78#ibcon#about to read 5, iclass 16, count 2 2006.285.06:23:59.78#ibcon#read 5, iclass 16, count 2 2006.285.06:23:59.78#ibcon#about to read 6, iclass 16, count 2 2006.285.06:23:59.78#ibcon#read 6, iclass 16, count 2 2006.285.06:23:59.78#ibcon#end of sib2, iclass 16, count 2 2006.285.06:23:59.78#ibcon#*after write, iclass 16, count 2 2006.285.06:23:59.78#ibcon#*before return 0, iclass 16, count 2 2006.285.06:23:59.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:23:59.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:23:59.78#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.06:23:59.78#ibcon#ireg 7 cls_cnt 0 2006.285.06:23:59.78#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:23:59.90#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:23:59.90#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:23:59.90#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:23:59.90#ibcon#first serial, iclass 16, count 0 2006.285.06:23:59.90#ibcon#enter sib2, iclass 16, count 0 2006.285.06:23:59.90#ibcon#flushed, iclass 16, count 0 2006.285.06:23:59.90#ibcon#about to write, iclass 16, count 0 2006.285.06:23:59.90#ibcon#wrote, iclass 16, count 0 2006.285.06:23:59.90#ibcon#about to read 3, iclass 16, count 0 2006.285.06:23:59.92#ibcon#read 3, iclass 16, count 0 2006.285.06:23:59.92#ibcon#about to read 4, iclass 16, count 0 2006.285.06:23:59.92#ibcon#read 4, iclass 16, count 0 2006.285.06:23:59.92#ibcon#about to read 5, iclass 16, count 0 2006.285.06:23:59.92#ibcon#read 5, iclass 16, count 0 2006.285.06:23:59.92#ibcon#about to read 6, iclass 16, count 0 2006.285.06:23:59.92#ibcon#read 6, iclass 16, count 0 2006.285.06:23:59.92#ibcon#end of sib2, iclass 16, count 0 2006.285.06:23:59.92#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:23:59.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:23:59.92#ibcon#[25=USB\r\n] 2006.285.06:23:59.92#ibcon#*before write, iclass 16, count 0 2006.285.06:23:59.92#ibcon#enter sib2, iclass 16, count 0 2006.285.06:23:59.92#ibcon#flushed, iclass 16, count 0 2006.285.06:23:59.92#ibcon#about to write, iclass 16, count 0 2006.285.06:23:59.92#ibcon#wrote, iclass 16, count 0 2006.285.06:23:59.92#ibcon#about to read 3, iclass 16, count 0 2006.285.06:23:59.95#ibcon#read 3, iclass 16, count 0 2006.285.06:23:59.95#ibcon#about to read 4, iclass 16, count 0 2006.285.06:23:59.95#ibcon#read 4, iclass 16, count 0 2006.285.06:23:59.95#ibcon#about to read 5, iclass 16, count 0 2006.285.06:23:59.95#ibcon#read 5, iclass 16, count 0 2006.285.06:23:59.95#ibcon#about to read 6, iclass 16, count 0 2006.285.06:23:59.95#ibcon#read 6, iclass 16, count 0 2006.285.06:23:59.95#ibcon#end of sib2, iclass 16, count 0 2006.285.06:23:59.95#ibcon#*after write, iclass 16, count 0 2006.285.06:23:59.95#ibcon#*before return 0, iclass 16, count 0 2006.285.06:23:59.95#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:23:59.95#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:23:59.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:23:59.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:23:59.95$vck44/valo=3,564.99 2006.285.06:23:59.95#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.06:23:59.95#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.06:23:59.95#ibcon#ireg 17 cls_cnt 0 2006.285.06:23:59.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:23:59.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:23:59.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:23:59.95#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:23:59.95#ibcon#first serial, iclass 18, count 0 2006.285.06:23:59.95#ibcon#enter sib2, iclass 18, count 0 2006.285.06:23:59.95#ibcon#flushed, iclass 18, count 0 2006.285.06:23:59.95#ibcon#about to write, iclass 18, count 0 2006.285.06:23:59.95#ibcon#wrote, iclass 18, count 0 2006.285.06:23:59.95#ibcon#about to read 3, iclass 18, count 0 2006.285.06:23:59.97#ibcon#read 3, iclass 18, count 0 2006.285.06:23:59.97#ibcon#about to read 4, iclass 18, count 0 2006.285.06:23:59.97#ibcon#read 4, iclass 18, count 0 2006.285.06:23:59.97#ibcon#about to read 5, iclass 18, count 0 2006.285.06:23:59.97#ibcon#read 5, iclass 18, count 0 2006.285.06:23:59.97#ibcon#about to read 6, iclass 18, count 0 2006.285.06:23:59.97#ibcon#read 6, iclass 18, count 0 2006.285.06:23:59.97#ibcon#end of sib2, iclass 18, count 0 2006.285.06:23:59.97#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:23:59.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:23:59.97#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:23:59.97#ibcon#*before write, iclass 18, count 0 2006.285.06:23:59.97#ibcon#enter sib2, iclass 18, count 0 2006.285.06:23:59.97#ibcon#flushed, iclass 18, count 0 2006.285.06:23:59.97#ibcon#about to write, iclass 18, count 0 2006.285.06:23:59.97#ibcon#wrote, iclass 18, count 0 2006.285.06:23:59.97#ibcon#about to read 3, iclass 18, count 0 2006.285.06:24:00.01#ibcon#read 3, iclass 18, count 0 2006.285.06:24:00.01#ibcon#about to read 4, iclass 18, count 0 2006.285.06:24:00.01#ibcon#read 4, iclass 18, count 0 2006.285.06:24:00.01#ibcon#about to read 5, iclass 18, count 0 2006.285.06:24:00.01#ibcon#read 5, iclass 18, count 0 2006.285.06:24:00.01#ibcon#about to read 6, iclass 18, count 0 2006.285.06:24:00.01#ibcon#read 6, iclass 18, count 0 2006.285.06:24:00.01#ibcon#end of sib2, iclass 18, count 0 2006.285.06:24:00.01#ibcon#*after write, iclass 18, count 0 2006.285.06:24:00.01#ibcon#*before return 0, iclass 18, count 0 2006.285.06:24:00.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:24:00.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:24:00.01#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:24:00.01#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:24:00.01$vck44/va=3,7 2006.285.06:24:00.01#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.06:24:00.01#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.06:24:00.01#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:00.01#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:24:00.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:24:00.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:24:00.07#ibcon#enter wrdev, iclass 20, count 2 2006.285.06:24:00.07#ibcon#first serial, iclass 20, count 2 2006.285.06:24:00.07#ibcon#enter sib2, iclass 20, count 2 2006.285.06:24:00.07#ibcon#flushed, iclass 20, count 2 2006.285.06:24:00.07#ibcon#about to write, iclass 20, count 2 2006.285.06:24:00.07#ibcon#wrote, iclass 20, count 2 2006.285.06:24:00.07#ibcon#about to read 3, iclass 20, count 2 2006.285.06:24:00.09#ibcon#read 3, iclass 20, count 2 2006.285.06:24:00.09#ibcon#about to read 4, iclass 20, count 2 2006.285.06:24:00.09#ibcon#read 4, iclass 20, count 2 2006.285.06:24:00.09#ibcon#about to read 5, iclass 20, count 2 2006.285.06:24:00.09#ibcon#read 5, iclass 20, count 2 2006.285.06:24:00.09#ibcon#about to read 6, iclass 20, count 2 2006.285.06:24:00.09#ibcon#read 6, iclass 20, count 2 2006.285.06:24:00.09#ibcon#end of sib2, iclass 20, count 2 2006.285.06:24:00.09#ibcon#*mode == 0, iclass 20, count 2 2006.285.06:24:00.09#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.06:24:00.09#ibcon#[25=AT03-07\r\n] 2006.285.06:24:00.09#ibcon#*before write, iclass 20, count 2 2006.285.06:24:00.09#ibcon#enter sib2, iclass 20, count 2 2006.285.06:24:00.09#ibcon#flushed, iclass 20, count 2 2006.285.06:24:00.09#ibcon#about to write, iclass 20, count 2 2006.285.06:24:00.09#ibcon#wrote, iclass 20, count 2 2006.285.06:24:00.09#ibcon#about to read 3, iclass 20, count 2 2006.285.06:24:00.12#ibcon#read 3, iclass 20, count 2 2006.285.06:24:00.12#ibcon#about to read 4, iclass 20, count 2 2006.285.06:24:00.12#ibcon#read 4, iclass 20, count 2 2006.285.06:24:00.12#ibcon#about to read 5, iclass 20, count 2 2006.285.06:24:00.12#ibcon#read 5, iclass 20, count 2 2006.285.06:24:00.12#ibcon#about to read 6, iclass 20, count 2 2006.285.06:24:00.12#ibcon#read 6, iclass 20, count 2 2006.285.06:24:00.12#ibcon#end of sib2, iclass 20, count 2 2006.285.06:24:00.12#ibcon#*after write, iclass 20, count 2 2006.285.06:24:00.12#ibcon#*before return 0, iclass 20, count 2 2006.285.06:24:00.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:24:00.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:24:00.12#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.06:24:00.12#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:00.12#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:24:00.24#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:24:00.24#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:24:00.24#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:24:00.24#ibcon#first serial, iclass 20, count 0 2006.285.06:24:00.24#ibcon#enter sib2, iclass 20, count 0 2006.285.06:24:00.24#ibcon#flushed, iclass 20, count 0 2006.285.06:24:00.24#ibcon#about to write, iclass 20, count 0 2006.285.06:24:00.24#ibcon#wrote, iclass 20, count 0 2006.285.06:24:00.24#ibcon#about to read 3, iclass 20, count 0 2006.285.06:24:00.27#ibcon#read 3, iclass 20, count 0 2006.285.06:24:00.27#ibcon#about to read 4, iclass 20, count 0 2006.285.06:24:00.27#ibcon#read 4, iclass 20, count 0 2006.285.06:24:00.27#ibcon#about to read 5, iclass 20, count 0 2006.285.06:24:00.27#ibcon#read 5, iclass 20, count 0 2006.285.06:24:00.27#ibcon#about to read 6, iclass 20, count 0 2006.285.06:24:00.27#ibcon#read 6, iclass 20, count 0 2006.285.06:24:00.27#ibcon#end of sib2, iclass 20, count 0 2006.285.06:24:00.27#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:24:00.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:24:00.27#ibcon#[25=USB\r\n] 2006.285.06:24:00.27#ibcon#*before write, iclass 20, count 0 2006.285.06:24:00.27#ibcon#enter sib2, iclass 20, count 0 2006.285.06:24:00.27#ibcon#flushed, iclass 20, count 0 2006.285.06:24:00.27#ibcon#about to write, iclass 20, count 0 2006.285.06:24:00.27#ibcon#wrote, iclass 20, count 0 2006.285.06:24:00.27#ibcon#about to read 3, iclass 20, count 0 2006.285.06:24:00.30#ibcon#read 3, iclass 20, count 0 2006.285.06:24:00.30#ibcon#about to read 4, iclass 20, count 0 2006.285.06:24:00.30#ibcon#read 4, iclass 20, count 0 2006.285.06:24:00.30#ibcon#about to read 5, iclass 20, count 0 2006.285.06:24:00.30#ibcon#read 5, iclass 20, count 0 2006.285.06:24:00.30#ibcon#about to read 6, iclass 20, count 0 2006.285.06:24:00.30#ibcon#read 6, iclass 20, count 0 2006.285.06:24:00.30#ibcon#end of sib2, iclass 20, count 0 2006.285.06:24:00.30#ibcon#*after write, iclass 20, count 0 2006.285.06:24:00.30#ibcon#*before return 0, iclass 20, count 0 2006.285.06:24:00.30#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:24:00.30#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:24:00.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:24:00.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:24:00.30$vck44/valo=4,624.99 2006.285.06:24:00.30#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.06:24:00.30#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.06:24:00.30#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:00.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:24:00.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:24:00.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:24:00.30#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:24:00.30#ibcon#first serial, iclass 22, count 0 2006.285.06:24:00.30#ibcon#enter sib2, iclass 22, count 0 2006.285.06:24:00.30#ibcon#flushed, iclass 22, count 0 2006.285.06:24:00.30#ibcon#about to write, iclass 22, count 0 2006.285.06:24:00.30#ibcon#wrote, iclass 22, count 0 2006.285.06:24:00.30#ibcon#about to read 3, iclass 22, count 0 2006.285.06:24:00.32#ibcon#read 3, iclass 22, count 0 2006.285.06:24:00.32#ibcon#about to read 4, iclass 22, count 0 2006.285.06:24:00.32#ibcon#read 4, iclass 22, count 0 2006.285.06:24:00.32#ibcon#about to read 5, iclass 22, count 0 2006.285.06:24:00.32#ibcon#read 5, iclass 22, count 0 2006.285.06:24:00.32#ibcon#about to read 6, iclass 22, count 0 2006.285.06:24:00.32#ibcon#read 6, iclass 22, count 0 2006.285.06:24:00.32#ibcon#end of sib2, iclass 22, count 0 2006.285.06:24:00.32#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:24:00.32#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:24:00.32#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:24:00.32#ibcon#*before write, iclass 22, count 0 2006.285.06:24:00.32#ibcon#enter sib2, iclass 22, count 0 2006.285.06:24:00.32#ibcon#flushed, iclass 22, count 0 2006.285.06:24:00.32#ibcon#about to write, iclass 22, count 0 2006.285.06:24:00.32#ibcon#wrote, iclass 22, count 0 2006.285.06:24:00.32#ibcon#about to read 3, iclass 22, count 0 2006.285.06:24:00.36#ibcon#read 3, iclass 22, count 0 2006.285.06:24:00.36#ibcon#about to read 4, iclass 22, count 0 2006.285.06:24:00.36#ibcon#read 4, iclass 22, count 0 2006.285.06:24:00.36#ibcon#about to read 5, iclass 22, count 0 2006.285.06:24:00.36#ibcon#read 5, iclass 22, count 0 2006.285.06:24:00.36#ibcon#about to read 6, iclass 22, count 0 2006.285.06:24:00.36#ibcon#read 6, iclass 22, count 0 2006.285.06:24:00.36#ibcon#end of sib2, iclass 22, count 0 2006.285.06:24:00.36#ibcon#*after write, iclass 22, count 0 2006.285.06:24:00.36#ibcon#*before return 0, iclass 22, count 0 2006.285.06:24:00.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:24:00.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:24:00.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:24:00.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:24:00.36$vck44/va=4,6 2006.285.06:24:00.36#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.06:24:00.36#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.06:24:00.36#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:00.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:24:00.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:24:00.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:24:00.42#ibcon#enter wrdev, iclass 24, count 2 2006.285.06:24:00.42#ibcon#first serial, iclass 24, count 2 2006.285.06:24:00.42#ibcon#enter sib2, iclass 24, count 2 2006.285.06:24:00.42#ibcon#flushed, iclass 24, count 2 2006.285.06:24:00.42#ibcon#about to write, iclass 24, count 2 2006.285.06:24:00.42#ibcon#wrote, iclass 24, count 2 2006.285.06:24:00.42#ibcon#about to read 3, iclass 24, count 2 2006.285.06:24:00.44#ibcon#read 3, iclass 24, count 2 2006.285.06:24:00.44#ibcon#about to read 4, iclass 24, count 2 2006.285.06:24:00.44#ibcon#read 4, iclass 24, count 2 2006.285.06:24:00.44#ibcon#about to read 5, iclass 24, count 2 2006.285.06:24:00.44#ibcon#read 5, iclass 24, count 2 2006.285.06:24:00.44#ibcon#about to read 6, iclass 24, count 2 2006.285.06:24:00.44#ibcon#read 6, iclass 24, count 2 2006.285.06:24:00.44#ibcon#end of sib2, iclass 24, count 2 2006.285.06:24:00.44#ibcon#*mode == 0, iclass 24, count 2 2006.285.06:24:00.44#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.06:24:00.44#ibcon#[25=AT04-06\r\n] 2006.285.06:24:00.44#ibcon#*before write, iclass 24, count 2 2006.285.06:24:00.44#ibcon#enter sib2, iclass 24, count 2 2006.285.06:24:00.44#ibcon#flushed, iclass 24, count 2 2006.285.06:24:00.44#ibcon#about to write, iclass 24, count 2 2006.285.06:24:00.44#ibcon#wrote, iclass 24, count 2 2006.285.06:24:00.44#ibcon#about to read 3, iclass 24, count 2 2006.285.06:24:00.47#ibcon#read 3, iclass 24, count 2 2006.285.06:24:00.47#ibcon#about to read 4, iclass 24, count 2 2006.285.06:24:00.47#ibcon#read 4, iclass 24, count 2 2006.285.06:24:00.47#ibcon#about to read 5, iclass 24, count 2 2006.285.06:24:00.47#ibcon#read 5, iclass 24, count 2 2006.285.06:24:00.47#ibcon#about to read 6, iclass 24, count 2 2006.285.06:24:00.47#ibcon#read 6, iclass 24, count 2 2006.285.06:24:00.47#ibcon#end of sib2, iclass 24, count 2 2006.285.06:24:00.47#ibcon#*after write, iclass 24, count 2 2006.285.06:24:00.47#ibcon#*before return 0, iclass 24, count 2 2006.285.06:24:00.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:24:00.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:24:00.47#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.06:24:00.47#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:00.47#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:24:00.59#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:24:00.59#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:24:00.59#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:24:00.59#ibcon#first serial, iclass 24, count 0 2006.285.06:24:00.59#ibcon#enter sib2, iclass 24, count 0 2006.285.06:24:00.59#ibcon#flushed, iclass 24, count 0 2006.285.06:24:00.59#ibcon#about to write, iclass 24, count 0 2006.285.06:24:00.59#ibcon#wrote, iclass 24, count 0 2006.285.06:24:00.59#ibcon#about to read 3, iclass 24, count 0 2006.285.06:24:00.61#ibcon#read 3, iclass 24, count 0 2006.285.06:24:00.61#ibcon#about to read 4, iclass 24, count 0 2006.285.06:24:00.61#ibcon#read 4, iclass 24, count 0 2006.285.06:24:00.61#ibcon#about to read 5, iclass 24, count 0 2006.285.06:24:00.61#ibcon#read 5, iclass 24, count 0 2006.285.06:24:00.61#ibcon#about to read 6, iclass 24, count 0 2006.285.06:24:00.61#ibcon#read 6, iclass 24, count 0 2006.285.06:24:00.61#ibcon#end of sib2, iclass 24, count 0 2006.285.06:24:00.61#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:24:00.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:24:00.61#ibcon#[25=USB\r\n] 2006.285.06:24:00.61#ibcon#*before write, iclass 24, count 0 2006.285.06:24:00.61#ibcon#enter sib2, iclass 24, count 0 2006.285.06:24:00.61#ibcon#flushed, iclass 24, count 0 2006.285.06:24:00.61#ibcon#about to write, iclass 24, count 0 2006.285.06:24:00.61#ibcon#wrote, iclass 24, count 0 2006.285.06:24:00.61#ibcon#about to read 3, iclass 24, count 0 2006.285.06:24:00.64#ibcon#read 3, iclass 24, count 0 2006.285.06:24:00.64#ibcon#about to read 4, iclass 24, count 0 2006.285.06:24:00.64#ibcon#read 4, iclass 24, count 0 2006.285.06:24:00.64#ibcon#about to read 5, iclass 24, count 0 2006.285.06:24:00.64#ibcon#read 5, iclass 24, count 0 2006.285.06:24:00.64#ibcon#about to read 6, iclass 24, count 0 2006.285.06:24:00.64#ibcon#read 6, iclass 24, count 0 2006.285.06:24:00.64#ibcon#end of sib2, iclass 24, count 0 2006.285.06:24:00.64#ibcon#*after write, iclass 24, count 0 2006.285.06:24:00.64#ibcon#*before return 0, iclass 24, count 0 2006.285.06:24:00.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:24:00.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:24:00.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:24:00.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:24:00.64$vck44/valo=5,734.99 2006.285.06:24:00.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.06:24:00.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.06:24:00.64#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:00.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:24:00.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:24:00.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:24:00.64#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:24:00.64#ibcon#first serial, iclass 26, count 0 2006.285.06:24:00.64#ibcon#enter sib2, iclass 26, count 0 2006.285.06:24:00.64#ibcon#flushed, iclass 26, count 0 2006.285.06:24:00.64#ibcon#about to write, iclass 26, count 0 2006.285.06:24:00.64#ibcon#wrote, iclass 26, count 0 2006.285.06:24:00.64#ibcon#about to read 3, iclass 26, count 0 2006.285.06:24:00.66#ibcon#read 3, iclass 26, count 0 2006.285.06:24:00.66#ibcon#about to read 4, iclass 26, count 0 2006.285.06:24:00.66#ibcon#read 4, iclass 26, count 0 2006.285.06:24:00.66#ibcon#about to read 5, iclass 26, count 0 2006.285.06:24:00.66#ibcon#read 5, iclass 26, count 0 2006.285.06:24:00.66#ibcon#about to read 6, iclass 26, count 0 2006.285.06:24:00.66#ibcon#read 6, iclass 26, count 0 2006.285.06:24:00.66#ibcon#end of sib2, iclass 26, count 0 2006.285.06:24:00.66#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:24:00.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:24:00.66#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:24:00.66#ibcon#*before write, iclass 26, count 0 2006.285.06:24:00.66#ibcon#enter sib2, iclass 26, count 0 2006.285.06:24:00.66#ibcon#flushed, iclass 26, count 0 2006.285.06:24:00.66#ibcon#about to write, iclass 26, count 0 2006.285.06:24:00.66#ibcon#wrote, iclass 26, count 0 2006.285.06:24:00.66#ibcon#about to read 3, iclass 26, count 0 2006.285.06:24:00.70#ibcon#read 3, iclass 26, count 0 2006.285.06:24:00.70#ibcon#about to read 4, iclass 26, count 0 2006.285.06:24:00.70#ibcon#read 4, iclass 26, count 0 2006.285.06:24:00.70#ibcon#about to read 5, iclass 26, count 0 2006.285.06:24:00.70#ibcon#read 5, iclass 26, count 0 2006.285.06:24:00.70#ibcon#about to read 6, iclass 26, count 0 2006.285.06:24:00.70#ibcon#read 6, iclass 26, count 0 2006.285.06:24:00.70#ibcon#end of sib2, iclass 26, count 0 2006.285.06:24:00.70#ibcon#*after write, iclass 26, count 0 2006.285.06:24:00.70#ibcon#*before return 0, iclass 26, count 0 2006.285.06:24:00.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:24:00.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:24:00.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:24:00.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:24:00.70$vck44/va=5,3 2006.285.06:24:00.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.06:24:00.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.06:24:00.70#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:00.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:24:00.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:24:00.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:24:00.76#ibcon#enter wrdev, iclass 28, count 2 2006.285.06:24:00.76#ibcon#first serial, iclass 28, count 2 2006.285.06:24:00.76#ibcon#enter sib2, iclass 28, count 2 2006.285.06:24:00.76#ibcon#flushed, iclass 28, count 2 2006.285.06:24:00.76#ibcon#about to write, iclass 28, count 2 2006.285.06:24:00.76#ibcon#wrote, iclass 28, count 2 2006.285.06:24:00.76#ibcon#about to read 3, iclass 28, count 2 2006.285.06:24:00.78#ibcon#read 3, iclass 28, count 2 2006.285.06:24:00.78#ibcon#about to read 4, iclass 28, count 2 2006.285.06:24:00.78#ibcon#read 4, iclass 28, count 2 2006.285.06:24:00.78#ibcon#about to read 5, iclass 28, count 2 2006.285.06:24:00.78#ibcon#read 5, iclass 28, count 2 2006.285.06:24:00.78#ibcon#about to read 6, iclass 28, count 2 2006.285.06:24:00.78#ibcon#read 6, iclass 28, count 2 2006.285.06:24:00.78#ibcon#end of sib2, iclass 28, count 2 2006.285.06:24:00.78#ibcon#*mode == 0, iclass 28, count 2 2006.285.06:24:00.78#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.06:24:00.78#ibcon#[25=AT05-03\r\n] 2006.285.06:24:00.78#ibcon#*before write, iclass 28, count 2 2006.285.06:24:00.78#ibcon#enter sib2, iclass 28, count 2 2006.285.06:24:00.78#ibcon#flushed, iclass 28, count 2 2006.285.06:24:00.78#ibcon#about to write, iclass 28, count 2 2006.285.06:24:00.78#ibcon#wrote, iclass 28, count 2 2006.285.06:24:00.78#ibcon#about to read 3, iclass 28, count 2 2006.285.06:24:00.81#ibcon#read 3, iclass 28, count 2 2006.285.06:24:00.81#ibcon#about to read 4, iclass 28, count 2 2006.285.06:24:00.81#ibcon#read 4, iclass 28, count 2 2006.285.06:24:00.81#ibcon#about to read 5, iclass 28, count 2 2006.285.06:24:00.81#ibcon#read 5, iclass 28, count 2 2006.285.06:24:00.81#ibcon#about to read 6, iclass 28, count 2 2006.285.06:24:00.81#ibcon#read 6, iclass 28, count 2 2006.285.06:24:00.81#ibcon#end of sib2, iclass 28, count 2 2006.285.06:24:00.81#ibcon#*after write, iclass 28, count 2 2006.285.06:24:00.81#ibcon#*before return 0, iclass 28, count 2 2006.285.06:24:00.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:24:00.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:24:00.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.06:24:00.81#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:00.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:24:00.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:24:00.93#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:24:00.93#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:24:00.93#ibcon#first serial, iclass 28, count 0 2006.285.06:24:00.93#ibcon#enter sib2, iclass 28, count 0 2006.285.06:24:00.93#ibcon#flushed, iclass 28, count 0 2006.285.06:24:00.93#ibcon#about to write, iclass 28, count 0 2006.285.06:24:00.93#ibcon#wrote, iclass 28, count 0 2006.285.06:24:00.93#ibcon#about to read 3, iclass 28, count 0 2006.285.06:24:00.95#ibcon#read 3, iclass 28, count 0 2006.285.06:24:00.95#ibcon#about to read 4, iclass 28, count 0 2006.285.06:24:00.95#ibcon#read 4, iclass 28, count 0 2006.285.06:24:00.95#ibcon#about to read 5, iclass 28, count 0 2006.285.06:24:00.95#ibcon#read 5, iclass 28, count 0 2006.285.06:24:00.95#ibcon#about to read 6, iclass 28, count 0 2006.285.06:24:00.95#ibcon#read 6, iclass 28, count 0 2006.285.06:24:00.95#ibcon#end of sib2, iclass 28, count 0 2006.285.06:24:00.95#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:24:00.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:24:00.95#ibcon#[25=USB\r\n] 2006.285.06:24:00.95#ibcon#*before write, iclass 28, count 0 2006.285.06:24:00.95#ibcon#enter sib2, iclass 28, count 0 2006.285.06:24:00.95#ibcon#flushed, iclass 28, count 0 2006.285.06:24:00.95#ibcon#about to write, iclass 28, count 0 2006.285.06:24:00.95#ibcon#wrote, iclass 28, count 0 2006.285.06:24:00.95#ibcon#about to read 3, iclass 28, count 0 2006.285.06:24:00.98#ibcon#read 3, iclass 28, count 0 2006.285.06:24:00.98#ibcon#about to read 4, iclass 28, count 0 2006.285.06:24:00.98#ibcon#read 4, iclass 28, count 0 2006.285.06:24:00.98#ibcon#about to read 5, iclass 28, count 0 2006.285.06:24:00.98#ibcon#read 5, iclass 28, count 0 2006.285.06:24:00.98#ibcon#about to read 6, iclass 28, count 0 2006.285.06:24:00.98#ibcon#read 6, iclass 28, count 0 2006.285.06:24:00.98#ibcon#end of sib2, iclass 28, count 0 2006.285.06:24:00.98#ibcon#*after write, iclass 28, count 0 2006.285.06:24:00.98#ibcon#*before return 0, iclass 28, count 0 2006.285.06:24:00.98#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:24:00.98#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:24:00.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:24:00.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:24:00.98$vck44/valo=6,814.99 2006.285.06:24:00.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.06:24:00.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.06:24:00.98#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:00.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:24:00.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:24:00.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:24:00.98#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:24:00.98#ibcon#first serial, iclass 30, count 0 2006.285.06:24:00.98#ibcon#enter sib2, iclass 30, count 0 2006.285.06:24:00.98#ibcon#flushed, iclass 30, count 0 2006.285.06:24:00.98#ibcon#about to write, iclass 30, count 0 2006.285.06:24:00.98#ibcon#wrote, iclass 30, count 0 2006.285.06:24:00.98#ibcon#about to read 3, iclass 30, count 0 2006.285.06:24:01.00#ibcon#read 3, iclass 30, count 0 2006.285.06:24:01.00#ibcon#about to read 4, iclass 30, count 0 2006.285.06:24:01.00#ibcon#read 4, iclass 30, count 0 2006.285.06:24:01.00#ibcon#about to read 5, iclass 30, count 0 2006.285.06:24:01.00#ibcon#read 5, iclass 30, count 0 2006.285.06:24:01.00#ibcon#about to read 6, iclass 30, count 0 2006.285.06:24:01.00#ibcon#read 6, iclass 30, count 0 2006.285.06:24:01.00#ibcon#end of sib2, iclass 30, count 0 2006.285.06:24:01.00#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:24:01.00#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:24:01.00#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:24:01.00#ibcon#*before write, iclass 30, count 0 2006.285.06:24:01.00#ibcon#enter sib2, iclass 30, count 0 2006.285.06:24:01.00#ibcon#flushed, iclass 30, count 0 2006.285.06:24:01.00#ibcon#about to write, iclass 30, count 0 2006.285.06:24:01.00#ibcon#wrote, iclass 30, count 0 2006.285.06:24:01.00#ibcon#about to read 3, iclass 30, count 0 2006.285.06:24:01.04#ibcon#read 3, iclass 30, count 0 2006.285.06:24:01.04#ibcon#about to read 4, iclass 30, count 0 2006.285.06:24:01.04#ibcon#read 4, iclass 30, count 0 2006.285.06:24:01.04#ibcon#about to read 5, iclass 30, count 0 2006.285.06:24:01.04#ibcon#read 5, iclass 30, count 0 2006.285.06:24:01.04#ibcon#about to read 6, iclass 30, count 0 2006.285.06:24:01.04#ibcon#read 6, iclass 30, count 0 2006.285.06:24:01.04#ibcon#end of sib2, iclass 30, count 0 2006.285.06:24:01.04#ibcon#*after write, iclass 30, count 0 2006.285.06:24:01.04#ibcon#*before return 0, iclass 30, count 0 2006.285.06:24:01.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:24:01.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:24:01.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:24:01.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:24:01.04$vck44/va=6,4 2006.285.06:24:01.04#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.06:24:01.04#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.06:24:01.04#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:01.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:24:01.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:24:01.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:24:01.10#ibcon#enter wrdev, iclass 32, count 2 2006.285.06:24:01.10#ibcon#first serial, iclass 32, count 2 2006.285.06:24:01.10#ibcon#enter sib2, iclass 32, count 2 2006.285.06:24:01.10#ibcon#flushed, iclass 32, count 2 2006.285.06:24:01.10#ibcon#about to write, iclass 32, count 2 2006.285.06:24:01.10#ibcon#wrote, iclass 32, count 2 2006.285.06:24:01.10#ibcon#about to read 3, iclass 32, count 2 2006.285.06:24:01.12#ibcon#read 3, iclass 32, count 2 2006.285.06:24:01.12#ibcon#about to read 4, iclass 32, count 2 2006.285.06:24:01.12#ibcon#read 4, iclass 32, count 2 2006.285.06:24:01.12#ibcon#about to read 5, iclass 32, count 2 2006.285.06:24:01.12#ibcon#read 5, iclass 32, count 2 2006.285.06:24:01.12#ibcon#about to read 6, iclass 32, count 2 2006.285.06:24:01.12#ibcon#read 6, iclass 32, count 2 2006.285.06:24:01.12#ibcon#end of sib2, iclass 32, count 2 2006.285.06:24:01.12#ibcon#*mode == 0, iclass 32, count 2 2006.285.06:24:01.12#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.06:24:01.12#ibcon#[25=AT06-04\r\n] 2006.285.06:24:01.12#ibcon#*before write, iclass 32, count 2 2006.285.06:24:01.12#ibcon#enter sib2, iclass 32, count 2 2006.285.06:24:01.12#ibcon#flushed, iclass 32, count 2 2006.285.06:24:01.12#ibcon#about to write, iclass 32, count 2 2006.285.06:24:01.12#ibcon#wrote, iclass 32, count 2 2006.285.06:24:01.12#ibcon#about to read 3, iclass 32, count 2 2006.285.06:24:01.15#ibcon#read 3, iclass 32, count 2 2006.285.06:24:01.15#ibcon#about to read 4, iclass 32, count 2 2006.285.06:24:01.15#ibcon#read 4, iclass 32, count 2 2006.285.06:24:01.15#ibcon#about to read 5, iclass 32, count 2 2006.285.06:24:01.15#ibcon#read 5, iclass 32, count 2 2006.285.06:24:01.15#ibcon#about to read 6, iclass 32, count 2 2006.285.06:24:01.15#ibcon#read 6, iclass 32, count 2 2006.285.06:24:01.15#ibcon#end of sib2, iclass 32, count 2 2006.285.06:24:01.15#ibcon#*after write, iclass 32, count 2 2006.285.06:24:01.15#ibcon#*before return 0, iclass 32, count 2 2006.285.06:24:01.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:24:01.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:24:01.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.06:24:01.15#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:01.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:24:01.27#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:24:01.27#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:24:01.27#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:24:01.27#ibcon#first serial, iclass 32, count 0 2006.285.06:24:01.27#ibcon#enter sib2, iclass 32, count 0 2006.285.06:24:01.27#ibcon#flushed, iclass 32, count 0 2006.285.06:24:01.27#ibcon#about to write, iclass 32, count 0 2006.285.06:24:01.27#ibcon#wrote, iclass 32, count 0 2006.285.06:24:01.27#ibcon#about to read 3, iclass 32, count 0 2006.285.06:24:01.29#ibcon#read 3, iclass 32, count 0 2006.285.06:24:01.29#ibcon#about to read 4, iclass 32, count 0 2006.285.06:24:01.29#ibcon#read 4, iclass 32, count 0 2006.285.06:24:01.29#ibcon#about to read 5, iclass 32, count 0 2006.285.06:24:01.29#ibcon#read 5, iclass 32, count 0 2006.285.06:24:01.29#ibcon#about to read 6, iclass 32, count 0 2006.285.06:24:01.29#ibcon#read 6, iclass 32, count 0 2006.285.06:24:01.29#ibcon#end of sib2, iclass 32, count 0 2006.285.06:24:01.29#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:24:01.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:24:01.29#ibcon#[25=USB\r\n] 2006.285.06:24:01.29#ibcon#*before write, iclass 32, count 0 2006.285.06:24:01.29#ibcon#enter sib2, iclass 32, count 0 2006.285.06:24:01.29#ibcon#flushed, iclass 32, count 0 2006.285.06:24:01.29#ibcon#about to write, iclass 32, count 0 2006.285.06:24:01.29#ibcon#wrote, iclass 32, count 0 2006.285.06:24:01.29#ibcon#about to read 3, iclass 32, count 0 2006.285.06:24:01.32#ibcon#read 3, iclass 32, count 0 2006.285.06:24:01.32#ibcon#about to read 4, iclass 32, count 0 2006.285.06:24:01.32#ibcon#read 4, iclass 32, count 0 2006.285.06:24:01.32#ibcon#about to read 5, iclass 32, count 0 2006.285.06:24:01.32#ibcon#read 5, iclass 32, count 0 2006.285.06:24:01.32#ibcon#about to read 6, iclass 32, count 0 2006.285.06:24:01.32#ibcon#read 6, iclass 32, count 0 2006.285.06:24:01.32#ibcon#end of sib2, iclass 32, count 0 2006.285.06:24:01.32#ibcon#*after write, iclass 32, count 0 2006.285.06:24:01.32#ibcon#*before return 0, iclass 32, count 0 2006.285.06:24:01.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:24:01.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:24:01.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:24:01.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:24:01.32$vck44/valo=7,864.99 2006.285.06:24:01.32#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.06:24:01.32#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.06:24:01.32#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:01.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:24:01.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:24:01.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:24:01.32#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:24:01.32#ibcon#first serial, iclass 34, count 0 2006.285.06:24:01.32#ibcon#enter sib2, iclass 34, count 0 2006.285.06:24:01.32#ibcon#flushed, iclass 34, count 0 2006.285.06:24:01.32#ibcon#about to write, iclass 34, count 0 2006.285.06:24:01.32#ibcon#wrote, iclass 34, count 0 2006.285.06:24:01.32#ibcon#about to read 3, iclass 34, count 0 2006.285.06:24:01.34#ibcon#read 3, iclass 34, count 0 2006.285.06:24:01.34#ibcon#about to read 4, iclass 34, count 0 2006.285.06:24:01.34#ibcon#read 4, iclass 34, count 0 2006.285.06:24:01.34#ibcon#about to read 5, iclass 34, count 0 2006.285.06:24:01.34#ibcon#read 5, iclass 34, count 0 2006.285.06:24:01.34#ibcon#about to read 6, iclass 34, count 0 2006.285.06:24:01.34#ibcon#read 6, iclass 34, count 0 2006.285.06:24:01.34#ibcon#end of sib2, iclass 34, count 0 2006.285.06:24:01.34#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:24:01.34#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:24:01.34#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:24:01.34#ibcon#*before write, iclass 34, count 0 2006.285.06:24:01.34#ibcon#enter sib2, iclass 34, count 0 2006.285.06:24:01.34#ibcon#flushed, iclass 34, count 0 2006.285.06:24:01.34#ibcon#about to write, iclass 34, count 0 2006.285.06:24:01.34#ibcon#wrote, iclass 34, count 0 2006.285.06:24:01.34#ibcon#about to read 3, iclass 34, count 0 2006.285.06:24:01.38#ibcon#read 3, iclass 34, count 0 2006.285.06:24:01.38#ibcon#about to read 4, iclass 34, count 0 2006.285.06:24:01.38#ibcon#read 4, iclass 34, count 0 2006.285.06:24:01.38#ibcon#about to read 5, iclass 34, count 0 2006.285.06:24:01.38#ibcon#read 5, iclass 34, count 0 2006.285.06:24:01.38#ibcon#about to read 6, iclass 34, count 0 2006.285.06:24:01.38#ibcon#read 6, iclass 34, count 0 2006.285.06:24:01.38#ibcon#end of sib2, iclass 34, count 0 2006.285.06:24:01.38#ibcon#*after write, iclass 34, count 0 2006.285.06:24:01.38#ibcon#*before return 0, iclass 34, count 0 2006.285.06:24:01.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:24:01.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:24:01.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:24:01.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:24:01.38$vck44/va=7,4 2006.285.06:24:01.38#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.06:24:01.38#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.06:24:01.38#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:01.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:24:01.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:24:01.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:24:01.44#ibcon#enter wrdev, iclass 36, count 2 2006.285.06:24:01.44#ibcon#first serial, iclass 36, count 2 2006.285.06:24:01.44#ibcon#enter sib2, iclass 36, count 2 2006.285.06:24:01.44#ibcon#flushed, iclass 36, count 2 2006.285.06:24:01.44#ibcon#about to write, iclass 36, count 2 2006.285.06:24:01.44#ibcon#wrote, iclass 36, count 2 2006.285.06:24:01.44#ibcon#about to read 3, iclass 36, count 2 2006.285.06:24:01.46#ibcon#read 3, iclass 36, count 2 2006.285.06:24:01.46#ibcon#about to read 4, iclass 36, count 2 2006.285.06:24:01.46#ibcon#read 4, iclass 36, count 2 2006.285.06:24:01.46#ibcon#about to read 5, iclass 36, count 2 2006.285.06:24:01.46#ibcon#read 5, iclass 36, count 2 2006.285.06:24:01.46#ibcon#about to read 6, iclass 36, count 2 2006.285.06:24:01.46#ibcon#read 6, iclass 36, count 2 2006.285.06:24:01.46#ibcon#end of sib2, iclass 36, count 2 2006.285.06:24:01.46#ibcon#*mode == 0, iclass 36, count 2 2006.285.06:24:01.46#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.06:24:01.46#ibcon#[25=AT07-04\r\n] 2006.285.06:24:01.46#ibcon#*before write, iclass 36, count 2 2006.285.06:24:01.46#ibcon#enter sib2, iclass 36, count 2 2006.285.06:24:01.46#ibcon#flushed, iclass 36, count 2 2006.285.06:24:01.46#ibcon#about to write, iclass 36, count 2 2006.285.06:24:01.46#ibcon#wrote, iclass 36, count 2 2006.285.06:24:01.46#ibcon#about to read 3, iclass 36, count 2 2006.285.06:24:01.49#ibcon#read 3, iclass 36, count 2 2006.285.06:24:01.49#ibcon#about to read 4, iclass 36, count 2 2006.285.06:24:01.49#ibcon#read 4, iclass 36, count 2 2006.285.06:24:01.49#ibcon#about to read 5, iclass 36, count 2 2006.285.06:24:01.49#ibcon#read 5, iclass 36, count 2 2006.285.06:24:01.49#ibcon#about to read 6, iclass 36, count 2 2006.285.06:24:01.49#ibcon#read 6, iclass 36, count 2 2006.285.06:24:01.49#ibcon#end of sib2, iclass 36, count 2 2006.285.06:24:01.49#ibcon#*after write, iclass 36, count 2 2006.285.06:24:01.49#ibcon#*before return 0, iclass 36, count 2 2006.285.06:24:01.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:24:01.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:24:01.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.06:24:01.49#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:01.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:24:01.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:24:01.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:24:01.61#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:24:01.61#ibcon#first serial, iclass 36, count 0 2006.285.06:24:01.61#ibcon#enter sib2, iclass 36, count 0 2006.285.06:24:01.61#ibcon#flushed, iclass 36, count 0 2006.285.06:24:01.61#ibcon#about to write, iclass 36, count 0 2006.285.06:24:01.61#ibcon#wrote, iclass 36, count 0 2006.285.06:24:01.61#ibcon#about to read 3, iclass 36, count 0 2006.285.06:24:01.63#ibcon#read 3, iclass 36, count 0 2006.285.06:24:01.63#ibcon#about to read 4, iclass 36, count 0 2006.285.06:24:01.63#ibcon#read 4, iclass 36, count 0 2006.285.06:24:01.63#ibcon#about to read 5, iclass 36, count 0 2006.285.06:24:01.63#ibcon#read 5, iclass 36, count 0 2006.285.06:24:01.63#ibcon#about to read 6, iclass 36, count 0 2006.285.06:24:01.63#ibcon#read 6, iclass 36, count 0 2006.285.06:24:01.63#ibcon#end of sib2, iclass 36, count 0 2006.285.06:24:01.63#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:24:01.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:24:01.63#ibcon#[25=USB\r\n] 2006.285.06:24:01.63#ibcon#*before write, iclass 36, count 0 2006.285.06:24:01.63#ibcon#enter sib2, iclass 36, count 0 2006.285.06:24:01.63#ibcon#flushed, iclass 36, count 0 2006.285.06:24:01.63#ibcon#about to write, iclass 36, count 0 2006.285.06:24:01.63#ibcon#wrote, iclass 36, count 0 2006.285.06:24:01.63#ibcon#about to read 3, iclass 36, count 0 2006.285.06:24:01.66#ibcon#read 3, iclass 36, count 0 2006.285.06:24:01.66#ibcon#about to read 4, iclass 36, count 0 2006.285.06:24:01.66#ibcon#read 4, iclass 36, count 0 2006.285.06:24:01.66#ibcon#about to read 5, iclass 36, count 0 2006.285.06:24:01.66#ibcon#read 5, iclass 36, count 0 2006.285.06:24:01.66#ibcon#about to read 6, iclass 36, count 0 2006.285.06:24:01.66#ibcon#read 6, iclass 36, count 0 2006.285.06:24:01.66#ibcon#end of sib2, iclass 36, count 0 2006.285.06:24:01.66#ibcon#*after write, iclass 36, count 0 2006.285.06:24:01.66#ibcon#*before return 0, iclass 36, count 0 2006.285.06:24:01.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:24:01.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:24:01.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:24:01.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:24:01.66$vck44/valo=8,884.99 2006.285.06:24:01.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.06:24:01.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.06:24:01.66#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:01.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:24:01.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:24:01.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:24:01.66#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:24:01.66#ibcon#first serial, iclass 38, count 0 2006.285.06:24:01.66#ibcon#enter sib2, iclass 38, count 0 2006.285.06:24:01.66#ibcon#flushed, iclass 38, count 0 2006.285.06:24:01.66#ibcon#about to write, iclass 38, count 0 2006.285.06:24:01.66#ibcon#wrote, iclass 38, count 0 2006.285.06:24:01.66#ibcon#about to read 3, iclass 38, count 0 2006.285.06:24:01.68#ibcon#read 3, iclass 38, count 0 2006.285.06:24:01.68#ibcon#about to read 4, iclass 38, count 0 2006.285.06:24:01.68#ibcon#read 4, iclass 38, count 0 2006.285.06:24:01.68#ibcon#about to read 5, iclass 38, count 0 2006.285.06:24:01.68#ibcon#read 5, iclass 38, count 0 2006.285.06:24:01.68#ibcon#about to read 6, iclass 38, count 0 2006.285.06:24:01.68#ibcon#read 6, iclass 38, count 0 2006.285.06:24:01.68#ibcon#end of sib2, iclass 38, count 0 2006.285.06:24:01.68#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:24:01.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:24:01.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:24:01.68#ibcon#*before write, iclass 38, count 0 2006.285.06:24:01.68#ibcon#enter sib2, iclass 38, count 0 2006.285.06:24:01.68#ibcon#flushed, iclass 38, count 0 2006.285.06:24:01.68#ibcon#about to write, iclass 38, count 0 2006.285.06:24:01.68#ibcon#wrote, iclass 38, count 0 2006.285.06:24:01.68#ibcon#about to read 3, iclass 38, count 0 2006.285.06:24:01.72#ibcon#read 3, iclass 38, count 0 2006.285.06:24:01.72#ibcon#about to read 4, iclass 38, count 0 2006.285.06:24:01.72#ibcon#read 4, iclass 38, count 0 2006.285.06:24:01.72#ibcon#about to read 5, iclass 38, count 0 2006.285.06:24:01.72#ibcon#read 5, iclass 38, count 0 2006.285.06:24:01.72#ibcon#about to read 6, iclass 38, count 0 2006.285.06:24:01.72#ibcon#read 6, iclass 38, count 0 2006.285.06:24:01.72#ibcon#end of sib2, iclass 38, count 0 2006.285.06:24:01.72#ibcon#*after write, iclass 38, count 0 2006.285.06:24:01.72#ibcon#*before return 0, iclass 38, count 0 2006.285.06:24:01.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:24:01.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:24:01.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:24:01.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:24:01.72$vck44/va=8,3 2006.285.06:24:01.72#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.06:24:01.72#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.06:24:01.72#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:01.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:24:01.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:24:01.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:24:01.78#ibcon#enter wrdev, iclass 40, count 2 2006.285.06:24:01.78#ibcon#first serial, iclass 40, count 2 2006.285.06:24:01.78#ibcon#enter sib2, iclass 40, count 2 2006.285.06:24:01.78#ibcon#flushed, iclass 40, count 2 2006.285.06:24:01.78#ibcon#about to write, iclass 40, count 2 2006.285.06:24:01.78#ibcon#wrote, iclass 40, count 2 2006.285.06:24:01.78#ibcon#about to read 3, iclass 40, count 2 2006.285.06:24:01.80#ibcon#read 3, iclass 40, count 2 2006.285.06:24:01.80#ibcon#about to read 4, iclass 40, count 2 2006.285.06:24:01.80#ibcon#read 4, iclass 40, count 2 2006.285.06:24:01.80#ibcon#about to read 5, iclass 40, count 2 2006.285.06:24:01.80#ibcon#read 5, iclass 40, count 2 2006.285.06:24:01.80#ibcon#about to read 6, iclass 40, count 2 2006.285.06:24:01.80#ibcon#read 6, iclass 40, count 2 2006.285.06:24:01.80#ibcon#end of sib2, iclass 40, count 2 2006.285.06:24:01.80#ibcon#*mode == 0, iclass 40, count 2 2006.285.06:24:01.80#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.06:24:01.80#ibcon#[25=AT08-03\r\n] 2006.285.06:24:01.80#ibcon#*before write, iclass 40, count 2 2006.285.06:24:01.80#ibcon#enter sib2, iclass 40, count 2 2006.285.06:24:01.80#ibcon#flushed, iclass 40, count 2 2006.285.06:24:01.80#ibcon#about to write, iclass 40, count 2 2006.285.06:24:01.80#ibcon#wrote, iclass 40, count 2 2006.285.06:24:01.80#ibcon#about to read 3, iclass 40, count 2 2006.285.06:24:01.83#ibcon#read 3, iclass 40, count 2 2006.285.06:24:01.83#ibcon#about to read 4, iclass 40, count 2 2006.285.06:24:01.83#ibcon#read 4, iclass 40, count 2 2006.285.06:24:01.83#ibcon#about to read 5, iclass 40, count 2 2006.285.06:24:01.83#ibcon#read 5, iclass 40, count 2 2006.285.06:24:01.83#ibcon#about to read 6, iclass 40, count 2 2006.285.06:24:01.83#ibcon#read 6, iclass 40, count 2 2006.285.06:24:01.83#ibcon#end of sib2, iclass 40, count 2 2006.285.06:24:01.83#ibcon#*after write, iclass 40, count 2 2006.285.06:24:01.83#ibcon#*before return 0, iclass 40, count 2 2006.285.06:24:01.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:24:01.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:24:01.83#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.06:24:01.83#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:01.83#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:24:01.95#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:24:01.95#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:24:01.95#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:24:01.95#ibcon#first serial, iclass 40, count 0 2006.285.06:24:01.95#ibcon#enter sib2, iclass 40, count 0 2006.285.06:24:01.95#ibcon#flushed, iclass 40, count 0 2006.285.06:24:01.95#ibcon#about to write, iclass 40, count 0 2006.285.06:24:01.95#ibcon#wrote, iclass 40, count 0 2006.285.06:24:01.95#ibcon#about to read 3, iclass 40, count 0 2006.285.06:24:01.97#ibcon#read 3, iclass 40, count 0 2006.285.06:24:01.97#ibcon#about to read 4, iclass 40, count 0 2006.285.06:24:01.97#ibcon#read 4, iclass 40, count 0 2006.285.06:24:01.97#ibcon#about to read 5, iclass 40, count 0 2006.285.06:24:01.97#ibcon#read 5, iclass 40, count 0 2006.285.06:24:01.97#ibcon#about to read 6, iclass 40, count 0 2006.285.06:24:01.97#ibcon#read 6, iclass 40, count 0 2006.285.06:24:01.97#ibcon#end of sib2, iclass 40, count 0 2006.285.06:24:01.97#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:24:01.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:24:01.97#ibcon#[25=USB\r\n] 2006.285.06:24:01.97#ibcon#*before write, iclass 40, count 0 2006.285.06:24:01.97#ibcon#enter sib2, iclass 40, count 0 2006.285.06:24:01.97#ibcon#flushed, iclass 40, count 0 2006.285.06:24:01.97#ibcon#about to write, iclass 40, count 0 2006.285.06:24:01.97#ibcon#wrote, iclass 40, count 0 2006.285.06:24:01.97#ibcon#about to read 3, iclass 40, count 0 2006.285.06:24:02.00#ibcon#read 3, iclass 40, count 0 2006.285.06:24:02.00#ibcon#about to read 4, iclass 40, count 0 2006.285.06:24:02.00#ibcon#read 4, iclass 40, count 0 2006.285.06:24:02.00#ibcon#about to read 5, iclass 40, count 0 2006.285.06:24:02.00#ibcon#read 5, iclass 40, count 0 2006.285.06:24:02.00#ibcon#about to read 6, iclass 40, count 0 2006.285.06:24:02.00#ibcon#read 6, iclass 40, count 0 2006.285.06:24:02.00#ibcon#end of sib2, iclass 40, count 0 2006.285.06:24:02.00#ibcon#*after write, iclass 40, count 0 2006.285.06:24:02.00#ibcon#*before return 0, iclass 40, count 0 2006.285.06:24:02.00#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:24:02.00#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:24:02.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:24:02.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:24:02.00$vck44/vblo=1,629.99 2006.285.06:24:02.00#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.06:24:02.00#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.06:24:02.00#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:02.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:24:02.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:24:02.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:24:02.00#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:24:02.00#ibcon#first serial, iclass 4, count 0 2006.285.06:24:02.00#ibcon#enter sib2, iclass 4, count 0 2006.285.06:24:02.00#ibcon#flushed, iclass 4, count 0 2006.285.06:24:02.00#ibcon#about to write, iclass 4, count 0 2006.285.06:24:02.00#ibcon#wrote, iclass 4, count 0 2006.285.06:24:02.00#ibcon#about to read 3, iclass 4, count 0 2006.285.06:24:02.02#ibcon#read 3, iclass 4, count 0 2006.285.06:24:02.02#ibcon#about to read 4, iclass 4, count 0 2006.285.06:24:02.02#ibcon#read 4, iclass 4, count 0 2006.285.06:24:02.02#ibcon#about to read 5, iclass 4, count 0 2006.285.06:24:02.02#ibcon#read 5, iclass 4, count 0 2006.285.06:24:02.02#ibcon#about to read 6, iclass 4, count 0 2006.285.06:24:02.02#ibcon#read 6, iclass 4, count 0 2006.285.06:24:02.02#ibcon#end of sib2, iclass 4, count 0 2006.285.06:24:02.02#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:24:02.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:24:02.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:24:02.02#ibcon#*before write, iclass 4, count 0 2006.285.06:24:02.02#ibcon#enter sib2, iclass 4, count 0 2006.285.06:24:02.02#ibcon#flushed, iclass 4, count 0 2006.285.06:24:02.02#ibcon#about to write, iclass 4, count 0 2006.285.06:24:02.02#ibcon#wrote, iclass 4, count 0 2006.285.06:24:02.02#ibcon#about to read 3, iclass 4, count 0 2006.285.06:24:02.06#ibcon#read 3, iclass 4, count 0 2006.285.06:24:02.06#ibcon#about to read 4, iclass 4, count 0 2006.285.06:24:02.06#ibcon#read 4, iclass 4, count 0 2006.285.06:24:02.06#ibcon#about to read 5, iclass 4, count 0 2006.285.06:24:02.06#ibcon#read 5, iclass 4, count 0 2006.285.06:24:02.06#ibcon#about to read 6, iclass 4, count 0 2006.285.06:24:02.06#ibcon#read 6, iclass 4, count 0 2006.285.06:24:02.06#ibcon#end of sib2, iclass 4, count 0 2006.285.06:24:02.06#ibcon#*after write, iclass 4, count 0 2006.285.06:24:02.06#ibcon#*before return 0, iclass 4, count 0 2006.285.06:24:02.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:24:02.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:24:02.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:24:02.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:24:02.06$vck44/vb=1,4 2006.285.06:24:02.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.06:24:02.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.06:24:02.06#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:02.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:24:02.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:24:02.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:24:02.06#ibcon#enter wrdev, iclass 6, count 2 2006.285.06:24:02.06#ibcon#first serial, iclass 6, count 2 2006.285.06:24:02.06#ibcon#enter sib2, iclass 6, count 2 2006.285.06:24:02.06#ibcon#flushed, iclass 6, count 2 2006.285.06:24:02.06#ibcon#about to write, iclass 6, count 2 2006.285.06:24:02.06#ibcon#wrote, iclass 6, count 2 2006.285.06:24:02.06#ibcon#about to read 3, iclass 6, count 2 2006.285.06:24:02.08#ibcon#read 3, iclass 6, count 2 2006.285.06:24:02.08#ibcon#about to read 4, iclass 6, count 2 2006.285.06:24:02.08#ibcon#read 4, iclass 6, count 2 2006.285.06:24:02.08#ibcon#about to read 5, iclass 6, count 2 2006.285.06:24:02.08#ibcon#read 5, iclass 6, count 2 2006.285.06:24:02.08#ibcon#about to read 6, iclass 6, count 2 2006.285.06:24:02.08#ibcon#read 6, iclass 6, count 2 2006.285.06:24:02.08#ibcon#end of sib2, iclass 6, count 2 2006.285.06:24:02.08#ibcon#*mode == 0, iclass 6, count 2 2006.285.06:24:02.08#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.06:24:02.08#ibcon#[27=AT01-04\r\n] 2006.285.06:24:02.08#ibcon#*before write, iclass 6, count 2 2006.285.06:24:02.08#ibcon#enter sib2, iclass 6, count 2 2006.285.06:24:02.08#ibcon#flushed, iclass 6, count 2 2006.285.06:24:02.08#ibcon#about to write, iclass 6, count 2 2006.285.06:24:02.08#ibcon#wrote, iclass 6, count 2 2006.285.06:24:02.08#ibcon#about to read 3, iclass 6, count 2 2006.285.06:24:02.11#ibcon#read 3, iclass 6, count 2 2006.285.06:24:02.11#ibcon#about to read 4, iclass 6, count 2 2006.285.06:24:02.11#ibcon#read 4, iclass 6, count 2 2006.285.06:24:02.11#ibcon#about to read 5, iclass 6, count 2 2006.285.06:24:02.11#ibcon#read 5, iclass 6, count 2 2006.285.06:24:02.11#ibcon#about to read 6, iclass 6, count 2 2006.285.06:24:02.11#ibcon#read 6, iclass 6, count 2 2006.285.06:24:02.11#ibcon#end of sib2, iclass 6, count 2 2006.285.06:24:02.11#ibcon#*after write, iclass 6, count 2 2006.285.06:24:02.11#ibcon#*before return 0, iclass 6, count 2 2006.285.06:24:02.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:24:02.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:24:02.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.06:24:02.11#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:02.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:24:02.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:24:02.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:24:02.23#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:24:02.23#ibcon#first serial, iclass 6, count 0 2006.285.06:24:02.23#ibcon#enter sib2, iclass 6, count 0 2006.285.06:24:02.23#ibcon#flushed, iclass 6, count 0 2006.285.06:24:02.23#ibcon#about to write, iclass 6, count 0 2006.285.06:24:02.23#ibcon#wrote, iclass 6, count 0 2006.285.06:24:02.23#ibcon#about to read 3, iclass 6, count 0 2006.285.06:24:02.25#ibcon#read 3, iclass 6, count 0 2006.285.06:24:02.25#ibcon#about to read 4, iclass 6, count 0 2006.285.06:24:02.25#ibcon#read 4, iclass 6, count 0 2006.285.06:24:02.25#ibcon#about to read 5, iclass 6, count 0 2006.285.06:24:02.25#ibcon#read 5, iclass 6, count 0 2006.285.06:24:02.25#ibcon#about to read 6, iclass 6, count 0 2006.285.06:24:02.25#ibcon#read 6, iclass 6, count 0 2006.285.06:24:02.25#ibcon#end of sib2, iclass 6, count 0 2006.285.06:24:02.25#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:24:02.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:24:02.25#ibcon#[27=USB\r\n] 2006.285.06:24:02.25#ibcon#*before write, iclass 6, count 0 2006.285.06:24:02.25#ibcon#enter sib2, iclass 6, count 0 2006.285.06:24:02.25#ibcon#flushed, iclass 6, count 0 2006.285.06:24:02.25#ibcon#about to write, iclass 6, count 0 2006.285.06:24:02.25#ibcon#wrote, iclass 6, count 0 2006.285.06:24:02.25#ibcon#about to read 3, iclass 6, count 0 2006.285.06:24:02.28#ibcon#read 3, iclass 6, count 0 2006.285.06:24:02.28#ibcon#about to read 4, iclass 6, count 0 2006.285.06:24:02.28#ibcon#read 4, iclass 6, count 0 2006.285.06:24:02.28#ibcon#about to read 5, iclass 6, count 0 2006.285.06:24:02.28#ibcon#read 5, iclass 6, count 0 2006.285.06:24:02.28#ibcon#about to read 6, iclass 6, count 0 2006.285.06:24:02.28#ibcon#read 6, iclass 6, count 0 2006.285.06:24:02.28#ibcon#end of sib2, iclass 6, count 0 2006.285.06:24:02.28#ibcon#*after write, iclass 6, count 0 2006.285.06:24:02.28#ibcon#*before return 0, iclass 6, count 0 2006.285.06:24:02.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:24:02.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:24:02.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:24:02.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:24:02.28$vck44/vblo=2,634.99 2006.285.06:24:02.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.06:24:02.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.06:24:02.28#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:02.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:24:02.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:24:02.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:24:02.28#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:24:02.28#ibcon#first serial, iclass 10, count 0 2006.285.06:24:02.28#ibcon#enter sib2, iclass 10, count 0 2006.285.06:24:02.28#ibcon#flushed, iclass 10, count 0 2006.285.06:24:02.28#ibcon#about to write, iclass 10, count 0 2006.285.06:24:02.28#ibcon#wrote, iclass 10, count 0 2006.285.06:24:02.28#ibcon#about to read 3, iclass 10, count 0 2006.285.06:24:02.30#ibcon#read 3, iclass 10, count 0 2006.285.06:24:02.30#ibcon#about to read 4, iclass 10, count 0 2006.285.06:24:02.30#ibcon#read 4, iclass 10, count 0 2006.285.06:24:02.30#ibcon#about to read 5, iclass 10, count 0 2006.285.06:24:02.30#ibcon#read 5, iclass 10, count 0 2006.285.06:24:02.30#ibcon#about to read 6, iclass 10, count 0 2006.285.06:24:02.30#ibcon#read 6, iclass 10, count 0 2006.285.06:24:02.30#ibcon#end of sib2, iclass 10, count 0 2006.285.06:24:02.30#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:24:02.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:24:02.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:24:02.30#ibcon#*before write, iclass 10, count 0 2006.285.06:24:02.30#ibcon#enter sib2, iclass 10, count 0 2006.285.06:24:02.30#ibcon#flushed, iclass 10, count 0 2006.285.06:24:02.30#ibcon#about to write, iclass 10, count 0 2006.285.06:24:02.30#ibcon#wrote, iclass 10, count 0 2006.285.06:24:02.30#ibcon#about to read 3, iclass 10, count 0 2006.285.06:24:02.34#ibcon#read 3, iclass 10, count 0 2006.285.06:24:02.34#ibcon#about to read 4, iclass 10, count 0 2006.285.06:24:02.34#ibcon#read 4, iclass 10, count 0 2006.285.06:24:02.34#ibcon#about to read 5, iclass 10, count 0 2006.285.06:24:02.34#ibcon#read 5, iclass 10, count 0 2006.285.06:24:02.34#ibcon#about to read 6, iclass 10, count 0 2006.285.06:24:02.34#ibcon#read 6, iclass 10, count 0 2006.285.06:24:02.34#ibcon#end of sib2, iclass 10, count 0 2006.285.06:24:02.34#ibcon#*after write, iclass 10, count 0 2006.285.06:24:02.34#ibcon#*before return 0, iclass 10, count 0 2006.285.06:24:02.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:24:02.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:24:02.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:24:02.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:24:02.34$vck44/vb=2,5 2006.285.06:24:02.34#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.06:24:02.34#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.06:24:02.34#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:02.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:24:02.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:24:02.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:24:02.40#ibcon#enter wrdev, iclass 12, count 2 2006.285.06:24:02.40#ibcon#first serial, iclass 12, count 2 2006.285.06:24:02.40#ibcon#enter sib2, iclass 12, count 2 2006.285.06:24:02.40#ibcon#flushed, iclass 12, count 2 2006.285.06:24:02.40#ibcon#about to write, iclass 12, count 2 2006.285.06:24:02.40#ibcon#wrote, iclass 12, count 2 2006.285.06:24:02.40#ibcon#about to read 3, iclass 12, count 2 2006.285.06:24:02.42#ibcon#read 3, iclass 12, count 2 2006.285.06:24:02.42#ibcon#about to read 4, iclass 12, count 2 2006.285.06:24:02.42#ibcon#read 4, iclass 12, count 2 2006.285.06:24:02.42#ibcon#about to read 5, iclass 12, count 2 2006.285.06:24:02.42#ibcon#read 5, iclass 12, count 2 2006.285.06:24:02.42#ibcon#about to read 6, iclass 12, count 2 2006.285.06:24:02.42#ibcon#read 6, iclass 12, count 2 2006.285.06:24:02.42#ibcon#end of sib2, iclass 12, count 2 2006.285.06:24:02.42#ibcon#*mode == 0, iclass 12, count 2 2006.285.06:24:02.42#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.06:24:02.42#ibcon#[27=AT02-05\r\n] 2006.285.06:24:02.42#ibcon#*before write, iclass 12, count 2 2006.285.06:24:02.42#ibcon#enter sib2, iclass 12, count 2 2006.285.06:24:02.42#ibcon#flushed, iclass 12, count 2 2006.285.06:24:02.42#ibcon#about to write, iclass 12, count 2 2006.285.06:24:02.42#ibcon#wrote, iclass 12, count 2 2006.285.06:24:02.42#ibcon#about to read 3, iclass 12, count 2 2006.285.06:24:02.45#ibcon#read 3, iclass 12, count 2 2006.285.06:24:02.45#ibcon#about to read 4, iclass 12, count 2 2006.285.06:24:02.45#ibcon#read 4, iclass 12, count 2 2006.285.06:24:02.45#ibcon#about to read 5, iclass 12, count 2 2006.285.06:24:02.45#ibcon#read 5, iclass 12, count 2 2006.285.06:24:02.45#ibcon#about to read 6, iclass 12, count 2 2006.285.06:24:02.45#ibcon#read 6, iclass 12, count 2 2006.285.06:24:02.45#ibcon#end of sib2, iclass 12, count 2 2006.285.06:24:02.45#ibcon#*after write, iclass 12, count 2 2006.285.06:24:02.45#ibcon#*before return 0, iclass 12, count 2 2006.285.06:24:02.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:24:02.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:24:02.45#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.06:24:02.45#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:02.45#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:24:02.57#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:24:02.57#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:24:02.57#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:24:02.57#ibcon#first serial, iclass 12, count 0 2006.285.06:24:02.57#ibcon#enter sib2, iclass 12, count 0 2006.285.06:24:02.57#ibcon#flushed, iclass 12, count 0 2006.285.06:24:02.57#ibcon#about to write, iclass 12, count 0 2006.285.06:24:02.57#ibcon#wrote, iclass 12, count 0 2006.285.06:24:02.57#ibcon#about to read 3, iclass 12, count 0 2006.285.06:24:02.59#ibcon#read 3, iclass 12, count 0 2006.285.06:24:02.59#ibcon#about to read 4, iclass 12, count 0 2006.285.06:24:02.59#ibcon#read 4, iclass 12, count 0 2006.285.06:24:02.59#ibcon#about to read 5, iclass 12, count 0 2006.285.06:24:02.59#ibcon#read 5, iclass 12, count 0 2006.285.06:24:02.59#ibcon#about to read 6, iclass 12, count 0 2006.285.06:24:02.59#ibcon#read 6, iclass 12, count 0 2006.285.06:24:02.59#ibcon#end of sib2, iclass 12, count 0 2006.285.06:24:02.59#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:24:02.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:24:02.59#ibcon#[27=USB\r\n] 2006.285.06:24:02.59#ibcon#*before write, iclass 12, count 0 2006.285.06:24:02.59#ibcon#enter sib2, iclass 12, count 0 2006.285.06:24:02.59#ibcon#flushed, iclass 12, count 0 2006.285.06:24:02.59#ibcon#about to write, iclass 12, count 0 2006.285.06:24:02.59#ibcon#wrote, iclass 12, count 0 2006.285.06:24:02.59#ibcon#about to read 3, iclass 12, count 0 2006.285.06:24:02.62#ibcon#read 3, iclass 12, count 0 2006.285.06:24:02.62#ibcon#about to read 4, iclass 12, count 0 2006.285.06:24:02.62#ibcon#read 4, iclass 12, count 0 2006.285.06:24:02.62#ibcon#about to read 5, iclass 12, count 0 2006.285.06:24:02.62#ibcon#read 5, iclass 12, count 0 2006.285.06:24:02.62#ibcon#about to read 6, iclass 12, count 0 2006.285.06:24:02.62#ibcon#read 6, iclass 12, count 0 2006.285.06:24:02.62#ibcon#end of sib2, iclass 12, count 0 2006.285.06:24:02.62#ibcon#*after write, iclass 12, count 0 2006.285.06:24:02.62#ibcon#*before return 0, iclass 12, count 0 2006.285.06:24:02.62#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:24:02.62#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:24:02.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:24:02.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:24:02.62$vck44/vblo=3,649.99 2006.285.06:24:02.62#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.06:24:02.62#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.06:24:02.62#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:02.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:24:02.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:24:02.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:24:02.62#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:24:02.62#ibcon#first serial, iclass 14, count 0 2006.285.06:24:02.62#ibcon#enter sib2, iclass 14, count 0 2006.285.06:24:02.62#ibcon#flushed, iclass 14, count 0 2006.285.06:24:02.62#ibcon#about to write, iclass 14, count 0 2006.285.06:24:02.62#ibcon#wrote, iclass 14, count 0 2006.285.06:24:02.62#ibcon#about to read 3, iclass 14, count 0 2006.285.06:24:02.64#ibcon#read 3, iclass 14, count 0 2006.285.06:24:02.64#ibcon#about to read 4, iclass 14, count 0 2006.285.06:24:02.64#ibcon#read 4, iclass 14, count 0 2006.285.06:24:02.64#ibcon#about to read 5, iclass 14, count 0 2006.285.06:24:02.64#ibcon#read 5, iclass 14, count 0 2006.285.06:24:02.64#ibcon#about to read 6, iclass 14, count 0 2006.285.06:24:02.64#ibcon#read 6, iclass 14, count 0 2006.285.06:24:02.64#ibcon#end of sib2, iclass 14, count 0 2006.285.06:24:02.64#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:24:02.64#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:24:02.64#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:24:02.64#ibcon#*before write, iclass 14, count 0 2006.285.06:24:02.64#ibcon#enter sib2, iclass 14, count 0 2006.285.06:24:02.64#ibcon#flushed, iclass 14, count 0 2006.285.06:24:02.64#ibcon#about to write, iclass 14, count 0 2006.285.06:24:02.64#ibcon#wrote, iclass 14, count 0 2006.285.06:24:02.64#ibcon#about to read 3, iclass 14, count 0 2006.285.06:24:02.68#ibcon#read 3, iclass 14, count 0 2006.285.06:24:02.68#ibcon#about to read 4, iclass 14, count 0 2006.285.06:24:02.68#ibcon#read 4, iclass 14, count 0 2006.285.06:24:02.68#ibcon#about to read 5, iclass 14, count 0 2006.285.06:24:02.68#ibcon#read 5, iclass 14, count 0 2006.285.06:24:02.68#ibcon#about to read 6, iclass 14, count 0 2006.285.06:24:02.68#ibcon#read 6, iclass 14, count 0 2006.285.06:24:02.68#ibcon#end of sib2, iclass 14, count 0 2006.285.06:24:02.68#ibcon#*after write, iclass 14, count 0 2006.285.06:24:02.68#ibcon#*before return 0, iclass 14, count 0 2006.285.06:24:02.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:24:02.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:24:02.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:24:02.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:24:02.68$vck44/vb=3,4 2006.285.06:24:02.68#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.06:24:02.68#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.06:24:02.68#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:02.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:24:02.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:24:02.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:24:02.74#ibcon#enter wrdev, iclass 16, count 2 2006.285.06:24:02.74#ibcon#first serial, iclass 16, count 2 2006.285.06:24:02.74#ibcon#enter sib2, iclass 16, count 2 2006.285.06:24:02.74#ibcon#flushed, iclass 16, count 2 2006.285.06:24:02.74#ibcon#about to write, iclass 16, count 2 2006.285.06:24:02.74#ibcon#wrote, iclass 16, count 2 2006.285.06:24:02.74#ibcon#about to read 3, iclass 16, count 2 2006.285.06:24:02.76#ibcon#read 3, iclass 16, count 2 2006.285.06:24:02.76#ibcon#about to read 4, iclass 16, count 2 2006.285.06:24:02.76#ibcon#read 4, iclass 16, count 2 2006.285.06:24:02.76#ibcon#about to read 5, iclass 16, count 2 2006.285.06:24:02.76#ibcon#read 5, iclass 16, count 2 2006.285.06:24:02.76#ibcon#about to read 6, iclass 16, count 2 2006.285.06:24:02.76#ibcon#read 6, iclass 16, count 2 2006.285.06:24:02.76#ibcon#end of sib2, iclass 16, count 2 2006.285.06:24:02.76#ibcon#*mode == 0, iclass 16, count 2 2006.285.06:24:02.76#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.06:24:02.76#ibcon#[27=AT03-04\r\n] 2006.285.06:24:02.76#ibcon#*before write, iclass 16, count 2 2006.285.06:24:02.76#ibcon#enter sib2, iclass 16, count 2 2006.285.06:24:02.76#ibcon#flushed, iclass 16, count 2 2006.285.06:24:02.76#ibcon#about to write, iclass 16, count 2 2006.285.06:24:02.76#ibcon#wrote, iclass 16, count 2 2006.285.06:24:02.76#ibcon#about to read 3, iclass 16, count 2 2006.285.06:24:02.79#ibcon#read 3, iclass 16, count 2 2006.285.06:24:02.79#ibcon#about to read 4, iclass 16, count 2 2006.285.06:24:02.79#ibcon#read 4, iclass 16, count 2 2006.285.06:24:02.79#ibcon#about to read 5, iclass 16, count 2 2006.285.06:24:02.79#ibcon#read 5, iclass 16, count 2 2006.285.06:24:02.79#ibcon#about to read 6, iclass 16, count 2 2006.285.06:24:02.79#ibcon#read 6, iclass 16, count 2 2006.285.06:24:02.79#ibcon#end of sib2, iclass 16, count 2 2006.285.06:24:02.79#ibcon#*after write, iclass 16, count 2 2006.285.06:24:02.79#ibcon#*before return 0, iclass 16, count 2 2006.285.06:24:02.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:24:02.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:24:02.79#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.06:24:02.79#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:02.79#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:24:02.91#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:24:02.91#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:24:02.91#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:24:02.91#ibcon#first serial, iclass 16, count 0 2006.285.06:24:02.91#ibcon#enter sib2, iclass 16, count 0 2006.285.06:24:02.91#ibcon#flushed, iclass 16, count 0 2006.285.06:24:02.91#ibcon#about to write, iclass 16, count 0 2006.285.06:24:02.91#ibcon#wrote, iclass 16, count 0 2006.285.06:24:02.91#ibcon#about to read 3, iclass 16, count 0 2006.285.06:24:02.93#ibcon#read 3, iclass 16, count 0 2006.285.06:24:02.93#ibcon#about to read 4, iclass 16, count 0 2006.285.06:24:02.93#ibcon#read 4, iclass 16, count 0 2006.285.06:24:02.93#ibcon#about to read 5, iclass 16, count 0 2006.285.06:24:02.93#ibcon#read 5, iclass 16, count 0 2006.285.06:24:02.93#ibcon#about to read 6, iclass 16, count 0 2006.285.06:24:02.93#ibcon#read 6, iclass 16, count 0 2006.285.06:24:02.93#ibcon#end of sib2, iclass 16, count 0 2006.285.06:24:02.93#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:24:02.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:24:02.93#ibcon#[27=USB\r\n] 2006.285.06:24:02.93#ibcon#*before write, iclass 16, count 0 2006.285.06:24:02.93#ibcon#enter sib2, iclass 16, count 0 2006.285.06:24:02.93#ibcon#flushed, iclass 16, count 0 2006.285.06:24:02.93#ibcon#about to write, iclass 16, count 0 2006.285.06:24:02.93#ibcon#wrote, iclass 16, count 0 2006.285.06:24:02.93#ibcon#about to read 3, iclass 16, count 0 2006.285.06:24:02.96#ibcon#read 3, iclass 16, count 0 2006.285.06:24:02.96#ibcon#about to read 4, iclass 16, count 0 2006.285.06:24:02.96#ibcon#read 4, iclass 16, count 0 2006.285.06:24:02.96#ibcon#about to read 5, iclass 16, count 0 2006.285.06:24:02.96#ibcon#read 5, iclass 16, count 0 2006.285.06:24:02.96#ibcon#about to read 6, iclass 16, count 0 2006.285.06:24:02.96#ibcon#read 6, iclass 16, count 0 2006.285.06:24:02.96#ibcon#end of sib2, iclass 16, count 0 2006.285.06:24:02.96#ibcon#*after write, iclass 16, count 0 2006.285.06:24:02.96#ibcon#*before return 0, iclass 16, count 0 2006.285.06:24:02.96#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:24:02.96#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:24:02.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:24:02.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:24:02.96$vck44/vblo=4,679.99 2006.285.06:24:02.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.06:24:02.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.06:24:02.96#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:02.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:24:02.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:24:02.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:24:02.96#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:24:02.96#ibcon#first serial, iclass 18, count 0 2006.285.06:24:02.96#ibcon#enter sib2, iclass 18, count 0 2006.285.06:24:02.96#ibcon#flushed, iclass 18, count 0 2006.285.06:24:02.96#ibcon#about to write, iclass 18, count 0 2006.285.06:24:02.96#ibcon#wrote, iclass 18, count 0 2006.285.06:24:02.96#ibcon#about to read 3, iclass 18, count 0 2006.285.06:24:02.98#ibcon#read 3, iclass 18, count 0 2006.285.06:24:02.98#ibcon#about to read 4, iclass 18, count 0 2006.285.06:24:02.98#ibcon#read 4, iclass 18, count 0 2006.285.06:24:02.98#ibcon#about to read 5, iclass 18, count 0 2006.285.06:24:02.98#ibcon#read 5, iclass 18, count 0 2006.285.06:24:02.98#ibcon#about to read 6, iclass 18, count 0 2006.285.06:24:02.98#ibcon#read 6, iclass 18, count 0 2006.285.06:24:02.98#ibcon#end of sib2, iclass 18, count 0 2006.285.06:24:02.98#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:24:02.98#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:24:02.98#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:24:02.98#ibcon#*before write, iclass 18, count 0 2006.285.06:24:02.98#ibcon#enter sib2, iclass 18, count 0 2006.285.06:24:02.98#ibcon#flushed, iclass 18, count 0 2006.285.06:24:02.98#ibcon#about to write, iclass 18, count 0 2006.285.06:24:02.98#ibcon#wrote, iclass 18, count 0 2006.285.06:24:02.98#ibcon#about to read 3, iclass 18, count 0 2006.285.06:24:03.02#ibcon#read 3, iclass 18, count 0 2006.285.06:24:03.02#ibcon#about to read 4, iclass 18, count 0 2006.285.06:24:03.02#ibcon#read 4, iclass 18, count 0 2006.285.06:24:03.02#ibcon#about to read 5, iclass 18, count 0 2006.285.06:24:03.02#ibcon#read 5, iclass 18, count 0 2006.285.06:24:03.02#ibcon#about to read 6, iclass 18, count 0 2006.285.06:24:03.02#ibcon#read 6, iclass 18, count 0 2006.285.06:24:03.02#ibcon#end of sib2, iclass 18, count 0 2006.285.06:24:03.02#ibcon#*after write, iclass 18, count 0 2006.285.06:24:03.02#ibcon#*before return 0, iclass 18, count 0 2006.285.06:24:03.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:24:03.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:24:03.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:24:03.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:24:03.02$vck44/vb=4,5 2006.285.06:24:03.02#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.06:24:03.02#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.06:24:03.02#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:03.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:24:03.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:24:03.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:24:03.08#ibcon#enter wrdev, iclass 20, count 2 2006.285.06:24:03.08#ibcon#first serial, iclass 20, count 2 2006.285.06:24:03.08#ibcon#enter sib2, iclass 20, count 2 2006.285.06:24:03.08#ibcon#flushed, iclass 20, count 2 2006.285.06:24:03.08#ibcon#about to write, iclass 20, count 2 2006.285.06:24:03.08#ibcon#wrote, iclass 20, count 2 2006.285.06:24:03.08#ibcon#about to read 3, iclass 20, count 2 2006.285.06:24:03.10#ibcon#read 3, iclass 20, count 2 2006.285.06:24:03.10#ibcon#about to read 4, iclass 20, count 2 2006.285.06:24:03.10#ibcon#read 4, iclass 20, count 2 2006.285.06:24:03.10#ibcon#about to read 5, iclass 20, count 2 2006.285.06:24:03.10#ibcon#read 5, iclass 20, count 2 2006.285.06:24:03.10#ibcon#about to read 6, iclass 20, count 2 2006.285.06:24:03.10#ibcon#read 6, iclass 20, count 2 2006.285.06:24:03.10#ibcon#end of sib2, iclass 20, count 2 2006.285.06:24:03.10#ibcon#*mode == 0, iclass 20, count 2 2006.285.06:24:03.10#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.06:24:03.10#ibcon#[27=AT04-05\r\n] 2006.285.06:24:03.10#ibcon#*before write, iclass 20, count 2 2006.285.06:24:03.10#ibcon#enter sib2, iclass 20, count 2 2006.285.06:24:03.10#ibcon#flushed, iclass 20, count 2 2006.285.06:24:03.10#ibcon#about to write, iclass 20, count 2 2006.285.06:24:03.10#ibcon#wrote, iclass 20, count 2 2006.285.06:24:03.10#ibcon#about to read 3, iclass 20, count 2 2006.285.06:24:03.13#ibcon#read 3, iclass 20, count 2 2006.285.06:24:03.13#ibcon#about to read 4, iclass 20, count 2 2006.285.06:24:03.13#ibcon#read 4, iclass 20, count 2 2006.285.06:24:03.13#ibcon#about to read 5, iclass 20, count 2 2006.285.06:24:03.13#ibcon#read 5, iclass 20, count 2 2006.285.06:24:03.13#ibcon#about to read 6, iclass 20, count 2 2006.285.06:24:03.13#ibcon#read 6, iclass 20, count 2 2006.285.06:24:03.13#ibcon#end of sib2, iclass 20, count 2 2006.285.06:24:03.13#ibcon#*after write, iclass 20, count 2 2006.285.06:24:03.13#ibcon#*before return 0, iclass 20, count 2 2006.285.06:24:03.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:24:03.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:24:03.13#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.06:24:03.13#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:03.13#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:24:03.25#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:24:03.25#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:24:03.25#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:24:03.25#ibcon#first serial, iclass 20, count 0 2006.285.06:24:03.25#ibcon#enter sib2, iclass 20, count 0 2006.285.06:24:03.25#ibcon#flushed, iclass 20, count 0 2006.285.06:24:03.25#ibcon#about to write, iclass 20, count 0 2006.285.06:24:03.25#ibcon#wrote, iclass 20, count 0 2006.285.06:24:03.25#ibcon#about to read 3, iclass 20, count 0 2006.285.06:24:03.28#ibcon#read 3, iclass 20, count 0 2006.285.06:24:03.28#ibcon#about to read 4, iclass 20, count 0 2006.285.06:24:03.28#ibcon#read 4, iclass 20, count 0 2006.285.06:24:03.28#ibcon#about to read 5, iclass 20, count 0 2006.285.06:24:03.28#ibcon#read 5, iclass 20, count 0 2006.285.06:24:03.28#ibcon#about to read 6, iclass 20, count 0 2006.285.06:24:03.28#ibcon#read 6, iclass 20, count 0 2006.285.06:24:03.28#ibcon#end of sib2, iclass 20, count 0 2006.285.06:24:03.28#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:24:03.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:24:03.28#ibcon#[27=USB\r\n] 2006.285.06:24:03.28#ibcon#*before write, iclass 20, count 0 2006.285.06:24:03.28#ibcon#enter sib2, iclass 20, count 0 2006.285.06:24:03.28#ibcon#flushed, iclass 20, count 0 2006.285.06:24:03.28#ibcon#about to write, iclass 20, count 0 2006.285.06:24:03.28#ibcon#wrote, iclass 20, count 0 2006.285.06:24:03.28#ibcon#about to read 3, iclass 20, count 0 2006.285.06:24:03.31#ibcon#read 3, iclass 20, count 0 2006.285.06:24:03.31#ibcon#about to read 4, iclass 20, count 0 2006.285.06:24:03.31#ibcon#read 4, iclass 20, count 0 2006.285.06:24:03.31#ibcon#about to read 5, iclass 20, count 0 2006.285.06:24:03.31#ibcon#read 5, iclass 20, count 0 2006.285.06:24:03.31#ibcon#about to read 6, iclass 20, count 0 2006.285.06:24:03.31#ibcon#read 6, iclass 20, count 0 2006.285.06:24:03.31#ibcon#end of sib2, iclass 20, count 0 2006.285.06:24:03.31#ibcon#*after write, iclass 20, count 0 2006.285.06:24:03.31#ibcon#*before return 0, iclass 20, count 0 2006.285.06:24:03.31#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:24:03.31#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:24:03.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:24:03.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:24:03.31$vck44/vblo=5,709.99 2006.285.06:24:03.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.06:24:03.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.06:24:03.31#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:03.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:24:03.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:24:03.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:24:03.31#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:24:03.31#ibcon#first serial, iclass 22, count 0 2006.285.06:24:03.31#ibcon#enter sib2, iclass 22, count 0 2006.285.06:24:03.31#ibcon#flushed, iclass 22, count 0 2006.285.06:24:03.31#ibcon#about to write, iclass 22, count 0 2006.285.06:24:03.31#ibcon#wrote, iclass 22, count 0 2006.285.06:24:03.31#ibcon#about to read 3, iclass 22, count 0 2006.285.06:24:03.33#ibcon#read 3, iclass 22, count 0 2006.285.06:24:03.33#ibcon#about to read 4, iclass 22, count 0 2006.285.06:24:03.33#ibcon#read 4, iclass 22, count 0 2006.285.06:24:03.33#ibcon#about to read 5, iclass 22, count 0 2006.285.06:24:03.33#ibcon#read 5, iclass 22, count 0 2006.285.06:24:03.33#ibcon#about to read 6, iclass 22, count 0 2006.285.06:24:03.33#ibcon#read 6, iclass 22, count 0 2006.285.06:24:03.33#ibcon#end of sib2, iclass 22, count 0 2006.285.06:24:03.33#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:24:03.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:24:03.33#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:24:03.33#ibcon#*before write, iclass 22, count 0 2006.285.06:24:03.33#ibcon#enter sib2, iclass 22, count 0 2006.285.06:24:03.33#ibcon#flushed, iclass 22, count 0 2006.285.06:24:03.33#ibcon#about to write, iclass 22, count 0 2006.285.06:24:03.33#ibcon#wrote, iclass 22, count 0 2006.285.06:24:03.33#ibcon#about to read 3, iclass 22, count 0 2006.285.06:24:03.37#ibcon#read 3, iclass 22, count 0 2006.285.06:24:03.37#ibcon#about to read 4, iclass 22, count 0 2006.285.06:24:03.37#ibcon#read 4, iclass 22, count 0 2006.285.06:24:03.37#ibcon#about to read 5, iclass 22, count 0 2006.285.06:24:03.37#ibcon#read 5, iclass 22, count 0 2006.285.06:24:03.37#ibcon#about to read 6, iclass 22, count 0 2006.285.06:24:03.37#ibcon#read 6, iclass 22, count 0 2006.285.06:24:03.37#ibcon#end of sib2, iclass 22, count 0 2006.285.06:24:03.37#ibcon#*after write, iclass 22, count 0 2006.285.06:24:03.37#ibcon#*before return 0, iclass 22, count 0 2006.285.06:24:03.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:24:03.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:24:03.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:24:03.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:24:03.37$vck44/vb=5,4 2006.285.06:24:03.37#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.06:24:03.37#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.06:24:03.37#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:03.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:24:03.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:24:03.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:24:03.43#ibcon#enter wrdev, iclass 24, count 2 2006.285.06:24:03.43#ibcon#first serial, iclass 24, count 2 2006.285.06:24:03.43#ibcon#enter sib2, iclass 24, count 2 2006.285.06:24:03.43#ibcon#flushed, iclass 24, count 2 2006.285.06:24:03.43#ibcon#about to write, iclass 24, count 2 2006.285.06:24:03.43#ibcon#wrote, iclass 24, count 2 2006.285.06:24:03.43#ibcon#about to read 3, iclass 24, count 2 2006.285.06:24:03.45#ibcon#read 3, iclass 24, count 2 2006.285.06:24:03.45#ibcon#about to read 4, iclass 24, count 2 2006.285.06:24:03.45#ibcon#read 4, iclass 24, count 2 2006.285.06:24:03.45#ibcon#about to read 5, iclass 24, count 2 2006.285.06:24:03.45#ibcon#read 5, iclass 24, count 2 2006.285.06:24:03.45#ibcon#about to read 6, iclass 24, count 2 2006.285.06:24:03.45#ibcon#read 6, iclass 24, count 2 2006.285.06:24:03.45#ibcon#end of sib2, iclass 24, count 2 2006.285.06:24:03.45#ibcon#*mode == 0, iclass 24, count 2 2006.285.06:24:03.45#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.06:24:03.45#ibcon#[27=AT05-04\r\n] 2006.285.06:24:03.45#ibcon#*before write, iclass 24, count 2 2006.285.06:24:03.45#ibcon#enter sib2, iclass 24, count 2 2006.285.06:24:03.45#ibcon#flushed, iclass 24, count 2 2006.285.06:24:03.45#ibcon#about to write, iclass 24, count 2 2006.285.06:24:03.45#ibcon#wrote, iclass 24, count 2 2006.285.06:24:03.45#ibcon#about to read 3, iclass 24, count 2 2006.285.06:24:03.48#ibcon#read 3, iclass 24, count 2 2006.285.06:24:03.48#ibcon#about to read 4, iclass 24, count 2 2006.285.06:24:03.48#ibcon#read 4, iclass 24, count 2 2006.285.06:24:03.48#ibcon#about to read 5, iclass 24, count 2 2006.285.06:24:03.48#ibcon#read 5, iclass 24, count 2 2006.285.06:24:03.48#ibcon#about to read 6, iclass 24, count 2 2006.285.06:24:03.48#ibcon#read 6, iclass 24, count 2 2006.285.06:24:03.48#ibcon#end of sib2, iclass 24, count 2 2006.285.06:24:03.48#ibcon#*after write, iclass 24, count 2 2006.285.06:24:03.48#ibcon#*before return 0, iclass 24, count 2 2006.285.06:24:03.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:24:03.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:24:03.48#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.06:24:03.48#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:03.48#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:24:03.60#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:24:03.60#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:24:03.60#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:24:03.60#ibcon#first serial, iclass 24, count 0 2006.285.06:24:03.60#ibcon#enter sib2, iclass 24, count 0 2006.285.06:24:03.60#ibcon#flushed, iclass 24, count 0 2006.285.06:24:03.60#ibcon#about to write, iclass 24, count 0 2006.285.06:24:03.60#ibcon#wrote, iclass 24, count 0 2006.285.06:24:03.60#ibcon#about to read 3, iclass 24, count 0 2006.285.06:24:03.62#ibcon#read 3, iclass 24, count 0 2006.285.06:24:03.62#ibcon#about to read 4, iclass 24, count 0 2006.285.06:24:03.62#ibcon#read 4, iclass 24, count 0 2006.285.06:24:03.62#ibcon#about to read 5, iclass 24, count 0 2006.285.06:24:03.62#ibcon#read 5, iclass 24, count 0 2006.285.06:24:03.62#ibcon#about to read 6, iclass 24, count 0 2006.285.06:24:03.62#ibcon#read 6, iclass 24, count 0 2006.285.06:24:03.62#ibcon#end of sib2, iclass 24, count 0 2006.285.06:24:03.62#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:24:03.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:24:03.62#ibcon#[27=USB\r\n] 2006.285.06:24:03.62#ibcon#*before write, iclass 24, count 0 2006.285.06:24:03.62#ibcon#enter sib2, iclass 24, count 0 2006.285.06:24:03.62#ibcon#flushed, iclass 24, count 0 2006.285.06:24:03.62#ibcon#about to write, iclass 24, count 0 2006.285.06:24:03.62#ibcon#wrote, iclass 24, count 0 2006.285.06:24:03.62#ibcon#about to read 3, iclass 24, count 0 2006.285.06:24:03.65#ibcon#read 3, iclass 24, count 0 2006.285.06:24:03.65#ibcon#about to read 4, iclass 24, count 0 2006.285.06:24:03.65#ibcon#read 4, iclass 24, count 0 2006.285.06:24:03.65#ibcon#about to read 5, iclass 24, count 0 2006.285.06:24:03.65#ibcon#read 5, iclass 24, count 0 2006.285.06:24:03.65#ibcon#about to read 6, iclass 24, count 0 2006.285.06:24:03.65#ibcon#read 6, iclass 24, count 0 2006.285.06:24:03.65#ibcon#end of sib2, iclass 24, count 0 2006.285.06:24:03.65#ibcon#*after write, iclass 24, count 0 2006.285.06:24:03.65#ibcon#*before return 0, iclass 24, count 0 2006.285.06:24:03.65#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:24:03.65#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:24:03.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:24:03.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:24:03.65$vck44/vblo=6,719.99 2006.285.06:24:03.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.06:24:03.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.06:24:03.65#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:03.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:24:03.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:24:03.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:24:03.65#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:24:03.65#ibcon#first serial, iclass 26, count 0 2006.285.06:24:03.65#ibcon#enter sib2, iclass 26, count 0 2006.285.06:24:03.65#ibcon#flushed, iclass 26, count 0 2006.285.06:24:03.65#ibcon#about to write, iclass 26, count 0 2006.285.06:24:03.65#ibcon#wrote, iclass 26, count 0 2006.285.06:24:03.65#ibcon#about to read 3, iclass 26, count 0 2006.285.06:24:03.67#ibcon#read 3, iclass 26, count 0 2006.285.06:24:03.67#ibcon#about to read 4, iclass 26, count 0 2006.285.06:24:03.67#ibcon#read 4, iclass 26, count 0 2006.285.06:24:03.67#ibcon#about to read 5, iclass 26, count 0 2006.285.06:24:03.67#ibcon#read 5, iclass 26, count 0 2006.285.06:24:03.67#ibcon#about to read 6, iclass 26, count 0 2006.285.06:24:03.67#ibcon#read 6, iclass 26, count 0 2006.285.06:24:03.67#ibcon#end of sib2, iclass 26, count 0 2006.285.06:24:03.67#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:24:03.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:24:03.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:24:03.67#ibcon#*before write, iclass 26, count 0 2006.285.06:24:03.67#ibcon#enter sib2, iclass 26, count 0 2006.285.06:24:03.67#ibcon#flushed, iclass 26, count 0 2006.285.06:24:03.67#ibcon#about to write, iclass 26, count 0 2006.285.06:24:03.67#ibcon#wrote, iclass 26, count 0 2006.285.06:24:03.67#ibcon#about to read 3, iclass 26, count 0 2006.285.06:24:03.71#ibcon#read 3, iclass 26, count 0 2006.285.06:24:03.71#ibcon#about to read 4, iclass 26, count 0 2006.285.06:24:03.71#ibcon#read 4, iclass 26, count 0 2006.285.06:24:03.71#ibcon#about to read 5, iclass 26, count 0 2006.285.06:24:03.71#ibcon#read 5, iclass 26, count 0 2006.285.06:24:03.71#ibcon#about to read 6, iclass 26, count 0 2006.285.06:24:03.71#ibcon#read 6, iclass 26, count 0 2006.285.06:24:03.71#ibcon#end of sib2, iclass 26, count 0 2006.285.06:24:03.71#ibcon#*after write, iclass 26, count 0 2006.285.06:24:03.71#ibcon#*before return 0, iclass 26, count 0 2006.285.06:24:03.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:24:03.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:24:03.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:24:03.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:24:03.71$vck44/vb=6,3 2006.285.06:24:03.71#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.06:24:03.71#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.06:24:03.71#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:03.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:24:03.77#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:24:03.77#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:24:03.77#ibcon#enter wrdev, iclass 28, count 2 2006.285.06:24:03.77#ibcon#first serial, iclass 28, count 2 2006.285.06:24:03.77#ibcon#enter sib2, iclass 28, count 2 2006.285.06:24:03.77#ibcon#flushed, iclass 28, count 2 2006.285.06:24:03.77#ibcon#about to write, iclass 28, count 2 2006.285.06:24:03.77#ibcon#wrote, iclass 28, count 2 2006.285.06:24:03.77#ibcon#about to read 3, iclass 28, count 2 2006.285.06:24:03.79#ibcon#read 3, iclass 28, count 2 2006.285.06:24:03.79#ibcon#about to read 4, iclass 28, count 2 2006.285.06:24:03.79#ibcon#read 4, iclass 28, count 2 2006.285.06:24:03.79#ibcon#about to read 5, iclass 28, count 2 2006.285.06:24:03.79#ibcon#read 5, iclass 28, count 2 2006.285.06:24:03.79#ibcon#about to read 6, iclass 28, count 2 2006.285.06:24:03.79#ibcon#read 6, iclass 28, count 2 2006.285.06:24:03.79#ibcon#end of sib2, iclass 28, count 2 2006.285.06:24:03.79#ibcon#*mode == 0, iclass 28, count 2 2006.285.06:24:03.79#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.06:24:03.79#ibcon#[27=AT06-03\r\n] 2006.285.06:24:03.79#ibcon#*before write, iclass 28, count 2 2006.285.06:24:03.79#ibcon#enter sib2, iclass 28, count 2 2006.285.06:24:03.79#ibcon#flushed, iclass 28, count 2 2006.285.06:24:03.79#ibcon#about to write, iclass 28, count 2 2006.285.06:24:03.79#ibcon#wrote, iclass 28, count 2 2006.285.06:24:03.79#ibcon#about to read 3, iclass 28, count 2 2006.285.06:24:03.82#ibcon#read 3, iclass 28, count 2 2006.285.06:24:03.82#ibcon#about to read 4, iclass 28, count 2 2006.285.06:24:03.82#ibcon#read 4, iclass 28, count 2 2006.285.06:24:03.82#ibcon#about to read 5, iclass 28, count 2 2006.285.06:24:03.82#ibcon#read 5, iclass 28, count 2 2006.285.06:24:03.82#ibcon#about to read 6, iclass 28, count 2 2006.285.06:24:03.82#ibcon#read 6, iclass 28, count 2 2006.285.06:24:03.82#ibcon#end of sib2, iclass 28, count 2 2006.285.06:24:03.82#ibcon#*after write, iclass 28, count 2 2006.285.06:24:03.82#ibcon#*before return 0, iclass 28, count 2 2006.285.06:24:03.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:24:03.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:24:03.82#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.06:24:03.82#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:03.82#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:24:03.88#abcon#<5=/05 4.6 7.3 24.96 701014.0\r\n> 2006.285.06:24:03.90#abcon#{5=INTERFACE CLEAR} 2006.285.06:24:03.94#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:24:03.94#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:24:03.94#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:24:03.94#ibcon#first serial, iclass 28, count 0 2006.285.06:24:03.94#ibcon#enter sib2, iclass 28, count 0 2006.285.06:24:03.94#ibcon#flushed, iclass 28, count 0 2006.285.06:24:03.94#ibcon#about to write, iclass 28, count 0 2006.285.06:24:03.94#ibcon#wrote, iclass 28, count 0 2006.285.06:24:03.94#ibcon#about to read 3, iclass 28, count 0 2006.285.06:24:03.96#ibcon#read 3, iclass 28, count 0 2006.285.06:24:03.96#ibcon#about to read 4, iclass 28, count 0 2006.285.06:24:03.96#ibcon#read 4, iclass 28, count 0 2006.285.06:24:03.96#ibcon#about to read 5, iclass 28, count 0 2006.285.06:24:03.96#ibcon#read 5, iclass 28, count 0 2006.285.06:24:03.96#ibcon#about to read 6, iclass 28, count 0 2006.285.06:24:03.96#ibcon#read 6, iclass 28, count 0 2006.285.06:24:03.96#ibcon#end of sib2, iclass 28, count 0 2006.285.06:24:03.96#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:24:03.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:24:03.96#ibcon#[27=USB\r\n] 2006.285.06:24:03.96#ibcon#*before write, iclass 28, count 0 2006.285.06:24:03.96#ibcon#enter sib2, iclass 28, count 0 2006.285.06:24:03.96#ibcon#flushed, iclass 28, count 0 2006.285.06:24:03.96#ibcon#about to write, iclass 28, count 0 2006.285.06:24:03.96#ibcon#wrote, iclass 28, count 0 2006.285.06:24:03.96#ibcon#about to read 3, iclass 28, count 0 2006.285.06:24:03.96#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:24:03.99#ibcon#read 3, iclass 28, count 0 2006.285.06:24:03.99#ibcon#about to read 4, iclass 28, count 0 2006.285.06:24:03.99#ibcon#read 4, iclass 28, count 0 2006.285.06:24:03.99#ibcon#about to read 5, iclass 28, count 0 2006.285.06:24:03.99#ibcon#read 5, iclass 28, count 0 2006.285.06:24:03.99#ibcon#about to read 6, iclass 28, count 0 2006.285.06:24:03.99#ibcon#read 6, iclass 28, count 0 2006.285.06:24:03.99#ibcon#end of sib2, iclass 28, count 0 2006.285.06:24:03.99#ibcon#*after write, iclass 28, count 0 2006.285.06:24:03.99#ibcon#*before return 0, iclass 28, count 0 2006.285.06:24:03.99#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:24:03.99#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:24:03.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:24:03.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:24:03.99$vck44/vblo=7,734.99 2006.285.06:24:03.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.06:24:03.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.06:24:03.99#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:03.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:24:03.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:24:03.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:24:03.99#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:24:03.99#ibcon#first serial, iclass 34, count 0 2006.285.06:24:03.99#ibcon#enter sib2, iclass 34, count 0 2006.285.06:24:03.99#ibcon#flushed, iclass 34, count 0 2006.285.06:24:03.99#ibcon#about to write, iclass 34, count 0 2006.285.06:24:03.99#ibcon#wrote, iclass 34, count 0 2006.285.06:24:03.99#ibcon#about to read 3, iclass 34, count 0 2006.285.06:24:04.01#ibcon#read 3, iclass 34, count 0 2006.285.06:24:04.01#ibcon#about to read 4, iclass 34, count 0 2006.285.06:24:04.01#ibcon#read 4, iclass 34, count 0 2006.285.06:24:04.01#ibcon#about to read 5, iclass 34, count 0 2006.285.06:24:04.01#ibcon#read 5, iclass 34, count 0 2006.285.06:24:04.01#ibcon#about to read 6, iclass 34, count 0 2006.285.06:24:04.01#ibcon#read 6, iclass 34, count 0 2006.285.06:24:04.01#ibcon#end of sib2, iclass 34, count 0 2006.285.06:24:04.01#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:24:04.01#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:24:04.01#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:24:04.01#ibcon#*before write, iclass 34, count 0 2006.285.06:24:04.01#ibcon#enter sib2, iclass 34, count 0 2006.285.06:24:04.01#ibcon#flushed, iclass 34, count 0 2006.285.06:24:04.01#ibcon#about to write, iclass 34, count 0 2006.285.06:24:04.01#ibcon#wrote, iclass 34, count 0 2006.285.06:24:04.01#ibcon#about to read 3, iclass 34, count 0 2006.285.06:24:04.05#ibcon#read 3, iclass 34, count 0 2006.285.06:24:04.05#ibcon#about to read 4, iclass 34, count 0 2006.285.06:24:04.05#ibcon#read 4, iclass 34, count 0 2006.285.06:24:04.05#ibcon#about to read 5, iclass 34, count 0 2006.285.06:24:04.05#ibcon#read 5, iclass 34, count 0 2006.285.06:24:04.05#ibcon#about to read 6, iclass 34, count 0 2006.285.06:24:04.05#ibcon#read 6, iclass 34, count 0 2006.285.06:24:04.05#ibcon#end of sib2, iclass 34, count 0 2006.285.06:24:04.05#ibcon#*after write, iclass 34, count 0 2006.285.06:24:04.05#ibcon#*before return 0, iclass 34, count 0 2006.285.06:24:04.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:24:04.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:24:04.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:24:04.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:24:04.05$vck44/vb=7,4 2006.285.06:24:04.05#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.06:24:04.05#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.06:24:04.05#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:04.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:24:04.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:24:04.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:24:04.11#ibcon#enter wrdev, iclass 36, count 2 2006.285.06:24:04.11#ibcon#first serial, iclass 36, count 2 2006.285.06:24:04.11#ibcon#enter sib2, iclass 36, count 2 2006.285.06:24:04.11#ibcon#flushed, iclass 36, count 2 2006.285.06:24:04.11#ibcon#about to write, iclass 36, count 2 2006.285.06:24:04.11#ibcon#wrote, iclass 36, count 2 2006.285.06:24:04.11#ibcon#about to read 3, iclass 36, count 2 2006.285.06:24:04.13#ibcon#read 3, iclass 36, count 2 2006.285.06:24:04.13#ibcon#about to read 4, iclass 36, count 2 2006.285.06:24:04.13#ibcon#read 4, iclass 36, count 2 2006.285.06:24:04.13#ibcon#about to read 5, iclass 36, count 2 2006.285.06:24:04.13#ibcon#read 5, iclass 36, count 2 2006.285.06:24:04.13#ibcon#about to read 6, iclass 36, count 2 2006.285.06:24:04.13#ibcon#read 6, iclass 36, count 2 2006.285.06:24:04.13#ibcon#end of sib2, iclass 36, count 2 2006.285.06:24:04.13#ibcon#*mode == 0, iclass 36, count 2 2006.285.06:24:04.13#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.06:24:04.13#ibcon#[27=AT07-04\r\n] 2006.285.06:24:04.13#ibcon#*before write, iclass 36, count 2 2006.285.06:24:04.13#ibcon#enter sib2, iclass 36, count 2 2006.285.06:24:04.13#ibcon#flushed, iclass 36, count 2 2006.285.06:24:04.13#ibcon#about to write, iclass 36, count 2 2006.285.06:24:04.13#ibcon#wrote, iclass 36, count 2 2006.285.06:24:04.13#ibcon#about to read 3, iclass 36, count 2 2006.285.06:24:04.16#ibcon#read 3, iclass 36, count 2 2006.285.06:24:04.16#ibcon#about to read 4, iclass 36, count 2 2006.285.06:24:04.16#ibcon#read 4, iclass 36, count 2 2006.285.06:24:04.16#ibcon#about to read 5, iclass 36, count 2 2006.285.06:24:04.16#ibcon#read 5, iclass 36, count 2 2006.285.06:24:04.16#ibcon#about to read 6, iclass 36, count 2 2006.285.06:24:04.16#ibcon#read 6, iclass 36, count 2 2006.285.06:24:04.16#ibcon#end of sib2, iclass 36, count 2 2006.285.06:24:04.16#ibcon#*after write, iclass 36, count 2 2006.285.06:24:04.16#ibcon#*before return 0, iclass 36, count 2 2006.285.06:24:04.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:24:04.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:24:04.16#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.06:24:04.16#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:04.16#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:24:04.28#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:24:04.28#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:24:04.28#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:24:04.28#ibcon#first serial, iclass 36, count 0 2006.285.06:24:04.28#ibcon#enter sib2, iclass 36, count 0 2006.285.06:24:04.28#ibcon#flushed, iclass 36, count 0 2006.285.06:24:04.28#ibcon#about to write, iclass 36, count 0 2006.285.06:24:04.28#ibcon#wrote, iclass 36, count 0 2006.285.06:24:04.28#ibcon#about to read 3, iclass 36, count 0 2006.285.06:24:04.30#ibcon#read 3, iclass 36, count 0 2006.285.06:24:04.30#ibcon#about to read 4, iclass 36, count 0 2006.285.06:24:04.30#ibcon#read 4, iclass 36, count 0 2006.285.06:24:04.30#ibcon#about to read 5, iclass 36, count 0 2006.285.06:24:04.30#ibcon#read 5, iclass 36, count 0 2006.285.06:24:04.30#ibcon#about to read 6, iclass 36, count 0 2006.285.06:24:04.30#ibcon#read 6, iclass 36, count 0 2006.285.06:24:04.30#ibcon#end of sib2, iclass 36, count 0 2006.285.06:24:04.30#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:24:04.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:24:04.30#ibcon#[27=USB\r\n] 2006.285.06:24:04.30#ibcon#*before write, iclass 36, count 0 2006.285.06:24:04.30#ibcon#enter sib2, iclass 36, count 0 2006.285.06:24:04.30#ibcon#flushed, iclass 36, count 0 2006.285.06:24:04.30#ibcon#about to write, iclass 36, count 0 2006.285.06:24:04.30#ibcon#wrote, iclass 36, count 0 2006.285.06:24:04.30#ibcon#about to read 3, iclass 36, count 0 2006.285.06:24:04.33#ibcon#read 3, iclass 36, count 0 2006.285.06:24:04.33#ibcon#about to read 4, iclass 36, count 0 2006.285.06:24:04.33#ibcon#read 4, iclass 36, count 0 2006.285.06:24:04.33#ibcon#about to read 5, iclass 36, count 0 2006.285.06:24:04.33#ibcon#read 5, iclass 36, count 0 2006.285.06:24:04.33#ibcon#about to read 6, iclass 36, count 0 2006.285.06:24:04.33#ibcon#read 6, iclass 36, count 0 2006.285.06:24:04.33#ibcon#end of sib2, iclass 36, count 0 2006.285.06:24:04.33#ibcon#*after write, iclass 36, count 0 2006.285.06:24:04.33#ibcon#*before return 0, iclass 36, count 0 2006.285.06:24:04.33#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:24:04.33#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:24:04.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:24:04.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:24:04.33$vck44/vblo=8,744.99 2006.285.06:24:04.33#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.06:24:04.33#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.06:24:04.33#ibcon#ireg 17 cls_cnt 0 2006.285.06:24:04.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:24:04.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:24:04.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:24:04.33#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:24:04.33#ibcon#first serial, iclass 38, count 0 2006.285.06:24:04.33#ibcon#enter sib2, iclass 38, count 0 2006.285.06:24:04.33#ibcon#flushed, iclass 38, count 0 2006.285.06:24:04.33#ibcon#about to write, iclass 38, count 0 2006.285.06:24:04.33#ibcon#wrote, iclass 38, count 0 2006.285.06:24:04.33#ibcon#about to read 3, iclass 38, count 0 2006.285.06:24:04.35#ibcon#read 3, iclass 38, count 0 2006.285.06:24:04.35#ibcon#about to read 4, iclass 38, count 0 2006.285.06:24:04.35#ibcon#read 4, iclass 38, count 0 2006.285.06:24:04.35#ibcon#about to read 5, iclass 38, count 0 2006.285.06:24:04.35#ibcon#read 5, iclass 38, count 0 2006.285.06:24:04.35#ibcon#about to read 6, iclass 38, count 0 2006.285.06:24:04.35#ibcon#read 6, iclass 38, count 0 2006.285.06:24:04.35#ibcon#end of sib2, iclass 38, count 0 2006.285.06:24:04.35#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:24:04.35#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:24:04.35#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:24:04.35#ibcon#*before write, iclass 38, count 0 2006.285.06:24:04.35#ibcon#enter sib2, iclass 38, count 0 2006.285.06:24:04.35#ibcon#flushed, iclass 38, count 0 2006.285.06:24:04.35#ibcon#about to write, iclass 38, count 0 2006.285.06:24:04.35#ibcon#wrote, iclass 38, count 0 2006.285.06:24:04.35#ibcon#about to read 3, iclass 38, count 0 2006.285.06:24:04.39#ibcon#read 3, iclass 38, count 0 2006.285.06:24:04.39#ibcon#about to read 4, iclass 38, count 0 2006.285.06:24:04.39#ibcon#read 4, iclass 38, count 0 2006.285.06:24:04.39#ibcon#about to read 5, iclass 38, count 0 2006.285.06:24:04.39#ibcon#read 5, iclass 38, count 0 2006.285.06:24:04.39#ibcon#about to read 6, iclass 38, count 0 2006.285.06:24:04.39#ibcon#read 6, iclass 38, count 0 2006.285.06:24:04.39#ibcon#end of sib2, iclass 38, count 0 2006.285.06:24:04.39#ibcon#*after write, iclass 38, count 0 2006.285.06:24:04.39#ibcon#*before return 0, iclass 38, count 0 2006.285.06:24:04.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:24:04.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:24:04.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:24:04.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:24:04.39$vck44/vb=8,4 2006.285.06:24:04.39#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.06:24:04.39#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.06:24:04.39#ibcon#ireg 11 cls_cnt 2 2006.285.06:24:04.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:24:04.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:24:04.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:24:04.45#ibcon#enter wrdev, iclass 40, count 2 2006.285.06:24:04.45#ibcon#first serial, iclass 40, count 2 2006.285.06:24:04.45#ibcon#enter sib2, iclass 40, count 2 2006.285.06:24:04.45#ibcon#flushed, iclass 40, count 2 2006.285.06:24:04.45#ibcon#about to write, iclass 40, count 2 2006.285.06:24:04.45#ibcon#wrote, iclass 40, count 2 2006.285.06:24:04.45#ibcon#about to read 3, iclass 40, count 2 2006.285.06:24:04.47#ibcon#read 3, iclass 40, count 2 2006.285.06:24:04.47#ibcon#about to read 4, iclass 40, count 2 2006.285.06:24:04.47#ibcon#read 4, iclass 40, count 2 2006.285.06:24:04.47#ibcon#about to read 5, iclass 40, count 2 2006.285.06:24:04.47#ibcon#read 5, iclass 40, count 2 2006.285.06:24:04.47#ibcon#about to read 6, iclass 40, count 2 2006.285.06:24:04.47#ibcon#read 6, iclass 40, count 2 2006.285.06:24:04.47#ibcon#end of sib2, iclass 40, count 2 2006.285.06:24:04.47#ibcon#*mode == 0, iclass 40, count 2 2006.285.06:24:04.47#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.06:24:04.47#ibcon#[27=AT08-04\r\n] 2006.285.06:24:04.47#ibcon#*before write, iclass 40, count 2 2006.285.06:24:04.47#ibcon#enter sib2, iclass 40, count 2 2006.285.06:24:04.47#ibcon#flushed, iclass 40, count 2 2006.285.06:24:04.47#ibcon#about to write, iclass 40, count 2 2006.285.06:24:04.47#ibcon#wrote, iclass 40, count 2 2006.285.06:24:04.47#ibcon#about to read 3, iclass 40, count 2 2006.285.06:24:04.50#ibcon#read 3, iclass 40, count 2 2006.285.06:24:04.50#ibcon#about to read 4, iclass 40, count 2 2006.285.06:24:04.50#ibcon#read 4, iclass 40, count 2 2006.285.06:24:04.50#ibcon#about to read 5, iclass 40, count 2 2006.285.06:24:04.50#ibcon#read 5, iclass 40, count 2 2006.285.06:24:04.50#ibcon#about to read 6, iclass 40, count 2 2006.285.06:24:04.50#ibcon#read 6, iclass 40, count 2 2006.285.06:24:04.50#ibcon#end of sib2, iclass 40, count 2 2006.285.06:24:04.50#ibcon#*after write, iclass 40, count 2 2006.285.06:24:04.50#ibcon#*before return 0, iclass 40, count 2 2006.285.06:24:04.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:24:04.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:24:04.50#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.06:24:04.50#ibcon#ireg 7 cls_cnt 0 2006.285.06:24:04.50#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:24:04.62#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:24:04.62#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:24:04.62#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:24:04.62#ibcon#first serial, iclass 40, count 0 2006.285.06:24:04.62#ibcon#enter sib2, iclass 40, count 0 2006.285.06:24:04.62#ibcon#flushed, iclass 40, count 0 2006.285.06:24:04.62#ibcon#about to write, iclass 40, count 0 2006.285.06:24:04.62#ibcon#wrote, iclass 40, count 0 2006.285.06:24:04.62#ibcon#about to read 3, iclass 40, count 0 2006.285.06:24:04.64#ibcon#read 3, iclass 40, count 0 2006.285.06:24:04.64#ibcon#about to read 4, iclass 40, count 0 2006.285.06:24:04.64#ibcon#read 4, iclass 40, count 0 2006.285.06:24:04.64#ibcon#about to read 5, iclass 40, count 0 2006.285.06:24:04.64#ibcon#read 5, iclass 40, count 0 2006.285.06:24:04.64#ibcon#about to read 6, iclass 40, count 0 2006.285.06:24:04.64#ibcon#read 6, iclass 40, count 0 2006.285.06:24:04.64#ibcon#end of sib2, iclass 40, count 0 2006.285.06:24:04.64#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:24:04.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:24:04.64#ibcon#[27=USB\r\n] 2006.285.06:24:04.64#ibcon#*before write, iclass 40, count 0 2006.285.06:24:04.64#ibcon#enter sib2, iclass 40, count 0 2006.285.06:24:04.64#ibcon#flushed, iclass 40, count 0 2006.285.06:24:04.64#ibcon#about to write, iclass 40, count 0 2006.285.06:24:04.64#ibcon#wrote, iclass 40, count 0 2006.285.06:24:04.64#ibcon#about to read 3, iclass 40, count 0 2006.285.06:24:04.67#ibcon#read 3, iclass 40, count 0 2006.285.06:24:04.67#ibcon#about to read 4, iclass 40, count 0 2006.285.06:24:04.67#ibcon#read 4, iclass 40, count 0 2006.285.06:24:04.67#ibcon#about to read 5, iclass 40, count 0 2006.285.06:24:04.67#ibcon#read 5, iclass 40, count 0 2006.285.06:24:04.67#ibcon#about to read 6, iclass 40, count 0 2006.285.06:24:04.67#ibcon#read 6, iclass 40, count 0 2006.285.06:24:04.67#ibcon#end of sib2, iclass 40, count 0 2006.285.06:24:04.67#ibcon#*after write, iclass 40, count 0 2006.285.06:24:04.67#ibcon#*before return 0, iclass 40, count 0 2006.285.06:24:04.67#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:24:04.67#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:24:04.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:24:04.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:24:04.67$vck44/vabw=wide 2006.285.06:24:04.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.06:24:04.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.06:24:04.67#ibcon#ireg 8 cls_cnt 0 2006.285.06:24:04.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:24:04.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:24:04.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:24:04.67#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:24:04.67#ibcon#first serial, iclass 4, count 0 2006.285.06:24:04.67#ibcon#enter sib2, iclass 4, count 0 2006.285.06:24:04.67#ibcon#flushed, iclass 4, count 0 2006.285.06:24:04.67#ibcon#about to write, iclass 4, count 0 2006.285.06:24:04.67#ibcon#wrote, iclass 4, count 0 2006.285.06:24:04.67#ibcon#about to read 3, iclass 4, count 0 2006.285.06:24:04.69#ibcon#read 3, iclass 4, count 0 2006.285.06:24:04.69#ibcon#about to read 4, iclass 4, count 0 2006.285.06:24:04.69#ibcon#read 4, iclass 4, count 0 2006.285.06:24:04.69#ibcon#about to read 5, iclass 4, count 0 2006.285.06:24:04.69#ibcon#read 5, iclass 4, count 0 2006.285.06:24:04.69#ibcon#about to read 6, iclass 4, count 0 2006.285.06:24:04.69#ibcon#read 6, iclass 4, count 0 2006.285.06:24:04.69#ibcon#end of sib2, iclass 4, count 0 2006.285.06:24:04.69#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:24:04.69#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:24:04.69#ibcon#[25=BW32\r\n] 2006.285.06:24:04.69#ibcon#*before write, iclass 4, count 0 2006.285.06:24:04.69#ibcon#enter sib2, iclass 4, count 0 2006.285.06:24:04.69#ibcon#flushed, iclass 4, count 0 2006.285.06:24:04.69#ibcon#about to write, iclass 4, count 0 2006.285.06:24:04.69#ibcon#wrote, iclass 4, count 0 2006.285.06:24:04.69#ibcon#about to read 3, iclass 4, count 0 2006.285.06:24:04.72#ibcon#read 3, iclass 4, count 0 2006.285.06:24:04.72#ibcon#about to read 4, iclass 4, count 0 2006.285.06:24:04.72#ibcon#read 4, iclass 4, count 0 2006.285.06:24:04.72#ibcon#about to read 5, iclass 4, count 0 2006.285.06:24:04.72#ibcon#read 5, iclass 4, count 0 2006.285.06:24:04.72#ibcon#about to read 6, iclass 4, count 0 2006.285.06:24:04.72#ibcon#read 6, iclass 4, count 0 2006.285.06:24:04.72#ibcon#end of sib2, iclass 4, count 0 2006.285.06:24:04.72#ibcon#*after write, iclass 4, count 0 2006.285.06:24:04.72#ibcon#*before return 0, iclass 4, count 0 2006.285.06:24:04.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:24:04.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:24:04.72#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:24:04.72#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:24:04.72$vck44/vbbw=wide 2006.285.06:24:04.72#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.06:24:04.72#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.06:24:04.72#ibcon#ireg 8 cls_cnt 0 2006.285.06:24:04.72#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:24:04.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:24:04.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:24:04.79#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:24:04.79#ibcon#first serial, iclass 6, count 0 2006.285.06:24:04.79#ibcon#enter sib2, iclass 6, count 0 2006.285.06:24:04.79#ibcon#flushed, iclass 6, count 0 2006.285.06:24:04.79#ibcon#about to write, iclass 6, count 0 2006.285.06:24:04.79#ibcon#wrote, iclass 6, count 0 2006.285.06:24:04.79#ibcon#about to read 3, iclass 6, count 0 2006.285.06:24:04.81#ibcon#read 3, iclass 6, count 0 2006.285.06:24:04.81#ibcon#about to read 4, iclass 6, count 0 2006.285.06:24:04.81#ibcon#read 4, iclass 6, count 0 2006.285.06:24:04.81#ibcon#about to read 5, iclass 6, count 0 2006.285.06:24:04.81#ibcon#read 5, iclass 6, count 0 2006.285.06:24:04.81#ibcon#about to read 6, iclass 6, count 0 2006.285.06:24:04.81#ibcon#read 6, iclass 6, count 0 2006.285.06:24:04.81#ibcon#end of sib2, iclass 6, count 0 2006.285.06:24:04.81#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:24:04.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:24:04.81#ibcon#[27=BW32\r\n] 2006.285.06:24:04.81#ibcon#*before write, iclass 6, count 0 2006.285.06:24:04.81#ibcon#enter sib2, iclass 6, count 0 2006.285.06:24:04.81#ibcon#flushed, iclass 6, count 0 2006.285.06:24:04.81#ibcon#about to write, iclass 6, count 0 2006.285.06:24:04.81#ibcon#wrote, iclass 6, count 0 2006.285.06:24:04.81#ibcon#about to read 3, iclass 6, count 0 2006.285.06:24:04.84#ibcon#read 3, iclass 6, count 0 2006.285.06:24:04.84#ibcon#about to read 4, iclass 6, count 0 2006.285.06:24:04.84#ibcon#read 4, iclass 6, count 0 2006.285.06:24:04.84#ibcon#about to read 5, iclass 6, count 0 2006.285.06:24:04.84#ibcon#read 5, iclass 6, count 0 2006.285.06:24:04.84#ibcon#about to read 6, iclass 6, count 0 2006.285.06:24:04.84#ibcon#read 6, iclass 6, count 0 2006.285.06:24:04.84#ibcon#end of sib2, iclass 6, count 0 2006.285.06:24:04.84#ibcon#*after write, iclass 6, count 0 2006.285.06:24:04.84#ibcon#*before return 0, iclass 6, count 0 2006.285.06:24:04.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:24:04.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:24:04.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:24:04.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:24:04.84$setupk4/ifdk4 2006.285.06:24:04.84$ifdk4/lo= 2006.285.06:24:04.84$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:24:04.84$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:24:04.84$ifdk4/patch= 2006.285.06:24:04.84$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:24:04.84$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:24:04.84$setupk4/!*+20s 2006.285.06:24:14.05#abcon#<5=/05 4.6 7.3 24.96 691014.0\r\n> 2006.285.06:24:14.07#abcon#{5=INTERFACE CLEAR} 2006.285.06:24:14.13#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:24:18.13#trakl#Source acquired 2006.285.06:24:19.13#flagr#flagr/antenna,acquired 2006.285.06:24:19.33$setupk4/"tpicd 2006.285.06:24:19.33$setupk4/echo=off 2006.285.06:24:19.33$setupk4/xlog=off 2006.285.06:24:19.33:!2006.285.06:27:15 2006.285.06:27:15.02:preob 2006.285.06:27:16.14/onsource/TRACKING 2006.285.06:27:16.14:!2006.285.06:27:25 2006.285.06:27:25.02:"tape 2006.285.06:27:25.02:"st=record 2006.285.06:27:25.02:data_valid=on 2006.285.06:27:25.02:midob 2006.285.06:27:25.15/onsource/TRACKING 2006.285.06:27:25.15/wx/24.93,1014.0,67 2006.285.06:27:25.27/cable/+6.4743E-03 2006.285.06:27:26.37/va/01,07,usb,yes,34,37 2006.285.06:27:26.37/va/02,06,usb,yes,34,35 2006.285.06:27:26.37/va/03,07,usb,yes,34,35 2006.285.06:27:26.37/va/04,06,usb,yes,35,37 2006.285.06:27:26.37/va/05,03,usb,yes,35,35 2006.285.06:27:26.37/va/06,04,usb,yes,31,31 2006.285.06:27:26.37/va/07,04,usb,yes,32,33 2006.285.06:27:26.37/va/08,03,usb,yes,32,40 2006.285.06:27:26.60/valo/01,524.99,yes,locked 2006.285.06:27:26.60/valo/02,534.99,yes,locked 2006.285.06:27:26.60/valo/03,564.99,yes,locked 2006.285.06:27:26.60/valo/04,624.99,yes,locked 2006.285.06:27:26.60/valo/05,734.99,yes,locked 2006.285.06:27:26.60/valo/06,814.99,yes,locked 2006.285.06:27:26.60/valo/07,864.99,yes,locked 2006.285.06:27:26.60/valo/08,884.99,yes,locked 2006.285.06:27:27.69/vb/01,04,usb,yes,32,30 2006.285.06:27:27.69/vb/02,05,usb,yes,31,30 2006.285.06:27:27.69/vb/03,04,usb,yes,32,35 2006.285.06:27:27.69/vb/04,05,usb,yes,32,31 2006.285.06:27:27.69/vb/05,04,usb,yes,29,31 2006.285.06:27:27.69/vb/06,03,usb,yes,41,36 2006.285.06:27:27.69/vb/07,04,usb,yes,33,33 2006.285.06:27:27.69/vb/08,04,usb,yes,30,34 2006.285.06:27:27.92/vblo/01,629.99,yes,locked 2006.285.06:27:27.92/vblo/02,634.99,yes,locked 2006.285.06:27:27.92/vblo/03,649.99,yes,locked 2006.285.06:27:27.92/vblo/04,679.99,yes,locked 2006.285.06:27:27.92/vblo/05,709.99,yes,locked 2006.285.06:27:27.92/vblo/06,719.99,yes,locked 2006.285.06:27:27.92/vblo/07,734.99,yes,locked 2006.285.06:27:27.92/vblo/08,744.99,yes,locked 2006.285.06:27:28.07/vabw/8 2006.285.06:27:28.22/vbbw/8 2006.285.06:27:28.31/xfe/off,on,12.2 2006.285.06:27:28.68/ifatt/23,28,28,28 2006.285.06:27:29.07/fmout-gps/S +2.53E-07 2006.285.06:27:29.09:!2006.285.06:29:35 2006.285.06:29:35.00:data_valid=off 2006.285.06:29:35.00:"et 2006.285.06:29:35.01:!+3s 2006.285.06:29:38.03:"tape 2006.285.06:29:38.03:postob 2006.285.06:29:38.15/cable/+6.4742E-03 2006.285.06:29:38.15/wx/24.90,1014.0,68 2006.285.06:29:38.21/fmout-gps/S +2.56E-07 2006.285.06:29:38.21:scan_name=285-0630,jd0610,40 2006.285.06:29:38.22:source=1954-388,195800.00,-384506.4,2000.0,cw 2006.285.06:29:39.14#flagr#flagr/antenna,new-source 2006.285.06:29:39.15:checkk5 2006.285.06:29:39.62/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:29:40.00/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:29:40.43/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:29:40.85/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:29:41.30/chk_obsdata//k5ts1/T2850627??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.285.06:29:41.71/chk_obsdata//k5ts2/T2850627??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.285.06:29:42.10/chk_obsdata//k5ts3/T2850627??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.285.06:29:42.50/chk_obsdata//k5ts4/T2850627??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.285.06:29:43.28/k5log//k5ts1_log_newline 2006.285.06:29:44.07/k5log//k5ts2_log_newline 2006.285.06:29:44.82/k5log//k5ts3_log_newline 2006.285.06:29:45.84/k5log//k5ts4_log_newline 2006.285.06:29:45.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:29:45.87:setupk4=1 2006.285.06:29:45.87$setupk4/echo=on 2006.285.06:29:45.87$setupk4/pcalon 2006.285.06:29:45.87$pcalon/"no phase cal control is implemented here 2006.285.06:29:45.87$setupk4/"tpicd=stop 2006.285.06:29:45.87$setupk4/"rec=synch_on 2006.285.06:29:45.87$setupk4/"rec_mode=128 2006.285.06:29:45.87$setupk4/!* 2006.285.06:29:45.87$setupk4/recpk4 2006.285.06:29:45.87$recpk4/recpatch= 2006.285.06:29:45.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:29:45.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:29:45.87$setupk4/vck44 2006.285.06:29:45.87$vck44/valo=1,524.99 2006.285.06:29:45.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.06:29:45.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.06:29:45.87#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:45.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:29:45.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:29:45.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:29:45.87#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:29:45.87#ibcon#first serial, iclass 32, count 0 2006.285.06:29:45.87#ibcon#enter sib2, iclass 32, count 0 2006.285.06:29:45.87#ibcon#flushed, iclass 32, count 0 2006.285.06:29:45.87#ibcon#about to write, iclass 32, count 0 2006.285.06:29:45.87#ibcon#wrote, iclass 32, count 0 2006.285.06:29:45.87#ibcon#about to read 3, iclass 32, count 0 2006.285.06:29:45.88#ibcon#read 3, iclass 32, count 0 2006.285.06:29:45.88#ibcon#about to read 4, iclass 32, count 0 2006.285.06:29:45.88#ibcon#read 4, iclass 32, count 0 2006.285.06:29:45.88#ibcon#about to read 5, iclass 32, count 0 2006.285.06:29:45.88#ibcon#read 5, iclass 32, count 0 2006.285.06:29:45.88#ibcon#about to read 6, iclass 32, count 0 2006.285.06:29:45.88#ibcon#read 6, iclass 32, count 0 2006.285.06:29:45.88#ibcon#end of sib2, iclass 32, count 0 2006.285.06:29:45.88#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:29:45.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:29:45.88#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:29:45.88#ibcon#*before write, iclass 32, count 0 2006.285.06:29:45.88#ibcon#enter sib2, iclass 32, count 0 2006.285.06:29:45.88#ibcon#flushed, iclass 32, count 0 2006.285.06:29:45.88#ibcon#about to write, iclass 32, count 0 2006.285.06:29:45.88#ibcon#wrote, iclass 32, count 0 2006.285.06:29:45.88#ibcon#about to read 3, iclass 32, count 0 2006.285.06:29:45.93#ibcon#read 3, iclass 32, count 0 2006.285.06:29:45.93#ibcon#about to read 4, iclass 32, count 0 2006.285.06:29:45.93#ibcon#read 4, iclass 32, count 0 2006.285.06:29:45.93#ibcon#about to read 5, iclass 32, count 0 2006.285.06:29:45.93#ibcon#read 5, iclass 32, count 0 2006.285.06:29:45.93#ibcon#about to read 6, iclass 32, count 0 2006.285.06:29:45.93#ibcon#read 6, iclass 32, count 0 2006.285.06:29:45.93#ibcon#end of sib2, iclass 32, count 0 2006.285.06:29:45.93#ibcon#*after write, iclass 32, count 0 2006.285.06:29:45.93#ibcon#*before return 0, iclass 32, count 0 2006.285.06:29:45.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:29:45.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:29:45.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:29:45.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:29:45.93$vck44/va=1,7 2006.285.06:29:45.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.06:29:45.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.06:29:45.93#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:45.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:29:45.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:29:45.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:29:45.93#ibcon#enter wrdev, iclass 34, count 2 2006.285.06:29:45.93#ibcon#first serial, iclass 34, count 2 2006.285.06:29:45.93#ibcon#enter sib2, iclass 34, count 2 2006.285.06:29:45.93#ibcon#flushed, iclass 34, count 2 2006.285.06:29:45.93#ibcon#about to write, iclass 34, count 2 2006.285.06:29:45.93#ibcon#wrote, iclass 34, count 2 2006.285.06:29:45.93#ibcon#about to read 3, iclass 34, count 2 2006.285.06:29:45.95#ibcon#read 3, iclass 34, count 2 2006.285.06:29:45.95#ibcon#about to read 4, iclass 34, count 2 2006.285.06:29:45.95#ibcon#read 4, iclass 34, count 2 2006.285.06:29:45.95#ibcon#about to read 5, iclass 34, count 2 2006.285.06:29:45.95#ibcon#read 5, iclass 34, count 2 2006.285.06:29:45.95#ibcon#about to read 6, iclass 34, count 2 2006.285.06:29:45.95#ibcon#read 6, iclass 34, count 2 2006.285.06:29:45.95#ibcon#end of sib2, iclass 34, count 2 2006.285.06:29:45.95#ibcon#*mode == 0, iclass 34, count 2 2006.285.06:29:45.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.06:29:45.95#ibcon#[25=AT01-07\r\n] 2006.285.06:29:45.95#ibcon#*before write, iclass 34, count 2 2006.285.06:29:45.95#ibcon#enter sib2, iclass 34, count 2 2006.285.06:29:45.95#ibcon#flushed, iclass 34, count 2 2006.285.06:29:45.95#ibcon#about to write, iclass 34, count 2 2006.285.06:29:45.95#ibcon#wrote, iclass 34, count 2 2006.285.06:29:45.95#ibcon#about to read 3, iclass 34, count 2 2006.285.06:29:45.98#ibcon#read 3, iclass 34, count 2 2006.285.06:29:45.98#ibcon#about to read 4, iclass 34, count 2 2006.285.06:29:45.98#ibcon#read 4, iclass 34, count 2 2006.285.06:29:45.98#ibcon#about to read 5, iclass 34, count 2 2006.285.06:29:45.98#ibcon#read 5, iclass 34, count 2 2006.285.06:29:45.98#ibcon#about to read 6, iclass 34, count 2 2006.285.06:29:45.98#ibcon#read 6, iclass 34, count 2 2006.285.06:29:45.98#ibcon#end of sib2, iclass 34, count 2 2006.285.06:29:45.98#ibcon#*after write, iclass 34, count 2 2006.285.06:29:45.98#ibcon#*before return 0, iclass 34, count 2 2006.285.06:29:45.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:29:45.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:29:45.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.06:29:45.98#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:45.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:29:46.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:29:46.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:29:46.10#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:29:46.10#ibcon#first serial, iclass 34, count 0 2006.285.06:29:46.10#ibcon#enter sib2, iclass 34, count 0 2006.285.06:29:46.10#ibcon#flushed, iclass 34, count 0 2006.285.06:29:46.10#ibcon#about to write, iclass 34, count 0 2006.285.06:29:46.10#ibcon#wrote, iclass 34, count 0 2006.285.06:29:46.10#ibcon#about to read 3, iclass 34, count 0 2006.285.06:29:46.12#ibcon#read 3, iclass 34, count 0 2006.285.06:29:46.12#ibcon#about to read 4, iclass 34, count 0 2006.285.06:29:46.12#ibcon#read 4, iclass 34, count 0 2006.285.06:29:46.12#ibcon#about to read 5, iclass 34, count 0 2006.285.06:29:46.12#ibcon#read 5, iclass 34, count 0 2006.285.06:29:46.12#ibcon#about to read 6, iclass 34, count 0 2006.285.06:29:46.12#ibcon#read 6, iclass 34, count 0 2006.285.06:29:46.12#ibcon#end of sib2, iclass 34, count 0 2006.285.06:29:46.12#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:29:46.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:29:46.12#ibcon#[25=USB\r\n] 2006.285.06:29:46.12#ibcon#*before write, iclass 34, count 0 2006.285.06:29:46.12#ibcon#enter sib2, iclass 34, count 0 2006.285.06:29:46.12#ibcon#flushed, iclass 34, count 0 2006.285.06:29:46.12#ibcon#about to write, iclass 34, count 0 2006.285.06:29:46.12#ibcon#wrote, iclass 34, count 0 2006.285.06:29:46.12#ibcon#about to read 3, iclass 34, count 0 2006.285.06:29:46.15#ibcon#read 3, iclass 34, count 0 2006.285.06:29:46.15#ibcon#about to read 4, iclass 34, count 0 2006.285.06:29:46.15#ibcon#read 4, iclass 34, count 0 2006.285.06:29:46.15#ibcon#about to read 5, iclass 34, count 0 2006.285.06:29:46.15#ibcon#read 5, iclass 34, count 0 2006.285.06:29:46.15#ibcon#about to read 6, iclass 34, count 0 2006.285.06:29:46.15#ibcon#read 6, iclass 34, count 0 2006.285.06:29:46.15#ibcon#end of sib2, iclass 34, count 0 2006.285.06:29:46.15#ibcon#*after write, iclass 34, count 0 2006.285.06:29:46.15#ibcon#*before return 0, iclass 34, count 0 2006.285.06:29:46.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:29:46.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:29:46.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:29:46.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:29:46.15$vck44/valo=2,534.99 2006.285.06:29:46.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.06:29:46.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.06:29:46.15#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:46.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:29:46.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:29:46.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:29:46.15#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:29:46.15#ibcon#first serial, iclass 36, count 0 2006.285.06:29:46.15#ibcon#enter sib2, iclass 36, count 0 2006.285.06:29:46.15#ibcon#flushed, iclass 36, count 0 2006.285.06:29:46.15#ibcon#about to write, iclass 36, count 0 2006.285.06:29:46.15#ibcon#wrote, iclass 36, count 0 2006.285.06:29:46.15#ibcon#about to read 3, iclass 36, count 0 2006.285.06:29:46.17#ibcon#read 3, iclass 36, count 0 2006.285.06:29:46.17#ibcon#about to read 4, iclass 36, count 0 2006.285.06:29:46.17#ibcon#read 4, iclass 36, count 0 2006.285.06:29:46.17#ibcon#about to read 5, iclass 36, count 0 2006.285.06:29:46.17#ibcon#read 5, iclass 36, count 0 2006.285.06:29:46.17#ibcon#about to read 6, iclass 36, count 0 2006.285.06:29:46.17#ibcon#read 6, iclass 36, count 0 2006.285.06:29:46.17#ibcon#end of sib2, iclass 36, count 0 2006.285.06:29:46.17#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:29:46.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:29:46.17#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:29:46.17#ibcon#*before write, iclass 36, count 0 2006.285.06:29:46.17#ibcon#enter sib2, iclass 36, count 0 2006.285.06:29:46.17#ibcon#flushed, iclass 36, count 0 2006.285.06:29:46.17#ibcon#about to write, iclass 36, count 0 2006.285.06:29:46.17#ibcon#wrote, iclass 36, count 0 2006.285.06:29:46.17#ibcon#about to read 3, iclass 36, count 0 2006.285.06:29:46.21#ibcon#read 3, iclass 36, count 0 2006.285.06:29:46.21#ibcon#about to read 4, iclass 36, count 0 2006.285.06:29:46.21#ibcon#read 4, iclass 36, count 0 2006.285.06:29:46.21#ibcon#about to read 5, iclass 36, count 0 2006.285.06:29:46.21#ibcon#read 5, iclass 36, count 0 2006.285.06:29:46.21#ibcon#about to read 6, iclass 36, count 0 2006.285.06:29:46.21#ibcon#read 6, iclass 36, count 0 2006.285.06:29:46.21#ibcon#end of sib2, iclass 36, count 0 2006.285.06:29:46.21#ibcon#*after write, iclass 36, count 0 2006.285.06:29:46.21#ibcon#*before return 0, iclass 36, count 0 2006.285.06:29:46.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:29:46.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:29:46.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:29:46.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:29:46.21$vck44/va=2,6 2006.285.06:29:46.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.06:29:46.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.06:29:46.21#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:46.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:29:46.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:29:46.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:29:46.27#ibcon#enter wrdev, iclass 38, count 2 2006.285.06:29:46.27#ibcon#first serial, iclass 38, count 2 2006.285.06:29:46.27#ibcon#enter sib2, iclass 38, count 2 2006.285.06:29:46.27#ibcon#flushed, iclass 38, count 2 2006.285.06:29:46.27#ibcon#about to write, iclass 38, count 2 2006.285.06:29:46.27#ibcon#wrote, iclass 38, count 2 2006.285.06:29:46.27#ibcon#about to read 3, iclass 38, count 2 2006.285.06:29:46.29#ibcon#read 3, iclass 38, count 2 2006.285.06:29:46.29#ibcon#about to read 4, iclass 38, count 2 2006.285.06:29:46.29#ibcon#read 4, iclass 38, count 2 2006.285.06:29:46.29#ibcon#about to read 5, iclass 38, count 2 2006.285.06:29:46.29#ibcon#read 5, iclass 38, count 2 2006.285.06:29:46.29#ibcon#about to read 6, iclass 38, count 2 2006.285.06:29:46.29#ibcon#read 6, iclass 38, count 2 2006.285.06:29:46.29#ibcon#end of sib2, iclass 38, count 2 2006.285.06:29:46.29#ibcon#*mode == 0, iclass 38, count 2 2006.285.06:29:46.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.06:29:46.29#ibcon#[25=AT02-06\r\n] 2006.285.06:29:46.29#ibcon#*before write, iclass 38, count 2 2006.285.06:29:46.29#ibcon#enter sib2, iclass 38, count 2 2006.285.06:29:46.29#ibcon#flushed, iclass 38, count 2 2006.285.06:29:46.29#ibcon#about to write, iclass 38, count 2 2006.285.06:29:46.29#ibcon#wrote, iclass 38, count 2 2006.285.06:29:46.29#ibcon#about to read 3, iclass 38, count 2 2006.285.06:29:46.32#ibcon#read 3, iclass 38, count 2 2006.285.06:29:46.32#ibcon#about to read 4, iclass 38, count 2 2006.285.06:29:46.32#ibcon#read 4, iclass 38, count 2 2006.285.06:29:46.32#ibcon#about to read 5, iclass 38, count 2 2006.285.06:29:46.32#ibcon#read 5, iclass 38, count 2 2006.285.06:29:46.32#ibcon#about to read 6, iclass 38, count 2 2006.285.06:29:46.32#ibcon#read 6, iclass 38, count 2 2006.285.06:29:46.32#ibcon#end of sib2, iclass 38, count 2 2006.285.06:29:46.32#ibcon#*after write, iclass 38, count 2 2006.285.06:29:46.32#ibcon#*before return 0, iclass 38, count 2 2006.285.06:29:46.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:29:46.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:29:46.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.06:29:46.32#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:46.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:29:46.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:29:46.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:29:46.44#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:29:46.44#ibcon#first serial, iclass 38, count 0 2006.285.06:29:46.44#ibcon#enter sib2, iclass 38, count 0 2006.285.06:29:46.44#ibcon#flushed, iclass 38, count 0 2006.285.06:29:46.44#ibcon#about to write, iclass 38, count 0 2006.285.06:29:46.44#ibcon#wrote, iclass 38, count 0 2006.285.06:29:46.44#ibcon#about to read 3, iclass 38, count 0 2006.285.06:29:46.46#ibcon#read 3, iclass 38, count 0 2006.285.06:29:46.46#ibcon#about to read 4, iclass 38, count 0 2006.285.06:29:46.46#ibcon#read 4, iclass 38, count 0 2006.285.06:29:46.46#ibcon#about to read 5, iclass 38, count 0 2006.285.06:29:46.46#ibcon#read 5, iclass 38, count 0 2006.285.06:29:46.46#ibcon#about to read 6, iclass 38, count 0 2006.285.06:29:46.46#ibcon#read 6, iclass 38, count 0 2006.285.06:29:46.46#ibcon#end of sib2, iclass 38, count 0 2006.285.06:29:46.46#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:29:46.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:29:46.46#ibcon#[25=USB\r\n] 2006.285.06:29:46.46#ibcon#*before write, iclass 38, count 0 2006.285.06:29:46.46#ibcon#enter sib2, iclass 38, count 0 2006.285.06:29:46.46#ibcon#flushed, iclass 38, count 0 2006.285.06:29:46.46#ibcon#about to write, iclass 38, count 0 2006.285.06:29:46.46#ibcon#wrote, iclass 38, count 0 2006.285.06:29:46.46#ibcon#about to read 3, iclass 38, count 0 2006.285.06:29:46.49#ibcon#read 3, iclass 38, count 0 2006.285.06:29:46.49#ibcon#about to read 4, iclass 38, count 0 2006.285.06:29:46.49#ibcon#read 4, iclass 38, count 0 2006.285.06:29:46.49#ibcon#about to read 5, iclass 38, count 0 2006.285.06:29:46.49#ibcon#read 5, iclass 38, count 0 2006.285.06:29:46.49#ibcon#about to read 6, iclass 38, count 0 2006.285.06:29:46.49#ibcon#read 6, iclass 38, count 0 2006.285.06:29:46.49#ibcon#end of sib2, iclass 38, count 0 2006.285.06:29:46.49#ibcon#*after write, iclass 38, count 0 2006.285.06:29:46.49#ibcon#*before return 0, iclass 38, count 0 2006.285.06:29:46.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:29:46.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:29:46.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:29:46.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:29:46.49$vck44/valo=3,564.99 2006.285.06:29:46.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.06:29:46.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.06:29:46.49#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:46.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:29:46.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:29:46.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:29:46.49#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:29:46.49#ibcon#first serial, iclass 40, count 0 2006.285.06:29:46.49#ibcon#enter sib2, iclass 40, count 0 2006.285.06:29:46.49#ibcon#flushed, iclass 40, count 0 2006.285.06:29:46.49#ibcon#about to write, iclass 40, count 0 2006.285.06:29:46.49#ibcon#wrote, iclass 40, count 0 2006.285.06:29:46.49#ibcon#about to read 3, iclass 40, count 0 2006.285.06:29:46.51#ibcon#read 3, iclass 40, count 0 2006.285.06:29:46.51#ibcon#about to read 4, iclass 40, count 0 2006.285.06:29:46.51#ibcon#read 4, iclass 40, count 0 2006.285.06:29:46.51#ibcon#about to read 5, iclass 40, count 0 2006.285.06:29:46.51#ibcon#read 5, iclass 40, count 0 2006.285.06:29:46.51#ibcon#about to read 6, iclass 40, count 0 2006.285.06:29:46.51#ibcon#read 6, iclass 40, count 0 2006.285.06:29:46.51#ibcon#end of sib2, iclass 40, count 0 2006.285.06:29:46.51#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:29:46.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:29:46.51#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:29:46.51#ibcon#*before write, iclass 40, count 0 2006.285.06:29:46.51#ibcon#enter sib2, iclass 40, count 0 2006.285.06:29:46.51#ibcon#flushed, iclass 40, count 0 2006.285.06:29:46.51#ibcon#about to write, iclass 40, count 0 2006.285.06:29:46.51#ibcon#wrote, iclass 40, count 0 2006.285.06:29:46.51#ibcon#about to read 3, iclass 40, count 0 2006.285.06:29:46.55#ibcon#read 3, iclass 40, count 0 2006.285.06:29:46.55#ibcon#about to read 4, iclass 40, count 0 2006.285.06:29:46.55#ibcon#read 4, iclass 40, count 0 2006.285.06:29:46.55#ibcon#about to read 5, iclass 40, count 0 2006.285.06:29:46.55#ibcon#read 5, iclass 40, count 0 2006.285.06:29:46.55#ibcon#about to read 6, iclass 40, count 0 2006.285.06:29:46.55#ibcon#read 6, iclass 40, count 0 2006.285.06:29:46.55#ibcon#end of sib2, iclass 40, count 0 2006.285.06:29:46.55#ibcon#*after write, iclass 40, count 0 2006.285.06:29:46.55#ibcon#*before return 0, iclass 40, count 0 2006.285.06:29:46.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:29:46.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:29:46.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:29:46.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:29:46.55$vck44/va=3,7 2006.285.06:29:46.55#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.06:29:46.55#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.06:29:46.55#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:46.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:29:46.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:29:46.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:29:46.61#ibcon#enter wrdev, iclass 4, count 2 2006.285.06:29:46.61#ibcon#first serial, iclass 4, count 2 2006.285.06:29:46.61#ibcon#enter sib2, iclass 4, count 2 2006.285.06:29:46.61#ibcon#flushed, iclass 4, count 2 2006.285.06:29:46.61#ibcon#about to write, iclass 4, count 2 2006.285.06:29:46.61#ibcon#wrote, iclass 4, count 2 2006.285.06:29:46.61#ibcon#about to read 3, iclass 4, count 2 2006.285.06:29:46.64#ibcon#read 3, iclass 4, count 2 2006.285.06:29:46.64#ibcon#about to read 4, iclass 4, count 2 2006.285.06:29:46.64#ibcon#read 4, iclass 4, count 2 2006.285.06:29:46.64#ibcon#about to read 5, iclass 4, count 2 2006.285.06:29:46.64#ibcon#read 5, iclass 4, count 2 2006.285.06:29:46.64#ibcon#about to read 6, iclass 4, count 2 2006.285.06:29:46.64#ibcon#read 6, iclass 4, count 2 2006.285.06:29:46.64#ibcon#end of sib2, iclass 4, count 2 2006.285.06:29:46.64#ibcon#*mode == 0, iclass 4, count 2 2006.285.06:29:46.64#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.06:29:46.64#ibcon#[25=AT03-07\r\n] 2006.285.06:29:46.64#ibcon#*before write, iclass 4, count 2 2006.285.06:29:46.64#ibcon#enter sib2, iclass 4, count 2 2006.285.06:29:46.64#ibcon#flushed, iclass 4, count 2 2006.285.06:29:46.64#ibcon#about to write, iclass 4, count 2 2006.285.06:29:46.64#ibcon#wrote, iclass 4, count 2 2006.285.06:29:46.64#ibcon#about to read 3, iclass 4, count 2 2006.285.06:29:46.67#ibcon#read 3, iclass 4, count 2 2006.285.06:29:46.67#ibcon#about to read 4, iclass 4, count 2 2006.285.06:29:46.67#ibcon#read 4, iclass 4, count 2 2006.285.06:29:46.67#ibcon#about to read 5, iclass 4, count 2 2006.285.06:29:46.67#ibcon#read 5, iclass 4, count 2 2006.285.06:29:46.67#ibcon#about to read 6, iclass 4, count 2 2006.285.06:29:46.67#ibcon#read 6, iclass 4, count 2 2006.285.06:29:46.67#ibcon#end of sib2, iclass 4, count 2 2006.285.06:29:46.67#ibcon#*after write, iclass 4, count 2 2006.285.06:29:46.67#ibcon#*before return 0, iclass 4, count 2 2006.285.06:29:46.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:29:46.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:29:46.67#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.06:29:46.67#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:46.67#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:29:46.79#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:29:46.79#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:29:46.79#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:29:46.79#ibcon#first serial, iclass 4, count 0 2006.285.06:29:46.79#ibcon#enter sib2, iclass 4, count 0 2006.285.06:29:46.79#ibcon#flushed, iclass 4, count 0 2006.285.06:29:46.79#ibcon#about to write, iclass 4, count 0 2006.285.06:29:46.79#ibcon#wrote, iclass 4, count 0 2006.285.06:29:46.79#ibcon#about to read 3, iclass 4, count 0 2006.285.06:29:46.81#ibcon#read 3, iclass 4, count 0 2006.285.06:29:46.81#ibcon#about to read 4, iclass 4, count 0 2006.285.06:29:46.81#ibcon#read 4, iclass 4, count 0 2006.285.06:29:46.81#ibcon#about to read 5, iclass 4, count 0 2006.285.06:29:46.81#ibcon#read 5, iclass 4, count 0 2006.285.06:29:46.81#ibcon#about to read 6, iclass 4, count 0 2006.285.06:29:46.81#ibcon#read 6, iclass 4, count 0 2006.285.06:29:46.81#ibcon#end of sib2, iclass 4, count 0 2006.285.06:29:46.81#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:29:46.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:29:46.81#ibcon#[25=USB\r\n] 2006.285.06:29:46.81#ibcon#*before write, iclass 4, count 0 2006.285.06:29:46.81#ibcon#enter sib2, iclass 4, count 0 2006.285.06:29:46.81#ibcon#flushed, iclass 4, count 0 2006.285.06:29:46.81#ibcon#about to write, iclass 4, count 0 2006.285.06:29:46.81#ibcon#wrote, iclass 4, count 0 2006.285.06:29:46.81#ibcon#about to read 3, iclass 4, count 0 2006.285.06:29:46.84#ibcon#read 3, iclass 4, count 0 2006.285.06:29:46.84#ibcon#about to read 4, iclass 4, count 0 2006.285.06:29:46.84#ibcon#read 4, iclass 4, count 0 2006.285.06:29:46.84#ibcon#about to read 5, iclass 4, count 0 2006.285.06:29:46.84#ibcon#read 5, iclass 4, count 0 2006.285.06:29:46.84#ibcon#about to read 6, iclass 4, count 0 2006.285.06:29:46.84#ibcon#read 6, iclass 4, count 0 2006.285.06:29:46.84#ibcon#end of sib2, iclass 4, count 0 2006.285.06:29:46.84#ibcon#*after write, iclass 4, count 0 2006.285.06:29:46.84#ibcon#*before return 0, iclass 4, count 0 2006.285.06:29:46.84#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:29:46.84#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:29:46.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:29:46.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:29:46.84$vck44/valo=4,624.99 2006.285.06:29:46.84#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.06:29:46.84#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.06:29:46.84#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:46.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:29:46.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:29:46.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:29:46.84#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:29:46.84#ibcon#first serial, iclass 6, count 0 2006.285.06:29:46.84#ibcon#enter sib2, iclass 6, count 0 2006.285.06:29:46.84#ibcon#flushed, iclass 6, count 0 2006.285.06:29:46.84#ibcon#about to write, iclass 6, count 0 2006.285.06:29:46.84#ibcon#wrote, iclass 6, count 0 2006.285.06:29:46.84#ibcon#about to read 3, iclass 6, count 0 2006.285.06:29:46.86#ibcon#read 3, iclass 6, count 0 2006.285.06:29:46.86#ibcon#about to read 4, iclass 6, count 0 2006.285.06:29:46.86#ibcon#read 4, iclass 6, count 0 2006.285.06:29:46.86#ibcon#about to read 5, iclass 6, count 0 2006.285.06:29:46.86#ibcon#read 5, iclass 6, count 0 2006.285.06:29:46.86#ibcon#about to read 6, iclass 6, count 0 2006.285.06:29:46.86#ibcon#read 6, iclass 6, count 0 2006.285.06:29:46.86#ibcon#end of sib2, iclass 6, count 0 2006.285.06:29:46.86#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:29:46.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:29:46.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:29:46.86#ibcon#*before write, iclass 6, count 0 2006.285.06:29:46.86#ibcon#enter sib2, iclass 6, count 0 2006.285.06:29:46.86#ibcon#flushed, iclass 6, count 0 2006.285.06:29:46.86#ibcon#about to write, iclass 6, count 0 2006.285.06:29:46.86#ibcon#wrote, iclass 6, count 0 2006.285.06:29:46.86#ibcon#about to read 3, iclass 6, count 0 2006.285.06:29:46.90#ibcon#read 3, iclass 6, count 0 2006.285.06:29:46.90#ibcon#about to read 4, iclass 6, count 0 2006.285.06:29:46.90#ibcon#read 4, iclass 6, count 0 2006.285.06:29:46.90#ibcon#about to read 5, iclass 6, count 0 2006.285.06:29:46.90#ibcon#read 5, iclass 6, count 0 2006.285.06:29:46.90#ibcon#about to read 6, iclass 6, count 0 2006.285.06:29:46.90#ibcon#read 6, iclass 6, count 0 2006.285.06:29:46.90#ibcon#end of sib2, iclass 6, count 0 2006.285.06:29:46.90#ibcon#*after write, iclass 6, count 0 2006.285.06:29:46.90#ibcon#*before return 0, iclass 6, count 0 2006.285.06:29:46.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:29:46.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:29:46.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:29:46.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:29:46.90$vck44/va=4,6 2006.285.06:29:46.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.06:29:46.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.06:29:46.90#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:46.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:29:46.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:29:46.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:29:46.96#ibcon#enter wrdev, iclass 10, count 2 2006.285.06:29:46.96#ibcon#first serial, iclass 10, count 2 2006.285.06:29:46.96#ibcon#enter sib2, iclass 10, count 2 2006.285.06:29:46.96#ibcon#flushed, iclass 10, count 2 2006.285.06:29:46.96#ibcon#about to write, iclass 10, count 2 2006.285.06:29:46.96#ibcon#wrote, iclass 10, count 2 2006.285.06:29:46.96#ibcon#about to read 3, iclass 10, count 2 2006.285.06:29:46.98#ibcon#read 3, iclass 10, count 2 2006.285.06:29:46.98#ibcon#about to read 4, iclass 10, count 2 2006.285.06:29:46.98#ibcon#read 4, iclass 10, count 2 2006.285.06:29:46.98#ibcon#about to read 5, iclass 10, count 2 2006.285.06:29:46.98#ibcon#read 5, iclass 10, count 2 2006.285.06:29:46.98#ibcon#about to read 6, iclass 10, count 2 2006.285.06:29:46.98#ibcon#read 6, iclass 10, count 2 2006.285.06:29:46.98#ibcon#end of sib2, iclass 10, count 2 2006.285.06:29:46.98#ibcon#*mode == 0, iclass 10, count 2 2006.285.06:29:46.98#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.06:29:46.98#ibcon#[25=AT04-06\r\n] 2006.285.06:29:46.98#ibcon#*before write, iclass 10, count 2 2006.285.06:29:46.98#ibcon#enter sib2, iclass 10, count 2 2006.285.06:29:46.98#ibcon#flushed, iclass 10, count 2 2006.285.06:29:46.98#ibcon#about to write, iclass 10, count 2 2006.285.06:29:46.98#ibcon#wrote, iclass 10, count 2 2006.285.06:29:46.98#ibcon#about to read 3, iclass 10, count 2 2006.285.06:29:47.01#ibcon#read 3, iclass 10, count 2 2006.285.06:29:47.01#ibcon#about to read 4, iclass 10, count 2 2006.285.06:29:47.01#ibcon#read 4, iclass 10, count 2 2006.285.06:29:47.01#ibcon#about to read 5, iclass 10, count 2 2006.285.06:29:47.01#ibcon#read 5, iclass 10, count 2 2006.285.06:29:47.01#ibcon#about to read 6, iclass 10, count 2 2006.285.06:29:47.01#ibcon#read 6, iclass 10, count 2 2006.285.06:29:47.01#ibcon#end of sib2, iclass 10, count 2 2006.285.06:29:47.01#ibcon#*after write, iclass 10, count 2 2006.285.06:29:47.01#ibcon#*before return 0, iclass 10, count 2 2006.285.06:29:47.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:29:47.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:29:47.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.06:29:47.01#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:47.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:29:47.13#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:29:47.13#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:29:47.13#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:29:47.13#ibcon#first serial, iclass 10, count 0 2006.285.06:29:47.13#ibcon#enter sib2, iclass 10, count 0 2006.285.06:29:47.13#ibcon#flushed, iclass 10, count 0 2006.285.06:29:47.13#ibcon#about to write, iclass 10, count 0 2006.285.06:29:47.13#ibcon#wrote, iclass 10, count 0 2006.285.06:29:47.13#ibcon#about to read 3, iclass 10, count 0 2006.285.06:29:47.15#ibcon#read 3, iclass 10, count 0 2006.285.06:29:47.15#ibcon#about to read 4, iclass 10, count 0 2006.285.06:29:47.15#ibcon#read 4, iclass 10, count 0 2006.285.06:29:47.15#ibcon#about to read 5, iclass 10, count 0 2006.285.06:29:47.15#ibcon#read 5, iclass 10, count 0 2006.285.06:29:47.15#ibcon#about to read 6, iclass 10, count 0 2006.285.06:29:47.15#ibcon#read 6, iclass 10, count 0 2006.285.06:29:47.15#ibcon#end of sib2, iclass 10, count 0 2006.285.06:29:47.15#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:29:47.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:29:47.15#ibcon#[25=USB\r\n] 2006.285.06:29:47.15#ibcon#*before write, iclass 10, count 0 2006.285.06:29:47.15#ibcon#enter sib2, iclass 10, count 0 2006.285.06:29:47.15#ibcon#flushed, iclass 10, count 0 2006.285.06:29:47.15#ibcon#about to write, iclass 10, count 0 2006.285.06:29:47.15#ibcon#wrote, iclass 10, count 0 2006.285.06:29:47.15#ibcon#about to read 3, iclass 10, count 0 2006.285.06:29:47.18#ibcon#read 3, iclass 10, count 0 2006.285.06:29:47.18#ibcon#about to read 4, iclass 10, count 0 2006.285.06:29:47.18#ibcon#read 4, iclass 10, count 0 2006.285.06:29:47.18#ibcon#about to read 5, iclass 10, count 0 2006.285.06:29:47.18#ibcon#read 5, iclass 10, count 0 2006.285.06:29:47.18#ibcon#about to read 6, iclass 10, count 0 2006.285.06:29:47.18#ibcon#read 6, iclass 10, count 0 2006.285.06:29:47.18#ibcon#end of sib2, iclass 10, count 0 2006.285.06:29:47.18#ibcon#*after write, iclass 10, count 0 2006.285.06:29:47.18#ibcon#*before return 0, iclass 10, count 0 2006.285.06:29:47.18#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:29:47.18#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:29:47.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:29:47.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:29:47.18$vck44/valo=5,734.99 2006.285.06:29:47.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.06:29:47.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.06:29:47.18#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:47.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:29:47.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:29:47.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:29:47.18#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:29:47.18#ibcon#first serial, iclass 12, count 0 2006.285.06:29:47.18#ibcon#enter sib2, iclass 12, count 0 2006.285.06:29:47.18#ibcon#flushed, iclass 12, count 0 2006.285.06:29:47.18#ibcon#about to write, iclass 12, count 0 2006.285.06:29:47.18#ibcon#wrote, iclass 12, count 0 2006.285.06:29:47.18#ibcon#about to read 3, iclass 12, count 0 2006.285.06:29:47.20#ibcon#read 3, iclass 12, count 0 2006.285.06:29:47.20#ibcon#about to read 4, iclass 12, count 0 2006.285.06:29:47.20#ibcon#read 4, iclass 12, count 0 2006.285.06:29:47.20#ibcon#about to read 5, iclass 12, count 0 2006.285.06:29:47.20#ibcon#read 5, iclass 12, count 0 2006.285.06:29:47.20#ibcon#about to read 6, iclass 12, count 0 2006.285.06:29:47.20#ibcon#read 6, iclass 12, count 0 2006.285.06:29:47.20#ibcon#end of sib2, iclass 12, count 0 2006.285.06:29:47.20#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:29:47.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:29:47.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:29:47.20#ibcon#*before write, iclass 12, count 0 2006.285.06:29:47.20#ibcon#enter sib2, iclass 12, count 0 2006.285.06:29:47.20#ibcon#flushed, iclass 12, count 0 2006.285.06:29:47.20#ibcon#about to write, iclass 12, count 0 2006.285.06:29:47.20#ibcon#wrote, iclass 12, count 0 2006.285.06:29:47.20#ibcon#about to read 3, iclass 12, count 0 2006.285.06:29:47.24#ibcon#read 3, iclass 12, count 0 2006.285.06:29:47.24#ibcon#about to read 4, iclass 12, count 0 2006.285.06:29:47.24#ibcon#read 4, iclass 12, count 0 2006.285.06:29:47.24#ibcon#about to read 5, iclass 12, count 0 2006.285.06:29:47.24#ibcon#read 5, iclass 12, count 0 2006.285.06:29:47.24#ibcon#about to read 6, iclass 12, count 0 2006.285.06:29:47.24#ibcon#read 6, iclass 12, count 0 2006.285.06:29:47.24#ibcon#end of sib2, iclass 12, count 0 2006.285.06:29:47.24#ibcon#*after write, iclass 12, count 0 2006.285.06:29:47.24#ibcon#*before return 0, iclass 12, count 0 2006.285.06:29:47.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:29:47.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:29:47.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:29:47.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:29:47.24$vck44/va=5,3 2006.285.06:29:47.24#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.06:29:47.24#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.06:29:47.24#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:47.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:29:47.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:29:47.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:29:47.30#ibcon#enter wrdev, iclass 14, count 2 2006.285.06:29:47.30#ibcon#first serial, iclass 14, count 2 2006.285.06:29:47.30#ibcon#enter sib2, iclass 14, count 2 2006.285.06:29:47.30#ibcon#flushed, iclass 14, count 2 2006.285.06:29:47.30#ibcon#about to write, iclass 14, count 2 2006.285.06:29:47.30#ibcon#wrote, iclass 14, count 2 2006.285.06:29:47.30#ibcon#about to read 3, iclass 14, count 2 2006.285.06:29:47.32#ibcon#read 3, iclass 14, count 2 2006.285.06:29:47.32#ibcon#about to read 4, iclass 14, count 2 2006.285.06:29:47.32#ibcon#read 4, iclass 14, count 2 2006.285.06:29:47.32#ibcon#about to read 5, iclass 14, count 2 2006.285.06:29:47.32#ibcon#read 5, iclass 14, count 2 2006.285.06:29:47.32#ibcon#about to read 6, iclass 14, count 2 2006.285.06:29:47.32#ibcon#read 6, iclass 14, count 2 2006.285.06:29:47.32#ibcon#end of sib2, iclass 14, count 2 2006.285.06:29:47.32#ibcon#*mode == 0, iclass 14, count 2 2006.285.06:29:47.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.06:29:47.32#ibcon#[25=AT05-03\r\n] 2006.285.06:29:47.32#ibcon#*before write, iclass 14, count 2 2006.285.06:29:47.32#ibcon#enter sib2, iclass 14, count 2 2006.285.06:29:47.32#ibcon#flushed, iclass 14, count 2 2006.285.06:29:47.32#ibcon#about to write, iclass 14, count 2 2006.285.06:29:47.32#ibcon#wrote, iclass 14, count 2 2006.285.06:29:47.32#ibcon#about to read 3, iclass 14, count 2 2006.285.06:29:47.35#ibcon#read 3, iclass 14, count 2 2006.285.06:29:47.35#ibcon#about to read 4, iclass 14, count 2 2006.285.06:29:47.35#ibcon#read 4, iclass 14, count 2 2006.285.06:29:47.35#ibcon#about to read 5, iclass 14, count 2 2006.285.06:29:47.35#ibcon#read 5, iclass 14, count 2 2006.285.06:29:47.35#ibcon#about to read 6, iclass 14, count 2 2006.285.06:29:47.35#ibcon#read 6, iclass 14, count 2 2006.285.06:29:47.35#ibcon#end of sib2, iclass 14, count 2 2006.285.06:29:47.35#ibcon#*after write, iclass 14, count 2 2006.285.06:29:47.35#ibcon#*before return 0, iclass 14, count 2 2006.285.06:29:47.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:29:47.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:29:47.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.06:29:47.35#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:47.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:29:47.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:29:47.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:29:47.47#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:29:47.47#ibcon#first serial, iclass 14, count 0 2006.285.06:29:47.47#ibcon#enter sib2, iclass 14, count 0 2006.285.06:29:47.47#ibcon#flushed, iclass 14, count 0 2006.285.06:29:47.47#ibcon#about to write, iclass 14, count 0 2006.285.06:29:47.47#ibcon#wrote, iclass 14, count 0 2006.285.06:29:47.47#ibcon#about to read 3, iclass 14, count 0 2006.285.06:29:47.49#ibcon#read 3, iclass 14, count 0 2006.285.06:29:47.49#ibcon#about to read 4, iclass 14, count 0 2006.285.06:29:47.49#ibcon#read 4, iclass 14, count 0 2006.285.06:29:47.49#ibcon#about to read 5, iclass 14, count 0 2006.285.06:29:47.49#ibcon#read 5, iclass 14, count 0 2006.285.06:29:47.49#ibcon#about to read 6, iclass 14, count 0 2006.285.06:29:47.49#ibcon#read 6, iclass 14, count 0 2006.285.06:29:47.49#ibcon#end of sib2, iclass 14, count 0 2006.285.06:29:47.49#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:29:47.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:29:47.49#ibcon#[25=USB\r\n] 2006.285.06:29:47.49#ibcon#*before write, iclass 14, count 0 2006.285.06:29:47.49#ibcon#enter sib2, iclass 14, count 0 2006.285.06:29:47.49#ibcon#flushed, iclass 14, count 0 2006.285.06:29:47.49#ibcon#about to write, iclass 14, count 0 2006.285.06:29:47.49#ibcon#wrote, iclass 14, count 0 2006.285.06:29:47.49#ibcon#about to read 3, iclass 14, count 0 2006.285.06:29:47.52#ibcon#read 3, iclass 14, count 0 2006.285.06:29:47.52#ibcon#about to read 4, iclass 14, count 0 2006.285.06:29:47.52#ibcon#read 4, iclass 14, count 0 2006.285.06:29:47.52#ibcon#about to read 5, iclass 14, count 0 2006.285.06:29:47.52#ibcon#read 5, iclass 14, count 0 2006.285.06:29:47.52#ibcon#about to read 6, iclass 14, count 0 2006.285.06:29:47.52#ibcon#read 6, iclass 14, count 0 2006.285.06:29:47.52#ibcon#end of sib2, iclass 14, count 0 2006.285.06:29:47.52#ibcon#*after write, iclass 14, count 0 2006.285.06:29:47.52#ibcon#*before return 0, iclass 14, count 0 2006.285.06:29:47.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:29:47.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:29:47.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:29:47.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:29:47.52$vck44/valo=6,814.99 2006.285.06:29:47.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.06:29:47.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.06:29:47.52#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:47.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:29:47.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:29:47.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:29:47.52#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:29:47.52#ibcon#first serial, iclass 16, count 0 2006.285.06:29:47.52#ibcon#enter sib2, iclass 16, count 0 2006.285.06:29:47.52#ibcon#flushed, iclass 16, count 0 2006.285.06:29:47.52#ibcon#about to write, iclass 16, count 0 2006.285.06:29:47.52#ibcon#wrote, iclass 16, count 0 2006.285.06:29:47.52#ibcon#about to read 3, iclass 16, count 0 2006.285.06:29:47.54#ibcon#read 3, iclass 16, count 0 2006.285.06:29:47.54#ibcon#about to read 4, iclass 16, count 0 2006.285.06:29:47.54#ibcon#read 4, iclass 16, count 0 2006.285.06:29:47.54#ibcon#about to read 5, iclass 16, count 0 2006.285.06:29:47.54#ibcon#read 5, iclass 16, count 0 2006.285.06:29:47.54#ibcon#about to read 6, iclass 16, count 0 2006.285.06:29:47.54#ibcon#read 6, iclass 16, count 0 2006.285.06:29:47.54#ibcon#end of sib2, iclass 16, count 0 2006.285.06:29:47.54#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:29:47.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:29:47.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:29:47.54#ibcon#*before write, iclass 16, count 0 2006.285.06:29:47.54#ibcon#enter sib2, iclass 16, count 0 2006.285.06:29:47.54#ibcon#flushed, iclass 16, count 0 2006.285.06:29:47.54#ibcon#about to write, iclass 16, count 0 2006.285.06:29:47.54#ibcon#wrote, iclass 16, count 0 2006.285.06:29:47.54#ibcon#about to read 3, iclass 16, count 0 2006.285.06:29:47.58#ibcon#read 3, iclass 16, count 0 2006.285.06:29:47.58#ibcon#about to read 4, iclass 16, count 0 2006.285.06:29:47.58#ibcon#read 4, iclass 16, count 0 2006.285.06:29:47.58#ibcon#about to read 5, iclass 16, count 0 2006.285.06:29:47.58#ibcon#read 5, iclass 16, count 0 2006.285.06:29:47.58#ibcon#about to read 6, iclass 16, count 0 2006.285.06:29:47.58#ibcon#read 6, iclass 16, count 0 2006.285.06:29:47.58#ibcon#end of sib2, iclass 16, count 0 2006.285.06:29:47.58#ibcon#*after write, iclass 16, count 0 2006.285.06:29:47.58#ibcon#*before return 0, iclass 16, count 0 2006.285.06:29:47.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:29:47.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:29:47.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:29:47.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:29:47.58$vck44/va=6,4 2006.285.06:29:47.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.06:29:47.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.06:29:47.58#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:47.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:29:47.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:29:47.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:29:47.64#ibcon#enter wrdev, iclass 18, count 2 2006.285.06:29:47.64#ibcon#first serial, iclass 18, count 2 2006.285.06:29:47.64#ibcon#enter sib2, iclass 18, count 2 2006.285.06:29:47.64#ibcon#flushed, iclass 18, count 2 2006.285.06:29:47.64#ibcon#about to write, iclass 18, count 2 2006.285.06:29:47.64#ibcon#wrote, iclass 18, count 2 2006.285.06:29:47.64#ibcon#about to read 3, iclass 18, count 2 2006.285.06:29:47.67#ibcon#read 3, iclass 18, count 2 2006.285.06:29:47.67#ibcon#about to read 4, iclass 18, count 2 2006.285.06:29:47.67#ibcon#read 4, iclass 18, count 2 2006.285.06:29:47.67#ibcon#about to read 5, iclass 18, count 2 2006.285.06:29:47.67#ibcon#read 5, iclass 18, count 2 2006.285.06:29:47.67#ibcon#about to read 6, iclass 18, count 2 2006.285.06:29:47.67#ibcon#read 6, iclass 18, count 2 2006.285.06:29:47.67#ibcon#end of sib2, iclass 18, count 2 2006.285.06:29:47.67#ibcon#*mode == 0, iclass 18, count 2 2006.285.06:29:47.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.06:29:47.67#ibcon#[25=AT06-04\r\n] 2006.285.06:29:47.67#ibcon#*before write, iclass 18, count 2 2006.285.06:29:47.67#ibcon#enter sib2, iclass 18, count 2 2006.285.06:29:47.67#ibcon#flushed, iclass 18, count 2 2006.285.06:29:47.67#ibcon#about to write, iclass 18, count 2 2006.285.06:29:47.67#ibcon#wrote, iclass 18, count 2 2006.285.06:29:47.67#ibcon#about to read 3, iclass 18, count 2 2006.285.06:29:47.70#ibcon#read 3, iclass 18, count 2 2006.285.06:29:47.70#ibcon#about to read 4, iclass 18, count 2 2006.285.06:29:47.70#ibcon#read 4, iclass 18, count 2 2006.285.06:29:47.70#ibcon#about to read 5, iclass 18, count 2 2006.285.06:29:47.70#ibcon#read 5, iclass 18, count 2 2006.285.06:29:47.70#ibcon#about to read 6, iclass 18, count 2 2006.285.06:29:47.70#ibcon#read 6, iclass 18, count 2 2006.285.06:29:47.70#ibcon#end of sib2, iclass 18, count 2 2006.285.06:29:47.70#ibcon#*after write, iclass 18, count 2 2006.285.06:29:47.70#ibcon#*before return 0, iclass 18, count 2 2006.285.06:29:47.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:29:47.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:29:47.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.06:29:47.70#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:47.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:29:47.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:29:47.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:29:47.82#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:29:47.82#ibcon#first serial, iclass 18, count 0 2006.285.06:29:47.82#ibcon#enter sib2, iclass 18, count 0 2006.285.06:29:47.82#ibcon#flushed, iclass 18, count 0 2006.285.06:29:47.82#ibcon#about to write, iclass 18, count 0 2006.285.06:29:47.82#ibcon#wrote, iclass 18, count 0 2006.285.06:29:47.82#ibcon#about to read 3, iclass 18, count 0 2006.285.06:29:47.84#ibcon#read 3, iclass 18, count 0 2006.285.06:29:47.84#ibcon#about to read 4, iclass 18, count 0 2006.285.06:29:47.84#ibcon#read 4, iclass 18, count 0 2006.285.06:29:47.84#ibcon#about to read 5, iclass 18, count 0 2006.285.06:29:47.84#ibcon#read 5, iclass 18, count 0 2006.285.06:29:47.84#ibcon#about to read 6, iclass 18, count 0 2006.285.06:29:47.84#ibcon#read 6, iclass 18, count 0 2006.285.06:29:47.84#ibcon#end of sib2, iclass 18, count 0 2006.285.06:29:47.84#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:29:47.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:29:47.84#ibcon#[25=USB\r\n] 2006.285.06:29:47.84#ibcon#*before write, iclass 18, count 0 2006.285.06:29:47.84#ibcon#enter sib2, iclass 18, count 0 2006.285.06:29:47.84#ibcon#flushed, iclass 18, count 0 2006.285.06:29:47.84#ibcon#about to write, iclass 18, count 0 2006.285.06:29:47.84#ibcon#wrote, iclass 18, count 0 2006.285.06:29:47.84#ibcon#about to read 3, iclass 18, count 0 2006.285.06:29:47.87#ibcon#read 3, iclass 18, count 0 2006.285.06:29:47.87#ibcon#about to read 4, iclass 18, count 0 2006.285.06:29:47.87#ibcon#read 4, iclass 18, count 0 2006.285.06:29:47.87#ibcon#about to read 5, iclass 18, count 0 2006.285.06:29:47.87#ibcon#read 5, iclass 18, count 0 2006.285.06:29:47.87#ibcon#about to read 6, iclass 18, count 0 2006.285.06:29:47.87#ibcon#read 6, iclass 18, count 0 2006.285.06:29:47.87#ibcon#end of sib2, iclass 18, count 0 2006.285.06:29:47.87#ibcon#*after write, iclass 18, count 0 2006.285.06:29:47.87#ibcon#*before return 0, iclass 18, count 0 2006.285.06:29:47.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:29:47.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:29:47.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:29:47.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:29:47.87$vck44/valo=7,864.99 2006.285.06:29:47.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.06:29:47.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.06:29:47.87#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:47.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:29:47.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:29:47.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:29:47.87#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:29:47.87#ibcon#first serial, iclass 20, count 0 2006.285.06:29:47.87#ibcon#enter sib2, iclass 20, count 0 2006.285.06:29:47.87#ibcon#flushed, iclass 20, count 0 2006.285.06:29:47.87#ibcon#about to write, iclass 20, count 0 2006.285.06:29:47.87#ibcon#wrote, iclass 20, count 0 2006.285.06:29:47.87#ibcon#about to read 3, iclass 20, count 0 2006.285.06:29:47.89#ibcon#read 3, iclass 20, count 0 2006.285.06:29:47.89#ibcon#about to read 4, iclass 20, count 0 2006.285.06:29:47.89#ibcon#read 4, iclass 20, count 0 2006.285.06:29:47.89#ibcon#about to read 5, iclass 20, count 0 2006.285.06:29:47.89#ibcon#read 5, iclass 20, count 0 2006.285.06:29:47.89#ibcon#about to read 6, iclass 20, count 0 2006.285.06:29:47.89#ibcon#read 6, iclass 20, count 0 2006.285.06:29:47.89#ibcon#end of sib2, iclass 20, count 0 2006.285.06:29:47.89#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:29:47.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:29:47.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:29:47.89#ibcon#*before write, iclass 20, count 0 2006.285.06:29:47.89#ibcon#enter sib2, iclass 20, count 0 2006.285.06:29:47.89#ibcon#flushed, iclass 20, count 0 2006.285.06:29:47.89#ibcon#about to write, iclass 20, count 0 2006.285.06:29:47.89#ibcon#wrote, iclass 20, count 0 2006.285.06:29:47.89#ibcon#about to read 3, iclass 20, count 0 2006.285.06:29:47.93#ibcon#read 3, iclass 20, count 0 2006.285.06:29:47.93#ibcon#about to read 4, iclass 20, count 0 2006.285.06:29:47.93#ibcon#read 4, iclass 20, count 0 2006.285.06:29:47.93#ibcon#about to read 5, iclass 20, count 0 2006.285.06:29:47.93#ibcon#read 5, iclass 20, count 0 2006.285.06:29:47.93#ibcon#about to read 6, iclass 20, count 0 2006.285.06:29:47.93#ibcon#read 6, iclass 20, count 0 2006.285.06:29:47.93#ibcon#end of sib2, iclass 20, count 0 2006.285.06:29:47.93#ibcon#*after write, iclass 20, count 0 2006.285.06:29:47.93#ibcon#*before return 0, iclass 20, count 0 2006.285.06:29:47.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:29:47.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:29:47.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:29:47.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:29:47.93$vck44/va=7,4 2006.285.06:29:47.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.06:29:47.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.06:29:47.93#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:47.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:29:47.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:29:47.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:29:47.99#ibcon#enter wrdev, iclass 22, count 2 2006.285.06:29:47.99#ibcon#first serial, iclass 22, count 2 2006.285.06:29:47.99#ibcon#enter sib2, iclass 22, count 2 2006.285.06:29:47.99#ibcon#flushed, iclass 22, count 2 2006.285.06:29:47.99#ibcon#about to write, iclass 22, count 2 2006.285.06:29:47.99#ibcon#wrote, iclass 22, count 2 2006.285.06:29:47.99#ibcon#about to read 3, iclass 22, count 2 2006.285.06:29:48.01#ibcon#read 3, iclass 22, count 2 2006.285.06:29:48.01#ibcon#about to read 4, iclass 22, count 2 2006.285.06:29:48.01#ibcon#read 4, iclass 22, count 2 2006.285.06:29:48.01#ibcon#about to read 5, iclass 22, count 2 2006.285.06:29:48.01#ibcon#read 5, iclass 22, count 2 2006.285.06:29:48.01#ibcon#about to read 6, iclass 22, count 2 2006.285.06:29:48.01#ibcon#read 6, iclass 22, count 2 2006.285.06:29:48.01#ibcon#end of sib2, iclass 22, count 2 2006.285.06:29:48.01#ibcon#*mode == 0, iclass 22, count 2 2006.285.06:29:48.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.06:29:48.01#ibcon#[25=AT07-04\r\n] 2006.285.06:29:48.01#ibcon#*before write, iclass 22, count 2 2006.285.06:29:48.01#ibcon#enter sib2, iclass 22, count 2 2006.285.06:29:48.01#ibcon#flushed, iclass 22, count 2 2006.285.06:29:48.01#ibcon#about to write, iclass 22, count 2 2006.285.06:29:48.01#ibcon#wrote, iclass 22, count 2 2006.285.06:29:48.01#ibcon#about to read 3, iclass 22, count 2 2006.285.06:29:48.04#ibcon#read 3, iclass 22, count 2 2006.285.06:29:48.04#ibcon#about to read 4, iclass 22, count 2 2006.285.06:29:48.04#ibcon#read 4, iclass 22, count 2 2006.285.06:29:48.04#ibcon#about to read 5, iclass 22, count 2 2006.285.06:29:48.04#ibcon#read 5, iclass 22, count 2 2006.285.06:29:48.04#ibcon#about to read 6, iclass 22, count 2 2006.285.06:29:48.04#ibcon#read 6, iclass 22, count 2 2006.285.06:29:48.04#ibcon#end of sib2, iclass 22, count 2 2006.285.06:29:48.04#ibcon#*after write, iclass 22, count 2 2006.285.06:29:48.04#ibcon#*before return 0, iclass 22, count 2 2006.285.06:29:48.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:29:48.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:29:48.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.06:29:48.04#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:48.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:29:48.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:29:48.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:29:48.16#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:29:48.16#ibcon#first serial, iclass 22, count 0 2006.285.06:29:48.16#ibcon#enter sib2, iclass 22, count 0 2006.285.06:29:48.16#ibcon#flushed, iclass 22, count 0 2006.285.06:29:48.16#ibcon#about to write, iclass 22, count 0 2006.285.06:29:48.16#ibcon#wrote, iclass 22, count 0 2006.285.06:29:48.16#ibcon#about to read 3, iclass 22, count 0 2006.285.06:29:48.18#ibcon#read 3, iclass 22, count 0 2006.285.06:29:48.18#ibcon#about to read 4, iclass 22, count 0 2006.285.06:29:48.18#ibcon#read 4, iclass 22, count 0 2006.285.06:29:48.18#ibcon#about to read 5, iclass 22, count 0 2006.285.06:29:48.18#ibcon#read 5, iclass 22, count 0 2006.285.06:29:48.18#ibcon#about to read 6, iclass 22, count 0 2006.285.06:29:48.18#ibcon#read 6, iclass 22, count 0 2006.285.06:29:48.18#ibcon#end of sib2, iclass 22, count 0 2006.285.06:29:48.18#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:29:48.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:29:48.18#ibcon#[25=USB\r\n] 2006.285.06:29:48.18#ibcon#*before write, iclass 22, count 0 2006.285.06:29:48.18#ibcon#enter sib2, iclass 22, count 0 2006.285.06:29:48.18#ibcon#flushed, iclass 22, count 0 2006.285.06:29:48.18#ibcon#about to write, iclass 22, count 0 2006.285.06:29:48.18#ibcon#wrote, iclass 22, count 0 2006.285.06:29:48.18#ibcon#about to read 3, iclass 22, count 0 2006.285.06:29:48.21#ibcon#read 3, iclass 22, count 0 2006.285.06:29:48.21#ibcon#about to read 4, iclass 22, count 0 2006.285.06:29:48.21#ibcon#read 4, iclass 22, count 0 2006.285.06:29:48.21#ibcon#about to read 5, iclass 22, count 0 2006.285.06:29:48.21#ibcon#read 5, iclass 22, count 0 2006.285.06:29:48.21#ibcon#about to read 6, iclass 22, count 0 2006.285.06:29:48.21#ibcon#read 6, iclass 22, count 0 2006.285.06:29:48.21#ibcon#end of sib2, iclass 22, count 0 2006.285.06:29:48.21#ibcon#*after write, iclass 22, count 0 2006.285.06:29:48.21#ibcon#*before return 0, iclass 22, count 0 2006.285.06:29:48.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:29:48.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:29:48.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:29:48.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:29:48.21$vck44/valo=8,884.99 2006.285.06:29:48.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.06:29:48.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.06:29:48.21#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:48.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:29:48.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:29:48.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:29:48.21#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:29:48.21#ibcon#first serial, iclass 24, count 0 2006.285.06:29:48.21#ibcon#enter sib2, iclass 24, count 0 2006.285.06:29:48.21#ibcon#flushed, iclass 24, count 0 2006.285.06:29:48.21#ibcon#about to write, iclass 24, count 0 2006.285.06:29:48.21#ibcon#wrote, iclass 24, count 0 2006.285.06:29:48.21#ibcon#about to read 3, iclass 24, count 0 2006.285.06:29:48.23#ibcon#read 3, iclass 24, count 0 2006.285.06:29:48.23#ibcon#about to read 4, iclass 24, count 0 2006.285.06:29:48.23#ibcon#read 4, iclass 24, count 0 2006.285.06:29:48.23#ibcon#about to read 5, iclass 24, count 0 2006.285.06:29:48.23#ibcon#read 5, iclass 24, count 0 2006.285.06:29:48.23#ibcon#about to read 6, iclass 24, count 0 2006.285.06:29:48.23#ibcon#read 6, iclass 24, count 0 2006.285.06:29:48.23#ibcon#end of sib2, iclass 24, count 0 2006.285.06:29:48.23#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:29:48.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:29:48.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:29:48.23#ibcon#*before write, iclass 24, count 0 2006.285.06:29:48.23#ibcon#enter sib2, iclass 24, count 0 2006.285.06:29:48.23#ibcon#flushed, iclass 24, count 0 2006.285.06:29:48.23#ibcon#about to write, iclass 24, count 0 2006.285.06:29:48.23#ibcon#wrote, iclass 24, count 0 2006.285.06:29:48.23#ibcon#about to read 3, iclass 24, count 0 2006.285.06:29:48.27#ibcon#read 3, iclass 24, count 0 2006.285.06:29:48.27#ibcon#about to read 4, iclass 24, count 0 2006.285.06:29:48.27#ibcon#read 4, iclass 24, count 0 2006.285.06:29:48.27#ibcon#about to read 5, iclass 24, count 0 2006.285.06:29:48.27#ibcon#read 5, iclass 24, count 0 2006.285.06:29:48.27#ibcon#about to read 6, iclass 24, count 0 2006.285.06:29:48.27#ibcon#read 6, iclass 24, count 0 2006.285.06:29:48.27#ibcon#end of sib2, iclass 24, count 0 2006.285.06:29:48.27#ibcon#*after write, iclass 24, count 0 2006.285.06:29:48.27#ibcon#*before return 0, iclass 24, count 0 2006.285.06:29:48.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:29:48.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:29:48.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:29:48.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:29:48.27$vck44/va=8,3 2006.285.06:29:48.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.06:29:48.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.06:29:48.27#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:48.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:29:48.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:29:48.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:29:48.33#ibcon#enter wrdev, iclass 26, count 2 2006.285.06:29:48.33#ibcon#first serial, iclass 26, count 2 2006.285.06:29:48.33#ibcon#enter sib2, iclass 26, count 2 2006.285.06:29:48.33#ibcon#flushed, iclass 26, count 2 2006.285.06:29:48.33#ibcon#about to write, iclass 26, count 2 2006.285.06:29:48.33#ibcon#wrote, iclass 26, count 2 2006.285.06:29:48.33#ibcon#about to read 3, iclass 26, count 2 2006.285.06:29:48.35#ibcon#read 3, iclass 26, count 2 2006.285.06:29:48.35#ibcon#about to read 4, iclass 26, count 2 2006.285.06:29:48.35#ibcon#read 4, iclass 26, count 2 2006.285.06:29:48.35#ibcon#about to read 5, iclass 26, count 2 2006.285.06:29:48.35#ibcon#read 5, iclass 26, count 2 2006.285.06:29:48.35#ibcon#about to read 6, iclass 26, count 2 2006.285.06:29:48.35#ibcon#read 6, iclass 26, count 2 2006.285.06:29:48.35#ibcon#end of sib2, iclass 26, count 2 2006.285.06:29:48.35#ibcon#*mode == 0, iclass 26, count 2 2006.285.06:29:48.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.06:29:48.35#ibcon#[25=AT08-03\r\n] 2006.285.06:29:48.35#ibcon#*before write, iclass 26, count 2 2006.285.06:29:48.35#ibcon#enter sib2, iclass 26, count 2 2006.285.06:29:48.35#ibcon#flushed, iclass 26, count 2 2006.285.06:29:48.35#ibcon#about to write, iclass 26, count 2 2006.285.06:29:48.35#ibcon#wrote, iclass 26, count 2 2006.285.06:29:48.35#ibcon#about to read 3, iclass 26, count 2 2006.285.06:29:48.38#ibcon#read 3, iclass 26, count 2 2006.285.06:29:48.38#ibcon#about to read 4, iclass 26, count 2 2006.285.06:29:48.38#ibcon#read 4, iclass 26, count 2 2006.285.06:29:48.38#ibcon#about to read 5, iclass 26, count 2 2006.285.06:29:48.38#ibcon#read 5, iclass 26, count 2 2006.285.06:29:48.38#ibcon#about to read 6, iclass 26, count 2 2006.285.06:29:48.38#ibcon#read 6, iclass 26, count 2 2006.285.06:29:48.38#ibcon#end of sib2, iclass 26, count 2 2006.285.06:29:48.38#ibcon#*after write, iclass 26, count 2 2006.285.06:29:48.38#ibcon#*before return 0, iclass 26, count 2 2006.285.06:29:48.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:29:48.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:29:48.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.06:29:48.38#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:48.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:29:48.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:29:48.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:29:48.50#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:29:48.50#ibcon#first serial, iclass 26, count 0 2006.285.06:29:48.50#ibcon#enter sib2, iclass 26, count 0 2006.285.06:29:48.50#ibcon#flushed, iclass 26, count 0 2006.285.06:29:48.50#ibcon#about to write, iclass 26, count 0 2006.285.06:29:48.50#ibcon#wrote, iclass 26, count 0 2006.285.06:29:48.50#ibcon#about to read 3, iclass 26, count 0 2006.285.06:29:48.52#ibcon#read 3, iclass 26, count 0 2006.285.06:29:48.52#ibcon#about to read 4, iclass 26, count 0 2006.285.06:29:48.52#ibcon#read 4, iclass 26, count 0 2006.285.06:29:48.52#ibcon#about to read 5, iclass 26, count 0 2006.285.06:29:48.52#ibcon#read 5, iclass 26, count 0 2006.285.06:29:48.52#ibcon#about to read 6, iclass 26, count 0 2006.285.06:29:48.52#ibcon#read 6, iclass 26, count 0 2006.285.06:29:48.52#ibcon#end of sib2, iclass 26, count 0 2006.285.06:29:48.52#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:29:48.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:29:48.52#ibcon#[25=USB\r\n] 2006.285.06:29:48.52#ibcon#*before write, iclass 26, count 0 2006.285.06:29:48.52#ibcon#enter sib2, iclass 26, count 0 2006.285.06:29:48.52#ibcon#flushed, iclass 26, count 0 2006.285.06:29:48.52#ibcon#about to write, iclass 26, count 0 2006.285.06:29:48.52#ibcon#wrote, iclass 26, count 0 2006.285.06:29:48.52#ibcon#about to read 3, iclass 26, count 0 2006.285.06:29:48.55#ibcon#read 3, iclass 26, count 0 2006.285.06:29:48.55#ibcon#about to read 4, iclass 26, count 0 2006.285.06:29:48.55#ibcon#read 4, iclass 26, count 0 2006.285.06:29:48.55#ibcon#about to read 5, iclass 26, count 0 2006.285.06:29:48.55#ibcon#read 5, iclass 26, count 0 2006.285.06:29:48.55#ibcon#about to read 6, iclass 26, count 0 2006.285.06:29:48.55#ibcon#read 6, iclass 26, count 0 2006.285.06:29:48.55#ibcon#end of sib2, iclass 26, count 0 2006.285.06:29:48.55#ibcon#*after write, iclass 26, count 0 2006.285.06:29:48.55#ibcon#*before return 0, iclass 26, count 0 2006.285.06:29:48.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:29:48.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:29:48.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:29:48.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:29:48.55$vck44/vblo=1,629.99 2006.285.06:29:48.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.06:29:48.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.06:29:48.55#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:48.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:29:48.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:29:48.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:29:48.55#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:29:48.55#ibcon#first serial, iclass 28, count 0 2006.285.06:29:48.55#ibcon#enter sib2, iclass 28, count 0 2006.285.06:29:48.55#ibcon#flushed, iclass 28, count 0 2006.285.06:29:48.55#ibcon#about to write, iclass 28, count 0 2006.285.06:29:48.55#ibcon#wrote, iclass 28, count 0 2006.285.06:29:48.55#ibcon#about to read 3, iclass 28, count 0 2006.285.06:29:48.57#ibcon#read 3, iclass 28, count 0 2006.285.06:29:48.57#ibcon#about to read 4, iclass 28, count 0 2006.285.06:29:48.57#ibcon#read 4, iclass 28, count 0 2006.285.06:29:48.57#ibcon#about to read 5, iclass 28, count 0 2006.285.06:29:48.57#ibcon#read 5, iclass 28, count 0 2006.285.06:29:48.57#ibcon#about to read 6, iclass 28, count 0 2006.285.06:29:48.57#ibcon#read 6, iclass 28, count 0 2006.285.06:29:48.57#ibcon#end of sib2, iclass 28, count 0 2006.285.06:29:48.57#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:29:48.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:29:48.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:29:48.57#ibcon#*before write, iclass 28, count 0 2006.285.06:29:48.57#ibcon#enter sib2, iclass 28, count 0 2006.285.06:29:48.57#ibcon#flushed, iclass 28, count 0 2006.285.06:29:48.57#ibcon#about to write, iclass 28, count 0 2006.285.06:29:48.57#ibcon#wrote, iclass 28, count 0 2006.285.06:29:48.57#ibcon#about to read 3, iclass 28, count 0 2006.285.06:29:48.61#ibcon#read 3, iclass 28, count 0 2006.285.06:29:48.61#ibcon#about to read 4, iclass 28, count 0 2006.285.06:29:48.61#ibcon#read 4, iclass 28, count 0 2006.285.06:29:48.61#ibcon#about to read 5, iclass 28, count 0 2006.285.06:29:48.61#ibcon#read 5, iclass 28, count 0 2006.285.06:29:48.61#ibcon#about to read 6, iclass 28, count 0 2006.285.06:29:48.61#ibcon#read 6, iclass 28, count 0 2006.285.06:29:48.61#ibcon#end of sib2, iclass 28, count 0 2006.285.06:29:48.61#ibcon#*after write, iclass 28, count 0 2006.285.06:29:48.61#ibcon#*before return 0, iclass 28, count 0 2006.285.06:29:48.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:29:48.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:29:48.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:29:48.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:29:48.61$vck44/vb=1,4 2006.285.06:29:48.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.06:29:48.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.06:29:48.61#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:48.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:29:48.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:29:48.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:29:48.61#ibcon#enter wrdev, iclass 30, count 2 2006.285.06:29:48.61#ibcon#first serial, iclass 30, count 2 2006.285.06:29:48.61#ibcon#enter sib2, iclass 30, count 2 2006.285.06:29:48.61#ibcon#flushed, iclass 30, count 2 2006.285.06:29:48.61#ibcon#about to write, iclass 30, count 2 2006.285.06:29:48.61#ibcon#wrote, iclass 30, count 2 2006.285.06:29:48.61#ibcon#about to read 3, iclass 30, count 2 2006.285.06:29:48.63#ibcon#read 3, iclass 30, count 2 2006.285.06:29:48.63#ibcon#about to read 4, iclass 30, count 2 2006.285.06:29:48.63#ibcon#read 4, iclass 30, count 2 2006.285.06:29:48.63#ibcon#about to read 5, iclass 30, count 2 2006.285.06:29:48.63#ibcon#read 5, iclass 30, count 2 2006.285.06:29:48.63#ibcon#about to read 6, iclass 30, count 2 2006.285.06:29:48.63#ibcon#read 6, iclass 30, count 2 2006.285.06:29:48.63#ibcon#end of sib2, iclass 30, count 2 2006.285.06:29:48.63#ibcon#*mode == 0, iclass 30, count 2 2006.285.06:29:48.63#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.06:29:48.63#ibcon#[27=AT01-04\r\n] 2006.285.06:29:48.63#ibcon#*before write, iclass 30, count 2 2006.285.06:29:48.63#ibcon#enter sib2, iclass 30, count 2 2006.285.06:29:48.63#ibcon#flushed, iclass 30, count 2 2006.285.06:29:48.63#ibcon#about to write, iclass 30, count 2 2006.285.06:29:48.63#ibcon#wrote, iclass 30, count 2 2006.285.06:29:48.63#ibcon#about to read 3, iclass 30, count 2 2006.285.06:29:48.66#ibcon#read 3, iclass 30, count 2 2006.285.06:29:48.66#ibcon#about to read 4, iclass 30, count 2 2006.285.06:29:48.66#ibcon#read 4, iclass 30, count 2 2006.285.06:29:48.66#ibcon#about to read 5, iclass 30, count 2 2006.285.06:29:48.66#ibcon#read 5, iclass 30, count 2 2006.285.06:29:48.66#ibcon#about to read 6, iclass 30, count 2 2006.285.06:29:48.66#ibcon#read 6, iclass 30, count 2 2006.285.06:29:48.66#ibcon#end of sib2, iclass 30, count 2 2006.285.06:29:48.66#ibcon#*after write, iclass 30, count 2 2006.285.06:29:48.66#ibcon#*before return 0, iclass 30, count 2 2006.285.06:29:48.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:29:48.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:29:48.66#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.06:29:48.66#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:48.66#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:29:48.78#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:29:48.78#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:29:48.78#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:29:48.78#ibcon#first serial, iclass 30, count 0 2006.285.06:29:48.78#ibcon#enter sib2, iclass 30, count 0 2006.285.06:29:48.78#ibcon#flushed, iclass 30, count 0 2006.285.06:29:48.78#ibcon#about to write, iclass 30, count 0 2006.285.06:29:48.78#ibcon#wrote, iclass 30, count 0 2006.285.06:29:48.78#ibcon#about to read 3, iclass 30, count 0 2006.285.06:29:48.80#ibcon#read 3, iclass 30, count 0 2006.285.06:29:48.80#ibcon#about to read 4, iclass 30, count 0 2006.285.06:29:48.80#ibcon#read 4, iclass 30, count 0 2006.285.06:29:48.80#ibcon#about to read 5, iclass 30, count 0 2006.285.06:29:48.80#ibcon#read 5, iclass 30, count 0 2006.285.06:29:48.80#ibcon#about to read 6, iclass 30, count 0 2006.285.06:29:48.80#ibcon#read 6, iclass 30, count 0 2006.285.06:29:48.80#ibcon#end of sib2, iclass 30, count 0 2006.285.06:29:48.80#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:29:48.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:29:48.80#ibcon#[27=USB\r\n] 2006.285.06:29:48.80#ibcon#*before write, iclass 30, count 0 2006.285.06:29:48.80#ibcon#enter sib2, iclass 30, count 0 2006.285.06:29:48.80#ibcon#flushed, iclass 30, count 0 2006.285.06:29:48.80#ibcon#about to write, iclass 30, count 0 2006.285.06:29:48.80#ibcon#wrote, iclass 30, count 0 2006.285.06:29:48.80#ibcon#about to read 3, iclass 30, count 0 2006.285.06:29:48.83#ibcon#read 3, iclass 30, count 0 2006.285.06:29:48.83#ibcon#about to read 4, iclass 30, count 0 2006.285.06:29:48.83#ibcon#read 4, iclass 30, count 0 2006.285.06:29:48.83#ibcon#about to read 5, iclass 30, count 0 2006.285.06:29:48.83#ibcon#read 5, iclass 30, count 0 2006.285.06:29:48.83#ibcon#about to read 6, iclass 30, count 0 2006.285.06:29:48.83#ibcon#read 6, iclass 30, count 0 2006.285.06:29:48.83#ibcon#end of sib2, iclass 30, count 0 2006.285.06:29:48.83#ibcon#*after write, iclass 30, count 0 2006.285.06:29:48.83#ibcon#*before return 0, iclass 30, count 0 2006.285.06:29:48.83#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:29:48.83#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:29:48.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:29:48.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:29:48.83$vck44/vblo=2,634.99 2006.285.06:29:48.83#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.06:29:48.83#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.06:29:48.83#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:48.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:29:48.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:29:48.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:29:48.83#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:29:48.83#ibcon#first serial, iclass 32, count 0 2006.285.06:29:48.83#ibcon#enter sib2, iclass 32, count 0 2006.285.06:29:48.83#ibcon#flushed, iclass 32, count 0 2006.285.06:29:48.83#ibcon#about to write, iclass 32, count 0 2006.285.06:29:48.83#ibcon#wrote, iclass 32, count 0 2006.285.06:29:48.83#ibcon#about to read 3, iclass 32, count 0 2006.285.06:29:48.85#ibcon#read 3, iclass 32, count 0 2006.285.06:29:48.85#ibcon#about to read 4, iclass 32, count 0 2006.285.06:29:48.85#ibcon#read 4, iclass 32, count 0 2006.285.06:29:48.85#ibcon#about to read 5, iclass 32, count 0 2006.285.06:29:48.85#ibcon#read 5, iclass 32, count 0 2006.285.06:29:48.85#ibcon#about to read 6, iclass 32, count 0 2006.285.06:29:48.85#ibcon#read 6, iclass 32, count 0 2006.285.06:29:48.85#ibcon#end of sib2, iclass 32, count 0 2006.285.06:29:48.85#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:29:48.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:29:48.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:29:48.85#ibcon#*before write, iclass 32, count 0 2006.285.06:29:48.85#ibcon#enter sib2, iclass 32, count 0 2006.285.06:29:48.85#ibcon#flushed, iclass 32, count 0 2006.285.06:29:48.85#ibcon#about to write, iclass 32, count 0 2006.285.06:29:48.85#ibcon#wrote, iclass 32, count 0 2006.285.06:29:48.85#ibcon#about to read 3, iclass 32, count 0 2006.285.06:29:48.89#ibcon#read 3, iclass 32, count 0 2006.285.06:29:48.89#ibcon#about to read 4, iclass 32, count 0 2006.285.06:29:48.89#ibcon#read 4, iclass 32, count 0 2006.285.06:29:48.89#ibcon#about to read 5, iclass 32, count 0 2006.285.06:29:48.89#ibcon#read 5, iclass 32, count 0 2006.285.06:29:48.89#ibcon#about to read 6, iclass 32, count 0 2006.285.06:29:48.89#ibcon#read 6, iclass 32, count 0 2006.285.06:29:48.89#ibcon#end of sib2, iclass 32, count 0 2006.285.06:29:48.89#ibcon#*after write, iclass 32, count 0 2006.285.06:29:48.89#ibcon#*before return 0, iclass 32, count 0 2006.285.06:29:48.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:29:48.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:29:48.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:29:48.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:29:48.89$vck44/vb=2,5 2006.285.06:29:48.89#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.06:29:48.89#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.06:29:48.89#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:48.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:29:48.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:29:48.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:29:48.95#ibcon#enter wrdev, iclass 34, count 2 2006.285.06:29:48.95#ibcon#first serial, iclass 34, count 2 2006.285.06:29:48.95#ibcon#enter sib2, iclass 34, count 2 2006.285.06:29:48.95#ibcon#flushed, iclass 34, count 2 2006.285.06:29:48.95#ibcon#about to write, iclass 34, count 2 2006.285.06:29:48.95#ibcon#wrote, iclass 34, count 2 2006.285.06:29:48.95#ibcon#about to read 3, iclass 34, count 2 2006.285.06:29:48.97#ibcon#read 3, iclass 34, count 2 2006.285.06:29:48.97#ibcon#about to read 4, iclass 34, count 2 2006.285.06:29:48.97#ibcon#read 4, iclass 34, count 2 2006.285.06:29:48.97#ibcon#about to read 5, iclass 34, count 2 2006.285.06:29:48.97#ibcon#read 5, iclass 34, count 2 2006.285.06:29:48.97#ibcon#about to read 6, iclass 34, count 2 2006.285.06:29:48.97#ibcon#read 6, iclass 34, count 2 2006.285.06:29:48.97#ibcon#end of sib2, iclass 34, count 2 2006.285.06:29:48.97#ibcon#*mode == 0, iclass 34, count 2 2006.285.06:29:48.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.06:29:48.97#ibcon#[27=AT02-05\r\n] 2006.285.06:29:48.97#ibcon#*before write, iclass 34, count 2 2006.285.06:29:48.97#ibcon#enter sib2, iclass 34, count 2 2006.285.06:29:48.97#ibcon#flushed, iclass 34, count 2 2006.285.06:29:48.97#ibcon#about to write, iclass 34, count 2 2006.285.06:29:48.97#ibcon#wrote, iclass 34, count 2 2006.285.06:29:48.97#ibcon#about to read 3, iclass 34, count 2 2006.285.06:29:49.00#ibcon#read 3, iclass 34, count 2 2006.285.06:29:49.00#ibcon#about to read 4, iclass 34, count 2 2006.285.06:29:49.00#ibcon#read 4, iclass 34, count 2 2006.285.06:29:49.00#ibcon#about to read 5, iclass 34, count 2 2006.285.06:29:49.00#ibcon#read 5, iclass 34, count 2 2006.285.06:29:49.00#ibcon#about to read 6, iclass 34, count 2 2006.285.06:29:49.00#ibcon#read 6, iclass 34, count 2 2006.285.06:29:49.00#ibcon#end of sib2, iclass 34, count 2 2006.285.06:29:49.00#ibcon#*after write, iclass 34, count 2 2006.285.06:29:49.00#ibcon#*before return 0, iclass 34, count 2 2006.285.06:29:49.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:29:49.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:29:49.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.06:29:49.00#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:49.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:29:49.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:29:49.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:29:49.12#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:29:49.12#ibcon#first serial, iclass 34, count 0 2006.285.06:29:49.12#ibcon#enter sib2, iclass 34, count 0 2006.285.06:29:49.12#ibcon#flushed, iclass 34, count 0 2006.285.06:29:49.12#ibcon#about to write, iclass 34, count 0 2006.285.06:29:49.12#ibcon#wrote, iclass 34, count 0 2006.285.06:29:49.12#ibcon#about to read 3, iclass 34, count 0 2006.285.06:29:49.14#ibcon#read 3, iclass 34, count 0 2006.285.06:29:49.14#ibcon#about to read 4, iclass 34, count 0 2006.285.06:29:49.14#ibcon#read 4, iclass 34, count 0 2006.285.06:29:49.14#ibcon#about to read 5, iclass 34, count 0 2006.285.06:29:49.14#ibcon#read 5, iclass 34, count 0 2006.285.06:29:49.14#ibcon#about to read 6, iclass 34, count 0 2006.285.06:29:49.14#ibcon#read 6, iclass 34, count 0 2006.285.06:29:49.14#ibcon#end of sib2, iclass 34, count 0 2006.285.06:29:49.14#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:29:49.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:29:49.14#ibcon#[27=USB\r\n] 2006.285.06:29:49.14#ibcon#*before write, iclass 34, count 0 2006.285.06:29:49.14#ibcon#enter sib2, iclass 34, count 0 2006.285.06:29:49.14#ibcon#flushed, iclass 34, count 0 2006.285.06:29:49.14#ibcon#about to write, iclass 34, count 0 2006.285.06:29:49.14#ibcon#wrote, iclass 34, count 0 2006.285.06:29:49.14#ibcon#about to read 3, iclass 34, count 0 2006.285.06:29:49.17#ibcon#read 3, iclass 34, count 0 2006.285.06:29:49.17#ibcon#about to read 4, iclass 34, count 0 2006.285.06:29:49.17#ibcon#read 4, iclass 34, count 0 2006.285.06:29:49.17#ibcon#about to read 5, iclass 34, count 0 2006.285.06:29:49.17#ibcon#read 5, iclass 34, count 0 2006.285.06:29:49.17#ibcon#about to read 6, iclass 34, count 0 2006.285.06:29:49.17#ibcon#read 6, iclass 34, count 0 2006.285.06:29:49.17#ibcon#end of sib2, iclass 34, count 0 2006.285.06:29:49.17#ibcon#*after write, iclass 34, count 0 2006.285.06:29:49.17#ibcon#*before return 0, iclass 34, count 0 2006.285.06:29:49.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:29:49.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:29:49.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:29:49.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:29:49.17$vck44/vblo=3,649.99 2006.285.06:29:49.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.06:29:49.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.06:29:49.17#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:49.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:29:49.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:29:49.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:29:49.17#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:29:49.17#ibcon#first serial, iclass 36, count 0 2006.285.06:29:49.17#ibcon#enter sib2, iclass 36, count 0 2006.285.06:29:49.17#ibcon#flushed, iclass 36, count 0 2006.285.06:29:49.17#ibcon#about to write, iclass 36, count 0 2006.285.06:29:49.17#ibcon#wrote, iclass 36, count 0 2006.285.06:29:49.17#ibcon#about to read 3, iclass 36, count 0 2006.285.06:29:49.19#ibcon#read 3, iclass 36, count 0 2006.285.06:29:49.19#ibcon#about to read 4, iclass 36, count 0 2006.285.06:29:49.19#ibcon#read 4, iclass 36, count 0 2006.285.06:29:49.19#ibcon#about to read 5, iclass 36, count 0 2006.285.06:29:49.19#ibcon#read 5, iclass 36, count 0 2006.285.06:29:49.19#ibcon#about to read 6, iclass 36, count 0 2006.285.06:29:49.19#ibcon#read 6, iclass 36, count 0 2006.285.06:29:49.19#ibcon#end of sib2, iclass 36, count 0 2006.285.06:29:49.19#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:29:49.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:29:49.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:29:49.19#ibcon#*before write, iclass 36, count 0 2006.285.06:29:49.19#ibcon#enter sib2, iclass 36, count 0 2006.285.06:29:49.19#ibcon#flushed, iclass 36, count 0 2006.285.06:29:49.19#ibcon#about to write, iclass 36, count 0 2006.285.06:29:49.19#ibcon#wrote, iclass 36, count 0 2006.285.06:29:49.19#ibcon#about to read 3, iclass 36, count 0 2006.285.06:29:49.23#ibcon#read 3, iclass 36, count 0 2006.285.06:29:49.23#ibcon#about to read 4, iclass 36, count 0 2006.285.06:29:49.23#ibcon#read 4, iclass 36, count 0 2006.285.06:29:49.23#ibcon#about to read 5, iclass 36, count 0 2006.285.06:29:49.23#ibcon#read 5, iclass 36, count 0 2006.285.06:29:49.23#ibcon#about to read 6, iclass 36, count 0 2006.285.06:29:49.23#ibcon#read 6, iclass 36, count 0 2006.285.06:29:49.23#ibcon#end of sib2, iclass 36, count 0 2006.285.06:29:49.23#ibcon#*after write, iclass 36, count 0 2006.285.06:29:49.23#ibcon#*before return 0, iclass 36, count 0 2006.285.06:29:49.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:29:49.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:29:49.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:29:49.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:29:49.23$vck44/vb=3,4 2006.285.06:29:49.23#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.06:29:49.23#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.06:29:49.23#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:49.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:29:49.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:29:49.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:29:49.29#ibcon#enter wrdev, iclass 38, count 2 2006.285.06:29:49.29#ibcon#first serial, iclass 38, count 2 2006.285.06:29:49.29#ibcon#enter sib2, iclass 38, count 2 2006.285.06:29:49.29#ibcon#flushed, iclass 38, count 2 2006.285.06:29:49.29#ibcon#about to write, iclass 38, count 2 2006.285.06:29:49.29#ibcon#wrote, iclass 38, count 2 2006.285.06:29:49.29#ibcon#about to read 3, iclass 38, count 2 2006.285.06:29:49.31#ibcon#read 3, iclass 38, count 2 2006.285.06:29:49.31#ibcon#about to read 4, iclass 38, count 2 2006.285.06:29:49.31#ibcon#read 4, iclass 38, count 2 2006.285.06:29:49.31#ibcon#about to read 5, iclass 38, count 2 2006.285.06:29:49.31#ibcon#read 5, iclass 38, count 2 2006.285.06:29:49.31#ibcon#about to read 6, iclass 38, count 2 2006.285.06:29:49.31#ibcon#read 6, iclass 38, count 2 2006.285.06:29:49.31#ibcon#end of sib2, iclass 38, count 2 2006.285.06:29:49.31#ibcon#*mode == 0, iclass 38, count 2 2006.285.06:29:49.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.06:29:49.31#ibcon#[27=AT03-04\r\n] 2006.285.06:29:49.31#ibcon#*before write, iclass 38, count 2 2006.285.06:29:49.31#ibcon#enter sib2, iclass 38, count 2 2006.285.06:29:49.31#ibcon#flushed, iclass 38, count 2 2006.285.06:29:49.31#ibcon#about to write, iclass 38, count 2 2006.285.06:29:49.31#ibcon#wrote, iclass 38, count 2 2006.285.06:29:49.31#ibcon#about to read 3, iclass 38, count 2 2006.285.06:29:49.34#ibcon#read 3, iclass 38, count 2 2006.285.06:29:49.34#ibcon#about to read 4, iclass 38, count 2 2006.285.06:29:49.34#ibcon#read 4, iclass 38, count 2 2006.285.06:29:49.34#ibcon#about to read 5, iclass 38, count 2 2006.285.06:29:49.34#ibcon#read 5, iclass 38, count 2 2006.285.06:29:49.34#ibcon#about to read 6, iclass 38, count 2 2006.285.06:29:49.34#ibcon#read 6, iclass 38, count 2 2006.285.06:29:49.34#ibcon#end of sib2, iclass 38, count 2 2006.285.06:29:49.34#ibcon#*after write, iclass 38, count 2 2006.285.06:29:49.34#ibcon#*before return 0, iclass 38, count 2 2006.285.06:29:49.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:29:49.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:29:49.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.06:29:49.34#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:49.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:29:49.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:29:49.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:29:49.46#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:29:49.46#ibcon#first serial, iclass 38, count 0 2006.285.06:29:49.46#ibcon#enter sib2, iclass 38, count 0 2006.285.06:29:49.46#ibcon#flushed, iclass 38, count 0 2006.285.06:29:49.46#ibcon#about to write, iclass 38, count 0 2006.285.06:29:49.46#ibcon#wrote, iclass 38, count 0 2006.285.06:29:49.46#ibcon#about to read 3, iclass 38, count 0 2006.285.06:29:49.48#ibcon#read 3, iclass 38, count 0 2006.285.06:29:49.48#ibcon#about to read 4, iclass 38, count 0 2006.285.06:29:49.48#ibcon#read 4, iclass 38, count 0 2006.285.06:29:49.48#ibcon#about to read 5, iclass 38, count 0 2006.285.06:29:49.48#ibcon#read 5, iclass 38, count 0 2006.285.06:29:49.48#ibcon#about to read 6, iclass 38, count 0 2006.285.06:29:49.48#ibcon#read 6, iclass 38, count 0 2006.285.06:29:49.48#ibcon#end of sib2, iclass 38, count 0 2006.285.06:29:49.48#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:29:49.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:29:49.48#ibcon#[27=USB\r\n] 2006.285.06:29:49.48#ibcon#*before write, iclass 38, count 0 2006.285.06:29:49.48#ibcon#enter sib2, iclass 38, count 0 2006.285.06:29:49.48#ibcon#flushed, iclass 38, count 0 2006.285.06:29:49.48#ibcon#about to write, iclass 38, count 0 2006.285.06:29:49.48#ibcon#wrote, iclass 38, count 0 2006.285.06:29:49.48#ibcon#about to read 3, iclass 38, count 0 2006.285.06:29:49.51#ibcon#read 3, iclass 38, count 0 2006.285.06:29:49.51#ibcon#about to read 4, iclass 38, count 0 2006.285.06:29:49.51#ibcon#read 4, iclass 38, count 0 2006.285.06:29:49.51#ibcon#about to read 5, iclass 38, count 0 2006.285.06:29:49.51#ibcon#read 5, iclass 38, count 0 2006.285.06:29:49.51#ibcon#about to read 6, iclass 38, count 0 2006.285.06:29:49.51#ibcon#read 6, iclass 38, count 0 2006.285.06:29:49.51#ibcon#end of sib2, iclass 38, count 0 2006.285.06:29:49.51#ibcon#*after write, iclass 38, count 0 2006.285.06:29:49.51#ibcon#*before return 0, iclass 38, count 0 2006.285.06:29:49.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:29:49.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:29:49.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:29:49.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:29:49.51$vck44/vblo=4,679.99 2006.285.06:29:49.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.06:29:49.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.06:29:49.51#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:49.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:29:49.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:29:49.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:29:49.51#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:29:49.51#ibcon#first serial, iclass 40, count 0 2006.285.06:29:49.51#ibcon#enter sib2, iclass 40, count 0 2006.285.06:29:49.51#ibcon#flushed, iclass 40, count 0 2006.285.06:29:49.51#ibcon#about to write, iclass 40, count 0 2006.285.06:29:49.51#ibcon#wrote, iclass 40, count 0 2006.285.06:29:49.51#ibcon#about to read 3, iclass 40, count 0 2006.285.06:29:49.53#ibcon#read 3, iclass 40, count 0 2006.285.06:29:49.53#ibcon#about to read 4, iclass 40, count 0 2006.285.06:29:49.53#ibcon#read 4, iclass 40, count 0 2006.285.06:29:49.53#ibcon#about to read 5, iclass 40, count 0 2006.285.06:29:49.53#ibcon#read 5, iclass 40, count 0 2006.285.06:29:49.53#ibcon#about to read 6, iclass 40, count 0 2006.285.06:29:49.53#ibcon#read 6, iclass 40, count 0 2006.285.06:29:49.53#ibcon#end of sib2, iclass 40, count 0 2006.285.06:29:49.53#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:29:49.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:29:49.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:29:49.53#ibcon#*before write, iclass 40, count 0 2006.285.06:29:49.53#ibcon#enter sib2, iclass 40, count 0 2006.285.06:29:49.53#ibcon#flushed, iclass 40, count 0 2006.285.06:29:49.53#ibcon#about to write, iclass 40, count 0 2006.285.06:29:49.53#ibcon#wrote, iclass 40, count 0 2006.285.06:29:49.53#ibcon#about to read 3, iclass 40, count 0 2006.285.06:29:49.57#ibcon#read 3, iclass 40, count 0 2006.285.06:29:49.57#ibcon#about to read 4, iclass 40, count 0 2006.285.06:29:49.57#ibcon#read 4, iclass 40, count 0 2006.285.06:29:49.57#ibcon#about to read 5, iclass 40, count 0 2006.285.06:29:49.57#ibcon#read 5, iclass 40, count 0 2006.285.06:29:49.57#ibcon#about to read 6, iclass 40, count 0 2006.285.06:29:49.57#ibcon#read 6, iclass 40, count 0 2006.285.06:29:49.57#ibcon#end of sib2, iclass 40, count 0 2006.285.06:29:49.57#ibcon#*after write, iclass 40, count 0 2006.285.06:29:49.57#ibcon#*before return 0, iclass 40, count 0 2006.285.06:29:49.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:29:49.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:29:49.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:29:49.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:29:49.57$vck44/vb=4,5 2006.285.06:29:49.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.06:29:49.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.06:29:49.57#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:49.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:29:49.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:29:49.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:29:49.63#ibcon#enter wrdev, iclass 4, count 2 2006.285.06:29:49.63#ibcon#first serial, iclass 4, count 2 2006.285.06:29:49.63#ibcon#enter sib2, iclass 4, count 2 2006.285.06:29:49.63#ibcon#flushed, iclass 4, count 2 2006.285.06:29:49.63#ibcon#about to write, iclass 4, count 2 2006.285.06:29:49.63#ibcon#wrote, iclass 4, count 2 2006.285.06:29:49.63#ibcon#about to read 3, iclass 4, count 2 2006.285.06:29:49.65#ibcon#read 3, iclass 4, count 2 2006.285.06:29:49.65#ibcon#about to read 4, iclass 4, count 2 2006.285.06:29:49.65#ibcon#read 4, iclass 4, count 2 2006.285.06:29:49.65#ibcon#about to read 5, iclass 4, count 2 2006.285.06:29:49.65#ibcon#read 5, iclass 4, count 2 2006.285.06:29:49.65#ibcon#about to read 6, iclass 4, count 2 2006.285.06:29:49.65#ibcon#read 6, iclass 4, count 2 2006.285.06:29:49.65#ibcon#end of sib2, iclass 4, count 2 2006.285.06:29:49.65#ibcon#*mode == 0, iclass 4, count 2 2006.285.06:29:49.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.06:29:49.65#ibcon#[27=AT04-05\r\n] 2006.285.06:29:49.65#ibcon#*before write, iclass 4, count 2 2006.285.06:29:49.65#ibcon#enter sib2, iclass 4, count 2 2006.285.06:29:49.65#ibcon#flushed, iclass 4, count 2 2006.285.06:29:49.65#ibcon#about to write, iclass 4, count 2 2006.285.06:29:49.65#ibcon#wrote, iclass 4, count 2 2006.285.06:29:49.65#ibcon#about to read 3, iclass 4, count 2 2006.285.06:29:49.70#ibcon#read 3, iclass 4, count 2 2006.285.06:29:49.70#ibcon#about to read 4, iclass 4, count 2 2006.285.06:29:49.70#ibcon#read 4, iclass 4, count 2 2006.285.06:29:49.70#ibcon#about to read 5, iclass 4, count 2 2006.285.06:29:49.70#ibcon#read 5, iclass 4, count 2 2006.285.06:29:49.70#ibcon#about to read 6, iclass 4, count 2 2006.285.06:29:49.70#ibcon#read 6, iclass 4, count 2 2006.285.06:29:49.70#ibcon#end of sib2, iclass 4, count 2 2006.285.06:29:49.70#ibcon#*after write, iclass 4, count 2 2006.285.06:29:49.70#ibcon#*before return 0, iclass 4, count 2 2006.285.06:29:49.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:29:49.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:29:49.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.06:29:49.70#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:49.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:29:49.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:29:49.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:29:49.81#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:29:49.81#ibcon#first serial, iclass 4, count 0 2006.285.06:29:49.81#ibcon#enter sib2, iclass 4, count 0 2006.285.06:29:49.81#ibcon#flushed, iclass 4, count 0 2006.285.06:29:49.81#ibcon#about to write, iclass 4, count 0 2006.285.06:29:49.81#ibcon#wrote, iclass 4, count 0 2006.285.06:29:49.81#ibcon#about to read 3, iclass 4, count 0 2006.285.06:29:49.83#ibcon#read 3, iclass 4, count 0 2006.285.06:29:49.83#ibcon#about to read 4, iclass 4, count 0 2006.285.06:29:49.83#ibcon#read 4, iclass 4, count 0 2006.285.06:29:49.83#ibcon#about to read 5, iclass 4, count 0 2006.285.06:29:49.83#ibcon#read 5, iclass 4, count 0 2006.285.06:29:49.83#ibcon#about to read 6, iclass 4, count 0 2006.285.06:29:49.83#ibcon#read 6, iclass 4, count 0 2006.285.06:29:49.83#ibcon#end of sib2, iclass 4, count 0 2006.285.06:29:49.83#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:29:49.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:29:49.83#ibcon#[27=USB\r\n] 2006.285.06:29:49.83#ibcon#*before write, iclass 4, count 0 2006.285.06:29:49.83#ibcon#enter sib2, iclass 4, count 0 2006.285.06:29:49.83#ibcon#flushed, iclass 4, count 0 2006.285.06:29:49.83#ibcon#about to write, iclass 4, count 0 2006.285.06:29:49.83#ibcon#wrote, iclass 4, count 0 2006.285.06:29:49.83#ibcon#about to read 3, iclass 4, count 0 2006.285.06:29:49.86#ibcon#read 3, iclass 4, count 0 2006.285.06:29:49.86#ibcon#about to read 4, iclass 4, count 0 2006.285.06:29:49.86#ibcon#read 4, iclass 4, count 0 2006.285.06:29:49.86#ibcon#about to read 5, iclass 4, count 0 2006.285.06:29:49.86#ibcon#read 5, iclass 4, count 0 2006.285.06:29:49.86#ibcon#about to read 6, iclass 4, count 0 2006.285.06:29:49.86#ibcon#read 6, iclass 4, count 0 2006.285.06:29:49.86#ibcon#end of sib2, iclass 4, count 0 2006.285.06:29:49.86#ibcon#*after write, iclass 4, count 0 2006.285.06:29:49.86#ibcon#*before return 0, iclass 4, count 0 2006.285.06:29:49.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:29:49.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:29:49.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:29:49.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:29:49.86$vck44/vblo=5,709.99 2006.285.06:29:49.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.06:29:49.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.06:29:49.86#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:49.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:29:49.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:29:49.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:29:49.86#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:29:49.86#ibcon#first serial, iclass 6, count 0 2006.285.06:29:49.86#ibcon#enter sib2, iclass 6, count 0 2006.285.06:29:49.86#ibcon#flushed, iclass 6, count 0 2006.285.06:29:49.86#ibcon#about to write, iclass 6, count 0 2006.285.06:29:49.86#ibcon#wrote, iclass 6, count 0 2006.285.06:29:49.86#ibcon#about to read 3, iclass 6, count 0 2006.285.06:29:49.88#ibcon#read 3, iclass 6, count 0 2006.285.06:29:49.88#ibcon#about to read 4, iclass 6, count 0 2006.285.06:29:49.88#ibcon#read 4, iclass 6, count 0 2006.285.06:29:49.88#ibcon#about to read 5, iclass 6, count 0 2006.285.06:29:49.88#ibcon#read 5, iclass 6, count 0 2006.285.06:29:49.88#ibcon#about to read 6, iclass 6, count 0 2006.285.06:29:49.88#ibcon#read 6, iclass 6, count 0 2006.285.06:29:49.88#ibcon#end of sib2, iclass 6, count 0 2006.285.06:29:49.88#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:29:49.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:29:49.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:29:49.88#ibcon#*before write, iclass 6, count 0 2006.285.06:29:49.88#ibcon#enter sib2, iclass 6, count 0 2006.285.06:29:49.88#ibcon#flushed, iclass 6, count 0 2006.285.06:29:49.88#ibcon#about to write, iclass 6, count 0 2006.285.06:29:49.88#ibcon#wrote, iclass 6, count 0 2006.285.06:29:49.88#ibcon#about to read 3, iclass 6, count 0 2006.285.06:29:49.92#ibcon#read 3, iclass 6, count 0 2006.285.06:29:49.92#ibcon#about to read 4, iclass 6, count 0 2006.285.06:29:49.92#ibcon#read 4, iclass 6, count 0 2006.285.06:29:49.92#ibcon#about to read 5, iclass 6, count 0 2006.285.06:29:49.92#ibcon#read 5, iclass 6, count 0 2006.285.06:29:49.92#ibcon#about to read 6, iclass 6, count 0 2006.285.06:29:49.92#ibcon#read 6, iclass 6, count 0 2006.285.06:29:49.92#ibcon#end of sib2, iclass 6, count 0 2006.285.06:29:49.92#ibcon#*after write, iclass 6, count 0 2006.285.06:29:49.92#ibcon#*before return 0, iclass 6, count 0 2006.285.06:29:49.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:29:49.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:29:49.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:29:49.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:29:49.92$vck44/vb=5,4 2006.285.06:29:49.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.06:29:49.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.06:29:49.92#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:49.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:29:49.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:29:49.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:29:49.98#ibcon#enter wrdev, iclass 10, count 2 2006.285.06:29:49.98#ibcon#first serial, iclass 10, count 2 2006.285.06:29:49.98#ibcon#enter sib2, iclass 10, count 2 2006.285.06:29:49.98#ibcon#flushed, iclass 10, count 2 2006.285.06:29:49.98#ibcon#about to write, iclass 10, count 2 2006.285.06:29:49.98#ibcon#wrote, iclass 10, count 2 2006.285.06:29:49.98#ibcon#about to read 3, iclass 10, count 2 2006.285.06:29:50.00#ibcon#read 3, iclass 10, count 2 2006.285.06:29:50.00#ibcon#about to read 4, iclass 10, count 2 2006.285.06:29:50.00#ibcon#read 4, iclass 10, count 2 2006.285.06:29:50.00#ibcon#about to read 5, iclass 10, count 2 2006.285.06:29:50.00#ibcon#read 5, iclass 10, count 2 2006.285.06:29:50.00#ibcon#about to read 6, iclass 10, count 2 2006.285.06:29:50.00#ibcon#read 6, iclass 10, count 2 2006.285.06:29:50.00#ibcon#end of sib2, iclass 10, count 2 2006.285.06:29:50.00#ibcon#*mode == 0, iclass 10, count 2 2006.285.06:29:50.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.06:29:50.00#ibcon#[27=AT05-04\r\n] 2006.285.06:29:50.00#ibcon#*before write, iclass 10, count 2 2006.285.06:29:50.00#ibcon#enter sib2, iclass 10, count 2 2006.285.06:29:50.00#ibcon#flushed, iclass 10, count 2 2006.285.06:29:50.00#ibcon#about to write, iclass 10, count 2 2006.285.06:29:50.00#ibcon#wrote, iclass 10, count 2 2006.285.06:29:50.00#ibcon#about to read 3, iclass 10, count 2 2006.285.06:29:50.03#ibcon#read 3, iclass 10, count 2 2006.285.06:29:50.03#ibcon#about to read 4, iclass 10, count 2 2006.285.06:29:50.03#ibcon#read 4, iclass 10, count 2 2006.285.06:29:50.03#ibcon#about to read 5, iclass 10, count 2 2006.285.06:29:50.03#ibcon#read 5, iclass 10, count 2 2006.285.06:29:50.03#ibcon#about to read 6, iclass 10, count 2 2006.285.06:29:50.03#ibcon#read 6, iclass 10, count 2 2006.285.06:29:50.03#ibcon#end of sib2, iclass 10, count 2 2006.285.06:29:50.03#ibcon#*after write, iclass 10, count 2 2006.285.06:29:50.03#ibcon#*before return 0, iclass 10, count 2 2006.285.06:29:50.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:29:50.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:29:50.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.06:29:50.03#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:50.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:29:50.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:29:50.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:29:50.15#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:29:50.15#ibcon#first serial, iclass 10, count 0 2006.285.06:29:50.15#ibcon#enter sib2, iclass 10, count 0 2006.285.06:29:50.15#ibcon#flushed, iclass 10, count 0 2006.285.06:29:50.15#ibcon#about to write, iclass 10, count 0 2006.285.06:29:50.15#ibcon#wrote, iclass 10, count 0 2006.285.06:29:50.15#ibcon#about to read 3, iclass 10, count 0 2006.285.06:29:50.17#ibcon#read 3, iclass 10, count 0 2006.285.06:29:50.17#ibcon#about to read 4, iclass 10, count 0 2006.285.06:29:50.17#ibcon#read 4, iclass 10, count 0 2006.285.06:29:50.17#ibcon#about to read 5, iclass 10, count 0 2006.285.06:29:50.17#ibcon#read 5, iclass 10, count 0 2006.285.06:29:50.17#ibcon#about to read 6, iclass 10, count 0 2006.285.06:29:50.17#ibcon#read 6, iclass 10, count 0 2006.285.06:29:50.17#ibcon#end of sib2, iclass 10, count 0 2006.285.06:29:50.17#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:29:50.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:29:50.17#ibcon#[27=USB\r\n] 2006.285.06:29:50.17#ibcon#*before write, iclass 10, count 0 2006.285.06:29:50.17#ibcon#enter sib2, iclass 10, count 0 2006.285.06:29:50.17#ibcon#flushed, iclass 10, count 0 2006.285.06:29:50.17#ibcon#about to write, iclass 10, count 0 2006.285.06:29:50.17#ibcon#wrote, iclass 10, count 0 2006.285.06:29:50.17#ibcon#about to read 3, iclass 10, count 0 2006.285.06:29:50.20#ibcon#read 3, iclass 10, count 0 2006.285.06:29:50.20#ibcon#about to read 4, iclass 10, count 0 2006.285.06:29:50.20#ibcon#read 4, iclass 10, count 0 2006.285.06:29:50.20#ibcon#about to read 5, iclass 10, count 0 2006.285.06:29:50.20#ibcon#read 5, iclass 10, count 0 2006.285.06:29:50.20#ibcon#about to read 6, iclass 10, count 0 2006.285.06:29:50.20#ibcon#read 6, iclass 10, count 0 2006.285.06:29:50.20#ibcon#end of sib2, iclass 10, count 0 2006.285.06:29:50.20#ibcon#*after write, iclass 10, count 0 2006.285.06:29:50.20#ibcon#*before return 0, iclass 10, count 0 2006.285.06:29:50.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:29:50.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:29:50.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:29:50.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:29:50.20$vck44/vblo=6,719.99 2006.285.06:29:50.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.06:29:50.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.06:29:50.20#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:50.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:29:50.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:29:50.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:29:50.20#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:29:50.20#ibcon#first serial, iclass 12, count 0 2006.285.06:29:50.20#ibcon#enter sib2, iclass 12, count 0 2006.285.06:29:50.20#ibcon#flushed, iclass 12, count 0 2006.285.06:29:50.20#ibcon#about to write, iclass 12, count 0 2006.285.06:29:50.20#ibcon#wrote, iclass 12, count 0 2006.285.06:29:50.20#ibcon#about to read 3, iclass 12, count 0 2006.285.06:29:50.22#ibcon#read 3, iclass 12, count 0 2006.285.06:29:50.22#ibcon#about to read 4, iclass 12, count 0 2006.285.06:29:50.22#ibcon#read 4, iclass 12, count 0 2006.285.06:29:50.22#ibcon#about to read 5, iclass 12, count 0 2006.285.06:29:50.22#ibcon#read 5, iclass 12, count 0 2006.285.06:29:50.22#ibcon#about to read 6, iclass 12, count 0 2006.285.06:29:50.22#ibcon#read 6, iclass 12, count 0 2006.285.06:29:50.22#ibcon#end of sib2, iclass 12, count 0 2006.285.06:29:50.22#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:29:50.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:29:50.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:29:50.22#ibcon#*before write, iclass 12, count 0 2006.285.06:29:50.22#ibcon#enter sib2, iclass 12, count 0 2006.285.06:29:50.22#ibcon#flushed, iclass 12, count 0 2006.285.06:29:50.22#ibcon#about to write, iclass 12, count 0 2006.285.06:29:50.22#ibcon#wrote, iclass 12, count 0 2006.285.06:29:50.22#ibcon#about to read 3, iclass 12, count 0 2006.285.06:29:50.26#ibcon#read 3, iclass 12, count 0 2006.285.06:29:50.26#ibcon#about to read 4, iclass 12, count 0 2006.285.06:29:50.26#ibcon#read 4, iclass 12, count 0 2006.285.06:29:50.26#ibcon#about to read 5, iclass 12, count 0 2006.285.06:29:50.26#ibcon#read 5, iclass 12, count 0 2006.285.06:29:50.26#ibcon#about to read 6, iclass 12, count 0 2006.285.06:29:50.26#ibcon#read 6, iclass 12, count 0 2006.285.06:29:50.26#ibcon#end of sib2, iclass 12, count 0 2006.285.06:29:50.26#ibcon#*after write, iclass 12, count 0 2006.285.06:29:50.26#ibcon#*before return 0, iclass 12, count 0 2006.285.06:29:50.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:29:50.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:29:50.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:29:50.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:29:50.26$vck44/vb=6,3 2006.285.06:29:50.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.06:29:50.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.06:29:50.26#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:50.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:29:50.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:29:50.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:29:50.32#ibcon#enter wrdev, iclass 14, count 2 2006.285.06:29:50.32#ibcon#first serial, iclass 14, count 2 2006.285.06:29:50.32#ibcon#enter sib2, iclass 14, count 2 2006.285.06:29:50.32#ibcon#flushed, iclass 14, count 2 2006.285.06:29:50.32#ibcon#about to write, iclass 14, count 2 2006.285.06:29:50.32#ibcon#wrote, iclass 14, count 2 2006.285.06:29:50.32#ibcon#about to read 3, iclass 14, count 2 2006.285.06:29:50.34#ibcon#read 3, iclass 14, count 2 2006.285.06:29:50.34#ibcon#about to read 4, iclass 14, count 2 2006.285.06:29:50.34#ibcon#read 4, iclass 14, count 2 2006.285.06:29:50.34#ibcon#about to read 5, iclass 14, count 2 2006.285.06:29:50.34#ibcon#read 5, iclass 14, count 2 2006.285.06:29:50.34#ibcon#about to read 6, iclass 14, count 2 2006.285.06:29:50.34#ibcon#read 6, iclass 14, count 2 2006.285.06:29:50.34#ibcon#end of sib2, iclass 14, count 2 2006.285.06:29:50.34#ibcon#*mode == 0, iclass 14, count 2 2006.285.06:29:50.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.06:29:50.34#ibcon#[27=AT06-03\r\n] 2006.285.06:29:50.34#ibcon#*before write, iclass 14, count 2 2006.285.06:29:50.34#ibcon#enter sib2, iclass 14, count 2 2006.285.06:29:50.34#ibcon#flushed, iclass 14, count 2 2006.285.06:29:50.34#ibcon#about to write, iclass 14, count 2 2006.285.06:29:50.34#ibcon#wrote, iclass 14, count 2 2006.285.06:29:50.34#ibcon#about to read 3, iclass 14, count 2 2006.285.06:29:50.37#ibcon#read 3, iclass 14, count 2 2006.285.06:29:50.37#ibcon#about to read 4, iclass 14, count 2 2006.285.06:29:50.37#ibcon#read 4, iclass 14, count 2 2006.285.06:29:50.37#ibcon#about to read 5, iclass 14, count 2 2006.285.06:29:50.37#ibcon#read 5, iclass 14, count 2 2006.285.06:29:50.37#ibcon#about to read 6, iclass 14, count 2 2006.285.06:29:50.37#ibcon#read 6, iclass 14, count 2 2006.285.06:29:50.37#ibcon#end of sib2, iclass 14, count 2 2006.285.06:29:50.37#ibcon#*after write, iclass 14, count 2 2006.285.06:29:50.37#ibcon#*before return 0, iclass 14, count 2 2006.285.06:29:50.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:29:50.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:29:50.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.06:29:50.37#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:50.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:29:50.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:29:50.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:29:50.49#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:29:50.49#ibcon#first serial, iclass 14, count 0 2006.285.06:29:50.49#ibcon#enter sib2, iclass 14, count 0 2006.285.06:29:50.49#ibcon#flushed, iclass 14, count 0 2006.285.06:29:50.49#ibcon#about to write, iclass 14, count 0 2006.285.06:29:50.49#ibcon#wrote, iclass 14, count 0 2006.285.06:29:50.49#ibcon#about to read 3, iclass 14, count 0 2006.285.06:29:50.51#ibcon#read 3, iclass 14, count 0 2006.285.06:29:50.51#ibcon#about to read 4, iclass 14, count 0 2006.285.06:29:50.51#ibcon#read 4, iclass 14, count 0 2006.285.06:29:50.51#ibcon#about to read 5, iclass 14, count 0 2006.285.06:29:50.51#ibcon#read 5, iclass 14, count 0 2006.285.06:29:50.51#ibcon#about to read 6, iclass 14, count 0 2006.285.06:29:50.51#ibcon#read 6, iclass 14, count 0 2006.285.06:29:50.51#ibcon#end of sib2, iclass 14, count 0 2006.285.06:29:50.51#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:29:50.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:29:50.51#ibcon#[27=USB\r\n] 2006.285.06:29:50.51#ibcon#*before write, iclass 14, count 0 2006.285.06:29:50.51#ibcon#enter sib2, iclass 14, count 0 2006.285.06:29:50.51#ibcon#flushed, iclass 14, count 0 2006.285.06:29:50.51#ibcon#about to write, iclass 14, count 0 2006.285.06:29:50.51#ibcon#wrote, iclass 14, count 0 2006.285.06:29:50.51#ibcon#about to read 3, iclass 14, count 0 2006.285.06:29:50.54#ibcon#read 3, iclass 14, count 0 2006.285.06:29:50.54#ibcon#about to read 4, iclass 14, count 0 2006.285.06:29:50.54#ibcon#read 4, iclass 14, count 0 2006.285.06:29:50.54#ibcon#about to read 5, iclass 14, count 0 2006.285.06:29:50.54#ibcon#read 5, iclass 14, count 0 2006.285.06:29:50.54#ibcon#about to read 6, iclass 14, count 0 2006.285.06:29:50.54#ibcon#read 6, iclass 14, count 0 2006.285.06:29:50.54#ibcon#end of sib2, iclass 14, count 0 2006.285.06:29:50.54#ibcon#*after write, iclass 14, count 0 2006.285.06:29:50.54#ibcon#*before return 0, iclass 14, count 0 2006.285.06:29:50.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:29:50.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:29:50.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:29:50.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:29:50.54$vck44/vblo=7,734.99 2006.285.06:29:50.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.06:29:50.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.06:29:50.54#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:50.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:29:50.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:29:50.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:29:50.54#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:29:50.54#ibcon#first serial, iclass 16, count 0 2006.285.06:29:50.54#ibcon#enter sib2, iclass 16, count 0 2006.285.06:29:50.54#ibcon#flushed, iclass 16, count 0 2006.285.06:29:50.54#ibcon#about to write, iclass 16, count 0 2006.285.06:29:50.54#ibcon#wrote, iclass 16, count 0 2006.285.06:29:50.54#ibcon#about to read 3, iclass 16, count 0 2006.285.06:29:50.56#ibcon#read 3, iclass 16, count 0 2006.285.06:29:50.56#ibcon#about to read 4, iclass 16, count 0 2006.285.06:29:50.56#ibcon#read 4, iclass 16, count 0 2006.285.06:29:50.56#ibcon#about to read 5, iclass 16, count 0 2006.285.06:29:50.56#ibcon#read 5, iclass 16, count 0 2006.285.06:29:50.56#ibcon#about to read 6, iclass 16, count 0 2006.285.06:29:50.56#ibcon#read 6, iclass 16, count 0 2006.285.06:29:50.56#ibcon#end of sib2, iclass 16, count 0 2006.285.06:29:50.56#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:29:50.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:29:50.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:29:50.56#ibcon#*before write, iclass 16, count 0 2006.285.06:29:50.56#ibcon#enter sib2, iclass 16, count 0 2006.285.06:29:50.56#ibcon#flushed, iclass 16, count 0 2006.285.06:29:50.56#ibcon#about to write, iclass 16, count 0 2006.285.06:29:50.56#ibcon#wrote, iclass 16, count 0 2006.285.06:29:50.56#ibcon#about to read 3, iclass 16, count 0 2006.285.06:29:50.60#ibcon#read 3, iclass 16, count 0 2006.285.06:29:50.60#ibcon#about to read 4, iclass 16, count 0 2006.285.06:29:50.60#ibcon#read 4, iclass 16, count 0 2006.285.06:29:50.60#ibcon#about to read 5, iclass 16, count 0 2006.285.06:29:50.60#ibcon#read 5, iclass 16, count 0 2006.285.06:29:50.60#ibcon#about to read 6, iclass 16, count 0 2006.285.06:29:50.60#ibcon#read 6, iclass 16, count 0 2006.285.06:29:50.60#ibcon#end of sib2, iclass 16, count 0 2006.285.06:29:50.60#ibcon#*after write, iclass 16, count 0 2006.285.06:29:50.60#ibcon#*before return 0, iclass 16, count 0 2006.285.06:29:50.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:29:50.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:29:50.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:29:50.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:29:50.60$vck44/vb=7,4 2006.285.06:29:50.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.06:29:50.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.06:29:50.60#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:50.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:29:50.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:29:50.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:29:50.66#ibcon#enter wrdev, iclass 18, count 2 2006.285.06:29:50.66#ibcon#first serial, iclass 18, count 2 2006.285.06:29:50.66#ibcon#enter sib2, iclass 18, count 2 2006.285.06:29:50.66#ibcon#flushed, iclass 18, count 2 2006.285.06:29:50.66#ibcon#about to write, iclass 18, count 2 2006.285.06:29:50.66#ibcon#wrote, iclass 18, count 2 2006.285.06:29:50.66#ibcon#about to read 3, iclass 18, count 2 2006.285.06:29:50.70#ibcon#read 3, iclass 18, count 2 2006.285.06:29:50.70#ibcon#about to read 4, iclass 18, count 2 2006.285.06:29:50.70#ibcon#read 4, iclass 18, count 2 2006.285.06:29:50.70#ibcon#about to read 5, iclass 18, count 2 2006.285.06:29:50.70#ibcon#read 5, iclass 18, count 2 2006.285.06:29:50.70#ibcon#about to read 6, iclass 18, count 2 2006.285.06:29:50.70#ibcon#read 6, iclass 18, count 2 2006.285.06:29:50.70#ibcon#end of sib2, iclass 18, count 2 2006.285.06:29:50.70#ibcon#*mode == 0, iclass 18, count 2 2006.285.06:29:50.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.06:29:50.70#ibcon#[27=AT07-04\r\n] 2006.285.06:29:50.70#ibcon#*before write, iclass 18, count 2 2006.285.06:29:50.70#ibcon#enter sib2, iclass 18, count 2 2006.285.06:29:50.70#ibcon#flushed, iclass 18, count 2 2006.285.06:29:50.70#ibcon#about to write, iclass 18, count 2 2006.285.06:29:50.70#ibcon#wrote, iclass 18, count 2 2006.285.06:29:50.70#ibcon#about to read 3, iclass 18, count 2 2006.285.06:29:50.73#ibcon#read 3, iclass 18, count 2 2006.285.06:29:50.73#ibcon#about to read 4, iclass 18, count 2 2006.285.06:29:50.73#ibcon#read 4, iclass 18, count 2 2006.285.06:29:50.73#ibcon#about to read 5, iclass 18, count 2 2006.285.06:29:50.73#ibcon#read 5, iclass 18, count 2 2006.285.06:29:50.73#ibcon#about to read 6, iclass 18, count 2 2006.285.06:29:50.73#ibcon#read 6, iclass 18, count 2 2006.285.06:29:50.73#ibcon#end of sib2, iclass 18, count 2 2006.285.06:29:50.73#ibcon#*after write, iclass 18, count 2 2006.285.06:29:50.73#ibcon#*before return 0, iclass 18, count 2 2006.285.06:29:50.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:29:50.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:29:50.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.06:29:50.73#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:50.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:29:50.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:29:50.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:29:50.85#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:29:50.85#ibcon#first serial, iclass 18, count 0 2006.285.06:29:50.85#ibcon#enter sib2, iclass 18, count 0 2006.285.06:29:50.85#ibcon#flushed, iclass 18, count 0 2006.285.06:29:50.85#ibcon#about to write, iclass 18, count 0 2006.285.06:29:50.85#ibcon#wrote, iclass 18, count 0 2006.285.06:29:50.85#ibcon#about to read 3, iclass 18, count 0 2006.285.06:29:50.87#ibcon#read 3, iclass 18, count 0 2006.285.06:29:50.87#ibcon#about to read 4, iclass 18, count 0 2006.285.06:29:50.87#ibcon#read 4, iclass 18, count 0 2006.285.06:29:50.87#ibcon#about to read 5, iclass 18, count 0 2006.285.06:29:50.87#ibcon#read 5, iclass 18, count 0 2006.285.06:29:50.87#ibcon#about to read 6, iclass 18, count 0 2006.285.06:29:50.87#ibcon#read 6, iclass 18, count 0 2006.285.06:29:50.87#ibcon#end of sib2, iclass 18, count 0 2006.285.06:29:50.87#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:29:50.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:29:50.87#ibcon#[27=USB\r\n] 2006.285.06:29:50.87#ibcon#*before write, iclass 18, count 0 2006.285.06:29:50.87#ibcon#enter sib2, iclass 18, count 0 2006.285.06:29:50.87#ibcon#flushed, iclass 18, count 0 2006.285.06:29:50.87#ibcon#about to write, iclass 18, count 0 2006.285.06:29:50.87#ibcon#wrote, iclass 18, count 0 2006.285.06:29:50.87#ibcon#about to read 3, iclass 18, count 0 2006.285.06:29:50.90#ibcon#read 3, iclass 18, count 0 2006.285.06:29:50.90#ibcon#about to read 4, iclass 18, count 0 2006.285.06:29:50.90#ibcon#read 4, iclass 18, count 0 2006.285.06:29:50.90#ibcon#about to read 5, iclass 18, count 0 2006.285.06:29:50.90#ibcon#read 5, iclass 18, count 0 2006.285.06:29:50.90#ibcon#about to read 6, iclass 18, count 0 2006.285.06:29:50.90#ibcon#read 6, iclass 18, count 0 2006.285.06:29:50.90#ibcon#end of sib2, iclass 18, count 0 2006.285.06:29:50.90#ibcon#*after write, iclass 18, count 0 2006.285.06:29:50.90#ibcon#*before return 0, iclass 18, count 0 2006.285.06:29:50.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:29:50.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:29:50.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:29:50.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:29:50.90$vck44/vblo=8,744.99 2006.285.06:29:50.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.06:29:50.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.06:29:50.90#ibcon#ireg 17 cls_cnt 0 2006.285.06:29:50.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:29:50.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:29:50.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:29:50.90#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:29:50.90#ibcon#first serial, iclass 20, count 0 2006.285.06:29:50.90#ibcon#enter sib2, iclass 20, count 0 2006.285.06:29:50.90#ibcon#flushed, iclass 20, count 0 2006.285.06:29:50.90#ibcon#about to write, iclass 20, count 0 2006.285.06:29:50.90#ibcon#wrote, iclass 20, count 0 2006.285.06:29:50.90#ibcon#about to read 3, iclass 20, count 0 2006.285.06:29:50.92#ibcon#read 3, iclass 20, count 0 2006.285.06:29:50.92#ibcon#about to read 4, iclass 20, count 0 2006.285.06:29:50.92#ibcon#read 4, iclass 20, count 0 2006.285.06:29:50.92#ibcon#about to read 5, iclass 20, count 0 2006.285.06:29:50.92#ibcon#read 5, iclass 20, count 0 2006.285.06:29:50.92#ibcon#about to read 6, iclass 20, count 0 2006.285.06:29:50.92#ibcon#read 6, iclass 20, count 0 2006.285.06:29:50.92#ibcon#end of sib2, iclass 20, count 0 2006.285.06:29:50.92#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:29:50.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:29:50.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:29:50.92#ibcon#*before write, iclass 20, count 0 2006.285.06:29:50.92#ibcon#enter sib2, iclass 20, count 0 2006.285.06:29:50.92#ibcon#flushed, iclass 20, count 0 2006.285.06:29:50.92#ibcon#about to write, iclass 20, count 0 2006.285.06:29:50.92#ibcon#wrote, iclass 20, count 0 2006.285.06:29:50.92#ibcon#about to read 3, iclass 20, count 0 2006.285.06:29:50.96#ibcon#read 3, iclass 20, count 0 2006.285.06:29:50.96#ibcon#about to read 4, iclass 20, count 0 2006.285.06:29:50.96#ibcon#read 4, iclass 20, count 0 2006.285.06:29:50.96#ibcon#about to read 5, iclass 20, count 0 2006.285.06:29:50.96#ibcon#read 5, iclass 20, count 0 2006.285.06:29:50.96#ibcon#about to read 6, iclass 20, count 0 2006.285.06:29:50.96#ibcon#read 6, iclass 20, count 0 2006.285.06:29:50.96#ibcon#end of sib2, iclass 20, count 0 2006.285.06:29:50.96#ibcon#*after write, iclass 20, count 0 2006.285.06:29:50.96#ibcon#*before return 0, iclass 20, count 0 2006.285.06:29:50.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:29:50.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:29:50.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:29:50.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:29:50.96$vck44/vb=8,4 2006.285.06:29:50.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.06:29:50.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.06:29:50.96#ibcon#ireg 11 cls_cnt 2 2006.285.06:29:50.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:29:51.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:29:51.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:29:51.02#ibcon#enter wrdev, iclass 22, count 2 2006.285.06:29:51.02#ibcon#first serial, iclass 22, count 2 2006.285.06:29:51.02#ibcon#enter sib2, iclass 22, count 2 2006.285.06:29:51.02#ibcon#flushed, iclass 22, count 2 2006.285.06:29:51.02#ibcon#about to write, iclass 22, count 2 2006.285.06:29:51.02#ibcon#wrote, iclass 22, count 2 2006.285.06:29:51.02#ibcon#about to read 3, iclass 22, count 2 2006.285.06:29:51.04#ibcon#read 3, iclass 22, count 2 2006.285.06:29:51.04#ibcon#about to read 4, iclass 22, count 2 2006.285.06:29:51.04#ibcon#read 4, iclass 22, count 2 2006.285.06:29:51.04#ibcon#about to read 5, iclass 22, count 2 2006.285.06:29:51.04#ibcon#read 5, iclass 22, count 2 2006.285.06:29:51.04#ibcon#about to read 6, iclass 22, count 2 2006.285.06:29:51.04#ibcon#read 6, iclass 22, count 2 2006.285.06:29:51.04#ibcon#end of sib2, iclass 22, count 2 2006.285.06:29:51.04#ibcon#*mode == 0, iclass 22, count 2 2006.285.06:29:51.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.06:29:51.04#ibcon#[27=AT08-04\r\n] 2006.285.06:29:51.04#ibcon#*before write, iclass 22, count 2 2006.285.06:29:51.04#ibcon#enter sib2, iclass 22, count 2 2006.285.06:29:51.04#ibcon#flushed, iclass 22, count 2 2006.285.06:29:51.04#ibcon#about to write, iclass 22, count 2 2006.285.06:29:51.04#ibcon#wrote, iclass 22, count 2 2006.285.06:29:51.04#ibcon#about to read 3, iclass 22, count 2 2006.285.06:29:51.07#ibcon#read 3, iclass 22, count 2 2006.285.06:29:51.07#ibcon#about to read 4, iclass 22, count 2 2006.285.06:29:51.07#ibcon#read 4, iclass 22, count 2 2006.285.06:29:51.07#ibcon#about to read 5, iclass 22, count 2 2006.285.06:29:51.07#ibcon#read 5, iclass 22, count 2 2006.285.06:29:51.07#ibcon#about to read 6, iclass 22, count 2 2006.285.06:29:51.07#ibcon#read 6, iclass 22, count 2 2006.285.06:29:51.07#ibcon#end of sib2, iclass 22, count 2 2006.285.06:29:51.07#ibcon#*after write, iclass 22, count 2 2006.285.06:29:51.07#ibcon#*before return 0, iclass 22, count 2 2006.285.06:29:51.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:29:51.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:29:51.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.06:29:51.07#ibcon#ireg 7 cls_cnt 0 2006.285.06:29:51.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:29:51.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:29:51.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:29:51.19#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:29:51.19#ibcon#first serial, iclass 22, count 0 2006.285.06:29:51.19#ibcon#enter sib2, iclass 22, count 0 2006.285.06:29:51.19#ibcon#flushed, iclass 22, count 0 2006.285.06:29:51.19#ibcon#about to write, iclass 22, count 0 2006.285.06:29:51.19#ibcon#wrote, iclass 22, count 0 2006.285.06:29:51.19#ibcon#about to read 3, iclass 22, count 0 2006.285.06:29:51.21#ibcon#read 3, iclass 22, count 0 2006.285.06:29:51.21#ibcon#about to read 4, iclass 22, count 0 2006.285.06:29:51.21#ibcon#read 4, iclass 22, count 0 2006.285.06:29:51.21#ibcon#about to read 5, iclass 22, count 0 2006.285.06:29:51.21#ibcon#read 5, iclass 22, count 0 2006.285.06:29:51.21#ibcon#about to read 6, iclass 22, count 0 2006.285.06:29:51.21#ibcon#read 6, iclass 22, count 0 2006.285.06:29:51.21#ibcon#end of sib2, iclass 22, count 0 2006.285.06:29:51.21#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:29:51.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:29:51.21#ibcon#[27=USB\r\n] 2006.285.06:29:51.21#ibcon#*before write, iclass 22, count 0 2006.285.06:29:51.21#ibcon#enter sib2, iclass 22, count 0 2006.285.06:29:51.21#ibcon#flushed, iclass 22, count 0 2006.285.06:29:51.21#ibcon#about to write, iclass 22, count 0 2006.285.06:29:51.21#ibcon#wrote, iclass 22, count 0 2006.285.06:29:51.21#ibcon#about to read 3, iclass 22, count 0 2006.285.06:29:51.24#ibcon#read 3, iclass 22, count 0 2006.285.06:29:51.24#ibcon#about to read 4, iclass 22, count 0 2006.285.06:29:51.24#ibcon#read 4, iclass 22, count 0 2006.285.06:29:51.24#ibcon#about to read 5, iclass 22, count 0 2006.285.06:29:51.24#ibcon#read 5, iclass 22, count 0 2006.285.06:29:51.24#ibcon#about to read 6, iclass 22, count 0 2006.285.06:29:51.24#ibcon#read 6, iclass 22, count 0 2006.285.06:29:51.24#ibcon#end of sib2, iclass 22, count 0 2006.285.06:29:51.24#ibcon#*after write, iclass 22, count 0 2006.285.06:29:51.24#ibcon#*before return 0, iclass 22, count 0 2006.285.06:29:51.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:29:51.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:29:51.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:29:51.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:29:51.24$vck44/vabw=wide 2006.285.06:29:51.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.06:29:51.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.06:29:51.24#ibcon#ireg 8 cls_cnt 0 2006.285.06:29:51.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:29:51.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:29:51.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:29:51.24#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:29:51.24#ibcon#first serial, iclass 24, count 0 2006.285.06:29:51.24#ibcon#enter sib2, iclass 24, count 0 2006.285.06:29:51.24#ibcon#flushed, iclass 24, count 0 2006.285.06:29:51.24#ibcon#about to write, iclass 24, count 0 2006.285.06:29:51.24#ibcon#wrote, iclass 24, count 0 2006.285.06:29:51.24#ibcon#about to read 3, iclass 24, count 0 2006.285.06:29:51.26#ibcon#read 3, iclass 24, count 0 2006.285.06:29:51.26#ibcon#about to read 4, iclass 24, count 0 2006.285.06:29:51.26#ibcon#read 4, iclass 24, count 0 2006.285.06:29:51.26#ibcon#about to read 5, iclass 24, count 0 2006.285.06:29:51.26#ibcon#read 5, iclass 24, count 0 2006.285.06:29:51.26#ibcon#about to read 6, iclass 24, count 0 2006.285.06:29:51.26#ibcon#read 6, iclass 24, count 0 2006.285.06:29:51.26#ibcon#end of sib2, iclass 24, count 0 2006.285.06:29:51.26#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:29:51.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:29:51.26#ibcon#[25=BW32\r\n] 2006.285.06:29:51.26#ibcon#*before write, iclass 24, count 0 2006.285.06:29:51.26#ibcon#enter sib2, iclass 24, count 0 2006.285.06:29:51.26#ibcon#flushed, iclass 24, count 0 2006.285.06:29:51.26#ibcon#about to write, iclass 24, count 0 2006.285.06:29:51.26#ibcon#wrote, iclass 24, count 0 2006.285.06:29:51.26#ibcon#about to read 3, iclass 24, count 0 2006.285.06:29:51.29#ibcon#read 3, iclass 24, count 0 2006.285.06:29:51.29#ibcon#about to read 4, iclass 24, count 0 2006.285.06:29:51.29#ibcon#read 4, iclass 24, count 0 2006.285.06:29:51.29#ibcon#about to read 5, iclass 24, count 0 2006.285.06:29:51.29#ibcon#read 5, iclass 24, count 0 2006.285.06:29:51.29#ibcon#about to read 6, iclass 24, count 0 2006.285.06:29:51.29#ibcon#read 6, iclass 24, count 0 2006.285.06:29:51.29#ibcon#end of sib2, iclass 24, count 0 2006.285.06:29:51.29#ibcon#*after write, iclass 24, count 0 2006.285.06:29:51.29#ibcon#*before return 0, iclass 24, count 0 2006.285.06:29:51.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:29:51.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:29:51.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:29:51.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:29:51.29$vck44/vbbw=wide 2006.285.06:29:51.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.06:29:51.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.06:29:51.29#ibcon#ireg 8 cls_cnt 0 2006.285.06:29:51.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:29:51.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:29:51.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:29:51.36#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:29:51.36#ibcon#first serial, iclass 26, count 0 2006.285.06:29:51.36#ibcon#enter sib2, iclass 26, count 0 2006.285.06:29:51.36#ibcon#flushed, iclass 26, count 0 2006.285.06:29:51.36#ibcon#about to write, iclass 26, count 0 2006.285.06:29:51.36#ibcon#wrote, iclass 26, count 0 2006.285.06:29:51.36#ibcon#about to read 3, iclass 26, count 0 2006.285.06:29:51.38#ibcon#read 3, iclass 26, count 0 2006.285.06:29:51.38#ibcon#about to read 4, iclass 26, count 0 2006.285.06:29:51.38#ibcon#read 4, iclass 26, count 0 2006.285.06:29:51.38#ibcon#about to read 5, iclass 26, count 0 2006.285.06:29:51.38#ibcon#read 5, iclass 26, count 0 2006.285.06:29:51.38#ibcon#about to read 6, iclass 26, count 0 2006.285.06:29:51.38#ibcon#read 6, iclass 26, count 0 2006.285.06:29:51.38#ibcon#end of sib2, iclass 26, count 0 2006.285.06:29:51.38#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:29:51.38#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:29:51.38#ibcon#[27=BW32\r\n] 2006.285.06:29:51.38#ibcon#*before write, iclass 26, count 0 2006.285.06:29:51.38#ibcon#enter sib2, iclass 26, count 0 2006.285.06:29:51.38#ibcon#flushed, iclass 26, count 0 2006.285.06:29:51.38#ibcon#about to write, iclass 26, count 0 2006.285.06:29:51.38#ibcon#wrote, iclass 26, count 0 2006.285.06:29:51.38#ibcon#about to read 3, iclass 26, count 0 2006.285.06:29:51.41#ibcon#read 3, iclass 26, count 0 2006.285.06:29:51.41#ibcon#about to read 4, iclass 26, count 0 2006.285.06:29:51.41#ibcon#read 4, iclass 26, count 0 2006.285.06:29:51.41#ibcon#about to read 5, iclass 26, count 0 2006.285.06:29:51.41#ibcon#read 5, iclass 26, count 0 2006.285.06:29:51.41#ibcon#about to read 6, iclass 26, count 0 2006.285.06:29:51.41#ibcon#read 6, iclass 26, count 0 2006.285.06:29:51.41#ibcon#end of sib2, iclass 26, count 0 2006.285.06:29:51.41#ibcon#*after write, iclass 26, count 0 2006.285.06:29:51.41#ibcon#*before return 0, iclass 26, count 0 2006.285.06:29:51.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:29:51.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:29:51.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:29:51.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:29:51.41$setupk4/ifdk4 2006.285.06:29:51.41$ifdk4/lo= 2006.285.06:29:51.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:29:51.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:29:51.42$ifdk4/patch= 2006.285.06:29:51.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:29:51.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:29:51.42$setupk4/!*+20s 2006.285.06:29:52.58#abcon#<5=/05 4.8 7.6 24.90 681014.0\r\n> 2006.285.06:29:52.60#abcon#{5=INTERFACE CLEAR} 2006.285.06:29:52.66#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:30:02.75#abcon#<5=/05 4.8 7.6 24.90 681014.0\r\n> 2006.285.06:30:02.77#abcon#{5=INTERFACE CLEAR} 2006.285.06:30:02.83#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:30:05.89$setupk4/"tpicd 2006.285.06:30:05.89$setupk4/echo=off 2006.285.06:30:05.89$setupk4/xlog=off 2006.285.06:30:05.89:!2006.285.06:30:45 2006.285.06:30:25.14#trakl#Source acquired 2006.285.06:30:25.14#flagr#flagr/antenna,acquired 2006.285.06:30:45.00:preob 2006.285.06:30:45.13/onsource/TRACKING 2006.285.06:30:45.13:!2006.285.06:30:55 2006.285.06:30:55.00:"tape 2006.285.06:30:55.00:"st=record 2006.285.06:30:55.00:data_valid=on 2006.285.06:30:55.00:midob 2006.285.06:30:55.13/onsource/TRACKING 2006.285.06:30:55.14/wx/24.89,1014.0,67 2006.285.06:30:55.27/cable/+6.4746E-03 2006.285.06:30:56.36/va/01,07,usb,yes,42,46 2006.285.06:30:56.36/va/02,06,usb,yes,42,43 2006.285.06:30:56.36/va/03,07,usb,yes,42,44 2006.285.06:30:56.36/va/04,06,usb,yes,44,46 2006.285.06:30:56.36/va/05,03,usb,yes,43,44 2006.285.06:30:56.36/va/06,04,usb,yes,39,39 2006.285.06:30:56.36/va/07,04,usb,yes,40,41 2006.285.06:30:56.36/va/08,03,usb,yes,41,49 2006.285.06:30:56.59/valo/01,524.99,yes,locked 2006.285.06:30:56.59/valo/02,534.99,yes,locked 2006.285.06:30:56.59/valo/03,564.99,yes,locked 2006.285.06:30:56.59/valo/04,624.99,yes,locked 2006.285.06:30:56.59/valo/05,734.99,yes,locked 2006.285.06:30:56.59/valo/06,814.99,yes,locked 2006.285.06:30:56.59/valo/07,864.99,yes,locked 2006.285.06:30:56.59/valo/08,884.99,yes,locked 2006.285.06:30:57.68/vb/01,04,usb,yes,35,76 2006.285.06:30:57.68/vb/02,05,usb,yes,32,79 2006.285.06:30:57.68/vb/03,04,usb,yes,33,52 2006.285.06:30:57.68/vb/04,05,usb,yes,33,32 2006.285.06:30:57.68/vb/05,04,usb,yes,30,33 2006.285.06:30:57.68/vb/06,03,usb,yes,44,39 2006.285.06:30:57.68/vb/07,04,usb,yes,35,35 2006.285.06:30:57.68/vb/08,04,usb,yes,32,35 2006.285.06:30:57.92/vblo/01,629.99,yes,locked 2006.285.06:30:57.92/vblo/02,634.99,yes,locked 2006.285.06:30:57.92/vblo/03,649.99,yes,locked 2006.285.06:30:57.92/vblo/04,679.99,yes,locked 2006.285.06:30:57.92/vblo/05,709.99,yes,locked 2006.285.06:30:57.92/vblo/06,719.99,yes,locked 2006.285.06:30:57.92/vblo/07,734.99,yes,locked 2006.285.06:30:57.92/vblo/08,744.99,yes,locked 2006.285.06:30:58.07/vabw/8 2006.285.06:30:58.22/vbbw/8 2006.285.06:30:58.31/xfe/off,on,12.2 2006.285.06:30:58.68/ifatt/23,28,28,28 2006.285.06:30:59.07/fmout-gps/S +2.57E-07 2006.285.06:30:59.09:!2006.285.06:31:35 2006.285.06:31:35.01:data_valid=off 2006.285.06:31:35.01:"et 2006.285.06:31:35.01:!+3s 2006.285.06:31:38.02:"tape 2006.285.06:31:38.02:postob 2006.285.06:31:38.11/cable/+6.4722E-03 2006.285.06:31:38.11/wx/24.88,1014.0,67 2006.285.06:31:38.17/fmout-gps/S +2.58E-07 2006.285.06:31:38.17:scan_name=285-0632,jd0610,60 2006.285.06:31:38.17:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.285.06:31:40.13#flagr#flagr/antenna,new-source 2006.285.06:31:40.13:checkk5 2006.285.06:31:40.60/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:31:41.15/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:31:41.99/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:31:42.48/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:31:42.94/chk_obsdata//k5ts1/T2850630??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.06:31:43.38/chk_obsdata//k5ts2/T2850630??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.06:31:43.80/chk_obsdata//k5ts3/T2850630??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.06:31:44.23/chk_obsdata//k5ts4/T2850630??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.06:31:45.12/k5log//k5ts1_log_newline 2006.285.06:31:45.96/k5log//k5ts2_log_newline 2006.285.06:31:46.72/k5log//k5ts3_log_newline 2006.285.06:31:48.08/k5log//k5ts4_log_newline 2006.285.06:31:48.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:31:48.10:setupk4=1 2006.285.06:31:48.10$setupk4/echo=on 2006.285.06:31:48.10$setupk4/pcalon 2006.285.06:31:48.10$pcalon/"no phase cal control is implemented here 2006.285.06:31:48.10$setupk4/"tpicd=stop 2006.285.06:31:48.10$setupk4/"rec=synch_on 2006.285.06:31:48.10$setupk4/"rec_mode=128 2006.285.06:31:48.10$setupk4/!* 2006.285.06:31:48.10$setupk4/recpk4 2006.285.06:31:48.10$recpk4/recpatch= 2006.285.06:31:48.10$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:31:48.10$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:31:48.10$setupk4/vck44 2006.285.06:31:48.10$vck44/valo=1,524.99 2006.285.06:31:48.10#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.06:31:48.10#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.06:31:48.10#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:48.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:31:48.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:31:48.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:31:48.10#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:31:48.10#ibcon#first serial, iclass 5, count 0 2006.285.06:31:48.10#ibcon#enter sib2, iclass 5, count 0 2006.285.06:31:48.10#ibcon#flushed, iclass 5, count 0 2006.285.06:31:48.10#ibcon#about to write, iclass 5, count 0 2006.285.06:31:48.10#ibcon#wrote, iclass 5, count 0 2006.285.06:31:48.10#ibcon#about to read 3, iclass 5, count 0 2006.285.06:31:48.12#ibcon#read 3, iclass 5, count 0 2006.285.06:31:48.12#ibcon#about to read 4, iclass 5, count 0 2006.285.06:31:48.12#ibcon#read 4, iclass 5, count 0 2006.285.06:31:48.12#ibcon#about to read 5, iclass 5, count 0 2006.285.06:31:48.12#ibcon#read 5, iclass 5, count 0 2006.285.06:31:48.12#ibcon#about to read 6, iclass 5, count 0 2006.285.06:31:48.12#ibcon#read 6, iclass 5, count 0 2006.285.06:31:48.12#ibcon#end of sib2, iclass 5, count 0 2006.285.06:31:48.12#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:31:48.12#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:31:48.12#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:31:48.12#ibcon#*before write, iclass 5, count 0 2006.285.06:31:48.12#ibcon#enter sib2, iclass 5, count 0 2006.285.06:31:48.12#ibcon#flushed, iclass 5, count 0 2006.285.06:31:48.12#ibcon#about to write, iclass 5, count 0 2006.285.06:31:48.12#ibcon#wrote, iclass 5, count 0 2006.285.06:31:48.12#ibcon#about to read 3, iclass 5, count 0 2006.285.06:31:48.17#ibcon#read 3, iclass 5, count 0 2006.285.06:31:48.17#ibcon#about to read 4, iclass 5, count 0 2006.285.06:31:48.17#ibcon#read 4, iclass 5, count 0 2006.285.06:31:48.17#ibcon#about to read 5, iclass 5, count 0 2006.285.06:31:48.17#ibcon#read 5, iclass 5, count 0 2006.285.06:31:48.17#ibcon#about to read 6, iclass 5, count 0 2006.285.06:31:48.17#ibcon#read 6, iclass 5, count 0 2006.285.06:31:48.17#ibcon#end of sib2, iclass 5, count 0 2006.285.06:31:48.17#ibcon#*after write, iclass 5, count 0 2006.285.06:31:48.17#ibcon#*before return 0, iclass 5, count 0 2006.285.06:31:48.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:31:48.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:31:48.17#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:31:48.17#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:31:48.17$vck44/va=1,7 2006.285.06:31:48.17#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.06:31:48.17#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.06:31:48.17#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:48.17#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:31:48.17#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:31:48.17#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:31:48.17#ibcon#enter wrdev, iclass 7, count 2 2006.285.06:31:48.17#ibcon#first serial, iclass 7, count 2 2006.285.06:31:48.17#ibcon#enter sib2, iclass 7, count 2 2006.285.06:31:48.17#ibcon#flushed, iclass 7, count 2 2006.285.06:31:48.17#ibcon#about to write, iclass 7, count 2 2006.285.06:31:48.17#ibcon#wrote, iclass 7, count 2 2006.285.06:31:48.17#ibcon#about to read 3, iclass 7, count 2 2006.285.06:31:48.19#ibcon#read 3, iclass 7, count 2 2006.285.06:31:48.19#ibcon#about to read 4, iclass 7, count 2 2006.285.06:31:48.19#ibcon#read 4, iclass 7, count 2 2006.285.06:31:48.19#ibcon#about to read 5, iclass 7, count 2 2006.285.06:31:48.19#ibcon#read 5, iclass 7, count 2 2006.285.06:31:48.19#ibcon#about to read 6, iclass 7, count 2 2006.285.06:31:48.19#ibcon#read 6, iclass 7, count 2 2006.285.06:31:48.19#ibcon#end of sib2, iclass 7, count 2 2006.285.06:31:48.19#ibcon#*mode == 0, iclass 7, count 2 2006.285.06:31:48.19#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.06:31:48.19#ibcon#[25=AT01-07\r\n] 2006.285.06:31:48.19#ibcon#*before write, iclass 7, count 2 2006.285.06:31:48.19#ibcon#enter sib2, iclass 7, count 2 2006.285.06:31:48.19#ibcon#flushed, iclass 7, count 2 2006.285.06:31:48.19#ibcon#about to write, iclass 7, count 2 2006.285.06:31:48.19#ibcon#wrote, iclass 7, count 2 2006.285.06:31:48.19#ibcon#about to read 3, iclass 7, count 2 2006.285.06:31:48.22#ibcon#read 3, iclass 7, count 2 2006.285.06:31:48.22#ibcon#about to read 4, iclass 7, count 2 2006.285.06:31:48.22#ibcon#read 4, iclass 7, count 2 2006.285.06:31:48.22#ibcon#about to read 5, iclass 7, count 2 2006.285.06:31:48.22#ibcon#read 5, iclass 7, count 2 2006.285.06:31:48.22#ibcon#about to read 6, iclass 7, count 2 2006.285.06:31:48.22#ibcon#read 6, iclass 7, count 2 2006.285.06:31:48.22#ibcon#end of sib2, iclass 7, count 2 2006.285.06:31:48.22#ibcon#*after write, iclass 7, count 2 2006.285.06:31:48.22#ibcon#*before return 0, iclass 7, count 2 2006.285.06:31:48.22#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:31:48.22#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:31:48.22#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.06:31:48.22#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:48.22#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:31:48.34#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:31:48.34#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:31:48.34#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:31:48.34#ibcon#first serial, iclass 7, count 0 2006.285.06:31:48.34#ibcon#enter sib2, iclass 7, count 0 2006.285.06:31:48.34#ibcon#flushed, iclass 7, count 0 2006.285.06:31:48.34#ibcon#about to write, iclass 7, count 0 2006.285.06:31:48.34#ibcon#wrote, iclass 7, count 0 2006.285.06:31:48.34#ibcon#about to read 3, iclass 7, count 0 2006.285.06:31:48.36#ibcon#read 3, iclass 7, count 0 2006.285.06:31:48.36#ibcon#about to read 4, iclass 7, count 0 2006.285.06:31:48.36#ibcon#read 4, iclass 7, count 0 2006.285.06:31:48.36#ibcon#about to read 5, iclass 7, count 0 2006.285.06:31:48.36#ibcon#read 5, iclass 7, count 0 2006.285.06:31:48.36#ibcon#about to read 6, iclass 7, count 0 2006.285.06:31:48.36#ibcon#read 6, iclass 7, count 0 2006.285.06:31:48.36#ibcon#end of sib2, iclass 7, count 0 2006.285.06:31:48.36#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:31:48.36#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:31:48.36#ibcon#[25=USB\r\n] 2006.285.06:31:48.36#ibcon#*before write, iclass 7, count 0 2006.285.06:31:48.36#ibcon#enter sib2, iclass 7, count 0 2006.285.06:31:48.36#ibcon#flushed, iclass 7, count 0 2006.285.06:31:48.36#ibcon#about to write, iclass 7, count 0 2006.285.06:31:48.36#ibcon#wrote, iclass 7, count 0 2006.285.06:31:48.36#ibcon#about to read 3, iclass 7, count 0 2006.285.06:31:48.39#ibcon#read 3, iclass 7, count 0 2006.285.06:31:48.39#ibcon#about to read 4, iclass 7, count 0 2006.285.06:31:48.39#ibcon#read 4, iclass 7, count 0 2006.285.06:31:48.39#ibcon#about to read 5, iclass 7, count 0 2006.285.06:31:48.39#ibcon#read 5, iclass 7, count 0 2006.285.06:31:48.39#ibcon#about to read 6, iclass 7, count 0 2006.285.06:31:48.39#ibcon#read 6, iclass 7, count 0 2006.285.06:31:48.39#ibcon#end of sib2, iclass 7, count 0 2006.285.06:31:48.39#ibcon#*after write, iclass 7, count 0 2006.285.06:31:48.39#ibcon#*before return 0, iclass 7, count 0 2006.285.06:31:48.39#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:31:48.39#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:31:48.39#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:31:48.39#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:31:48.39$vck44/valo=2,534.99 2006.285.06:31:48.39#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.06:31:48.39#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.06:31:48.39#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:48.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:31:48.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:31:48.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:31:48.39#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:31:48.39#ibcon#first serial, iclass 11, count 0 2006.285.06:31:48.39#ibcon#enter sib2, iclass 11, count 0 2006.285.06:31:48.39#ibcon#flushed, iclass 11, count 0 2006.285.06:31:48.39#ibcon#about to write, iclass 11, count 0 2006.285.06:31:48.39#ibcon#wrote, iclass 11, count 0 2006.285.06:31:48.39#ibcon#about to read 3, iclass 11, count 0 2006.285.06:31:48.41#ibcon#read 3, iclass 11, count 0 2006.285.06:31:48.41#ibcon#about to read 4, iclass 11, count 0 2006.285.06:31:48.41#ibcon#read 4, iclass 11, count 0 2006.285.06:31:48.41#ibcon#about to read 5, iclass 11, count 0 2006.285.06:31:48.41#ibcon#read 5, iclass 11, count 0 2006.285.06:31:48.41#ibcon#about to read 6, iclass 11, count 0 2006.285.06:31:48.41#ibcon#read 6, iclass 11, count 0 2006.285.06:31:48.41#ibcon#end of sib2, iclass 11, count 0 2006.285.06:31:48.41#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:31:48.41#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:31:48.41#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:31:48.41#ibcon#*before write, iclass 11, count 0 2006.285.06:31:48.41#ibcon#enter sib2, iclass 11, count 0 2006.285.06:31:48.41#ibcon#flushed, iclass 11, count 0 2006.285.06:31:48.41#ibcon#about to write, iclass 11, count 0 2006.285.06:31:48.41#ibcon#wrote, iclass 11, count 0 2006.285.06:31:48.41#ibcon#about to read 3, iclass 11, count 0 2006.285.06:31:48.45#ibcon#read 3, iclass 11, count 0 2006.285.06:31:48.45#ibcon#about to read 4, iclass 11, count 0 2006.285.06:31:48.45#ibcon#read 4, iclass 11, count 0 2006.285.06:31:48.45#ibcon#about to read 5, iclass 11, count 0 2006.285.06:31:48.45#ibcon#read 5, iclass 11, count 0 2006.285.06:31:48.45#ibcon#about to read 6, iclass 11, count 0 2006.285.06:31:48.45#ibcon#read 6, iclass 11, count 0 2006.285.06:31:48.45#ibcon#end of sib2, iclass 11, count 0 2006.285.06:31:48.45#ibcon#*after write, iclass 11, count 0 2006.285.06:31:48.45#ibcon#*before return 0, iclass 11, count 0 2006.285.06:31:48.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:31:48.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:31:48.45#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:31:48.45#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:31:48.45$vck44/va=2,6 2006.285.06:31:48.45#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.06:31:48.45#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.06:31:48.45#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:48.45#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:31:48.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:31:48.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:31:48.51#ibcon#enter wrdev, iclass 13, count 2 2006.285.06:31:48.51#ibcon#first serial, iclass 13, count 2 2006.285.06:31:48.51#ibcon#enter sib2, iclass 13, count 2 2006.285.06:31:48.51#ibcon#flushed, iclass 13, count 2 2006.285.06:31:48.51#ibcon#about to write, iclass 13, count 2 2006.285.06:31:48.51#ibcon#wrote, iclass 13, count 2 2006.285.06:31:48.51#ibcon#about to read 3, iclass 13, count 2 2006.285.06:31:48.53#ibcon#read 3, iclass 13, count 2 2006.285.06:31:48.53#ibcon#about to read 4, iclass 13, count 2 2006.285.06:31:48.53#ibcon#read 4, iclass 13, count 2 2006.285.06:31:48.53#ibcon#about to read 5, iclass 13, count 2 2006.285.06:31:48.53#ibcon#read 5, iclass 13, count 2 2006.285.06:31:48.53#ibcon#about to read 6, iclass 13, count 2 2006.285.06:31:48.53#ibcon#read 6, iclass 13, count 2 2006.285.06:31:48.53#ibcon#end of sib2, iclass 13, count 2 2006.285.06:31:48.53#ibcon#*mode == 0, iclass 13, count 2 2006.285.06:31:48.53#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.06:31:48.53#ibcon#[25=AT02-06\r\n] 2006.285.06:31:48.53#ibcon#*before write, iclass 13, count 2 2006.285.06:31:48.53#ibcon#enter sib2, iclass 13, count 2 2006.285.06:31:48.53#ibcon#flushed, iclass 13, count 2 2006.285.06:31:48.53#ibcon#about to write, iclass 13, count 2 2006.285.06:31:48.53#ibcon#wrote, iclass 13, count 2 2006.285.06:31:48.53#ibcon#about to read 3, iclass 13, count 2 2006.285.06:31:48.56#ibcon#read 3, iclass 13, count 2 2006.285.06:31:48.56#ibcon#about to read 4, iclass 13, count 2 2006.285.06:31:48.56#ibcon#read 4, iclass 13, count 2 2006.285.06:31:48.56#ibcon#about to read 5, iclass 13, count 2 2006.285.06:31:48.56#ibcon#read 5, iclass 13, count 2 2006.285.06:31:48.56#ibcon#about to read 6, iclass 13, count 2 2006.285.06:31:48.56#ibcon#read 6, iclass 13, count 2 2006.285.06:31:48.56#ibcon#end of sib2, iclass 13, count 2 2006.285.06:31:48.56#ibcon#*after write, iclass 13, count 2 2006.285.06:31:48.56#ibcon#*before return 0, iclass 13, count 2 2006.285.06:31:48.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:31:48.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:31:48.56#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.06:31:48.56#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:48.56#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:31:48.68#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:31:48.68#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:31:48.68#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:31:48.68#ibcon#first serial, iclass 13, count 0 2006.285.06:31:48.68#ibcon#enter sib2, iclass 13, count 0 2006.285.06:31:48.68#ibcon#flushed, iclass 13, count 0 2006.285.06:31:48.68#ibcon#about to write, iclass 13, count 0 2006.285.06:31:48.68#ibcon#wrote, iclass 13, count 0 2006.285.06:31:48.68#ibcon#about to read 3, iclass 13, count 0 2006.285.06:31:48.70#ibcon#read 3, iclass 13, count 0 2006.285.06:31:48.70#ibcon#about to read 4, iclass 13, count 0 2006.285.06:31:48.70#ibcon#read 4, iclass 13, count 0 2006.285.06:31:48.70#ibcon#about to read 5, iclass 13, count 0 2006.285.06:31:48.70#ibcon#read 5, iclass 13, count 0 2006.285.06:31:48.70#ibcon#about to read 6, iclass 13, count 0 2006.285.06:31:48.70#ibcon#read 6, iclass 13, count 0 2006.285.06:31:48.70#ibcon#end of sib2, iclass 13, count 0 2006.285.06:31:48.70#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:31:48.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:31:48.70#ibcon#[25=USB\r\n] 2006.285.06:31:48.70#ibcon#*before write, iclass 13, count 0 2006.285.06:31:48.70#ibcon#enter sib2, iclass 13, count 0 2006.285.06:31:48.70#ibcon#flushed, iclass 13, count 0 2006.285.06:31:48.70#ibcon#about to write, iclass 13, count 0 2006.285.06:31:48.70#ibcon#wrote, iclass 13, count 0 2006.285.06:31:48.70#ibcon#about to read 3, iclass 13, count 0 2006.285.06:31:48.73#ibcon#read 3, iclass 13, count 0 2006.285.06:31:48.73#ibcon#about to read 4, iclass 13, count 0 2006.285.06:31:48.73#ibcon#read 4, iclass 13, count 0 2006.285.06:31:48.73#ibcon#about to read 5, iclass 13, count 0 2006.285.06:31:48.73#ibcon#read 5, iclass 13, count 0 2006.285.06:31:48.73#ibcon#about to read 6, iclass 13, count 0 2006.285.06:31:48.73#ibcon#read 6, iclass 13, count 0 2006.285.06:31:48.73#ibcon#end of sib2, iclass 13, count 0 2006.285.06:31:48.73#ibcon#*after write, iclass 13, count 0 2006.285.06:31:48.73#ibcon#*before return 0, iclass 13, count 0 2006.285.06:31:48.73#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:31:48.73#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:31:48.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:31:48.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:31:48.73$vck44/valo=3,564.99 2006.285.06:31:48.73#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.06:31:48.73#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.06:31:48.73#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:48.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:31:48.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:31:48.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:31:48.73#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:31:48.73#ibcon#first serial, iclass 15, count 0 2006.285.06:31:48.73#ibcon#enter sib2, iclass 15, count 0 2006.285.06:31:48.73#ibcon#flushed, iclass 15, count 0 2006.285.06:31:48.73#ibcon#about to write, iclass 15, count 0 2006.285.06:31:48.73#ibcon#wrote, iclass 15, count 0 2006.285.06:31:48.73#ibcon#about to read 3, iclass 15, count 0 2006.285.06:31:48.75#ibcon#read 3, iclass 15, count 0 2006.285.06:31:48.75#ibcon#about to read 4, iclass 15, count 0 2006.285.06:31:48.75#ibcon#read 4, iclass 15, count 0 2006.285.06:31:48.75#ibcon#about to read 5, iclass 15, count 0 2006.285.06:31:48.75#ibcon#read 5, iclass 15, count 0 2006.285.06:31:48.75#ibcon#about to read 6, iclass 15, count 0 2006.285.06:31:48.75#ibcon#read 6, iclass 15, count 0 2006.285.06:31:48.75#ibcon#end of sib2, iclass 15, count 0 2006.285.06:31:48.75#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:31:48.75#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:31:48.75#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:31:48.75#ibcon#*before write, iclass 15, count 0 2006.285.06:31:48.75#ibcon#enter sib2, iclass 15, count 0 2006.285.06:31:48.75#ibcon#flushed, iclass 15, count 0 2006.285.06:31:48.75#ibcon#about to write, iclass 15, count 0 2006.285.06:31:48.75#ibcon#wrote, iclass 15, count 0 2006.285.06:31:48.75#ibcon#about to read 3, iclass 15, count 0 2006.285.06:31:48.79#ibcon#read 3, iclass 15, count 0 2006.285.06:31:48.79#ibcon#about to read 4, iclass 15, count 0 2006.285.06:31:48.79#ibcon#read 4, iclass 15, count 0 2006.285.06:31:48.79#ibcon#about to read 5, iclass 15, count 0 2006.285.06:31:48.79#ibcon#read 5, iclass 15, count 0 2006.285.06:31:48.79#ibcon#about to read 6, iclass 15, count 0 2006.285.06:31:48.79#ibcon#read 6, iclass 15, count 0 2006.285.06:31:48.79#ibcon#end of sib2, iclass 15, count 0 2006.285.06:31:48.79#ibcon#*after write, iclass 15, count 0 2006.285.06:31:48.79#ibcon#*before return 0, iclass 15, count 0 2006.285.06:31:48.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:31:48.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:31:48.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:31:48.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:31:48.79$vck44/va=3,7 2006.285.06:31:48.79#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.06:31:48.79#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.06:31:48.79#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:48.79#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:31:48.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:31:48.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:31:48.85#ibcon#enter wrdev, iclass 17, count 2 2006.285.06:31:48.85#ibcon#first serial, iclass 17, count 2 2006.285.06:31:48.85#ibcon#enter sib2, iclass 17, count 2 2006.285.06:31:48.85#ibcon#flushed, iclass 17, count 2 2006.285.06:31:48.85#ibcon#about to write, iclass 17, count 2 2006.285.06:31:48.85#ibcon#wrote, iclass 17, count 2 2006.285.06:31:48.85#ibcon#about to read 3, iclass 17, count 2 2006.285.06:31:48.87#ibcon#read 3, iclass 17, count 2 2006.285.06:31:48.87#ibcon#about to read 4, iclass 17, count 2 2006.285.06:31:48.87#ibcon#read 4, iclass 17, count 2 2006.285.06:31:48.87#ibcon#about to read 5, iclass 17, count 2 2006.285.06:31:48.87#ibcon#read 5, iclass 17, count 2 2006.285.06:31:48.87#ibcon#about to read 6, iclass 17, count 2 2006.285.06:31:48.87#ibcon#read 6, iclass 17, count 2 2006.285.06:31:48.87#ibcon#end of sib2, iclass 17, count 2 2006.285.06:31:48.87#ibcon#*mode == 0, iclass 17, count 2 2006.285.06:31:48.87#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.06:31:48.87#ibcon#[25=AT03-07\r\n] 2006.285.06:31:48.87#ibcon#*before write, iclass 17, count 2 2006.285.06:31:48.87#ibcon#enter sib2, iclass 17, count 2 2006.285.06:31:48.87#ibcon#flushed, iclass 17, count 2 2006.285.06:31:48.87#ibcon#about to write, iclass 17, count 2 2006.285.06:31:48.87#ibcon#wrote, iclass 17, count 2 2006.285.06:31:48.87#ibcon#about to read 3, iclass 17, count 2 2006.285.06:31:48.90#ibcon#read 3, iclass 17, count 2 2006.285.06:31:48.90#ibcon#about to read 4, iclass 17, count 2 2006.285.06:31:48.90#ibcon#read 4, iclass 17, count 2 2006.285.06:31:48.90#ibcon#about to read 5, iclass 17, count 2 2006.285.06:31:48.90#ibcon#read 5, iclass 17, count 2 2006.285.06:31:48.90#ibcon#about to read 6, iclass 17, count 2 2006.285.06:31:48.90#ibcon#read 6, iclass 17, count 2 2006.285.06:31:48.90#ibcon#end of sib2, iclass 17, count 2 2006.285.06:31:48.90#ibcon#*after write, iclass 17, count 2 2006.285.06:31:48.90#ibcon#*before return 0, iclass 17, count 2 2006.285.06:31:48.90#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:31:48.90#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:31:48.90#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.06:31:48.90#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:48.90#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:31:49.02#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:31:49.02#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:31:49.02#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:31:49.02#ibcon#first serial, iclass 17, count 0 2006.285.06:31:49.02#ibcon#enter sib2, iclass 17, count 0 2006.285.06:31:49.02#ibcon#flushed, iclass 17, count 0 2006.285.06:31:49.02#ibcon#about to write, iclass 17, count 0 2006.285.06:31:49.02#ibcon#wrote, iclass 17, count 0 2006.285.06:31:49.02#ibcon#about to read 3, iclass 17, count 0 2006.285.06:31:49.04#ibcon#read 3, iclass 17, count 0 2006.285.06:31:49.04#ibcon#about to read 4, iclass 17, count 0 2006.285.06:31:49.04#ibcon#read 4, iclass 17, count 0 2006.285.06:31:49.04#ibcon#about to read 5, iclass 17, count 0 2006.285.06:31:49.04#ibcon#read 5, iclass 17, count 0 2006.285.06:31:49.04#ibcon#about to read 6, iclass 17, count 0 2006.285.06:31:49.04#ibcon#read 6, iclass 17, count 0 2006.285.06:31:49.04#ibcon#end of sib2, iclass 17, count 0 2006.285.06:31:49.04#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:31:49.04#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:31:49.04#ibcon#[25=USB\r\n] 2006.285.06:31:49.04#ibcon#*before write, iclass 17, count 0 2006.285.06:31:49.04#ibcon#enter sib2, iclass 17, count 0 2006.285.06:31:49.04#ibcon#flushed, iclass 17, count 0 2006.285.06:31:49.04#ibcon#about to write, iclass 17, count 0 2006.285.06:31:49.04#ibcon#wrote, iclass 17, count 0 2006.285.06:31:49.04#ibcon#about to read 3, iclass 17, count 0 2006.285.06:31:49.07#ibcon#read 3, iclass 17, count 0 2006.285.06:31:49.07#ibcon#about to read 4, iclass 17, count 0 2006.285.06:31:49.07#ibcon#read 4, iclass 17, count 0 2006.285.06:31:49.07#ibcon#about to read 5, iclass 17, count 0 2006.285.06:31:49.07#ibcon#read 5, iclass 17, count 0 2006.285.06:31:49.07#ibcon#about to read 6, iclass 17, count 0 2006.285.06:31:49.07#ibcon#read 6, iclass 17, count 0 2006.285.06:31:49.07#ibcon#end of sib2, iclass 17, count 0 2006.285.06:31:49.07#ibcon#*after write, iclass 17, count 0 2006.285.06:31:49.07#ibcon#*before return 0, iclass 17, count 0 2006.285.06:31:49.07#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:31:49.07#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:31:49.07#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:31:49.07#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:31:49.07$vck44/valo=4,624.99 2006.285.06:31:49.07#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.06:31:49.07#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.06:31:49.07#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:49.07#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:31:49.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:31:49.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:31:49.07#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:31:49.07#ibcon#first serial, iclass 19, count 0 2006.285.06:31:49.07#ibcon#enter sib2, iclass 19, count 0 2006.285.06:31:49.07#ibcon#flushed, iclass 19, count 0 2006.285.06:31:49.07#ibcon#about to write, iclass 19, count 0 2006.285.06:31:49.07#ibcon#wrote, iclass 19, count 0 2006.285.06:31:49.07#ibcon#about to read 3, iclass 19, count 0 2006.285.06:31:49.09#ibcon#read 3, iclass 19, count 0 2006.285.06:31:49.09#ibcon#about to read 4, iclass 19, count 0 2006.285.06:31:49.09#ibcon#read 4, iclass 19, count 0 2006.285.06:31:49.09#ibcon#about to read 5, iclass 19, count 0 2006.285.06:31:49.09#ibcon#read 5, iclass 19, count 0 2006.285.06:31:49.09#ibcon#about to read 6, iclass 19, count 0 2006.285.06:31:49.09#ibcon#read 6, iclass 19, count 0 2006.285.06:31:49.09#ibcon#end of sib2, iclass 19, count 0 2006.285.06:31:49.09#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:31:49.09#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:31:49.09#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:31:49.09#ibcon#*before write, iclass 19, count 0 2006.285.06:31:49.09#ibcon#enter sib2, iclass 19, count 0 2006.285.06:31:49.09#ibcon#flushed, iclass 19, count 0 2006.285.06:31:49.09#ibcon#about to write, iclass 19, count 0 2006.285.06:31:49.09#ibcon#wrote, iclass 19, count 0 2006.285.06:31:49.09#ibcon#about to read 3, iclass 19, count 0 2006.285.06:31:49.13#ibcon#read 3, iclass 19, count 0 2006.285.06:31:49.13#ibcon#about to read 4, iclass 19, count 0 2006.285.06:31:49.13#ibcon#read 4, iclass 19, count 0 2006.285.06:31:49.13#ibcon#about to read 5, iclass 19, count 0 2006.285.06:31:49.13#ibcon#read 5, iclass 19, count 0 2006.285.06:31:49.13#ibcon#about to read 6, iclass 19, count 0 2006.285.06:31:49.13#ibcon#read 6, iclass 19, count 0 2006.285.06:31:49.13#ibcon#end of sib2, iclass 19, count 0 2006.285.06:31:49.13#ibcon#*after write, iclass 19, count 0 2006.285.06:31:49.13#ibcon#*before return 0, iclass 19, count 0 2006.285.06:31:49.13#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:31:49.13#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:31:49.13#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:31:49.13#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:31:49.13$vck44/va=4,6 2006.285.06:31:49.13#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.06:31:49.13#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.06:31:49.13#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:49.13#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:31:49.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:31:49.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:31:49.19#ibcon#enter wrdev, iclass 21, count 2 2006.285.06:31:49.19#ibcon#first serial, iclass 21, count 2 2006.285.06:31:49.19#ibcon#enter sib2, iclass 21, count 2 2006.285.06:31:49.19#ibcon#flushed, iclass 21, count 2 2006.285.06:31:49.19#ibcon#about to write, iclass 21, count 2 2006.285.06:31:49.19#ibcon#wrote, iclass 21, count 2 2006.285.06:31:49.19#ibcon#about to read 3, iclass 21, count 2 2006.285.06:31:49.21#ibcon#read 3, iclass 21, count 2 2006.285.06:31:49.21#ibcon#about to read 4, iclass 21, count 2 2006.285.06:31:49.21#ibcon#read 4, iclass 21, count 2 2006.285.06:31:49.21#ibcon#about to read 5, iclass 21, count 2 2006.285.06:31:49.21#ibcon#read 5, iclass 21, count 2 2006.285.06:31:49.21#ibcon#about to read 6, iclass 21, count 2 2006.285.06:31:49.21#ibcon#read 6, iclass 21, count 2 2006.285.06:31:49.21#ibcon#end of sib2, iclass 21, count 2 2006.285.06:31:49.21#ibcon#*mode == 0, iclass 21, count 2 2006.285.06:31:49.21#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.06:31:49.21#ibcon#[25=AT04-06\r\n] 2006.285.06:31:49.21#ibcon#*before write, iclass 21, count 2 2006.285.06:31:49.21#ibcon#enter sib2, iclass 21, count 2 2006.285.06:31:49.21#ibcon#flushed, iclass 21, count 2 2006.285.06:31:49.21#ibcon#about to write, iclass 21, count 2 2006.285.06:31:49.21#ibcon#wrote, iclass 21, count 2 2006.285.06:31:49.21#ibcon#about to read 3, iclass 21, count 2 2006.285.06:31:49.24#ibcon#read 3, iclass 21, count 2 2006.285.06:31:49.24#ibcon#about to read 4, iclass 21, count 2 2006.285.06:31:49.24#ibcon#read 4, iclass 21, count 2 2006.285.06:31:49.24#ibcon#about to read 5, iclass 21, count 2 2006.285.06:31:49.24#ibcon#read 5, iclass 21, count 2 2006.285.06:31:49.24#ibcon#about to read 6, iclass 21, count 2 2006.285.06:31:49.24#ibcon#read 6, iclass 21, count 2 2006.285.06:31:49.24#ibcon#end of sib2, iclass 21, count 2 2006.285.06:31:49.24#ibcon#*after write, iclass 21, count 2 2006.285.06:31:49.24#ibcon#*before return 0, iclass 21, count 2 2006.285.06:31:49.24#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:31:49.24#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:31:49.24#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.06:31:49.24#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:49.24#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:31:49.36#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:31:49.36#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:31:49.36#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:31:49.36#ibcon#first serial, iclass 21, count 0 2006.285.06:31:49.36#ibcon#enter sib2, iclass 21, count 0 2006.285.06:31:49.36#ibcon#flushed, iclass 21, count 0 2006.285.06:31:49.36#ibcon#about to write, iclass 21, count 0 2006.285.06:31:49.36#ibcon#wrote, iclass 21, count 0 2006.285.06:31:49.36#ibcon#about to read 3, iclass 21, count 0 2006.285.06:31:49.38#ibcon#read 3, iclass 21, count 0 2006.285.06:31:49.38#ibcon#about to read 4, iclass 21, count 0 2006.285.06:31:49.38#ibcon#read 4, iclass 21, count 0 2006.285.06:31:49.38#ibcon#about to read 5, iclass 21, count 0 2006.285.06:31:49.38#ibcon#read 5, iclass 21, count 0 2006.285.06:31:49.38#ibcon#about to read 6, iclass 21, count 0 2006.285.06:31:49.38#ibcon#read 6, iclass 21, count 0 2006.285.06:31:49.38#ibcon#end of sib2, iclass 21, count 0 2006.285.06:31:49.38#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:31:49.38#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:31:49.38#ibcon#[25=USB\r\n] 2006.285.06:31:49.38#ibcon#*before write, iclass 21, count 0 2006.285.06:31:49.38#ibcon#enter sib2, iclass 21, count 0 2006.285.06:31:49.38#ibcon#flushed, iclass 21, count 0 2006.285.06:31:49.38#ibcon#about to write, iclass 21, count 0 2006.285.06:31:49.38#ibcon#wrote, iclass 21, count 0 2006.285.06:31:49.38#ibcon#about to read 3, iclass 21, count 0 2006.285.06:31:49.41#ibcon#read 3, iclass 21, count 0 2006.285.06:31:49.41#ibcon#about to read 4, iclass 21, count 0 2006.285.06:31:49.41#ibcon#read 4, iclass 21, count 0 2006.285.06:31:49.41#ibcon#about to read 5, iclass 21, count 0 2006.285.06:31:49.41#ibcon#read 5, iclass 21, count 0 2006.285.06:31:49.41#ibcon#about to read 6, iclass 21, count 0 2006.285.06:31:49.41#ibcon#read 6, iclass 21, count 0 2006.285.06:31:49.41#ibcon#end of sib2, iclass 21, count 0 2006.285.06:31:49.41#ibcon#*after write, iclass 21, count 0 2006.285.06:31:49.41#ibcon#*before return 0, iclass 21, count 0 2006.285.06:31:49.41#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:31:49.41#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:31:49.41#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:31:49.41#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:31:49.41$vck44/valo=5,734.99 2006.285.06:31:49.41#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.06:31:49.41#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.06:31:49.41#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:49.41#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:31:49.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:31:49.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:31:49.41#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:31:49.41#ibcon#first serial, iclass 23, count 0 2006.285.06:31:49.41#ibcon#enter sib2, iclass 23, count 0 2006.285.06:31:49.41#ibcon#flushed, iclass 23, count 0 2006.285.06:31:49.41#ibcon#about to write, iclass 23, count 0 2006.285.06:31:49.41#ibcon#wrote, iclass 23, count 0 2006.285.06:31:49.41#ibcon#about to read 3, iclass 23, count 0 2006.285.06:31:49.43#ibcon#read 3, iclass 23, count 0 2006.285.06:31:49.43#ibcon#about to read 4, iclass 23, count 0 2006.285.06:31:49.43#ibcon#read 4, iclass 23, count 0 2006.285.06:31:49.43#ibcon#about to read 5, iclass 23, count 0 2006.285.06:31:49.43#ibcon#read 5, iclass 23, count 0 2006.285.06:31:49.43#ibcon#about to read 6, iclass 23, count 0 2006.285.06:31:49.43#ibcon#read 6, iclass 23, count 0 2006.285.06:31:49.43#ibcon#end of sib2, iclass 23, count 0 2006.285.06:31:49.43#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:31:49.43#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:31:49.43#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:31:49.43#ibcon#*before write, iclass 23, count 0 2006.285.06:31:49.43#ibcon#enter sib2, iclass 23, count 0 2006.285.06:31:49.43#ibcon#flushed, iclass 23, count 0 2006.285.06:31:49.43#ibcon#about to write, iclass 23, count 0 2006.285.06:31:49.43#ibcon#wrote, iclass 23, count 0 2006.285.06:31:49.43#ibcon#about to read 3, iclass 23, count 0 2006.285.06:31:49.47#ibcon#read 3, iclass 23, count 0 2006.285.06:31:49.47#ibcon#about to read 4, iclass 23, count 0 2006.285.06:31:49.47#ibcon#read 4, iclass 23, count 0 2006.285.06:31:49.47#ibcon#about to read 5, iclass 23, count 0 2006.285.06:31:49.47#ibcon#read 5, iclass 23, count 0 2006.285.06:31:49.47#ibcon#about to read 6, iclass 23, count 0 2006.285.06:31:49.47#ibcon#read 6, iclass 23, count 0 2006.285.06:31:49.47#ibcon#end of sib2, iclass 23, count 0 2006.285.06:31:49.47#ibcon#*after write, iclass 23, count 0 2006.285.06:31:49.47#ibcon#*before return 0, iclass 23, count 0 2006.285.06:31:49.47#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:31:49.47#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:31:49.47#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:31:49.47#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:31:49.47$vck44/va=5,3 2006.285.06:31:49.47#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.06:31:49.47#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.06:31:49.47#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:49.47#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:31:49.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:31:49.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:31:49.53#ibcon#enter wrdev, iclass 25, count 2 2006.285.06:31:49.53#ibcon#first serial, iclass 25, count 2 2006.285.06:31:49.53#ibcon#enter sib2, iclass 25, count 2 2006.285.06:31:49.53#ibcon#flushed, iclass 25, count 2 2006.285.06:31:49.53#ibcon#about to write, iclass 25, count 2 2006.285.06:31:49.53#ibcon#wrote, iclass 25, count 2 2006.285.06:31:49.53#ibcon#about to read 3, iclass 25, count 2 2006.285.06:31:49.55#ibcon#read 3, iclass 25, count 2 2006.285.06:31:49.55#ibcon#about to read 4, iclass 25, count 2 2006.285.06:31:49.55#ibcon#read 4, iclass 25, count 2 2006.285.06:31:49.55#ibcon#about to read 5, iclass 25, count 2 2006.285.06:31:49.55#ibcon#read 5, iclass 25, count 2 2006.285.06:31:49.55#ibcon#about to read 6, iclass 25, count 2 2006.285.06:31:49.55#ibcon#read 6, iclass 25, count 2 2006.285.06:31:49.55#ibcon#end of sib2, iclass 25, count 2 2006.285.06:31:49.55#ibcon#*mode == 0, iclass 25, count 2 2006.285.06:31:49.55#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.06:31:49.55#ibcon#[25=AT05-03\r\n] 2006.285.06:31:49.55#ibcon#*before write, iclass 25, count 2 2006.285.06:31:49.55#ibcon#enter sib2, iclass 25, count 2 2006.285.06:31:49.55#ibcon#flushed, iclass 25, count 2 2006.285.06:31:49.55#ibcon#about to write, iclass 25, count 2 2006.285.06:31:49.55#ibcon#wrote, iclass 25, count 2 2006.285.06:31:49.55#ibcon#about to read 3, iclass 25, count 2 2006.285.06:31:49.58#ibcon#read 3, iclass 25, count 2 2006.285.06:31:49.58#ibcon#about to read 4, iclass 25, count 2 2006.285.06:31:49.58#ibcon#read 4, iclass 25, count 2 2006.285.06:31:49.58#ibcon#about to read 5, iclass 25, count 2 2006.285.06:31:49.58#ibcon#read 5, iclass 25, count 2 2006.285.06:31:49.58#ibcon#about to read 6, iclass 25, count 2 2006.285.06:31:49.58#ibcon#read 6, iclass 25, count 2 2006.285.06:31:49.58#ibcon#end of sib2, iclass 25, count 2 2006.285.06:31:49.58#ibcon#*after write, iclass 25, count 2 2006.285.06:31:49.58#ibcon#*before return 0, iclass 25, count 2 2006.285.06:31:49.58#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:31:49.58#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:31:49.58#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.06:31:49.58#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:49.58#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:31:49.70#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:31:49.70#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:31:49.70#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:31:49.70#ibcon#first serial, iclass 25, count 0 2006.285.06:31:49.70#ibcon#enter sib2, iclass 25, count 0 2006.285.06:31:49.70#ibcon#flushed, iclass 25, count 0 2006.285.06:31:49.70#ibcon#about to write, iclass 25, count 0 2006.285.06:31:49.70#ibcon#wrote, iclass 25, count 0 2006.285.06:31:49.70#ibcon#about to read 3, iclass 25, count 0 2006.285.06:31:49.72#ibcon#read 3, iclass 25, count 0 2006.285.06:31:49.72#ibcon#about to read 4, iclass 25, count 0 2006.285.06:31:49.72#ibcon#read 4, iclass 25, count 0 2006.285.06:31:49.72#ibcon#about to read 5, iclass 25, count 0 2006.285.06:31:49.72#ibcon#read 5, iclass 25, count 0 2006.285.06:31:49.72#ibcon#about to read 6, iclass 25, count 0 2006.285.06:31:49.72#ibcon#read 6, iclass 25, count 0 2006.285.06:31:49.72#ibcon#end of sib2, iclass 25, count 0 2006.285.06:31:49.72#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:31:49.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:31:49.72#ibcon#[25=USB\r\n] 2006.285.06:31:49.72#ibcon#*before write, iclass 25, count 0 2006.285.06:31:49.72#ibcon#enter sib2, iclass 25, count 0 2006.285.06:31:49.72#ibcon#flushed, iclass 25, count 0 2006.285.06:31:49.72#ibcon#about to write, iclass 25, count 0 2006.285.06:31:49.72#ibcon#wrote, iclass 25, count 0 2006.285.06:31:49.72#ibcon#about to read 3, iclass 25, count 0 2006.285.06:31:49.75#ibcon#read 3, iclass 25, count 0 2006.285.06:31:49.75#ibcon#about to read 4, iclass 25, count 0 2006.285.06:31:49.75#ibcon#read 4, iclass 25, count 0 2006.285.06:31:49.75#ibcon#about to read 5, iclass 25, count 0 2006.285.06:31:49.75#ibcon#read 5, iclass 25, count 0 2006.285.06:31:49.75#ibcon#about to read 6, iclass 25, count 0 2006.285.06:31:49.75#ibcon#read 6, iclass 25, count 0 2006.285.06:31:49.75#ibcon#end of sib2, iclass 25, count 0 2006.285.06:31:49.75#ibcon#*after write, iclass 25, count 0 2006.285.06:31:49.75#ibcon#*before return 0, iclass 25, count 0 2006.285.06:31:49.75#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:31:49.75#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:31:49.75#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:31:49.75#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:31:49.75$vck44/valo=6,814.99 2006.285.06:31:49.75#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.06:31:49.75#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.06:31:49.75#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:49.75#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:31:49.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:31:49.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:31:49.75#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:31:49.75#ibcon#first serial, iclass 27, count 0 2006.285.06:31:49.75#ibcon#enter sib2, iclass 27, count 0 2006.285.06:31:49.75#ibcon#flushed, iclass 27, count 0 2006.285.06:31:49.75#ibcon#about to write, iclass 27, count 0 2006.285.06:31:49.75#ibcon#wrote, iclass 27, count 0 2006.285.06:31:49.75#ibcon#about to read 3, iclass 27, count 0 2006.285.06:31:49.77#ibcon#read 3, iclass 27, count 0 2006.285.06:31:49.77#ibcon#about to read 4, iclass 27, count 0 2006.285.06:31:49.77#ibcon#read 4, iclass 27, count 0 2006.285.06:31:49.77#ibcon#about to read 5, iclass 27, count 0 2006.285.06:31:49.77#ibcon#read 5, iclass 27, count 0 2006.285.06:31:49.77#ibcon#about to read 6, iclass 27, count 0 2006.285.06:31:49.77#ibcon#read 6, iclass 27, count 0 2006.285.06:31:49.77#ibcon#end of sib2, iclass 27, count 0 2006.285.06:31:49.77#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:31:49.77#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:31:49.77#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:31:49.77#ibcon#*before write, iclass 27, count 0 2006.285.06:31:49.77#ibcon#enter sib2, iclass 27, count 0 2006.285.06:31:49.77#ibcon#flushed, iclass 27, count 0 2006.285.06:31:49.77#ibcon#about to write, iclass 27, count 0 2006.285.06:31:49.77#ibcon#wrote, iclass 27, count 0 2006.285.06:31:49.77#ibcon#about to read 3, iclass 27, count 0 2006.285.06:31:49.81#ibcon#read 3, iclass 27, count 0 2006.285.06:31:49.81#ibcon#about to read 4, iclass 27, count 0 2006.285.06:31:49.81#ibcon#read 4, iclass 27, count 0 2006.285.06:31:49.81#ibcon#about to read 5, iclass 27, count 0 2006.285.06:31:49.81#ibcon#read 5, iclass 27, count 0 2006.285.06:31:49.81#ibcon#about to read 6, iclass 27, count 0 2006.285.06:31:49.81#ibcon#read 6, iclass 27, count 0 2006.285.06:31:49.81#ibcon#end of sib2, iclass 27, count 0 2006.285.06:31:49.81#ibcon#*after write, iclass 27, count 0 2006.285.06:31:49.81#ibcon#*before return 0, iclass 27, count 0 2006.285.06:31:49.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:31:49.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:31:49.81#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:31:49.81#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:31:49.81$vck44/va=6,4 2006.285.06:31:49.81#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.06:31:49.81#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.06:31:49.81#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:49.81#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:31:49.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:31:49.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:31:49.87#ibcon#enter wrdev, iclass 29, count 2 2006.285.06:31:49.87#ibcon#first serial, iclass 29, count 2 2006.285.06:31:49.87#ibcon#enter sib2, iclass 29, count 2 2006.285.06:31:49.87#ibcon#flushed, iclass 29, count 2 2006.285.06:31:49.87#ibcon#about to write, iclass 29, count 2 2006.285.06:31:49.87#ibcon#wrote, iclass 29, count 2 2006.285.06:31:49.87#ibcon#about to read 3, iclass 29, count 2 2006.285.06:31:49.89#ibcon#read 3, iclass 29, count 2 2006.285.06:31:49.89#ibcon#about to read 4, iclass 29, count 2 2006.285.06:31:49.89#ibcon#read 4, iclass 29, count 2 2006.285.06:31:49.89#ibcon#about to read 5, iclass 29, count 2 2006.285.06:31:49.89#ibcon#read 5, iclass 29, count 2 2006.285.06:31:49.89#ibcon#about to read 6, iclass 29, count 2 2006.285.06:31:49.89#ibcon#read 6, iclass 29, count 2 2006.285.06:31:49.89#ibcon#end of sib2, iclass 29, count 2 2006.285.06:31:49.89#ibcon#*mode == 0, iclass 29, count 2 2006.285.06:31:49.89#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.06:31:49.89#ibcon#[25=AT06-04\r\n] 2006.285.06:31:49.89#ibcon#*before write, iclass 29, count 2 2006.285.06:31:49.89#ibcon#enter sib2, iclass 29, count 2 2006.285.06:31:49.89#ibcon#flushed, iclass 29, count 2 2006.285.06:31:49.89#ibcon#about to write, iclass 29, count 2 2006.285.06:31:49.89#ibcon#wrote, iclass 29, count 2 2006.285.06:31:49.89#ibcon#about to read 3, iclass 29, count 2 2006.285.06:31:49.92#ibcon#read 3, iclass 29, count 2 2006.285.06:31:49.92#ibcon#about to read 4, iclass 29, count 2 2006.285.06:31:49.92#ibcon#read 4, iclass 29, count 2 2006.285.06:31:49.92#ibcon#about to read 5, iclass 29, count 2 2006.285.06:31:49.92#ibcon#read 5, iclass 29, count 2 2006.285.06:31:49.92#ibcon#about to read 6, iclass 29, count 2 2006.285.06:31:49.92#ibcon#read 6, iclass 29, count 2 2006.285.06:31:49.92#ibcon#end of sib2, iclass 29, count 2 2006.285.06:31:49.92#ibcon#*after write, iclass 29, count 2 2006.285.06:31:49.92#ibcon#*before return 0, iclass 29, count 2 2006.285.06:31:49.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:31:49.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:31:49.92#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.06:31:49.92#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:49.92#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:31:50.04#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:31:50.04#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:31:50.04#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:31:50.04#ibcon#first serial, iclass 29, count 0 2006.285.06:31:50.04#ibcon#enter sib2, iclass 29, count 0 2006.285.06:31:50.04#ibcon#flushed, iclass 29, count 0 2006.285.06:31:50.04#ibcon#about to write, iclass 29, count 0 2006.285.06:31:50.04#ibcon#wrote, iclass 29, count 0 2006.285.06:31:50.04#ibcon#about to read 3, iclass 29, count 0 2006.285.06:31:50.06#ibcon#read 3, iclass 29, count 0 2006.285.06:31:50.06#ibcon#about to read 4, iclass 29, count 0 2006.285.06:31:50.06#ibcon#read 4, iclass 29, count 0 2006.285.06:31:50.06#ibcon#about to read 5, iclass 29, count 0 2006.285.06:31:50.06#ibcon#read 5, iclass 29, count 0 2006.285.06:31:50.06#ibcon#about to read 6, iclass 29, count 0 2006.285.06:31:50.06#ibcon#read 6, iclass 29, count 0 2006.285.06:31:50.06#ibcon#end of sib2, iclass 29, count 0 2006.285.06:31:50.06#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:31:50.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:31:50.06#ibcon#[25=USB\r\n] 2006.285.06:31:50.06#ibcon#*before write, iclass 29, count 0 2006.285.06:31:50.06#ibcon#enter sib2, iclass 29, count 0 2006.285.06:31:50.06#ibcon#flushed, iclass 29, count 0 2006.285.06:31:50.06#ibcon#about to write, iclass 29, count 0 2006.285.06:31:50.06#ibcon#wrote, iclass 29, count 0 2006.285.06:31:50.06#ibcon#about to read 3, iclass 29, count 0 2006.285.06:31:50.09#ibcon#read 3, iclass 29, count 0 2006.285.06:31:50.09#ibcon#about to read 4, iclass 29, count 0 2006.285.06:31:50.09#ibcon#read 4, iclass 29, count 0 2006.285.06:31:50.09#ibcon#about to read 5, iclass 29, count 0 2006.285.06:31:50.09#ibcon#read 5, iclass 29, count 0 2006.285.06:31:50.09#ibcon#about to read 6, iclass 29, count 0 2006.285.06:31:50.09#ibcon#read 6, iclass 29, count 0 2006.285.06:31:50.09#ibcon#end of sib2, iclass 29, count 0 2006.285.06:31:50.09#ibcon#*after write, iclass 29, count 0 2006.285.06:31:50.09#ibcon#*before return 0, iclass 29, count 0 2006.285.06:31:50.09#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:31:50.09#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:31:50.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:31:50.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:31:50.09$vck44/valo=7,864.99 2006.285.06:31:50.09#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.06:31:50.09#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.06:31:50.09#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:50.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:31:50.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:31:50.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:31:50.09#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:31:50.09#ibcon#first serial, iclass 31, count 0 2006.285.06:31:50.09#ibcon#enter sib2, iclass 31, count 0 2006.285.06:31:50.09#ibcon#flushed, iclass 31, count 0 2006.285.06:31:50.09#ibcon#about to write, iclass 31, count 0 2006.285.06:31:50.09#ibcon#wrote, iclass 31, count 0 2006.285.06:31:50.09#ibcon#about to read 3, iclass 31, count 0 2006.285.06:31:50.11#ibcon#read 3, iclass 31, count 0 2006.285.06:31:50.11#ibcon#about to read 4, iclass 31, count 0 2006.285.06:31:50.11#ibcon#read 4, iclass 31, count 0 2006.285.06:31:50.11#ibcon#about to read 5, iclass 31, count 0 2006.285.06:31:50.11#ibcon#read 5, iclass 31, count 0 2006.285.06:31:50.11#ibcon#about to read 6, iclass 31, count 0 2006.285.06:31:50.11#ibcon#read 6, iclass 31, count 0 2006.285.06:31:50.11#ibcon#end of sib2, iclass 31, count 0 2006.285.06:31:50.11#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:31:50.11#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:31:50.11#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:31:50.11#ibcon#*before write, iclass 31, count 0 2006.285.06:31:50.11#ibcon#enter sib2, iclass 31, count 0 2006.285.06:31:50.11#ibcon#flushed, iclass 31, count 0 2006.285.06:31:50.11#ibcon#about to write, iclass 31, count 0 2006.285.06:31:50.11#ibcon#wrote, iclass 31, count 0 2006.285.06:31:50.11#ibcon#about to read 3, iclass 31, count 0 2006.285.06:31:50.15#ibcon#read 3, iclass 31, count 0 2006.285.06:31:50.15#ibcon#about to read 4, iclass 31, count 0 2006.285.06:31:50.15#ibcon#read 4, iclass 31, count 0 2006.285.06:31:50.15#ibcon#about to read 5, iclass 31, count 0 2006.285.06:31:50.15#ibcon#read 5, iclass 31, count 0 2006.285.06:31:50.15#ibcon#about to read 6, iclass 31, count 0 2006.285.06:31:50.15#ibcon#read 6, iclass 31, count 0 2006.285.06:31:50.15#ibcon#end of sib2, iclass 31, count 0 2006.285.06:31:50.15#ibcon#*after write, iclass 31, count 0 2006.285.06:31:50.15#ibcon#*before return 0, iclass 31, count 0 2006.285.06:31:50.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:31:50.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:31:50.15#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:31:50.15#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:31:50.15$vck44/va=7,4 2006.285.06:31:50.15#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.06:31:50.15#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.06:31:50.15#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:50.15#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:31:50.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:31:50.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:31:50.21#ibcon#enter wrdev, iclass 33, count 2 2006.285.06:31:50.21#ibcon#first serial, iclass 33, count 2 2006.285.06:31:50.21#ibcon#enter sib2, iclass 33, count 2 2006.285.06:31:50.21#ibcon#flushed, iclass 33, count 2 2006.285.06:31:50.21#ibcon#about to write, iclass 33, count 2 2006.285.06:31:50.21#ibcon#wrote, iclass 33, count 2 2006.285.06:31:50.21#ibcon#about to read 3, iclass 33, count 2 2006.285.06:31:50.23#ibcon#read 3, iclass 33, count 2 2006.285.06:31:50.23#ibcon#about to read 4, iclass 33, count 2 2006.285.06:31:50.23#ibcon#read 4, iclass 33, count 2 2006.285.06:31:50.23#ibcon#about to read 5, iclass 33, count 2 2006.285.06:31:50.23#ibcon#read 5, iclass 33, count 2 2006.285.06:31:50.23#ibcon#about to read 6, iclass 33, count 2 2006.285.06:31:50.23#ibcon#read 6, iclass 33, count 2 2006.285.06:31:50.23#ibcon#end of sib2, iclass 33, count 2 2006.285.06:31:50.23#ibcon#*mode == 0, iclass 33, count 2 2006.285.06:31:50.23#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.06:31:50.23#ibcon#[25=AT07-04\r\n] 2006.285.06:31:50.23#ibcon#*before write, iclass 33, count 2 2006.285.06:31:50.23#ibcon#enter sib2, iclass 33, count 2 2006.285.06:31:50.23#ibcon#flushed, iclass 33, count 2 2006.285.06:31:50.23#ibcon#about to write, iclass 33, count 2 2006.285.06:31:50.23#ibcon#wrote, iclass 33, count 2 2006.285.06:31:50.23#ibcon#about to read 3, iclass 33, count 2 2006.285.06:31:50.26#ibcon#read 3, iclass 33, count 2 2006.285.06:31:50.26#ibcon#about to read 4, iclass 33, count 2 2006.285.06:31:50.26#ibcon#read 4, iclass 33, count 2 2006.285.06:31:50.26#ibcon#about to read 5, iclass 33, count 2 2006.285.06:31:50.26#ibcon#read 5, iclass 33, count 2 2006.285.06:31:50.26#ibcon#about to read 6, iclass 33, count 2 2006.285.06:31:50.26#ibcon#read 6, iclass 33, count 2 2006.285.06:31:50.26#ibcon#end of sib2, iclass 33, count 2 2006.285.06:31:50.26#ibcon#*after write, iclass 33, count 2 2006.285.06:31:50.26#ibcon#*before return 0, iclass 33, count 2 2006.285.06:31:50.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:31:50.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:31:50.26#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.06:31:50.26#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:50.26#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:31:50.38#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:31:50.38#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:31:50.38#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:31:50.38#ibcon#first serial, iclass 33, count 0 2006.285.06:31:50.38#ibcon#enter sib2, iclass 33, count 0 2006.285.06:31:50.38#ibcon#flushed, iclass 33, count 0 2006.285.06:31:50.38#ibcon#about to write, iclass 33, count 0 2006.285.06:31:50.38#ibcon#wrote, iclass 33, count 0 2006.285.06:31:50.38#ibcon#about to read 3, iclass 33, count 0 2006.285.06:31:50.40#ibcon#read 3, iclass 33, count 0 2006.285.06:31:50.40#ibcon#about to read 4, iclass 33, count 0 2006.285.06:31:50.40#ibcon#read 4, iclass 33, count 0 2006.285.06:31:50.40#ibcon#about to read 5, iclass 33, count 0 2006.285.06:31:50.40#ibcon#read 5, iclass 33, count 0 2006.285.06:31:50.40#ibcon#about to read 6, iclass 33, count 0 2006.285.06:31:50.40#ibcon#read 6, iclass 33, count 0 2006.285.06:31:50.40#ibcon#end of sib2, iclass 33, count 0 2006.285.06:31:50.40#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:31:50.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:31:50.40#ibcon#[25=USB\r\n] 2006.285.06:31:50.40#ibcon#*before write, iclass 33, count 0 2006.285.06:31:50.40#ibcon#enter sib2, iclass 33, count 0 2006.285.06:31:50.40#ibcon#flushed, iclass 33, count 0 2006.285.06:31:50.40#ibcon#about to write, iclass 33, count 0 2006.285.06:31:50.40#ibcon#wrote, iclass 33, count 0 2006.285.06:31:50.40#ibcon#about to read 3, iclass 33, count 0 2006.285.06:31:50.43#ibcon#read 3, iclass 33, count 0 2006.285.06:31:50.43#ibcon#about to read 4, iclass 33, count 0 2006.285.06:31:50.43#ibcon#read 4, iclass 33, count 0 2006.285.06:31:50.43#ibcon#about to read 5, iclass 33, count 0 2006.285.06:31:50.43#ibcon#read 5, iclass 33, count 0 2006.285.06:31:50.43#ibcon#about to read 6, iclass 33, count 0 2006.285.06:31:50.43#ibcon#read 6, iclass 33, count 0 2006.285.06:31:50.43#ibcon#end of sib2, iclass 33, count 0 2006.285.06:31:50.43#ibcon#*after write, iclass 33, count 0 2006.285.06:31:50.43#ibcon#*before return 0, iclass 33, count 0 2006.285.06:31:50.43#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:31:50.43#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:31:50.43#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:31:50.43#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:31:50.43$vck44/valo=8,884.99 2006.285.06:31:50.43#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.06:31:50.43#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.06:31:50.43#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:50.43#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:31:50.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:31:50.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:31:50.43#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:31:50.43#ibcon#first serial, iclass 35, count 0 2006.285.06:31:50.43#ibcon#enter sib2, iclass 35, count 0 2006.285.06:31:50.43#ibcon#flushed, iclass 35, count 0 2006.285.06:31:50.43#ibcon#about to write, iclass 35, count 0 2006.285.06:31:50.43#ibcon#wrote, iclass 35, count 0 2006.285.06:31:50.43#ibcon#about to read 3, iclass 35, count 0 2006.285.06:31:50.45#ibcon#read 3, iclass 35, count 0 2006.285.06:31:50.45#ibcon#about to read 4, iclass 35, count 0 2006.285.06:31:50.45#ibcon#read 4, iclass 35, count 0 2006.285.06:31:50.45#ibcon#about to read 5, iclass 35, count 0 2006.285.06:31:50.45#ibcon#read 5, iclass 35, count 0 2006.285.06:31:50.45#ibcon#about to read 6, iclass 35, count 0 2006.285.06:31:50.45#ibcon#read 6, iclass 35, count 0 2006.285.06:31:50.45#ibcon#end of sib2, iclass 35, count 0 2006.285.06:31:50.45#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:31:50.45#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:31:50.45#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:31:50.45#ibcon#*before write, iclass 35, count 0 2006.285.06:31:50.45#ibcon#enter sib2, iclass 35, count 0 2006.285.06:31:50.45#ibcon#flushed, iclass 35, count 0 2006.285.06:31:50.45#ibcon#about to write, iclass 35, count 0 2006.285.06:31:50.45#ibcon#wrote, iclass 35, count 0 2006.285.06:31:50.45#ibcon#about to read 3, iclass 35, count 0 2006.285.06:31:50.49#ibcon#read 3, iclass 35, count 0 2006.285.06:31:50.49#ibcon#about to read 4, iclass 35, count 0 2006.285.06:31:50.49#ibcon#read 4, iclass 35, count 0 2006.285.06:31:50.49#ibcon#about to read 5, iclass 35, count 0 2006.285.06:31:50.49#ibcon#read 5, iclass 35, count 0 2006.285.06:31:50.49#ibcon#about to read 6, iclass 35, count 0 2006.285.06:31:50.49#ibcon#read 6, iclass 35, count 0 2006.285.06:31:50.49#ibcon#end of sib2, iclass 35, count 0 2006.285.06:31:50.49#ibcon#*after write, iclass 35, count 0 2006.285.06:31:50.49#ibcon#*before return 0, iclass 35, count 0 2006.285.06:31:50.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:31:50.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:31:50.49#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:31:50.49#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:31:50.49$vck44/va=8,3 2006.285.06:31:50.49#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.06:31:50.49#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.06:31:50.49#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:50.49#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:31:50.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:31:50.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:31:50.55#ibcon#enter wrdev, iclass 37, count 2 2006.285.06:31:50.55#ibcon#first serial, iclass 37, count 2 2006.285.06:31:50.55#ibcon#enter sib2, iclass 37, count 2 2006.285.06:31:50.55#ibcon#flushed, iclass 37, count 2 2006.285.06:31:50.55#ibcon#about to write, iclass 37, count 2 2006.285.06:31:50.55#ibcon#wrote, iclass 37, count 2 2006.285.06:31:50.55#ibcon#about to read 3, iclass 37, count 2 2006.285.06:31:50.57#ibcon#read 3, iclass 37, count 2 2006.285.06:31:50.57#ibcon#about to read 4, iclass 37, count 2 2006.285.06:31:50.57#ibcon#read 4, iclass 37, count 2 2006.285.06:31:50.57#ibcon#about to read 5, iclass 37, count 2 2006.285.06:31:50.57#ibcon#read 5, iclass 37, count 2 2006.285.06:31:50.57#ibcon#about to read 6, iclass 37, count 2 2006.285.06:31:50.57#ibcon#read 6, iclass 37, count 2 2006.285.06:31:50.57#ibcon#end of sib2, iclass 37, count 2 2006.285.06:31:50.57#ibcon#*mode == 0, iclass 37, count 2 2006.285.06:31:50.57#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.06:31:50.57#ibcon#[25=AT08-03\r\n] 2006.285.06:31:50.57#ibcon#*before write, iclass 37, count 2 2006.285.06:31:50.57#ibcon#enter sib2, iclass 37, count 2 2006.285.06:31:50.57#ibcon#flushed, iclass 37, count 2 2006.285.06:31:50.57#ibcon#about to write, iclass 37, count 2 2006.285.06:31:50.57#ibcon#wrote, iclass 37, count 2 2006.285.06:31:50.57#ibcon#about to read 3, iclass 37, count 2 2006.285.06:31:50.60#ibcon#read 3, iclass 37, count 2 2006.285.06:31:50.60#ibcon#about to read 4, iclass 37, count 2 2006.285.06:31:50.60#ibcon#read 4, iclass 37, count 2 2006.285.06:31:50.60#ibcon#about to read 5, iclass 37, count 2 2006.285.06:31:50.60#ibcon#read 5, iclass 37, count 2 2006.285.06:31:50.60#ibcon#about to read 6, iclass 37, count 2 2006.285.06:31:50.60#ibcon#read 6, iclass 37, count 2 2006.285.06:31:50.60#ibcon#end of sib2, iclass 37, count 2 2006.285.06:31:50.60#ibcon#*after write, iclass 37, count 2 2006.285.06:31:50.60#ibcon#*before return 0, iclass 37, count 2 2006.285.06:31:50.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:31:50.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:31:50.60#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.06:31:50.60#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:50.60#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:31:50.72#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:31:50.72#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:31:50.72#ibcon#enter wrdev, iclass 37, count 0 2006.285.06:31:50.72#ibcon#first serial, iclass 37, count 0 2006.285.06:31:50.72#ibcon#enter sib2, iclass 37, count 0 2006.285.06:31:50.72#ibcon#flushed, iclass 37, count 0 2006.285.06:31:50.72#ibcon#about to write, iclass 37, count 0 2006.285.06:31:50.72#ibcon#wrote, iclass 37, count 0 2006.285.06:31:50.72#ibcon#about to read 3, iclass 37, count 0 2006.285.06:31:50.74#ibcon#read 3, iclass 37, count 0 2006.285.06:31:50.74#ibcon#about to read 4, iclass 37, count 0 2006.285.06:31:50.74#ibcon#read 4, iclass 37, count 0 2006.285.06:31:50.74#ibcon#about to read 5, iclass 37, count 0 2006.285.06:31:50.74#ibcon#read 5, iclass 37, count 0 2006.285.06:31:50.74#ibcon#about to read 6, iclass 37, count 0 2006.285.06:31:50.74#ibcon#read 6, iclass 37, count 0 2006.285.06:31:50.74#ibcon#end of sib2, iclass 37, count 0 2006.285.06:31:50.74#ibcon#*mode == 0, iclass 37, count 0 2006.285.06:31:50.74#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.06:31:50.74#ibcon#[25=USB\r\n] 2006.285.06:31:50.74#ibcon#*before write, iclass 37, count 0 2006.285.06:31:50.74#ibcon#enter sib2, iclass 37, count 0 2006.285.06:31:50.74#ibcon#flushed, iclass 37, count 0 2006.285.06:31:50.74#ibcon#about to write, iclass 37, count 0 2006.285.06:31:50.74#ibcon#wrote, iclass 37, count 0 2006.285.06:31:50.74#ibcon#about to read 3, iclass 37, count 0 2006.285.06:31:50.77#ibcon#read 3, iclass 37, count 0 2006.285.06:31:50.77#ibcon#about to read 4, iclass 37, count 0 2006.285.06:31:50.77#ibcon#read 4, iclass 37, count 0 2006.285.06:31:50.77#ibcon#about to read 5, iclass 37, count 0 2006.285.06:31:50.77#ibcon#read 5, iclass 37, count 0 2006.285.06:31:50.77#ibcon#about to read 6, iclass 37, count 0 2006.285.06:31:50.77#ibcon#read 6, iclass 37, count 0 2006.285.06:31:50.77#ibcon#end of sib2, iclass 37, count 0 2006.285.06:31:50.77#ibcon#*after write, iclass 37, count 0 2006.285.06:31:50.77#ibcon#*before return 0, iclass 37, count 0 2006.285.06:31:50.77#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:31:50.77#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:31:50.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.06:31:50.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.06:31:50.77$vck44/vblo=1,629.99 2006.285.06:31:50.77#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.06:31:50.77#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.06:31:50.77#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:50.77#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:31:50.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:31:50.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:31:50.77#ibcon#enter wrdev, iclass 39, count 0 2006.285.06:31:50.77#ibcon#first serial, iclass 39, count 0 2006.285.06:31:50.77#ibcon#enter sib2, iclass 39, count 0 2006.285.06:31:50.77#ibcon#flushed, iclass 39, count 0 2006.285.06:31:50.77#ibcon#about to write, iclass 39, count 0 2006.285.06:31:50.77#ibcon#wrote, iclass 39, count 0 2006.285.06:31:50.77#ibcon#about to read 3, iclass 39, count 0 2006.285.06:31:50.79#ibcon#read 3, iclass 39, count 0 2006.285.06:31:50.79#ibcon#about to read 4, iclass 39, count 0 2006.285.06:31:50.79#ibcon#read 4, iclass 39, count 0 2006.285.06:31:50.79#ibcon#about to read 5, iclass 39, count 0 2006.285.06:31:50.79#ibcon#read 5, iclass 39, count 0 2006.285.06:31:50.79#ibcon#about to read 6, iclass 39, count 0 2006.285.06:31:50.79#ibcon#read 6, iclass 39, count 0 2006.285.06:31:50.79#ibcon#end of sib2, iclass 39, count 0 2006.285.06:31:50.79#ibcon#*mode == 0, iclass 39, count 0 2006.285.06:31:50.79#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.06:31:50.79#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:31:50.79#ibcon#*before write, iclass 39, count 0 2006.285.06:31:50.79#ibcon#enter sib2, iclass 39, count 0 2006.285.06:31:50.79#ibcon#flushed, iclass 39, count 0 2006.285.06:31:50.79#ibcon#about to write, iclass 39, count 0 2006.285.06:31:50.79#ibcon#wrote, iclass 39, count 0 2006.285.06:31:50.79#ibcon#about to read 3, iclass 39, count 0 2006.285.06:31:50.83#ibcon#read 3, iclass 39, count 0 2006.285.06:31:50.83#ibcon#about to read 4, iclass 39, count 0 2006.285.06:31:50.83#ibcon#read 4, iclass 39, count 0 2006.285.06:31:50.83#ibcon#about to read 5, iclass 39, count 0 2006.285.06:31:50.83#ibcon#read 5, iclass 39, count 0 2006.285.06:31:50.83#ibcon#about to read 6, iclass 39, count 0 2006.285.06:31:50.83#ibcon#read 6, iclass 39, count 0 2006.285.06:31:50.83#ibcon#end of sib2, iclass 39, count 0 2006.285.06:31:50.83#ibcon#*after write, iclass 39, count 0 2006.285.06:31:50.83#ibcon#*before return 0, iclass 39, count 0 2006.285.06:31:50.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:31:50.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:31:50.83#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.06:31:50.83#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.06:31:50.83$vck44/vb=1,4 2006.285.06:31:50.83#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.06:31:50.83#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.06:31:50.83#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:50.83#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:31:50.83#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:31:50.83#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:31:50.83#ibcon#enter wrdev, iclass 3, count 2 2006.285.06:31:50.83#ibcon#first serial, iclass 3, count 2 2006.285.06:31:50.83#ibcon#enter sib2, iclass 3, count 2 2006.285.06:31:50.83#ibcon#flushed, iclass 3, count 2 2006.285.06:31:50.83#ibcon#about to write, iclass 3, count 2 2006.285.06:31:50.83#ibcon#wrote, iclass 3, count 2 2006.285.06:31:50.83#ibcon#about to read 3, iclass 3, count 2 2006.285.06:31:50.85#ibcon#read 3, iclass 3, count 2 2006.285.06:31:50.85#ibcon#about to read 4, iclass 3, count 2 2006.285.06:31:50.85#ibcon#read 4, iclass 3, count 2 2006.285.06:31:50.85#ibcon#about to read 5, iclass 3, count 2 2006.285.06:31:50.85#ibcon#read 5, iclass 3, count 2 2006.285.06:31:50.85#ibcon#about to read 6, iclass 3, count 2 2006.285.06:31:50.85#ibcon#read 6, iclass 3, count 2 2006.285.06:31:50.85#ibcon#end of sib2, iclass 3, count 2 2006.285.06:31:50.85#ibcon#*mode == 0, iclass 3, count 2 2006.285.06:31:50.85#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.06:31:50.85#ibcon#[27=AT01-04\r\n] 2006.285.06:31:50.85#ibcon#*before write, iclass 3, count 2 2006.285.06:31:50.85#ibcon#enter sib2, iclass 3, count 2 2006.285.06:31:50.85#ibcon#flushed, iclass 3, count 2 2006.285.06:31:50.85#ibcon#about to write, iclass 3, count 2 2006.285.06:31:50.85#ibcon#wrote, iclass 3, count 2 2006.285.06:31:50.85#ibcon#about to read 3, iclass 3, count 2 2006.285.06:31:50.88#ibcon#read 3, iclass 3, count 2 2006.285.06:31:50.88#ibcon#about to read 4, iclass 3, count 2 2006.285.06:31:50.88#ibcon#read 4, iclass 3, count 2 2006.285.06:31:50.88#ibcon#about to read 5, iclass 3, count 2 2006.285.06:31:50.88#ibcon#read 5, iclass 3, count 2 2006.285.06:31:50.88#ibcon#about to read 6, iclass 3, count 2 2006.285.06:31:50.88#ibcon#read 6, iclass 3, count 2 2006.285.06:31:50.88#ibcon#end of sib2, iclass 3, count 2 2006.285.06:31:50.88#ibcon#*after write, iclass 3, count 2 2006.285.06:31:50.88#ibcon#*before return 0, iclass 3, count 2 2006.285.06:31:50.88#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:31:50.88#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:31:50.88#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.06:31:50.88#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:50.88#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:31:51.00#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:31:51.00#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:31:51.00#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:31:51.00#ibcon#first serial, iclass 3, count 0 2006.285.06:31:51.00#ibcon#enter sib2, iclass 3, count 0 2006.285.06:31:51.00#ibcon#flushed, iclass 3, count 0 2006.285.06:31:51.00#ibcon#about to write, iclass 3, count 0 2006.285.06:31:51.00#ibcon#wrote, iclass 3, count 0 2006.285.06:31:51.00#ibcon#about to read 3, iclass 3, count 0 2006.285.06:31:51.02#ibcon#read 3, iclass 3, count 0 2006.285.06:31:51.02#ibcon#about to read 4, iclass 3, count 0 2006.285.06:31:51.02#ibcon#read 4, iclass 3, count 0 2006.285.06:31:51.02#ibcon#about to read 5, iclass 3, count 0 2006.285.06:31:51.02#ibcon#read 5, iclass 3, count 0 2006.285.06:31:51.02#ibcon#about to read 6, iclass 3, count 0 2006.285.06:31:51.02#ibcon#read 6, iclass 3, count 0 2006.285.06:31:51.02#ibcon#end of sib2, iclass 3, count 0 2006.285.06:31:51.02#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:31:51.02#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:31:51.02#ibcon#[27=USB\r\n] 2006.285.06:31:51.02#ibcon#*before write, iclass 3, count 0 2006.285.06:31:51.02#ibcon#enter sib2, iclass 3, count 0 2006.285.06:31:51.02#ibcon#flushed, iclass 3, count 0 2006.285.06:31:51.02#ibcon#about to write, iclass 3, count 0 2006.285.06:31:51.02#ibcon#wrote, iclass 3, count 0 2006.285.06:31:51.02#ibcon#about to read 3, iclass 3, count 0 2006.285.06:31:51.05#ibcon#read 3, iclass 3, count 0 2006.285.06:31:51.05#ibcon#about to read 4, iclass 3, count 0 2006.285.06:31:51.05#ibcon#read 4, iclass 3, count 0 2006.285.06:31:51.05#ibcon#about to read 5, iclass 3, count 0 2006.285.06:31:51.05#ibcon#read 5, iclass 3, count 0 2006.285.06:31:51.05#ibcon#about to read 6, iclass 3, count 0 2006.285.06:31:51.05#ibcon#read 6, iclass 3, count 0 2006.285.06:31:51.05#ibcon#end of sib2, iclass 3, count 0 2006.285.06:31:51.05#ibcon#*after write, iclass 3, count 0 2006.285.06:31:51.05#ibcon#*before return 0, iclass 3, count 0 2006.285.06:31:51.05#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:31:51.05#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:31:51.05#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:31:51.05#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:31:51.05$vck44/vblo=2,634.99 2006.285.06:31:51.05#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.06:31:51.05#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.06:31:51.05#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:51.05#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:31:51.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:31:51.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:31:51.05#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:31:51.05#ibcon#first serial, iclass 5, count 0 2006.285.06:31:51.05#ibcon#enter sib2, iclass 5, count 0 2006.285.06:31:51.05#ibcon#flushed, iclass 5, count 0 2006.285.06:31:51.05#ibcon#about to write, iclass 5, count 0 2006.285.06:31:51.05#ibcon#wrote, iclass 5, count 0 2006.285.06:31:51.05#ibcon#about to read 3, iclass 5, count 0 2006.285.06:31:51.07#ibcon#read 3, iclass 5, count 0 2006.285.06:31:51.07#ibcon#about to read 4, iclass 5, count 0 2006.285.06:31:51.07#ibcon#read 4, iclass 5, count 0 2006.285.06:31:51.07#ibcon#about to read 5, iclass 5, count 0 2006.285.06:31:51.07#ibcon#read 5, iclass 5, count 0 2006.285.06:31:51.07#ibcon#about to read 6, iclass 5, count 0 2006.285.06:31:51.07#ibcon#read 6, iclass 5, count 0 2006.285.06:31:51.07#ibcon#end of sib2, iclass 5, count 0 2006.285.06:31:51.07#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:31:51.07#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:31:51.07#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:31:51.07#ibcon#*before write, iclass 5, count 0 2006.285.06:31:51.07#ibcon#enter sib2, iclass 5, count 0 2006.285.06:31:51.07#ibcon#flushed, iclass 5, count 0 2006.285.06:31:51.07#ibcon#about to write, iclass 5, count 0 2006.285.06:31:51.07#ibcon#wrote, iclass 5, count 0 2006.285.06:31:51.07#ibcon#about to read 3, iclass 5, count 0 2006.285.06:31:51.11#ibcon#read 3, iclass 5, count 0 2006.285.06:31:51.11#ibcon#about to read 4, iclass 5, count 0 2006.285.06:31:51.11#ibcon#read 4, iclass 5, count 0 2006.285.06:31:51.11#ibcon#about to read 5, iclass 5, count 0 2006.285.06:31:51.11#ibcon#read 5, iclass 5, count 0 2006.285.06:31:51.11#ibcon#about to read 6, iclass 5, count 0 2006.285.06:31:51.11#ibcon#read 6, iclass 5, count 0 2006.285.06:31:51.11#ibcon#end of sib2, iclass 5, count 0 2006.285.06:31:51.11#ibcon#*after write, iclass 5, count 0 2006.285.06:31:51.11#ibcon#*before return 0, iclass 5, count 0 2006.285.06:31:51.11#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:31:51.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:31:51.11#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:31:51.11#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:31:51.11$vck44/vb=2,5 2006.285.06:31:51.11#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.06:31:51.11#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.06:31:51.11#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:51.11#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:31:51.17#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:31:51.17#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:31:51.17#ibcon#enter wrdev, iclass 7, count 2 2006.285.06:31:51.17#ibcon#first serial, iclass 7, count 2 2006.285.06:31:51.17#ibcon#enter sib2, iclass 7, count 2 2006.285.06:31:51.17#ibcon#flushed, iclass 7, count 2 2006.285.06:31:51.17#ibcon#about to write, iclass 7, count 2 2006.285.06:31:51.17#ibcon#wrote, iclass 7, count 2 2006.285.06:31:51.17#ibcon#about to read 3, iclass 7, count 2 2006.285.06:31:51.19#ibcon#read 3, iclass 7, count 2 2006.285.06:31:51.19#ibcon#about to read 4, iclass 7, count 2 2006.285.06:31:51.19#ibcon#read 4, iclass 7, count 2 2006.285.06:31:51.19#ibcon#about to read 5, iclass 7, count 2 2006.285.06:31:51.19#ibcon#read 5, iclass 7, count 2 2006.285.06:31:51.19#ibcon#about to read 6, iclass 7, count 2 2006.285.06:31:51.19#ibcon#read 6, iclass 7, count 2 2006.285.06:31:51.19#ibcon#end of sib2, iclass 7, count 2 2006.285.06:31:51.19#ibcon#*mode == 0, iclass 7, count 2 2006.285.06:31:51.19#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.06:31:51.19#ibcon#[27=AT02-05\r\n] 2006.285.06:31:51.19#ibcon#*before write, iclass 7, count 2 2006.285.06:31:51.19#ibcon#enter sib2, iclass 7, count 2 2006.285.06:31:51.19#ibcon#flushed, iclass 7, count 2 2006.285.06:31:51.19#ibcon#about to write, iclass 7, count 2 2006.285.06:31:51.19#ibcon#wrote, iclass 7, count 2 2006.285.06:31:51.19#ibcon#about to read 3, iclass 7, count 2 2006.285.06:31:51.22#ibcon#read 3, iclass 7, count 2 2006.285.06:31:51.22#ibcon#about to read 4, iclass 7, count 2 2006.285.06:31:51.22#ibcon#read 4, iclass 7, count 2 2006.285.06:31:51.22#ibcon#about to read 5, iclass 7, count 2 2006.285.06:31:51.22#ibcon#read 5, iclass 7, count 2 2006.285.06:31:51.22#ibcon#about to read 6, iclass 7, count 2 2006.285.06:31:51.22#ibcon#read 6, iclass 7, count 2 2006.285.06:31:51.22#ibcon#end of sib2, iclass 7, count 2 2006.285.06:31:51.22#ibcon#*after write, iclass 7, count 2 2006.285.06:31:51.22#ibcon#*before return 0, iclass 7, count 2 2006.285.06:31:51.22#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:31:51.22#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:31:51.22#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.06:31:51.22#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:51.22#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:31:51.34#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:31:51.34#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:31:51.34#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:31:51.34#ibcon#first serial, iclass 7, count 0 2006.285.06:31:51.34#ibcon#enter sib2, iclass 7, count 0 2006.285.06:31:51.34#ibcon#flushed, iclass 7, count 0 2006.285.06:31:51.34#ibcon#about to write, iclass 7, count 0 2006.285.06:31:51.34#ibcon#wrote, iclass 7, count 0 2006.285.06:31:51.34#ibcon#about to read 3, iclass 7, count 0 2006.285.06:31:51.36#ibcon#read 3, iclass 7, count 0 2006.285.06:31:51.36#ibcon#about to read 4, iclass 7, count 0 2006.285.06:31:51.36#ibcon#read 4, iclass 7, count 0 2006.285.06:31:51.36#ibcon#about to read 5, iclass 7, count 0 2006.285.06:31:51.36#ibcon#read 5, iclass 7, count 0 2006.285.06:31:51.36#ibcon#about to read 6, iclass 7, count 0 2006.285.06:31:51.36#ibcon#read 6, iclass 7, count 0 2006.285.06:31:51.36#ibcon#end of sib2, iclass 7, count 0 2006.285.06:31:51.36#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:31:51.36#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:31:51.36#ibcon#[27=USB\r\n] 2006.285.06:31:51.36#ibcon#*before write, iclass 7, count 0 2006.285.06:31:51.36#ibcon#enter sib2, iclass 7, count 0 2006.285.06:31:51.36#ibcon#flushed, iclass 7, count 0 2006.285.06:31:51.36#ibcon#about to write, iclass 7, count 0 2006.285.06:31:51.36#ibcon#wrote, iclass 7, count 0 2006.285.06:31:51.36#ibcon#about to read 3, iclass 7, count 0 2006.285.06:31:51.39#ibcon#read 3, iclass 7, count 0 2006.285.06:31:51.39#ibcon#about to read 4, iclass 7, count 0 2006.285.06:31:51.39#ibcon#read 4, iclass 7, count 0 2006.285.06:31:51.39#ibcon#about to read 5, iclass 7, count 0 2006.285.06:31:51.39#ibcon#read 5, iclass 7, count 0 2006.285.06:31:51.39#ibcon#about to read 6, iclass 7, count 0 2006.285.06:31:51.39#ibcon#read 6, iclass 7, count 0 2006.285.06:31:51.39#ibcon#end of sib2, iclass 7, count 0 2006.285.06:31:51.39#ibcon#*after write, iclass 7, count 0 2006.285.06:31:51.39#ibcon#*before return 0, iclass 7, count 0 2006.285.06:31:51.39#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:31:51.39#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:31:51.39#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:31:51.39#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:31:51.39$vck44/vblo=3,649.99 2006.285.06:31:51.39#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.06:31:51.39#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.06:31:51.39#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:51.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:31:51.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:31:51.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:31:51.39#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:31:51.39#ibcon#first serial, iclass 11, count 0 2006.285.06:31:51.39#ibcon#enter sib2, iclass 11, count 0 2006.285.06:31:51.39#ibcon#flushed, iclass 11, count 0 2006.285.06:31:51.39#ibcon#about to write, iclass 11, count 0 2006.285.06:31:51.39#ibcon#wrote, iclass 11, count 0 2006.285.06:31:51.39#ibcon#about to read 3, iclass 11, count 0 2006.285.06:31:51.41#ibcon#read 3, iclass 11, count 0 2006.285.06:31:51.41#ibcon#about to read 4, iclass 11, count 0 2006.285.06:31:51.41#ibcon#read 4, iclass 11, count 0 2006.285.06:31:51.41#ibcon#about to read 5, iclass 11, count 0 2006.285.06:31:51.41#ibcon#read 5, iclass 11, count 0 2006.285.06:31:51.41#ibcon#about to read 6, iclass 11, count 0 2006.285.06:31:51.41#ibcon#read 6, iclass 11, count 0 2006.285.06:31:51.41#ibcon#end of sib2, iclass 11, count 0 2006.285.06:31:51.41#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:31:51.41#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:31:51.41#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:31:51.41#ibcon#*before write, iclass 11, count 0 2006.285.06:31:51.41#ibcon#enter sib2, iclass 11, count 0 2006.285.06:31:51.41#ibcon#flushed, iclass 11, count 0 2006.285.06:31:51.41#ibcon#about to write, iclass 11, count 0 2006.285.06:31:51.41#ibcon#wrote, iclass 11, count 0 2006.285.06:31:51.41#ibcon#about to read 3, iclass 11, count 0 2006.285.06:31:51.45#ibcon#read 3, iclass 11, count 0 2006.285.06:31:51.45#ibcon#about to read 4, iclass 11, count 0 2006.285.06:31:51.45#ibcon#read 4, iclass 11, count 0 2006.285.06:31:51.45#ibcon#about to read 5, iclass 11, count 0 2006.285.06:31:51.45#ibcon#read 5, iclass 11, count 0 2006.285.06:31:51.45#ibcon#about to read 6, iclass 11, count 0 2006.285.06:31:51.45#ibcon#read 6, iclass 11, count 0 2006.285.06:31:51.45#ibcon#end of sib2, iclass 11, count 0 2006.285.06:31:51.45#ibcon#*after write, iclass 11, count 0 2006.285.06:31:51.45#ibcon#*before return 0, iclass 11, count 0 2006.285.06:31:51.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:31:51.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:31:51.45#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:31:51.45#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:31:51.45$vck44/vb=3,4 2006.285.06:31:51.45#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.06:31:51.45#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.06:31:51.45#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:51.45#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:31:51.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:31:51.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:31:51.51#ibcon#enter wrdev, iclass 13, count 2 2006.285.06:31:51.51#ibcon#first serial, iclass 13, count 2 2006.285.06:31:51.51#ibcon#enter sib2, iclass 13, count 2 2006.285.06:31:51.51#ibcon#flushed, iclass 13, count 2 2006.285.06:31:51.51#ibcon#about to write, iclass 13, count 2 2006.285.06:31:51.51#ibcon#wrote, iclass 13, count 2 2006.285.06:31:51.51#ibcon#about to read 3, iclass 13, count 2 2006.285.06:31:51.53#ibcon#read 3, iclass 13, count 2 2006.285.06:31:51.53#ibcon#about to read 4, iclass 13, count 2 2006.285.06:31:51.53#ibcon#read 4, iclass 13, count 2 2006.285.06:31:51.53#ibcon#about to read 5, iclass 13, count 2 2006.285.06:31:51.53#ibcon#read 5, iclass 13, count 2 2006.285.06:31:51.53#ibcon#about to read 6, iclass 13, count 2 2006.285.06:31:51.53#ibcon#read 6, iclass 13, count 2 2006.285.06:31:51.53#ibcon#end of sib2, iclass 13, count 2 2006.285.06:31:51.53#ibcon#*mode == 0, iclass 13, count 2 2006.285.06:31:51.53#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.06:31:51.53#ibcon#[27=AT03-04\r\n] 2006.285.06:31:51.53#ibcon#*before write, iclass 13, count 2 2006.285.06:31:51.53#ibcon#enter sib2, iclass 13, count 2 2006.285.06:31:51.53#ibcon#flushed, iclass 13, count 2 2006.285.06:31:51.53#ibcon#about to write, iclass 13, count 2 2006.285.06:31:51.53#ibcon#wrote, iclass 13, count 2 2006.285.06:31:51.53#ibcon#about to read 3, iclass 13, count 2 2006.285.06:31:51.56#ibcon#read 3, iclass 13, count 2 2006.285.06:31:51.56#ibcon#about to read 4, iclass 13, count 2 2006.285.06:31:51.56#ibcon#read 4, iclass 13, count 2 2006.285.06:31:51.56#ibcon#about to read 5, iclass 13, count 2 2006.285.06:31:51.56#ibcon#read 5, iclass 13, count 2 2006.285.06:31:51.56#ibcon#about to read 6, iclass 13, count 2 2006.285.06:31:51.56#ibcon#read 6, iclass 13, count 2 2006.285.06:31:51.56#ibcon#end of sib2, iclass 13, count 2 2006.285.06:31:51.56#ibcon#*after write, iclass 13, count 2 2006.285.06:31:51.56#ibcon#*before return 0, iclass 13, count 2 2006.285.06:31:51.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:31:51.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:31:51.56#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.06:31:51.56#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:51.56#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:31:51.68#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:31:51.68#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:31:51.68#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:31:51.68#ibcon#first serial, iclass 13, count 0 2006.285.06:31:51.68#ibcon#enter sib2, iclass 13, count 0 2006.285.06:31:51.68#ibcon#flushed, iclass 13, count 0 2006.285.06:31:51.68#ibcon#about to write, iclass 13, count 0 2006.285.06:31:51.68#ibcon#wrote, iclass 13, count 0 2006.285.06:31:51.68#ibcon#about to read 3, iclass 13, count 0 2006.285.06:31:51.70#ibcon#read 3, iclass 13, count 0 2006.285.06:31:51.70#ibcon#about to read 4, iclass 13, count 0 2006.285.06:31:51.70#ibcon#read 4, iclass 13, count 0 2006.285.06:31:51.70#ibcon#about to read 5, iclass 13, count 0 2006.285.06:31:51.70#ibcon#read 5, iclass 13, count 0 2006.285.06:31:51.70#ibcon#about to read 6, iclass 13, count 0 2006.285.06:31:51.70#ibcon#read 6, iclass 13, count 0 2006.285.06:31:51.70#ibcon#end of sib2, iclass 13, count 0 2006.285.06:31:51.70#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:31:51.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:31:51.70#ibcon#[27=USB\r\n] 2006.285.06:31:51.70#ibcon#*before write, iclass 13, count 0 2006.285.06:31:51.70#ibcon#enter sib2, iclass 13, count 0 2006.285.06:31:51.70#ibcon#flushed, iclass 13, count 0 2006.285.06:31:51.70#ibcon#about to write, iclass 13, count 0 2006.285.06:31:51.70#ibcon#wrote, iclass 13, count 0 2006.285.06:31:51.70#ibcon#about to read 3, iclass 13, count 0 2006.285.06:31:51.73#ibcon#read 3, iclass 13, count 0 2006.285.06:31:51.73#ibcon#about to read 4, iclass 13, count 0 2006.285.06:31:51.73#ibcon#read 4, iclass 13, count 0 2006.285.06:31:51.73#ibcon#about to read 5, iclass 13, count 0 2006.285.06:31:51.73#ibcon#read 5, iclass 13, count 0 2006.285.06:31:51.73#ibcon#about to read 6, iclass 13, count 0 2006.285.06:31:51.73#ibcon#read 6, iclass 13, count 0 2006.285.06:31:51.73#ibcon#end of sib2, iclass 13, count 0 2006.285.06:31:51.73#ibcon#*after write, iclass 13, count 0 2006.285.06:31:51.73#ibcon#*before return 0, iclass 13, count 0 2006.285.06:31:51.73#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:31:51.73#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:31:51.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:31:51.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:31:51.73$vck44/vblo=4,679.99 2006.285.06:31:51.73#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.06:31:51.73#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.06:31:51.73#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:51.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:31:51.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:31:51.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:31:51.73#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:31:51.73#ibcon#first serial, iclass 15, count 0 2006.285.06:31:51.73#ibcon#enter sib2, iclass 15, count 0 2006.285.06:31:51.73#ibcon#flushed, iclass 15, count 0 2006.285.06:31:51.73#ibcon#about to write, iclass 15, count 0 2006.285.06:31:51.73#ibcon#wrote, iclass 15, count 0 2006.285.06:31:51.73#ibcon#about to read 3, iclass 15, count 0 2006.285.06:31:51.75#ibcon#read 3, iclass 15, count 0 2006.285.06:31:51.75#ibcon#about to read 4, iclass 15, count 0 2006.285.06:31:51.75#ibcon#read 4, iclass 15, count 0 2006.285.06:31:51.75#ibcon#about to read 5, iclass 15, count 0 2006.285.06:31:51.75#ibcon#read 5, iclass 15, count 0 2006.285.06:31:51.75#ibcon#about to read 6, iclass 15, count 0 2006.285.06:31:51.75#ibcon#read 6, iclass 15, count 0 2006.285.06:31:51.75#ibcon#end of sib2, iclass 15, count 0 2006.285.06:31:51.75#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:31:51.75#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:31:51.75#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:31:51.75#ibcon#*before write, iclass 15, count 0 2006.285.06:31:51.75#ibcon#enter sib2, iclass 15, count 0 2006.285.06:31:51.75#ibcon#flushed, iclass 15, count 0 2006.285.06:31:51.75#ibcon#about to write, iclass 15, count 0 2006.285.06:31:51.75#ibcon#wrote, iclass 15, count 0 2006.285.06:31:51.75#ibcon#about to read 3, iclass 15, count 0 2006.285.06:31:51.79#ibcon#read 3, iclass 15, count 0 2006.285.06:31:51.79#ibcon#about to read 4, iclass 15, count 0 2006.285.06:31:51.79#ibcon#read 4, iclass 15, count 0 2006.285.06:31:51.79#ibcon#about to read 5, iclass 15, count 0 2006.285.06:31:51.79#ibcon#read 5, iclass 15, count 0 2006.285.06:31:51.79#ibcon#about to read 6, iclass 15, count 0 2006.285.06:31:51.79#ibcon#read 6, iclass 15, count 0 2006.285.06:31:51.79#ibcon#end of sib2, iclass 15, count 0 2006.285.06:31:51.79#ibcon#*after write, iclass 15, count 0 2006.285.06:31:51.79#ibcon#*before return 0, iclass 15, count 0 2006.285.06:31:51.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:31:51.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:31:51.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:31:51.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:31:51.79$vck44/vb=4,5 2006.285.06:31:51.79#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.06:31:51.79#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.06:31:51.79#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:51.79#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:31:51.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:31:51.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:31:51.85#ibcon#enter wrdev, iclass 17, count 2 2006.285.06:31:51.85#ibcon#first serial, iclass 17, count 2 2006.285.06:31:51.85#ibcon#enter sib2, iclass 17, count 2 2006.285.06:31:51.85#ibcon#flushed, iclass 17, count 2 2006.285.06:31:51.85#ibcon#about to write, iclass 17, count 2 2006.285.06:31:51.85#ibcon#wrote, iclass 17, count 2 2006.285.06:31:51.85#ibcon#about to read 3, iclass 17, count 2 2006.285.06:31:51.87#ibcon#read 3, iclass 17, count 2 2006.285.06:31:51.87#ibcon#about to read 4, iclass 17, count 2 2006.285.06:31:51.87#ibcon#read 4, iclass 17, count 2 2006.285.06:31:51.87#ibcon#about to read 5, iclass 17, count 2 2006.285.06:31:51.87#ibcon#read 5, iclass 17, count 2 2006.285.06:31:51.87#ibcon#about to read 6, iclass 17, count 2 2006.285.06:31:51.87#ibcon#read 6, iclass 17, count 2 2006.285.06:31:51.87#ibcon#end of sib2, iclass 17, count 2 2006.285.06:31:51.87#ibcon#*mode == 0, iclass 17, count 2 2006.285.06:31:51.87#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.06:31:51.87#ibcon#[27=AT04-05\r\n] 2006.285.06:31:51.87#ibcon#*before write, iclass 17, count 2 2006.285.06:31:51.87#ibcon#enter sib2, iclass 17, count 2 2006.285.06:31:51.87#ibcon#flushed, iclass 17, count 2 2006.285.06:31:51.87#ibcon#about to write, iclass 17, count 2 2006.285.06:31:51.87#ibcon#wrote, iclass 17, count 2 2006.285.06:31:51.87#ibcon#about to read 3, iclass 17, count 2 2006.285.06:31:51.90#ibcon#read 3, iclass 17, count 2 2006.285.06:31:51.90#ibcon#about to read 4, iclass 17, count 2 2006.285.06:31:51.90#ibcon#read 4, iclass 17, count 2 2006.285.06:31:51.90#ibcon#about to read 5, iclass 17, count 2 2006.285.06:31:51.90#ibcon#read 5, iclass 17, count 2 2006.285.06:31:51.90#ibcon#about to read 6, iclass 17, count 2 2006.285.06:31:51.90#ibcon#read 6, iclass 17, count 2 2006.285.06:31:51.90#ibcon#end of sib2, iclass 17, count 2 2006.285.06:31:51.90#ibcon#*after write, iclass 17, count 2 2006.285.06:31:51.90#ibcon#*before return 0, iclass 17, count 2 2006.285.06:31:51.90#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:31:51.90#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:31:51.90#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.06:31:51.90#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:51.90#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:31:52.02#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:31:52.02#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:31:52.02#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:31:52.02#ibcon#first serial, iclass 17, count 0 2006.285.06:31:52.02#ibcon#enter sib2, iclass 17, count 0 2006.285.06:31:52.02#ibcon#flushed, iclass 17, count 0 2006.285.06:31:52.02#ibcon#about to write, iclass 17, count 0 2006.285.06:31:52.02#ibcon#wrote, iclass 17, count 0 2006.285.06:31:52.02#ibcon#about to read 3, iclass 17, count 0 2006.285.06:31:52.04#ibcon#read 3, iclass 17, count 0 2006.285.06:31:52.04#ibcon#about to read 4, iclass 17, count 0 2006.285.06:31:52.04#ibcon#read 4, iclass 17, count 0 2006.285.06:31:52.04#ibcon#about to read 5, iclass 17, count 0 2006.285.06:31:52.04#ibcon#read 5, iclass 17, count 0 2006.285.06:31:52.04#ibcon#about to read 6, iclass 17, count 0 2006.285.06:31:52.04#ibcon#read 6, iclass 17, count 0 2006.285.06:31:52.04#ibcon#end of sib2, iclass 17, count 0 2006.285.06:31:52.04#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:31:52.04#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:31:52.04#ibcon#[27=USB\r\n] 2006.285.06:31:52.04#ibcon#*before write, iclass 17, count 0 2006.285.06:31:52.04#ibcon#enter sib2, iclass 17, count 0 2006.285.06:31:52.04#ibcon#flushed, iclass 17, count 0 2006.285.06:31:52.04#ibcon#about to write, iclass 17, count 0 2006.285.06:31:52.04#ibcon#wrote, iclass 17, count 0 2006.285.06:31:52.04#ibcon#about to read 3, iclass 17, count 0 2006.285.06:31:52.07#ibcon#read 3, iclass 17, count 0 2006.285.06:31:52.07#ibcon#about to read 4, iclass 17, count 0 2006.285.06:31:52.07#ibcon#read 4, iclass 17, count 0 2006.285.06:31:52.07#ibcon#about to read 5, iclass 17, count 0 2006.285.06:31:52.07#ibcon#read 5, iclass 17, count 0 2006.285.06:31:52.07#ibcon#about to read 6, iclass 17, count 0 2006.285.06:31:52.07#ibcon#read 6, iclass 17, count 0 2006.285.06:31:52.07#ibcon#end of sib2, iclass 17, count 0 2006.285.06:31:52.07#ibcon#*after write, iclass 17, count 0 2006.285.06:31:52.07#ibcon#*before return 0, iclass 17, count 0 2006.285.06:31:52.07#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:31:52.07#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:31:52.07#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:31:52.07#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:31:52.07$vck44/vblo=5,709.99 2006.285.06:31:52.07#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.06:31:52.07#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.06:31:52.07#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:52.07#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:31:52.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:31:52.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:31:52.07#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:31:52.07#ibcon#first serial, iclass 19, count 0 2006.285.06:31:52.07#ibcon#enter sib2, iclass 19, count 0 2006.285.06:31:52.07#ibcon#flushed, iclass 19, count 0 2006.285.06:31:52.07#ibcon#about to write, iclass 19, count 0 2006.285.06:31:52.07#ibcon#wrote, iclass 19, count 0 2006.285.06:31:52.07#ibcon#about to read 3, iclass 19, count 0 2006.285.06:31:52.09#ibcon#read 3, iclass 19, count 0 2006.285.06:31:52.20#ibcon#about to read 4, iclass 19, count 0 2006.285.06:31:52.20#ibcon#read 4, iclass 19, count 0 2006.285.06:31:52.20#ibcon#about to read 5, iclass 19, count 0 2006.285.06:31:52.20#ibcon#read 5, iclass 19, count 0 2006.285.06:31:52.20#ibcon#about to read 6, iclass 19, count 0 2006.285.06:31:52.20#ibcon#read 6, iclass 19, count 0 2006.285.06:31:52.20#ibcon#end of sib2, iclass 19, count 0 2006.285.06:31:52.20#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:31:52.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:31:52.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:31:52.20#ibcon#*before write, iclass 19, count 0 2006.285.06:31:52.20#ibcon#enter sib2, iclass 19, count 0 2006.285.06:31:52.20#ibcon#flushed, iclass 19, count 0 2006.285.06:31:52.20#ibcon#about to write, iclass 19, count 0 2006.285.06:31:52.20#ibcon#wrote, iclass 19, count 0 2006.285.06:31:52.20#ibcon#about to read 3, iclass 19, count 0 2006.285.06:31:52.24#ibcon#read 3, iclass 19, count 0 2006.285.06:31:52.24#ibcon#about to read 4, iclass 19, count 0 2006.285.06:31:52.24#ibcon#read 4, iclass 19, count 0 2006.285.06:31:52.24#ibcon#about to read 5, iclass 19, count 0 2006.285.06:31:52.24#ibcon#read 5, iclass 19, count 0 2006.285.06:31:52.24#ibcon#about to read 6, iclass 19, count 0 2006.285.06:31:52.24#ibcon#read 6, iclass 19, count 0 2006.285.06:31:52.24#ibcon#end of sib2, iclass 19, count 0 2006.285.06:31:52.24#ibcon#*after write, iclass 19, count 0 2006.285.06:31:52.24#ibcon#*before return 0, iclass 19, count 0 2006.285.06:31:52.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:31:52.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:31:52.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:31:52.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:31:52.24$vck44/vb=5,4 2006.285.06:31:52.24#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.06:31:52.24#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.06:31:52.24#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:52.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:31:52.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:31:52.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:31:52.24#ibcon#enter wrdev, iclass 21, count 2 2006.285.06:31:52.24#ibcon#first serial, iclass 21, count 2 2006.285.06:31:52.24#ibcon#enter sib2, iclass 21, count 2 2006.285.06:31:52.24#ibcon#flushed, iclass 21, count 2 2006.285.06:31:52.24#ibcon#about to write, iclass 21, count 2 2006.285.06:31:52.24#ibcon#wrote, iclass 21, count 2 2006.285.06:31:52.24#ibcon#about to read 3, iclass 21, count 2 2006.285.06:31:52.26#ibcon#read 3, iclass 21, count 2 2006.285.06:31:52.26#ibcon#about to read 4, iclass 21, count 2 2006.285.06:31:52.26#ibcon#read 4, iclass 21, count 2 2006.285.06:31:52.26#ibcon#about to read 5, iclass 21, count 2 2006.285.06:31:52.26#ibcon#read 5, iclass 21, count 2 2006.285.06:31:52.26#ibcon#about to read 6, iclass 21, count 2 2006.285.06:31:52.26#ibcon#read 6, iclass 21, count 2 2006.285.06:31:52.26#ibcon#end of sib2, iclass 21, count 2 2006.285.06:31:52.26#ibcon#*mode == 0, iclass 21, count 2 2006.285.06:31:52.26#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.06:31:52.26#ibcon#[27=AT05-04\r\n] 2006.285.06:31:52.26#ibcon#*before write, iclass 21, count 2 2006.285.06:31:52.26#ibcon#enter sib2, iclass 21, count 2 2006.285.06:31:52.26#ibcon#flushed, iclass 21, count 2 2006.285.06:31:52.26#ibcon#about to write, iclass 21, count 2 2006.285.06:31:52.26#ibcon#wrote, iclass 21, count 2 2006.285.06:31:52.26#ibcon#about to read 3, iclass 21, count 2 2006.285.06:31:52.29#ibcon#read 3, iclass 21, count 2 2006.285.06:31:52.29#ibcon#about to read 4, iclass 21, count 2 2006.285.06:31:52.29#ibcon#read 4, iclass 21, count 2 2006.285.06:31:52.29#ibcon#about to read 5, iclass 21, count 2 2006.285.06:31:52.29#ibcon#read 5, iclass 21, count 2 2006.285.06:31:52.29#ibcon#about to read 6, iclass 21, count 2 2006.285.06:31:52.29#ibcon#read 6, iclass 21, count 2 2006.285.06:31:52.29#ibcon#end of sib2, iclass 21, count 2 2006.285.06:31:52.29#ibcon#*after write, iclass 21, count 2 2006.285.06:31:52.29#ibcon#*before return 0, iclass 21, count 2 2006.285.06:31:52.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:31:52.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:31:52.29#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.06:31:52.29#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:52.29#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:31:52.41#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:31:52.41#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:31:52.41#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:31:52.41#ibcon#first serial, iclass 21, count 0 2006.285.06:31:52.41#ibcon#enter sib2, iclass 21, count 0 2006.285.06:31:52.41#ibcon#flushed, iclass 21, count 0 2006.285.06:31:52.41#ibcon#about to write, iclass 21, count 0 2006.285.06:31:52.41#ibcon#wrote, iclass 21, count 0 2006.285.06:31:52.41#ibcon#about to read 3, iclass 21, count 0 2006.285.06:31:52.43#ibcon#read 3, iclass 21, count 0 2006.285.06:31:52.43#ibcon#about to read 4, iclass 21, count 0 2006.285.06:31:52.43#ibcon#read 4, iclass 21, count 0 2006.285.06:31:52.43#ibcon#about to read 5, iclass 21, count 0 2006.285.06:31:52.43#ibcon#read 5, iclass 21, count 0 2006.285.06:31:52.43#ibcon#about to read 6, iclass 21, count 0 2006.285.06:31:52.43#ibcon#read 6, iclass 21, count 0 2006.285.06:31:52.43#ibcon#end of sib2, iclass 21, count 0 2006.285.06:31:52.43#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:31:52.43#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:31:52.43#ibcon#[27=USB\r\n] 2006.285.06:31:52.43#ibcon#*before write, iclass 21, count 0 2006.285.06:31:52.43#ibcon#enter sib2, iclass 21, count 0 2006.285.06:31:52.43#ibcon#flushed, iclass 21, count 0 2006.285.06:31:52.43#ibcon#about to write, iclass 21, count 0 2006.285.06:31:52.43#ibcon#wrote, iclass 21, count 0 2006.285.06:31:52.43#ibcon#about to read 3, iclass 21, count 0 2006.285.06:31:52.46#ibcon#read 3, iclass 21, count 0 2006.285.06:31:52.46#ibcon#about to read 4, iclass 21, count 0 2006.285.06:31:52.46#ibcon#read 4, iclass 21, count 0 2006.285.06:31:52.46#ibcon#about to read 5, iclass 21, count 0 2006.285.06:31:52.46#ibcon#read 5, iclass 21, count 0 2006.285.06:31:52.46#ibcon#about to read 6, iclass 21, count 0 2006.285.06:31:52.46#ibcon#read 6, iclass 21, count 0 2006.285.06:31:52.46#ibcon#end of sib2, iclass 21, count 0 2006.285.06:31:52.46#ibcon#*after write, iclass 21, count 0 2006.285.06:31:52.46#ibcon#*before return 0, iclass 21, count 0 2006.285.06:31:52.46#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:31:52.46#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:31:52.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:31:52.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:31:52.46$vck44/vblo=6,719.99 2006.285.06:31:52.46#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.06:31:52.46#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.06:31:52.46#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:52.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:31:52.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:31:52.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:31:52.46#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:31:52.46#ibcon#first serial, iclass 23, count 0 2006.285.06:31:52.46#ibcon#enter sib2, iclass 23, count 0 2006.285.06:31:52.46#ibcon#flushed, iclass 23, count 0 2006.285.06:31:52.46#ibcon#about to write, iclass 23, count 0 2006.285.06:31:52.46#ibcon#wrote, iclass 23, count 0 2006.285.06:31:52.46#ibcon#about to read 3, iclass 23, count 0 2006.285.06:31:52.48#ibcon#read 3, iclass 23, count 0 2006.285.06:31:52.48#ibcon#about to read 4, iclass 23, count 0 2006.285.06:31:52.48#ibcon#read 4, iclass 23, count 0 2006.285.06:31:52.48#ibcon#about to read 5, iclass 23, count 0 2006.285.06:31:52.48#ibcon#read 5, iclass 23, count 0 2006.285.06:31:52.48#ibcon#about to read 6, iclass 23, count 0 2006.285.06:31:52.48#ibcon#read 6, iclass 23, count 0 2006.285.06:31:52.48#ibcon#end of sib2, iclass 23, count 0 2006.285.06:31:52.48#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:31:52.48#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:31:52.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:31:52.48#ibcon#*before write, iclass 23, count 0 2006.285.06:31:52.48#ibcon#enter sib2, iclass 23, count 0 2006.285.06:31:52.48#ibcon#flushed, iclass 23, count 0 2006.285.06:31:52.48#ibcon#about to write, iclass 23, count 0 2006.285.06:31:52.48#ibcon#wrote, iclass 23, count 0 2006.285.06:31:52.48#ibcon#about to read 3, iclass 23, count 0 2006.285.06:31:52.52#ibcon#read 3, iclass 23, count 0 2006.285.06:31:52.52#ibcon#about to read 4, iclass 23, count 0 2006.285.06:31:52.52#ibcon#read 4, iclass 23, count 0 2006.285.06:31:52.52#ibcon#about to read 5, iclass 23, count 0 2006.285.06:31:52.52#ibcon#read 5, iclass 23, count 0 2006.285.06:31:52.52#ibcon#about to read 6, iclass 23, count 0 2006.285.06:31:52.52#ibcon#read 6, iclass 23, count 0 2006.285.06:31:52.52#ibcon#end of sib2, iclass 23, count 0 2006.285.06:31:52.52#ibcon#*after write, iclass 23, count 0 2006.285.06:31:52.52#ibcon#*before return 0, iclass 23, count 0 2006.285.06:31:52.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:31:52.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:31:52.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:31:52.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:31:52.52$vck44/vb=6,3 2006.285.06:31:52.52#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.06:31:52.52#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.06:31:52.52#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:52.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:31:52.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:31:52.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:31:52.58#ibcon#enter wrdev, iclass 25, count 2 2006.285.06:31:52.58#ibcon#first serial, iclass 25, count 2 2006.285.06:31:52.58#ibcon#enter sib2, iclass 25, count 2 2006.285.06:31:52.58#ibcon#flushed, iclass 25, count 2 2006.285.06:31:52.58#ibcon#about to write, iclass 25, count 2 2006.285.06:31:52.58#ibcon#wrote, iclass 25, count 2 2006.285.06:31:52.58#ibcon#about to read 3, iclass 25, count 2 2006.285.06:31:52.60#ibcon#read 3, iclass 25, count 2 2006.285.06:31:52.60#ibcon#about to read 4, iclass 25, count 2 2006.285.06:31:52.60#ibcon#read 4, iclass 25, count 2 2006.285.06:31:52.60#ibcon#about to read 5, iclass 25, count 2 2006.285.06:31:52.60#ibcon#read 5, iclass 25, count 2 2006.285.06:31:52.60#ibcon#about to read 6, iclass 25, count 2 2006.285.06:31:52.60#ibcon#read 6, iclass 25, count 2 2006.285.06:31:52.60#ibcon#end of sib2, iclass 25, count 2 2006.285.06:31:52.60#ibcon#*mode == 0, iclass 25, count 2 2006.285.06:31:52.60#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.06:31:52.60#ibcon#[27=AT06-03\r\n] 2006.285.06:31:52.60#ibcon#*before write, iclass 25, count 2 2006.285.06:31:52.60#ibcon#enter sib2, iclass 25, count 2 2006.285.06:31:52.60#ibcon#flushed, iclass 25, count 2 2006.285.06:31:52.60#ibcon#about to write, iclass 25, count 2 2006.285.06:31:52.60#ibcon#wrote, iclass 25, count 2 2006.285.06:31:52.60#ibcon#about to read 3, iclass 25, count 2 2006.285.06:31:52.63#ibcon#read 3, iclass 25, count 2 2006.285.06:31:52.63#ibcon#about to read 4, iclass 25, count 2 2006.285.06:31:52.63#ibcon#read 4, iclass 25, count 2 2006.285.06:31:52.63#ibcon#about to read 5, iclass 25, count 2 2006.285.06:31:52.63#ibcon#read 5, iclass 25, count 2 2006.285.06:31:52.63#ibcon#about to read 6, iclass 25, count 2 2006.285.06:31:52.63#ibcon#read 6, iclass 25, count 2 2006.285.06:31:52.63#ibcon#end of sib2, iclass 25, count 2 2006.285.06:31:52.63#ibcon#*after write, iclass 25, count 2 2006.285.06:31:52.63#ibcon#*before return 0, iclass 25, count 2 2006.285.06:31:52.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:31:52.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:31:52.63#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.06:31:52.63#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:52.63#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:31:52.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:31:52.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:31:52.75#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:31:52.75#ibcon#first serial, iclass 25, count 0 2006.285.06:31:52.75#ibcon#enter sib2, iclass 25, count 0 2006.285.06:31:52.75#ibcon#flushed, iclass 25, count 0 2006.285.06:31:52.75#ibcon#about to write, iclass 25, count 0 2006.285.06:31:52.75#ibcon#wrote, iclass 25, count 0 2006.285.06:31:52.75#ibcon#about to read 3, iclass 25, count 0 2006.285.06:31:52.77#ibcon#read 3, iclass 25, count 0 2006.285.06:31:52.77#ibcon#about to read 4, iclass 25, count 0 2006.285.06:31:52.77#ibcon#read 4, iclass 25, count 0 2006.285.06:31:52.77#ibcon#about to read 5, iclass 25, count 0 2006.285.06:31:52.77#ibcon#read 5, iclass 25, count 0 2006.285.06:31:52.77#ibcon#about to read 6, iclass 25, count 0 2006.285.06:31:52.77#ibcon#read 6, iclass 25, count 0 2006.285.06:31:52.77#ibcon#end of sib2, iclass 25, count 0 2006.285.06:31:52.77#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:31:52.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:31:52.77#ibcon#[27=USB\r\n] 2006.285.06:31:52.77#ibcon#*before write, iclass 25, count 0 2006.285.06:31:52.77#ibcon#enter sib2, iclass 25, count 0 2006.285.06:31:52.77#ibcon#flushed, iclass 25, count 0 2006.285.06:31:52.77#ibcon#about to write, iclass 25, count 0 2006.285.06:31:52.77#ibcon#wrote, iclass 25, count 0 2006.285.06:31:52.77#ibcon#about to read 3, iclass 25, count 0 2006.285.06:31:52.80#ibcon#read 3, iclass 25, count 0 2006.285.06:31:52.80#ibcon#about to read 4, iclass 25, count 0 2006.285.06:31:52.80#ibcon#read 4, iclass 25, count 0 2006.285.06:31:52.80#ibcon#about to read 5, iclass 25, count 0 2006.285.06:31:52.80#ibcon#read 5, iclass 25, count 0 2006.285.06:31:52.80#ibcon#about to read 6, iclass 25, count 0 2006.285.06:31:52.80#ibcon#read 6, iclass 25, count 0 2006.285.06:31:52.80#ibcon#end of sib2, iclass 25, count 0 2006.285.06:31:52.80#ibcon#*after write, iclass 25, count 0 2006.285.06:31:52.80#ibcon#*before return 0, iclass 25, count 0 2006.285.06:31:52.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:31:52.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:31:52.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:31:52.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:31:52.80$vck44/vblo=7,734.99 2006.285.06:31:52.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.06:31:52.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.06:31:52.80#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:52.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:31:52.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:31:52.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:31:52.80#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:31:52.80#ibcon#first serial, iclass 27, count 0 2006.285.06:31:52.80#ibcon#enter sib2, iclass 27, count 0 2006.285.06:31:52.80#ibcon#flushed, iclass 27, count 0 2006.285.06:31:52.80#ibcon#about to write, iclass 27, count 0 2006.285.06:31:52.80#ibcon#wrote, iclass 27, count 0 2006.285.06:31:52.80#ibcon#about to read 3, iclass 27, count 0 2006.285.06:31:52.82#ibcon#read 3, iclass 27, count 0 2006.285.06:31:52.91#ibcon#about to read 4, iclass 27, count 0 2006.285.06:31:52.91#ibcon#read 4, iclass 27, count 0 2006.285.06:31:52.91#ibcon#about to read 5, iclass 27, count 0 2006.285.06:31:52.91#ibcon#read 5, iclass 27, count 0 2006.285.06:31:52.91#ibcon#about to read 6, iclass 27, count 0 2006.285.06:31:52.91#ibcon#read 6, iclass 27, count 0 2006.285.06:31:52.91#ibcon#end of sib2, iclass 27, count 0 2006.285.06:31:52.91#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:31:52.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:31:52.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:31:52.91#ibcon#*before write, iclass 27, count 0 2006.285.06:31:52.91#ibcon#enter sib2, iclass 27, count 0 2006.285.06:31:52.91#ibcon#flushed, iclass 27, count 0 2006.285.06:31:52.91#ibcon#about to write, iclass 27, count 0 2006.285.06:31:52.91#ibcon#wrote, iclass 27, count 0 2006.285.06:31:52.91#ibcon#about to read 3, iclass 27, count 0 2006.285.06:31:52.95#ibcon#read 3, iclass 27, count 0 2006.285.06:31:52.95#ibcon#about to read 4, iclass 27, count 0 2006.285.06:31:52.95#ibcon#read 4, iclass 27, count 0 2006.285.06:31:52.95#ibcon#about to read 5, iclass 27, count 0 2006.285.06:31:52.95#ibcon#read 5, iclass 27, count 0 2006.285.06:31:52.95#ibcon#about to read 6, iclass 27, count 0 2006.285.06:31:52.95#ibcon#read 6, iclass 27, count 0 2006.285.06:31:52.95#ibcon#end of sib2, iclass 27, count 0 2006.285.06:31:52.95#ibcon#*after write, iclass 27, count 0 2006.285.06:31:52.95#ibcon#*before return 0, iclass 27, count 0 2006.285.06:31:52.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:31:52.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:31:52.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:31:52.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:31:52.95$vck44/vb=7,4 2006.285.06:31:52.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.06:31:52.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.06:31:52.95#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:52.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:31:52.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:31:52.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:31:52.95#ibcon#enter wrdev, iclass 29, count 2 2006.285.06:31:52.95#ibcon#first serial, iclass 29, count 2 2006.285.06:31:52.95#ibcon#enter sib2, iclass 29, count 2 2006.285.06:31:52.95#ibcon#flushed, iclass 29, count 2 2006.285.06:31:52.95#ibcon#about to write, iclass 29, count 2 2006.285.06:31:52.95#ibcon#wrote, iclass 29, count 2 2006.285.06:31:52.95#ibcon#about to read 3, iclass 29, count 2 2006.285.06:31:52.97#ibcon#read 3, iclass 29, count 2 2006.285.06:31:52.97#ibcon#about to read 4, iclass 29, count 2 2006.285.06:31:52.97#ibcon#read 4, iclass 29, count 2 2006.285.06:31:52.97#ibcon#about to read 5, iclass 29, count 2 2006.285.06:31:52.97#ibcon#read 5, iclass 29, count 2 2006.285.06:31:52.97#ibcon#about to read 6, iclass 29, count 2 2006.285.06:31:52.97#ibcon#read 6, iclass 29, count 2 2006.285.06:31:52.97#ibcon#end of sib2, iclass 29, count 2 2006.285.06:31:52.97#ibcon#*mode == 0, iclass 29, count 2 2006.285.06:31:52.97#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.06:31:52.97#ibcon#[27=AT07-04\r\n] 2006.285.06:31:52.97#ibcon#*before write, iclass 29, count 2 2006.285.06:31:52.97#ibcon#enter sib2, iclass 29, count 2 2006.285.06:31:52.97#ibcon#flushed, iclass 29, count 2 2006.285.06:31:52.97#ibcon#about to write, iclass 29, count 2 2006.285.06:31:52.97#ibcon#wrote, iclass 29, count 2 2006.285.06:31:52.97#ibcon#about to read 3, iclass 29, count 2 2006.285.06:31:53.00#ibcon#read 3, iclass 29, count 2 2006.285.06:31:53.00#ibcon#about to read 4, iclass 29, count 2 2006.285.06:31:53.00#ibcon#read 4, iclass 29, count 2 2006.285.06:31:53.00#ibcon#about to read 5, iclass 29, count 2 2006.285.06:31:53.00#ibcon#read 5, iclass 29, count 2 2006.285.06:31:53.00#ibcon#about to read 6, iclass 29, count 2 2006.285.06:31:53.00#ibcon#read 6, iclass 29, count 2 2006.285.06:31:53.00#ibcon#end of sib2, iclass 29, count 2 2006.285.06:31:53.00#ibcon#*after write, iclass 29, count 2 2006.285.06:31:53.00#ibcon#*before return 0, iclass 29, count 2 2006.285.06:31:53.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:31:53.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:31:53.00#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.06:31:53.00#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:53.00#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:31:53.12#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:31:53.12#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:31:53.12#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:31:53.12#ibcon#first serial, iclass 29, count 0 2006.285.06:31:53.12#ibcon#enter sib2, iclass 29, count 0 2006.285.06:31:53.12#ibcon#flushed, iclass 29, count 0 2006.285.06:31:53.12#ibcon#about to write, iclass 29, count 0 2006.285.06:31:53.12#ibcon#wrote, iclass 29, count 0 2006.285.06:31:53.12#ibcon#about to read 3, iclass 29, count 0 2006.285.06:31:53.14#ibcon#read 3, iclass 29, count 0 2006.285.06:31:53.14#ibcon#about to read 4, iclass 29, count 0 2006.285.06:31:53.14#ibcon#read 4, iclass 29, count 0 2006.285.06:31:53.14#ibcon#about to read 5, iclass 29, count 0 2006.285.06:31:53.14#ibcon#read 5, iclass 29, count 0 2006.285.06:31:53.14#ibcon#about to read 6, iclass 29, count 0 2006.285.06:31:53.14#ibcon#read 6, iclass 29, count 0 2006.285.06:31:53.14#ibcon#end of sib2, iclass 29, count 0 2006.285.06:31:53.14#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:31:53.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:31:53.14#ibcon#[27=USB\r\n] 2006.285.06:31:53.14#ibcon#*before write, iclass 29, count 0 2006.285.06:31:53.14#ibcon#enter sib2, iclass 29, count 0 2006.285.06:31:53.14#ibcon#flushed, iclass 29, count 0 2006.285.06:31:53.14#ibcon#about to write, iclass 29, count 0 2006.285.06:31:53.14#ibcon#wrote, iclass 29, count 0 2006.285.06:31:53.14#ibcon#about to read 3, iclass 29, count 0 2006.285.06:31:53.17#ibcon#read 3, iclass 29, count 0 2006.285.06:31:53.17#ibcon#about to read 4, iclass 29, count 0 2006.285.06:31:53.17#ibcon#read 4, iclass 29, count 0 2006.285.06:31:53.17#ibcon#about to read 5, iclass 29, count 0 2006.285.06:31:53.17#ibcon#read 5, iclass 29, count 0 2006.285.06:31:53.17#ibcon#about to read 6, iclass 29, count 0 2006.285.06:31:53.17#ibcon#read 6, iclass 29, count 0 2006.285.06:31:53.17#ibcon#end of sib2, iclass 29, count 0 2006.285.06:31:53.17#ibcon#*after write, iclass 29, count 0 2006.285.06:31:53.17#ibcon#*before return 0, iclass 29, count 0 2006.285.06:31:53.17#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:31:53.17#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:31:53.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:31:53.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:31:53.17$vck44/vblo=8,744.99 2006.285.06:31:53.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.06:31:53.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.06:31:53.17#ibcon#ireg 17 cls_cnt 0 2006.285.06:31:53.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:31:53.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:31:53.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:31:53.17#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:31:53.17#ibcon#first serial, iclass 31, count 0 2006.285.06:31:53.17#ibcon#enter sib2, iclass 31, count 0 2006.285.06:31:53.17#ibcon#flushed, iclass 31, count 0 2006.285.06:31:53.17#ibcon#about to write, iclass 31, count 0 2006.285.06:31:53.17#ibcon#wrote, iclass 31, count 0 2006.285.06:31:53.17#ibcon#about to read 3, iclass 31, count 0 2006.285.06:31:53.19#ibcon#read 3, iclass 31, count 0 2006.285.06:31:53.19#ibcon#about to read 4, iclass 31, count 0 2006.285.06:31:53.19#ibcon#read 4, iclass 31, count 0 2006.285.06:31:53.19#ibcon#about to read 5, iclass 31, count 0 2006.285.06:31:53.19#ibcon#read 5, iclass 31, count 0 2006.285.06:31:53.19#ibcon#about to read 6, iclass 31, count 0 2006.285.06:31:53.19#ibcon#read 6, iclass 31, count 0 2006.285.06:31:53.19#ibcon#end of sib2, iclass 31, count 0 2006.285.06:31:53.19#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:31:53.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:31:53.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:31:53.19#ibcon#*before write, iclass 31, count 0 2006.285.06:31:53.19#ibcon#enter sib2, iclass 31, count 0 2006.285.06:31:53.19#ibcon#flushed, iclass 31, count 0 2006.285.06:31:53.19#ibcon#about to write, iclass 31, count 0 2006.285.06:31:53.19#ibcon#wrote, iclass 31, count 0 2006.285.06:31:53.19#ibcon#about to read 3, iclass 31, count 0 2006.285.06:31:53.23#ibcon#read 3, iclass 31, count 0 2006.285.06:31:53.23#ibcon#about to read 4, iclass 31, count 0 2006.285.06:31:53.23#ibcon#read 4, iclass 31, count 0 2006.285.06:31:53.23#ibcon#about to read 5, iclass 31, count 0 2006.285.06:31:53.23#ibcon#read 5, iclass 31, count 0 2006.285.06:31:53.23#ibcon#about to read 6, iclass 31, count 0 2006.285.06:31:53.23#ibcon#read 6, iclass 31, count 0 2006.285.06:31:53.23#ibcon#end of sib2, iclass 31, count 0 2006.285.06:31:53.23#ibcon#*after write, iclass 31, count 0 2006.285.06:31:53.23#ibcon#*before return 0, iclass 31, count 0 2006.285.06:31:53.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:31:53.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:31:53.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:31:53.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:31:53.23$vck44/vb=8,4 2006.285.06:31:53.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.06:31:53.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.06:31:53.23#ibcon#ireg 11 cls_cnt 2 2006.285.06:31:53.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:31:53.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:31:53.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:31:53.29#ibcon#enter wrdev, iclass 33, count 2 2006.285.06:31:53.29#ibcon#first serial, iclass 33, count 2 2006.285.06:31:53.29#ibcon#enter sib2, iclass 33, count 2 2006.285.06:31:53.29#ibcon#flushed, iclass 33, count 2 2006.285.06:31:53.29#ibcon#about to write, iclass 33, count 2 2006.285.06:31:53.29#ibcon#wrote, iclass 33, count 2 2006.285.06:31:53.29#ibcon#about to read 3, iclass 33, count 2 2006.285.06:31:53.31#ibcon#read 3, iclass 33, count 2 2006.285.06:31:53.31#ibcon#about to read 4, iclass 33, count 2 2006.285.06:31:53.31#ibcon#read 4, iclass 33, count 2 2006.285.06:31:53.31#ibcon#about to read 5, iclass 33, count 2 2006.285.06:31:53.31#ibcon#read 5, iclass 33, count 2 2006.285.06:31:53.31#ibcon#about to read 6, iclass 33, count 2 2006.285.06:31:53.31#ibcon#read 6, iclass 33, count 2 2006.285.06:31:53.31#ibcon#end of sib2, iclass 33, count 2 2006.285.06:31:53.31#ibcon#*mode == 0, iclass 33, count 2 2006.285.06:31:53.31#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.06:31:53.31#ibcon#[27=AT08-04\r\n] 2006.285.06:31:53.31#ibcon#*before write, iclass 33, count 2 2006.285.06:31:53.31#ibcon#enter sib2, iclass 33, count 2 2006.285.06:31:53.31#ibcon#flushed, iclass 33, count 2 2006.285.06:31:53.31#ibcon#about to write, iclass 33, count 2 2006.285.06:31:53.31#ibcon#wrote, iclass 33, count 2 2006.285.06:31:53.31#ibcon#about to read 3, iclass 33, count 2 2006.285.06:31:53.34#ibcon#read 3, iclass 33, count 2 2006.285.06:31:53.34#ibcon#about to read 4, iclass 33, count 2 2006.285.06:31:53.34#ibcon#read 4, iclass 33, count 2 2006.285.06:31:53.34#ibcon#about to read 5, iclass 33, count 2 2006.285.06:31:53.34#ibcon#read 5, iclass 33, count 2 2006.285.06:31:53.34#ibcon#about to read 6, iclass 33, count 2 2006.285.06:31:53.34#ibcon#read 6, iclass 33, count 2 2006.285.06:31:53.34#ibcon#end of sib2, iclass 33, count 2 2006.285.06:31:53.34#ibcon#*after write, iclass 33, count 2 2006.285.06:31:53.34#ibcon#*before return 0, iclass 33, count 2 2006.285.06:31:53.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:31:53.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:31:53.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.06:31:53.34#ibcon#ireg 7 cls_cnt 0 2006.285.06:31:53.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:31:53.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:31:53.46#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:31:53.46#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:31:53.46#ibcon#first serial, iclass 33, count 0 2006.285.06:31:53.46#ibcon#enter sib2, iclass 33, count 0 2006.285.06:31:53.46#ibcon#flushed, iclass 33, count 0 2006.285.06:31:53.46#ibcon#about to write, iclass 33, count 0 2006.285.06:31:53.46#ibcon#wrote, iclass 33, count 0 2006.285.06:31:53.46#ibcon#about to read 3, iclass 33, count 0 2006.285.06:31:53.48#ibcon#read 3, iclass 33, count 0 2006.285.06:31:53.48#ibcon#about to read 4, iclass 33, count 0 2006.285.06:31:53.48#ibcon#read 4, iclass 33, count 0 2006.285.06:31:53.48#ibcon#about to read 5, iclass 33, count 0 2006.285.06:31:53.48#ibcon#read 5, iclass 33, count 0 2006.285.06:31:53.48#ibcon#about to read 6, iclass 33, count 0 2006.285.06:31:53.48#ibcon#read 6, iclass 33, count 0 2006.285.06:31:53.48#ibcon#end of sib2, iclass 33, count 0 2006.285.06:31:53.48#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:31:53.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:31:53.48#ibcon#[27=USB\r\n] 2006.285.06:31:53.48#ibcon#*before write, iclass 33, count 0 2006.285.06:31:53.48#ibcon#enter sib2, iclass 33, count 0 2006.285.06:31:53.48#ibcon#flushed, iclass 33, count 0 2006.285.06:31:53.48#ibcon#about to write, iclass 33, count 0 2006.285.06:31:53.48#ibcon#wrote, iclass 33, count 0 2006.285.06:31:53.48#ibcon#about to read 3, iclass 33, count 0 2006.285.06:31:53.51#ibcon#read 3, iclass 33, count 0 2006.285.06:31:53.51#ibcon#about to read 4, iclass 33, count 0 2006.285.06:31:53.51#ibcon#read 4, iclass 33, count 0 2006.285.06:31:53.51#ibcon#about to read 5, iclass 33, count 0 2006.285.06:31:53.51#ibcon#read 5, iclass 33, count 0 2006.285.06:31:53.51#ibcon#about to read 6, iclass 33, count 0 2006.285.06:31:53.51#ibcon#read 6, iclass 33, count 0 2006.285.06:31:53.51#ibcon#end of sib2, iclass 33, count 0 2006.285.06:31:53.51#ibcon#*after write, iclass 33, count 0 2006.285.06:31:53.51#ibcon#*before return 0, iclass 33, count 0 2006.285.06:31:53.51#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:31:53.51#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:31:53.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:31:53.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:31:53.51$vck44/vabw=wide 2006.285.06:31:53.51#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.06:31:53.51#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.06:31:53.51#ibcon#ireg 8 cls_cnt 0 2006.285.06:31:53.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:31:53.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:31:53.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:31:53.51#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:31:53.51#ibcon#first serial, iclass 35, count 0 2006.285.06:31:53.51#ibcon#enter sib2, iclass 35, count 0 2006.285.06:31:53.51#ibcon#flushed, iclass 35, count 0 2006.285.06:31:53.51#ibcon#about to write, iclass 35, count 0 2006.285.06:31:53.51#ibcon#wrote, iclass 35, count 0 2006.285.06:31:53.51#ibcon#about to read 3, iclass 35, count 0 2006.285.06:31:53.53#ibcon#read 3, iclass 35, count 0 2006.285.06:31:53.53#ibcon#about to read 4, iclass 35, count 0 2006.285.06:31:53.53#ibcon#read 4, iclass 35, count 0 2006.285.06:31:53.53#ibcon#about to read 5, iclass 35, count 0 2006.285.06:31:53.53#ibcon#read 5, iclass 35, count 0 2006.285.06:31:53.53#ibcon#about to read 6, iclass 35, count 0 2006.285.06:31:53.53#ibcon#read 6, iclass 35, count 0 2006.285.06:31:53.53#ibcon#end of sib2, iclass 35, count 0 2006.285.06:31:53.53#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:31:53.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:31:53.53#ibcon#[25=BW32\r\n] 2006.285.06:31:53.53#ibcon#*before write, iclass 35, count 0 2006.285.06:31:53.53#ibcon#enter sib2, iclass 35, count 0 2006.285.06:31:53.53#ibcon#flushed, iclass 35, count 0 2006.285.06:31:53.53#ibcon#about to write, iclass 35, count 0 2006.285.06:31:53.53#ibcon#wrote, iclass 35, count 0 2006.285.06:31:53.53#ibcon#about to read 3, iclass 35, count 0 2006.285.06:31:53.56#ibcon#read 3, iclass 35, count 0 2006.285.06:31:53.56#ibcon#about to read 4, iclass 35, count 0 2006.285.06:31:53.56#ibcon#read 4, iclass 35, count 0 2006.285.06:31:53.56#ibcon#about to read 5, iclass 35, count 0 2006.285.06:31:53.56#ibcon#read 5, iclass 35, count 0 2006.285.06:31:53.56#ibcon#about to read 6, iclass 35, count 0 2006.285.06:31:53.56#ibcon#read 6, iclass 35, count 0 2006.285.06:31:53.56#ibcon#end of sib2, iclass 35, count 0 2006.285.06:31:53.56#ibcon#*after write, iclass 35, count 0 2006.285.06:31:53.56#ibcon#*before return 0, iclass 35, count 0 2006.285.06:31:53.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:31:53.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:31:53.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:31:53.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:31:53.56$vck44/vbbw=wide 2006.285.06:31:53.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.06:31:53.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.06:31:53.56#ibcon#ireg 8 cls_cnt 0 2006.285.06:31:53.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:31:53.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:31:53.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:31:53.63#ibcon#enter wrdev, iclass 37, count 0 2006.285.06:31:53.63#ibcon#first serial, iclass 37, count 0 2006.285.06:31:53.63#ibcon#enter sib2, iclass 37, count 0 2006.285.06:31:53.63#ibcon#flushed, iclass 37, count 0 2006.285.06:31:53.63#ibcon#about to write, iclass 37, count 0 2006.285.06:31:53.63#ibcon#wrote, iclass 37, count 0 2006.285.06:31:53.63#ibcon#about to read 3, iclass 37, count 0 2006.285.06:31:53.65#ibcon#read 3, iclass 37, count 0 2006.285.06:31:53.65#ibcon#about to read 4, iclass 37, count 0 2006.285.06:31:53.65#ibcon#read 4, iclass 37, count 0 2006.285.06:31:53.65#ibcon#about to read 5, iclass 37, count 0 2006.285.06:31:53.65#ibcon#read 5, iclass 37, count 0 2006.285.06:31:53.65#ibcon#about to read 6, iclass 37, count 0 2006.285.06:31:53.65#ibcon#read 6, iclass 37, count 0 2006.285.06:31:53.65#ibcon#end of sib2, iclass 37, count 0 2006.285.06:31:53.65#ibcon#*mode == 0, iclass 37, count 0 2006.285.06:31:53.65#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.06:31:53.65#ibcon#[27=BW32\r\n] 2006.285.06:31:53.65#ibcon#*before write, iclass 37, count 0 2006.285.06:31:53.65#ibcon#enter sib2, iclass 37, count 0 2006.285.06:31:53.65#ibcon#flushed, iclass 37, count 0 2006.285.06:31:53.65#ibcon#about to write, iclass 37, count 0 2006.285.06:31:53.65#ibcon#wrote, iclass 37, count 0 2006.285.06:31:53.65#ibcon#about to read 3, iclass 37, count 0 2006.285.06:31:53.68#ibcon#read 3, iclass 37, count 0 2006.285.06:31:53.68#ibcon#about to read 4, iclass 37, count 0 2006.285.06:31:53.68#ibcon#read 4, iclass 37, count 0 2006.285.06:31:53.68#ibcon#about to read 5, iclass 37, count 0 2006.285.06:31:53.68#ibcon#read 5, iclass 37, count 0 2006.285.06:31:53.68#ibcon#about to read 6, iclass 37, count 0 2006.285.06:31:53.68#ibcon#read 6, iclass 37, count 0 2006.285.06:31:53.68#ibcon#end of sib2, iclass 37, count 0 2006.285.06:31:53.68#ibcon#*after write, iclass 37, count 0 2006.285.06:31:53.68#ibcon#*before return 0, iclass 37, count 0 2006.285.06:31:53.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:31:53.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:31:53.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.06:31:53.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.06:31:53.68$setupk4/ifdk4 2006.285.06:31:53.68$ifdk4/lo= 2006.285.06:31:53.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:31:53.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:31:53.68$ifdk4/patch= 2006.285.06:31:53.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:31:53.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:31:53.69$setupk4/!*+20s 2006.285.06:31:54.71#abcon#<5=/05 4.8 7.6 24.88 671014.1\r\n> 2006.285.06:31:54.73#abcon#{5=INTERFACE CLEAR} 2006.285.06:31:54.79#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:31:57.13#trakl#Source acquired 2006.285.06:31:59.13#flagr#flagr/antenna,acquired 2006.285.06:32:04.88#abcon#<5=/05 4.8 7.6 24.88 671014.1\r\n> 2006.285.06:32:04.90#abcon#{5=INTERFACE CLEAR} 2006.285.06:32:04.96#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:32:08.12$setupk4/"tpicd 2006.285.06:32:08.12$setupk4/echo=off 2006.285.06:32:08.12$setupk4/xlog=off 2006.285.06:32:08.12:!2006.285.06:32:13 2006.285.06:32:13.00:preob 2006.285.06:32:13.13/onsource/TRACKING 2006.285.06:32:13.13:!2006.285.06:32:23 2006.285.06:32:23.00:"tape 2006.285.06:32:23.00:"st=record 2006.285.06:32:23.00:data_valid=on 2006.285.06:32:23.00:midob 2006.285.06:32:23.13/onsource/TRACKING 2006.285.06:32:23.13/wx/24.87,1014.0,67 2006.285.06:32:23.22/cable/+6.4740E-03 2006.285.06:32:24.31/va/01,07,usb,yes,33,35 2006.285.06:32:24.31/va/02,06,usb,yes,33,33 2006.285.06:32:24.31/va/03,07,usb,yes,32,34 2006.285.06:32:24.31/va/04,06,usb,yes,34,35 2006.285.06:32:24.31/va/05,03,usb,yes,33,34 2006.285.06:32:24.31/va/06,04,usb,yes,30,29 2006.285.06:32:24.31/va/07,04,usb,yes,31,31 2006.285.06:32:24.31/va/08,03,usb,yes,31,38 2006.285.06:32:24.54/valo/01,524.99,yes,locked 2006.285.06:32:24.54/valo/02,534.99,yes,locked 2006.285.06:32:24.54/valo/03,564.99,yes,locked 2006.285.06:32:24.54/valo/04,624.99,yes,locked 2006.285.06:32:24.54/valo/05,734.99,yes,locked 2006.285.06:32:24.54/valo/06,814.99,yes,locked 2006.285.06:32:24.54/valo/07,864.99,yes,locked 2006.285.06:32:24.54/valo/08,884.99,yes,locked 2006.285.06:32:25.63/vb/01,04,usb,yes,31,29 2006.285.06:32:25.63/vb/02,05,usb,yes,29,29 2006.285.06:32:25.63/vb/03,04,usb,yes,30,33 2006.285.06:32:25.63/vb/04,05,usb,yes,31,30 2006.285.06:32:25.63/vb/05,04,usb,yes,27,30 2006.285.06:32:25.63/vb/06,03,usb,yes,39,34 2006.285.06:32:25.63/vb/07,04,usb,yes,31,31 2006.285.06:32:25.63/vb/08,04,usb,yes,29,32 2006.285.06:32:25.86/vblo/01,629.99,yes,locked 2006.285.06:32:25.86/vblo/02,634.99,yes,locked 2006.285.06:32:25.86/vblo/03,649.99,yes,locked 2006.285.06:32:25.86/vblo/04,679.99,yes,locked 2006.285.06:32:25.86/vblo/05,709.99,yes,locked 2006.285.06:32:25.86/vblo/06,719.99,yes,locked 2006.285.06:32:25.86/vblo/07,734.99,yes,locked 2006.285.06:32:25.86/vblo/08,744.99,yes,locked 2006.285.06:32:26.01/vabw/8 2006.285.06:32:26.16/vbbw/8 2006.285.06:32:26.33/xfe/off,on,12.2 2006.285.06:32:26.72/ifatt/23,28,28,28 2006.285.06:32:27.07/fmout-gps/S +2.57E-07 2006.285.06:32:27.09:!2006.285.06:33:23 2006.285.06:33:23.01:data_valid=off 2006.285.06:33:23.01:"et 2006.285.06:33:23.01:!+3s 2006.285.06:33:26.02:"tape 2006.285.06:33:26.02:postob 2006.285.06:33:26.23/cable/+6.4735E-03 2006.285.06:33:26.23/wx/24.86,1014.1,69 2006.285.06:33:26.29/fmout-gps/S +2.58E-07 2006.285.06:33:26.29:scan_name=285-0636,jd0610,40 2006.285.06:33:26.29:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.285.06:33:27.14#flagr#flagr/antenna,new-source 2006.285.06:33:27.14:checkk5 2006.285.06:33:27.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:33:27.93/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:33:28.35/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:33:28.98/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:33:29.36/chk_obsdata//k5ts1/T2850632??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.06:33:29.75/chk_obsdata//k5ts2/T2850632??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.06:33:30.12/chk_obsdata//k5ts3/T2850632??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.06:33:30.52/chk_obsdata//k5ts4/T2850632??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.06:33:31.26/k5log//k5ts1_log_newline 2006.285.06:33:32.20/k5log//k5ts2_log_newline 2006.285.06:33:32.99/k5log//k5ts3_log_newline 2006.285.06:33:33.73/k5log//k5ts4_log_newline 2006.285.06:33:33.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:33:33.75:setupk4=1 2006.285.06:33:33.75$setupk4/echo=on 2006.285.06:33:33.75$setupk4/pcalon 2006.285.06:33:33.75$pcalon/"no phase cal control is implemented here 2006.285.06:33:33.75$setupk4/"tpicd=stop 2006.285.06:33:33.75$setupk4/"rec=synch_on 2006.285.06:33:33.75$setupk4/"rec_mode=128 2006.285.06:33:33.75$setupk4/!* 2006.285.06:33:33.75$setupk4/recpk4 2006.285.06:33:33.75$recpk4/recpatch= 2006.285.06:33:33.75$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:33:33.75$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:33:33.75$setupk4/vck44 2006.285.06:33:33.75$vck44/valo=1,524.99 2006.285.06:33:33.76#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.06:33:33.76#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.06:33:33.76#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:33.76#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:33:33.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:33:33.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:33:33.76#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:33:33.76#ibcon#first serial, iclass 3, count 0 2006.285.06:33:33.76#ibcon#enter sib2, iclass 3, count 0 2006.285.06:33:33.76#ibcon#flushed, iclass 3, count 0 2006.285.06:33:33.76#ibcon#about to write, iclass 3, count 0 2006.285.06:33:33.76#ibcon#wrote, iclass 3, count 0 2006.285.06:33:33.76#ibcon#about to read 3, iclass 3, count 0 2006.285.06:33:33.77#ibcon#read 3, iclass 3, count 0 2006.285.06:33:33.77#ibcon#about to read 4, iclass 3, count 0 2006.285.06:33:33.77#ibcon#read 4, iclass 3, count 0 2006.285.06:33:33.77#ibcon#about to read 5, iclass 3, count 0 2006.285.06:33:33.77#ibcon#read 5, iclass 3, count 0 2006.285.06:33:33.77#ibcon#about to read 6, iclass 3, count 0 2006.285.06:33:33.77#ibcon#read 6, iclass 3, count 0 2006.285.06:33:33.77#ibcon#end of sib2, iclass 3, count 0 2006.285.06:33:33.77#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:33:33.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:33:33.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:33:33.77#ibcon#*before write, iclass 3, count 0 2006.285.06:33:33.77#ibcon#enter sib2, iclass 3, count 0 2006.285.06:33:33.77#ibcon#flushed, iclass 3, count 0 2006.285.06:33:33.77#ibcon#about to write, iclass 3, count 0 2006.285.06:33:33.77#ibcon#wrote, iclass 3, count 0 2006.285.06:33:33.77#ibcon#about to read 3, iclass 3, count 0 2006.285.06:33:33.82#ibcon#read 3, iclass 3, count 0 2006.285.06:33:33.82#ibcon#about to read 4, iclass 3, count 0 2006.285.06:33:33.82#ibcon#read 4, iclass 3, count 0 2006.285.06:33:33.82#ibcon#about to read 5, iclass 3, count 0 2006.285.06:33:33.82#ibcon#read 5, iclass 3, count 0 2006.285.06:33:33.82#ibcon#about to read 6, iclass 3, count 0 2006.285.06:33:33.82#ibcon#read 6, iclass 3, count 0 2006.285.06:33:33.82#ibcon#end of sib2, iclass 3, count 0 2006.285.06:33:33.82#ibcon#*after write, iclass 3, count 0 2006.285.06:33:33.82#ibcon#*before return 0, iclass 3, count 0 2006.285.06:33:33.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:33:33.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:33:33.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:33:33.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:33:33.82$vck44/va=1,7 2006.285.06:33:33.82#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.06:33:33.82#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.06:33:33.82#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:33.82#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:33:33.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:33:33.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:33:33.82#ibcon#enter wrdev, iclass 5, count 2 2006.285.06:33:33.82#ibcon#first serial, iclass 5, count 2 2006.285.06:33:33.82#ibcon#enter sib2, iclass 5, count 2 2006.285.06:33:33.82#ibcon#flushed, iclass 5, count 2 2006.285.06:33:33.82#ibcon#about to write, iclass 5, count 2 2006.285.06:33:33.82#ibcon#wrote, iclass 5, count 2 2006.285.06:33:33.82#ibcon#about to read 3, iclass 5, count 2 2006.285.06:33:33.84#ibcon#read 3, iclass 5, count 2 2006.285.06:33:33.84#ibcon#about to read 4, iclass 5, count 2 2006.285.06:33:33.84#ibcon#read 4, iclass 5, count 2 2006.285.06:33:33.84#ibcon#about to read 5, iclass 5, count 2 2006.285.06:33:33.84#ibcon#read 5, iclass 5, count 2 2006.285.06:33:33.84#ibcon#about to read 6, iclass 5, count 2 2006.285.06:33:33.84#ibcon#read 6, iclass 5, count 2 2006.285.06:33:33.84#ibcon#end of sib2, iclass 5, count 2 2006.285.06:33:33.84#ibcon#*mode == 0, iclass 5, count 2 2006.285.06:33:33.84#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.06:33:33.84#ibcon#[25=AT01-07\r\n] 2006.285.06:33:33.84#ibcon#*before write, iclass 5, count 2 2006.285.06:33:33.84#ibcon#enter sib2, iclass 5, count 2 2006.285.06:33:33.84#ibcon#flushed, iclass 5, count 2 2006.285.06:33:33.84#ibcon#about to write, iclass 5, count 2 2006.285.06:33:33.84#ibcon#wrote, iclass 5, count 2 2006.285.06:33:33.84#ibcon#about to read 3, iclass 5, count 2 2006.285.06:33:33.87#ibcon#read 3, iclass 5, count 2 2006.285.06:33:33.87#ibcon#about to read 4, iclass 5, count 2 2006.285.06:33:33.87#ibcon#read 4, iclass 5, count 2 2006.285.06:33:33.87#ibcon#about to read 5, iclass 5, count 2 2006.285.06:33:33.87#ibcon#read 5, iclass 5, count 2 2006.285.06:33:33.87#ibcon#about to read 6, iclass 5, count 2 2006.285.06:33:33.87#ibcon#read 6, iclass 5, count 2 2006.285.06:33:33.87#ibcon#end of sib2, iclass 5, count 2 2006.285.06:33:33.87#ibcon#*after write, iclass 5, count 2 2006.285.06:33:33.87#ibcon#*before return 0, iclass 5, count 2 2006.285.06:33:33.87#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:33:33.87#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:33:33.87#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.06:33:33.87#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:33.87#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:33:33.99#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:33:33.99#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:33:33.99#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:33:33.99#ibcon#first serial, iclass 5, count 0 2006.285.06:33:33.99#ibcon#enter sib2, iclass 5, count 0 2006.285.06:33:33.99#ibcon#flushed, iclass 5, count 0 2006.285.06:33:33.99#ibcon#about to write, iclass 5, count 0 2006.285.06:33:33.99#ibcon#wrote, iclass 5, count 0 2006.285.06:33:33.99#ibcon#about to read 3, iclass 5, count 0 2006.285.06:33:34.01#ibcon#read 3, iclass 5, count 0 2006.285.06:33:34.01#ibcon#about to read 4, iclass 5, count 0 2006.285.06:33:34.01#ibcon#read 4, iclass 5, count 0 2006.285.06:33:34.01#ibcon#about to read 5, iclass 5, count 0 2006.285.06:33:34.01#ibcon#read 5, iclass 5, count 0 2006.285.06:33:34.01#ibcon#about to read 6, iclass 5, count 0 2006.285.06:33:34.01#ibcon#read 6, iclass 5, count 0 2006.285.06:33:34.01#ibcon#end of sib2, iclass 5, count 0 2006.285.06:33:34.01#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:33:34.01#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:33:34.01#ibcon#[25=USB\r\n] 2006.285.06:33:34.01#ibcon#*before write, iclass 5, count 0 2006.285.06:33:34.01#ibcon#enter sib2, iclass 5, count 0 2006.285.06:33:34.01#ibcon#flushed, iclass 5, count 0 2006.285.06:33:34.01#ibcon#about to write, iclass 5, count 0 2006.285.06:33:34.01#ibcon#wrote, iclass 5, count 0 2006.285.06:33:34.01#ibcon#about to read 3, iclass 5, count 0 2006.285.06:33:34.04#ibcon#read 3, iclass 5, count 0 2006.285.06:33:34.04#ibcon#about to read 4, iclass 5, count 0 2006.285.06:33:34.04#ibcon#read 4, iclass 5, count 0 2006.285.06:33:34.04#ibcon#about to read 5, iclass 5, count 0 2006.285.06:33:34.04#ibcon#read 5, iclass 5, count 0 2006.285.06:33:34.04#ibcon#about to read 6, iclass 5, count 0 2006.285.06:33:34.04#ibcon#read 6, iclass 5, count 0 2006.285.06:33:34.04#ibcon#end of sib2, iclass 5, count 0 2006.285.06:33:34.04#ibcon#*after write, iclass 5, count 0 2006.285.06:33:34.04#ibcon#*before return 0, iclass 5, count 0 2006.285.06:33:34.04#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:33:34.04#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:33:34.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:33:34.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:33:34.04$vck44/valo=2,534.99 2006.285.06:33:34.04#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.06:33:34.04#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.06:33:34.04#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:34.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:33:34.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:33:34.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:33:34.04#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:33:34.04#ibcon#first serial, iclass 7, count 0 2006.285.06:33:34.04#ibcon#enter sib2, iclass 7, count 0 2006.285.06:33:34.04#ibcon#flushed, iclass 7, count 0 2006.285.06:33:34.04#ibcon#about to write, iclass 7, count 0 2006.285.06:33:34.04#ibcon#wrote, iclass 7, count 0 2006.285.06:33:34.04#ibcon#about to read 3, iclass 7, count 0 2006.285.06:33:34.06#ibcon#read 3, iclass 7, count 0 2006.285.06:33:34.06#ibcon#about to read 4, iclass 7, count 0 2006.285.06:33:34.06#ibcon#read 4, iclass 7, count 0 2006.285.06:33:34.06#ibcon#about to read 5, iclass 7, count 0 2006.285.06:33:34.06#ibcon#read 5, iclass 7, count 0 2006.285.06:33:34.06#ibcon#about to read 6, iclass 7, count 0 2006.285.06:33:34.06#ibcon#read 6, iclass 7, count 0 2006.285.06:33:34.06#ibcon#end of sib2, iclass 7, count 0 2006.285.06:33:34.06#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:33:34.06#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:33:34.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:33:34.06#ibcon#*before write, iclass 7, count 0 2006.285.06:33:34.06#ibcon#enter sib2, iclass 7, count 0 2006.285.06:33:34.06#ibcon#flushed, iclass 7, count 0 2006.285.06:33:34.06#ibcon#about to write, iclass 7, count 0 2006.285.06:33:34.06#ibcon#wrote, iclass 7, count 0 2006.285.06:33:34.06#ibcon#about to read 3, iclass 7, count 0 2006.285.06:33:34.10#ibcon#read 3, iclass 7, count 0 2006.285.06:33:34.10#ibcon#about to read 4, iclass 7, count 0 2006.285.06:33:34.10#ibcon#read 4, iclass 7, count 0 2006.285.06:33:34.10#ibcon#about to read 5, iclass 7, count 0 2006.285.06:33:34.10#ibcon#read 5, iclass 7, count 0 2006.285.06:33:34.10#ibcon#about to read 6, iclass 7, count 0 2006.285.06:33:34.10#ibcon#read 6, iclass 7, count 0 2006.285.06:33:34.10#ibcon#end of sib2, iclass 7, count 0 2006.285.06:33:34.10#ibcon#*after write, iclass 7, count 0 2006.285.06:33:34.10#ibcon#*before return 0, iclass 7, count 0 2006.285.06:33:34.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:33:34.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:33:34.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:33:34.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:33:34.10$vck44/va=2,6 2006.285.06:33:34.10#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.06:33:34.10#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.06:33:34.10#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:34.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:33:34.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:33:34.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:33:34.16#ibcon#enter wrdev, iclass 11, count 2 2006.285.06:33:34.16#ibcon#first serial, iclass 11, count 2 2006.285.06:33:34.16#ibcon#enter sib2, iclass 11, count 2 2006.285.06:33:34.16#ibcon#flushed, iclass 11, count 2 2006.285.06:33:34.16#ibcon#about to write, iclass 11, count 2 2006.285.06:33:34.16#ibcon#wrote, iclass 11, count 2 2006.285.06:33:34.16#ibcon#about to read 3, iclass 11, count 2 2006.285.06:33:34.18#ibcon#read 3, iclass 11, count 2 2006.285.06:33:34.18#ibcon#about to read 4, iclass 11, count 2 2006.285.06:33:34.18#ibcon#read 4, iclass 11, count 2 2006.285.06:33:34.18#ibcon#about to read 5, iclass 11, count 2 2006.285.06:33:34.18#ibcon#read 5, iclass 11, count 2 2006.285.06:33:34.18#ibcon#about to read 6, iclass 11, count 2 2006.285.06:33:34.18#ibcon#read 6, iclass 11, count 2 2006.285.06:33:34.18#ibcon#end of sib2, iclass 11, count 2 2006.285.06:33:34.18#ibcon#*mode == 0, iclass 11, count 2 2006.285.06:33:34.18#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.06:33:34.18#ibcon#[25=AT02-06\r\n] 2006.285.06:33:34.18#ibcon#*before write, iclass 11, count 2 2006.285.06:33:34.18#ibcon#enter sib2, iclass 11, count 2 2006.285.06:33:34.18#ibcon#flushed, iclass 11, count 2 2006.285.06:33:34.18#ibcon#about to write, iclass 11, count 2 2006.285.06:33:34.18#ibcon#wrote, iclass 11, count 2 2006.285.06:33:34.18#ibcon#about to read 3, iclass 11, count 2 2006.285.06:33:34.21#ibcon#read 3, iclass 11, count 2 2006.285.06:33:34.21#ibcon#about to read 4, iclass 11, count 2 2006.285.06:33:34.21#ibcon#read 4, iclass 11, count 2 2006.285.06:33:34.21#ibcon#about to read 5, iclass 11, count 2 2006.285.06:33:34.21#ibcon#read 5, iclass 11, count 2 2006.285.06:33:34.21#ibcon#about to read 6, iclass 11, count 2 2006.285.06:33:34.21#ibcon#read 6, iclass 11, count 2 2006.285.06:33:34.21#ibcon#end of sib2, iclass 11, count 2 2006.285.06:33:34.21#ibcon#*after write, iclass 11, count 2 2006.285.06:33:34.21#ibcon#*before return 0, iclass 11, count 2 2006.285.06:33:34.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:33:34.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:33:34.21#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.06:33:34.21#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:34.21#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:33:34.33#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:33:34.33#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:33:34.33#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:33:34.33#ibcon#first serial, iclass 11, count 0 2006.285.06:33:34.33#ibcon#enter sib2, iclass 11, count 0 2006.285.06:33:34.33#ibcon#flushed, iclass 11, count 0 2006.285.06:33:34.33#ibcon#about to write, iclass 11, count 0 2006.285.06:33:34.33#ibcon#wrote, iclass 11, count 0 2006.285.06:33:34.33#ibcon#about to read 3, iclass 11, count 0 2006.285.06:33:34.35#ibcon#read 3, iclass 11, count 0 2006.285.06:33:34.35#ibcon#about to read 4, iclass 11, count 0 2006.285.06:33:34.35#ibcon#read 4, iclass 11, count 0 2006.285.06:33:34.35#ibcon#about to read 5, iclass 11, count 0 2006.285.06:33:34.35#ibcon#read 5, iclass 11, count 0 2006.285.06:33:34.35#ibcon#about to read 6, iclass 11, count 0 2006.285.06:33:34.35#ibcon#read 6, iclass 11, count 0 2006.285.06:33:34.35#ibcon#end of sib2, iclass 11, count 0 2006.285.06:33:34.35#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:33:34.35#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:33:34.35#ibcon#[25=USB\r\n] 2006.285.06:33:34.35#ibcon#*before write, iclass 11, count 0 2006.285.06:33:34.35#ibcon#enter sib2, iclass 11, count 0 2006.285.06:33:34.35#ibcon#flushed, iclass 11, count 0 2006.285.06:33:34.35#ibcon#about to write, iclass 11, count 0 2006.285.06:33:34.35#ibcon#wrote, iclass 11, count 0 2006.285.06:33:34.35#ibcon#about to read 3, iclass 11, count 0 2006.285.06:33:34.38#ibcon#read 3, iclass 11, count 0 2006.285.06:33:34.38#ibcon#about to read 4, iclass 11, count 0 2006.285.06:33:34.38#ibcon#read 4, iclass 11, count 0 2006.285.06:33:34.38#ibcon#about to read 5, iclass 11, count 0 2006.285.06:33:34.38#ibcon#read 5, iclass 11, count 0 2006.285.06:33:34.38#ibcon#about to read 6, iclass 11, count 0 2006.285.06:33:34.38#ibcon#read 6, iclass 11, count 0 2006.285.06:33:34.38#ibcon#end of sib2, iclass 11, count 0 2006.285.06:33:34.38#ibcon#*after write, iclass 11, count 0 2006.285.06:33:34.38#ibcon#*before return 0, iclass 11, count 0 2006.285.06:33:34.38#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:33:34.38#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:33:34.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:33:34.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:33:34.38$vck44/valo=3,564.99 2006.285.06:33:34.38#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.06:33:34.38#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.06:33:34.38#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:34.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:33:34.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:33:34.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:33:34.38#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:33:34.38#ibcon#first serial, iclass 13, count 0 2006.285.06:33:34.38#ibcon#enter sib2, iclass 13, count 0 2006.285.06:33:34.38#ibcon#flushed, iclass 13, count 0 2006.285.06:33:34.38#ibcon#about to write, iclass 13, count 0 2006.285.06:33:34.38#ibcon#wrote, iclass 13, count 0 2006.285.06:33:34.38#ibcon#about to read 3, iclass 13, count 0 2006.285.06:33:34.40#ibcon#read 3, iclass 13, count 0 2006.285.06:33:34.40#ibcon#about to read 4, iclass 13, count 0 2006.285.06:33:34.40#ibcon#read 4, iclass 13, count 0 2006.285.06:33:34.40#ibcon#about to read 5, iclass 13, count 0 2006.285.06:33:34.40#ibcon#read 5, iclass 13, count 0 2006.285.06:33:34.40#ibcon#about to read 6, iclass 13, count 0 2006.285.06:33:34.40#ibcon#read 6, iclass 13, count 0 2006.285.06:33:34.40#ibcon#end of sib2, iclass 13, count 0 2006.285.06:33:34.40#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:33:34.40#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:33:34.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:33:34.40#ibcon#*before write, iclass 13, count 0 2006.285.06:33:34.40#ibcon#enter sib2, iclass 13, count 0 2006.285.06:33:34.40#ibcon#flushed, iclass 13, count 0 2006.285.06:33:34.40#ibcon#about to write, iclass 13, count 0 2006.285.06:33:34.40#ibcon#wrote, iclass 13, count 0 2006.285.06:33:34.40#ibcon#about to read 3, iclass 13, count 0 2006.285.06:33:34.44#ibcon#read 3, iclass 13, count 0 2006.285.06:33:34.44#ibcon#about to read 4, iclass 13, count 0 2006.285.06:33:34.44#ibcon#read 4, iclass 13, count 0 2006.285.06:33:34.44#ibcon#about to read 5, iclass 13, count 0 2006.285.06:33:34.44#ibcon#read 5, iclass 13, count 0 2006.285.06:33:34.44#ibcon#about to read 6, iclass 13, count 0 2006.285.06:33:34.44#ibcon#read 6, iclass 13, count 0 2006.285.06:33:34.44#ibcon#end of sib2, iclass 13, count 0 2006.285.06:33:34.44#ibcon#*after write, iclass 13, count 0 2006.285.06:33:34.44#ibcon#*before return 0, iclass 13, count 0 2006.285.06:33:34.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:33:34.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:33:34.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:33:34.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:33:34.44$vck44/va=3,7 2006.285.06:33:34.44#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.06:33:34.44#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.06:33:34.44#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:34.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:33:34.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:33:34.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:33:34.50#ibcon#enter wrdev, iclass 15, count 2 2006.285.06:33:34.50#ibcon#first serial, iclass 15, count 2 2006.285.06:33:34.50#ibcon#enter sib2, iclass 15, count 2 2006.285.06:33:34.50#ibcon#flushed, iclass 15, count 2 2006.285.06:33:34.50#ibcon#about to write, iclass 15, count 2 2006.285.06:33:34.50#ibcon#wrote, iclass 15, count 2 2006.285.06:33:34.50#ibcon#about to read 3, iclass 15, count 2 2006.285.06:33:34.52#ibcon#read 3, iclass 15, count 2 2006.285.06:33:34.52#ibcon#about to read 4, iclass 15, count 2 2006.285.06:33:34.52#ibcon#read 4, iclass 15, count 2 2006.285.06:33:34.52#ibcon#about to read 5, iclass 15, count 2 2006.285.06:33:34.52#ibcon#read 5, iclass 15, count 2 2006.285.06:33:34.52#ibcon#about to read 6, iclass 15, count 2 2006.285.06:33:34.52#ibcon#read 6, iclass 15, count 2 2006.285.06:33:34.52#ibcon#end of sib2, iclass 15, count 2 2006.285.06:33:34.52#ibcon#*mode == 0, iclass 15, count 2 2006.285.06:33:34.52#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.06:33:34.52#ibcon#[25=AT03-07\r\n] 2006.285.06:33:34.52#ibcon#*before write, iclass 15, count 2 2006.285.06:33:34.52#ibcon#enter sib2, iclass 15, count 2 2006.285.06:33:34.52#ibcon#flushed, iclass 15, count 2 2006.285.06:33:34.52#ibcon#about to write, iclass 15, count 2 2006.285.06:33:34.52#ibcon#wrote, iclass 15, count 2 2006.285.06:33:34.52#ibcon#about to read 3, iclass 15, count 2 2006.285.06:33:34.55#ibcon#read 3, iclass 15, count 2 2006.285.06:33:34.55#ibcon#about to read 4, iclass 15, count 2 2006.285.06:33:34.55#ibcon#read 4, iclass 15, count 2 2006.285.06:33:34.55#ibcon#about to read 5, iclass 15, count 2 2006.285.06:33:34.55#ibcon#read 5, iclass 15, count 2 2006.285.06:33:34.55#ibcon#about to read 6, iclass 15, count 2 2006.285.06:33:34.55#ibcon#read 6, iclass 15, count 2 2006.285.06:33:34.55#ibcon#end of sib2, iclass 15, count 2 2006.285.06:33:34.55#ibcon#*after write, iclass 15, count 2 2006.285.06:33:34.55#ibcon#*before return 0, iclass 15, count 2 2006.285.06:33:34.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:33:34.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:33:34.55#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.06:33:34.55#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:34.55#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:33:34.67#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:33:34.67#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:33:34.67#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:33:34.67#ibcon#first serial, iclass 15, count 0 2006.285.06:33:34.67#ibcon#enter sib2, iclass 15, count 0 2006.285.06:33:34.67#ibcon#flushed, iclass 15, count 0 2006.285.06:33:34.67#ibcon#about to write, iclass 15, count 0 2006.285.06:33:34.67#ibcon#wrote, iclass 15, count 0 2006.285.06:33:34.67#ibcon#about to read 3, iclass 15, count 0 2006.285.06:33:34.69#ibcon#read 3, iclass 15, count 0 2006.285.06:33:34.69#ibcon#about to read 4, iclass 15, count 0 2006.285.06:33:34.69#ibcon#read 4, iclass 15, count 0 2006.285.06:33:34.69#ibcon#about to read 5, iclass 15, count 0 2006.285.06:33:34.69#ibcon#read 5, iclass 15, count 0 2006.285.06:33:34.69#ibcon#about to read 6, iclass 15, count 0 2006.285.06:33:34.69#ibcon#read 6, iclass 15, count 0 2006.285.06:33:34.69#ibcon#end of sib2, iclass 15, count 0 2006.285.06:33:34.69#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:33:34.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:33:34.69#ibcon#[25=USB\r\n] 2006.285.06:33:34.69#ibcon#*before write, iclass 15, count 0 2006.285.06:33:34.69#ibcon#enter sib2, iclass 15, count 0 2006.285.06:33:34.69#ibcon#flushed, iclass 15, count 0 2006.285.06:33:34.69#ibcon#about to write, iclass 15, count 0 2006.285.06:33:34.69#ibcon#wrote, iclass 15, count 0 2006.285.06:33:34.69#ibcon#about to read 3, iclass 15, count 0 2006.285.06:33:34.72#ibcon#read 3, iclass 15, count 0 2006.285.06:33:34.72#ibcon#about to read 4, iclass 15, count 0 2006.285.06:33:34.72#ibcon#read 4, iclass 15, count 0 2006.285.06:33:34.72#ibcon#about to read 5, iclass 15, count 0 2006.285.06:33:34.72#ibcon#read 5, iclass 15, count 0 2006.285.06:33:34.72#ibcon#about to read 6, iclass 15, count 0 2006.285.06:33:34.72#ibcon#read 6, iclass 15, count 0 2006.285.06:33:34.72#ibcon#end of sib2, iclass 15, count 0 2006.285.06:33:34.72#ibcon#*after write, iclass 15, count 0 2006.285.06:33:34.72#ibcon#*before return 0, iclass 15, count 0 2006.285.06:33:34.72#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:33:34.72#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:33:34.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:33:34.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:33:34.72$vck44/valo=4,624.99 2006.285.06:33:34.72#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.06:33:34.72#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.06:33:34.72#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:34.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:33:34.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:33:34.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:33:34.72#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:33:34.72#ibcon#first serial, iclass 17, count 0 2006.285.06:33:34.72#ibcon#enter sib2, iclass 17, count 0 2006.285.06:33:34.72#ibcon#flushed, iclass 17, count 0 2006.285.06:33:34.72#ibcon#about to write, iclass 17, count 0 2006.285.06:33:34.72#ibcon#wrote, iclass 17, count 0 2006.285.06:33:34.72#ibcon#about to read 3, iclass 17, count 0 2006.285.06:33:34.74#ibcon#read 3, iclass 17, count 0 2006.285.06:33:34.74#ibcon#about to read 4, iclass 17, count 0 2006.285.06:33:34.74#ibcon#read 4, iclass 17, count 0 2006.285.06:33:34.74#ibcon#about to read 5, iclass 17, count 0 2006.285.06:33:34.74#ibcon#read 5, iclass 17, count 0 2006.285.06:33:34.74#ibcon#about to read 6, iclass 17, count 0 2006.285.06:33:34.74#ibcon#read 6, iclass 17, count 0 2006.285.06:33:34.74#ibcon#end of sib2, iclass 17, count 0 2006.285.06:33:34.74#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:33:34.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:33:34.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:33:34.74#ibcon#*before write, iclass 17, count 0 2006.285.06:33:34.74#ibcon#enter sib2, iclass 17, count 0 2006.285.06:33:34.74#ibcon#flushed, iclass 17, count 0 2006.285.06:33:34.74#ibcon#about to write, iclass 17, count 0 2006.285.06:33:34.74#ibcon#wrote, iclass 17, count 0 2006.285.06:33:34.74#ibcon#about to read 3, iclass 17, count 0 2006.285.06:33:34.78#ibcon#read 3, iclass 17, count 0 2006.285.06:33:34.78#ibcon#about to read 4, iclass 17, count 0 2006.285.06:33:34.78#ibcon#read 4, iclass 17, count 0 2006.285.06:33:34.78#ibcon#about to read 5, iclass 17, count 0 2006.285.06:33:34.78#ibcon#read 5, iclass 17, count 0 2006.285.06:33:34.78#ibcon#about to read 6, iclass 17, count 0 2006.285.06:33:34.78#ibcon#read 6, iclass 17, count 0 2006.285.06:33:34.78#ibcon#end of sib2, iclass 17, count 0 2006.285.06:33:34.78#ibcon#*after write, iclass 17, count 0 2006.285.06:33:34.78#ibcon#*before return 0, iclass 17, count 0 2006.285.06:33:34.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:33:34.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:33:34.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:33:34.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:33:34.78$vck44/va=4,6 2006.285.06:33:34.78#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.06:33:34.78#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.06:33:34.78#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:34.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:33:34.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:33:34.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:33:34.84#ibcon#enter wrdev, iclass 19, count 2 2006.285.06:33:34.84#ibcon#first serial, iclass 19, count 2 2006.285.06:33:34.84#ibcon#enter sib2, iclass 19, count 2 2006.285.06:33:34.84#ibcon#flushed, iclass 19, count 2 2006.285.06:33:34.84#ibcon#about to write, iclass 19, count 2 2006.285.06:33:34.84#ibcon#wrote, iclass 19, count 2 2006.285.06:33:34.84#ibcon#about to read 3, iclass 19, count 2 2006.285.06:33:34.86#ibcon#read 3, iclass 19, count 2 2006.285.06:33:34.86#ibcon#about to read 4, iclass 19, count 2 2006.285.06:33:34.86#ibcon#read 4, iclass 19, count 2 2006.285.06:33:34.86#ibcon#about to read 5, iclass 19, count 2 2006.285.06:33:34.86#ibcon#read 5, iclass 19, count 2 2006.285.06:33:34.86#ibcon#about to read 6, iclass 19, count 2 2006.285.06:33:34.86#ibcon#read 6, iclass 19, count 2 2006.285.06:33:34.86#ibcon#end of sib2, iclass 19, count 2 2006.285.06:33:34.86#ibcon#*mode == 0, iclass 19, count 2 2006.285.06:33:34.86#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.06:33:34.86#ibcon#[25=AT04-06\r\n] 2006.285.06:33:34.86#ibcon#*before write, iclass 19, count 2 2006.285.06:33:34.86#ibcon#enter sib2, iclass 19, count 2 2006.285.06:33:34.86#ibcon#flushed, iclass 19, count 2 2006.285.06:33:34.86#ibcon#about to write, iclass 19, count 2 2006.285.06:33:34.86#ibcon#wrote, iclass 19, count 2 2006.285.06:33:34.86#ibcon#about to read 3, iclass 19, count 2 2006.285.06:33:34.89#ibcon#read 3, iclass 19, count 2 2006.285.06:33:34.89#ibcon#about to read 4, iclass 19, count 2 2006.285.06:33:34.89#ibcon#read 4, iclass 19, count 2 2006.285.06:33:34.89#ibcon#about to read 5, iclass 19, count 2 2006.285.06:33:34.89#ibcon#read 5, iclass 19, count 2 2006.285.06:33:34.89#ibcon#about to read 6, iclass 19, count 2 2006.285.06:33:34.89#ibcon#read 6, iclass 19, count 2 2006.285.06:33:34.89#ibcon#end of sib2, iclass 19, count 2 2006.285.06:33:34.89#ibcon#*after write, iclass 19, count 2 2006.285.06:33:34.89#ibcon#*before return 0, iclass 19, count 2 2006.285.06:33:34.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:33:34.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:33:34.89#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.06:33:34.89#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:34.89#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:33:35.01#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:33:35.01#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:33:35.01#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:33:35.01#ibcon#first serial, iclass 19, count 0 2006.285.06:33:35.01#ibcon#enter sib2, iclass 19, count 0 2006.285.06:33:35.01#ibcon#flushed, iclass 19, count 0 2006.285.06:33:35.01#ibcon#about to write, iclass 19, count 0 2006.285.06:33:35.01#ibcon#wrote, iclass 19, count 0 2006.285.06:33:35.01#ibcon#about to read 3, iclass 19, count 0 2006.285.06:33:35.03#ibcon#read 3, iclass 19, count 0 2006.285.06:33:35.03#ibcon#about to read 4, iclass 19, count 0 2006.285.06:33:35.03#ibcon#read 4, iclass 19, count 0 2006.285.06:33:35.03#ibcon#about to read 5, iclass 19, count 0 2006.285.06:33:35.03#ibcon#read 5, iclass 19, count 0 2006.285.06:33:35.03#ibcon#about to read 6, iclass 19, count 0 2006.285.06:33:35.03#ibcon#read 6, iclass 19, count 0 2006.285.06:33:35.03#ibcon#end of sib2, iclass 19, count 0 2006.285.06:33:35.03#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:33:35.03#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:33:35.03#ibcon#[25=USB\r\n] 2006.285.06:33:35.03#ibcon#*before write, iclass 19, count 0 2006.285.06:33:35.03#ibcon#enter sib2, iclass 19, count 0 2006.285.06:33:35.03#ibcon#flushed, iclass 19, count 0 2006.285.06:33:35.03#ibcon#about to write, iclass 19, count 0 2006.285.06:33:35.03#ibcon#wrote, iclass 19, count 0 2006.285.06:33:35.03#ibcon#about to read 3, iclass 19, count 0 2006.285.06:33:35.06#ibcon#read 3, iclass 19, count 0 2006.285.06:33:35.06#ibcon#about to read 4, iclass 19, count 0 2006.285.06:33:35.06#ibcon#read 4, iclass 19, count 0 2006.285.06:33:35.06#ibcon#about to read 5, iclass 19, count 0 2006.285.06:33:35.06#ibcon#read 5, iclass 19, count 0 2006.285.06:33:35.06#ibcon#about to read 6, iclass 19, count 0 2006.285.06:33:35.06#ibcon#read 6, iclass 19, count 0 2006.285.06:33:35.06#ibcon#end of sib2, iclass 19, count 0 2006.285.06:33:35.06#ibcon#*after write, iclass 19, count 0 2006.285.06:33:35.06#ibcon#*before return 0, iclass 19, count 0 2006.285.06:33:35.06#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:33:35.06#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:33:35.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:33:35.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:33:35.06$vck44/valo=5,734.99 2006.285.06:33:35.06#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.06:33:35.06#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.06:33:35.06#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:35.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:33:35.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:33:35.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:33:35.06#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:33:35.06#ibcon#first serial, iclass 21, count 0 2006.285.06:33:35.06#ibcon#enter sib2, iclass 21, count 0 2006.285.06:33:35.06#ibcon#flushed, iclass 21, count 0 2006.285.06:33:35.06#ibcon#about to write, iclass 21, count 0 2006.285.06:33:35.06#ibcon#wrote, iclass 21, count 0 2006.285.06:33:35.06#ibcon#about to read 3, iclass 21, count 0 2006.285.06:33:35.08#ibcon#read 3, iclass 21, count 0 2006.285.06:33:35.08#ibcon#about to read 4, iclass 21, count 0 2006.285.06:33:35.08#ibcon#read 4, iclass 21, count 0 2006.285.06:33:35.08#ibcon#about to read 5, iclass 21, count 0 2006.285.06:33:35.08#ibcon#read 5, iclass 21, count 0 2006.285.06:33:35.08#ibcon#about to read 6, iclass 21, count 0 2006.285.06:33:35.08#ibcon#read 6, iclass 21, count 0 2006.285.06:33:35.08#ibcon#end of sib2, iclass 21, count 0 2006.285.06:33:35.08#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:33:35.08#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:33:35.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:33:35.08#ibcon#*before write, iclass 21, count 0 2006.285.06:33:35.08#ibcon#enter sib2, iclass 21, count 0 2006.285.06:33:35.08#ibcon#flushed, iclass 21, count 0 2006.285.06:33:35.08#ibcon#about to write, iclass 21, count 0 2006.285.06:33:35.08#ibcon#wrote, iclass 21, count 0 2006.285.06:33:35.08#ibcon#about to read 3, iclass 21, count 0 2006.285.06:33:35.12#ibcon#read 3, iclass 21, count 0 2006.285.06:33:35.12#ibcon#about to read 4, iclass 21, count 0 2006.285.06:33:35.12#ibcon#read 4, iclass 21, count 0 2006.285.06:33:35.12#ibcon#about to read 5, iclass 21, count 0 2006.285.06:33:35.12#ibcon#read 5, iclass 21, count 0 2006.285.06:33:35.12#ibcon#about to read 6, iclass 21, count 0 2006.285.06:33:35.12#ibcon#read 6, iclass 21, count 0 2006.285.06:33:35.12#ibcon#end of sib2, iclass 21, count 0 2006.285.06:33:35.12#ibcon#*after write, iclass 21, count 0 2006.285.06:33:35.12#ibcon#*before return 0, iclass 21, count 0 2006.285.06:33:35.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:33:35.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:33:35.12#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:33:35.12#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:33:35.12$vck44/va=5,3 2006.285.06:33:35.12#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.06:33:35.12#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.06:33:35.12#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:35.12#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:33:35.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:33:35.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:33:35.18#ibcon#enter wrdev, iclass 23, count 2 2006.285.06:33:35.18#ibcon#first serial, iclass 23, count 2 2006.285.06:33:35.18#ibcon#enter sib2, iclass 23, count 2 2006.285.06:33:35.18#ibcon#flushed, iclass 23, count 2 2006.285.06:33:35.18#ibcon#about to write, iclass 23, count 2 2006.285.06:33:35.18#ibcon#wrote, iclass 23, count 2 2006.285.06:33:35.18#ibcon#about to read 3, iclass 23, count 2 2006.285.06:33:35.20#ibcon#read 3, iclass 23, count 2 2006.285.06:33:35.20#ibcon#about to read 4, iclass 23, count 2 2006.285.06:33:35.20#ibcon#read 4, iclass 23, count 2 2006.285.06:33:35.20#ibcon#about to read 5, iclass 23, count 2 2006.285.06:33:35.20#ibcon#read 5, iclass 23, count 2 2006.285.06:33:35.20#ibcon#about to read 6, iclass 23, count 2 2006.285.06:33:35.20#ibcon#read 6, iclass 23, count 2 2006.285.06:33:35.20#ibcon#end of sib2, iclass 23, count 2 2006.285.06:33:35.20#ibcon#*mode == 0, iclass 23, count 2 2006.285.06:33:35.20#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.06:33:35.20#ibcon#[25=AT05-03\r\n] 2006.285.06:33:35.20#ibcon#*before write, iclass 23, count 2 2006.285.06:33:35.20#ibcon#enter sib2, iclass 23, count 2 2006.285.06:33:35.20#ibcon#flushed, iclass 23, count 2 2006.285.06:33:35.20#ibcon#about to write, iclass 23, count 2 2006.285.06:33:35.20#ibcon#wrote, iclass 23, count 2 2006.285.06:33:35.20#ibcon#about to read 3, iclass 23, count 2 2006.285.06:33:35.23#ibcon#read 3, iclass 23, count 2 2006.285.06:33:35.23#ibcon#about to read 4, iclass 23, count 2 2006.285.06:33:35.23#ibcon#read 4, iclass 23, count 2 2006.285.06:33:35.23#ibcon#about to read 5, iclass 23, count 2 2006.285.06:33:35.23#ibcon#read 5, iclass 23, count 2 2006.285.06:33:35.23#ibcon#about to read 6, iclass 23, count 2 2006.285.06:33:35.23#ibcon#read 6, iclass 23, count 2 2006.285.06:33:35.23#ibcon#end of sib2, iclass 23, count 2 2006.285.06:33:35.23#ibcon#*after write, iclass 23, count 2 2006.285.06:33:35.23#ibcon#*before return 0, iclass 23, count 2 2006.285.06:33:35.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:33:35.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:33:35.23#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.06:33:35.23#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:35.23#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:33:35.35#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:33:35.35#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:33:35.35#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:33:35.35#ibcon#first serial, iclass 23, count 0 2006.285.06:33:35.35#ibcon#enter sib2, iclass 23, count 0 2006.285.06:33:35.35#ibcon#flushed, iclass 23, count 0 2006.285.06:33:35.35#ibcon#about to write, iclass 23, count 0 2006.285.06:33:35.35#ibcon#wrote, iclass 23, count 0 2006.285.06:33:35.35#ibcon#about to read 3, iclass 23, count 0 2006.285.06:33:35.37#ibcon#read 3, iclass 23, count 0 2006.285.06:33:35.37#ibcon#about to read 4, iclass 23, count 0 2006.285.06:33:35.37#ibcon#read 4, iclass 23, count 0 2006.285.06:33:35.37#ibcon#about to read 5, iclass 23, count 0 2006.285.06:33:35.37#ibcon#read 5, iclass 23, count 0 2006.285.06:33:35.37#ibcon#about to read 6, iclass 23, count 0 2006.285.06:33:35.37#ibcon#read 6, iclass 23, count 0 2006.285.06:33:35.37#ibcon#end of sib2, iclass 23, count 0 2006.285.06:33:35.37#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:33:35.37#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:33:35.37#ibcon#[25=USB\r\n] 2006.285.06:33:35.37#ibcon#*before write, iclass 23, count 0 2006.285.06:33:35.37#ibcon#enter sib2, iclass 23, count 0 2006.285.06:33:35.37#ibcon#flushed, iclass 23, count 0 2006.285.06:33:35.37#ibcon#about to write, iclass 23, count 0 2006.285.06:33:35.37#ibcon#wrote, iclass 23, count 0 2006.285.06:33:35.37#ibcon#about to read 3, iclass 23, count 0 2006.285.06:33:35.40#ibcon#read 3, iclass 23, count 0 2006.285.06:33:35.40#ibcon#about to read 4, iclass 23, count 0 2006.285.06:33:35.40#ibcon#read 4, iclass 23, count 0 2006.285.06:33:35.40#ibcon#about to read 5, iclass 23, count 0 2006.285.06:33:35.40#ibcon#read 5, iclass 23, count 0 2006.285.06:33:35.40#ibcon#about to read 6, iclass 23, count 0 2006.285.06:33:35.40#ibcon#read 6, iclass 23, count 0 2006.285.06:33:35.40#ibcon#end of sib2, iclass 23, count 0 2006.285.06:33:35.40#ibcon#*after write, iclass 23, count 0 2006.285.06:33:35.40#ibcon#*before return 0, iclass 23, count 0 2006.285.06:33:35.40#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:33:35.40#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:33:35.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:33:35.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:33:35.40$vck44/valo=6,814.99 2006.285.06:33:35.40#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.06:33:35.40#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.06:33:35.40#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:35.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:33:35.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:33:35.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:33:35.40#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:33:35.40#ibcon#first serial, iclass 25, count 0 2006.285.06:33:35.40#ibcon#enter sib2, iclass 25, count 0 2006.285.06:33:35.40#ibcon#flushed, iclass 25, count 0 2006.285.06:33:35.40#ibcon#about to write, iclass 25, count 0 2006.285.06:33:35.40#ibcon#wrote, iclass 25, count 0 2006.285.06:33:35.40#ibcon#about to read 3, iclass 25, count 0 2006.285.06:33:35.42#ibcon#read 3, iclass 25, count 0 2006.285.06:33:35.42#ibcon#about to read 4, iclass 25, count 0 2006.285.06:33:35.42#ibcon#read 4, iclass 25, count 0 2006.285.06:33:35.42#ibcon#about to read 5, iclass 25, count 0 2006.285.06:33:35.42#ibcon#read 5, iclass 25, count 0 2006.285.06:33:35.42#ibcon#about to read 6, iclass 25, count 0 2006.285.06:33:35.42#ibcon#read 6, iclass 25, count 0 2006.285.06:33:35.42#ibcon#end of sib2, iclass 25, count 0 2006.285.06:33:35.42#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:33:35.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:33:35.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:33:35.42#ibcon#*before write, iclass 25, count 0 2006.285.06:33:35.42#ibcon#enter sib2, iclass 25, count 0 2006.285.06:33:35.42#ibcon#flushed, iclass 25, count 0 2006.285.06:33:35.42#ibcon#about to write, iclass 25, count 0 2006.285.06:33:35.42#ibcon#wrote, iclass 25, count 0 2006.285.06:33:35.42#ibcon#about to read 3, iclass 25, count 0 2006.285.06:33:35.46#ibcon#read 3, iclass 25, count 0 2006.285.06:33:35.46#ibcon#about to read 4, iclass 25, count 0 2006.285.06:33:35.46#ibcon#read 4, iclass 25, count 0 2006.285.06:33:35.46#ibcon#about to read 5, iclass 25, count 0 2006.285.06:33:35.46#ibcon#read 5, iclass 25, count 0 2006.285.06:33:35.46#ibcon#about to read 6, iclass 25, count 0 2006.285.06:33:35.46#ibcon#read 6, iclass 25, count 0 2006.285.06:33:35.46#ibcon#end of sib2, iclass 25, count 0 2006.285.06:33:35.46#ibcon#*after write, iclass 25, count 0 2006.285.06:33:35.46#ibcon#*before return 0, iclass 25, count 0 2006.285.06:33:35.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:33:35.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:33:35.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:33:35.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:33:35.46$vck44/va=6,4 2006.285.06:33:35.46#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.06:33:35.46#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.06:33:35.46#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:35.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:33:35.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:33:35.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:33:35.52#ibcon#enter wrdev, iclass 27, count 2 2006.285.06:33:35.52#ibcon#first serial, iclass 27, count 2 2006.285.06:33:35.52#ibcon#enter sib2, iclass 27, count 2 2006.285.06:33:35.52#ibcon#flushed, iclass 27, count 2 2006.285.06:33:35.52#ibcon#about to write, iclass 27, count 2 2006.285.06:33:35.52#ibcon#wrote, iclass 27, count 2 2006.285.06:33:35.52#ibcon#about to read 3, iclass 27, count 2 2006.285.06:33:35.54#ibcon#read 3, iclass 27, count 2 2006.285.06:33:35.54#ibcon#about to read 4, iclass 27, count 2 2006.285.06:33:35.54#ibcon#read 4, iclass 27, count 2 2006.285.06:33:35.54#ibcon#about to read 5, iclass 27, count 2 2006.285.06:33:35.54#ibcon#read 5, iclass 27, count 2 2006.285.06:33:35.54#ibcon#about to read 6, iclass 27, count 2 2006.285.06:33:35.54#ibcon#read 6, iclass 27, count 2 2006.285.06:33:35.54#ibcon#end of sib2, iclass 27, count 2 2006.285.06:33:35.54#ibcon#*mode == 0, iclass 27, count 2 2006.285.06:33:35.54#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.06:33:35.54#ibcon#[25=AT06-04\r\n] 2006.285.06:33:35.54#ibcon#*before write, iclass 27, count 2 2006.285.06:33:35.54#ibcon#enter sib2, iclass 27, count 2 2006.285.06:33:35.54#ibcon#flushed, iclass 27, count 2 2006.285.06:33:35.54#ibcon#about to write, iclass 27, count 2 2006.285.06:33:35.54#ibcon#wrote, iclass 27, count 2 2006.285.06:33:35.54#ibcon#about to read 3, iclass 27, count 2 2006.285.06:33:35.57#ibcon#read 3, iclass 27, count 2 2006.285.06:33:35.57#ibcon#about to read 4, iclass 27, count 2 2006.285.06:33:35.57#ibcon#read 4, iclass 27, count 2 2006.285.06:33:35.57#ibcon#about to read 5, iclass 27, count 2 2006.285.06:33:35.57#ibcon#read 5, iclass 27, count 2 2006.285.06:33:35.57#ibcon#about to read 6, iclass 27, count 2 2006.285.06:33:35.57#ibcon#read 6, iclass 27, count 2 2006.285.06:33:35.57#ibcon#end of sib2, iclass 27, count 2 2006.285.06:33:35.57#ibcon#*after write, iclass 27, count 2 2006.285.06:33:35.57#ibcon#*before return 0, iclass 27, count 2 2006.285.06:33:35.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:33:35.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:33:35.57#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.06:33:35.57#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:35.57#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:33:35.69#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:33:35.69#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:33:35.69#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:33:35.69#ibcon#first serial, iclass 27, count 0 2006.285.06:33:35.69#ibcon#enter sib2, iclass 27, count 0 2006.285.06:33:35.69#ibcon#flushed, iclass 27, count 0 2006.285.06:33:35.69#ibcon#about to write, iclass 27, count 0 2006.285.06:33:35.69#ibcon#wrote, iclass 27, count 0 2006.285.06:33:35.69#ibcon#about to read 3, iclass 27, count 0 2006.285.06:33:35.71#ibcon#read 3, iclass 27, count 0 2006.285.06:33:35.71#ibcon#about to read 4, iclass 27, count 0 2006.285.06:33:35.71#ibcon#read 4, iclass 27, count 0 2006.285.06:33:35.71#ibcon#about to read 5, iclass 27, count 0 2006.285.06:33:35.71#ibcon#read 5, iclass 27, count 0 2006.285.06:33:35.71#ibcon#about to read 6, iclass 27, count 0 2006.285.06:33:35.71#ibcon#read 6, iclass 27, count 0 2006.285.06:33:35.71#ibcon#end of sib2, iclass 27, count 0 2006.285.06:33:35.71#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:33:35.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:33:35.71#ibcon#[25=USB\r\n] 2006.285.06:33:35.71#ibcon#*before write, iclass 27, count 0 2006.285.06:33:35.71#ibcon#enter sib2, iclass 27, count 0 2006.285.06:33:35.71#ibcon#flushed, iclass 27, count 0 2006.285.06:33:35.71#ibcon#about to write, iclass 27, count 0 2006.285.06:33:35.71#ibcon#wrote, iclass 27, count 0 2006.285.06:33:35.71#ibcon#about to read 3, iclass 27, count 0 2006.285.06:33:35.74#ibcon#read 3, iclass 27, count 0 2006.285.06:33:35.74#ibcon#about to read 4, iclass 27, count 0 2006.285.06:33:35.74#ibcon#read 4, iclass 27, count 0 2006.285.06:33:35.74#ibcon#about to read 5, iclass 27, count 0 2006.285.06:33:35.74#ibcon#read 5, iclass 27, count 0 2006.285.06:33:35.74#ibcon#about to read 6, iclass 27, count 0 2006.285.06:33:35.74#ibcon#read 6, iclass 27, count 0 2006.285.06:33:35.74#ibcon#end of sib2, iclass 27, count 0 2006.285.06:33:35.74#ibcon#*after write, iclass 27, count 0 2006.285.06:33:35.74#ibcon#*before return 0, iclass 27, count 0 2006.285.06:33:35.74#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:33:35.74#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:33:35.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:33:35.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:33:35.74$vck44/valo=7,864.99 2006.285.06:33:35.74#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.06:33:35.74#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.06:33:35.74#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:35.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:33:35.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:33:35.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:33:35.74#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:33:35.74#ibcon#first serial, iclass 29, count 0 2006.285.06:33:35.74#ibcon#enter sib2, iclass 29, count 0 2006.285.06:33:35.74#ibcon#flushed, iclass 29, count 0 2006.285.06:33:35.74#ibcon#about to write, iclass 29, count 0 2006.285.06:33:35.74#ibcon#wrote, iclass 29, count 0 2006.285.06:33:35.74#ibcon#about to read 3, iclass 29, count 0 2006.285.06:33:35.76#ibcon#read 3, iclass 29, count 0 2006.285.06:33:35.76#ibcon#about to read 4, iclass 29, count 0 2006.285.06:33:35.76#ibcon#read 4, iclass 29, count 0 2006.285.06:33:35.76#ibcon#about to read 5, iclass 29, count 0 2006.285.06:33:35.76#ibcon#read 5, iclass 29, count 0 2006.285.06:33:35.76#ibcon#about to read 6, iclass 29, count 0 2006.285.06:33:35.76#ibcon#read 6, iclass 29, count 0 2006.285.06:33:35.76#ibcon#end of sib2, iclass 29, count 0 2006.285.06:33:35.76#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:33:35.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:33:35.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:33:35.76#ibcon#*before write, iclass 29, count 0 2006.285.06:33:35.76#ibcon#enter sib2, iclass 29, count 0 2006.285.06:33:35.76#ibcon#flushed, iclass 29, count 0 2006.285.06:33:35.76#ibcon#about to write, iclass 29, count 0 2006.285.06:33:35.76#ibcon#wrote, iclass 29, count 0 2006.285.06:33:35.76#ibcon#about to read 3, iclass 29, count 0 2006.285.06:33:35.80#ibcon#read 3, iclass 29, count 0 2006.285.06:33:35.80#ibcon#about to read 4, iclass 29, count 0 2006.285.06:33:35.80#ibcon#read 4, iclass 29, count 0 2006.285.06:33:35.80#ibcon#about to read 5, iclass 29, count 0 2006.285.06:33:35.80#ibcon#read 5, iclass 29, count 0 2006.285.06:33:35.80#ibcon#about to read 6, iclass 29, count 0 2006.285.06:33:35.80#ibcon#read 6, iclass 29, count 0 2006.285.06:33:35.80#ibcon#end of sib2, iclass 29, count 0 2006.285.06:33:35.80#ibcon#*after write, iclass 29, count 0 2006.285.06:33:35.80#ibcon#*before return 0, iclass 29, count 0 2006.285.06:33:35.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:33:35.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:33:35.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:33:35.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:33:35.80$vck44/va=7,4 2006.285.06:33:35.80#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.06:33:35.80#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.06:33:35.80#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:35.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:33:35.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:33:35.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:33:35.86#ibcon#enter wrdev, iclass 31, count 2 2006.285.06:33:35.86#ibcon#first serial, iclass 31, count 2 2006.285.06:33:35.86#ibcon#enter sib2, iclass 31, count 2 2006.285.06:33:35.86#ibcon#flushed, iclass 31, count 2 2006.285.06:33:35.86#ibcon#about to write, iclass 31, count 2 2006.285.06:33:35.86#ibcon#wrote, iclass 31, count 2 2006.285.06:33:35.86#ibcon#about to read 3, iclass 31, count 2 2006.285.06:33:35.88#ibcon#read 3, iclass 31, count 2 2006.285.06:33:35.88#ibcon#about to read 4, iclass 31, count 2 2006.285.06:33:35.88#ibcon#read 4, iclass 31, count 2 2006.285.06:33:35.88#ibcon#about to read 5, iclass 31, count 2 2006.285.06:33:35.88#ibcon#read 5, iclass 31, count 2 2006.285.06:33:35.88#ibcon#about to read 6, iclass 31, count 2 2006.285.06:33:35.88#ibcon#read 6, iclass 31, count 2 2006.285.06:33:35.88#ibcon#end of sib2, iclass 31, count 2 2006.285.06:33:35.88#ibcon#*mode == 0, iclass 31, count 2 2006.285.06:33:35.88#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.06:33:35.88#ibcon#[25=AT07-04\r\n] 2006.285.06:33:35.88#ibcon#*before write, iclass 31, count 2 2006.285.06:33:35.88#ibcon#enter sib2, iclass 31, count 2 2006.285.06:33:35.88#ibcon#flushed, iclass 31, count 2 2006.285.06:33:35.88#ibcon#about to write, iclass 31, count 2 2006.285.06:33:35.88#ibcon#wrote, iclass 31, count 2 2006.285.06:33:35.88#ibcon#about to read 3, iclass 31, count 2 2006.285.06:33:35.91#ibcon#read 3, iclass 31, count 2 2006.285.06:33:35.91#ibcon#about to read 4, iclass 31, count 2 2006.285.06:33:35.91#ibcon#read 4, iclass 31, count 2 2006.285.06:33:35.91#ibcon#about to read 5, iclass 31, count 2 2006.285.06:33:35.91#ibcon#read 5, iclass 31, count 2 2006.285.06:33:35.91#ibcon#about to read 6, iclass 31, count 2 2006.285.06:33:35.91#ibcon#read 6, iclass 31, count 2 2006.285.06:33:35.91#ibcon#end of sib2, iclass 31, count 2 2006.285.06:33:35.91#ibcon#*after write, iclass 31, count 2 2006.285.06:33:35.91#ibcon#*before return 0, iclass 31, count 2 2006.285.06:33:35.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:33:35.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:33:35.91#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.06:33:35.91#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:35.91#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:33:36.03#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:33:36.03#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:33:36.03#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:33:36.03#ibcon#first serial, iclass 31, count 0 2006.285.06:33:36.03#ibcon#enter sib2, iclass 31, count 0 2006.285.06:33:36.03#ibcon#flushed, iclass 31, count 0 2006.285.06:33:36.03#ibcon#about to write, iclass 31, count 0 2006.285.06:33:36.03#ibcon#wrote, iclass 31, count 0 2006.285.06:33:36.03#ibcon#about to read 3, iclass 31, count 0 2006.285.06:33:36.05#ibcon#read 3, iclass 31, count 0 2006.285.06:33:36.05#ibcon#about to read 4, iclass 31, count 0 2006.285.06:33:36.05#ibcon#read 4, iclass 31, count 0 2006.285.06:33:36.05#ibcon#about to read 5, iclass 31, count 0 2006.285.06:33:36.05#ibcon#read 5, iclass 31, count 0 2006.285.06:33:36.05#ibcon#about to read 6, iclass 31, count 0 2006.285.06:33:36.05#ibcon#read 6, iclass 31, count 0 2006.285.06:33:36.05#ibcon#end of sib2, iclass 31, count 0 2006.285.06:33:36.05#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:33:36.05#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:33:36.05#ibcon#[25=USB\r\n] 2006.285.06:33:36.05#ibcon#*before write, iclass 31, count 0 2006.285.06:33:36.05#ibcon#enter sib2, iclass 31, count 0 2006.285.06:33:36.05#ibcon#flushed, iclass 31, count 0 2006.285.06:33:36.05#ibcon#about to write, iclass 31, count 0 2006.285.06:33:36.05#ibcon#wrote, iclass 31, count 0 2006.285.06:33:36.05#ibcon#about to read 3, iclass 31, count 0 2006.285.06:33:36.08#ibcon#read 3, iclass 31, count 0 2006.285.06:33:36.08#ibcon#about to read 4, iclass 31, count 0 2006.285.06:33:36.08#ibcon#read 4, iclass 31, count 0 2006.285.06:33:36.08#ibcon#about to read 5, iclass 31, count 0 2006.285.06:33:36.08#ibcon#read 5, iclass 31, count 0 2006.285.06:33:36.08#ibcon#about to read 6, iclass 31, count 0 2006.285.06:33:36.08#ibcon#read 6, iclass 31, count 0 2006.285.06:33:36.08#ibcon#end of sib2, iclass 31, count 0 2006.285.06:33:36.08#ibcon#*after write, iclass 31, count 0 2006.285.06:33:36.08#ibcon#*before return 0, iclass 31, count 0 2006.285.06:33:36.08#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:33:36.08#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:33:36.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:33:36.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:33:36.08$vck44/valo=8,884.99 2006.285.06:33:36.08#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.06:33:36.08#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.06:33:36.08#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:36.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:33:36.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:33:36.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:33:36.08#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:33:36.08#ibcon#first serial, iclass 33, count 0 2006.285.06:33:36.08#ibcon#enter sib2, iclass 33, count 0 2006.285.06:33:36.08#ibcon#flushed, iclass 33, count 0 2006.285.06:33:36.08#ibcon#about to write, iclass 33, count 0 2006.285.06:33:36.08#ibcon#wrote, iclass 33, count 0 2006.285.06:33:36.08#ibcon#about to read 3, iclass 33, count 0 2006.285.06:33:36.10#ibcon#read 3, iclass 33, count 0 2006.285.06:33:36.10#ibcon#about to read 4, iclass 33, count 0 2006.285.06:33:36.10#ibcon#read 4, iclass 33, count 0 2006.285.06:33:36.10#ibcon#about to read 5, iclass 33, count 0 2006.285.06:33:36.10#ibcon#read 5, iclass 33, count 0 2006.285.06:33:36.10#ibcon#about to read 6, iclass 33, count 0 2006.285.06:33:36.10#ibcon#read 6, iclass 33, count 0 2006.285.06:33:36.10#ibcon#end of sib2, iclass 33, count 0 2006.285.06:33:36.10#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:33:36.10#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:33:36.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:33:36.10#ibcon#*before write, iclass 33, count 0 2006.285.06:33:36.10#ibcon#enter sib2, iclass 33, count 0 2006.285.06:33:36.10#ibcon#flushed, iclass 33, count 0 2006.285.06:33:36.10#ibcon#about to write, iclass 33, count 0 2006.285.06:33:36.10#ibcon#wrote, iclass 33, count 0 2006.285.06:33:36.10#ibcon#about to read 3, iclass 33, count 0 2006.285.06:33:36.14#ibcon#read 3, iclass 33, count 0 2006.285.06:33:36.14#ibcon#about to read 4, iclass 33, count 0 2006.285.06:33:36.14#ibcon#read 4, iclass 33, count 0 2006.285.06:33:36.14#ibcon#about to read 5, iclass 33, count 0 2006.285.06:33:36.14#ibcon#read 5, iclass 33, count 0 2006.285.06:33:36.14#ibcon#about to read 6, iclass 33, count 0 2006.285.06:33:36.14#ibcon#read 6, iclass 33, count 0 2006.285.06:33:36.14#ibcon#end of sib2, iclass 33, count 0 2006.285.06:33:36.14#ibcon#*after write, iclass 33, count 0 2006.285.06:33:36.14#ibcon#*before return 0, iclass 33, count 0 2006.285.06:33:36.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:33:36.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:33:36.14#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:33:36.14#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:33:36.14$vck44/va=8,3 2006.285.06:33:36.14#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.06:33:36.14#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.06:33:36.14#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:36.14#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:33:36.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:33:36.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:33:36.20#ibcon#enter wrdev, iclass 35, count 2 2006.285.06:33:36.20#ibcon#first serial, iclass 35, count 2 2006.285.06:33:36.20#ibcon#enter sib2, iclass 35, count 2 2006.285.06:33:36.20#ibcon#flushed, iclass 35, count 2 2006.285.06:33:36.20#ibcon#about to write, iclass 35, count 2 2006.285.06:33:36.20#ibcon#wrote, iclass 35, count 2 2006.285.06:33:36.20#ibcon#about to read 3, iclass 35, count 2 2006.285.06:33:36.22#ibcon#read 3, iclass 35, count 2 2006.285.06:33:36.22#ibcon#about to read 4, iclass 35, count 2 2006.285.06:33:36.22#ibcon#read 4, iclass 35, count 2 2006.285.06:33:36.22#ibcon#about to read 5, iclass 35, count 2 2006.285.06:33:36.22#ibcon#read 5, iclass 35, count 2 2006.285.06:33:36.22#ibcon#about to read 6, iclass 35, count 2 2006.285.06:33:36.22#ibcon#read 6, iclass 35, count 2 2006.285.06:33:36.22#ibcon#end of sib2, iclass 35, count 2 2006.285.06:33:36.22#ibcon#*mode == 0, iclass 35, count 2 2006.285.06:33:36.22#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.06:33:36.22#ibcon#[25=AT08-03\r\n] 2006.285.06:33:36.22#ibcon#*before write, iclass 35, count 2 2006.285.06:33:36.22#ibcon#enter sib2, iclass 35, count 2 2006.285.06:33:36.22#ibcon#flushed, iclass 35, count 2 2006.285.06:33:36.22#ibcon#about to write, iclass 35, count 2 2006.285.06:33:36.22#ibcon#wrote, iclass 35, count 2 2006.285.06:33:36.22#ibcon#about to read 3, iclass 35, count 2 2006.285.06:33:36.25#ibcon#read 3, iclass 35, count 2 2006.285.06:33:36.25#ibcon#about to read 4, iclass 35, count 2 2006.285.06:33:36.25#ibcon#read 4, iclass 35, count 2 2006.285.06:33:36.25#ibcon#about to read 5, iclass 35, count 2 2006.285.06:33:36.25#ibcon#read 5, iclass 35, count 2 2006.285.06:33:36.25#ibcon#about to read 6, iclass 35, count 2 2006.285.06:33:36.25#ibcon#read 6, iclass 35, count 2 2006.285.06:33:36.25#ibcon#end of sib2, iclass 35, count 2 2006.285.06:33:36.25#ibcon#*after write, iclass 35, count 2 2006.285.06:33:36.25#ibcon#*before return 0, iclass 35, count 2 2006.285.06:33:36.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:33:36.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.06:33:36.25#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.06:33:36.25#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:36.25#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:33:36.37#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:33:36.37#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:33:36.37#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:33:36.37#ibcon#first serial, iclass 35, count 0 2006.285.06:33:36.37#ibcon#enter sib2, iclass 35, count 0 2006.285.06:33:36.37#ibcon#flushed, iclass 35, count 0 2006.285.06:33:36.37#ibcon#about to write, iclass 35, count 0 2006.285.06:33:36.37#ibcon#wrote, iclass 35, count 0 2006.285.06:33:36.37#ibcon#about to read 3, iclass 35, count 0 2006.285.06:33:36.39#ibcon#read 3, iclass 35, count 0 2006.285.06:33:36.39#ibcon#about to read 4, iclass 35, count 0 2006.285.06:33:36.39#ibcon#read 4, iclass 35, count 0 2006.285.06:33:36.39#ibcon#about to read 5, iclass 35, count 0 2006.285.06:33:36.39#ibcon#read 5, iclass 35, count 0 2006.285.06:33:36.39#ibcon#about to read 6, iclass 35, count 0 2006.285.06:33:36.39#ibcon#read 6, iclass 35, count 0 2006.285.06:33:36.39#ibcon#end of sib2, iclass 35, count 0 2006.285.06:33:36.39#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:33:36.39#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:33:36.39#ibcon#[25=USB\r\n] 2006.285.06:33:36.39#ibcon#*before write, iclass 35, count 0 2006.285.06:33:36.39#ibcon#enter sib2, iclass 35, count 0 2006.285.06:33:36.39#ibcon#flushed, iclass 35, count 0 2006.285.06:33:36.39#ibcon#about to write, iclass 35, count 0 2006.285.06:33:36.39#ibcon#wrote, iclass 35, count 0 2006.285.06:33:36.39#ibcon#about to read 3, iclass 35, count 0 2006.285.06:33:36.42#ibcon#read 3, iclass 35, count 0 2006.285.06:33:36.42#ibcon#about to read 4, iclass 35, count 0 2006.285.06:33:36.42#ibcon#read 4, iclass 35, count 0 2006.285.06:33:36.42#ibcon#about to read 5, iclass 35, count 0 2006.285.06:33:36.42#ibcon#read 5, iclass 35, count 0 2006.285.06:33:36.42#ibcon#about to read 6, iclass 35, count 0 2006.285.06:33:36.42#ibcon#read 6, iclass 35, count 0 2006.285.06:33:36.42#ibcon#end of sib2, iclass 35, count 0 2006.285.06:33:36.42#ibcon#*after write, iclass 35, count 0 2006.285.06:33:36.42#ibcon#*before return 0, iclass 35, count 0 2006.285.06:33:36.42#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:33:36.42#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.06:33:36.42#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:33:36.42#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:33:36.42$vck44/vblo=1,629.99 2006.285.06:33:36.42#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.06:33:36.42#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.06:33:36.42#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:36.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:33:36.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:33:36.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:33:36.42#ibcon#enter wrdev, iclass 37, count 0 2006.285.06:33:36.42#ibcon#first serial, iclass 37, count 0 2006.285.06:33:36.42#ibcon#enter sib2, iclass 37, count 0 2006.285.06:33:36.42#ibcon#flushed, iclass 37, count 0 2006.285.06:33:36.42#ibcon#about to write, iclass 37, count 0 2006.285.06:33:36.42#ibcon#wrote, iclass 37, count 0 2006.285.06:33:36.42#ibcon#about to read 3, iclass 37, count 0 2006.285.06:33:36.44#ibcon#read 3, iclass 37, count 0 2006.285.06:33:36.44#ibcon#about to read 4, iclass 37, count 0 2006.285.06:33:36.44#ibcon#read 4, iclass 37, count 0 2006.285.06:33:36.44#ibcon#about to read 5, iclass 37, count 0 2006.285.06:33:36.44#ibcon#read 5, iclass 37, count 0 2006.285.06:33:36.44#ibcon#about to read 6, iclass 37, count 0 2006.285.06:33:36.44#ibcon#read 6, iclass 37, count 0 2006.285.06:33:36.44#ibcon#end of sib2, iclass 37, count 0 2006.285.06:33:36.44#ibcon#*mode == 0, iclass 37, count 0 2006.285.06:33:36.44#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.06:33:36.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:33:36.44#ibcon#*before write, iclass 37, count 0 2006.285.06:33:36.44#ibcon#enter sib2, iclass 37, count 0 2006.285.06:33:36.44#ibcon#flushed, iclass 37, count 0 2006.285.06:33:36.44#ibcon#about to write, iclass 37, count 0 2006.285.06:33:36.44#ibcon#wrote, iclass 37, count 0 2006.285.06:33:36.44#ibcon#about to read 3, iclass 37, count 0 2006.285.06:33:36.48#ibcon#read 3, iclass 37, count 0 2006.285.06:33:36.48#ibcon#about to read 4, iclass 37, count 0 2006.285.06:33:36.48#ibcon#read 4, iclass 37, count 0 2006.285.06:33:36.48#ibcon#about to read 5, iclass 37, count 0 2006.285.06:33:36.48#ibcon#read 5, iclass 37, count 0 2006.285.06:33:36.48#ibcon#about to read 6, iclass 37, count 0 2006.285.06:33:36.48#ibcon#read 6, iclass 37, count 0 2006.285.06:33:36.48#ibcon#end of sib2, iclass 37, count 0 2006.285.06:33:36.48#ibcon#*after write, iclass 37, count 0 2006.285.06:33:36.48#ibcon#*before return 0, iclass 37, count 0 2006.285.06:33:36.48#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:33:36.48#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.06:33:36.48#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.06:33:36.48#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.06:33:36.48$vck44/vb=1,4 2006.285.06:33:36.48#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.06:33:36.48#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.06:33:36.48#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:36.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:33:36.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:33:36.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:33:36.48#ibcon#enter wrdev, iclass 39, count 2 2006.285.06:33:36.48#ibcon#first serial, iclass 39, count 2 2006.285.06:33:36.48#ibcon#enter sib2, iclass 39, count 2 2006.285.06:33:36.48#ibcon#flushed, iclass 39, count 2 2006.285.06:33:36.48#ibcon#about to write, iclass 39, count 2 2006.285.06:33:36.48#ibcon#wrote, iclass 39, count 2 2006.285.06:33:36.48#ibcon#about to read 3, iclass 39, count 2 2006.285.06:33:36.50#ibcon#read 3, iclass 39, count 2 2006.285.06:33:36.50#ibcon#about to read 4, iclass 39, count 2 2006.285.06:33:36.50#ibcon#read 4, iclass 39, count 2 2006.285.06:33:36.50#ibcon#about to read 5, iclass 39, count 2 2006.285.06:33:36.50#ibcon#read 5, iclass 39, count 2 2006.285.06:33:36.50#ibcon#about to read 6, iclass 39, count 2 2006.285.06:33:36.50#ibcon#read 6, iclass 39, count 2 2006.285.06:33:36.50#ibcon#end of sib2, iclass 39, count 2 2006.285.06:33:36.50#ibcon#*mode == 0, iclass 39, count 2 2006.285.06:33:36.50#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.06:33:36.50#ibcon#[27=AT01-04\r\n] 2006.285.06:33:36.50#ibcon#*before write, iclass 39, count 2 2006.285.06:33:36.50#ibcon#enter sib2, iclass 39, count 2 2006.285.06:33:36.50#ibcon#flushed, iclass 39, count 2 2006.285.06:33:36.50#ibcon#about to write, iclass 39, count 2 2006.285.06:33:36.50#ibcon#wrote, iclass 39, count 2 2006.285.06:33:36.50#ibcon#about to read 3, iclass 39, count 2 2006.285.06:33:36.53#ibcon#read 3, iclass 39, count 2 2006.285.06:33:36.53#ibcon#about to read 4, iclass 39, count 2 2006.285.06:33:36.53#ibcon#read 4, iclass 39, count 2 2006.285.06:33:36.53#ibcon#about to read 5, iclass 39, count 2 2006.285.06:33:36.53#ibcon#read 5, iclass 39, count 2 2006.285.06:33:36.53#ibcon#about to read 6, iclass 39, count 2 2006.285.06:33:36.53#ibcon#read 6, iclass 39, count 2 2006.285.06:33:36.53#ibcon#end of sib2, iclass 39, count 2 2006.285.06:33:36.53#ibcon#*after write, iclass 39, count 2 2006.285.06:33:36.53#ibcon#*before return 0, iclass 39, count 2 2006.285.06:33:36.53#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:33:36.53#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.06:33:36.53#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.06:33:36.53#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:36.53#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:33:36.65#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:33:36.65#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:33:36.65#ibcon#enter wrdev, iclass 39, count 0 2006.285.06:33:36.65#ibcon#first serial, iclass 39, count 0 2006.285.06:33:36.65#ibcon#enter sib2, iclass 39, count 0 2006.285.06:33:36.65#ibcon#flushed, iclass 39, count 0 2006.285.06:33:36.65#ibcon#about to write, iclass 39, count 0 2006.285.06:33:36.65#ibcon#wrote, iclass 39, count 0 2006.285.06:33:36.65#ibcon#about to read 3, iclass 39, count 0 2006.285.06:33:36.67#ibcon#read 3, iclass 39, count 0 2006.285.06:33:36.67#ibcon#about to read 4, iclass 39, count 0 2006.285.06:33:36.67#ibcon#read 4, iclass 39, count 0 2006.285.06:33:36.67#ibcon#about to read 5, iclass 39, count 0 2006.285.06:33:36.67#ibcon#read 5, iclass 39, count 0 2006.285.06:33:36.67#ibcon#about to read 6, iclass 39, count 0 2006.285.06:33:36.67#ibcon#read 6, iclass 39, count 0 2006.285.06:33:36.67#ibcon#end of sib2, iclass 39, count 0 2006.285.06:33:36.67#ibcon#*mode == 0, iclass 39, count 0 2006.285.06:33:36.67#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.06:33:36.67#ibcon#[27=USB\r\n] 2006.285.06:33:36.67#ibcon#*before write, iclass 39, count 0 2006.285.06:33:36.67#ibcon#enter sib2, iclass 39, count 0 2006.285.06:33:36.67#ibcon#flushed, iclass 39, count 0 2006.285.06:33:36.67#ibcon#about to write, iclass 39, count 0 2006.285.06:33:36.67#ibcon#wrote, iclass 39, count 0 2006.285.06:33:36.67#ibcon#about to read 3, iclass 39, count 0 2006.285.06:33:36.70#ibcon#read 3, iclass 39, count 0 2006.285.06:33:36.70#ibcon#about to read 4, iclass 39, count 0 2006.285.06:33:36.70#ibcon#read 4, iclass 39, count 0 2006.285.06:33:36.70#ibcon#about to read 5, iclass 39, count 0 2006.285.06:33:36.70#ibcon#read 5, iclass 39, count 0 2006.285.06:33:36.70#ibcon#about to read 6, iclass 39, count 0 2006.285.06:33:36.70#ibcon#read 6, iclass 39, count 0 2006.285.06:33:36.70#ibcon#end of sib2, iclass 39, count 0 2006.285.06:33:36.70#ibcon#*after write, iclass 39, count 0 2006.285.06:33:36.70#ibcon#*before return 0, iclass 39, count 0 2006.285.06:33:36.70#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:33:36.70#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.06:33:36.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.06:33:36.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.06:33:36.70$vck44/vblo=2,634.99 2006.285.06:33:36.70#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.06:33:36.70#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.06:33:36.70#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:36.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:33:36.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:33:36.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:33:36.70#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:33:36.70#ibcon#first serial, iclass 3, count 0 2006.285.06:33:36.70#ibcon#enter sib2, iclass 3, count 0 2006.285.06:33:36.70#ibcon#flushed, iclass 3, count 0 2006.285.06:33:36.70#ibcon#about to write, iclass 3, count 0 2006.285.06:33:36.70#ibcon#wrote, iclass 3, count 0 2006.285.06:33:36.70#ibcon#about to read 3, iclass 3, count 0 2006.285.06:33:36.72#ibcon#read 3, iclass 3, count 0 2006.285.06:33:36.72#ibcon#about to read 4, iclass 3, count 0 2006.285.06:33:36.72#ibcon#read 4, iclass 3, count 0 2006.285.06:33:36.72#ibcon#about to read 5, iclass 3, count 0 2006.285.06:33:36.72#ibcon#read 5, iclass 3, count 0 2006.285.06:33:36.72#ibcon#about to read 6, iclass 3, count 0 2006.285.06:33:36.72#ibcon#read 6, iclass 3, count 0 2006.285.06:33:36.72#ibcon#end of sib2, iclass 3, count 0 2006.285.06:33:36.72#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:33:36.72#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:33:36.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:33:36.72#ibcon#*before write, iclass 3, count 0 2006.285.06:33:36.72#ibcon#enter sib2, iclass 3, count 0 2006.285.06:33:36.72#ibcon#flushed, iclass 3, count 0 2006.285.06:33:36.72#ibcon#about to write, iclass 3, count 0 2006.285.06:33:36.72#ibcon#wrote, iclass 3, count 0 2006.285.06:33:36.72#ibcon#about to read 3, iclass 3, count 0 2006.285.06:33:36.76#ibcon#read 3, iclass 3, count 0 2006.285.06:33:36.76#ibcon#about to read 4, iclass 3, count 0 2006.285.06:33:36.76#ibcon#read 4, iclass 3, count 0 2006.285.06:33:36.76#ibcon#about to read 5, iclass 3, count 0 2006.285.06:33:36.76#ibcon#read 5, iclass 3, count 0 2006.285.06:33:36.76#ibcon#about to read 6, iclass 3, count 0 2006.285.06:33:36.76#ibcon#read 6, iclass 3, count 0 2006.285.06:33:36.76#ibcon#end of sib2, iclass 3, count 0 2006.285.06:33:36.76#ibcon#*after write, iclass 3, count 0 2006.285.06:33:36.76#ibcon#*before return 0, iclass 3, count 0 2006.285.06:33:36.76#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:33:36.76#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.06:33:36.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:33:36.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:33:36.76$vck44/vb=2,5 2006.285.06:33:36.76#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.06:33:36.76#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.06:33:36.76#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:36.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:33:36.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:33:36.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:33:36.82#ibcon#enter wrdev, iclass 5, count 2 2006.285.06:33:36.82#ibcon#first serial, iclass 5, count 2 2006.285.06:33:36.82#ibcon#enter sib2, iclass 5, count 2 2006.285.06:33:36.82#ibcon#flushed, iclass 5, count 2 2006.285.06:33:36.82#ibcon#about to write, iclass 5, count 2 2006.285.06:33:36.82#ibcon#wrote, iclass 5, count 2 2006.285.06:33:36.82#ibcon#about to read 3, iclass 5, count 2 2006.285.06:33:36.84#ibcon#read 3, iclass 5, count 2 2006.285.06:33:36.84#ibcon#about to read 4, iclass 5, count 2 2006.285.06:33:36.84#ibcon#read 4, iclass 5, count 2 2006.285.06:33:36.84#ibcon#about to read 5, iclass 5, count 2 2006.285.06:33:36.84#ibcon#read 5, iclass 5, count 2 2006.285.06:33:36.84#ibcon#about to read 6, iclass 5, count 2 2006.285.06:33:36.84#ibcon#read 6, iclass 5, count 2 2006.285.06:33:36.84#ibcon#end of sib2, iclass 5, count 2 2006.285.06:33:36.84#ibcon#*mode == 0, iclass 5, count 2 2006.285.06:33:36.84#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.06:33:36.84#ibcon#[27=AT02-05\r\n] 2006.285.06:33:36.84#ibcon#*before write, iclass 5, count 2 2006.285.06:33:36.84#ibcon#enter sib2, iclass 5, count 2 2006.285.06:33:36.84#ibcon#flushed, iclass 5, count 2 2006.285.06:33:36.84#ibcon#about to write, iclass 5, count 2 2006.285.06:33:36.84#ibcon#wrote, iclass 5, count 2 2006.285.06:33:36.84#ibcon#about to read 3, iclass 5, count 2 2006.285.06:33:36.87#ibcon#read 3, iclass 5, count 2 2006.285.06:33:36.87#ibcon#about to read 4, iclass 5, count 2 2006.285.06:33:36.87#ibcon#read 4, iclass 5, count 2 2006.285.06:33:36.87#ibcon#about to read 5, iclass 5, count 2 2006.285.06:33:36.87#ibcon#read 5, iclass 5, count 2 2006.285.06:33:36.87#ibcon#about to read 6, iclass 5, count 2 2006.285.06:33:36.87#ibcon#read 6, iclass 5, count 2 2006.285.06:33:36.87#ibcon#end of sib2, iclass 5, count 2 2006.285.06:33:36.87#ibcon#*after write, iclass 5, count 2 2006.285.06:33:36.87#ibcon#*before return 0, iclass 5, count 2 2006.285.06:33:36.87#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:33:36.87#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.06:33:36.87#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.06:33:36.87#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:36.87#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:33:36.99#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:33:36.99#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:33:36.99#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:33:36.99#ibcon#first serial, iclass 5, count 0 2006.285.06:33:36.99#ibcon#enter sib2, iclass 5, count 0 2006.285.06:33:36.99#ibcon#flushed, iclass 5, count 0 2006.285.06:33:36.99#ibcon#about to write, iclass 5, count 0 2006.285.06:33:36.99#ibcon#wrote, iclass 5, count 0 2006.285.06:33:36.99#ibcon#about to read 3, iclass 5, count 0 2006.285.06:33:37.01#ibcon#read 3, iclass 5, count 0 2006.285.06:33:37.01#ibcon#about to read 4, iclass 5, count 0 2006.285.06:33:37.01#ibcon#read 4, iclass 5, count 0 2006.285.06:33:37.01#ibcon#about to read 5, iclass 5, count 0 2006.285.06:33:37.01#ibcon#read 5, iclass 5, count 0 2006.285.06:33:37.01#ibcon#about to read 6, iclass 5, count 0 2006.285.06:33:37.01#ibcon#read 6, iclass 5, count 0 2006.285.06:33:37.01#ibcon#end of sib2, iclass 5, count 0 2006.285.06:33:37.01#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:33:37.01#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:33:37.01#ibcon#[27=USB\r\n] 2006.285.06:33:37.01#ibcon#*before write, iclass 5, count 0 2006.285.06:33:37.01#ibcon#enter sib2, iclass 5, count 0 2006.285.06:33:37.01#ibcon#flushed, iclass 5, count 0 2006.285.06:33:37.01#ibcon#about to write, iclass 5, count 0 2006.285.06:33:37.01#ibcon#wrote, iclass 5, count 0 2006.285.06:33:37.01#ibcon#about to read 3, iclass 5, count 0 2006.285.06:33:37.04#ibcon#read 3, iclass 5, count 0 2006.285.06:33:37.04#ibcon#about to read 4, iclass 5, count 0 2006.285.06:33:37.04#ibcon#read 4, iclass 5, count 0 2006.285.06:33:37.04#ibcon#about to read 5, iclass 5, count 0 2006.285.06:33:37.04#ibcon#read 5, iclass 5, count 0 2006.285.06:33:37.04#ibcon#about to read 6, iclass 5, count 0 2006.285.06:33:37.04#ibcon#read 6, iclass 5, count 0 2006.285.06:33:37.04#ibcon#end of sib2, iclass 5, count 0 2006.285.06:33:37.04#ibcon#*after write, iclass 5, count 0 2006.285.06:33:37.04#ibcon#*before return 0, iclass 5, count 0 2006.285.06:33:37.04#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:33:37.04#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.06:33:37.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:33:37.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:33:37.04$vck44/vblo=3,649.99 2006.285.06:33:37.04#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.06:33:37.04#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.06:33:37.04#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:37.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:33:37.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:33:37.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:33:37.04#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:33:37.04#ibcon#first serial, iclass 7, count 0 2006.285.06:33:37.04#ibcon#enter sib2, iclass 7, count 0 2006.285.06:33:37.04#ibcon#flushed, iclass 7, count 0 2006.285.06:33:37.04#ibcon#about to write, iclass 7, count 0 2006.285.06:33:37.04#ibcon#wrote, iclass 7, count 0 2006.285.06:33:37.04#ibcon#about to read 3, iclass 7, count 0 2006.285.06:33:37.06#ibcon#read 3, iclass 7, count 0 2006.285.06:33:37.06#ibcon#about to read 4, iclass 7, count 0 2006.285.06:33:37.06#ibcon#read 4, iclass 7, count 0 2006.285.06:33:37.06#ibcon#about to read 5, iclass 7, count 0 2006.285.06:33:37.06#ibcon#read 5, iclass 7, count 0 2006.285.06:33:37.06#ibcon#about to read 6, iclass 7, count 0 2006.285.06:33:37.06#ibcon#read 6, iclass 7, count 0 2006.285.06:33:37.06#ibcon#end of sib2, iclass 7, count 0 2006.285.06:33:37.06#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:33:37.06#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:33:37.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:33:37.06#ibcon#*before write, iclass 7, count 0 2006.285.06:33:37.06#ibcon#enter sib2, iclass 7, count 0 2006.285.06:33:37.06#ibcon#flushed, iclass 7, count 0 2006.285.06:33:37.06#ibcon#about to write, iclass 7, count 0 2006.285.06:33:37.06#ibcon#wrote, iclass 7, count 0 2006.285.06:33:37.06#ibcon#about to read 3, iclass 7, count 0 2006.285.06:33:37.10#ibcon#read 3, iclass 7, count 0 2006.285.06:33:37.10#ibcon#about to read 4, iclass 7, count 0 2006.285.06:33:37.10#ibcon#read 4, iclass 7, count 0 2006.285.06:33:37.10#ibcon#about to read 5, iclass 7, count 0 2006.285.06:33:37.10#ibcon#read 5, iclass 7, count 0 2006.285.06:33:37.10#ibcon#about to read 6, iclass 7, count 0 2006.285.06:33:37.10#ibcon#read 6, iclass 7, count 0 2006.285.06:33:37.10#ibcon#end of sib2, iclass 7, count 0 2006.285.06:33:37.10#ibcon#*after write, iclass 7, count 0 2006.285.06:33:37.10#ibcon#*before return 0, iclass 7, count 0 2006.285.06:33:37.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:33:37.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:33:37.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:33:37.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:33:37.10$vck44/vb=3,4 2006.285.06:33:37.10#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.06:33:37.10#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.06:33:37.10#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:37.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:33:37.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:33:37.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:33:37.16#ibcon#enter wrdev, iclass 11, count 2 2006.285.06:33:37.16#ibcon#first serial, iclass 11, count 2 2006.285.06:33:37.16#ibcon#enter sib2, iclass 11, count 2 2006.285.06:33:37.16#ibcon#flushed, iclass 11, count 2 2006.285.06:33:37.16#ibcon#about to write, iclass 11, count 2 2006.285.06:33:37.16#ibcon#wrote, iclass 11, count 2 2006.285.06:33:37.16#ibcon#about to read 3, iclass 11, count 2 2006.285.06:33:37.18#ibcon#read 3, iclass 11, count 2 2006.285.06:33:37.18#ibcon#about to read 4, iclass 11, count 2 2006.285.06:33:37.18#ibcon#read 4, iclass 11, count 2 2006.285.06:33:37.18#ibcon#about to read 5, iclass 11, count 2 2006.285.06:33:37.18#ibcon#read 5, iclass 11, count 2 2006.285.06:33:37.18#ibcon#about to read 6, iclass 11, count 2 2006.285.06:33:37.18#ibcon#read 6, iclass 11, count 2 2006.285.06:33:37.18#ibcon#end of sib2, iclass 11, count 2 2006.285.06:33:37.18#ibcon#*mode == 0, iclass 11, count 2 2006.285.06:33:37.18#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.06:33:37.18#ibcon#[27=AT03-04\r\n] 2006.285.06:33:37.18#ibcon#*before write, iclass 11, count 2 2006.285.06:33:37.18#ibcon#enter sib2, iclass 11, count 2 2006.285.06:33:37.18#ibcon#flushed, iclass 11, count 2 2006.285.06:33:37.18#ibcon#about to write, iclass 11, count 2 2006.285.06:33:37.18#ibcon#wrote, iclass 11, count 2 2006.285.06:33:37.18#ibcon#about to read 3, iclass 11, count 2 2006.285.06:33:37.21#ibcon#read 3, iclass 11, count 2 2006.285.06:33:37.21#ibcon#about to read 4, iclass 11, count 2 2006.285.06:33:37.21#ibcon#read 4, iclass 11, count 2 2006.285.06:33:37.21#ibcon#about to read 5, iclass 11, count 2 2006.285.06:33:37.21#ibcon#read 5, iclass 11, count 2 2006.285.06:33:37.21#ibcon#about to read 6, iclass 11, count 2 2006.285.06:33:37.21#ibcon#read 6, iclass 11, count 2 2006.285.06:33:37.21#ibcon#end of sib2, iclass 11, count 2 2006.285.06:33:37.21#ibcon#*after write, iclass 11, count 2 2006.285.06:33:37.21#ibcon#*before return 0, iclass 11, count 2 2006.285.06:33:37.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:33:37.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.06:33:37.21#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.06:33:37.21#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:37.21#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:33:37.33#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:33:37.33#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:33:37.33#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:33:37.33#ibcon#first serial, iclass 11, count 0 2006.285.06:33:37.33#ibcon#enter sib2, iclass 11, count 0 2006.285.06:33:37.33#ibcon#flushed, iclass 11, count 0 2006.285.06:33:37.33#ibcon#about to write, iclass 11, count 0 2006.285.06:33:37.33#ibcon#wrote, iclass 11, count 0 2006.285.06:33:37.33#ibcon#about to read 3, iclass 11, count 0 2006.285.06:33:37.35#ibcon#read 3, iclass 11, count 0 2006.285.06:33:37.35#ibcon#about to read 4, iclass 11, count 0 2006.285.06:33:37.35#ibcon#read 4, iclass 11, count 0 2006.285.06:33:37.35#ibcon#about to read 5, iclass 11, count 0 2006.285.06:33:37.35#ibcon#read 5, iclass 11, count 0 2006.285.06:33:37.35#ibcon#about to read 6, iclass 11, count 0 2006.285.06:33:37.35#ibcon#read 6, iclass 11, count 0 2006.285.06:33:37.35#ibcon#end of sib2, iclass 11, count 0 2006.285.06:33:37.35#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:33:37.35#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:33:37.35#ibcon#[27=USB\r\n] 2006.285.06:33:37.35#ibcon#*before write, iclass 11, count 0 2006.285.06:33:37.35#ibcon#enter sib2, iclass 11, count 0 2006.285.06:33:37.35#ibcon#flushed, iclass 11, count 0 2006.285.06:33:37.35#ibcon#about to write, iclass 11, count 0 2006.285.06:33:37.35#ibcon#wrote, iclass 11, count 0 2006.285.06:33:37.35#ibcon#about to read 3, iclass 11, count 0 2006.285.06:33:37.38#ibcon#read 3, iclass 11, count 0 2006.285.06:33:37.38#ibcon#about to read 4, iclass 11, count 0 2006.285.06:33:37.38#ibcon#read 4, iclass 11, count 0 2006.285.06:33:37.38#ibcon#about to read 5, iclass 11, count 0 2006.285.06:33:37.38#ibcon#read 5, iclass 11, count 0 2006.285.06:33:37.38#ibcon#about to read 6, iclass 11, count 0 2006.285.06:33:37.38#ibcon#read 6, iclass 11, count 0 2006.285.06:33:37.38#ibcon#end of sib2, iclass 11, count 0 2006.285.06:33:37.38#ibcon#*after write, iclass 11, count 0 2006.285.06:33:37.38#ibcon#*before return 0, iclass 11, count 0 2006.285.06:33:37.38#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:33:37.38#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.06:33:37.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:33:37.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:33:37.38$vck44/vblo=4,679.99 2006.285.06:33:37.38#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.06:33:37.38#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.06:33:37.38#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:37.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:33:37.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:33:37.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:33:37.38#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:33:37.38#ibcon#first serial, iclass 13, count 0 2006.285.06:33:37.38#ibcon#enter sib2, iclass 13, count 0 2006.285.06:33:37.38#ibcon#flushed, iclass 13, count 0 2006.285.06:33:37.38#ibcon#about to write, iclass 13, count 0 2006.285.06:33:37.38#ibcon#wrote, iclass 13, count 0 2006.285.06:33:37.38#ibcon#about to read 3, iclass 13, count 0 2006.285.06:33:37.40#ibcon#read 3, iclass 13, count 0 2006.285.06:33:37.40#ibcon#about to read 4, iclass 13, count 0 2006.285.06:33:37.40#ibcon#read 4, iclass 13, count 0 2006.285.06:33:37.40#ibcon#about to read 5, iclass 13, count 0 2006.285.06:33:37.40#ibcon#read 5, iclass 13, count 0 2006.285.06:33:37.40#ibcon#about to read 6, iclass 13, count 0 2006.285.06:33:37.40#ibcon#read 6, iclass 13, count 0 2006.285.06:33:37.40#ibcon#end of sib2, iclass 13, count 0 2006.285.06:33:37.40#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:33:37.40#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:33:37.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:33:37.40#ibcon#*before write, iclass 13, count 0 2006.285.06:33:37.40#ibcon#enter sib2, iclass 13, count 0 2006.285.06:33:37.40#ibcon#flushed, iclass 13, count 0 2006.285.06:33:37.40#ibcon#about to write, iclass 13, count 0 2006.285.06:33:37.40#ibcon#wrote, iclass 13, count 0 2006.285.06:33:37.40#ibcon#about to read 3, iclass 13, count 0 2006.285.06:33:37.44#ibcon#read 3, iclass 13, count 0 2006.285.06:33:37.44#ibcon#about to read 4, iclass 13, count 0 2006.285.06:33:37.44#ibcon#read 4, iclass 13, count 0 2006.285.06:33:37.44#ibcon#about to read 5, iclass 13, count 0 2006.285.06:33:37.44#ibcon#read 5, iclass 13, count 0 2006.285.06:33:37.44#ibcon#about to read 6, iclass 13, count 0 2006.285.06:33:37.44#ibcon#read 6, iclass 13, count 0 2006.285.06:33:37.44#ibcon#end of sib2, iclass 13, count 0 2006.285.06:33:37.44#ibcon#*after write, iclass 13, count 0 2006.285.06:33:37.44#ibcon#*before return 0, iclass 13, count 0 2006.285.06:33:37.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:33:37.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.06:33:37.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:33:37.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:33:37.44$vck44/vb=4,5 2006.285.06:33:37.44#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.06:33:37.44#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.06:33:37.44#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:37.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:33:37.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:33:37.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:33:37.50#ibcon#enter wrdev, iclass 15, count 2 2006.285.06:33:37.50#ibcon#first serial, iclass 15, count 2 2006.285.06:33:37.50#ibcon#enter sib2, iclass 15, count 2 2006.285.06:33:37.50#ibcon#flushed, iclass 15, count 2 2006.285.06:33:37.50#ibcon#about to write, iclass 15, count 2 2006.285.06:33:37.50#ibcon#wrote, iclass 15, count 2 2006.285.06:33:37.50#ibcon#about to read 3, iclass 15, count 2 2006.285.06:33:37.52#ibcon#read 3, iclass 15, count 2 2006.285.06:33:37.52#ibcon#about to read 4, iclass 15, count 2 2006.285.06:33:37.52#ibcon#read 4, iclass 15, count 2 2006.285.06:33:37.52#ibcon#about to read 5, iclass 15, count 2 2006.285.06:33:37.52#ibcon#read 5, iclass 15, count 2 2006.285.06:33:37.52#ibcon#about to read 6, iclass 15, count 2 2006.285.06:33:37.52#ibcon#read 6, iclass 15, count 2 2006.285.06:33:37.52#ibcon#end of sib2, iclass 15, count 2 2006.285.06:33:37.52#ibcon#*mode == 0, iclass 15, count 2 2006.285.06:33:37.52#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.06:33:37.52#ibcon#[27=AT04-05\r\n] 2006.285.06:33:37.52#ibcon#*before write, iclass 15, count 2 2006.285.06:33:37.52#ibcon#enter sib2, iclass 15, count 2 2006.285.06:33:37.52#ibcon#flushed, iclass 15, count 2 2006.285.06:33:37.52#ibcon#about to write, iclass 15, count 2 2006.285.06:33:37.52#ibcon#wrote, iclass 15, count 2 2006.285.06:33:37.52#ibcon#about to read 3, iclass 15, count 2 2006.285.06:33:37.55#ibcon#read 3, iclass 15, count 2 2006.285.06:33:37.55#ibcon#about to read 4, iclass 15, count 2 2006.285.06:33:37.55#ibcon#read 4, iclass 15, count 2 2006.285.06:33:37.55#ibcon#about to read 5, iclass 15, count 2 2006.285.06:33:37.55#ibcon#read 5, iclass 15, count 2 2006.285.06:33:37.55#ibcon#about to read 6, iclass 15, count 2 2006.285.06:33:37.55#ibcon#read 6, iclass 15, count 2 2006.285.06:33:37.55#ibcon#end of sib2, iclass 15, count 2 2006.285.06:33:37.55#ibcon#*after write, iclass 15, count 2 2006.285.06:33:37.55#ibcon#*before return 0, iclass 15, count 2 2006.285.06:33:37.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:33:37.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.06:33:37.55#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.06:33:37.55#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:37.55#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:33:37.67#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:33:37.67#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:33:37.67#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:33:37.67#ibcon#first serial, iclass 15, count 0 2006.285.06:33:37.67#ibcon#enter sib2, iclass 15, count 0 2006.285.06:33:37.67#ibcon#flushed, iclass 15, count 0 2006.285.06:33:37.67#ibcon#about to write, iclass 15, count 0 2006.285.06:33:37.67#ibcon#wrote, iclass 15, count 0 2006.285.06:33:37.67#ibcon#about to read 3, iclass 15, count 0 2006.285.06:33:37.69#ibcon#read 3, iclass 15, count 0 2006.285.06:33:37.69#ibcon#about to read 4, iclass 15, count 0 2006.285.06:33:37.69#ibcon#read 4, iclass 15, count 0 2006.285.06:33:37.69#ibcon#about to read 5, iclass 15, count 0 2006.285.06:33:37.69#ibcon#read 5, iclass 15, count 0 2006.285.06:33:37.69#ibcon#about to read 6, iclass 15, count 0 2006.285.06:33:37.69#ibcon#read 6, iclass 15, count 0 2006.285.06:33:37.69#ibcon#end of sib2, iclass 15, count 0 2006.285.06:33:37.69#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:33:37.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:33:37.69#ibcon#[27=USB\r\n] 2006.285.06:33:37.69#ibcon#*before write, iclass 15, count 0 2006.285.06:33:37.69#ibcon#enter sib2, iclass 15, count 0 2006.285.06:33:37.69#ibcon#flushed, iclass 15, count 0 2006.285.06:33:37.69#ibcon#about to write, iclass 15, count 0 2006.285.06:33:37.69#ibcon#wrote, iclass 15, count 0 2006.285.06:33:37.69#ibcon#about to read 3, iclass 15, count 0 2006.285.06:33:37.72#ibcon#read 3, iclass 15, count 0 2006.285.06:33:37.72#ibcon#about to read 4, iclass 15, count 0 2006.285.06:33:37.72#ibcon#read 4, iclass 15, count 0 2006.285.06:33:37.72#ibcon#about to read 5, iclass 15, count 0 2006.285.06:33:37.72#ibcon#read 5, iclass 15, count 0 2006.285.06:33:37.72#ibcon#about to read 6, iclass 15, count 0 2006.285.06:33:37.72#ibcon#read 6, iclass 15, count 0 2006.285.06:33:37.72#ibcon#end of sib2, iclass 15, count 0 2006.285.06:33:37.72#ibcon#*after write, iclass 15, count 0 2006.285.06:33:37.72#ibcon#*before return 0, iclass 15, count 0 2006.285.06:33:37.72#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:33:37.72#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.06:33:37.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:33:37.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:33:37.72$vck44/vblo=5,709.99 2006.285.06:33:37.72#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.06:33:37.72#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.06:33:37.72#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:37.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:33:37.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:33:37.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:33:37.72#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:33:37.72#ibcon#first serial, iclass 17, count 0 2006.285.06:33:37.72#ibcon#enter sib2, iclass 17, count 0 2006.285.06:33:37.72#ibcon#flushed, iclass 17, count 0 2006.285.06:33:37.72#ibcon#about to write, iclass 17, count 0 2006.285.06:33:37.72#ibcon#wrote, iclass 17, count 0 2006.285.06:33:37.72#ibcon#about to read 3, iclass 17, count 0 2006.285.06:33:37.74#ibcon#read 3, iclass 17, count 0 2006.285.06:33:37.74#ibcon#about to read 4, iclass 17, count 0 2006.285.06:33:37.74#ibcon#read 4, iclass 17, count 0 2006.285.06:33:37.74#ibcon#about to read 5, iclass 17, count 0 2006.285.06:33:37.74#ibcon#read 5, iclass 17, count 0 2006.285.06:33:37.74#ibcon#about to read 6, iclass 17, count 0 2006.285.06:33:37.74#ibcon#read 6, iclass 17, count 0 2006.285.06:33:37.74#ibcon#end of sib2, iclass 17, count 0 2006.285.06:33:37.74#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:33:37.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:33:37.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:33:37.74#ibcon#*before write, iclass 17, count 0 2006.285.06:33:37.74#ibcon#enter sib2, iclass 17, count 0 2006.285.06:33:37.74#ibcon#flushed, iclass 17, count 0 2006.285.06:33:37.74#ibcon#about to write, iclass 17, count 0 2006.285.06:33:37.74#ibcon#wrote, iclass 17, count 0 2006.285.06:33:37.74#ibcon#about to read 3, iclass 17, count 0 2006.285.06:33:37.78#ibcon#read 3, iclass 17, count 0 2006.285.06:33:37.78#ibcon#about to read 4, iclass 17, count 0 2006.285.06:33:37.78#ibcon#read 4, iclass 17, count 0 2006.285.06:33:37.78#ibcon#about to read 5, iclass 17, count 0 2006.285.06:33:37.78#ibcon#read 5, iclass 17, count 0 2006.285.06:33:37.78#ibcon#about to read 6, iclass 17, count 0 2006.285.06:33:37.78#ibcon#read 6, iclass 17, count 0 2006.285.06:33:37.78#ibcon#end of sib2, iclass 17, count 0 2006.285.06:33:37.78#ibcon#*after write, iclass 17, count 0 2006.285.06:33:37.78#ibcon#*before return 0, iclass 17, count 0 2006.285.06:33:37.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:33:37.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.06:33:37.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:33:37.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:33:37.78$vck44/vb=5,4 2006.285.06:33:37.78#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.06:33:37.78#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.06:33:37.78#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:37.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:33:37.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:33:37.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:33:37.84#ibcon#enter wrdev, iclass 19, count 2 2006.285.06:33:37.84#ibcon#first serial, iclass 19, count 2 2006.285.06:33:37.84#ibcon#enter sib2, iclass 19, count 2 2006.285.06:33:37.84#ibcon#flushed, iclass 19, count 2 2006.285.06:33:37.84#ibcon#about to write, iclass 19, count 2 2006.285.06:33:37.84#ibcon#wrote, iclass 19, count 2 2006.285.06:33:37.84#ibcon#about to read 3, iclass 19, count 2 2006.285.06:33:37.86#ibcon#read 3, iclass 19, count 2 2006.285.06:33:37.86#ibcon#about to read 4, iclass 19, count 2 2006.285.06:33:37.86#ibcon#read 4, iclass 19, count 2 2006.285.06:33:37.86#ibcon#about to read 5, iclass 19, count 2 2006.285.06:33:37.86#ibcon#read 5, iclass 19, count 2 2006.285.06:33:37.86#ibcon#about to read 6, iclass 19, count 2 2006.285.06:33:37.86#ibcon#read 6, iclass 19, count 2 2006.285.06:33:37.86#ibcon#end of sib2, iclass 19, count 2 2006.285.06:33:37.86#ibcon#*mode == 0, iclass 19, count 2 2006.285.06:33:37.86#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.06:33:37.86#ibcon#[27=AT05-04\r\n] 2006.285.06:33:37.86#ibcon#*before write, iclass 19, count 2 2006.285.06:33:37.86#ibcon#enter sib2, iclass 19, count 2 2006.285.06:33:37.86#ibcon#flushed, iclass 19, count 2 2006.285.06:33:37.86#ibcon#about to write, iclass 19, count 2 2006.285.06:33:37.86#ibcon#wrote, iclass 19, count 2 2006.285.06:33:37.86#ibcon#about to read 3, iclass 19, count 2 2006.285.06:33:37.89#ibcon#read 3, iclass 19, count 2 2006.285.06:33:37.89#ibcon#about to read 4, iclass 19, count 2 2006.285.06:33:37.89#ibcon#read 4, iclass 19, count 2 2006.285.06:33:37.89#ibcon#about to read 5, iclass 19, count 2 2006.285.06:33:37.89#ibcon#read 5, iclass 19, count 2 2006.285.06:33:37.89#ibcon#about to read 6, iclass 19, count 2 2006.285.06:33:37.89#ibcon#read 6, iclass 19, count 2 2006.285.06:33:37.89#ibcon#end of sib2, iclass 19, count 2 2006.285.06:33:37.89#ibcon#*after write, iclass 19, count 2 2006.285.06:33:37.89#ibcon#*before return 0, iclass 19, count 2 2006.285.06:33:37.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:33:37.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.06:33:37.89#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.06:33:37.89#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:37.89#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:33:38.01#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:33:38.01#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:33:38.01#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:33:38.01#ibcon#first serial, iclass 19, count 0 2006.285.06:33:38.01#ibcon#enter sib2, iclass 19, count 0 2006.285.06:33:38.01#ibcon#flushed, iclass 19, count 0 2006.285.06:33:38.01#ibcon#about to write, iclass 19, count 0 2006.285.06:33:38.01#ibcon#wrote, iclass 19, count 0 2006.285.06:33:38.01#ibcon#about to read 3, iclass 19, count 0 2006.285.06:33:38.03#ibcon#read 3, iclass 19, count 0 2006.285.06:33:38.03#ibcon#about to read 4, iclass 19, count 0 2006.285.06:33:38.03#ibcon#read 4, iclass 19, count 0 2006.285.06:33:38.03#ibcon#about to read 5, iclass 19, count 0 2006.285.06:33:38.03#ibcon#read 5, iclass 19, count 0 2006.285.06:33:38.03#ibcon#about to read 6, iclass 19, count 0 2006.285.06:33:38.03#ibcon#read 6, iclass 19, count 0 2006.285.06:33:38.03#ibcon#end of sib2, iclass 19, count 0 2006.285.06:33:38.03#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:33:38.03#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:33:38.03#ibcon#[27=USB\r\n] 2006.285.06:33:38.03#ibcon#*before write, iclass 19, count 0 2006.285.06:33:38.03#ibcon#enter sib2, iclass 19, count 0 2006.285.06:33:38.03#ibcon#flushed, iclass 19, count 0 2006.285.06:33:38.03#ibcon#about to write, iclass 19, count 0 2006.285.06:33:38.03#ibcon#wrote, iclass 19, count 0 2006.285.06:33:38.03#ibcon#about to read 3, iclass 19, count 0 2006.285.06:33:38.06#ibcon#read 3, iclass 19, count 0 2006.285.06:33:38.06#ibcon#about to read 4, iclass 19, count 0 2006.285.06:33:38.06#ibcon#read 4, iclass 19, count 0 2006.285.06:33:38.06#ibcon#about to read 5, iclass 19, count 0 2006.285.06:33:38.06#ibcon#read 5, iclass 19, count 0 2006.285.06:33:38.06#ibcon#about to read 6, iclass 19, count 0 2006.285.06:33:38.06#ibcon#read 6, iclass 19, count 0 2006.285.06:33:38.06#ibcon#end of sib2, iclass 19, count 0 2006.285.06:33:38.06#ibcon#*after write, iclass 19, count 0 2006.285.06:33:38.06#ibcon#*before return 0, iclass 19, count 0 2006.285.06:33:38.06#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:33:38.06#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.06:33:38.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:33:38.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:33:38.06$vck44/vblo=6,719.99 2006.285.06:33:38.06#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.06:33:38.06#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.06:33:38.06#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:38.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:33:38.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:33:38.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:33:38.06#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:33:38.06#ibcon#first serial, iclass 21, count 0 2006.285.06:33:38.06#ibcon#enter sib2, iclass 21, count 0 2006.285.06:33:38.06#ibcon#flushed, iclass 21, count 0 2006.285.06:33:38.06#ibcon#about to write, iclass 21, count 0 2006.285.06:33:38.06#ibcon#wrote, iclass 21, count 0 2006.285.06:33:38.06#ibcon#about to read 3, iclass 21, count 0 2006.285.06:33:38.08#ibcon#read 3, iclass 21, count 0 2006.285.06:33:38.08#ibcon#about to read 4, iclass 21, count 0 2006.285.06:33:38.08#ibcon#read 4, iclass 21, count 0 2006.285.06:33:38.08#ibcon#about to read 5, iclass 21, count 0 2006.285.06:33:38.08#ibcon#read 5, iclass 21, count 0 2006.285.06:33:38.08#ibcon#about to read 6, iclass 21, count 0 2006.285.06:33:38.08#ibcon#read 6, iclass 21, count 0 2006.285.06:33:38.08#ibcon#end of sib2, iclass 21, count 0 2006.285.06:33:38.08#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:33:38.08#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:33:38.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:33:38.08#ibcon#*before write, iclass 21, count 0 2006.285.06:33:38.08#ibcon#enter sib2, iclass 21, count 0 2006.285.06:33:38.08#ibcon#flushed, iclass 21, count 0 2006.285.06:33:38.08#ibcon#about to write, iclass 21, count 0 2006.285.06:33:38.08#ibcon#wrote, iclass 21, count 0 2006.285.06:33:38.08#ibcon#about to read 3, iclass 21, count 0 2006.285.06:33:38.12#ibcon#read 3, iclass 21, count 0 2006.285.06:33:38.12#ibcon#about to read 4, iclass 21, count 0 2006.285.06:33:38.12#ibcon#read 4, iclass 21, count 0 2006.285.06:33:38.12#ibcon#about to read 5, iclass 21, count 0 2006.285.06:33:38.12#ibcon#read 5, iclass 21, count 0 2006.285.06:33:38.12#ibcon#about to read 6, iclass 21, count 0 2006.285.06:33:38.12#ibcon#read 6, iclass 21, count 0 2006.285.06:33:38.12#ibcon#end of sib2, iclass 21, count 0 2006.285.06:33:38.12#ibcon#*after write, iclass 21, count 0 2006.285.06:33:38.12#ibcon#*before return 0, iclass 21, count 0 2006.285.06:33:38.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:33:38.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.06:33:38.12#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:33:38.12#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:33:38.12$vck44/vb=6,3 2006.285.06:33:38.12#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.06:33:38.12#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.06:33:38.12#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:38.12#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:33:38.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:33:38.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:33:38.18#ibcon#enter wrdev, iclass 23, count 2 2006.285.06:33:38.18#ibcon#first serial, iclass 23, count 2 2006.285.06:33:38.18#ibcon#enter sib2, iclass 23, count 2 2006.285.06:33:38.18#ibcon#flushed, iclass 23, count 2 2006.285.06:33:38.18#ibcon#about to write, iclass 23, count 2 2006.285.06:33:38.18#ibcon#wrote, iclass 23, count 2 2006.285.06:33:38.18#ibcon#about to read 3, iclass 23, count 2 2006.285.06:33:38.20#ibcon#read 3, iclass 23, count 2 2006.285.06:33:38.20#ibcon#about to read 4, iclass 23, count 2 2006.285.06:33:38.20#ibcon#read 4, iclass 23, count 2 2006.285.06:33:38.20#ibcon#about to read 5, iclass 23, count 2 2006.285.06:33:38.20#ibcon#read 5, iclass 23, count 2 2006.285.06:33:38.20#ibcon#about to read 6, iclass 23, count 2 2006.285.06:33:38.20#ibcon#read 6, iclass 23, count 2 2006.285.06:33:38.20#ibcon#end of sib2, iclass 23, count 2 2006.285.06:33:38.20#ibcon#*mode == 0, iclass 23, count 2 2006.285.06:33:38.20#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.06:33:38.20#ibcon#[27=AT06-03\r\n] 2006.285.06:33:38.20#ibcon#*before write, iclass 23, count 2 2006.285.06:33:38.20#ibcon#enter sib2, iclass 23, count 2 2006.285.06:33:38.20#ibcon#flushed, iclass 23, count 2 2006.285.06:33:38.20#ibcon#about to write, iclass 23, count 2 2006.285.06:33:38.20#ibcon#wrote, iclass 23, count 2 2006.285.06:33:38.20#ibcon#about to read 3, iclass 23, count 2 2006.285.06:33:38.23#ibcon#read 3, iclass 23, count 2 2006.285.06:33:38.23#ibcon#about to read 4, iclass 23, count 2 2006.285.06:33:38.23#ibcon#read 4, iclass 23, count 2 2006.285.06:33:38.23#ibcon#about to read 5, iclass 23, count 2 2006.285.06:33:38.23#ibcon#read 5, iclass 23, count 2 2006.285.06:33:38.23#ibcon#about to read 6, iclass 23, count 2 2006.285.06:33:38.23#ibcon#read 6, iclass 23, count 2 2006.285.06:33:38.23#ibcon#end of sib2, iclass 23, count 2 2006.285.06:33:38.23#ibcon#*after write, iclass 23, count 2 2006.285.06:33:38.23#ibcon#*before return 0, iclass 23, count 2 2006.285.06:33:38.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:33:38.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.06:33:38.23#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.06:33:38.23#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:38.23#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:33:38.35#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:33:38.35#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:33:38.35#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:33:38.35#ibcon#first serial, iclass 23, count 0 2006.285.06:33:38.35#ibcon#enter sib2, iclass 23, count 0 2006.285.06:33:38.35#ibcon#flushed, iclass 23, count 0 2006.285.06:33:38.35#ibcon#about to write, iclass 23, count 0 2006.285.06:33:38.35#ibcon#wrote, iclass 23, count 0 2006.285.06:33:38.35#ibcon#about to read 3, iclass 23, count 0 2006.285.06:33:38.37#ibcon#read 3, iclass 23, count 0 2006.285.06:33:38.37#ibcon#about to read 4, iclass 23, count 0 2006.285.06:33:38.37#ibcon#read 4, iclass 23, count 0 2006.285.06:33:38.37#ibcon#about to read 5, iclass 23, count 0 2006.285.06:33:38.37#ibcon#read 5, iclass 23, count 0 2006.285.06:33:38.37#ibcon#about to read 6, iclass 23, count 0 2006.285.06:33:38.37#ibcon#read 6, iclass 23, count 0 2006.285.06:33:38.37#ibcon#end of sib2, iclass 23, count 0 2006.285.06:33:38.37#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:33:38.37#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:33:38.37#ibcon#[27=USB\r\n] 2006.285.06:33:38.37#ibcon#*before write, iclass 23, count 0 2006.285.06:33:38.37#ibcon#enter sib2, iclass 23, count 0 2006.285.06:33:38.37#ibcon#flushed, iclass 23, count 0 2006.285.06:33:38.37#ibcon#about to write, iclass 23, count 0 2006.285.06:33:38.37#ibcon#wrote, iclass 23, count 0 2006.285.06:33:38.37#ibcon#about to read 3, iclass 23, count 0 2006.285.06:33:38.40#ibcon#read 3, iclass 23, count 0 2006.285.06:33:38.40#ibcon#about to read 4, iclass 23, count 0 2006.285.06:33:38.40#ibcon#read 4, iclass 23, count 0 2006.285.06:33:38.40#ibcon#about to read 5, iclass 23, count 0 2006.285.06:33:38.40#ibcon#read 5, iclass 23, count 0 2006.285.06:33:38.40#ibcon#about to read 6, iclass 23, count 0 2006.285.06:33:38.40#ibcon#read 6, iclass 23, count 0 2006.285.06:33:38.40#ibcon#end of sib2, iclass 23, count 0 2006.285.06:33:38.40#ibcon#*after write, iclass 23, count 0 2006.285.06:33:38.40#ibcon#*before return 0, iclass 23, count 0 2006.285.06:33:38.40#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:33:38.40#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.06:33:38.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:33:38.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:33:38.40$vck44/vblo=7,734.99 2006.285.06:33:38.40#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.06:33:38.40#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.06:33:38.40#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:38.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:33:38.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:33:38.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:33:38.40#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:33:38.40#ibcon#first serial, iclass 25, count 0 2006.285.06:33:38.40#ibcon#enter sib2, iclass 25, count 0 2006.285.06:33:38.40#ibcon#flushed, iclass 25, count 0 2006.285.06:33:38.40#ibcon#about to write, iclass 25, count 0 2006.285.06:33:38.40#ibcon#wrote, iclass 25, count 0 2006.285.06:33:38.40#ibcon#about to read 3, iclass 25, count 0 2006.285.06:33:38.42#ibcon#read 3, iclass 25, count 0 2006.285.06:33:38.42#ibcon#about to read 4, iclass 25, count 0 2006.285.06:33:38.42#ibcon#read 4, iclass 25, count 0 2006.285.06:33:38.42#ibcon#about to read 5, iclass 25, count 0 2006.285.06:33:38.42#ibcon#read 5, iclass 25, count 0 2006.285.06:33:38.42#ibcon#about to read 6, iclass 25, count 0 2006.285.06:33:38.42#ibcon#read 6, iclass 25, count 0 2006.285.06:33:38.42#ibcon#end of sib2, iclass 25, count 0 2006.285.06:33:38.42#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:33:38.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:33:38.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:33:38.42#ibcon#*before write, iclass 25, count 0 2006.285.06:33:38.42#ibcon#enter sib2, iclass 25, count 0 2006.285.06:33:38.42#ibcon#flushed, iclass 25, count 0 2006.285.06:33:38.42#ibcon#about to write, iclass 25, count 0 2006.285.06:33:38.42#ibcon#wrote, iclass 25, count 0 2006.285.06:33:38.42#ibcon#about to read 3, iclass 25, count 0 2006.285.06:33:38.46#ibcon#read 3, iclass 25, count 0 2006.285.06:33:38.46#ibcon#about to read 4, iclass 25, count 0 2006.285.06:33:38.46#ibcon#read 4, iclass 25, count 0 2006.285.06:33:38.46#ibcon#about to read 5, iclass 25, count 0 2006.285.06:33:38.46#ibcon#read 5, iclass 25, count 0 2006.285.06:33:38.46#ibcon#about to read 6, iclass 25, count 0 2006.285.06:33:38.46#ibcon#read 6, iclass 25, count 0 2006.285.06:33:38.46#ibcon#end of sib2, iclass 25, count 0 2006.285.06:33:38.46#ibcon#*after write, iclass 25, count 0 2006.285.06:33:38.46#ibcon#*before return 0, iclass 25, count 0 2006.285.06:33:38.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:33:38.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.06:33:38.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:33:38.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:33:38.46$vck44/vb=7,4 2006.285.06:33:38.46#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.06:33:38.46#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.06:33:38.46#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:38.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:33:38.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:33:38.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:33:38.52#ibcon#enter wrdev, iclass 27, count 2 2006.285.06:33:38.52#ibcon#first serial, iclass 27, count 2 2006.285.06:33:38.52#ibcon#enter sib2, iclass 27, count 2 2006.285.06:33:38.52#ibcon#flushed, iclass 27, count 2 2006.285.06:33:38.52#ibcon#about to write, iclass 27, count 2 2006.285.06:33:38.52#ibcon#wrote, iclass 27, count 2 2006.285.06:33:38.52#ibcon#about to read 3, iclass 27, count 2 2006.285.06:33:38.54#ibcon#read 3, iclass 27, count 2 2006.285.06:33:38.54#ibcon#about to read 4, iclass 27, count 2 2006.285.06:33:38.54#ibcon#read 4, iclass 27, count 2 2006.285.06:33:38.54#ibcon#about to read 5, iclass 27, count 2 2006.285.06:33:38.54#ibcon#read 5, iclass 27, count 2 2006.285.06:33:38.54#ibcon#about to read 6, iclass 27, count 2 2006.285.06:33:38.54#ibcon#read 6, iclass 27, count 2 2006.285.06:33:38.54#ibcon#end of sib2, iclass 27, count 2 2006.285.06:33:38.54#ibcon#*mode == 0, iclass 27, count 2 2006.285.06:33:38.54#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.06:33:38.54#ibcon#[27=AT07-04\r\n] 2006.285.06:33:38.54#ibcon#*before write, iclass 27, count 2 2006.285.06:33:38.54#ibcon#enter sib2, iclass 27, count 2 2006.285.06:33:38.54#ibcon#flushed, iclass 27, count 2 2006.285.06:33:38.54#ibcon#about to write, iclass 27, count 2 2006.285.06:33:38.54#ibcon#wrote, iclass 27, count 2 2006.285.06:33:38.54#ibcon#about to read 3, iclass 27, count 2 2006.285.06:33:38.57#ibcon#read 3, iclass 27, count 2 2006.285.06:33:38.57#ibcon#about to read 4, iclass 27, count 2 2006.285.06:33:38.57#ibcon#read 4, iclass 27, count 2 2006.285.06:33:38.57#ibcon#about to read 5, iclass 27, count 2 2006.285.06:33:38.57#ibcon#read 5, iclass 27, count 2 2006.285.06:33:38.57#ibcon#about to read 6, iclass 27, count 2 2006.285.06:33:38.57#ibcon#read 6, iclass 27, count 2 2006.285.06:33:38.57#ibcon#end of sib2, iclass 27, count 2 2006.285.06:33:38.57#ibcon#*after write, iclass 27, count 2 2006.285.06:33:38.57#ibcon#*before return 0, iclass 27, count 2 2006.285.06:33:38.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:33:38.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.06:33:38.57#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.06:33:38.57#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:38.57#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:33:38.69#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:33:38.69#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:33:38.69#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:33:38.69#ibcon#first serial, iclass 27, count 0 2006.285.06:33:38.69#ibcon#enter sib2, iclass 27, count 0 2006.285.06:33:38.69#ibcon#flushed, iclass 27, count 0 2006.285.06:33:38.69#ibcon#about to write, iclass 27, count 0 2006.285.06:33:38.69#ibcon#wrote, iclass 27, count 0 2006.285.06:33:38.69#ibcon#about to read 3, iclass 27, count 0 2006.285.06:33:38.71#ibcon#read 3, iclass 27, count 0 2006.285.06:33:38.71#ibcon#about to read 4, iclass 27, count 0 2006.285.06:33:38.71#ibcon#read 4, iclass 27, count 0 2006.285.06:33:38.71#ibcon#about to read 5, iclass 27, count 0 2006.285.06:33:38.71#ibcon#read 5, iclass 27, count 0 2006.285.06:33:38.71#ibcon#about to read 6, iclass 27, count 0 2006.285.06:33:38.71#ibcon#read 6, iclass 27, count 0 2006.285.06:33:38.71#ibcon#end of sib2, iclass 27, count 0 2006.285.06:33:38.71#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:33:38.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:33:38.71#ibcon#[27=USB\r\n] 2006.285.06:33:38.71#ibcon#*before write, iclass 27, count 0 2006.285.06:33:38.71#ibcon#enter sib2, iclass 27, count 0 2006.285.06:33:38.71#ibcon#flushed, iclass 27, count 0 2006.285.06:33:38.71#ibcon#about to write, iclass 27, count 0 2006.285.06:33:38.71#ibcon#wrote, iclass 27, count 0 2006.285.06:33:38.71#ibcon#about to read 3, iclass 27, count 0 2006.285.06:33:38.74#ibcon#read 3, iclass 27, count 0 2006.285.06:33:38.74#ibcon#about to read 4, iclass 27, count 0 2006.285.06:33:38.74#ibcon#read 4, iclass 27, count 0 2006.285.06:33:38.74#ibcon#about to read 5, iclass 27, count 0 2006.285.06:33:38.74#ibcon#read 5, iclass 27, count 0 2006.285.06:33:38.74#ibcon#about to read 6, iclass 27, count 0 2006.285.06:33:38.74#ibcon#read 6, iclass 27, count 0 2006.285.06:33:38.74#ibcon#end of sib2, iclass 27, count 0 2006.285.06:33:38.74#ibcon#*after write, iclass 27, count 0 2006.285.06:33:38.74#ibcon#*before return 0, iclass 27, count 0 2006.285.06:33:38.74#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:33:38.74#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.06:33:38.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:33:38.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:33:38.74$vck44/vblo=8,744.99 2006.285.06:33:38.74#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.06:33:38.74#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.06:33:38.74#ibcon#ireg 17 cls_cnt 0 2006.285.06:33:38.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:33:38.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:33:38.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:33:38.74#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:33:38.74#ibcon#first serial, iclass 29, count 0 2006.285.06:33:38.74#ibcon#enter sib2, iclass 29, count 0 2006.285.06:33:38.74#ibcon#flushed, iclass 29, count 0 2006.285.06:33:38.74#ibcon#about to write, iclass 29, count 0 2006.285.06:33:38.74#ibcon#wrote, iclass 29, count 0 2006.285.06:33:38.74#ibcon#about to read 3, iclass 29, count 0 2006.285.06:33:38.76#ibcon#read 3, iclass 29, count 0 2006.285.06:33:38.76#ibcon#about to read 4, iclass 29, count 0 2006.285.06:33:38.76#ibcon#read 4, iclass 29, count 0 2006.285.06:33:38.76#ibcon#about to read 5, iclass 29, count 0 2006.285.06:33:38.76#ibcon#read 5, iclass 29, count 0 2006.285.06:33:38.76#ibcon#about to read 6, iclass 29, count 0 2006.285.06:33:38.76#ibcon#read 6, iclass 29, count 0 2006.285.06:33:38.76#ibcon#end of sib2, iclass 29, count 0 2006.285.06:33:38.76#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:33:38.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:33:38.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:33:38.76#ibcon#*before write, iclass 29, count 0 2006.285.06:33:38.76#ibcon#enter sib2, iclass 29, count 0 2006.285.06:33:38.76#ibcon#flushed, iclass 29, count 0 2006.285.06:33:38.76#ibcon#about to write, iclass 29, count 0 2006.285.06:33:38.76#ibcon#wrote, iclass 29, count 0 2006.285.06:33:38.76#ibcon#about to read 3, iclass 29, count 0 2006.285.06:33:38.80#ibcon#read 3, iclass 29, count 0 2006.285.06:33:38.80#ibcon#about to read 4, iclass 29, count 0 2006.285.06:33:38.80#ibcon#read 4, iclass 29, count 0 2006.285.06:33:38.80#ibcon#about to read 5, iclass 29, count 0 2006.285.06:33:38.80#ibcon#read 5, iclass 29, count 0 2006.285.06:33:38.80#ibcon#about to read 6, iclass 29, count 0 2006.285.06:33:38.80#ibcon#read 6, iclass 29, count 0 2006.285.06:33:38.80#ibcon#end of sib2, iclass 29, count 0 2006.285.06:33:38.80#ibcon#*after write, iclass 29, count 0 2006.285.06:33:38.80#ibcon#*before return 0, iclass 29, count 0 2006.285.06:33:38.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:33:38.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.06:33:38.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:33:38.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:33:38.80$vck44/vb=8,4 2006.285.06:33:38.80#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.06:33:38.80#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.06:33:38.80#ibcon#ireg 11 cls_cnt 2 2006.285.06:33:38.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:33:38.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:33:38.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:33:38.86#ibcon#enter wrdev, iclass 31, count 2 2006.285.06:33:38.86#ibcon#first serial, iclass 31, count 2 2006.285.06:33:38.86#ibcon#enter sib2, iclass 31, count 2 2006.285.06:33:38.86#ibcon#flushed, iclass 31, count 2 2006.285.06:33:38.86#ibcon#about to write, iclass 31, count 2 2006.285.06:33:38.86#ibcon#wrote, iclass 31, count 2 2006.285.06:33:38.86#ibcon#about to read 3, iclass 31, count 2 2006.285.06:33:38.88#ibcon#read 3, iclass 31, count 2 2006.285.06:33:38.88#ibcon#about to read 4, iclass 31, count 2 2006.285.06:33:38.88#ibcon#read 4, iclass 31, count 2 2006.285.06:33:38.88#ibcon#about to read 5, iclass 31, count 2 2006.285.06:33:38.88#ibcon#read 5, iclass 31, count 2 2006.285.06:33:38.88#ibcon#about to read 6, iclass 31, count 2 2006.285.06:33:38.88#ibcon#read 6, iclass 31, count 2 2006.285.06:33:38.88#ibcon#end of sib2, iclass 31, count 2 2006.285.06:33:38.88#ibcon#*mode == 0, iclass 31, count 2 2006.285.06:33:38.88#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.06:33:38.88#ibcon#[27=AT08-04\r\n] 2006.285.06:33:38.88#ibcon#*before write, iclass 31, count 2 2006.285.06:33:38.88#ibcon#enter sib2, iclass 31, count 2 2006.285.06:33:38.88#ibcon#flushed, iclass 31, count 2 2006.285.06:33:38.88#ibcon#about to write, iclass 31, count 2 2006.285.06:33:38.88#ibcon#wrote, iclass 31, count 2 2006.285.06:33:38.88#ibcon#about to read 3, iclass 31, count 2 2006.285.06:33:38.91#ibcon#read 3, iclass 31, count 2 2006.285.06:33:38.91#ibcon#about to read 4, iclass 31, count 2 2006.285.06:33:38.91#ibcon#read 4, iclass 31, count 2 2006.285.06:33:38.91#ibcon#about to read 5, iclass 31, count 2 2006.285.06:33:38.91#ibcon#read 5, iclass 31, count 2 2006.285.06:33:38.91#ibcon#about to read 6, iclass 31, count 2 2006.285.06:33:38.91#ibcon#read 6, iclass 31, count 2 2006.285.06:33:38.91#ibcon#end of sib2, iclass 31, count 2 2006.285.06:33:38.91#ibcon#*after write, iclass 31, count 2 2006.285.06:33:38.91#ibcon#*before return 0, iclass 31, count 2 2006.285.06:33:38.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:33:38.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.06:33:38.91#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.06:33:38.91#ibcon#ireg 7 cls_cnt 0 2006.285.06:33:38.91#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:33:39.03#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:33:39.03#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:33:39.03#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:33:39.03#ibcon#first serial, iclass 31, count 0 2006.285.06:33:39.03#ibcon#enter sib2, iclass 31, count 0 2006.285.06:33:39.03#ibcon#flushed, iclass 31, count 0 2006.285.06:33:39.03#ibcon#about to write, iclass 31, count 0 2006.285.06:33:39.03#ibcon#wrote, iclass 31, count 0 2006.285.06:33:39.03#ibcon#about to read 3, iclass 31, count 0 2006.285.06:33:39.05#ibcon#read 3, iclass 31, count 0 2006.285.06:33:39.05#ibcon#about to read 4, iclass 31, count 0 2006.285.06:33:39.05#ibcon#read 4, iclass 31, count 0 2006.285.06:33:39.05#ibcon#about to read 5, iclass 31, count 0 2006.285.06:33:39.05#ibcon#read 5, iclass 31, count 0 2006.285.06:33:39.05#ibcon#about to read 6, iclass 31, count 0 2006.285.06:33:39.05#ibcon#read 6, iclass 31, count 0 2006.285.06:33:39.05#ibcon#end of sib2, iclass 31, count 0 2006.285.06:33:39.05#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:33:39.05#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:33:39.05#ibcon#[27=USB\r\n] 2006.285.06:33:39.05#ibcon#*before write, iclass 31, count 0 2006.285.06:33:39.05#ibcon#enter sib2, iclass 31, count 0 2006.285.06:33:39.05#ibcon#flushed, iclass 31, count 0 2006.285.06:33:39.05#ibcon#about to write, iclass 31, count 0 2006.285.06:33:39.05#ibcon#wrote, iclass 31, count 0 2006.285.06:33:39.05#ibcon#about to read 3, iclass 31, count 0 2006.285.06:33:39.08#ibcon#read 3, iclass 31, count 0 2006.285.06:33:39.08#ibcon#about to read 4, iclass 31, count 0 2006.285.06:33:39.08#ibcon#read 4, iclass 31, count 0 2006.285.06:33:39.08#ibcon#about to read 5, iclass 31, count 0 2006.285.06:33:39.08#ibcon#read 5, iclass 31, count 0 2006.285.06:33:39.08#ibcon#about to read 6, iclass 31, count 0 2006.285.06:33:39.08#ibcon#read 6, iclass 31, count 0 2006.285.06:33:39.08#ibcon#end of sib2, iclass 31, count 0 2006.285.06:33:39.08#ibcon#*after write, iclass 31, count 0 2006.285.06:33:39.08#ibcon#*before return 0, iclass 31, count 0 2006.285.06:33:39.08#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:33:39.08#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.06:33:39.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:33:39.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:33:39.08$vck44/vabw=wide 2006.285.06:33:39.08#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.06:33:39.08#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.06:33:39.08#ibcon#ireg 8 cls_cnt 0 2006.285.06:33:39.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:33:39.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:33:39.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:33:39.08#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:33:39.08#ibcon#first serial, iclass 33, count 0 2006.285.06:33:39.08#ibcon#enter sib2, iclass 33, count 0 2006.285.06:33:39.08#ibcon#flushed, iclass 33, count 0 2006.285.06:33:39.08#ibcon#about to write, iclass 33, count 0 2006.285.06:33:39.08#ibcon#wrote, iclass 33, count 0 2006.285.06:33:39.08#ibcon#about to read 3, iclass 33, count 0 2006.285.06:33:39.10#ibcon#read 3, iclass 33, count 0 2006.285.06:33:39.10#ibcon#about to read 4, iclass 33, count 0 2006.285.06:33:39.10#ibcon#read 4, iclass 33, count 0 2006.285.06:33:39.10#ibcon#about to read 5, iclass 33, count 0 2006.285.06:33:39.10#ibcon#read 5, iclass 33, count 0 2006.285.06:33:39.10#ibcon#about to read 6, iclass 33, count 0 2006.285.06:33:39.10#ibcon#read 6, iclass 33, count 0 2006.285.06:33:39.10#ibcon#end of sib2, iclass 33, count 0 2006.285.06:33:39.10#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:33:39.10#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:33:39.10#ibcon#[25=BW32\r\n] 2006.285.06:33:39.10#ibcon#*before write, iclass 33, count 0 2006.285.06:33:39.10#ibcon#enter sib2, iclass 33, count 0 2006.285.06:33:39.10#ibcon#flushed, iclass 33, count 0 2006.285.06:33:39.10#ibcon#about to write, iclass 33, count 0 2006.285.06:33:39.10#ibcon#wrote, iclass 33, count 0 2006.285.06:33:39.10#ibcon#about to read 3, iclass 33, count 0 2006.285.06:33:39.13#ibcon#read 3, iclass 33, count 0 2006.285.06:33:39.13#ibcon#about to read 4, iclass 33, count 0 2006.285.06:33:39.13#ibcon#read 4, iclass 33, count 0 2006.285.06:33:39.13#ibcon#about to read 5, iclass 33, count 0 2006.285.06:33:39.13#ibcon#read 5, iclass 33, count 0 2006.285.06:33:39.13#ibcon#about to read 6, iclass 33, count 0 2006.285.06:33:39.13#ibcon#read 6, iclass 33, count 0 2006.285.06:33:39.13#ibcon#end of sib2, iclass 33, count 0 2006.285.06:33:39.13#ibcon#*after write, iclass 33, count 0 2006.285.06:33:39.13#ibcon#*before return 0, iclass 33, count 0 2006.285.06:33:39.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:33:39.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.06:33:39.13#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:33:39.13#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:33:39.13$vck44/vbbw=wide 2006.285.06:33:39.13#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.06:33:39.13#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.06:33:39.13#ibcon#ireg 8 cls_cnt 0 2006.285.06:33:39.13#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:33:39.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:33:39.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:33:39.20#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:33:39.20#ibcon#first serial, iclass 35, count 0 2006.285.06:33:39.20#ibcon#enter sib2, iclass 35, count 0 2006.285.06:33:39.20#ibcon#flushed, iclass 35, count 0 2006.285.06:33:39.20#ibcon#about to write, iclass 35, count 0 2006.285.06:33:39.20#ibcon#wrote, iclass 35, count 0 2006.285.06:33:39.20#ibcon#about to read 3, iclass 35, count 0 2006.285.06:33:39.22#ibcon#read 3, iclass 35, count 0 2006.285.06:33:39.22#ibcon#about to read 4, iclass 35, count 0 2006.285.06:33:39.22#ibcon#read 4, iclass 35, count 0 2006.285.06:33:39.22#ibcon#about to read 5, iclass 35, count 0 2006.285.06:33:39.22#ibcon#read 5, iclass 35, count 0 2006.285.06:33:39.22#ibcon#about to read 6, iclass 35, count 0 2006.285.06:33:39.22#ibcon#read 6, iclass 35, count 0 2006.285.06:33:39.22#ibcon#end of sib2, iclass 35, count 0 2006.285.06:33:39.22#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:33:39.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:33:39.22#ibcon#[27=BW32\r\n] 2006.285.06:33:39.22#ibcon#*before write, iclass 35, count 0 2006.285.06:33:39.22#ibcon#enter sib2, iclass 35, count 0 2006.285.06:33:39.22#ibcon#flushed, iclass 35, count 0 2006.285.06:33:39.22#ibcon#about to write, iclass 35, count 0 2006.285.06:33:39.22#ibcon#wrote, iclass 35, count 0 2006.285.06:33:39.22#ibcon#about to read 3, iclass 35, count 0 2006.285.06:33:39.24#abcon#<5=/05 4.9 7.6 24.85 691014.1\r\n> 2006.285.06:33:39.25#ibcon#read 3, iclass 35, count 0 2006.285.06:33:39.25#ibcon#about to read 4, iclass 35, count 0 2006.285.06:33:39.25#ibcon#read 4, iclass 35, count 0 2006.285.06:33:39.25#ibcon#about to read 5, iclass 35, count 0 2006.285.06:33:39.25#ibcon#read 5, iclass 35, count 0 2006.285.06:33:39.25#ibcon#about to read 6, iclass 35, count 0 2006.285.06:33:39.25#ibcon#read 6, iclass 35, count 0 2006.285.06:33:39.25#ibcon#end of sib2, iclass 35, count 0 2006.285.06:33:39.25#ibcon#*after write, iclass 35, count 0 2006.285.06:33:39.25#ibcon#*before return 0, iclass 35, count 0 2006.285.06:33:39.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:33:39.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:33:39.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:33:39.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:33:39.25$setupk4/ifdk4 2006.285.06:33:39.25$ifdk4/lo= 2006.285.06:33:39.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:33:39.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:33:39.25$ifdk4/patch= 2006.285.06:33:39.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:33:39.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:33:39.25$setupk4/!*+20s 2006.285.06:33:39.26#abcon#{5=INTERFACE CLEAR} 2006.285.06:33:39.32#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:33:45.14#trakl#Source acquired 2006.285.06:33:47.14#flagr#flagr/antenna,acquired 2006.285.06:33:49.41#abcon#<5=/05 4.9 7.6 24.85 691014.1\r\n> 2006.285.06:33:49.43#abcon#{5=INTERFACE CLEAR} 2006.285.06:33:49.49#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:33:53.76$setupk4/"tpicd 2006.285.06:33:53.76$setupk4/echo=off 2006.285.06:33:53.76$setupk4/xlog=off 2006.285.06:33:53.76:!2006.285.06:36:30 2006.285.06:36:30.00:preob 2006.285.06:36:30.14/onsource/TRACKING 2006.285.06:36:30.14:!2006.285.06:36:40 2006.285.06:36:40.00:"tape 2006.285.06:36:40.00:"st=record 2006.285.06:36:40.00:data_valid=on 2006.285.06:36:40.00:midob 2006.285.06:36:41.14/onsource/TRACKING 2006.285.06:36:41.14/wx/24.83,1014.1,70 2006.285.06:36:41.34/cable/+6.4734E-03 2006.285.06:36:42.43/va/01,07,usb,yes,32,35 2006.285.06:36:42.43/va/02,06,usb,yes,32,32 2006.285.06:36:42.43/va/03,07,usb,yes,31,33 2006.285.06:36:42.43/va/04,06,usb,yes,33,34 2006.285.06:36:42.43/va/05,03,usb,yes,32,33 2006.285.06:36:42.43/va/06,04,usb,yes,29,29 2006.285.06:36:42.43/va/07,04,usb,yes,30,30 2006.285.06:36:42.43/va/08,03,usb,yes,30,37 2006.285.06:36:42.66/valo/01,524.99,yes,locked 2006.285.06:36:42.66/valo/02,534.99,yes,locked 2006.285.06:36:42.66/valo/03,564.99,yes,locked 2006.285.06:36:42.66/valo/04,624.99,yes,locked 2006.285.06:36:42.66/valo/05,734.99,yes,locked 2006.285.06:36:42.66/valo/06,814.99,yes,locked 2006.285.06:36:42.66/valo/07,864.99,yes,locked 2006.285.06:36:42.66/valo/08,884.99,yes,locked 2006.285.06:36:43.75/vb/01,04,usb,yes,31,29 2006.285.06:36:43.75/vb/02,05,usb,yes,29,29 2006.285.06:36:43.75/vb/03,04,usb,yes,30,33 2006.285.06:36:43.75/vb/04,05,usb,yes,30,29 2006.285.06:36:43.75/vb/05,04,usb,yes,27,29 2006.285.06:36:43.75/vb/06,03,usb,yes,38,34 2006.285.06:36:43.75/vb/07,04,usb,yes,31,31 2006.285.06:36:43.75/vb/08,04,usb,yes,28,32 2006.285.06:36:43.99/vblo/01,629.99,yes,locked 2006.285.06:36:43.99/vblo/02,634.99,yes,locked 2006.285.06:36:43.99/vblo/03,649.99,yes,locked 2006.285.06:36:43.99/vblo/04,679.99,yes,locked 2006.285.06:36:43.99/vblo/05,709.99,yes,locked 2006.285.06:36:43.99/vblo/06,719.99,yes,locked 2006.285.06:36:43.99/vblo/07,734.99,yes,locked 2006.285.06:36:43.99/vblo/08,744.99,yes,locked 2006.285.06:36:44.14/vabw/8 2006.285.06:36:44.29/vbbw/8 2006.285.06:36:44.38/xfe/off,on,12.2 2006.285.06:36:44.80/ifatt/23,28,28,28 2006.285.06:36:45.07/fmout-gps/S +2.58E-07 2006.285.06:36:45.09:!2006.285.06:37:20 2006.285.06:37:20.00:data_valid=off 2006.285.06:37:20.00:"et 2006.285.06:37:20.00:!+3s 2006.285.06:37:23.01:"tape 2006.285.06:37:23.01:postob 2006.285.06:37:23.23/cable/+6.4741E-03 2006.285.06:37:23.23/wx/24.83,1014.1,70 2006.285.06:37:24.07/fmout-gps/S +2.56E-07 2006.285.06:37:24.07:scan_name=285-0639,jd0610,40 2006.285.06:37:24.07:source=3c454.3,225357.75,160853.6,2000.0,cw 2006.285.06:37:25.14#flagr#flagr/antenna,new-source 2006.285.06:37:25.14:checkk5 2006.285.06:37:25.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:37:25.91/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:37:26.41/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:37:26.78/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:37:27.26/chk_obsdata//k5ts1/T2850636??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:37:27.64/chk_obsdata//k5ts2/T2850636??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:37:28.02/chk_obsdata//k5ts3/T2850636??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:37:28.46/chk_obsdata//k5ts4/T2850636??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:37:29.40/k5log//k5ts1_log_newline 2006.285.06:37:30.18/k5log//k5ts2_log_newline 2006.285.06:37:31.02/k5log//k5ts3_log_newline 2006.285.06:37:31.83/k5log//k5ts4_log_newline 2006.285.06:37:31.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:37:31.85:setupk4=1 2006.285.06:37:31.85$setupk4/echo=on 2006.285.06:37:31.85$setupk4/pcalon 2006.285.06:37:31.85$pcalon/"no phase cal control is implemented here 2006.285.06:37:31.85$setupk4/"tpicd=stop 2006.285.06:37:31.85$setupk4/"rec=synch_on 2006.285.06:37:31.85$setupk4/"rec_mode=128 2006.285.06:37:31.85$setupk4/!* 2006.285.06:37:31.85$setupk4/recpk4 2006.285.06:37:31.85$recpk4/recpatch= 2006.285.06:37:31.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:37:31.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:37:31.86$setupk4/vck44 2006.285.06:37:31.86$vck44/valo=1,524.99 2006.285.06:37:31.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.06:37:31.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.06:37:31.86#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:31.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:37:31.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:37:31.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:37:31.86#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:37:31.86#ibcon#first serial, iclass 24, count 0 2006.285.06:37:31.86#ibcon#enter sib2, iclass 24, count 0 2006.285.06:37:31.86#ibcon#flushed, iclass 24, count 0 2006.285.06:37:31.86#ibcon#about to write, iclass 24, count 0 2006.285.06:37:31.86#ibcon#wrote, iclass 24, count 0 2006.285.06:37:31.86#ibcon#about to read 3, iclass 24, count 0 2006.285.06:37:31.87#ibcon#read 3, iclass 24, count 0 2006.285.06:37:31.87#ibcon#about to read 4, iclass 24, count 0 2006.285.06:37:31.87#ibcon#read 4, iclass 24, count 0 2006.285.06:37:31.87#ibcon#about to read 5, iclass 24, count 0 2006.285.06:37:31.87#ibcon#read 5, iclass 24, count 0 2006.285.06:37:31.87#ibcon#about to read 6, iclass 24, count 0 2006.285.06:37:31.87#ibcon#read 6, iclass 24, count 0 2006.285.06:37:31.87#ibcon#end of sib2, iclass 24, count 0 2006.285.06:37:31.87#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:37:31.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:37:31.87#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:37:31.87#ibcon#*before write, iclass 24, count 0 2006.285.06:37:31.87#ibcon#enter sib2, iclass 24, count 0 2006.285.06:37:31.87#ibcon#flushed, iclass 24, count 0 2006.285.06:37:31.87#ibcon#about to write, iclass 24, count 0 2006.285.06:37:31.87#ibcon#wrote, iclass 24, count 0 2006.285.06:37:31.87#ibcon#about to read 3, iclass 24, count 0 2006.285.06:37:31.92#ibcon#read 3, iclass 24, count 0 2006.285.06:37:31.92#ibcon#about to read 4, iclass 24, count 0 2006.285.06:37:31.92#ibcon#read 4, iclass 24, count 0 2006.285.06:37:31.92#ibcon#about to read 5, iclass 24, count 0 2006.285.06:37:31.92#ibcon#read 5, iclass 24, count 0 2006.285.06:37:31.92#ibcon#about to read 6, iclass 24, count 0 2006.285.06:37:31.92#ibcon#read 6, iclass 24, count 0 2006.285.06:37:31.92#ibcon#end of sib2, iclass 24, count 0 2006.285.06:37:31.92#ibcon#*after write, iclass 24, count 0 2006.285.06:37:31.92#ibcon#*before return 0, iclass 24, count 0 2006.285.06:37:31.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:37:31.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:37:31.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:37:31.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:37:31.92$vck44/va=1,7 2006.285.06:37:31.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.06:37:31.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.06:37:31.92#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:31.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:37:31.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:37:31.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:37:31.92#ibcon#enter wrdev, iclass 26, count 2 2006.285.06:37:31.92#ibcon#first serial, iclass 26, count 2 2006.285.06:37:31.92#ibcon#enter sib2, iclass 26, count 2 2006.285.06:37:31.92#ibcon#flushed, iclass 26, count 2 2006.285.06:37:31.92#ibcon#about to write, iclass 26, count 2 2006.285.06:37:31.92#ibcon#wrote, iclass 26, count 2 2006.285.06:37:31.92#ibcon#about to read 3, iclass 26, count 2 2006.285.06:37:31.94#ibcon#read 3, iclass 26, count 2 2006.285.06:37:31.94#ibcon#about to read 4, iclass 26, count 2 2006.285.06:37:31.94#ibcon#read 4, iclass 26, count 2 2006.285.06:37:31.94#ibcon#about to read 5, iclass 26, count 2 2006.285.06:37:31.94#ibcon#read 5, iclass 26, count 2 2006.285.06:37:31.94#ibcon#about to read 6, iclass 26, count 2 2006.285.06:37:31.94#ibcon#read 6, iclass 26, count 2 2006.285.06:37:31.94#ibcon#end of sib2, iclass 26, count 2 2006.285.06:37:31.94#ibcon#*mode == 0, iclass 26, count 2 2006.285.06:37:31.94#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.06:37:31.94#ibcon#[25=AT01-07\r\n] 2006.285.06:37:31.94#ibcon#*before write, iclass 26, count 2 2006.285.06:37:31.94#ibcon#enter sib2, iclass 26, count 2 2006.285.06:37:31.94#ibcon#flushed, iclass 26, count 2 2006.285.06:37:31.94#ibcon#about to write, iclass 26, count 2 2006.285.06:37:31.94#ibcon#wrote, iclass 26, count 2 2006.285.06:37:31.94#ibcon#about to read 3, iclass 26, count 2 2006.285.06:37:31.97#ibcon#read 3, iclass 26, count 2 2006.285.06:37:31.97#ibcon#about to read 4, iclass 26, count 2 2006.285.06:37:31.97#ibcon#read 4, iclass 26, count 2 2006.285.06:37:31.97#ibcon#about to read 5, iclass 26, count 2 2006.285.06:37:31.97#ibcon#read 5, iclass 26, count 2 2006.285.06:37:31.97#ibcon#about to read 6, iclass 26, count 2 2006.285.06:37:31.97#ibcon#read 6, iclass 26, count 2 2006.285.06:37:31.97#ibcon#end of sib2, iclass 26, count 2 2006.285.06:37:31.97#ibcon#*after write, iclass 26, count 2 2006.285.06:37:31.97#ibcon#*before return 0, iclass 26, count 2 2006.285.06:37:31.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:37:31.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:37:31.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.06:37:31.97#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:31.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:37:32.09#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:37:32.09#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:37:32.09#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:37:32.09#ibcon#first serial, iclass 26, count 0 2006.285.06:37:32.09#ibcon#enter sib2, iclass 26, count 0 2006.285.06:37:32.09#ibcon#flushed, iclass 26, count 0 2006.285.06:37:32.09#ibcon#about to write, iclass 26, count 0 2006.285.06:37:32.09#ibcon#wrote, iclass 26, count 0 2006.285.06:37:32.09#ibcon#about to read 3, iclass 26, count 0 2006.285.06:37:32.11#ibcon#read 3, iclass 26, count 0 2006.285.06:37:32.11#ibcon#about to read 4, iclass 26, count 0 2006.285.06:37:32.11#ibcon#read 4, iclass 26, count 0 2006.285.06:37:32.11#ibcon#about to read 5, iclass 26, count 0 2006.285.06:37:32.11#ibcon#read 5, iclass 26, count 0 2006.285.06:37:32.11#ibcon#about to read 6, iclass 26, count 0 2006.285.06:37:32.11#ibcon#read 6, iclass 26, count 0 2006.285.06:37:32.11#ibcon#end of sib2, iclass 26, count 0 2006.285.06:37:32.11#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:37:32.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:37:32.11#ibcon#[25=USB\r\n] 2006.285.06:37:32.11#ibcon#*before write, iclass 26, count 0 2006.285.06:37:32.11#ibcon#enter sib2, iclass 26, count 0 2006.285.06:37:32.11#ibcon#flushed, iclass 26, count 0 2006.285.06:37:32.11#ibcon#about to write, iclass 26, count 0 2006.285.06:37:32.11#ibcon#wrote, iclass 26, count 0 2006.285.06:37:32.11#ibcon#about to read 3, iclass 26, count 0 2006.285.06:37:32.14#ibcon#read 3, iclass 26, count 0 2006.285.06:37:32.14#ibcon#about to read 4, iclass 26, count 0 2006.285.06:37:32.14#ibcon#read 4, iclass 26, count 0 2006.285.06:37:32.14#ibcon#about to read 5, iclass 26, count 0 2006.285.06:37:32.14#ibcon#read 5, iclass 26, count 0 2006.285.06:37:32.14#ibcon#about to read 6, iclass 26, count 0 2006.285.06:37:32.14#ibcon#read 6, iclass 26, count 0 2006.285.06:37:32.14#ibcon#end of sib2, iclass 26, count 0 2006.285.06:37:32.14#ibcon#*after write, iclass 26, count 0 2006.285.06:37:32.14#ibcon#*before return 0, iclass 26, count 0 2006.285.06:37:32.14#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:37:32.14#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:37:32.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:37:32.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:37:32.14$vck44/valo=2,534.99 2006.285.06:37:32.14#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.06:37:32.14#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.06:37:32.14#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:32.14#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:37:32.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:37:32.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:37:32.14#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:37:32.14#ibcon#first serial, iclass 28, count 0 2006.285.06:37:32.14#ibcon#enter sib2, iclass 28, count 0 2006.285.06:37:32.14#ibcon#flushed, iclass 28, count 0 2006.285.06:37:32.14#ibcon#about to write, iclass 28, count 0 2006.285.06:37:32.14#ibcon#wrote, iclass 28, count 0 2006.285.06:37:32.14#ibcon#about to read 3, iclass 28, count 0 2006.285.06:37:32.16#ibcon#read 3, iclass 28, count 0 2006.285.06:37:32.16#ibcon#about to read 4, iclass 28, count 0 2006.285.06:37:32.16#ibcon#read 4, iclass 28, count 0 2006.285.06:37:32.16#ibcon#about to read 5, iclass 28, count 0 2006.285.06:37:32.16#ibcon#read 5, iclass 28, count 0 2006.285.06:37:32.16#ibcon#about to read 6, iclass 28, count 0 2006.285.06:37:32.16#ibcon#read 6, iclass 28, count 0 2006.285.06:37:32.16#ibcon#end of sib2, iclass 28, count 0 2006.285.06:37:32.16#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:37:32.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:37:32.16#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:37:32.16#ibcon#*before write, iclass 28, count 0 2006.285.06:37:32.16#ibcon#enter sib2, iclass 28, count 0 2006.285.06:37:32.16#ibcon#flushed, iclass 28, count 0 2006.285.06:37:32.16#ibcon#about to write, iclass 28, count 0 2006.285.06:37:32.16#ibcon#wrote, iclass 28, count 0 2006.285.06:37:32.16#ibcon#about to read 3, iclass 28, count 0 2006.285.06:37:32.20#ibcon#read 3, iclass 28, count 0 2006.285.06:37:32.20#ibcon#about to read 4, iclass 28, count 0 2006.285.06:37:32.20#ibcon#read 4, iclass 28, count 0 2006.285.06:37:32.20#ibcon#about to read 5, iclass 28, count 0 2006.285.06:37:32.20#ibcon#read 5, iclass 28, count 0 2006.285.06:37:32.20#ibcon#about to read 6, iclass 28, count 0 2006.285.06:37:32.20#ibcon#read 6, iclass 28, count 0 2006.285.06:37:32.20#ibcon#end of sib2, iclass 28, count 0 2006.285.06:37:32.20#ibcon#*after write, iclass 28, count 0 2006.285.06:37:32.20#ibcon#*before return 0, iclass 28, count 0 2006.285.06:37:32.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:37:32.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:37:32.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:37:32.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:37:32.20$vck44/va=2,6 2006.285.06:37:32.20#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.06:37:32.20#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.06:37:32.20#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:32.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:37:32.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:37:32.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:37:32.26#ibcon#enter wrdev, iclass 30, count 2 2006.285.06:37:32.26#ibcon#first serial, iclass 30, count 2 2006.285.06:37:32.26#ibcon#enter sib2, iclass 30, count 2 2006.285.06:37:32.26#ibcon#flushed, iclass 30, count 2 2006.285.06:37:32.26#ibcon#about to write, iclass 30, count 2 2006.285.06:37:32.26#ibcon#wrote, iclass 30, count 2 2006.285.06:37:32.26#ibcon#about to read 3, iclass 30, count 2 2006.285.06:37:32.28#ibcon#read 3, iclass 30, count 2 2006.285.06:37:32.28#ibcon#about to read 4, iclass 30, count 2 2006.285.06:37:32.28#ibcon#read 4, iclass 30, count 2 2006.285.06:37:32.28#ibcon#about to read 5, iclass 30, count 2 2006.285.06:37:32.28#ibcon#read 5, iclass 30, count 2 2006.285.06:37:32.28#ibcon#about to read 6, iclass 30, count 2 2006.285.06:37:32.28#ibcon#read 6, iclass 30, count 2 2006.285.06:37:32.28#ibcon#end of sib2, iclass 30, count 2 2006.285.06:37:32.28#ibcon#*mode == 0, iclass 30, count 2 2006.285.06:37:32.28#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.06:37:32.28#ibcon#[25=AT02-06\r\n] 2006.285.06:37:32.28#ibcon#*before write, iclass 30, count 2 2006.285.06:37:32.28#ibcon#enter sib2, iclass 30, count 2 2006.285.06:37:32.28#ibcon#flushed, iclass 30, count 2 2006.285.06:37:32.28#ibcon#about to write, iclass 30, count 2 2006.285.06:37:32.28#ibcon#wrote, iclass 30, count 2 2006.285.06:37:32.28#ibcon#about to read 3, iclass 30, count 2 2006.285.06:37:32.31#ibcon#read 3, iclass 30, count 2 2006.285.06:37:32.31#ibcon#about to read 4, iclass 30, count 2 2006.285.06:37:32.31#ibcon#read 4, iclass 30, count 2 2006.285.06:37:32.31#ibcon#about to read 5, iclass 30, count 2 2006.285.06:37:32.31#ibcon#read 5, iclass 30, count 2 2006.285.06:37:32.31#ibcon#about to read 6, iclass 30, count 2 2006.285.06:37:32.31#ibcon#read 6, iclass 30, count 2 2006.285.06:37:32.31#ibcon#end of sib2, iclass 30, count 2 2006.285.06:37:32.31#ibcon#*after write, iclass 30, count 2 2006.285.06:37:32.31#ibcon#*before return 0, iclass 30, count 2 2006.285.06:37:32.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:37:32.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:37:32.31#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.06:37:32.31#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:32.31#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:37:32.43#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:37:32.43#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:37:32.43#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:37:32.43#ibcon#first serial, iclass 30, count 0 2006.285.06:37:32.43#ibcon#enter sib2, iclass 30, count 0 2006.285.06:37:32.43#ibcon#flushed, iclass 30, count 0 2006.285.06:37:32.43#ibcon#about to write, iclass 30, count 0 2006.285.06:37:32.43#ibcon#wrote, iclass 30, count 0 2006.285.06:37:32.43#ibcon#about to read 3, iclass 30, count 0 2006.285.06:37:32.45#ibcon#read 3, iclass 30, count 0 2006.285.06:37:32.45#ibcon#about to read 4, iclass 30, count 0 2006.285.06:37:32.45#ibcon#read 4, iclass 30, count 0 2006.285.06:37:32.45#ibcon#about to read 5, iclass 30, count 0 2006.285.06:37:32.45#ibcon#read 5, iclass 30, count 0 2006.285.06:37:32.45#ibcon#about to read 6, iclass 30, count 0 2006.285.06:37:32.45#ibcon#read 6, iclass 30, count 0 2006.285.06:37:32.45#ibcon#end of sib2, iclass 30, count 0 2006.285.06:37:32.45#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:37:32.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:37:32.45#ibcon#[25=USB\r\n] 2006.285.06:37:32.45#ibcon#*before write, iclass 30, count 0 2006.285.06:37:32.45#ibcon#enter sib2, iclass 30, count 0 2006.285.06:37:32.45#ibcon#flushed, iclass 30, count 0 2006.285.06:37:32.45#ibcon#about to write, iclass 30, count 0 2006.285.06:37:32.45#ibcon#wrote, iclass 30, count 0 2006.285.06:37:32.45#ibcon#about to read 3, iclass 30, count 0 2006.285.06:37:32.48#ibcon#read 3, iclass 30, count 0 2006.285.06:37:32.48#ibcon#about to read 4, iclass 30, count 0 2006.285.06:37:32.48#ibcon#read 4, iclass 30, count 0 2006.285.06:37:32.48#ibcon#about to read 5, iclass 30, count 0 2006.285.06:37:32.48#ibcon#read 5, iclass 30, count 0 2006.285.06:37:32.48#ibcon#about to read 6, iclass 30, count 0 2006.285.06:37:32.48#ibcon#read 6, iclass 30, count 0 2006.285.06:37:32.48#ibcon#end of sib2, iclass 30, count 0 2006.285.06:37:32.48#ibcon#*after write, iclass 30, count 0 2006.285.06:37:32.48#ibcon#*before return 0, iclass 30, count 0 2006.285.06:37:32.48#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:37:32.48#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:37:32.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:37:32.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:37:32.48$vck44/valo=3,564.99 2006.285.06:37:32.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.06:37:32.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.06:37:32.48#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:32.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:37:32.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:37:32.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:37:32.48#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:37:32.48#ibcon#first serial, iclass 32, count 0 2006.285.06:37:32.48#ibcon#enter sib2, iclass 32, count 0 2006.285.06:37:32.48#ibcon#flushed, iclass 32, count 0 2006.285.06:37:32.48#ibcon#about to write, iclass 32, count 0 2006.285.06:37:32.48#ibcon#wrote, iclass 32, count 0 2006.285.06:37:32.48#ibcon#about to read 3, iclass 32, count 0 2006.285.06:37:32.50#ibcon#read 3, iclass 32, count 0 2006.285.06:37:32.50#ibcon#about to read 4, iclass 32, count 0 2006.285.06:37:32.50#ibcon#read 4, iclass 32, count 0 2006.285.06:37:32.50#ibcon#about to read 5, iclass 32, count 0 2006.285.06:37:32.50#ibcon#read 5, iclass 32, count 0 2006.285.06:37:32.50#ibcon#about to read 6, iclass 32, count 0 2006.285.06:37:32.50#ibcon#read 6, iclass 32, count 0 2006.285.06:37:32.50#ibcon#end of sib2, iclass 32, count 0 2006.285.06:37:32.50#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:37:32.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:37:32.50#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:37:32.50#ibcon#*before write, iclass 32, count 0 2006.285.06:37:32.50#ibcon#enter sib2, iclass 32, count 0 2006.285.06:37:32.50#ibcon#flushed, iclass 32, count 0 2006.285.06:37:32.50#ibcon#about to write, iclass 32, count 0 2006.285.06:37:32.50#ibcon#wrote, iclass 32, count 0 2006.285.06:37:32.50#ibcon#about to read 3, iclass 32, count 0 2006.285.06:37:32.54#ibcon#read 3, iclass 32, count 0 2006.285.06:37:32.54#ibcon#about to read 4, iclass 32, count 0 2006.285.06:37:32.54#ibcon#read 4, iclass 32, count 0 2006.285.06:37:32.54#ibcon#about to read 5, iclass 32, count 0 2006.285.06:37:32.54#ibcon#read 5, iclass 32, count 0 2006.285.06:37:32.54#ibcon#about to read 6, iclass 32, count 0 2006.285.06:37:32.54#ibcon#read 6, iclass 32, count 0 2006.285.06:37:32.54#ibcon#end of sib2, iclass 32, count 0 2006.285.06:37:32.54#ibcon#*after write, iclass 32, count 0 2006.285.06:37:32.54#ibcon#*before return 0, iclass 32, count 0 2006.285.06:37:32.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:37:32.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:37:32.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:37:32.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:37:32.54$vck44/va=3,7 2006.285.06:37:32.54#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.06:37:32.54#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.06:37:32.54#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:32.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:37:32.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:37:32.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:37:32.60#ibcon#enter wrdev, iclass 34, count 2 2006.285.06:37:32.60#ibcon#first serial, iclass 34, count 2 2006.285.06:37:32.60#ibcon#enter sib2, iclass 34, count 2 2006.285.06:37:32.60#ibcon#flushed, iclass 34, count 2 2006.285.06:37:32.60#ibcon#about to write, iclass 34, count 2 2006.285.06:37:32.60#ibcon#wrote, iclass 34, count 2 2006.285.06:37:32.60#ibcon#about to read 3, iclass 34, count 2 2006.285.06:37:32.62#ibcon#read 3, iclass 34, count 2 2006.285.06:37:32.62#ibcon#about to read 4, iclass 34, count 2 2006.285.06:37:32.62#ibcon#read 4, iclass 34, count 2 2006.285.06:37:32.62#ibcon#about to read 5, iclass 34, count 2 2006.285.06:37:32.62#ibcon#read 5, iclass 34, count 2 2006.285.06:37:32.62#ibcon#about to read 6, iclass 34, count 2 2006.285.06:37:32.62#ibcon#read 6, iclass 34, count 2 2006.285.06:37:32.62#ibcon#end of sib2, iclass 34, count 2 2006.285.06:37:32.62#ibcon#*mode == 0, iclass 34, count 2 2006.285.06:37:32.62#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.06:37:32.62#ibcon#[25=AT03-07\r\n] 2006.285.06:37:32.62#ibcon#*before write, iclass 34, count 2 2006.285.06:37:32.62#ibcon#enter sib2, iclass 34, count 2 2006.285.06:37:32.62#ibcon#flushed, iclass 34, count 2 2006.285.06:37:32.62#ibcon#about to write, iclass 34, count 2 2006.285.06:37:32.62#ibcon#wrote, iclass 34, count 2 2006.285.06:37:32.62#ibcon#about to read 3, iclass 34, count 2 2006.285.06:37:32.65#ibcon#read 3, iclass 34, count 2 2006.285.06:37:32.65#ibcon#about to read 4, iclass 34, count 2 2006.285.06:37:32.65#ibcon#read 4, iclass 34, count 2 2006.285.06:37:32.65#ibcon#about to read 5, iclass 34, count 2 2006.285.06:37:32.65#ibcon#read 5, iclass 34, count 2 2006.285.06:37:32.65#ibcon#about to read 6, iclass 34, count 2 2006.285.06:37:32.65#ibcon#read 6, iclass 34, count 2 2006.285.06:37:32.65#ibcon#end of sib2, iclass 34, count 2 2006.285.06:37:32.65#ibcon#*after write, iclass 34, count 2 2006.285.06:37:32.65#ibcon#*before return 0, iclass 34, count 2 2006.285.06:37:32.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:37:32.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:37:32.65#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.06:37:32.65#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:32.65#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:37:32.77#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:37:32.77#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:37:32.77#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:37:32.77#ibcon#first serial, iclass 34, count 0 2006.285.06:37:32.77#ibcon#enter sib2, iclass 34, count 0 2006.285.06:37:32.77#ibcon#flushed, iclass 34, count 0 2006.285.06:37:32.77#ibcon#about to write, iclass 34, count 0 2006.285.06:37:32.77#ibcon#wrote, iclass 34, count 0 2006.285.06:37:32.77#ibcon#about to read 3, iclass 34, count 0 2006.285.06:37:32.79#ibcon#read 3, iclass 34, count 0 2006.285.06:37:32.79#ibcon#about to read 4, iclass 34, count 0 2006.285.06:37:32.79#ibcon#read 4, iclass 34, count 0 2006.285.06:37:32.79#ibcon#about to read 5, iclass 34, count 0 2006.285.06:37:32.79#ibcon#read 5, iclass 34, count 0 2006.285.06:37:32.79#ibcon#about to read 6, iclass 34, count 0 2006.285.06:37:32.79#ibcon#read 6, iclass 34, count 0 2006.285.06:37:32.79#ibcon#end of sib2, iclass 34, count 0 2006.285.06:37:32.79#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:37:32.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:37:32.79#ibcon#[25=USB\r\n] 2006.285.06:37:32.79#ibcon#*before write, iclass 34, count 0 2006.285.06:37:32.79#ibcon#enter sib2, iclass 34, count 0 2006.285.06:37:32.79#ibcon#flushed, iclass 34, count 0 2006.285.06:37:32.79#ibcon#about to write, iclass 34, count 0 2006.285.06:37:32.79#ibcon#wrote, iclass 34, count 0 2006.285.06:37:32.79#ibcon#about to read 3, iclass 34, count 0 2006.285.06:37:32.82#ibcon#read 3, iclass 34, count 0 2006.285.06:37:32.82#ibcon#about to read 4, iclass 34, count 0 2006.285.06:37:32.82#ibcon#read 4, iclass 34, count 0 2006.285.06:37:32.82#ibcon#about to read 5, iclass 34, count 0 2006.285.06:37:32.82#ibcon#read 5, iclass 34, count 0 2006.285.06:37:32.82#ibcon#about to read 6, iclass 34, count 0 2006.285.06:37:32.82#ibcon#read 6, iclass 34, count 0 2006.285.06:37:32.82#ibcon#end of sib2, iclass 34, count 0 2006.285.06:37:32.82#ibcon#*after write, iclass 34, count 0 2006.285.06:37:32.82#ibcon#*before return 0, iclass 34, count 0 2006.285.06:37:32.82#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:37:32.82#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:37:32.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:37:32.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:37:32.82$vck44/valo=4,624.99 2006.285.06:37:32.82#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.06:37:32.82#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.06:37:32.82#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:32.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:37:32.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:37:32.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:37:32.82#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:37:32.82#ibcon#first serial, iclass 36, count 0 2006.285.06:37:32.82#ibcon#enter sib2, iclass 36, count 0 2006.285.06:37:32.82#ibcon#flushed, iclass 36, count 0 2006.285.06:37:32.82#ibcon#about to write, iclass 36, count 0 2006.285.06:37:32.82#ibcon#wrote, iclass 36, count 0 2006.285.06:37:32.82#ibcon#about to read 3, iclass 36, count 0 2006.285.06:37:32.84#ibcon#read 3, iclass 36, count 0 2006.285.06:37:32.84#ibcon#about to read 4, iclass 36, count 0 2006.285.06:37:32.84#ibcon#read 4, iclass 36, count 0 2006.285.06:37:32.84#ibcon#about to read 5, iclass 36, count 0 2006.285.06:37:32.84#ibcon#read 5, iclass 36, count 0 2006.285.06:37:32.84#ibcon#about to read 6, iclass 36, count 0 2006.285.06:37:32.84#ibcon#read 6, iclass 36, count 0 2006.285.06:37:32.84#ibcon#end of sib2, iclass 36, count 0 2006.285.06:37:32.84#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:37:32.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:37:32.84#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:37:32.84#ibcon#*before write, iclass 36, count 0 2006.285.06:37:32.84#ibcon#enter sib2, iclass 36, count 0 2006.285.06:37:32.84#ibcon#flushed, iclass 36, count 0 2006.285.06:37:32.84#ibcon#about to write, iclass 36, count 0 2006.285.06:37:32.84#ibcon#wrote, iclass 36, count 0 2006.285.06:37:32.84#ibcon#about to read 3, iclass 36, count 0 2006.285.06:37:32.88#ibcon#read 3, iclass 36, count 0 2006.285.06:37:32.88#ibcon#about to read 4, iclass 36, count 0 2006.285.06:37:32.88#ibcon#read 4, iclass 36, count 0 2006.285.06:37:32.88#ibcon#about to read 5, iclass 36, count 0 2006.285.06:37:32.88#ibcon#read 5, iclass 36, count 0 2006.285.06:37:32.88#ibcon#about to read 6, iclass 36, count 0 2006.285.06:37:32.88#ibcon#read 6, iclass 36, count 0 2006.285.06:37:32.88#ibcon#end of sib2, iclass 36, count 0 2006.285.06:37:32.88#ibcon#*after write, iclass 36, count 0 2006.285.06:37:32.88#ibcon#*before return 0, iclass 36, count 0 2006.285.06:37:32.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:37:32.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:37:32.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:37:32.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:37:32.88$vck44/va=4,6 2006.285.06:37:32.88#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.06:37:32.88#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.06:37:32.88#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:32.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:37:32.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:37:32.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:37:32.94#ibcon#enter wrdev, iclass 38, count 2 2006.285.06:37:32.94#ibcon#first serial, iclass 38, count 2 2006.285.06:37:32.94#ibcon#enter sib2, iclass 38, count 2 2006.285.06:37:32.94#ibcon#flushed, iclass 38, count 2 2006.285.06:37:32.94#ibcon#about to write, iclass 38, count 2 2006.285.06:37:32.94#ibcon#wrote, iclass 38, count 2 2006.285.06:37:32.94#ibcon#about to read 3, iclass 38, count 2 2006.285.06:37:32.96#ibcon#read 3, iclass 38, count 2 2006.285.06:37:32.96#ibcon#about to read 4, iclass 38, count 2 2006.285.06:37:32.96#ibcon#read 4, iclass 38, count 2 2006.285.06:37:32.96#ibcon#about to read 5, iclass 38, count 2 2006.285.06:37:32.96#ibcon#read 5, iclass 38, count 2 2006.285.06:37:32.96#ibcon#about to read 6, iclass 38, count 2 2006.285.06:37:32.96#ibcon#read 6, iclass 38, count 2 2006.285.06:37:32.96#ibcon#end of sib2, iclass 38, count 2 2006.285.06:37:32.96#ibcon#*mode == 0, iclass 38, count 2 2006.285.06:37:32.96#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.06:37:32.96#ibcon#[25=AT04-06\r\n] 2006.285.06:37:32.96#ibcon#*before write, iclass 38, count 2 2006.285.06:37:32.96#ibcon#enter sib2, iclass 38, count 2 2006.285.06:37:32.96#ibcon#flushed, iclass 38, count 2 2006.285.06:37:32.96#ibcon#about to write, iclass 38, count 2 2006.285.06:37:32.96#ibcon#wrote, iclass 38, count 2 2006.285.06:37:32.96#ibcon#about to read 3, iclass 38, count 2 2006.285.06:37:32.99#ibcon#read 3, iclass 38, count 2 2006.285.06:37:32.99#ibcon#about to read 4, iclass 38, count 2 2006.285.06:37:32.99#ibcon#read 4, iclass 38, count 2 2006.285.06:37:32.99#ibcon#about to read 5, iclass 38, count 2 2006.285.06:37:32.99#ibcon#read 5, iclass 38, count 2 2006.285.06:37:32.99#ibcon#about to read 6, iclass 38, count 2 2006.285.06:37:32.99#ibcon#read 6, iclass 38, count 2 2006.285.06:37:32.99#ibcon#end of sib2, iclass 38, count 2 2006.285.06:37:32.99#ibcon#*after write, iclass 38, count 2 2006.285.06:37:32.99#ibcon#*before return 0, iclass 38, count 2 2006.285.06:37:32.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:37:32.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:37:32.99#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.06:37:32.99#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:32.99#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:37:33.11#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:37:33.11#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:37:33.11#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:37:33.11#ibcon#first serial, iclass 38, count 0 2006.285.06:37:33.11#ibcon#enter sib2, iclass 38, count 0 2006.285.06:37:33.11#ibcon#flushed, iclass 38, count 0 2006.285.06:37:33.11#ibcon#about to write, iclass 38, count 0 2006.285.06:37:33.11#ibcon#wrote, iclass 38, count 0 2006.285.06:37:33.11#ibcon#about to read 3, iclass 38, count 0 2006.285.06:37:33.13#ibcon#read 3, iclass 38, count 0 2006.285.06:37:33.13#ibcon#about to read 4, iclass 38, count 0 2006.285.06:37:33.13#ibcon#read 4, iclass 38, count 0 2006.285.06:37:33.13#ibcon#about to read 5, iclass 38, count 0 2006.285.06:37:33.13#ibcon#read 5, iclass 38, count 0 2006.285.06:37:33.13#ibcon#about to read 6, iclass 38, count 0 2006.285.06:37:33.13#ibcon#read 6, iclass 38, count 0 2006.285.06:37:33.13#ibcon#end of sib2, iclass 38, count 0 2006.285.06:37:33.13#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:37:33.13#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:37:33.13#ibcon#[25=USB\r\n] 2006.285.06:37:33.13#ibcon#*before write, iclass 38, count 0 2006.285.06:37:33.13#ibcon#enter sib2, iclass 38, count 0 2006.285.06:37:33.13#ibcon#flushed, iclass 38, count 0 2006.285.06:37:33.13#ibcon#about to write, iclass 38, count 0 2006.285.06:37:33.13#ibcon#wrote, iclass 38, count 0 2006.285.06:37:33.13#ibcon#about to read 3, iclass 38, count 0 2006.285.06:37:33.15#abcon#<5=/05 4.9 7.6 24.82 691014.1\r\n> 2006.285.06:37:33.16#ibcon#read 3, iclass 38, count 0 2006.285.06:37:33.16#ibcon#about to read 4, iclass 38, count 0 2006.285.06:37:33.16#ibcon#read 4, iclass 38, count 0 2006.285.06:37:33.16#ibcon#about to read 5, iclass 38, count 0 2006.285.06:37:33.16#ibcon#read 5, iclass 38, count 0 2006.285.06:37:33.16#ibcon#about to read 6, iclass 38, count 0 2006.285.06:37:33.16#ibcon#read 6, iclass 38, count 0 2006.285.06:37:33.16#ibcon#end of sib2, iclass 38, count 0 2006.285.06:37:33.16#ibcon#*after write, iclass 38, count 0 2006.285.06:37:33.16#ibcon#*before return 0, iclass 38, count 0 2006.285.06:37:33.16#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:37:33.16#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:37:33.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:37:33.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:37:33.16$vck44/valo=5,734.99 2006.285.06:37:33.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.06:37:33.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.06:37:33.16#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:33.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:37:33.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:37:33.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:37:33.16#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:37:33.16#ibcon#first serial, iclass 5, count 0 2006.285.06:37:33.16#ibcon#enter sib2, iclass 5, count 0 2006.285.06:37:33.16#ibcon#flushed, iclass 5, count 0 2006.285.06:37:33.16#ibcon#about to write, iclass 5, count 0 2006.285.06:37:33.16#ibcon#wrote, iclass 5, count 0 2006.285.06:37:33.16#ibcon#about to read 3, iclass 5, count 0 2006.285.06:37:33.17#abcon#{5=INTERFACE CLEAR} 2006.285.06:37:33.18#ibcon#read 3, iclass 5, count 0 2006.285.06:37:33.18#ibcon#about to read 4, iclass 5, count 0 2006.285.06:37:33.18#ibcon#read 4, iclass 5, count 0 2006.285.06:37:33.18#ibcon#about to read 5, iclass 5, count 0 2006.285.06:37:33.18#ibcon#read 5, iclass 5, count 0 2006.285.06:37:33.18#ibcon#about to read 6, iclass 5, count 0 2006.285.06:37:33.18#ibcon#read 6, iclass 5, count 0 2006.285.06:37:33.18#ibcon#end of sib2, iclass 5, count 0 2006.285.06:37:33.18#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:37:33.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:37:33.18#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:37:33.18#ibcon#*before write, iclass 5, count 0 2006.285.06:37:33.18#ibcon#enter sib2, iclass 5, count 0 2006.285.06:37:33.18#ibcon#flushed, iclass 5, count 0 2006.285.06:37:33.18#ibcon#about to write, iclass 5, count 0 2006.285.06:37:33.18#ibcon#wrote, iclass 5, count 0 2006.285.06:37:33.18#ibcon#about to read 3, iclass 5, count 0 2006.285.06:37:33.22#ibcon#read 3, iclass 5, count 0 2006.285.06:37:33.22#ibcon#about to read 4, iclass 5, count 0 2006.285.06:37:33.22#ibcon#read 4, iclass 5, count 0 2006.285.06:37:33.22#ibcon#about to read 5, iclass 5, count 0 2006.285.06:37:33.22#ibcon#read 5, iclass 5, count 0 2006.285.06:37:33.22#ibcon#about to read 6, iclass 5, count 0 2006.285.06:37:33.22#ibcon#read 6, iclass 5, count 0 2006.285.06:37:33.22#ibcon#end of sib2, iclass 5, count 0 2006.285.06:37:33.22#ibcon#*after write, iclass 5, count 0 2006.285.06:37:33.22#ibcon#*before return 0, iclass 5, count 0 2006.285.06:37:33.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:37:33.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:37:33.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:37:33.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:37:33.22$vck44/va=5,3 2006.285.06:37:33.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.06:37:33.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.06:37:33.22#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:33.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:37:33.23#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:37:33.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:37:33.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:37:33.28#ibcon#enter wrdev, iclass 10, count 2 2006.285.06:37:33.28#ibcon#first serial, iclass 10, count 2 2006.285.06:37:33.28#ibcon#enter sib2, iclass 10, count 2 2006.285.06:37:33.28#ibcon#flushed, iclass 10, count 2 2006.285.06:37:33.28#ibcon#about to write, iclass 10, count 2 2006.285.06:37:33.28#ibcon#wrote, iclass 10, count 2 2006.285.06:37:33.28#ibcon#about to read 3, iclass 10, count 2 2006.285.06:37:33.30#ibcon#read 3, iclass 10, count 2 2006.285.06:37:33.30#ibcon#about to read 4, iclass 10, count 2 2006.285.06:37:33.30#ibcon#read 4, iclass 10, count 2 2006.285.06:37:33.30#ibcon#about to read 5, iclass 10, count 2 2006.285.06:37:33.30#ibcon#read 5, iclass 10, count 2 2006.285.06:37:33.30#ibcon#about to read 6, iclass 10, count 2 2006.285.06:37:33.30#ibcon#read 6, iclass 10, count 2 2006.285.06:37:33.30#ibcon#end of sib2, iclass 10, count 2 2006.285.06:37:33.30#ibcon#*mode == 0, iclass 10, count 2 2006.285.06:37:33.30#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.06:37:33.30#ibcon#[25=AT05-03\r\n] 2006.285.06:37:33.30#ibcon#*before write, iclass 10, count 2 2006.285.06:37:33.30#ibcon#enter sib2, iclass 10, count 2 2006.285.06:37:33.30#ibcon#flushed, iclass 10, count 2 2006.285.06:37:33.30#ibcon#about to write, iclass 10, count 2 2006.285.06:37:33.30#ibcon#wrote, iclass 10, count 2 2006.285.06:37:33.30#ibcon#about to read 3, iclass 10, count 2 2006.285.06:37:33.33#ibcon#read 3, iclass 10, count 2 2006.285.06:37:33.33#ibcon#about to read 4, iclass 10, count 2 2006.285.06:37:33.33#ibcon#read 4, iclass 10, count 2 2006.285.06:37:33.33#ibcon#about to read 5, iclass 10, count 2 2006.285.06:37:33.33#ibcon#read 5, iclass 10, count 2 2006.285.06:37:33.33#ibcon#about to read 6, iclass 10, count 2 2006.285.06:37:33.33#ibcon#read 6, iclass 10, count 2 2006.285.06:37:33.33#ibcon#end of sib2, iclass 10, count 2 2006.285.06:37:33.33#ibcon#*after write, iclass 10, count 2 2006.285.06:37:33.33#ibcon#*before return 0, iclass 10, count 2 2006.285.06:37:33.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:37:33.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:37:33.33#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.06:37:33.33#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:33.33#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:37:33.45#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:37:33.45#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:37:33.45#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:37:33.45#ibcon#first serial, iclass 10, count 0 2006.285.06:37:33.45#ibcon#enter sib2, iclass 10, count 0 2006.285.06:37:33.45#ibcon#flushed, iclass 10, count 0 2006.285.06:37:33.45#ibcon#about to write, iclass 10, count 0 2006.285.06:37:33.45#ibcon#wrote, iclass 10, count 0 2006.285.06:37:33.45#ibcon#about to read 3, iclass 10, count 0 2006.285.06:37:33.47#ibcon#read 3, iclass 10, count 0 2006.285.06:37:33.47#ibcon#about to read 4, iclass 10, count 0 2006.285.06:37:33.47#ibcon#read 4, iclass 10, count 0 2006.285.06:37:33.47#ibcon#about to read 5, iclass 10, count 0 2006.285.06:37:33.47#ibcon#read 5, iclass 10, count 0 2006.285.06:37:33.47#ibcon#about to read 6, iclass 10, count 0 2006.285.06:37:33.47#ibcon#read 6, iclass 10, count 0 2006.285.06:37:33.47#ibcon#end of sib2, iclass 10, count 0 2006.285.06:37:33.47#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:37:33.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:37:33.47#ibcon#[25=USB\r\n] 2006.285.06:37:33.47#ibcon#*before write, iclass 10, count 0 2006.285.06:37:33.47#ibcon#enter sib2, iclass 10, count 0 2006.285.06:37:33.47#ibcon#flushed, iclass 10, count 0 2006.285.06:37:33.47#ibcon#about to write, iclass 10, count 0 2006.285.06:37:33.47#ibcon#wrote, iclass 10, count 0 2006.285.06:37:33.47#ibcon#about to read 3, iclass 10, count 0 2006.285.06:37:33.50#ibcon#read 3, iclass 10, count 0 2006.285.06:37:33.50#ibcon#about to read 4, iclass 10, count 0 2006.285.06:37:33.50#ibcon#read 4, iclass 10, count 0 2006.285.06:37:33.50#ibcon#about to read 5, iclass 10, count 0 2006.285.06:37:33.50#ibcon#read 5, iclass 10, count 0 2006.285.06:37:33.50#ibcon#about to read 6, iclass 10, count 0 2006.285.06:37:33.50#ibcon#read 6, iclass 10, count 0 2006.285.06:37:33.50#ibcon#end of sib2, iclass 10, count 0 2006.285.06:37:33.50#ibcon#*after write, iclass 10, count 0 2006.285.06:37:33.50#ibcon#*before return 0, iclass 10, count 0 2006.285.06:37:33.50#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:37:33.50#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:37:33.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:37:33.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:37:33.50$vck44/valo=6,814.99 2006.285.06:37:33.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.06:37:33.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.06:37:33.50#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:33.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:37:33.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:37:33.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:37:33.50#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:37:33.50#ibcon#first serial, iclass 12, count 0 2006.285.06:37:33.50#ibcon#enter sib2, iclass 12, count 0 2006.285.06:37:33.50#ibcon#flushed, iclass 12, count 0 2006.285.06:37:33.50#ibcon#about to write, iclass 12, count 0 2006.285.06:37:33.50#ibcon#wrote, iclass 12, count 0 2006.285.06:37:33.50#ibcon#about to read 3, iclass 12, count 0 2006.285.06:37:33.52#ibcon#read 3, iclass 12, count 0 2006.285.06:37:33.52#ibcon#about to read 4, iclass 12, count 0 2006.285.06:37:33.52#ibcon#read 4, iclass 12, count 0 2006.285.06:37:33.52#ibcon#about to read 5, iclass 12, count 0 2006.285.06:37:33.52#ibcon#read 5, iclass 12, count 0 2006.285.06:37:33.52#ibcon#about to read 6, iclass 12, count 0 2006.285.06:37:33.52#ibcon#read 6, iclass 12, count 0 2006.285.06:37:33.52#ibcon#end of sib2, iclass 12, count 0 2006.285.06:37:33.52#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:37:33.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:37:33.52#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:37:33.52#ibcon#*before write, iclass 12, count 0 2006.285.06:37:33.52#ibcon#enter sib2, iclass 12, count 0 2006.285.06:37:33.52#ibcon#flushed, iclass 12, count 0 2006.285.06:37:33.52#ibcon#about to write, iclass 12, count 0 2006.285.06:37:33.52#ibcon#wrote, iclass 12, count 0 2006.285.06:37:33.52#ibcon#about to read 3, iclass 12, count 0 2006.285.06:37:33.56#ibcon#read 3, iclass 12, count 0 2006.285.06:37:33.56#ibcon#about to read 4, iclass 12, count 0 2006.285.06:37:33.56#ibcon#read 4, iclass 12, count 0 2006.285.06:37:33.56#ibcon#about to read 5, iclass 12, count 0 2006.285.06:37:33.56#ibcon#read 5, iclass 12, count 0 2006.285.06:37:33.56#ibcon#about to read 6, iclass 12, count 0 2006.285.06:37:33.56#ibcon#read 6, iclass 12, count 0 2006.285.06:37:33.56#ibcon#end of sib2, iclass 12, count 0 2006.285.06:37:33.56#ibcon#*after write, iclass 12, count 0 2006.285.06:37:33.56#ibcon#*before return 0, iclass 12, count 0 2006.285.06:37:33.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:37:33.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:37:33.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:37:33.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:37:33.56$vck44/va=6,4 2006.285.06:37:33.56#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.06:37:33.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.06:37:33.56#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:33.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:37:33.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:37:33.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:37:33.62#ibcon#enter wrdev, iclass 14, count 2 2006.285.06:37:33.62#ibcon#first serial, iclass 14, count 2 2006.285.06:37:33.62#ibcon#enter sib2, iclass 14, count 2 2006.285.06:37:33.62#ibcon#flushed, iclass 14, count 2 2006.285.06:37:33.62#ibcon#about to write, iclass 14, count 2 2006.285.06:37:33.62#ibcon#wrote, iclass 14, count 2 2006.285.06:37:33.62#ibcon#about to read 3, iclass 14, count 2 2006.285.06:37:33.64#ibcon#read 3, iclass 14, count 2 2006.285.06:37:33.64#ibcon#about to read 4, iclass 14, count 2 2006.285.06:37:33.64#ibcon#read 4, iclass 14, count 2 2006.285.06:37:33.64#ibcon#about to read 5, iclass 14, count 2 2006.285.06:37:33.64#ibcon#read 5, iclass 14, count 2 2006.285.06:37:33.64#ibcon#about to read 6, iclass 14, count 2 2006.285.06:37:33.64#ibcon#read 6, iclass 14, count 2 2006.285.06:37:33.64#ibcon#end of sib2, iclass 14, count 2 2006.285.06:37:33.64#ibcon#*mode == 0, iclass 14, count 2 2006.285.06:37:33.64#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.06:37:33.64#ibcon#[25=AT06-04\r\n] 2006.285.06:37:33.64#ibcon#*before write, iclass 14, count 2 2006.285.06:37:33.64#ibcon#enter sib2, iclass 14, count 2 2006.285.06:37:33.64#ibcon#flushed, iclass 14, count 2 2006.285.06:37:33.64#ibcon#about to write, iclass 14, count 2 2006.285.06:37:33.64#ibcon#wrote, iclass 14, count 2 2006.285.06:37:33.64#ibcon#about to read 3, iclass 14, count 2 2006.285.06:37:33.67#ibcon#read 3, iclass 14, count 2 2006.285.06:37:33.67#ibcon#about to read 4, iclass 14, count 2 2006.285.06:37:33.67#ibcon#read 4, iclass 14, count 2 2006.285.06:37:33.67#ibcon#about to read 5, iclass 14, count 2 2006.285.06:37:33.67#ibcon#read 5, iclass 14, count 2 2006.285.06:37:33.67#ibcon#about to read 6, iclass 14, count 2 2006.285.06:37:33.67#ibcon#read 6, iclass 14, count 2 2006.285.06:37:33.67#ibcon#end of sib2, iclass 14, count 2 2006.285.06:37:33.67#ibcon#*after write, iclass 14, count 2 2006.285.06:37:33.67#ibcon#*before return 0, iclass 14, count 2 2006.285.06:37:33.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:37:33.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:37:33.67#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.06:37:33.67#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:33.67#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:37:33.79#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:37:33.79#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:37:33.79#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:37:33.79#ibcon#first serial, iclass 14, count 0 2006.285.06:37:33.79#ibcon#enter sib2, iclass 14, count 0 2006.285.06:37:33.79#ibcon#flushed, iclass 14, count 0 2006.285.06:37:33.79#ibcon#about to write, iclass 14, count 0 2006.285.06:37:33.79#ibcon#wrote, iclass 14, count 0 2006.285.06:37:33.79#ibcon#about to read 3, iclass 14, count 0 2006.285.06:37:33.81#ibcon#read 3, iclass 14, count 0 2006.285.06:37:33.81#ibcon#about to read 4, iclass 14, count 0 2006.285.06:37:33.81#ibcon#read 4, iclass 14, count 0 2006.285.06:37:33.81#ibcon#about to read 5, iclass 14, count 0 2006.285.06:37:33.81#ibcon#read 5, iclass 14, count 0 2006.285.06:37:33.81#ibcon#about to read 6, iclass 14, count 0 2006.285.06:37:33.81#ibcon#read 6, iclass 14, count 0 2006.285.06:37:33.81#ibcon#end of sib2, iclass 14, count 0 2006.285.06:37:33.81#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:37:33.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:37:33.81#ibcon#[25=USB\r\n] 2006.285.06:37:33.81#ibcon#*before write, iclass 14, count 0 2006.285.06:37:33.81#ibcon#enter sib2, iclass 14, count 0 2006.285.06:37:33.81#ibcon#flushed, iclass 14, count 0 2006.285.06:37:33.81#ibcon#about to write, iclass 14, count 0 2006.285.06:37:33.81#ibcon#wrote, iclass 14, count 0 2006.285.06:37:33.81#ibcon#about to read 3, iclass 14, count 0 2006.285.06:37:33.84#ibcon#read 3, iclass 14, count 0 2006.285.06:37:33.84#ibcon#about to read 4, iclass 14, count 0 2006.285.06:37:33.84#ibcon#read 4, iclass 14, count 0 2006.285.06:37:33.84#ibcon#about to read 5, iclass 14, count 0 2006.285.06:37:33.84#ibcon#read 5, iclass 14, count 0 2006.285.06:37:33.84#ibcon#about to read 6, iclass 14, count 0 2006.285.06:37:33.84#ibcon#read 6, iclass 14, count 0 2006.285.06:37:33.84#ibcon#end of sib2, iclass 14, count 0 2006.285.06:37:33.84#ibcon#*after write, iclass 14, count 0 2006.285.06:37:33.84#ibcon#*before return 0, iclass 14, count 0 2006.285.06:37:33.84#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:37:33.84#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:37:33.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:37:33.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:37:33.84$vck44/valo=7,864.99 2006.285.06:37:33.84#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.06:37:33.84#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.06:37:33.84#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:33.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:37:33.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:37:33.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:37:33.84#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:37:33.84#ibcon#first serial, iclass 16, count 0 2006.285.06:37:33.84#ibcon#enter sib2, iclass 16, count 0 2006.285.06:37:33.84#ibcon#flushed, iclass 16, count 0 2006.285.06:37:33.84#ibcon#about to write, iclass 16, count 0 2006.285.06:37:33.84#ibcon#wrote, iclass 16, count 0 2006.285.06:37:33.84#ibcon#about to read 3, iclass 16, count 0 2006.285.06:37:33.86#ibcon#read 3, iclass 16, count 0 2006.285.06:37:33.86#ibcon#about to read 4, iclass 16, count 0 2006.285.06:37:33.86#ibcon#read 4, iclass 16, count 0 2006.285.06:37:33.86#ibcon#about to read 5, iclass 16, count 0 2006.285.06:37:33.86#ibcon#read 5, iclass 16, count 0 2006.285.06:37:33.86#ibcon#about to read 6, iclass 16, count 0 2006.285.06:37:33.86#ibcon#read 6, iclass 16, count 0 2006.285.06:37:33.86#ibcon#end of sib2, iclass 16, count 0 2006.285.06:37:33.86#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:37:33.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:37:33.86#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:37:33.86#ibcon#*before write, iclass 16, count 0 2006.285.06:37:33.86#ibcon#enter sib2, iclass 16, count 0 2006.285.06:37:33.86#ibcon#flushed, iclass 16, count 0 2006.285.06:37:33.86#ibcon#about to write, iclass 16, count 0 2006.285.06:37:33.86#ibcon#wrote, iclass 16, count 0 2006.285.06:37:33.86#ibcon#about to read 3, iclass 16, count 0 2006.285.06:37:33.90#ibcon#read 3, iclass 16, count 0 2006.285.06:37:33.90#ibcon#about to read 4, iclass 16, count 0 2006.285.06:37:33.90#ibcon#read 4, iclass 16, count 0 2006.285.06:37:33.90#ibcon#about to read 5, iclass 16, count 0 2006.285.06:37:33.90#ibcon#read 5, iclass 16, count 0 2006.285.06:37:33.90#ibcon#about to read 6, iclass 16, count 0 2006.285.06:37:33.90#ibcon#read 6, iclass 16, count 0 2006.285.06:37:33.90#ibcon#end of sib2, iclass 16, count 0 2006.285.06:37:33.90#ibcon#*after write, iclass 16, count 0 2006.285.06:37:33.90#ibcon#*before return 0, iclass 16, count 0 2006.285.06:37:33.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:37:33.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:37:33.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:37:33.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:37:33.90$vck44/va=7,4 2006.285.06:37:33.90#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.06:37:33.90#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.06:37:33.90#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:33.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:37:33.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:37:33.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:37:33.96#ibcon#enter wrdev, iclass 18, count 2 2006.285.06:37:33.96#ibcon#first serial, iclass 18, count 2 2006.285.06:37:33.96#ibcon#enter sib2, iclass 18, count 2 2006.285.06:37:33.96#ibcon#flushed, iclass 18, count 2 2006.285.06:37:33.96#ibcon#about to write, iclass 18, count 2 2006.285.06:37:33.96#ibcon#wrote, iclass 18, count 2 2006.285.06:37:33.96#ibcon#about to read 3, iclass 18, count 2 2006.285.06:37:33.98#ibcon#read 3, iclass 18, count 2 2006.285.06:37:33.98#ibcon#about to read 4, iclass 18, count 2 2006.285.06:37:33.98#ibcon#read 4, iclass 18, count 2 2006.285.06:37:33.98#ibcon#about to read 5, iclass 18, count 2 2006.285.06:37:33.98#ibcon#read 5, iclass 18, count 2 2006.285.06:37:33.98#ibcon#about to read 6, iclass 18, count 2 2006.285.06:37:33.98#ibcon#read 6, iclass 18, count 2 2006.285.06:37:33.98#ibcon#end of sib2, iclass 18, count 2 2006.285.06:37:33.98#ibcon#*mode == 0, iclass 18, count 2 2006.285.06:37:33.98#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.06:37:33.98#ibcon#[25=AT07-04\r\n] 2006.285.06:37:33.98#ibcon#*before write, iclass 18, count 2 2006.285.06:37:33.98#ibcon#enter sib2, iclass 18, count 2 2006.285.06:37:33.98#ibcon#flushed, iclass 18, count 2 2006.285.06:37:33.98#ibcon#about to write, iclass 18, count 2 2006.285.06:37:33.98#ibcon#wrote, iclass 18, count 2 2006.285.06:37:33.98#ibcon#about to read 3, iclass 18, count 2 2006.285.06:37:34.01#ibcon#read 3, iclass 18, count 2 2006.285.06:37:34.01#ibcon#about to read 4, iclass 18, count 2 2006.285.06:37:34.01#ibcon#read 4, iclass 18, count 2 2006.285.06:37:34.01#ibcon#about to read 5, iclass 18, count 2 2006.285.06:37:34.01#ibcon#read 5, iclass 18, count 2 2006.285.06:37:34.01#ibcon#about to read 6, iclass 18, count 2 2006.285.06:37:34.01#ibcon#read 6, iclass 18, count 2 2006.285.06:37:34.01#ibcon#end of sib2, iclass 18, count 2 2006.285.06:37:34.01#ibcon#*after write, iclass 18, count 2 2006.285.06:37:34.01#ibcon#*before return 0, iclass 18, count 2 2006.285.06:37:34.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:37:34.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:37:34.01#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.06:37:34.01#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:34.01#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:37:34.13#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:37:34.13#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:37:34.13#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:37:34.13#ibcon#first serial, iclass 18, count 0 2006.285.06:37:34.13#ibcon#enter sib2, iclass 18, count 0 2006.285.06:37:34.13#ibcon#flushed, iclass 18, count 0 2006.285.06:37:34.13#ibcon#about to write, iclass 18, count 0 2006.285.06:37:34.13#ibcon#wrote, iclass 18, count 0 2006.285.06:37:34.13#ibcon#about to read 3, iclass 18, count 0 2006.285.06:37:34.15#ibcon#read 3, iclass 18, count 0 2006.285.06:37:34.15#ibcon#about to read 4, iclass 18, count 0 2006.285.06:37:34.15#ibcon#read 4, iclass 18, count 0 2006.285.06:37:34.15#ibcon#about to read 5, iclass 18, count 0 2006.285.06:37:34.15#ibcon#read 5, iclass 18, count 0 2006.285.06:37:34.15#ibcon#about to read 6, iclass 18, count 0 2006.285.06:37:34.15#ibcon#read 6, iclass 18, count 0 2006.285.06:37:34.15#ibcon#end of sib2, iclass 18, count 0 2006.285.06:37:34.15#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:37:34.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:37:34.15#ibcon#[25=USB\r\n] 2006.285.06:37:34.15#ibcon#*before write, iclass 18, count 0 2006.285.06:37:34.15#ibcon#enter sib2, iclass 18, count 0 2006.285.06:37:34.15#ibcon#flushed, iclass 18, count 0 2006.285.06:37:34.15#ibcon#about to write, iclass 18, count 0 2006.285.06:37:34.15#ibcon#wrote, iclass 18, count 0 2006.285.06:37:34.15#ibcon#about to read 3, iclass 18, count 0 2006.285.06:37:34.18#ibcon#read 3, iclass 18, count 0 2006.285.06:37:34.18#ibcon#about to read 4, iclass 18, count 0 2006.285.06:37:34.18#ibcon#read 4, iclass 18, count 0 2006.285.06:37:34.18#ibcon#about to read 5, iclass 18, count 0 2006.285.06:37:34.18#ibcon#read 5, iclass 18, count 0 2006.285.06:37:34.18#ibcon#about to read 6, iclass 18, count 0 2006.285.06:37:34.18#ibcon#read 6, iclass 18, count 0 2006.285.06:37:34.18#ibcon#end of sib2, iclass 18, count 0 2006.285.06:37:34.18#ibcon#*after write, iclass 18, count 0 2006.285.06:37:34.18#ibcon#*before return 0, iclass 18, count 0 2006.285.06:37:34.18#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:37:34.18#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:37:34.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:37:34.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:37:34.18$vck44/valo=8,884.99 2006.285.06:37:34.18#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.06:37:34.18#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.06:37:34.18#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:34.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:37:34.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:37:34.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:37:34.18#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:37:34.18#ibcon#first serial, iclass 20, count 0 2006.285.06:37:34.18#ibcon#enter sib2, iclass 20, count 0 2006.285.06:37:34.18#ibcon#flushed, iclass 20, count 0 2006.285.06:37:34.18#ibcon#about to write, iclass 20, count 0 2006.285.06:37:34.18#ibcon#wrote, iclass 20, count 0 2006.285.06:37:34.18#ibcon#about to read 3, iclass 20, count 0 2006.285.06:37:34.20#ibcon#read 3, iclass 20, count 0 2006.285.06:37:34.20#ibcon#about to read 4, iclass 20, count 0 2006.285.06:37:34.20#ibcon#read 4, iclass 20, count 0 2006.285.06:37:34.20#ibcon#about to read 5, iclass 20, count 0 2006.285.06:37:34.20#ibcon#read 5, iclass 20, count 0 2006.285.06:37:34.20#ibcon#about to read 6, iclass 20, count 0 2006.285.06:37:34.20#ibcon#read 6, iclass 20, count 0 2006.285.06:37:34.20#ibcon#end of sib2, iclass 20, count 0 2006.285.06:37:34.20#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:37:34.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:37:34.20#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:37:34.20#ibcon#*before write, iclass 20, count 0 2006.285.06:37:34.20#ibcon#enter sib2, iclass 20, count 0 2006.285.06:37:34.20#ibcon#flushed, iclass 20, count 0 2006.285.06:37:34.20#ibcon#about to write, iclass 20, count 0 2006.285.06:37:34.20#ibcon#wrote, iclass 20, count 0 2006.285.06:37:34.20#ibcon#about to read 3, iclass 20, count 0 2006.285.06:37:34.24#ibcon#read 3, iclass 20, count 0 2006.285.06:37:34.24#ibcon#about to read 4, iclass 20, count 0 2006.285.06:37:34.24#ibcon#read 4, iclass 20, count 0 2006.285.06:37:34.24#ibcon#about to read 5, iclass 20, count 0 2006.285.06:37:34.24#ibcon#read 5, iclass 20, count 0 2006.285.06:37:34.24#ibcon#about to read 6, iclass 20, count 0 2006.285.06:37:34.24#ibcon#read 6, iclass 20, count 0 2006.285.06:37:34.24#ibcon#end of sib2, iclass 20, count 0 2006.285.06:37:34.24#ibcon#*after write, iclass 20, count 0 2006.285.06:37:34.24#ibcon#*before return 0, iclass 20, count 0 2006.285.06:37:34.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:37:34.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:37:34.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:37:34.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:37:34.24$vck44/va=8,3 2006.285.06:37:34.24#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.06:37:34.24#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.06:37:34.24#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:34.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:37:34.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:37:34.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:37:34.30#ibcon#enter wrdev, iclass 22, count 2 2006.285.06:37:34.30#ibcon#first serial, iclass 22, count 2 2006.285.06:37:34.30#ibcon#enter sib2, iclass 22, count 2 2006.285.06:37:34.30#ibcon#flushed, iclass 22, count 2 2006.285.06:37:34.30#ibcon#about to write, iclass 22, count 2 2006.285.06:37:34.30#ibcon#wrote, iclass 22, count 2 2006.285.06:37:34.30#ibcon#about to read 3, iclass 22, count 2 2006.285.06:37:34.32#ibcon#read 3, iclass 22, count 2 2006.285.06:37:34.32#ibcon#about to read 4, iclass 22, count 2 2006.285.06:37:34.32#ibcon#read 4, iclass 22, count 2 2006.285.06:37:34.32#ibcon#about to read 5, iclass 22, count 2 2006.285.06:37:34.32#ibcon#read 5, iclass 22, count 2 2006.285.06:37:34.32#ibcon#about to read 6, iclass 22, count 2 2006.285.06:37:34.32#ibcon#read 6, iclass 22, count 2 2006.285.06:37:34.32#ibcon#end of sib2, iclass 22, count 2 2006.285.06:37:34.32#ibcon#*mode == 0, iclass 22, count 2 2006.285.06:37:34.32#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.06:37:34.32#ibcon#[25=AT08-03\r\n] 2006.285.06:37:34.32#ibcon#*before write, iclass 22, count 2 2006.285.06:37:34.32#ibcon#enter sib2, iclass 22, count 2 2006.285.06:37:34.32#ibcon#flushed, iclass 22, count 2 2006.285.06:37:34.32#ibcon#about to write, iclass 22, count 2 2006.285.06:37:34.32#ibcon#wrote, iclass 22, count 2 2006.285.06:37:34.32#ibcon#about to read 3, iclass 22, count 2 2006.285.06:37:34.35#ibcon#read 3, iclass 22, count 2 2006.285.06:37:34.35#ibcon#about to read 4, iclass 22, count 2 2006.285.06:37:34.35#ibcon#read 4, iclass 22, count 2 2006.285.06:37:34.35#ibcon#about to read 5, iclass 22, count 2 2006.285.06:37:34.35#ibcon#read 5, iclass 22, count 2 2006.285.06:37:34.35#ibcon#about to read 6, iclass 22, count 2 2006.285.06:37:34.35#ibcon#read 6, iclass 22, count 2 2006.285.06:37:34.35#ibcon#end of sib2, iclass 22, count 2 2006.285.06:37:34.35#ibcon#*after write, iclass 22, count 2 2006.285.06:37:34.35#ibcon#*before return 0, iclass 22, count 2 2006.285.06:37:34.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:37:34.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.06:37:34.35#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.06:37:34.35#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:34.35#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:37:34.47#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:37:34.47#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:37:34.47#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:37:34.47#ibcon#first serial, iclass 22, count 0 2006.285.06:37:34.47#ibcon#enter sib2, iclass 22, count 0 2006.285.06:37:34.47#ibcon#flushed, iclass 22, count 0 2006.285.06:37:34.47#ibcon#about to write, iclass 22, count 0 2006.285.06:37:34.47#ibcon#wrote, iclass 22, count 0 2006.285.06:37:34.47#ibcon#about to read 3, iclass 22, count 0 2006.285.06:37:34.49#ibcon#read 3, iclass 22, count 0 2006.285.06:37:34.49#ibcon#about to read 4, iclass 22, count 0 2006.285.06:37:34.49#ibcon#read 4, iclass 22, count 0 2006.285.06:37:34.49#ibcon#about to read 5, iclass 22, count 0 2006.285.06:37:34.49#ibcon#read 5, iclass 22, count 0 2006.285.06:37:34.49#ibcon#about to read 6, iclass 22, count 0 2006.285.06:37:34.49#ibcon#read 6, iclass 22, count 0 2006.285.06:37:34.49#ibcon#end of sib2, iclass 22, count 0 2006.285.06:37:34.49#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:37:34.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:37:34.49#ibcon#[25=USB\r\n] 2006.285.06:37:34.49#ibcon#*before write, iclass 22, count 0 2006.285.06:37:34.49#ibcon#enter sib2, iclass 22, count 0 2006.285.06:37:34.49#ibcon#flushed, iclass 22, count 0 2006.285.06:37:34.49#ibcon#about to write, iclass 22, count 0 2006.285.06:37:34.49#ibcon#wrote, iclass 22, count 0 2006.285.06:37:34.49#ibcon#about to read 3, iclass 22, count 0 2006.285.06:37:34.52#ibcon#read 3, iclass 22, count 0 2006.285.06:37:34.52#ibcon#about to read 4, iclass 22, count 0 2006.285.06:37:34.52#ibcon#read 4, iclass 22, count 0 2006.285.06:37:34.52#ibcon#about to read 5, iclass 22, count 0 2006.285.06:37:34.52#ibcon#read 5, iclass 22, count 0 2006.285.06:37:34.52#ibcon#about to read 6, iclass 22, count 0 2006.285.06:37:34.52#ibcon#read 6, iclass 22, count 0 2006.285.06:37:34.52#ibcon#end of sib2, iclass 22, count 0 2006.285.06:37:34.52#ibcon#*after write, iclass 22, count 0 2006.285.06:37:34.52#ibcon#*before return 0, iclass 22, count 0 2006.285.06:37:34.52#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:37:34.52#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.06:37:34.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:37:34.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:37:34.52$vck44/vblo=1,629.99 2006.285.06:37:34.52#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.06:37:34.52#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.06:37:34.52#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:34.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:37:34.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:37:34.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:37:34.52#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:37:34.52#ibcon#first serial, iclass 24, count 0 2006.285.06:37:34.52#ibcon#enter sib2, iclass 24, count 0 2006.285.06:37:34.52#ibcon#flushed, iclass 24, count 0 2006.285.06:37:34.52#ibcon#about to write, iclass 24, count 0 2006.285.06:37:34.52#ibcon#wrote, iclass 24, count 0 2006.285.06:37:34.52#ibcon#about to read 3, iclass 24, count 0 2006.285.06:37:34.54#ibcon#read 3, iclass 24, count 0 2006.285.06:37:34.54#ibcon#about to read 4, iclass 24, count 0 2006.285.06:37:34.54#ibcon#read 4, iclass 24, count 0 2006.285.06:37:34.54#ibcon#about to read 5, iclass 24, count 0 2006.285.06:37:34.54#ibcon#read 5, iclass 24, count 0 2006.285.06:37:34.54#ibcon#about to read 6, iclass 24, count 0 2006.285.06:37:34.54#ibcon#read 6, iclass 24, count 0 2006.285.06:37:34.54#ibcon#end of sib2, iclass 24, count 0 2006.285.06:37:34.54#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:37:34.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:37:34.54#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:37:34.54#ibcon#*before write, iclass 24, count 0 2006.285.06:37:34.54#ibcon#enter sib2, iclass 24, count 0 2006.285.06:37:34.54#ibcon#flushed, iclass 24, count 0 2006.285.06:37:34.54#ibcon#about to write, iclass 24, count 0 2006.285.06:37:34.54#ibcon#wrote, iclass 24, count 0 2006.285.06:37:34.54#ibcon#about to read 3, iclass 24, count 0 2006.285.06:37:34.58#ibcon#read 3, iclass 24, count 0 2006.285.06:37:34.58#ibcon#about to read 4, iclass 24, count 0 2006.285.06:37:34.58#ibcon#read 4, iclass 24, count 0 2006.285.06:37:34.58#ibcon#about to read 5, iclass 24, count 0 2006.285.06:37:34.58#ibcon#read 5, iclass 24, count 0 2006.285.06:37:34.58#ibcon#about to read 6, iclass 24, count 0 2006.285.06:37:34.58#ibcon#read 6, iclass 24, count 0 2006.285.06:37:34.58#ibcon#end of sib2, iclass 24, count 0 2006.285.06:37:34.58#ibcon#*after write, iclass 24, count 0 2006.285.06:37:34.58#ibcon#*before return 0, iclass 24, count 0 2006.285.06:37:34.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:37:34.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.06:37:34.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:37:34.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:37:34.58$vck44/vb=1,4 2006.285.06:37:34.58#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.06:37:34.58#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.06:37:34.58#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:34.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:37:34.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:37:34.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:37:34.58#ibcon#enter wrdev, iclass 26, count 2 2006.285.06:37:34.58#ibcon#first serial, iclass 26, count 2 2006.285.06:37:34.58#ibcon#enter sib2, iclass 26, count 2 2006.285.06:37:34.58#ibcon#flushed, iclass 26, count 2 2006.285.06:37:34.58#ibcon#about to write, iclass 26, count 2 2006.285.06:37:34.58#ibcon#wrote, iclass 26, count 2 2006.285.06:37:34.58#ibcon#about to read 3, iclass 26, count 2 2006.285.06:37:34.60#ibcon#read 3, iclass 26, count 2 2006.285.06:37:34.60#ibcon#about to read 4, iclass 26, count 2 2006.285.06:37:34.60#ibcon#read 4, iclass 26, count 2 2006.285.06:37:34.60#ibcon#about to read 5, iclass 26, count 2 2006.285.06:37:34.60#ibcon#read 5, iclass 26, count 2 2006.285.06:37:34.60#ibcon#about to read 6, iclass 26, count 2 2006.285.06:37:34.60#ibcon#read 6, iclass 26, count 2 2006.285.06:37:34.60#ibcon#end of sib2, iclass 26, count 2 2006.285.06:37:34.60#ibcon#*mode == 0, iclass 26, count 2 2006.285.06:37:34.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.06:37:34.60#ibcon#[27=AT01-04\r\n] 2006.285.06:37:34.60#ibcon#*before write, iclass 26, count 2 2006.285.06:37:34.60#ibcon#enter sib2, iclass 26, count 2 2006.285.06:37:34.60#ibcon#flushed, iclass 26, count 2 2006.285.06:37:34.60#ibcon#about to write, iclass 26, count 2 2006.285.06:37:34.60#ibcon#wrote, iclass 26, count 2 2006.285.06:37:34.60#ibcon#about to read 3, iclass 26, count 2 2006.285.06:37:34.63#ibcon#read 3, iclass 26, count 2 2006.285.06:37:34.63#ibcon#about to read 4, iclass 26, count 2 2006.285.06:37:34.63#ibcon#read 4, iclass 26, count 2 2006.285.06:37:34.63#ibcon#about to read 5, iclass 26, count 2 2006.285.06:37:34.63#ibcon#read 5, iclass 26, count 2 2006.285.06:37:34.63#ibcon#about to read 6, iclass 26, count 2 2006.285.06:37:34.63#ibcon#read 6, iclass 26, count 2 2006.285.06:37:34.63#ibcon#end of sib2, iclass 26, count 2 2006.285.06:37:34.63#ibcon#*after write, iclass 26, count 2 2006.285.06:37:34.63#ibcon#*before return 0, iclass 26, count 2 2006.285.06:37:34.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:37:34.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.06:37:34.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.06:37:34.63#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:34.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:37:34.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:37:34.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:37:34.75#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:37:34.75#ibcon#first serial, iclass 26, count 0 2006.285.06:37:34.75#ibcon#enter sib2, iclass 26, count 0 2006.285.06:37:34.75#ibcon#flushed, iclass 26, count 0 2006.285.06:37:34.75#ibcon#about to write, iclass 26, count 0 2006.285.06:37:34.75#ibcon#wrote, iclass 26, count 0 2006.285.06:37:34.75#ibcon#about to read 3, iclass 26, count 0 2006.285.06:37:34.77#ibcon#read 3, iclass 26, count 0 2006.285.06:37:34.77#ibcon#about to read 4, iclass 26, count 0 2006.285.06:37:34.77#ibcon#read 4, iclass 26, count 0 2006.285.06:37:34.77#ibcon#about to read 5, iclass 26, count 0 2006.285.06:37:34.77#ibcon#read 5, iclass 26, count 0 2006.285.06:37:34.77#ibcon#about to read 6, iclass 26, count 0 2006.285.06:37:34.77#ibcon#read 6, iclass 26, count 0 2006.285.06:37:34.77#ibcon#end of sib2, iclass 26, count 0 2006.285.06:37:34.77#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:37:34.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:37:34.77#ibcon#[27=USB\r\n] 2006.285.06:37:34.77#ibcon#*before write, iclass 26, count 0 2006.285.06:37:34.77#ibcon#enter sib2, iclass 26, count 0 2006.285.06:37:34.77#ibcon#flushed, iclass 26, count 0 2006.285.06:37:34.77#ibcon#about to write, iclass 26, count 0 2006.285.06:37:34.77#ibcon#wrote, iclass 26, count 0 2006.285.06:37:34.77#ibcon#about to read 3, iclass 26, count 0 2006.285.06:37:34.80#ibcon#read 3, iclass 26, count 0 2006.285.06:37:34.80#ibcon#about to read 4, iclass 26, count 0 2006.285.06:37:34.80#ibcon#read 4, iclass 26, count 0 2006.285.06:37:34.80#ibcon#about to read 5, iclass 26, count 0 2006.285.06:37:34.80#ibcon#read 5, iclass 26, count 0 2006.285.06:37:34.80#ibcon#about to read 6, iclass 26, count 0 2006.285.06:37:34.80#ibcon#read 6, iclass 26, count 0 2006.285.06:37:34.80#ibcon#end of sib2, iclass 26, count 0 2006.285.06:37:34.80#ibcon#*after write, iclass 26, count 0 2006.285.06:37:34.80#ibcon#*before return 0, iclass 26, count 0 2006.285.06:37:34.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:37:34.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.06:37:34.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:37:34.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:37:34.80$vck44/vblo=2,634.99 2006.285.06:37:34.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.06:37:34.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.06:37:34.80#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:34.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:37:34.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:37:34.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:37:34.80#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:37:34.80#ibcon#first serial, iclass 28, count 0 2006.285.06:37:34.80#ibcon#enter sib2, iclass 28, count 0 2006.285.06:37:34.80#ibcon#flushed, iclass 28, count 0 2006.285.06:37:34.80#ibcon#about to write, iclass 28, count 0 2006.285.06:37:34.80#ibcon#wrote, iclass 28, count 0 2006.285.06:37:34.80#ibcon#about to read 3, iclass 28, count 0 2006.285.06:37:34.82#ibcon#read 3, iclass 28, count 0 2006.285.06:37:34.82#ibcon#about to read 4, iclass 28, count 0 2006.285.06:37:34.82#ibcon#read 4, iclass 28, count 0 2006.285.06:37:34.82#ibcon#about to read 5, iclass 28, count 0 2006.285.06:37:34.82#ibcon#read 5, iclass 28, count 0 2006.285.06:37:34.82#ibcon#about to read 6, iclass 28, count 0 2006.285.06:37:34.82#ibcon#read 6, iclass 28, count 0 2006.285.06:37:34.82#ibcon#end of sib2, iclass 28, count 0 2006.285.06:37:34.82#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:37:34.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:37:34.82#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:37:34.82#ibcon#*before write, iclass 28, count 0 2006.285.06:37:34.82#ibcon#enter sib2, iclass 28, count 0 2006.285.06:37:34.82#ibcon#flushed, iclass 28, count 0 2006.285.06:37:34.82#ibcon#about to write, iclass 28, count 0 2006.285.06:37:34.82#ibcon#wrote, iclass 28, count 0 2006.285.06:37:34.82#ibcon#about to read 3, iclass 28, count 0 2006.285.06:37:34.86#ibcon#read 3, iclass 28, count 0 2006.285.06:37:34.86#ibcon#about to read 4, iclass 28, count 0 2006.285.06:37:34.86#ibcon#read 4, iclass 28, count 0 2006.285.06:37:34.86#ibcon#about to read 5, iclass 28, count 0 2006.285.06:37:34.86#ibcon#read 5, iclass 28, count 0 2006.285.06:37:34.86#ibcon#about to read 6, iclass 28, count 0 2006.285.06:37:34.86#ibcon#read 6, iclass 28, count 0 2006.285.06:37:34.86#ibcon#end of sib2, iclass 28, count 0 2006.285.06:37:34.86#ibcon#*after write, iclass 28, count 0 2006.285.06:37:34.86#ibcon#*before return 0, iclass 28, count 0 2006.285.06:37:34.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:37:34.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.06:37:34.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:37:34.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:37:34.86$vck44/vb=2,5 2006.285.06:37:34.86#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.06:37:34.86#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.06:37:34.86#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:34.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:37:34.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:37:34.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:37:34.92#ibcon#enter wrdev, iclass 30, count 2 2006.285.06:37:34.92#ibcon#first serial, iclass 30, count 2 2006.285.06:37:34.92#ibcon#enter sib2, iclass 30, count 2 2006.285.06:37:34.92#ibcon#flushed, iclass 30, count 2 2006.285.06:37:34.92#ibcon#about to write, iclass 30, count 2 2006.285.06:37:34.92#ibcon#wrote, iclass 30, count 2 2006.285.06:37:34.92#ibcon#about to read 3, iclass 30, count 2 2006.285.06:37:34.94#ibcon#read 3, iclass 30, count 2 2006.285.06:37:34.94#ibcon#about to read 4, iclass 30, count 2 2006.285.06:37:34.94#ibcon#read 4, iclass 30, count 2 2006.285.06:37:34.94#ibcon#about to read 5, iclass 30, count 2 2006.285.06:37:34.94#ibcon#read 5, iclass 30, count 2 2006.285.06:37:34.94#ibcon#about to read 6, iclass 30, count 2 2006.285.06:37:34.94#ibcon#read 6, iclass 30, count 2 2006.285.06:37:34.94#ibcon#end of sib2, iclass 30, count 2 2006.285.06:37:34.94#ibcon#*mode == 0, iclass 30, count 2 2006.285.06:37:34.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.06:37:34.94#ibcon#[27=AT02-05\r\n] 2006.285.06:37:34.94#ibcon#*before write, iclass 30, count 2 2006.285.06:37:34.94#ibcon#enter sib2, iclass 30, count 2 2006.285.06:37:34.94#ibcon#flushed, iclass 30, count 2 2006.285.06:37:34.94#ibcon#about to write, iclass 30, count 2 2006.285.06:37:34.94#ibcon#wrote, iclass 30, count 2 2006.285.06:37:34.94#ibcon#about to read 3, iclass 30, count 2 2006.285.06:37:34.97#ibcon#read 3, iclass 30, count 2 2006.285.06:37:34.97#ibcon#about to read 4, iclass 30, count 2 2006.285.06:37:34.97#ibcon#read 4, iclass 30, count 2 2006.285.06:37:34.97#ibcon#about to read 5, iclass 30, count 2 2006.285.06:37:34.97#ibcon#read 5, iclass 30, count 2 2006.285.06:37:34.97#ibcon#about to read 6, iclass 30, count 2 2006.285.06:37:34.97#ibcon#read 6, iclass 30, count 2 2006.285.06:37:34.97#ibcon#end of sib2, iclass 30, count 2 2006.285.06:37:34.97#ibcon#*after write, iclass 30, count 2 2006.285.06:37:34.97#ibcon#*before return 0, iclass 30, count 2 2006.285.06:37:34.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:37:34.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.06:37:34.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.06:37:34.97#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:34.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:37:35.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:37:35.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:37:35.09#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:37:35.09#ibcon#first serial, iclass 30, count 0 2006.285.06:37:35.09#ibcon#enter sib2, iclass 30, count 0 2006.285.06:37:35.09#ibcon#flushed, iclass 30, count 0 2006.285.06:37:35.09#ibcon#about to write, iclass 30, count 0 2006.285.06:37:35.09#ibcon#wrote, iclass 30, count 0 2006.285.06:37:35.09#ibcon#about to read 3, iclass 30, count 0 2006.285.06:37:35.11#ibcon#read 3, iclass 30, count 0 2006.285.06:37:35.11#ibcon#about to read 4, iclass 30, count 0 2006.285.06:37:35.11#ibcon#read 4, iclass 30, count 0 2006.285.06:37:35.11#ibcon#about to read 5, iclass 30, count 0 2006.285.06:37:35.11#ibcon#read 5, iclass 30, count 0 2006.285.06:37:35.11#ibcon#about to read 6, iclass 30, count 0 2006.285.06:37:35.11#ibcon#read 6, iclass 30, count 0 2006.285.06:37:35.11#ibcon#end of sib2, iclass 30, count 0 2006.285.06:37:35.11#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:37:35.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:37:35.11#ibcon#[27=USB\r\n] 2006.285.06:37:35.11#ibcon#*before write, iclass 30, count 0 2006.285.06:37:35.11#ibcon#enter sib2, iclass 30, count 0 2006.285.06:37:35.11#ibcon#flushed, iclass 30, count 0 2006.285.06:37:35.11#ibcon#about to write, iclass 30, count 0 2006.285.06:37:35.11#ibcon#wrote, iclass 30, count 0 2006.285.06:37:35.11#ibcon#about to read 3, iclass 30, count 0 2006.285.06:37:35.14#ibcon#read 3, iclass 30, count 0 2006.285.06:37:35.14#ibcon#about to read 4, iclass 30, count 0 2006.285.06:37:35.14#ibcon#read 4, iclass 30, count 0 2006.285.06:37:35.14#ibcon#about to read 5, iclass 30, count 0 2006.285.06:37:35.14#ibcon#read 5, iclass 30, count 0 2006.285.06:37:35.14#ibcon#about to read 6, iclass 30, count 0 2006.285.06:37:35.14#ibcon#read 6, iclass 30, count 0 2006.285.06:37:35.14#ibcon#end of sib2, iclass 30, count 0 2006.285.06:37:35.14#ibcon#*after write, iclass 30, count 0 2006.285.06:37:35.14#ibcon#*before return 0, iclass 30, count 0 2006.285.06:37:35.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:37:35.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.06:37:35.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:37:35.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:37:35.14$vck44/vblo=3,649.99 2006.285.06:37:35.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.06:37:35.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.06:37:35.14#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:35.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:37:35.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:37:35.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:37:35.14#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:37:35.14#ibcon#first serial, iclass 32, count 0 2006.285.06:37:35.14#ibcon#enter sib2, iclass 32, count 0 2006.285.06:37:35.14#ibcon#flushed, iclass 32, count 0 2006.285.06:37:35.14#ibcon#about to write, iclass 32, count 0 2006.285.06:37:35.14#ibcon#wrote, iclass 32, count 0 2006.285.06:37:35.14#ibcon#about to read 3, iclass 32, count 0 2006.285.06:37:35.16#ibcon#read 3, iclass 32, count 0 2006.285.06:37:35.16#ibcon#about to read 4, iclass 32, count 0 2006.285.06:37:35.16#ibcon#read 4, iclass 32, count 0 2006.285.06:37:35.16#ibcon#about to read 5, iclass 32, count 0 2006.285.06:37:35.16#ibcon#read 5, iclass 32, count 0 2006.285.06:37:35.16#ibcon#about to read 6, iclass 32, count 0 2006.285.06:37:35.16#ibcon#read 6, iclass 32, count 0 2006.285.06:37:35.16#ibcon#end of sib2, iclass 32, count 0 2006.285.06:37:35.16#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:37:35.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:37:35.16#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:37:35.16#ibcon#*before write, iclass 32, count 0 2006.285.06:37:35.16#ibcon#enter sib2, iclass 32, count 0 2006.285.06:37:35.16#ibcon#flushed, iclass 32, count 0 2006.285.06:37:35.16#ibcon#about to write, iclass 32, count 0 2006.285.06:37:35.16#ibcon#wrote, iclass 32, count 0 2006.285.06:37:35.16#ibcon#about to read 3, iclass 32, count 0 2006.285.06:37:35.20#ibcon#read 3, iclass 32, count 0 2006.285.06:37:35.20#ibcon#about to read 4, iclass 32, count 0 2006.285.06:37:35.20#ibcon#read 4, iclass 32, count 0 2006.285.06:37:35.20#ibcon#about to read 5, iclass 32, count 0 2006.285.06:37:35.20#ibcon#read 5, iclass 32, count 0 2006.285.06:37:35.20#ibcon#about to read 6, iclass 32, count 0 2006.285.06:37:35.20#ibcon#read 6, iclass 32, count 0 2006.285.06:37:35.20#ibcon#end of sib2, iclass 32, count 0 2006.285.06:37:35.20#ibcon#*after write, iclass 32, count 0 2006.285.06:37:35.20#ibcon#*before return 0, iclass 32, count 0 2006.285.06:37:35.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:37:35.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:37:35.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:37:35.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:37:35.20$vck44/vb=3,4 2006.285.06:37:35.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.06:37:35.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.06:37:35.20#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:35.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:37:35.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:37:35.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:37:35.26#ibcon#enter wrdev, iclass 34, count 2 2006.285.06:37:35.26#ibcon#first serial, iclass 34, count 2 2006.285.06:37:35.26#ibcon#enter sib2, iclass 34, count 2 2006.285.06:37:35.26#ibcon#flushed, iclass 34, count 2 2006.285.06:37:35.26#ibcon#about to write, iclass 34, count 2 2006.285.06:37:35.26#ibcon#wrote, iclass 34, count 2 2006.285.06:37:35.26#ibcon#about to read 3, iclass 34, count 2 2006.285.06:37:35.28#ibcon#read 3, iclass 34, count 2 2006.285.06:37:35.28#ibcon#about to read 4, iclass 34, count 2 2006.285.06:37:35.28#ibcon#read 4, iclass 34, count 2 2006.285.06:37:35.28#ibcon#about to read 5, iclass 34, count 2 2006.285.06:37:35.28#ibcon#read 5, iclass 34, count 2 2006.285.06:37:35.28#ibcon#about to read 6, iclass 34, count 2 2006.285.06:37:35.28#ibcon#read 6, iclass 34, count 2 2006.285.06:37:35.28#ibcon#end of sib2, iclass 34, count 2 2006.285.06:37:35.28#ibcon#*mode == 0, iclass 34, count 2 2006.285.06:37:35.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.06:37:35.28#ibcon#[27=AT03-04\r\n] 2006.285.06:37:35.28#ibcon#*before write, iclass 34, count 2 2006.285.06:37:35.28#ibcon#enter sib2, iclass 34, count 2 2006.285.06:37:35.28#ibcon#flushed, iclass 34, count 2 2006.285.06:37:35.28#ibcon#about to write, iclass 34, count 2 2006.285.06:37:35.28#ibcon#wrote, iclass 34, count 2 2006.285.06:37:35.28#ibcon#about to read 3, iclass 34, count 2 2006.285.06:37:35.31#ibcon#read 3, iclass 34, count 2 2006.285.06:37:35.31#ibcon#about to read 4, iclass 34, count 2 2006.285.06:37:35.31#ibcon#read 4, iclass 34, count 2 2006.285.06:37:35.31#ibcon#about to read 5, iclass 34, count 2 2006.285.06:37:35.31#ibcon#read 5, iclass 34, count 2 2006.285.06:37:35.31#ibcon#about to read 6, iclass 34, count 2 2006.285.06:37:35.31#ibcon#read 6, iclass 34, count 2 2006.285.06:37:35.31#ibcon#end of sib2, iclass 34, count 2 2006.285.06:37:35.31#ibcon#*after write, iclass 34, count 2 2006.285.06:37:35.31#ibcon#*before return 0, iclass 34, count 2 2006.285.06:37:35.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:37:35.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.06:37:35.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.06:37:35.31#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:35.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:37:35.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:37:35.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:37:35.43#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:37:35.43#ibcon#first serial, iclass 34, count 0 2006.285.06:37:35.43#ibcon#enter sib2, iclass 34, count 0 2006.285.06:37:35.43#ibcon#flushed, iclass 34, count 0 2006.285.06:37:35.43#ibcon#about to write, iclass 34, count 0 2006.285.06:37:35.43#ibcon#wrote, iclass 34, count 0 2006.285.06:37:35.43#ibcon#about to read 3, iclass 34, count 0 2006.285.06:37:35.45#ibcon#read 3, iclass 34, count 0 2006.285.06:37:35.45#ibcon#about to read 4, iclass 34, count 0 2006.285.06:37:35.45#ibcon#read 4, iclass 34, count 0 2006.285.06:37:35.45#ibcon#about to read 5, iclass 34, count 0 2006.285.06:37:35.45#ibcon#read 5, iclass 34, count 0 2006.285.06:37:35.45#ibcon#about to read 6, iclass 34, count 0 2006.285.06:37:35.45#ibcon#read 6, iclass 34, count 0 2006.285.06:37:35.45#ibcon#end of sib2, iclass 34, count 0 2006.285.06:37:35.45#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:37:35.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:37:35.45#ibcon#[27=USB\r\n] 2006.285.06:37:35.45#ibcon#*before write, iclass 34, count 0 2006.285.06:37:35.45#ibcon#enter sib2, iclass 34, count 0 2006.285.06:37:35.45#ibcon#flushed, iclass 34, count 0 2006.285.06:37:35.45#ibcon#about to write, iclass 34, count 0 2006.285.06:37:35.45#ibcon#wrote, iclass 34, count 0 2006.285.06:37:35.45#ibcon#about to read 3, iclass 34, count 0 2006.285.06:37:35.48#ibcon#read 3, iclass 34, count 0 2006.285.06:37:35.48#ibcon#about to read 4, iclass 34, count 0 2006.285.06:37:35.48#ibcon#read 4, iclass 34, count 0 2006.285.06:37:35.48#ibcon#about to read 5, iclass 34, count 0 2006.285.06:37:35.48#ibcon#read 5, iclass 34, count 0 2006.285.06:37:35.48#ibcon#about to read 6, iclass 34, count 0 2006.285.06:37:35.48#ibcon#read 6, iclass 34, count 0 2006.285.06:37:35.48#ibcon#end of sib2, iclass 34, count 0 2006.285.06:37:35.48#ibcon#*after write, iclass 34, count 0 2006.285.06:37:35.48#ibcon#*before return 0, iclass 34, count 0 2006.285.06:37:35.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:37:35.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.06:37:35.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:37:35.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:37:35.48$vck44/vblo=4,679.99 2006.285.06:37:35.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.06:37:35.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.06:37:35.48#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:35.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:37:35.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:37:35.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:37:35.48#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:37:35.48#ibcon#first serial, iclass 36, count 0 2006.285.06:37:35.48#ibcon#enter sib2, iclass 36, count 0 2006.285.06:37:35.48#ibcon#flushed, iclass 36, count 0 2006.285.06:37:35.48#ibcon#about to write, iclass 36, count 0 2006.285.06:37:35.48#ibcon#wrote, iclass 36, count 0 2006.285.06:37:35.48#ibcon#about to read 3, iclass 36, count 0 2006.285.06:37:35.50#ibcon#read 3, iclass 36, count 0 2006.285.06:37:35.50#ibcon#about to read 4, iclass 36, count 0 2006.285.06:37:35.50#ibcon#read 4, iclass 36, count 0 2006.285.06:37:35.50#ibcon#about to read 5, iclass 36, count 0 2006.285.06:37:35.50#ibcon#read 5, iclass 36, count 0 2006.285.06:37:35.50#ibcon#about to read 6, iclass 36, count 0 2006.285.06:37:35.50#ibcon#read 6, iclass 36, count 0 2006.285.06:37:35.50#ibcon#end of sib2, iclass 36, count 0 2006.285.06:37:35.50#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:37:35.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:37:35.50#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:37:35.50#ibcon#*before write, iclass 36, count 0 2006.285.06:37:35.50#ibcon#enter sib2, iclass 36, count 0 2006.285.06:37:35.50#ibcon#flushed, iclass 36, count 0 2006.285.06:37:35.50#ibcon#about to write, iclass 36, count 0 2006.285.06:37:35.50#ibcon#wrote, iclass 36, count 0 2006.285.06:37:35.50#ibcon#about to read 3, iclass 36, count 0 2006.285.06:37:35.54#ibcon#read 3, iclass 36, count 0 2006.285.06:37:35.54#ibcon#about to read 4, iclass 36, count 0 2006.285.06:37:35.54#ibcon#read 4, iclass 36, count 0 2006.285.06:37:35.54#ibcon#about to read 5, iclass 36, count 0 2006.285.06:37:35.54#ibcon#read 5, iclass 36, count 0 2006.285.06:37:35.54#ibcon#about to read 6, iclass 36, count 0 2006.285.06:37:35.54#ibcon#read 6, iclass 36, count 0 2006.285.06:37:35.54#ibcon#end of sib2, iclass 36, count 0 2006.285.06:37:35.54#ibcon#*after write, iclass 36, count 0 2006.285.06:37:35.54#ibcon#*before return 0, iclass 36, count 0 2006.285.06:37:35.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:37:35.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.06:37:35.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:37:35.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:37:35.54$vck44/vb=4,5 2006.285.06:37:35.54#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.06:37:35.54#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.06:37:35.54#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:35.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:37:35.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:37:35.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:37:35.60#ibcon#enter wrdev, iclass 38, count 2 2006.285.06:37:35.60#ibcon#first serial, iclass 38, count 2 2006.285.06:37:35.60#ibcon#enter sib2, iclass 38, count 2 2006.285.06:37:35.60#ibcon#flushed, iclass 38, count 2 2006.285.06:37:35.60#ibcon#about to write, iclass 38, count 2 2006.285.06:37:35.60#ibcon#wrote, iclass 38, count 2 2006.285.06:37:35.60#ibcon#about to read 3, iclass 38, count 2 2006.285.06:37:35.62#ibcon#read 3, iclass 38, count 2 2006.285.06:37:35.62#ibcon#about to read 4, iclass 38, count 2 2006.285.06:37:35.62#ibcon#read 4, iclass 38, count 2 2006.285.06:37:35.62#ibcon#about to read 5, iclass 38, count 2 2006.285.06:37:35.62#ibcon#read 5, iclass 38, count 2 2006.285.06:37:35.62#ibcon#about to read 6, iclass 38, count 2 2006.285.06:37:35.62#ibcon#read 6, iclass 38, count 2 2006.285.06:37:35.62#ibcon#end of sib2, iclass 38, count 2 2006.285.06:37:35.62#ibcon#*mode == 0, iclass 38, count 2 2006.285.06:37:35.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.06:37:35.62#ibcon#[27=AT04-05\r\n] 2006.285.06:37:35.62#ibcon#*before write, iclass 38, count 2 2006.285.06:37:35.62#ibcon#enter sib2, iclass 38, count 2 2006.285.06:37:35.62#ibcon#flushed, iclass 38, count 2 2006.285.06:37:35.62#ibcon#about to write, iclass 38, count 2 2006.285.06:37:35.62#ibcon#wrote, iclass 38, count 2 2006.285.06:37:35.62#ibcon#about to read 3, iclass 38, count 2 2006.285.06:37:35.65#ibcon#read 3, iclass 38, count 2 2006.285.06:37:35.65#ibcon#about to read 4, iclass 38, count 2 2006.285.06:37:35.65#ibcon#read 4, iclass 38, count 2 2006.285.06:37:35.65#ibcon#about to read 5, iclass 38, count 2 2006.285.06:37:35.65#ibcon#read 5, iclass 38, count 2 2006.285.06:37:35.65#ibcon#about to read 6, iclass 38, count 2 2006.285.06:37:35.65#ibcon#read 6, iclass 38, count 2 2006.285.06:37:35.65#ibcon#end of sib2, iclass 38, count 2 2006.285.06:37:35.65#ibcon#*after write, iclass 38, count 2 2006.285.06:37:35.65#ibcon#*before return 0, iclass 38, count 2 2006.285.06:37:35.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:37:35.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.06:37:35.65#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.06:37:35.65#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:35.65#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:37:35.77#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:37:35.77#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:37:35.77#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:37:35.77#ibcon#first serial, iclass 38, count 0 2006.285.06:37:35.77#ibcon#enter sib2, iclass 38, count 0 2006.285.06:37:35.77#ibcon#flushed, iclass 38, count 0 2006.285.06:37:35.77#ibcon#about to write, iclass 38, count 0 2006.285.06:37:35.77#ibcon#wrote, iclass 38, count 0 2006.285.06:37:35.77#ibcon#about to read 3, iclass 38, count 0 2006.285.06:37:35.79#ibcon#read 3, iclass 38, count 0 2006.285.06:37:35.79#ibcon#about to read 4, iclass 38, count 0 2006.285.06:37:35.79#ibcon#read 4, iclass 38, count 0 2006.285.06:37:35.79#ibcon#about to read 5, iclass 38, count 0 2006.285.06:37:35.79#ibcon#read 5, iclass 38, count 0 2006.285.06:37:35.79#ibcon#about to read 6, iclass 38, count 0 2006.285.06:37:35.79#ibcon#read 6, iclass 38, count 0 2006.285.06:37:35.79#ibcon#end of sib2, iclass 38, count 0 2006.285.06:37:35.79#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:37:35.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:37:35.79#ibcon#[27=USB\r\n] 2006.285.06:37:35.79#ibcon#*before write, iclass 38, count 0 2006.285.06:37:35.79#ibcon#enter sib2, iclass 38, count 0 2006.285.06:37:35.79#ibcon#flushed, iclass 38, count 0 2006.285.06:37:35.79#ibcon#about to write, iclass 38, count 0 2006.285.06:37:35.79#ibcon#wrote, iclass 38, count 0 2006.285.06:37:35.79#ibcon#about to read 3, iclass 38, count 0 2006.285.06:37:35.82#ibcon#read 3, iclass 38, count 0 2006.285.06:37:35.82#ibcon#about to read 4, iclass 38, count 0 2006.285.06:37:35.82#ibcon#read 4, iclass 38, count 0 2006.285.06:37:35.82#ibcon#about to read 5, iclass 38, count 0 2006.285.06:37:35.82#ibcon#read 5, iclass 38, count 0 2006.285.06:37:35.82#ibcon#about to read 6, iclass 38, count 0 2006.285.06:37:35.82#ibcon#read 6, iclass 38, count 0 2006.285.06:37:35.82#ibcon#end of sib2, iclass 38, count 0 2006.285.06:37:35.82#ibcon#*after write, iclass 38, count 0 2006.285.06:37:35.82#ibcon#*before return 0, iclass 38, count 0 2006.285.06:37:35.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:37:35.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.06:37:35.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:37:35.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:37:35.82$vck44/vblo=5,709.99 2006.285.06:37:35.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.06:37:35.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.06:37:35.82#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:35.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:37:35.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:37:35.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:37:35.82#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:37:35.82#ibcon#first serial, iclass 40, count 0 2006.285.06:37:35.82#ibcon#enter sib2, iclass 40, count 0 2006.285.06:37:35.82#ibcon#flushed, iclass 40, count 0 2006.285.06:37:35.82#ibcon#about to write, iclass 40, count 0 2006.285.06:37:35.82#ibcon#wrote, iclass 40, count 0 2006.285.06:37:35.82#ibcon#about to read 3, iclass 40, count 0 2006.285.06:37:35.84#ibcon#read 3, iclass 40, count 0 2006.285.06:37:35.84#ibcon#about to read 4, iclass 40, count 0 2006.285.06:37:35.84#ibcon#read 4, iclass 40, count 0 2006.285.06:37:35.84#ibcon#about to read 5, iclass 40, count 0 2006.285.06:37:35.84#ibcon#read 5, iclass 40, count 0 2006.285.06:37:35.84#ibcon#about to read 6, iclass 40, count 0 2006.285.06:37:35.84#ibcon#read 6, iclass 40, count 0 2006.285.06:37:35.84#ibcon#end of sib2, iclass 40, count 0 2006.285.06:37:35.84#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:37:35.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:37:35.84#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:37:35.84#ibcon#*before write, iclass 40, count 0 2006.285.06:37:35.84#ibcon#enter sib2, iclass 40, count 0 2006.285.06:37:35.84#ibcon#flushed, iclass 40, count 0 2006.285.06:37:35.84#ibcon#about to write, iclass 40, count 0 2006.285.06:37:35.84#ibcon#wrote, iclass 40, count 0 2006.285.06:37:35.84#ibcon#about to read 3, iclass 40, count 0 2006.285.06:37:35.88#ibcon#read 3, iclass 40, count 0 2006.285.06:37:35.88#ibcon#about to read 4, iclass 40, count 0 2006.285.06:37:35.88#ibcon#read 4, iclass 40, count 0 2006.285.06:37:35.88#ibcon#about to read 5, iclass 40, count 0 2006.285.06:37:35.88#ibcon#read 5, iclass 40, count 0 2006.285.06:37:35.88#ibcon#about to read 6, iclass 40, count 0 2006.285.06:37:35.88#ibcon#read 6, iclass 40, count 0 2006.285.06:37:35.88#ibcon#end of sib2, iclass 40, count 0 2006.285.06:37:35.88#ibcon#*after write, iclass 40, count 0 2006.285.06:37:35.88#ibcon#*before return 0, iclass 40, count 0 2006.285.06:37:35.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:37:35.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:37:35.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:37:35.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:37:35.88$vck44/vb=5,4 2006.285.06:37:35.88#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.06:37:35.88#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.06:37:35.88#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:35.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:37:35.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:37:35.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:37:35.94#ibcon#enter wrdev, iclass 4, count 2 2006.285.06:37:35.94#ibcon#first serial, iclass 4, count 2 2006.285.06:37:35.94#ibcon#enter sib2, iclass 4, count 2 2006.285.06:37:35.94#ibcon#flushed, iclass 4, count 2 2006.285.06:37:35.94#ibcon#about to write, iclass 4, count 2 2006.285.06:37:35.94#ibcon#wrote, iclass 4, count 2 2006.285.06:37:35.94#ibcon#about to read 3, iclass 4, count 2 2006.285.06:37:35.96#ibcon#read 3, iclass 4, count 2 2006.285.06:37:35.96#ibcon#about to read 4, iclass 4, count 2 2006.285.06:37:35.96#ibcon#read 4, iclass 4, count 2 2006.285.06:37:35.96#ibcon#about to read 5, iclass 4, count 2 2006.285.06:37:35.96#ibcon#read 5, iclass 4, count 2 2006.285.06:37:35.96#ibcon#about to read 6, iclass 4, count 2 2006.285.06:37:35.96#ibcon#read 6, iclass 4, count 2 2006.285.06:37:35.96#ibcon#end of sib2, iclass 4, count 2 2006.285.06:37:35.96#ibcon#*mode == 0, iclass 4, count 2 2006.285.06:37:35.96#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.06:37:35.96#ibcon#[27=AT05-04\r\n] 2006.285.06:37:35.96#ibcon#*before write, iclass 4, count 2 2006.285.06:37:35.96#ibcon#enter sib2, iclass 4, count 2 2006.285.06:37:35.96#ibcon#flushed, iclass 4, count 2 2006.285.06:37:35.96#ibcon#about to write, iclass 4, count 2 2006.285.06:37:35.96#ibcon#wrote, iclass 4, count 2 2006.285.06:37:35.96#ibcon#about to read 3, iclass 4, count 2 2006.285.06:37:35.99#ibcon#read 3, iclass 4, count 2 2006.285.06:37:35.99#ibcon#about to read 4, iclass 4, count 2 2006.285.06:37:35.99#ibcon#read 4, iclass 4, count 2 2006.285.06:37:35.99#ibcon#about to read 5, iclass 4, count 2 2006.285.06:37:35.99#ibcon#read 5, iclass 4, count 2 2006.285.06:37:35.99#ibcon#about to read 6, iclass 4, count 2 2006.285.06:37:35.99#ibcon#read 6, iclass 4, count 2 2006.285.06:37:35.99#ibcon#end of sib2, iclass 4, count 2 2006.285.06:37:35.99#ibcon#*after write, iclass 4, count 2 2006.285.06:37:35.99#ibcon#*before return 0, iclass 4, count 2 2006.285.06:37:35.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:37:35.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.06:37:35.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.06:37:35.99#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:35.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:37:36.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:37:36.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:37:36.11#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:37:36.11#ibcon#first serial, iclass 4, count 0 2006.285.06:37:36.11#ibcon#enter sib2, iclass 4, count 0 2006.285.06:37:36.11#ibcon#flushed, iclass 4, count 0 2006.285.06:37:36.11#ibcon#about to write, iclass 4, count 0 2006.285.06:37:36.11#ibcon#wrote, iclass 4, count 0 2006.285.06:37:36.11#ibcon#about to read 3, iclass 4, count 0 2006.285.06:37:36.13#ibcon#read 3, iclass 4, count 0 2006.285.06:37:36.13#ibcon#about to read 4, iclass 4, count 0 2006.285.06:37:36.13#ibcon#read 4, iclass 4, count 0 2006.285.06:37:36.13#ibcon#about to read 5, iclass 4, count 0 2006.285.06:37:36.13#ibcon#read 5, iclass 4, count 0 2006.285.06:37:36.13#ibcon#about to read 6, iclass 4, count 0 2006.285.06:37:36.13#ibcon#read 6, iclass 4, count 0 2006.285.06:37:36.13#ibcon#end of sib2, iclass 4, count 0 2006.285.06:37:36.13#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:37:36.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:37:36.13#ibcon#[27=USB\r\n] 2006.285.06:37:36.13#ibcon#*before write, iclass 4, count 0 2006.285.06:37:36.13#ibcon#enter sib2, iclass 4, count 0 2006.285.06:37:36.13#ibcon#flushed, iclass 4, count 0 2006.285.06:37:36.13#ibcon#about to write, iclass 4, count 0 2006.285.06:37:36.13#ibcon#wrote, iclass 4, count 0 2006.285.06:37:36.13#ibcon#about to read 3, iclass 4, count 0 2006.285.06:37:36.16#ibcon#read 3, iclass 4, count 0 2006.285.06:37:36.16#ibcon#about to read 4, iclass 4, count 0 2006.285.06:37:36.16#ibcon#read 4, iclass 4, count 0 2006.285.06:37:36.16#ibcon#about to read 5, iclass 4, count 0 2006.285.06:37:36.16#ibcon#read 5, iclass 4, count 0 2006.285.06:37:36.16#ibcon#about to read 6, iclass 4, count 0 2006.285.06:37:36.16#ibcon#read 6, iclass 4, count 0 2006.285.06:37:36.16#ibcon#end of sib2, iclass 4, count 0 2006.285.06:37:36.16#ibcon#*after write, iclass 4, count 0 2006.285.06:37:36.16#ibcon#*before return 0, iclass 4, count 0 2006.285.06:37:36.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:37:36.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.06:37:36.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:37:36.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:37:36.16$vck44/vblo=6,719.99 2006.285.06:37:36.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.06:37:36.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.06:37:36.16#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:36.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:37:36.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:37:36.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:37:36.16#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:37:36.16#ibcon#first serial, iclass 6, count 0 2006.285.06:37:36.16#ibcon#enter sib2, iclass 6, count 0 2006.285.06:37:36.16#ibcon#flushed, iclass 6, count 0 2006.285.06:37:36.16#ibcon#about to write, iclass 6, count 0 2006.285.06:37:36.16#ibcon#wrote, iclass 6, count 0 2006.285.06:37:36.16#ibcon#about to read 3, iclass 6, count 0 2006.285.06:37:36.18#ibcon#read 3, iclass 6, count 0 2006.285.06:37:36.18#ibcon#about to read 4, iclass 6, count 0 2006.285.06:37:36.18#ibcon#read 4, iclass 6, count 0 2006.285.06:37:36.18#ibcon#about to read 5, iclass 6, count 0 2006.285.06:37:36.18#ibcon#read 5, iclass 6, count 0 2006.285.06:37:36.18#ibcon#about to read 6, iclass 6, count 0 2006.285.06:37:36.18#ibcon#read 6, iclass 6, count 0 2006.285.06:37:36.18#ibcon#end of sib2, iclass 6, count 0 2006.285.06:37:36.18#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:37:36.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:37:36.18#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:37:36.18#ibcon#*before write, iclass 6, count 0 2006.285.06:37:36.18#ibcon#enter sib2, iclass 6, count 0 2006.285.06:37:36.18#ibcon#flushed, iclass 6, count 0 2006.285.06:37:36.18#ibcon#about to write, iclass 6, count 0 2006.285.06:37:36.18#ibcon#wrote, iclass 6, count 0 2006.285.06:37:36.18#ibcon#about to read 3, iclass 6, count 0 2006.285.06:37:36.22#ibcon#read 3, iclass 6, count 0 2006.285.06:37:36.22#ibcon#about to read 4, iclass 6, count 0 2006.285.06:37:36.22#ibcon#read 4, iclass 6, count 0 2006.285.06:37:36.22#ibcon#about to read 5, iclass 6, count 0 2006.285.06:37:36.22#ibcon#read 5, iclass 6, count 0 2006.285.06:37:36.22#ibcon#about to read 6, iclass 6, count 0 2006.285.06:37:36.22#ibcon#read 6, iclass 6, count 0 2006.285.06:37:36.22#ibcon#end of sib2, iclass 6, count 0 2006.285.06:37:36.22#ibcon#*after write, iclass 6, count 0 2006.285.06:37:36.22#ibcon#*before return 0, iclass 6, count 0 2006.285.06:37:36.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:37:36.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.06:37:36.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:37:36.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:37:36.22$vck44/vb=6,3 2006.285.06:37:36.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.06:37:36.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.06:37:36.22#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:36.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:37:36.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:37:36.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:37:36.28#ibcon#enter wrdev, iclass 10, count 2 2006.285.06:37:36.28#ibcon#first serial, iclass 10, count 2 2006.285.06:37:36.28#ibcon#enter sib2, iclass 10, count 2 2006.285.06:37:36.28#ibcon#flushed, iclass 10, count 2 2006.285.06:37:36.28#ibcon#about to write, iclass 10, count 2 2006.285.06:37:36.28#ibcon#wrote, iclass 10, count 2 2006.285.06:37:36.28#ibcon#about to read 3, iclass 10, count 2 2006.285.06:37:36.30#ibcon#read 3, iclass 10, count 2 2006.285.06:37:36.30#ibcon#about to read 4, iclass 10, count 2 2006.285.06:37:36.30#ibcon#read 4, iclass 10, count 2 2006.285.06:37:36.30#ibcon#about to read 5, iclass 10, count 2 2006.285.06:37:36.30#ibcon#read 5, iclass 10, count 2 2006.285.06:37:36.30#ibcon#about to read 6, iclass 10, count 2 2006.285.06:37:36.30#ibcon#read 6, iclass 10, count 2 2006.285.06:37:36.30#ibcon#end of sib2, iclass 10, count 2 2006.285.06:37:36.30#ibcon#*mode == 0, iclass 10, count 2 2006.285.06:37:36.30#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.06:37:36.30#ibcon#[27=AT06-03\r\n] 2006.285.06:37:36.30#ibcon#*before write, iclass 10, count 2 2006.285.06:37:36.30#ibcon#enter sib2, iclass 10, count 2 2006.285.06:37:36.30#ibcon#flushed, iclass 10, count 2 2006.285.06:37:36.30#ibcon#about to write, iclass 10, count 2 2006.285.06:37:36.30#ibcon#wrote, iclass 10, count 2 2006.285.06:37:36.30#ibcon#about to read 3, iclass 10, count 2 2006.285.06:37:36.33#ibcon#read 3, iclass 10, count 2 2006.285.06:37:36.33#ibcon#about to read 4, iclass 10, count 2 2006.285.06:37:36.33#ibcon#read 4, iclass 10, count 2 2006.285.06:37:36.33#ibcon#about to read 5, iclass 10, count 2 2006.285.06:37:36.33#ibcon#read 5, iclass 10, count 2 2006.285.06:37:36.33#ibcon#about to read 6, iclass 10, count 2 2006.285.06:37:36.33#ibcon#read 6, iclass 10, count 2 2006.285.06:37:36.33#ibcon#end of sib2, iclass 10, count 2 2006.285.06:37:36.33#ibcon#*after write, iclass 10, count 2 2006.285.06:37:36.33#ibcon#*before return 0, iclass 10, count 2 2006.285.06:37:36.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:37:36.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.06:37:36.33#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.06:37:36.33#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:36.33#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:37:36.45#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:37:36.45#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:37:36.45#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:37:36.45#ibcon#first serial, iclass 10, count 0 2006.285.06:37:36.45#ibcon#enter sib2, iclass 10, count 0 2006.285.06:37:36.45#ibcon#flushed, iclass 10, count 0 2006.285.06:37:36.45#ibcon#about to write, iclass 10, count 0 2006.285.06:37:36.45#ibcon#wrote, iclass 10, count 0 2006.285.06:37:36.45#ibcon#about to read 3, iclass 10, count 0 2006.285.06:37:36.47#ibcon#read 3, iclass 10, count 0 2006.285.06:37:36.47#ibcon#about to read 4, iclass 10, count 0 2006.285.06:37:36.47#ibcon#read 4, iclass 10, count 0 2006.285.06:37:36.47#ibcon#about to read 5, iclass 10, count 0 2006.285.06:37:36.47#ibcon#read 5, iclass 10, count 0 2006.285.06:37:36.47#ibcon#about to read 6, iclass 10, count 0 2006.285.06:37:36.47#ibcon#read 6, iclass 10, count 0 2006.285.06:37:36.47#ibcon#end of sib2, iclass 10, count 0 2006.285.06:37:36.47#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:37:36.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:37:36.47#ibcon#[27=USB\r\n] 2006.285.06:37:36.47#ibcon#*before write, iclass 10, count 0 2006.285.06:37:36.47#ibcon#enter sib2, iclass 10, count 0 2006.285.06:37:36.47#ibcon#flushed, iclass 10, count 0 2006.285.06:37:36.47#ibcon#about to write, iclass 10, count 0 2006.285.06:37:36.47#ibcon#wrote, iclass 10, count 0 2006.285.06:37:36.47#ibcon#about to read 3, iclass 10, count 0 2006.285.06:37:36.50#ibcon#read 3, iclass 10, count 0 2006.285.06:37:36.50#ibcon#about to read 4, iclass 10, count 0 2006.285.06:37:36.50#ibcon#read 4, iclass 10, count 0 2006.285.06:37:36.50#ibcon#about to read 5, iclass 10, count 0 2006.285.06:37:36.50#ibcon#read 5, iclass 10, count 0 2006.285.06:37:36.50#ibcon#about to read 6, iclass 10, count 0 2006.285.06:37:36.50#ibcon#read 6, iclass 10, count 0 2006.285.06:37:36.50#ibcon#end of sib2, iclass 10, count 0 2006.285.06:37:36.50#ibcon#*after write, iclass 10, count 0 2006.285.06:37:36.50#ibcon#*before return 0, iclass 10, count 0 2006.285.06:37:36.50#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:37:36.50#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.06:37:36.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:37:36.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:37:36.50$vck44/vblo=7,734.99 2006.285.06:37:36.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.06:37:36.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.06:37:36.50#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:36.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:37:36.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:37:36.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:37:36.50#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:37:36.50#ibcon#first serial, iclass 12, count 0 2006.285.06:37:36.50#ibcon#enter sib2, iclass 12, count 0 2006.285.06:37:36.50#ibcon#flushed, iclass 12, count 0 2006.285.06:37:36.50#ibcon#about to write, iclass 12, count 0 2006.285.06:37:36.50#ibcon#wrote, iclass 12, count 0 2006.285.06:37:36.50#ibcon#about to read 3, iclass 12, count 0 2006.285.06:37:36.52#ibcon#read 3, iclass 12, count 0 2006.285.06:37:36.52#ibcon#about to read 4, iclass 12, count 0 2006.285.06:37:36.52#ibcon#read 4, iclass 12, count 0 2006.285.06:37:36.52#ibcon#about to read 5, iclass 12, count 0 2006.285.06:37:36.52#ibcon#read 5, iclass 12, count 0 2006.285.06:37:36.52#ibcon#about to read 6, iclass 12, count 0 2006.285.06:37:36.52#ibcon#read 6, iclass 12, count 0 2006.285.06:37:36.52#ibcon#end of sib2, iclass 12, count 0 2006.285.06:37:36.52#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:37:36.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:37:36.52#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:37:36.52#ibcon#*before write, iclass 12, count 0 2006.285.06:37:36.52#ibcon#enter sib2, iclass 12, count 0 2006.285.06:37:36.52#ibcon#flushed, iclass 12, count 0 2006.285.06:37:36.52#ibcon#about to write, iclass 12, count 0 2006.285.06:37:36.52#ibcon#wrote, iclass 12, count 0 2006.285.06:37:36.52#ibcon#about to read 3, iclass 12, count 0 2006.285.06:37:36.56#ibcon#read 3, iclass 12, count 0 2006.285.06:37:36.56#ibcon#about to read 4, iclass 12, count 0 2006.285.06:37:36.56#ibcon#read 4, iclass 12, count 0 2006.285.06:37:36.56#ibcon#about to read 5, iclass 12, count 0 2006.285.06:37:36.56#ibcon#read 5, iclass 12, count 0 2006.285.06:37:36.56#ibcon#about to read 6, iclass 12, count 0 2006.285.06:37:36.56#ibcon#read 6, iclass 12, count 0 2006.285.06:37:36.56#ibcon#end of sib2, iclass 12, count 0 2006.285.06:37:36.56#ibcon#*after write, iclass 12, count 0 2006.285.06:37:36.56#ibcon#*before return 0, iclass 12, count 0 2006.285.06:37:36.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:37:36.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.06:37:36.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:37:36.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:37:36.56$vck44/vb=7,4 2006.285.06:37:36.56#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.06:37:36.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.06:37:36.56#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:36.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:37:36.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:37:36.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:37:36.62#ibcon#enter wrdev, iclass 14, count 2 2006.285.06:37:36.62#ibcon#first serial, iclass 14, count 2 2006.285.06:37:36.62#ibcon#enter sib2, iclass 14, count 2 2006.285.06:37:36.62#ibcon#flushed, iclass 14, count 2 2006.285.06:37:36.62#ibcon#about to write, iclass 14, count 2 2006.285.06:37:36.62#ibcon#wrote, iclass 14, count 2 2006.285.06:37:36.62#ibcon#about to read 3, iclass 14, count 2 2006.285.06:37:36.64#ibcon#read 3, iclass 14, count 2 2006.285.06:37:36.64#ibcon#about to read 4, iclass 14, count 2 2006.285.06:37:36.64#ibcon#read 4, iclass 14, count 2 2006.285.06:37:36.64#ibcon#about to read 5, iclass 14, count 2 2006.285.06:37:36.64#ibcon#read 5, iclass 14, count 2 2006.285.06:37:36.64#ibcon#about to read 6, iclass 14, count 2 2006.285.06:37:36.64#ibcon#read 6, iclass 14, count 2 2006.285.06:37:36.64#ibcon#end of sib2, iclass 14, count 2 2006.285.06:37:36.64#ibcon#*mode == 0, iclass 14, count 2 2006.285.06:37:36.64#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.06:37:36.64#ibcon#[27=AT07-04\r\n] 2006.285.06:37:36.64#ibcon#*before write, iclass 14, count 2 2006.285.06:37:36.64#ibcon#enter sib2, iclass 14, count 2 2006.285.06:37:36.64#ibcon#flushed, iclass 14, count 2 2006.285.06:37:36.64#ibcon#about to write, iclass 14, count 2 2006.285.06:37:36.64#ibcon#wrote, iclass 14, count 2 2006.285.06:37:36.64#ibcon#about to read 3, iclass 14, count 2 2006.285.06:37:36.67#ibcon#read 3, iclass 14, count 2 2006.285.06:37:36.67#ibcon#about to read 4, iclass 14, count 2 2006.285.06:37:36.67#ibcon#read 4, iclass 14, count 2 2006.285.06:37:36.67#ibcon#about to read 5, iclass 14, count 2 2006.285.06:37:36.67#ibcon#read 5, iclass 14, count 2 2006.285.06:37:36.67#ibcon#about to read 6, iclass 14, count 2 2006.285.06:37:36.67#ibcon#read 6, iclass 14, count 2 2006.285.06:37:36.67#ibcon#end of sib2, iclass 14, count 2 2006.285.06:37:36.67#ibcon#*after write, iclass 14, count 2 2006.285.06:37:36.67#ibcon#*before return 0, iclass 14, count 2 2006.285.06:37:36.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:37:36.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.06:37:36.67#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.06:37:36.67#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:36.67#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:37:36.79#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:37:36.79#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:37:36.79#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:37:36.79#ibcon#first serial, iclass 14, count 0 2006.285.06:37:36.79#ibcon#enter sib2, iclass 14, count 0 2006.285.06:37:36.79#ibcon#flushed, iclass 14, count 0 2006.285.06:37:36.79#ibcon#about to write, iclass 14, count 0 2006.285.06:37:36.79#ibcon#wrote, iclass 14, count 0 2006.285.06:37:36.79#ibcon#about to read 3, iclass 14, count 0 2006.285.06:37:36.81#ibcon#read 3, iclass 14, count 0 2006.285.06:37:36.81#ibcon#about to read 4, iclass 14, count 0 2006.285.06:37:36.81#ibcon#read 4, iclass 14, count 0 2006.285.06:37:36.81#ibcon#about to read 5, iclass 14, count 0 2006.285.06:37:36.81#ibcon#read 5, iclass 14, count 0 2006.285.06:37:36.81#ibcon#about to read 6, iclass 14, count 0 2006.285.06:37:36.81#ibcon#read 6, iclass 14, count 0 2006.285.06:37:36.81#ibcon#end of sib2, iclass 14, count 0 2006.285.06:37:36.81#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:37:36.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:37:36.81#ibcon#[27=USB\r\n] 2006.285.06:37:36.81#ibcon#*before write, iclass 14, count 0 2006.285.06:37:36.81#ibcon#enter sib2, iclass 14, count 0 2006.285.06:37:36.81#ibcon#flushed, iclass 14, count 0 2006.285.06:37:36.81#ibcon#about to write, iclass 14, count 0 2006.285.06:37:36.81#ibcon#wrote, iclass 14, count 0 2006.285.06:37:36.81#ibcon#about to read 3, iclass 14, count 0 2006.285.06:37:36.84#ibcon#read 3, iclass 14, count 0 2006.285.06:37:36.84#ibcon#about to read 4, iclass 14, count 0 2006.285.06:37:36.84#ibcon#read 4, iclass 14, count 0 2006.285.06:37:36.84#ibcon#about to read 5, iclass 14, count 0 2006.285.06:37:36.84#ibcon#read 5, iclass 14, count 0 2006.285.06:37:36.84#ibcon#about to read 6, iclass 14, count 0 2006.285.06:37:36.84#ibcon#read 6, iclass 14, count 0 2006.285.06:37:36.84#ibcon#end of sib2, iclass 14, count 0 2006.285.06:37:36.84#ibcon#*after write, iclass 14, count 0 2006.285.06:37:36.84#ibcon#*before return 0, iclass 14, count 0 2006.285.06:37:36.84#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:37:36.84#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.06:37:36.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:37:36.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:37:36.84$vck44/vblo=8,744.99 2006.285.06:37:36.84#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.06:37:36.84#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.06:37:36.84#ibcon#ireg 17 cls_cnt 0 2006.285.06:37:36.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:37:36.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:37:36.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:37:36.84#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:37:36.84#ibcon#first serial, iclass 16, count 0 2006.285.06:37:36.84#ibcon#enter sib2, iclass 16, count 0 2006.285.06:37:36.84#ibcon#flushed, iclass 16, count 0 2006.285.06:37:36.84#ibcon#about to write, iclass 16, count 0 2006.285.06:37:36.84#ibcon#wrote, iclass 16, count 0 2006.285.06:37:36.84#ibcon#about to read 3, iclass 16, count 0 2006.285.06:37:36.86#ibcon#read 3, iclass 16, count 0 2006.285.06:37:36.86#ibcon#about to read 4, iclass 16, count 0 2006.285.06:37:36.86#ibcon#read 4, iclass 16, count 0 2006.285.06:37:36.86#ibcon#about to read 5, iclass 16, count 0 2006.285.06:37:36.86#ibcon#read 5, iclass 16, count 0 2006.285.06:37:36.86#ibcon#about to read 6, iclass 16, count 0 2006.285.06:37:36.86#ibcon#read 6, iclass 16, count 0 2006.285.06:37:36.86#ibcon#end of sib2, iclass 16, count 0 2006.285.06:37:36.86#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:37:36.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:37:36.86#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:37:36.86#ibcon#*before write, iclass 16, count 0 2006.285.06:37:36.86#ibcon#enter sib2, iclass 16, count 0 2006.285.06:37:36.86#ibcon#flushed, iclass 16, count 0 2006.285.06:37:36.86#ibcon#about to write, iclass 16, count 0 2006.285.06:37:36.86#ibcon#wrote, iclass 16, count 0 2006.285.06:37:36.86#ibcon#about to read 3, iclass 16, count 0 2006.285.06:37:36.90#ibcon#read 3, iclass 16, count 0 2006.285.06:37:36.90#ibcon#about to read 4, iclass 16, count 0 2006.285.06:37:36.90#ibcon#read 4, iclass 16, count 0 2006.285.06:37:36.90#ibcon#about to read 5, iclass 16, count 0 2006.285.06:37:36.90#ibcon#read 5, iclass 16, count 0 2006.285.06:37:36.90#ibcon#about to read 6, iclass 16, count 0 2006.285.06:37:36.90#ibcon#read 6, iclass 16, count 0 2006.285.06:37:36.90#ibcon#end of sib2, iclass 16, count 0 2006.285.06:37:36.90#ibcon#*after write, iclass 16, count 0 2006.285.06:37:36.90#ibcon#*before return 0, iclass 16, count 0 2006.285.06:37:36.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:37:36.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.06:37:36.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:37:36.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:37:36.90$vck44/vb=8,4 2006.285.06:37:36.90#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.06:37:36.90#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.06:37:36.90#ibcon#ireg 11 cls_cnt 2 2006.285.06:37:36.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:37:36.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:37:36.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:37:36.96#ibcon#enter wrdev, iclass 18, count 2 2006.285.06:37:36.96#ibcon#first serial, iclass 18, count 2 2006.285.06:37:36.96#ibcon#enter sib2, iclass 18, count 2 2006.285.06:37:36.96#ibcon#flushed, iclass 18, count 2 2006.285.06:37:36.96#ibcon#about to write, iclass 18, count 2 2006.285.06:37:36.96#ibcon#wrote, iclass 18, count 2 2006.285.06:37:36.96#ibcon#about to read 3, iclass 18, count 2 2006.285.06:37:36.98#ibcon#read 3, iclass 18, count 2 2006.285.06:37:36.98#ibcon#about to read 4, iclass 18, count 2 2006.285.06:37:36.98#ibcon#read 4, iclass 18, count 2 2006.285.06:37:36.98#ibcon#about to read 5, iclass 18, count 2 2006.285.06:37:36.98#ibcon#read 5, iclass 18, count 2 2006.285.06:37:36.98#ibcon#about to read 6, iclass 18, count 2 2006.285.06:37:36.98#ibcon#read 6, iclass 18, count 2 2006.285.06:37:36.98#ibcon#end of sib2, iclass 18, count 2 2006.285.06:37:36.98#ibcon#*mode == 0, iclass 18, count 2 2006.285.06:37:36.98#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.06:37:36.98#ibcon#[27=AT08-04\r\n] 2006.285.06:37:36.98#ibcon#*before write, iclass 18, count 2 2006.285.06:37:36.98#ibcon#enter sib2, iclass 18, count 2 2006.285.06:37:36.98#ibcon#flushed, iclass 18, count 2 2006.285.06:37:36.98#ibcon#about to write, iclass 18, count 2 2006.285.06:37:36.98#ibcon#wrote, iclass 18, count 2 2006.285.06:37:36.98#ibcon#about to read 3, iclass 18, count 2 2006.285.06:37:37.01#ibcon#read 3, iclass 18, count 2 2006.285.06:37:37.01#ibcon#about to read 4, iclass 18, count 2 2006.285.06:37:37.01#ibcon#read 4, iclass 18, count 2 2006.285.06:37:37.01#ibcon#about to read 5, iclass 18, count 2 2006.285.06:37:37.01#ibcon#read 5, iclass 18, count 2 2006.285.06:37:37.01#ibcon#about to read 6, iclass 18, count 2 2006.285.06:37:37.01#ibcon#read 6, iclass 18, count 2 2006.285.06:37:37.01#ibcon#end of sib2, iclass 18, count 2 2006.285.06:37:37.01#ibcon#*after write, iclass 18, count 2 2006.285.06:37:37.01#ibcon#*before return 0, iclass 18, count 2 2006.285.06:37:37.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:37:37.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.06:37:37.01#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.06:37:37.01#ibcon#ireg 7 cls_cnt 0 2006.285.06:37:37.01#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:37:37.13#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:37:37.13#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:37:37.13#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:37:37.13#ibcon#first serial, iclass 18, count 0 2006.285.06:37:37.13#ibcon#enter sib2, iclass 18, count 0 2006.285.06:37:37.13#ibcon#flushed, iclass 18, count 0 2006.285.06:37:37.13#ibcon#about to write, iclass 18, count 0 2006.285.06:37:37.13#ibcon#wrote, iclass 18, count 0 2006.285.06:37:37.13#ibcon#about to read 3, iclass 18, count 0 2006.285.06:37:37.15#ibcon#read 3, iclass 18, count 0 2006.285.06:37:37.15#ibcon#about to read 4, iclass 18, count 0 2006.285.06:37:37.15#ibcon#read 4, iclass 18, count 0 2006.285.06:37:37.15#ibcon#about to read 5, iclass 18, count 0 2006.285.06:37:37.15#ibcon#read 5, iclass 18, count 0 2006.285.06:37:37.15#ibcon#about to read 6, iclass 18, count 0 2006.285.06:37:37.15#ibcon#read 6, iclass 18, count 0 2006.285.06:37:37.15#ibcon#end of sib2, iclass 18, count 0 2006.285.06:37:37.15#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:37:37.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:37:37.15#ibcon#[27=USB\r\n] 2006.285.06:37:37.15#ibcon#*before write, iclass 18, count 0 2006.285.06:37:37.15#ibcon#enter sib2, iclass 18, count 0 2006.285.06:37:37.15#ibcon#flushed, iclass 18, count 0 2006.285.06:37:37.15#ibcon#about to write, iclass 18, count 0 2006.285.06:37:37.15#ibcon#wrote, iclass 18, count 0 2006.285.06:37:37.15#ibcon#about to read 3, iclass 18, count 0 2006.285.06:37:37.18#ibcon#read 3, iclass 18, count 0 2006.285.06:37:37.18#ibcon#about to read 4, iclass 18, count 0 2006.285.06:37:37.18#ibcon#read 4, iclass 18, count 0 2006.285.06:37:37.18#ibcon#about to read 5, iclass 18, count 0 2006.285.06:37:37.18#ibcon#read 5, iclass 18, count 0 2006.285.06:37:37.18#ibcon#about to read 6, iclass 18, count 0 2006.285.06:37:37.18#ibcon#read 6, iclass 18, count 0 2006.285.06:37:37.18#ibcon#end of sib2, iclass 18, count 0 2006.285.06:37:37.18#ibcon#*after write, iclass 18, count 0 2006.285.06:37:37.18#ibcon#*before return 0, iclass 18, count 0 2006.285.06:37:37.18#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:37:37.18#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.06:37:37.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:37:37.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:37:37.18$vck44/vabw=wide 2006.285.06:37:37.18#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.06:37:37.18#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.06:37:37.18#ibcon#ireg 8 cls_cnt 0 2006.285.06:37:37.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:37:37.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:37:37.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:37:37.18#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:37:37.18#ibcon#first serial, iclass 20, count 0 2006.285.06:37:37.18#ibcon#enter sib2, iclass 20, count 0 2006.285.06:37:37.18#ibcon#flushed, iclass 20, count 0 2006.285.06:37:37.18#ibcon#about to write, iclass 20, count 0 2006.285.06:37:37.18#ibcon#wrote, iclass 20, count 0 2006.285.06:37:37.18#ibcon#about to read 3, iclass 20, count 0 2006.285.06:37:37.20#ibcon#read 3, iclass 20, count 0 2006.285.06:37:37.20#ibcon#about to read 4, iclass 20, count 0 2006.285.06:37:37.20#ibcon#read 4, iclass 20, count 0 2006.285.06:37:37.20#ibcon#about to read 5, iclass 20, count 0 2006.285.06:37:37.20#ibcon#read 5, iclass 20, count 0 2006.285.06:37:37.20#ibcon#about to read 6, iclass 20, count 0 2006.285.06:37:37.20#ibcon#read 6, iclass 20, count 0 2006.285.06:37:37.20#ibcon#end of sib2, iclass 20, count 0 2006.285.06:37:37.20#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:37:37.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:37:37.20#ibcon#[25=BW32\r\n] 2006.285.06:37:37.20#ibcon#*before write, iclass 20, count 0 2006.285.06:37:37.20#ibcon#enter sib2, iclass 20, count 0 2006.285.06:37:37.20#ibcon#flushed, iclass 20, count 0 2006.285.06:37:37.20#ibcon#about to write, iclass 20, count 0 2006.285.06:37:37.20#ibcon#wrote, iclass 20, count 0 2006.285.06:37:37.20#ibcon#about to read 3, iclass 20, count 0 2006.285.06:37:37.23#ibcon#read 3, iclass 20, count 0 2006.285.06:37:37.23#ibcon#about to read 4, iclass 20, count 0 2006.285.06:37:37.23#ibcon#read 4, iclass 20, count 0 2006.285.06:37:37.23#ibcon#about to read 5, iclass 20, count 0 2006.285.06:37:37.23#ibcon#read 5, iclass 20, count 0 2006.285.06:37:37.23#ibcon#about to read 6, iclass 20, count 0 2006.285.06:37:37.23#ibcon#read 6, iclass 20, count 0 2006.285.06:37:37.23#ibcon#end of sib2, iclass 20, count 0 2006.285.06:37:37.23#ibcon#*after write, iclass 20, count 0 2006.285.06:37:37.23#ibcon#*before return 0, iclass 20, count 0 2006.285.06:37:37.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:37:37.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.06:37:37.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:37:37.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:37:37.23$vck44/vbbw=wide 2006.285.06:37:37.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.06:37:37.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.06:37:37.23#ibcon#ireg 8 cls_cnt 0 2006.285.06:37:37.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:37:37.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:37:37.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:37:37.30#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:37:37.30#ibcon#first serial, iclass 22, count 0 2006.285.06:37:37.30#ibcon#enter sib2, iclass 22, count 0 2006.285.06:37:37.30#ibcon#flushed, iclass 22, count 0 2006.285.06:37:37.30#ibcon#about to write, iclass 22, count 0 2006.285.06:37:37.30#ibcon#wrote, iclass 22, count 0 2006.285.06:37:37.30#ibcon#about to read 3, iclass 22, count 0 2006.285.06:37:37.32#ibcon#read 3, iclass 22, count 0 2006.285.06:37:37.32#ibcon#about to read 4, iclass 22, count 0 2006.285.06:37:37.32#ibcon#read 4, iclass 22, count 0 2006.285.06:37:37.32#ibcon#about to read 5, iclass 22, count 0 2006.285.06:37:37.32#ibcon#read 5, iclass 22, count 0 2006.285.06:37:37.32#ibcon#about to read 6, iclass 22, count 0 2006.285.06:37:37.32#ibcon#read 6, iclass 22, count 0 2006.285.06:37:37.32#ibcon#end of sib2, iclass 22, count 0 2006.285.06:37:37.32#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:37:37.32#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:37:37.32#ibcon#[27=BW32\r\n] 2006.285.06:37:37.32#ibcon#*before write, iclass 22, count 0 2006.285.06:37:37.32#ibcon#enter sib2, iclass 22, count 0 2006.285.06:37:37.32#ibcon#flushed, iclass 22, count 0 2006.285.06:37:37.32#ibcon#about to write, iclass 22, count 0 2006.285.06:37:37.32#ibcon#wrote, iclass 22, count 0 2006.285.06:37:37.32#ibcon#about to read 3, iclass 22, count 0 2006.285.06:37:37.35#ibcon#read 3, iclass 22, count 0 2006.285.06:37:37.35#ibcon#about to read 4, iclass 22, count 0 2006.285.06:37:37.35#ibcon#read 4, iclass 22, count 0 2006.285.06:37:37.35#ibcon#about to read 5, iclass 22, count 0 2006.285.06:37:37.35#ibcon#read 5, iclass 22, count 0 2006.285.06:37:37.35#ibcon#about to read 6, iclass 22, count 0 2006.285.06:37:37.35#ibcon#read 6, iclass 22, count 0 2006.285.06:37:37.35#ibcon#end of sib2, iclass 22, count 0 2006.285.06:37:37.35#ibcon#*after write, iclass 22, count 0 2006.285.06:37:37.35#ibcon#*before return 0, iclass 22, count 0 2006.285.06:37:37.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:37:37.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:37:37.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:37:37.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:37:37.35$setupk4/ifdk4 2006.285.06:37:37.35$ifdk4/lo= 2006.285.06:37:37.35$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:37:37.35$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:37:37.35$ifdk4/patch= 2006.285.06:37:37.35$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:37:37.35$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:37:37.35$setupk4/!*+20s 2006.285.06:37:43.32#abcon#<5=/05 4.9 7.6 24.82 691014.1\r\n> 2006.285.06:37:43.34#abcon#{5=INTERFACE CLEAR} 2006.285.06:37:43.40#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:37:51.86$setupk4/"tpicd 2006.285.06:37:51.86$setupk4/echo=off 2006.285.06:37:51.86$setupk4/xlog=off 2006.285.06:37:51.86:!2006.285.06:39:07 2006.285.06:38:03.14#trakl#Source acquired 2006.285.06:38:05.14#flagr#flagr/antenna,acquired 2006.285.06:39:07.00:preob 2006.285.06:39:07.14/onsource/TRACKING 2006.285.06:39:07.14:!2006.285.06:39:17 2006.285.06:39:17.00:"tape 2006.285.06:39:17.00:"st=record 2006.285.06:39:17.00:data_valid=on 2006.285.06:39:17.00:midob 2006.285.06:39:17.13/onsource/TRACKING 2006.285.06:39:17.13/wx/24.80,1014.2,69 2006.285.06:39:17.18/cable/+6.4718E-03 2006.285.06:39:18.27/va/01,07,usb,yes,35,38 2006.285.06:39:18.27/va/02,06,usb,yes,35,35 2006.285.06:39:18.27/va/03,07,usb,yes,34,36 2006.285.06:39:18.27/va/04,06,usb,yes,36,38 2006.285.06:39:18.27/va/05,03,usb,yes,35,35 2006.285.06:39:18.27/va/06,04,usb,yes,31,30 2006.285.06:39:18.27/va/07,04,usb,yes,32,33 2006.285.06:39:18.27/va/08,03,usb,yes,33,40 2006.285.06:39:18.50/valo/01,524.99,yes,locked 2006.285.06:39:18.50/valo/02,534.99,yes,locked 2006.285.06:39:18.50/valo/03,564.99,yes,locked 2006.285.06:39:18.50/valo/04,624.99,yes,locked 2006.285.06:39:18.50/valo/05,734.99,yes,locked 2006.285.06:39:18.50/valo/06,814.99,yes,locked 2006.285.06:39:18.50/valo/07,864.99,yes,locked 2006.285.06:39:18.50/valo/08,884.99,yes,locked 2006.285.06:39:19.59/vb/01,04,usb,yes,32,31 2006.285.06:39:19.59/vb/02,05,usb,yes,31,31 2006.285.06:39:19.59/vb/03,04,usb,yes,32,35 2006.285.06:39:19.59/vb/04,05,usb,yes,32,31 2006.285.06:39:19.59/vb/05,04,usb,yes,29,31 2006.285.06:39:19.59/vb/06,03,usb,yes,41,37 2006.285.06:39:19.59/vb/07,04,usb,yes,33,33 2006.285.06:39:19.59/vb/08,04,usb,yes,30,34 2006.285.06:39:19.82/vblo/01,629.99,yes,locked 2006.285.06:39:19.82/vblo/02,634.99,yes,locked 2006.285.06:39:19.82/vblo/03,649.99,yes,locked 2006.285.06:39:19.82/vblo/04,679.99,yes,locked 2006.285.06:39:19.82/vblo/05,709.99,yes,locked 2006.285.06:39:19.82/vblo/06,719.99,yes,locked 2006.285.06:39:19.82/vblo/07,734.99,yes,locked 2006.285.06:39:19.82/vblo/08,744.99,yes,locked 2006.285.06:39:19.97/vabw/8 2006.285.06:39:20.12/vbbw/8 2006.285.06:39:20.21/xfe/off,on,12.2 2006.285.06:39:20.59/ifatt/23,28,28,28 2006.285.06:39:21.07/fmout-gps/S +2.57E-07 2006.285.06:39:21.09:!2006.285.06:39:57 2006.285.06:39:57.00:data_valid=off 2006.285.06:39:57.00:"et 2006.285.06:39:57.00:!+3s 2006.285.06:40:00.01:"tape 2006.285.06:40:00.01:postob 2006.285.06:40:00.18/cable/+6.4720E-03 2006.285.06:40:00.18/wx/24.79,1014.2,70 2006.285.06:40:01.07/fmout-gps/S +2.58E-07 2006.285.06:40:01.07:scan_name=285-0641,jd0610,170 2006.285.06:40:01.07:source=2201+315,220314.98,314538.3,2000.0,cw 2006.285.06:40:02.13#flagr#flagr/antenna,new-source 2006.285.06:40:02.13:checkk5 2006.285.06:40:02.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:40:03.17/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:40:03.56/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:40:03.93/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:40:04.31/chk_obsdata//k5ts1/T2850639??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:40:04.66/chk_obsdata//k5ts2/T2850639??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:40:05.05/chk_obsdata//k5ts3/T2850639??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:40:05.45/chk_obsdata//k5ts4/T2850639??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.06:40:06.23/k5log//k5ts1_log_newline 2006.285.06:40:07.03/k5log//k5ts2_log_newline 2006.285.06:40:07.75/k5log//k5ts3_log_newline 2006.285.06:40:08.68/k5log//k5ts4_log_newline 2006.285.06:40:08.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:40:08.70:setupk4=1 2006.285.06:40:08.70$setupk4/echo=on 2006.285.06:40:08.70$setupk4/pcalon 2006.285.06:40:08.70$pcalon/"no phase cal control is implemented here 2006.285.06:40:08.70$setupk4/"tpicd=stop 2006.285.06:40:08.70$setupk4/"rec=synch_on 2006.285.06:40:08.70$setupk4/"rec_mode=128 2006.285.06:40:08.70$setupk4/!* 2006.285.06:40:08.70$setupk4/recpk4 2006.285.06:40:08.70$recpk4/recpatch= 2006.285.06:40:08.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:40:08.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:40:08.70$setupk4/vck44 2006.285.06:40:08.70$vck44/valo=1,524.99 2006.285.06:40:08.70#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.06:40:08.70#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.06:40:08.70#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:08.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:40:08.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:40:08.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:40:08.70#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:40:08.70#ibcon#first serial, iclass 15, count 0 2006.285.06:40:08.70#ibcon#enter sib2, iclass 15, count 0 2006.285.06:40:08.70#ibcon#flushed, iclass 15, count 0 2006.285.06:40:08.70#ibcon#about to write, iclass 15, count 0 2006.285.06:40:08.70#ibcon#wrote, iclass 15, count 0 2006.285.06:40:08.70#ibcon#about to read 3, iclass 15, count 0 2006.285.06:40:08.72#ibcon#read 3, iclass 15, count 0 2006.285.06:40:08.72#ibcon#about to read 4, iclass 15, count 0 2006.285.06:40:08.72#ibcon#read 4, iclass 15, count 0 2006.285.06:40:08.72#ibcon#about to read 5, iclass 15, count 0 2006.285.06:40:08.72#ibcon#read 5, iclass 15, count 0 2006.285.06:40:08.72#ibcon#about to read 6, iclass 15, count 0 2006.285.06:40:08.72#ibcon#read 6, iclass 15, count 0 2006.285.06:40:08.72#ibcon#end of sib2, iclass 15, count 0 2006.285.06:40:08.72#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:40:08.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:40:08.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:40:08.72#ibcon#*before write, iclass 15, count 0 2006.285.06:40:08.72#ibcon#enter sib2, iclass 15, count 0 2006.285.06:40:08.72#ibcon#flushed, iclass 15, count 0 2006.285.06:40:08.72#ibcon#about to write, iclass 15, count 0 2006.285.06:40:08.72#ibcon#wrote, iclass 15, count 0 2006.285.06:40:08.72#ibcon#about to read 3, iclass 15, count 0 2006.285.06:40:08.77#ibcon#read 3, iclass 15, count 0 2006.285.06:40:08.77#ibcon#about to read 4, iclass 15, count 0 2006.285.06:40:08.77#ibcon#read 4, iclass 15, count 0 2006.285.06:40:08.77#ibcon#about to read 5, iclass 15, count 0 2006.285.06:40:08.77#ibcon#read 5, iclass 15, count 0 2006.285.06:40:08.77#ibcon#about to read 6, iclass 15, count 0 2006.285.06:40:08.77#ibcon#read 6, iclass 15, count 0 2006.285.06:40:08.77#ibcon#end of sib2, iclass 15, count 0 2006.285.06:40:08.77#ibcon#*after write, iclass 15, count 0 2006.285.06:40:08.77#ibcon#*before return 0, iclass 15, count 0 2006.285.06:40:08.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:40:08.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:40:08.77#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:40:08.77#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:40:08.77$vck44/va=1,7 2006.285.06:40:08.77#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.06:40:08.77#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.06:40:08.77#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:08.77#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:40:08.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:40:08.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:40:08.77#ibcon#enter wrdev, iclass 17, count 2 2006.285.06:40:08.77#ibcon#first serial, iclass 17, count 2 2006.285.06:40:08.77#ibcon#enter sib2, iclass 17, count 2 2006.285.06:40:08.77#ibcon#flushed, iclass 17, count 2 2006.285.06:40:08.77#ibcon#about to write, iclass 17, count 2 2006.285.06:40:08.77#ibcon#wrote, iclass 17, count 2 2006.285.06:40:08.77#ibcon#about to read 3, iclass 17, count 2 2006.285.06:40:08.79#ibcon#read 3, iclass 17, count 2 2006.285.06:40:08.79#ibcon#about to read 4, iclass 17, count 2 2006.285.06:40:08.79#ibcon#read 4, iclass 17, count 2 2006.285.06:40:08.79#ibcon#about to read 5, iclass 17, count 2 2006.285.06:40:08.79#ibcon#read 5, iclass 17, count 2 2006.285.06:40:08.79#ibcon#about to read 6, iclass 17, count 2 2006.285.06:40:08.79#ibcon#read 6, iclass 17, count 2 2006.285.06:40:08.79#ibcon#end of sib2, iclass 17, count 2 2006.285.06:40:08.79#ibcon#*mode == 0, iclass 17, count 2 2006.285.06:40:08.79#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.06:40:08.79#ibcon#[25=AT01-07\r\n] 2006.285.06:40:08.79#ibcon#*before write, iclass 17, count 2 2006.285.06:40:08.79#ibcon#enter sib2, iclass 17, count 2 2006.285.06:40:08.79#ibcon#flushed, iclass 17, count 2 2006.285.06:40:08.79#ibcon#about to write, iclass 17, count 2 2006.285.06:40:08.79#ibcon#wrote, iclass 17, count 2 2006.285.06:40:08.79#ibcon#about to read 3, iclass 17, count 2 2006.285.06:40:08.82#ibcon#read 3, iclass 17, count 2 2006.285.06:40:08.82#ibcon#about to read 4, iclass 17, count 2 2006.285.06:40:08.82#ibcon#read 4, iclass 17, count 2 2006.285.06:40:08.82#ibcon#about to read 5, iclass 17, count 2 2006.285.06:40:08.82#ibcon#read 5, iclass 17, count 2 2006.285.06:40:08.82#ibcon#about to read 6, iclass 17, count 2 2006.285.06:40:08.82#ibcon#read 6, iclass 17, count 2 2006.285.06:40:08.82#ibcon#end of sib2, iclass 17, count 2 2006.285.06:40:08.82#ibcon#*after write, iclass 17, count 2 2006.285.06:40:08.82#ibcon#*before return 0, iclass 17, count 2 2006.285.06:40:08.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:40:08.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:40:08.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.06:40:08.82#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:08.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:40:08.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:40:08.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:40:08.94#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:40:08.94#ibcon#first serial, iclass 17, count 0 2006.285.06:40:08.94#ibcon#enter sib2, iclass 17, count 0 2006.285.06:40:08.94#ibcon#flushed, iclass 17, count 0 2006.285.06:40:08.94#ibcon#about to write, iclass 17, count 0 2006.285.06:40:08.94#ibcon#wrote, iclass 17, count 0 2006.285.06:40:08.94#ibcon#about to read 3, iclass 17, count 0 2006.285.06:40:08.96#ibcon#read 3, iclass 17, count 0 2006.285.06:40:08.96#ibcon#about to read 4, iclass 17, count 0 2006.285.06:40:08.96#ibcon#read 4, iclass 17, count 0 2006.285.06:40:08.96#ibcon#about to read 5, iclass 17, count 0 2006.285.06:40:08.96#ibcon#read 5, iclass 17, count 0 2006.285.06:40:08.96#ibcon#about to read 6, iclass 17, count 0 2006.285.06:40:08.96#ibcon#read 6, iclass 17, count 0 2006.285.06:40:08.96#ibcon#end of sib2, iclass 17, count 0 2006.285.06:40:08.96#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:40:08.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:40:08.96#ibcon#[25=USB\r\n] 2006.285.06:40:08.96#ibcon#*before write, iclass 17, count 0 2006.285.06:40:08.96#ibcon#enter sib2, iclass 17, count 0 2006.285.06:40:08.96#ibcon#flushed, iclass 17, count 0 2006.285.06:40:08.96#ibcon#about to write, iclass 17, count 0 2006.285.06:40:08.96#ibcon#wrote, iclass 17, count 0 2006.285.06:40:08.96#ibcon#about to read 3, iclass 17, count 0 2006.285.06:40:08.99#ibcon#read 3, iclass 17, count 0 2006.285.06:40:08.99#ibcon#about to read 4, iclass 17, count 0 2006.285.06:40:08.99#ibcon#read 4, iclass 17, count 0 2006.285.06:40:08.99#ibcon#about to read 5, iclass 17, count 0 2006.285.06:40:08.99#ibcon#read 5, iclass 17, count 0 2006.285.06:40:08.99#ibcon#about to read 6, iclass 17, count 0 2006.285.06:40:08.99#ibcon#read 6, iclass 17, count 0 2006.285.06:40:08.99#ibcon#end of sib2, iclass 17, count 0 2006.285.06:40:08.99#ibcon#*after write, iclass 17, count 0 2006.285.06:40:08.99#ibcon#*before return 0, iclass 17, count 0 2006.285.06:40:08.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:40:08.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:40:08.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:40:08.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:40:08.99$vck44/valo=2,534.99 2006.285.06:40:08.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.06:40:08.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.06:40:08.99#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:08.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:40:08.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:40:08.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:40:08.99#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:40:08.99#ibcon#first serial, iclass 19, count 0 2006.285.06:40:08.99#ibcon#enter sib2, iclass 19, count 0 2006.285.06:40:08.99#ibcon#flushed, iclass 19, count 0 2006.285.06:40:08.99#ibcon#about to write, iclass 19, count 0 2006.285.06:40:08.99#ibcon#wrote, iclass 19, count 0 2006.285.06:40:08.99#ibcon#about to read 3, iclass 19, count 0 2006.285.06:40:09.01#ibcon#read 3, iclass 19, count 0 2006.285.06:40:09.01#ibcon#about to read 4, iclass 19, count 0 2006.285.06:40:09.01#ibcon#read 4, iclass 19, count 0 2006.285.06:40:09.01#ibcon#about to read 5, iclass 19, count 0 2006.285.06:40:09.01#ibcon#read 5, iclass 19, count 0 2006.285.06:40:09.01#ibcon#about to read 6, iclass 19, count 0 2006.285.06:40:09.01#ibcon#read 6, iclass 19, count 0 2006.285.06:40:09.01#ibcon#end of sib2, iclass 19, count 0 2006.285.06:40:09.01#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:40:09.01#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:40:09.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:40:09.01#ibcon#*before write, iclass 19, count 0 2006.285.06:40:09.01#ibcon#enter sib2, iclass 19, count 0 2006.285.06:40:09.01#ibcon#flushed, iclass 19, count 0 2006.285.06:40:09.01#ibcon#about to write, iclass 19, count 0 2006.285.06:40:09.01#ibcon#wrote, iclass 19, count 0 2006.285.06:40:09.01#ibcon#about to read 3, iclass 19, count 0 2006.285.06:40:09.05#ibcon#read 3, iclass 19, count 0 2006.285.06:40:09.05#ibcon#about to read 4, iclass 19, count 0 2006.285.06:40:09.05#ibcon#read 4, iclass 19, count 0 2006.285.06:40:09.05#ibcon#about to read 5, iclass 19, count 0 2006.285.06:40:09.05#ibcon#read 5, iclass 19, count 0 2006.285.06:40:09.05#ibcon#about to read 6, iclass 19, count 0 2006.285.06:40:09.05#ibcon#read 6, iclass 19, count 0 2006.285.06:40:09.05#ibcon#end of sib2, iclass 19, count 0 2006.285.06:40:09.05#ibcon#*after write, iclass 19, count 0 2006.285.06:40:09.05#ibcon#*before return 0, iclass 19, count 0 2006.285.06:40:09.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:40:09.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:40:09.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:40:09.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:40:09.05$vck44/va=2,6 2006.285.06:40:09.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.06:40:09.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.06:40:09.05#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:09.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:40:09.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:40:09.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:40:09.11#ibcon#enter wrdev, iclass 21, count 2 2006.285.06:40:09.11#ibcon#first serial, iclass 21, count 2 2006.285.06:40:09.11#ibcon#enter sib2, iclass 21, count 2 2006.285.06:40:09.11#ibcon#flushed, iclass 21, count 2 2006.285.06:40:09.11#ibcon#about to write, iclass 21, count 2 2006.285.06:40:09.11#ibcon#wrote, iclass 21, count 2 2006.285.06:40:09.11#ibcon#about to read 3, iclass 21, count 2 2006.285.06:40:09.13#ibcon#read 3, iclass 21, count 2 2006.285.06:40:09.13#ibcon#about to read 4, iclass 21, count 2 2006.285.06:40:09.13#ibcon#read 4, iclass 21, count 2 2006.285.06:40:09.13#ibcon#about to read 5, iclass 21, count 2 2006.285.06:40:09.13#ibcon#read 5, iclass 21, count 2 2006.285.06:40:09.13#ibcon#about to read 6, iclass 21, count 2 2006.285.06:40:09.13#ibcon#read 6, iclass 21, count 2 2006.285.06:40:09.13#ibcon#end of sib2, iclass 21, count 2 2006.285.06:40:09.13#ibcon#*mode == 0, iclass 21, count 2 2006.285.06:40:09.13#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.06:40:09.13#ibcon#[25=AT02-06\r\n] 2006.285.06:40:09.13#ibcon#*before write, iclass 21, count 2 2006.285.06:40:09.13#ibcon#enter sib2, iclass 21, count 2 2006.285.06:40:09.13#ibcon#flushed, iclass 21, count 2 2006.285.06:40:09.13#ibcon#about to write, iclass 21, count 2 2006.285.06:40:09.13#ibcon#wrote, iclass 21, count 2 2006.285.06:40:09.13#ibcon#about to read 3, iclass 21, count 2 2006.285.06:40:09.16#ibcon#read 3, iclass 21, count 2 2006.285.06:40:09.16#ibcon#about to read 4, iclass 21, count 2 2006.285.06:40:09.16#ibcon#read 4, iclass 21, count 2 2006.285.06:40:09.16#ibcon#about to read 5, iclass 21, count 2 2006.285.06:40:09.16#ibcon#read 5, iclass 21, count 2 2006.285.06:40:09.16#ibcon#about to read 6, iclass 21, count 2 2006.285.06:40:09.16#ibcon#read 6, iclass 21, count 2 2006.285.06:40:09.16#ibcon#end of sib2, iclass 21, count 2 2006.285.06:40:09.16#ibcon#*after write, iclass 21, count 2 2006.285.06:40:09.16#ibcon#*before return 0, iclass 21, count 2 2006.285.06:40:09.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:40:09.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:40:09.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.06:40:09.16#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:09.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:40:09.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:40:09.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:40:09.28#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:40:09.28#ibcon#first serial, iclass 21, count 0 2006.285.06:40:09.28#ibcon#enter sib2, iclass 21, count 0 2006.285.06:40:09.28#ibcon#flushed, iclass 21, count 0 2006.285.06:40:09.28#ibcon#about to write, iclass 21, count 0 2006.285.06:40:09.28#ibcon#wrote, iclass 21, count 0 2006.285.06:40:09.28#ibcon#about to read 3, iclass 21, count 0 2006.285.06:40:09.30#ibcon#read 3, iclass 21, count 0 2006.285.06:40:09.30#ibcon#about to read 4, iclass 21, count 0 2006.285.06:40:09.30#ibcon#read 4, iclass 21, count 0 2006.285.06:40:09.30#ibcon#about to read 5, iclass 21, count 0 2006.285.06:40:09.30#ibcon#read 5, iclass 21, count 0 2006.285.06:40:09.30#ibcon#about to read 6, iclass 21, count 0 2006.285.06:40:09.30#ibcon#read 6, iclass 21, count 0 2006.285.06:40:09.30#ibcon#end of sib2, iclass 21, count 0 2006.285.06:40:09.30#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:40:09.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:40:09.30#ibcon#[25=USB\r\n] 2006.285.06:40:09.30#ibcon#*before write, iclass 21, count 0 2006.285.06:40:09.30#ibcon#enter sib2, iclass 21, count 0 2006.285.06:40:09.30#ibcon#flushed, iclass 21, count 0 2006.285.06:40:09.30#ibcon#about to write, iclass 21, count 0 2006.285.06:40:09.30#ibcon#wrote, iclass 21, count 0 2006.285.06:40:09.30#ibcon#about to read 3, iclass 21, count 0 2006.285.06:40:09.33#ibcon#read 3, iclass 21, count 0 2006.285.06:40:09.33#ibcon#about to read 4, iclass 21, count 0 2006.285.06:40:09.33#ibcon#read 4, iclass 21, count 0 2006.285.06:40:09.33#ibcon#about to read 5, iclass 21, count 0 2006.285.06:40:09.33#ibcon#read 5, iclass 21, count 0 2006.285.06:40:09.33#ibcon#about to read 6, iclass 21, count 0 2006.285.06:40:09.33#ibcon#read 6, iclass 21, count 0 2006.285.06:40:09.33#ibcon#end of sib2, iclass 21, count 0 2006.285.06:40:09.33#ibcon#*after write, iclass 21, count 0 2006.285.06:40:09.33#ibcon#*before return 0, iclass 21, count 0 2006.285.06:40:09.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:40:09.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:40:09.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:40:09.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:40:09.33$vck44/valo=3,564.99 2006.285.06:40:09.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.06:40:09.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.06:40:09.33#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:09.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:40:09.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:40:09.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:40:09.33#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:40:09.33#ibcon#first serial, iclass 23, count 0 2006.285.06:40:09.33#ibcon#enter sib2, iclass 23, count 0 2006.285.06:40:09.33#ibcon#flushed, iclass 23, count 0 2006.285.06:40:09.33#ibcon#about to write, iclass 23, count 0 2006.285.06:40:09.33#ibcon#wrote, iclass 23, count 0 2006.285.06:40:09.33#ibcon#about to read 3, iclass 23, count 0 2006.285.06:40:09.35#ibcon#read 3, iclass 23, count 0 2006.285.06:40:09.35#ibcon#about to read 4, iclass 23, count 0 2006.285.06:40:09.35#ibcon#read 4, iclass 23, count 0 2006.285.06:40:09.35#ibcon#about to read 5, iclass 23, count 0 2006.285.06:40:09.35#ibcon#read 5, iclass 23, count 0 2006.285.06:40:09.35#ibcon#about to read 6, iclass 23, count 0 2006.285.06:40:09.35#ibcon#read 6, iclass 23, count 0 2006.285.06:40:09.35#ibcon#end of sib2, iclass 23, count 0 2006.285.06:40:09.35#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:40:09.35#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:40:09.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:40:09.35#ibcon#*before write, iclass 23, count 0 2006.285.06:40:09.35#ibcon#enter sib2, iclass 23, count 0 2006.285.06:40:09.35#ibcon#flushed, iclass 23, count 0 2006.285.06:40:09.35#ibcon#about to write, iclass 23, count 0 2006.285.06:40:09.35#ibcon#wrote, iclass 23, count 0 2006.285.06:40:09.35#ibcon#about to read 3, iclass 23, count 0 2006.285.06:40:09.39#ibcon#read 3, iclass 23, count 0 2006.285.06:40:09.39#ibcon#about to read 4, iclass 23, count 0 2006.285.06:40:09.39#ibcon#read 4, iclass 23, count 0 2006.285.06:40:09.39#ibcon#about to read 5, iclass 23, count 0 2006.285.06:40:09.39#ibcon#read 5, iclass 23, count 0 2006.285.06:40:09.39#ibcon#about to read 6, iclass 23, count 0 2006.285.06:40:09.39#ibcon#read 6, iclass 23, count 0 2006.285.06:40:09.39#ibcon#end of sib2, iclass 23, count 0 2006.285.06:40:09.39#ibcon#*after write, iclass 23, count 0 2006.285.06:40:09.39#ibcon#*before return 0, iclass 23, count 0 2006.285.06:40:09.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:40:09.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:40:09.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:40:09.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:40:09.39$vck44/va=3,7 2006.285.06:40:09.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.06:40:09.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.06:40:09.39#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:09.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:40:09.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:40:09.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:40:09.45#ibcon#enter wrdev, iclass 25, count 2 2006.285.06:40:09.45#ibcon#first serial, iclass 25, count 2 2006.285.06:40:09.45#ibcon#enter sib2, iclass 25, count 2 2006.285.06:40:09.45#ibcon#flushed, iclass 25, count 2 2006.285.06:40:09.45#ibcon#about to write, iclass 25, count 2 2006.285.06:40:09.45#ibcon#wrote, iclass 25, count 2 2006.285.06:40:09.45#ibcon#about to read 3, iclass 25, count 2 2006.285.06:40:09.47#ibcon#read 3, iclass 25, count 2 2006.285.06:40:09.47#ibcon#about to read 4, iclass 25, count 2 2006.285.06:40:09.47#ibcon#read 4, iclass 25, count 2 2006.285.06:40:09.47#ibcon#about to read 5, iclass 25, count 2 2006.285.06:40:09.47#ibcon#read 5, iclass 25, count 2 2006.285.06:40:09.47#ibcon#about to read 6, iclass 25, count 2 2006.285.06:40:09.47#ibcon#read 6, iclass 25, count 2 2006.285.06:40:09.47#ibcon#end of sib2, iclass 25, count 2 2006.285.06:40:09.47#ibcon#*mode == 0, iclass 25, count 2 2006.285.06:40:09.47#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.06:40:09.47#ibcon#[25=AT03-07\r\n] 2006.285.06:40:09.47#ibcon#*before write, iclass 25, count 2 2006.285.06:40:09.47#ibcon#enter sib2, iclass 25, count 2 2006.285.06:40:09.47#ibcon#flushed, iclass 25, count 2 2006.285.06:40:09.47#ibcon#about to write, iclass 25, count 2 2006.285.06:40:09.47#ibcon#wrote, iclass 25, count 2 2006.285.06:40:09.47#ibcon#about to read 3, iclass 25, count 2 2006.285.06:40:09.50#ibcon#read 3, iclass 25, count 2 2006.285.06:40:09.50#ibcon#about to read 4, iclass 25, count 2 2006.285.06:40:09.50#ibcon#read 4, iclass 25, count 2 2006.285.06:40:09.50#ibcon#about to read 5, iclass 25, count 2 2006.285.06:40:09.50#ibcon#read 5, iclass 25, count 2 2006.285.06:40:09.50#ibcon#about to read 6, iclass 25, count 2 2006.285.06:40:09.50#ibcon#read 6, iclass 25, count 2 2006.285.06:40:09.50#ibcon#end of sib2, iclass 25, count 2 2006.285.06:40:09.50#ibcon#*after write, iclass 25, count 2 2006.285.06:40:09.50#ibcon#*before return 0, iclass 25, count 2 2006.285.06:40:09.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:40:09.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:40:09.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.06:40:09.50#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:09.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:40:09.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:40:09.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:40:09.62#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:40:09.62#ibcon#first serial, iclass 25, count 0 2006.285.06:40:09.62#ibcon#enter sib2, iclass 25, count 0 2006.285.06:40:09.62#ibcon#flushed, iclass 25, count 0 2006.285.06:40:09.62#ibcon#about to write, iclass 25, count 0 2006.285.06:40:09.62#ibcon#wrote, iclass 25, count 0 2006.285.06:40:09.62#ibcon#about to read 3, iclass 25, count 0 2006.285.06:40:09.64#ibcon#read 3, iclass 25, count 0 2006.285.06:40:09.64#ibcon#about to read 4, iclass 25, count 0 2006.285.06:40:09.64#ibcon#read 4, iclass 25, count 0 2006.285.06:40:09.64#ibcon#about to read 5, iclass 25, count 0 2006.285.06:40:09.64#ibcon#read 5, iclass 25, count 0 2006.285.06:40:09.64#ibcon#about to read 6, iclass 25, count 0 2006.285.06:40:09.64#ibcon#read 6, iclass 25, count 0 2006.285.06:40:09.64#ibcon#end of sib2, iclass 25, count 0 2006.285.06:40:09.64#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:40:09.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:40:09.64#ibcon#[25=USB\r\n] 2006.285.06:40:09.64#ibcon#*before write, iclass 25, count 0 2006.285.06:40:09.64#ibcon#enter sib2, iclass 25, count 0 2006.285.06:40:09.64#ibcon#flushed, iclass 25, count 0 2006.285.06:40:09.64#ibcon#about to write, iclass 25, count 0 2006.285.06:40:09.64#ibcon#wrote, iclass 25, count 0 2006.285.06:40:09.64#ibcon#about to read 3, iclass 25, count 0 2006.285.06:40:09.67#ibcon#read 3, iclass 25, count 0 2006.285.06:40:09.67#ibcon#about to read 4, iclass 25, count 0 2006.285.06:40:09.67#ibcon#read 4, iclass 25, count 0 2006.285.06:40:09.67#ibcon#about to read 5, iclass 25, count 0 2006.285.06:40:09.67#ibcon#read 5, iclass 25, count 0 2006.285.06:40:09.67#ibcon#about to read 6, iclass 25, count 0 2006.285.06:40:09.67#ibcon#read 6, iclass 25, count 0 2006.285.06:40:09.67#ibcon#end of sib2, iclass 25, count 0 2006.285.06:40:09.67#ibcon#*after write, iclass 25, count 0 2006.285.06:40:09.67#ibcon#*before return 0, iclass 25, count 0 2006.285.06:40:09.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:40:09.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:40:09.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:40:09.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:40:09.67$vck44/valo=4,624.99 2006.285.06:40:09.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.06:40:09.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.06:40:09.67#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:09.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:40:09.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:40:09.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:40:09.67#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:40:09.67#ibcon#first serial, iclass 27, count 0 2006.285.06:40:09.67#ibcon#enter sib2, iclass 27, count 0 2006.285.06:40:09.67#ibcon#flushed, iclass 27, count 0 2006.285.06:40:09.67#ibcon#about to write, iclass 27, count 0 2006.285.06:40:09.67#ibcon#wrote, iclass 27, count 0 2006.285.06:40:09.67#ibcon#about to read 3, iclass 27, count 0 2006.285.06:40:09.69#ibcon#read 3, iclass 27, count 0 2006.285.06:40:09.69#ibcon#about to read 4, iclass 27, count 0 2006.285.06:40:09.69#ibcon#read 4, iclass 27, count 0 2006.285.06:40:09.69#ibcon#about to read 5, iclass 27, count 0 2006.285.06:40:09.69#ibcon#read 5, iclass 27, count 0 2006.285.06:40:09.69#ibcon#about to read 6, iclass 27, count 0 2006.285.06:40:09.69#ibcon#read 6, iclass 27, count 0 2006.285.06:40:09.69#ibcon#end of sib2, iclass 27, count 0 2006.285.06:40:09.69#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:40:09.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:40:09.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:40:09.69#ibcon#*before write, iclass 27, count 0 2006.285.06:40:09.69#ibcon#enter sib2, iclass 27, count 0 2006.285.06:40:09.69#ibcon#flushed, iclass 27, count 0 2006.285.06:40:09.69#ibcon#about to write, iclass 27, count 0 2006.285.06:40:09.69#ibcon#wrote, iclass 27, count 0 2006.285.06:40:09.69#ibcon#about to read 3, iclass 27, count 0 2006.285.06:40:09.73#ibcon#read 3, iclass 27, count 0 2006.285.06:40:09.73#ibcon#about to read 4, iclass 27, count 0 2006.285.06:40:09.73#ibcon#read 4, iclass 27, count 0 2006.285.06:40:09.73#ibcon#about to read 5, iclass 27, count 0 2006.285.06:40:09.73#ibcon#read 5, iclass 27, count 0 2006.285.06:40:09.73#ibcon#about to read 6, iclass 27, count 0 2006.285.06:40:09.73#ibcon#read 6, iclass 27, count 0 2006.285.06:40:09.73#ibcon#end of sib2, iclass 27, count 0 2006.285.06:40:09.73#ibcon#*after write, iclass 27, count 0 2006.285.06:40:09.73#ibcon#*before return 0, iclass 27, count 0 2006.285.06:40:09.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:40:09.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:40:09.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:40:09.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:40:09.73$vck44/va=4,6 2006.285.06:40:09.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.06:40:09.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.06:40:09.73#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:09.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:40:09.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:40:09.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:40:09.79#ibcon#enter wrdev, iclass 29, count 2 2006.285.06:40:09.79#ibcon#first serial, iclass 29, count 2 2006.285.06:40:09.79#ibcon#enter sib2, iclass 29, count 2 2006.285.06:40:09.79#ibcon#flushed, iclass 29, count 2 2006.285.06:40:09.79#ibcon#about to write, iclass 29, count 2 2006.285.06:40:09.79#ibcon#wrote, iclass 29, count 2 2006.285.06:40:09.79#ibcon#about to read 3, iclass 29, count 2 2006.285.06:40:09.81#ibcon#read 3, iclass 29, count 2 2006.285.06:40:09.81#ibcon#about to read 4, iclass 29, count 2 2006.285.06:40:09.81#ibcon#read 4, iclass 29, count 2 2006.285.06:40:09.81#ibcon#about to read 5, iclass 29, count 2 2006.285.06:40:09.81#ibcon#read 5, iclass 29, count 2 2006.285.06:40:09.81#ibcon#about to read 6, iclass 29, count 2 2006.285.06:40:09.81#ibcon#read 6, iclass 29, count 2 2006.285.06:40:09.81#ibcon#end of sib2, iclass 29, count 2 2006.285.06:40:09.81#ibcon#*mode == 0, iclass 29, count 2 2006.285.06:40:09.81#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.06:40:09.81#ibcon#[25=AT04-06\r\n] 2006.285.06:40:09.81#ibcon#*before write, iclass 29, count 2 2006.285.06:40:09.81#ibcon#enter sib2, iclass 29, count 2 2006.285.06:40:09.81#ibcon#flushed, iclass 29, count 2 2006.285.06:40:09.81#ibcon#about to write, iclass 29, count 2 2006.285.06:40:09.81#ibcon#wrote, iclass 29, count 2 2006.285.06:40:09.81#ibcon#about to read 3, iclass 29, count 2 2006.285.06:40:09.84#ibcon#read 3, iclass 29, count 2 2006.285.06:40:09.84#ibcon#about to read 4, iclass 29, count 2 2006.285.06:40:09.84#ibcon#read 4, iclass 29, count 2 2006.285.06:40:09.84#ibcon#about to read 5, iclass 29, count 2 2006.285.06:40:09.84#ibcon#read 5, iclass 29, count 2 2006.285.06:40:09.84#ibcon#about to read 6, iclass 29, count 2 2006.285.06:40:09.84#ibcon#read 6, iclass 29, count 2 2006.285.06:40:09.84#ibcon#end of sib2, iclass 29, count 2 2006.285.06:40:09.84#ibcon#*after write, iclass 29, count 2 2006.285.06:40:09.84#ibcon#*before return 0, iclass 29, count 2 2006.285.06:40:09.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:40:09.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:40:09.84#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.06:40:09.84#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:09.84#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:40:09.96#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:40:09.96#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:40:09.96#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:40:09.96#ibcon#first serial, iclass 29, count 0 2006.285.06:40:09.96#ibcon#enter sib2, iclass 29, count 0 2006.285.06:40:09.96#ibcon#flushed, iclass 29, count 0 2006.285.06:40:09.96#ibcon#about to write, iclass 29, count 0 2006.285.06:40:09.96#ibcon#wrote, iclass 29, count 0 2006.285.06:40:09.96#ibcon#about to read 3, iclass 29, count 0 2006.285.06:40:09.98#ibcon#read 3, iclass 29, count 0 2006.285.06:40:09.98#ibcon#about to read 4, iclass 29, count 0 2006.285.06:40:09.98#ibcon#read 4, iclass 29, count 0 2006.285.06:40:09.98#ibcon#about to read 5, iclass 29, count 0 2006.285.06:40:09.98#ibcon#read 5, iclass 29, count 0 2006.285.06:40:09.98#ibcon#about to read 6, iclass 29, count 0 2006.285.06:40:09.98#ibcon#read 6, iclass 29, count 0 2006.285.06:40:09.98#ibcon#end of sib2, iclass 29, count 0 2006.285.06:40:09.98#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:40:09.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:40:09.98#ibcon#[25=USB\r\n] 2006.285.06:40:09.98#ibcon#*before write, iclass 29, count 0 2006.285.06:40:09.98#ibcon#enter sib2, iclass 29, count 0 2006.285.06:40:09.98#ibcon#flushed, iclass 29, count 0 2006.285.06:40:09.98#ibcon#about to write, iclass 29, count 0 2006.285.06:40:09.98#ibcon#wrote, iclass 29, count 0 2006.285.06:40:09.98#ibcon#about to read 3, iclass 29, count 0 2006.285.06:40:10.01#ibcon#read 3, iclass 29, count 0 2006.285.06:40:10.01#ibcon#about to read 4, iclass 29, count 0 2006.285.06:40:10.01#ibcon#read 4, iclass 29, count 0 2006.285.06:40:10.01#ibcon#about to read 5, iclass 29, count 0 2006.285.06:40:10.01#ibcon#read 5, iclass 29, count 0 2006.285.06:40:10.01#ibcon#about to read 6, iclass 29, count 0 2006.285.06:40:10.01#ibcon#read 6, iclass 29, count 0 2006.285.06:40:10.01#ibcon#end of sib2, iclass 29, count 0 2006.285.06:40:10.01#ibcon#*after write, iclass 29, count 0 2006.285.06:40:10.01#ibcon#*before return 0, iclass 29, count 0 2006.285.06:40:10.01#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:40:10.01#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:40:10.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:40:10.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:40:10.01$vck44/valo=5,734.99 2006.285.06:40:10.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.06:40:10.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.06:40:10.01#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:10.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:40:10.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:40:10.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:40:10.01#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:40:10.01#ibcon#first serial, iclass 31, count 0 2006.285.06:40:10.01#ibcon#enter sib2, iclass 31, count 0 2006.285.06:40:10.01#ibcon#flushed, iclass 31, count 0 2006.285.06:40:10.01#ibcon#about to write, iclass 31, count 0 2006.285.06:40:10.01#ibcon#wrote, iclass 31, count 0 2006.285.06:40:10.01#ibcon#about to read 3, iclass 31, count 0 2006.285.06:40:10.03#ibcon#read 3, iclass 31, count 0 2006.285.06:40:10.03#ibcon#about to read 4, iclass 31, count 0 2006.285.06:40:10.03#ibcon#read 4, iclass 31, count 0 2006.285.06:40:10.03#ibcon#about to read 5, iclass 31, count 0 2006.285.06:40:10.03#ibcon#read 5, iclass 31, count 0 2006.285.06:40:10.03#ibcon#about to read 6, iclass 31, count 0 2006.285.06:40:10.03#ibcon#read 6, iclass 31, count 0 2006.285.06:40:10.03#ibcon#end of sib2, iclass 31, count 0 2006.285.06:40:10.03#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:40:10.03#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:40:10.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:40:10.03#ibcon#*before write, iclass 31, count 0 2006.285.06:40:10.03#ibcon#enter sib2, iclass 31, count 0 2006.285.06:40:10.03#ibcon#flushed, iclass 31, count 0 2006.285.06:40:10.03#ibcon#about to write, iclass 31, count 0 2006.285.06:40:10.03#ibcon#wrote, iclass 31, count 0 2006.285.06:40:10.03#ibcon#about to read 3, iclass 31, count 0 2006.285.06:40:10.07#ibcon#read 3, iclass 31, count 0 2006.285.06:40:10.07#ibcon#about to read 4, iclass 31, count 0 2006.285.06:40:10.07#ibcon#read 4, iclass 31, count 0 2006.285.06:40:10.07#ibcon#about to read 5, iclass 31, count 0 2006.285.06:40:10.07#ibcon#read 5, iclass 31, count 0 2006.285.06:40:10.07#ibcon#about to read 6, iclass 31, count 0 2006.285.06:40:10.07#ibcon#read 6, iclass 31, count 0 2006.285.06:40:10.07#ibcon#end of sib2, iclass 31, count 0 2006.285.06:40:10.07#ibcon#*after write, iclass 31, count 0 2006.285.06:40:10.07#ibcon#*before return 0, iclass 31, count 0 2006.285.06:40:10.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:40:10.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:40:10.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:40:10.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:40:10.07$vck44/va=5,3 2006.285.06:40:10.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.06:40:10.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.06:40:10.07#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:10.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:40:10.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:40:10.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:40:10.13#ibcon#enter wrdev, iclass 33, count 2 2006.285.06:40:10.13#ibcon#first serial, iclass 33, count 2 2006.285.06:40:10.13#ibcon#enter sib2, iclass 33, count 2 2006.285.06:40:10.13#ibcon#flushed, iclass 33, count 2 2006.285.06:40:10.13#ibcon#about to write, iclass 33, count 2 2006.285.06:40:10.13#ibcon#wrote, iclass 33, count 2 2006.285.06:40:10.13#ibcon#about to read 3, iclass 33, count 2 2006.285.06:40:10.15#ibcon#read 3, iclass 33, count 2 2006.285.06:40:10.15#ibcon#about to read 4, iclass 33, count 2 2006.285.06:40:10.15#ibcon#read 4, iclass 33, count 2 2006.285.06:40:10.15#ibcon#about to read 5, iclass 33, count 2 2006.285.06:40:10.15#ibcon#read 5, iclass 33, count 2 2006.285.06:40:10.15#ibcon#about to read 6, iclass 33, count 2 2006.285.06:40:10.15#ibcon#read 6, iclass 33, count 2 2006.285.06:40:10.15#ibcon#end of sib2, iclass 33, count 2 2006.285.06:40:10.15#ibcon#*mode == 0, iclass 33, count 2 2006.285.06:40:10.15#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.06:40:10.15#ibcon#[25=AT05-03\r\n] 2006.285.06:40:10.15#ibcon#*before write, iclass 33, count 2 2006.285.06:40:10.15#ibcon#enter sib2, iclass 33, count 2 2006.285.06:40:10.15#ibcon#flushed, iclass 33, count 2 2006.285.06:40:10.15#ibcon#about to write, iclass 33, count 2 2006.285.06:40:10.15#ibcon#wrote, iclass 33, count 2 2006.285.06:40:10.15#ibcon#about to read 3, iclass 33, count 2 2006.285.06:40:10.18#ibcon#read 3, iclass 33, count 2 2006.285.06:40:10.18#ibcon#about to read 4, iclass 33, count 2 2006.285.06:40:10.18#ibcon#read 4, iclass 33, count 2 2006.285.06:40:10.18#ibcon#about to read 5, iclass 33, count 2 2006.285.06:40:10.18#ibcon#read 5, iclass 33, count 2 2006.285.06:40:10.18#ibcon#about to read 6, iclass 33, count 2 2006.285.06:40:10.18#ibcon#read 6, iclass 33, count 2 2006.285.06:40:10.18#ibcon#end of sib2, iclass 33, count 2 2006.285.06:40:10.18#ibcon#*after write, iclass 33, count 2 2006.285.06:40:10.18#ibcon#*before return 0, iclass 33, count 2 2006.285.06:40:10.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:40:10.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:40:10.18#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.06:40:10.18#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:10.18#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:40:10.30#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:40:10.30#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:40:10.30#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:40:10.30#ibcon#first serial, iclass 33, count 0 2006.285.06:40:10.30#ibcon#enter sib2, iclass 33, count 0 2006.285.06:40:10.30#ibcon#flushed, iclass 33, count 0 2006.285.06:40:10.30#ibcon#about to write, iclass 33, count 0 2006.285.06:40:10.30#ibcon#wrote, iclass 33, count 0 2006.285.06:40:10.30#ibcon#about to read 3, iclass 33, count 0 2006.285.06:40:10.32#ibcon#read 3, iclass 33, count 0 2006.285.06:40:10.32#ibcon#about to read 4, iclass 33, count 0 2006.285.06:40:10.32#ibcon#read 4, iclass 33, count 0 2006.285.06:40:10.32#ibcon#about to read 5, iclass 33, count 0 2006.285.06:40:10.32#ibcon#read 5, iclass 33, count 0 2006.285.06:40:10.32#ibcon#about to read 6, iclass 33, count 0 2006.285.06:40:10.32#ibcon#read 6, iclass 33, count 0 2006.285.06:40:10.32#ibcon#end of sib2, iclass 33, count 0 2006.285.06:40:10.32#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:40:10.32#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:40:10.32#ibcon#[25=USB\r\n] 2006.285.06:40:10.32#ibcon#*before write, iclass 33, count 0 2006.285.06:40:10.32#ibcon#enter sib2, iclass 33, count 0 2006.285.06:40:10.32#ibcon#flushed, iclass 33, count 0 2006.285.06:40:10.32#ibcon#about to write, iclass 33, count 0 2006.285.06:40:10.32#ibcon#wrote, iclass 33, count 0 2006.285.06:40:10.32#ibcon#about to read 3, iclass 33, count 0 2006.285.06:40:10.35#ibcon#read 3, iclass 33, count 0 2006.285.06:40:10.35#ibcon#about to read 4, iclass 33, count 0 2006.285.06:40:10.35#ibcon#read 4, iclass 33, count 0 2006.285.06:40:10.35#ibcon#about to read 5, iclass 33, count 0 2006.285.06:40:10.35#ibcon#read 5, iclass 33, count 0 2006.285.06:40:10.35#ibcon#about to read 6, iclass 33, count 0 2006.285.06:40:10.35#ibcon#read 6, iclass 33, count 0 2006.285.06:40:10.35#ibcon#end of sib2, iclass 33, count 0 2006.285.06:40:10.35#ibcon#*after write, iclass 33, count 0 2006.285.06:40:10.35#ibcon#*before return 0, iclass 33, count 0 2006.285.06:40:10.35#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:40:10.35#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:40:10.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:40:10.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:40:10.35$vck44/valo=6,814.99 2006.285.06:40:10.35#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.06:40:10.35#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.06:40:10.35#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:10.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:40:10.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:40:10.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:40:10.35#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:40:10.35#ibcon#first serial, iclass 35, count 0 2006.285.06:40:10.35#ibcon#enter sib2, iclass 35, count 0 2006.285.06:40:10.35#ibcon#flushed, iclass 35, count 0 2006.285.06:40:10.35#ibcon#about to write, iclass 35, count 0 2006.285.06:40:10.35#ibcon#wrote, iclass 35, count 0 2006.285.06:40:10.35#ibcon#about to read 3, iclass 35, count 0 2006.285.06:40:10.37#ibcon#read 3, iclass 35, count 0 2006.285.06:40:10.37#ibcon#about to read 4, iclass 35, count 0 2006.285.06:40:10.37#ibcon#read 4, iclass 35, count 0 2006.285.06:40:10.37#ibcon#about to read 5, iclass 35, count 0 2006.285.06:40:10.37#ibcon#read 5, iclass 35, count 0 2006.285.06:40:10.37#ibcon#about to read 6, iclass 35, count 0 2006.285.06:40:10.37#ibcon#read 6, iclass 35, count 0 2006.285.06:40:10.37#ibcon#end of sib2, iclass 35, count 0 2006.285.06:40:10.37#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:40:10.37#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:40:10.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:40:10.37#ibcon#*before write, iclass 35, count 0 2006.285.06:40:10.37#ibcon#enter sib2, iclass 35, count 0 2006.285.06:40:10.37#ibcon#flushed, iclass 35, count 0 2006.285.06:40:10.37#ibcon#about to write, iclass 35, count 0 2006.285.06:40:10.37#ibcon#wrote, iclass 35, count 0 2006.285.06:40:10.37#ibcon#about to read 3, iclass 35, count 0 2006.285.06:40:10.41#ibcon#read 3, iclass 35, count 0 2006.285.06:40:10.41#ibcon#about to read 4, iclass 35, count 0 2006.285.06:40:10.41#ibcon#read 4, iclass 35, count 0 2006.285.06:40:10.41#ibcon#about to read 5, iclass 35, count 0 2006.285.06:40:10.41#ibcon#read 5, iclass 35, count 0 2006.285.06:40:10.41#ibcon#about to read 6, iclass 35, count 0 2006.285.06:40:10.41#ibcon#read 6, iclass 35, count 0 2006.285.06:40:10.41#ibcon#end of sib2, iclass 35, count 0 2006.285.06:40:10.41#ibcon#*after write, iclass 35, count 0 2006.285.06:40:10.41#ibcon#*before return 0, iclass 35, count 0 2006.285.06:40:10.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:40:10.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:40:10.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:40:10.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:40:10.41$vck44/va=6,4 2006.285.06:40:10.41#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.06:40:10.41#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.06:40:10.41#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:10.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:40:10.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:40:10.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:40:10.47#ibcon#enter wrdev, iclass 37, count 2 2006.285.06:40:10.47#ibcon#first serial, iclass 37, count 2 2006.285.06:40:10.47#ibcon#enter sib2, iclass 37, count 2 2006.285.06:40:10.47#ibcon#flushed, iclass 37, count 2 2006.285.06:40:10.47#ibcon#about to write, iclass 37, count 2 2006.285.06:40:10.47#ibcon#wrote, iclass 37, count 2 2006.285.06:40:10.47#ibcon#about to read 3, iclass 37, count 2 2006.285.06:40:10.49#ibcon#read 3, iclass 37, count 2 2006.285.06:40:10.49#ibcon#about to read 4, iclass 37, count 2 2006.285.06:40:10.49#ibcon#read 4, iclass 37, count 2 2006.285.06:40:10.49#ibcon#about to read 5, iclass 37, count 2 2006.285.06:40:10.49#ibcon#read 5, iclass 37, count 2 2006.285.06:40:10.49#ibcon#about to read 6, iclass 37, count 2 2006.285.06:40:10.49#ibcon#read 6, iclass 37, count 2 2006.285.06:40:10.49#ibcon#end of sib2, iclass 37, count 2 2006.285.06:40:10.49#ibcon#*mode == 0, iclass 37, count 2 2006.285.06:40:10.49#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.06:40:10.49#ibcon#[25=AT06-04\r\n] 2006.285.06:40:10.49#ibcon#*before write, iclass 37, count 2 2006.285.06:40:10.49#ibcon#enter sib2, iclass 37, count 2 2006.285.06:40:10.49#ibcon#flushed, iclass 37, count 2 2006.285.06:40:10.49#ibcon#about to write, iclass 37, count 2 2006.285.06:40:10.49#ibcon#wrote, iclass 37, count 2 2006.285.06:40:10.49#ibcon#about to read 3, iclass 37, count 2 2006.285.06:40:10.52#ibcon#read 3, iclass 37, count 2 2006.285.06:40:10.52#ibcon#about to read 4, iclass 37, count 2 2006.285.06:40:10.52#ibcon#read 4, iclass 37, count 2 2006.285.06:40:10.52#ibcon#about to read 5, iclass 37, count 2 2006.285.06:40:10.52#ibcon#read 5, iclass 37, count 2 2006.285.06:40:10.52#ibcon#about to read 6, iclass 37, count 2 2006.285.06:40:10.52#ibcon#read 6, iclass 37, count 2 2006.285.06:40:10.52#ibcon#end of sib2, iclass 37, count 2 2006.285.06:40:10.52#ibcon#*after write, iclass 37, count 2 2006.285.06:40:10.52#ibcon#*before return 0, iclass 37, count 2 2006.285.06:40:10.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:40:10.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:40:10.52#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.06:40:10.52#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:10.52#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:40:10.64#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:40:10.64#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:40:10.64#ibcon#enter wrdev, iclass 37, count 0 2006.285.06:40:10.64#ibcon#first serial, iclass 37, count 0 2006.285.06:40:10.64#ibcon#enter sib2, iclass 37, count 0 2006.285.06:40:10.64#ibcon#flushed, iclass 37, count 0 2006.285.06:40:10.64#ibcon#about to write, iclass 37, count 0 2006.285.06:40:10.64#ibcon#wrote, iclass 37, count 0 2006.285.06:40:10.64#ibcon#about to read 3, iclass 37, count 0 2006.285.06:40:10.66#ibcon#read 3, iclass 37, count 0 2006.285.06:40:10.66#ibcon#about to read 4, iclass 37, count 0 2006.285.06:40:10.66#ibcon#read 4, iclass 37, count 0 2006.285.06:40:10.66#ibcon#about to read 5, iclass 37, count 0 2006.285.06:40:10.66#ibcon#read 5, iclass 37, count 0 2006.285.06:40:10.66#ibcon#about to read 6, iclass 37, count 0 2006.285.06:40:10.66#ibcon#read 6, iclass 37, count 0 2006.285.06:40:10.66#ibcon#end of sib2, iclass 37, count 0 2006.285.06:40:10.66#ibcon#*mode == 0, iclass 37, count 0 2006.285.06:40:10.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.06:40:10.66#ibcon#[25=USB\r\n] 2006.285.06:40:10.66#ibcon#*before write, iclass 37, count 0 2006.285.06:40:10.66#ibcon#enter sib2, iclass 37, count 0 2006.285.06:40:10.66#ibcon#flushed, iclass 37, count 0 2006.285.06:40:10.66#ibcon#about to write, iclass 37, count 0 2006.285.06:40:10.66#ibcon#wrote, iclass 37, count 0 2006.285.06:40:10.66#ibcon#about to read 3, iclass 37, count 0 2006.285.06:40:10.69#ibcon#read 3, iclass 37, count 0 2006.285.06:40:10.69#ibcon#about to read 4, iclass 37, count 0 2006.285.06:40:10.69#ibcon#read 4, iclass 37, count 0 2006.285.06:40:10.69#ibcon#about to read 5, iclass 37, count 0 2006.285.06:40:10.69#ibcon#read 5, iclass 37, count 0 2006.285.06:40:10.69#ibcon#about to read 6, iclass 37, count 0 2006.285.06:40:10.69#ibcon#read 6, iclass 37, count 0 2006.285.06:40:10.69#ibcon#end of sib2, iclass 37, count 0 2006.285.06:40:10.69#ibcon#*after write, iclass 37, count 0 2006.285.06:40:10.69#ibcon#*before return 0, iclass 37, count 0 2006.285.06:40:10.69#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:40:10.69#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:40:10.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.06:40:10.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.06:40:10.69$vck44/valo=7,864.99 2006.285.06:40:10.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.06:40:10.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.06:40:10.69#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:10.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:40:10.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:40:10.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:40:10.69#ibcon#enter wrdev, iclass 39, count 0 2006.285.06:40:10.69#ibcon#first serial, iclass 39, count 0 2006.285.06:40:10.69#ibcon#enter sib2, iclass 39, count 0 2006.285.06:40:10.69#ibcon#flushed, iclass 39, count 0 2006.285.06:40:10.69#ibcon#about to write, iclass 39, count 0 2006.285.06:40:10.69#ibcon#wrote, iclass 39, count 0 2006.285.06:40:10.69#ibcon#about to read 3, iclass 39, count 0 2006.285.06:40:10.71#ibcon#read 3, iclass 39, count 0 2006.285.06:40:10.71#ibcon#about to read 4, iclass 39, count 0 2006.285.06:40:10.71#ibcon#read 4, iclass 39, count 0 2006.285.06:40:10.71#ibcon#about to read 5, iclass 39, count 0 2006.285.06:40:10.71#ibcon#read 5, iclass 39, count 0 2006.285.06:40:10.71#ibcon#about to read 6, iclass 39, count 0 2006.285.06:40:10.71#ibcon#read 6, iclass 39, count 0 2006.285.06:40:10.71#ibcon#end of sib2, iclass 39, count 0 2006.285.06:40:10.71#ibcon#*mode == 0, iclass 39, count 0 2006.285.06:40:10.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.06:40:10.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:40:10.71#ibcon#*before write, iclass 39, count 0 2006.285.06:40:10.71#ibcon#enter sib2, iclass 39, count 0 2006.285.06:40:10.71#ibcon#flushed, iclass 39, count 0 2006.285.06:40:10.71#ibcon#about to write, iclass 39, count 0 2006.285.06:40:10.71#ibcon#wrote, iclass 39, count 0 2006.285.06:40:10.71#ibcon#about to read 3, iclass 39, count 0 2006.285.06:40:10.75#ibcon#read 3, iclass 39, count 0 2006.285.06:40:10.75#ibcon#about to read 4, iclass 39, count 0 2006.285.06:40:10.75#ibcon#read 4, iclass 39, count 0 2006.285.06:40:10.75#ibcon#about to read 5, iclass 39, count 0 2006.285.06:40:10.75#ibcon#read 5, iclass 39, count 0 2006.285.06:40:10.75#ibcon#about to read 6, iclass 39, count 0 2006.285.06:40:10.75#ibcon#read 6, iclass 39, count 0 2006.285.06:40:10.75#ibcon#end of sib2, iclass 39, count 0 2006.285.06:40:10.75#ibcon#*after write, iclass 39, count 0 2006.285.06:40:10.75#ibcon#*before return 0, iclass 39, count 0 2006.285.06:40:10.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:40:10.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:40:10.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.06:40:10.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.06:40:10.75$vck44/va=7,4 2006.285.06:40:10.75#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.06:40:10.75#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.06:40:10.75#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:10.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:40:10.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:40:10.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:40:10.81#ibcon#enter wrdev, iclass 3, count 2 2006.285.06:40:10.81#ibcon#first serial, iclass 3, count 2 2006.285.06:40:10.81#ibcon#enter sib2, iclass 3, count 2 2006.285.06:40:10.81#ibcon#flushed, iclass 3, count 2 2006.285.06:40:10.81#ibcon#about to write, iclass 3, count 2 2006.285.06:40:10.81#ibcon#wrote, iclass 3, count 2 2006.285.06:40:10.81#ibcon#about to read 3, iclass 3, count 2 2006.285.06:40:10.83#ibcon#read 3, iclass 3, count 2 2006.285.06:40:10.83#ibcon#about to read 4, iclass 3, count 2 2006.285.06:40:10.83#ibcon#read 4, iclass 3, count 2 2006.285.06:40:10.83#ibcon#about to read 5, iclass 3, count 2 2006.285.06:40:10.83#ibcon#read 5, iclass 3, count 2 2006.285.06:40:10.83#ibcon#about to read 6, iclass 3, count 2 2006.285.06:40:10.83#ibcon#read 6, iclass 3, count 2 2006.285.06:40:10.83#ibcon#end of sib2, iclass 3, count 2 2006.285.06:40:10.83#ibcon#*mode == 0, iclass 3, count 2 2006.285.06:40:10.83#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.06:40:10.83#ibcon#[25=AT07-04\r\n] 2006.285.06:40:10.83#ibcon#*before write, iclass 3, count 2 2006.285.06:40:10.83#ibcon#enter sib2, iclass 3, count 2 2006.285.06:40:10.83#ibcon#flushed, iclass 3, count 2 2006.285.06:40:10.83#ibcon#about to write, iclass 3, count 2 2006.285.06:40:10.83#ibcon#wrote, iclass 3, count 2 2006.285.06:40:10.83#ibcon#about to read 3, iclass 3, count 2 2006.285.06:40:10.86#ibcon#read 3, iclass 3, count 2 2006.285.06:40:10.86#ibcon#about to read 4, iclass 3, count 2 2006.285.06:40:10.86#ibcon#read 4, iclass 3, count 2 2006.285.06:40:10.86#ibcon#about to read 5, iclass 3, count 2 2006.285.06:40:10.86#ibcon#read 5, iclass 3, count 2 2006.285.06:40:10.86#ibcon#about to read 6, iclass 3, count 2 2006.285.06:40:10.86#ibcon#read 6, iclass 3, count 2 2006.285.06:40:10.86#ibcon#end of sib2, iclass 3, count 2 2006.285.06:40:10.86#ibcon#*after write, iclass 3, count 2 2006.285.06:40:10.86#ibcon#*before return 0, iclass 3, count 2 2006.285.06:40:10.86#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:40:10.86#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:40:10.86#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.06:40:10.86#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:10.86#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:40:10.98#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:40:10.98#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:40:10.98#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:40:10.98#ibcon#first serial, iclass 3, count 0 2006.285.06:40:10.98#ibcon#enter sib2, iclass 3, count 0 2006.285.06:40:10.98#ibcon#flushed, iclass 3, count 0 2006.285.06:40:10.98#ibcon#about to write, iclass 3, count 0 2006.285.06:40:10.98#ibcon#wrote, iclass 3, count 0 2006.285.06:40:10.98#ibcon#about to read 3, iclass 3, count 0 2006.285.06:40:11.00#ibcon#read 3, iclass 3, count 0 2006.285.06:40:11.00#ibcon#about to read 4, iclass 3, count 0 2006.285.06:40:11.00#ibcon#read 4, iclass 3, count 0 2006.285.06:40:11.00#ibcon#about to read 5, iclass 3, count 0 2006.285.06:40:11.00#ibcon#read 5, iclass 3, count 0 2006.285.06:40:11.00#ibcon#about to read 6, iclass 3, count 0 2006.285.06:40:11.00#ibcon#read 6, iclass 3, count 0 2006.285.06:40:11.00#ibcon#end of sib2, iclass 3, count 0 2006.285.06:40:11.00#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:40:11.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:40:11.00#ibcon#[25=USB\r\n] 2006.285.06:40:11.00#ibcon#*before write, iclass 3, count 0 2006.285.06:40:11.00#ibcon#enter sib2, iclass 3, count 0 2006.285.06:40:11.00#ibcon#flushed, iclass 3, count 0 2006.285.06:40:11.00#ibcon#about to write, iclass 3, count 0 2006.285.06:40:11.00#ibcon#wrote, iclass 3, count 0 2006.285.06:40:11.00#ibcon#about to read 3, iclass 3, count 0 2006.285.06:40:11.03#ibcon#read 3, iclass 3, count 0 2006.285.06:40:11.03#ibcon#about to read 4, iclass 3, count 0 2006.285.06:40:11.03#ibcon#read 4, iclass 3, count 0 2006.285.06:40:11.03#ibcon#about to read 5, iclass 3, count 0 2006.285.06:40:11.03#ibcon#read 5, iclass 3, count 0 2006.285.06:40:11.03#ibcon#about to read 6, iclass 3, count 0 2006.285.06:40:11.03#ibcon#read 6, iclass 3, count 0 2006.285.06:40:11.03#ibcon#end of sib2, iclass 3, count 0 2006.285.06:40:11.03#ibcon#*after write, iclass 3, count 0 2006.285.06:40:11.03#ibcon#*before return 0, iclass 3, count 0 2006.285.06:40:11.03#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:40:11.03#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:40:11.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:40:11.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:40:11.03$vck44/valo=8,884.99 2006.285.06:40:11.03#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.06:40:11.03#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.06:40:11.03#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:11.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:40:11.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:40:11.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:40:11.03#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:40:11.03#ibcon#first serial, iclass 5, count 0 2006.285.06:40:11.03#ibcon#enter sib2, iclass 5, count 0 2006.285.06:40:11.03#ibcon#flushed, iclass 5, count 0 2006.285.06:40:11.03#ibcon#about to write, iclass 5, count 0 2006.285.06:40:11.03#ibcon#wrote, iclass 5, count 0 2006.285.06:40:11.03#ibcon#about to read 3, iclass 5, count 0 2006.285.06:40:11.05#ibcon#read 3, iclass 5, count 0 2006.285.06:40:11.05#ibcon#about to read 4, iclass 5, count 0 2006.285.06:40:11.05#ibcon#read 4, iclass 5, count 0 2006.285.06:40:11.05#ibcon#about to read 5, iclass 5, count 0 2006.285.06:40:11.05#ibcon#read 5, iclass 5, count 0 2006.285.06:40:11.05#ibcon#about to read 6, iclass 5, count 0 2006.285.06:40:11.05#ibcon#read 6, iclass 5, count 0 2006.285.06:40:11.05#ibcon#end of sib2, iclass 5, count 0 2006.285.06:40:11.05#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:40:11.05#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:40:11.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:40:11.05#ibcon#*before write, iclass 5, count 0 2006.285.06:40:11.05#ibcon#enter sib2, iclass 5, count 0 2006.285.06:40:11.05#ibcon#flushed, iclass 5, count 0 2006.285.06:40:11.05#ibcon#about to write, iclass 5, count 0 2006.285.06:40:11.05#ibcon#wrote, iclass 5, count 0 2006.285.06:40:11.05#ibcon#about to read 3, iclass 5, count 0 2006.285.06:40:11.09#ibcon#read 3, iclass 5, count 0 2006.285.06:40:11.09#ibcon#about to read 4, iclass 5, count 0 2006.285.06:40:11.09#ibcon#read 4, iclass 5, count 0 2006.285.06:40:11.09#ibcon#about to read 5, iclass 5, count 0 2006.285.06:40:11.09#ibcon#read 5, iclass 5, count 0 2006.285.06:40:11.09#ibcon#about to read 6, iclass 5, count 0 2006.285.06:40:11.09#ibcon#read 6, iclass 5, count 0 2006.285.06:40:11.09#ibcon#end of sib2, iclass 5, count 0 2006.285.06:40:11.09#ibcon#*after write, iclass 5, count 0 2006.285.06:40:11.09#ibcon#*before return 0, iclass 5, count 0 2006.285.06:40:11.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:40:11.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:40:11.09#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:40:11.09#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:40:11.09$vck44/va=8,3 2006.285.06:40:11.09#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.06:40:11.09#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.06:40:11.09#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:11.09#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:40:11.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:40:11.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:40:11.15#ibcon#enter wrdev, iclass 7, count 2 2006.285.06:40:11.15#ibcon#first serial, iclass 7, count 2 2006.285.06:40:11.15#ibcon#enter sib2, iclass 7, count 2 2006.285.06:40:11.15#ibcon#flushed, iclass 7, count 2 2006.285.06:40:11.15#ibcon#about to write, iclass 7, count 2 2006.285.06:40:11.15#ibcon#wrote, iclass 7, count 2 2006.285.06:40:11.15#ibcon#about to read 3, iclass 7, count 2 2006.285.06:40:11.17#ibcon#read 3, iclass 7, count 2 2006.285.06:40:11.17#ibcon#about to read 4, iclass 7, count 2 2006.285.06:40:11.17#ibcon#read 4, iclass 7, count 2 2006.285.06:40:11.17#ibcon#about to read 5, iclass 7, count 2 2006.285.06:40:11.17#ibcon#read 5, iclass 7, count 2 2006.285.06:40:11.17#ibcon#about to read 6, iclass 7, count 2 2006.285.06:40:11.17#ibcon#read 6, iclass 7, count 2 2006.285.06:40:11.17#ibcon#end of sib2, iclass 7, count 2 2006.285.06:40:11.17#ibcon#*mode == 0, iclass 7, count 2 2006.285.06:40:11.17#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.06:40:11.17#ibcon#[25=AT08-03\r\n] 2006.285.06:40:11.17#ibcon#*before write, iclass 7, count 2 2006.285.06:40:11.17#ibcon#enter sib2, iclass 7, count 2 2006.285.06:40:11.17#ibcon#flushed, iclass 7, count 2 2006.285.06:40:11.17#ibcon#about to write, iclass 7, count 2 2006.285.06:40:11.17#ibcon#wrote, iclass 7, count 2 2006.285.06:40:11.17#ibcon#about to read 3, iclass 7, count 2 2006.285.06:40:11.20#ibcon#read 3, iclass 7, count 2 2006.285.06:40:11.20#ibcon#about to read 4, iclass 7, count 2 2006.285.06:40:11.20#ibcon#read 4, iclass 7, count 2 2006.285.06:40:11.20#ibcon#about to read 5, iclass 7, count 2 2006.285.06:40:11.20#ibcon#read 5, iclass 7, count 2 2006.285.06:40:11.20#ibcon#about to read 6, iclass 7, count 2 2006.285.06:40:11.20#ibcon#read 6, iclass 7, count 2 2006.285.06:40:11.20#ibcon#end of sib2, iclass 7, count 2 2006.285.06:40:11.20#ibcon#*after write, iclass 7, count 2 2006.285.06:40:11.20#ibcon#*before return 0, iclass 7, count 2 2006.285.06:40:11.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:40:11.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.06:40:11.20#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.06:40:11.20#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:11.20#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:40:11.32#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:40:11.32#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:40:11.32#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:40:11.32#ibcon#first serial, iclass 7, count 0 2006.285.06:40:11.32#ibcon#enter sib2, iclass 7, count 0 2006.285.06:40:11.32#ibcon#flushed, iclass 7, count 0 2006.285.06:40:11.32#ibcon#about to write, iclass 7, count 0 2006.285.06:40:11.32#ibcon#wrote, iclass 7, count 0 2006.285.06:40:11.32#ibcon#about to read 3, iclass 7, count 0 2006.285.06:40:11.34#ibcon#read 3, iclass 7, count 0 2006.285.06:40:11.34#ibcon#about to read 4, iclass 7, count 0 2006.285.06:40:11.34#ibcon#read 4, iclass 7, count 0 2006.285.06:40:11.34#ibcon#about to read 5, iclass 7, count 0 2006.285.06:40:11.34#ibcon#read 5, iclass 7, count 0 2006.285.06:40:11.34#ibcon#about to read 6, iclass 7, count 0 2006.285.06:40:11.34#ibcon#read 6, iclass 7, count 0 2006.285.06:40:11.34#ibcon#end of sib2, iclass 7, count 0 2006.285.06:40:11.34#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:40:11.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:40:11.34#ibcon#[25=USB\r\n] 2006.285.06:40:11.34#ibcon#*before write, iclass 7, count 0 2006.285.06:40:11.34#ibcon#enter sib2, iclass 7, count 0 2006.285.06:40:11.34#ibcon#flushed, iclass 7, count 0 2006.285.06:40:11.34#ibcon#about to write, iclass 7, count 0 2006.285.06:40:11.34#ibcon#wrote, iclass 7, count 0 2006.285.06:40:11.34#ibcon#about to read 3, iclass 7, count 0 2006.285.06:40:11.37#ibcon#read 3, iclass 7, count 0 2006.285.06:40:11.37#ibcon#about to read 4, iclass 7, count 0 2006.285.06:40:11.37#ibcon#read 4, iclass 7, count 0 2006.285.06:40:11.37#ibcon#about to read 5, iclass 7, count 0 2006.285.06:40:11.37#ibcon#read 5, iclass 7, count 0 2006.285.06:40:11.37#ibcon#about to read 6, iclass 7, count 0 2006.285.06:40:11.37#ibcon#read 6, iclass 7, count 0 2006.285.06:40:11.37#ibcon#end of sib2, iclass 7, count 0 2006.285.06:40:11.37#ibcon#*after write, iclass 7, count 0 2006.285.06:40:11.37#ibcon#*before return 0, iclass 7, count 0 2006.285.06:40:11.37#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:40:11.37#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.06:40:11.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:40:11.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:40:11.37$vck44/vblo=1,629.99 2006.285.06:40:11.37#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.06:40:11.37#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.06:40:11.37#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:11.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:40:11.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:40:11.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:40:11.37#ibcon#enter wrdev, iclass 11, count 0 2006.285.06:40:11.37#ibcon#first serial, iclass 11, count 0 2006.285.06:40:11.37#ibcon#enter sib2, iclass 11, count 0 2006.285.06:40:11.37#ibcon#flushed, iclass 11, count 0 2006.285.06:40:11.37#ibcon#about to write, iclass 11, count 0 2006.285.06:40:11.37#ibcon#wrote, iclass 11, count 0 2006.285.06:40:11.37#ibcon#about to read 3, iclass 11, count 0 2006.285.06:40:11.39#ibcon#read 3, iclass 11, count 0 2006.285.06:40:11.39#ibcon#about to read 4, iclass 11, count 0 2006.285.06:40:11.39#ibcon#read 4, iclass 11, count 0 2006.285.06:40:11.39#ibcon#about to read 5, iclass 11, count 0 2006.285.06:40:11.39#ibcon#read 5, iclass 11, count 0 2006.285.06:40:11.39#ibcon#about to read 6, iclass 11, count 0 2006.285.06:40:11.39#ibcon#read 6, iclass 11, count 0 2006.285.06:40:11.39#ibcon#end of sib2, iclass 11, count 0 2006.285.06:40:11.39#ibcon#*mode == 0, iclass 11, count 0 2006.285.06:40:11.39#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.06:40:11.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:40:11.39#ibcon#*before write, iclass 11, count 0 2006.285.06:40:11.39#ibcon#enter sib2, iclass 11, count 0 2006.285.06:40:11.39#ibcon#flushed, iclass 11, count 0 2006.285.06:40:11.39#ibcon#about to write, iclass 11, count 0 2006.285.06:40:11.39#ibcon#wrote, iclass 11, count 0 2006.285.06:40:11.39#ibcon#about to read 3, iclass 11, count 0 2006.285.06:40:11.43#ibcon#read 3, iclass 11, count 0 2006.285.06:40:11.43#ibcon#about to read 4, iclass 11, count 0 2006.285.06:40:11.43#ibcon#read 4, iclass 11, count 0 2006.285.06:40:11.43#ibcon#about to read 5, iclass 11, count 0 2006.285.06:40:11.43#ibcon#read 5, iclass 11, count 0 2006.285.06:40:11.43#ibcon#about to read 6, iclass 11, count 0 2006.285.06:40:11.43#ibcon#read 6, iclass 11, count 0 2006.285.06:40:11.43#ibcon#end of sib2, iclass 11, count 0 2006.285.06:40:11.43#ibcon#*after write, iclass 11, count 0 2006.285.06:40:11.43#ibcon#*before return 0, iclass 11, count 0 2006.285.06:40:11.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:40:11.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.06:40:11.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.06:40:11.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.06:40:11.43$vck44/vb=1,4 2006.285.06:40:11.43#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.06:40:11.43#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.06:40:11.43#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:11.43#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:40:11.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:40:11.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:40:11.43#ibcon#enter wrdev, iclass 13, count 2 2006.285.06:40:11.43#ibcon#first serial, iclass 13, count 2 2006.285.06:40:11.43#ibcon#enter sib2, iclass 13, count 2 2006.285.06:40:11.43#ibcon#flushed, iclass 13, count 2 2006.285.06:40:11.43#ibcon#about to write, iclass 13, count 2 2006.285.06:40:11.43#ibcon#wrote, iclass 13, count 2 2006.285.06:40:11.43#ibcon#about to read 3, iclass 13, count 2 2006.285.06:40:11.45#ibcon#read 3, iclass 13, count 2 2006.285.06:40:11.45#ibcon#about to read 4, iclass 13, count 2 2006.285.06:40:11.45#ibcon#read 4, iclass 13, count 2 2006.285.06:40:11.45#ibcon#about to read 5, iclass 13, count 2 2006.285.06:40:11.45#ibcon#read 5, iclass 13, count 2 2006.285.06:40:11.45#ibcon#about to read 6, iclass 13, count 2 2006.285.06:40:11.45#ibcon#read 6, iclass 13, count 2 2006.285.06:40:11.45#ibcon#end of sib2, iclass 13, count 2 2006.285.06:40:11.45#ibcon#*mode == 0, iclass 13, count 2 2006.285.06:40:11.45#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.06:40:11.45#ibcon#[27=AT01-04\r\n] 2006.285.06:40:11.45#ibcon#*before write, iclass 13, count 2 2006.285.06:40:11.45#ibcon#enter sib2, iclass 13, count 2 2006.285.06:40:11.45#ibcon#flushed, iclass 13, count 2 2006.285.06:40:11.45#ibcon#about to write, iclass 13, count 2 2006.285.06:40:11.45#ibcon#wrote, iclass 13, count 2 2006.285.06:40:11.45#ibcon#about to read 3, iclass 13, count 2 2006.285.06:40:11.48#ibcon#read 3, iclass 13, count 2 2006.285.06:40:11.48#ibcon#about to read 4, iclass 13, count 2 2006.285.06:40:11.48#ibcon#read 4, iclass 13, count 2 2006.285.06:40:11.48#ibcon#about to read 5, iclass 13, count 2 2006.285.06:40:11.48#ibcon#read 5, iclass 13, count 2 2006.285.06:40:11.48#ibcon#about to read 6, iclass 13, count 2 2006.285.06:40:11.48#ibcon#read 6, iclass 13, count 2 2006.285.06:40:11.48#ibcon#end of sib2, iclass 13, count 2 2006.285.06:40:11.48#ibcon#*after write, iclass 13, count 2 2006.285.06:40:11.48#ibcon#*before return 0, iclass 13, count 2 2006.285.06:40:11.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:40:11.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.06:40:11.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.06:40:11.48#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:11.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:40:11.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:40:11.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:40:11.60#ibcon#enter wrdev, iclass 13, count 0 2006.285.06:40:11.60#ibcon#first serial, iclass 13, count 0 2006.285.06:40:11.60#ibcon#enter sib2, iclass 13, count 0 2006.285.06:40:11.60#ibcon#flushed, iclass 13, count 0 2006.285.06:40:11.60#ibcon#about to write, iclass 13, count 0 2006.285.06:40:11.60#ibcon#wrote, iclass 13, count 0 2006.285.06:40:11.60#ibcon#about to read 3, iclass 13, count 0 2006.285.06:40:11.62#ibcon#read 3, iclass 13, count 0 2006.285.06:40:11.62#ibcon#about to read 4, iclass 13, count 0 2006.285.06:40:11.62#ibcon#read 4, iclass 13, count 0 2006.285.06:40:11.62#ibcon#about to read 5, iclass 13, count 0 2006.285.06:40:11.62#ibcon#read 5, iclass 13, count 0 2006.285.06:40:11.62#ibcon#about to read 6, iclass 13, count 0 2006.285.06:40:11.62#ibcon#read 6, iclass 13, count 0 2006.285.06:40:11.62#ibcon#end of sib2, iclass 13, count 0 2006.285.06:40:11.62#ibcon#*mode == 0, iclass 13, count 0 2006.285.06:40:11.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.06:40:11.62#ibcon#[27=USB\r\n] 2006.285.06:40:11.62#ibcon#*before write, iclass 13, count 0 2006.285.06:40:11.62#ibcon#enter sib2, iclass 13, count 0 2006.285.06:40:11.62#ibcon#flushed, iclass 13, count 0 2006.285.06:40:11.62#ibcon#about to write, iclass 13, count 0 2006.285.06:40:11.62#ibcon#wrote, iclass 13, count 0 2006.285.06:40:11.62#ibcon#about to read 3, iclass 13, count 0 2006.285.06:40:11.65#ibcon#read 3, iclass 13, count 0 2006.285.06:40:11.65#ibcon#about to read 4, iclass 13, count 0 2006.285.06:40:11.65#ibcon#read 4, iclass 13, count 0 2006.285.06:40:11.65#ibcon#about to read 5, iclass 13, count 0 2006.285.06:40:11.65#ibcon#read 5, iclass 13, count 0 2006.285.06:40:11.65#ibcon#about to read 6, iclass 13, count 0 2006.285.06:40:11.65#ibcon#read 6, iclass 13, count 0 2006.285.06:40:11.65#ibcon#end of sib2, iclass 13, count 0 2006.285.06:40:11.65#ibcon#*after write, iclass 13, count 0 2006.285.06:40:11.65#ibcon#*before return 0, iclass 13, count 0 2006.285.06:40:11.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:40:11.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.06:40:11.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.06:40:11.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.06:40:11.65$vck44/vblo=2,634.99 2006.285.06:40:11.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.06:40:11.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.06:40:11.65#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:11.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:40:11.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:40:11.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:40:11.65#ibcon#enter wrdev, iclass 15, count 0 2006.285.06:40:11.65#ibcon#first serial, iclass 15, count 0 2006.285.06:40:11.65#ibcon#enter sib2, iclass 15, count 0 2006.285.06:40:11.65#ibcon#flushed, iclass 15, count 0 2006.285.06:40:11.65#ibcon#about to write, iclass 15, count 0 2006.285.06:40:11.65#ibcon#wrote, iclass 15, count 0 2006.285.06:40:11.65#ibcon#about to read 3, iclass 15, count 0 2006.285.06:40:11.67#ibcon#read 3, iclass 15, count 0 2006.285.06:40:11.67#ibcon#about to read 4, iclass 15, count 0 2006.285.06:40:11.67#ibcon#read 4, iclass 15, count 0 2006.285.06:40:11.67#ibcon#about to read 5, iclass 15, count 0 2006.285.06:40:11.67#ibcon#read 5, iclass 15, count 0 2006.285.06:40:11.67#ibcon#about to read 6, iclass 15, count 0 2006.285.06:40:11.67#ibcon#read 6, iclass 15, count 0 2006.285.06:40:11.67#ibcon#end of sib2, iclass 15, count 0 2006.285.06:40:11.67#ibcon#*mode == 0, iclass 15, count 0 2006.285.06:40:11.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.06:40:11.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:40:11.67#ibcon#*before write, iclass 15, count 0 2006.285.06:40:11.67#ibcon#enter sib2, iclass 15, count 0 2006.285.06:40:11.67#ibcon#flushed, iclass 15, count 0 2006.285.06:40:11.67#ibcon#about to write, iclass 15, count 0 2006.285.06:40:11.67#ibcon#wrote, iclass 15, count 0 2006.285.06:40:11.67#ibcon#about to read 3, iclass 15, count 0 2006.285.06:40:11.71#ibcon#read 3, iclass 15, count 0 2006.285.06:40:11.71#ibcon#about to read 4, iclass 15, count 0 2006.285.06:40:11.71#ibcon#read 4, iclass 15, count 0 2006.285.06:40:11.71#ibcon#about to read 5, iclass 15, count 0 2006.285.06:40:11.71#ibcon#read 5, iclass 15, count 0 2006.285.06:40:11.71#ibcon#about to read 6, iclass 15, count 0 2006.285.06:40:11.71#ibcon#read 6, iclass 15, count 0 2006.285.06:40:11.71#ibcon#end of sib2, iclass 15, count 0 2006.285.06:40:11.71#ibcon#*after write, iclass 15, count 0 2006.285.06:40:11.71#ibcon#*before return 0, iclass 15, count 0 2006.285.06:40:11.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:40:11.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.06:40:11.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.06:40:11.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.06:40:11.71$vck44/vb=2,5 2006.285.06:40:11.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.06:40:11.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.06:40:11.71#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:11.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:40:11.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:40:11.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:40:11.77#ibcon#enter wrdev, iclass 17, count 2 2006.285.06:40:11.77#ibcon#first serial, iclass 17, count 2 2006.285.06:40:11.77#ibcon#enter sib2, iclass 17, count 2 2006.285.06:40:11.77#ibcon#flushed, iclass 17, count 2 2006.285.06:40:11.77#ibcon#about to write, iclass 17, count 2 2006.285.06:40:11.77#ibcon#wrote, iclass 17, count 2 2006.285.06:40:11.77#ibcon#about to read 3, iclass 17, count 2 2006.285.06:40:11.79#ibcon#read 3, iclass 17, count 2 2006.285.06:40:11.79#ibcon#about to read 4, iclass 17, count 2 2006.285.06:40:11.79#ibcon#read 4, iclass 17, count 2 2006.285.06:40:11.79#ibcon#about to read 5, iclass 17, count 2 2006.285.06:40:11.79#ibcon#read 5, iclass 17, count 2 2006.285.06:40:11.79#ibcon#about to read 6, iclass 17, count 2 2006.285.06:40:11.79#ibcon#read 6, iclass 17, count 2 2006.285.06:40:11.79#ibcon#end of sib2, iclass 17, count 2 2006.285.06:40:11.79#ibcon#*mode == 0, iclass 17, count 2 2006.285.06:40:11.79#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.06:40:11.79#ibcon#[27=AT02-05\r\n] 2006.285.06:40:11.79#ibcon#*before write, iclass 17, count 2 2006.285.06:40:11.79#ibcon#enter sib2, iclass 17, count 2 2006.285.06:40:11.79#ibcon#flushed, iclass 17, count 2 2006.285.06:40:11.79#ibcon#about to write, iclass 17, count 2 2006.285.06:40:11.79#ibcon#wrote, iclass 17, count 2 2006.285.06:40:11.79#ibcon#about to read 3, iclass 17, count 2 2006.285.06:40:11.82#ibcon#read 3, iclass 17, count 2 2006.285.06:40:11.82#ibcon#about to read 4, iclass 17, count 2 2006.285.06:40:11.82#ibcon#read 4, iclass 17, count 2 2006.285.06:40:11.82#ibcon#about to read 5, iclass 17, count 2 2006.285.06:40:11.82#ibcon#read 5, iclass 17, count 2 2006.285.06:40:11.82#ibcon#about to read 6, iclass 17, count 2 2006.285.06:40:11.82#ibcon#read 6, iclass 17, count 2 2006.285.06:40:11.82#ibcon#end of sib2, iclass 17, count 2 2006.285.06:40:11.82#ibcon#*after write, iclass 17, count 2 2006.285.06:40:11.82#ibcon#*before return 0, iclass 17, count 2 2006.285.06:40:11.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:40:11.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.06:40:11.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.06:40:11.82#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:11.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:40:11.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:40:11.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:40:11.94#ibcon#enter wrdev, iclass 17, count 0 2006.285.06:40:11.94#ibcon#first serial, iclass 17, count 0 2006.285.06:40:11.94#ibcon#enter sib2, iclass 17, count 0 2006.285.06:40:11.94#ibcon#flushed, iclass 17, count 0 2006.285.06:40:11.94#ibcon#about to write, iclass 17, count 0 2006.285.06:40:11.94#ibcon#wrote, iclass 17, count 0 2006.285.06:40:11.94#ibcon#about to read 3, iclass 17, count 0 2006.285.06:40:11.96#ibcon#read 3, iclass 17, count 0 2006.285.06:40:11.96#ibcon#about to read 4, iclass 17, count 0 2006.285.06:40:11.96#ibcon#read 4, iclass 17, count 0 2006.285.06:40:11.96#ibcon#about to read 5, iclass 17, count 0 2006.285.06:40:11.96#ibcon#read 5, iclass 17, count 0 2006.285.06:40:11.96#ibcon#about to read 6, iclass 17, count 0 2006.285.06:40:11.96#ibcon#read 6, iclass 17, count 0 2006.285.06:40:11.96#ibcon#end of sib2, iclass 17, count 0 2006.285.06:40:11.96#ibcon#*mode == 0, iclass 17, count 0 2006.285.06:40:11.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.06:40:11.96#ibcon#[27=USB\r\n] 2006.285.06:40:11.96#ibcon#*before write, iclass 17, count 0 2006.285.06:40:11.96#ibcon#enter sib2, iclass 17, count 0 2006.285.06:40:11.96#ibcon#flushed, iclass 17, count 0 2006.285.06:40:11.96#ibcon#about to write, iclass 17, count 0 2006.285.06:40:11.96#ibcon#wrote, iclass 17, count 0 2006.285.06:40:11.96#ibcon#about to read 3, iclass 17, count 0 2006.285.06:40:11.99#ibcon#read 3, iclass 17, count 0 2006.285.06:40:11.99#ibcon#about to read 4, iclass 17, count 0 2006.285.06:40:11.99#ibcon#read 4, iclass 17, count 0 2006.285.06:40:11.99#ibcon#about to read 5, iclass 17, count 0 2006.285.06:40:11.99#ibcon#read 5, iclass 17, count 0 2006.285.06:40:11.99#ibcon#about to read 6, iclass 17, count 0 2006.285.06:40:11.99#ibcon#read 6, iclass 17, count 0 2006.285.06:40:11.99#ibcon#end of sib2, iclass 17, count 0 2006.285.06:40:11.99#ibcon#*after write, iclass 17, count 0 2006.285.06:40:11.99#ibcon#*before return 0, iclass 17, count 0 2006.285.06:40:11.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:40:11.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.06:40:11.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.06:40:11.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.06:40:11.99$vck44/vblo=3,649.99 2006.285.06:40:11.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.06:40:11.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.06:40:11.99#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:11.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:40:11.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:40:11.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:40:11.99#ibcon#enter wrdev, iclass 19, count 0 2006.285.06:40:11.99#ibcon#first serial, iclass 19, count 0 2006.285.06:40:11.99#ibcon#enter sib2, iclass 19, count 0 2006.285.06:40:11.99#ibcon#flushed, iclass 19, count 0 2006.285.06:40:11.99#ibcon#about to write, iclass 19, count 0 2006.285.06:40:11.99#ibcon#wrote, iclass 19, count 0 2006.285.06:40:11.99#ibcon#about to read 3, iclass 19, count 0 2006.285.06:40:12.01#ibcon#read 3, iclass 19, count 0 2006.285.06:40:12.01#ibcon#about to read 4, iclass 19, count 0 2006.285.06:40:12.01#ibcon#read 4, iclass 19, count 0 2006.285.06:40:12.01#ibcon#about to read 5, iclass 19, count 0 2006.285.06:40:12.01#ibcon#read 5, iclass 19, count 0 2006.285.06:40:12.01#ibcon#about to read 6, iclass 19, count 0 2006.285.06:40:12.01#ibcon#read 6, iclass 19, count 0 2006.285.06:40:12.01#ibcon#end of sib2, iclass 19, count 0 2006.285.06:40:12.01#ibcon#*mode == 0, iclass 19, count 0 2006.285.06:40:12.01#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.06:40:12.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:40:12.01#ibcon#*before write, iclass 19, count 0 2006.285.06:40:12.01#ibcon#enter sib2, iclass 19, count 0 2006.285.06:40:12.01#ibcon#flushed, iclass 19, count 0 2006.285.06:40:12.01#ibcon#about to write, iclass 19, count 0 2006.285.06:40:12.01#ibcon#wrote, iclass 19, count 0 2006.285.06:40:12.01#ibcon#about to read 3, iclass 19, count 0 2006.285.06:40:12.05#ibcon#read 3, iclass 19, count 0 2006.285.06:40:12.05#ibcon#about to read 4, iclass 19, count 0 2006.285.06:40:12.05#ibcon#read 4, iclass 19, count 0 2006.285.06:40:12.05#ibcon#about to read 5, iclass 19, count 0 2006.285.06:40:12.05#ibcon#read 5, iclass 19, count 0 2006.285.06:40:12.05#ibcon#about to read 6, iclass 19, count 0 2006.285.06:40:12.05#ibcon#read 6, iclass 19, count 0 2006.285.06:40:12.05#ibcon#end of sib2, iclass 19, count 0 2006.285.06:40:12.05#ibcon#*after write, iclass 19, count 0 2006.285.06:40:12.05#ibcon#*before return 0, iclass 19, count 0 2006.285.06:40:12.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:40:12.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.06:40:12.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.06:40:12.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.06:40:12.05$vck44/vb=3,4 2006.285.06:40:12.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.06:40:12.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.06:40:12.05#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:12.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:40:12.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:40:12.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:40:12.11#ibcon#enter wrdev, iclass 21, count 2 2006.285.06:40:12.11#ibcon#first serial, iclass 21, count 2 2006.285.06:40:12.11#ibcon#enter sib2, iclass 21, count 2 2006.285.06:40:12.11#ibcon#flushed, iclass 21, count 2 2006.285.06:40:12.11#ibcon#about to write, iclass 21, count 2 2006.285.06:40:12.11#ibcon#wrote, iclass 21, count 2 2006.285.06:40:12.11#ibcon#about to read 3, iclass 21, count 2 2006.285.06:40:12.13#ibcon#read 3, iclass 21, count 2 2006.285.06:40:12.13#ibcon#about to read 4, iclass 21, count 2 2006.285.06:40:12.13#ibcon#read 4, iclass 21, count 2 2006.285.06:40:12.13#ibcon#about to read 5, iclass 21, count 2 2006.285.06:40:12.13#ibcon#read 5, iclass 21, count 2 2006.285.06:40:12.13#ibcon#about to read 6, iclass 21, count 2 2006.285.06:40:12.13#ibcon#read 6, iclass 21, count 2 2006.285.06:40:12.13#ibcon#end of sib2, iclass 21, count 2 2006.285.06:40:12.13#ibcon#*mode == 0, iclass 21, count 2 2006.285.06:40:12.13#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.06:40:12.13#ibcon#[27=AT03-04\r\n] 2006.285.06:40:12.13#ibcon#*before write, iclass 21, count 2 2006.285.06:40:12.13#ibcon#enter sib2, iclass 21, count 2 2006.285.06:40:12.13#ibcon#flushed, iclass 21, count 2 2006.285.06:40:12.13#ibcon#about to write, iclass 21, count 2 2006.285.06:40:12.13#ibcon#wrote, iclass 21, count 2 2006.285.06:40:12.13#ibcon#about to read 3, iclass 21, count 2 2006.285.06:40:12.16#ibcon#read 3, iclass 21, count 2 2006.285.06:40:12.16#ibcon#about to read 4, iclass 21, count 2 2006.285.06:40:12.16#ibcon#read 4, iclass 21, count 2 2006.285.06:40:12.16#ibcon#about to read 5, iclass 21, count 2 2006.285.06:40:12.16#ibcon#read 5, iclass 21, count 2 2006.285.06:40:12.16#ibcon#about to read 6, iclass 21, count 2 2006.285.06:40:12.16#ibcon#read 6, iclass 21, count 2 2006.285.06:40:12.16#ibcon#end of sib2, iclass 21, count 2 2006.285.06:40:12.16#ibcon#*after write, iclass 21, count 2 2006.285.06:40:12.16#ibcon#*before return 0, iclass 21, count 2 2006.285.06:40:12.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:40:12.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:40:12.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.06:40:12.16#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:12.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:40:12.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:40:12.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:40:12.28#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:40:12.28#ibcon#first serial, iclass 21, count 0 2006.285.06:40:12.28#ibcon#enter sib2, iclass 21, count 0 2006.285.06:40:12.28#ibcon#flushed, iclass 21, count 0 2006.285.06:40:12.28#ibcon#about to write, iclass 21, count 0 2006.285.06:40:12.28#ibcon#wrote, iclass 21, count 0 2006.285.06:40:12.28#ibcon#about to read 3, iclass 21, count 0 2006.285.06:40:12.30#ibcon#read 3, iclass 21, count 0 2006.285.06:40:12.30#ibcon#about to read 4, iclass 21, count 0 2006.285.06:40:12.30#ibcon#read 4, iclass 21, count 0 2006.285.06:40:12.30#ibcon#about to read 5, iclass 21, count 0 2006.285.06:40:12.30#ibcon#read 5, iclass 21, count 0 2006.285.06:40:12.30#ibcon#about to read 6, iclass 21, count 0 2006.285.06:40:12.30#ibcon#read 6, iclass 21, count 0 2006.285.06:40:12.30#ibcon#end of sib2, iclass 21, count 0 2006.285.06:40:12.30#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:40:12.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:40:12.30#ibcon#[27=USB\r\n] 2006.285.06:40:12.30#ibcon#*before write, iclass 21, count 0 2006.285.06:40:12.30#ibcon#enter sib2, iclass 21, count 0 2006.285.06:40:12.30#ibcon#flushed, iclass 21, count 0 2006.285.06:40:12.30#ibcon#about to write, iclass 21, count 0 2006.285.06:40:12.30#ibcon#wrote, iclass 21, count 0 2006.285.06:40:12.30#ibcon#about to read 3, iclass 21, count 0 2006.285.06:40:12.33#ibcon#read 3, iclass 21, count 0 2006.285.06:40:12.33#ibcon#about to read 4, iclass 21, count 0 2006.285.06:40:12.33#ibcon#read 4, iclass 21, count 0 2006.285.06:40:12.33#ibcon#about to read 5, iclass 21, count 0 2006.285.06:40:12.33#ibcon#read 5, iclass 21, count 0 2006.285.06:40:12.33#ibcon#about to read 6, iclass 21, count 0 2006.285.06:40:12.33#ibcon#read 6, iclass 21, count 0 2006.285.06:40:12.33#ibcon#end of sib2, iclass 21, count 0 2006.285.06:40:12.33#ibcon#*after write, iclass 21, count 0 2006.285.06:40:12.33#ibcon#*before return 0, iclass 21, count 0 2006.285.06:40:12.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:40:12.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:40:12.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:40:12.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:40:12.33$vck44/vblo=4,679.99 2006.285.06:40:12.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.06:40:12.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.06:40:12.33#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:12.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:40:12.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:40:12.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:40:12.33#ibcon#enter wrdev, iclass 23, count 0 2006.285.06:40:12.33#ibcon#first serial, iclass 23, count 0 2006.285.06:40:12.33#ibcon#enter sib2, iclass 23, count 0 2006.285.06:40:12.33#ibcon#flushed, iclass 23, count 0 2006.285.06:40:12.33#ibcon#about to write, iclass 23, count 0 2006.285.06:40:12.33#ibcon#wrote, iclass 23, count 0 2006.285.06:40:12.33#ibcon#about to read 3, iclass 23, count 0 2006.285.06:40:12.35#ibcon#read 3, iclass 23, count 0 2006.285.06:40:12.35#ibcon#about to read 4, iclass 23, count 0 2006.285.06:40:12.35#ibcon#read 4, iclass 23, count 0 2006.285.06:40:12.35#ibcon#about to read 5, iclass 23, count 0 2006.285.06:40:12.35#ibcon#read 5, iclass 23, count 0 2006.285.06:40:12.35#ibcon#about to read 6, iclass 23, count 0 2006.285.06:40:12.35#ibcon#read 6, iclass 23, count 0 2006.285.06:40:12.35#ibcon#end of sib2, iclass 23, count 0 2006.285.06:40:12.35#ibcon#*mode == 0, iclass 23, count 0 2006.285.06:40:12.35#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.06:40:12.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:40:12.35#ibcon#*before write, iclass 23, count 0 2006.285.06:40:12.35#ibcon#enter sib2, iclass 23, count 0 2006.285.06:40:12.35#ibcon#flushed, iclass 23, count 0 2006.285.06:40:12.35#ibcon#about to write, iclass 23, count 0 2006.285.06:40:12.35#ibcon#wrote, iclass 23, count 0 2006.285.06:40:12.35#ibcon#about to read 3, iclass 23, count 0 2006.285.06:40:12.39#ibcon#read 3, iclass 23, count 0 2006.285.06:40:12.39#ibcon#about to read 4, iclass 23, count 0 2006.285.06:40:12.39#ibcon#read 4, iclass 23, count 0 2006.285.06:40:12.39#ibcon#about to read 5, iclass 23, count 0 2006.285.06:40:12.39#ibcon#read 5, iclass 23, count 0 2006.285.06:40:12.39#ibcon#about to read 6, iclass 23, count 0 2006.285.06:40:12.39#ibcon#read 6, iclass 23, count 0 2006.285.06:40:12.39#ibcon#end of sib2, iclass 23, count 0 2006.285.06:40:12.39#ibcon#*after write, iclass 23, count 0 2006.285.06:40:12.39#ibcon#*before return 0, iclass 23, count 0 2006.285.06:40:12.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:40:12.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.06:40:12.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.06:40:12.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.06:40:12.39$vck44/vb=4,5 2006.285.06:40:12.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.06:40:12.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.06:40:12.39#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:12.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:40:12.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:40:12.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:40:12.45#ibcon#enter wrdev, iclass 25, count 2 2006.285.06:40:12.45#ibcon#first serial, iclass 25, count 2 2006.285.06:40:12.45#ibcon#enter sib2, iclass 25, count 2 2006.285.06:40:12.45#ibcon#flushed, iclass 25, count 2 2006.285.06:40:12.45#ibcon#about to write, iclass 25, count 2 2006.285.06:40:12.45#ibcon#wrote, iclass 25, count 2 2006.285.06:40:12.45#ibcon#about to read 3, iclass 25, count 2 2006.285.06:40:12.47#ibcon#read 3, iclass 25, count 2 2006.285.06:40:12.47#ibcon#about to read 4, iclass 25, count 2 2006.285.06:40:12.47#ibcon#read 4, iclass 25, count 2 2006.285.06:40:12.47#ibcon#about to read 5, iclass 25, count 2 2006.285.06:40:12.47#ibcon#read 5, iclass 25, count 2 2006.285.06:40:12.47#ibcon#about to read 6, iclass 25, count 2 2006.285.06:40:12.47#ibcon#read 6, iclass 25, count 2 2006.285.06:40:12.47#ibcon#end of sib2, iclass 25, count 2 2006.285.06:40:12.47#ibcon#*mode == 0, iclass 25, count 2 2006.285.06:40:12.47#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.06:40:12.47#ibcon#[27=AT04-05\r\n] 2006.285.06:40:12.47#ibcon#*before write, iclass 25, count 2 2006.285.06:40:12.47#ibcon#enter sib2, iclass 25, count 2 2006.285.06:40:12.47#ibcon#flushed, iclass 25, count 2 2006.285.06:40:12.47#ibcon#about to write, iclass 25, count 2 2006.285.06:40:12.47#ibcon#wrote, iclass 25, count 2 2006.285.06:40:12.47#ibcon#about to read 3, iclass 25, count 2 2006.285.06:40:12.50#ibcon#read 3, iclass 25, count 2 2006.285.06:40:12.50#ibcon#about to read 4, iclass 25, count 2 2006.285.06:40:12.50#ibcon#read 4, iclass 25, count 2 2006.285.06:40:12.50#ibcon#about to read 5, iclass 25, count 2 2006.285.06:40:12.50#ibcon#read 5, iclass 25, count 2 2006.285.06:40:12.50#ibcon#about to read 6, iclass 25, count 2 2006.285.06:40:12.50#ibcon#read 6, iclass 25, count 2 2006.285.06:40:12.50#ibcon#end of sib2, iclass 25, count 2 2006.285.06:40:12.50#ibcon#*after write, iclass 25, count 2 2006.285.06:40:12.50#ibcon#*before return 0, iclass 25, count 2 2006.285.06:40:12.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:40:12.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.06:40:12.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.06:40:12.50#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:12.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:40:12.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:40:12.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:40:12.62#ibcon#enter wrdev, iclass 25, count 0 2006.285.06:40:12.62#ibcon#first serial, iclass 25, count 0 2006.285.06:40:12.62#ibcon#enter sib2, iclass 25, count 0 2006.285.06:40:12.62#ibcon#flushed, iclass 25, count 0 2006.285.06:40:12.62#ibcon#about to write, iclass 25, count 0 2006.285.06:40:12.62#ibcon#wrote, iclass 25, count 0 2006.285.06:40:12.62#ibcon#about to read 3, iclass 25, count 0 2006.285.06:40:12.64#ibcon#read 3, iclass 25, count 0 2006.285.06:40:12.64#ibcon#about to read 4, iclass 25, count 0 2006.285.06:40:12.64#ibcon#read 4, iclass 25, count 0 2006.285.06:40:12.64#ibcon#about to read 5, iclass 25, count 0 2006.285.06:40:12.64#ibcon#read 5, iclass 25, count 0 2006.285.06:40:12.64#ibcon#about to read 6, iclass 25, count 0 2006.285.06:40:12.64#ibcon#read 6, iclass 25, count 0 2006.285.06:40:12.64#ibcon#end of sib2, iclass 25, count 0 2006.285.06:40:12.64#ibcon#*mode == 0, iclass 25, count 0 2006.285.06:40:12.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.06:40:12.64#ibcon#[27=USB\r\n] 2006.285.06:40:12.64#ibcon#*before write, iclass 25, count 0 2006.285.06:40:12.64#ibcon#enter sib2, iclass 25, count 0 2006.285.06:40:12.64#ibcon#flushed, iclass 25, count 0 2006.285.06:40:12.64#ibcon#about to write, iclass 25, count 0 2006.285.06:40:12.64#ibcon#wrote, iclass 25, count 0 2006.285.06:40:12.64#ibcon#about to read 3, iclass 25, count 0 2006.285.06:40:12.67#ibcon#read 3, iclass 25, count 0 2006.285.06:40:12.67#ibcon#about to read 4, iclass 25, count 0 2006.285.06:40:12.67#ibcon#read 4, iclass 25, count 0 2006.285.06:40:12.67#ibcon#about to read 5, iclass 25, count 0 2006.285.06:40:12.67#ibcon#read 5, iclass 25, count 0 2006.285.06:40:12.67#ibcon#about to read 6, iclass 25, count 0 2006.285.06:40:12.67#ibcon#read 6, iclass 25, count 0 2006.285.06:40:12.67#ibcon#end of sib2, iclass 25, count 0 2006.285.06:40:12.67#ibcon#*after write, iclass 25, count 0 2006.285.06:40:12.67#ibcon#*before return 0, iclass 25, count 0 2006.285.06:40:12.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:40:12.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.06:40:12.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.06:40:12.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.06:40:12.67$vck44/vblo=5,709.99 2006.285.06:40:12.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.06:40:12.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.06:40:12.67#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:12.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:40:12.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:40:12.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:40:12.67#ibcon#enter wrdev, iclass 27, count 0 2006.285.06:40:12.67#ibcon#first serial, iclass 27, count 0 2006.285.06:40:12.67#ibcon#enter sib2, iclass 27, count 0 2006.285.06:40:12.67#ibcon#flushed, iclass 27, count 0 2006.285.06:40:12.67#ibcon#about to write, iclass 27, count 0 2006.285.06:40:12.67#ibcon#wrote, iclass 27, count 0 2006.285.06:40:12.67#ibcon#about to read 3, iclass 27, count 0 2006.285.06:40:12.69#ibcon#read 3, iclass 27, count 0 2006.285.06:40:12.69#ibcon#about to read 4, iclass 27, count 0 2006.285.06:40:12.69#ibcon#read 4, iclass 27, count 0 2006.285.06:40:12.69#ibcon#about to read 5, iclass 27, count 0 2006.285.06:40:12.69#ibcon#read 5, iclass 27, count 0 2006.285.06:40:12.69#ibcon#about to read 6, iclass 27, count 0 2006.285.06:40:12.69#ibcon#read 6, iclass 27, count 0 2006.285.06:40:12.69#ibcon#end of sib2, iclass 27, count 0 2006.285.06:40:12.69#ibcon#*mode == 0, iclass 27, count 0 2006.285.06:40:12.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.06:40:12.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:40:12.69#ibcon#*before write, iclass 27, count 0 2006.285.06:40:12.69#ibcon#enter sib2, iclass 27, count 0 2006.285.06:40:12.69#ibcon#flushed, iclass 27, count 0 2006.285.06:40:12.69#ibcon#about to write, iclass 27, count 0 2006.285.06:40:12.69#ibcon#wrote, iclass 27, count 0 2006.285.06:40:12.69#ibcon#about to read 3, iclass 27, count 0 2006.285.06:40:12.73#ibcon#read 3, iclass 27, count 0 2006.285.06:40:12.73#ibcon#about to read 4, iclass 27, count 0 2006.285.06:40:12.73#ibcon#read 4, iclass 27, count 0 2006.285.06:40:12.73#ibcon#about to read 5, iclass 27, count 0 2006.285.06:40:12.73#ibcon#read 5, iclass 27, count 0 2006.285.06:40:12.73#ibcon#about to read 6, iclass 27, count 0 2006.285.06:40:12.73#ibcon#read 6, iclass 27, count 0 2006.285.06:40:12.73#ibcon#end of sib2, iclass 27, count 0 2006.285.06:40:12.73#ibcon#*after write, iclass 27, count 0 2006.285.06:40:12.73#ibcon#*before return 0, iclass 27, count 0 2006.285.06:40:12.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:40:12.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.06:40:12.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.06:40:12.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.06:40:12.73$vck44/vb=5,4 2006.285.06:40:12.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.06:40:12.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.06:40:12.73#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:12.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:40:12.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:40:12.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:40:12.79#ibcon#enter wrdev, iclass 29, count 2 2006.285.06:40:12.79#ibcon#first serial, iclass 29, count 2 2006.285.06:40:12.79#ibcon#enter sib2, iclass 29, count 2 2006.285.06:40:12.79#ibcon#flushed, iclass 29, count 2 2006.285.06:40:12.79#ibcon#about to write, iclass 29, count 2 2006.285.06:40:12.79#ibcon#wrote, iclass 29, count 2 2006.285.06:40:12.79#ibcon#about to read 3, iclass 29, count 2 2006.285.06:40:12.81#ibcon#read 3, iclass 29, count 2 2006.285.06:40:12.81#ibcon#about to read 4, iclass 29, count 2 2006.285.06:40:12.81#ibcon#read 4, iclass 29, count 2 2006.285.06:40:12.81#ibcon#about to read 5, iclass 29, count 2 2006.285.06:40:12.81#ibcon#read 5, iclass 29, count 2 2006.285.06:40:12.81#ibcon#about to read 6, iclass 29, count 2 2006.285.06:40:12.81#ibcon#read 6, iclass 29, count 2 2006.285.06:40:12.81#ibcon#end of sib2, iclass 29, count 2 2006.285.06:40:12.81#ibcon#*mode == 0, iclass 29, count 2 2006.285.06:40:12.81#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.06:40:12.81#ibcon#[27=AT05-04\r\n] 2006.285.06:40:12.81#ibcon#*before write, iclass 29, count 2 2006.285.06:40:12.81#ibcon#enter sib2, iclass 29, count 2 2006.285.06:40:12.81#ibcon#flushed, iclass 29, count 2 2006.285.06:40:12.81#ibcon#about to write, iclass 29, count 2 2006.285.06:40:12.81#ibcon#wrote, iclass 29, count 2 2006.285.06:40:12.81#ibcon#about to read 3, iclass 29, count 2 2006.285.06:40:12.84#ibcon#read 3, iclass 29, count 2 2006.285.06:40:12.84#ibcon#about to read 4, iclass 29, count 2 2006.285.06:40:12.84#ibcon#read 4, iclass 29, count 2 2006.285.06:40:12.84#ibcon#about to read 5, iclass 29, count 2 2006.285.06:40:12.84#ibcon#read 5, iclass 29, count 2 2006.285.06:40:12.84#ibcon#about to read 6, iclass 29, count 2 2006.285.06:40:12.84#ibcon#read 6, iclass 29, count 2 2006.285.06:40:12.84#ibcon#end of sib2, iclass 29, count 2 2006.285.06:40:12.84#ibcon#*after write, iclass 29, count 2 2006.285.06:40:12.84#ibcon#*before return 0, iclass 29, count 2 2006.285.06:40:12.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:40:12.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.06:40:12.84#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.06:40:12.84#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:12.84#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:40:12.96#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:40:12.96#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:40:12.96#ibcon#enter wrdev, iclass 29, count 0 2006.285.06:40:12.96#ibcon#first serial, iclass 29, count 0 2006.285.06:40:12.96#ibcon#enter sib2, iclass 29, count 0 2006.285.06:40:12.96#ibcon#flushed, iclass 29, count 0 2006.285.06:40:12.96#ibcon#about to write, iclass 29, count 0 2006.285.06:40:12.96#ibcon#wrote, iclass 29, count 0 2006.285.06:40:12.96#ibcon#about to read 3, iclass 29, count 0 2006.285.06:40:12.98#ibcon#read 3, iclass 29, count 0 2006.285.06:40:12.98#ibcon#about to read 4, iclass 29, count 0 2006.285.06:40:12.98#ibcon#read 4, iclass 29, count 0 2006.285.06:40:12.98#ibcon#about to read 5, iclass 29, count 0 2006.285.06:40:12.98#ibcon#read 5, iclass 29, count 0 2006.285.06:40:12.98#ibcon#about to read 6, iclass 29, count 0 2006.285.06:40:12.98#ibcon#read 6, iclass 29, count 0 2006.285.06:40:12.98#ibcon#end of sib2, iclass 29, count 0 2006.285.06:40:12.98#ibcon#*mode == 0, iclass 29, count 0 2006.285.06:40:12.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.06:40:12.98#ibcon#[27=USB\r\n] 2006.285.06:40:12.98#ibcon#*before write, iclass 29, count 0 2006.285.06:40:12.98#ibcon#enter sib2, iclass 29, count 0 2006.285.06:40:12.98#ibcon#flushed, iclass 29, count 0 2006.285.06:40:12.98#ibcon#about to write, iclass 29, count 0 2006.285.06:40:12.98#ibcon#wrote, iclass 29, count 0 2006.285.06:40:12.98#ibcon#about to read 3, iclass 29, count 0 2006.285.06:40:13.01#ibcon#read 3, iclass 29, count 0 2006.285.06:40:13.01#ibcon#about to read 4, iclass 29, count 0 2006.285.06:40:13.01#ibcon#read 4, iclass 29, count 0 2006.285.06:40:13.01#ibcon#about to read 5, iclass 29, count 0 2006.285.06:40:13.01#ibcon#read 5, iclass 29, count 0 2006.285.06:40:13.01#ibcon#about to read 6, iclass 29, count 0 2006.285.06:40:13.01#ibcon#read 6, iclass 29, count 0 2006.285.06:40:13.01#ibcon#end of sib2, iclass 29, count 0 2006.285.06:40:13.01#ibcon#*after write, iclass 29, count 0 2006.285.06:40:13.01#ibcon#*before return 0, iclass 29, count 0 2006.285.06:40:13.01#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:40:13.01#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.06:40:13.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.06:40:13.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.06:40:13.01$vck44/vblo=6,719.99 2006.285.06:40:13.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.06:40:13.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.06:40:13.01#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:13.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:40:13.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:40:13.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:40:13.01#ibcon#enter wrdev, iclass 31, count 0 2006.285.06:40:13.01#ibcon#first serial, iclass 31, count 0 2006.285.06:40:13.01#ibcon#enter sib2, iclass 31, count 0 2006.285.06:40:13.01#ibcon#flushed, iclass 31, count 0 2006.285.06:40:13.01#ibcon#about to write, iclass 31, count 0 2006.285.06:40:13.01#ibcon#wrote, iclass 31, count 0 2006.285.06:40:13.01#ibcon#about to read 3, iclass 31, count 0 2006.285.06:40:13.03#ibcon#read 3, iclass 31, count 0 2006.285.06:40:13.03#ibcon#about to read 4, iclass 31, count 0 2006.285.06:40:13.03#ibcon#read 4, iclass 31, count 0 2006.285.06:40:13.03#ibcon#about to read 5, iclass 31, count 0 2006.285.06:40:13.03#ibcon#read 5, iclass 31, count 0 2006.285.06:40:13.03#ibcon#about to read 6, iclass 31, count 0 2006.285.06:40:13.03#ibcon#read 6, iclass 31, count 0 2006.285.06:40:13.03#ibcon#end of sib2, iclass 31, count 0 2006.285.06:40:13.03#ibcon#*mode == 0, iclass 31, count 0 2006.285.06:40:13.03#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.06:40:13.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:40:13.03#ibcon#*before write, iclass 31, count 0 2006.285.06:40:13.03#ibcon#enter sib2, iclass 31, count 0 2006.285.06:40:13.03#ibcon#flushed, iclass 31, count 0 2006.285.06:40:13.03#ibcon#about to write, iclass 31, count 0 2006.285.06:40:13.03#ibcon#wrote, iclass 31, count 0 2006.285.06:40:13.03#ibcon#about to read 3, iclass 31, count 0 2006.285.06:40:13.07#ibcon#read 3, iclass 31, count 0 2006.285.06:40:13.07#ibcon#about to read 4, iclass 31, count 0 2006.285.06:40:13.07#ibcon#read 4, iclass 31, count 0 2006.285.06:40:13.07#ibcon#about to read 5, iclass 31, count 0 2006.285.06:40:13.07#ibcon#read 5, iclass 31, count 0 2006.285.06:40:13.07#ibcon#about to read 6, iclass 31, count 0 2006.285.06:40:13.07#ibcon#read 6, iclass 31, count 0 2006.285.06:40:13.07#ibcon#end of sib2, iclass 31, count 0 2006.285.06:40:13.07#ibcon#*after write, iclass 31, count 0 2006.285.06:40:13.07#ibcon#*before return 0, iclass 31, count 0 2006.285.06:40:13.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:40:13.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.06:40:13.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.06:40:13.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.06:40:13.07$vck44/vb=6,3 2006.285.06:40:13.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.06:40:13.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.06:40:13.07#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:13.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:40:13.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:40:13.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:40:13.13#ibcon#enter wrdev, iclass 33, count 2 2006.285.06:40:13.13#ibcon#first serial, iclass 33, count 2 2006.285.06:40:13.13#ibcon#enter sib2, iclass 33, count 2 2006.285.06:40:13.13#ibcon#flushed, iclass 33, count 2 2006.285.06:40:13.13#ibcon#about to write, iclass 33, count 2 2006.285.06:40:13.13#ibcon#wrote, iclass 33, count 2 2006.285.06:40:13.13#ibcon#about to read 3, iclass 33, count 2 2006.285.06:40:13.15#ibcon#read 3, iclass 33, count 2 2006.285.06:40:13.15#ibcon#about to read 4, iclass 33, count 2 2006.285.06:40:13.15#ibcon#read 4, iclass 33, count 2 2006.285.06:40:13.15#ibcon#about to read 5, iclass 33, count 2 2006.285.06:40:13.15#ibcon#read 5, iclass 33, count 2 2006.285.06:40:13.15#ibcon#about to read 6, iclass 33, count 2 2006.285.06:40:13.15#ibcon#read 6, iclass 33, count 2 2006.285.06:40:13.15#ibcon#end of sib2, iclass 33, count 2 2006.285.06:40:13.15#ibcon#*mode == 0, iclass 33, count 2 2006.285.06:40:13.15#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.06:40:13.15#ibcon#[27=AT06-03\r\n] 2006.285.06:40:13.15#ibcon#*before write, iclass 33, count 2 2006.285.06:40:13.15#ibcon#enter sib2, iclass 33, count 2 2006.285.06:40:13.15#ibcon#flushed, iclass 33, count 2 2006.285.06:40:13.15#ibcon#about to write, iclass 33, count 2 2006.285.06:40:13.15#ibcon#wrote, iclass 33, count 2 2006.285.06:40:13.15#ibcon#about to read 3, iclass 33, count 2 2006.285.06:40:13.18#ibcon#read 3, iclass 33, count 2 2006.285.06:40:13.18#ibcon#about to read 4, iclass 33, count 2 2006.285.06:40:13.18#ibcon#read 4, iclass 33, count 2 2006.285.06:40:13.18#ibcon#about to read 5, iclass 33, count 2 2006.285.06:40:13.18#ibcon#read 5, iclass 33, count 2 2006.285.06:40:13.18#ibcon#about to read 6, iclass 33, count 2 2006.285.06:40:13.18#ibcon#read 6, iclass 33, count 2 2006.285.06:40:13.18#ibcon#end of sib2, iclass 33, count 2 2006.285.06:40:13.18#ibcon#*after write, iclass 33, count 2 2006.285.06:40:13.18#ibcon#*before return 0, iclass 33, count 2 2006.285.06:40:13.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:40:13.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.06:40:13.18#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.06:40:13.18#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:13.18#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:40:13.30#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:40:13.30#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:40:13.30#ibcon#enter wrdev, iclass 33, count 0 2006.285.06:40:13.30#ibcon#first serial, iclass 33, count 0 2006.285.06:40:13.30#ibcon#enter sib2, iclass 33, count 0 2006.285.06:40:13.30#ibcon#flushed, iclass 33, count 0 2006.285.06:40:13.30#ibcon#about to write, iclass 33, count 0 2006.285.06:40:13.30#ibcon#wrote, iclass 33, count 0 2006.285.06:40:13.30#ibcon#about to read 3, iclass 33, count 0 2006.285.06:40:13.32#ibcon#read 3, iclass 33, count 0 2006.285.06:40:13.32#ibcon#about to read 4, iclass 33, count 0 2006.285.06:40:13.32#ibcon#read 4, iclass 33, count 0 2006.285.06:40:13.32#ibcon#about to read 5, iclass 33, count 0 2006.285.06:40:13.32#ibcon#read 5, iclass 33, count 0 2006.285.06:40:13.32#ibcon#about to read 6, iclass 33, count 0 2006.285.06:40:13.32#ibcon#read 6, iclass 33, count 0 2006.285.06:40:13.32#ibcon#end of sib2, iclass 33, count 0 2006.285.06:40:13.32#ibcon#*mode == 0, iclass 33, count 0 2006.285.06:40:13.32#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.06:40:13.32#ibcon#[27=USB\r\n] 2006.285.06:40:13.32#ibcon#*before write, iclass 33, count 0 2006.285.06:40:13.32#ibcon#enter sib2, iclass 33, count 0 2006.285.06:40:13.32#ibcon#flushed, iclass 33, count 0 2006.285.06:40:13.32#ibcon#about to write, iclass 33, count 0 2006.285.06:40:13.32#ibcon#wrote, iclass 33, count 0 2006.285.06:40:13.32#ibcon#about to read 3, iclass 33, count 0 2006.285.06:40:13.35#ibcon#read 3, iclass 33, count 0 2006.285.06:40:13.35#ibcon#about to read 4, iclass 33, count 0 2006.285.06:40:13.35#ibcon#read 4, iclass 33, count 0 2006.285.06:40:13.35#ibcon#about to read 5, iclass 33, count 0 2006.285.06:40:13.35#ibcon#read 5, iclass 33, count 0 2006.285.06:40:13.35#ibcon#about to read 6, iclass 33, count 0 2006.285.06:40:13.35#ibcon#read 6, iclass 33, count 0 2006.285.06:40:13.35#ibcon#end of sib2, iclass 33, count 0 2006.285.06:40:13.35#ibcon#*after write, iclass 33, count 0 2006.285.06:40:13.35#ibcon#*before return 0, iclass 33, count 0 2006.285.06:40:13.35#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:40:13.35#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.06:40:13.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.06:40:13.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.06:40:13.35$vck44/vblo=7,734.99 2006.285.06:40:13.35#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.06:40:13.35#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.06:40:13.35#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:13.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:40:13.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:40:13.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:40:13.35#ibcon#enter wrdev, iclass 35, count 0 2006.285.06:40:13.35#ibcon#first serial, iclass 35, count 0 2006.285.06:40:13.35#ibcon#enter sib2, iclass 35, count 0 2006.285.06:40:13.35#ibcon#flushed, iclass 35, count 0 2006.285.06:40:13.35#ibcon#about to write, iclass 35, count 0 2006.285.06:40:13.35#ibcon#wrote, iclass 35, count 0 2006.285.06:40:13.35#ibcon#about to read 3, iclass 35, count 0 2006.285.06:40:13.37#ibcon#read 3, iclass 35, count 0 2006.285.06:40:13.37#ibcon#about to read 4, iclass 35, count 0 2006.285.06:40:13.37#ibcon#read 4, iclass 35, count 0 2006.285.06:40:13.37#ibcon#about to read 5, iclass 35, count 0 2006.285.06:40:13.37#ibcon#read 5, iclass 35, count 0 2006.285.06:40:13.37#ibcon#about to read 6, iclass 35, count 0 2006.285.06:40:13.37#ibcon#read 6, iclass 35, count 0 2006.285.06:40:13.37#ibcon#end of sib2, iclass 35, count 0 2006.285.06:40:13.37#ibcon#*mode == 0, iclass 35, count 0 2006.285.06:40:13.37#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.06:40:13.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:40:13.37#ibcon#*before write, iclass 35, count 0 2006.285.06:40:13.37#ibcon#enter sib2, iclass 35, count 0 2006.285.06:40:13.37#ibcon#flushed, iclass 35, count 0 2006.285.06:40:13.37#ibcon#about to write, iclass 35, count 0 2006.285.06:40:13.37#ibcon#wrote, iclass 35, count 0 2006.285.06:40:13.37#ibcon#about to read 3, iclass 35, count 0 2006.285.06:40:13.41#ibcon#read 3, iclass 35, count 0 2006.285.06:40:13.41#ibcon#about to read 4, iclass 35, count 0 2006.285.06:40:13.41#ibcon#read 4, iclass 35, count 0 2006.285.06:40:13.41#ibcon#about to read 5, iclass 35, count 0 2006.285.06:40:13.41#ibcon#read 5, iclass 35, count 0 2006.285.06:40:13.41#ibcon#about to read 6, iclass 35, count 0 2006.285.06:40:13.41#ibcon#read 6, iclass 35, count 0 2006.285.06:40:13.41#ibcon#end of sib2, iclass 35, count 0 2006.285.06:40:13.41#ibcon#*after write, iclass 35, count 0 2006.285.06:40:13.41#ibcon#*before return 0, iclass 35, count 0 2006.285.06:40:13.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:40:13.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.06:40:13.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.06:40:13.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.06:40:13.41$vck44/vb=7,4 2006.285.06:40:13.41#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.06:40:13.41#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.06:40:13.41#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:13.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:40:13.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:40:13.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:40:13.47#ibcon#enter wrdev, iclass 37, count 2 2006.285.06:40:13.47#ibcon#first serial, iclass 37, count 2 2006.285.06:40:13.47#ibcon#enter sib2, iclass 37, count 2 2006.285.06:40:13.47#ibcon#flushed, iclass 37, count 2 2006.285.06:40:13.47#ibcon#about to write, iclass 37, count 2 2006.285.06:40:13.47#ibcon#wrote, iclass 37, count 2 2006.285.06:40:13.47#ibcon#about to read 3, iclass 37, count 2 2006.285.06:40:13.49#ibcon#read 3, iclass 37, count 2 2006.285.06:40:13.49#ibcon#about to read 4, iclass 37, count 2 2006.285.06:40:13.49#ibcon#read 4, iclass 37, count 2 2006.285.06:40:13.49#ibcon#about to read 5, iclass 37, count 2 2006.285.06:40:13.49#ibcon#read 5, iclass 37, count 2 2006.285.06:40:13.49#ibcon#about to read 6, iclass 37, count 2 2006.285.06:40:13.49#ibcon#read 6, iclass 37, count 2 2006.285.06:40:13.49#ibcon#end of sib2, iclass 37, count 2 2006.285.06:40:13.49#ibcon#*mode == 0, iclass 37, count 2 2006.285.06:40:13.49#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.06:40:13.49#ibcon#[27=AT07-04\r\n] 2006.285.06:40:13.49#ibcon#*before write, iclass 37, count 2 2006.285.06:40:13.49#ibcon#enter sib2, iclass 37, count 2 2006.285.06:40:13.49#ibcon#flushed, iclass 37, count 2 2006.285.06:40:13.49#ibcon#about to write, iclass 37, count 2 2006.285.06:40:13.49#ibcon#wrote, iclass 37, count 2 2006.285.06:40:13.49#ibcon#about to read 3, iclass 37, count 2 2006.285.06:40:13.52#ibcon#read 3, iclass 37, count 2 2006.285.06:40:13.52#ibcon#about to read 4, iclass 37, count 2 2006.285.06:40:13.52#ibcon#read 4, iclass 37, count 2 2006.285.06:40:13.52#ibcon#about to read 5, iclass 37, count 2 2006.285.06:40:13.52#ibcon#read 5, iclass 37, count 2 2006.285.06:40:13.52#ibcon#about to read 6, iclass 37, count 2 2006.285.06:40:13.52#ibcon#read 6, iclass 37, count 2 2006.285.06:40:13.52#ibcon#end of sib2, iclass 37, count 2 2006.285.06:40:13.52#ibcon#*after write, iclass 37, count 2 2006.285.06:40:13.52#ibcon#*before return 0, iclass 37, count 2 2006.285.06:40:13.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:40:13.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.06:40:13.52#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.06:40:13.52#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:13.52#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:40:13.64#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:40:13.64#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:40:13.64#ibcon#enter wrdev, iclass 37, count 0 2006.285.06:40:13.64#ibcon#first serial, iclass 37, count 0 2006.285.06:40:13.64#ibcon#enter sib2, iclass 37, count 0 2006.285.06:40:13.64#ibcon#flushed, iclass 37, count 0 2006.285.06:40:13.64#ibcon#about to write, iclass 37, count 0 2006.285.06:40:13.64#ibcon#wrote, iclass 37, count 0 2006.285.06:40:13.64#ibcon#about to read 3, iclass 37, count 0 2006.285.06:40:13.66#ibcon#read 3, iclass 37, count 0 2006.285.06:40:13.66#ibcon#about to read 4, iclass 37, count 0 2006.285.06:40:13.66#ibcon#read 4, iclass 37, count 0 2006.285.06:40:13.66#ibcon#about to read 5, iclass 37, count 0 2006.285.06:40:13.66#ibcon#read 5, iclass 37, count 0 2006.285.06:40:13.66#ibcon#about to read 6, iclass 37, count 0 2006.285.06:40:13.66#ibcon#read 6, iclass 37, count 0 2006.285.06:40:13.66#ibcon#end of sib2, iclass 37, count 0 2006.285.06:40:13.66#ibcon#*mode == 0, iclass 37, count 0 2006.285.06:40:13.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.06:40:13.66#ibcon#[27=USB\r\n] 2006.285.06:40:13.66#ibcon#*before write, iclass 37, count 0 2006.285.06:40:13.66#ibcon#enter sib2, iclass 37, count 0 2006.285.06:40:13.66#ibcon#flushed, iclass 37, count 0 2006.285.06:40:13.66#ibcon#about to write, iclass 37, count 0 2006.285.06:40:13.66#ibcon#wrote, iclass 37, count 0 2006.285.06:40:13.66#ibcon#about to read 3, iclass 37, count 0 2006.285.06:40:13.69#ibcon#read 3, iclass 37, count 0 2006.285.06:40:13.69#ibcon#about to read 4, iclass 37, count 0 2006.285.06:40:13.69#ibcon#read 4, iclass 37, count 0 2006.285.06:40:13.69#ibcon#about to read 5, iclass 37, count 0 2006.285.06:40:13.69#ibcon#read 5, iclass 37, count 0 2006.285.06:40:13.69#ibcon#about to read 6, iclass 37, count 0 2006.285.06:40:13.69#ibcon#read 6, iclass 37, count 0 2006.285.06:40:13.69#ibcon#end of sib2, iclass 37, count 0 2006.285.06:40:13.69#ibcon#*after write, iclass 37, count 0 2006.285.06:40:13.69#ibcon#*before return 0, iclass 37, count 0 2006.285.06:40:13.69#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:40:13.69#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.06:40:13.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.06:40:13.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.06:40:13.69$vck44/vblo=8,744.99 2006.285.06:40:13.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.06:40:13.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.06:40:13.69#ibcon#ireg 17 cls_cnt 0 2006.285.06:40:13.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:40:13.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:40:13.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:40:13.69#ibcon#enter wrdev, iclass 39, count 0 2006.285.06:40:13.69#ibcon#first serial, iclass 39, count 0 2006.285.06:40:13.69#ibcon#enter sib2, iclass 39, count 0 2006.285.06:40:13.69#ibcon#flushed, iclass 39, count 0 2006.285.06:40:13.69#ibcon#about to write, iclass 39, count 0 2006.285.06:40:13.69#ibcon#wrote, iclass 39, count 0 2006.285.06:40:13.69#ibcon#about to read 3, iclass 39, count 0 2006.285.06:40:13.71#ibcon#read 3, iclass 39, count 0 2006.285.06:40:13.71#ibcon#about to read 4, iclass 39, count 0 2006.285.06:40:13.71#ibcon#read 4, iclass 39, count 0 2006.285.06:40:13.71#ibcon#about to read 5, iclass 39, count 0 2006.285.06:40:13.71#ibcon#read 5, iclass 39, count 0 2006.285.06:40:13.71#ibcon#about to read 6, iclass 39, count 0 2006.285.06:40:13.71#ibcon#read 6, iclass 39, count 0 2006.285.06:40:13.71#ibcon#end of sib2, iclass 39, count 0 2006.285.06:40:13.71#ibcon#*mode == 0, iclass 39, count 0 2006.285.06:40:13.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.06:40:13.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:40:13.71#ibcon#*before write, iclass 39, count 0 2006.285.06:40:13.71#ibcon#enter sib2, iclass 39, count 0 2006.285.06:40:13.71#ibcon#flushed, iclass 39, count 0 2006.285.06:40:13.71#ibcon#about to write, iclass 39, count 0 2006.285.06:40:13.71#ibcon#wrote, iclass 39, count 0 2006.285.06:40:13.71#ibcon#about to read 3, iclass 39, count 0 2006.285.06:40:13.75#ibcon#read 3, iclass 39, count 0 2006.285.06:40:13.75#ibcon#about to read 4, iclass 39, count 0 2006.285.06:40:13.75#ibcon#read 4, iclass 39, count 0 2006.285.06:40:13.75#ibcon#about to read 5, iclass 39, count 0 2006.285.06:40:13.75#ibcon#read 5, iclass 39, count 0 2006.285.06:40:13.75#ibcon#about to read 6, iclass 39, count 0 2006.285.06:40:13.75#ibcon#read 6, iclass 39, count 0 2006.285.06:40:13.75#ibcon#end of sib2, iclass 39, count 0 2006.285.06:40:13.75#ibcon#*after write, iclass 39, count 0 2006.285.06:40:13.75#ibcon#*before return 0, iclass 39, count 0 2006.285.06:40:13.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:40:13.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.06:40:13.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.06:40:13.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.06:40:13.75$vck44/vb=8,4 2006.285.06:40:13.75#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.06:40:13.75#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.06:40:13.75#ibcon#ireg 11 cls_cnt 2 2006.285.06:40:13.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:40:13.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:40:13.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:40:13.81#ibcon#enter wrdev, iclass 3, count 2 2006.285.06:40:13.81#ibcon#first serial, iclass 3, count 2 2006.285.06:40:13.81#ibcon#enter sib2, iclass 3, count 2 2006.285.06:40:13.81#ibcon#flushed, iclass 3, count 2 2006.285.06:40:13.81#ibcon#about to write, iclass 3, count 2 2006.285.06:40:13.81#ibcon#wrote, iclass 3, count 2 2006.285.06:40:13.81#ibcon#about to read 3, iclass 3, count 2 2006.285.06:40:13.83#ibcon#read 3, iclass 3, count 2 2006.285.06:40:13.83#ibcon#about to read 4, iclass 3, count 2 2006.285.06:40:13.83#ibcon#read 4, iclass 3, count 2 2006.285.06:40:13.83#ibcon#about to read 5, iclass 3, count 2 2006.285.06:40:13.83#ibcon#read 5, iclass 3, count 2 2006.285.06:40:13.83#ibcon#about to read 6, iclass 3, count 2 2006.285.06:40:13.83#ibcon#read 6, iclass 3, count 2 2006.285.06:40:13.83#ibcon#end of sib2, iclass 3, count 2 2006.285.06:40:13.83#ibcon#*mode == 0, iclass 3, count 2 2006.285.06:40:13.83#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.06:40:13.83#ibcon#[27=AT08-04\r\n] 2006.285.06:40:13.83#ibcon#*before write, iclass 3, count 2 2006.285.06:40:13.83#ibcon#enter sib2, iclass 3, count 2 2006.285.06:40:13.83#ibcon#flushed, iclass 3, count 2 2006.285.06:40:13.83#ibcon#about to write, iclass 3, count 2 2006.285.06:40:13.83#ibcon#wrote, iclass 3, count 2 2006.285.06:40:13.83#ibcon#about to read 3, iclass 3, count 2 2006.285.06:40:13.86#ibcon#read 3, iclass 3, count 2 2006.285.06:40:13.86#ibcon#about to read 4, iclass 3, count 2 2006.285.06:40:13.86#ibcon#read 4, iclass 3, count 2 2006.285.06:40:13.86#ibcon#about to read 5, iclass 3, count 2 2006.285.06:40:13.86#ibcon#read 5, iclass 3, count 2 2006.285.06:40:13.86#ibcon#about to read 6, iclass 3, count 2 2006.285.06:40:13.86#ibcon#read 6, iclass 3, count 2 2006.285.06:40:13.86#ibcon#end of sib2, iclass 3, count 2 2006.285.06:40:13.86#ibcon#*after write, iclass 3, count 2 2006.285.06:40:13.86#ibcon#*before return 0, iclass 3, count 2 2006.285.06:40:13.86#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:40:13.86#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.06:40:13.86#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.06:40:13.86#ibcon#ireg 7 cls_cnt 0 2006.285.06:40:13.86#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:40:13.98#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:40:13.98#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:40:13.98#ibcon#enter wrdev, iclass 3, count 0 2006.285.06:40:13.98#ibcon#first serial, iclass 3, count 0 2006.285.06:40:13.98#ibcon#enter sib2, iclass 3, count 0 2006.285.06:40:13.98#ibcon#flushed, iclass 3, count 0 2006.285.06:40:13.98#ibcon#about to write, iclass 3, count 0 2006.285.06:40:13.98#ibcon#wrote, iclass 3, count 0 2006.285.06:40:13.98#ibcon#about to read 3, iclass 3, count 0 2006.285.06:40:14.00#ibcon#read 3, iclass 3, count 0 2006.285.06:40:14.00#ibcon#about to read 4, iclass 3, count 0 2006.285.06:40:14.00#ibcon#read 4, iclass 3, count 0 2006.285.06:40:14.00#ibcon#about to read 5, iclass 3, count 0 2006.285.06:40:14.00#ibcon#read 5, iclass 3, count 0 2006.285.06:40:14.00#ibcon#about to read 6, iclass 3, count 0 2006.285.06:40:14.00#ibcon#read 6, iclass 3, count 0 2006.285.06:40:14.00#ibcon#end of sib2, iclass 3, count 0 2006.285.06:40:14.00#ibcon#*mode == 0, iclass 3, count 0 2006.285.06:40:14.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.06:40:14.00#ibcon#[27=USB\r\n] 2006.285.06:40:14.00#ibcon#*before write, iclass 3, count 0 2006.285.06:40:14.00#ibcon#enter sib2, iclass 3, count 0 2006.285.06:40:14.00#ibcon#flushed, iclass 3, count 0 2006.285.06:40:14.00#ibcon#about to write, iclass 3, count 0 2006.285.06:40:14.00#ibcon#wrote, iclass 3, count 0 2006.285.06:40:14.00#ibcon#about to read 3, iclass 3, count 0 2006.285.06:40:14.03#ibcon#read 3, iclass 3, count 0 2006.285.06:40:14.03#ibcon#about to read 4, iclass 3, count 0 2006.285.06:40:14.03#ibcon#read 4, iclass 3, count 0 2006.285.06:40:14.03#ibcon#about to read 5, iclass 3, count 0 2006.285.06:40:14.03#ibcon#read 5, iclass 3, count 0 2006.285.06:40:14.03#ibcon#about to read 6, iclass 3, count 0 2006.285.06:40:14.03#ibcon#read 6, iclass 3, count 0 2006.285.06:40:14.03#ibcon#end of sib2, iclass 3, count 0 2006.285.06:40:14.03#ibcon#*after write, iclass 3, count 0 2006.285.06:40:14.03#ibcon#*before return 0, iclass 3, count 0 2006.285.06:40:14.03#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:40:14.03#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.06:40:14.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.06:40:14.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.06:40:14.03$vck44/vabw=wide 2006.285.06:40:14.03#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.06:40:14.03#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.06:40:14.03#ibcon#ireg 8 cls_cnt 0 2006.285.06:40:14.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:40:14.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:40:14.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:40:14.03#ibcon#enter wrdev, iclass 5, count 0 2006.285.06:40:14.03#ibcon#first serial, iclass 5, count 0 2006.285.06:40:14.03#ibcon#enter sib2, iclass 5, count 0 2006.285.06:40:14.03#ibcon#flushed, iclass 5, count 0 2006.285.06:40:14.03#ibcon#about to write, iclass 5, count 0 2006.285.06:40:14.03#ibcon#wrote, iclass 5, count 0 2006.285.06:40:14.03#ibcon#about to read 3, iclass 5, count 0 2006.285.06:40:14.05#ibcon#read 3, iclass 5, count 0 2006.285.06:40:14.05#ibcon#about to read 4, iclass 5, count 0 2006.285.06:40:14.05#ibcon#read 4, iclass 5, count 0 2006.285.06:40:14.05#ibcon#about to read 5, iclass 5, count 0 2006.285.06:40:14.05#ibcon#read 5, iclass 5, count 0 2006.285.06:40:14.05#ibcon#about to read 6, iclass 5, count 0 2006.285.06:40:14.05#ibcon#read 6, iclass 5, count 0 2006.285.06:40:14.05#ibcon#end of sib2, iclass 5, count 0 2006.285.06:40:14.05#ibcon#*mode == 0, iclass 5, count 0 2006.285.06:40:14.05#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.06:40:14.05#ibcon#[25=BW32\r\n] 2006.285.06:40:14.05#ibcon#*before write, iclass 5, count 0 2006.285.06:40:14.05#ibcon#enter sib2, iclass 5, count 0 2006.285.06:40:14.05#ibcon#flushed, iclass 5, count 0 2006.285.06:40:14.05#ibcon#about to write, iclass 5, count 0 2006.285.06:40:14.05#ibcon#wrote, iclass 5, count 0 2006.285.06:40:14.05#ibcon#about to read 3, iclass 5, count 0 2006.285.06:40:14.08#ibcon#read 3, iclass 5, count 0 2006.285.06:40:14.08#ibcon#about to read 4, iclass 5, count 0 2006.285.06:40:14.08#ibcon#read 4, iclass 5, count 0 2006.285.06:40:14.08#ibcon#about to read 5, iclass 5, count 0 2006.285.06:40:14.08#ibcon#read 5, iclass 5, count 0 2006.285.06:40:14.08#ibcon#about to read 6, iclass 5, count 0 2006.285.06:40:14.08#ibcon#read 6, iclass 5, count 0 2006.285.06:40:14.08#ibcon#end of sib2, iclass 5, count 0 2006.285.06:40:14.08#ibcon#*after write, iclass 5, count 0 2006.285.06:40:14.08#ibcon#*before return 0, iclass 5, count 0 2006.285.06:40:14.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:40:14.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.06:40:14.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.06:40:14.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.06:40:14.08$vck44/vbbw=wide 2006.285.06:40:14.08#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.06:40:14.08#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.06:40:14.08#ibcon#ireg 8 cls_cnt 0 2006.285.06:40:14.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:40:14.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:40:14.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:40:14.15#ibcon#enter wrdev, iclass 7, count 0 2006.285.06:40:14.15#ibcon#first serial, iclass 7, count 0 2006.285.06:40:14.15#ibcon#enter sib2, iclass 7, count 0 2006.285.06:40:14.15#ibcon#flushed, iclass 7, count 0 2006.285.06:40:14.15#ibcon#about to write, iclass 7, count 0 2006.285.06:40:14.15#ibcon#wrote, iclass 7, count 0 2006.285.06:40:14.15#ibcon#about to read 3, iclass 7, count 0 2006.285.06:40:14.17#ibcon#read 3, iclass 7, count 0 2006.285.06:40:14.17#ibcon#about to read 4, iclass 7, count 0 2006.285.06:40:14.17#ibcon#read 4, iclass 7, count 0 2006.285.06:40:14.17#ibcon#about to read 5, iclass 7, count 0 2006.285.06:40:14.17#ibcon#read 5, iclass 7, count 0 2006.285.06:40:14.17#ibcon#about to read 6, iclass 7, count 0 2006.285.06:40:14.17#ibcon#read 6, iclass 7, count 0 2006.285.06:40:14.17#ibcon#end of sib2, iclass 7, count 0 2006.285.06:40:14.17#ibcon#*mode == 0, iclass 7, count 0 2006.285.06:40:14.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.06:40:14.17#ibcon#[27=BW32\r\n] 2006.285.06:40:14.17#ibcon#*before write, iclass 7, count 0 2006.285.06:40:14.17#ibcon#enter sib2, iclass 7, count 0 2006.285.06:40:14.17#ibcon#flushed, iclass 7, count 0 2006.285.06:40:14.17#ibcon#about to write, iclass 7, count 0 2006.285.06:40:14.17#ibcon#wrote, iclass 7, count 0 2006.285.06:40:14.17#ibcon#about to read 3, iclass 7, count 0 2006.285.06:40:14.20#ibcon#read 3, iclass 7, count 0 2006.285.06:40:14.20#ibcon#about to read 4, iclass 7, count 0 2006.285.06:40:14.20#ibcon#read 4, iclass 7, count 0 2006.285.06:40:14.20#ibcon#about to read 5, iclass 7, count 0 2006.285.06:40:14.20#ibcon#read 5, iclass 7, count 0 2006.285.06:40:14.20#ibcon#about to read 6, iclass 7, count 0 2006.285.06:40:14.20#ibcon#read 6, iclass 7, count 0 2006.285.06:40:14.20#ibcon#end of sib2, iclass 7, count 0 2006.285.06:40:14.20#ibcon#*after write, iclass 7, count 0 2006.285.06:40:14.20#ibcon#*before return 0, iclass 7, count 0 2006.285.06:40:14.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:40:14.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.06:40:14.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.06:40:14.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.06:40:14.20$setupk4/ifdk4 2006.285.06:40:14.20$ifdk4/lo= 2006.285.06:40:14.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:40:14.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:40:14.20$ifdk4/patch= 2006.285.06:40:14.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:40:14.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:40:14.20$setupk4/!*+20s 2006.285.06:40:16.10#abcon#<5=/05 4.5 7.6 24.78 691014.2\r\n> 2006.285.06:40:16.12#abcon#{5=INTERFACE CLEAR} 2006.285.06:40:16.18#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:40:20.13#trakl#Source acquired 2006.285.06:40:22.13#flagr#flagr/antenna,acquired 2006.285.06:40:26.27#abcon#<5=/05 4.5 7.6 24.78 691014.2\r\n> 2006.285.06:40:26.29#abcon#{5=INTERFACE CLEAR} 2006.285.06:40:26.35#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:40:28.71$setupk4/"tpicd 2006.285.06:40:28.71$setupk4/echo=off 2006.285.06:40:28.71$setupk4/xlog=off 2006.285.06:40:28.71:!2006.285.06:41:24 2006.285.06:41:24.00:preob 2006.285.06:41:24.14/onsource/TRACKING 2006.285.06:41:24.14:!2006.285.06:41:34 2006.285.06:41:34.00:"tape 2006.285.06:41:34.00:"st=record 2006.285.06:41:34.00:data_valid=on 2006.285.06:41:34.00:midob 2006.285.06:41:34.14/onsource/TRACKING 2006.285.06:41:34.14/wx/24.77,1014.2,70 2006.285.06:41:34.23/cable/+6.4738E-03 2006.285.06:41:35.32/va/01,07,usb,yes,32,35 2006.285.06:41:35.32/va/02,06,usb,yes,32,33 2006.285.06:41:35.32/va/03,07,usb,yes,32,33 2006.285.06:41:35.32/va/04,06,usb,yes,33,35 2006.285.06:41:35.32/va/05,03,usb,yes,33,33 2006.285.06:41:35.32/va/06,04,usb,yes,29,29 2006.285.06:41:35.32/va/07,04,usb,yes,30,31 2006.285.06:41:35.32/va/08,03,usb,yes,30,37 2006.285.06:41:35.55/valo/01,524.99,yes,locked 2006.285.06:41:35.55/valo/02,534.99,yes,locked 2006.285.06:41:35.55/valo/03,564.99,yes,locked 2006.285.06:41:35.55/valo/04,624.99,yes,locked 2006.285.06:41:35.55/valo/05,734.99,yes,locked 2006.285.06:41:35.55/valo/06,814.99,yes,locked 2006.285.06:41:35.55/valo/07,864.99,yes,locked 2006.285.06:41:35.55/valo/08,884.99,yes,locked 2006.285.06:41:36.64/vb/01,04,usb,yes,31,29 2006.285.06:41:36.64/vb/02,05,usb,yes,29,29 2006.285.06:41:36.64/vb/03,04,usb,yes,30,33 2006.285.06:41:36.64/vb/04,05,usb,yes,31,30 2006.285.06:41:36.64/vb/05,04,usb,yes,27,29 2006.285.06:41:36.64/vb/06,03,usb,yes,39,34 2006.285.06:41:36.64/vb/07,04,usb,yes,31,31 2006.285.06:41:36.64/vb/08,04,usb,yes,28,32 2006.285.06:41:36.87/vblo/01,629.99,yes,locked 2006.285.06:41:36.87/vblo/02,634.99,yes,locked 2006.285.06:41:36.87/vblo/03,649.99,yes,locked 2006.285.06:41:36.87/vblo/04,679.99,yes,locked 2006.285.06:41:36.87/vblo/05,709.99,yes,locked 2006.285.06:41:36.87/vblo/06,719.99,yes,locked 2006.285.06:41:36.87/vblo/07,734.99,yes,locked 2006.285.06:41:36.87/vblo/08,744.99,yes,locked 2006.285.06:41:37.02/vabw/8 2006.285.06:41:37.17/vbbw/8 2006.285.06:41:37.26/xfe/off,on,12.5 2006.285.06:41:37.63/ifatt/23,28,28,28 2006.285.06:41:38.07/fmout-gps/S +2.58E-07 2006.285.06:41:38.09:!2006.285.06:44:24 2006.285.06:44:24.01:data_valid=off 2006.285.06:44:24.01:"et 2006.285.06:44:24.01:!+3s 2006.285.06:44:27.02:"tape 2006.285.06:44:27.02:postob 2006.285.06:44:27.14/cable/+6.4724E-03 2006.285.06:44:27.14/wx/24.73,1014.1,71 2006.285.06:44:27.20/fmout-gps/S +2.60E-07 2006.285.06:44:27.20:scan_name=285-0652,jd0610,150 2006.285.06:44:27.20:source=2128-123,213135.26,-120704.8,2000.0,cw 2006.285.06:44:28.14#flagr#flagr/antenna,new-source 2006.285.06:44:28.14:checkk5 2006.285.06:44:28.59/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:44:28.95/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:44:29.37/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:44:29.78/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:44:30.17/chk_obsdata//k5ts1/T2850641??a.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.06:44:30.60/chk_obsdata//k5ts2/T2850641??b.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.06:44:30.96/chk_obsdata//k5ts3/T2850641??c.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.06:44:31.37/chk_obsdata//k5ts4/T2850641??d.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.06:44:32.16/k5log//k5ts1_log_newline 2006.285.06:44:32.93/k5log//k5ts2_log_newline 2006.285.06:44:33.72/k5log//k5ts3_log_newline 2006.285.06:44:34.46/k5log//k5ts4_log_newline 2006.285.06:44:34.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:44:34.48:setupk4=1 2006.285.06:44:34.48$setupk4/echo=on 2006.285.06:44:34.48$setupk4/pcalon 2006.285.06:44:34.48$pcalon/"no phase cal control is implemented here 2006.285.06:44:34.48$setupk4/"tpicd=stop 2006.285.06:44:34.48$setupk4/"rec=synch_on 2006.285.06:44:34.48$setupk4/"rec_mode=128 2006.285.06:44:34.48$setupk4/!* 2006.285.06:44:34.48$setupk4/recpk4 2006.285.06:44:34.48$recpk4/recpatch= 2006.285.06:44:34.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:44:34.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:44:34.49$setupk4/vck44 2006.285.06:44:34.49$vck44/valo=1,524.99 2006.285.06:44:34.49#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.06:44:34.49#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.06:44:34.49#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:34.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:44:34.49#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:44:34.49#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:44:34.49#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:44:34.49#ibcon#first serial, iclass 10, count 0 2006.285.06:44:34.49#ibcon#enter sib2, iclass 10, count 0 2006.285.06:44:34.49#ibcon#flushed, iclass 10, count 0 2006.285.06:44:34.49#ibcon#about to write, iclass 10, count 0 2006.285.06:44:34.49#ibcon#wrote, iclass 10, count 0 2006.285.06:44:34.49#ibcon#about to read 3, iclass 10, count 0 2006.285.06:44:34.50#ibcon#read 3, iclass 10, count 0 2006.285.06:44:34.50#ibcon#about to read 4, iclass 10, count 0 2006.285.06:44:34.50#ibcon#read 4, iclass 10, count 0 2006.285.06:44:34.50#ibcon#about to read 5, iclass 10, count 0 2006.285.06:44:34.50#ibcon#read 5, iclass 10, count 0 2006.285.06:44:34.50#ibcon#about to read 6, iclass 10, count 0 2006.285.06:44:34.50#ibcon#read 6, iclass 10, count 0 2006.285.06:44:34.50#ibcon#end of sib2, iclass 10, count 0 2006.285.06:44:34.50#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:44:34.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:44:34.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:44:34.50#ibcon#*before write, iclass 10, count 0 2006.285.06:44:34.50#ibcon#enter sib2, iclass 10, count 0 2006.285.06:44:34.50#ibcon#flushed, iclass 10, count 0 2006.285.06:44:34.50#ibcon#about to write, iclass 10, count 0 2006.285.06:44:34.50#ibcon#wrote, iclass 10, count 0 2006.285.06:44:34.50#ibcon#about to read 3, iclass 10, count 0 2006.285.06:44:34.55#ibcon#read 3, iclass 10, count 0 2006.285.06:44:34.55#ibcon#about to read 4, iclass 10, count 0 2006.285.06:44:34.55#ibcon#read 4, iclass 10, count 0 2006.285.06:44:34.55#ibcon#about to read 5, iclass 10, count 0 2006.285.06:44:34.55#ibcon#read 5, iclass 10, count 0 2006.285.06:44:34.55#ibcon#about to read 6, iclass 10, count 0 2006.285.06:44:34.55#ibcon#read 6, iclass 10, count 0 2006.285.06:44:34.55#ibcon#end of sib2, iclass 10, count 0 2006.285.06:44:34.55#ibcon#*after write, iclass 10, count 0 2006.285.06:44:34.55#ibcon#*before return 0, iclass 10, count 0 2006.285.06:44:34.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:44:34.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:44:34.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:44:34.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:44:34.55$vck44/va=1,7 2006.285.06:44:34.55#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.06:44:34.55#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.06:44:34.55#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:34.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:44:34.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:44:34.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:44:34.55#ibcon#enter wrdev, iclass 12, count 2 2006.285.06:44:34.55#ibcon#first serial, iclass 12, count 2 2006.285.06:44:34.55#ibcon#enter sib2, iclass 12, count 2 2006.285.06:44:34.55#ibcon#flushed, iclass 12, count 2 2006.285.06:44:34.55#ibcon#about to write, iclass 12, count 2 2006.285.06:44:34.55#ibcon#wrote, iclass 12, count 2 2006.285.06:44:34.55#ibcon#about to read 3, iclass 12, count 2 2006.285.06:44:34.57#ibcon#read 3, iclass 12, count 2 2006.285.06:44:34.57#ibcon#about to read 4, iclass 12, count 2 2006.285.06:44:34.57#ibcon#read 4, iclass 12, count 2 2006.285.06:44:34.57#ibcon#about to read 5, iclass 12, count 2 2006.285.06:44:34.57#ibcon#read 5, iclass 12, count 2 2006.285.06:44:34.57#ibcon#about to read 6, iclass 12, count 2 2006.285.06:44:34.57#ibcon#read 6, iclass 12, count 2 2006.285.06:44:34.57#ibcon#end of sib2, iclass 12, count 2 2006.285.06:44:34.57#ibcon#*mode == 0, iclass 12, count 2 2006.285.06:44:34.57#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.06:44:34.57#ibcon#[25=AT01-07\r\n] 2006.285.06:44:34.57#ibcon#*before write, iclass 12, count 2 2006.285.06:44:34.57#ibcon#enter sib2, iclass 12, count 2 2006.285.06:44:34.57#ibcon#flushed, iclass 12, count 2 2006.285.06:44:34.57#ibcon#about to write, iclass 12, count 2 2006.285.06:44:34.57#ibcon#wrote, iclass 12, count 2 2006.285.06:44:34.57#ibcon#about to read 3, iclass 12, count 2 2006.285.06:44:34.60#ibcon#read 3, iclass 12, count 2 2006.285.06:44:34.60#ibcon#about to read 4, iclass 12, count 2 2006.285.06:44:34.60#ibcon#read 4, iclass 12, count 2 2006.285.06:44:34.60#ibcon#about to read 5, iclass 12, count 2 2006.285.06:44:34.60#ibcon#read 5, iclass 12, count 2 2006.285.06:44:34.60#ibcon#about to read 6, iclass 12, count 2 2006.285.06:44:34.60#ibcon#read 6, iclass 12, count 2 2006.285.06:44:34.60#ibcon#end of sib2, iclass 12, count 2 2006.285.06:44:34.60#ibcon#*after write, iclass 12, count 2 2006.285.06:44:34.60#ibcon#*before return 0, iclass 12, count 2 2006.285.06:44:34.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:44:34.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:44:34.60#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.06:44:34.60#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:34.60#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:44:34.72#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:44:34.72#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:44:34.72#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:44:34.72#ibcon#first serial, iclass 12, count 0 2006.285.06:44:34.72#ibcon#enter sib2, iclass 12, count 0 2006.285.06:44:34.72#ibcon#flushed, iclass 12, count 0 2006.285.06:44:34.72#ibcon#about to write, iclass 12, count 0 2006.285.06:44:34.72#ibcon#wrote, iclass 12, count 0 2006.285.06:44:34.72#ibcon#about to read 3, iclass 12, count 0 2006.285.06:44:34.74#ibcon#read 3, iclass 12, count 0 2006.285.06:44:34.74#ibcon#about to read 4, iclass 12, count 0 2006.285.06:44:34.74#ibcon#read 4, iclass 12, count 0 2006.285.06:44:34.74#ibcon#about to read 5, iclass 12, count 0 2006.285.06:44:34.74#ibcon#read 5, iclass 12, count 0 2006.285.06:44:34.74#ibcon#about to read 6, iclass 12, count 0 2006.285.06:44:34.74#ibcon#read 6, iclass 12, count 0 2006.285.06:44:34.74#ibcon#end of sib2, iclass 12, count 0 2006.285.06:44:34.74#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:44:34.74#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:44:34.74#ibcon#[25=USB\r\n] 2006.285.06:44:34.74#ibcon#*before write, iclass 12, count 0 2006.285.06:44:34.74#ibcon#enter sib2, iclass 12, count 0 2006.285.06:44:34.74#ibcon#flushed, iclass 12, count 0 2006.285.06:44:34.74#ibcon#about to write, iclass 12, count 0 2006.285.06:44:34.74#ibcon#wrote, iclass 12, count 0 2006.285.06:44:34.74#ibcon#about to read 3, iclass 12, count 0 2006.285.06:44:34.77#ibcon#read 3, iclass 12, count 0 2006.285.06:44:34.77#ibcon#about to read 4, iclass 12, count 0 2006.285.06:44:34.77#ibcon#read 4, iclass 12, count 0 2006.285.06:44:34.77#ibcon#about to read 5, iclass 12, count 0 2006.285.06:44:34.77#ibcon#read 5, iclass 12, count 0 2006.285.06:44:34.77#ibcon#about to read 6, iclass 12, count 0 2006.285.06:44:34.77#ibcon#read 6, iclass 12, count 0 2006.285.06:44:34.77#ibcon#end of sib2, iclass 12, count 0 2006.285.06:44:34.77#ibcon#*after write, iclass 12, count 0 2006.285.06:44:34.77#ibcon#*before return 0, iclass 12, count 0 2006.285.06:44:34.77#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:44:34.77#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:44:34.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:44:34.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:44:34.77$vck44/valo=2,534.99 2006.285.06:44:34.77#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.06:44:34.77#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.06:44:34.77#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:34.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:44:34.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:44:34.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:44:34.77#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:44:34.77#ibcon#first serial, iclass 14, count 0 2006.285.06:44:34.77#ibcon#enter sib2, iclass 14, count 0 2006.285.06:44:34.77#ibcon#flushed, iclass 14, count 0 2006.285.06:44:34.77#ibcon#about to write, iclass 14, count 0 2006.285.06:44:34.77#ibcon#wrote, iclass 14, count 0 2006.285.06:44:34.77#ibcon#about to read 3, iclass 14, count 0 2006.285.06:44:34.79#ibcon#read 3, iclass 14, count 0 2006.285.06:44:34.79#ibcon#about to read 4, iclass 14, count 0 2006.285.06:44:34.79#ibcon#read 4, iclass 14, count 0 2006.285.06:44:34.79#ibcon#about to read 5, iclass 14, count 0 2006.285.06:44:34.79#ibcon#read 5, iclass 14, count 0 2006.285.06:44:34.79#ibcon#about to read 6, iclass 14, count 0 2006.285.06:44:34.79#ibcon#read 6, iclass 14, count 0 2006.285.06:44:34.79#ibcon#end of sib2, iclass 14, count 0 2006.285.06:44:34.79#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:44:34.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:44:34.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:44:34.79#ibcon#*before write, iclass 14, count 0 2006.285.06:44:34.79#ibcon#enter sib2, iclass 14, count 0 2006.285.06:44:34.79#ibcon#flushed, iclass 14, count 0 2006.285.06:44:34.79#ibcon#about to write, iclass 14, count 0 2006.285.06:44:34.79#ibcon#wrote, iclass 14, count 0 2006.285.06:44:34.79#ibcon#about to read 3, iclass 14, count 0 2006.285.06:44:34.83#ibcon#read 3, iclass 14, count 0 2006.285.06:44:34.83#ibcon#about to read 4, iclass 14, count 0 2006.285.06:44:34.83#ibcon#read 4, iclass 14, count 0 2006.285.06:44:34.83#ibcon#about to read 5, iclass 14, count 0 2006.285.06:44:34.83#ibcon#read 5, iclass 14, count 0 2006.285.06:44:34.83#ibcon#about to read 6, iclass 14, count 0 2006.285.06:44:34.83#ibcon#read 6, iclass 14, count 0 2006.285.06:44:34.83#ibcon#end of sib2, iclass 14, count 0 2006.285.06:44:34.83#ibcon#*after write, iclass 14, count 0 2006.285.06:44:34.83#ibcon#*before return 0, iclass 14, count 0 2006.285.06:44:34.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:44:34.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:44:34.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:44:34.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:44:34.83$vck44/va=2,6 2006.285.06:44:34.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.06:44:34.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.06:44:34.83#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:34.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:44:34.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:44:34.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:44:34.89#ibcon#enter wrdev, iclass 16, count 2 2006.285.06:44:34.89#ibcon#first serial, iclass 16, count 2 2006.285.06:44:34.89#ibcon#enter sib2, iclass 16, count 2 2006.285.06:44:34.89#ibcon#flushed, iclass 16, count 2 2006.285.06:44:34.89#ibcon#about to write, iclass 16, count 2 2006.285.06:44:34.89#ibcon#wrote, iclass 16, count 2 2006.285.06:44:34.89#ibcon#about to read 3, iclass 16, count 2 2006.285.06:44:34.91#ibcon#read 3, iclass 16, count 2 2006.285.06:44:34.91#ibcon#about to read 4, iclass 16, count 2 2006.285.06:44:34.91#ibcon#read 4, iclass 16, count 2 2006.285.06:44:34.91#ibcon#about to read 5, iclass 16, count 2 2006.285.06:44:34.91#ibcon#read 5, iclass 16, count 2 2006.285.06:44:34.91#ibcon#about to read 6, iclass 16, count 2 2006.285.06:44:34.91#ibcon#read 6, iclass 16, count 2 2006.285.06:44:34.91#ibcon#end of sib2, iclass 16, count 2 2006.285.06:44:34.91#ibcon#*mode == 0, iclass 16, count 2 2006.285.06:44:34.91#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.06:44:34.91#ibcon#[25=AT02-06\r\n] 2006.285.06:44:34.91#ibcon#*before write, iclass 16, count 2 2006.285.06:44:34.91#ibcon#enter sib2, iclass 16, count 2 2006.285.06:44:34.91#ibcon#flushed, iclass 16, count 2 2006.285.06:44:34.91#ibcon#about to write, iclass 16, count 2 2006.285.06:44:34.91#ibcon#wrote, iclass 16, count 2 2006.285.06:44:34.91#ibcon#about to read 3, iclass 16, count 2 2006.285.06:44:34.94#ibcon#read 3, iclass 16, count 2 2006.285.06:44:34.94#ibcon#about to read 4, iclass 16, count 2 2006.285.06:44:34.94#ibcon#read 4, iclass 16, count 2 2006.285.06:44:34.94#ibcon#about to read 5, iclass 16, count 2 2006.285.06:44:34.94#ibcon#read 5, iclass 16, count 2 2006.285.06:44:34.94#ibcon#about to read 6, iclass 16, count 2 2006.285.06:44:34.94#ibcon#read 6, iclass 16, count 2 2006.285.06:44:34.94#ibcon#end of sib2, iclass 16, count 2 2006.285.06:44:34.94#ibcon#*after write, iclass 16, count 2 2006.285.06:44:34.94#ibcon#*before return 0, iclass 16, count 2 2006.285.06:44:34.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:44:34.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:44:34.94#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.06:44:34.94#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:34.94#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:44:35.06#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:44:35.06#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:44:35.06#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:44:35.06#ibcon#first serial, iclass 16, count 0 2006.285.06:44:35.06#ibcon#enter sib2, iclass 16, count 0 2006.285.06:44:35.06#ibcon#flushed, iclass 16, count 0 2006.285.06:44:35.06#ibcon#about to write, iclass 16, count 0 2006.285.06:44:35.06#ibcon#wrote, iclass 16, count 0 2006.285.06:44:35.06#ibcon#about to read 3, iclass 16, count 0 2006.285.06:44:35.08#ibcon#read 3, iclass 16, count 0 2006.285.06:44:35.08#ibcon#about to read 4, iclass 16, count 0 2006.285.06:44:35.08#ibcon#read 4, iclass 16, count 0 2006.285.06:44:35.08#ibcon#about to read 5, iclass 16, count 0 2006.285.06:44:35.08#ibcon#read 5, iclass 16, count 0 2006.285.06:44:35.08#ibcon#about to read 6, iclass 16, count 0 2006.285.06:44:35.08#ibcon#read 6, iclass 16, count 0 2006.285.06:44:35.08#ibcon#end of sib2, iclass 16, count 0 2006.285.06:44:35.08#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:44:35.08#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:44:35.08#ibcon#[25=USB\r\n] 2006.285.06:44:35.08#ibcon#*before write, iclass 16, count 0 2006.285.06:44:35.08#ibcon#enter sib2, iclass 16, count 0 2006.285.06:44:35.08#ibcon#flushed, iclass 16, count 0 2006.285.06:44:35.08#ibcon#about to write, iclass 16, count 0 2006.285.06:44:35.08#ibcon#wrote, iclass 16, count 0 2006.285.06:44:35.08#ibcon#about to read 3, iclass 16, count 0 2006.285.06:44:35.11#ibcon#read 3, iclass 16, count 0 2006.285.06:44:35.11#ibcon#about to read 4, iclass 16, count 0 2006.285.06:44:35.11#ibcon#read 4, iclass 16, count 0 2006.285.06:44:35.11#ibcon#about to read 5, iclass 16, count 0 2006.285.06:44:35.11#ibcon#read 5, iclass 16, count 0 2006.285.06:44:35.11#ibcon#about to read 6, iclass 16, count 0 2006.285.06:44:35.11#ibcon#read 6, iclass 16, count 0 2006.285.06:44:35.11#ibcon#end of sib2, iclass 16, count 0 2006.285.06:44:35.11#ibcon#*after write, iclass 16, count 0 2006.285.06:44:35.11#ibcon#*before return 0, iclass 16, count 0 2006.285.06:44:35.11#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:44:35.11#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:44:35.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:44:35.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:44:35.11$vck44/valo=3,564.99 2006.285.06:44:35.11#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.06:44:35.11#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.06:44:35.11#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:35.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:44:35.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:44:35.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:44:35.11#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:44:35.11#ibcon#first serial, iclass 18, count 0 2006.285.06:44:35.11#ibcon#enter sib2, iclass 18, count 0 2006.285.06:44:35.11#ibcon#flushed, iclass 18, count 0 2006.285.06:44:35.11#ibcon#about to write, iclass 18, count 0 2006.285.06:44:35.11#ibcon#wrote, iclass 18, count 0 2006.285.06:44:35.11#ibcon#about to read 3, iclass 18, count 0 2006.285.06:44:35.13#ibcon#read 3, iclass 18, count 0 2006.285.06:44:35.13#ibcon#about to read 4, iclass 18, count 0 2006.285.06:44:35.13#ibcon#read 4, iclass 18, count 0 2006.285.06:44:35.13#ibcon#about to read 5, iclass 18, count 0 2006.285.06:44:35.13#ibcon#read 5, iclass 18, count 0 2006.285.06:44:35.13#ibcon#about to read 6, iclass 18, count 0 2006.285.06:44:35.13#ibcon#read 6, iclass 18, count 0 2006.285.06:44:35.13#ibcon#end of sib2, iclass 18, count 0 2006.285.06:44:35.13#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:44:35.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:44:35.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:44:35.13#ibcon#*before write, iclass 18, count 0 2006.285.06:44:35.13#ibcon#enter sib2, iclass 18, count 0 2006.285.06:44:35.13#ibcon#flushed, iclass 18, count 0 2006.285.06:44:35.13#ibcon#about to write, iclass 18, count 0 2006.285.06:44:35.13#ibcon#wrote, iclass 18, count 0 2006.285.06:44:35.13#ibcon#about to read 3, iclass 18, count 0 2006.285.06:44:35.17#ibcon#read 3, iclass 18, count 0 2006.285.06:44:35.17#ibcon#about to read 4, iclass 18, count 0 2006.285.06:44:35.17#ibcon#read 4, iclass 18, count 0 2006.285.06:44:35.17#ibcon#about to read 5, iclass 18, count 0 2006.285.06:44:35.17#ibcon#read 5, iclass 18, count 0 2006.285.06:44:35.17#ibcon#about to read 6, iclass 18, count 0 2006.285.06:44:35.17#ibcon#read 6, iclass 18, count 0 2006.285.06:44:35.17#ibcon#end of sib2, iclass 18, count 0 2006.285.06:44:35.17#ibcon#*after write, iclass 18, count 0 2006.285.06:44:35.17#ibcon#*before return 0, iclass 18, count 0 2006.285.06:44:35.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:44:35.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:44:35.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:44:35.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:44:35.17$vck44/va=3,7 2006.285.06:44:35.17#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.06:44:35.17#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.06:44:35.17#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:35.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:44:35.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:44:35.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:44:35.23#ibcon#enter wrdev, iclass 20, count 2 2006.285.06:44:35.23#ibcon#first serial, iclass 20, count 2 2006.285.06:44:35.23#ibcon#enter sib2, iclass 20, count 2 2006.285.06:44:35.23#ibcon#flushed, iclass 20, count 2 2006.285.06:44:35.23#ibcon#about to write, iclass 20, count 2 2006.285.06:44:35.23#ibcon#wrote, iclass 20, count 2 2006.285.06:44:35.23#ibcon#about to read 3, iclass 20, count 2 2006.285.06:44:35.25#ibcon#read 3, iclass 20, count 2 2006.285.06:44:35.25#ibcon#about to read 4, iclass 20, count 2 2006.285.06:44:35.25#ibcon#read 4, iclass 20, count 2 2006.285.06:44:35.25#ibcon#about to read 5, iclass 20, count 2 2006.285.06:44:35.25#ibcon#read 5, iclass 20, count 2 2006.285.06:44:35.25#ibcon#about to read 6, iclass 20, count 2 2006.285.06:44:35.25#ibcon#read 6, iclass 20, count 2 2006.285.06:44:35.25#ibcon#end of sib2, iclass 20, count 2 2006.285.06:44:35.25#ibcon#*mode == 0, iclass 20, count 2 2006.285.06:44:35.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.06:44:35.25#ibcon#[25=AT03-07\r\n] 2006.285.06:44:35.25#ibcon#*before write, iclass 20, count 2 2006.285.06:44:35.25#ibcon#enter sib2, iclass 20, count 2 2006.285.06:44:35.25#ibcon#flushed, iclass 20, count 2 2006.285.06:44:35.25#ibcon#about to write, iclass 20, count 2 2006.285.06:44:35.25#ibcon#wrote, iclass 20, count 2 2006.285.06:44:35.25#ibcon#about to read 3, iclass 20, count 2 2006.285.06:44:35.28#ibcon#read 3, iclass 20, count 2 2006.285.06:44:35.28#ibcon#about to read 4, iclass 20, count 2 2006.285.06:44:35.28#ibcon#read 4, iclass 20, count 2 2006.285.06:44:35.28#ibcon#about to read 5, iclass 20, count 2 2006.285.06:44:35.28#ibcon#read 5, iclass 20, count 2 2006.285.06:44:35.28#ibcon#about to read 6, iclass 20, count 2 2006.285.06:44:35.28#ibcon#read 6, iclass 20, count 2 2006.285.06:44:35.28#ibcon#end of sib2, iclass 20, count 2 2006.285.06:44:35.28#ibcon#*after write, iclass 20, count 2 2006.285.06:44:35.28#ibcon#*before return 0, iclass 20, count 2 2006.285.06:44:35.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:44:35.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:44:35.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.06:44:35.28#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:35.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:44:35.41#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:44:35.41#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:44:35.41#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:44:35.41#ibcon#first serial, iclass 20, count 0 2006.285.06:44:35.41#ibcon#enter sib2, iclass 20, count 0 2006.285.06:44:35.41#ibcon#flushed, iclass 20, count 0 2006.285.06:44:35.41#ibcon#about to write, iclass 20, count 0 2006.285.06:44:35.41#ibcon#wrote, iclass 20, count 0 2006.285.06:44:35.41#ibcon#about to read 3, iclass 20, count 0 2006.285.06:44:35.43#ibcon#read 3, iclass 20, count 0 2006.285.06:44:35.43#ibcon#about to read 4, iclass 20, count 0 2006.285.06:44:35.43#ibcon#read 4, iclass 20, count 0 2006.285.06:44:35.43#ibcon#about to read 5, iclass 20, count 0 2006.285.06:44:35.43#ibcon#read 5, iclass 20, count 0 2006.285.06:44:35.43#ibcon#about to read 6, iclass 20, count 0 2006.285.06:44:35.43#ibcon#read 6, iclass 20, count 0 2006.285.06:44:35.43#ibcon#end of sib2, iclass 20, count 0 2006.285.06:44:35.43#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:44:35.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:44:35.43#ibcon#[25=USB\r\n] 2006.285.06:44:35.43#ibcon#*before write, iclass 20, count 0 2006.285.06:44:35.43#ibcon#enter sib2, iclass 20, count 0 2006.285.06:44:35.43#ibcon#flushed, iclass 20, count 0 2006.285.06:44:35.43#ibcon#about to write, iclass 20, count 0 2006.285.06:44:35.43#ibcon#wrote, iclass 20, count 0 2006.285.06:44:35.43#ibcon#about to read 3, iclass 20, count 0 2006.285.06:44:35.46#ibcon#read 3, iclass 20, count 0 2006.285.06:44:35.46#ibcon#about to read 4, iclass 20, count 0 2006.285.06:44:35.46#ibcon#read 4, iclass 20, count 0 2006.285.06:44:35.46#ibcon#about to read 5, iclass 20, count 0 2006.285.06:44:35.46#ibcon#read 5, iclass 20, count 0 2006.285.06:44:35.46#ibcon#about to read 6, iclass 20, count 0 2006.285.06:44:35.46#ibcon#read 6, iclass 20, count 0 2006.285.06:44:35.46#ibcon#end of sib2, iclass 20, count 0 2006.285.06:44:35.46#ibcon#*after write, iclass 20, count 0 2006.285.06:44:35.46#ibcon#*before return 0, iclass 20, count 0 2006.285.06:44:35.46#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:44:35.46#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:44:35.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:44:35.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:44:35.46$vck44/valo=4,624.99 2006.285.06:44:35.46#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.06:44:35.46#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.06:44:35.46#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:35.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:44:35.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:44:35.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:44:35.46#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:44:35.46#ibcon#first serial, iclass 22, count 0 2006.285.06:44:35.46#ibcon#enter sib2, iclass 22, count 0 2006.285.06:44:35.46#ibcon#flushed, iclass 22, count 0 2006.285.06:44:35.46#ibcon#about to write, iclass 22, count 0 2006.285.06:44:35.46#ibcon#wrote, iclass 22, count 0 2006.285.06:44:35.46#ibcon#about to read 3, iclass 22, count 0 2006.285.06:44:35.48#ibcon#read 3, iclass 22, count 0 2006.285.06:44:35.48#ibcon#about to read 4, iclass 22, count 0 2006.285.06:44:35.48#ibcon#read 4, iclass 22, count 0 2006.285.06:44:35.48#ibcon#about to read 5, iclass 22, count 0 2006.285.06:44:35.48#ibcon#read 5, iclass 22, count 0 2006.285.06:44:35.48#ibcon#about to read 6, iclass 22, count 0 2006.285.06:44:35.48#ibcon#read 6, iclass 22, count 0 2006.285.06:44:35.48#ibcon#end of sib2, iclass 22, count 0 2006.285.06:44:35.48#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:44:35.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:44:35.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:44:35.48#ibcon#*before write, iclass 22, count 0 2006.285.06:44:35.48#ibcon#enter sib2, iclass 22, count 0 2006.285.06:44:35.48#ibcon#flushed, iclass 22, count 0 2006.285.06:44:35.48#ibcon#about to write, iclass 22, count 0 2006.285.06:44:35.48#ibcon#wrote, iclass 22, count 0 2006.285.06:44:35.48#ibcon#about to read 3, iclass 22, count 0 2006.285.06:44:35.52#ibcon#read 3, iclass 22, count 0 2006.285.06:44:35.52#ibcon#about to read 4, iclass 22, count 0 2006.285.06:44:35.52#ibcon#read 4, iclass 22, count 0 2006.285.06:44:35.52#ibcon#about to read 5, iclass 22, count 0 2006.285.06:44:35.52#ibcon#read 5, iclass 22, count 0 2006.285.06:44:35.52#ibcon#about to read 6, iclass 22, count 0 2006.285.06:44:35.52#ibcon#read 6, iclass 22, count 0 2006.285.06:44:35.52#ibcon#end of sib2, iclass 22, count 0 2006.285.06:44:35.52#ibcon#*after write, iclass 22, count 0 2006.285.06:44:35.52#ibcon#*before return 0, iclass 22, count 0 2006.285.06:44:35.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:44:35.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:44:35.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:44:35.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:44:35.52$vck44/va=4,6 2006.285.06:44:35.52#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.06:44:35.52#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.06:44:35.52#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:35.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:44:35.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:44:35.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:44:35.58#ibcon#enter wrdev, iclass 24, count 2 2006.285.06:44:35.58#ibcon#first serial, iclass 24, count 2 2006.285.06:44:35.58#ibcon#enter sib2, iclass 24, count 2 2006.285.06:44:35.58#ibcon#flushed, iclass 24, count 2 2006.285.06:44:35.58#ibcon#about to write, iclass 24, count 2 2006.285.06:44:35.58#ibcon#wrote, iclass 24, count 2 2006.285.06:44:35.58#ibcon#about to read 3, iclass 24, count 2 2006.285.06:44:35.60#ibcon#read 3, iclass 24, count 2 2006.285.06:44:35.60#ibcon#about to read 4, iclass 24, count 2 2006.285.06:44:35.60#ibcon#read 4, iclass 24, count 2 2006.285.06:44:35.60#ibcon#about to read 5, iclass 24, count 2 2006.285.06:44:35.60#ibcon#read 5, iclass 24, count 2 2006.285.06:44:35.60#ibcon#about to read 6, iclass 24, count 2 2006.285.06:44:35.60#ibcon#read 6, iclass 24, count 2 2006.285.06:44:35.60#ibcon#end of sib2, iclass 24, count 2 2006.285.06:44:35.60#ibcon#*mode == 0, iclass 24, count 2 2006.285.06:44:35.60#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.06:44:35.60#ibcon#[25=AT04-06\r\n] 2006.285.06:44:35.60#ibcon#*before write, iclass 24, count 2 2006.285.06:44:35.60#ibcon#enter sib2, iclass 24, count 2 2006.285.06:44:35.60#ibcon#flushed, iclass 24, count 2 2006.285.06:44:35.60#ibcon#about to write, iclass 24, count 2 2006.285.06:44:35.60#ibcon#wrote, iclass 24, count 2 2006.285.06:44:35.60#ibcon#about to read 3, iclass 24, count 2 2006.285.06:44:35.63#ibcon#read 3, iclass 24, count 2 2006.285.06:44:35.63#ibcon#about to read 4, iclass 24, count 2 2006.285.06:44:35.63#ibcon#read 4, iclass 24, count 2 2006.285.06:44:35.63#ibcon#about to read 5, iclass 24, count 2 2006.285.06:44:35.63#ibcon#read 5, iclass 24, count 2 2006.285.06:44:35.63#ibcon#about to read 6, iclass 24, count 2 2006.285.06:44:35.63#ibcon#read 6, iclass 24, count 2 2006.285.06:44:35.63#ibcon#end of sib2, iclass 24, count 2 2006.285.06:44:35.63#ibcon#*after write, iclass 24, count 2 2006.285.06:44:35.63#ibcon#*before return 0, iclass 24, count 2 2006.285.06:44:35.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:44:35.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:44:35.63#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.06:44:35.63#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:35.63#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:44:35.75#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:44:35.75#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:44:35.75#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:44:35.75#ibcon#first serial, iclass 24, count 0 2006.285.06:44:35.75#ibcon#enter sib2, iclass 24, count 0 2006.285.06:44:35.75#ibcon#flushed, iclass 24, count 0 2006.285.06:44:35.75#ibcon#about to write, iclass 24, count 0 2006.285.06:44:35.75#ibcon#wrote, iclass 24, count 0 2006.285.06:44:35.75#ibcon#about to read 3, iclass 24, count 0 2006.285.06:44:35.77#ibcon#read 3, iclass 24, count 0 2006.285.06:44:35.77#ibcon#about to read 4, iclass 24, count 0 2006.285.06:44:35.77#ibcon#read 4, iclass 24, count 0 2006.285.06:44:35.77#ibcon#about to read 5, iclass 24, count 0 2006.285.06:44:35.77#ibcon#read 5, iclass 24, count 0 2006.285.06:44:35.77#ibcon#about to read 6, iclass 24, count 0 2006.285.06:44:35.77#ibcon#read 6, iclass 24, count 0 2006.285.06:44:35.77#ibcon#end of sib2, iclass 24, count 0 2006.285.06:44:35.77#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:44:35.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:44:35.77#ibcon#[25=USB\r\n] 2006.285.06:44:35.77#ibcon#*before write, iclass 24, count 0 2006.285.06:44:35.77#ibcon#enter sib2, iclass 24, count 0 2006.285.06:44:35.77#ibcon#flushed, iclass 24, count 0 2006.285.06:44:35.77#ibcon#about to write, iclass 24, count 0 2006.285.06:44:35.77#ibcon#wrote, iclass 24, count 0 2006.285.06:44:35.77#ibcon#about to read 3, iclass 24, count 0 2006.285.06:44:35.80#ibcon#read 3, iclass 24, count 0 2006.285.06:44:35.80#ibcon#about to read 4, iclass 24, count 0 2006.285.06:44:35.80#ibcon#read 4, iclass 24, count 0 2006.285.06:44:35.80#ibcon#about to read 5, iclass 24, count 0 2006.285.06:44:35.80#ibcon#read 5, iclass 24, count 0 2006.285.06:44:35.80#ibcon#about to read 6, iclass 24, count 0 2006.285.06:44:35.80#ibcon#read 6, iclass 24, count 0 2006.285.06:44:35.80#ibcon#end of sib2, iclass 24, count 0 2006.285.06:44:35.80#ibcon#*after write, iclass 24, count 0 2006.285.06:44:35.80#ibcon#*before return 0, iclass 24, count 0 2006.285.06:44:35.80#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:44:35.80#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:44:35.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:44:35.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:44:35.80$vck44/valo=5,734.99 2006.285.06:44:35.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.06:44:35.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.06:44:35.80#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:35.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:44:35.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:44:35.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:44:35.80#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:44:35.80#ibcon#first serial, iclass 26, count 0 2006.285.06:44:35.80#ibcon#enter sib2, iclass 26, count 0 2006.285.06:44:35.80#ibcon#flushed, iclass 26, count 0 2006.285.06:44:35.80#ibcon#about to write, iclass 26, count 0 2006.285.06:44:35.80#ibcon#wrote, iclass 26, count 0 2006.285.06:44:35.80#ibcon#about to read 3, iclass 26, count 0 2006.285.06:44:35.82#ibcon#read 3, iclass 26, count 0 2006.285.06:44:35.82#ibcon#about to read 4, iclass 26, count 0 2006.285.06:44:35.82#ibcon#read 4, iclass 26, count 0 2006.285.06:44:35.82#ibcon#about to read 5, iclass 26, count 0 2006.285.06:44:35.82#ibcon#read 5, iclass 26, count 0 2006.285.06:44:35.82#ibcon#about to read 6, iclass 26, count 0 2006.285.06:44:35.82#ibcon#read 6, iclass 26, count 0 2006.285.06:44:35.82#ibcon#end of sib2, iclass 26, count 0 2006.285.06:44:35.82#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:44:35.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:44:35.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:44:35.82#ibcon#*before write, iclass 26, count 0 2006.285.06:44:35.82#ibcon#enter sib2, iclass 26, count 0 2006.285.06:44:35.82#ibcon#flushed, iclass 26, count 0 2006.285.06:44:35.82#ibcon#about to write, iclass 26, count 0 2006.285.06:44:35.82#ibcon#wrote, iclass 26, count 0 2006.285.06:44:35.82#ibcon#about to read 3, iclass 26, count 0 2006.285.06:44:35.86#ibcon#read 3, iclass 26, count 0 2006.285.06:44:35.86#ibcon#about to read 4, iclass 26, count 0 2006.285.06:44:35.86#ibcon#read 4, iclass 26, count 0 2006.285.06:44:35.86#ibcon#about to read 5, iclass 26, count 0 2006.285.06:44:35.86#ibcon#read 5, iclass 26, count 0 2006.285.06:44:35.86#ibcon#about to read 6, iclass 26, count 0 2006.285.06:44:35.86#ibcon#read 6, iclass 26, count 0 2006.285.06:44:35.86#ibcon#end of sib2, iclass 26, count 0 2006.285.06:44:35.86#ibcon#*after write, iclass 26, count 0 2006.285.06:44:35.86#ibcon#*before return 0, iclass 26, count 0 2006.285.06:44:35.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:44:35.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:44:35.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:44:35.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:44:35.86$vck44/va=5,3 2006.285.06:44:35.86#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.06:44:35.86#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.06:44:35.86#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:35.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:44:35.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:44:35.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:44:35.92#ibcon#enter wrdev, iclass 28, count 2 2006.285.06:44:35.92#ibcon#first serial, iclass 28, count 2 2006.285.06:44:35.92#ibcon#enter sib2, iclass 28, count 2 2006.285.06:44:35.92#ibcon#flushed, iclass 28, count 2 2006.285.06:44:35.92#ibcon#about to write, iclass 28, count 2 2006.285.06:44:35.92#ibcon#wrote, iclass 28, count 2 2006.285.06:44:35.92#ibcon#about to read 3, iclass 28, count 2 2006.285.06:44:35.94#ibcon#read 3, iclass 28, count 2 2006.285.06:44:35.94#ibcon#about to read 4, iclass 28, count 2 2006.285.06:44:35.94#ibcon#read 4, iclass 28, count 2 2006.285.06:44:35.94#ibcon#about to read 5, iclass 28, count 2 2006.285.06:44:35.94#ibcon#read 5, iclass 28, count 2 2006.285.06:44:35.94#ibcon#about to read 6, iclass 28, count 2 2006.285.06:44:35.94#ibcon#read 6, iclass 28, count 2 2006.285.06:44:35.94#ibcon#end of sib2, iclass 28, count 2 2006.285.06:44:35.94#ibcon#*mode == 0, iclass 28, count 2 2006.285.06:44:35.94#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.06:44:35.94#ibcon#[25=AT05-03\r\n] 2006.285.06:44:35.94#ibcon#*before write, iclass 28, count 2 2006.285.06:44:35.94#ibcon#enter sib2, iclass 28, count 2 2006.285.06:44:35.94#ibcon#flushed, iclass 28, count 2 2006.285.06:44:35.94#ibcon#about to write, iclass 28, count 2 2006.285.06:44:35.94#ibcon#wrote, iclass 28, count 2 2006.285.06:44:35.94#ibcon#about to read 3, iclass 28, count 2 2006.285.06:44:35.97#ibcon#read 3, iclass 28, count 2 2006.285.06:44:35.97#ibcon#about to read 4, iclass 28, count 2 2006.285.06:44:35.97#ibcon#read 4, iclass 28, count 2 2006.285.06:44:35.97#ibcon#about to read 5, iclass 28, count 2 2006.285.06:44:35.97#ibcon#read 5, iclass 28, count 2 2006.285.06:44:35.97#ibcon#about to read 6, iclass 28, count 2 2006.285.06:44:35.97#ibcon#read 6, iclass 28, count 2 2006.285.06:44:35.97#ibcon#end of sib2, iclass 28, count 2 2006.285.06:44:35.97#ibcon#*after write, iclass 28, count 2 2006.285.06:44:35.97#ibcon#*before return 0, iclass 28, count 2 2006.285.06:44:35.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:44:35.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:44:35.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.06:44:35.97#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:35.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:44:36.09#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:44:36.09#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:44:36.09#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:44:36.09#ibcon#first serial, iclass 28, count 0 2006.285.06:44:36.09#ibcon#enter sib2, iclass 28, count 0 2006.285.06:44:36.09#ibcon#flushed, iclass 28, count 0 2006.285.06:44:36.09#ibcon#about to write, iclass 28, count 0 2006.285.06:44:36.09#ibcon#wrote, iclass 28, count 0 2006.285.06:44:36.09#ibcon#about to read 3, iclass 28, count 0 2006.285.06:44:36.11#ibcon#read 3, iclass 28, count 0 2006.285.06:44:36.11#ibcon#about to read 4, iclass 28, count 0 2006.285.06:44:36.11#ibcon#read 4, iclass 28, count 0 2006.285.06:44:36.11#ibcon#about to read 5, iclass 28, count 0 2006.285.06:44:36.11#ibcon#read 5, iclass 28, count 0 2006.285.06:44:36.11#ibcon#about to read 6, iclass 28, count 0 2006.285.06:44:36.11#ibcon#read 6, iclass 28, count 0 2006.285.06:44:36.11#ibcon#end of sib2, iclass 28, count 0 2006.285.06:44:36.11#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:44:36.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:44:36.11#ibcon#[25=USB\r\n] 2006.285.06:44:36.11#ibcon#*before write, iclass 28, count 0 2006.285.06:44:36.11#ibcon#enter sib2, iclass 28, count 0 2006.285.06:44:36.11#ibcon#flushed, iclass 28, count 0 2006.285.06:44:36.11#ibcon#about to write, iclass 28, count 0 2006.285.06:44:36.11#ibcon#wrote, iclass 28, count 0 2006.285.06:44:36.11#ibcon#about to read 3, iclass 28, count 0 2006.285.06:44:36.14#ibcon#read 3, iclass 28, count 0 2006.285.06:44:36.14#ibcon#about to read 4, iclass 28, count 0 2006.285.06:44:36.14#ibcon#read 4, iclass 28, count 0 2006.285.06:44:36.14#ibcon#about to read 5, iclass 28, count 0 2006.285.06:44:36.14#ibcon#read 5, iclass 28, count 0 2006.285.06:44:36.14#ibcon#about to read 6, iclass 28, count 0 2006.285.06:44:36.14#ibcon#read 6, iclass 28, count 0 2006.285.06:44:36.14#ibcon#end of sib2, iclass 28, count 0 2006.285.06:44:36.14#ibcon#*after write, iclass 28, count 0 2006.285.06:44:36.14#ibcon#*before return 0, iclass 28, count 0 2006.285.06:44:36.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:44:36.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:44:36.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:44:36.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:44:36.14$vck44/valo=6,814.99 2006.285.06:44:36.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.06:44:36.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.06:44:36.14#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:36.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:44:36.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:44:36.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:44:36.14#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:44:36.14#ibcon#first serial, iclass 30, count 0 2006.285.06:44:36.14#ibcon#enter sib2, iclass 30, count 0 2006.285.06:44:36.14#ibcon#flushed, iclass 30, count 0 2006.285.06:44:36.14#ibcon#about to write, iclass 30, count 0 2006.285.06:44:36.14#ibcon#wrote, iclass 30, count 0 2006.285.06:44:36.14#ibcon#about to read 3, iclass 30, count 0 2006.285.06:44:36.16#ibcon#read 3, iclass 30, count 0 2006.285.06:44:36.16#ibcon#about to read 4, iclass 30, count 0 2006.285.06:44:36.16#ibcon#read 4, iclass 30, count 0 2006.285.06:44:36.16#ibcon#about to read 5, iclass 30, count 0 2006.285.06:44:36.16#ibcon#read 5, iclass 30, count 0 2006.285.06:44:36.16#ibcon#about to read 6, iclass 30, count 0 2006.285.06:44:36.16#ibcon#read 6, iclass 30, count 0 2006.285.06:44:36.16#ibcon#end of sib2, iclass 30, count 0 2006.285.06:44:36.16#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:44:36.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:44:36.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:44:36.16#ibcon#*before write, iclass 30, count 0 2006.285.06:44:36.16#ibcon#enter sib2, iclass 30, count 0 2006.285.06:44:36.16#ibcon#flushed, iclass 30, count 0 2006.285.06:44:36.16#ibcon#about to write, iclass 30, count 0 2006.285.06:44:36.16#ibcon#wrote, iclass 30, count 0 2006.285.06:44:36.16#ibcon#about to read 3, iclass 30, count 0 2006.285.06:44:36.20#ibcon#read 3, iclass 30, count 0 2006.285.06:44:36.20#ibcon#about to read 4, iclass 30, count 0 2006.285.06:44:36.20#ibcon#read 4, iclass 30, count 0 2006.285.06:44:36.20#ibcon#about to read 5, iclass 30, count 0 2006.285.06:44:36.20#ibcon#read 5, iclass 30, count 0 2006.285.06:44:36.20#ibcon#about to read 6, iclass 30, count 0 2006.285.06:44:36.20#ibcon#read 6, iclass 30, count 0 2006.285.06:44:36.20#ibcon#end of sib2, iclass 30, count 0 2006.285.06:44:36.20#ibcon#*after write, iclass 30, count 0 2006.285.06:44:36.20#ibcon#*before return 0, iclass 30, count 0 2006.285.06:44:36.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:44:36.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:44:36.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:44:36.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:44:36.20$vck44/va=6,4 2006.285.06:44:36.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.06:44:36.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.06:44:36.20#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:36.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:44:36.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:44:36.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:44:36.26#ibcon#enter wrdev, iclass 32, count 2 2006.285.06:44:36.26#ibcon#first serial, iclass 32, count 2 2006.285.06:44:36.26#ibcon#enter sib2, iclass 32, count 2 2006.285.06:44:36.26#ibcon#flushed, iclass 32, count 2 2006.285.06:44:36.26#ibcon#about to write, iclass 32, count 2 2006.285.06:44:36.26#ibcon#wrote, iclass 32, count 2 2006.285.06:44:36.26#ibcon#about to read 3, iclass 32, count 2 2006.285.06:44:36.28#ibcon#read 3, iclass 32, count 2 2006.285.06:44:36.28#ibcon#about to read 4, iclass 32, count 2 2006.285.06:44:36.28#ibcon#read 4, iclass 32, count 2 2006.285.06:44:36.28#ibcon#about to read 5, iclass 32, count 2 2006.285.06:44:36.28#ibcon#read 5, iclass 32, count 2 2006.285.06:44:36.28#ibcon#about to read 6, iclass 32, count 2 2006.285.06:44:36.28#ibcon#read 6, iclass 32, count 2 2006.285.06:44:36.28#ibcon#end of sib2, iclass 32, count 2 2006.285.06:44:36.28#ibcon#*mode == 0, iclass 32, count 2 2006.285.06:44:36.28#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.06:44:36.28#ibcon#[25=AT06-04\r\n] 2006.285.06:44:36.28#ibcon#*before write, iclass 32, count 2 2006.285.06:44:36.28#ibcon#enter sib2, iclass 32, count 2 2006.285.06:44:36.28#ibcon#flushed, iclass 32, count 2 2006.285.06:44:36.28#ibcon#about to write, iclass 32, count 2 2006.285.06:44:36.28#ibcon#wrote, iclass 32, count 2 2006.285.06:44:36.28#ibcon#about to read 3, iclass 32, count 2 2006.285.06:44:36.31#ibcon#read 3, iclass 32, count 2 2006.285.06:44:36.31#ibcon#about to read 4, iclass 32, count 2 2006.285.06:44:36.31#ibcon#read 4, iclass 32, count 2 2006.285.06:44:36.31#ibcon#about to read 5, iclass 32, count 2 2006.285.06:44:36.31#ibcon#read 5, iclass 32, count 2 2006.285.06:44:36.31#ibcon#about to read 6, iclass 32, count 2 2006.285.06:44:36.31#ibcon#read 6, iclass 32, count 2 2006.285.06:44:36.31#ibcon#end of sib2, iclass 32, count 2 2006.285.06:44:36.31#ibcon#*after write, iclass 32, count 2 2006.285.06:44:36.31#ibcon#*before return 0, iclass 32, count 2 2006.285.06:44:36.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:44:36.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:44:36.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.06:44:36.31#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:36.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:44:36.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:44:36.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:44:36.43#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:44:36.43#ibcon#first serial, iclass 32, count 0 2006.285.06:44:36.43#ibcon#enter sib2, iclass 32, count 0 2006.285.06:44:36.43#ibcon#flushed, iclass 32, count 0 2006.285.06:44:36.43#ibcon#about to write, iclass 32, count 0 2006.285.06:44:36.43#ibcon#wrote, iclass 32, count 0 2006.285.06:44:36.43#ibcon#about to read 3, iclass 32, count 0 2006.285.06:44:36.45#ibcon#read 3, iclass 32, count 0 2006.285.06:44:36.45#ibcon#about to read 4, iclass 32, count 0 2006.285.06:44:36.45#ibcon#read 4, iclass 32, count 0 2006.285.06:44:36.45#ibcon#about to read 5, iclass 32, count 0 2006.285.06:44:36.45#ibcon#read 5, iclass 32, count 0 2006.285.06:44:36.45#ibcon#about to read 6, iclass 32, count 0 2006.285.06:44:36.45#ibcon#read 6, iclass 32, count 0 2006.285.06:44:36.45#ibcon#end of sib2, iclass 32, count 0 2006.285.06:44:36.45#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:44:36.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:44:36.45#ibcon#[25=USB\r\n] 2006.285.06:44:36.45#ibcon#*before write, iclass 32, count 0 2006.285.06:44:36.45#ibcon#enter sib2, iclass 32, count 0 2006.285.06:44:36.45#ibcon#flushed, iclass 32, count 0 2006.285.06:44:36.45#ibcon#about to write, iclass 32, count 0 2006.285.06:44:36.45#ibcon#wrote, iclass 32, count 0 2006.285.06:44:36.45#ibcon#about to read 3, iclass 32, count 0 2006.285.06:44:36.48#ibcon#read 3, iclass 32, count 0 2006.285.06:44:36.48#ibcon#about to read 4, iclass 32, count 0 2006.285.06:44:36.48#ibcon#read 4, iclass 32, count 0 2006.285.06:44:36.48#ibcon#about to read 5, iclass 32, count 0 2006.285.06:44:36.48#ibcon#read 5, iclass 32, count 0 2006.285.06:44:36.48#ibcon#about to read 6, iclass 32, count 0 2006.285.06:44:36.48#ibcon#read 6, iclass 32, count 0 2006.285.06:44:36.48#ibcon#end of sib2, iclass 32, count 0 2006.285.06:44:36.48#ibcon#*after write, iclass 32, count 0 2006.285.06:44:36.48#ibcon#*before return 0, iclass 32, count 0 2006.285.06:44:36.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:44:36.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:44:36.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:44:36.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:44:36.48$vck44/valo=7,864.99 2006.285.06:44:36.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.06:44:36.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.06:44:36.48#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:36.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:44:36.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:44:36.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:44:36.48#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:44:36.48#ibcon#first serial, iclass 34, count 0 2006.285.06:44:36.48#ibcon#enter sib2, iclass 34, count 0 2006.285.06:44:36.48#ibcon#flushed, iclass 34, count 0 2006.285.06:44:36.48#ibcon#about to write, iclass 34, count 0 2006.285.06:44:36.48#ibcon#wrote, iclass 34, count 0 2006.285.06:44:36.48#ibcon#about to read 3, iclass 34, count 0 2006.285.06:44:36.50#ibcon#read 3, iclass 34, count 0 2006.285.06:44:36.50#ibcon#about to read 4, iclass 34, count 0 2006.285.06:44:36.50#ibcon#read 4, iclass 34, count 0 2006.285.06:44:36.50#ibcon#about to read 5, iclass 34, count 0 2006.285.06:44:36.50#ibcon#read 5, iclass 34, count 0 2006.285.06:44:36.50#ibcon#about to read 6, iclass 34, count 0 2006.285.06:44:36.50#ibcon#read 6, iclass 34, count 0 2006.285.06:44:36.50#ibcon#end of sib2, iclass 34, count 0 2006.285.06:44:36.50#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:44:36.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:44:36.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:44:36.50#ibcon#*before write, iclass 34, count 0 2006.285.06:44:36.50#ibcon#enter sib2, iclass 34, count 0 2006.285.06:44:36.50#ibcon#flushed, iclass 34, count 0 2006.285.06:44:36.50#ibcon#about to write, iclass 34, count 0 2006.285.06:44:36.50#ibcon#wrote, iclass 34, count 0 2006.285.06:44:36.50#ibcon#about to read 3, iclass 34, count 0 2006.285.06:44:36.54#ibcon#read 3, iclass 34, count 0 2006.285.06:44:36.54#ibcon#about to read 4, iclass 34, count 0 2006.285.06:44:36.54#ibcon#read 4, iclass 34, count 0 2006.285.06:44:36.54#ibcon#about to read 5, iclass 34, count 0 2006.285.06:44:36.54#ibcon#read 5, iclass 34, count 0 2006.285.06:44:36.54#ibcon#about to read 6, iclass 34, count 0 2006.285.06:44:36.54#ibcon#read 6, iclass 34, count 0 2006.285.06:44:36.54#ibcon#end of sib2, iclass 34, count 0 2006.285.06:44:36.54#ibcon#*after write, iclass 34, count 0 2006.285.06:44:36.54#ibcon#*before return 0, iclass 34, count 0 2006.285.06:44:36.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:44:36.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:44:36.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:44:36.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:44:36.54$vck44/va=7,4 2006.285.06:44:36.54#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.06:44:36.54#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.06:44:36.54#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:36.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:44:36.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:44:36.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:44:36.60#ibcon#enter wrdev, iclass 36, count 2 2006.285.06:44:36.60#ibcon#first serial, iclass 36, count 2 2006.285.06:44:36.60#ibcon#enter sib2, iclass 36, count 2 2006.285.06:44:36.60#ibcon#flushed, iclass 36, count 2 2006.285.06:44:36.60#ibcon#about to write, iclass 36, count 2 2006.285.06:44:36.60#ibcon#wrote, iclass 36, count 2 2006.285.06:44:36.60#ibcon#about to read 3, iclass 36, count 2 2006.285.06:44:36.62#ibcon#read 3, iclass 36, count 2 2006.285.06:44:36.62#ibcon#about to read 4, iclass 36, count 2 2006.285.06:44:36.62#ibcon#read 4, iclass 36, count 2 2006.285.06:44:36.62#ibcon#about to read 5, iclass 36, count 2 2006.285.06:44:36.62#ibcon#read 5, iclass 36, count 2 2006.285.06:44:36.62#ibcon#about to read 6, iclass 36, count 2 2006.285.06:44:36.62#ibcon#read 6, iclass 36, count 2 2006.285.06:44:36.62#ibcon#end of sib2, iclass 36, count 2 2006.285.06:44:36.62#ibcon#*mode == 0, iclass 36, count 2 2006.285.06:44:36.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.06:44:36.62#ibcon#[25=AT07-04\r\n] 2006.285.06:44:36.62#ibcon#*before write, iclass 36, count 2 2006.285.06:44:36.62#ibcon#enter sib2, iclass 36, count 2 2006.285.06:44:36.62#ibcon#flushed, iclass 36, count 2 2006.285.06:44:36.62#ibcon#about to write, iclass 36, count 2 2006.285.06:44:36.62#ibcon#wrote, iclass 36, count 2 2006.285.06:44:36.62#ibcon#about to read 3, iclass 36, count 2 2006.285.06:44:36.65#ibcon#read 3, iclass 36, count 2 2006.285.06:44:36.65#ibcon#about to read 4, iclass 36, count 2 2006.285.06:44:36.65#ibcon#read 4, iclass 36, count 2 2006.285.06:44:36.65#ibcon#about to read 5, iclass 36, count 2 2006.285.06:44:36.65#ibcon#read 5, iclass 36, count 2 2006.285.06:44:36.65#ibcon#about to read 6, iclass 36, count 2 2006.285.06:44:36.65#ibcon#read 6, iclass 36, count 2 2006.285.06:44:36.65#ibcon#end of sib2, iclass 36, count 2 2006.285.06:44:36.65#ibcon#*after write, iclass 36, count 2 2006.285.06:44:36.65#ibcon#*before return 0, iclass 36, count 2 2006.285.06:44:36.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:44:36.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:44:36.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.06:44:36.65#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:36.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:44:36.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:44:36.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:44:36.77#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:44:36.77#ibcon#first serial, iclass 36, count 0 2006.285.06:44:36.77#ibcon#enter sib2, iclass 36, count 0 2006.285.06:44:36.77#ibcon#flushed, iclass 36, count 0 2006.285.06:44:36.77#ibcon#about to write, iclass 36, count 0 2006.285.06:44:36.77#ibcon#wrote, iclass 36, count 0 2006.285.06:44:36.77#ibcon#about to read 3, iclass 36, count 0 2006.285.06:44:36.79#ibcon#read 3, iclass 36, count 0 2006.285.06:44:36.79#ibcon#about to read 4, iclass 36, count 0 2006.285.06:44:36.79#ibcon#read 4, iclass 36, count 0 2006.285.06:44:36.79#ibcon#about to read 5, iclass 36, count 0 2006.285.06:44:36.79#ibcon#read 5, iclass 36, count 0 2006.285.06:44:36.79#ibcon#about to read 6, iclass 36, count 0 2006.285.06:44:36.79#ibcon#read 6, iclass 36, count 0 2006.285.06:44:36.79#ibcon#end of sib2, iclass 36, count 0 2006.285.06:44:36.79#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:44:36.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:44:36.79#ibcon#[25=USB\r\n] 2006.285.06:44:36.79#ibcon#*before write, iclass 36, count 0 2006.285.06:44:36.79#ibcon#enter sib2, iclass 36, count 0 2006.285.06:44:36.79#ibcon#flushed, iclass 36, count 0 2006.285.06:44:36.79#ibcon#about to write, iclass 36, count 0 2006.285.06:44:36.79#ibcon#wrote, iclass 36, count 0 2006.285.06:44:36.79#ibcon#about to read 3, iclass 36, count 0 2006.285.06:44:36.82#ibcon#read 3, iclass 36, count 0 2006.285.06:44:36.82#ibcon#about to read 4, iclass 36, count 0 2006.285.06:44:36.82#ibcon#read 4, iclass 36, count 0 2006.285.06:44:36.82#ibcon#about to read 5, iclass 36, count 0 2006.285.06:44:36.82#ibcon#read 5, iclass 36, count 0 2006.285.06:44:36.82#ibcon#about to read 6, iclass 36, count 0 2006.285.06:44:36.82#ibcon#read 6, iclass 36, count 0 2006.285.06:44:36.82#ibcon#end of sib2, iclass 36, count 0 2006.285.06:44:36.82#ibcon#*after write, iclass 36, count 0 2006.285.06:44:36.82#ibcon#*before return 0, iclass 36, count 0 2006.285.06:44:36.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:44:36.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:44:36.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:44:36.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:44:36.82$vck44/valo=8,884.99 2006.285.06:44:36.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.06:44:36.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.06:44:36.82#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:36.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:44:36.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:44:36.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:44:36.82#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:44:36.82#ibcon#first serial, iclass 38, count 0 2006.285.06:44:36.82#ibcon#enter sib2, iclass 38, count 0 2006.285.06:44:36.82#ibcon#flushed, iclass 38, count 0 2006.285.06:44:36.82#ibcon#about to write, iclass 38, count 0 2006.285.06:44:36.82#ibcon#wrote, iclass 38, count 0 2006.285.06:44:36.82#ibcon#about to read 3, iclass 38, count 0 2006.285.06:44:36.84#ibcon#read 3, iclass 38, count 0 2006.285.06:44:36.84#ibcon#about to read 4, iclass 38, count 0 2006.285.06:44:36.84#ibcon#read 4, iclass 38, count 0 2006.285.06:44:36.84#ibcon#about to read 5, iclass 38, count 0 2006.285.06:44:36.84#ibcon#read 5, iclass 38, count 0 2006.285.06:44:36.84#ibcon#about to read 6, iclass 38, count 0 2006.285.06:44:36.84#ibcon#read 6, iclass 38, count 0 2006.285.06:44:36.84#ibcon#end of sib2, iclass 38, count 0 2006.285.06:44:36.84#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:44:36.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:44:36.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:44:36.84#ibcon#*before write, iclass 38, count 0 2006.285.06:44:36.84#ibcon#enter sib2, iclass 38, count 0 2006.285.06:44:36.84#ibcon#flushed, iclass 38, count 0 2006.285.06:44:36.84#ibcon#about to write, iclass 38, count 0 2006.285.06:44:36.84#ibcon#wrote, iclass 38, count 0 2006.285.06:44:36.84#ibcon#about to read 3, iclass 38, count 0 2006.285.06:44:36.88#ibcon#read 3, iclass 38, count 0 2006.285.06:44:36.88#ibcon#about to read 4, iclass 38, count 0 2006.285.06:44:36.88#ibcon#read 4, iclass 38, count 0 2006.285.06:44:36.88#ibcon#about to read 5, iclass 38, count 0 2006.285.06:44:36.88#ibcon#read 5, iclass 38, count 0 2006.285.06:44:36.88#ibcon#about to read 6, iclass 38, count 0 2006.285.06:44:36.88#ibcon#read 6, iclass 38, count 0 2006.285.06:44:36.88#ibcon#end of sib2, iclass 38, count 0 2006.285.06:44:36.88#ibcon#*after write, iclass 38, count 0 2006.285.06:44:36.88#ibcon#*before return 0, iclass 38, count 0 2006.285.06:44:36.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:44:36.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:44:36.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:44:36.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:44:36.88$vck44/va=8,3 2006.285.06:44:36.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.06:44:36.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.06:44:36.88#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:36.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:44:36.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:44:36.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:44:36.94#ibcon#enter wrdev, iclass 40, count 2 2006.285.06:44:36.94#ibcon#first serial, iclass 40, count 2 2006.285.06:44:36.94#ibcon#enter sib2, iclass 40, count 2 2006.285.06:44:36.94#ibcon#flushed, iclass 40, count 2 2006.285.06:44:36.94#ibcon#about to write, iclass 40, count 2 2006.285.06:44:36.94#ibcon#wrote, iclass 40, count 2 2006.285.06:44:36.94#ibcon#about to read 3, iclass 40, count 2 2006.285.06:44:36.96#ibcon#read 3, iclass 40, count 2 2006.285.06:44:36.96#ibcon#about to read 4, iclass 40, count 2 2006.285.06:44:36.96#ibcon#read 4, iclass 40, count 2 2006.285.06:44:36.96#ibcon#about to read 5, iclass 40, count 2 2006.285.06:44:36.96#ibcon#read 5, iclass 40, count 2 2006.285.06:44:36.96#ibcon#about to read 6, iclass 40, count 2 2006.285.06:44:36.96#ibcon#read 6, iclass 40, count 2 2006.285.06:44:36.96#ibcon#end of sib2, iclass 40, count 2 2006.285.06:44:36.96#ibcon#*mode == 0, iclass 40, count 2 2006.285.06:44:36.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.06:44:36.96#ibcon#[25=AT08-03\r\n] 2006.285.06:44:36.96#ibcon#*before write, iclass 40, count 2 2006.285.06:44:36.96#ibcon#enter sib2, iclass 40, count 2 2006.285.06:44:36.96#ibcon#flushed, iclass 40, count 2 2006.285.06:44:36.96#ibcon#about to write, iclass 40, count 2 2006.285.06:44:36.96#ibcon#wrote, iclass 40, count 2 2006.285.06:44:36.96#ibcon#about to read 3, iclass 40, count 2 2006.285.06:44:36.99#ibcon#read 3, iclass 40, count 2 2006.285.06:44:36.99#ibcon#about to read 4, iclass 40, count 2 2006.285.06:44:36.99#ibcon#read 4, iclass 40, count 2 2006.285.06:44:36.99#ibcon#about to read 5, iclass 40, count 2 2006.285.06:44:36.99#ibcon#read 5, iclass 40, count 2 2006.285.06:44:36.99#ibcon#about to read 6, iclass 40, count 2 2006.285.06:44:36.99#ibcon#read 6, iclass 40, count 2 2006.285.06:44:36.99#ibcon#end of sib2, iclass 40, count 2 2006.285.06:44:36.99#ibcon#*after write, iclass 40, count 2 2006.285.06:44:36.99#ibcon#*before return 0, iclass 40, count 2 2006.285.06:44:36.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:44:36.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:44:36.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.06:44:36.99#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:36.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:44:37.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:44:37.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:44:37.11#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:44:37.11#ibcon#first serial, iclass 40, count 0 2006.285.06:44:37.11#ibcon#enter sib2, iclass 40, count 0 2006.285.06:44:37.11#ibcon#flushed, iclass 40, count 0 2006.285.06:44:37.11#ibcon#about to write, iclass 40, count 0 2006.285.06:44:37.11#ibcon#wrote, iclass 40, count 0 2006.285.06:44:37.11#ibcon#about to read 3, iclass 40, count 0 2006.285.06:44:37.13#ibcon#read 3, iclass 40, count 0 2006.285.06:44:37.13#ibcon#about to read 4, iclass 40, count 0 2006.285.06:44:37.13#ibcon#read 4, iclass 40, count 0 2006.285.06:44:37.13#ibcon#about to read 5, iclass 40, count 0 2006.285.06:44:37.13#ibcon#read 5, iclass 40, count 0 2006.285.06:44:37.13#ibcon#about to read 6, iclass 40, count 0 2006.285.06:44:37.13#ibcon#read 6, iclass 40, count 0 2006.285.06:44:37.13#ibcon#end of sib2, iclass 40, count 0 2006.285.06:44:37.13#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:44:37.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:44:37.13#ibcon#[25=USB\r\n] 2006.285.06:44:37.13#ibcon#*before write, iclass 40, count 0 2006.285.06:44:37.13#ibcon#enter sib2, iclass 40, count 0 2006.285.06:44:37.13#ibcon#flushed, iclass 40, count 0 2006.285.06:44:37.13#ibcon#about to write, iclass 40, count 0 2006.285.06:44:37.13#ibcon#wrote, iclass 40, count 0 2006.285.06:44:37.13#ibcon#about to read 3, iclass 40, count 0 2006.285.06:44:37.16#ibcon#read 3, iclass 40, count 0 2006.285.06:44:37.16#ibcon#about to read 4, iclass 40, count 0 2006.285.06:44:37.16#ibcon#read 4, iclass 40, count 0 2006.285.06:44:37.16#ibcon#about to read 5, iclass 40, count 0 2006.285.06:44:37.16#ibcon#read 5, iclass 40, count 0 2006.285.06:44:37.16#ibcon#about to read 6, iclass 40, count 0 2006.285.06:44:37.16#ibcon#read 6, iclass 40, count 0 2006.285.06:44:37.16#ibcon#end of sib2, iclass 40, count 0 2006.285.06:44:37.16#ibcon#*after write, iclass 40, count 0 2006.285.06:44:37.16#ibcon#*before return 0, iclass 40, count 0 2006.285.06:44:37.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:44:37.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:44:37.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:44:37.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:44:37.16$vck44/vblo=1,629.99 2006.285.06:44:37.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.06:44:37.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.06:44:37.16#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:37.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:44:37.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:44:37.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:44:37.16#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:44:37.16#ibcon#first serial, iclass 4, count 0 2006.285.06:44:37.16#ibcon#enter sib2, iclass 4, count 0 2006.285.06:44:37.16#ibcon#flushed, iclass 4, count 0 2006.285.06:44:37.16#ibcon#about to write, iclass 4, count 0 2006.285.06:44:37.16#ibcon#wrote, iclass 4, count 0 2006.285.06:44:37.16#ibcon#about to read 3, iclass 4, count 0 2006.285.06:44:37.18#ibcon#read 3, iclass 4, count 0 2006.285.06:44:37.18#ibcon#about to read 4, iclass 4, count 0 2006.285.06:44:37.18#ibcon#read 4, iclass 4, count 0 2006.285.06:44:37.18#ibcon#about to read 5, iclass 4, count 0 2006.285.06:44:37.18#ibcon#read 5, iclass 4, count 0 2006.285.06:44:37.18#ibcon#about to read 6, iclass 4, count 0 2006.285.06:44:37.18#ibcon#read 6, iclass 4, count 0 2006.285.06:44:37.18#ibcon#end of sib2, iclass 4, count 0 2006.285.06:44:37.18#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:44:37.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:44:37.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:44:37.18#ibcon#*before write, iclass 4, count 0 2006.285.06:44:37.18#ibcon#enter sib2, iclass 4, count 0 2006.285.06:44:37.18#ibcon#flushed, iclass 4, count 0 2006.285.06:44:37.18#ibcon#about to write, iclass 4, count 0 2006.285.06:44:37.18#ibcon#wrote, iclass 4, count 0 2006.285.06:44:37.18#ibcon#about to read 3, iclass 4, count 0 2006.285.06:44:37.22#ibcon#read 3, iclass 4, count 0 2006.285.06:44:37.22#ibcon#about to read 4, iclass 4, count 0 2006.285.06:44:37.22#ibcon#read 4, iclass 4, count 0 2006.285.06:44:37.22#ibcon#about to read 5, iclass 4, count 0 2006.285.06:44:37.22#ibcon#read 5, iclass 4, count 0 2006.285.06:44:37.22#ibcon#about to read 6, iclass 4, count 0 2006.285.06:44:37.22#ibcon#read 6, iclass 4, count 0 2006.285.06:44:37.22#ibcon#end of sib2, iclass 4, count 0 2006.285.06:44:37.22#ibcon#*after write, iclass 4, count 0 2006.285.06:44:37.22#ibcon#*before return 0, iclass 4, count 0 2006.285.06:44:37.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:44:37.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:44:37.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:44:37.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:44:37.22$vck44/vb=1,4 2006.285.06:44:37.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.06:44:37.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.06:44:37.22#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:37.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:44:37.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:44:37.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:44:37.22#ibcon#enter wrdev, iclass 6, count 2 2006.285.06:44:37.22#ibcon#first serial, iclass 6, count 2 2006.285.06:44:37.22#ibcon#enter sib2, iclass 6, count 2 2006.285.06:44:37.22#ibcon#flushed, iclass 6, count 2 2006.285.06:44:37.22#ibcon#about to write, iclass 6, count 2 2006.285.06:44:37.22#ibcon#wrote, iclass 6, count 2 2006.285.06:44:37.22#ibcon#about to read 3, iclass 6, count 2 2006.285.06:44:37.24#ibcon#read 3, iclass 6, count 2 2006.285.06:44:37.24#ibcon#about to read 4, iclass 6, count 2 2006.285.06:44:37.24#ibcon#read 4, iclass 6, count 2 2006.285.06:44:37.24#ibcon#about to read 5, iclass 6, count 2 2006.285.06:44:37.24#ibcon#read 5, iclass 6, count 2 2006.285.06:44:37.24#ibcon#about to read 6, iclass 6, count 2 2006.285.06:44:37.24#ibcon#read 6, iclass 6, count 2 2006.285.06:44:37.24#ibcon#end of sib2, iclass 6, count 2 2006.285.06:44:37.24#ibcon#*mode == 0, iclass 6, count 2 2006.285.06:44:37.24#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.06:44:37.24#ibcon#[27=AT01-04\r\n] 2006.285.06:44:37.24#ibcon#*before write, iclass 6, count 2 2006.285.06:44:37.24#ibcon#enter sib2, iclass 6, count 2 2006.285.06:44:37.24#ibcon#flushed, iclass 6, count 2 2006.285.06:44:37.24#ibcon#about to write, iclass 6, count 2 2006.285.06:44:37.24#ibcon#wrote, iclass 6, count 2 2006.285.06:44:37.24#ibcon#about to read 3, iclass 6, count 2 2006.285.06:44:37.27#ibcon#read 3, iclass 6, count 2 2006.285.06:44:37.27#ibcon#about to read 4, iclass 6, count 2 2006.285.06:44:37.27#ibcon#read 4, iclass 6, count 2 2006.285.06:44:37.27#ibcon#about to read 5, iclass 6, count 2 2006.285.06:44:37.27#ibcon#read 5, iclass 6, count 2 2006.285.06:44:37.27#ibcon#about to read 6, iclass 6, count 2 2006.285.06:44:37.27#ibcon#read 6, iclass 6, count 2 2006.285.06:44:37.27#ibcon#end of sib2, iclass 6, count 2 2006.285.06:44:37.27#ibcon#*after write, iclass 6, count 2 2006.285.06:44:37.27#ibcon#*before return 0, iclass 6, count 2 2006.285.06:44:37.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:44:37.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:44:37.27#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.06:44:37.27#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:37.27#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:44:37.39#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:44:37.39#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:44:37.39#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:44:37.39#ibcon#first serial, iclass 6, count 0 2006.285.06:44:37.39#ibcon#enter sib2, iclass 6, count 0 2006.285.06:44:37.39#ibcon#flushed, iclass 6, count 0 2006.285.06:44:37.39#ibcon#about to write, iclass 6, count 0 2006.285.06:44:37.39#ibcon#wrote, iclass 6, count 0 2006.285.06:44:37.39#ibcon#about to read 3, iclass 6, count 0 2006.285.06:44:37.41#ibcon#read 3, iclass 6, count 0 2006.285.06:44:37.41#ibcon#about to read 4, iclass 6, count 0 2006.285.06:44:37.41#ibcon#read 4, iclass 6, count 0 2006.285.06:44:37.41#ibcon#about to read 5, iclass 6, count 0 2006.285.06:44:37.41#ibcon#read 5, iclass 6, count 0 2006.285.06:44:37.41#ibcon#about to read 6, iclass 6, count 0 2006.285.06:44:37.41#ibcon#read 6, iclass 6, count 0 2006.285.06:44:37.41#ibcon#end of sib2, iclass 6, count 0 2006.285.06:44:37.41#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:44:37.41#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:44:37.41#ibcon#[27=USB\r\n] 2006.285.06:44:37.41#ibcon#*before write, iclass 6, count 0 2006.285.06:44:37.41#ibcon#enter sib2, iclass 6, count 0 2006.285.06:44:37.41#ibcon#flushed, iclass 6, count 0 2006.285.06:44:37.41#ibcon#about to write, iclass 6, count 0 2006.285.06:44:37.41#ibcon#wrote, iclass 6, count 0 2006.285.06:44:37.41#ibcon#about to read 3, iclass 6, count 0 2006.285.06:44:37.44#ibcon#read 3, iclass 6, count 0 2006.285.06:44:37.44#ibcon#about to read 4, iclass 6, count 0 2006.285.06:44:37.44#ibcon#read 4, iclass 6, count 0 2006.285.06:44:37.44#ibcon#about to read 5, iclass 6, count 0 2006.285.06:44:37.44#ibcon#read 5, iclass 6, count 0 2006.285.06:44:37.44#ibcon#about to read 6, iclass 6, count 0 2006.285.06:44:37.44#ibcon#read 6, iclass 6, count 0 2006.285.06:44:37.44#ibcon#end of sib2, iclass 6, count 0 2006.285.06:44:37.44#ibcon#*after write, iclass 6, count 0 2006.285.06:44:37.44#ibcon#*before return 0, iclass 6, count 0 2006.285.06:44:37.44#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:44:37.44#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:44:37.44#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:44:37.44#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:44:37.44$vck44/vblo=2,634.99 2006.285.06:44:37.44#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.06:44:37.44#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.06:44:37.44#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:37.44#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:44:37.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:44:37.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:44:37.44#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:44:37.44#ibcon#first serial, iclass 10, count 0 2006.285.06:44:37.44#ibcon#enter sib2, iclass 10, count 0 2006.285.06:44:37.44#ibcon#flushed, iclass 10, count 0 2006.285.06:44:37.44#ibcon#about to write, iclass 10, count 0 2006.285.06:44:37.44#ibcon#wrote, iclass 10, count 0 2006.285.06:44:37.44#ibcon#about to read 3, iclass 10, count 0 2006.285.06:44:37.46#ibcon#read 3, iclass 10, count 0 2006.285.06:44:37.46#ibcon#about to read 4, iclass 10, count 0 2006.285.06:44:37.46#ibcon#read 4, iclass 10, count 0 2006.285.06:44:37.46#ibcon#about to read 5, iclass 10, count 0 2006.285.06:44:37.46#ibcon#read 5, iclass 10, count 0 2006.285.06:44:37.46#ibcon#about to read 6, iclass 10, count 0 2006.285.06:44:37.46#ibcon#read 6, iclass 10, count 0 2006.285.06:44:37.46#ibcon#end of sib2, iclass 10, count 0 2006.285.06:44:37.46#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:44:37.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:44:37.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:44:37.46#ibcon#*before write, iclass 10, count 0 2006.285.06:44:37.46#ibcon#enter sib2, iclass 10, count 0 2006.285.06:44:37.46#ibcon#flushed, iclass 10, count 0 2006.285.06:44:37.46#ibcon#about to write, iclass 10, count 0 2006.285.06:44:37.46#ibcon#wrote, iclass 10, count 0 2006.285.06:44:37.46#ibcon#about to read 3, iclass 10, count 0 2006.285.06:44:37.50#ibcon#read 3, iclass 10, count 0 2006.285.06:44:37.50#ibcon#about to read 4, iclass 10, count 0 2006.285.06:44:37.50#ibcon#read 4, iclass 10, count 0 2006.285.06:44:37.50#ibcon#about to read 5, iclass 10, count 0 2006.285.06:44:37.50#ibcon#read 5, iclass 10, count 0 2006.285.06:44:37.50#ibcon#about to read 6, iclass 10, count 0 2006.285.06:44:37.50#ibcon#read 6, iclass 10, count 0 2006.285.06:44:37.50#ibcon#end of sib2, iclass 10, count 0 2006.285.06:44:37.50#ibcon#*after write, iclass 10, count 0 2006.285.06:44:37.50#ibcon#*before return 0, iclass 10, count 0 2006.285.06:44:37.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:44:37.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:44:37.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:44:37.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:44:37.50$vck44/vb=2,5 2006.285.06:44:37.50#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.06:44:37.50#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.06:44:37.50#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:37.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:44:37.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:44:37.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:44:37.56#ibcon#enter wrdev, iclass 12, count 2 2006.285.06:44:37.56#ibcon#first serial, iclass 12, count 2 2006.285.06:44:37.56#ibcon#enter sib2, iclass 12, count 2 2006.285.06:44:37.56#ibcon#flushed, iclass 12, count 2 2006.285.06:44:37.56#ibcon#about to write, iclass 12, count 2 2006.285.06:44:37.56#ibcon#wrote, iclass 12, count 2 2006.285.06:44:37.56#ibcon#about to read 3, iclass 12, count 2 2006.285.06:44:37.58#ibcon#read 3, iclass 12, count 2 2006.285.06:44:37.58#ibcon#about to read 4, iclass 12, count 2 2006.285.06:44:37.58#ibcon#read 4, iclass 12, count 2 2006.285.06:44:37.58#ibcon#about to read 5, iclass 12, count 2 2006.285.06:44:37.58#ibcon#read 5, iclass 12, count 2 2006.285.06:44:37.58#ibcon#about to read 6, iclass 12, count 2 2006.285.06:44:37.58#ibcon#read 6, iclass 12, count 2 2006.285.06:44:37.58#ibcon#end of sib2, iclass 12, count 2 2006.285.06:44:37.58#ibcon#*mode == 0, iclass 12, count 2 2006.285.06:44:37.58#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.06:44:37.58#ibcon#[27=AT02-05\r\n] 2006.285.06:44:37.58#ibcon#*before write, iclass 12, count 2 2006.285.06:44:37.58#ibcon#enter sib2, iclass 12, count 2 2006.285.06:44:37.58#ibcon#flushed, iclass 12, count 2 2006.285.06:44:37.58#ibcon#about to write, iclass 12, count 2 2006.285.06:44:37.58#ibcon#wrote, iclass 12, count 2 2006.285.06:44:37.58#ibcon#about to read 3, iclass 12, count 2 2006.285.06:44:37.61#ibcon#read 3, iclass 12, count 2 2006.285.06:44:37.61#ibcon#about to read 4, iclass 12, count 2 2006.285.06:44:37.61#ibcon#read 4, iclass 12, count 2 2006.285.06:44:37.61#ibcon#about to read 5, iclass 12, count 2 2006.285.06:44:37.61#ibcon#read 5, iclass 12, count 2 2006.285.06:44:37.61#ibcon#about to read 6, iclass 12, count 2 2006.285.06:44:37.61#ibcon#read 6, iclass 12, count 2 2006.285.06:44:37.61#ibcon#end of sib2, iclass 12, count 2 2006.285.06:44:37.61#ibcon#*after write, iclass 12, count 2 2006.285.06:44:37.61#ibcon#*before return 0, iclass 12, count 2 2006.285.06:44:37.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:44:37.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:44:37.61#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.06:44:37.61#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:37.61#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:44:37.73#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:44:37.73#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:44:37.73#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:44:37.73#ibcon#first serial, iclass 12, count 0 2006.285.06:44:37.73#ibcon#enter sib2, iclass 12, count 0 2006.285.06:44:37.73#ibcon#flushed, iclass 12, count 0 2006.285.06:44:37.73#ibcon#about to write, iclass 12, count 0 2006.285.06:44:37.73#ibcon#wrote, iclass 12, count 0 2006.285.06:44:37.73#ibcon#about to read 3, iclass 12, count 0 2006.285.06:44:37.75#ibcon#read 3, iclass 12, count 0 2006.285.06:44:37.75#ibcon#about to read 4, iclass 12, count 0 2006.285.06:44:37.75#ibcon#read 4, iclass 12, count 0 2006.285.06:44:37.75#ibcon#about to read 5, iclass 12, count 0 2006.285.06:44:37.75#ibcon#read 5, iclass 12, count 0 2006.285.06:44:37.75#ibcon#about to read 6, iclass 12, count 0 2006.285.06:44:37.75#ibcon#read 6, iclass 12, count 0 2006.285.06:44:37.75#ibcon#end of sib2, iclass 12, count 0 2006.285.06:44:37.75#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:44:37.75#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:44:37.75#ibcon#[27=USB\r\n] 2006.285.06:44:37.75#ibcon#*before write, iclass 12, count 0 2006.285.06:44:37.75#ibcon#enter sib2, iclass 12, count 0 2006.285.06:44:37.75#ibcon#flushed, iclass 12, count 0 2006.285.06:44:37.75#ibcon#about to write, iclass 12, count 0 2006.285.06:44:37.75#ibcon#wrote, iclass 12, count 0 2006.285.06:44:37.75#ibcon#about to read 3, iclass 12, count 0 2006.285.06:44:37.78#ibcon#read 3, iclass 12, count 0 2006.285.06:44:37.78#ibcon#about to read 4, iclass 12, count 0 2006.285.06:44:37.78#ibcon#read 4, iclass 12, count 0 2006.285.06:44:37.78#ibcon#about to read 5, iclass 12, count 0 2006.285.06:44:37.78#ibcon#read 5, iclass 12, count 0 2006.285.06:44:37.78#ibcon#about to read 6, iclass 12, count 0 2006.285.06:44:37.78#ibcon#read 6, iclass 12, count 0 2006.285.06:44:37.78#ibcon#end of sib2, iclass 12, count 0 2006.285.06:44:37.78#ibcon#*after write, iclass 12, count 0 2006.285.06:44:37.78#ibcon#*before return 0, iclass 12, count 0 2006.285.06:44:37.78#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:44:37.78#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:44:37.78#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:44:37.78#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:44:37.78$vck44/vblo=3,649.99 2006.285.06:44:37.78#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.06:44:37.78#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.06:44:37.78#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:37.78#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:44:37.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:44:37.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:44:37.78#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:44:37.78#ibcon#first serial, iclass 14, count 0 2006.285.06:44:37.78#ibcon#enter sib2, iclass 14, count 0 2006.285.06:44:37.78#ibcon#flushed, iclass 14, count 0 2006.285.06:44:37.78#ibcon#about to write, iclass 14, count 0 2006.285.06:44:37.78#ibcon#wrote, iclass 14, count 0 2006.285.06:44:37.78#ibcon#about to read 3, iclass 14, count 0 2006.285.06:44:37.80#ibcon#read 3, iclass 14, count 0 2006.285.06:44:37.80#ibcon#about to read 4, iclass 14, count 0 2006.285.06:44:37.80#ibcon#read 4, iclass 14, count 0 2006.285.06:44:37.80#ibcon#about to read 5, iclass 14, count 0 2006.285.06:44:37.80#ibcon#read 5, iclass 14, count 0 2006.285.06:44:37.80#ibcon#about to read 6, iclass 14, count 0 2006.285.06:44:37.80#ibcon#read 6, iclass 14, count 0 2006.285.06:44:37.80#ibcon#end of sib2, iclass 14, count 0 2006.285.06:44:37.80#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:44:37.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:44:37.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:44:37.80#ibcon#*before write, iclass 14, count 0 2006.285.06:44:37.80#ibcon#enter sib2, iclass 14, count 0 2006.285.06:44:37.80#ibcon#flushed, iclass 14, count 0 2006.285.06:44:37.80#ibcon#about to write, iclass 14, count 0 2006.285.06:44:37.80#ibcon#wrote, iclass 14, count 0 2006.285.06:44:37.80#ibcon#about to read 3, iclass 14, count 0 2006.285.06:44:37.84#ibcon#read 3, iclass 14, count 0 2006.285.06:44:37.84#ibcon#about to read 4, iclass 14, count 0 2006.285.06:44:37.84#ibcon#read 4, iclass 14, count 0 2006.285.06:44:37.84#ibcon#about to read 5, iclass 14, count 0 2006.285.06:44:37.84#ibcon#read 5, iclass 14, count 0 2006.285.06:44:37.84#ibcon#about to read 6, iclass 14, count 0 2006.285.06:44:37.84#ibcon#read 6, iclass 14, count 0 2006.285.06:44:37.84#ibcon#end of sib2, iclass 14, count 0 2006.285.06:44:37.84#ibcon#*after write, iclass 14, count 0 2006.285.06:44:37.84#ibcon#*before return 0, iclass 14, count 0 2006.285.06:44:37.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:44:37.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:44:37.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:44:37.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:44:37.84$vck44/vb=3,4 2006.285.06:44:37.84#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.06:44:37.84#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.06:44:37.84#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:37.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:44:37.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:44:37.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:44:37.90#ibcon#enter wrdev, iclass 16, count 2 2006.285.06:44:37.90#ibcon#first serial, iclass 16, count 2 2006.285.06:44:37.90#ibcon#enter sib2, iclass 16, count 2 2006.285.06:44:37.90#ibcon#flushed, iclass 16, count 2 2006.285.06:44:37.90#ibcon#about to write, iclass 16, count 2 2006.285.06:44:37.90#ibcon#wrote, iclass 16, count 2 2006.285.06:44:37.90#ibcon#about to read 3, iclass 16, count 2 2006.285.06:44:37.92#ibcon#read 3, iclass 16, count 2 2006.285.06:44:37.92#ibcon#about to read 4, iclass 16, count 2 2006.285.06:44:37.92#ibcon#read 4, iclass 16, count 2 2006.285.06:44:37.92#ibcon#about to read 5, iclass 16, count 2 2006.285.06:44:37.92#ibcon#read 5, iclass 16, count 2 2006.285.06:44:37.92#ibcon#about to read 6, iclass 16, count 2 2006.285.06:44:37.92#ibcon#read 6, iclass 16, count 2 2006.285.06:44:37.92#ibcon#end of sib2, iclass 16, count 2 2006.285.06:44:37.92#ibcon#*mode == 0, iclass 16, count 2 2006.285.06:44:37.92#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.06:44:37.92#ibcon#[27=AT03-04\r\n] 2006.285.06:44:37.92#ibcon#*before write, iclass 16, count 2 2006.285.06:44:37.92#ibcon#enter sib2, iclass 16, count 2 2006.285.06:44:37.92#ibcon#flushed, iclass 16, count 2 2006.285.06:44:37.92#ibcon#about to write, iclass 16, count 2 2006.285.06:44:37.92#ibcon#wrote, iclass 16, count 2 2006.285.06:44:37.92#ibcon#about to read 3, iclass 16, count 2 2006.285.06:44:37.95#ibcon#read 3, iclass 16, count 2 2006.285.06:44:37.95#ibcon#about to read 4, iclass 16, count 2 2006.285.06:44:37.95#ibcon#read 4, iclass 16, count 2 2006.285.06:44:37.95#ibcon#about to read 5, iclass 16, count 2 2006.285.06:44:37.95#ibcon#read 5, iclass 16, count 2 2006.285.06:44:37.95#ibcon#about to read 6, iclass 16, count 2 2006.285.06:44:37.95#ibcon#read 6, iclass 16, count 2 2006.285.06:44:37.95#ibcon#end of sib2, iclass 16, count 2 2006.285.06:44:37.95#ibcon#*after write, iclass 16, count 2 2006.285.06:44:37.95#ibcon#*before return 0, iclass 16, count 2 2006.285.06:44:37.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:44:37.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:44:37.95#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.06:44:37.95#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:37.95#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:44:38.07#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:44:38.07#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:44:38.07#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:44:38.07#ibcon#first serial, iclass 16, count 0 2006.285.06:44:38.07#ibcon#enter sib2, iclass 16, count 0 2006.285.06:44:38.07#ibcon#flushed, iclass 16, count 0 2006.285.06:44:38.07#ibcon#about to write, iclass 16, count 0 2006.285.06:44:38.07#ibcon#wrote, iclass 16, count 0 2006.285.06:44:38.07#ibcon#about to read 3, iclass 16, count 0 2006.285.06:44:38.09#ibcon#read 3, iclass 16, count 0 2006.285.06:44:38.09#ibcon#about to read 4, iclass 16, count 0 2006.285.06:44:38.09#ibcon#read 4, iclass 16, count 0 2006.285.06:44:38.09#ibcon#about to read 5, iclass 16, count 0 2006.285.06:44:38.09#ibcon#read 5, iclass 16, count 0 2006.285.06:44:38.09#ibcon#about to read 6, iclass 16, count 0 2006.285.06:44:38.09#ibcon#read 6, iclass 16, count 0 2006.285.06:44:38.09#ibcon#end of sib2, iclass 16, count 0 2006.285.06:44:38.09#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:44:38.09#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:44:38.09#ibcon#[27=USB\r\n] 2006.285.06:44:38.09#ibcon#*before write, iclass 16, count 0 2006.285.06:44:38.09#ibcon#enter sib2, iclass 16, count 0 2006.285.06:44:38.09#ibcon#flushed, iclass 16, count 0 2006.285.06:44:38.09#ibcon#about to write, iclass 16, count 0 2006.285.06:44:38.09#ibcon#wrote, iclass 16, count 0 2006.285.06:44:38.09#ibcon#about to read 3, iclass 16, count 0 2006.285.06:44:38.12#ibcon#read 3, iclass 16, count 0 2006.285.06:44:38.12#ibcon#about to read 4, iclass 16, count 0 2006.285.06:44:38.12#ibcon#read 4, iclass 16, count 0 2006.285.06:44:38.12#ibcon#about to read 5, iclass 16, count 0 2006.285.06:44:38.12#ibcon#read 5, iclass 16, count 0 2006.285.06:44:38.12#ibcon#about to read 6, iclass 16, count 0 2006.285.06:44:38.12#ibcon#read 6, iclass 16, count 0 2006.285.06:44:38.12#ibcon#end of sib2, iclass 16, count 0 2006.285.06:44:38.12#ibcon#*after write, iclass 16, count 0 2006.285.06:44:38.12#ibcon#*before return 0, iclass 16, count 0 2006.285.06:44:38.12#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:44:38.12#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:44:38.12#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:44:38.12#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:44:38.12$vck44/vblo=4,679.99 2006.285.06:44:38.12#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.06:44:38.12#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.06:44:38.12#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:38.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:44:38.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:44:38.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:44:38.12#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:44:38.12#ibcon#first serial, iclass 18, count 0 2006.285.06:44:38.12#ibcon#enter sib2, iclass 18, count 0 2006.285.06:44:38.12#ibcon#flushed, iclass 18, count 0 2006.285.06:44:38.12#ibcon#about to write, iclass 18, count 0 2006.285.06:44:38.12#ibcon#wrote, iclass 18, count 0 2006.285.06:44:38.12#ibcon#about to read 3, iclass 18, count 0 2006.285.06:44:38.14#ibcon#read 3, iclass 18, count 0 2006.285.06:44:38.14#ibcon#about to read 4, iclass 18, count 0 2006.285.06:44:38.14#ibcon#read 4, iclass 18, count 0 2006.285.06:44:38.14#ibcon#about to read 5, iclass 18, count 0 2006.285.06:44:38.14#ibcon#read 5, iclass 18, count 0 2006.285.06:44:38.14#ibcon#about to read 6, iclass 18, count 0 2006.285.06:44:38.14#ibcon#read 6, iclass 18, count 0 2006.285.06:44:38.14#ibcon#end of sib2, iclass 18, count 0 2006.285.06:44:38.14#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:44:38.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:44:38.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:44:38.14#ibcon#*before write, iclass 18, count 0 2006.285.06:44:38.14#ibcon#enter sib2, iclass 18, count 0 2006.285.06:44:38.14#ibcon#flushed, iclass 18, count 0 2006.285.06:44:38.14#ibcon#about to write, iclass 18, count 0 2006.285.06:44:38.14#ibcon#wrote, iclass 18, count 0 2006.285.06:44:38.14#ibcon#about to read 3, iclass 18, count 0 2006.285.06:44:38.18#ibcon#read 3, iclass 18, count 0 2006.285.06:44:38.18#ibcon#about to read 4, iclass 18, count 0 2006.285.06:44:38.18#ibcon#read 4, iclass 18, count 0 2006.285.06:44:38.18#ibcon#about to read 5, iclass 18, count 0 2006.285.06:44:38.18#ibcon#read 5, iclass 18, count 0 2006.285.06:44:38.18#ibcon#about to read 6, iclass 18, count 0 2006.285.06:44:38.18#ibcon#read 6, iclass 18, count 0 2006.285.06:44:38.18#ibcon#end of sib2, iclass 18, count 0 2006.285.06:44:38.18#ibcon#*after write, iclass 18, count 0 2006.285.06:44:38.18#ibcon#*before return 0, iclass 18, count 0 2006.285.06:44:38.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:44:38.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:44:38.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:44:38.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:44:38.18$vck44/vb=4,5 2006.285.06:44:38.18#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.06:44:38.18#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.06:44:38.18#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:38.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:44:38.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:44:38.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:44:38.24#ibcon#enter wrdev, iclass 20, count 2 2006.285.06:44:38.24#ibcon#first serial, iclass 20, count 2 2006.285.06:44:38.24#ibcon#enter sib2, iclass 20, count 2 2006.285.06:44:38.24#ibcon#flushed, iclass 20, count 2 2006.285.06:44:38.24#ibcon#about to write, iclass 20, count 2 2006.285.06:44:38.24#ibcon#wrote, iclass 20, count 2 2006.285.06:44:38.24#ibcon#about to read 3, iclass 20, count 2 2006.285.06:44:38.26#ibcon#read 3, iclass 20, count 2 2006.285.06:44:38.26#ibcon#about to read 4, iclass 20, count 2 2006.285.06:44:38.26#ibcon#read 4, iclass 20, count 2 2006.285.06:44:38.26#ibcon#about to read 5, iclass 20, count 2 2006.285.06:44:38.26#ibcon#read 5, iclass 20, count 2 2006.285.06:44:38.26#ibcon#about to read 6, iclass 20, count 2 2006.285.06:44:38.26#ibcon#read 6, iclass 20, count 2 2006.285.06:44:38.26#ibcon#end of sib2, iclass 20, count 2 2006.285.06:44:38.26#ibcon#*mode == 0, iclass 20, count 2 2006.285.06:44:38.26#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.06:44:38.26#ibcon#[27=AT04-05\r\n] 2006.285.06:44:38.26#ibcon#*before write, iclass 20, count 2 2006.285.06:44:38.26#ibcon#enter sib2, iclass 20, count 2 2006.285.06:44:38.26#ibcon#flushed, iclass 20, count 2 2006.285.06:44:38.26#ibcon#about to write, iclass 20, count 2 2006.285.06:44:38.26#ibcon#wrote, iclass 20, count 2 2006.285.06:44:38.26#ibcon#about to read 3, iclass 20, count 2 2006.285.06:44:38.29#ibcon#read 3, iclass 20, count 2 2006.285.06:44:38.29#ibcon#about to read 4, iclass 20, count 2 2006.285.06:44:38.29#ibcon#read 4, iclass 20, count 2 2006.285.06:44:38.29#ibcon#about to read 5, iclass 20, count 2 2006.285.06:44:38.29#ibcon#read 5, iclass 20, count 2 2006.285.06:44:38.29#ibcon#about to read 6, iclass 20, count 2 2006.285.06:44:38.29#ibcon#read 6, iclass 20, count 2 2006.285.06:44:38.29#ibcon#end of sib2, iclass 20, count 2 2006.285.06:44:38.29#ibcon#*after write, iclass 20, count 2 2006.285.06:44:38.29#ibcon#*before return 0, iclass 20, count 2 2006.285.06:44:38.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:44:38.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:44:38.29#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.06:44:38.29#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:38.29#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:44:38.41#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:44:38.41#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:44:38.41#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:44:38.41#ibcon#first serial, iclass 20, count 0 2006.285.06:44:38.41#ibcon#enter sib2, iclass 20, count 0 2006.285.06:44:38.41#ibcon#flushed, iclass 20, count 0 2006.285.06:44:38.41#ibcon#about to write, iclass 20, count 0 2006.285.06:44:38.41#ibcon#wrote, iclass 20, count 0 2006.285.06:44:38.41#ibcon#about to read 3, iclass 20, count 0 2006.285.06:44:38.43#ibcon#read 3, iclass 20, count 0 2006.285.06:44:38.43#ibcon#about to read 4, iclass 20, count 0 2006.285.06:44:38.43#ibcon#read 4, iclass 20, count 0 2006.285.06:44:38.43#ibcon#about to read 5, iclass 20, count 0 2006.285.06:44:38.43#ibcon#read 5, iclass 20, count 0 2006.285.06:44:38.43#ibcon#about to read 6, iclass 20, count 0 2006.285.06:44:38.43#ibcon#read 6, iclass 20, count 0 2006.285.06:44:38.43#ibcon#end of sib2, iclass 20, count 0 2006.285.06:44:38.43#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:44:38.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:44:38.43#ibcon#[27=USB\r\n] 2006.285.06:44:38.43#ibcon#*before write, iclass 20, count 0 2006.285.06:44:38.43#ibcon#enter sib2, iclass 20, count 0 2006.285.06:44:38.43#ibcon#flushed, iclass 20, count 0 2006.285.06:44:38.43#ibcon#about to write, iclass 20, count 0 2006.285.06:44:38.43#ibcon#wrote, iclass 20, count 0 2006.285.06:44:38.43#ibcon#about to read 3, iclass 20, count 0 2006.285.06:44:38.46#ibcon#read 3, iclass 20, count 0 2006.285.06:44:38.46#ibcon#about to read 4, iclass 20, count 0 2006.285.06:44:38.46#ibcon#read 4, iclass 20, count 0 2006.285.06:44:38.46#ibcon#about to read 5, iclass 20, count 0 2006.285.06:44:38.46#ibcon#read 5, iclass 20, count 0 2006.285.06:44:38.46#ibcon#about to read 6, iclass 20, count 0 2006.285.06:44:38.46#ibcon#read 6, iclass 20, count 0 2006.285.06:44:38.46#ibcon#end of sib2, iclass 20, count 0 2006.285.06:44:38.46#ibcon#*after write, iclass 20, count 0 2006.285.06:44:38.46#ibcon#*before return 0, iclass 20, count 0 2006.285.06:44:38.46#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:44:38.46#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:44:38.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:44:38.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:44:38.46$vck44/vblo=5,709.99 2006.285.06:44:38.46#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.06:44:38.46#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.06:44:38.46#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:38.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:44:38.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:44:38.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:44:38.46#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:44:38.46#ibcon#first serial, iclass 22, count 0 2006.285.06:44:38.46#ibcon#enter sib2, iclass 22, count 0 2006.285.06:44:38.46#ibcon#flushed, iclass 22, count 0 2006.285.06:44:38.46#ibcon#about to write, iclass 22, count 0 2006.285.06:44:38.46#ibcon#wrote, iclass 22, count 0 2006.285.06:44:38.46#ibcon#about to read 3, iclass 22, count 0 2006.285.06:44:38.48#ibcon#read 3, iclass 22, count 0 2006.285.06:44:38.48#ibcon#about to read 4, iclass 22, count 0 2006.285.06:44:38.48#ibcon#read 4, iclass 22, count 0 2006.285.06:44:38.48#ibcon#about to read 5, iclass 22, count 0 2006.285.06:44:38.48#ibcon#read 5, iclass 22, count 0 2006.285.06:44:38.48#ibcon#about to read 6, iclass 22, count 0 2006.285.06:44:38.48#ibcon#read 6, iclass 22, count 0 2006.285.06:44:38.48#ibcon#end of sib2, iclass 22, count 0 2006.285.06:44:38.48#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:44:38.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:44:38.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:44:38.48#ibcon#*before write, iclass 22, count 0 2006.285.06:44:38.48#ibcon#enter sib2, iclass 22, count 0 2006.285.06:44:38.48#ibcon#flushed, iclass 22, count 0 2006.285.06:44:38.48#ibcon#about to write, iclass 22, count 0 2006.285.06:44:38.48#ibcon#wrote, iclass 22, count 0 2006.285.06:44:38.48#ibcon#about to read 3, iclass 22, count 0 2006.285.06:44:38.52#ibcon#read 3, iclass 22, count 0 2006.285.06:44:38.52#ibcon#about to read 4, iclass 22, count 0 2006.285.06:44:38.52#ibcon#read 4, iclass 22, count 0 2006.285.06:44:38.52#ibcon#about to read 5, iclass 22, count 0 2006.285.06:44:38.52#ibcon#read 5, iclass 22, count 0 2006.285.06:44:38.52#ibcon#about to read 6, iclass 22, count 0 2006.285.06:44:38.52#ibcon#read 6, iclass 22, count 0 2006.285.06:44:38.52#ibcon#end of sib2, iclass 22, count 0 2006.285.06:44:38.52#ibcon#*after write, iclass 22, count 0 2006.285.06:44:38.52#ibcon#*before return 0, iclass 22, count 0 2006.285.06:44:38.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:44:38.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:44:38.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:44:38.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:44:38.52$vck44/vb=5,4 2006.285.06:44:38.52#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.06:44:38.52#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.06:44:38.52#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:38.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:44:38.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:44:38.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:44:38.58#ibcon#enter wrdev, iclass 24, count 2 2006.285.06:44:38.58#ibcon#first serial, iclass 24, count 2 2006.285.06:44:38.58#ibcon#enter sib2, iclass 24, count 2 2006.285.06:44:38.58#ibcon#flushed, iclass 24, count 2 2006.285.06:44:38.58#ibcon#about to write, iclass 24, count 2 2006.285.06:44:38.58#ibcon#wrote, iclass 24, count 2 2006.285.06:44:38.58#ibcon#about to read 3, iclass 24, count 2 2006.285.06:44:38.60#ibcon#read 3, iclass 24, count 2 2006.285.06:44:38.60#ibcon#about to read 4, iclass 24, count 2 2006.285.06:44:38.60#ibcon#read 4, iclass 24, count 2 2006.285.06:44:38.60#ibcon#about to read 5, iclass 24, count 2 2006.285.06:44:38.60#ibcon#read 5, iclass 24, count 2 2006.285.06:44:38.60#ibcon#about to read 6, iclass 24, count 2 2006.285.06:44:38.60#ibcon#read 6, iclass 24, count 2 2006.285.06:44:38.60#ibcon#end of sib2, iclass 24, count 2 2006.285.06:44:38.60#ibcon#*mode == 0, iclass 24, count 2 2006.285.06:44:38.60#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.06:44:38.60#ibcon#[27=AT05-04\r\n] 2006.285.06:44:38.60#ibcon#*before write, iclass 24, count 2 2006.285.06:44:38.60#ibcon#enter sib2, iclass 24, count 2 2006.285.06:44:38.60#ibcon#flushed, iclass 24, count 2 2006.285.06:44:38.60#ibcon#about to write, iclass 24, count 2 2006.285.06:44:38.60#ibcon#wrote, iclass 24, count 2 2006.285.06:44:38.60#ibcon#about to read 3, iclass 24, count 2 2006.285.06:44:38.63#ibcon#read 3, iclass 24, count 2 2006.285.06:44:38.63#ibcon#about to read 4, iclass 24, count 2 2006.285.06:44:38.63#ibcon#read 4, iclass 24, count 2 2006.285.06:44:38.63#ibcon#about to read 5, iclass 24, count 2 2006.285.06:44:38.63#ibcon#read 5, iclass 24, count 2 2006.285.06:44:38.63#ibcon#about to read 6, iclass 24, count 2 2006.285.06:44:38.63#ibcon#read 6, iclass 24, count 2 2006.285.06:44:38.63#ibcon#end of sib2, iclass 24, count 2 2006.285.06:44:38.63#ibcon#*after write, iclass 24, count 2 2006.285.06:44:38.63#ibcon#*before return 0, iclass 24, count 2 2006.285.06:44:38.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:44:38.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:44:38.63#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.06:44:38.63#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:38.63#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:44:38.75#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:44:38.75#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:44:38.75#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:44:38.75#ibcon#first serial, iclass 24, count 0 2006.285.06:44:38.75#ibcon#enter sib2, iclass 24, count 0 2006.285.06:44:38.75#ibcon#flushed, iclass 24, count 0 2006.285.06:44:38.75#ibcon#about to write, iclass 24, count 0 2006.285.06:44:38.75#ibcon#wrote, iclass 24, count 0 2006.285.06:44:38.75#ibcon#about to read 3, iclass 24, count 0 2006.285.06:44:38.77#ibcon#read 3, iclass 24, count 0 2006.285.06:44:38.77#ibcon#about to read 4, iclass 24, count 0 2006.285.06:44:38.77#ibcon#read 4, iclass 24, count 0 2006.285.06:44:38.77#ibcon#about to read 5, iclass 24, count 0 2006.285.06:44:38.77#ibcon#read 5, iclass 24, count 0 2006.285.06:44:38.77#ibcon#about to read 6, iclass 24, count 0 2006.285.06:44:38.77#ibcon#read 6, iclass 24, count 0 2006.285.06:44:38.77#ibcon#end of sib2, iclass 24, count 0 2006.285.06:44:38.77#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:44:38.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:44:38.77#ibcon#[27=USB\r\n] 2006.285.06:44:38.77#ibcon#*before write, iclass 24, count 0 2006.285.06:44:38.77#ibcon#enter sib2, iclass 24, count 0 2006.285.06:44:38.77#ibcon#flushed, iclass 24, count 0 2006.285.06:44:38.77#ibcon#about to write, iclass 24, count 0 2006.285.06:44:38.77#ibcon#wrote, iclass 24, count 0 2006.285.06:44:38.77#ibcon#about to read 3, iclass 24, count 0 2006.285.06:44:38.80#ibcon#read 3, iclass 24, count 0 2006.285.06:44:38.80#ibcon#about to read 4, iclass 24, count 0 2006.285.06:44:38.80#ibcon#read 4, iclass 24, count 0 2006.285.06:44:38.80#ibcon#about to read 5, iclass 24, count 0 2006.285.06:44:38.80#ibcon#read 5, iclass 24, count 0 2006.285.06:44:38.80#ibcon#about to read 6, iclass 24, count 0 2006.285.06:44:38.80#ibcon#read 6, iclass 24, count 0 2006.285.06:44:38.80#ibcon#end of sib2, iclass 24, count 0 2006.285.06:44:38.80#ibcon#*after write, iclass 24, count 0 2006.285.06:44:38.80#ibcon#*before return 0, iclass 24, count 0 2006.285.06:44:38.80#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:44:38.80#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:44:38.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:44:38.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:44:38.80$vck44/vblo=6,719.99 2006.285.06:44:38.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.06:44:38.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.06:44:38.80#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:38.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:44:38.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:44:38.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:44:38.80#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:44:38.80#ibcon#first serial, iclass 26, count 0 2006.285.06:44:38.80#ibcon#enter sib2, iclass 26, count 0 2006.285.06:44:38.80#ibcon#flushed, iclass 26, count 0 2006.285.06:44:38.80#ibcon#about to write, iclass 26, count 0 2006.285.06:44:38.80#ibcon#wrote, iclass 26, count 0 2006.285.06:44:38.80#ibcon#about to read 3, iclass 26, count 0 2006.285.06:44:38.82#ibcon#read 3, iclass 26, count 0 2006.285.06:44:38.82#ibcon#about to read 4, iclass 26, count 0 2006.285.06:44:38.82#ibcon#read 4, iclass 26, count 0 2006.285.06:44:38.82#ibcon#about to read 5, iclass 26, count 0 2006.285.06:44:38.82#ibcon#read 5, iclass 26, count 0 2006.285.06:44:38.82#ibcon#about to read 6, iclass 26, count 0 2006.285.06:44:38.82#ibcon#read 6, iclass 26, count 0 2006.285.06:44:38.82#ibcon#end of sib2, iclass 26, count 0 2006.285.06:44:38.82#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:44:38.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:44:38.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:44:38.82#ibcon#*before write, iclass 26, count 0 2006.285.06:44:38.82#ibcon#enter sib2, iclass 26, count 0 2006.285.06:44:38.82#ibcon#flushed, iclass 26, count 0 2006.285.06:44:38.82#ibcon#about to write, iclass 26, count 0 2006.285.06:44:38.82#ibcon#wrote, iclass 26, count 0 2006.285.06:44:38.82#ibcon#about to read 3, iclass 26, count 0 2006.285.06:44:38.86#ibcon#read 3, iclass 26, count 0 2006.285.06:44:38.86#ibcon#about to read 4, iclass 26, count 0 2006.285.06:44:38.86#ibcon#read 4, iclass 26, count 0 2006.285.06:44:38.86#ibcon#about to read 5, iclass 26, count 0 2006.285.06:44:38.86#ibcon#read 5, iclass 26, count 0 2006.285.06:44:38.86#ibcon#about to read 6, iclass 26, count 0 2006.285.06:44:38.86#ibcon#read 6, iclass 26, count 0 2006.285.06:44:38.86#ibcon#end of sib2, iclass 26, count 0 2006.285.06:44:38.86#ibcon#*after write, iclass 26, count 0 2006.285.06:44:38.86#ibcon#*before return 0, iclass 26, count 0 2006.285.06:44:38.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:44:38.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:44:38.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:44:38.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:44:38.86$vck44/vb=6,3 2006.285.06:44:38.86#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.06:44:38.86#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.06:44:38.86#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:38.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:44:38.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:44:38.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:44:38.92#ibcon#enter wrdev, iclass 28, count 2 2006.285.06:44:38.92#ibcon#first serial, iclass 28, count 2 2006.285.06:44:38.92#ibcon#enter sib2, iclass 28, count 2 2006.285.06:44:38.92#ibcon#flushed, iclass 28, count 2 2006.285.06:44:38.92#ibcon#about to write, iclass 28, count 2 2006.285.06:44:38.92#ibcon#wrote, iclass 28, count 2 2006.285.06:44:38.92#ibcon#about to read 3, iclass 28, count 2 2006.285.06:44:38.94#ibcon#read 3, iclass 28, count 2 2006.285.06:44:38.94#ibcon#about to read 4, iclass 28, count 2 2006.285.06:44:38.94#ibcon#read 4, iclass 28, count 2 2006.285.06:44:38.94#ibcon#about to read 5, iclass 28, count 2 2006.285.06:44:38.94#ibcon#read 5, iclass 28, count 2 2006.285.06:44:38.94#ibcon#about to read 6, iclass 28, count 2 2006.285.06:44:38.94#ibcon#read 6, iclass 28, count 2 2006.285.06:44:38.94#ibcon#end of sib2, iclass 28, count 2 2006.285.06:44:38.94#ibcon#*mode == 0, iclass 28, count 2 2006.285.06:44:38.94#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.06:44:38.94#ibcon#[27=AT06-03\r\n] 2006.285.06:44:38.94#ibcon#*before write, iclass 28, count 2 2006.285.06:44:38.94#ibcon#enter sib2, iclass 28, count 2 2006.285.06:44:38.94#ibcon#flushed, iclass 28, count 2 2006.285.06:44:38.94#ibcon#about to write, iclass 28, count 2 2006.285.06:44:38.94#ibcon#wrote, iclass 28, count 2 2006.285.06:44:38.94#ibcon#about to read 3, iclass 28, count 2 2006.285.06:44:38.97#ibcon#read 3, iclass 28, count 2 2006.285.06:44:38.97#ibcon#about to read 4, iclass 28, count 2 2006.285.06:44:38.97#ibcon#read 4, iclass 28, count 2 2006.285.06:44:38.97#ibcon#about to read 5, iclass 28, count 2 2006.285.06:44:38.97#ibcon#read 5, iclass 28, count 2 2006.285.06:44:38.97#ibcon#about to read 6, iclass 28, count 2 2006.285.06:44:38.97#ibcon#read 6, iclass 28, count 2 2006.285.06:44:38.97#ibcon#end of sib2, iclass 28, count 2 2006.285.06:44:38.97#ibcon#*after write, iclass 28, count 2 2006.285.06:44:38.97#ibcon#*before return 0, iclass 28, count 2 2006.285.06:44:38.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:44:38.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:44:38.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.06:44:38.97#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:38.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:44:39.09#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:44:39.09#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:44:39.09#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:44:39.09#ibcon#first serial, iclass 28, count 0 2006.285.06:44:39.09#ibcon#enter sib2, iclass 28, count 0 2006.285.06:44:39.09#ibcon#flushed, iclass 28, count 0 2006.285.06:44:39.09#ibcon#about to write, iclass 28, count 0 2006.285.06:44:39.09#ibcon#wrote, iclass 28, count 0 2006.285.06:44:39.09#ibcon#about to read 3, iclass 28, count 0 2006.285.06:44:39.11#ibcon#read 3, iclass 28, count 0 2006.285.06:44:39.11#ibcon#about to read 4, iclass 28, count 0 2006.285.06:44:39.11#ibcon#read 4, iclass 28, count 0 2006.285.06:44:39.11#ibcon#about to read 5, iclass 28, count 0 2006.285.06:44:39.11#ibcon#read 5, iclass 28, count 0 2006.285.06:44:39.11#ibcon#about to read 6, iclass 28, count 0 2006.285.06:44:39.11#ibcon#read 6, iclass 28, count 0 2006.285.06:44:39.11#ibcon#end of sib2, iclass 28, count 0 2006.285.06:44:39.11#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:44:39.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:44:39.11#ibcon#[27=USB\r\n] 2006.285.06:44:39.11#ibcon#*before write, iclass 28, count 0 2006.285.06:44:39.11#ibcon#enter sib2, iclass 28, count 0 2006.285.06:44:39.11#ibcon#flushed, iclass 28, count 0 2006.285.06:44:39.11#ibcon#about to write, iclass 28, count 0 2006.285.06:44:39.11#ibcon#wrote, iclass 28, count 0 2006.285.06:44:39.11#ibcon#about to read 3, iclass 28, count 0 2006.285.06:44:39.14#ibcon#read 3, iclass 28, count 0 2006.285.06:44:39.14#ibcon#about to read 4, iclass 28, count 0 2006.285.06:44:39.14#ibcon#read 4, iclass 28, count 0 2006.285.06:44:39.14#ibcon#about to read 5, iclass 28, count 0 2006.285.06:44:39.14#ibcon#read 5, iclass 28, count 0 2006.285.06:44:39.14#ibcon#about to read 6, iclass 28, count 0 2006.285.06:44:39.14#ibcon#read 6, iclass 28, count 0 2006.285.06:44:39.14#ibcon#end of sib2, iclass 28, count 0 2006.285.06:44:39.14#ibcon#*after write, iclass 28, count 0 2006.285.06:44:39.14#ibcon#*before return 0, iclass 28, count 0 2006.285.06:44:39.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:44:39.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:44:39.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:44:39.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:44:39.14$vck44/vblo=7,734.99 2006.285.06:44:39.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.06:44:39.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.06:44:39.14#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:39.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:44:39.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:44:39.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:44:39.14#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:44:39.14#ibcon#first serial, iclass 30, count 0 2006.285.06:44:39.14#ibcon#enter sib2, iclass 30, count 0 2006.285.06:44:39.14#ibcon#flushed, iclass 30, count 0 2006.285.06:44:39.14#ibcon#about to write, iclass 30, count 0 2006.285.06:44:39.14#ibcon#wrote, iclass 30, count 0 2006.285.06:44:39.14#ibcon#about to read 3, iclass 30, count 0 2006.285.06:44:39.16#ibcon#read 3, iclass 30, count 0 2006.285.06:44:39.16#ibcon#about to read 4, iclass 30, count 0 2006.285.06:44:39.16#ibcon#read 4, iclass 30, count 0 2006.285.06:44:39.16#ibcon#about to read 5, iclass 30, count 0 2006.285.06:44:39.16#ibcon#read 5, iclass 30, count 0 2006.285.06:44:39.16#ibcon#about to read 6, iclass 30, count 0 2006.285.06:44:39.16#ibcon#read 6, iclass 30, count 0 2006.285.06:44:39.16#ibcon#end of sib2, iclass 30, count 0 2006.285.06:44:39.16#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:44:39.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:44:39.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:44:39.16#ibcon#*before write, iclass 30, count 0 2006.285.06:44:39.16#ibcon#enter sib2, iclass 30, count 0 2006.285.06:44:39.16#ibcon#flushed, iclass 30, count 0 2006.285.06:44:39.16#ibcon#about to write, iclass 30, count 0 2006.285.06:44:39.16#ibcon#wrote, iclass 30, count 0 2006.285.06:44:39.16#ibcon#about to read 3, iclass 30, count 0 2006.285.06:44:39.20#ibcon#read 3, iclass 30, count 0 2006.285.06:44:39.20#ibcon#about to read 4, iclass 30, count 0 2006.285.06:44:39.20#ibcon#read 4, iclass 30, count 0 2006.285.06:44:39.20#ibcon#about to read 5, iclass 30, count 0 2006.285.06:44:39.20#ibcon#read 5, iclass 30, count 0 2006.285.06:44:39.20#ibcon#about to read 6, iclass 30, count 0 2006.285.06:44:39.20#ibcon#read 6, iclass 30, count 0 2006.285.06:44:39.20#ibcon#end of sib2, iclass 30, count 0 2006.285.06:44:39.20#ibcon#*after write, iclass 30, count 0 2006.285.06:44:39.20#ibcon#*before return 0, iclass 30, count 0 2006.285.06:44:39.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:44:39.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:44:39.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:44:39.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:44:39.20$vck44/vb=7,4 2006.285.06:44:39.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.06:44:39.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.06:44:39.20#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:39.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:44:39.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:44:39.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:44:39.26#ibcon#enter wrdev, iclass 32, count 2 2006.285.06:44:39.26#ibcon#first serial, iclass 32, count 2 2006.285.06:44:39.26#ibcon#enter sib2, iclass 32, count 2 2006.285.06:44:39.26#ibcon#flushed, iclass 32, count 2 2006.285.06:44:39.26#ibcon#about to write, iclass 32, count 2 2006.285.06:44:39.26#ibcon#wrote, iclass 32, count 2 2006.285.06:44:39.26#ibcon#about to read 3, iclass 32, count 2 2006.285.06:44:39.28#ibcon#read 3, iclass 32, count 2 2006.285.06:44:39.28#ibcon#about to read 4, iclass 32, count 2 2006.285.06:44:39.28#ibcon#read 4, iclass 32, count 2 2006.285.06:44:39.28#ibcon#about to read 5, iclass 32, count 2 2006.285.06:44:39.28#ibcon#read 5, iclass 32, count 2 2006.285.06:44:39.28#ibcon#about to read 6, iclass 32, count 2 2006.285.06:44:39.28#ibcon#read 6, iclass 32, count 2 2006.285.06:44:39.28#ibcon#end of sib2, iclass 32, count 2 2006.285.06:44:39.28#ibcon#*mode == 0, iclass 32, count 2 2006.285.06:44:39.28#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.06:44:39.28#ibcon#[27=AT07-04\r\n] 2006.285.06:44:39.28#ibcon#*before write, iclass 32, count 2 2006.285.06:44:39.28#ibcon#enter sib2, iclass 32, count 2 2006.285.06:44:39.28#ibcon#flushed, iclass 32, count 2 2006.285.06:44:39.28#ibcon#about to write, iclass 32, count 2 2006.285.06:44:39.28#ibcon#wrote, iclass 32, count 2 2006.285.06:44:39.28#ibcon#about to read 3, iclass 32, count 2 2006.285.06:44:39.31#ibcon#read 3, iclass 32, count 2 2006.285.06:44:39.31#ibcon#about to read 4, iclass 32, count 2 2006.285.06:44:39.31#ibcon#read 4, iclass 32, count 2 2006.285.06:44:39.31#ibcon#about to read 5, iclass 32, count 2 2006.285.06:44:39.31#ibcon#read 5, iclass 32, count 2 2006.285.06:44:39.31#ibcon#about to read 6, iclass 32, count 2 2006.285.06:44:39.31#ibcon#read 6, iclass 32, count 2 2006.285.06:44:39.31#ibcon#end of sib2, iclass 32, count 2 2006.285.06:44:39.31#ibcon#*after write, iclass 32, count 2 2006.285.06:44:39.31#ibcon#*before return 0, iclass 32, count 2 2006.285.06:44:39.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:44:39.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:44:39.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.06:44:39.31#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:39.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:44:39.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:44:39.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:44:39.43#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:44:39.43#ibcon#first serial, iclass 32, count 0 2006.285.06:44:39.43#ibcon#enter sib2, iclass 32, count 0 2006.285.06:44:39.43#ibcon#flushed, iclass 32, count 0 2006.285.06:44:39.43#ibcon#about to write, iclass 32, count 0 2006.285.06:44:39.43#ibcon#wrote, iclass 32, count 0 2006.285.06:44:39.43#ibcon#about to read 3, iclass 32, count 0 2006.285.06:44:39.45#ibcon#read 3, iclass 32, count 0 2006.285.06:44:39.45#ibcon#about to read 4, iclass 32, count 0 2006.285.06:44:39.45#ibcon#read 4, iclass 32, count 0 2006.285.06:44:39.45#ibcon#about to read 5, iclass 32, count 0 2006.285.06:44:39.45#ibcon#read 5, iclass 32, count 0 2006.285.06:44:39.45#ibcon#about to read 6, iclass 32, count 0 2006.285.06:44:39.45#ibcon#read 6, iclass 32, count 0 2006.285.06:44:39.45#ibcon#end of sib2, iclass 32, count 0 2006.285.06:44:39.45#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:44:39.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:44:39.45#ibcon#[27=USB\r\n] 2006.285.06:44:39.45#ibcon#*before write, iclass 32, count 0 2006.285.06:44:39.45#ibcon#enter sib2, iclass 32, count 0 2006.285.06:44:39.45#ibcon#flushed, iclass 32, count 0 2006.285.06:44:39.45#ibcon#about to write, iclass 32, count 0 2006.285.06:44:39.45#ibcon#wrote, iclass 32, count 0 2006.285.06:44:39.45#ibcon#about to read 3, iclass 32, count 0 2006.285.06:44:39.48#ibcon#read 3, iclass 32, count 0 2006.285.06:44:39.48#ibcon#about to read 4, iclass 32, count 0 2006.285.06:44:39.48#ibcon#read 4, iclass 32, count 0 2006.285.06:44:39.48#ibcon#about to read 5, iclass 32, count 0 2006.285.06:44:39.48#ibcon#read 5, iclass 32, count 0 2006.285.06:44:39.48#ibcon#about to read 6, iclass 32, count 0 2006.285.06:44:39.48#ibcon#read 6, iclass 32, count 0 2006.285.06:44:39.48#ibcon#end of sib2, iclass 32, count 0 2006.285.06:44:39.48#ibcon#*after write, iclass 32, count 0 2006.285.06:44:39.48#ibcon#*before return 0, iclass 32, count 0 2006.285.06:44:39.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:44:39.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:44:39.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:44:39.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:44:39.48$vck44/vblo=8,744.99 2006.285.06:44:39.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.06:44:39.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.06:44:39.48#ibcon#ireg 17 cls_cnt 0 2006.285.06:44:39.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:44:39.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:44:39.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:44:39.48#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:44:39.48#ibcon#first serial, iclass 34, count 0 2006.285.06:44:39.48#ibcon#enter sib2, iclass 34, count 0 2006.285.06:44:39.48#ibcon#flushed, iclass 34, count 0 2006.285.06:44:39.48#ibcon#about to write, iclass 34, count 0 2006.285.06:44:39.48#ibcon#wrote, iclass 34, count 0 2006.285.06:44:39.48#ibcon#about to read 3, iclass 34, count 0 2006.285.06:44:39.50#ibcon#read 3, iclass 34, count 0 2006.285.06:44:39.50#ibcon#about to read 4, iclass 34, count 0 2006.285.06:44:39.50#ibcon#read 4, iclass 34, count 0 2006.285.06:44:39.50#ibcon#about to read 5, iclass 34, count 0 2006.285.06:44:39.50#ibcon#read 5, iclass 34, count 0 2006.285.06:44:39.50#ibcon#about to read 6, iclass 34, count 0 2006.285.06:44:39.50#ibcon#read 6, iclass 34, count 0 2006.285.06:44:39.50#ibcon#end of sib2, iclass 34, count 0 2006.285.06:44:39.50#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:44:39.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:44:39.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:44:39.50#ibcon#*before write, iclass 34, count 0 2006.285.06:44:39.50#ibcon#enter sib2, iclass 34, count 0 2006.285.06:44:39.50#ibcon#flushed, iclass 34, count 0 2006.285.06:44:39.50#ibcon#about to write, iclass 34, count 0 2006.285.06:44:39.50#ibcon#wrote, iclass 34, count 0 2006.285.06:44:39.50#ibcon#about to read 3, iclass 34, count 0 2006.285.06:44:39.54#ibcon#read 3, iclass 34, count 0 2006.285.06:44:39.54#ibcon#about to read 4, iclass 34, count 0 2006.285.06:44:39.54#ibcon#read 4, iclass 34, count 0 2006.285.06:44:39.54#ibcon#about to read 5, iclass 34, count 0 2006.285.06:44:39.54#ibcon#read 5, iclass 34, count 0 2006.285.06:44:39.54#ibcon#about to read 6, iclass 34, count 0 2006.285.06:44:39.54#ibcon#read 6, iclass 34, count 0 2006.285.06:44:39.54#ibcon#end of sib2, iclass 34, count 0 2006.285.06:44:39.54#ibcon#*after write, iclass 34, count 0 2006.285.06:44:39.54#ibcon#*before return 0, iclass 34, count 0 2006.285.06:44:39.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:44:39.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:44:39.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:44:39.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:44:39.54$vck44/vb=8,4 2006.285.06:44:39.54#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.06:44:39.54#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.06:44:39.54#ibcon#ireg 11 cls_cnt 2 2006.285.06:44:39.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:44:39.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:44:39.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:44:39.60#ibcon#enter wrdev, iclass 36, count 2 2006.285.06:44:39.60#ibcon#first serial, iclass 36, count 2 2006.285.06:44:39.60#ibcon#enter sib2, iclass 36, count 2 2006.285.06:44:39.60#ibcon#flushed, iclass 36, count 2 2006.285.06:44:39.60#ibcon#about to write, iclass 36, count 2 2006.285.06:44:39.60#ibcon#wrote, iclass 36, count 2 2006.285.06:44:39.60#ibcon#about to read 3, iclass 36, count 2 2006.285.06:44:39.62#ibcon#read 3, iclass 36, count 2 2006.285.06:44:39.62#ibcon#about to read 4, iclass 36, count 2 2006.285.06:44:39.62#ibcon#read 4, iclass 36, count 2 2006.285.06:44:39.62#ibcon#about to read 5, iclass 36, count 2 2006.285.06:44:39.62#ibcon#read 5, iclass 36, count 2 2006.285.06:44:39.62#ibcon#about to read 6, iclass 36, count 2 2006.285.06:44:39.62#ibcon#read 6, iclass 36, count 2 2006.285.06:44:39.62#ibcon#end of sib2, iclass 36, count 2 2006.285.06:44:39.62#ibcon#*mode == 0, iclass 36, count 2 2006.285.06:44:39.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.06:44:39.62#ibcon#[27=AT08-04\r\n] 2006.285.06:44:39.62#ibcon#*before write, iclass 36, count 2 2006.285.06:44:39.62#ibcon#enter sib2, iclass 36, count 2 2006.285.06:44:39.62#ibcon#flushed, iclass 36, count 2 2006.285.06:44:39.62#ibcon#about to write, iclass 36, count 2 2006.285.06:44:39.62#ibcon#wrote, iclass 36, count 2 2006.285.06:44:39.62#ibcon#about to read 3, iclass 36, count 2 2006.285.06:44:39.65#ibcon#read 3, iclass 36, count 2 2006.285.06:44:39.65#ibcon#about to read 4, iclass 36, count 2 2006.285.06:44:39.65#ibcon#read 4, iclass 36, count 2 2006.285.06:44:39.65#ibcon#about to read 5, iclass 36, count 2 2006.285.06:44:39.65#ibcon#read 5, iclass 36, count 2 2006.285.06:44:39.65#ibcon#about to read 6, iclass 36, count 2 2006.285.06:44:39.65#ibcon#read 6, iclass 36, count 2 2006.285.06:44:39.65#ibcon#end of sib2, iclass 36, count 2 2006.285.06:44:39.65#ibcon#*after write, iclass 36, count 2 2006.285.06:44:39.65#ibcon#*before return 0, iclass 36, count 2 2006.285.06:44:39.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:44:39.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:44:39.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.06:44:39.65#ibcon#ireg 7 cls_cnt 0 2006.285.06:44:39.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:44:39.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:44:39.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:44:39.77#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:44:39.77#ibcon#first serial, iclass 36, count 0 2006.285.06:44:39.77#ibcon#enter sib2, iclass 36, count 0 2006.285.06:44:39.77#ibcon#flushed, iclass 36, count 0 2006.285.06:44:39.77#ibcon#about to write, iclass 36, count 0 2006.285.06:44:39.77#ibcon#wrote, iclass 36, count 0 2006.285.06:44:39.77#ibcon#about to read 3, iclass 36, count 0 2006.285.06:44:39.79#ibcon#read 3, iclass 36, count 0 2006.285.06:44:39.79#ibcon#about to read 4, iclass 36, count 0 2006.285.06:44:39.79#ibcon#read 4, iclass 36, count 0 2006.285.06:44:39.79#ibcon#about to read 5, iclass 36, count 0 2006.285.06:44:39.79#ibcon#read 5, iclass 36, count 0 2006.285.06:44:39.79#ibcon#about to read 6, iclass 36, count 0 2006.285.06:44:39.79#ibcon#read 6, iclass 36, count 0 2006.285.06:44:39.79#ibcon#end of sib2, iclass 36, count 0 2006.285.06:44:39.79#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:44:39.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:44:39.79#ibcon#[27=USB\r\n] 2006.285.06:44:39.79#ibcon#*before write, iclass 36, count 0 2006.285.06:44:39.79#ibcon#enter sib2, iclass 36, count 0 2006.285.06:44:39.79#ibcon#flushed, iclass 36, count 0 2006.285.06:44:39.79#ibcon#about to write, iclass 36, count 0 2006.285.06:44:39.79#ibcon#wrote, iclass 36, count 0 2006.285.06:44:39.79#ibcon#about to read 3, iclass 36, count 0 2006.285.06:44:39.82#ibcon#read 3, iclass 36, count 0 2006.285.06:44:39.82#ibcon#about to read 4, iclass 36, count 0 2006.285.06:44:39.82#ibcon#read 4, iclass 36, count 0 2006.285.06:44:39.82#ibcon#about to read 5, iclass 36, count 0 2006.285.06:44:39.82#ibcon#read 5, iclass 36, count 0 2006.285.06:44:39.82#ibcon#about to read 6, iclass 36, count 0 2006.285.06:44:39.82#ibcon#read 6, iclass 36, count 0 2006.285.06:44:39.82#ibcon#end of sib2, iclass 36, count 0 2006.285.06:44:39.82#ibcon#*after write, iclass 36, count 0 2006.285.06:44:39.82#ibcon#*before return 0, iclass 36, count 0 2006.285.06:44:39.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:44:39.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:44:39.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:44:39.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:44:39.82$vck44/vabw=wide 2006.285.06:44:39.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.06:44:39.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.06:44:39.82#ibcon#ireg 8 cls_cnt 0 2006.285.06:44:39.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:44:39.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:44:39.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:44:39.82#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:44:39.82#ibcon#first serial, iclass 38, count 0 2006.285.06:44:39.82#ibcon#enter sib2, iclass 38, count 0 2006.285.06:44:39.82#ibcon#flushed, iclass 38, count 0 2006.285.06:44:39.82#ibcon#about to write, iclass 38, count 0 2006.285.06:44:39.82#ibcon#wrote, iclass 38, count 0 2006.285.06:44:39.82#ibcon#about to read 3, iclass 38, count 0 2006.285.06:44:39.84#ibcon#read 3, iclass 38, count 0 2006.285.06:44:39.84#ibcon#about to read 4, iclass 38, count 0 2006.285.06:44:39.84#ibcon#read 4, iclass 38, count 0 2006.285.06:44:39.84#ibcon#about to read 5, iclass 38, count 0 2006.285.06:44:39.84#ibcon#read 5, iclass 38, count 0 2006.285.06:44:39.84#ibcon#about to read 6, iclass 38, count 0 2006.285.06:44:39.84#ibcon#read 6, iclass 38, count 0 2006.285.06:44:39.84#ibcon#end of sib2, iclass 38, count 0 2006.285.06:44:39.84#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:44:39.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:44:39.84#ibcon#[25=BW32\r\n] 2006.285.06:44:39.84#ibcon#*before write, iclass 38, count 0 2006.285.06:44:39.84#ibcon#enter sib2, iclass 38, count 0 2006.285.06:44:39.84#ibcon#flushed, iclass 38, count 0 2006.285.06:44:39.84#ibcon#about to write, iclass 38, count 0 2006.285.06:44:39.84#ibcon#wrote, iclass 38, count 0 2006.285.06:44:39.84#ibcon#about to read 3, iclass 38, count 0 2006.285.06:44:39.87#ibcon#read 3, iclass 38, count 0 2006.285.06:44:39.87#ibcon#about to read 4, iclass 38, count 0 2006.285.06:44:39.87#ibcon#read 4, iclass 38, count 0 2006.285.06:44:39.87#ibcon#about to read 5, iclass 38, count 0 2006.285.06:44:39.87#ibcon#read 5, iclass 38, count 0 2006.285.06:44:39.87#ibcon#about to read 6, iclass 38, count 0 2006.285.06:44:39.87#ibcon#read 6, iclass 38, count 0 2006.285.06:44:39.87#ibcon#end of sib2, iclass 38, count 0 2006.285.06:44:39.87#ibcon#*after write, iclass 38, count 0 2006.285.06:44:39.87#ibcon#*before return 0, iclass 38, count 0 2006.285.06:44:39.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:44:39.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:44:39.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:44:39.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:44:39.87$vck44/vbbw=wide 2006.285.06:44:39.87#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.06:44:39.87#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.06:44:39.87#ibcon#ireg 8 cls_cnt 0 2006.285.06:44:39.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:44:39.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:44:39.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:44:39.94#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:44:39.94#ibcon#first serial, iclass 40, count 0 2006.285.06:44:39.94#ibcon#enter sib2, iclass 40, count 0 2006.285.06:44:39.94#ibcon#flushed, iclass 40, count 0 2006.285.06:44:39.94#ibcon#about to write, iclass 40, count 0 2006.285.06:44:39.94#ibcon#wrote, iclass 40, count 0 2006.285.06:44:39.94#ibcon#about to read 3, iclass 40, count 0 2006.285.06:44:39.96#ibcon#read 3, iclass 40, count 0 2006.285.06:44:39.96#ibcon#about to read 4, iclass 40, count 0 2006.285.06:44:39.96#ibcon#read 4, iclass 40, count 0 2006.285.06:44:39.96#ibcon#about to read 5, iclass 40, count 0 2006.285.06:44:39.96#ibcon#read 5, iclass 40, count 0 2006.285.06:44:39.96#ibcon#about to read 6, iclass 40, count 0 2006.285.06:44:39.96#ibcon#read 6, iclass 40, count 0 2006.285.06:44:39.96#ibcon#end of sib2, iclass 40, count 0 2006.285.06:44:39.96#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:44:39.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:44:39.96#ibcon#[27=BW32\r\n] 2006.285.06:44:39.96#ibcon#*before write, iclass 40, count 0 2006.285.06:44:39.96#ibcon#enter sib2, iclass 40, count 0 2006.285.06:44:39.96#ibcon#flushed, iclass 40, count 0 2006.285.06:44:39.96#ibcon#about to write, iclass 40, count 0 2006.285.06:44:39.96#ibcon#wrote, iclass 40, count 0 2006.285.06:44:39.96#ibcon#about to read 3, iclass 40, count 0 2006.285.06:44:39.99#ibcon#read 3, iclass 40, count 0 2006.285.06:44:39.99#ibcon#about to read 4, iclass 40, count 0 2006.285.06:44:39.99#ibcon#read 4, iclass 40, count 0 2006.285.06:44:39.99#ibcon#about to read 5, iclass 40, count 0 2006.285.06:44:39.99#ibcon#read 5, iclass 40, count 0 2006.285.06:44:39.99#ibcon#about to read 6, iclass 40, count 0 2006.285.06:44:39.99#ibcon#read 6, iclass 40, count 0 2006.285.06:44:39.99#ibcon#end of sib2, iclass 40, count 0 2006.285.06:44:39.99#ibcon#*after write, iclass 40, count 0 2006.285.06:44:39.99#ibcon#*before return 0, iclass 40, count 0 2006.285.06:44:39.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:44:39.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.06:44:39.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:44:39.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:44:39.99$setupk4/ifdk4 2006.285.06:44:39.99$ifdk4/lo= 2006.285.06:44:39.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:44:39.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:44:39.99$ifdk4/patch= 2006.285.06:44:39.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:44:39.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:44:39.99$setupk4/!*+20s 2006.285.06:44:40.83#abcon#<5=/05 4.1 7.6 24.72 711014.1\r\n> 2006.285.06:44:40.85#abcon#{5=INTERFACE CLEAR} 2006.285.06:44:40.91#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:44:51.00#abcon#<5=/05 4.1 7.6 24.72 711014.2\r\n> 2006.285.06:44:51.02#abcon#{5=INTERFACE CLEAR} 2006.285.06:44:51.08#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:44:51.14#trakl#Source acquired 2006.285.06:44:53.14#flagr#flagr/antenna,acquired 2006.285.06:44:54.49$setupk4/"tpicd 2006.285.06:44:54.49$setupk4/echo=off 2006.285.06:44:54.49$setupk4/xlog=off 2006.285.06:44:54.49:!2006.285.06:52:11 2006.285.06:51:45.14#trakl#Off source 2006.285.06:51:45.14?ERROR st -7 Antenna off-source! 2006.285.06:51:45.14#trakl#az 118.881 el 16.295 azerr*cos(el) 0.0166 elerr 0.0032 2006.285.06:51:47.14#flagr#flagr/antenna,off-source 2006.285.06:51:51.14#trakl#Source re-acquired 2006.285.06:51:53.14#flagr#flagr/antenna,re-acquired 2006.285.06:52:11.00:preob 2006.285.06:52:12.14/onsource/TRACKING 2006.285.06:52:12.14:!2006.285.06:52:21 2006.285.06:52:21.00:"tape 2006.285.06:52:21.00:"st=record 2006.285.06:52:21.00:data_valid=on 2006.285.06:52:21.00:midob 2006.285.06:52:21.14/onsource/TRACKING 2006.285.06:52:21.14/wx/24.52,1014.2,72 2006.285.06:52:21.22/cable/+6.4712E-03 2006.285.06:52:22.31/va/01,07,usb,yes,34,37 2006.285.06:52:22.31/va/02,06,usb,yes,35,35 2006.285.06:52:22.31/va/03,07,usb,yes,34,36 2006.285.06:52:22.31/va/04,06,usb,yes,36,37 2006.285.06:52:22.31/va/05,03,usb,yes,35,36 2006.285.06:52:22.31/va/06,04,usb,yes,32,31 2006.285.06:52:22.31/va/07,04,usb,yes,32,33 2006.285.06:52:22.31/va/08,03,usb,yes,33,40 2006.285.06:52:22.54/valo/01,524.99,yes,locked 2006.285.06:52:22.54/valo/02,534.99,yes,locked 2006.285.06:52:22.54/valo/03,564.99,yes,locked 2006.285.06:52:22.54/valo/04,624.99,yes,locked 2006.285.06:52:22.54/valo/05,734.99,yes,locked 2006.285.06:52:22.54/valo/06,814.99,yes,locked 2006.285.06:52:22.54/valo/07,864.99,yes,locked 2006.285.06:52:22.54/valo/08,884.99,yes,locked 2006.285.06:52:23.63/vb/01,04,usb,yes,32,30 2006.285.06:52:23.63/vb/02,05,usb,yes,30,30 2006.285.06:52:23.63/vb/03,04,usb,yes,31,34 2006.285.06:52:23.63/vb/04,05,usb,yes,31,30 2006.285.06:52:23.63/vb/05,04,usb,yes,28,30 2006.285.06:52:23.63/vb/06,03,usb,yes,40,35 2006.285.06:52:23.63/vb/07,04,usb,yes,32,32 2006.285.06:52:23.63/vb/08,04,usb,yes,29,33 2006.285.06:52:23.86/vblo/01,629.99,yes,locked 2006.285.06:52:23.86/vblo/02,634.99,yes,locked 2006.285.06:52:23.86/vblo/03,649.99,yes,locked 2006.285.06:52:23.86/vblo/04,679.99,yes,locked 2006.285.06:52:23.86/vblo/05,709.99,yes,locked 2006.285.06:52:23.86/vblo/06,719.99,yes,locked 2006.285.06:52:23.86/vblo/07,734.99,yes,locked 2006.285.06:52:23.86/vblo/08,744.99,yes,locked 2006.285.06:52:24.01/vabw/8 2006.285.06:52:24.16/vbbw/8 2006.285.06:52:24.27/xfe/off,on,12.2 2006.285.06:52:24.65/ifatt/23,28,28,28 2006.285.06:52:25.08/fmout-gps/S +2.59E-07 2006.285.06:52:25.10:!2006.285.06:54:51 2006.285.06:54:51.00:data_valid=off 2006.285.06:54:51.00:"et 2006.285.06:54:51.00:!+3s 2006.285.06:54:54.01:"tape 2006.285.06:54:54.01:postob 2006.285.06:54:54.11/cable/+6.4727E-03 2006.285.06:54:54.11/wx/24.44,1014.2,73 2006.285.06:54:55.07/fmout-gps/S +2.60E-07 2006.285.06:54:55.07:scan_name=285-0702,jd0610,80 2006.285.06:54:55.07:source=2121+053,212344.52,053522.1,2000.0,cw 2006.285.06:54:55.14#flagr#flagr/antenna,new-source 2006.285.06:54:56.14:checkk5 2006.285.06:54:56.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.06:54:56.98/chk_autoobs//k5ts2/ autoobs is running! 2006.285.06:54:57.33/chk_autoobs//k5ts3/ autoobs is running! 2006.285.06:54:57.78/chk_autoobs//k5ts4/ autoobs is running! 2006.285.06:54:58.18/chk_obsdata//k5ts1/T2850652??a.dat file size is correct (nominal:600MB, actual:596MB). 2006.285.06:54:58.56/chk_obsdata//k5ts2/T2850652??b.dat file size is correct (nominal:600MB, actual:596MB). 2006.285.06:54:58.97/chk_obsdata//k5ts3/T2850652??c.dat file size is correct (nominal:600MB, actual:596MB). 2006.285.06:54:59.37/chk_obsdata//k5ts4/T2850652??d.dat file size is correct (nominal:600MB, actual:596MB). 2006.285.06:55:00.12/k5log//k5ts1_log_newline 2006.285.06:55:00.86/k5log//k5ts2_log_newline 2006.285.06:55:01.59/k5log//k5ts3_log_newline 2006.285.06:55:02.33/k5log//k5ts4_log_newline 2006.285.06:55:02.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.06:55:02.35:setupk4=1 2006.285.06:55:02.35$setupk4/echo=on 2006.285.06:55:02.35$setupk4/pcalon 2006.285.06:55:02.35$pcalon/"no phase cal control is implemented here 2006.285.06:55:02.35$setupk4/"tpicd=stop 2006.285.06:55:02.35$setupk4/"rec=synch_on 2006.285.06:55:02.35$setupk4/"rec_mode=128 2006.285.06:55:02.35$setupk4/!* 2006.285.06:55:02.35$setupk4/recpk4 2006.285.06:55:02.35$recpk4/recpatch= 2006.285.06:55:02.36$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.06:55:02.36$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.06:55:02.36$setupk4/vck44 2006.285.06:55:02.36$vck44/valo=1,524.99 2006.285.06:55:02.36#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.06:55:02.36#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.06:55:02.36#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:02.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:55:02.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:55:02.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:55:02.36#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:55:02.36#ibcon#first serial, iclass 34, count 0 2006.285.06:55:02.36#ibcon#enter sib2, iclass 34, count 0 2006.285.06:55:02.36#ibcon#flushed, iclass 34, count 0 2006.285.06:55:02.36#ibcon#about to write, iclass 34, count 0 2006.285.06:55:02.36#ibcon#wrote, iclass 34, count 0 2006.285.06:55:02.36#ibcon#about to read 3, iclass 34, count 0 2006.285.06:55:02.38#ibcon#read 3, iclass 34, count 0 2006.285.06:55:02.38#ibcon#about to read 4, iclass 34, count 0 2006.285.06:55:02.38#ibcon#read 4, iclass 34, count 0 2006.285.06:55:02.38#ibcon#about to read 5, iclass 34, count 0 2006.285.06:55:02.38#ibcon#read 5, iclass 34, count 0 2006.285.06:55:02.38#ibcon#about to read 6, iclass 34, count 0 2006.285.06:55:02.38#ibcon#read 6, iclass 34, count 0 2006.285.06:55:02.38#ibcon#end of sib2, iclass 34, count 0 2006.285.06:55:02.38#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:55:02.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:55:02.38#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.06:55:02.38#ibcon#*before write, iclass 34, count 0 2006.285.06:55:02.38#ibcon#enter sib2, iclass 34, count 0 2006.285.06:55:02.38#ibcon#flushed, iclass 34, count 0 2006.285.06:55:02.38#ibcon#about to write, iclass 34, count 0 2006.285.06:55:02.38#ibcon#wrote, iclass 34, count 0 2006.285.06:55:02.38#ibcon#about to read 3, iclass 34, count 0 2006.285.06:55:02.43#ibcon#read 3, iclass 34, count 0 2006.285.06:55:02.43#ibcon#about to read 4, iclass 34, count 0 2006.285.06:55:02.43#ibcon#read 4, iclass 34, count 0 2006.285.06:55:02.43#ibcon#about to read 5, iclass 34, count 0 2006.285.06:55:02.43#ibcon#read 5, iclass 34, count 0 2006.285.06:55:02.43#ibcon#about to read 6, iclass 34, count 0 2006.285.06:55:02.43#ibcon#read 6, iclass 34, count 0 2006.285.06:55:02.43#ibcon#end of sib2, iclass 34, count 0 2006.285.06:55:02.43#ibcon#*after write, iclass 34, count 0 2006.285.06:55:02.43#ibcon#*before return 0, iclass 34, count 0 2006.285.06:55:02.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:55:02.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:55:02.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:55:02.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:55:02.43$vck44/va=1,7 2006.285.06:55:02.43#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.06:55:02.43#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.06:55:02.43#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:02.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:55:02.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:55:02.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:55:02.43#ibcon#enter wrdev, iclass 36, count 2 2006.285.06:55:02.43#ibcon#first serial, iclass 36, count 2 2006.285.06:55:02.43#ibcon#enter sib2, iclass 36, count 2 2006.285.06:55:02.43#ibcon#flushed, iclass 36, count 2 2006.285.06:55:02.43#ibcon#about to write, iclass 36, count 2 2006.285.06:55:02.43#ibcon#wrote, iclass 36, count 2 2006.285.06:55:02.43#ibcon#about to read 3, iclass 36, count 2 2006.285.06:55:02.45#ibcon#read 3, iclass 36, count 2 2006.285.06:55:02.45#ibcon#about to read 4, iclass 36, count 2 2006.285.06:55:02.45#ibcon#read 4, iclass 36, count 2 2006.285.06:55:02.45#ibcon#about to read 5, iclass 36, count 2 2006.285.06:55:02.45#ibcon#read 5, iclass 36, count 2 2006.285.06:55:02.45#ibcon#about to read 6, iclass 36, count 2 2006.285.06:55:02.45#ibcon#read 6, iclass 36, count 2 2006.285.06:55:02.45#ibcon#end of sib2, iclass 36, count 2 2006.285.06:55:02.45#ibcon#*mode == 0, iclass 36, count 2 2006.285.06:55:02.45#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.06:55:02.45#ibcon#[25=AT01-07\r\n] 2006.285.06:55:02.45#ibcon#*before write, iclass 36, count 2 2006.285.06:55:02.45#ibcon#enter sib2, iclass 36, count 2 2006.285.06:55:02.45#ibcon#flushed, iclass 36, count 2 2006.285.06:55:02.45#ibcon#about to write, iclass 36, count 2 2006.285.06:55:02.45#ibcon#wrote, iclass 36, count 2 2006.285.06:55:02.45#ibcon#about to read 3, iclass 36, count 2 2006.285.06:55:02.48#ibcon#read 3, iclass 36, count 2 2006.285.06:55:02.48#ibcon#about to read 4, iclass 36, count 2 2006.285.06:55:02.48#ibcon#read 4, iclass 36, count 2 2006.285.06:55:02.48#ibcon#about to read 5, iclass 36, count 2 2006.285.06:55:02.48#ibcon#read 5, iclass 36, count 2 2006.285.06:55:02.48#ibcon#about to read 6, iclass 36, count 2 2006.285.06:55:02.48#ibcon#read 6, iclass 36, count 2 2006.285.06:55:02.48#ibcon#end of sib2, iclass 36, count 2 2006.285.06:55:02.48#ibcon#*after write, iclass 36, count 2 2006.285.06:55:02.48#ibcon#*before return 0, iclass 36, count 2 2006.285.06:55:02.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:55:02.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:55:02.48#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.06:55:02.48#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:02.48#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:55:02.60#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:55:02.60#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:55:02.60#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:55:02.60#ibcon#first serial, iclass 36, count 0 2006.285.06:55:02.60#ibcon#enter sib2, iclass 36, count 0 2006.285.06:55:02.60#ibcon#flushed, iclass 36, count 0 2006.285.06:55:02.60#ibcon#about to write, iclass 36, count 0 2006.285.06:55:02.60#ibcon#wrote, iclass 36, count 0 2006.285.06:55:02.60#ibcon#about to read 3, iclass 36, count 0 2006.285.06:55:02.62#ibcon#read 3, iclass 36, count 0 2006.285.06:55:02.62#ibcon#about to read 4, iclass 36, count 0 2006.285.06:55:02.62#ibcon#read 4, iclass 36, count 0 2006.285.06:55:02.62#ibcon#about to read 5, iclass 36, count 0 2006.285.06:55:02.62#ibcon#read 5, iclass 36, count 0 2006.285.06:55:02.62#ibcon#about to read 6, iclass 36, count 0 2006.285.06:55:02.62#ibcon#read 6, iclass 36, count 0 2006.285.06:55:02.62#ibcon#end of sib2, iclass 36, count 0 2006.285.06:55:02.62#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:55:02.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:55:02.62#ibcon#[25=USB\r\n] 2006.285.06:55:02.62#ibcon#*before write, iclass 36, count 0 2006.285.06:55:02.62#ibcon#enter sib2, iclass 36, count 0 2006.285.06:55:02.62#ibcon#flushed, iclass 36, count 0 2006.285.06:55:02.62#ibcon#about to write, iclass 36, count 0 2006.285.06:55:02.62#ibcon#wrote, iclass 36, count 0 2006.285.06:55:02.62#ibcon#about to read 3, iclass 36, count 0 2006.285.06:55:02.65#ibcon#read 3, iclass 36, count 0 2006.285.06:55:02.65#ibcon#about to read 4, iclass 36, count 0 2006.285.06:55:02.65#ibcon#read 4, iclass 36, count 0 2006.285.06:55:02.65#ibcon#about to read 5, iclass 36, count 0 2006.285.06:55:02.65#ibcon#read 5, iclass 36, count 0 2006.285.06:55:02.65#ibcon#about to read 6, iclass 36, count 0 2006.285.06:55:02.65#ibcon#read 6, iclass 36, count 0 2006.285.06:55:02.65#ibcon#end of sib2, iclass 36, count 0 2006.285.06:55:02.65#ibcon#*after write, iclass 36, count 0 2006.285.06:55:02.65#ibcon#*before return 0, iclass 36, count 0 2006.285.06:55:02.65#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:55:02.65#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:55:02.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:55:02.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:55:02.65$vck44/valo=2,534.99 2006.285.06:55:02.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.06:55:02.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.06:55:02.65#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:02.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:55:02.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:55:02.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:55:02.65#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:55:02.65#ibcon#first serial, iclass 38, count 0 2006.285.06:55:02.65#ibcon#enter sib2, iclass 38, count 0 2006.285.06:55:02.65#ibcon#flushed, iclass 38, count 0 2006.285.06:55:02.65#ibcon#about to write, iclass 38, count 0 2006.285.06:55:02.65#ibcon#wrote, iclass 38, count 0 2006.285.06:55:02.65#ibcon#about to read 3, iclass 38, count 0 2006.285.06:55:02.67#ibcon#read 3, iclass 38, count 0 2006.285.06:55:02.67#ibcon#about to read 4, iclass 38, count 0 2006.285.06:55:02.67#ibcon#read 4, iclass 38, count 0 2006.285.06:55:02.67#ibcon#about to read 5, iclass 38, count 0 2006.285.06:55:02.67#ibcon#read 5, iclass 38, count 0 2006.285.06:55:02.67#ibcon#about to read 6, iclass 38, count 0 2006.285.06:55:02.67#ibcon#read 6, iclass 38, count 0 2006.285.06:55:02.67#ibcon#end of sib2, iclass 38, count 0 2006.285.06:55:02.67#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:55:02.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:55:02.67#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.06:55:02.67#ibcon#*before write, iclass 38, count 0 2006.285.06:55:02.67#ibcon#enter sib2, iclass 38, count 0 2006.285.06:55:02.67#ibcon#flushed, iclass 38, count 0 2006.285.06:55:02.67#ibcon#about to write, iclass 38, count 0 2006.285.06:55:02.67#ibcon#wrote, iclass 38, count 0 2006.285.06:55:02.67#ibcon#about to read 3, iclass 38, count 0 2006.285.06:55:02.71#ibcon#read 3, iclass 38, count 0 2006.285.06:55:02.71#ibcon#about to read 4, iclass 38, count 0 2006.285.06:55:02.71#ibcon#read 4, iclass 38, count 0 2006.285.06:55:02.71#ibcon#about to read 5, iclass 38, count 0 2006.285.06:55:02.71#ibcon#read 5, iclass 38, count 0 2006.285.06:55:02.71#ibcon#about to read 6, iclass 38, count 0 2006.285.06:55:02.71#ibcon#read 6, iclass 38, count 0 2006.285.06:55:02.71#ibcon#end of sib2, iclass 38, count 0 2006.285.06:55:02.71#ibcon#*after write, iclass 38, count 0 2006.285.06:55:02.71#ibcon#*before return 0, iclass 38, count 0 2006.285.06:55:02.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:55:02.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:55:02.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:55:02.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:55:02.71$vck44/va=2,6 2006.285.06:55:02.71#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.06:55:02.71#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.06:55:02.71#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:02.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:55:02.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:55:02.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:55:02.77#ibcon#enter wrdev, iclass 40, count 2 2006.285.06:55:02.77#ibcon#first serial, iclass 40, count 2 2006.285.06:55:02.77#ibcon#enter sib2, iclass 40, count 2 2006.285.06:55:02.77#ibcon#flushed, iclass 40, count 2 2006.285.06:55:02.77#ibcon#about to write, iclass 40, count 2 2006.285.06:55:02.77#ibcon#wrote, iclass 40, count 2 2006.285.06:55:02.77#ibcon#about to read 3, iclass 40, count 2 2006.285.06:55:02.79#ibcon#read 3, iclass 40, count 2 2006.285.06:55:02.79#ibcon#about to read 4, iclass 40, count 2 2006.285.06:55:02.79#ibcon#read 4, iclass 40, count 2 2006.285.06:55:02.79#ibcon#about to read 5, iclass 40, count 2 2006.285.06:55:02.79#ibcon#read 5, iclass 40, count 2 2006.285.06:55:02.79#ibcon#about to read 6, iclass 40, count 2 2006.285.06:55:02.79#ibcon#read 6, iclass 40, count 2 2006.285.06:55:02.79#ibcon#end of sib2, iclass 40, count 2 2006.285.06:55:02.79#ibcon#*mode == 0, iclass 40, count 2 2006.285.06:55:02.79#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.06:55:02.79#ibcon#[25=AT02-06\r\n] 2006.285.06:55:02.79#ibcon#*before write, iclass 40, count 2 2006.285.06:55:02.79#ibcon#enter sib2, iclass 40, count 2 2006.285.06:55:02.79#ibcon#flushed, iclass 40, count 2 2006.285.06:55:02.79#ibcon#about to write, iclass 40, count 2 2006.285.06:55:02.79#ibcon#wrote, iclass 40, count 2 2006.285.06:55:02.79#ibcon#about to read 3, iclass 40, count 2 2006.285.06:55:02.82#ibcon#read 3, iclass 40, count 2 2006.285.06:55:02.82#ibcon#about to read 4, iclass 40, count 2 2006.285.06:55:02.82#ibcon#read 4, iclass 40, count 2 2006.285.06:55:02.82#ibcon#about to read 5, iclass 40, count 2 2006.285.06:55:02.82#ibcon#read 5, iclass 40, count 2 2006.285.06:55:02.82#ibcon#about to read 6, iclass 40, count 2 2006.285.06:55:02.82#ibcon#read 6, iclass 40, count 2 2006.285.06:55:02.82#ibcon#end of sib2, iclass 40, count 2 2006.285.06:55:02.82#ibcon#*after write, iclass 40, count 2 2006.285.06:55:02.82#ibcon#*before return 0, iclass 40, count 2 2006.285.06:55:02.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:55:02.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:55:02.82#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.06:55:02.82#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:02.82#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:55:02.94#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:55:02.94#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:55:02.94#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:55:02.94#ibcon#first serial, iclass 40, count 0 2006.285.06:55:02.94#ibcon#enter sib2, iclass 40, count 0 2006.285.06:55:02.94#ibcon#flushed, iclass 40, count 0 2006.285.06:55:02.94#ibcon#about to write, iclass 40, count 0 2006.285.06:55:02.94#ibcon#wrote, iclass 40, count 0 2006.285.06:55:02.94#ibcon#about to read 3, iclass 40, count 0 2006.285.06:55:02.96#ibcon#read 3, iclass 40, count 0 2006.285.06:55:02.96#ibcon#about to read 4, iclass 40, count 0 2006.285.06:55:02.96#ibcon#read 4, iclass 40, count 0 2006.285.06:55:02.96#ibcon#about to read 5, iclass 40, count 0 2006.285.06:55:02.96#ibcon#read 5, iclass 40, count 0 2006.285.06:55:02.96#ibcon#about to read 6, iclass 40, count 0 2006.285.06:55:02.96#ibcon#read 6, iclass 40, count 0 2006.285.06:55:02.96#ibcon#end of sib2, iclass 40, count 0 2006.285.06:55:02.96#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:55:02.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:55:02.96#ibcon#[25=USB\r\n] 2006.285.06:55:02.96#ibcon#*before write, iclass 40, count 0 2006.285.06:55:02.96#ibcon#enter sib2, iclass 40, count 0 2006.285.06:55:02.96#ibcon#flushed, iclass 40, count 0 2006.285.06:55:02.96#ibcon#about to write, iclass 40, count 0 2006.285.06:55:02.96#ibcon#wrote, iclass 40, count 0 2006.285.06:55:02.96#ibcon#about to read 3, iclass 40, count 0 2006.285.06:55:02.99#ibcon#read 3, iclass 40, count 0 2006.285.06:55:02.99#ibcon#about to read 4, iclass 40, count 0 2006.285.06:55:02.99#ibcon#read 4, iclass 40, count 0 2006.285.06:55:02.99#ibcon#about to read 5, iclass 40, count 0 2006.285.06:55:02.99#ibcon#read 5, iclass 40, count 0 2006.285.06:55:02.99#ibcon#about to read 6, iclass 40, count 0 2006.285.06:55:02.99#ibcon#read 6, iclass 40, count 0 2006.285.06:55:02.99#ibcon#end of sib2, iclass 40, count 0 2006.285.06:55:02.99#ibcon#*after write, iclass 40, count 0 2006.285.06:55:02.99#ibcon#*before return 0, iclass 40, count 0 2006.285.06:55:02.99#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:55:02.99#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:55:02.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:55:02.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:55:02.99$vck44/valo=3,564.99 2006.285.06:55:02.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.06:55:02.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.06:55:02.99#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:02.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:55:02.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:55:02.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:55:02.99#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:55:02.99#ibcon#first serial, iclass 4, count 0 2006.285.06:55:02.99#ibcon#enter sib2, iclass 4, count 0 2006.285.06:55:02.99#ibcon#flushed, iclass 4, count 0 2006.285.06:55:02.99#ibcon#about to write, iclass 4, count 0 2006.285.06:55:02.99#ibcon#wrote, iclass 4, count 0 2006.285.06:55:02.99#ibcon#about to read 3, iclass 4, count 0 2006.285.06:55:03.01#ibcon#read 3, iclass 4, count 0 2006.285.06:55:03.01#ibcon#about to read 4, iclass 4, count 0 2006.285.06:55:03.01#ibcon#read 4, iclass 4, count 0 2006.285.06:55:03.01#ibcon#about to read 5, iclass 4, count 0 2006.285.06:55:03.01#ibcon#read 5, iclass 4, count 0 2006.285.06:55:03.01#ibcon#about to read 6, iclass 4, count 0 2006.285.06:55:03.01#ibcon#read 6, iclass 4, count 0 2006.285.06:55:03.01#ibcon#end of sib2, iclass 4, count 0 2006.285.06:55:03.01#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:55:03.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:55:03.01#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.06:55:03.01#ibcon#*before write, iclass 4, count 0 2006.285.06:55:03.01#ibcon#enter sib2, iclass 4, count 0 2006.285.06:55:03.01#ibcon#flushed, iclass 4, count 0 2006.285.06:55:03.01#ibcon#about to write, iclass 4, count 0 2006.285.06:55:03.01#ibcon#wrote, iclass 4, count 0 2006.285.06:55:03.01#ibcon#about to read 3, iclass 4, count 0 2006.285.06:55:03.05#ibcon#read 3, iclass 4, count 0 2006.285.06:55:03.05#ibcon#about to read 4, iclass 4, count 0 2006.285.06:55:03.05#ibcon#read 4, iclass 4, count 0 2006.285.06:55:03.05#ibcon#about to read 5, iclass 4, count 0 2006.285.06:55:03.05#ibcon#read 5, iclass 4, count 0 2006.285.06:55:03.05#ibcon#about to read 6, iclass 4, count 0 2006.285.06:55:03.05#ibcon#read 6, iclass 4, count 0 2006.285.06:55:03.05#ibcon#end of sib2, iclass 4, count 0 2006.285.06:55:03.05#ibcon#*after write, iclass 4, count 0 2006.285.06:55:03.05#ibcon#*before return 0, iclass 4, count 0 2006.285.06:55:03.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:55:03.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:55:03.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:55:03.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:55:03.05$vck44/va=3,7 2006.285.06:55:03.05#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.06:55:03.05#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.06:55:03.05#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:03.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:55:03.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:55:03.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:55:03.11#ibcon#enter wrdev, iclass 6, count 2 2006.285.06:55:03.11#ibcon#first serial, iclass 6, count 2 2006.285.06:55:03.11#ibcon#enter sib2, iclass 6, count 2 2006.285.06:55:03.11#ibcon#flushed, iclass 6, count 2 2006.285.06:55:03.11#ibcon#about to write, iclass 6, count 2 2006.285.06:55:03.11#ibcon#wrote, iclass 6, count 2 2006.285.06:55:03.11#ibcon#about to read 3, iclass 6, count 2 2006.285.06:55:03.13#ibcon#read 3, iclass 6, count 2 2006.285.06:55:03.13#ibcon#about to read 4, iclass 6, count 2 2006.285.06:55:03.13#ibcon#read 4, iclass 6, count 2 2006.285.06:55:03.13#ibcon#about to read 5, iclass 6, count 2 2006.285.06:55:03.13#ibcon#read 5, iclass 6, count 2 2006.285.06:55:03.13#ibcon#about to read 6, iclass 6, count 2 2006.285.06:55:03.13#ibcon#read 6, iclass 6, count 2 2006.285.06:55:03.13#ibcon#end of sib2, iclass 6, count 2 2006.285.06:55:03.13#ibcon#*mode == 0, iclass 6, count 2 2006.285.06:55:03.13#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.06:55:03.13#ibcon#[25=AT03-07\r\n] 2006.285.06:55:03.13#ibcon#*before write, iclass 6, count 2 2006.285.06:55:03.13#ibcon#enter sib2, iclass 6, count 2 2006.285.06:55:03.13#ibcon#flushed, iclass 6, count 2 2006.285.06:55:03.13#ibcon#about to write, iclass 6, count 2 2006.285.06:55:03.13#ibcon#wrote, iclass 6, count 2 2006.285.06:55:03.13#ibcon#about to read 3, iclass 6, count 2 2006.285.06:55:03.16#ibcon#read 3, iclass 6, count 2 2006.285.06:55:03.16#ibcon#about to read 4, iclass 6, count 2 2006.285.06:55:03.16#ibcon#read 4, iclass 6, count 2 2006.285.06:55:03.16#ibcon#about to read 5, iclass 6, count 2 2006.285.06:55:03.16#ibcon#read 5, iclass 6, count 2 2006.285.06:55:03.16#ibcon#about to read 6, iclass 6, count 2 2006.285.06:55:03.16#ibcon#read 6, iclass 6, count 2 2006.285.06:55:03.16#ibcon#end of sib2, iclass 6, count 2 2006.285.06:55:03.16#ibcon#*after write, iclass 6, count 2 2006.285.06:55:03.16#ibcon#*before return 0, iclass 6, count 2 2006.285.06:55:03.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:55:03.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:55:03.16#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.06:55:03.16#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:03.16#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:55:03.28#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:55:03.28#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:55:03.28#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:55:03.28#ibcon#first serial, iclass 6, count 0 2006.285.06:55:03.28#ibcon#enter sib2, iclass 6, count 0 2006.285.06:55:03.28#ibcon#flushed, iclass 6, count 0 2006.285.06:55:03.28#ibcon#about to write, iclass 6, count 0 2006.285.06:55:03.28#ibcon#wrote, iclass 6, count 0 2006.285.06:55:03.28#ibcon#about to read 3, iclass 6, count 0 2006.285.06:55:03.30#ibcon#read 3, iclass 6, count 0 2006.285.06:55:03.30#ibcon#about to read 4, iclass 6, count 0 2006.285.06:55:03.30#ibcon#read 4, iclass 6, count 0 2006.285.06:55:03.30#ibcon#about to read 5, iclass 6, count 0 2006.285.06:55:03.30#ibcon#read 5, iclass 6, count 0 2006.285.06:55:03.30#ibcon#about to read 6, iclass 6, count 0 2006.285.06:55:03.30#ibcon#read 6, iclass 6, count 0 2006.285.06:55:03.30#ibcon#end of sib2, iclass 6, count 0 2006.285.06:55:03.30#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:55:03.30#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:55:03.30#ibcon#[25=USB\r\n] 2006.285.06:55:03.30#ibcon#*before write, iclass 6, count 0 2006.285.06:55:03.30#ibcon#enter sib2, iclass 6, count 0 2006.285.06:55:03.30#ibcon#flushed, iclass 6, count 0 2006.285.06:55:03.30#ibcon#about to write, iclass 6, count 0 2006.285.06:55:03.30#ibcon#wrote, iclass 6, count 0 2006.285.06:55:03.30#ibcon#about to read 3, iclass 6, count 0 2006.285.06:55:03.33#ibcon#read 3, iclass 6, count 0 2006.285.06:55:03.33#ibcon#about to read 4, iclass 6, count 0 2006.285.06:55:03.33#ibcon#read 4, iclass 6, count 0 2006.285.06:55:03.33#ibcon#about to read 5, iclass 6, count 0 2006.285.06:55:03.33#ibcon#read 5, iclass 6, count 0 2006.285.06:55:03.33#ibcon#about to read 6, iclass 6, count 0 2006.285.06:55:03.33#ibcon#read 6, iclass 6, count 0 2006.285.06:55:03.33#ibcon#end of sib2, iclass 6, count 0 2006.285.06:55:03.33#ibcon#*after write, iclass 6, count 0 2006.285.06:55:03.33#ibcon#*before return 0, iclass 6, count 0 2006.285.06:55:03.33#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:55:03.33#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:55:03.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:55:03.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:55:03.33$vck44/valo=4,624.99 2006.285.06:55:03.33#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.06:55:03.33#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.06:55:03.33#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:03.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:55:03.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:55:03.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:55:03.33#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:55:03.33#ibcon#first serial, iclass 10, count 0 2006.285.06:55:03.33#ibcon#enter sib2, iclass 10, count 0 2006.285.06:55:03.33#ibcon#flushed, iclass 10, count 0 2006.285.06:55:03.33#ibcon#about to write, iclass 10, count 0 2006.285.06:55:03.33#ibcon#wrote, iclass 10, count 0 2006.285.06:55:03.33#ibcon#about to read 3, iclass 10, count 0 2006.285.06:55:03.35#ibcon#read 3, iclass 10, count 0 2006.285.06:55:03.35#ibcon#about to read 4, iclass 10, count 0 2006.285.06:55:03.35#ibcon#read 4, iclass 10, count 0 2006.285.06:55:03.35#ibcon#about to read 5, iclass 10, count 0 2006.285.06:55:03.35#ibcon#read 5, iclass 10, count 0 2006.285.06:55:03.35#ibcon#about to read 6, iclass 10, count 0 2006.285.06:55:03.35#ibcon#read 6, iclass 10, count 0 2006.285.06:55:03.35#ibcon#end of sib2, iclass 10, count 0 2006.285.06:55:03.35#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:55:03.35#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:55:03.35#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.06:55:03.35#ibcon#*before write, iclass 10, count 0 2006.285.06:55:03.35#ibcon#enter sib2, iclass 10, count 0 2006.285.06:55:03.35#ibcon#flushed, iclass 10, count 0 2006.285.06:55:03.35#ibcon#about to write, iclass 10, count 0 2006.285.06:55:03.35#ibcon#wrote, iclass 10, count 0 2006.285.06:55:03.35#ibcon#about to read 3, iclass 10, count 0 2006.285.06:55:03.39#ibcon#read 3, iclass 10, count 0 2006.285.06:55:03.39#ibcon#about to read 4, iclass 10, count 0 2006.285.06:55:03.39#ibcon#read 4, iclass 10, count 0 2006.285.06:55:03.39#ibcon#about to read 5, iclass 10, count 0 2006.285.06:55:03.39#ibcon#read 5, iclass 10, count 0 2006.285.06:55:03.39#ibcon#about to read 6, iclass 10, count 0 2006.285.06:55:03.39#ibcon#read 6, iclass 10, count 0 2006.285.06:55:03.39#ibcon#end of sib2, iclass 10, count 0 2006.285.06:55:03.39#ibcon#*after write, iclass 10, count 0 2006.285.06:55:03.39#ibcon#*before return 0, iclass 10, count 0 2006.285.06:55:03.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:55:03.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:55:03.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:55:03.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:55:03.39$vck44/va=4,6 2006.285.06:55:03.39#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.06:55:03.39#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.06:55:03.39#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:03.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:55:03.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:55:03.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:55:03.45#ibcon#enter wrdev, iclass 12, count 2 2006.285.06:55:03.45#ibcon#first serial, iclass 12, count 2 2006.285.06:55:03.45#ibcon#enter sib2, iclass 12, count 2 2006.285.06:55:03.45#ibcon#flushed, iclass 12, count 2 2006.285.06:55:03.45#ibcon#about to write, iclass 12, count 2 2006.285.06:55:03.45#ibcon#wrote, iclass 12, count 2 2006.285.06:55:03.45#ibcon#about to read 3, iclass 12, count 2 2006.285.06:55:03.47#ibcon#read 3, iclass 12, count 2 2006.285.06:55:03.47#ibcon#about to read 4, iclass 12, count 2 2006.285.06:55:03.47#ibcon#read 4, iclass 12, count 2 2006.285.06:55:03.47#ibcon#about to read 5, iclass 12, count 2 2006.285.06:55:03.47#ibcon#read 5, iclass 12, count 2 2006.285.06:55:03.47#ibcon#about to read 6, iclass 12, count 2 2006.285.06:55:03.47#ibcon#read 6, iclass 12, count 2 2006.285.06:55:03.47#ibcon#end of sib2, iclass 12, count 2 2006.285.06:55:03.47#ibcon#*mode == 0, iclass 12, count 2 2006.285.06:55:03.47#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.06:55:03.47#ibcon#[25=AT04-06\r\n] 2006.285.06:55:03.47#ibcon#*before write, iclass 12, count 2 2006.285.06:55:03.47#ibcon#enter sib2, iclass 12, count 2 2006.285.06:55:03.47#ibcon#flushed, iclass 12, count 2 2006.285.06:55:03.47#ibcon#about to write, iclass 12, count 2 2006.285.06:55:03.47#ibcon#wrote, iclass 12, count 2 2006.285.06:55:03.47#ibcon#about to read 3, iclass 12, count 2 2006.285.06:55:03.50#ibcon#read 3, iclass 12, count 2 2006.285.06:55:03.50#ibcon#about to read 4, iclass 12, count 2 2006.285.06:55:03.50#ibcon#read 4, iclass 12, count 2 2006.285.06:55:03.50#ibcon#about to read 5, iclass 12, count 2 2006.285.06:55:03.50#ibcon#read 5, iclass 12, count 2 2006.285.06:55:03.50#ibcon#about to read 6, iclass 12, count 2 2006.285.06:55:03.50#ibcon#read 6, iclass 12, count 2 2006.285.06:55:03.50#ibcon#end of sib2, iclass 12, count 2 2006.285.06:55:03.50#ibcon#*after write, iclass 12, count 2 2006.285.06:55:03.50#ibcon#*before return 0, iclass 12, count 2 2006.285.06:55:03.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:55:03.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:55:03.50#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.06:55:03.50#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:03.50#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:55:03.62#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:55:03.62#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:55:03.62#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:55:03.62#ibcon#first serial, iclass 12, count 0 2006.285.06:55:03.62#ibcon#enter sib2, iclass 12, count 0 2006.285.06:55:03.62#ibcon#flushed, iclass 12, count 0 2006.285.06:55:03.62#ibcon#about to write, iclass 12, count 0 2006.285.06:55:03.62#ibcon#wrote, iclass 12, count 0 2006.285.06:55:03.62#ibcon#about to read 3, iclass 12, count 0 2006.285.06:55:03.64#ibcon#read 3, iclass 12, count 0 2006.285.06:55:03.64#ibcon#about to read 4, iclass 12, count 0 2006.285.06:55:03.64#ibcon#read 4, iclass 12, count 0 2006.285.06:55:03.64#ibcon#about to read 5, iclass 12, count 0 2006.285.06:55:03.64#ibcon#read 5, iclass 12, count 0 2006.285.06:55:03.64#ibcon#about to read 6, iclass 12, count 0 2006.285.06:55:03.64#ibcon#read 6, iclass 12, count 0 2006.285.06:55:03.64#ibcon#end of sib2, iclass 12, count 0 2006.285.06:55:03.64#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:55:03.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:55:03.64#ibcon#[25=USB\r\n] 2006.285.06:55:03.64#ibcon#*before write, iclass 12, count 0 2006.285.06:55:03.64#ibcon#enter sib2, iclass 12, count 0 2006.285.06:55:03.64#ibcon#flushed, iclass 12, count 0 2006.285.06:55:03.64#ibcon#about to write, iclass 12, count 0 2006.285.06:55:03.64#ibcon#wrote, iclass 12, count 0 2006.285.06:55:03.64#ibcon#about to read 3, iclass 12, count 0 2006.285.06:55:03.67#ibcon#read 3, iclass 12, count 0 2006.285.06:55:03.67#ibcon#about to read 4, iclass 12, count 0 2006.285.06:55:03.67#ibcon#read 4, iclass 12, count 0 2006.285.06:55:03.67#ibcon#about to read 5, iclass 12, count 0 2006.285.06:55:03.67#ibcon#read 5, iclass 12, count 0 2006.285.06:55:03.67#ibcon#about to read 6, iclass 12, count 0 2006.285.06:55:03.67#ibcon#read 6, iclass 12, count 0 2006.285.06:55:03.67#ibcon#end of sib2, iclass 12, count 0 2006.285.06:55:03.67#ibcon#*after write, iclass 12, count 0 2006.285.06:55:03.67#ibcon#*before return 0, iclass 12, count 0 2006.285.06:55:03.67#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:55:03.67#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:55:03.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:55:03.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:55:03.67$vck44/valo=5,734.99 2006.285.06:55:03.67#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.06:55:03.67#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.06:55:03.67#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:03.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:55:03.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:55:03.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:55:03.67#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:55:03.67#ibcon#first serial, iclass 14, count 0 2006.285.06:55:03.67#ibcon#enter sib2, iclass 14, count 0 2006.285.06:55:03.67#ibcon#flushed, iclass 14, count 0 2006.285.06:55:03.67#ibcon#about to write, iclass 14, count 0 2006.285.06:55:03.67#ibcon#wrote, iclass 14, count 0 2006.285.06:55:03.67#ibcon#about to read 3, iclass 14, count 0 2006.285.06:55:03.69#ibcon#read 3, iclass 14, count 0 2006.285.06:55:03.69#ibcon#about to read 4, iclass 14, count 0 2006.285.06:55:03.69#ibcon#read 4, iclass 14, count 0 2006.285.06:55:03.69#ibcon#about to read 5, iclass 14, count 0 2006.285.06:55:03.69#ibcon#read 5, iclass 14, count 0 2006.285.06:55:03.69#ibcon#about to read 6, iclass 14, count 0 2006.285.06:55:03.69#ibcon#read 6, iclass 14, count 0 2006.285.06:55:03.69#ibcon#end of sib2, iclass 14, count 0 2006.285.06:55:03.69#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:55:03.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:55:03.69#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.06:55:03.69#ibcon#*before write, iclass 14, count 0 2006.285.06:55:03.69#ibcon#enter sib2, iclass 14, count 0 2006.285.06:55:03.69#ibcon#flushed, iclass 14, count 0 2006.285.06:55:03.69#ibcon#about to write, iclass 14, count 0 2006.285.06:55:03.69#ibcon#wrote, iclass 14, count 0 2006.285.06:55:03.69#ibcon#about to read 3, iclass 14, count 0 2006.285.06:55:03.73#ibcon#read 3, iclass 14, count 0 2006.285.06:55:03.73#ibcon#about to read 4, iclass 14, count 0 2006.285.06:55:03.73#ibcon#read 4, iclass 14, count 0 2006.285.06:55:03.73#ibcon#about to read 5, iclass 14, count 0 2006.285.06:55:03.73#ibcon#read 5, iclass 14, count 0 2006.285.06:55:03.73#ibcon#about to read 6, iclass 14, count 0 2006.285.06:55:03.73#ibcon#read 6, iclass 14, count 0 2006.285.06:55:03.73#ibcon#end of sib2, iclass 14, count 0 2006.285.06:55:03.73#ibcon#*after write, iclass 14, count 0 2006.285.06:55:03.73#ibcon#*before return 0, iclass 14, count 0 2006.285.06:55:03.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:55:03.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:55:03.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:55:03.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:55:03.73$vck44/va=5,3 2006.285.06:55:03.73#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.06:55:03.73#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.06:55:03.73#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:03.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:55:03.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:55:03.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:55:03.79#ibcon#enter wrdev, iclass 16, count 2 2006.285.06:55:03.79#ibcon#first serial, iclass 16, count 2 2006.285.06:55:03.79#ibcon#enter sib2, iclass 16, count 2 2006.285.06:55:03.79#ibcon#flushed, iclass 16, count 2 2006.285.06:55:03.79#ibcon#about to write, iclass 16, count 2 2006.285.06:55:03.79#ibcon#wrote, iclass 16, count 2 2006.285.06:55:03.79#ibcon#about to read 3, iclass 16, count 2 2006.285.06:55:03.81#ibcon#read 3, iclass 16, count 2 2006.285.06:55:03.81#ibcon#about to read 4, iclass 16, count 2 2006.285.06:55:03.81#ibcon#read 4, iclass 16, count 2 2006.285.06:55:03.81#ibcon#about to read 5, iclass 16, count 2 2006.285.06:55:03.81#ibcon#read 5, iclass 16, count 2 2006.285.06:55:03.81#ibcon#about to read 6, iclass 16, count 2 2006.285.06:55:03.81#ibcon#read 6, iclass 16, count 2 2006.285.06:55:03.81#ibcon#end of sib2, iclass 16, count 2 2006.285.06:55:03.81#ibcon#*mode == 0, iclass 16, count 2 2006.285.06:55:03.81#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.06:55:03.81#ibcon#[25=AT05-03\r\n] 2006.285.06:55:03.81#ibcon#*before write, iclass 16, count 2 2006.285.06:55:03.81#ibcon#enter sib2, iclass 16, count 2 2006.285.06:55:03.81#ibcon#flushed, iclass 16, count 2 2006.285.06:55:03.81#ibcon#about to write, iclass 16, count 2 2006.285.06:55:03.81#ibcon#wrote, iclass 16, count 2 2006.285.06:55:03.81#ibcon#about to read 3, iclass 16, count 2 2006.285.06:55:03.84#ibcon#read 3, iclass 16, count 2 2006.285.06:55:03.84#ibcon#about to read 4, iclass 16, count 2 2006.285.06:55:03.84#ibcon#read 4, iclass 16, count 2 2006.285.06:55:03.84#ibcon#about to read 5, iclass 16, count 2 2006.285.06:55:03.84#ibcon#read 5, iclass 16, count 2 2006.285.06:55:03.84#ibcon#about to read 6, iclass 16, count 2 2006.285.06:55:03.84#ibcon#read 6, iclass 16, count 2 2006.285.06:55:03.84#ibcon#end of sib2, iclass 16, count 2 2006.285.06:55:03.84#ibcon#*after write, iclass 16, count 2 2006.285.06:55:03.84#ibcon#*before return 0, iclass 16, count 2 2006.285.06:55:03.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:55:03.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:55:03.84#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.06:55:03.84#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:03.84#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:55:03.96#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:55:03.96#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:55:03.96#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:55:03.96#ibcon#first serial, iclass 16, count 0 2006.285.06:55:03.96#ibcon#enter sib2, iclass 16, count 0 2006.285.06:55:03.96#ibcon#flushed, iclass 16, count 0 2006.285.06:55:03.96#ibcon#about to write, iclass 16, count 0 2006.285.06:55:03.96#ibcon#wrote, iclass 16, count 0 2006.285.06:55:03.96#ibcon#about to read 3, iclass 16, count 0 2006.285.06:55:03.98#ibcon#read 3, iclass 16, count 0 2006.285.06:55:03.98#ibcon#about to read 4, iclass 16, count 0 2006.285.06:55:03.98#ibcon#read 4, iclass 16, count 0 2006.285.06:55:03.98#ibcon#about to read 5, iclass 16, count 0 2006.285.06:55:03.98#ibcon#read 5, iclass 16, count 0 2006.285.06:55:03.98#ibcon#about to read 6, iclass 16, count 0 2006.285.06:55:03.98#ibcon#read 6, iclass 16, count 0 2006.285.06:55:03.98#ibcon#end of sib2, iclass 16, count 0 2006.285.06:55:03.98#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:55:03.98#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:55:03.98#ibcon#[25=USB\r\n] 2006.285.06:55:03.98#ibcon#*before write, iclass 16, count 0 2006.285.06:55:03.98#ibcon#enter sib2, iclass 16, count 0 2006.285.06:55:03.98#ibcon#flushed, iclass 16, count 0 2006.285.06:55:03.98#ibcon#about to write, iclass 16, count 0 2006.285.06:55:03.98#ibcon#wrote, iclass 16, count 0 2006.285.06:55:03.98#ibcon#about to read 3, iclass 16, count 0 2006.285.06:55:04.01#ibcon#read 3, iclass 16, count 0 2006.285.06:55:04.01#ibcon#about to read 4, iclass 16, count 0 2006.285.06:55:04.01#ibcon#read 4, iclass 16, count 0 2006.285.06:55:04.01#ibcon#about to read 5, iclass 16, count 0 2006.285.06:55:04.01#ibcon#read 5, iclass 16, count 0 2006.285.06:55:04.01#ibcon#about to read 6, iclass 16, count 0 2006.285.06:55:04.01#ibcon#read 6, iclass 16, count 0 2006.285.06:55:04.01#ibcon#end of sib2, iclass 16, count 0 2006.285.06:55:04.01#ibcon#*after write, iclass 16, count 0 2006.285.06:55:04.01#ibcon#*before return 0, iclass 16, count 0 2006.285.06:55:04.01#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:55:04.01#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:55:04.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:55:04.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:55:04.01$vck44/valo=6,814.99 2006.285.06:55:04.01#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.06:55:04.01#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.06:55:04.01#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:04.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:55:04.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:55:04.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:55:04.01#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:55:04.01#ibcon#first serial, iclass 18, count 0 2006.285.06:55:04.01#ibcon#enter sib2, iclass 18, count 0 2006.285.06:55:04.01#ibcon#flushed, iclass 18, count 0 2006.285.06:55:04.01#ibcon#about to write, iclass 18, count 0 2006.285.06:55:04.01#ibcon#wrote, iclass 18, count 0 2006.285.06:55:04.01#ibcon#about to read 3, iclass 18, count 0 2006.285.06:55:04.03#ibcon#read 3, iclass 18, count 0 2006.285.06:55:04.03#ibcon#about to read 4, iclass 18, count 0 2006.285.06:55:04.03#ibcon#read 4, iclass 18, count 0 2006.285.06:55:04.03#ibcon#about to read 5, iclass 18, count 0 2006.285.06:55:04.03#ibcon#read 5, iclass 18, count 0 2006.285.06:55:04.03#ibcon#about to read 6, iclass 18, count 0 2006.285.06:55:04.03#ibcon#read 6, iclass 18, count 0 2006.285.06:55:04.03#ibcon#end of sib2, iclass 18, count 0 2006.285.06:55:04.03#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:55:04.03#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:55:04.03#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.06:55:04.03#ibcon#*before write, iclass 18, count 0 2006.285.06:55:04.03#ibcon#enter sib2, iclass 18, count 0 2006.285.06:55:04.03#ibcon#flushed, iclass 18, count 0 2006.285.06:55:04.03#ibcon#about to write, iclass 18, count 0 2006.285.06:55:04.03#ibcon#wrote, iclass 18, count 0 2006.285.06:55:04.03#ibcon#about to read 3, iclass 18, count 0 2006.285.06:55:04.07#ibcon#read 3, iclass 18, count 0 2006.285.06:55:04.07#ibcon#about to read 4, iclass 18, count 0 2006.285.06:55:04.07#ibcon#read 4, iclass 18, count 0 2006.285.06:55:04.07#ibcon#about to read 5, iclass 18, count 0 2006.285.06:55:04.07#ibcon#read 5, iclass 18, count 0 2006.285.06:55:04.07#ibcon#about to read 6, iclass 18, count 0 2006.285.06:55:04.07#ibcon#read 6, iclass 18, count 0 2006.285.06:55:04.07#ibcon#end of sib2, iclass 18, count 0 2006.285.06:55:04.07#ibcon#*after write, iclass 18, count 0 2006.285.06:55:04.07#ibcon#*before return 0, iclass 18, count 0 2006.285.06:55:04.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:55:04.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:55:04.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:55:04.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:55:04.07$vck44/va=6,4 2006.285.06:55:04.07#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.06:55:04.07#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.06:55:04.07#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:04.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:55:04.12#abcon#<5=/05 4.2 7.4 24.43 721014.2\r\n> 2006.285.06:55:04.13#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:55:04.13#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:55:04.13#ibcon#enter wrdev, iclass 21, count 2 2006.285.06:55:04.13#ibcon#first serial, iclass 21, count 2 2006.285.06:55:04.13#ibcon#enter sib2, iclass 21, count 2 2006.285.06:55:04.13#ibcon#flushed, iclass 21, count 2 2006.285.06:55:04.13#ibcon#about to write, iclass 21, count 2 2006.285.06:55:04.13#ibcon#wrote, iclass 21, count 2 2006.285.06:55:04.13#ibcon#about to read 3, iclass 21, count 2 2006.285.06:55:04.14#abcon#{5=INTERFACE CLEAR} 2006.285.06:55:04.15#ibcon#read 3, iclass 21, count 2 2006.285.06:55:04.15#ibcon#about to read 4, iclass 21, count 2 2006.285.06:55:04.15#ibcon#read 4, iclass 21, count 2 2006.285.06:55:04.15#ibcon#about to read 5, iclass 21, count 2 2006.285.06:55:04.15#ibcon#read 5, iclass 21, count 2 2006.285.06:55:04.15#ibcon#about to read 6, iclass 21, count 2 2006.285.06:55:04.15#ibcon#read 6, iclass 21, count 2 2006.285.06:55:04.15#ibcon#end of sib2, iclass 21, count 2 2006.285.06:55:04.15#ibcon#*mode == 0, iclass 21, count 2 2006.285.06:55:04.15#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.06:55:04.15#ibcon#[25=AT06-04\r\n] 2006.285.06:55:04.15#ibcon#*before write, iclass 21, count 2 2006.285.06:55:04.15#ibcon#enter sib2, iclass 21, count 2 2006.285.06:55:04.15#ibcon#flushed, iclass 21, count 2 2006.285.06:55:04.15#ibcon#about to write, iclass 21, count 2 2006.285.06:55:04.15#ibcon#wrote, iclass 21, count 2 2006.285.06:55:04.15#ibcon#about to read 3, iclass 21, count 2 2006.285.06:55:04.18#ibcon#read 3, iclass 21, count 2 2006.285.06:55:04.18#ibcon#about to read 4, iclass 21, count 2 2006.285.06:55:04.18#ibcon#read 4, iclass 21, count 2 2006.285.06:55:04.18#ibcon#about to read 5, iclass 21, count 2 2006.285.06:55:04.18#ibcon#read 5, iclass 21, count 2 2006.285.06:55:04.18#ibcon#about to read 6, iclass 21, count 2 2006.285.06:55:04.18#ibcon#read 6, iclass 21, count 2 2006.285.06:55:04.18#ibcon#end of sib2, iclass 21, count 2 2006.285.06:55:04.18#ibcon#*after write, iclass 21, count 2 2006.285.06:55:04.18#ibcon#*before return 0, iclass 21, count 2 2006.285.06:55:04.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:55:04.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.06:55:04.18#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.06:55:04.18#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:04.18#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:55:04.20#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:55:04.30#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:55:04.30#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:55:04.30#ibcon#enter wrdev, iclass 21, count 0 2006.285.06:55:04.30#ibcon#first serial, iclass 21, count 0 2006.285.06:55:04.30#ibcon#enter sib2, iclass 21, count 0 2006.285.06:55:04.30#ibcon#flushed, iclass 21, count 0 2006.285.06:55:04.30#ibcon#about to write, iclass 21, count 0 2006.285.06:55:04.30#ibcon#wrote, iclass 21, count 0 2006.285.06:55:04.30#ibcon#about to read 3, iclass 21, count 0 2006.285.06:55:04.32#ibcon#read 3, iclass 21, count 0 2006.285.06:55:04.32#ibcon#about to read 4, iclass 21, count 0 2006.285.06:55:04.32#ibcon#read 4, iclass 21, count 0 2006.285.06:55:04.32#ibcon#about to read 5, iclass 21, count 0 2006.285.06:55:04.32#ibcon#read 5, iclass 21, count 0 2006.285.06:55:04.32#ibcon#about to read 6, iclass 21, count 0 2006.285.06:55:04.32#ibcon#read 6, iclass 21, count 0 2006.285.06:55:04.32#ibcon#end of sib2, iclass 21, count 0 2006.285.06:55:04.32#ibcon#*mode == 0, iclass 21, count 0 2006.285.06:55:04.32#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.06:55:04.32#ibcon#[25=USB\r\n] 2006.285.06:55:04.32#ibcon#*before write, iclass 21, count 0 2006.285.06:55:04.32#ibcon#enter sib2, iclass 21, count 0 2006.285.06:55:04.32#ibcon#flushed, iclass 21, count 0 2006.285.06:55:04.32#ibcon#about to write, iclass 21, count 0 2006.285.06:55:04.32#ibcon#wrote, iclass 21, count 0 2006.285.06:55:04.32#ibcon#about to read 3, iclass 21, count 0 2006.285.06:55:04.35#ibcon#read 3, iclass 21, count 0 2006.285.06:55:04.35#ibcon#about to read 4, iclass 21, count 0 2006.285.06:55:04.35#ibcon#read 4, iclass 21, count 0 2006.285.06:55:04.35#ibcon#about to read 5, iclass 21, count 0 2006.285.06:55:04.35#ibcon#read 5, iclass 21, count 0 2006.285.06:55:04.35#ibcon#about to read 6, iclass 21, count 0 2006.285.06:55:04.35#ibcon#read 6, iclass 21, count 0 2006.285.06:55:04.35#ibcon#end of sib2, iclass 21, count 0 2006.285.06:55:04.35#ibcon#*after write, iclass 21, count 0 2006.285.06:55:04.35#ibcon#*before return 0, iclass 21, count 0 2006.285.06:55:04.35#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:55:04.35#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.06:55:04.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.06:55:04.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.06:55:04.35$vck44/valo=7,864.99 2006.285.06:55:04.35#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.06:55:04.35#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.06:55:04.35#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:04.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:55:04.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:55:04.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:55:04.35#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:55:04.35#ibcon#first serial, iclass 26, count 0 2006.285.06:55:04.35#ibcon#enter sib2, iclass 26, count 0 2006.285.06:55:04.35#ibcon#flushed, iclass 26, count 0 2006.285.06:55:04.35#ibcon#about to write, iclass 26, count 0 2006.285.06:55:04.35#ibcon#wrote, iclass 26, count 0 2006.285.06:55:04.35#ibcon#about to read 3, iclass 26, count 0 2006.285.06:55:04.37#ibcon#read 3, iclass 26, count 0 2006.285.06:55:04.37#ibcon#about to read 4, iclass 26, count 0 2006.285.06:55:04.37#ibcon#read 4, iclass 26, count 0 2006.285.06:55:04.37#ibcon#about to read 5, iclass 26, count 0 2006.285.06:55:04.37#ibcon#read 5, iclass 26, count 0 2006.285.06:55:04.37#ibcon#about to read 6, iclass 26, count 0 2006.285.06:55:04.37#ibcon#read 6, iclass 26, count 0 2006.285.06:55:04.37#ibcon#end of sib2, iclass 26, count 0 2006.285.06:55:04.37#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:55:04.37#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:55:04.37#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.06:55:04.37#ibcon#*before write, iclass 26, count 0 2006.285.06:55:04.37#ibcon#enter sib2, iclass 26, count 0 2006.285.06:55:04.37#ibcon#flushed, iclass 26, count 0 2006.285.06:55:04.37#ibcon#about to write, iclass 26, count 0 2006.285.06:55:04.37#ibcon#wrote, iclass 26, count 0 2006.285.06:55:04.37#ibcon#about to read 3, iclass 26, count 0 2006.285.06:55:04.41#ibcon#read 3, iclass 26, count 0 2006.285.06:55:04.41#ibcon#about to read 4, iclass 26, count 0 2006.285.06:55:04.41#ibcon#read 4, iclass 26, count 0 2006.285.06:55:04.41#ibcon#about to read 5, iclass 26, count 0 2006.285.06:55:04.41#ibcon#read 5, iclass 26, count 0 2006.285.06:55:04.41#ibcon#about to read 6, iclass 26, count 0 2006.285.06:55:04.41#ibcon#read 6, iclass 26, count 0 2006.285.06:55:04.41#ibcon#end of sib2, iclass 26, count 0 2006.285.06:55:04.41#ibcon#*after write, iclass 26, count 0 2006.285.06:55:04.41#ibcon#*before return 0, iclass 26, count 0 2006.285.06:55:04.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:55:04.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:55:04.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:55:04.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:55:04.41$vck44/va=7,4 2006.285.06:55:04.41#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.06:55:04.41#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.06:55:04.41#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:04.41#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:55:04.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:55:04.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:55:04.47#ibcon#enter wrdev, iclass 28, count 2 2006.285.06:55:04.47#ibcon#first serial, iclass 28, count 2 2006.285.06:55:04.47#ibcon#enter sib2, iclass 28, count 2 2006.285.06:55:04.47#ibcon#flushed, iclass 28, count 2 2006.285.06:55:04.47#ibcon#about to write, iclass 28, count 2 2006.285.06:55:04.47#ibcon#wrote, iclass 28, count 2 2006.285.06:55:04.47#ibcon#about to read 3, iclass 28, count 2 2006.285.06:55:04.49#ibcon#read 3, iclass 28, count 2 2006.285.06:55:04.49#ibcon#about to read 4, iclass 28, count 2 2006.285.06:55:04.49#ibcon#read 4, iclass 28, count 2 2006.285.06:55:04.49#ibcon#about to read 5, iclass 28, count 2 2006.285.06:55:04.49#ibcon#read 5, iclass 28, count 2 2006.285.06:55:04.49#ibcon#about to read 6, iclass 28, count 2 2006.285.06:55:04.49#ibcon#read 6, iclass 28, count 2 2006.285.06:55:04.49#ibcon#end of sib2, iclass 28, count 2 2006.285.06:55:04.49#ibcon#*mode == 0, iclass 28, count 2 2006.285.06:55:04.49#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.06:55:04.49#ibcon#[25=AT07-04\r\n] 2006.285.06:55:04.49#ibcon#*before write, iclass 28, count 2 2006.285.06:55:04.49#ibcon#enter sib2, iclass 28, count 2 2006.285.06:55:04.49#ibcon#flushed, iclass 28, count 2 2006.285.06:55:04.49#ibcon#about to write, iclass 28, count 2 2006.285.06:55:04.49#ibcon#wrote, iclass 28, count 2 2006.285.06:55:04.49#ibcon#about to read 3, iclass 28, count 2 2006.285.06:55:04.52#ibcon#read 3, iclass 28, count 2 2006.285.06:55:04.52#ibcon#about to read 4, iclass 28, count 2 2006.285.06:55:04.52#ibcon#read 4, iclass 28, count 2 2006.285.06:55:04.52#ibcon#about to read 5, iclass 28, count 2 2006.285.06:55:04.52#ibcon#read 5, iclass 28, count 2 2006.285.06:55:04.52#ibcon#about to read 6, iclass 28, count 2 2006.285.06:55:04.52#ibcon#read 6, iclass 28, count 2 2006.285.06:55:04.52#ibcon#end of sib2, iclass 28, count 2 2006.285.06:55:04.52#ibcon#*after write, iclass 28, count 2 2006.285.06:55:04.52#ibcon#*before return 0, iclass 28, count 2 2006.285.06:55:04.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:55:04.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:55:04.52#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.06:55:04.52#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:04.52#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:55:04.64#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:55:04.64#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:55:04.64#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:55:04.64#ibcon#first serial, iclass 28, count 0 2006.285.06:55:04.64#ibcon#enter sib2, iclass 28, count 0 2006.285.06:55:04.64#ibcon#flushed, iclass 28, count 0 2006.285.06:55:04.64#ibcon#about to write, iclass 28, count 0 2006.285.06:55:04.64#ibcon#wrote, iclass 28, count 0 2006.285.06:55:04.64#ibcon#about to read 3, iclass 28, count 0 2006.285.06:55:04.66#ibcon#read 3, iclass 28, count 0 2006.285.06:55:04.66#ibcon#about to read 4, iclass 28, count 0 2006.285.06:55:04.66#ibcon#read 4, iclass 28, count 0 2006.285.06:55:04.66#ibcon#about to read 5, iclass 28, count 0 2006.285.06:55:04.66#ibcon#read 5, iclass 28, count 0 2006.285.06:55:04.66#ibcon#about to read 6, iclass 28, count 0 2006.285.06:55:04.66#ibcon#read 6, iclass 28, count 0 2006.285.06:55:04.66#ibcon#end of sib2, iclass 28, count 0 2006.285.06:55:04.66#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:55:04.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:55:04.66#ibcon#[25=USB\r\n] 2006.285.06:55:04.66#ibcon#*before write, iclass 28, count 0 2006.285.06:55:04.66#ibcon#enter sib2, iclass 28, count 0 2006.285.06:55:04.66#ibcon#flushed, iclass 28, count 0 2006.285.06:55:04.66#ibcon#about to write, iclass 28, count 0 2006.285.06:55:04.66#ibcon#wrote, iclass 28, count 0 2006.285.06:55:04.66#ibcon#about to read 3, iclass 28, count 0 2006.285.06:55:04.69#ibcon#read 3, iclass 28, count 0 2006.285.06:55:04.69#ibcon#about to read 4, iclass 28, count 0 2006.285.06:55:04.69#ibcon#read 4, iclass 28, count 0 2006.285.06:55:04.69#ibcon#about to read 5, iclass 28, count 0 2006.285.06:55:04.69#ibcon#read 5, iclass 28, count 0 2006.285.06:55:04.69#ibcon#about to read 6, iclass 28, count 0 2006.285.06:55:04.69#ibcon#read 6, iclass 28, count 0 2006.285.06:55:04.69#ibcon#end of sib2, iclass 28, count 0 2006.285.06:55:04.69#ibcon#*after write, iclass 28, count 0 2006.285.06:55:04.69#ibcon#*before return 0, iclass 28, count 0 2006.285.06:55:04.69#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:55:04.69#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:55:04.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:55:04.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:55:04.69$vck44/valo=8,884.99 2006.285.06:55:04.69#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.06:55:04.69#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.06:55:04.69#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:04.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:55:04.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:55:04.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:55:04.69#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:55:04.69#ibcon#first serial, iclass 30, count 0 2006.285.06:55:04.69#ibcon#enter sib2, iclass 30, count 0 2006.285.06:55:04.69#ibcon#flushed, iclass 30, count 0 2006.285.06:55:04.69#ibcon#about to write, iclass 30, count 0 2006.285.06:55:04.69#ibcon#wrote, iclass 30, count 0 2006.285.06:55:04.69#ibcon#about to read 3, iclass 30, count 0 2006.285.06:55:04.71#ibcon#read 3, iclass 30, count 0 2006.285.06:55:04.71#ibcon#about to read 4, iclass 30, count 0 2006.285.06:55:04.71#ibcon#read 4, iclass 30, count 0 2006.285.06:55:04.71#ibcon#about to read 5, iclass 30, count 0 2006.285.06:55:04.71#ibcon#read 5, iclass 30, count 0 2006.285.06:55:04.71#ibcon#about to read 6, iclass 30, count 0 2006.285.06:55:04.71#ibcon#read 6, iclass 30, count 0 2006.285.06:55:04.71#ibcon#end of sib2, iclass 30, count 0 2006.285.06:55:04.71#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:55:04.71#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:55:04.71#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.06:55:04.71#ibcon#*before write, iclass 30, count 0 2006.285.06:55:04.71#ibcon#enter sib2, iclass 30, count 0 2006.285.06:55:04.71#ibcon#flushed, iclass 30, count 0 2006.285.06:55:04.71#ibcon#about to write, iclass 30, count 0 2006.285.06:55:04.71#ibcon#wrote, iclass 30, count 0 2006.285.06:55:04.71#ibcon#about to read 3, iclass 30, count 0 2006.285.06:55:04.75#ibcon#read 3, iclass 30, count 0 2006.285.06:55:04.75#ibcon#about to read 4, iclass 30, count 0 2006.285.06:55:04.75#ibcon#read 4, iclass 30, count 0 2006.285.06:55:04.75#ibcon#about to read 5, iclass 30, count 0 2006.285.06:55:04.75#ibcon#read 5, iclass 30, count 0 2006.285.06:55:04.75#ibcon#about to read 6, iclass 30, count 0 2006.285.06:55:04.75#ibcon#read 6, iclass 30, count 0 2006.285.06:55:04.75#ibcon#end of sib2, iclass 30, count 0 2006.285.06:55:04.75#ibcon#*after write, iclass 30, count 0 2006.285.06:55:04.75#ibcon#*before return 0, iclass 30, count 0 2006.285.06:55:04.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:55:04.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:55:04.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:55:04.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:55:04.75$vck44/va=8,3 2006.285.06:55:04.75#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.06:55:04.75#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.06:55:04.75#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:04.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:55:04.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:55:04.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:55:04.81#ibcon#enter wrdev, iclass 32, count 2 2006.285.06:55:04.81#ibcon#first serial, iclass 32, count 2 2006.285.06:55:04.81#ibcon#enter sib2, iclass 32, count 2 2006.285.06:55:04.81#ibcon#flushed, iclass 32, count 2 2006.285.06:55:04.81#ibcon#about to write, iclass 32, count 2 2006.285.06:55:04.81#ibcon#wrote, iclass 32, count 2 2006.285.06:55:04.81#ibcon#about to read 3, iclass 32, count 2 2006.285.06:55:04.83#ibcon#read 3, iclass 32, count 2 2006.285.06:55:04.83#ibcon#about to read 4, iclass 32, count 2 2006.285.06:55:04.83#ibcon#read 4, iclass 32, count 2 2006.285.06:55:04.83#ibcon#about to read 5, iclass 32, count 2 2006.285.06:55:04.83#ibcon#read 5, iclass 32, count 2 2006.285.06:55:04.83#ibcon#about to read 6, iclass 32, count 2 2006.285.06:55:04.83#ibcon#read 6, iclass 32, count 2 2006.285.06:55:04.83#ibcon#end of sib2, iclass 32, count 2 2006.285.06:55:04.83#ibcon#*mode == 0, iclass 32, count 2 2006.285.06:55:04.83#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.06:55:04.83#ibcon#[25=AT08-03\r\n] 2006.285.06:55:04.83#ibcon#*before write, iclass 32, count 2 2006.285.06:55:04.83#ibcon#enter sib2, iclass 32, count 2 2006.285.06:55:04.83#ibcon#flushed, iclass 32, count 2 2006.285.06:55:04.83#ibcon#about to write, iclass 32, count 2 2006.285.06:55:04.83#ibcon#wrote, iclass 32, count 2 2006.285.06:55:04.83#ibcon#about to read 3, iclass 32, count 2 2006.285.06:55:04.86#ibcon#read 3, iclass 32, count 2 2006.285.06:55:04.86#ibcon#about to read 4, iclass 32, count 2 2006.285.06:55:04.86#ibcon#read 4, iclass 32, count 2 2006.285.06:55:04.86#ibcon#about to read 5, iclass 32, count 2 2006.285.06:55:04.86#ibcon#read 5, iclass 32, count 2 2006.285.06:55:04.86#ibcon#about to read 6, iclass 32, count 2 2006.285.06:55:04.86#ibcon#read 6, iclass 32, count 2 2006.285.06:55:04.86#ibcon#end of sib2, iclass 32, count 2 2006.285.06:55:04.86#ibcon#*after write, iclass 32, count 2 2006.285.06:55:04.86#ibcon#*before return 0, iclass 32, count 2 2006.285.06:55:04.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:55:04.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.06:55:04.86#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.06:55:04.86#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:04.86#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:55:04.98#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:55:04.98#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:55:04.98#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:55:04.98#ibcon#first serial, iclass 32, count 0 2006.285.06:55:04.98#ibcon#enter sib2, iclass 32, count 0 2006.285.06:55:04.98#ibcon#flushed, iclass 32, count 0 2006.285.06:55:04.98#ibcon#about to write, iclass 32, count 0 2006.285.06:55:04.98#ibcon#wrote, iclass 32, count 0 2006.285.06:55:04.98#ibcon#about to read 3, iclass 32, count 0 2006.285.06:55:05.00#ibcon#read 3, iclass 32, count 0 2006.285.06:55:05.00#ibcon#about to read 4, iclass 32, count 0 2006.285.06:55:05.00#ibcon#read 4, iclass 32, count 0 2006.285.06:55:05.00#ibcon#about to read 5, iclass 32, count 0 2006.285.06:55:05.00#ibcon#read 5, iclass 32, count 0 2006.285.06:55:05.00#ibcon#about to read 6, iclass 32, count 0 2006.285.06:55:05.00#ibcon#read 6, iclass 32, count 0 2006.285.06:55:05.00#ibcon#end of sib2, iclass 32, count 0 2006.285.06:55:05.00#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:55:05.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:55:05.00#ibcon#[25=USB\r\n] 2006.285.06:55:05.00#ibcon#*before write, iclass 32, count 0 2006.285.06:55:05.00#ibcon#enter sib2, iclass 32, count 0 2006.285.06:55:05.00#ibcon#flushed, iclass 32, count 0 2006.285.06:55:05.00#ibcon#about to write, iclass 32, count 0 2006.285.06:55:05.00#ibcon#wrote, iclass 32, count 0 2006.285.06:55:05.00#ibcon#about to read 3, iclass 32, count 0 2006.285.06:55:05.03#ibcon#read 3, iclass 32, count 0 2006.285.06:55:05.03#ibcon#about to read 4, iclass 32, count 0 2006.285.06:55:05.03#ibcon#read 4, iclass 32, count 0 2006.285.06:55:05.03#ibcon#about to read 5, iclass 32, count 0 2006.285.06:55:05.03#ibcon#read 5, iclass 32, count 0 2006.285.06:55:05.03#ibcon#about to read 6, iclass 32, count 0 2006.285.06:55:05.03#ibcon#read 6, iclass 32, count 0 2006.285.06:55:05.03#ibcon#end of sib2, iclass 32, count 0 2006.285.06:55:05.03#ibcon#*after write, iclass 32, count 0 2006.285.06:55:05.03#ibcon#*before return 0, iclass 32, count 0 2006.285.06:55:05.03#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:55:05.03#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.06:55:05.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:55:05.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:55:05.03$vck44/vblo=1,629.99 2006.285.06:55:05.03#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.06:55:05.03#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.06:55:05.03#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:05.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:55:05.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:55:05.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:55:05.03#ibcon#enter wrdev, iclass 34, count 0 2006.285.06:55:05.03#ibcon#first serial, iclass 34, count 0 2006.285.06:55:05.03#ibcon#enter sib2, iclass 34, count 0 2006.285.06:55:05.03#ibcon#flushed, iclass 34, count 0 2006.285.06:55:05.03#ibcon#about to write, iclass 34, count 0 2006.285.06:55:05.03#ibcon#wrote, iclass 34, count 0 2006.285.06:55:05.03#ibcon#about to read 3, iclass 34, count 0 2006.285.06:55:05.05#ibcon#read 3, iclass 34, count 0 2006.285.06:55:05.05#ibcon#about to read 4, iclass 34, count 0 2006.285.06:55:05.05#ibcon#read 4, iclass 34, count 0 2006.285.06:55:05.05#ibcon#about to read 5, iclass 34, count 0 2006.285.06:55:05.05#ibcon#read 5, iclass 34, count 0 2006.285.06:55:05.05#ibcon#about to read 6, iclass 34, count 0 2006.285.06:55:05.05#ibcon#read 6, iclass 34, count 0 2006.285.06:55:05.05#ibcon#end of sib2, iclass 34, count 0 2006.285.06:55:05.05#ibcon#*mode == 0, iclass 34, count 0 2006.285.06:55:05.05#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.06:55:05.05#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.06:55:05.05#ibcon#*before write, iclass 34, count 0 2006.285.06:55:05.05#ibcon#enter sib2, iclass 34, count 0 2006.285.06:55:05.05#ibcon#flushed, iclass 34, count 0 2006.285.06:55:05.05#ibcon#about to write, iclass 34, count 0 2006.285.06:55:05.05#ibcon#wrote, iclass 34, count 0 2006.285.06:55:05.05#ibcon#about to read 3, iclass 34, count 0 2006.285.06:55:05.09#ibcon#read 3, iclass 34, count 0 2006.285.06:55:05.09#ibcon#about to read 4, iclass 34, count 0 2006.285.06:55:05.09#ibcon#read 4, iclass 34, count 0 2006.285.06:55:05.09#ibcon#about to read 5, iclass 34, count 0 2006.285.06:55:05.09#ibcon#read 5, iclass 34, count 0 2006.285.06:55:05.09#ibcon#about to read 6, iclass 34, count 0 2006.285.06:55:05.09#ibcon#read 6, iclass 34, count 0 2006.285.06:55:05.09#ibcon#end of sib2, iclass 34, count 0 2006.285.06:55:05.09#ibcon#*after write, iclass 34, count 0 2006.285.06:55:05.09#ibcon#*before return 0, iclass 34, count 0 2006.285.06:55:05.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:55:05.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.06:55:05.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.06:55:05.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.06:55:05.09$vck44/vb=1,4 2006.285.06:55:05.09#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.06:55:05.09#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.06:55:05.09#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:05.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:55:05.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:55:05.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:55:05.09#ibcon#enter wrdev, iclass 36, count 2 2006.285.06:55:05.09#ibcon#first serial, iclass 36, count 2 2006.285.06:55:05.09#ibcon#enter sib2, iclass 36, count 2 2006.285.06:55:05.09#ibcon#flushed, iclass 36, count 2 2006.285.06:55:05.09#ibcon#about to write, iclass 36, count 2 2006.285.06:55:05.09#ibcon#wrote, iclass 36, count 2 2006.285.06:55:05.09#ibcon#about to read 3, iclass 36, count 2 2006.285.06:55:05.11#ibcon#read 3, iclass 36, count 2 2006.285.06:55:05.11#ibcon#about to read 4, iclass 36, count 2 2006.285.06:55:05.11#ibcon#read 4, iclass 36, count 2 2006.285.06:55:05.11#ibcon#about to read 5, iclass 36, count 2 2006.285.06:55:05.11#ibcon#read 5, iclass 36, count 2 2006.285.06:55:05.11#ibcon#about to read 6, iclass 36, count 2 2006.285.06:55:05.11#ibcon#read 6, iclass 36, count 2 2006.285.06:55:05.11#ibcon#end of sib2, iclass 36, count 2 2006.285.06:55:05.11#ibcon#*mode == 0, iclass 36, count 2 2006.285.06:55:05.11#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.06:55:05.11#ibcon#[27=AT01-04\r\n] 2006.285.06:55:05.11#ibcon#*before write, iclass 36, count 2 2006.285.06:55:05.11#ibcon#enter sib2, iclass 36, count 2 2006.285.06:55:05.11#ibcon#flushed, iclass 36, count 2 2006.285.06:55:05.11#ibcon#about to write, iclass 36, count 2 2006.285.06:55:05.11#ibcon#wrote, iclass 36, count 2 2006.285.06:55:05.11#ibcon#about to read 3, iclass 36, count 2 2006.285.06:55:05.14#ibcon#read 3, iclass 36, count 2 2006.285.06:55:05.14#ibcon#about to read 4, iclass 36, count 2 2006.285.06:55:05.14#ibcon#read 4, iclass 36, count 2 2006.285.06:55:05.14#ibcon#about to read 5, iclass 36, count 2 2006.285.06:55:05.14#ibcon#read 5, iclass 36, count 2 2006.285.06:55:05.14#ibcon#about to read 6, iclass 36, count 2 2006.285.06:55:05.14#ibcon#read 6, iclass 36, count 2 2006.285.06:55:05.14#ibcon#end of sib2, iclass 36, count 2 2006.285.06:55:05.14#ibcon#*after write, iclass 36, count 2 2006.285.06:55:05.14#ibcon#*before return 0, iclass 36, count 2 2006.285.06:55:05.14#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:55:05.14#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.06:55:05.14#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.06:55:05.14#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:05.14#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:55:05.26#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:55:05.26#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:55:05.26#ibcon#enter wrdev, iclass 36, count 0 2006.285.06:55:05.26#ibcon#first serial, iclass 36, count 0 2006.285.06:55:05.26#ibcon#enter sib2, iclass 36, count 0 2006.285.06:55:05.26#ibcon#flushed, iclass 36, count 0 2006.285.06:55:05.26#ibcon#about to write, iclass 36, count 0 2006.285.06:55:05.26#ibcon#wrote, iclass 36, count 0 2006.285.06:55:05.26#ibcon#about to read 3, iclass 36, count 0 2006.285.06:55:05.28#ibcon#read 3, iclass 36, count 0 2006.285.06:55:05.28#ibcon#about to read 4, iclass 36, count 0 2006.285.06:55:05.28#ibcon#read 4, iclass 36, count 0 2006.285.06:55:05.28#ibcon#about to read 5, iclass 36, count 0 2006.285.06:55:05.28#ibcon#read 5, iclass 36, count 0 2006.285.06:55:05.28#ibcon#about to read 6, iclass 36, count 0 2006.285.06:55:05.28#ibcon#read 6, iclass 36, count 0 2006.285.06:55:05.28#ibcon#end of sib2, iclass 36, count 0 2006.285.06:55:05.28#ibcon#*mode == 0, iclass 36, count 0 2006.285.06:55:05.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.06:55:05.28#ibcon#[27=USB\r\n] 2006.285.06:55:05.28#ibcon#*before write, iclass 36, count 0 2006.285.06:55:05.28#ibcon#enter sib2, iclass 36, count 0 2006.285.06:55:05.28#ibcon#flushed, iclass 36, count 0 2006.285.06:55:05.28#ibcon#about to write, iclass 36, count 0 2006.285.06:55:05.28#ibcon#wrote, iclass 36, count 0 2006.285.06:55:05.28#ibcon#about to read 3, iclass 36, count 0 2006.285.06:55:05.31#ibcon#read 3, iclass 36, count 0 2006.285.06:55:05.31#ibcon#about to read 4, iclass 36, count 0 2006.285.06:55:05.31#ibcon#read 4, iclass 36, count 0 2006.285.06:55:05.31#ibcon#about to read 5, iclass 36, count 0 2006.285.06:55:05.31#ibcon#read 5, iclass 36, count 0 2006.285.06:55:05.31#ibcon#about to read 6, iclass 36, count 0 2006.285.06:55:05.31#ibcon#read 6, iclass 36, count 0 2006.285.06:55:05.31#ibcon#end of sib2, iclass 36, count 0 2006.285.06:55:05.31#ibcon#*after write, iclass 36, count 0 2006.285.06:55:05.31#ibcon#*before return 0, iclass 36, count 0 2006.285.06:55:05.31#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:55:05.31#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.06:55:05.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.06:55:05.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.06:55:05.31$vck44/vblo=2,634.99 2006.285.06:55:05.31#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.06:55:05.31#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.06:55:05.31#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:05.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:55:05.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:55:05.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:55:05.31#ibcon#enter wrdev, iclass 38, count 0 2006.285.06:55:05.31#ibcon#first serial, iclass 38, count 0 2006.285.06:55:05.31#ibcon#enter sib2, iclass 38, count 0 2006.285.06:55:05.31#ibcon#flushed, iclass 38, count 0 2006.285.06:55:05.31#ibcon#about to write, iclass 38, count 0 2006.285.06:55:05.31#ibcon#wrote, iclass 38, count 0 2006.285.06:55:05.31#ibcon#about to read 3, iclass 38, count 0 2006.285.06:55:05.33#ibcon#read 3, iclass 38, count 0 2006.285.06:55:05.33#ibcon#about to read 4, iclass 38, count 0 2006.285.06:55:05.33#ibcon#read 4, iclass 38, count 0 2006.285.06:55:05.33#ibcon#about to read 5, iclass 38, count 0 2006.285.06:55:05.33#ibcon#read 5, iclass 38, count 0 2006.285.06:55:05.33#ibcon#about to read 6, iclass 38, count 0 2006.285.06:55:05.33#ibcon#read 6, iclass 38, count 0 2006.285.06:55:05.33#ibcon#end of sib2, iclass 38, count 0 2006.285.06:55:05.33#ibcon#*mode == 0, iclass 38, count 0 2006.285.06:55:05.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.06:55:05.33#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.06:55:05.33#ibcon#*before write, iclass 38, count 0 2006.285.06:55:05.33#ibcon#enter sib2, iclass 38, count 0 2006.285.06:55:05.33#ibcon#flushed, iclass 38, count 0 2006.285.06:55:05.33#ibcon#about to write, iclass 38, count 0 2006.285.06:55:05.33#ibcon#wrote, iclass 38, count 0 2006.285.06:55:05.33#ibcon#about to read 3, iclass 38, count 0 2006.285.06:55:05.37#ibcon#read 3, iclass 38, count 0 2006.285.06:55:05.37#ibcon#about to read 4, iclass 38, count 0 2006.285.06:55:05.37#ibcon#read 4, iclass 38, count 0 2006.285.06:55:05.37#ibcon#about to read 5, iclass 38, count 0 2006.285.06:55:05.37#ibcon#read 5, iclass 38, count 0 2006.285.06:55:05.37#ibcon#about to read 6, iclass 38, count 0 2006.285.06:55:05.37#ibcon#read 6, iclass 38, count 0 2006.285.06:55:05.37#ibcon#end of sib2, iclass 38, count 0 2006.285.06:55:05.37#ibcon#*after write, iclass 38, count 0 2006.285.06:55:05.37#ibcon#*before return 0, iclass 38, count 0 2006.285.06:55:05.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:55:05.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.06:55:05.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.06:55:05.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.06:55:05.37$vck44/vb=2,5 2006.285.06:55:05.37#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.06:55:05.37#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.06:55:05.37#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:05.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:55:05.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:55:05.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:55:05.43#ibcon#enter wrdev, iclass 40, count 2 2006.285.06:55:05.43#ibcon#first serial, iclass 40, count 2 2006.285.06:55:05.43#ibcon#enter sib2, iclass 40, count 2 2006.285.06:55:05.43#ibcon#flushed, iclass 40, count 2 2006.285.06:55:05.43#ibcon#about to write, iclass 40, count 2 2006.285.06:55:05.43#ibcon#wrote, iclass 40, count 2 2006.285.06:55:05.43#ibcon#about to read 3, iclass 40, count 2 2006.285.06:55:05.45#ibcon#read 3, iclass 40, count 2 2006.285.06:55:05.45#ibcon#about to read 4, iclass 40, count 2 2006.285.06:55:05.45#ibcon#read 4, iclass 40, count 2 2006.285.06:55:05.45#ibcon#about to read 5, iclass 40, count 2 2006.285.06:55:05.45#ibcon#read 5, iclass 40, count 2 2006.285.06:55:05.45#ibcon#about to read 6, iclass 40, count 2 2006.285.06:55:05.45#ibcon#read 6, iclass 40, count 2 2006.285.06:55:05.45#ibcon#end of sib2, iclass 40, count 2 2006.285.06:55:05.45#ibcon#*mode == 0, iclass 40, count 2 2006.285.06:55:05.45#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.06:55:05.45#ibcon#[27=AT02-05\r\n] 2006.285.06:55:05.45#ibcon#*before write, iclass 40, count 2 2006.285.06:55:05.45#ibcon#enter sib2, iclass 40, count 2 2006.285.06:55:05.45#ibcon#flushed, iclass 40, count 2 2006.285.06:55:05.45#ibcon#about to write, iclass 40, count 2 2006.285.06:55:05.45#ibcon#wrote, iclass 40, count 2 2006.285.06:55:05.45#ibcon#about to read 3, iclass 40, count 2 2006.285.06:55:05.48#ibcon#read 3, iclass 40, count 2 2006.285.06:55:05.48#ibcon#about to read 4, iclass 40, count 2 2006.285.06:55:05.48#ibcon#read 4, iclass 40, count 2 2006.285.06:55:05.48#ibcon#about to read 5, iclass 40, count 2 2006.285.06:55:05.48#ibcon#read 5, iclass 40, count 2 2006.285.06:55:05.48#ibcon#about to read 6, iclass 40, count 2 2006.285.06:55:05.48#ibcon#read 6, iclass 40, count 2 2006.285.06:55:05.48#ibcon#end of sib2, iclass 40, count 2 2006.285.06:55:05.48#ibcon#*after write, iclass 40, count 2 2006.285.06:55:05.48#ibcon#*before return 0, iclass 40, count 2 2006.285.06:55:05.48#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:55:05.48#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.06:55:05.48#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.06:55:05.48#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:05.48#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:55:05.60#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:55:05.60#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:55:05.60#ibcon#enter wrdev, iclass 40, count 0 2006.285.06:55:05.60#ibcon#first serial, iclass 40, count 0 2006.285.06:55:05.60#ibcon#enter sib2, iclass 40, count 0 2006.285.06:55:05.60#ibcon#flushed, iclass 40, count 0 2006.285.06:55:05.60#ibcon#about to write, iclass 40, count 0 2006.285.06:55:05.60#ibcon#wrote, iclass 40, count 0 2006.285.06:55:05.60#ibcon#about to read 3, iclass 40, count 0 2006.285.06:55:05.62#ibcon#read 3, iclass 40, count 0 2006.285.06:55:05.62#ibcon#about to read 4, iclass 40, count 0 2006.285.06:55:05.62#ibcon#read 4, iclass 40, count 0 2006.285.06:55:05.62#ibcon#about to read 5, iclass 40, count 0 2006.285.06:55:05.62#ibcon#read 5, iclass 40, count 0 2006.285.06:55:05.62#ibcon#about to read 6, iclass 40, count 0 2006.285.06:55:05.62#ibcon#read 6, iclass 40, count 0 2006.285.06:55:05.62#ibcon#end of sib2, iclass 40, count 0 2006.285.06:55:05.62#ibcon#*mode == 0, iclass 40, count 0 2006.285.06:55:05.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.06:55:05.62#ibcon#[27=USB\r\n] 2006.285.06:55:05.62#ibcon#*before write, iclass 40, count 0 2006.285.06:55:05.62#ibcon#enter sib2, iclass 40, count 0 2006.285.06:55:05.62#ibcon#flushed, iclass 40, count 0 2006.285.06:55:05.62#ibcon#about to write, iclass 40, count 0 2006.285.06:55:05.62#ibcon#wrote, iclass 40, count 0 2006.285.06:55:05.62#ibcon#about to read 3, iclass 40, count 0 2006.285.06:55:05.65#ibcon#read 3, iclass 40, count 0 2006.285.06:55:05.65#ibcon#about to read 4, iclass 40, count 0 2006.285.06:55:05.65#ibcon#read 4, iclass 40, count 0 2006.285.06:55:05.65#ibcon#about to read 5, iclass 40, count 0 2006.285.06:55:05.65#ibcon#read 5, iclass 40, count 0 2006.285.06:55:05.65#ibcon#about to read 6, iclass 40, count 0 2006.285.06:55:05.65#ibcon#read 6, iclass 40, count 0 2006.285.06:55:05.65#ibcon#end of sib2, iclass 40, count 0 2006.285.06:55:05.65#ibcon#*after write, iclass 40, count 0 2006.285.06:55:05.65#ibcon#*before return 0, iclass 40, count 0 2006.285.06:55:05.65#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:55:05.65#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.06:55:05.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.06:55:05.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.06:55:05.65$vck44/vblo=3,649.99 2006.285.06:55:05.65#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.06:55:05.65#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.06:55:05.65#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:05.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:55:05.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:55:05.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:55:05.65#ibcon#enter wrdev, iclass 4, count 0 2006.285.06:55:05.65#ibcon#first serial, iclass 4, count 0 2006.285.06:55:05.65#ibcon#enter sib2, iclass 4, count 0 2006.285.06:55:05.65#ibcon#flushed, iclass 4, count 0 2006.285.06:55:05.65#ibcon#about to write, iclass 4, count 0 2006.285.06:55:05.65#ibcon#wrote, iclass 4, count 0 2006.285.06:55:05.65#ibcon#about to read 3, iclass 4, count 0 2006.285.06:55:05.67#ibcon#read 3, iclass 4, count 0 2006.285.06:55:05.67#ibcon#about to read 4, iclass 4, count 0 2006.285.06:55:05.67#ibcon#read 4, iclass 4, count 0 2006.285.06:55:05.67#ibcon#about to read 5, iclass 4, count 0 2006.285.06:55:05.67#ibcon#read 5, iclass 4, count 0 2006.285.06:55:05.67#ibcon#about to read 6, iclass 4, count 0 2006.285.06:55:05.67#ibcon#read 6, iclass 4, count 0 2006.285.06:55:05.67#ibcon#end of sib2, iclass 4, count 0 2006.285.06:55:05.67#ibcon#*mode == 0, iclass 4, count 0 2006.285.06:55:05.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.06:55:05.67#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.06:55:05.67#ibcon#*before write, iclass 4, count 0 2006.285.06:55:05.67#ibcon#enter sib2, iclass 4, count 0 2006.285.06:55:05.67#ibcon#flushed, iclass 4, count 0 2006.285.06:55:05.67#ibcon#about to write, iclass 4, count 0 2006.285.06:55:05.67#ibcon#wrote, iclass 4, count 0 2006.285.06:55:05.67#ibcon#about to read 3, iclass 4, count 0 2006.285.06:55:05.71#ibcon#read 3, iclass 4, count 0 2006.285.06:55:05.71#ibcon#about to read 4, iclass 4, count 0 2006.285.06:55:05.71#ibcon#read 4, iclass 4, count 0 2006.285.06:55:05.71#ibcon#about to read 5, iclass 4, count 0 2006.285.06:55:05.71#ibcon#read 5, iclass 4, count 0 2006.285.06:55:05.71#ibcon#about to read 6, iclass 4, count 0 2006.285.06:55:05.71#ibcon#read 6, iclass 4, count 0 2006.285.06:55:05.71#ibcon#end of sib2, iclass 4, count 0 2006.285.06:55:05.71#ibcon#*after write, iclass 4, count 0 2006.285.06:55:05.71#ibcon#*before return 0, iclass 4, count 0 2006.285.06:55:05.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:55:05.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.06:55:05.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.06:55:05.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.06:55:05.71$vck44/vb=3,4 2006.285.06:55:05.71#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.06:55:05.71#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.06:55:05.71#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:05.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:55:05.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:55:05.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:55:05.77#ibcon#enter wrdev, iclass 6, count 2 2006.285.06:55:05.77#ibcon#first serial, iclass 6, count 2 2006.285.06:55:05.77#ibcon#enter sib2, iclass 6, count 2 2006.285.06:55:05.77#ibcon#flushed, iclass 6, count 2 2006.285.06:55:05.77#ibcon#about to write, iclass 6, count 2 2006.285.06:55:05.77#ibcon#wrote, iclass 6, count 2 2006.285.06:55:05.77#ibcon#about to read 3, iclass 6, count 2 2006.285.06:55:05.79#ibcon#read 3, iclass 6, count 2 2006.285.06:55:05.79#ibcon#about to read 4, iclass 6, count 2 2006.285.06:55:05.79#ibcon#read 4, iclass 6, count 2 2006.285.06:55:05.79#ibcon#about to read 5, iclass 6, count 2 2006.285.06:55:05.79#ibcon#read 5, iclass 6, count 2 2006.285.06:55:05.79#ibcon#about to read 6, iclass 6, count 2 2006.285.06:55:05.79#ibcon#read 6, iclass 6, count 2 2006.285.06:55:05.79#ibcon#end of sib2, iclass 6, count 2 2006.285.06:55:05.79#ibcon#*mode == 0, iclass 6, count 2 2006.285.06:55:05.79#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.06:55:05.79#ibcon#[27=AT03-04\r\n] 2006.285.06:55:05.79#ibcon#*before write, iclass 6, count 2 2006.285.06:55:05.79#ibcon#enter sib2, iclass 6, count 2 2006.285.06:55:05.79#ibcon#flushed, iclass 6, count 2 2006.285.06:55:05.79#ibcon#about to write, iclass 6, count 2 2006.285.06:55:05.79#ibcon#wrote, iclass 6, count 2 2006.285.06:55:05.79#ibcon#about to read 3, iclass 6, count 2 2006.285.06:55:05.82#ibcon#read 3, iclass 6, count 2 2006.285.06:55:05.82#ibcon#about to read 4, iclass 6, count 2 2006.285.06:55:05.82#ibcon#read 4, iclass 6, count 2 2006.285.06:55:05.82#ibcon#about to read 5, iclass 6, count 2 2006.285.06:55:05.82#ibcon#read 5, iclass 6, count 2 2006.285.06:55:05.82#ibcon#about to read 6, iclass 6, count 2 2006.285.06:55:05.82#ibcon#read 6, iclass 6, count 2 2006.285.06:55:05.82#ibcon#end of sib2, iclass 6, count 2 2006.285.06:55:05.82#ibcon#*after write, iclass 6, count 2 2006.285.06:55:05.82#ibcon#*before return 0, iclass 6, count 2 2006.285.06:55:05.82#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:55:05.82#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.06:55:05.82#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.06:55:05.82#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:05.82#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:55:05.94#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:55:05.94#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:55:05.94#ibcon#enter wrdev, iclass 6, count 0 2006.285.06:55:05.94#ibcon#first serial, iclass 6, count 0 2006.285.06:55:05.94#ibcon#enter sib2, iclass 6, count 0 2006.285.06:55:05.94#ibcon#flushed, iclass 6, count 0 2006.285.06:55:05.94#ibcon#about to write, iclass 6, count 0 2006.285.06:55:05.94#ibcon#wrote, iclass 6, count 0 2006.285.06:55:05.94#ibcon#about to read 3, iclass 6, count 0 2006.285.06:55:05.96#ibcon#read 3, iclass 6, count 0 2006.285.06:55:05.96#ibcon#about to read 4, iclass 6, count 0 2006.285.06:55:05.96#ibcon#read 4, iclass 6, count 0 2006.285.06:55:05.96#ibcon#about to read 5, iclass 6, count 0 2006.285.06:55:05.96#ibcon#read 5, iclass 6, count 0 2006.285.06:55:05.96#ibcon#about to read 6, iclass 6, count 0 2006.285.06:55:05.96#ibcon#read 6, iclass 6, count 0 2006.285.06:55:05.96#ibcon#end of sib2, iclass 6, count 0 2006.285.06:55:05.96#ibcon#*mode == 0, iclass 6, count 0 2006.285.06:55:05.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.06:55:05.96#ibcon#[27=USB\r\n] 2006.285.06:55:05.96#ibcon#*before write, iclass 6, count 0 2006.285.06:55:05.96#ibcon#enter sib2, iclass 6, count 0 2006.285.06:55:05.96#ibcon#flushed, iclass 6, count 0 2006.285.06:55:05.96#ibcon#about to write, iclass 6, count 0 2006.285.06:55:05.96#ibcon#wrote, iclass 6, count 0 2006.285.06:55:05.96#ibcon#about to read 3, iclass 6, count 0 2006.285.06:55:05.99#ibcon#read 3, iclass 6, count 0 2006.285.06:55:05.99#ibcon#about to read 4, iclass 6, count 0 2006.285.06:55:05.99#ibcon#read 4, iclass 6, count 0 2006.285.06:55:05.99#ibcon#about to read 5, iclass 6, count 0 2006.285.06:55:05.99#ibcon#read 5, iclass 6, count 0 2006.285.06:55:05.99#ibcon#about to read 6, iclass 6, count 0 2006.285.06:55:05.99#ibcon#read 6, iclass 6, count 0 2006.285.06:55:05.99#ibcon#end of sib2, iclass 6, count 0 2006.285.06:55:05.99#ibcon#*after write, iclass 6, count 0 2006.285.06:55:05.99#ibcon#*before return 0, iclass 6, count 0 2006.285.06:55:05.99#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:55:05.99#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.06:55:05.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.06:55:05.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.06:55:05.99$vck44/vblo=4,679.99 2006.285.06:55:05.99#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.06:55:05.99#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.06:55:05.99#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:05.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:55:05.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:55:05.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:55:05.99#ibcon#enter wrdev, iclass 10, count 0 2006.285.06:55:05.99#ibcon#first serial, iclass 10, count 0 2006.285.06:55:05.99#ibcon#enter sib2, iclass 10, count 0 2006.285.06:55:05.99#ibcon#flushed, iclass 10, count 0 2006.285.06:55:05.99#ibcon#about to write, iclass 10, count 0 2006.285.06:55:05.99#ibcon#wrote, iclass 10, count 0 2006.285.06:55:05.99#ibcon#about to read 3, iclass 10, count 0 2006.285.06:55:06.01#ibcon#read 3, iclass 10, count 0 2006.285.06:55:06.01#ibcon#about to read 4, iclass 10, count 0 2006.285.06:55:06.01#ibcon#read 4, iclass 10, count 0 2006.285.06:55:06.01#ibcon#about to read 5, iclass 10, count 0 2006.285.06:55:06.01#ibcon#read 5, iclass 10, count 0 2006.285.06:55:06.01#ibcon#about to read 6, iclass 10, count 0 2006.285.06:55:06.01#ibcon#read 6, iclass 10, count 0 2006.285.06:55:06.01#ibcon#end of sib2, iclass 10, count 0 2006.285.06:55:06.01#ibcon#*mode == 0, iclass 10, count 0 2006.285.06:55:06.01#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.06:55:06.01#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.06:55:06.01#ibcon#*before write, iclass 10, count 0 2006.285.06:55:06.01#ibcon#enter sib2, iclass 10, count 0 2006.285.06:55:06.01#ibcon#flushed, iclass 10, count 0 2006.285.06:55:06.01#ibcon#about to write, iclass 10, count 0 2006.285.06:55:06.01#ibcon#wrote, iclass 10, count 0 2006.285.06:55:06.01#ibcon#about to read 3, iclass 10, count 0 2006.285.06:55:06.05#ibcon#read 3, iclass 10, count 0 2006.285.06:55:06.05#ibcon#about to read 4, iclass 10, count 0 2006.285.06:55:06.05#ibcon#read 4, iclass 10, count 0 2006.285.06:55:06.05#ibcon#about to read 5, iclass 10, count 0 2006.285.06:55:06.05#ibcon#read 5, iclass 10, count 0 2006.285.06:55:06.05#ibcon#about to read 6, iclass 10, count 0 2006.285.06:55:06.05#ibcon#read 6, iclass 10, count 0 2006.285.06:55:06.05#ibcon#end of sib2, iclass 10, count 0 2006.285.06:55:06.05#ibcon#*after write, iclass 10, count 0 2006.285.06:55:06.05#ibcon#*before return 0, iclass 10, count 0 2006.285.06:55:06.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:55:06.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.06:55:06.05#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.06:55:06.05#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.06:55:06.05$vck44/vb=4,5 2006.285.06:55:06.05#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.06:55:06.05#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.06:55:06.05#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:06.05#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:55:06.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:55:06.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:55:06.11#ibcon#enter wrdev, iclass 12, count 2 2006.285.06:55:06.11#ibcon#first serial, iclass 12, count 2 2006.285.06:55:06.11#ibcon#enter sib2, iclass 12, count 2 2006.285.06:55:06.11#ibcon#flushed, iclass 12, count 2 2006.285.06:55:06.11#ibcon#about to write, iclass 12, count 2 2006.285.06:55:06.11#ibcon#wrote, iclass 12, count 2 2006.285.06:55:06.11#ibcon#about to read 3, iclass 12, count 2 2006.285.06:55:06.13#ibcon#read 3, iclass 12, count 2 2006.285.06:55:06.13#ibcon#about to read 4, iclass 12, count 2 2006.285.06:55:06.13#ibcon#read 4, iclass 12, count 2 2006.285.06:55:06.13#ibcon#about to read 5, iclass 12, count 2 2006.285.06:55:06.13#ibcon#read 5, iclass 12, count 2 2006.285.06:55:06.13#ibcon#about to read 6, iclass 12, count 2 2006.285.06:55:06.13#ibcon#read 6, iclass 12, count 2 2006.285.06:55:06.13#ibcon#end of sib2, iclass 12, count 2 2006.285.06:55:06.13#ibcon#*mode == 0, iclass 12, count 2 2006.285.06:55:06.13#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.06:55:06.13#ibcon#[27=AT04-05\r\n] 2006.285.06:55:06.13#ibcon#*before write, iclass 12, count 2 2006.285.06:55:06.13#ibcon#enter sib2, iclass 12, count 2 2006.285.06:55:06.13#ibcon#flushed, iclass 12, count 2 2006.285.06:55:06.13#ibcon#about to write, iclass 12, count 2 2006.285.06:55:06.13#ibcon#wrote, iclass 12, count 2 2006.285.06:55:06.13#ibcon#about to read 3, iclass 12, count 2 2006.285.06:55:06.16#ibcon#read 3, iclass 12, count 2 2006.285.06:55:06.16#ibcon#about to read 4, iclass 12, count 2 2006.285.06:55:06.16#ibcon#read 4, iclass 12, count 2 2006.285.06:55:06.16#ibcon#about to read 5, iclass 12, count 2 2006.285.06:55:06.16#ibcon#read 5, iclass 12, count 2 2006.285.06:55:06.16#ibcon#about to read 6, iclass 12, count 2 2006.285.06:55:06.16#ibcon#read 6, iclass 12, count 2 2006.285.06:55:06.16#ibcon#end of sib2, iclass 12, count 2 2006.285.06:55:06.16#ibcon#*after write, iclass 12, count 2 2006.285.06:55:06.16#ibcon#*before return 0, iclass 12, count 2 2006.285.06:55:06.16#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:55:06.16#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.06:55:06.16#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.06:55:06.16#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:06.16#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:55:06.28#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:55:06.28#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:55:06.28#ibcon#enter wrdev, iclass 12, count 0 2006.285.06:55:06.28#ibcon#first serial, iclass 12, count 0 2006.285.06:55:06.28#ibcon#enter sib2, iclass 12, count 0 2006.285.06:55:06.28#ibcon#flushed, iclass 12, count 0 2006.285.06:55:06.28#ibcon#about to write, iclass 12, count 0 2006.285.06:55:06.28#ibcon#wrote, iclass 12, count 0 2006.285.06:55:06.28#ibcon#about to read 3, iclass 12, count 0 2006.285.06:55:06.30#ibcon#read 3, iclass 12, count 0 2006.285.06:55:06.30#ibcon#about to read 4, iclass 12, count 0 2006.285.06:55:06.30#ibcon#read 4, iclass 12, count 0 2006.285.06:55:06.30#ibcon#about to read 5, iclass 12, count 0 2006.285.06:55:06.30#ibcon#read 5, iclass 12, count 0 2006.285.06:55:06.30#ibcon#about to read 6, iclass 12, count 0 2006.285.06:55:06.30#ibcon#read 6, iclass 12, count 0 2006.285.06:55:06.30#ibcon#end of sib2, iclass 12, count 0 2006.285.06:55:06.30#ibcon#*mode == 0, iclass 12, count 0 2006.285.06:55:06.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.06:55:06.30#ibcon#[27=USB\r\n] 2006.285.06:55:06.30#ibcon#*before write, iclass 12, count 0 2006.285.06:55:06.30#ibcon#enter sib2, iclass 12, count 0 2006.285.06:55:06.30#ibcon#flushed, iclass 12, count 0 2006.285.06:55:06.30#ibcon#about to write, iclass 12, count 0 2006.285.06:55:06.30#ibcon#wrote, iclass 12, count 0 2006.285.06:55:06.30#ibcon#about to read 3, iclass 12, count 0 2006.285.06:55:06.33#ibcon#read 3, iclass 12, count 0 2006.285.06:55:06.33#ibcon#about to read 4, iclass 12, count 0 2006.285.06:55:06.33#ibcon#read 4, iclass 12, count 0 2006.285.06:55:06.33#ibcon#about to read 5, iclass 12, count 0 2006.285.06:55:06.33#ibcon#read 5, iclass 12, count 0 2006.285.06:55:06.33#ibcon#about to read 6, iclass 12, count 0 2006.285.06:55:06.33#ibcon#read 6, iclass 12, count 0 2006.285.06:55:06.33#ibcon#end of sib2, iclass 12, count 0 2006.285.06:55:06.33#ibcon#*after write, iclass 12, count 0 2006.285.06:55:06.33#ibcon#*before return 0, iclass 12, count 0 2006.285.06:55:06.33#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:55:06.33#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.06:55:06.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.06:55:06.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.06:55:06.33$vck44/vblo=5,709.99 2006.285.06:55:06.33#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.06:55:06.33#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.06:55:06.33#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:06.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:55:06.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:55:06.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:55:06.33#ibcon#enter wrdev, iclass 14, count 0 2006.285.06:55:06.33#ibcon#first serial, iclass 14, count 0 2006.285.06:55:06.33#ibcon#enter sib2, iclass 14, count 0 2006.285.06:55:06.33#ibcon#flushed, iclass 14, count 0 2006.285.06:55:06.33#ibcon#about to write, iclass 14, count 0 2006.285.06:55:06.33#ibcon#wrote, iclass 14, count 0 2006.285.06:55:06.33#ibcon#about to read 3, iclass 14, count 0 2006.285.06:55:06.35#ibcon#read 3, iclass 14, count 0 2006.285.06:55:06.35#ibcon#about to read 4, iclass 14, count 0 2006.285.06:55:06.35#ibcon#read 4, iclass 14, count 0 2006.285.06:55:06.35#ibcon#about to read 5, iclass 14, count 0 2006.285.06:55:06.35#ibcon#read 5, iclass 14, count 0 2006.285.06:55:06.35#ibcon#about to read 6, iclass 14, count 0 2006.285.06:55:06.35#ibcon#read 6, iclass 14, count 0 2006.285.06:55:06.35#ibcon#end of sib2, iclass 14, count 0 2006.285.06:55:06.35#ibcon#*mode == 0, iclass 14, count 0 2006.285.06:55:06.35#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.06:55:06.35#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.06:55:06.35#ibcon#*before write, iclass 14, count 0 2006.285.06:55:06.35#ibcon#enter sib2, iclass 14, count 0 2006.285.06:55:06.35#ibcon#flushed, iclass 14, count 0 2006.285.06:55:06.35#ibcon#about to write, iclass 14, count 0 2006.285.06:55:06.35#ibcon#wrote, iclass 14, count 0 2006.285.06:55:06.35#ibcon#about to read 3, iclass 14, count 0 2006.285.06:55:06.39#ibcon#read 3, iclass 14, count 0 2006.285.06:55:06.39#ibcon#about to read 4, iclass 14, count 0 2006.285.06:55:06.39#ibcon#read 4, iclass 14, count 0 2006.285.06:55:06.39#ibcon#about to read 5, iclass 14, count 0 2006.285.06:55:06.39#ibcon#read 5, iclass 14, count 0 2006.285.06:55:06.39#ibcon#about to read 6, iclass 14, count 0 2006.285.06:55:06.39#ibcon#read 6, iclass 14, count 0 2006.285.06:55:06.39#ibcon#end of sib2, iclass 14, count 0 2006.285.06:55:06.39#ibcon#*after write, iclass 14, count 0 2006.285.06:55:06.39#ibcon#*before return 0, iclass 14, count 0 2006.285.06:55:06.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:55:06.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.06:55:06.39#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.06:55:06.39#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.06:55:06.39$vck44/vb=5,4 2006.285.06:55:06.39#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.06:55:06.39#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.06:55:06.39#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:06.39#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:55:06.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:55:06.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:55:06.45#ibcon#enter wrdev, iclass 16, count 2 2006.285.06:55:06.45#ibcon#first serial, iclass 16, count 2 2006.285.06:55:06.45#ibcon#enter sib2, iclass 16, count 2 2006.285.06:55:06.45#ibcon#flushed, iclass 16, count 2 2006.285.06:55:06.45#ibcon#about to write, iclass 16, count 2 2006.285.06:55:06.45#ibcon#wrote, iclass 16, count 2 2006.285.06:55:06.45#ibcon#about to read 3, iclass 16, count 2 2006.285.06:55:06.47#ibcon#read 3, iclass 16, count 2 2006.285.06:55:06.47#ibcon#about to read 4, iclass 16, count 2 2006.285.06:55:06.47#ibcon#read 4, iclass 16, count 2 2006.285.06:55:06.47#ibcon#about to read 5, iclass 16, count 2 2006.285.06:55:06.47#ibcon#read 5, iclass 16, count 2 2006.285.06:55:06.47#ibcon#about to read 6, iclass 16, count 2 2006.285.06:55:06.47#ibcon#read 6, iclass 16, count 2 2006.285.06:55:06.47#ibcon#end of sib2, iclass 16, count 2 2006.285.06:55:06.47#ibcon#*mode == 0, iclass 16, count 2 2006.285.06:55:06.47#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.06:55:06.47#ibcon#[27=AT05-04\r\n] 2006.285.06:55:06.47#ibcon#*before write, iclass 16, count 2 2006.285.06:55:06.47#ibcon#enter sib2, iclass 16, count 2 2006.285.06:55:06.47#ibcon#flushed, iclass 16, count 2 2006.285.06:55:06.47#ibcon#about to write, iclass 16, count 2 2006.285.06:55:06.47#ibcon#wrote, iclass 16, count 2 2006.285.06:55:06.47#ibcon#about to read 3, iclass 16, count 2 2006.285.06:55:06.50#ibcon#read 3, iclass 16, count 2 2006.285.06:55:06.50#ibcon#about to read 4, iclass 16, count 2 2006.285.06:55:06.50#ibcon#read 4, iclass 16, count 2 2006.285.06:55:06.50#ibcon#about to read 5, iclass 16, count 2 2006.285.06:55:06.50#ibcon#read 5, iclass 16, count 2 2006.285.06:55:06.50#ibcon#about to read 6, iclass 16, count 2 2006.285.06:55:06.50#ibcon#read 6, iclass 16, count 2 2006.285.06:55:06.50#ibcon#end of sib2, iclass 16, count 2 2006.285.06:55:06.50#ibcon#*after write, iclass 16, count 2 2006.285.06:55:06.50#ibcon#*before return 0, iclass 16, count 2 2006.285.06:55:06.50#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:55:06.50#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.06:55:06.50#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.06:55:06.50#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:06.50#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:55:06.62#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:55:06.62#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:55:06.62#ibcon#enter wrdev, iclass 16, count 0 2006.285.06:55:06.62#ibcon#first serial, iclass 16, count 0 2006.285.06:55:06.62#ibcon#enter sib2, iclass 16, count 0 2006.285.06:55:06.62#ibcon#flushed, iclass 16, count 0 2006.285.06:55:06.62#ibcon#about to write, iclass 16, count 0 2006.285.06:55:06.62#ibcon#wrote, iclass 16, count 0 2006.285.06:55:06.62#ibcon#about to read 3, iclass 16, count 0 2006.285.06:55:06.64#ibcon#read 3, iclass 16, count 0 2006.285.06:55:06.64#ibcon#about to read 4, iclass 16, count 0 2006.285.06:55:06.64#ibcon#read 4, iclass 16, count 0 2006.285.06:55:06.64#ibcon#about to read 5, iclass 16, count 0 2006.285.06:55:06.64#ibcon#read 5, iclass 16, count 0 2006.285.06:55:06.64#ibcon#about to read 6, iclass 16, count 0 2006.285.06:55:06.64#ibcon#read 6, iclass 16, count 0 2006.285.06:55:06.64#ibcon#end of sib2, iclass 16, count 0 2006.285.06:55:06.64#ibcon#*mode == 0, iclass 16, count 0 2006.285.06:55:06.64#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.06:55:06.64#ibcon#[27=USB\r\n] 2006.285.06:55:06.64#ibcon#*before write, iclass 16, count 0 2006.285.06:55:06.64#ibcon#enter sib2, iclass 16, count 0 2006.285.06:55:06.64#ibcon#flushed, iclass 16, count 0 2006.285.06:55:06.64#ibcon#about to write, iclass 16, count 0 2006.285.06:55:06.64#ibcon#wrote, iclass 16, count 0 2006.285.06:55:06.64#ibcon#about to read 3, iclass 16, count 0 2006.285.06:55:06.67#ibcon#read 3, iclass 16, count 0 2006.285.06:55:06.67#ibcon#about to read 4, iclass 16, count 0 2006.285.06:55:06.67#ibcon#read 4, iclass 16, count 0 2006.285.06:55:06.67#ibcon#about to read 5, iclass 16, count 0 2006.285.06:55:06.67#ibcon#read 5, iclass 16, count 0 2006.285.06:55:06.67#ibcon#about to read 6, iclass 16, count 0 2006.285.06:55:06.67#ibcon#read 6, iclass 16, count 0 2006.285.06:55:06.67#ibcon#end of sib2, iclass 16, count 0 2006.285.06:55:06.67#ibcon#*after write, iclass 16, count 0 2006.285.06:55:06.67#ibcon#*before return 0, iclass 16, count 0 2006.285.06:55:06.67#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:55:06.67#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.06:55:06.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.06:55:06.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.06:55:06.67$vck44/vblo=6,719.99 2006.285.06:55:06.67#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.06:55:06.67#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.06:55:06.67#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:06.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:55:06.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:55:06.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:55:06.67#ibcon#enter wrdev, iclass 18, count 0 2006.285.06:55:06.67#ibcon#first serial, iclass 18, count 0 2006.285.06:55:06.67#ibcon#enter sib2, iclass 18, count 0 2006.285.06:55:06.67#ibcon#flushed, iclass 18, count 0 2006.285.06:55:06.67#ibcon#about to write, iclass 18, count 0 2006.285.06:55:06.67#ibcon#wrote, iclass 18, count 0 2006.285.06:55:06.67#ibcon#about to read 3, iclass 18, count 0 2006.285.06:55:06.69#ibcon#read 3, iclass 18, count 0 2006.285.06:55:06.69#ibcon#about to read 4, iclass 18, count 0 2006.285.06:55:06.69#ibcon#read 4, iclass 18, count 0 2006.285.06:55:06.69#ibcon#about to read 5, iclass 18, count 0 2006.285.06:55:06.69#ibcon#read 5, iclass 18, count 0 2006.285.06:55:06.69#ibcon#about to read 6, iclass 18, count 0 2006.285.06:55:06.69#ibcon#read 6, iclass 18, count 0 2006.285.06:55:06.69#ibcon#end of sib2, iclass 18, count 0 2006.285.06:55:06.69#ibcon#*mode == 0, iclass 18, count 0 2006.285.06:55:06.69#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.06:55:06.69#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.06:55:06.69#ibcon#*before write, iclass 18, count 0 2006.285.06:55:06.69#ibcon#enter sib2, iclass 18, count 0 2006.285.06:55:06.69#ibcon#flushed, iclass 18, count 0 2006.285.06:55:06.69#ibcon#about to write, iclass 18, count 0 2006.285.06:55:06.69#ibcon#wrote, iclass 18, count 0 2006.285.06:55:06.69#ibcon#about to read 3, iclass 18, count 0 2006.285.06:55:06.73#ibcon#read 3, iclass 18, count 0 2006.285.06:55:06.73#ibcon#about to read 4, iclass 18, count 0 2006.285.06:55:06.73#ibcon#read 4, iclass 18, count 0 2006.285.06:55:06.73#ibcon#about to read 5, iclass 18, count 0 2006.285.06:55:06.73#ibcon#read 5, iclass 18, count 0 2006.285.06:55:06.73#ibcon#about to read 6, iclass 18, count 0 2006.285.06:55:06.73#ibcon#read 6, iclass 18, count 0 2006.285.06:55:06.73#ibcon#end of sib2, iclass 18, count 0 2006.285.06:55:06.73#ibcon#*after write, iclass 18, count 0 2006.285.06:55:06.73#ibcon#*before return 0, iclass 18, count 0 2006.285.06:55:06.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:55:06.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.06:55:06.73#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.06:55:06.73#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.06:55:06.73$vck44/vb=6,3 2006.285.06:55:06.73#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.06:55:06.73#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.06:55:06.73#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:06.73#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:55:06.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:55:06.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:55:06.79#ibcon#enter wrdev, iclass 20, count 2 2006.285.06:55:06.79#ibcon#first serial, iclass 20, count 2 2006.285.06:55:06.79#ibcon#enter sib2, iclass 20, count 2 2006.285.06:55:06.79#ibcon#flushed, iclass 20, count 2 2006.285.06:55:06.79#ibcon#about to write, iclass 20, count 2 2006.285.06:55:06.79#ibcon#wrote, iclass 20, count 2 2006.285.06:55:06.79#ibcon#about to read 3, iclass 20, count 2 2006.285.06:55:06.81#ibcon#read 3, iclass 20, count 2 2006.285.06:55:06.81#ibcon#about to read 4, iclass 20, count 2 2006.285.06:55:06.81#ibcon#read 4, iclass 20, count 2 2006.285.06:55:06.81#ibcon#about to read 5, iclass 20, count 2 2006.285.06:55:06.81#ibcon#read 5, iclass 20, count 2 2006.285.06:55:06.81#ibcon#about to read 6, iclass 20, count 2 2006.285.06:55:06.81#ibcon#read 6, iclass 20, count 2 2006.285.06:55:06.81#ibcon#end of sib2, iclass 20, count 2 2006.285.06:55:06.81#ibcon#*mode == 0, iclass 20, count 2 2006.285.06:55:06.81#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.06:55:06.81#ibcon#[27=AT06-03\r\n] 2006.285.06:55:06.81#ibcon#*before write, iclass 20, count 2 2006.285.06:55:06.81#ibcon#enter sib2, iclass 20, count 2 2006.285.06:55:06.81#ibcon#flushed, iclass 20, count 2 2006.285.06:55:06.81#ibcon#about to write, iclass 20, count 2 2006.285.06:55:06.81#ibcon#wrote, iclass 20, count 2 2006.285.06:55:06.81#ibcon#about to read 3, iclass 20, count 2 2006.285.06:55:06.84#ibcon#read 3, iclass 20, count 2 2006.285.06:55:06.84#ibcon#about to read 4, iclass 20, count 2 2006.285.06:55:06.84#ibcon#read 4, iclass 20, count 2 2006.285.06:55:06.84#ibcon#about to read 5, iclass 20, count 2 2006.285.06:55:06.84#ibcon#read 5, iclass 20, count 2 2006.285.06:55:06.84#ibcon#about to read 6, iclass 20, count 2 2006.285.06:55:06.84#ibcon#read 6, iclass 20, count 2 2006.285.06:55:06.84#ibcon#end of sib2, iclass 20, count 2 2006.285.06:55:06.84#ibcon#*after write, iclass 20, count 2 2006.285.06:55:06.84#ibcon#*before return 0, iclass 20, count 2 2006.285.06:55:06.84#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:55:06.84#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.06:55:06.84#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.06:55:06.84#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:06.84#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:55:06.96#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:55:06.96#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:55:06.96#ibcon#enter wrdev, iclass 20, count 0 2006.285.06:55:06.96#ibcon#first serial, iclass 20, count 0 2006.285.06:55:06.96#ibcon#enter sib2, iclass 20, count 0 2006.285.06:55:06.96#ibcon#flushed, iclass 20, count 0 2006.285.06:55:06.96#ibcon#about to write, iclass 20, count 0 2006.285.06:55:06.96#ibcon#wrote, iclass 20, count 0 2006.285.06:55:06.96#ibcon#about to read 3, iclass 20, count 0 2006.285.06:55:06.98#ibcon#read 3, iclass 20, count 0 2006.285.06:55:06.98#ibcon#about to read 4, iclass 20, count 0 2006.285.06:55:06.98#ibcon#read 4, iclass 20, count 0 2006.285.06:55:06.98#ibcon#about to read 5, iclass 20, count 0 2006.285.06:55:06.98#ibcon#read 5, iclass 20, count 0 2006.285.06:55:06.98#ibcon#about to read 6, iclass 20, count 0 2006.285.06:55:06.98#ibcon#read 6, iclass 20, count 0 2006.285.06:55:06.98#ibcon#end of sib2, iclass 20, count 0 2006.285.06:55:06.98#ibcon#*mode == 0, iclass 20, count 0 2006.285.06:55:06.98#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.06:55:06.98#ibcon#[27=USB\r\n] 2006.285.06:55:06.98#ibcon#*before write, iclass 20, count 0 2006.285.06:55:06.98#ibcon#enter sib2, iclass 20, count 0 2006.285.06:55:06.98#ibcon#flushed, iclass 20, count 0 2006.285.06:55:06.98#ibcon#about to write, iclass 20, count 0 2006.285.06:55:06.98#ibcon#wrote, iclass 20, count 0 2006.285.06:55:06.98#ibcon#about to read 3, iclass 20, count 0 2006.285.06:55:07.01#ibcon#read 3, iclass 20, count 0 2006.285.06:55:07.01#ibcon#about to read 4, iclass 20, count 0 2006.285.06:55:07.01#ibcon#read 4, iclass 20, count 0 2006.285.06:55:07.01#ibcon#about to read 5, iclass 20, count 0 2006.285.06:55:07.01#ibcon#read 5, iclass 20, count 0 2006.285.06:55:07.01#ibcon#about to read 6, iclass 20, count 0 2006.285.06:55:07.01#ibcon#read 6, iclass 20, count 0 2006.285.06:55:07.01#ibcon#end of sib2, iclass 20, count 0 2006.285.06:55:07.01#ibcon#*after write, iclass 20, count 0 2006.285.06:55:07.01#ibcon#*before return 0, iclass 20, count 0 2006.285.06:55:07.01#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:55:07.01#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.06:55:07.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.06:55:07.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.06:55:07.01$vck44/vblo=7,734.99 2006.285.06:55:07.01#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.06:55:07.01#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.06:55:07.01#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:07.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:55:07.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:55:07.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:55:07.01#ibcon#enter wrdev, iclass 22, count 0 2006.285.06:55:07.01#ibcon#first serial, iclass 22, count 0 2006.285.06:55:07.01#ibcon#enter sib2, iclass 22, count 0 2006.285.06:55:07.01#ibcon#flushed, iclass 22, count 0 2006.285.06:55:07.01#ibcon#about to write, iclass 22, count 0 2006.285.06:55:07.01#ibcon#wrote, iclass 22, count 0 2006.285.06:55:07.01#ibcon#about to read 3, iclass 22, count 0 2006.285.06:55:07.03#ibcon#read 3, iclass 22, count 0 2006.285.06:55:07.03#ibcon#about to read 4, iclass 22, count 0 2006.285.06:55:07.03#ibcon#read 4, iclass 22, count 0 2006.285.06:55:07.03#ibcon#about to read 5, iclass 22, count 0 2006.285.06:55:07.03#ibcon#read 5, iclass 22, count 0 2006.285.06:55:07.03#ibcon#about to read 6, iclass 22, count 0 2006.285.06:55:07.03#ibcon#read 6, iclass 22, count 0 2006.285.06:55:07.03#ibcon#end of sib2, iclass 22, count 0 2006.285.06:55:07.03#ibcon#*mode == 0, iclass 22, count 0 2006.285.06:55:07.03#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.06:55:07.03#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.06:55:07.03#ibcon#*before write, iclass 22, count 0 2006.285.06:55:07.03#ibcon#enter sib2, iclass 22, count 0 2006.285.06:55:07.03#ibcon#flushed, iclass 22, count 0 2006.285.06:55:07.03#ibcon#about to write, iclass 22, count 0 2006.285.06:55:07.03#ibcon#wrote, iclass 22, count 0 2006.285.06:55:07.03#ibcon#about to read 3, iclass 22, count 0 2006.285.06:55:07.07#ibcon#read 3, iclass 22, count 0 2006.285.06:55:07.07#ibcon#about to read 4, iclass 22, count 0 2006.285.06:55:07.07#ibcon#read 4, iclass 22, count 0 2006.285.06:55:07.07#ibcon#about to read 5, iclass 22, count 0 2006.285.06:55:07.07#ibcon#read 5, iclass 22, count 0 2006.285.06:55:07.07#ibcon#about to read 6, iclass 22, count 0 2006.285.06:55:07.07#ibcon#read 6, iclass 22, count 0 2006.285.06:55:07.07#ibcon#end of sib2, iclass 22, count 0 2006.285.06:55:07.07#ibcon#*after write, iclass 22, count 0 2006.285.06:55:07.07#ibcon#*before return 0, iclass 22, count 0 2006.285.06:55:07.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:55:07.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.06:55:07.07#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.06:55:07.07#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.06:55:07.07$vck44/vb=7,4 2006.285.06:55:07.07#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.06:55:07.07#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.06:55:07.07#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:07.07#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:55:07.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:55:07.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:55:07.13#ibcon#enter wrdev, iclass 24, count 2 2006.285.06:55:07.13#ibcon#first serial, iclass 24, count 2 2006.285.06:55:07.13#ibcon#enter sib2, iclass 24, count 2 2006.285.06:55:07.13#ibcon#flushed, iclass 24, count 2 2006.285.06:55:07.13#ibcon#about to write, iclass 24, count 2 2006.285.06:55:07.13#ibcon#wrote, iclass 24, count 2 2006.285.06:55:07.13#ibcon#about to read 3, iclass 24, count 2 2006.285.06:55:07.15#ibcon#read 3, iclass 24, count 2 2006.285.06:55:07.15#ibcon#about to read 4, iclass 24, count 2 2006.285.06:55:07.15#ibcon#read 4, iclass 24, count 2 2006.285.06:55:07.15#ibcon#about to read 5, iclass 24, count 2 2006.285.06:55:07.15#ibcon#read 5, iclass 24, count 2 2006.285.06:55:07.15#ibcon#about to read 6, iclass 24, count 2 2006.285.06:55:07.15#ibcon#read 6, iclass 24, count 2 2006.285.06:55:07.15#ibcon#end of sib2, iclass 24, count 2 2006.285.06:55:07.15#ibcon#*mode == 0, iclass 24, count 2 2006.285.06:55:07.15#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.06:55:07.15#ibcon#[27=AT07-04\r\n] 2006.285.06:55:07.15#ibcon#*before write, iclass 24, count 2 2006.285.06:55:07.15#ibcon#enter sib2, iclass 24, count 2 2006.285.06:55:07.15#ibcon#flushed, iclass 24, count 2 2006.285.06:55:07.15#ibcon#about to write, iclass 24, count 2 2006.285.06:55:07.15#ibcon#wrote, iclass 24, count 2 2006.285.06:55:07.15#ibcon#about to read 3, iclass 24, count 2 2006.285.06:55:07.18#ibcon#read 3, iclass 24, count 2 2006.285.06:55:07.18#ibcon#about to read 4, iclass 24, count 2 2006.285.06:55:07.18#ibcon#read 4, iclass 24, count 2 2006.285.06:55:07.18#ibcon#about to read 5, iclass 24, count 2 2006.285.06:55:07.18#ibcon#read 5, iclass 24, count 2 2006.285.06:55:07.18#ibcon#about to read 6, iclass 24, count 2 2006.285.06:55:07.18#ibcon#read 6, iclass 24, count 2 2006.285.06:55:07.18#ibcon#end of sib2, iclass 24, count 2 2006.285.06:55:07.18#ibcon#*after write, iclass 24, count 2 2006.285.06:55:07.18#ibcon#*before return 0, iclass 24, count 2 2006.285.06:55:07.18#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:55:07.18#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.06:55:07.18#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.06:55:07.18#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:07.18#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:55:07.30#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:55:07.30#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:55:07.30#ibcon#enter wrdev, iclass 24, count 0 2006.285.06:55:07.30#ibcon#first serial, iclass 24, count 0 2006.285.06:55:07.30#ibcon#enter sib2, iclass 24, count 0 2006.285.06:55:07.30#ibcon#flushed, iclass 24, count 0 2006.285.06:55:07.30#ibcon#about to write, iclass 24, count 0 2006.285.06:55:07.30#ibcon#wrote, iclass 24, count 0 2006.285.06:55:07.30#ibcon#about to read 3, iclass 24, count 0 2006.285.06:55:07.32#ibcon#read 3, iclass 24, count 0 2006.285.06:55:07.32#ibcon#about to read 4, iclass 24, count 0 2006.285.06:55:07.32#ibcon#read 4, iclass 24, count 0 2006.285.06:55:07.32#ibcon#about to read 5, iclass 24, count 0 2006.285.06:55:07.32#ibcon#read 5, iclass 24, count 0 2006.285.06:55:07.32#ibcon#about to read 6, iclass 24, count 0 2006.285.06:55:07.32#ibcon#read 6, iclass 24, count 0 2006.285.06:55:07.32#ibcon#end of sib2, iclass 24, count 0 2006.285.06:55:07.32#ibcon#*mode == 0, iclass 24, count 0 2006.285.06:55:07.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.06:55:07.32#ibcon#[27=USB\r\n] 2006.285.06:55:07.32#ibcon#*before write, iclass 24, count 0 2006.285.06:55:07.32#ibcon#enter sib2, iclass 24, count 0 2006.285.06:55:07.32#ibcon#flushed, iclass 24, count 0 2006.285.06:55:07.32#ibcon#about to write, iclass 24, count 0 2006.285.06:55:07.32#ibcon#wrote, iclass 24, count 0 2006.285.06:55:07.32#ibcon#about to read 3, iclass 24, count 0 2006.285.06:55:07.35#ibcon#read 3, iclass 24, count 0 2006.285.06:55:07.35#ibcon#about to read 4, iclass 24, count 0 2006.285.06:55:07.35#ibcon#read 4, iclass 24, count 0 2006.285.06:55:07.35#ibcon#about to read 5, iclass 24, count 0 2006.285.06:55:07.35#ibcon#read 5, iclass 24, count 0 2006.285.06:55:07.35#ibcon#about to read 6, iclass 24, count 0 2006.285.06:55:07.35#ibcon#read 6, iclass 24, count 0 2006.285.06:55:07.35#ibcon#end of sib2, iclass 24, count 0 2006.285.06:55:07.35#ibcon#*after write, iclass 24, count 0 2006.285.06:55:07.35#ibcon#*before return 0, iclass 24, count 0 2006.285.06:55:07.35#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:55:07.35#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.06:55:07.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.06:55:07.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.06:55:07.35$vck44/vblo=8,744.99 2006.285.06:55:07.35#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.06:55:07.35#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.06:55:07.35#ibcon#ireg 17 cls_cnt 0 2006.285.06:55:07.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:55:07.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:55:07.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:55:07.35#ibcon#enter wrdev, iclass 26, count 0 2006.285.06:55:07.35#ibcon#first serial, iclass 26, count 0 2006.285.06:55:07.35#ibcon#enter sib2, iclass 26, count 0 2006.285.06:55:07.35#ibcon#flushed, iclass 26, count 0 2006.285.06:55:07.35#ibcon#about to write, iclass 26, count 0 2006.285.06:55:07.35#ibcon#wrote, iclass 26, count 0 2006.285.06:55:07.35#ibcon#about to read 3, iclass 26, count 0 2006.285.06:55:07.37#ibcon#read 3, iclass 26, count 0 2006.285.06:55:07.37#ibcon#about to read 4, iclass 26, count 0 2006.285.06:55:07.37#ibcon#read 4, iclass 26, count 0 2006.285.06:55:07.37#ibcon#about to read 5, iclass 26, count 0 2006.285.06:55:07.37#ibcon#read 5, iclass 26, count 0 2006.285.06:55:07.37#ibcon#about to read 6, iclass 26, count 0 2006.285.06:55:07.37#ibcon#read 6, iclass 26, count 0 2006.285.06:55:07.37#ibcon#end of sib2, iclass 26, count 0 2006.285.06:55:07.37#ibcon#*mode == 0, iclass 26, count 0 2006.285.06:55:07.37#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.06:55:07.37#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.06:55:07.37#ibcon#*before write, iclass 26, count 0 2006.285.06:55:07.37#ibcon#enter sib2, iclass 26, count 0 2006.285.06:55:07.37#ibcon#flushed, iclass 26, count 0 2006.285.06:55:07.37#ibcon#about to write, iclass 26, count 0 2006.285.06:55:07.37#ibcon#wrote, iclass 26, count 0 2006.285.06:55:07.37#ibcon#about to read 3, iclass 26, count 0 2006.285.06:55:07.41#ibcon#read 3, iclass 26, count 0 2006.285.06:55:07.41#ibcon#about to read 4, iclass 26, count 0 2006.285.06:55:07.41#ibcon#read 4, iclass 26, count 0 2006.285.06:55:07.41#ibcon#about to read 5, iclass 26, count 0 2006.285.06:55:07.41#ibcon#read 5, iclass 26, count 0 2006.285.06:55:07.41#ibcon#about to read 6, iclass 26, count 0 2006.285.06:55:07.41#ibcon#read 6, iclass 26, count 0 2006.285.06:55:07.41#ibcon#end of sib2, iclass 26, count 0 2006.285.06:55:07.41#ibcon#*after write, iclass 26, count 0 2006.285.06:55:07.41#ibcon#*before return 0, iclass 26, count 0 2006.285.06:55:07.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:55:07.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.06:55:07.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.06:55:07.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.06:55:07.41$vck44/vb=8,4 2006.285.06:55:07.41#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.06:55:07.41#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.06:55:07.41#ibcon#ireg 11 cls_cnt 2 2006.285.06:55:07.41#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:55:07.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:55:07.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:55:07.47#ibcon#enter wrdev, iclass 28, count 2 2006.285.06:55:07.47#ibcon#first serial, iclass 28, count 2 2006.285.06:55:07.47#ibcon#enter sib2, iclass 28, count 2 2006.285.06:55:07.47#ibcon#flushed, iclass 28, count 2 2006.285.06:55:07.47#ibcon#about to write, iclass 28, count 2 2006.285.06:55:07.47#ibcon#wrote, iclass 28, count 2 2006.285.06:55:07.47#ibcon#about to read 3, iclass 28, count 2 2006.285.06:55:07.49#ibcon#read 3, iclass 28, count 2 2006.285.06:55:07.49#ibcon#about to read 4, iclass 28, count 2 2006.285.06:55:07.49#ibcon#read 4, iclass 28, count 2 2006.285.06:55:07.49#ibcon#about to read 5, iclass 28, count 2 2006.285.06:55:07.49#ibcon#read 5, iclass 28, count 2 2006.285.06:55:07.49#ibcon#about to read 6, iclass 28, count 2 2006.285.06:55:07.49#ibcon#read 6, iclass 28, count 2 2006.285.06:55:07.49#ibcon#end of sib2, iclass 28, count 2 2006.285.06:55:07.49#ibcon#*mode == 0, iclass 28, count 2 2006.285.06:55:07.49#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.06:55:07.49#ibcon#[27=AT08-04\r\n] 2006.285.06:55:07.49#ibcon#*before write, iclass 28, count 2 2006.285.06:55:07.49#ibcon#enter sib2, iclass 28, count 2 2006.285.06:55:07.49#ibcon#flushed, iclass 28, count 2 2006.285.06:55:07.49#ibcon#about to write, iclass 28, count 2 2006.285.06:55:07.49#ibcon#wrote, iclass 28, count 2 2006.285.06:55:07.49#ibcon#about to read 3, iclass 28, count 2 2006.285.06:55:07.52#ibcon#read 3, iclass 28, count 2 2006.285.06:55:07.52#ibcon#about to read 4, iclass 28, count 2 2006.285.06:55:07.52#ibcon#read 4, iclass 28, count 2 2006.285.06:55:07.52#ibcon#about to read 5, iclass 28, count 2 2006.285.06:55:07.52#ibcon#read 5, iclass 28, count 2 2006.285.06:55:07.52#ibcon#about to read 6, iclass 28, count 2 2006.285.06:55:07.52#ibcon#read 6, iclass 28, count 2 2006.285.06:55:07.52#ibcon#end of sib2, iclass 28, count 2 2006.285.06:55:07.52#ibcon#*after write, iclass 28, count 2 2006.285.06:55:07.52#ibcon#*before return 0, iclass 28, count 2 2006.285.06:55:07.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:55:07.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.06:55:07.52#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.06:55:07.52#ibcon#ireg 7 cls_cnt 0 2006.285.06:55:07.52#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:55:07.64#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:55:07.64#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:55:07.64#ibcon#enter wrdev, iclass 28, count 0 2006.285.06:55:07.64#ibcon#first serial, iclass 28, count 0 2006.285.06:55:07.64#ibcon#enter sib2, iclass 28, count 0 2006.285.06:55:07.64#ibcon#flushed, iclass 28, count 0 2006.285.06:55:07.64#ibcon#about to write, iclass 28, count 0 2006.285.06:55:07.64#ibcon#wrote, iclass 28, count 0 2006.285.06:55:07.64#ibcon#about to read 3, iclass 28, count 0 2006.285.06:55:07.66#ibcon#read 3, iclass 28, count 0 2006.285.06:55:07.66#ibcon#about to read 4, iclass 28, count 0 2006.285.06:55:07.66#ibcon#read 4, iclass 28, count 0 2006.285.06:55:07.66#ibcon#about to read 5, iclass 28, count 0 2006.285.06:55:07.66#ibcon#read 5, iclass 28, count 0 2006.285.06:55:07.66#ibcon#about to read 6, iclass 28, count 0 2006.285.06:55:07.66#ibcon#read 6, iclass 28, count 0 2006.285.06:55:07.66#ibcon#end of sib2, iclass 28, count 0 2006.285.06:55:07.66#ibcon#*mode == 0, iclass 28, count 0 2006.285.06:55:07.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.06:55:07.66#ibcon#[27=USB\r\n] 2006.285.06:55:07.66#ibcon#*before write, iclass 28, count 0 2006.285.06:55:07.66#ibcon#enter sib2, iclass 28, count 0 2006.285.06:55:07.66#ibcon#flushed, iclass 28, count 0 2006.285.06:55:07.66#ibcon#about to write, iclass 28, count 0 2006.285.06:55:07.66#ibcon#wrote, iclass 28, count 0 2006.285.06:55:07.66#ibcon#about to read 3, iclass 28, count 0 2006.285.06:55:07.69#ibcon#read 3, iclass 28, count 0 2006.285.06:55:07.69#ibcon#about to read 4, iclass 28, count 0 2006.285.06:55:07.69#ibcon#read 4, iclass 28, count 0 2006.285.06:55:07.69#ibcon#about to read 5, iclass 28, count 0 2006.285.06:55:07.69#ibcon#read 5, iclass 28, count 0 2006.285.06:55:07.69#ibcon#about to read 6, iclass 28, count 0 2006.285.06:55:07.69#ibcon#read 6, iclass 28, count 0 2006.285.06:55:07.69#ibcon#end of sib2, iclass 28, count 0 2006.285.06:55:07.69#ibcon#*after write, iclass 28, count 0 2006.285.06:55:07.69#ibcon#*before return 0, iclass 28, count 0 2006.285.06:55:07.69#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:55:07.69#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.06:55:07.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.06:55:07.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.06:55:07.69$vck44/vabw=wide 2006.285.06:55:07.69#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.06:55:07.69#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.06:55:07.69#ibcon#ireg 8 cls_cnt 0 2006.285.06:55:07.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:55:07.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:55:07.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:55:07.69#ibcon#enter wrdev, iclass 30, count 0 2006.285.06:55:07.69#ibcon#first serial, iclass 30, count 0 2006.285.06:55:07.69#ibcon#enter sib2, iclass 30, count 0 2006.285.06:55:07.69#ibcon#flushed, iclass 30, count 0 2006.285.06:55:07.69#ibcon#about to write, iclass 30, count 0 2006.285.06:55:07.69#ibcon#wrote, iclass 30, count 0 2006.285.06:55:07.69#ibcon#about to read 3, iclass 30, count 0 2006.285.06:55:07.71#ibcon#read 3, iclass 30, count 0 2006.285.06:55:07.71#ibcon#about to read 4, iclass 30, count 0 2006.285.06:55:07.71#ibcon#read 4, iclass 30, count 0 2006.285.06:55:07.71#ibcon#about to read 5, iclass 30, count 0 2006.285.06:55:07.71#ibcon#read 5, iclass 30, count 0 2006.285.06:55:07.71#ibcon#about to read 6, iclass 30, count 0 2006.285.06:55:07.71#ibcon#read 6, iclass 30, count 0 2006.285.06:55:07.71#ibcon#end of sib2, iclass 30, count 0 2006.285.06:55:07.71#ibcon#*mode == 0, iclass 30, count 0 2006.285.06:55:07.71#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.06:55:07.71#ibcon#[25=BW32\r\n] 2006.285.06:55:07.71#ibcon#*before write, iclass 30, count 0 2006.285.06:55:07.71#ibcon#enter sib2, iclass 30, count 0 2006.285.06:55:07.71#ibcon#flushed, iclass 30, count 0 2006.285.06:55:07.71#ibcon#about to write, iclass 30, count 0 2006.285.06:55:07.71#ibcon#wrote, iclass 30, count 0 2006.285.06:55:07.71#ibcon#about to read 3, iclass 30, count 0 2006.285.06:55:07.74#ibcon#read 3, iclass 30, count 0 2006.285.06:55:07.74#ibcon#about to read 4, iclass 30, count 0 2006.285.06:55:07.74#ibcon#read 4, iclass 30, count 0 2006.285.06:55:07.74#ibcon#about to read 5, iclass 30, count 0 2006.285.06:55:07.74#ibcon#read 5, iclass 30, count 0 2006.285.06:55:07.74#ibcon#about to read 6, iclass 30, count 0 2006.285.06:55:07.74#ibcon#read 6, iclass 30, count 0 2006.285.06:55:07.74#ibcon#end of sib2, iclass 30, count 0 2006.285.06:55:07.74#ibcon#*after write, iclass 30, count 0 2006.285.06:55:07.74#ibcon#*before return 0, iclass 30, count 0 2006.285.06:55:07.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:55:07.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.06:55:07.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.06:55:07.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.06:55:07.74$vck44/vbbw=wide 2006.285.06:55:07.74#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.06:55:07.74#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.06:55:07.74#ibcon#ireg 8 cls_cnt 0 2006.285.06:55:07.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:55:07.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:55:07.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:55:07.81#ibcon#enter wrdev, iclass 32, count 0 2006.285.06:55:07.81#ibcon#first serial, iclass 32, count 0 2006.285.06:55:07.81#ibcon#enter sib2, iclass 32, count 0 2006.285.06:55:07.81#ibcon#flushed, iclass 32, count 0 2006.285.06:55:07.81#ibcon#about to write, iclass 32, count 0 2006.285.06:55:07.81#ibcon#wrote, iclass 32, count 0 2006.285.06:55:07.81#ibcon#about to read 3, iclass 32, count 0 2006.285.06:55:07.83#ibcon#read 3, iclass 32, count 0 2006.285.06:55:07.83#ibcon#about to read 4, iclass 32, count 0 2006.285.06:55:07.83#ibcon#read 4, iclass 32, count 0 2006.285.06:55:07.83#ibcon#about to read 5, iclass 32, count 0 2006.285.06:55:07.83#ibcon#read 5, iclass 32, count 0 2006.285.06:55:07.83#ibcon#about to read 6, iclass 32, count 0 2006.285.06:55:07.83#ibcon#read 6, iclass 32, count 0 2006.285.06:55:07.83#ibcon#end of sib2, iclass 32, count 0 2006.285.06:55:07.83#ibcon#*mode == 0, iclass 32, count 0 2006.285.06:55:07.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.06:55:07.83#ibcon#[27=BW32\r\n] 2006.285.06:55:07.83#ibcon#*before write, iclass 32, count 0 2006.285.06:55:07.83#ibcon#enter sib2, iclass 32, count 0 2006.285.06:55:07.83#ibcon#flushed, iclass 32, count 0 2006.285.06:55:07.83#ibcon#about to write, iclass 32, count 0 2006.285.06:55:07.83#ibcon#wrote, iclass 32, count 0 2006.285.06:55:07.83#ibcon#about to read 3, iclass 32, count 0 2006.285.06:55:07.86#ibcon#read 3, iclass 32, count 0 2006.285.06:55:07.86#ibcon#about to read 4, iclass 32, count 0 2006.285.06:55:07.86#ibcon#read 4, iclass 32, count 0 2006.285.06:55:07.86#ibcon#about to read 5, iclass 32, count 0 2006.285.06:55:07.86#ibcon#read 5, iclass 32, count 0 2006.285.06:55:07.86#ibcon#about to read 6, iclass 32, count 0 2006.285.06:55:07.86#ibcon#read 6, iclass 32, count 0 2006.285.06:55:07.86#ibcon#end of sib2, iclass 32, count 0 2006.285.06:55:07.86#ibcon#*after write, iclass 32, count 0 2006.285.06:55:07.86#ibcon#*before return 0, iclass 32, count 0 2006.285.06:55:07.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:55:07.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.06:55:07.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.06:55:07.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.06:55:07.86$setupk4/ifdk4 2006.285.06:55:07.86$ifdk4/lo= 2006.285.06:55:07.86$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.06:55:07.86$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.06:55:07.86$ifdk4/patch= 2006.285.06:55:07.86$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.06:55:07.86$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.06:55:07.86$setupk4/!*+20s 2006.285.06:55:12.14#trakl#Source acquired 2006.285.06:55:13.14#flagr#flagr/antenna,acquired 2006.285.06:55:14.29#abcon#<5=/05 4.2 7.5 24.43 721014.2\r\n> 2006.285.06:55:14.31#abcon#{5=INTERFACE CLEAR} 2006.285.06:55:14.37#abcon#[5=S1D000X0/0*\r\n] 2006.285.06:55:22.36$setupk4/"tpicd 2006.285.06:55:22.36$setupk4/echo=off 2006.285.06:55:22.36$setupk4/xlog=off 2006.285.06:55:22.36:!2006.285.07:02:08 2006.285.07:02:08.02:preob 2006.285.07:02:09.15/onsource/TRACKING 2006.285.07:02:09.15:!2006.285.07:02:18 2006.285.07:02:18.02:"tape 2006.285.07:02:18.02:"st=record 2006.285.07:02:18.02:data_valid=on 2006.285.07:02:18.02:midob 2006.285.07:02:19.15/onsource/TRACKING 2006.285.07:02:19.15/wx/24.29,1014.2,74 2006.285.07:02:19.27/cable/+6.4719E-03 2006.285.07:02:20.36/va/01,07,usb,yes,32,35 2006.285.07:02:20.36/va/02,06,usb,yes,33,33 2006.285.07:02:20.36/va/03,07,usb,yes,32,34 2006.285.07:02:20.36/va/04,06,usb,yes,33,35 2006.285.07:02:20.36/va/05,03,usb,yes,33,33 2006.285.07:02:20.36/va/06,04,usb,yes,30,29 2006.285.07:02:20.36/va/07,04,usb,yes,30,31 2006.285.07:02:20.36/va/08,03,usb,yes,31,38 2006.285.07:02:20.59/valo/01,524.99,yes,locked 2006.285.07:02:20.59/valo/02,534.99,yes,locked 2006.285.07:02:20.59/valo/03,564.99,yes,locked 2006.285.07:02:20.59/valo/04,624.99,yes,locked 2006.285.07:02:20.59/valo/05,734.99,yes,locked 2006.285.07:02:20.59/valo/06,814.99,yes,locked 2006.285.07:02:20.59/valo/07,864.99,yes,locked 2006.285.07:02:20.59/valo/08,884.99,yes,locked 2006.285.07:02:21.68/vb/01,04,usb,yes,31,29 2006.285.07:02:21.68/vb/02,05,usb,yes,29,29 2006.285.07:02:21.68/vb/03,04,usb,yes,30,33 2006.285.07:02:21.68/vb/04,05,usb,yes,30,29 2006.285.07:02:21.68/vb/05,04,usb,yes,27,29 2006.285.07:02:21.68/vb/06,03,usb,yes,39,34 2006.285.07:02:21.68/vb/07,04,usb,yes,31,31 2006.285.07:02:21.68/vb/08,04,usb,yes,28,32 2006.285.07:02:21.91/vblo/01,629.99,yes,locked 2006.285.07:02:21.91/vblo/02,634.99,yes,locked 2006.285.07:02:21.91/vblo/03,649.99,yes,locked 2006.285.07:02:21.91/vblo/04,679.99,yes,locked 2006.285.07:02:21.91/vblo/05,709.99,yes,locked 2006.285.07:02:21.91/vblo/06,719.99,yes,locked 2006.285.07:02:21.91/vblo/07,734.99,yes,locked 2006.285.07:02:21.91/vblo/08,744.99,yes,locked 2006.285.07:02:22.06/vabw/8 2006.285.07:02:22.21/vbbw/8 2006.285.07:02:22.30/xfe/off,on,12.2 2006.285.07:02:22.69/ifatt/23,28,28,28 2006.285.07:02:23.07/fmout-gps/S +2.69E-07 2006.285.07:02:23.09:!2006.285.07:03:38 2006.285.07:03:38.00:data_valid=off 2006.285.07:03:38.01:"et 2006.285.07:03:38.01:!+3s 2006.285.07:03:41.03:"tape 2006.285.07:03:41.03:postob 2006.285.07:03:41.15/cable/+6.4714E-03 2006.285.07:03:41.16/wx/24.27,1014.2,74 2006.285.07:03:41.21/fmout-gps/S +2.68E-07 2006.285.07:03:41.21:scan_name=285-0705,jd0610,130 2006.285.07:03:41.22:source=0059+581,010245.76,582411.1,2000.0,cw 2006.285.07:03:43.14#flagr#flagr/antenna,new-source 2006.285.07:03:43.15:checkk5 2006.285.07:03:43.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:03:43.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:03:44.33/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:03:44.68/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:03:45.07/chk_obsdata//k5ts1/T2850702??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.07:03:45.39/chk_obsdata//k5ts2/T2850702??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.07:03:45.73/chk_obsdata//k5ts3/T2850702??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.07:03:46.31/chk_obsdata//k5ts4/T2850702??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.07:03:47.02/k5log//k5ts1_log_newline 2006.285.07:03:47.94/k5log//k5ts2_log_newline 2006.285.07:03:48.70/k5log//k5ts3_log_newline 2006.285.07:03:49.46/k5log//k5ts4_log_newline 2006.285.07:03:49.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:03:49.48:setupk4=1 2006.285.07:03:49.48$setupk4/echo=on 2006.285.07:03:49.48$setupk4/pcalon 2006.285.07:03:49.48$pcalon/"no phase cal control is implemented here 2006.285.07:03:49.48$setupk4/"tpicd=stop 2006.285.07:03:49.48$setupk4/"rec=synch_on 2006.285.07:03:49.48$setupk4/"rec_mode=128 2006.285.07:03:49.48$setupk4/!* 2006.285.07:03:49.48$setupk4/recpk4 2006.285.07:03:49.48$recpk4/recpatch= 2006.285.07:03:49.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:03:49.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:03:49.48$setupk4/vck44 2006.285.07:03:49.48$vck44/valo=1,524.99 2006.285.07:03:49.48#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.07:03:49.48#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.07:03:49.48#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:49.48#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:03:49.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:03:49.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:03:49.48#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:03:49.48#ibcon#first serial, iclass 25, count 0 2006.285.07:03:49.48#ibcon#enter sib2, iclass 25, count 0 2006.285.07:03:49.48#ibcon#flushed, iclass 25, count 0 2006.285.07:03:49.48#ibcon#about to write, iclass 25, count 0 2006.285.07:03:49.48#ibcon#wrote, iclass 25, count 0 2006.285.07:03:49.48#ibcon#about to read 3, iclass 25, count 0 2006.285.07:03:49.49#ibcon#read 3, iclass 25, count 0 2006.285.07:03:49.49#ibcon#about to read 4, iclass 25, count 0 2006.285.07:03:49.49#ibcon#read 4, iclass 25, count 0 2006.285.07:03:49.49#ibcon#about to read 5, iclass 25, count 0 2006.285.07:03:49.49#ibcon#read 5, iclass 25, count 0 2006.285.07:03:49.49#ibcon#about to read 6, iclass 25, count 0 2006.285.07:03:49.49#ibcon#read 6, iclass 25, count 0 2006.285.07:03:49.49#ibcon#end of sib2, iclass 25, count 0 2006.285.07:03:49.49#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:03:49.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:03:49.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:03:49.49#ibcon#*before write, iclass 25, count 0 2006.285.07:03:49.49#ibcon#enter sib2, iclass 25, count 0 2006.285.07:03:49.49#ibcon#flushed, iclass 25, count 0 2006.285.07:03:49.49#ibcon#about to write, iclass 25, count 0 2006.285.07:03:49.49#ibcon#wrote, iclass 25, count 0 2006.285.07:03:49.49#ibcon#about to read 3, iclass 25, count 0 2006.285.07:03:49.54#ibcon#read 3, iclass 25, count 0 2006.285.07:03:49.54#ibcon#about to read 4, iclass 25, count 0 2006.285.07:03:49.54#ibcon#read 4, iclass 25, count 0 2006.285.07:03:49.54#ibcon#about to read 5, iclass 25, count 0 2006.285.07:03:49.54#ibcon#read 5, iclass 25, count 0 2006.285.07:03:49.54#ibcon#about to read 6, iclass 25, count 0 2006.285.07:03:49.54#ibcon#read 6, iclass 25, count 0 2006.285.07:03:49.54#ibcon#end of sib2, iclass 25, count 0 2006.285.07:03:49.54#ibcon#*after write, iclass 25, count 0 2006.285.07:03:49.54#ibcon#*before return 0, iclass 25, count 0 2006.285.07:03:49.54#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:03:49.54#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:03:49.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:03:49.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:03:49.54$vck44/va=1,7 2006.285.07:03:49.54#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.07:03:49.54#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.07:03:49.54#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:49.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:03:49.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:03:49.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:03:49.54#ibcon#enter wrdev, iclass 27, count 2 2006.285.07:03:49.54#ibcon#first serial, iclass 27, count 2 2006.285.07:03:49.54#ibcon#enter sib2, iclass 27, count 2 2006.285.07:03:49.54#ibcon#flushed, iclass 27, count 2 2006.285.07:03:49.55#ibcon#about to write, iclass 27, count 2 2006.285.07:03:49.55#ibcon#wrote, iclass 27, count 2 2006.285.07:03:49.55#ibcon#about to read 3, iclass 27, count 2 2006.285.07:03:49.56#ibcon#read 3, iclass 27, count 2 2006.285.07:03:49.56#ibcon#about to read 4, iclass 27, count 2 2006.285.07:03:49.56#ibcon#read 4, iclass 27, count 2 2006.285.07:03:49.56#ibcon#about to read 5, iclass 27, count 2 2006.285.07:03:49.56#ibcon#read 5, iclass 27, count 2 2006.285.07:03:49.56#ibcon#about to read 6, iclass 27, count 2 2006.285.07:03:49.56#ibcon#read 6, iclass 27, count 2 2006.285.07:03:49.56#ibcon#end of sib2, iclass 27, count 2 2006.285.07:03:49.56#ibcon#*mode == 0, iclass 27, count 2 2006.285.07:03:49.56#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.07:03:49.56#ibcon#[25=AT01-07\r\n] 2006.285.07:03:49.56#ibcon#*before write, iclass 27, count 2 2006.285.07:03:49.56#ibcon#enter sib2, iclass 27, count 2 2006.285.07:03:49.56#ibcon#flushed, iclass 27, count 2 2006.285.07:03:49.56#ibcon#about to write, iclass 27, count 2 2006.285.07:03:49.56#ibcon#wrote, iclass 27, count 2 2006.285.07:03:49.56#ibcon#about to read 3, iclass 27, count 2 2006.285.07:03:49.59#ibcon#read 3, iclass 27, count 2 2006.285.07:03:49.59#ibcon#about to read 4, iclass 27, count 2 2006.285.07:03:49.59#ibcon#read 4, iclass 27, count 2 2006.285.07:03:49.59#ibcon#about to read 5, iclass 27, count 2 2006.285.07:03:49.59#ibcon#read 5, iclass 27, count 2 2006.285.07:03:49.59#ibcon#about to read 6, iclass 27, count 2 2006.285.07:03:49.59#ibcon#read 6, iclass 27, count 2 2006.285.07:03:49.59#ibcon#end of sib2, iclass 27, count 2 2006.285.07:03:49.59#ibcon#*after write, iclass 27, count 2 2006.285.07:03:49.59#ibcon#*before return 0, iclass 27, count 2 2006.285.07:03:49.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:03:49.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:03:49.59#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.07:03:49.59#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:49.59#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:03:49.71#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:03:49.71#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:03:49.71#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:03:49.71#ibcon#first serial, iclass 27, count 0 2006.285.07:03:49.71#ibcon#enter sib2, iclass 27, count 0 2006.285.07:03:49.71#ibcon#flushed, iclass 27, count 0 2006.285.07:03:49.71#ibcon#about to write, iclass 27, count 0 2006.285.07:03:49.71#ibcon#wrote, iclass 27, count 0 2006.285.07:03:49.71#ibcon#about to read 3, iclass 27, count 0 2006.285.07:03:49.73#ibcon#read 3, iclass 27, count 0 2006.285.07:03:49.73#ibcon#about to read 4, iclass 27, count 0 2006.285.07:03:49.73#ibcon#read 4, iclass 27, count 0 2006.285.07:03:49.73#ibcon#about to read 5, iclass 27, count 0 2006.285.07:03:49.73#ibcon#read 5, iclass 27, count 0 2006.285.07:03:49.73#ibcon#about to read 6, iclass 27, count 0 2006.285.07:03:49.73#ibcon#read 6, iclass 27, count 0 2006.285.07:03:49.73#ibcon#end of sib2, iclass 27, count 0 2006.285.07:03:49.73#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:03:49.73#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:03:49.73#ibcon#[25=USB\r\n] 2006.285.07:03:49.73#ibcon#*before write, iclass 27, count 0 2006.285.07:03:49.73#ibcon#enter sib2, iclass 27, count 0 2006.285.07:03:49.73#ibcon#flushed, iclass 27, count 0 2006.285.07:03:49.73#ibcon#about to write, iclass 27, count 0 2006.285.07:03:49.73#ibcon#wrote, iclass 27, count 0 2006.285.07:03:49.73#ibcon#about to read 3, iclass 27, count 0 2006.285.07:03:49.76#ibcon#read 3, iclass 27, count 0 2006.285.07:03:49.76#ibcon#about to read 4, iclass 27, count 0 2006.285.07:03:49.76#ibcon#read 4, iclass 27, count 0 2006.285.07:03:49.76#ibcon#about to read 5, iclass 27, count 0 2006.285.07:03:49.76#ibcon#read 5, iclass 27, count 0 2006.285.07:03:49.76#ibcon#about to read 6, iclass 27, count 0 2006.285.07:03:49.76#ibcon#read 6, iclass 27, count 0 2006.285.07:03:49.76#ibcon#end of sib2, iclass 27, count 0 2006.285.07:03:49.76#ibcon#*after write, iclass 27, count 0 2006.285.07:03:49.76#ibcon#*before return 0, iclass 27, count 0 2006.285.07:03:49.76#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:03:49.76#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:03:49.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:03:49.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:03:49.76$vck44/valo=2,534.99 2006.285.07:03:49.76#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.07:03:49.76#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.07:03:49.76#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:49.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:03:49.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:03:49.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:03:49.76#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:03:49.76#ibcon#first serial, iclass 29, count 0 2006.285.07:03:49.76#ibcon#enter sib2, iclass 29, count 0 2006.285.07:03:49.76#ibcon#flushed, iclass 29, count 0 2006.285.07:03:49.77#ibcon#about to write, iclass 29, count 0 2006.285.07:03:49.77#ibcon#wrote, iclass 29, count 0 2006.285.07:03:49.77#ibcon#about to read 3, iclass 29, count 0 2006.285.07:03:49.78#ibcon#read 3, iclass 29, count 0 2006.285.07:03:49.78#ibcon#about to read 4, iclass 29, count 0 2006.285.07:03:49.78#ibcon#read 4, iclass 29, count 0 2006.285.07:03:49.78#ibcon#about to read 5, iclass 29, count 0 2006.285.07:03:49.78#ibcon#read 5, iclass 29, count 0 2006.285.07:03:49.78#ibcon#about to read 6, iclass 29, count 0 2006.285.07:03:49.78#ibcon#read 6, iclass 29, count 0 2006.285.07:03:49.78#ibcon#end of sib2, iclass 29, count 0 2006.285.07:03:49.78#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:03:49.78#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:03:49.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:03:49.78#ibcon#*before write, iclass 29, count 0 2006.285.07:03:49.78#ibcon#enter sib2, iclass 29, count 0 2006.285.07:03:49.78#ibcon#flushed, iclass 29, count 0 2006.285.07:03:49.78#ibcon#about to write, iclass 29, count 0 2006.285.07:03:49.78#ibcon#wrote, iclass 29, count 0 2006.285.07:03:49.78#ibcon#about to read 3, iclass 29, count 0 2006.285.07:03:49.82#ibcon#read 3, iclass 29, count 0 2006.285.07:03:49.82#ibcon#about to read 4, iclass 29, count 0 2006.285.07:03:49.82#ibcon#read 4, iclass 29, count 0 2006.285.07:03:49.82#ibcon#about to read 5, iclass 29, count 0 2006.285.07:03:49.82#ibcon#read 5, iclass 29, count 0 2006.285.07:03:49.82#ibcon#about to read 6, iclass 29, count 0 2006.285.07:03:49.82#ibcon#read 6, iclass 29, count 0 2006.285.07:03:49.82#ibcon#end of sib2, iclass 29, count 0 2006.285.07:03:49.82#ibcon#*after write, iclass 29, count 0 2006.285.07:03:49.82#ibcon#*before return 0, iclass 29, count 0 2006.285.07:03:49.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:03:49.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:03:49.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:03:49.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:03:49.82$vck44/va=2,6 2006.285.07:03:49.82#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.07:03:49.82#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.07:03:49.82#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:49.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:03:49.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:03:49.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:03:49.88#ibcon#enter wrdev, iclass 31, count 2 2006.285.07:03:49.88#ibcon#first serial, iclass 31, count 2 2006.285.07:03:49.88#ibcon#enter sib2, iclass 31, count 2 2006.285.07:03:49.88#ibcon#flushed, iclass 31, count 2 2006.285.07:03:49.88#ibcon#about to write, iclass 31, count 2 2006.285.07:03:49.88#ibcon#wrote, iclass 31, count 2 2006.285.07:03:49.88#ibcon#about to read 3, iclass 31, count 2 2006.285.07:03:49.90#ibcon#read 3, iclass 31, count 2 2006.285.07:03:49.90#ibcon#about to read 4, iclass 31, count 2 2006.285.07:03:49.90#ibcon#read 4, iclass 31, count 2 2006.285.07:03:49.90#ibcon#about to read 5, iclass 31, count 2 2006.285.07:03:49.90#ibcon#read 5, iclass 31, count 2 2006.285.07:03:49.90#ibcon#about to read 6, iclass 31, count 2 2006.285.07:03:49.90#ibcon#read 6, iclass 31, count 2 2006.285.07:03:49.90#ibcon#end of sib2, iclass 31, count 2 2006.285.07:03:49.90#ibcon#*mode == 0, iclass 31, count 2 2006.285.07:03:49.90#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.07:03:49.90#ibcon#[25=AT02-06\r\n] 2006.285.07:03:49.90#ibcon#*before write, iclass 31, count 2 2006.285.07:03:49.90#ibcon#enter sib2, iclass 31, count 2 2006.285.07:03:49.90#ibcon#flushed, iclass 31, count 2 2006.285.07:03:49.90#ibcon#about to write, iclass 31, count 2 2006.285.07:03:49.90#ibcon#wrote, iclass 31, count 2 2006.285.07:03:49.90#ibcon#about to read 3, iclass 31, count 2 2006.285.07:03:49.93#ibcon#read 3, iclass 31, count 2 2006.285.07:03:49.93#ibcon#about to read 4, iclass 31, count 2 2006.285.07:03:49.93#ibcon#read 4, iclass 31, count 2 2006.285.07:03:49.93#ibcon#about to read 5, iclass 31, count 2 2006.285.07:03:49.93#ibcon#read 5, iclass 31, count 2 2006.285.07:03:49.93#ibcon#about to read 6, iclass 31, count 2 2006.285.07:03:49.93#ibcon#read 6, iclass 31, count 2 2006.285.07:03:49.93#ibcon#end of sib2, iclass 31, count 2 2006.285.07:03:49.93#ibcon#*after write, iclass 31, count 2 2006.285.07:03:49.93#ibcon#*before return 0, iclass 31, count 2 2006.285.07:03:49.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:03:49.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:03:49.93#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.07:03:49.93#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:49.93#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:03:50.05#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:03:50.05#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:03:50.05#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:03:50.05#ibcon#first serial, iclass 31, count 0 2006.285.07:03:50.05#ibcon#enter sib2, iclass 31, count 0 2006.285.07:03:50.05#ibcon#flushed, iclass 31, count 0 2006.285.07:03:50.05#ibcon#about to write, iclass 31, count 0 2006.285.07:03:50.05#ibcon#wrote, iclass 31, count 0 2006.285.07:03:50.05#ibcon#about to read 3, iclass 31, count 0 2006.285.07:03:50.07#ibcon#read 3, iclass 31, count 0 2006.285.07:03:50.07#ibcon#about to read 4, iclass 31, count 0 2006.285.07:03:50.07#ibcon#read 4, iclass 31, count 0 2006.285.07:03:50.07#ibcon#about to read 5, iclass 31, count 0 2006.285.07:03:50.07#ibcon#read 5, iclass 31, count 0 2006.285.07:03:50.07#ibcon#about to read 6, iclass 31, count 0 2006.285.07:03:50.07#ibcon#read 6, iclass 31, count 0 2006.285.07:03:50.07#ibcon#end of sib2, iclass 31, count 0 2006.285.07:03:50.07#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:03:50.07#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:03:50.07#ibcon#[25=USB\r\n] 2006.285.07:03:50.07#ibcon#*before write, iclass 31, count 0 2006.285.07:03:50.07#ibcon#enter sib2, iclass 31, count 0 2006.285.07:03:50.07#ibcon#flushed, iclass 31, count 0 2006.285.07:03:50.07#ibcon#about to write, iclass 31, count 0 2006.285.07:03:50.07#ibcon#wrote, iclass 31, count 0 2006.285.07:03:50.07#ibcon#about to read 3, iclass 31, count 0 2006.285.07:03:50.10#ibcon#read 3, iclass 31, count 0 2006.285.07:03:50.10#ibcon#about to read 4, iclass 31, count 0 2006.285.07:03:50.10#ibcon#read 4, iclass 31, count 0 2006.285.07:03:50.10#ibcon#about to read 5, iclass 31, count 0 2006.285.07:03:50.10#ibcon#read 5, iclass 31, count 0 2006.285.07:03:50.10#ibcon#about to read 6, iclass 31, count 0 2006.285.07:03:50.10#ibcon#read 6, iclass 31, count 0 2006.285.07:03:50.10#ibcon#end of sib2, iclass 31, count 0 2006.285.07:03:50.10#ibcon#*after write, iclass 31, count 0 2006.285.07:03:50.10#ibcon#*before return 0, iclass 31, count 0 2006.285.07:03:50.10#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:03:50.10#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:03:50.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:03:50.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:03:50.10$vck44/valo=3,564.99 2006.285.07:03:50.10#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.07:03:50.10#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.07:03:50.10#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:50.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:03:50.10#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:03:50.10#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:03:50.10#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:03:50.11#ibcon#first serial, iclass 33, count 0 2006.285.07:03:50.11#ibcon#enter sib2, iclass 33, count 0 2006.285.07:03:50.11#ibcon#flushed, iclass 33, count 0 2006.285.07:03:50.11#ibcon#about to write, iclass 33, count 0 2006.285.07:03:50.11#ibcon#wrote, iclass 33, count 0 2006.285.07:03:50.11#ibcon#about to read 3, iclass 33, count 0 2006.285.07:03:50.12#ibcon#read 3, iclass 33, count 0 2006.285.07:03:50.12#ibcon#about to read 4, iclass 33, count 0 2006.285.07:03:50.12#ibcon#read 4, iclass 33, count 0 2006.285.07:03:50.12#ibcon#about to read 5, iclass 33, count 0 2006.285.07:03:50.12#ibcon#read 5, iclass 33, count 0 2006.285.07:03:50.12#ibcon#about to read 6, iclass 33, count 0 2006.285.07:03:50.12#ibcon#read 6, iclass 33, count 0 2006.285.07:03:50.12#ibcon#end of sib2, iclass 33, count 0 2006.285.07:03:50.12#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:03:50.12#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:03:50.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:03:50.12#ibcon#*before write, iclass 33, count 0 2006.285.07:03:50.12#ibcon#enter sib2, iclass 33, count 0 2006.285.07:03:50.12#ibcon#flushed, iclass 33, count 0 2006.285.07:03:50.12#ibcon#about to write, iclass 33, count 0 2006.285.07:03:50.12#ibcon#wrote, iclass 33, count 0 2006.285.07:03:50.12#ibcon#about to read 3, iclass 33, count 0 2006.285.07:03:50.16#ibcon#read 3, iclass 33, count 0 2006.285.07:03:50.16#ibcon#about to read 4, iclass 33, count 0 2006.285.07:03:50.16#ibcon#read 4, iclass 33, count 0 2006.285.07:03:50.16#ibcon#about to read 5, iclass 33, count 0 2006.285.07:03:50.16#ibcon#read 5, iclass 33, count 0 2006.285.07:03:50.16#ibcon#about to read 6, iclass 33, count 0 2006.285.07:03:50.16#ibcon#read 6, iclass 33, count 0 2006.285.07:03:50.16#ibcon#end of sib2, iclass 33, count 0 2006.285.07:03:50.16#ibcon#*after write, iclass 33, count 0 2006.285.07:03:50.16#ibcon#*before return 0, iclass 33, count 0 2006.285.07:03:50.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:03:50.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:03:50.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:03:50.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:03:50.16$vck44/va=3,7 2006.285.07:03:50.16#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.07:03:50.16#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.07:03:50.16#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:50.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:03:50.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:03:50.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:03:50.22#ibcon#enter wrdev, iclass 35, count 2 2006.285.07:03:50.22#ibcon#first serial, iclass 35, count 2 2006.285.07:03:50.22#ibcon#enter sib2, iclass 35, count 2 2006.285.07:03:50.22#ibcon#flushed, iclass 35, count 2 2006.285.07:03:50.22#ibcon#about to write, iclass 35, count 2 2006.285.07:03:50.22#ibcon#wrote, iclass 35, count 2 2006.285.07:03:50.22#ibcon#about to read 3, iclass 35, count 2 2006.285.07:03:50.24#ibcon#read 3, iclass 35, count 2 2006.285.07:03:50.24#ibcon#about to read 4, iclass 35, count 2 2006.285.07:03:50.24#ibcon#read 4, iclass 35, count 2 2006.285.07:03:50.24#ibcon#about to read 5, iclass 35, count 2 2006.285.07:03:50.24#ibcon#read 5, iclass 35, count 2 2006.285.07:03:50.24#ibcon#about to read 6, iclass 35, count 2 2006.285.07:03:50.24#ibcon#read 6, iclass 35, count 2 2006.285.07:03:50.24#ibcon#end of sib2, iclass 35, count 2 2006.285.07:03:50.24#ibcon#*mode == 0, iclass 35, count 2 2006.285.07:03:50.24#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.07:03:50.24#ibcon#[25=AT03-07\r\n] 2006.285.07:03:50.24#ibcon#*before write, iclass 35, count 2 2006.285.07:03:50.24#ibcon#enter sib2, iclass 35, count 2 2006.285.07:03:50.24#ibcon#flushed, iclass 35, count 2 2006.285.07:03:50.24#ibcon#about to write, iclass 35, count 2 2006.285.07:03:50.24#ibcon#wrote, iclass 35, count 2 2006.285.07:03:50.24#ibcon#about to read 3, iclass 35, count 2 2006.285.07:03:50.27#ibcon#read 3, iclass 35, count 2 2006.285.07:03:50.27#ibcon#about to read 4, iclass 35, count 2 2006.285.07:03:50.27#ibcon#read 4, iclass 35, count 2 2006.285.07:03:50.27#ibcon#about to read 5, iclass 35, count 2 2006.285.07:03:50.27#ibcon#read 5, iclass 35, count 2 2006.285.07:03:50.27#ibcon#about to read 6, iclass 35, count 2 2006.285.07:03:50.27#ibcon#read 6, iclass 35, count 2 2006.285.07:03:50.27#ibcon#end of sib2, iclass 35, count 2 2006.285.07:03:50.27#ibcon#*after write, iclass 35, count 2 2006.285.07:03:50.27#ibcon#*before return 0, iclass 35, count 2 2006.285.07:03:50.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:03:50.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:03:50.27#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.07:03:50.27#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:50.27#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:03:50.39#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:03:50.39#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:03:50.39#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:03:50.39#ibcon#first serial, iclass 35, count 0 2006.285.07:03:50.39#ibcon#enter sib2, iclass 35, count 0 2006.285.07:03:50.39#ibcon#flushed, iclass 35, count 0 2006.285.07:03:50.39#ibcon#about to write, iclass 35, count 0 2006.285.07:03:50.39#ibcon#wrote, iclass 35, count 0 2006.285.07:03:50.39#ibcon#about to read 3, iclass 35, count 0 2006.285.07:03:50.41#ibcon#read 3, iclass 35, count 0 2006.285.07:03:50.41#ibcon#about to read 4, iclass 35, count 0 2006.285.07:03:50.41#ibcon#read 4, iclass 35, count 0 2006.285.07:03:50.41#ibcon#about to read 5, iclass 35, count 0 2006.285.07:03:50.41#ibcon#read 5, iclass 35, count 0 2006.285.07:03:50.41#ibcon#about to read 6, iclass 35, count 0 2006.285.07:03:50.41#ibcon#read 6, iclass 35, count 0 2006.285.07:03:50.41#ibcon#end of sib2, iclass 35, count 0 2006.285.07:03:50.41#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:03:50.41#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:03:50.41#ibcon#[25=USB\r\n] 2006.285.07:03:50.41#ibcon#*before write, iclass 35, count 0 2006.285.07:03:50.41#ibcon#enter sib2, iclass 35, count 0 2006.285.07:03:50.41#ibcon#flushed, iclass 35, count 0 2006.285.07:03:50.41#ibcon#about to write, iclass 35, count 0 2006.285.07:03:50.41#ibcon#wrote, iclass 35, count 0 2006.285.07:03:50.41#ibcon#about to read 3, iclass 35, count 0 2006.285.07:03:50.44#ibcon#read 3, iclass 35, count 0 2006.285.07:03:50.44#ibcon#about to read 4, iclass 35, count 0 2006.285.07:03:50.44#ibcon#read 4, iclass 35, count 0 2006.285.07:03:50.44#ibcon#about to read 5, iclass 35, count 0 2006.285.07:03:50.44#ibcon#read 5, iclass 35, count 0 2006.285.07:03:50.44#ibcon#about to read 6, iclass 35, count 0 2006.285.07:03:50.44#ibcon#read 6, iclass 35, count 0 2006.285.07:03:50.44#ibcon#end of sib2, iclass 35, count 0 2006.285.07:03:50.44#ibcon#*after write, iclass 35, count 0 2006.285.07:03:50.44#ibcon#*before return 0, iclass 35, count 0 2006.285.07:03:50.44#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:03:50.44#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:03:50.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:03:50.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:03:50.44$vck44/valo=4,624.99 2006.285.07:03:50.44#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.07:03:50.44#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.07:03:50.44#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:50.44#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:03:50.44#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:03:50.44#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:03:50.44#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:03:50.44#ibcon#first serial, iclass 37, count 0 2006.285.07:03:50.44#ibcon#enter sib2, iclass 37, count 0 2006.285.07:03:50.44#ibcon#flushed, iclass 37, count 0 2006.285.07:03:50.45#ibcon#about to write, iclass 37, count 0 2006.285.07:03:50.45#ibcon#wrote, iclass 37, count 0 2006.285.07:03:50.45#ibcon#about to read 3, iclass 37, count 0 2006.285.07:03:50.46#ibcon#read 3, iclass 37, count 0 2006.285.07:03:50.46#ibcon#about to read 4, iclass 37, count 0 2006.285.07:03:50.46#ibcon#read 4, iclass 37, count 0 2006.285.07:03:50.46#ibcon#about to read 5, iclass 37, count 0 2006.285.07:03:50.46#ibcon#read 5, iclass 37, count 0 2006.285.07:03:50.46#ibcon#about to read 6, iclass 37, count 0 2006.285.07:03:50.46#ibcon#read 6, iclass 37, count 0 2006.285.07:03:50.46#ibcon#end of sib2, iclass 37, count 0 2006.285.07:03:50.46#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:03:50.46#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:03:50.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:03:50.46#ibcon#*before write, iclass 37, count 0 2006.285.07:03:50.46#ibcon#enter sib2, iclass 37, count 0 2006.285.07:03:50.46#ibcon#flushed, iclass 37, count 0 2006.285.07:03:50.46#ibcon#about to write, iclass 37, count 0 2006.285.07:03:50.46#ibcon#wrote, iclass 37, count 0 2006.285.07:03:50.46#ibcon#about to read 3, iclass 37, count 0 2006.285.07:03:50.50#ibcon#read 3, iclass 37, count 0 2006.285.07:03:50.50#ibcon#about to read 4, iclass 37, count 0 2006.285.07:03:50.50#ibcon#read 4, iclass 37, count 0 2006.285.07:03:50.50#ibcon#about to read 5, iclass 37, count 0 2006.285.07:03:50.50#ibcon#read 5, iclass 37, count 0 2006.285.07:03:50.50#ibcon#about to read 6, iclass 37, count 0 2006.285.07:03:50.50#ibcon#read 6, iclass 37, count 0 2006.285.07:03:50.50#ibcon#end of sib2, iclass 37, count 0 2006.285.07:03:50.50#ibcon#*after write, iclass 37, count 0 2006.285.07:03:50.50#ibcon#*before return 0, iclass 37, count 0 2006.285.07:03:50.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:03:50.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:03:50.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:03:50.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:03:50.50$vck44/va=4,6 2006.285.07:03:50.50#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.07:03:50.50#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.07:03:50.50#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:50.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:03:50.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:03:50.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:03:50.56#ibcon#enter wrdev, iclass 39, count 2 2006.285.07:03:50.56#ibcon#first serial, iclass 39, count 2 2006.285.07:03:50.56#ibcon#enter sib2, iclass 39, count 2 2006.285.07:03:50.56#ibcon#flushed, iclass 39, count 2 2006.285.07:03:50.56#ibcon#about to write, iclass 39, count 2 2006.285.07:03:50.56#ibcon#wrote, iclass 39, count 2 2006.285.07:03:50.56#ibcon#about to read 3, iclass 39, count 2 2006.285.07:03:50.58#ibcon#read 3, iclass 39, count 2 2006.285.07:03:50.58#ibcon#about to read 4, iclass 39, count 2 2006.285.07:03:50.58#ibcon#read 4, iclass 39, count 2 2006.285.07:03:50.58#ibcon#about to read 5, iclass 39, count 2 2006.285.07:03:50.58#ibcon#read 5, iclass 39, count 2 2006.285.07:03:50.58#ibcon#about to read 6, iclass 39, count 2 2006.285.07:03:50.58#ibcon#read 6, iclass 39, count 2 2006.285.07:03:50.58#ibcon#end of sib2, iclass 39, count 2 2006.285.07:03:50.58#ibcon#*mode == 0, iclass 39, count 2 2006.285.07:03:50.58#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.07:03:50.58#ibcon#[25=AT04-06\r\n] 2006.285.07:03:50.58#ibcon#*before write, iclass 39, count 2 2006.285.07:03:50.58#ibcon#enter sib2, iclass 39, count 2 2006.285.07:03:50.58#ibcon#flushed, iclass 39, count 2 2006.285.07:03:50.58#ibcon#about to write, iclass 39, count 2 2006.285.07:03:50.58#ibcon#wrote, iclass 39, count 2 2006.285.07:03:50.58#ibcon#about to read 3, iclass 39, count 2 2006.285.07:03:50.61#ibcon#read 3, iclass 39, count 2 2006.285.07:03:50.61#ibcon#about to read 4, iclass 39, count 2 2006.285.07:03:50.61#ibcon#read 4, iclass 39, count 2 2006.285.07:03:50.61#ibcon#about to read 5, iclass 39, count 2 2006.285.07:03:50.61#ibcon#read 5, iclass 39, count 2 2006.285.07:03:50.61#ibcon#about to read 6, iclass 39, count 2 2006.285.07:03:50.61#ibcon#read 6, iclass 39, count 2 2006.285.07:03:50.61#ibcon#end of sib2, iclass 39, count 2 2006.285.07:03:50.61#ibcon#*after write, iclass 39, count 2 2006.285.07:03:50.61#ibcon#*before return 0, iclass 39, count 2 2006.285.07:03:50.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:03:50.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:03:50.61#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.07:03:50.61#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:50.61#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:03:50.73#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:03:50.73#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:03:50.73#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:03:50.73#ibcon#first serial, iclass 39, count 0 2006.285.07:03:50.73#ibcon#enter sib2, iclass 39, count 0 2006.285.07:03:50.73#ibcon#flushed, iclass 39, count 0 2006.285.07:03:50.73#ibcon#about to write, iclass 39, count 0 2006.285.07:03:50.73#ibcon#wrote, iclass 39, count 0 2006.285.07:03:50.73#ibcon#about to read 3, iclass 39, count 0 2006.285.07:03:50.75#ibcon#read 3, iclass 39, count 0 2006.285.07:03:50.75#ibcon#about to read 4, iclass 39, count 0 2006.285.07:03:50.75#ibcon#read 4, iclass 39, count 0 2006.285.07:03:50.75#ibcon#about to read 5, iclass 39, count 0 2006.285.07:03:50.75#ibcon#read 5, iclass 39, count 0 2006.285.07:03:50.75#ibcon#about to read 6, iclass 39, count 0 2006.285.07:03:50.75#ibcon#read 6, iclass 39, count 0 2006.285.07:03:50.75#ibcon#end of sib2, iclass 39, count 0 2006.285.07:03:50.75#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:03:50.75#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:03:50.75#ibcon#[25=USB\r\n] 2006.285.07:03:50.75#ibcon#*before write, iclass 39, count 0 2006.285.07:03:50.75#ibcon#enter sib2, iclass 39, count 0 2006.285.07:03:50.75#ibcon#flushed, iclass 39, count 0 2006.285.07:03:50.75#ibcon#about to write, iclass 39, count 0 2006.285.07:03:50.75#ibcon#wrote, iclass 39, count 0 2006.285.07:03:50.75#ibcon#about to read 3, iclass 39, count 0 2006.285.07:03:50.78#ibcon#read 3, iclass 39, count 0 2006.285.07:03:50.78#ibcon#about to read 4, iclass 39, count 0 2006.285.07:03:50.78#ibcon#read 4, iclass 39, count 0 2006.285.07:03:50.78#ibcon#about to read 5, iclass 39, count 0 2006.285.07:03:50.78#ibcon#read 5, iclass 39, count 0 2006.285.07:03:50.78#ibcon#about to read 6, iclass 39, count 0 2006.285.07:03:50.78#ibcon#read 6, iclass 39, count 0 2006.285.07:03:50.78#ibcon#end of sib2, iclass 39, count 0 2006.285.07:03:50.78#ibcon#*after write, iclass 39, count 0 2006.285.07:03:50.78#ibcon#*before return 0, iclass 39, count 0 2006.285.07:03:50.78#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:03:50.78#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:03:50.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:03:50.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:03:50.78$vck44/valo=5,734.99 2006.285.07:03:50.78#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.07:03:50.78#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.07:03:50.78#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:50.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:03:50.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:03:50.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:03:50.78#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:03:50.78#ibcon#first serial, iclass 3, count 0 2006.285.07:03:50.78#ibcon#enter sib2, iclass 3, count 0 2006.285.07:03:50.78#ibcon#flushed, iclass 3, count 0 2006.285.07:03:50.79#ibcon#about to write, iclass 3, count 0 2006.285.07:03:50.79#ibcon#wrote, iclass 3, count 0 2006.285.07:03:50.79#ibcon#about to read 3, iclass 3, count 0 2006.285.07:03:50.80#ibcon#read 3, iclass 3, count 0 2006.285.07:03:50.80#ibcon#about to read 4, iclass 3, count 0 2006.285.07:03:50.80#ibcon#read 4, iclass 3, count 0 2006.285.07:03:50.80#ibcon#about to read 5, iclass 3, count 0 2006.285.07:03:50.80#ibcon#read 5, iclass 3, count 0 2006.285.07:03:50.80#ibcon#about to read 6, iclass 3, count 0 2006.285.07:03:50.80#ibcon#read 6, iclass 3, count 0 2006.285.07:03:50.80#ibcon#end of sib2, iclass 3, count 0 2006.285.07:03:50.80#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:03:50.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:03:50.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:03:50.80#ibcon#*before write, iclass 3, count 0 2006.285.07:03:50.80#ibcon#enter sib2, iclass 3, count 0 2006.285.07:03:50.80#ibcon#flushed, iclass 3, count 0 2006.285.07:03:50.80#ibcon#about to write, iclass 3, count 0 2006.285.07:03:50.80#ibcon#wrote, iclass 3, count 0 2006.285.07:03:50.80#ibcon#about to read 3, iclass 3, count 0 2006.285.07:03:50.84#ibcon#read 3, iclass 3, count 0 2006.285.07:03:50.84#ibcon#about to read 4, iclass 3, count 0 2006.285.07:03:50.84#ibcon#read 4, iclass 3, count 0 2006.285.07:03:50.84#ibcon#about to read 5, iclass 3, count 0 2006.285.07:03:50.84#ibcon#read 5, iclass 3, count 0 2006.285.07:03:50.84#ibcon#about to read 6, iclass 3, count 0 2006.285.07:03:50.84#ibcon#read 6, iclass 3, count 0 2006.285.07:03:50.84#ibcon#end of sib2, iclass 3, count 0 2006.285.07:03:50.84#ibcon#*after write, iclass 3, count 0 2006.285.07:03:50.84#ibcon#*before return 0, iclass 3, count 0 2006.285.07:03:50.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:03:50.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:03:50.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:03:50.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:03:50.84$vck44/va=5,3 2006.285.07:03:50.84#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.07:03:50.84#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.07:03:50.84#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:50.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:03:50.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:03:50.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:03:50.90#ibcon#enter wrdev, iclass 5, count 2 2006.285.07:03:50.90#ibcon#first serial, iclass 5, count 2 2006.285.07:03:50.90#ibcon#enter sib2, iclass 5, count 2 2006.285.07:03:50.90#ibcon#flushed, iclass 5, count 2 2006.285.07:03:50.90#ibcon#about to write, iclass 5, count 2 2006.285.07:03:50.90#ibcon#wrote, iclass 5, count 2 2006.285.07:03:50.90#ibcon#about to read 3, iclass 5, count 2 2006.285.07:03:50.92#ibcon#read 3, iclass 5, count 2 2006.285.07:03:50.92#ibcon#about to read 4, iclass 5, count 2 2006.285.07:03:50.92#ibcon#read 4, iclass 5, count 2 2006.285.07:03:50.92#ibcon#about to read 5, iclass 5, count 2 2006.285.07:03:50.92#ibcon#read 5, iclass 5, count 2 2006.285.07:03:50.92#ibcon#about to read 6, iclass 5, count 2 2006.285.07:03:50.92#ibcon#read 6, iclass 5, count 2 2006.285.07:03:50.92#ibcon#end of sib2, iclass 5, count 2 2006.285.07:03:50.92#ibcon#*mode == 0, iclass 5, count 2 2006.285.07:03:50.92#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.07:03:50.92#ibcon#[25=AT05-03\r\n] 2006.285.07:03:50.92#ibcon#*before write, iclass 5, count 2 2006.285.07:03:50.92#ibcon#enter sib2, iclass 5, count 2 2006.285.07:03:50.92#ibcon#flushed, iclass 5, count 2 2006.285.07:03:50.92#ibcon#about to write, iclass 5, count 2 2006.285.07:03:50.92#ibcon#wrote, iclass 5, count 2 2006.285.07:03:50.92#ibcon#about to read 3, iclass 5, count 2 2006.285.07:03:50.95#ibcon#read 3, iclass 5, count 2 2006.285.07:03:50.95#ibcon#about to read 4, iclass 5, count 2 2006.285.07:03:50.95#ibcon#read 4, iclass 5, count 2 2006.285.07:03:50.95#ibcon#about to read 5, iclass 5, count 2 2006.285.07:03:50.95#ibcon#read 5, iclass 5, count 2 2006.285.07:03:50.95#ibcon#about to read 6, iclass 5, count 2 2006.285.07:03:50.95#ibcon#read 6, iclass 5, count 2 2006.285.07:03:50.95#ibcon#end of sib2, iclass 5, count 2 2006.285.07:03:50.95#ibcon#*after write, iclass 5, count 2 2006.285.07:03:50.95#ibcon#*before return 0, iclass 5, count 2 2006.285.07:03:50.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:03:50.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:03:50.95#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.07:03:50.95#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:50.95#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:03:51.07#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:03:51.07#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:03:51.07#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:03:51.07#ibcon#first serial, iclass 5, count 0 2006.285.07:03:51.07#ibcon#enter sib2, iclass 5, count 0 2006.285.07:03:51.07#ibcon#flushed, iclass 5, count 0 2006.285.07:03:51.07#ibcon#about to write, iclass 5, count 0 2006.285.07:03:51.07#ibcon#wrote, iclass 5, count 0 2006.285.07:03:51.07#ibcon#about to read 3, iclass 5, count 0 2006.285.07:03:51.09#ibcon#read 3, iclass 5, count 0 2006.285.07:03:51.09#ibcon#about to read 4, iclass 5, count 0 2006.285.07:03:51.09#ibcon#read 4, iclass 5, count 0 2006.285.07:03:51.09#ibcon#about to read 5, iclass 5, count 0 2006.285.07:03:51.09#ibcon#read 5, iclass 5, count 0 2006.285.07:03:51.09#ibcon#about to read 6, iclass 5, count 0 2006.285.07:03:51.09#ibcon#read 6, iclass 5, count 0 2006.285.07:03:51.09#ibcon#end of sib2, iclass 5, count 0 2006.285.07:03:51.09#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:03:51.09#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:03:51.09#ibcon#[25=USB\r\n] 2006.285.07:03:51.09#ibcon#*before write, iclass 5, count 0 2006.285.07:03:51.09#ibcon#enter sib2, iclass 5, count 0 2006.285.07:03:51.09#ibcon#flushed, iclass 5, count 0 2006.285.07:03:51.09#ibcon#about to write, iclass 5, count 0 2006.285.07:03:51.09#ibcon#wrote, iclass 5, count 0 2006.285.07:03:51.09#ibcon#about to read 3, iclass 5, count 0 2006.285.07:03:51.12#ibcon#read 3, iclass 5, count 0 2006.285.07:03:51.12#ibcon#about to read 4, iclass 5, count 0 2006.285.07:03:51.12#ibcon#read 4, iclass 5, count 0 2006.285.07:03:51.12#ibcon#about to read 5, iclass 5, count 0 2006.285.07:03:51.12#ibcon#read 5, iclass 5, count 0 2006.285.07:03:51.12#ibcon#about to read 6, iclass 5, count 0 2006.285.07:03:51.12#ibcon#read 6, iclass 5, count 0 2006.285.07:03:51.12#ibcon#end of sib2, iclass 5, count 0 2006.285.07:03:51.12#ibcon#*after write, iclass 5, count 0 2006.285.07:03:51.12#ibcon#*before return 0, iclass 5, count 0 2006.285.07:03:51.12#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:03:51.12#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:03:51.12#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:03:51.12#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:03:51.12$vck44/valo=6,814.99 2006.285.07:03:51.12#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.07:03:51.12#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.07:03:51.12#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:51.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:03:51.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:03:51.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:03:51.13#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:03:51.13#ibcon#first serial, iclass 7, count 0 2006.285.07:03:51.13#ibcon#enter sib2, iclass 7, count 0 2006.285.07:03:51.13#ibcon#flushed, iclass 7, count 0 2006.285.07:03:51.13#ibcon#about to write, iclass 7, count 0 2006.285.07:03:51.13#ibcon#wrote, iclass 7, count 0 2006.285.07:03:51.13#ibcon#about to read 3, iclass 7, count 0 2006.285.07:03:51.14#ibcon#read 3, iclass 7, count 0 2006.285.07:03:51.14#ibcon#about to read 4, iclass 7, count 0 2006.285.07:03:51.14#ibcon#read 4, iclass 7, count 0 2006.285.07:03:51.14#ibcon#about to read 5, iclass 7, count 0 2006.285.07:03:51.14#ibcon#read 5, iclass 7, count 0 2006.285.07:03:51.14#ibcon#about to read 6, iclass 7, count 0 2006.285.07:03:51.14#ibcon#read 6, iclass 7, count 0 2006.285.07:03:51.14#ibcon#end of sib2, iclass 7, count 0 2006.285.07:03:51.14#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:03:51.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:03:51.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:03:51.15#ibcon#*before write, iclass 7, count 0 2006.285.07:03:51.15#ibcon#enter sib2, iclass 7, count 0 2006.285.07:03:51.15#ibcon#flushed, iclass 7, count 0 2006.285.07:03:51.15#ibcon#about to write, iclass 7, count 0 2006.285.07:03:51.15#ibcon#wrote, iclass 7, count 0 2006.285.07:03:51.15#ibcon#about to read 3, iclass 7, count 0 2006.285.07:03:51.18#ibcon#read 3, iclass 7, count 0 2006.285.07:03:51.18#ibcon#about to read 4, iclass 7, count 0 2006.285.07:03:51.18#ibcon#read 4, iclass 7, count 0 2006.285.07:03:51.18#ibcon#about to read 5, iclass 7, count 0 2006.285.07:03:51.18#ibcon#read 5, iclass 7, count 0 2006.285.07:03:51.18#ibcon#about to read 6, iclass 7, count 0 2006.285.07:03:51.18#ibcon#read 6, iclass 7, count 0 2006.285.07:03:51.18#ibcon#end of sib2, iclass 7, count 0 2006.285.07:03:51.18#ibcon#*after write, iclass 7, count 0 2006.285.07:03:51.18#ibcon#*before return 0, iclass 7, count 0 2006.285.07:03:51.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:03:51.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:03:51.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:03:51.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:03:51.18$vck44/va=6,4 2006.285.07:03:51.18#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.07:03:51.18#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.07:03:51.18#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:51.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:03:51.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:03:51.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:03:51.24#ibcon#enter wrdev, iclass 11, count 2 2006.285.07:03:51.24#ibcon#first serial, iclass 11, count 2 2006.285.07:03:51.24#ibcon#enter sib2, iclass 11, count 2 2006.285.07:03:51.24#ibcon#flushed, iclass 11, count 2 2006.285.07:03:51.24#ibcon#about to write, iclass 11, count 2 2006.285.07:03:51.24#ibcon#wrote, iclass 11, count 2 2006.285.07:03:51.24#ibcon#about to read 3, iclass 11, count 2 2006.285.07:03:51.26#ibcon#read 3, iclass 11, count 2 2006.285.07:03:51.26#ibcon#about to read 4, iclass 11, count 2 2006.285.07:03:51.26#ibcon#read 4, iclass 11, count 2 2006.285.07:03:51.26#ibcon#about to read 5, iclass 11, count 2 2006.285.07:03:51.26#ibcon#read 5, iclass 11, count 2 2006.285.07:03:51.26#ibcon#about to read 6, iclass 11, count 2 2006.285.07:03:51.26#ibcon#read 6, iclass 11, count 2 2006.285.07:03:51.26#ibcon#end of sib2, iclass 11, count 2 2006.285.07:03:51.26#ibcon#*mode == 0, iclass 11, count 2 2006.285.07:03:51.26#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.07:03:51.26#ibcon#[25=AT06-04\r\n] 2006.285.07:03:51.26#ibcon#*before write, iclass 11, count 2 2006.285.07:03:51.26#ibcon#enter sib2, iclass 11, count 2 2006.285.07:03:51.26#ibcon#flushed, iclass 11, count 2 2006.285.07:03:51.26#ibcon#about to write, iclass 11, count 2 2006.285.07:03:51.26#ibcon#wrote, iclass 11, count 2 2006.285.07:03:51.26#ibcon#about to read 3, iclass 11, count 2 2006.285.07:03:51.29#ibcon#read 3, iclass 11, count 2 2006.285.07:03:51.29#ibcon#about to read 4, iclass 11, count 2 2006.285.07:03:51.29#ibcon#read 4, iclass 11, count 2 2006.285.07:03:51.29#ibcon#about to read 5, iclass 11, count 2 2006.285.07:03:51.29#ibcon#read 5, iclass 11, count 2 2006.285.07:03:51.29#ibcon#about to read 6, iclass 11, count 2 2006.285.07:03:51.29#ibcon#read 6, iclass 11, count 2 2006.285.07:03:51.29#ibcon#end of sib2, iclass 11, count 2 2006.285.07:03:51.29#ibcon#*after write, iclass 11, count 2 2006.285.07:03:51.29#ibcon#*before return 0, iclass 11, count 2 2006.285.07:03:51.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:03:51.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:03:51.29#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.07:03:51.29#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:51.29#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:03:51.41#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:03:51.41#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:03:51.41#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:03:51.41#ibcon#first serial, iclass 11, count 0 2006.285.07:03:51.41#ibcon#enter sib2, iclass 11, count 0 2006.285.07:03:51.41#ibcon#flushed, iclass 11, count 0 2006.285.07:03:51.41#ibcon#about to write, iclass 11, count 0 2006.285.07:03:51.41#ibcon#wrote, iclass 11, count 0 2006.285.07:03:51.41#ibcon#about to read 3, iclass 11, count 0 2006.285.07:03:51.43#ibcon#read 3, iclass 11, count 0 2006.285.07:03:51.43#ibcon#about to read 4, iclass 11, count 0 2006.285.07:03:51.43#ibcon#read 4, iclass 11, count 0 2006.285.07:03:51.43#ibcon#about to read 5, iclass 11, count 0 2006.285.07:03:51.43#ibcon#read 5, iclass 11, count 0 2006.285.07:03:51.43#ibcon#about to read 6, iclass 11, count 0 2006.285.07:03:51.43#ibcon#read 6, iclass 11, count 0 2006.285.07:03:51.43#ibcon#end of sib2, iclass 11, count 0 2006.285.07:03:51.43#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:03:51.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:03:51.43#ibcon#[25=USB\r\n] 2006.285.07:03:51.43#ibcon#*before write, iclass 11, count 0 2006.285.07:03:51.43#ibcon#enter sib2, iclass 11, count 0 2006.285.07:03:51.43#ibcon#flushed, iclass 11, count 0 2006.285.07:03:51.43#ibcon#about to write, iclass 11, count 0 2006.285.07:03:51.43#ibcon#wrote, iclass 11, count 0 2006.285.07:03:51.43#ibcon#about to read 3, iclass 11, count 0 2006.285.07:03:51.46#ibcon#read 3, iclass 11, count 0 2006.285.07:03:51.46#ibcon#about to read 4, iclass 11, count 0 2006.285.07:03:51.46#ibcon#read 4, iclass 11, count 0 2006.285.07:03:51.46#ibcon#about to read 5, iclass 11, count 0 2006.285.07:03:51.46#ibcon#read 5, iclass 11, count 0 2006.285.07:03:51.46#ibcon#about to read 6, iclass 11, count 0 2006.285.07:03:51.46#ibcon#read 6, iclass 11, count 0 2006.285.07:03:51.46#ibcon#end of sib2, iclass 11, count 0 2006.285.07:03:51.46#ibcon#*after write, iclass 11, count 0 2006.285.07:03:51.46#ibcon#*before return 0, iclass 11, count 0 2006.285.07:03:51.46#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:03:51.46#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:03:51.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:03:51.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:03:51.46$vck44/valo=7,864.99 2006.285.07:03:51.46#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.07:03:51.46#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.07:03:51.46#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:51.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:03:51.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:03:51.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:03:51.46#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:03:51.46#ibcon#first serial, iclass 13, count 0 2006.285.07:03:51.46#ibcon#enter sib2, iclass 13, count 0 2006.285.07:03:51.46#ibcon#flushed, iclass 13, count 0 2006.285.07:03:51.46#ibcon#about to write, iclass 13, count 0 2006.285.07:03:51.47#ibcon#wrote, iclass 13, count 0 2006.285.07:03:51.47#ibcon#about to read 3, iclass 13, count 0 2006.285.07:03:51.48#ibcon#read 3, iclass 13, count 0 2006.285.07:03:51.48#ibcon#about to read 4, iclass 13, count 0 2006.285.07:03:51.48#ibcon#read 4, iclass 13, count 0 2006.285.07:03:51.48#ibcon#about to read 5, iclass 13, count 0 2006.285.07:03:51.48#ibcon#read 5, iclass 13, count 0 2006.285.07:03:51.48#ibcon#about to read 6, iclass 13, count 0 2006.285.07:03:51.48#ibcon#read 6, iclass 13, count 0 2006.285.07:03:51.48#ibcon#end of sib2, iclass 13, count 0 2006.285.07:03:51.48#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:03:51.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:03:51.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:03:51.48#ibcon#*before write, iclass 13, count 0 2006.285.07:03:51.48#ibcon#enter sib2, iclass 13, count 0 2006.285.07:03:51.48#ibcon#flushed, iclass 13, count 0 2006.285.07:03:51.48#ibcon#about to write, iclass 13, count 0 2006.285.07:03:51.48#ibcon#wrote, iclass 13, count 0 2006.285.07:03:51.48#ibcon#about to read 3, iclass 13, count 0 2006.285.07:03:51.52#ibcon#read 3, iclass 13, count 0 2006.285.07:03:51.52#ibcon#about to read 4, iclass 13, count 0 2006.285.07:03:51.52#ibcon#read 4, iclass 13, count 0 2006.285.07:03:51.52#ibcon#about to read 5, iclass 13, count 0 2006.285.07:03:51.52#ibcon#read 5, iclass 13, count 0 2006.285.07:03:51.52#ibcon#about to read 6, iclass 13, count 0 2006.285.07:03:51.52#ibcon#read 6, iclass 13, count 0 2006.285.07:03:51.52#ibcon#end of sib2, iclass 13, count 0 2006.285.07:03:51.52#ibcon#*after write, iclass 13, count 0 2006.285.07:03:51.52#ibcon#*before return 0, iclass 13, count 0 2006.285.07:03:51.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:03:51.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:03:51.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:03:51.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:03:51.52$vck44/va=7,4 2006.285.07:03:51.52#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.07:03:51.52#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.07:03:51.52#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:51.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:03:51.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:03:51.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:03:51.58#ibcon#enter wrdev, iclass 15, count 2 2006.285.07:03:51.58#ibcon#first serial, iclass 15, count 2 2006.285.07:03:51.58#ibcon#enter sib2, iclass 15, count 2 2006.285.07:03:51.58#ibcon#flushed, iclass 15, count 2 2006.285.07:03:51.58#ibcon#about to write, iclass 15, count 2 2006.285.07:03:51.58#ibcon#wrote, iclass 15, count 2 2006.285.07:03:51.58#ibcon#about to read 3, iclass 15, count 2 2006.285.07:03:51.60#ibcon#read 3, iclass 15, count 2 2006.285.07:03:51.60#ibcon#about to read 4, iclass 15, count 2 2006.285.07:03:51.60#ibcon#read 4, iclass 15, count 2 2006.285.07:03:51.60#ibcon#about to read 5, iclass 15, count 2 2006.285.07:03:51.60#ibcon#read 5, iclass 15, count 2 2006.285.07:03:51.60#ibcon#about to read 6, iclass 15, count 2 2006.285.07:03:51.60#ibcon#read 6, iclass 15, count 2 2006.285.07:03:51.60#ibcon#end of sib2, iclass 15, count 2 2006.285.07:03:51.60#ibcon#*mode == 0, iclass 15, count 2 2006.285.07:03:51.60#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.07:03:51.60#ibcon#[25=AT07-04\r\n] 2006.285.07:03:51.60#ibcon#*before write, iclass 15, count 2 2006.285.07:03:51.60#ibcon#enter sib2, iclass 15, count 2 2006.285.07:03:51.60#ibcon#flushed, iclass 15, count 2 2006.285.07:03:51.60#ibcon#about to write, iclass 15, count 2 2006.285.07:03:51.60#ibcon#wrote, iclass 15, count 2 2006.285.07:03:51.60#ibcon#about to read 3, iclass 15, count 2 2006.285.07:03:51.63#ibcon#read 3, iclass 15, count 2 2006.285.07:03:51.63#ibcon#about to read 4, iclass 15, count 2 2006.285.07:03:51.63#ibcon#read 4, iclass 15, count 2 2006.285.07:03:51.63#ibcon#about to read 5, iclass 15, count 2 2006.285.07:03:51.63#ibcon#read 5, iclass 15, count 2 2006.285.07:03:51.63#ibcon#about to read 6, iclass 15, count 2 2006.285.07:03:51.63#ibcon#read 6, iclass 15, count 2 2006.285.07:03:51.63#ibcon#end of sib2, iclass 15, count 2 2006.285.07:03:51.63#ibcon#*after write, iclass 15, count 2 2006.285.07:03:51.63#ibcon#*before return 0, iclass 15, count 2 2006.285.07:03:51.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:03:51.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:03:51.63#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.07:03:51.63#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:51.63#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:03:51.75#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:03:51.75#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:03:51.75#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:03:51.75#ibcon#first serial, iclass 15, count 0 2006.285.07:03:51.75#ibcon#enter sib2, iclass 15, count 0 2006.285.07:03:51.75#ibcon#flushed, iclass 15, count 0 2006.285.07:03:51.75#ibcon#about to write, iclass 15, count 0 2006.285.07:03:51.75#ibcon#wrote, iclass 15, count 0 2006.285.07:03:51.75#ibcon#about to read 3, iclass 15, count 0 2006.285.07:03:51.77#ibcon#read 3, iclass 15, count 0 2006.285.07:03:51.77#ibcon#about to read 4, iclass 15, count 0 2006.285.07:03:51.77#ibcon#read 4, iclass 15, count 0 2006.285.07:03:51.77#ibcon#about to read 5, iclass 15, count 0 2006.285.07:03:51.77#ibcon#read 5, iclass 15, count 0 2006.285.07:03:51.77#ibcon#about to read 6, iclass 15, count 0 2006.285.07:03:51.77#ibcon#read 6, iclass 15, count 0 2006.285.07:03:51.77#ibcon#end of sib2, iclass 15, count 0 2006.285.07:03:51.77#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:03:51.77#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:03:51.77#ibcon#[25=USB\r\n] 2006.285.07:03:51.77#ibcon#*before write, iclass 15, count 0 2006.285.07:03:51.77#ibcon#enter sib2, iclass 15, count 0 2006.285.07:03:51.77#ibcon#flushed, iclass 15, count 0 2006.285.07:03:51.77#ibcon#about to write, iclass 15, count 0 2006.285.07:03:51.77#ibcon#wrote, iclass 15, count 0 2006.285.07:03:51.77#ibcon#about to read 3, iclass 15, count 0 2006.285.07:03:51.80#ibcon#read 3, iclass 15, count 0 2006.285.07:03:51.80#ibcon#about to read 4, iclass 15, count 0 2006.285.07:03:51.80#ibcon#read 4, iclass 15, count 0 2006.285.07:03:51.80#ibcon#about to read 5, iclass 15, count 0 2006.285.07:03:51.80#ibcon#read 5, iclass 15, count 0 2006.285.07:03:51.80#ibcon#about to read 6, iclass 15, count 0 2006.285.07:03:51.80#ibcon#read 6, iclass 15, count 0 2006.285.07:03:51.80#ibcon#end of sib2, iclass 15, count 0 2006.285.07:03:51.80#ibcon#*after write, iclass 15, count 0 2006.285.07:03:51.80#ibcon#*before return 0, iclass 15, count 0 2006.285.07:03:51.80#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:03:51.80#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:03:51.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:03:51.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:03:51.80$vck44/valo=8,884.99 2006.285.07:03:51.80#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.07:03:51.80#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.07:03:51.80#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:51.80#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:03:51.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:03:51.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:03:51.80#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:03:51.80#ibcon#first serial, iclass 17, count 0 2006.285.07:03:51.80#ibcon#enter sib2, iclass 17, count 0 2006.285.07:03:51.80#ibcon#flushed, iclass 17, count 0 2006.285.07:03:51.81#ibcon#about to write, iclass 17, count 0 2006.285.07:03:51.81#ibcon#wrote, iclass 17, count 0 2006.285.07:03:51.81#ibcon#about to read 3, iclass 17, count 0 2006.285.07:03:51.82#ibcon#read 3, iclass 17, count 0 2006.285.07:03:51.82#ibcon#about to read 4, iclass 17, count 0 2006.285.07:03:51.82#ibcon#read 4, iclass 17, count 0 2006.285.07:03:51.82#ibcon#about to read 5, iclass 17, count 0 2006.285.07:03:51.82#ibcon#read 5, iclass 17, count 0 2006.285.07:03:51.82#ibcon#about to read 6, iclass 17, count 0 2006.285.07:03:51.82#ibcon#read 6, iclass 17, count 0 2006.285.07:03:51.82#ibcon#end of sib2, iclass 17, count 0 2006.285.07:03:51.82#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:03:51.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:03:51.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:03:51.82#ibcon#*before write, iclass 17, count 0 2006.285.07:03:51.82#ibcon#enter sib2, iclass 17, count 0 2006.285.07:03:51.82#ibcon#flushed, iclass 17, count 0 2006.285.07:03:51.82#ibcon#about to write, iclass 17, count 0 2006.285.07:03:51.82#ibcon#wrote, iclass 17, count 0 2006.285.07:03:51.82#ibcon#about to read 3, iclass 17, count 0 2006.285.07:03:51.86#ibcon#read 3, iclass 17, count 0 2006.285.07:03:51.86#ibcon#about to read 4, iclass 17, count 0 2006.285.07:03:51.86#ibcon#read 4, iclass 17, count 0 2006.285.07:03:51.86#ibcon#about to read 5, iclass 17, count 0 2006.285.07:03:51.86#ibcon#read 5, iclass 17, count 0 2006.285.07:03:51.86#ibcon#about to read 6, iclass 17, count 0 2006.285.07:03:51.86#ibcon#read 6, iclass 17, count 0 2006.285.07:03:51.86#ibcon#end of sib2, iclass 17, count 0 2006.285.07:03:51.86#ibcon#*after write, iclass 17, count 0 2006.285.07:03:51.86#ibcon#*before return 0, iclass 17, count 0 2006.285.07:03:51.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:03:51.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:03:51.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:03:51.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:03:51.86$vck44/va=8,3 2006.285.07:03:51.86#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.07:03:51.86#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.07:03:51.86#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:51.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:03:51.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:03:51.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:03:51.92#ibcon#enter wrdev, iclass 19, count 2 2006.285.07:03:51.92#ibcon#first serial, iclass 19, count 2 2006.285.07:03:51.92#ibcon#enter sib2, iclass 19, count 2 2006.285.07:03:51.92#ibcon#flushed, iclass 19, count 2 2006.285.07:03:51.92#ibcon#about to write, iclass 19, count 2 2006.285.07:03:51.92#ibcon#wrote, iclass 19, count 2 2006.285.07:03:51.92#ibcon#about to read 3, iclass 19, count 2 2006.285.07:03:51.94#ibcon#read 3, iclass 19, count 2 2006.285.07:03:51.94#ibcon#about to read 4, iclass 19, count 2 2006.285.07:03:51.94#ibcon#read 4, iclass 19, count 2 2006.285.07:03:51.94#ibcon#about to read 5, iclass 19, count 2 2006.285.07:03:51.94#ibcon#read 5, iclass 19, count 2 2006.285.07:03:51.94#ibcon#about to read 6, iclass 19, count 2 2006.285.07:03:51.94#ibcon#read 6, iclass 19, count 2 2006.285.07:03:51.94#ibcon#end of sib2, iclass 19, count 2 2006.285.07:03:51.94#ibcon#*mode == 0, iclass 19, count 2 2006.285.07:03:51.94#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.07:03:51.94#ibcon#[25=AT08-03\r\n] 2006.285.07:03:51.94#ibcon#*before write, iclass 19, count 2 2006.285.07:03:51.94#ibcon#enter sib2, iclass 19, count 2 2006.285.07:03:51.94#ibcon#flushed, iclass 19, count 2 2006.285.07:03:51.94#ibcon#about to write, iclass 19, count 2 2006.285.07:03:51.94#ibcon#wrote, iclass 19, count 2 2006.285.07:03:51.94#ibcon#about to read 3, iclass 19, count 2 2006.285.07:03:51.97#ibcon#read 3, iclass 19, count 2 2006.285.07:03:51.97#ibcon#about to read 4, iclass 19, count 2 2006.285.07:03:51.97#ibcon#read 4, iclass 19, count 2 2006.285.07:03:51.97#ibcon#about to read 5, iclass 19, count 2 2006.285.07:03:51.97#ibcon#read 5, iclass 19, count 2 2006.285.07:03:51.97#ibcon#about to read 6, iclass 19, count 2 2006.285.07:03:51.97#ibcon#read 6, iclass 19, count 2 2006.285.07:03:51.97#ibcon#end of sib2, iclass 19, count 2 2006.285.07:03:51.97#ibcon#*after write, iclass 19, count 2 2006.285.07:03:51.97#ibcon#*before return 0, iclass 19, count 2 2006.285.07:03:51.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:03:51.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:03:51.97#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.07:03:51.97#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:51.97#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:03:52.09#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:03:52.09#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:03:52.09#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:03:52.09#ibcon#first serial, iclass 19, count 0 2006.285.07:03:52.09#ibcon#enter sib2, iclass 19, count 0 2006.285.07:03:52.09#ibcon#flushed, iclass 19, count 0 2006.285.07:03:52.09#ibcon#about to write, iclass 19, count 0 2006.285.07:03:52.09#ibcon#wrote, iclass 19, count 0 2006.285.07:03:52.09#ibcon#about to read 3, iclass 19, count 0 2006.285.07:03:52.11#ibcon#read 3, iclass 19, count 0 2006.285.07:03:52.11#ibcon#about to read 4, iclass 19, count 0 2006.285.07:03:52.11#ibcon#read 4, iclass 19, count 0 2006.285.07:03:52.11#ibcon#about to read 5, iclass 19, count 0 2006.285.07:03:52.11#ibcon#read 5, iclass 19, count 0 2006.285.07:03:52.11#ibcon#about to read 6, iclass 19, count 0 2006.285.07:03:52.11#ibcon#read 6, iclass 19, count 0 2006.285.07:03:52.11#ibcon#end of sib2, iclass 19, count 0 2006.285.07:03:52.11#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:03:52.11#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:03:52.11#ibcon#[25=USB\r\n] 2006.285.07:03:52.11#ibcon#*before write, iclass 19, count 0 2006.285.07:03:52.11#ibcon#enter sib2, iclass 19, count 0 2006.285.07:03:52.11#ibcon#flushed, iclass 19, count 0 2006.285.07:03:52.11#ibcon#about to write, iclass 19, count 0 2006.285.07:03:52.11#ibcon#wrote, iclass 19, count 0 2006.285.07:03:52.11#ibcon#about to read 3, iclass 19, count 0 2006.285.07:03:52.14#ibcon#read 3, iclass 19, count 0 2006.285.07:03:52.14#ibcon#about to read 4, iclass 19, count 0 2006.285.07:03:52.14#ibcon#read 4, iclass 19, count 0 2006.285.07:03:52.14#ibcon#about to read 5, iclass 19, count 0 2006.285.07:03:52.14#ibcon#read 5, iclass 19, count 0 2006.285.07:03:52.14#ibcon#about to read 6, iclass 19, count 0 2006.285.07:03:52.14#ibcon#read 6, iclass 19, count 0 2006.285.07:03:52.14#ibcon#end of sib2, iclass 19, count 0 2006.285.07:03:52.14#ibcon#*after write, iclass 19, count 0 2006.285.07:03:52.14#ibcon#*before return 0, iclass 19, count 0 2006.285.07:03:52.14#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:03:52.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:03:52.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:03:52.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:03:52.15$vck44/vblo=1,629.99 2006.285.07:03:52.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.07:03:52.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.07:03:52.15#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:52.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:03:52.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:03:52.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:03:52.15#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:03:52.15#ibcon#first serial, iclass 21, count 0 2006.285.07:03:52.15#ibcon#enter sib2, iclass 21, count 0 2006.285.07:03:52.15#ibcon#flushed, iclass 21, count 0 2006.285.07:03:52.15#ibcon#about to write, iclass 21, count 0 2006.285.07:03:52.15#ibcon#wrote, iclass 21, count 0 2006.285.07:03:52.15#ibcon#about to read 3, iclass 21, count 0 2006.285.07:03:52.16#ibcon#read 3, iclass 21, count 0 2006.285.07:03:52.16#ibcon#about to read 4, iclass 21, count 0 2006.285.07:03:52.16#ibcon#read 4, iclass 21, count 0 2006.285.07:03:52.16#ibcon#about to read 5, iclass 21, count 0 2006.285.07:03:52.16#ibcon#read 5, iclass 21, count 0 2006.285.07:03:52.16#ibcon#about to read 6, iclass 21, count 0 2006.285.07:03:52.16#ibcon#read 6, iclass 21, count 0 2006.285.07:03:52.16#ibcon#end of sib2, iclass 21, count 0 2006.285.07:03:52.16#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:03:52.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:03:52.16#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:03:52.16#ibcon#*before write, iclass 21, count 0 2006.285.07:03:52.16#ibcon#enter sib2, iclass 21, count 0 2006.285.07:03:52.16#ibcon#flushed, iclass 21, count 0 2006.285.07:03:52.16#ibcon#about to write, iclass 21, count 0 2006.285.07:03:52.16#ibcon#wrote, iclass 21, count 0 2006.285.07:03:52.16#ibcon#about to read 3, iclass 21, count 0 2006.285.07:03:52.20#ibcon#read 3, iclass 21, count 0 2006.285.07:03:52.20#ibcon#about to read 4, iclass 21, count 0 2006.285.07:03:52.20#ibcon#read 4, iclass 21, count 0 2006.285.07:03:52.20#ibcon#about to read 5, iclass 21, count 0 2006.285.07:03:52.20#ibcon#read 5, iclass 21, count 0 2006.285.07:03:52.20#ibcon#about to read 6, iclass 21, count 0 2006.285.07:03:52.20#ibcon#read 6, iclass 21, count 0 2006.285.07:03:52.20#ibcon#end of sib2, iclass 21, count 0 2006.285.07:03:52.20#ibcon#*after write, iclass 21, count 0 2006.285.07:03:52.20#ibcon#*before return 0, iclass 21, count 0 2006.285.07:03:52.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:03:52.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:03:52.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:03:52.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:03:52.20$vck44/vb=1,4 2006.285.07:03:52.20#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.07:03:52.20#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.07:03:52.20#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:52.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:03:52.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:03:52.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:03:52.20#ibcon#enter wrdev, iclass 23, count 2 2006.285.07:03:52.20#ibcon#first serial, iclass 23, count 2 2006.285.07:03:52.20#ibcon#enter sib2, iclass 23, count 2 2006.285.07:03:52.21#ibcon#flushed, iclass 23, count 2 2006.285.07:03:52.21#ibcon#about to write, iclass 23, count 2 2006.285.07:03:52.21#ibcon#wrote, iclass 23, count 2 2006.285.07:03:52.21#ibcon#about to read 3, iclass 23, count 2 2006.285.07:03:52.22#ibcon#read 3, iclass 23, count 2 2006.285.07:03:52.22#ibcon#about to read 4, iclass 23, count 2 2006.285.07:03:52.22#ibcon#read 4, iclass 23, count 2 2006.285.07:03:52.22#ibcon#about to read 5, iclass 23, count 2 2006.285.07:03:52.22#ibcon#read 5, iclass 23, count 2 2006.285.07:03:52.22#ibcon#about to read 6, iclass 23, count 2 2006.285.07:03:52.22#ibcon#read 6, iclass 23, count 2 2006.285.07:03:52.22#ibcon#end of sib2, iclass 23, count 2 2006.285.07:03:52.22#ibcon#*mode == 0, iclass 23, count 2 2006.285.07:03:52.22#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.07:03:52.22#ibcon#[27=AT01-04\r\n] 2006.285.07:03:52.22#ibcon#*before write, iclass 23, count 2 2006.285.07:03:52.22#ibcon#enter sib2, iclass 23, count 2 2006.285.07:03:52.22#ibcon#flushed, iclass 23, count 2 2006.285.07:03:52.22#ibcon#about to write, iclass 23, count 2 2006.285.07:03:52.22#ibcon#wrote, iclass 23, count 2 2006.285.07:03:52.22#ibcon#about to read 3, iclass 23, count 2 2006.285.07:03:52.25#ibcon#read 3, iclass 23, count 2 2006.285.07:03:52.25#ibcon#about to read 4, iclass 23, count 2 2006.285.07:03:52.25#ibcon#read 4, iclass 23, count 2 2006.285.07:03:52.25#ibcon#about to read 5, iclass 23, count 2 2006.285.07:03:52.25#ibcon#read 5, iclass 23, count 2 2006.285.07:03:52.25#ibcon#about to read 6, iclass 23, count 2 2006.285.07:03:52.25#ibcon#read 6, iclass 23, count 2 2006.285.07:03:52.25#ibcon#end of sib2, iclass 23, count 2 2006.285.07:03:52.25#ibcon#*after write, iclass 23, count 2 2006.285.07:03:52.25#ibcon#*before return 0, iclass 23, count 2 2006.285.07:03:52.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:03:52.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:03:52.25#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.07:03:52.25#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:52.25#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:03:52.37#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:03:52.37#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:03:52.37#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:03:52.37#ibcon#first serial, iclass 23, count 0 2006.285.07:03:52.37#ibcon#enter sib2, iclass 23, count 0 2006.285.07:03:52.37#ibcon#flushed, iclass 23, count 0 2006.285.07:03:52.37#ibcon#about to write, iclass 23, count 0 2006.285.07:03:52.37#ibcon#wrote, iclass 23, count 0 2006.285.07:03:52.37#ibcon#about to read 3, iclass 23, count 0 2006.285.07:03:52.39#ibcon#read 3, iclass 23, count 0 2006.285.07:03:52.39#ibcon#about to read 4, iclass 23, count 0 2006.285.07:03:52.39#ibcon#read 4, iclass 23, count 0 2006.285.07:03:52.39#ibcon#about to read 5, iclass 23, count 0 2006.285.07:03:52.39#ibcon#read 5, iclass 23, count 0 2006.285.07:03:52.39#ibcon#about to read 6, iclass 23, count 0 2006.285.07:03:52.39#ibcon#read 6, iclass 23, count 0 2006.285.07:03:52.39#ibcon#end of sib2, iclass 23, count 0 2006.285.07:03:52.39#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:03:52.39#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:03:52.39#ibcon#[27=USB\r\n] 2006.285.07:03:52.39#ibcon#*before write, iclass 23, count 0 2006.285.07:03:52.39#ibcon#enter sib2, iclass 23, count 0 2006.285.07:03:52.39#ibcon#flushed, iclass 23, count 0 2006.285.07:03:52.39#ibcon#about to write, iclass 23, count 0 2006.285.07:03:52.39#ibcon#wrote, iclass 23, count 0 2006.285.07:03:52.39#ibcon#about to read 3, iclass 23, count 0 2006.285.07:03:52.42#ibcon#read 3, iclass 23, count 0 2006.285.07:03:52.42#ibcon#about to read 4, iclass 23, count 0 2006.285.07:03:52.42#ibcon#read 4, iclass 23, count 0 2006.285.07:03:52.42#ibcon#about to read 5, iclass 23, count 0 2006.285.07:03:52.42#ibcon#read 5, iclass 23, count 0 2006.285.07:03:52.42#ibcon#about to read 6, iclass 23, count 0 2006.285.07:03:52.42#ibcon#read 6, iclass 23, count 0 2006.285.07:03:52.42#ibcon#end of sib2, iclass 23, count 0 2006.285.07:03:52.42#ibcon#*after write, iclass 23, count 0 2006.285.07:03:52.42#ibcon#*before return 0, iclass 23, count 0 2006.285.07:03:52.42#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:03:52.42#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:03:52.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:03:52.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:03:52.42$vck44/vblo=2,634.99 2006.285.07:03:52.42#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.07:03:52.42#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.07:03:52.42#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:52.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:03:52.42#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:03:52.42#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:03:52.42#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:03:52.42#ibcon#first serial, iclass 25, count 0 2006.285.07:03:52.42#ibcon#enter sib2, iclass 25, count 0 2006.285.07:03:52.42#ibcon#flushed, iclass 25, count 0 2006.285.07:03:52.42#ibcon#about to write, iclass 25, count 0 2006.285.07:03:52.43#ibcon#wrote, iclass 25, count 0 2006.285.07:03:52.43#ibcon#about to read 3, iclass 25, count 0 2006.285.07:03:52.44#ibcon#read 3, iclass 25, count 0 2006.285.07:03:52.44#ibcon#about to read 4, iclass 25, count 0 2006.285.07:03:52.44#ibcon#read 4, iclass 25, count 0 2006.285.07:03:52.44#ibcon#about to read 5, iclass 25, count 0 2006.285.07:03:52.44#ibcon#read 5, iclass 25, count 0 2006.285.07:03:52.44#ibcon#about to read 6, iclass 25, count 0 2006.285.07:03:52.44#ibcon#read 6, iclass 25, count 0 2006.285.07:03:52.44#ibcon#end of sib2, iclass 25, count 0 2006.285.07:03:52.44#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:03:52.44#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:03:52.44#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:03:52.44#ibcon#*before write, iclass 25, count 0 2006.285.07:03:52.44#ibcon#enter sib2, iclass 25, count 0 2006.285.07:03:52.44#ibcon#flushed, iclass 25, count 0 2006.285.07:03:52.44#ibcon#about to write, iclass 25, count 0 2006.285.07:03:52.44#ibcon#wrote, iclass 25, count 0 2006.285.07:03:52.44#ibcon#about to read 3, iclass 25, count 0 2006.285.07:03:52.48#ibcon#read 3, iclass 25, count 0 2006.285.07:03:52.48#ibcon#about to read 4, iclass 25, count 0 2006.285.07:03:52.48#ibcon#read 4, iclass 25, count 0 2006.285.07:03:52.48#ibcon#about to read 5, iclass 25, count 0 2006.285.07:03:52.48#ibcon#read 5, iclass 25, count 0 2006.285.07:03:52.48#ibcon#about to read 6, iclass 25, count 0 2006.285.07:03:52.48#ibcon#read 6, iclass 25, count 0 2006.285.07:03:52.48#ibcon#end of sib2, iclass 25, count 0 2006.285.07:03:52.48#ibcon#*after write, iclass 25, count 0 2006.285.07:03:52.48#ibcon#*before return 0, iclass 25, count 0 2006.285.07:03:52.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:03:52.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:03:52.48#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:03:52.48#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:03:52.48$vck44/vb=2,5 2006.285.07:03:52.48#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.07:03:52.48#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.07:03:52.48#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:52.48#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:03:52.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:03:52.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:03:52.54#ibcon#enter wrdev, iclass 27, count 2 2006.285.07:03:52.54#ibcon#first serial, iclass 27, count 2 2006.285.07:03:52.54#ibcon#enter sib2, iclass 27, count 2 2006.285.07:03:52.54#ibcon#flushed, iclass 27, count 2 2006.285.07:03:52.54#ibcon#about to write, iclass 27, count 2 2006.285.07:03:52.54#ibcon#wrote, iclass 27, count 2 2006.285.07:03:52.54#ibcon#about to read 3, iclass 27, count 2 2006.285.07:03:52.56#ibcon#read 3, iclass 27, count 2 2006.285.07:03:52.56#ibcon#about to read 4, iclass 27, count 2 2006.285.07:03:52.56#ibcon#read 4, iclass 27, count 2 2006.285.07:03:52.56#ibcon#about to read 5, iclass 27, count 2 2006.285.07:03:52.56#ibcon#read 5, iclass 27, count 2 2006.285.07:03:52.56#ibcon#about to read 6, iclass 27, count 2 2006.285.07:03:52.56#ibcon#read 6, iclass 27, count 2 2006.285.07:03:52.56#ibcon#end of sib2, iclass 27, count 2 2006.285.07:03:52.56#ibcon#*mode == 0, iclass 27, count 2 2006.285.07:03:52.56#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.07:03:52.56#ibcon#[27=AT02-05\r\n] 2006.285.07:03:52.56#ibcon#*before write, iclass 27, count 2 2006.285.07:03:52.56#ibcon#enter sib2, iclass 27, count 2 2006.285.07:03:52.56#ibcon#flushed, iclass 27, count 2 2006.285.07:03:52.56#ibcon#about to write, iclass 27, count 2 2006.285.07:03:52.56#ibcon#wrote, iclass 27, count 2 2006.285.07:03:52.56#ibcon#about to read 3, iclass 27, count 2 2006.285.07:03:52.59#ibcon#read 3, iclass 27, count 2 2006.285.07:03:52.59#ibcon#about to read 4, iclass 27, count 2 2006.285.07:03:52.59#ibcon#read 4, iclass 27, count 2 2006.285.07:03:52.59#ibcon#about to read 5, iclass 27, count 2 2006.285.07:03:52.59#ibcon#read 5, iclass 27, count 2 2006.285.07:03:52.59#ibcon#about to read 6, iclass 27, count 2 2006.285.07:03:52.59#ibcon#read 6, iclass 27, count 2 2006.285.07:03:52.59#ibcon#end of sib2, iclass 27, count 2 2006.285.07:03:52.59#ibcon#*after write, iclass 27, count 2 2006.285.07:03:52.59#ibcon#*before return 0, iclass 27, count 2 2006.285.07:03:52.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:03:52.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:03:52.59#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.07:03:52.59#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:52.59#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:03:52.71#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:03:52.71#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:03:52.71#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:03:52.71#ibcon#first serial, iclass 27, count 0 2006.285.07:03:52.71#ibcon#enter sib2, iclass 27, count 0 2006.285.07:03:52.71#ibcon#flushed, iclass 27, count 0 2006.285.07:03:52.71#ibcon#about to write, iclass 27, count 0 2006.285.07:03:52.71#ibcon#wrote, iclass 27, count 0 2006.285.07:03:52.71#ibcon#about to read 3, iclass 27, count 0 2006.285.07:03:52.73#ibcon#read 3, iclass 27, count 0 2006.285.07:03:52.73#ibcon#about to read 4, iclass 27, count 0 2006.285.07:03:52.73#ibcon#read 4, iclass 27, count 0 2006.285.07:03:52.73#ibcon#about to read 5, iclass 27, count 0 2006.285.07:03:52.73#ibcon#read 5, iclass 27, count 0 2006.285.07:03:52.73#ibcon#about to read 6, iclass 27, count 0 2006.285.07:03:52.73#ibcon#read 6, iclass 27, count 0 2006.285.07:03:52.73#ibcon#end of sib2, iclass 27, count 0 2006.285.07:03:52.73#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:03:52.73#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:03:52.73#ibcon#[27=USB\r\n] 2006.285.07:03:52.73#ibcon#*before write, iclass 27, count 0 2006.285.07:03:52.73#ibcon#enter sib2, iclass 27, count 0 2006.285.07:03:52.73#ibcon#flushed, iclass 27, count 0 2006.285.07:03:52.73#ibcon#about to write, iclass 27, count 0 2006.285.07:03:52.73#ibcon#wrote, iclass 27, count 0 2006.285.07:03:52.73#ibcon#about to read 3, iclass 27, count 0 2006.285.07:03:52.76#ibcon#read 3, iclass 27, count 0 2006.285.07:03:52.76#ibcon#about to read 4, iclass 27, count 0 2006.285.07:03:52.76#ibcon#read 4, iclass 27, count 0 2006.285.07:03:52.76#ibcon#about to read 5, iclass 27, count 0 2006.285.07:03:52.76#ibcon#read 5, iclass 27, count 0 2006.285.07:03:52.76#ibcon#about to read 6, iclass 27, count 0 2006.285.07:03:52.76#ibcon#read 6, iclass 27, count 0 2006.285.07:03:52.76#ibcon#end of sib2, iclass 27, count 0 2006.285.07:03:52.76#ibcon#*after write, iclass 27, count 0 2006.285.07:03:52.76#ibcon#*before return 0, iclass 27, count 0 2006.285.07:03:52.76#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:03:52.76#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:03:52.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:03:52.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:03:52.76$vck44/vblo=3,649.99 2006.285.07:03:52.76#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.07:03:52.76#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.07:03:52.76#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:52.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:03:52.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:03:52.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:03:52.76#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:03:52.76#ibcon#first serial, iclass 29, count 0 2006.285.07:03:52.76#ibcon#enter sib2, iclass 29, count 0 2006.285.07:03:52.76#ibcon#flushed, iclass 29, count 0 2006.285.07:03:52.77#ibcon#about to write, iclass 29, count 0 2006.285.07:03:52.77#ibcon#wrote, iclass 29, count 0 2006.285.07:03:52.77#ibcon#about to read 3, iclass 29, count 0 2006.285.07:03:52.78#ibcon#read 3, iclass 29, count 0 2006.285.07:03:52.78#ibcon#about to read 4, iclass 29, count 0 2006.285.07:03:52.78#ibcon#read 4, iclass 29, count 0 2006.285.07:03:52.78#ibcon#about to read 5, iclass 29, count 0 2006.285.07:03:52.78#ibcon#read 5, iclass 29, count 0 2006.285.07:03:52.78#ibcon#about to read 6, iclass 29, count 0 2006.285.07:03:52.78#ibcon#read 6, iclass 29, count 0 2006.285.07:03:52.78#ibcon#end of sib2, iclass 29, count 0 2006.285.07:03:52.78#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:03:52.78#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:03:52.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:03:52.78#ibcon#*before write, iclass 29, count 0 2006.285.07:03:52.78#ibcon#enter sib2, iclass 29, count 0 2006.285.07:03:52.78#ibcon#flushed, iclass 29, count 0 2006.285.07:03:52.78#ibcon#about to write, iclass 29, count 0 2006.285.07:03:52.78#ibcon#wrote, iclass 29, count 0 2006.285.07:03:52.78#ibcon#about to read 3, iclass 29, count 0 2006.285.07:03:52.82#ibcon#read 3, iclass 29, count 0 2006.285.07:03:52.82#ibcon#about to read 4, iclass 29, count 0 2006.285.07:03:52.82#ibcon#read 4, iclass 29, count 0 2006.285.07:03:52.82#ibcon#about to read 5, iclass 29, count 0 2006.285.07:03:52.82#ibcon#read 5, iclass 29, count 0 2006.285.07:03:52.82#ibcon#about to read 6, iclass 29, count 0 2006.285.07:03:52.82#ibcon#read 6, iclass 29, count 0 2006.285.07:03:52.82#ibcon#end of sib2, iclass 29, count 0 2006.285.07:03:52.82#ibcon#*after write, iclass 29, count 0 2006.285.07:03:52.82#ibcon#*before return 0, iclass 29, count 0 2006.285.07:03:52.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:03:52.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:03:52.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:03:52.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:03:52.82$vck44/vb=3,4 2006.285.07:03:52.82#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.07:03:52.82#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.07:03:52.82#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:52.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:03:52.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:03:52.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:03:52.88#ibcon#enter wrdev, iclass 31, count 2 2006.285.07:03:52.88#ibcon#first serial, iclass 31, count 2 2006.285.07:03:52.88#ibcon#enter sib2, iclass 31, count 2 2006.285.07:03:52.88#ibcon#flushed, iclass 31, count 2 2006.285.07:03:52.88#ibcon#about to write, iclass 31, count 2 2006.285.07:03:52.88#ibcon#wrote, iclass 31, count 2 2006.285.07:03:52.88#ibcon#about to read 3, iclass 31, count 2 2006.285.07:03:52.90#ibcon#read 3, iclass 31, count 2 2006.285.07:03:52.90#ibcon#about to read 4, iclass 31, count 2 2006.285.07:03:52.90#ibcon#read 4, iclass 31, count 2 2006.285.07:03:52.90#ibcon#about to read 5, iclass 31, count 2 2006.285.07:03:52.90#ibcon#read 5, iclass 31, count 2 2006.285.07:03:52.90#ibcon#about to read 6, iclass 31, count 2 2006.285.07:03:52.90#ibcon#read 6, iclass 31, count 2 2006.285.07:03:52.90#ibcon#end of sib2, iclass 31, count 2 2006.285.07:03:52.90#ibcon#*mode == 0, iclass 31, count 2 2006.285.07:03:52.90#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.07:03:52.90#ibcon#[27=AT03-04\r\n] 2006.285.07:03:52.90#ibcon#*before write, iclass 31, count 2 2006.285.07:03:52.90#ibcon#enter sib2, iclass 31, count 2 2006.285.07:03:52.90#ibcon#flushed, iclass 31, count 2 2006.285.07:03:52.90#ibcon#about to write, iclass 31, count 2 2006.285.07:03:52.90#ibcon#wrote, iclass 31, count 2 2006.285.07:03:52.90#ibcon#about to read 3, iclass 31, count 2 2006.285.07:03:52.93#ibcon#read 3, iclass 31, count 2 2006.285.07:03:52.93#ibcon#about to read 4, iclass 31, count 2 2006.285.07:03:52.93#ibcon#read 4, iclass 31, count 2 2006.285.07:03:52.93#ibcon#about to read 5, iclass 31, count 2 2006.285.07:03:52.93#ibcon#read 5, iclass 31, count 2 2006.285.07:03:52.93#ibcon#about to read 6, iclass 31, count 2 2006.285.07:03:52.93#ibcon#read 6, iclass 31, count 2 2006.285.07:03:52.93#ibcon#end of sib2, iclass 31, count 2 2006.285.07:03:52.93#ibcon#*after write, iclass 31, count 2 2006.285.07:03:52.93#ibcon#*before return 0, iclass 31, count 2 2006.285.07:03:52.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:03:52.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:03:52.93#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.07:03:52.93#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:52.93#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:03:53.05#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:03:53.05#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:03:53.05#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:03:53.05#ibcon#first serial, iclass 31, count 0 2006.285.07:03:53.05#ibcon#enter sib2, iclass 31, count 0 2006.285.07:03:53.05#ibcon#flushed, iclass 31, count 0 2006.285.07:03:53.05#ibcon#about to write, iclass 31, count 0 2006.285.07:03:53.05#ibcon#wrote, iclass 31, count 0 2006.285.07:03:53.05#ibcon#about to read 3, iclass 31, count 0 2006.285.07:03:53.07#ibcon#read 3, iclass 31, count 0 2006.285.07:03:53.07#ibcon#about to read 4, iclass 31, count 0 2006.285.07:03:53.07#ibcon#read 4, iclass 31, count 0 2006.285.07:03:53.07#ibcon#about to read 5, iclass 31, count 0 2006.285.07:03:53.07#ibcon#read 5, iclass 31, count 0 2006.285.07:03:53.07#ibcon#about to read 6, iclass 31, count 0 2006.285.07:03:53.07#ibcon#read 6, iclass 31, count 0 2006.285.07:03:53.07#ibcon#end of sib2, iclass 31, count 0 2006.285.07:03:53.07#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:03:53.07#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:03:53.07#ibcon#[27=USB\r\n] 2006.285.07:03:53.07#ibcon#*before write, iclass 31, count 0 2006.285.07:03:53.07#ibcon#enter sib2, iclass 31, count 0 2006.285.07:03:53.07#ibcon#flushed, iclass 31, count 0 2006.285.07:03:53.07#ibcon#about to write, iclass 31, count 0 2006.285.07:03:53.07#ibcon#wrote, iclass 31, count 0 2006.285.07:03:53.07#ibcon#about to read 3, iclass 31, count 0 2006.285.07:03:53.10#ibcon#read 3, iclass 31, count 0 2006.285.07:03:53.10#ibcon#about to read 4, iclass 31, count 0 2006.285.07:03:53.10#ibcon#read 4, iclass 31, count 0 2006.285.07:03:53.10#ibcon#about to read 5, iclass 31, count 0 2006.285.07:03:53.10#ibcon#read 5, iclass 31, count 0 2006.285.07:03:53.10#ibcon#about to read 6, iclass 31, count 0 2006.285.07:03:53.10#ibcon#read 6, iclass 31, count 0 2006.285.07:03:53.10#ibcon#end of sib2, iclass 31, count 0 2006.285.07:03:53.10#ibcon#*after write, iclass 31, count 0 2006.285.07:03:53.10#ibcon#*before return 0, iclass 31, count 0 2006.285.07:03:53.10#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:03:53.10#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:03:53.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:03:53.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:03:53.10$vck44/vblo=4,679.99 2006.285.07:03:53.10#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.07:03:53.10#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.07:03:53.10#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:53.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:03:53.10#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:03:53.10#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:03:53.10#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:03:53.10#ibcon#first serial, iclass 33, count 0 2006.285.07:03:53.10#ibcon#enter sib2, iclass 33, count 0 2006.285.07:03:53.10#ibcon#flushed, iclass 33, count 0 2006.285.07:03:53.11#ibcon#about to write, iclass 33, count 0 2006.285.07:03:53.11#ibcon#wrote, iclass 33, count 0 2006.285.07:03:53.11#ibcon#about to read 3, iclass 33, count 0 2006.285.07:03:53.12#ibcon#read 3, iclass 33, count 0 2006.285.07:03:53.12#ibcon#about to read 4, iclass 33, count 0 2006.285.07:03:53.12#ibcon#read 4, iclass 33, count 0 2006.285.07:03:53.12#ibcon#about to read 5, iclass 33, count 0 2006.285.07:03:53.12#ibcon#read 5, iclass 33, count 0 2006.285.07:03:53.12#ibcon#about to read 6, iclass 33, count 0 2006.285.07:03:53.12#ibcon#read 6, iclass 33, count 0 2006.285.07:03:53.12#ibcon#end of sib2, iclass 33, count 0 2006.285.07:03:53.12#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:03:53.12#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:03:53.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:03:53.12#ibcon#*before write, iclass 33, count 0 2006.285.07:03:53.12#ibcon#enter sib2, iclass 33, count 0 2006.285.07:03:53.12#ibcon#flushed, iclass 33, count 0 2006.285.07:03:53.12#ibcon#about to write, iclass 33, count 0 2006.285.07:03:53.12#ibcon#wrote, iclass 33, count 0 2006.285.07:03:53.12#ibcon#about to read 3, iclass 33, count 0 2006.285.07:03:53.15#abcon#<5=/05 3.8 6.5 24.27 741014.2\r\n> 2006.285.07:03:53.16#ibcon#read 3, iclass 33, count 0 2006.285.07:03:53.16#ibcon#about to read 4, iclass 33, count 0 2006.285.07:03:53.16#ibcon#read 4, iclass 33, count 0 2006.285.07:03:53.16#ibcon#about to read 5, iclass 33, count 0 2006.285.07:03:53.16#ibcon#read 5, iclass 33, count 0 2006.285.07:03:53.16#ibcon#about to read 6, iclass 33, count 0 2006.285.07:03:53.16#ibcon#read 6, iclass 33, count 0 2006.285.07:03:53.16#ibcon#end of sib2, iclass 33, count 0 2006.285.07:03:53.16#ibcon#*after write, iclass 33, count 0 2006.285.07:03:53.16#ibcon#*before return 0, iclass 33, count 0 2006.285.07:03:53.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:03:53.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:03:53.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:03:53.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:03:53.16$vck44/vb=4,5 2006.285.07:03:53.16#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.07:03:53.16#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.07:03:53.16#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:53.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:03:53.17#abcon#{5=INTERFACE CLEAR} 2006.285.07:03:53.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:03:53.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:03:53.22#ibcon#enter wrdev, iclass 38, count 2 2006.285.07:03:53.22#ibcon#first serial, iclass 38, count 2 2006.285.07:03:53.22#ibcon#enter sib2, iclass 38, count 2 2006.285.07:03:53.22#ibcon#flushed, iclass 38, count 2 2006.285.07:03:53.22#ibcon#about to write, iclass 38, count 2 2006.285.07:03:53.22#ibcon#wrote, iclass 38, count 2 2006.285.07:03:53.22#ibcon#about to read 3, iclass 38, count 2 2006.285.07:03:53.23#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:03:53.24#ibcon#read 3, iclass 38, count 2 2006.285.07:03:53.24#ibcon#about to read 4, iclass 38, count 2 2006.285.07:03:53.24#ibcon#read 4, iclass 38, count 2 2006.285.07:03:53.24#ibcon#about to read 5, iclass 38, count 2 2006.285.07:03:53.24#ibcon#read 5, iclass 38, count 2 2006.285.07:03:53.24#ibcon#about to read 6, iclass 38, count 2 2006.285.07:03:53.24#ibcon#read 6, iclass 38, count 2 2006.285.07:03:53.24#ibcon#end of sib2, iclass 38, count 2 2006.285.07:03:53.24#ibcon#*mode == 0, iclass 38, count 2 2006.285.07:03:53.24#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.07:03:53.24#ibcon#[27=AT04-05\r\n] 2006.285.07:03:53.24#ibcon#*before write, iclass 38, count 2 2006.285.07:03:53.24#ibcon#enter sib2, iclass 38, count 2 2006.285.07:03:53.24#ibcon#flushed, iclass 38, count 2 2006.285.07:03:53.24#ibcon#about to write, iclass 38, count 2 2006.285.07:03:53.24#ibcon#wrote, iclass 38, count 2 2006.285.07:03:53.24#ibcon#about to read 3, iclass 38, count 2 2006.285.07:03:53.27#ibcon#read 3, iclass 38, count 2 2006.285.07:03:53.27#ibcon#about to read 4, iclass 38, count 2 2006.285.07:03:53.27#ibcon#read 4, iclass 38, count 2 2006.285.07:03:53.27#ibcon#about to read 5, iclass 38, count 2 2006.285.07:03:53.27#ibcon#read 5, iclass 38, count 2 2006.285.07:03:53.27#ibcon#about to read 6, iclass 38, count 2 2006.285.07:03:53.27#ibcon#read 6, iclass 38, count 2 2006.285.07:03:53.27#ibcon#end of sib2, iclass 38, count 2 2006.285.07:03:53.27#ibcon#*after write, iclass 38, count 2 2006.285.07:03:53.27#ibcon#*before return 0, iclass 38, count 2 2006.285.07:03:53.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:03:53.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:03:53.27#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.07:03:53.27#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:53.27#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:03:53.39#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:03:53.39#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:03:53.39#ibcon#enter wrdev, iclass 38, count 0 2006.285.07:03:53.39#ibcon#first serial, iclass 38, count 0 2006.285.07:03:53.39#ibcon#enter sib2, iclass 38, count 0 2006.285.07:03:53.39#ibcon#flushed, iclass 38, count 0 2006.285.07:03:53.39#ibcon#about to write, iclass 38, count 0 2006.285.07:03:53.39#ibcon#wrote, iclass 38, count 0 2006.285.07:03:53.39#ibcon#about to read 3, iclass 38, count 0 2006.285.07:03:53.41#ibcon#read 3, iclass 38, count 0 2006.285.07:03:53.41#ibcon#about to read 4, iclass 38, count 0 2006.285.07:03:53.41#ibcon#read 4, iclass 38, count 0 2006.285.07:03:53.41#ibcon#about to read 5, iclass 38, count 0 2006.285.07:03:53.41#ibcon#read 5, iclass 38, count 0 2006.285.07:03:53.41#ibcon#about to read 6, iclass 38, count 0 2006.285.07:03:53.41#ibcon#read 6, iclass 38, count 0 2006.285.07:03:53.41#ibcon#end of sib2, iclass 38, count 0 2006.285.07:03:53.41#ibcon#*mode == 0, iclass 38, count 0 2006.285.07:03:53.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.07:03:53.41#ibcon#[27=USB\r\n] 2006.285.07:03:53.41#ibcon#*before write, iclass 38, count 0 2006.285.07:03:53.41#ibcon#enter sib2, iclass 38, count 0 2006.285.07:03:53.41#ibcon#flushed, iclass 38, count 0 2006.285.07:03:53.41#ibcon#about to write, iclass 38, count 0 2006.285.07:03:53.41#ibcon#wrote, iclass 38, count 0 2006.285.07:03:53.41#ibcon#about to read 3, iclass 38, count 0 2006.285.07:03:53.44#ibcon#read 3, iclass 38, count 0 2006.285.07:03:53.44#ibcon#about to read 4, iclass 38, count 0 2006.285.07:03:53.44#ibcon#read 4, iclass 38, count 0 2006.285.07:03:53.44#ibcon#about to read 5, iclass 38, count 0 2006.285.07:03:53.44#ibcon#read 5, iclass 38, count 0 2006.285.07:03:53.44#ibcon#about to read 6, iclass 38, count 0 2006.285.07:03:53.44#ibcon#read 6, iclass 38, count 0 2006.285.07:03:53.44#ibcon#end of sib2, iclass 38, count 0 2006.285.07:03:53.44#ibcon#*after write, iclass 38, count 0 2006.285.07:03:53.44#ibcon#*before return 0, iclass 38, count 0 2006.285.07:03:53.44#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:03:53.44#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:03:53.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.07:03:53.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.07:03:53.44$vck44/vblo=5,709.99 2006.285.07:03:53.44#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.07:03:53.44#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.07:03:53.44#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:53.44#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:03:53.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:03:53.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:03:53.44#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:03:53.44#ibcon#first serial, iclass 3, count 0 2006.285.07:03:53.44#ibcon#enter sib2, iclass 3, count 0 2006.285.07:03:53.44#ibcon#flushed, iclass 3, count 0 2006.285.07:03:53.44#ibcon#about to write, iclass 3, count 0 2006.285.07:03:53.45#ibcon#wrote, iclass 3, count 0 2006.285.07:03:53.45#ibcon#about to read 3, iclass 3, count 0 2006.285.07:03:53.46#ibcon#read 3, iclass 3, count 0 2006.285.07:03:53.46#ibcon#about to read 4, iclass 3, count 0 2006.285.07:03:53.46#ibcon#read 4, iclass 3, count 0 2006.285.07:03:53.46#ibcon#about to read 5, iclass 3, count 0 2006.285.07:03:53.46#ibcon#read 5, iclass 3, count 0 2006.285.07:03:53.46#ibcon#about to read 6, iclass 3, count 0 2006.285.07:03:53.46#ibcon#read 6, iclass 3, count 0 2006.285.07:03:53.46#ibcon#end of sib2, iclass 3, count 0 2006.285.07:03:53.46#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:03:53.46#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:03:53.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:03:53.46#ibcon#*before write, iclass 3, count 0 2006.285.07:03:53.46#ibcon#enter sib2, iclass 3, count 0 2006.285.07:03:53.46#ibcon#flushed, iclass 3, count 0 2006.285.07:03:53.46#ibcon#about to write, iclass 3, count 0 2006.285.07:03:53.46#ibcon#wrote, iclass 3, count 0 2006.285.07:03:53.46#ibcon#about to read 3, iclass 3, count 0 2006.285.07:03:53.50#ibcon#read 3, iclass 3, count 0 2006.285.07:03:53.50#ibcon#about to read 4, iclass 3, count 0 2006.285.07:03:53.50#ibcon#read 4, iclass 3, count 0 2006.285.07:03:53.50#ibcon#about to read 5, iclass 3, count 0 2006.285.07:03:53.50#ibcon#read 5, iclass 3, count 0 2006.285.07:03:53.50#ibcon#about to read 6, iclass 3, count 0 2006.285.07:03:53.50#ibcon#read 6, iclass 3, count 0 2006.285.07:03:53.50#ibcon#end of sib2, iclass 3, count 0 2006.285.07:03:53.50#ibcon#*after write, iclass 3, count 0 2006.285.07:03:53.50#ibcon#*before return 0, iclass 3, count 0 2006.285.07:03:53.50#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:03:53.50#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:03:53.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:03:53.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:03:53.50$vck44/vb=5,4 2006.285.07:03:53.50#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.07:03:53.50#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.07:03:53.50#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:53.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:03:53.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:03:53.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:03:53.56#ibcon#enter wrdev, iclass 5, count 2 2006.285.07:03:53.56#ibcon#first serial, iclass 5, count 2 2006.285.07:03:53.56#ibcon#enter sib2, iclass 5, count 2 2006.285.07:03:53.56#ibcon#flushed, iclass 5, count 2 2006.285.07:03:53.56#ibcon#about to write, iclass 5, count 2 2006.285.07:03:53.56#ibcon#wrote, iclass 5, count 2 2006.285.07:03:53.56#ibcon#about to read 3, iclass 5, count 2 2006.285.07:03:53.58#ibcon#read 3, iclass 5, count 2 2006.285.07:03:53.58#ibcon#about to read 4, iclass 5, count 2 2006.285.07:03:53.58#ibcon#read 4, iclass 5, count 2 2006.285.07:03:53.58#ibcon#about to read 5, iclass 5, count 2 2006.285.07:03:53.58#ibcon#read 5, iclass 5, count 2 2006.285.07:03:53.58#ibcon#about to read 6, iclass 5, count 2 2006.285.07:03:53.58#ibcon#read 6, iclass 5, count 2 2006.285.07:03:53.58#ibcon#end of sib2, iclass 5, count 2 2006.285.07:03:53.58#ibcon#*mode == 0, iclass 5, count 2 2006.285.07:03:53.58#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.07:03:53.58#ibcon#[27=AT05-04\r\n] 2006.285.07:03:53.58#ibcon#*before write, iclass 5, count 2 2006.285.07:03:53.58#ibcon#enter sib2, iclass 5, count 2 2006.285.07:03:53.58#ibcon#flushed, iclass 5, count 2 2006.285.07:03:53.58#ibcon#about to write, iclass 5, count 2 2006.285.07:03:53.58#ibcon#wrote, iclass 5, count 2 2006.285.07:03:53.58#ibcon#about to read 3, iclass 5, count 2 2006.285.07:03:53.61#ibcon#read 3, iclass 5, count 2 2006.285.07:03:53.61#ibcon#about to read 4, iclass 5, count 2 2006.285.07:03:53.61#ibcon#read 4, iclass 5, count 2 2006.285.07:03:53.61#ibcon#about to read 5, iclass 5, count 2 2006.285.07:03:53.61#ibcon#read 5, iclass 5, count 2 2006.285.07:03:53.61#ibcon#about to read 6, iclass 5, count 2 2006.285.07:03:53.61#ibcon#read 6, iclass 5, count 2 2006.285.07:03:53.61#ibcon#end of sib2, iclass 5, count 2 2006.285.07:03:53.61#ibcon#*after write, iclass 5, count 2 2006.285.07:03:53.61#ibcon#*before return 0, iclass 5, count 2 2006.285.07:03:53.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:03:53.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:03:53.61#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.07:03:53.61#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:53.61#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:03:53.73#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:03:53.73#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:03:53.73#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:03:53.73#ibcon#first serial, iclass 5, count 0 2006.285.07:03:53.73#ibcon#enter sib2, iclass 5, count 0 2006.285.07:03:53.73#ibcon#flushed, iclass 5, count 0 2006.285.07:03:53.73#ibcon#about to write, iclass 5, count 0 2006.285.07:03:53.73#ibcon#wrote, iclass 5, count 0 2006.285.07:03:53.73#ibcon#about to read 3, iclass 5, count 0 2006.285.07:03:53.75#ibcon#read 3, iclass 5, count 0 2006.285.07:03:53.75#ibcon#about to read 4, iclass 5, count 0 2006.285.07:03:53.75#ibcon#read 4, iclass 5, count 0 2006.285.07:03:53.75#ibcon#about to read 5, iclass 5, count 0 2006.285.07:03:53.75#ibcon#read 5, iclass 5, count 0 2006.285.07:03:53.75#ibcon#about to read 6, iclass 5, count 0 2006.285.07:03:53.75#ibcon#read 6, iclass 5, count 0 2006.285.07:03:53.75#ibcon#end of sib2, iclass 5, count 0 2006.285.07:03:53.75#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:03:53.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:03:53.75#ibcon#[27=USB\r\n] 2006.285.07:03:53.75#ibcon#*before write, iclass 5, count 0 2006.285.07:03:53.75#ibcon#enter sib2, iclass 5, count 0 2006.285.07:03:53.75#ibcon#flushed, iclass 5, count 0 2006.285.07:03:53.75#ibcon#about to write, iclass 5, count 0 2006.285.07:03:53.75#ibcon#wrote, iclass 5, count 0 2006.285.07:03:53.75#ibcon#about to read 3, iclass 5, count 0 2006.285.07:03:53.78#ibcon#read 3, iclass 5, count 0 2006.285.07:03:53.78#ibcon#about to read 4, iclass 5, count 0 2006.285.07:03:53.78#ibcon#read 4, iclass 5, count 0 2006.285.07:03:53.78#ibcon#about to read 5, iclass 5, count 0 2006.285.07:03:53.78#ibcon#read 5, iclass 5, count 0 2006.285.07:03:53.78#ibcon#about to read 6, iclass 5, count 0 2006.285.07:03:53.78#ibcon#read 6, iclass 5, count 0 2006.285.07:03:53.78#ibcon#end of sib2, iclass 5, count 0 2006.285.07:03:53.78#ibcon#*after write, iclass 5, count 0 2006.285.07:03:53.78#ibcon#*before return 0, iclass 5, count 0 2006.285.07:03:53.78#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:03:53.78#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:03:53.78#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:03:53.78#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:03:53.78$vck44/vblo=6,719.99 2006.285.07:03:53.78#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.07:03:53.78#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.07:03:53.78#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:53.78#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:03:53.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:03:53.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:03:53.78#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:03:53.78#ibcon#first serial, iclass 7, count 0 2006.285.07:03:53.78#ibcon#enter sib2, iclass 7, count 0 2006.285.07:03:53.78#ibcon#flushed, iclass 7, count 0 2006.285.07:03:53.78#ibcon#about to write, iclass 7, count 0 2006.285.07:03:53.79#ibcon#wrote, iclass 7, count 0 2006.285.07:03:53.79#ibcon#about to read 3, iclass 7, count 0 2006.285.07:03:53.80#ibcon#read 3, iclass 7, count 0 2006.285.07:03:53.80#ibcon#about to read 4, iclass 7, count 0 2006.285.07:03:53.80#ibcon#read 4, iclass 7, count 0 2006.285.07:03:53.80#ibcon#about to read 5, iclass 7, count 0 2006.285.07:03:53.80#ibcon#read 5, iclass 7, count 0 2006.285.07:03:53.80#ibcon#about to read 6, iclass 7, count 0 2006.285.07:03:53.80#ibcon#read 6, iclass 7, count 0 2006.285.07:03:53.80#ibcon#end of sib2, iclass 7, count 0 2006.285.07:03:53.80#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:03:53.80#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:03:53.80#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:03:53.80#ibcon#*before write, iclass 7, count 0 2006.285.07:03:53.80#ibcon#enter sib2, iclass 7, count 0 2006.285.07:03:53.80#ibcon#flushed, iclass 7, count 0 2006.285.07:03:53.80#ibcon#about to write, iclass 7, count 0 2006.285.07:03:53.80#ibcon#wrote, iclass 7, count 0 2006.285.07:03:53.80#ibcon#about to read 3, iclass 7, count 0 2006.285.07:03:53.84#ibcon#read 3, iclass 7, count 0 2006.285.07:03:53.84#ibcon#about to read 4, iclass 7, count 0 2006.285.07:03:53.84#ibcon#read 4, iclass 7, count 0 2006.285.07:03:53.84#ibcon#about to read 5, iclass 7, count 0 2006.285.07:03:53.84#ibcon#read 5, iclass 7, count 0 2006.285.07:03:53.84#ibcon#about to read 6, iclass 7, count 0 2006.285.07:03:53.84#ibcon#read 6, iclass 7, count 0 2006.285.07:03:53.84#ibcon#end of sib2, iclass 7, count 0 2006.285.07:03:53.84#ibcon#*after write, iclass 7, count 0 2006.285.07:03:53.84#ibcon#*before return 0, iclass 7, count 0 2006.285.07:03:53.84#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:03:53.84#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:03:53.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:03:53.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:03:53.84$vck44/vb=6,3 2006.285.07:03:53.84#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.07:03:53.84#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.07:03:53.84#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:53.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:03:53.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:03:53.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:03:53.90#ibcon#enter wrdev, iclass 11, count 2 2006.285.07:03:53.90#ibcon#first serial, iclass 11, count 2 2006.285.07:03:53.90#ibcon#enter sib2, iclass 11, count 2 2006.285.07:03:53.90#ibcon#flushed, iclass 11, count 2 2006.285.07:03:53.90#ibcon#about to write, iclass 11, count 2 2006.285.07:03:53.90#ibcon#wrote, iclass 11, count 2 2006.285.07:03:53.90#ibcon#about to read 3, iclass 11, count 2 2006.285.07:03:53.92#ibcon#read 3, iclass 11, count 2 2006.285.07:03:53.92#ibcon#about to read 4, iclass 11, count 2 2006.285.07:03:53.92#ibcon#read 4, iclass 11, count 2 2006.285.07:03:53.92#ibcon#about to read 5, iclass 11, count 2 2006.285.07:03:53.92#ibcon#read 5, iclass 11, count 2 2006.285.07:03:53.92#ibcon#about to read 6, iclass 11, count 2 2006.285.07:03:53.92#ibcon#read 6, iclass 11, count 2 2006.285.07:03:53.92#ibcon#end of sib2, iclass 11, count 2 2006.285.07:03:53.92#ibcon#*mode == 0, iclass 11, count 2 2006.285.07:03:53.92#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.07:03:53.92#ibcon#[27=AT06-03\r\n] 2006.285.07:03:53.92#ibcon#*before write, iclass 11, count 2 2006.285.07:03:53.92#ibcon#enter sib2, iclass 11, count 2 2006.285.07:03:53.92#ibcon#flushed, iclass 11, count 2 2006.285.07:03:53.92#ibcon#about to write, iclass 11, count 2 2006.285.07:03:53.92#ibcon#wrote, iclass 11, count 2 2006.285.07:03:53.92#ibcon#about to read 3, iclass 11, count 2 2006.285.07:03:53.95#ibcon#read 3, iclass 11, count 2 2006.285.07:03:53.95#ibcon#about to read 4, iclass 11, count 2 2006.285.07:03:53.95#ibcon#read 4, iclass 11, count 2 2006.285.07:03:53.95#ibcon#about to read 5, iclass 11, count 2 2006.285.07:03:53.95#ibcon#read 5, iclass 11, count 2 2006.285.07:03:53.95#ibcon#about to read 6, iclass 11, count 2 2006.285.07:03:53.95#ibcon#read 6, iclass 11, count 2 2006.285.07:03:53.95#ibcon#end of sib2, iclass 11, count 2 2006.285.07:03:53.95#ibcon#*after write, iclass 11, count 2 2006.285.07:03:53.95#ibcon#*before return 0, iclass 11, count 2 2006.285.07:03:53.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:03:53.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:03:53.95#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.07:03:53.95#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:53.95#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:03:54.07#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:03:54.07#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:03:54.07#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:03:54.07#ibcon#first serial, iclass 11, count 0 2006.285.07:03:54.07#ibcon#enter sib2, iclass 11, count 0 2006.285.07:03:54.07#ibcon#flushed, iclass 11, count 0 2006.285.07:03:54.07#ibcon#about to write, iclass 11, count 0 2006.285.07:03:54.07#ibcon#wrote, iclass 11, count 0 2006.285.07:03:54.07#ibcon#about to read 3, iclass 11, count 0 2006.285.07:03:54.09#ibcon#read 3, iclass 11, count 0 2006.285.07:03:54.09#ibcon#about to read 4, iclass 11, count 0 2006.285.07:03:54.09#ibcon#read 4, iclass 11, count 0 2006.285.07:03:54.09#ibcon#about to read 5, iclass 11, count 0 2006.285.07:03:54.09#ibcon#read 5, iclass 11, count 0 2006.285.07:03:54.09#ibcon#about to read 6, iclass 11, count 0 2006.285.07:03:54.09#ibcon#read 6, iclass 11, count 0 2006.285.07:03:54.09#ibcon#end of sib2, iclass 11, count 0 2006.285.07:03:54.09#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:03:54.09#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:03:54.09#ibcon#[27=USB\r\n] 2006.285.07:03:54.09#ibcon#*before write, iclass 11, count 0 2006.285.07:03:54.09#ibcon#enter sib2, iclass 11, count 0 2006.285.07:03:54.09#ibcon#flushed, iclass 11, count 0 2006.285.07:03:54.09#ibcon#about to write, iclass 11, count 0 2006.285.07:03:54.09#ibcon#wrote, iclass 11, count 0 2006.285.07:03:54.09#ibcon#about to read 3, iclass 11, count 0 2006.285.07:03:54.12#ibcon#read 3, iclass 11, count 0 2006.285.07:03:54.12#ibcon#about to read 4, iclass 11, count 0 2006.285.07:03:54.12#ibcon#read 4, iclass 11, count 0 2006.285.07:03:54.12#ibcon#about to read 5, iclass 11, count 0 2006.285.07:03:54.12#ibcon#read 5, iclass 11, count 0 2006.285.07:03:54.12#ibcon#about to read 6, iclass 11, count 0 2006.285.07:03:54.12#ibcon#read 6, iclass 11, count 0 2006.285.07:03:54.12#ibcon#end of sib2, iclass 11, count 0 2006.285.07:03:54.12#ibcon#*after write, iclass 11, count 0 2006.285.07:03:54.12#ibcon#*before return 0, iclass 11, count 0 2006.285.07:03:54.12#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:03:54.12#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:03:54.12#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:03:54.12#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:03:54.12$vck44/vblo=7,734.99 2006.285.07:03:54.12#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.07:03:54.12#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.07:03:54.12#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:54.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:03:54.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:03:54.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:03:54.12#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:03:54.12#ibcon#first serial, iclass 13, count 0 2006.285.07:03:54.12#ibcon#enter sib2, iclass 13, count 0 2006.285.07:03:54.12#ibcon#flushed, iclass 13, count 0 2006.285.07:03:54.12#ibcon#about to write, iclass 13, count 0 2006.285.07:03:54.13#ibcon#wrote, iclass 13, count 0 2006.285.07:03:54.13#ibcon#about to read 3, iclass 13, count 0 2006.285.07:03:54.14#ibcon#read 3, iclass 13, count 0 2006.285.07:03:54.14#ibcon#about to read 4, iclass 13, count 0 2006.285.07:03:54.14#ibcon#read 4, iclass 13, count 0 2006.285.07:03:54.14#ibcon#about to read 5, iclass 13, count 0 2006.285.07:03:54.14#ibcon#read 5, iclass 13, count 0 2006.285.07:03:54.14#ibcon#about to read 6, iclass 13, count 0 2006.285.07:03:54.14#ibcon#read 6, iclass 13, count 0 2006.285.07:03:54.14#ibcon#end of sib2, iclass 13, count 0 2006.285.07:03:54.14#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:03:54.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:03:54.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:03:54.15#ibcon#*before write, iclass 13, count 0 2006.285.07:03:54.15#ibcon#enter sib2, iclass 13, count 0 2006.285.07:03:54.15#ibcon#flushed, iclass 13, count 0 2006.285.07:03:54.15#ibcon#about to write, iclass 13, count 0 2006.285.07:03:54.15#ibcon#wrote, iclass 13, count 0 2006.285.07:03:54.15#ibcon#about to read 3, iclass 13, count 0 2006.285.07:03:54.18#ibcon#read 3, iclass 13, count 0 2006.285.07:03:54.18#ibcon#about to read 4, iclass 13, count 0 2006.285.07:03:54.18#ibcon#read 4, iclass 13, count 0 2006.285.07:03:54.18#ibcon#about to read 5, iclass 13, count 0 2006.285.07:03:54.18#ibcon#read 5, iclass 13, count 0 2006.285.07:03:54.18#ibcon#about to read 6, iclass 13, count 0 2006.285.07:03:54.18#ibcon#read 6, iclass 13, count 0 2006.285.07:03:54.18#ibcon#end of sib2, iclass 13, count 0 2006.285.07:03:54.18#ibcon#*after write, iclass 13, count 0 2006.285.07:03:54.18#ibcon#*before return 0, iclass 13, count 0 2006.285.07:03:54.18#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:03:54.18#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:03:54.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:03:54.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:03:54.18$vck44/vb=7,4 2006.285.07:03:54.18#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.07:03:54.18#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.07:03:54.18#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:54.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:03:54.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:03:54.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:03:54.24#ibcon#enter wrdev, iclass 15, count 2 2006.285.07:03:54.24#ibcon#first serial, iclass 15, count 2 2006.285.07:03:54.24#ibcon#enter sib2, iclass 15, count 2 2006.285.07:03:54.24#ibcon#flushed, iclass 15, count 2 2006.285.07:03:54.24#ibcon#about to write, iclass 15, count 2 2006.285.07:03:54.24#ibcon#wrote, iclass 15, count 2 2006.285.07:03:54.24#ibcon#about to read 3, iclass 15, count 2 2006.285.07:03:54.26#ibcon#read 3, iclass 15, count 2 2006.285.07:03:54.26#ibcon#about to read 4, iclass 15, count 2 2006.285.07:03:54.26#ibcon#read 4, iclass 15, count 2 2006.285.07:03:54.26#ibcon#about to read 5, iclass 15, count 2 2006.285.07:03:54.26#ibcon#read 5, iclass 15, count 2 2006.285.07:03:54.26#ibcon#about to read 6, iclass 15, count 2 2006.285.07:03:54.26#ibcon#read 6, iclass 15, count 2 2006.285.07:03:54.26#ibcon#end of sib2, iclass 15, count 2 2006.285.07:03:54.26#ibcon#*mode == 0, iclass 15, count 2 2006.285.07:03:54.26#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.07:03:54.26#ibcon#[27=AT07-04\r\n] 2006.285.07:03:54.26#ibcon#*before write, iclass 15, count 2 2006.285.07:03:54.26#ibcon#enter sib2, iclass 15, count 2 2006.285.07:03:54.26#ibcon#flushed, iclass 15, count 2 2006.285.07:03:54.26#ibcon#about to write, iclass 15, count 2 2006.285.07:03:54.26#ibcon#wrote, iclass 15, count 2 2006.285.07:03:54.26#ibcon#about to read 3, iclass 15, count 2 2006.285.07:03:54.29#ibcon#read 3, iclass 15, count 2 2006.285.07:03:54.29#ibcon#about to read 4, iclass 15, count 2 2006.285.07:03:54.29#ibcon#read 4, iclass 15, count 2 2006.285.07:03:54.29#ibcon#about to read 5, iclass 15, count 2 2006.285.07:03:54.29#ibcon#read 5, iclass 15, count 2 2006.285.07:03:54.29#ibcon#about to read 6, iclass 15, count 2 2006.285.07:03:54.29#ibcon#read 6, iclass 15, count 2 2006.285.07:03:54.29#ibcon#end of sib2, iclass 15, count 2 2006.285.07:03:54.29#ibcon#*after write, iclass 15, count 2 2006.285.07:03:54.29#ibcon#*before return 0, iclass 15, count 2 2006.285.07:03:54.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:03:54.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:03:54.29#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.07:03:54.29#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:54.29#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:03:54.41#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:03:54.41#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:03:54.41#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:03:54.41#ibcon#first serial, iclass 15, count 0 2006.285.07:03:54.41#ibcon#enter sib2, iclass 15, count 0 2006.285.07:03:54.41#ibcon#flushed, iclass 15, count 0 2006.285.07:03:54.41#ibcon#about to write, iclass 15, count 0 2006.285.07:03:54.41#ibcon#wrote, iclass 15, count 0 2006.285.07:03:54.41#ibcon#about to read 3, iclass 15, count 0 2006.285.07:03:54.43#ibcon#read 3, iclass 15, count 0 2006.285.07:03:54.43#ibcon#about to read 4, iclass 15, count 0 2006.285.07:03:54.43#ibcon#read 4, iclass 15, count 0 2006.285.07:03:54.43#ibcon#about to read 5, iclass 15, count 0 2006.285.07:03:54.43#ibcon#read 5, iclass 15, count 0 2006.285.07:03:54.43#ibcon#about to read 6, iclass 15, count 0 2006.285.07:03:54.43#ibcon#read 6, iclass 15, count 0 2006.285.07:03:54.43#ibcon#end of sib2, iclass 15, count 0 2006.285.07:03:54.43#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:03:54.43#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:03:54.43#ibcon#[27=USB\r\n] 2006.285.07:03:54.43#ibcon#*before write, iclass 15, count 0 2006.285.07:03:54.43#ibcon#enter sib2, iclass 15, count 0 2006.285.07:03:54.43#ibcon#flushed, iclass 15, count 0 2006.285.07:03:54.43#ibcon#about to write, iclass 15, count 0 2006.285.07:03:54.43#ibcon#wrote, iclass 15, count 0 2006.285.07:03:54.43#ibcon#about to read 3, iclass 15, count 0 2006.285.07:03:54.46#ibcon#read 3, iclass 15, count 0 2006.285.07:03:54.46#ibcon#about to read 4, iclass 15, count 0 2006.285.07:03:54.46#ibcon#read 4, iclass 15, count 0 2006.285.07:03:54.46#ibcon#about to read 5, iclass 15, count 0 2006.285.07:03:54.46#ibcon#read 5, iclass 15, count 0 2006.285.07:03:54.46#ibcon#about to read 6, iclass 15, count 0 2006.285.07:03:54.46#ibcon#read 6, iclass 15, count 0 2006.285.07:03:54.46#ibcon#end of sib2, iclass 15, count 0 2006.285.07:03:54.46#ibcon#*after write, iclass 15, count 0 2006.285.07:03:54.46#ibcon#*before return 0, iclass 15, count 0 2006.285.07:03:54.46#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:03:54.46#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:03:54.46#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:03:54.46#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:03:54.46$vck44/vblo=8,744.99 2006.285.07:03:54.46#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.07:03:54.46#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.07:03:54.46#ibcon#ireg 17 cls_cnt 0 2006.285.07:03:54.46#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:03:54.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:03:54.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:03:54.46#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:03:54.46#ibcon#first serial, iclass 17, count 0 2006.285.07:03:54.46#ibcon#enter sib2, iclass 17, count 0 2006.285.07:03:54.46#ibcon#flushed, iclass 17, count 0 2006.285.07:03:54.46#ibcon#about to write, iclass 17, count 0 2006.285.07:03:54.47#ibcon#wrote, iclass 17, count 0 2006.285.07:03:54.47#ibcon#about to read 3, iclass 17, count 0 2006.285.07:03:54.48#ibcon#read 3, iclass 17, count 0 2006.285.07:03:54.48#ibcon#about to read 4, iclass 17, count 0 2006.285.07:03:54.48#ibcon#read 4, iclass 17, count 0 2006.285.07:03:54.48#ibcon#about to read 5, iclass 17, count 0 2006.285.07:03:54.48#ibcon#read 5, iclass 17, count 0 2006.285.07:03:54.48#ibcon#about to read 6, iclass 17, count 0 2006.285.07:03:54.48#ibcon#read 6, iclass 17, count 0 2006.285.07:03:54.48#ibcon#end of sib2, iclass 17, count 0 2006.285.07:03:54.48#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:03:54.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:03:54.48#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:03:54.48#ibcon#*before write, iclass 17, count 0 2006.285.07:03:54.48#ibcon#enter sib2, iclass 17, count 0 2006.285.07:03:54.48#ibcon#flushed, iclass 17, count 0 2006.285.07:03:54.48#ibcon#about to write, iclass 17, count 0 2006.285.07:03:54.48#ibcon#wrote, iclass 17, count 0 2006.285.07:03:54.48#ibcon#about to read 3, iclass 17, count 0 2006.285.07:03:54.52#ibcon#read 3, iclass 17, count 0 2006.285.07:03:54.52#ibcon#about to read 4, iclass 17, count 0 2006.285.07:03:54.52#ibcon#read 4, iclass 17, count 0 2006.285.07:03:54.52#ibcon#about to read 5, iclass 17, count 0 2006.285.07:03:54.52#ibcon#read 5, iclass 17, count 0 2006.285.07:03:54.52#ibcon#about to read 6, iclass 17, count 0 2006.285.07:03:54.52#ibcon#read 6, iclass 17, count 0 2006.285.07:03:54.52#ibcon#end of sib2, iclass 17, count 0 2006.285.07:03:54.52#ibcon#*after write, iclass 17, count 0 2006.285.07:03:54.52#ibcon#*before return 0, iclass 17, count 0 2006.285.07:03:54.52#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:03:54.52#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:03:54.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:03:54.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:03:54.52$vck44/vb=8,4 2006.285.07:03:54.52#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.07:03:54.52#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.07:03:54.52#ibcon#ireg 11 cls_cnt 2 2006.285.07:03:54.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:03:54.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:03:54.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:03:54.58#ibcon#enter wrdev, iclass 19, count 2 2006.285.07:03:54.58#ibcon#first serial, iclass 19, count 2 2006.285.07:03:54.58#ibcon#enter sib2, iclass 19, count 2 2006.285.07:03:54.58#ibcon#flushed, iclass 19, count 2 2006.285.07:03:54.58#ibcon#about to write, iclass 19, count 2 2006.285.07:03:54.58#ibcon#wrote, iclass 19, count 2 2006.285.07:03:54.58#ibcon#about to read 3, iclass 19, count 2 2006.285.07:03:54.60#ibcon#read 3, iclass 19, count 2 2006.285.07:03:54.60#ibcon#about to read 4, iclass 19, count 2 2006.285.07:03:54.60#ibcon#read 4, iclass 19, count 2 2006.285.07:03:54.60#ibcon#about to read 5, iclass 19, count 2 2006.285.07:03:54.60#ibcon#read 5, iclass 19, count 2 2006.285.07:03:54.60#ibcon#about to read 6, iclass 19, count 2 2006.285.07:03:54.60#ibcon#read 6, iclass 19, count 2 2006.285.07:03:54.60#ibcon#end of sib2, iclass 19, count 2 2006.285.07:03:54.60#ibcon#*mode == 0, iclass 19, count 2 2006.285.07:03:54.60#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.07:03:54.60#ibcon#[27=AT08-04\r\n] 2006.285.07:03:54.60#ibcon#*before write, iclass 19, count 2 2006.285.07:03:54.60#ibcon#enter sib2, iclass 19, count 2 2006.285.07:03:54.60#ibcon#flushed, iclass 19, count 2 2006.285.07:03:54.60#ibcon#about to write, iclass 19, count 2 2006.285.07:03:54.60#ibcon#wrote, iclass 19, count 2 2006.285.07:03:54.60#ibcon#about to read 3, iclass 19, count 2 2006.285.07:03:54.63#ibcon#read 3, iclass 19, count 2 2006.285.07:03:54.63#ibcon#about to read 4, iclass 19, count 2 2006.285.07:03:54.63#ibcon#read 4, iclass 19, count 2 2006.285.07:03:54.63#ibcon#about to read 5, iclass 19, count 2 2006.285.07:03:54.63#ibcon#read 5, iclass 19, count 2 2006.285.07:03:54.63#ibcon#about to read 6, iclass 19, count 2 2006.285.07:03:54.63#ibcon#read 6, iclass 19, count 2 2006.285.07:03:54.63#ibcon#end of sib2, iclass 19, count 2 2006.285.07:03:54.63#ibcon#*after write, iclass 19, count 2 2006.285.07:03:54.63#ibcon#*before return 0, iclass 19, count 2 2006.285.07:03:54.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:03:54.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:03:54.63#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.07:03:54.63#ibcon#ireg 7 cls_cnt 0 2006.285.07:03:54.63#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:03:54.75#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:03:54.75#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:03:54.75#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:03:54.75#ibcon#first serial, iclass 19, count 0 2006.285.07:03:54.75#ibcon#enter sib2, iclass 19, count 0 2006.285.07:03:54.75#ibcon#flushed, iclass 19, count 0 2006.285.07:03:54.75#ibcon#about to write, iclass 19, count 0 2006.285.07:03:54.75#ibcon#wrote, iclass 19, count 0 2006.285.07:03:54.75#ibcon#about to read 3, iclass 19, count 0 2006.285.07:03:54.77#ibcon#read 3, iclass 19, count 0 2006.285.07:03:54.77#ibcon#about to read 4, iclass 19, count 0 2006.285.07:03:54.77#ibcon#read 4, iclass 19, count 0 2006.285.07:03:54.77#ibcon#about to read 5, iclass 19, count 0 2006.285.07:03:54.77#ibcon#read 5, iclass 19, count 0 2006.285.07:03:54.77#ibcon#about to read 6, iclass 19, count 0 2006.285.07:03:54.77#ibcon#read 6, iclass 19, count 0 2006.285.07:03:54.77#ibcon#end of sib2, iclass 19, count 0 2006.285.07:03:54.77#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:03:54.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:03:54.77#ibcon#[27=USB\r\n] 2006.285.07:03:54.77#ibcon#*before write, iclass 19, count 0 2006.285.07:03:54.77#ibcon#enter sib2, iclass 19, count 0 2006.285.07:03:54.77#ibcon#flushed, iclass 19, count 0 2006.285.07:03:54.77#ibcon#about to write, iclass 19, count 0 2006.285.07:03:54.77#ibcon#wrote, iclass 19, count 0 2006.285.07:03:54.77#ibcon#about to read 3, iclass 19, count 0 2006.285.07:03:54.80#ibcon#read 3, iclass 19, count 0 2006.285.07:03:54.80#ibcon#about to read 4, iclass 19, count 0 2006.285.07:03:54.80#ibcon#read 4, iclass 19, count 0 2006.285.07:03:54.80#ibcon#about to read 5, iclass 19, count 0 2006.285.07:03:54.80#ibcon#read 5, iclass 19, count 0 2006.285.07:03:54.80#ibcon#about to read 6, iclass 19, count 0 2006.285.07:03:54.80#ibcon#read 6, iclass 19, count 0 2006.285.07:03:54.80#ibcon#end of sib2, iclass 19, count 0 2006.285.07:03:54.80#ibcon#*after write, iclass 19, count 0 2006.285.07:03:54.80#ibcon#*before return 0, iclass 19, count 0 2006.285.07:03:54.80#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:03:54.80#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:03:54.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:03:54.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:03:54.80$vck44/vabw=wide 2006.285.07:03:54.80#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.07:03:54.80#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.07:03:54.80#ibcon#ireg 8 cls_cnt 0 2006.285.07:03:54.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:03:54.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:03:54.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:03:54.80#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:03:54.80#ibcon#first serial, iclass 21, count 0 2006.285.07:03:54.80#ibcon#enter sib2, iclass 21, count 0 2006.285.07:03:54.80#ibcon#flushed, iclass 21, count 0 2006.285.07:03:54.80#ibcon#about to write, iclass 21, count 0 2006.285.07:03:54.80#ibcon#wrote, iclass 21, count 0 2006.285.07:03:54.81#ibcon#about to read 3, iclass 21, count 0 2006.285.07:03:54.82#ibcon#read 3, iclass 21, count 0 2006.285.07:03:54.82#ibcon#about to read 4, iclass 21, count 0 2006.285.07:03:54.82#ibcon#read 4, iclass 21, count 0 2006.285.07:03:54.82#ibcon#about to read 5, iclass 21, count 0 2006.285.07:03:54.82#ibcon#read 5, iclass 21, count 0 2006.285.07:03:54.82#ibcon#about to read 6, iclass 21, count 0 2006.285.07:03:54.82#ibcon#read 6, iclass 21, count 0 2006.285.07:03:54.82#ibcon#end of sib2, iclass 21, count 0 2006.285.07:03:54.82#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:03:54.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:03:54.82#ibcon#[25=BW32\r\n] 2006.285.07:03:54.82#ibcon#*before write, iclass 21, count 0 2006.285.07:03:54.82#ibcon#enter sib2, iclass 21, count 0 2006.285.07:03:54.82#ibcon#flushed, iclass 21, count 0 2006.285.07:03:54.82#ibcon#about to write, iclass 21, count 0 2006.285.07:03:54.82#ibcon#wrote, iclass 21, count 0 2006.285.07:03:54.82#ibcon#about to read 3, iclass 21, count 0 2006.285.07:03:54.85#ibcon#read 3, iclass 21, count 0 2006.285.07:03:54.85#ibcon#about to read 4, iclass 21, count 0 2006.285.07:03:54.85#ibcon#read 4, iclass 21, count 0 2006.285.07:03:54.85#ibcon#about to read 5, iclass 21, count 0 2006.285.07:03:54.85#ibcon#read 5, iclass 21, count 0 2006.285.07:03:54.85#ibcon#about to read 6, iclass 21, count 0 2006.285.07:03:54.85#ibcon#read 6, iclass 21, count 0 2006.285.07:03:54.85#ibcon#end of sib2, iclass 21, count 0 2006.285.07:03:54.85#ibcon#*after write, iclass 21, count 0 2006.285.07:03:54.85#ibcon#*before return 0, iclass 21, count 0 2006.285.07:03:54.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:03:54.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:03:54.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:03:54.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:03:54.85$vck44/vbbw=wide 2006.285.07:03:54.85#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.07:03:54.85#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.07:03:54.85#ibcon#ireg 8 cls_cnt 0 2006.285.07:03:54.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:03:54.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:03:54.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:03:54.92#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:03:54.92#ibcon#first serial, iclass 23, count 0 2006.285.07:03:54.92#ibcon#enter sib2, iclass 23, count 0 2006.285.07:03:54.92#ibcon#flushed, iclass 23, count 0 2006.285.07:03:54.92#ibcon#about to write, iclass 23, count 0 2006.285.07:03:54.92#ibcon#wrote, iclass 23, count 0 2006.285.07:03:54.92#ibcon#about to read 3, iclass 23, count 0 2006.285.07:03:54.94#ibcon#read 3, iclass 23, count 0 2006.285.07:03:54.94#ibcon#about to read 4, iclass 23, count 0 2006.285.07:03:54.94#ibcon#read 4, iclass 23, count 0 2006.285.07:03:54.94#ibcon#about to read 5, iclass 23, count 0 2006.285.07:03:54.94#ibcon#read 5, iclass 23, count 0 2006.285.07:03:54.94#ibcon#about to read 6, iclass 23, count 0 2006.285.07:03:54.94#ibcon#read 6, iclass 23, count 0 2006.285.07:03:54.94#ibcon#end of sib2, iclass 23, count 0 2006.285.07:03:54.94#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:03:54.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:03:54.94#ibcon#[27=BW32\r\n] 2006.285.07:03:54.94#ibcon#*before write, iclass 23, count 0 2006.285.07:03:54.94#ibcon#enter sib2, iclass 23, count 0 2006.285.07:03:54.94#ibcon#flushed, iclass 23, count 0 2006.285.07:03:54.94#ibcon#about to write, iclass 23, count 0 2006.285.07:03:54.94#ibcon#wrote, iclass 23, count 0 2006.285.07:03:54.94#ibcon#about to read 3, iclass 23, count 0 2006.285.07:03:54.97#ibcon#read 3, iclass 23, count 0 2006.285.07:03:54.97#ibcon#about to read 4, iclass 23, count 0 2006.285.07:03:54.97#ibcon#read 4, iclass 23, count 0 2006.285.07:03:54.97#ibcon#about to read 5, iclass 23, count 0 2006.285.07:03:54.97#ibcon#read 5, iclass 23, count 0 2006.285.07:03:54.97#ibcon#about to read 6, iclass 23, count 0 2006.285.07:03:54.97#ibcon#read 6, iclass 23, count 0 2006.285.07:03:54.97#ibcon#end of sib2, iclass 23, count 0 2006.285.07:03:54.97#ibcon#*after write, iclass 23, count 0 2006.285.07:03:54.97#ibcon#*before return 0, iclass 23, count 0 2006.285.07:03:54.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:03:54.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:03:54.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:03:54.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:03:54.97$setupk4/ifdk4 2006.285.07:03:54.97$ifdk4/lo= 2006.285.07:03:54.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:03:54.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:03:54.98$ifdk4/patch= 2006.285.07:03:54.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:03:54.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:03:54.98$setupk4/!*+20s 2006.285.07:04:03.32#abcon#<5=/05 3.8 6.5 24.26 741014.2\r\n> 2006.285.07:04:03.34#abcon#{5=INTERFACE CLEAR} 2006.285.07:04:03.40#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:04:09.50$setupk4/"tpicd 2006.285.07:04:09.50$setupk4/echo=off 2006.285.07:04:09.50$setupk4/xlog=off 2006.285.07:04:09.50:!2006.285.07:05:19 2006.285.07:04:18.14#trakl#Source acquired 2006.285.07:04:20.14#flagr#flagr/antenna,acquired 2006.285.07:05:19.00:preob 2006.285.07:05:19.13/onsource/TRACKING 2006.285.07:05:19.13:!2006.285.07:05:29 2006.285.07:05:29.00:"tape 2006.285.07:05:29.00:"st=record 2006.285.07:05:29.00:data_valid=on 2006.285.07:05:29.00:midob 2006.285.07:05:29.13/onsource/TRACKING 2006.285.07:05:29.14/wx/24.24,1014.2,74 2006.285.07:05:29.31/cable/+6.4719E-03 2006.285.07:05:30.40/va/01,07,usb,yes,33,36 2006.285.07:05:30.40/va/02,06,usb,yes,34,34 2006.285.07:05:30.40/va/03,07,usb,yes,33,35 2006.285.07:05:30.40/va/04,06,usb,yes,34,36 2006.285.07:05:30.40/va/05,03,usb,yes,34,34 2006.285.07:05:30.40/va/06,04,usb,yes,31,30 2006.285.07:05:30.40/va/07,04,usb,yes,31,32 2006.285.07:05:30.40/va/08,03,usb,yes,32,39 2006.285.07:05:30.63/valo/01,524.99,yes,locked 2006.285.07:05:30.63/valo/02,534.99,yes,locked 2006.285.07:05:30.63/valo/03,564.99,yes,locked 2006.285.07:05:30.63/valo/04,624.99,yes,locked 2006.285.07:05:30.63/valo/05,734.99,yes,locked 2006.285.07:05:30.63/valo/06,814.99,yes,locked 2006.285.07:05:30.63/valo/07,864.99,yes,locked 2006.285.07:05:30.63/valo/08,884.99,yes,locked 2006.285.07:05:31.72/vb/01,04,usb,yes,32,29 2006.285.07:05:31.72/vb/02,05,usb,yes,30,30 2006.285.07:05:31.72/vb/03,04,usb,yes,31,34 2006.285.07:05:31.72/vb/04,05,usb,yes,31,30 2006.285.07:05:31.72/vb/05,04,usb,yes,28,30 2006.285.07:05:31.72/vb/06,03,usb,yes,40,35 2006.285.07:05:31.72/vb/07,04,usb,yes,32,32 2006.285.07:05:31.72/vb/08,04,usb,yes,29,33 2006.285.07:05:31.95/vblo/01,629.99,yes,locked 2006.285.07:05:31.95/vblo/02,634.99,yes,locked 2006.285.07:05:31.95/vblo/03,649.99,yes,locked 2006.285.07:05:31.95/vblo/04,679.99,yes,locked 2006.285.07:05:31.95/vblo/05,709.99,yes,locked 2006.285.07:05:31.95/vblo/06,719.99,yes,locked 2006.285.07:05:31.95/vblo/07,734.99,yes,locked 2006.285.07:05:31.95/vblo/08,744.99,yes,locked 2006.285.07:05:32.10/vabw/8 2006.285.07:05:32.25/vbbw/8 2006.285.07:05:32.34/xfe/off,on,12.2 2006.285.07:05:32.72/ifatt/23,28,28,28 2006.285.07:05:33.07/fmout-gps/S +2.64E-07 2006.285.07:05:33.09:!2006.285.07:07:39 2006.285.07:07:39.00:data_valid=off 2006.285.07:07:39.00:"et 2006.285.07:07:39.00:!+3s 2006.285.07:07:42.01:"tape 2006.285.07:07:42.01:postob 2006.285.07:07:42.10/cable/+6.4724E-03 2006.285.07:07:42.10/wx/24.20,1014.2,74 2006.285.07:07:43.07/fmout-gps/S +2.65E-07 2006.285.07:07:43.07:scan_name=285-0713,jd0610,50 2006.285.07:07:43.07:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.285.07:07:44.14#flagr#flagr/antenna,new-source 2006.285.07:07:44.14:checkk5 2006.285.07:07:44.70/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:07:45.11/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:07:45.56/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:07:45.98/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:07:46.37/chk_obsdata//k5ts1/T2850705??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.285.07:07:46.78/chk_obsdata//k5ts2/T2850705??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.285.07:07:47.14/chk_obsdata//k5ts3/T2850705??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.285.07:07:47.47/chk_obsdata//k5ts4/T2850705??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.285.07:07:48.22/k5log//k5ts1_log_newline 2006.285.07:07:48.97/k5log//k5ts2_log_newline 2006.285.07:07:49.74/k5log//k5ts3_log_newline 2006.285.07:07:50.67/k5log//k5ts4_log_newline 2006.285.07:07:50.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:07:50.69:setupk4=1 2006.285.07:07:50.69$setupk4/echo=on 2006.285.07:07:50.69$setupk4/pcalon 2006.285.07:07:50.69$pcalon/"no phase cal control is implemented here 2006.285.07:07:50.69$setupk4/"tpicd=stop 2006.285.07:07:50.69$setupk4/"rec=synch_on 2006.285.07:07:50.69$setupk4/"rec_mode=128 2006.285.07:07:50.69$setupk4/!* 2006.285.07:07:50.69$setupk4/recpk4 2006.285.07:07:50.69$recpk4/recpatch= 2006.285.07:07:50.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:07:50.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:07:50.69$setupk4/vck44 2006.285.07:07:50.69$vck44/valo=1,524.99 2006.285.07:07:50.69#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.07:07:50.69#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.07:07:50.70#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:50.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:07:50.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:07:50.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:07:50.70#ibcon#enter wrdev, iclass 12, count 0 2006.285.07:07:50.70#ibcon#first serial, iclass 12, count 0 2006.285.07:07:50.70#ibcon#enter sib2, iclass 12, count 0 2006.285.07:07:50.70#ibcon#flushed, iclass 12, count 0 2006.285.07:07:50.70#ibcon#about to write, iclass 12, count 0 2006.285.07:07:50.70#ibcon#wrote, iclass 12, count 0 2006.285.07:07:50.70#ibcon#about to read 3, iclass 12, count 0 2006.285.07:07:50.71#ibcon#read 3, iclass 12, count 0 2006.285.07:07:50.71#ibcon#about to read 4, iclass 12, count 0 2006.285.07:07:50.71#ibcon#read 4, iclass 12, count 0 2006.285.07:07:50.71#ibcon#about to read 5, iclass 12, count 0 2006.285.07:07:50.71#ibcon#read 5, iclass 12, count 0 2006.285.07:07:50.71#ibcon#about to read 6, iclass 12, count 0 2006.285.07:07:50.71#ibcon#read 6, iclass 12, count 0 2006.285.07:07:50.71#ibcon#end of sib2, iclass 12, count 0 2006.285.07:07:50.71#ibcon#*mode == 0, iclass 12, count 0 2006.285.07:07:50.71#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.07:07:50.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:07:50.71#ibcon#*before write, iclass 12, count 0 2006.285.07:07:50.71#ibcon#enter sib2, iclass 12, count 0 2006.285.07:07:50.71#ibcon#flushed, iclass 12, count 0 2006.285.07:07:50.71#ibcon#about to write, iclass 12, count 0 2006.285.07:07:50.71#ibcon#wrote, iclass 12, count 0 2006.285.07:07:50.71#ibcon#about to read 3, iclass 12, count 0 2006.285.07:07:50.76#ibcon#read 3, iclass 12, count 0 2006.285.07:07:50.76#ibcon#about to read 4, iclass 12, count 0 2006.285.07:07:50.76#ibcon#read 4, iclass 12, count 0 2006.285.07:07:50.76#ibcon#about to read 5, iclass 12, count 0 2006.285.07:07:50.76#ibcon#read 5, iclass 12, count 0 2006.285.07:07:50.76#ibcon#about to read 6, iclass 12, count 0 2006.285.07:07:50.76#ibcon#read 6, iclass 12, count 0 2006.285.07:07:50.76#ibcon#end of sib2, iclass 12, count 0 2006.285.07:07:50.76#ibcon#*after write, iclass 12, count 0 2006.285.07:07:50.76#ibcon#*before return 0, iclass 12, count 0 2006.285.07:07:50.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:07:50.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:07:50.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.07:07:50.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.07:07:50.76$vck44/va=1,7 2006.285.07:07:50.76#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.07:07:50.76#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.07:07:50.76#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:50.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:07:50.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:07:50.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:07:50.76#ibcon#enter wrdev, iclass 14, count 2 2006.285.07:07:50.76#ibcon#first serial, iclass 14, count 2 2006.285.07:07:50.76#ibcon#enter sib2, iclass 14, count 2 2006.285.07:07:50.76#ibcon#flushed, iclass 14, count 2 2006.285.07:07:50.76#ibcon#about to write, iclass 14, count 2 2006.285.07:07:50.76#ibcon#wrote, iclass 14, count 2 2006.285.07:07:50.76#ibcon#about to read 3, iclass 14, count 2 2006.285.07:07:50.78#ibcon#read 3, iclass 14, count 2 2006.285.07:07:50.78#ibcon#about to read 4, iclass 14, count 2 2006.285.07:07:50.78#ibcon#read 4, iclass 14, count 2 2006.285.07:07:50.78#ibcon#about to read 5, iclass 14, count 2 2006.285.07:07:50.78#ibcon#read 5, iclass 14, count 2 2006.285.07:07:50.78#ibcon#about to read 6, iclass 14, count 2 2006.285.07:07:50.78#ibcon#read 6, iclass 14, count 2 2006.285.07:07:50.78#ibcon#end of sib2, iclass 14, count 2 2006.285.07:07:50.78#ibcon#*mode == 0, iclass 14, count 2 2006.285.07:07:50.78#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.07:07:50.78#ibcon#[25=AT01-07\r\n] 2006.285.07:07:50.78#ibcon#*before write, iclass 14, count 2 2006.285.07:07:50.78#ibcon#enter sib2, iclass 14, count 2 2006.285.07:07:50.78#ibcon#flushed, iclass 14, count 2 2006.285.07:07:50.78#ibcon#about to write, iclass 14, count 2 2006.285.07:07:50.78#ibcon#wrote, iclass 14, count 2 2006.285.07:07:50.78#ibcon#about to read 3, iclass 14, count 2 2006.285.07:07:50.81#ibcon#read 3, iclass 14, count 2 2006.285.07:07:50.81#ibcon#about to read 4, iclass 14, count 2 2006.285.07:07:50.81#ibcon#read 4, iclass 14, count 2 2006.285.07:07:50.81#ibcon#about to read 5, iclass 14, count 2 2006.285.07:07:50.81#ibcon#read 5, iclass 14, count 2 2006.285.07:07:50.81#ibcon#about to read 6, iclass 14, count 2 2006.285.07:07:50.81#ibcon#read 6, iclass 14, count 2 2006.285.07:07:50.81#ibcon#end of sib2, iclass 14, count 2 2006.285.07:07:50.81#ibcon#*after write, iclass 14, count 2 2006.285.07:07:50.81#ibcon#*before return 0, iclass 14, count 2 2006.285.07:07:50.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:07:50.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:07:50.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.07:07:50.81#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:50.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:07:50.93#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:07:50.93#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:07:50.93#ibcon#enter wrdev, iclass 14, count 0 2006.285.07:07:50.93#ibcon#first serial, iclass 14, count 0 2006.285.07:07:50.93#ibcon#enter sib2, iclass 14, count 0 2006.285.07:07:50.93#ibcon#flushed, iclass 14, count 0 2006.285.07:07:50.93#ibcon#about to write, iclass 14, count 0 2006.285.07:07:50.93#ibcon#wrote, iclass 14, count 0 2006.285.07:07:50.93#ibcon#about to read 3, iclass 14, count 0 2006.285.07:07:50.95#ibcon#read 3, iclass 14, count 0 2006.285.07:07:50.95#ibcon#about to read 4, iclass 14, count 0 2006.285.07:07:50.95#ibcon#read 4, iclass 14, count 0 2006.285.07:07:50.95#ibcon#about to read 5, iclass 14, count 0 2006.285.07:07:50.95#ibcon#read 5, iclass 14, count 0 2006.285.07:07:50.95#ibcon#about to read 6, iclass 14, count 0 2006.285.07:07:50.95#ibcon#read 6, iclass 14, count 0 2006.285.07:07:50.95#ibcon#end of sib2, iclass 14, count 0 2006.285.07:07:50.95#ibcon#*mode == 0, iclass 14, count 0 2006.285.07:07:50.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.07:07:50.95#ibcon#[25=USB\r\n] 2006.285.07:07:50.95#ibcon#*before write, iclass 14, count 0 2006.285.07:07:50.95#ibcon#enter sib2, iclass 14, count 0 2006.285.07:07:50.95#ibcon#flushed, iclass 14, count 0 2006.285.07:07:50.95#ibcon#about to write, iclass 14, count 0 2006.285.07:07:50.95#ibcon#wrote, iclass 14, count 0 2006.285.07:07:50.95#ibcon#about to read 3, iclass 14, count 0 2006.285.07:07:50.98#ibcon#read 3, iclass 14, count 0 2006.285.07:07:50.98#ibcon#about to read 4, iclass 14, count 0 2006.285.07:07:50.98#ibcon#read 4, iclass 14, count 0 2006.285.07:07:50.98#ibcon#about to read 5, iclass 14, count 0 2006.285.07:07:50.98#ibcon#read 5, iclass 14, count 0 2006.285.07:07:50.98#ibcon#about to read 6, iclass 14, count 0 2006.285.07:07:50.98#ibcon#read 6, iclass 14, count 0 2006.285.07:07:50.98#ibcon#end of sib2, iclass 14, count 0 2006.285.07:07:50.98#ibcon#*after write, iclass 14, count 0 2006.285.07:07:50.98#ibcon#*before return 0, iclass 14, count 0 2006.285.07:07:50.98#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:07:50.98#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:07:50.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.07:07:50.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.07:07:50.98$vck44/valo=2,534.99 2006.285.07:07:50.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.07:07:50.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.07:07:50.98#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:50.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:07:50.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:07:50.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:07:50.98#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:07:50.98#ibcon#first serial, iclass 16, count 0 2006.285.07:07:50.98#ibcon#enter sib2, iclass 16, count 0 2006.285.07:07:50.98#ibcon#flushed, iclass 16, count 0 2006.285.07:07:50.98#ibcon#about to write, iclass 16, count 0 2006.285.07:07:50.98#ibcon#wrote, iclass 16, count 0 2006.285.07:07:50.98#ibcon#about to read 3, iclass 16, count 0 2006.285.07:07:51.00#ibcon#read 3, iclass 16, count 0 2006.285.07:07:51.00#ibcon#about to read 4, iclass 16, count 0 2006.285.07:07:51.00#ibcon#read 4, iclass 16, count 0 2006.285.07:07:51.00#ibcon#about to read 5, iclass 16, count 0 2006.285.07:07:51.00#ibcon#read 5, iclass 16, count 0 2006.285.07:07:51.00#ibcon#about to read 6, iclass 16, count 0 2006.285.07:07:51.00#ibcon#read 6, iclass 16, count 0 2006.285.07:07:51.00#ibcon#end of sib2, iclass 16, count 0 2006.285.07:07:51.00#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:07:51.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:07:51.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:07:51.00#ibcon#*before write, iclass 16, count 0 2006.285.07:07:51.00#ibcon#enter sib2, iclass 16, count 0 2006.285.07:07:51.00#ibcon#flushed, iclass 16, count 0 2006.285.07:07:51.00#ibcon#about to write, iclass 16, count 0 2006.285.07:07:51.00#ibcon#wrote, iclass 16, count 0 2006.285.07:07:51.00#ibcon#about to read 3, iclass 16, count 0 2006.285.07:07:51.04#ibcon#read 3, iclass 16, count 0 2006.285.07:07:51.04#ibcon#about to read 4, iclass 16, count 0 2006.285.07:07:51.04#ibcon#read 4, iclass 16, count 0 2006.285.07:07:51.04#ibcon#about to read 5, iclass 16, count 0 2006.285.07:07:51.04#ibcon#read 5, iclass 16, count 0 2006.285.07:07:51.04#ibcon#about to read 6, iclass 16, count 0 2006.285.07:07:51.04#ibcon#read 6, iclass 16, count 0 2006.285.07:07:51.04#ibcon#end of sib2, iclass 16, count 0 2006.285.07:07:51.04#ibcon#*after write, iclass 16, count 0 2006.285.07:07:51.04#ibcon#*before return 0, iclass 16, count 0 2006.285.07:07:51.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:07:51.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:07:51.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:07:51.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:07:51.04$vck44/va=2,6 2006.285.07:07:51.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.07:07:51.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.07:07:51.04#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:51.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:07:51.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:07:51.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:07:51.10#ibcon#enter wrdev, iclass 18, count 2 2006.285.07:07:51.10#ibcon#first serial, iclass 18, count 2 2006.285.07:07:51.10#ibcon#enter sib2, iclass 18, count 2 2006.285.07:07:51.10#ibcon#flushed, iclass 18, count 2 2006.285.07:07:51.10#ibcon#about to write, iclass 18, count 2 2006.285.07:07:51.10#ibcon#wrote, iclass 18, count 2 2006.285.07:07:51.10#ibcon#about to read 3, iclass 18, count 2 2006.285.07:07:51.12#ibcon#read 3, iclass 18, count 2 2006.285.07:07:51.12#ibcon#about to read 4, iclass 18, count 2 2006.285.07:07:51.12#ibcon#read 4, iclass 18, count 2 2006.285.07:07:51.12#ibcon#about to read 5, iclass 18, count 2 2006.285.07:07:51.12#ibcon#read 5, iclass 18, count 2 2006.285.07:07:51.12#ibcon#about to read 6, iclass 18, count 2 2006.285.07:07:51.12#ibcon#read 6, iclass 18, count 2 2006.285.07:07:51.12#ibcon#end of sib2, iclass 18, count 2 2006.285.07:07:51.12#ibcon#*mode == 0, iclass 18, count 2 2006.285.07:07:51.12#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.07:07:51.12#ibcon#[25=AT02-06\r\n] 2006.285.07:07:51.12#ibcon#*before write, iclass 18, count 2 2006.285.07:07:51.12#ibcon#enter sib2, iclass 18, count 2 2006.285.07:07:51.12#ibcon#flushed, iclass 18, count 2 2006.285.07:07:51.12#ibcon#about to write, iclass 18, count 2 2006.285.07:07:51.12#ibcon#wrote, iclass 18, count 2 2006.285.07:07:51.12#ibcon#about to read 3, iclass 18, count 2 2006.285.07:07:51.15#ibcon#read 3, iclass 18, count 2 2006.285.07:07:51.15#ibcon#about to read 4, iclass 18, count 2 2006.285.07:07:51.15#ibcon#read 4, iclass 18, count 2 2006.285.07:07:51.15#ibcon#about to read 5, iclass 18, count 2 2006.285.07:07:51.15#ibcon#read 5, iclass 18, count 2 2006.285.07:07:51.15#ibcon#about to read 6, iclass 18, count 2 2006.285.07:07:51.15#ibcon#read 6, iclass 18, count 2 2006.285.07:07:51.15#ibcon#end of sib2, iclass 18, count 2 2006.285.07:07:51.15#ibcon#*after write, iclass 18, count 2 2006.285.07:07:51.15#ibcon#*before return 0, iclass 18, count 2 2006.285.07:07:51.15#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:07:51.15#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:07:51.15#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.07:07:51.15#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:51.15#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:07:51.27#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:07:51.27#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:07:51.27#ibcon#enter wrdev, iclass 18, count 0 2006.285.07:07:51.27#ibcon#first serial, iclass 18, count 0 2006.285.07:07:51.27#ibcon#enter sib2, iclass 18, count 0 2006.285.07:07:51.27#ibcon#flushed, iclass 18, count 0 2006.285.07:07:51.27#ibcon#about to write, iclass 18, count 0 2006.285.07:07:51.27#ibcon#wrote, iclass 18, count 0 2006.285.07:07:51.27#ibcon#about to read 3, iclass 18, count 0 2006.285.07:07:51.29#ibcon#read 3, iclass 18, count 0 2006.285.07:07:51.29#ibcon#about to read 4, iclass 18, count 0 2006.285.07:07:51.29#ibcon#read 4, iclass 18, count 0 2006.285.07:07:51.29#ibcon#about to read 5, iclass 18, count 0 2006.285.07:07:51.29#ibcon#read 5, iclass 18, count 0 2006.285.07:07:51.29#ibcon#about to read 6, iclass 18, count 0 2006.285.07:07:51.29#ibcon#read 6, iclass 18, count 0 2006.285.07:07:51.29#ibcon#end of sib2, iclass 18, count 0 2006.285.07:07:51.29#ibcon#*mode == 0, iclass 18, count 0 2006.285.07:07:51.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.07:07:51.29#ibcon#[25=USB\r\n] 2006.285.07:07:51.29#ibcon#*before write, iclass 18, count 0 2006.285.07:07:51.29#ibcon#enter sib2, iclass 18, count 0 2006.285.07:07:51.29#ibcon#flushed, iclass 18, count 0 2006.285.07:07:51.29#ibcon#about to write, iclass 18, count 0 2006.285.07:07:51.29#ibcon#wrote, iclass 18, count 0 2006.285.07:07:51.29#ibcon#about to read 3, iclass 18, count 0 2006.285.07:07:51.32#ibcon#read 3, iclass 18, count 0 2006.285.07:07:51.32#ibcon#about to read 4, iclass 18, count 0 2006.285.07:07:51.32#ibcon#read 4, iclass 18, count 0 2006.285.07:07:51.32#ibcon#about to read 5, iclass 18, count 0 2006.285.07:07:51.32#ibcon#read 5, iclass 18, count 0 2006.285.07:07:51.32#ibcon#about to read 6, iclass 18, count 0 2006.285.07:07:51.32#ibcon#read 6, iclass 18, count 0 2006.285.07:07:51.32#ibcon#end of sib2, iclass 18, count 0 2006.285.07:07:51.32#ibcon#*after write, iclass 18, count 0 2006.285.07:07:51.32#ibcon#*before return 0, iclass 18, count 0 2006.285.07:07:51.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:07:51.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:07:51.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.07:07:51.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.07:07:51.32$vck44/valo=3,564.99 2006.285.07:07:51.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.07:07:51.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.07:07:51.32#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:51.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:07:51.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:07:51.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:07:51.32#ibcon#enter wrdev, iclass 20, count 0 2006.285.07:07:51.32#ibcon#first serial, iclass 20, count 0 2006.285.07:07:51.32#ibcon#enter sib2, iclass 20, count 0 2006.285.07:07:51.32#ibcon#flushed, iclass 20, count 0 2006.285.07:07:51.32#ibcon#about to write, iclass 20, count 0 2006.285.07:07:51.32#ibcon#wrote, iclass 20, count 0 2006.285.07:07:51.32#ibcon#about to read 3, iclass 20, count 0 2006.285.07:07:51.34#ibcon#read 3, iclass 20, count 0 2006.285.07:07:51.34#ibcon#about to read 4, iclass 20, count 0 2006.285.07:07:51.34#ibcon#read 4, iclass 20, count 0 2006.285.07:07:51.34#ibcon#about to read 5, iclass 20, count 0 2006.285.07:07:51.34#ibcon#read 5, iclass 20, count 0 2006.285.07:07:51.34#ibcon#about to read 6, iclass 20, count 0 2006.285.07:07:51.34#ibcon#read 6, iclass 20, count 0 2006.285.07:07:51.34#ibcon#end of sib2, iclass 20, count 0 2006.285.07:07:51.34#ibcon#*mode == 0, iclass 20, count 0 2006.285.07:07:51.34#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.07:07:51.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:07:51.34#ibcon#*before write, iclass 20, count 0 2006.285.07:07:51.34#ibcon#enter sib2, iclass 20, count 0 2006.285.07:07:51.34#ibcon#flushed, iclass 20, count 0 2006.285.07:07:51.34#ibcon#about to write, iclass 20, count 0 2006.285.07:07:51.34#ibcon#wrote, iclass 20, count 0 2006.285.07:07:51.34#ibcon#about to read 3, iclass 20, count 0 2006.285.07:07:51.38#ibcon#read 3, iclass 20, count 0 2006.285.07:07:51.38#ibcon#about to read 4, iclass 20, count 0 2006.285.07:07:51.38#ibcon#read 4, iclass 20, count 0 2006.285.07:07:51.38#ibcon#about to read 5, iclass 20, count 0 2006.285.07:07:51.38#ibcon#read 5, iclass 20, count 0 2006.285.07:07:51.38#ibcon#about to read 6, iclass 20, count 0 2006.285.07:07:51.38#ibcon#read 6, iclass 20, count 0 2006.285.07:07:51.38#ibcon#end of sib2, iclass 20, count 0 2006.285.07:07:51.38#ibcon#*after write, iclass 20, count 0 2006.285.07:07:51.38#ibcon#*before return 0, iclass 20, count 0 2006.285.07:07:51.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:07:51.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:07:51.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.07:07:51.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.07:07:51.38$vck44/va=3,7 2006.285.07:07:51.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.07:07:51.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.07:07:51.38#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:51.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:07:51.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:07:51.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:07:51.44#ibcon#enter wrdev, iclass 22, count 2 2006.285.07:07:51.44#ibcon#first serial, iclass 22, count 2 2006.285.07:07:51.44#ibcon#enter sib2, iclass 22, count 2 2006.285.07:07:51.44#ibcon#flushed, iclass 22, count 2 2006.285.07:07:51.44#ibcon#about to write, iclass 22, count 2 2006.285.07:07:51.44#ibcon#wrote, iclass 22, count 2 2006.285.07:07:51.44#ibcon#about to read 3, iclass 22, count 2 2006.285.07:07:51.46#ibcon#read 3, iclass 22, count 2 2006.285.07:07:51.46#ibcon#about to read 4, iclass 22, count 2 2006.285.07:07:51.46#ibcon#read 4, iclass 22, count 2 2006.285.07:07:51.46#ibcon#about to read 5, iclass 22, count 2 2006.285.07:07:51.46#ibcon#read 5, iclass 22, count 2 2006.285.07:07:51.46#ibcon#about to read 6, iclass 22, count 2 2006.285.07:07:51.46#ibcon#read 6, iclass 22, count 2 2006.285.07:07:51.46#ibcon#end of sib2, iclass 22, count 2 2006.285.07:07:51.46#ibcon#*mode == 0, iclass 22, count 2 2006.285.07:07:51.46#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.07:07:51.46#ibcon#[25=AT03-07\r\n] 2006.285.07:07:51.46#ibcon#*before write, iclass 22, count 2 2006.285.07:07:51.46#ibcon#enter sib2, iclass 22, count 2 2006.285.07:07:51.46#ibcon#flushed, iclass 22, count 2 2006.285.07:07:51.46#ibcon#about to write, iclass 22, count 2 2006.285.07:07:51.46#ibcon#wrote, iclass 22, count 2 2006.285.07:07:51.46#ibcon#about to read 3, iclass 22, count 2 2006.285.07:07:51.49#ibcon#read 3, iclass 22, count 2 2006.285.07:07:51.49#ibcon#about to read 4, iclass 22, count 2 2006.285.07:07:51.49#ibcon#read 4, iclass 22, count 2 2006.285.07:07:51.49#ibcon#about to read 5, iclass 22, count 2 2006.285.07:07:51.49#ibcon#read 5, iclass 22, count 2 2006.285.07:07:51.49#ibcon#about to read 6, iclass 22, count 2 2006.285.07:07:51.49#ibcon#read 6, iclass 22, count 2 2006.285.07:07:51.49#ibcon#end of sib2, iclass 22, count 2 2006.285.07:07:51.49#ibcon#*after write, iclass 22, count 2 2006.285.07:07:51.49#ibcon#*before return 0, iclass 22, count 2 2006.285.07:07:51.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:07:51.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:07:51.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.07:07:51.49#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:51.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:07:51.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:07:51.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:07:51.61#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:07:51.61#ibcon#first serial, iclass 22, count 0 2006.285.07:07:51.61#ibcon#enter sib2, iclass 22, count 0 2006.285.07:07:51.61#ibcon#flushed, iclass 22, count 0 2006.285.07:07:51.61#ibcon#about to write, iclass 22, count 0 2006.285.07:07:51.61#ibcon#wrote, iclass 22, count 0 2006.285.07:07:51.61#ibcon#about to read 3, iclass 22, count 0 2006.285.07:07:51.63#ibcon#read 3, iclass 22, count 0 2006.285.07:07:51.63#ibcon#about to read 4, iclass 22, count 0 2006.285.07:07:51.63#ibcon#read 4, iclass 22, count 0 2006.285.07:07:51.63#ibcon#about to read 5, iclass 22, count 0 2006.285.07:07:51.63#ibcon#read 5, iclass 22, count 0 2006.285.07:07:51.63#ibcon#about to read 6, iclass 22, count 0 2006.285.07:07:51.63#ibcon#read 6, iclass 22, count 0 2006.285.07:07:51.63#ibcon#end of sib2, iclass 22, count 0 2006.285.07:07:51.63#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:07:51.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:07:51.63#ibcon#[25=USB\r\n] 2006.285.07:07:51.63#ibcon#*before write, iclass 22, count 0 2006.285.07:07:51.63#ibcon#enter sib2, iclass 22, count 0 2006.285.07:07:51.63#ibcon#flushed, iclass 22, count 0 2006.285.07:07:51.63#ibcon#about to write, iclass 22, count 0 2006.285.07:07:51.63#ibcon#wrote, iclass 22, count 0 2006.285.07:07:51.63#ibcon#about to read 3, iclass 22, count 0 2006.285.07:07:51.66#ibcon#read 3, iclass 22, count 0 2006.285.07:07:51.66#ibcon#about to read 4, iclass 22, count 0 2006.285.07:07:51.66#ibcon#read 4, iclass 22, count 0 2006.285.07:07:51.66#ibcon#about to read 5, iclass 22, count 0 2006.285.07:07:51.66#ibcon#read 5, iclass 22, count 0 2006.285.07:07:51.66#ibcon#about to read 6, iclass 22, count 0 2006.285.07:07:51.66#ibcon#read 6, iclass 22, count 0 2006.285.07:07:51.66#ibcon#end of sib2, iclass 22, count 0 2006.285.07:07:51.66#ibcon#*after write, iclass 22, count 0 2006.285.07:07:51.66#ibcon#*before return 0, iclass 22, count 0 2006.285.07:07:51.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:07:51.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:07:51.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:07:51.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:07:51.66$vck44/valo=4,624.99 2006.285.07:07:51.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.07:07:51.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.07:07:51.66#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:51.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:07:51.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:07:51.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:07:51.66#ibcon#enter wrdev, iclass 24, count 0 2006.285.07:07:51.66#ibcon#first serial, iclass 24, count 0 2006.285.07:07:51.66#ibcon#enter sib2, iclass 24, count 0 2006.285.07:07:51.66#ibcon#flushed, iclass 24, count 0 2006.285.07:07:51.66#ibcon#about to write, iclass 24, count 0 2006.285.07:07:51.66#ibcon#wrote, iclass 24, count 0 2006.285.07:07:51.66#ibcon#about to read 3, iclass 24, count 0 2006.285.07:07:51.68#ibcon#read 3, iclass 24, count 0 2006.285.07:07:51.68#ibcon#about to read 4, iclass 24, count 0 2006.285.07:07:51.68#ibcon#read 4, iclass 24, count 0 2006.285.07:07:51.68#ibcon#about to read 5, iclass 24, count 0 2006.285.07:07:51.68#ibcon#read 5, iclass 24, count 0 2006.285.07:07:51.68#ibcon#about to read 6, iclass 24, count 0 2006.285.07:07:51.68#ibcon#read 6, iclass 24, count 0 2006.285.07:07:51.68#ibcon#end of sib2, iclass 24, count 0 2006.285.07:07:51.68#ibcon#*mode == 0, iclass 24, count 0 2006.285.07:07:51.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.07:07:51.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:07:51.68#ibcon#*before write, iclass 24, count 0 2006.285.07:07:51.68#ibcon#enter sib2, iclass 24, count 0 2006.285.07:07:51.68#ibcon#flushed, iclass 24, count 0 2006.285.07:07:51.68#ibcon#about to write, iclass 24, count 0 2006.285.07:07:51.68#ibcon#wrote, iclass 24, count 0 2006.285.07:07:51.68#ibcon#about to read 3, iclass 24, count 0 2006.285.07:07:51.72#ibcon#read 3, iclass 24, count 0 2006.285.07:07:51.72#ibcon#about to read 4, iclass 24, count 0 2006.285.07:07:51.72#ibcon#read 4, iclass 24, count 0 2006.285.07:07:51.72#ibcon#about to read 5, iclass 24, count 0 2006.285.07:07:51.72#ibcon#read 5, iclass 24, count 0 2006.285.07:07:51.72#ibcon#about to read 6, iclass 24, count 0 2006.285.07:07:51.72#ibcon#read 6, iclass 24, count 0 2006.285.07:07:51.72#ibcon#end of sib2, iclass 24, count 0 2006.285.07:07:51.72#ibcon#*after write, iclass 24, count 0 2006.285.07:07:51.72#ibcon#*before return 0, iclass 24, count 0 2006.285.07:07:51.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:07:51.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:07:51.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.07:07:51.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.07:07:51.72$vck44/va=4,6 2006.285.07:07:51.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.07:07:51.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.07:07:51.72#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:51.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:07:51.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:07:51.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:07:51.78#ibcon#enter wrdev, iclass 26, count 2 2006.285.07:07:51.78#ibcon#first serial, iclass 26, count 2 2006.285.07:07:51.78#ibcon#enter sib2, iclass 26, count 2 2006.285.07:07:51.78#ibcon#flushed, iclass 26, count 2 2006.285.07:07:51.78#ibcon#about to write, iclass 26, count 2 2006.285.07:07:51.78#ibcon#wrote, iclass 26, count 2 2006.285.07:07:51.78#ibcon#about to read 3, iclass 26, count 2 2006.285.07:07:51.80#ibcon#read 3, iclass 26, count 2 2006.285.07:07:51.80#ibcon#about to read 4, iclass 26, count 2 2006.285.07:07:51.80#ibcon#read 4, iclass 26, count 2 2006.285.07:07:51.80#ibcon#about to read 5, iclass 26, count 2 2006.285.07:07:51.80#ibcon#read 5, iclass 26, count 2 2006.285.07:07:51.80#ibcon#about to read 6, iclass 26, count 2 2006.285.07:07:51.80#ibcon#read 6, iclass 26, count 2 2006.285.07:07:51.80#ibcon#end of sib2, iclass 26, count 2 2006.285.07:07:51.80#ibcon#*mode == 0, iclass 26, count 2 2006.285.07:07:51.80#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.07:07:51.80#ibcon#[25=AT04-06\r\n] 2006.285.07:07:51.80#ibcon#*before write, iclass 26, count 2 2006.285.07:07:51.80#ibcon#enter sib2, iclass 26, count 2 2006.285.07:07:51.80#ibcon#flushed, iclass 26, count 2 2006.285.07:07:51.80#ibcon#about to write, iclass 26, count 2 2006.285.07:07:51.80#ibcon#wrote, iclass 26, count 2 2006.285.07:07:51.80#ibcon#about to read 3, iclass 26, count 2 2006.285.07:07:51.83#ibcon#read 3, iclass 26, count 2 2006.285.07:07:51.83#ibcon#about to read 4, iclass 26, count 2 2006.285.07:07:51.83#ibcon#read 4, iclass 26, count 2 2006.285.07:07:51.83#ibcon#about to read 5, iclass 26, count 2 2006.285.07:07:51.83#ibcon#read 5, iclass 26, count 2 2006.285.07:07:51.83#ibcon#about to read 6, iclass 26, count 2 2006.285.07:07:51.83#ibcon#read 6, iclass 26, count 2 2006.285.07:07:51.83#ibcon#end of sib2, iclass 26, count 2 2006.285.07:07:51.83#ibcon#*after write, iclass 26, count 2 2006.285.07:07:51.83#ibcon#*before return 0, iclass 26, count 2 2006.285.07:07:51.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:07:51.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:07:51.83#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.07:07:51.83#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:51.83#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:07:51.95#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:07:51.95#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:07:51.95#ibcon#enter wrdev, iclass 26, count 0 2006.285.07:07:51.95#ibcon#first serial, iclass 26, count 0 2006.285.07:07:51.95#ibcon#enter sib2, iclass 26, count 0 2006.285.07:07:51.95#ibcon#flushed, iclass 26, count 0 2006.285.07:07:51.95#ibcon#about to write, iclass 26, count 0 2006.285.07:07:51.95#ibcon#wrote, iclass 26, count 0 2006.285.07:07:51.95#ibcon#about to read 3, iclass 26, count 0 2006.285.07:07:51.97#ibcon#read 3, iclass 26, count 0 2006.285.07:07:51.97#ibcon#about to read 4, iclass 26, count 0 2006.285.07:07:51.97#ibcon#read 4, iclass 26, count 0 2006.285.07:07:51.97#ibcon#about to read 5, iclass 26, count 0 2006.285.07:07:51.97#ibcon#read 5, iclass 26, count 0 2006.285.07:07:51.97#ibcon#about to read 6, iclass 26, count 0 2006.285.07:07:51.97#ibcon#read 6, iclass 26, count 0 2006.285.07:07:51.97#ibcon#end of sib2, iclass 26, count 0 2006.285.07:07:51.97#ibcon#*mode == 0, iclass 26, count 0 2006.285.07:07:51.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.07:07:51.97#ibcon#[25=USB\r\n] 2006.285.07:07:51.97#ibcon#*before write, iclass 26, count 0 2006.285.07:07:51.97#ibcon#enter sib2, iclass 26, count 0 2006.285.07:07:51.97#ibcon#flushed, iclass 26, count 0 2006.285.07:07:51.97#ibcon#about to write, iclass 26, count 0 2006.285.07:07:51.97#ibcon#wrote, iclass 26, count 0 2006.285.07:07:51.97#ibcon#about to read 3, iclass 26, count 0 2006.285.07:07:52.00#ibcon#read 3, iclass 26, count 0 2006.285.07:07:52.00#ibcon#about to read 4, iclass 26, count 0 2006.285.07:07:52.00#ibcon#read 4, iclass 26, count 0 2006.285.07:07:52.00#ibcon#about to read 5, iclass 26, count 0 2006.285.07:07:52.00#ibcon#read 5, iclass 26, count 0 2006.285.07:07:52.00#ibcon#about to read 6, iclass 26, count 0 2006.285.07:07:52.00#ibcon#read 6, iclass 26, count 0 2006.285.07:07:52.00#ibcon#end of sib2, iclass 26, count 0 2006.285.07:07:52.00#ibcon#*after write, iclass 26, count 0 2006.285.07:07:52.00#ibcon#*before return 0, iclass 26, count 0 2006.285.07:07:52.00#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:07:52.00#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:07:52.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.07:07:52.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.07:07:52.00$vck44/valo=5,734.99 2006.285.07:07:52.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.07:07:52.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.07:07:52.00#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:52.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:07:52.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:07:52.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:07:52.00#ibcon#enter wrdev, iclass 28, count 0 2006.285.07:07:52.00#ibcon#first serial, iclass 28, count 0 2006.285.07:07:52.00#ibcon#enter sib2, iclass 28, count 0 2006.285.07:07:52.00#ibcon#flushed, iclass 28, count 0 2006.285.07:07:52.00#ibcon#about to write, iclass 28, count 0 2006.285.07:07:52.00#ibcon#wrote, iclass 28, count 0 2006.285.07:07:52.00#ibcon#about to read 3, iclass 28, count 0 2006.285.07:07:52.02#ibcon#read 3, iclass 28, count 0 2006.285.07:07:52.02#ibcon#about to read 4, iclass 28, count 0 2006.285.07:07:52.02#ibcon#read 4, iclass 28, count 0 2006.285.07:07:52.02#ibcon#about to read 5, iclass 28, count 0 2006.285.07:07:52.02#ibcon#read 5, iclass 28, count 0 2006.285.07:07:52.02#ibcon#about to read 6, iclass 28, count 0 2006.285.07:07:52.02#ibcon#read 6, iclass 28, count 0 2006.285.07:07:52.02#ibcon#end of sib2, iclass 28, count 0 2006.285.07:07:52.02#ibcon#*mode == 0, iclass 28, count 0 2006.285.07:07:52.02#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.07:07:52.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:07:52.02#ibcon#*before write, iclass 28, count 0 2006.285.07:07:52.02#ibcon#enter sib2, iclass 28, count 0 2006.285.07:07:52.02#ibcon#flushed, iclass 28, count 0 2006.285.07:07:52.02#ibcon#about to write, iclass 28, count 0 2006.285.07:07:52.02#ibcon#wrote, iclass 28, count 0 2006.285.07:07:52.02#ibcon#about to read 3, iclass 28, count 0 2006.285.07:07:52.06#ibcon#read 3, iclass 28, count 0 2006.285.07:07:52.06#ibcon#about to read 4, iclass 28, count 0 2006.285.07:07:52.06#ibcon#read 4, iclass 28, count 0 2006.285.07:07:52.06#ibcon#about to read 5, iclass 28, count 0 2006.285.07:07:52.06#ibcon#read 5, iclass 28, count 0 2006.285.07:07:52.06#ibcon#about to read 6, iclass 28, count 0 2006.285.07:07:52.06#ibcon#read 6, iclass 28, count 0 2006.285.07:07:52.06#ibcon#end of sib2, iclass 28, count 0 2006.285.07:07:52.06#ibcon#*after write, iclass 28, count 0 2006.285.07:07:52.06#ibcon#*before return 0, iclass 28, count 0 2006.285.07:07:52.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:07:52.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:07:52.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.07:07:52.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.07:07:52.06$vck44/va=5,3 2006.285.07:07:52.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.07:07:52.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.07:07:52.06#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:52.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:07:52.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:07:52.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:07:52.12#ibcon#enter wrdev, iclass 30, count 2 2006.285.07:07:52.12#ibcon#first serial, iclass 30, count 2 2006.285.07:07:52.12#ibcon#enter sib2, iclass 30, count 2 2006.285.07:07:52.12#ibcon#flushed, iclass 30, count 2 2006.285.07:07:52.12#ibcon#about to write, iclass 30, count 2 2006.285.07:07:52.12#ibcon#wrote, iclass 30, count 2 2006.285.07:07:52.12#ibcon#about to read 3, iclass 30, count 2 2006.285.07:07:52.14#ibcon#read 3, iclass 30, count 2 2006.285.07:07:52.14#ibcon#about to read 4, iclass 30, count 2 2006.285.07:07:52.14#ibcon#read 4, iclass 30, count 2 2006.285.07:07:52.14#ibcon#about to read 5, iclass 30, count 2 2006.285.07:07:52.14#ibcon#read 5, iclass 30, count 2 2006.285.07:07:52.14#ibcon#about to read 6, iclass 30, count 2 2006.285.07:07:52.14#ibcon#read 6, iclass 30, count 2 2006.285.07:07:52.14#ibcon#end of sib2, iclass 30, count 2 2006.285.07:07:52.14#ibcon#*mode == 0, iclass 30, count 2 2006.285.07:07:52.14#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.07:07:52.14#ibcon#[25=AT05-03\r\n] 2006.285.07:07:52.14#ibcon#*before write, iclass 30, count 2 2006.285.07:07:52.14#ibcon#enter sib2, iclass 30, count 2 2006.285.07:07:52.14#ibcon#flushed, iclass 30, count 2 2006.285.07:07:52.14#ibcon#about to write, iclass 30, count 2 2006.285.07:07:52.14#ibcon#wrote, iclass 30, count 2 2006.285.07:07:52.14#ibcon#about to read 3, iclass 30, count 2 2006.285.07:07:52.17#ibcon#read 3, iclass 30, count 2 2006.285.07:07:52.17#ibcon#about to read 4, iclass 30, count 2 2006.285.07:07:52.17#ibcon#read 4, iclass 30, count 2 2006.285.07:07:52.17#ibcon#about to read 5, iclass 30, count 2 2006.285.07:07:52.17#ibcon#read 5, iclass 30, count 2 2006.285.07:07:52.17#ibcon#about to read 6, iclass 30, count 2 2006.285.07:07:52.17#ibcon#read 6, iclass 30, count 2 2006.285.07:07:52.17#ibcon#end of sib2, iclass 30, count 2 2006.285.07:07:52.17#ibcon#*after write, iclass 30, count 2 2006.285.07:07:52.17#ibcon#*before return 0, iclass 30, count 2 2006.285.07:07:52.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:07:52.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:07:52.17#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.07:07:52.17#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:52.17#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:07:52.29#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:07:52.29#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:07:52.29#ibcon#enter wrdev, iclass 30, count 0 2006.285.07:07:52.29#ibcon#first serial, iclass 30, count 0 2006.285.07:07:52.29#ibcon#enter sib2, iclass 30, count 0 2006.285.07:07:52.29#ibcon#flushed, iclass 30, count 0 2006.285.07:07:52.29#ibcon#about to write, iclass 30, count 0 2006.285.07:07:52.29#ibcon#wrote, iclass 30, count 0 2006.285.07:07:52.29#ibcon#about to read 3, iclass 30, count 0 2006.285.07:07:52.31#ibcon#read 3, iclass 30, count 0 2006.285.07:07:52.31#ibcon#about to read 4, iclass 30, count 0 2006.285.07:07:52.31#ibcon#read 4, iclass 30, count 0 2006.285.07:07:52.31#ibcon#about to read 5, iclass 30, count 0 2006.285.07:07:52.31#ibcon#read 5, iclass 30, count 0 2006.285.07:07:52.31#ibcon#about to read 6, iclass 30, count 0 2006.285.07:07:52.31#ibcon#read 6, iclass 30, count 0 2006.285.07:07:52.31#ibcon#end of sib2, iclass 30, count 0 2006.285.07:07:52.31#ibcon#*mode == 0, iclass 30, count 0 2006.285.07:07:52.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.07:07:52.31#ibcon#[25=USB\r\n] 2006.285.07:07:52.31#ibcon#*before write, iclass 30, count 0 2006.285.07:07:52.31#ibcon#enter sib2, iclass 30, count 0 2006.285.07:07:52.31#ibcon#flushed, iclass 30, count 0 2006.285.07:07:52.31#ibcon#about to write, iclass 30, count 0 2006.285.07:07:52.31#ibcon#wrote, iclass 30, count 0 2006.285.07:07:52.31#ibcon#about to read 3, iclass 30, count 0 2006.285.07:07:52.34#ibcon#read 3, iclass 30, count 0 2006.285.07:07:52.34#ibcon#about to read 4, iclass 30, count 0 2006.285.07:07:52.34#ibcon#read 4, iclass 30, count 0 2006.285.07:07:52.34#ibcon#about to read 5, iclass 30, count 0 2006.285.07:07:52.34#ibcon#read 5, iclass 30, count 0 2006.285.07:07:52.34#ibcon#about to read 6, iclass 30, count 0 2006.285.07:07:52.34#ibcon#read 6, iclass 30, count 0 2006.285.07:07:52.34#ibcon#end of sib2, iclass 30, count 0 2006.285.07:07:52.34#ibcon#*after write, iclass 30, count 0 2006.285.07:07:52.34#ibcon#*before return 0, iclass 30, count 0 2006.285.07:07:52.34#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:07:52.34#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:07:52.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.07:07:52.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.07:07:52.34$vck44/valo=6,814.99 2006.285.07:07:52.34#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.07:07:52.34#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.07:07:52.34#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:52.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:07:52.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:07:52.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:07:52.34#ibcon#enter wrdev, iclass 32, count 0 2006.285.07:07:52.34#ibcon#first serial, iclass 32, count 0 2006.285.07:07:52.34#ibcon#enter sib2, iclass 32, count 0 2006.285.07:07:52.34#ibcon#flushed, iclass 32, count 0 2006.285.07:07:52.34#ibcon#about to write, iclass 32, count 0 2006.285.07:07:52.34#ibcon#wrote, iclass 32, count 0 2006.285.07:07:52.34#ibcon#about to read 3, iclass 32, count 0 2006.285.07:07:52.36#ibcon#read 3, iclass 32, count 0 2006.285.07:07:52.36#ibcon#about to read 4, iclass 32, count 0 2006.285.07:07:52.36#ibcon#read 4, iclass 32, count 0 2006.285.07:07:52.36#ibcon#about to read 5, iclass 32, count 0 2006.285.07:07:52.36#ibcon#read 5, iclass 32, count 0 2006.285.07:07:52.36#ibcon#about to read 6, iclass 32, count 0 2006.285.07:07:52.36#ibcon#read 6, iclass 32, count 0 2006.285.07:07:52.36#ibcon#end of sib2, iclass 32, count 0 2006.285.07:07:52.36#ibcon#*mode == 0, iclass 32, count 0 2006.285.07:07:52.36#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.07:07:52.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:07:52.36#ibcon#*before write, iclass 32, count 0 2006.285.07:07:52.36#ibcon#enter sib2, iclass 32, count 0 2006.285.07:07:52.36#ibcon#flushed, iclass 32, count 0 2006.285.07:07:52.36#ibcon#about to write, iclass 32, count 0 2006.285.07:07:52.36#ibcon#wrote, iclass 32, count 0 2006.285.07:07:52.36#ibcon#about to read 3, iclass 32, count 0 2006.285.07:07:52.40#ibcon#read 3, iclass 32, count 0 2006.285.07:07:52.40#ibcon#about to read 4, iclass 32, count 0 2006.285.07:07:52.40#ibcon#read 4, iclass 32, count 0 2006.285.07:07:52.40#ibcon#about to read 5, iclass 32, count 0 2006.285.07:07:52.40#ibcon#read 5, iclass 32, count 0 2006.285.07:07:52.40#ibcon#about to read 6, iclass 32, count 0 2006.285.07:07:52.40#ibcon#read 6, iclass 32, count 0 2006.285.07:07:52.40#ibcon#end of sib2, iclass 32, count 0 2006.285.07:07:52.40#ibcon#*after write, iclass 32, count 0 2006.285.07:07:52.40#ibcon#*before return 0, iclass 32, count 0 2006.285.07:07:52.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:07:52.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:07:52.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.07:07:52.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.07:07:52.40$vck44/va=6,4 2006.285.07:07:52.40#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.07:07:52.40#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.07:07:52.40#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:52.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:07:52.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:07:52.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:07:52.46#ibcon#enter wrdev, iclass 34, count 2 2006.285.07:07:52.46#ibcon#first serial, iclass 34, count 2 2006.285.07:07:52.46#ibcon#enter sib2, iclass 34, count 2 2006.285.07:07:52.46#ibcon#flushed, iclass 34, count 2 2006.285.07:07:52.46#ibcon#about to write, iclass 34, count 2 2006.285.07:07:52.46#ibcon#wrote, iclass 34, count 2 2006.285.07:07:52.46#ibcon#about to read 3, iclass 34, count 2 2006.285.07:07:52.48#ibcon#read 3, iclass 34, count 2 2006.285.07:07:52.48#ibcon#about to read 4, iclass 34, count 2 2006.285.07:07:52.48#ibcon#read 4, iclass 34, count 2 2006.285.07:07:52.48#ibcon#about to read 5, iclass 34, count 2 2006.285.07:07:52.48#ibcon#read 5, iclass 34, count 2 2006.285.07:07:52.48#ibcon#about to read 6, iclass 34, count 2 2006.285.07:07:52.48#ibcon#read 6, iclass 34, count 2 2006.285.07:07:52.48#ibcon#end of sib2, iclass 34, count 2 2006.285.07:07:52.48#ibcon#*mode == 0, iclass 34, count 2 2006.285.07:07:52.48#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.07:07:52.48#ibcon#[25=AT06-04\r\n] 2006.285.07:07:52.48#ibcon#*before write, iclass 34, count 2 2006.285.07:07:52.48#ibcon#enter sib2, iclass 34, count 2 2006.285.07:07:52.48#ibcon#flushed, iclass 34, count 2 2006.285.07:07:52.48#ibcon#about to write, iclass 34, count 2 2006.285.07:07:52.48#ibcon#wrote, iclass 34, count 2 2006.285.07:07:52.48#ibcon#about to read 3, iclass 34, count 2 2006.285.07:07:52.51#ibcon#read 3, iclass 34, count 2 2006.285.07:07:52.51#ibcon#about to read 4, iclass 34, count 2 2006.285.07:07:52.51#ibcon#read 4, iclass 34, count 2 2006.285.07:07:52.51#ibcon#about to read 5, iclass 34, count 2 2006.285.07:07:52.51#ibcon#read 5, iclass 34, count 2 2006.285.07:07:52.51#ibcon#about to read 6, iclass 34, count 2 2006.285.07:07:52.51#ibcon#read 6, iclass 34, count 2 2006.285.07:07:52.51#ibcon#end of sib2, iclass 34, count 2 2006.285.07:07:52.51#ibcon#*after write, iclass 34, count 2 2006.285.07:07:52.51#ibcon#*before return 0, iclass 34, count 2 2006.285.07:07:52.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:07:52.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:07:52.51#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.07:07:52.51#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:52.51#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:07:52.63#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:07:52.63#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:07:52.63#ibcon#enter wrdev, iclass 34, count 0 2006.285.07:07:52.63#ibcon#first serial, iclass 34, count 0 2006.285.07:07:52.63#ibcon#enter sib2, iclass 34, count 0 2006.285.07:07:52.63#ibcon#flushed, iclass 34, count 0 2006.285.07:07:52.63#ibcon#about to write, iclass 34, count 0 2006.285.07:07:52.63#ibcon#wrote, iclass 34, count 0 2006.285.07:07:52.63#ibcon#about to read 3, iclass 34, count 0 2006.285.07:07:52.65#ibcon#read 3, iclass 34, count 0 2006.285.07:07:52.65#ibcon#about to read 4, iclass 34, count 0 2006.285.07:07:52.65#ibcon#read 4, iclass 34, count 0 2006.285.07:07:52.65#ibcon#about to read 5, iclass 34, count 0 2006.285.07:07:52.65#ibcon#read 5, iclass 34, count 0 2006.285.07:07:52.65#ibcon#about to read 6, iclass 34, count 0 2006.285.07:07:52.65#ibcon#read 6, iclass 34, count 0 2006.285.07:07:52.65#ibcon#end of sib2, iclass 34, count 0 2006.285.07:07:52.65#ibcon#*mode == 0, iclass 34, count 0 2006.285.07:07:52.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.07:07:52.65#ibcon#[25=USB\r\n] 2006.285.07:07:52.65#ibcon#*before write, iclass 34, count 0 2006.285.07:07:52.65#ibcon#enter sib2, iclass 34, count 0 2006.285.07:07:52.65#ibcon#flushed, iclass 34, count 0 2006.285.07:07:52.65#ibcon#about to write, iclass 34, count 0 2006.285.07:07:52.65#ibcon#wrote, iclass 34, count 0 2006.285.07:07:52.65#ibcon#about to read 3, iclass 34, count 0 2006.285.07:07:52.68#ibcon#read 3, iclass 34, count 0 2006.285.07:07:52.68#ibcon#about to read 4, iclass 34, count 0 2006.285.07:07:52.68#ibcon#read 4, iclass 34, count 0 2006.285.07:07:52.68#ibcon#about to read 5, iclass 34, count 0 2006.285.07:07:52.68#ibcon#read 5, iclass 34, count 0 2006.285.07:07:52.68#ibcon#about to read 6, iclass 34, count 0 2006.285.07:07:52.68#ibcon#read 6, iclass 34, count 0 2006.285.07:07:52.68#ibcon#end of sib2, iclass 34, count 0 2006.285.07:07:52.68#ibcon#*after write, iclass 34, count 0 2006.285.07:07:52.68#ibcon#*before return 0, iclass 34, count 0 2006.285.07:07:52.68#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:07:52.68#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:07:52.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.07:07:52.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.07:07:52.68$vck44/valo=7,864.99 2006.285.07:07:52.68#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.07:07:52.68#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.07:07:52.68#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:52.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:07:52.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:07:52.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:07:52.68#ibcon#enter wrdev, iclass 36, count 0 2006.285.07:07:52.68#ibcon#first serial, iclass 36, count 0 2006.285.07:07:52.68#ibcon#enter sib2, iclass 36, count 0 2006.285.07:07:52.68#ibcon#flushed, iclass 36, count 0 2006.285.07:07:52.68#ibcon#about to write, iclass 36, count 0 2006.285.07:07:52.68#ibcon#wrote, iclass 36, count 0 2006.285.07:07:52.68#ibcon#about to read 3, iclass 36, count 0 2006.285.07:07:52.70#ibcon#read 3, iclass 36, count 0 2006.285.07:07:52.70#ibcon#about to read 4, iclass 36, count 0 2006.285.07:07:52.70#ibcon#read 4, iclass 36, count 0 2006.285.07:07:52.70#ibcon#about to read 5, iclass 36, count 0 2006.285.07:07:52.70#ibcon#read 5, iclass 36, count 0 2006.285.07:07:52.70#ibcon#about to read 6, iclass 36, count 0 2006.285.07:07:52.70#ibcon#read 6, iclass 36, count 0 2006.285.07:07:52.70#ibcon#end of sib2, iclass 36, count 0 2006.285.07:07:52.70#ibcon#*mode == 0, iclass 36, count 0 2006.285.07:07:52.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.07:07:52.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:07:52.70#ibcon#*before write, iclass 36, count 0 2006.285.07:07:52.70#ibcon#enter sib2, iclass 36, count 0 2006.285.07:07:52.70#ibcon#flushed, iclass 36, count 0 2006.285.07:07:52.70#ibcon#about to write, iclass 36, count 0 2006.285.07:07:52.70#ibcon#wrote, iclass 36, count 0 2006.285.07:07:52.70#ibcon#about to read 3, iclass 36, count 0 2006.285.07:07:52.74#ibcon#read 3, iclass 36, count 0 2006.285.07:07:52.74#ibcon#about to read 4, iclass 36, count 0 2006.285.07:07:52.74#ibcon#read 4, iclass 36, count 0 2006.285.07:07:52.74#ibcon#about to read 5, iclass 36, count 0 2006.285.07:07:52.74#ibcon#read 5, iclass 36, count 0 2006.285.07:07:52.74#ibcon#about to read 6, iclass 36, count 0 2006.285.07:07:52.74#ibcon#read 6, iclass 36, count 0 2006.285.07:07:52.74#ibcon#end of sib2, iclass 36, count 0 2006.285.07:07:52.74#ibcon#*after write, iclass 36, count 0 2006.285.07:07:52.74#ibcon#*before return 0, iclass 36, count 0 2006.285.07:07:52.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:07:52.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:07:52.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.07:07:52.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.07:07:52.74$vck44/va=7,4 2006.285.07:07:52.74#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.07:07:52.74#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.07:07:52.74#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:52.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:07:52.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:07:52.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:07:52.80#ibcon#enter wrdev, iclass 38, count 2 2006.285.07:07:52.80#ibcon#first serial, iclass 38, count 2 2006.285.07:07:52.80#ibcon#enter sib2, iclass 38, count 2 2006.285.07:07:52.80#ibcon#flushed, iclass 38, count 2 2006.285.07:07:52.80#ibcon#about to write, iclass 38, count 2 2006.285.07:07:52.80#ibcon#wrote, iclass 38, count 2 2006.285.07:07:52.80#ibcon#about to read 3, iclass 38, count 2 2006.285.07:07:52.82#ibcon#read 3, iclass 38, count 2 2006.285.07:07:52.82#ibcon#about to read 4, iclass 38, count 2 2006.285.07:07:52.82#ibcon#read 4, iclass 38, count 2 2006.285.07:07:52.82#ibcon#about to read 5, iclass 38, count 2 2006.285.07:07:52.82#ibcon#read 5, iclass 38, count 2 2006.285.07:07:52.82#ibcon#about to read 6, iclass 38, count 2 2006.285.07:07:52.82#ibcon#read 6, iclass 38, count 2 2006.285.07:07:52.82#ibcon#end of sib2, iclass 38, count 2 2006.285.07:07:52.82#ibcon#*mode == 0, iclass 38, count 2 2006.285.07:07:52.82#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.07:07:52.82#ibcon#[25=AT07-04\r\n] 2006.285.07:07:52.82#ibcon#*before write, iclass 38, count 2 2006.285.07:07:52.82#ibcon#enter sib2, iclass 38, count 2 2006.285.07:07:52.82#ibcon#flushed, iclass 38, count 2 2006.285.07:07:52.82#ibcon#about to write, iclass 38, count 2 2006.285.07:07:52.82#ibcon#wrote, iclass 38, count 2 2006.285.07:07:52.82#ibcon#about to read 3, iclass 38, count 2 2006.285.07:07:52.85#ibcon#read 3, iclass 38, count 2 2006.285.07:07:52.85#ibcon#about to read 4, iclass 38, count 2 2006.285.07:07:52.85#ibcon#read 4, iclass 38, count 2 2006.285.07:07:52.85#ibcon#about to read 5, iclass 38, count 2 2006.285.07:07:52.85#ibcon#read 5, iclass 38, count 2 2006.285.07:07:52.85#ibcon#about to read 6, iclass 38, count 2 2006.285.07:07:52.85#ibcon#read 6, iclass 38, count 2 2006.285.07:07:52.85#ibcon#end of sib2, iclass 38, count 2 2006.285.07:07:52.85#ibcon#*after write, iclass 38, count 2 2006.285.07:07:52.85#ibcon#*before return 0, iclass 38, count 2 2006.285.07:07:52.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:07:52.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:07:52.85#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.07:07:52.85#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:52.85#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:07:52.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:07:52.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:07:52.97#ibcon#enter wrdev, iclass 38, count 0 2006.285.07:07:52.97#ibcon#first serial, iclass 38, count 0 2006.285.07:07:52.97#ibcon#enter sib2, iclass 38, count 0 2006.285.07:07:52.97#ibcon#flushed, iclass 38, count 0 2006.285.07:07:52.97#ibcon#about to write, iclass 38, count 0 2006.285.07:07:52.97#ibcon#wrote, iclass 38, count 0 2006.285.07:07:52.97#ibcon#about to read 3, iclass 38, count 0 2006.285.07:07:52.99#ibcon#read 3, iclass 38, count 0 2006.285.07:07:52.99#ibcon#about to read 4, iclass 38, count 0 2006.285.07:07:52.99#ibcon#read 4, iclass 38, count 0 2006.285.07:07:52.99#ibcon#about to read 5, iclass 38, count 0 2006.285.07:07:52.99#ibcon#read 5, iclass 38, count 0 2006.285.07:07:52.99#ibcon#about to read 6, iclass 38, count 0 2006.285.07:07:52.99#ibcon#read 6, iclass 38, count 0 2006.285.07:07:52.99#ibcon#end of sib2, iclass 38, count 0 2006.285.07:07:52.99#ibcon#*mode == 0, iclass 38, count 0 2006.285.07:07:52.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.07:07:52.99#ibcon#[25=USB\r\n] 2006.285.07:07:52.99#ibcon#*before write, iclass 38, count 0 2006.285.07:07:52.99#ibcon#enter sib2, iclass 38, count 0 2006.285.07:07:52.99#ibcon#flushed, iclass 38, count 0 2006.285.07:07:52.99#ibcon#about to write, iclass 38, count 0 2006.285.07:07:52.99#ibcon#wrote, iclass 38, count 0 2006.285.07:07:52.99#ibcon#about to read 3, iclass 38, count 0 2006.285.07:07:53.02#ibcon#read 3, iclass 38, count 0 2006.285.07:07:53.02#ibcon#about to read 4, iclass 38, count 0 2006.285.07:07:53.02#ibcon#read 4, iclass 38, count 0 2006.285.07:07:53.02#ibcon#about to read 5, iclass 38, count 0 2006.285.07:07:53.02#ibcon#read 5, iclass 38, count 0 2006.285.07:07:53.02#ibcon#about to read 6, iclass 38, count 0 2006.285.07:07:53.02#ibcon#read 6, iclass 38, count 0 2006.285.07:07:53.02#ibcon#end of sib2, iclass 38, count 0 2006.285.07:07:53.02#ibcon#*after write, iclass 38, count 0 2006.285.07:07:53.02#ibcon#*before return 0, iclass 38, count 0 2006.285.07:07:53.02#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:07:53.02#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:07:53.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.07:07:53.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.07:07:53.02$vck44/valo=8,884.99 2006.285.07:07:53.02#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.07:07:53.02#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.07:07:53.02#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:53.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:07:53.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:07:53.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:07:53.02#ibcon#enter wrdev, iclass 40, count 0 2006.285.07:07:53.02#ibcon#first serial, iclass 40, count 0 2006.285.07:07:53.02#ibcon#enter sib2, iclass 40, count 0 2006.285.07:07:53.02#ibcon#flushed, iclass 40, count 0 2006.285.07:07:53.02#ibcon#about to write, iclass 40, count 0 2006.285.07:07:53.02#ibcon#wrote, iclass 40, count 0 2006.285.07:07:53.02#ibcon#about to read 3, iclass 40, count 0 2006.285.07:07:53.04#ibcon#read 3, iclass 40, count 0 2006.285.07:07:53.04#ibcon#about to read 4, iclass 40, count 0 2006.285.07:07:53.04#ibcon#read 4, iclass 40, count 0 2006.285.07:07:53.04#ibcon#about to read 5, iclass 40, count 0 2006.285.07:07:53.04#ibcon#read 5, iclass 40, count 0 2006.285.07:07:53.04#ibcon#about to read 6, iclass 40, count 0 2006.285.07:07:53.04#ibcon#read 6, iclass 40, count 0 2006.285.07:07:53.04#ibcon#end of sib2, iclass 40, count 0 2006.285.07:07:53.04#ibcon#*mode == 0, iclass 40, count 0 2006.285.07:07:53.04#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.07:07:53.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:07:53.04#ibcon#*before write, iclass 40, count 0 2006.285.07:07:53.04#ibcon#enter sib2, iclass 40, count 0 2006.285.07:07:53.04#ibcon#flushed, iclass 40, count 0 2006.285.07:07:53.04#ibcon#about to write, iclass 40, count 0 2006.285.07:07:53.04#ibcon#wrote, iclass 40, count 0 2006.285.07:07:53.04#ibcon#about to read 3, iclass 40, count 0 2006.285.07:07:53.08#ibcon#read 3, iclass 40, count 0 2006.285.07:07:53.08#ibcon#about to read 4, iclass 40, count 0 2006.285.07:07:53.08#ibcon#read 4, iclass 40, count 0 2006.285.07:07:53.08#ibcon#about to read 5, iclass 40, count 0 2006.285.07:07:53.08#ibcon#read 5, iclass 40, count 0 2006.285.07:07:53.08#ibcon#about to read 6, iclass 40, count 0 2006.285.07:07:53.08#ibcon#read 6, iclass 40, count 0 2006.285.07:07:53.08#ibcon#end of sib2, iclass 40, count 0 2006.285.07:07:53.08#ibcon#*after write, iclass 40, count 0 2006.285.07:07:53.08#ibcon#*before return 0, iclass 40, count 0 2006.285.07:07:53.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:07:53.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:07:53.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.07:07:53.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.07:07:53.08$vck44/va=8,3 2006.285.07:07:53.08#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.07:07:53.08#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.07:07:53.08#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:53.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:07:53.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:07:53.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:07:53.14#ibcon#enter wrdev, iclass 4, count 2 2006.285.07:07:53.14#ibcon#first serial, iclass 4, count 2 2006.285.07:07:53.14#ibcon#enter sib2, iclass 4, count 2 2006.285.07:07:53.14#ibcon#flushed, iclass 4, count 2 2006.285.07:07:53.14#ibcon#about to write, iclass 4, count 2 2006.285.07:07:53.14#ibcon#wrote, iclass 4, count 2 2006.285.07:07:53.14#ibcon#about to read 3, iclass 4, count 2 2006.285.07:07:53.16#ibcon#read 3, iclass 4, count 2 2006.285.07:07:53.16#ibcon#about to read 4, iclass 4, count 2 2006.285.07:07:53.16#ibcon#read 4, iclass 4, count 2 2006.285.07:07:53.16#ibcon#about to read 5, iclass 4, count 2 2006.285.07:07:53.16#ibcon#read 5, iclass 4, count 2 2006.285.07:07:53.16#ibcon#about to read 6, iclass 4, count 2 2006.285.07:07:53.16#ibcon#read 6, iclass 4, count 2 2006.285.07:07:53.16#ibcon#end of sib2, iclass 4, count 2 2006.285.07:07:53.16#ibcon#*mode == 0, iclass 4, count 2 2006.285.07:07:53.16#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.07:07:53.16#ibcon#[25=AT08-03\r\n] 2006.285.07:07:53.16#ibcon#*before write, iclass 4, count 2 2006.285.07:07:53.16#ibcon#enter sib2, iclass 4, count 2 2006.285.07:07:53.16#ibcon#flushed, iclass 4, count 2 2006.285.07:07:53.16#ibcon#about to write, iclass 4, count 2 2006.285.07:07:53.16#ibcon#wrote, iclass 4, count 2 2006.285.07:07:53.16#ibcon#about to read 3, iclass 4, count 2 2006.285.07:07:53.19#ibcon#read 3, iclass 4, count 2 2006.285.07:07:53.19#ibcon#about to read 4, iclass 4, count 2 2006.285.07:07:53.19#ibcon#read 4, iclass 4, count 2 2006.285.07:07:53.19#ibcon#about to read 5, iclass 4, count 2 2006.285.07:07:53.19#ibcon#read 5, iclass 4, count 2 2006.285.07:07:53.19#ibcon#about to read 6, iclass 4, count 2 2006.285.07:07:53.19#ibcon#read 6, iclass 4, count 2 2006.285.07:07:53.19#ibcon#end of sib2, iclass 4, count 2 2006.285.07:07:53.19#ibcon#*after write, iclass 4, count 2 2006.285.07:07:53.19#ibcon#*before return 0, iclass 4, count 2 2006.285.07:07:53.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:07:53.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:07:53.19#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.07:07:53.19#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:53.19#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:07:53.31#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:07:53.31#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:07:53.31#ibcon#enter wrdev, iclass 4, count 0 2006.285.07:07:53.31#ibcon#first serial, iclass 4, count 0 2006.285.07:07:53.31#ibcon#enter sib2, iclass 4, count 0 2006.285.07:07:53.31#ibcon#flushed, iclass 4, count 0 2006.285.07:07:53.31#ibcon#about to write, iclass 4, count 0 2006.285.07:07:53.31#ibcon#wrote, iclass 4, count 0 2006.285.07:07:53.31#ibcon#about to read 3, iclass 4, count 0 2006.285.07:07:53.33#ibcon#read 3, iclass 4, count 0 2006.285.07:07:53.33#ibcon#about to read 4, iclass 4, count 0 2006.285.07:07:53.33#ibcon#read 4, iclass 4, count 0 2006.285.07:07:53.33#ibcon#about to read 5, iclass 4, count 0 2006.285.07:07:53.33#ibcon#read 5, iclass 4, count 0 2006.285.07:07:53.33#ibcon#about to read 6, iclass 4, count 0 2006.285.07:07:53.33#ibcon#read 6, iclass 4, count 0 2006.285.07:07:53.33#ibcon#end of sib2, iclass 4, count 0 2006.285.07:07:53.33#ibcon#*mode == 0, iclass 4, count 0 2006.285.07:07:53.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.07:07:53.33#ibcon#[25=USB\r\n] 2006.285.07:07:53.33#ibcon#*before write, iclass 4, count 0 2006.285.07:07:53.33#ibcon#enter sib2, iclass 4, count 0 2006.285.07:07:53.33#ibcon#flushed, iclass 4, count 0 2006.285.07:07:53.33#ibcon#about to write, iclass 4, count 0 2006.285.07:07:53.33#ibcon#wrote, iclass 4, count 0 2006.285.07:07:53.33#ibcon#about to read 3, iclass 4, count 0 2006.285.07:07:53.36#ibcon#read 3, iclass 4, count 0 2006.285.07:07:53.36#ibcon#about to read 4, iclass 4, count 0 2006.285.07:07:53.36#ibcon#read 4, iclass 4, count 0 2006.285.07:07:53.36#ibcon#about to read 5, iclass 4, count 0 2006.285.07:07:53.36#ibcon#read 5, iclass 4, count 0 2006.285.07:07:53.36#ibcon#about to read 6, iclass 4, count 0 2006.285.07:07:53.36#ibcon#read 6, iclass 4, count 0 2006.285.07:07:53.36#ibcon#end of sib2, iclass 4, count 0 2006.285.07:07:53.36#ibcon#*after write, iclass 4, count 0 2006.285.07:07:53.36#ibcon#*before return 0, iclass 4, count 0 2006.285.07:07:53.36#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:07:53.36#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:07:53.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.07:07:53.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.07:07:53.36$vck44/vblo=1,629.99 2006.285.07:07:53.36#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.07:07:53.36#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.07:07:53.36#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:53.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:07:53.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:07:53.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:07:53.36#ibcon#enter wrdev, iclass 6, count 0 2006.285.07:07:53.36#ibcon#first serial, iclass 6, count 0 2006.285.07:07:53.36#ibcon#enter sib2, iclass 6, count 0 2006.285.07:07:53.36#ibcon#flushed, iclass 6, count 0 2006.285.07:07:53.36#ibcon#about to write, iclass 6, count 0 2006.285.07:07:53.36#ibcon#wrote, iclass 6, count 0 2006.285.07:07:53.36#ibcon#about to read 3, iclass 6, count 0 2006.285.07:07:53.38#ibcon#read 3, iclass 6, count 0 2006.285.07:07:53.38#ibcon#about to read 4, iclass 6, count 0 2006.285.07:07:53.38#ibcon#read 4, iclass 6, count 0 2006.285.07:07:53.38#ibcon#about to read 5, iclass 6, count 0 2006.285.07:07:53.38#ibcon#read 5, iclass 6, count 0 2006.285.07:07:53.38#ibcon#about to read 6, iclass 6, count 0 2006.285.07:07:53.38#ibcon#read 6, iclass 6, count 0 2006.285.07:07:53.38#ibcon#end of sib2, iclass 6, count 0 2006.285.07:07:53.38#ibcon#*mode == 0, iclass 6, count 0 2006.285.07:07:53.38#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.07:07:53.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:07:53.38#ibcon#*before write, iclass 6, count 0 2006.285.07:07:53.38#ibcon#enter sib2, iclass 6, count 0 2006.285.07:07:53.38#ibcon#flushed, iclass 6, count 0 2006.285.07:07:53.38#ibcon#about to write, iclass 6, count 0 2006.285.07:07:53.38#ibcon#wrote, iclass 6, count 0 2006.285.07:07:53.38#ibcon#about to read 3, iclass 6, count 0 2006.285.07:07:53.42#ibcon#read 3, iclass 6, count 0 2006.285.07:07:53.42#ibcon#about to read 4, iclass 6, count 0 2006.285.07:07:53.42#ibcon#read 4, iclass 6, count 0 2006.285.07:07:53.42#ibcon#about to read 5, iclass 6, count 0 2006.285.07:07:53.42#ibcon#read 5, iclass 6, count 0 2006.285.07:07:53.42#ibcon#about to read 6, iclass 6, count 0 2006.285.07:07:53.42#ibcon#read 6, iclass 6, count 0 2006.285.07:07:53.42#ibcon#end of sib2, iclass 6, count 0 2006.285.07:07:53.42#ibcon#*after write, iclass 6, count 0 2006.285.07:07:53.42#ibcon#*before return 0, iclass 6, count 0 2006.285.07:07:53.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:07:53.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:07:53.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.07:07:53.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.07:07:53.42$vck44/vb=1,4 2006.285.07:07:53.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.07:07:53.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.07:07:53.42#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:53.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:07:53.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:07:53.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:07:53.42#ibcon#enter wrdev, iclass 10, count 2 2006.285.07:07:53.42#ibcon#first serial, iclass 10, count 2 2006.285.07:07:53.42#ibcon#enter sib2, iclass 10, count 2 2006.285.07:07:53.42#ibcon#flushed, iclass 10, count 2 2006.285.07:07:53.42#ibcon#about to write, iclass 10, count 2 2006.285.07:07:53.42#ibcon#wrote, iclass 10, count 2 2006.285.07:07:53.42#ibcon#about to read 3, iclass 10, count 2 2006.285.07:07:53.44#ibcon#read 3, iclass 10, count 2 2006.285.07:07:53.44#ibcon#about to read 4, iclass 10, count 2 2006.285.07:07:53.44#ibcon#read 4, iclass 10, count 2 2006.285.07:07:53.44#ibcon#about to read 5, iclass 10, count 2 2006.285.07:07:53.44#ibcon#read 5, iclass 10, count 2 2006.285.07:07:53.44#ibcon#about to read 6, iclass 10, count 2 2006.285.07:07:53.44#ibcon#read 6, iclass 10, count 2 2006.285.07:07:53.44#ibcon#end of sib2, iclass 10, count 2 2006.285.07:07:53.44#ibcon#*mode == 0, iclass 10, count 2 2006.285.07:07:53.44#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.07:07:53.44#ibcon#[27=AT01-04\r\n] 2006.285.07:07:53.44#ibcon#*before write, iclass 10, count 2 2006.285.07:07:53.44#ibcon#enter sib2, iclass 10, count 2 2006.285.07:07:53.44#ibcon#flushed, iclass 10, count 2 2006.285.07:07:53.44#ibcon#about to write, iclass 10, count 2 2006.285.07:07:53.44#ibcon#wrote, iclass 10, count 2 2006.285.07:07:53.44#ibcon#about to read 3, iclass 10, count 2 2006.285.07:07:53.47#ibcon#read 3, iclass 10, count 2 2006.285.07:07:53.47#ibcon#about to read 4, iclass 10, count 2 2006.285.07:07:53.47#ibcon#read 4, iclass 10, count 2 2006.285.07:07:53.47#ibcon#about to read 5, iclass 10, count 2 2006.285.07:07:53.47#ibcon#read 5, iclass 10, count 2 2006.285.07:07:53.47#ibcon#about to read 6, iclass 10, count 2 2006.285.07:07:53.47#ibcon#read 6, iclass 10, count 2 2006.285.07:07:53.47#ibcon#end of sib2, iclass 10, count 2 2006.285.07:07:53.47#ibcon#*after write, iclass 10, count 2 2006.285.07:07:53.47#ibcon#*before return 0, iclass 10, count 2 2006.285.07:07:53.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:07:53.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:07:53.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.07:07:53.47#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:53.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:07:53.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:07:53.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:07:53.59#ibcon#enter wrdev, iclass 10, count 0 2006.285.07:07:53.59#ibcon#first serial, iclass 10, count 0 2006.285.07:07:53.59#ibcon#enter sib2, iclass 10, count 0 2006.285.07:07:53.59#ibcon#flushed, iclass 10, count 0 2006.285.07:07:53.59#ibcon#about to write, iclass 10, count 0 2006.285.07:07:53.59#ibcon#wrote, iclass 10, count 0 2006.285.07:07:53.59#ibcon#about to read 3, iclass 10, count 0 2006.285.07:07:53.61#ibcon#read 3, iclass 10, count 0 2006.285.07:07:53.61#ibcon#about to read 4, iclass 10, count 0 2006.285.07:07:53.61#ibcon#read 4, iclass 10, count 0 2006.285.07:07:53.61#ibcon#about to read 5, iclass 10, count 0 2006.285.07:07:53.61#ibcon#read 5, iclass 10, count 0 2006.285.07:07:53.61#ibcon#about to read 6, iclass 10, count 0 2006.285.07:07:53.61#ibcon#read 6, iclass 10, count 0 2006.285.07:07:53.61#ibcon#end of sib2, iclass 10, count 0 2006.285.07:07:53.61#ibcon#*mode == 0, iclass 10, count 0 2006.285.07:07:53.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.07:07:53.61#ibcon#[27=USB\r\n] 2006.285.07:07:53.61#ibcon#*before write, iclass 10, count 0 2006.285.07:07:53.61#ibcon#enter sib2, iclass 10, count 0 2006.285.07:07:53.61#ibcon#flushed, iclass 10, count 0 2006.285.07:07:53.61#ibcon#about to write, iclass 10, count 0 2006.285.07:07:53.61#ibcon#wrote, iclass 10, count 0 2006.285.07:07:53.61#ibcon#about to read 3, iclass 10, count 0 2006.285.07:07:53.64#ibcon#read 3, iclass 10, count 0 2006.285.07:07:53.64#ibcon#about to read 4, iclass 10, count 0 2006.285.07:07:53.64#ibcon#read 4, iclass 10, count 0 2006.285.07:07:53.64#ibcon#about to read 5, iclass 10, count 0 2006.285.07:07:53.64#ibcon#read 5, iclass 10, count 0 2006.285.07:07:53.64#ibcon#about to read 6, iclass 10, count 0 2006.285.07:07:53.64#ibcon#read 6, iclass 10, count 0 2006.285.07:07:53.64#ibcon#end of sib2, iclass 10, count 0 2006.285.07:07:53.64#ibcon#*after write, iclass 10, count 0 2006.285.07:07:53.64#ibcon#*before return 0, iclass 10, count 0 2006.285.07:07:53.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:07:53.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:07:53.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.07:07:53.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.07:07:53.64$vck44/vblo=2,634.99 2006.285.07:07:53.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.07:07:53.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.07:07:53.64#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:53.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:07:53.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:07:53.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:07:53.64#ibcon#enter wrdev, iclass 12, count 0 2006.285.07:07:53.64#ibcon#first serial, iclass 12, count 0 2006.285.07:07:53.64#ibcon#enter sib2, iclass 12, count 0 2006.285.07:07:53.64#ibcon#flushed, iclass 12, count 0 2006.285.07:07:53.64#ibcon#about to write, iclass 12, count 0 2006.285.07:07:53.64#ibcon#wrote, iclass 12, count 0 2006.285.07:07:53.64#ibcon#about to read 3, iclass 12, count 0 2006.285.07:07:53.66#ibcon#read 3, iclass 12, count 0 2006.285.07:07:53.66#ibcon#about to read 4, iclass 12, count 0 2006.285.07:07:53.66#ibcon#read 4, iclass 12, count 0 2006.285.07:07:53.66#ibcon#about to read 5, iclass 12, count 0 2006.285.07:07:53.66#ibcon#read 5, iclass 12, count 0 2006.285.07:07:53.66#ibcon#about to read 6, iclass 12, count 0 2006.285.07:07:53.66#ibcon#read 6, iclass 12, count 0 2006.285.07:07:53.66#ibcon#end of sib2, iclass 12, count 0 2006.285.07:07:53.66#ibcon#*mode == 0, iclass 12, count 0 2006.285.07:07:53.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.07:07:53.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:07:53.66#ibcon#*before write, iclass 12, count 0 2006.285.07:07:53.66#ibcon#enter sib2, iclass 12, count 0 2006.285.07:07:53.66#ibcon#flushed, iclass 12, count 0 2006.285.07:07:53.66#ibcon#about to write, iclass 12, count 0 2006.285.07:07:53.66#ibcon#wrote, iclass 12, count 0 2006.285.07:07:53.66#ibcon#about to read 3, iclass 12, count 0 2006.285.07:07:53.70#ibcon#read 3, iclass 12, count 0 2006.285.07:07:53.70#ibcon#about to read 4, iclass 12, count 0 2006.285.07:07:53.70#ibcon#read 4, iclass 12, count 0 2006.285.07:07:53.70#ibcon#about to read 5, iclass 12, count 0 2006.285.07:07:53.70#ibcon#read 5, iclass 12, count 0 2006.285.07:07:53.70#ibcon#about to read 6, iclass 12, count 0 2006.285.07:07:53.70#ibcon#read 6, iclass 12, count 0 2006.285.07:07:53.70#ibcon#end of sib2, iclass 12, count 0 2006.285.07:07:53.70#ibcon#*after write, iclass 12, count 0 2006.285.07:07:53.70#ibcon#*before return 0, iclass 12, count 0 2006.285.07:07:53.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:07:53.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:07:53.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.07:07:53.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.07:07:53.70$vck44/vb=2,5 2006.285.07:07:53.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.07:07:53.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.07:07:53.70#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:53.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:07:53.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:07:53.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:07:53.76#ibcon#enter wrdev, iclass 14, count 2 2006.285.07:07:53.76#ibcon#first serial, iclass 14, count 2 2006.285.07:07:53.76#ibcon#enter sib2, iclass 14, count 2 2006.285.07:07:53.76#ibcon#flushed, iclass 14, count 2 2006.285.07:07:53.76#ibcon#about to write, iclass 14, count 2 2006.285.07:07:53.76#ibcon#wrote, iclass 14, count 2 2006.285.07:07:53.76#ibcon#about to read 3, iclass 14, count 2 2006.285.07:07:53.78#ibcon#read 3, iclass 14, count 2 2006.285.07:07:53.78#ibcon#about to read 4, iclass 14, count 2 2006.285.07:07:53.78#ibcon#read 4, iclass 14, count 2 2006.285.07:07:53.78#ibcon#about to read 5, iclass 14, count 2 2006.285.07:07:53.78#ibcon#read 5, iclass 14, count 2 2006.285.07:07:53.78#ibcon#about to read 6, iclass 14, count 2 2006.285.07:07:53.78#ibcon#read 6, iclass 14, count 2 2006.285.07:07:53.78#ibcon#end of sib2, iclass 14, count 2 2006.285.07:07:53.78#ibcon#*mode == 0, iclass 14, count 2 2006.285.07:07:53.78#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.07:07:53.78#ibcon#[27=AT02-05\r\n] 2006.285.07:07:53.78#ibcon#*before write, iclass 14, count 2 2006.285.07:07:53.78#ibcon#enter sib2, iclass 14, count 2 2006.285.07:07:53.78#ibcon#flushed, iclass 14, count 2 2006.285.07:07:53.78#ibcon#about to write, iclass 14, count 2 2006.285.07:07:53.78#ibcon#wrote, iclass 14, count 2 2006.285.07:07:53.78#ibcon#about to read 3, iclass 14, count 2 2006.285.07:07:53.81#ibcon#read 3, iclass 14, count 2 2006.285.07:07:53.81#ibcon#about to read 4, iclass 14, count 2 2006.285.07:07:53.81#ibcon#read 4, iclass 14, count 2 2006.285.07:07:53.81#ibcon#about to read 5, iclass 14, count 2 2006.285.07:07:53.81#ibcon#read 5, iclass 14, count 2 2006.285.07:07:53.81#ibcon#about to read 6, iclass 14, count 2 2006.285.07:07:53.81#ibcon#read 6, iclass 14, count 2 2006.285.07:07:53.81#ibcon#end of sib2, iclass 14, count 2 2006.285.07:07:53.81#ibcon#*after write, iclass 14, count 2 2006.285.07:07:53.81#ibcon#*before return 0, iclass 14, count 2 2006.285.07:07:53.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:07:53.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:07:53.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.07:07:53.81#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:53.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:07:53.93#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:07:53.93#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:07:53.93#ibcon#enter wrdev, iclass 14, count 0 2006.285.07:07:53.93#ibcon#first serial, iclass 14, count 0 2006.285.07:07:53.93#ibcon#enter sib2, iclass 14, count 0 2006.285.07:07:53.93#ibcon#flushed, iclass 14, count 0 2006.285.07:07:53.93#ibcon#about to write, iclass 14, count 0 2006.285.07:07:53.93#ibcon#wrote, iclass 14, count 0 2006.285.07:07:53.93#ibcon#about to read 3, iclass 14, count 0 2006.285.07:07:53.95#ibcon#read 3, iclass 14, count 0 2006.285.07:07:53.95#ibcon#about to read 4, iclass 14, count 0 2006.285.07:07:53.95#ibcon#read 4, iclass 14, count 0 2006.285.07:07:53.95#ibcon#about to read 5, iclass 14, count 0 2006.285.07:07:53.95#ibcon#read 5, iclass 14, count 0 2006.285.07:07:53.95#ibcon#about to read 6, iclass 14, count 0 2006.285.07:07:53.95#ibcon#read 6, iclass 14, count 0 2006.285.07:07:53.95#ibcon#end of sib2, iclass 14, count 0 2006.285.07:07:53.95#ibcon#*mode == 0, iclass 14, count 0 2006.285.07:07:53.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.07:07:53.95#ibcon#[27=USB\r\n] 2006.285.07:07:53.95#ibcon#*before write, iclass 14, count 0 2006.285.07:07:53.95#ibcon#enter sib2, iclass 14, count 0 2006.285.07:07:53.95#ibcon#flushed, iclass 14, count 0 2006.285.07:07:53.95#ibcon#about to write, iclass 14, count 0 2006.285.07:07:53.95#ibcon#wrote, iclass 14, count 0 2006.285.07:07:53.95#ibcon#about to read 3, iclass 14, count 0 2006.285.07:07:53.98#ibcon#read 3, iclass 14, count 0 2006.285.07:07:53.98#ibcon#about to read 4, iclass 14, count 0 2006.285.07:07:53.98#ibcon#read 4, iclass 14, count 0 2006.285.07:07:53.98#ibcon#about to read 5, iclass 14, count 0 2006.285.07:07:53.98#ibcon#read 5, iclass 14, count 0 2006.285.07:07:53.98#ibcon#about to read 6, iclass 14, count 0 2006.285.07:07:53.98#ibcon#read 6, iclass 14, count 0 2006.285.07:07:53.98#ibcon#end of sib2, iclass 14, count 0 2006.285.07:07:53.98#ibcon#*after write, iclass 14, count 0 2006.285.07:07:53.98#ibcon#*before return 0, iclass 14, count 0 2006.285.07:07:53.98#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:07:53.98#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:07:53.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.07:07:53.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.07:07:53.98$vck44/vblo=3,649.99 2006.285.07:07:53.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.07:07:53.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.07:07:53.98#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:53.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:07:53.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:07:53.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:07:53.98#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:07:53.98#ibcon#first serial, iclass 16, count 0 2006.285.07:07:53.98#ibcon#enter sib2, iclass 16, count 0 2006.285.07:07:53.98#ibcon#flushed, iclass 16, count 0 2006.285.07:07:53.98#ibcon#about to write, iclass 16, count 0 2006.285.07:07:53.98#ibcon#wrote, iclass 16, count 0 2006.285.07:07:53.98#ibcon#about to read 3, iclass 16, count 0 2006.285.07:07:54.00#ibcon#read 3, iclass 16, count 0 2006.285.07:07:54.00#ibcon#about to read 4, iclass 16, count 0 2006.285.07:07:54.00#ibcon#read 4, iclass 16, count 0 2006.285.07:07:54.00#ibcon#about to read 5, iclass 16, count 0 2006.285.07:07:54.00#ibcon#read 5, iclass 16, count 0 2006.285.07:07:54.00#ibcon#about to read 6, iclass 16, count 0 2006.285.07:07:54.00#ibcon#read 6, iclass 16, count 0 2006.285.07:07:54.00#ibcon#end of sib2, iclass 16, count 0 2006.285.07:07:54.00#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:07:54.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:07:54.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:07:54.00#ibcon#*before write, iclass 16, count 0 2006.285.07:07:54.00#ibcon#enter sib2, iclass 16, count 0 2006.285.07:07:54.00#ibcon#flushed, iclass 16, count 0 2006.285.07:07:54.00#ibcon#about to write, iclass 16, count 0 2006.285.07:07:54.00#ibcon#wrote, iclass 16, count 0 2006.285.07:07:54.00#ibcon#about to read 3, iclass 16, count 0 2006.285.07:07:54.04#ibcon#read 3, iclass 16, count 0 2006.285.07:07:54.04#ibcon#about to read 4, iclass 16, count 0 2006.285.07:07:54.04#ibcon#read 4, iclass 16, count 0 2006.285.07:07:54.04#ibcon#about to read 5, iclass 16, count 0 2006.285.07:07:54.04#ibcon#read 5, iclass 16, count 0 2006.285.07:07:54.04#ibcon#about to read 6, iclass 16, count 0 2006.285.07:07:54.04#ibcon#read 6, iclass 16, count 0 2006.285.07:07:54.04#ibcon#end of sib2, iclass 16, count 0 2006.285.07:07:54.04#ibcon#*after write, iclass 16, count 0 2006.285.07:07:54.04#ibcon#*before return 0, iclass 16, count 0 2006.285.07:07:54.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:07:54.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:07:54.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:07:54.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:07:54.04$vck44/vb=3,4 2006.285.07:07:54.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.07:07:54.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.07:07:54.04#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:54.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:07:54.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:07:54.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:07:54.10#ibcon#enter wrdev, iclass 18, count 2 2006.285.07:07:54.10#ibcon#first serial, iclass 18, count 2 2006.285.07:07:54.10#ibcon#enter sib2, iclass 18, count 2 2006.285.07:07:54.10#ibcon#flushed, iclass 18, count 2 2006.285.07:07:54.10#ibcon#about to write, iclass 18, count 2 2006.285.07:07:54.10#ibcon#wrote, iclass 18, count 2 2006.285.07:07:54.10#ibcon#about to read 3, iclass 18, count 2 2006.285.07:07:54.12#ibcon#read 3, iclass 18, count 2 2006.285.07:07:54.12#ibcon#about to read 4, iclass 18, count 2 2006.285.07:07:54.12#ibcon#read 4, iclass 18, count 2 2006.285.07:07:54.12#ibcon#about to read 5, iclass 18, count 2 2006.285.07:07:54.12#ibcon#read 5, iclass 18, count 2 2006.285.07:07:54.12#ibcon#about to read 6, iclass 18, count 2 2006.285.07:07:54.12#ibcon#read 6, iclass 18, count 2 2006.285.07:07:54.12#ibcon#end of sib2, iclass 18, count 2 2006.285.07:07:54.12#ibcon#*mode == 0, iclass 18, count 2 2006.285.07:07:54.12#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.07:07:54.12#ibcon#[27=AT03-04\r\n] 2006.285.07:07:54.12#ibcon#*before write, iclass 18, count 2 2006.285.07:07:54.12#ibcon#enter sib2, iclass 18, count 2 2006.285.07:07:54.12#ibcon#flushed, iclass 18, count 2 2006.285.07:07:54.12#ibcon#about to write, iclass 18, count 2 2006.285.07:07:54.12#ibcon#wrote, iclass 18, count 2 2006.285.07:07:54.12#ibcon#about to read 3, iclass 18, count 2 2006.285.07:07:54.15#ibcon#read 3, iclass 18, count 2 2006.285.07:07:54.15#ibcon#about to read 4, iclass 18, count 2 2006.285.07:07:54.15#ibcon#read 4, iclass 18, count 2 2006.285.07:07:54.15#ibcon#about to read 5, iclass 18, count 2 2006.285.07:07:54.15#ibcon#read 5, iclass 18, count 2 2006.285.07:07:54.15#ibcon#about to read 6, iclass 18, count 2 2006.285.07:07:54.15#ibcon#read 6, iclass 18, count 2 2006.285.07:07:54.15#ibcon#end of sib2, iclass 18, count 2 2006.285.07:07:54.15#ibcon#*after write, iclass 18, count 2 2006.285.07:07:54.15#ibcon#*before return 0, iclass 18, count 2 2006.285.07:07:54.15#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:07:54.15#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:07:54.15#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.07:07:54.15#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:54.15#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:07:54.27#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:07:54.27#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:07:54.27#ibcon#enter wrdev, iclass 18, count 0 2006.285.07:07:54.27#ibcon#first serial, iclass 18, count 0 2006.285.07:07:54.27#ibcon#enter sib2, iclass 18, count 0 2006.285.07:07:54.27#ibcon#flushed, iclass 18, count 0 2006.285.07:07:54.27#ibcon#about to write, iclass 18, count 0 2006.285.07:07:54.27#ibcon#wrote, iclass 18, count 0 2006.285.07:07:54.27#ibcon#about to read 3, iclass 18, count 0 2006.285.07:07:54.29#ibcon#read 3, iclass 18, count 0 2006.285.07:07:54.29#ibcon#about to read 4, iclass 18, count 0 2006.285.07:07:54.29#ibcon#read 4, iclass 18, count 0 2006.285.07:07:54.29#ibcon#about to read 5, iclass 18, count 0 2006.285.07:07:54.29#ibcon#read 5, iclass 18, count 0 2006.285.07:07:54.29#ibcon#about to read 6, iclass 18, count 0 2006.285.07:07:54.29#ibcon#read 6, iclass 18, count 0 2006.285.07:07:54.29#ibcon#end of sib2, iclass 18, count 0 2006.285.07:07:54.29#ibcon#*mode == 0, iclass 18, count 0 2006.285.07:07:54.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.07:07:54.29#ibcon#[27=USB\r\n] 2006.285.07:07:54.29#ibcon#*before write, iclass 18, count 0 2006.285.07:07:54.29#ibcon#enter sib2, iclass 18, count 0 2006.285.07:07:54.29#ibcon#flushed, iclass 18, count 0 2006.285.07:07:54.29#ibcon#about to write, iclass 18, count 0 2006.285.07:07:54.29#ibcon#wrote, iclass 18, count 0 2006.285.07:07:54.29#ibcon#about to read 3, iclass 18, count 0 2006.285.07:07:54.32#ibcon#read 3, iclass 18, count 0 2006.285.07:07:54.32#ibcon#about to read 4, iclass 18, count 0 2006.285.07:07:54.32#ibcon#read 4, iclass 18, count 0 2006.285.07:07:54.32#ibcon#about to read 5, iclass 18, count 0 2006.285.07:07:54.32#ibcon#read 5, iclass 18, count 0 2006.285.07:07:54.32#ibcon#about to read 6, iclass 18, count 0 2006.285.07:07:54.32#ibcon#read 6, iclass 18, count 0 2006.285.07:07:54.32#ibcon#end of sib2, iclass 18, count 0 2006.285.07:07:54.32#ibcon#*after write, iclass 18, count 0 2006.285.07:07:54.32#ibcon#*before return 0, iclass 18, count 0 2006.285.07:07:54.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:07:54.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:07:54.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.07:07:54.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.07:07:54.32$vck44/vblo=4,679.99 2006.285.07:07:54.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.07:07:54.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.07:07:54.32#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:54.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:07:54.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:07:54.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:07:54.32#ibcon#enter wrdev, iclass 20, count 0 2006.285.07:07:54.32#ibcon#first serial, iclass 20, count 0 2006.285.07:07:54.32#ibcon#enter sib2, iclass 20, count 0 2006.285.07:07:54.32#ibcon#flushed, iclass 20, count 0 2006.285.07:07:54.32#ibcon#about to write, iclass 20, count 0 2006.285.07:07:54.32#ibcon#wrote, iclass 20, count 0 2006.285.07:07:54.32#ibcon#about to read 3, iclass 20, count 0 2006.285.07:07:54.34#ibcon#read 3, iclass 20, count 0 2006.285.07:07:54.34#ibcon#about to read 4, iclass 20, count 0 2006.285.07:07:54.34#ibcon#read 4, iclass 20, count 0 2006.285.07:07:54.34#ibcon#about to read 5, iclass 20, count 0 2006.285.07:07:54.34#ibcon#read 5, iclass 20, count 0 2006.285.07:07:54.34#ibcon#about to read 6, iclass 20, count 0 2006.285.07:07:54.34#ibcon#read 6, iclass 20, count 0 2006.285.07:07:54.34#ibcon#end of sib2, iclass 20, count 0 2006.285.07:07:54.34#ibcon#*mode == 0, iclass 20, count 0 2006.285.07:07:54.34#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.07:07:54.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:07:54.34#ibcon#*before write, iclass 20, count 0 2006.285.07:07:54.34#ibcon#enter sib2, iclass 20, count 0 2006.285.07:07:54.34#ibcon#flushed, iclass 20, count 0 2006.285.07:07:54.34#ibcon#about to write, iclass 20, count 0 2006.285.07:07:54.34#ibcon#wrote, iclass 20, count 0 2006.285.07:07:54.34#ibcon#about to read 3, iclass 20, count 0 2006.285.07:07:54.38#ibcon#read 3, iclass 20, count 0 2006.285.07:07:54.38#ibcon#about to read 4, iclass 20, count 0 2006.285.07:07:54.38#ibcon#read 4, iclass 20, count 0 2006.285.07:07:54.38#ibcon#about to read 5, iclass 20, count 0 2006.285.07:07:54.38#ibcon#read 5, iclass 20, count 0 2006.285.07:07:54.38#ibcon#about to read 6, iclass 20, count 0 2006.285.07:07:54.38#ibcon#read 6, iclass 20, count 0 2006.285.07:07:54.38#ibcon#end of sib2, iclass 20, count 0 2006.285.07:07:54.38#ibcon#*after write, iclass 20, count 0 2006.285.07:07:54.38#ibcon#*before return 0, iclass 20, count 0 2006.285.07:07:54.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:07:54.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:07:54.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.07:07:54.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.07:07:54.38$vck44/vb=4,5 2006.285.07:07:54.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.07:07:54.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.07:07:54.38#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:54.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:07:54.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:07:54.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:07:54.44#ibcon#enter wrdev, iclass 22, count 2 2006.285.07:07:54.44#ibcon#first serial, iclass 22, count 2 2006.285.07:07:54.44#ibcon#enter sib2, iclass 22, count 2 2006.285.07:07:54.44#ibcon#flushed, iclass 22, count 2 2006.285.07:07:54.44#ibcon#about to write, iclass 22, count 2 2006.285.07:07:54.44#ibcon#wrote, iclass 22, count 2 2006.285.07:07:54.44#ibcon#about to read 3, iclass 22, count 2 2006.285.07:07:54.46#ibcon#read 3, iclass 22, count 2 2006.285.07:07:54.46#ibcon#about to read 4, iclass 22, count 2 2006.285.07:07:54.46#ibcon#read 4, iclass 22, count 2 2006.285.07:07:54.46#ibcon#about to read 5, iclass 22, count 2 2006.285.07:07:54.46#ibcon#read 5, iclass 22, count 2 2006.285.07:07:54.46#ibcon#about to read 6, iclass 22, count 2 2006.285.07:07:54.46#ibcon#read 6, iclass 22, count 2 2006.285.07:07:54.46#ibcon#end of sib2, iclass 22, count 2 2006.285.07:07:54.46#ibcon#*mode == 0, iclass 22, count 2 2006.285.07:07:54.46#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.07:07:54.46#ibcon#[27=AT04-05\r\n] 2006.285.07:07:54.46#ibcon#*before write, iclass 22, count 2 2006.285.07:07:54.46#ibcon#enter sib2, iclass 22, count 2 2006.285.07:07:54.46#ibcon#flushed, iclass 22, count 2 2006.285.07:07:54.46#ibcon#about to write, iclass 22, count 2 2006.285.07:07:54.46#ibcon#wrote, iclass 22, count 2 2006.285.07:07:54.46#ibcon#about to read 3, iclass 22, count 2 2006.285.07:07:54.49#ibcon#read 3, iclass 22, count 2 2006.285.07:07:54.49#ibcon#about to read 4, iclass 22, count 2 2006.285.07:07:54.49#ibcon#read 4, iclass 22, count 2 2006.285.07:07:54.49#ibcon#about to read 5, iclass 22, count 2 2006.285.07:07:54.49#ibcon#read 5, iclass 22, count 2 2006.285.07:07:54.49#ibcon#about to read 6, iclass 22, count 2 2006.285.07:07:54.49#ibcon#read 6, iclass 22, count 2 2006.285.07:07:54.49#ibcon#end of sib2, iclass 22, count 2 2006.285.07:07:54.49#ibcon#*after write, iclass 22, count 2 2006.285.07:07:54.49#ibcon#*before return 0, iclass 22, count 2 2006.285.07:07:54.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:07:54.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:07:54.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.07:07:54.49#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:54.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:07:54.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:07:54.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:07:54.61#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:07:54.61#ibcon#first serial, iclass 22, count 0 2006.285.07:07:54.61#ibcon#enter sib2, iclass 22, count 0 2006.285.07:07:54.61#ibcon#flushed, iclass 22, count 0 2006.285.07:07:54.61#ibcon#about to write, iclass 22, count 0 2006.285.07:07:54.61#ibcon#wrote, iclass 22, count 0 2006.285.07:07:54.61#ibcon#about to read 3, iclass 22, count 0 2006.285.07:07:54.63#ibcon#read 3, iclass 22, count 0 2006.285.07:07:54.63#ibcon#about to read 4, iclass 22, count 0 2006.285.07:07:54.63#ibcon#read 4, iclass 22, count 0 2006.285.07:07:54.63#ibcon#about to read 5, iclass 22, count 0 2006.285.07:07:54.63#ibcon#read 5, iclass 22, count 0 2006.285.07:07:54.63#ibcon#about to read 6, iclass 22, count 0 2006.285.07:07:54.63#ibcon#read 6, iclass 22, count 0 2006.285.07:07:54.63#ibcon#end of sib2, iclass 22, count 0 2006.285.07:07:54.63#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:07:54.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:07:54.63#ibcon#[27=USB\r\n] 2006.285.07:07:54.63#ibcon#*before write, iclass 22, count 0 2006.285.07:07:54.63#ibcon#enter sib2, iclass 22, count 0 2006.285.07:07:54.63#ibcon#flushed, iclass 22, count 0 2006.285.07:07:54.63#ibcon#about to write, iclass 22, count 0 2006.285.07:07:54.63#ibcon#wrote, iclass 22, count 0 2006.285.07:07:54.63#ibcon#about to read 3, iclass 22, count 0 2006.285.07:07:54.66#ibcon#read 3, iclass 22, count 0 2006.285.07:07:54.66#ibcon#about to read 4, iclass 22, count 0 2006.285.07:07:54.66#ibcon#read 4, iclass 22, count 0 2006.285.07:07:54.66#ibcon#about to read 5, iclass 22, count 0 2006.285.07:07:54.66#ibcon#read 5, iclass 22, count 0 2006.285.07:07:54.66#ibcon#about to read 6, iclass 22, count 0 2006.285.07:07:54.66#ibcon#read 6, iclass 22, count 0 2006.285.07:07:54.66#ibcon#end of sib2, iclass 22, count 0 2006.285.07:07:54.66#ibcon#*after write, iclass 22, count 0 2006.285.07:07:54.66#ibcon#*before return 0, iclass 22, count 0 2006.285.07:07:54.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:07:54.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:07:54.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:07:54.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:07:54.66$vck44/vblo=5,709.99 2006.285.07:07:54.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.07:07:54.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.07:07:54.66#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:54.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:07:54.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:07:54.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:07:54.66#ibcon#enter wrdev, iclass 24, count 0 2006.285.07:07:54.66#ibcon#first serial, iclass 24, count 0 2006.285.07:07:54.66#ibcon#enter sib2, iclass 24, count 0 2006.285.07:07:54.66#ibcon#flushed, iclass 24, count 0 2006.285.07:07:54.66#ibcon#about to write, iclass 24, count 0 2006.285.07:07:54.66#ibcon#wrote, iclass 24, count 0 2006.285.07:07:54.66#ibcon#about to read 3, iclass 24, count 0 2006.285.07:07:54.68#ibcon#read 3, iclass 24, count 0 2006.285.07:07:54.68#ibcon#about to read 4, iclass 24, count 0 2006.285.07:07:54.68#ibcon#read 4, iclass 24, count 0 2006.285.07:07:54.68#ibcon#about to read 5, iclass 24, count 0 2006.285.07:07:54.68#ibcon#read 5, iclass 24, count 0 2006.285.07:07:54.68#ibcon#about to read 6, iclass 24, count 0 2006.285.07:07:54.68#ibcon#read 6, iclass 24, count 0 2006.285.07:07:54.68#ibcon#end of sib2, iclass 24, count 0 2006.285.07:07:54.68#ibcon#*mode == 0, iclass 24, count 0 2006.285.07:07:54.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.07:07:54.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:07:54.68#ibcon#*before write, iclass 24, count 0 2006.285.07:07:54.68#ibcon#enter sib2, iclass 24, count 0 2006.285.07:07:54.68#ibcon#flushed, iclass 24, count 0 2006.285.07:07:54.68#ibcon#about to write, iclass 24, count 0 2006.285.07:07:54.68#ibcon#wrote, iclass 24, count 0 2006.285.07:07:54.68#ibcon#about to read 3, iclass 24, count 0 2006.285.07:07:54.72#ibcon#read 3, iclass 24, count 0 2006.285.07:07:54.72#ibcon#about to read 4, iclass 24, count 0 2006.285.07:07:54.72#ibcon#read 4, iclass 24, count 0 2006.285.07:07:54.72#ibcon#about to read 5, iclass 24, count 0 2006.285.07:07:54.72#ibcon#read 5, iclass 24, count 0 2006.285.07:07:54.72#ibcon#about to read 6, iclass 24, count 0 2006.285.07:07:54.72#ibcon#read 6, iclass 24, count 0 2006.285.07:07:54.72#ibcon#end of sib2, iclass 24, count 0 2006.285.07:07:54.72#ibcon#*after write, iclass 24, count 0 2006.285.07:07:54.72#ibcon#*before return 0, iclass 24, count 0 2006.285.07:07:54.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:07:54.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:07:54.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.07:07:54.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.07:07:54.72$vck44/vb=5,4 2006.285.07:07:54.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.07:07:54.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.07:07:54.72#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:54.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:07:54.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:07:54.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:07:54.78#ibcon#enter wrdev, iclass 26, count 2 2006.285.07:07:54.78#ibcon#first serial, iclass 26, count 2 2006.285.07:07:54.78#ibcon#enter sib2, iclass 26, count 2 2006.285.07:07:54.78#ibcon#flushed, iclass 26, count 2 2006.285.07:07:54.78#ibcon#about to write, iclass 26, count 2 2006.285.07:07:54.78#ibcon#wrote, iclass 26, count 2 2006.285.07:07:54.78#ibcon#about to read 3, iclass 26, count 2 2006.285.07:07:54.80#ibcon#read 3, iclass 26, count 2 2006.285.07:07:54.80#ibcon#about to read 4, iclass 26, count 2 2006.285.07:07:54.80#ibcon#read 4, iclass 26, count 2 2006.285.07:07:54.80#ibcon#about to read 5, iclass 26, count 2 2006.285.07:07:54.80#ibcon#read 5, iclass 26, count 2 2006.285.07:07:54.80#ibcon#about to read 6, iclass 26, count 2 2006.285.07:07:54.80#ibcon#read 6, iclass 26, count 2 2006.285.07:07:54.80#ibcon#end of sib2, iclass 26, count 2 2006.285.07:07:54.80#ibcon#*mode == 0, iclass 26, count 2 2006.285.07:07:54.80#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.07:07:54.80#ibcon#[27=AT05-04\r\n] 2006.285.07:07:54.80#ibcon#*before write, iclass 26, count 2 2006.285.07:07:54.80#ibcon#enter sib2, iclass 26, count 2 2006.285.07:07:54.80#ibcon#flushed, iclass 26, count 2 2006.285.07:07:54.80#ibcon#about to write, iclass 26, count 2 2006.285.07:07:54.80#ibcon#wrote, iclass 26, count 2 2006.285.07:07:54.80#ibcon#about to read 3, iclass 26, count 2 2006.285.07:07:54.83#ibcon#read 3, iclass 26, count 2 2006.285.07:07:54.83#ibcon#about to read 4, iclass 26, count 2 2006.285.07:07:54.83#ibcon#read 4, iclass 26, count 2 2006.285.07:07:54.83#ibcon#about to read 5, iclass 26, count 2 2006.285.07:07:54.83#ibcon#read 5, iclass 26, count 2 2006.285.07:07:54.83#ibcon#about to read 6, iclass 26, count 2 2006.285.07:07:54.83#ibcon#read 6, iclass 26, count 2 2006.285.07:07:54.83#ibcon#end of sib2, iclass 26, count 2 2006.285.07:07:54.83#ibcon#*after write, iclass 26, count 2 2006.285.07:07:54.83#ibcon#*before return 0, iclass 26, count 2 2006.285.07:07:54.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:07:54.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:07:54.83#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.07:07:54.83#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:54.83#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:07:54.95#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:07:54.95#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:07:54.95#ibcon#enter wrdev, iclass 26, count 0 2006.285.07:07:54.95#ibcon#first serial, iclass 26, count 0 2006.285.07:07:54.95#ibcon#enter sib2, iclass 26, count 0 2006.285.07:07:54.95#ibcon#flushed, iclass 26, count 0 2006.285.07:07:54.95#ibcon#about to write, iclass 26, count 0 2006.285.07:07:54.95#ibcon#wrote, iclass 26, count 0 2006.285.07:07:54.95#ibcon#about to read 3, iclass 26, count 0 2006.285.07:07:54.97#ibcon#read 3, iclass 26, count 0 2006.285.07:07:54.97#ibcon#about to read 4, iclass 26, count 0 2006.285.07:07:54.97#ibcon#read 4, iclass 26, count 0 2006.285.07:07:54.97#ibcon#about to read 5, iclass 26, count 0 2006.285.07:07:54.97#ibcon#read 5, iclass 26, count 0 2006.285.07:07:54.97#ibcon#about to read 6, iclass 26, count 0 2006.285.07:07:54.97#ibcon#read 6, iclass 26, count 0 2006.285.07:07:54.97#ibcon#end of sib2, iclass 26, count 0 2006.285.07:07:54.97#ibcon#*mode == 0, iclass 26, count 0 2006.285.07:07:54.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.07:07:54.97#ibcon#[27=USB\r\n] 2006.285.07:07:54.97#ibcon#*before write, iclass 26, count 0 2006.285.07:07:54.97#ibcon#enter sib2, iclass 26, count 0 2006.285.07:07:54.97#ibcon#flushed, iclass 26, count 0 2006.285.07:07:54.97#ibcon#about to write, iclass 26, count 0 2006.285.07:07:54.97#ibcon#wrote, iclass 26, count 0 2006.285.07:07:54.97#ibcon#about to read 3, iclass 26, count 0 2006.285.07:07:55.00#ibcon#read 3, iclass 26, count 0 2006.285.07:07:55.00#ibcon#about to read 4, iclass 26, count 0 2006.285.07:07:55.00#ibcon#read 4, iclass 26, count 0 2006.285.07:07:55.00#ibcon#about to read 5, iclass 26, count 0 2006.285.07:07:55.00#ibcon#read 5, iclass 26, count 0 2006.285.07:07:55.00#ibcon#about to read 6, iclass 26, count 0 2006.285.07:07:55.00#ibcon#read 6, iclass 26, count 0 2006.285.07:07:55.00#ibcon#end of sib2, iclass 26, count 0 2006.285.07:07:55.00#ibcon#*after write, iclass 26, count 0 2006.285.07:07:55.00#ibcon#*before return 0, iclass 26, count 0 2006.285.07:07:55.00#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:07:55.00#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:07:55.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.07:07:55.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.07:07:55.00$vck44/vblo=6,719.99 2006.285.07:07:55.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.07:07:55.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.07:07:55.00#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:55.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:07:55.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:07:55.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:07:55.00#ibcon#enter wrdev, iclass 28, count 0 2006.285.07:07:55.00#ibcon#first serial, iclass 28, count 0 2006.285.07:07:55.00#ibcon#enter sib2, iclass 28, count 0 2006.285.07:07:55.00#ibcon#flushed, iclass 28, count 0 2006.285.07:07:55.00#ibcon#about to write, iclass 28, count 0 2006.285.07:07:55.00#ibcon#wrote, iclass 28, count 0 2006.285.07:07:55.00#ibcon#about to read 3, iclass 28, count 0 2006.285.07:07:55.02#ibcon#read 3, iclass 28, count 0 2006.285.07:07:55.02#ibcon#about to read 4, iclass 28, count 0 2006.285.07:07:55.02#ibcon#read 4, iclass 28, count 0 2006.285.07:07:55.02#ibcon#about to read 5, iclass 28, count 0 2006.285.07:07:55.02#ibcon#read 5, iclass 28, count 0 2006.285.07:07:55.02#ibcon#about to read 6, iclass 28, count 0 2006.285.07:07:55.02#ibcon#read 6, iclass 28, count 0 2006.285.07:07:55.02#ibcon#end of sib2, iclass 28, count 0 2006.285.07:07:55.02#ibcon#*mode == 0, iclass 28, count 0 2006.285.07:07:55.02#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.07:07:55.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:07:55.02#ibcon#*before write, iclass 28, count 0 2006.285.07:07:55.02#ibcon#enter sib2, iclass 28, count 0 2006.285.07:07:55.02#ibcon#flushed, iclass 28, count 0 2006.285.07:07:55.02#ibcon#about to write, iclass 28, count 0 2006.285.07:07:55.02#ibcon#wrote, iclass 28, count 0 2006.285.07:07:55.02#ibcon#about to read 3, iclass 28, count 0 2006.285.07:07:55.06#ibcon#read 3, iclass 28, count 0 2006.285.07:07:55.06#ibcon#about to read 4, iclass 28, count 0 2006.285.07:07:55.06#ibcon#read 4, iclass 28, count 0 2006.285.07:07:55.06#ibcon#about to read 5, iclass 28, count 0 2006.285.07:07:55.06#ibcon#read 5, iclass 28, count 0 2006.285.07:07:55.06#ibcon#about to read 6, iclass 28, count 0 2006.285.07:07:55.06#ibcon#read 6, iclass 28, count 0 2006.285.07:07:55.06#ibcon#end of sib2, iclass 28, count 0 2006.285.07:07:55.06#ibcon#*after write, iclass 28, count 0 2006.285.07:07:55.06#ibcon#*before return 0, iclass 28, count 0 2006.285.07:07:55.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:07:55.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:07:55.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.07:07:55.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.07:07:55.06$vck44/vb=6,3 2006.285.07:07:55.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.07:07:55.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.07:07:55.06#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:55.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:07:55.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:07:55.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:07:55.12#ibcon#enter wrdev, iclass 30, count 2 2006.285.07:07:55.12#ibcon#first serial, iclass 30, count 2 2006.285.07:07:55.12#ibcon#enter sib2, iclass 30, count 2 2006.285.07:07:55.12#ibcon#flushed, iclass 30, count 2 2006.285.07:07:55.12#ibcon#about to write, iclass 30, count 2 2006.285.07:07:55.12#ibcon#wrote, iclass 30, count 2 2006.285.07:07:55.12#ibcon#about to read 3, iclass 30, count 2 2006.285.07:07:55.14#ibcon#read 3, iclass 30, count 2 2006.285.07:07:55.14#ibcon#about to read 4, iclass 30, count 2 2006.285.07:07:55.14#ibcon#read 4, iclass 30, count 2 2006.285.07:07:55.14#ibcon#about to read 5, iclass 30, count 2 2006.285.07:07:55.14#ibcon#read 5, iclass 30, count 2 2006.285.07:07:55.14#ibcon#about to read 6, iclass 30, count 2 2006.285.07:07:55.14#ibcon#read 6, iclass 30, count 2 2006.285.07:07:55.14#ibcon#end of sib2, iclass 30, count 2 2006.285.07:07:55.14#ibcon#*mode == 0, iclass 30, count 2 2006.285.07:07:55.14#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.07:07:55.14#ibcon#[27=AT06-03\r\n] 2006.285.07:07:55.14#ibcon#*before write, iclass 30, count 2 2006.285.07:07:55.14#ibcon#enter sib2, iclass 30, count 2 2006.285.07:07:55.14#ibcon#flushed, iclass 30, count 2 2006.285.07:07:55.14#ibcon#about to write, iclass 30, count 2 2006.285.07:07:55.14#ibcon#wrote, iclass 30, count 2 2006.285.07:07:55.14#ibcon#about to read 3, iclass 30, count 2 2006.285.07:07:55.17#ibcon#read 3, iclass 30, count 2 2006.285.07:07:55.17#ibcon#about to read 4, iclass 30, count 2 2006.285.07:07:55.17#ibcon#read 4, iclass 30, count 2 2006.285.07:07:55.17#ibcon#about to read 5, iclass 30, count 2 2006.285.07:07:55.17#ibcon#read 5, iclass 30, count 2 2006.285.07:07:55.17#ibcon#about to read 6, iclass 30, count 2 2006.285.07:07:55.17#ibcon#read 6, iclass 30, count 2 2006.285.07:07:55.17#ibcon#end of sib2, iclass 30, count 2 2006.285.07:07:55.17#ibcon#*after write, iclass 30, count 2 2006.285.07:07:55.17#ibcon#*before return 0, iclass 30, count 2 2006.285.07:07:55.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:07:55.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:07:55.17#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.07:07:55.17#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:55.17#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:07:55.29#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:07:55.29#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:07:55.29#ibcon#enter wrdev, iclass 30, count 0 2006.285.07:07:55.29#ibcon#first serial, iclass 30, count 0 2006.285.07:07:55.29#ibcon#enter sib2, iclass 30, count 0 2006.285.07:07:55.29#ibcon#flushed, iclass 30, count 0 2006.285.07:07:55.29#ibcon#about to write, iclass 30, count 0 2006.285.07:07:55.29#ibcon#wrote, iclass 30, count 0 2006.285.07:07:55.29#ibcon#about to read 3, iclass 30, count 0 2006.285.07:07:55.31#ibcon#read 3, iclass 30, count 0 2006.285.07:07:55.31#ibcon#about to read 4, iclass 30, count 0 2006.285.07:07:55.31#ibcon#read 4, iclass 30, count 0 2006.285.07:07:55.31#ibcon#about to read 5, iclass 30, count 0 2006.285.07:07:55.31#ibcon#read 5, iclass 30, count 0 2006.285.07:07:55.31#ibcon#about to read 6, iclass 30, count 0 2006.285.07:07:55.31#ibcon#read 6, iclass 30, count 0 2006.285.07:07:55.31#ibcon#end of sib2, iclass 30, count 0 2006.285.07:07:55.31#ibcon#*mode == 0, iclass 30, count 0 2006.285.07:07:55.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.07:07:55.31#ibcon#[27=USB\r\n] 2006.285.07:07:55.31#ibcon#*before write, iclass 30, count 0 2006.285.07:07:55.31#ibcon#enter sib2, iclass 30, count 0 2006.285.07:07:55.31#ibcon#flushed, iclass 30, count 0 2006.285.07:07:55.31#ibcon#about to write, iclass 30, count 0 2006.285.07:07:55.31#ibcon#wrote, iclass 30, count 0 2006.285.07:07:55.31#ibcon#about to read 3, iclass 30, count 0 2006.285.07:07:55.34#ibcon#read 3, iclass 30, count 0 2006.285.07:07:55.34#ibcon#about to read 4, iclass 30, count 0 2006.285.07:07:55.34#ibcon#read 4, iclass 30, count 0 2006.285.07:07:55.34#ibcon#about to read 5, iclass 30, count 0 2006.285.07:07:55.34#ibcon#read 5, iclass 30, count 0 2006.285.07:07:55.34#ibcon#about to read 6, iclass 30, count 0 2006.285.07:07:55.34#ibcon#read 6, iclass 30, count 0 2006.285.07:07:55.34#ibcon#end of sib2, iclass 30, count 0 2006.285.07:07:55.34#ibcon#*after write, iclass 30, count 0 2006.285.07:07:55.34#ibcon#*before return 0, iclass 30, count 0 2006.285.07:07:55.34#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:07:55.34#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:07:55.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.07:07:55.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.07:07:55.34$vck44/vblo=7,734.99 2006.285.07:07:55.34#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.07:07:55.34#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.07:07:55.34#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:55.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:07:55.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:07:55.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:07:55.34#ibcon#enter wrdev, iclass 32, count 0 2006.285.07:07:55.34#ibcon#first serial, iclass 32, count 0 2006.285.07:07:55.34#ibcon#enter sib2, iclass 32, count 0 2006.285.07:07:55.34#ibcon#flushed, iclass 32, count 0 2006.285.07:07:55.34#ibcon#about to write, iclass 32, count 0 2006.285.07:07:55.34#ibcon#wrote, iclass 32, count 0 2006.285.07:07:55.34#ibcon#about to read 3, iclass 32, count 0 2006.285.07:07:55.36#ibcon#read 3, iclass 32, count 0 2006.285.07:07:55.36#ibcon#about to read 4, iclass 32, count 0 2006.285.07:07:55.36#ibcon#read 4, iclass 32, count 0 2006.285.07:07:55.36#ibcon#about to read 5, iclass 32, count 0 2006.285.07:07:55.36#ibcon#read 5, iclass 32, count 0 2006.285.07:07:55.36#ibcon#about to read 6, iclass 32, count 0 2006.285.07:07:55.36#ibcon#read 6, iclass 32, count 0 2006.285.07:07:55.36#ibcon#end of sib2, iclass 32, count 0 2006.285.07:07:55.36#ibcon#*mode == 0, iclass 32, count 0 2006.285.07:07:55.36#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.07:07:55.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:07:55.36#ibcon#*before write, iclass 32, count 0 2006.285.07:07:55.36#ibcon#enter sib2, iclass 32, count 0 2006.285.07:07:55.36#ibcon#flushed, iclass 32, count 0 2006.285.07:07:55.36#ibcon#about to write, iclass 32, count 0 2006.285.07:07:55.36#ibcon#wrote, iclass 32, count 0 2006.285.07:07:55.36#ibcon#about to read 3, iclass 32, count 0 2006.285.07:07:55.40#ibcon#read 3, iclass 32, count 0 2006.285.07:07:55.40#ibcon#about to read 4, iclass 32, count 0 2006.285.07:07:55.40#ibcon#read 4, iclass 32, count 0 2006.285.07:07:55.40#ibcon#about to read 5, iclass 32, count 0 2006.285.07:07:55.40#ibcon#read 5, iclass 32, count 0 2006.285.07:07:55.40#ibcon#about to read 6, iclass 32, count 0 2006.285.07:07:55.40#ibcon#read 6, iclass 32, count 0 2006.285.07:07:55.40#ibcon#end of sib2, iclass 32, count 0 2006.285.07:07:55.40#ibcon#*after write, iclass 32, count 0 2006.285.07:07:55.40#ibcon#*before return 0, iclass 32, count 0 2006.285.07:07:55.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:07:55.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:07:55.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.07:07:55.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.07:07:55.40$vck44/vb=7,4 2006.285.07:07:55.40#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.07:07:55.40#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.07:07:55.40#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:55.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:07:55.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:07:55.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:07:55.46#ibcon#enter wrdev, iclass 34, count 2 2006.285.07:07:55.46#ibcon#first serial, iclass 34, count 2 2006.285.07:07:55.46#ibcon#enter sib2, iclass 34, count 2 2006.285.07:07:55.46#ibcon#flushed, iclass 34, count 2 2006.285.07:07:55.46#ibcon#about to write, iclass 34, count 2 2006.285.07:07:55.46#ibcon#wrote, iclass 34, count 2 2006.285.07:07:55.46#ibcon#about to read 3, iclass 34, count 2 2006.285.07:07:55.48#ibcon#read 3, iclass 34, count 2 2006.285.07:07:55.48#ibcon#about to read 4, iclass 34, count 2 2006.285.07:07:55.48#ibcon#read 4, iclass 34, count 2 2006.285.07:07:55.48#ibcon#about to read 5, iclass 34, count 2 2006.285.07:07:55.48#ibcon#read 5, iclass 34, count 2 2006.285.07:07:55.48#ibcon#about to read 6, iclass 34, count 2 2006.285.07:07:55.48#ibcon#read 6, iclass 34, count 2 2006.285.07:07:55.48#ibcon#end of sib2, iclass 34, count 2 2006.285.07:07:55.48#ibcon#*mode == 0, iclass 34, count 2 2006.285.07:07:55.48#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.07:07:55.48#ibcon#[27=AT07-04\r\n] 2006.285.07:07:55.48#ibcon#*before write, iclass 34, count 2 2006.285.07:07:55.48#ibcon#enter sib2, iclass 34, count 2 2006.285.07:07:55.48#ibcon#flushed, iclass 34, count 2 2006.285.07:07:55.48#ibcon#about to write, iclass 34, count 2 2006.285.07:07:55.48#ibcon#wrote, iclass 34, count 2 2006.285.07:07:55.48#ibcon#about to read 3, iclass 34, count 2 2006.285.07:07:55.51#ibcon#read 3, iclass 34, count 2 2006.285.07:07:55.51#ibcon#about to read 4, iclass 34, count 2 2006.285.07:07:55.51#ibcon#read 4, iclass 34, count 2 2006.285.07:07:55.51#ibcon#about to read 5, iclass 34, count 2 2006.285.07:07:55.51#ibcon#read 5, iclass 34, count 2 2006.285.07:07:55.51#ibcon#about to read 6, iclass 34, count 2 2006.285.07:07:55.51#ibcon#read 6, iclass 34, count 2 2006.285.07:07:55.51#ibcon#end of sib2, iclass 34, count 2 2006.285.07:07:55.51#ibcon#*after write, iclass 34, count 2 2006.285.07:07:55.51#ibcon#*before return 0, iclass 34, count 2 2006.285.07:07:55.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:07:55.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:07:55.51#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.07:07:55.51#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:55.51#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:07:55.63#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:07:55.63#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:07:55.63#ibcon#enter wrdev, iclass 34, count 0 2006.285.07:07:55.63#ibcon#first serial, iclass 34, count 0 2006.285.07:07:55.63#ibcon#enter sib2, iclass 34, count 0 2006.285.07:07:55.63#ibcon#flushed, iclass 34, count 0 2006.285.07:07:55.63#ibcon#about to write, iclass 34, count 0 2006.285.07:07:55.63#ibcon#wrote, iclass 34, count 0 2006.285.07:07:55.63#ibcon#about to read 3, iclass 34, count 0 2006.285.07:07:55.65#ibcon#read 3, iclass 34, count 0 2006.285.07:07:55.65#ibcon#about to read 4, iclass 34, count 0 2006.285.07:07:55.65#ibcon#read 4, iclass 34, count 0 2006.285.07:07:55.65#ibcon#about to read 5, iclass 34, count 0 2006.285.07:07:55.65#ibcon#read 5, iclass 34, count 0 2006.285.07:07:55.65#ibcon#about to read 6, iclass 34, count 0 2006.285.07:07:55.65#ibcon#read 6, iclass 34, count 0 2006.285.07:07:55.65#ibcon#end of sib2, iclass 34, count 0 2006.285.07:07:55.65#ibcon#*mode == 0, iclass 34, count 0 2006.285.07:07:55.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.07:07:55.65#ibcon#[27=USB\r\n] 2006.285.07:07:55.65#ibcon#*before write, iclass 34, count 0 2006.285.07:07:55.65#ibcon#enter sib2, iclass 34, count 0 2006.285.07:07:55.65#ibcon#flushed, iclass 34, count 0 2006.285.07:07:55.65#ibcon#about to write, iclass 34, count 0 2006.285.07:07:55.65#ibcon#wrote, iclass 34, count 0 2006.285.07:07:55.65#ibcon#about to read 3, iclass 34, count 0 2006.285.07:07:55.68#ibcon#read 3, iclass 34, count 0 2006.285.07:07:55.68#ibcon#about to read 4, iclass 34, count 0 2006.285.07:07:55.68#ibcon#read 4, iclass 34, count 0 2006.285.07:07:55.68#ibcon#about to read 5, iclass 34, count 0 2006.285.07:07:55.68#ibcon#read 5, iclass 34, count 0 2006.285.07:07:55.68#ibcon#about to read 6, iclass 34, count 0 2006.285.07:07:55.68#ibcon#read 6, iclass 34, count 0 2006.285.07:07:55.68#ibcon#end of sib2, iclass 34, count 0 2006.285.07:07:55.68#ibcon#*after write, iclass 34, count 0 2006.285.07:07:55.68#ibcon#*before return 0, iclass 34, count 0 2006.285.07:07:55.68#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:07:55.68#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:07:55.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.07:07:55.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.07:07:55.68$vck44/vblo=8,744.99 2006.285.07:07:55.68#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.07:07:55.68#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.07:07:55.68#ibcon#ireg 17 cls_cnt 0 2006.285.07:07:55.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:07:55.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:07:55.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:07:55.68#ibcon#enter wrdev, iclass 36, count 0 2006.285.07:07:55.68#ibcon#first serial, iclass 36, count 0 2006.285.07:07:55.68#ibcon#enter sib2, iclass 36, count 0 2006.285.07:07:55.68#ibcon#flushed, iclass 36, count 0 2006.285.07:07:55.68#ibcon#about to write, iclass 36, count 0 2006.285.07:07:55.68#ibcon#wrote, iclass 36, count 0 2006.285.07:07:55.68#ibcon#about to read 3, iclass 36, count 0 2006.285.07:07:55.70#ibcon#read 3, iclass 36, count 0 2006.285.07:07:55.70#ibcon#about to read 4, iclass 36, count 0 2006.285.07:07:55.70#ibcon#read 4, iclass 36, count 0 2006.285.07:07:55.70#ibcon#about to read 5, iclass 36, count 0 2006.285.07:07:55.70#ibcon#read 5, iclass 36, count 0 2006.285.07:07:55.70#ibcon#about to read 6, iclass 36, count 0 2006.285.07:07:55.70#ibcon#read 6, iclass 36, count 0 2006.285.07:07:55.70#ibcon#end of sib2, iclass 36, count 0 2006.285.07:07:55.70#ibcon#*mode == 0, iclass 36, count 0 2006.285.07:07:55.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.07:07:55.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:07:55.70#ibcon#*before write, iclass 36, count 0 2006.285.07:07:55.70#ibcon#enter sib2, iclass 36, count 0 2006.285.07:07:55.70#ibcon#flushed, iclass 36, count 0 2006.285.07:07:55.70#ibcon#about to write, iclass 36, count 0 2006.285.07:07:55.70#ibcon#wrote, iclass 36, count 0 2006.285.07:07:55.70#ibcon#about to read 3, iclass 36, count 0 2006.285.07:07:55.74#ibcon#read 3, iclass 36, count 0 2006.285.07:07:55.74#ibcon#about to read 4, iclass 36, count 0 2006.285.07:07:55.74#ibcon#read 4, iclass 36, count 0 2006.285.07:07:55.74#ibcon#about to read 5, iclass 36, count 0 2006.285.07:07:55.74#ibcon#read 5, iclass 36, count 0 2006.285.07:07:55.74#ibcon#about to read 6, iclass 36, count 0 2006.285.07:07:55.74#ibcon#read 6, iclass 36, count 0 2006.285.07:07:55.74#ibcon#end of sib2, iclass 36, count 0 2006.285.07:07:55.74#ibcon#*after write, iclass 36, count 0 2006.285.07:07:55.74#ibcon#*before return 0, iclass 36, count 0 2006.285.07:07:55.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:07:55.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:07:55.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.07:07:55.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.07:07:55.74$vck44/vb=8,4 2006.285.07:07:55.74#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.07:07:55.74#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.07:07:55.74#ibcon#ireg 11 cls_cnt 2 2006.285.07:07:55.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:07:55.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:07:55.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:07:55.80#ibcon#enter wrdev, iclass 38, count 2 2006.285.07:07:55.80#ibcon#first serial, iclass 38, count 2 2006.285.07:07:55.80#ibcon#enter sib2, iclass 38, count 2 2006.285.07:07:55.80#ibcon#flushed, iclass 38, count 2 2006.285.07:07:55.80#ibcon#about to write, iclass 38, count 2 2006.285.07:07:55.80#ibcon#wrote, iclass 38, count 2 2006.285.07:07:55.80#ibcon#about to read 3, iclass 38, count 2 2006.285.07:07:55.82#ibcon#read 3, iclass 38, count 2 2006.285.07:07:55.82#ibcon#about to read 4, iclass 38, count 2 2006.285.07:07:55.82#ibcon#read 4, iclass 38, count 2 2006.285.07:07:55.82#ibcon#about to read 5, iclass 38, count 2 2006.285.07:07:55.82#ibcon#read 5, iclass 38, count 2 2006.285.07:07:55.82#ibcon#about to read 6, iclass 38, count 2 2006.285.07:07:55.82#ibcon#read 6, iclass 38, count 2 2006.285.07:07:55.82#ibcon#end of sib2, iclass 38, count 2 2006.285.07:07:55.82#ibcon#*mode == 0, iclass 38, count 2 2006.285.07:07:55.82#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.07:07:55.82#ibcon#[27=AT08-04\r\n] 2006.285.07:07:55.82#ibcon#*before write, iclass 38, count 2 2006.285.07:07:55.82#ibcon#enter sib2, iclass 38, count 2 2006.285.07:07:55.82#ibcon#flushed, iclass 38, count 2 2006.285.07:07:55.82#ibcon#about to write, iclass 38, count 2 2006.285.07:07:55.82#ibcon#wrote, iclass 38, count 2 2006.285.07:07:55.82#ibcon#about to read 3, iclass 38, count 2 2006.285.07:07:55.85#ibcon#read 3, iclass 38, count 2 2006.285.07:07:55.85#ibcon#about to read 4, iclass 38, count 2 2006.285.07:07:55.85#ibcon#read 4, iclass 38, count 2 2006.285.07:07:55.85#ibcon#about to read 5, iclass 38, count 2 2006.285.07:07:55.85#ibcon#read 5, iclass 38, count 2 2006.285.07:07:55.85#ibcon#about to read 6, iclass 38, count 2 2006.285.07:07:55.85#ibcon#read 6, iclass 38, count 2 2006.285.07:07:55.85#ibcon#end of sib2, iclass 38, count 2 2006.285.07:07:55.85#ibcon#*after write, iclass 38, count 2 2006.285.07:07:55.85#ibcon#*before return 0, iclass 38, count 2 2006.285.07:07:55.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:07:55.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:07:55.85#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.07:07:55.85#ibcon#ireg 7 cls_cnt 0 2006.285.07:07:55.85#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:07:55.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:07:55.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:07:55.97#ibcon#enter wrdev, iclass 38, count 0 2006.285.07:07:55.97#ibcon#first serial, iclass 38, count 0 2006.285.07:07:55.97#ibcon#enter sib2, iclass 38, count 0 2006.285.07:07:55.97#ibcon#flushed, iclass 38, count 0 2006.285.07:07:55.97#ibcon#about to write, iclass 38, count 0 2006.285.07:07:55.97#ibcon#wrote, iclass 38, count 0 2006.285.07:07:55.97#ibcon#about to read 3, iclass 38, count 0 2006.285.07:07:55.99#ibcon#read 3, iclass 38, count 0 2006.285.07:07:55.99#ibcon#about to read 4, iclass 38, count 0 2006.285.07:07:55.99#ibcon#read 4, iclass 38, count 0 2006.285.07:07:55.99#ibcon#about to read 5, iclass 38, count 0 2006.285.07:07:55.99#ibcon#read 5, iclass 38, count 0 2006.285.07:07:55.99#ibcon#about to read 6, iclass 38, count 0 2006.285.07:07:55.99#ibcon#read 6, iclass 38, count 0 2006.285.07:07:55.99#ibcon#end of sib2, iclass 38, count 0 2006.285.07:07:55.99#ibcon#*mode == 0, iclass 38, count 0 2006.285.07:07:55.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.07:07:55.99#ibcon#[27=USB\r\n] 2006.285.07:07:55.99#ibcon#*before write, iclass 38, count 0 2006.285.07:07:55.99#ibcon#enter sib2, iclass 38, count 0 2006.285.07:07:55.99#ibcon#flushed, iclass 38, count 0 2006.285.07:07:55.99#ibcon#about to write, iclass 38, count 0 2006.285.07:07:55.99#ibcon#wrote, iclass 38, count 0 2006.285.07:07:55.99#ibcon#about to read 3, iclass 38, count 0 2006.285.07:07:56.02#ibcon#read 3, iclass 38, count 0 2006.285.07:07:56.02#ibcon#about to read 4, iclass 38, count 0 2006.285.07:07:56.02#ibcon#read 4, iclass 38, count 0 2006.285.07:07:56.02#ibcon#about to read 5, iclass 38, count 0 2006.285.07:07:56.02#ibcon#read 5, iclass 38, count 0 2006.285.07:07:56.02#ibcon#about to read 6, iclass 38, count 0 2006.285.07:07:56.02#ibcon#read 6, iclass 38, count 0 2006.285.07:07:56.02#ibcon#end of sib2, iclass 38, count 0 2006.285.07:07:56.02#ibcon#*after write, iclass 38, count 0 2006.285.07:07:56.02#ibcon#*before return 0, iclass 38, count 0 2006.285.07:07:56.02#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:07:56.02#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:07:56.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.07:07:56.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.07:07:56.02$vck44/vabw=wide 2006.285.07:07:56.02#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.07:07:56.02#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.07:07:56.02#ibcon#ireg 8 cls_cnt 0 2006.285.07:07:56.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:07:56.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:07:56.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:07:56.02#ibcon#enter wrdev, iclass 40, count 0 2006.285.07:07:56.02#ibcon#first serial, iclass 40, count 0 2006.285.07:07:56.02#ibcon#enter sib2, iclass 40, count 0 2006.285.07:07:56.02#ibcon#flushed, iclass 40, count 0 2006.285.07:07:56.02#ibcon#about to write, iclass 40, count 0 2006.285.07:07:56.02#ibcon#wrote, iclass 40, count 0 2006.285.07:07:56.02#ibcon#about to read 3, iclass 40, count 0 2006.285.07:07:56.04#ibcon#read 3, iclass 40, count 0 2006.285.07:07:56.04#ibcon#about to read 4, iclass 40, count 0 2006.285.07:07:56.04#ibcon#read 4, iclass 40, count 0 2006.285.07:07:56.04#ibcon#about to read 5, iclass 40, count 0 2006.285.07:07:56.04#ibcon#read 5, iclass 40, count 0 2006.285.07:07:56.04#ibcon#about to read 6, iclass 40, count 0 2006.285.07:07:56.04#ibcon#read 6, iclass 40, count 0 2006.285.07:07:56.04#ibcon#end of sib2, iclass 40, count 0 2006.285.07:07:56.04#ibcon#*mode == 0, iclass 40, count 0 2006.285.07:07:56.04#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.07:07:56.04#ibcon#[25=BW32\r\n] 2006.285.07:07:56.04#ibcon#*before write, iclass 40, count 0 2006.285.07:07:56.04#ibcon#enter sib2, iclass 40, count 0 2006.285.07:07:56.04#ibcon#flushed, iclass 40, count 0 2006.285.07:07:56.04#ibcon#about to write, iclass 40, count 0 2006.285.07:07:56.04#ibcon#wrote, iclass 40, count 0 2006.285.07:07:56.04#ibcon#about to read 3, iclass 40, count 0 2006.285.07:07:56.07#ibcon#read 3, iclass 40, count 0 2006.285.07:07:56.07#ibcon#about to read 4, iclass 40, count 0 2006.285.07:07:56.07#ibcon#read 4, iclass 40, count 0 2006.285.07:07:56.07#ibcon#about to read 5, iclass 40, count 0 2006.285.07:07:56.07#ibcon#read 5, iclass 40, count 0 2006.285.07:07:56.07#ibcon#about to read 6, iclass 40, count 0 2006.285.07:07:56.07#ibcon#read 6, iclass 40, count 0 2006.285.07:07:56.07#ibcon#end of sib2, iclass 40, count 0 2006.285.07:07:56.07#ibcon#*after write, iclass 40, count 0 2006.285.07:07:56.07#ibcon#*before return 0, iclass 40, count 0 2006.285.07:07:56.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:07:56.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:07:56.07#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.07:07:56.07#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.07:07:56.07$vck44/vbbw=wide 2006.285.07:07:56.07#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.07:07:56.07#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.07:07:56.07#ibcon#ireg 8 cls_cnt 0 2006.285.07:07:56.07#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:07:56.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:07:56.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:07:56.14#ibcon#enter wrdev, iclass 4, count 0 2006.285.07:07:56.14#ibcon#first serial, iclass 4, count 0 2006.285.07:07:56.14#ibcon#enter sib2, iclass 4, count 0 2006.285.07:07:56.14#ibcon#flushed, iclass 4, count 0 2006.285.07:07:56.14#ibcon#about to write, iclass 4, count 0 2006.285.07:07:56.14#ibcon#wrote, iclass 4, count 0 2006.285.07:07:56.14#ibcon#about to read 3, iclass 4, count 0 2006.285.07:07:56.16#ibcon#read 3, iclass 4, count 0 2006.285.07:07:56.16#ibcon#about to read 4, iclass 4, count 0 2006.285.07:07:56.16#ibcon#read 4, iclass 4, count 0 2006.285.07:07:56.16#ibcon#about to read 5, iclass 4, count 0 2006.285.07:07:56.16#ibcon#read 5, iclass 4, count 0 2006.285.07:07:56.16#ibcon#about to read 6, iclass 4, count 0 2006.285.07:07:56.16#ibcon#read 6, iclass 4, count 0 2006.285.07:07:56.16#ibcon#end of sib2, iclass 4, count 0 2006.285.07:07:56.16#ibcon#*mode == 0, iclass 4, count 0 2006.285.07:07:56.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.07:07:56.16#ibcon#[27=BW32\r\n] 2006.285.07:07:56.16#ibcon#*before write, iclass 4, count 0 2006.285.07:07:56.16#ibcon#enter sib2, iclass 4, count 0 2006.285.07:07:56.16#ibcon#flushed, iclass 4, count 0 2006.285.07:07:56.16#ibcon#about to write, iclass 4, count 0 2006.285.07:07:56.16#ibcon#wrote, iclass 4, count 0 2006.285.07:07:56.16#ibcon#about to read 3, iclass 4, count 0 2006.285.07:07:56.19#ibcon#read 3, iclass 4, count 0 2006.285.07:07:56.19#ibcon#about to read 4, iclass 4, count 0 2006.285.07:07:56.19#ibcon#read 4, iclass 4, count 0 2006.285.07:07:56.19#ibcon#about to read 5, iclass 4, count 0 2006.285.07:07:56.19#ibcon#read 5, iclass 4, count 0 2006.285.07:07:56.19#ibcon#about to read 6, iclass 4, count 0 2006.285.07:07:56.19#ibcon#read 6, iclass 4, count 0 2006.285.07:07:56.19#ibcon#end of sib2, iclass 4, count 0 2006.285.07:07:56.19#ibcon#*after write, iclass 4, count 0 2006.285.07:07:56.19#ibcon#*before return 0, iclass 4, count 0 2006.285.07:07:56.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:07:56.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:07:56.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.07:07:56.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.07:07:56.19$setupk4/ifdk4 2006.285.07:07:56.19$ifdk4/lo= 2006.285.07:07:56.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:07:56.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:07:56.19$ifdk4/patch= 2006.285.07:07:56.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:07:56.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:07:56.20$setupk4/!*+20s 2006.285.07:07:57.47#abcon#<5=/05 3.9 6.6 24.19 751014.2\r\n> 2006.285.07:07:57.49#abcon#{5=INTERFACE CLEAR} 2006.285.07:07:57.55#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:08:07.64#abcon#<5=/05 3.9 6.6 24.19 741014.2\r\n> 2006.285.07:08:07.66#abcon#{5=INTERFACE CLEAR} 2006.285.07:08:07.72#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:08:10.71$setupk4/"tpicd 2006.285.07:08:10.71$setupk4/echo=off 2006.285.07:08:10.71$setupk4/xlog=off 2006.285.07:08:10.71:!2006.285.07:13:10 2006.285.07:08:31.14#trakl#Source acquired 2006.285.07:08:33.14#flagr#flagr/antenna,acquired 2006.285.07:13:10.00:preob 2006.285.07:13:10.14/onsource/TRACKING 2006.285.07:13:10.14:!2006.285.07:13:20 2006.285.07:13:20.00:"tape 2006.285.07:13:20.00:"st=record 2006.285.07:13:20.00:data_valid=on 2006.285.07:13:20.00:midob 2006.285.07:13:21.13/onsource/TRACKING 2006.285.07:13:21.13/wx/24.08,1014.2,75 2006.285.07:13:21.19/cable/+6.4741E-03 2006.285.07:13:22.28/va/01,07,usb,yes,31,34 2006.285.07:13:22.28/va/02,06,usb,yes,32,32 2006.285.07:13:22.28/va/03,07,usb,yes,31,33 2006.285.07:13:22.28/va/04,06,usb,yes,32,34 2006.285.07:13:22.28/va/05,03,usb,yes,32,32 2006.285.07:13:22.28/va/06,04,usb,yes,29,28 2006.285.07:13:22.28/va/07,04,usb,yes,29,30 2006.285.07:13:22.28/va/08,03,usb,yes,30,37 2006.285.07:13:22.51/valo/01,524.99,yes,locked 2006.285.07:13:22.51/valo/02,534.99,yes,locked 2006.285.07:13:22.51/valo/03,564.99,yes,locked 2006.285.07:13:22.51/valo/04,624.99,yes,locked 2006.285.07:13:22.51/valo/05,734.99,yes,locked 2006.285.07:13:22.51/valo/06,814.99,yes,locked 2006.285.07:13:22.51/valo/07,864.99,yes,locked 2006.285.07:13:22.51/valo/08,884.99,yes,locked 2006.285.07:13:23.60/vb/01,04,usb,yes,30,28 2006.285.07:13:23.60/vb/02,05,usb,yes,29,29 2006.285.07:13:23.60/vb/03,04,usb,yes,30,33 2006.285.07:13:23.60/vb/04,05,usb,yes,30,29 2006.285.07:13:23.60/vb/05,04,usb,yes,26,29 2006.285.07:13:23.60/vb/06,03,usb,yes,38,34 2006.285.07:13:23.60/vb/07,04,usb,yes,31,31 2006.285.07:13:23.60/vb/08,04,usb,yes,28,31 2006.285.07:13:23.84/vblo/01,629.99,yes,locked 2006.285.07:13:23.84/vblo/02,634.99,yes,locked 2006.285.07:13:23.84/vblo/03,649.99,yes,locked 2006.285.07:13:23.84/vblo/04,679.99,yes,locked 2006.285.07:13:23.84/vblo/05,709.99,yes,locked 2006.285.07:13:23.84/vblo/06,719.99,yes,locked 2006.285.07:13:23.84/vblo/07,734.99,yes,locked 2006.285.07:13:23.84/vblo/08,744.99,yes,locked 2006.285.07:13:23.99/vabw/8 2006.285.07:13:24.14/vbbw/8 2006.285.07:13:24.23/xfe/off,on,12.2 2006.285.07:13:24.61/ifatt/23,28,28,28 2006.285.07:13:25.07/fmout-gps/S +2.65E-07 2006.285.07:13:25.09:!2006.285.07:14:10 2006.285.07:14:10.00:data_valid=off 2006.285.07:14:10.00:"et 2006.285.07:14:10.00:!+3s 2006.285.07:14:13.02:"tape 2006.285.07:14:13.02:postob 2006.285.07:14:13.18/cable/+6.4729E-03 2006.285.07:14:13.18/wx/24.06,1014.2,75 2006.285.07:14:13.24/fmout-gps/S +2.64E-07 2006.285.07:14:13.24:scan_name=285-0718,jd0610,120 2006.285.07:14:13.24:source=3c274,123049.42,122328.0,2000.0,ccw 2006.285.07:14:14.13#flagr#flagr/antenna,new-source 2006.285.07:14:14.13:checkk5 2006.285.07:14:14.48/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:14:14.86/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:14:15.32/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:14:15.70/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:14:16.07/chk_obsdata//k5ts1/T2850713??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.07:14:16.45/chk_obsdata//k5ts2/T2850713??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.07:14:16.90/chk_obsdata//k5ts3/T2850713??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.07:14:17.52/chk_obsdata//k5ts4/T2850713??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.07:14:18.28/k5log//k5ts1_log_newline 2006.285.07:14:19.02/k5log//k5ts2_log_newline 2006.285.07:14:20.06/k5log//k5ts3_log_newline 2006.285.07:14:20.97/k5log//k5ts4_log_newline 2006.285.07:14:20.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:14:20.99:setupk4=1 2006.285.07:14:20.99$setupk4/echo=on 2006.285.07:14:20.99$setupk4/pcalon 2006.285.07:14:20.99$pcalon/"no phase cal control is implemented here 2006.285.07:14:20.99$setupk4/"tpicd=stop 2006.285.07:14:20.99$setupk4/"rec=synch_on 2006.285.07:14:20.99$setupk4/"rec_mode=128 2006.285.07:14:20.99$setupk4/!* 2006.285.07:14:20.99$setupk4/recpk4 2006.285.07:14:20.99$recpk4/recpatch= 2006.285.07:14:20.99$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:14:20.99$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:14:20.99$setupk4/vck44 2006.285.07:14:20.99$vck44/valo=1,524.99 2006.285.07:14:20.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.07:14:20.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.07:14:20.99#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:20.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:14:20.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:14:20.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:14:20.99#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:14:20.99#ibcon#first serial, iclass 19, count 0 2006.285.07:14:20.99#ibcon#enter sib2, iclass 19, count 0 2006.285.07:14:20.99#ibcon#flushed, iclass 19, count 0 2006.285.07:14:20.99#ibcon#about to write, iclass 19, count 0 2006.285.07:14:20.99#ibcon#wrote, iclass 19, count 0 2006.285.07:14:20.99#ibcon#about to read 3, iclass 19, count 0 2006.285.07:14:21.01#ibcon#read 3, iclass 19, count 0 2006.285.07:14:21.01#ibcon#about to read 4, iclass 19, count 0 2006.285.07:14:21.01#ibcon#read 4, iclass 19, count 0 2006.285.07:14:21.01#ibcon#about to read 5, iclass 19, count 0 2006.285.07:14:21.01#ibcon#read 5, iclass 19, count 0 2006.285.07:14:21.01#ibcon#about to read 6, iclass 19, count 0 2006.285.07:14:21.01#ibcon#read 6, iclass 19, count 0 2006.285.07:14:21.01#ibcon#end of sib2, iclass 19, count 0 2006.285.07:14:21.01#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:14:21.01#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:14:21.01#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:14:21.01#ibcon#*before write, iclass 19, count 0 2006.285.07:14:21.01#ibcon#enter sib2, iclass 19, count 0 2006.285.07:14:21.01#ibcon#flushed, iclass 19, count 0 2006.285.07:14:21.01#ibcon#about to write, iclass 19, count 0 2006.285.07:14:21.01#ibcon#wrote, iclass 19, count 0 2006.285.07:14:21.01#ibcon#about to read 3, iclass 19, count 0 2006.285.07:14:21.06#ibcon#read 3, iclass 19, count 0 2006.285.07:14:21.06#ibcon#about to read 4, iclass 19, count 0 2006.285.07:14:21.06#ibcon#read 4, iclass 19, count 0 2006.285.07:14:21.06#ibcon#about to read 5, iclass 19, count 0 2006.285.07:14:21.06#ibcon#read 5, iclass 19, count 0 2006.285.07:14:21.06#ibcon#about to read 6, iclass 19, count 0 2006.285.07:14:21.06#ibcon#read 6, iclass 19, count 0 2006.285.07:14:21.06#ibcon#end of sib2, iclass 19, count 0 2006.285.07:14:21.06#ibcon#*after write, iclass 19, count 0 2006.285.07:14:21.06#ibcon#*before return 0, iclass 19, count 0 2006.285.07:14:21.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:14:21.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:14:21.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:14:21.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:14:21.06$vck44/va=1,7 2006.285.07:14:21.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.07:14:21.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.07:14:21.06#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:21.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:14:21.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:14:21.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:14:21.06#ibcon#enter wrdev, iclass 21, count 2 2006.285.07:14:21.06#ibcon#first serial, iclass 21, count 2 2006.285.07:14:21.06#ibcon#enter sib2, iclass 21, count 2 2006.285.07:14:21.06#ibcon#flushed, iclass 21, count 2 2006.285.07:14:21.06#ibcon#about to write, iclass 21, count 2 2006.285.07:14:21.06#ibcon#wrote, iclass 21, count 2 2006.285.07:14:21.06#ibcon#about to read 3, iclass 21, count 2 2006.285.07:14:21.08#ibcon#read 3, iclass 21, count 2 2006.285.07:14:21.08#ibcon#about to read 4, iclass 21, count 2 2006.285.07:14:21.08#ibcon#read 4, iclass 21, count 2 2006.285.07:14:21.08#ibcon#about to read 5, iclass 21, count 2 2006.285.07:14:21.08#ibcon#read 5, iclass 21, count 2 2006.285.07:14:21.08#ibcon#about to read 6, iclass 21, count 2 2006.285.07:14:21.08#ibcon#read 6, iclass 21, count 2 2006.285.07:14:21.08#ibcon#end of sib2, iclass 21, count 2 2006.285.07:14:21.08#ibcon#*mode == 0, iclass 21, count 2 2006.285.07:14:21.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.07:14:21.08#ibcon#[25=AT01-07\r\n] 2006.285.07:14:21.08#ibcon#*before write, iclass 21, count 2 2006.285.07:14:21.08#ibcon#enter sib2, iclass 21, count 2 2006.285.07:14:21.08#ibcon#flushed, iclass 21, count 2 2006.285.07:14:21.08#ibcon#about to write, iclass 21, count 2 2006.285.07:14:21.08#ibcon#wrote, iclass 21, count 2 2006.285.07:14:21.08#ibcon#about to read 3, iclass 21, count 2 2006.285.07:14:21.11#ibcon#read 3, iclass 21, count 2 2006.285.07:14:21.11#ibcon#about to read 4, iclass 21, count 2 2006.285.07:14:21.11#ibcon#read 4, iclass 21, count 2 2006.285.07:14:21.11#ibcon#about to read 5, iclass 21, count 2 2006.285.07:14:21.11#ibcon#read 5, iclass 21, count 2 2006.285.07:14:21.11#ibcon#about to read 6, iclass 21, count 2 2006.285.07:14:21.11#ibcon#read 6, iclass 21, count 2 2006.285.07:14:21.11#ibcon#end of sib2, iclass 21, count 2 2006.285.07:14:21.11#ibcon#*after write, iclass 21, count 2 2006.285.07:14:21.11#ibcon#*before return 0, iclass 21, count 2 2006.285.07:14:21.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:14:21.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:14:21.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.07:14:21.11#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:21.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:14:21.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:14:21.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:14:21.23#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:14:21.23#ibcon#first serial, iclass 21, count 0 2006.285.07:14:21.23#ibcon#enter sib2, iclass 21, count 0 2006.285.07:14:21.23#ibcon#flushed, iclass 21, count 0 2006.285.07:14:21.23#ibcon#about to write, iclass 21, count 0 2006.285.07:14:21.23#ibcon#wrote, iclass 21, count 0 2006.285.07:14:21.23#ibcon#about to read 3, iclass 21, count 0 2006.285.07:14:21.25#ibcon#read 3, iclass 21, count 0 2006.285.07:14:21.25#ibcon#about to read 4, iclass 21, count 0 2006.285.07:14:21.25#ibcon#read 4, iclass 21, count 0 2006.285.07:14:21.25#ibcon#about to read 5, iclass 21, count 0 2006.285.07:14:21.25#ibcon#read 5, iclass 21, count 0 2006.285.07:14:21.25#ibcon#about to read 6, iclass 21, count 0 2006.285.07:14:21.25#ibcon#read 6, iclass 21, count 0 2006.285.07:14:21.25#ibcon#end of sib2, iclass 21, count 0 2006.285.07:14:21.25#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:14:21.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:14:21.25#ibcon#[25=USB\r\n] 2006.285.07:14:21.25#ibcon#*before write, iclass 21, count 0 2006.285.07:14:21.25#ibcon#enter sib2, iclass 21, count 0 2006.285.07:14:21.25#ibcon#flushed, iclass 21, count 0 2006.285.07:14:21.25#ibcon#about to write, iclass 21, count 0 2006.285.07:14:21.25#ibcon#wrote, iclass 21, count 0 2006.285.07:14:21.25#ibcon#about to read 3, iclass 21, count 0 2006.285.07:14:21.28#ibcon#read 3, iclass 21, count 0 2006.285.07:14:21.28#ibcon#about to read 4, iclass 21, count 0 2006.285.07:14:21.28#ibcon#read 4, iclass 21, count 0 2006.285.07:14:21.28#ibcon#about to read 5, iclass 21, count 0 2006.285.07:14:21.28#ibcon#read 5, iclass 21, count 0 2006.285.07:14:21.28#ibcon#about to read 6, iclass 21, count 0 2006.285.07:14:21.28#ibcon#read 6, iclass 21, count 0 2006.285.07:14:21.28#ibcon#end of sib2, iclass 21, count 0 2006.285.07:14:21.28#ibcon#*after write, iclass 21, count 0 2006.285.07:14:21.28#ibcon#*before return 0, iclass 21, count 0 2006.285.07:14:21.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:14:21.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:14:21.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:14:21.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:14:21.28$vck44/valo=2,534.99 2006.285.07:14:21.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.07:14:21.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.07:14:21.28#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:21.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:14:21.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:14:21.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:14:21.28#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:14:21.28#ibcon#first serial, iclass 23, count 0 2006.285.07:14:21.28#ibcon#enter sib2, iclass 23, count 0 2006.285.07:14:21.28#ibcon#flushed, iclass 23, count 0 2006.285.07:14:21.28#ibcon#about to write, iclass 23, count 0 2006.285.07:14:21.28#ibcon#wrote, iclass 23, count 0 2006.285.07:14:21.28#ibcon#about to read 3, iclass 23, count 0 2006.285.07:14:21.30#ibcon#read 3, iclass 23, count 0 2006.285.07:14:21.30#ibcon#about to read 4, iclass 23, count 0 2006.285.07:14:21.30#ibcon#read 4, iclass 23, count 0 2006.285.07:14:21.30#ibcon#about to read 5, iclass 23, count 0 2006.285.07:14:21.30#ibcon#read 5, iclass 23, count 0 2006.285.07:14:21.30#ibcon#about to read 6, iclass 23, count 0 2006.285.07:14:21.30#ibcon#read 6, iclass 23, count 0 2006.285.07:14:21.30#ibcon#end of sib2, iclass 23, count 0 2006.285.07:14:21.30#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:14:21.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:14:21.30#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:14:21.30#ibcon#*before write, iclass 23, count 0 2006.285.07:14:21.30#ibcon#enter sib2, iclass 23, count 0 2006.285.07:14:21.30#ibcon#flushed, iclass 23, count 0 2006.285.07:14:21.30#ibcon#about to write, iclass 23, count 0 2006.285.07:14:21.30#ibcon#wrote, iclass 23, count 0 2006.285.07:14:21.30#ibcon#about to read 3, iclass 23, count 0 2006.285.07:14:21.34#ibcon#read 3, iclass 23, count 0 2006.285.07:14:21.34#ibcon#about to read 4, iclass 23, count 0 2006.285.07:14:21.34#ibcon#read 4, iclass 23, count 0 2006.285.07:14:21.34#ibcon#about to read 5, iclass 23, count 0 2006.285.07:14:21.34#ibcon#read 5, iclass 23, count 0 2006.285.07:14:21.34#ibcon#about to read 6, iclass 23, count 0 2006.285.07:14:21.34#ibcon#read 6, iclass 23, count 0 2006.285.07:14:21.34#ibcon#end of sib2, iclass 23, count 0 2006.285.07:14:21.34#ibcon#*after write, iclass 23, count 0 2006.285.07:14:21.34#ibcon#*before return 0, iclass 23, count 0 2006.285.07:14:21.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:14:21.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:14:21.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:14:21.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:14:21.34$vck44/va=2,6 2006.285.07:14:21.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.07:14:21.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.07:14:21.34#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:21.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:14:21.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:14:21.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:14:21.40#ibcon#enter wrdev, iclass 25, count 2 2006.285.07:14:21.40#ibcon#first serial, iclass 25, count 2 2006.285.07:14:21.40#ibcon#enter sib2, iclass 25, count 2 2006.285.07:14:21.40#ibcon#flushed, iclass 25, count 2 2006.285.07:14:21.40#ibcon#about to write, iclass 25, count 2 2006.285.07:14:21.40#ibcon#wrote, iclass 25, count 2 2006.285.07:14:21.40#ibcon#about to read 3, iclass 25, count 2 2006.285.07:14:21.42#ibcon#read 3, iclass 25, count 2 2006.285.07:14:21.42#ibcon#about to read 4, iclass 25, count 2 2006.285.07:14:21.42#ibcon#read 4, iclass 25, count 2 2006.285.07:14:21.42#ibcon#about to read 5, iclass 25, count 2 2006.285.07:14:21.42#ibcon#read 5, iclass 25, count 2 2006.285.07:14:21.42#ibcon#about to read 6, iclass 25, count 2 2006.285.07:14:21.42#ibcon#read 6, iclass 25, count 2 2006.285.07:14:21.42#ibcon#end of sib2, iclass 25, count 2 2006.285.07:14:21.42#ibcon#*mode == 0, iclass 25, count 2 2006.285.07:14:21.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.07:14:21.42#ibcon#[25=AT02-06\r\n] 2006.285.07:14:21.42#ibcon#*before write, iclass 25, count 2 2006.285.07:14:21.42#ibcon#enter sib2, iclass 25, count 2 2006.285.07:14:21.42#ibcon#flushed, iclass 25, count 2 2006.285.07:14:21.42#ibcon#about to write, iclass 25, count 2 2006.285.07:14:21.42#ibcon#wrote, iclass 25, count 2 2006.285.07:14:21.42#ibcon#about to read 3, iclass 25, count 2 2006.285.07:14:21.45#ibcon#read 3, iclass 25, count 2 2006.285.07:14:21.45#ibcon#about to read 4, iclass 25, count 2 2006.285.07:14:21.45#ibcon#read 4, iclass 25, count 2 2006.285.07:14:21.45#ibcon#about to read 5, iclass 25, count 2 2006.285.07:14:21.45#ibcon#read 5, iclass 25, count 2 2006.285.07:14:21.45#ibcon#about to read 6, iclass 25, count 2 2006.285.07:14:21.45#ibcon#read 6, iclass 25, count 2 2006.285.07:14:21.45#ibcon#end of sib2, iclass 25, count 2 2006.285.07:14:21.45#ibcon#*after write, iclass 25, count 2 2006.285.07:14:21.45#ibcon#*before return 0, iclass 25, count 2 2006.285.07:14:21.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:14:21.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:14:21.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.07:14:21.45#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:21.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:14:21.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:14:21.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:14:21.57#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:14:21.57#ibcon#first serial, iclass 25, count 0 2006.285.07:14:21.57#ibcon#enter sib2, iclass 25, count 0 2006.285.07:14:21.57#ibcon#flushed, iclass 25, count 0 2006.285.07:14:21.57#ibcon#about to write, iclass 25, count 0 2006.285.07:14:21.57#ibcon#wrote, iclass 25, count 0 2006.285.07:14:21.57#ibcon#about to read 3, iclass 25, count 0 2006.285.07:14:21.59#ibcon#read 3, iclass 25, count 0 2006.285.07:14:21.59#ibcon#about to read 4, iclass 25, count 0 2006.285.07:14:21.59#ibcon#read 4, iclass 25, count 0 2006.285.07:14:21.59#ibcon#about to read 5, iclass 25, count 0 2006.285.07:14:21.59#ibcon#read 5, iclass 25, count 0 2006.285.07:14:21.59#ibcon#about to read 6, iclass 25, count 0 2006.285.07:14:21.59#ibcon#read 6, iclass 25, count 0 2006.285.07:14:21.59#ibcon#end of sib2, iclass 25, count 0 2006.285.07:14:21.59#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:14:21.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:14:21.59#ibcon#[25=USB\r\n] 2006.285.07:14:21.59#ibcon#*before write, iclass 25, count 0 2006.285.07:14:21.59#ibcon#enter sib2, iclass 25, count 0 2006.285.07:14:21.59#ibcon#flushed, iclass 25, count 0 2006.285.07:14:21.59#ibcon#about to write, iclass 25, count 0 2006.285.07:14:21.59#ibcon#wrote, iclass 25, count 0 2006.285.07:14:21.59#ibcon#about to read 3, iclass 25, count 0 2006.285.07:14:21.62#ibcon#read 3, iclass 25, count 0 2006.285.07:14:21.62#ibcon#about to read 4, iclass 25, count 0 2006.285.07:14:21.62#ibcon#read 4, iclass 25, count 0 2006.285.07:14:21.62#ibcon#about to read 5, iclass 25, count 0 2006.285.07:14:21.62#ibcon#read 5, iclass 25, count 0 2006.285.07:14:21.62#ibcon#about to read 6, iclass 25, count 0 2006.285.07:14:21.62#ibcon#read 6, iclass 25, count 0 2006.285.07:14:21.62#ibcon#end of sib2, iclass 25, count 0 2006.285.07:14:21.62#ibcon#*after write, iclass 25, count 0 2006.285.07:14:21.62#ibcon#*before return 0, iclass 25, count 0 2006.285.07:14:21.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:14:21.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:14:21.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:14:21.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:14:21.62$vck44/valo=3,564.99 2006.285.07:14:21.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.07:14:21.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.07:14:21.62#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:21.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:14:21.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:14:21.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:14:21.62#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:14:21.62#ibcon#first serial, iclass 27, count 0 2006.285.07:14:21.62#ibcon#enter sib2, iclass 27, count 0 2006.285.07:14:21.62#ibcon#flushed, iclass 27, count 0 2006.285.07:14:21.62#ibcon#about to write, iclass 27, count 0 2006.285.07:14:21.62#ibcon#wrote, iclass 27, count 0 2006.285.07:14:21.62#ibcon#about to read 3, iclass 27, count 0 2006.285.07:14:21.64#ibcon#read 3, iclass 27, count 0 2006.285.07:14:21.64#ibcon#about to read 4, iclass 27, count 0 2006.285.07:14:21.64#ibcon#read 4, iclass 27, count 0 2006.285.07:14:21.64#ibcon#about to read 5, iclass 27, count 0 2006.285.07:14:21.64#ibcon#read 5, iclass 27, count 0 2006.285.07:14:21.64#ibcon#about to read 6, iclass 27, count 0 2006.285.07:14:21.64#ibcon#read 6, iclass 27, count 0 2006.285.07:14:21.64#ibcon#end of sib2, iclass 27, count 0 2006.285.07:14:21.64#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:14:21.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:14:21.64#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:14:21.64#ibcon#*before write, iclass 27, count 0 2006.285.07:14:21.64#ibcon#enter sib2, iclass 27, count 0 2006.285.07:14:21.64#ibcon#flushed, iclass 27, count 0 2006.285.07:14:21.64#ibcon#about to write, iclass 27, count 0 2006.285.07:14:21.64#ibcon#wrote, iclass 27, count 0 2006.285.07:14:21.64#ibcon#about to read 3, iclass 27, count 0 2006.285.07:14:21.68#ibcon#read 3, iclass 27, count 0 2006.285.07:14:21.68#ibcon#about to read 4, iclass 27, count 0 2006.285.07:14:21.68#ibcon#read 4, iclass 27, count 0 2006.285.07:14:21.68#ibcon#about to read 5, iclass 27, count 0 2006.285.07:14:21.68#ibcon#read 5, iclass 27, count 0 2006.285.07:14:21.68#ibcon#about to read 6, iclass 27, count 0 2006.285.07:14:21.68#ibcon#read 6, iclass 27, count 0 2006.285.07:14:21.68#ibcon#end of sib2, iclass 27, count 0 2006.285.07:14:21.68#ibcon#*after write, iclass 27, count 0 2006.285.07:14:21.68#ibcon#*before return 0, iclass 27, count 0 2006.285.07:14:21.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:14:21.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:14:21.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:14:21.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:14:21.68$vck44/va=3,7 2006.285.07:14:21.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.07:14:21.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.07:14:21.68#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:21.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:14:21.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:14:21.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:14:21.74#ibcon#enter wrdev, iclass 29, count 2 2006.285.07:14:21.74#ibcon#first serial, iclass 29, count 2 2006.285.07:14:21.74#ibcon#enter sib2, iclass 29, count 2 2006.285.07:14:21.74#ibcon#flushed, iclass 29, count 2 2006.285.07:14:21.74#ibcon#about to write, iclass 29, count 2 2006.285.07:14:21.74#ibcon#wrote, iclass 29, count 2 2006.285.07:14:21.74#ibcon#about to read 3, iclass 29, count 2 2006.285.07:14:21.76#ibcon#read 3, iclass 29, count 2 2006.285.07:14:21.76#ibcon#about to read 4, iclass 29, count 2 2006.285.07:14:21.76#ibcon#read 4, iclass 29, count 2 2006.285.07:14:21.76#ibcon#about to read 5, iclass 29, count 2 2006.285.07:14:21.76#ibcon#read 5, iclass 29, count 2 2006.285.07:14:21.76#ibcon#about to read 6, iclass 29, count 2 2006.285.07:14:21.76#ibcon#read 6, iclass 29, count 2 2006.285.07:14:21.76#ibcon#end of sib2, iclass 29, count 2 2006.285.07:14:21.76#ibcon#*mode == 0, iclass 29, count 2 2006.285.07:14:21.76#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.07:14:21.76#ibcon#[25=AT03-07\r\n] 2006.285.07:14:21.76#ibcon#*before write, iclass 29, count 2 2006.285.07:14:21.76#ibcon#enter sib2, iclass 29, count 2 2006.285.07:14:21.76#ibcon#flushed, iclass 29, count 2 2006.285.07:14:21.76#ibcon#about to write, iclass 29, count 2 2006.285.07:14:21.76#ibcon#wrote, iclass 29, count 2 2006.285.07:14:21.76#ibcon#about to read 3, iclass 29, count 2 2006.285.07:14:21.79#ibcon#read 3, iclass 29, count 2 2006.285.07:14:21.79#ibcon#about to read 4, iclass 29, count 2 2006.285.07:14:21.79#ibcon#read 4, iclass 29, count 2 2006.285.07:14:21.79#ibcon#about to read 5, iclass 29, count 2 2006.285.07:14:21.79#ibcon#read 5, iclass 29, count 2 2006.285.07:14:21.79#ibcon#about to read 6, iclass 29, count 2 2006.285.07:14:21.79#ibcon#read 6, iclass 29, count 2 2006.285.07:14:21.79#ibcon#end of sib2, iclass 29, count 2 2006.285.07:14:21.79#ibcon#*after write, iclass 29, count 2 2006.285.07:14:21.79#ibcon#*before return 0, iclass 29, count 2 2006.285.07:14:21.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:14:21.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:14:21.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.07:14:21.79#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:21.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:14:21.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:14:21.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:14:21.91#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:14:21.91#ibcon#first serial, iclass 29, count 0 2006.285.07:14:21.91#ibcon#enter sib2, iclass 29, count 0 2006.285.07:14:21.91#ibcon#flushed, iclass 29, count 0 2006.285.07:14:21.91#ibcon#about to write, iclass 29, count 0 2006.285.07:14:21.91#ibcon#wrote, iclass 29, count 0 2006.285.07:14:21.91#ibcon#about to read 3, iclass 29, count 0 2006.285.07:14:21.93#ibcon#read 3, iclass 29, count 0 2006.285.07:14:21.93#ibcon#about to read 4, iclass 29, count 0 2006.285.07:14:21.93#ibcon#read 4, iclass 29, count 0 2006.285.07:14:21.93#ibcon#about to read 5, iclass 29, count 0 2006.285.07:14:21.93#ibcon#read 5, iclass 29, count 0 2006.285.07:14:21.93#ibcon#about to read 6, iclass 29, count 0 2006.285.07:14:21.93#ibcon#read 6, iclass 29, count 0 2006.285.07:14:21.93#ibcon#end of sib2, iclass 29, count 0 2006.285.07:14:21.93#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:14:21.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:14:21.93#ibcon#[25=USB\r\n] 2006.285.07:14:21.93#ibcon#*before write, iclass 29, count 0 2006.285.07:14:21.93#ibcon#enter sib2, iclass 29, count 0 2006.285.07:14:21.93#ibcon#flushed, iclass 29, count 0 2006.285.07:14:21.93#ibcon#about to write, iclass 29, count 0 2006.285.07:14:21.93#ibcon#wrote, iclass 29, count 0 2006.285.07:14:21.93#ibcon#about to read 3, iclass 29, count 0 2006.285.07:14:21.96#ibcon#read 3, iclass 29, count 0 2006.285.07:14:21.96#ibcon#about to read 4, iclass 29, count 0 2006.285.07:14:21.96#ibcon#read 4, iclass 29, count 0 2006.285.07:14:21.96#ibcon#about to read 5, iclass 29, count 0 2006.285.07:14:21.96#ibcon#read 5, iclass 29, count 0 2006.285.07:14:21.96#ibcon#about to read 6, iclass 29, count 0 2006.285.07:14:21.96#ibcon#read 6, iclass 29, count 0 2006.285.07:14:21.96#ibcon#end of sib2, iclass 29, count 0 2006.285.07:14:21.96#ibcon#*after write, iclass 29, count 0 2006.285.07:14:21.96#ibcon#*before return 0, iclass 29, count 0 2006.285.07:14:21.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:14:21.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:14:21.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:14:21.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:14:21.96$vck44/valo=4,624.99 2006.285.07:14:21.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.07:14:21.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.07:14:21.96#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:21.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:14:21.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:14:21.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:14:21.96#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:14:21.96#ibcon#first serial, iclass 31, count 0 2006.285.07:14:21.96#ibcon#enter sib2, iclass 31, count 0 2006.285.07:14:21.96#ibcon#flushed, iclass 31, count 0 2006.285.07:14:21.96#ibcon#about to write, iclass 31, count 0 2006.285.07:14:21.96#ibcon#wrote, iclass 31, count 0 2006.285.07:14:21.96#ibcon#about to read 3, iclass 31, count 0 2006.285.07:14:21.98#ibcon#read 3, iclass 31, count 0 2006.285.07:14:21.98#ibcon#about to read 4, iclass 31, count 0 2006.285.07:14:21.98#ibcon#read 4, iclass 31, count 0 2006.285.07:14:21.98#ibcon#about to read 5, iclass 31, count 0 2006.285.07:14:21.98#ibcon#read 5, iclass 31, count 0 2006.285.07:14:21.98#ibcon#about to read 6, iclass 31, count 0 2006.285.07:14:21.98#ibcon#read 6, iclass 31, count 0 2006.285.07:14:21.98#ibcon#end of sib2, iclass 31, count 0 2006.285.07:14:21.98#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:14:21.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:14:21.98#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:14:21.98#ibcon#*before write, iclass 31, count 0 2006.285.07:14:21.98#ibcon#enter sib2, iclass 31, count 0 2006.285.07:14:21.98#ibcon#flushed, iclass 31, count 0 2006.285.07:14:21.98#ibcon#about to write, iclass 31, count 0 2006.285.07:14:21.98#ibcon#wrote, iclass 31, count 0 2006.285.07:14:21.98#ibcon#about to read 3, iclass 31, count 0 2006.285.07:14:22.02#ibcon#read 3, iclass 31, count 0 2006.285.07:14:22.02#ibcon#about to read 4, iclass 31, count 0 2006.285.07:14:22.02#ibcon#read 4, iclass 31, count 0 2006.285.07:14:22.02#ibcon#about to read 5, iclass 31, count 0 2006.285.07:14:22.02#ibcon#read 5, iclass 31, count 0 2006.285.07:14:22.02#ibcon#about to read 6, iclass 31, count 0 2006.285.07:14:22.02#ibcon#read 6, iclass 31, count 0 2006.285.07:14:22.02#ibcon#end of sib2, iclass 31, count 0 2006.285.07:14:22.02#ibcon#*after write, iclass 31, count 0 2006.285.07:14:22.02#ibcon#*before return 0, iclass 31, count 0 2006.285.07:14:22.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:14:22.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:14:22.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:14:22.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:14:22.02$vck44/va=4,6 2006.285.07:14:22.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.07:14:22.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.07:14:22.02#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:22.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:14:22.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:14:22.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:14:22.08#ibcon#enter wrdev, iclass 33, count 2 2006.285.07:14:22.08#ibcon#first serial, iclass 33, count 2 2006.285.07:14:22.08#ibcon#enter sib2, iclass 33, count 2 2006.285.07:14:22.08#ibcon#flushed, iclass 33, count 2 2006.285.07:14:22.08#ibcon#about to write, iclass 33, count 2 2006.285.07:14:22.08#ibcon#wrote, iclass 33, count 2 2006.285.07:14:22.08#ibcon#about to read 3, iclass 33, count 2 2006.285.07:14:22.10#ibcon#read 3, iclass 33, count 2 2006.285.07:14:22.10#ibcon#about to read 4, iclass 33, count 2 2006.285.07:14:22.10#ibcon#read 4, iclass 33, count 2 2006.285.07:14:22.10#ibcon#about to read 5, iclass 33, count 2 2006.285.07:14:22.10#ibcon#read 5, iclass 33, count 2 2006.285.07:14:22.10#ibcon#about to read 6, iclass 33, count 2 2006.285.07:14:22.10#ibcon#read 6, iclass 33, count 2 2006.285.07:14:22.10#ibcon#end of sib2, iclass 33, count 2 2006.285.07:14:22.10#ibcon#*mode == 0, iclass 33, count 2 2006.285.07:14:22.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.07:14:22.10#ibcon#[25=AT04-06\r\n] 2006.285.07:14:22.10#ibcon#*before write, iclass 33, count 2 2006.285.07:14:22.10#ibcon#enter sib2, iclass 33, count 2 2006.285.07:14:22.10#ibcon#flushed, iclass 33, count 2 2006.285.07:14:22.10#ibcon#about to write, iclass 33, count 2 2006.285.07:14:22.10#ibcon#wrote, iclass 33, count 2 2006.285.07:14:22.10#ibcon#about to read 3, iclass 33, count 2 2006.285.07:14:22.13#ibcon#read 3, iclass 33, count 2 2006.285.07:14:22.13#ibcon#about to read 4, iclass 33, count 2 2006.285.07:14:22.13#ibcon#read 4, iclass 33, count 2 2006.285.07:14:22.13#ibcon#about to read 5, iclass 33, count 2 2006.285.07:14:22.13#ibcon#read 5, iclass 33, count 2 2006.285.07:14:22.13#ibcon#about to read 6, iclass 33, count 2 2006.285.07:14:22.13#ibcon#read 6, iclass 33, count 2 2006.285.07:14:22.13#ibcon#end of sib2, iclass 33, count 2 2006.285.07:14:22.13#ibcon#*after write, iclass 33, count 2 2006.285.07:14:22.13#ibcon#*before return 0, iclass 33, count 2 2006.285.07:14:22.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:14:22.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:14:22.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.07:14:22.13#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:22.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:14:22.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:14:22.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:14:22.25#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:14:22.25#ibcon#first serial, iclass 33, count 0 2006.285.07:14:22.25#ibcon#enter sib2, iclass 33, count 0 2006.285.07:14:22.25#ibcon#flushed, iclass 33, count 0 2006.285.07:14:22.25#ibcon#about to write, iclass 33, count 0 2006.285.07:14:22.25#ibcon#wrote, iclass 33, count 0 2006.285.07:14:22.25#ibcon#about to read 3, iclass 33, count 0 2006.285.07:14:22.27#ibcon#read 3, iclass 33, count 0 2006.285.07:14:22.27#ibcon#about to read 4, iclass 33, count 0 2006.285.07:14:22.27#ibcon#read 4, iclass 33, count 0 2006.285.07:14:22.27#ibcon#about to read 5, iclass 33, count 0 2006.285.07:14:22.27#ibcon#read 5, iclass 33, count 0 2006.285.07:14:22.27#ibcon#about to read 6, iclass 33, count 0 2006.285.07:14:22.27#ibcon#read 6, iclass 33, count 0 2006.285.07:14:22.27#ibcon#end of sib2, iclass 33, count 0 2006.285.07:14:22.27#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:14:22.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:14:22.27#ibcon#[25=USB\r\n] 2006.285.07:14:22.27#ibcon#*before write, iclass 33, count 0 2006.285.07:14:22.27#ibcon#enter sib2, iclass 33, count 0 2006.285.07:14:22.27#ibcon#flushed, iclass 33, count 0 2006.285.07:14:22.27#ibcon#about to write, iclass 33, count 0 2006.285.07:14:22.27#ibcon#wrote, iclass 33, count 0 2006.285.07:14:22.27#ibcon#about to read 3, iclass 33, count 0 2006.285.07:14:22.30#ibcon#read 3, iclass 33, count 0 2006.285.07:14:22.30#ibcon#about to read 4, iclass 33, count 0 2006.285.07:14:22.30#ibcon#read 4, iclass 33, count 0 2006.285.07:14:22.30#ibcon#about to read 5, iclass 33, count 0 2006.285.07:14:22.30#ibcon#read 5, iclass 33, count 0 2006.285.07:14:22.30#ibcon#about to read 6, iclass 33, count 0 2006.285.07:14:22.30#ibcon#read 6, iclass 33, count 0 2006.285.07:14:22.30#ibcon#end of sib2, iclass 33, count 0 2006.285.07:14:22.30#ibcon#*after write, iclass 33, count 0 2006.285.07:14:22.30#ibcon#*before return 0, iclass 33, count 0 2006.285.07:14:22.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:14:22.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:14:22.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:14:22.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:14:22.30$vck44/valo=5,734.99 2006.285.07:14:22.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.07:14:22.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.07:14:22.30#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:22.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:14:22.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:14:22.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:14:22.30#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:14:22.30#ibcon#first serial, iclass 35, count 0 2006.285.07:14:22.30#ibcon#enter sib2, iclass 35, count 0 2006.285.07:14:22.30#ibcon#flushed, iclass 35, count 0 2006.285.07:14:22.30#ibcon#about to write, iclass 35, count 0 2006.285.07:14:22.30#ibcon#wrote, iclass 35, count 0 2006.285.07:14:22.30#ibcon#about to read 3, iclass 35, count 0 2006.285.07:14:22.32#ibcon#read 3, iclass 35, count 0 2006.285.07:14:22.32#ibcon#about to read 4, iclass 35, count 0 2006.285.07:14:22.32#ibcon#read 4, iclass 35, count 0 2006.285.07:14:22.32#ibcon#about to read 5, iclass 35, count 0 2006.285.07:14:22.32#ibcon#read 5, iclass 35, count 0 2006.285.07:14:22.32#ibcon#about to read 6, iclass 35, count 0 2006.285.07:14:22.32#ibcon#read 6, iclass 35, count 0 2006.285.07:14:22.32#ibcon#end of sib2, iclass 35, count 0 2006.285.07:14:22.32#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:14:22.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:14:22.32#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:14:22.32#ibcon#*before write, iclass 35, count 0 2006.285.07:14:22.32#ibcon#enter sib2, iclass 35, count 0 2006.285.07:14:22.32#ibcon#flushed, iclass 35, count 0 2006.285.07:14:22.32#ibcon#about to write, iclass 35, count 0 2006.285.07:14:22.32#ibcon#wrote, iclass 35, count 0 2006.285.07:14:22.32#ibcon#about to read 3, iclass 35, count 0 2006.285.07:14:22.36#ibcon#read 3, iclass 35, count 0 2006.285.07:14:22.36#ibcon#about to read 4, iclass 35, count 0 2006.285.07:14:22.36#ibcon#read 4, iclass 35, count 0 2006.285.07:14:22.36#ibcon#about to read 5, iclass 35, count 0 2006.285.07:14:22.36#ibcon#read 5, iclass 35, count 0 2006.285.07:14:22.36#ibcon#about to read 6, iclass 35, count 0 2006.285.07:14:22.36#ibcon#read 6, iclass 35, count 0 2006.285.07:14:22.36#ibcon#end of sib2, iclass 35, count 0 2006.285.07:14:22.36#ibcon#*after write, iclass 35, count 0 2006.285.07:14:22.36#ibcon#*before return 0, iclass 35, count 0 2006.285.07:14:22.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:14:22.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:14:22.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:14:22.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:14:22.36$vck44/va=5,3 2006.285.07:14:22.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.07:14:22.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.07:14:22.36#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:22.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:14:22.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:14:22.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:14:22.42#ibcon#enter wrdev, iclass 37, count 2 2006.285.07:14:22.42#ibcon#first serial, iclass 37, count 2 2006.285.07:14:22.42#ibcon#enter sib2, iclass 37, count 2 2006.285.07:14:22.42#ibcon#flushed, iclass 37, count 2 2006.285.07:14:22.42#ibcon#about to write, iclass 37, count 2 2006.285.07:14:22.42#ibcon#wrote, iclass 37, count 2 2006.285.07:14:22.42#ibcon#about to read 3, iclass 37, count 2 2006.285.07:14:22.44#ibcon#read 3, iclass 37, count 2 2006.285.07:14:22.44#ibcon#about to read 4, iclass 37, count 2 2006.285.07:14:22.44#ibcon#read 4, iclass 37, count 2 2006.285.07:14:22.44#ibcon#about to read 5, iclass 37, count 2 2006.285.07:14:22.44#ibcon#read 5, iclass 37, count 2 2006.285.07:14:22.44#ibcon#about to read 6, iclass 37, count 2 2006.285.07:14:22.44#ibcon#read 6, iclass 37, count 2 2006.285.07:14:22.44#ibcon#end of sib2, iclass 37, count 2 2006.285.07:14:22.44#ibcon#*mode == 0, iclass 37, count 2 2006.285.07:14:22.44#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.07:14:22.44#ibcon#[25=AT05-03\r\n] 2006.285.07:14:22.44#ibcon#*before write, iclass 37, count 2 2006.285.07:14:22.44#ibcon#enter sib2, iclass 37, count 2 2006.285.07:14:22.44#ibcon#flushed, iclass 37, count 2 2006.285.07:14:22.44#ibcon#about to write, iclass 37, count 2 2006.285.07:14:22.44#ibcon#wrote, iclass 37, count 2 2006.285.07:14:22.44#ibcon#about to read 3, iclass 37, count 2 2006.285.07:14:22.47#ibcon#read 3, iclass 37, count 2 2006.285.07:14:22.47#ibcon#about to read 4, iclass 37, count 2 2006.285.07:14:22.47#ibcon#read 4, iclass 37, count 2 2006.285.07:14:22.47#ibcon#about to read 5, iclass 37, count 2 2006.285.07:14:22.47#ibcon#read 5, iclass 37, count 2 2006.285.07:14:22.47#ibcon#about to read 6, iclass 37, count 2 2006.285.07:14:22.47#ibcon#read 6, iclass 37, count 2 2006.285.07:14:22.47#ibcon#end of sib2, iclass 37, count 2 2006.285.07:14:22.47#ibcon#*after write, iclass 37, count 2 2006.285.07:14:22.47#ibcon#*before return 0, iclass 37, count 2 2006.285.07:14:22.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:14:22.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:14:22.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.07:14:22.47#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:22.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:14:22.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:14:22.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:14:22.59#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:14:22.59#ibcon#first serial, iclass 37, count 0 2006.285.07:14:22.59#ibcon#enter sib2, iclass 37, count 0 2006.285.07:14:22.59#ibcon#flushed, iclass 37, count 0 2006.285.07:14:22.59#ibcon#about to write, iclass 37, count 0 2006.285.07:14:22.59#ibcon#wrote, iclass 37, count 0 2006.285.07:14:22.59#ibcon#about to read 3, iclass 37, count 0 2006.285.07:14:22.61#ibcon#read 3, iclass 37, count 0 2006.285.07:14:22.61#ibcon#about to read 4, iclass 37, count 0 2006.285.07:14:22.61#ibcon#read 4, iclass 37, count 0 2006.285.07:14:22.61#ibcon#about to read 5, iclass 37, count 0 2006.285.07:14:22.61#ibcon#read 5, iclass 37, count 0 2006.285.07:14:22.61#ibcon#about to read 6, iclass 37, count 0 2006.285.07:14:22.61#ibcon#read 6, iclass 37, count 0 2006.285.07:14:22.61#ibcon#end of sib2, iclass 37, count 0 2006.285.07:14:22.61#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:14:22.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:14:22.61#ibcon#[25=USB\r\n] 2006.285.07:14:22.61#ibcon#*before write, iclass 37, count 0 2006.285.07:14:22.61#ibcon#enter sib2, iclass 37, count 0 2006.285.07:14:22.61#ibcon#flushed, iclass 37, count 0 2006.285.07:14:22.61#ibcon#about to write, iclass 37, count 0 2006.285.07:14:22.61#ibcon#wrote, iclass 37, count 0 2006.285.07:14:22.61#ibcon#about to read 3, iclass 37, count 0 2006.285.07:14:22.64#ibcon#read 3, iclass 37, count 0 2006.285.07:14:22.64#ibcon#about to read 4, iclass 37, count 0 2006.285.07:14:22.64#ibcon#read 4, iclass 37, count 0 2006.285.07:14:22.64#ibcon#about to read 5, iclass 37, count 0 2006.285.07:14:22.64#ibcon#read 5, iclass 37, count 0 2006.285.07:14:22.64#ibcon#about to read 6, iclass 37, count 0 2006.285.07:14:22.64#ibcon#read 6, iclass 37, count 0 2006.285.07:14:22.64#ibcon#end of sib2, iclass 37, count 0 2006.285.07:14:22.64#ibcon#*after write, iclass 37, count 0 2006.285.07:14:22.64#ibcon#*before return 0, iclass 37, count 0 2006.285.07:14:22.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:14:22.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:14:22.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:14:22.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:14:22.64$vck44/valo=6,814.99 2006.285.07:14:22.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.07:14:22.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.07:14:22.64#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:22.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:14:22.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:14:22.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:14:22.64#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:14:22.64#ibcon#first serial, iclass 39, count 0 2006.285.07:14:22.64#ibcon#enter sib2, iclass 39, count 0 2006.285.07:14:22.64#ibcon#flushed, iclass 39, count 0 2006.285.07:14:22.64#ibcon#about to write, iclass 39, count 0 2006.285.07:14:22.64#ibcon#wrote, iclass 39, count 0 2006.285.07:14:22.64#ibcon#about to read 3, iclass 39, count 0 2006.285.07:14:22.66#ibcon#read 3, iclass 39, count 0 2006.285.07:14:22.66#ibcon#about to read 4, iclass 39, count 0 2006.285.07:14:22.66#ibcon#read 4, iclass 39, count 0 2006.285.07:14:22.66#ibcon#about to read 5, iclass 39, count 0 2006.285.07:14:22.66#ibcon#read 5, iclass 39, count 0 2006.285.07:14:22.66#ibcon#about to read 6, iclass 39, count 0 2006.285.07:14:22.66#ibcon#read 6, iclass 39, count 0 2006.285.07:14:22.66#ibcon#end of sib2, iclass 39, count 0 2006.285.07:14:22.66#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:14:22.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:14:22.66#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:14:22.66#ibcon#*before write, iclass 39, count 0 2006.285.07:14:22.66#ibcon#enter sib2, iclass 39, count 0 2006.285.07:14:22.66#ibcon#flushed, iclass 39, count 0 2006.285.07:14:22.66#ibcon#about to write, iclass 39, count 0 2006.285.07:14:22.66#ibcon#wrote, iclass 39, count 0 2006.285.07:14:22.66#ibcon#about to read 3, iclass 39, count 0 2006.285.07:14:22.70#ibcon#read 3, iclass 39, count 0 2006.285.07:14:22.70#ibcon#about to read 4, iclass 39, count 0 2006.285.07:14:22.70#ibcon#read 4, iclass 39, count 0 2006.285.07:14:22.70#ibcon#about to read 5, iclass 39, count 0 2006.285.07:14:22.70#ibcon#read 5, iclass 39, count 0 2006.285.07:14:22.70#ibcon#about to read 6, iclass 39, count 0 2006.285.07:14:22.70#ibcon#read 6, iclass 39, count 0 2006.285.07:14:22.70#ibcon#end of sib2, iclass 39, count 0 2006.285.07:14:22.70#ibcon#*after write, iclass 39, count 0 2006.285.07:14:22.70#ibcon#*before return 0, iclass 39, count 0 2006.285.07:14:22.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:14:22.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:14:22.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:14:22.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:14:22.70$vck44/va=6,4 2006.285.07:14:22.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.07:14:22.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.07:14:22.70#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:22.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:14:22.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:14:22.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:14:22.76#ibcon#enter wrdev, iclass 3, count 2 2006.285.07:14:22.76#ibcon#first serial, iclass 3, count 2 2006.285.07:14:22.76#ibcon#enter sib2, iclass 3, count 2 2006.285.07:14:22.76#ibcon#flushed, iclass 3, count 2 2006.285.07:14:22.76#ibcon#about to write, iclass 3, count 2 2006.285.07:14:22.76#ibcon#wrote, iclass 3, count 2 2006.285.07:14:22.76#ibcon#about to read 3, iclass 3, count 2 2006.285.07:14:22.78#ibcon#read 3, iclass 3, count 2 2006.285.07:14:22.78#ibcon#about to read 4, iclass 3, count 2 2006.285.07:14:22.78#ibcon#read 4, iclass 3, count 2 2006.285.07:14:22.78#ibcon#about to read 5, iclass 3, count 2 2006.285.07:14:22.78#ibcon#read 5, iclass 3, count 2 2006.285.07:14:22.78#ibcon#about to read 6, iclass 3, count 2 2006.285.07:14:22.78#ibcon#read 6, iclass 3, count 2 2006.285.07:14:22.78#ibcon#end of sib2, iclass 3, count 2 2006.285.07:14:22.78#ibcon#*mode == 0, iclass 3, count 2 2006.285.07:14:22.78#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.07:14:22.78#ibcon#[25=AT06-04\r\n] 2006.285.07:14:22.78#ibcon#*before write, iclass 3, count 2 2006.285.07:14:22.78#ibcon#enter sib2, iclass 3, count 2 2006.285.07:14:22.78#ibcon#flushed, iclass 3, count 2 2006.285.07:14:22.78#ibcon#about to write, iclass 3, count 2 2006.285.07:14:22.78#ibcon#wrote, iclass 3, count 2 2006.285.07:14:22.78#ibcon#about to read 3, iclass 3, count 2 2006.285.07:14:22.81#ibcon#read 3, iclass 3, count 2 2006.285.07:14:22.81#ibcon#about to read 4, iclass 3, count 2 2006.285.07:14:22.81#ibcon#read 4, iclass 3, count 2 2006.285.07:14:22.81#ibcon#about to read 5, iclass 3, count 2 2006.285.07:14:22.81#ibcon#read 5, iclass 3, count 2 2006.285.07:14:22.81#ibcon#about to read 6, iclass 3, count 2 2006.285.07:14:22.81#ibcon#read 6, iclass 3, count 2 2006.285.07:14:22.81#ibcon#end of sib2, iclass 3, count 2 2006.285.07:14:22.81#ibcon#*after write, iclass 3, count 2 2006.285.07:14:22.81#ibcon#*before return 0, iclass 3, count 2 2006.285.07:14:22.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:14:22.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:14:22.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.07:14:22.81#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:22.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:14:22.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:14:22.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:14:22.93#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:14:22.93#ibcon#first serial, iclass 3, count 0 2006.285.07:14:22.93#ibcon#enter sib2, iclass 3, count 0 2006.285.07:14:22.93#ibcon#flushed, iclass 3, count 0 2006.285.07:14:22.93#ibcon#about to write, iclass 3, count 0 2006.285.07:14:22.93#ibcon#wrote, iclass 3, count 0 2006.285.07:14:22.93#ibcon#about to read 3, iclass 3, count 0 2006.285.07:14:22.95#ibcon#read 3, iclass 3, count 0 2006.285.07:14:22.95#ibcon#about to read 4, iclass 3, count 0 2006.285.07:14:22.95#ibcon#read 4, iclass 3, count 0 2006.285.07:14:22.95#ibcon#about to read 5, iclass 3, count 0 2006.285.07:14:22.95#ibcon#read 5, iclass 3, count 0 2006.285.07:14:22.95#ibcon#about to read 6, iclass 3, count 0 2006.285.07:14:22.95#ibcon#read 6, iclass 3, count 0 2006.285.07:14:22.95#ibcon#end of sib2, iclass 3, count 0 2006.285.07:14:22.95#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:14:22.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:14:22.95#ibcon#[25=USB\r\n] 2006.285.07:14:22.95#ibcon#*before write, iclass 3, count 0 2006.285.07:14:22.95#ibcon#enter sib2, iclass 3, count 0 2006.285.07:14:22.95#ibcon#flushed, iclass 3, count 0 2006.285.07:14:22.95#ibcon#about to write, iclass 3, count 0 2006.285.07:14:22.95#ibcon#wrote, iclass 3, count 0 2006.285.07:14:22.95#ibcon#about to read 3, iclass 3, count 0 2006.285.07:14:22.98#ibcon#read 3, iclass 3, count 0 2006.285.07:14:22.98#ibcon#about to read 4, iclass 3, count 0 2006.285.07:14:22.98#ibcon#read 4, iclass 3, count 0 2006.285.07:14:22.98#ibcon#about to read 5, iclass 3, count 0 2006.285.07:14:22.98#ibcon#read 5, iclass 3, count 0 2006.285.07:14:22.98#ibcon#about to read 6, iclass 3, count 0 2006.285.07:14:22.98#ibcon#read 6, iclass 3, count 0 2006.285.07:14:22.98#ibcon#end of sib2, iclass 3, count 0 2006.285.07:14:22.98#ibcon#*after write, iclass 3, count 0 2006.285.07:14:22.98#ibcon#*before return 0, iclass 3, count 0 2006.285.07:14:22.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:14:22.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:14:22.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:14:22.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:14:22.98$vck44/valo=7,864.99 2006.285.07:14:22.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.07:14:22.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.07:14:22.98#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:22.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:14:22.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:14:22.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:14:22.98#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:14:22.98#ibcon#first serial, iclass 5, count 0 2006.285.07:14:22.98#ibcon#enter sib2, iclass 5, count 0 2006.285.07:14:22.98#ibcon#flushed, iclass 5, count 0 2006.285.07:14:22.98#ibcon#about to write, iclass 5, count 0 2006.285.07:14:22.98#ibcon#wrote, iclass 5, count 0 2006.285.07:14:22.98#ibcon#about to read 3, iclass 5, count 0 2006.285.07:14:23.00#ibcon#read 3, iclass 5, count 0 2006.285.07:14:23.00#ibcon#about to read 4, iclass 5, count 0 2006.285.07:14:23.00#ibcon#read 4, iclass 5, count 0 2006.285.07:14:23.00#ibcon#about to read 5, iclass 5, count 0 2006.285.07:14:23.00#ibcon#read 5, iclass 5, count 0 2006.285.07:14:23.00#ibcon#about to read 6, iclass 5, count 0 2006.285.07:14:23.00#ibcon#read 6, iclass 5, count 0 2006.285.07:14:23.00#ibcon#end of sib2, iclass 5, count 0 2006.285.07:14:23.00#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:14:23.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:14:23.00#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:14:23.00#ibcon#*before write, iclass 5, count 0 2006.285.07:14:23.00#ibcon#enter sib2, iclass 5, count 0 2006.285.07:14:23.00#ibcon#flushed, iclass 5, count 0 2006.285.07:14:23.00#ibcon#about to write, iclass 5, count 0 2006.285.07:14:23.00#ibcon#wrote, iclass 5, count 0 2006.285.07:14:23.00#ibcon#about to read 3, iclass 5, count 0 2006.285.07:14:23.04#ibcon#read 3, iclass 5, count 0 2006.285.07:14:23.04#ibcon#about to read 4, iclass 5, count 0 2006.285.07:14:23.04#ibcon#read 4, iclass 5, count 0 2006.285.07:14:23.04#ibcon#about to read 5, iclass 5, count 0 2006.285.07:14:23.04#ibcon#read 5, iclass 5, count 0 2006.285.07:14:23.04#ibcon#about to read 6, iclass 5, count 0 2006.285.07:14:23.04#ibcon#read 6, iclass 5, count 0 2006.285.07:14:23.04#ibcon#end of sib2, iclass 5, count 0 2006.285.07:14:23.04#ibcon#*after write, iclass 5, count 0 2006.285.07:14:23.04#ibcon#*before return 0, iclass 5, count 0 2006.285.07:14:23.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:14:23.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:14:23.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:14:23.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:14:23.04$vck44/va=7,4 2006.285.07:14:23.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.07:14:23.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.07:14:23.04#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:23.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:14:23.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:14:23.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:14:23.10#ibcon#enter wrdev, iclass 7, count 2 2006.285.07:14:23.10#ibcon#first serial, iclass 7, count 2 2006.285.07:14:23.10#ibcon#enter sib2, iclass 7, count 2 2006.285.07:14:23.10#ibcon#flushed, iclass 7, count 2 2006.285.07:14:23.10#ibcon#about to write, iclass 7, count 2 2006.285.07:14:23.10#ibcon#wrote, iclass 7, count 2 2006.285.07:14:23.10#ibcon#about to read 3, iclass 7, count 2 2006.285.07:14:23.12#ibcon#read 3, iclass 7, count 2 2006.285.07:14:23.12#ibcon#about to read 4, iclass 7, count 2 2006.285.07:14:23.12#ibcon#read 4, iclass 7, count 2 2006.285.07:14:23.12#ibcon#about to read 5, iclass 7, count 2 2006.285.07:14:23.12#ibcon#read 5, iclass 7, count 2 2006.285.07:14:23.12#ibcon#about to read 6, iclass 7, count 2 2006.285.07:14:23.12#ibcon#read 6, iclass 7, count 2 2006.285.07:14:23.12#ibcon#end of sib2, iclass 7, count 2 2006.285.07:14:23.12#ibcon#*mode == 0, iclass 7, count 2 2006.285.07:14:23.12#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.07:14:23.12#ibcon#[25=AT07-04\r\n] 2006.285.07:14:23.12#ibcon#*before write, iclass 7, count 2 2006.285.07:14:23.12#ibcon#enter sib2, iclass 7, count 2 2006.285.07:14:23.12#ibcon#flushed, iclass 7, count 2 2006.285.07:14:23.12#ibcon#about to write, iclass 7, count 2 2006.285.07:14:23.12#ibcon#wrote, iclass 7, count 2 2006.285.07:14:23.12#ibcon#about to read 3, iclass 7, count 2 2006.285.07:14:23.15#ibcon#read 3, iclass 7, count 2 2006.285.07:14:23.15#ibcon#about to read 4, iclass 7, count 2 2006.285.07:14:23.15#ibcon#read 4, iclass 7, count 2 2006.285.07:14:23.15#ibcon#about to read 5, iclass 7, count 2 2006.285.07:14:23.15#ibcon#read 5, iclass 7, count 2 2006.285.07:14:23.15#ibcon#about to read 6, iclass 7, count 2 2006.285.07:14:23.15#ibcon#read 6, iclass 7, count 2 2006.285.07:14:23.15#ibcon#end of sib2, iclass 7, count 2 2006.285.07:14:23.15#ibcon#*after write, iclass 7, count 2 2006.285.07:14:23.15#ibcon#*before return 0, iclass 7, count 2 2006.285.07:14:23.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:14:23.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:14:23.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.07:14:23.15#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:23.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:14:23.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:14:23.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:14:23.27#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:14:23.27#ibcon#first serial, iclass 7, count 0 2006.285.07:14:23.27#ibcon#enter sib2, iclass 7, count 0 2006.285.07:14:23.27#ibcon#flushed, iclass 7, count 0 2006.285.07:14:23.27#ibcon#about to write, iclass 7, count 0 2006.285.07:14:23.27#ibcon#wrote, iclass 7, count 0 2006.285.07:14:23.27#ibcon#about to read 3, iclass 7, count 0 2006.285.07:14:23.29#ibcon#read 3, iclass 7, count 0 2006.285.07:14:23.29#ibcon#about to read 4, iclass 7, count 0 2006.285.07:14:23.29#ibcon#read 4, iclass 7, count 0 2006.285.07:14:23.29#ibcon#about to read 5, iclass 7, count 0 2006.285.07:14:23.29#ibcon#read 5, iclass 7, count 0 2006.285.07:14:23.29#ibcon#about to read 6, iclass 7, count 0 2006.285.07:14:23.29#ibcon#read 6, iclass 7, count 0 2006.285.07:14:23.29#ibcon#end of sib2, iclass 7, count 0 2006.285.07:14:23.29#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:14:23.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:14:23.29#ibcon#[25=USB\r\n] 2006.285.07:14:23.29#ibcon#*before write, iclass 7, count 0 2006.285.07:14:23.29#ibcon#enter sib2, iclass 7, count 0 2006.285.07:14:23.29#ibcon#flushed, iclass 7, count 0 2006.285.07:14:23.29#ibcon#about to write, iclass 7, count 0 2006.285.07:14:23.29#ibcon#wrote, iclass 7, count 0 2006.285.07:14:23.29#ibcon#about to read 3, iclass 7, count 0 2006.285.07:14:23.32#ibcon#read 3, iclass 7, count 0 2006.285.07:14:23.32#ibcon#about to read 4, iclass 7, count 0 2006.285.07:14:23.32#ibcon#read 4, iclass 7, count 0 2006.285.07:14:23.32#ibcon#about to read 5, iclass 7, count 0 2006.285.07:14:23.32#ibcon#read 5, iclass 7, count 0 2006.285.07:14:23.32#ibcon#about to read 6, iclass 7, count 0 2006.285.07:14:23.32#ibcon#read 6, iclass 7, count 0 2006.285.07:14:23.32#ibcon#end of sib2, iclass 7, count 0 2006.285.07:14:23.32#ibcon#*after write, iclass 7, count 0 2006.285.07:14:23.32#ibcon#*before return 0, iclass 7, count 0 2006.285.07:14:23.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:14:23.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:14:23.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:14:23.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:14:23.32$vck44/valo=8,884.99 2006.285.07:14:23.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.07:14:23.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.07:14:23.32#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:23.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:14:23.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:14:23.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:14:23.32#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:14:23.32#ibcon#first serial, iclass 11, count 0 2006.285.07:14:23.32#ibcon#enter sib2, iclass 11, count 0 2006.285.07:14:23.32#ibcon#flushed, iclass 11, count 0 2006.285.07:14:23.32#ibcon#about to write, iclass 11, count 0 2006.285.07:14:23.32#ibcon#wrote, iclass 11, count 0 2006.285.07:14:23.32#ibcon#about to read 3, iclass 11, count 0 2006.285.07:14:23.34#ibcon#read 3, iclass 11, count 0 2006.285.07:14:23.34#ibcon#about to read 4, iclass 11, count 0 2006.285.07:14:23.34#ibcon#read 4, iclass 11, count 0 2006.285.07:14:23.34#ibcon#about to read 5, iclass 11, count 0 2006.285.07:14:23.34#ibcon#read 5, iclass 11, count 0 2006.285.07:14:23.34#ibcon#about to read 6, iclass 11, count 0 2006.285.07:14:23.34#ibcon#read 6, iclass 11, count 0 2006.285.07:14:23.34#ibcon#end of sib2, iclass 11, count 0 2006.285.07:14:23.34#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:14:23.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:14:23.34#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:14:23.34#ibcon#*before write, iclass 11, count 0 2006.285.07:14:23.34#ibcon#enter sib2, iclass 11, count 0 2006.285.07:14:23.34#ibcon#flushed, iclass 11, count 0 2006.285.07:14:23.34#ibcon#about to write, iclass 11, count 0 2006.285.07:14:23.34#ibcon#wrote, iclass 11, count 0 2006.285.07:14:23.34#ibcon#about to read 3, iclass 11, count 0 2006.285.07:14:23.38#ibcon#read 3, iclass 11, count 0 2006.285.07:14:23.38#ibcon#about to read 4, iclass 11, count 0 2006.285.07:14:23.38#ibcon#read 4, iclass 11, count 0 2006.285.07:14:23.38#ibcon#about to read 5, iclass 11, count 0 2006.285.07:14:23.38#ibcon#read 5, iclass 11, count 0 2006.285.07:14:23.38#ibcon#about to read 6, iclass 11, count 0 2006.285.07:14:23.38#ibcon#read 6, iclass 11, count 0 2006.285.07:14:23.38#ibcon#end of sib2, iclass 11, count 0 2006.285.07:14:23.38#ibcon#*after write, iclass 11, count 0 2006.285.07:14:23.38#ibcon#*before return 0, iclass 11, count 0 2006.285.07:14:23.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:14:23.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:14:23.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:14:23.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:14:23.38$vck44/va=8,3 2006.285.07:14:23.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.07:14:23.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.07:14:23.38#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:23.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:14:23.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:14:23.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:14:23.44#ibcon#enter wrdev, iclass 13, count 2 2006.285.07:14:23.44#ibcon#first serial, iclass 13, count 2 2006.285.07:14:23.44#ibcon#enter sib2, iclass 13, count 2 2006.285.07:14:23.44#ibcon#flushed, iclass 13, count 2 2006.285.07:14:23.44#ibcon#about to write, iclass 13, count 2 2006.285.07:14:23.44#ibcon#wrote, iclass 13, count 2 2006.285.07:14:23.44#ibcon#about to read 3, iclass 13, count 2 2006.285.07:14:23.46#ibcon#read 3, iclass 13, count 2 2006.285.07:14:23.46#ibcon#about to read 4, iclass 13, count 2 2006.285.07:14:23.46#ibcon#read 4, iclass 13, count 2 2006.285.07:14:23.46#ibcon#about to read 5, iclass 13, count 2 2006.285.07:14:23.46#ibcon#read 5, iclass 13, count 2 2006.285.07:14:23.46#ibcon#about to read 6, iclass 13, count 2 2006.285.07:14:23.46#ibcon#read 6, iclass 13, count 2 2006.285.07:14:23.46#ibcon#end of sib2, iclass 13, count 2 2006.285.07:14:23.46#ibcon#*mode == 0, iclass 13, count 2 2006.285.07:14:23.46#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.07:14:23.46#ibcon#[25=AT08-03\r\n] 2006.285.07:14:23.46#ibcon#*before write, iclass 13, count 2 2006.285.07:14:23.46#ibcon#enter sib2, iclass 13, count 2 2006.285.07:14:23.46#ibcon#flushed, iclass 13, count 2 2006.285.07:14:23.46#ibcon#about to write, iclass 13, count 2 2006.285.07:14:23.46#ibcon#wrote, iclass 13, count 2 2006.285.07:14:23.46#ibcon#about to read 3, iclass 13, count 2 2006.285.07:14:23.49#ibcon#read 3, iclass 13, count 2 2006.285.07:14:23.49#ibcon#about to read 4, iclass 13, count 2 2006.285.07:14:23.49#ibcon#read 4, iclass 13, count 2 2006.285.07:14:23.49#ibcon#about to read 5, iclass 13, count 2 2006.285.07:14:23.49#ibcon#read 5, iclass 13, count 2 2006.285.07:14:23.49#ibcon#about to read 6, iclass 13, count 2 2006.285.07:14:23.49#ibcon#read 6, iclass 13, count 2 2006.285.07:14:23.49#ibcon#end of sib2, iclass 13, count 2 2006.285.07:14:23.49#ibcon#*after write, iclass 13, count 2 2006.285.07:14:23.49#ibcon#*before return 0, iclass 13, count 2 2006.285.07:14:23.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:14:23.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:14:23.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.07:14:23.49#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:23.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:14:23.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:14:23.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:14:23.61#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:14:23.61#ibcon#first serial, iclass 13, count 0 2006.285.07:14:23.61#ibcon#enter sib2, iclass 13, count 0 2006.285.07:14:23.61#ibcon#flushed, iclass 13, count 0 2006.285.07:14:23.61#ibcon#about to write, iclass 13, count 0 2006.285.07:14:23.61#ibcon#wrote, iclass 13, count 0 2006.285.07:14:23.61#ibcon#about to read 3, iclass 13, count 0 2006.285.07:14:23.63#ibcon#read 3, iclass 13, count 0 2006.285.07:14:23.63#ibcon#about to read 4, iclass 13, count 0 2006.285.07:14:23.63#ibcon#read 4, iclass 13, count 0 2006.285.07:14:23.63#ibcon#about to read 5, iclass 13, count 0 2006.285.07:14:23.63#ibcon#read 5, iclass 13, count 0 2006.285.07:14:23.63#ibcon#about to read 6, iclass 13, count 0 2006.285.07:14:23.63#ibcon#read 6, iclass 13, count 0 2006.285.07:14:23.63#ibcon#end of sib2, iclass 13, count 0 2006.285.07:14:23.63#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:14:23.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:14:23.63#ibcon#[25=USB\r\n] 2006.285.07:14:23.63#ibcon#*before write, iclass 13, count 0 2006.285.07:14:23.63#ibcon#enter sib2, iclass 13, count 0 2006.285.07:14:23.63#ibcon#flushed, iclass 13, count 0 2006.285.07:14:23.63#ibcon#about to write, iclass 13, count 0 2006.285.07:14:23.63#ibcon#wrote, iclass 13, count 0 2006.285.07:14:23.63#ibcon#about to read 3, iclass 13, count 0 2006.285.07:14:23.66#ibcon#read 3, iclass 13, count 0 2006.285.07:14:23.66#ibcon#about to read 4, iclass 13, count 0 2006.285.07:14:23.66#ibcon#read 4, iclass 13, count 0 2006.285.07:14:23.66#ibcon#about to read 5, iclass 13, count 0 2006.285.07:14:23.66#ibcon#read 5, iclass 13, count 0 2006.285.07:14:23.66#ibcon#about to read 6, iclass 13, count 0 2006.285.07:14:23.66#ibcon#read 6, iclass 13, count 0 2006.285.07:14:23.66#ibcon#end of sib2, iclass 13, count 0 2006.285.07:14:23.66#ibcon#*after write, iclass 13, count 0 2006.285.07:14:23.66#ibcon#*before return 0, iclass 13, count 0 2006.285.07:14:23.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:14:23.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:14:23.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:14:23.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:14:23.66$vck44/vblo=1,629.99 2006.285.07:14:23.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.07:14:23.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.07:14:23.66#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:23.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:14:23.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:14:23.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:14:23.66#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:14:23.66#ibcon#first serial, iclass 15, count 0 2006.285.07:14:23.66#ibcon#enter sib2, iclass 15, count 0 2006.285.07:14:23.66#ibcon#flushed, iclass 15, count 0 2006.285.07:14:23.66#ibcon#about to write, iclass 15, count 0 2006.285.07:14:23.66#ibcon#wrote, iclass 15, count 0 2006.285.07:14:23.66#ibcon#about to read 3, iclass 15, count 0 2006.285.07:14:23.68#ibcon#read 3, iclass 15, count 0 2006.285.07:14:23.68#ibcon#about to read 4, iclass 15, count 0 2006.285.07:14:23.68#ibcon#read 4, iclass 15, count 0 2006.285.07:14:23.68#ibcon#about to read 5, iclass 15, count 0 2006.285.07:14:23.68#ibcon#read 5, iclass 15, count 0 2006.285.07:14:23.68#ibcon#about to read 6, iclass 15, count 0 2006.285.07:14:23.68#ibcon#read 6, iclass 15, count 0 2006.285.07:14:23.68#ibcon#end of sib2, iclass 15, count 0 2006.285.07:14:23.68#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:14:23.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:14:23.68#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:14:23.68#ibcon#*before write, iclass 15, count 0 2006.285.07:14:23.68#ibcon#enter sib2, iclass 15, count 0 2006.285.07:14:23.68#ibcon#flushed, iclass 15, count 0 2006.285.07:14:23.68#ibcon#about to write, iclass 15, count 0 2006.285.07:14:23.68#ibcon#wrote, iclass 15, count 0 2006.285.07:14:23.68#ibcon#about to read 3, iclass 15, count 0 2006.285.07:14:23.72#ibcon#read 3, iclass 15, count 0 2006.285.07:14:23.72#ibcon#about to read 4, iclass 15, count 0 2006.285.07:14:23.72#ibcon#read 4, iclass 15, count 0 2006.285.07:14:23.72#ibcon#about to read 5, iclass 15, count 0 2006.285.07:14:23.72#ibcon#read 5, iclass 15, count 0 2006.285.07:14:23.72#ibcon#about to read 6, iclass 15, count 0 2006.285.07:14:23.72#ibcon#read 6, iclass 15, count 0 2006.285.07:14:23.72#ibcon#end of sib2, iclass 15, count 0 2006.285.07:14:23.72#ibcon#*after write, iclass 15, count 0 2006.285.07:14:23.72#ibcon#*before return 0, iclass 15, count 0 2006.285.07:14:23.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:14:23.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:14:23.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:14:23.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:14:23.72$vck44/vb=1,4 2006.285.07:14:23.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.07:14:23.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.07:14:23.72#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:23.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:14:23.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:14:23.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:14:23.72#ibcon#enter wrdev, iclass 17, count 2 2006.285.07:14:23.72#ibcon#first serial, iclass 17, count 2 2006.285.07:14:23.72#ibcon#enter sib2, iclass 17, count 2 2006.285.07:14:23.72#ibcon#flushed, iclass 17, count 2 2006.285.07:14:23.72#ibcon#about to write, iclass 17, count 2 2006.285.07:14:23.72#ibcon#wrote, iclass 17, count 2 2006.285.07:14:23.72#ibcon#about to read 3, iclass 17, count 2 2006.285.07:14:23.74#ibcon#read 3, iclass 17, count 2 2006.285.07:14:23.74#ibcon#about to read 4, iclass 17, count 2 2006.285.07:14:23.74#ibcon#read 4, iclass 17, count 2 2006.285.07:14:23.74#ibcon#about to read 5, iclass 17, count 2 2006.285.07:14:23.74#ibcon#read 5, iclass 17, count 2 2006.285.07:14:23.74#ibcon#about to read 6, iclass 17, count 2 2006.285.07:14:23.74#ibcon#read 6, iclass 17, count 2 2006.285.07:14:23.74#ibcon#end of sib2, iclass 17, count 2 2006.285.07:14:23.74#ibcon#*mode == 0, iclass 17, count 2 2006.285.07:14:23.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.07:14:23.74#ibcon#[27=AT01-04\r\n] 2006.285.07:14:23.74#ibcon#*before write, iclass 17, count 2 2006.285.07:14:23.74#ibcon#enter sib2, iclass 17, count 2 2006.285.07:14:23.74#ibcon#flushed, iclass 17, count 2 2006.285.07:14:23.74#ibcon#about to write, iclass 17, count 2 2006.285.07:14:23.74#ibcon#wrote, iclass 17, count 2 2006.285.07:14:23.74#ibcon#about to read 3, iclass 17, count 2 2006.285.07:14:23.77#ibcon#read 3, iclass 17, count 2 2006.285.07:14:23.77#ibcon#about to read 4, iclass 17, count 2 2006.285.07:14:23.77#ibcon#read 4, iclass 17, count 2 2006.285.07:14:23.77#ibcon#about to read 5, iclass 17, count 2 2006.285.07:14:23.77#ibcon#read 5, iclass 17, count 2 2006.285.07:14:23.77#ibcon#about to read 6, iclass 17, count 2 2006.285.07:14:23.77#ibcon#read 6, iclass 17, count 2 2006.285.07:14:23.77#ibcon#end of sib2, iclass 17, count 2 2006.285.07:14:23.77#ibcon#*after write, iclass 17, count 2 2006.285.07:14:23.77#ibcon#*before return 0, iclass 17, count 2 2006.285.07:14:23.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:14:23.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:14:23.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.07:14:23.77#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:23.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:14:23.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:14:23.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:14:23.89#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:14:23.89#ibcon#first serial, iclass 17, count 0 2006.285.07:14:23.89#ibcon#enter sib2, iclass 17, count 0 2006.285.07:14:23.89#ibcon#flushed, iclass 17, count 0 2006.285.07:14:23.89#ibcon#about to write, iclass 17, count 0 2006.285.07:14:23.89#ibcon#wrote, iclass 17, count 0 2006.285.07:14:23.89#ibcon#about to read 3, iclass 17, count 0 2006.285.07:14:23.91#ibcon#read 3, iclass 17, count 0 2006.285.07:14:23.91#ibcon#about to read 4, iclass 17, count 0 2006.285.07:14:23.91#ibcon#read 4, iclass 17, count 0 2006.285.07:14:23.91#ibcon#about to read 5, iclass 17, count 0 2006.285.07:14:23.91#ibcon#read 5, iclass 17, count 0 2006.285.07:14:23.91#ibcon#about to read 6, iclass 17, count 0 2006.285.07:14:23.91#ibcon#read 6, iclass 17, count 0 2006.285.07:14:23.91#ibcon#end of sib2, iclass 17, count 0 2006.285.07:14:23.91#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:14:23.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:14:23.91#ibcon#[27=USB\r\n] 2006.285.07:14:23.91#ibcon#*before write, iclass 17, count 0 2006.285.07:14:23.91#ibcon#enter sib2, iclass 17, count 0 2006.285.07:14:23.91#ibcon#flushed, iclass 17, count 0 2006.285.07:14:23.91#ibcon#about to write, iclass 17, count 0 2006.285.07:14:23.91#ibcon#wrote, iclass 17, count 0 2006.285.07:14:23.91#ibcon#about to read 3, iclass 17, count 0 2006.285.07:14:23.93#abcon#<5=/05 3.7 6.2 24.05 751014.2\r\n> 2006.285.07:14:23.94#ibcon#read 3, iclass 17, count 0 2006.285.07:14:23.94#ibcon#about to read 4, iclass 17, count 0 2006.285.07:14:23.94#ibcon#read 4, iclass 17, count 0 2006.285.07:14:23.94#ibcon#about to read 5, iclass 17, count 0 2006.285.07:14:23.94#ibcon#read 5, iclass 17, count 0 2006.285.07:14:23.94#ibcon#about to read 6, iclass 17, count 0 2006.285.07:14:23.94#ibcon#read 6, iclass 17, count 0 2006.285.07:14:23.94#ibcon#end of sib2, iclass 17, count 0 2006.285.07:14:23.94#ibcon#*after write, iclass 17, count 0 2006.285.07:14:23.94#ibcon#*before return 0, iclass 17, count 0 2006.285.07:14:23.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:14:23.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:14:23.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:14:23.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:14:23.94$vck44/vblo=2,634.99 2006.285.07:14:23.94#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.07:14:23.94#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.07:14:23.94#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:23.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:14:23.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:14:23.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:14:23.94#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:14:23.94#ibcon#first serial, iclass 22, count 0 2006.285.07:14:23.94#ibcon#enter sib2, iclass 22, count 0 2006.285.07:14:23.94#ibcon#flushed, iclass 22, count 0 2006.285.07:14:23.94#ibcon#about to write, iclass 22, count 0 2006.285.07:14:23.94#ibcon#wrote, iclass 22, count 0 2006.285.07:14:23.94#ibcon#about to read 3, iclass 22, count 0 2006.285.07:14:23.95#abcon#{5=INTERFACE CLEAR} 2006.285.07:14:23.96#ibcon#read 3, iclass 22, count 0 2006.285.07:14:23.96#ibcon#about to read 4, iclass 22, count 0 2006.285.07:14:23.96#ibcon#read 4, iclass 22, count 0 2006.285.07:14:23.96#ibcon#about to read 5, iclass 22, count 0 2006.285.07:14:23.96#ibcon#read 5, iclass 22, count 0 2006.285.07:14:23.96#ibcon#about to read 6, iclass 22, count 0 2006.285.07:14:23.96#ibcon#read 6, iclass 22, count 0 2006.285.07:14:23.96#ibcon#end of sib2, iclass 22, count 0 2006.285.07:14:23.96#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:14:23.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:14:23.96#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:14:23.96#ibcon#*before write, iclass 22, count 0 2006.285.07:14:23.96#ibcon#enter sib2, iclass 22, count 0 2006.285.07:14:23.96#ibcon#flushed, iclass 22, count 0 2006.285.07:14:23.96#ibcon#about to write, iclass 22, count 0 2006.285.07:14:23.96#ibcon#wrote, iclass 22, count 0 2006.285.07:14:23.96#ibcon#about to read 3, iclass 22, count 0 2006.285.07:14:24.00#ibcon#read 3, iclass 22, count 0 2006.285.07:14:24.00#ibcon#about to read 4, iclass 22, count 0 2006.285.07:14:24.00#ibcon#read 4, iclass 22, count 0 2006.285.07:14:24.00#ibcon#about to read 5, iclass 22, count 0 2006.285.07:14:24.00#ibcon#read 5, iclass 22, count 0 2006.285.07:14:24.00#ibcon#about to read 6, iclass 22, count 0 2006.285.07:14:24.00#ibcon#read 6, iclass 22, count 0 2006.285.07:14:24.00#ibcon#end of sib2, iclass 22, count 0 2006.285.07:14:24.00#ibcon#*after write, iclass 22, count 0 2006.285.07:14:24.00#ibcon#*before return 0, iclass 22, count 0 2006.285.07:14:24.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:14:24.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:14:24.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:14:24.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:14:24.00$vck44/vb=2,5 2006.285.07:14:24.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.07:14:24.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.07:14:24.00#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:24.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:14:24.01#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:14:24.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:14:24.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:14:24.06#ibcon#enter wrdev, iclass 25, count 2 2006.285.07:14:24.06#ibcon#first serial, iclass 25, count 2 2006.285.07:14:24.06#ibcon#enter sib2, iclass 25, count 2 2006.285.07:14:24.06#ibcon#flushed, iclass 25, count 2 2006.285.07:14:24.06#ibcon#about to write, iclass 25, count 2 2006.285.07:14:24.06#ibcon#wrote, iclass 25, count 2 2006.285.07:14:24.06#ibcon#about to read 3, iclass 25, count 2 2006.285.07:14:24.08#ibcon#read 3, iclass 25, count 2 2006.285.07:14:24.08#ibcon#about to read 4, iclass 25, count 2 2006.285.07:14:24.08#ibcon#read 4, iclass 25, count 2 2006.285.07:14:24.08#ibcon#about to read 5, iclass 25, count 2 2006.285.07:14:24.08#ibcon#read 5, iclass 25, count 2 2006.285.07:14:24.08#ibcon#about to read 6, iclass 25, count 2 2006.285.07:14:24.08#ibcon#read 6, iclass 25, count 2 2006.285.07:14:24.08#ibcon#end of sib2, iclass 25, count 2 2006.285.07:14:24.08#ibcon#*mode == 0, iclass 25, count 2 2006.285.07:14:24.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.07:14:24.08#ibcon#[27=AT02-05\r\n] 2006.285.07:14:24.08#ibcon#*before write, iclass 25, count 2 2006.285.07:14:24.08#ibcon#enter sib2, iclass 25, count 2 2006.285.07:14:24.08#ibcon#flushed, iclass 25, count 2 2006.285.07:14:24.08#ibcon#about to write, iclass 25, count 2 2006.285.07:14:24.08#ibcon#wrote, iclass 25, count 2 2006.285.07:14:24.08#ibcon#about to read 3, iclass 25, count 2 2006.285.07:14:24.11#ibcon#read 3, iclass 25, count 2 2006.285.07:14:24.11#ibcon#about to read 4, iclass 25, count 2 2006.285.07:14:24.11#ibcon#read 4, iclass 25, count 2 2006.285.07:14:24.11#ibcon#about to read 5, iclass 25, count 2 2006.285.07:14:24.11#ibcon#read 5, iclass 25, count 2 2006.285.07:14:24.11#ibcon#about to read 6, iclass 25, count 2 2006.285.07:14:24.11#ibcon#read 6, iclass 25, count 2 2006.285.07:14:24.11#ibcon#end of sib2, iclass 25, count 2 2006.285.07:14:24.11#ibcon#*after write, iclass 25, count 2 2006.285.07:14:24.11#ibcon#*before return 0, iclass 25, count 2 2006.285.07:14:24.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:14:24.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:14:24.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.07:14:24.11#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:24.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:14:24.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:14:24.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:14:24.23#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:14:24.23#ibcon#first serial, iclass 25, count 0 2006.285.07:14:24.23#ibcon#enter sib2, iclass 25, count 0 2006.285.07:14:24.23#ibcon#flushed, iclass 25, count 0 2006.285.07:14:24.23#ibcon#about to write, iclass 25, count 0 2006.285.07:14:24.23#ibcon#wrote, iclass 25, count 0 2006.285.07:14:24.23#ibcon#about to read 3, iclass 25, count 0 2006.285.07:14:24.25#ibcon#read 3, iclass 25, count 0 2006.285.07:14:24.25#ibcon#about to read 4, iclass 25, count 0 2006.285.07:14:24.25#ibcon#read 4, iclass 25, count 0 2006.285.07:14:24.25#ibcon#about to read 5, iclass 25, count 0 2006.285.07:14:24.25#ibcon#read 5, iclass 25, count 0 2006.285.07:14:24.25#ibcon#about to read 6, iclass 25, count 0 2006.285.07:14:24.25#ibcon#read 6, iclass 25, count 0 2006.285.07:14:24.25#ibcon#end of sib2, iclass 25, count 0 2006.285.07:14:24.25#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:14:24.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:14:24.25#ibcon#[27=USB\r\n] 2006.285.07:14:24.25#ibcon#*before write, iclass 25, count 0 2006.285.07:14:24.25#ibcon#enter sib2, iclass 25, count 0 2006.285.07:14:24.25#ibcon#flushed, iclass 25, count 0 2006.285.07:14:24.25#ibcon#about to write, iclass 25, count 0 2006.285.07:14:24.25#ibcon#wrote, iclass 25, count 0 2006.285.07:14:24.25#ibcon#about to read 3, iclass 25, count 0 2006.285.07:14:24.28#ibcon#read 3, iclass 25, count 0 2006.285.07:14:24.28#ibcon#about to read 4, iclass 25, count 0 2006.285.07:14:24.28#ibcon#read 4, iclass 25, count 0 2006.285.07:14:24.28#ibcon#about to read 5, iclass 25, count 0 2006.285.07:14:24.28#ibcon#read 5, iclass 25, count 0 2006.285.07:14:24.28#ibcon#about to read 6, iclass 25, count 0 2006.285.07:14:24.28#ibcon#read 6, iclass 25, count 0 2006.285.07:14:24.28#ibcon#end of sib2, iclass 25, count 0 2006.285.07:14:24.28#ibcon#*after write, iclass 25, count 0 2006.285.07:14:24.28#ibcon#*before return 0, iclass 25, count 0 2006.285.07:14:24.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:14:24.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:14:24.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:14:24.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:14:24.28$vck44/vblo=3,649.99 2006.285.07:14:24.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.07:14:24.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.07:14:24.28#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:24.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:14:24.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:14:24.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:14:24.28#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:14:24.28#ibcon#first serial, iclass 27, count 0 2006.285.07:14:24.28#ibcon#enter sib2, iclass 27, count 0 2006.285.07:14:24.28#ibcon#flushed, iclass 27, count 0 2006.285.07:14:24.28#ibcon#about to write, iclass 27, count 0 2006.285.07:14:24.28#ibcon#wrote, iclass 27, count 0 2006.285.07:14:24.28#ibcon#about to read 3, iclass 27, count 0 2006.285.07:14:24.30#ibcon#read 3, iclass 27, count 0 2006.285.07:14:24.30#ibcon#about to read 4, iclass 27, count 0 2006.285.07:14:24.30#ibcon#read 4, iclass 27, count 0 2006.285.07:14:24.30#ibcon#about to read 5, iclass 27, count 0 2006.285.07:14:24.30#ibcon#read 5, iclass 27, count 0 2006.285.07:14:24.30#ibcon#about to read 6, iclass 27, count 0 2006.285.07:14:24.30#ibcon#read 6, iclass 27, count 0 2006.285.07:14:24.30#ibcon#end of sib2, iclass 27, count 0 2006.285.07:14:24.30#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:14:24.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:14:24.30#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:14:24.30#ibcon#*before write, iclass 27, count 0 2006.285.07:14:24.30#ibcon#enter sib2, iclass 27, count 0 2006.285.07:14:24.30#ibcon#flushed, iclass 27, count 0 2006.285.07:14:24.30#ibcon#about to write, iclass 27, count 0 2006.285.07:14:24.30#ibcon#wrote, iclass 27, count 0 2006.285.07:14:24.30#ibcon#about to read 3, iclass 27, count 0 2006.285.07:14:24.34#ibcon#read 3, iclass 27, count 0 2006.285.07:14:24.34#ibcon#about to read 4, iclass 27, count 0 2006.285.07:14:24.34#ibcon#read 4, iclass 27, count 0 2006.285.07:14:24.34#ibcon#about to read 5, iclass 27, count 0 2006.285.07:14:24.34#ibcon#read 5, iclass 27, count 0 2006.285.07:14:24.34#ibcon#about to read 6, iclass 27, count 0 2006.285.07:14:24.34#ibcon#read 6, iclass 27, count 0 2006.285.07:14:24.34#ibcon#end of sib2, iclass 27, count 0 2006.285.07:14:24.34#ibcon#*after write, iclass 27, count 0 2006.285.07:14:24.34#ibcon#*before return 0, iclass 27, count 0 2006.285.07:14:24.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:14:24.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:14:24.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:14:24.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:14:24.34$vck44/vb=3,4 2006.285.07:14:24.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.07:14:24.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.07:14:24.34#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:24.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:14:24.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:14:24.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:14:24.40#ibcon#enter wrdev, iclass 29, count 2 2006.285.07:14:24.40#ibcon#first serial, iclass 29, count 2 2006.285.07:14:24.40#ibcon#enter sib2, iclass 29, count 2 2006.285.07:14:24.40#ibcon#flushed, iclass 29, count 2 2006.285.07:14:24.40#ibcon#about to write, iclass 29, count 2 2006.285.07:14:24.40#ibcon#wrote, iclass 29, count 2 2006.285.07:14:24.40#ibcon#about to read 3, iclass 29, count 2 2006.285.07:14:24.42#ibcon#read 3, iclass 29, count 2 2006.285.07:14:24.42#ibcon#about to read 4, iclass 29, count 2 2006.285.07:14:24.42#ibcon#read 4, iclass 29, count 2 2006.285.07:14:24.42#ibcon#about to read 5, iclass 29, count 2 2006.285.07:14:24.42#ibcon#read 5, iclass 29, count 2 2006.285.07:14:24.42#ibcon#about to read 6, iclass 29, count 2 2006.285.07:14:24.42#ibcon#read 6, iclass 29, count 2 2006.285.07:14:24.42#ibcon#end of sib2, iclass 29, count 2 2006.285.07:14:24.42#ibcon#*mode == 0, iclass 29, count 2 2006.285.07:14:24.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.07:14:24.42#ibcon#[27=AT03-04\r\n] 2006.285.07:14:24.42#ibcon#*before write, iclass 29, count 2 2006.285.07:14:24.42#ibcon#enter sib2, iclass 29, count 2 2006.285.07:14:24.42#ibcon#flushed, iclass 29, count 2 2006.285.07:14:24.42#ibcon#about to write, iclass 29, count 2 2006.285.07:14:24.42#ibcon#wrote, iclass 29, count 2 2006.285.07:14:24.42#ibcon#about to read 3, iclass 29, count 2 2006.285.07:14:24.45#ibcon#read 3, iclass 29, count 2 2006.285.07:14:24.45#ibcon#about to read 4, iclass 29, count 2 2006.285.07:14:24.45#ibcon#read 4, iclass 29, count 2 2006.285.07:14:24.45#ibcon#about to read 5, iclass 29, count 2 2006.285.07:14:24.45#ibcon#read 5, iclass 29, count 2 2006.285.07:14:24.45#ibcon#about to read 6, iclass 29, count 2 2006.285.07:14:24.45#ibcon#read 6, iclass 29, count 2 2006.285.07:14:24.45#ibcon#end of sib2, iclass 29, count 2 2006.285.07:14:24.45#ibcon#*after write, iclass 29, count 2 2006.285.07:14:24.45#ibcon#*before return 0, iclass 29, count 2 2006.285.07:14:24.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:14:24.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:14:24.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.07:14:24.45#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:24.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:14:24.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:14:24.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:14:24.57#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:14:24.57#ibcon#first serial, iclass 29, count 0 2006.285.07:14:24.57#ibcon#enter sib2, iclass 29, count 0 2006.285.07:14:24.57#ibcon#flushed, iclass 29, count 0 2006.285.07:14:24.57#ibcon#about to write, iclass 29, count 0 2006.285.07:14:24.57#ibcon#wrote, iclass 29, count 0 2006.285.07:14:24.57#ibcon#about to read 3, iclass 29, count 0 2006.285.07:14:24.59#ibcon#read 3, iclass 29, count 0 2006.285.07:14:24.59#ibcon#about to read 4, iclass 29, count 0 2006.285.07:14:24.59#ibcon#read 4, iclass 29, count 0 2006.285.07:14:24.59#ibcon#about to read 5, iclass 29, count 0 2006.285.07:14:24.59#ibcon#read 5, iclass 29, count 0 2006.285.07:14:24.59#ibcon#about to read 6, iclass 29, count 0 2006.285.07:14:24.59#ibcon#read 6, iclass 29, count 0 2006.285.07:14:24.59#ibcon#end of sib2, iclass 29, count 0 2006.285.07:14:24.59#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:14:24.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:14:24.59#ibcon#[27=USB\r\n] 2006.285.07:14:24.59#ibcon#*before write, iclass 29, count 0 2006.285.07:14:24.59#ibcon#enter sib2, iclass 29, count 0 2006.285.07:14:24.59#ibcon#flushed, iclass 29, count 0 2006.285.07:14:24.59#ibcon#about to write, iclass 29, count 0 2006.285.07:14:24.59#ibcon#wrote, iclass 29, count 0 2006.285.07:14:24.59#ibcon#about to read 3, iclass 29, count 0 2006.285.07:14:24.62#ibcon#read 3, iclass 29, count 0 2006.285.07:14:24.62#ibcon#about to read 4, iclass 29, count 0 2006.285.07:14:24.62#ibcon#read 4, iclass 29, count 0 2006.285.07:14:24.62#ibcon#about to read 5, iclass 29, count 0 2006.285.07:14:24.62#ibcon#read 5, iclass 29, count 0 2006.285.07:14:24.62#ibcon#about to read 6, iclass 29, count 0 2006.285.07:14:24.62#ibcon#read 6, iclass 29, count 0 2006.285.07:14:24.62#ibcon#end of sib2, iclass 29, count 0 2006.285.07:14:24.62#ibcon#*after write, iclass 29, count 0 2006.285.07:14:24.62#ibcon#*before return 0, iclass 29, count 0 2006.285.07:14:24.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:14:24.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:14:24.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:14:24.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:14:24.62$vck44/vblo=4,679.99 2006.285.07:14:24.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.07:14:24.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.07:14:24.62#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:24.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:14:24.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:14:24.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:14:24.62#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:14:24.62#ibcon#first serial, iclass 31, count 0 2006.285.07:14:24.62#ibcon#enter sib2, iclass 31, count 0 2006.285.07:14:24.62#ibcon#flushed, iclass 31, count 0 2006.285.07:14:24.62#ibcon#about to write, iclass 31, count 0 2006.285.07:14:24.62#ibcon#wrote, iclass 31, count 0 2006.285.07:14:24.62#ibcon#about to read 3, iclass 31, count 0 2006.285.07:14:24.64#ibcon#read 3, iclass 31, count 0 2006.285.07:14:24.64#ibcon#about to read 4, iclass 31, count 0 2006.285.07:14:24.64#ibcon#read 4, iclass 31, count 0 2006.285.07:14:24.64#ibcon#about to read 5, iclass 31, count 0 2006.285.07:14:24.64#ibcon#read 5, iclass 31, count 0 2006.285.07:14:24.64#ibcon#about to read 6, iclass 31, count 0 2006.285.07:14:24.64#ibcon#read 6, iclass 31, count 0 2006.285.07:14:24.64#ibcon#end of sib2, iclass 31, count 0 2006.285.07:14:24.64#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:14:24.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:14:24.64#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:14:24.64#ibcon#*before write, iclass 31, count 0 2006.285.07:14:24.64#ibcon#enter sib2, iclass 31, count 0 2006.285.07:14:24.64#ibcon#flushed, iclass 31, count 0 2006.285.07:14:24.64#ibcon#about to write, iclass 31, count 0 2006.285.07:14:24.64#ibcon#wrote, iclass 31, count 0 2006.285.07:14:24.64#ibcon#about to read 3, iclass 31, count 0 2006.285.07:14:24.68#ibcon#read 3, iclass 31, count 0 2006.285.07:14:24.68#ibcon#about to read 4, iclass 31, count 0 2006.285.07:14:24.68#ibcon#read 4, iclass 31, count 0 2006.285.07:14:24.68#ibcon#about to read 5, iclass 31, count 0 2006.285.07:14:24.68#ibcon#read 5, iclass 31, count 0 2006.285.07:14:24.68#ibcon#about to read 6, iclass 31, count 0 2006.285.07:14:24.68#ibcon#read 6, iclass 31, count 0 2006.285.07:14:24.68#ibcon#end of sib2, iclass 31, count 0 2006.285.07:14:24.68#ibcon#*after write, iclass 31, count 0 2006.285.07:14:24.68#ibcon#*before return 0, iclass 31, count 0 2006.285.07:14:24.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:14:24.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:14:24.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:14:24.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:14:24.68$vck44/vb=4,5 2006.285.07:14:24.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.07:14:24.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.07:14:24.68#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:24.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:14:24.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:14:24.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:14:24.74#ibcon#enter wrdev, iclass 33, count 2 2006.285.07:14:24.74#ibcon#first serial, iclass 33, count 2 2006.285.07:14:24.74#ibcon#enter sib2, iclass 33, count 2 2006.285.07:14:24.74#ibcon#flushed, iclass 33, count 2 2006.285.07:14:24.74#ibcon#about to write, iclass 33, count 2 2006.285.07:14:24.74#ibcon#wrote, iclass 33, count 2 2006.285.07:14:24.74#ibcon#about to read 3, iclass 33, count 2 2006.285.07:14:24.76#ibcon#read 3, iclass 33, count 2 2006.285.07:14:24.76#ibcon#about to read 4, iclass 33, count 2 2006.285.07:14:24.76#ibcon#read 4, iclass 33, count 2 2006.285.07:14:24.76#ibcon#about to read 5, iclass 33, count 2 2006.285.07:14:24.76#ibcon#read 5, iclass 33, count 2 2006.285.07:14:24.76#ibcon#about to read 6, iclass 33, count 2 2006.285.07:14:24.76#ibcon#read 6, iclass 33, count 2 2006.285.07:14:24.76#ibcon#end of sib2, iclass 33, count 2 2006.285.07:14:24.76#ibcon#*mode == 0, iclass 33, count 2 2006.285.07:14:24.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.07:14:24.76#ibcon#[27=AT04-05\r\n] 2006.285.07:14:24.76#ibcon#*before write, iclass 33, count 2 2006.285.07:14:24.76#ibcon#enter sib2, iclass 33, count 2 2006.285.07:14:24.76#ibcon#flushed, iclass 33, count 2 2006.285.07:14:24.76#ibcon#about to write, iclass 33, count 2 2006.285.07:14:24.76#ibcon#wrote, iclass 33, count 2 2006.285.07:14:24.76#ibcon#about to read 3, iclass 33, count 2 2006.285.07:14:24.79#ibcon#read 3, iclass 33, count 2 2006.285.07:14:24.79#ibcon#about to read 4, iclass 33, count 2 2006.285.07:14:24.79#ibcon#read 4, iclass 33, count 2 2006.285.07:14:24.79#ibcon#about to read 5, iclass 33, count 2 2006.285.07:14:24.79#ibcon#read 5, iclass 33, count 2 2006.285.07:14:24.79#ibcon#about to read 6, iclass 33, count 2 2006.285.07:14:24.79#ibcon#read 6, iclass 33, count 2 2006.285.07:14:24.79#ibcon#end of sib2, iclass 33, count 2 2006.285.07:14:24.79#ibcon#*after write, iclass 33, count 2 2006.285.07:14:24.79#ibcon#*before return 0, iclass 33, count 2 2006.285.07:14:24.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:14:24.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:14:24.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.07:14:24.79#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:24.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:14:24.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:14:24.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:14:24.91#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:14:24.91#ibcon#first serial, iclass 33, count 0 2006.285.07:14:24.91#ibcon#enter sib2, iclass 33, count 0 2006.285.07:14:24.91#ibcon#flushed, iclass 33, count 0 2006.285.07:14:24.91#ibcon#about to write, iclass 33, count 0 2006.285.07:14:24.91#ibcon#wrote, iclass 33, count 0 2006.285.07:14:24.91#ibcon#about to read 3, iclass 33, count 0 2006.285.07:14:24.93#ibcon#read 3, iclass 33, count 0 2006.285.07:14:24.93#ibcon#about to read 4, iclass 33, count 0 2006.285.07:14:24.93#ibcon#read 4, iclass 33, count 0 2006.285.07:14:24.93#ibcon#about to read 5, iclass 33, count 0 2006.285.07:14:24.93#ibcon#read 5, iclass 33, count 0 2006.285.07:14:24.93#ibcon#about to read 6, iclass 33, count 0 2006.285.07:14:24.93#ibcon#read 6, iclass 33, count 0 2006.285.07:14:24.93#ibcon#end of sib2, iclass 33, count 0 2006.285.07:14:24.93#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:14:24.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:14:24.93#ibcon#[27=USB\r\n] 2006.285.07:14:24.93#ibcon#*before write, iclass 33, count 0 2006.285.07:14:24.93#ibcon#enter sib2, iclass 33, count 0 2006.285.07:14:24.93#ibcon#flushed, iclass 33, count 0 2006.285.07:14:24.93#ibcon#about to write, iclass 33, count 0 2006.285.07:14:24.93#ibcon#wrote, iclass 33, count 0 2006.285.07:14:24.93#ibcon#about to read 3, iclass 33, count 0 2006.285.07:14:24.96#ibcon#read 3, iclass 33, count 0 2006.285.07:14:24.96#ibcon#about to read 4, iclass 33, count 0 2006.285.07:14:24.96#ibcon#read 4, iclass 33, count 0 2006.285.07:14:24.96#ibcon#about to read 5, iclass 33, count 0 2006.285.07:14:24.96#ibcon#read 5, iclass 33, count 0 2006.285.07:14:24.96#ibcon#about to read 6, iclass 33, count 0 2006.285.07:14:24.96#ibcon#read 6, iclass 33, count 0 2006.285.07:14:24.96#ibcon#end of sib2, iclass 33, count 0 2006.285.07:14:24.96#ibcon#*after write, iclass 33, count 0 2006.285.07:14:24.96#ibcon#*before return 0, iclass 33, count 0 2006.285.07:14:24.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:14:24.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:14:24.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:14:24.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:14:24.96$vck44/vblo=5,709.99 2006.285.07:14:24.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.07:14:24.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.07:14:24.96#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:24.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:14:24.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:14:24.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:14:24.96#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:14:24.96#ibcon#first serial, iclass 35, count 0 2006.285.07:14:24.96#ibcon#enter sib2, iclass 35, count 0 2006.285.07:14:24.96#ibcon#flushed, iclass 35, count 0 2006.285.07:14:24.96#ibcon#about to write, iclass 35, count 0 2006.285.07:14:24.96#ibcon#wrote, iclass 35, count 0 2006.285.07:14:24.96#ibcon#about to read 3, iclass 35, count 0 2006.285.07:14:24.98#ibcon#read 3, iclass 35, count 0 2006.285.07:14:24.98#ibcon#about to read 4, iclass 35, count 0 2006.285.07:14:24.98#ibcon#read 4, iclass 35, count 0 2006.285.07:14:24.98#ibcon#about to read 5, iclass 35, count 0 2006.285.07:14:24.98#ibcon#read 5, iclass 35, count 0 2006.285.07:14:24.98#ibcon#about to read 6, iclass 35, count 0 2006.285.07:14:24.98#ibcon#read 6, iclass 35, count 0 2006.285.07:14:24.98#ibcon#end of sib2, iclass 35, count 0 2006.285.07:14:24.98#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:14:24.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:14:24.98#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:14:24.98#ibcon#*before write, iclass 35, count 0 2006.285.07:14:24.98#ibcon#enter sib2, iclass 35, count 0 2006.285.07:14:24.98#ibcon#flushed, iclass 35, count 0 2006.285.07:14:24.98#ibcon#about to write, iclass 35, count 0 2006.285.07:14:24.98#ibcon#wrote, iclass 35, count 0 2006.285.07:14:24.98#ibcon#about to read 3, iclass 35, count 0 2006.285.07:14:25.02#ibcon#read 3, iclass 35, count 0 2006.285.07:14:25.02#ibcon#about to read 4, iclass 35, count 0 2006.285.07:14:25.02#ibcon#read 4, iclass 35, count 0 2006.285.07:14:25.02#ibcon#about to read 5, iclass 35, count 0 2006.285.07:14:25.02#ibcon#read 5, iclass 35, count 0 2006.285.07:14:25.02#ibcon#about to read 6, iclass 35, count 0 2006.285.07:14:25.02#ibcon#read 6, iclass 35, count 0 2006.285.07:14:25.02#ibcon#end of sib2, iclass 35, count 0 2006.285.07:14:25.02#ibcon#*after write, iclass 35, count 0 2006.285.07:14:25.02#ibcon#*before return 0, iclass 35, count 0 2006.285.07:14:25.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:14:25.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:14:25.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:14:25.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:14:25.02$vck44/vb=5,4 2006.285.07:14:25.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.07:14:25.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.07:14:25.02#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:25.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:14:25.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:14:25.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:14:25.08#ibcon#enter wrdev, iclass 37, count 2 2006.285.07:14:25.08#ibcon#first serial, iclass 37, count 2 2006.285.07:14:25.08#ibcon#enter sib2, iclass 37, count 2 2006.285.07:14:25.08#ibcon#flushed, iclass 37, count 2 2006.285.07:14:25.08#ibcon#about to write, iclass 37, count 2 2006.285.07:14:25.08#ibcon#wrote, iclass 37, count 2 2006.285.07:14:25.08#ibcon#about to read 3, iclass 37, count 2 2006.285.07:14:25.10#ibcon#read 3, iclass 37, count 2 2006.285.07:14:25.10#ibcon#about to read 4, iclass 37, count 2 2006.285.07:14:25.10#ibcon#read 4, iclass 37, count 2 2006.285.07:14:25.10#ibcon#about to read 5, iclass 37, count 2 2006.285.07:14:25.10#ibcon#read 5, iclass 37, count 2 2006.285.07:14:25.10#ibcon#about to read 6, iclass 37, count 2 2006.285.07:14:25.10#ibcon#read 6, iclass 37, count 2 2006.285.07:14:25.10#ibcon#end of sib2, iclass 37, count 2 2006.285.07:14:25.10#ibcon#*mode == 0, iclass 37, count 2 2006.285.07:14:25.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.07:14:25.10#ibcon#[27=AT05-04\r\n] 2006.285.07:14:25.10#ibcon#*before write, iclass 37, count 2 2006.285.07:14:25.10#ibcon#enter sib2, iclass 37, count 2 2006.285.07:14:25.10#ibcon#flushed, iclass 37, count 2 2006.285.07:14:25.10#ibcon#about to write, iclass 37, count 2 2006.285.07:14:25.10#ibcon#wrote, iclass 37, count 2 2006.285.07:14:25.10#ibcon#about to read 3, iclass 37, count 2 2006.285.07:14:25.13#ibcon#read 3, iclass 37, count 2 2006.285.07:14:25.13#ibcon#about to read 4, iclass 37, count 2 2006.285.07:14:25.13#ibcon#read 4, iclass 37, count 2 2006.285.07:14:25.13#ibcon#about to read 5, iclass 37, count 2 2006.285.07:14:25.13#ibcon#read 5, iclass 37, count 2 2006.285.07:14:25.13#ibcon#about to read 6, iclass 37, count 2 2006.285.07:14:25.13#ibcon#read 6, iclass 37, count 2 2006.285.07:14:25.13#ibcon#end of sib2, iclass 37, count 2 2006.285.07:14:25.13#ibcon#*after write, iclass 37, count 2 2006.285.07:14:25.13#ibcon#*before return 0, iclass 37, count 2 2006.285.07:14:25.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:14:25.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:14:25.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.07:14:25.13#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:25.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:14:25.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:14:25.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:14:25.25#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:14:25.25#ibcon#first serial, iclass 37, count 0 2006.285.07:14:25.25#ibcon#enter sib2, iclass 37, count 0 2006.285.07:14:25.25#ibcon#flushed, iclass 37, count 0 2006.285.07:14:25.25#ibcon#about to write, iclass 37, count 0 2006.285.07:14:25.25#ibcon#wrote, iclass 37, count 0 2006.285.07:14:25.25#ibcon#about to read 3, iclass 37, count 0 2006.285.07:14:25.27#ibcon#read 3, iclass 37, count 0 2006.285.07:14:25.27#ibcon#about to read 4, iclass 37, count 0 2006.285.07:14:25.27#ibcon#read 4, iclass 37, count 0 2006.285.07:14:25.27#ibcon#about to read 5, iclass 37, count 0 2006.285.07:14:25.27#ibcon#read 5, iclass 37, count 0 2006.285.07:14:25.27#ibcon#about to read 6, iclass 37, count 0 2006.285.07:14:25.27#ibcon#read 6, iclass 37, count 0 2006.285.07:14:25.27#ibcon#end of sib2, iclass 37, count 0 2006.285.07:14:25.27#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:14:25.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:14:25.27#ibcon#[27=USB\r\n] 2006.285.07:14:25.27#ibcon#*before write, iclass 37, count 0 2006.285.07:14:25.27#ibcon#enter sib2, iclass 37, count 0 2006.285.07:14:25.27#ibcon#flushed, iclass 37, count 0 2006.285.07:14:25.27#ibcon#about to write, iclass 37, count 0 2006.285.07:14:25.27#ibcon#wrote, iclass 37, count 0 2006.285.07:14:25.27#ibcon#about to read 3, iclass 37, count 0 2006.285.07:14:25.30#ibcon#read 3, iclass 37, count 0 2006.285.07:14:25.30#ibcon#about to read 4, iclass 37, count 0 2006.285.07:14:25.30#ibcon#read 4, iclass 37, count 0 2006.285.07:14:25.30#ibcon#about to read 5, iclass 37, count 0 2006.285.07:14:25.30#ibcon#read 5, iclass 37, count 0 2006.285.07:14:25.30#ibcon#about to read 6, iclass 37, count 0 2006.285.07:14:25.30#ibcon#read 6, iclass 37, count 0 2006.285.07:14:25.30#ibcon#end of sib2, iclass 37, count 0 2006.285.07:14:25.30#ibcon#*after write, iclass 37, count 0 2006.285.07:14:25.30#ibcon#*before return 0, iclass 37, count 0 2006.285.07:14:25.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:14:25.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:14:25.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:14:25.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:14:25.30$vck44/vblo=6,719.99 2006.285.07:14:25.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.07:14:25.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.07:14:25.30#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:25.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:14:25.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:14:25.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:14:25.30#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:14:25.30#ibcon#first serial, iclass 39, count 0 2006.285.07:14:25.30#ibcon#enter sib2, iclass 39, count 0 2006.285.07:14:25.30#ibcon#flushed, iclass 39, count 0 2006.285.07:14:25.30#ibcon#about to write, iclass 39, count 0 2006.285.07:14:25.30#ibcon#wrote, iclass 39, count 0 2006.285.07:14:25.30#ibcon#about to read 3, iclass 39, count 0 2006.285.07:14:25.32#ibcon#read 3, iclass 39, count 0 2006.285.07:14:25.32#ibcon#about to read 4, iclass 39, count 0 2006.285.07:14:25.32#ibcon#read 4, iclass 39, count 0 2006.285.07:14:25.32#ibcon#about to read 5, iclass 39, count 0 2006.285.07:14:25.32#ibcon#read 5, iclass 39, count 0 2006.285.07:14:25.32#ibcon#about to read 6, iclass 39, count 0 2006.285.07:14:25.32#ibcon#read 6, iclass 39, count 0 2006.285.07:14:25.32#ibcon#end of sib2, iclass 39, count 0 2006.285.07:14:25.32#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:14:25.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:14:25.32#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:14:25.32#ibcon#*before write, iclass 39, count 0 2006.285.07:14:25.32#ibcon#enter sib2, iclass 39, count 0 2006.285.07:14:25.32#ibcon#flushed, iclass 39, count 0 2006.285.07:14:25.32#ibcon#about to write, iclass 39, count 0 2006.285.07:14:25.32#ibcon#wrote, iclass 39, count 0 2006.285.07:14:25.32#ibcon#about to read 3, iclass 39, count 0 2006.285.07:14:25.36#ibcon#read 3, iclass 39, count 0 2006.285.07:14:25.36#ibcon#about to read 4, iclass 39, count 0 2006.285.07:14:25.36#ibcon#read 4, iclass 39, count 0 2006.285.07:14:25.36#ibcon#about to read 5, iclass 39, count 0 2006.285.07:14:25.36#ibcon#read 5, iclass 39, count 0 2006.285.07:14:25.36#ibcon#about to read 6, iclass 39, count 0 2006.285.07:14:25.36#ibcon#read 6, iclass 39, count 0 2006.285.07:14:25.36#ibcon#end of sib2, iclass 39, count 0 2006.285.07:14:25.36#ibcon#*after write, iclass 39, count 0 2006.285.07:14:25.36#ibcon#*before return 0, iclass 39, count 0 2006.285.07:14:25.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:14:25.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:14:25.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:14:25.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:14:25.36$vck44/vb=6,3 2006.285.07:14:25.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.07:14:25.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.07:14:25.36#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:25.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:14:25.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:14:25.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:14:25.42#ibcon#enter wrdev, iclass 3, count 2 2006.285.07:14:25.42#ibcon#first serial, iclass 3, count 2 2006.285.07:14:25.42#ibcon#enter sib2, iclass 3, count 2 2006.285.07:14:25.42#ibcon#flushed, iclass 3, count 2 2006.285.07:14:25.42#ibcon#about to write, iclass 3, count 2 2006.285.07:14:25.42#ibcon#wrote, iclass 3, count 2 2006.285.07:14:25.42#ibcon#about to read 3, iclass 3, count 2 2006.285.07:14:25.44#ibcon#read 3, iclass 3, count 2 2006.285.07:14:25.44#ibcon#about to read 4, iclass 3, count 2 2006.285.07:14:25.44#ibcon#read 4, iclass 3, count 2 2006.285.07:14:25.44#ibcon#about to read 5, iclass 3, count 2 2006.285.07:14:25.44#ibcon#read 5, iclass 3, count 2 2006.285.07:14:25.44#ibcon#about to read 6, iclass 3, count 2 2006.285.07:14:25.44#ibcon#read 6, iclass 3, count 2 2006.285.07:14:25.44#ibcon#end of sib2, iclass 3, count 2 2006.285.07:14:25.44#ibcon#*mode == 0, iclass 3, count 2 2006.285.07:14:25.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.07:14:25.44#ibcon#[27=AT06-03\r\n] 2006.285.07:14:25.44#ibcon#*before write, iclass 3, count 2 2006.285.07:14:25.44#ibcon#enter sib2, iclass 3, count 2 2006.285.07:14:25.44#ibcon#flushed, iclass 3, count 2 2006.285.07:14:25.44#ibcon#about to write, iclass 3, count 2 2006.285.07:14:25.44#ibcon#wrote, iclass 3, count 2 2006.285.07:14:25.44#ibcon#about to read 3, iclass 3, count 2 2006.285.07:14:25.47#ibcon#read 3, iclass 3, count 2 2006.285.07:14:25.47#ibcon#about to read 4, iclass 3, count 2 2006.285.07:14:25.47#ibcon#read 4, iclass 3, count 2 2006.285.07:14:25.47#ibcon#about to read 5, iclass 3, count 2 2006.285.07:14:25.47#ibcon#read 5, iclass 3, count 2 2006.285.07:14:25.47#ibcon#about to read 6, iclass 3, count 2 2006.285.07:14:25.47#ibcon#read 6, iclass 3, count 2 2006.285.07:14:25.47#ibcon#end of sib2, iclass 3, count 2 2006.285.07:14:25.47#ibcon#*after write, iclass 3, count 2 2006.285.07:14:25.47#ibcon#*before return 0, iclass 3, count 2 2006.285.07:14:25.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:14:25.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:14:25.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.07:14:25.47#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:25.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:14:25.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:14:25.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:14:25.59#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:14:25.59#ibcon#first serial, iclass 3, count 0 2006.285.07:14:25.59#ibcon#enter sib2, iclass 3, count 0 2006.285.07:14:25.59#ibcon#flushed, iclass 3, count 0 2006.285.07:14:25.59#ibcon#about to write, iclass 3, count 0 2006.285.07:14:25.59#ibcon#wrote, iclass 3, count 0 2006.285.07:14:25.59#ibcon#about to read 3, iclass 3, count 0 2006.285.07:14:25.61#ibcon#read 3, iclass 3, count 0 2006.285.07:14:25.61#ibcon#about to read 4, iclass 3, count 0 2006.285.07:14:25.61#ibcon#read 4, iclass 3, count 0 2006.285.07:14:25.61#ibcon#about to read 5, iclass 3, count 0 2006.285.07:14:25.61#ibcon#read 5, iclass 3, count 0 2006.285.07:14:25.61#ibcon#about to read 6, iclass 3, count 0 2006.285.07:14:25.61#ibcon#read 6, iclass 3, count 0 2006.285.07:14:25.61#ibcon#end of sib2, iclass 3, count 0 2006.285.07:14:25.61#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:14:25.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:14:25.61#ibcon#[27=USB\r\n] 2006.285.07:14:25.61#ibcon#*before write, iclass 3, count 0 2006.285.07:14:25.61#ibcon#enter sib2, iclass 3, count 0 2006.285.07:14:25.61#ibcon#flushed, iclass 3, count 0 2006.285.07:14:25.61#ibcon#about to write, iclass 3, count 0 2006.285.07:14:25.61#ibcon#wrote, iclass 3, count 0 2006.285.07:14:25.61#ibcon#about to read 3, iclass 3, count 0 2006.285.07:14:25.64#ibcon#read 3, iclass 3, count 0 2006.285.07:14:25.64#ibcon#about to read 4, iclass 3, count 0 2006.285.07:14:25.64#ibcon#read 4, iclass 3, count 0 2006.285.07:14:25.64#ibcon#about to read 5, iclass 3, count 0 2006.285.07:14:25.64#ibcon#read 5, iclass 3, count 0 2006.285.07:14:25.64#ibcon#about to read 6, iclass 3, count 0 2006.285.07:14:25.64#ibcon#read 6, iclass 3, count 0 2006.285.07:14:25.64#ibcon#end of sib2, iclass 3, count 0 2006.285.07:14:25.64#ibcon#*after write, iclass 3, count 0 2006.285.07:14:25.64#ibcon#*before return 0, iclass 3, count 0 2006.285.07:14:25.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:14:25.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:14:25.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:14:25.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:14:25.64$vck44/vblo=7,734.99 2006.285.07:14:25.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.07:14:25.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.07:14:25.64#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:25.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:14:25.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:14:25.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:14:25.64#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:14:25.64#ibcon#first serial, iclass 5, count 0 2006.285.07:14:25.64#ibcon#enter sib2, iclass 5, count 0 2006.285.07:14:25.64#ibcon#flushed, iclass 5, count 0 2006.285.07:14:25.64#ibcon#about to write, iclass 5, count 0 2006.285.07:14:25.64#ibcon#wrote, iclass 5, count 0 2006.285.07:14:25.64#ibcon#about to read 3, iclass 5, count 0 2006.285.07:14:25.66#ibcon#read 3, iclass 5, count 0 2006.285.07:14:25.66#ibcon#about to read 4, iclass 5, count 0 2006.285.07:14:25.66#ibcon#read 4, iclass 5, count 0 2006.285.07:14:25.66#ibcon#about to read 5, iclass 5, count 0 2006.285.07:14:25.66#ibcon#read 5, iclass 5, count 0 2006.285.07:14:25.66#ibcon#about to read 6, iclass 5, count 0 2006.285.07:14:25.66#ibcon#read 6, iclass 5, count 0 2006.285.07:14:25.66#ibcon#end of sib2, iclass 5, count 0 2006.285.07:14:25.66#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:14:25.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:14:25.66#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:14:25.66#ibcon#*before write, iclass 5, count 0 2006.285.07:14:25.66#ibcon#enter sib2, iclass 5, count 0 2006.285.07:14:25.66#ibcon#flushed, iclass 5, count 0 2006.285.07:14:25.66#ibcon#about to write, iclass 5, count 0 2006.285.07:14:25.66#ibcon#wrote, iclass 5, count 0 2006.285.07:14:25.66#ibcon#about to read 3, iclass 5, count 0 2006.285.07:14:25.70#ibcon#read 3, iclass 5, count 0 2006.285.07:14:25.70#ibcon#about to read 4, iclass 5, count 0 2006.285.07:14:25.70#ibcon#read 4, iclass 5, count 0 2006.285.07:14:25.70#ibcon#about to read 5, iclass 5, count 0 2006.285.07:14:25.70#ibcon#read 5, iclass 5, count 0 2006.285.07:14:25.70#ibcon#about to read 6, iclass 5, count 0 2006.285.07:14:25.70#ibcon#read 6, iclass 5, count 0 2006.285.07:14:25.70#ibcon#end of sib2, iclass 5, count 0 2006.285.07:14:25.70#ibcon#*after write, iclass 5, count 0 2006.285.07:14:25.70#ibcon#*before return 0, iclass 5, count 0 2006.285.07:14:25.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:14:25.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:14:25.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:14:25.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:14:25.70$vck44/vb=7,4 2006.285.07:14:25.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.07:14:25.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.07:14:25.70#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:25.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:14:25.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:14:25.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:14:25.76#ibcon#enter wrdev, iclass 7, count 2 2006.285.07:14:25.76#ibcon#first serial, iclass 7, count 2 2006.285.07:14:25.76#ibcon#enter sib2, iclass 7, count 2 2006.285.07:14:25.76#ibcon#flushed, iclass 7, count 2 2006.285.07:14:25.76#ibcon#about to write, iclass 7, count 2 2006.285.07:14:25.76#ibcon#wrote, iclass 7, count 2 2006.285.07:14:25.76#ibcon#about to read 3, iclass 7, count 2 2006.285.07:14:25.78#ibcon#read 3, iclass 7, count 2 2006.285.07:14:25.78#ibcon#about to read 4, iclass 7, count 2 2006.285.07:14:25.78#ibcon#read 4, iclass 7, count 2 2006.285.07:14:25.78#ibcon#about to read 5, iclass 7, count 2 2006.285.07:14:25.78#ibcon#read 5, iclass 7, count 2 2006.285.07:14:25.78#ibcon#about to read 6, iclass 7, count 2 2006.285.07:14:25.78#ibcon#read 6, iclass 7, count 2 2006.285.07:14:25.78#ibcon#end of sib2, iclass 7, count 2 2006.285.07:14:25.78#ibcon#*mode == 0, iclass 7, count 2 2006.285.07:14:25.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.07:14:25.78#ibcon#[27=AT07-04\r\n] 2006.285.07:14:25.78#ibcon#*before write, iclass 7, count 2 2006.285.07:14:25.78#ibcon#enter sib2, iclass 7, count 2 2006.285.07:14:25.78#ibcon#flushed, iclass 7, count 2 2006.285.07:14:25.78#ibcon#about to write, iclass 7, count 2 2006.285.07:14:25.78#ibcon#wrote, iclass 7, count 2 2006.285.07:14:25.78#ibcon#about to read 3, iclass 7, count 2 2006.285.07:14:25.81#ibcon#read 3, iclass 7, count 2 2006.285.07:14:25.81#ibcon#about to read 4, iclass 7, count 2 2006.285.07:14:25.81#ibcon#read 4, iclass 7, count 2 2006.285.07:14:25.81#ibcon#about to read 5, iclass 7, count 2 2006.285.07:14:25.81#ibcon#read 5, iclass 7, count 2 2006.285.07:14:25.81#ibcon#about to read 6, iclass 7, count 2 2006.285.07:14:25.81#ibcon#read 6, iclass 7, count 2 2006.285.07:14:25.81#ibcon#end of sib2, iclass 7, count 2 2006.285.07:14:25.81#ibcon#*after write, iclass 7, count 2 2006.285.07:14:25.81#ibcon#*before return 0, iclass 7, count 2 2006.285.07:14:25.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:14:25.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:14:25.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.07:14:25.81#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:25.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:14:25.93#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:14:25.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:14:25.93#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:14:25.93#ibcon#first serial, iclass 7, count 0 2006.285.07:14:25.93#ibcon#enter sib2, iclass 7, count 0 2006.285.07:14:25.93#ibcon#flushed, iclass 7, count 0 2006.285.07:14:25.93#ibcon#about to write, iclass 7, count 0 2006.285.07:14:25.93#ibcon#wrote, iclass 7, count 0 2006.285.07:14:25.93#ibcon#about to read 3, iclass 7, count 0 2006.285.07:14:25.95#ibcon#read 3, iclass 7, count 0 2006.285.07:14:25.95#ibcon#about to read 4, iclass 7, count 0 2006.285.07:14:25.95#ibcon#read 4, iclass 7, count 0 2006.285.07:14:25.95#ibcon#about to read 5, iclass 7, count 0 2006.285.07:14:25.95#ibcon#read 5, iclass 7, count 0 2006.285.07:14:25.95#ibcon#about to read 6, iclass 7, count 0 2006.285.07:14:25.95#ibcon#read 6, iclass 7, count 0 2006.285.07:14:25.95#ibcon#end of sib2, iclass 7, count 0 2006.285.07:14:25.95#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:14:25.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:14:25.95#ibcon#[27=USB\r\n] 2006.285.07:14:25.95#ibcon#*before write, iclass 7, count 0 2006.285.07:14:25.95#ibcon#enter sib2, iclass 7, count 0 2006.285.07:14:25.95#ibcon#flushed, iclass 7, count 0 2006.285.07:14:25.95#ibcon#about to write, iclass 7, count 0 2006.285.07:14:25.95#ibcon#wrote, iclass 7, count 0 2006.285.07:14:25.95#ibcon#about to read 3, iclass 7, count 0 2006.285.07:14:25.98#ibcon#read 3, iclass 7, count 0 2006.285.07:14:25.98#ibcon#about to read 4, iclass 7, count 0 2006.285.07:14:25.98#ibcon#read 4, iclass 7, count 0 2006.285.07:14:25.98#ibcon#about to read 5, iclass 7, count 0 2006.285.07:14:25.98#ibcon#read 5, iclass 7, count 0 2006.285.07:14:25.98#ibcon#about to read 6, iclass 7, count 0 2006.285.07:14:25.98#ibcon#read 6, iclass 7, count 0 2006.285.07:14:25.98#ibcon#end of sib2, iclass 7, count 0 2006.285.07:14:25.98#ibcon#*after write, iclass 7, count 0 2006.285.07:14:25.98#ibcon#*before return 0, iclass 7, count 0 2006.285.07:14:25.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:14:25.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:14:25.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:14:25.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:14:25.98$vck44/vblo=8,744.99 2006.285.07:14:25.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.07:14:25.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.07:14:25.98#ibcon#ireg 17 cls_cnt 0 2006.285.07:14:25.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:14:25.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:14:25.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:14:25.98#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:14:25.98#ibcon#first serial, iclass 11, count 0 2006.285.07:14:25.98#ibcon#enter sib2, iclass 11, count 0 2006.285.07:14:25.98#ibcon#flushed, iclass 11, count 0 2006.285.07:14:25.98#ibcon#about to write, iclass 11, count 0 2006.285.07:14:25.98#ibcon#wrote, iclass 11, count 0 2006.285.07:14:25.98#ibcon#about to read 3, iclass 11, count 0 2006.285.07:14:26.00#ibcon#read 3, iclass 11, count 0 2006.285.07:14:26.00#ibcon#about to read 4, iclass 11, count 0 2006.285.07:14:26.00#ibcon#read 4, iclass 11, count 0 2006.285.07:14:26.00#ibcon#about to read 5, iclass 11, count 0 2006.285.07:14:26.00#ibcon#read 5, iclass 11, count 0 2006.285.07:14:26.00#ibcon#about to read 6, iclass 11, count 0 2006.285.07:14:26.00#ibcon#read 6, iclass 11, count 0 2006.285.07:14:26.00#ibcon#end of sib2, iclass 11, count 0 2006.285.07:14:26.00#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:14:26.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:14:26.00#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:14:26.00#ibcon#*before write, iclass 11, count 0 2006.285.07:14:26.00#ibcon#enter sib2, iclass 11, count 0 2006.285.07:14:26.00#ibcon#flushed, iclass 11, count 0 2006.285.07:14:26.00#ibcon#about to write, iclass 11, count 0 2006.285.07:14:26.00#ibcon#wrote, iclass 11, count 0 2006.285.07:14:26.00#ibcon#about to read 3, iclass 11, count 0 2006.285.07:14:26.04#ibcon#read 3, iclass 11, count 0 2006.285.07:14:26.04#ibcon#about to read 4, iclass 11, count 0 2006.285.07:14:26.04#ibcon#read 4, iclass 11, count 0 2006.285.07:14:26.04#ibcon#about to read 5, iclass 11, count 0 2006.285.07:14:26.04#ibcon#read 5, iclass 11, count 0 2006.285.07:14:26.04#ibcon#about to read 6, iclass 11, count 0 2006.285.07:14:26.04#ibcon#read 6, iclass 11, count 0 2006.285.07:14:26.04#ibcon#end of sib2, iclass 11, count 0 2006.285.07:14:26.04#ibcon#*after write, iclass 11, count 0 2006.285.07:14:26.04#ibcon#*before return 0, iclass 11, count 0 2006.285.07:14:26.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:14:26.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:14:26.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:14:26.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:14:26.04$vck44/vb=8,4 2006.285.07:14:26.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.07:14:26.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.07:14:26.04#ibcon#ireg 11 cls_cnt 2 2006.285.07:14:26.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:14:26.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:14:26.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:14:26.10#ibcon#enter wrdev, iclass 13, count 2 2006.285.07:14:26.10#ibcon#first serial, iclass 13, count 2 2006.285.07:14:26.10#ibcon#enter sib2, iclass 13, count 2 2006.285.07:14:26.10#ibcon#flushed, iclass 13, count 2 2006.285.07:14:26.10#ibcon#about to write, iclass 13, count 2 2006.285.07:14:26.10#ibcon#wrote, iclass 13, count 2 2006.285.07:14:26.10#ibcon#about to read 3, iclass 13, count 2 2006.285.07:14:26.12#ibcon#read 3, iclass 13, count 2 2006.285.07:14:26.12#ibcon#about to read 4, iclass 13, count 2 2006.285.07:14:26.12#ibcon#read 4, iclass 13, count 2 2006.285.07:14:26.12#ibcon#about to read 5, iclass 13, count 2 2006.285.07:14:26.12#ibcon#read 5, iclass 13, count 2 2006.285.07:14:26.12#ibcon#about to read 6, iclass 13, count 2 2006.285.07:14:26.12#ibcon#read 6, iclass 13, count 2 2006.285.07:14:26.12#ibcon#end of sib2, iclass 13, count 2 2006.285.07:14:26.12#ibcon#*mode == 0, iclass 13, count 2 2006.285.07:14:26.12#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.07:14:26.12#ibcon#[27=AT08-04\r\n] 2006.285.07:14:26.12#ibcon#*before write, iclass 13, count 2 2006.285.07:14:26.12#ibcon#enter sib2, iclass 13, count 2 2006.285.07:14:26.12#ibcon#flushed, iclass 13, count 2 2006.285.07:14:26.12#ibcon#about to write, iclass 13, count 2 2006.285.07:14:26.12#ibcon#wrote, iclass 13, count 2 2006.285.07:14:26.12#ibcon#about to read 3, iclass 13, count 2 2006.285.07:14:26.15#ibcon#read 3, iclass 13, count 2 2006.285.07:14:26.15#ibcon#about to read 4, iclass 13, count 2 2006.285.07:14:26.15#ibcon#read 4, iclass 13, count 2 2006.285.07:14:26.15#ibcon#about to read 5, iclass 13, count 2 2006.285.07:14:26.15#ibcon#read 5, iclass 13, count 2 2006.285.07:14:26.15#ibcon#about to read 6, iclass 13, count 2 2006.285.07:14:26.15#ibcon#read 6, iclass 13, count 2 2006.285.07:14:26.15#ibcon#end of sib2, iclass 13, count 2 2006.285.07:14:26.15#ibcon#*after write, iclass 13, count 2 2006.285.07:14:26.15#ibcon#*before return 0, iclass 13, count 2 2006.285.07:14:26.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:14:26.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:14:26.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.07:14:26.15#ibcon#ireg 7 cls_cnt 0 2006.285.07:14:26.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:14:26.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:14:26.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:14:26.27#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:14:26.27#ibcon#first serial, iclass 13, count 0 2006.285.07:14:26.27#ibcon#enter sib2, iclass 13, count 0 2006.285.07:14:26.27#ibcon#flushed, iclass 13, count 0 2006.285.07:14:26.27#ibcon#about to write, iclass 13, count 0 2006.285.07:14:26.27#ibcon#wrote, iclass 13, count 0 2006.285.07:14:26.27#ibcon#about to read 3, iclass 13, count 0 2006.285.07:14:26.29#ibcon#read 3, iclass 13, count 0 2006.285.07:14:26.29#ibcon#about to read 4, iclass 13, count 0 2006.285.07:14:26.29#ibcon#read 4, iclass 13, count 0 2006.285.07:14:26.29#ibcon#about to read 5, iclass 13, count 0 2006.285.07:14:26.29#ibcon#read 5, iclass 13, count 0 2006.285.07:14:26.29#ibcon#about to read 6, iclass 13, count 0 2006.285.07:14:26.29#ibcon#read 6, iclass 13, count 0 2006.285.07:14:26.29#ibcon#end of sib2, iclass 13, count 0 2006.285.07:14:26.29#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:14:26.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:14:26.29#ibcon#[27=USB\r\n] 2006.285.07:14:26.29#ibcon#*before write, iclass 13, count 0 2006.285.07:14:26.29#ibcon#enter sib2, iclass 13, count 0 2006.285.07:14:26.29#ibcon#flushed, iclass 13, count 0 2006.285.07:14:26.29#ibcon#about to write, iclass 13, count 0 2006.285.07:14:26.29#ibcon#wrote, iclass 13, count 0 2006.285.07:14:26.29#ibcon#about to read 3, iclass 13, count 0 2006.285.07:14:26.32#ibcon#read 3, iclass 13, count 0 2006.285.07:14:26.32#ibcon#about to read 4, iclass 13, count 0 2006.285.07:14:26.32#ibcon#read 4, iclass 13, count 0 2006.285.07:14:26.32#ibcon#about to read 5, iclass 13, count 0 2006.285.07:14:26.32#ibcon#read 5, iclass 13, count 0 2006.285.07:14:26.32#ibcon#about to read 6, iclass 13, count 0 2006.285.07:14:26.32#ibcon#read 6, iclass 13, count 0 2006.285.07:14:26.32#ibcon#end of sib2, iclass 13, count 0 2006.285.07:14:26.32#ibcon#*after write, iclass 13, count 0 2006.285.07:14:26.32#ibcon#*before return 0, iclass 13, count 0 2006.285.07:14:26.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:14:26.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:14:26.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:14:26.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:14:26.32$vck44/vabw=wide 2006.285.07:14:26.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.07:14:26.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.07:14:26.32#ibcon#ireg 8 cls_cnt 0 2006.285.07:14:26.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:14:26.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:14:26.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:14:26.32#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:14:26.32#ibcon#first serial, iclass 15, count 0 2006.285.07:14:26.32#ibcon#enter sib2, iclass 15, count 0 2006.285.07:14:26.32#ibcon#flushed, iclass 15, count 0 2006.285.07:14:26.32#ibcon#about to write, iclass 15, count 0 2006.285.07:14:26.32#ibcon#wrote, iclass 15, count 0 2006.285.07:14:26.32#ibcon#about to read 3, iclass 15, count 0 2006.285.07:14:26.34#ibcon#read 3, iclass 15, count 0 2006.285.07:14:26.34#ibcon#about to read 4, iclass 15, count 0 2006.285.07:14:26.34#ibcon#read 4, iclass 15, count 0 2006.285.07:14:26.34#ibcon#about to read 5, iclass 15, count 0 2006.285.07:14:26.34#ibcon#read 5, iclass 15, count 0 2006.285.07:14:26.34#ibcon#about to read 6, iclass 15, count 0 2006.285.07:14:26.34#ibcon#read 6, iclass 15, count 0 2006.285.07:14:26.34#ibcon#end of sib2, iclass 15, count 0 2006.285.07:14:26.34#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:14:26.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:14:26.34#ibcon#[25=BW32\r\n] 2006.285.07:14:26.34#ibcon#*before write, iclass 15, count 0 2006.285.07:14:26.34#ibcon#enter sib2, iclass 15, count 0 2006.285.07:14:26.34#ibcon#flushed, iclass 15, count 0 2006.285.07:14:26.34#ibcon#about to write, iclass 15, count 0 2006.285.07:14:26.34#ibcon#wrote, iclass 15, count 0 2006.285.07:14:26.34#ibcon#about to read 3, iclass 15, count 0 2006.285.07:14:26.37#ibcon#read 3, iclass 15, count 0 2006.285.07:14:26.37#ibcon#about to read 4, iclass 15, count 0 2006.285.07:14:26.37#ibcon#read 4, iclass 15, count 0 2006.285.07:14:26.37#ibcon#about to read 5, iclass 15, count 0 2006.285.07:14:26.37#ibcon#read 5, iclass 15, count 0 2006.285.07:14:26.37#ibcon#about to read 6, iclass 15, count 0 2006.285.07:14:26.37#ibcon#read 6, iclass 15, count 0 2006.285.07:14:26.37#ibcon#end of sib2, iclass 15, count 0 2006.285.07:14:26.37#ibcon#*after write, iclass 15, count 0 2006.285.07:14:26.37#ibcon#*before return 0, iclass 15, count 0 2006.285.07:14:26.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:14:26.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:14:26.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:14:26.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:14:26.37$vck44/vbbw=wide 2006.285.07:14:26.37#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.07:14:26.37#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.07:14:26.37#ibcon#ireg 8 cls_cnt 0 2006.285.07:14:26.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:14:26.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:14:26.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:14:26.44#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:14:26.44#ibcon#first serial, iclass 17, count 0 2006.285.07:14:26.44#ibcon#enter sib2, iclass 17, count 0 2006.285.07:14:26.44#ibcon#flushed, iclass 17, count 0 2006.285.07:14:26.44#ibcon#about to write, iclass 17, count 0 2006.285.07:14:26.44#ibcon#wrote, iclass 17, count 0 2006.285.07:14:26.44#ibcon#about to read 3, iclass 17, count 0 2006.285.07:14:26.46#ibcon#read 3, iclass 17, count 0 2006.285.07:14:26.46#ibcon#about to read 4, iclass 17, count 0 2006.285.07:14:26.46#ibcon#read 4, iclass 17, count 0 2006.285.07:14:26.46#ibcon#about to read 5, iclass 17, count 0 2006.285.07:14:26.46#ibcon#read 5, iclass 17, count 0 2006.285.07:14:26.46#ibcon#about to read 6, iclass 17, count 0 2006.285.07:14:26.46#ibcon#read 6, iclass 17, count 0 2006.285.07:14:26.46#ibcon#end of sib2, iclass 17, count 0 2006.285.07:14:26.46#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:14:26.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:14:26.46#ibcon#[27=BW32\r\n] 2006.285.07:14:26.46#ibcon#*before write, iclass 17, count 0 2006.285.07:14:26.46#ibcon#enter sib2, iclass 17, count 0 2006.285.07:14:26.46#ibcon#flushed, iclass 17, count 0 2006.285.07:14:26.46#ibcon#about to write, iclass 17, count 0 2006.285.07:14:26.46#ibcon#wrote, iclass 17, count 0 2006.285.07:14:26.46#ibcon#about to read 3, iclass 17, count 0 2006.285.07:14:26.49#ibcon#read 3, iclass 17, count 0 2006.285.07:14:26.49#ibcon#about to read 4, iclass 17, count 0 2006.285.07:14:26.49#ibcon#read 4, iclass 17, count 0 2006.285.07:14:26.49#ibcon#about to read 5, iclass 17, count 0 2006.285.07:14:26.49#ibcon#read 5, iclass 17, count 0 2006.285.07:14:26.49#ibcon#about to read 6, iclass 17, count 0 2006.285.07:14:26.49#ibcon#read 6, iclass 17, count 0 2006.285.07:14:26.49#ibcon#end of sib2, iclass 17, count 0 2006.285.07:14:26.49#ibcon#*after write, iclass 17, count 0 2006.285.07:14:26.49#ibcon#*before return 0, iclass 17, count 0 2006.285.07:14:26.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:14:26.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:14:26.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:14:26.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:14:26.49$setupk4/ifdk4 2006.285.07:14:26.49$ifdk4/lo= 2006.285.07:14:26.49$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:14:26.49$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:14:26.49$ifdk4/patch= 2006.285.07:14:26.49$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:14:26.49$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:14:26.49$setupk4/!*+20s 2006.285.07:14:34.10#abcon#<5=/05 3.7 6.2 24.05 751014.2\r\n> 2006.285.07:14:34.12#abcon#{5=INTERFACE CLEAR} 2006.285.07:14:34.18#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:14:41.00$setupk4/"tpicd 2006.285.07:14:41.00$setupk4/echo=off 2006.285.07:14:41.00$setupk4/xlog=off 2006.285.07:14:41.00:!2006.285.07:18:37 2006.285.07:14:44.13#trakl#Source acquired 2006.285.07:14:45.13#flagr#flagr/antenna,acquired 2006.285.07:18:37.00:preob 2006.285.07:18:37.14/onsource/TRACKING 2006.285.07:18:37.14:!2006.285.07:18:47 2006.285.07:18:47.00:"tape 2006.285.07:18:47.00:"st=record 2006.285.07:18:47.00:data_valid=on 2006.285.07:18:47.00:midob 2006.285.07:18:48.14/onsource/TRACKING 2006.285.07:18:48.14/wx/23.95,1014.3,76 2006.285.07:18:48.19/cable/+6.4740E-03 2006.285.07:18:49.28/va/01,07,usb,yes,38,41 2006.285.07:18:49.28/va/02,06,usb,yes,38,39 2006.285.07:18:49.28/va/03,07,usb,yes,38,40 2006.285.07:18:49.28/va/04,06,usb,yes,39,41 2006.285.07:18:49.28/va/05,03,usb,yes,39,39 2006.285.07:18:49.28/va/06,04,usb,yes,35,34 2006.285.07:18:49.28/va/07,04,usb,yes,36,36 2006.285.07:18:49.28/va/08,03,usb,yes,36,44 2006.285.07:18:49.51/valo/01,524.99,yes,locked 2006.285.07:18:49.51/valo/02,534.99,yes,locked 2006.285.07:18:49.51/valo/03,564.99,yes,locked 2006.285.07:18:49.51/valo/04,624.99,yes,locked 2006.285.07:18:49.51/valo/05,734.99,yes,locked 2006.285.07:18:49.51/valo/06,814.99,yes,locked 2006.285.07:18:49.51/valo/07,864.99,yes,locked 2006.285.07:18:49.51/valo/08,884.99,yes,locked 2006.285.07:18:50.60/vb/01,04,usb,yes,38,35 2006.285.07:18:50.60/vb/02,05,usb,yes,36,35 2006.285.07:18:50.60/vb/03,04,usb,yes,37,41 2006.285.07:18:50.60/vb/04,05,usb,yes,37,36 2006.285.07:18:50.60/vb/05,04,usb,yes,33,36 2006.285.07:18:50.60/vb/06,03,usb,yes,47,42 2006.285.07:18:50.60/vb/07,04,usb,yes,38,38 2006.285.07:18:50.60/vb/08,04,usb,yes,34,39 2006.285.07:18:50.83/vblo/01,629.99,yes,locked 2006.285.07:18:50.83/vblo/02,634.99,yes,locked 2006.285.07:18:50.83/vblo/03,649.99,yes,locked 2006.285.07:18:50.83/vblo/04,679.99,yes,locked 2006.285.07:18:50.83/vblo/05,709.99,yes,locked 2006.285.07:18:50.83/vblo/06,719.99,yes,locked 2006.285.07:18:50.83/vblo/07,734.99,yes,locked 2006.285.07:18:50.83/vblo/08,744.99,yes,locked 2006.285.07:18:50.98/vabw/8 2006.285.07:18:51.13/vbbw/8 2006.285.07:18:51.22/xfe/off,on,12.2 2006.285.07:18:51.60/ifatt/23,28,28,28 2006.285.07:18:52.07/fmout-gps/S +2.59E-07 2006.285.07:18:52.09:!2006.285.07:20:47 2006.285.07:20:47.00:data_valid=off 2006.285.07:20:47.00:"et 2006.285.07:20:47.00:!+3s 2006.285.07:20:50.01:"tape 2006.285.07:20:50.01:postob 2006.285.07:20:50.18/cable/+6.4737E-03 2006.285.07:20:50.18/wx/23.91,1014.3,75 2006.285.07:20:51.07/fmout-gps/S +2.59E-07 2006.285.07:20:51.07:scan_name=285-0724,jd0610,290 2006.285.07:20:51.07:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.285.07:20:51.14#flagr#flagr/antenna,new-source 2006.285.07:20:52.14:checkk5 2006.285.07:20:52.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:20:52.93/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:20:53.50/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:20:53.92/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:20:54.60/chk_obsdata//k5ts1/T2850718??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.285.07:20:54.96/chk_obsdata//k5ts2/T2850718??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.285.07:20:55.37/chk_obsdata//k5ts3/T2850718??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.285.07:20:55.77/chk_obsdata//k5ts4/T2850718??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.285.07:20:57.03/k5log//k5ts1_log_newline 2006.285.07:20:57.90/k5log//k5ts2_log_newline 2006.285.07:20:58.67/k5log//k5ts3_log_newline 2006.285.07:20:59.45/k5log//k5ts4_log_newline 2006.285.07:20:59.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:20:59.47:setupk4=1 2006.285.07:20:59.47$setupk4/echo=on 2006.285.07:20:59.47$setupk4/pcalon 2006.285.07:20:59.47$pcalon/"no phase cal control is implemented here 2006.285.07:20:59.47$setupk4/"tpicd=stop 2006.285.07:20:59.47$setupk4/"rec=synch_on 2006.285.07:20:59.48$setupk4/"rec_mode=128 2006.285.07:20:59.48$setupk4/!* 2006.285.07:20:59.48$setupk4/recpk4 2006.285.07:20:59.48$recpk4/recpatch= 2006.285.07:20:59.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:20:59.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:20:59.48$setupk4/vck44 2006.285.07:20:59.48$vck44/valo=1,524.99 2006.285.07:20:59.48#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.07:20:59.48#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.07:20:59.48#ibcon#ireg 17 cls_cnt 0 2006.285.07:20:59.48#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:20:59.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:20:59.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:20:59.48#ibcon#enter wrdev, iclass 30, count 0 2006.285.07:20:59.48#ibcon#first serial, iclass 30, count 0 2006.285.07:20:59.48#ibcon#enter sib2, iclass 30, count 0 2006.285.07:20:59.48#ibcon#flushed, iclass 30, count 0 2006.285.07:20:59.48#ibcon#about to write, iclass 30, count 0 2006.285.07:20:59.48#ibcon#wrote, iclass 30, count 0 2006.285.07:20:59.48#ibcon#about to read 3, iclass 30, count 0 2006.285.07:20:59.50#ibcon#read 3, iclass 30, count 0 2006.285.07:20:59.50#ibcon#about to read 4, iclass 30, count 0 2006.285.07:20:59.50#ibcon#read 4, iclass 30, count 0 2006.285.07:20:59.50#ibcon#about to read 5, iclass 30, count 0 2006.285.07:20:59.50#ibcon#read 5, iclass 30, count 0 2006.285.07:20:59.50#ibcon#about to read 6, iclass 30, count 0 2006.285.07:20:59.50#ibcon#read 6, iclass 30, count 0 2006.285.07:20:59.50#ibcon#end of sib2, iclass 30, count 0 2006.285.07:20:59.50#ibcon#*mode == 0, iclass 30, count 0 2006.285.07:20:59.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.07:20:59.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:20:59.50#ibcon#*before write, iclass 30, count 0 2006.285.07:20:59.50#ibcon#enter sib2, iclass 30, count 0 2006.285.07:20:59.50#ibcon#flushed, iclass 30, count 0 2006.285.07:20:59.50#ibcon#about to write, iclass 30, count 0 2006.285.07:20:59.50#ibcon#wrote, iclass 30, count 0 2006.285.07:20:59.50#ibcon#about to read 3, iclass 30, count 0 2006.285.07:20:59.55#ibcon#read 3, iclass 30, count 0 2006.285.07:20:59.55#ibcon#about to read 4, iclass 30, count 0 2006.285.07:20:59.55#ibcon#read 4, iclass 30, count 0 2006.285.07:20:59.55#ibcon#about to read 5, iclass 30, count 0 2006.285.07:20:59.55#ibcon#read 5, iclass 30, count 0 2006.285.07:20:59.55#ibcon#about to read 6, iclass 30, count 0 2006.285.07:20:59.55#ibcon#read 6, iclass 30, count 0 2006.285.07:20:59.55#ibcon#end of sib2, iclass 30, count 0 2006.285.07:20:59.55#ibcon#*after write, iclass 30, count 0 2006.285.07:20:59.55#ibcon#*before return 0, iclass 30, count 0 2006.285.07:20:59.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:20:59.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:20:59.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.07:20:59.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.07:20:59.55$vck44/va=1,7 2006.285.07:20:59.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.07:20:59.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.07:20:59.55#ibcon#ireg 11 cls_cnt 2 2006.285.07:20:59.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:20:59.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:20:59.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:20:59.55#ibcon#enter wrdev, iclass 32, count 2 2006.285.07:20:59.55#ibcon#first serial, iclass 32, count 2 2006.285.07:20:59.55#ibcon#enter sib2, iclass 32, count 2 2006.285.07:20:59.55#ibcon#flushed, iclass 32, count 2 2006.285.07:20:59.55#ibcon#about to write, iclass 32, count 2 2006.285.07:20:59.55#ibcon#wrote, iclass 32, count 2 2006.285.07:20:59.55#ibcon#about to read 3, iclass 32, count 2 2006.285.07:20:59.57#ibcon#read 3, iclass 32, count 2 2006.285.07:20:59.57#ibcon#about to read 4, iclass 32, count 2 2006.285.07:20:59.57#ibcon#read 4, iclass 32, count 2 2006.285.07:20:59.57#ibcon#about to read 5, iclass 32, count 2 2006.285.07:20:59.57#ibcon#read 5, iclass 32, count 2 2006.285.07:20:59.57#ibcon#about to read 6, iclass 32, count 2 2006.285.07:20:59.57#ibcon#read 6, iclass 32, count 2 2006.285.07:20:59.57#ibcon#end of sib2, iclass 32, count 2 2006.285.07:20:59.57#ibcon#*mode == 0, iclass 32, count 2 2006.285.07:20:59.57#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.07:20:59.57#ibcon#[25=AT01-07\r\n] 2006.285.07:20:59.57#ibcon#*before write, iclass 32, count 2 2006.285.07:20:59.57#ibcon#enter sib2, iclass 32, count 2 2006.285.07:20:59.57#ibcon#flushed, iclass 32, count 2 2006.285.07:20:59.57#ibcon#about to write, iclass 32, count 2 2006.285.07:20:59.57#ibcon#wrote, iclass 32, count 2 2006.285.07:20:59.57#ibcon#about to read 3, iclass 32, count 2 2006.285.07:20:59.60#ibcon#read 3, iclass 32, count 2 2006.285.07:20:59.60#ibcon#about to read 4, iclass 32, count 2 2006.285.07:20:59.60#ibcon#read 4, iclass 32, count 2 2006.285.07:20:59.60#ibcon#about to read 5, iclass 32, count 2 2006.285.07:20:59.60#ibcon#read 5, iclass 32, count 2 2006.285.07:20:59.60#ibcon#about to read 6, iclass 32, count 2 2006.285.07:20:59.60#ibcon#read 6, iclass 32, count 2 2006.285.07:20:59.60#ibcon#end of sib2, iclass 32, count 2 2006.285.07:20:59.60#ibcon#*after write, iclass 32, count 2 2006.285.07:20:59.60#ibcon#*before return 0, iclass 32, count 2 2006.285.07:20:59.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:20:59.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:20:59.60#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.07:20:59.60#ibcon#ireg 7 cls_cnt 0 2006.285.07:20:59.60#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:20:59.72#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:20:59.72#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:20:59.72#ibcon#enter wrdev, iclass 32, count 0 2006.285.07:20:59.72#ibcon#first serial, iclass 32, count 0 2006.285.07:20:59.72#ibcon#enter sib2, iclass 32, count 0 2006.285.07:20:59.72#ibcon#flushed, iclass 32, count 0 2006.285.07:20:59.72#ibcon#about to write, iclass 32, count 0 2006.285.07:20:59.72#ibcon#wrote, iclass 32, count 0 2006.285.07:20:59.72#ibcon#about to read 3, iclass 32, count 0 2006.285.07:20:59.74#ibcon#read 3, iclass 32, count 0 2006.285.07:20:59.74#ibcon#about to read 4, iclass 32, count 0 2006.285.07:20:59.74#ibcon#read 4, iclass 32, count 0 2006.285.07:20:59.74#ibcon#about to read 5, iclass 32, count 0 2006.285.07:20:59.74#ibcon#read 5, iclass 32, count 0 2006.285.07:20:59.74#ibcon#about to read 6, iclass 32, count 0 2006.285.07:20:59.74#ibcon#read 6, iclass 32, count 0 2006.285.07:20:59.74#ibcon#end of sib2, iclass 32, count 0 2006.285.07:20:59.74#ibcon#*mode == 0, iclass 32, count 0 2006.285.07:20:59.74#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.07:20:59.74#ibcon#[25=USB\r\n] 2006.285.07:20:59.74#ibcon#*before write, iclass 32, count 0 2006.285.07:20:59.74#ibcon#enter sib2, iclass 32, count 0 2006.285.07:20:59.74#ibcon#flushed, iclass 32, count 0 2006.285.07:20:59.74#ibcon#about to write, iclass 32, count 0 2006.285.07:20:59.74#ibcon#wrote, iclass 32, count 0 2006.285.07:20:59.74#ibcon#about to read 3, iclass 32, count 0 2006.285.07:20:59.77#ibcon#read 3, iclass 32, count 0 2006.285.07:20:59.77#ibcon#about to read 4, iclass 32, count 0 2006.285.07:20:59.77#ibcon#read 4, iclass 32, count 0 2006.285.07:20:59.77#ibcon#about to read 5, iclass 32, count 0 2006.285.07:20:59.77#ibcon#read 5, iclass 32, count 0 2006.285.07:20:59.77#ibcon#about to read 6, iclass 32, count 0 2006.285.07:20:59.77#ibcon#read 6, iclass 32, count 0 2006.285.07:20:59.77#ibcon#end of sib2, iclass 32, count 0 2006.285.07:20:59.77#ibcon#*after write, iclass 32, count 0 2006.285.07:20:59.77#ibcon#*before return 0, iclass 32, count 0 2006.285.07:20:59.77#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:20:59.77#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:20:59.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.07:20:59.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.07:20:59.77$vck44/valo=2,534.99 2006.285.07:20:59.77#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.07:20:59.77#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.07:20:59.77#ibcon#ireg 17 cls_cnt 0 2006.285.07:20:59.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:20:59.77#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:20:59.77#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:20:59.77#ibcon#enter wrdev, iclass 34, count 0 2006.285.07:20:59.77#ibcon#first serial, iclass 34, count 0 2006.285.07:20:59.77#ibcon#enter sib2, iclass 34, count 0 2006.285.07:20:59.77#ibcon#flushed, iclass 34, count 0 2006.285.07:20:59.77#ibcon#about to write, iclass 34, count 0 2006.285.07:20:59.77#ibcon#wrote, iclass 34, count 0 2006.285.07:20:59.77#ibcon#about to read 3, iclass 34, count 0 2006.285.07:20:59.79#ibcon#read 3, iclass 34, count 0 2006.285.07:20:59.79#ibcon#about to read 4, iclass 34, count 0 2006.285.07:20:59.79#ibcon#read 4, iclass 34, count 0 2006.285.07:20:59.79#ibcon#about to read 5, iclass 34, count 0 2006.285.07:20:59.79#ibcon#read 5, iclass 34, count 0 2006.285.07:20:59.79#ibcon#about to read 6, iclass 34, count 0 2006.285.07:20:59.79#ibcon#read 6, iclass 34, count 0 2006.285.07:20:59.79#ibcon#end of sib2, iclass 34, count 0 2006.285.07:20:59.79#ibcon#*mode == 0, iclass 34, count 0 2006.285.07:20:59.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.07:20:59.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:20:59.79#ibcon#*before write, iclass 34, count 0 2006.285.07:20:59.79#ibcon#enter sib2, iclass 34, count 0 2006.285.07:20:59.79#ibcon#flushed, iclass 34, count 0 2006.285.07:20:59.79#ibcon#about to write, iclass 34, count 0 2006.285.07:20:59.79#ibcon#wrote, iclass 34, count 0 2006.285.07:20:59.79#ibcon#about to read 3, iclass 34, count 0 2006.285.07:20:59.83#ibcon#read 3, iclass 34, count 0 2006.285.07:20:59.83#ibcon#about to read 4, iclass 34, count 0 2006.285.07:20:59.83#ibcon#read 4, iclass 34, count 0 2006.285.07:20:59.83#ibcon#about to read 5, iclass 34, count 0 2006.285.07:20:59.83#ibcon#read 5, iclass 34, count 0 2006.285.07:20:59.83#ibcon#about to read 6, iclass 34, count 0 2006.285.07:20:59.83#ibcon#read 6, iclass 34, count 0 2006.285.07:20:59.83#ibcon#end of sib2, iclass 34, count 0 2006.285.07:20:59.83#ibcon#*after write, iclass 34, count 0 2006.285.07:20:59.83#ibcon#*before return 0, iclass 34, count 0 2006.285.07:20:59.83#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:20:59.83#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:20:59.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.07:20:59.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.07:20:59.83$vck44/va=2,6 2006.285.07:20:59.83#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.07:20:59.83#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.07:20:59.83#ibcon#ireg 11 cls_cnt 2 2006.285.07:20:59.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:20:59.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:20:59.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:20:59.89#ibcon#enter wrdev, iclass 36, count 2 2006.285.07:20:59.89#ibcon#first serial, iclass 36, count 2 2006.285.07:20:59.89#ibcon#enter sib2, iclass 36, count 2 2006.285.07:20:59.89#ibcon#flushed, iclass 36, count 2 2006.285.07:20:59.89#ibcon#about to write, iclass 36, count 2 2006.285.07:20:59.89#ibcon#wrote, iclass 36, count 2 2006.285.07:20:59.89#ibcon#about to read 3, iclass 36, count 2 2006.285.07:20:59.91#ibcon#read 3, iclass 36, count 2 2006.285.07:20:59.91#ibcon#about to read 4, iclass 36, count 2 2006.285.07:20:59.91#ibcon#read 4, iclass 36, count 2 2006.285.07:20:59.91#ibcon#about to read 5, iclass 36, count 2 2006.285.07:20:59.91#ibcon#read 5, iclass 36, count 2 2006.285.07:20:59.91#ibcon#about to read 6, iclass 36, count 2 2006.285.07:20:59.91#ibcon#read 6, iclass 36, count 2 2006.285.07:20:59.91#ibcon#end of sib2, iclass 36, count 2 2006.285.07:20:59.91#ibcon#*mode == 0, iclass 36, count 2 2006.285.07:20:59.91#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.07:20:59.91#ibcon#[25=AT02-06\r\n] 2006.285.07:20:59.91#ibcon#*before write, iclass 36, count 2 2006.285.07:20:59.91#ibcon#enter sib2, iclass 36, count 2 2006.285.07:20:59.91#ibcon#flushed, iclass 36, count 2 2006.285.07:20:59.91#ibcon#about to write, iclass 36, count 2 2006.285.07:20:59.91#ibcon#wrote, iclass 36, count 2 2006.285.07:20:59.91#ibcon#about to read 3, iclass 36, count 2 2006.285.07:20:59.94#ibcon#read 3, iclass 36, count 2 2006.285.07:20:59.94#ibcon#about to read 4, iclass 36, count 2 2006.285.07:20:59.94#ibcon#read 4, iclass 36, count 2 2006.285.07:20:59.94#ibcon#about to read 5, iclass 36, count 2 2006.285.07:20:59.94#ibcon#read 5, iclass 36, count 2 2006.285.07:20:59.94#ibcon#about to read 6, iclass 36, count 2 2006.285.07:20:59.94#ibcon#read 6, iclass 36, count 2 2006.285.07:20:59.94#ibcon#end of sib2, iclass 36, count 2 2006.285.07:20:59.94#ibcon#*after write, iclass 36, count 2 2006.285.07:20:59.94#ibcon#*before return 0, iclass 36, count 2 2006.285.07:20:59.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:20:59.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:20:59.94#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.07:20:59.94#ibcon#ireg 7 cls_cnt 0 2006.285.07:20:59.94#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:21:00.06#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:21:00.06#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:21:00.06#ibcon#enter wrdev, iclass 36, count 0 2006.285.07:21:00.06#ibcon#first serial, iclass 36, count 0 2006.285.07:21:00.06#ibcon#enter sib2, iclass 36, count 0 2006.285.07:21:00.06#ibcon#flushed, iclass 36, count 0 2006.285.07:21:00.06#ibcon#about to write, iclass 36, count 0 2006.285.07:21:00.06#ibcon#wrote, iclass 36, count 0 2006.285.07:21:00.06#ibcon#about to read 3, iclass 36, count 0 2006.285.07:21:00.10#ibcon#read 3, iclass 36, count 0 2006.285.07:21:00.10#ibcon#about to read 4, iclass 36, count 0 2006.285.07:21:00.10#ibcon#read 4, iclass 36, count 0 2006.285.07:21:00.10#ibcon#about to read 5, iclass 36, count 0 2006.285.07:21:00.10#ibcon#read 5, iclass 36, count 0 2006.285.07:21:00.10#ibcon#about to read 6, iclass 36, count 0 2006.285.07:21:00.10#ibcon#read 6, iclass 36, count 0 2006.285.07:21:00.10#ibcon#end of sib2, iclass 36, count 0 2006.285.07:21:00.10#ibcon#*mode == 0, iclass 36, count 0 2006.285.07:21:00.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.07:21:00.10#ibcon#[25=USB\r\n] 2006.285.07:21:00.10#ibcon#*before write, iclass 36, count 0 2006.285.07:21:00.10#ibcon#enter sib2, iclass 36, count 0 2006.285.07:21:00.10#ibcon#flushed, iclass 36, count 0 2006.285.07:21:00.10#ibcon#about to write, iclass 36, count 0 2006.285.07:21:00.10#ibcon#wrote, iclass 36, count 0 2006.285.07:21:00.10#ibcon#about to read 3, iclass 36, count 0 2006.285.07:21:00.13#ibcon#read 3, iclass 36, count 0 2006.285.07:21:00.13#ibcon#about to read 4, iclass 36, count 0 2006.285.07:21:00.13#ibcon#read 4, iclass 36, count 0 2006.285.07:21:00.13#ibcon#about to read 5, iclass 36, count 0 2006.285.07:21:00.13#ibcon#read 5, iclass 36, count 0 2006.285.07:21:00.13#ibcon#about to read 6, iclass 36, count 0 2006.285.07:21:00.13#ibcon#read 6, iclass 36, count 0 2006.285.07:21:00.13#ibcon#end of sib2, iclass 36, count 0 2006.285.07:21:00.13#ibcon#*after write, iclass 36, count 0 2006.285.07:21:00.13#ibcon#*before return 0, iclass 36, count 0 2006.285.07:21:00.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:21:00.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:21:00.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.07:21:00.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.07:21:00.13$vck44/valo=3,564.99 2006.285.07:21:00.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.07:21:00.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.07:21:00.13#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:00.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:21:00.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:21:00.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:21:00.13#ibcon#enter wrdev, iclass 38, count 0 2006.285.07:21:00.13#ibcon#first serial, iclass 38, count 0 2006.285.07:21:00.13#ibcon#enter sib2, iclass 38, count 0 2006.285.07:21:00.13#ibcon#flushed, iclass 38, count 0 2006.285.07:21:00.13#ibcon#about to write, iclass 38, count 0 2006.285.07:21:00.13#ibcon#wrote, iclass 38, count 0 2006.285.07:21:00.13#ibcon#about to read 3, iclass 38, count 0 2006.285.07:21:00.15#ibcon#read 3, iclass 38, count 0 2006.285.07:21:00.15#ibcon#about to read 4, iclass 38, count 0 2006.285.07:21:00.15#ibcon#read 4, iclass 38, count 0 2006.285.07:21:00.15#ibcon#about to read 5, iclass 38, count 0 2006.285.07:21:00.15#ibcon#read 5, iclass 38, count 0 2006.285.07:21:00.15#ibcon#about to read 6, iclass 38, count 0 2006.285.07:21:00.15#ibcon#read 6, iclass 38, count 0 2006.285.07:21:00.15#ibcon#end of sib2, iclass 38, count 0 2006.285.07:21:00.15#ibcon#*mode == 0, iclass 38, count 0 2006.285.07:21:00.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.07:21:00.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:21:00.15#ibcon#*before write, iclass 38, count 0 2006.285.07:21:00.15#ibcon#enter sib2, iclass 38, count 0 2006.285.07:21:00.15#ibcon#flushed, iclass 38, count 0 2006.285.07:21:00.15#ibcon#about to write, iclass 38, count 0 2006.285.07:21:00.15#ibcon#wrote, iclass 38, count 0 2006.285.07:21:00.15#ibcon#about to read 3, iclass 38, count 0 2006.285.07:21:00.19#ibcon#read 3, iclass 38, count 0 2006.285.07:21:00.19#ibcon#about to read 4, iclass 38, count 0 2006.285.07:21:00.19#ibcon#read 4, iclass 38, count 0 2006.285.07:21:00.19#ibcon#about to read 5, iclass 38, count 0 2006.285.07:21:00.19#ibcon#read 5, iclass 38, count 0 2006.285.07:21:00.19#ibcon#about to read 6, iclass 38, count 0 2006.285.07:21:00.19#ibcon#read 6, iclass 38, count 0 2006.285.07:21:00.19#ibcon#end of sib2, iclass 38, count 0 2006.285.07:21:00.19#ibcon#*after write, iclass 38, count 0 2006.285.07:21:00.19#ibcon#*before return 0, iclass 38, count 0 2006.285.07:21:00.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:21:00.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:21:00.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.07:21:00.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.07:21:00.19$vck44/va=3,7 2006.285.07:21:00.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.07:21:00.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.07:21:00.19#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:00.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:21:00.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:21:00.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:21:00.25#ibcon#enter wrdev, iclass 40, count 2 2006.285.07:21:00.25#ibcon#first serial, iclass 40, count 2 2006.285.07:21:00.25#ibcon#enter sib2, iclass 40, count 2 2006.285.07:21:00.25#ibcon#flushed, iclass 40, count 2 2006.285.07:21:00.25#ibcon#about to write, iclass 40, count 2 2006.285.07:21:00.25#ibcon#wrote, iclass 40, count 2 2006.285.07:21:00.25#ibcon#about to read 3, iclass 40, count 2 2006.285.07:21:00.27#ibcon#read 3, iclass 40, count 2 2006.285.07:21:00.27#ibcon#about to read 4, iclass 40, count 2 2006.285.07:21:00.27#ibcon#read 4, iclass 40, count 2 2006.285.07:21:00.27#ibcon#about to read 5, iclass 40, count 2 2006.285.07:21:00.27#ibcon#read 5, iclass 40, count 2 2006.285.07:21:00.27#ibcon#about to read 6, iclass 40, count 2 2006.285.07:21:00.27#ibcon#read 6, iclass 40, count 2 2006.285.07:21:00.27#ibcon#end of sib2, iclass 40, count 2 2006.285.07:21:00.27#ibcon#*mode == 0, iclass 40, count 2 2006.285.07:21:00.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.07:21:00.27#ibcon#[25=AT03-07\r\n] 2006.285.07:21:00.27#ibcon#*before write, iclass 40, count 2 2006.285.07:21:00.27#ibcon#enter sib2, iclass 40, count 2 2006.285.07:21:00.27#ibcon#flushed, iclass 40, count 2 2006.285.07:21:00.27#ibcon#about to write, iclass 40, count 2 2006.285.07:21:00.27#ibcon#wrote, iclass 40, count 2 2006.285.07:21:00.27#ibcon#about to read 3, iclass 40, count 2 2006.285.07:21:00.30#ibcon#read 3, iclass 40, count 2 2006.285.07:21:00.30#ibcon#about to read 4, iclass 40, count 2 2006.285.07:21:00.30#ibcon#read 4, iclass 40, count 2 2006.285.07:21:00.30#ibcon#about to read 5, iclass 40, count 2 2006.285.07:21:00.30#ibcon#read 5, iclass 40, count 2 2006.285.07:21:00.30#ibcon#about to read 6, iclass 40, count 2 2006.285.07:21:00.30#ibcon#read 6, iclass 40, count 2 2006.285.07:21:00.30#ibcon#end of sib2, iclass 40, count 2 2006.285.07:21:00.30#ibcon#*after write, iclass 40, count 2 2006.285.07:21:00.30#ibcon#*before return 0, iclass 40, count 2 2006.285.07:21:00.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:21:00.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:21:00.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.07:21:00.30#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:00.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:21:00.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:21:00.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:21:00.42#ibcon#enter wrdev, iclass 40, count 0 2006.285.07:21:00.42#ibcon#first serial, iclass 40, count 0 2006.285.07:21:00.42#ibcon#enter sib2, iclass 40, count 0 2006.285.07:21:00.42#ibcon#flushed, iclass 40, count 0 2006.285.07:21:00.42#ibcon#about to write, iclass 40, count 0 2006.285.07:21:00.42#ibcon#wrote, iclass 40, count 0 2006.285.07:21:00.42#ibcon#about to read 3, iclass 40, count 0 2006.285.07:21:00.44#ibcon#read 3, iclass 40, count 0 2006.285.07:21:00.44#ibcon#about to read 4, iclass 40, count 0 2006.285.07:21:00.44#ibcon#read 4, iclass 40, count 0 2006.285.07:21:00.44#ibcon#about to read 5, iclass 40, count 0 2006.285.07:21:00.44#ibcon#read 5, iclass 40, count 0 2006.285.07:21:00.44#ibcon#about to read 6, iclass 40, count 0 2006.285.07:21:00.44#ibcon#read 6, iclass 40, count 0 2006.285.07:21:00.44#ibcon#end of sib2, iclass 40, count 0 2006.285.07:21:00.44#ibcon#*mode == 0, iclass 40, count 0 2006.285.07:21:00.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.07:21:00.44#ibcon#[25=USB\r\n] 2006.285.07:21:00.44#ibcon#*before write, iclass 40, count 0 2006.285.07:21:00.44#ibcon#enter sib2, iclass 40, count 0 2006.285.07:21:00.44#ibcon#flushed, iclass 40, count 0 2006.285.07:21:00.44#ibcon#about to write, iclass 40, count 0 2006.285.07:21:00.44#ibcon#wrote, iclass 40, count 0 2006.285.07:21:00.44#ibcon#about to read 3, iclass 40, count 0 2006.285.07:21:00.47#ibcon#read 3, iclass 40, count 0 2006.285.07:21:00.47#ibcon#about to read 4, iclass 40, count 0 2006.285.07:21:00.47#ibcon#read 4, iclass 40, count 0 2006.285.07:21:00.47#ibcon#about to read 5, iclass 40, count 0 2006.285.07:21:00.47#ibcon#read 5, iclass 40, count 0 2006.285.07:21:00.47#ibcon#about to read 6, iclass 40, count 0 2006.285.07:21:00.47#ibcon#read 6, iclass 40, count 0 2006.285.07:21:00.47#ibcon#end of sib2, iclass 40, count 0 2006.285.07:21:00.47#ibcon#*after write, iclass 40, count 0 2006.285.07:21:00.47#ibcon#*before return 0, iclass 40, count 0 2006.285.07:21:00.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:21:00.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:21:00.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.07:21:00.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.07:21:00.47$vck44/valo=4,624.99 2006.285.07:21:00.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.07:21:00.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.07:21:00.47#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:00.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:21:00.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:21:00.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:21:00.47#ibcon#enter wrdev, iclass 4, count 0 2006.285.07:21:00.47#ibcon#first serial, iclass 4, count 0 2006.285.07:21:00.47#ibcon#enter sib2, iclass 4, count 0 2006.285.07:21:00.47#ibcon#flushed, iclass 4, count 0 2006.285.07:21:00.47#ibcon#about to write, iclass 4, count 0 2006.285.07:21:00.47#ibcon#wrote, iclass 4, count 0 2006.285.07:21:00.47#ibcon#about to read 3, iclass 4, count 0 2006.285.07:21:00.49#ibcon#read 3, iclass 4, count 0 2006.285.07:21:00.49#ibcon#about to read 4, iclass 4, count 0 2006.285.07:21:00.49#ibcon#read 4, iclass 4, count 0 2006.285.07:21:00.49#ibcon#about to read 5, iclass 4, count 0 2006.285.07:21:00.49#ibcon#read 5, iclass 4, count 0 2006.285.07:21:00.49#ibcon#about to read 6, iclass 4, count 0 2006.285.07:21:00.49#ibcon#read 6, iclass 4, count 0 2006.285.07:21:00.49#ibcon#end of sib2, iclass 4, count 0 2006.285.07:21:00.49#ibcon#*mode == 0, iclass 4, count 0 2006.285.07:21:00.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.07:21:00.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:21:00.49#ibcon#*before write, iclass 4, count 0 2006.285.07:21:00.49#ibcon#enter sib2, iclass 4, count 0 2006.285.07:21:00.49#ibcon#flushed, iclass 4, count 0 2006.285.07:21:00.49#ibcon#about to write, iclass 4, count 0 2006.285.07:21:00.49#ibcon#wrote, iclass 4, count 0 2006.285.07:21:00.49#ibcon#about to read 3, iclass 4, count 0 2006.285.07:21:00.53#ibcon#read 3, iclass 4, count 0 2006.285.07:21:00.53#ibcon#about to read 4, iclass 4, count 0 2006.285.07:21:00.53#ibcon#read 4, iclass 4, count 0 2006.285.07:21:00.53#ibcon#about to read 5, iclass 4, count 0 2006.285.07:21:00.53#ibcon#read 5, iclass 4, count 0 2006.285.07:21:00.53#ibcon#about to read 6, iclass 4, count 0 2006.285.07:21:00.53#ibcon#read 6, iclass 4, count 0 2006.285.07:21:00.53#ibcon#end of sib2, iclass 4, count 0 2006.285.07:21:00.53#ibcon#*after write, iclass 4, count 0 2006.285.07:21:00.53#ibcon#*before return 0, iclass 4, count 0 2006.285.07:21:00.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:21:00.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:21:00.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.07:21:00.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.07:21:00.53$vck44/va=4,6 2006.285.07:21:00.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.07:21:00.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.07:21:00.53#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:00.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:21:00.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:21:00.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:21:00.59#ibcon#enter wrdev, iclass 6, count 2 2006.285.07:21:00.59#ibcon#first serial, iclass 6, count 2 2006.285.07:21:00.59#ibcon#enter sib2, iclass 6, count 2 2006.285.07:21:00.59#ibcon#flushed, iclass 6, count 2 2006.285.07:21:00.59#ibcon#about to write, iclass 6, count 2 2006.285.07:21:00.59#ibcon#wrote, iclass 6, count 2 2006.285.07:21:00.59#ibcon#about to read 3, iclass 6, count 2 2006.285.07:21:00.61#ibcon#read 3, iclass 6, count 2 2006.285.07:21:00.61#ibcon#about to read 4, iclass 6, count 2 2006.285.07:21:00.61#ibcon#read 4, iclass 6, count 2 2006.285.07:21:00.61#ibcon#about to read 5, iclass 6, count 2 2006.285.07:21:00.61#ibcon#read 5, iclass 6, count 2 2006.285.07:21:00.61#ibcon#about to read 6, iclass 6, count 2 2006.285.07:21:00.61#ibcon#read 6, iclass 6, count 2 2006.285.07:21:00.61#ibcon#end of sib2, iclass 6, count 2 2006.285.07:21:00.61#ibcon#*mode == 0, iclass 6, count 2 2006.285.07:21:00.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.07:21:00.61#ibcon#[25=AT04-06\r\n] 2006.285.07:21:00.61#ibcon#*before write, iclass 6, count 2 2006.285.07:21:00.61#ibcon#enter sib2, iclass 6, count 2 2006.285.07:21:00.61#ibcon#flushed, iclass 6, count 2 2006.285.07:21:00.61#ibcon#about to write, iclass 6, count 2 2006.285.07:21:00.61#ibcon#wrote, iclass 6, count 2 2006.285.07:21:00.61#ibcon#about to read 3, iclass 6, count 2 2006.285.07:21:00.64#ibcon#read 3, iclass 6, count 2 2006.285.07:21:00.64#ibcon#about to read 4, iclass 6, count 2 2006.285.07:21:00.64#ibcon#read 4, iclass 6, count 2 2006.285.07:21:00.64#ibcon#about to read 5, iclass 6, count 2 2006.285.07:21:00.64#ibcon#read 5, iclass 6, count 2 2006.285.07:21:00.64#ibcon#about to read 6, iclass 6, count 2 2006.285.07:21:00.64#ibcon#read 6, iclass 6, count 2 2006.285.07:21:00.64#ibcon#end of sib2, iclass 6, count 2 2006.285.07:21:00.64#ibcon#*after write, iclass 6, count 2 2006.285.07:21:00.64#ibcon#*before return 0, iclass 6, count 2 2006.285.07:21:00.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:21:00.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:21:00.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.07:21:00.64#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:00.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:21:00.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:21:00.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:21:00.76#ibcon#enter wrdev, iclass 6, count 0 2006.285.07:21:00.76#ibcon#first serial, iclass 6, count 0 2006.285.07:21:00.76#ibcon#enter sib2, iclass 6, count 0 2006.285.07:21:00.76#ibcon#flushed, iclass 6, count 0 2006.285.07:21:00.76#ibcon#about to write, iclass 6, count 0 2006.285.07:21:00.76#ibcon#wrote, iclass 6, count 0 2006.285.07:21:00.76#ibcon#about to read 3, iclass 6, count 0 2006.285.07:21:00.77#abcon#<5=/05 3.1 6.2 23.90 761014.3\r\n> 2006.285.07:21:00.78#ibcon#read 3, iclass 6, count 0 2006.285.07:21:00.78#ibcon#about to read 4, iclass 6, count 0 2006.285.07:21:00.78#ibcon#read 4, iclass 6, count 0 2006.285.07:21:00.78#ibcon#about to read 5, iclass 6, count 0 2006.285.07:21:00.78#ibcon#read 5, iclass 6, count 0 2006.285.07:21:00.78#ibcon#about to read 6, iclass 6, count 0 2006.285.07:21:00.78#ibcon#read 6, iclass 6, count 0 2006.285.07:21:00.78#ibcon#end of sib2, iclass 6, count 0 2006.285.07:21:00.78#ibcon#*mode == 0, iclass 6, count 0 2006.285.07:21:00.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.07:21:00.78#ibcon#[25=USB\r\n] 2006.285.07:21:00.78#ibcon#*before write, iclass 6, count 0 2006.285.07:21:00.78#ibcon#enter sib2, iclass 6, count 0 2006.285.07:21:00.78#ibcon#flushed, iclass 6, count 0 2006.285.07:21:00.78#ibcon#about to write, iclass 6, count 0 2006.285.07:21:00.78#ibcon#wrote, iclass 6, count 0 2006.285.07:21:00.78#ibcon#about to read 3, iclass 6, count 0 2006.285.07:21:00.79#abcon#{5=INTERFACE CLEAR} 2006.285.07:21:00.81#ibcon#read 3, iclass 6, count 0 2006.285.07:21:00.81#ibcon#about to read 4, iclass 6, count 0 2006.285.07:21:00.81#ibcon#read 4, iclass 6, count 0 2006.285.07:21:00.81#ibcon#about to read 5, iclass 6, count 0 2006.285.07:21:00.81#ibcon#read 5, iclass 6, count 0 2006.285.07:21:00.81#ibcon#about to read 6, iclass 6, count 0 2006.285.07:21:00.81#ibcon#read 6, iclass 6, count 0 2006.285.07:21:00.81#ibcon#end of sib2, iclass 6, count 0 2006.285.07:21:00.81#ibcon#*after write, iclass 6, count 0 2006.285.07:21:00.81#ibcon#*before return 0, iclass 6, count 0 2006.285.07:21:00.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:21:00.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:21:00.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.07:21:00.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.07:21:00.81$vck44/valo=5,734.99 2006.285.07:21:00.81#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.07:21:00.81#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.07:21:00.81#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:00.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:21:00.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:21:00.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:21:00.81#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:21:00.81#ibcon#first serial, iclass 13, count 0 2006.285.07:21:00.81#ibcon#enter sib2, iclass 13, count 0 2006.285.07:21:00.81#ibcon#flushed, iclass 13, count 0 2006.285.07:21:00.81#ibcon#about to write, iclass 13, count 0 2006.285.07:21:00.81#ibcon#wrote, iclass 13, count 0 2006.285.07:21:00.81#ibcon#about to read 3, iclass 13, count 0 2006.285.07:21:00.83#ibcon#read 3, iclass 13, count 0 2006.285.07:21:00.83#ibcon#about to read 4, iclass 13, count 0 2006.285.07:21:00.83#ibcon#read 4, iclass 13, count 0 2006.285.07:21:00.83#ibcon#about to read 5, iclass 13, count 0 2006.285.07:21:00.83#ibcon#read 5, iclass 13, count 0 2006.285.07:21:00.83#ibcon#about to read 6, iclass 13, count 0 2006.285.07:21:00.83#ibcon#read 6, iclass 13, count 0 2006.285.07:21:00.83#ibcon#end of sib2, iclass 13, count 0 2006.285.07:21:00.83#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:21:00.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:21:00.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:21:00.83#ibcon#*before write, iclass 13, count 0 2006.285.07:21:00.83#ibcon#enter sib2, iclass 13, count 0 2006.285.07:21:00.83#ibcon#flushed, iclass 13, count 0 2006.285.07:21:00.83#ibcon#about to write, iclass 13, count 0 2006.285.07:21:00.83#ibcon#wrote, iclass 13, count 0 2006.285.07:21:00.83#ibcon#about to read 3, iclass 13, count 0 2006.285.07:21:00.85#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:21:00.87#ibcon#read 3, iclass 13, count 0 2006.285.07:21:00.87#ibcon#about to read 4, iclass 13, count 0 2006.285.07:21:00.87#ibcon#read 4, iclass 13, count 0 2006.285.07:21:00.87#ibcon#about to read 5, iclass 13, count 0 2006.285.07:21:00.87#ibcon#read 5, iclass 13, count 0 2006.285.07:21:00.87#ibcon#about to read 6, iclass 13, count 0 2006.285.07:21:00.87#ibcon#read 6, iclass 13, count 0 2006.285.07:21:00.87#ibcon#end of sib2, iclass 13, count 0 2006.285.07:21:00.87#ibcon#*after write, iclass 13, count 0 2006.285.07:21:00.87#ibcon#*before return 0, iclass 13, count 0 2006.285.07:21:00.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:21:00.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:21:00.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:21:00.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:21:00.87$vck44/va=5,3 2006.285.07:21:00.87#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.07:21:00.87#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.07:21:00.87#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:00.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:21:00.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:21:00.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:21:00.93#ibcon#enter wrdev, iclass 16, count 2 2006.285.07:21:00.93#ibcon#first serial, iclass 16, count 2 2006.285.07:21:00.93#ibcon#enter sib2, iclass 16, count 2 2006.285.07:21:00.93#ibcon#flushed, iclass 16, count 2 2006.285.07:21:00.93#ibcon#about to write, iclass 16, count 2 2006.285.07:21:00.93#ibcon#wrote, iclass 16, count 2 2006.285.07:21:00.93#ibcon#about to read 3, iclass 16, count 2 2006.285.07:21:00.95#ibcon#read 3, iclass 16, count 2 2006.285.07:21:00.95#ibcon#about to read 4, iclass 16, count 2 2006.285.07:21:00.95#ibcon#read 4, iclass 16, count 2 2006.285.07:21:00.95#ibcon#about to read 5, iclass 16, count 2 2006.285.07:21:00.95#ibcon#read 5, iclass 16, count 2 2006.285.07:21:00.95#ibcon#about to read 6, iclass 16, count 2 2006.285.07:21:00.95#ibcon#read 6, iclass 16, count 2 2006.285.07:21:00.95#ibcon#end of sib2, iclass 16, count 2 2006.285.07:21:00.95#ibcon#*mode == 0, iclass 16, count 2 2006.285.07:21:00.95#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.07:21:00.95#ibcon#[25=AT05-03\r\n] 2006.285.07:21:00.95#ibcon#*before write, iclass 16, count 2 2006.285.07:21:00.95#ibcon#enter sib2, iclass 16, count 2 2006.285.07:21:00.95#ibcon#flushed, iclass 16, count 2 2006.285.07:21:00.95#ibcon#about to write, iclass 16, count 2 2006.285.07:21:00.95#ibcon#wrote, iclass 16, count 2 2006.285.07:21:00.95#ibcon#about to read 3, iclass 16, count 2 2006.285.07:21:00.98#ibcon#read 3, iclass 16, count 2 2006.285.07:21:00.98#ibcon#about to read 4, iclass 16, count 2 2006.285.07:21:00.98#ibcon#read 4, iclass 16, count 2 2006.285.07:21:00.98#ibcon#about to read 5, iclass 16, count 2 2006.285.07:21:00.98#ibcon#read 5, iclass 16, count 2 2006.285.07:21:00.98#ibcon#about to read 6, iclass 16, count 2 2006.285.07:21:00.98#ibcon#read 6, iclass 16, count 2 2006.285.07:21:00.98#ibcon#end of sib2, iclass 16, count 2 2006.285.07:21:00.98#ibcon#*after write, iclass 16, count 2 2006.285.07:21:00.98#ibcon#*before return 0, iclass 16, count 2 2006.285.07:21:00.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:21:00.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:21:00.98#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.07:21:00.98#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:00.98#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:21:01.10#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:21:01.10#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:21:01.10#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:21:01.10#ibcon#first serial, iclass 16, count 0 2006.285.07:21:01.10#ibcon#enter sib2, iclass 16, count 0 2006.285.07:21:01.10#ibcon#flushed, iclass 16, count 0 2006.285.07:21:01.10#ibcon#about to write, iclass 16, count 0 2006.285.07:21:01.10#ibcon#wrote, iclass 16, count 0 2006.285.07:21:01.10#ibcon#about to read 3, iclass 16, count 0 2006.285.07:21:01.12#ibcon#read 3, iclass 16, count 0 2006.285.07:21:01.12#ibcon#about to read 4, iclass 16, count 0 2006.285.07:21:01.12#ibcon#read 4, iclass 16, count 0 2006.285.07:21:01.12#ibcon#about to read 5, iclass 16, count 0 2006.285.07:21:01.12#ibcon#read 5, iclass 16, count 0 2006.285.07:21:01.12#ibcon#about to read 6, iclass 16, count 0 2006.285.07:21:01.12#ibcon#read 6, iclass 16, count 0 2006.285.07:21:01.12#ibcon#end of sib2, iclass 16, count 0 2006.285.07:21:01.12#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:21:01.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:21:01.12#ibcon#[25=USB\r\n] 2006.285.07:21:01.12#ibcon#*before write, iclass 16, count 0 2006.285.07:21:01.12#ibcon#enter sib2, iclass 16, count 0 2006.285.07:21:01.12#ibcon#flushed, iclass 16, count 0 2006.285.07:21:01.12#ibcon#about to write, iclass 16, count 0 2006.285.07:21:01.12#ibcon#wrote, iclass 16, count 0 2006.285.07:21:01.12#ibcon#about to read 3, iclass 16, count 0 2006.285.07:21:01.15#ibcon#read 3, iclass 16, count 0 2006.285.07:21:01.15#ibcon#about to read 4, iclass 16, count 0 2006.285.07:21:01.15#ibcon#read 4, iclass 16, count 0 2006.285.07:21:01.15#ibcon#about to read 5, iclass 16, count 0 2006.285.07:21:01.15#ibcon#read 5, iclass 16, count 0 2006.285.07:21:01.15#ibcon#about to read 6, iclass 16, count 0 2006.285.07:21:01.15#ibcon#read 6, iclass 16, count 0 2006.285.07:21:01.15#ibcon#end of sib2, iclass 16, count 0 2006.285.07:21:01.15#ibcon#*after write, iclass 16, count 0 2006.285.07:21:01.15#ibcon#*before return 0, iclass 16, count 0 2006.285.07:21:01.15#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:21:01.15#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:21:01.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:21:01.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:21:01.15$vck44/valo=6,814.99 2006.285.07:21:01.15#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.07:21:01.15#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.07:21:01.15#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:01.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:21:01.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:21:01.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:21:01.15#ibcon#enter wrdev, iclass 18, count 0 2006.285.07:21:01.15#ibcon#first serial, iclass 18, count 0 2006.285.07:21:01.15#ibcon#enter sib2, iclass 18, count 0 2006.285.07:21:01.15#ibcon#flushed, iclass 18, count 0 2006.285.07:21:01.15#ibcon#about to write, iclass 18, count 0 2006.285.07:21:01.15#ibcon#wrote, iclass 18, count 0 2006.285.07:21:01.15#ibcon#about to read 3, iclass 18, count 0 2006.285.07:21:01.17#ibcon#read 3, iclass 18, count 0 2006.285.07:21:01.17#ibcon#about to read 4, iclass 18, count 0 2006.285.07:21:01.17#ibcon#read 4, iclass 18, count 0 2006.285.07:21:01.17#ibcon#about to read 5, iclass 18, count 0 2006.285.07:21:01.17#ibcon#read 5, iclass 18, count 0 2006.285.07:21:01.17#ibcon#about to read 6, iclass 18, count 0 2006.285.07:21:01.17#ibcon#read 6, iclass 18, count 0 2006.285.07:21:01.17#ibcon#end of sib2, iclass 18, count 0 2006.285.07:21:01.17#ibcon#*mode == 0, iclass 18, count 0 2006.285.07:21:01.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.07:21:01.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:21:01.17#ibcon#*before write, iclass 18, count 0 2006.285.07:21:01.17#ibcon#enter sib2, iclass 18, count 0 2006.285.07:21:01.17#ibcon#flushed, iclass 18, count 0 2006.285.07:21:01.17#ibcon#about to write, iclass 18, count 0 2006.285.07:21:01.17#ibcon#wrote, iclass 18, count 0 2006.285.07:21:01.17#ibcon#about to read 3, iclass 18, count 0 2006.285.07:21:01.21#ibcon#read 3, iclass 18, count 0 2006.285.07:21:01.21#ibcon#about to read 4, iclass 18, count 0 2006.285.07:21:01.21#ibcon#read 4, iclass 18, count 0 2006.285.07:21:01.21#ibcon#about to read 5, iclass 18, count 0 2006.285.07:21:01.21#ibcon#read 5, iclass 18, count 0 2006.285.07:21:01.21#ibcon#about to read 6, iclass 18, count 0 2006.285.07:21:01.21#ibcon#read 6, iclass 18, count 0 2006.285.07:21:01.21#ibcon#end of sib2, iclass 18, count 0 2006.285.07:21:01.21#ibcon#*after write, iclass 18, count 0 2006.285.07:21:01.21#ibcon#*before return 0, iclass 18, count 0 2006.285.07:21:01.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:21:01.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:21:01.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.07:21:01.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.07:21:01.21$vck44/va=6,4 2006.285.07:21:01.21#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.07:21:01.21#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.07:21:01.21#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:01.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:21:01.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:21:01.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:21:01.27#ibcon#enter wrdev, iclass 20, count 2 2006.285.07:21:01.27#ibcon#first serial, iclass 20, count 2 2006.285.07:21:01.27#ibcon#enter sib2, iclass 20, count 2 2006.285.07:21:01.27#ibcon#flushed, iclass 20, count 2 2006.285.07:21:01.27#ibcon#about to write, iclass 20, count 2 2006.285.07:21:01.27#ibcon#wrote, iclass 20, count 2 2006.285.07:21:01.27#ibcon#about to read 3, iclass 20, count 2 2006.285.07:21:01.29#ibcon#read 3, iclass 20, count 2 2006.285.07:21:01.29#ibcon#about to read 4, iclass 20, count 2 2006.285.07:21:01.29#ibcon#read 4, iclass 20, count 2 2006.285.07:21:01.29#ibcon#about to read 5, iclass 20, count 2 2006.285.07:21:01.29#ibcon#read 5, iclass 20, count 2 2006.285.07:21:01.29#ibcon#about to read 6, iclass 20, count 2 2006.285.07:21:01.29#ibcon#read 6, iclass 20, count 2 2006.285.07:21:01.29#ibcon#end of sib2, iclass 20, count 2 2006.285.07:21:01.29#ibcon#*mode == 0, iclass 20, count 2 2006.285.07:21:01.29#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.07:21:01.29#ibcon#[25=AT06-04\r\n] 2006.285.07:21:01.29#ibcon#*before write, iclass 20, count 2 2006.285.07:21:01.29#ibcon#enter sib2, iclass 20, count 2 2006.285.07:21:01.29#ibcon#flushed, iclass 20, count 2 2006.285.07:21:01.29#ibcon#about to write, iclass 20, count 2 2006.285.07:21:01.29#ibcon#wrote, iclass 20, count 2 2006.285.07:21:01.29#ibcon#about to read 3, iclass 20, count 2 2006.285.07:21:01.32#ibcon#read 3, iclass 20, count 2 2006.285.07:21:01.32#ibcon#about to read 4, iclass 20, count 2 2006.285.07:21:01.32#ibcon#read 4, iclass 20, count 2 2006.285.07:21:01.32#ibcon#about to read 5, iclass 20, count 2 2006.285.07:21:01.32#ibcon#read 5, iclass 20, count 2 2006.285.07:21:01.32#ibcon#about to read 6, iclass 20, count 2 2006.285.07:21:01.32#ibcon#read 6, iclass 20, count 2 2006.285.07:21:01.32#ibcon#end of sib2, iclass 20, count 2 2006.285.07:21:01.32#ibcon#*after write, iclass 20, count 2 2006.285.07:21:01.32#ibcon#*before return 0, iclass 20, count 2 2006.285.07:21:01.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:21:01.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:21:01.32#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.07:21:01.32#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:01.32#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:21:01.44#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:21:01.44#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:21:01.44#ibcon#enter wrdev, iclass 20, count 0 2006.285.07:21:01.44#ibcon#first serial, iclass 20, count 0 2006.285.07:21:01.44#ibcon#enter sib2, iclass 20, count 0 2006.285.07:21:01.44#ibcon#flushed, iclass 20, count 0 2006.285.07:21:01.44#ibcon#about to write, iclass 20, count 0 2006.285.07:21:01.44#ibcon#wrote, iclass 20, count 0 2006.285.07:21:01.44#ibcon#about to read 3, iclass 20, count 0 2006.285.07:21:01.46#ibcon#read 3, iclass 20, count 0 2006.285.07:21:01.46#ibcon#about to read 4, iclass 20, count 0 2006.285.07:21:01.46#ibcon#read 4, iclass 20, count 0 2006.285.07:21:01.46#ibcon#about to read 5, iclass 20, count 0 2006.285.07:21:01.46#ibcon#read 5, iclass 20, count 0 2006.285.07:21:01.46#ibcon#about to read 6, iclass 20, count 0 2006.285.07:21:01.46#ibcon#read 6, iclass 20, count 0 2006.285.07:21:01.46#ibcon#end of sib2, iclass 20, count 0 2006.285.07:21:01.46#ibcon#*mode == 0, iclass 20, count 0 2006.285.07:21:01.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.07:21:01.46#ibcon#[25=USB\r\n] 2006.285.07:21:01.46#ibcon#*before write, iclass 20, count 0 2006.285.07:21:01.46#ibcon#enter sib2, iclass 20, count 0 2006.285.07:21:01.46#ibcon#flushed, iclass 20, count 0 2006.285.07:21:01.46#ibcon#about to write, iclass 20, count 0 2006.285.07:21:01.46#ibcon#wrote, iclass 20, count 0 2006.285.07:21:01.46#ibcon#about to read 3, iclass 20, count 0 2006.285.07:21:01.49#ibcon#read 3, iclass 20, count 0 2006.285.07:21:01.49#ibcon#about to read 4, iclass 20, count 0 2006.285.07:21:01.49#ibcon#read 4, iclass 20, count 0 2006.285.07:21:01.49#ibcon#about to read 5, iclass 20, count 0 2006.285.07:21:01.49#ibcon#read 5, iclass 20, count 0 2006.285.07:21:01.49#ibcon#about to read 6, iclass 20, count 0 2006.285.07:21:01.49#ibcon#read 6, iclass 20, count 0 2006.285.07:21:01.49#ibcon#end of sib2, iclass 20, count 0 2006.285.07:21:01.49#ibcon#*after write, iclass 20, count 0 2006.285.07:21:01.49#ibcon#*before return 0, iclass 20, count 0 2006.285.07:21:01.49#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:21:01.49#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:21:01.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.07:21:01.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.07:21:01.49$vck44/valo=7,864.99 2006.285.07:21:01.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.07:21:01.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.07:21:01.49#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:01.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:21:01.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:21:01.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:21:01.49#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:21:01.49#ibcon#first serial, iclass 22, count 0 2006.285.07:21:01.49#ibcon#enter sib2, iclass 22, count 0 2006.285.07:21:01.49#ibcon#flushed, iclass 22, count 0 2006.285.07:21:01.49#ibcon#about to write, iclass 22, count 0 2006.285.07:21:01.49#ibcon#wrote, iclass 22, count 0 2006.285.07:21:01.49#ibcon#about to read 3, iclass 22, count 0 2006.285.07:21:01.51#ibcon#read 3, iclass 22, count 0 2006.285.07:21:01.51#ibcon#about to read 4, iclass 22, count 0 2006.285.07:21:01.51#ibcon#read 4, iclass 22, count 0 2006.285.07:21:01.51#ibcon#about to read 5, iclass 22, count 0 2006.285.07:21:01.51#ibcon#read 5, iclass 22, count 0 2006.285.07:21:01.51#ibcon#about to read 6, iclass 22, count 0 2006.285.07:21:01.51#ibcon#read 6, iclass 22, count 0 2006.285.07:21:01.51#ibcon#end of sib2, iclass 22, count 0 2006.285.07:21:01.51#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:21:01.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:21:01.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:21:01.51#ibcon#*before write, iclass 22, count 0 2006.285.07:21:01.51#ibcon#enter sib2, iclass 22, count 0 2006.285.07:21:01.51#ibcon#flushed, iclass 22, count 0 2006.285.07:21:01.51#ibcon#about to write, iclass 22, count 0 2006.285.07:21:01.51#ibcon#wrote, iclass 22, count 0 2006.285.07:21:01.51#ibcon#about to read 3, iclass 22, count 0 2006.285.07:21:01.55#ibcon#read 3, iclass 22, count 0 2006.285.07:21:01.55#ibcon#about to read 4, iclass 22, count 0 2006.285.07:21:01.55#ibcon#read 4, iclass 22, count 0 2006.285.07:21:01.55#ibcon#about to read 5, iclass 22, count 0 2006.285.07:21:01.55#ibcon#read 5, iclass 22, count 0 2006.285.07:21:01.55#ibcon#about to read 6, iclass 22, count 0 2006.285.07:21:01.55#ibcon#read 6, iclass 22, count 0 2006.285.07:21:01.55#ibcon#end of sib2, iclass 22, count 0 2006.285.07:21:01.55#ibcon#*after write, iclass 22, count 0 2006.285.07:21:01.55#ibcon#*before return 0, iclass 22, count 0 2006.285.07:21:01.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:21:01.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:21:01.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:21:01.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:21:01.55$vck44/va=7,4 2006.285.07:21:01.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.07:21:01.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.07:21:01.55#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:01.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:21:01.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:21:01.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:21:01.61#ibcon#enter wrdev, iclass 24, count 2 2006.285.07:21:01.61#ibcon#first serial, iclass 24, count 2 2006.285.07:21:01.61#ibcon#enter sib2, iclass 24, count 2 2006.285.07:21:01.61#ibcon#flushed, iclass 24, count 2 2006.285.07:21:01.61#ibcon#about to write, iclass 24, count 2 2006.285.07:21:01.61#ibcon#wrote, iclass 24, count 2 2006.285.07:21:01.61#ibcon#about to read 3, iclass 24, count 2 2006.285.07:21:01.63#ibcon#read 3, iclass 24, count 2 2006.285.07:21:01.63#ibcon#about to read 4, iclass 24, count 2 2006.285.07:21:01.63#ibcon#read 4, iclass 24, count 2 2006.285.07:21:01.63#ibcon#about to read 5, iclass 24, count 2 2006.285.07:21:01.63#ibcon#read 5, iclass 24, count 2 2006.285.07:21:01.63#ibcon#about to read 6, iclass 24, count 2 2006.285.07:21:01.63#ibcon#read 6, iclass 24, count 2 2006.285.07:21:01.63#ibcon#end of sib2, iclass 24, count 2 2006.285.07:21:01.63#ibcon#*mode == 0, iclass 24, count 2 2006.285.07:21:01.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.07:21:01.63#ibcon#[25=AT07-04\r\n] 2006.285.07:21:01.63#ibcon#*before write, iclass 24, count 2 2006.285.07:21:01.63#ibcon#enter sib2, iclass 24, count 2 2006.285.07:21:01.63#ibcon#flushed, iclass 24, count 2 2006.285.07:21:01.63#ibcon#about to write, iclass 24, count 2 2006.285.07:21:01.63#ibcon#wrote, iclass 24, count 2 2006.285.07:21:01.63#ibcon#about to read 3, iclass 24, count 2 2006.285.07:21:01.66#ibcon#read 3, iclass 24, count 2 2006.285.07:21:01.66#ibcon#about to read 4, iclass 24, count 2 2006.285.07:21:01.66#ibcon#read 4, iclass 24, count 2 2006.285.07:21:01.66#ibcon#about to read 5, iclass 24, count 2 2006.285.07:21:01.66#ibcon#read 5, iclass 24, count 2 2006.285.07:21:01.66#ibcon#about to read 6, iclass 24, count 2 2006.285.07:21:01.66#ibcon#read 6, iclass 24, count 2 2006.285.07:21:01.66#ibcon#end of sib2, iclass 24, count 2 2006.285.07:21:01.66#ibcon#*after write, iclass 24, count 2 2006.285.07:21:01.66#ibcon#*before return 0, iclass 24, count 2 2006.285.07:21:01.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:21:01.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:21:01.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.07:21:01.66#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:01.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:21:01.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:21:01.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:21:01.78#ibcon#enter wrdev, iclass 24, count 0 2006.285.07:21:01.78#ibcon#first serial, iclass 24, count 0 2006.285.07:21:01.78#ibcon#enter sib2, iclass 24, count 0 2006.285.07:21:01.78#ibcon#flushed, iclass 24, count 0 2006.285.07:21:01.78#ibcon#about to write, iclass 24, count 0 2006.285.07:21:01.78#ibcon#wrote, iclass 24, count 0 2006.285.07:21:01.78#ibcon#about to read 3, iclass 24, count 0 2006.285.07:21:01.80#ibcon#read 3, iclass 24, count 0 2006.285.07:21:01.80#ibcon#about to read 4, iclass 24, count 0 2006.285.07:21:01.80#ibcon#read 4, iclass 24, count 0 2006.285.07:21:01.80#ibcon#about to read 5, iclass 24, count 0 2006.285.07:21:01.80#ibcon#read 5, iclass 24, count 0 2006.285.07:21:01.80#ibcon#about to read 6, iclass 24, count 0 2006.285.07:21:01.80#ibcon#read 6, iclass 24, count 0 2006.285.07:21:01.80#ibcon#end of sib2, iclass 24, count 0 2006.285.07:21:01.80#ibcon#*mode == 0, iclass 24, count 0 2006.285.07:21:01.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.07:21:01.80#ibcon#[25=USB\r\n] 2006.285.07:21:01.80#ibcon#*before write, iclass 24, count 0 2006.285.07:21:01.80#ibcon#enter sib2, iclass 24, count 0 2006.285.07:21:01.80#ibcon#flushed, iclass 24, count 0 2006.285.07:21:01.80#ibcon#about to write, iclass 24, count 0 2006.285.07:21:01.80#ibcon#wrote, iclass 24, count 0 2006.285.07:21:01.80#ibcon#about to read 3, iclass 24, count 0 2006.285.07:21:01.83#ibcon#read 3, iclass 24, count 0 2006.285.07:21:01.83#ibcon#about to read 4, iclass 24, count 0 2006.285.07:21:01.83#ibcon#read 4, iclass 24, count 0 2006.285.07:21:01.83#ibcon#about to read 5, iclass 24, count 0 2006.285.07:21:01.83#ibcon#read 5, iclass 24, count 0 2006.285.07:21:01.83#ibcon#about to read 6, iclass 24, count 0 2006.285.07:21:01.83#ibcon#read 6, iclass 24, count 0 2006.285.07:21:01.83#ibcon#end of sib2, iclass 24, count 0 2006.285.07:21:01.83#ibcon#*after write, iclass 24, count 0 2006.285.07:21:01.83#ibcon#*before return 0, iclass 24, count 0 2006.285.07:21:01.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:21:01.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:21:01.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.07:21:01.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.07:21:01.83$vck44/valo=8,884.99 2006.285.07:21:01.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.07:21:01.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.07:21:01.83#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:01.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:21:01.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:21:01.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:21:01.83#ibcon#enter wrdev, iclass 26, count 0 2006.285.07:21:01.83#ibcon#first serial, iclass 26, count 0 2006.285.07:21:01.83#ibcon#enter sib2, iclass 26, count 0 2006.285.07:21:01.83#ibcon#flushed, iclass 26, count 0 2006.285.07:21:01.83#ibcon#about to write, iclass 26, count 0 2006.285.07:21:01.83#ibcon#wrote, iclass 26, count 0 2006.285.07:21:01.83#ibcon#about to read 3, iclass 26, count 0 2006.285.07:21:01.85#ibcon#read 3, iclass 26, count 0 2006.285.07:21:01.85#ibcon#about to read 4, iclass 26, count 0 2006.285.07:21:01.85#ibcon#read 4, iclass 26, count 0 2006.285.07:21:01.85#ibcon#about to read 5, iclass 26, count 0 2006.285.07:21:01.85#ibcon#read 5, iclass 26, count 0 2006.285.07:21:01.85#ibcon#about to read 6, iclass 26, count 0 2006.285.07:21:01.85#ibcon#read 6, iclass 26, count 0 2006.285.07:21:01.85#ibcon#end of sib2, iclass 26, count 0 2006.285.07:21:01.85#ibcon#*mode == 0, iclass 26, count 0 2006.285.07:21:01.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.07:21:01.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:21:01.85#ibcon#*before write, iclass 26, count 0 2006.285.07:21:01.85#ibcon#enter sib2, iclass 26, count 0 2006.285.07:21:01.85#ibcon#flushed, iclass 26, count 0 2006.285.07:21:01.85#ibcon#about to write, iclass 26, count 0 2006.285.07:21:01.85#ibcon#wrote, iclass 26, count 0 2006.285.07:21:01.85#ibcon#about to read 3, iclass 26, count 0 2006.285.07:21:01.89#ibcon#read 3, iclass 26, count 0 2006.285.07:21:01.89#ibcon#about to read 4, iclass 26, count 0 2006.285.07:21:01.89#ibcon#read 4, iclass 26, count 0 2006.285.07:21:01.89#ibcon#about to read 5, iclass 26, count 0 2006.285.07:21:01.89#ibcon#read 5, iclass 26, count 0 2006.285.07:21:01.89#ibcon#about to read 6, iclass 26, count 0 2006.285.07:21:01.89#ibcon#read 6, iclass 26, count 0 2006.285.07:21:01.89#ibcon#end of sib2, iclass 26, count 0 2006.285.07:21:01.89#ibcon#*after write, iclass 26, count 0 2006.285.07:21:01.89#ibcon#*before return 0, iclass 26, count 0 2006.285.07:21:01.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:21:01.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:21:01.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.07:21:01.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.07:21:01.89$vck44/va=8,3 2006.285.07:21:01.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.07:21:01.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.07:21:01.89#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:01.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:21:01.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:21:01.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:21:01.95#ibcon#enter wrdev, iclass 28, count 2 2006.285.07:21:01.95#ibcon#first serial, iclass 28, count 2 2006.285.07:21:01.95#ibcon#enter sib2, iclass 28, count 2 2006.285.07:21:01.95#ibcon#flushed, iclass 28, count 2 2006.285.07:21:01.95#ibcon#about to write, iclass 28, count 2 2006.285.07:21:01.95#ibcon#wrote, iclass 28, count 2 2006.285.07:21:01.95#ibcon#about to read 3, iclass 28, count 2 2006.285.07:21:01.97#ibcon#read 3, iclass 28, count 2 2006.285.07:21:01.97#ibcon#about to read 4, iclass 28, count 2 2006.285.07:21:01.97#ibcon#read 4, iclass 28, count 2 2006.285.07:21:01.97#ibcon#about to read 5, iclass 28, count 2 2006.285.07:21:01.97#ibcon#read 5, iclass 28, count 2 2006.285.07:21:01.97#ibcon#about to read 6, iclass 28, count 2 2006.285.07:21:01.97#ibcon#read 6, iclass 28, count 2 2006.285.07:21:01.97#ibcon#end of sib2, iclass 28, count 2 2006.285.07:21:01.97#ibcon#*mode == 0, iclass 28, count 2 2006.285.07:21:01.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.07:21:01.97#ibcon#[25=AT08-03\r\n] 2006.285.07:21:01.97#ibcon#*before write, iclass 28, count 2 2006.285.07:21:01.97#ibcon#enter sib2, iclass 28, count 2 2006.285.07:21:01.97#ibcon#flushed, iclass 28, count 2 2006.285.07:21:01.97#ibcon#about to write, iclass 28, count 2 2006.285.07:21:01.97#ibcon#wrote, iclass 28, count 2 2006.285.07:21:01.97#ibcon#about to read 3, iclass 28, count 2 2006.285.07:21:02.00#ibcon#read 3, iclass 28, count 2 2006.285.07:21:02.00#ibcon#about to read 4, iclass 28, count 2 2006.285.07:21:02.00#ibcon#read 4, iclass 28, count 2 2006.285.07:21:02.00#ibcon#about to read 5, iclass 28, count 2 2006.285.07:21:02.00#ibcon#read 5, iclass 28, count 2 2006.285.07:21:02.00#ibcon#about to read 6, iclass 28, count 2 2006.285.07:21:02.00#ibcon#read 6, iclass 28, count 2 2006.285.07:21:02.00#ibcon#end of sib2, iclass 28, count 2 2006.285.07:21:02.00#ibcon#*after write, iclass 28, count 2 2006.285.07:21:02.00#ibcon#*before return 0, iclass 28, count 2 2006.285.07:21:02.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:21:02.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:21:02.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.07:21:02.00#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:02.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:21:02.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:21:02.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:21:02.12#ibcon#enter wrdev, iclass 28, count 0 2006.285.07:21:02.12#ibcon#first serial, iclass 28, count 0 2006.285.07:21:02.12#ibcon#enter sib2, iclass 28, count 0 2006.285.07:21:02.12#ibcon#flushed, iclass 28, count 0 2006.285.07:21:02.12#ibcon#about to write, iclass 28, count 0 2006.285.07:21:02.12#ibcon#wrote, iclass 28, count 0 2006.285.07:21:02.12#ibcon#about to read 3, iclass 28, count 0 2006.285.07:21:02.14#ibcon#read 3, iclass 28, count 0 2006.285.07:21:02.14#ibcon#about to read 4, iclass 28, count 0 2006.285.07:21:02.14#ibcon#read 4, iclass 28, count 0 2006.285.07:21:02.14#ibcon#about to read 5, iclass 28, count 0 2006.285.07:21:02.14#ibcon#read 5, iclass 28, count 0 2006.285.07:21:02.14#ibcon#about to read 6, iclass 28, count 0 2006.285.07:21:02.14#ibcon#read 6, iclass 28, count 0 2006.285.07:21:02.14#ibcon#end of sib2, iclass 28, count 0 2006.285.07:21:02.14#ibcon#*mode == 0, iclass 28, count 0 2006.285.07:21:02.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.07:21:02.14#ibcon#[25=USB\r\n] 2006.285.07:21:02.14#ibcon#*before write, iclass 28, count 0 2006.285.07:21:02.14#ibcon#enter sib2, iclass 28, count 0 2006.285.07:21:02.14#ibcon#flushed, iclass 28, count 0 2006.285.07:21:02.14#ibcon#about to write, iclass 28, count 0 2006.285.07:21:02.14#ibcon#wrote, iclass 28, count 0 2006.285.07:21:02.14#ibcon#about to read 3, iclass 28, count 0 2006.285.07:21:02.17#ibcon#read 3, iclass 28, count 0 2006.285.07:21:02.17#ibcon#about to read 4, iclass 28, count 0 2006.285.07:21:02.17#ibcon#read 4, iclass 28, count 0 2006.285.07:21:02.17#ibcon#about to read 5, iclass 28, count 0 2006.285.07:21:02.17#ibcon#read 5, iclass 28, count 0 2006.285.07:21:02.17#ibcon#about to read 6, iclass 28, count 0 2006.285.07:21:02.17#ibcon#read 6, iclass 28, count 0 2006.285.07:21:02.17#ibcon#end of sib2, iclass 28, count 0 2006.285.07:21:02.17#ibcon#*after write, iclass 28, count 0 2006.285.07:21:02.17#ibcon#*before return 0, iclass 28, count 0 2006.285.07:21:02.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:21:02.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:21:02.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.07:21:02.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.07:21:02.17$vck44/vblo=1,629.99 2006.285.07:21:02.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.07:21:02.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.07:21:02.17#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:02.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:21:02.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:21:02.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:21:02.17#ibcon#enter wrdev, iclass 30, count 0 2006.285.07:21:02.17#ibcon#first serial, iclass 30, count 0 2006.285.07:21:02.17#ibcon#enter sib2, iclass 30, count 0 2006.285.07:21:02.17#ibcon#flushed, iclass 30, count 0 2006.285.07:21:02.17#ibcon#about to write, iclass 30, count 0 2006.285.07:21:02.17#ibcon#wrote, iclass 30, count 0 2006.285.07:21:02.17#ibcon#about to read 3, iclass 30, count 0 2006.285.07:21:02.19#ibcon#read 3, iclass 30, count 0 2006.285.07:21:02.19#ibcon#about to read 4, iclass 30, count 0 2006.285.07:21:02.19#ibcon#read 4, iclass 30, count 0 2006.285.07:21:02.19#ibcon#about to read 5, iclass 30, count 0 2006.285.07:21:02.19#ibcon#read 5, iclass 30, count 0 2006.285.07:21:02.19#ibcon#about to read 6, iclass 30, count 0 2006.285.07:21:02.19#ibcon#read 6, iclass 30, count 0 2006.285.07:21:02.19#ibcon#end of sib2, iclass 30, count 0 2006.285.07:21:02.19#ibcon#*mode == 0, iclass 30, count 0 2006.285.07:21:02.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.07:21:02.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:21:02.19#ibcon#*before write, iclass 30, count 0 2006.285.07:21:02.19#ibcon#enter sib2, iclass 30, count 0 2006.285.07:21:02.19#ibcon#flushed, iclass 30, count 0 2006.285.07:21:02.19#ibcon#about to write, iclass 30, count 0 2006.285.07:21:02.19#ibcon#wrote, iclass 30, count 0 2006.285.07:21:02.19#ibcon#about to read 3, iclass 30, count 0 2006.285.07:21:02.23#ibcon#read 3, iclass 30, count 0 2006.285.07:21:02.23#ibcon#about to read 4, iclass 30, count 0 2006.285.07:21:02.23#ibcon#read 4, iclass 30, count 0 2006.285.07:21:02.23#ibcon#about to read 5, iclass 30, count 0 2006.285.07:21:02.23#ibcon#read 5, iclass 30, count 0 2006.285.07:21:02.23#ibcon#about to read 6, iclass 30, count 0 2006.285.07:21:02.23#ibcon#read 6, iclass 30, count 0 2006.285.07:21:02.23#ibcon#end of sib2, iclass 30, count 0 2006.285.07:21:02.23#ibcon#*after write, iclass 30, count 0 2006.285.07:21:02.23#ibcon#*before return 0, iclass 30, count 0 2006.285.07:21:02.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:21:02.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:21:02.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.07:21:02.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.07:21:02.23$vck44/vb=1,4 2006.285.07:21:02.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.07:21:02.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.07:21:02.23#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:02.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:21:02.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:21:02.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:21:02.23#ibcon#enter wrdev, iclass 32, count 2 2006.285.07:21:02.23#ibcon#first serial, iclass 32, count 2 2006.285.07:21:02.23#ibcon#enter sib2, iclass 32, count 2 2006.285.07:21:02.23#ibcon#flushed, iclass 32, count 2 2006.285.07:21:02.23#ibcon#about to write, iclass 32, count 2 2006.285.07:21:02.23#ibcon#wrote, iclass 32, count 2 2006.285.07:21:02.23#ibcon#about to read 3, iclass 32, count 2 2006.285.07:21:02.25#ibcon#read 3, iclass 32, count 2 2006.285.07:21:02.25#ibcon#about to read 4, iclass 32, count 2 2006.285.07:21:02.25#ibcon#read 4, iclass 32, count 2 2006.285.07:21:02.25#ibcon#about to read 5, iclass 32, count 2 2006.285.07:21:02.25#ibcon#read 5, iclass 32, count 2 2006.285.07:21:02.25#ibcon#about to read 6, iclass 32, count 2 2006.285.07:21:02.25#ibcon#read 6, iclass 32, count 2 2006.285.07:21:02.25#ibcon#end of sib2, iclass 32, count 2 2006.285.07:21:02.25#ibcon#*mode == 0, iclass 32, count 2 2006.285.07:21:02.25#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.07:21:02.25#ibcon#[27=AT01-04\r\n] 2006.285.07:21:02.25#ibcon#*before write, iclass 32, count 2 2006.285.07:21:02.25#ibcon#enter sib2, iclass 32, count 2 2006.285.07:21:02.25#ibcon#flushed, iclass 32, count 2 2006.285.07:21:02.25#ibcon#about to write, iclass 32, count 2 2006.285.07:21:02.25#ibcon#wrote, iclass 32, count 2 2006.285.07:21:02.25#ibcon#about to read 3, iclass 32, count 2 2006.285.07:21:02.28#ibcon#read 3, iclass 32, count 2 2006.285.07:21:02.28#ibcon#about to read 4, iclass 32, count 2 2006.285.07:21:02.28#ibcon#read 4, iclass 32, count 2 2006.285.07:21:02.28#ibcon#about to read 5, iclass 32, count 2 2006.285.07:21:02.28#ibcon#read 5, iclass 32, count 2 2006.285.07:21:02.28#ibcon#about to read 6, iclass 32, count 2 2006.285.07:21:02.28#ibcon#read 6, iclass 32, count 2 2006.285.07:21:02.28#ibcon#end of sib2, iclass 32, count 2 2006.285.07:21:02.28#ibcon#*after write, iclass 32, count 2 2006.285.07:21:02.28#ibcon#*before return 0, iclass 32, count 2 2006.285.07:21:02.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:21:02.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:21:02.28#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.07:21:02.28#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:02.28#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:21:02.40#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:21:02.40#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:21:02.40#ibcon#enter wrdev, iclass 32, count 0 2006.285.07:21:02.40#ibcon#first serial, iclass 32, count 0 2006.285.07:21:02.40#ibcon#enter sib2, iclass 32, count 0 2006.285.07:21:02.40#ibcon#flushed, iclass 32, count 0 2006.285.07:21:02.40#ibcon#about to write, iclass 32, count 0 2006.285.07:21:02.40#ibcon#wrote, iclass 32, count 0 2006.285.07:21:02.40#ibcon#about to read 3, iclass 32, count 0 2006.285.07:21:02.42#ibcon#read 3, iclass 32, count 0 2006.285.07:21:02.42#ibcon#about to read 4, iclass 32, count 0 2006.285.07:21:02.42#ibcon#read 4, iclass 32, count 0 2006.285.07:21:02.42#ibcon#about to read 5, iclass 32, count 0 2006.285.07:21:02.42#ibcon#read 5, iclass 32, count 0 2006.285.07:21:02.42#ibcon#about to read 6, iclass 32, count 0 2006.285.07:21:02.42#ibcon#read 6, iclass 32, count 0 2006.285.07:21:02.42#ibcon#end of sib2, iclass 32, count 0 2006.285.07:21:02.42#ibcon#*mode == 0, iclass 32, count 0 2006.285.07:21:02.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.07:21:02.42#ibcon#[27=USB\r\n] 2006.285.07:21:02.42#ibcon#*before write, iclass 32, count 0 2006.285.07:21:02.42#ibcon#enter sib2, iclass 32, count 0 2006.285.07:21:02.42#ibcon#flushed, iclass 32, count 0 2006.285.07:21:02.42#ibcon#about to write, iclass 32, count 0 2006.285.07:21:02.42#ibcon#wrote, iclass 32, count 0 2006.285.07:21:02.42#ibcon#about to read 3, iclass 32, count 0 2006.285.07:21:02.45#ibcon#read 3, iclass 32, count 0 2006.285.07:21:02.45#ibcon#about to read 4, iclass 32, count 0 2006.285.07:21:02.45#ibcon#read 4, iclass 32, count 0 2006.285.07:21:02.45#ibcon#about to read 5, iclass 32, count 0 2006.285.07:21:02.45#ibcon#read 5, iclass 32, count 0 2006.285.07:21:02.45#ibcon#about to read 6, iclass 32, count 0 2006.285.07:21:02.45#ibcon#read 6, iclass 32, count 0 2006.285.07:21:02.45#ibcon#end of sib2, iclass 32, count 0 2006.285.07:21:02.45#ibcon#*after write, iclass 32, count 0 2006.285.07:21:02.45#ibcon#*before return 0, iclass 32, count 0 2006.285.07:21:02.45#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:21:02.45#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:21:02.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.07:21:02.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.07:21:02.45$vck44/vblo=2,634.99 2006.285.07:21:02.45#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.07:21:02.45#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.07:21:02.45#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:02.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:21:02.45#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:21:02.45#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:21:02.45#ibcon#enter wrdev, iclass 34, count 0 2006.285.07:21:02.45#ibcon#first serial, iclass 34, count 0 2006.285.07:21:02.45#ibcon#enter sib2, iclass 34, count 0 2006.285.07:21:02.45#ibcon#flushed, iclass 34, count 0 2006.285.07:21:02.45#ibcon#about to write, iclass 34, count 0 2006.285.07:21:02.45#ibcon#wrote, iclass 34, count 0 2006.285.07:21:02.45#ibcon#about to read 3, iclass 34, count 0 2006.285.07:21:02.47#ibcon#read 3, iclass 34, count 0 2006.285.07:21:02.47#ibcon#about to read 4, iclass 34, count 0 2006.285.07:21:02.47#ibcon#read 4, iclass 34, count 0 2006.285.07:21:02.47#ibcon#about to read 5, iclass 34, count 0 2006.285.07:21:02.47#ibcon#read 5, iclass 34, count 0 2006.285.07:21:02.47#ibcon#about to read 6, iclass 34, count 0 2006.285.07:21:02.47#ibcon#read 6, iclass 34, count 0 2006.285.07:21:02.47#ibcon#end of sib2, iclass 34, count 0 2006.285.07:21:02.47#ibcon#*mode == 0, iclass 34, count 0 2006.285.07:21:02.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.07:21:02.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:21:02.47#ibcon#*before write, iclass 34, count 0 2006.285.07:21:02.47#ibcon#enter sib2, iclass 34, count 0 2006.285.07:21:02.47#ibcon#flushed, iclass 34, count 0 2006.285.07:21:02.47#ibcon#about to write, iclass 34, count 0 2006.285.07:21:02.47#ibcon#wrote, iclass 34, count 0 2006.285.07:21:02.47#ibcon#about to read 3, iclass 34, count 0 2006.285.07:21:02.51#ibcon#read 3, iclass 34, count 0 2006.285.07:21:02.51#ibcon#about to read 4, iclass 34, count 0 2006.285.07:21:02.51#ibcon#read 4, iclass 34, count 0 2006.285.07:21:02.51#ibcon#about to read 5, iclass 34, count 0 2006.285.07:21:02.51#ibcon#read 5, iclass 34, count 0 2006.285.07:21:02.51#ibcon#about to read 6, iclass 34, count 0 2006.285.07:21:02.51#ibcon#read 6, iclass 34, count 0 2006.285.07:21:02.51#ibcon#end of sib2, iclass 34, count 0 2006.285.07:21:02.51#ibcon#*after write, iclass 34, count 0 2006.285.07:21:02.51#ibcon#*before return 0, iclass 34, count 0 2006.285.07:21:02.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:21:02.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:21:02.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.07:21:02.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.07:21:02.51$vck44/vb=2,5 2006.285.07:21:02.51#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.07:21:02.51#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.07:21:02.51#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:02.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:21:02.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:21:02.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:21:02.57#ibcon#enter wrdev, iclass 36, count 2 2006.285.07:21:02.57#ibcon#first serial, iclass 36, count 2 2006.285.07:21:02.57#ibcon#enter sib2, iclass 36, count 2 2006.285.07:21:02.57#ibcon#flushed, iclass 36, count 2 2006.285.07:21:02.57#ibcon#about to write, iclass 36, count 2 2006.285.07:21:02.57#ibcon#wrote, iclass 36, count 2 2006.285.07:21:02.57#ibcon#about to read 3, iclass 36, count 2 2006.285.07:21:02.59#ibcon#read 3, iclass 36, count 2 2006.285.07:21:02.59#ibcon#about to read 4, iclass 36, count 2 2006.285.07:21:02.59#ibcon#read 4, iclass 36, count 2 2006.285.07:21:02.59#ibcon#about to read 5, iclass 36, count 2 2006.285.07:21:02.59#ibcon#read 5, iclass 36, count 2 2006.285.07:21:02.59#ibcon#about to read 6, iclass 36, count 2 2006.285.07:21:02.59#ibcon#read 6, iclass 36, count 2 2006.285.07:21:02.59#ibcon#end of sib2, iclass 36, count 2 2006.285.07:21:02.59#ibcon#*mode == 0, iclass 36, count 2 2006.285.07:21:02.59#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.07:21:02.59#ibcon#[27=AT02-05\r\n] 2006.285.07:21:02.59#ibcon#*before write, iclass 36, count 2 2006.285.07:21:02.59#ibcon#enter sib2, iclass 36, count 2 2006.285.07:21:02.59#ibcon#flushed, iclass 36, count 2 2006.285.07:21:02.59#ibcon#about to write, iclass 36, count 2 2006.285.07:21:02.59#ibcon#wrote, iclass 36, count 2 2006.285.07:21:02.59#ibcon#about to read 3, iclass 36, count 2 2006.285.07:21:02.62#ibcon#read 3, iclass 36, count 2 2006.285.07:21:02.62#ibcon#about to read 4, iclass 36, count 2 2006.285.07:21:02.62#ibcon#read 4, iclass 36, count 2 2006.285.07:21:02.62#ibcon#about to read 5, iclass 36, count 2 2006.285.07:21:02.62#ibcon#read 5, iclass 36, count 2 2006.285.07:21:02.62#ibcon#about to read 6, iclass 36, count 2 2006.285.07:21:02.62#ibcon#read 6, iclass 36, count 2 2006.285.07:21:02.62#ibcon#end of sib2, iclass 36, count 2 2006.285.07:21:02.62#ibcon#*after write, iclass 36, count 2 2006.285.07:21:02.62#ibcon#*before return 0, iclass 36, count 2 2006.285.07:21:02.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:21:02.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:21:02.62#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.07:21:02.62#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:02.62#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:21:02.74#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:21:02.74#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:21:02.74#ibcon#enter wrdev, iclass 36, count 0 2006.285.07:21:02.74#ibcon#first serial, iclass 36, count 0 2006.285.07:21:02.74#ibcon#enter sib2, iclass 36, count 0 2006.285.07:21:02.74#ibcon#flushed, iclass 36, count 0 2006.285.07:21:02.74#ibcon#about to write, iclass 36, count 0 2006.285.07:21:02.74#ibcon#wrote, iclass 36, count 0 2006.285.07:21:02.74#ibcon#about to read 3, iclass 36, count 0 2006.285.07:21:02.76#ibcon#read 3, iclass 36, count 0 2006.285.07:21:02.76#ibcon#about to read 4, iclass 36, count 0 2006.285.07:21:02.76#ibcon#read 4, iclass 36, count 0 2006.285.07:21:02.76#ibcon#about to read 5, iclass 36, count 0 2006.285.07:21:02.76#ibcon#read 5, iclass 36, count 0 2006.285.07:21:02.76#ibcon#about to read 6, iclass 36, count 0 2006.285.07:21:02.76#ibcon#read 6, iclass 36, count 0 2006.285.07:21:02.76#ibcon#end of sib2, iclass 36, count 0 2006.285.07:21:02.76#ibcon#*mode == 0, iclass 36, count 0 2006.285.07:21:02.76#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.07:21:02.76#ibcon#[27=USB\r\n] 2006.285.07:21:02.76#ibcon#*before write, iclass 36, count 0 2006.285.07:21:02.76#ibcon#enter sib2, iclass 36, count 0 2006.285.07:21:02.76#ibcon#flushed, iclass 36, count 0 2006.285.07:21:02.76#ibcon#about to write, iclass 36, count 0 2006.285.07:21:02.76#ibcon#wrote, iclass 36, count 0 2006.285.07:21:02.76#ibcon#about to read 3, iclass 36, count 0 2006.285.07:21:02.79#ibcon#read 3, iclass 36, count 0 2006.285.07:21:02.79#ibcon#about to read 4, iclass 36, count 0 2006.285.07:21:02.79#ibcon#read 4, iclass 36, count 0 2006.285.07:21:02.79#ibcon#about to read 5, iclass 36, count 0 2006.285.07:21:02.79#ibcon#read 5, iclass 36, count 0 2006.285.07:21:02.79#ibcon#about to read 6, iclass 36, count 0 2006.285.07:21:02.79#ibcon#read 6, iclass 36, count 0 2006.285.07:21:02.79#ibcon#end of sib2, iclass 36, count 0 2006.285.07:21:02.79#ibcon#*after write, iclass 36, count 0 2006.285.07:21:02.79#ibcon#*before return 0, iclass 36, count 0 2006.285.07:21:02.79#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:21:02.79#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:21:02.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.07:21:02.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.07:21:02.79$vck44/vblo=3,649.99 2006.285.07:21:02.79#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.07:21:02.79#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.07:21:02.79#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:02.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:21:02.79#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:21:02.79#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:21:02.79#ibcon#enter wrdev, iclass 38, count 0 2006.285.07:21:02.79#ibcon#first serial, iclass 38, count 0 2006.285.07:21:02.79#ibcon#enter sib2, iclass 38, count 0 2006.285.07:21:02.79#ibcon#flushed, iclass 38, count 0 2006.285.07:21:02.79#ibcon#about to write, iclass 38, count 0 2006.285.07:21:02.79#ibcon#wrote, iclass 38, count 0 2006.285.07:21:02.79#ibcon#about to read 3, iclass 38, count 0 2006.285.07:21:02.81#ibcon#read 3, iclass 38, count 0 2006.285.07:21:02.81#ibcon#about to read 4, iclass 38, count 0 2006.285.07:21:02.81#ibcon#read 4, iclass 38, count 0 2006.285.07:21:02.81#ibcon#about to read 5, iclass 38, count 0 2006.285.07:21:02.81#ibcon#read 5, iclass 38, count 0 2006.285.07:21:02.81#ibcon#about to read 6, iclass 38, count 0 2006.285.07:21:02.81#ibcon#read 6, iclass 38, count 0 2006.285.07:21:02.81#ibcon#end of sib2, iclass 38, count 0 2006.285.07:21:02.81#ibcon#*mode == 0, iclass 38, count 0 2006.285.07:21:02.81#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.07:21:02.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:21:02.81#ibcon#*before write, iclass 38, count 0 2006.285.07:21:02.81#ibcon#enter sib2, iclass 38, count 0 2006.285.07:21:02.81#ibcon#flushed, iclass 38, count 0 2006.285.07:21:02.81#ibcon#about to write, iclass 38, count 0 2006.285.07:21:02.81#ibcon#wrote, iclass 38, count 0 2006.285.07:21:02.81#ibcon#about to read 3, iclass 38, count 0 2006.285.07:21:02.85#ibcon#read 3, iclass 38, count 0 2006.285.07:21:02.85#ibcon#about to read 4, iclass 38, count 0 2006.285.07:21:02.85#ibcon#read 4, iclass 38, count 0 2006.285.07:21:02.85#ibcon#about to read 5, iclass 38, count 0 2006.285.07:21:02.85#ibcon#read 5, iclass 38, count 0 2006.285.07:21:02.85#ibcon#about to read 6, iclass 38, count 0 2006.285.07:21:02.85#ibcon#read 6, iclass 38, count 0 2006.285.07:21:02.85#ibcon#end of sib2, iclass 38, count 0 2006.285.07:21:02.85#ibcon#*after write, iclass 38, count 0 2006.285.07:21:02.85#ibcon#*before return 0, iclass 38, count 0 2006.285.07:21:02.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:21:02.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:21:02.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.07:21:02.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.07:21:02.85$vck44/vb=3,4 2006.285.07:21:02.85#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.07:21:02.85#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.07:21:02.85#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:02.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:21:02.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:21:02.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:21:02.91#ibcon#enter wrdev, iclass 40, count 2 2006.285.07:21:02.91#ibcon#first serial, iclass 40, count 2 2006.285.07:21:02.91#ibcon#enter sib2, iclass 40, count 2 2006.285.07:21:02.91#ibcon#flushed, iclass 40, count 2 2006.285.07:21:02.91#ibcon#about to write, iclass 40, count 2 2006.285.07:21:02.91#ibcon#wrote, iclass 40, count 2 2006.285.07:21:02.91#ibcon#about to read 3, iclass 40, count 2 2006.285.07:21:02.93#ibcon#read 3, iclass 40, count 2 2006.285.07:21:02.93#ibcon#about to read 4, iclass 40, count 2 2006.285.07:21:02.93#ibcon#read 4, iclass 40, count 2 2006.285.07:21:02.93#ibcon#about to read 5, iclass 40, count 2 2006.285.07:21:02.93#ibcon#read 5, iclass 40, count 2 2006.285.07:21:02.93#ibcon#about to read 6, iclass 40, count 2 2006.285.07:21:02.93#ibcon#read 6, iclass 40, count 2 2006.285.07:21:02.93#ibcon#end of sib2, iclass 40, count 2 2006.285.07:21:02.93#ibcon#*mode == 0, iclass 40, count 2 2006.285.07:21:02.93#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.07:21:02.93#ibcon#[27=AT03-04\r\n] 2006.285.07:21:02.93#ibcon#*before write, iclass 40, count 2 2006.285.07:21:02.93#ibcon#enter sib2, iclass 40, count 2 2006.285.07:21:02.93#ibcon#flushed, iclass 40, count 2 2006.285.07:21:02.93#ibcon#about to write, iclass 40, count 2 2006.285.07:21:02.93#ibcon#wrote, iclass 40, count 2 2006.285.07:21:02.93#ibcon#about to read 3, iclass 40, count 2 2006.285.07:21:02.96#ibcon#read 3, iclass 40, count 2 2006.285.07:21:02.96#ibcon#about to read 4, iclass 40, count 2 2006.285.07:21:02.96#ibcon#read 4, iclass 40, count 2 2006.285.07:21:02.96#ibcon#about to read 5, iclass 40, count 2 2006.285.07:21:02.96#ibcon#read 5, iclass 40, count 2 2006.285.07:21:02.96#ibcon#about to read 6, iclass 40, count 2 2006.285.07:21:02.96#ibcon#read 6, iclass 40, count 2 2006.285.07:21:02.96#ibcon#end of sib2, iclass 40, count 2 2006.285.07:21:02.96#ibcon#*after write, iclass 40, count 2 2006.285.07:21:02.96#ibcon#*before return 0, iclass 40, count 2 2006.285.07:21:02.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:21:02.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:21:02.96#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.07:21:02.96#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:02.96#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:21:03.08#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:21:03.08#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:21:03.08#ibcon#enter wrdev, iclass 40, count 0 2006.285.07:21:03.08#ibcon#first serial, iclass 40, count 0 2006.285.07:21:03.08#ibcon#enter sib2, iclass 40, count 0 2006.285.07:21:03.08#ibcon#flushed, iclass 40, count 0 2006.285.07:21:03.08#ibcon#about to write, iclass 40, count 0 2006.285.07:21:03.08#ibcon#wrote, iclass 40, count 0 2006.285.07:21:03.08#ibcon#about to read 3, iclass 40, count 0 2006.285.07:21:03.10#ibcon#read 3, iclass 40, count 0 2006.285.07:21:03.10#ibcon#about to read 4, iclass 40, count 0 2006.285.07:21:03.10#ibcon#read 4, iclass 40, count 0 2006.285.07:21:03.10#ibcon#about to read 5, iclass 40, count 0 2006.285.07:21:03.10#ibcon#read 5, iclass 40, count 0 2006.285.07:21:03.10#ibcon#about to read 6, iclass 40, count 0 2006.285.07:21:03.10#ibcon#read 6, iclass 40, count 0 2006.285.07:21:03.10#ibcon#end of sib2, iclass 40, count 0 2006.285.07:21:03.10#ibcon#*mode == 0, iclass 40, count 0 2006.285.07:21:03.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.07:21:03.10#ibcon#[27=USB\r\n] 2006.285.07:21:03.10#ibcon#*before write, iclass 40, count 0 2006.285.07:21:03.10#ibcon#enter sib2, iclass 40, count 0 2006.285.07:21:03.10#ibcon#flushed, iclass 40, count 0 2006.285.07:21:03.10#ibcon#about to write, iclass 40, count 0 2006.285.07:21:03.10#ibcon#wrote, iclass 40, count 0 2006.285.07:21:03.10#ibcon#about to read 3, iclass 40, count 0 2006.285.07:21:03.13#ibcon#read 3, iclass 40, count 0 2006.285.07:21:03.13#ibcon#about to read 4, iclass 40, count 0 2006.285.07:21:03.13#ibcon#read 4, iclass 40, count 0 2006.285.07:21:03.13#ibcon#about to read 5, iclass 40, count 0 2006.285.07:21:03.13#ibcon#read 5, iclass 40, count 0 2006.285.07:21:03.13#ibcon#about to read 6, iclass 40, count 0 2006.285.07:21:03.13#ibcon#read 6, iclass 40, count 0 2006.285.07:21:03.13#ibcon#end of sib2, iclass 40, count 0 2006.285.07:21:03.13#ibcon#*after write, iclass 40, count 0 2006.285.07:21:03.13#ibcon#*before return 0, iclass 40, count 0 2006.285.07:21:03.13#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:21:03.13#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:21:03.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.07:21:03.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.07:21:03.13$vck44/vblo=4,679.99 2006.285.07:21:03.13#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.07:21:03.13#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.07:21:03.13#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:03.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:21:03.13#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:21:03.13#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:21:03.13#ibcon#enter wrdev, iclass 4, count 0 2006.285.07:21:03.13#ibcon#first serial, iclass 4, count 0 2006.285.07:21:03.13#ibcon#enter sib2, iclass 4, count 0 2006.285.07:21:03.13#ibcon#flushed, iclass 4, count 0 2006.285.07:21:03.13#ibcon#about to write, iclass 4, count 0 2006.285.07:21:03.13#ibcon#wrote, iclass 4, count 0 2006.285.07:21:03.13#ibcon#about to read 3, iclass 4, count 0 2006.285.07:21:03.15#ibcon#read 3, iclass 4, count 0 2006.285.07:21:03.15#ibcon#about to read 4, iclass 4, count 0 2006.285.07:21:03.15#ibcon#read 4, iclass 4, count 0 2006.285.07:21:03.15#ibcon#about to read 5, iclass 4, count 0 2006.285.07:21:03.15#ibcon#read 5, iclass 4, count 0 2006.285.07:21:03.15#ibcon#about to read 6, iclass 4, count 0 2006.285.07:21:03.15#ibcon#read 6, iclass 4, count 0 2006.285.07:21:03.15#ibcon#end of sib2, iclass 4, count 0 2006.285.07:21:03.15#ibcon#*mode == 0, iclass 4, count 0 2006.285.07:21:03.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.07:21:03.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:21:03.15#ibcon#*before write, iclass 4, count 0 2006.285.07:21:03.15#ibcon#enter sib2, iclass 4, count 0 2006.285.07:21:03.15#ibcon#flushed, iclass 4, count 0 2006.285.07:21:03.15#ibcon#about to write, iclass 4, count 0 2006.285.07:21:03.15#ibcon#wrote, iclass 4, count 0 2006.285.07:21:03.15#ibcon#about to read 3, iclass 4, count 0 2006.285.07:21:03.19#ibcon#read 3, iclass 4, count 0 2006.285.07:21:03.19#ibcon#about to read 4, iclass 4, count 0 2006.285.07:21:03.19#ibcon#read 4, iclass 4, count 0 2006.285.07:21:03.19#ibcon#about to read 5, iclass 4, count 0 2006.285.07:21:03.19#ibcon#read 5, iclass 4, count 0 2006.285.07:21:03.19#ibcon#about to read 6, iclass 4, count 0 2006.285.07:21:03.19#ibcon#read 6, iclass 4, count 0 2006.285.07:21:03.19#ibcon#end of sib2, iclass 4, count 0 2006.285.07:21:03.19#ibcon#*after write, iclass 4, count 0 2006.285.07:21:03.19#ibcon#*before return 0, iclass 4, count 0 2006.285.07:21:03.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:21:03.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:21:03.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.07:21:03.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.07:21:03.19$vck44/vb=4,5 2006.285.07:21:03.19#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.07:21:03.19#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.07:21:03.19#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:03.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:21:03.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:21:03.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:21:03.25#ibcon#enter wrdev, iclass 6, count 2 2006.285.07:21:03.25#ibcon#first serial, iclass 6, count 2 2006.285.07:21:03.25#ibcon#enter sib2, iclass 6, count 2 2006.285.07:21:03.25#ibcon#flushed, iclass 6, count 2 2006.285.07:21:03.25#ibcon#about to write, iclass 6, count 2 2006.285.07:21:03.25#ibcon#wrote, iclass 6, count 2 2006.285.07:21:03.25#ibcon#about to read 3, iclass 6, count 2 2006.285.07:21:03.27#ibcon#read 3, iclass 6, count 2 2006.285.07:21:03.27#ibcon#about to read 4, iclass 6, count 2 2006.285.07:21:03.27#ibcon#read 4, iclass 6, count 2 2006.285.07:21:03.27#ibcon#about to read 5, iclass 6, count 2 2006.285.07:21:03.27#ibcon#read 5, iclass 6, count 2 2006.285.07:21:03.27#ibcon#about to read 6, iclass 6, count 2 2006.285.07:21:03.27#ibcon#read 6, iclass 6, count 2 2006.285.07:21:03.27#ibcon#end of sib2, iclass 6, count 2 2006.285.07:21:03.27#ibcon#*mode == 0, iclass 6, count 2 2006.285.07:21:03.27#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.07:21:03.27#ibcon#[27=AT04-05\r\n] 2006.285.07:21:03.27#ibcon#*before write, iclass 6, count 2 2006.285.07:21:03.27#ibcon#enter sib2, iclass 6, count 2 2006.285.07:21:03.27#ibcon#flushed, iclass 6, count 2 2006.285.07:21:03.27#ibcon#about to write, iclass 6, count 2 2006.285.07:21:03.27#ibcon#wrote, iclass 6, count 2 2006.285.07:21:03.27#ibcon#about to read 3, iclass 6, count 2 2006.285.07:21:03.30#ibcon#read 3, iclass 6, count 2 2006.285.07:21:03.30#ibcon#about to read 4, iclass 6, count 2 2006.285.07:21:03.30#ibcon#read 4, iclass 6, count 2 2006.285.07:21:03.30#ibcon#about to read 5, iclass 6, count 2 2006.285.07:21:03.30#ibcon#read 5, iclass 6, count 2 2006.285.07:21:03.30#ibcon#about to read 6, iclass 6, count 2 2006.285.07:21:03.30#ibcon#read 6, iclass 6, count 2 2006.285.07:21:03.30#ibcon#end of sib2, iclass 6, count 2 2006.285.07:21:03.30#ibcon#*after write, iclass 6, count 2 2006.285.07:21:03.30#ibcon#*before return 0, iclass 6, count 2 2006.285.07:21:03.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:21:03.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:21:03.30#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.07:21:03.30#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:03.30#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:21:03.42#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:21:03.42#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:21:03.42#ibcon#enter wrdev, iclass 6, count 0 2006.285.07:21:03.42#ibcon#first serial, iclass 6, count 0 2006.285.07:21:03.42#ibcon#enter sib2, iclass 6, count 0 2006.285.07:21:03.42#ibcon#flushed, iclass 6, count 0 2006.285.07:21:03.42#ibcon#about to write, iclass 6, count 0 2006.285.07:21:03.42#ibcon#wrote, iclass 6, count 0 2006.285.07:21:03.42#ibcon#about to read 3, iclass 6, count 0 2006.285.07:21:03.44#ibcon#read 3, iclass 6, count 0 2006.285.07:21:03.44#ibcon#about to read 4, iclass 6, count 0 2006.285.07:21:03.44#ibcon#read 4, iclass 6, count 0 2006.285.07:21:03.44#ibcon#about to read 5, iclass 6, count 0 2006.285.07:21:03.44#ibcon#read 5, iclass 6, count 0 2006.285.07:21:03.44#ibcon#about to read 6, iclass 6, count 0 2006.285.07:21:03.44#ibcon#read 6, iclass 6, count 0 2006.285.07:21:03.44#ibcon#end of sib2, iclass 6, count 0 2006.285.07:21:03.44#ibcon#*mode == 0, iclass 6, count 0 2006.285.07:21:03.44#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.07:21:03.44#ibcon#[27=USB\r\n] 2006.285.07:21:03.44#ibcon#*before write, iclass 6, count 0 2006.285.07:21:03.44#ibcon#enter sib2, iclass 6, count 0 2006.285.07:21:03.44#ibcon#flushed, iclass 6, count 0 2006.285.07:21:03.44#ibcon#about to write, iclass 6, count 0 2006.285.07:21:03.44#ibcon#wrote, iclass 6, count 0 2006.285.07:21:03.44#ibcon#about to read 3, iclass 6, count 0 2006.285.07:21:03.47#ibcon#read 3, iclass 6, count 0 2006.285.07:21:03.47#ibcon#about to read 4, iclass 6, count 0 2006.285.07:21:03.47#ibcon#read 4, iclass 6, count 0 2006.285.07:21:03.47#ibcon#about to read 5, iclass 6, count 0 2006.285.07:21:03.47#ibcon#read 5, iclass 6, count 0 2006.285.07:21:03.47#ibcon#about to read 6, iclass 6, count 0 2006.285.07:21:03.47#ibcon#read 6, iclass 6, count 0 2006.285.07:21:03.47#ibcon#end of sib2, iclass 6, count 0 2006.285.07:21:03.47#ibcon#*after write, iclass 6, count 0 2006.285.07:21:03.47#ibcon#*before return 0, iclass 6, count 0 2006.285.07:21:03.47#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:21:03.47#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:21:03.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.07:21:03.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.07:21:03.47$vck44/vblo=5,709.99 2006.285.07:21:03.47#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.07:21:03.47#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.07:21:03.47#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:03.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:21:03.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:21:03.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:21:03.47#ibcon#enter wrdev, iclass 10, count 0 2006.285.07:21:03.47#ibcon#first serial, iclass 10, count 0 2006.285.07:21:03.47#ibcon#enter sib2, iclass 10, count 0 2006.285.07:21:03.47#ibcon#flushed, iclass 10, count 0 2006.285.07:21:03.47#ibcon#about to write, iclass 10, count 0 2006.285.07:21:03.47#ibcon#wrote, iclass 10, count 0 2006.285.07:21:03.47#ibcon#about to read 3, iclass 10, count 0 2006.285.07:21:03.49#ibcon#read 3, iclass 10, count 0 2006.285.07:21:03.49#ibcon#about to read 4, iclass 10, count 0 2006.285.07:21:03.49#ibcon#read 4, iclass 10, count 0 2006.285.07:21:03.49#ibcon#about to read 5, iclass 10, count 0 2006.285.07:21:03.49#ibcon#read 5, iclass 10, count 0 2006.285.07:21:03.49#ibcon#about to read 6, iclass 10, count 0 2006.285.07:21:03.49#ibcon#read 6, iclass 10, count 0 2006.285.07:21:03.49#ibcon#end of sib2, iclass 10, count 0 2006.285.07:21:03.49#ibcon#*mode == 0, iclass 10, count 0 2006.285.07:21:03.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.07:21:03.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:21:03.49#ibcon#*before write, iclass 10, count 0 2006.285.07:21:03.49#ibcon#enter sib2, iclass 10, count 0 2006.285.07:21:03.49#ibcon#flushed, iclass 10, count 0 2006.285.07:21:03.49#ibcon#about to write, iclass 10, count 0 2006.285.07:21:03.49#ibcon#wrote, iclass 10, count 0 2006.285.07:21:03.49#ibcon#about to read 3, iclass 10, count 0 2006.285.07:21:03.53#ibcon#read 3, iclass 10, count 0 2006.285.07:21:03.53#ibcon#about to read 4, iclass 10, count 0 2006.285.07:21:03.53#ibcon#read 4, iclass 10, count 0 2006.285.07:21:03.53#ibcon#about to read 5, iclass 10, count 0 2006.285.07:21:03.53#ibcon#read 5, iclass 10, count 0 2006.285.07:21:03.53#ibcon#about to read 6, iclass 10, count 0 2006.285.07:21:03.53#ibcon#read 6, iclass 10, count 0 2006.285.07:21:03.53#ibcon#end of sib2, iclass 10, count 0 2006.285.07:21:03.53#ibcon#*after write, iclass 10, count 0 2006.285.07:21:03.53#ibcon#*before return 0, iclass 10, count 0 2006.285.07:21:03.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:21:03.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:21:03.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.07:21:03.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.07:21:03.53$vck44/vb=5,4 2006.285.07:21:03.53#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.07:21:03.53#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.07:21:03.53#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:03.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:21:03.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:21:03.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:21:03.59#ibcon#enter wrdev, iclass 12, count 2 2006.285.07:21:03.59#ibcon#first serial, iclass 12, count 2 2006.285.07:21:03.59#ibcon#enter sib2, iclass 12, count 2 2006.285.07:21:03.59#ibcon#flushed, iclass 12, count 2 2006.285.07:21:03.59#ibcon#about to write, iclass 12, count 2 2006.285.07:21:03.59#ibcon#wrote, iclass 12, count 2 2006.285.07:21:03.59#ibcon#about to read 3, iclass 12, count 2 2006.285.07:21:03.61#ibcon#read 3, iclass 12, count 2 2006.285.07:21:03.61#ibcon#about to read 4, iclass 12, count 2 2006.285.07:21:03.61#ibcon#read 4, iclass 12, count 2 2006.285.07:21:03.61#ibcon#about to read 5, iclass 12, count 2 2006.285.07:21:03.61#ibcon#read 5, iclass 12, count 2 2006.285.07:21:03.61#ibcon#about to read 6, iclass 12, count 2 2006.285.07:21:03.61#ibcon#read 6, iclass 12, count 2 2006.285.07:21:03.61#ibcon#end of sib2, iclass 12, count 2 2006.285.07:21:03.61#ibcon#*mode == 0, iclass 12, count 2 2006.285.07:21:03.61#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.07:21:03.61#ibcon#[27=AT05-04\r\n] 2006.285.07:21:03.61#ibcon#*before write, iclass 12, count 2 2006.285.07:21:03.61#ibcon#enter sib2, iclass 12, count 2 2006.285.07:21:03.61#ibcon#flushed, iclass 12, count 2 2006.285.07:21:03.61#ibcon#about to write, iclass 12, count 2 2006.285.07:21:03.61#ibcon#wrote, iclass 12, count 2 2006.285.07:21:03.61#ibcon#about to read 3, iclass 12, count 2 2006.285.07:21:03.64#ibcon#read 3, iclass 12, count 2 2006.285.07:21:03.64#ibcon#about to read 4, iclass 12, count 2 2006.285.07:21:03.64#ibcon#read 4, iclass 12, count 2 2006.285.07:21:03.64#ibcon#about to read 5, iclass 12, count 2 2006.285.07:21:03.64#ibcon#read 5, iclass 12, count 2 2006.285.07:21:03.64#ibcon#about to read 6, iclass 12, count 2 2006.285.07:21:03.64#ibcon#read 6, iclass 12, count 2 2006.285.07:21:03.64#ibcon#end of sib2, iclass 12, count 2 2006.285.07:21:03.64#ibcon#*after write, iclass 12, count 2 2006.285.07:21:03.64#ibcon#*before return 0, iclass 12, count 2 2006.285.07:21:03.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:21:03.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:21:03.64#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.07:21:03.64#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:03.64#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:21:03.76#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:21:03.76#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:21:03.76#ibcon#enter wrdev, iclass 12, count 0 2006.285.07:21:03.76#ibcon#first serial, iclass 12, count 0 2006.285.07:21:03.76#ibcon#enter sib2, iclass 12, count 0 2006.285.07:21:03.76#ibcon#flushed, iclass 12, count 0 2006.285.07:21:03.76#ibcon#about to write, iclass 12, count 0 2006.285.07:21:03.76#ibcon#wrote, iclass 12, count 0 2006.285.07:21:03.76#ibcon#about to read 3, iclass 12, count 0 2006.285.07:21:03.78#ibcon#read 3, iclass 12, count 0 2006.285.07:21:03.78#ibcon#about to read 4, iclass 12, count 0 2006.285.07:21:03.78#ibcon#read 4, iclass 12, count 0 2006.285.07:21:03.78#ibcon#about to read 5, iclass 12, count 0 2006.285.07:21:03.78#ibcon#read 5, iclass 12, count 0 2006.285.07:21:03.78#ibcon#about to read 6, iclass 12, count 0 2006.285.07:21:03.78#ibcon#read 6, iclass 12, count 0 2006.285.07:21:03.78#ibcon#end of sib2, iclass 12, count 0 2006.285.07:21:03.78#ibcon#*mode == 0, iclass 12, count 0 2006.285.07:21:03.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.07:21:03.78#ibcon#[27=USB\r\n] 2006.285.07:21:03.78#ibcon#*before write, iclass 12, count 0 2006.285.07:21:03.78#ibcon#enter sib2, iclass 12, count 0 2006.285.07:21:03.78#ibcon#flushed, iclass 12, count 0 2006.285.07:21:03.78#ibcon#about to write, iclass 12, count 0 2006.285.07:21:03.78#ibcon#wrote, iclass 12, count 0 2006.285.07:21:03.78#ibcon#about to read 3, iclass 12, count 0 2006.285.07:21:03.81#ibcon#read 3, iclass 12, count 0 2006.285.07:21:03.81#ibcon#about to read 4, iclass 12, count 0 2006.285.07:21:03.81#ibcon#read 4, iclass 12, count 0 2006.285.07:21:03.81#ibcon#about to read 5, iclass 12, count 0 2006.285.07:21:03.81#ibcon#read 5, iclass 12, count 0 2006.285.07:21:03.81#ibcon#about to read 6, iclass 12, count 0 2006.285.07:21:03.81#ibcon#read 6, iclass 12, count 0 2006.285.07:21:03.81#ibcon#end of sib2, iclass 12, count 0 2006.285.07:21:03.81#ibcon#*after write, iclass 12, count 0 2006.285.07:21:03.81#ibcon#*before return 0, iclass 12, count 0 2006.285.07:21:03.81#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:21:03.81#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:21:03.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.07:21:03.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.07:21:03.81$vck44/vblo=6,719.99 2006.285.07:21:03.81#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.07:21:03.81#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.07:21:03.81#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:03.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:21:03.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:21:03.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:21:03.81#ibcon#enter wrdev, iclass 14, count 0 2006.285.07:21:03.81#ibcon#first serial, iclass 14, count 0 2006.285.07:21:03.81#ibcon#enter sib2, iclass 14, count 0 2006.285.07:21:03.81#ibcon#flushed, iclass 14, count 0 2006.285.07:21:03.81#ibcon#about to write, iclass 14, count 0 2006.285.07:21:03.81#ibcon#wrote, iclass 14, count 0 2006.285.07:21:03.81#ibcon#about to read 3, iclass 14, count 0 2006.285.07:21:03.83#ibcon#read 3, iclass 14, count 0 2006.285.07:21:03.83#ibcon#about to read 4, iclass 14, count 0 2006.285.07:21:03.83#ibcon#read 4, iclass 14, count 0 2006.285.07:21:03.83#ibcon#about to read 5, iclass 14, count 0 2006.285.07:21:03.83#ibcon#read 5, iclass 14, count 0 2006.285.07:21:03.83#ibcon#about to read 6, iclass 14, count 0 2006.285.07:21:03.83#ibcon#read 6, iclass 14, count 0 2006.285.07:21:03.83#ibcon#end of sib2, iclass 14, count 0 2006.285.07:21:03.83#ibcon#*mode == 0, iclass 14, count 0 2006.285.07:21:03.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.07:21:03.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:21:03.83#ibcon#*before write, iclass 14, count 0 2006.285.07:21:03.83#ibcon#enter sib2, iclass 14, count 0 2006.285.07:21:03.83#ibcon#flushed, iclass 14, count 0 2006.285.07:21:03.83#ibcon#about to write, iclass 14, count 0 2006.285.07:21:03.83#ibcon#wrote, iclass 14, count 0 2006.285.07:21:03.83#ibcon#about to read 3, iclass 14, count 0 2006.285.07:21:03.87#ibcon#read 3, iclass 14, count 0 2006.285.07:21:03.87#ibcon#about to read 4, iclass 14, count 0 2006.285.07:21:03.87#ibcon#read 4, iclass 14, count 0 2006.285.07:21:03.87#ibcon#about to read 5, iclass 14, count 0 2006.285.07:21:03.87#ibcon#read 5, iclass 14, count 0 2006.285.07:21:03.87#ibcon#about to read 6, iclass 14, count 0 2006.285.07:21:03.87#ibcon#read 6, iclass 14, count 0 2006.285.07:21:03.87#ibcon#end of sib2, iclass 14, count 0 2006.285.07:21:03.87#ibcon#*after write, iclass 14, count 0 2006.285.07:21:03.87#ibcon#*before return 0, iclass 14, count 0 2006.285.07:21:03.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:21:03.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:21:03.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.07:21:03.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.07:21:03.87$vck44/vb=6,3 2006.285.07:21:03.87#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.07:21:03.87#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.07:21:03.87#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:03.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:21:03.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:21:03.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:21:03.93#ibcon#enter wrdev, iclass 16, count 2 2006.285.07:21:03.93#ibcon#first serial, iclass 16, count 2 2006.285.07:21:03.93#ibcon#enter sib2, iclass 16, count 2 2006.285.07:21:03.93#ibcon#flushed, iclass 16, count 2 2006.285.07:21:03.93#ibcon#about to write, iclass 16, count 2 2006.285.07:21:03.93#ibcon#wrote, iclass 16, count 2 2006.285.07:21:03.93#ibcon#about to read 3, iclass 16, count 2 2006.285.07:21:03.95#ibcon#read 3, iclass 16, count 2 2006.285.07:21:03.95#ibcon#about to read 4, iclass 16, count 2 2006.285.07:21:03.95#ibcon#read 4, iclass 16, count 2 2006.285.07:21:03.95#ibcon#about to read 5, iclass 16, count 2 2006.285.07:21:03.95#ibcon#read 5, iclass 16, count 2 2006.285.07:21:03.95#ibcon#about to read 6, iclass 16, count 2 2006.285.07:21:03.95#ibcon#read 6, iclass 16, count 2 2006.285.07:21:03.95#ibcon#end of sib2, iclass 16, count 2 2006.285.07:21:03.95#ibcon#*mode == 0, iclass 16, count 2 2006.285.07:21:03.95#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.07:21:03.95#ibcon#[27=AT06-03\r\n] 2006.285.07:21:03.95#ibcon#*before write, iclass 16, count 2 2006.285.07:21:03.95#ibcon#enter sib2, iclass 16, count 2 2006.285.07:21:03.95#ibcon#flushed, iclass 16, count 2 2006.285.07:21:03.95#ibcon#about to write, iclass 16, count 2 2006.285.07:21:03.95#ibcon#wrote, iclass 16, count 2 2006.285.07:21:03.95#ibcon#about to read 3, iclass 16, count 2 2006.285.07:21:03.98#ibcon#read 3, iclass 16, count 2 2006.285.07:21:03.98#ibcon#about to read 4, iclass 16, count 2 2006.285.07:21:03.98#ibcon#read 4, iclass 16, count 2 2006.285.07:21:03.98#ibcon#about to read 5, iclass 16, count 2 2006.285.07:21:03.98#ibcon#read 5, iclass 16, count 2 2006.285.07:21:03.98#ibcon#about to read 6, iclass 16, count 2 2006.285.07:21:03.98#ibcon#read 6, iclass 16, count 2 2006.285.07:21:03.98#ibcon#end of sib2, iclass 16, count 2 2006.285.07:21:03.98#ibcon#*after write, iclass 16, count 2 2006.285.07:21:03.98#ibcon#*before return 0, iclass 16, count 2 2006.285.07:21:03.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:21:03.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:21:03.98#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.07:21:03.98#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:03.98#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:21:04.10#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:21:04.10#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:21:04.10#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:21:04.10#ibcon#first serial, iclass 16, count 0 2006.285.07:21:04.10#ibcon#enter sib2, iclass 16, count 0 2006.285.07:21:04.10#ibcon#flushed, iclass 16, count 0 2006.285.07:21:04.10#ibcon#about to write, iclass 16, count 0 2006.285.07:21:04.10#ibcon#wrote, iclass 16, count 0 2006.285.07:21:04.10#ibcon#about to read 3, iclass 16, count 0 2006.285.07:21:04.12#ibcon#read 3, iclass 16, count 0 2006.285.07:21:04.12#ibcon#about to read 4, iclass 16, count 0 2006.285.07:21:04.12#ibcon#read 4, iclass 16, count 0 2006.285.07:21:04.12#ibcon#about to read 5, iclass 16, count 0 2006.285.07:21:04.12#ibcon#read 5, iclass 16, count 0 2006.285.07:21:04.12#ibcon#about to read 6, iclass 16, count 0 2006.285.07:21:04.12#ibcon#read 6, iclass 16, count 0 2006.285.07:21:04.12#ibcon#end of sib2, iclass 16, count 0 2006.285.07:21:04.12#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:21:04.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:21:04.12#ibcon#[27=USB\r\n] 2006.285.07:21:04.12#ibcon#*before write, iclass 16, count 0 2006.285.07:21:04.12#ibcon#enter sib2, iclass 16, count 0 2006.285.07:21:04.12#ibcon#flushed, iclass 16, count 0 2006.285.07:21:04.12#ibcon#about to write, iclass 16, count 0 2006.285.07:21:04.12#ibcon#wrote, iclass 16, count 0 2006.285.07:21:04.12#ibcon#about to read 3, iclass 16, count 0 2006.285.07:21:04.15#ibcon#read 3, iclass 16, count 0 2006.285.07:21:04.15#ibcon#about to read 4, iclass 16, count 0 2006.285.07:21:04.15#ibcon#read 4, iclass 16, count 0 2006.285.07:21:04.15#ibcon#about to read 5, iclass 16, count 0 2006.285.07:21:04.15#ibcon#read 5, iclass 16, count 0 2006.285.07:21:04.15#ibcon#about to read 6, iclass 16, count 0 2006.285.07:21:04.15#ibcon#read 6, iclass 16, count 0 2006.285.07:21:04.15#ibcon#end of sib2, iclass 16, count 0 2006.285.07:21:04.15#ibcon#*after write, iclass 16, count 0 2006.285.07:21:04.15#ibcon#*before return 0, iclass 16, count 0 2006.285.07:21:04.15#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:21:04.15#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:21:04.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:21:04.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:21:04.15$vck44/vblo=7,734.99 2006.285.07:21:04.15#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.07:21:04.15#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.07:21:04.15#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:04.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:21:04.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:21:04.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:21:04.15#ibcon#enter wrdev, iclass 18, count 0 2006.285.07:21:04.15#ibcon#first serial, iclass 18, count 0 2006.285.07:21:04.15#ibcon#enter sib2, iclass 18, count 0 2006.285.07:21:04.15#ibcon#flushed, iclass 18, count 0 2006.285.07:21:04.15#ibcon#about to write, iclass 18, count 0 2006.285.07:21:04.15#ibcon#wrote, iclass 18, count 0 2006.285.07:21:04.15#ibcon#about to read 3, iclass 18, count 0 2006.285.07:21:04.17#ibcon#read 3, iclass 18, count 0 2006.285.07:21:04.17#ibcon#about to read 4, iclass 18, count 0 2006.285.07:21:04.17#ibcon#read 4, iclass 18, count 0 2006.285.07:21:04.17#ibcon#about to read 5, iclass 18, count 0 2006.285.07:21:04.17#ibcon#read 5, iclass 18, count 0 2006.285.07:21:04.17#ibcon#about to read 6, iclass 18, count 0 2006.285.07:21:04.17#ibcon#read 6, iclass 18, count 0 2006.285.07:21:04.17#ibcon#end of sib2, iclass 18, count 0 2006.285.07:21:04.17#ibcon#*mode == 0, iclass 18, count 0 2006.285.07:21:04.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.07:21:04.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:21:04.17#ibcon#*before write, iclass 18, count 0 2006.285.07:21:04.17#ibcon#enter sib2, iclass 18, count 0 2006.285.07:21:04.17#ibcon#flushed, iclass 18, count 0 2006.285.07:21:04.17#ibcon#about to write, iclass 18, count 0 2006.285.07:21:04.17#ibcon#wrote, iclass 18, count 0 2006.285.07:21:04.17#ibcon#about to read 3, iclass 18, count 0 2006.285.07:21:04.21#ibcon#read 3, iclass 18, count 0 2006.285.07:21:04.21#ibcon#about to read 4, iclass 18, count 0 2006.285.07:21:04.21#ibcon#read 4, iclass 18, count 0 2006.285.07:21:04.21#ibcon#about to read 5, iclass 18, count 0 2006.285.07:21:04.21#ibcon#read 5, iclass 18, count 0 2006.285.07:21:04.21#ibcon#about to read 6, iclass 18, count 0 2006.285.07:21:04.21#ibcon#read 6, iclass 18, count 0 2006.285.07:21:04.21#ibcon#end of sib2, iclass 18, count 0 2006.285.07:21:04.21#ibcon#*after write, iclass 18, count 0 2006.285.07:21:04.21#ibcon#*before return 0, iclass 18, count 0 2006.285.07:21:04.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:21:04.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:21:04.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.07:21:04.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.07:21:04.21$vck44/vb=7,4 2006.285.07:21:04.21#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.07:21:04.21#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.07:21:04.21#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:04.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:21:04.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:21:04.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:21:04.27#ibcon#enter wrdev, iclass 20, count 2 2006.285.07:21:04.27#ibcon#first serial, iclass 20, count 2 2006.285.07:21:04.27#ibcon#enter sib2, iclass 20, count 2 2006.285.07:21:04.27#ibcon#flushed, iclass 20, count 2 2006.285.07:21:04.27#ibcon#about to write, iclass 20, count 2 2006.285.07:21:04.27#ibcon#wrote, iclass 20, count 2 2006.285.07:21:04.27#ibcon#about to read 3, iclass 20, count 2 2006.285.07:21:04.29#ibcon#read 3, iclass 20, count 2 2006.285.07:21:04.29#ibcon#about to read 4, iclass 20, count 2 2006.285.07:21:04.29#ibcon#read 4, iclass 20, count 2 2006.285.07:21:04.29#ibcon#about to read 5, iclass 20, count 2 2006.285.07:21:04.29#ibcon#read 5, iclass 20, count 2 2006.285.07:21:04.29#ibcon#about to read 6, iclass 20, count 2 2006.285.07:21:04.29#ibcon#read 6, iclass 20, count 2 2006.285.07:21:04.29#ibcon#end of sib2, iclass 20, count 2 2006.285.07:21:04.29#ibcon#*mode == 0, iclass 20, count 2 2006.285.07:21:04.29#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.07:21:04.29#ibcon#[27=AT07-04\r\n] 2006.285.07:21:04.29#ibcon#*before write, iclass 20, count 2 2006.285.07:21:04.29#ibcon#enter sib2, iclass 20, count 2 2006.285.07:21:04.29#ibcon#flushed, iclass 20, count 2 2006.285.07:21:04.29#ibcon#about to write, iclass 20, count 2 2006.285.07:21:04.29#ibcon#wrote, iclass 20, count 2 2006.285.07:21:04.29#ibcon#about to read 3, iclass 20, count 2 2006.285.07:21:04.32#ibcon#read 3, iclass 20, count 2 2006.285.07:21:04.32#ibcon#about to read 4, iclass 20, count 2 2006.285.07:21:04.32#ibcon#read 4, iclass 20, count 2 2006.285.07:21:04.32#ibcon#about to read 5, iclass 20, count 2 2006.285.07:21:04.32#ibcon#read 5, iclass 20, count 2 2006.285.07:21:04.32#ibcon#about to read 6, iclass 20, count 2 2006.285.07:21:04.32#ibcon#read 6, iclass 20, count 2 2006.285.07:21:04.32#ibcon#end of sib2, iclass 20, count 2 2006.285.07:21:04.32#ibcon#*after write, iclass 20, count 2 2006.285.07:21:04.32#ibcon#*before return 0, iclass 20, count 2 2006.285.07:21:04.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:21:04.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:21:04.32#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.07:21:04.32#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:04.32#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:21:04.44#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:21:04.44#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:21:04.44#ibcon#enter wrdev, iclass 20, count 0 2006.285.07:21:04.44#ibcon#first serial, iclass 20, count 0 2006.285.07:21:04.44#ibcon#enter sib2, iclass 20, count 0 2006.285.07:21:04.44#ibcon#flushed, iclass 20, count 0 2006.285.07:21:04.44#ibcon#about to write, iclass 20, count 0 2006.285.07:21:04.44#ibcon#wrote, iclass 20, count 0 2006.285.07:21:04.44#ibcon#about to read 3, iclass 20, count 0 2006.285.07:21:04.46#ibcon#read 3, iclass 20, count 0 2006.285.07:21:04.46#ibcon#about to read 4, iclass 20, count 0 2006.285.07:21:04.46#ibcon#read 4, iclass 20, count 0 2006.285.07:21:04.46#ibcon#about to read 5, iclass 20, count 0 2006.285.07:21:04.46#ibcon#read 5, iclass 20, count 0 2006.285.07:21:04.46#ibcon#about to read 6, iclass 20, count 0 2006.285.07:21:04.46#ibcon#read 6, iclass 20, count 0 2006.285.07:21:04.46#ibcon#end of sib2, iclass 20, count 0 2006.285.07:21:04.46#ibcon#*mode == 0, iclass 20, count 0 2006.285.07:21:04.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.07:21:04.46#ibcon#[27=USB\r\n] 2006.285.07:21:04.46#ibcon#*before write, iclass 20, count 0 2006.285.07:21:04.46#ibcon#enter sib2, iclass 20, count 0 2006.285.07:21:04.46#ibcon#flushed, iclass 20, count 0 2006.285.07:21:04.46#ibcon#about to write, iclass 20, count 0 2006.285.07:21:04.46#ibcon#wrote, iclass 20, count 0 2006.285.07:21:04.46#ibcon#about to read 3, iclass 20, count 0 2006.285.07:21:04.49#ibcon#read 3, iclass 20, count 0 2006.285.07:21:04.49#ibcon#about to read 4, iclass 20, count 0 2006.285.07:21:04.49#ibcon#read 4, iclass 20, count 0 2006.285.07:21:04.49#ibcon#about to read 5, iclass 20, count 0 2006.285.07:21:04.49#ibcon#read 5, iclass 20, count 0 2006.285.07:21:04.49#ibcon#about to read 6, iclass 20, count 0 2006.285.07:21:04.49#ibcon#read 6, iclass 20, count 0 2006.285.07:21:04.49#ibcon#end of sib2, iclass 20, count 0 2006.285.07:21:04.49#ibcon#*after write, iclass 20, count 0 2006.285.07:21:04.49#ibcon#*before return 0, iclass 20, count 0 2006.285.07:21:04.49#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:21:04.49#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:21:04.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.07:21:04.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.07:21:04.49$vck44/vblo=8,744.99 2006.285.07:21:04.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.07:21:04.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.07:21:04.49#ibcon#ireg 17 cls_cnt 0 2006.285.07:21:04.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:21:04.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:21:04.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:21:04.49#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:21:04.49#ibcon#first serial, iclass 22, count 0 2006.285.07:21:04.49#ibcon#enter sib2, iclass 22, count 0 2006.285.07:21:04.49#ibcon#flushed, iclass 22, count 0 2006.285.07:21:04.49#ibcon#about to write, iclass 22, count 0 2006.285.07:21:04.49#ibcon#wrote, iclass 22, count 0 2006.285.07:21:04.49#ibcon#about to read 3, iclass 22, count 0 2006.285.07:21:04.51#ibcon#read 3, iclass 22, count 0 2006.285.07:21:04.51#ibcon#about to read 4, iclass 22, count 0 2006.285.07:21:04.51#ibcon#read 4, iclass 22, count 0 2006.285.07:21:04.51#ibcon#about to read 5, iclass 22, count 0 2006.285.07:21:04.51#ibcon#read 5, iclass 22, count 0 2006.285.07:21:04.51#ibcon#about to read 6, iclass 22, count 0 2006.285.07:21:04.51#ibcon#read 6, iclass 22, count 0 2006.285.07:21:04.51#ibcon#end of sib2, iclass 22, count 0 2006.285.07:21:04.51#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:21:04.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:21:04.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:21:04.51#ibcon#*before write, iclass 22, count 0 2006.285.07:21:04.51#ibcon#enter sib2, iclass 22, count 0 2006.285.07:21:04.51#ibcon#flushed, iclass 22, count 0 2006.285.07:21:04.51#ibcon#about to write, iclass 22, count 0 2006.285.07:21:04.51#ibcon#wrote, iclass 22, count 0 2006.285.07:21:04.51#ibcon#about to read 3, iclass 22, count 0 2006.285.07:21:04.55#ibcon#read 3, iclass 22, count 0 2006.285.07:21:04.55#ibcon#about to read 4, iclass 22, count 0 2006.285.07:21:04.55#ibcon#read 4, iclass 22, count 0 2006.285.07:21:04.55#ibcon#about to read 5, iclass 22, count 0 2006.285.07:21:04.55#ibcon#read 5, iclass 22, count 0 2006.285.07:21:04.55#ibcon#about to read 6, iclass 22, count 0 2006.285.07:21:04.55#ibcon#read 6, iclass 22, count 0 2006.285.07:21:04.55#ibcon#end of sib2, iclass 22, count 0 2006.285.07:21:04.55#ibcon#*after write, iclass 22, count 0 2006.285.07:21:04.55#ibcon#*before return 0, iclass 22, count 0 2006.285.07:21:04.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:21:04.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:21:04.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:21:04.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:21:04.55$vck44/vb=8,4 2006.285.07:21:04.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.07:21:04.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.07:21:04.55#ibcon#ireg 11 cls_cnt 2 2006.285.07:21:04.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:21:04.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:21:04.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:21:04.61#ibcon#enter wrdev, iclass 24, count 2 2006.285.07:21:04.61#ibcon#first serial, iclass 24, count 2 2006.285.07:21:04.61#ibcon#enter sib2, iclass 24, count 2 2006.285.07:21:04.61#ibcon#flushed, iclass 24, count 2 2006.285.07:21:04.61#ibcon#about to write, iclass 24, count 2 2006.285.07:21:04.61#ibcon#wrote, iclass 24, count 2 2006.285.07:21:04.61#ibcon#about to read 3, iclass 24, count 2 2006.285.07:21:04.63#ibcon#read 3, iclass 24, count 2 2006.285.07:21:04.63#ibcon#about to read 4, iclass 24, count 2 2006.285.07:21:04.63#ibcon#read 4, iclass 24, count 2 2006.285.07:21:04.63#ibcon#about to read 5, iclass 24, count 2 2006.285.07:21:04.63#ibcon#read 5, iclass 24, count 2 2006.285.07:21:04.63#ibcon#about to read 6, iclass 24, count 2 2006.285.07:21:04.63#ibcon#read 6, iclass 24, count 2 2006.285.07:21:04.63#ibcon#end of sib2, iclass 24, count 2 2006.285.07:21:04.63#ibcon#*mode == 0, iclass 24, count 2 2006.285.07:21:04.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.07:21:04.63#ibcon#[27=AT08-04\r\n] 2006.285.07:21:04.63#ibcon#*before write, iclass 24, count 2 2006.285.07:21:04.63#ibcon#enter sib2, iclass 24, count 2 2006.285.07:21:04.63#ibcon#flushed, iclass 24, count 2 2006.285.07:21:04.63#ibcon#about to write, iclass 24, count 2 2006.285.07:21:04.63#ibcon#wrote, iclass 24, count 2 2006.285.07:21:04.63#ibcon#about to read 3, iclass 24, count 2 2006.285.07:21:04.66#ibcon#read 3, iclass 24, count 2 2006.285.07:21:04.66#ibcon#about to read 4, iclass 24, count 2 2006.285.07:21:04.66#ibcon#read 4, iclass 24, count 2 2006.285.07:21:04.66#ibcon#about to read 5, iclass 24, count 2 2006.285.07:21:04.66#ibcon#read 5, iclass 24, count 2 2006.285.07:21:04.66#ibcon#about to read 6, iclass 24, count 2 2006.285.07:21:04.66#ibcon#read 6, iclass 24, count 2 2006.285.07:21:04.66#ibcon#end of sib2, iclass 24, count 2 2006.285.07:21:04.66#ibcon#*after write, iclass 24, count 2 2006.285.07:21:04.66#ibcon#*before return 0, iclass 24, count 2 2006.285.07:21:04.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:21:04.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:21:04.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.07:21:04.66#ibcon#ireg 7 cls_cnt 0 2006.285.07:21:04.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:21:04.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:21:04.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:21:04.78#ibcon#enter wrdev, iclass 24, count 0 2006.285.07:21:04.78#ibcon#first serial, iclass 24, count 0 2006.285.07:21:04.78#ibcon#enter sib2, iclass 24, count 0 2006.285.07:21:04.78#ibcon#flushed, iclass 24, count 0 2006.285.07:21:04.78#ibcon#about to write, iclass 24, count 0 2006.285.07:21:04.78#ibcon#wrote, iclass 24, count 0 2006.285.07:21:04.78#ibcon#about to read 3, iclass 24, count 0 2006.285.07:21:04.80#ibcon#read 3, iclass 24, count 0 2006.285.07:21:04.80#ibcon#about to read 4, iclass 24, count 0 2006.285.07:21:04.80#ibcon#read 4, iclass 24, count 0 2006.285.07:21:04.80#ibcon#about to read 5, iclass 24, count 0 2006.285.07:21:04.80#ibcon#read 5, iclass 24, count 0 2006.285.07:21:04.80#ibcon#about to read 6, iclass 24, count 0 2006.285.07:21:04.80#ibcon#read 6, iclass 24, count 0 2006.285.07:21:04.80#ibcon#end of sib2, iclass 24, count 0 2006.285.07:21:04.80#ibcon#*mode == 0, iclass 24, count 0 2006.285.07:21:04.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.07:21:04.80#ibcon#[27=USB\r\n] 2006.285.07:21:04.80#ibcon#*before write, iclass 24, count 0 2006.285.07:21:04.80#ibcon#enter sib2, iclass 24, count 0 2006.285.07:21:04.80#ibcon#flushed, iclass 24, count 0 2006.285.07:21:04.80#ibcon#about to write, iclass 24, count 0 2006.285.07:21:04.80#ibcon#wrote, iclass 24, count 0 2006.285.07:21:04.80#ibcon#about to read 3, iclass 24, count 0 2006.285.07:21:04.83#ibcon#read 3, iclass 24, count 0 2006.285.07:21:04.83#ibcon#about to read 4, iclass 24, count 0 2006.285.07:21:04.83#ibcon#read 4, iclass 24, count 0 2006.285.07:21:04.83#ibcon#about to read 5, iclass 24, count 0 2006.285.07:21:04.83#ibcon#read 5, iclass 24, count 0 2006.285.07:21:04.83#ibcon#about to read 6, iclass 24, count 0 2006.285.07:21:04.83#ibcon#read 6, iclass 24, count 0 2006.285.07:21:04.83#ibcon#end of sib2, iclass 24, count 0 2006.285.07:21:04.83#ibcon#*after write, iclass 24, count 0 2006.285.07:21:04.83#ibcon#*before return 0, iclass 24, count 0 2006.285.07:21:04.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:21:04.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:21:04.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.07:21:04.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.07:21:04.83$vck44/vabw=wide 2006.285.07:21:04.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.07:21:04.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.07:21:04.83#ibcon#ireg 8 cls_cnt 0 2006.285.07:21:04.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:21:04.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:21:04.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:21:04.83#ibcon#enter wrdev, iclass 26, count 0 2006.285.07:21:04.83#ibcon#first serial, iclass 26, count 0 2006.285.07:21:04.83#ibcon#enter sib2, iclass 26, count 0 2006.285.07:21:04.83#ibcon#flushed, iclass 26, count 0 2006.285.07:21:04.83#ibcon#about to write, iclass 26, count 0 2006.285.07:21:04.83#ibcon#wrote, iclass 26, count 0 2006.285.07:21:04.83#ibcon#about to read 3, iclass 26, count 0 2006.285.07:21:04.85#ibcon#read 3, iclass 26, count 0 2006.285.07:21:04.85#ibcon#about to read 4, iclass 26, count 0 2006.285.07:21:04.85#ibcon#read 4, iclass 26, count 0 2006.285.07:21:04.85#ibcon#about to read 5, iclass 26, count 0 2006.285.07:21:04.85#ibcon#read 5, iclass 26, count 0 2006.285.07:21:04.85#ibcon#about to read 6, iclass 26, count 0 2006.285.07:21:04.85#ibcon#read 6, iclass 26, count 0 2006.285.07:21:04.85#ibcon#end of sib2, iclass 26, count 0 2006.285.07:21:04.85#ibcon#*mode == 0, iclass 26, count 0 2006.285.07:21:04.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.07:21:04.85#ibcon#[25=BW32\r\n] 2006.285.07:21:04.85#ibcon#*before write, iclass 26, count 0 2006.285.07:21:04.85#ibcon#enter sib2, iclass 26, count 0 2006.285.07:21:04.85#ibcon#flushed, iclass 26, count 0 2006.285.07:21:04.85#ibcon#about to write, iclass 26, count 0 2006.285.07:21:04.85#ibcon#wrote, iclass 26, count 0 2006.285.07:21:04.85#ibcon#about to read 3, iclass 26, count 0 2006.285.07:21:04.88#ibcon#read 3, iclass 26, count 0 2006.285.07:21:04.88#ibcon#about to read 4, iclass 26, count 0 2006.285.07:21:04.88#ibcon#read 4, iclass 26, count 0 2006.285.07:21:04.88#ibcon#about to read 5, iclass 26, count 0 2006.285.07:21:04.88#ibcon#read 5, iclass 26, count 0 2006.285.07:21:04.88#ibcon#about to read 6, iclass 26, count 0 2006.285.07:21:04.88#ibcon#read 6, iclass 26, count 0 2006.285.07:21:04.88#ibcon#end of sib2, iclass 26, count 0 2006.285.07:21:04.88#ibcon#*after write, iclass 26, count 0 2006.285.07:21:04.88#ibcon#*before return 0, iclass 26, count 0 2006.285.07:21:04.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:21:04.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:21:04.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.07:21:04.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.07:21:04.88$vck44/vbbw=wide 2006.285.07:21:04.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.07:21:04.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.07:21:04.88#ibcon#ireg 8 cls_cnt 0 2006.285.07:21:04.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:21:04.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:21:04.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:21:04.95#ibcon#enter wrdev, iclass 28, count 0 2006.285.07:21:04.95#ibcon#first serial, iclass 28, count 0 2006.285.07:21:04.95#ibcon#enter sib2, iclass 28, count 0 2006.285.07:21:04.95#ibcon#flushed, iclass 28, count 0 2006.285.07:21:04.95#ibcon#about to write, iclass 28, count 0 2006.285.07:21:04.95#ibcon#wrote, iclass 28, count 0 2006.285.07:21:04.95#ibcon#about to read 3, iclass 28, count 0 2006.285.07:21:04.97#ibcon#read 3, iclass 28, count 0 2006.285.07:21:04.97#ibcon#about to read 4, iclass 28, count 0 2006.285.07:21:04.97#ibcon#read 4, iclass 28, count 0 2006.285.07:21:04.97#ibcon#about to read 5, iclass 28, count 0 2006.285.07:21:04.97#ibcon#read 5, iclass 28, count 0 2006.285.07:21:04.97#ibcon#about to read 6, iclass 28, count 0 2006.285.07:21:04.97#ibcon#read 6, iclass 28, count 0 2006.285.07:21:04.97#ibcon#end of sib2, iclass 28, count 0 2006.285.07:21:04.97#ibcon#*mode == 0, iclass 28, count 0 2006.285.07:21:04.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.07:21:04.97#ibcon#[27=BW32\r\n] 2006.285.07:21:04.97#ibcon#*before write, iclass 28, count 0 2006.285.07:21:04.97#ibcon#enter sib2, iclass 28, count 0 2006.285.07:21:04.97#ibcon#flushed, iclass 28, count 0 2006.285.07:21:04.97#ibcon#about to write, iclass 28, count 0 2006.285.07:21:04.97#ibcon#wrote, iclass 28, count 0 2006.285.07:21:04.97#ibcon#about to read 3, iclass 28, count 0 2006.285.07:21:05.00#ibcon#read 3, iclass 28, count 0 2006.285.07:21:05.00#ibcon#about to read 4, iclass 28, count 0 2006.285.07:21:05.00#ibcon#read 4, iclass 28, count 0 2006.285.07:21:05.00#ibcon#about to read 5, iclass 28, count 0 2006.285.07:21:05.00#ibcon#read 5, iclass 28, count 0 2006.285.07:21:05.00#ibcon#about to read 6, iclass 28, count 0 2006.285.07:21:05.00#ibcon#read 6, iclass 28, count 0 2006.285.07:21:05.00#ibcon#end of sib2, iclass 28, count 0 2006.285.07:21:05.00#ibcon#*after write, iclass 28, count 0 2006.285.07:21:05.00#ibcon#*before return 0, iclass 28, count 0 2006.285.07:21:05.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:21:05.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:21:05.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.07:21:05.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.07:21:05.00$setupk4/ifdk4 2006.285.07:21:05.00$ifdk4/lo= 2006.285.07:21:05.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:21:05.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:21:05.00$ifdk4/patch= 2006.285.07:21:05.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:21:05.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:21:05.00$setupk4/!*+20s 2006.285.07:21:10.94#abcon#<5=/05 3.1 6.2 23.90 751014.3\r\n> 2006.285.07:21:10.96#abcon#{5=INTERFACE CLEAR} 2006.285.07:21:11.02#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:21:19.49$setupk4/"tpicd 2006.285.07:21:19.49$setupk4/echo=off 2006.285.07:21:19.49$setupk4/xlog=off 2006.285.07:21:19.49:!2006.285.07:23:59 2006.285.07:21:24.14#trakl#Source acquired 2006.285.07:21:24.14#flagr#flagr/antenna,acquired 2006.285.07:23:21.13#trakl#Off source 2006.285.07:23:21.13?ERROR st -7 Antenna off-source! 2006.285.07:23:21.13#trakl#az 204.786 el 24.006 azerr*cos(el) 0.0161 elerr -0.0017 2006.285.07:23:21.13#flagr#flagr/antenna,off-source 2006.285.07:23:27.13#trakl#Source re-acquired 2006.285.07:23:27.13#flagr#flagr/antenna,re-acquired 2006.285.07:23:59.00:preob 2006.285.07:23:59.14/onsource/TRACKING 2006.285.07:23:59.14:!2006.285.07:24:09 2006.285.07:24:09.00:"tape 2006.285.07:24:09.00:"st=record 2006.285.07:24:09.00:data_valid=on 2006.285.07:24:09.00:midob 2006.285.07:24:09.14/onsource/TRACKING 2006.285.07:24:09.14/wx/23.83,1014.3,76 2006.285.07:24:09.35/cable/+6.4728E-03 2006.285.07:24:10.44/va/01,07,usb,yes,33,36 2006.285.07:24:10.44/va/02,06,usb,yes,33,34 2006.285.07:24:10.44/va/03,07,usb,yes,33,34 2006.285.07:24:10.44/va/04,06,usb,yes,34,36 2006.285.07:24:10.44/va/05,03,usb,yes,34,34 2006.285.07:24:10.44/va/06,04,usb,yes,30,30 2006.285.07:24:10.44/va/07,04,usb,yes,31,32 2006.285.07:24:10.44/va/08,03,usb,yes,31,39 2006.285.07:24:10.67/valo/01,524.99,yes,locked 2006.285.07:24:10.67/valo/02,534.99,yes,locked 2006.285.07:24:10.67/valo/03,564.99,yes,locked 2006.285.07:24:10.67/valo/04,624.99,yes,locked 2006.285.07:24:10.67/valo/05,734.99,yes,locked 2006.285.07:24:10.67/valo/06,814.99,yes,locked 2006.285.07:24:10.67/valo/07,864.99,yes,locked 2006.285.07:24:10.67/valo/08,884.99,yes,locked 2006.285.07:24:11.76/vb/01,04,usb,yes,31,29 2006.285.07:24:11.76/vb/02,05,usb,yes,30,30 2006.285.07:24:11.76/vb/03,04,usb,yes,31,34 2006.285.07:24:11.76/vb/04,05,usb,yes,31,30 2006.285.07:24:11.76/vb/05,04,usb,yes,27,30 2006.285.07:24:11.76/vb/06,03,usb,yes,39,35 2006.285.07:24:11.76/vb/07,04,usb,yes,32,32 2006.285.07:24:11.76/vb/08,04,usb,yes,29,33 2006.285.07:24:12.00/vblo/01,629.99,yes,locked 2006.285.07:24:12.00/vblo/02,634.99,yes,locked 2006.285.07:24:12.00/vblo/03,649.99,yes,locked 2006.285.07:24:12.00/vblo/04,679.99,yes,locked 2006.285.07:24:12.00/vblo/05,709.99,yes,locked 2006.285.07:24:12.00/vblo/06,719.99,yes,locked 2006.285.07:24:12.00/vblo/07,734.99,yes,locked 2006.285.07:24:12.00/vblo/08,744.99,yes,locked 2006.285.07:24:12.15/vabw/8 2006.285.07:24:12.30/vbbw/8 2006.285.07:24:12.39/xfe/off,on,12.2 2006.285.07:24:12.76/ifatt/23,28,28,28 2006.285.07:24:13.07/fmout-gps/S +2.63E-07 2006.285.07:24:13.09:!2006.285.07:28:59 2006.285.07:28:59.00:data_valid=off 2006.285.07:28:59.00:"et 2006.285.07:28:59.00:!+3s 2006.285.07:29:02.01:"tape 2006.285.07:29:02.01:postob 2006.285.07:29:02.20/cable/+6.4734E-03 2006.285.07:29:02.20/wx/23.72,1014.4,76 2006.285.07:29:03.07/fmout-gps/S +2.67E-07 2006.285.07:29:03.07:scan_name=285-0732,jd0610,40 2006.285.07:29:03.07:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.285.07:29:04.14#flagr#flagr/antenna,new-source 2006.285.07:29:04.14:checkk5 2006.285.07:29:04.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:29:04.99/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:29:05.49/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:29:06.13/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:29:06.52/chk_obsdata//k5ts1/T2850724??a.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.07:29:06.92/chk_obsdata//k5ts2/T2850724??b.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.07:29:07.33/chk_obsdata//k5ts3/T2850724??c.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.07:29:07.72/chk_obsdata//k5ts4/T2850724??d.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.07:29:08.72/k5log//k5ts1_log_newline 2006.285.07:29:09.56/k5log//k5ts2_log_newline 2006.285.07:29:10.38/k5log//k5ts3_log_newline 2006.285.07:29:11.10/k5log//k5ts4_log_newline 2006.285.07:29:11.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:29:11.13:setupk4=1 2006.285.07:29:11.13$setupk4/echo=on 2006.285.07:29:11.13$setupk4/pcalon 2006.285.07:29:11.13$pcalon/"no phase cal control is implemented here 2006.285.07:29:11.13$setupk4/"tpicd=stop 2006.285.07:29:11.13$setupk4/"rec=synch_on 2006.285.07:29:11.13$setupk4/"rec_mode=128 2006.285.07:29:11.13$setupk4/!* 2006.285.07:29:11.13$setupk4/recpk4 2006.285.07:29:11.13$recpk4/recpatch= 2006.285.07:29:11.13$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:29:11.13$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:29:11.13$setupk4/vck44 2006.285.07:29:11.13$vck44/valo=1,524.99 2006.285.07:29:11.13#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.07:29:11.13#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.07:29:11.13#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:11.13#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:29:11.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:29:11.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:29:11.13#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:29:11.13#ibcon#first serial, iclass 11, count 0 2006.285.07:29:11.13#ibcon#enter sib2, iclass 11, count 0 2006.285.07:29:11.13#ibcon#flushed, iclass 11, count 0 2006.285.07:29:11.13#ibcon#about to write, iclass 11, count 0 2006.285.07:29:11.13#ibcon#wrote, iclass 11, count 0 2006.285.07:29:11.13#ibcon#about to read 3, iclass 11, count 0 2006.285.07:29:11.15#ibcon#read 3, iclass 11, count 0 2006.285.07:29:11.15#ibcon#about to read 4, iclass 11, count 0 2006.285.07:29:11.15#ibcon#read 4, iclass 11, count 0 2006.285.07:29:11.15#ibcon#about to read 5, iclass 11, count 0 2006.285.07:29:11.15#ibcon#read 5, iclass 11, count 0 2006.285.07:29:11.15#ibcon#about to read 6, iclass 11, count 0 2006.285.07:29:11.15#ibcon#read 6, iclass 11, count 0 2006.285.07:29:11.15#ibcon#end of sib2, iclass 11, count 0 2006.285.07:29:11.15#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:29:11.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:29:11.15#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:29:11.15#ibcon#*before write, iclass 11, count 0 2006.285.07:29:11.15#ibcon#enter sib2, iclass 11, count 0 2006.285.07:29:11.15#ibcon#flushed, iclass 11, count 0 2006.285.07:29:11.15#ibcon#about to write, iclass 11, count 0 2006.285.07:29:11.15#ibcon#wrote, iclass 11, count 0 2006.285.07:29:11.15#ibcon#about to read 3, iclass 11, count 0 2006.285.07:29:11.20#ibcon#read 3, iclass 11, count 0 2006.285.07:29:11.20#ibcon#about to read 4, iclass 11, count 0 2006.285.07:29:11.20#ibcon#read 4, iclass 11, count 0 2006.285.07:29:11.20#ibcon#about to read 5, iclass 11, count 0 2006.285.07:29:11.20#ibcon#read 5, iclass 11, count 0 2006.285.07:29:11.20#ibcon#about to read 6, iclass 11, count 0 2006.285.07:29:11.20#ibcon#read 6, iclass 11, count 0 2006.285.07:29:11.20#ibcon#end of sib2, iclass 11, count 0 2006.285.07:29:11.20#ibcon#*after write, iclass 11, count 0 2006.285.07:29:11.20#ibcon#*before return 0, iclass 11, count 0 2006.285.07:29:11.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:29:11.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:29:11.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:29:11.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:29:11.20$vck44/va=1,7 2006.285.07:29:11.20#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.07:29:11.20#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.07:29:11.20#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:11.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:29:11.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:29:11.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:29:11.20#ibcon#enter wrdev, iclass 13, count 2 2006.285.07:29:11.20#ibcon#first serial, iclass 13, count 2 2006.285.07:29:11.20#ibcon#enter sib2, iclass 13, count 2 2006.285.07:29:11.20#ibcon#flushed, iclass 13, count 2 2006.285.07:29:11.20#ibcon#about to write, iclass 13, count 2 2006.285.07:29:11.20#ibcon#wrote, iclass 13, count 2 2006.285.07:29:11.20#ibcon#about to read 3, iclass 13, count 2 2006.285.07:29:11.22#ibcon#read 3, iclass 13, count 2 2006.285.07:29:11.22#ibcon#about to read 4, iclass 13, count 2 2006.285.07:29:11.22#ibcon#read 4, iclass 13, count 2 2006.285.07:29:11.22#ibcon#about to read 5, iclass 13, count 2 2006.285.07:29:11.22#ibcon#read 5, iclass 13, count 2 2006.285.07:29:11.22#ibcon#about to read 6, iclass 13, count 2 2006.285.07:29:11.22#ibcon#read 6, iclass 13, count 2 2006.285.07:29:11.22#ibcon#end of sib2, iclass 13, count 2 2006.285.07:29:11.22#ibcon#*mode == 0, iclass 13, count 2 2006.285.07:29:11.22#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.07:29:11.22#ibcon#[25=AT01-07\r\n] 2006.285.07:29:11.22#ibcon#*before write, iclass 13, count 2 2006.285.07:29:11.22#ibcon#enter sib2, iclass 13, count 2 2006.285.07:29:11.22#ibcon#flushed, iclass 13, count 2 2006.285.07:29:11.22#ibcon#about to write, iclass 13, count 2 2006.285.07:29:11.22#ibcon#wrote, iclass 13, count 2 2006.285.07:29:11.22#ibcon#about to read 3, iclass 13, count 2 2006.285.07:29:11.25#ibcon#read 3, iclass 13, count 2 2006.285.07:29:11.25#ibcon#about to read 4, iclass 13, count 2 2006.285.07:29:11.25#ibcon#read 4, iclass 13, count 2 2006.285.07:29:11.25#ibcon#about to read 5, iclass 13, count 2 2006.285.07:29:11.25#ibcon#read 5, iclass 13, count 2 2006.285.07:29:11.25#ibcon#about to read 6, iclass 13, count 2 2006.285.07:29:11.25#ibcon#read 6, iclass 13, count 2 2006.285.07:29:11.25#ibcon#end of sib2, iclass 13, count 2 2006.285.07:29:11.25#ibcon#*after write, iclass 13, count 2 2006.285.07:29:11.25#ibcon#*before return 0, iclass 13, count 2 2006.285.07:29:11.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:29:11.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:29:11.25#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.07:29:11.25#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:11.25#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:29:11.37#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:29:11.37#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:29:11.37#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:29:11.37#ibcon#first serial, iclass 13, count 0 2006.285.07:29:11.37#ibcon#enter sib2, iclass 13, count 0 2006.285.07:29:11.37#ibcon#flushed, iclass 13, count 0 2006.285.07:29:11.37#ibcon#about to write, iclass 13, count 0 2006.285.07:29:11.37#ibcon#wrote, iclass 13, count 0 2006.285.07:29:11.37#ibcon#about to read 3, iclass 13, count 0 2006.285.07:29:11.39#ibcon#read 3, iclass 13, count 0 2006.285.07:29:11.39#ibcon#about to read 4, iclass 13, count 0 2006.285.07:29:11.39#ibcon#read 4, iclass 13, count 0 2006.285.07:29:11.39#ibcon#about to read 5, iclass 13, count 0 2006.285.07:29:11.39#ibcon#read 5, iclass 13, count 0 2006.285.07:29:11.39#ibcon#about to read 6, iclass 13, count 0 2006.285.07:29:11.39#ibcon#read 6, iclass 13, count 0 2006.285.07:29:11.39#ibcon#end of sib2, iclass 13, count 0 2006.285.07:29:11.39#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:29:11.39#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:29:11.39#ibcon#[25=USB\r\n] 2006.285.07:29:11.39#ibcon#*before write, iclass 13, count 0 2006.285.07:29:11.39#ibcon#enter sib2, iclass 13, count 0 2006.285.07:29:11.39#ibcon#flushed, iclass 13, count 0 2006.285.07:29:11.39#ibcon#about to write, iclass 13, count 0 2006.285.07:29:11.39#ibcon#wrote, iclass 13, count 0 2006.285.07:29:11.39#ibcon#about to read 3, iclass 13, count 0 2006.285.07:29:11.42#ibcon#read 3, iclass 13, count 0 2006.285.07:29:11.42#ibcon#about to read 4, iclass 13, count 0 2006.285.07:29:11.42#ibcon#read 4, iclass 13, count 0 2006.285.07:29:11.42#ibcon#about to read 5, iclass 13, count 0 2006.285.07:29:11.42#ibcon#read 5, iclass 13, count 0 2006.285.07:29:11.42#ibcon#about to read 6, iclass 13, count 0 2006.285.07:29:11.42#ibcon#read 6, iclass 13, count 0 2006.285.07:29:11.42#ibcon#end of sib2, iclass 13, count 0 2006.285.07:29:11.42#ibcon#*after write, iclass 13, count 0 2006.285.07:29:11.42#ibcon#*before return 0, iclass 13, count 0 2006.285.07:29:11.42#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:29:11.42#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:29:11.42#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:29:11.42#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:29:11.42$vck44/valo=2,534.99 2006.285.07:29:11.42#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.07:29:11.42#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.07:29:11.42#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:11.42#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:29:11.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:29:11.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:29:11.42#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:29:11.42#ibcon#first serial, iclass 15, count 0 2006.285.07:29:11.42#ibcon#enter sib2, iclass 15, count 0 2006.285.07:29:11.42#ibcon#flushed, iclass 15, count 0 2006.285.07:29:11.42#ibcon#about to write, iclass 15, count 0 2006.285.07:29:11.42#ibcon#wrote, iclass 15, count 0 2006.285.07:29:11.42#ibcon#about to read 3, iclass 15, count 0 2006.285.07:29:11.44#ibcon#read 3, iclass 15, count 0 2006.285.07:29:11.44#ibcon#about to read 4, iclass 15, count 0 2006.285.07:29:11.44#ibcon#read 4, iclass 15, count 0 2006.285.07:29:11.44#ibcon#about to read 5, iclass 15, count 0 2006.285.07:29:11.44#ibcon#read 5, iclass 15, count 0 2006.285.07:29:11.44#ibcon#about to read 6, iclass 15, count 0 2006.285.07:29:11.44#ibcon#read 6, iclass 15, count 0 2006.285.07:29:11.44#ibcon#end of sib2, iclass 15, count 0 2006.285.07:29:11.44#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:29:11.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:29:11.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:29:11.44#ibcon#*before write, iclass 15, count 0 2006.285.07:29:11.44#ibcon#enter sib2, iclass 15, count 0 2006.285.07:29:11.44#ibcon#flushed, iclass 15, count 0 2006.285.07:29:11.44#ibcon#about to write, iclass 15, count 0 2006.285.07:29:11.44#ibcon#wrote, iclass 15, count 0 2006.285.07:29:11.44#ibcon#about to read 3, iclass 15, count 0 2006.285.07:29:11.48#ibcon#read 3, iclass 15, count 0 2006.285.07:29:11.48#ibcon#about to read 4, iclass 15, count 0 2006.285.07:29:11.48#ibcon#read 4, iclass 15, count 0 2006.285.07:29:11.48#ibcon#about to read 5, iclass 15, count 0 2006.285.07:29:11.48#ibcon#read 5, iclass 15, count 0 2006.285.07:29:11.48#ibcon#about to read 6, iclass 15, count 0 2006.285.07:29:11.48#ibcon#read 6, iclass 15, count 0 2006.285.07:29:11.48#ibcon#end of sib2, iclass 15, count 0 2006.285.07:29:11.48#ibcon#*after write, iclass 15, count 0 2006.285.07:29:11.48#ibcon#*before return 0, iclass 15, count 0 2006.285.07:29:11.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:29:11.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:29:11.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:29:11.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:29:11.48$vck44/va=2,6 2006.285.07:29:11.48#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.07:29:11.48#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.07:29:11.48#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:11.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:29:11.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:29:11.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:29:11.54#ibcon#enter wrdev, iclass 17, count 2 2006.285.07:29:11.54#ibcon#first serial, iclass 17, count 2 2006.285.07:29:11.54#ibcon#enter sib2, iclass 17, count 2 2006.285.07:29:11.54#ibcon#flushed, iclass 17, count 2 2006.285.07:29:11.54#ibcon#about to write, iclass 17, count 2 2006.285.07:29:11.54#ibcon#wrote, iclass 17, count 2 2006.285.07:29:11.54#ibcon#about to read 3, iclass 17, count 2 2006.285.07:29:11.56#ibcon#read 3, iclass 17, count 2 2006.285.07:29:11.56#ibcon#about to read 4, iclass 17, count 2 2006.285.07:29:11.56#ibcon#read 4, iclass 17, count 2 2006.285.07:29:11.56#ibcon#about to read 5, iclass 17, count 2 2006.285.07:29:11.56#ibcon#read 5, iclass 17, count 2 2006.285.07:29:11.56#ibcon#about to read 6, iclass 17, count 2 2006.285.07:29:11.56#ibcon#read 6, iclass 17, count 2 2006.285.07:29:11.56#ibcon#end of sib2, iclass 17, count 2 2006.285.07:29:11.56#ibcon#*mode == 0, iclass 17, count 2 2006.285.07:29:11.56#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.07:29:11.56#ibcon#[25=AT02-06\r\n] 2006.285.07:29:11.56#ibcon#*before write, iclass 17, count 2 2006.285.07:29:11.56#ibcon#enter sib2, iclass 17, count 2 2006.285.07:29:11.56#ibcon#flushed, iclass 17, count 2 2006.285.07:29:11.56#ibcon#about to write, iclass 17, count 2 2006.285.07:29:11.56#ibcon#wrote, iclass 17, count 2 2006.285.07:29:11.56#ibcon#about to read 3, iclass 17, count 2 2006.285.07:29:11.59#ibcon#read 3, iclass 17, count 2 2006.285.07:29:11.59#ibcon#about to read 4, iclass 17, count 2 2006.285.07:29:11.59#ibcon#read 4, iclass 17, count 2 2006.285.07:29:11.59#ibcon#about to read 5, iclass 17, count 2 2006.285.07:29:11.59#ibcon#read 5, iclass 17, count 2 2006.285.07:29:11.59#ibcon#about to read 6, iclass 17, count 2 2006.285.07:29:11.59#ibcon#read 6, iclass 17, count 2 2006.285.07:29:11.59#ibcon#end of sib2, iclass 17, count 2 2006.285.07:29:11.59#ibcon#*after write, iclass 17, count 2 2006.285.07:29:11.59#ibcon#*before return 0, iclass 17, count 2 2006.285.07:29:11.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:29:11.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:29:11.59#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.07:29:11.59#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:11.59#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:29:11.71#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:29:11.71#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:29:11.71#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:29:11.71#ibcon#first serial, iclass 17, count 0 2006.285.07:29:11.71#ibcon#enter sib2, iclass 17, count 0 2006.285.07:29:11.71#ibcon#flushed, iclass 17, count 0 2006.285.07:29:11.71#ibcon#about to write, iclass 17, count 0 2006.285.07:29:11.71#ibcon#wrote, iclass 17, count 0 2006.285.07:29:11.71#ibcon#about to read 3, iclass 17, count 0 2006.285.07:29:11.73#ibcon#read 3, iclass 17, count 0 2006.285.07:29:11.73#ibcon#about to read 4, iclass 17, count 0 2006.285.07:29:11.73#ibcon#read 4, iclass 17, count 0 2006.285.07:29:11.73#ibcon#about to read 5, iclass 17, count 0 2006.285.07:29:11.73#ibcon#read 5, iclass 17, count 0 2006.285.07:29:11.73#ibcon#about to read 6, iclass 17, count 0 2006.285.07:29:11.73#ibcon#read 6, iclass 17, count 0 2006.285.07:29:11.73#ibcon#end of sib2, iclass 17, count 0 2006.285.07:29:11.73#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:29:11.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:29:11.73#ibcon#[25=USB\r\n] 2006.285.07:29:11.73#ibcon#*before write, iclass 17, count 0 2006.285.07:29:11.73#ibcon#enter sib2, iclass 17, count 0 2006.285.07:29:11.73#ibcon#flushed, iclass 17, count 0 2006.285.07:29:11.73#ibcon#about to write, iclass 17, count 0 2006.285.07:29:11.73#ibcon#wrote, iclass 17, count 0 2006.285.07:29:11.73#ibcon#about to read 3, iclass 17, count 0 2006.285.07:29:11.76#ibcon#read 3, iclass 17, count 0 2006.285.07:29:11.76#ibcon#about to read 4, iclass 17, count 0 2006.285.07:29:11.76#ibcon#read 4, iclass 17, count 0 2006.285.07:29:11.76#ibcon#about to read 5, iclass 17, count 0 2006.285.07:29:11.76#ibcon#read 5, iclass 17, count 0 2006.285.07:29:11.76#ibcon#about to read 6, iclass 17, count 0 2006.285.07:29:11.76#ibcon#read 6, iclass 17, count 0 2006.285.07:29:11.76#ibcon#end of sib2, iclass 17, count 0 2006.285.07:29:11.76#ibcon#*after write, iclass 17, count 0 2006.285.07:29:11.76#ibcon#*before return 0, iclass 17, count 0 2006.285.07:29:11.76#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:29:11.76#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:29:11.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:29:11.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:29:11.76$vck44/valo=3,564.99 2006.285.07:29:11.76#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.07:29:11.76#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.07:29:11.76#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:11.76#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:29:11.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:29:11.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:29:11.76#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:29:11.76#ibcon#first serial, iclass 19, count 0 2006.285.07:29:11.76#ibcon#enter sib2, iclass 19, count 0 2006.285.07:29:11.76#ibcon#flushed, iclass 19, count 0 2006.285.07:29:11.76#ibcon#about to write, iclass 19, count 0 2006.285.07:29:11.76#ibcon#wrote, iclass 19, count 0 2006.285.07:29:11.76#ibcon#about to read 3, iclass 19, count 0 2006.285.07:29:11.78#ibcon#read 3, iclass 19, count 0 2006.285.07:29:11.78#ibcon#about to read 4, iclass 19, count 0 2006.285.07:29:11.78#ibcon#read 4, iclass 19, count 0 2006.285.07:29:11.78#ibcon#about to read 5, iclass 19, count 0 2006.285.07:29:11.78#ibcon#read 5, iclass 19, count 0 2006.285.07:29:11.78#ibcon#about to read 6, iclass 19, count 0 2006.285.07:29:11.78#ibcon#read 6, iclass 19, count 0 2006.285.07:29:11.78#ibcon#end of sib2, iclass 19, count 0 2006.285.07:29:11.78#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:29:11.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:29:11.78#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:29:11.78#ibcon#*before write, iclass 19, count 0 2006.285.07:29:11.78#ibcon#enter sib2, iclass 19, count 0 2006.285.07:29:11.78#ibcon#flushed, iclass 19, count 0 2006.285.07:29:11.78#ibcon#about to write, iclass 19, count 0 2006.285.07:29:11.78#ibcon#wrote, iclass 19, count 0 2006.285.07:29:11.78#ibcon#about to read 3, iclass 19, count 0 2006.285.07:29:11.82#ibcon#read 3, iclass 19, count 0 2006.285.07:29:11.82#ibcon#about to read 4, iclass 19, count 0 2006.285.07:29:11.82#ibcon#read 4, iclass 19, count 0 2006.285.07:29:11.82#ibcon#about to read 5, iclass 19, count 0 2006.285.07:29:11.82#ibcon#read 5, iclass 19, count 0 2006.285.07:29:11.82#ibcon#about to read 6, iclass 19, count 0 2006.285.07:29:11.82#ibcon#read 6, iclass 19, count 0 2006.285.07:29:11.82#ibcon#end of sib2, iclass 19, count 0 2006.285.07:29:11.82#ibcon#*after write, iclass 19, count 0 2006.285.07:29:11.82#ibcon#*before return 0, iclass 19, count 0 2006.285.07:29:11.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:29:11.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:29:11.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:29:11.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:29:11.82$vck44/va=3,7 2006.285.07:29:11.82#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.07:29:11.82#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.07:29:11.82#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:11.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:29:11.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:29:11.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:29:11.88#ibcon#enter wrdev, iclass 21, count 2 2006.285.07:29:11.88#ibcon#first serial, iclass 21, count 2 2006.285.07:29:11.88#ibcon#enter sib2, iclass 21, count 2 2006.285.07:29:11.88#ibcon#flushed, iclass 21, count 2 2006.285.07:29:11.88#ibcon#about to write, iclass 21, count 2 2006.285.07:29:11.88#ibcon#wrote, iclass 21, count 2 2006.285.07:29:11.88#ibcon#about to read 3, iclass 21, count 2 2006.285.07:29:11.90#ibcon#read 3, iclass 21, count 2 2006.285.07:29:11.90#ibcon#about to read 4, iclass 21, count 2 2006.285.07:29:11.90#ibcon#read 4, iclass 21, count 2 2006.285.07:29:11.90#ibcon#about to read 5, iclass 21, count 2 2006.285.07:29:11.90#ibcon#read 5, iclass 21, count 2 2006.285.07:29:11.90#ibcon#about to read 6, iclass 21, count 2 2006.285.07:29:11.90#ibcon#read 6, iclass 21, count 2 2006.285.07:29:11.90#ibcon#end of sib2, iclass 21, count 2 2006.285.07:29:11.90#ibcon#*mode == 0, iclass 21, count 2 2006.285.07:29:11.90#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.07:29:11.90#ibcon#[25=AT03-07\r\n] 2006.285.07:29:11.90#ibcon#*before write, iclass 21, count 2 2006.285.07:29:11.90#ibcon#enter sib2, iclass 21, count 2 2006.285.07:29:11.90#ibcon#flushed, iclass 21, count 2 2006.285.07:29:11.90#ibcon#about to write, iclass 21, count 2 2006.285.07:29:11.90#ibcon#wrote, iclass 21, count 2 2006.285.07:29:11.90#ibcon#about to read 3, iclass 21, count 2 2006.285.07:29:11.93#ibcon#read 3, iclass 21, count 2 2006.285.07:29:11.93#ibcon#about to read 4, iclass 21, count 2 2006.285.07:29:11.93#ibcon#read 4, iclass 21, count 2 2006.285.07:29:11.93#ibcon#about to read 5, iclass 21, count 2 2006.285.07:29:11.93#ibcon#read 5, iclass 21, count 2 2006.285.07:29:11.93#ibcon#about to read 6, iclass 21, count 2 2006.285.07:29:11.93#ibcon#read 6, iclass 21, count 2 2006.285.07:29:11.93#ibcon#end of sib2, iclass 21, count 2 2006.285.07:29:11.93#ibcon#*after write, iclass 21, count 2 2006.285.07:29:11.93#ibcon#*before return 0, iclass 21, count 2 2006.285.07:29:11.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:29:11.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:29:11.93#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.07:29:11.93#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:11.93#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:29:12.05#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:29:12.05#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:29:12.05#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:29:12.05#ibcon#first serial, iclass 21, count 0 2006.285.07:29:12.05#ibcon#enter sib2, iclass 21, count 0 2006.285.07:29:12.05#ibcon#flushed, iclass 21, count 0 2006.285.07:29:12.05#ibcon#about to write, iclass 21, count 0 2006.285.07:29:12.05#ibcon#wrote, iclass 21, count 0 2006.285.07:29:12.05#ibcon#about to read 3, iclass 21, count 0 2006.285.07:29:12.07#ibcon#read 3, iclass 21, count 0 2006.285.07:29:12.07#ibcon#about to read 4, iclass 21, count 0 2006.285.07:29:12.07#ibcon#read 4, iclass 21, count 0 2006.285.07:29:12.07#ibcon#about to read 5, iclass 21, count 0 2006.285.07:29:12.07#ibcon#read 5, iclass 21, count 0 2006.285.07:29:12.07#ibcon#about to read 6, iclass 21, count 0 2006.285.07:29:12.07#ibcon#read 6, iclass 21, count 0 2006.285.07:29:12.07#ibcon#end of sib2, iclass 21, count 0 2006.285.07:29:12.07#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:29:12.07#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:29:12.07#ibcon#[25=USB\r\n] 2006.285.07:29:12.07#ibcon#*before write, iclass 21, count 0 2006.285.07:29:12.07#ibcon#enter sib2, iclass 21, count 0 2006.285.07:29:12.07#ibcon#flushed, iclass 21, count 0 2006.285.07:29:12.07#ibcon#about to write, iclass 21, count 0 2006.285.07:29:12.07#ibcon#wrote, iclass 21, count 0 2006.285.07:29:12.07#ibcon#about to read 3, iclass 21, count 0 2006.285.07:29:12.10#ibcon#read 3, iclass 21, count 0 2006.285.07:29:12.10#ibcon#about to read 4, iclass 21, count 0 2006.285.07:29:12.10#ibcon#read 4, iclass 21, count 0 2006.285.07:29:12.10#ibcon#about to read 5, iclass 21, count 0 2006.285.07:29:12.10#ibcon#read 5, iclass 21, count 0 2006.285.07:29:12.10#ibcon#about to read 6, iclass 21, count 0 2006.285.07:29:12.10#ibcon#read 6, iclass 21, count 0 2006.285.07:29:12.10#ibcon#end of sib2, iclass 21, count 0 2006.285.07:29:12.10#ibcon#*after write, iclass 21, count 0 2006.285.07:29:12.10#ibcon#*before return 0, iclass 21, count 0 2006.285.07:29:12.10#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:29:12.10#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:29:12.10#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:29:12.10#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:29:12.10$vck44/valo=4,624.99 2006.285.07:29:12.10#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.07:29:12.10#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.07:29:12.10#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:12.10#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:29:12.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:29:12.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:29:12.10#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:29:12.10#ibcon#first serial, iclass 23, count 0 2006.285.07:29:12.10#ibcon#enter sib2, iclass 23, count 0 2006.285.07:29:12.10#ibcon#flushed, iclass 23, count 0 2006.285.07:29:12.10#ibcon#about to write, iclass 23, count 0 2006.285.07:29:12.10#ibcon#wrote, iclass 23, count 0 2006.285.07:29:12.10#ibcon#about to read 3, iclass 23, count 0 2006.285.07:29:12.12#ibcon#read 3, iclass 23, count 0 2006.285.07:29:12.12#ibcon#about to read 4, iclass 23, count 0 2006.285.07:29:12.12#ibcon#read 4, iclass 23, count 0 2006.285.07:29:12.12#ibcon#about to read 5, iclass 23, count 0 2006.285.07:29:12.12#ibcon#read 5, iclass 23, count 0 2006.285.07:29:12.12#ibcon#about to read 6, iclass 23, count 0 2006.285.07:29:12.12#ibcon#read 6, iclass 23, count 0 2006.285.07:29:12.12#ibcon#end of sib2, iclass 23, count 0 2006.285.07:29:12.12#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:29:12.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:29:12.12#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:29:12.12#ibcon#*before write, iclass 23, count 0 2006.285.07:29:12.12#ibcon#enter sib2, iclass 23, count 0 2006.285.07:29:12.12#ibcon#flushed, iclass 23, count 0 2006.285.07:29:12.12#ibcon#about to write, iclass 23, count 0 2006.285.07:29:12.12#ibcon#wrote, iclass 23, count 0 2006.285.07:29:12.12#ibcon#about to read 3, iclass 23, count 0 2006.285.07:29:12.16#ibcon#read 3, iclass 23, count 0 2006.285.07:29:12.16#ibcon#about to read 4, iclass 23, count 0 2006.285.07:29:12.16#ibcon#read 4, iclass 23, count 0 2006.285.07:29:12.16#ibcon#about to read 5, iclass 23, count 0 2006.285.07:29:12.16#ibcon#read 5, iclass 23, count 0 2006.285.07:29:12.16#ibcon#about to read 6, iclass 23, count 0 2006.285.07:29:12.16#ibcon#read 6, iclass 23, count 0 2006.285.07:29:12.16#ibcon#end of sib2, iclass 23, count 0 2006.285.07:29:12.16#ibcon#*after write, iclass 23, count 0 2006.285.07:29:12.16#ibcon#*before return 0, iclass 23, count 0 2006.285.07:29:12.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:29:12.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:29:12.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:29:12.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:29:12.16$vck44/va=4,6 2006.285.07:29:12.16#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.07:29:12.16#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.07:29:12.16#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:12.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:29:12.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:29:12.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:29:12.22#ibcon#enter wrdev, iclass 25, count 2 2006.285.07:29:12.22#ibcon#first serial, iclass 25, count 2 2006.285.07:29:12.22#ibcon#enter sib2, iclass 25, count 2 2006.285.07:29:12.22#ibcon#flushed, iclass 25, count 2 2006.285.07:29:12.22#ibcon#about to write, iclass 25, count 2 2006.285.07:29:12.22#ibcon#wrote, iclass 25, count 2 2006.285.07:29:12.22#ibcon#about to read 3, iclass 25, count 2 2006.285.07:29:12.24#ibcon#read 3, iclass 25, count 2 2006.285.07:29:12.24#ibcon#about to read 4, iclass 25, count 2 2006.285.07:29:12.24#ibcon#read 4, iclass 25, count 2 2006.285.07:29:12.24#ibcon#about to read 5, iclass 25, count 2 2006.285.07:29:12.24#ibcon#read 5, iclass 25, count 2 2006.285.07:29:12.24#ibcon#about to read 6, iclass 25, count 2 2006.285.07:29:12.24#ibcon#read 6, iclass 25, count 2 2006.285.07:29:12.24#ibcon#end of sib2, iclass 25, count 2 2006.285.07:29:12.24#ibcon#*mode == 0, iclass 25, count 2 2006.285.07:29:12.24#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.07:29:12.24#ibcon#[25=AT04-06\r\n] 2006.285.07:29:12.24#ibcon#*before write, iclass 25, count 2 2006.285.07:29:12.24#ibcon#enter sib2, iclass 25, count 2 2006.285.07:29:12.24#ibcon#flushed, iclass 25, count 2 2006.285.07:29:12.24#ibcon#about to write, iclass 25, count 2 2006.285.07:29:12.24#ibcon#wrote, iclass 25, count 2 2006.285.07:29:12.24#ibcon#about to read 3, iclass 25, count 2 2006.285.07:29:12.27#ibcon#read 3, iclass 25, count 2 2006.285.07:29:12.27#ibcon#about to read 4, iclass 25, count 2 2006.285.07:29:12.27#ibcon#read 4, iclass 25, count 2 2006.285.07:29:12.27#ibcon#about to read 5, iclass 25, count 2 2006.285.07:29:12.27#ibcon#read 5, iclass 25, count 2 2006.285.07:29:12.27#ibcon#about to read 6, iclass 25, count 2 2006.285.07:29:12.27#ibcon#read 6, iclass 25, count 2 2006.285.07:29:12.27#ibcon#end of sib2, iclass 25, count 2 2006.285.07:29:12.27#ibcon#*after write, iclass 25, count 2 2006.285.07:29:12.27#ibcon#*before return 0, iclass 25, count 2 2006.285.07:29:12.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:29:12.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:29:12.27#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.07:29:12.27#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:12.27#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:29:12.39#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:29:12.39#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:29:12.39#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:29:12.39#ibcon#first serial, iclass 25, count 0 2006.285.07:29:12.39#ibcon#enter sib2, iclass 25, count 0 2006.285.07:29:12.39#ibcon#flushed, iclass 25, count 0 2006.285.07:29:12.39#ibcon#about to write, iclass 25, count 0 2006.285.07:29:12.39#ibcon#wrote, iclass 25, count 0 2006.285.07:29:12.39#ibcon#about to read 3, iclass 25, count 0 2006.285.07:29:12.41#ibcon#read 3, iclass 25, count 0 2006.285.07:29:12.41#ibcon#about to read 4, iclass 25, count 0 2006.285.07:29:12.41#ibcon#read 4, iclass 25, count 0 2006.285.07:29:12.41#ibcon#about to read 5, iclass 25, count 0 2006.285.07:29:12.41#ibcon#read 5, iclass 25, count 0 2006.285.07:29:12.41#ibcon#about to read 6, iclass 25, count 0 2006.285.07:29:12.41#ibcon#read 6, iclass 25, count 0 2006.285.07:29:12.41#ibcon#end of sib2, iclass 25, count 0 2006.285.07:29:12.41#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:29:12.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:29:12.41#ibcon#[25=USB\r\n] 2006.285.07:29:12.41#ibcon#*before write, iclass 25, count 0 2006.285.07:29:12.41#ibcon#enter sib2, iclass 25, count 0 2006.285.07:29:12.41#ibcon#flushed, iclass 25, count 0 2006.285.07:29:12.41#ibcon#about to write, iclass 25, count 0 2006.285.07:29:12.41#ibcon#wrote, iclass 25, count 0 2006.285.07:29:12.41#ibcon#about to read 3, iclass 25, count 0 2006.285.07:29:12.44#ibcon#read 3, iclass 25, count 0 2006.285.07:29:12.44#ibcon#about to read 4, iclass 25, count 0 2006.285.07:29:12.44#ibcon#read 4, iclass 25, count 0 2006.285.07:29:12.44#ibcon#about to read 5, iclass 25, count 0 2006.285.07:29:12.44#ibcon#read 5, iclass 25, count 0 2006.285.07:29:12.44#ibcon#about to read 6, iclass 25, count 0 2006.285.07:29:12.44#ibcon#read 6, iclass 25, count 0 2006.285.07:29:12.44#ibcon#end of sib2, iclass 25, count 0 2006.285.07:29:12.44#ibcon#*after write, iclass 25, count 0 2006.285.07:29:12.44#ibcon#*before return 0, iclass 25, count 0 2006.285.07:29:12.44#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:29:12.44#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:29:12.44#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:29:12.44#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:29:12.44$vck44/valo=5,734.99 2006.285.07:29:12.44#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.07:29:12.44#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.07:29:12.44#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:12.44#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:29:12.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:29:12.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:29:12.44#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:29:12.44#ibcon#first serial, iclass 27, count 0 2006.285.07:29:12.44#ibcon#enter sib2, iclass 27, count 0 2006.285.07:29:12.44#ibcon#flushed, iclass 27, count 0 2006.285.07:29:12.44#ibcon#about to write, iclass 27, count 0 2006.285.07:29:12.44#ibcon#wrote, iclass 27, count 0 2006.285.07:29:12.44#ibcon#about to read 3, iclass 27, count 0 2006.285.07:29:12.46#ibcon#read 3, iclass 27, count 0 2006.285.07:29:12.46#ibcon#about to read 4, iclass 27, count 0 2006.285.07:29:12.46#ibcon#read 4, iclass 27, count 0 2006.285.07:29:12.46#ibcon#about to read 5, iclass 27, count 0 2006.285.07:29:12.46#ibcon#read 5, iclass 27, count 0 2006.285.07:29:12.46#ibcon#about to read 6, iclass 27, count 0 2006.285.07:29:12.46#ibcon#read 6, iclass 27, count 0 2006.285.07:29:12.46#ibcon#end of sib2, iclass 27, count 0 2006.285.07:29:12.46#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:29:12.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:29:12.46#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:29:12.46#ibcon#*before write, iclass 27, count 0 2006.285.07:29:12.46#ibcon#enter sib2, iclass 27, count 0 2006.285.07:29:12.46#ibcon#flushed, iclass 27, count 0 2006.285.07:29:12.46#ibcon#about to write, iclass 27, count 0 2006.285.07:29:12.46#ibcon#wrote, iclass 27, count 0 2006.285.07:29:12.46#ibcon#about to read 3, iclass 27, count 0 2006.285.07:29:12.50#ibcon#read 3, iclass 27, count 0 2006.285.07:29:12.50#ibcon#about to read 4, iclass 27, count 0 2006.285.07:29:12.50#ibcon#read 4, iclass 27, count 0 2006.285.07:29:12.50#ibcon#about to read 5, iclass 27, count 0 2006.285.07:29:12.50#ibcon#read 5, iclass 27, count 0 2006.285.07:29:12.50#ibcon#about to read 6, iclass 27, count 0 2006.285.07:29:12.50#ibcon#read 6, iclass 27, count 0 2006.285.07:29:12.50#ibcon#end of sib2, iclass 27, count 0 2006.285.07:29:12.50#ibcon#*after write, iclass 27, count 0 2006.285.07:29:12.50#ibcon#*before return 0, iclass 27, count 0 2006.285.07:29:12.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:29:12.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:29:12.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:29:12.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:29:12.50$vck44/va=5,3 2006.285.07:29:12.50#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.07:29:12.50#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.07:29:12.50#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:12.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:29:12.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:29:12.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:29:12.56#ibcon#enter wrdev, iclass 29, count 2 2006.285.07:29:12.56#ibcon#first serial, iclass 29, count 2 2006.285.07:29:12.56#ibcon#enter sib2, iclass 29, count 2 2006.285.07:29:12.56#ibcon#flushed, iclass 29, count 2 2006.285.07:29:12.56#ibcon#about to write, iclass 29, count 2 2006.285.07:29:12.56#ibcon#wrote, iclass 29, count 2 2006.285.07:29:12.56#ibcon#about to read 3, iclass 29, count 2 2006.285.07:29:12.58#ibcon#read 3, iclass 29, count 2 2006.285.07:29:12.58#ibcon#about to read 4, iclass 29, count 2 2006.285.07:29:12.58#ibcon#read 4, iclass 29, count 2 2006.285.07:29:12.58#ibcon#about to read 5, iclass 29, count 2 2006.285.07:29:12.58#ibcon#read 5, iclass 29, count 2 2006.285.07:29:12.58#ibcon#about to read 6, iclass 29, count 2 2006.285.07:29:12.58#ibcon#read 6, iclass 29, count 2 2006.285.07:29:12.58#ibcon#end of sib2, iclass 29, count 2 2006.285.07:29:12.58#ibcon#*mode == 0, iclass 29, count 2 2006.285.07:29:12.58#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.07:29:12.58#ibcon#[25=AT05-03\r\n] 2006.285.07:29:12.58#ibcon#*before write, iclass 29, count 2 2006.285.07:29:12.58#ibcon#enter sib2, iclass 29, count 2 2006.285.07:29:12.58#ibcon#flushed, iclass 29, count 2 2006.285.07:29:12.58#ibcon#about to write, iclass 29, count 2 2006.285.07:29:12.58#ibcon#wrote, iclass 29, count 2 2006.285.07:29:12.58#ibcon#about to read 3, iclass 29, count 2 2006.285.07:29:12.61#ibcon#read 3, iclass 29, count 2 2006.285.07:29:12.61#ibcon#about to read 4, iclass 29, count 2 2006.285.07:29:12.61#ibcon#read 4, iclass 29, count 2 2006.285.07:29:12.61#ibcon#about to read 5, iclass 29, count 2 2006.285.07:29:12.61#ibcon#read 5, iclass 29, count 2 2006.285.07:29:12.61#ibcon#about to read 6, iclass 29, count 2 2006.285.07:29:12.61#ibcon#read 6, iclass 29, count 2 2006.285.07:29:12.61#ibcon#end of sib2, iclass 29, count 2 2006.285.07:29:12.61#ibcon#*after write, iclass 29, count 2 2006.285.07:29:12.61#ibcon#*before return 0, iclass 29, count 2 2006.285.07:29:12.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:29:12.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:29:12.61#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.07:29:12.61#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:12.61#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:29:12.73#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:29:12.73#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:29:12.73#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:29:12.73#ibcon#first serial, iclass 29, count 0 2006.285.07:29:12.73#ibcon#enter sib2, iclass 29, count 0 2006.285.07:29:12.73#ibcon#flushed, iclass 29, count 0 2006.285.07:29:12.73#ibcon#about to write, iclass 29, count 0 2006.285.07:29:12.73#ibcon#wrote, iclass 29, count 0 2006.285.07:29:12.73#ibcon#about to read 3, iclass 29, count 0 2006.285.07:29:12.75#ibcon#read 3, iclass 29, count 0 2006.285.07:29:12.75#ibcon#about to read 4, iclass 29, count 0 2006.285.07:29:12.75#ibcon#read 4, iclass 29, count 0 2006.285.07:29:12.75#ibcon#about to read 5, iclass 29, count 0 2006.285.07:29:12.75#ibcon#read 5, iclass 29, count 0 2006.285.07:29:12.75#ibcon#about to read 6, iclass 29, count 0 2006.285.07:29:12.75#ibcon#read 6, iclass 29, count 0 2006.285.07:29:12.75#ibcon#end of sib2, iclass 29, count 0 2006.285.07:29:12.75#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:29:12.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:29:12.75#ibcon#[25=USB\r\n] 2006.285.07:29:12.75#ibcon#*before write, iclass 29, count 0 2006.285.07:29:12.75#ibcon#enter sib2, iclass 29, count 0 2006.285.07:29:12.75#ibcon#flushed, iclass 29, count 0 2006.285.07:29:12.75#ibcon#about to write, iclass 29, count 0 2006.285.07:29:12.75#ibcon#wrote, iclass 29, count 0 2006.285.07:29:12.75#ibcon#about to read 3, iclass 29, count 0 2006.285.07:29:12.78#ibcon#read 3, iclass 29, count 0 2006.285.07:29:12.78#ibcon#about to read 4, iclass 29, count 0 2006.285.07:29:12.78#ibcon#read 4, iclass 29, count 0 2006.285.07:29:12.78#ibcon#about to read 5, iclass 29, count 0 2006.285.07:29:12.78#ibcon#read 5, iclass 29, count 0 2006.285.07:29:12.78#ibcon#about to read 6, iclass 29, count 0 2006.285.07:29:12.78#ibcon#read 6, iclass 29, count 0 2006.285.07:29:12.78#ibcon#end of sib2, iclass 29, count 0 2006.285.07:29:12.78#ibcon#*after write, iclass 29, count 0 2006.285.07:29:12.78#ibcon#*before return 0, iclass 29, count 0 2006.285.07:29:12.78#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:29:12.78#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:29:12.78#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:29:12.78#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:29:12.78$vck44/valo=6,814.99 2006.285.07:29:12.78#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.07:29:12.78#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.07:29:12.78#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:12.78#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:29:12.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:29:12.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:29:12.78#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:29:12.78#ibcon#first serial, iclass 31, count 0 2006.285.07:29:12.78#ibcon#enter sib2, iclass 31, count 0 2006.285.07:29:12.78#ibcon#flushed, iclass 31, count 0 2006.285.07:29:12.78#ibcon#about to write, iclass 31, count 0 2006.285.07:29:12.78#ibcon#wrote, iclass 31, count 0 2006.285.07:29:12.78#ibcon#about to read 3, iclass 31, count 0 2006.285.07:29:12.80#ibcon#read 3, iclass 31, count 0 2006.285.07:29:12.80#ibcon#about to read 4, iclass 31, count 0 2006.285.07:29:12.80#ibcon#read 4, iclass 31, count 0 2006.285.07:29:12.80#ibcon#about to read 5, iclass 31, count 0 2006.285.07:29:12.80#ibcon#read 5, iclass 31, count 0 2006.285.07:29:12.80#ibcon#about to read 6, iclass 31, count 0 2006.285.07:29:12.80#ibcon#read 6, iclass 31, count 0 2006.285.07:29:12.80#ibcon#end of sib2, iclass 31, count 0 2006.285.07:29:12.80#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:29:12.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:29:12.80#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:29:12.80#ibcon#*before write, iclass 31, count 0 2006.285.07:29:12.80#ibcon#enter sib2, iclass 31, count 0 2006.285.07:29:12.80#ibcon#flushed, iclass 31, count 0 2006.285.07:29:12.80#ibcon#about to write, iclass 31, count 0 2006.285.07:29:12.80#ibcon#wrote, iclass 31, count 0 2006.285.07:29:12.80#ibcon#about to read 3, iclass 31, count 0 2006.285.07:29:12.84#ibcon#read 3, iclass 31, count 0 2006.285.07:29:12.84#ibcon#about to read 4, iclass 31, count 0 2006.285.07:29:12.84#ibcon#read 4, iclass 31, count 0 2006.285.07:29:12.84#ibcon#about to read 5, iclass 31, count 0 2006.285.07:29:12.84#ibcon#read 5, iclass 31, count 0 2006.285.07:29:12.84#ibcon#about to read 6, iclass 31, count 0 2006.285.07:29:12.84#ibcon#read 6, iclass 31, count 0 2006.285.07:29:12.84#ibcon#end of sib2, iclass 31, count 0 2006.285.07:29:12.84#ibcon#*after write, iclass 31, count 0 2006.285.07:29:12.84#ibcon#*before return 0, iclass 31, count 0 2006.285.07:29:12.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:29:12.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:29:12.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:29:12.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:29:12.84$vck44/va=6,4 2006.285.07:29:12.84#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.07:29:12.84#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.07:29:12.84#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:12.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:29:12.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:29:12.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:29:12.90#ibcon#enter wrdev, iclass 33, count 2 2006.285.07:29:12.90#ibcon#first serial, iclass 33, count 2 2006.285.07:29:12.90#ibcon#enter sib2, iclass 33, count 2 2006.285.07:29:12.90#ibcon#flushed, iclass 33, count 2 2006.285.07:29:12.90#ibcon#about to write, iclass 33, count 2 2006.285.07:29:12.90#ibcon#wrote, iclass 33, count 2 2006.285.07:29:12.90#ibcon#about to read 3, iclass 33, count 2 2006.285.07:29:12.92#ibcon#read 3, iclass 33, count 2 2006.285.07:29:12.92#ibcon#about to read 4, iclass 33, count 2 2006.285.07:29:12.92#ibcon#read 4, iclass 33, count 2 2006.285.07:29:12.92#ibcon#about to read 5, iclass 33, count 2 2006.285.07:29:12.92#ibcon#read 5, iclass 33, count 2 2006.285.07:29:12.92#ibcon#about to read 6, iclass 33, count 2 2006.285.07:29:12.92#ibcon#read 6, iclass 33, count 2 2006.285.07:29:12.92#ibcon#end of sib2, iclass 33, count 2 2006.285.07:29:12.92#ibcon#*mode == 0, iclass 33, count 2 2006.285.07:29:12.92#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.07:29:12.92#ibcon#[25=AT06-04\r\n] 2006.285.07:29:12.92#ibcon#*before write, iclass 33, count 2 2006.285.07:29:12.92#ibcon#enter sib2, iclass 33, count 2 2006.285.07:29:12.92#ibcon#flushed, iclass 33, count 2 2006.285.07:29:12.92#ibcon#about to write, iclass 33, count 2 2006.285.07:29:12.92#ibcon#wrote, iclass 33, count 2 2006.285.07:29:12.92#ibcon#about to read 3, iclass 33, count 2 2006.285.07:29:12.95#ibcon#read 3, iclass 33, count 2 2006.285.07:29:12.95#ibcon#about to read 4, iclass 33, count 2 2006.285.07:29:12.95#ibcon#read 4, iclass 33, count 2 2006.285.07:29:12.95#ibcon#about to read 5, iclass 33, count 2 2006.285.07:29:12.95#ibcon#read 5, iclass 33, count 2 2006.285.07:29:12.95#ibcon#about to read 6, iclass 33, count 2 2006.285.07:29:12.95#ibcon#read 6, iclass 33, count 2 2006.285.07:29:12.95#ibcon#end of sib2, iclass 33, count 2 2006.285.07:29:12.95#ibcon#*after write, iclass 33, count 2 2006.285.07:29:12.95#ibcon#*before return 0, iclass 33, count 2 2006.285.07:29:12.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:29:12.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:29:12.95#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.07:29:12.95#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:12.95#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:29:13.07#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:29:13.07#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:29:13.07#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:29:13.07#ibcon#first serial, iclass 33, count 0 2006.285.07:29:13.07#ibcon#enter sib2, iclass 33, count 0 2006.285.07:29:13.07#ibcon#flushed, iclass 33, count 0 2006.285.07:29:13.07#ibcon#about to write, iclass 33, count 0 2006.285.07:29:13.07#ibcon#wrote, iclass 33, count 0 2006.285.07:29:13.07#ibcon#about to read 3, iclass 33, count 0 2006.285.07:29:13.09#ibcon#read 3, iclass 33, count 0 2006.285.07:29:13.09#ibcon#about to read 4, iclass 33, count 0 2006.285.07:29:13.09#ibcon#read 4, iclass 33, count 0 2006.285.07:29:13.09#ibcon#about to read 5, iclass 33, count 0 2006.285.07:29:13.09#ibcon#read 5, iclass 33, count 0 2006.285.07:29:13.09#ibcon#about to read 6, iclass 33, count 0 2006.285.07:29:13.09#ibcon#read 6, iclass 33, count 0 2006.285.07:29:13.09#ibcon#end of sib2, iclass 33, count 0 2006.285.07:29:13.09#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:29:13.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:29:13.09#ibcon#[25=USB\r\n] 2006.285.07:29:13.09#ibcon#*before write, iclass 33, count 0 2006.285.07:29:13.09#ibcon#enter sib2, iclass 33, count 0 2006.285.07:29:13.09#ibcon#flushed, iclass 33, count 0 2006.285.07:29:13.09#ibcon#about to write, iclass 33, count 0 2006.285.07:29:13.09#ibcon#wrote, iclass 33, count 0 2006.285.07:29:13.09#ibcon#about to read 3, iclass 33, count 0 2006.285.07:29:13.12#ibcon#read 3, iclass 33, count 0 2006.285.07:29:13.12#ibcon#about to read 4, iclass 33, count 0 2006.285.07:29:13.12#ibcon#read 4, iclass 33, count 0 2006.285.07:29:13.12#ibcon#about to read 5, iclass 33, count 0 2006.285.07:29:13.12#ibcon#read 5, iclass 33, count 0 2006.285.07:29:13.12#ibcon#about to read 6, iclass 33, count 0 2006.285.07:29:13.12#ibcon#read 6, iclass 33, count 0 2006.285.07:29:13.12#ibcon#end of sib2, iclass 33, count 0 2006.285.07:29:13.12#ibcon#*after write, iclass 33, count 0 2006.285.07:29:13.12#ibcon#*before return 0, iclass 33, count 0 2006.285.07:29:13.12#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:29:13.12#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:29:13.12#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:29:13.12#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:29:13.12$vck44/valo=7,864.99 2006.285.07:29:13.12#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.07:29:13.12#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.07:29:13.12#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:13.12#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:29:13.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:29:13.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:29:13.12#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:29:13.12#ibcon#first serial, iclass 35, count 0 2006.285.07:29:13.12#ibcon#enter sib2, iclass 35, count 0 2006.285.07:29:13.12#ibcon#flushed, iclass 35, count 0 2006.285.07:29:13.12#ibcon#about to write, iclass 35, count 0 2006.285.07:29:13.12#ibcon#wrote, iclass 35, count 0 2006.285.07:29:13.12#ibcon#about to read 3, iclass 35, count 0 2006.285.07:29:13.14#ibcon#read 3, iclass 35, count 0 2006.285.07:29:13.14#ibcon#about to read 4, iclass 35, count 0 2006.285.07:29:13.14#ibcon#read 4, iclass 35, count 0 2006.285.07:29:13.14#ibcon#about to read 5, iclass 35, count 0 2006.285.07:29:13.14#ibcon#read 5, iclass 35, count 0 2006.285.07:29:13.14#ibcon#about to read 6, iclass 35, count 0 2006.285.07:29:13.14#ibcon#read 6, iclass 35, count 0 2006.285.07:29:13.14#ibcon#end of sib2, iclass 35, count 0 2006.285.07:29:13.14#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:29:13.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:29:13.14#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:29:13.14#ibcon#*before write, iclass 35, count 0 2006.285.07:29:13.14#ibcon#enter sib2, iclass 35, count 0 2006.285.07:29:13.14#ibcon#flushed, iclass 35, count 0 2006.285.07:29:13.14#ibcon#about to write, iclass 35, count 0 2006.285.07:29:13.14#ibcon#wrote, iclass 35, count 0 2006.285.07:29:13.14#ibcon#about to read 3, iclass 35, count 0 2006.285.07:29:13.18#ibcon#read 3, iclass 35, count 0 2006.285.07:29:13.18#ibcon#about to read 4, iclass 35, count 0 2006.285.07:29:13.18#ibcon#read 4, iclass 35, count 0 2006.285.07:29:13.18#ibcon#about to read 5, iclass 35, count 0 2006.285.07:29:13.18#ibcon#read 5, iclass 35, count 0 2006.285.07:29:13.18#ibcon#about to read 6, iclass 35, count 0 2006.285.07:29:13.18#ibcon#read 6, iclass 35, count 0 2006.285.07:29:13.18#ibcon#end of sib2, iclass 35, count 0 2006.285.07:29:13.18#ibcon#*after write, iclass 35, count 0 2006.285.07:29:13.18#ibcon#*before return 0, iclass 35, count 0 2006.285.07:29:13.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:29:13.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:29:13.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:29:13.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:29:13.18$vck44/va=7,4 2006.285.07:29:13.18#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.07:29:13.18#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.07:29:13.18#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:13.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:29:13.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:29:13.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:29:13.24#ibcon#enter wrdev, iclass 37, count 2 2006.285.07:29:13.24#ibcon#first serial, iclass 37, count 2 2006.285.07:29:13.24#ibcon#enter sib2, iclass 37, count 2 2006.285.07:29:13.24#ibcon#flushed, iclass 37, count 2 2006.285.07:29:13.24#ibcon#about to write, iclass 37, count 2 2006.285.07:29:13.24#ibcon#wrote, iclass 37, count 2 2006.285.07:29:13.24#ibcon#about to read 3, iclass 37, count 2 2006.285.07:29:13.26#ibcon#read 3, iclass 37, count 2 2006.285.07:29:13.26#ibcon#about to read 4, iclass 37, count 2 2006.285.07:29:13.26#ibcon#read 4, iclass 37, count 2 2006.285.07:29:13.26#ibcon#about to read 5, iclass 37, count 2 2006.285.07:29:13.26#ibcon#read 5, iclass 37, count 2 2006.285.07:29:13.26#ibcon#about to read 6, iclass 37, count 2 2006.285.07:29:13.26#ibcon#read 6, iclass 37, count 2 2006.285.07:29:13.26#ibcon#end of sib2, iclass 37, count 2 2006.285.07:29:13.26#ibcon#*mode == 0, iclass 37, count 2 2006.285.07:29:13.26#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.07:29:13.26#ibcon#[25=AT07-04\r\n] 2006.285.07:29:13.26#ibcon#*before write, iclass 37, count 2 2006.285.07:29:13.26#ibcon#enter sib2, iclass 37, count 2 2006.285.07:29:13.26#ibcon#flushed, iclass 37, count 2 2006.285.07:29:13.26#ibcon#about to write, iclass 37, count 2 2006.285.07:29:13.26#ibcon#wrote, iclass 37, count 2 2006.285.07:29:13.26#ibcon#about to read 3, iclass 37, count 2 2006.285.07:29:13.29#ibcon#read 3, iclass 37, count 2 2006.285.07:29:13.29#ibcon#about to read 4, iclass 37, count 2 2006.285.07:29:13.29#ibcon#read 4, iclass 37, count 2 2006.285.07:29:13.29#ibcon#about to read 5, iclass 37, count 2 2006.285.07:29:13.29#ibcon#read 5, iclass 37, count 2 2006.285.07:29:13.29#ibcon#about to read 6, iclass 37, count 2 2006.285.07:29:13.29#ibcon#read 6, iclass 37, count 2 2006.285.07:29:13.29#ibcon#end of sib2, iclass 37, count 2 2006.285.07:29:13.29#ibcon#*after write, iclass 37, count 2 2006.285.07:29:13.29#ibcon#*before return 0, iclass 37, count 2 2006.285.07:29:13.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:29:13.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:29:13.29#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.07:29:13.29#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:13.29#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:29:13.41#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:29:13.41#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:29:13.41#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:29:13.41#ibcon#first serial, iclass 37, count 0 2006.285.07:29:13.41#ibcon#enter sib2, iclass 37, count 0 2006.285.07:29:13.41#ibcon#flushed, iclass 37, count 0 2006.285.07:29:13.41#ibcon#about to write, iclass 37, count 0 2006.285.07:29:13.41#ibcon#wrote, iclass 37, count 0 2006.285.07:29:13.41#ibcon#about to read 3, iclass 37, count 0 2006.285.07:29:13.43#ibcon#read 3, iclass 37, count 0 2006.285.07:29:13.43#ibcon#about to read 4, iclass 37, count 0 2006.285.07:29:13.43#ibcon#read 4, iclass 37, count 0 2006.285.07:29:13.43#ibcon#about to read 5, iclass 37, count 0 2006.285.07:29:13.43#ibcon#read 5, iclass 37, count 0 2006.285.07:29:13.43#ibcon#about to read 6, iclass 37, count 0 2006.285.07:29:13.43#ibcon#read 6, iclass 37, count 0 2006.285.07:29:13.43#ibcon#end of sib2, iclass 37, count 0 2006.285.07:29:13.43#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:29:13.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:29:13.43#ibcon#[25=USB\r\n] 2006.285.07:29:13.43#ibcon#*before write, iclass 37, count 0 2006.285.07:29:13.43#ibcon#enter sib2, iclass 37, count 0 2006.285.07:29:13.43#ibcon#flushed, iclass 37, count 0 2006.285.07:29:13.43#ibcon#about to write, iclass 37, count 0 2006.285.07:29:13.43#ibcon#wrote, iclass 37, count 0 2006.285.07:29:13.43#ibcon#about to read 3, iclass 37, count 0 2006.285.07:29:13.46#ibcon#read 3, iclass 37, count 0 2006.285.07:29:13.46#ibcon#about to read 4, iclass 37, count 0 2006.285.07:29:13.46#ibcon#read 4, iclass 37, count 0 2006.285.07:29:13.46#ibcon#about to read 5, iclass 37, count 0 2006.285.07:29:13.46#ibcon#read 5, iclass 37, count 0 2006.285.07:29:13.46#ibcon#about to read 6, iclass 37, count 0 2006.285.07:29:13.46#ibcon#read 6, iclass 37, count 0 2006.285.07:29:13.46#ibcon#end of sib2, iclass 37, count 0 2006.285.07:29:13.46#ibcon#*after write, iclass 37, count 0 2006.285.07:29:13.46#ibcon#*before return 0, iclass 37, count 0 2006.285.07:29:13.46#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:29:13.46#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:29:13.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:29:13.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:29:13.46$vck44/valo=8,884.99 2006.285.07:29:13.46#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.07:29:13.46#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.07:29:13.46#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:13.46#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:29:13.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:29:13.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:29:13.46#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:29:13.46#ibcon#first serial, iclass 39, count 0 2006.285.07:29:13.46#ibcon#enter sib2, iclass 39, count 0 2006.285.07:29:13.46#ibcon#flushed, iclass 39, count 0 2006.285.07:29:13.46#ibcon#about to write, iclass 39, count 0 2006.285.07:29:13.46#ibcon#wrote, iclass 39, count 0 2006.285.07:29:13.46#ibcon#about to read 3, iclass 39, count 0 2006.285.07:29:13.48#ibcon#read 3, iclass 39, count 0 2006.285.07:29:13.48#ibcon#about to read 4, iclass 39, count 0 2006.285.07:29:13.48#ibcon#read 4, iclass 39, count 0 2006.285.07:29:13.48#ibcon#about to read 5, iclass 39, count 0 2006.285.07:29:13.48#ibcon#read 5, iclass 39, count 0 2006.285.07:29:13.48#ibcon#about to read 6, iclass 39, count 0 2006.285.07:29:13.48#ibcon#read 6, iclass 39, count 0 2006.285.07:29:13.48#ibcon#end of sib2, iclass 39, count 0 2006.285.07:29:13.48#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:29:13.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:29:13.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:29:13.48#ibcon#*before write, iclass 39, count 0 2006.285.07:29:13.48#ibcon#enter sib2, iclass 39, count 0 2006.285.07:29:13.48#ibcon#flushed, iclass 39, count 0 2006.285.07:29:13.48#ibcon#about to write, iclass 39, count 0 2006.285.07:29:13.48#ibcon#wrote, iclass 39, count 0 2006.285.07:29:13.48#ibcon#about to read 3, iclass 39, count 0 2006.285.07:29:13.52#ibcon#read 3, iclass 39, count 0 2006.285.07:29:13.52#ibcon#about to read 4, iclass 39, count 0 2006.285.07:29:13.52#ibcon#read 4, iclass 39, count 0 2006.285.07:29:13.52#ibcon#about to read 5, iclass 39, count 0 2006.285.07:29:13.52#ibcon#read 5, iclass 39, count 0 2006.285.07:29:13.52#ibcon#about to read 6, iclass 39, count 0 2006.285.07:29:13.52#ibcon#read 6, iclass 39, count 0 2006.285.07:29:13.52#ibcon#end of sib2, iclass 39, count 0 2006.285.07:29:13.52#ibcon#*after write, iclass 39, count 0 2006.285.07:29:13.52#ibcon#*before return 0, iclass 39, count 0 2006.285.07:29:13.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:29:13.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:29:13.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:29:13.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:29:13.52$vck44/va=8,3 2006.285.07:29:13.52#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.07:29:13.52#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.07:29:13.52#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:13.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:29:13.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:29:13.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:29:13.58#ibcon#enter wrdev, iclass 3, count 2 2006.285.07:29:13.58#ibcon#first serial, iclass 3, count 2 2006.285.07:29:13.58#ibcon#enter sib2, iclass 3, count 2 2006.285.07:29:13.58#ibcon#flushed, iclass 3, count 2 2006.285.07:29:13.58#ibcon#about to write, iclass 3, count 2 2006.285.07:29:13.58#ibcon#wrote, iclass 3, count 2 2006.285.07:29:13.58#ibcon#about to read 3, iclass 3, count 2 2006.285.07:29:13.60#ibcon#read 3, iclass 3, count 2 2006.285.07:29:13.60#ibcon#about to read 4, iclass 3, count 2 2006.285.07:29:13.60#ibcon#read 4, iclass 3, count 2 2006.285.07:29:13.60#ibcon#about to read 5, iclass 3, count 2 2006.285.07:29:13.60#ibcon#read 5, iclass 3, count 2 2006.285.07:29:13.60#ibcon#about to read 6, iclass 3, count 2 2006.285.07:29:13.60#ibcon#read 6, iclass 3, count 2 2006.285.07:29:13.60#ibcon#end of sib2, iclass 3, count 2 2006.285.07:29:13.60#ibcon#*mode == 0, iclass 3, count 2 2006.285.07:29:13.60#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.07:29:13.60#ibcon#[25=AT08-03\r\n] 2006.285.07:29:13.60#ibcon#*before write, iclass 3, count 2 2006.285.07:29:13.60#ibcon#enter sib2, iclass 3, count 2 2006.285.07:29:13.60#ibcon#flushed, iclass 3, count 2 2006.285.07:29:13.60#ibcon#about to write, iclass 3, count 2 2006.285.07:29:13.60#ibcon#wrote, iclass 3, count 2 2006.285.07:29:13.60#ibcon#about to read 3, iclass 3, count 2 2006.285.07:29:13.63#ibcon#read 3, iclass 3, count 2 2006.285.07:29:13.63#ibcon#about to read 4, iclass 3, count 2 2006.285.07:29:13.63#ibcon#read 4, iclass 3, count 2 2006.285.07:29:13.63#ibcon#about to read 5, iclass 3, count 2 2006.285.07:29:13.63#ibcon#read 5, iclass 3, count 2 2006.285.07:29:13.63#ibcon#about to read 6, iclass 3, count 2 2006.285.07:29:13.63#ibcon#read 6, iclass 3, count 2 2006.285.07:29:13.63#ibcon#end of sib2, iclass 3, count 2 2006.285.07:29:13.63#ibcon#*after write, iclass 3, count 2 2006.285.07:29:13.63#ibcon#*before return 0, iclass 3, count 2 2006.285.07:29:13.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:29:13.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:29:13.63#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.07:29:13.63#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:13.63#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:29:13.75#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:29:13.75#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:29:13.75#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:29:13.75#ibcon#first serial, iclass 3, count 0 2006.285.07:29:13.75#ibcon#enter sib2, iclass 3, count 0 2006.285.07:29:13.75#ibcon#flushed, iclass 3, count 0 2006.285.07:29:13.75#ibcon#about to write, iclass 3, count 0 2006.285.07:29:13.75#ibcon#wrote, iclass 3, count 0 2006.285.07:29:13.75#ibcon#about to read 3, iclass 3, count 0 2006.285.07:29:13.77#ibcon#read 3, iclass 3, count 0 2006.285.07:29:13.77#ibcon#about to read 4, iclass 3, count 0 2006.285.07:29:13.77#ibcon#read 4, iclass 3, count 0 2006.285.07:29:13.77#ibcon#about to read 5, iclass 3, count 0 2006.285.07:29:13.77#ibcon#read 5, iclass 3, count 0 2006.285.07:29:13.77#ibcon#about to read 6, iclass 3, count 0 2006.285.07:29:13.77#ibcon#read 6, iclass 3, count 0 2006.285.07:29:13.77#ibcon#end of sib2, iclass 3, count 0 2006.285.07:29:13.77#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:29:13.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:29:13.77#ibcon#[25=USB\r\n] 2006.285.07:29:13.77#ibcon#*before write, iclass 3, count 0 2006.285.07:29:13.77#ibcon#enter sib2, iclass 3, count 0 2006.285.07:29:13.77#ibcon#flushed, iclass 3, count 0 2006.285.07:29:13.77#ibcon#about to write, iclass 3, count 0 2006.285.07:29:13.77#ibcon#wrote, iclass 3, count 0 2006.285.07:29:13.77#ibcon#about to read 3, iclass 3, count 0 2006.285.07:29:13.80#ibcon#read 3, iclass 3, count 0 2006.285.07:29:13.80#ibcon#about to read 4, iclass 3, count 0 2006.285.07:29:13.80#ibcon#read 4, iclass 3, count 0 2006.285.07:29:13.80#ibcon#about to read 5, iclass 3, count 0 2006.285.07:29:13.80#ibcon#read 5, iclass 3, count 0 2006.285.07:29:13.80#ibcon#about to read 6, iclass 3, count 0 2006.285.07:29:13.80#ibcon#read 6, iclass 3, count 0 2006.285.07:29:13.80#ibcon#end of sib2, iclass 3, count 0 2006.285.07:29:13.80#ibcon#*after write, iclass 3, count 0 2006.285.07:29:13.80#ibcon#*before return 0, iclass 3, count 0 2006.285.07:29:13.80#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:29:13.80#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:29:13.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:29:13.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:29:13.80$vck44/vblo=1,629.99 2006.285.07:29:13.80#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.07:29:13.80#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.07:29:13.80#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:13.80#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:29:13.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:29:13.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:29:13.80#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:29:13.80#ibcon#first serial, iclass 5, count 0 2006.285.07:29:13.80#ibcon#enter sib2, iclass 5, count 0 2006.285.07:29:13.80#ibcon#flushed, iclass 5, count 0 2006.285.07:29:13.80#ibcon#about to write, iclass 5, count 0 2006.285.07:29:13.80#ibcon#wrote, iclass 5, count 0 2006.285.07:29:13.80#ibcon#about to read 3, iclass 5, count 0 2006.285.07:29:13.82#ibcon#read 3, iclass 5, count 0 2006.285.07:29:13.82#ibcon#about to read 4, iclass 5, count 0 2006.285.07:29:13.82#ibcon#read 4, iclass 5, count 0 2006.285.07:29:13.82#ibcon#about to read 5, iclass 5, count 0 2006.285.07:29:13.82#ibcon#read 5, iclass 5, count 0 2006.285.07:29:13.82#ibcon#about to read 6, iclass 5, count 0 2006.285.07:29:13.82#ibcon#read 6, iclass 5, count 0 2006.285.07:29:13.82#ibcon#end of sib2, iclass 5, count 0 2006.285.07:29:13.82#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:29:13.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:29:13.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:29:13.82#ibcon#*before write, iclass 5, count 0 2006.285.07:29:13.82#ibcon#enter sib2, iclass 5, count 0 2006.285.07:29:13.82#ibcon#flushed, iclass 5, count 0 2006.285.07:29:13.82#ibcon#about to write, iclass 5, count 0 2006.285.07:29:13.82#ibcon#wrote, iclass 5, count 0 2006.285.07:29:13.82#ibcon#about to read 3, iclass 5, count 0 2006.285.07:29:13.86#ibcon#read 3, iclass 5, count 0 2006.285.07:29:13.86#ibcon#about to read 4, iclass 5, count 0 2006.285.07:29:13.86#ibcon#read 4, iclass 5, count 0 2006.285.07:29:13.86#ibcon#about to read 5, iclass 5, count 0 2006.285.07:29:13.86#ibcon#read 5, iclass 5, count 0 2006.285.07:29:13.86#ibcon#about to read 6, iclass 5, count 0 2006.285.07:29:13.86#ibcon#read 6, iclass 5, count 0 2006.285.07:29:13.86#ibcon#end of sib2, iclass 5, count 0 2006.285.07:29:13.86#ibcon#*after write, iclass 5, count 0 2006.285.07:29:13.86#ibcon#*before return 0, iclass 5, count 0 2006.285.07:29:13.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:29:13.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:29:13.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:29:13.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:29:13.86$vck44/vb=1,4 2006.285.07:29:13.86#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.07:29:13.86#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.07:29:13.86#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:13.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:29:13.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:29:13.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:29:13.86#ibcon#enter wrdev, iclass 7, count 2 2006.285.07:29:13.86#ibcon#first serial, iclass 7, count 2 2006.285.07:29:13.86#ibcon#enter sib2, iclass 7, count 2 2006.285.07:29:13.86#ibcon#flushed, iclass 7, count 2 2006.285.07:29:13.86#ibcon#about to write, iclass 7, count 2 2006.285.07:29:13.86#ibcon#wrote, iclass 7, count 2 2006.285.07:29:13.86#ibcon#about to read 3, iclass 7, count 2 2006.285.07:29:13.88#ibcon#read 3, iclass 7, count 2 2006.285.07:29:13.88#ibcon#about to read 4, iclass 7, count 2 2006.285.07:29:13.88#ibcon#read 4, iclass 7, count 2 2006.285.07:29:13.88#ibcon#about to read 5, iclass 7, count 2 2006.285.07:29:13.88#ibcon#read 5, iclass 7, count 2 2006.285.07:29:13.88#ibcon#about to read 6, iclass 7, count 2 2006.285.07:29:13.88#ibcon#read 6, iclass 7, count 2 2006.285.07:29:13.88#ibcon#end of sib2, iclass 7, count 2 2006.285.07:29:13.88#ibcon#*mode == 0, iclass 7, count 2 2006.285.07:29:13.88#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.07:29:13.88#ibcon#[27=AT01-04\r\n] 2006.285.07:29:13.88#ibcon#*before write, iclass 7, count 2 2006.285.07:29:13.88#ibcon#enter sib2, iclass 7, count 2 2006.285.07:29:13.88#ibcon#flushed, iclass 7, count 2 2006.285.07:29:13.88#ibcon#about to write, iclass 7, count 2 2006.285.07:29:13.88#ibcon#wrote, iclass 7, count 2 2006.285.07:29:13.88#ibcon#about to read 3, iclass 7, count 2 2006.285.07:29:13.91#ibcon#read 3, iclass 7, count 2 2006.285.07:29:13.91#ibcon#about to read 4, iclass 7, count 2 2006.285.07:29:13.91#ibcon#read 4, iclass 7, count 2 2006.285.07:29:13.91#ibcon#about to read 5, iclass 7, count 2 2006.285.07:29:13.91#ibcon#read 5, iclass 7, count 2 2006.285.07:29:13.91#ibcon#about to read 6, iclass 7, count 2 2006.285.07:29:13.91#ibcon#read 6, iclass 7, count 2 2006.285.07:29:13.91#ibcon#end of sib2, iclass 7, count 2 2006.285.07:29:13.91#ibcon#*after write, iclass 7, count 2 2006.285.07:29:13.91#ibcon#*before return 0, iclass 7, count 2 2006.285.07:29:13.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:29:13.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:29:13.91#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.07:29:13.91#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:13.91#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:29:14.03#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:29:14.03#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:29:14.03#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:29:14.03#ibcon#first serial, iclass 7, count 0 2006.285.07:29:14.03#ibcon#enter sib2, iclass 7, count 0 2006.285.07:29:14.03#ibcon#flushed, iclass 7, count 0 2006.285.07:29:14.03#ibcon#about to write, iclass 7, count 0 2006.285.07:29:14.03#ibcon#wrote, iclass 7, count 0 2006.285.07:29:14.03#ibcon#about to read 3, iclass 7, count 0 2006.285.07:29:14.05#ibcon#read 3, iclass 7, count 0 2006.285.07:29:14.05#ibcon#about to read 4, iclass 7, count 0 2006.285.07:29:14.05#ibcon#read 4, iclass 7, count 0 2006.285.07:29:14.05#ibcon#about to read 5, iclass 7, count 0 2006.285.07:29:14.05#ibcon#read 5, iclass 7, count 0 2006.285.07:29:14.05#ibcon#about to read 6, iclass 7, count 0 2006.285.07:29:14.05#ibcon#read 6, iclass 7, count 0 2006.285.07:29:14.05#ibcon#end of sib2, iclass 7, count 0 2006.285.07:29:14.05#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:29:14.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:29:14.05#ibcon#[27=USB\r\n] 2006.285.07:29:14.05#ibcon#*before write, iclass 7, count 0 2006.285.07:29:14.05#ibcon#enter sib2, iclass 7, count 0 2006.285.07:29:14.05#ibcon#flushed, iclass 7, count 0 2006.285.07:29:14.05#ibcon#about to write, iclass 7, count 0 2006.285.07:29:14.05#ibcon#wrote, iclass 7, count 0 2006.285.07:29:14.05#ibcon#about to read 3, iclass 7, count 0 2006.285.07:29:14.08#ibcon#read 3, iclass 7, count 0 2006.285.07:29:14.08#ibcon#about to read 4, iclass 7, count 0 2006.285.07:29:14.08#ibcon#read 4, iclass 7, count 0 2006.285.07:29:14.08#ibcon#about to read 5, iclass 7, count 0 2006.285.07:29:14.08#ibcon#read 5, iclass 7, count 0 2006.285.07:29:14.08#ibcon#about to read 6, iclass 7, count 0 2006.285.07:29:14.08#ibcon#read 6, iclass 7, count 0 2006.285.07:29:14.08#ibcon#end of sib2, iclass 7, count 0 2006.285.07:29:14.08#ibcon#*after write, iclass 7, count 0 2006.285.07:29:14.08#ibcon#*before return 0, iclass 7, count 0 2006.285.07:29:14.08#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:29:14.08#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:29:14.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:29:14.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:29:14.08$vck44/vblo=2,634.99 2006.285.07:29:14.08#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.07:29:14.08#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.07:29:14.08#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:14.08#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:29:14.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:29:14.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:29:14.08#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:29:14.08#ibcon#first serial, iclass 11, count 0 2006.285.07:29:14.08#ibcon#enter sib2, iclass 11, count 0 2006.285.07:29:14.08#ibcon#flushed, iclass 11, count 0 2006.285.07:29:14.08#ibcon#about to write, iclass 11, count 0 2006.285.07:29:14.08#ibcon#wrote, iclass 11, count 0 2006.285.07:29:14.08#ibcon#about to read 3, iclass 11, count 0 2006.285.07:29:14.10#ibcon#read 3, iclass 11, count 0 2006.285.07:29:14.10#ibcon#about to read 4, iclass 11, count 0 2006.285.07:29:14.10#ibcon#read 4, iclass 11, count 0 2006.285.07:29:14.10#ibcon#about to read 5, iclass 11, count 0 2006.285.07:29:14.10#ibcon#read 5, iclass 11, count 0 2006.285.07:29:14.10#ibcon#about to read 6, iclass 11, count 0 2006.285.07:29:14.10#ibcon#read 6, iclass 11, count 0 2006.285.07:29:14.10#ibcon#end of sib2, iclass 11, count 0 2006.285.07:29:14.10#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:29:14.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:29:14.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:29:14.10#ibcon#*before write, iclass 11, count 0 2006.285.07:29:14.10#ibcon#enter sib2, iclass 11, count 0 2006.285.07:29:14.10#ibcon#flushed, iclass 11, count 0 2006.285.07:29:14.10#ibcon#about to write, iclass 11, count 0 2006.285.07:29:14.10#ibcon#wrote, iclass 11, count 0 2006.285.07:29:14.10#ibcon#about to read 3, iclass 11, count 0 2006.285.07:29:14.14#ibcon#read 3, iclass 11, count 0 2006.285.07:29:14.14#ibcon#about to read 4, iclass 11, count 0 2006.285.07:29:14.14#ibcon#read 4, iclass 11, count 0 2006.285.07:29:14.14#ibcon#about to read 5, iclass 11, count 0 2006.285.07:29:14.14#ibcon#read 5, iclass 11, count 0 2006.285.07:29:14.14#ibcon#about to read 6, iclass 11, count 0 2006.285.07:29:14.14#ibcon#read 6, iclass 11, count 0 2006.285.07:29:14.14#ibcon#end of sib2, iclass 11, count 0 2006.285.07:29:14.14#ibcon#*after write, iclass 11, count 0 2006.285.07:29:14.14#ibcon#*before return 0, iclass 11, count 0 2006.285.07:29:14.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:29:14.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:29:14.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:29:14.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:29:14.14$vck44/vb=2,5 2006.285.07:29:14.14#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.07:29:14.14#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.07:29:14.14#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:14.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:29:14.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:29:14.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:29:14.20#ibcon#enter wrdev, iclass 13, count 2 2006.285.07:29:14.20#ibcon#first serial, iclass 13, count 2 2006.285.07:29:14.20#ibcon#enter sib2, iclass 13, count 2 2006.285.07:29:14.20#ibcon#flushed, iclass 13, count 2 2006.285.07:29:14.20#ibcon#about to write, iclass 13, count 2 2006.285.07:29:14.20#ibcon#wrote, iclass 13, count 2 2006.285.07:29:14.20#ibcon#about to read 3, iclass 13, count 2 2006.285.07:29:14.22#ibcon#read 3, iclass 13, count 2 2006.285.07:29:14.22#ibcon#about to read 4, iclass 13, count 2 2006.285.07:29:14.22#ibcon#read 4, iclass 13, count 2 2006.285.07:29:14.22#ibcon#about to read 5, iclass 13, count 2 2006.285.07:29:14.22#ibcon#read 5, iclass 13, count 2 2006.285.07:29:14.22#ibcon#about to read 6, iclass 13, count 2 2006.285.07:29:14.22#ibcon#read 6, iclass 13, count 2 2006.285.07:29:14.22#ibcon#end of sib2, iclass 13, count 2 2006.285.07:29:14.22#ibcon#*mode == 0, iclass 13, count 2 2006.285.07:29:14.22#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.07:29:14.22#ibcon#[27=AT02-05\r\n] 2006.285.07:29:14.22#ibcon#*before write, iclass 13, count 2 2006.285.07:29:14.22#ibcon#enter sib2, iclass 13, count 2 2006.285.07:29:14.22#ibcon#flushed, iclass 13, count 2 2006.285.07:29:14.22#ibcon#about to write, iclass 13, count 2 2006.285.07:29:14.22#ibcon#wrote, iclass 13, count 2 2006.285.07:29:14.22#ibcon#about to read 3, iclass 13, count 2 2006.285.07:29:14.25#ibcon#read 3, iclass 13, count 2 2006.285.07:29:14.25#ibcon#about to read 4, iclass 13, count 2 2006.285.07:29:14.25#ibcon#read 4, iclass 13, count 2 2006.285.07:29:14.25#ibcon#about to read 5, iclass 13, count 2 2006.285.07:29:14.25#ibcon#read 5, iclass 13, count 2 2006.285.07:29:14.25#ibcon#about to read 6, iclass 13, count 2 2006.285.07:29:14.25#ibcon#read 6, iclass 13, count 2 2006.285.07:29:14.25#ibcon#end of sib2, iclass 13, count 2 2006.285.07:29:14.25#ibcon#*after write, iclass 13, count 2 2006.285.07:29:14.25#ibcon#*before return 0, iclass 13, count 2 2006.285.07:29:14.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:29:14.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:29:14.25#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.07:29:14.25#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:14.25#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:29:14.37#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:29:14.37#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:29:14.37#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:29:14.37#ibcon#first serial, iclass 13, count 0 2006.285.07:29:14.37#ibcon#enter sib2, iclass 13, count 0 2006.285.07:29:14.37#ibcon#flushed, iclass 13, count 0 2006.285.07:29:14.37#ibcon#about to write, iclass 13, count 0 2006.285.07:29:14.37#ibcon#wrote, iclass 13, count 0 2006.285.07:29:14.37#ibcon#about to read 3, iclass 13, count 0 2006.285.07:29:14.39#ibcon#read 3, iclass 13, count 0 2006.285.07:29:14.39#ibcon#about to read 4, iclass 13, count 0 2006.285.07:29:14.39#ibcon#read 4, iclass 13, count 0 2006.285.07:29:14.39#ibcon#about to read 5, iclass 13, count 0 2006.285.07:29:14.39#ibcon#read 5, iclass 13, count 0 2006.285.07:29:14.39#ibcon#about to read 6, iclass 13, count 0 2006.285.07:29:14.39#ibcon#read 6, iclass 13, count 0 2006.285.07:29:14.39#ibcon#end of sib2, iclass 13, count 0 2006.285.07:29:14.39#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:29:14.39#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:29:14.39#ibcon#[27=USB\r\n] 2006.285.07:29:14.39#ibcon#*before write, iclass 13, count 0 2006.285.07:29:14.39#ibcon#enter sib2, iclass 13, count 0 2006.285.07:29:14.39#ibcon#flushed, iclass 13, count 0 2006.285.07:29:14.39#ibcon#about to write, iclass 13, count 0 2006.285.07:29:14.39#ibcon#wrote, iclass 13, count 0 2006.285.07:29:14.39#ibcon#about to read 3, iclass 13, count 0 2006.285.07:29:14.42#ibcon#read 3, iclass 13, count 0 2006.285.07:29:14.42#ibcon#about to read 4, iclass 13, count 0 2006.285.07:29:14.42#ibcon#read 4, iclass 13, count 0 2006.285.07:29:14.42#ibcon#about to read 5, iclass 13, count 0 2006.285.07:29:14.42#ibcon#read 5, iclass 13, count 0 2006.285.07:29:14.42#ibcon#about to read 6, iclass 13, count 0 2006.285.07:29:14.42#ibcon#read 6, iclass 13, count 0 2006.285.07:29:14.42#ibcon#end of sib2, iclass 13, count 0 2006.285.07:29:14.42#ibcon#*after write, iclass 13, count 0 2006.285.07:29:14.42#ibcon#*before return 0, iclass 13, count 0 2006.285.07:29:14.42#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:29:14.42#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:29:14.42#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:29:14.42#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:29:14.42$vck44/vblo=3,649.99 2006.285.07:29:14.42#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.07:29:14.42#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.07:29:14.42#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:14.42#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:29:14.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:29:14.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:29:14.42#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:29:14.42#ibcon#first serial, iclass 15, count 0 2006.285.07:29:14.42#ibcon#enter sib2, iclass 15, count 0 2006.285.07:29:14.42#ibcon#flushed, iclass 15, count 0 2006.285.07:29:14.42#ibcon#about to write, iclass 15, count 0 2006.285.07:29:14.42#ibcon#wrote, iclass 15, count 0 2006.285.07:29:14.42#ibcon#about to read 3, iclass 15, count 0 2006.285.07:29:14.44#ibcon#read 3, iclass 15, count 0 2006.285.07:29:14.44#ibcon#about to read 4, iclass 15, count 0 2006.285.07:29:14.44#ibcon#read 4, iclass 15, count 0 2006.285.07:29:14.44#ibcon#about to read 5, iclass 15, count 0 2006.285.07:29:14.44#ibcon#read 5, iclass 15, count 0 2006.285.07:29:14.44#ibcon#about to read 6, iclass 15, count 0 2006.285.07:29:14.44#ibcon#read 6, iclass 15, count 0 2006.285.07:29:14.44#ibcon#end of sib2, iclass 15, count 0 2006.285.07:29:14.44#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:29:14.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:29:14.44#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:29:14.44#ibcon#*before write, iclass 15, count 0 2006.285.07:29:14.44#ibcon#enter sib2, iclass 15, count 0 2006.285.07:29:14.44#ibcon#flushed, iclass 15, count 0 2006.285.07:29:14.44#ibcon#about to write, iclass 15, count 0 2006.285.07:29:14.44#ibcon#wrote, iclass 15, count 0 2006.285.07:29:14.44#ibcon#about to read 3, iclass 15, count 0 2006.285.07:29:14.48#ibcon#read 3, iclass 15, count 0 2006.285.07:29:14.48#ibcon#about to read 4, iclass 15, count 0 2006.285.07:29:14.48#ibcon#read 4, iclass 15, count 0 2006.285.07:29:14.48#ibcon#about to read 5, iclass 15, count 0 2006.285.07:29:14.48#ibcon#read 5, iclass 15, count 0 2006.285.07:29:14.48#ibcon#about to read 6, iclass 15, count 0 2006.285.07:29:14.48#ibcon#read 6, iclass 15, count 0 2006.285.07:29:14.48#ibcon#end of sib2, iclass 15, count 0 2006.285.07:29:14.48#ibcon#*after write, iclass 15, count 0 2006.285.07:29:14.48#ibcon#*before return 0, iclass 15, count 0 2006.285.07:29:14.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:29:14.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:29:14.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:29:14.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:29:14.48$vck44/vb=3,4 2006.285.07:29:14.48#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.07:29:14.48#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.07:29:14.48#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:14.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:29:14.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:29:14.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:29:14.54#ibcon#enter wrdev, iclass 17, count 2 2006.285.07:29:14.54#ibcon#first serial, iclass 17, count 2 2006.285.07:29:14.54#ibcon#enter sib2, iclass 17, count 2 2006.285.07:29:14.54#ibcon#flushed, iclass 17, count 2 2006.285.07:29:14.54#ibcon#about to write, iclass 17, count 2 2006.285.07:29:14.54#ibcon#wrote, iclass 17, count 2 2006.285.07:29:14.54#ibcon#about to read 3, iclass 17, count 2 2006.285.07:29:14.56#ibcon#read 3, iclass 17, count 2 2006.285.07:29:14.56#ibcon#about to read 4, iclass 17, count 2 2006.285.07:29:14.56#ibcon#read 4, iclass 17, count 2 2006.285.07:29:14.56#ibcon#about to read 5, iclass 17, count 2 2006.285.07:29:14.56#ibcon#read 5, iclass 17, count 2 2006.285.07:29:14.56#ibcon#about to read 6, iclass 17, count 2 2006.285.07:29:14.56#ibcon#read 6, iclass 17, count 2 2006.285.07:29:14.56#ibcon#end of sib2, iclass 17, count 2 2006.285.07:29:14.56#ibcon#*mode == 0, iclass 17, count 2 2006.285.07:29:14.56#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.07:29:14.56#ibcon#[27=AT03-04\r\n] 2006.285.07:29:14.56#ibcon#*before write, iclass 17, count 2 2006.285.07:29:14.56#ibcon#enter sib2, iclass 17, count 2 2006.285.07:29:14.56#ibcon#flushed, iclass 17, count 2 2006.285.07:29:14.56#ibcon#about to write, iclass 17, count 2 2006.285.07:29:14.56#ibcon#wrote, iclass 17, count 2 2006.285.07:29:14.56#ibcon#about to read 3, iclass 17, count 2 2006.285.07:29:14.59#ibcon#read 3, iclass 17, count 2 2006.285.07:29:14.59#ibcon#about to read 4, iclass 17, count 2 2006.285.07:29:14.59#ibcon#read 4, iclass 17, count 2 2006.285.07:29:14.59#ibcon#about to read 5, iclass 17, count 2 2006.285.07:29:14.59#ibcon#read 5, iclass 17, count 2 2006.285.07:29:14.59#ibcon#about to read 6, iclass 17, count 2 2006.285.07:29:14.59#ibcon#read 6, iclass 17, count 2 2006.285.07:29:14.59#ibcon#end of sib2, iclass 17, count 2 2006.285.07:29:14.59#ibcon#*after write, iclass 17, count 2 2006.285.07:29:14.59#ibcon#*before return 0, iclass 17, count 2 2006.285.07:29:14.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:29:14.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:29:14.59#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.07:29:14.59#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:14.59#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:29:14.71#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:29:14.71#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:29:14.71#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:29:14.71#ibcon#first serial, iclass 17, count 0 2006.285.07:29:14.71#ibcon#enter sib2, iclass 17, count 0 2006.285.07:29:14.71#ibcon#flushed, iclass 17, count 0 2006.285.07:29:14.71#ibcon#about to write, iclass 17, count 0 2006.285.07:29:14.71#ibcon#wrote, iclass 17, count 0 2006.285.07:29:14.71#ibcon#about to read 3, iclass 17, count 0 2006.285.07:29:14.73#ibcon#read 3, iclass 17, count 0 2006.285.07:29:14.73#ibcon#about to read 4, iclass 17, count 0 2006.285.07:29:14.73#ibcon#read 4, iclass 17, count 0 2006.285.07:29:14.73#ibcon#about to read 5, iclass 17, count 0 2006.285.07:29:14.73#ibcon#read 5, iclass 17, count 0 2006.285.07:29:14.73#ibcon#about to read 6, iclass 17, count 0 2006.285.07:29:14.73#ibcon#read 6, iclass 17, count 0 2006.285.07:29:14.73#ibcon#end of sib2, iclass 17, count 0 2006.285.07:29:14.73#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:29:14.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:29:14.73#ibcon#[27=USB\r\n] 2006.285.07:29:14.73#ibcon#*before write, iclass 17, count 0 2006.285.07:29:14.73#ibcon#enter sib2, iclass 17, count 0 2006.285.07:29:14.73#ibcon#flushed, iclass 17, count 0 2006.285.07:29:14.73#ibcon#about to write, iclass 17, count 0 2006.285.07:29:14.73#ibcon#wrote, iclass 17, count 0 2006.285.07:29:14.73#ibcon#about to read 3, iclass 17, count 0 2006.285.07:29:14.76#ibcon#read 3, iclass 17, count 0 2006.285.07:29:14.76#ibcon#about to read 4, iclass 17, count 0 2006.285.07:29:14.76#ibcon#read 4, iclass 17, count 0 2006.285.07:29:14.76#ibcon#about to read 5, iclass 17, count 0 2006.285.07:29:14.76#ibcon#read 5, iclass 17, count 0 2006.285.07:29:14.76#ibcon#about to read 6, iclass 17, count 0 2006.285.07:29:14.76#ibcon#read 6, iclass 17, count 0 2006.285.07:29:14.76#ibcon#end of sib2, iclass 17, count 0 2006.285.07:29:14.76#ibcon#*after write, iclass 17, count 0 2006.285.07:29:14.76#ibcon#*before return 0, iclass 17, count 0 2006.285.07:29:14.76#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:29:14.76#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:29:14.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:29:14.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:29:14.76$vck44/vblo=4,679.99 2006.285.07:29:14.76#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.07:29:14.76#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.07:29:14.76#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:14.76#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:29:14.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:29:14.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:29:14.76#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:29:14.76#ibcon#first serial, iclass 19, count 0 2006.285.07:29:14.76#ibcon#enter sib2, iclass 19, count 0 2006.285.07:29:14.76#ibcon#flushed, iclass 19, count 0 2006.285.07:29:14.76#ibcon#about to write, iclass 19, count 0 2006.285.07:29:14.76#ibcon#wrote, iclass 19, count 0 2006.285.07:29:14.76#ibcon#about to read 3, iclass 19, count 0 2006.285.07:29:14.78#ibcon#read 3, iclass 19, count 0 2006.285.07:29:14.78#ibcon#about to read 4, iclass 19, count 0 2006.285.07:29:14.78#ibcon#read 4, iclass 19, count 0 2006.285.07:29:14.78#ibcon#about to read 5, iclass 19, count 0 2006.285.07:29:14.78#ibcon#read 5, iclass 19, count 0 2006.285.07:29:14.78#ibcon#about to read 6, iclass 19, count 0 2006.285.07:29:14.78#ibcon#read 6, iclass 19, count 0 2006.285.07:29:14.78#ibcon#end of sib2, iclass 19, count 0 2006.285.07:29:14.78#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:29:14.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:29:14.78#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:29:14.78#ibcon#*before write, iclass 19, count 0 2006.285.07:29:14.78#ibcon#enter sib2, iclass 19, count 0 2006.285.07:29:14.78#ibcon#flushed, iclass 19, count 0 2006.285.07:29:14.78#ibcon#about to write, iclass 19, count 0 2006.285.07:29:14.78#ibcon#wrote, iclass 19, count 0 2006.285.07:29:14.78#ibcon#about to read 3, iclass 19, count 0 2006.285.07:29:14.82#ibcon#read 3, iclass 19, count 0 2006.285.07:29:14.82#ibcon#about to read 4, iclass 19, count 0 2006.285.07:29:14.82#ibcon#read 4, iclass 19, count 0 2006.285.07:29:14.82#ibcon#about to read 5, iclass 19, count 0 2006.285.07:29:14.82#ibcon#read 5, iclass 19, count 0 2006.285.07:29:14.82#ibcon#about to read 6, iclass 19, count 0 2006.285.07:29:14.82#ibcon#read 6, iclass 19, count 0 2006.285.07:29:14.82#ibcon#end of sib2, iclass 19, count 0 2006.285.07:29:14.82#ibcon#*after write, iclass 19, count 0 2006.285.07:29:14.82#ibcon#*before return 0, iclass 19, count 0 2006.285.07:29:14.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:29:14.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:29:14.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:29:14.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:29:14.82$vck44/vb=4,5 2006.285.07:29:14.82#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.07:29:14.82#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.07:29:14.82#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:14.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:29:14.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:29:14.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:29:14.88#ibcon#enter wrdev, iclass 21, count 2 2006.285.07:29:14.88#ibcon#first serial, iclass 21, count 2 2006.285.07:29:14.88#ibcon#enter sib2, iclass 21, count 2 2006.285.07:29:14.88#ibcon#flushed, iclass 21, count 2 2006.285.07:29:14.88#ibcon#about to write, iclass 21, count 2 2006.285.07:29:14.88#ibcon#wrote, iclass 21, count 2 2006.285.07:29:14.88#ibcon#about to read 3, iclass 21, count 2 2006.285.07:29:14.90#ibcon#read 3, iclass 21, count 2 2006.285.07:29:14.90#ibcon#about to read 4, iclass 21, count 2 2006.285.07:29:14.90#ibcon#read 4, iclass 21, count 2 2006.285.07:29:14.90#ibcon#about to read 5, iclass 21, count 2 2006.285.07:29:14.90#ibcon#read 5, iclass 21, count 2 2006.285.07:29:14.90#ibcon#about to read 6, iclass 21, count 2 2006.285.07:29:14.90#ibcon#read 6, iclass 21, count 2 2006.285.07:29:14.90#ibcon#end of sib2, iclass 21, count 2 2006.285.07:29:14.90#ibcon#*mode == 0, iclass 21, count 2 2006.285.07:29:14.90#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.07:29:14.90#ibcon#[27=AT04-05\r\n] 2006.285.07:29:14.90#ibcon#*before write, iclass 21, count 2 2006.285.07:29:14.90#ibcon#enter sib2, iclass 21, count 2 2006.285.07:29:14.90#ibcon#flushed, iclass 21, count 2 2006.285.07:29:14.90#ibcon#about to write, iclass 21, count 2 2006.285.07:29:14.90#ibcon#wrote, iclass 21, count 2 2006.285.07:29:14.90#ibcon#about to read 3, iclass 21, count 2 2006.285.07:29:14.93#ibcon#read 3, iclass 21, count 2 2006.285.07:29:14.93#ibcon#about to read 4, iclass 21, count 2 2006.285.07:29:14.93#ibcon#read 4, iclass 21, count 2 2006.285.07:29:14.93#ibcon#about to read 5, iclass 21, count 2 2006.285.07:29:14.93#ibcon#read 5, iclass 21, count 2 2006.285.07:29:14.93#ibcon#about to read 6, iclass 21, count 2 2006.285.07:29:14.93#ibcon#read 6, iclass 21, count 2 2006.285.07:29:14.93#ibcon#end of sib2, iclass 21, count 2 2006.285.07:29:14.93#ibcon#*after write, iclass 21, count 2 2006.285.07:29:14.93#ibcon#*before return 0, iclass 21, count 2 2006.285.07:29:14.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:29:14.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:29:14.93#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.07:29:14.93#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:14.93#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:29:15.05#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:29:15.05#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:29:15.05#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:29:15.05#ibcon#first serial, iclass 21, count 0 2006.285.07:29:15.05#ibcon#enter sib2, iclass 21, count 0 2006.285.07:29:15.05#ibcon#flushed, iclass 21, count 0 2006.285.07:29:15.05#ibcon#about to write, iclass 21, count 0 2006.285.07:29:15.05#ibcon#wrote, iclass 21, count 0 2006.285.07:29:15.05#ibcon#about to read 3, iclass 21, count 0 2006.285.07:29:15.07#ibcon#read 3, iclass 21, count 0 2006.285.07:29:15.07#ibcon#about to read 4, iclass 21, count 0 2006.285.07:29:15.07#ibcon#read 4, iclass 21, count 0 2006.285.07:29:15.07#ibcon#about to read 5, iclass 21, count 0 2006.285.07:29:15.07#ibcon#read 5, iclass 21, count 0 2006.285.07:29:15.07#ibcon#about to read 6, iclass 21, count 0 2006.285.07:29:15.07#ibcon#read 6, iclass 21, count 0 2006.285.07:29:15.07#ibcon#end of sib2, iclass 21, count 0 2006.285.07:29:15.07#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:29:15.07#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:29:15.07#ibcon#[27=USB\r\n] 2006.285.07:29:15.07#ibcon#*before write, iclass 21, count 0 2006.285.07:29:15.07#ibcon#enter sib2, iclass 21, count 0 2006.285.07:29:15.07#ibcon#flushed, iclass 21, count 0 2006.285.07:29:15.07#ibcon#about to write, iclass 21, count 0 2006.285.07:29:15.07#ibcon#wrote, iclass 21, count 0 2006.285.07:29:15.07#ibcon#about to read 3, iclass 21, count 0 2006.285.07:29:15.10#ibcon#read 3, iclass 21, count 0 2006.285.07:29:15.10#ibcon#about to read 4, iclass 21, count 0 2006.285.07:29:15.10#ibcon#read 4, iclass 21, count 0 2006.285.07:29:15.10#ibcon#about to read 5, iclass 21, count 0 2006.285.07:29:15.10#ibcon#read 5, iclass 21, count 0 2006.285.07:29:15.10#ibcon#about to read 6, iclass 21, count 0 2006.285.07:29:15.10#ibcon#read 6, iclass 21, count 0 2006.285.07:29:15.10#ibcon#end of sib2, iclass 21, count 0 2006.285.07:29:15.10#ibcon#*after write, iclass 21, count 0 2006.285.07:29:15.10#ibcon#*before return 0, iclass 21, count 0 2006.285.07:29:15.10#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:29:15.10#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:29:15.10#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:29:15.10#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:29:15.10$vck44/vblo=5,709.99 2006.285.07:29:15.10#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.07:29:15.10#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.07:29:15.10#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:15.10#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:29:15.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:29:15.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:29:15.10#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:29:15.10#ibcon#first serial, iclass 23, count 0 2006.285.07:29:15.10#ibcon#enter sib2, iclass 23, count 0 2006.285.07:29:15.10#ibcon#flushed, iclass 23, count 0 2006.285.07:29:15.10#ibcon#about to write, iclass 23, count 0 2006.285.07:29:15.10#ibcon#wrote, iclass 23, count 0 2006.285.07:29:15.10#ibcon#about to read 3, iclass 23, count 0 2006.285.07:29:15.12#ibcon#read 3, iclass 23, count 0 2006.285.07:29:15.12#ibcon#about to read 4, iclass 23, count 0 2006.285.07:29:15.12#ibcon#read 4, iclass 23, count 0 2006.285.07:29:15.12#ibcon#about to read 5, iclass 23, count 0 2006.285.07:29:15.12#ibcon#read 5, iclass 23, count 0 2006.285.07:29:15.12#ibcon#about to read 6, iclass 23, count 0 2006.285.07:29:15.12#ibcon#read 6, iclass 23, count 0 2006.285.07:29:15.12#ibcon#end of sib2, iclass 23, count 0 2006.285.07:29:15.12#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:29:15.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:29:15.12#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:29:15.12#ibcon#*before write, iclass 23, count 0 2006.285.07:29:15.12#ibcon#enter sib2, iclass 23, count 0 2006.285.07:29:15.12#ibcon#flushed, iclass 23, count 0 2006.285.07:29:15.12#ibcon#about to write, iclass 23, count 0 2006.285.07:29:15.12#ibcon#wrote, iclass 23, count 0 2006.285.07:29:15.12#ibcon#about to read 3, iclass 23, count 0 2006.285.07:29:15.16#ibcon#read 3, iclass 23, count 0 2006.285.07:29:15.16#ibcon#about to read 4, iclass 23, count 0 2006.285.07:29:15.16#ibcon#read 4, iclass 23, count 0 2006.285.07:29:15.16#ibcon#about to read 5, iclass 23, count 0 2006.285.07:29:15.16#ibcon#read 5, iclass 23, count 0 2006.285.07:29:15.16#ibcon#about to read 6, iclass 23, count 0 2006.285.07:29:15.16#ibcon#read 6, iclass 23, count 0 2006.285.07:29:15.16#ibcon#end of sib2, iclass 23, count 0 2006.285.07:29:15.16#ibcon#*after write, iclass 23, count 0 2006.285.07:29:15.16#ibcon#*before return 0, iclass 23, count 0 2006.285.07:29:15.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:29:15.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:29:15.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:29:15.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:29:15.16$vck44/vb=5,4 2006.285.07:29:15.16#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.07:29:15.16#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.07:29:15.16#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:15.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:29:15.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:29:15.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:29:15.22#ibcon#enter wrdev, iclass 25, count 2 2006.285.07:29:15.22#ibcon#first serial, iclass 25, count 2 2006.285.07:29:15.22#ibcon#enter sib2, iclass 25, count 2 2006.285.07:29:15.22#ibcon#flushed, iclass 25, count 2 2006.285.07:29:15.22#ibcon#about to write, iclass 25, count 2 2006.285.07:29:15.22#ibcon#wrote, iclass 25, count 2 2006.285.07:29:15.22#ibcon#about to read 3, iclass 25, count 2 2006.285.07:29:15.24#ibcon#read 3, iclass 25, count 2 2006.285.07:29:15.24#ibcon#about to read 4, iclass 25, count 2 2006.285.07:29:15.24#ibcon#read 4, iclass 25, count 2 2006.285.07:29:15.24#ibcon#about to read 5, iclass 25, count 2 2006.285.07:29:15.24#ibcon#read 5, iclass 25, count 2 2006.285.07:29:15.24#ibcon#about to read 6, iclass 25, count 2 2006.285.07:29:15.24#ibcon#read 6, iclass 25, count 2 2006.285.07:29:15.24#ibcon#end of sib2, iclass 25, count 2 2006.285.07:29:15.24#ibcon#*mode == 0, iclass 25, count 2 2006.285.07:29:15.24#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.07:29:15.24#ibcon#[27=AT05-04\r\n] 2006.285.07:29:15.24#ibcon#*before write, iclass 25, count 2 2006.285.07:29:15.24#ibcon#enter sib2, iclass 25, count 2 2006.285.07:29:15.24#ibcon#flushed, iclass 25, count 2 2006.285.07:29:15.24#ibcon#about to write, iclass 25, count 2 2006.285.07:29:15.24#ibcon#wrote, iclass 25, count 2 2006.285.07:29:15.24#ibcon#about to read 3, iclass 25, count 2 2006.285.07:29:15.27#ibcon#read 3, iclass 25, count 2 2006.285.07:29:15.27#ibcon#about to read 4, iclass 25, count 2 2006.285.07:29:15.27#ibcon#read 4, iclass 25, count 2 2006.285.07:29:15.27#ibcon#about to read 5, iclass 25, count 2 2006.285.07:29:15.27#ibcon#read 5, iclass 25, count 2 2006.285.07:29:15.27#ibcon#about to read 6, iclass 25, count 2 2006.285.07:29:15.27#ibcon#read 6, iclass 25, count 2 2006.285.07:29:15.27#ibcon#end of sib2, iclass 25, count 2 2006.285.07:29:15.27#ibcon#*after write, iclass 25, count 2 2006.285.07:29:15.27#ibcon#*before return 0, iclass 25, count 2 2006.285.07:29:15.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:29:15.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:29:15.27#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.07:29:15.27#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:15.27#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:29:15.39#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:29:15.39#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:29:15.39#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:29:15.39#ibcon#first serial, iclass 25, count 0 2006.285.07:29:15.39#ibcon#enter sib2, iclass 25, count 0 2006.285.07:29:15.39#ibcon#flushed, iclass 25, count 0 2006.285.07:29:15.39#ibcon#about to write, iclass 25, count 0 2006.285.07:29:15.39#ibcon#wrote, iclass 25, count 0 2006.285.07:29:15.39#ibcon#about to read 3, iclass 25, count 0 2006.285.07:29:15.41#ibcon#read 3, iclass 25, count 0 2006.285.07:29:15.41#ibcon#about to read 4, iclass 25, count 0 2006.285.07:29:15.41#ibcon#read 4, iclass 25, count 0 2006.285.07:29:15.41#ibcon#about to read 5, iclass 25, count 0 2006.285.07:29:15.41#ibcon#read 5, iclass 25, count 0 2006.285.07:29:15.41#ibcon#about to read 6, iclass 25, count 0 2006.285.07:29:15.41#ibcon#read 6, iclass 25, count 0 2006.285.07:29:15.41#ibcon#end of sib2, iclass 25, count 0 2006.285.07:29:15.41#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:29:15.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:29:15.41#ibcon#[27=USB\r\n] 2006.285.07:29:15.41#ibcon#*before write, iclass 25, count 0 2006.285.07:29:15.41#ibcon#enter sib2, iclass 25, count 0 2006.285.07:29:15.41#ibcon#flushed, iclass 25, count 0 2006.285.07:29:15.41#ibcon#about to write, iclass 25, count 0 2006.285.07:29:15.41#ibcon#wrote, iclass 25, count 0 2006.285.07:29:15.41#ibcon#about to read 3, iclass 25, count 0 2006.285.07:29:15.44#ibcon#read 3, iclass 25, count 0 2006.285.07:29:15.44#ibcon#about to read 4, iclass 25, count 0 2006.285.07:29:15.44#ibcon#read 4, iclass 25, count 0 2006.285.07:29:15.44#ibcon#about to read 5, iclass 25, count 0 2006.285.07:29:15.44#ibcon#read 5, iclass 25, count 0 2006.285.07:29:15.44#ibcon#about to read 6, iclass 25, count 0 2006.285.07:29:15.44#ibcon#read 6, iclass 25, count 0 2006.285.07:29:15.44#ibcon#end of sib2, iclass 25, count 0 2006.285.07:29:15.44#ibcon#*after write, iclass 25, count 0 2006.285.07:29:15.44#ibcon#*before return 0, iclass 25, count 0 2006.285.07:29:15.44#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:29:15.44#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:29:15.44#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:29:15.44#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:29:15.44$vck44/vblo=6,719.99 2006.285.07:29:15.44#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.07:29:15.44#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.07:29:15.44#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:15.44#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:29:15.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:29:15.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:29:15.44#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:29:15.44#ibcon#first serial, iclass 27, count 0 2006.285.07:29:15.44#ibcon#enter sib2, iclass 27, count 0 2006.285.07:29:15.44#ibcon#flushed, iclass 27, count 0 2006.285.07:29:15.44#ibcon#about to write, iclass 27, count 0 2006.285.07:29:15.44#ibcon#wrote, iclass 27, count 0 2006.285.07:29:15.44#ibcon#about to read 3, iclass 27, count 0 2006.285.07:29:15.46#ibcon#read 3, iclass 27, count 0 2006.285.07:29:15.46#ibcon#about to read 4, iclass 27, count 0 2006.285.07:29:15.46#ibcon#read 4, iclass 27, count 0 2006.285.07:29:15.46#ibcon#about to read 5, iclass 27, count 0 2006.285.07:29:15.46#ibcon#read 5, iclass 27, count 0 2006.285.07:29:15.46#ibcon#about to read 6, iclass 27, count 0 2006.285.07:29:15.46#ibcon#read 6, iclass 27, count 0 2006.285.07:29:15.46#ibcon#end of sib2, iclass 27, count 0 2006.285.07:29:15.46#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:29:15.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:29:15.46#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:29:15.46#ibcon#*before write, iclass 27, count 0 2006.285.07:29:15.46#ibcon#enter sib2, iclass 27, count 0 2006.285.07:29:15.46#ibcon#flushed, iclass 27, count 0 2006.285.07:29:15.46#ibcon#about to write, iclass 27, count 0 2006.285.07:29:15.46#ibcon#wrote, iclass 27, count 0 2006.285.07:29:15.46#ibcon#about to read 3, iclass 27, count 0 2006.285.07:29:15.50#ibcon#read 3, iclass 27, count 0 2006.285.07:29:15.50#ibcon#about to read 4, iclass 27, count 0 2006.285.07:29:15.50#ibcon#read 4, iclass 27, count 0 2006.285.07:29:15.50#ibcon#about to read 5, iclass 27, count 0 2006.285.07:29:15.50#ibcon#read 5, iclass 27, count 0 2006.285.07:29:15.50#ibcon#about to read 6, iclass 27, count 0 2006.285.07:29:15.50#ibcon#read 6, iclass 27, count 0 2006.285.07:29:15.50#ibcon#end of sib2, iclass 27, count 0 2006.285.07:29:15.50#ibcon#*after write, iclass 27, count 0 2006.285.07:29:15.50#ibcon#*before return 0, iclass 27, count 0 2006.285.07:29:15.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:29:15.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:29:15.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:29:15.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:29:15.50$vck44/vb=6,3 2006.285.07:29:15.50#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.07:29:15.50#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.07:29:15.50#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:15.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:29:15.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:29:15.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:29:15.56#ibcon#enter wrdev, iclass 29, count 2 2006.285.07:29:15.56#ibcon#first serial, iclass 29, count 2 2006.285.07:29:15.56#ibcon#enter sib2, iclass 29, count 2 2006.285.07:29:15.56#ibcon#flushed, iclass 29, count 2 2006.285.07:29:15.56#ibcon#about to write, iclass 29, count 2 2006.285.07:29:15.56#ibcon#wrote, iclass 29, count 2 2006.285.07:29:15.56#ibcon#about to read 3, iclass 29, count 2 2006.285.07:29:15.58#ibcon#read 3, iclass 29, count 2 2006.285.07:29:15.58#ibcon#about to read 4, iclass 29, count 2 2006.285.07:29:15.58#ibcon#read 4, iclass 29, count 2 2006.285.07:29:15.58#ibcon#about to read 5, iclass 29, count 2 2006.285.07:29:15.58#ibcon#read 5, iclass 29, count 2 2006.285.07:29:15.58#ibcon#about to read 6, iclass 29, count 2 2006.285.07:29:15.58#ibcon#read 6, iclass 29, count 2 2006.285.07:29:15.58#ibcon#end of sib2, iclass 29, count 2 2006.285.07:29:15.58#ibcon#*mode == 0, iclass 29, count 2 2006.285.07:29:15.58#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.07:29:15.58#ibcon#[27=AT06-03\r\n] 2006.285.07:29:15.58#ibcon#*before write, iclass 29, count 2 2006.285.07:29:15.58#ibcon#enter sib2, iclass 29, count 2 2006.285.07:29:15.58#ibcon#flushed, iclass 29, count 2 2006.285.07:29:15.58#ibcon#about to write, iclass 29, count 2 2006.285.07:29:15.58#ibcon#wrote, iclass 29, count 2 2006.285.07:29:15.58#ibcon#about to read 3, iclass 29, count 2 2006.285.07:29:15.61#ibcon#read 3, iclass 29, count 2 2006.285.07:29:15.61#ibcon#about to read 4, iclass 29, count 2 2006.285.07:29:15.61#ibcon#read 4, iclass 29, count 2 2006.285.07:29:15.61#ibcon#about to read 5, iclass 29, count 2 2006.285.07:29:15.61#ibcon#read 5, iclass 29, count 2 2006.285.07:29:15.61#ibcon#about to read 6, iclass 29, count 2 2006.285.07:29:15.61#ibcon#read 6, iclass 29, count 2 2006.285.07:29:15.61#ibcon#end of sib2, iclass 29, count 2 2006.285.07:29:15.61#ibcon#*after write, iclass 29, count 2 2006.285.07:29:15.61#ibcon#*before return 0, iclass 29, count 2 2006.285.07:29:15.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:29:15.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:29:15.61#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.07:29:15.61#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:15.61#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:29:15.73#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:29:15.73#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:29:15.73#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:29:15.73#ibcon#first serial, iclass 29, count 0 2006.285.07:29:15.73#ibcon#enter sib2, iclass 29, count 0 2006.285.07:29:15.73#ibcon#flushed, iclass 29, count 0 2006.285.07:29:15.73#ibcon#about to write, iclass 29, count 0 2006.285.07:29:15.73#ibcon#wrote, iclass 29, count 0 2006.285.07:29:15.73#ibcon#about to read 3, iclass 29, count 0 2006.285.07:29:15.75#ibcon#read 3, iclass 29, count 0 2006.285.07:29:15.75#ibcon#about to read 4, iclass 29, count 0 2006.285.07:29:15.75#ibcon#read 4, iclass 29, count 0 2006.285.07:29:15.75#ibcon#about to read 5, iclass 29, count 0 2006.285.07:29:15.75#ibcon#read 5, iclass 29, count 0 2006.285.07:29:15.75#ibcon#about to read 6, iclass 29, count 0 2006.285.07:29:15.75#ibcon#read 6, iclass 29, count 0 2006.285.07:29:15.75#ibcon#end of sib2, iclass 29, count 0 2006.285.07:29:15.75#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:29:15.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:29:15.75#ibcon#[27=USB\r\n] 2006.285.07:29:15.75#ibcon#*before write, iclass 29, count 0 2006.285.07:29:15.75#ibcon#enter sib2, iclass 29, count 0 2006.285.07:29:15.75#ibcon#flushed, iclass 29, count 0 2006.285.07:29:15.75#ibcon#about to write, iclass 29, count 0 2006.285.07:29:15.75#ibcon#wrote, iclass 29, count 0 2006.285.07:29:15.75#ibcon#about to read 3, iclass 29, count 0 2006.285.07:29:15.78#ibcon#read 3, iclass 29, count 0 2006.285.07:29:15.78#ibcon#about to read 4, iclass 29, count 0 2006.285.07:29:15.78#ibcon#read 4, iclass 29, count 0 2006.285.07:29:15.78#ibcon#about to read 5, iclass 29, count 0 2006.285.07:29:15.78#ibcon#read 5, iclass 29, count 0 2006.285.07:29:15.78#ibcon#about to read 6, iclass 29, count 0 2006.285.07:29:15.78#ibcon#read 6, iclass 29, count 0 2006.285.07:29:15.78#ibcon#end of sib2, iclass 29, count 0 2006.285.07:29:15.78#ibcon#*after write, iclass 29, count 0 2006.285.07:29:15.78#ibcon#*before return 0, iclass 29, count 0 2006.285.07:29:15.78#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:29:15.78#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:29:15.78#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:29:15.78#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:29:15.78$vck44/vblo=7,734.99 2006.285.07:29:15.78#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.07:29:15.78#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.07:29:15.78#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:15.78#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:29:15.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:29:15.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:29:15.78#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:29:15.78#ibcon#first serial, iclass 31, count 0 2006.285.07:29:15.78#ibcon#enter sib2, iclass 31, count 0 2006.285.07:29:15.78#ibcon#flushed, iclass 31, count 0 2006.285.07:29:15.78#ibcon#about to write, iclass 31, count 0 2006.285.07:29:15.78#ibcon#wrote, iclass 31, count 0 2006.285.07:29:15.78#ibcon#about to read 3, iclass 31, count 0 2006.285.07:29:15.80#ibcon#read 3, iclass 31, count 0 2006.285.07:29:15.80#ibcon#about to read 4, iclass 31, count 0 2006.285.07:29:15.80#ibcon#read 4, iclass 31, count 0 2006.285.07:29:15.80#ibcon#about to read 5, iclass 31, count 0 2006.285.07:29:15.80#ibcon#read 5, iclass 31, count 0 2006.285.07:29:15.80#ibcon#about to read 6, iclass 31, count 0 2006.285.07:29:15.80#ibcon#read 6, iclass 31, count 0 2006.285.07:29:15.80#ibcon#end of sib2, iclass 31, count 0 2006.285.07:29:15.80#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:29:15.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:29:15.80#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:29:15.80#ibcon#*before write, iclass 31, count 0 2006.285.07:29:15.80#ibcon#enter sib2, iclass 31, count 0 2006.285.07:29:15.80#ibcon#flushed, iclass 31, count 0 2006.285.07:29:15.80#ibcon#about to write, iclass 31, count 0 2006.285.07:29:15.80#ibcon#wrote, iclass 31, count 0 2006.285.07:29:15.80#ibcon#about to read 3, iclass 31, count 0 2006.285.07:29:15.84#ibcon#read 3, iclass 31, count 0 2006.285.07:29:15.84#ibcon#about to read 4, iclass 31, count 0 2006.285.07:29:15.84#ibcon#read 4, iclass 31, count 0 2006.285.07:29:15.84#ibcon#about to read 5, iclass 31, count 0 2006.285.07:29:15.84#ibcon#read 5, iclass 31, count 0 2006.285.07:29:15.84#ibcon#about to read 6, iclass 31, count 0 2006.285.07:29:15.84#ibcon#read 6, iclass 31, count 0 2006.285.07:29:15.84#ibcon#end of sib2, iclass 31, count 0 2006.285.07:29:15.84#ibcon#*after write, iclass 31, count 0 2006.285.07:29:15.84#ibcon#*before return 0, iclass 31, count 0 2006.285.07:29:15.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:29:15.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:29:15.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:29:15.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:29:15.84$vck44/vb=7,4 2006.285.07:29:15.84#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.07:29:15.84#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.07:29:15.84#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:15.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:29:15.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:29:15.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:29:15.90#ibcon#enter wrdev, iclass 33, count 2 2006.285.07:29:15.90#ibcon#first serial, iclass 33, count 2 2006.285.07:29:15.90#ibcon#enter sib2, iclass 33, count 2 2006.285.07:29:15.90#ibcon#flushed, iclass 33, count 2 2006.285.07:29:15.90#ibcon#about to write, iclass 33, count 2 2006.285.07:29:15.90#ibcon#wrote, iclass 33, count 2 2006.285.07:29:15.90#ibcon#about to read 3, iclass 33, count 2 2006.285.07:29:15.92#ibcon#read 3, iclass 33, count 2 2006.285.07:29:15.92#ibcon#about to read 4, iclass 33, count 2 2006.285.07:29:15.92#ibcon#read 4, iclass 33, count 2 2006.285.07:29:15.92#ibcon#about to read 5, iclass 33, count 2 2006.285.07:29:15.92#ibcon#read 5, iclass 33, count 2 2006.285.07:29:15.92#ibcon#about to read 6, iclass 33, count 2 2006.285.07:29:15.92#ibcon#read 6, iclass 33, count 2 2006.285.07:29:15.92#ibcon#end of sib2, iclass 33, count 2 2006.285.07:29:15.92#ibcon#*mode == 0, iclass 33, count 2 2006.285.07:29:15.92#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.07:29:15.92#ibcon#[27=AT07-04\r\n] 2006.285.07:29:15.92#ibcon#*before write, iclass 33, count 2 2006.285.07:29:15.92#ibcon#enter sib2, iclass 33, count 2 2006.285.07:29:15.92#ibcon#flushed, iclass 33, count 2 2006.285.07:29:15.92#ibcon#about to write, iclass 33, count 2 2006.285.07:29:15.92#ibcon#wrote, iclass 33, count 2 2006.285.07:29:15.92#ibcon#about to read 3, iclass 33, count 2 2006.285.07:29:15.95#ibcon#read 3, iclass 33, count 2 2006.285.07:29:15.95#ibcon#about to read 4, iclass 33, count 2 2006.285.07:29:15.95#ibcon#read 4, iclass 33, count 2 2006.285.07:29:15.95#ibcon#about to read 5, iclass 33, count 2 2006.285.07:29:15.95#ibcon#read 5, iclass 33, count 2 2006.285.07:29:15.95#ibcon#about to read 6, iclass 33, count 2 2006.285.07:29:15.95#ibcon#read 6, iclass 33, count 2 2006.285.07:29:15.95#ibcon#end of sib2, iclass 33, count 2 2006.285.07:29:15.95#ibcon#*after write, iclass 33, count 2 2006.285.07:29:15.95#ibcon#*before return 0, iclass 33, count 2 2006.285.07:29:15.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:29:15.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:29:15.95#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.07:29:15.95#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:15.95#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:29:16.07#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:29:16.07#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:29:16.07#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:29:16.07#ibcon#first serial, iclass 33, count 0 2006.285.07:29:16.07#ibcon#enter sib2, iclass 33, count 0 2006.285.07:29:16.07#ibcon#flushed, iclass 33, count 0 2006.285.07:29:16.07#ibcon#about to write, iclass 33, count 0 2006.285.07:29:16.07#ibcon#wrote, iclass 33, count 0 2006.285.07:29:16.07#ibcon#about to read 3, iclass 33, count 0 2006.285.07:29:16.09#ibcon#read 3, iclass 33, count 0 2006.285.07:29:16.09#ibcon#about to read 4, iclass 33, count 0 2006.285.07:29:16.09#ibcon#read 4, iclass 33, count 0 2006.285.07:29:16.09#ibcon#about to read 5, iclass 33, count 0 2006.285.07:29:16.09#ibcon#read 5, iclass 33, count 0 2006.285.07:29:16.09#ibcon#about to read 6, iclass 33, count 0 2006.285.07:29:16.09#ibcon#read 6, iclass 33, count 0 2006.285.07:29:16.09#ibcon#end of sib2, iclass 33, count 0 2006.285.07:29:16.09#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:29:16.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:29:16.09#ibcon#[27=USB\r\n] 2006.285.07:29:16.09#ibcon#*before write, iclass 33, count 0 2006.285.07:29:16.09#ibcon#enter sib2, iclass 33, count 0 2006.285.07:29:16.09#ibcon#flushed, iclass 33, count 0 2006.285.07:29:16.09#ibcon#about to write, iclass 33, count 0 2006.285.07:29:16.09#ibcon#wrote, iclass 33, count 0 2006.285.07:29:16.09#ibcon#about to read 3, iclass 33, count 0 2006.285.07:29:16.12#ibcon#read 3, iclass 33, count 0 2006.285.07:29:16.12#ibcon#about to read 4, iclass 33, count 0 2006.285.07:29:16.12#ibcon#read 4, iclass 33, count 0 2006.285.07:29:16.12#ibcon#about to read 5, iclass 33, count 0 2006.285.07:29:16.12#ibcon#read 5, iclass 33, count 0 2006.285.07:29:16.12#ibcon#about to read 6, iclass 33, count 0 2006.285.07:29:16.12#ibcon#read 6, iclass 33, count 0 2006.285.07:29:16.12#ibcon#end of sib2, iclass 33, count 0 2006.285.07:29:16.12#ibcon#*after write, iclass 33, count 0 2006.285.07:29:16.12#ibcon#*before return 0, iclass 33, count 0 2006.285.07:29:16.12#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:29:16.12#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:29:16.12#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:29:16.12#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:29:16.12$vck44/vblo=8,744.99 2006.285.07:29:16.12#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.07:29:16.12#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.07:29:16.12#ibcon#ireg 17 cls_cnt 0 2006.285.07:29:16.12#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:29:16.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:29:16.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:29:16.12#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:29:16.12#ibcon#first serial, iclass 35, count 0 2006.285.07:29:16.12#ibcon#enter sib2, iclass 35, count 0 2006.285.07:29:16.12#ibcon#flushed, iclass 35, count 0 2006.285.07:29:16.12#ibcon#about to write, iclass 35, count 0 2006.285.07:29:16.12#ibcon#wrote, iclass 35, count 0 2006.285.07:29:16.12#ibcon#about to read 3, iclass 35, count 0 2006.285.07:29:16.14#ibcon#read 3, iclass 35, count 0 2006.285.07:29:16.14#ibcon#about to read 4, iclass 35, count 0 2006.285.07:29:16.14#ibcon#read 4, iclass 35, count 0 2006.285.07:29:16.14#ibcon#about to read 5, iclass 35, count 0 2006.285.07:29:16.14#ibcon#read 5, iclass 35, count 0 2006.285.07:29:16.14#ibcon#about to read 6, iclass 35, count 0 2006.285.07:29:16.14#ibcon#read 6, iclass 35, count 0 2006.285.07:29:16.14#ibcon#end of sib2, iclass 35, count 0 2006.285.07:29:16.14#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:29:16.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:29:16.14#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:29:16.14#ibcon#*before write, iclass 35, count 0 2006.285.07:29:16.14#ibcon#enter sib2, iclass 35, count 0 2006.285.07:29:16.14#ibcon#flushed, iclass 35, count 0 2006.285.07:29:16.14#ibcon#about to write, iclass 35, count 0 2006.285.07:29:16.14#ibcon#wrote, iclass 35, count 0 2006.285.07:29:16.14#ibcon#about to read 3, iclass 35, count 0 2006.285.07:29:16.18#ibcon#read 3, iclass 35, count 0 2006.285.07:29:16.18#ibcon#about to read 4, iclass 35, count 0 2006.285.07:29:16.18#ibcon#read 4, iclass 35, count 0 2006.285.07:29:16.18#ibcon#about to read 5, iclass 35, count 0 2006.285.07:29:16.18#ibcon#read 5, iclass 35, count 0 2006.285.07:29:16.18#ibcon#about to read 6, iclass 35, count 0 2006.285.07:29:16.18#ibcon#read 6, iclass 35, count 0 2006.285.07:29:16.18#ibcon#end of sib2, iclass 35, count 0 2006.285.07:29:16.18#ibcon#*after write, iclass 35, count 0 2006.285.07:29:16.18#ibcon#*before return 0, iclass 35, count 0 2006.285.07:29:16.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:29:16.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:29:16.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:29:16.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:29:16.18$vck44/vb=8,4 2006.285.07:29:16.18#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.07:29:16.18#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.07:29:16.18#ibcon#ireg 11 cls_cnt 2 2006.285.07:29:16.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:29:16.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:29:16.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:29:16.24#ibcon#enter wrdev, iclass 37, count 2 2006.285.07:29:16.24#ibcon#first serial, iclass 37, count 2 2006.285.07:29:16.24#ibcon#enter sib2, iclass 37, count 2 2006.285.07:29:16.24#ibcon#flushed, iclass 37, count 2 2006.285.07:29:16.24#ibcon#about to write, iclass 37, count 2 2006.285.07:29:16.24#ibcon#wrote, iclass 37, count 2 2006.285.07:29:16.24#ibcon#about to read 3, iclass 37, count 2 2006.285.07:29:16.26#ibcon#read 3, iclass 37, count 2 2006.285.07:29:16.26#ibcon#about to read 4, iclass 37, count 2 2006.285.07:29:16.26#ibcon#read 4, iclass 37, count 2 2006.285.07:29:16.26#ibcon#about to read 5, iclass 37, count 2 2006.285.07:29:16.26#ibcon#read 5, iclass 37, count 2 2006.285.07:29:16.26#ibcon#about to read 6, iclass 37, count 2 2006.285.07:29:16.26#ibcon#read 6, iclass 37, count 2 2006.285.07:29:16.26#ibcon#end of sib2, iclass 37, count 2 2006.285.07:29:16.26#ibcon#*mode == 0, iclass 37, count 2 2006.285.07:29:16.26#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.07:29:16.26#ibcon#[27=AT08-04\r\n] 2006.285.07:29:16.26#ibcon#*before write, iclass 37, count 2 2006.285.07:29:16.26#ibcon#enter sib2, iclass 37, count 2 2006.285.07:29:16.26#ibcon#flushed, iclass 37, count 2 2006.285.07:29:16.26#ibcon#about to write, iclass 37, count 2 2006.285.07:29:16.26#ibcon#wrote, iclass 37, count 2 2006.285.07:29:16.26#ibcon#about to read 3, iclass 37, count 2 2006.285.07:29:16.29#ibcon#read 3, iclass 37, count 2 2006.285.07:29:16.29#ibcon#about to read 4, iclass 37, count 2 2006.285.07:29:16.29#ibcon#read 4, iclass 37, count 2 2006.285.07:29:16.29#ibcon#about to read 5, iclass 37, count 2 2006.285.07:29:16.29#ibcon#read 5, iclass 37, count 2 2006.285.07:29:16.29#ibcon#about to read 6, iclass 37, count 2 2006.285.07:29:16.29#ibcon#read 6, iclass 37, count 2 2006.285.07:29:16.29#ibcon#end of sib2, iclass 37, count 2 2006.285.07:29:16.29#ibcon#*after write, iclass 37, count 2 2006.285.07:29:16.29#ibcon#*before return 0, iclass 37, count 2 2006.285.07:29:16.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:29:16.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:29:16.29#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.07:29:16.29#ibcon#ireg 7 cls_cnt 0 2006.285.07:29:16.29#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:29:16.41#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:29:16.41#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:29:16.41#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:29:16.41#ibcon#first serial, iclass 37, count 0 2006.285.07:29:16.41#ibcon#enter sib2, iclass 37, count 0 2006.285.07:29:16.41#ibcon#flushed, iclass 37, count 0 2006.285.07:29:16.41#ibcon#about to write, iclass 37, count 0 2006.285.07:29:16.41#ibcon#wrote, iclass 37, count 0 2006.285.07:29:16.41#ibcon#about to read 3, iclass 37, count 0 2006.285.07:29:16.43#ibcon#read 3, iclass 37, count 0 2006.285.07:29:16.43#ibcon#about to read 4, iclass 37, count 0 2006.285.07:29:16.43#ibcon#read 4, iclass 37, count 0 2006.285.07:29:16.43#ibcon#about to read 5, iclass 37, count 0 2006.285.07:29:16.43#ibcon#read 5, iclass 37, count 0 2006.285.07:29:16.43#ibcon#about to read 6, iclass 37, count 0 2006.285.07:29:16.43#ibcon#read 6, iclass 37, count 0 2006.285.07:29:16.43#ibcon#end of sib2, iclass 37, count 0 2006.285.07:29:16.43#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:29:16.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:29:16.43#ibcon#[27=USB\r\n] 2006.285.07:29:16.43#ibcon#*before write, iclass 37, count 0 2006.285.07:29:16.43#ibcon#enter sib2, iclass 37, count 0 2006.285.07:29:16.43#ibcon#flushed, iclass 37, count 0 2006.285.07:29:16.43#ibcon#about to write, iclass 37, count 0 2006.285.07:29:16.43#ibcon#wrote, iclass 37, count 0 2006.285.07:29:16.43#ibcon#about to read 3, iclass 37, count 0 2006.285.07:29:16.46#ibcon#read 3, iclass 37, count 0 2006.285.07:29:16.46#ibcon#about to read 4, iclass 37, count 0 2006.285.07:29:16.46#ibcon#read 4, iclass 37, count 0 2006.285.07:29:16.46#ibcon#about to read 5, iclass 37, count 0 2006.285.07:29:16.46#ibcon#read 5, iclass 37, count 0 2006.285.07:29:16.46#ibcon#about to read 6, iclass 37, count 0 2006.285.07:29:16.46#ibcon#read 6, iclass 37, count 0 2006.285.07:29:16.46#ibcon#end of sib2, iclass 37, count 0 2006.285.07:29:16.46#ibcon#*after write, iclass 37, count 0 2006.285.07:29:16.46#ibcon#*before return 0, iclass 37, count 0 2006.285.07:29:16.46#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:29:16.46#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:29:16.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:29:16.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:29:16.46$vck44/vabw=wide 2006.285.07:29:16.46#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.07:29:16.46#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.07:29:16.46#ibcon#ireg 8 cls_cnt 0 2006.285.07:29:16.46#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:29:16.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:29:16.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:29:16.46#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:29:16.46#ibcon#first serial, iclass 39, count 0 2006.285.07:29:16.46#ibcon#enter sib2, iclass 39, count 0 2006.285.07:29:16.46#ibcon#flushed, iclass 39, count 0 2006.285.07:29:16.46#ibcon#about to write, iclass 39, count 0 2006.285.07:29:16.46#ibcon#wrote, iclass 39, count 0 2006.285.07:29:16.46#ibcon#about to read 3, iclass 39, count 0 2006.285.07:29:16.48#ibcon#read 3, iclass 39, count 0 2006.285.07:29:16.48#ibcon#about to read 4, iclass 39, count 0 2006.285.07:29:16.48#ibcon#read 4, iclass 39, count 0 2006.285.07:29:16.48#ibcon#about to read 5, iclass 39, count 0 2006.285.07:29:16.48#ibcon#read 5, iclass 39, count 0 2006.285.07:29:16.48#ibcon#about to read 6, iclass 39, count 0 2006.285.07:29:16.48#ibcon#read 6, iclass 39, count 0 2006.285.07:29:16.48#ibcon#end of sib2, iclass 39, count 0 2006.285.07:29:16.48#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:29:16.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:29:16.48#ibcon#[25=BW32\r\n] 2006.285.07:29:16.48#ibcon#*before write, iclass 39, count 0 2006.285.07:29:16.48#ibcon#enter sib2, iclass 39, count 0 2006.285.07:29:16.48#ibcon#flushed, iclass 39, count 0 2006.285.07:29:16.48#ibcon#about to write, iclass 39, count 0 2006.285.07:29:16.48#ibcon#wrote, iclass 39, count 0 2006.285.07:29:16.48#ibcon#about to read 3, iclass 39, count 0 2006.285.07:29:16.51#ibcon#read 3, iclass 39, count 0 2006.285.07:29:16.51#ibcon#about to read 4, iclass 39, count 0 2006.285.07:29:16.51#ibcon#read 4, iclass 39, count 0 2006.285.07:29:16.51#ibcon#about to read 5, iclass 39, count 0 2006.285.07:29:16.51#ibcon#read 5, iclass 39, count 0 2006.285.07:29:16.51#ibcon#about to read 6, iclass 39, count 0 2006.285.07:29:16.51#ibcon#read 6, iclass 39, count 0 2006.285.07:29:16.51#ibcon#end of sib2, iclass 39, count 0 2006.285.07:29:16.51#ibcon#*after write, iclass 39, count 0 2006.285.07:29:16.51#ibcon#*before return 0, iclass 39, count 0 2006.285.07:29:16.51#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:29:16.51#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:29:16.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:29:16.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:29:16.51$vck44/vbbw=wide 2006.285.07:29:16.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.07:29:16.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.07:29:16.51#ibcon#ireg 8 cls_cnt 0 2006.285.07:29:16.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:29:16.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:29:16.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:29:16.58#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:29:16.58#ibcon#first serial, iclass 3, count 0 2006.285.07:29:16.58#ibcon#enter sib2, iclass 3, count 0 2006.285.07:29:16.58#ibcon#flushed, iclass 3, count 0 2006.285.07:29:16.58#ibcon#about to write, iclass 3, count 0 2006.285.07:29:16.58#ibcon#wrote, iclass 3, count 0 2006.285.07:29:16.58#ibcon#about to read 3, iclass 3, count 0 2006.285.07:29:16.60#ibcon#read 3, iclass 3, count 0 2006.285.07:29:16.60#ibcon#about to read 4, iclass 3, count 0 2006.285.07:29:16.60#ibcon#read 4, iclass 3, count 0 2006.285.07:29:16.60#ibcon#about to read 5, iclass 3, count 0 2006.285.07:29:16.60#ibcon#read 5, iclass 3, count 0 2006.285.07:29:16.60#ibcon#about to read 6, iclass 3, count 0 2006.285.07:29:16.60#ibcon#read 6, iclass 3, count 0 2006.285.07:29:16.60#ibcon#end of sib2, iclass 3, count 0 2006.285.07:29:16.60#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:29:16.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:29:16.60#ibcon#[27=BW32\r\n] 2006.285.07:29:16.60#ibcon#*before write, iclass 3, count 0 2006.285.07:29:16.60#ibcon#enter sib2, iclass 3, count 0 2006.285.07:29:16.60#ibcon#flushed, iclass 3, count 0 2006.285.07:29:16.60#ibcon#about to write, iclass 3, count 0 2006.285.07:29:16.60#ibcon#wrote, iclass 3, count 0 2006.285.07:29:16.60#ibcon#about to read 3, iclass 3, count 0 2006.285.07:29:16.63#ibcon#read 3, iclass 3, count 0 2006.285.07:29:16.63#ibcon#about to read 4, iclass 3, count 0 2006.285.07:29:16.63#ibcon#read 4, iclass 3, count 0 2006.285.07:29:16.63#ibcon#about to read 5, iclass 3, count 0 2006.285.07:29:16.63#ibcon#read 5, iclass 3, count 0 2006.285.07:29:16.63#ibcon#about to read 6, iclass 3, count 0 2006.285.07:29:16.63#ibcon#read 6, iclass 3, count 0 2006.285.07:29:16.63#ibcon#end of sib2, iclass 3, count 0 2006.285.07:29:16.63#ibcon#*after write, iclass 3, count 0 2006.285.07:29:16.63#ibcon#*before return 0, iclass 3, count 0 2006.285.07:29:16.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:29:16.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:29:16.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:29:16.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:29:16.63$setupk4/ifdk4 2006.285.07:29:16.63$ifdk4/lo= 2006.285.07:29:16.63$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:29:16.63$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:29:16.63$ifdk4/patch= 2006.285.07:29:16.63$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:29:16.63$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:29:16.63$setupk4/!*+20s 2006.285.07:29:19.24#abcon#<5=/05 3.1 5.6 23.71 771014.3\r\n> 2006.285.07:29:19.26#abcon#{5=INTERFACE CLEAR} 2006.285.07:29:19.32#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:29:23.14#trakl#Source acquired 2006.285.07:29:24.14#flagr#flagr/antenna,acquired 2006.285.07:29:29.41#abcon#<5=/05 3.0 5.6 23.71 771014.3\r\n> 2006.285.07:29:29.43#abcon#{5=INTERFACE CLEAR} 2006.285.07:29:29.49#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:29:31.14$setupk4/"tpicd 2006.285.07:29:31.14$setupk4/echo=off 2006.285.07:29:31.14$setupk4/xlog=off 2006.285.07:29:31.14:!2006.285.07:32:16 2006.285.07:32:16.00:preob 2006.285.07:32:16.13/onsource/TRACKING 2006.285.07:32:16.13:!2006.285.07:32:26 2006.285.07:32:26.00:"tape 2006.285.07:32:26.00:"st=record 2006.285.07:32:26.00:data_valid=on 2006.285.07:32:26.00:midob 2006.285.07:32:27.14/onsource/TRACKING 2006.285.07:32:27.14/wx/23.65,1014.4,77 2006.285.07:32:27.28/cable/+6.4727E-03 2006.285.07:32:28.37/va/01,07,usb,yes,32,35 2006.285.07:32:28.37/va/02,06,usb,yes,32,32 2006.285.07:32:28.37/va/03,07,usb,yes,31,33 2006.285.07:32:28.37/va/04,06,usb,yes,33,34 2006.285.07:32:28.37/va/05,03,usb,yes,32,33 2006.285.07:32:28.37/va/06,04,usb,yes,29,29 2006.285.07:32:28.37/va/07,04,usb,yes,30,30 2006.285.07:32:28.37/va/08,03,usb,yes,30,37 2006.285.07:32:28.60/valo/01,524.99,yes,locked 2006.285.07:32:28.60/valo/02,534.99,yes,locked 2006.285.07:32:28.60/valo/03,564.99,yes,locked 2006.285.07:32:28.60/valo/04,624.99,yes,locked 2006.285.07:32:28.60/valo/05,734.99,yes,locked 2006.285.07:32:28.60/valo/06,814.99,yes,locked 2006.285.07:32:28.60/valo/07,864.99,yes,locked 2006.285.07:32:28.60/valo/08,884.99,yes,locked 2006.285.07:32:29.69/vb/01,04,usb,yes,31,29 2006.285.07:32:29.69/vb/02,05,usb,yes,29,29 2006.285.07:32:29.69/vb/03,04,usb,yes,30,33 2006.285.07:32:29.69/vb/04,05,usb,yes,30,29 2006.285.07:32:29.69/vb/05,04,usb,yes,27,29 2006.285.07:32:29.69/vb/06,03,usb,yes,38,34 2006.285.07:32:29.69/vb/07,04,usb,yes,31,31 2006.285.07:32:29.69/vb/08,04,usb,yes,28,32 2006.285.07:32:29.92/vblo/01,629.99,yes,locked 2006.285.07:32:29.92/vblo/02,634.99,yes,locked 2006.285.07:32:29.92/vblo/03,649.99,yes,locked 2006.285.07:32:29.92/vblo/04,679.99,yes,locked 2006.285.07:32:29.92/vblo/05,709.99,yes,locked 2006.285.07:32:29.92/vblo/06,719.99,yes,locked 2006.285.07:32:29.92/vblo/07,734.99,yes,locked 2006.285.07:32:29.92/vblo/08,744.99,yes,locked 2006.285.07:32:30.07/vabw/8 2006.285.07:32:30.22/vbbw/8 2006.285.07:32:30.31/xfe/off,on,12.2 2006.285.07:32:30.68/ifatt/23,28,28,28 2006.285.07:32:31.07/fmout-gps/S +2.74E-07 2006.285.07:32:31.09:!2006.285.07:33:06 2006.285.07:33:06.00:data_valid=off 2006.285.07:33:06.00:"et 2006.285.07:33:06.00:!+3s 2006.285.07:33:09.01:"tape 2006.285.07:33:09.01:postob 2006.285.07:33:09.19/cable/+6.4751E-03 2006.285.07:33:09.19/wx/23.63,1014.4,77 2006.285.07:33:10.08/fmout-gps/S +2.75E-07 2006.285.07:33:10.08:scan_name=285-0734,jd0610,40 2006.285.07:33:10.08:source=1921-293,192451.06,-291430.1,2000.0,ccw 2006.285.07:33:11.14#flagr#flagr/antenna,new-source 2006.285.07:33:11.14:checkk5 2006.285.07:33:11.51/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:33:11.89/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:33:12.27/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:33:12.67/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:33:13.30/chk_obsdata//k5ts1/T2850732??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.07:33:13.66/chk_obsdata//k5ts2/T2850732??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.07:33:14.06/chk_obsdata//k5ts3/T2850732??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.07:33:14.45/chk_obsdata//k5ts4/T2850732??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.07:33:15.45/k5log//k5ts1_log_newline 2006.285.07:33:16.20/k5log//k5ts2_log_newline 2006.285.07:33:17.35/k5log//k5ts3_log_newline 2006.285.07:33:18.03/k5log//k5ts4_log_newline 2006.285.07:33:18.05/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:33:18.05:setupk4=1 2006.285.07:33:18.05$setupk4/echo=on 2006.285.07:33:18.05$setupk4/pcalon 2006.285.07:33:18.05$pcalon/"no phase cal control is implemented here 2006.285.07:33:18.05$setupk4/"tpicd=stop 2006.285.07:33:18.05$setupk4/"rec=synch_on 2006.285.07:33:18.05$setupk4/"rec_mode=128 2006.285.07:33:18.05$setupk4/!* 2006.285.07:33:18.05$setupk4/recpk4 2006.285.07:33:18.05$recpk4/recpatch= 2006.285.07:33:18.05$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:33:18.05$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:33:18.05$setupk4/vck44 2006.285.07:33:18.05$vck44/valo=1,524.99 2006.285.07:33:18.05#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.07:33:18.05#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.07:33:18.05#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:18.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:33:18.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:33:18.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:33:18.05#ibcon#enter wrdev, iclass 34, count 0 2006.285.07:33:18.05#ibcon#first serial, iclass 34, count 0 2006.285.07:33:18.05#ibcon#enter sib2, iclass 34, count 0 2006.285.07:33:18.05#ibcon#flushed, iclass 34, count 0 2006.285.07:33:18.05#ibcon#about to write, iclass 34, count 0 2006.285.07:33:18.05#ibcon#wrote, iclass 34, count 0 2006.285.07:33:18.05#ibcon#about to read 3, iclass 34, count 0 2006.285.07:33:18.07#ibcon#read 3, iclass 34, count 0 2006.285.07:33:18.07#ibcon#about to read 4, iclass 34, count 0 2006.285.07:33:18.07#ibcon#read 4, iclass 34, count 0 2006.285.07:33:18.07#ibcon#about to read 5, iclass 34, count 0 2006.285.07:33:18.07#ibcon#read 5, iclass 34, count 0 2006.285.07:33:18.07#ibcon#about to read 6, iclass 34, count 0 2006.285.07:33:18.07#ibcon#read 6, iclass 34, count 0 2006.285.07:33:18.07#ibcon#end of sib2, iclass 34, count 0 2006.285.07:33:18.07#ibcon#*mode == 0, iclass 34, count 0 2006.285.07:33:18.07#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.07:33:18.07#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:33:18.07#ibcon#*before write, iclass 34, count 0 2006.285.07:33:18.07#ibcon#enter sib2, iclass 34, count 0 2006.285.07:33:18.07#ibcon#flushed, iclass 34, count 0 2006.285.07:33:18.07#ibcon#about to write, iclass 34, count 0 2006.285.07:33:18.07#ibcon#wrote, iclass 34, count 0 2006.285.07:33:18.07#ibcon#about to read 3, iclass 34, count 0 2006.285.07:33:18.12#ibcon#read 3, iclass 34, count 0 2006.285.07:33:18.12#ibcon#about to read 4, iclass 34, count 0 2006.285.07:33:18.12#ibcon#read 4, iclass 34, count 0 2006.285.07:33:18.12#ibcon#about to read 5, iclass 34, count 0 2006.285.07:33:18.12#ibcon#read 5, iclass 34, count 0 2006.285.07:33:18.12#ibcon#about to read 6, iclass 34, count 0 2006.285.07:33:18.12#ibcon#read 6, iclass 34, count 0 2006.285.07:33:18.12#ibcon#end of sib2, iclass 34, count 0 2006.285.07:33:18.12#ibcon#*after write, iclass 34, count 0 2006.285.07:33:18.12#ibcon#*before return 0, iclass 34, count 0 2006.285.07:33:18.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:33:18.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:33:18.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.07:33:18.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.07:33:18.12$vck44/va=1,7 2006.285.07:33:18.12#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.07:33:18.12#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.07:33:18.12#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:18.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:33:18.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:33:18.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:33:18.12#ibcon#enter wrdev, iclass 36, count 2 2006.285.07:33:18.12#ibcon#first serial, iclass 36, count 2 2006.285.07:33:18.12#ibcon#enter sib2, iclass 36, count 2 2006.285.07:33:18.12#ibcon#flushed, iclass 36, count 2 2006.285.07:33:18.12#ibcon#about to write, iclass 36, count 2 2006.285.07:33:18.12#ibcon#wrote, iclass 36, count 2 2006.285.07:33:18.12#ibcon#about to read 3, iclass 36, count 2 2006.285.07:33:18.14#ibcon#read 3, iclass 36, count 2 2006.285.07:33:18.14#ibcon#about to read 4, iclass 36, count 2 2006.285.07:33:18.14#ibcon#read 4, iclass 36, count 2 2006.285.07:33:18.14#ibcon#about to read 5, iclass 36, count 2 2006.285.07:33:18.14#ibcon#read 5, iclass 36, count 2 2006.285.07:33:18.14#ibcon#about to read 6, iclass 36, count 2 2006.285.07:33:18.14#ibcon#read 6, iclass 36, count 2 2006.285.07:33:18.14#ibcon#end of sib2, iclass 36, count 2 2006.285.07:33:18.14#ibcon#*mode == 0, iclass 36, count 2 2006.285.07:33:18.14#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.07:33:18.14#ibcon#[25=AT01-07\r\n] 2006.285.07:33:18.14#ibcon#*before write, iclass 36, count 2 2006.285.07:33:18.14#ibcon#enter sib2, iclass 36, count 2 2006.285.07:33:18.14#ibcon#flushed, iclass 36, count 2 2006.285.07:33:18.14#ibcon#about to write, iclass 36, count 2 2006.285.07:33:18.14#ibcon#wrote, iclass 36, count 2 2006.285.07:33:18.14#ibcon#about to read 3, iclass 36, count 2 2006.285.07:33:18.17#ibcon#read 3, iclass 36, count 2 2006.285.07:33:18.17#ibcon#about to read 4, iclass 36, count 2 2006.285.07:33:18.17#ibcon#read 4, iclass 36, count 2 2006.285.07:33:18.17#ibcon#about to read 5, iclass 36, count 2 2006.285.07:33:18.17#ibcon#read 5, iclass 36, count 2 2006.285.07:33:18.17#ibcon#about to read 6, iclass 36, count 2 2006.285.07:33:18.17#ibcon#read 6, iclass 36, count 2 2006.285.07:33:18.17#ibcon#end of sib2, iclass 36, count 2 2006.285.07:33:18.17#ibcon#*after write, iclass 36, count 2 2006.285.07:33:18.17#ibcon#*before return 0, iclass 36, count 2 2006.285.07:33:18.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:33:18.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:33:18.17#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.07:33:18.17#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:18.17#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:33:18.29#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:33:18.29#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:33:18.29#ibcon#enter wrdev, iclass 36, count 0 2006.285.07:33:18.29#ibcon#first serial, iclass 36, count 0 2006.285.07:33:18.29#ibcon#enter sib2, iclass 36, count 0 2006.285.07:33:18.29#ibcon#flushed, iclass 36, count 0 2006.285.07:33:18.29#ibcon#about to write, iclass 36, count 0 2006.285.07:33:18.29#ibcon#wrote, iclass 36, count 0 2006.285.07:33:18.29#ibcon#about to read 3, iclass 36, count 0 2006.285.07:33:18.31#ibcon#read 3, iclass 36, count 0 2006.285.07:33:18.31#ibcon#about to read 4, iclass 36, count 0 2006.285.07:33:18.31#ibcon#read 4, iclass 36, count 0 2006.285.07:33:18.31#ibcon#about to read 5, iclass 36, count 0 2006.285.07:33:18.31#ibcon#read 5, iclass 36, count 0 2006.285.07:33:18.31#ibcon#about to read 6, iclass 36, count 0 2006.285.07:33:18.31#ibcon#read 6, iclass 36, count 0 2006.285.07:33:18.31#ibcon#end of sib2, iclass 36, count 0 2006.285.07:33:18.31#ibcon#*mode == 0, iclass 36, count 0 2006.285.07:33:18.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.07:33:18.31#ibcon#[25=USB\r\n] 2006.285.07:33:18.31#ibcon#*before write, iclass 36, count 0 2006.285.07:33:18.31#ibcon#enter sib2, iclass 36, count 0 2006.285.07:33:18.31#ibcon#flushed, iclass 36, count 0 2006.285.07:33:18.31#ibcon#about to write, iclass 36, count 0 2006.285.07:33:18.31#ibcon#wrote, iclass 36, count 0 2006.285.07:33:18.31#ibcon#about to read 3, iclass 36, count 0 2006.285.07:33:18.34#ibcon#read 3, iclass 36, count 0 2006.285.07:33:18.34#ibcon#about to read 4, iclass 36, count 0 2006.285.07:33:18.34#ibcon#read 4, iclass 36, count 0 2006.285.07:33:18.34#ibcon#about to read 5, iclass 36, count 0 2006.285.07:33:18.34#ibcon#read 5, iclass 36, count 0 2006.285.07:33:18.34#ibcon#about to read 6, iclass 36, count 0 2006.285.07:33:18.34#ibcon#read 6, iclass 36, count 0 2006.285.07:33:18.34#ibcon#end of sib2, iclass 36, count 0 2006.285.07:33:18.34#ibcon#*after write, iclass 36, count 0 2006.285.07:33:18.34#ibcon#*before return 0, iclass 36, count 0 2006.285.07:33:18.34#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:33:18.34#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:33:18.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.07:33:18.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.07:33:18.34$vck44/valo=2,534.99 2006.285.07:33:18.34#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.07:33:18.34#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.07:33:18.34#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:18.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:33:18.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:33:18.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:33:18.34#ibcon#enter wrdev, iclass 38, count 0 2006.285.07:33:18.34#ibcon#first serial, iclass 38, count 0 2006.285.07:33:18.34#ibcon#enter sib2, iclass 38, count 0 2006.285.07:33:18.34#ibcon#flushed, iclass 38, count 0 2006.285.07:33:18.34#ibcon#about to write, iclass 38, count 0 2006.285.07:33:18.34#ibcon#wrote, iclass 38, count 0 2006.285.07:33:18.34#ibcon#about to read 3, iclass 38, count 0 2006.285.07:33:18.36#ibcon#read 3, iclass 38, count 0 2006.285.07:33:18.36#ibcon#about to read 4, iclass 38, count 0 2006.285.07:33:18.36#ibcon#read 4, iclass 38, count 0 2006.285.07:33:18.36#ibcon#about to read 5, iclass 38, count 0 2006.285.07:33:18.36#ibcon#read 5, iclass 38, count 0 2006.285.07:33:18.36#ibcon#about to read 6, iclass 38, count 0 2006.285.07:33:18.36#ibcon#read 6, iclass 38, count 0 2006.285.07:33:18.36#ibcon#end of sib2, iclass 38, count 0 2006.285.07:33:18.36#ibcon#*mode == 0, iclass 38, count 0 2006.285.07:33:18.36#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.07:33:18.36#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:33:18.36#ibcon#*before write, iclass 38, count 0 2006.285.07:33:18.36#ibcon#enter sib2, iclass 38, count 0 2006.285.07:33:18.36#ibcon#flushed, iclass 38, count 0 2006.285.07:33:18.36#ibcon#about to write, iclass 38, count 0 2006.285.07:33:18.36#ibcon#wrote, iclass 38, count 0 2006.285.07:33:18.36#ibcon#about to read 3, iclass 38, count 0 2006.285.07:33:18.40#ibcon#read 3, iclass 38, count 0 2006.285.07:33:18.40#ibcon#about to read 4, iclass 38, count 0 2006.285.07:33:18.40#ibcon#read 4, iclass 38, count 0 2006.285.07:33:18.40#ibcon#about to read 5, iclass 38, count 0 2006.285.07:33:18.40#ibcon#read 5, iclass 38, count 0 2006.285.07:33:18.40#ibcon#about to read 6, iclass 38, count 0 2006.285.07:33:18.40#ibcon#read 6, iclass 38, count 0 2006.285.07:33:18.40#ibcon#end of sib2, iclass 38, count 0 2006.285.07:33:18.40#ibcon#*after write, iclass 38, count 0 2006.285.07:33:18.40#ibcon#*before return 0, iclass 38, count 0 2006.285.07:33:18.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:33:18.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:33:18.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.07:33:18.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.07:33:18.40$vck44/va=2,6 2006.285.07:33:18.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.07:33:18.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.07:33:18.40#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:18.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:33:18.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:33:18.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:33:18.46#ibcon#enter wrdev, iclass 40, count 2 2006.285.07:33:18.46#ibcon#first serial, iclass 40, count 2 2006.285.07:33:18.46#ibcon#enter sib2, iclass 40, count 2 2006.285.07:33:18.46#ibcon#flushed, iclass 40, count 2 2006.285.07:33:18.46#ibcon#about to write, iclass 40, count 2 2006.285.07:33:18.46#ibcon#wrote, iclass 40, count 2 2006.285.07:33:18.46#ibcon#about to read 3, iclass 40, count 2 2006.285.07:33:18.48#ibcon#read 3, iclass 40, count 2 2006.285.07:33:18.48#ibcon#about to read 4, iclass 40, count 2 2006.285.07:33:18.48#ibcon#read 4, iclass 40, count 2 2006.285.07:33:18.48#ibcon#about to read 5, iclass 40, count 2 2006.285.07:33:18.48#ibcon#read 5, iclass 40, count 2 2006.285.07:33:18.48#ibcon#about to read 6, iclass 40, count 2 2006.285.07:33:18.48#ibcon#read 6, iclass 40, count 2 2006.285.07:33:18.48#ibcon#end of sib2, iclass 40, count 2 2006.285.07:33:18.48#ibcon#*mode == 0, iclass 40, count 2 2006.285.07:33:18.48#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.07:33:18.48#ibcon#[25=AT02-06\r\n] 2006.285.07:33:18.48#ibcon#*before write, iclass 40, count 2 2006.285.07:33:18.48#ibcon#enter sib2, iclass 40, count 2 2006.285.07:33:18.48#ibcon#flushed, iclass 40, count 2 2006.285.07:33:18.48#ibcon#about to write, iclass 40, count 2 2006.285.07:33:18.48#ibcon#wrote, iclass 40, count 2 2006.285.07:33:18.48#ibcon#about to read 3, iclass 40, count 2 2006.285.07:33:18.51#ibcon#read 3, iclass 40, count 2 2006.285.07:33:18.51#ibcon#about to read 4, iclass 40, count 2 2006.285.07:33:18.51#ibcon#read 4, iclass 40, count 2 2006.285.07:33:18.51#ibcon#about to read 5, iclass 40, count 2 2006.285.07:33:18.51#ibcon#read 5, iclass 40, count 2 2006.285.07:33:18.51#ibcon#about to read 6, iclass 40, count 2 2006.285.07:33:18.51#ibcon#read 6, iclass 40, count 2 2006.285.07:33:18.51#ibcon#end of sib2, iclass 40, count 2 2006.285.07:33:18.51#ibcon#*after write, iclass 40, count 2 2006.285.07:33:18.51#ibcon#*before return 0, iclass 40, count 2 2006.285.07:33:18.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:33:18.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:33:18.51#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.07:33:18.51#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:18.51#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:33:18.63#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:33:18.63#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:33:18.63#ibcon#enter wrdev, iclass 40, count 0 2006.285.07:33:18.63#ibcon#first serial, iclass 40, count 0 2006.285.07:33:18.63#ibcon#enter sib2, iclass 40, count 0 2006.285.07:33:18.63#ibcon#flushed, iclass 40, count 0 2006.285.07:33:18.63#ibcon#about to write, iclass 40, count 0 2006.285.07:33:18.63#ibcon#wrote, iclass 40, count 0 2006.285.07:33:18.63#ibcon#about to read 3, iclass 40, count 0 2006.285.07:33:18.65#ibcon#read 3, iclass 40, count 0 2006.285.07:33:18.65#ibcon#about to read 4, iclass 40, count 0 2006.285.07:33:18.65#ibcon#read 4, iclass 40, count 0 2006.285.07:33:18.65#ibcon#about to read 5, iclass 40, count 0 2006.285.07:33:18.65#ibcon#read 5, iclass 40, count 0 2006.285.07:33:18.65#ibcon#about to read 6, iclass 40, count 0 2006.285.07:33:18.65#ibcon#read 6, iclass 40, count 0 2006.285.07:33:18.65#ibcon#end of sib2, iclass 40, count 0 2006.285.07:33:18.65#ibcon#*mode == 0, iclass 40, count 0 2006.285.07:33:18.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.07:33:18.65#ibcon#[25=USB\r\n] 2006.285.07:33:18.65#ibcon#*before write, iclass 40, count 0 2006.285.07:33:18.65#ibcon#enter sib2, iclass 40, count 0 2006.285.07:33:18.65#ibcon#flushed, iclass 40, count 0 2006.285.07:33:18.65#ibcon#about to write, iclass 40, count 0 2006.285.07:33:18.65#ibcon#wrote, iclass 40, count 0 2006.285.07:33:18.65#ibcon#about to read 3, iclass 40, count 0 2006.285.07:33:18.68#ibcon#read 3, iclass 40, count 0 2006.285.07:33:18.68#ibcon#about to read 4, iclass 40, count 0 2006.285.07:33:18.68#ibcon#read 4, iclass 40, count 0 2006.285.07:33:18.68#ibcon#about to read 5, iclass 40, count 0 2006.285.07:33:18.68#ibcon#read 5, iclass 40, count 0 2006.285.07:33:18.68#ibcon#about to read 6, iclass 40, count 0 2006.285.07:33:18.68#ibcon#read 6, iclass 40, count 0 2006.285.07:33:18.68#ibcon#end of sib2, iclass 40, count 0 2006.285.07:33:18.68#ibcon#*after write, iclass 40, count 0 2006.285.07:33:18.68#ibcon#*before return 0, iclass 40, count 0 2006.285.07:33:18.68#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:33:18.68#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:33:18.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.07:33:18.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.07:33:18.68$vck44/valo=3,564.99 2006.285.07:33:18.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.07:33:18.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.07:33:18.68#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:18.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:33:18.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:33:18.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:33:18.68#ibcon#enter wrdev, iclass 4, count 0 2006.285.07:33:18.68#ibcon#first serial, iclass 4, count 0 2006.285.07:33:18.68#ibcon#enter sib2, iclass 4, count 0 2006.285.07:33:18.68#ibcon#flushed, iclass 4, count 0 2006.285.07:33:18.68#ibcon#about to write, iclass 4, count 0 2006.285.07:33:18.68#ibcon#wrote, iclass 4, count 0 2006.285.07:33:18.68#ibcon#about to read 3, iclass 4, count 0 2006.285.07:33:18.70#ibcon#read 3, iclass 4, count 0 2006.285.07:33:18.70#ibcon#about to read 4, iclass 4, count 0 2006.285.07:33:18.70#ibcon#read 4, iclass 4, count 0 2006.285.07:33:18.70#ibcon#about to read 5, iclass 4, count 0 2006.285.07:33:18.70#ibcon#read 5, iclass 4, count 0 2006.285.07:33:18.70#ibcon#about to read 6, iclass 4, count 0 2006.285.07:33:18.70#ibcon#read 6, iclass 4, count 0 2006.285.07:33:18.70#ibcon#end of sib2, iclass 4, count 0 2006.285.07:33:18.70#ibcon#*mode == 0, iclass 4, count 0 2006.285.07:33:18.70#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.07:33:18.70#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:33:18.70#ibcon#*before write, iclass 4, count 0 2006.285.07:33:18.70#ibcon#enter sib2, iclass 4, count 0 2006.285.07:33:18.70#ibcon#flushed, iclass 4, count 0 2006.285.07:33:18.70#ibcon#about to write, iclass 4, count 0 2006.285.07:33:18.70#ibcon#wrote, iclass 4, count 0 2006.285.07:33:18.70#ibcon#about to read 3, iclass 4, count 0 2006.285.07:33:18.74#ibcon#read 3, iclass 4, count 0 2006.285.07:33:18.74#ibcon#about to read 4, iclass 4, count 0 2006.285.07:33:18.74#ibcon#read 4, iclass 4, count 0 2006.285.07:33:18.74#ibcon#about to read 5, iclass 4, count 0 2006.285.07:33:18.74#ibcon#read 5, iclass 4, count 0 2006.285.07:33:18.74#ibcon#about to read 6, iclass 4, count 0 2006.285.07:33:18.74#ibcon#read 6, iclass 4, count 0 2006.285.07:33:18.74#ibcon#end of sib2, iclass 4, count 0 2006.285.07:33:18.74#ibcon#*after write, iclass 4, count 0 2006.285.07:33:18.74#ibcon#*before return 0, iclass 4, count 0 2006.285.07:33:18.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:33:18.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:33:18.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.07:33:18.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.07:33:18.74$vck44/va=3,7 2006.285.07:33:18.74#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.07:33:18.74#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.07:33:18.74#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:18.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:33:18.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:33:18.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:33:18.80#ibcon#enter wrdev, iclass 6, count 2 2006.285.07:33:18.80#ibcon#first serial, iclass 6, count 2 2006.285.07:33:18.80#ibcon#enter sib2, iclass 6, count 2 2006.285.07:33:18.80#ibcon#flushed, iclass 6, count 2 2006.285.07:33:18.80#ibcon#about to write, iclass 6, count 2 2006.285.07:33:18.80#ibcon#wrote, iclass 6, count 2 2006.285.07:33:18.80#ibcon#about to read 3, iclass 6, count 2 2006.285.07:33:18.82#ibcon#read 3, iclass 6, count 2 2006.285.07:33:18.82#ibcon#about to read 4, iclass 6, count 2 2006.285.07:33:18.82#ibcon#read 4, iclass 6, count 2 2006.285.07:33:18.82#ibcon#about to read 5, iclass 6, count 2 2006.285.07:33:18.82#ibcon#read 5, iclass 6, count 2 2006.285.07:33:18.82#ibcon#about to read 6, iclass 6, count 2 2006.285.07:33:18.82#ibcon#read 6, iclass 6, count 2 2006.285.07:33:18.82#ibcon#end of sib2, iclass 6, count 2 2006.285.07:33:18.82#ibcon#*mode == 0, iclass 6, count 2 2006.285.07:33:18.82#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.07:33:18.82#ibcon#[25=AT03-07\r\n] 2006.285.07:33:18.82#ibcon#*before write, iclass 6, count 2 2006.285.07:33:18.82#ibcon#enter sib2, iclass 6, count 2 2006.285.07:33:18.82#ibcon#flushed, iclass 6, count 2 2006.285.07:33:18.82#ibcon#about to write, iclass 6, count 2 2006.285.07:33:18.82#ibcon#wrote, iclass 6, count 2 2006.285.07:33:18.82#ibcon#about to read 3, iclass 6, count 2 2006.285.07:33:18.85#ibcon#read 3, iclass 6, count 2 2006.285.07:33:18.85#ibcon#about to read 4, iclass 6, count 2 2006.285.07:33:18.85#ibcon#read 4, iclass 6, count 2 2006.285.07:33:18.85#ibcon#about to read 5, iclass 6, count 2 2006.285.07:33:18.85#ibcon#read 5, iclass 6, count 2 2006.285.07:33:18.85#ibcon#about to read 6, iclass 6, count 2 2006.285.07:33:18.85#ibcon#read 6, iclass 6, count 2 2006.285.07:33:18.85#ibcon#end of sib2, iclass 6, count 2 2006.285.07:33:18.85#ibcon#*after write, iclass 6, count 2 2006.285.07:33:18.85#ibcon#*before return 0, iclass 6, count 2 2006.285.07:33:18.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:33:18.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:33:18.85#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.07:33:18.85#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:18.85#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:33:18.97#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:33:18.97#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:33:18.97#ibcon#enter wrdev, iclass 6, count 0 2006.285.07:33:18.97#ibcon#first serial, iclass 6, count 0 2006.285.07:33:18.97#ibcon#enter sib2, iclass 6, count 0 2006.285.07:33:18.97#ibcon#flushed, iclass 6, count 0 2006.285.07:33:18.97#ibcon#about to write, iclass 6, count 0 2006.285.07:33:18.97#ibcon#wrote, iclass 6, count 0 2006.285.07:33:18.97#ibcon#about to read 3, iclass 6, count 0 2006.285.07:33:18.99#ibcon#read 3, iclass 6, count 0 2006.285.07:33:18.99#ibcon#about to read 4, iclass 6, count 0 2006.285.07:33:18.99#ibcon#read 4, iclass 6, count 0 2006.285.07:33:18.99#ibcon#about to read 5, iclass 6, count 0 2006.285.07:33:18.99#ibcon#read 5, iclass 6, count 0 2006.285.07:33:18.99#ibcon#about to read 6, iclass 6, count 0 2006.285.07:33:18.99#ibcon#read 6, iclass 6, count 0 2006.285.07:33:18.99#ibcon#end of sib2, iclass 6, count 0 2006.285.07:33:18.99#ibcon#*mode == 0, iclass 6, count 0 2006.285.07:33:18.99#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.07:33:18.99#ibcon#[25=USB\r\n] 2006.285.07:33:18.99#ibcon#*before write, iclass 6, count 0 2006.285.07:33:18.99#ibcon#enter sib2, iclass 6, count 0 2006.285.07:33:18.99#ibcon#flushed, iclass 6, count 0 2006.285.07:33:18.99#ibcon#about to write, iclass 6, count 0 2006.285.07:33:18.99#ibcon#wrote, iclass 6, count 0 2006.285.07:33:18.99#ibcon#about to read 3, iclass 6, count 0 2006.285.07:33:19.02#ibcon#read 3, iclass 6, count 0 2006.285.07:33:19.02#ibcon#about to read 4, iclass 6, count 0 2006.285.07:33:19.02#ibcon#read 4, iclass 6, count 0 2006.285.07:33:19.02#ibcon#about to read 5, iclass 6, count 0 2006.285.07:33:19.02#ibcon#read 5, iclass 6, count 0 2006.285.07:33:19.02#ibcon#about to read 6, iclass 6, count 0 2006.285.07:33:19.02#ibcon#read 6, iclass 6, count 0 2006.285.07:33:19.02#ibcon#end of sib2, iclass 6, count 0 2006.285.07:33:19.02#ibcon#*after write, iclass 6, count 0 2006.285.07:33:19.02#ibcon#*before return 0, iclass 6, count 0 2006.285.07:33:19.02#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:33:19.02#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:33:19.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.07:33:19.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.07:33:19.02$vck44/valo=4,624.99 2006.285.07:33:19.02#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.07:33:19.02#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.07:33:19.02#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:19.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:33:19.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:33:19.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:33:19.02#ibcon#enter wrdev, iclass 10, count 0 2006.285.07:33:19.02#ibcon#first serial, iclass 10, count 0 2006.285.07:33:19.02#ibcon#enter sib2, iclass 10, count 0 2006.285.07:33:19.02#ibcon#flushed, iclass 10, count 0 2006.285.07:33:19.02#ibcon#about to write, iclass 10, count 0 2006.285.07:33:19.02#ibcon#wrote, iclass 10, count 0 2006.285.07:33:19.02#ibcon#about to read 3, iclass 10, count 0 2006.285.07:33:19.04#ibcon#read 3, iclass 10, count 0 2006.285.07:33:19.04#ibcon#about to read 4, iclass 10, count 0 2006.285.07:33:19.04#ibcon#read 4, iclass 10, count 0 2006.285.07:33:19.04#ibcon#about to read 5, iclass 10, count 0 2006.285.07:33:19.04#ibcon#read 5, iclass 10, count 0 2006.285.07:33:19.04#ibcon#about to read 6, iclass 10, count 0 2006.285.07:33:19.04#ibcon#read 6, iclass 10, count 0 2006.285.07:33:19.04#ibcon#end of sib2, iclass 10, count 0 2006.285.07:33:19.04#ibcon#*mode == 0, iclass 10, count 0 2006.285.07:33:19.04#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.07:33:19.04#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:33:19.04#ibcon#*before write, iclass 10, count 0 2006.285.07:33:19.04#ibcon#enter sib2, iclass 10, count 0 2006.285.07:33:19.04#ibcon#flushed, iclass 10, count 0 2006.285.07:33:19.04#ibcon#about to write, iclass 10, count 0 2006.285.07:33:19.04#ibcon#wrote, iclass 10, count 0 2006.285.07:33:19.04#ibcon#about to read 3, iclass 10, count 0 2006.285.07:33:19.08#ibcon#read 3, iclass 10, count 0 2006.285.07:33:19.08#ibcon#about to read 4, iclass 10, count 0 2006.285.07:33:19.08#ibcon#read 4, iclass 10, count 0 2006.285.07:33:19.08#ibcon#about to read 5, iclass 10, count 0 2006.285.07:33:19.08#ibcon#read 5, iclass 10, count 0 2006.285.07:33:19.08#ibcon#about to read 6, iclass 10, count 0 2006.285.07:33:19.08#ibcon#read 6, iclass 10, count 0 2006.285.07:33:19.08#ibcon#end of sib2, iclass 10, count 0 2006.285.07:33:19.08#ibcon#*after write, iclass 10, count 0 2006.285.07:33:19.08#ibcon#*before return 0, iclass 10, count 0 2006.285.07:33:19.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:33:19.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:33:19.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.07:33:19.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.07:33:19.08$vck44/va=4,6 2006.285.07:33:19.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.07:33:19.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.07:33:19.08#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:19.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:33:19.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:33:19.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:33:19.14#ibcon#enter wrdev, iclass 12, count 2 2006.285.07:33:19.14#ibcon#first serial, iclass 12, count 2 2006.285.07:33:19.14#ibcon#enter sib2, iclass 12, count 2 2006.285.07:33:19.14#ibcon#flushed, iclass 12, count 2 2006.285.07:33:19.14#ibcon#about to write, iclass 12, count 2 2006.285.07:33:19.14#ibcon#wrote, iclass 12, count 2 2006.285.07:33:19.14#ibcon#about to read 3, iclass 12, count 2 2006.285.07:33:19.16#ibcon#read 3, iclass 12, count 2 2006.285.07:33:19.16#ibcon#about to read 4, iclass 12, count 2 2006.285.07:33:19.16#ibcon#read 4, iclass 12, count 2 2006.285.07:33:19.16#ibcon#about to read 5, iclass 12, count 2 2006.285.07:33:19.16#ibcon#read 5, iclass 12, count 2 2006.285.07:33:19.16#ibcon#about to read 6, iclass 12, count 2 2006.285.07:33:19.16#ibcon#read 6, iclass 12, count 2 2006.285.07:33:19.16#ibcon#end of sib2, iclass 12, count 2 2006.285.07:33:19.16#ibcon#*mode == 0, iclass 12, count 2 2006.285.07:33:19.16#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.07:33:19.16#ibcon#[25=AT04-06\r\n] 2006.285.07:33:19.16#ibcon#*before write, iclass 12, count 2 2006.285.07:33:19.16#ibcon#enter sib2, iclass 12, count 2 2006.285.07:33:19.16#ibcon#flushed, iclass 12, count 2 2006.285.07:33:19.16#ibcon#about to write, iclass 12, count 2 2006.285.07:33:19.16#ibcon#wrote, iclass 12, count 2 2006.285.07:33:19.16#ibcon#about to read 3, iclass 12, count 2 2006.285.07:33:19.19#ibcon#read 3, iclass 12, count 2 2006.285.07:33:19.19#ibcon#about to read 4, iclass 12, count 2 2006.285.07:33:19.19#ibcon#read 4, iclass 12, count 2 2006.285.07:33:19.19#ibcon#about to read 5, iclass 12, count 2 2006.285.07:33:19.19#ibcon#read 5, iclass 12, count 2 2006.285.07:33:19.19#ibcon#about to read 6, iclass 12, count 2 2006.285.07:33:19.19#ibcon#read 6, iclass 12, count 2 2006.285.07:33:19.19#ibcon#end of sib2, iclass 12, count 2 2006.285.07:33:19.19#ibcon#*after write, iclass 12, count 2 2006.285.07:33:19.19#ibcon#*before return 0, iclass 12, count 2 2006.285.07:33:19.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:33:19.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:33:19.19#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.07:33:19.19#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:19.19#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:33:19.31#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:33:19.31#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:33:19.31#ibcon#enter wrdev, iclass 12, count 0 2006.285.07:33:19.31#ibcon#first serial, iclass 12, count 0 2006.285.07:33:19.31#ibcon#enter sib2, iclass 12, count 0 2006.285.07:33:19.31#ibcon#flushed, iclass 12, count 0 2006.285.07:33:19.31#ibcon#about to write, iclass 12, count 0 2006.285.07:33:19.31#ibcon#wrote, iclass 12, count 0 2006.285.07:33:19.31#ibcon#about to read 3, iclass 12, count 0 2006.285.07:33:19.33#ibcon#read 3, iclass 12, count 0 2006.285.07:33:19.33#ibcon#about to read 4, iclass 12, count 0 2006.285.07:33:19.33#ibcon#read 4, iclass 12, count 0 2006.285.07:33:19.33#ibcon#about to read 5, iclass 12, count 0 2006.285.07:33:19.33#ibcon#read 5, iclass 12, count 0 2006.285.07:33:19.33#ibcon#about to read 6, iclass 12, count 0 2006.285.07:33:19.33#ibcon#read 6, iclass 12, count 0 2006.285.07:33:19.33#ibcon#end of sib2, iclass 12, count 0 2006.285.07:33:19.33#ibcon#*mode == 0, iclass 12, count 0 2006.285.07:33:19.33#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.07:33:19.33#ibcon#[25=USB\r\n] 2006.285.07:33:19.33#ibcon#*before write, iclass 12, count 0 2006.285.07:33:19.33#ibcon#enter sib2, iclass 12, count 0 2006.285.07:33:19.33#ibcon#flushed, iclass 12, count 0 2006.285.07:33:19.33#ibcon#about to write, iclass 12, count 0 2006.285.07:33:19.33#ibcon#wrote, iclass 12, count 0 2006.285.07:33:19.33#ibcon#about to read 3, iclass 12, count 0 2006.285.07:33:19.36#ibcon#read 3, iclass 12, count 0 2006.285.07:33:19.36#ibcon#about to read 4, iclass 12, count 0 2006.285.07:33:19.36#ibcon#read 4, iclass 12, count 0 2006.285.07:33:19.36#ibcon#about to read 5, iclass 12, count 0 2006.285.07:33:19.36#ibcon#read 5, iclass 12, count 0 2006.285.07:33:19.36#ibcon#about to read 6, iclass 12, count 0 2006.285.07:33:19.36#ibcon#read 6, iclass 12, count 0 2006.285.07:33:19.36#ibcon#end of sib2, iclass 12, count 0 2006.285.07:33:19.36#ibcon#*after write, iclass 12, count 0 2006.285.07:33:19.36#ibcon#*before return 0, iclass 12, count 0 2006.285.07:33:19.36#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:33:19.36#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:33:19.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.07:33:19.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.07:33:19.36$vck44/valo=5,734.99 2006.285.07:33:19.36#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.07:33:19.36#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.07:33:19.36#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:19.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:33:19.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:33:19.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:33:19.36#ibcon#enter wrdev, iclass 14, count 0 2006.285.07:33:19.36#ibcon#first serial, iclass 14, count 0 2006.285.07:33:19.36#ibcon#enter sib2, iclass 14, count 0 2006.285.07:33:19.36#ibcon#flushed, iclass 14, count 0 2006.285.07:33:19.36#ibcon#about to write, iclass 14, count 0 2006.285.07:33:19.36#ibcon#wrote, iclass 14, count 0 2006.285.07:33:19.36#ibcon#about to read 3, iclass 14, count 0 2006.285.07:33:19.38#ibcon#read 3, iclass 14, count 0 2006.285.07:33:19.38#ibcon#about to read 4, iclass 14, count 0 2006.285.07:33:19.38#ibcon#read 4, iclass 14, count 0 2006.285.07:33:19.38#ibcon#about to read 5, iclass 14, count 0 2006.285.07:33:19.38#ibcon#read 5, iclass 14, count 0 2006.285.07:33:19.38#ibcon#about to read 6, iclass 14, count 0 2006.285.07:33:19.38#ibcon#read 6, iclass 14, count 0 2006.285.07:33:19.38#ibcon#end of sib2, iclass 14, count 0 2006.285.07:33:19.38#ibcon#*mode == 0, iclass 14, count 0 2006.285.07:33:19.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.07:33:19.38#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:33:19.38#ibcon#*before write, iclass 14, count 0 2006.285.07:33:19.38#ibcon#enter sib2, iclass 14, count 0 2006.285.07:33:19.38#ibcon#flushed, iclass 14, count 0 2006.285.07:33:19.38#ibcon#about to write, iclass 14, count 0 2006.285.07:33:19.38#ibcon#wrote, iclass 14, count 0 2006.285.07:33:19.38#ibcon#about to read 3, iclass 14, count 0 2006.285.07:33:19.42#ibcon#read 3, iclass 14, count 0 2006.285.07:33:19.42#ibcon#about to read 4, iclass 14, count 0 2006.285.07:33:19.42#ibcon#read 4, iclass 14, count 0 2006.285.07:33:19.42#ibcon#about to read 5, iclass 14, count 0 2006.285.07:33:19.42#ibcon#read 5, iclass 14, count 0 2006.285.07:33:19.42#ibcon#about to read 6, iclass 14, count 0 2006.285.07:33:19.42#ibcon#read 6, iclass 14, count 0 2006.285.07:33:19.42#ibcon#end of sib2, iclass 14, count 0 2006.285.07:33:19.42#ibcon#*after write, iclass 14, count 0 2006.285.07:33:19.42#ibcon#*before return 0, iclass 14, count 0 2006.285.07:33:19.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:33:19.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:33:19.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.07:33:19.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.07:33:19.42$vck44/va=5,3 2006.285.07:33:19.42#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.07:33:19.42#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.07:33:19.42#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:19.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:33:19.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:33:19.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:33:19.48#ibcon#enter wrdev, iclass 16, count 2 2006.285.07:33:19.48#ibcon#first serial, iclass 16, count 2 2006.285.07:33:19.48#ibcon#enter sib2, iclass 16, count 2 2006.285.07:33:19.48#ibcon#flushed, iclass 16, count 2 2006.285.07:33:19.48#ibcon#about to write, iclass 16, count 2 2006.285.07:33:19.48#ibcon#wrote, iclass 16, count 2 2006.285.07:33:19.48#ibcon#about to read 3, iclass 16, count 2 2006.285.07:33:19.50#ibcon#read 3, iclass 16, count 2 2006.285.07:33:19.50#ibcon#about to read 4, iclass 16, count 2 2006.285.07:33:19.50#ibcon#read 4, iclass 16, count 2 2006.285.07:33:19.50#ibcon#about to read 5, iclass 16, count 2 2006.285.07:33:19.50#ibcon#read 5, iclass 16, count 2 2006.285.07:33:19.50#ibcon#about to read 6, iclass 16, count 2 2006.285.07:33:19.50#ibcon#read 6, iclass 16, count 2 2006.285.07:33:19.50#ibcon#end of sib2, iclass 16, count 2 2006.285.07:33:19.50#ibcon#*mode == 0, iclass 16, count 2 2006.285.07:33:19.50#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.07:33:19.50#ibcon#[25=AT05-03\r\n] 2006.285.07:33:19.50#ibcon#*before write, iclass 16, count 2 2006.285.07:33:19.50#ibcon#enter sib2, iclass 16, count 2 2006.285.07:33:19.50#ibcon#flushed, iclass 16, count 2 2006.285.07:33:19.50#ibcon#about to write, iclass 16, count 2 2006.285.07:33:19.50#ibcon#wrote, iclass 16, count 2 2006.285.07:33:19.50#ibcon#about to read 3, iclass 16, count 2 2006.285.07:33:19.53#ibcon#read 3, iclass 16, count 2 2006.285.07:33:19.53#ibcon#about to read 4, iclass 16, count 2 2006.285.07:33:19.53#ibcon#read 4, iclass 16, count 2 2006.285.07:33:19.53#ibcon#about to read 5, iclass 16, count 2 2006.285.07:33:19.53#ibcon#read 5, iclass 16, count 2 2006.285.07:33:19.53#ibcon#about to read 6, iclass 16, count 2 2006.285.07:33:19.53#ibcon#read 6, iclass 16, count 2 2006.285.07:33:19.53#ibcon#end of sib2, iclass 16, count 2 2006.285.07:33:19.53#ibcon#*after write, iclass 16, count 2 2006.285.07:33:19.53#ibcon#*before return 0, iclass 16, count 2 2006.285.07:33:19.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:33:19.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:33:19.53#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.07:33:19.53#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:19.53#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:33:19.65#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:33:19.65#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:33:19.65#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:33:19.65#ibcon#first serial, iclass 16, count 0 2006.285.07:33:19.65#ibcon#enter sib2, iclass 16, count 0 2006.285.07:33:19.65#ibcon#flushed, iclass 16, count 0 2006.285.07:33:19.65#ibcon#about to write, iclass 16, count 0 2006.285.07:33:19.65#ibcon#wrote, iclass 16, count 0 2006.285.07:33:19.65#ibcon#about to read 3, iclass 16, count 0 2006.285.07:33:19.67#ibcon#read 3, iclass 16, count 0 2006.285.07:33:19.67#ibcon#about to read 4, iclass 16, count 0 2006.285.07:33:19.67#ibcon#read 4, iclass 16, count 0 2006.285.07:33:19.67#ibcon#about to read 5, iclass 16, count 0 2006.285.07:33:19.67#ibcon#read 5, iclass 16, count 0 2006.285.07:33:19.67#ibcon#about to read 6, iclass 16, count 0 2006.285.07:33:19.67#ibcon#read 6, iclass 16, count 0 2006.285.07:33:19.67#ibcon#end of sib2, iclass 16, count 0 2006.285.07:33:19.67#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:33:19.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:33:19.67#ibcon#[25=USB\r\n] 2006.285.07:33:19.67#ibcon#*before write, iclass 16, count 0 2006.285.07:33:19.67#ibcon#enter sib2, iclass 16, count 0 2006.285.07:33:19.67#ibcon#flushed, iclass 16, count 0 2006.285.07:33:19.67#ibcon#about to write, iclass 16, count 0 2006.285.07:33:19.67#ibcon#wrote, iclass 16, count 0 2006.285.07:33:19.67#ibcon#about to read 3, iclass 16, count 0 2006.285.07:33:19.70#ibcon#read 3, iclass 16, count 0 2006.285.07:33:19.70#ibcon#about to read 4, iclass 16, count 0 2006.285.07:33:19.70#ibcon#read 4, iclass 16, count 0 2006.285.07:33:19.70#ibcon#about to read 5, iclass 16, count 0 2006.285.07:33:19.70#ibcon#read 5, iclass 16, count 0 2006.285.07:33:19.70#ibcon#about to read 6, iclass 16, count 0 2006.285.07:33:19.70#ibcon#read 6, iclass 16, count 0 2006.285.07:33:19.70#ibcon#end of sib2, iclass 16, count 0 2006.285.07:33:19.70#ibcon#*after write, iclass 16, count 0 2006.285.07:33:19.70#ibcon#*before return 0, iclass 16, count 0 2006.285.07:33:19.70#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:33:19.70#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:33:19.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:33:19.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:33:19.70$vck44/valo=6,814.99 2006.285.07:33:19.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.07:33:19.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.07:33:19.70#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:19.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:33:19.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:33:19.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:33:19.70#ibcon#enter wrdev, iclass 18, count 0 2006.285.07:33:19.70#ibcon#first serial, iclass 18, count 0 2006.285.07:33:19.70#ibcon#enter sib2, iclass 18, count 0 2006.285.07:33:19.70#ibcon#flushed, iclass 18, count 0 2006.285.07:33:19.70#ibcon#about to write, iclass 18, count 0 2006.285.07:33:19.70#ibcon#wrote, iclass 18, count 0 2006.285.07:33:19.70#ibcon#about to read 3, iclass 18, count 0 2006.285.07:33:19.72#ibcon#read 3, iclass 18, count 0 2006.285.07:33:19.72#ibcon#about to read 4, iclass 18, count 0 2006.285.07:33:19.72#ibcon#read 4, iclass 18, count 0 2006.285.07:33:19.72#ibcon#about to read 5, iclass 18, count 0 2006.285.07:33:19.72#ibcon#read 5, iclass 18, count 0 2006.285.07:33:19.72#ibcon#about to read 6, iclass 18, count 0 2006.285.07:33:19.72#ibcon#read 6, iclass 18, count 0 2006.285.07:33:19.72#ibcon#end of sib2, iclass 18, count 0 2006.285.07:33:19.72#ibcon#*mode == 0, iclass 18, count 0 2006.285.07:33:19.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.07:33:19.72#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:33:19.72#ibcon#*before write, iclass 18, count 0 2006.285.07:33:19.72#ibcon#enter sib2, iclass 18, count 0 2006.285.07:33:19.72#ibcon#flushed, iclass 18, count 0 2006.285.07:33:19.72#ibcon#about to write, iclass 18, count 0 2006.285.07:33:19.72#ibcon#wrote, iclass 18, count 0 2006.285.07:33:19.72#ibcon#about to read 3, iclass 18, count 0 2006.285.07:33:19.76#ibcon#read 3, iclass 18, count 0 2006.285.07:33:19.76#ibcon#about to read 4, iclass 18, count 0 2006.285.07:33:19.76#ibcon#read 4, iclass 18, count 0 2006.285.07:33:19.76#ibcon#about to read 5, iclass 18, count 0 2006.285.07:33:19.76#ibcon#read 5, iclass 18, count 0 2006.285.07:33:19.76#ibcon#about to read 6, iclass 18, count 0 2006.285.07:33:19.76#ibcon#read 6, iclass 18, count 0 2006.285.07:33:19.76#ibcon#end of sib2, iclass 18, count 0 2006.285.07:33:19.76#ibcon#*after write, iclass 18, count 0 2006.285.07:33:19.76#ibcon#*before return 0, iclass 18, count 0 2006.285.07:33:19.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:33:19.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:33:19.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.07:33:19.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.07:33:19.76$vck44/va=6,4 2006.285.07:33:19.76#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.07:33:19.76#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.07:33:19.76#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:19.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:33:19.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:33:19.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:33:19.82#ibcon#enter wrdev, iclass 20, count 2 2006.285.07:33:19.82#ibcon#first serial, iclass 20, count 2 2006.285.07:33:19.82#ibcon#enter sib2, iclass 20, count 2 2006.285.07:33:19.82#ibcon#flushed, iclass 20, count 2 2006.285.07:33:19.82#ibcon#about to write, iclass 20, count 2 2006.285.07:33:19.82#ibcon#wrote, iclass 20, count 2 2006.285.07:33:19.82#ibcon#about to read 3, iclass 20, count 2 2006.285.07:33:19.84#ibcon#read 3, iclass 20, count 2 2006.285.07:33:19.84#ibcon#about to read 4, iclass 20, count 2 2006.285.07:33:19.84#ibcon#read 4, iclass 20, count 2 2006.285.07:33:19.84#ibcon#about to read 5, iclass 20, count 2 2006.285.07:33:19.84#ibcon#read 5, iclass 20, count 2 2006.285.07:33:19.84#ibcon#about to read 6, iclass 20, count 2 2006.285.07:33:19.84#ibcon#read 6, iclass 20, count 2 2006.285.07:33:19.84#ibcon#end of sib2, iclass 20, count 2 2006.285.07:33:19.84#ibcon#*mode == 0, iclass 20, count 2 2006.285.07:33:19.84#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.07:33:19.84#ibcon#[25=AT06-04\r\n] 2006.285.07:33:19.84#ibcon#*before write, iclass 20, count 2 2006.285.07:33:19.84#ibcon#enter sib2, iclass 20, count 2 2006.285.07:33:19.84#ibcon#flushed, iclass 20, count 2 2006.285.07:33:19.84#ibcon#about to write, iclass 20, count 2 2006.285.07:33:19.84#ibcon#wrote, iclass 20, count 2 2006.285.07:33:19.84#ibcon#about to read 3, iclass 20, count 2 2006.285.07:33:19.87#ibcon#read 3, iclass 20, count 2 2006.285.07:33:19.87#ibcon#about to read 4, iclass 20, count 2 2006.285.07:33:19.87#ibcon#read 4, iclass 20, count 2 2006.285.07:33:19.87#ibcon#about to read 5, iclass 20, count 2 2006.285.07:33:19.87#ibcon#read 5, iclass 20, count 2 2006.285.07:33:19.87#ibcon#about to read 6, iclass 20, count 2 2006.285.07:33:19.87#ibcon#read 6, iclass 20, count 2 2006.285.07:33:19.87#ibcon#end of sib2, iclass 20, count 2 2006.285.07:33:19.87#ibcon#*after write, iclass 20, count 2 2006.285.07:33:19.87#ibcon#*before return 0, iclass 20, count 2 2006.285.07:33:19.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:33:19.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:33:19.87#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.07:33:19.87#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:19.87#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:33:19.99#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:33:19.99#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:33:19.99#ibcon#enter wrdev, iclass 20, count 0 2006.285.07:33:19.99#ibcon#first serial, iclass 20, count 0 2006.285.07:33:19.99#ibcon#enter sib2, iclass 20, count 0 2006.285.07:33:19.99#ibcon#flushed, iclass 20, count 0 2006.285.07:33:19.99#ibcon#about to write, iclass 20, count 0 2006.285.07:33:19.99#ibcon#wrote, iclass 20, count 0 2006.285.07:33:19.99#ibcon#about to read 3, iclass 20, count 0 2006.285.07:33:20.01#ibcon#read 3, iclass 20, count 0 2006.285.07:33:20.01#ibcon#about to read 4, iclass 20, count 0 2006.285.07:33:20.01#ibcon#read 4, iclass 20, count 0 2006.285.07:33:20.01#ibcon#about to read 5, iclass 20, count 0 2006.285.07:33:20.01#ibcon#read 5, iclass 20, count 0 2006.285.07:33:20.01#ibcon#about to read 6, iclass 20, count 0 2006.285.07:33:20.01#ibcon#read 6, iclass 20, count 0 2006.285.07:33:20.01#ibcon#end of sib2, iclass 20, count 0 2006.285.07:33:20.01#ibcon#*mode == 0, iclass 20, count 0 2006.285.07:33:20.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.07:33:20.01#ibcon#[25=USB\r\n] 2006.285.07:33:20.01#ibcon#*before write, iclass 20, count 0 2006.285.07:33:20.01#ibcon#enter sib2, iclass 20, count 0 2006.285.07:33:20.01#ibcon#flushed, iclass 20, count 0 2006.285.07:33:20.01#ibcon#about to write, iclass 20, count 0 2006.285.07:33:20.01#ibcon#wrote, iclass 20, count 0 2006.285.07:33:20.01#ibcon#about to read 3, iclass 20, count 0 2006.285.07:33:20.04#ibcon#read 3, iclass 20, count 0 2006.285.07:33:20.04#ibcon#about to read 4, iclass 20, count 0 2006.285.07:33:20.04#ibcon#read 4, iclass 20, count 0 2006.285.07:33:20.04#ibcon#about to read 5, iclass 20, count 0 2006.285.07:33:20.04#ibcon#read 5, iclass 20, count 0 2006.285.07:33:20.04#ibcon#about to read 6, iclass 20, count 0 2006.285.07:33:20.04#ibcon#read 6, iclass 20, count 0 2006.285.07:33:20.04#ibcon#end of sib2, iclass 20, count 0 2006.285.07:33:20.04#ibcon#*after write, iclass 20, count 0 2006.285.07:33:20.04#ibcon#*before return 0, iclass 20, count 0 2006.285.07:33:20.04#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:33:20.04#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:33:20.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.07:33:20.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.07:33:20.04$vck44/valo=7,864.99 2006.285.07:33:20.04#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.07:33:20.04#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.07:33:20.04#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:20.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:33:20.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:33:20.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:33:20.04#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:33:20.04#ibcon#first serial, iclass 22, count 0 2006.285.07:33:20.04#ibcon#enter sib2, iclass 22, count 0 2006.285.07:33:20.04#ibcon#flushed, iclass 22, count 0 2006.285.07:33:20.04#ibcon#about to write, iclass 22, count 0 2006.285.07:33:20.04#ibcon#wrote, iclass 22, count 0 2006.285.07:33:20.04#ibcon#about to read 3, iclass 22, count 0 2006.285.07:33:20.06#ibcon#read 3, iclass 22, count 0 2006.285.07:33:20.06#ibcon#about to read 4, iclass 22, count 0 2006.285.07:33:20.06#ibcon#read 4, iclass 22, count 0 2006.285.07:33:20.06#ibcon#about to read 5, iclass 22, count 0 2006.285.07:33:20.06#ibcon#read 5, iclass 22, count 0 2006.285.07:33:20.06#ibcon#about to read 6, iclass 22, count 0 2006.285.07:33:20.06#ibcon#read 6, iclass 22, count 0 2006.285.07:33:20.06#ibcon#end of sib2, iclass 22, count 0 2006.285.07:33:20.06#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:33:20.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:33:20.06#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:33:20.06#ibcon#*before write, iclass 22, count 0 2006.285.07:33:20.06#ibcon#enter sib2, iclass 22, count 0 2006.285.07:33:20.06#ibcon#flushed, iclass 22, count 0 2006.285.07:33:20.06#ibcon#about to write, iclass 22, count 0 2006.285.07:33:20.06#ibcon#wrote, iclass 22, count 0 2006.285.07:33:20.06#ibcon#about to read 3, iclass 22, count 0 2006.285.07:33:20.10#ibcon#read 3, iclass 22, count 0 2006.285.07:33:20.10#ibcon#about to read 4, iclass 22, count 0 2006.285.07:33:20.10#ibcon#read 4, iclass 22, count 0 2006.285.07:33:20.10#ibcon#about to read 5, iclass 22, count 0 2006.285.07:33:20.10#ibcon#read 5, iclass 22, count 0 2006.285.07:33:20.10#ibcon#about to read 6, iclass 22, count 0 2006.285.07:33:20.10#ibcon#read 6, iclass 22, count 0 2006.285.07:33:20.10#ibcon#end of sib2, iclass 22, count 0 2006.285.07:33:20.10#ibcon#*after write, iclass 22, count 0 2006.285.07:33:20.10#ibcon#*before return 0, iclass 22, count 0 2006.285.07:33:20.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:33:20.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:33:20.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:33:20.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:33:20.10$vck44/va=7,4 2006.285.07:33:20.10#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.07:33:20.10#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.07:33:20.10#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:20.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:33:20.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:33:20.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:33:20.16#ibcon#enter wrdev, iclass 24, count 2 2006.285.07:33:20.16#ibcon#first serial, iclass 24, count 2 2006.285.07:33:20.16#ibcon#enter sib2, iclass 24, count 2 2006.285.07:33:20.16#ibcon#flushed, iclass 24, count 2 2006.285.07:33:20.16#ibcon#about to write, iclass 24, count 2 2006.285.07:33:20.16#ibcon#wrote, iclass 24, count 2 2006.285.07:33:20.16#ibcon#about to read 3, iclass 24, count 2 2006.285.07:33:20.18#ibcon#read 3, iclass 24, count 2 2006.285.07:33:20.18#ibcon#about to read 4, iclass 24, count 2 2006.285.07:33:20.18#ibcon#read 4, iclass 24, count 2 2006.285.07:33:20.18#ibcon#about to read 5, iclass 24, count 2 2006.285.07:33:20.18#ibcon#read 5, iclass 24, count 2 2006.285.07:33:20.18#ibcon#about to read 6, iclass 24, count 2 2006.285.07:33:20.18#ibcon#read 6, iclass 24, count 2 2006.285.07:33:20.18#ibcon#end of sib2, iclass 24, count 2 2006.285.07:33:20.18#ibcon#*mode == 0, iclass 24, count 2 2006.285.07:33:20.18#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.07:33:20.18#ibcon#[25=AT07-04\r\n] 2006.285.07:33:20.18#ibcon#*before write, iclass 24, count 2 2006.285.07:33:20.18#ibcon#enter sib2, iclass 24, count 2 2006.285.07:33:20.18#ibcon#flushed, iclass 24, count 2 2006.285.07:33:20.18#ibcon#about to write, iclass 24, count 2 2006.285.07:33:20.18#ibcon#wrote, iclass 24, count 2 2006.285.07:33:20.18#ibcon#about to read 3, iclass 24, count 2 2006.285.07:33:20.21#ibcon#read 3, iclass 24, count 2 2006.285.07:33:20.21#ibcon#about to read 4, iclass 24, count 2 2006.285.07:33:20.21#ibcon#read 4, iclass 24, count 2 2006.285.07:33:20.21#ibcon#about to read 5, iclass 24, count 2 2006.285.07:33:20.21#ibcon#read 5, iclass 24, count 2 2006.285.07:33:20.21#ibcon#about to read 6, iclass 24, count 2 2006.285.07:33:20.21#ibcon#read 6, iclass 24, count 2 2006.285.07:33:20.21#ibcon#end of sib2, iclass 24, count 2 2006.285.07:33:20.21#ibcon#*after write, iclass 24, count 2 2006.285.07:33:20.21#ibcon#*before return 0, iclass 24, count 2 2006.285.07:33:20.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:33:20.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:33:20.21#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.07:33:20.21#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:20.21#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:33:20.33#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:33:20.33#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:33:20.33#ibcon#enter wrdev, iclass 24, count 0 2006.285.07:33:20.33#ibcon#first serial, iclass 24, count 0 2006.285.07:33:20.33#ibcon#enter sib2, iclass 24, count 0 2006.285.07:33:20.33#ibcon#flushed, iclass 24, count 0 2006.285.07:33:20.33#ibcon#about to write, iclass 24, count 0 2006.285.07:33:20.33#ibcon#wrote, iclass 24, count 0 2006.285.07:33:20.33#ibcon#about to read 3, iclass 24, count 0 2006.285.07:33:20.35#ibcon#read 3, iclass 24, count 0 2006.285.07:33:20.35#ibcon#about to read 4, iclass 24, count 0 2006.285.07:33:20.35#ibcon#read 4, iclass 24, count 0 2006.285.07:33:20.35#ibcon#about to read 5, iclass 24, count 0 2006.285.07:33:20.35#ibcon#read 5, iclass 24, count 0 2006.285.07:33:20.35#ibcon#about to read 6, iclass 24, count 0 2006.285.07:33:20.35#ibcon#read 6, iclass 24, count 0 2006.285.07:33:20.35#ibcon#end of sib2, iclass 24, count 0 2006.285.07:33:20.35#ibcon#*mode == 0, iclass 24, count 0 2006.285.07:33:20.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.07:33:20.35#ibcon#[25=USB\r\n] 2006.285.07:33:20.35#ibcon#*before write, iclass 24, count 0 2006.285.07:33:20.35#ibcon#enter sib2, iclass 24, count 0 2006.285.07:33:20.35#ibcon#flushed, iclass 24, count 0 2006.285.07:33:20.35#ibcon#about to write, iclass 24, count 0 2006.285.07:33:20.35#ibcon#wrote, iclass 24, count 0 2006.285.07:33:20.35#ibcon#about to read 3, iclass 24, count 0 2006.285.07:33:20.38#ibcon#read 3, iclass 24, count 0 2006.285.07:33:20.38#ibcon#about to read 4, iclass 24, count 0 2006.285.07:33:20.38#ibcon#read 4, iclass 24, count 0 2006.285.07:33:20.38#ibcon#about to read 5, iclass 24, count 0 2006.285.07:33:20.38#ibcon#read 5, iclass 24, count 0 2006.285.07:33:20.38#ibcon#about to read 6, iclass 24, count 0 2006.285.07:33:20.38#ibcon#read 6, iclass 24, count 0 2006.285.07:33:20.38#ibcon#end of sib2, iclass 24, count 0 2006.285.07:33:20.38#ibcon#*after write, iclass 24, count 0 2006.285.07:33:20.38#ibcon#*before return 0, iclass 24, count 0 2006.285.07:33:20.38#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:33:20.38#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:33:20.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.07:33:20.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.07:33:20.38$vck44/valo=8,884.99 2006.285.07:33:20.38#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.07:33:20.38#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.07:33:20.38#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:20.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:33:20.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:33:20.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:33:20.38#ibcon#enter wrdev, iclass 26, count 0 2006.285.07:33:20.38#ibcon#first serial, iclass 26, count 0 2006.285.07:33:20.38#ibcon#enter sib2, iclass 26, count 0 2006.285.07:33:20.38#ibcon#flushed, iclass 26, count 0 2006.285.07:33:20.38#ibcon#about to write, iclass 26, count 0 2006.285.07:33:20.38#ibcon#wrote, iclass 26, count 0 2006.285.07:33:20.38#ibcon#about to read 3, iclass 26, count 0 2006.285.07:33:20.40#ibcon#read 3, iclass 26, count 0 2006.285.07:33:20.40#ibcon#about to read 4, iclass 26, count 0 2006.285.07:33:20.40#ibcon#read 4, iclass 26, count 0 2006.285.07:33:20.40#ibcon#about to read 5, iclass 26, count 0 2006.285.07:33:20.40#ibcon#read 5, iclass 26, count 0 2006.285.07:33:20.40#ibcon#about to read 6, iclass 26, count 0 2006.285.07:33:20.40#ibcon#read 6, iclass 26, count 0 2006.285.07:33:20.40#ibcon#end of sib2, iclass 26, count 0 2006.285.07:33:20.40#ibcon#*mode == 0, iclass 26, count 0 2006.285.07:33:20.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.07:33:20.40#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:33:20.40#ibcon#*before write, iclass 26, count 0 2006.285.07:33:20.40#ibcon#enter sib2, iclass 26, count 0 2006.285.07:33:20.40#ibcon#flushed, iclass 26, count 0 2006.285.07:33:20.40#ibcon#about to write, iclass 26, count 0 2006.285.07:33:20.40#ibcon#wrote, iclass 26, count 0 2006.285.07:33:20.40#ibcon#about to read 3, iclass 26, count 0 2006.285.07:33:20.44#ibcon#read 3, iclass 26, count 0 2006.285.07:33:20.44#ibcon#about to read 4, iclass 26, count 0 2006.285.07:33:20.44#ibcon#read 4, iclass 26, count 0 2006.285.07:33:20.44#ibcon#about to read 5, iclass 26, count 0 2006.285.07:33:20.44#ibcon#read 5, iclass 26, count 0 2006.285.07:33:20.44#ibcon#about to read 6, iclass 26, count 0 2006.285.07:33:20.44#ibcon#read 6, iclass 26, count 0 2006.285.07:33:20.44#ibcon#end of sib2, iclass 26, count 0 2006.285.07:33:20.44#ibcon#*after write, iclass 26, count 0 2006.285.07:33:20.44#ibcon#*before return 0, iclass 26, count 0 2006.285.07:33:20.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:33:20.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:33:20.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.07:33:20.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.07:33:20.44$vck44/va=8,3 2006.285.07:33:20.44#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.07:33:20.44#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.07:33:20.44#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:20.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:33:20.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:33:20.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:33:20.50#ibcon#enter wrdev, iclass 28, count 2 2006.285.07:33:20.50#ibcon#first serial, iclass 28, count 2 2006.285.07:33:20.50#ibcon#enter sib2, iclass 28, count 2 2006.285.07:33:20.50#ibcon#flushed, iclass 28, count 2 2006.285.07:33:20.50#ibcon#about to write, iclass 28, count 2 2006.285.07:33:20.50#ibcon#wrote, iclass 28, count 2 2006.285.07:33:20.50#ibcon#about to read 3, iclass 28, count 2 2006.285.07:33:20.52#ibcon#read 3, iclass 28, count 2 2006.285.07:33:20.52#ibcon#about to read 4, iclass 28, count 2 2006.285.07:33:20.52#ibcon#read 4, iclass 28, count 2 2006.285.07:33:20.52#ibcon#about to read 5, iclass 28, count 2 2006.285.07:33:20.52#ibcon#read 5, iclass 28, count 2 2006.285.07:33:20.52#ibcon#about to read 6, iclass 28, count 2 2006.285.07:33:20.52#ibcon#read 6, iclass 28, count 2 2006.285.07:33:20.52#ibcon#end of sib2, iclass 28, count 2 2006.285.07:33:20.52#ibcon#*mode == 0, iclass 28, count 2 2006.285.07:33:20.52#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.07:33:20.52#ibcon#[25=AT08-03\r\n] 2006.285.07:33:20.52#ibcon#*before write, iclass 28, count 2 2006.285.07:33:20.52#ibcon#enter sib2, iclass 28, count 2 2006.285.07:33:20.52#ibcon#flushed, iclass 28, count 2 2006.285.07:33:20.52#ibcon#about to write, iclass 28, count 2 2006.285.07:33:20.52#ibcon#wrote, iclass 28, count 2 2006.285.07:33:20.52#ibcon#about to read 3, iclass 28, count 2 2006.285.07:33:20.55#ibcon#read 3, iclass 28, count 2 2006.285.07:33:20.55#ibcon#about to read 4, iclass 28, count 2 2006.285.07:33:20.55#ibcon#read 4, iclass 28, count 2 2006.285.07:33:20.55#ibcon#about to read 5, iclass 28, count 2 2006.285.07:33:20.55#ibcon#read 5, iclass 28, count 2 2006.285.07:33:20.55#ibcon#about to read 6, iclass 28, count 2 2006.285.07:33:20.55#ibcon#read 6, iclass 28, count 2 2006.285.07:33:20.55#ibcon#end of sib2, iclass 28, count 2 2006.285.07:33:20.55#ibcon#*after write, iclass 28, count 2 2006.285.07:33:20.55#ibcon#*before return 0, iclass 28, count 2 2006.285.07:33:20.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:33:20.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:33:20.55#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.07:33:20.55#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:20.55#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:33:20.67#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:33:20.67#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:33:20.67#ibcon#enter wrdev, iclass 28, count 0 2006.285.07:33:20.67#ibcon#first serial, iclass 28, count 0 2006.285.07:33:20.67#ibcon#enter sib2, iclass 28, count 0 2006.285.07:33:20.67#ibcon#flushed, iclass 28, count 0 2006.285.07:33:20.67#ibcon#about to write, iclass 28, count 0 2006.285.07:33:20.67#ibcon#wrote, iclass 28, count 0 2006.285.07:33:20.67#ibcon#about to read 3, iclass 28, count 0 2006.285.07:33:20.69#ibcon#read 3, iclass 28, count 0 2006.285.07:33:20.69#ibcon#about to read 4, iclass 28, count 0 2006.285.07:33:20.69#ibcon#read 4, iclass 28, count 0 2006.285.07:33:20.69#ibcon#about to read 5, iclass 28, count 0 2006.285.07:33:20.69#ibcon#read 5, iclass 28, count 0 2006.285.07:33:20.69#ibcon#about to read 6, iclass 28, count 0 2006.285.07:33:20.69#ibcon#read 6, iclass 28, count 0 2006.285.07:33:20.69#ibcon#end of sib2, iclass 28, count 0 2006.285.07:33:20.69#ibcon#*mode == 0, iclass 28, count 0 2006.285.07:33:20.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.07:33:20.69#ibcon#[25=USB\r\n] 2006.285.07:33:20.69#ibcon#*before write, iclass 28, count 0 2006.285.07:33:20.69#ibcon#enter sib2, iclass 28, count 0 2006.285.07:33:20.69#ibcon#flushed, iclass 28, count 0 2006.285.07:33:20.69#ibcon#about to write, iclass 28, count 0 2006.285.07:33:20.69#ibcon#wrote, iclass 28, count 0 2006.285.07:33:20.69#ibcon#about to read 3, iclass 28, count 0 2006.285.07:33:20.72#ibcon#read 3, iclass 28, count 0 2006.285.07:33:20.72#ibcon#about to read 4, iclass 28, count 0 2006.285.07:33:20.72#ibcon#read 4, iclass 28, count 0 2006.285.07:33:20.72#ibcon#about to read 5, iclass 28, count 0 2006.285.07:33:20.72#ibcon#read 5, iclass 28, count 0 2006.285.07:33:20.72#ibcon#about to read 6, iclass 28, count 0 2006.285.07:33:20.72#ibcon#read 6, iclass 28, count 0 2006.285.07:33:20.72#ibcon#end of sib2, iclass 28, count 0 2006.285.07:33:20.72#ibcon#*after write, iclass 28, count 0 2006.285.07:33:20.72#ibcon#*before return 0, iclass 28, count 0 2006.285.07:33:20.72#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:33:20.72#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:33:20.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.07:33:20.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.07:33:20.72$vck44/vblo=1,629.99 2006.285.07:33:20.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.07:33:20.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.07:33:20.72#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:20.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:33:20.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:33:20.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:33:20.72#ibcon#enter wrdev, iclass 30, count 0 2006.285.07:33:20.72#ibcon#first serial, iclass 30, count 0 2006.285.07:33:20.72#ibcon#enter sib2, iclass 30, count 0 2006.285.07:33:20.72#ibcon#flushed, iclass 30, count 0 2006.285.07:33:20.72#ibcon#about to write, iclass 30, count 0 2006.285.07:33:20.72#ibcon#wrote, iclass 30, count 0 2006.285.07:33:20.72#ibcon#about to read 3, iclass 30, count 0 2006.285.07:33:20.74#ibcon#read 3, iclass 30, count 0 2006.285.07:33:20.74#ibcon#about to read 4, iclass 30, count 0 2006.285.07:33:20.74#ibcon#read 4, iclass 30, count 0 2006.285.07:33:20.74#ibcon#about to read 5, iclass 30, count 0 2006.285.07:33:20.74#ibcon#read 5, iclass 30, count 0 2006.285.07:33:20.74#ibcon#about to read 6, iclass 30, count 0 2006.285.07:33:20.74#ibcon#read 6, iclass 30, count 0 2006.285.07:33:20.74#ibcon#end of sib2, iclass 30, count 0 2006.285.07:33:20.74#ibcon#*mode == 0, iclass 30, count 0 2006.285.07:33:20.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.07:33:20.74#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:33:20.74#ibcon#*before write, iclass 30, count 0 2006.285.07:33:20.74#ibcon#enter sib2, iclass 30, count 0 2006.285.07:33:20.74#ibcon#flushed, iclass 30, count 0 2006.285.07:33:20.74#ibcon#about to write, iclass 30, count 0 2006.285.07:33:20.74#ibcon#wrote, iclass 30, count 0 2006.285.07:33:20.74#ibcon#about to read 3, iclass 30, count 0 2006.285.07:33:20.78#ibcon#read 3, iclass 30, count 0 2006.285.07:33:20.78#ibcon#about to read 4, iclass 30, count 0 2006.285.07:33:20.78#ibcon#read 4, iclass 30, count 0 2006.285.07:33:20.78#ibcon#about to read 5, iclass 30, count 0 2006.285.07:33:20.78#ibcon#read 5, iclass 30, count 0 2006.285.07:33:20.78#ibcon#about to read 6, iclass 30, count 0 2006.285.07:33:20.78#ibcon#read 6, iclass 30, count 0 2006.285.07:33:20.78#ibcon#end of sib2, iclass 30, count 0 2006.285.07:33:20.78#ibcon#*after write, iclass 30, count 0 2006.285.07:33:20.78#ibcon#*before return 0, iclass 30, count 0 2006.285.07:33:20.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:33:20.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:33:20.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.07:33:20.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.07:33:20.78$vck44/vb=1,4 2006.285.07:33:20.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.07:33:20.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.07:33:20.78#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:20.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:33:20.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:33:20.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:33:20.78#ibcon#enter wrdev, iclass 32, count 2 2006.285.07:33:20.78#ibcon#first serial, iclass 32, count 2 2006.285.07:33:20.78#ibcon#enter sib2, iclass 32, count 2 2006.285.07:33:20.78#ibcon#flushed, iclass 32, count 2 2006.285.07:33:20.78#ibcon#about to write, iclass 32, count 2 2006.285.07:33:20.78#ibcon#wrote, iclass 32, count 2 2006.285.07:33:20.78#ibcon#about to read 3, iclass 32, count 2 2006.285.07:33:20.80#ibcon#read 3, iclass 32, count 2 2006.285.07:33:20.80#ibcon#about to read 4, iclass 32, count 2 2006.285.07:33:20.80#ibcon#read 4, iclass 32, count 2 2006.285.07:33:20.80#ibcon#about to read 5, iclass 32, count 2 2006.285.07:33:20.80#ibcon#read 5, iclass 32, count 2 2006.285.07:33:20.80#ibcon#about to read 6, iclass 32, count 2 2006.285.07:33:20.80#ibcon#read 6, iclass 32, count 2 2006.285.07:33:20.80#ibcon#end of sib2, iclass 32, count 2 2006.285.07:33:20.80#ibcon#*mode == 0, iclass 32, count 2 2006.285.07:33:20.80#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.07:33:20.80#ibcon#[27=AT01-04\r\n] 2006.285.07:33:20.80#ibcon#*before write, iclass 32, count 2 2006.285.07:33:20.80#ibcon#enter sib2, iclass 32, count 2 2006.285.07:33:20.80#ibcon#flushed, iclass 32, count 2 2006.285.07:33:20.80#ibcon#about to write, iclass 32, count 2 2006.285.07:33:20.80#ibcon#wrote, iclass 32, count 2 2006.285.07:33:20.80#ibcon#about to read 3, iclass 32, count 2 2006.285.07:33:20.83#ibcon#read 3, iclass 32, count 2 2006.285.07:33:20.83#ibcon#about to read 4, iclass 32, count 2 2006.285.07:33:20.83#ibcon#read 4, iclass 32, count 2 2006.285.07:33:20.83#ibcon#about to read 5, iclass 32, count 2 2006.285.07:33:20.83#ibcon#read 5, iclass 32, count 2 2006.285.07:33:20.83#ibcon#about to read 6, iclass 32, count 2 2006.285.07:33:20.83#ibcon#read 6, iclass 32, count 2 2006.285.07:33:20.83#ibcon#end of sib2, iclass 32, count 2 2006.285.07:33:20.83#ibcon#*after write, iclass 32, count 2 2006.285.07:33:20.83#ibcon#*before return 0, iclass 32, count 2 2006.285.07:33:20.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:33:20.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:33:20.83#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.07:33:20.83#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:20.83#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:33:20.95#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:33:20.95#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:33:20.95#ibcon#enter wrdev, iclass 32, count 0 2006.285.07:33:20.95#ibcon#first serial, iclass 32, count 0 2006.285.07:33:20.95#ibcon#enter sib2, iclass 32, count 0 2006.285.07:33:20.95#ibcon#flushed, iclass 32, count 0 2006.285.07:33:20.95#ibcon#about to write, iclass 32, count 0 2006.285.07:33:20.95#ibcon#wrote, iclass 32, count 0 2006.285.07:33:20.95#ibcon#about to read 3, iclass 32, count 0 2006.285.07:33:20.97#ibcon#read 3, iclass 32, count 0 2006.285.07:33:20.97#ibcon#about to read 4, iclass 32, count 0 2006.285.07:33:20.97#ibcon#read 4, iclass 32, count 0 2006.285.07:33:20.97#ibcon#about to read 5, iclass 32, count 0 2006.285.07:33:20.97#ibcon#read 5, iclass 32, count 0 2006.285.07:33:20.97#ibcon#about to read 6, iclass 32, count 0 2006.285.07:33:20.97#ibcon#read 6, iclass 32, count 0 2006.285.07:33:20.97#ibcon#end of sib2, iclass 32, count 0 2006.285.07:33:20.97#ibcon#*mode == 0, iclass 32, count 0 2006.285.07:33:20.97#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.07:33:20.97#ibcon#[27=USB\r\n] 2006.285.07:33:20.97#ibcon#*before write, iclass 32, count 0 2006.285.07:33:20.97#ibcon#enter sib2, iclass 32, count 0 2006.285.07:33:20.97#ibcon#flushed, iclass 32, count 0 2006.285.07:33:20.97#ibcon#about to write, iclass 32, count 0 2006.285.07:33:20.97#ibcon#wrote, iclass 32, count 0 2006.285.07:33:20.97#ibcon#about to read 3, iclass 32, count 0 2006.285.07:33:21.00#ibcon#read 3, iclass 32, count 0 2006.285.07:33:21.00#ibcon#about to read 4, iclass 32, count 0 2006.285.07:33:21.00#ibcon#read 4, iclass 32, count 0 2006.285.07:33:21.00#ibcon#about to read 5, iclass 32, count 0 2006.285.07:33:21.00#ibcon#read 5, iclass 32, count 0 2006.285.07:33:21.00#ibcon#about to read 6, iclass 32, count 0 2006.285.07:33:21.00#ibcon#read 6, iclass 32, count 0 2006.285.07:33:21.00#ibcon#end of sib2, iclass 32, count 0 2006.285.07:33:21.00#ibcon#*after write, iclass 32, count 0 2006.285.07:33:21.00#ibcon#*before return 0, iclass 32, count 0 2006.285.07:33:21.00#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:33:21.00#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:33:21.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.07:33:21.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.07:33:21.00$vck44/vblo=2,634.99 2006.285.07:33:21.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.07:33:21.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.07:33:21.00#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:21.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:33:21.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:33:21.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:33:21.00#ibcon#enter wrdev, iclass 34, count 0 2006.285.07:33:21.00#ibcon#first serial, iclass 34, count 0 2006.285.07:33:21.00#ibcon#enter sib2, iclass 34, count 0 2006.285.07:33:21.00#ibcon#flushed, iclass 34, count 0 2006.285.07:33:21.00#ibcon#about to write, iclass 34, count 0 2006.285.07:33:21.00#ibcon#wrote, iclass 34, count 0 2006.285.07:33:21.00#ibcon#about to read 3, iclass 34, count 0 2006.285.07:33:21.02#ibcon#read 3, iclass 34, count 0 2006.285.07:33:21.02#ibcon#about to read 4, iclass 34, count 0 2006.285.07:33:21.02#ibcon#read 4, iclass 34, count 0 2006.285.07:33:21.02#ibcon#about to read 5, iclass 34, count 0 2006.285.07:33:21.02#ibcon#read 5, iclass 34, count 0 2006.285.07:33:21.02#ibcon#about to read 6, iclass 34, count 0 2006.285.07:33:21.02#ibcon#read 6, iclass 34, count 0 2006.285.07:33:21.02#ibcon#end of sib2, iclass 34, count 0 2006.285.07:33:21.02#ibcon#*mode == 0, iclass 34, count 0 2006.285.07:33:21.02#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.07:33:21.02#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:33:21.02#ibcon#*before write, iclass 34, count 0 2006.285.07:33:21.02#ibcon#enter sib2, iclass 34, count 0 2006.285.07:33:21.02#ibcon#flushed, iclass 34, count 0 2006.285.07:33:21.02#ibcon#about to write, iclass 34, count 0 2006.285.07:33:21.02#ibcon#wrote, iclass 34, count 0 2006.285.07:33:21.02#ibcon#about to read 3, iclass 34, count 0 2006.285.07:33:21.06#ibcon#read 3, iclass 34, count 0 2006.285.07:33:21.06#ibcon#about to read 4, iclass 34, count 0 2006.285.07:33:21.06#ibcon#read 4, iclass 34, count 0 2006.285.07:33:21.06#ibcon#about to read 5, iclass 34, count 0 2006.285.07:33:21.06#ibcon#read 5, iclass 34, count 0 2006.285.07:33:21.06#ibcon#about to read 6, iclass 34, count 0 2006.285.07:33:21.06#ibcon#read 6, iclass 34, count 0 2006.285.07:33:21.06#ibcon#end of sib2, iclass 34, count 0 2006.285.07:33:21.06#ibcon#*after write, iclass 34, count 0 2006.285.07:33:21.06#ibcon#*before return 0, iclass 34, count 0 2006.285.07:33:21.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:33:21.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:33:21.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.07:33:21.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.07:33:21.06$vck44/vb=2,5 2006.285.07:33:21.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.07:33:21.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.07:33:21.06#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:21.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:33:21.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:33:21.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:33:21.12#ibcon#enter wrdev, iclass 36, count 2 2006.285.07:33:21.12#ibcon#first serial, iclass 36, count 2 2006.285.07:33:21.12#ibcon#enter sib2, iclass 36, count 2 2006.285.07:33:21.12#ibcon#flushed, iclass 36, count 2 2006.285.07:33:21.12#ibcon#about to write, iclass 36, count 2 2006.285.07:33:21.12#ibcon#wrote, iclass 36, count 2 2006.285.07:33:21.12#ibcon#about to read 3, iclass 36, count 2 2006.285.07:33:21.14#ibcon#read 3, iclass 36, count 2 2006.285.07:33:21.14#ibcon#about to read 4, iclass 36, count 2 2006.285.07:33:21.14#ibcon#read 4, iclass 36, count 2 2006.285.07:33:21.14#ibcon#about to read 5, iclass 36, count 2 2006.285.07:33:21.14#ibcon#read 5, iclass 36, count 2 2006.285.07:33:21.14#ibcon#about to read 6, iclass 36, count 2 2006.285.07:33:21.14#ibcon#read 6, iclass 36, count 2 2006.285.07:33:21.14#ibcon#end of sib2, iclass 36, count 2 2006.285.07:33:21.14#ibcon#*mode == 0, iclass 36, count 2 2006.285.07:33:21.14#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.07:33:21.14#ibcon#[27=AT02-05\r\n] 2006.285.07:33:21.14#ibcon#*before write, iclass 36, count 2 2006.285.07:33:21.14#ibcon#enter sib2, iclass 36, count 2 2006.285.07:33:21.14#ibcon#flushed, iclass 36, count 2 2006.285.07:33:21.14#ibcon#about to write, iclass 36, count 2 2006.285.07:33:21.14#ibcon#wrote, iclass 36, count 2 2006.285.07:33:21.14#ibcon#about to read 3, iclass 36, count 2 2006.285.07:33:21.17#ibcon#read 3, iclass 36, count 2 2006.285.07:33:21.17#ibcon#about to read 4, iclass 36, count 2 2006.285.07:33:21.17#ibcon#read 4, iclass 36, count 2 2006.285.07:33:21.17#ibcon#about to read 5, iclass 36, count 2 2006.285.07:33:21.17#ibcon#read 5, iclass 36, count 2 2006.285.07:33:21.17#ibcon#about to read 6, iclass 36, count 2 2006.285.07:33:21.17#ibcon#read 6, iclass 36, count 2 2006.285.07:33:21.17#ibcon#end of sib2, iclass 36, count 2 2006.285.07:33:21.17#ibcon#*after write, iclass 36, count 2 2006.285.07:33:21.17#ibcon#*before return 0, iclass 36, count 2 2006.285.07:33:21.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:33:21.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:33:21.17#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.07:33:21.17#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:21.17#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:33:21.29#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:33:21.29#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:33:21.29#ibcon#enter wrdev, iclass 36, count 0 2006.285.07:33:21.29#ibcon#first serial, iclass 36, count 0 2006.285.07:33:21.29#ibcon#enter sib2, iclass 36, count 0 2006.285.07:33:21.29#ibcon#flushed, iclass 36, count 0 2006.285.07:33:21.29#ibcon#about to write, iclass 36, count 0 2006.285.07:33:21.29#ibcon#wrote, iclass 36, count 0 2006.285.07:33:21.29#ibcon#about to read 3, iclass 36, count 0 2006.285.07:33:21.31#ibcon#read 3, iclass 36, count 0 2006.285.07:33:21.31#ibcon#about to read 4, iclass 36, count 0 2006.285.07:33:21.31#ibcon#read 4, iclass 36, count 0 2006.285.07:33:21.31#ibcon#about to read 5, iclass 36, count 0 2006.285.07:33:21.31#ibcon#read 5, iclass 36, count 0 2006.285.07:33:21.31#ibcon#about to read 6, iclass 36, count 0 2006.285.07:33:21.31#ibcon#read 6, iclass 36, count 0 2006.285.07:33:21.31#ibcon#end of sib2, iclass 36, count 0 2006.285.07:33:21.31#ibcon#*mode == 0, iclass 36, count 0 2006.285.07:33:21.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.07:33:21.31#ibcon#[27=USB\r\n] 2006.285.07:33:21.31#ibcon#*before write, iclass 36, count 0 2006.285.07:33:21.31#ibcon#enter sib2, iclass 36, count 0 2006.285.07:33:21.31#ibcon#flushed, iclass 36, count 0 2006.285.07:33:21.31#ibcon#about to write, iclass 36, count 0 2006.285.07:33:21.31#ibcon#wrote, iclass 36, count 0 2006.285.07:33:21.31#ibcon#about to read 3, iclass 36, count 0 2006.285.07:33:21.34#ibcon#read 3, iclass 36, count 0 2006.285.07:33:21.34#ibcon#about to read 4, iclass 36, count 0 2006.285.07:33:21.34#ibcon#read 4, iclass 36, count 0 2006.285.07:33:21.34#ibcon#about to read 5, iclass 36, count 0 2006.285.07:33:21.34#ibcon#read 5, iclass 36, count 0 2006.285.07:33:21.34#ibcon#about to read 6, iclass 36, count 0 2006.285.07:33:21.34#ibcon#read 6, iclass 36, count 0 2006.285.07:33:21.34#ibcon#end of sib2, iclass 36, count 0 2006.285.07:33:21.34#ibcon#*after write, iclass 36, count 0 2006.285.07:33:21.34#ibcon#*before return 0, iclass 36, count 0 2006.285.07:33:21.34#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:33:21.34#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:33:21.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.07:33:21.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.07:33:21.34$vck44/vblo=3,649.99 2006.285.07:33:21.34#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.07:33:21.34#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.07:33:21.34#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:21.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:33:21.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:33:21.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:33:21.34#ibcon#enter wrdev, iclass 38, count 0 2006.285.07:33:21.34#ibcon#first serial, iclass 38, count 0 2006.285.07:33:21.34#ibcon#enter sib2, iclass 38, count 0 2006.285.07:33:21.34#ibcon#flushed, iclass 38, count 0 2006.285.07:33:21.34#ibcon#about to write, iclass 38, count 0 2006.285.07:33:21.34#ibcon#wrote, iclass 38, count 0 2006.285.07:33:21.34#ibcon#about to read 3, iclass 38, count 0 2006.285.07:33:21.36#ibcon#read 3, iclass 38, count 0 2006.285.07:33:21.36#ibcon#about to read 4, iclass 38, count 0 2006.285.07:33:21.36#ibcon#read 4, iclass 38, count 0 2006.285.07:33:21.36#ibcon#about to read 5, iclass 38, count 0 2006.285.07:33:21.36#ibcon#read 5, iclass 38, count 0 2006.285.07:33:21.36#ibcon#about to read 6, iclass 38, count 0 2006.285.07:33:21.36#ibcon#read 6, iclass 38, count 0 2006.285.07:33:21.36#ibcon#end of sib2, iclass 38, count 0 2006.285.07:33:21.36#ibcon#*mode == 0, iclass 38, count 0 2006.285.07:33:21.36#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.07:33:21.36#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:33:21.36#ibcon#*before write, iclass 38, count 0 2006.285.07:33:21.36#ibcon#enter sib2, iclass 38, count 0 2006.285.07:33:21.36#ibcon#flushed, iclass 38, count 0 2006.285.07:33:21.36#ibcon#about to write, iclass 38, count 0 2006.285.07:33:21.36#ibcon#wrote, iclass 38, count 0 2006.285.07:33:21.36#ibcon#about to read 3, iclass 38, count 0 2006.285.07:33:21.40#ibcon#read 3, iclass 38, count 0 2006.285.07:33:21.40#ibcon#about to read 4, iclass 38, count 0 2006.285.07:33:21.40#ibcon#read 4, iclass 38, count 0 2006.285.07:33:21.40#ibcon#about to read 5, iclass 38, count 0 2006.285.07:33:21.40#ibcon#read 5, iclass 38, count 0 2006.285.07:33:21.40#ibcon#about to read 6, iclass 38, count 0 2006.285.07:33:21.40#ibcon#read 6, iclass 38, count 0 2006.285.07:33:21.40#ibcon#end of sib2, iclass 38, count 0 2006.285.07:33:21.40#ibcon#*after write, iclass 38, count 0 2006.285.07:33:21.40#ibcon#*before return 0, iclass 38, count 0 2006.285.07:33:21.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:33:21.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:33:21.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.07:33:21.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.07:33:21.40$vck44/vb=3,4 2006.285.07:33:21.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.07:33:21.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.07:33:21.40#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:21.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:33:21.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:33:21.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:33:21.46#ibcon#enter wrdev, iclass 40, count 2 2006.285.07:33:21.46#ibcon#first serial, iclass 40, count 2 2006.285.07:33:21.46#ibcon#enter sib2, iclass 40, count 2 2006.285.07:33:21.46#ibcon#flushed, iclass 40, count 2 2006.285.07:33:21.46#ibcon#about to write, iclass 40, count 2 2006.285.07:33:21.46#ibcon#wrote, iclass 40, count 2 2006.285.07:33:21.46#ibcon#about to read 3, iclass 40, count 2 2006.285.07:33:21.48#ibcon#read 3, iclass 40, count 2 2006.285.07:33:21.48#ibcon#about to read 4, iclass 40, count 2 2006.285.07:33:21.48#ibcon#read 4, iclass 40, count 2 2006.285.07:33:21.48#ibcon#about to read 5, iclass 40, count 2 2006.285.07:33:21.48#ibcon#read 5, iclass 40, count 2 2006.285.07:33:21.48#ibcon#about to read 6, iclass 40, count 2 2006.285.07:33:21.48#ibcon#read 6, iclass 40, count 2 2006.285.07:33:21.48#ibcon#end of sib2, iclass 40, count 2 2006.285.07:33:21.48#ibcon#*mode == 0, iclass 40, count 2 2006.285.07:33:21.48#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.07:33:21.48#ibcon#[27=AT03-04\r\n] 2006.285.07:33:21.48#ibcon#*before write, iclass 40, count 2 2006.285.07:33:21.48#ibcon#enter sib2, iclass 40, count 2 2006.285.07:33:21.48#ibcon#flushed, iclass 40, count 2 2006.285.07:33:21.48#ibcon#about to write, iclass 40, count 2 2006.285.07:33:21.48#ibcon#wrote, iclass 40, count 2 2006.285.07:33:21.48#ibcon#about to read 3, iclass 40, count 2 2006.285.07:33:21.51#ibcon#read 3, iclass 40, count 2 2006.285.07:33:21.51#ibcon#about to read 4, iclass 40, count 2 2006.285.07:33:21.51#ibcon#read 4, iclass 40, count 2 2006.285.07:33:21.51#ibcon#about to read 5, iclass 40, count 2 2006.285.07:33:21.51#ibcon#read 5, iclass 40, count 2 2006.285.07:33:21.51#ibcon#about to read 6, iclass 40, count 2 2006.285.07:33:21.51#ibcon#read 6, iclass 40, count 2 2006.285.07:33:21.51#ibcon#end of sib2, iclass 40, count 2 2006.285.07:33:21.51#ibcon#*after write, iclass 40, count 2 2006.285.07:33:21.51#ibcon#*before return 0, iclass 40, count 2 2006.285.07:33:21.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:33:21.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:33:21.51#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.07:33:21.51#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:21.51#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:33:21.63#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:33:21.63#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:33:21.63#ibcon#enter wrdev, iclass 40, count 0 2006.285.07:33:21.63#ibcon#first serial, iclass 40, count 0 2006.285.07:33:21.63#ibcon#enter sib2, iclass 40, count 0 2006.285.07:33:21.63#ibcon#flushed, iclass 40, count 0 2006.285.07:33:21.63#ibcon#about to write, iclass 40, count 0 2006.285.07:33:21.63#ibcon#wrote, iclass 40, count 0 2006.285.07:33:21.63#ibcon#about to read 3, iclass 40, count 0 2006.285.07:33:21.65#ibcon#read 3, iclass 40, count 0 2006.285.07:33:21.65#ibcon#about to read 4, iclass 40, count 0 2006.285.07:33:21.65#ibcon#read 4, iclass 40, count 0 2006.285.07:33:21.65#ibcon#about to read 5, iclass 40, count 0 2006.285.07:33:21.65#ibcon#read 5, iclass 40, count 0 2006.285.07:33:21.65#ibcon#about to read 6, iclass 40, count 0 2006.285.07:33:21.65#ibcon#read 6, iclass 40, count 0 2006.285.07:33:21.65#ibcon#end of sib2, iclass 40, count 0 2006.285.07:33:21.65#ibcon#*mode == 0, iclass 40, count 0 2006.285.07:33:21.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.07:33:21.65#ibcon#[27=USB\r\n] 2006.285.07:33:21.65#ibcon#*before write, iclass 40, count 0 2006.285.07:33:21.65#ibcon#enter sib2, iclass 40, count 0 2006.285.07:33:21.65#ibcon#flushed, iclass 40, count 0 2006.285.07:33:21.65#ibcon#about to write, iclass 40, count 0 2006.285.07:33:21.65#ibcon#wrote, iclass 40, count 0 2006.285.07:33:21.65#ibcon#about to read 3, iclass 40, count 0 2006.285.07:33:21.68#ibcon#read 3, iclass 40, count 0 2006.285.07:33:21.68#ibcon#about to read 4, iclass 40, count 0 2006.285.07:33:21.68#ibcon#read 4, iclass 40, count 0 2006.285.07:33:21.68#ibcon#about to read 5, iclass 40, count 0 2006.285.07:33:21.68#ibcon#read 5, iclass 40, count 0 2006.285.07:33:21.68#ibcon#about to read 6, iclass 40, count 0 2006.285.07:33:21.68#ibcon#read 6, iclass 40, count 0 2006.285.07:33:21.68#ibcon#end of sib2, iclass 40, count 0 2006.285.07:33:21.68#ibcon#*after write, iclass 40, count 0 2006.285.07:33:21.68#ibcon#*before return 0, iclass 40, count 0 2006.285.07:33:21.68#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:33:21.68#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:33:21.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.07:33:21.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.07:33:21.68$vck44/vblo=4,679.99 2006.285.07:33:21.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.07:33:21.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.07:33:21.68#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:21.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:33:21.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:33:21.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:33:21.68#ibcon#enter wrdev, iclass 4, count 0 2006.285.07:33:21.68#ibcon#first serial, iclass 4, count 0 2006.285.07:33:21.68#ibcon#enter sib2, iclass 4, count 0 2006.285.07:33:21.68#ibcon#flushed, iclass 4, count 0 2006.285.07:33:21.68#ibcon#about to write, iclass 4, count 0 2006.285.07:33:21.68#ibcon#wrote, iclass 4, count 0 2006.285.07:33:21.68#ibcon#about to read 3, iclass 4, count 0 2006.285.07:33:21.70#ibcon#read 3, iclass 4, count 0 2006.285.07:33:21.70#ibcon#about to read 4, iclass 4, count 0 2006.285.07:33:21.70#ibcon#read 4, iclass 4, count 0 2006.285.07:33:21.70#ibcon#about to read 5, iclass 4, count 0 2006.285.07:33:21.70#ibcon#read 5, iclass 4, count 0 2006.285.07:33:21.70#ibcon#about to read 6, iclass 4, count 0 2006.285.07:33:21.70#ibcon#read 6, iclass 4, count 0 2006.285.07:33:21.70#ibcon#end of sib2, iclass 4, count 0 2006.285.07:33:21.70#ibcon#*mode == 0, iclass 4, count 0 2006.285.07:33:21.70#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.07:33:21.70#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:33:21.70#ibcon#*before write, iclass 4, count 0 2006.285.07:33:21.70#ibcon#enter sib2, iclass 4, count 0 2006.285.07:33:21.70#ibcon#flushed, iclass 4, count 0 2006.285.07:33:21.70#ibcon#about to write, iclass 4, count 0 2006.285.07:33:21.70#ibcon#wrote, iclass 4, count 0 2006.285.07:33:21.70#ibcon#about to read 3, iclass 4, count 0 2006.285.07:33:21.74#ibcon#read 3, iclass 4, count 0 2006.285.07:33:21.74#ibcon#about to read 4, iclass 4, count 0 2006.285.07:33:21.74#ibcon#read 4, iclass 4, count 0 2006.285.07:33:21.74#ibcon#about to read 5, iclass 4, count 0 2006.285.07:33:21.74#ibcon#read 5, iclass 4, count 0 2006.285.07:33:21.74#ibcon#about to read 6, iclass 4, count 0 2006.285.07:33:21.74#ibcon#read 6, iclass 4, count 0 2006.285.07:33:21.74#ibcon#end of sib2, iclass 4, count 0 2006.285.07:33:21.74#ibcon#*after write, iclass 4, count 0 2006.285.07:33:21.74#ibcon#*before return 0, iclass 4, count 0 2006.285.07:33:21.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:33:21.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:33:21.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.07:33:21.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.07:33:21.74$vck44/vb=4,5 2006.285.07:33:21.74#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.07:33:21.74#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.07:33:21.74#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:21.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:33:21.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:33:21.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:33:21.80#ibcon#enter wrdev, iclass 6, count 2 2006.285.07:33:21.80#ibcon#first serial, iclass 6, count 2 2006.285.07:33:21.80#ibcon#enter sib2, iclass 6, count 2 2006.285.07:33:21.80#ibcon#flushed, iclass 6, count 2 2006.285.07:33:21.80#ibcon#about to write, iclass 6, count 2 2006.285.07:33:21.80#ibcon#wrote, iclass 6, count 2 2006.285.07:33:21.80#ibcon#about to read 3, iclass 6, count 2 2006.285.07:33:21.82#ibcon#read 3, iclass 6, count 2 2006.285.07:33:21.82#ibcon#about to read 4, iclass 6, count 2 2006.285.07:33:21.82#ibcon#read 4, iclass 6, count 2 2006.285.07:33:21.82#ibcon#about to read 5, iclass 6, count 2 2006.285.07:33:21.82#ibcon#read 5, iclass 6, count 2 2006.285.07:33:21.82#ibcon#about to read 6, iclass 6, count 2 2006.285.07:33:21.82#ibcon#read 6, iclass 6, count 2 2006.285.07:33:21.82#ibcon#end of sib2, iclass 6, count 2 2006.285.07:33:21.82#ibcon#*mode == 0, iclass 6, count 2 2006.285.07:33:21.82#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.07:33:21.82#ibcon#[27=AT04-05\r\n] 2006.285.07:33:21.82#ibcon#*before write, iclass 6, count 2 2006.285.07:33:21.82#ibcon#enter sib2, iclass 6, count 2 2006.285.07:33:21.82#ibcon#flushed, iclass 6, count 2 2006.285.07:33:21.82#ibcon#about to write, iclass 6, count 2 2006.285.07:33:21.82#ibcon#wrote, iclass 6, count 2 2006.285.07:33:21.82#ibcon#about to read 3, iclass 6, count 2 2006.285.07:33:21.85#ibcon#read 3, iclass 6, count 2 2006.285.07:33:21.85#ibcon#about to read 4, iclass 6, count 2 2006.285.07:33:21.85#ibcon#read 4, iclass 6, count 2 2006.285.07:33:21.85#ibcon#about to read 5, iclass 6, count 2 2006.285.07:33:21.85#ibcon#read 5, iclass 6, count 2 2006.285.07:33:21.85#ibcon#about to read 6, iclass 6, count 2 2006.285.07:33:21.85#ibcon#read 6, iclass 6, count 2 2006.285.07:33:21.85#ibcon#end of sib2, iclass 6, count 2 2006.285.07:33:21.85#ibcon#*after write, iclass 6, count 2 2006.285.07:33:21.85#ibcon#*before return 0, iclass 6, count 2 2006.285.07:33:21.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:33:21.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:33:21.85#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.07:33:21.85#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:21.85#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:33:21.97#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:33:21.97#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:33:21.97#ibcon#enter wrdev, iclass 6, count 0 2006.285.07:33:21.97#ibcon#first serial, iclass 6, count 0 2006.285.07:33:21.97#ibcon#enter sib2, iclass 6, count 0 2006.285.07:33:21.97#ibcon#flushed, iclass 6, count 0 2006.285.07:33:21.97#ibcon#about to write, iclass 6, count 0 2006.285.07:33:21.97#ibcon#wrote, iclass 6, count 0 2006.285.07:33:21.97#ibcon#about to read 3, iclass 6, count 0 2006.285.07:33:21.99#ibcon#read 3, iclass 6, count 0 2006.285.07:33:21.99#ibcon#about to read 4, iclass 6, count 0 2006.285.07:33:21.99#ibcon#read 4, iclass 6, count 0 2006.285.07:33:21.99#ibcon#about to read 5, iclass 6, count 0 2006.285.07:33:21.99#ibcon#read 5, iclass 6, count 0 2006.285.07:33:21.99#ibcon#about to read 6, iclass 6, count 0 2006.285.07:33:21.99#ibcon#read 6, iclass 6, count 0 2006.285.07:33:21.99#ibcon#end of sib2, iclass 6, count 0 2006.285.07:33:21.99#ibcon#*mode == 0, iclass 6, count 0 2006.285.07:33:21.99#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.07:33:21.99#ibcon#[27=USB\r\n] 2006.285.07:33:21.99#ibcon#*before write, iclass 6, count 0 2006.285.07:33:21.99#ibcon#enter sib2, iclass 6, count 0 2006.285.07:33:21.99#ibcon#flushed, iclass 6, count 0 2006.285.07:33:21.99#ibcon#about to write, iclass 6, count 0 2006.285.07:33:21.99#ibcon#wrote, iclass 6, count 0 2006.285.07:33:21.99#ibcon#about to read 3, iclass 6, count 0 2006.285.07:33:22.02#ibcon#read 3, iclass 6, count 0 2006.285.07:33:22.02#ibcon#about to read 4, iclass 6, count 0 2006.285.07:33:22.02#ibcon#read 4, iclass 6, count 0 2006.285.07:33:22.02#ibcon#about to read 5, iclass 6, count 0 2006.285.07:33:22.02#ibcon#read 5, iclass 6, count 0 2006.285.07:33:22.02#ibcon#about to read 6, iclass 6, count 0 2006.285.07:33:22.02#ibcon#read 6, iclass 6, count 0 2006.285.07:33:22.02#ibcon#end of sib2, iclass 6, count 0 2006.285.07:33:22.02#ibcon#*after write, iclass 6, count 0 2006.285.07:33:22.02#ibcon#*before return 0, iclass 6, count 0 2006.285.07:33:22.02#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:33:22.02#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:33:22.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.07:33:22.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.07:33:22.02$vck44/vblo=5,709.99 2006.285.07:33:22.02#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.07:33:22.02#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.07:33:22.02#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:22.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:33:22.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:33:22.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:33:22.02#ibcon#enter wrdev, iclass 10, count 0 2006.285.07:33:22.02#ibcon#first serial, iclass 10, count 0 2006.285.07:33:22.02#ibcon#enter sib2, iclass 10, count 0 2006.285.07:33:22.02#ibcon#flushed, iclass 10, count 0 2006.285.07:33:22.02#ibcon#about to write, iclass 10, count 0 2006.285.07:33:22.02#ibcon#wrote, iclass 10, count 0 2006.285.07:33:22.02#ibcon#about to read 3, iclass 10, count 0 2006.285.07:33:22.04#ibcon#read 3, iclass 10, count 0 2006.285.07:33:22.04#ibcon#about to read 4, iclass 10, count 0 2006.285.07:33:22.04#ibcon#read 4, iclass 10, count 0 2006.285.07:33:22.04#ibcon#about to read 5, iclass 10, count 0 2006.285.07:33:22.04#ibcon#read 5, iclass 10, count 0 2006.285.07:33:22.04#ibcon#about to read 6, iclass 10, count 0 2006.285.07:33:22.04#ibcon#read 6, iclass 10, count 0 2006.285.07:33:22.04#ibcon#end of sib2, iclass 10, count 0 2006.285.07:33:22.04#ibcon#*mode == 0, iclass 10, count 0 2006.285.07:33:22.04#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.07:33:22.04#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:33:22.04#ibcon#*before write, iclass 10, count 0 2006.285.07:33:22.04#ibcon#enter sib2, iclass 10, count 0 2006.285.07:33:22.04#ibcon#flushed, iclass 10, count 0 2006.285.07:33:22.04#ibcon#about to write, iclass 10, count 0 2006.285.07:33:22.04#ibcon#wrote, iclass 10, count 0 2006.285.07:33:22.04#ibcon#about to read 3, iclass 10, count 0 2006.285.07:33:22.08#ibcon#read 3, iclass 10, count 0 2006.285.07:33:22.08#ibcon#about to read 4, iclass 10, count 0 2006.285.07:33:22.08#ibcon#read 4, iclass 10, count 0 2006.285.07:33:22.08#ibcon#about to read 5, iclass 10, count 0 2006.285.07:33:22.08#ibcon#read 5, iclass 10, count 0 2006.285.07:33:22.08#ibcon#about to read 6, iclass 10, count 0 2006.285.07:33:22.08#ibcon#read 6, iclass 10, count 0 2006.285.07:33:22.08#ibcon#end of sib2, iclass 10, count 0 2006.285.07:33:22.08#ibcon#*after write, iclass 10, count 0 2006.285.07:33:22.08#ibcon#*before return 0, iclass 10, count 0 2006.285.07:33:22.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:33:22.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:33:22.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.07:33:22.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.07:33:22.08$vck44/vb=5,4 2006.285.07:33:22.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.07:33:22.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.07:33:22.08#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:22.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:33:22.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:33:22.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:33:22.14#ibcon#enter wrdev, iclass 12, count 2 2006.285.07:33:22.14#ibcon#first serial, iclass 12, count 2 2006.285.07:33:22.14#ibcon#enter sib2, iclass 12, count 2 2006.285.07:33:22.14#ibcon#flushed, iclass 12, count 2 2006.285.07:33:22.14#ibcon#about to write, iclass 12, count 2 2006.285.07:33:22.14#ibcon#wrote, iclass 12, count 2 2006.285.07:33:22.14#ibcon#about to read 3, iclass 12, count 2 2006.285.07:33:22.16#ibcon#read 3, iclass 12, count 2 2006.285.07:33:22.16#ibcon#about to read 4, iclass 12, count 2 2006.285.07:33:22.16#ibcon#read 4, iclass 12, count 2 2006.285.07:33:22.16#ibcon#about to read 5, iclass 12, count 2 2006.285.07:33:22.16#ibcon#read 5, iclass 12, count 2 2006.285.07:33:22.16#ibcon#about to read 6, iclass 12, count 2 2006.285.07:33:22.16#ibcon#read 6, iclass 12, count 2 2006.285.07:33:22.16#ibcon#end of sib2, iclass 12, count 2 2006.285.07:33:22.16#ibcon#*mode == 0, iclass 12, count 2 2006.285.07:33:22.16#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.07:33:22.16#ibcon#[27=AT05-04\r\n] 2006.285.07:33:22.16#ibcon#*before write, iclass 12, count 2 2006.285.07:33:22.16#ibcon#enter sib2, iclass 12, count 2 2006.285.07:33:22.16#ibcon#flushed, iclass 12, count 2 2006.285.07:33:22.16#ibcon#about to write, iclass 12, count 2 2006.285.07:33:22.16#ibcon#wrote, iclass 12, count 2 2006.285.07:33:22.16#ibcon#about to read 3, iclass 12, count 2 2006.285.07:33:22.19#ibcon#read 3, iclass 12, count 2 2006.285.07:33:22.19#ibcon#about to read 4, iclass 12, count 2 2006.285.07:33:22.19#ibcon#read 4, iclass 12, count 2 2006.285.07:33:22.19#ibcon#about to read 5, iclass 12, count 2 2006.285.07:33:22.19#ibcon#read 5, iclass 12, count 2 2006.285.07:33:22.19#ibcon#about to read 6, iclass 12, count 2 2006.285.07:33:22.19#ibcon#read 6, iclass 12, count 2 2006.285.07:33:22.19#ibcon#end of sib2, iclass 12, count 2 2006.285.07:33:22.19#ibcon#*after write, iclass 12, count 2 2006.285.07:33:22.19#ibcon#*before return 0, iclass 12, count 2 2006.285.07:33:22.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:33:22.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:33:22.19#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.07:33:22.19#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:22.19#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:33:22.31#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:33:22.31#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:33:22.31#ibcon#enter wrdev, iclass 12, count 0 2006.285.07:33:22.31#ibcon#first serial, iclass 12, count 0 2006.285.07:33:22.31#ibcon#enter sib2, iclass 12, count 0 2006.285.07:33:22.31#ibcon#flushed, iclass 12, count 0 2006.285.07:33:22.31#ibcon#about to write, iclass 12, count 0 2006.285.07:33:22.31#ibcon#wrote, iclass 12, count 0 2006.285.07:33:22.31#ibcon#about to read 3, iclass 12, count 0 2006.285.07:33:22.33#ibcon#read 3, iclass 12, count 0 2006.285.07:33:22.33#ibcon#about to read 4, iclass 12, count 0 2006.285.07:33:22.33#ibcon#read 4, iclass 12, count 0 2006.285.07:33:22.33#ibcon#about to read 5, iclass 12, count 0 2006.285.07:33:22.33#ibcon#read 5, iclass 12, count 0 2006.285.07:33:22.33#ibcon#about to read 6, iclass 12, count 0 2006.285.07:33:22.33#ibcon#read 6, iclass 12, count 0 2006.285.07:33:22.33#ibcon#end of sib2, iclass 12, count 0 2006.285.07:33:22.33#ibcon#*mode == 0, iclass 12, count 0 2006.285.07:33:22.33#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.07:33:22.33#ibcon#[27=USB\r\n] 2006.285.07:33:22.33#ibcon#*before write, iclass 12, count 0 2006.285.07:33:22.33#ibcon#enter sib2, iclass 12, count 0 2006.285.07:33:22.33#ibcon#flushed, iclass 12, count 0 2006.285.07:33:22.33#ibcon#about to write, iclass 12, count 0 2006.285.07:33:22.33#ibcon#wrote, iclass 12, count 0 2006.285.07:33:22.33#ibcon#about to read 3, iclass 12, count 0 2006.285.07:33:22.36#ibcon#read 3, iclass 12, count 0 2006.285.07:33:22.36#ibcon#about to read 4, iclass 12, count 0 2006.285.07:33:22.36#ibcon#read 4, iclass 12, count 0 2006.285.07:33:22.36#ibcon#about to read 5, iclass 12, count 0 2006.285.07:33:22.36#ibcon#read 5, iclass 12, count 0 2006.285.07:33:22.36#ibcon#about to read 6, iclass 12, count 0 2006.285.07:33:22.36#ibcon#read 6, iclass 12, count 0 2006.285.07:33:22.36#ibcon#end of sib2, iclass 12, count 0 2006.285.07:33:22.36#ibcon#*after write, iclass 12, count 0 2006.285.07:33:22.36#ibcon#*before return 0, iclass 12, count 0 2006.285.07:33:22.36#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:33:22.36#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:33:22.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.07:33:22.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.07:33:22.36$vck44/vblo=6,719.99 2006.285.07:33:22.36#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.07:33:22.36#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.07:33:22.36#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:22.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:33:22.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:33:22.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:33:22.36#ibcon#enter wrdev, iclass 14, count 0 2006.285.07:33:22.36#ibcon#first serial, iclass 14, count 0 2006.285.07:33:22.36#ibcon#enter sib2, iclass 14, count 0 2006.285.07:33:22.36#ibcon#flushed, iclass 14, count 0 2006.285.07:33:22.36#ibcon#about to write, iclass 14, count 0 2006.285.07:33:22.36#ibcon#wrote, iclass 14, count 0 2006.285.07:33:22.36#ibcon#about to read 3, iclass 14, count 0 2006.285.07:33:22.38#ibcon#read 3, iclass 14, count 0 2006.285.07:33:22.38#ibcon#about to read 4, iclass 14, count 0 2006.285.07:33:22.38#ibcon#read 4, iclass 14, count 0 2006.285.07:33:22.38#ibcon#about to read 5, iclass 14, count 0 2006.285.07:33:22.38#ibcon#read 5, iclass 14, count 0 2006.285.07:33:22.38#ibcon#about to read 6, iclass 14, count 0 2006.285.07:33:22.38#ibcon#read 6, iclass 14, count 0 2006.285.07:33:22.38#ibcon#end of sib2, iclass 14, count 0 2006.285.07:33:22.38#ibcon#*mode == 0, iclass 14, count 0 2006.285.07:33:22.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.07:33:22.38#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:33:22.38#ibcon#*before write, iclass 14, count 0 2006.285.07:33:22.38#ibcon#enter sib2, iclass 14, count 0 2006.285.07:33:22.38#ibcon#flushed, iclass 14, count 0 2006.285.07:33:22.38#ibcon#about to write, iclass 14, count 0 2006.285.07:33:22.38#ibcon#wrote, iclass 14, count 0 2006.285.07:33:22.38#ibcon#about to read 3, iclass 14, count 0 2006.285.07:33:22.42#ibcon#read 3, iclass 14, count 0 2006.285.07:33:22.42#ibcon#about to read 4, iclass 14, count 0 2006.285.07:33:22.42#ibcon#read 4, iclass 14, count 0 2006.285.07:33:22.42#ibcon#about to read 5, iclass 14, count 0 2006.285.07:33:22.42#ibcon#read 5, iclass 14, count 0 2006.285.07:33:22.42#ibcon#about to read 6, iclass 14, count 0 2006.285.07:33:22.42#ibcon#read 6, iclass 14, count 0 2006.285.07:33:22.42#ibcon#end of sib2, iclass 14, count 0 2006.285.07:33:22.42#ibcon#*after write, iclass 14, count 0 2006.285.07:33:22.42#ibcon#*before return 0, iclass 14, count 0 2006.285.07:33:22.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:33:22.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:33:22.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.07:33:22.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.07:33:22.42$vck44/vb=6,3 2006.285.07:33:22.42#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.07:33:22.42#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.07:33:22.42#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:22.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:33:22.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:33:22.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:33:22.48#ibcon#enter wrdev, iclass 16, count 2 2006.285.07:33:22.48#ibcon#first serial, iclass 16, count 2 2006.285.07:33:22.48#ibcon#enter sib2, iclass 16, count 2 2006.285.07:33:22.48#ibcon#flushed, iclass 16, count 2 2006.285.07:33:22.48#ibcon#about to write, iclass 16, count 2 2006.285.07:33:22.48#ibcon#wrote, iclass 16, count 2 2006.285.07:33:22.48#ibcon#about to read 3, iclass 16, count 2 2006.285.07:33:22.50#ibcon#read 3, iclass 16, count 2 2006.285.07:33:22.50#ibcon#about to read 4, iclass 16, count 2 2006.285.07:33:22.50#ibcon#read 4, iclass 16, count 2 2006.285.07:33:22.50#ibcon#about to read 5, iclass 16, count 2 2006.285.07:33:22.50#ibcon#read 5, iclass 16, count 2 2006.285.07:33:22.50#ibcon#about to read 6, iclass 16, count 2 2006.285.07:33:22.50#ibcon#read 6, iclass 16, count 2 2006.285.07:33:22.50#ibcon#end of sib2, iclass 16, count 2 2006.285.07:33:22.50#ibcon#*mode == 0, iclass 16, count 2 2006.285.07:33:22.50#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.07:33:22.50#ibcon#[27=AT06-03\r\n] 2006.285.07:33:22.50#ibcon#*before write, iclass 16, count 2 2006.285.07:33:22.50#ibcon#enter sib2, iclass 16, count 2 2006.285.07:33:22.50#ibcon#flushed, iclass 16, count 2 2006.285.07:33:22.50#ibcon#about to write, iclass 16, count 2 2006.285.07:33:22.50#ibcon#wrote, iclass 16, count 2 2006.285.07:33:22.50#ibcon#about to read 3, iclass 16, count 2 2006.285.07:33:22.53#ibcon#read 3, iclass 16, count 2 2006.285.07:33:22.53#ibcon#about to read 4, iclass 16, count 2 2006.285.07:33:22.53#ibcon#read 4, iclass 16, count 2 2006.285.07:33:22.53#ibcon#about to read 5, iclass 16, count 2 2006.285.07:33:22.53#ibcon#read 5, iclass 16, count 2 2006.285.07:33:22.53#ibcon#about to read 6, iclass 16, count 2 2006.285.07:33:22.53#ibcon#read 6, iclass 16, count 2 2006.285.07:33:22.53#ibcon#end of sib2, iclass 16, count 2 2006.285.07:33:22.53#ibcon#*after write, iclass 16, count 2 2006.285.07:33:22.53#ibcon#*before return 0, iclass 16, count 2 2006.285.07:33:22.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:33:22.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:33:22.53#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.07:33:22.53#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:22.53#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:33:22.65#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:33:22.65#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:33:22.65#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:33:22.65#ibcon#first serial, iclass 16, count 0 2006.285.07:33:22.65#ibcon#enter sib2, iclass 16, count 0 2006.285.07:33:22.65#ibcon#flushed, iclass 16, count 0 2006.285.07:33:22.65#ibcon#about to write, iclass 16, count 0 2006.285.07:33:22.65#ibcon#wrote, iclass 16, count 0 2006.285.07:33:22.65#ibcon#about to read 3, iclass 16, count 0 2006.285.07:33:22.67#ibcon#read 3, iclass 16, count 0 2006.285.07:33:22.67#ibcon#about to read 4, iclass 16, count 0 2006.285.07:33:22.67#ibcon#read 4, iclass 16, count 0 2006.285.07:33:22.67#ibcon#about to read 5, iclass 16, count 0 2006.285.07:33:22.67#ibcon#read 5, iclass 16, count 0 2006.285.07:33:22.67#ibcon#about to read 6, iclass 16, count 0 2006.285.07:33:22.67#ibcon#read 6, iclass 16, count 0 2006.285.07:33:22.67#ibcon#end of sib2, iclass 16, count 0 2006.285.07:33:22.67#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:33:22.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:33:22.67#ibcon#[27=USB\r\n] 2006.285.07:33:22.67#ibcon#*before write, iclass 16, count 0 2006.285.07:33:22.67#ibcon#enter sib2, iclass 16, count 0 2006.285.07:33:22.67#ibcon#flushed, iclass 16, count 0 2006.285.07:33:22.67#ibcon#about to write, iclass 16, count 0 2006.285.07:33:22.67#ibcon#wrote, iclass 16, count 0 2006.285.07:33:22.67#ibcon#about to read 3, iclass 16, count 0 2006.285.07:33:22.70#ibcon#read 3, iclass 16, count 0 2006.285.07:33:22.70#ibcon#about to read 4, iclass 16, count 0 2006.285.07:33:22.70#ibcon#read 4, iclass 16, count 0 2006.285.07:33:22.70#ibcon#about to read 5, iclass 16, count 0 2006.285.07:33:22.70#ibcon#read 5, iclass 16, count 0 2006.285.07:33:22.70#ibcon#about to read 6, iclass 16, count 0 2006.285.07:33:22.70#ibcon#read 6, iclass 16, count 0 2006.285.07:33:22.70#ibcon#end of sib2, iclass 16, count 0 2006.285.07:33:22.70#ibcon#*after write, iclass 16, count 0 2006.285.07:33:22.70#ibcon#*before return 0, iclass 16, count 0 2006.285.07:33:22.70#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:33:22.70#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:33:22.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:33:22.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:33:22.70$vck44/vblo=7,734.99 2006.285.07:33:22.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.07:33:22.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.07:33:22.70#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:22.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:33:22.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:33:22.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:33:22.70#ibcon#enter wrdev, iclass 18, count 0 2006.285.07:33:22.70#ibcon#first serial, iclass 18, count 0 2006.285.07:33:22.70#ibcon#enter sib2, iclass 18, count 0 2006.285.07:33:22.70#ibcon#flushed, iclass 18, count 0 2006.285.07:33:22.70#ibcon#about to write, iclass 18, count 0 2006.285.07:33:22.70#ibcon#wrote, iclass 18, count 0 2006.285.07:33:22.70#ibcon#about to read 3, iclass 18, count 0 2006.285.07:33:22.72#ibcon#read 3, iclass 18, count 0 2006.285.07:33:22.72#ibcon#about to read 4, iclass 18, count 0 2006.285.07:33:22.72#ibcon#read 4, iclass 18, count 0 2006.285.07:33:22.72#ibcon#about to read 5, iclass 18, count 0 2006.285.07:33:22.72#ibcon#read 5, iclass 18, count 0 2006.285.07:33:22.72#ibcon#about to read 6, iclass 18, count 0 2006.285.07:33:22.72#ibcon#read 6, iclass 18, count 0 2006.285.07:33:22.72#ibcon#end of sib2, iclass 18, count 0 2006.285.07:33:22.72#ibcon#*mode == 0, iclass 18, count 0 2006.285.07:33:22.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.07:33:22.72#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:33:22.72#ibcon#*before write, iclass 18, count 0 2006.285.07:33:22.72#ibcon#enter sib2, iclass 18, count 0 2006.285.07:33:22.72#ibcon#flushed, iclass 18, count 0 2006.285.07:33:22.72#ibcon#about to write, iclass 18, count 0 2006.285.07:33:22.72#ibcon#wrote, iclass 18, count 0 2006.285.07:33:22.72#ibcon#about to read 3, iclass 18, count 0 2006.285.07:33:22.76#ibcon#read 3, iclass 18, count 0 2006.285.07:33:22.76#ibcon#about to read 4, iclass 18, count 0 2006.285.07:33:22.76#ibcon#read 4, iclass 18, count 0 2006.285.07:33:22.76#ibcon#about to read 5, iclass 18, count 0 2006.285.07:33:22.76#ibcon#read 5, iclass 18, count 0 2006.285.07:33:22.76#ibcon#about to read 6, iclass 18, count 0 2006.285.07:33:22.76#ibcon#read 6, iclass 18, count 0 2006.285.07:33:22.76#ibcon#end of sib2, iclass 18, count 0 2006.285.07:33:22.76#ibcon#*after write, iclass 18, count 0 2006.285.07:33:22.76#ibcon#*before return 0, iclass 18, count 0 2006.285.07:33:22.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:33:22.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:33:22.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.07:33:22.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.07:33:22.76$vck44/vb=7,4 2006.285.07:33:22.76#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.07:33:22.76#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.07:33:22.76#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:22.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:33:22.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:33:22.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:33:22.82#ibcon#enter wrdev, iclass 20, count 2 2006.285.07:33:22.82#ibcon#first serial, iclass 20, count 2 2006.285.07:33:22.82#ibcon#enter sib2, iclass 20, count 2 2006.285.07:33:22.82#ibcon#flushed, iclass 20, count 2 2006.285.07:33:22.82#ibcon#about to write, iclass 20, count 2 2006.285.07:33:22.82#ibcon#wrote, iclass 20, count 2 2006.285.07:33:22.82#ibcon#about to read 3, iclass 20, count 2 2006.285.07:33:22.84#ibcon#read 3, iclass 20, count 2 2006.285.07:33:22.84#ibcon#about to read 4, iclass 20, count 2 2006.285.07:33:22.84#ibcon#read 4, iclass 20, count 2 2006.285.07:33:22.84#ibcon#about to read 5, iclass 20, count 2 2006.285.07:33:22.84#ibcon#read 5, iclass 20, count 2 2006.285.07:33:22.84#ibcon#about to read 6, iclass 20, count 2 2006.285.07:33:22.84#ibcon#read 6, iclass 20, count 2 2006.285.07:33:22.84#ibcon#end of sib2, iclass 20, count 2 2006.285.07:33:22.84#ibcon#*mode == 0, iclass 20, count 2 2006.285.07:33:22.84#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.07:33:22.84#ibcon#[27=AT07-04\r\n] 2006.285.07:33:22.84#ibcon#*before write, iclass 20, count 2 2006.285.07:33:22.84#ibcon#enter sib2, iclass 20, count 2 2006.285.07:33:22.84#ibcon#flushed, iclass 20, count 2 2006.285.07:33:22.84#ibcon#about to write, iclass 20, count 2 2006.285.07:33:22.84#ibcon#wrote, iclass 20, count 2 2006.285.07:33:22.84#ibcon#about to read 3, iclass 20, count 2 2006.285.07:33:22.87#ibcon#read 3, iclass 20, count 2 2006.285.07:33:22.87#ibcon#about to read 4, iclass 20, count 2 2006.285.07:33:22.87#ibcon#read 4, iclass 20, count 2 2006.285.07:33:22.87#ibcon#about to read 5, iclass 20, count 2 2006.285.07:33:22.87#ibcon#read 5, iclass 20, count 2 2006.285.07:33:22.87#ibcon#about to read 6, iclass 20, count 2 2006.285.07:33:22.87#ibcon#read 6, iclass 20, count 2 2006.285.07:33:22.87#ibcon#end of sib2, iclass 20, count 2 2006.285.07:33:22.87#ibcon#*after write, iclass 20, count 2 2006.285.07:33:22.87#ibcon#*before return 0, iclass 20, count 2 2006.285.07:33:22.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:33:22.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:33:22.87#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.07:33:22.87#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:22.87#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:33:22.99#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:33:22.99#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:33:22.99#ibcon#enter wrdev, iclass 20, count 0 2006.285.07:33:22.99#ibcon#first serial, iclass 20, count 0 2006.285.07:33:22.99#ibcon#enter sib2, iclass 20, count 0 2006.285.07:33:22.99#ibcon#flushed, iclass 20, count 0 2006.285.07:33:22.99#ibcon#about to write, iclass 20, count 0 2006.285.07:33:22.99#ibcon#wrote, iclass 20, count 0 2006.285.07:33:22.99#ibcon#about to read 3, iclass 20, count 0 2006.285.07:33:23.01#ibcon#read 3, iclass 20, count 0 2006.285.07:33:23.01#ibcon#about to read 4, iclass 20, count 0 2006.285.07:33:23.01#ibcon#read 4, iclass 20, count 0 2006.285.07:33:23.01#ibcon#about to read 5, iclass 20, count 0 2006.285.07:33:23.01#ibcon#read 5, iclass 20, count 0 2006.285.07:33:23.01#ibcon#about to read 6, iclass 20, count 0 2006.285.07:33:23.01#ibcon#read 6, iclass 20, count 0 2006.285.07:33:23.01#ibcon#end of sib2, iclass 20, count 0 2006.285.07:33:23.01#ibcon#*mode == 0, iclass 20, count 0 2006.285.07:33:23.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.07:33:23.01#ibcon#[27=USB\r\n] 2006.285.07:33:23.01#ibcon#*before write, iclass 20, count 0 2006.285.07:33:23.01#ibcon#enter sib2, iclass 20, count 0 2006.285.07:33:23.01#ibcon#flushed, iclass 20, count 0 2006.285.07:33:23.01#ibcon#about to write, iclass 20, count 0 2006.285.07:33:23.01#ibcon#wrote, iclass 20, count 0 2006.285.07:33:23.01#ibcon#about to read 3, iclass 20, count 0 2006.285.07:33:23.04#ibcon#read 3, iclass 20, count 0 2006.285.07:33:23.04#ibcon#about to read 4, iclass 20, count 0 2006.285.07:33:23.04#ibcon#read 4, iclass 20, count 0 2006.285.07:33:23.04#ibcon#about to read 5, iclass 20, count 0 2006.285.07:33:23.04#ibcon#read 5, iclass 20, count 0 2006.285.07:33:23.04#ibcon#about to read 6, iclass 20, count 0 2006.285.07:33:23.04#ibcon#read 6, iclass 20, count 0 2006.285.07:33:23.04#ibcon#end of sib2, iclass 20, count 0 2006.285.07:33:23.04#ibcon#*after write, iclass 20, count 0 2006.285.07:33:23.04#ibcon#*before return 0, iclass 20, count 0 2006.285.07:33:23.04#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:33:23.04#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:33:23.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.07:33:23.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.07:33:23.04$vck44/vblo=8,744.99 2006.285.07:33:23.04#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.07:33:23.04#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.07:33:23.04#ibcon#ireg 17 cls_cnt 0 2006.285.07:33:23.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:33:23.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:33:23.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:33:23.04#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:33:23.04#ibcon#first serial, iclass 22, count 0 2006.285.07:33:23.04#ibcon#enter sib2, iclass 22, count 0 2006.285.07:33:23.04#ibcon#flushed, iclass 22, count 0 2006.285.07:33:23.04#ibcon#about to write, iclass 22, count 0 2006.285.07:33:23.04#ibcon#wrote, iclass 22, count 0 2006.285.07:33:23.04#ibcon#about to read 3, iclass 22, count 0 2006.285.07:33:23.06#ibcon#read 3, iclass 22, count 0 2006.285.07:33:23.06#ibcon#about to read 4, iclass 22, count 0 2006.285.07:33:23.06#ibcon#read 4, iclass 22, count 0 2006.285.07:33:23.06#ibcon#about to read 5, iclass 22, count 0 2006.285.07:33:23.06#ibcon#read 5, iclass 22, count 0 2006.285.07:33:23.06#ibcon#about to read 6, iclass 22, count 0 2006.285.07:33:23.06#ibcon#read 6, iclass 22, count 0 2006.285.07:33:23.06#ibcon#end of sib2, iclass 22, count 0 2006.285.07:33:23.06#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:33:23.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:33:23.06#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:33:23.06#ibcon#*before write, iclass 22, count 0 2006.285.07:33:23.06#ibcon#enter sib2, iclass 22, count 0 2006.285.07:33:23.06#ibcon#flushed, iclass 22, count 0 2006.285.07:33:23.06#ibcon#about to write, iclass 22, count 0 2006.285.07:33:23.06#ibcon#wrote, iclass 22, count 0 2006.285.07:33:23.06#ibcon#about to read 3, iclass 22, count 0 2006.285.07:33:23.10#ibcon#read 3, iclass 22, count 0 2006.285.07:33:23.10#ibcon#about to read 4, iclass 22, count 0 2006.285.07:33:23.10#ibcon#read 4, iclass 22, count 0 2006.285.07:33:23.10#ibcon#about to read 5, iclass 22, count 0 2006.285.07:33:23.10#ibcon#read 5, iclass 22, count 0 2006.285.07:33:23.10#ibcon#about to read 6, iclass 22, count 0 2006.285.07:33:23.10#ibcon#read 6, iclass 22, count 0 2006.285.07:33:23.10#ibcon#end of sib2, iclass 22, count 0 2006.285.07:33:23.10#ibcon#*after write, iclass 22, count 0 2006.285.07:33:23.10#ibcon#*before return 0, iclass 22, count 0 2006.285.07:33:23.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:33:23.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:33:23.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:33:23.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:33:23.10$vck44/vb=8,4 2006.285.07:33:23.10#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.07:33:23.10#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.07:33:23.10#ibcon#ireg 11 cls_cnt 2 2006.285.07:33:23.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:33:23.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:33:23.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:33:23.16#ibcon#enter wrdev, iclass 24, count 2 2006.285.07:33:23.16#ibcon#first serial, iclass 24, count 2 2006.285.07:33:23.16#ibcon#enter sib2, iclass 24, count 2 2006.285.07:33:23.16#ibcon#flushed, iclass 24, count 2 2006.285.07:33:23.16#ibcon#about to write, iclass 24, count 2 2006.285.07:33:23.16#ibcon#wrote, iclass 24, count 2 2006.285.07:33:23.16#ibcon#about to read 3, iclass 24, count 2 2006.285.07:33:23.18#ibcon#read 3, iclass 24, count 2 2006.285.07:33:23.18#ibcon#about to read 4, iclass 24, count 2 2006.285.07:33:23.18#ibcon#read 4, iclass 24, count 2 2006.285.07:33:23.18#ibcon#about to read 5, iclass 24, count 2 2006.285.07:33:23.18#ibcon#read 5, iclass 24, count 2 2006.285.07:33:23.18#ibcon#about to read 6, iclass 24, count 2 2006.285.07:33:23.18#ibcon#read 6, iclass 24, count 2 2006.285.07:33:23.18#ibcon#end of sib2, iclass 24, count 2 2006.285.07:33:23.18#ibcon#*mode == 0, iclass 24, count 2 2006.285.07:33:23.18#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.07:33:23.18#ibcon#[27=AT08-04\r\n] 2006.285.07:33:23.18#ibcon#*before write, iclass 24, count 2 2006.285.07:33:23.18#ibcon#enter sib2, iclass 24, count 2 2006.285.07:33:23.18#ibcon#flushed, iclass 24, count 2 2006.285.07:33:23.18#ibcon#about to write, iclass 24, count 2 2006.285.07:33:23.18#ibcon#wrote, iclass 24, count 2 2006.285.07:33:23.18#ibcon#about to read 3, iclass 24, count 2 2006.285.07:33:23.21#ibcon#read 3, iclass 24, count 2 2006.285.07:33:23.21#ibcon#about to read 4, iclass 24, count 2 2006.285.07:33:23.21#ibcon#read 4, iclass 24, count 2 2006.285.07:33:23.21#ibcon#about to read 5, iclass 24, count 2 2006.285.07:33:23.21#ibcon#read 5, iclass 24, count 2 2006.285.07:33:23.21#ibcon#about to read 6, iclass 24, count 2 2006.285.07:33:23.21#ibcon#read 6, iclass 24, count 2 2006.285.07:33:23.21#ibcon#end of sib2, iclass 24, count 2 2006.285.07:33:23.21#ibcon#*after write, iclass 24, count 2 2006.285.07:33:23.21#ibcon#*before return 0, iclass 24, count 2 2006.285.07:33:23.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:33:23.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:33:23.21#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.07:33:23.21#ibcon#ireg 7 cls_cnt 0 2006.285.07:33:23.21#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:33:23.32#abcon#<5=/04 2.9 5.6 23.62 771014.3\r\n> 2006.285.07:33:23.33#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:33:23.33#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:33:23.33#ibcon#enter wrdev, iclass 24, count 0 2006.285.07:33:23.33#ibcon#first serial, iclass 24, count 0 2006.285.07:33:23.33#ibcon#enter sib2, iclass 24, count 0 2006.285.07:33:23.33#ibcon#flushed, iclass 24, count 0 2006.285.07:33:23.33#ibcon#about to write, iclass 24, count 0 2006.285.07:33:23.33#ibcon#wrote, iclass 24, count 0 2006.285.07:33:23.33#ibcon#about to read 3, iclass 24, count 0 2006.285.07:33:23.34#abcon#{5=INTERFACE CLEAR} 2006.285.07:33:23.35#ibcon#read 3, iclass 24, count 0 2006.285.07:33:23.35#ibcon#about to read 4, iclass 24, count 0 2006.285.07:33:23.35#ibcon#read 4, iclass 24, count 0 2006.285.07:33:23.35#ibcon#about to read 5, iclass 24, count 0 2006.285.07:33:23.35#ibcon#read 5, iclass 24, count 0 2006.285.07:33:23.35#ibcon#about to read 6, iclass 24, count 0 2006.285.07:33:23.35#ibcon#read 6, iclass 24, count 0 2006.285.07:33:23.35#ibcon#end of sib2, iclass 24, count 0 2006.285.07:33:23.35#ibcon#*mode == 0, iclass 24, count 0 2006.285.07:33:23.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.07:33:23.35#ibcon#[27=USB\r\n] 2006.285.07:33:23.35#ibcon#*before write, iclass 24, count 0 2006.285.07:33:23.35#ibcon#enter sib2, iclass 24, count 0 2006.285.07:33:23.35#ibcon#flushed, iclass 24, count 0 2006.285.07:33:23.35#ibcon#about to write, iclass 24, count 0 2006.285.07:33:23.35#ibcon#wrote, iclass 24, count 0 2006.285.07:33:23.35#ibcon#about to read 3, iclass 24, count 0 2006.285.07:33:23.38#ibcon#read 3, iclass 24, count 0 2006.285.07:33:23.38#ibcon#about to read 4, iclass 24, count 0 2006.285.07:33:23.38#ibcon#read 4, iclass 24, count 0 2006.285.07:33:23.38#ibcon#about to read 5, iclass 24, count 0 2006.285.07:33:23.38#ibcon#read 5, iclass 24, count 0 2006.285.07:33:23.38#ibcon#about to read 6, iclass 24, count 0 2006.285.07:33:23.38#ibcon#read 6, iclass 24, count 0 2006.285.07:33:23.38#ibcon#end of sib2, iclass 24, count 0 2006.285.07:33:23.38#ibcon#*after write, iclass 24, count 0 2006.285.07:33:23.38#ibcon#*before return 0, iclass 24, count 0 2006.285.07:33:23.38#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:33:23.38#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:33:23.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.07:33:23.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.07:33:23.38$vck44/vabw=wide 2006.285.07:33:23.38#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.07:33:23.38#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.07:33:23.38#ibcon#ireg 8 cls_cnt 0 2006.285.07:33:23.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:33:23.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:33:23.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:33:23.38#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:33:23.38#ibcon#first serial, iclass 29, count 0 2006.285.07:33:23.38#ibcon#enter sib2, iclass 29, count 0 2006.285.07:33:23.38#ibcon#flushed, iclass 29, count 0 2006.285.07:33:23.38#ibcon#about to write, iclass 29, count 0 2006.285.07:33:23.38#ibcon#wrote, iclass 29, count 0 2006.285.07:33:23.38#ibcon#about to read 3, iclass 29, count 0 2006.285.07:33:23.40#ibcon#read 3, iclass 29, count 0 2006.285.07:33:23.40#ibcon#about to read 4, iclass 29, count 0 2006.285.07:33:23.40#ibcon#read 4, iclass 29, count 0 2006.285.07:33:23.40#ibcon#about to read 5, iclass 29, count 0 2006.285.07:33:23.40#ibcon#read 5, iclass 29, count 0 2006.285.07:33:23.40#ibcon#about to read 6, iclass 29, count 0 2006.285.07:33:23.40#ibcon#read 6, iclass 29, count 0 2006.285.07:33:23.40#ibcon#end of sib2, iclass 29, count 0 2006.285.07:33:23.40#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:33:23.40#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:33:23.40#ibcon#[25=BW32\r\n] 2006.285.07:33:23.40#ibcon#*before write, iclass 29, count 0 2006.285.07:33:23.40#ibcon#enter sib2, iclass 29, count 0 2006.285.07:33:23.40#ibcon#flushed, iclass 29, count 0 2006.285.07:33:23.40#ibcon#about to write, iclass 29, count 0 2006.285.07:33:23.40#ibcon#wrote, iclass 29, count 0 2006.285.07:33:23.40#ibcon#about to read 3, iclass 29, count 0 2006.285.07:33:23.40#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:33:23.43#ibcon#read 3, iclass 29, count 0 2006.285.07:33:23.43#ibcon#about to read 4, iclass 29, count 0 2006.285.07:33:23.43#ibcon#read 4, iclass 29, count 0 2006.285.07:33:23.43#ibcon#about to read 5, iclass 29, count 0 2006.285.07:33:23.43#ibcon#read 5, iclass 29, count 0 2006.285.07:33:23.43#ibcon#about to read 6, iclass 29, count 0 2006.285.07:33:23.43#ibcon#read 6, iclass 29, count 0 2006.285.07:33:23.43#ibcon#end of sib2, iclass 29, count 0 2006.285.07:33:23.43#ibcon#*after write, iclass 29, count 0 2006.285.07:33:23.43#ibcon#*before return 0, iclass 29, count 0 2006.285.07:33:23.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:33:23.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:33:23.43#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:33:23.43#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:33:23.43$vck44/vbbw=wide 2006.285.07:33:23.43#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.07:33:23.43#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.07:33:23.43#ibcon#ireg 8 cls_cnt 0 2006.285.07:33:23.43#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:33:23.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:33:23.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:33:23.50#ibcon#enter wrdev, iclass 32, count 0 2006.285.07:33:23.50#ibcon#first serial, iclass 32, count 0 2006.285.07:33:23.50#ibcon#enter sib2, iclass 32, count 0 2006.285.07:33:23.50#ibcon#flushed, iclass 32, count 0 2006.285.07:33:23.50#ibcon#about to write, iclass 32, count 0 2006.285.07:33:23.50#ibcon#wrote, iclass 32, count 0 2006.285.07:33:23.50#ibcon#about to read 3, iclass 32, count 0 2006.285.07:33:23.52#ibcon#read 3, iclass 32, count 0 2006.285.07:33:23.52#ibcon#about to read 4, iclass 32, count 0 2006.285.07:33:23.52#ibcon#read 4, iclass 32, count 0 2006.285.07:33:23.52#ibcon#about to read 5, iclass 32, count 0 2006.285.07:33:23.52#ibcon#read 5, iclass 32, count 0 2006.285.07:33:23.52#ibcon#about to read 6, iclass 32, count 0 2006.285.07:33:23.52#ibcon#read 6, iclass 32, count 0 2006.285.07:33:23.52#ibcon#end of sib2, iclass 32, count 0 2006.285.07:33:23.52#ibcon#*mode == 0, iclass 32, count 0 2006.285.07:33:23.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.07:33:23.52#ibcon#[27=BW32\r\n] 2006.285.07:33:23.52#ibcon#*before write, iclass 32, count 0 2006.285.07:33:23.52#ibcon#enter sib2, iclass 32, count 0 2006.285.07:33:23.52#ibcon#flushed, iclass 32, count 0 2006.285.07:33:23.52#ibcon#about to write, iclass 32, count 0 2006.285.07:33:23.52#ibcon#wrote, iclass 32, count 0 2006.285.07:33:23.52#ibcon#about to read 3, iclass 32, count 0 2006.285.07:33:23.55#ibcon#read 3, iclass 32, count 0 2006.285.07:33:23.55#ibcon#about to read 4, iclass 32, count 0 2006.285.07:33:23.55#ibcon#read 4, iclass 32, count 0 2006.285.07:33:23.55#ibcon#about to read 5, iclass 32, count 0 2006.285.07:33:23.55#ibcon#read 5, iclass 32, count 0 2006.285.07:33:23.55#ibcon#about to read 6, iclass 32, count 0 2006.285.07:33:23.55#ibcon#read 6, iclass 32, count 0 2006.285.07:33:23.55#ibcon#end of sib2, iclass 32, count 0 2006.285.07:33:23.55#ibcon#*after write, iclass 32, count 0 2006.285.07:33:23.55#ibcon#*before return 0, iclass 32, count 0 2006.285.07:33:23.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:33:23.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:33:23.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.07:33:23.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.07:33:23.55$setupk4/ifdk4 2006.285.07:33:23.55$ifdk4/lo= 2006.285.07:33:23.55$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:33:23.55$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:33:23.55$ifdk4/patch= 2006.285.07:33:23.55$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:33:23.55$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:33:23.55$setupk4/!*+20s 2006.285.07:33:32.14#trakl#Source acquired 2006.285.07:33:33.14#flagr#flagr/antenna,acquired 2006.285.07:33:33.49#abcon#<5=/04 2.9 5.6 23.62 771014.4\r\n> 2006.285.07:33:33.51#abcon#{5=INTERFACE CLEAR} 2006.285.07:33:33.57#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:33:38.06$setupk4/"tpicd 2006.285.07:33:38.06$setupk4/echo=off 2006.285.07:33:38.06$setupk4/xlog=off 2006.285.07:33:38.06:!2006.285.07:34:23 2006.285.07:34:23.00:preob 2006.285.07:34:23.14/onsource/TRACKING 2006.285.07:34:23.14:!2006.285.07:34:33 2006.285.07:34:33.00:"tape 2006.285.07:34:33.00:"st=record 2006.285.07:34:33.00:data_valid=on 2006.285.07:34:33.00:midob 2006.285.07:34:33.14/onsource/TRACKING 2006.285.07:34:33.14/wx/23.61,1014.4,77 2006.285.07:34:33.32/cable/+6.4735E-03 2006.285.07:34:34.41/va/01,07,usb,yes,34,37 2006.285.07:34:34.41/va/02,06,usb,yes,34,34 2006.285.07:34:34.41/va/03,07,usb,yes,33,35 2006.285.07:34:34.41/va/04,06,usb,yes,35,36 2006.285.07:34:34.41/va/05,03,usb,yes,34,35 2006.285.07:34:34.41/va/06,04,usb,yes,31,30 2006.285.07:34:34.41/va/07,04,usb,yes,32,32 2006.285.07:34:34.41/va/08,03,usb,yes,32,39 2006.285.07:34:34.64/valo/01,524.99,yes,locked 2006.285.07:34:34.64/valo/02,534.99,yes,locked 2006.285.07:34:34.64/valo/03,564.99,yes,locked 2006.285.07:34:34.64/valo/04,624.99,yes,locked 2006.285.07:34:34.64/valo/05,734.99,yes,locked 2006.285.07:34:34.64/valo/06,814.99,yes,locked 2006.285.07:34:34.64/valo/07,864.99,yes,locked 2006.285.07:34:34.64/valo/08,884.99,yes,locked 2006.285.07:34:35.73/vb/01,04,usb,yes,32,30 2006.285.07:34:35.73/vb/02,05,usb,yes,30,30 2006.285.07:34:35.73/vb/03,04,usb,yes,31,34 2006.285.07:34:35.73/vb/04,05,usb,yes,31,30 2006.285.07:34:35.73/vb/05,04,usb,yes,28,30 2006.285.07:34:35.73/vb/06,03,usb,yes,40,35 2006.285.07:34:35.73/vb/07,04,usb,yes,32,32 2006.285.07:34:35.73/vb/08,04,usb,yes,29,33 2006.285.07:34:35.97/vblo/01,629.99,yes,locked 2006.285.07:34:35.97/vblo/02,634.99,yes,locked 2006.285.07:34:35.97/vblo/03,649.99,yes,locked 2006.285.07:34:35.97/vblo/04,679.99,yes,locked 2006.285.07:34:35.97/vblo/05,709.99,yes,locked 2006.285.07:34:35.97/vblo/06,719.99,yes,locked 2006.285.07:34:35.97/vblo/07,734.99,yes,locked 2006.285.07:34:35.97/vblo/08,744.99,yes,locked 2006.285.07:34:36.12/vabw/8 2006.285.07:34:36.27/vbbw/8 2006.285.07:34:36.36/xfe/off,on,12.2 2006.285.07:34:36.74/ifatt/23,28,28,28 2006.285.07:34:37.08/fmout-gps/S +2.75E-07 2006.285.07:34:37.10:!2006.285.07:35:13 2006.285.07:35:13.00:data_valid=off 2006.285.07:35:13.00:"et 2006.285.07:35:13.00:!+3s 2006.285.07:35:16.01:"tape 2006.285.07:35:16.01:postob 2006.285.07:35:16.23/cable/+6.4724E-03 2006.285.07:35:16.23/wx/23.59,1014.3,77 2006.285.07:35:17.07/fmout-gps/S +2.75E-07 2006.285.07:35:17.07:scan_name=285-0737,jd0610,40 2006.285.07:35:17.07:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.285.07:35:18.14#flagr#flagr/antenna,new-source 2006.285.07:35:18.14:checkk5 2006.285.07:35:18.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:35:18.97/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:35:19.58/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:35:19.98/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:35:20.53/chk_obsdata//k5ts1/T2850734??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.07:35:20.93/chk_obsdata//k5ts2/T2850734??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.07:35:21.33/chk_obsdata//k5ts3/T2850734??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.07:35:21.73/chk_obsdata//k5ts4/T2850734??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.07:35:22.49/k5log//k5ts1_log_newline 2006.285.07:35:23.43/k5log//k5ts2_log_newline 2006.285.07:35:24.17/k5log//k5ts3_log_newline 2006.285.07:35:24.98/k5log//k5ts4_log_newline 2006.285.07:35:25.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:35:25.01:setupk4=1 2006.285.07:35:25.01$setupk4/echo=on 2006.285.07:35:25.01$setupk4/pcalon 2006.285.07:35:25.01$pcalon/"no phase cal control is implemented here 2006.285.07:35:25.01$setupk4/"tpicd=stop 2006.285.07:35:25.01$setupk4/"rec=synch_on 2006.285.07:35:25.01$setupk4/"rec_mode=128 2006.285.07:35:25.01$setupk4/!* 2006.285.07:35:25.01$setupk4/recpk4 2006.285.07:35:25.01$recpk4/recpatch= 2006.285.07:35:25.01$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:35:25.01$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:35:25.01$setupk4/vck44 2006.285.07:35:25.01$vck44/valo=1,524.99 2006.285.07:35:25.01#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.07:35:25.01#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.07:35:25.01#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:25.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:35:25.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:35:25.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:35:25.01#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:35:25.01#ibcon#first serial, iclass 7, count 0 2006.285.07:35:25.01#ibcon#enter sib2, iclass 7, count 0 2006.285.07:35:25.01#ibcon#flushed, iclass 7, count 0 2006.285.07:35:25.01#ibcon#about to write, iclass 7, count 0 2006.285.07:35:25.01#ibcon#wrote, iclass 7, count 0 2006.285.07:35:25.01#ibcon#about to read 3, iclass 7, count 0 2006.285.07:35:25.03#ibcon#read 3, iclass 7, count 0 2006.285.07:35:25.03#ibcon#about to read 4, iclass 7, count 0 2006.285.07:35:25.03#ibcon#read 4, iclass 7, count 0 2006.285.07:35:25.03#ibcon#about to read 5, iclass 7, count 0 2006.285.07:35:25.03#ibcon#read 5, iclass 7, count 0 2006.285.07:35:25.03#ibcon#about to read 6, iclass 7, count 0 2006.285.07:35:25.03#ibcon#read 6, iclass 7, count 0 2006.285.07:35:25.03#ibcon#end of sib2, iclass 7, count 0 2006.285.07:35:25.03#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:35:25.03#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:35:25.03#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:35:25.03#ibcon#*before write, iclass 7, count 0 2006.285.07:35:25.03#ibcon#enter sib2, iclass 7, count 0 2006.285.07:35:25.03#ibcon#flushed, iclass 7, count 0 2006.285.07:35:25.03#ibcon#about to write, iclass 7, count 0 2006.285.07:35:25.03#ibcon#wrote, iclass 7, count 0 2006.285.07:35:25.03#ibcon#about to read 3, iclass 7, count 0 2006.285.07:35:25.08#ibcon#read 3, iclass 7, count 0 2006.285.07:35:25.08#ibcon#about to read 4, iclass 7, count 0 2006.285.07:35:25.08#ibcon#read 4, iclass 7, count 0 2006.285.07:35:25.08#ibcon#about to read 5, iclass 7, count 0 2006.285.07:35:25.08#ibcon#read 5, iclass 7, count 0 2006.285.07:35:25.08#ibcon#about to read 6, iclass 7, count 0 2006.285.07:35:25.08#ibcon#read 6, iclass 7, count 0 2006.285.07:35:25.08#ibcon#end of sib2, iclass 7, count 0 2006.285.07:35:25.08#ibcon#*after write, iclass 7, count 0 2006.285.07:35:25.08#ibcon#*before return 0, iclass 7, count 0 2006.285.07:35:25.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:35:25.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:35:25.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:35:25.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:35:25.08$vck44/va=1,7 2006.285.07:35:25.08#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.07:35:25.08#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.07:35:25.08#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:25.08#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:35:25.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:35:25.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:35:25.08#ibcon#enter wrdev, iclass 11, count 2 2006.285.07:35:25.08#ibcon#first serial, iclass 11, count 2 2006.285.07:35:25.08#ibcon#enter sib2, iclass 11, count 2 2006.285.07:35:25.08#ibcon#flushed, iclass 11, count 2 2006.285.07:35:25.08#ibcon#about to write, iclass 11, count 2 2006.285.07:35:25.08#ibcon#wrote, iclass 11, count 2 2006.285.07:35:25.08#ibcon#about to read 3, iclass 11, count 2 2006.285.07:35:25.10#ibcon#read 3, iclass 11, count 2 2006.285.07:35:25.10#ibcon#about to read 4, iclass 11, count 2 2006.285.07:35:25.10#ibcon#read 4, iclass 11, count 2 2006.285.07:35:25.10#ibcon#about to read 5, iclass 11, count 2 2006.285.07:35:25.10#ibcon#read 5, iclass 11, count 2 2006.285.07:35:25.10#ibcon#about to read 6, iclass 11, count 2 2006.285.07:35:25.10#ibcon#read 6, iclass 11, count 2 2006.285.07:35:25.10#ibcon#end of sib2, iclass 11, count 2 2006.285.07:35:25.10#ibcon#*mode == 0, iclass 11, count 2 2006.285.07:35:25.10#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.07:35:25.10#ibcon#[25=AT01-07\r\n] 2006.285.07:35:25.10#ibcon#*before write, iclass 11, count 2 2006.285.07:35:25.10#ibcon#enter sib2, iclass 11, count 2 2006.285.07:35:25.10#ibcon#flushed, iclass 11, count 2 2006.285.07:35:25.10#ibcon#about to write, iclass 11, count 2 2006.285.07:35:25.10#ibcon#wrote, iclass 11, count 2 2006.285.07:35:25.10#ibcon#about to read 3, iclass 11, count 2 2006.285.07:35:25.13#ibcon#read 3, iclass 11, count 2 2006.285.07:35:25.13#ibcon#about to read 4, iclass 11, count 2 2006.285.07:35:25.13#ibcon#read 4, iclass 11, count 2 2006.285.07:35:25.13#ibcon#about to read 5, iclass 11, count 2 2006.285.07:35:25.13#ibcon#read 5, iclass 11, count 2 2006.285.07:35:25.13#ibcon#about to read 6, iclass 11, count 2 2006.285.07:35:25.13#ibcon#read 6, iclass 11, count 2 2006.285.07:35:25.13#ibcon#end of sib2, iclass 11, count 2 2006.285.07:35:25.13#ibcon#*after write, iclass 11, count 2 2006.285.07:35:25.13#ibcon#*before return 0, iclass 11, count 2 2006.285.07:35:25.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:35:25.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:35:25.13#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.07:35:25.13#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:25.13#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:35:25.25#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:35:25.25#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:35:25.25#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:35:25.25#ibcon#first serial, iclass 11, count 0 2006.285.07:35:25.25#ibcon#enter sib2, iclass 11, count 0 2006.285.07:35:25.25#ibcon#flushed, iclass 11, count 0 2006.285.07:35:25.25#ibcon#about to write, iclass 11, count 0 2006.285.07:35:25.25#ibcon#wrote, iclass 11, count 0 2006.285.07:35:25.25#ibcon#about to read 3, iclass 11, count 0 2006.285.07:35:25.27#ibcon#read 3, iclass 11, count 0 2006.285.07:35:25.27#ibcon#about to read 4, iclass 11, count 0 2006.285.07:35:25.27#ibcon#read 4, iclass 11, count 0 2006.285.07:35:25.27#ibcon#about to read 5, iclass 11, count 0 2006.285.07:35:25.27#ibcon#read 5, iclass 11, count 0 2006.285.07:35:25.27#ibcon#about to read 6, iclass 11, count 0 2006.285.07:35:25.27#ibcon#read 6, iclass 11, count 0 2006.285.07:35:25.27#ibcon#end of sib2, iclass 11, count 0 2006.285.07:35:25.27#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:35:25.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:35:25.27#ibcon#[25=USB\r\n] 2006.285.07:35:25.27#ibcon#*before write, iclass 11, count 0 2006.285.07:35:25.27#ibcon#enter sib2, iclass 11, count 0 2006.285.07:35:25.27#ibcon#flushed, iclass 11, count 0 2006.285.07:35:25.27#ibcon#about to write, iclass 11, count 0 2006.285.07:35:25.27#ibcon#wrote, iclass 11, count 0 2006.285.07:35:25.27#ibcon#about to read 3, iclass 11, count 0 2006.285.07:35:25.30#ibcon#read 3, iclass 11, count 0 2006.285.07:35:25.30#ibcon#about to read 4, iclass 11, count 0 2006.285.07:35:25.30#ibcon#read 4, iclass 11, count 0 2006.285.07:35:25.30#ibcon#about to read 5, iclass 11, count 0 2006.285.07:35:25.30#ibcon#read 5, iclass 11, count 0 2006.285.07:35:25.30#ibcon#about to read 6, iclass 11, count 0 2006.285.07:35:25.30#ibcon#read 6, iclass 11, count 0 2006.285.07:35:25.30#ibcon#end of sib2, iclass 11, count 0 2006.285.07:35:25.30#ibcon#*after write, iclass 11, count 0 2006.285.07:35:25.30#ibcon#*before return 0, iclass 11, count 0 2006.285.07:35:25.30#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:35:25.30#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:35:25.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:35:25.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:35:25.30$vck44/valo=2,534.99 2006.285.07:35:25.30#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.07:35:25.30#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.07:35:25.30#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:25.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:35:25.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:35:25.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:35:25.30#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:35:25.30#ibcon#first serial, iclass 13, count 0 2006.285.07:35:25.30#ibcon#enter sib2, iclass 13, count 0 2006.285.07:35:25.30#ibcon#flushed, iclass 13, count 0 2006.285.07:35:25.30#ibcon#about to write, iclass 13, count 0 2006.285.07:35:25.30#ibcon#wrote, iclass 13, count 0 2006.285.07:35:25.30#ibcon#about to read 3, iclass 13, count 0 2006.285.07:35:25.32#ibcon#read 3, iclass 13, count 0 2006.285.07:35:25.32#ibcon#about to read 4, iclass 13, count 0 2006.285.07:35:25.32#ibcon#read 4, iclass 13, count 0 2006.285.07:35:25.32#ibcon#about to read 5, iclass 13, count 0 2006.285.07:35:25.32#ibcon#read 5, iclass 13, count 0 2006.285.07:35:25.32#ibcon#about to read 6, iclass 13, count 0 2006.285.07:35:25.32#ibcon#read 6, iclass 13, count 0 2006.285.07:35:25.32#ibcon#end of sib2, iclass 13, count 0 2006.285.07:35:25.32#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:35:25.32#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:35:25.32#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:35:25.32#ibcon#*before write, iclass 13, count 0 2006.285.07:35:25.32#ibcon#enter sib2, iclass 13, count 0 2006.285.07:35:25.32#ibcon#flushed, iclass 13, count 0 2006.285.07:35:25.32#ibcon#about to write, iclass 13, count 0 2006.285.07:35:25.32#ibcon#wrote, iclass 13, count 0 2006.285.07:35:25.32#ibcon#about to read 3, iclass 13, count 0 2006.285.07:35:25.36#ibcon#read 3, iclass 13, count 0 2006.285.07:35:25.36#ibcon#about to read 4, iclass 13, count 0 2006.285.07:35:25.36#ibcon#read 4, iclass 13, count 0 2006.285.07:35:25.36#ibcon#about to read 5, iclass 13, count 0 2006.285.07:35:25.36#ibcon#read 5, iclass 13, count 0 2006.285.07:35:25.36#ibcon#about to read 6, iclass 13, count 0 2006.285.07:35:25.36#ibcon#read 6, iclass 13, count 0 2006.285.07:35:25.36#ibcon#end of sib2, iclass 13, count 0 2006.285.07:35:25.36#ibcon#*after write, iclass 13, count 0 2006.285.07:35:25.36#ibcon#*before return 0, iclass 13, count 0 2006.285.07:35:25.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:35:25.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:35:25.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:35:25.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:35:25.36$vck44/va=2,6 2006.285.07:35:25.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.07:35:25.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.07:35:25.36#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:25.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:35:25.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:35:25.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:35:25.42#ibcon#enter wrdev, iclass 16, count 2 2006.285.07:35:25.42#ibcon#first serial, iclass 16, count 2 2006.285.07:35:25.42#ibcon#enter sib2, iclass 16, count 2 2006.285.07:35:25.42#ibcon#flushed, iclass 16, count 2 2006.285.07:35:25.42#ibcon#about to write, iclass 16, count 2 2006.285.07:35:25.42#ibcon#wrote, iclass 16, count 2 2006.285.07:35:25.42#ibcon#about to read 3, iclass 16, count 2 2006.285.07:35:25.44#ibcon#read 3, iclass 16, count 2 2006.285.07:35:25.44#ibcon#about to read 4, iclass 16, count 2 2006.285.07:35:25.44#ibcon#read 4, iclass 16, count 2 2006.285.07:35:25.44#ibcon#about to read 5, iclass 16, count 2 2006.285.07:35:25.44#ibcon#read 5, iclass 16, count 2 2006.285.07:35:25.44#ibcon#about to read 6, iclass 16, count 2 2006.285.07:35:25.44#ibcon#read 6, iclass 16, count 2 2006.285.07:35:25.44#ibcon#end of sib2, iclass 16, count 2 2006.285.07:35:25.44#ibcon#*mode == 0, iclass 16, count 2 2006.285.07:35:25.44#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.07:35:25.44#ibcon#[25=AT02-06\r\n] 2006.285.07:35:25.44#ibcon#*before write, iclass 16, count 2 2006.285.07:35:25.44#ibcon#enter sib2, iclass 16, count 2 2006.285.07:35:25.44#ibcon#flushed, iclass 16, count 2 2006.285.07:35:25.44#ibcon#about to write, iclass 16, count 2 2006.285.07:35:25.44#ibcon#wrote, iclass 16, count 2 2006.285.07:35:25.44#ibcon#about to read 3, iclass 16, count 2 2006.285.07:35:25.47#ibcon#read 3, iclass 16, count 2 2006.285.07:35:25.47#ibcon#about to read 4, iclass 16, count 2 2006.285.07:35:25.47#ibcon#read 4, iclass 16, count 2 2006.285.07:35:25.47#ibcon#about to read 5, iclass 16, count 2 2006.285.07:35:25.47#ibcon#read 5, iclass 16, count 2 2006.285.07:35:25.47#ibcon#about to read 6, iclass 16, count 2 2006.285.07:35:25.47#ibcon#read 6, iclass 16, count 2 2006.285.07:35:25.47#ibcon#end of sib2, iclass 16, count 2 2006.285.07:35:25.47#ibcon#*after write, iclass 16, count 2 2006.285.07:35:25.47#ibcon#*before return 0, iclass 16, count 2 2006.285.07:35:25.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:35:25.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:35:25.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.07:35:25.47#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:25.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:35:25.50#abcon#<5=/04 2.7 4.8 23.58 771014.3\r\n> 2006.285.07:35:25.52#abcon#{5=INTERFACE CLEAR} 2006.285.07:35:25.58#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:35:25.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:35:25.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:35:25.59#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:35:25.59#ibcon#first serial, iclass 16, count 0 2006.285.07:35:25.59#ibcon#enter sib2, iclass 16, count 0 2006.285.07:35:25.59#ibcon#flushed, iclass 16, count 0 2006.285.07:35:25.59#ibcon#about to write, iclass 16, count 0 2006.285.07:35:25.59#ibcon#wrote, iclass 16, count 0 2006.285.07:35:25.59#ibcon#about to read 3, iclass 16, count 0 2006.285.07:35:25.61#ibcon#read 3, iclass 16, count 0 2006.285.07:35:25.61#ibcon#about to read 4, iclass 16, count 0 2006.285.07:35:25.61#ibcon#read 4, iclass 16, count 0 2006.285.07:35:25.61#ibcon#about to read 5, iclass 16, count 0 2006.285.07:35:25.61#ibcon#read 5, iclass 16, count 0 2006.285.07:35:25.61#ibcon#about to read 6, iclass 16, count 0 2006.285.07:35:25.61#ibcon#read 6, iclass 16, count 0 2006.285.07:35:25.61#ibcon#end of sib2, iclass 16, count 0 2006.285.07:35:25.61#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:35:25.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:35:25.61#ibcon#[25=USB\r\n] 2006.285.07:35:25.61#ibcon#*before write, iclass 16, count 0 2006.285.07:35:25.61#ibcon#enter sib2, iclass 16, count 0 2006.285.07:35:25.61#ibcon#flushed, iclass 16, count 0 2006.285.07:35:25.61#ibcon#about to write, iclass 16, count 0 2006.285.07:35:25.61#ibcon#wrote, iclass 16, count 0 2006.285.07:35:25.61#ibcon#about to read 3, iclass 16, count 0 2006.285.07:35:25.64#ibcon#read 3, iclass 16, count 0 2006.285.07:35:25.64#ibcon#about to read 4, iclass 16, count 0 2006.285.07:35:25.64#ibcon#read 4, iclass 16, count 0 2006.285.07:35:25.64#ibcon#about to read 5, iclass 16, count 0 2006.285.07:35:25.64#ibcon#read 5, iclass 16, count 0 2006.285.07:35:25.64#ibcon#about to read 6, iclass 16, count 0 2006.285.07:35:25.64#ibcon#read 6, iclass 16, count 0 2006.285.07:35:25.64#ibcon#end of sib2, iclass 16, count 0 2006.285.07:35:25.64#ibcon#*after write, iclass 16, count 0 2006.285.07:35:25.64#ibcon#*before return 0, iclass 16, count 0 2006.285.07:35:25.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:35:25.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:35:25.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:35:25.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:35:25.64$vck44/valo=3,564.99 2006.285.07:35:25.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.07:35:25.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.07:35:25.64#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:25.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:35:25.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:35:25.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:35:25.64#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:35:25.64#ibcon#first serial, iclass 21, count 0 2006.285.07:35:25.64#ibcon#enter sib2, iclass 21, count 0 2006.285.07:35:25.64#ibcon#flushed, iclass 21, count 0 2006.285.07:35:25.64#ibcon#about to write, iclass 21, count 0 2006.285.07:35:25.64#ibcon#wrote, iclass 21, count 0 2006.285.07:35:25.64#ibcon#about to read 3, iclass 21, count 0 2006.285.07:35:25.66#ibcon#read 3, iclass 21, count 0 2006.285.07:35:25.66#ibcon#about to read 4, iclass 21, count 0 2006.285.07:35:25.66#ibcon#read 4, iclass 21, count 0 2006.285.07:35:25.66#ibcon#about to read 5, iclass 21, count 0 2006.285.07:35:25.66#ibcon#read 5, iclass 21, count 0 2006.285.07:35:25.66#ibcon#about to read 6, iclass 21, count 0 2006.285.07:35:25.66#ibcon#read 6, iclass 21, count 0 2006.285.07:35:25.66#ibcon#end of sib2, iclass 21, count 0 2006.285.07:35:25.66#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:35:25.66#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:35:25.66#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:35:25.66#ibcon#*before write, iclass 21, count 0 2006.285.07:35:25.66#ibcon#enter sib2, iclass 21, count 0 2006.285.07:35:25.66#ibcon#flushed, iclass 21, count 0 2006.285.07:35:25.66#ibcon#about to write, iclass 21, count 0 2006.285.07:35:25.66#ibcon#wrote, iclass 21, count 0 2006.285.07:35:25.66#ibcon#about to read 3, iclass 21, count 0 2006.285.07:35:25.70#ibcon#read 3, iclass 21, count 0 2006.285.07:35:25.70#ibcon#about to read 4, iclass 21, count 0 2006.285.07:35:25.70#ibcon#read 4, iclass 21, count 0 2006.285.07:35:25.70#ibcon#about to read 5, iclass 21, count 0 2006.285.07:35:25.70#ibcon#read 5, iclass 21, count 0 2006.285.07:35:25.70#ibcon#about to read 6, iclass 21, count 0 2006.285.07:35:25.70#ibcon#read 6, iclass 21, count 0 2006.285.07:35:25.70#ibcon#end of sib2, iclass 21, count 0 2006.285.07:35:25.70#ibcon#*after write, iclass 21, count 0 2006.285.07:35:25.70#ibcon#*before return 0, iclass 21, count 0 2006.285.07:35:25.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:35:25.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:35:25.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:35:25.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:35:25.70$vck44/va=3,7 2006.285.07:35:25.70#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.07:35:25.70#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.07:35:25.70#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:25.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:35:25.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:35:25.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:35:25.76#ibcon#enter wrdev, iclass 23, count 2 2006.285.07:35:25.76#ibcon#first serial, iclass 23, count 2 2006.285.07:35:25.76#ibcon#enter sib2, iclass 23, count 2 2006.285.07:35:25.76#ibcon#flushed, iclass 23, count 2 2006.285.07:35:25.76#ibcon#about to write, iclass 23, count 2 2006.285.07:35:25.76#ibcon#wrote, iclass 23, count 2 2006.285.07:35:25.76#ibcon#about to read 3, iclass 23, count 2 2006.285.07:35:25.78#ibcon#read 3, iclass 23, count 2 2006.285.07:35:25.78#ibcon#about to read 4, iclass 23, count 2 2006.285.07:35:25.78#ibcon#read 4, iclass 23, count 2 2006.285.07:35:25.78#ibcon#about to read 5, iclass 23, count 2 2006.285.07:35:25.78#ibcon#read 5, iclass 23, count 2 2006.285.07:35:25.78#ibcon#about to read 6, iclass 23, count 2 2006.285.07:35:25.78#ibcon#read 6, iclass 23, count 2 2006.285.07:35:25.78#ibcon#end of sib2, iclass 23, count 2 2006.285.07:35:25.78#ibcon#*mode == 0, iclass 23, count 2 2006.285.07:35:25.78#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.07:35:25.78#ibcon#[25=AT03-07\r\n] 2006.285.07:35:25.78#ibcon#*before write, iclass 23, count 2 2006.285.07:35:25.78#ibcon#enter sib2, iclass 23, count 2 2006.285.07:35:25.78#ibcon#flushed, iclass 23, count 2 2006.285.07:35:25.78#ibcon#about to write, iclass 23, count 2 2006.285.07:35:25.78#ibcon#wrote, iclass 23, count 2 2006.285.07:35:25.78#ibcon#about to read 3, iclass 23, count 2 2006.285.07:35:25.81#ibcon#read 3, iclass 23, count 2 2006.285.07:35:25.81#ibcon#about to read 4, iclass 23, count 2 2006.285.07:35:25.81#ibcon#read 4, iclass 23, count 2 2006.285.07:35:25.81#ibcon#about to read 5, iclass 23, count 2 2006.285.07:35:25.81#ibcon#read 5, iclass 23, count 2 2006.285.07:35:25.81#ibcon#about to read 6, iclass 23, count 2 2006.285.07:35:25.81#ibcon#read 6, iclass 23, count 2 2006.285.07:35:25.81#ibcon#end of sib2, iclass 23, count 2 2006.285.07:35:25.81#ibcon#*after write, iclass 23, count 2 2006.285.07:35:25.81#ibcon#*before return 0, iclass 23, count 2 2006.285.07:35:25.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:35:25.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:35:25.81#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.07:35:25.81#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:25.81#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:35:25.93#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:35:25.93#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:35:25.93#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:35:25.93#ibcon#first serial, iclass 23, count 0 2006.285.07:35:25.93#ibcon#enter sib2, iclass 23, count 0 2006.285.07:35:25.93#ibcon#flushed, iclass 23, count 0 2006.285.07:35:25.93#ibcon#about to write, iclass 23, count 0 2006.285.07:35:25.93#ibcon#wrote, iclass 23, count 0 2006.285.07:35:25.93#ibcon#about to read 3, iclass 23, count 0 2006.285.07:35:25.95#ibcon#read 3, iclass 23, count 0 2006.285.07:35:25.95#ibcon#about to read 4, iclass 23, count 0 2006.285.07:35:25.95#ibcon#read 4, iclass 23, count 0 2006.285.07:35:25.95#ibcon#about to read 5, iclass 23, count 0 2006.285.07:35:25.95#ibcon#read 5, iclass 23, count 0 2006.285.07:35:25.95#ibcon#about to read 6, iclass 23, count 0 2006.285.07:35:25.95#ibcon#read 6, iclass 23, count 0 2006.285.07:35:25.95#ibcon#end of sib2, iclass 23, count 0 2006.285.07:35:25.95#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:35:25.95#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:35:25.95#ibcon#[25=USB\r\n] 2006.285.07:35:25.95#ibcon#*before write, iclass 23, count 0 2006.285.07:35:25.95#ibcon#enter sib2, iclass 23, count 0 2006.285.07:35:25.95#ibcon#flushed, iclass 23, count 0 2006.285.07:35:25.95#ibcon#about to write, iclass 23, count 0 2006.285.07:35:25.95#ibcon#wrote, iclass 23, count 0 2006.285.07:35:25.95#ibcon#about to read 3, iclass 23, count 0 2006.285.07:35:25.98#ibcon#read 3, iclass 23, count 0 2006.285.07:35:25.98#ibcon#about to read 4, iclass 23, count 0 2006.285.07:35:25.98#ibcon#read 4, iclass 23, count 0 2006.285.07:35:25.98#ibcon#about to read 5, iclass 23, count 0 2006.285.07:35:25.98#ibcon#read 5, iclass 23, count 0 2006.285.07:35:25.98#ibcon#about to read 6, iclass 23, count 0 2006.285.07:35:25.98#ibcon#read 6, iclass 23, count 0 2006.285.07:35:25.98#ibcon#end of sib2, iclass 23, count 0 2006.285.07:35:25.98#ibcon#*after write, iclass 23, count 0 2006.285.07:35:25.98#ibcon#*before return 0, iclass 23, count 0 2006.285.07:35:25.98#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:35:25.98#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:35:25.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:35:25.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:35:25.98$vck44/valo=4,624.99 2006.285.07:35:25.98#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.07:35:25.98#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.07:35:25.98#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:25.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:35:25.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:35:25.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:35:25.98#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:35:25.98#ibcon#first serial, iclass 25, count 0 2006.285.07:35:25.98#ibcon#enter sib2, iclass 25, count 0 2006.285.07:35:25.98#ibcon#flushed, iclass 25, count 0 2006.285.07:35:25.98#ibcon#about to write, iclass 25, count 0 2006.285.07:35:25.98#ibcon#wrote, iclass 25, count 0 2006.285.07:35:25.98#ibcon#about to read 3, iclass 25, count 0 2006.285.07:35:26.00#ibcon#read 3, iclass 25, count 0 2006.285.07:35:26.00#ibcon#about to read 4, iclass 25, count 0 2006.285.07:35:26.00#ibcon#read 4, iclass 25, count 0 2006.285.07:35:26.00#ibcon#about to read 5, iclass 25, count 0 2006.285.07:35:26.00#ibcon#read 5, iclass 25, count 0 2006.285.07:35:26.00#ibcon#about to read 6, iclass 25, count 0 2006.285.07:35:26.00#ibcon#read 6, iclass 25, count 0 2006.285.07:35:26.00#ibcon#end of sib2, iclass 25, count 0 2006.285.07:35:26.00#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:35:26.00#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:35:26.00#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:35:26.00#ibcon#*before write, iclass 25, count 0 2006.285.07:35:26.00#ibcon#enter sib2, iclass 25, count 0 2006.285.07:35:26.00#ibcon#flushed, iclass 25, count 0 2006.285.07:35:26.00#ibcon#about to write, iclass 25, count 0 2006.285.07:35:26.00#ibcon#wrote, iclass 25, count 0 2006.285.07:35:26.00#ibcon#about to read 3, iclass 25, count 0 2006.285.07:35:26.04#ibcon#read 3, iclass 25, count 0 2006.285.07:35:26.04#ibcon#about to read 4, iclass 25, count 0 2006.285.07:35:26.04#ibcon#read 4, iclass 25, count 0 2006.285.07:35:26.04#ibcon#about to read 5, iclass 25, count 0 2006.285.07:35:26.04#ibcon#read 5, iclass 25, count 0 2006.285.07:35:26.04#ibcon#about to read 6, iclass 25, count 0 2006.285.07:35:26.04#ibcon#read 6, iclass 25, count 0 2006.285.07:35:26.04#ibcon#end of sib2, iclass 25, count 0 2006.285.07:35:26.04#ibcon#*after write, iclass 25, count 0 2006.285.07:35:26.04#ibcon#*before return 0, iclass 25, count 0 2006.285.07:35:26.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:35:26.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:35:26.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:35:26.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:35:26.04$vck44/va=4,6 2006.285.07:35:26.04#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.07:35:26.04#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.07:35:26.04#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:26.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:35:26.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:35:26.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:35:26.10#ibcon#enter wrdev, iclass 27, count 2 2006.285.07:35:26.10#ibcon#first serial, iclass 27, count 2 2006.285.07:35:26.10#ibcon#enter sib2, iclass 27, count 2 2006.285.07:35:26.10#ibcon#flushed, iclass 27, count 2 2006.285.07:35:26.10#ibcon#about to write, iclass 27, count 2 2006.285.07:35:26.10#ibcon#wrote, iclass 27, count 2 2006.285.07:35:26.10#ibcon#about to read 3, iclass 27, count 2 2006.285.07:35:26.12#ibcon#read 3, iclass 27, count 2 2006.285.07:35:26.12#ibcon#about to read 4, iclass 27, count 2 2006.285.07:35:26.12#ibcon#read 4, iclass 27, count 2 2006.285.07:35:26.12#ibcon#about to read 5, iclass 27, count 2 2006.285.07:35:26.12#ibcon#read 5, iclass 27, count 2 2006.285.07:35:26.12#ibcon#about to read 6, iclass 27, count 2 2006.285.07:35:26.12#ibcon#read 6, iclass 27, count 2 2006.285.07:35:26.12#ibcon#end of sib2, iclass 27, count 2 2006.285.07:35:26.12#ibcon#*mode == 0, iclass 27, count 2 2006.285.07:35:26.12#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.07:35:26.12#ibcon#[25=AT04-06\r\n] 2006.285.07:35:26.12#ibcon#*before write, iclass 27, count 2 2006.285.07:35:26.12#ibcon#enter sib2, iclass 27, count 2 2006.285.07:35:26.12#ibcon#flushed, iclass 27, count 2 2006.285.07:35:26.12#ibcon#about to write, iclass 27, count 2 2006.285.07:35:26.12#ibcon#wrote, iclass 27, count 2 2006.285.07:35:26.12#ibcon#about to read 3, iclass 27, count 2 2006.285.07:35:26.15#ibcon#read 3, iclass 27, count 2 2006.285.07:35:26.15#ibcon#about to read 4, iclass 27, count 2 2006.285.07:35:26.15#ibcon#read 4, iclass 27, count 2 2006.285.07:35:26.15#ibcon#about to read 5, iclass 27, count 2 2006.285.07:35:26.15#ibcon#read 5, iclass 27, count 2 2006.285.07:35:26.15#ibcon#about to read 6, iclass 27, count 2 2006.285.07:35:26.15#ibcon#read 6, iclass 27, count 2 2006.285.07:35:26.15#ibcon#end of sib2, iclass 27, count 2 2006.285.07:35:26.15#ibcon#*after write, iclass 27, count 2 2006.285.07:35:26.15#ibcon#*before return 0, iclass 27, count 2 2006.285.07:35:26.15#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:35:26.15#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:35:26.15#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.07:35:26.15#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:26.15#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:35:26.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:35:26.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:35:26.27#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:35:26.27#ibcon#first serial, iclass 27, count 0 2006.285.07:35:26.27#ibcon#enter sib2, iclass 27, count 0 2006.285.07:35:26.27#ibcon#flushed, iclass 27, count 0 2006.285.07:35:26.27#ibcon#about to write, iclass 27, count 0 2006.285.07:35:26.27#ibcon#wrote, iclass 27, count 0 2006.285.07:35:26.27#ibcon#about to read 3, iclass 27, count 0 2006.285.07:35:26.29#ibcon#read 3, iclass 27, count 0 2006.285.07:35:26.29#ibcon#about to read 4, iclass 27, count 0 2006.285.07:35:26.29#ibcon#read 4, iclass 27, count 0 2006.285.07:35:26.29#ibcon#about to read 5, iclass 27, count 0 2006.285.07:35:26.29#ibcon#read 5, iclass 27, count 0 2006.285.07:35:26.29#ibcon#about to read 6, iclass 27, count 0 2006.285.07:35:26.29#ibcon#read 6, iclass 27, count 0 2006.285.07:35:26.29#ibcon#end of sib2, iclass 27, count 0 2006.285.07:35:26.29#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:35:26.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:35:26.29#ibcon#[25=USB\r\n] 2006.285.07:35:26.29#ibcon#*before write, iclass 27, count 0 2006.285.07:35:26.29#ibcon#enter sib2, iclass 27, count 0 2006.285.07:35:26.29#ibcon#flushed, iclass 27, count 0 2006.285.07:35:26.29#ibcon#about to write, iclass 27, count 0 2006.285.07:35:26.29#ibcon#wrote, iclass 27, count 0 2006.285.07:35:26.29#ibcon#about to read 3, iclass 27, count 0 2006.285.07:35:26.32#ibcon#read 3, iclass 27, count 0 2006.285.07:35:26.32#ibcon#about to read 4, iclass 27, count 0 2006.285.07:35:26.32#ibcon#read 4, iclass 27, count 0 2006.285.07:35:26.32#ibcon#about to read 5, iclass 27, count 0 2006.285.07:35:26.32#ibcon#read 5, iclass 27, count 0 2006.285.07:35:26.32#ibcon#about to read 6, iclass 27, count 0 2006.285.07:35:26.32#ibcon#read 6, iclass 27, count 0 2006.285.07:35:26.32#ibcon#end of sib2, iclass 27, count 0 2006.285.07:35:26.32#ibcon#*after write, iclass 27, count 0 2006.285.07:35:26.32#ibcon#*before return 0, iclass 27, count 0 2006.285.07:35:26.32#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:35:26.32#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:35:26.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:35:26.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:35:26.32$vck44/valo=5,734.99 2006.285.07:35:26.32#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.07:35:26.32#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.07:35:26.32#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:26.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:35:26.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:35:26.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:35:26.32#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:35:26.32#ibcon#first serial, iclass 29, count 0 2006.285.07:35:26.32#ibcon#enter sib2, iclass 29, count 0 2006.285.07:35:26.32#ibcon#flushed, iclass 29, count 0 2006.285.07:35:26.32#ibcon#about to write, iclass 29, count 0 2006.285.07:35:26.32#ibcon#wrote, iclass 29, count 0 2006.285.07:35:26.32#ibcon#about to read 3, iclass 29, count 0 2006.285.07:35:26.34#ibcon#read 3, iclass 29, count 0 2006.285.07:35:26.34#ibcon#about to read 4, iclass 29, count 0 2006.285.07:35:26.34#ibcon#read 4, iclass 29, count 0 2006.285.07:35:26.34#ibcon#about to read 5, iclass 29, count 0 2006.285.07:35:26.34#ibcon#read 5, iclass 29, count 0 2006.285.07:35:26.34#ibcon#about to read 6, iclass 29, count 0 2006.285.07:35:26.34#ibcon#read 6, iclass 29, count 0 2006.285.07:35:26.34#ibcon#end of sib2, iclass 29, count 0 2006.285.07:35:26.34#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:35:26.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:35:26.34#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:35:26.34#ibcon#*before write, iclass 29, count 0 2006.285.07:35:26.34#ibcon#enter sib2, iclass 29, count 0 2006.285.07:35:26.34#ibcon#flushed, iclass 29, count 0 2006.285.07:35:26.34#ibcon#about to write, iclass 29, count 0 2006.285.07:35:26.34#ibcon#wrote, iclass 29, count 0 2006.285.07:35:26.34#ibcon#about to read 3, iclass 29, count 0 2006.285.07:35:26.38#ibcon#read 3, iclass 29, count 0 2006.285.07:35:26.38#ibcon#about to read 4, iclass 29, count 0 2006.285.07:35:26.38#ibcon#read 4, iclass 29, count 0 2006.285.07:35:26.38#ibcon#about to read 5, iclass 29, count 0 2006.285.07:35:26.38#ibcon#read 5, iclass 29, count 0 2006.285.07:35:26.38#ibcon#about to read 6, iclass 29, count 0 2006.285.07:35:26.38#ibcon#read 6, iclass 29, count 0 2006.285.07:35:26.38#ibcon#end of sib2, iclass 29, count 0 2006.285.07:35:26.38#ibcon#*after write, iclass 29, count 0 2006.285.07:35:26.38#ibcon#*before return 0, iclass 29, count 0 2006.285.07:35:26.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:35:26.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:35:26.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:35:26.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:35:26.38$vck44/va=5,3 2006.285.07:35:26.38#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.07:35:26.38#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.07:35:26.38#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:26.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:35:26.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:35:26.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:35:26.44#ibcon#enter wrdev, iclass 31, count 2 2006.285.07:35:26.44#ibcon#first serial, iclass 31, count 2 2006.285.07:35:26.44#ibcon#enter sib2, iclass 31, count 2 2006.285.07:35:26.44#ibcon#flushed, iclass 31, count 2 2006.285.07:35:26.44#ibcon#about to write, iclass 31, count 2 2006.285.07:35:26.44#ibcon#wrote, iclass 31, count 2 2006.285.07:35:26.44#ibcon#about to read 3, iclass 31, count 2 2006.285.07:35:26.46#ibcon#read 3, iclass 31, count 2 2006.285.07:35:26.46#ibcon#about to read 4, iclass 31, count 2 2006.285.07:35:26.46#ibcon#read 4, iclass 31, count 2 2006.285.07:35:26.46#ibcon#about to read 5, iclass 31, count 2 2006.285.07:35:26.46#ibcon#read 5, iclass 31, count 2 2006.285.07:35:26.46#ibcon#about to read 6, iclass 31, count 2 2006.285.07:35:26.46#ibcon#read 6, iclass 31, count 2 2006.285.07:35:26.46#ibcon#end of sib2, iclass 31, count 2 2006.285.07:35:26.46#ibcon#*mode == 0, iclass 31, count 2 2006.285.07:35:26.46#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.07:35:26.46#ibcon#[25=AT05-03\r\n] 2006.285.07:35:26.46#ibcon#*before write, iclass 31, count 2 2006.285.07:35:26.46#ibcon#enter sib2, iclass 31, count 2 2006.285.07:35:26.46#ibcon#flushed, iclass 31, count 2 2006.285.07:35:26.46#ibcon#about to write, iclass 31, count 2 2006.285.07:35:26.46#ibcon#wrote, iclass 31, count 2 2006.285.07:35:26.46#ibcon#about to read 3, iclass 31, count 2 2006.285.07:35:26.49#ibcon#read 3, iclass 31, count 2 2006.285.07:35:26.49#ibcon#about to read 4, iclass 31, count 2 2006.285.07:35:26.49#ibcon#read 4, iclass 31, count 2 2006.285.07:35:26.49#ibcon#about to read 5, iclass 31, count 2 2006.285.07:35:26.49#ibcon#read 5, iclass 31, count 2 2006.285.07:35:26.49#ibcon#about to read 6, iclass 31, count 2 2006.285.07:35:26.49#ibcon#read 6, iclass 31, count 2 2006.285.07:35:26.49#ibcon#end of sib2, iclass 31, count 2 2006.285.07:35:26.49#ibcon#*after write, iclass 31, count 2 2006.285.07:35:26.49#ibcon#*before return 0, iclass 31, count 2 2006.285.07:35:26.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:35:26.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:35:26.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.07:35:26.49#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:26.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:35:26.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:35:26.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:35:26.61#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:35:26.61#ibcon#first serial, iclass 31, count 0 2006.285.07:35:26.61#ibcon#enter sib2, iclass 31, count 0 2006.285.07:35:26.61#ibcon#flushed, iclass 31, count 0 2006.285.07:35:26.61#ibcon#about to write, iclass 31, count 0 2006.285.07:35:26.61#ibcon#wrote, iclass 31, count 0 2006.285.07:35:26.61#ibcon#about to read 3, iclass 31, count 0 2006.285.07:35:26.63#ibcon#read 3, iclass 31, count 0 2006.285.07:35:26.63#ibcon#about to read 4, iclass 31, count 0 2006.285.07:35:26.63#ibcon#read 4, iclass 31, count 0 2006.285.07:35:26.63#ibcon#about to read 5, iclass 31, count 0 2006.285.07:35:26.63#ibcon#read 5, iclass 31, count 0 2006.285.07:35:26.63#ibcon#about to read 6, iclass 31, count 0 2006.285.07:35:26.63#ibcon#read 6, iclass 31, count 0 2006.285.07:35:26.63#ibcon#end of sib2, iclass 31, count 0 2006.285.07:35:26.63#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:35:26.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:35:26.63#ibcon#[25=USB\r\n] 2006.285.07:35:26.63#ibcon#*before write, iclass 31, count 0 2006.285.07:35:26.63#ibcon#enter sib2, iclass 31, count 0 2006.285.07:35:26.63#ibcon#flushed, iclass 31, count 0 2006.285.07:35:26.63#ibcon#about to write, iclass 31, count 0 2006.285.07:35:26.63#ibcon#wrote, iclass 31, count 0 2006.285.07:35:26.63#ibcon#about to read 3, iclass 31, count 0 2006.285.07:35:26.66#ibcon#read 3, iclass 31, count 0 2006.285.07:35:26.66#ibcon#about to read 4, iclass 31, count 0 2006.285.07:35:26.66#ibcon#read 4, iclass 31, count 0 2006.285.07:35:26.66#ibcon#about to read 5, iclass 31, count 0 2006.285.07:35:26.66#ibcon#read 5, iclass 31, count 0 2006.285.07:35:26.66#ibcon#about to read 6, iclass 31, count 0 2006.285.07:35:26.66#ibcon#read 6, iclass 31, count 0 2006.285.07:35:26.66#ibcon#end of sib2, iclass 31, count 0 2006.285.07:35:26.66#ibcon#*after write, iclass 31, count 0 2006.285.07:35:26.66#ibcon#*before return 0, iclass 31, count 0 2006.285.07:35:26.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:35:26.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:35:26.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:35:26.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:35:26.66$vck44/valo=6,814.99 2006.285.07:35:26.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.07:35:26.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.07:35:26.66#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:26.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:35:26.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:35:26.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:35:26.66#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:35:26.66#ibcon#first serial, iclass 33, count 0 2006.285.07:35:26.66#ibcon#enter sib2, iclass 33, count 0 2006.285.07:35:26.66#ibcon#flushed, iclass 33, count 0 2006.285.07:35:26.66#ibcon#about to write, iclass 33, count 0 2006.285.07:35:26.66#ibcon#wrote, iclass 33, count 0 2006.285.07:35:26.66#ibcon#about to read 3, iclass 33, count 0 2006.285.07:35:26.68#ibcon#read 3, iclass 33, count 0 2006.285.07:35:26.68#ibcon#about to read 4, iclass 33, count 0 2006.285.07:35:26.68#ibcon#read 4, iclass 33, count 0 2006.285.07:35:26.68#ibcon#about to read 5, iclass 33, count 0 2006.285.07:35:26.68#ibcon#read 5, iclass 33, count 0 2006.285.07:35:26.68#ibcon#about to read 6, iclass 33, count 0 2006.285.07:35:26.68#ibcon#read 6, iclass 33, count 0 2006.285.07:35:26.68#ibcon#end of sib2, iclass 33, count 0 2006.285.07:35:26.68#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:35:26.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:35:26.68#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:35:26.68#ibcon#*before write, iclass 33, count 0 2006.285.07:35:26.68#ibcon#enter sib2, iclass 33, count 0 2006.285.07:35:26.68#ibcon#flushed, iclass 33, count 0 2006.285.07:35:26.68#ibcon#about to write, iclass 33, count 0 2006.285.07:35:26.68#ibcon#wrote, iclass 33, count 0 2006.285.07:35:26.68#ibcon#about to read 3, iclass 33, count 0 2006.285.07:35:26.72#ibcon#read 3, iclass 33, count 0 2006.285.07:35:26.72#ibcon#about to read 4, iclass 33, count 0 2006.285.07:35:26.72#ibcon#read 4, iclass 33, count 0 2006.285.07:35:26.72#ibcon#about to read 5, iclass 33, count 0 2006.285.07:35:26.72#ibcon#read 5, iclass 33, count 0 2006.285.07:35:26.72#ibcon#about to read 6, iclass 33, count 0 2006.285.07:35:26.72#ibcon#read 6, iclass 33, count 0 2006.285.07:35:26.72#ibcon#end of sib2, iclass 33, count 0 2006.285.07:35:26.72#ibcon#*after write, iclass 33, count 0 2006.285.07:35:26.72#ibcon#*before return 0, iclass 33, count 0 2006.285.07:35:26.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:35:26.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:35:26.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:35:26.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:35:26.72$vck44/va=6,4 2006.285.07:35:26.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.07:35:26.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.07:35:26.72#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:26.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:35:26.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:35:26.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:35:26.78#ibcon#enter wrdev, iclass 35, count 2 2006.285.07:35:26.78#ibcon#first serial, iclass 35, count 2 2006.285.07:35:26.78#ibcon#enter sib2, iclass 35, count 2 2006.285.07:35:26.78#ibcon#flushed, iclass 35, count 2 2006.285.07:35:26.78#ibcon#about to write, iclass 35, count 2 2006.285.07:35:26.78#ibcon#wrote, iclass 35, count 2 2006.285.07:35:26.78#ibcon#about to read 3, iclass 35, count 2 2006.285.07:35:26.80#ibcon#read 3, iclass 35, count 2 2006.285.07:35:26.80#ibcon#about to read 4, iclass 35, count 2 2006.285.07:35:26.80#ibcon#read 4, iclass 35, count 2 2006.285.07:35:26.80#ibcon#about to read 5, iclass 35, count 2 2006.285.07:35:26.80#ibcon#read 5, iclass 35, count 2 2006.285.07:35:26.80#ibcon#about to read 6, iclass 35, count 2 2006.285.07:35:26.80#ibcon#read 6, iclass 35, count 2 2006.285.07:35:26.80#ibcon#end of sib2, iclass 35, count 2 2006.285.07:35:26.80#ibcon#*mode == 0, iclass 35, count 2 2006.285.07:35:26.80#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.07:35:26.80#ibcon#[25=AT06-04\r\n] 2006.285.07:35:26.80#ibcon#*before write, iclass 35, count 2 2006.285.07:35:26.80#ibcon#enter sib2, iclass 35, count 2 2006.285.07:35:26.80#ibcon#flushed, iclass 35, count 2 2006.285.07:35:26.80#ibcon#about to write, iclass 35, count 2 2006.285.07:35:26.80#ibcon#wrote, iclass 35, count 2 2006.285.07:35:26.80#ibcon#about to read 3, iclass 35, count 2 2006.285.07:35:26.83#ibcon#read 3, iclass 35, count 2 2006.285.07:35:26.83#ibcon#about to read 4, iclass 35, count 2 2006.285.07:35:26.83#ibcon#read 4, iclass 35, count 2 2006.285.07:35:26.83#ibcon#about to read 5, iclass 35, count 2 2006.285.07:35:26.83#ibcon#read 5, iclass 35, count 2 2006.285.07:35:26.83#ibcon#about to read 6, iclass 35, count 2 2006.285.07:35:26.83#ibcon#read 6, iclass 35, count 2 2006.285.07:35:26.83#ibcon#end of sib2, iclass 35, count 2 2006.285.07:35:26.83#ibcon#*after write, iclass 35, count 2 2006.285.07:35:26.83#ibcon#*before return 0, iclass 35, count 2 2006.285.07:35:26.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:35:26.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:35:26.83#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.07:35:26.83#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:26.83#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:35:26.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:35:26.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:35:26.95#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:35:26.95#ibcon#first serial, iclass 35, count 0 2006.285.07:35:26.95#ibcon#enter sib2, iclass 35, count 0 2006.285.07:35:26.95#ibcon#flushed, iclass 35, count 0 2006.285.07:35:26.95#ibcon#about to write, iclass 35, count 0 2006.285.07:35:26.95#ibcon#wrote, iclass 35, count 0 2006.285.07:35:26.95#ibcon#about to read 3, iclass 35, count 0 2006.285.07:35:26.97#ibcon#read 3, iclass 35, count 0 2006.285.07:35:26.97#ibcon#about to read 4, iclass 35, count 0 2006.285.07:35:26.97#ibcon#read 4, iclass 35, count 0 2006.285.07:35:26.97#ibcon#about to read 5, iclass 35, count 0 2006.285.07:35:26.97#ibcon#read 5, iclass 35, count 0 2006.285.07:35:26.97#ibcon#about to read 6, iclass 35, count 0 2006.285.07:35:26.97#ibcon#read 6, iclass 35, count 0 2006.285.07:35:26.97#ibcon#end of sib2, iclass 35, count 0 2006.285.07:35:26.97#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:35:26.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:35:26.97#ibcon#[25=USB\r\n] 2006.285.07:35:26.97#ibcon#*before write, iclass 35, count 0 2006.285.07:35:26.97#ibcon#enter sib2, iclass 35, count 0 2006.285.07:35:26.97#ibcon#flushed, iclass 35, count 0 2006.285.07:35:26.97#ibcon#about to write, iclass 35, count 0 2006.285.07:35:26.97#ibcon#wrote, iclass 35, count 0 2006.285.07:35:26.97#ibcon#about to read 3, iclass 35, count 0 2006.285.07:35:27.00#ibcon#read 3, iclass 35, count 0 2006.285.07:35:27.00#ibcon#about to read 4, iclass 35, count 0 2006.285.07:35:27.00#ibcon#read 4, iclass 35, count 0 2006.285.07:35:27.00#ibcon#about to read 5, iclass 35, count 0 2006.285.07:35:27.00#ibcon#read 5, iclass 35, count 0 2006.285.07:35:27.00#ibcon#about to read 6, iclass 35, count 0 2006.285.07:35:27.00#ibcon#read 6, iclass 35, count 0 2006.285.07:35:27.00#ibcon#end of sib2, iclass 35, count 0 2006.285.07:35:27.00#ibcon#*after write, iclass 35, count 0 2006.285.07:35:27.00#ibcon#*before return 0, iclass 35, count 0 2006.285.07:35:27.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:35:27.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:35:27.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:35:27.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:35:27.00$vck44/valo=7,864.99 2006.285.07:35:27.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.07:35:27.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.07:35:27.00#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:27.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:35:27.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:35:27.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:35:27.00#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:35:27.00#ibcon#first serial, iclass 37, count 0 2006.285.07:35:27.00#ibcon#enter sib2, iclass 37, count 0 2006.285.07:35:27.00#ibcon#flushed, iclass 37, count 0 2006.285.07:35:27.00#ibcon#about to write, iclass 37, count 0 2006.285.07:35:27.00#ibcon#wrote, iclass 37, count 0 2006.285.07:35:27.00#ibcon#about to read 3, iclass 37, count 0 2006.285.07:35:27.02#ibcon#read 3, iclass 37, count 0 2006.285.07:35:27.02#ibcon#about to read 4, iclass 37, count 0 2006.285.07:35:27.02#ibcon#read 4, iclass 37, count 0 2006.285.07:35:27.02#ibcon#about to read 5, iclass 37, count 0 2006.285.07:35:27.02#ibcon#read 5, iclass 37, count 0 2006.285.07:35:27.02#ibcon#about to read 6, iclass 37, count 0 2006.285.07:35:27.02#ibcon#read 6, iclass 37, count 0 2006.285.07:35:27.02#ibcon#end of sib2, iclass 37, count 0 2006.285.07:35:27.02#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:35:27.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:35:27.02#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:35:27.02#ibcon#*before write, iclass 37, count 0 2006.285.07:35:27.02#ibcon#enter sib2, iclass 37, count 0 2006.285.07:35:27.02#ibcon#flushed, iclass 37, count 0 2006.285.07:35:27.02#ibcon#about to write, iclass 37, count 0 2006.285.07:35:27.02#ibcon#wrote, iclass 37, count 0 2006.285.07:35:27.02#ibcon#about to read 3, iclass 37, count 0 2006.285.07:35:27.06#ibcon#read 3, iclass 37, count 0 2006.285.07:35:27.06#ibcon#about to read 4, iclass 37, count 0 2006.285.07:35:27.06#ibcon#read 4, iclass 37, count 0 2006.285.07:35:27.06#ibcon#about to read 5, iclass 37, count 0 2006.285.07:35:27.06#ibcon#read 5, iclass 37, count 0 2006.285.07:35:27.06#ibcon#about to read 6, iclass 37, count 0 2006.285.07:35:27.06#ibcon#read 6, iclass 37, count 0 2006.285.07:35:27.06#ibcon#end of sib2, iclass 37, count 0 2006.285.07:35:27.06#ibcon#*after write, iclass 37, count 0 2006.285.07:35:27.06#ibcon#*before return 0, iclass 37, count 0 2006.285.07:35:27.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:35:27.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:35:27.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:35:27.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:35:27.06$vck44/va=7,4 2006.285.07:35:27.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.07:35:27.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.07:35:27.06#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:27.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:35:27.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:35:27.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:35:27.12#ibcon#enter wrdev, iclass 39, count 2 2006.285.07:35:27.12#ibcon#first serial, iclass 39, count 2 2006.285.07:35:27.12#ibcon#enter sib2, iclass 39, count 2 2006.285.07:35:27.12#ibcon#flushed, iclass 39, count 2 2006.285.07:35:27.12#ibcon#about to write, iclass 39, count 2 2006.285.07:35:27.12#ibcon#wrote, iclass 39, count 2 2006.285.07:35:27.12#ibcon#about to read 3, iclass 39, count 2 2006.285.07:35:27.14#ibcon#read 3, iclass 39, count 2 2006.285.07:35:27.14#ibcon#about to read 4, iclass 39, count 2 2006.285.07:35:27.14#ibcon#read 4, iclass 39, count 2 2006.285.07:35:27.14#ibcon#about to read 5, iclass 39, count 2 2006.285.07:35:27.14#ibcon#read 5, iclass 39, count 2 2006.285.07:35:27.14#ibcon#about to read 6, iclass 39, count 2 2006.285.07:35:27.14#ibcon#read 6, iclass 39, count 2 2006.285.07:35:27.14#ibcon#end of sib2, iclass 39, count 2 2006.285.07:35:27.14#ibcon#*mode == 0, iclass 39, count 2 2006.285.07:35:27.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.07:35:27.14#ibcon#[25=AT07-04\r\n] 2006.285.07:35:27.14#ibcon#*before write, iclass 39, count 2 2006.285.07:35:27.14#ibcon#enter sib2, iclass 39, count 2 2006.285.07:35:27.14#ibcon#flushed, iclass 39, count 2 2006.285.07:35:27.14#ibcon#about to write, iclass 39, count 2 2006.285.07:35:27.14#ibcon#wrote, iclass 39, count 2 2006.285.07:35:27.14#ibcon#about to read 3, iclass 39, count 2 2006.285.07:35:27.17#ibcon#read 3, iclass 39, count 2 2006.285.07:35:27.17#ibcon#about to read 4, iclass 39, count 2 2006.285.07:35:27.17#ibcon#read 4, iclass 39, count 2 2006.285.07:35:27.17#ibcon#about to read 5, iclass 39, count 2 2006.285.07:35:27.17#ibcon#read 5, iclass 39, count 2 2006.285.07:35:27.17#ibcon#about to read 6, iclass 39, count 2 2006.285.07:35:27.17#ibcon#read 6, iclass 39, count 2 2006.285.07:35:27.17#ibcon#end of sib2, iclass 39, count 2 2006.285.07:35:27.17#ibcon#*after write, iclass 39, count 2 2006.285.07:35:27.17#ibcon#*before return 0, iclass 39, count 2 2006.285.07:35:27.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:35:27.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:35:27.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.07:35:27.17#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:27.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:35:27.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:35:27.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:35:27.29#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:35:27.29#ibcon#first serial, iclass 39, count 0 2006.285.07:35:27.29#ibcon#enter sib2, iclass 39, count 0 2006.285.07:35:27.29#ibcon#flushed, iclass 39, count 0 2006.285.07:35:27.29#ibcon#about to write, iclass 39, count 0 2006.285.07:35:27.29#ibcon#wrote, iclass 39, count 0 2006.285.07:35:27.29#ibcon#about to read 3, iclass 39, count 0 2006.285.07:35:27.31#ibcon#read 3, iclass 39, count 0 2006.285.07:35:27.31#ibcon#about to read 4, iclass 39, count 0 2006.285.07:35:27.31#ibcon#read 4, iclass 39, count 0 2006.285.07:35:27.31#ibcon#about to read 5, iclass 39, count 0 2006.285.07:35:27.31#ibcon#read 5, iclass 39, count 0 2006.285.07:35:27.31#ibcon#about to read 6, iclass 39, count 0 2006.285.07:35:27.31#ibcon#read 6, iclass 39, count 0 2006.285.07:35:27.31#ibcon#end of sib2, iclass 39, count 0 2006.285.07:35:27.31#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:35:27.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:35:27.31#ibcon#[25=USB\r\n] 2006.285.07:35:27.31#ibcon#*before write, iclass 39, count 0 2006.285.07:35:27.31#ibcon#enter sib2, iclass 39, count 0 2006.285.07:35:27.31#ibcon#flushed, iclass 39, count 0 2006.285.07:35:27.31#ibcon#about to write, iclass 39, count 0 2006.285.07:35:27.31#ibcon#wrote, iclass 39, count 0 2006.285.07:35:27.31#ibcon#about to read 3, iclass 39, count 0 2006.285.07:35:27.34#ibcon#read 3, iclass 39, count 0 2006.285.07:35:27.34#ibcon#about to read 4, iclass 39, count 0 2006.285.07:35:27.34#ibcon#read 4, iclass 39, count 0 2006.285.07:35:27.34#ibcon#about to read 5, iclass 39, count 0 2006.285.07:35:27.34#ibcon#read 5, iclass 39, count 0 2006.285.07:35:27.34#ibcon#about to read 6, iclass 39, count 0 2006.285.07:35:27.34#ibcon#read 6, iclass 39, count 0 2006.285.07:35:27.34#ibcon#end of sib2, iclass 39, count 0 2006.285.07:35:27.34#ibcon#*after write, iclass 39, count 0 2006.285.07:35:27.34#ibcon#*before return 0, iclass 39, count 0 2006.285.07:35:27.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:35:27.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:35:27.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:35:27.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:35:27.34$vck44/valo=8,884.99 2006.285.07:35:27.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.07:35:27.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.07:35:27.34#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:27.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:35:27.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:35:27.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:35:27.34#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:35:27.34#ibcon#first serial, iclass 3, count 0 2006.285.07:35:27.34#ibcon#enter sib2, iclass 3, count 0 2006.285.07:35:27.34#ibcon#flushed, iclass 3, count 0 2006.285.07:35:27.34#ibcon#about to write, iclass 3, count 0 2006.285.07:35:27.34#ibcon#wrote, iclass 3, count 0 2006.285.07:35:27.34#ibcon#about to read 3, iclass 3, count 0 2006.285.07:35:27.36#ibcon#read 3, iclass 3, count 0 2006.285.07:35:27.36#ibcon#about to read 4, iclass 3, count 0 2006.285.07:35:27.36#ibcon#read 4, iclass 3, count 0 2006.285.07:35:27.36#ibcon#about to read 5, iclass 3, count 0 2006.285.07:35:27.36#ibcon#read 5, iclass 3, count 0 2006.285.07:35:27.36#ibcon#about to read 6, iclass 3, count 0 2006.285.07:35:27.36#ibcon#read 6, iclass 3, count 0 2006.285.07:35:27.36#ibcon#end of sib2, iclass 3, count 0 2006.285.07:35:27.36#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:35:27.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:35:27.36#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:35:27.36#ibcon#*before write, iclass 3, count 0 2006.285.07:35:27.36#ibcon#enter sib2, iclass 3, count 0 2006.285.07:35:27.36#ibcon#flushed, iclass 3, count 0 2006.285.07:35:27.36#ibcon#about to write, iclass 3, count 0 2006.285.07:35:27.36#ibcon#wrote, iclass 3, count 0 2006.285.07:35:27.36#ibcon#about to read 3, iclass 3, count 0 2006.285.07:35:27.40#ibcon#read 3, iclass 3, count 0 2006.285.07:35:27.40#ibcon#about to read 4, iclass 3, count 0 2006.285.07:35:27.40#ibcon#read 4, iclass 3, count 0 2006.285.07:35:27.40#ibcon#about to read 5, iclass 3, count 0 2006.285.07:35:27.40#ibcon#read 5, iclass 3, count 0 2006.285.07:35:27.40#ibcon#about to read 6, iclass 3, count 0 2006.285.07:35:27.40#ibcon#read 6, iclass 3, count 0 2006.285.07:35:27.40#ibcon#end of sib2, iclass 3, count 0 2006.285.07:35:27.40#ibcon#*after write, iclass 3, count 0 2006.285.07:35:27.40#ibcon#*before return 0, iclass 3, count 0 2006.285.07:35:27.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:35:27.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:35:27.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:35:27.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:35:27.40$vck44/va=8,3 2006.285.07:35:27.40#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.07:35:27.40#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.07:35:27.40#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:27.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:35:27.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:35:27.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:35:27.46#ibcon#enter wrdev, iclass 5, count 2 2006.285.07:35:27.46#ibcon#first serial, iclass 5, count 2 2006.285.07:35:27.46#ibcon#enter sib2, iclass 5, count 2 2006.285.07:35:27.46#ibcon#flushed, iclass 5, count 2 2006.285.07:35:27.46#ibcon#about to write, iclass 5, count 2 2006.285.07:35:27.46#ibcon#wrote, iclass 5, count 2 2006.285.07:35:27.46#ibcon#about to read 3, iclass 5, count 2 2006.285.07:35:27.48#ibcon#read 3, iclass 5, count 2 2006.285.07:35:27.48#ibcon#about to read 4, iclass 5, count 2 2006.285.07:35:27.48#ibcon#read 4, iclass 5, count 2 2006.285.07:35:27.48#ibcon#about to read 5, iclass 5, count 2 2006.285.07:35:27.48#ibcon#read 5, iclass 5, count 2 2006.285.07:35:27.48#ibcon#about to read 6, iclass 5, count 2 2006.285.07:35:27.48#ibcon#read 6, iclass 5, count 2 2006.285.07:35:27.48#ibcon#end of sib2, iclass 5, count 2 2006.285.07:35:27.48#ibcon#*mode == 0, iclass 5, count 2 2006.285.07:35:27.48#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.07:35:27.48#ibcon#[25=AT08-03\r\n] 2006.285.07:35:27.48#ibcon#*before write, iclass 5, count 2 2006.285.07:35:27.48#ibcon#enter sib2, iclass 5, count 2 2006.285.07:35:27.48#ibcon#flushed, iclass 5, count 2 2006.285.07:35:27.48#ibcon#about to write, iclass 5, count 2 2006.285.07:35:27.48#ibcon#wrote, iclass 5, count 2 2006.285.07:35:27.48#ibcon#about to read 3, iclass 5, count 2 2006.285.07:35:27.51#ibcon#read 3, iclass 5, count 2 2006.285.07:35:27.51#ibcon#about to read 4, iclass 5, count 2 2006.285.07:35:27.51#ibcon#read 4, iclass 5, count 2 2006.285.07:35:27.51#ibcon#about to read 5, iclass 5, count 2 2006.285.07:35:27.51#ibcon#read 5, iclass 5, count 2 2006.285.07:35:27.51#ibcon#about to read 6, iclass 5, count 2 2006.285.07:35:27.51#ibcon#read 6, iclass 5, count 2 2006.285.07:35:27.51#ibcon#end of sib2, iclass 5, count 2 2006.285.07:35:27.51#ibcon#*after write, iclass 5, count 2 2006.285.07:35:27.51#ibcon#*before return 0, iclass 5, count 2 2006.285.07:35:27.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:35:27.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:35:27.51#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.07:35:27.51#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:27.51#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:35:27.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:35:27.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:35:27.63#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:35:27.63#ibcon#first serial, iclass 5, count 0 2006.285.07:35:27.63#ibcon#enter sib2, iclass 5, count 0 2006.285.07:35:27.63#ibcon#flushed, iclass 5, count 0 2006.285.07:35:27.63#ibcon#about to write, iclass 5, count 0 2006.285.07:35:27.63#ibcon#wrote, iclass 5, count 0 2006.285.07:35:27.63#ibcon#about to read 3, iclass 5, count 0 2006.285.07:35:27.65#ibcon#read 3, iclass 5, count 0 2006.285.07:35:27.65#ibcon#about to read 4, iclass 5, count 0 2006.285.07:35:27.65#ibcon#read 4, iclass 5, count 0 2006.285.07:35:27.65#ibcon#about to read 5, iclass 5, count 0 2006.285.07:35:27.65#ibcon#read 5, iclass 5, count 0 2006.285.07:35:27.65#ibcon#about to read 6, iclass 5, count 0 2006.285.07:35:27.65#ibcon#read 6, iclass 5, count 0 2006.285.07:35:27.65#ibcon#end of sib2, iclass 5, count 0 2006.285.07:35:27.65#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:35:27.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:35:27.65#ibcon#[25=USB\r\n] 2006.285.07:35:27.65#ibcon#*before write, iclass 5, count 0 2006.285.07:35:27.65#ibcon#enter sib2, iclass 5, count 0 2006.285.07:35:27.65#ibcon#flushed, iclass 5, count 0 2006.285.07:35:27.65#ibcon#about to write, iclass 5, count 0 2006.285.07:35:27.65#ibcon#wrote, iclass 5, count 0 2006.285.07:35:27.65#ibcon#about to read 3, iclass 5, count 0 2006.285.07:35:27.68#ibcon#read 3, iclass 5, count 0 2006.285.07:35:27.68#ibcon#about to read 4, iclass 5, count 0 2006.285.07:35:27.68#ibcon#read 4, iclass 5, count 0 2006.285.07:35:27.68#ibcon#about to read 5, iclass 5, count 0 2006.285.07:35:27.68#ibcon#read 5, iclass 5, count 0 2006.285.07:35:27.68#ibcon#about to read 6, iclass 5, count 0 2006.285.07:35:27.68#ibcon#read 6, iclass 5, count 0 2006.285.07:35:27.68#ibcon#end of sib2, iclass 5, count 0 2006.285.07:35:27.68#ibcon#*after write, iclass 5, count 0 2006.285.07:35:27.68#ibcon#*before return 0, iclass 5, count 0 2006.285.07:35:27.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:35:27.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:35:27.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:35:27.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:35:27.68$vck44/vblo=1,629.99 2006.285.07:35:27.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.07:35:27.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.07:35:27.68#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:27.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:35:27.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:35:27.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:35:27.68#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:35:27.68#ibcon#first serial, iclass 7, count 0 2006.285.07:35:27.68#ibcon#enter sib2, iclass 7, count 0 2006.285.07:35:27.68#ibcon#flushed, iclass 7, count 0 2006.285.07:35:27.68#ibcon#about to write, iclass 7, count 0 2006.285.07:35:27.68#ibcon#wrote, iclass 7, count 0 2006.285.07:35:27.68#ibcon#about to read 3, iclass 7, count 0 2006.285.07:35:27.70#ibcon#read 3, iclass 7, count 0 2006.285.07:35:27.70#ibcon#about to read 4, iclass 7, count 0 2006.285.07:35:27.70#ibcon#read 4, iclass 7, count 0 2006.285.07:35:27.70#ibcon#about to read 5, iclass 7, count 0 2006.285.07:35:27.70#ibcon#read 5, iclass 7, count 0 2006.285.07:35:27.70#ibcon#about to read 6, iclass 7, count 0 2006.285.07:35:27.70#ibcon#read 6, iclass 7, count 0 2006.285.07:35:27.70#ibcon#end of sib2, iclass 7, count 0 2006.285.07:35:27.70#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:35:27.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:35:27.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:35:27.70#ibcon#*before write, iclass 7, count 0 2006.285.07:35:27.70#ibcon#enter sib2, iclass 7, count 0 2006.285.07:35:27.70#ibcon#flushed, iclass 7, count 0 2006.285.07:35:27.70#ibcon#about to write, iclass 7, count 0 2006.285.07:35:27.70#ibcon#wrote, iclass 7, count 0 2006.285.07:35:27.70#ibcon#about to read 3, iclass 7, count 0 2006.285.07:35:27.74#ibcon#read 3, iclass 7, count 0 2006.285.07:35:27.74#ibcon#about to read 4, iclass 7, count 0 2006.285.07:35:27.74#ibcon#read 4, iclass 7, count 0 2006.285.07:35:27.74#ibcon#about to read 5, iclass 7, count 0 2006.285.07:35:27.74#ibcon#read 5, iclass 7, count 0 2006.285.07:35:27.74#ibcon#about to read 6, iclass 7, count 0 2006.285.07:35:27.74#ibcon#read 6, iclass 7, count 0 2006.285.07:35:27.74#ibcon#end of sib2, iclass 7, count 0 2006.285.07:35:27.74#ibcon#*after write, iclass 7, count 0 2006.285.07:35:27.74#ibcon#*before return 0, iclass 7, count 0 2006.285.07:35:27.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:35:27.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:35:27.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:35:27.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:35:27.74$vck44/vb=1,4 2006.285.07:35:27.74#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.07:35:27.74#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.07:35:27.74#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:27.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:35:27.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:35:27.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:35:27.74#ibcon#enter wrdev, iclass 11, count 2 2006.285.07:35:27.74#ibcon#first serial, iclass 11, count 2 2006.285.07:35:27.74#ibcon#enter sib2, iclass 11, count 2 2006.285.07:35:27.74#ibcon#flushed, iclass 11, count 2 2006.285.07:35:27.74#ibcon#about to write, iclass 11, count 2 2006.285.07:35:27.74#ibcon#wrote, iclass 11, count 2 2006.285.07:35:27.74#ibcon#about to read 3, iclass 11, count 2 2006.285.07:35:27.76#ibcon#read 3, iclass 11, count 2 2006.285.07:35:27.76#ibcon#about to read 4, iclass 11, count 2 2006.285.07:35:27.76#ibcon#read 4, iclass 11, count 2 2006.285.07:35:27.76#ibcon#about to read 5, iclass 11, count 2 2006.285.07:35:27.76#ibcon#read 5, iclass 11, count 2 2006.285.07:35:27.76#ibcon#about to read 6, iclass 11, count 2 2006.285.07:35:27.76#ibcon#read 6, iclass 11, count 2 2006.285.07:35:27.76#ibcon#end of sib2, iclass 11, count 2 2006.285.07:35:27.76#ibcon#*mode == 0, iclass 11, count 2 2006.285.07:35:27.76#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.07:35:27.76#ibcon#[27=AT01-04\r\n] 2006.285.07:35:27.76#ibcon#*before write, iclass 11, count 2 2006.285.07:35:27.76#ibcon#enter sib2, iclass 11, count 2 2006.285.07:35:27.76#ibcon#flushed, iclass 11, count 2 2006.285.07:35:27.76#ibcon#about to write, iclass 11, count 2 2006.285.07:35:27.76#ibcon#wrote, iclass 11, count 2 2006.285.07:35:27.76#ibcon#about to read 3, iclass 11, count 2 2006.285.07:35:27.79#ibcon#read 3, iclass 11, count 2 2006.285.07:35:27.79#ibcon#about to read 4, iclass 11, count 2 2006.285.07:35:27.79#ibcon#read 4, iclass 11, count 2 2006.285.07:35:27.79#ibcon#about to read 5, iclass 11, count 2 2006.285.07:35:27.79#ibcon#read 5, iclass 11, count 2 2006.285.07:35:27.79#ibcon#about to read 6, iclass 11, count 2 2006.285.07:35:27.79#ibcon#read 6, iclass 11, count 2 2006.285.07:35:27.79#ibcon#end of sib2, iclass 11, count 2 2006.285.07:35:27.79#ibcon#*after write, iclass 11, count 2 2006.285.07:35:27.79#ibcon#*before return 0, iclass 11, count 2 2006.285.07:35:27.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:35:27.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:35:27.79#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.07:35:27.79#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:27.79#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:35:27.91#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:35:27.91#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:35:27.91#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:35:27.91#ibcon#first serial, iclass 11, count 0 2006.285.07:35:27.91#ibcon#enter sib2, iclass 11, count 0 2006.285.07:35:27.91#ibcon#flushed, iclass 11, count 0 2006.285.07:35:27.91#ibcon#about to write, iclass 11, count 0 2006.285.07:35:27.91#ibcon#wrote, iclass 11, count 0 2006.285.07:35:27.91#ibcon#about to read 3, iclass 11, count 0 2006.285.07:35:27.93#ibcon#read 3, iclass 11, count 0 2006.285.07:35:27.93#ibcon#about to read 4, iclass 11, count 0 2006.285.07:35:27.93#ibcon#read 4, iclass 11, count 0 2006.285.07:35:27.93#ibcon#about to read 5, iclass 11, count 0 2006.285.07:35:27.93#ibcon#read 5, iclass 11, count 0 2006.285.07:35:27.93#ibcon#about to read 6, iclass 11, count 0 2006.285.07:35:27.93#ibcon#read 6, iclass 11, count 0 2006.285.07:35:27.93#ibcon#end of sib2, iclass 11, count 0 2006.285.07:35:27.93#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:35:27.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:35:27.93#ibcon#[27=USB\r\n] 2006.285.07:35:27.93#ibcon#*before write, iclass 11, count 0 2006.285.07:35:27.93#ibcon#enter sib2, iclass 11, count 0 2006.285.07:35:27.93#ibcon#flushed, iclass 11, count 0 2006.285.07:35:27.93#ibcon#about to write, iclass 11, count 0 2006.285.07:35:27.93#ibcon#wrote, iclass 11, count 0 2006.285.07:35:27.93#ibcon#about to read 3, iclass 11, count 0 2006.285.07:35:27.96#ibcon#read 3, iclass 11, count 0 2006.285.07:35:27.96#ibcon#about to read 4, iclass 11, count 0 2006.285.07:35:27.96#ibcon#read 4, iclass 11, count 0 2006.285.07:35:27.96#ibcon#about to read 5, iclass 11, count 0 2006.285.07:35:27.96#ibcon#read 5, iclass 11, count 0 2006.285.07:35:27.96#ibcon#about to read 6, iclass 11, count 0 2006.285.07:35:27.96#ibcon#read 6, iclass 11, count 0 2006.285.07:35:27.96#ibcon#end of sib2, iclass 11, count 0 2006.285.07:35:27.96#ibcon#*after write, iclass 11, count 0 2006.285.07:35:27.96#ibcon#*before return 0, iclass 11, count 0 2006.285.07:35:27.96#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:35:27.96#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:35:27.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:35:27.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:35:27.96$vck44/vblo=2,634.99 2006.285.07:35:27.96#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.07:35:27.96#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.07:35:27.96#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:27.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:35:27.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:35:27.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:35:27.96#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:35:27.96#ibcon#first serial, iclass 13, count 0 2006.285.07:35:27.96#ibcon#enter sib2, iclass 13, count 0 2006.285.07:35:27.96#ibcon#flushed, iclass 13, count 0 2006.285.07:35:27.96#ibcon#about to write, iclass 13, count 0 2006.285.07:35:27.96#ibcon#wrote, iclass 13, count 0 2006.285.07:35:27.96#ibcon#about to read 3, iclass 13, count 0 2006.285.07:35:27.98#ibcon#read 3, iclass 13, count 0 2006.285.07:35:27.98#ibcon#about to read 4, iclass 13, count 0 2006.285.07:35:27.98#ibcon#read 4, iclass 13, count 0 2006.285.07:35:27.98#ibcon#about to read 5, iclass 13, count 0 2006.285.07:35:27.98#ibcon#read 5, iclass 13, count 0 2006.285.07:35:27.98#ibcon#about to read 6, iclass 13, count 0 2006.285.07:35:27.98#ibcon#read 6, iclass 13, count 0 2006.285.07:35:27.98#ibcon#end of sib2, iclass 13, count 0 2006.285.07:35:27.98#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:35:27.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:35:27.98#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:35:27.98#ibcon#*before write, iclass 13, count 0 2006.285.07:35:27.98#ibcon#enter sib2, iclass 13, count 0 2006.285.07:35:27.98#ibcon#flushed, iclass 13, count 0 2006.285.07:35:27.98#ibcon#about to write, iclass 13, count 0 2006.285.07:35:27.98#ibcon#wrote, iclass 13, count 0 2006.285.07:35:27.98#ibcon#about to read 3, iclass 13, count 0 2006.285.07:35:28.02#ibcon#read 3, iclass 13, count 0 2006.285.07:35:28.02#ibcon#about to read 4, iclass 13, count 0 2006.285.07:35:28.02#ibcon#read 4, iclass 13, count 0 2006.285.07:35:28.02#ibcon#about to read 5, iclass 13, count 0 2006.285.07:35:28.02#ibcon#read 5, iclass 13, count 0 2006.285.07:35:28.02#ibcon#about to read 6, iclass 13, count 0 2006.285.07:35:28.02#ibcon#read 6, iclass 13, count 0 2006.285.07:35:28.02#ibcon#end of sib2, iclass 13, count 0 2006.285.07:35:28.02#ibcon#*after write, iclass 13, count 0 2006.285.07:35:28.02#ibcon#*before return 0, iclass 13, count 0 2006.285.07:35:28.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:35:28.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:35:28.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:35:28.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:35:28.02$vck44/vb=2,5 2006.285.07:35:28.02#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.07:35:28.02#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.07:35:28.02#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:28.02#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:35:28.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:35:28.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:35:28.08#ibcon#enter wrdev, iclass 15, count 2 2006.285.07:35:28.08#ibcon#first serial, iclass 15, count 2 2006.285.07:35:28.08#ibcon#enter sib2, iclass 15, count 2 2006.285.07:35:28.08#ibcon#flushed, iclass 15, count 2 2006.285.07:35:28.08#ibcon#about to write, iclass 15, count 2 2006.285.07:35:28.08#ibcon#wrote, iclass 15, count 2 2006.285.07:35:28.08#ibcon#about to read 3, iclass 15, count 2 2006.285.07:35:28.10#ibcon#read 3, iclass 15, count 2 2006.285.07:35:28.10#ibcon#about to read 4, iclass 15, count 2 2006.285.07:35:28.10#ibcon#read 4, iclass 15, count 2 2006.285.07:35:28.10#ibcon#about to read 5, iclass 15, count 2 2006.285.07:35:28.10#ibcon#read 5, iclass 15, count 2 2006.285.07:35:28.10#ibcon#about to read 6, iclass 15, count 2 2006.285.07:35:28.10#ibcon#read 6, iclass 15, count 2 2006.285.07:35:28.10#ibcon#end of sib2, iclass 15, count 2 2006.285.07:35:28.10#ibcon#*mode == 0, iclass 15, count 2 2006.285.07:35:28.10#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.07:35:28.10#ibcon#[27=AT02-05\r\n] 2006.285.07:35:28.10#ibcon#*before write, iclass 15, count 2 2006.285.07:35:28.10#ibcon#enter sib2, iclass 15, count 2 2006.285.07:35:28.10#ibcon#flushed, iclass 15, count 2 2006.285.07:35:28.10#ibcon#about to write, iclass 15, count 2 2006.285.07:35:28.10#ibcon#wrote, iclass 15, count 2 2006.285.07:35:28.10#ibcon#about to read 3, iclass 15, count 2 2006.285.07:35:28.13#ibcon#read 3, iclass 15, count 2 2006.285.07:35:28.13#ibcon#about to read 4, iclass 15, count 2 2006.285.07:35:28.13#ibcon#read 4, iclass 15, count 2 2006.285.07:35:28.13#ibcon#about to read 5, iclass 15, count 2 2006.285.07:35:28.13#ibcon#read 5, iclass 15, count 2 2006.285.07:35:28.13#ibcon#about to read 6, iclass 15, count 2 2006.285.07:35:28.13#ibcon#read 6, iclass 15, count 2 2006.285.07:35:28.13#ibcon#end of sib2, iclass 15, count 2 2006.285.07:35:28.13#ibcon#*after write, iclass 15, count 2 2006.285.07:35:28.13#ibcon#*before return 0, iclass 15, count 2 2006.285.07:35:28.13#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:35:28.13#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:35:28.13#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.07:35:28.13#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:28.13#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:35:28.25#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:35:28.25#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:35:28.25#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:35:28.25#ibcon#first serial, iclass 15, count 0 2006.285.07:35:28.25#ibcon#enter sib2, iclass 15, count 0 2006.285.07:35:28.25#ibcon#flushed, iclass 15, count 0 2006.285.07:35:28.25#ibcon#about to write, iclass 15, count 0 2006.285.07:35:28.25#ibcon#wrote, iclass 15, count 0 2006.285.07:35:28.25#ibcon#about to read 3, iclass 15, count 0 2006.285.07:35:28.27#ibcon#read 3, iclass 15, count 0 2006.285.07:35:28.27#ibcon#about to read 4, iclass 15, count 0 2006.285.07:35:28.27#ibcon#read 4, iclass 15, count 0 2006.285.07:35:28.27#ibcon#about to read 5, iclass 15, count 0 2006.285.07:35:28.27#ibcon#read 5, iclass 15, count 0 2006.285.07:35:28.27#ibcon#about to read 6, iclass 15, count 0 2006.285.07:35:28.27#ibcon#read 6, iclass 15, count 0 2006.285.07:35:28.27#ibcon#end of sib2, iclass 15, count 0 2006.285.07:35:28.27#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:35:28.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:35:28.27#ibcon#[27=USB\r\n] 2006.285.07:35:28.27#ibcon#*before write, iclass 15, count 0 2006.285.07:35:28.27#ibcon#enter sib2, iclass 15, count 0 2006.285.07:35:28.27#ibcon#flushed, iclass 15, count 0 2006.285.07:35:28.27#ibcon#about to write, iclass 15, count 0 2006.285.07:35:28.27#ibcon#wrote, iclass 15, count 0 2006.285.07:35:28.27#ibcon#about to read 3, iclass 15, count 0 2006.285.07:35:28.30#ibcon#read 3, iclass 15, count 0 2006.285.07:35:28.30#ibcon#about to read 4, iclass 15, count 0 2006.285.07:35:28.30#ibcon#read 4, iclass 15, count 0 2006.285.07:35:28.30#ibcon#about to read 5, iclass 15, count 0 2006.285.07:35:28.30#ibcon#read 5, iclass 15, count 0 2006.285.07:35:28.30#ibcon#about to read 6, iclass 15, count 0 2006.285.07:35:28.30#ibcon#read 6, iclass 15, count 0 2006.285.07:35:28.30#ibcon#end of sib2, iclass 15, count 0 2006.285.07:35:28.30#ibcon#*after write, iclass 15, count 0 2006.285.07:35:28.30#ibcon#*before return 0, iclass 15, count 0 2006.285.07:35:28.30#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:35:28.30#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:35:28.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:35:28.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:35:28.30$vck44/vblo=3,649.99 2006.285.07:35:28.30#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.07:35:28.30#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.07:35:28.30#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:28.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:35:28.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:35:28.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:35:28.30#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:35:28.30#ibcon#first serial, iclass 17, count 0 2006.285.07:35:28.30#ibcon#enter sib2, iclass 17, count 0 2006.285.07:35:28.30#ibcon#flushed, iclass 17, count 0 2006.285.07:35:28.30#ibcon#about to write, iclass 17, count 0 2006.285.07:35:28.30#ibcon#wrote, iclass 17, count 0 2006.285.07:35:28.30#ibcon#about to read 3, iclass 17, count 0 2006.285.07:35:28.32#ibcon#read 3, iclass 17, count 0 2006.285.07:35:28.32#ibcon#about to read 4, iclass 17, count 0 2006.285.07:35:28.32#ibcon#read 4, iclass 17, count 0 2006.285.07:35:28.32#ibcon#about to read 5, iclass 17, count 0 2006.285.07:35:28.32#ibcon#read 5, iclass 17, count 0 2006.285.07:35:28.32#ibcon#about to read 6, iclass 17, count 0 2006.285.07:35:28.32#ibcon#read 6, iclass 17, count 0 2006.285.07:35:28.32#ibcon#end of sib2, iclass 17, count 0 2006.285.07:35:28.32#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:35:28.32#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:35:28.32#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:35:28.32#ibcon#*before write, iclass 17, count 0 2006.285.07:35:28.32#ibcon#enter sib2, iclass 17, count 0 2006.285.07:35:28.32#ibcon#flushed, iclass 17, count 0 2006.285.07:35:28.32#ibcon#about to write, iclass 17, count 0 2006.285.07:35:28.32#ibcon#wrote, iclass 17, count 0 2006.285.07:35:28.32#ibcon#about to read 3, iclass 17, count 0 2006.285.07:35:28.36#ibcon#read 3, iclass 17, count 0 2006.285.07:35:28.36#ibcon#about to read 4, iclass 17, count 0 2006.285.07:35:28.36#ibcon#read 4, iclass 17, count 0 2006.285.07:35:28.36#ibcon#about to read 5, iclass 17, count 0 2006.285.07:35:28.36#ibcon#read 5, iclass 17, count 0 2006.285.07:35:28.36#ibcon#about to read 6, iclass 17, count 0 2006.285.07:35:28.36#ibcon#read 6, iclass 17, count 0 2006.285.07:35:28.36#ibcon#end of sib2, iclass 17, count 0 2006.285.07:35:28.36#ibcon#*after write, iclass 17, count 0 2006.285.07:35:28.36#ibcon#*before return 0, iclass 17, count 0 2006.285.07:35:28.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:35:28.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:35:28.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:35:28.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:35:28.36$vck44/vb=3,4 2006.285.07:35:28.36#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.07:35:28.36#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.07:35:28.36#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:28.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:35:28.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:35:28.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:35:28.42#ibcon#enter wrdev, iclass 19, count 2 2006.285.07:35:28.42#ibcon#first serial, iclass 19, count 2 2006.285.07:35:28.42#ibcon#enter sib2, iclass 19, count 2 2006.285.07:35:28.42#ibcon#flushed, iclass 19, count 2 2006.285.07:35:28.42#ibcon#about to write, iclass 19, count 2 2006.285.07:35:28.42#ibcon#wrote, iclass 19, count 2 2006.285.07:35:28.42#ibcon#about to read 3, iclass 19, count 2 2006.285.07:35:28.44#ibcon#read 3, iclass 19, count 2 2006.285.07:35:28.44#ibcon#about to read 4, iclass 19, count 2 2006.285.07:35:28.44#ibcon#read 4, iclass 19, count 2 2006.285.07:35:28.44#ibcon#about to read 5, iclass 19, count 2 2006.285.07:35:28.44#ibcon#read 5, iclass 19, count 2 2006.285.07:35:28.44#ibcon#about to read 6, iclass 19, count 2 2006.285.07:35:28.44#ibcon#read 6, iclass 19, count 2 2006.285.07:35:28.44#ibcon#end of sib2, iclass 19, count 2 2006.285.07:35:28.44#ibcon#*mode == 0, iclass 19, count 2 2006.285.07:35:28.44#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.07:35:28.44#ibcon#[27=AT03-04\r\n] 2006.285.07:35:28.44#ibcon#*before write, iclass 19, count 2 2006.285.07:35:28.44#ibcon#enter sib2, iclass 19, count 2 2006.285.07:35:28.44#ibcon#flushed, iclass 19, count 2 2006.285.07:35:28.44#ibcon#about to write, iclass 19, count 2 2006.285.07:35:28.44#ibcon#wrote, iclass 19, count 2 2006.285.07:35:28.44#ibcon#about to read 3, iclass 19, count 2 2006.285.07:35:28.47#ibcon#read 3, iclass 19, count 2 2006.285.07:35:28.47#ibcon#about to read 4, iclass 19, count 2 2006.285.07:35:28.47#ibcon#read 4, iclass 19, count 2 2006.285.07:35:28.47#ibcon#about to read 5, iclass 19, count 2 2006.285.07:35:28.47#ibcon#read 5, iclass 19, count 2 2006.285.07:35:28.47#ibcon#about to read 6, iclass 19, count 2 2006.285.07:35:28.47#ibcon#read 6, iclass 19, count 2 2006.285.07:35:28.47#ibcon#end of sib2, iclass 19, count 2 2006.285.07:35:28.47#ibcon#*after write, iclass 19, count 2 2006.285.07:35:28.47#ibcon#*before return 0, iclass 19, count 2 2006.285.07:35:28.47#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:35:28.47#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:35:28.47#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.07:35:28.47#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:28.47#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:35:28.59#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:35:28.59#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:35:28.59#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:35:28.59#ibcon#first serial, iclass 19, count 0 2006.285.07:35:28.59#ibcon#enter sib2, iclass 19, count 0 2006.285.07:35:28.59#ibcon#flushed, iclass 19, count 0 2006.285.07:35:28.59#ibcon#about to write, iclass 19, count 0 2006.285.07:35:28.59#ibcon#wrote, iclass 19, count 0 2006.285.07:35:28.59#ibcon#about to read 3, iclass 19, count 0 2006.285.07:35:28.61#ibcon#read 3, iclass 19, count 0 2006.285.07:35:28.61#ibcon#about to read 4, iclass 19, count 0 2006.285.07:35:28.61#ibcon#read 4, iclass 19, count 0 2006.285.07:35:28.61#ibcon#about to read 5, iclass 19, count 0 2006.285.07:35:28.61#ibcon#read 5, iclass 19, count 0 2006.285.07:35:28.61#ibcon#about to read 6, iclass 19, count 0 2006.285.07:35:28.61#ibcon#read 6, iclass 19, count 0 2006.285.07:35:28.61#ibcon#end of sib2, iclass 19, count 0 2006.285.07:35:28.61#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:35:28.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:35:28.61#ibcon#[27=USB\r\n] 2006.285.07:35:28.61#ibcon#*before write, iclass 19, count 0 2006.285.07:35:28.61#ibcon#enter sib2, iclass 19, count 0 2006.285.07:35:28.61#ibcon#flushed, iclass 19, count 0 2006.285.07:35:28.61#ibcon#about to write, iclass 19, count 0 2006.285.07:35:28.61#ibcon#wrote, iclass 19, count 0 2006.285.07:35:28.61#ibcon#about to read 3, iclass 19, count 0 2006.285.07:35:28.64#ibcon#read 3, iclass 19, count 0 2006.285.07:35:28.64#ibcon#about to read 4, iclass 19, count 0 2006.285.07:35:28.64#ibcon#read 4, iclass 19, count 0 2006.285.07:35:28.64#ibcon#about to read 5, iclass 19, count 0 2006.285.07:35:28.64#ibcon#read 5, iclass 19, count 0 2006.285.07:35:28.64#ibcon#about to read 6, iclass 19, count 0 2006.285.07:35:28.64#ibcon#read 6, iclass 19, count 0 2006.285.07:35:28.64#ibcon#end of sib2, iclass 19, count 0 2006.285.07:35:28.64#ibcon#*after write, iclass 19, count 0 2006.285.07:35:28.64#ibcon#*before return 0, iclass 19, count 0 2006.285.07:35:28.64#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:35:28.64#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:35:28.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:35:28.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:35:28.64$vck44/vblo=4,679.99 2006.285.07:35:28.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.07:35:28.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.07:35:28.64#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:28.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:35:28.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:35:28.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:35:28.64#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:35:28.64#ibcon#first serial, iclass 21, count 0 2006.285.07:35:28.64#ibcon#enter sib2, iclass 21, count 0 2006.285.07:35:28.64#ibcon#flushed, iclass 21, count 0 2006.285.07:35:28.64#ibcon#about to write, iclass 21, count 0 2006.285.07:35:28.64#ibcon#wrote, iclass 21, count 0 2006.285.07:35:28.64#ibcon#about to read 3, iclass 21, count 0 2006.285.07:35:28.66#ibcon#read 3, iclass 21, count 0 2006.285.07:35:28.66#ibcon#about to read 4, iclass 21, count 0 2006.285.07:35:28.66#ibcon#read 4, iclass 21, count 0 2006.285.07:35:28.66#ibcon#about to read 5, iclass 21, count 0 2006.285.07:35:28.66#ibcon#read 5, iclass 21, count 0 2006.285.07:35:28.66#ibcon#about to read 6, iclass 21, count 0 2006.285.07:35:28.66#ibcon#read 6, iclass 21, count 0 2006.285.07:35:28.66#ibcon#end of sib2, iclass 21, count 0 2006.285.07:35:28.66#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:35:28.66#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:35:28.66#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:35:28.66#ibcon#*before write, iclass 21, count 0 2006.285.07:35:28.66#ibcon#enter sib2, iclass 21, count 0 2006.285.07:35:28.66#ibcon#flushed, iclass 21, count 0 2006.285.07:35:28.66#ibcon#about to write, iclass 21, count 0 2006.285.07:35:28.66#ibcon#wrote, iclass 21, count 0 2006.285.07:35:28.66#ibcon#about to read 3, iclass 21, count 0 2006.285.07:35:28.70#ibcon#read 3, iclass 21, count 0 2006.285.07:35:28.70#ibcon#about to read 4, iclass 21, count 0 2006.285.07:35:28.70#ibcon#read 4, iclass 21, count 0 2006.285.07:35:28.70#ibcon#about to read 5, iclass 21, count 0 2006.285.07:35:28.70#ibcon#read 5, iclass 21, count 0 2006.285.07:35:28.70#ibcon#about to read 6, iclass 21, count 0 2006.285.07:35:28.70#ibcon#read 6, iclass 21, count 0 2006.285.07:35:28.70#ibcon#end of sib2, iclass 21, count 0 2006.285.07:35:28.70#ibcon#*after write, iclass 21, count 0 2006.285.07:35:28.70#ibcon#*before return 0, iclass 21, count 0 2006.285.07:35:28.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:35:28.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:35:28.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:35:28.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:35:28.70$vck44/vb=4,5 2006.285.07:35:28.70#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.07:35:28.70#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.07:35:28.70#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:28.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:35:28.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:35:28.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:35:28.76#ibcon#enter wrdev, iclass 23, count 2 2006.285.07:35:28.76#ibcon#first serial, iclass 23, count 2 2006.285.07:35:28.76#ibcon#enter sib2, iclass 23, count 2 2006.285.07:35:28.76#ibcon#flushed, iclass 23, count 2 2006.285.07:35:28.76#ibcon#about to write, iclass 23, count 2 2006.285.07:35:28.76#ibcon#wrote, iclass 23, count 2 2006.285.07:35:28.76#ibcon#about to read 3, iclass 23, count 2 2006.285.07:35:28.78#ibcon#read 3, iclass 23, count 2 2006.285.07:35:28.78#ibcon#about to read 4, iclass 23, count 2 2006.285.07:35:28.78#ibcon#read 4, iclass 23, count 2 2006.285.07:35:28.78#ibcon#about to read 5, iclass 23, count 2 2006.285.07:35:28.78#ibcon#read 5, iclass 23, count 2 2006.285.07:35:28.78#ibcon#about to read 6, iclass 23, count 2 2006.285.07:35:28.78#ibcon#read 6, iclass 23, count 2 2006.285.07:35:28.78#ibcon#end of sib2, iclass 23, count 2 2006.285.07:35:28.78#ibcon#*mode == 0, iclass 23, count 2 2006.285.07:35:28.78#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.07:35:28.78#ibcon#[27=AT04-05\r\n] 2006.285.07:35:28.78#ibcon#*before write, iclass 23, count 2 2006.285.07:35:28.78#ibcon#enter sib2, iclass 23, count 2 2006.285.07:35:28.78#ibcon#flushed, iclass 23, count 2 2006.285.07:35:28.78#ibcon#about to write, iclass 23, count 2 2006.285.07:35:28.78#ibcon#wrote, iclass 23, count 2 2006.285.07:35:28.78#ibcon#about to read 3, iclass 23, count 2 2006.285.07:35:28.81#ibcon#read 3, iclass 23, count 2 2006.285.07:35:28.81#ibcon#about to read 4, iclass 23, count 2 2006.285.07:35:28.81#ibcon#read 4, iclass 23, count 2 2006.285.07:35:28.81#ibcon#about to read 5, iclass 23, count 2 2006.285.07:35:28.81#ibcon#read 5, iclass 23, count 2 2006.285.07:35:28.81#ibcon#about to read 6, iclass 23, count 2 2006.285.07:35:28.81#ibcon#read 6, iclass 23, count 2 2006.285.07:35:28.81#ibcon#end of sib2, iclass 23, count 2 2006.285.07:35:28.81#ibcon#*after write, iclass 23, count 2 2006.285.07:35:28.81#ibcon#*before return 0, iclass 23, count 2 2006.285.07:35:28.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:35:28.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:35:28.81#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.07:35:28.81#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:28.81#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:35:28.93#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:35:28.93#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:35:28.93#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:35:28.93#ibcon#first serial, iclass 23, count 0 2006.285.07:35:28.93#ibcon#enter sib2, iclass 23, count 0 2006.285.07:35:28.93#ibcon#flushed, iclass 23, count 0 2006.285.07:35:28.93#ibcon#about to write, iclass 23, count 0 2006.285.07:35:28.93#ibcon#wrote, iclass 23, count 0 2006.285.07:35:28.93#ibcon#about to read 3, iclass 23, count 0 2006.285.07:35:28.95#ibcon#read 3, iclass 23, count 0 2006.285.07:35:28.95#ibcon#about to read 4, iclass 23, count 0 2006.285.07:35:28.95#ibcon#read 4, iclass 23, count 0 2006.285.07:35:28.95#ibcon#about to read 5, iclass 23, count 0 2006.285.07:35:28.95#ibcon#read 5, iclass 23, count 0 2006.285.07:35:28.95#ibcon#about to read 6, iclass 23, count 0 2006.285.07:35:28.95#ibcon#read 6, iclass 23, count 0 2006.285.07:35:28.95#ibcon#end of sib2, iclass 23, count 0 2006.285.07:35:28.95#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:35:28.95#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:35:28.95#ibcon#[27=USB\r\n] 2006.285.07:35:28.95#ibcon#*before write, iclass 23, count 0 2006.285.07:35:28.95#ibcon#enter sib2, iclass 23, count 0 2006.285.07:35:28.95#ibcon#flushed, iclass 23, count 0 2006.285.07:35:28.95#ibcon#about to write, iclass 23, count 0 2006.285.07:35:28.95#ibcon#wrote, iclass 23, count 0 2006.285.07:35:28.95#ibcon#about to read 3, iclass 23, count 0 2006.285.07:35:28.98#ibcon#read 3, iclass 23, count 0 2006.285.07:35:28.98#ibcon#about to read 4, iclass 23, count 0 2006.285.07:35:28.98#ibcon#read 4, iclass 23, count 0 2006.285.07:35:28.98#ibcon#about to read 5, iclass 23, count 0 2006.285.07:35:28.98#ibcon#read 5, iclass 23, count 0 2006.285.07:35:28.98#ibcon#about to read 6, iclass 23, count 0 2006.285.07:35:28.98#ibcon#read 6, iclass 23, count 0 2006.285.07:35:28.98#ibcon#end of sib2, iclass 23, count 0 2006.285.07:35:28.98#ibcon#*after write, iclass 23, count 0 2006.285.07:35:28.98#ibcon#*before return 0, iclass 23, count 0 2006.285.07:35:28.98#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:35:28.98#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:35:28.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:35:28.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:35:28.98$vck44/vblo=5,709.99 2006.285.07:35:28.98#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.07:35:28.98#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.07:35:28.98#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:28.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:35:28.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:35:28.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:35:28.98#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:35:28.98#ibcon#first serial, iclass 25, count 0 2006.285.07:35:28.98#ibcon#enter sib2, iclass 25, count 0 2006.285.07:35:28.98#ibcon#flushed, iclass 25, count 0 2006.285.07:35:28.98#ibcon#about to write, iclass 25, count 0 2006.285.07:35:28.98#ibcon#wrote, iclass 25, count 0 2006.285.07:35:28.98#ibcon#about to read 3, iclass 25, count 0 2006.285.07:35:29.00#ibcon#read 3, iclass 25, count 0 2006.285.07:35:29.00#ibcon#about to read 4, iclass 25, count 0 2006.285.07:35:29.00#ibcon#read 4, iclass 25, count 0 2006.285.07:35:29.00#ibcon#about to read 5, iclass 25, count 0 2006.285.07:35:29.00#ibcon#read 5, iclass 25, count 0 2006.285.07:35:29.00#ibcon#about to read 6, iclass 25, count 0 2006.285.07:35:29.00#ibcon#read 6, iclass 25, count 0 2006.285.07:35:29.00#ibcon#end of sib2, iclass 25, count 0 2006.285.07:35:29.00#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:35:29.00#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:35:29.00#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:35:29.00#ibcon#*before write, iclass 25, count 0 2006.285.07:35:29.00#ibcon#enter sib2, iclass 25, count 0 2006.285.07:35:29.00#ibcon#flushed, iclass 25, count 0 2006.285.07:35:29.00#ibcon#about to write, iclass 25, count 0 2006.285.07:35:29.00#ibcon#wrote, iclass 25, count 0 2006.285.07:35:29.00#ibcon#about to read 3, iclass 25, count 0 2006.285.07:35:29.04#ibcon#read 3, iclass 25, count 0 2006.285.07:35:29.04#ibcon#about to read 4, iclass 25, count 0 2006.285.07:35:29.04#ibcon#read 4, iclass 25, count 0 2006.285.07:35:29.04#ibcon#about to read 5, iclass 25, count 0 2006.285.07:35:29.04#ibcon#read 5, iclass 25, count 0 2006.285.07:35:29.04#ibcon#about to read 6, iclass 25, count 0 2006.285.07:35:29.04#ibcon#read 6, iclass 25, count 0 2006.285.07:35:29.04#ibcon#end of sib2, iclass 25, count 0 2006.285.07:35:29.04#ibcon#*after write, iclass 25, count 0 2006.285.07:35:29.04#ibcon#*before return 0, iclass 25, count 0 2006.285.07:35:29.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:35:29.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:35:29.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:35:29.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:35:29.04$vck44/vb=5,4 2006.285.07:35:29.04#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.07:35:29.04#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.07:35:29.04#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:29.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:35:29.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:35:29.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:35:29.10#ibcon#enter wrdev, iclass 27, count 2 2006.285.07:35:29.10#ibcon#first serial, iclass 27, count 2 2006.285.07:35:29.10#ibcon#enter sib2, iclass 27, count 2 2006.285.07:35:29.10#ibcon#flushed, iclass 27, count 2 2006.285.07:35:29.10#ibcon#about to write, iclass 27, count 2 2006.285.07:35:29.10#ibcon#wrote, iclass 27, count 2 2006.285.07:35:29.10#ibcon#about to read 3, iclass 27, count 2 2006.285.07:35:29.12#ibcon#read 3, iclass 27, count 2 2006.285.07:35:29.12#ibcon#about to read 4, iclass 27, count 2 2006.285.07:35:29.12#ibcon#read 4, iclass 27, count 2 2006.285.07:35:29.12#ibcon#about to read 5, iclass 27, count 2 2006.285.07:35:29.12#ibcon#read 5, iclass 27, count 2 2006.285.07:35:29.12#ibcon#about to read 6, iclass 27, count 2 2006.285.07:35:29.12#ibcon#read 6, iclass 27, count 2 2006.285.07:35:29.12#ibcon#end of sib2, iclass 27, count 2 2006.285.07:35:29.12#ibcon#*mode == 0, iclass 27, count 2 2006.285.07:35:29.12#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.07:35:29.12#ibcon#[27=AT05-04\r\n] 2006.285.07:35:29.12#ibcon#*before write, iclass 27, count 2 2006.285.07:35:29.12#ibcon#enter sib2, iclass 27, count 2 2006.285.07:35:29.12#ibcon#flushed, iclass 27, count 2 2006.285.07:35:29.12#ibcon#about to write, iclass 27, count 2 2006.285.07:35:29.12#ibcon#wrote, iclass 27, count 2 2006.285.07:35:29.12#ibcon#about to read 3, iclass 27, count 2 2006.285.07:35:29.15#ibcon#read 3, iclass 27, count 2 2006.285.07:35:29.15#ibcon#about to read 4, iclass 27, count 2 2006.285.07:35:29.15#ibcon#read 4, iclass 27, count 2 2006.285.07:35:29.15#ibcon#about to read 5, iclass 27, count 2 2006.285.07:35:29.15#ibcon#read 5, iclass 27, count 2 2006.285.07:35:29.15#ibcon#about to read 6, iclass 27, count 2 2006.285.07:35:29.15#ibcon#read 6, iclass 27, count 2 2006.285.07:35:29.15#ibcon#end of sib2, iclass 27, count 2 2006.285.07:35:29.15#ibcon#*after write, iclass 27, count 2 2006.285.07:35:29.15#ibcon#*before return 0, iclass 27, count 2 2006.285.07:35:29.15#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:35:29.15#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:35:29.15#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.07:35:29.15#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:29.15#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:35:29.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:35:29.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:35:29.27#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:35:29.27#ibcon#first serial, iclass 27, count 0 2006.285.07:35:29.27#ibcon#enter sib2, iclass 27, count 0 2006.285.07:35:29.27#ibcon#flushed, iclass 27, count 0 2006.285.07:35:29.27#ibcon#about to write, iclass 27, count 0 2006.285.07:35:29.27#ibcon#wrote, iclass 27, count 0 2006.285.07:35:29.27#ibcon#about to read 3, iclass 27, count 0 2006.285.07:35:29.29#ibcon#read 3, iclass 27, count 0 2006.285.07:35:29.29#ibcon#about to read 4, iclass 27, count 0 2006.285.07:35:29.29#ibcon#read 4, iclass 27, count 0 2006.285.07:35:29.29#ibcon#about to read 5, iclass 27, count 0 2006.285.07:35:29.29#ibcon#read 5, iclass 27, count 0 2006.285.07:35:29.29#ibcon#about to read 6, iclass 27, count 0 2006.285.07:35:29.29#ibcon#read 6, iclass 27, count 0 2006.285.07:35:29.29#ibcon#end of sib2, iclass 27, count 0 2006.285.07:35:29.29#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:35:29.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:35:29.29#ibcon#[27=USB\r\n] 2006.285.07:35:29.29#ibcon#*before write, iclass 27, count 0 2006.285.07:35:29.29#ibcon#enter sib2, iclass 27, count 0 2006.285.07:35:29.29#ibcon#flushed, iclass 27, count 0 2006.285.07:35:29.29#ibcon#about to write, iclass 27, count 0 2006.285.07:35:29.29#ibcon#wrote, iclass 27, count 0 2006.285.07:35:29.29#ibcon#about to read 3, iclass 27, count 0 2006.285.07:35:29.32#ibcon#read 3, iclass 27, count 0 2006.285.07:35:29.32#ibcon#about to read 4, iclass 27, count 0 2006.285.07:35:29.32#ibcon#read 4, iclass 27, count 0 2006.285.07:35:29.32#ibcon#about to read 5, iclass 27, count 0 2006.285.07:35:29.32#ibcon#read 5, iclass 27, count 0 2006.285.07:35:29.32#ibcon#about to read 6, iclass 27, count 0 2006.285.07:35:29.32#ibcon#read 6, iclass 27, count 0 2006.285.07:35:29.32#ibcon#end of sib2, iclass 27, count 0 2006.285.07:35:29.32#ibcon#*after write, iclass 27, count 0 2006.285.07:35:29.32#ibcon#*before return 0, iclass 27, count 0 2006.285.07:35:29.32#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:35:29.32#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:35:29.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:35:29.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:35:29.32$vck44/vblo=6,719.99 2006.285.07:35:29.32#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.07:35:29.32#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.07:35:29.32#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:29.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:35:29.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:35:29.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:35:29.32#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:35:29.32#ibcon#first serial, iclass 29, count 0 2006.285.07:35:29.32#ibcon#enter sib2, iclass 29, count 0 2006.285.07:35:29.32#ibcon#flushed, iclass 29, count 0 2006.285.07:35:29.32#ibcon#about to write, iclass 29, count 0 2006.285.07:35:29.32#ibcon#wrote, iclass 29, count 0 2006.285.07:35:29.32#ibcon#about to read 3, iclass 29, count 0 2006.285.07:35:29.34#ibcon#read 3, iclass 29, count 0 2006.285.07:35:29.34#ibcon#about to read 4, iclass 29, count 0 2006.285.07:35:29.34#ibcon#read 4, iclass 29, count 0 2006.285.07:35:29.34#ibcon#about to read 5, iclass 29, count 0 2006.285.07:35:29.34#ibcon#read 5, iclass 29, count 0 2006.285.07:35:29.34#ibcon#about to read 6, iclass 29, count 0 2006.285.07:35:29.34#ibcon#read 6, iclass 29, count 0 2006.285.07:35:29.34#ibcon#end of sib2, iclass 29, count 0 2006.285.07:35:29.34#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:35:29.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:35:29.34#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:35:29.34#ibcon#*before write, iclass 29, count 0 2006.285.07:35:29.34#ibcon#enter sib2, iclass 29, count 0 2006.285.07:35:29.34#ibcon#flushed, iclass 29, count 0 2006.285.07:35:29.34#ibcon#about to write, iclass 29, count 0 2006.285.07:35:29.34#ibcon#wrote, iclass 29, count 0 2006.285.07:35:29.34#ibcon#about to read 3, iclass 29, count 0 2006.285.07:35:29.38#ibcon#read 3, iclass 29, count 0 2006.285.07:35:29.38#ibcon#about to read 4, iclass 29, count 0 2006.285.07:35:29.38#ibcon#read 4, iclass 29, count 0 2006.285.07:35:29.38#ibcon#about to read 5, iclass 29, count 0 2006.285.07:35:29.38#ibcon#read 5, iclass 29, count 0 2006.285.07:35:29.38#ibcon#about to read 6, iclass 29, count 0 2006.285.07:35:29.38#ibcon#read 6, iclass 29, count 0 2006.285.07:35:29.38#ibcon#end of sib2, iclass 29, count 0 2006.285.07:35:29.38#ibcon#*after write, iclass 29, count 0 2006.285.07:35:29.38#ibcon#*before return 0, iclass 29, count 0 2006.285.07:35:29.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:35:29.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:35:29.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:35:29.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:35:29.38$vck44/vb=6,3 2006.285.07:35:29.38#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.07:35:29.38#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.07:35:29.38#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:29.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:35:29.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:35:29.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:35:29.44#ibcon#enter wrdev, iclass 31, count 2 2006.285.07:35:29.44#ibcon#first serial, iclass 31, count 2 2006.285.07:35:29.44#ibcon#enter sib2, iclass 31, count 2 2006.285.07:35:29.44#ibcon#flushed, iclass 31, count 2 2006.285.07:35:29.44#ibcon#about to write, iclass 31, count 2 2006.285.07:35:29.44#ibcon#wrote, iclass 31, count 2 2006.285.07:35:29.44#ibcon#about to read 3, iclass 31, count 2 2006.285.07:35:29.46#ibcon#read 3, iclass 31, count 2 2006.285.07:35:29.46#ibcon#about to read 4, iclass 31, count 2 2006.285.07:35:29.46#ibcon#read 4, iclass 31, count 2 2006.285.07:35:29.46#ibcon#about to read 5, iclass 31, count 2 2006.285.07:35:29.46#ibcon#read 5, iclass 31, count 2 2006.285.07:35:29.46#ibcon#about to read 6, iclass 31, count 2 2006.285.07:35:29.46#ibcon#read 6, iclass 31, count 2 2006.285.07:35:29.46#ibcon#end of sib2, iclass 31, count 2 2006.285.07:35:29.46#ibcon#*mode == 0, iclass 31, count 2 2006.285.07:35:29.46#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.07:35:29.46#ibcon#[27=AT06-03\r\n] 2006.285.07:35:29.46#ibcon#*before write, iclass 31, count 2 2006.285.07:35:29.46#ibcon#enter sib2, iclass 31, count 2 2006.285.07:35:29.46#ibcon#flushed, iclass 31, count 2 2006.285.07:35:29.46#ibcon#about to write, iclass 31, count 2 2006.285.07:35:29.46#ibcon#wrote, iclass 31, count 2 2006.285.07:35:29.46#ibcon#about to read 3, iclass 31, count 2 2006.285.07:35:29.49#ibcon#read 3, iclass 31, count 2 2006.285.07:35:29.49#ibcon#about to read 4, iclass 31, count 2 2006.285.07:35:29.49#ibcon#read 4, iclass 31, count 2 2006.285.07:35:29.49#ibcon#about to read 5, iclass 31, count 2 2006.285.07:35:29.49#ibcon#read 5, iclass 31, count 2 2006.285.07:35:29.49#ibcon#about to read 6, iclass 31, count 2 2006.285.07:35:29.49#ibcon#read 6, iclass 31, count 2 2006.285.07:35:29.49#ibcon#end of sib2, iclass 31, count 2 2006.285.07:35:29.49#ibcon#*after write, iclass 31, count 2 2006.285.07:35:29.49#ibcon#*before return 0, iclass 31, count 2 2006.285.07:35:29.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:35:29.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:35:29.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.07:35:29.49#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:29.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:35:29.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:35:29.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:35:29.61#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:35:29.61#ibcon#first serial, iclass 31, count 0 2006.285.07:35:29.61#ibcon#enter sib2, iclass 31, count 0 2006.285.07:35:29.61#ibcon#flushed, iclass 31, count 0 2006.285.07:35:29.61#ibcon#about to write, iclass 31, count 0 2006.285.07:35:29.61#ibcon#wrote, iclass 31, count 0 2006.285.07:35:29.61#ibcon#about to read 3, iclass 31, count 0 2006.285.07:35:29.63#ibcon#read 3, iclass 31, count 0 2006.285.07:35:29.63#ibcon#about to read 4, iclass 31, count 0 2006.285.07:35:29.63#ibcon#read 4, iclass 31, count 0 2006.285.07:35:29.63#ibcon#about to read 5, iclass 31, count 0 2006.285.07:35:29.63#ibcon#read 5, iclass 31, count 0 2006.285.07:35:29.63#ibcon#about to read 6, iclass 31, count 0 2006.285.07:35:29.63#ibcon#read 6, iclass 31, count 0 2006.285.07:35:29.63#ibcon#end of sib2, iclass 31, count 0 2006.285.07:35:29.63#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:35:29.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:35:29.63#ibcon#[27=USB\r\n] 2006.285.07:35:29.63#ibcon#*before write, iclass 31, count 0 2006.285.07:35:29.63#ibcon#enter sib2, iclass 31, count 0 2006.285.07:35:29.63#ibcon#flushed, iclass 31, count 0 2006.285.07:35:29.63#ibcon#about to write, iclass 31, count 0 2006.285.07:35:29.63#ibcon#wrote, iclass 31, count 0 2006.285.07:35:29.63#ibcon#about to read 3, iclass 31, count 0 2006.285.07:35:29.66#ibcon#read 3, iclass 31, count 0 2006.285.07:35:29.66#ibcon#about to read 4, iclass 31, count 0 2006.285.07:35:29.66#ibcon#read 4, iclass 31, count 0 2006.285.07:35:29.66#ibcon#about to read 5, iclass 31, count 0 2006.285.07:35:29.66#ibcon#read 5, iclass 31, count 0 2006.285.07:35:29.66#ibcon#about to read 6, iclass 31, count 0 2006.285.07:35:29.66#ibcon#read 6, iclass 31, count 0 2006.285.07:35:29.66#ibcon#end of sib2, iclass 31, count 0 2006.285.07:35:29.66#ibcon#*after write, iclass 31, count 0 2006.285.07:35:29.66#ibcon#*before return 0, iclass 31, count 0 2006.285.07:35:29.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:35:29.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:35:29.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:35:29.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:35:29.66$vck44/vblo=7,734.99 2006.285.07:35:29.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.07:35:29.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.07:35:29.66#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:29.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:35:29.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:35:29.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:35:29.66#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:35:29.66#ibcon#first serial, iclass 33, count 0 2006.285.07:35:29.66#ibcon#enter sib2, iclass 33, count 0 2006.285.07:35:29.66#ibcon#flushed, iclass 33, count 0 2006.285.07:35:29.66#ibcon#about to write, iclass 33, count 0 2006.285.07:35:29.66#ibcon#wrote, iclass 33, count 0 2006.285.07:35:29.66#ibcon#about to read 3, iclass 33, count 0 2006.285.07:35:29.68#ibcon#read 3, iclass 33, count 0 2006.285.07:35:29.68#ibcon#about to read 4, iclass 33, count 0 2006.285.07:35:29.68#ibcon#read 4, iclass 33, count 0 2006.285.07:35:29.68#ibcon#about to read 5, iclass 33, count 0 2006.285.07:35:29.68#ibcon#read 5, iclass 33, count 0 2006.285.07:35:29.68#ibcon#about to read 6, iclass 33, count 0 2006.285.07:35:29.68#ibcon#read 6, iclass 33, count 0 2006.285.07:35:29.68#ibcon#end of sib2, iclass 33, count 0 2006.285.07:35:29.68#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:35:29.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:35:29.68#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:35:29.68#ibcon#*before write, iclass 33, count 0 2006.285.07:35:29.68#ibcon#enter sib2, iclass 33, count 0 2006.285.07:35:29.68#ibcon#flushed, iclass 33, count 0 2006.285.07:35:29.68#ibcon#about to write, iclass 33, count 0 2006.285.07:35:29.68#ibcon#wrote, iclass 33, count 0 2006.285.07:35:29.68#ibcon#about to read 3, iclass 33, count 0 2006.285.07:35:29.72#ibcon#read 3, iclass 33, count 0 2006.285.07:35:29.72#ibcon#about to read 4, iclass 33, count 0 2006.285.07:35:29.72#ibcon#read 4, iclass 33, count 0 2006.285.07:35:29.72#ibcon#about to read 5, iclass 33, count 0 2006.285.07:35:29.72#ibcon#read 5, iclass 33, count 0 2006.285.07:35:29.72#ibcon#about to read 6, iclass 33, count 0 2006.285.07:35:29.72#ibcon#read 6, iclass 33, count 0 2006.285.07:35:29.72#ibcon#end of sib2, iclass 33, count 0 2006.285.07:35:29.72#ibcon#*after write, iclass 33, count 0 2006.285.07:35:29.72#ibcon#*before return 0, iclass 33, count 0 2006.285.07:35:29.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:35:29.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:35:29.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:35:29.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:35:29.72$vck44/vb=7,4 2006.285.07:35:29.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.07:35:29.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.07:35:29.72#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:29.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:35:29.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:35:29.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:35:29.78#ibcon#enter wrdev, iclass 35, count 2 2006.285.07:35:29.78#ibcon#first serial, iclass 35, count 2 2006.285.07:35:29.78#ibcon#enter sib2, iclass 35, count 2 2006.285.07:35:29.78#ibcon#flushed, iclass 35, count 2 2006.285.07:35:29.78#ibcon#about to write, iclass 35, count 2 2006.285.07:35:29.78#ibcon#wrote, iclass 35, count 2 2006.285.07:35:29.78#ibcon#about to read 3, iclass 35, count 2 2006.285.07:35:29.80#ibcon#read 3, iclass 35, count 2 2006.285.07:35:29.80#ibcon#about to read 4, iclass 35, count 2 2006.285.07:35:29.80#ibcon#read 4, iclass 35, count 2 2006.285.07:35:29.80#ibcon#about to read 5, iclass 35, count 2 2006.285.07:35:29.80#ibcon#read 5, iclass 35, count 2 2006.285.07:35:29.80#ibcon#about to read 6, iclass 35, count 2 2006.285.07:35:29.80#ibcon#read 6, iclass 35, count 2 2006.285.07:35:29.80#ibcon#end of sib2, iclass 35, count 2 2006.285.07:35:29.80#ibcon#*mode == 0, iclass 35, count 2 2006.285.07:35:29.80#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.07:35:29.80#ibcon#[27=AT07-04\r\n] 2006.285.07:35:29.80#ibcon#*before write, iclass 35, count 2 2006.285.07:35:29.80#ibcon#enter sib2, iclass 35, count 2 2006.285.07:35:29.80#ibcon#flushed, iclass 35, count 2 2006.285.07:35:29.80#ibcon#about to write, iclass 35, count 2 2006.285.07:35:29.80#ibcon#wrote, iclass 35, count 2 2006.285.07:35:29.80#ibcon#about to read 3, iclass 35, count 2 2006.285.07:35:29.83#ibcon#read 3, iclass 35, count 2 2006.285.07:35:29.83#ibcon#about to read 4, iclass 35, count 2 2006.285.07:35:29.83#ibcon#read 4, iclass 35, count 2 2006.285.07:35:29.83#ibcon#about to read 5, iclass 35, count 2 2006.285.07:35:29.83#ibcon#read 5, iclass 35, count 2 2006.285.07:35:29.83#ibcon#about to read 6, iclass 35, count 2 2006.285.07:35:29.83#ibcon#read 6, iclass 35, count 2 2006.285.07:35:29.83#ibcon#end of sib2, iclass 35, count 2 2006.285.07:35:29.83#ibcon#*after write, iclass 35, count 2 2006.285.07:35:29.83#ibcon#*before return 0, iclass 35, count 2 2006.285.07:35:29.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:35:29.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:35:29.83#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.07:35:29.83#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:29.83#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:35:29.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:35:29.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:35:29.95#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:35:29.95#ibcon#first serial, iclass 35, count 0 2006.285.07:35:29.95#ibcon#enter sib2, iclass 35, count 0 2006.285.07:35:29.95#ibcon#flushed, iclass 35, count 0 2006.285.07:35:29.95#ibcon#about to write, iclass 35, count 0 2006.285.07:35:29.95#ibcon#wrote, iclass 35, count 0 2006.285.07:35:29.95#ibcon#about to read 3, iclass 35, count 0 2006.285.07:35:29.97#ibcon#read 3, iclass 35, count 0 2006.285.07:35:29.97#ibcon#about to read 4, iclass 35, count 0 2006.285.07:35:29.97#ibcon#read 4, iclass 35, count 0 2006.285.07:35:29.97#ibcon#about to read 5, iclass 35, count 0 2006.285.07:35:29.97#ibcon#read 5, iclass 35, count 0 2006.285.07:35:29.97#ibcon#about to read 6, iclass 35, count 0 2006.285.07:35:29.97#ibcon#read 6, iclass 35, count 0 2006.285.07:35:29.97#ibcon#end of sib2, iclass 35, count 0 2006.285.07:35:29.97#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:35:29.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:35:29.97#ibcon#[27=USB\r\n] 2006.285.07:35:29.97#ibcon#*before write, iclass 35, count 0 2006.285.07:35:29.97#ibcon#enter sib2, iclass 35, count 0 2006.285.07:35:29.97#ibcon#flushed, iclass 35, count 0 2006.285.07:35:29.97#ibcon#about to write, iclass 35, count 0 2006.285.07:35:29.97#ibcon#wrote, iclass 35, count 0 2006.285.07:35:29.97#ibcon#about to read 3, iclass 35, count 0 2006.285.07:35:30.00#ibcon#read 3, iclass 35, count 0 2006.285.07:35:30.00#ibcon#about to read 4, iclass 35, count 0 2006.285.07:35:30.00#ibcon#read 4, iclass 35, count 0 2006.285.07:35:30.00#ibcon#about to read 5, iclass 35, count 0 2006.285.07:35:30.00#ibcon#read 5, iclass 35, count 0 2006.285.07:35:30.00#ibcon#about to read 6, iclass 35, count 0 2006.285.07:35:30.00#ibcon#read 6, iclass 35, count 0 2006.285.07:35:30.00#ibcon#end of sib2, iclass 35, count 0 2006.285.07:35:30.00#ibcon#*after write, iclass 35, count 0 2006.285.07:35:30.00#ibcon#*before return 0, iclass 35, count 0 2006.285.07:35:30.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:35:30.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:35:30.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:35:30.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:35:30.00$vck44/vblo=8,744.99 2006.285.07:35:30.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.07:35:30.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.07:35:30.00#ibcon#ireg 17 cls_cnt 0 2006.285.07:35:30.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:35:30.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:35:30.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:35:30.00#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:35:30.00#ibcon#first serial, iclass 37, count 0 2006.285.07:35:30.00#ibcon#enter sib2, iclass 37, count 0 2006.285.07:35:30.00#ibcon#flushed, iclass 37, count 0 2006.285.07:35:30.00#ibcon#about to write, iclass 37, count 0 2006.285.07:35:30.00#ibcon#wrote, iclass 37, count 0 2006.285.07:35:30.00#ibcon#about to read 3, iclass 37, count 0 2006.285.07:35:30.02#ibcon#read 3, iclass 37, count 0 2006.285.07:35:30.02#ibcon#about to read 4, iclass 37, count 0 2006.285.07:35:30.02#ibcon#read 4, iclass 37, count 0 2006.285.07:35:30.02#ibcon#about to read 5, iclass 37, count 0 2006.285.07:35:30.02#ibcon#read 5, iclass 37, count 0 2006.285.07:35:30.02#ibcon#about to read 6, iclass 37, count 0 2006.285.07:35:30.02#ibcon#read 6, iclass 37, count 0 2006.285.07:35:30.02#ibcon#end of sib2, iclass 37, count 0 2006.285.07:35:30.02#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:35:30.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:35:30.02#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:35:30.02#ibcon#*before write, iclass 37, count 0 2006.285.07:35:30.02#ibcon#enter sib2, iclass 37, count 0 2006.285.07:35:30.02#ibcon#flushed, iclass 37, count 0 2006.285.07:35:30.02#ibcon#about to write, iclass 37, count 0 2006.285.07:35:30.02#ibcon#wrote, iclass 37, count 0 2006.285.07:35:30.02#ibcon#about to read 3, iclass 37, count 0 2006.285.07:35:30.06#ibcon#read 3, iclass 37, count 0 2006.285.07:35:30.06#ibcon#about to read 4, iclass 37, count 0 2006.285.07:35:30.06#ibcon#read 4, iclass 37, count 0 2006.285.07:35:30.06#ibcon#about to read 5, iclass 37, count 0 2006.285.07:35:30.06#ibcon#read 5, iclass 37, count 0 2006.285.07:35:30.06#ibcon#about to read 6, iclass 37, count 0 2006.285.07:35:30.06#ibcon#read 6, iclass 37, count 0 2006.285.07:35:30.06#ibcon#end of sib2, iclass 37, count 0 2006.285.07:35:30.06#ibcon#*after write, iclass 37, count 0 2006.285.07:35:30.06#ibcon#*before return 0, iclass 37, count 0 2006.285.07:35:30.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:35:30.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:35:30.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:35:30.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:35:30.06$vck44/vb=8,4 2006.285.07:35:30.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.07:35:30.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.07:35:30.06#ibcon#ireg 11 cls_cnt 2 2006.285.07:35:30.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:35:30.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:35:30.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:35:30.12#ibcon#enter wrdev, iclass 39, count 2 2006.285.07:35:30.12#ibcon#first serial, iclass 39, count 2 2006.285.07:35:30.12#ibcon#enter sib2, iclass 39, count 2 2006.285.07:35:30.12#ibcon#flushed, iclass 39, count 2 2006.285.07:35:30.12#ibcon#about to write, iclass 39, count 2 2006.285.07:35:30.12#ibcon#wrote, iclass 39, count 2 2006.285.07:35:30.12#ibcon#about to read 3, iclass 39, count 2 2006.285.07:35:30.14#ibcon#read 3, iclass 39, count 2 2006.285.07:35:30.14#ibcon#about to read 4, iclass 39, count 2 2006.285.07:35:30.14#ibcon#read 4, iclass 39, count 2 2006.285.07:35:30.14#ibcon#about to read 5, iclass 39, count 2 2006.285.07:35:30.14#ibcon#read 5, iclass 39, count 2 2006.285.07:35:30.14#ibcon#about to read 6, iclass 39, count 2 2006.285.07:35:30.14#ibcon#read 6, iclass 39, count 2 2006.285.07:35:30.14#ibcon#end of sib2, iclass 39, count 2 2006.285.07:35:30.14#ibcon#*mode == 0, iclass 39, count 2 2006.285.07:35:30.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.07:35:30.14#ibcon#[27=AT08-04\r\n] 2006.285.07:35:30.14#ibcon#*before write, iclass 39, count 2 2006.285.07:35:30.14#ibcon#enter sib2, iclass 39, count 2 2006.285.07:35:30.14#ibcon#flushed, iclass 39, count 2 2006.285.07:35:30.14#ibcon#about to write, iclass 39, count 2 2006.285.07:35:30.14#ibcon#wrote, iclass 39, count 2 2006.285.07:35:30.14#ibcon#about to read 3, iclass 39, count 2 2006.285.07:35:30.17#ibcon#read 3, iclass 39, count 2 2006.285.07:35:30.17#ibcon#about to read 4, iclass 39, count 2 2006.285.07:35:30.17#ibcon#read 4, iclass 39, count 2 2006.285.07:35:30.17#ibcon#about to read 5, iclass 39, count 2 2006.285.07:35:30.17#ibcon#read 5, iclass 39, count 2 2006.285.07:35:30.17#ibcon#about to read 6, iclass 39, count 2 2006.285.07:35:30.17#ibcon#read 6, iclass 39, count 2 2006.285.07:35:30.17#ibcon#end of sib2, iclass 39, count 2 2006.285.07:35:30.17#ibcon#*after write, iclass 39, count 2 2006.285.07:35:30.17#ibcon#*before return 0, iclass 39, count 2 2006.285.07:35:30.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:35:30.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:35:30.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.07:35:30.17#ibcon#ireg 7 cls_cnt 0 2006.285.07:35:30.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:35:30.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:35:30.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:35:30.29#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:35:30.29#ibcon#first serial, iclass 39, count 0 2006.285.07:35:30.29#ibcon#enter sib2, iclass 39, count 0 2006.285.07:35:30.29#ibcon#flushed, iclass 39, count 0 2006.285.07:35:30.29#ibcon#about to write, iclass 39, count 0 2006.285.07:35:30.29#ibcon#wrote, iclass 39, count 0 2006.285.07:35:30.29#ibcon#about to read 3, iclass 39, count 0 2006.285.07:35:30.31#ibcon#read 3, iclass 39, count 0 2006.285.07:35:30.31#ibcon#about to read 4, iclass 39, count 0 2006.285.07:35:30.31#ibcon#read 4, iclass 39, count 0 2006.285.07:35:30.31#ibcon#about to read 5, iclass 39, count 0 2006.285.07:35:30.31#ibcon#read 5, iclass 39, count 0 2006.285.07:35:30.31#ibcon#about to read 6, iclass 39, count 0 2006.285.07:35:30.31#ibcon#read 6, iclass 39, count 0 2006.285.07:35:30.31#ibcon#end of sib2, iclass 39, count 0 2006.285.07:35:30.31#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:35:30.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:35:30.31#ibcon#[27=USB\r\n] 2006.285.07:35:30.31#ibcon#*before write, iclass 39, count 0 2006.285.07:35:30.31#ibcon#enter sib2, iclass 39, count 0 2006.285.07:35:30.31#ibcon#flushed, iclass 39, count 0 2006.285.07:35:30.31#ibcon#about to write, iclass 39, count 0 2006.285.07:35:30.31#ibcon#wrote, iclass 39, count 0 2006.285.07:35:30.31#ibcon#about to read 3, iclass 39, count 0 2006.285.07:35:30.34#ibcon#read 3, iclass 39, count 0 2006.285.07:35:30.34#ibcon#about to read 4, iclass 39, count 0 2006.285.07:35:30.34#ibcon#read 4, iclass 39, count 0 2006.285.07:35:30.34#ibcon#about to read 5, iclass 39, count 0 2006.285.07:35:30.34#ibcon#read 5, iclass 39, count 0 2006.285.07:35:30.34#ibcon#about to read 6, iclass 39, count 0 2006.285.07:35:30.34#ibcon#read 6, iclass 39, count 0 2006.285.07:35:30.34#ibcon#end of sib2, iclass 39, count 0 2006.285.07:35:30.34#ibcon#*after write, iclass 39, count 0 2006.285.07:35:30.34#ibcon#*before return 0, iclass 39, count 0 2006.285.07:35:30.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:35:30.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:35:30.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:35:30.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:35:30.34$vck44/vabw=wide 2006.285.07:35:30.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.07:35:30.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.07:35:30.34#ibcon#ireg 8 cls_cnt 0 2006.285.07:35:30.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:35:30.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:35:30.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:35:30.34#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:35:30.34#ibcon#first serial, iclass 3, count 0 2006.285.07:35:30.34#ibcon#enter sib2, iclass 3, count 0 2006.285.07:35:30.34#ibcon#flushed, iclass 3, count 0 2006.285.07:35:30.34#ibcon#about to write, iclass 3, count 0 2006.285.07:35:30.34#ibcon#wrote, iclass 3, count 0 2006.285.07:35:30.34#ibcon#about to read 3, iclass 3, count 0 2006.285.07:35:30.36#ibcon#read 3, iclass 3, count 0 2006.285.07:35:30.36#ibcon#about to read 4, iclass 3, count 0 2006.285.07:35:30.36#ibcon#read 4, iclass 3, count 0 2006.285.07:35:30.36#ibcon#about to read 5, iclass 3, count 0 2006.285.07:35:30.36#ibcon#read 5, iclass 3, count 0 2006.285.07:35:30.36#ibcon#about to read 6, iclass 3, count 0 2006.285.07:35:30.36#ibcon#read 6, iclass 3, count 0 2006.285.07:35:30.36#ibcon#end of sib2, iclass 3, count 0 2006.285.07:35:30.36#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:35:30.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:35:30.36#ibcon#[25=BW32\r\n] 2006.285.07:35:30.36#ibcon#*before write, iclass 3, count 0 2006.285.07:35:30.36#ibcon#enter sib2, iclass 3, count 0 2006.285.07:35:30.36#ibcon#flushed, iclass 3, count 0 2006.285.07:35:30.36#ibcon#about to write, iclass 3, count 0 2006.285.07:35:30.36#ibcon#wrote, iclass 3, count 0 2006.285.07:35:30.36#ibcon#about to read 3, iclass 3, count 0 2006.285.07:35:30.39#ibcon#read 3, iclass 3, count 0 2006.285.07:35:30.39#ibcon#about to read 4, iclass 3, count 0 2006.285.07:35:30.39#ibcon#read 4, iclass 3, count 0 2006.285.07:35:30.39#ibcon#about to read 5, iclass 3, count 0 2006.285.07:35:30.39#ibcon#read 5, iclass 3, count 0 2006.285.07:35:30.39#ibcon#about to read 6, iclass 3, count 0 2006.285.07:35:30.39#ibcon#read 6, iclass 3, count 0 2006.285.07:35:30.39#ibcon#end of sib2, iclass 3, count 0 2006.285.07:35:30.39#ibcon#*after write, iclass 3, count 0 2006.285.07:35:30.39#ibcon#*before return 0, iclass 3, count 0 2006.285.07:35:30.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:35:30.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:35:30.39#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:35:30.39#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:35:30.39$vck44/vbbw=wide 2006.285.07:35:30.39#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.07:35:30.39#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.07:35:30.39#ibcon#ireg 8 cls_cnt 0 2006.285.07:35:30.39#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:35:30.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:35:30.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:35:30.46#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:35:30.46#ibcon#first serial, iclass 5, count 0 2006.285.07:35:30.46#ibcon#enter sib2, iclass 5, count 0 2006.285.07:35:30.46#ibcon#flushed, iclass 5, count 0 2006.285.07:35:30.46#ibcon#about to write, iclass 5, count 0 2006.285.07:35:30.46#ibcon#wrote, iclass 5, count 0 2006.285.07:35:30.46#ibcon#about to read 3, iclass 5, count 0 2006.285.07:35:30.48#ibcon#read 3, iclass 5, count 0 2006.285.07:35:30.48#ibcon#about to read 4, iclass 5, count 0 2006.285.07:35:30.48#ibcon#read 4, iclass 5, count 0 2006.285.07:35:30.48#ibcon#about to read 5, iclass 5, count 0 2006.285.07:35:30.48#ibcon#read 5, iclass 5, count 0 2006.285.07:35:30.48#ibcon#about to read 6, iclass 5, count 0 2006.285.07:35:30.48#ibcon#read 6, iclass 5, count 0 2006.285.07:35:30.48#ibcon#end of sib2, iclass 5, count 0 2006.285.07:35:30.48#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:35:30.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:35:30.48#ibcon#[27=BW32\r\n] 2006.285.07:35:30.48#ibcon#*before write, iclass 5, count 0 2006.285.07:35:30.48#ibcon#enter sib2, iclass 5, count 0 2006.285.07:35:30.48#ibcon#flushed, iclass 5, count 0 2006.285.07:35:30.48#ibcon#about to write, iclass 5, count 0 2006.285.07:35:30.48#ibcon#wrote, iclass 5, count 0 2006.285.07:35:30.48#ibcon#about to read 3, iclass 5, count 0 2006.285.07:35:30.51#ibcon#read 3, iclass 5, count 0 2006.285.07:35:30.51#ibcon#about to read 4, iclass 5, count 0 2006.285.07:35:30.51#ibcon#read 4, iclass 5, count 0 2006.285.07:35:30.51#ibcon#about to read 5, iclass 5, count 0 2006.285.07:35:30.51#ibcon#read 5, iclass 5, count 0 2006.285.07:35:30.51#ibcon#about to read 6, iclass 5, count 0 2006.285.07:35:30.51#ibcon#read 6, iclass 5, count 0 2006.285.07:35:30.51#ibcon#end of sib2, iclass 5, count 0 2006.285.07:35:30.51#ibcon#*after write, iclass 5, count 0 2006.285.07:35:30.51#ibcon#*before return 0, iclass 5, count 0 2006.285.07:35:30.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:35:30.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:35:30.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:35:30.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:35:30.51$setupk4/ifdk4 2006.285.07:35:30.51$ifdk4/lo= 2006.285.07:35:30.51$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:35:30.51$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:35:30.51$ifdk4/patch= 2006.285.07:35:30.51$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:35:30.51$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:35:30.51$setupk4/!*+20s 2006.285.07:35:35.67#abcon#<5=/04 2.7 4.8 23.58 771014.4\r\n> 2006.285.07:35:35.69#abcon#{5=INTERFACE CLEAR} 2006.285.07:35:35.75#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:35:45.02$setupk4/"tpicd 2006.285.07:35:45.02$setupk4/echo=off 2006.285.07:35:45.02$setupk4/xlog=off 2006.285.07:35:45.02:!2006.285.07:36:56 2006.285.07:35:51.14#trakl#Source acquired 2006.285.07:35:52.14#flagr#flagr/antenna,acquired 2006.285.07:36:56.02:preob 2006.285.07:36:57.15/onsource/TRACKING 2006.285.07:36:57.15:!2006.285.07:37:06 2006.285.07:37:06.02:"tape 2006.285.07:37:06.02:"st=record 2006.285.07:37:06.02:data_valid=on 2006.285.07:37:06.02:midob 2006.285.07:37:07.15/onsource/TRACKING 2006.285.07:37:07.15/wx/23.54,1014.4,77 2006.285.07:37:07.29/cable/+6.4731E-03 2006.285.07:37:08.38/va/01,07,usb,yes,33,36 2006.285.07:37:08.38/va/02,06,usb,yes,33,34 2006.285.07:37:08.38/va/03,07,usb,yes,33,35 2006.285.07:37:08.39/va/04,06,usb,yes,34,36 2006.285.07:37:08.39/va/05,03,usb,yes,34,34 2006.285.07:37:08.39/va/06,04,usb,yes,31,30 2006.285.07:37:08.39/va/07,04,usb,yes,31,32 2006.285.07:37:08.39/va/08,03,usb,yes,32,39 2006.285.07:37:08.61/valo/01,524.99,yes,locked 2006.285.07:37:08.61/valo/02,534.99,yes,locked 2006.285.07:37:08.61/valo/03,564.99,yes,locked 2006.285.07:37:08.61/valo/04,624.99,yes,locked 2006.285.07:37:08.61/valo/05,734.99,yes,locked 2006.285.07:37:08.62/valo/06,814.99,yes,locked 2006.285.07:37:08.62/valo/07,864.99,yes,locked 2006.285.07:37:08.62/valo/08,884.99,yes,locked 2006.285.07:37:09.70/vb/01,04,usb,yes,32,30 2006.285.07:37:09.70/vb/02,05,usb,yes,30,30 2006.285.07:37:09.70/vb/03,04,usb,yes,31,34 2006.285.07:37:09.70/vb/04,05,usb,yes,31,30 2006.285.07:37:09.71/vb/05,04,usb,yes,28,30 2006.285.07:37:09.71/vb/06,03,usb,yes,40,35 2006.285.07:37:09.71/vb/07,04,usb,yes,32,32 2006.285.07:37:09.71/vb/08,04,usb,yes,29,33 2006.285.07:37:09.94/vblo/01,629.99,yes,locked 2006.285.07:37:09.94/vblo/02,634.99,yes,locked 2006.285.07:37:09.95/vblo/03,649.99,yes,locked 2006.285.07:37:09.95/vblo/04,679.99,yes,locked 2006.285.07:37:09.95/vblo/05,709.99,yes,locked 2006.285.07:37:09.95/vblo/06,719.99,yes,locked 2006.285.07:37:09.95/vblo/07,734.99,yes,locked 2006.285.07:37:09.95/vblo/08,744.99,yes,locked 2006.285.07:37:10.09/vabw/8 2006.285.07:37:10.24/vbbw/8 2006.285.07:37:10.33/xfe/off,on,12.2 2006.285.07:37:10.70/ifatt/23,28,28,28 2006.285.07:37:11.07/fmout-gps/S +2.71E-07 2006.285.07:37:11.09:!2006.285.07:37:46 2006.285.07:37:46.00:data_valid=off 2006.285.07:37:46.01:"et 2006.285.07:37:46.01:!+3s 2006.285.07:37:49.02:"tape 2006.285.07:37:49.02:postob 2006.285.07:37:49.15/cable/+6.4718E-03 2006.285.07:37:49.16/wx/23.52,1014.3,77 2006.285.07:37:50.07/fmout-gps/S +2.69E-07 2006.285.07:37:50.08:scan_name=285-0738,jd0610,120 2006.285.07:37:50.08:source=2128-123,213135.26,-120704.8,2000.0,ccw 2006.285.07:37:50.15#flagr#flagr/antenna,new-source 2006.285.07:37:51.15:checkk5 2006.285.07:37:51.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:37:51.97/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:37:52.39/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:37:52.79/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:37:53.37/chk_obsdata//k5ts1/T2850737??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.07:37:53.75/chk_obsdata//k5ts2/T2850737??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.07:37:54.14/chk_obsdata//k5ts3/T2850737??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.07:37:54.58/chk_obsdata//k5ts4/T2850737??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.07:37:55.41/k5log//k5ts1_log_newline 2006.285.07:37:56.37/k5log//k5ts2_log_newline 2006.285.07:37:57.30/k5log//k5ts3_log_newline 2006.285.07:37:58.03/k5log//k5ts4_log_newline 2006.285.07:37:58.05/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:37:58.05:setupk4=1 2006.285.07:37:58.05$setupk4/echo=on 2006.285.07:37:58.05$setupk4/pcalon 2006.285.07:37:58.05$pcalon/"no phase cal control is implemented here 2006.285.07:37:58.05$setupk4/"tpicd=stop 2006.285.07:37:58.05$setupk4/"rec=synch_on 2006.285.07:37:58.05$setupk4/"rec_mode=128 2006.285.07:37:58.05$setupk4/!* 2006.285.07:37:58.05$setupk4/recpk4 2006.285.07:37:58.05$recpk4/recpatch= 2006.285.07:37:58.05$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:37:58.05$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:37:58.05$setupk4/vck44 2006.285.07:37:58.05$vck44/valo=1,524.99 2006.285.07:37:58.06#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.07:37:58.06#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.07:37:58.06#ibcon#ireg 17 cls_cnt 0 2006.285.07:37:58.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:37:58.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:37:58.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:37:58.06#ibcon#enter wrdev, iclass 32, count 0 2006.285.07:37:58.06#ibcon#first serial, iclass 32, count 0 2006.285.07:37:58.06#ibcon#enter sib2, iclass 32, count 0 2006.285.07:37:58.06#ibcon#flushed, iclass 32, count 0 2006.285.07:37:58.06#ibcon#about to write, iclass 32, count 0 2006.285.07:37:58.06#ibcon#wrote, iclass 32, count 0 2006.285.07:37:58.06#ibcon#about to read 3, iclass 32, count 0 2006.285.07:37:58.07#ibcon#read 3, iclass 32, count 0 2006.285.07:37:58.07#ibcon#about to read 4, iclass 32, count 0 2006.285.07:37:58.07#ibcon#read 4, iclass 32, count 0 2006.285.07:37:58.07#ibcon#about to read 5, iclass 32, count 0 2006.285.07:37:58.07#ibcon#read 5, iclass 32, count 0 2006.285.07:37:58.07#ibcon#about to read 6, iclass 32, count 0 2006.285.07:37:58.07#ibcon#read 6, iclass 32, count 0 2006.285.07:37:58.07#ibcon#end of sib2, iclass 32, count 0 2006.285.07:37:58.07#ibcon#*mode == 0, iclass 32, count 0 2006.285.07:37:58.07#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.07:37:58.07#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:37:58.07#ibcon#*before write, iclass 32, count 0 2006.285.07:37:58.07#ibcon#enter sib2, iclass 32, count 0 2006.285.07:37:58.07#ibcon#flushed, iclass 32, count 0 2006.285.07:37:58.07#ibcon#about to write, iclass 32, count 0 2006.285.07:37:58.07#ibcon#wrote, iclass 32, count 0 2006.285.07:37:58.07#ibcon#about to read 3, iclass 32, count 0 2006.285.07:37:58.12#ibcon#read 3, iclass 32, count 0 2006.285.07:37:58.12#ibcon#about to read 4, iclass 32, count 0 2006.285.07:37:58.12#ibcon#read 4, iclass 32, count 0 2006.285.07:37:58.12#ibcon#about to read 5, iclass 32, count 0 2006.285.07:37:58.12#ibcon#read 5, iclass 32, count 0 2006.285.07:37:58.12#ibcon#about to read 6, iclass 32, count 0 2006.285.07:37:58.12#ibcon#read 6, iclass 32, count 0 2006.285.07:37:58.12#ibcon#end of sib2, iclass 32, count 0 2006.285.07:37:58.12#ibcon#*after write, iclass 32, count 0 2006.285.07:37:58.12#ibcon#*before return 0, iclass 32, count 0 2006.285.07:37:58.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:37:58.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:37:58.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.07:37:58.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.07:37:58.13$vck44/va=1,7 2006.285.07:37:58.13#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.07:37:58.13#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.07:37:58.13#ibcon#ireg 11 cls_cnt 2 2006.285.07:37:58.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:37:58.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:37:58.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:37:58.13#ibcon#enter wrdev, iclass 34, count 2 2006.285.07:37:58.13#ibcon#first serial, iclass 34, count 2 2006.285.07:37:58.13#ibcon#enter sib2, iclass 34, count 2 2006.285.07:37:58.13#ibcon#flushed, iclass 34, count 2 2006.285.07:37:58.13#ibcon#about to write, iclass 34, count 2 2006.285.07:37:58.13#ibcon#wrote, iclass 34, count 2 2006.285.07:37:58.13#ibcon#about to read 3, iclass 34, count 2 2006.285.07:37:58.15#ibcon#read 3, iclass 34, count 2 2006.285.07:37:58.15#ibcon#about to read 4, iclass 34, count 2 2006.285.07:37:58.15#ibcon#read 4, iclass 34, count 2 2006.285.07:37:58.15#ibcon#about to read 5, iclass 34, count 2 2006.285.07:37:58.15#ibcon#read 5, iclass 34, count 2 2006.285.07:37:58.15#ibcon#about to read 6, iclass 34, count 2 2006.285.07:37:58.15#ibcon#read 6, iclass 34, count 2 2006.285.07:37:58.15#ibcon#end of sib2, iclass 34, count 2 2006.285.07:37:58.15#ibcon#*mode == 0, iclass 34, count 2 2006.285.07:37:58.15#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.07:37:58.15#ibcon#[25=AT01-07\r\n] 2006.285.07:37:58.15#ibcon#*before write, iclass 34, count 2 2006.285.07:37:58.15#ibcon#enter sib2, iclass 34, count 2 2006.285.07:37:58.15#ibcon#flushed, iclass 34, count 2 2006.285.07:37:58.15#ibcon#about to write, iclass 34, count 2 2006.285.07:37:58.15#ibcon#wrote, iclass 34, count 2 2006.285.07:37:58.15#ibcon#about to read 3, iclass 34, count 2 2006.285.07:37:58.17#ibcon#read 3, iclass 34, count 2 2006.285.07:37:58.17#ibcon#about to read 4, iclass 34, count 2 2006.285.07:37:58.17#ibcon#read 4, iclass 34, count 2 2006.285.07:37:58.17#ibcon#about to read 5, iclass 34, count 2 2006.285.07:37:58.17#ibcon#read 5, iclass 34, count 2 2006.285.07:37:58.17#ibcon#about to read 6, iclass 34, count 2 2006.285.07:37:58.17#ibcon#read 6, iclass 34, count 2 2006.285.07:37:58.17#ibcon#end of sib2, iclass 34, count 2 2006.285.07:37:58.17#ibcon#*after write, iclass 34, count 2 2006.285.07:37:58.17#ibcon#*before return 0, iclass 34, count 2 2006.285.07:37:58.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:37:58.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:37:58.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.07:37:58.17#ibcon#ireg 7 cls_cnt 0 2006.285.07:37:58.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:37:58.22#abcon#<5=/05 2.7 4.8 23.52 771014.3\r\n> 2006.285.07:37:58.24#abcon#{5=INTERFACE CLEAR} 2006.285.07:37:58.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:37:58.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:37:58.29#ibcon#enter wrdev, iclass 34, count 0 2006.285.07:37:58.29#ibcon#first serial, iclass 34, count 0 2006.285.07:37:58.29#ibcon#enter sib2, iclass 34, count 0 2006.285.07:37:58.29#ibcon#flushed, iclass 34, count 0 2006.285.07:37:58.29#ibcon#about to write, iclass 34, count 0 2006.285.07:37:58.29#ibcon#wrote, iclass 34, count 0 2006.285.07:37:58.29#ibcon#about to read 3, iclass 34, count 0 2006.285.07:37:58.30#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:37:58.31#ibcon#read 3, iclass 34, count 0 2006.285.07:37:58.31#ibcon#about to read 4, iclass 34, count 0 2006.285.07:37:58.31#ibcon#read 4, iclass 34, count 0 2006.285.07:37:58.31#ibcon#about to read 5, iclass 34, count 0 2006.285.07:37:58.31#ibcon#read 5, iclass 34, count 0 2006.285.07:37:58.31#ibcon#about to read 6, iclass 34, count 0 2006.285.07:37:58.31#ibcon#read 6, iclass 34, count 0 2006.285.07:37:58.31#ibcon#end of sib2, iclass 34, count 0 2006.285.07:37:58.31#ibcon#*mode == 0, iclass 34, count 0 2006.285.07:37:58.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.07:37:58.31#ibcon#[25=USB\r\n] 2006.285.07:37:58.31#ibcon#*before write, iclass 34, count 0 2006.285.07:37:58.31#ibcon#enter sib2, iclass 34, count 0 2006.285.07:37:58.31#ibcon#flushed, iclass 34, count 0 2006.285.07:37:58.31#ibcon#about to write, iclass 34, count 0 2006.285.07:37:58.31#ibcon#wrote, iclass 34, count 0 2006.285.07:37:58.31#ibcon#about to read 3, iclass 34, count 0 2006.285.07:37:58.34#ibcon#read 3, iclass 34, count 0 2006.285.07:37:58.34#ibcon#about to read 4, iclass 34, count 0 2006.285.07:37:58.34#ibcon#read 4, iclass 34, count 0 2006.285.07:37:58.34#ibcon#about to read 5, iclass 34, count 0 2006.285.07:37:58.34#ibcon#read 5, iclass 34, count 0 2006.285.07:37:58.34#ibcon#about to read 6, iclass 34, count 0 2006.285.07:37:58.34#ibcon#read 6, iclass 34, count 0 2006.285.07:37:58.34#ibcon#end of sib2, iclass 34, count 0 2006.285.07:37:58.34#ibcon#*after write, iclass 34, count 0 2006.285.07:37:58.34#ibcon#*before return 0, iclass 34, count 0 2006.285.07:37:58.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:37:58.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:37:58.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.07:37:58.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.07:37:58.35$vck44/valo=2,534.99 2006.285.07:37:58.35#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.07:37:58.35#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.07:37:58.35#ibcon#ireg 17 cls_cnt 0 2006.285.07:37:58.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:37:58.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:37:58.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:37:58.35#ibcon#enter wrdev, iclass 40, count 0 2006.285.07:37:58.35#ibcon#first serial, iclass 40, count 0 2006.285.07:37:58.35#ibcon#enter sib2, iclass 40, count 0 2006.285.07:37:58.35#ibcon#flushed, iclass 40, count 0 2006.285.07:37:58.35#ibcon#about to write, iclass 40, count 0 2006.285.07:37:58.35#ibcon#wrote, iclass 40, count 0 2006.285.07:37:58.35#ibcon#about to read 3, iclass 40, count 0 2006.285.07:37:58.36#ibcon#read 3, iclass 40, count 0 2006.285.07:37:58.36#ibcon#about to read 4, iclass 40, count 0 2006.285.07:37:58.36#ibcon#read 4, iclass 40, count 0 2006.285.07:37:58.36#ibcon#about to read 5, iclass 40, count 0 2006.285.07:37:58.36#ibcon#read 5, iclass 40, count 0 2006.285.07:37:58.36#ibcon#about to read 6, iclass 40, count 0 2006.285.07:37:58.36#ibcon#read 6, iclass 40, count 0 2006.285.07:37:58.36#ibcon#end of sib2, iclass 40, count 0 2006.285.07:37:58.36#ibcon#*mode == 0, iclass 40, count 0 2006.285.07:37:58.36#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.07:37:58.36#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:37:58.36#ibcon#*before write, iclass 40, count 0 2006.285.07:37:58.36#ibcon#enter sib2, iclass 40, count 0 2006.285.07:37:58.36#ibcon#flushed, iclass 40, count 0 2006.285.07:37:58.36#ibcon#about to write, iclass 40, count 0 2006.285.07:37:58.36#ibcon#wrote, iclass 40, count 0 2006.285.07:37:58.37#ibcon#about to read 3, iclass 40, count 0 2006.285.07:37:58.40#ibcon#read 3, iclass 40, count 0 2006.285.07:37:58.40#ibcon#about to read 4, iclass 40, count 0 2006.285.07:37:58.40#ibcon#read 4, iclass 40, count 0 2006.285.07:37:58.40#ibcon#about to read 5, iclass 40, count 0 2006.285.07:37:58.40#ibcon#read 5, iclass 40, count 0 2006.285.07:37:58.40#ibcon#about to read 6, iclass 40, count 0 2006.285.07:37:58.40#ibcon#read 6, iclass 40, count 0 2006.285.07:37:58.40#ibcon#end of sib2, iclass 40, count 0 2006.285.07:37:58.40#ibcon#*after write, iclass 40, count 0 2006.285.07:37:58.40#ibcon#*before return 0, iclass 40, count 0 2006.285.07:37:58.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:37:58.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:37:58.40#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.07:37:58.40#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.07:37:58.41$vck44/va=2,6 2006.285.07:37:58.41#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.07:37:58.41#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.07:37:58.41#ibcon#ireg 11 cls_cnt 2 2006.285.07:37:58.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:37:58.45#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:37:58.45#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:37:58.45#ibcon#enter wrdev, iclass 4, count 2 2006.285.07:37:58.45#ibcon#first serial, iclass 4, count 2 2006.285.07:37:58.45#ibcon#enter sib2, iclass 4, count 2 2006.285.07:37:58.45#ibcon#flushed, iclass 4, count 2 2006.285.07:37:58.45#ibcon#about to write, iclass 4, count 2 2006.285.07:37:58.45#ibcon#wrote, iclass 4, count 2 2006.285.07:37:58.45#ibcon#about to read 3, iclass 4, count 2 2006.285.07:37:58.47#ibcon#read 3, iclass 4, count 2 2006.285.07:37:58.47#ibcon#about to read 4, iclass 4, count 2 2006.285.07:37:58.47#ibcon#read 4, iclass 4, count 2 2006.285.07:37:58.47#ibcon#about to read 5, iclass 4, count 2 2006.285.07:37:58.47#ibcon#read 5, iclass 4, count 2 2006.285.07:37:58.47#ibcon#about to read 6, iclass 4, count 2 2006.285.07:37:58.47#ibcon#read 6, iclass 4, count 2 2006.285.07:37:58.47#ibcon#end of sib2, iclass 4, count 2 2006.285.07:37:58.47#ibcon#*mode == 0, iclass 4, count 2 2006.285.07:37:58.47#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.07:37:58.47#ibcon#[25=AT02-06\r\n] 2006.285.07:37:58.47#ibcon#*before write, iclass 4, count 2 2006.285.07:37:58.47#ibcon#enter sib2, iclass 4, count 2 2006.285.07:37:58.47#ibcon#flushed, iclass 4, count 2 2006.285.07:37:58.47#ibcon#about to write, iclass 4, count 2 2006.285.07:37:58.47#ibcon#wrote, iclass 4, count 2 2006.285.07:37:58.47#ibcon#about to read 3, iclass 4, count 2 2006.285.07:37:58.50#ibcon#read 3, iclass 4, count 2 2006.285.07:37:58.50#ibcon#about to read 4, iclass 4, count 2 2006.285.07:37:58.50#ibcon#read 4, iclass 4, count 2 2006.285.07:37:58.50#ibcon#about to read 5, iclass 4, count 2 2006.285.07:37:58.50#ibcon#read 5, iclass 4, count 2 2006.285.07:37:58.50#ibcon#about to read 6, iclass 4, count 2 2006.285.07:37:58.50#ibcon#read 6, iclass 4, count 2 2006.285.07:37:58.50#ibcon#end of sib2, iclass 4, count 2 2006.285.07:37:58.50#ibcon#*after write, iclass 4, count 2 2006.285.07:37:58.50#ibcon#*before return 0, iclass 4, count 2 2006.285.07:37:58.50#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:37:58.50#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:37:58.50#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.07:37:58.50#ibcon#ireg 7 cls_cnt 0 2006.285.07:37:58.50#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:37:58.62#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:37:58.62#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:37:58.62#ibcon#enter wrdev, iclass 4, count 0 2006.285.07:37:58.62#ibcon#first serial, iclass 4, count 0 2006.285.07:37:58.62#ibcon#enter sib2, iclass 4, count 0 2006.285.07:37:58.62#ibcon#flushed, iclass 4, count 0 2006.285.07:37:58.62#ibcon#about to write, iclass 4, count 0 2006.285.07:37:58.62#ibcon#wrote, iclass 4, count 0 2006.285.07:37:58.62#ibcon#about to read 3, iclass 4, count 0 2006.285.07:37:58.64#ibcon#read 3, iclass 4, count 0 2006.285.07:37:58.64#ibcon#about to read 4, iclass 4, count 0 2006.285.07:37:58.64#ibcon#read 4, iclass 4, count 0 2006.285.07:37:58.64#ibcon#about to read 5, iclass 4, count 0 2006.285.07:37:58.64#ibcon#read 5, iclass 4, count 0 2006.285.07:37:58.64#ibcon#about to read 6, iclass 4, count 0 2006.285.07:37:58.64#ibcon#read 6, iclass 4, count 0 2006.285.07:37:58.64#ibcon#end of sib2, iclass 4, count 0 2006.285.07:37:58.64#ibcon#*mode == 0, iclass 4, count 0 2006.285.07:37:58.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.07:37:58.64#ibcon#[25=USB\r\n] 2006.285.07:37:58.64#ibcon#*before write, iclass 4, count 0 2006.285.07:37:58.64#ibcon#enter sib2, iclass 4, count 0 2006.285.07:37:58.64#ibcon#flushed, iclass 4, count 0 2006.285.07:37:58.64#ibcon#about to write, iclass 4, count 0 2006.285.07:37:58.64#ibcon#wrote, iclass 4, count 0 2006.285.07:37:58.64#ibcon#about to read 3, iclass 4, count 0 2006.285.07:37:58.67#ibcon#read 3, iclass 4, count 0 2006.285.07:37:58.67#ibcon#about to read 4, iclass 4, count 0 2006.285.07:37:58.67#ibcon#read 4, iclass 4, count 0 2006.285.07:37:58.67#ibcon#about to read 5, iclass 4, count 0 2006.285.07:37:58.67#ibcon#read 5, iclass 4, count 0 2006.285.07:37:58.67#ibcon#about to read 6, iclass 4, count 0 2006.285.07:37:58.67#ibcon#read 6, iclass 4, count 0 2006.285.07:37:58.67#ibcon#end of sib2, iclass 4, count 0 2006.285.07:37:58.67#ibcon#*after write, iclass 4, count 0 2006.285.07:37:58.67#ibcon#*before return 0, iclass 4, count 0 2006.285.07:37:58.67#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:37:58.67#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:37:58.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.07:37:58.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.07:37:58.68$vck44/valo=3,564.99 2006.285.07:37:58.68#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.07:37:58.68#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.07:37:58.68#ibcon#ireg 17 cls_cnt 0 2006.285.07:37:58.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:37:58.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:37:58.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:37:58.68#ibcon#enter wrdev, iclass 6, count 0 2006.285.07:37:58.68#ibcon#first serial, iclass 6, count 0 2006.285.07:37:58.68#ibcon#enter sib2, iclass 6, count 0 2006.285.07:37:58.68#ibcon#flushed, iclass 6, count 0 2006.285.07:37:58.68#ibcon#about to write, iclass 6, count 0 2006.285.07:37:58.68#ibcon#wrote, iclass 6, count 0 2006.285.07:37:58.68#ibcon#about to read 3, iclass 6, count 0 2006.285.07:37:58.69#ibcon#read 3, iclass 6, count 0 2006.285.07:37:58.69#ibcon#about to read 4, iclass 6, count 0 2006.285.07:37:58.69#ibcon#read 4, iclass 6, count 0 2006.285.07:37:58.69#ibcon#about to read 5, iclass 6, count 0 2006.285.07:37:58.69#ibcon#read 5, iclass 6, count 0 2006.285.07:37:58.69#ibcon#about to read 6, iclass 6, count 0 2006.285.07:37:58.69#ibcon#read 6, iclass 6, count 0 2006.285.07:37:58.69#ibcon#end of sib2, iclass 6, count 0 2006.285.07:37:58.69#ibcon#*mode == 0, iclass 6, count 0 2006.285.07:37:58.69#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.07:37:58.69#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:37:58.69#ibcon#*before write, iclass 6, count 0 2006.285.07:37:58.69#ibcon#enter sib2, iclass 6, count 0 2006.285.07:37:58.69#ibcon#flushed, iclass 6, count 0 2006.285.07:37:58.69#ibcon#about to write, iclass 6, count 0 2006.285.07:37:58.69#ibcon#wrote, iclass 6, count 0 2006.285.07:37:58.69#ibcon#about to read 3, iclass 6, count 0 2006.285.07:37:58.73#ibcon#read 3, iclass 6, count 0 2006.285.07:37:58.73#ibcon#about to read 4, iclass 6, count 0 2006.285.07:37:58.73#ibcon#read 4, iclass 6, count 0 2006.285.07:37:58.73#ibcon#about to read 5, iclass 6, count 0 2006.285.07:37:58.73#ibcon#read 5, iclass 6, count 0 2006.285.07:37:58.73#ibcon#about to read 6, iclass 6, count 0 2006.285.07:37:58.73#ibcon#read 6, iclass 6, count 0 2006.285.07:37:58.73#ibcon#end of sib2, iclass 6, count 0 2006.285.07:37:58.73#ibcon#*after write, iclass 6, count 0 2006.285.07:37:58.73#ibcon#*before return 0, iclass 6, count 0 2006.285.07:37:58.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:37:58.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:37:58.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.07:37:58.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.07:37:58.74$vck44/va=3,7 2006.285.07:37:58.74#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.07:37:58.74#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.07:37:58.74#ibcon#ireg 11 cls_cnt 2 2006.285.07:37:58.74#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:37:58.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:37:58.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:37:58.78#ibcon#enter wrdev, iclass 10, count 2 2006.285.07:37:58.78#ibcon#first serial, iclass 10, count 2 2006.285.07:37:58.78#ibcon#enter sib2, iclass 10, count 2 2006.285.07:37:58.78#ibcon#flushed, iclass 10, count 2 2006.285.07:37:58.78#ibcon#about to write, iclass 10, count 2 2006.285.07:37:58.78#ibcon#wrote, iclass 10, count 2 2006.285.07:37:58.78#ibcon#about to read 3, iclass 10, count 2 2006.285.07:37:58.80#ibcon#read 3, iclass 10, count 2 2006.285.07:37:58.80#ibcon#about to read 4, iclass 10, count 2 2006.285.07:37:58.80#ibcon#read 4, iclass 10, count 2 2006.285.07:37:58.80#ibcon#about to read 5, iclass 10, count 2 2006.285.07:37:58.80#ibcon#read 5, iclass 10, count 2 2006.285.07:37:58.80#ibcon#about to read 6, iclass 10, count 2 2006.285.07:37:58.80#ibcon#read 6, iclass 10, count 2 2006.285.07:37:58.80#ibcon#end of sib2, iclass 10, count 2 2006.285.07:37:58.80#ibcon#*mode == 0, iclass 10, count 2 2006.285.07:37:58.80#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.07:37:58.80#ibcon#[25=AT03-07\r\n] 2006.285.07:37:58.80#ibcon#*before write, iclass 10, count 2 2006.285.07:37:58.80#ibcon#enter sib2, iclass 10, count 2 2006.285.07:37:58.80#ibcon#flushed, iclass 10, count 2 2006.285.07:37:58.80#ibcon#about to write, iclass 10, count 2 2006.285.07:37:58.80#ibcon#wrote, iclass 10, count 2 2006.285.07:37:58.80#ibcon#about to read 3, iclass 10, count 2 2006.285.07:37:58.83#ibcon#read 3, iclass 10, count 2 2006.285.07:37:58.83#ibcon#about to read 4, iclass 10, count 2 2006.285.07:37:58.83#ibcon#read 4, iclass 10, count 2 2006.285.07:37:58.83#ibcon#about to read 5, iclass 10, count 2 2006.285.07:37:58.83#ibcon#read 5, iclass 10, count 2 2006.285.07:37:58.83#ibcon#about to read 6, iclass 10, count 2 2006.285.07:37:58.83#ibcon#read 6, iclass 10, count 2 2006.285.07:37:58.83#ibcon#end of sib2, iclass 10, count 2 2006.285.07:37:58.83#ibcon#*after write, iclass 10, count 2 2006.285.07:37:58.83#ibcon#*before return 0, iclass 10, count 2 2006.285.07:37:58.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:37:58.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:37:58.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.07:37:58.83#ibcon#ireg 7 cls_cnt 0 2006.285.07:37:58.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:37:58.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:37:58.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:37:58.95#ibcon#enter wrdev, iclass 10, count 0 2006.285.07:37:58.95#ibcon#first serial, iclass 10, count 0 2006.285.07:37:58.95#ibcon#enter sib2, iclass 10, count 0 2006.285.07:37:58.95#ibcon#flushed, iclass 10, count 0 2006.285.07:37:58.95#ibcon#about to write, iclass 10, count 0 2006.285.07:37:58.95#ibcon#wrote, iclass 10, count 0 2006.285.07:37:58.95#ibcon#about to read 3, iclass 10, count 0 2006.285.07:37:58.97#ibcon#read 3, iclass 10, count 0 2006.285.07:37:58.97#ibcon#about to read 4, iclass 10, count 0 2006.285.07:37:58.97#ibcon#read 4, iclass 10, count 0 2006.285.07:37:58.97#ibcon#about to read 5, iclass 10, count 0 2006.285.07:37:58.97#ibcon#read 5, iclass 10, count 0 2006.285.07:37:58.97#ibcon#about to read 6, iclass 10, count 0 2006.285.07:37:58.97#ibcon#read 6, iclass 10, count 0 2006.285.07:37:58.97#ibcon#end of sib2, iclass 10, count 0 2006.285.07:37:58.97#ibcon#*mode == 0, iclass 10, count 0 2006.285.07:37:58.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.07:37:58.97#ibcon#[25=USB\r\n] 2006.285.07:37:58.97#ibcon#*before write, iclass 10, count 0 2006.285.07:37:58.97#ibcon#enter sib2, iclass 10, count 0 2006.285.07:37:58.97#ibcon#flushed, iclass 10, count 0 2006.285.07:37:58.97#ibcon#about to write, iclass 10, count 0 2006.285.07:37:58.97#ibcon#wrote, iclass 10, count 0 2006.285.07:37:58.97#ibcon#about to read 3, iclass 10, count 0 2006.285.07:37:59.00#ibcon#read 3, iclass 10, count 0 2006.285.07:37:59.00#ibcon#about to read 4, iclass 10, count 0 2006.285.07:37:59.00#ibcon#read 4, iclass 10, count 0 2006.285.07:37:59.00#ibcon#about to read 5, iclass 10, count 0 2006.285.07:37:59.00#ibcon#read 5, iclass 10, count 0 2006.285.07:37:59.00#ibcon#about to read 6, iclass 10, count 0 2006.285.07:37:59.00#ibcon#read 6, iclass 10, count 0 2006.285.07:37:59.00#ibcon#end of sib2, iclass 10, count 0 2006.285.07:37:59.00#ibcon#*after write, iclass 10, count 0 2006.285.07:37:59.00#ibcon#*before return 0, iclass 10, count 0 2006.285.07:37:59.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:37:59.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:37:59.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.07:37:59.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.07:37:59.01$vck44/valo=4,624.99 2006.285.07:37:59.01#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.07:37:59.01#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.07:37:59.01#ibcon#ireg 17 cls_cnt 0 2006.285.07:37:59.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:37:59.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:37:59.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:37:59.01#ibcon#enter wrdev, iclass 12, count 0 2006.285.07:37:59.01#ibcon#first serial, iclass 12, count 0 2006.285.07:37:59.01#ibcon#enter sib2, iclass 12, count 0 2006.285.07:37:59.01#ibcon#flushed, iclass 12, count 0 2006.285.07:37:59.01#ibcon#about to write, iclass 12, count 0 2006.285.07:37:59.01#ibcon#wrote, iclass 12, count 0 2006.285.07:37:59.01#ibcon#about to read 3, iclass 12, count 0 2006.285.07:37:59.02#ibcon#read 3, iclass 12, count 0 2006.285.07:37:59.02#ibcon#about to read 4, iclass 12, count 0 2006.285.07:37:59.02#ibcon#read 4, iclass 12, count 0 2006.285.07:37:59.02#ibcon#about to read 5, iclass 12, count 0 2006.285.07:37:59.02#ibcon#read 5, iclass 12, count 0 2006.285.07:37:59.02#ibcon#about to read 6, iclass 12, count 0 2006.285.07:37:59.02#ibcon#read 6, iclass 12, count 0 2006.285.07:37:59.02#ibcon#end of sib2, iclass 12, count 0 2006.285.07:37:59.02#ibcon#*mode == 0, iclass 12, count 0 2006.285.07:37:59.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.07:37:59.02#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:37:59.02#ibcon#*before write, iclass 12, count 0 2006.285.07:37:59.02#ibcon#enter sib2, iclass 12, count 0 2006.285.07:37:59.02#ibcon#flushed, iclass 12, count 0 2006.285.07:37:59.02#ibcon#about to write, iclass 12, count 0 2006.285.07:37:59.02#ibcon#wrote, iclass 12, count 0 2006.285.07:37:59.02#ibcon#about to read 3, iclass 12, count 0 2006.285.07:37:59.06#ibcon#read 3, iclass 12, count 0 2006.285.07:37:59.06#ibcon#about to read 4, iclass 12, count 0 2006.285.07:37:59.06#ibcon#read 4, iclass 12, count 0 2006.285.07:37:59.06#ibcon#about to read 5, iclass 12, count 0 2006.285.07:37:59.06#ibcon#read 5, iclass 12, count 0 2006.285.07:37:59.06#ibcon#about to read 6, iclass 12, count 0 2006.285.07:37:59.06#ibcon#read 6, iclass 12, count 0 2006.285.07:37:59.06#ibcon#end of sib2, iclass 12, count 0 2006.285.07:37:59.06#ibcon#*after write, iclass 12, count 0 2006.285.07:37:59.06#ibcon#*before return 0, iclass 12, count 0 2006.285.07:37:59.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:37:59.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:37:59.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.07:37:59.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.07:37:59.07$vck44/va=4,6 2006.285.07:37:59.07#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.07:37:59.07#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.07:37:59.07#ibcon#ireg 11 cls_cnt 2 2006.285.07:37:59.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:37:59.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:37:59.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:37:59.11#ibcon#enter wrdev, iclass 14, count 2 2006.285.07:37:59.11#ibcon#first serial, iclass 14, count 2 2006.285.07:37:59.11#ibcon#enter sib2, iclass 14, count 2 2006.285.07:37:59.11#ibcon#flushed, iclass 14, count 2 2006.285.07:37:59.11#ibcon#about to write, iclass 14, count 2 2006.285.07:37:59.11#ibcon#wrote, iclass 14, count 2 2006.285.07:37:59.11#ibcon#about to read 3, iclass 14, count 2 2006.285.07:37:59.13#ibcon#read 3, iclass 14, count 2 2006.285.07:37:59.13#ibcon#about to read 4, iclass 14, count 2 2006.285.07:37:59.13#ibcon#read 4, iclass 14, count 2 2006.285.07:37:59.13#ibcon#about to read 5, iclass 14, count 2 2006.285.07:37:59.13#ibcon#read 5, iclass 14, count 2 2006.285.07:37:59.13#ibcon#about to read 6, iclass 14, count 2 2006.285.07:37:59.13#ibcon#read 6, iclass 14, count 2 2006.285.07:37:59.13#ibcon#end of sib2, iclass 14, count 2 2006.285.07:37:59.13#ibcon#*mode == 0, iclass 14, count 2 2006.285.07:37:59.13#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.07:37:59.13#ibcon#[25=AT04-06\r\n] 2006.285.07:37:59.13#ibcon#*before write, iclass 14, count 2 2006.285.07:37:59.13#ibcon#enter sib2, iclass 14, count 2 2006.285.07:37:59.13#ibcon#flushed, iclass 14, count 2 2006.285.07:37:59.13#ibcon#about to write, iclass 14, count 2 2006.285.07:37:59.13#ibcon#wrote, iclass 14, count 2 2006.285.07:37:59.13#ibcon#about to read 3, iclass 14, count 2 2006.285.07:37:59.16#ibcon#read 3, iclass 14, count 2 2006.285.07:37:59.16#ibcon#about to read 4, iclass 14, count 2 2006.285.07:37:59.16#ibcon#read 4, iclass 14, count 2 2006.285.07:37:59.16#ibcon#about to read 5, iclass 14, count 2 2006.285.07:37:59.16#ibcon#read 5, iclass 14, count 2 2006.285.07:37:59.16#ibcon#about to read 6, iclass 14, count 2 2006.285.07:37:59.16#ibcon#read 6, iclass 14, count 2 2006.285.07:37:59.16#ibcon#end of sib2, iclass 14, count 2 2006.285.07:37:59.16#ibcon#*after write, iclass 14, count 2 2006.285.07:37:59.16#ibcon#*before return 0, iclass 14, count 2 2006.285.07:37:59.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:37:59.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:37:59.16#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.07:37:59.16#ibcon#ireg 7 cls_cnt 0 2006.285.07:37:59.16#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:37:59.28#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:37:59.28#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:37:59.28#ibcon#enter wrdev, iclass 14, count 0 2006.285.07:37:59.28#ibcon#first serial, iclass 14, count 0 2006.285.07:37:59.28#ibcon#enter sib2, iclass 14, count 0 2006.285.07:37:59.28#ibcon#flushed, iclass 14, count 0 2006.285.07:37:59.28#ibcon#about to write, iclass 14, count 0 2006.285.07:37:59.28#ibcon#wrote, iclass 14, count 0 2006.285.07:37:59.28#ibcon#about to read 3, iclass 14, count 0 2006.285.07:37:59.30#ibcon#read 3, iclass 14, count 0 2006.285.07:37:59.30#ibcon#about to read 4, iclass 14, count 0 2006.285.07:37:59.30#ibcon#read 4, iclass 14, count 0 2006.285.07:37:59.30#ibcon#about to read 5, iclass 14, count 0 2006.285.07:37:59.30#ibcon#read 5, iclass 14, count 0 2006.285.07:37:59.30#ibcon#about to read 6, iclass 14, count 0 2006.285.07:37:59.30#ibcon#read 6, iclass 14, count 0 2006.285.07:37:59.30#ibcon#end of sib2, iclass 14, count 0 2006.285.07:37:59.30#ibcon#*mode == 0, iclass 14, count 0 2006.285.07:37:59.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.07:37:59.30#ibcon#[25=USB\r\n] 2006.285.07:37:59.30#ibcon#*before write, iclass 14, count 0 2006.285.07:37:59.30#ibcon#enter sib2, iclass 14, count 0 2006.285.07:37:59.30#ibcon#flushed, iclass 14, count 0 2006.285.07:37:59.30#ibcon#about to write, iclass 14, count 0 2006.285.07:37:59.30#ibcon#wrote, iclass 14, count 0 2006.285.07:37:59.30#ibcon#about to read 3, iclass 14, count 0 2006.285.07:37:59.33#ibcon#read 3, iclass 14, count 0 2006.285.07:37:59.33#ibcon#about to read 4, iclass 14, count 0 2006.285.07:37:59.33#ibcon#read 4, iclass 14, count 0 2006.285.07:37:59.33#ibcon#about to read 5, iclass 14, count 0 2006.285.07:37:59.33#ibcon#read 5, iclass 14, count 0 2006.285.07:37:59.33#ibcon#about to read 6, iclass 14, count 0 2006.285.07:37:59.33#ibcon#read 6, iclass 14, count 0 2006.285.07:37:59.33#ibcon#end of sib2, iclass 14, count 0 2006.285.07:37:59.33#ibcon#*after write, iclass 14, count 0 2006.285.07:37:59.33#ibcon#*before return 0, iclass 14, count 0 2006.285.07:37:59.33#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:37:59.33#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:37:59.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.07:37:59.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.07:37:59.34$vck44/valo=5,734.99 2006.285.07:37:59.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.07:37:59.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.07:37:59.34#ibcon#ireg 17 cls_cnt 0 2006.285.07:37:59.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:37:59.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:37:59.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:37:59.34#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:37:59.34#ibcon#first serial, iclass 16, count 0 2006.285.07:37:59.34#ibcon#enter sib2, iclass 16, count 0 2006.285.07:37:59.34#ibcon#flushed, iclass 16, count 0 2006.285.07:37:59.34#ibcon#about to write, iclass 16, count 0 2006.285.07:37:59.34#ibcon#wrote, iclass 16, count 0 2006.285.07:37:59.34#ibcon#about to read 3, iclass 16, count 0 2006.285.07:37:59.35#ibcon#read 3, iclass 16, count 0 2006.285.07:37:59.35#ibcon#about to read 4, iclass 16, count 0 2006.285.07:37:59.35#ibcon#read 4, iclass 16, count 0 2006.285.07:37:59.35#ibcon#about to read 5, iclass 16, count 0 2006.285.07:37:59.35#ibcon#read 5, iclass 16, count 0 2006.285.07:37:59.35#ibcon#about to read 6, iclass 16, count 0 2006.285.07:37:59.35#ibcon#read 6, iclass 16, count 0 2006.285.07:37:59.35#ibcon#end of sib2, iclass 16, count 0 2006.285.07:37:59.35#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:37:59.35#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:37:59.35#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:37:59.35#ibcon#*before write, iclass 16, count 0 2006.285.07:37:59.35#ibcon#enter sib2, iclass 16, count 0 2006.285.07:37:59.35#ibcon#flushed, iclass 16, count 0 2006.285.07:37:59.35#ibcon#about to write, iclass 16, count 0 2006.285.07:37:59.35#ibcon#wrote, iclass 16, count 0 2006.285.07:37:59.35#ibcon#about to read 3, iclass 16, count 0 2006.285.07:37:59.39#ibcon#read 3, iclass 16, count 0 2006.285.07:37:59.39#ibcon#about to read 4, iclass 16, count 0 2006.285.07:37:59.39#ibcon#read 4, iclass 16, count 0 2006.285.07:37:59.39#ibcon#about to read 5, iclass 16, count 0 2006.285.07:37:59.39#ibcon#read 5, iclass 16, count 0 2006.285.07:37:59.39#ibcon#about to read 6, iclass 16, count 0 2006.285.07:37:59.39#ibcon#read 6, iclass 16, count 0 2006.285.07:37:59.39#ibcon#end of sib2, iclass 16, count 0 2006.285.07:37:59.39#ibcon#*after write, iclass 16, count 0 2006.285.07:37:59.39#ibcon#*before return 0, iclass 16, count 0 2006.285.07:37:59.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:37:59.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:37:59.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:37:59.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:37:59.40$vck44/va=5,3 2006.285.07:37:59.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.07:37:59.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.07:37:59.40#ibcon#ireg 11 cls_cnt 2 2006.285.07:37:59.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:37:59.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:37:59.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:37:59.44#ibcon#enter wrdev, iclass 18, count 2 2006.285.07:37:59.44#ibcon#first serial, iclass 18, count 2 2006.285.07:37:59.44#ibcon#enter sib2, iclass 18, count 2 2006.285.07:37:59.44#ibcon#flushed, iclass 18, count 2 2006.285.07:37:59.44#ibcon#about to write, iclass 18, count 2 2006.285.07:37:59.44#ibcon#wrote, iclass 18, count 2 2006.285.07:37:59.44#ibcon#about to read 3, iclass 18, count 2 2006.285.07:37:59.46#ibcon#read 3, iclass 18, count 2 2006.285.07:37:59.46#ibcon#about to read 4, iclass 18, count 2 2006.285.07:37:59.46#ibcon#read 4, iclass 18, count 2 2006.285.07:37:59.46#ibcon#about to read 5, iclass 18, count 2 2006.285.07:37:59.46#ibcon#read 5, iclass 18, count 2 2006.285.07:37:59.46#ibcon#about to read 6, iclass 18, count 2 2006.285.07:37:59.46#ibcon#read 6, iclass 18, count 2 2006.285.07:37:59.46#ibcon#end of sib2, iclass 18, count 2 2006.285.07:37:59.46#ibcon#*mode == 0, iclass 18, count 2 2006.285.07:37:59.46#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.07:37:59.46#ibcon#[25=AT05-03\r\n] 2006.285.07:37:59.46#ibcon#*before write, iclass 18, count 2 2006.285.07:37:59.46#ibcon#enter sib2, iclass 18, count 2 2006.285.07:37:59.46#ibcon#flushed, iclass 18, count 2 2006.285.07:37:59.46#ibcon#about to write, iclass 18, count 2 2006.285.07:37:59.46#ibcon#wrote, iclass 18, count 2 2006.285.07:37:59.46#ibcon#about to read 3, iclass 18, count 2 2006.285.07:37:59.49#ibcon#read 3, iclass 18, count 2 2006.285.07:37:59.49#ibcon#about to read 4, iclass 18, count 2 2006.285.07:37:59.49#ibcon#read 4, iclass 18, count 2 2006.285.07:37:59.49#ibcon#about to read 5, iclass 18, count 2 2006.285.07:37:59.49#ibcon#read 5, iclass 18, count 2 2006.285.07:37:59.49#ibcon#about to read 6, iclass 18, count 2 2006.285.07:37:59.49#ibcon#read 6, iclass 18, count 2 2006.285.07:37:59.49#ibcon#end of sib2, iclass 18, count 2 2006.285.07:37:59.49#ibcon#*after write, iclass 18, count 2 2006.285.07:37:59.49#ibcon#*before return 0, iclass 18, count 2 2006.285.07:37:59.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:37:59.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:37:59.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.07:37:59.49#ibcon#ireg 7 cls_cnt 0 2006.285.07:37:59.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:37:59.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:37:59.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:37:59.61#ibcon#enter wrdev, iclass 18, count 0 2006.285.07:37:59.61#ibcon#first serial, iclass 18, count 0 2006.285.07:37:59.61#ibcon#enter sib2, iclass 18, count 0 2006.285.07:37:59.61#ibcon#flushed, iclass 18, count 0 2006.285.07:37:59.61#ibcon#about to write, iclass 18, count 0 2006.285.07:37:59.61#ibcon#wrote, iclass 18, count 0 2006.285.07:37:59.61#ibcon#about to read 3, iclass 18, count 0 2006.285.07:37:59.63#ibcon#read 3, iclass 18, count 0 2006.285.07:37:59.63#ibcon#about to read 4, iclass 18, count 0 2006.285.07:37:59.63#ibcon#read 4, iclass 18, count 0 2006.285.07:37:59.63#ibcon#about to read 5, iclass 18, count 0 2006.285.07:37:59.63#ibcon#read 5, iclass 18, count 0 2006.285.07:37:59.63#ibcon#about to read 6, iclass 18, count 0 2006.285.07:37:59.63#ibcon#read 6, iclass 18, count 0 2006.285.07:37:59.63#ibcon#end of sib2, iclass 18, count 0 2006.285.07:37:59.63#ibcon#*mode == 0, iclass 18, count 0 2006.285.07:37:59.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.07:37:59.63#ibcon#[25=USB\r\n] 2006.285.07:37:59.63#ibcon#*before write, iclass 18, count 0 2006.285.07:37:59.63#ibcon#enter sib2, iclass 18, count 0 2006.285.07:37:59.63#ibcon#flushed, iclass 18, count 0 2006.285.07:37:59.63#ibcon#about to write, iclass 18, count 0 2006.285.07:37:59.63#ibcon#wrote, iclass 18, count 0 2006.285.07:37:59.63#ibcon#about to read 3, iclass 18, count 0 2006.285.07:37:59.66#ibcon#read 3, iclass 18, count 0 2006.285.07:37:59.66#ibcon#about to read 4, iclass 18, count 0 2006.285.07:37:59.66#ibcon#read 4, iclass 18, count 0 2006.285.07:37:59.66#ibcon#about to read 5, iclass 18, count 0 2006.285.07:37:59.66#ibcon#read 5, iclass 18, count 0 2006.285.07:37:59.66#ibcon#about to read 6, iclass 18, count 0 2006.285.07:37:59.66#ibcon#read 6, iclass 18, count 0 2006.285.07:37:59.66#ibcon#end of sib2, iclass 18, count 0 2006.285.07:37:59.66#ibcon#*after write, iclass 18, count 0 2006.285.07:37:59.66#ibcon#*before return 0, iclass 18, count 0 2006.285.07:37:59.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:37:59.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:37:59.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.07:37:59.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.07:37:59.67$vck44/valo=6,814.99 2006.285.07:37:59.67#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.07:37:59.67#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.07:37:59.67#ibcon#ireg 17 cls_cnt 0 2006.285.07:37:59.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:37:59.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:37:59.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:37:59.67#ibcon#enter wrdev, iclass 20, count 0 2006.285.07:37:59.67#ibcon#first serial, iclass 20, count 0 2006.285.07:37:59.67#ibcon#enter sib2, iclass 20, count 0 2006.285.07:37:59.67#ibcon#flushed, iclass 20, count 0 2006.285.07:37:59.67#ibcon#about to write, iclass 20, count 0 2006.285.07:37:59.67#ibcon#wrote, iclass 20, count 0 2006.285.07:37:59.67#ibcon#about to read 3, iclass 20, count 0 2006.285.07:37:59.68#ibcon#read 3, iclass 20, count 0 2006.285.07:37:59.68#ibcon#about to read 4, iclass 20, count 0 2006.285.07:37:59.68#ibcon#read 4, iclass 20, count 0 2006.285.07:37:59.68#ibcon#about to read 5, iclass 20, count 0 2006.285.07:37:59.68#ibcon#read 5, iclass 20, count 0 2006.285.07:37:59.68#ibcon#about to read 6, iclass 20, count 0 2006.285.07:37:59.68#ibcon#read 6, iclass 20, count 0 2006.285.07:37:59.68#ibcon#end of sib2, iclass 20, count 0 2006.285.07:37:59.68#ibcon#*mode == 0, iclass 20, count 0 2006.285.07:37:59.68#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.07:37:59.68#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:37:59.68#ibcon#*before write, iclass 20, count 0 2006.285.07:37:59.68#ibcon#enter sib2, iclass 20, count 0 2006.285.07:37:59.68#ibcon#flushed, iclass 20, count 0 2006.285.07:37:59.68#ibcon#about to write, iclass 20, count 0 2006.285.07:37:59.68#ibcon#wrote, iclass 20, count 0 2006.285.07:37:59.68#ibcon#about to read 3, iclass 20, count 0 2006.285.07:37:59.72#ibcon#read 3, iclass 20, count 0 2006.285.07:37:59.72#ibcon#about to read 4, iclass 20, count 0 2006.285.07:37:59.72#ibcon#read 4, iclass 20, count 0 2006.285.07:37:59.72#ibcon#about to read 5, iclass 20, count 0 2006.285.07:37:59.72#ibcon#read 5, iclass 20, count 0 2006.285.07:37:59.72#ibcon#about to read 6, iclass 20, count 0 2006.285.07:37:59.72#ibcon#read 6, iclass 20, count 0 2006.285.07:37:59.72#ibcon#end of sib2, iclass 20, count 0 2006.285.07:37:59.72#ibcon#*after write, iclass 20, count 0 2006.285.07:37:59.72#ibcon#*before return 0, iclass 20, count 0 2006.285.07:37:59.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:37:59.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:37:59.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.07:37:59.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.07:37:59.73$vck44/va=6,4 2006.285.07:37:59.73#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.07:37:59.73#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.07:37:59.73#ibcon#ireg 11 cls_cnt 2 2006.285.07:37:59.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:37:59.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:37:59.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:37:59.77#ibcon#enter wrdev, iclass 22, count 2 2006.285.07:37:59.77#ibcon#first serial, iclass 22, count 2 2006.285.07:37:59.77#ibcon#enter sib2, iclass 22, count 2 2006.285.07:37:59.77#ibcon#flushed, iclass 22, count 2 2006.285.07:37:59.77#ibcon#about to write, iclass 22, count 2 2006.285.07:37:59.77#ibcon#wrote, iclass 22, count 2 2006.285.07:37:59.77#ibcon#about to read 3, iclass 22, count 2 2006.285.07:37:59.79#ibcon#read 3, iclass 22, count 2 2006.285.07:37:59.79#ibcon#about to read 4, iclass 22, count 2 2006.285.07:37:59.79#ibcon#read 4, iclass 22, count 2 2006.285.07:37:59.79#ibcon#about to read 5, iclass 22, count 2 2006.285.07:37:59.79#ibcon#read 5, iclass 22, count 2 2006.285.07:37:59.79#ibcon#about to read 6, iclass 22, count 2 2006.285.07:37:59.79#ibcon#read 6, iclass 22, count 2 2006.285.07:37:59.79#ibcon#end of sib2, iclass 22, count 2 2006.285.07:37:59.79#ibcon#*mode == 0, iclass 22, count 2 2006.285.07:37:59.79#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.07:37:59.79#ibcon#[25=AT06-04\r\n] 2006.285.07:37:59.79#ibcon#*before write, iclass 22, count 2 2006.285.07:37:59.79#ibcon#enter sib2, iclass 22, count 2 2006.285.07:37:59.79#ibcon#flushed, iclass 22, count 2 2006.285.07:37:59.79#ibcon#about to write, iclass 22, count 2 2006.285.07:37:59.79#ibcon#wrote, iclass 22, count 2 2006.285.07:37:59.79#ibcon#about to read 3, iclass 22, count 2 2006.285.07:37:59.82#ibcon#read 3, iclass 22, count 2 2006.285.07:37:59.82#ibcon#about to read 4, iclass 22, count 2 2006.285.07:37:59.82#ibcon#read 4, iclass 22, count 2 2006.285.07:37:59.82#ibcon#about to read 5, iclass 22, count 2 2006.285.07:37:59.82#ibcon#read 5, iclass 22, count 2 2006.285.07:37:59.82#ibcon#about to read 6, iclass 22, count 2 2006.285.07:37:59.82#ibcon#read 6, iclass 22, count 2 2006.285.07:37:59.82#ibcon#end of sib2, iclass 22, count 2 2006.285.07:37:59.82#ibcon#*after write, iclass 22, count 2 2006.285.07:37:59.82#ibcon#*before return 0, iclass 22, count 2 2006.285.07:37:59.82#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:37:59.82#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:37:59.82#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.07:37:59.82#ibcon#ireg 7 cls_cnt 0 2006.285.07:37:59.82#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:37:59.94#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:37:59.94#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:37:59.94#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:37:59.94#ibcon#first serial, iclass 22, count 0 2006.285.07:37:59.94#ibcon#enter sib2, iclass 22, count 0 2006.285.07:37:59.94#ibcon#flushed, iclass 22, count 0 2006.285.07:37:59.94#ibcon#about to write, iclass 22, count 0 2006.285.07:37:59.94#ibcon#wrote, iclass 22, count 0 2006.285.07:37:59.94#ibcon#about to read 3, iclass 22, count 0 2006.285.07:37:59.96#ibcon#read 3, iclass 22, count 0 2006.285.07:37:59.96#ibcon#about to read 4, iclass 22, count 0 2006.285.07:37:59.96#ibcon#read 4, iclass 22, count 0 2006.285.07:37:59.96#ibcon#about to read 5, iclass 22, count 0 2006.285.07:37:59.96#ibcon#read 5, iclass 22, count 0 2006.285.07:37:59.96#ibcon#about to read 6, iclass 22, count 0 2006.285.07:37:59.96#ibcon#read 6, iclass 22, count 0 2006.285.07:37:59.96#ibcon#end of sib2, iclass 22, count 0 2006.285.07:37:59.96#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:37:59.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:37:59.96#ibcon#[25=USB\r\n] 2006.285.07:37:59.96#ibcon#*before write, iclass 22, count 0 2006.285.07:37:59.96#ibcon#enter sib2, iclass 22, count 0 2006.285.07:37:59.96#ibcon#flushed, iclass 22, count 0 2006.285.07:37:59.96#ibcon#about to write, iclass 22, count 0 2006.285.07:37:59.96#ibcon#wrote, iclass 22, count 0 2006.285.07:37:59.96#ibcon#about to read 3, iclass 22, count 0 2006.285.07:37:59.99#ibcon#read 3, iclass 22, count 0 2006.285.07:37:59.99#ibcon#about to read 4, iclass 22, count 0 2006.285.07:37:59.99#ibcon#read 4, iclass 22, count 0 2006.285.07:37:59.99#ibcon#about to read 5, iclass 22, count 0 2006.285.07:37:59.99#ibcon#read 5, iclass 22, count 0 2006.285.07:37:59.99#ibcon#about to read 6, iclass 22, count 0 2006.285.07:37:59.99#ibcon#read 6, iclass 22, count 0 2006.285.07:37:59.99#ibcon#end of sib2, iclass 22, count 0 2006.285.07:37:59.99#ibcon#*after write, iclass 22, count 0 2006.285.07:37:59.99#ibcon#*before return 0, iclass 22, count 0 2006.285.07:37:59.99#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:37:59.99#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:37:59.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:37:59.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:38:00.00$vck44/valo=7,864.99 2006.285.07:38:00.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.07:38:00.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.07:38:00.00#ibcon#ireg 17 cls_cnt 0 2006.285.07:38:00.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:38:00.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:38:00.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:38:00.00#ibcon#enter wrdev, iclass 24, count 0 2006.285.07:38:00.00#ibcon#first serial, iclass 24, count 0 2006.285.07:38:00.00#ibcon#enter sib2, iclass 24, count 0 2006.285.07:38:00.00#ibcon#flushed, iclass 24, count 0 2006.285.07:38:00.00#ibcon#about to write, iclass 24, count 0 2006.285.07:38:00.00#ibcon#wrote, iclass 24, count 0 2006.285.07:38:00.00#ibcon#about to read 3, iclass 24, count 0 2006.285.07:38:00.01#ibcon#read 3, iclass 24, count 0 2006.285.07:38:00.01#ibcon#about to read 4, iclass 24, count 0 2006.285.07:38:00.01#ibcon#read 4, iclass 24, count 0 2006.285.07:38:00.01#ibcon#about to read 5, iclass 24, count 0 2006.285.07:38:00.01#ibcon#read 5, iclass 24, count 0 2006.285.07:38:00.01#ibcon#about to read 6, iclass 24, count 0 2006.285.07:38:00.01#ibcon#read 6, iclass 24, count 0 2006.285.07:38:00.01#ibcon#end of sib2, iclass 24, count 0 2006.285.07:38:00.01#ibcon#*mode == 0, iclass 24, count 0 2006.285.07:38:00.01#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.07:38:00.01#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:38:00.01#ibcon#*before write, iclass 24, count 0 2006.285.07:38:00.01#ibcon#enter sib2, iclass 24, count 0 2006.285.07:38:00.01#ibcon#flushed, iclass 24, count 0 2006.285.07:38:00.01#ibcon#about to write, iclass 24, count 0 2006.285.07:38:00.01#ibcon#wrote, iclass 24, count 0 2006.285.07:38:00.01#ibcon#about to read 3, iclass 24, count 0 2006.285.07:38:00.05#ibcon#read 3, iclass 24, count 0 2006.285.07:38:00.05#ibcon#about to read 4, iclass 24, count 0 2006.285.07:38:00.05#ibcon#read 4, iclass 24, count 0 2006.285.07:38:00.05#ibcon#about to read 5, iclass 24, count 0 2006.285.07:38:00.05#ibcon#read 5, iclass 24, count 0 2006.285.07:38:00.05#ibcon#about to read 6, iclass 24, count 0 2006.285.07:38:00.05#ibcon#read 6, iclass 24, count 0 2006.285.07:38:00.05#ibcon#end of sib2, iclass 24, count 0 2006.285.07:38:00.05#ibcon#*after write, iclass 24, count 0 2006.285.07:38:00.05#ibcon#*before return 0, iclass 24, count 0 2006.285.07:38:00.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:38:00.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:38:00.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.07:38:00.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.07:38:00.06$vck44/va=7,4 2006.285.07:38:00.06#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.07:38:00.06#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.07:38:00.06#ibcon#ireg 11 cls_cnt 2 2006.285.07:38:00.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:38:00.10#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:38:00.10#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:38:00.10#ibcon#enter wrdev, iclass 26, count 2 2006.285.07:38:00.10#ibcon#first serial, iclass 26, count 2 2006.285.07:38:00.10#ibcon#enter sib2, iclass 26, count 2 2006.285.07:38:00.10#ibcon#flushed, iclass 26, count 2 2006.285.07:38:00.10#ibcon#about to write, iclass 26, count 2 2006.285.07:38:00.10#ibcon#wrote, iclass 26, count 2 2006.285.07:38:00.10#ibcon#about to read 3, iclass 26, count 2 2006.285.07:38:00.12#ibcon#read 3, iclass 26, count 2 2006.285.07:38:00.12#ibcon#about to read 4, iclass 26, count 2 2006.285.07:38:00.12#ibcon#read 4, iclass 26, count 2 2006.285.07:38:00.12#ibcon#about to read 5, iclass 26, count 2 2006.285.07:38:00.12#ibcon#read 5, iclass 26, count 2 2006.285.07:38:00.12#ibcon#about to read 6, iclass 26, count 2 2006.285.07:38:00.12#ibcon#read 6, iclass 26, count 2 2006.285.07:38:00.12#ibcon#end of sib2, iclass 26, count 2 2006.285.07:38:00.12#ibcon#*mode == 0, iclass 26, count 2 2006.285.07:38:00.12#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.07:38:00.12#ibcon#[25=AT07-04\r\n] 2006.285.07:38:00.12#ibcon#*before write, iclass 26, count 2 2006.285.07:38:00.12#ibcon#enter sib2, iclass 26, count 2 2006.285.07:38:00.12#ibcon#flushed, iclass 26, count 2 2006.285.07:38:00.12#ibcon#about to write, iclass 26, count 2 2006.285.07:38:00.12#ibcon#wrote, iclass 26, count 2 2006.285.07:38:00.12#ibcon#about to read 3, iclass 26, count 2 2006.285.07:38:00.15#ibcon#read 3, iclass 26, count 2 2006.285.07:38:00.15#ibcon#about to read 4, iclass 26, count 2 2006.285.07:38:00.15#ibcon#read 4, iclass 26, count 2 2006.285.07:38:00.15#ibcon#about to read 5, iclass 26, count 2 2006.285.07:38:00.15#ibcon#read 5, iclass 26, count 2 2006.285.07:38:00.15#ibcon#about to read 6, iclass 26, count 2 2006.285.07:38:00.15#ibcon#read 6, iclass 26, count 2 2006.285.07:38:00.15#ibcon#end of sib2, iclass 26, count 2 2006.285.07:38:00.15#ibcon#*after write, iclass 26, count 2 2006.285.07:38:00.15#ibcon#*before return 0, iclass 26, count 2 2006.285.07:38:00.15#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:38:00.15#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:38:00.15#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.07:38:00.15#ibcon#ireg 7 cls_cnt 0 2006.285.07:38:00.15#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:38:00.27#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:38:00.27#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:38:00.27#ibcon#enter wrdev, iclass 26, count 0 2006.285.07:38:00.27#ibcon#first serial, iclass 26, count 0 2006.285.07:38:00.27#ibcon#enter sib2, iclass 26, count 0 2006.285.07:38:00.27#ibcon#flushed, iclass 26, count 0 2006.285.07:38:00.27#ibcon#about to write, iclass 26, count 0 2006.285.07:38:00.27#ibcon#wrote, iclass 26, count 0 2006.285.07:38:00.27#ibcon#about to read 3, iclass 26, count 0 2006.285.07:38:00.29#ibcon#read 3, iclass 26, count 0 2006.285.07:38:00.29#ibcon#about to read 4, iclass 26, count 0 2006.285.07:38:00.29#ibcon#read 4, iclass 26, count 0 2006.285.07:38:00.29#ibcon#about to read 5, iclass 26, count 0 2006.285.07:38:00.29#ibcon#read 5, iclass 26, count 0 2006.285.07:38:00.29#ibcon#about to read 6, iclass 26, count 0 2006.285.07:38:00.29#ibcon#read 6, iclass 26, count 0 2006.285.07:38:00.29#ibcon#end of sib2, iclass 26, count 0 2006.285.07:38:00.29#ibcon#*mode == 0, iclass 26, count 0 2006.285.07:38:00.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.07:38:00.29#ibcon#[25=USB\r\n] 2006.285.07:38:00.29#ibcon#*before write, iclass 26, count 0 2006.285.07:38:00.29#ibcon#enter sib2, iclass 26, count 0 2006.285.07:38:00.29#ibcon#flushed, iclass 26, count 0 2006.285.07:38:00.29#ibcon#about to write, iclass 26, count 0 2006.285.07:38:00.29#ibcon#wrote, iclass 26, count 0 2006.285.07:38:00.29#ibcon#about to read 3, iclass 26, count 0 2006.285.07:38:00.32#ibcon#read 3, iclass 26, count 0 2006.285.07:38:00.32#ibcon#about to read 4, iclass 26, count 0 2006.285.07:38:00.32#ibcon#read 4, iclass 26, count 0 2006.285.07:38:00.32#ibcon#about to read 5, iclass 26, count 0 2006.285.07:38:00.32#ibcon#read 5, iclass 26, count 0 2006.285.07:38:00.32#ibcon#about to read 6, iclass 26, count 0 2006.285.07:38:00.32#ibcon#read 6, iclass 26, count 0 2006.285.07:38:00.32#ibcon#end of sib2, iclass 26, count 0 2006.285.07:38:00.32#ibcon#*after write, iclass 26, count 0 2006.285.07:38:00.32#ibcon#*before return 0, iclass 26, count 0 2006.285.07:38:00.32#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:38:00.32#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:38:00.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.07:38:00.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.07:38:00.33$vck44/valo=8,884.99 2006.285.07:38:00.33#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.07:38:00.33#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.07:38:00.33#ibcon#ireg 17 cls_cnt 0 2006.285.07:38:00.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:38:00.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:38:00.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:38:00.33#ibcon#enter wrdev, iclass 28, count 0 2006.285.07:38:00.33#ibcon#first serial, iclass 28, count 0 2006.285.07:38:00.33#ibcon#enter sib2, iclass 28, count 0 2006.285.07:38:00.33#ibcon#flushed, iclass 28, count 0 2006.285.07:38:00.33#ibcon#about to write, iclass 28, count 0 2006.285.07:38:00.33#ibcon#wrote, iclass 28, count 0 2006.285.07:38:00.33#ibcon#about to read 3, iclass 28, count 0 2006.285.07:38:00.34#ibcon#read 3, iclass 28, count 0 2006.285.07:38:00.34#ibcon#about to read 4, iclass 28, count 0 2006.285.07:38:00.34#ibcon#read 4, iclass 28, count 0 2006.285.07:38:00.34#ibcon#about to read 5, iclass 28, count 0 2006.285.07:38:00.34#ibcon#read 5, iclass 28, count 0 2006.285.07:38:00.34#ibcon#about to read 6, iclass 28, count 0 2006.285.07:38:00.34#ibcon#read 6, iclass 28, count 0 2006.285.07:38:00.34#ibcon#end of sib2, iclass 28, count 0 2006.285.07:38:00.34#ibcon#*mode == 0, iclass 28, count 0 2006.285.07:38:00.34#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.07:38:00.34#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:38:00.34#ibcon#*before write, iclass 28, count 0 2006.285.07:38:00.34#ibcon#enter sib2, iclass 28, count 0 2006.285.07:38:00.34#ibcon#flushed, iclass 28, count 0 2006.285.07:38:00.34#ibcon#about to write, iclass 28, count 0 2006.285.07:38:00.34#ibcon#wrote, iclass 28, count 0 2006.285.07:38:00.34#ibcon#about to read 3, iclass 28, count 0 2006.285.07:38:00.38#ibcon#read 3, iclass 28, count 0 2006.285.07:38:00.38#ibcon#about to read 4, iclass 28, count 0 2006.285.07:38:00.38#ibcon#read 4, iclass 28, count 0 2006.285.07:38:00.38#ibcon#about to read 5, iclass 28, count 0 2006.285.07:38:00.38#ibcon#read 5, iclass 28, count 0 2006.285.07:38:00.38#ibcon#about to read 6, iclass 28, count 0 2006.285.07:38:00.38#ibcon#read 6, iclass 28, count 0 2006.285.07:38:00.38#ibcon#end of sib2, iclass 28, count 0 2006.285.07:38:00.38#ibcon#*after write, iclass 28, count 0 2006.285.07:38:00.38#ibcon#*before return 0, iclass 28, count 0 2006.285.07:38:00.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:38:00.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:38:00.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.07:38:00.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.07:38:00.39$vck44/va=8,3 2006.285.07:38:00.39#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.07:38:00.39#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.07:38:00.39#ibcon#ireg 11 cls_cnt 2 2006.285.07:38:00.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:38:00.43#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:38:00.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:38:00.43#ibcon#enter wrdev, iclass 30, count 2 2006.285.07:38:00.43#ibcon#first serial, iclass 30, count 2 2006.285.07:38:00.43#ibcon#enter sib2, iclass 30, count 2 2006.285.07:38:00.43#ibcon#flushed, iclass 30, count 2 2006.285.07:38:00.43#ibcon#about to write, iclass 30, count 2 2006.285.07:38:00.43#ibcon#wrote, iclass 30, count 2 2006.285.07:38:00.43#ibcon#about to read 3, iclass 30, count 2 2006.285.07:38:00.45#ibcon#read 3, iclass 30, count 2 2006.285.07:38:00.45#ibcon#about to read 4, iclass 30, count 2 2006.285.07:38:00.45#ibcon#read 4, iclass 30, count 2 2006.285.07:38:00.45#ibcon#about to read 5, iclass 30, count 2 2006.285.07:38:00.45#ibcon#read 5, iclass 30, count 2 2006.285.07:38:00.45#ibcon#about to read 6, iclass 30, count 2 2006.285.07:38:00.45#ibcon#read 6, iclass 30, count 2 2006.285.07:38:00.45#ibcon#end of sib2, iclass 30, count 2 2006.285.07:38:00.45#ibcon#*mode == 0, iclass 30, count 2 2006.285.07:38:00.45#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.07:38:00.45#ibcon#[25=AT08-03\r\n] 2006.285.07:38:00.45#ibcon#*before write, iclass 30, count 2 2006.285.07:38:00.45#ibcon#enter sib2, iclass 30, count 2 2006.285.07:38:00.45#ibcon#flushed, iclass 30, count 2 2006.285.07:38:00.45#ibcon#about to write, iclass 30, count 2 2006.285.07:38:00.45#ibcon#wrote, iclass 30, count 2 2006.285.07:38:00.45#ibcon#about to read 3, iclass 30, count 2 2006.285.07:38:00.48#ibcon#read 3, iclass 30, count 2 2006.285.07:38:00.48#ibcon#about to read 4, iclass 30, count 2 2006.285.07:38:00.48#ibcon#read 4, iclass 30, count 2 2006.285.07:38:00.48#ibcon#about to read 5, iclass 30, count 2 2006.285.07:38:00.48#ibcon#read 5, iclass 30, count 2 2006.285.07:38:00.48#ibcon#about to read 6, iclass 30, count 2 2006.285.07:38:00.48#ibcon#read 6, iclass 30, count 2 2006.285.07:38:00.48#ibcon#end of sib2, iclass 30, count 2 2006.285.07:38:00.48#ibcon#*after write, iclass 30, count 2 2006.285.07:38:00.48#ibcon#*before return 0, iclass 30, count 2 2006.285.07:38:00.48#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:38:00.48#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.07:38:00.48#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.07:38:00.48#ibcon#ireg 7 cls_cnt 0 2006.285.07:38:00.48#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:38:00.60#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:38:00.60#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:38:00.60#ibcon#enter wrdev, iclass 30, count 0 2006.285.07:38:00.60#ibcon#first serial, iclass 30, count 0 2006.285.07:38:00.60#ibcon#enter sib2, iclass 30, count 0 2006.285.07:38:00.60#ibcon#flushed, iclass 30, count 0 2006.285.07:38:00.60#ibcon#about to write, iclass 30, count 0 2006.285.07:38:00.60#ibcon#wrote, iclass 30, count 0 2006.285.07:38:00.60#ibcon#about to read 3, iclass 30, count 0 2006.285.07:38:00.62#ibcon#read 3, iclass 30, count 0 2006.285.07:38:00.62#ibcon#about to read 4, iclass 30, count 0 2006.285.07:38:00.62#ibcon#read 4, iclass 30, count 0 2006.285.07:38:00.62#ibcon#about to read 5, iclass 30, count 0 2006.285.07:38:00.62#ibcon#read 5, iclass 30, count 0 2006.285.07:38:00.62#ibcon#about to read 6, iclass 30, count 0 2006.285.07:38:00.62#ibcon#read 6, iclass 30, count 0 2006.285.07:38:00.62#ibcon#end of sib2, iclass 30, count 0 2006.285.07:38:00.62#ibcon#*mode == 0, iclass 30, count 0 2006.285.07:38:00.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.07:38:00.62#ibcon#[25=USB\r\n] 2006.285.07:38:00.62#ibcon#*before write, iclass 30, count 0 2006.285.07:38:00.62#ibcon#enter sib2, iclass 30, count 0 2006.285.07:38:00.62#ibcon#flushed, iclass 30, count 0 2006.285.07:38:00.62#ibcon#about to write, iclass 30, count 0 2006.285.07:38:00.62#ibcon#wrote, iclass 30, count 0 2006.285.07:38:00.62#ibcon#about to read 3, iclass 30, count 0 2006.285.07:38:00.65#ibcon#read 3, iclass 30, count 0 2006.285.07:38:00.65#ibcon#about to read 4, iclass 30, count 0 2006.285.07:38:00.65#ibcon#read 4, iclass 30, count 0 2006.285.07:38:00.65#ibcon#about to read 5, iclass 30, count 0 2006.285.07:38:00.65#ibcon#read 5, iclass 30, count 0 2006.285.07:38:00.65#ibcon#about to read 6, iclass 30, count 0 2006.285.07:38:00.65#ibcon#read 6, iclass 30, count 0 2006.285.07:38:00.65#ibcon#end of sib2, iclass 30, count 0 2006.285.07:38:00.65#ibcon#*after write, iclass 30, count 0 2006.285.07:38:00.65#ibcon#*before return 0, iclass 30, count 0 2006.285.07:38:00.65#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:38:00.65#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.07:38:00.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.07:38:00.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.07:38:00.66$vck44/vblo=1,629.99 2006.285.07:38:00.66#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.07:38:00.66#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.07:38:00.66#ibcon#ireg 17 cls_cnt 0 2006.285.07:38:00.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:38:00.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:38:00.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:38:00.66#ibcon#enter wrdev, iclass 32, count 0 2006.285.07:38:00.66#ibcon#first serial, iclass 32, count 0 2006.285.07:38:00.66#ibcon#enter sib2, iclass 32, count 0 2006.285.07:38:00.66#ibcon#flushed, iclass 32, count 0 2006.285.07:38:00.66#ibcon#about to write, iclass 32, count 0 2006.285.07:38:00.66#ibcon#wrote, iclass 32, count 0 2006.285.07:38:00.66#ibcon#about to read 3, iclass 32, count 0 2006.285.07:38:00.67#ibcon#read 3, iclass 32, count 0 2006.285.07:38:00.67#ibcon#about to read 4, iclass 32, count 0 2006.285.07:38:00.67#ibcon#read 4, iclass 32, count 0 2006.285.07:38:00.67#ibcon#about to read 5, iclass 32, count 0 2006.285.07:38:00.67#ibcon#read 5, iclass 32, count 0 2006.285.07:38:00.67#ibcon#about to read 6, iclass 32, count 0 2006.285.07:38:00.67#ibcon#read 6, iclass 32, count 0 2006.285.07:38:00.67#ibcon#end of sib2, iclass 32, count 0 2006.285.07:38:00.67#ibcon#*mode == 0, iclass 32, count 0 2006.285.07:38:00.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.07:38:00.67#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:38:00.67#ibcon#*before write, iclass 32, count 0 2006.285.07:38:00.67#ibcon#enter sib2, iclass 32, count 0 2006.285.07:38:00.67#ibcon#flushed, iclass 32, count 0 2006.285.07:38:00.67#ibcon#about to write, iclass 32, count 0 2006.285.07:38:00.67#ibcon#wrote, iclass 32, count 0 2006.285.07:38:00.67#ibcon#about to read 3, iclass 32, count 0 2006.285.07:38:00.71#ibcon#read 3, iclass 32, count 0 2006.285.07:38:00.71#ibcon#about to read 4, iclass 32, count 0 2006.285.07:38:00.71#ibcon#read 4, iclass 32, count 0 2006.285.07:38:00.71#ibcon#about to read 5, iclass 32, count 0 2006.285.07:38:00.71#ibcon#read 5, iclass 32, count 0 2006.285.07:38:00.71#ibcon#about to read 6, iclass 32, count 0 2006.285.07:38:00.71#ibcon#read 6, iclass 32, count 0 2006.285.07:38:00.71#ibcon#end of sib2, iclass 32, count 0 2006.285.07:38:00.71#ibcon#*after write, iclass 32, count 0 2006.285.07:38:00.71#ibcon#*before return 0, iclass 32, count 0 2006.285.07:38:00.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:38:00.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.07:38:00.71#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.07:38:00.71#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.07:38:00.72$vck44/vb=1,4 2006.285.07:38:00.72#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.07:38:00.72#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.07:38:00.72#ibcon#ireg 11 cls_cnt 2 2006.285.07:38:00.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:38:00.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:38:00.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:38:00.72#ibcon#enter wrdev, iclass 34, count 2 2006.285.07:38:00.72#ibcon#first serial, iclass 34, count 2 2006.285.07:38:00.72#ibcon#enter sib2, iclass 34, count 2 2006.285.07:38:00.72#ibcon#flushed, iclass 34, count 2 2006.285.07:38:00.72#ibcon#about to write, iclass 34, count 2 2006.285.07:38:00.72#ibcon#wrote, iclass 34, count 2 2006.285.07:38:00.72#ibcon#about to read 3, iclass 34, count 2 2006.285.07:38:00.73#ibcon#read 3, iclass 34, count 2 2006.285.07:38:00.73#ibcon#about to read 4, iclass 34, count 2 2006.285.07:38:00.73#ibcon#read 4, iclass 34, count 2 2006.285.07:38:00.73#ibcon#about to read 5, iclass 34, count 2 2006.285.07:38:00.73#ibcon#read 5, iclass 34, count 2 2006.285.07:38:00.73#ibcon#about to read 6, iclass 34, count 2 2006.285.07:38:00.73#ibcon#read 6, iclass 34, count 2 2006.285.07:38:00.73#ibcon#end of sib2, iclass 34, count 2 2006.285.07:38:00.73#ibcon#*mode == 0, iclass 34, count 2 2006.285.07:38:00.73#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.07:38:00.73#ibcon#[27=AT01-04\r\n] 2006.285.07:38:00.73#ibcon#*before write, iclass 34, count 2 2006.285.07:38:00.73#ibcon#enter sib2, iclass 34, count 2 2006.285.07:38:00.73#ibcon#flushed, iclass 34, count 2 2006.285.07:38:00.73#ibcon#about to write, iclass 34, count 2 2006.285.07:38:00.73#ibcon#wrote, iclass 34, count 2 2006.285.07:38:00.73#ibcon#about to read 3, iclass 34, count 2 2006.285.07:38:00.76#ibcon#read 3, iclass 34, count 2 2006.285.07:38:00.76#ibcon#about to read 4, iclass 34, count 2 2006.285.07:38:00.76#ibcon#read 4, iclass 34, count 2 2006.285.07:38:00.76#ibcon#about to read 5, iclass 34, count 2 2006.285.07:38:00.76#ibcon#read 5, iclass 34, count 2 2006.285.07:38:00.76#ibcon#about to read 6, iclass 34, count 2 2006.285.07:38:00.76#ibcon#read 6, iclass 34, count 2 2006.285.07:38:00.76#ibcon#end of sib2, iclass 34, count 2 2006.285.07:38:00.76#ibcon#*after write, iclass 34, count 2 2006.285.07:38:00.76#ibcon#*before return 0, iclass 34, count 2 2006.285.07:38:00.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:38:00.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.07:38:00.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.07:38:00.76#ibcon#ireg 7 cls_cnt 0 2006.285.07:38:00.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:38:00.88#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:38:00.88#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:38:00.88#ibcon#enter wrdev, iclass 34, count 0 2006.285.07:38:00.88#ibcon#first serial, iclass 34, count 0 2006.285.07:38:00.88#ibcon#enter sib2, iclass 34, count 0 2006.285.07:38:00.88#ibcon#flushed, iclass 34, count 0 2006.285.07:38:00.88#ibcon#about to write, iclass 34, count 0 2006.285.07:38:00.88#ibcon#wrote, iclass 34, count 0 2006.285.07:38:00.88#ibcon#about to read 3, iclass 34, count 0 2006.285.07:38:00.90#ibcon#read 3, iclass 34, count 0 2006.285.07:38:00.90#ibcon#about to read 4, iclass 34, count 0 2006.285.07:38:00.90#ibcon#read 4, iclass 34, count 0 2006.285.07:38:00.90#ibcon#about to read 5, iclass 34, count 0 2006.285.07:38:00.90#ibcon#read 5, iclass 34, count 0 2006.285.07:38:00.90#ibcon#about to read 6, iclass 34, count 0 2006.285.07:38:00.90#ibcon#read 6, iclass 34, count 0 2006.285.07:38:00.90#ibcon#end of sib2, iclass 34, count 0 2006.285.07:38:00.90#ibcon#*mode == 0, iclass 34, count 0 2006.285.07:38:00.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.07:38:00.90#ibcon#[27=USB\r\n] 2006.285.07:38:00.90#ibcon#*before write, iclass 34, count 0 2006.285.07:38:00.90#ibcon#enter sib2, iclass 34, count 0 2006.285.07:38:00.90#ibcon#flushed, iclass 34, count 0 2006.285.07:38:00.90#ibcon#about to write, iclass 34, count 0 2006.285.07:38:00.90#ibcon#wrote, iclass 34, count 0 2006.285.07:38:00.90#ibcon#about to read 3, iclass 34, count 0 2006.285.07:38:00.93#ibcon#read 3, iclass 34, count 0 2006.285.07:38:00.93#ibcon#about to read 4, iclass 34, count 0 2006.285.07:38:00.93#ibcon#read 4, iclass 34, count 0 2006.285.07:38:00.93#ibcon#about to read 5, iclass 34, count 0 2006.285.07:38:00.93#ibcon#read 5, iclass 34, count 0 2006.285.07:38:00.93#ibcon#about to read 6, iclass 34, count 0 2006.285.07:38:00.93#ibcon#read 6, iclass 34, count 0 2006.285.07:38:00.93#ibcon#end of sib2, iclass 34, count 0 2006.285.07:38:00.93#ibcon#*after write, iclass 34, count 0 2006.285.07:38:00.93#ibcon#*before return 0, iclass 34, count 0 2006.285.07:38:00.93#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:38:00.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.07:38:00.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.07:38:00.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.07:38:00.94$vck44/vblo=2,634.99 2006.285.07:38:00.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.07:38:00.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.07:38:00.94#ibcon#ireg 17 cls_cnt 0 2006.285.07:38:00.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:38:00.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:38:00.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:38:00.94#ibcon#enter wrdev, iclass 36, count 0 2006.285.07:38:00.94#ibcon#first serial, iclass 36, count 0 2006.285.07:38:00.94#ibcon#enter sib2, iclass 36, count 0 2006.285.07:38:00.94#ibcon#flushed, iclass 36, count 0 2006.285.07:38:00.94#ibcon#about to write, iclass 36, count 0 2006.285.07:38:00.94#ibcon#wrote, iclass 36, count 0 2006.285.07:38:00.94#ibcon#about to read 3, iclass 36, count 0 2006.285.07:38:00.95#ibcon#read 3, iclass 36, count 0 2006.285.07:38:00.95#ibcon#about to read 4, iclass 36, count 0 2006.285.07:38:00.95#ibcon#read 4, iclass 36, count 0 2006.285.07:38:00.95#ibcon#about to read 5, iclass 36, count 0 2006.285.07:38:00.95#ibcon#read 5, iclass 36, count 0 2006.285.07:38:00.95#ibcon#about to read 6, iclass 36, count 0 2006.285.07:38:00.95#ibcon#read 6, iclass 36, count 0 2006.285.07:38:00.95#ibcon#end of sib2, iclass 36, count 0 2006.285.07:38:00.95#ibcon#*mode == 0, iclass 36, count 0 2006.285.07:38:00.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.07:38:00.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:38:00.95#ibcon#*before write, iclass 36, count 0 2006.285.07:38:00.95#ibcon#enter sib2, iclass 36, count 0 2006.285.07:38:00.95#ibcon#flushed, iclass 36, count 0 2006.285.07:38:00.95#ibcon#about to write, iclass 36, count 0 2006.285.07:38:00.95#ibcon#wrote, iclass 36, count 0 2006.285.07:38:00.95#ibcon#about to read 3, iclass 36, count 0 2006.285.07:38:00.99#ibcon#read 3, iclass 36, count 0 2006.285.07:38:00.99#ibcon#about to read 4, iclass 36, count 0 2006.285.07:38:00.99#ibcon#read 4, iclass 36, count 0 2006.285.07:38:00.99#ibcon#about to read 5, iclass 36, count 0 2006.285.07:38:00.99#ibcon#read 5, iclass 36, count 0 2006.285.07:38:00.99#ibcon#about to read 6, iclass 36, count 0 2006.285.07:38:00.99#ibcon#read 6, iclass 36, count 0 2006.285.07:38:00.99#ibcon#end of sib2, iclass 36, count 0 2006.285.07:38:00.99#ibcon#*after write, iclass 36, count 0 2006.285.07:38:00.99#ibcon#*before return 0, iclass 36, count 0 2006.285.07:38:00.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:38:00.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.07:38:00.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.07:38:00.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.07:38:01.00$vck44/vb=2,5 2006.285.07:38:01.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.07:38:01.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.07:38:01.00#ibcon#ireg 11 cls_cnt 2 2006.285.07:38:01.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:38:01.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:38:01.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:38:01.04#ibcon#enter wrdev, iclass 38, count 2 2006.285.07:38:01.04#ibcon#first serial, iclass 38, count 2 2006.285.07:38:01.04#ibcon#enter sib2, iclass 38, count 2 2006.285.07:38:01.04#ibcon#flushed, iclass 38, count 2 2006.285.07:38:01.04#ibcon#about to write, iclass 38, count 2 2006.285.07:38:01.04#ibcon#wrote, iclass 38, count 2 2006.285.07:38:01.04#ibcon#about to read 3, iclass 38, count 2 2006.285.07:38:01.06#ibcon#read 3, iclass 38, count 2 2006.285.07:38:01.06#ibcon#about to read 4, iclass 38, count 2 2006.285.07:38:01.06#ibcon#read 4, iclass 38, count 2 2006.285.07:38:01.06#ibcon#about to read 5, iclass 38, count 2 2006.285.07:38:01.06#ibcon#read 5, iclass 38, count 2 2006.285.07:38:01.06#ibcon#about to read 6, iclass 38, count 2 2006.285.07:38:01.06#ibcon#read 6, iclass 38, count 2 2006.285.07:38:01.06#ibcon#end of sib2, iclass 38, count 2 2006.285.07:38:01.06#ibcon#*mode == 0, iclass 38, count 2 2006.285.07:38:01.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.07:38:01.06#ibcon#[27=AT02-05\r\n] 2006.285.07:38:01.06#ibcon#*before write, iclass 38, count 2 2006.285.07:38:01.06#ibcon#enter sib2, iclass 38, count 2 2006.285.07:38:01.06#ibcon#flushed, iclass 38, count 2 2006.285.07:38:01.06#ibcon#about to write, iclass 38, count 2 2006.285.07:38:01.06#ibcon#wrote, iclass 38, count 2 2006.285.07:38:01.06#ibcon#about to read 3, iclass 38, count 2 2006.285.07:38:01.09#ibcon#read 3, iclass 38, count 2 2006.285.07:38:01.09#ibcon#about to read 4, iclass 38, count 2 2006.285.07:38:01.09#ibcon#read 4, iclass 38, count 2 2006.285.07:38:01.09#ibcon#about to read 5, iclass 38, count 2 2006.285.07:38:01.09#ibcon#read 5, iclass 38, count 2 2006.285.07:38:01.09#ibcon#about to read 6, iclass 38, count 2 2006.285.07:38:01.09#ibcon#read 6, iclass 38, count 2 2006.285.07:38:01.09#ibcon#end of sib2, iclass 38, count 2 2006.285.07:38:01.09#ibcon#*after write, iclass 38, count 2 2006.285.07:38:01.09#ibcon#*before return 0, iclass 38, count 2 2006.285.07:38:01.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:38:01.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.07:38:01.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.07:38:01.09#ibcon#ireg 7 cls_cnt 0 2006.285.07:38:01.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:38:01.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:38:01.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:38:01.21#ibcon#enter wrdev, iclass 38, count 0 2006.285.07:38:01.21#ibcon#first serial, iclass 38, count 0 2006.285.07:38:01.21#ibcon#enter sib2, iclass 38, count 0 2006.285.07:38:01.21#ibcon#flushed, iclass 38, count 0 2006.285.07:38:01.21#ibcon#about to write, iclass 38, count 0 2006.285.07:38:01.21#ibcon#wrote, iclass 38, count 0 2006.285.07:38:01.21#ibcon#about to read 3, iclass 38, count 0 2006.285.07:38:01.23#ibcon#read 3, iclass 38, count 0 2006.285.07:38:01.23#ibcon#about to read 4, iclass 38, count 0 2006.285.07:38:01.23#ibcon#read 4, iclass 38, count 0 2006.285.07:38:01.23#ibcon#about to read 5, iclass 38, count 0 2006.285.07:38:01.23#ibcon#read 5, iclass 38, count 0 2006.285.07:38:01.23#ibcon#about to read 6, iclass 38, count 0 2006.285.07:38:01.23#ibcon#read 6, iclass 38, count 0 2006.285.07:38:01.23#ibcon#end of sib2, iclass 38, count 0 2006.285.07:38:01.23#ibcon#*mode == 0, iclass 38, count 0 2006.285.07:38:01.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.07:38:01.23#ibcon#[27=USB\r\n] 2006.285.07:38:01.23#ibcon#*before write, iclass 38, count 0 2006.285.07:38:01.23#ibcon#enter sib2, iclass 38, count 0 2006.285.07:38:01.23#ibcon#flushed, iclass 38, count 0 2006.285.07:38:01.23#ibcon#about to write, iclass 38, count 0 2006.285.07:38:01.23#ibcon#wrote, iclass 38, count 0 2006.285.07:38:01.23#ibcon#about to read 3, iclass 38, count 0 2006.285.07:38:01.26#ibcon#read 3, iclass 38, count 0 2006.285.07:38:01.26#ibcon#about to read 4, iclass 38, count 0 2006.285.07:38:01.26#ibcon#read 4, iclass 38, count 0 2006.285.07:38:01.26#ibcon#about to read 5, iclass 38, count 0 2006.285.07:38:01.26#ibcon#read 5, iclass 38, count 0 2006.285.07:38:01.26#ibcon#about to read 6, iclass 38, count 0 2006.285.07:38:01.26#ibcon#read 6, iclass 38, count 0 2006.285.07:38:01.26#ibcon#end of sib2, iclass 38, count 0 2006.285.07:38:01.26#ibcon#*after write, iclass 38, count 0 2006.285.07:38:01.26#ibcon#*before return 0, iclass 38, count 0 2006.285.07:38:01.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:38:01.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.07:38:01.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.07:38:01.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.07:38:01.27$vck44/vblo=3,649.99 2006.285.07:38:01.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.07:38:01.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.07:38:01.27#ibcon#ireg 17 cls_cnt 0 2006.285.07:38:01.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:38:01.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:38:01.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:38:01.27#ibcon#enter wrdev, iclass 40, count 0 2006.285.07:38:01.27#ibcon#first serial, iclass 40, count 0 2006.285.07:38:01.27#ibcon#enter sib2, iclass 40, count 0 2006.285.07:38:01.27#ibcon#flushed, iclass 40, count 0 2006.285.07:38:01.27#ibcon#about to write, iclass 40, count 0 2006.285.07:38:01.27#ibcon#wrote, iclass 40, count 0 2006.285.07:38:01.27#ibcon#about to read 3, iclass 40, count 0 2006.285.07:38:01.28#ibcon#read 3, iclass 40, count 0 2006.285.07:38:01.28#ibcon#about to read 4, iclass 40, count 0 2006.285.07:38:01.28#ibcon#read 4, iclass 40, count 0 2006.285.07:38:01.28#ibcon#about to read 5, iclass 40, count 0 2006.285.07:38:01.28#ibcon#read 5, iclass 40, count 0 2006.285.07:38:01.28#ibcon#about to read 6, iclass 40, count 0 2006.285.07:38:01.28#ibcon#read 6, iclass 40, count 0 2006.285.07:38:01.28#ibcon#end of sib2, iclass 40, count 0 2006.285.07:38:01.28#ibcon#*mode == 0, iclass 40, count 0 2006.285.07:38:01.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.07:38:01.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:38:01.28#ibcon#*before write, iclass 40, count 0 2006.285.07:38:01.28#ibcon#enter sib2, iclass 40, count 0 2006.285.07:38:01.28#ibcon#flushed, iclass 40, count 0 2006.285.07:38:01.28#ibcon#about to write, iclass 40, count 0 2006.285.07:38:01.28#ibcon#wrote, iclass 40, count 0 2006.285.07:38:01.28#ibcon#about to read 3, iclass 40, count 0 2006.285.07:38:01.32#ibcon#read 3, iclass 40, count 0 2006.285.07:38:01.32#ibcon#about to read 4, iclass 40, count 0 2006.285.07:38:01.32#ibcon#read 4, iclass 40, count 0 2006.285.07:38:01.32#ibcon#about to read 5, iclass 40, count 0 2006.285.07:38:01.32#ibcon#read 5, iclass 40, count 0 2006.285.07:38:01.32#ibcon#about to read 6, iclass 40, count 0 2006.285.07:38:01.32#ibcon#read 6, iclass 40, count 0 2006.285.07:38:01.32#ibcon#end of sib2, iclass 40, count 0 2006.285.07:38:01.32#ibcon#*after write, iclass 40, count 0 2006.285.07:38:01.32#ibcon#*before return 0, iclass 40, count 0 2006.285.07:38:01.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:38:01.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.07:38:01.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.07:38:01.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.07:38:01.33$vck44/vb=3,4 2006.285.07:38:01.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.07:38:01.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.07:38:01.33#ibcon#ireg 11 cls_cnt 2 2006.285.07:38:01.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:38:01.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:38:01.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:38:01.37#ibcon#enter wrdev, iclass 4, count 2 2006.285.07:38:01.37#ibcon#first serial, iclass 4, count 2 2006.285.07:38:01.37#ibcon#enter sib2, iclass 4, count 2 2006.285.07:38:01.37#ibcon#flushed, iclass 4, count 2 2006.285.07:38:01.37#ibcon#about to write, iclass 4, count 2 2006.285.07:38:01.37#ibcon#wrote, iclass 4, count 2 2006.285.07:38:01.37#ibcon#about to read 3, iclass 4, count 2 2006.285.07:38:01.39#ibcon#read 3, iclass 4, count 2 2006.285.07:38:01.39#ibcon#about to read 4, iclass 4, count 2 2006.285.07:38:01.39#ibcon#read 4, iclass 4, count 2 2006.285.07:38:01.39#ibcon#about to read 5, iclass 4, count 2 2006.285.07:38:01.39#ibcon#read 5, iclass 4, count 2 2006.285.07:38:01.39#ibcon#about to read 6, iclass 4, count 2 2006.285.07:38:01.39#ibcon#read 6, iclass 4, count 2 2006.285.07:38:01.39#ibcon#end of sib2, iclass 4, count 2 2006.285.07:38:01.39#ibcon#*mode == 0, iclass 4, count 2 2006.285.07:38:01.39#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.07:38:01.39#ibcon#[27=AT03-04\r\n] 2006.285.07:38:01.39#ibcon#*before write, iclass 4, count 2 2006.285.07:38:01.39#ibcon#enter sib2, iclass 4, count 2 2006.285.07:38:01.39#ibcon#flushed, iclass 4, count 2 2006.285.07:38:01.39#ibcon#about to write, iclass 4, count 2 2006.285.07:38:01.39#ibcon#wrote, iclass 4, count 2 2006.285.07:38:01.39#ibcon#about to read 3, iclass 4, count 2 2006.285.07:38:01.42#ibcon#read 3, iclass 4, count 2 2006.285.07:38:01.42#ibcon#about to read 4, iclass 4, count 2 2006.285.07:38:01.42#ibcon#read 4, iclass 4, count 2 2006.285.07:38:01.42#ibcon#about to read 5, iclass 4, count 2 2006.285.07:38:01.42#ibcon#read 5, iclass 4, count 2 2006.285.07:38:01.42#ibcon#about to read 6, iclass 4, count 2 2006.285.07:38:01.42#ibcon#read 6, iclass 4, count 2 2006.285.07:38:01.42#ibcon#end of sib2, iclass 4, count 2 2006.285.07:38:01.42#ibcon#*after write, iclass 4, count 2 2006.285.07:38:01.42#ibcon#*before return 0, iclass 4, count 2 2006.285.07:38:01.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:38:01.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.07:38:01.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.07:38:01.42#ibcon#ireg 7 cls_cnt 0 2006.285.07:38:01.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:38:01.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:38:01.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:38:01.54#ibcon#enter wrdev, iclass 4, count 0 2006.285.07:38:01.54#ibcon#first serial, iclass 4, count 0 2006.285.07:38:01.54#ibcon#enter sib2, iclass 4, count 0 2006.285.07:38:01.54#ibcon#flushed, iclass 4, count 0 2006.285.07:38:01.54#ibcon#about to write, iclass 4, count 0 2006.285.07:38:01.54#ibcon#wrote, iclass 4, count 0 2006.285.07:38:01.54#ibcon#about to read 3, iclass 4, count 0 2006.285.07:38:01.56#ibcon#read 3, iclass 4, count 0 2006.285.07:38:01.56#ibcon#about to read 4, iclass 4, count 0 2006.285.07:38:01.56#ibcon#read 4, iclass 4, count 0 2006.285.07:38:01.56#ibcon#about to read 5, iclass 4, count 0 2006.285.07:38:01.56#ibcon#read 5, iclass 4, count 0 2006.285.07:38:01.56#ibcon#about to read 6, iclass 4, count 0 2006.285.07:38:01.56#ibcon#read 6, iclass 4, count 0 2006.285.07:38:01.56#ibcon#end of sib2, iclass 4, count 0 2006.285.07:38:01.56#ibcon#*mode == 0, iclass 4, count 0 2006.285.07:38:01.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.07:38:01.56#ibcon#[27=USB\r\n] 2006.285.07:38:01.56#ibcon#*before write, iclass 4, count 0 2006.285.07:38:01.56#ibcon#enter sib2, iclass 4, count 0 2006.285.07:38:01.56#ibcon#flushed, iclass 4, count 0 2006.285.07:38:01.56#ibcon#about to write, iclass 4, count 0 2006.285.07:38:01.56#ibcon#wrote, iclass 4, count 0 2006.285.07:38:01.56#ibcon#about to read 3, iclass 4, count 0 2006.285.07:38:01.59#ibcon#read 3, iclass 4, count 0 2006.285.07:38:01.59#ibcon#about to read 4, iclass 4, count 0 2006.285.07:38:01.59#ibcon#read 4, iclass 4, count 0 2006.285.07:38:01.59#ibcon#about to read 5, iclass 4, count 0 2006.285.07:38:01.59#ibcon#read 5, iclass 4, count 0 2006.285.07:38:01.59#ibcon#about to read 6, iclass 4, count 0 2006.285.07:38:01.59#ibcon#read 6, iclass 4, count 0 2006.285.07:38:01.59#ibcon#end of sib2, iclass 4, count 0 2006.285.07:38:01.59#ibcon#*after write, iclass 4, count 0 2006.285.07:38:01.59#ibcon#*before return 0, iclass 4, count 0 2006.285.07:38:01.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:38:01.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.07:38:01.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.07:38:01.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.07:38:01.60$vck44/vblo=4,679.99 2006.285.07:38:01.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.07:38:01.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.07:38:01.60#ibcon#ireg 17 cls_cnt 0 2006.285.07:38:01.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:38:01.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:38:01.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:38:01.60#ibcon#enter wrdev, iclass 6, count 0 2006.285.07:38:01.60#ibcon#first serial, iclass 6, count 0 2006.285.07:38:01.60#ibcon#enter sib2, iclass 6, count 0 2006.285.07:38:01.60#ibcon#flushed, iclass 6, count 0 2006.285.07:38:01.60#ibcon#about to write, iclass 6, count 0 2006.285.07:38:01.60#ibcon#wrote, iclass 6, count 0 2006.285.07:38:01.60#ibcon#about to read 3, iclass 6, count 0 2006.285.07:38:01.61#ibcon#read 3, iclass 6, count 0 2006.285.07:38:01.61#ibcon#about to read 4, iclass 6, count 0 2006.285.07:38:01.61#ibcon#read 4, iclass 6, count 0 2006.285.07:38:01.61#ibcon#about to read 5, iclass 6, count 0 2006.285.07:38:01.61#ibcon#read 5, iclass 6, count 0 2006.285.07:38:01.61#ibcon#about to read 6, iclass 6, count 0 2006.285.07:38:01.61#ibcon#read 6, iclass 6, count 0 2006.285.07:38:01.61#ibcon#end of sib2, iclass 6, count 0 2006.285.07:38:01.61#ibcon#*mode == 0, iclass 6, count 0 2006.285.07:38:01.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.07:38:01.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:38:01.61#ibcon#*before write, iclass 6, count 0 2006.285.07:38:01.61#ibcon#enter sib2, iclass 6, count 0 2006.285.07:38:01.61#ibcon#flushed, iclass 6, count 0 2006.285.07:38:01.61#ibcon#about to write, iclass 6, count 0 2006.285.07:38:01.61#ibcon#wrote, iclass 6, count 0 2006.285.07:38:01.61#ibcon#about to read 3, iclass 6, count 0 2006.285.07:38:01.65#ibcon#read 3, iclass 6, count 0 2006.285.07:38:01.65#ibcon#about to read 4, iclass 6, count 0 2006.285.07:38:01.65#ibcon#read 4, iclass 6, count 0 2006.285.07:38:01.65#ibcon#about to read 5, iclass 6, count 0 2006.285.07:38:01.65#ibcon#read 5, iclass 6, count 0 2006.285.07:38:01.65#ibcon#about to read 6, iclass 6, count 0 2006.285.07:38:01.65#ibcon#read 6, iclass 6, count 0 2006.285.07:38:01.65#ibcon#end of sib2, iclass 6, count 0 2006.285.07:38:01.65#ibcon#*after write, iclass 6, count 0 2006.285.07:38:01.65#ibcon#*before return 0, iclass 6, count 0 2006.285.07:38:01.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:38:01.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.07:38:01.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.07:38:01.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.07:38:01.66$vck44/vb=4,5 2006.285.07:38:01.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.07:38:01.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.07:38:01.66#ibcon#ireg 11 cls_cnt 2 2006.285.07:38:01.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:38:01.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:38:01.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:38:01.70#ibcon#enter wrdev, iclass 10, count 2 2006.285.07:38:01.70#ibcon#first serial, iclass 10, count 2 2006.285.07:38:01.70#ibcon#enter sib2, iclass 10, count 2 2006.285.07:38:01.70#ibcon#flushed, iclass 10, count 2 2006.285.07:38:01.70#ibcon#about to write, iclass 10, count 2 2006.285.07:38:01.70#ibcon#wrote, iclass 10, count 2 2006.285.07:38:01.70#ibcon#about to read 3, iclass 10, count 2 2006.285.07:38:01.72#ibcon#read 3, iclass 10, count 2 2006.285.07:38:01.72#ibcon#about to read 4, iclass 10, count 2 2006.285.07:38:01.72#ibcon#read 4, iclass 10, count 2 2006.285.07:38:01.72#ibcon#about to read 5, iclass 10, count 2 2006.285.07:38:01.72#ibcon#read 5, iclass 10, count 2 2006.285.07:38:01.72#ibcon#about to read 6, iclass 10, count 2 2006.285.07:38:01.72#ibcon#read 6, iclass 10, count 2 2006.285.07:38:01.72#ibcon#end of sib2, iclass 10, count 2 2006.285.07:38:01.72#ibcon#*mode == 0, iclass 10, count 2 2006.285.07:38:01.72#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.07:38:01.72#ibcon#[27=AT04-05\r\n] 2006.285.07:38:01.72#ibcon#*before write, iclass 10, count 2 2006.285.07:38:01.72#ibcon#enter sib2, iclass 10, count 2 2006.285.07:38:01.72#ibcon#flushed, iclass 10, count 2 2006.285.07:38:01.72#ibcon#about to write, iclass 10, count 2 2006.285.07:38:01.72#ibcon#wrote, iclass 10, count 2 2006.285.07:38:01.72#ibcon#about to read 3, iclass 10, count 2 2006.285.07:38:01.75#ibcon#read 3, iclass 10, count 2 2006.285.07:38:01.75#ibcon#about to read 4, iclass 10, count 2 2006.285.07:38:01.75#ibcon#read 4, iclass 10, count 2 2006.285.07:38:01.75#ibcon#about to read 5, iclass 10, count 2 2006.285.07:38:01.75#ibcon#read 5, iclass 10, count 2 2006.285.07:38:01.75#ibcon#about to read 6, iclass 10, count 2 2006.285.07:38:01.75#ibcon#read 6, iclass 10, count 2 2006.285.07:38:01.75#ibcon#end of sib2, iclass 10, count 2 2006.285.07:38:01.75#ibcon#*after write, iclass 10, count 2 2006.285.07:38:01.75#ibcon#*before return 0, iclass 10, count 2 2006.285.07:38:01.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:38:01.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.07:38:01.75#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.07:38:01.75#ibcon#ireg 7 cls_cnt 0 2006.285.07:38:01.75#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:38:01.87#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:38:01.87#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:38:01.87#ibcon#enter wrdev, iclass 10, count 0 2006.285.07:38:01.87#ibcon#first serial, iclass 10, count 0 2006.285.07:38:01.87#ibcon#enter sib2, iclass 10, count 0 2006.285.07:38:01.87#ibcon#flushed, iclass 10, count 0 2006.285.07:38:01.87#ibcon#about to write, iclass 10, count 0 2006.285.07:38:01.87#ibcon#wrote, iclass 10, count 0 2006.285.07:38:01.87#ibcon#about to read 3, iclass 10, count 0 2006.285.07:38:01.90#ibcon#read 3, iclass 10, count 0 2006.285.07:38:01.90#ibcon#about to read 4, iclass 10, count 0 2006.285.07:38:01.90#ibcon#read 4, iclass 10, count 0 2006.285.07:38:01.90#ibcon#about to read 5, iclass 10, count 0 2006.285.07:38:01.90#ibcon#read 5, iclass 10, count 0 2006.285.07:38:01.90#ibcon#about to read 6, iclass 10, count 0 2006.285.07:38:01.90#ibcon#read 6, iclass 10, count 0 2006.285.07:38:01.90#ibcon#end of sib2, iclass 10, count 0 2006.285.07:38:01.90#ibcon#*mode == 0, iclass 10, count 0 2006.285.07:38:01.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.07:38:01.90#ibcon#[27=USB\r\n] 2006.285.07:38:01.90#ibcon#*before write, iclass 10, count 0 2006.285.07:38:01.90#ibcon#enter sib2, iclass 10, count 0 2006.285.07:38:01.90#ibcon#flushed, iclass 10, count 0 2006.285.07:38:01.90#ibcon#about to write, iclass 10, count 0 2006.285.07:38:01.90#ibcon#wrote, iclass 10, count 0 2006.285.07:38:01.90#ibcon#about to read 3, iclass 10, count 0 2006.285.07:38:01.93#ibcon#read 3, iclass 10, count 0 2006.285.07:38:01.93#ibcon#about to read 4, iclass 10, count 0 2006.285.07:38:01.93#ibcon#read 4, iclass 10, count 0 2006.285.07:38:01.93#ibcon#about to read 5, iclass 10, count 0 2006.285.07:38:01.93#ibcon#read 5, iclass 10, count 0 2006.285.07:38:01.93#ibcon#about to read 6, iclass 10, count 0 2006.285.07:38:01.93#ibcon#read 6, iclass 10, count 0 2006.285.07:38:01.93#ibcon#end of sib2, iclass 10, count 0 2006.285.07:38:01.93#ibcon#*after write, iclass 10, count 0 2006.285.07:38:01.93#ibcon#*before return 0, iclass 10, count 0 2006.285.07:38:01.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:38:01.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.07:38:01.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.07:38:01.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.07:38:01.94$vck44/vblo=5,709.99 2006.285.07:38:01.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.07:38:01.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.07:38:01.94#ibcon#ireg 17 cls_cnt 0 2006.285.07:38:01.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:38:01.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:38:01.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:38:01.94#ibcon#enter wrdev, iclass 12, count 0 2006.285.07:38:01.94#ibcon#first serial, iclass 12, count 0 2006.285.07:38:01.94#ibcon#enter sib2, iclass 12, count 0 2006.285.07:38:01.94#ibcon#flushed, iclass 12, count 0 2006.285.07:38:01.94#ibcon#about to write, iclass 12, count 0 2006.285.07:38:01.94#ibcon#wrote, iclass 12, count 0 2006.285.07:38:01.94#ibcon#about to read 3, iclass 12, count 0 2006.285.07:38:01.95#ibcon#read 3, iclass 12, count 0 2006.285.07:38:01.95#ibcon#about to read 4, iclass 12, count 0 2006.285.07:38:01.95#ibcon#read 4, iclass 12, count 0 2006.285.07:38:01.95#ibcon#about to read 5, iclass 12, count 0 2006.285.07:38:01.95#ibcon#read 5, iclass 12, count 0 2006.285.07:38:01.95#ibcon#about to read 6, iclass 12, count 0 2006.285.07:38:01.95#ibcon#read 6, iclass 12, count 0 2006.285.07:38:01.95#ibcon#end of sib2, iclass 12, count 0 2006.285.07:38:01.95#ibcon#*mode == 0, iclass 12, count 0 2006.285.07:38:01.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.07:38:01.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:38:01.95#ibcon#*before write, iclass 12, count 0 2006.285.07:38:01.95#ibcon#enter sib2, iclass 12, count 0 2006.285.07:38:01.95#ibcon#flushed, iclass 12, count 0 2006.285.07:38:01.95#ibcon#about to write, iclass 12, count 0 2006.285.07:38:01.95#ibcon#wrote, iclass 12, count 0 2006.285.07:38:01.95#ibcon#about to read 3, iclass 12, count 0 2006.285.07:38:01.99#ibcon#read 3, iclass 12, count 0 2006.285.07:38:01.99#ibcon#about to read 4, iclass 12, count 0 2006.285.07:38:01.99#ibcon#read 4, iclass 12, count 0 2006.285.07:38:01.99#ibcon#about to read 5, iclass 12, count 0 2006.285.07:38:01.99#ibcon#read 5, iclass 12, count 0 2006.285.07:38:01.99#ibcon#about to read 6, iclass 12, count 0 2006.285.07:38:01.99#ibcon#read 6, iclass 12, count 0 2006.285.07:38:01.99#ibcon#end of sib2, iclass 12, count 0 2006.285.07:38:01.99#ibcon#*after write, iclass 12, count 0 2006.285.07:38:01.99#ibcon#*before return 0, iclass 12, count 0 2006.285.07:38:01.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:38:01.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:38:01.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.07:38:01.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.07:38:02.00$vck44/vb=5,4 2006.285.07:38:02.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.07:38:02.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.07:38:02.00#ibcon#ireg 11 cls_cnt 2 2006.285.07:38:02.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:38:02.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:38:02.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:38:02.04#ibcon#enter wrdev, iclass 14, count 2 2006.285.07:38:02.04#ibcon#first serial, iclass 14, count 2 2006.285.07:38:02.04#ibcon#enter sib2, iclass 14, count 2 2006.285.07:38:02.04#ibcon#flushed, iclass 14, count 2 2006.285.07:38:02.04#ibcon#about to write, iclass 14, count 2 2006.285.07:38:02.04#ibcon#wrote, iclass 14, count 2 2006.285.07:38:02.04#ibcon#about to read 3, iclass 14, count 2 2006.285.07:38:02.06#ibcon#read 3, iclass 14, count 2 2006.285.07:38:02.06#ibcon#about to read 4, iclass 14, count 2 2006.285.07:38:02.06#ibcon#read 4, iclass 14, count 2 2006.285.07:38:02.06#ibcon#about to read 5, iclass 14, count 2 2006.285.07:38:02.06#ibcon#read 5, iclass 14, count 2 2006.285.07:38:02.06#ibcon#about to read 6, iclass 14, count 2 2006.285.07:38:02.06#ibcon#read 6, iclass 14, count 2 2006.285.07:38:02.06#ibcon#end of sib2, iclass 14, count 2 2006.285.07:38:02.06#ibcon#*mode == 0, iclass 14, count 2 2006.285.07:38:02.06#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.07:38:02.06#ibcon#[27=AT05-04\r\n] 2006.285.07:38:02.06#ibcon#*before write, iclass 14, count 2 2006.285.07:38:02.06#ibcon#enter sib2, iclass 14, count 2 2006.285.07:38:02.06#ibcon#flushed, iclass 14, count 2 2006.285.07:38:02.06#ibcon#about to write, iclass 14, count 2 2006.285.07:38:02.06#ibcon#wrote, iclass 14, count 2 2006.285.07:38:02.06#ibcon#about to read 3, iclass 14, count 2 2006.285.07:38:02.09#ibcon#read 3, iclass 14, count 2 2006.285.07:38:02.09#ibcon#about to read 4, iclass 14, count 2 2006.285.07:38:02.09#ibcon#read 4, iclass 14, count 2 2006.285.07:38:02.09#ibcon#about to read 5, iclass 14, count 2 2006.285.07:38:02.09#ibcon#read 5, iclass 14, count 2 2006.285.07:38:02.09#ibcon#about to read 6, iclass 14, count 2 2006.285.07:38:02.09#ibcon#read 6, iclass 14, count 2 2006.285.07:38:02.09#ibcon#end of sib2, iclass 14, count 2 2006.285.07:38:02.09#ibcon#*after write, iclass 14, count 2 2006.285.07:38:02.09#ibcon#*before return 0, iclass 14, count 2 2006.285.07:38:02.09#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:38:02.09#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.07:38:02.09#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.07:38:02.09#ibcon#ireg 7 cls_cnt 0 2006.285.07:38:02.09#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:38:02.21#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:38:02.21#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:38:02.21#ibcon#enter wrdev, iclass 14, count 0 2006.285.07:38:02.21#ibcon#first serial, iclass 14, count 0 2006.285.07:38:02.21#ibcon#enter sib2, iclass 14, count 0 2006.285.07:38:02.21#ibcon#flushed, iclass 14, count 0 2006.285.07:38:02.21#ibcon#about to write, iclass 14, count 0 2006.285.07:38:02.21#ibcon#wrote, iclass 14, count 0 2006.285.07:38:02.21#ibcon#about to read 3, iclass 14, count 0 2006.285.07:38:02.23#ibcon#read 3, iclass 14, count 0 2006.285.07:38:02.23#ibcon#about to read 4, iclass 14, count 0 2006.285.07:38:02.23#ibcon#read 4, iclass 14, count 0 2006.285.07:38:02.23#ibcon#about to read 5, iclass 14, count 0 2006.285.07:38:02.23#ibcon#read 5, iclass 14, count 0 2006.285.07:38:02.23#ibcon#about to read 6, iclass 14, count 0 2006.285.07:38:02.23#ibcon#read 6, iclass 14, count 0 2006.285.07:38:02.23#ibcon#end of sib2, iclass 14, count 0 2006.285.07:38:02.23#ibcon#*mode == 0, iclass 14, count 0 2006.285.07:38:02.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.07:38:02.23#ibcon#[27=USB\r\n] 2006.285.07:38:02.23#ibcon#*before write, iclass 14, count 0 2006.285.07:38:02.23#ibcon#enter sib2, iclass 14, count 0 2006.285.07:38:02.23#ibcon#flushed, iclass 14, count 0 2006.285.07:38:02.23#ibcon#about to write, iclass 14, count 0 2006.285.07:38:02.23#ibcon#wrote, iclass 14, count 0 2006.285.07:38:02.23#ibcon#about to read 3, iclass 14, count 0 2006.285.07:38:02.26#ibcon#read 3, iclass 14, count 0 2006.285.07:38:02.26#ibcon#about to read 4, iclass 14, count 0 2006.285.07:38:02.26#ibcon#read 4, iclass 14, count 0 2006.285.07:38:02.26#ibcon#about to read 5, iclass 14, count 0 2006.285.07:38:02.26#ibcon#read 5, iclass 14, count 0 2006.285.07:38:02.26#ibcon#about to read 6, iclass 14, count 0 2006.285.07:38:02.26#ibcon#read 6, iclass 14, count 0 2006.285.07:38:02.26#ibcon#end of sib2, iclass 14, count 0 2006.285.07:38:02.26#ibcon#*after write, iclass 14, count 0 2006.285.07:38:02.26#ibcon#*before return 0, iclass 14, count 0 2006.285.07:38:02.26#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:38:02.26#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.07:38:02.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.07:38:02.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.07:38:02.27$vck44/vblo=6,719.99 2006.285.07:38:02.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.07:38:02.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.07:38:02.27#ibcon#ireg 17 cls_cnt 0 2006.285.07:38:02.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:38:02.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:38:02.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:38:02.27#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:38:02.27#ibcon#first serial, iclass 16, count 0 2006.285.07:38:02.27#ibcon#enter sib2, iclass 16, count 0 2006.285.07:38:02.27#ibcon#flushed, iclass 16, count 0 2006.285.07:38:02.27#ibcon#about to write, iclass 16, count 0 2006.285.07:38:02.27#ibcon#wrote, iclass 16, count 0 2006.285.07:38:02.27#ibcon#about to read 3, iclass 16, count 0 2006.285.07:38:02.28#ibcon#read 3, iclass 16, count 0 2006.285.07:38:02.28#ibcon#about to read 4, iclass 16, count 0 2006.285.07:38:02.28#ibcon#read 4, iclass 16, count 0 2006.285.07:38:02.28#ibcon#about to read 5, iclass 16, count 0 2006.285.07:38:02.28#ibcon#read 5, iclass 16, count 0 2006.285.07:38:02.28#ibcon#about to read 6, iclass 16, count 0 2006.285.07:38:02.28#ibcon#read 6, iclass 16, count 0 2006.285.07:38:02.28#ibcon#end of sib2, iclass 16, count 0 2006.285.07:38:02.28#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:38:02.28#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:38:02.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:38:02.28#ibcon#*before write, iclass 16, count 0 2006.285.07:38:02.28#ibcon#enter sib2, iclass 16, count 0 2006.285.07:38:02.28#ibcon#flushed, iclass 16, count 0 2006.285.07:38:02.28#ibcon#about to write, iclass 16, count 0 2006.285.07:38:02.28#ibcon#wrote, iclass 16, count 0 2006.285.07:38:02.28#ibcon#about to read 3, iclass 16, count 0 2006.285.07:38:02.32#ibcon#read 3, iclass 16, count 0 2006.285.07:38:02.32#ibcon#about to read 4, iclass 16, count 0 2006.285.07:38:02.32#ibcon#read 4, iclass 16, count 0 2006.285.07:38:02.32#ibcon#about to read 5, iclass 16, count 0 2006.285.07:38:02.32#ibcon#read 5, iclass 16, count 0 2006.285.07:38:02.32#ibcon#about to read 6, iclass 16, count 0 2006.285.07:38:02.32#ibcon#read 6, iclass 16, count 0 2006.285.07:38:02.32#ibcon#end of sib2, iclass 16, count 0 2006.285.07:38:02.32#ibcon#*after write, iclass 16, count 0 2006.285.07:38:02.32#ibcon#*before return 0, iclass 16, count 0 2006.285.07:38:02.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:38:02.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.07:38:02.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:38:02.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:38:02.33$vck44/vb=6,3 2006.285.07:38:02.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.07:38:02.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.07:38:02.33#ibcon#ireg 11 cls_cnt 2 2006.285.07:38:02.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:38:02.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:38:02.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:38:02.37#ibcon#enter wrdev, iclass 18, count 2 2006.285.07:38:02.37#ibcon#first serial, iclass 18, count 2 2006.285.07:38:02.37#ibcon#enter sib2, iclass 18, count 2 2006.285.07:38:02.37#ibcon#flushed, iclass 18, count 2 2006.285.07:38:02.37#ibcon#about to write, iclass 18, count 2 2006.285.07:38:02.37#ibcon#wrote, iclass 18, count 2 2006.285.07:38:02.37#ibcon#about to read 3, iclass 18, count 2 2006.285.07:38:02.39#ibcon#read 3, iclass 18, count 2 2006.285.07:38:02.39#ibcon#about to read 4, iclass 18, count 2 2006.285.07:38:02.39#ibcon#read 4, iclass 18, count 2 2006.285.07:38:02.39#ibcon#about to read 5, iclass 18, count 2 2006.285.07:38:02.39#ibcon#read 5, iclass 18, count 2 2006.285.07:38:02.39#ibcon#about to read 6, iclass 18, count 2 2006.285.07:38:02.39#ibcon#read 6, iclass 18, count 2 2006.285.07:38:02.39#ibcon#end of sib2, iclass 18, count 2 2006.285.07:38:02.39#ibcon#*mode == 0, iclass 18, count 2 2006.285.07:38:02.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.07:38:02.39#ibcon#[27=AT06-03\r\n] 2006.285.07:38:02.39#ibcon#*before write, iclass 18, count 2 2006.285.07:38:02.39#ibcon#enter sib2, iclass 18, count 2 2006.285.07:38:02.39#ibcon#flushed, iclass 18, count 2 2006.285.07:38:02.39#ibcon#about to write, iclass 18, count 2 2006.285.07:38:02.39#ibcon#wrote, iclass 18, count 2 2006.285.07:38:02.39#ibcon#about to read 3, iclass 18, count 2 2006.285.07:38:02.42#ibcon#read 3, iclass 18, count 2 2006.285.07:38:02.42#ibcon#about to read 4, iclass 18, count 2 2006.285.07:38:02.42#ibcon#read 4, iclass 18, count 2 2006.285.07:38:02.42#ibcon#about to read 5, iclass 18, count 2 2006.285.07:38:02.42#ibcon#read 5, iclass 18, count 2 2006.285.07:38:02.42#ibcon#about to read 6, iclass 18, count 2 2006.285.07:38:02.42#ibcon#read 6, iclass 18, count 2 2006.285.07:38:02.42#ibcon#end of sib2, iclass 18, count 2 2006.285.07:38:02.42#ibcon#*after write, iclass 18, count 2 2006.285.07:38:02.42#ibcon#*before return 0, iclass 18, count 2 2006.285.07:38:02.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:38:02.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.07:38:02.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.07:38:02.42#ibcon#ireg 7 cls_cnt 0 2006.285.07:38:02.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:38:02.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:38:02.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:38:02.54#ibcon#enter wrdev, iclass 18, count 0 2006.285.07:38:02.54#ibcon#first serial, iclass 18, count 0 2006.285.07:38:02.54#ibcon#enter sib2, iclass 18, count 0 2006.285.07:38:02.54#ibcon#flushed, iclass 18, count 0 2006.285.07:38:02.54#ibcon#about to write, iclass 18, count 0 2006.285.07:38:02.54#ibcon#wrote, iclass 18, count 0 2006.285.07:38:02.54#ibcon#about to read 3, iclass 18, count 0 2006.285.07:38:02.56#ibcon#read 3, iclass 18, count 0 2006.285.07:38:02.56#ibcon#about to read 4, iclass 18, count 0 2006.285.07:38:02.56#ibcon#read 4, iclass 18, count 0 2006.285.07:38:02.56#ibcon#about to read 5, iclass 18, count 0 2006.285.07:38:02.56#ibcon#read 5, iclass 18, count 0 2006.285.07:38:02.56#ibcon#about to read 6, iclass 18, count 0 2006.285.07:38:02.56#ibcon#read 6, iclass 18, count 0 2006.285.07:38:02.56#ibcon#end of sib2, iclass 18, count 0 2006.285.07:38:02.56#ibcon#*mode == 0, iclass 18, count 0 2006.285.07:38:02.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.07:38:02.56#ibcon#[27=USB\r\n] 2006.285.07:38:02.56#ibcon#*before write, iclass 18, count 0 2006.285.07:38:02.56#ibcon#enter sib2, iclass 18, count 0 2006.285.07:38:02.56#ibcon#flushed, iclass 18, count 0 2006.285.07:38:02.56#ibcon#about to write, iclass 18, count 0 2006.285.07:38:02.56#ibcon#wrote, iclass 18, count 0 2006.285.07:38:02.56#ibcon#about to read 3, iclass 18, count 0 2006.285.07:38:02.59#ibcon#read 3, iclass 18, count 0 2006.285.07:38:02.59#ibcon#about to read 4, iclass 18, count 0 2006.285.07:38:02.59#ibcon#read 4, iclass 18, count 0 2006.285.07:38:02.59#ibcon#about to read 5, iclass 18, count 0 2006.285.07:38:02.59#ibcon#read 5, iclass 18, count 0 2006.285.07:38:02.59#ibcon#about to read 6, iclass 18, count 0 2006.285.07:38:02.59#ibcon#read 6, iclass 18, count 0 2006.285.07:38:02.59#ibcon#end of sib2, iclass 18, count 0 2006.285.07:38:02.59#ibcon#*after write, iclass 18, count 0 2006.285.07:38:02.59#ibcon#*before return 0, iclass 18, count 0 2006.285.07:38:02.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:38:02.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.07:38:02.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.07:38:02.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.07:38:02.60$vck44/vblo=7,734.99 2006.285.07:38:02.60#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.07:38:02.60#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.07:38:02.60#ibcon#ireg 17 cls_cnt 0 2006.285.07:38:02.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:38:02.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:38:02.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:38:02.60#ibcon#enter wrdev, iclass 20, count 0 2006.285.07:38:02.60#ibcon#first serial, iclass 20, count 0 2006.285.07:38:02.60#ibcon#enter sib2, iclass 20, count 0 2006.285.07:38:02.60#ibcon#flushed, iclass 20, count 0 2006.285.07:38:02.60#ibcon#about to write, iclass 20, count 0 2006.285.07:38:02.60#ibcon#wrote, iclass 20, count 0 2006.285.07:38:02.60#ibcon#about to read 3, iclass 20, count 0 2006.285.07:38:02.61#ibcon#read 3, iclass 20, count 0 2006.285.07:38:02.61#ibcon#about to read 4, iclass 20, count 0 2006.285.07:38:02.61#ibcon#read 4, iclass 20, count 0 2006.285.07:38:02.61#ibcon#about to read 5, iclass 20, count 0 2006.285.07:38:02.61#ibcon#read 5, iclass 20, count 0 2006.285.07:38:02.61#ibcon#about to read 6, iclass 20, count 0 2006.285.07:38:02.61#ibcon#read 6, iclass 20, count 0 2006.285.07:38:02.61#ibcon#end of sib2, iclass 20, count 0 2006.285.07:38:02.61#ibcon#*mode == 0, iclass 20, count 0 2006.285.07:38:02.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.07:38:02.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:38:02.61#ibcon#*before write, iclass 20, count 0 2006.285.07:38:02.61#ibcon#enter sib2, iclass 20, count 0 2006.285.07:38:02.61#ibcon#flushed, iclass 20, count 0 2006.285.07:38:02.61#ibcon#about to write, iclass 20, count 0 2006.285.07:38:02.61#ibcon#wrote, iclass 20, count 0 2006.285.07:38:02.61#ibcon#about to read 3, iclass 20, count 0 2006.285.07:38:02.65#ibcon#read 3, iclass 20, count 0 2006.285.07:38:02.65#ibcon#about to read 4, iclass 20, count 0 2006.285.07:38:02.65#ibcon#read 4, iclass 20, count 0 2006.285.07:38:02.65#ibcon#about to read 5, iclass 20, count 0 2006.285.07:38:02.65#ibcon#read 5, iclass 20, count 0 2006.285.07:38:02.65#ibcon#about to read 6, iclass 20, count 0 2006.285.07:38:02.65#ibcon#read 6, iclass 20, count 0 2006.285.07:38:02.65#ibcon#end of sib2, iclass 20, count 0 2006.285.07:38:02.65#ibcon#*after write, iclass 20, count 0 2006.285.07:38:02.65#ibcon#*before return 0, iclass 20, count 0 2006.285.07:38:02.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:38:02.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.07:38:02.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.07:38:02.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.07:38:02.66$vck44/vb=7,4 2006.285.07:38:02.66#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.07:38:02.66#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.07:38:02.66#ibcon#ireg 11 cls_cnt 2 2006.285.07:38:02.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:38:02.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:38:02.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:38:02.70#ibcon#enter wrdev, iclass 22, count 2 2006.285.07:38:02.70#ibcon#first serial, iclass 22, count 2 2006.285.07:38:02.70#ibcon#enter sib2, iclass 22, count 2 2006.285.07:38:02.70#ibcon#flushed, iclass 22, count 2 2006.285.07:38:02.70#ibcon#about to write, iclass 22, count 2 2006.285.07:38:02.70#ibcon#wrote, iclass 22, count 2 2006.285.07:38:02.70#ibcon#about to read 3, iclass 22, count 2 2006.285.07:38:02.72#ibcon#read 3, iclass 22, count 2 2006.285.07:38:02.72#ibcon#about to read 4, iclass 22, count 2 2006.285.07:38:02.72#ibcon#read 4, iclass 22, count 2 2006.285.07:38:02.72#ibcon#about to read 5, iclass 22, count 2 2006.285.07:38:02.72#ibcon#read 5, iclass 22, count 2 2006.285.07:38:02.72#ibcon#about to read 6, iclass 22, count 2 2006.285.07:38:02.72#ibcon#read 6, iclass 22, count 2 2006.285.07:38:02.72#ibcon#end of sib2, iclass 22, count 2 2006.285.07:38:02.72#ibcon#*mode == 0, iclass 22, count 2 2006.285.07:38:02.72#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.07:38:02.72#ibcon#[27=AT07-04\r\n] 2006.285.07:38:02.72#ibcon#*before write, iclass 22, count 2 2006.285.07:38:02.72#ibcon#enter sib2, iclass 22, count 2 2006.285.07:38:02.72#ibcon#flushed, iclass 22, count 2 2006.285.07:38:02.72#ibcon#about to write, iclass 22, count 2 2006.285.07:38:02.72#ibcon#wrote, iclass 22, count 2 2006.285.07:38:02.72#ibcon#about to read 3, iclass 22, count 2 2006.285.07:38:02.75#ibcon#read 3, iclass 22, count 2 2006.285.07:38:02.75#ibcon#about to read 4, iclass 22, count 2 2006.285.07:38:02.75#ibcon#read 4, iclass 22, count 2 2006.285.07:38:02.75#ibcon#about to read 5, iclass 22, count 2 2006.285.07:38:02.75#ibcon#read 5, iclass 22, count 2 2006.285.07:38:02.75#ibcon#about to read 6, iclass 22, count 2 2006.285.07:38:02.75#ibcon#read 6, iclass 22, count 2 2006.285.07:38:02.75#ibcon#end of sib2, iclass 22, count 2 2006.285.07:38:02.75#ibcon#*after write, iclass 22, count 2 2006.285.07:38:02.75#ibcon#*before return 0, iclass 22, count 2 2006.285.07:38:02.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:38:02.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.07:38:02.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.07:38:02.75#ibcon#ireg 7 cls_cnt 0 2006.285.07:38:02.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:38:02.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:38:02.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:38:02.87#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:38:02.87#ibcon#first serial, iclass 22, count 0 2006.285.07:38:02.87#ibcon#enter sib2, iclass 22, count 0 2006.285.07:38:02.87#ibcon#flushed, iclass 22, count 0 2006.285.07:38:02.87#ibcon#about to write, iclass 22, count 0 2006.285.07:38:02.87#ibcon#wrote, iclass 22, count 0 2006.285.07:38:02.87#ibcon#about to read 3, iclass 22, count 0 2006.285.07:38:02.89#ibcon#read 3, iclass 22, count 0 2006.285.07:38:02.89#ibcon#about to read 4, iclass 22, count 0 2006.285.07:38:02.89#ibcon#read 4, iclass 22, count 0 2006.285.07:38:02.89#ibcon#about to read 5, iclass 22, count 0 2006.285.07:38:02.89#ibcon#read 5, iclass 22, count 0 2006.285.07:38:02.89#ibcon#about to read 6, iclass 22, count 0 2006.285.07:38:02.89#ibcon#read 6, iclass 22, count 0 2006.285.07:38:02.89#ibcon#end of sib2, iclass 22, count 0 2006.285.07:38:02.89#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:38:02.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:38:02.89#ibcon#[27=USB\r\n] 2006.285.07:38:02.89#ibcon#*before write, iclass 22, count 0 2006.285.07:38:02.89#ibcon#enter sib2, iclass 22, count 0 2006.285.07:38:02.89#ibcon#flushed, iclass 22, count 0 2006.285.07:38:02.89#ibcon#about to write, iclass 22, count 0 2006.285.07:38:02.89#ibcon#wrote, iclass 22, count 0 2006.285.07:38:02.89#ibcon#about to read 3, iclass 22, count 0 2006.285.07:38:02.92#ibcon#read 3, iclass 22, count 0 2006.285.07:38:02.92#ibcon#about to read 4, iclass 22, count 0 2006.285.07:38:02.92#ibcon#read 4, iclass 22, count 0 2006.285.07:38:02.92#ibcon#about to read 5, iclass 22, count 0 2006.285.07:38:02.92#ibcon#read 5, iclass 22, count 0 2006.285.07:38:02.92#ibcon#about to read 6, iclass 22, count 0 2006.285.07:38:02.92#ibcon#read 6, iclass 22, count 0 2006.285.07:38:02.92#ibcon#end of sib2, iclass 22, count 0 2006.285.07:38:02.92#ibcon#*after write, iclass 22, count 0 2006.285.07:38:02.92#ibcon#*before return 0, iclass 22, count 0 2006.285.07:38:02.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:38:02.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.07:38:02.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:38:02.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:38:02.93$vck44/vblo=8,744.99 2006.285.07:38:02.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.07:38:02.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.07:38:02.93#ibcon#ireg 17 cls_cnt 0 2006.285.07:38:02.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:38:02.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:38:02.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:38:02.93#ibcon#enter wrdev, iclass 24, count 0 2006.285.07:38:02.93#ibcon#first serial, iclass 24, count 0 2006.285.07:38:02.93#ibcon#enter sib2, iclass 24, count 0 2006.285.07:38:02.93#ibcon#flushed, iclass 24, count 0 2006.285.07:38:02.93#ibcon#about to write, iclass 24, count 0 2006.285.07:38:02.93#ibcon#wrote, iclass 24, count 0 2006.285.07:38:02.93#ibcon#about to read 3, iclass 24, count 0 2006.285.07:38:02.94#ibcon#read 3, iclass 24, count 0 2006.285.07:38:02.94#ibcon#about to read 4, iclass 24, count 0 2006.285.07:38:02.94#ibcon#read 4, iclass 24, count 0 2006.285.07:38:02.94#ibcon#about to read 5, iclass 24, count 0 2006.285.07:38:02.94#ibcon#read 5, iclass 24, count 0 2006.285.07:38:02.94#ibcon#about to read 6, iclass 24, count 0 2006.285.07:38:02.94#ibcon#read 6, iclass 24, count 0 2006.285.07:38:02.94#ibcon#end of sib2, iclass 24, count 0 2006.285.07:38:02.94#ibcon#*mode == 0, iclass 24, count 0 2006.285.07:38:02.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.07:38:02.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:38:02.94#ibcon#*before write, iclass 24, count 0 2006.285.07:38:02.94#ibcon#enter sib2, iclass 24, count 0 2006.285.07:38:02.94#ibcon#flushed, iclass 24, count 0 2006.285.07:38:02.94#ibcon#about to write, iclass 24, count 0 2006.285.07:38:02.94#ibcon#wrote, iclass 24, count 0 2006.285.07:38:02.94#ibcon#about to read 3, iclass 24, count 0 2006.285.07:38:02.98#ibcon#read 3, iclass 24, count 0 2006.285.07:38:02.98#ibcon#about to read 4, iclass 24, count 0 2006.285.07:38:02.98#ibcon#read 4, iclass 24, count 0 2006.285.07:38:02.98#ibcon#about to read 5, iclass 24, count 0 2006.285.07:38:02.98#ibcon#read 5, iclass 24, count 0 2006.285.07:38:02.98#ibcon#about to read 6, iclass 24, count 0 2006.285.07:38:02.98#ibcon#read 6, iclass 24, count 0 2006.285.07:38:02.98#ibcon#end of sib2, iclass 24, count 0 2006.285.07:38:02.98#ibcon#*after write, iclass 24, count 0 2006.285.07:38:02.98#ibcon#*before return 0, iclass 24, count 0 2006.285.07:38:02.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:38:02.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.07:38:02.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.07:38:02.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.07:38:02.99$vck44/vb=8,4 2006.285.07:38:02.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.07:38:02.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.07:38:02.99#ibcon#ireg 11 cls_cnt 2 2006.285.07:38:02.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:38:03.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:38:03.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:38:03.03#ibcon#enter wrdev, iclass 26, count 2 2006.285.07:38:03.03#ibcon#first serial, iclass 26, count 2 2006.285.07:38:03.03#ibcon#enter sib2, iclass 26, count 2 2006.285.07:38:03.03#ibcon#flushed, iclass 26, count 2 2006.285.07:38:03.03#ibcon#about to write, iclass 26, count 2 2006.285.07:38:03.03#ibcon#wrote, iclass 26, count 2 2006.285.07:38:03.03#ibcon#about to read 3, iclass 26, count 2 2006.285.07:38:03.05#ibcon#read 3, iclass 26, count 2 2006.285.07:38:03.05#ibcon#about to read 4, iclass 26, count 2 2006.285.07:38:03.05#ibcon#read 4, iclass 26, count 2 2006.285.07:38:03.05#ibcon#about to read 5, iclass 26, count 2 2006.285.07:38:03.05#ibcon#read 5, iclass 26, count 2 2006.285.07:38:03.05#ibcon#about to read 6, iclass 26, count 2 2006.285.07:38:03.05#ibcon#read 6, iclass 26, count 2 2006.285.07:38:03.05#ibcon#end of sib2, iclass 26, count 2 2006.285.07:38:03.05#ibcon#*mode == 0, iclass 26, count 2 2006.285.07:38:03.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.07:38:03.05#ibcon#[27=AT08-04\r\n] 2006.285.07:38:03.05#ibcon#*before write, iclass 26, count 2 2006.285.07:38:03.05#ibcon#enter sib2, iclass 26, count 2 2006.285.07:38:03.05#ibcon#flushed, iclass 26, count 2 2006.285.07:38:03.05#ibcon#about to write, iclass 26, count 2 2006.285.07:38:03.05#ibcon#wrote, iclass 26, count 2 2006.285.07:38:03.05#ibcon#about to read 3, iclass 26, count 2 2006.285.07:38:03.08#ibcon#read 3, iclass 26, count 2 2006.285.07:38:03.08#ibcon#about to read 4, iclass 26, count 2 2006.285.07:38:03.08#ibcon#read 4, iclass 26, count 2 2006.285.07:38:03.08#ibcon#about to read 5, iclass 26, count 2 2006.285.07:38:03.08#ibcon#read 5, iclass 26, count 2 2006.285.07:38:03.08#ibcon#about to read 6, iclass 26, count 2 2006.285.07:38:03.08#ibcon#read 6, iclass 26, count 2 2006.285.07:38:03.08#ibcon#end of sib2, iclass 26, count 2 2006.285.07:38:03.08#ibcon#*after write, iclass 26, count 2 2006.285.07:38:03.08#ibcon#*before return 0, iclass 26, count 2 2006.285.07:38:03.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:38:03.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.07:38:03.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.07:38:03.08#ibcon#ireg 7 cls_cnt 0 2006.285.07:38:03.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:38:03.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:38:03.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:38:03.20#ibcon#enter wrdev, iclass 26, count 0 2006.285.07:38:03.20#ibcon#first serial, iclass 26, count 0 2006.285.07:38:03.20#ibcon#enter sib2, iclass 26, count 0 2006.285.07:38:03.20#ibcon#flushed, iclass 26, count 0 2006.285.07:38:03.20#ibcon#about to write, iclass 26, count 0 2006.285.07:38:03.20#ibcon#wrote, iclass 26, count 0 2006.285.07:38:03.20#ibcon#about to read 3, iclass 26, count 0 2006.285.07:38:03.22#ibcon#read 3, iclass 26, count 0 2006.285.07:38:03.22#ibcon#about to read 4, iclass 26, count 0 2006.285.07:38:03.22#ibcon#read 4, iclass 26, count 0 2006.285.07:38:03.22#ibcon#about to read 5, iclass 26, count 0 2006.285.07:38:03.22#ibcon#read 5, iclass 26, count 0 2006.285.07:38:03.22#ibcon#about to read 6, iclass 26, count 0 2006.285.07:38:03.22#ibcon#read 6, iclass 26, count 0 2006.285.07:38:03.22#ibcon#end of sib2, iclass 26, count 0 2006.285.07:38:03.22#ibcon#*mode == 0, iclass 26, count 0 2006.285.07:38:03.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.07:38:03.22#ibcon#[27=USB\r\n] 2006.285.07:38:03.22#ibcon#*before write, iclass 26, count 0 2006.285.07:38:03.22#ibcon#enter sib2, iclass 26, count 0 2006.285.07:38:03.22#ibcon#flushed, iclass 26, count 0 2006.285.07:38:03.22#ibcon#about to write, iclass 26, count 0 2006.285.07:38:03.22#ibcon#wrote, iclass 26, count 0 2006.285.07:38:03.22#ibcon#about to read 3, iclass 26, count 0 2006.285.07:38:03.25#ibcon#read 3, iclass 26, count 0 2006.285.07:38:03.25#ibcon#about to read 4, iclass 26, count 0 2006.285.07:38:03.25#ibcon#read 4, iclass 26, count 0 2006.285.07:38:03.25#ibcon#about to read 5, iclass 26, count 0 2006.285.07:38:03.25#ibcon#read 5, iclass 26, count 0 2006.285.07:38:03.25#ibcon#about to read 6, iclass 26, count 0 2006.285.07:38:03.25#ibcon#read 6, iclass 26, count 0 2006.285.07:38:03.25#ibcon#end of sib2, iclass 26, count 0 2006.285.07:38:03.25#ibcon#*after write, iclass 26, count 0 2006.285.07:38:03.25#ibcon#*before return 0, iclass 26, count 0 2006.285.07:38:03.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:38:03.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.07:38:03.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.07:38:03.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.07:38:03.26$vck44/vabw=wide 2006.285.07:38:03.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.07:38:03.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.07:38:03.26#ibcon#ireg 8 cls_cnt 0 2006.285.07:38:03.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:38:03.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:38:03.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:38:03.26#ibcon#enter wrdev, iclass 28, count 0 2006.285.07:38:03.26#ibcon#first serial, iclass 28, count 0 2006.285.07:38:03.26#ibcon#enter sib2, iclass 28, count 0 2006.285.07:38:03.26#ibcon#flushed, iclass 28, count 0 2006.285.07:38:03.26#ibcon#about to write, iclass 28, count 0 2006.285.07:38:03.26#ibcon#wrote, iclass 28, count 0 2006.285.07:38:03.26#ibcon#about to read 3, iclass 28, count 0 2006.285.07:38:03.27#ibcon#read 3, iclass 28, count 0 2006.285.07:38:03.27#ibcon#about to read 4, iclass 28, count 0 2006.285.07:38:03.27#ibcon#read 4, iclass 28, count 0 2006.285.07:38:03.27#ibcon#about to read 5, iclass 28, count 0 2006.285.07:38:03.27#ibcon#read 5, iclass 28, count 0 2006.285.07:38:03.27#ibcon#about to read 6, iclass 28, count 0 2006.285.07:38:03.27#ibcon#read 6, iclass 28, count 0 2006.285.07:38:03.27#ibcon#end of sib2, iclass 28, count 0 2006.285.07:38:03.27#ibcon#*mode == 0, iclass 28, count 0 2006.285.07:38:03.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.07:38:03.27#ibcon#[25=BW32\r\n] 2006.285.07:38:03.27#ibcon#*before write, iclass 28, count 0 2006.285.07:38:03.27#ibcon#enter sib2, iclass 28, count 0 2006.285.07:38:03.27#ibcon#flushed, iclass 28, count 0 2006.285.07:38:03.27#ibcon#about to write, iclass 28, count 0 2006.285.07:38:03.27#ibcon#wrote, iclass 28, count 0 2006.285.07:38:03.27#ibcon#about to read 3, iclass 28, count 0 2006.285.07:38:03.30#ibcon#read 3, iclass 28, count 0 2006.285.07:38:03.30#ibcon#about to read 4, iclass 28, count 0 2006.285.07:38:03.30#ibcon#read 4, iclass 28, count 0 2006.285.07:38:03.30#ibcon#about to read 5, iclass 28, count 0 2006.285.07:38:03.30#ibcon#read 5, iclass 28, count 0 2006.285.07:38:03.30#ibcon#about to read 6, iclass 28, count 0 2006.285.07:38:03.30#ibcon#read 6, iclass 28, count 0 2006.285.07:38:03.30#ibcon#end of sib2, iclass 28, count 0 2006.285.07:38:03.30#ibcon#*after write, iclass 28, count 0 2006.285.07:38:03.30#ibcon#*before return 0, iclass 28, count 0 2006.285.07:38:03.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:38:03.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.07:38:03.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.07:38:03.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.07:38:03.31$vck44/vbbw=wide 2006.285.07:38:03.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.07:38:03.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.07:38:03.31#ibcon#ireg 8 cls_cnt 0 2006.285.07:38:03.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:38:03.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:38:03.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:38:03.36#ibcon#enter wrdev, iclass 30, count 0 2006.285.07:38:03.36#ibcon#first serial, iclass 30, count 0 2006.285.07:38:03.36#ibcon#enter sib2, iclass 30, count 0 2006.285.07:38:03.36#ibcon#flushed, iclass 30, count 0 2006.285.07:38:03.36#ibcon#about to write, iclass 30, count 0 2006.285.07:38:03.36#ibcon#wrote, iclass 30, count 0 2006.285.07:38:03.36#ibcon#about to read 3, iclass 30, count 0 2006.285.07:38:03.38#ibcon#read 3, iclass 30, count 0 2006.285.07:38:03.38#ibcon#about to read 4, iclass 30, count 0 2006.285.07:38:03.38#ibcon#read 4, iclass 30, count 0 2006.285.07:38:03.38#ibcon#about to read 5, iclass 30, count 0 2006.285.07:38:03.38#ibcon#read 5, iclass 30, count 0 2006.285.07:38:03.38#ibcon#about to read 6, iclass 30, count 0 2006.285.07:38:03.38#ibcon#read 6, iclass 30, count 0 2006.285.07:38:03.38#ibcon#end of sib2, iclass 30, count 0 2006.285.07:38:03.38#ibcon#*mode == 0, iclass 30, count 0 2006.285.07:38:03.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.07:38:03.38#ibcon#[27=BW32\r\n] 2006.285.07:38:03.38#ibcon#*before write, iclass 30, count 0 2006.285.07:38:03.38#ibcon#enter sib2, iclass 30, count 0 2006.285.07:38:03.38#ibcon#flushed, iclass 30, count 0 2006.285.07:38:03.38#ibcon#about to write, iclass 30, count 0 2006.285.07:38:03.38#ibcon#wrote, iclass 30, count 0 2006.285.07:38:03.38#ibcon#about to read 3, iclass 30, count 0 2006.285.07:38:03.41#ibcon#read 3, iclass 30, count 0 2006.285.07:38:03.41#ibcon#about to read 4, iclass 30, count 0 2006.285.07:38:03.41#ibcon#read 4, iclass 30, count 0 2006.285.07:38:03.41#ibcon#about to read 5, iclass 30, count 0 2006.285.07:38:03.41#ibcon#read 5, iclass 30, count 0 2006.285.07:38:03.41#ibcon#about to read 6, iclass 30, count 0 2006.285.07:38:03.41#ibcon#read 6, iclass 30, count 0 2006.285.07:38:03.41#ibcon#end of sib2, iclass 30, count 0 2006.285.07:38:03.41#ibcon#*after write, iclass 30, count 0 2006.285.07:38:03.41#ibcon#*before return 0, iclass 30, count 0 2006.285.07:38:03.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:38:03.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:38:03.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.07:38:03.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.07:38:03.42$setupk4/ifdk4 2006.285.07:38:03.42$ifdk4/lo= 2006.285.07:38:03.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:38:03.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:38:03.42$ifdk4/patch= 2006.285.07:38:03.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:38:03.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:38:03.42$setupk4/!*+20s 2006.285.07:38:08.39#abcon#<5=/05 2.7 4.8 23.52 771014.3\r\n> 2006.285.07:38:08.41#abcon#{5=INTERFACE CLEAR} 2006.285.07:38:08.47#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:38:13.14#trakl#Source acquired 2006.285.07:38:14.15#flagr#flagr/antenna,acquired 2006.285.07:38:18.07$setupk4/"tpicd 2006.285.07:38:18.07$setupk4/echo=off 2006.285.07:38:18.07$setupk4/xlog=off 2006.285.07:38:18.07:!2006.285.07:38:40 2006.285.07:38:40.02:preob 2006.285.07:38:41.14/onsource/TRACKING 2006.285.07:38:41.14:!2006.285.07:38:50 2006.285.07:38:50.01:"tape 2006.285.07:38:50.02:"st=record 2006.285.07:38:50.02:data_valid=on 2006.285.07:38:50.02:midob 2006.285.07:38:51.14/onsource/TRACKING 2006.285.07:38:51.14/wx/23.50,1014.3,77 2006.285.07:38:51.23/cable/+6.4731E-03 2006.285.07:38:52.32/va/01,07,usb,yes,33,36 2006.285.07:38:52.32/va/02,06,usb,yes,33,34 2006.285.07:38:52.32/va/03,07,usb,yes,33,35 2006.285.07:38:52.32/va/04,06,usb,yes,34,36 2006.285.07:38:52.32/va/05,03,usb,yes,34,34 2006.285.07:38:52.32/va/06,04,usb,yes,30,30 2006.285.07:38:52.32/va/07,04,usb,yes,31,32 2006.285.07:38:52.32/va/08,03,usb,yes,32,39 2006.285.07:38:52.55/valo/01,524.99,yes,locked 2006.285.07:38:52.55/valo/02,534.99,yes,locked 2006.285.07:38:52.55/valo/03,564.99,yes,locked 2006.285.07:38:52.55/valo/04,624.99,yes,locked 2006.285.07:38:52.55/valo/05,734.99,yes,locked 2006.285.07:38:52.55/valo/06,814.99,yes,locked 2006.285.07:38:52.55/valo/07,864.99,yes,locked 2006.285.07:38:52.55/valo/08,884.99,yes,locked 2006.285.07:38:53.64/vb/01,04,usb,yes,31,29 2006.285.07:38:53.64/vb/02,05,usb,yes,30,30 2006.285.07:38:53.64/vb/03,04,usb,yes,31,34 2006.285.07:38:53.64/vb/04,05,usb,yes,31,30 2006.285.07:38:53.64/vb/05,04,usb,yes,27,30 2006.285.07:38:53.64/vb/06,03,usb,yes,39,35 2006.285.07:38:53.64/vb/07,04,usb,yes,32,32 2006.285.07:38:53.64/vb/08,04,usb,yes,29,32 2006.285.07:38:53.87/vblo/01,629.99,yes,locked 2006.285.07:38:53.87/vblo/02,634.99,yes,locked 2006.285.07:38:53.87/vblo/03,649.99,yes,locked 2006.285.07:38:53.87/vblo/04,679.99,yes,locked 2006.285.07:38:53.87/vblo/05,709.99,yes,locked 2006.285.07:38:53.87/vblo/06,719.99,yes,locked 2006.285.07:38:53.87/vblo/07,734.99,yes,locked 2006.285.07:38:53.87/vblo/08,744.99,yes,locked 2006.285.07:38:54.02/vabw/8 2006.285.07:38:54.17/vbbw/8 2006.285.07:38:54.33/xfe/off,on,12.2 2006.285.07:38:54.72/ifatt/23,28,28,28 2006.285.07:38:55.07/fmout-gps/S +2.71E-07 2006.285.07:38:55.09:!2006.285.07:40:50 2006.285.07:40:50.00:data_valid=off 2006.285.07:40:50.00:"et 2006.285.07:40:50.01:!+3s 2006.285.07:40:53.03:"tape 2006.285.07:40:53.03:postob 2006.285.07:40:53.23/cable/+6.4739E-03 2006.285.07:40:53.23/wx/23.45,1014.4,77 2006.285.07:40:53.29/fmout-gps/S +2.72E-07 2006.285.07:40:53.29:scan_name=285-0746,jd0610,80 2006.285.07:40:53.29:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.285.07:40:54.14#flagr#flagr/antenna,new-source 2006.285.07:40:54.15:checkk5 2006.285.07:40:54.76/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:40:55.17/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:40:55.57/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:40:55.98/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:40:56.36/chk_obsdata//k5ts1/T2850738??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.285.07:40:56.69/chk_obsdata//k5ts2/T2850738??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.285.07:40:57.36/chk_obsdata//k5ts3/T2850738??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.285.07:40:57.73/chk_obsdata//k5ts4/T2850738??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.285.07:40:58.56/k5log//k5ts1_log_newline 2006.285.07:40:59.39/k5log//k5ts2_log_newline 2006.285.07:41:00.13/k5log//k5ts3_log_newline 2006.285.07:41:00.90/k5log//k5ts4_log_newline 2006.285.07:41:00.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:41:00.92:setupk4=1 2006.285.07:41:00.92$setupk4/echo=on 2006.285.07:41:00.92$setupk4/pcalon 2006.285.07:41:00.92$pcalon/"no phase cal control is implemented here 2006.285.07:41:00.92$setupk4/"tpicd=stop 2006.285.07:41:00.92$setupk4/"rec=synch_on 2006.285.07:41:00.93$setupk4/"rec_mode=128 2006.285.07:41:00.93$setupk4/!* 2006.285.07:41:00.93$setupk4/recpk4 2006.285.07:41:00.93$recpk4/recpatch= 2006.285.07:41:00.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:41:00.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:41:00.93$setupk4/vck44 2006.285.07:41:00.93$vck44/valo=1,524.99 2006.285.07:41:00.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.07:41:00.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.07:41:00.93#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:00.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:41:00.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:41:00.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:41:00.93#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:41:00.93#ibcon#first serial, iclass 31, count 0 2006.285.07:41:00.93#ibcon#enter sib2, iclass 31, count 0 2006.285.07:41:00.93#ibcon#flushed, iclass 31, count 0 2006.285.07:41:00.93#ibcon#about to write, iclass 31, count 0 2006.285.07:41:00.93#ibcon#wrote, iclass 31, count 0 2006.285.07:41:00.93#ibcon#about to read 3, iclass 31, count 0 2006.285.07:41:00.94#ibcon#read 3, iclass 31, count 0 2006.285.07:41:00.94#ibcon#about to read 4, iclass 31, count 0 2006.285.07:41:00.94#ibcon#read 4, iclass 31, count 0 2006.285.07:41:00.94#ibcon#about to read 5, iclass 31, count 0 2006.285.07:41:00.94#ibcon#read 5, iclass 31, count 0 2006.285.07:41:00.94#ibcon#about to read 6, iclass 31, count 0 2006.285.07:41:00.94#ibcon#read 6, iclass 31, count 0 2006.285.07:41:00.94#ibcon#end of sib2, iclass 31, count 0 2006.285.07:41:00.94#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:41:00.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:41:00.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:41:00.94#ibcon#*before write, iclass 31, count 0 2006.285.07:41:00.94#ibcon#enter sib2, iclass 31, count 0 2006.285.07:41:00.94#ibcon#flushed, iclass 31, count 0 2006.285.07:41:00.94#ibcon#about to write, iclass 31, count 0 2006.285.07:41:00.94#ibcon#wrote, iclass 31, count 0 2006.285.07:41:00.94#ibcon#about to read 3, iclass 31, count 0 2006.285.07:41:00.99#ibcon#read 3, iclass 31, count 0 2006.285.07:41:00.99#ibcon#about to read 4, iclass 31, count 0 2006.285.07:41:00.99#ibcon#read 4, iclass 31, count 0 2006.285.07:41:00.99#ibcon#about to read 5, iclass 31, count 0 2006.285.07:41:00.99#ibcon#read 5, iclass 31, count 0 2006.285.07:41:00.99#ibcon#about to read 6, iclass 31, count 0 2006.285.07:41:00.99#ibcon#read 6, iclass 31, count 0 2006.285.07:41:00.99#ibcon#end of sib2, iclass 31, count 0 2006.285.07:41:00.99#ibcon#*after write, iclass 31, count 0 2006.285.07:41:00.99#ibcon#*before return 0, iclass 31, count 0 2006.285.07:41:00.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:41:00.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:41:00.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:41:00.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:41:00.99$vck44/va=1,7 2006.285.07:41:00.99#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.07:41:00.99#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.07:41:00.99#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:00.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:41:00.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:41:00.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:41:00.99#ibcon#enter wrdev, iclass 33, count 2 2006.285.07:41:00.99#ibcon#first serial, iclass 33, count 2 2006.285.07:41:00.99#ibcon#enter sib2, iclass 33, count 2 2006.285.07:41:00.99#ibcon#flushed, iclass 33, count 2 2006.285.07:41:00.99#ibcon#about to write, iclass 33, count 2 2006.285.07:41:00.99#ibcon#wrote, iclass 33, count 2 2006.285.07:41:00.99#ibcon#about to read 3, iclass 33, count 2 2006.285.07:41:01.01#ibcon#read 3, iclass 33, count 2 2006.285.07:41:01.01#ibcon#about to read 4, iclass 33, count 2 2006.285.07:41:01.01#ibcon#read 4, iclass 33, count 2 2006.285.07:41:01.01#ibcon#about to read 5, iclass 33, count 2 2006.285.07:41:01.01#ibcon#read 5, iclass 33, count 2 2006.285.07:41:01.01#ibcon#about to read 6, iclass 33, count 2 2006.285.07:41:01.01#ibcon#read 6, iclass 33, count 2 2006.285.07:41:01.01#ibcon#end of sib2, iclass 33, count 2 2006.285.07:41:01.01#ibcon#*mode == 0, iclass 33, count 2 2006.285.07:41:01.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.07:41:01.01#ibcon#[25=AT01-07\r\n] 2006.285.07:41:01.01#ibcon#*before write, iclass 33, count 2 2006.285.07:41:01.01#ibcon#enter sib2, iclass 33, count 2 2006.285.07:41:01.01#ibcon#flushed, iclass 33, count 2 2006.285.07:41:01.01#ibcon#about to write, iclass 33, count 2 2006.285.07:41:01.01#ibcon#wrote, iclass 33, count 2 2006.285.07:41:01.01#ibcon#about to read 3, iclass 33, count 2 2006.285.07:41:01.04#ibcon#read 3, iclass 33, count 2 2006.285.07:41:01.04#ibcon#about to read 4, iclass 33, count 2 2006.285.07:41:01.04#ibcon#read 4, iclass 33, count 2 2006.285.07:41:01.04#ibcon#about to read 5, iclass 33, count 2 2006.285.07:41:01.04#ibcon#read 5, iclass 33, count 2 2006.285.07:41:01.04#ibcon#about to read 6, iclass 33, count 2 2006.285.07:41:01.04#ibcon#read 6, iclass 33, count 2 2006.285.07:41:01.04#ibcon#end of sib2, iclass 33, count 2 2006.285.07:41:01.04#ibcon#*after write, iclass 33, count 2 2006.285.07:41:01.04#ibcon#*before return 0, iclass 33, count 2 2006.285.07:41:01.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:41:01.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:41:01.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.07:41:01.04#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:01.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:41:01.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:41:01.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:41:01.16#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:41:01.16#ibcon#first serial, iclass 33, count 0 2006.285.07:41:01.16#ibcon#enter sib2, iclass 33, count 0 2006.285.07:41:01.16#ibcon#flushed, iclass 33, count 0 2006.285.07:41:01.16#ibcon#about to write, iclass 33, count 0 2006.285.07:41:01.16#ibcon#wrote, iclass 33, count 0 2006.285.07:41:01.16#ibcon#about to read 3, iclass 33, count 0 2006.285.07:41:01.18#ibcon#read 3, iclass 33, count 0 2006.285.07:41:01.18#ibcon#about to read 4, iclass 33, count 0 2006.285.07:41:01.18#ibcon#read 4, iclass 33, count 0 2006.285.07:41:01.18#ibcon#about to read 5, iclass 33, count 0 2006.285.07:41:01.18#ibcon#read 5, iclass 33, count 0 2006.285.07:41:01.18#ibcon#about to read 6, iclass 33, count 0 2006.285.07:41:01.18#ibcon#read 6, iclass 33, count 0 2006.285.07:41:01.18#ibcon#end of sib2, iclass 33, count 0 2006.285.07:41:01.18#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:41:01.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:41:01.18#ibcon#[25=USB\r\n] 2006.285.07:41:01.18#ibcon#*before write, iclass 33, count 0 2006.285.07:41:01.18#ibcon#enter sib2, iclass 33, count 0 2006.285.07:41:01.18#ibcon#flushed, iclass 33, count 0 2006.285.07:41:01.18#ibcon#about to write, iclass 33, count 0 2006.285.07:41:01.18#ibcon#wrote, iclass 33, count 0 2006.285.07:41:01.18#ibcon#about to read 3, iclass 33, count 0 2006.285.07:41:01.21#ibcon#read 3, iclass 33, count 0 2006.285.07:41:01.21#ibcon#about to read 4, iclass 33, count 0 2006.285.07:41:01.21#ibcon#read 4, iclass 33, count 0 2006.285.07:41:01.21#ibcon#about to read 5, iclass 33, count 0 2006.285.07:41:01.21#ibcon#read 5, iclass 33, count 0 2006.285.07:41:01.21#ibcon#about to read 6, iclass 33, count 0 2006.285.07:41:01.21#ibcon#read 6, iclass 33, count 0 2006.285.07:41:01.21#ibcon#end of sib2, iclass 33, count 0 2006.285.07:41:01.21#ibcon#*after write, iclass 33, count 0 2006.285.07:41:01.21#ibcon#*before return 0, iclass 33, count 0 2006.285.07:41:01.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:41:01.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:41:01.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:41:01.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:41:01.21$vck44/valo=2,534.99 2006.285.07:41:01.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.07:41:01.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.07:41:01.21#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:01.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:41:01.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:41:01.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:41:01.21#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:41:01.21#ibcon#first serial, iclass 35, count 0 2006.285.07:41:01.21#ibcon#enter sib2, iclass 35, count 0 2006.285.07:41:01.21#ibcon#flushed, iclass 35, count 0 2006.285.07:41:01.21#ibcon#about to write, iclass 35, count 0 2006.285.07:41:01.21#ibcon#wrote, iclass 35, count 0 2006.285.07:41:01.21#ibcon#about to read 3, iclass 35, count 0 2006.285.07:41:01.23#ibcon#read 3, iclass 35, count 0 2006.285.07:41:01.23#ibcon#about to read 4, iclass 35, count 0 2006.285.07:41:01.23#ibcon#read 4, iclass 35, count 0 2006.285.07:41:01.23#ibcon#about to read 5, iclass 35, count 0 2006.285.07:41:01.23#ibcon#read 5, iclass 35, count 0 2006.285.07:41:01.23#ibcon#about to read 6, iclass 35, count 0 2006.285.07:41:01.23#ibcon#read 6, iclass 35, count 0 2006.285.07:41:01.23#ibcon#end of sib2, iclass 35, count 0 2006.285.07:41:01.23#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:41:01.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:41:01.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:41:01.23#ibcon#*before write, iclass 35, count 0 2006.285.07:41:01.23#ibcon#enter sib2, iclass 35, count 0 2006.285.07:41:01.23#ibcon#flushed, iclass 35, count 0 2006.285.07:41:01.23#ibcon#about to write, iclass 35, count 0 2006.285.07:41:01.23#ibcon#wrote, iclass 35, count 0 2006.285.07:41:01.23#ibcon#about to read 3, iclass 35, count 0 2006.285.07:41:01.27#ibcon#read 3, iclass 35, count 0 2006.285.07:41:01.27#ibcon#about to read 4, iclass 35, count 0 2006.285.07:41:01.27#ibcon#read 4, iclass 35, count 0 2006.285.07:41:01.27#ibcon#about to read 5, iclass 35, count 0 2006.285.07:41:01.27#ibcon#read 5, iclass 35, count 0 2006.285.07:41:01.27#ibcon#about to read 6, iclass 35, count 0 2006.285.07:41:01.27#ibcon#read 6, iclass 35, count 0 2006.285.07:41:01.27#ibcon#end of sib2, iclass 35, count 0 2006.285.07:41:01.27#ibcon#*after write, iclass 35, count 0 2006.285.07:41:01.27#ibcon#*before return 0, iclass 35, count 0 2006.285.07:41:01.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:41:01.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:41:01.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:41:01.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:41:01.27$vck44/va=2,6 2006.285.07:41:01.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.07:41:01.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.07:41:01.27#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:01.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:41:01.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:41:01.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:41:01.33#ibcon#enter wrdev, iclass 37, count 2 2006.285.07:41:01.33#ibcon#first serial, iclass 37, count 2 2006.285.07:41:01.33#ibcon#enter sib2, iclass 37, count 2 2006.285.07:41:01.33#ibcon#flushed, iclass 37, count 2 2006.285.07:41:01.33#ibcon#about to write, iclass 37, count 2 2006.285.07:41:01.33#ibcon#wrote, iclass 37, count 2 2006.285.07:41:01.33#ibcon#about to read 3, iclass 37, count 2 2006.285.07:41:01.35#ibcon#read 3, iclass 37, count 2 2006.285.07:41:01.35#ibcon#about to read 4, iclass 37, count 2 2006.285.07:41:01.35#ibcon#read 4, iclass 37, count 2 2006.285.07:41:01.35#ibcon#about to read 5, iclass 37, count 2 2006.285.07:41:01.35#ibcon#read 5, iclass 37, count 2 2006.285.07:41:01.35#ibcon#about to read 6, iclass 37, count 2 2006.285.07:41:01.35#ibcon#read 6, iclass 37, count 2 2006.285.07:41:01.35#ibcon#end of sib2, iclass 37, count 2 2006.285.07:41:01.35#ibcon#*mode == 0, iclass 37, count 2 2006.285.07:41:01.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.07:41:01.35#ibcon#[25=AT02-06\r\n] 2006.285.07:41:01.35#ibcon#*before write, iclass 37, count 2 2006.285.07:41:01.35#ibcon#enter sib2, iclass 37, count 2 2006.285.07:41:01.35#ibcon#flushed, iclass 37, count 2 2006.285.07:41:01.35#ibcon#about to write, iclass 37, count 2 2006.285.07:41:01.35#ibcon#wrote, iclass 37, count 2 2006.285.07:41:01.35#ibcon#about to read 3, iclass 37, count 2 2006.285.07:41:01.37#abcon#<5=/05 2.7 4.8 23.45 781014.3\r\n> 2006.285.07:41:01.38#ibcon#read 3, iclass 37, count 2 2006.285.07:41:01.38#ibcon#about to read 4, iclass 37, count 2 2006.285.07:41:01.38#ibcon#read 4, iclass 37, count 2 2006.285.07:41:01.38#ibcon#about to read 5, iclass 37, count 2 2006.285.07:41:01.38#ibcon#read 5, iclass 37, count 2 2006.285.07:41:01.38#ibcon#about to read 6, iclass 37, count 2 2006.285.07:41:01.38#ibcon#read 6, iclass 37, count 2 2006.285.07:41:01.38#ibcon#end of sib2, iclass 37, count 2 2006.285.07:41:01.38#ibcon#*after write, iclass 37, count 2 2006.285.07:41:01.38#ibcon#*before return 0, iclass 37, count 2 2006.285.07:41:01.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:41:01.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:41:01.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.07:41:01.38#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:01.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:41:01.39#abcon#{5=INTERFACE CLEAR} 2006.285.07:41:01.45#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:41:01.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:41:01.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:41:01.50#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:41:01.50#ibcon#first serial, iclass 37, count 0 2006.285.07:41:01.50#ibcon#enter sib2, iclass 37, count 0 2006.285.07:41:01.50#ibcon#flushed, iclass 37, count 0 2006.285.07:41:01.50#ibcon#about to write, iclass 37, count 0 2006.285.07:41:01.50#ibcon#wrote, iclass 37, count 0 2006.285.07:41:01.50#ibcon#about to read 3, iclass 37, count 0 2006.285.07:41:01.52#ibcon#read 3, iclass 37, count 0 2006.285.07:41:01.52#ibcon#about to read 4, iclass 37, count 0 2006.285.07:41:01.52#ibcon#read 4, iclass 37, count 0 2006.285.07:41:01.52#ibcon#about to read 5, iclass 37, count 0 2006.285.07:41:01.52#ibcon#read 5, iclass 37, count 0 2006.285.07:41:01.52#ibcon#about to read 6, iclass 37, count 0 2006.285.07:41:01.52#ibcon#read 6, iclass 37, count 0 2006.285.07:41:01.52#ibcon#end of sib2, iclass 37, count 0 2006.285.07:41:01.52#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:41:01.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:41:01.52#ibcon#[25=USB\r\n] 2006.285.07:41:01.52#ibcon#*before write, iclass 37, count 0 2006.285.07:41:01.52#ibcon#enter sib2, iclass 37, count 0 2006.285.07:41:01.52#ibcon#flushed, iclass 37, count 0 2006.285.07:41:01.52#ibcon#about to write, iclass 37, count 0 2006.285.07:41:01.52#ibcon#wrote, iclass 37, count 0 2006.285.07:41:01.52#ibcon#about to read 3, iclass 37, count 0 2006.285.07:41:01.55#ibcon#read 3, iclass 37, count 0 2006.285.07:41:01.55#ibcon#about to read 4, iclass 37, count 0 2006.285.07:41:01.55#ibcon#read 4, iclass 37, count 0 2006.285.07:41:01.55#ibcon#about to read 5, iclass 37, count 0 2006.285.07:41:01.55#ibcon#read 5, iclass 37, count 0 2006.285.07:41:01.55#ibcon#about to read 6, iclass 37, count 0 2006.285.07:41:01.55#ibcon#read 6, iclass 37, count 0 2006.285.07:41:01.55#ibcon#end of sib2, iclass 37, count 0 2006.285.07:41:01.55#ibcon#*after write, iclass 37, count 0 2006.285.07:41:01.55#ibcon#*before return 0, iclass 37, count 0 2006.285.07:41:01.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:41:01.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:41:01.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:41:01.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:41:01.55$vck44/valo=3,564.99 2006.285.07:41:01.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.07:41:01.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.07:41:01.55#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:01.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:41:01.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:41:01.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:41:01.55#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:41:01.55#ibcon#first serial, iclass 5, count 0 2006.285.07:41:01.55#ibcon#enter sib2, iclass 5, count 0 2006.285.07:41:01.55#ibcon#flushed, iclass 5, count 0 2006.285.07:41:01.55#ibcon#about to write, iclass 5, count 0 2006.285.07:41:01.55#ibcon#wrote, iclass 5, count 0 2006.285.07:41:01.55#ibcon#about to read 3, iclass 5, count 0 2006.285.07:41:01.57#ibcon#read 3, iclass 5, count 0 2006.285.07:41:01.57#ibcon#about to read 4, iclass 5, count 0 2006.285.07:41:01.57#ibcon#read 4, iclass 5, count 0 2006.285.07:41:01.57#ibcon#about to read 5, iclass 5, count 0 2006.285.07:41:01.57#ibcon#read 5, iclass 5, count 0 2006.285.07:41:01.57#ibcon#about to read 6, iclass 5, count 0 2006.285.07:41:01.57#ibcon#read 6, iclass 5, count 0 2006.285.07:41:01.57#ibcon#end of sib2, iclass 5, count 0 2006.285.07:41:01.57#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:41:01.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:41:01.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:41:01.57#ibcon#*before write, iclass 5, count 0 2006.285.07:41:01.57#ibcon#enter sib2, iclass 5, count 0 2006.285.07:41:01.57#ibcon#flushed, iclass 5, count 0 2006.285.07:41:01.57#ibcon#about to write, iclass 5, count 0 2006.285.07:41:01.57#ibcon#wrote, iclass 5, count 0 2006.285.07:41:01.57#ibcon#about to read 3, iclass 5, count 0 2006.285.07:41:01.61#ibcon#read 3, iclass 5, count 0 2006.285.07:41:01.61#ibcon#about to read 4, iclass 5, count 0 2006.285.07:41:01.61#ibcon#read 4, iclass 5, count 0 2006.285.07:41:01.61#ibcon#about to read 5, iclass 5, count 0 2006.285.07:41:01.61#ibcon#read 5, iclass 5, count 0 2006.285.07:41:01.61#ibcon#about to read 6, iclass 5, count 0 2006.285.07:41:01.61#ibcon#read 6, iclass 5, count 0 2006.285.07:41:01.61#ibcon#end of sib2, iclass 5, count 0 2006.285.07:41:01.61#ibcon#*after write, iclass 5, count 0 2006.285.07:41:01.61#ibcon#*before return 0, iclass 5, count 0 2006.285.07:41:01.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:41:01.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:41:01.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:41:01.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:41:01.61$vck44/va=3,7 2006.285.07:41:01.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.07:41:01.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.07:41:01.61#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:01.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:41:01.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:41:01.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:41:01.67#ibcon#enter wrdev, iclass 7, count 2 2006.285.07:41:01.67#ibcon#first serial, iclass 7, count 2 2006.285.07:41:01.67#ibcon#enter sib2, iclass 7, count 2 2006.285.07:41:01.67#ibcon#flushed, iclass 7, count 2 2006.285.07:41:01.67#ibcon#about to write, iclass 7, count 2 2006.285.07:41:01.67#ibcon#wrote, iclass 7, count 2 2006.285.07:41:01.67#ibcon#about to read 3, iclass 7, count 2 2006.285.07:41:01.69#ibcon#read 3, iclass 7, count 2 2006.285.07:41:01.69#ibcon#about to read 4, iclass 7, count 2 2006.285.07:41:01.69#ibcon#read 4, iclass 7, count 2 2006.285.07:41:01.69#ibcon#about to read 5, iclass 7, count 2 2006.285.07:41:01.69#ibcon#read 5, iclass 7, count 2 2006.285.07:41:01.69#ibcon#about to read 6, iclass 7, count 2 2006.285.07:41:01.69#ibcon#read 6, iclass 7, count 2 2006.285.07:41:01.69#ibcon#end of sib2, iclass 7, count 2 2006.285.07:41:01.69#ibcon#*mode == 0, iclass 7, count 2 2006.285.07:41:01.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.07:41:01.69#ibcon#[25=AT03-07\r\n] 2006.285.07:41:01.69#ibcon#*before write, iclass 7, count 2 2006.285.07:41:01.69#ibcon#enter sib2, iclass 7, count 2 2006.285.07:41:01.69#ibcon#flushed, iclass 7, count 2 2006.285.07:41:01.69#ibcon#about to write, iclass 7, count 2 2006.285.07:41:01.69#ibcon#wrote, iclass 7, count 2 2006.285.07:41:01.69#ibcon#about to read 3, iclass 7, count 2 2006.285.07:41:01.72#ibcon#read 3, iclass 7, count 2 2006.285.07:41:01.72#ibcon#about to read 4, iclass 7, count 2 2006.285.07:41:01.72#ibcon#read 4, iclass 7, count 2 2006.285.07:41:01.72#ibcon#about to read 5, iclass 7, count 2 2006.285.07:41:01.72#ibcon#read 5, iclass 7, count 2 2006.285.07:41:01.72#ibcon#about to read 6, iclass 7, count 2 2006.285.07:41:01.72#ibcon#read 6, iclass 7, count 2 2006.285.07:41:01.72#ibcon#end of sib2, iclass 7, count 2 2006.285.07:41:01.72#ibcon#*after write, iclass 7, count 2 2006.285.07:41:01.72#ibcon#*before return 0, iclass 7, count 2 2006.285.07:41:01.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:41:01.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:41:01.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.07:41:01.72#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:01.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:41:01.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:41:01.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:41:01.84#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:41:01.84#ibcon#first serial, iclass 7, count 0 2006.285.07:41:01.84#ibcon#enter sib2, iclass 7, count 0 2006.285.07:41:01.84#ibcon#flushed, iclass 7, count 0 2006.285.07:41:01.84#ibcon#about to write, iclass 7, count 0 2006.285.07:41:01.84#ibcon#wrote, iclass 7, count 0 2006.285.07:41:01.84#ibcon#about to read 3, iclass 7, count 0 2006.285.07:41:01.86#ibcon#read 3, iclass 7, count 0 2006.285.07:41:01.86#ibcon#about to read 4, iclass 7, count 0 2006.285.07:41:01.86#ibcon#read 4, iclass 7, count 0 2006.285.07:41:01.86#ibcon#about to read 5, iclass 7, count 0 2006.285.07:41:01.86#ibcon#read 5, iclass 7, count 0 2006.285.07:41:01.86#ibcon#about to read 6, iclass 7, count 0 2006.285.07:41:01.86#ibcon#read 6, iclass 7, count 0 2006.285.07:41:01.86#ibcon#end of sib2, iclass 7, count 0 2006.285.07:41:01.86#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:41:01.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:41:01.86#ibcon#[25=USB\r\n] 2006.285.07:41:01.86#ibcon#*before write, iclass 7, count 0 2006.285.07:41:01.86#ibcon#enter sib2, iclass 7, count 0 2006.285.07:41:01.86#ibcon#flushed, iclass 7, count 0 2006.285.07:41:01.86#ibcon#about to write, iclass 7, count 0 2006.285.07:41:01.86#ibcon#wrote, iclass 7, count 0 2006.285.07:41:01.86#ibcon#about to read 3, iclass 7, count 0 2006.285.07:41:01.89#ibcon#read 3, iclass 7, count 0 2006.285.07:41:01.89#ibcon#about to read 4, iclass 7, count 0 2006.285.07:41:01.89#ibcon#read 4, iclass 7, count 0 2006.285.07:41:01.89#ibcon#about to read 5, iclass 7, count 0 2006.285.07:41:01.89#ibcon#read 5, iclass 7, count 0 2006.285.07:41:01.89#ibcon#about to read 6, iclass 7, count 0 2006.285.07:41:01.89#ibcon#read 6, iclass 7, count 0 2006.285.07:41:01.89#ibcon#end of sib2, iclass 7, count 0 2006.285.07:41:01.89#ibcon#*after write, iclass 7, count 0 2006.285.07:41:01.89#ibcon#*before return 0, iclass 7, count 0 2006.285.07:41:01.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:41:01.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:41:01.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:41:01.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:41:01.89$vck44/valo=4,624.99 2006.285.07:41:01.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.07:41:01.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.07:41:01.89#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:01.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:41:01.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:41:01.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:41:01.89#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:41:01.89#ibcon#first serial, iclass 11, count 0 2006.285.07:41:01.89#ibcon#enter sib2, iclass 11, count 0 2006.285.07:41:01.89#ibcon#flushed, iclass 11, count 0 2006.285.07:41:01.89#ibcon#about to write, iclass 11, count 0 2006.285.07:41:01.89#ibcon#wrote, iclass 11, count 0 2006.285.07:41:01.89#ibcon#about to read 3, iclass 11, count 0 2006.285.07:41:01.91#ibcon#read 3, iclass 11, count 0 2006.285.07:41:01.91#ibcon#about to read 4, iclass 11, count 0 2006.285.07:41:01.91#ibcon#read 4, iclass 11, count 0 2006.285.07:41:01.91#ibcon#about to read 5, iclass 11, count 0 2006.285.07:41:01.91#ibcon#read 5, iclass 11, count 0 2006.285.07:41:01.91#ibcon#about to read 6, iclass 11, count 0 2006.285.07:41:01.91#ibcon#read 6, iclass 11, count 0 2006.285.07:41:01.91#ibcon#end of sib2, iclass 11, count 0 2006.285.07:41:01.91#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:41:01.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:41:01.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:41:01.91#ibcon#*before write, iclass 11, count 0 2006.285.07:41:01.91#ibcon#enter sib2, iclass 11, count 0 2006.285.07:41:01.91#ibcon#flushed, iclass 11, count 0 2006.285.07:41:01.91#ibcon#about to write, iclass 11, count 0 2006.285.07:41:01.91#ibcon#wrote, iclass 11, count 0 2006.285.07:41:01.91#ibcon#about to read 3, iclass 11, count 0 2006.285.07:41:01.95#ibcon#read 3, iclass 11, count 0 2006.285.07:41:01.95#ibcon#about to read 4, iclass 11, count 0 2006.285.07:41:01.95#ibcon#read 4, iclass 11, count 0 2006.285.07:41:01.95#ibcon#about to read 5, iclass 11, count 0 2006.285.07:41:01.95#ibcon#read 5, iclass 11, count 0 2006.285.07:41:01.95#ibcon#about to read 6, iclass 11, count 0 2006.285.07:41:01.95#ibcon#read 6, iclass 11, count 0 2006.285.07:41:01.95#ibcon#end of sib2, iclass 11, count 0 2006.285.07:41:01.95#ibcon#*after write, iclass 11, count 0 2006.285.07:41:01.95#ibcon#*before return 0, iclass 11, count 0 2006.285.07:41:01.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:41:01.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:41:01.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:41:01.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:41:01.95$vck44/va=4,6 2006.285.07:41:01.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.07:41:01.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.07:41:01.95#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:01.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:41:02.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:41:02.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:41:02.01#ibcon#enter wrdev, iclass 13, count 2 2006.285.07:41:02.01#ibcon#first serial, iclass 13, count 2 2006.285.07:41:02.01#ibcon#enter sib2, iclass 13, count 2 2006.285.07:41:02.01#ibcon#flushed, iclass 13, count 2 2006.285.07:41:02.01#ibcon#about to write, iclass 13, count 2 2006.285.07:41:02.01#ibcon#wrote, iclass 13, count 2 2006.285.07:41:02.01#ibcon#about to read 3, iclass 13, count 2 2006.285.07:41:02.03#ibcon#read 3, iclass 13, count 2 2006.285.07:41:02.03#ibcon#about to read 4, iclass 13, count 2 2006.285.07:41:02.03#ibcon#read 4, iclass 13, count 2 2006.285.07:41:02.03#ibcon#about to read 5, iclass 13, count 2 2006.285.07:41:02.03#ibcon#read 5, iclass 13, count 2 2006.285.07:41:02.03#ibcon#about to read 6, iclass 13, count 2 2006.285.07:41:02.03#ibcon#read 6, iclass 13, count 2 2006.285.07:41:02.03#ibcon#end of sib2, iclass 13, count 2 2006.285.07:41:02.03#ibcon#*mode == 0, iclass 13, count 2 2006.285.07:41:02.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.07:41:02.03#ibcon#[25=AT04-06\r\n] 2006.285.07:41:02.03#ibcon#*before write, iclass 13, count 2 2006.285.07:41:02.03#ibcon#enter sib2, iclass 13, count 2 2006.285.07:41:02.03#ibcon#flushed, iclass 13, count 2 2006.285.07:41:02.03#ibcon#about to write, iclass 13, count 2 2006.285.07:41:02.03#ibcon#wrote, iclass 13, count 2 2006.285.07:41:02.03#ibcon#about to read 3, iclass 13, count 2 2006.285.07:41:02.06#ibcon#read 3, iclass 13, count 2 2006.285.07:41:02.06#ibcon#about to read 4, iclass 13, count 2 2006.285.07:41:02.06#ibcon#read 4, iclass 13, count 2 2006.285.07:41:02.06#ibcon#about to read 5, iclass 13, count 2 2006.285.07:41:02.06#ibcon#read 5, iclass 13, count 2 2006.285.07:41:02.06#ibcon#about to read 6, iclass 13, count 2 2006.285.07:41:02.06#ibcon#read 6, iclass 13, count 2 2006.285.07:41:02.06#ibcon#end of sib2, iclass 13, count 2 2006.285.07:41:02.06#ibcon#*after write, iclass 13, count 2 2006.285.07:41:02.06#ibcon#*before return 0, iclass 13, count 2 2006.285.07:41:02.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:41:02.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:41:02.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.07:41:02.06#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:02.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:41:02.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:41:02.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:41:02.18#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:41:02.18#ibcon#first serial, iclass 13, count 0 2006.285.07:41:02.18#ibcon#enter sib2, iclass 13, count 0 2006.285.07:41:02.18#ibcon#flushed, iclass 13, count 0 2006.285.07:41:02.18#ibcon#about to write, iclass 13, count 0 2006.285.07:41:02.18#ibcon#wrote, iclass 13, count 0 2006.285.07:41:02.18#ibcon#about to read 3, iclass 13, count 0 2006.285.07:41:02.20#ibcon#read 3, iclass 13, count 0 2006.285.07:41:02.20#ibcon#about to read 4, iclass 13, count 0 2006.285.07:41:02.20#ibcon#read 4, iclass 13, count 0 2006.285.07:41:02.20#ibcon#about to read 5, iclass 13, count 0 2006.285.07:41:02.20#ibcon#read 5, iclass 13, count 0 2006.285.07:41:02.20#ibcon#about to read 6, iclass 13, count 0 2006.285.07:41:02.20#ibcon#read 6, iclass 13, count 0 2006.285.07:41:02.20#ibcon#end of sib2, iclass 13, count 0 2006.285.07:41:02.20#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:41:02.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:41:02.20#ibcon#[25=USB\r\n] 2006.285.07:41:02.20#ibcon#*before write, iclass 13, count 0 2006.285.07:41:02.20#ibcon#enter sib2, iclass 13, count 0 2006.285.07:41:02.20#ibcon#flushed, iclass 13, count 0 2006.285.07:41:02.20#ibcon#about to write, iclass 13, count 0 2006.285.07:41:02.20#ibcon#wrote, iclass 13, count 0 2006.285.07:41:02.20#ibcon#about to read 3, iclass 13, count 0 2006.285.07:41:02.23#ibcon#read 3, iclass 13, count 0 2006.285.07:41:02.23#ibcon#about to read 4, iclass 13, count 0 2006.285.07:41:02.23#ibcon#read 4, iclass 13, count 0 2006.285.07:41:02.23#ibcon#about to read 5, iclass 13, count 0 2006.285.07:41:02.23#ibcon#read 5, iclass 13, count 0 2006.285.07:41:02.23#ibcon#about to read 6, iclass 13, count 0 2006.285.07:41:02.23#ibcon#read 6, iclass 13, count 0 2006.285.07:41:02.23#ibcon#end of sib2, iclass 13, count 0 2006.285.07:41:02.23#ibcon#*after write, iclass 13, count 0 2006.285.07:41:02.23#ibcon#*before return 0, iclass 13, count 0 2006.285.07:41:02.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:41:02.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:41:02.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:41:02.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:41:02.23$vck44/valo=5,734.99 2006.285.07:41:02.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.07:41:02.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.07:41:02.23#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:02.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:41:02.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:41:02.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:41:02.23#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:41:02.23#ibcon#first serial, iclass 15, count 0 2006.285.07:41:02.23#ibcon#enter sib2, iclass 15, count 0 2006.285.07:41:02.23#ibcon#flushed, iclass 15, count 0 2006.285.07:41:02.23#ibcon#about to write, iclass 15, count 0 2006.285.07:41:02.23#ibcon#wrote, iclass 15, count 0 2006.285.07:41:02.23#ibcon#about to read 3, iclass 15, count 0 2006.285.07:41:02.25#ibcon#read 3, iclass 15, count 0 2006.285.07:41:02.25#ibcon#about to read 4, iclass 15, count 0 2006.285.07:41:02.25#ibcon#read 4, iclass 15, count 0 2006.285.07:41:02.25#ibcon#about to read 5, iclass 15, count 0 2006.285.07:41:02.25#ibcon#read 5, iclass 15, count 0 2006.285.07:41:02.25#ibcon#about to read 6, iclass 15, count 0 2006.285.07:41:02.25#ibcon#read 6, iclass 15, count 0 2006.285.07:41:02.25#ibcon#end of sib2, iclass 15, count 0 2006.285.07:41:02.25#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:41:02.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:41:02.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:41:02.25#ibcon#*before write, iclass 15, count 0 2006.285.07:41:02.25#ibcon#enter sib2, iclass 15, count 0 2006.285.07:41:02.25#ibcon#flushed, iclass 15, count 0 2006.285.07:41:02.25#ibcon#about to write, iclass 15, count 0 2006.285.07:41:02.25#ibcon#wrote, iclass 15, count 0 2006.285.07:41:02.25#ibcon#about to read 3, iclass 15, count 0 2006.285.07:41:02.29#ibcon#read 3, iclass 15, count 0 2006.285.07:41:02.29#ibcon#about to read 4, iclass 15, count 0 2006.285.07:41:02.29#ibcon#read 4, iclass 15, count 0 2006.285.07:41:02.29#ibcon#about to read 5, iclass 15, count 0 2006.285.07:41:02.29#ibcon#read 5, iclass 15, count 0 2006.285.07:41:02.29#ibcon#about to read 6, iclass 15, count 0 2006.285.07:41:02.29#ibcon#read 6, iclass 15, count 0 2006.285.07:41:02.29#ibcon#end of sib2, iclass 15, count 0 2006.285.07:41:02.29#ibcon#*after write, iclass 15, count 0 2006.285.07:41:02.29#ibcon#*before return 0, iclass 15, count 0 2006.285.07:41:02.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:41:02.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:41:02.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:41:02.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:41:02.29$vck44/va=5,3 2006.285.07:41:02.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.07:41:02.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.07:41:02.29#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:02.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:41:02.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:41:02.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:41:02.35#ibcon#enter wrdev, iclass 17, count 2 2006.285.07:41:02.35#ibcon#first serial, iclass 17, count 2 2006.285.07:41:02.35#ibcon#enter sib2, iclass 17, count 2 2006.285.07:41:02.35#ibcon#flushed, iclass 17, count 2 2006.285.07:41:02.35#ibcon#about to write, iclass 17, count 2 2006.285.07:41:02.35#ibcon#wrote, iclass 17, count 2 2006.285.07:41:02.35#ibcon#about to read 3, iclass 17, count 2 2006.285.07:41:02.37#ibcon#read 3, iclass 17, count 2 2006.285.07:41:02.37#ibcon#about to read 4, iclass 17, count 2 2006.285.07:41:02.37#ibcon#read 4, iclass 17, count 2 2006.285.07:41:02.37#ibcon#about to read 5, iclass 17, count 2 2006.285.07:41:02.37#ibcon#read 5, iclass 17, count 2 2006.285.07:41:02.37#ibcon#about to read 6, iclass 17, count 2 2006.285.07:41:02.37#ibcon#read 6, iclass 17, count 2 2006.285.07:41:02.37#ibcon#end of sib2, iclass 17, count 2 2006.285.07:41:02.37#ibcon#*mode == 0, iclass 17, count 2 2006.285.07:41:02.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.07:41:02.37#ibcon#[25=AT05-03\r\n] 2006.285.07:41:02.37#ibcon#*before write, iclass 17, count 2 2006.285.07:41:02.37#ibcon#enter sib2, iclass 17, count 2 2006.285.07:41:02.37#ibcon#flushed, iclass 17, count 2 2006.285.07:41:02.37#ibcon#about to write, iclass 17, count 2 2006.285.07:41:02.37#ibcon#wrote, iclass 17, count 2 2006.285.07:41:02.37#ibcon#about to read 3, iclass 17, count 2 2006.285.07:41:02.40#ibcon#read 3, iclass 17, count 2 2006.285.07:41:02.40#ibcon#about to read 4, iclass 17, count 2 2006.285.07:41:02.40#ibcon#read 4, iclass 17, count 2 2006.285.07:41:02.40#ibcon#about to read 5, iclass 17, count 2 2006.285.07:41:02.40#ibcon#read 5, iclass 17, count 2 2006.285.07:41:02.40#ibcon#about to read 6, iclass 17, count 2 2006.285.07:41:02.40#ibcon#read 6, iclass 17, count 2 2006.285.07:41:02.40#ibcon#end of sib2, iclass 17, count 2 2006.285.07:41:02.40#ibcon#*after write, iclass 17, count 2 2006.285.07:41:02.40#ibcon#*before return 0, iclass 17, count 2 2006.285.07:41:02.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:41:02.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:41:02.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.07:41:02.40#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:02.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:41:02.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:41:02.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:41:02.52#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:41:02.52#ibcon#first serial, iclass 17, count 0 2006.285.07:41:02.52#ibcon#enter sib2, iclass 17, count 0 2006.285.07:41:02.52#ibcon#flushed, iclass 17, count 0 2006.285.07:41:02.52#ibcon#about to write, iclass 17, count 0 2006.285.07:41:02.52#ibcon#wrote, iclass 17, count 0 2006.285.07:41:02.52#ibcon#about to read 3, iclass 17, count 0 2006.285.07:41:02.54#ibcon#read 3, iclass 17, count 0 2006.285.07:41:02.54#ibcon#about to read 4, iclass 17, count 0 2006.285.07:41:02.54#ibcon#read 4, iclass 17, count 0 2006.285.07:41:02.54#ibcon#about to read 5, iclass 17, count 0 2006.285.07:41:02.54#ibcon#read 5, iclass 17, count 0 2006.285.07:41:02.54#ibcon#about to read 6, iclass 17, count 0 2006.285.07:41:02.54#ibcon#read 6, iclass 17, count 0 2006.285.07:41:02.54#ibcon#end of sib2, iclass 17, count 0 2006.285.07:41:02.54#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:41:02.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:41:02.54#ibcon#[25=USB\r\n] 2006.285.07:41:02.54#ibcon#*before write, iclass 17, count 0 2006.285.07:41:02.54#ibcon#enter sib2, iclass 17, count 0 2006.285.07:41:02.54#ibcon#flushed, iclass 17, count 0 2006.285.07:41:02.54#ibcon#about to write, iclass 17, count 0 2006.285.07:41:02.54#ibcon#wrote, iclass 17, count 0 2006.285.07:41:02.54#ibcon#about to read 3, iclass 17, count 0 2006.285.07:41:02.57#ibcon#read 3, iclass 17, count 0 2006.285.07:41:02.57#ibcon#about to read 4, iclass 17, count 0 2006.285.07:41:02.57#ibcon#read 4, iclass 17, count 0 2006.285.07:41:02.57#ibcon#about to read 5, iclass 17, count 0 2006.285.07:41:02.57#ibcon#read 5, iclass 17, count 0 2006.285.07:41:02.57#ibcon#about to read 6, iclass 17, count 0 2006.285.07:41:02.57#ibcon#read 6, iclass 17, count 0 2006.285.07:41:02.57#ibcon#end of sib2, iclass 17, count 0 2006.285.07:41:02.57#ibcon#*after write, iclass 17, count 0 2006.285.07:41:02.57#ibcon#*before return 0, iclass 17, count 0 2006.285.07:41:02.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:41:02.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:41:02.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:41:02.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:41:02.57$vck44/valo=6,814.99 2006.285.07:41:02.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.07:41:02.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.07:41:02.57#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:02.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:41:02.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:41:02.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:41:02.57#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:41:02.57#ibcon#first serial, iclass 19, count 0 2006.285.07:41:02.57#ibcon#enter sib2, iclass 19, count 0 2006.285.07:41:02.57#ibcon#flushed, iclass 19, count 0 2006.285.07:41:02.57#ibcon#about to write, iclass 19, count 0 2006.285.07:41:02.57#ibcon#wrote, iclass 19, count 0 2006.285.07:41:02.57#ibcon#about to read 3, iclass 19, count 0 2006.285.07:41:02.59#ibcon#read 3, iclass 19, count 0 2006.285.07:41:02.59#ibcon#about to read 4, iclass 19, count 0 2006.285.07:41:02.59#ibcon#read 4, iclass 19, count 0 2006.285.07:41:02.59#ibcon#about to read 5, iclass 19, count 0 2006.285.07:41:02.59#ibcon#read 5, iclass 19, count 0 2006.285.07:41:02.59#ibcon#about to read 6, iclass 19, count 0 2006.285.07:41:02.59#ibcon#read 6, iclass 19, count 0 2006.285.07:41:02.59#ibcon#end of sib2, iclass 19, count 0 2006.285.07:41:02.59#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:41:02.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:41:02.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:41:02.59#ibcon#*before write, iclass 19, count 0 2006.285.07:41:02.59#ibcon#enter sib2, iclass 19, count 0 2006.285.07:41:02.59#ibcon#flushed, iclass 19, count 0 2006.285.07:41:02.59#ibcon#about to write, iclass 19, count 0 2006.285.07:41:02.59#ibcon#wrote, iclass 19, count 0 2006.285.07:41:02.59#ibcon#about to read 3, iclass 19, count 0 2006.285.07:41:02.63#ibcon#read 3, iclass 19, count 0 2006.285.07:41:02.63#ibcon#about to read 4, iclass 19, count 0 2006.285.07:41:02.63#ibcon#read 4, iclass 19, count 0 2006.285.07:41:02.63#ibcon#about to read 5, iclass 19, count 0 2006.285.07:41:02.63#ibcon#read 5, iclass 19, count 0 2006.285.07:41:02.63#ibcon#about to read 6, iclass 19, count 0 2006.285.07:41:02.63#ibcon#read 6, iclass 19, count 0 2006.285.07:41:02.63#ibcon#end of sib2, iclass 19, count 0 2006.285.07:41:02.63#ibcon#*after write, iclass 19, count 0 2006.285.07:41:02.63#ibcon#*before return 0, iclass 19, count 0 2006.285.07:41:02.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:41:02.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:41:02.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:41:02.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:41:02.63$vck44/va=6,4 2006.285.07:41:02.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.07:41:02.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.07:41:02.63#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:02.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:41:02.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:41:02.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:41:02.69#ibcon#enter wrdev, iclass 21, count 2 2006.285.07:41:02.69#ibcon#first serial, iclass 21, count 2 2006.285.07:41:02.69#ibcon#enter sib2, iclass 21, count 2 2006.285.07:41:02.69#ibcon#flushed, iclass 21, count 2 2006.285.07:41:02.69#ibcon#about to write, iclass 21, count 2 2006.285.07:41:02.69#ibcon#wrote, iclass 21, count 2 2006.285.07:41:02.69#ibcon#about to read 3, iclass 21, count 2 2006.285.07:41:02.71#ibcon#read 3, iclass 21, count 2 2006.285.07:41:02.71#ibcon#about to read 4, iclass 21, count 2 2006.285.07:41:02.71#ibcon#read 4, iclass 21, count 2 2006.285.07:41:02.71#ibcon#about to read 5, iclass 21, count 2 2006.285.07:41:02.71#ibcon#read 5, iclass 21, count 2 2006.285.07:41:02.71#ibcon#about to read 6, iclass 21, count 2 2006.285.07:41:02.71#ibcon#read 6, iclass 21, count 2 2006.285.07:41:02.71#ibcon#end of sib2, iclass 21, count 2 2006.285.07:41:02.71#ibcon#*mode == 0, iclass 21, count 2 2006.285.07:41:02.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.07:41:02.71#ibcon#[25=AT06-04\r\n] 2006.285.07:41:02.71#ibcon#*before write, iclass 21, count 2 2006.285.07:41:02.71#ibcon#enter sib2, iclass 21, count 2 2006.285.07:41:02.71#ibcon#flushed, iclass 21, count 2 2006.285.07:41:02.71#ibcon#about to write, iclass 21, count 2 2006.285.07:41:02.71#ibcon#wrote, iclass 21, count 2 2006.285.07:41:02.71#ibcon#about to read 3, iclass 21, count 2 2006.285.07:41:02.74#ibcon#read 3, iclass 21, count 2 2006.285.07:41:02.74#ibcon#about to read 4, iclass 21, count 2 2006.285.07:41:02.74#ibcon#read 4, iclass 21, count 2 2006.285.07:41:02.74#ibcon#about to read 5, iclass 21, count 2 2006.285.07:41:02.74#ibcon#read 5, iclass 21, count 2 2006.285.07:41:02.74#ibcon#about to read 6, iclass 21, count 2 2006.285.07:41:02.74#ibcon#read 6, iclass 21, count 2 2006.285.07:41:02.74#ibcon#end of sib2, iclass 21, count 2 2006.285.07:41:02.74#ibcon#*after write, iclass 21, count 2 2006.285.07:41:02.74#ibcon#*before return 0, iclass 21, count 2 2006.285.07:41:02.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:41:02.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:41:02.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.07:41:02.74#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:02.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:41:02.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:41:02.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:41:02.86#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:41:02.86#ibcon#first serial, iclass 21, count 0 2006.285.07:41:02.86#ibcon#enter sib2, iclass 21, count 0 2006.285.07:41:02.86#ibcon#flushed, iclass 21, count 0 2006.285.07:41:02.86#ibcon#about to write, iclass 21, count 0 2006.285.07:41:02.86#ibcon#wrote, iclass 21, count 0 2006.285.07:41:02.86#ibcon#about to read 3, iclass 21, count 0 2006.285.07:41:02.88#ibcon#read 3, iclass 21, count 0 2006.285.07:41:02.88#ibcon#about to read 4, iclass 21, count 0 2006.285.07:41:02.88#ibcon#read 4, iclass 21, count 0 2006.285.07:41:02.88#ibcon#about to read 5, iclass 21, count 0 2006.285.07:41:02.88#ibcon#read 5, iclass 21, count 0 2006.285.07:41:02.88#ibcon#about to read 6, iclass 21, count 0 2006.285.07:41:02.88#ibcon#read 6, iclass 21, count 0 2006.285.07:41:02.88#ibcon#end of sib2, iclass 21, count 0 2006.285.07:41:02.88#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:41:02.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:41:02.88#ibcon#[25=USB\r\n] 2006.285.07:41:02.88#ibcon#*before write, iclass 21, count 0 2006.285.07:41:02.88#ibcon#enter sib2, iclass 21, count 0 2006.285.07:41:02.88#ibcon#flushed, iclass 21, count 0 2006.285.07:41:02.88#ibcon#about to write, iclass 21, count 0 2006.285.07:41:02.88#ibcon#wrote, iclass 21, count 0 2006.285.07:41:02.88#ibcon#about to read 3, iclass 21, count 0 2006.285.07:41:02.91#ibcon#read 3, iclass 21, count 0 2006.285.07:41:02.91#ibcon#about to read 4, iclass 21, count 0 2006.285.07:41:02.91#ibcon#read 4, iclass 21, count 0 2006.285.07:41:02.91#ibcon#about to read 5, iclass 21, count 0 2006.285.07:41:02.91#ibcon#read 5, iclass 21, count 0 2006.285.07:41:02.91#ibcon#about to read 6, iclass 21, count 0 2006.285.07:41:02.91#ibcon#read 6, iclass 21, count 0 2006.285.07:41:02.91#ibcon#end of sib2, iclass 21, count 0 2006.285.07:41:02.91#ibcon#*after write, iclass 21, count 0 2006.285.07:41:02.91#ibcon#*before return 0, iclass 21, count 0 2006.285.07:41:02.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:41:02.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:41:02.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:41:02.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:41:02.91$vck44/valo=7,864.99 2006.285.07:41:02.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.07:41:02.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.07:41:02.91#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:02.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:41:02.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:41:02.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:41:02.91#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:41:02.91#ibcon#first serial, iclass 23, count 0 2006.285.07:41:02.91#ibcon#enter sib2, iclass 23, count 0 2006.285.07:41:02.91#ibcon#flushed, iclass 23, count 0 2006.285.07:41:02.91#ibcon#about to write, iclass 23, count 0 2006.285.07:41:02.91#ibcon#wrote, iclass 23, count 0 2006.285.07:41:02.91#ibcon#about to read 3, iclass 23, count 0 2006.285.07:41:02.93#ibcon#read 3, iclass 23, count 0 2006.285.07:41:02.93#ibcon#about to read 4, iclass 23, count 0 2006.285.07:41:02.93#ibcon#read 4, iclass 23, count 0 2006.285.07:41:02.93#ibcon#about to read 5, iclass 23, count 0 2006.285.07:41:02.93#ibcon#read 5, iclass 23, count 0 2006.285.07:41:02.93#ibcon#about to read 6, iclass 23, count 0 2006.285.07:41:02.93#ibcon#read 6, iclass 23, count 0 2006.285.07:41:02.93#ibcon#end of sib2, iclass 23, count 0 2006.285.07:41:02.93#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:41:02.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:41:02.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:41:02.93#ibcon#*before write, iclass 23, count 0 2006.285.07:41:02.93#ibcon#enter sib2, iclass 23, count 0 2006.285.07:41:02.93#ibcon#flushed, iclass 23, count 0 2006.285.07:41:02.93#ibcon#about to write, iclass 23, count 0 2006.285.07:41:02.93#ibcon#wrote, iclass 23, count 0 2006.285.07:41:02.93#ibcon#about to read 3, iclass 23, count 0 2006.285.07:41:02.97#ibcon#read 3, iclass 23, count 0 2006.285.07:41:02.97#ibcon#about to read 4, iclass 23, count 0 2006.285.07:41:02.97#ibcon#read 4, iclass 23, count 0 2006.285.07:41:02.97#ibcon#about to read 5, iclass 23, count 0 2006.285.07:41:02.97#ibcon#read 5, iclass 23, count 0 2006.285.07:41:02.97#ibcon#about to read 6, iclass 23, count 0 2006.285.07:41:02.97#ibcon#read 6, iclass 23, count 0 2006.285.07:41:02.97#ibcon#end of sib2, iclass 23, count 0 2006.285.07:41:02.97#ibcon#*after write, iclass 23, count 0 2006.285.07:41:02.97#ibcon#*before return 0, iclass 23, count 0 2006.285.07:41:02.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:41:02.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:41:02.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:41:02.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:41:02.97$vck44/va=7,4 2006.285.07:41:02.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.07:41:02.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.07:41:02.97#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:02.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:41:03.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:41:03.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:41:03.03#ibcon#enter wrdev, iclass 25, count 2 2006.285.07:41:03.03#ibcon#first serial, iclass 25, count 2 2006.285.07:41:03.03#ibcon#enter sib2, iclass 25, count 2 2006.285.07:41:03.03#ibcon#flushed, iclass 25, count 2 2006.285.07:41:03.03#ibcon#about to write, iclass 25, count 2 2006.285.07:41:03.03#ibcon#wrote, iclass 25, count 2 2006.285.07:41:03.03#ibcon#about to read 3, iclass 25, count 2 2006.285.07:41:03.05#ibcon#read 3, iclass 25, count 2 2006.285.07:41:03.05#ibcon#about to read 4, iclass 25, count 2 2006.285.07:41:03.05#ibcon#read 4, iclass 25, count 2 2006.285.07:41:03.05#ibcon#about to read 5, iclass 25, count 2 2006.285.07:41:03.05#ibcon#read 5, iclass 25, count 2 2006.285.07:41:03.05#ibcon#about to read 6, iclass 25, count 2 2006.285.07:41:03.05#ibcon#read 6, iclass 25, count 2 2006.285.07:41:03.05#ibcon#end of sib2, iclass 25, count 2 2006.285.07:41:03.05#ibcon#*mode == 0, iclass 25, count 2 2006.285.07:41:03.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.07:41:03.05#ibcon#[25=AT07-04\r\n] 2006.285.07:41:03.05#ibcon#*before write, iclass 25, count 2 2006.285.07:41:03.05#ibcon#enter sib2, iclass 25, count 2 2006.285.07:41:03.05#ibcon#flushed, iclass 25, count 2 2006.285.07:41:03.05#ibcon#about to write, iclass 25, count 2 2006.285.07:41:03.05#ibcon#wrote, iclass 25, count 2 2006.285.07:41:03.05#ibcon#about to read 3, iclass 25, count 2 2006.285.07:41:03.08#ibcon#read 3, iclass 25, count 2 2006.285.07:41:03.08#ibcon#about to read 4, iclass 25, count 2 2006.285.07:41:03.08#ibcon#read 4, iclass 25, count 2 2006.285.07:41:03.08#ibcon#about to read 5, iclass 25, count 2 2006.285.07:41:03.08#ibcon#read 5, iclass 25, count 2 2006.285.07:41:03.08#ibcon#about to read 6, iclass 25, count 2 2006.285.07:41:03.08#ibcon#read 6, iclass 25, count 2 2006.285.07:41:03.08#ibcon#end of sib2, iclass 25, count 2 2006.285.07:41:03.08#ibcon#*after write, iclass 25, count 2 2006.285.07:41:03.08#ibcon#*before return 0, iclass 25, count 2 2006.285.07:41:03.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:41:03.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:41:03.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.07:41:03.08#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:03.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:41:03.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:41:03.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:41:03.20#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:41:03.20#ibcon#first serial, iclass 25, count 0 2006.285.07:41:03.20#ibcon#enter sib2, iclass 25, count 0 2006.285.07:41:03.20#ibcon#flushed, iclass 25, count 0 2006.285.07:41:03.20#ibcon#about to write, iclass 25, count 0 2006.285.07:41:03.20#ibcon#wrote, iclass 25, count 0 2006.285.07:41:03.20#ibcon#about to read 3, iclass 25, count 0 2006.285.07:41:03.22#ibcon#read 3, iclass 25, count 0 2006.285.07:41:03.22#ibcon#about to read 4, iclass 25, count 0 2006.285.07:41:03.22#ibcon#read 4, iclass 25, count 0 2006.285.07:41:03.22#ibcon#about to read 5, iclass 25, count 0 2006.285.07:41:03.22#ibcon#read 5, iclass 25, count 0 2006.285.07:41:03.22#ibcon#about to read 6, iclass 25, count 0 2006.285.07:41:03.22#ibcon#read 6, iclass 25, count 0 2006.285.07:41:03.22#ibcon#end of sib2, iclass 25, count 0 2006.285.07:41:03.22#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:41:03.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:41:03.22#ibcon#[25=USB\r\n] 2006.285.07:41:03.22#ibcon#*before write, iclass 25, count 0 2006.285.07:41:03.22#ibcon#enter sib2, iclass 25, count 0 2006.285.07:41:03.22#ibcon#flushed, iclass 25, count 0 2006.285.07:41:03.22#ibcon#about to write, iclass 25, count 0 2006.285.07:41:03.22#ibcon#wrote, iclass 25, count 0 2006.285.07:41:03.22#ibcon#about to read 3, iclass 25, count 0 2006.285.07:41:03.25#ibcon#read 3, iclass 25, count 0 2006.285.07:41:03.25#ibcon#about to read 4, iclass 25, count 0 2006.285.07:41:03.25#ibcon#read 4, iclass 25, count 0 2006.285.07:41:03.25#ibcon#about to read 5, iclass 25, count 0 2006.285.07:41:03.25#ibcon#read 5, iclass 25, count 0 2006.285.07:41:03.25#ibcon#about to read 6, iclass 25, count 0 2006.285.07:41:03.25#ibcon#read 6, iclass 25, count 0 2006.285.07:41:03.25#ibcon#end of sib2, iclass 25, count 0 2006.285.07:41:03.25#ibcon#*after write, iclass 25, count 0 2006.285.07:41:03.25#ibcon#*before return 0, iclass 25, count 0 2006.285.07:41:03.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:41:03.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:41:03.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:41:03.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:41:03.25$vck44/valo=8,884.99 2006.285.07:41:03.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.07:41:03.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.07:41:03.25#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:03.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:41:03.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:41:03.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:41:03.25#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:41:03.25#ibcon#first serial, iclass 27, count 0 2006.285.07:41:03.25#ibcon#enter sib2, iclass 27, count 0 2006.285.07:41:03.25#ibcon#flushed, iclass 27, count 0 2006.285.07:41:03.25#ibcon#about to write, iclass 27, count 0 2006.285.07:41:03.25#ibcon#wrote, iclass 27, count 0 2006.285.07:41:03.25#ibcon#about to read 3, iclass 27, count 0 2006.285.07:41:03.27#ibcon#read 3, iclass 27, count 0 2006.285.07:41:03.27#ibcon#about to read 4, iclass 27, count 0 2006.285.07:41:03.27#ibcon#read 4, iclass 27, count 0 2006.285.07:41:03.27#ibcon#about to read 5, iclass 27, count 0 2006.285.07:41:03.27#ibcon#read 5, iclass 27, count 0 2006.285.07:41:03.27#ibcon#about to read 6, iclass 27, count 0 2006.285.07:41:03.27#ibcon#read 6, iclass 27, count 0 2006.285.07:41:03.27#ibcon#end of sib2, iclass 27, count 0 2006.285.07:41:03.27#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:41:03.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:41:03.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:41:03.27#ibcon#*before write, iclass 27, count 0 2006.285.07:41:03.27#ibcon#enter sib2, iclass 27, count 0 2006.285.07:41:03.27#ibcon#flushed, iclass 27, count 0 2006.285.07:41:03.27#ibcon#about to write, iclass 27, count 0 2006.285.07:41:03.27#ibcon#wrote, iclass 27, count 0 2006.285.07:41:03.27#ibcon#about to read 3, iclass 27, count 0 2006.285.07:41:03.31#ibcon#read 3, iclass 27, count 0 2006.285.07:41:03.31#ibcon#about to read 4, iclass 27, count 0 2006.285.07:41:03.31#ibcon#read 4, iclass 27, count 0 2006.285.07:41:03.31#ibcon#about to read 5, iclass 27, count 0 2006.285.07:41:03.31#ibcon#read 5, iclass 27, count 0 2006.285.07:41:03.31#ibcon#about to read 6, iclass 27, count 0 2006.285.07:41:03.31#ibcon#read 6, iclass 27, count 0 2006.285.07:41:03.31#ibcon#end of sib2, iclass 27, count 0 2006.285.07:41:03.31#ibcon#*after write, iclass 27, count 0 2006.285.07:41:03.31#ibcon#*before return 0, iclass 27, count 0 2006.285.07:41:03.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:41:03.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:41:03.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:41:03.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:41:03.31$vck44/va=8,3 2006.285.07:41:03.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.07:41:03.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.07:41:03.31#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:03.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:41:03.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:41:03.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:41:03.37#ibcon#enter wrdev, iclass 29, count 2 2006.285.07:41:03.37#ibcon#first serial, iclass 29, count 2 2006.285.07:41:03.37#ibcon#enter sib2, iclass 29, count 2 2006.285.07:41:03.37#ibcon#flushed, iclass 29, count 2 2006.285.07:41:03.37#ibcon#about to write, iclass 29, count 2 2006.285.07:41:03.37#ibcon#wrote, iclass 29, count 2 2006.285.07:41:03.37#ibcon#about to read 3, iclass 29, count 2 2006.285.07:41:03.39#ibcon#read 3, iclass 29, count 2 2006.285.07:41:03.39#ibcon#about to read 4, iclass 29, count 2 2006.285.07:41:03.39#ibcon#read 4, iclass 29, count 2 2006.285.07:41:03.39#ibcon#about to read 5, iclass 29, count 2 2006.285.07:41:03.39#ibcon#read 5, iclass 29, count 2 2006.285.07:41:03.39#ibcon#about to read 6, iclass 29, count 2 2006.285.07:41:03.39#ibcon#read 6, iclass 29, count 2 2006.285.07:41:03.39#ibcon#end of sib2, iclass 29, count 2 2006.285.07:41:03.39#ibcon#*mode == 0, iclass 29, count 2 2006.285.07:41:03.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.07:41:03.39#ibcon#[25=AT08-03\r\n] 2006.285.07:41:03.39#ibcon#*before write, iclass 29, count 2 2006.285.07:41:03.39#ibcon#enter sib2, iclass 29, count 2 2006.285.07:41:03.39#ibcon#flushed, iclass 29, count 2 2006.285.07:41:03.39#ibcon#about to write, iclass 29, count 2 2006.285.07:41:03.39#ibcon#wrote, iclass 29, count 2 2006.285.07:41:03.39#ibcon#about to read 3, iclass 29, count 2 2006.285.07:41:03.42#ibcon#read 3, iclass 29, count 2 2006.285.07:41:03.42#ibcon#about to read 4, iclass 29, count 2 2006.285.07:41:03.42#ibcon#read 4, iclass 29, count 2 2006.285.07:41:03.42#ibcon#about to read 5, iclass 29, count 2 2006.285.07:41:03.42#ibcon#read 5, iclass 29, count 2 2006.285.07:41:03.42#ibcon#about to read 6, iclass 29, count 2 2006.285.07:41:03.42#ibcon#read 6, iclass 29, count 2 2006.285.07:41:03.42#ibcon#end of sib2, iclass 29, count 2 2006.285.07:41:03.42#ibcon#*after write, iclass 29, count 2 2006.285.07:41:03.42#ibcon#*before return 0, iclass 29, count 2 2006.285.07:41:03.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:41:03.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:41:03.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.07:41:03.42#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:03.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:41:03.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:41:03.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:41:03.54#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:41:03.54#ibcon#first serial, iclass 29, count 0 2006.285.07:41:03.54#ibcon#enter sib2, iclass 29, count 0 2006.285.07:41:03.54#ibcon#flushed, iclass 29, count 0 2006.285.07:41:03.54#ibcon#about to write, iclass 29, count 0 2006.285.07:41:03.54#ibcon#wrote, iclass 29, count 0 2006.285.07:41:03.54#ibcon#about to read 3, iclass 29, count 0 2006.285.07:41:03.56#ibcon#read 3, iclass 29, count 0 2006.285.07:41:03.56#ibcon#about to read 4, iclass 29, count 0 2006.285.07:41:03.56#ibcon#read 4, iclass 29, count 0 2006.285.07:41:03.56#ibcon#about to read 5, iclass 29, count 0 2006.285.07:41:03.56#ibcon#read 5, iclass 29, count 0 2006.285.07:41:03.56#ibcon#about to read 6, iclass 29, count 0 2006.285.07:41:03.56#ibcon#read 6, iclass 29, count 0 2006.285.07:41:03.56#ibcon#end of sib2, iclass 29, count 0 2006.285.07:41:03.56#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:41:03.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:41:03.56#ibcon#[25=USB\r\n] 2006.285.07:41:03.56#ibcon#*before write, iclass 29, count 0 2006.285.07:41:03.56#ibcon#enter sib2, iclass 29, count 0 2006.285.07:41:03.56#ibcon#flushed, iclass 29, count 0 2006.285.07:41:03.56#ibcon#about to write, iclass 29, count 0 2006.285.07:41:03.56#ibcon#wrote, iclass 29, count 0 2006.285.07:41:03.56#ibcon#about to read 3, iclass 29, count 0 2006.285.07:41:03.59#ibcon#read 3, iclass 29, count 0 2006.285.07:41:03.59#ibcon#about to read 4, iclass 29, count 0 2006.285.07:41:03.59#ibcon#read 4, iclass 29, count 0 2006.285.07:41:03.59#ibcon#about to read 5, iclass 29, count 0 2006.285.07:41:03.59#ibcon#read 5, iclass 29, count 0 2006.285.07:41:03.59#ibcon#about to read 6, iclass 29, count 0 2006.285.07:41:03.59#ibcon#read 6, iclass 29, count 0 2006.285.07:41:03.59#ibcon#end of sib2, iclass 29, count 0 2006.285.07:41:03.59#ibcon#*after write, iclass 29, count 0 2006.285.07:41:03.59#ibcon#*before return 0, iclass 29, count 0 2006.285.07:41:03.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:41:03.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:41:03.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:41:03.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:41:03.59$vck44/vblo=1,629.99 2006.285.07:41:03.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.07:41:03.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.07:41:03.59#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:03.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:41:03.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:41:03.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:41:03.59#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:41:03.59#ibcon#first serial, iclass 31, count 0 2006.285.07:41:03.59#ibcon#enter sib2, iclass 31, count 0 2006.285.07:41:03.59#ibcon#flushed, iclass 31, count 0 2006.285.07:41:03.59#ibcon#about to write, iclass 31, count 0 2006.285.07:41:03.59#ibcon#wrote, iclass 31, count 0 2006.285.07:41:03.59#ibcon#about to read 3, iclass 31, count 0 2006.285.07:41:03.61#ibcon#read 3, iclass 31, count 0 2006.285.07:41:03.61#ibcon#about to read 4, iclass 31, count 0 2006.285.07:41:03.61#ibcon#read 4, iclass 31, count 0 2006.285.07:41:03.61#ibcon#about to read 5, iclass 31, count 0 2006.285.07:41:03.61#ibcon#read 5, iclass 31, count 0 2006.285.07:41:03.61#ibcon#about to read 6, iclass 31, count 0 2006.285.07:41:03.61#ibcon#read 6, iclass 31, count 0 2006.285.07:41:03.61#ibcon#end of sib2, iclass 31, count 0 2006.285.07:41:03.61#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:41:03.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:41:03.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:41:03.61#ibcon#*before write, iclass 31, count 0 2006.285.07:41:03.61#ibcon#enter sib2, iclass 31, count 0 2006.285.07:41:03.61#ibcon#flushed, iclass 31, count 0 2006.285.07:41:03.61#ibcon#about to write, iclass 31, count 0 2006.285.07:41:03.61#ibcon#wrote, iclass 31, count 0 2006.285.07:41:03.61#ibcon#about to read 3, iclass 31, count 0 2006.285.07:41:03.65#ibcon#read 3, iclass 31, count 0 2006.285.07:41:03.65#ibcon#about to read 4, iclass 31, count 0 2006.285.07:41:03.65#ibcon#read 4, iclass 31, count 0 2006.285.07:41:03.65#ibcon#about to read 5, iclass 31, count 0 2006.285.07:41:03.65#ibcon#read 5, iclass 31, count 0 2006.285.07:41:03.65#ibcon#about to read 6, iclass 31, count 0 2006.285.07:41:03.65#ibcon#read 6, iclass 31, count 0 2006.285.07:41:03.65#ibcon#end of sib2, iclass 31, count 0 2006.285.07:41:03.65#ibcon#*after write, iclass 31, count 0 2006.285.07:41:03.65#ibcon#*before return 0, iclass 31, count 0 2006.285.07:41:03.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:41:03.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:41:03.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:41:03.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:41:03.65$vck44/vb=1,4 2006.285.07:41:03.65#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.07:41:03.65#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.07:41:03.65#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:03.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:41:03.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:41:03.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:41:03.65#ibcon#enter wrdev, iclass 33, count 2 2006.285.07:41:03.65#ibcon#first serial, iclass 33, count 2 2006.285.07:41:03.65#ibcon#enter sib2, iclass 33, count 2 2006.285.07:41:03.65#ibcon#flushed, iclass 33, count 2 2006.285.07:41:03.65#ibcon#about to write, iclass 33, count 2 2006.285.07:41:03.65#ibcon#wrote, iclass 33, count 2 2006.285.07:41:03.65#ibcon#about to read 3, iclass 33, count 2 2006.285.07:41:03.67#ibcon#read 3, iclass 33, count 2 2006.285.07:41:03.67#ibcon#about to read 4, iclass 33, count 2 2006.285.07:41:03.67#ibcon#read 4, iclass 33, count 2 2006.285.07:41:03.67#ibcon#about to read 5, iclass 33, count 2 2006.285.07:41:03.67#ibcon#read 5, iclass 33, count 2 2006.285.07:41:03.67#ibcon#about to read 6, iclass 33, count 2 2006.285.07:41:03.67#ibcon#read 6, iclass 33, count 2 2006.285.07:41:03.67#ibcon#end of sib2, iclass 33, count 2 2006.285.07:41:03.67#ibcon#*mode == 0, iclass 33, count 2 2006.285.07:41:03.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.07:41:03.67#ibcon#[27=AT01-04\r\n] 2006.285.07:41:03.67#ibcon#*before write, iclass 33, count 2 2006.285.07:41:03.67#ibcon#enter sib2, iclass 33, count 2 2006.285.07:41:03.67#ibcon#flushed, iclass 33, count 2 2006.285.07:41:03.67#ibcon#about to write, iclass 33, count 2 2006.285.07:41:03.67#ibcon#wrote, iclass 33, count 2 2006.285.07:41:03.67#ibcon#about to read 3, iclass 33, count 2 2006.285.07:41:03.70#ibcon#read 3, iclass 33, count 2 2006.285.07:41:03.70#ibcon#about to read 4, iclass 33, count 2 2006.285.07:41:03.70#ibcon#read 4, iclass 33, count 2 2006.285.07:41:03.70#ibcon#about to read 5, iclass 33, count 2 2006.285.07:41:03.70#ibcon#read 5, iclass 33, count 2 2006.285.07:41:03.70#ibcon#about to read 6, iclass 33, count 2 2006.285.07:41:03.70#ibcon#read 6, iclass 33, count 2 2006.285.07:41:03.70#ibcon#end of sib2, iclass 33, count 2 2006.285.07:41:03.70#ibcon#*after write, iclass 33, count 2 2006.285.07:41:03.70#ibcon#*before return 0, iclass 33, count 2 2006.285.07:41:03.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:41:03.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:41:03.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.07:41:03.70#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:03.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:41:03.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:41:03.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:41:03.82#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:41:03.82#ibcon#first serial, iclass 33, count 0 2006.285.07:41:03.82#ibcon#enter sib2, iclass 33, count 0 2006.285.07:41:03.82#ibcon#flushed, iclass 33, count 0 2006.285.07:41:03.82#ibcon#about to write, iclass 33, count 0 2006.285.07:41:03.82#ibcon#wrote, iclass 33, count 0 2006.285.07:41:03.82#ibcon#about to read 3, iclass 33, count 0 2006.285.07:41:03.84#ibcon#read 3, iclass 33, count 0 2006.285.07:41:03.84#ibcon#about to read 4, iclass 33, count 0 2006.285.07:41:03.84#ibcon#read 4, iclass 33, count 0 2006.285.07:41:03.84#ibcon#about to read 5, iclass 33, count 0 2006.285.07:41:03.84#ibcon#read 5, iclass 33, count 0 2006.285.07:41:03.84#ibcon#about to read 6, iclass 33, count 0 2006.285.07:41:03.84#ibcon#read 6, iclass 33, count 0 2006.285.07:41:03.84#ibcon#end of sib2, iclass 33, count 0 2006.285.07:41:03.84#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:41:03.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:41:03.84#ibcon#[27=USB\r\n] 2006.285.07:41:03.84#ibcon#*before write, iclass 33, count 0 2006.285.07:41:03.84#ibcon#enter sib2, iclass 33, count 0 2006.285.07:41:03.84#ibcon#flushed, iclass 33, count 0 2006.285.07:41:03.84#ibcon#about to write, iclass 33, count 0 2006.285.07:41:03.84#ibcon#wrote, iclass 33, count 0 2006.285.07:41:03.84#ibcon#about to read 3, iclass 33, count 0 2006.285.07:41:03.87#ibcon#read 3, iclass 33, count 0 2006.285.07:41:03.87#ibcon#about to read 4, iclass 33, count 0 2006.285.07:41:03.87#ibcon#read 4, iclass 33, count 0 2006.285.07:41:03.87#ibcon#about to read 5, iclass 33, count 0 2006.285.07:41:03.87#ibcon#read 5, iclass 33, count 0 2006.285.07:41:03.87#ibcon#about to read 6, iclass 33, count 0 2006.285.07:41:03.87#ibcon#read 6, iclass 33, count 0 2006.285.07:41:03.87#ibcon#end of sib2, iclass 33, count 0 2006.285.07:41:03.87#ibcon#*after write, iclass 33, count 0 2006.285.07:41:03.87#ibcon#*before return 0, iclass 33, count 0 2006.285.07:41:03.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:41:03.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:41:03.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:41:03.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:41:03.87$vck44/vblo=2,634.99 2006.285.07:41:03.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.07:41:03.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.07:41:03.87#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:03.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:41:03.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:41:03.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:41:03.87#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:41:03.87#ibcon#first serial, iclass 35, count 0 2006.285.07:41:03.87#ibcon#enter sib2, iclass 35, count 0 2006.285.07:41:03.87#ibcon#flushed, iclass 35, count 0 2006.285.07:41:03.87#ibcon#about to write, iclass 35, count 0 2006.285.07:41:03.87#ibcon#wrote, iclass 35, count 0 2006.285.07:41:03.87#ibcon#about to read 3, iclass 35, count 0 2006.285.07:41:03.89#ibcon#read 3, iclass 35, count 0 2006.285.07:41:03.89#ibcon#about to read 4, iclass 35, count 0 2006.285.07:41:03.89#ibcon#read 4, iclass 35, count 0 2006.285.07:41:03.89#ibcon#about to read 5, iclass 35, count 0 2006.285.07:41:03.89#ibcon#read 5, iclass 35, count 0 2006.285.07:41:03.89#ibcon#about to read 6, iclass 35, count 0 2006.285.07:41:03.89#ibcon#read 6, iclass 35, count 0 2006.285.07:41:03.89#ibcon#end of sib2, iclass 35, count 0 2006.285.07:41:03.89#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:41:03.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:41:03.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:41:03.89#ibcon#*before write, iclass 35, count 0 2006.285.07:41:03.89#ibcon#enter sib2, iclass 35, count 0 2006.285.07:41:03.89#ibcon#flushed, iclass 35, count 0 2006.285.07:41:03.89#ibcon#about to write, iclass 35, count 0 2006.285.07:41:03.89#ibcon#wrote, iclass 35, count 0 2006.285.07:41:03.89#ibcon#about to read 3, iclass 35, count 0 2006.285.07:41:03.93#ibcon#read 3, iclass 35, count 0 2006.285.07:41:03.93#ibcon#about to read 4, iclass 35, count 0 2006.285.07:41:03.93#ibcon#read 4, iclass 35, count 0 2006.285.07:41:03.93#ibcon#about to read 5, iclass 35, count 0 2006.285.07:41:03.93#ibcon#read 5, iclass 35, count 0 2006.285.07:41:03.93#ibcon#about to read 6, iclass 35, count 0 2006.285.07:41:03.93#ibcon#read 6, iclass 35, count 0 2006.285.07:41:03.93#ibcon#end of sib2, iclass 35, count 0 2006.285.07:41:03.93#ibcon#*after write, iclass 35, count 0 2006.285.07:41:03.93#ibcon#*before return 0, iclass 35, count 0 2006.285.07:41:03.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:41:03.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:41:03.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:41:03.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:41:03.93$vck44/vb=2,5 2006.285.07:41:03.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.07:41:03.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.07:41:03.93#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:03.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:41:03.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:41:03.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:41:03.99#ibcon#enter wrdev, iclass 37, count 2 2006.285.07:41:03.99#ibcon#first serial, iclass 37, count 2 2006.285.07:41:03.99#ibcon#enter sib2, iclass 37, count 2 2006.285.07:41:03.99#ibcon#flushed, iclass 37, count 2 2006.285.07:41:03.99#ibcon#about to write, iclass 37, count 2 2006.285.07:41:03.99#ibcon#wrote, iclass 37, count 2 2006.285.07:41:03.99#ibcon#about to read 3, iclass 37, count 2 2006.285.07:41:04.01#ibcon#read 3, iclass 37, count 2 2006.285.07:41:04.01#ibcon#about to read 4, iclass 37, count 2 2006.285.07:41:04.01#ibcon#read 4, iclass 37, count 2 2006.285.07:41:04.01#ibcon#about to read 5, iclass 37, count 2 2006.285.07:41:04.01#ibcon#read 5, iclass 37, count 2 2006.285.07:41:04.01#ibcon#about to read 6, iclass 37, count 2 2006.285.07:41:04.01#ibcon#read 6, iclass 37, count 2 2006.285.07:41:04.01#ibcon#end of sib2, iclass 37, count 2 2006.285.07:41:04.01#ibcon#*mode == 0, iclass 37, count 2 2006.285.07:41:04.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.07:41:04.01#ibcon#[27=AT02-05\r\n] 2006.285.07:41:04.01#ibcon#*before write, iclass 37, count 2 2006.285.07:41:04.01#ibcon#enter sib2, iclass 37, count 2 2006.285.07:41:04.01#ibcon#flushed, iclass 37, count 2 2006.285.07:41:04.01#ibcon#about to write, iclass 37, count 2 2006.285.07:41:04.01#ibcon#wrote, iclass 37, count 2 2006.285.07:41:04.01#ibcon#about to read 3, iclass 37, count 2 2006.285.07:41:04.04#ibcon#read 3, iclass 37, count 2 2006.285.07:41:04.04#ibcon#about to read 4, iclass 37, count 2 2006.285.07:41:04.04#ibcon#read 4, iclass 37, count 2 2006.285.07:41:04.04#ibcon#about to read 5, iclass 37, count 2 2006.285.07:41:04.04#ibcon#read 5, iclass 37, count 2 2006.285.07:41:04.04#ibcon#about to read 6, iclass 37, count 2 2006.285.07:41:04.04#ibcon#read 6, iclass 37, count 2 2006.285.07:41:04.04#ibcon#end of sib2, iclass 37, count 2 2006.285.07:41:04.04#ibcon#*after write, iclass 37, count 2 2006.285.07:41:04.04#ibcon#*before return 0, iclass 37, count 2 2006.285.07:41:04.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:41:04.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:41:04.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.07:41:04.04#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:04.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:41:04.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:41:04.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:41:04.16#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:41:04.16#ibcon#first serial, iclass 37, count 0 2006.285.07:41:04.16#ibcon#enter sib2, iclass 37, count 0 2006.285.07:41:04.16#ibcon#flushed, iclass 37, count 0 2006.285.07:41:04.16#ibcon#about to write, iclass 37, count 0 2006.285.07:41:04.16#ibcon#wrote, iclass 37, count 0 2006.285.07:41:04.16#ibcon#about to read 3, iclass 37, count 0 2006.285.07:41:04.18#ibcon#read 3, iclass 37, count 0 2006.285.07:41:04.18#ibcon#about to read 4, iclass 37, count 0 2006.285.07:41:04.18#ibcon#read 4, iclass 37, count 0 2006.285.07:41:04.18#ibcon#about to read 5, iclass 37, count 0 2006.285.07:41:04.18#ibcon#read 5, iclass 37, count 0 2006.285.07:41:04.18#ibcon#about to read 6, iclass 37, count 0 2006.285.07:41:04.18#ibcon#read 6, iclass 37, count 0 2006.285.07:41:04.18#ibcon#end of sib2, iclass 37, count 0 2006.285.07:41:04.18#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:41:04.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:41:04.18#ibcon#[27=USB\r\n] 2006.285.07:41:04.18#ibcon#*before write, iclass 37, count 0 2006.285.07:41:04.18#ibcon#enter sib2, iclass 37, count 0 2006.285.07:41:04.18#ibcon#flushed, iclass 37, count 0 2006.285.07:41:04.18#ibcon#about to write, iclass 37, count 0 2006.285.07:41:04.18#ibcon#wrote, iclass 37, count 0 2006.285.07:41:04.18#ibcon#about to read 3, iclass 37, count 0 2006.285.07:41:04.21#ibcon#read 3, iclass 37, count 0 2006.285.07:41:04.21#ibcon#about to read 4, iclass 37, count 0 2006.285.07:41:04.21#ibcon#read 4, iclass 37, count 0 2006.285.07:41:04.21#ibcon#about to read 5, iclass 37, count 0 2006.285.07:41:04.21#ibcon#read 5, iclass 37, count 0 2006.285.07:41:04.21#ibcon#about to read 6, iclass 37, count 0 2006.285.07:41:04.21#ibcon#read 6, iclass 37, count 0 2006.285.07:41:04.21#ibcon#end of sib2, iclass 37, count 0 2006.285.07:41:04.21#ibcon#*after write, iclass 37, count 0 2006.285.07:41:04.21#ibcon#*before return 0, iclass 37, count 0 2006.285.07:41:04.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:41:04.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:41:04.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:41:04.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:41:04.21$vck44/vblo=3,649.99 2006.285.07:41:04.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.07:41:04.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.07:41:04.21#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:04.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:41:04.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:41:04.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:41:04.21#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:41:04.21#ibcon#first serial, iclass 39, count 0 2006.285.07:41:04.21#ibcon#enter sib2, iclass 39, count 0 2006.285.07:41:04.21#ibcon#flushed, iclass 39, count 0 2006.285.07:41:04.21#ibcon#about to write, iclass 39, count 0 2006.285.07:41:04.21#ibcon#wrote, iclass 39, count 0 2006.285.07:41:04.21#ibcon#about to read 3, iclass 39, count 0 2006.285.07:41:04.23#ibcon#read 3, iclass 39, count 0 2006.285.07:41:04.23#ibcon#about to read 4, iclass 39, count 0 2006.285.07:41:04.23#ibcon#read 4, iclass 39, count 0 2006.285.07:41:04.23#ibcon#about to read 5, iclass 39, count 0 2006.285.07:41:04.23#ibcon#read 5, iclass 39, count 0 2006.285.07:41:04.23#ibcon#about to read 6, iclass 39, count 0 2006.285.07:41:04.23#ibcon#read 6, iclass 39, count 0 2006.285.07:41:04.23#ibcon#end of sib2, iclass 39, count 0 2006.285.07:41:04.23#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:41:04.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:41:04.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:41:04.23#ibcon#*before write, iclass 39, count 0 2006.285.07:41:04.23#ibcon#enter sib2, iclass 39, count 0 2006.285.07:41:04.23#ibcon#flushed, iclass 39, count 0 2006.285.07:41:04.23#ibcon#about to write, iclass 39, count 0 2006.285.07:41:04.23#ibcon#wrote, iclass 39, count 0 2006.285.07:41:04.23#ibcon#about to read 3, iclass 39, count 0 2006.285.07:41:04.27#ibcon#read 3, iclass 39, count 0 2006.285.07:41:04.27#ibcon#about to read 4, iclass 39, count 0 2006.285.07:41:04.27#ibcon#read 4, iclass 39, count 0 2006.285.07:41:04.27#ibcon#about to read 5, iclass 39, count 0 2006.285.07:41:04.27#ibcon#read 5, iclass 39, count 0 2006.285.07:41:04.27#ibcon#about to read 6, iclass 39, count 0 2006.285.07:41:04.27#ibcon#read 6, iclass 39, count 0 2006.285.07:41:04.27#ibcon#end of sib2, iclass 39, count 0 2006.285.07:41:04.27#ibcon#*after write, iclass 39, count 0 2006.285.07:41:04.27#ibcon#*before return 0, iclass 39, count 0 2006.285.07:41:04.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:41:04.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:41:04.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:41:04.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:41:04.27$vck44/vb=3,4 2006.285.07:41:04.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.07:41:04.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.07:41:04.27#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:04.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:41:04.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:41:04.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:41:04.33#ibcon#enter wrdev, iclass 3, count 2 2006.285.07:41:04.33#ibcon#first serial, iclass 3, count 2 2006.285.07:41:04.33#ibcon#enter sib2, iclass 3, count 2 2006.285.07:41:04.33#ibcon#flushed, iclass 3, count 2 2006.285.07:41:04.33#ibcon#about to write, iclass 3, count 2 2006.285.07:41:04.33#ibcon#wrote, iclass 3, count 2 2006.285.07:41:04.33#ibcon#about to read 3, iclass 3, count 2 2006.285.07:41:04.35#ibcon#read 3, iclass 3, count 2 2006.285.07:41:04.35#ibcon#about to read 4, iclass 3, count 2 2006.285.07:41:04.35#ibcon#read 4, iclass 3, count 2 2006.285.07:41:04.35#ibcon#about to read 5, iclass 3, count 2 2006.285.07:41:04.35#ibcon#read 5, iclass 3, count 2 2006.285.07:41:04.35#ibcon#about to read 6, iclass 3, count 2 2006.285.07:41:04.35#ibcon#read 6, iclass 3, count 2 2006.285.07:41:04.35#ibcon#end of sib2, iclass 3, count 2 2006.285.07:41:04.35#ibcon#*mode == 0, iclass 3, count 2 2006.285.07:41:04.35#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.07:41:04.35#ibcon#[27=AT03-04\r\n] 2006.285.07:41:04.35#ibcon#*before write, iclass 3, count 2 2006.285.07:41:04.35#ibcon#enter sib2, iclass 3, count 2 2006.285.07:41:04.35#ibcon#flushed, iclass 3, count 2 2006.285.07:41:04.35#ibcon#about to write, iclass 3, count 2 2006.285.07:41:04.35#ibcon#wrote, iclass 3, count 2 2006.285.07:41:04.35#ibcon#about to read 3, iclass 3, count 2 2006.285.07:41:04.38#ibcon#read 3, iclass 3, count 2 2006.285.07:41:04.38#ibcon#about to read 4, iclass 3, count 2 2006.285.07:41:04.38#ibcon#read 4, iclass 3, count 2 2006.285.07:41:04.38#ibcon#about to read 5, iclass 3, count 2 2006.285.07:41:04.38#ibcon#read 5, iclass 3, count 2 2006.285.07:41:04.38#ibcon#about to read 6, iclass 3, count 2 2006.285.07:41:04.38#ibcon#read 6, iclass 3, count 2 2006.285.07:41:04.38#ibcon#end of sib2, iclass 3, count 2 2006.285.07:41:04.38#ibcon#*after write, iclass 3, count 2 2006.285.07:41:04.38#ibcon#*before return 0, iclass 3, count 2 2006.285.07:41:04.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:41:04.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:41:04.38#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.07:41:04.38#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:04.38#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:41:04.50#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:41:04.50#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:41:04.50#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:41:04.50#ibcon#first serial, iclass 3, count 0 2006.285.07:41:04.50#ibcon#enter sib2, iclass 3, count 0 2006.285.07:41:04.50#ibcon#flushed, iclass 3, count 0 2006.285.07:41:04.50#ibcon#about to write, iclass 3, count 0 2006.285.07:41:04.50#ibcon#wrote, iclass 3, count 0 2006.285.07:41:04.50#ibcon#about to read 3, iclass 3, count 0 2006.285.07:41:04.52#ibcon#read 3, iclass 3, count 0 2006.285.07:41:04.52#ibcon#about to read 4, iclass 3, count 0 2006.285.07:41:04.52#ibcon#read 4, iclass 3, count 0 2006.285.07:41:04.52#ibcon#about to read 5, iclass 3, count 0 2006.285.07:41:04.52#ibcon#read 5, iclass 3, count 0 2006.285.07:41:04.52#ibcon#about to read 6, iclass 3, count 0 2006.285.07:41:04.52#ibcon#read 6, iclass 3, count 0 2006.285.07:41:04.52#ibcon#end of sib2, iclass 3, count 0 2006.285.07:41:04.52#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:41:04.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:41:04.52#ibcon#[27=USB\r\n] 2006.285.07:41:04.52#ibcon#*before write, iclass 3, count 0 2006.285.07:41:04.52#ibcon#enter sib2, iclass 3, count 0 2006.285.07:41:04.52#ibcon#flushed, iclass 3, count 0 2006.285.07:41:04.52#ibcon#about to write, iclass 3, count 0 2006.285.07:41:04.52#ibcon#wrote, iclass 3, count 0 2006.285.07:41:04.52#ibcon#about to read 3, iclass 3, count 0 2006.285.07:41:04.55#ibcon#read 3, iclass 3, count 0 2006.285.07:41:04.55#ibcon#about to read 4, iclass 3, count 0 2006.285.07:41:04.55#ibcon#read 4, iclass 3, count 0 2006.285.07:41:04.55#ibcon#about to read 5, iclass 3, count 0 2006.285.07:41:04.55#ibcon#read 5, iclass 3, count 0 2006.285.07:41:04.55#ibcon#about to read 6, iclass 3, count 0 2006.285.07:41:04.55#ibcon#read 6, iclass 3, count 0 2006.285.07:41:04.55#ibcon#end of sib2, iclass 3, count 0 2006.285.07:41:04.55#ibcon#*after write, iclass 3, count 0 2006.285.07:41:04.55#ibcon#*before return 0, iclass 3, count 0 2006.285.07:41:04.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:41:04.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:41:04.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:41:04.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:41:04.55$vck44/vblo=4,679.99 2006.285.07:41:04.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.07:41:04.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.07:41:04.55#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:04.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:41:04.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:41:04.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:41:04.55#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:41:04.55#ibcon#first serial, iclass 5, count 0 2006.285.07:41:04.55#ibcon#enter sib2, iclass 5, count 0 2006.285.07:41:04.55#ibcon#flushed, iclass 5, count 0 2006.285.07:41:04.55#ibcon#about to write, iclass 5, count 0 2006.285.07:41:04.55#ibcon#wrote, iclass 5, count 0 2006.285.07:41:04.55#ibcon#about to read 3, iclass 5, count 0 2006.285.07:41:04.57#ibcon#read 3, iclass 5, count 0 2006.285.07:41:04.57#ibcon#about to read 4, iclass 5, count 0 2006.285.07:41:04.57#ibcon#read 4, iclass 5, count 0 2006.285.07:41:04.57#ibcon#about to read 5, iclass 5, count 0 2006.285.07:41:04.57#ibcon#read 5, iclass 5, count 0 2006.285.07:41:04.57#ibcon#about to read 6, iclass 5, count 0 2006.285.07:41:04.57#ibcon#read 6, iclass 5, count 0 2006.285.07:41:04.57#ibcon#end of sib2, iclass 5, count 0 2006.285.07:41:04.57#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:41:04.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:41:04.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:41:04.57#ibcon#*before write, iclass 5, count 0 2006.285.07:41:04.57#ibcon#enter sib2, iclass 5, count 0 2006.285.07:41:04.57#ibcon#flushed, iclass 5, count 0 2006.285.07:41:04.57#ibcon#about to write, iclass 5, count 0 2006.285.07:41:04.57#ibcon#wrote, iclass 5, count 0 2006.285.07:41:04.57#ibcon#about to read 3, iclass 5, count 0 2006.285.07:41:04.61#ibcon#read 3, iclass 5, count 0 2006.285.07:41:04.61#ibcon#about to read 4, iclass 5, count 0 2006.285.07:41:04.61#ibcon#read 4, iclass 5, count 0 2006.285.07:41:04.61#ibcon#about to read 5, iclass 5, count 0 2006.285.07:41:04.61#ibcon#read 5, iclass 5, count 0 2006.285.07:41:04.61#ibcon#about to read 6, iclass 5, count 0 2006.285.07:41:04.61#ibcon#read 6, iclass 5, count 0 2006.285.07:41:04.61#ibcon#end of sib2, iclass 5, count 0 2006.285.07:41:04.61#ibcon#*after write, iclass 5, count 0 2006.285.07:41:04.61#ibcon#*before return 0, iclass 5, count 0 2006.285.07:41:04.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:41:04.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:41:04.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:41:04.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:41:04.61$vck44/vb=4,5 2006.285.07:41:04.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.07:41:04.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.07:41:04.61#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:04.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:41:04.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:41:04.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:41:04.67#ibcon#enter wrdev, iclass 7, count 2 2006.285.07:41:04.67#ibcon#first serial, iclass 7, count 2 2006.285.07:41:04.67#ibcon#enter sib2, iclass 7, count 2 2006.285.07:41:04.67#ibcon#flushed, iclass 7, count 2 2006.285.07:41:04.67#ibcon#about to write, iclass 7, count 2 2006.285.07:41:04.67#ibcon#wrote, iclass 7, count 2 2006.285.07:41:04.67#ibcon#about to read 3, iclass 7, count 2 2006.285.07:41:04.69#ibcon#read 3, iclass 7, count 2 2006.285.07:41:04.69#ibcon#about to read 4, iclass 7, count 2 2006.285.07:41:04.69#ibcon#read 4, iclass 7, count 2 2006.285.07:41:04.69#ibcon#about to read 5, iclass 7, count 2 2006.285.07:41:04.69#ibcon#read 5, iclass 7, count 2 2006.285.07:41:04.69#ibcon#about to read 6, iclass 7, count 2 2006.285.07:41:04.69#ibcon#read 6, iclass 7, count 2 2006.285.07:41:04.69#ibcon#end of sib2, iclass 7, count 2 2006.285.07:41:04.69#ibcon#*mode == 0, iclass 7, count 2 2006.285.07:41:04.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.07:41:04.69#ibcon#[27=AT04-05\r\n] 2006.285.07:41:04.69#ibcon#*before write, iclass 7, count 2 2006.285.07:41:04.69#ibcon#enter sib2, iclass 7, count 2 2006.285.07:41:04.69#ibcon#flushed, iclass 7, count 2 2006.285.07:41:04.69#ibcon#about to write, iclass 7, count 2 2006.285.07:41:04.69#ibcon#wrote, iclass 7, count 2 2006.285.07:41:04.69#ibcon#about to read 3, iclass 7, count 2 2006.285.07:41:04.72#ibcon#read 3, iclass 7, count 2 2006.285.07:41:04.72#ibcon#about to read 4, iclass 7, count 2 2006.285.07:41:04.72#ibcon#read 4, iclass 7, count 2 2006.285.07:41:04.72#ibcon#about to read 5, iclass 7, count 2 2006.285.07:41:04.72#ibcon#read 5, iclass 7, count 2 2006.285.07:41:04.72#ibcon#about to read 6, iclass 7, count 2 2006.285.07:41:04.72#ibcon#read 6, iclass 7, count 2 2006.285.07:41:04.72#ibcon#end of sib2, iclass 7, count 2 2006.285.07:41:04.72#ibcon#*after write, iclass 7, count 2 2006.285.07:41:04.72#ibcon#*before return 0, iclass 7, count 2 2006.285.07:41:04.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:41:04.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:41:04.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.07:41:04.72#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:04.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:41:04.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:41:04.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:41:04.84#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:41:04.84#ibcon#first serial, iclass 7, count 0 2006.285.07:41:04.84#ibcon#enter sib2, iclass 7, count 0 2006.285.07:41:04.84#ibcon#flushed, iclass 7, count 0 2006.285.07:41:04.84#ibcon#about to write, iclass 7, count 0 2006.285.07:41:04.84#ibcon#wrote, iclass 7, count 0 2006.285.07:41:04.84#ibcon#about to read 3, iclass 7, count 0 2006.285.07:41:04.86#ibcon#read 3, iclass 7, count 0 2006.285.07:41:04.86#ibcon#about to read 4, iclass 7, count 0 2006.285.07:41:04.86#ibcon#read 4, iclass 7, count 0 2006.285.07:41:04.86#ibcon#about to read 5, iclass 7, count 0 2006.285.07:41:04.86#ibcon#read 5, iclass 7, count 0 2006.285.07:41:04.86#ibcon#about to read 6, iclass 7, count 0 2006.285.07:41:04.86#ibcon#read 6, iclass 7, count 0 2006.285.07:41:04.86#ibcon#end of sib2, iclass 7, count 0 2006.285.07:41:04.86#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:41:04.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:41:04.86#ibcon#[27=USB\r\n] 2006.285.07:41:04.86#ibcon#*before write, iclass 7, count 0 2006.285.07:41:04.86#ibcon#enter sib2, iclass 7, count 0 2006.285.07:41:04.86#ibcon#flushed, iclass 7, count 0 2006.285.07:41:04.86#ibcon#about to write, iclass 7, count 0 2006.285.07:41:04.86#ibcon#wrote, iclass 7, count 0 2006.285.07:41:04.86#ibcon#about to read 3, iclass 7, count 0 2006.285.07:41:04.89#ibcon#read 3, iclass 7, count 0 2006.285.07:41:04.89#ibcon#about to read 4, iclass 7, count 0 2006.285.07:41:04.89#ibcon#read 4, iclass 7, count 0 2006.285.07:41:04.89#ibcon#about to read 5, iclass 7, count 0 2006.285.07:41:04.89#ibcon#read 5, iclass 7, count 0 2006.285.07:41:04.89#ibcon#about to read 6, iclass 7, count 0 2006.285.07:41:04.89#ibcon#read 6, iclass 7, count 0 2006.285.07:41:04.89#ibcon#end of sib2, iclass 7, count 0 2006.285.07:41:04.89#ibcon#*after write, iclass 7, count 0 2006.285.07:41:04.89#ibcon#*before return 0, iclass 7, count 0 2006.285.07:41:04.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:41:04.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:41:04.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:41:04.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:41:04.89$vck44/vblo=5,709.99 2006.285.07:41:04.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.07:41:04.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.07:41:04.89#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:04.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:41:04.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:41:04.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:41:04.89#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:41:04.89#ibcon#first serial, iclass 11, count 0 2006.285.07:41:04.89#ibcon#enter sib2, iclass 11, count 0 2006.285.07:41:04.89#ibcon#flushed, iclass 11, count 0 2006.285.07:41:04.89#ibcon#about to write, iclass 11, count 0 2006.285.07:41:04.89#ibcon#wrote, iclass 11, count 0 2006.285.07:41:04.89#ibcon#about to read 3, iclass 11, count 0 2006.285.07:41:04.91#ibcon#read 3, iclass 11, count 0 2006.285.07:41:04.91#ibcon#about to read 4, iclass 11, count 0 2006.285.07:41:04.91#ibcon#read 4, iclass 11, count 0 2006.285.07:41:04.91#ibcon#about to read 5, iclass 11, count 0 2006.285.07:41:04.91#ibcon#read 5, iclass 11, count 0 2006.285.07:41:04.91#ibcon#about to read 6, iclass 11, count 0 2006.285.07:41:04.91#ibcon#read 6, iclass 11, count 0 2006.285.07:41:04.91#ibcon#end of sib2, iclass 11, count 0 2006.285.07:41:04.91#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:41:04.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:41:04.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:41:04.91#ibcon#*before write, iclass 11, count 0 2006.285.07:41:04.91#ibcon#enter sib2, iclass 11, count 0 2006.285.07:41:04.91#ibcon#flushed, iclass 11, count 0 2006.285.07:41:04.91#ibcon#about to write, iclass 11, count 0 2006.285.07:41:04.91#ibcon#wrote, iclass 11, count 0 2006.285.07:41:04.91#ibcon#about to read 3, iclass 11, count 0 2006.285.07:41:04.95#ibcon#read 3, iclass 11, count 0 2006.285.07:41:04.95#ibcon#about to read 4, iclass 11, count 0 2006.285.07:41:04.95#ibcon#read 4, iclass 11, count 0 2006.285.07:41:04.95#ibcon#about to read 5, iclass 11, count 0 2006.285.07:41:04.95#ibcon#read 5, iclass 11, count 0 2006.285.07:41:04.95#ibcon#about to read 6, iclass 11, count 0 2006.285.07:41:04.95#ibcon#read 6, iclass 11, count 0 2006.285.07:41:04.95#ibcon#end of sib2, iclass 11, count 0 2006.285.07:41:04.95#ibcon#*after write, iclass 11, count 0 2006.285.07:41:04.95#ibcon#*before return 0, iclass 11, count 0 2006.285.07:41:04.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:41:04.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:41:04.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:41:04.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:41:04.95$vck44/vb=5,4 2006.285.07:41:04.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.07:41:04.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.07:41:04.95#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:04.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:41:05.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:41:05.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:41:05.01#ibcon#enter wrdev, iclass 13, count 2 2006.285.07:41:05.01#ibcon#first serial, iclass 13, count 2 2006.285.07:41:05.01#ibcon#enter sib2, iclass 13, count 2 2006.285.07:41:05.01#ibcon#flushed, iclass 13, count 2 2006.285.07:41:05.01#ibcon#about to write, iclass 13, count 2 2006.285.07:41:05.01#ibcon#wrote, iclass 13, count 2 2006.285.07:41:05.01#ibcon#about to read 3, iclass 13, count 2 2006.285.07:41:05.03#ibcon#read 3, iclass 13, count 2 2006.285.07:41:05.03#ibcon#about to read 4, iclass 13, count 2 2006.285.07:41:05.03#ibcon#read 4, iclass 13, count 2 2006.285.07:41:05.03#ibcon#about to read 5, iclass 13, count 2 2006.285.07:41:05.03#ibcon#read 5, iclass 13, count 2 2006.285.07:41:05.03#ibcon#about to read 6, iclass 13, count 2 2006.285.07:41:05.03#ibcon#read 6, iclass 13, count 2 2006.285.07:41:05.03#ibcon#end of sib2, iclass 13, count 2 2006.285.07:41:05.03#ibcon#*mode == 0, iclass 13, count 2 2006.285.07:41:05.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.07:41:05.03#ibcon#[27=AT05-04\r\n] 2006.285.07:41:05.03#ibcon#*before write, iclass 13, count 2 2006.285.07:41:05.03#ibcon#enter sib2, iclass 13, count 2 2006.285.07:41:05.03#ibcon#flushed, iclass 13, count 2 2006.285.07:41:05.03#ibcon#about to write, iclass 13, count 2 2006.285.07:41:05.03#ibcon#wrote, iclass 13, count 2 2006.285.07:41:05.03#ibcon#about to read 3, iclass 13, count 2 2006.285.07:41:05.06#ibcon#read 3, iclass 13, count 2 2006.285.07:41:05.06#ibcon#about to read 4, iclass 13, count 2 2006.285.07:41:05.06#ibcon#read 4, iclass 13, count 2 2006.285.07:41:05.06#ibcon#about to read 5, iclass 13, count 2 2006.285.07:41:05.06#ibcon#read 5, iclass 13, count 2 2006.285.07:41:05.06#ibcon#about to read 6, iclass 13, count 2 2006.285.07:41:05.06#ibcon#read 6, iclass 13, count 2 2006.285.07:41:05.06#ibcon#end of sib2, iclass 13, count 2 2006.285.07:41:05.06#ibcon#*after write, iclass 13, count 2 2006.285.07:41:05.06#ibcon#*before return 0, iclass 13, count 2 2006.285.07:41:05.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:41:05.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:41:05.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.07:41:05.06#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:05.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:41:05.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:41:05.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:41:05.18#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:41:05.18#ibcon#first serial, iclass 13, count 0 2006.285.07:41:05.18#ibcon#enter sib2, iclass 13, count 0 2006.285.07:41:05.18#ibcon#flushed, iclass 13, count 0 2006.285.07:41:05.18#ibcon#about to write, iclass 13, count 0 2006.285.07:41:05.18#ibcon#wrote, iclass 13, count 0 2006.285.07:41:05.18#ibcon#about to read 3, iclass 13, count 0 2006.285.07:41:05.20#ibcon#read 3, iclass 13, count 0 2006.285.07:41:05.20#ibcon#about to read 4, iclass 13, count 0 2006.285.07:41:05.20#ibcon#read 4, iclass 13, count 0 2006.285.07:41:05.20#ibcon#about to read 5, iclass 13, count 0 2006.285.07:41:05.20#ibcon#read 5, iclass 13, count 0 2006.285.07:41:05.20#ibcon#about to read 6, iclass 13, count 0 2006.285.07:41:05.20#ibcon#read 6, iclass 13, count 0 2006.285.07:41:05.20#ibcon#end of sib2, iclass 13, count 0 2006.285.07:41:05.20#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:41:05.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:41:05.20#ibcon#[27=USB\r\n] 2006.285.07:41:05.20#ibcon#*before write, iclass 13, count 0 2006.285.07:41:05.20#ibcon#enter sib2, iclass 13, count 0 2006.285.07:41:05.20#ibcon#flushed, iclass 13, count 0 2006.285.07:41:05.20#ibcon#about to write, iclass 13, count 0 2006.285.07:41:05.20#ibcon#wrote, iclass 13, count 0 2006.285.07:41:05.20#ibcon#about to read 3, iclass 13, count 0 2006.285.07:41:05.23#ibcon#read 3, iclass 13, count 0 2006.285.07:41:05.23#ibcon#about to read 4, iclass 13, count 0 2006.285.07:41:05.23#ibcon#read 4, iclass 13, count 0 2006.285.07:41:05.23#ibcon#about to read 5, iclass 13, count 0 2006.285.07:41:05.23#ibcon#read 5, iclass 13, count 0 2006.285.07:41:05.23#ibcon#about to read 6, iclass 13, count 0 2006.285.07:41:05.23#ibcon#read 6, iclass 13, count 0 2006.285.07:41:05.23#ibcon#end of sib2, iclass 13, count 0 2006.285.07:41:05.23#ibcon#*after write, iclass 13, count 0 2006.285.07:41:05.23#ibcon#*before return 0, iclass 13, count 0 2006.285.07:41:05.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:41:05.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:41:05.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:41:05.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:41:05.23$vck44/vblo=6,719.99 2006.285.07:41:05.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.07:41:05.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.07:41:05.23#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:05.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:41:05.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:41:05.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:41:05.23#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:41:05.23#ibcon#first serial, iclass 15, count 0 2006.285.07:41:05.23#ibcon#enter sib2, iclass 15, count 0 2006.285.07:41:05.23#ibcon#flushed, iclass 15, count 0 2006.285.07:41:05.23#ibcon#about to write, iclass 15, count 0 2006.285.07:41:05.23#ibcon#wrote, iclass 15, count 0 2006.285.07:41:05.23#ibcon#about to read 3, iclass 15, count 0 2006.285.07:41:05.25#ibcon#read 3, iclass 15, count 0 2006.285.07:41:05.25#ibcon#about to read 4, iclass 15, count 0 2006.285.07:41:05.25#ibcon#read 4, iclass 15, count 0 2006.285.07:41:05.25#ibcon#about to read 5, iclass 15, count 0 2006.285.07:41:05.25#ibcon#read 5, iclass 15, count 0 2006.285.07:41:05.25#ibcon#about to read 6, iclass 15, count 0 2006.285.07:41:05.25#ibcon#read 6, iclass 15, count 0 2006.285.07:41:05.25#ibcon#end of sib2, iclass 15, count 0 2006.285.07:41:05.25#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:41:05.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:41:05.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:41:05.25#ibcon#*before write, iclass 15, count 0 2006.285.07:41:05.25#ibcon#enter sib2, iclass 15, count 0 2006.285.07:41:05.25#ibcon#flushed, iclass 15, count 0 2006.285.07:41:05.25#ibcon#about to write, iclass 15, count 0 2006.285.07:41:05.25#ibcon#wrote, iclass 15, count 0 2006.285.07:41:05.25#ibcon#about to read 3, iclass 15, count 0 2006.285.07:41:05.29#ibcon#read 3, iclass 15, count 0 2006.285.07:41:05.29#ibcon#about to read 4, iclass 15, count 0 2006.285.07:41:05.29#ibcon#read 4, iclass 15, count 0 2006.285.07:41:05.29#ibcon#about to read 5, iclass 15, count 0 2006.285.07:41:05.29#ibcon#read 5, iclass 15, count 0 2006.285.07:41:05.29#ibcon#about to read 6, iclass 15, count 0 2006.285.07:41:05.29#ibcon#read 6, iclass 15, count 0 2006.285.07:41:05.29#ibcon#end of sib2, iclass 15, count 0 2006.285.07:41:05.29#ibcon#*after write, iclass 15, count 0 2006.285.07:41:05.29#ibcon#*before return 0, iclass 15, count 0 2006.285.07:41:05.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:41:05.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:41:05.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:41:05.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:41:05.29$vck44/vb=6,3 2006.285.07:41:05.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.07:41:05.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.07:41:05.29#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:05.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:41:05.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:41:05.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:41:05.35#ibcon#enter wrdev, iclass 17, count 2 2006.285.07:41:05.35#ibcon#first serial, iclass 17, count 2 2006.285.07:41:05.35#ibcon#enter sib2, iclass 17, count 2 2006.285.07:41:05.35#ibcon#flushed, iclass 17, count 2 2006.285.07:41:05.35#ibcon#about to write, iclass 17, count 2 2006.285.07:41:05.35#ibcon#wrote, iclass 17, count 2 2006.285.07:41:05.35#ibcon#about to read 3, iclass 17, count 2 2006.285.07:41:05.37#ibcon#read 3, iclass 17, count 2 2006.285.07:41:05.37#ibcon#about to read 4, iclass 17, count 2 2006.285.07:41:05.37#ibcon#read 4, iclass 17, count 2 2006.285.07:41:05.37#ibcon#about to read 5, iclass 17, count 2 2006.285.07:41:05.37#ibcon#read 5, iclass 17, count 2 2006.285.07:41:05.37#ibcon#about to read 6, iclass 17, count 2 2006.285.07:41:05.37#ibcon#read 6, iclass 17, count 2 2006.285.07:41:05.37#ibcon#end of sib2, iclass 17, count 2 2006.285.07:41:05.37#ibcon#*mode == 0, iclass 17, count 2 2006.285.07:41:05.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.07:41:05.37#ibcon#[27=AT06-03\r\n] 2006.285.07:41:05.37#ibcon#*before write, iclass 17, count 2 2006.285.07:41:05.37#ibcon#enter sib2, iclass 17, count 2 2006.285.07:41:05.37#ibcon#flushed, iclass 17, count 2 2006.285.07:41:05.37#ibcon#about to write, iclass 17, count 2 2006.285.07:41:05.37#ibcon#wrote, iclass 17, count 2 2006.285.07:41:05.37#ibcon#about to read 3, iclass 17, count 2 2006.285.07:41:05.40#ibcon#read 3, iclass 17, count 2 2006.285.07:41:05.40#ibcon#about to read 4, iclass 17, count 2 2006.285.07:41:05.40#ibcon#read 4, iclass 17, count 2 2006.285.07:41:05.40#ibcon#about to read 5, iclass 17, count 2 2006.285.07:41:05.40#ibcon#read 5, iclass 17, count 2 2006.285.07:41:05.40#ibcon#about to read 6, iclass 17, count 2 2006.285.07:41:05.40#ibcon#read 6, iclass 17, count 2 2006.285.07:41:05.40#ibcon#end of sib2, iclass 17, count 2 2006.285.07:41:05.40#ibcon#*after write, iclass 17, count 2 2006.285.07:41:05.40#ibcon#*before return 0, iclass 17, count 2 2006.285.07:41:05.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:41:05.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:41:05.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.07:41:05.40#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:05.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:41:05.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:41:05.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:41:05.52#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:41:05.52#ibcon#first serial, iclass 17, count 0 2006.285.07:41:05.52#ibcon#enter sib2, iclass 17, count 0 2006.285.07:41:05.52#ibcon#flushed, iclass 17, count 0 2006.285.07:41:05.52#ibcon#about to write, iclass 17, count 0 2006.285.07:41:05.52#ibcon#wrote, iclass 17, count 0 2006.285.07:41:05.52#ibcon#about to read 3, iclass 17, count 0 2006.285.07:41:05.54#ibcon#read 3, iclass 17, count 0 2006.285.07:41:05.54#ibcon#about to read 4, iclass 17, count 0 2006.285.07:41:05.54#ibcon#read 4, iclass 17, count 0 2006.285.07:41:05.54#ibcon#about to read 5, iclass 17, count 0 2006.285.07:41:05.54#ibcon#read 5, iclass 17, count 0 2006.285.07:41:05.54#ibcon#about to read 6, iclass 17, count 0 2006.285.07:41:05.54#ibcon#read 6, iclass 17, count 0 2006.285.07:41:05.54#ibcon#end of sib2, iclass 17, count 0 2006.285.07:41:05.54#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:41:05.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:41:05.54#ibcon#[27=USB\r\n] 2006.285.07:41:05.54#ibcon#*before write, iclass 17, count 0 2006.285.07:41:05.54#ibcon#enter sib2, iclass 17, count 0 2006.285.07:41:05.54#ibcon#flushed, iclass 17, count 0 2006.285.07:41:05.54#ibcon#about to write, iclass 17, count 0 2006.285.07:41:05.54#ibcon#wrote, iclass 17, count 0 2006.285.07:41:05.54#ibcon#about to read 3, iclass 17, count 0 2006.285.07:41:05.57#ibcon#read 3, iclass 17, count 0 2006.285.07:41:05.57#ibcon#about to read 4, iclass 17, count 0 2006.285.07:41:05.57#ibcon#read 4, iclass 17, count 0 2006.285.07:41:05.57#ibcon#about to read 5, iclass 17, count 0 2006.285.07:41:05.57#ibcon#read 5, iclass 17, count 0 2006.285.07:41:05.57#ibcon#about to read 6, iclass 17, count 0 2006.285.07:41:05.57#ibcon#read 6, iclass 17, count 0 2006.285.07:41:05.57#ibcon#end of sib2, iclass 17, count 0 2006.285.07:41:05.57#ibcon#*after write, iclass 17, count 0 2006.285.07:41:05.57#ibcon#*before return 0, iclass 17, count 0 2006.285.07:41:05.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:41:05.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:41:05.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:41:05.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:41:05.57$vck44/vblo=7,734.99 2006.285.07:41:05.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.07:41:05.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.07:41:05.57#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:05.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:41:05.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:41:05.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:41:05.57#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:41:05.57#ibcon#first serial, iclass 19, count 0 2006.285.07:41:05.57#ibcon#enter sib2, iclass 19, count 0 2006.285.07:41:05.57#ibcon#flushed, iclass 19, count 0 2006.285.07:41:05.57#ibcon#about to write, iclass 19, count 0 2006.285.07:41:05.57#ibcon#wrote, iclass 19, count 0 2006.285.07:41:05.57#ibcon#about to read 3, iclass 19, count 0 2006.285.07:41:05.59#ibcon#read 3, iclass 19, count 0 2006.285.07:41:05.59#ibcon#about to read 4, iclass 19, count 0 2006.285.07:41:05.59#ibcon#read 4, iclass 19, count 0 2006.285.07:41:05.59#ibcon#about to read 5, iclass 19, count 0 2006.285.07:41:05.59#ibcon#read 5, iclass 19, count 0 2006.285.07:41:05.59#ibcon#about to read 6, iclass 19, count 0 2006.285.07:41:05.59#ibcon#read 6, iclass 19, count 0 2006.285.07:41:05.59#ibcon#end of sib2, iclass 19, count 0 2006.285.07:41:05.59#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:41:05.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:41:05.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:41:05.59#ibcon#*before write, iclass 19, count 0 2006.285.07:41:05.59#ibcon#enter sib2, iclass 19, count 0 2006.285.07:41:05.59#ibcon#flushed, iclass 19, count 0 2006.285.07:41:05.59#ibcon#about to write, iclass 19, count 0 2006.285.07:41:05.59#ibcon#wrote, iclass 19, count 0 2006.285.07:41:05.59#ibcon#about to read 3, iclass 19, count 0 2006.285.07:41:05.63#ibcon#read 3, iclass 19, count 0 2006.285.07:41:05.63#ibcon#about to read 4, iclass 19, count 0 2006.285.07:41:05.63#ibcon#read 4, iclass 19, count 0 2006.285.07:41:05.63#ibcon#about to read 5, iclass 19, count 0 2006.285.07:41:05.63#ibcon#read 5, iclass 19, count 0 2006.285.07:41:05.63#ibcon#about to read 6, iclass 19, count 0 2006.285.07:41:05.63#ibcon#read 6, iclass 19, count 0 2006.285.07:41:05.63#ibcon#end of sib2, iclass 19, count 0 2006.285.07:41:05.63#ibcon#*after write, iclass 19, count 0 2006.285.07:41:05.63#ibcon#*before return 0, iclass 19, count 0 2006.285.07:41:05.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:41:05.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:41:05.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:41:05.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:41:05.63$vck44/vb=7,4 2006.285.07:41:05.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.07:41:05.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.07:41:05.63#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:05.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:41:05.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:41:05.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:41:05.69#ibcon#enter wrdev, iclass 21, count 2 2006.285.07:41:05.69#ibcon#first serial, iclass 21, count 2 2006.285.07:41:05.69#ibcon#enter sib2, iclass 21, count 2 2006.285.07:41:05.69#ibcon#flushed, iclass 21, count 2 2006.285.07:41:05.69#ibcon#about to write, iclass 21, count 2 2006.285.07:41:05.69#ibcon#wrote, iclass 21, count 2 2006.285.07:41:05.69#ibcon#about to read 3, iclass 21, count 2 2006.285.07:41:05.71#ibcon#read 3, iclass 21, count 2 2006.285.07:41:05.71#ibcon#about to read 4, iclass 21, count 2 2006.285.07:41:05.71#ibcon#read 4, iclass 21, count 2 2006.285.07:41:05.71#ibcon#about to read 5, iclass 21, count 2 2006.285.07:41:05.71#ibcon#read 5, iclass 21, count 2 2006.285.07:41:05.71#ibcon#about to read 6, iclass 21, count 2 2006.285.07:41:05.71#ibcon#read 6, iclass 21, count 2 2006.285.07:41:05.71#ibcon#end of sib2, iclass 21, count 2 2006.285.07:41:05.71#ibcon#*mode == 0, iclass 21, count 2 2006.285.07:41:05.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.07:41:05.71#ibcon#[27=AT07-04\r\n] 2006.285.07:41:05.71#ibcon#*before write, iclass 21, count 2 2006.285.07:41:05.71#ibcon#enter sib2, iclass 21, count 2 2006.285.07:41:05.71#ibcon#flushed, iclass 21, count 2 2006.285.07:41:05.71#ibcon#about to write, iclass 21, count 2 2006.285.07:41:05.71#ibcon#wrote, iclass 21, count 2 2006.285.07:41:05.71#ibcon#about to read 3, iclass 21, count 2 2006.285.07:41:05.74#ibcon#read 3, iclass 21, count 2 2006.285.07:41:05.74#ibcon#about to read 4, iclass 21, count 2 2006.285.07:41:05.74#ibcon#read 4, iclass 21, count 2 2006.285.07:41:05.74#ibcon#about to read 5, iclass 21, count 2 2006.285.07:41:05.74#ibcon#read 5, iclass 21, count 2 2006.285.07:41:05.74#ibcon#about to read 6, iclass 21, count 2 2006.285.07:41:05.74#ibcon#read 6, iclass 21, count 2 2006.285.07:41:05.74#ibcon#end of sib2, iclass 21, count 2 2006.285.07:41:05.74#ibcon#*after write, iclass 21, count 2 2006.285.07:41:05.74#ibcon#*before return 0, iclass 21, count 2 2006.285.07:41:05.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:41:05.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:41:05.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.07:41:05.74#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:05.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:41:05.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:41:05.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:41:05.86#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:41:05.86#ibcon#first serial, iclass 21, count 0 2006.285.07:41:05.86#ibcon#enter sib2, iclass 21, count 0 2006.285.07:41:05.86#ibcon#flushed, iclass 21, count 0 2006.285.07:41:05.86#ibcon#about to write, iclass 21, count 0 2006.285.07:41:05.86#ibcon#wrote, iclass 21, count 0 2006.285.07:41:05.86#ibcon#about to read 3, iclass 21, count 0 2006.285.07:41:05.88#ibcon#read 3, iclass 21, count 0 2006.285.07:41:05.88#ibcon#about to read 4, iclass 21, count 0 2006.285.07:41:05.88#ibcon#read 4, iclass 21, count 0 2006.285.07:41:05.88#ibcon#about to read 5, iclass 21, count 0 2006.285.07:41:05.88#ibcon#read 5, iclass 21, count 0 2006.285.07:41:05.88#ibcon#about to read 6, iclass 21, count 0 2006.285.07:41:05.88#ibcon#read 6, iclass 21, count 0 2006.285.07:41:05.88#ibcon#end of sib2, iclass 21, count 0 2006.285.07:41:05.88#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:41:05.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:41:05.88#ibcon#[27=USB\r\n] 2006.285.07:41:05.88#ibcon#*before write, iclass 21, count 0 2006.285.07:41:05.88#ibcon#enter sib2, iclass 21, count 0 2006.285.07:41:05.88#ibcon#flushed, iclass 21, count 0 2006.285.07:41:05.88#ibcon#about to write, iclass 21, count 0 2006.285.07:41:05.88#ibcon#wrote, iclass 21, count 0 2006.285.07:41:05.88#ibcon#about to read 3, iclass 21, count 0 2006.285.07:41:05.91#ibcon#read 3, iclass 21, count 0 2006.285.07:41:05.91#ibcon#about to read 4, iclass 21, count 0 2006.285.07:41:05.91#ibcon#read 4, iclass 21, count 0 2006.285.07:41:05.91#ibcon#about to read 5, iclass 21, count 0 2006.285.07:41:05.91#ibcon#read 5, iclass 21, count 0 2006.285.07:41:05.91#ibcon#about to read 6, iclass 21, count 0 2006.285.07:41:05.91#ibcon#read 6, iclass 21, count 0 2006.285.07:41:05.91#ibcon#end of sib2, iclass 21, count 0 2006.285.07:41:05.91#ibcon#*after write, iclass 21, count 0 2006.285.07:41:05.91#ibcon#*before return 0, iclass 21, count 0 2006.285.07:41:05.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:41:05.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:41:05.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:41:05.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:41:05.91$vck44/vblo=8,744.99 2006.285.07:41:05.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.07:41:05.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.07:41:05.91#ibcon#ireg 17 cls_cnt 0 2006.285.07:41:05.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:41:05.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:41:05.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:41:05.91#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:41:05.91#ibcon#first serial, iclass 23, count 0 2006.285.07:41:05.91#ibcon#enter sib2, iclass 23, count 0 2006.285.07:41:05.91#ibcon#flushed, iclass 23, count 0 2006.285.07:41:05.91#ibcon#about to write, iclass 23, count 0 2006.285.07:41:05.91#ibcon#wrote, iclass 23, count 0 2006.285.07:41:05.91#ibcon#about to read 3, iclass 23, count 0 2006.285.07:41:05.93#ibcon#read 3, iclass 23, count 0 2006.285.07:41:05.93#ibcon#about to read 4, iclass 23, count 0 2006.285.07:41:05.93#ibcon#read 4, iclass 23, count 0 2006.285.07:41:05.93#ibcon#about to read 5, iclass 23, count 0 2006.285.07:41:05.93#ibcon#read 5, iclass 23, count 0 2006.285.07:41:05.93#ibcon#about to read 6, iclass 23, count 0 2006.285.07:41:05.93#ibcon#read 6, iclass 23, count 0 2006.285.07:41:05.93#ibcon#end of sib2, iclass 23, count 0 2006.285.07:41:05.93#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:41:05.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:41:05.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:41:05.93#ibcon#*before write, iclass 23, count 0 2006.285.07:41:05.93#ibcon#enter sib2, iclass 23, count 0 2006.285.07:41:05.93#ibcon#flushed, iclass 23, count 0 2006.285.07:41:05.93#ibcon#about to write, iclass 23, count 0 2006.285.07:41:05.93#ibcon#wrote, iclass 23, count 0 2006.285.07:41:05.93#ibcon#about to read 3, iclass 23, count 0 2006.285.07:41:05.97#ibcon#read 3, iclass 23, count 0 2006.285.07:41:05.97#ibcon#about to read 4, iclass 23, count 0 2006.285.07:41:05.97#ibcon#read 4, iclass 23, count 0 2006.285.07:41:05.97#ibcon#about to read 5, iclass 23, count 0 2006.285.07:41:05.97#ibcon#read 5, iclass 23, count 0 2006.285.07:41:05.97#ibcon#about to read 6, iclass 23, count 0 2006.285.07:41:05.97#ibcon#read 6, iclass 23, count 0 2006.285.07:41:05.97#ibcon#end of sib2, iclass 23, count 0 2006.285.07:41:05.97#ibcon#*after write, iclass 23, count 0 2006.285.07:41:05.97#ibcon#*before return 0, iclass 23, count 0 2006.285.07:41:05.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:41:05.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:41:05.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:41:05.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:41:05.97$vck44/vb=8,4 2006.285.07:41:05.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.07:41:05.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.07:41:05.97#ibcon#ireg 11 cls_cnt 2 2006.285.07:41:05.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:41:06.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:41:06.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:41:06.03#ibcon#enter wrdev, iclass 25, count 2 2006.285.07:41:06.03#ibcon#first serial, iclass 25, count 2 2006.285.07:41:06.03#ibcon#enter sib2, iclass 25, count 2 2006.285.07:41:06.03#ibcon#flushed, iclass 25, count 2 2006.285.07:41:06.03#ibcon#about to write, iclass 25, count 2 2006.285.07:41:06.03#ibcon#wrote, iclass 25, count 2 2006.285.07:41:06.03#ibcon#about to read 3, iclass 25, count 2 2006.285.07:41:06.05#ibcon#read 3, iclass 25, count 2 2006.285.07:41:06.05#ibcon#about to read 4, iclass 25, count 2 2006.285.07:41:06.05#ibcon#read 4, iclass 25, count 2 2006.285.07:41:06.05#ibcon#about to read 5, iclass 25, count 2 2006.285.07:41:06.05#ibcon#read 5, iclass 25, count 2 2006.285.07:41:06.05#ibcon#about to read 6, iclass 25, count 2 2006.285.07:41:06.05#ibcon#read 6, iclass 25, count 2 2006.285.07:41:06.05#ibcon#end of sib2, iclass 25, count 2 2006.285.07:41:06.05#ibcon#*mode == 0, iclass 25, count 2 2006.285.07:41:06.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.07:41:06.05#ibcon#[27=AT08-04\r\n] 2006.285.07:41:06.05#ibcon#*before write, iclass 25, count 2 2006.285.07:41:06.05#ibcon#enter sib2, iclass 25, count 2 2006.285.07:41:06.05#ibcon#flushed, iclass 25, count 2 2006.285.07:41:06.05#ibcon#about to write, iclass 25, count 2 2006.285.07:41:06.05#ibcon#wrote, iclass 25, count 2 2006.285.07:41:06.05#ibcon#about to read 3, iclass 25, count 2 2006.285.07:41:06.08#ibcon#read 3, iclass 25, count 2 2006.285.07:41:06.08#ibcon#about to read 4, iclass 25, count 2 2006.285.07:41:06.08#ibcon#read 4, iclass 25, count 2 2006.285.07:41:06.08#ibcon#about to read 5, iclass 25, count 2 2006.285.07:41:06.08#ibcon#read 5, iclass 25, count 2 2006.285.07:41:06.08#ibcon#about to read 6, iclass 25, count 2 2006.285.07:41:06.08#ibcon#read 6, iclass 25, count 2 2006.285.07:41:06.08#ibcon#end of sib2, iclass 25, count 2 2006.285.07:41:06.08#ibcon#*after write, iclass 25, count 2 2006.285.07:41:06.08#ibcon#*before return 0, iclass 25, count 2 2006.285.07:41:06.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:41:06.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:41:06.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.07:41:06.08#ibcon#ireg 7 cls_cnt 0 2006.285.07:41:06.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:41:06.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:41:06.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:41:06.20#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:41:06.20#ibcon#first serial, iclass 25, count 0 2006.285.07:41:06.20#ibcon#enter sib2, iclass 25, count 0 2006.285.07:41:06.20#ibcon#flushed, iclass 25, count 0 2006.285.07:41:06.20#ibcon#about to write, iclass 25, count 0 2006.285.07:41:06.20#ibcon#wrote, iclass 25, count 0 2006.285.07:41:06.20#ibcon#about to read 3, iclass 25, count 0 2006.285.07:41:06.22#ibcon#read 3, iclass 25, count 0 2006.285.07:41:06.22#ibcon#about to read 4, iclass 25, count 0 2006.285.07:41:06.22#ibcon#read 4, iclass 25, count 0 2006.285.07:41:06.22#ibcon#about to read 5, iclass 25, count 0 2006.285.07:41:06.22#ibcon#read 5, iclass 25, count 0 2006.285.07:41:06.22#ibcon#about to read 6, iclass 25, count 0 2006.285.07:41:06.22#ibcon#read 6, iclass 25, count 0 2006.285.07:41:06.22#ibcon#end of sib2, iclass 25, count 0 2006.285.07:41:06.22#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:41:06.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:41:06.22#ibcon#[27=USB\r\n] 2006.285.07:41:06.22#ibcon#*before write, iclass 25, count 0 2006.285.07:41:06.22#ibcon#enter sib2, iclass 25, count 0 2006.285.07:41:06.22#ibcon#flushed, iclass 25, count 0 2006.285.07:41:06.22#ibcon#about to write, iclass 25, count 0 2006.285.07:41:06.22#ibcon#wrote, iclass 25, count 0 2006.285.07:41:06.22#ibcon#about to read 3, iclass 25, count 0 2006.285.07:41:06.25#ibcon#read 3, iclass 25, count 0 2006.285.07:41:06.25#ibcon#about to read 4, iclass 25, count 0 2006.285.07:41:06.25#ibcon#read 4, iclass 25, count 0 2006.285.07:41:06.25#ibcon#about to read 5, iclass 25, count 0 2006.285.07:41:06.25#ibcon#read 5, iclass 25, count 0 2006.285.07:41:06.25#ibcon#about to read 6, iclass 25, count 0 2006.285.07:41:06.25#ibcon#read 6, iclass 25, count 0 2006.285.07:41:06.25#ibcon#end of sib2, iclass 25, count 0 2006.285.07:41:06.25#ibcon#*after write, iclass 25, count 0 2006.285.07:41:06.25#ibcon#*before return 0, iclass 25, count 0 2006.285.07:41:06.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:41:06.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:41:06.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:41:06.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:41:06.25$vck44/vabw=wide 2006.285.07:41:06.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.07:41:06.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.07:41:06.25#ibcon#ireg 8 cls_cnt 0 2006.285.07:41:06.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:41:06.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:41:06.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:41:06.25#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:41:06.25#ibcon#first serial, iclass 27, count 0 2006.285.07:41:06.25#ibcon#enter sib2, iclass 27, count 0 2006.285.07:41:06.25#ibcon#flushed, iclass 27, count 0 2006.285.07:41:06.25#ibcon#about to write, iclass 27, count 0 2006.285.07:41:06.25#ibcon#wrote, iclass 27, count 0 2006.285.07:41:06.25#ibcon#about to read 3, iclass 27, count 0 2006.285.07:41:06.27#ibcon#read 3, iclass 27, count 0 2006.285.07:41:06.27#ibcon#about to read 4, iclass 27, count 0 2006.285.07:41:06.27#ibcon#read 4, iclass 27, count 0 2006.285.07:41:06.27#ibcon#about to read 5, iclass 27, count 0 2006.285.07:41:06.27#ibcon#read 5, iclass 27, count 0 2006.285.07:41:06.27#ibcon#about to read 6, iclass 27, count 0 2006.285.07:41:06.27#ibcon#read 6, iclass 27, count 0 2006.285.07:41:06.27#ibcon#end of sib2, iclass 27, count 0 2006.285.07:41:06.27#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:41:06.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:41:06.27#ibcon#[25=BW32\r\n] 2006.285.07:41:06.27#ibcon#*before write, iclass 27, count 0 2006.285.07:41:06.27#ibcon#enter sib2, iclass 27, count 0 2006.285.07:41:06.27#ibcon#flushed, iclass 27, count 0 2006.285.07:41:06.27#ibcon#about to write, iclass 27, count 0 2006.285.07:41:06.27#ibcon#wrote, iclass 27, count 0 2006.285.07:41:06.27#ibcon#about to read 3, iclass 27, count 0 2006.285.07:41:06.30#ibcon#read 3, iclass 27, count 0 2006.285.07:41:06.30#ibcon#about to read 4, iclass 27, count 0 2006.285.07:41:06.30#ibcon#read 4, iclass 27, count 0 2006.285.07:41:06.30#ibcon#about to read 5, iclass 27, count 0 2006.285.07:41:06.30#ibcon#read 5, iclass 27, count 0 2006.285.07:41:06.30#ibcon#about to read 6, iclass 27, count 0 2006.285.07:41:06.30#ibcon#read 6, iclass 27, count 0 2006.285.07:41:06.30#ibcon#end of sib2, iclass 27, count 0 2006.285.07:41:06.30#ibcon#*after write, iclass 27, count 0 2006.285.07:41:06.30#ibcon#*before return 0, iclass 27, count 0 2006.285.07:41:06.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:41:06.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:41:06.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:41:06.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:41:06.30$vck44/vbbw=wide 2006.285.07:41:06.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.07:41:06.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.07:41:06.30#ibcon#ireg 8 cls_cnt 0 2006.285.07:41:06.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:41:06.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:41:06.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:41:06.37#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:41:06.37#ibcon#first serial, iclass 29, count 0 2006.285.07:41:06.37#ibcon#enter sib2, iclass 29, count 0 2006.285.07:41:06.37#ibcon#flushed, iclass 29, count 0 2006.285.07:41:06.37#ibcon#about to write, iclass 29, count 0 2006.285.07:41:06.37#ibcon#wrote, iclass 29, count 0 2006.285.07:41:06.37#ibcon#about to read 3, iclass 29, count 0 2006.285.07:41:06.39#ibcon#read 3, iclass 29, count 0 2006.285.07:41:06.39#ibcon#about to read 4, iclass 29, count 0 2006.285.07:41:06.39#ibcon#read 4, iclass 29, count 0 2006.285.07:41:06.39#ibcon#about to read 5, iclass 29, count 0 2006.285.07:41:06.39#ibcon#read 5, iclass 29, count 0 2006.285.07:41:06.39#ibcon#about to read 6, iclass 29, count 0 2006.285.07:41:06.39#ibcon#read 6, iclass 29, count 0 2006.285.07:41:06.39#ibcon#end of sib2, iclass 29, count 0 2006.285.07:41:06.39#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:41:06.39#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:41:06.39#ibcon#[27=BW32\r\n] 2006.285.07:41:06.39#ibcon#*before write, iclass 29, count 0 2006.285.07:41:06.39#ibcon#enter sib2, iclass 29, count 0 2006.285.07:41:06.39#ibcon#flushed, iclass 29, count 0 2006.285.07:41:06.39#ibcon#about to write, iclass 29, count 0 2006.285.07:41:06.39#ibcon#wrote, iclass 29, count 0 2006.285.07:41:06.39#ibcon#about to read 3, iclass 29, count 0 2006.285.07:41:06.42#ibcon#read 3, iclass 29, count 0 2006.285.07:41:06.42#ibcon#about to read 4, iclass 29, count 0 2006.285.07:41:06.42#ibcon#read 4, iclass 29, count 0 2006.285.07:41:06.42#ibcon#about to read 5, iclass 29, count 0 2006.285.07:41:06.42#ibcon#read 5, iclass 29, count 0 2006.285.07:41:06.42#ibcon#about to read 6, iclass 29, count 0 2006.285.07:41:06.42#ibcon#read 6, iclass 29, count 0 2006.285.07:41:06.42#ibcon#end of sib2, iclass 29, count 0 2006.285.07:41:06.42#ibcon#*after write, iclass 29, count 0 2006.285.07:41:06.42#ibcon#*before return 0, iclass 29, count 0 2006.285.07:41:06.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:41:06.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:41:06.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:41:06.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:41:06.42$setupk4/ifdk4 2006.285.07:41:06.42$ifdk4/lo= 2006.285.07:41:06.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:41:06.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:41:06.43$ifdk4/patch= 2006.285.07:41:06.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:41:06.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:41:06.43$setupk4/!*+20s 2006.285.07:41:10.14#trakl#Source acquired 2006.285.07:41:10.14#flagr#flagr/antenna,acquired 2006.285.07:41:11.54#abcon#<5=/05 2.7 4.8 23.45 771014.3\r\n> 2006.285.07:41:11.56#abcon#{5=INTERFACE CLEAR} 2006.285.07:41:11.62#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:41:20.95$setupk4/"tpicd 2006.285.07:41:20.95$setupk4/echo=off 2006.285.07:41:20.95$setupk4/xlog=off 2006.285.07:41:20.95:!2006.285.07:46:17 2006.285.07:46:17.00:preob 2006.285.07:46:17.14/onsource/TRACKING 2006.285.07:46:17.14:!2006.285.07:46:27 2006.285.07:46:27.00:"tape 2006.285.07:46:27.00:"st=record 2006.285.07:46:27.00:data_valid=on 2006.285.07:46:27.00:midob 2006.285.07:46:28.14/onsource/TRACKING 2006.285.07:46:28.14/wx/23.32,1014.4,78 2006.285.07:46:28.23/cable/+6.4728E-03 2006.285.07:46:29.32/va/01,07,usb,yes,32,35 2006.285.07:46:29.32/va/02,06,usb,yes,32,32 2006.285.07:46:29.32/va/03,07,usb,yes,32,33 2006.285.07:46:29.32/va/04,06,usb,yes,33,35 2006.285.07:46:29.32/va/05,03,usb,yes,33,33 2006.285.07:46:29.32/va/06,04,usb,yes,29,29 2006.285.07:46:29.32/va/07,04,usb,yes,30,31 2006.285.07:46:29.32/va/08,03,usb,yes,30,37 2006.285.07:46:29.55/valo/01,524.99,yes,locked 2006.285.07:46:29.55/valo/02,534.99,yes,locked 2006.285.07:46:29.55/valo/03,564.99,yes,locked 2006.285.07:46:29.55/valo/04,624.99,yes,locked 2006.285.07:46:29.55/valo/05,734.99,yes,locked 2006.285.07:46:29.55/valo/06,814.99,yes,locked 2006.285.07:46:29.55/valo/07,864.99,yes,locked 2006.285.07:46:29.55/valo/08,884.99,yes,locked 2006.285.07:46:30.64/vb/01,04,usb,yes,31,29 2006.285.07:46:30.64/vb/02,05,usb,yes,29,29 2006.285.07:46:30.64/vb/03,04,usb,yes,30,33 2006.285.07:46:30.64/vb/04,05,usb,yes,30,29 2006.285.07:46:30.64/vb/05,04,usb,yes,27,29 2006.285.07:46:30.64/vb/06,03,usb,yes,38,34 2006.285.07:46:30.64/vb/07,04,usb,yes,31,31 2006.285.07:46:30.64/vb/08,04,usb,yes,28,32 2006.285.07:46:30.87/vblo/01,629.99,yes,locked 2006.285.07:46:30.87/vblo/02,634.99,yes,locked 2006.285.07:46:30.87/vblo/03,649.99,yes,locked 2006.285.07:46:30.87/vblo/04,679.99,yes,locked 2006.285.07:46:30.87/vblo/05,709.99,yes,locked 2006.285.07:46:30.87/vblo/06,719.99,yes,locked 2006.285.07:46:30.87/vblo/07,734.99,yes,locked 2006.285.07:46:30.87/vblo/08,744.99,yes,locked 2006.285.07:46:31.02/vabw/8 2006.285.07:46:31.17/vbbw/8 2006.285.07:46:31.26/xfe/off,on,12.2 2006.285.07:46:31.64/ifatt/23,28,28,28 2006.285.07:46:32.07/fmout-gps/S +2.79E-07 2006.285.07:46:32.09:!2006.285.07:47:47 2006.285.07:47:47.01:data_valid=off 2006.285.07:47:47.01:"et 2006.285.07:47:47.01:!+3s 2006.285.07:47:50.02:"tape 2006.285.07:47:50.02:postob 2006.285.07:47:50.19/cable/+6.4743E-03 2006.285.07:47:50.19/wx/23.30,1014.4,78 2006.285.07:47:50.25/fmout-gps/S +2.78E-07 2006.285.07:47:50.25:scan_name=285-0749,jd0610,60 2006.285.07:47:50.25:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.285.07:47:51.13#flagr#flagr/antenna,new-source 2006.285.07:47:51.13:checkk5 2006.285.07:47:51.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:47:52.16/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:47:52.54/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:47:52.91/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:47:53.31/chk_obsdata//k5ts1/T2850746??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.285.07:47:53.69/chk_obsdata//k5ts2/T2850746??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.285.07:47:54.11/chk_obsdata//k5ts3/T2850746??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.285.07:47:54.49/chk_obsdata//k5ts4/T2850746??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.285.07:47:55.29/k5log//k5ts1_log_newline 2006.285.07:47:56.08/k5log//k5ts2_log_newline 2006.285.07:47:57.14/k5log//k5ts3_log_newline 2006.285.07:47:58.23/k5log//k5ts4_log_newline 2006.285.07:47:58.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:47:58.26:setupk4=1 2006.285.07:47:58.26$setupk4/echo=on 2006.285.07:47:58.26$setupk4/pcalon 2006.285.07:47:58.26$pcalon/"no phase cal control is implemented here 2006.285.07:47:58.26$setupk4/"tpicd=stop 2006.285.07:47:58.26$setupk4/"rec=synch_on 2006.285.07:47:58.26$setupk4/"rec_mode=128 2006.285.07:47:58.26$setupk4/!* 2006.285.07:47:58.26$setupk4/recpk4 2006.285.07:47:58.26$recpk4/recpatch= 2006.285.07:47:58.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:47:58.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:47:58.26$setupk4/vck44 2006.285.07:47:58.26$vck44/valo=1,524.99 2006.285.07:47:58.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.07:47:58.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.07:47:58.26#ibcon#ireg 17 cls_cnt 0 2006.285.07:47:58.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:47:58.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:47:58.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:47:58.26#ibcon#enter wrdev, iclass 14, count 0 2006.285.07:47:58.26#ibcon#first serial, iclass 14, count 0 2006.285.07:47:58.26#ibcon#enter sib2, iclass 14, count 0 2006.285.07:47:58.26#ibcon#flushed, iclass 14, count 0 2006.285.07:47:58.26#ibcon#about to write, iclass 14, count 0 2006.285.07:47:58.26#ibcon#wrote, iclass 14, count 0 2006.285.07:47:58.26#ibcon#about to read 3, iclass 14, count 0 2006.285.07:47:58.27#ibcon#read 3, iclass 14, count 0 2006.285.07:47:58.27#ibcon#about to read 4, iclass 14, count 0 2006.285.07:47:58.27#ibcon#read 4, iclass 14, count 0 2006.285.07:47:58.27#ibcon#about to read 5, iclass 14, count 0 2006.285.07:47:58.27#ibcon#read 5, iclass 14, count 0 2006.285.07:47:58.27#ibcon#about to read 6, iclass 14, count 0 2006.285.07:47:58.27#ibcon#read 6, iclass 14, count 0 2006.285.07:47:58.27#ibcon#end of sib2, iclass 14, count 0 2006.285.07:47:58.27#ibcon#*mode == 0, iclass 14, count 0 2006.285.07:47:58.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.07:47:58.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:47:58.27#ibcon#*before write, iclass 14, count 0 2006.285.07:47:58.27#ibcon#enter sib2, iclass 14, count 0 2006.285.07:47:58.27#ibcon#flushed, iclass 14, count 0 2006.285.07:47:58.27#ibcon#about to write, iclass 14, count 0 2006.285.07:47:58.27#ibcon#wrote, iclass 14, count 0 2006.285.07:47:58.27#ibcon#about to read 3, iclass 14, count 0 2006.285.07:47:58.32#ibcon#read 3, iclass 14, count 0 2006.285.07:47:58.32#ibcon#about to read 4, iclass 14, count 0 2006.285.07:47:58.32#ibcon#read 4, iclass 14, count 0 2006.285.07:47:58.32#ibcon#about to read 5, iclass 14, count 0 2006.285.07:47:58.32#ibcon#read 5, iclass 14, count 0 2006.285.07:47:58.32#ibcon#about to read 6, iclass 14, count 0 2006.285.07:47:58.32#ibcon#read 6, iclass 14, count 0 2006.285.07:47:58.32#ibcon#end of sib2, iclass 14, count 0 2006.285.07:47:58.32#ibcon#*after write, iclass 14, count 0 2006.285.07:47:58.32#ibcon#*before return 0, iclass 14, count 0 2006.285.07:47:58.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:47:58.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:47:58.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.07:47:58.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.07:47:58.32$vck44/va=1,7 2006.285.07:47:58.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.07:47:58.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.07:47:58.32#ibcon#ireg 11 cls_cnt 2 2006.285.07:47:58.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:47:58.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:47:58.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:47:58.32#ibcon#enter wrdev, iclass 16, count 2 2006.285.07:47:58.32#ibcon#first serial, iclass 16, count 2 2006.285.07:47:58.32#ibcon#enter sib2, iclass 16, count 2 2006.285.07:47:58.32#ibcon#flushed, iclass 16, count 2 2006.285.07:47:58.32#ibcon#about to write, iclass 16, count 2 2006.285.07:47:58.32#ibcon#wrote, iclass 16, count 2 2006.285.07:47:58.32#ibcon#about to read 3, iclass 16, count 2 2006.285.07:47:58.34#ibcon#read 3, iclass 16, count 2 2006.285.07:47:58.34#ibcon#about to read 4, iclass 16, count 2 2006.285.07:47:58.34#ibcon#read 4, iclass 16, count 2 2006.285.07:47:58.34#ibcon#about to read 5, iclass 16, count 2 2006.285.07:47:58.34#ibcon#read 5, iclass 16, count 2 2006.285.07:47:58.34#ibcon#about to read 6, iclass 16, count 2 2006.285.07:47:58.34#ibcon#read 6, iclass 16, count 2 2006.285.07:47:58.34#ibcon#end of sib2, iclass 16, count 2 2006.285.07:47:58.34#ibcon#*mode == 0, iclass 16, count 2 2006.285.07:47:58.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.07:47:58.34#ibcon#[25=AT01-07\r\n] 2006.285.07:47:58.34#ibcon#*before write, iclass 16, count 2 2006.285.07:47:58.34#ibcon#enter sib2, iclass 16, count 2 2006.285.07:47:58.34#ibcon#flushed, iclass 16, count 2 2006.285.07:47:58.34#ibcon#about to write, iclass 16, count 2 2006.285.07:47:58.34#ibcon#wrote, iclass 16, count 2 2006.285.07:47:58.34#ibcon#about to read 3, iclass 16, count 2 2006.285.07:47:58.37#ibcon#read 3, iclass 16, count 2 2006.285.07:47:58.37#ibcon#about to read 4, iclass 16, count 2 2006.285.07:47:58.37#ibcon#read 4, iclass 16, count 2 2006.285.07:47:58.37#ibcon#about to read 5, iclass 16, count 2 2006.285.07:47:58.37#ibcon#read 5, iclass 16, count 2 2006.285.07:47:58.37#ibcon#about to read 6, iclass 16, count 2 2006.285.07:47:58.37#ibcon#read 6, iclass 16, count 2 2006.285.07:47:58.37#ibcon#end of sib2, iclass 16, count 2 2006.285.07:47:58.37#ibcon#*after write, iclass 16, count 2 2006.285.07:47:58.37#ibcon#*before return 0, iclass 16, count 2 2006.285.07:47:58.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:47:58.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:47:58.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.07:47:58.37#ibcon#ireg 7 cls_cnt 0 2006.285.07:47:58.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:47:58.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:47:58.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:47:58.49#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:47:58.49#ibcon#first serial, iclass 16, count 0 2006.285.07:47:58.49#ibcon#enter sib2, iclass 16, count 0 2006.285.07:47:58.49#ibcon#flushed, iclass 16, count 0 2006.285.07:47:58.49#ibcon#about to write, iclass 16, count 0 2006.285.07:47:58.49#ibcon#wrote, iclass 16, count 0 2006.285.07:47:58.49#ibcon#about to read 3, iclass 16, count 0 2006.285.07:47:58.51#ibcon#read 3, iclass 16, count 0 2006.285.07:47:58.51#ibcon#about to read 4, iclass 16, count 0 2006.285.07:47:58.51#ibcon#read 4, iclass 16, count 0 2006.285.07:47:58.51#ibcon#about to read 5, iclass 16, count 0 2006.285.07:47:58.51#ibcon#read 5, iclass 16, count 0 2006.285.07:47:58.51#ibcon#about to read 6, iclass 16, count 0 2006.285.07:47:58.51#ibcon#read 6, iclass 16, count 0 2006.285.07:47:58.51#ibcon#end of sib2, iclass 16, count 0 2006.285.07:47:58.51#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:47:58.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:47:58.51#ibcon#[25=USB\r\n] 2006.285.07:47:58.51#ibcon#*before write, iclass 16, count 0 2006.285.07:47:58.51#ibcon#enter sib2, iclass 16, count 0 2006.285.07:47:58.51#ibcon#flushed, iclass 16, count 0 2006.285.07:47:58.51#ibcon#about to write, iclass 16, count 0 2006.285.07:47:58.51#ibcon#wrote, iclass 16, count 0 2006.285.07:47:58.51#ibcon#about to read 3, iclass 16, count 0 2006.285.07:47:58.54#ibcon#read 3, iclass 16, count 0 2006.285.07:47:58.54#ibcon#about to read 4, iclass 16, count 0 2006.285.07:47:58.54#ibcon#read 4, iclass 16, count 0 2006.285.07:47:58.54#ibcon#about to read 5, iclass 16, count 0 2006.285.07:47:58.54#ibcon#read 5, iclass 16, count 0 2006.285.07:47:58.54#ibcon#about to read 6, iclass 16, count 0 2006.285.07:47:58.54#ibcon#read 6, iclass 16, count 0 2006.285.07:47:58.54#ibcon#end of sib2, iclass 16, count 0 2006.285.07:47:58.54#ibcon#*after write, iclass 16, count 0 2006.285.07:47:58.54#ibcon#*before return 0, iclass 16, count 0 2006.285.07:47:58.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:47:58.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:47:58.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:47:58.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:47:58.54$vck44/valo=2,534.99 2006.285.07:47:58.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.07:47:58.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.07:47:58.54#ibcon#ireg 17 cls_cnt 0 2006.285.07:47:58.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:47:58.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:47:58.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:47:58.54#ibcon#enter wrdev, iclass 18, count 0 2006.285.07:47:58.54#ibcon#first serial, iclass 18, count 0 2006.285.07:47:58.54#ibcon#enter sib2, iclass 18, count 0 2006.285.07:47:58.54#ibcon#flushed, iclass 18, count 0 2006.285.07:47:58.54#ibcon#about to write, iclass 18, count 0 2006.285.07:47:58.54#ibcon#wrote, iclass 18, count 0 2006.285.07:47:58.54#ibcon#about to read 3, iclass 18, count 0 2006.285.07:47:58.56#ibcon#read 3, iclass 18, count 0 2006.285.07:47:58.56#ibcon#about to read 4, iclass 18, count 0 2006.285.07:47:58.56#ibcon#read 4, iclass 18, count 0 2006.285.07:47:58.56#ibcon#about to read 5, iclass 18, count 0 2006.285.07:47:58.56#ibcon#read 5, iclass 18, count 0 2006.285.07:47:58.56#ibcon#about to read 6, iclass 18, count 0 2006.285.07:47:58.56#ibcon#read 6, iclass 18, count 0 2006.285.07:47:58.56#ibcon#end of sib2, iclass 18, count 0 2006.285.07:47:58.56#ibcon#*mode == 0, iclass 18, count 0 2006.285.07:47:58.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.07:47:58.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:47:58.56#ibcon#*before write, iclass 18, count 0 2006.285.07:47:58.56#ibcon#enter sib2, iclass 18, count 0 2006.285.07:47:58.56#ibcon#flushed, iclass 18, count 0 2006.285.07:47:58.56#ibcon#about to write, iclass 18, count 0 2006.285.07:47:58.56#ibcon#wrote, iclass 18, count 0 2006.285.07:47:58.56#ibcon#about to read 3, iclass 18, count 0 2006.285.07:47:58.60#ibcon#read 3, iclass 18, count 0 2006.285.07:47:58.60#ibcon#about to read 4, iclass 18, count 0 2006.285.07:47:58.60#ibcon#read 4, iclass 18, count 0 2006.285.07:47:58.60#ibcon#about to read 5, iclass 18, count 0 2006.285.07:47:58.60#ibcon#read 5, iclass 18, count 0 2006.285.07:47:58.60#ibcon#about to read 6, iclass 18, count 0 2006.285.07:47:58.60#ibcon#read 6, iclass 18, count 0 2006.285.07:47:58.60#ibcon#end of sib2, iclass 18, count 0 2006.285.07:47:58.60#ibcon#*after write, iclass 18, count 0 2006.285.07:47:58.60#ibcon#*before return 0, iclass 18, count 0 2006.285.07:47:58.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:47:58.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:47:58.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.07:47:58.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.07:47:58.60$vck44/va=2,6 2006.285.07:47:58.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.07:47:58.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.07:47:58.60#ibcon#ireg 11 cls_cnt 2 2006.285.07:47:58.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:47:58.64#abcon#<5=/04 2.4 4.4 23.29 781014.4\r\n> 2006.285.07:47:58.66#abcon#{5=INTERFACE CLEAR} 2006.285.07:47:58.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:47:58.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:47:58.66#ibcon#enter wrdev, iclass 21, count 2 2006.285.07:47:58.66#ibcon#first serial, iclass 21, count 2 2006.285.07:47:58.66#ibcon#enter sib2, iclass 21, count 2 2006.285.07:47:58.66#ibcon#flushed, iclass 21, count 2 2006.285.07:47:58.66#ibcon#about to write, iclass 21, count 2 2006.285.07:47:58.66#ibcon#wrote, iclass 21, count 2 2006.285.07:47:58.66#ibcon#about to read 3, iclass 21, count 2 2006.285.07:47:58.68#ibcon#read 3, iclass 21, count 2 2006.285.07:47:58.68#ibcon#about to read 4, iclass 21, count 2 2006.285.07:47:58.68#ibcon#read 4, iclass 21, count 2 2006.285.07:47:58.68#ibcon#about to read 5, iclass 21, count 2 2006.285.07:47:58.68#ibcon#read 5, iclass 21, count 2 2006.285.07:47:58.68#ibcon#about to read 6, iclass 21, count 2 2006.285.07:47:58.68#ibcon#read 6, iclass 21, count 2 2006.285.07:47:58.68#ibcon#end of sib2, iclass 21, count 2 2006.285.07:47:58.68#ibcon#*mode == 0, iclass 21, count 2 2006.285.07:47:58.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.07:47:58.68#ibcon#[25=AT02-06\r\n] 2006.285.07:47:58.68#ibcon#*before write, iclass 21, count 2 2006.285.07:47:58.68#ibcon#enter sib2, iclass 21, count 2 2006.285.07:47:58.68#ibcon#flushed, iclass 21, count 2 2006.285.07:47:58.68#ibcon#about to write, iclass 21, count 2 2006.285.07:47:58.68#ibcon#wrote, iclass 21, count 2 2006.285.07:47:58.68#ibcon#about to read 3, iclass 21, count 2 2006.285.07:47:58.71#ibcon#read 3, iclass 21, count 2 2006.285.07:47:58.71#ibcon#about to read 4, iclass 21, count 2 2006.285.07:47:58.71#ibcon#read 4, iclass 21, count 2 2006.285.07:47:58.71#ibcon#about to read 5, iclass 21, count 2 2006.285.07:47:58.71#ibcon#read 5, iclass 21, count 2 2006.285.07:47:58.71#ibcon#about to read 6, iclass 21, count 2 2006.285.07:47:58.71#ibcon#read 6, iclass 21, count 2 2006.285.07:47:58.71#ibcon#end of sib2, iclass 21, count 2 2006.285.07:47:58.71#ibcon#*after write, iclass 21, count 2 2006.285.07:47:58.71#ibcon#*before return 0, iclass 21, count 2 2006.285.07:47:58.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:47:58.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:47:58.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.07:47:58.71#ibcon#ireg 7 cls_cnt 0 2006.285.07:47:58.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:47:58.72#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:47:58.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:47:58.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:47:58.83#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:47:58.83#ibcon#first serial, iclass 21, count 0 2006.285.07:47:58.83#ibcon#enter sib2, iclass 21, count 0 2006.285.07:47:58.83#ibcon#flushed, iclass 21, count 0 2006.285.07:47:58.83#ibcon#about to write, iclass 21, count 0 2006.285.07:47:58.83#ibcon#wrote, iclass 21, count 0 2006.285.07:47:58.83#ibcon#about to read 3, iclass 21, count 0 2006.285.07:47:58.85#ibcon#read 3, iclass 21, count 0 2006.285.07:47:58.85#ibcon#about to read 4, iclass 21, count 0 2006.285.07:47:58.85#ibcon#read 4, iclass 21, count 0 2006.285.07:47:58.85#ibcon#about to read 5, iclass 21, count 0 2006.285.07:47:58.85#ibcon#read 5, iclass 21, count 0 2006.285.07:47:58.85#ibcon#about to read 6, iclass 21, count 0 2006.285.07:47:58.85#ibcon#read 6, iclass 21, count 0 2006.285.07:47:58.85#ibcon#end of sib2, iclass 21, count 0 2006.285.07:47:58.85#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:47:58.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:47:58.85#ibcon#[25=USB\r\n] 2006.285.07:47:58.85#ibcon#*before write, iclass 21, count 0 2006.285.07:47:58.85#ibcon#enter sib2, iclass 21, count 0 2006.285.07:47:58.85#ibcon#flushed, iclass 21, count 0 2006.285.07:47:58.85#ibcon#about to write, iclass 21, count 0 2006.285.07:47:58.85#ibcon#wrote, iclass 21, count 0 2006.285.07:47:58.85#ibcon#about to read 3, iclass 21, count 0 2006.285.07:47:58.88#ibcon#read 3, iclass 21, count 0 2006.285.07:47:58.88#ibcon#about to read 4, iclass 21, count 0 2006.285.07:47:58.88#ibcon#read 4, iclass 21, count 0 2006.285.07:47:58.88#ibcon#about to read 5, iclass 21, count 0 2006.285.07:47:58.88#ibcon#read 5, iclass 21, count 0 2006.285.07:47:58.88#ibcon#about to read 6, iclass 21, count 0 2006.285.07:47:58.88#ibcon#read 6, iclass 21, count 0 2006.285.07:47:58.88#ibcon#end of sib2, iclass 21, count 0 2006.285.07:47:58.88#ibcon#*after write, iclass 21, count 0 2006.285.07:47:58.88#ibcon#*before return 0, iclass 21, count 0 2006.285.07:47:58.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:47:58.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:47:58.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:47:58.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:47:58.88$vck44/valo=3,564.99 2006.285.07:47:58.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.07:47:58.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.07:47:58.88#ibcon#ireg 17 cls_cnt 0 2006.285.07:47:58.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:47:58.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:47:58.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:47:58.88#ibcon#enter wrdev, iclass 26, count 0 2006.285.07:47:58.88#ibcon#first serial, iclass 26, count 0 2006.285.07:47:58.88#ibcon#enter sib2, iclass 26, count 0 2006.285.07:47:58.88#ibcon#flushed, iclass 26, count 0 2006.285.07:47:58.88#ibcon#about to write, iclass 26, count 0 2006.285.07:47:58.88#ibcon#wrote, iclass 26, count 0 2006.285.07:47:58.88#ibcon#about to read 3, iclass 26, count 0 2006.285.07:47:58.90#ibcon#read 3, iclass 26, count 0 2006.285.07:47:58.90#ibcon#about to read 4, iclass 26, count 0 2006.285.07:47:58.90#ibcon#read 4, iclass 26, count 0 2006.285.07:47:58.90#ibcon#about to read 5, iclass 26, count 0 2006.285.07:47:58.90#ibcon#read 5, iclass 26, count 0 2006.285.07:47:58.90#ibcon#about to read 6, iclass 26, count 0 2006.285.07:47:58.90#ibcon#read 6, iclass 26, count 0 2006.285.07:47:58.90#ibcon#end of sib2, iclass 26, count 0 2006.285.07:47:58.90#ibcon#*mode == 0, iclass 26, count 0 2006.285.07:47:58.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.07:47:58.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:47:58.90#ibcon#*before write, iclass 26, count 0 2006.285.07:47:58.90#ibcon#enter sib2, iclass 26, count 0 2006.285.07:47:58.90#ibcon#flushed, iclass 26, count 0 2006.285.07:47:58.90#ibcon#about to write, iclass 26, count 0 2006.285.07:47:58.90#ibcon#wrote, iclass 26, count 0 2006.285.07:47:58.90#ibcon#about to read 3, iclass 26, count 0 2006.285.07:47:58.94#ibcon#read 3, iclass 26, count 0 2006.285.07:47:58.94#ibcon#about to read 4, iclass 26, count 0 2006.285.07:47:58.94#ibcon#read 4, iclass 26, count 0 2006.285.07:47:58.94#ibcon#about to read 5, iclass 26, count 0 2006.285.07:47:58.94#ibcon#read 5, iclass 26, count 0 2006.285.07:47:58.94#ibcon#about to read 6, iclass 26, count 0 2006.285.07:47:58.94#ibcon#read 6, iclass 26, count 0 2006.285.07:47:58.94#ibcon#end of sib2, iclass 26, count 0 2006.285.07:47:58.94#ibcon#*after write, iclass 26, count 0 2006.285.07:47:58.94#ibcon#*before return 0, iclass 26, count 0 2006.285.07:47:58.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:47:58.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:47:58.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.07:47:58.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.07:47:58.94$vck44/va=3,7 2006.285.07:47:58.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.07:47:58.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.07:47:58.94#ibcon#ireg 11 cls_cnt 2 2006.285.07:47:58.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:47:59.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:47:59.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:47:59.00#ibcon#enter wrdev, iclass 28, count 2 2006.285.07:47:59.00#ibcon#first serial, iclass 28, count 2 2006.285.07:47:59.00#ibcon#enter sib2, iclass 28, count 2 2006.285.07:47:59.00#ibcon#flushed, iclass 28, count 2 2006.285.07:47:59.00#ibcon#about to write, iclass 28, count 2 2006.285.07:47:59.00#ibcon#wrote, iclass 28, count 2 2006.285.07:47:59.00#ibcon#about to read 3, iclass 28, count 2 2006.285.07:47:59.02#ibcon#read 3, iclass 28, count 2 2006.285.07:47:59.02#ibcon#about to read 4, iclass 28, count 2 2006.285.07:47:59.02#ibcon#read 4, iclass 28, count 2 2006.285.07:47:59.02#ibcon#about to read 5, iclass 28, count 2 2006.285.07:47:59.02#ibcon#read 5, iclass 28, count 2 2006.285.07:47:59.02#ibcon#about to read 6, iclass 28, count 2 2006.285.07:47:59.02#ibcon#read 6, iclass 28, count 2 2006.285.07:47:59.02#ibcon#end of sib2, iclass 28, count 2 2006.285.07:47:59.02#ibcon#*mode == 0, iclass 28, count 2 2006.285.07:47:59.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.07:47:59.02#ibcon#[25=AT03-07\r\n] 2006.285.07:47:59.02#ibcon#*before write, iclass 28, count 2 2006.285.07:47:59.02#ibcon#enter sib2, iclass 28, count 2 2006.285.07:47:59.02#ibcon#flushed, iclass 28, count 2 2006.285.07:47:59.02#ibcon#about to write, iclass 28, count 2 2006.285.07:47:59.02#ibcon#wrote, iclass 28, count 2 2006.285.07:47:59.02#ibcon#about to read 3, iclass 28, count 2 2006.285.07:47:59.05#ibcon#read 3, iclass 28, count 2 2006.285.07:47:59.05#ibcon#about to read 4, iclass 28, count 2 2006.285.07:47:59.05#ibcon#read 4, iclass 28, count 2 2006.285.07:47:59.05#ibcon#about to read 5, iclass 28, count 2 2006.285.07:47:59.05#ibcon#read 5, iclass 28, count 2 2006.285.07:47:59.05#ibcon#about to read 6, iclass 28, count 2 2006.285.07:47:59.05#ibcon#read 6, iclass 28, count 2 2006.285.07:47:59.05#ibcon#end of sib2, iclass 28, count 2 2006.285.07:47:59.05#ibcon#*after write, iclass 28, count 2 2006.285.07:47:59.05#ibcon#*before return 0, iclass 28, count 2 2006.285.07:47:59.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:47:59.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:47:59.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.07:47:59.05#ibcon#ireg 7 cls_cnt 0 2006.285.07:47:59.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:47:59.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:47:59.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:47:59.17#ibcon#enter wrdev, iclass 28, count 0 2006.285.07:47:59.17#ibcon#first serial, iclass 28, count 0 2006.285.07:47:59.17#ibcon#enter sib2, iclass 28, count 0 2006.285.07:47:59.17#ibcon#flushed, iclass 28, count 0 2006.285.07:47:59.17#ibcon#about to write, iclass 28, count 0 2006.285.07:47:59.17#ibcon#wrote, iclass 28, count 0 2006.285.07:47:59.17#ibcon#about to read 3, iclass 28, count 0 2006.285.07:47:59.19#ibcon#read 3, iclass 28, count 0 2006.285.07:47:59.19#ibcon#about to read 4, iclass 28, count 0 2006.285.07:47:59.19#ibcon#read 4, iclass 28, count 0 2006.285.07:47:59.19#ibcon#about to read 5, iclass 28, count 0 2006.285.07:47:59.19#ibcon#read 5, iclass 28, count 0 2006.285.07:47:59.19#ibcon#about to read 6, iclass 28, count 0 2006.285.07:47:59.19#ibcon#read 6, iclass 28, count 0 2006.285.07:47:59.19#ibcon#end of sib2, iclass 28, count 0 2006.285.07:47:59.19#ibcon#*mode == 0, iclass 28, count 0 2006.285.07:47:59.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.07:47:59.19#ibcon#[25=USB\r\n] 2006.285.07:47:59.19#ibcon#*before write, iclass 28, count 0 2006.285.07:47:59.19#ibcon#enter sib2, iclass 28, count 0 2006.285.07:47:59.19#ibcon#flushed, iclass 28, count 0 2006.285.07:47:59.19#ibcon#about to write, iclass 28, count 0 2006.285.07:47:59.19#ibcon#wrote, iclass 28, count 0 2006.285.07:47:59.19#ibcon#about to read 3, iclass 28, count 0 2006.285.07:47:59.22#ibcon#read 3, iclass 28, count 0 2006.285.07:47:59.22#ibcon#about to read 4, iclass 28, count 0 2006.285.07:47:59.22#ibcon#read 4, iclass 28, count 0 2006.285.07:47:59.22#ibcon#about to read 5, iclass 28, count 0 2006.285.07:47:59.22#ibcon#read 5, iclass 28, count 0 2006.285.07:47:59.22#ibcon#about to read 6, iclass 28, count 0 2006.285.07:47:59.22#ibcon#read 6, iclass 28, count 0 2006.285.07:47:59.22#ibcon#end of sib2, iclass 28, count 0 2006.285.07:47:59.22#ibcon#*after write, iclass 28, count 0 2006.285.07:47:59.22#ibcon#*before return 0, iclass 28, count 0 2006.285.07:47:59.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:47:59.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:47:59.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.07:47:59.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.07:47:59.22$vck44/valo=4,624.99 2006.285.07:47:59.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.07:47:59.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.07:47:59.22#ibcon#ireg 17 cls_cnt 0 2006.285.07:47:59.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:47:59.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:47:59.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:47:59.22#ibcon#enter wrdev, iclass 30, count 0 2006.285.07:47:59.22#ibcon#first serial, iclass 30, count 0 2006.285.07:47:59.22#ibcon#enter sib2, iclass 30, count 0 2006.285.07:47:59.22#ibcon#flushed, iclass 30, count 0 2006.285.07:47:59.22#ibcon#about to write, iclass 30, count 0 2006.285.07:47:59.22#ibcon#wrote, iclass 30, count 0 2006.285.07:47:59.22#ibcon#about to read 3, iclass 30, count 0 2006.285.07:47:59.24#ibcon#read 3, iclass 30, count 0 2006.285.07:47:59.24#ibcon#about to read 4, iclass 30, count 0 2006.285.07:47:59.24#ibcon#read 4, iclass 30, count 0 2006.285.07:47:59.24#ibcon#about to read 5, iclass 30, count 0 2006.285.07:47:59.24#ibcon#read 5, iclass 30, count 0 2006.285.07:47:59.24#ibcon#about to read 6, iclass 30, count 0 2006.285.07:47:59.24#ibcon#read 6, iclass 30, count 0 2006.285.07:47:59.24#ibcon#end of sib2, iclass 30, count 0 2006.285.07:47:59.24#ibcon#*mode == 0, iclass 30, count 0 2006.285.07:47:59.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.07:47:59.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:47:59.24#ibcon#*before write, iclass 30, count 0 2006.285.07:47:59.24#ibcon#enter sib2, iclass 30, count 0 2006.285.07:47:59.24#ibcon#flushed, iclass 30, count 0 2006.285.07:47:59.24#ibcon#about to write, iclass 30, count 0 2006.285.07:47:59.24#ibcon#wrote, iclass 30, count 0 2006.285.07:47:59.24#ibcon#about to read 3, iclass 30, count 0 2006.285.07:47:59.28#ibcon#read 3, iclass 30, count 0 2006.285.07:47:59.28#ibcon#about to read 4, iclass 30, count 0 2006.285.07:47:59.28#ibcon#read 4, iclass 30, count 0 2006.285.07:47:59.28#ibcon#about to read 5, iclass 30, count 0 2006.285.07:47:59.28#ibcon#read 5, iclass 30, count 0 2006.285.07:47:59.28#ibcon#about to read 6, iclass 30, count 0 2006.285.07:47:59.28#ibcon#read 6, iclass 30, count 0 2006.285.07:47:59.28#ibcon#end of sib2, iclass 30, count 0 2006.285.07:47:59.28#ibcon#*after write, iclass 30, count 0 2006.285.07:47:59.28#ibcon#*before return 0, iclass 30, count 0 2006.285.07:47:59.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:47:59.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:47:59.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.07:47:59.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.07:47:59.28$vck44/va=4,6 2006.285.07:47:59.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.07:47:59.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.07:47:59.28#ibcon#ireg 11 cls_cnt 2 2006.285.07:47:59.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:47:59.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:47:59.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:47:59.34#ibcon#enter wrdev, iclass 32, count 2 2006.285.07:47:59.34#ibcon#first serial, iclass 32, count 2 2006.285.07:47:59.34#ibcon#enter sib2, iclass 32, count 2 2006.285.07:47:59.34#ibcon#flushed, iclass 32, count 2 2006.285.07:47:59.34#ibcon#about to write, iclass 32, count 2 2006.285.07:47:59.34#ibcon#wrote, iclass 32, count 2 2006.285.07:47:59.34#ibcon#about to read 3, iclass 32, count 2 2006.285.07:47:59.36#ibcon#read 3, iclass 32, count 2 2006.285.07:47:59.36#ibcon#about to read 4, iclass 32, count 2 2006.285.07:47:59.36#ibcon#read 4, iclass 32, count 2 2006.285.07:47:59.36#ibcon#about to read 5, iclass 32, count 2 2006.285.07:47:59.36#ibcon#read 5, iclass 32, count 2 2006.285.07:47:59.36#ibcon#about to read 6, iclass 32, count 2 2006.285.07:47:59.36#ibcon#read 6, iclass 32, count 2 2006.285.07:47:59.36#ibcon#end of sib2, iclass 32, count 2 2006.285.07:47:59.36#ibcon#*mode == 0, iclass 32, count 2 2006.285.07:47:59.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.07:47:59.36#ibcon#[25=AT04-06\r\n] 2006.285.07:47:59.36#ibcon#*before write, iclass 32, count 2 2006.285.07:47:59.36#ibcon#enter sib2, iclass 32, count 2 2006.285.07:47:59.36#ibcon#flushed, iclass 32, count 2 2006.285.07:47:59.36#ibcon#about to write, iclass 32, count 2 2006.285.07:47:59.36#ibcon#wrote, iclass 32, count 2 2006.285.07:47:59.36#ibcon#about to read 3, iclass 32, count 2 2006.285.07:47:59.39#ibcon#read 3, iclass 32, count 2 2006.285.07:47:59.39#ibcon#about to read 4, iclass 32, count 2 2006.285.07:47:59.39#ibcon#read 4, iclass 32, count 2 2006.285.07:47:59.39#ibcon#about to read 5, iclass 32, count 2 2006.285.07:47:59.39#ibcon#read 5, iclass 32, count 2 2006.285.07:47:59.39#ibcon#about to read 6, iclass 32, count 2 2006.285.07:47:59.39#ibcon#read 6, iclass 32, count 2 2006.285.07:47:59.39#ibcon#end of sib2, iclass 32, count 2 2006.285.07:47:59.39#ibcon#*after write, iclass 32, count 2 2006.285.07:47:59.39#ibcon#*before return 0, iclass 32, count 2 2006.285.07:47:59.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:47:59.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:47:59.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.07:47:59.39#ibcon#ireg 7 cls_cnt 0 2006.285.07:47:59.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:47:59.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:47:59.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:47:59.51#ibcon#enter wrdev, iclass 32, count 0 2006.285.07:47:59.51#ibcon#first serial, iclass 32, count 0 2006.285.07:47:59.51#ibcon#enter sib2, iclass 32, count 0 2006.285.07:47:59.51#ibcon#flushed, iclass 32, count 0 2006.285.07:47:59.51#ibcon#about to write, iclass 32, count 0 2006.285.07:47:59.51#ibcon#wrote, iclass 32, count 0 2006.285.07:47:59.51#ibcon#about to read 3, iclass 32, count 0 2006.285.07:47:59.53#ibcon#read 3, iclass 32, count 0 2006.285.07:47:59.53#ibcon#about to read 4, iclass 32, count 0 2006.285.07:47:59.53#ibcon#read 4, iclass 32, count 0 2006.285.07:47:59.53#ibcon#about to read 5, iclass 32, count 0 2006.285.07:47:59.53#ibcon#read 5, iclass 32, count 0 2006.285.07:47:59.53#ibcon#about to read 6, iclass 32, count 0 2006.285.07:47:59.53#ibcon#read 6, iclass 32, count 0 2006.285.07:47:59.53#ibcon#end of sib2, iclass 32, count 0 2006.285.07:47:59.53#ibcon#*mode == 0, iclass 32, count 0 2006.285.07:47:59.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.07:47:59.53#ibcon#[25=USB\r\n] 2006.285.07:47:59.53#ibcon#*before write, iclass 32, count 0 2006.285.07:47:59.53#ibcon#enter sib2, iclass 32, count 0 2006.285.07:47:59.53#ibcon#flushed, iclass 32, count 0 2006.285.07:47:59.53#ibcon#about to write, iclass 32, count 0 2006.285.07:47:59.53#ibcon#wrote, iclass 32, count 0 2006.285.07:47:59.53#ibcon#about to read 3, iclass 32, count 0 2006.285.07:47:59.56#ibcon#read 3, iclass 32, count 0 2006.285.07:47:59.56#ibcon#about to read 4, iclass 32, count 0 2006.285.07:47:59.56#ibcon#read 4, iclass 32, count 0 2006.285.07:47:59.56#ibcon#about to read 5, iclass 32, count 0 2006.285.07:47:59.56#ibcon#read 5, iclass 32, count 0 2006.285.07:47:59.56#ibcon#about to read 6, iclass 32, count 0 2006.285.07:47:59.56#ibcon#read 6, iclass 32, count 0 2006.285.07:47:59.56#ibcon#end of sib2, iclass 32, count 0 2006.285.07:47:59.56#ibcon#*after write, iclass 32, count 0 2006.285.07:47:59.56#ibcon#*before return 0, iclass 32, count 0 2006.285.07:47:59.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:47:59.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:47:59.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.07:47:59.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.07:47:59.56$vck44/valo=5,734.99 2006.285.07:47:59.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.07:47:59.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.07:47:59.56#ibcon#ireg 17 cls_cnt 0 2006.285.07:47:59.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:47:59.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:47:59.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:47:59.56#ibcon#enter wrdev, iclass 34, count 0 2006.285.07:47:59.56#ibcon#first serial, iclass 34, count 0 2006.285.07:47:59.56#ibcon#enter sib2, iclass 34, count 0 2006.285.07:47:59.56#ibcon#flushed, iclass 34, count 0 2006.285.07:47:59.56#ibcon#about to write, iclass 34, count 0 2006.285.07:47:59.56#ibcon#wrote, iclass 34, count 0 2006.285.07:47:59.56#ibcon#about to read 3, iclass 34, count 0 2006.285.07:47:59.58#ibcon#read 3, iclass 34, count 0 2006.285.07:47:59.58#ibcon#about to read 4, iclass 34, count 0 2006.285.07:47:59.58#ibcon#read 4, iclass 34, count 0 2006.285.07:47:59.58#ibcon#about to read 5, iclass 34, count 0 2006.285.07:47:59.58#ibcon#read 5, iclass 34, count 0 2006.285.07:47:59.58#ibcon#about to read 6, iclass 34, count 0 2006.285.07:47:59.58#ibcon#read 6, iclass 34, count 0 2006.285.07:47:59.58#ibcon#end of sib2, iclass 34, count 0 2006.285.07:47:59.58#ibcon#*mode == 0, iclass 34, count 0 2006.285.07:47:59.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.07:47:59.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:47:59.58#ibcon#*before write, iclass 34, count 0 2006.285.07:47:59.58#ibcon#enter sib2, iclass 34, count 0 2006.285.07:47:59.58#ibcon#flushed, iclass 34, count 0 2006.285.07:47:59.58#ibcon#about to write, iclass 34, count 0 2006.285.07:47:59.58#ibcon#wrote, iclass 34, count 0 2006.285.07:47:59.58#ibcon#about to read 3, iclass 34, count 0 2006.285.07:47:59.62#ibcon#read 3, iclass 34, count 0 2006.285.07:47:59.62#ibcon#about to read 4, iclass 34, count 0 2006.285.07:47:59.62#ibcon#read 4, iclass 34, count 0 2006.285.07:47:59.62#ibcon#about to read 5, iclass 34, count 0 2006.285.07:47:59.62#ibcon#read 5, iclass 34, count 0 2006.285.07:47:59.62#ibcon#about to read 6, iclass 34, count 0 2006.285.07:47:59.62#ibcon#read 6, iclass 34, count 0 2006.285.07:47:59.62#ibcon#end of sib2, iclass 34, count 0 2006.285.07:47:59.62#ibcon#*after write, iclass 34, count 0 2006.285.07:47:59.62#ibcon#*before return 0, iclass 34, count 0 2006.285.07:47:59.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:47:59.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:47:59.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.07:47:59.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.07:47:59.62$vck44/va=5,3 2006.285.07:47:59.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.07:47:59.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.07:47:59.62#ibcon#ireg 11 cls_cnt 2 2006.285.07:47:59.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:47:59.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:47:59.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:47:59.68#ibcon#enter wrdev, iclass 36, count 2 2006.285.07:47:59.68#ibcon#first serial, iclass 36, count 2 2006.285.07:47:59.68#ibcon#enter sib2, iclass 36, count 2 2006.285.07:47:59.68#ibcon#flushed, iclass 36, count 2 2006.285.07:47:59.68#ibcon#about to write, iclass 36, count 2 2006.285.07:47:59.68#ibcon#wrote, iclass 36, count 2 2006.285.07:47:59.68#ibcon#about to read 3, iclass 36, count 2 2006.285.07:47:59.70#ibcon#read 3, iclass 36, count 2 2006.285.07:47:59.70#ibcon#about to read 4, iclass 36, count 2 2006.285.07:47:59.70#ibcon#read 4, iclass 36, count 2 2006.285.07:47:59.70#ibcon#about to read 5, iclass 36, count 2 2006.285.07:47:59.70#ibcon#read 5, iclass 36, count 2 2006.285.07:47:59.70#ibcon#about to read 6, iclass 36, count 2 2006.285.07:47:59.70#ibcon#read 6, iclass 36, count 2 2006.285.07:47:59.70#ibcon#end of sib2, iclass 36, count 2 2006.285.07:47:59.70#ibcon#*mode == 0, iclass 36, count 2 2006.285.07:47:59.70#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.07:47:59.70#ibcon#[25=AT05-03\r\n] 2006.285.07:47:59.70#ibcon#*before write, iclass 36, count 2 2006.285.07:47:59.70#ibcon#enter sib2, iclass 36, count 2 2006.285.07:47:59.70#ibcon#flushed, iclass 36, count 2 2006.285.07:47:59.70#ibcon#about to write, iclass 36, count 2 2006.285.07:47:59.70#ibcon#wrote, iclass 36, count 2 2006.285.07:47:59.70#ibcon#about to read 3, iclass 36, count 2 2006.285.07:47:59.73#ibcon#read 3, iclass 36, count 2 2006.285.07:47:59.73#ibcon#about to read 4, iclass 36, count 2 2006.285.07:47:59.73#ibcon#read 4, iclass 36, count 2 2006.285.07:47:59.73#ibcon#about to read 5, iclass 36, count 2 2006.285.07:47:59.73#ibcon#read 5, iclass 36, count 2 2006.285.07:47:59.73#ibcon#about to read 6, iclass 36, count 2 2006.285.07:47:59.73#ibcon#read 6, iclass 36, count 2 2006.285.07:47:59.73#ibcon#end of sib2, iclass 36, count 2 2006.285.07:47:59.73#ibcon#*after write, iclass 36, count 2 2006.285.07:47:59.73#ibcon#*before return 0, iclass 36, count 2 2006.285.07:47:59.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:47:59.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:47:59.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.07:47:59.73#ibcon#ireg 7 cls_cnt 0 2006.285.07:47:59.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:47:59.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:47:59.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:47:59.85#ibcon#enter wrdev, iclass 36, count 0 2006.285.07:47:59.85#ibcon#first serial, iclass 36, count 0 2006.285.07:47:59.85#ibcon#enter sib2, iclass 36, count 0 2006.285.07:47:59.85#ibcon#flushed, iclass 36, count 0 2006.285.07:47:59.85#ibcon#about to write, iclass 36, count 0 2006.285.07:47:59.85#ibcon#wrote, iclass 36, count 0 2006.285.07:47:59.85#ibcon#about to read 3, iclass 36, count 0 2006.285.07:47:59.87#ibcon#read 3, iclass 36, count 0 2006.285.07:47:59.87#ibcon#about to read 4, iclass 36, count 0 2006.285.07:47:59.87#ibcon#read 4, iclass 36, count 0 2006.285.07:47:59.87#ibcon#about to read 5, iclass 36, count 0 2006.285.07:47:59.87#ibcon#read 5, iclass 36, count 0 2006.285.07:47:59.87#ibcon#about to read 6, iclass 36, count 0 2006.285.07:47:59.87#ibcon#read 6, iclass 36, count 0 2006.285.07:47:59.87#ibcon#end of sib2, iclass 36, count 0 2006.285.07:47:59.87#ibcon#*mode == 0, iclass 36, count 0 2006.285.07:47:59.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.07:47:59.87#ibcon#[25=USB\r\n] 2006.285.07:47:59.87#ibcon#*before write, iclass 36, count 0 2006.285.07:47:59.87#ibcon#enter sib2, iclass 36, count 0 2006.285.07:47:59.87#ibcon#flushed, iclass 36, count 0 2006.285.07:47:59.87#ibcon#about to write, iclass 36, count 0 2006.285.07:47:59.87#ibcon#wrote, iclass 36, count 0 2006.285.07:47:59.87#ibcon#about to read 3, iclass 36, count 0 2006.285.07:47:59.90#ibcon#read 3, iclass 36, count 0 2006.285.07:47:59.90#ibcon#about to read 4, iclass 36, count 0 2006.285.07:47:59.90#ibcon#read 4, iclass 36, count 0 2006.285.07:47:59.90#ibcon#about to read 5, iclass 36, count 0 2006.285.07:47:59.90#ibcon#read 5, iclass 36, count 0 2006.285.07:47:59.90#ibcon#about to read 6, iclass 36, count 0 2006.285.07:47:59.90#ibcon#read 6, iclass 36, count 0 2006.285.07:47:59.90#ibcon#end of sib2, iclass 36, count 0 2006.285.07:47:59.90#ibcon#*after write, iclass 36, count 0 2006.285.07:47:59.90#ibcon#*before return 0, iclass 36, count 0 2006.285.07:47:59.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:47:59.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:47:59.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.07:47:59.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.07:47:59.90$vck44/valo=6,814.99 2006.285.07:47:59.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.07:47:59.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.07:47:59.90#ibcon#ireg 17 cls_cnt 0 2006.285.07:47:59.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:47:59.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:47:59.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:47:59.90#ibcon#enter wrdev, iclass 38, count 0 2006.285.07:47:59.90#ibcon#first serial, iclass 38, count 0 2006.285.07:47:59.90#ibcon#enter sib2, iclass 38, count 0 2006.285.07:47:59.90#ibcon#flushed, iclass 38, count 0 2006.285.07:47:59.90#ibcon#about to write, iclass 38, count 0 2006.285.07:47:59.90#ibcon#wrote, iclass 38, count 0 2006.285.07:47:59.90#ibcon#about to read 3, iclass 38, count 0 2006.285.07:47:59.92#ibcon#read 3, iclass 38, count 0 2006.285.07:47:59.92#ibcon#about to read 4, iclass 38, count 0 2006.285.07:47:59.92#ibcon#read 4, iclass 38, count 0 2006.285.07:47:59.92#ibcon#about to read 5, iclass 38, count 0 2006.285.07:47:59.92#ibcon#read 5, iclass 38, count 0 2006.285.07:47:59.92#ibcon#about to read 6, iclass 38, count 0 2006.285.07:47:59.92#ibcon#read 6, iclass 38, count 0 2006.285.07:47:59.92#ibcon#end of sib2, iclass 38, count 0 2006.285.07:47:59.92#ibcon#*mode == 0, iclass 38, count 0 2006.285.07:47:59.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.07:47:59.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:47:59.92#ibcon#*before write, iclass 38, count 0 2006.285.07:47:59.92#ibcon#enter sib2, iclass 38, count 0 2006.285.07:47:59.92#ibcon#flushed, iclass 38, count 0 2006.285.07:47:59.92#ibcon#about to write, iclass 38, count 0 2006.285.07:47:59.92#ibcon#wrote, iclass 38, count 0 2006.285.07:47:59.92#ibcon#about to read 3, iclass 38, count 0 2006.285.07:47:59.96#ibcon#read 3, iclass 38, count 0 2006.285.07:47:59.96#ibcon#about to read 4, iclass 38, count 0 2006.285.07:47:59.96#ibcon#read 4, iclass 38, count 0 2006.285.07:47:59.96#ibcon#about to read 5, iclass 38, count 0 2006.285.07:47:59.96#ibcon#read 5, iclass 38, count 0 2006.285.07:47:59.96#ibcon#about to read 6, iclass 38, count 0 2006.285.07:47:59.96#ibcon#read 6, iclass 38, count 0 2006.285.07:47:59.96#ibcon#end of sib2, iclass 38, count 0 2006.285.07:47:59.96#ibcon#*after write, iclass 38, count 0 2006.285.07:47:59.96#ibcon#*before return 0, iclass 38, count 0 2006.285.07:47:59.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:47:59.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:47:59.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.07:47:59.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.07:47:59.96$vck44/va=6,4 2006.285.07:47:59.96#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.07:47:59.96#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.07:47:59.96#ibcon#ireg 11 cls_cnt 2 2006.285.07:47:59.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:48:00.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:48:00.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:48:00.02#ibcon#enter wrdev, iclass 40, count 2 2006.285.07:48:00.02#ibcon#first serial, iclass 40, count 2 2006.285.07:48:00.02#ibcon#enter sib2, iclass 40, count 2 2006.285.07:48:00.02#ibcon#flushed, iclass 40, count 2 2006.285.07:48:00.02#ibcon#about to write, iclass 40, count 2 2006.285.07:48:00.02#ibcon#wrote, iclass 40, count 2 2006.285.07:48:00.02#ibcon#about to read 3, iclass 40, count 2 2006.285.07:48:00.04#ibcon#read 3, iclass 40, count 2 2006.285.07:48:00.04#ibcon#about to read 4, iclass 40, count 2 2006.285.07:48:00.04#ibcon#read 4, iclass 40, count 2 2006.285.07:48:00.04#ibcon#about to read 5, iclass 40, count 2 2006.285.07:48:00.04#ibcon#read 5, iclass 40, count 2 2006.285.07:48:00.04#ibcon#about to read 6, iclass 40, count 2 2006.285.07:48:00.04#ibcon#read 6, iclass 40, count 2 2006.285.07:48:00.04#ibcon#end of sib2, iclass 40, count 2 2006.285.07:48:00.04#ibcon#*mode == 0, iclass 40, count 2 2006.285.07:48:00.04#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.07:48:00.04#ibcon#[25=AT06-04\r\n] 2006.285.07:48:00.04#ibcon#*before write, iclass 40, count 2 2006.285.07:48:00.04#ibcon#enter sib2, iclass 40, count 2 2006.285.07:48:00.04#ibcon#flushed, iclass 40, count 2 2006.285.07:48:00.04#ibcon#about to write, iclass 40, count 2 2006.285.07:48:00.04#ibcon#wrote, iclass 40, count 2 2006.285.07:48:00.04#ibcon#about to read 3, iclass 40, count 2 2006.285.07:48:00.07#ibcon#read 3, iclass 40, count 2 2006.285.07:48:00.07#ibcon#about to read 4, iclass 40, count 2 2006.285.07:48:00.07#ibcon#read 4, iclass 40, count 2 2006.285.07:48:00.07#ibcon#about to read 5, iclass 40, count 2 2006.285.07:48:00.07#ibcon#read 5, iclass 40, count 2 2006.285.07:48:00.07#ibcon#about to read 6, iclass 40, count 2 2006.285.07:48:00.07#ibcon#read 6, iclass 40, count 2 2006.285.07:48:00.07#ibcon#end of sib2, iclass 40, count 2 2006.285.07:48:00.07#ibcon#*after write, iclass 40, count 2 2006.285.07:48:00.07#ibcon#*before return 0, iclass 40, count 2 2006.285.07:48:00.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:48:00.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:48:00.07#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.07:48:00.07#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:00.07#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:48:00.19#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:48:00.19#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:48:00.19#ibcon#enter wrdev, iclass 40, count 0 2006.285.07:48:00.19#ibcon#first serial, iclass 40, count 0 2006.285.07:48:00.19#ibcon#enter sib2, iclass 40, count 0 2006.285.07:48:00.19#ibcon#flushed, iclass 40, count 0 2006.285.07:48:00.19#ibcon#about to write, iclass 40, count 0 2006.285.07:48:00.19#ibcon#wrote, iclass 40, count 0 2006.285.07:48:00.19#ibcon#about to read 3, iclass 40, count 0 2006.285.07:48:00.21#ibcon#read 3, iclass 40, count 0 2006.285.07:48:00.21#ibcon#about to read 4, iclass 40, count 0 2006.285.07:48:00.21#ibcon#read 4, iclass 40, count 0 2006.285.07:48:00.21#ibcon#about to read 5, iclass 40, count 0 2006.285.07:48:00.21#ibcon#read 5, iclass 40, count 0 2006.285.07:48:00.21#ibcon#about to read 6, iclass 40, count 0 2006.285.07:48:00.21#ibcon#read 6, iclass 40, count 0 2006.285.07:48:00.21#ibcon#end of sib2, iclass 40, count 0 2006.285.07:48:00.21#ibcon#*mode == 0, iclass 40, count 0 2006.285.07:48:00.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.07:48:00.21#ibcon#[25=USB\r\n] 2006.285.07:48:00.21#ibcon#*before write, iclass 40, count 0 2006.285.07:48:00.21#ibcon#enter sib2, iclass 40, count 0 2006.285.07:48:00.21#ibcon#flushed, iclass 40, count 0 2006.285.07:48:00.21#ibcon#about to write, iclass 40, count 0 2006.285.07:48:00.21#ibcon#wrote, iclass 40, count 0 2006.285.07:48:00.21#ibcon#about to read 3, iclass 40, count 0 2006.285.07:48:00.24#ibcon#read 3, iclass 40, count 0 2006.285.07:48:00.24#ibcon#about to read 4, iclass 40, count 0 2006.285.07:48:00.24#ibcon#read 4, iclass 40, count 0 2006.285.07:48:00.24#ibcon#about to read 5, iclass 40, count 0 2006.285.07:48:00.24#ibcon#read 5, iclass 40, count 0 2006.285.07:48:00.24#ibcon#about to read 6, iclass 40, count 0 2006.285.07:48:00.24#ibcon#read 6, iclass 40, count 0 2006.285.07:48:00.24#ibcon#end of sib2, iclass 40, count 0 2006.285.07:48:00.24#ibcon#*after write, iclass 40, count 0 2006.285.07:48:00.24#ibcon#*before return 0, iclass 40, count 0 2006.285.07:48:00.24#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:48:00.24#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:48:00.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.07:48:00.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.07:48:00.24$vck44/valo=7,864.99 2006.285.07:48:00.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.07:48:00.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.07:48:00.24#ibcon#ireg 17 cls_cnt 0 2006.285.07:48:00.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:48:00.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:48:00.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:48:00.24#ibcon#enter wrdev, iclass 4, count 0 2006.285.07:48:00.24#ibcon#first serial, iclass 4, count 0 2006.285.07:48:00.24#ibcon#enter sib2, iclass 4, count 0 2006.285.07:48:00.24#ibcon#flushed, iclass 4, count 0 2006.285.07:48:00.24#ibcon#about to write, iclass 4, count 0 2006.285.07:48:00.24#ibcon#wrote, iclass 4, count 0 2006.285.07:48:00.24#ibcon#about to read 3, iclass 4, count 0 2006.285.07:48:00.26#ibcon#read 3, iclass 4, count 0 2006.285.07:48:00.26#ibcon#about to read 4, iclass 4, count 0 2006.285.07:48:00.26#ibcon#read 4, iclass 4, count 0 2006.285.07:48:00.26#ibcon#about to read 5, iclass 4, count 0 2006.285.07:48:00.26#ibcon#read 5, iclass 4, count 0 2006.285.07:48:00.26#ibcon#about to read 6, iclass 4, count 0 2006.285.07:48:00.26#ibcon#read 6, iclass 4, count 0 2006.285.07:48:00.26#ibcon#end of sib2, iclass 4, count 0 2006.285.07:48:00.26#ibcon#*mode == 0, iclass 4, count 0 2006.285.07:48:00.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.07:48:00.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:48:00.26#ibcon#*before write, iclass 4, count 0 2006.285.07:48:00.26#ibcon#enter sib2, iclass 4, count 0 2006.285.07:48:00.26#ibcon#flushed, iclass 4, count 0 2006.285.07:48:00.26#ibcon#about to write, iclass 4, count 0 2006.285.07:48:00.26#ibcon#wrote, iclass 4, count 0 2006.285.07:48:00.26#ibcon#about to read 3, iclass 4, count 0 2006.285.07:48:00.30#ibcon#read 3, iclass 4, count 0 2006.285.07:48:00.30#ibcon#about to read 4, iclass 4, count 0 2006.285.07:48:00.30#ibcon#read 4, iclass 4, count 0 2006.285.07:48:00.30#ibcon#about to read 5, iclass 4, count 0 2006.285.07:48:00.30#ibcon#read 5, iclass 4, count 0 2006.285.07:48:00.30#ibcon#about to read 6, iclass 4, count 0 2006.285.07:48:00.30#ibcon#read 6, iclass 4, count 0 2006.285.07:48:00.30#ibcon#end of sib2, iclass 4, count 0 2006.285.07:48:00.30#ibcon#*after write, iclass 4, count 0 2006.285.07:48:00.30#ibcon#*before return 0, iclass 4, count 0 2006.285.07:48:00.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:48:00.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:48:00.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.07:48:00.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.07:48:00.30$vck44/va=7,4 2006.285.07:48:00.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.07:48:00.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.07:48:00.30#ibcon#ireg 11 cls_cnt 2 2006.285.07:48:00.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:48:00.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:48:00.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:48:00.36#ibcon#enter wrdev, iclass 6, count 2 2006.285.07:48:00.36#ibcon#first serial, iclass 6, count 2 2006.285.07:48:00.36#ibcon#enter sib2, iclass 6, count 2 2006.285.07:48:00.36#ibcon#flushed, iclass 6, count 2 2006.285.07:48:00.36#ibcon#about to write, iclass 6, count 2 2006.285.07:48:00.36#ibcon#wrote, iclass 6, count 2 2006.285.07:48:00.36#ibcon#about to read 3, iclass 6, count 2 2006.285.07:48:00.38#ibcon#read 3, iclass 6, count 2 2006.285.07:48:00.38#ibcon#about to read 4, iclass 6, count 2 2006.285.07:48:00.38#ibcon#read 4, iclass 6, count 2 2006.285.07:48:00.38#ibcon#about to read 5, iclass 6, count 2 2006.285.07:48:00.38#ibcon#read 5, iclass 6, count 2 2006.285.07:48:00.38#ibcon#about to read 6, iclass 6, count 2 2006.285.07:48:00.38#ibcon#read 6, iclass 6, count 2 2006.285.07:48:00.38#ibcon#end of sib2, iclass 6, count 2 2006.285.07:48:00.38#ibcon#*mode == 0, iclass 6, count 2 2006.285.07:48:00.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.07:48:00.38#ibcon#[25=AT07-04\r\n] 2006.285.07:48:00.38#ibcon#*before write, iclass 6, count 2 2006.285.07:48:00.38#ibcon#enter sib2, iclass 6, count 2 2006.285.07:48:00.38#ibcon#flushed, iclass 6, count 2 2006.285.07:48:00.38#ibcon#about to write, iclass 6, count 2 2006.285.07:48:00.38#ibcon#wrote, iclass 6, count 2 2006.285.07:48:00.38#ibcon#about to read 3, iclass 6, count 2 2006.285.07:48:00.41#ibcon#read 3, iclass 6, count 2 2006.285.07:48:00.41#ibcon#about to read 4, iclass 6, count 2 2006.285.07:48:00.41#ibcon#read 4, iclass 6, count 2 2006.285.07:48:00.41#ibcon#about to read 5, iclass 6, count 2 2006.285.07:48:00.41#ibcon#read 5, iclass 6, count 2 2006.285.07:48:00.41#ibcon#about to read 6, iclass 6, count 2 2006.285.07:48:00.41#ibcon#read 6, iclass 6, count 2 2006.285.07:48:00.41#ibcon#end of sib2, iclass 6, count 2 2006.285.07:48:00.41#ibcon#*after write, iclass 6, count 2 2006.285.07:48:00.41#ibcon#*before return 0, iclass 6, count 2 2006.285.07:48:00.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:48:00.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:48:00.41#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.07:48:00.41#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:00.41#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:48:00.53#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:48:00.53#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:48:00.53#ibcon#enter wrdev, iclass 6, count 0 2006.285.07:48:00.53#ibcon#first serial, iclass 6, count 0 2006.285.07:48:00.53#ibcon#enter sib2, iclass 6, count 0 2006.285.07:48:00.53#ibcon#flushed, iclass 6, count 0 2006.285.07:48:00.53#ibcon#about to write, iclass 6, count 0 2006.285.07:48:00.53#ibcon#wrote, iclass 6, count 0 2006.285.07:48:00.53#ibcon#about to read 3, iclass 6, count 0 2006.285.07:48:00.55#ibcon#read 3, iclass 6, count 0 2006.285.07:48:00.55#ibcon#about to read 4, iclass 6, count 0 2006.285.07:48:00.55#ibcon#read 4, iclass 6, count 0 2006.285.07:48:00.55#ibcon#about to read 5, iclass 6, count 0 2006.285.07:48:00.55#ibcon#read 5, iclass 6, count 0 2006.285.07:48:00.55#ibcon#about to read 6, iclass 6, count 0 2006.285.07:48:00.55#ibcon#read 6, iclass 6, count 0 2006.285.07:48:00.55#ibcon#end of sib2, iclass 6, count 0 2006.285.07:48:00.55#ibcon#*mode == 0, iclass 6, count 0 2006.285.07:48:00.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.07:48:00.55#ibcon#[25=USB\r\n] 2006.285.07:48:00.55#ibcon#*before write, iclass 6, count 0 2006.285.07:48:00.55#ibcon#enter sib2, iclass 6, count 0 2006.285.07:48:00.55#ibcon#flushed, iclass 6, count 0 2006.285.07:48:00.55#ibcon#about to write, iclass 6, count 0 2006.285.07:48:00.55#ibcon#wrote, iclass 6, count 0 2006.285.07:48:00.55#ibcon#about to read 3, iclass 6, count 0 2006.285.07:48:00.58#ibcon#read 3, iclass 6, count 0 2006.285.07:48:00.58#ibcon#about to read 4, iclass 6, count 0 2006.285.07:48:00.58#ibcon#read 4, iclass 6, count 0 2006.285.07:48:00.58#ibcon#about to read 5, iclass 6, count 0 2006.285.07:48:00.58#ibcon#read 5, iclass 6, count 0 2006.285.07:48:00.58#ibcon#about to read 6, iclass 6, count 0 2006.285.07:48:00.58#ibcon#read 6, iclass 6, count 0 2006.285.07:48:00.58#ibcon#end of sib2, iclass 6, count 0 2006.285.07:48:00.58#ibcon#*after write, iclass 6, count 0 2006.285.07:48:00.58#ibcon#*before return 0, iclass 6, count 0 2006.285.07:48:00.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:48:00.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:48:00.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.07:48:00.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.07:48:00.58$vck44/valo=8,884.99 2006.285.07:48:00.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.07:48:00.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.07:48:00.58#ibcon#ireg 17 cls_cnt 0 2006.285.07:48:00.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:48:00.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:48:00.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:48:00.58#ibcon#enter wrdev, iclass 10, count 0 2006.285.07:48:00.58#ibcon#first serial, iclass 10, count 0 2006.285.07:48:00.58#ibcon#enter sib2, iclass 10, count 0 2006.285.07:48:00.58#ibcon#flushed, iclass 10, count 0 2006.285.07:48:00.58#ibcon#about to write, iclass 10, count 0 2006.285.07:48:00.58#ibcon#wrote, iclass 10, count 0 2006.285.07:48:00.58#ibcon#about to read 3, iclass 10, count 0 2006.285.07:48:00.60#ibcon#read 3, iclass 10, count 0 2006.285.07:48:00.60#ibcon#about to read 4, iclass 10, count 0 2006.285.07:48:00.60#ibcon#read 4, iclass 10, count 0 2006.285.07:48:00.60#ibcon#about to read 5, iclass 10, count 0 2006.285.07:48:00.60#ibcon#read 5, iclass 10, count 0 2006.285.07:48:00.60#ibcon#about to read 6, iclass 10, count 0 2006.285.07:48:00.60#ibcon#read 6, iclass 10, count 0 2006.285.07:48:00.60#ibcon#end of sib2, iclass 10, count 0 2006.285.07:48:00.60#ibcon#*mode == 0, iclass 10, count 0 2006.285.07:48:00.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.07:48:00.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:48:00.60#ibcon#*before write, iclass 10, count 0 2006.285.07:48:00.60#ibcon#enter sib2, iclass 10, count 0 2006.285.07:48:00.60#ibcon#flushed, iclass 10, count 0 2006.285.07:48:00.60#ibcon#about to write, iclass 10, count 0 2006.285.07:48:00.60#ibcon#wrote, iclass 10, count 0 2006.285.07:48:00.60#ibcon#about to read 3, iclass 10, count 0 2006.285.07:48:00.64#ibcon#read 3, iclass 10, count 0 2006.285.07:48:00.64#ibcon#about to read 4, iclass 10, count 0 2006.285.07:48:00.64#ibcon#read 4, iclass 10, count 0 2006.285.07:48:00.64#ibcon#about to read 5, iclass 10, count 0 2006.285.07:48:00.64#ibcon#read 5, iclass 10, count 0 2006.285.07:48:00.64#ibcon#about to read 6, iclass 10, count 0 2006.285.07:48:00.64#ibcon#read 6, iclass 10, count 0 2006.285.07:48:00.64#ibcon#end of sib2, iclass 10, count 0 2006.285.07:48:00.64#ibcon#*after write, iclass 10, count 0 2006.285.07:48:00.64#ibcon#*before return 0, iclass 10, count 0 2006.285.07:48:00.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:48:00.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:48:00.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.07:48:00.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.07:48:00.64$vck44/va=8,3 2006.285.07:48:00.64#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.07:48:00.64#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.07:48:00.64#ibcon#ireg 11 cls_cnt 2 2006.285.07:48:00.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:48:00.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:48:00.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:48:00.70#ibcon#enter wrdev, iclass 12, count 2 2006.285.07:48:00.70#ibcon#first serial, iclass 12, count 2 2006.285.07:48:00.70#ibcon#enter sib2, iclass 12, count 2 2006.285.07:48:00.70#ibcon#flushed, iclass 12, count 2 2006.285.07:48:00.70#ibcon#about to write, iclass 12, count 2 2006.285.07:48:00.70#ibcon#wrote, iclass 12, count 2 2006.285.07:48:00.70#ibcon#about to read 3, iclass 12, count 2 2006.285.07:48:00.72#ibcon#read 3, iclass 12, count 2 2006.285.07:48:00.72#ibcon#about to read 4, iclass 12, count 2 2006.285.07:48:00.72#ibcon#read 4, iclass 12, count 2 2006.285.07:48:00.72#ibcon#about to read 5, iclass 12, count 2 2006.285.07:48:00.72#ibcon#read 5, iclass 12, count 2 2006.285.07:48:00.72#ibcon#about to read 6, iclass 12, count 2 2006.285.07:48:00.72#ibcon#read 6, iclass 12, count 2 2006.285.07:48:00.72#ibcon#end of sib2, iclass 12, count 2 2006.285.07:48:00.72#ibcon#*mode == 0, iclass 12, count 2 2006.285.07:48:00.72#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.07:48:00.72#ibcon#[25=AT08-03\r\n] 2006.285.07:48:00.72#ibcon#*before write, iclass 12, count 2 2006.285.07:48:00.72#ibcon#enter sib2, iclass 12, count 2 2006.285.07:48:00.72#ibcon#flushed, iclass 12, count 2 2006.285.07:48:00.72#ibcon#about to write, iclass 12, count 2 2006.285.07:48:00.72#ibcon#wrote, iclass 12, count 2 2006.285.07:48:00.72#ibcon#about to read 3, iclass 12, count 2 2006.285.07:48:00.75#ibcon#read 3, iclass 12, count 2 2006.285.07:48:00.75#ibcon#about to read 4, iclass 12, count 2 2006.285.07:48:00.75#ibcon#read 4, iclass 12, count 2 2006.285.07:48:00.75#ibcon#about to read 5, iclass 12, count 2 2006.285.07:48:00.75#ibcon#read 5, iclass 12, count 2 2006.285.07:48:00.75#ibcon#about to read 6, iclass 12, count 2 2006.285.07:48:00.75#ibcon#read 6, iclass 12, count 2 2006.285.07:48:00.75#ibcon#end of sib2, iclass 12, count 2 2006.285.07:48:00.75#ibcon#*after write, iclass 12, count 2 2006.285.07:48:00.75#ibcon#*before return 0, iclass 12, count 2 2006.285.07:48:00.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:48:00.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.07:48:00.75#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.07:48:00.75#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:00.75#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:48:00.87#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:48:00.87#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:48:00.87#ibcon#enter wrdev, iclass 12, count 0 2006.285.07:48:00.87#ibcon#first serial, iclass 12, count 0 2006.285.07:48:00.87#ibcon#enter sib2, iclass 12, count 0 2006.285.07:48:00.87#ibcon#flushed, iclass 12, count 0 2006.285.07:48:00.87#ibcon#about to write, iclass 12, count 0 2006.285.07:48:00.87#ibcon#wrote, iclass 12, count 0 2006.285.07:48:00.87#ibcon#about to read 3, iclass 12, count 0 2006.285.07:48:00.89#ibcon#read 3, iclass 12, count 0 2006.285.07:48:00.89#ibcon#about to read 4, iclass 12, count 0 2006.285.07:48:00.89#ibcon#read 4, iclass 12, count 0 2006.285.07:48:00.89#ibcon#about to read 5, iclass 12, count 0 2006.285.07:48:00.89#ibcon#read 5, iclass 12, count 0 2006.285.07:48:00.89#ibcon#about to read 6, iclass 12, count 0 2006.285.07:48:00.89#ibcon#read 6, iclass 12, count 0 2006.285.07:48:00.89#ibcon#end of sib2, iclass 12, count 0 2006.285.07:48:00.89#ibcon#*mode == 0, iclass 12, count 0 2006.285.07:48:00.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.07:48:00.89#ibcon#[25=USB\r\n] 2006.285.07:48:00.89#ibcon#*before write, iclass 12, count 0 2006.285.07:48:00.89#ibcon#enter sib2, iclass 12, count 0 2006.285.07:48:00.89#ibcon#flushed, iclass 12, count 0 2006.285.07:48:00.89#ibcon#about to write, iclass 12, count 0 2006.285.07:48:00.89#ibcon#wrote, iclass 12, count 0 2006.285.07:48:00.89#ibcon#about to read 3, iclass 12, count 0 2006.285.07:48:00.92#ibcon#read 3, iclass 12, count 0 2006.285.07:48:00.92#ibcon#about to read 4, iclass 12, count 0 2006.285.07:48:00.92#ibcon#read 4, iclass 12, count 0 2006.285.07:48:00.92#ibcon#about to read 5, iclass 12, count 0 2006.285.07:48:00.92#ibcon#read 5, iclass 12, count 0 2006.285.07:48:00.92#ibcon#about to read 6, iclass 12, count 0 2006.285.07:48:00.92#ibcon#read 6, iclass 12, count 0 2006.285.07:48:00.92#ibcon#end of sib2, iclass 12, count 0 2006.285.07:48:00.92#ibcon#*after write, iclass 12, count 0 2006.285.07:48:00.92#ibcon#*before return 0, iclass 12, count 0 2006.285.07:48:00.92#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:48:00.92#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.07:48:00.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.07:48:00.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.07:48:00.92$vck44/vblo=1,629.99 2006.285.07:48:00.92#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.07:48:00.92#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.07:48:00.92#ibcon#ireg 17 cls_cnt 0 2006.285.07:48:00.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:48:00.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:48:00.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:48:00.92#ibcon#enter wrdev, iclass 14, count 0 2006.285.07:48:00.92#ibcon#first serial, iclass 14, count 0 2006.285.07:48:00.92#ibcon#enter sib2, iclass 14, count 0 2006.285.07:48:00.92#ibcon#flushed, iclass 14, count 0 2006.285.07:48:00.92#ibcon#about to write, iclass 14, count 0 2006.285.07:48:00.92#ibcon#wrote, iclass 14, count 0 2006.285.07:48:00.92#ibcon#about to read 3, iclass 14, count 0 2006.285.07:48:00.94#ibcon#read 3, iclass 14, count 0 2006.285.07:48:00.94#ibcon#about to read 4, iclass 14, count 0 2006.285.07:48:00.94#ibcon#read 4, iclass 14, count 0 2006.285.07:48:00.94#ibcon#about to read 5, iclass 14, count 0 2006.285.07:48:00.94#ibcon#read 5, iclass 14, count 0 2006.285.07:48:00.94#ibcon#about to read 6, iclass 14, count 0 2006.285.07:48:00.94#ibcon#read 6, iclass 14, count 0 2006.285.07:48:00.94#ibcon#end of sib2, iclass 14, count 0 2006.285.07:48:00.94#ibcon#*mode == 0, iclass 14, count 0 2006.285.07:48:00.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.07:48:00.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:48:00.94#ibcon#*before write, iclass 14, count 0 2006.285.07:48:00.94#ibcon#enter sib2, iclass 14, count 0 2006.285.07:48:00.94#ibcon#flushed, iclass 14, count 0 2006.285.07:48:00.94#ibcon#about to write, iclass 14, count 0 2006.285.07:48:00.94#ibcon#wrote, iclass 14, count 0 2006.285.07:48:00.94#ibcon#about to read 3, iclass 14, count 0 2006.285.07:48:00.98#ibcon#read 3, iclass 14, count 0 2006.285.07:48:00.98#ibcon#about to read 4, iclass 14, count 0 2006.285.07:48:00.98#ibcon#read 4, iclass 14, count 0 2006.285.07:48:00.98#ibcon#about to read 5, iclass 14, count 0 2006.285.07:48:00.98#ibcon#read 5, iclass 14, count 0 2006.285.07:48:00.98#ibcon#about to read 6, iclass 14, count 0 2006.285.07:48:00.98#ibcon#read 6, iclass 14, count 0 2006.285.07:48:00.98#ibcon#end of sib2, iclass 14, count 0 2006.285.07:48:00.98#ibcon#*after write, iclass 14, count 0 2006.285.07:48:00.98#ibcon#*before return 0, iclass 14, count 0 2006.285.07:48:00.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:48:00.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.07:48:00.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.07:48:00.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.07:48:00.98$vck44/vb=1,4 2006.285.07:48:00.98#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.07:48:00.98#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.07:48:00.98#ibcon#ireg 11 cls_cnt 2 2006.285.07:48:00.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:48:00.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:48:00.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:48:00.98#ibcon#enter wrdev, iclass 16, count 2 2006.285.07:48:00.98#ibcon#first serial, iclass 16, count 2 2006.285.07:48:00.98#ibcon#enter sib2, iclass 16, count 2 2006.285.07:48:00.98#ibcon#flushed, iclass 16, count 2 2006.285.07:48:00.98#ibcon#about to write, iclass 16, count 2 2006.285.07:48:00.98#ibcon#wrote, iclass 16, count 2 2006.285.07:48:00.98#ibcon#about to read 3, iclass 16, count 2 2006.285.07:48:01.00#ibcon#read 3, iclass 16, count 2 2006.285.07:48:01.00#ibcon#about to read 4, iclass 16, count 2 2006.285.07:48:01.00#ibcon#read 4, iclass 16, count 2 2006.285.07:48:01.00#ibcon#about to read 5, iclass 16, count 2 2006.285.07:48:01.00#ibcon#read 5, iclass 16, count 2 2006.285.07:48:01.00#ibcon#about to read 6, iclass 16, count 2 2006.285.07:48:01.00#ibcon#read 6, iclass 16, count 2 2006.285.07:48:01.00#ibcon#end of sib2, iclass 16, count 2 2006.285.07:48:01.00#ibcon#*mode == 0, iclass 16, count 2 2006.285.07:48:01.00#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.07:48:01.00#ibcon#[27=AT01-04\r\n] 2006.285.07:48:01.00#ibcon#*before write, iclass 16, count 2 2006.285.07:48:01.00#ibcon#enter sib2, iclass 16, count 2 2006.285.07:48:01.00#ibcon#flushed, iclass 16, count 2 2006.285.07:48:01.00#ibcon#about to write, iclass 16, count 2 2006.285.07:48:01.00#ibcon#wrote, iclass 16, count 2 2006.285.07:48:01.00#ibcon#about to read 3, iclass 16, count 2 2006.285.07:48:01.03#ibcon#read 3, iclass 16, count 2 2006.285.07:48:01.03#ibcon#about to read 4, iclass 16, count 2 2006.285.07:48:01.03#ibcon#read 4, iclass 16, count 2 2006.285.07:48:01.03#ibcon#about to read 5, iclass 16, count 2 2006.285.07:48:01.03#ibcon#read 5, iclass 16, count 2 2006.285.07:48:01.03#ibcon#about to read 6, iclass 16, count 2 2006.285.07:48:01.03#ibcon#read 6, iclass 16, count 2 2006.285.07:48:01.03#ibcon#end of sib2, iclass 16, count 2 2006.285.07:48:01.03#ibcon#*after write, iclass 16, count 2 2006.285.07:48:01.03#ibcon#*before return 0, iclass 16, count 2 2006.285.07:48:01.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:48:01.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.07:48:01.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.07:48:01.03#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:01.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:48:01.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:48:01.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:48:01.15#ibcon#enter wrdev, iclass 16, count 0 2006.285.07:48:01.15#ibcon#first serial, iclass 16, count 0 2006.285.07:48:01.15#ibcon#enter sib2, iclass 16, count 0 2006.285.07:48:01.15#ibcon#flushed, iclass 16, count 0 2006.285.07:48:01.15#ibcon#about to write, iclass 16, count 0 2006.285.07:48:01.15#ibcon#wrote, iclass 16, count 0 2006.285.07:48:01.15#ibcon#about to read 3, iclass 16, count 0 2006.285.07:48:01.17#ibcon#read 3, iclass 16, count 0 2006.285.07:48:01.17#ibcon#about to read 4, iclass 16, count 0 2006.285.07:48:01.17#ibcon#read 4, iclass 16, count 0 2006.285.07:48:01.17#ibcon#about to read 5, iclass 16, count 0 2006.285.07:48:01.17#ibcon#read 5, iclass 16, count 0 2006.285.07:48:01.17#ibcon#about to read 6, iclass 16, count 0 2006.285.07:48:01.17#ibcon#read 6, iclass 16, count 0 2006.285.07:48:01.17#ibcon#end of sib2, iclass 16, count 0 2006.285.07:48:01.17#ibcon#*mode == 0, iclass 16, count 0 2006.285.07:48:01.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.07:48:01.17#ibcon#[27=USB\r\n] 2006.285.07:48:01.17#ibcon#*before write, iclass 16, count 0 2006.285.07:48:01.17#ibcon#enter sib2, iclass 16, count 0 2006.285.07:48:01.17#ibcon#flushed, iclass 16, count 0 2006.285.07:48:01.17#ibcon#about to write, iclass 16, count 0 2006.285.07:48:01.17#ibcon#wrote, iclass 16, count 0 2006.285.07:48:01.17#ibcon#about to read 3, iclass 16, count 0 2006.285.07:48:01.20#ibcon#read 3, iclass 16, count 0 2006.285.07:48:01.20#ibcon#about to read 4, iclass 16, count 0 2006.285.07:48:01.20#ibcon#read 4, iclass 16, count 0 2006.285.07:48:01.20#ibcon#about to read 5, iclass 16, count 0 2006.285.07:48:01.20#ibcon#read 5, iclass 16, count 0 2006.285.07:48:01.20#ibcon#about to read 6, iclass 16, count 0 2006.285.07:48:01.20#ibcon#read 6, iclass 16, count 0 2006.285.07:48:01.20#ibcon#end of sib2, iclass 16, count 0 2006.285.07:48:01.20#ibcon#*after write, iclass 16, count 0 2006.285.07:48:01.20#ibcon#*before return 0, iclass 16, count 0 2006.285.07:48:01.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:48:01.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.07:48:01.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.07:48:01.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.07:48:01.20$vck44/vblo=2,634.99 2006.285.07:48:01.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.07:48:01.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.07:48:01.20#ibcon#ireg 17 cls_cnt 0 2006.285.07:48:01.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:48:01.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:48:01.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:48:01.20#ibcon#enter wrdev, iclass 18, count 0 2006.285.07:48:01.20#ibcon#first serial, iclass 18, count 0 2006.285.07:48:01.20#ibcon#enter sib2, iclass 18, count 0 2006.285.07:48:01.20#ibcon#flushed, iclass 18, count 0 2006.285.07:48:01.20#ibcon#about to write, iclass 18, count 0 2006.285.07:48:01.20#ibcon#wrote, iclass 18, count 0 2006.285.07:48:01.20#ibcon#about to read 3, iclass 18, count 0 2006.285.07:48:01.22#ibcon#read 3, iclass 18, count 0 2006.285.07:48:01.22#ibcon#about to read 4, iclass 18, count 0 2006.285.07:48:01.22#ibcon#read 4, iclass 18, count 0 2006.285.07:48:01.22#ibcon#about to read 5, iclass 18, count 0 2006.285.07:48:01.22#ibcon#read 5, iclass 18, count 0 2006.285.07:48:01.22#ibcon#about to read 6, iclass 18, count 0 2006.285.07:48:01.22#ibcon#read 6, iclass 18, count 0 2006.285.07:48:01.22#ibcon#end of sib2, iclass 18, count 0 2006.285.07:48:01.22#ibcon#*mode == 0, iclass 18, count 0 2006.285.07:48:01.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.07:48:01.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:48:01.22#ibcon#*before write, iclass 18, count 0 2006.285.07:48:01.22#ibcon#enter sib2, iclass 18, count 0 2006.285.07:48:01.22#ibcon#flushed, iclass 18, count 0 2006.285.07:48:01.22#ibcon#about to write, iclass 18, count 0 2006.285.07:48:01.22#ibcon#wrote, iclass 18, count 0 2006.285.07:48:01.22#ibcon#about to read 3, iclass 18, count 0 2006.285.07:48:01.26#ibcon#read 3, iclass 18, count 0 2006.285.07:48:01.26#ibcon#about to read 4, iclass 18, count 0 2006.285.07:48:01.26#ibcon#read 4, iclass 18, count 0 2006.285.07:48:01.26#ibcon#about to read 5, iclass 18, count 0 2006.285.07:48:01.26#ibcon#read 5, iclass 18, count 0 2006.285.07:48:01.26#ibcon#about to read 6, iclass 18, count 0 2006.285.07:48:01.26#ibcon#read 6, iclass 18, count 0 2006.285.07:48:01.26#ibcon#end of sib2, iclass 18, count 0 2006.285.07:48:01.26#ibcon#*after write, iclass 18, count 0 2006.285.07:48:01.26#ibcon#*before return 0, iclass 18, count 0 2006.285.07:48:01.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:48:01.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.07:48:01.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.07:48:01.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.07:48:01.26$vck44/vb=2,5 2006.285.07:48:01.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.07:48:01.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.07:48:01.26#ibcon#ireg 11 cls_cnt 2 2006.285.07:48:01.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:48:01.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:48:01.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:48:01.32#ibcon#enter wrdev, iclass 20, count 2 2006.285.07:48:01.32#ibcon#first serial, iclass 20, count 2 2006.285.07:48:01.32#ibcon#enter sib2, iclass 20, count 2 2006.285.07:48:01.32#ibcon#flushed, iclass 20, count 2 2006.285.07:48:01.32#ibcon#about to write, iclass 20, count 2 2006.285.07:48:01.32#ibcon#wrote, iclass 20, count 2 2006.285.07:48:01.32#ibcon#about to read 3, iclass 20, count 2 2006.285.07:48:01.34#ibcon#read 3, iclass 20, count 2 2006.285.07:48:01.34#ibcon#about to read 4, iclass 20, count 2 2006.285.07:48:01.34#ibcon#read 4, iclass 20, count 2 2006.285.07:48:01.34#ibcon#about to read 5, iclass 20, count 2 2006.285.07:48:01.34#ibcon#read 5, iclass 20, count 2 2006.285.07:48:01.34#ibcon#about to read 6, iclass 20, count 2 2006.285.07:48:01.34#ibcon#read 6, iclass 20, count 2 2006.285.07:48:01.34#ibcon#end of sib2, iclass 20, count 2 2006.285.07:48:01.34#ibcon#*mode == 0, iclass 20, count 2 2006.285.07:48:01.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.07:48:01.34#ibcon#[27=AT02-05\r\n] 2006.285.07:48:01.34#ibcon#*before write, iclass 20, count 2 2006.285.07:48:01.34#ibcon#enter sib2, iclass 20, count 2 2006.285.07:48:01.34#ibcon#flushed, iclass 20, count 2 2006.285.07:48:01.34#ibcon#about to write, iclass 20, count 2 2006.285.07:48:01.34#ibcon#wrote, iclass 20, count 2 2006.285.07:48:01.34#ibcon#about to read 3, iclass 20, count 2 2006.285.07:48:01.37#ibcon#read 3, iclass 20, count 2 2006.285.07:48:01.37#ibcon#about to read 4, iclass 20, count 2 2006.285.07:48:01.37#ibcon#read 4, iclass 20, count 2 2006.285.07:48:01.37#ibcon#about to read 5, iclass 20, count 2 2006.285.07:48:01.37#ibcon#read 5, iclass 20, count 2 2006.285.07:48:01.37#ibcon#about to read 6, iclass 20, count 2 2006.285.07:48:01.37#ibcon#read 6, iclass 20, count 2 2006.285.07:48:01.37#ibcon#end of sib2, iclass 20, count 2 2006.285.07:48:01.37#ibcon#*after write, iclass 20, count 2 2006.285.07:48:01.37#ibcon#*before return 0, iclass 20, count 2 2006.285.07:48:01.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:48:01.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.07:48:01.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.07:48:01.37#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:01.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:48:01.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:48:01.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:48:01.49#ibcon#enter wrdev, iclass 20, count 0 2006.285.07:48:01.49#ibcon#first serial, iclass 20, count 0 2006.285.07:48:01.49#ibcon#enter sib2, iclass 20, count 0 2006.285.07:48:01.49#ibcon#flushed, iclass 20, count 0 2006.285.07:48:01.49#ibcon#about to write, iclass 20, count 0 2006.285.07:48:01.49#ibcon#wrote, iclass 20, count 0 2006.285.07:48:01.49#ibcon#about to read 3, iclass 20, count 0 2006.285.07:48:01.51#ibcon#read 3, iclass 20, count 0 2006.285.07:48:01.51#ibcon#about to read 4, iclass 20, count 0 2006.285.07:48:01.51#ibcon#read 4, iclass 20, count 0 2006.285.07:48:01.51#ibcon#about to read 5, iclass 20, count 0 2006.285.07:48:01.51#ibcon#read 5, iclass 20, count 0 2006.285.07:48:01.51#ibcon#about to read 6, iclass 20, count 0 2006.285.07:48:01.51#ibcon#read 6, iclass 20, count 0 2006.285.07:48:01.51#ibcon#end of sib2, iclass 20, count 0 2006.285.07:48:01.51#ibcon#*mode == 0, iclass 20, count 0 2006.285.07:48:01.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.07:48:01.51#ibcon#[27=USB\r\n] 2006.285.07:48:01.51#ibcon#*before write, iclass 20, count 0 2006.285.07:48:01.51#ibcon#enter sib2, iclass 20, count 0 2006.285.07:48:01.51#ibcon#flushed, iclass 20, count 0 2006.285.07:48:01.51#ibcon#about to write, iclass 20, count 0 2006.285.07:48:01.51#ibcon#wrote, iclass 20, count 0 2006.285.07:48:01.51#ibcon#about to read 3, iclass 20, count 0 2006.285.07:48:01.54#ibcon#read 3, iclass 20, count 0 2006.285.07:48:01.54#ibcon#about to read 4, iclass 20, count 0 2006.285.07:48:01.54#ibcon#read 4, iclass 20, count 0 2006.285.07:48:01.54#ibcon#about to read 5, iclass 20, count 0 2006.285.07:48:01.54#ibcon#read 5, iclass 20, count 0 2006.285.07:48:01.54#ibcon#about to read 6, iclass 20, count 0 2006.285.07:48:01.54#ibcon#read 6, iclass 20, count 0 2006.285.07:48:01.54#ibcon#end of sib2, iclass 20, count 0 2006.285.07:48:01.54#ibcon#*after write, iclass 20, count 0 2006.285.07:48:01.54#ibcon#*before return 0, iclass 20, count 0 2006.285.07:48:01.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:48:01.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.07:48:01.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.07:48:01.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.07:48:01.54$vck44/vblo=3,649.99 2006.285.07:48:01.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.07:48:01.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.07:48:01.54#ibcon#ireg 17 cls_cnt 0 2006.285.07:48:01.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:48:01.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:48:01.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:48:01.54#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:48:01.54#ibcon#first serial, iclass 22, count 0 2006.285.07:48:01.54#ibcon#enter sib2, iclass 22, count 0 2006.285.07:48:01.54#ibcon#flushed, iclass 22, count 0 2006.285.07:48:01.54#ibcon#about to write, iclass 22, count 0 2006.285.07:48:01.54#ibcon#wrote, iclass 22, count 0 2006.285.07:48:01.54#ibcon#about to read 3, iclass 22, count 0 2006.285.07:48:01.56#ibcon#read 3, iclass 22, count 0 2006.285.07:48:01.56#ibcon#about to read 4, iclass 22, count 0 2006.285.07:48:01.56#ibcon#read 4, iclass 22, count 0 2006.285.07:48:01.56#ibcon#about to read 5, iclass 22, count 0 2006.285.07:48:01.56#ibcon#read 5, iclass 22, count 0 2006.285.07:48:01.56#ibcon#about to read 6, iclass 22, count 0 2006.285.07:48:01.56#ibcon#read 6, iclass 22, count 0 2006.285.07:48:01.56#ibcon#end of sib2, iclass 22, count 0 2006.285.07:48:01.56#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:48:01.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:48:01.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:48:01.56#ibcon#*before write, iclass 22, count 0 2006.285.07:48:01.56#ibcon#enter sib2, iclass 22, count 0 2006.285.07:48:01.56#ibcon#flushed, iclass 22, count 0 2006.285.07:48:01.56#ibcon#about to write, iclass 22, count 0 2006.285.07:48:01.56#ibcon#wrote, iclass 22, count 0 2006.285.07:48:01.56#ibcon#about to read 3, iclass 22, count 0 2006.285.07:48:01.60#ibcon#read 3, iclass 22, count 0 2006.285.07:48:01.60#ibcon#about to read 4, iclass 22, count 0 2006.285.07:48:01.60#ibcon#read 4, iclass 22, count 0 2006.285.07:48:01.60#ibcon#about to read 5, iclass 22, count 0 2006.285.07:48:01.60#ibcon#read 5, iclass 22, count 0 2006.285.07:48:01.60#ibcon#about to read 6, iclass 22, count 0 2006.285.07:48:01.60#ibcon#read 6, iclass 22, count 0 2006.285.07:48:01.60#ibcon#end of sib2, iclass 22, count 0 2006.285.07:48:01.60#ibcon#*after write, iclass 22, count 0 2006.285.07:48:01.60#ibcon#*before return 0, iclass 22, count 0 2006.285.07:48:01.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:48:01.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:48:01.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:48:01.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:48:01.60$vck44/vb=3,4 2006.285.07:48:01.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.07:48:01.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.07:48:01.60#ibcon#ireg 11 cls_cnt 2 2006.285.07:48:01.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:48:01.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:48:01.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:48:01.66#ibcon#enter wrdev, iclass 24, count 2 2006.285.07:48:01.66#ibcon#first serial, iclass 24, count 2 2006.285.07:48:01.66#ibcon#enter sib2, iclass 24, count 2 2006.285.07:48:01.66#ibcon#flushed, iclass 24, count 2 2006.285.07:48:01.66#ibcon#about to write, iclass 24, count 2 2006.285.07:48:01.66#ibcon#wrote, iclass 24, count 2 2006.285.07:48:01.66#ibcon#about to read 3, iclass 24, count 2 2006.285.07:48:01.68#ibcon#read 3, iclass 24, count 2 2006.285.07:48:01.68#ibcon#about to read 4, iclass 24, count 2 2006.285.07:48:01.68#ibcon#read 4, iclass 24, count 2 2006.285.07:48:01.68#ibcon#about to read 5, iclass 24, count 2 2006.285.07:48:01.68#ibcon#read 5, iclass 24, count 2 2006.285.07:48:01.68#ibcon#about to read 6, iclass 24, count 2 2006.285.07:48:01.68#ibcon#read 6, iclass 24, count 2 2006.285.07:48:01.68#ibcon#end of sib2, iclass 24, count 2 2006.285.07:48:01.68#ibcon#*mode == 0, iclass 24, count 2 2006.285.07:48:01.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.07:48:01.68#ibcon#[27=AT03-04\r\n] 2006.285.07:48:01.68#ibcon#*before write, iclass 24, count 2 2006.285.07:48:01.68#ibcon#enter sib2, iclass 24, count 2 2006.285.07:48:01.68#ibcon#flushed, iclass 24, count 2 2006.285.07:48:01.68#ibcon#about to write, iclass 24, count 2 2006.285.07:48:01.68#ibcon#wrote, iclass 24, count 2 2006.285.07:48:01.68#ibcon#about to read 3, iclass 24, count 2 2006.285.07:48:01.71#ibcon#read 3, iclass 24, count 2 2006.285.07:48:01.71#ibcon#about to read 4, iclass 24, count 2 2006.285.07:48:01.71#ibcon#read 4, iclass 24, count 2 2006.285.07:48:01.71#ibcon#about to read 5, iclass 24, count 2 2006.285.07:48:01.71#ibcon#read 5, iclass 24, count 2 2006.285.07:48:01.71#ibcon#about to read 6, iclass 24, count 2 2006.285.07:48:01.71#ibcon#read 6, iclass 24, count 2 2006.285.07:48:01.71#ibcon#end of sib2, iclass 24, count 2 2006.285.07:48:01.71#ibcon#*after write, iclass 24, count 2 2006.285.07:48:01.71#ibcon#*before return 0, iclass 24, count 2 2006.285.07:48:01.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:48:01.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.07:48:01.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.07:48:01.71#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:01.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:48:01.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:48:01.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:48:01.83#ibcon#enter wrdev, iclass 24, count 0 2006.285.07:48:01.83#ibcon#first serial, iclass 24, count 0 2006.285.07:48:01.83#ibcon#enter sib2, iclass 24, count 0 2006.285.07:48:01.83#ibcon#flushed, iclass 24, count 0 2006.285.07:48:01.83#ibcon#about to write, iclass 24, count 0 2006.285.07:48:01.83#ibcon#wrote, iclass 24, count 0 2006.285.07:48:01.83#ibcon#about to read 3, iclass 24, count 0 2006.285.07:48:01.85#ibcon#read 3, iclass 24, count 0 2006.285.07:48:01.85#ibcon#about to read 4, iclass 24, count 0 2006.285.07:48:01.85#ibcon#read 4, iclass 24, count 0 2006.285.07:48:01.85#ibcon#about to read 5, iclass 24, count 0 2006.285.07:48:01.85#ibcon#read 5, iclass 24, count 0 2006.285.07:48:01.85#ibcon#about to read 6, iclass 24, count 0 2006.285.07:48:01.85#ibcon#read 6, iclass 24, count 0 2006.285.07:48:01.85#ibcon#end of sib2, iclass 24, count 0 2006.285.07:48:01.85#ibcon#*mode == 0, iclass 24, count 0 2006.285.07:48:01.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.07:48:01.85#ibcon#[27=USB\r\n] 2006.285.07:48:01.85#ibcon#*before write, iclass 24, count 0 2006.285.07:48:01.85#ibcon#enter sib2, iclass 24, count 0 2006.285.07:48:01.85#ibcon#flushed, iclass 24, count 0 2006.285.07:48:01.85#ibcon#about to write, iclass 24, count 0 2006.285.07:48:01.85#ibcon#wrote, iclass 24, count 0 2006.285.07:48:01.85#ibcon#about to read 3, iclass 24, count 0 2006.285.07:48:01.88#ibcon#read 3, iclass 24, count 0 2006.285.07:48:01.88#ibcon#about to read 4, iclass 24, count 0 2006.285.07:48:01.88#ibcon#read 4, iclass 24, count 0 2006.285.07:48:01.88#ibcon#about to read 5, iclass 24, count 0 2006.285.07:48:01.88#ibcon#read 5, iclass 24, count 0 2006.285.07:48:01.88#ibcon#about to read 6, iclass 24, count 0 2006.285.07:48:01.88#ibcon#read 6, iclass 24, count 0 2006.285.07:48:01.88#ibcon#end of sib2, iclass 24, count 0 2006.285.07:48:01.88#ibcon#*after write, iclass 24, count 0 2006.285.07:48:01.88#ibcon#*before return 0, iclass 24, count 0 2006.285.07:48:01.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:48:01.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.07:48:01.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.07:48:01.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.07:48:01.88$vck44/vblo=4,679.99 2006.285.07:48:01.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.07:48:01.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.07:48:01.88#ibcon#ireg 17 cls_cnt 0 2006.285.07:48:01.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:48:01.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:48:01.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:48:01.88#ibcon#enter wrdev, iclass 26, count 0 2006.285.07:48:01.88#ibcon#first serial, iclass 26, count 0 2006.285.07:48:01.88#ibcon#enter sib2, iclass 26, count 0 2006.285.07:48:01.88#ibcon#flushed, iclass 26, count 0 2006.285.07:48:01.88#ibcon#about to write, iclass 26, count 0 2006.285.07:48:01.88#ibcon#wrote, iclass 26, count 0 2006.285.07:48:01.88#ibcon#about to read 3, iclass 26, count 0 2006.285.07:48:01.90#ibcon#read 3, iclass 26, count 0 2006.285.07:48:01.90#ibcon#about to read 4, iclass 26, count 0 2006.285.07:48:01.90#ibcon#read 4, iclass 26, count 0 2006.285.07:48:01.90#ibcon#about to read 5, iclass 26, count 0 2006.285.07:48:01.90#ibcon#read 5, iclass 26, count 0 2006.285.07:48:01.90#ibcon#about to read 6, iclass 26, count 0 2006.285.07:48:01.90#ibcon#read 6, iclass 26, count 0 2006.285.07:48:01.90#ibcon#end of sib2, iclass 26, count 0 2006.285.07:48:01.90#ibcon#*mode == 0, iclass 26, count 0 2006.285.07:48:01.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.07:48:01.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:48:01.90#ibcon#*before write, iclass 26, count 0 2006.285.07:48:01.90#ibcon#enter sib2, iclass 26, count 0 2006.285.07:48:01.90#ibcon#flushed, iclass 26, count 0 2006.285.07:48:01.90#ibcon#about to write, iclass 26, count 0 2006.285.07:48:01.90#ibcon#wrote, iclass 26, count 0 2006.285.07:48:01.90#ibcon#about to read 3, iclass 26, count 0 2006.285.07:48:01.94#ibcon#read 3, iclass 26, count 0 2006.285.07:48:01.94#ibcon#about to read 4, iclass 26, count 0 2006.285.07:48:01.94#ibcon#read 4, iclass 26, count 0 2006.285.07:48:01.94#ibcon#about to read 5, iclass 26, count 0 2006.285.07:48:01.94#ibcon#read 5, iclass 26, count 0 2006.285.07:48:01.94#ibcon#about to read 6, iclass 26, count 0 2006.285.07:48:01.94#ibcon#read 6, iclass 26, count 0 2006.285.07:48:01.94#ibcon#end of sib2, iclass 26, count 0 2006.285.07:48:01.94#ibcon#*after write, iclass 26, count 0 2006.285.07:48:01.94#ibcon#*before return 0, iclass 26, count 0 2006.285.07:48:01.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:48:01.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.07:48:01.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.07:48:01.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.07:48:01.94$vck44/vb=4,5 2006.285.07:48:01.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.07:48:01.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.07:48:01.94#ibcon#ireg 11 cls_cnt 2 2006.285.07:48:01.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:48:02.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:48:02.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:48:02.00#ibcon#enter wrdev, iclass 28, count 2 2006.285.07:48:02.00#ibcon#first serial, iclass 28, count 2 2006.285.07:48:02.00#ibcon#enter sib2, iclass 28, count 2 2006.285.07:48:02.00#ibcon#flushed, iclass 28, count 2 2006.285.07:48:02.00#ibcon#about to write, iclass 28, count 2 2006.285.07:48:02.00#ibcon#wrote, iclass 28, count 2 2006.285.07:48:02.00#ibcon#about to read 3, iclass 28, count 2 2006.285.07:48:02.02#ibcon#read 3, iclass 28, count 2 2006.285.07:48:02.02#ibcon#about to read 4, iclass 28, count 2 2006.285.07:48:02.02#ibcon#read 4, iclass 28, count 2 2006.285.07:48:02.02#ibcon#about to read 5, iclass 28, count 2 2006.285.07:48:02.02#ibcon#read 5, iclass 28, count 2 2006.285.07:48:02.02#ibcon#about to read 6, iclass 28, count 2 2006.285.07:48:02.02#ibcon#read 6, iclass 28, count 2 2006.285.07:48:02.02#ibcon#end of sib2, iclass 28, count 2 2006.285.07:48:02.02#ibcon#*mode == 0, iclass 28, count 2 2006.285.07:48:02.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.07:48:02.02#ibcon#[27=AT04-05\r\n] 2006.285.07:48:02.02#ibcon#*before write, iclass 28, count 2 2006.285.07:48:02.02#ibcon#enter sib2, iclass 28, count 2 2006.285.07:48:02.02#ibcon#flushed, iclass 28, count 2 2006.285.07:48:02.02#ibcon#about to write, iclass 28, count 2 2006.285.07:48:02.02#ibcon#wrote, iclass 28, count 2 2006.285.07:48:02.02#ibcon#about to read 3, iclass 28, count 2 2006.285.07:48:02.05#ibcon#read 3, iclass 28, count 2 2006.285.07:48:02.05#ibcon#about to read 4, iclass 28, count 2 2006.285.07:48:02.05#ibcon#read 4, iclass 28, count 2 2006.285.07:48:02.05#ibcon#about to read 5, iclass 28, count 2 2006.285.07:48:02.05#ibcon#read 5, iclass 28, count 2 2006.285.07:48:02.05#ibcon#about to read 6, iclass 28, count 2 2006.285.07:48:02.05#ibcon#read 6, iclass 28, count 2 2006.285.07:48:02.05#ibcon#end of sib2, iclass 28, count 2 2006.285.07:48:02.05#ibcon#*after write, iclass 28, count 2 2006.285.07:48:02.05#ibcon#*before return 0, iclass 28, count 2 2006.285.07:48:02.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:48:02.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.07:48:02.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.07:48:02.05#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:02.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:48:02.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:48:02.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:48:02.17#ibcon#enter wrdev, iclass 28, count 0 2006.285.07:48:02.17#ibcon#first serial, iclass 28, count 0 2006.285.07:48:02.17#ibcon#enter sib2, iclass 28, count 0 2006.285.07:48:02.17#ibcon#flushed, iclass 28, count 0 2006.285.07:48:02.17#ibcon#about to write, iclass 28, count 0 2006.285.07:48:02.17#ibcon#wrote, iclass 28, count 0 2006.285.07:48:02.17#ibcon#about to read 3, iclass 28, count 0 2006.285.07:48:02.19#ibcon#read 3, iclass 28, count 0 2006.285.07:48:02.19#ibcon#about to read 4, iclass 28, count 0 2006.285.07:48:02.19#ibcon#read 4, iclass 28, count 0 2006.285.07:48:02.19#ibcon#about to read 5, iclass 28, count 0 2006.285.07:48:02.19#ibcon#read 5, iclass 28, count 0 2006.285.07:48:02.19#ibcon#about to read 6, iclass 28, count 0 2006.285.07:48:02.19#ibcon#read 6, iclass 28, count 0 2006.285.07:48:02.19#ibcon#end of sib2, iclass 28, count 0 2006.285.07:48:02.19#ibcon#*mode == 0, iclass 28, count 0 2006.285.07:48:02.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.07:48:02.19#ibcon#[27=USB\r\n] 2006.285.07:48:02.19#ibcon#*before write, iclass 28, count 0 2006.285.07:48:02.19#ibcon#enter sib2, iclass 28, count 0 2006.285.07:48:02.19#ibcon#flushed, iclass 28, count 0 2006.285.07:48:02.19#ibcon#about to write, iclass 28, count 0 2006.285.07:48:02.19#ibcon#wrote, iclass 28, count 0 2006.285.07:48:02.19#ibcon#about to read 3, iclass 28, count 0 2006.285.07:48:02.22#ibcon#read 3, iclass 28, count 0 2006.285.07:48:02.22#ibcon#about to read 4, iclass 28, count 0 2006.285.07:48:02.22#ibcon#read 4, iclass 28, count 0 2006.285.07:48:02.22#ibcon#about to read 5, iclass 28, count 0 2006.285.07:48:02.22#ibcon#read 5, iclass 28, count 0 2006.285.07:48:02.22#ibcon#about to read 6, iclass 28, count 0 2006.285.07:48:02.22#ibcon#read 6, iclass 28, count 0 2006.285.07:48:02.22#ibcon#end of sib2, iclass 28, count 0 2006.285.07:48:02.22#ibcon#*after write, iclass 28, count 0 2006.285.07:48:02.22#ibcon#*before return 0, iclass 28, count 0 2006.285.07:48:02.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:48:02.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.07:48:02.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.07:48:02.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.07:48:02.22$vck44/vblo=5,709.99 2006.285.07:48:02.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.07:48:02.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.07:48:02.22#ibcon#ireg 17 cls_cnt 0 2006.285.07:48:02.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:48:02.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:48:02.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:48:02.22#ibcon#enter wrdev, iclass 30, count 0 2006.285.07:48:02.22#ibcon#first serial, iclass 30, count 0 2006.285.07:48:02.22#ibcon#enter sib2, iclass 30, count 0 2006.285.07:48:02.22#ibcon#flushed, iclass 30, count 0 2006.285.07:48:02.22#ibcon#about to write, iclass 30, count 0 2006.285.07:48:02.22#ibcon#wrote, iclass 30, count 0 2006.285.07:48:02.22#ibcon#about to read 3, iclass 30, count 0 2006.285.07:48:02.24#ibcon#read 3, iclass 30, count 0 2006.285.07:48:02.24#ibcon#about to read 4, iclass 30, count 0 2006.285.07:48:02.24#ibcon#read 4, iclass 30, count 0 2006.285.07:48:02.24#ibcon#about to read 5, iclass 30, count 0 2006.285.07:48:02.24#ibcon#read 5, iclass 30, count 0 2006.285.07:48:02.24#ibcon#about to read 6, iclass 30, count 0 2006.285.07:48:02.24#ibcon#read 6, iclass 30, count 0 2006.285.07:48:02.24#ibcon#end of sib2, iclass 30, count 0 2006.285.07:48:02.24#ibcon#*mode == 0, iclass 30, count 0 2006.285.07:48:02.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.07:48:02.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:48:02.24#ibcon#*before write, iclass 30, count 0 2006.285.07:48:02.24#ibcon#enter sib2, iclass 30, count 0 2006.285.07:48:02.24#ibcon#flushed, iclass 30, count 0 2006.285.07:48:02.24#ibcon#about to write, iclass 30, count 0 2006.285.07:48:02.24#ibcon#wrote, iclass 30, count 0 2006.285.07:48:02.24#ibcon#about to read 3, iclass 30, count 0 2006.285.07:48:02.28#ibcon#read 3, iclass 30, count 0 2006.285.07:48:02.28#ibcon#about to read 4, iclass 30, count 0 2006.285.07:48:02.28#ibcon#read 4, iclass 30, count 0 2006.285.07:48:02.28#ibcon#about to read 5, iclass 30, count 0 2006.285.07:48:02.28#ibcon#read 5, iclass 30, count 0 2006.285.07:48:02.28#ibcon#about to read 6, iclass 30, count 0 2006.285.07:48:02.28#ibcon#read 6, iclass 30, count 0 2006.285.07:48:02.28#ibcon#end of sib2, iclass 30, count 0 2006.285.07:48:02.28#ibcon#*after write, iclass 30, count 0 2006.285.07:48:02.28#ibcon#*before return 0, iclass 30, count 0 2006.285.07:48:02.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:48:02.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.07:48:02.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.07:48:02.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.07:48:02.28$vck44/vb=5,4 2006.285.07:48:02.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.07:48:02.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.07:48:02.28#ibcon#ireg 11 cls_cnt 2 2006.285.07:48:02.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:48:02.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:48:02.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:48:02.34#ibcon#enter wrdev, iclass 32, count 2 2006.285.07:48:02.34#ibcon#first serial, iclass 32, count 2 2006.285.07:48:02.34#ibcon#enter sib2, iclass 32, count 2 2006.285.07:48:02.34#ibcon#flushed, iclass 32, count 2 2006.285.07:48:02.34#ibcon#about to write, iclass 32, count 2 2006.285.07:48:02.34#ibcon#wrote, iclass 32, count 2 2006.285.07:48:02.34#ibcon#about to read 3, iclass 32, count 2 2006.285.07:48:02.36#ibcon#read 3, iclass 32, count 2 2006.285.07:48:02.36#ibcon#about to read 4, iclass 32, count 2 2006.285.07:48:02.36#ibcon#read 4, iclass 32, count 2 2006.285.07:48:02.36#ibcon#about to read 5, iclass 32, count 2 2006.285.07:48:02.36#ibcon#read 5, iclass 32, count 2 2006.285.07:48:02.36#ibcon#about to read 6, iclass 32, count 2 2006.285.07:48:02.36#ibcon#read 6, iclass 32, count 2 2006.285.07:48:02.36#ibcon#end of sib2, iclass 32, count 2 2006.285.07:48:02.36#ibcon#*mode == 0, iclass 32, count 2 2006.285.07:48:02.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.07:48:02.36#ibcon#[27=AT05-04\r\n] 2006.285.07:48:02.36#ibcon#*before write, iclass 32, count 2 2006.285.07:48:02.36#ibcon#enter sib2, iclass 32, count 2 2006.285.07:48:02.36#ibcon#flushed, iclass 32, count 2 2006.285.07:48:02.36#ibcon#about to write, iclass 32, count 2 2006.285.07:48:02.36#ibcon#wrote, iclass 32, count 2 2006.285.07:48:02.36#ibcon#about to read 3, iclass 32, count 2 2006.285.07:48:02.39#ibcon#read 3, iclass 32, count 2 2006.285.07:48:02.39#ibcon#about to read 4, iclass 32, count 2 2006.285.07:48:02.39#ibcon#read 4, iclass 32, count 2 2006.285.07:48:02.39#ibcon#about to read 5, iclass 32, count 2 2006.285.07:48:02.39#ibcon#read 5, iclass 32, count 2 2006.285.07:48:02.39#ibcon#about to read 6, iclass 32, count 2 2006.285.07:48:02.39#ibcon#read 6, iclass 32, count 2 2006.285.07:48:02.39#ibcon#end of sib2, iclass 32, count 2 2006.285.07:48:02.39#ibcon#*after write, iclass 32, count 2 2006.285.07:48:02.39#ibcon#*before return 0, iclass 32, count 2 2006.285.07:48:02.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:48:02.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.07:48:02.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.07:48:02.39#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:02.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:48:02.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:48:02.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:48:02.51#ibcon#enter wrdev, iclass 32, count 0 2006.285.07:48:02.51#ibcon#first serial, iclass 32, count 0 2006.285.07:48:02.51#ibcon#enter sib2, iclass 32, count 0 2006.285.07:48:02.51#ibcon#flushed, iclass 32, count 0 2006.285.07:48:02.51#ibcon#about to write, iclass 32, count 0 2006.285.07:48:02.51#ibcon#wrote, iclass 32, count 0 2006.285.07:48:02.51#ibcon#about to read 3, iclass 32, count 0 2006.285.07:48:02.53#ibcon#read 3, iclass 32, count 0 2006.285.07:48:02.53#ibcon#about to read 4, iclass 32, count 0 2006.285.07:48:02.53#ibcon#read 4, iclass 32, count 0 2006.285.07:48:02.53#ibcon#about to read 5, iclass 32, count 0 2006.285.07:48:02.53#ibcon#read 5, iclass 32, count 0 2006.285.07:48:02.53#ibcon#about to read 6, iclass 32, count 0 2006.285.07:48:02.53#ibcon#read 6, iclass 32, count 0 2006.285.07:48:02.53#ibcon#end of sib2, iclass 32, count 0 2006.285.07:48:02.53#ibcon#*mode == 0, iclass 32, count 0 2006.285.07:48:02.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.07:48:02.53#ibcon#[27=USB\r\n] 2006.285.07:48:02.53#ibcon#*before write, iclass 32, count 0 2006.285.07:48:02.53#ibcon#enter sib2, iclass 32, count 0 2006.285.07:48:02.53#ibcon#flushed, iclass 32, count 0 2006.285.07:48:02.53#ibcon#about to write, iclass 32, count 0 2006.285.07:48:02.53#ibcon#wrote, iclass 32, count 0 2006.285.07:48:02.53#ibcon#about to read 3, iclass 32, count 0 2006.285.07:48:02.56#ibcon#read 3, iclass 32, count 0 2006.285.07:48:02.56#ibcon#about to read 4, iclass 32, count 0 2006.285.07:48:02.56#ibcon#read 4, iclass 32, count 0 2006.285.07:48:02.56#ibcon#about to read 5, iclass 32, count 0 2006.285.07:48:02.56#ibcon#read 5, iclass 32, count 0 2006.285.07:48:02.56#ibcon#about to read 6, iclass 32, count 0 2006.285.07:48:02.56#ibcon#read 6, iclass 32, count 0 2006.285.07:48:02.56#ibcon#end of sib2, iclass 32, count 0 2006.285.07:48:02.56#ibcon#*after write, iclass 32, count 0 2006.285.07:48:02.56#ibcon#*before return 0, iclass 32, count 0 2006.285.07:48:02.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:48:02.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.07:48:02.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.07:48:02.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.07:48:02.56$vck44/vblo=6,719.99 2006.285.07:48:02.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.07:48:02.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.07:48:02.56#ibcon#ireg 17 cls_cnt 0 2006.285.07:48:02.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:48:02.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:48:02.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:48:02.56#ibcon#enter wrdev, iclass 34, count 0 2006.285.07:48:02.56#ibcon#first serial, iclass 34, count 0 2006.285.07:48:02.56#ibcon#enter sib2, iclass 34, count 0 2006.285.07:48:02.56#ibcon#flushed, iclass 34, count 0 2006.285.07:48:02.56#ibcon#about to write, iclass 34, count 0 2006.285.07:48:02.56#ibcon#wrote, iclass 34, count 0 2006.285.07:48:02.56#ibcon#about to read 3, iclass 34, count 0 2006.285.07:48:02.58#ibcon#read 3, iclass 34, count 0 2006.285.07:48:02.58#ibcon#about to read 4, iclass 34, count 0 2006.285.07:48:02.58#ibcon#read 4, iclass 34, count 0 2006.285.07:48:02.58#ibcon#about to read 5, iclass 34, count 0 2006.285.07:48:02.58#ibcon#read 5, iclass 34, count 0 2006.285.07:48:02.58#ibcon#about to read 6, iclass 34, count 0 2006.285.07:48:02.58#ibcon#read 6, iclass 34, count 0 2006.285.07:48:02.58#ibcon#end of sib2, iclass 34, count 0 2006.285.07:48:02.58#ibcon#*mode == 0, iclass 34, count 0 2006.285.07:48:02.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.07:48:02.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:48:02.58#ibcon#*before write, iclass 34, count 0 2006.285.07:48:02.58#ibcon#enter sib2, iclass 34, count 0 2006.285.07:48:02.58#ibcon#flushed, iclass 34, count 0 2006.285.07:48:02.58#ibcon#about to write, iclass 34, count 0 2006.285.07:48:02.58#ibcon#wrote, iclass 34, count 0 2006.285.07:48:02.58#ibcon#about to read 3, iclass 34, count 0 2006.285.07:48:02.62#ibcon#read 3, iclass 34, count 0 2006.285.07:48:02.62#ibcon#about to read 4, iclass 34, count 0 2006.285.07:48:02.62#ibcon#read 4, iclass 34, count 0 2006.285.07:48:02.62#ibcon#about to read 5, iclass 34, count 0 2006.285.07:48:02.62#ibcon#read 5, iclass 34, count 0 2006.285.07:48:02.62#ibcon#about to read 6, iclass 34, count 0 2006.285.07:48:02.62#ibcon#read 6, iclass 34, count 0 2006.285.07:48:02.62#ibcon#end of sib2, iclass 34, count 0 2006.285.07:48:02.62#ibcon#*after write, iclass 34, count 0 2006.285.07:48:02.62#ibcon#*before return 0, iclass 34, count 0 2006.285.07:48:02.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:48:02.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.07:48:02.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.07:48:02.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.07:48:02.62$vck44/vb=6,3 2006.285.07:48:02.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.07:48:02.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.07:48:02.62#ibcon#ireg 11 cls_cnt 2 2006.285.07:48:02.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:48:02.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:48:02.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:48:02.68#ibcon#enter wrdev, iclass 36, count 2 2006.285.07:48:02.68#ibcon#first serial, iclass 36, count 2 2006.285.07:48:02.68#ibcon#enter sib2, iclass 36, count 2 2006.285.07:48:02.68#ibcon#flushed, iclass 36, count 2 2006.285.07:48:02.68#ibcon#about to write, iclass 36, count 2 2006.285.07:48:02.68#ibcon#wrote, iclass 36, count 2 2006.285.07:48:02.68#ibcon#about to read 3, iclass 36, count 2 2006.285.07:48:02.70#ibcon#read 3, iclass 36, count 2 2006.285.07:48:02.70#ibcon#about to read 4, iclass 36, count 2 2006.285.07:48:02.70#ibcon#read 4, iclass 36, count 2 2006.285.07:48:02.70#ibcon#about to read 5, iclass 36, count 2 2006.285.07:48:02.70#ibcon#read 5, iclass 36, count 2 2006.285.07:48:02.70#ibcon#about to read 6, iclass 36, count 2 2006.285.07:48:02.70#ibcon#read 6, iclass 36, count 2 2006.285.07:48:02.70#ibcon#end of sib2, iclass 36, count 2 2006.285.07:48:02.70#ibcon#*mode == 0, iclass 36, count 2 2006.285.07:48:02.70#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.07:48:02.70#ibcon#[27=AT06-03\r\n] 2006.285.07:48:02.70#ibcon#*before write, iclass 36, count 2 2006.285.07:48:02.70#ibcon#enter sib2, iclass 36, count 2 2006.285.07:48:02.70#ibcon#flushed, iclass 36, count 2 2006.285.07:48:02.70#ibcon#about to write, iclass 36, count 2 2006.285.07:48:02.70#ibcon#wrote, iclass 36, count 2 2006.285.07:48:02.70#ibcon#about to read 3, iclass 36, count 2 2006.285.07:48:02.73#ibcon#read 3, iclass 36, count 2 2006.285.07:48:02.73#ibcon#about to read 4, iclass 36, count 2 2006.285.07:48:02.73#ibcon#read 4, iclass 36, count 2 2006.285.07:48:02.73#ibcon#about to read 5, iclass 36, count 2 2006.285.07:48:02.73#ibcon#read 5, iclass 36, count 2 2006.285.07:48:02.73#ibcon#about to read 6, iclass 36, count 2 2006.285.07:48:02.73#ibcon#read 6, iclass 36, count 2 2006.285.07:48:02.73#ibcon#end of sib2, iclass 36, count 2 2006.285.07:48:02.73#ibcon#*after write, iclass 36, count 2 2006.285.07:48:02.73#ibcon#*before return 0, iclass 36, count 2 2006.285.07:48:02.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:48:02.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.07:48:02.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.07:48:02.73#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:02.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:48:02.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:48:02.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:48:02.85#ibcon#enter wrdev, iclass 36, count 0 2006.285.07:48:02.85#ibcon#first serial, iclass 36, count 0 2006.285.07:48:02.85#ibcon#enter sib2, iclass 36, count 0 2006.285.07:48:02.85#ibcon#flushed, iclass 36, count 0 2006.285.07:48:02.85#ibcon#about to write, iclass 36, count 0 2006.285.07:48:02.85#ibcon#wrote, iclass 36, count 0 2006.285.07:48:02.85#ibcon#about to read 3, iclass 36, count 0 2006.285.07:48:02.87#ibcon#read 3, iclass 36, count 0 2006.285.07:48:02.87#ibcon#about to read 4, iclass 36, count 0 2006.285.07:48:02.87#ibcon#read 4, iclass 36, count 0 2006.285.07:48:02.87#ibcon#about to read 5, iclass 36, count 0 2006.285.07:48:02.87#ibcon#read 5, iclass 36, count 0 2006.285.07:48:02.87#ibcon#about to read 6, iclass 36, count 0 2006.285.07:48:02.87#ibcon#read 6, iclass 36, count 0 2006.285.07:48:02.87#ibcon#end of sib2, iclass 36, count 0 2006.285.07:48:02.87#ibcon#*mode == 0, iclass 36, count 0 2006.285.07:48:02.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.07:48:02.87#ibcon#[27=USB\r\n] 2006.285.07:48:02.87#ibcon#*before write, iclass 36, count 0 2006.285.07:48:02.87#ibcon#enter sib2, iclass 36, count 0 2006.285.07:48:02.87#ibcon#flushed, iclass 36, count 0 2006.285.07:48:02.87#ibcon#about to write, iclass 36, count 0 2006.285.07:48:02.87#ibcon#wrote, iclass 36, count 0 2006.285.07:48:02.87#ibcon#about to read 3, iclass 36, count 0 2006.285.07:48:02.90#ibcon#read 3, iclass 36, count 0 2006.285.07:48:02.90#ibcon#about to read 4, iclass 36, count 0 2006.285.07:48:02.90#ibcon#read 4, iclass 36, count 0 2006.285.07:48:02.90#ibcon#about to read 5, iclass 36, count 0 2006.285.07:48:02.90#ibcon#read 5, iclass 36, count 0 2006.285.07:48:02.90#ibcon#about to read 6, iclass 36, count 0 2006.285.07:48:02.90#ibcon#read 6, iclass 36, count 0 2006.285.07:48:02.90#ibcon#end of sib2, iclass 36, count 0 2006.285.07:48:02.90#ibcon#*after write, iclass 36, count 0 2006.285.07:48:02.90#ibcon#*before return 0, iclass 36, count 0 2006.285.07:48:02.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:48:02.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.07:48:02.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.07:48:02.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.07:48:02.90$vck44/vblo=7,734.99 2006.285.07:48:02.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.07:48:02.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.07:48:02.90#ibcon#ireg 17 cls_cnt 0 2006.285.07:48:02.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:48:02.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:48:02.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:48:02.90#ibcon#enter wrdev, iclass 38, count 0 2006.285.07:48:02.90#ibcon#first serial, iclass 38, count 0 2006.285.07:48:02.90#ibcon#enter sib2, iclass 38, count 0 2006.285.07:48:02.90#ibcon#flushed, iclass 38, count 0 2006.285.07:48:02.90#ibcon#about to write, iclass 38, count 0 2006.285.07:48:02.90#ibcon#wrote, iclass 38, count 0 2006.285.07:48:02.90#ibcon#about to read 3, iclass 38, count 0 2006.285.07:48:02.92#ibcon#read 3, iclass 38, count 0 2006.285.07:48:02.92#ibcon#about to read 4, iclass 38, count 0 2006.285.07:48:02.92#ibcon#read 4, iclass 38, count 0 2006.285.07:48:02.92#ibcon#about to read 5, iclass 38, count 0 2006.285.07:48:02.92#ibcon#read 5, iclass 38, count 0 2006.285.07:48:02.92#ibcon#about to read 6, iclass 38, count 0 2006.285.07:48:02.92#ibcon#read 6, iclass 38, count 0 2006.285.07:48:02.92#ibcon#end of sib2, iclass 38, count 0 2006.285.07:48:02.92#ibcon#*mode == 0, iclass 38, count 0 2006.285.07:48:02.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.07:48:02.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:48:02.92#ibcon#*before write, iclass 38, count 0 2006.285.07:48:02.92#ibcon#enter sib2, iclass 38, count 0 2006.285.07:48:02.92#ibcon#flushed, iclass 38, count 0 2006.285.07:48:02.92#ibcon#about to write, iclass 38, count 0 2006.285.07:48:02.92#ibcon#wrote, iclass 38, count 0 2006.285.07:48:02.92#ibcon#about to read 3, iclass 38, count 0 2006.285.07:48:02.96#ibcon#read 3, iclass 38, count 0 2006.285.07:48:02.96#ibcon#about to read 4, iclass 38, count 0 2006.285.07:48:02.96#ibcon#read 4, iclass 38, count 0 2006.285.07:48:02.96#ibcon#about to read 5, iclass 38, count 0 2006.285.07:48:02.96#ibcon#read 5, iclass 38, count 0 2006.285.07:48:02.96#ibcon#about to read 6, iclass 38, count 0 2006.285.07:48:02.96#ibcon#read 6, iclass 38, count 0 2006.285.07:48:02.96#ibcon#end of sib2, iclass 38, count 0 2006.285.07:48:02.96#ibcon#*after write, iclass 38, count 0 2006.285.07:48:02.96#ibcon#*before return 0, iclass 38, count 0 2006.285.07:48:02.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:48:02.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.07:48:02.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.07:48:02.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.07:48:02.96$vck44/vb=7,4 2006.285.07:48:02.96#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.07:48:02.96#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.07:48:02.96#ibcon#ireg 11 cls_cnt 2 2006.285.07:48:02.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:48:03.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:48:03.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:48:03.02#ibcon#enter wrdev, iclass 40, count 2 2006.285.07:48:03.02#ibcon#first serial, iclass 40, count 2 2006.285.07:48:03.02#ibcon#enter sib2, iclass 40, count 2 2006.285.07:48:03.02#ibcon#flushed, iclass 40, count 2 2006.285.07:48:03.02#ibcon#about to write, iclass 40, count 2 2006.285.07:48:03.02#ibcon#wrote, iclass 40, count 2 2006.285.07:48:03.02#ibcon#about to read 3, iclass 40, count 2 2006.285.07:48:03.04#ibcon#read 3, iclass 40, count 2 2006.285.07:48:03.04#ibcon#about to read 4, iclass 40, count 2 2006.285.07:48:03.04#ibcon#read 4, iclass 40, count 2 2006.285.07:48:03.04#ibcon#about to read 5, iclass 40, count 2 2006.285.07:48:03.04#ibcon#read 5, iclass 40, count 2 2006.285.07:48:03.04#ibcon#about to read 6, iclass 40, count 2 2006.285.07:48:03.04#ibcon#read 6, iclass 40, count 2 2006.285.07:48:03.04#ibcon#end of sib2, iclass 40, count 2 2006.285.07:48:03.04#ibcon#*mode == 0, iclass 40, count 2 2006.285.07:48:03.04#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.07:48:03.04#ibcon#[27=AT07-04\r\n] 2006.285.07:48:03.04#ibcon#*before write, iclass 40, count 2 2006.285.07:48:03.04#ibcon#enter sib2, iclass 40, count 2 2006.285.07:48:03.04#ibcon#flushed, iclass 40, count 2 2006.285.07:48:03.04#ibcon#about to write, iclass 40, count 2 2006.285.07:48:03.04#ibcon#wrote, iclass 40, count 2 2006.285.07:48:03.04#ibcon#about to read 3, iclass 40, count 2 2006.285.07:48:03.07#ibcon#read 3, iclass 40, count 2 2006.285.07:48:03.07#ibcon#about to read 4, iclass 40, count 2 2006.285.07:48:03.07#ibcon#read 4, iclass 40, count 2 2006.285.07:48:03.07#ibcon#about to read 5, iclass 40, count 2 2006.285.07:48:03.07#ibcon#read 5, iclass 40, count 2 2006.285.07:48:03.07#ibcon#about to read 6, iclass 40, count 2 2006.285.07:48:03.07#ibcon#read 6, iclass 40, count 2 2006.285.07:48:03.07#ibcon#end of sib2, iclass 40, count 2 2006.285.07:48:03.07#ibcon#*after write, iclass 40, count 2 2006.285.07:48:03.07#ibcon#*before return 0, iclass 40, count 2 2006.285.07:48:03.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:48:03.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.07:48:03.07#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.07:48:03.07#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:03.07#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:48:03.19#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:48:03.19#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:48:03.19#ibcon#enter wrdev, iclass 40, count 0 2006.285.07:48:03.19#ibcon#first serial, iclass 40, count 0 2006.285.07:48:03.19#ibcon#enter sib2, iclass 40, count 0 2006.285.07:48:03.19#ibcon#flushed, iclass 40, count 0 2006.285.07:48:03.19#ibcon#about to write, iclass 40, count 0 2006.285.07:48:03.19#ibcon#wrote, iclass 40, count 0 2006.285.07:48:03.19#ibcon#about to read 3, iclass 40, count 0 2006.285.07:48:03.21#ibcon#read 3, iclass 40, count 0 2006.285.07:48:03.21#ibcon#about to read 4, iclass 40, count 0 2006.285.07:48:03.21#ibcon#read 4, iclass 40, count 0 2006.285.07:48:03.21#ibcon#about to read 5, iclass 40, count 0 2006.285.07:48:03.21#ibcon#read 5, iclass 40, count 0 2006.285.07:48:03.21#ibcon#about to read 6, iclass 40, count 0 2006.285.07:48:03.21#ibcon#read 6, iclass 40, count 0 2006.285.07:48:03.21#ibcon#end of sib2, iclass 40, count 0 2006.285.07:48:03.21#ibcon#*mode == 0, iclass 40, count 0 2006.285.07:48:03.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.07:48:03.21#ibcon#[27=USB\r\n] 2006.285.07:48:03.21#ibcon#*before write, iclass 40, count 0 2006.285.07:48:03.21#ibcon#enter sib2, iclass 40, count 0 2006.285.07:48:03.21#ibcon#flushed, iclass 40, count 0 2006.285.07:48:03.21#ibcon#about to write, iclass 40, count 0 2006.285.07:48:03.21#ibcon#wrote, iclass 40, count 0 2006.285.07:48:03.21#ibcon#about to read 3, iclass 40, count 0 2006.285.07:48:03.24#ibcon#read 3, iclass 40, count 0 2006.285.07:48:03.24#ibcon#about to read 4, iclass 40, count 0 2006.285.07:48:03.24#ibcon#read 4, iclass 40, count 0 2006.285.07:48:03.24#ibcon#about to read 5, iclass 40, count 0 2006.285.07:48:03.24#ibcon#read 5, iclass 40, count 0 2006.285.07:48:03.24#ibcon#about to read 6, iclass 40, count 0 2006.285.07:48:03.24#ibcon#read 6, iclass 40, count 0 2006.285.07:48:03.24#ibcon#end of sib2, iclass 40, count 0 2006.285.07:48:03.24#ibcon#*after write, iclass 40, count 0 2006.285.07:48:03.24#ibcon#*before return 0, iclass 40, count 0 2006.285.07:48:03.24#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:48:03.24#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.07:48:03.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.07:48:03.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.07:48:03.24$vck44/vblo=8,744.99 2006.285.07:48:03.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.07:48:03.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.07:48:03.24#ibcon#ireg 17 cls_cnt 0 2006.285.07:48:03.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:48:03.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:48:03.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:48:03.24#ibcon#enter wrdev, iclass 4, count 0 2006.285.07:48:03.24#ibcon#first serial, iclass 4, count 0 2006.285.07:48:03.24#ibcon#enter sib2, iclass 4, count 0 2006.285.07:48:03.24#ibcon#flushed, iclass 4, count 0 2006.285.07:48:03.24#ibcon#about to write, iclass 4, count 0 2006.285.07:48:03.24#ibcon#wrote, iclass 4, count 0 2006.285.07:48:03.24#ibcon#about to read 3, iclass 4, count 0 2006.285.07:48:03.26#ibcon#read 3, iclass 4, count 0 2006.285.07:48:03.26#ibcon#about to read 4, iclass 4, count 0 2006.285.07:48:03.26#ibcon#read 4, iclass 4, count 0 2006.285.07:48:03.26#ibcon#about to read 5, iclass 4, count 0 2006.285.07:48:03.26#ibcon#read 5, iclass 4, count 0 2006.285.07:48:03.26#ibcon#about to read 6, iclass 4, count 0 2006.285.07:48:03.26#ibcon#read 6, iclass 4, count 0 2006.285.07:48:03.26#ibcon#end of sib2, iclass 4, count 0 2006.285.07:48:03.26#ibcon#*mode == 0, iclass 4, count 0 2006.285.07:48:03.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.07:48:03.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:48:03.26#ibcon#*before write, iclass 4, count 0 2006.285.07:48:03.26#ibcon#enter sib2, iclass 4, count 0 2006.285.07:48:03.26#ibcon#flushed, iclass 4, count 0 2006.285.07:48:03.26#ibcon#about to write, iclass 4, count 0 2006.285.07:48:03.26#ibcon#wrote, iclass 4, count 0 2006.285.07:48:03.26#ibcon#about to read 3, iclass 4, count 0 2006.285.07:48:03.30#ibcon#read 3, iclass 4, count 0 2006.285.07:48:03.30#ibcon#about to read 4, iclass 4, count 0 2006.285.07:48:03.30#ibcon#read 4, iclass 4, count 0 2006.285.07:48:03.30#ibcon#about to read 5, iclass 4, count 0 2006.285.07:48:03.30#ibcon#read 5, iclass 4, count 0 2006.285.07:48:03.30#ibcon#about to read 6, iclass 4, count 0 2006.285.07:48:03.30#ibcon#read 6, iclass 4, count 0 2006.285.07:48:03.30#ibcon#end of sib2, iclass 4, count 0 2006.285.07:48:03.30#ibcon#*after write, iclass 4, count 0 2006.285.07:48:03.30#ibcon#*before return 0, iclass 4, count 0 2006.285.07:48:03.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:48:03.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.07:48:03.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.07:48:03.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.07:48:03.30$vck44/vb=8,4 2006.285.07:48:03.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.07:48:03.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.07:48:03.30#ibcon#ireg 11 cls_cnt 2 2006.285.07:48:03.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:48:03.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:48:03.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:48:03.36#ibcon#enter wrdev, iclass 6, count 2 2006.285.07:48:03.36#ibcon#first serial, iclass 6, count 2 2006.285.07:48:03.36#ibcon#enter sib2, iclass 6, count 2 2006.285.07:48:03.36#ibcon#flushed, iclass 6, count 2 2006.285.07:48:03.36#ibcon#about to write, iclass 6, count 2 2006.285.07:48:03.36#ibcon#wrote, iclass 6, count 2 2006.285.07:48:03.36#ibcon#about to read 3, iclass 6, count 2 2006.285.07:48:03.38#ibcon#read 3, iclass 6, count 2 2006.285.07:48:03.38#ibcon#about to read 4, iclass 6, count 2 2006.285.07:48:03.38#ibcon#read 4, iclass 6, count 2 2006.285.07:48:03.38#ibcon#about to read 5, iclass 6, count 2 2006.285.07:48:03.38#ibcon#read 5, iclass 6, count 2 2006.285.07:48:03.38#ibcon#about to read 6, iclass 6, count 2 2006.285.07:48:03.38#ibcon#read 6, iclass 6, count 2 2006.285.07:48:03.38#ibcon#end of sib2, iclass 6, count 2 2006.285.07:48:03.38#ibcon#*mode == 0, iclass 6, count 2 2006.285.07:48:03.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.07:48:03.38#ibcon#[27=AT08-04\r\n] 2006.285.07:48:03.38#ibcon#*before write, iclass 6, count 2 2006.285.07:48:03.38#ibcon#enter sib2, iclass 6, count 2 2006.285.07:48:03.38#ibcon#flushed, iclass 6, count 2 2006.285.07:48:03.38#ibcon#about to write, iclass 6, count 2 2006.285.07:48:03.38#ibcon#wrote, iclass 6, count 2 2006.285.07:48:03.38#ibcon#about to read 3, iclass 6, count 2 2006.285.07:48:03.41#ibcon#read 3, iclass 6, count 2 2006.285.07:48:03.41#ibcon#about to read 4, iclass 6, count 2 2006.285.07:48:03.41#ibcon#read 4, iclass 6, count 2 2006.285.07:48:03.41#ibcon#about to read 5, iclass 6, count 2 2006.285.07:48:03.41#ibcon#read 5, iclass 6, count 2 2006.285.07:48:03.41#ibcon#about to read 6, iclass 6, count 2 2006.285.07:48:03.41#ibcon#read 6, iclass 6, count 2 2006.285.07:48:03.41#ibcon#end of sib2, iclass 6, count 2 2006.285.07:48:03.41#ibcon#*after write, iclass 6, count 2 2006.285.07:48:03.41#ibcon#*before return 0, iclass 6, count 2 2006.285.07:48:03.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:48:03.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.07:48:03.41#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.07:48:03.41#ibcon#ireg 7 cls_cnt 0 2006.285.07:48:03.41#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:48:03.53#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:48:03.53#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:48:03.53#ibcon#enter wrdev, iclass 6, count 0 2006.285.07:48:03.53#ibcon#first serial, iclass 6, count 0 2006.285.07:48:03.53#ibcon#enter sib2, iclass 6, count 0 2006.285.07:48:03.53#ibcon#flushed, iclass 6, count 0 2006.285.07:48:03.53#ibcon#about to write, iclass 6, count 0 2006.285.07:48:03.53#ibcon#wrote, iclass 6, count 0 2006.285.07:48:03.53#ibcon#about to read 3, iclass 6, count 0 2006.285.07:48:03.55#ibcon#read 3, iclass 6, count 0 2006.285.07:48:03.55#ibcon#about to read 4, iclass 6, count 0 2006.285.07:48:03.55#ibcon#read 4, iclass 6, count 0 2006.285.07:48:03.55#ibcon#about to read 5, iclass 6, count 0 2006.285.07:48:03.55#ibcon#read 5, iclass 6, count 0 2006.285.07:48:03.55#ibcon#about to read 6, iclass 6, count 0 2006.285.07:48:03.55#ibcon#read 6, iclass 6, count 0 2006.285.07:48:03.55#ibcon#end of sib2, iclass 6, count 0 2006.285.07:48:03.55#ibcon#*mode == 0, iclass 6, count 0 2006.285.07:48:03.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.07:48:03.55#ibcon#[27=USB\r\n] 2006.285.07:48:03.55#ibcon#*before write, iclass 6, count 0 2006.285.07:48:03.55#ibcon#enter sib2, iclass 6, count 0 2006.285.07:48:03.55#ibcon#flushed, iclass 6, count 0 2006.285.07:48:03.55#ibcon#about to write, iclass 6, count 0 2006.285.07:48:03.55#ibcon#wrote, iclass 6, count 0 2006.285.07:48:03.55#ibcon#about to read 3, iclass 6, count 0 2006.285.07:48:03.58#ibcon#read 3, iclass 6, count 0 2006.285.07:48:03.58#ibcon#about to read 4, iclass 6, count 0 2006.285.07:48:03.58#ibcon#read 4, iclass 6, count 0 2006.285.07:48:03.58#ibcon#about to read 5, iclass 6, count 0 2006.285.07:48:03.58#ibcon#read 5, iclass 6, count 0 2006.285.07:48:03.58#ibcon#about to read 6, iclass 6, count 0 2006.285.07:48:03.58#ibcon#read 6, iclass 6, count 0 2006.285.07:48:03.58#ibcon#end of sib2, iclass 6, count 0 2006.285.07:48:03.58#ibcon#*after write, iclass 6, count 0 2006.285.07:48:03.58#ibcon#*before return 0, iclass 6, count 0 2006.285.07:48:03.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:48:03.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.07:48:03.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.07:48:03.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.07:48:03.58$vck44/vabw=wide 2006.285.07:48:03.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.07:48:03.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.07:48:03.58#ibcon#ireg 8 cls_cnt 0 2006.285.07:48:03.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:48:03.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:48:03.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:48:03.58#ibcon#enter wrdev, iclass 10, count 0 2006.285.07:48:03.58#ibcon#first serial, iclass 10, count 0 2006.285.07:48:03.58#ibcon#enter sib2, iclass 10, count 0 2006.285.07:48:03.58#ibcon#flushed, iclass 10, count 0 2006.285.07:48:03.58#ibcon#about to write, iclass 10, count 0 2006.285.07:48:03.58#ibcon#wrote, iclass 10, count 0 2006.285.07:48:03.58#ibcon#about to read 3, iclass 10, count 0 2006.285.07:48:03.60#ibcon#read 3, iclass 10, count 0 2006.285.07:48:03.60#ibcon#about to read 4, iclass 10, count 0 2006.285.07:48:03.60#ibcon#read 4, iclass 10, count 0 2006.285.07:48:03.60#ibcon#about to read 5, iclass 10, count 0 2006.285.07:48:03.60#ibcon#read 5, iclass 10, count 0 2006.285.07:48:03.60#ibcon#about to read 6, iclass 10, count 0 2006.285.07:48:03.60#ibcon#read 6, iclass 10, count 0 2006.285.07:48:03.60#ibcon#end of sib2, iclass 10, count 0 2006.285.07:48:03.60#ibcon#*mode == 0, iclass 10, count 0 2006.285.07:48:03.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.07:48:03.60#ibcon#[25=BW32\r\n] 2006.285.07:48:03.60#ibcon#*before write, iclass 10, count 0 2006.285.07:48:03.60#ibcon#enter sib2, iclass 10, count 0 2006.285.07:48:03.60#ibcon#flushed, iclass 10, count 0 2006.285.07:48:03.60#ibcon#about to write, iclass 10, count 0 2006.285.07:48:03.60#ibcon#wrote, iclass 10, count 0 2006.285.07:48:03.60#ibcon#about to read 3, iclass 10, count 0 2006.285.07:48:03.63#ibcon#read 3, iclass 10, count 0 2006.285.07:48:03.63#ibcon#about to read 4, iclass 10, count 0 2006.285.07:48:03.63#ibcon#read 4, iclass 10, count 0 2006.285.07:48:03.63#ibcon#about to read 5, iclass 10, count 0 2006.285.07:48:03.63#ibcon#read 5, iclass 10, count 0 2006.285.07:48:03.63#ibcon#about to read 6, iclass 10, count 0 2006.285.07:48:03.63#ibcon#read 6, iclass 10, count 0 2006.285.07:48:03.63#ibcon#end of sib2, iclass 10, count 0 2006.285.07:48:03.63#ibcon#*after write, iclass 10, count 0 2006.285.07:48:03.63#ibcon#*before return 0, iclass 10, count 0 2006.285.07:48:03.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:48:03.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.07:48:03.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.07:48:03.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.07:48:03.63$vck44/vbbw=wide 2006.285.07:48:03.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.07:48:03.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.07:48:03.63#ibcon#ireg 8 cls_cnt 0 2006.285.07:48:03.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:48:03.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:48:03.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:48:03.70#ibcon#enter wrdev, iclass 12, count 0 2006.285.07:48:03.70#ibcon#first serial, iclass 12, count 0 2006.285.07:48:03.70#ibcon#enter sib2, iclass 12, count 0 2006.285.07:48:03.70#ibcon#flushed, iclass 12, count 0 2006.285.07:48:03.70#ibcon#about to write, iclass 12, count 0 2006.285.07:48:03.70#ibcon#wrote, iclass 12, count 0 2006.285.07:48:03.70#ibcon#about to read 3, iclass 12, count 0 2006.285.07:48:03.72#ibcon#read 3, iclass 12, count 0 2006.285.07:48:03.72#ibcon#about to read 4, iclass 12, count 0 2006.285.07:48:03.72#ibcon#read 4, iclass 12, count 0 2006.285.07:48:03.72#ibcon#about to read 5, iclass 12, count 0 2006.285.07:48:03.72#ibcon#read 5, iclass 12, count 0 2006.285.07:48:03.72#ibcon#about to read 6, iclass 12, count 0 2006.285.07:48:03.72#ibcon#read 6, iclass 12, count 0 2006.285.07:48:03.72#ibcon#end of sib2, iclass 12, count 0 2006.285.07:48:03.72#ibcon#*mode == 0, iclass 12, count 0 2006.285.07:48:03.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.07:48:03.72#ibcon#[27=BW32\r\n] 2006.285.07:48:03.72#ibcon#*before write, iclass 12, count 0 2006.285.07:48:03.72#ibcon#enter sib2, iclass 12, count 0 2006.285.07:48:03.72#ibcon#flushed, iclass 12, count 0 2006.285.07:48:03.72#ibcon#about to write, iclass 12, count 0 2006.285.07:48:03.72#ibcon#wrote, iclass 12, count 0 2006.285.07:48:03.72#ibcon#about to read 3, iclass 12, count 0 2006.285.07:48:03.75#ibcon#read 3, iclass 12, count 0 2006.285.07:48:03.75#ibcon#about to read 4, iclass 12, count 0 2006.285.07:48:03.75#ibcon#read 4, iclass 12, count 0 2006.285.07:48:03.75#ibcon#about to read 5, iclass 12, count 0 2006.285.07:48:03.75#ibcon#read 5, iclass 12, count 0 2006.285.07:48:03.75#ibcon#about to read 6, iclass 12, count 0 2006.285.07:48:03.75#ibcon#read 6, iclass 12, count 0 2006.285.07:48:03.75#ibcon#end of sib2, iclass 12, count 0 2006.285.07:48:03.75#ibcon#*after write, iclass 12, count 0 2006.285.07:48:03.75#ibcon#*before return 0, iclass 12, count 0 2006.285.07:48:03.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:48:03.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.07:48:03.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.07:48:03.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.07:48:03.75$setupk4/ifdk4 2006.285.07:48:03.75$ifdk4/lo= 2006.285.07:48:03.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:48:03.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:48:03.75$ifdk4/patch= 2006.285.07:48:03.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:48:03.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:48:03.75$setupk4/!*+20s 2006.285.07:48:08.81#abcon#<5=/04 2.3 4.4 23.29 781014.4\r\n> 2006.285.07:48:08.83#abcon#{5=INTERFACE CLEAR} 2006.285.07:48:08.89#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:48:17.13#trakl#Source acquired 2006.285.07:48:18.27$setupk4/"tpicd 2006.285.07:48:18.27$setupk4/echo=off 2006.285.07:48:18.27$setupk4/xlog=off 2006.285.07:48:18.27:!2006.285.07:49:14 2006.285.07:48:19.13#flagr#flagr/antenna,acquired 2006.285.07:49:14.00:preob 2006.285.07:49:14.13/onsource/TRACKING 2006.285.07:49:14.13:!2006.285.07:49:24 2006.285.07:49:24.00:"tape 2006.285.07:49:24.00:"st=record 2006.285.07:49:24.00:data_valid=on 2006.285.07:49:24.00:midob 2006.285.07:49:25.14/onsource/TRACKING 2006.285.07:49:25.14/wx/23.26,1014.5,78 2006.285.07:49:25.35/cable/+6.4722E-03 2006.285.07:49:26.44/va/01,07,usb,yes,32,35 2006.285.07:49:26.44/va/02,06,usb,yes,32,33 2006.285.07:49:26.44/va/03,07,usb,yes,32,34 2006.285.07:49:26.44/va/04,06,usb,yes,33,35 2006.285.07:49:26.44/va/05,03,usb,yes,33,33 2006.285.07:49:26.44/va/06,04,usb,yes,30,29 2006.285.07:49:26.44/va/07,04,usb,yes,30,31 2006.285.07:49:26.44/va/08,03,usb,yes,31,38 2006.285.07:49:26.67/valo/01,524.99,yes,locked 2006.285.07:49:26.67/valo/02,534.99,yes,locked 2006.285.07:49:26.67/valo/03,564.99,yes,locked 2006.285.07:49:26.67/valo/04,624.99,yes,locked 2006.285.07:49:26.67/valo/05,734.99,yes,locked 2006.285.07:49:26.67/valo/06,814.99,yes,locked 2006.285.07:49:26.67/valo/07,864.99,yes,locked 2006.285.07:49:26.67/valo/08,884.99,yes,locked 2006.285.07:49:27.76/vb/01,04,usb,yes,32,29 2006.285.07:49:27.76/vb/02,05,usb,yes,30,30 2006.285.07:49:27.76/vb/03,04,usb,yes,30,34 2006.285.07:49:27.76/vb/04,05,usb,yes,31,30 2006.285.07:49:27.76/vb/05,04,usb,yes,27,29 2006.285.07:49:27.76/vb/06,03,usb,yes,39,34 2006.285.07:49:27.76/vb/07,04,usb,yes,31,31 2006.285.07:49:27.76/vb/08,04,usb,yes,28,32 2006.285.07:49:27.99/vblo/01,629.99,yes,locked 2006.285.07:49:27.99/vblo/02,634.99,yes,locked 2006.285.07:49:27.99/vblo/03,649.99,yes,locked 2006.285.07:49:27.99/vblo/04,679.99,yes,locked 2006.285.07:49:27.99/vblo/05,709.99,yes,locked 2006.285.07:49:27.99/vblo/06,719.99,yes,locked 2006.285.07:49:27.99/vblo/07,734.99,yes,locked 2006.285.07:49:27.99/vblo/08,744.99,yes,locked 2006.285.07:49:28.14/vabw/8 2006.285.07:49:28.29/vbbw/8 2006.285.07:49:28.38/xfe/off,on,12.2 2006.285.07:49:28.76/ifatt/23,28,28,28 2006.285.07:49:29.07/fmout-gps/S +2.83E-07 2006.285.07:49:29.09:!2006.285.07:50:24 2006.285.07:50:24.01:data_valid=off 2006.285.07:50:24.01:"et 2006.285.07:50:24.01:!+3s 2006.285.07:50:27.02:"tape 2006.285.07:50:27.02:postob 2006.285.07:50:27.22/cable/+6.4749E-03 2006.285.07:50:27.22/wx/23.23,1014.5,78 2006.285.07:50:27.28/fmout-gps/S +2.82E-07 2006.285.07:50:27.28:scan_name=285-0753,jd0610,80 2006.285.07:50:27.28:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.285.07:50:28.14#flagr#flagr/antenna,new-source 2006.285.07:50:28.14:checkk5 2006.285.07:50:28.60/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:50:29.00/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:50:29.36/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:50:29.73/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:50:30.07/chk_obsdata//k5ts1/T2850749??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.07:50:30.47/chk_obsdata//k5ts2/T2850749??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.07:50:30.86/chk_obsdata//k5ts3/T2850749??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.07:50:31.24/chk_obsdata//k5ts4/T2850749??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.07:50:31.96/k5log//k5ts1_log_newline 2006.285.07:50:32.93/k5log//k5ts2_log_newline 2006.285.07:50:33.65/k5log//k5ts3_log_newline 2006.285.07:50:34.46/k5log//k5ts4_log_newline 2006.285.07:50:34.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:50:34.48:setupk4=1 2006.285.07:50:34.48$setupk4/echo=on 2006.285.07:50:34.48$setupk4/pcalon 2006.285.07:50:34.48$pcalon/"no phase cal control is implemented here 2006.285.07:50:34.48$setupk4/"tpicd=stop 2006.285.07:50:34.48$setupk4/"rec=synch_on 2006.285.07:50:34.48$setupk4/"rec_mode=128 2006.285.07:50:34.48$setupk4/!* 2006.285.07:50:34.48$setupk4/recpk4 2006.285.07:50:34.48$recpk4/recpatch= 2006.285.07:50:34.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:50:34.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:50:34.49$setupk4/vck44 2006.285.07:50:34.49$vck44/valo=1,524.99 2006.285.07:50:34.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.07:50:34.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.07:50:34.49#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:34.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:50:34.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:50:34.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:50:34.49#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:50:34.49#ibcon#first serial, iclass 3, count 0 2006.285.07:50:34.49#ibcon#enter sib2, iclass 3, count 0 2006.285.07:50:34.49#ibcon#flushed, iclass 3, count 0 2006.285.07:50:34.49#ibcon#about to write, iclass 3, count 0 2006.285.07:50:34.49#ibcon#wrote, iclass 3, count 0 2006.285.07:50:34.49#ibcon#about to read 3, iclass 3, count 0 2006.285.07:50:34.50#ibcon#read 3, iclass 3, count 0 2006.285.07:50:34.50#ibcon#about to read 4, iclass 3, count 0 2006.285.07:50:34.50#ibcon#read 4, iclass 3, count 0 2006.285.07:50:34.50#ibcon#about to read 5, iclass 3, count 0 2006.285.07:50:34.50#ibcon#read 5, iclass 3, count 0 2006.285.07:50:34.50#ibcon#about to read 6, iclass 3, count 0 2006.285.07:50:34.50#ibcon#read 6, iclass 3, count 0 2006.285.07:50:34.50#ibcon#end of sib2, iclass 3, count 0 2006.285.07:50:34.50#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:50:34.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:50:34.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:50:34.50#ibcon#*before write, iclass 3, count 0 2006.285.07:50:34.50#ibcon#enter sib2, iclass 3, count 0 2006.285.07:50:34.50#ibcon#flushed, iclass 3, count 0 2006.285.07:50:34.50#ibcon#about to write, iclass 3, count 0 2006.285.07:50:34.50#ibcon#wrote, iclass 3, count 0 2006.285.07:50:34.50#ibcon#about to read 3, iclass 3, count 0 2006.285.07:50:34.55#ibcon#read 3, iclass 3, count 0 2006.285.07:50:34.55#ibcon#about to read 4, iclass 3, count 0 2006.285.07:50:34.55#ibcon#read 4, iclass 3, count 0 2006.285.07:50:34.55#ibcon#about to read 5, iclass 3, count 0 2006.285.07:50:34.55#ibcon#read 5, iclass 3, count 0 2006.285.07:50:34.55#ibcon#about to read 6, iclass 3, count 0 2006.285.07:50:34.55#ibcon#read 6, iclass 3, count 0 2006.285.07:50:34.55#ibcon#end of sib2, iclass 3, count 0 2006.285.07:50:34.55#ibcon#*after write, iclass 3, count 0 2006.285.07:50:34.55#ibcon#*before return 0, iclass 3, count 0 2006.285.07:50:34.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:50:34.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:50:34.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:50:34.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:50:34.55$vck44/va=1,7 2006.285.07:50:34.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.07:50:34.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.07:50:34.55#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:34.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:50:34.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:50:34.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:50:34.55#ibcon#enter wrdev, iclass 5, count 2 2006.285.07:50:34.55#ibcon#first serial, iclass 5, count 2 2006.285.07:50:34.55#ibcon#enter sib2, iclass 5, count 2 2006.285.07:50:34.55#ibcon#flushed, iclass 5, count 2 2006.285.07:50:34.55#ibcon#about to write, iclass 5, count 2 2006.285.07:50:34.55#ibcon#wrote, iclass 5, count 2 2006.285.07:50:34.55#ibcon#about to read 3, iclass 5, count 2 2006.285.07:50:34.57#ibcon#read 3, iclass 5, count 2 2006.285.07:50:34.57#ibcon#about to read 4, iclass 5, count 2 2006.285.07:50:34.57#ibcon#read 4, iclass 5, count 2 2006.285.07:50:34.57#ibcon#about to read 5, iclass 5, count 2 2006.285.07:50:34.57#ibcon#read 5, iclass 5, count 2 2006.285.07:50:34.57#ibcon#about to read 6, iclass 5, count 2 2006.285.07:50:34.57#ibcon#read 6, iclass 5, count 2 2006.285.07:50:34.57#ibcon#end of sib2, iclass 5, count 2 2006.285.07:50:34.57#ibcon#*mode == 0, iclass 5, count 2 2006.285.07:50:34.57#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.07:50:34.57#ibcon#[25=AT01-07\r\n] 2006.285.07:50:34.57#ibcon#*before write, iclass 5, count 2 2006.285.07:50:34.57#ibcon#enter sib2, iclass 5, count 2 2006.285.07:50:34.57#ibcon#flushed, iclass 5, count 2 2006.285.07:50:34.57#ibcon#about to write, iclass 5, count 2 2006.285.07:50:34.57#ibcon#wrote, iclass 5, count 2 2006.285.07:50:34.57#ibcon#about to read 3, iclass 5, count 2 2006.285.07:50:34.60#ibcon#read 3, iclass 5, count 2 2006.285.07:50:34.60#ibcon#about to read 4, iclass 5, count 2 2006.285.07:50:34.60#ibcon#read 4, iclass 5, count 2 2006.285.07:50:34.60#ibcon#about to read 5, iclass 5, count 2 2006.285.07:50:34.60#ibcon#read 5, iclass 5, count 2 2006.285.07:50:34.60#ibcon#about to read 6, iclass 5, count 2 2006.285.07:50:34.60#ibcon#read 6, iclass 5, count 2 2006.285.07:50:34.60#ibcon#end of sib2, iclass 5, count 2 2006.285.07:50:34.60#ibcon#*after write, iclass 5, count 2 2006.285.07:50:34.60#ibcon#*before return 0, iclass 5, count 2 2006.285.07:50:34.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:50:34.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:50:34.60#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.07:50:34.60#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:34.60#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:50:34.72#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:50:34.72#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:50:34.72#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:50:34.72#ibcon#first serial, iclass 5, count 0 2006.285.07:50:34.72#ibcon#enter sib2, iclass 5, count 0 2006.285.07:50:34.72#ibcon#flushed, iclass 5, count 0 2006.285.07:50:34.72#ibcon#about to write, iclass 5, count 0 2006.285.07:50:34.72#ibcon#wrote, iclass 5, count 0 2006.285.07:50:34.72#ibcon#about to read 3, iclass 5, count 0 2006.285.07:50:34.74#ibcon#read 3, iclass 5, count 0 2006.285.07:50:34.74#ibcon#about to read 4, iclass 5, count 0 2006.285.07:50:34.74#ibcon#read 4, iclass 5, count 0 2006.285.07:50:34.74#ibcon#about to read 5, iclass 5, count 0 2006.285.07:50:34.74#ibcon#read 5, iclass 5, count 0 2006.285.07:50:34.74#ibcon#about to read 6, iclass 5, count 0 2006.285.07:50:34.74#ibcon#read 6, iclass 5, count 0 2006.285.07:50:34.74#ibcon#end of sib2, iclass 5, count 0 2006.285.07:50:34.74#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:50:34.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:50:34.74#ibcon#[25=USB\r\n] 2006.285.07:50:34.74#ibcon#*before write, iclass 5, count 0 2006.285.07:50:34.74#ibcon#enter sib2, iclass 5, count 0 2006.285.07:50:34.74#ibcon#flushed, iclass 5, count 0 2006.285.07:50:34.74#ibcon#about to write, iclass 5, count 0 2006.285.07:50:34.74#ibcon#wrote, iclass 5, count 0 2006.285.07:50:34.74#ibcon#about to read 3, iclass 5, count 0 2006.285.07:50:34.77#ibcon#read 3, iclass 5, count 0 2006.285.07:50:34.77#ibcon#about to read 4, iclass 5, count 0 2006.285.07:50:34.77#ibcon#read 4, iclass 5, count 0 2006.285.07:50:34.77#ibcon#about to read 5, iclass 5, count 0 2006.285.07:50:34.77#ibcon#read 5, iclass 5, count 0 2006.285.07:50:34.77#ibcon#about to read 6, iclass 5, count 0 2006.285.07:50:34.77#ibcon#read 6, iclass 5, count 0 2006.285.07:50:34.77#ibcon#end of sib2, iclass 5, count 0 2006.285.07:50:34.77#ibcon#*after write, iclass 5, count 0 2006.285.07:50:34.77#ibcon#*before return 0, iclass 5, count 0 2006.285.07:50:34.77#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:50:34.77#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:50:34.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:50:34.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:50:34.77$vck44/valo=2,534.99 2006.285.07:50:34.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.07:50:34.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.07:50:34.77#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:34.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:50:34.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:50:34.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:50:34.77#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:50:34.77#ibcon#first serial, iclass 7, count 0 2006.285.07:50:34.77#ibcon#enter sib2, iclass 7, count 0 2006.285.07:50:34.77#ibcon#flushed, iclass 7, count 0 2006.285.07:50:34.77#ibcon#about to write, iclass 7, count 0 2006.285.07:50:34.77#ibcon#wrote, iclass 7, count 0 2006.285.07:50:34.77#ibcon#about to read 3, iclass 7, count 0 2006.285.07:50:34.79#ibcon#read 3, iclass 7, count 0 2006.285.07:50:34.79#ibcon#about to read 4, iclass 7, count 0 2006.285.07:50:34.79#ibcon#read 4, iclass 7, count 0 2006.285.07:50:34.79#ibcon#about to read 5, iclass 7, count 0 2006.285.07:50:34.79#ibcon#read 5, iclass 7, count 0 2006.285.07:50:34.79#ibcon#about to read 6, iclass 7, count 0 2006.285.07:50:34.79#ibcon#read 6, iclass 7, count 0 2006.285.07:50:34.79#ibcon#end of sib2, iclass 7, count 0 2006.285.07:50:34.79#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:50:34.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:50:34.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:50:34.79#ibcon#*before write, iclass 7, count 0 2006.285.07:50:34.79#ibcon#enter sib2, iclass 7, count 0 2006.285.07:50:34.79#ibcon#flushed, iclass 7, count 0 2006.285.07:50:34.79#ibcon#about to write, iclass 7, count 0 2006.285.07:50:34.79#ibcon#wrote, iclass 7, count 0 2006.285.07:50:34.79#ibcon#about to read 3, iclass 7, count 0 2006.285.07:50:34.83#ibcon#read 3, iclass 7, count 0 2006.285.07:50:34.83#ibcon#about to read 4, iclass 7, count 0 2006.285.07:50:34.83#ibcon#read 4, iclass 7, count 0 2006.285.07:50:34.83#ibcon#about to read 5, iclass 7, count 0 2006.285.07:50:34.83#ibcon#read 5, iclass 7, count 0 2006.285.07:50:34.83#ibcon#about to read 6, iclass 7, count 0 2006.285.07:50:34.83#ibcon#read 6, iclass 7, count 0 2006.285.07:50:34.83#ibcon#end of sib2, iclass 7, count 0 2006.285.07:50:34.83#ibcon#*after write, iclass 7, count 0 2006.285.07:50:34.83#ibcon#*before return 0, iclass 7, count 0 2006.285.07:50:34.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:50:34.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:50:34.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:50:34.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:50:34.83$vck44/va=2,6 2006.285.07:50:34.83#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.07:50:34.83#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.07:50:34.83#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:34.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:50:34.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:50:34.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:50:34.89#ibcon#enter wrdev, iclass 11, count 2 2006.285.07:50:34.89#ibcon#first serial, iclass 11, count 2 2006.285.07:50:34.89#ibcon#enter sib2, iclass 11, count 2 2006.285.07:50:34.89#ibcon#flushed, iclass 11, count 2 2006.285.07:50:34.89#ibcon#about to write, iclass 11, count 2 2006.285.07:50:34.89#ibcon#wrote, iclass 11, count 2 2006.285.07:50:34.89#ibcon#about to read 3, iclass 11, count 2 2006.285.07:50:34.91#ibcon#read 3, iclass 11, count 2 2006.285.07:50:34.91#ibcon#about to read 4, iclass 11, count 2 2006.285.07:50:34.91#ibcon#read 4, iclass 11, count 2 2006.285.07:50:34.91#ibcon#about to read 5, iclass 11, count 2 2006.285.07:50:34.91#ibcon#read 5, iclass 11, count 2 2006.285.07:50:34.91#ibcon#about to read 6, iclass 11, count 2 2006.285.07:50:34.91#ibcon#read 6, iclass 11, count 2 2006.285.07:50:34.91#ibcon#end of sib2, iclass 11, count 2 2006.285.07:50:34.91#ibcon#*mode == 0, iclass 11, count 2 2006.285.07:50:34.91#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.07:50:34.91#ibcon#[25=AT02-06\r\n] 2006.285.07:50:34.91#ibcon#*before write, iclass 11, count 2 2006.285.07:50:34.91#ibcon#enter sib2, iclass 11, count 2 2006.285.07:50:34.91#ibcon#flushed, iclass 11, count 2 2006.285.07:50:34.91#ibcon#about to write, iclass 11, count 2 2006.285.07:50:34.91#ibcon#wrote, iclass 11, count 2 2006.285.07:50:34.91#ibcon#about to read 3, iclass 11, count 2 2006.285.07:50:34.94#ibcon#read 3, iclass 11, count 2 2006.285.07:50:34.94#ibcon#about to read 4, iclass 11, count 2 2006.285.07:50:34.94#ibcon#read 4, iclass 11, count 2 2006.285.07:50:34.94#ibcon#about to read 5, iclass 11, count 2 2006.285.07:50:34.94#ibcon#read 5, iclass 11, count 2 2006.285.07:50:34.94#ibcon#about to read 6, iclass 11, count 2 2006.285.07:50:34.94#ibcon#read 6, iclass 11, count 2 2006.285.07:50:34.94#ibcon#end of sib2, iclass 11, count 2 2006.285.07:50:34.94#ibcon#*after write, iclass 11, count 2 2006.285.07:50:34.94#ibcon#*before return 0, iclass 11, count 2 2006.285.07:50:34.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:50:34.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:50:34.94#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.07:50:34.94#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:34.94#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:50:35.06#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:50:35.06#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:50:35.06#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:50:35.06#ibcon#first serial, iclass 11, count 0 2006.285.07:50:35.06#ibcon#enter sib2, iclass 11, count 0 2006.285.07:50:35.06#ibcon#flushed, iclass 11, count 0 2006.285.07:50:35.06#ibcon#about to write, iclass 11, count 0 2006.285.07:50:35.06#ibcon#wrote, iclass 11, count 0 2006.285.07:50:35.06#ibcon#about to read 3, iclass 11, count 0 2006.285.07:50:35.08#ibcon#read 3, iclass 11, count 0 2006.285.07:50:35.08#ibcon#about to read 4, iclass 11, count 0 2006.285.07:50:35.08#ibcon#read 4, iclass 11, count 0 2006.285.07:50:35.08#ibcon#about to read 5, iclass 11, count 0 2006.285.07:50:35.08#ibcon#read 5, iclass 11, count 0 2006.285.07:50:35.08#ibcon#about to read 6, iclass 11, count 0 2006.285.07:50:35.08#ibcon#read 6, iclass 11, count 0 2006.285.07:50:35.08#ibcon#end of sib2, iclass 11, count 0 2006.285.07:50:35.08#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:50:35.08#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:50:35.08#ibcon#[25=USB\r\n] 2006.285.07:50:35.08#ibcon#*before write, iclass 11, count 0 2006.285.07:50:35.08#ibcon#enter sib2, iclass 11, count 0 2006.285.07:50:35.08#ibcon#flushed, iclass 11, count 0 2006.285.07:50:35.08#ibcon#about to write, iclass 11, count 0 2006.285.07:50:35.08#ibcon#wrote, iclass 11, count 0 2006.285.07:50:35.08#ibcon#about to read 3, iclass 11, count 0 2006.285.07:50:35.11#ibcon#read 3, iclass 11, count 0 2006.285.07:50:35.11#ibcon#about to read 4, iclass 11, count 0 2006.285.07:50:35.11#ibcon#read 4, iclass 11, count 0 2006.285.07:50:35.11#ibcon#about to read 5, iclass 11, count 0 2006.285.07:50:35.11#ibcon#read 5, iclass 11, count 0 2006.285.07:50:35.11#ibcon#about to read 6, iclass 11, count 0 2006.285.07:50:35.11#ibcon#read 6, iclass 11, count 0 2006.285.07:50:35.11#ibcon#end of sib2, iclass 11, count 0 2006.285.07:50:35.11#ibcon#*after write, iclass 11, count 0 2006.285.07:50:35.11#ibcon#*before return 0, iclass 11, count 0 2006.285.07:50:35.11#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:50:35.11#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:50:35.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:50:35.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:50:35.11$vck44/valo=3,564.99 2006.285.07:50:35.11#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.07:50:35.11#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.07:50:35.11#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:35.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:50:35.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:50:35.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:50:35.11#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:50:35.11#ibcon#first serial, iclass 13, count 0 2006.285.07:50:35.11#ibcon#enter sib2, iclass 13, count 0 2006.285.07:50:35.11#ibcon#flushed, iclass 13, count 0 2006.285.07:50:35.11#ibcon#about to write, iclass 13, count 0 2006.285.07:50:35.11#ibcon#wrote, iclass 13, count 0 2006.285.07:50:35.11#ibcon#about to read 3, iclass 13, count 0 2006.285.07:50:35.13#ibcon#read 3, iclass 13, count 0 2006.285.07:50:35.13#ibcon#about to read 4, iclass 13, count 0 2006.285.07:50:35.13#ibcon#read 4, iclass 13, count 0 2006.285.07:50:35.13#ibcon#about to read 5, iclass 13, count 0 2006.285.07:50:35.13#ibcon#read 5, iclass 13, count 0 2006.285.07:50:35.13#ibcon#about to read 6, iclass 13, count 0 2006.285.07:50:35.13#ibcon#read 6, iclass 13, count 0 2006.285.07:50:35.13#ibcon#end of sib2, iclass 13, count 0 2006.285.07:50:35.13#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:50:35.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:50:35.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:50:35.13#ibcon#*before write, iclass 13, count 0 2006.285.07:50:35.13#ibcon#enter sib2, iclass 13, count 0 2006.285.07:50:35.13#ibcon#flushed, iclass 13, count 0 2006.285.07:50:35.13#ibcon#about to write, iclass 13, count 0 2006.285.07:50:35.13#ibcon#wrote, iclass 13, count 0 2006.285.07:50:35.13#ibcon#about to read 3, iclass 13, count 0 2006.285.07:50:35.17#ibcon#read 3, iclass 13, count 0 2006.285.07:50:35.17#ibcon#about to read 4, iclass 13, count 0 2006.285.07:50:35.17#ibcon#read 4, iclass 13, count 0 2006.285.07:50:35.17#ibcon#about to read 5, iclass 13, count 0 2006.285.07:50:35.17#ibcon#read 5, iclass 13, count 0 2006.285.07:50:35.17#ibcon#about to read 6, iclass 13, count 0 2006.285.07:50:35.17#ibcon#read 6, iclass 13, count 0 2006.285.07:50:35.17#ibcon#end of sib2, iclass 13, count 0 2006.285.07:50:35.17#ibcon#*after write, iclass 13, count 0 2006.285.07:50:35.17#ibcon#*before return 0, iclass 13, count 0 2006.285.07:50:35.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:50:35.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:50:35.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:50:35.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:50:35.17$vck44/va=3,7 2006.285.07:50:35.17#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.07:50:35.17#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.07:50:35.17#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:35.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:50:35.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:50:35.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:50:35.23#ibcon#enter wrdev, iclass 15, count 2 2006.285.07:50:35.23#ibcon#first serial, iclass 15, count 2 2006.285.07:50:35.23#ibcon#enter sib2, iclass 15, count 2 2006.285.07:50:35.23#ibcon#flushed, iclass 15, count 2 2006.285.07:50:35.23#ibcon#about to write, iclass 15, count 2 2006.285.07:50:35.23#ibcon#wrote, iclass 15, count 2 2006.285.07:50:35.23#ibcon#about to read 3, iclass 15, count 2 2006.285.07:50:35.25#ibcon#read 3, iclass 15, count 2 2006.285.07:50:35.25#ibcon#about to read 4, iclass 15, count 2 2006.285.07:50:35.25#ibcon#read 4, iclass 15, count 2 2006.285.07:50:35.25#ibcon#about to read 5, iclass 15, count 2 2006.285.07:50:35.25#ibcon#read 5, iclass 15, count 2 2006.285.07:50:35.25#ibcon#about to read 6, iclass 15, count 2 2006.285.07:50:35.25#ibcon#read 6, iclass 15, count 2 2006.285.07:50:35.25#ibcon#end of sib2, iclass 15, count 2 2006.285.07:50:35.25#ibcon#*mode == 0, iclass 15, count 2 2006.285.07:50:35.25#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.07:50:35.25#ibcon#[25=AT03-07\r\n] 2006.285.07:50:35.25#ibcon#*before write, iclass 15, count 2 2006.285.07:50:35.25#ibcon#enter sib2, iclass 15, count 2 2006.285.07:50:35.25#ibcon#flushed, iclass 15, count 2 2006.285.07:50:35.25#ibcon#about to write, iclass 15, count 2 2006.285.07:50:35.25#ibcon#wrote, iclass 15, count 2 2006.285.07:50:35.25#ibcon#about to read 3, iclass 15, count 2 2006.285.07:50:35.28#ibcon#read 3, iclass 15, count 2 2006.285.07:50:35.28#ibcon#about to read 4, iclass 15, count 2 2006.285.07:50:35.28#ibcon#read 4, iclass 15, count 2 2006.285.07:50:35.28#ibcon#about to read 5, iclass 15, count 2 2006.285.07:50:35.28#ibcon#read 5, iclass 15, count 2 2006.285.07:50:35.28#ibcon#about to read 6, iclass 15, count 2 2006.285.07:50:35.28#ibcon#read 6, iclass 15, count 2 2006.285.07:50:35.28#ibcon#end of sib2, iclass 15, count 2 2006.285.07:50:35.28#ibcon#*after write, iclass 15, count 2 2006.285.07:50:35.28#ibcon#*before return 0, iclass 15, count 2 2006.285.07:50:35.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:50:35.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:50:35.28#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.07:50:35.28#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:35.28#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:50:35.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:50:35.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:50:35.40#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:50:35.40#ibcon#first serial, iclass 15, count 0 2006.285.07:50:35.40#ibcon#enter sib2, iclass 15, count 0 2006.285.07:50:35.40#ibcon#flushed, iclass 15, count 0 2006.285.07:50:35.40#ibcon#about to write, iclass 15, count 0 2006.285.07:50:35.40#ibcon#wrote, iclass 15, count 0 2006.285.07:50:35.40#ibcon#about to read 3, iclass 15, count 0 2006.285.07:50:35.42#ibcon#read 3, iclass 15, count 0 2006.285.07:50:35.42#ibcon#about to read 4, iclass 15, count 0 2006.285.07:50:35.42#ibcon#read 4, iclass 15, count 0 2006.285.07:50:35.42#ibcon#about to read 5, iclass 15, count 0 2006.285.07:50:35.42#ibcon#read 5, iclass 15, count 0 2006.285.07:50:35.42#ibcon#about to read 6, iclass 15, count 0 2006.285.07:50:35.42#ibcon#read 6, iclass 15, count 0 2006.285.07:50:35.42#ibcon#end of sib2, iclass 15, count 0 2006.285.07:50:35.42#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:50:35.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:50:35.42#ibcon#[25=USB\r\n] 2006.285.07:50:35.42#ibcon#*before write, iclass 15, count 0 2006.285.07:50:35.42#ibcon#enter sib2, iclass 15, count 0 2006.285.07:50:35.42#ibcon#flushed, iclass 15, count 0 2006.285.07:50:35.42#ibcon#about to write, iclass 15, count 0 2006.285.07:50:35.42#ibcon#wrote, iclass 15, count 0 2006.285.07:50:35.42#ibcon#about to read 3, iclass 15, count 0 2006.285.07:50:35.45#ibcon#read 3, iclass 15, count 0 2006.285.07:50:35.45#ibcon#about to read 4, iclass 15, count 0 2006.285.07:50:35.45#ibcon#read 4, iclass 15, count 0 2006.285.07:50:35.45#ibcon#about to read 5, iclass 15, count 0 2006.285.07:50:35.45#ibcon#read 5, iclass 15, count 0 2006.285.07:50:35.45#ibcon#about to read 6, iclass 15, count 0 2006.285.07:50:35.45#ibcon#read 6, iclass 15, count 0 2006.285.07:50:35.45#ibcon#end of sib2, iclass 15, count 0 2006.285.07:50:35.45#ibcon#*after write, iclass 15, count 0 2006.285.07:50:35.45#ibcon#*before return 0, iclass 15, count 0 2006.285.07:50:35.45#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:50:35.45#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:50:35.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:50:35.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:50:35.45$vck44/valo=4,624.99 2006.285.07:50:35.45#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.07:50:35.45#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.07:50:35.45#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:35.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:50:35.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:50:35.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:50:35.45#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:50:35.45#ibcon#first serial, iclass 17, count 0 2006.285.07:50:35.45#ibcon#enter sib2, iclass 17, count 0 2006.285.07:50:35.45#ibcon#flushed, iclass 17, count 0 2006.285.07:50:35.45#ibcon#about to write, iclass 17, count 0 2006.285.07:50:35.45#ibcon#wrote, iclass 17, count 0 2006.285.07:50:35.45#ibcon#about to read 3, iclass 17, count 0 2006.285.07:50:35.47#ibcon#read 3, iclass 17, count 0 2006.285.07:50:35.47#ibcon#about to read 4, iclass 17, count 0 2006.285.07:50:35.47#ibcon#read 4, iclass 17, count 0 2006.285.07:50:35.47#ibcon#about to read 5, iclass 17, count 0 2006.285.07:50:35.47#ibcon#read 5, iclass 17, count 0 2006.285.07:50:35.47#ibcon#about to read 6, iclass 17, count 0 2006.285.07:50:35.47#ibcon#read 6, iclass 17, count 0 2006.285.07:50:35.47#ibcon#end of sib2, iclass 17, count 0 2006.285.07:50:35.47#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:50:35.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:50:35.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:50:35.47#ibcon#*before write, iclass 17, count 0 2006.285.07:50:35.47#ibcon#enter sib2, iclass 17, count 0 2006.285.07:50:35.47#ibcon#flushed, iclass 17, count 0 2006.285.07:50:35.47#ibcon#about to write, iclass 17, count 0 2006.285.07:50:35.47#ibcon#wrote, iclass 17, count 0 2006.285.07:50:35.47#ibcon#about to read 3, iclass 17, count 0 2006.285.07:50:35.51#ibcon#read 3, iclass 17, count 0 2006.285.07:50:35.51#ibcon#about to read 4, iclass 17, count 0 2006.285.07:50:35.51#ibcon#read 4, iclass 17, count 0 2006.285.07:50:35.51#ibcon#about to read 5, iclass 17, count 0 2006.285.07:50:35.51#ibcon#read 5, iclass 17, count 0 2006.285.07:50:35.51#ibcon#about to read 6, iclass 17, count 0 2006.285.07:50:35.51#ibcon#read 6, iclass 17, count 0 2006.285.07:50:35.51#ibcon#end of sib2, iclass 17, count 0 2006.285.07:50:35.51#ibcon#*after write, iclass 17, count 0 2006.285.07:50:35.51#ibcon#*before return 0, iclass 17, count 0 2006.285.07:50:35.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:50:35.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:50:35.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:50:35.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:50:35.51$vck44/va=4,6 2006.285.07:50:35.51#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.07:50:35.51#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.07:50:35.51#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:35.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:50:35.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:50:35.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:50:35.57#ibcon#enter wrdev, iclass 19, count 2 2006.285.07:50:35.57#ibcon#first serial, iclass 19, count 2 2006.285.07:50:35.57#ibcon#enter sib2, iclass 19, count 2 2006.285.07:50:35.57#ibcon#flushed, iclass 19, count 2 2006.285.07:50:35.57#ibcon#about to write, iclass 19, count 2 2006.285.07:50:35.57#ibcon#wrote, iclass 19, count 2 2006.285.07:50:35.57#ibcon#about to read 3, iclass 19, count 2 2006.285.07:50:35.59#ibcon#read 3, iclass 19, count 2 2006.285.07:50:35.59#ibcon#about to read 4, iclass 19, count 2 2006.285.07:50:35.59#ibcon#read 4, iclass 19, count 2 2006.285.07:50:35.59#ibcon#about to read 5, iclass 19, count 2 2006.285.07:50:35.59#ibcon#read 5, iclass 19, count 2 2006.285.07:50:35.59#ibcon#about to read 6, iclass 19, count 2 2006.285.07:50:35.59#ibcon#read 6, iclass 19, count 2 2006.285.07:50:35.59#ibcon#end of sib2, iclass 19, count 2 2006.285.07:50:35.59#ibcon#*mode == 0, iclass 19, count 2 2006.285.07:50:35.59#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.07:50:35.59#ibcon#[25=AT04-06\r\n] 2006.285.07:50:35.59#ibcon#*before write, iclass 19, count 2 2006.285.07:50:35.59#ibcon#enter sib2, iclass 19, count 2 2006.285.07:50:35.59#ibcon#flushed, iclass 19, count 2 2006.285.07:50:35.59#ibcon#about to write, iclass 19, count 2 2006.285.07:50:35.59#ibcon#wrote, iclass 19, count 2 2006.285.07:50:35.59#ibcon#about to read 3, iclass 19, count 2 2006.285.07:50:35.62#ibcon#read 3, iclass 19, count 2 2006.285.07:50:35.62#ibcon#about to read 4, iclass 19, count 2 2006.285.07:50:35.62#ibcon#read 4, iclass 19, count 2 2006.285.07:50:35.62#ibcon#about to read 5, iclass 19, count 2 2006.285.07:50:35.62#ibcon#read 5, iclass 19, count 2 2006.285.07:50:35.62#ibcon#about to read 6, iclass 19, count 2 2006.285.07:50:35.62#ibcon#read 6, iclass 19, count 2 2006.285.07:50:35.62#ibcon#end of sib2, iclass 19, count 2 2006.285.07:50:35.62#ibcon#*after write, iclass 19, count 2 2006.285.07:50:35.62#ibcon#*before return 0, iclass 19, count 2 2006.285.07:50:35.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:50:35.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:50:35.62#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.07:50:35.62#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:35.62#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:50:35.74#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:50:35.74#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:50:35.74#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:50:35.74#ibcon#first serial, iclass 19, count 0 2006.285.07:50:35.74#ibcon#enter sib2, iclass 19, count 0 2006.285.07:50:35.74#ibcon#flushed, iclass 19, count 0 2006.285.07:50:35.74#ibcon#about to write, iclass 19, count 0 2006.285.07:50:35.74#ibcon#wrote, iclass 19, count 0 2006.285.07:50:35.74#ibcon#about to read 3, iclass 19, count 0 2006.285.07:50:35.76#ibcon#read 3, iclass 19, count 0 2006.285.07:50:35.76#ibcon#about to read 4, iclass 19, count 0 2006.285.07:50:35.76#ibcon#read 4, iclass 19, count 0 2006.285.07:50:35.76#ibcon#about to read 5, iclass 19, count 0 2006.285.07:50:35.76#ibcon#read 5, iclass 19, count 0 2006.285.07:50:35.76#ibcon#about to read 6, iclass 19, count 0 2006.285.07:50:35.76#ibcon#read 6, iclass 19, count 0 2006.285.07:50:35.76#ibcon#end of sib2, iclass 19, count 0 2006.285.07:50:35.76#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:50:35.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:50:35.76#ibcon#[25=USB\r\n] 2006.285.07:50:35.76#ibcon#*before write, iclass 19, count 0 2006.285.07:50:35.76#ibcon#enter sib2, iclass 19, count 0 2006.285.07:50:35.76#ibcon#flushed, iclass 19, count 0 2006.285.07:50:35.76#ibcon#about to write, iclass 19, count 0 2006.285.07:50:35.76#ibcon#wrote, iclass 19, count 0 2006.285.07:50:35.76#ibcon#about to read 3, iclass 19, count 0 2006.285.07:50:35.79#ibcon#read 3, iclass 19, count 0 2006.285.07:50:35.79#ibcon#about to read 4, iclass 19, count 0 2006.285.07:50:35.79#ibcon#read 4, iclass 19, count 0 2006.285.07:50:35.79#ibcon#about to read 5, iclass 19, count 0 2006.285.07:50:35.79#ibcon#read 5, iclass 19, count 0 2006.285.07:50:35.79#ibcon#about to read 6, iclass 19, count 0 2006.285.07:50:35.79#ibcon#read 6, iclass 19, count 0 2006.285.07:50:35.79#ibcon#end of sib2, iclass 19, count 0 2006.285.07:50:35.79#ibcon#*after write, iclass 19, count 0 2006.285.07:50:35.79#ibcon#*before return 0, iclass 19, count 0 2006.285.07:50:35.79#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:50:35.79#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:50:35.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:50:35.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:50:35.79$vck44/valo=5,734.99 2006.285.07:50:35.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.07:50:35.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.07:50:35.79#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:35.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:50:35.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:50:35.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:50:35.79#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:50:35.79#ibcon#first serial, iclass 21, count 0 2006.285.07:50:35.79#ibcon#enter sib2, iclass 21, count 0 2006.285.07:50:35.79#ibcon#flushed, iclass 21, count 0 2006.285.07:50:35.79#ibcon#about to write, iclass 21, count 0 2006.285.07:50:35.79#ibcon#wrote, iclass 21, count 0 2006.285.07:50:35.79#ibcon#about to read 3, iclass 21, count 0 2006.285.07:50:35.81#ibcon#read 3, iclass 21, count 0 2006.285.07:50:35.81#ibcon#about to read 4, iclass 21, count 0 2006.285.07:50:35.81#ibcon#read 4, iclass 21, count 0 2006.285.07:50:35.81#ibcon#about to read 5, iclass 21, count 0 2006.285.07:50:35.81#ibcon#read 5, iclass 21, count 0 2006.285.07:50:35.81#ibcon#about to read 6, iclass 21, count 0 2006.285.07:50:35.81#ibcon#read 6, iclass 21, count 0 2006.285.07:50:35.81#ibcon#end of sib2, iclass 21, count 0 2006.285.07:50:35.81#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:50:35.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:50:35.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:50:35.81#ibcon#*before write, iclass 21, count 0 2006.285.07:50:35.81#ibcon#enter sib2, iclass 21, count 0 2006.285.07:50:35.81#ibcon#flushed, iclass 21, count 0 2006.285.07:50:35.81#ibcon#about to write, iclass 21, count 0 2006.285.07:50:35.81#ibcon#wrote, iclass 21, count 0 2006.285.07:50:35.81#ibcon#about to read 3, iclass 21, count 0 2006.285.07:50:35.85#ibcon#read 3, iclass 21, count 0 2006.285.07:50:35.85#ibcon#about to read 4, iclass 21, count 0 2006.285.07:50:35.85#ibcon#read 4, iclass 21, count 0 2006.285.07:50:35.85#ibcon#about to read 5, iclass 21, count 0 2006.285.07:50:35.85#ibcon#read 5, iclass 21, count 0 2006.285.07:50:35.85#ibcon#about to read 6, iclass 21, count 0 2006.285.07:50:35.85#ibcon#read 6, iclass 21, count 0 2006.285.07:50:35.85#ibcon#end of sib2, iclass 21, count 0 2006.285.07:50:35.85#ibcon#*after write, iclass 21, count 0 2006.285.07:50:35.85#ibcon#*before return 0, iclass 21, count 0 2006.285.07:50:35.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:50:35.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:50:35.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:50:35.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:50:35.85$vck44/va=5,3 2006.285.07:50:35.85#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.07:50:35.85#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.07:50:35.85#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:35.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:50:35.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:50:35.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:50:35.91#ibcon#enter wrdev, iclass 23, count 2 2006.285.07:50:35.91#ibcon#first serial, iclass 23, count 2 2006.285.07:50:35.91#ibcon#enter sib2, iclass 23, count 2 2006.285.07:50:35.91#ibcon#flushed, iclass 23, count 2 2006.285.07:50:35.91#ibcon#about to write, iclass 23, count 2 2006.285.07:50:35.91#ibcon#wrote, iclass 23, count 2 2006.285.07:50:35.91#ibcon#about to read 3, iclass 23, count 2 2006.285.07:50:35.93#ibcon#read 3, iclass 23, count 2 2006.285.07:50:35.93#ibcon#about to read 4, iclass 23, count 2 2006.285.07:50:35.93#ibcon#read 4, iclass 23, count 2 2006.285.07:50:35.93#ibcon#about to read 5, iclass 23, count 2 2006.285.07:50:35.93#ibcon#read 5, iclass 23, count 2 2006.285.07:50:35.93#ibcon#about to read 6, iclass 23, count 2 2006.285.07:50:35.93#ibcon#read 6, iclass 23, count 2 2006.285.07:50:35.93#ibcon#end of sib2, iclass 23, count 2 2006.285.07:50:35.93#ibcon#*mode == 0, iclass 23, count 2 2006.285.07:50:35.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.07:50:35.93#ibcon#[25=AT05-03\r\n] 2006.285.07:50:35.93#ibcon#*before write, iclass 23, count 2 2006.285.07:50:35.93#ibcon#enter sib2, iclass 23, count 2 2006.285.07:50:35.93#ibcon#flushed, iclass 23, count 2 2006.285.07:50:35.93#ibcon#about to write, iclass 23, count 2 2006.285.07:50:35.93#ibcon#wrote, iclass 23, count 2 2006.285.07:50:35.93#ibcon#about to read 3, iclass 23, count 2 2006.285.07:50:35.96#ibcon#read 3, iclass 23, count 2 2006.285.07:50:35.96#ibcon#about to read 4, iclass 23, count 2 2006.285.07:50:35.96#ibcon#read 4, iclass 23, count 2 2006.285.07:50:35.96#ibcon#about to read 5, iclass 23, count 2 2006.285.07:50:35.96#ibcon#read 5, iclass 23, count 2 2006.285.07:50:35.96#ibcon#about to read 6, iclass 23, count 2 2006.285.07:50:35.96#ibcon#read 6, iclass 23, count 2 2006.285.07:50:35.96#ibcon#end of sib2, iclass 23, count 2 2006.285.07:50:35.96#ibcon#*after write, iclass 23, count 2 2006.285.07:50:35.96#ibcon#*before return 0, iclass 23, count 2 2006.285.07:50:35.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:50:35.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:50:35.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.07:50:35.96#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:35.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:50:36.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:50:36.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:50:36.08#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:50:36.08#ibcon#first serial, iclass 23, count 0 2006.285.07:50:36.08#ibcon#enter sib2, iclass 23, count 0 2006.285.07:50:36.08#ibcon#flushed, iclass 23, count 0 2006.285.07:50:36.08#ibcon#about to write, iclass 23, count 0 2006.285.07:50:36.08#ibcon#wrote, iclass 23, count 0 2006.285.07:50:36.08#ibcon#about to read 3, iclass 23, count 0 2006.285.07:50:36.10#ibcon#read 3, iclass 23, count 0 2006.285.07:50:36.10#ibcon#about to read 4, iclass 23, count 0 2006.285.07:50:36.10#ibcon#read 4, iclass 23, count 0 2006.285.07:50:36.10#ibcon#about to read 5, iclass 23, count 0 2006.285.07:50:36.10#ibcon#read 5, iclass 23, count 0 2006.285.07:50:36.10#ibcon#about to read 6, iclass 23, count 0 2006.285.07:50:36.10#ibcon#read 6, iclass 23, count 0 2006.285.07:50:36.10#ibcon#end of sib2, iclass 23, count 0 2006.285.07:50:36.10#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:50:36.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:50:36.10#ibcon#[25=USB\r\n] 2006.285.07:50:36.10#ibcon#*before write, iclass 23, count 0 2006.285.07:50:36.10#ibcon#enter sib2, iclass 23, count 0 2006.285.07:50:36.10#ibcon#flushed, iclass 23, count 0 2006.285.07:50:36.10#ibcon#about to write, iclass 23, count 0 2006.285.07:50:36.10#ibcon#wrote, iclass 23, count 0 2006.285.07:50:36.10#ibcon#about to read 3, iclass 23, count 0 2006.285.07:50:36.13#ibcon#read 3, iclass 23, count 0 2006.285.07:50:36.13#ibcon#about to read 4, iclass 23, count 0 2006.285.07:50:36.13#ibcon#read 4, iclass 23, count 0 2006.285.07:50:36.13#ibcon#about to read 5, iclass 23, count 0 2006.285.07:50:36.13#ibcon#read 5, iclass 23, count 0 2006.285.07:50:36.13#ibcon#about to read 6, iclass 23, count 0 2006.285.07:50:36.13#ibcon#read 6, iclass 23, count 0 2006.285.07:50:36.13#ibcon#end of sib2, iclass 23, count 0 2006.285.07:50:36.13#ibcon#*after write, iclass 23, count 0 2006.285.07:50:36.13#ibcon#*before return 0, iclass 23, count 0 2006.285.07:50:36.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:50:36.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:50:36.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:50:36.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:50:36.13$vck44/valo=6,814.99 2006.285.07:50:36.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.07:50:36.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.07:50:36.13#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:36.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:50:36.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:50:36.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:50:36.13#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:50:36.13#ibcon#first serial, iclass 25, count 0 2006.285.07:50:36.13#ibcon#enter sib2, iclass 25, count 0 2006.285.07:50:36.13#ibcon#flushed, iclass 25, count 0 2006.285.07:50:36.13#ibcon#about to write, iclass 25, count 0 2006.285.07:50:36.13#ibcon#wrote, iclass 25, count 0 2006.285.07:50:36.13#ibcon#about to read 3, iclass 25, count 0 2006.285.07:50:36.15#ibcon#read 3, iclass 25, count 0 2006.285.07:50:36.15#ibcon#about to read 4, iclass 25, count 0 2006.285.07:50:36.15#ibcon#read 4, iclass 25, count 0 2006.285.07:50:36.15#ibcon#about to read 5, iclass 25, count 0 2006.285.07:50:36.15#ibcon#read 5, iclass 25, count 0 2006.285.07:50:36.15#ibcon#about to read 6, iclass 25, count 0 2006.285.07:50:36.15#ibcon#read 6, iclass 25, count 0 2006.285.07:50:36.15#ibcon#end of sib2, iclass 25, count 0 2006.285.07:50:36.15#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:50:36.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:50:36.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:50:36.15#ibcon#*before write, iclass 25, count 0 2006.285.07:50:36.15#ibcon#enter sib2, iclass 25, count 0 2006.285.07:50:36.15#ibcon#flushed, iclass 25, count 0 2006.285.07:50:36.15#ibcon#about to write, iclass 25, count 0 2006.285.07:50:36.15#ibcon#wrote, iclass 25, count 0 2006.285.07:50:36.15#ibcon#about to read 3, iclass 25, count 0 2006.285.07:50:36.19#ibcon#read 3, iclass 25, count 0 2006.285.07:50:36.19#ibcon#about to read 4, iclass 25, count 0 2006.285.07:50:36.19#ibcon#read 4, iclass 25, count 0 2006.285.07:50:36.19#ibcon#about to read 5, iclass 25, count 0 2006.285.07:50:36.19#ibcon#read 5, iclass 25, count 0 2006.285.07:50:36.19#ibcon#about to read 6, iclass 25, count 0 2006.285.07:50:36.19#ibcon#read 6, iclass 25, count 0 2006.285.07:50:36.19#ibcon#end of sib2, iclass 25, count 0 2006.285.07:50:36.19#ibcon#*after write, iclass 25, count 0 2006.285.07:50:36.19#ibcon#*before return 0, iclass 25, count 0 2006.285.07:50:36.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:50:36.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:50:36.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:50:36.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:50:36.19$vck44/va=6,4 2006.285.07:50:36.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.07:50:36.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.07:50:36.19#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:36.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:50:36.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:50:36.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:50:36.25#ibcon#enter wrdev, iclass 27, count 2 2006.285.07:50:36.25#ibcon#first serial, iclass 27, count 2 2006.285.07:50:36.25#ibcon#enter sib2, iclass 27, count 2 2006.285.07:50:36.25#ibcon#flushed, iclass 27, count 2 2006.285.07:50:36.25#ibcon#about to write, iclass 27, count 2 2006.285.07:50:36.25#ibcon#wrote, iclass 27, count 2 2006.285.07:50:36.25#ibcon#about to read 3, iclass 27, count 2 2006.285.07:50:36.27#ibcon#read 3, iclass 27, count 2 2006.285.07:50:36.27#ibcon#about to read 4, iclass 27, count 2 2006.285.07:50:36.27#ibcon#read 4, iclass 27, count 2 2006.285.07:50:36.27#ibcon#about to read 5, iclass 27, count 2 2006.285.07:50:36.27#ibcon#read 5, iclass 27, count 2 2006.285.07:50:36.27#ibcon#about to read 6, iclass 27, count 2 2006.285.07:50:36.27#ibcon#read 6, iclass 27, count 2 2006.285.07:50:36.27#ibcon#end of sib2, iclass 27, count 2 2006.285.07:50:36.27#ibcon#*mode == 0, iclass 27, count 2 2006.285.07:50:36.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.07:50:36.27#ibcon#[25=AT06-04\r\n] 2006.285.07:50:36.27#ibcon#*before write, iclass 27, count 2 2006.285.07:50:36.27#ibcon#enter sib2, iclass 27, count 2 2006.285.07:50:36.27#ibcon#flushed, iclass 27, count 2 2006.285.07:50:36.27#ibcon#about to write, iclass 27, count 2 2006.285.07:50:36.27#ibcon#wrote, iclass 27, count 2 2006.285.07:50:36.27#ibcon#about to read 3, iclass 27, count 2 2006.285.07:50:36.30#ibcon#read 3, iclass 27, count 2 2006.285.07:50:36.30#ibcon#about to read 4, iclass 27, count 2 2006.285.07:50:36.30#ibcon#read 4, iclass 27, count 2 2006.285.07:50:36.30#ibcon#about to read 5, iclass 27, count 2 2006.285.07:50:36.30#ibcon#read 5, iclass 27, count 2 2006.285.07:50:36.30#ibcon#about to read 6, iclass 27, count 2 2006.285.07:50:36.30#ibcon#read 6, iclass 27, count 2 2006.285.07:50:36.30#ibcon#end of sib2, iclass 27, count 2 2006.285.07:50:36.30#ibcon#*after write, iclass 27, count 2 2006.285.07:50:36.30#ibcon#*before return 0, iclass 27, count 2 2006.285.07:50:36.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:50:36.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:50:36.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.07:50:36.30#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:36.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:50:36.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:50:36.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:50:36.42#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:50:36.42#ibcon#first serial, iclass 27, count 0 2006.285.07:50:36.42#ibcon#enter sib2, iclass 27, count 0 2006.285.07:50:36.42#ibcon#flushed, iclass 27, count 0 2006.285.07:50:36.42#ibcon#about to write, iclass 27, count 0 2006.285.07:50:36.42#ibcon#wrote, iclass 27, count 0 2006.285.07:50:36.42#ibcon#about to read 3, iclass 27, count 0 2006.285.07:50:36.44#ibcon#read 3, iclass 27, count 0 2006.285.07:50:36.44#ibcon#about to read 4, iclass 27, count 0 2006.285.07:50:36.44#ibcon#read 4, iclass 27, count 0 2006.285.07:50:36.44#ibcon#about to read 5, iclass 27, count 0 2006.285.07:50:36.44#ibcon#read 5, iclass 27, count 0 2006.285.07:50:36.44#ibcon#about to read 6, iclass 27, count 0 2006.285.07:50:36.44#ibcon#read 6, iclass 27, count 0 2006.285.07:50:36.44#ibcon#end of sib2, iclass 27, count 0 2006.285.07:50:36.44#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:50:36.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:50:36.44#ibcon#[25=USB\r\n] 2006.285.07:50:36.44#ibcon#*before write, iclass 27, count 0 2006.285.07:50:36.44#ibcon#enter sib2, iclass 27, count 0 2006.285.07:50:36.44#ibcon#flushed, iclass 27, count 0 2006.285.07:50:36.44#ibcon#about to write, iclass 27, count 0 2006.285.07:50:36.44#ibcon#wrote, iclass 27, count 0 2006.285.07:50:36.44#ibcon#about to read 3, iclass 27, count 0 2006.285.07:50:36.47#ibcon#read 3, iclass 27, count 0 2006.285.07:50:36.47#ibcon#about to read 4, iclass 27, count 0 2006.285.07:50:36.47#ibcon#read 4, iclass 27, count 0 2006.285.07:50:36.47#ibcon#about to read 5, iclass 27, count 0 2006.285.07:50:36.47#ibcon#read 5, iclass 27, count 0 2006.285.07:50:36.47#ibcon#about to read 6, iclass 27, count 0 2006.285.07:50:36.47#ibcon#read 6, iclass 27, count 0 2006.285.07:50:36.47#ibcon#end of sib2, iclass 27, count 0 2006.285.07:50:36.47#ibcon#*after write, iclass 27, count 0 2006.285.07:50:36.47#ibcon#*before return 0, iclass 27, count 0 2006.285.07:50:36.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:50:36.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:50:36.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:50:36.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:50:36.47$vck44/valo=7,864.99 2006.285.07:50:36.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.07:50:36.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.07:50:36.47#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:36.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:50:36.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:50:36.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:50:36.47#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:50:36.47#ibcon#first serial, iclass 29, count 0 2006.285.07:50:36.47#ibcon#enter sib2, iclass 29, count 0 2006.285.07:50:36.47#ibcon#flushed, iclass 29, count 0 2006.285.07:50:36.47#ibcon#about to write, iclass 29, count 0 2006.285.07:50:36.47#ibcon#wrote, iclass 29, count 0 2006.285.07:50:36.47#ibcon#about to read 3, iclass 29, count 0 2006.285.07:50:36.49#ibcon#read 3, iclass 29, count 0 2006.285.07:50:36.49#ibcon#about to read 4, iclass 29, count 0 2006.285.07:50:36.49#ibcon#read 4, iclass 29, count 0 2006.285.07:50:36.49#ibcon#about to read 5, iclass 29, count 0 2006.285.07:50:36.49#ibcon#read 5, iclass 29, count 0 2006.285.07:50:36.49#ibcon#about to read 6, iclass 29, count 0 2006.285.07:50:36.49#ibcon#read 6, iclass 29, count 0 2006.285.07:50:36.49#ibcon#end of sib2, iclass 29, count 0 2006.285.07:50:36.49#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:50:36.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:50:36.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:50:36.49#ibcon#*before write, iclass 29, count 0 2006.285.07:50:36.49#ibcon#enter sib2, iclass 29, count 0 2006.285.07:50:36.49#ibcon#flushed, iclass 29, count 0 2006.285.07:50:36.49#ibcon#about to write, iclass 29, count 0 2006.285.07:50:36.49#ibcon#wrote, iclass 29, count 0 2006.285.07:50:36.49#ibcon#about to read 3, iclass 29, count 0 2006.285.07:50:36.53#ibcon#read 3, iclass 29, count 0 2006.285.07:50:36.53#ibcon#about to read 4, iclass 29, count 0 2006.285.07:50:36.53#ibcon#read 4, iclass 29, count 0 2006.285.07:50:36.53#ibcon#about to read 5, iclass 29, count 0 2006.285.07:50:36.53#ibcon#read 5, iclass 29, count 0 2006.285.07:50:36.53#ibcon#about to read 6, iclass 29, count 0 2006.285.07:50:36.53#ibcon#read 6, iclass 29, count 0 2006.285.07:50:36.53#ibcon#end of sib2, iclass 29, count 0 2006.285.07:50:36.53#ibcon#*after write, iclass 29, count 0 2006.285.07:50:36.53#ibcon#*before return 0, iclass 29, count 0 2006.285.07:50:36.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:50:36.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:50:36.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:50:36.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:50:36.53$vck44/va=7,4 2006.285.07:50:36.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.07:50:36.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.07:50:36.53#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:36.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:50:36.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:50:36.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:50:36.59#ibcon#enter wrdev, iclass 31, count 2 2006.285.07:50:36.59#ibcon#first serial, iclass 31, count 2 2006.285.07:50:36.59#ibcon#enter sib2, iclass 31, count 2 2006.285.07:50:36.59#ibcon#flushed, iclass 31, count 2 2006.285.07:50:36.59#ibcon#about to write, iclass 31, count 2 2006.285.07:50:36.59#ibcon#wrote, iclass 31, count 2 2006.285.07:50:36.59#ibcon#about to read 3, iclass 31, count 2 2006.285.07:50:36.61#ibcon#read 3, iclass 31, count 2 2006.285.07:50:36.61#ibcon#about to read 4, iclass 31, count 2 2006.285.07:50:36.61#ibcon#read 4, iclass 31, count 2 2006.285.07:50:36.61#ibcon#about to read 5, iclass 31, count 2 2006.285.07:50:36.61#ibcon#read 5, iclass 31, count 2 2006.285.07:50:36.61#ibcon#about to read 6, iclass 31, count 2 2006.285.07:50:36.61#ibcon#read 6, iclass 31, count 2 2006.285.07:50:36.61#ibcon#end of sib2, iclass 31, count 2 2006.285.07:50:36.61#ibcon#*mode == 0, iclass 31, count 2 2006.285.07:50:36.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.07:50:36.61#ibcon#[25=AT07-04\r\n] 2006.285.07:50:36.61#ibcon#*before write, iclass 31, count 2 2006.285.07:50:36.61#ibcon#enter sib2, iclass 31, count 2 2006.285.07:50:36.61#ibcon#flushed, iclass 31, count 2 2006.285.07:50:36.61#ibcon#about to write, iclass 31, count 2 2006.285.07:50:36.61#ibcon#wrote, iclass 31, count 2 2006.285.07:50:36.61#ibcon#about to read 3, iclass 31, count 2 2006.285.07:50:36.64#ibcon#read 3, iclass 31, count 2 2006.285.07:50:36.64#ibcon#about to read 4, iclass 31, count 2 2006.285.07:50:36.64#ibcon#read 4, iclass 31, count 2 2006.285.07:50:36.64#ibcon#about to read 5, iclass 31, count 2 2006.285.07:50:36.64#ibcon#read 5, iclass 31, count 2 2006.285.07:50:36.64#ibcon#about to read 6, iclass 31, count 2 2006.285.07:50:36.64#ibcon#read 6, iclass 31, count 2 2006.285.07:50:36.64#ibcon#end of sib2, iclass 31, count 2 2006.285.07:50:36.64#ibcon#*after write, iclass 31, count 2 2006.285.07:50:36.64#ibcon#*before return 0, iclass 31, count 2 2006.285.07:50:36.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:50:36.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:50:36.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.07:50:36.64#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:36.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:50:36.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:50:36.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:50:36.76#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:50:36.76#ibcon#first serial, iclass 31, count 0 2006.285.07:50:36.76#ibcon#enter sib2, iclass 31, count 0 2006.285.07:50:36.76#ibcon#flushed, iclass 31, count 0 2006.285.07:50:36.76#ibcon#about to write, iclass 31, count 0 2006.285.07:50:36.76#ibcon#wrote, iclass 31, count 0 2006.285.07:50:36.76#ibcon#about to read 3, iclass 31, count 0 2006.285.07:50:36.78#ibcon#read 3, iclass 31, count 0 2006.285.07:50:36.78#ibcon#about to read 4, iclass 31, count 0 2006.285.07:50:36.78#ibcon#read 4, iclass 31, count 0 2006.285.07:50:36.78#ibcon#about to read 5, iclass 31, count 0 2006.285.07:50:36.78#ibcon#read 5, iclass 31, count 0 2006.285.07:50:36.78#ibcon#about to read 6, iclass 31, count 0 2006.285.07:50:36.78#ibcon#read 6, iclass 31, count 0 2006.285.07:50:36.78#ibcon#end of sib2, iclass 31, count 0 2006.285.07:50:36.78#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:50:36.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:50:36.78#ibcon#[25=USB\r\n] 2006.285.07:50:36.78#ibcon#*before write, iclass 31, count 0 2006.285.07:50:36.78#ibcon#enter sib2, iclass 31, count 0 2006.285.07:50:36.78#ibcon#flushed, iclass 31, count 0 2006.285.07:50:36.78#ibcon#about to write, iclass 31, count 0 2006.285.07:50:36.78#ibcon#wrote, iclass 31, count 0 2006.285.07:50:36.78#ibcon#about to read 3, iclass 31, count 0 2006.285.07:50:36.81#ibcon#read 3, iclass 31, count 0 2006.285.07:50:36.81#ibcon#about to read 4, iclass 31, count 0 2006.285.07:50:36.81#ibcon#read 4, iclass 31, count 0 2006.285.07:50:36.81#ibcon#about to read 5, iclass 31, count 0 2006.285.07:50:36.81#ibcon#read 5, iclass 31, count 0 2006.285.07:50:36.81#ibcon#about to read 6, iclass 31, count 0 2006.285.07:50:36.81#ibcon#read 6, iclass 31, count 0 2006.285.07:50:36.81#ibcon#end of sib2, iclass 31, count 0 2006.285.07:50:36.81#ibcon#*after write, iclass 31, count 0 2006.285.07:50:36.81#ibcon#*before return 0, iclass 31, count 0 2006.285.07:50:36.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:50:36.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:50:36.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:50:36.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:50:36.81$vck44/valo=8,884.99 2006.285.07:50:36.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.07:50:36.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.07:50:36.81#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:36.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:50:36.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:50:36.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:50:36.81#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:50:36.81#ibcon#first serial, iclass 33, count 0 2006.285.07:50:36.81#ibcon#enter sib2, iclass 33, count 0 2006.285.07:50:36.81#ibcon#flushed, iclass 33, count 0 2006.285.07:50:36.81#ibcon#about to write, iclass 33, count 0 2006.285.07:50:36.81#ibcon#wrote, iclass 33, count 0 2006.285.07:50:36.81#ibcon#about to read 3, iclass 33, count 0 2006.285.07:50:36.83#ibcon#read 3, iclass 33, count 0 2006.285.07:50:36.83#ibcon#about to read 4, iclass 33, count 0 2006.285.07:50:36.83#ibcon#read 4, iclass 33, count 0 2006.285.07:50:36.83#ibcon#about to read 5, iclass 33, count 0 2006.285.07:50:36.83#ibcon#read 5, iclass 33, count 0 2006.285.07:50:36.83#ibcon#about to read 6, iclass 33, count 0 2006.285.07:50:36.83#ibcon#read 6, iclass 33, count 0 2006.285.07:50:36.83#ibcon#end of sib2, iclass 33, count 0 2006.285.07:50:36.83#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:50:36.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:50:36.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:50:36.83#ibcon#*before write, iclass 33, count 0 2006.285.07:50:36.83#ibcon#enter sib2, iclass 33, count 0 2006.285.07:50:36.83#ibcon#flushed, iclass 33, count 0 2006.285.07:50:36.83#ibcon#about to write, iclass 33, count 0 2006.285.07:50:36.83#ibcon#wrote, iclass 33, count 0 2006.285.07:50:36.83#ibcon#about to read 3, iclass 33, count 0 2006.285.07:50:36.87#ibcon#read 3, iclass 33, count 0 2006.285.07:50:36.87#ibcon#about to read 4, iclass 33, count 0 2006.285.07:50:36.87#ibcon#read 4, iclass 33, count 0 2006.285.07:50:36.87#ibcon#about to read 5, iclass 33, count 0 2006.285.07:50:36.87#ibcon#read 5, iclass 33, count 0 2006.285.07:50:36.87#ibcon#about to read 6, iclass 33, count 0 2006.285.07:50:36.87#ibcon#read 6, iclass 33, count 0 2006.285.07:50:36.87#ibcon#end of sib2, iclass 33, count 0 2006.285.07:50:36.87#ibcon#*after write, iclass 33, count 0 2006.285.07:50:36.87#ibcon#*before return 0, iclass 33, count 0 2006.285.07:50:36.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:50:36.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:50:36.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:50:36.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:50:36.87$vck44/va=8,3 2006.285.07:50:36.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.07:50:36.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.07:50:36.87#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:36.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:50:36.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:50:36.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:50:36.93#ibcon#enter wrdev, iclass 35, count 2 2006.285.07:50:36.93#ibcon#first serial, iclass 35, count 2 2006.285.07:50:36.93#ibcon#enter sib2, iclass 35, count 2 2006.285.07:50:36.93#ibcon#flushed, iclass 35, count 2 2006.285.07:50:36.93#ibcon#about to write, iclass 35, count 2 2006.285.07:50:36.93#ibcon#wrote, iclass 35, count 2 2006.285.07:50:36.93#ibcon#about to read 3, iclass 35, count 2 2006.285.07:50:36.95#ibcon#read 3, iclass 35, count 2 2006.285.07:50:36.95#ibcon#about to read 4, iclass 35, count 2 2006.285.07:50:36.95#ibcon#read 4, iclass 35, count 2 2006.285.07:50:36.95#ibcon#about to read 5, iclass 35, count 2 2006.285.07:50:36.95#ibcon#read 5, iclass 35, count 2 2006.285.07:50:36.95#ibcon#about to read 6, iclass 35, count 2 2006.285.07:50:36.95#ibcon#read 6, iclass 35, count 2 2006.285.07:50:36.95#ibcon#end of sib2, iclass 35, count 2 2006.285.07:50:36.95#ibcon#*mode == 0, iclass 35, count 2 2006.285.07:50:36.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.07:50:36.95#ibcon#[25=AT08-03\r\n] 2006.285.07:50:36.95#ibcon#*before write, iclass 35, count 2 2006.285.07:50:36.95#ibcon#enter sib2, iclass 35, count 2 2006.285.07:50:36.95#ibcon#flushed, iclass 35, count 2 2006.285.07:50:36.95#ibcon#about to write, iclass 35, count 2 2006.285.07:50:36.95#ibcon#wrote, iclass 35, count 2 2006.285.07:50:36.95#ibcon#about to read 3, iclass 35, count 2 2006.285.07:50:36.98#ibcon#read 3, iclass 35, count 2 2006.285.07:50:36.98#ibcon#about to read 4, iclass 35, count 2 2006.285.07:50:36.98#ibcon#read 4, iclass 35, count 2 2006.285.07:50:36.98#ibcon#about to read 5, iclass 35, count 2 2006.285.07:50:36.98#ibcon#read 5, iclass 35, count 2 2006.285.07:50:36.98#ibcon#about to read 6, iclass 35, count 2 2006.285.07:50:36.98#ibcon#read 6, iclass 35, count 2 2006.285.07:50:36.98#ibcon#end of sib2, iclass 35, count 2 2006.285.07:50:36.98#ibcon#*after write, iclass 35, count 2 2006.285.07:50:36.98#ibcon#*before return 0, iclass 35, count 2 2006.285.07:50:36.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:50:36.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.07:50:36.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.07:50:36.98#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:36.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:50:37.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:50:37.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:50:37.10#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:50:37.10#ibcon#first serial, iclass 35, count 0 2006.285.07:50:37.10#ibcon#enter sib2, iclass 35, count 0 2006.285.07:50:37.10#ibcon#flushed, iclass 35, count 0 2006.285.07:50:37.10#ibcon#about to write, iclass 35, count 0 2006.285.07:50:37.10#ibcon#wrote, iclass 35, count 0 2006.285.07:50:37.10#ibcon#about to read 3, iclass 35, count 0 2006.285.07:50:37.12#ibcon#read 3, iclass 35, count 0 2006.285.07:50:37.12#ibcon#about to read 4, iclass 35, count 0 2006.285.07:50:37.12#ibcon#read 4, iclass 35, count 0 2006.285.07:50:37.12#ibcon#about to read 5, iclass 35, count 0 2006.285.07:50:37.12#ibcon#read 5, iclass 35, count 0 2006.285.07:50:37.12#ibcon#about to read 6, iclass 35, count 0 2006.285.07:50:37.12#ibcon#read 6, iclass 35, count 0 2006.285.07:50:37.12#ibcon#end of sib2, iclass 35, count 0 2006.285.07:50:37.12#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:50:37.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:50:37.12#ibcon#[25=USB\r\n] 2006.285.07:50:37.12#ibcon#*before write, iclass 35, count 0 2006.285.07:50:37.12#ibcon#enter sib2, iclass 35, count 0 2006.285.07:50:37.12#ibcon#flushed, iclass 35, count 0 2006.285.07:50:37.12#ibcon#about to write, iclass 35, count 0 2006.285.07:50:37.12#ibcon#wrote, iclass 35, count 0 2006.285.07:50:37.12#ibcon#about to read 3, iclass 35, count 0 2006.285.07:50:37.15#ibcon#read 3, iclass 35, count 0 2006.285.07:50:37.15#ibcon#about to read 4, iclass 35, count 0 2006.285.07:50:37.15#ibcon#read 4, iclass 35, count 0 2006.285.07:50:37.15#ibcon#about to read 5, iclass 35, count 0 2006.285.07:50:37.15#ibcon#read 5, iclass 35, count 0 2006.285.07:50:37.15#ibcon#about to read 6, iclass 35, count 0 2006.285.07:50:37.15#ibcon#read 6, iclass 35, count 0 2006.285.07:50:37.15#ibcon#end of sib2, iclass 35, count 0 2006.285.07:50:37.15#ibcon#*after write, iclass 35, count 0 2006.285.07:50:37.15#ibcon#*before return 0, iclass 35, count 0 2006.285.07:50:37.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:50:37.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.07:50:37.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:50:37.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:50:37.15$vck44/vblo=1,629.99 2006.285.07:50:37.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.07:50:37.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.07:50:37.15#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:37.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:50:37.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:50:37.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:50:37.15#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:50:37.15#ibcon#first serial, iclass 37, count 0 2006.285.07:50:37.15#ibcon#enter sib2, iclass 37, count 0 2006.285.07:50:37.15#ibcon#flushed, iclass 37, count 0 2006.285.07:50:37.15#ibcon#about to write, iclass 37, count 0 2006.285.07:50:37.15#ibcon#wrote, iclass 37, count 0 2006.285.07:50:37.15#ibcon#about to read 3, iclass 37, count 0 2006.285.07:50:37.17#ibcon#read 3, iclass 37, count 0 2006.285.07:50:37.17#ibcon#about to read 4, iclass 37, count 0 2006.285.07:50:37.17#ibcon#read 4, iclass 37, count 0 2006.285.07:50:37.17#ibcon#about to read 5, iclass 37, count 0 2006.285.07:50:37.17#ibcon#read 5, iclass 37, count 0 2006.285.07:50:37.17#ibcon#about to read 6, iclass 37, count 0 2006.285.07:50:37.17#ibcon#read 6, iclass 37, count 0 2006.285.07:50:37.17#ibcon#end of sib2, iclass 37, count 0 2006.285.07:50:37.17#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:50:37.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:50:37.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:50:37.17#ibcon#*before write, iclass 37, count 0 2006.285.07:50:37.17#ibcon#enter sib2, iclass 37, count 0 2006.285.07:50:37.17#ibcon#flushed, iclass 37, count 0 2006.285.07:50:37.17#ibcon#about to write, iclass 37, count 0 2006.285.07:50:37.17#ibcon#wrote, iclass 37, count 0 2006.285.07:50:37.17#ibcon#about to read 3, iclass 37, count 0 2006.285.07:50:37.21#ibcon#read 3, iclass 37, count 0 2006.285.07:50:37.21#ibcon#about to read 4, iclass 37, count 0 2006.285.07:50:37.21#ibcon#read 4, iclass 37, count 0 2006.285.07:50:37.21#ibcon#about to read 5, iclass 37, count 0 2006.285.07:50:37.21#ibcon#read 5, iclass 37, count 0 2006.285.07:50:37.21#ibcon#about to read 6, iclass 37, count 0 2006.285.07:50:37.21#ibcon#read 6, iclass 37, count 0 2006.285.07:50:37.21#ibcon#end of sib2, iclass 37, count 0 2006.285.07:50:37.21#ibcon#*after write, iclass 37, count 0 2006.285.07:50:37.21#ibcon#*before return 0, iclass 37, count 0 2006.285.07:50:37.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:50:37.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.07:50:37.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:50:37.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:50:37.21$vck44/vb=1,4 2006.285.07:50:37.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.07:50:37.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.07:50:37.21#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:37.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:50:37.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:50:37.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:50:37.21#ibcon#enter wrdev, iclass 39, count 2 2006.285.07:50:37.21#ibcon#first serial, iclass 39, count 2 2006.285.07:50:37.21#ibcon#enter sib2, iclass 39, count 2 2006.285.07:50:37.21#ibcon#flushed, iclass 39, count 2 2006.285.07:50:37.21#ibcon#about to write, iclass 39, count 2 2006.285.07:50:37.21#ibcon#wrote, iclass 39, count 2 2006.285.07:50:37.21#ibcon#about to read 3, iclass 39, count 2 2006.285.07:50:37.23#ibcon#read 3, iclass 39, count 2 2006.285.07:50:37.23#ibcon#about to read 4, iclass 39, count 2 2006.285.07:50:37.23#ibcon#read 4, iclass 39, count 2 2006.285.07:50:37.23#ibcon#about to read 5, iclass 39, count 2 2006.285.07:50:37.23#ibcon#read 5, iclass 39, count 2 2006.285.07:50:37.23#ibcon#about to read 6, iclass 39, count 2 2006.285.07:50:37.23#ibcon#read 6, iclass 39, count 2 2006.285.07:50:37.23#ibcon#end of sib2, iclass 39, count 2 2006.285.07:50:37.23#ibcon#*mode == 0, iclass 39, count 2 2006.285.07:50:37.23#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.07:50:37.23#ibcon#[27=AT01-04\r\n] 2006.285.07:50:37.23#ibcon#*before write, iclass 39, count 2 2006.285.07:50:37.23#ibcon#enter sib2, iclass 39, count 2 2006.285.07:50:37.23#ibcon#flushed, iclass 39, count 2 2006.285.07:50:37.23#ibcon#about to write, iclass 39, count 2 2006.285.07:50:37.23#ibcon#wrote, iclass 39, count 2 2006.285.07:50:37.23#ibcon#about to read 3, iclass 39, count 2 2006.285.07:50:37.26#ibcon#read 3, iclass 39, count 2 2006.285.07:50:37.26#ibcon#about to read 4, iclass 39, count 2 2006.285.07:50:37.26#ibcon#read 4, iclass 39, count 2 2006.285.07:50:37.26#ibcon#about to read 5, iclass 39, count 2 2006.285.07:50:37.26#ibcon#read 5, iclass 39, count 2 2006.285.07:50:37.26#ibcon#about to read 6, iclass 39, count 2 2006.285.07:50:37.26#ibcon#read 6, iclass 39, count 2 2006.285.07:50:37.26#ibcon#end of sib2, iclass 39, count 2 2006.285.07:50:37.26#ibcon#*after write, iclass 39, count 2 2006.285.07:50:37.26#ibcon#*before return 0, iclass 39, count 2 2006.285.07:50:37.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:50:37.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.07:50:37.26#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.07:50:37.26#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:37.26#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:50:37.38#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:50:37.38#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:50:37.38#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:50:37.38#ibcon#first serial, iclass 39, count 0 2006.285.07:50:37.38#ibcon#enter sib2, iclass 39, count 0 2006.285.07:50:37.38#ibcon#flushed, iclass 39, count 0 2006.285.07:50:37.38#ibcon#about to write, iclass 39, count 0 2006.285.07:50:37.38#ibcon#wrote, iclass 39, count 0 2006.285.07:50:37.38#ibcon#about to read 3, iclass 39, count 0 2006.285.07:50:37.40#ibcon#read 3, iclass 39, count 0 2006.285.07:50:37.40#ibcon#about to read 4, iclass 39, count 0 2006.285.07:50:37.40#ibcon#read 4, iclass 39, count 0 2006.285.07:50:37.40#ibcon#about to read 5, iclass 39, count 0 2006.285.07:50:37.40#ibcon#read 5, iclass 39, count 0 2006.285.07:50:37.40#ibcon#about to read 6, iclass 39, count 0 2006.285.07:50:37.40#ibcon#read 6, iclass 39, count 0 2006.285.07:50:37.40#ibcon#end of sib2, iclass 39, count 0 2006.285.07:50:37.40#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:50:37.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:50:37.40#ibcon#[27=USB\r\n] 2006.285.07:50:37.40#ibcon#*before write, iclass 39, count 0 2006.285.07:50:37.40#ibcon#enter sib2, iclass 39, count 0 2006.285.07:50:37.40#ibcon#flushed, iclass 39, count 0 2006.285.07:50:37.40#ibcon#about to write, iclass 39, count 0 2006.285.07:50:37.40#ibcon#wrote, iclass 39, count 0 2006.285.07:50:37.40#ibcon#about to read 3, iclass 39, count 0 2006.285.07:50:37.43#ibcon#read 3, iclass 39, count 0 2006.285.07:50:37.43#ibcon#about to read 4, iclass 39, count 0 2006.285.07:50:37.43#ibcon#read 4, iclass 39, count 0 2006.285.07:50:37.43#ibcon#about to read 5, iclass 39, count 0 2006.285.07:50:37.43#ibcon#read 5, iclass 39, count 0 2006.285.07:50:37.43#ibcon#about to read 6, iclass 39, count 0 2006.285.07:50:37.43#ibcon#read 6, iclass 39, count 0 2006.285.07:50:37.43#ibcon#end of sib2, iclass 39, count 0 2006.285.07:50:37.43#ibcon#*after write, iclass 39, count 0 2006.285.07:50:37.43#ibcon#*before return 0, iclass 39, count 0 2006.285.07:50:37.43#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:50:37.43#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.07:50:37.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:50:37.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:50:37.43$vck44/vblo=2,634.99 2006.285.07:50:37.43#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.07:50:37.43#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.07:50:37.43#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:37.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:50:37.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:50:37.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:50:37.43#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:50:37.43#ibcon#first serial, iclass 3, count 0 2006.285.07:50:37.43#ibcon#enter sib2, iclass 3, count 0 2006.285.07:50:37.43#ibcon#flushed, iclass 3, count 0 2006.285.07:50:37.43#ibcon#about to write, iclass 3, count 0 2006.285.07:50:37.43#ibcon#wrote, iclass 3, count 0 2006.285.07:50:37.43#ibcon#about to read 3, iclass 3, count 0 2006.285.07:50:37.45#ibcon#read 3, iclass 3, count 0 2006.285.07:50:37.45#ibcon#about to read 4, iclass 3, count 0 2006.285.07:50:37.45#ibcon#read 4, iclass 3, count 0 2006.285.07:50:37.45#ibcon#about to read 5, iclass 3, count 0 2006.285.07:50:37.45#ibcon#read 5, iclass 3, count 0 2006.285.07:50:37.45#ibcon#about to read 6, iclass 3, count 0 2006.285.07:50:37.45#ibcon#read 6, iclass 3, count 0 2006.285.07:50:37.45#ibcon#end of sib2, iclass 3, count 0 2006.285.07:50:37.45#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:50:37.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:50:37.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:50:37.45#ibcon#*before write, iclass 3, count 0 2006.285.07:50:37.45#ibcon#enter sib2, iclass 3, count 0 2006.285.07:50:37.45#ibcon#flushed, iclass 3, count 0 2006.285.07:50:37.45#ibcon#about to write, iclass 3, count 0 2006.285.07:50:37.45#ibcon#wrote, iclass 3, count 0 2006.285.07:50:37.45#ibcon#about to read 3, iclass 3, count 0 2006.285.07:50:37.49#ibcon#read 3, iclass 3, count 0 2006.285.07:50:37.49#ibcon#about to read 4, iclass 3, count 0 2006.285.07:50:37.49#ibcon#read 4, iclass 3, count 0 2006.285.07:50:37.49#ibcon#about to read 5, iclass 3, count 0 2006.285.07:50:37.49#ibcon#read 5, iclass 3, count 0 2006.285.07:50:37.49#ibcon#about to read 6, iclass 3, count 0 2006.285.07:50:37.49#ibcon#read 6, iclass 3, count 0 2006.285.07:50:37.49#ibcon#end of sib2, iclass 3, count 0 2006.285.07:50:37.49#ibcon#*after write, iclass 3, count 0 2006.285.07:50:37.49#ibcon#*before return 0, iclass 3, count 0 2006.285.07:50:37.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:50:37.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.07:50:37.49#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:50:37.49#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:50:37.49$vck44/vb=2,5 2006.285.07:50:37.49#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.07:50:37.49#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.07:50:37.49#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:37.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:50:37.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:50:37.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:50:37.55#ibcon#enter wrdev, iclass 5, count 2 2006.285.07:50:37.55#ibcon#first serial, iclass 5, count 2 2006.285.07:50:37.55#ibcon#enter sib2, iclass 5, count 2 2006.285.07:50:37.55#ibcon#flushed, iclass 5, count 2 2006.285.07:50:37.55#ibcon#about to write, iclass 5, count 2 2006.285.07:50:37.55#ibcon#wrote, iclass 5, count 2 2006.285.07:50:37.55#ibcon#about to read 3, iclass 5, count 2 2006.285.07:50:37.57#ibcon#read 3, iclass 5, count 2 2006.285.07:50:37.57#ibcon#about to read 4, iclass 5, count 2 2006.285.07:50:37.57#ibcon#read 4, iclass 5, count 2 2006.285.07:50:37.57#ibcon#about to read 5, iclass 5, count 2 2006.285.07:50:37.57#ibcon#read 5, iclass 5, count 2 2006.285.07:50:37.57#ibcon#about to read 6, iclass 5, count 2 2006.285.07:50:37.57#ibcon#read 6, iclass 5, count 2 2006.285.07:50:37.57#ibcon#end of sib2, iclass 5, count 2 2006.285.07:50:37.57#ibcon#*mode == 0, iclass 5, count 2 2006.285.07:50:37.57#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.07:50:37.57#ibcon#[27=AT02-05\r\n] 2006.285.07:50:37.57#ibcon#*before write, iclass 5, count 2 2006.285.07:50:37.57#ibcon#enter sib2, iclass 5, count 2 2006.285.07:50:37.57#ibcon#flushed, iclass 5, count 2 2006.285.07:50:37.57#ibcon#about to write, iclass 5, count 2 2006.285.07:50:37.57#ibcon#wrote, iclass 5, count 2 2006.285.07:50:37.57#ibcon#about to read 3, iclass 5, count 2 2006.285.07:50:37.60#ibcon#read 3, iclass 5, count 2 2006.285.07:50:37.60#ibcon#about to read 4, iclass 5, count 2 2006.285.07:50:37.60#ibcon#read 4, iclass 5, count 2 2006.285.07:50:37.60#ibcon#about to read 5, iclass 5, count 2 2006.285.07:50:37.60#ibcon#read 5, iclass 5, count 2 2006.285.07:50:37.60#ibcon#about to read 6, iclass 5, count 2 2006.285.07:50:37.60#ibcon#read 6, iclass 5, count 2 2006.285.07:50:37.60#ibcon#end of sib2, iclass 5, count 2 2006.285.07:50:37.60#ibcon#*after write, iclass 5, count 2 2006.285.07:50:37.60#ibcon#*before return 0, iclass 5, count 2 2006.285.07:50:37.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:50:37.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.07:50:37.60#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.07:50:37.60#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:37.60#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:50:37.72#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:50:37.72#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:50:37.72#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:50:37.72#ibcon#first serial, iclass 5, count 0 2006.285.07:50:37.72#ibcon#enter sib2, iclass 5, count 0 2006.285.07:50:37.72#ibcon#flushed, iclass 5, count 0 2006.285.07:50:37.72#ibcon#about to write, iclass 5, count 0 2006.285.07:50:37.72#ibcon#wrote, iclass 5, count 0 2006.285.07:50:37.72#ibcon#about to read 3, iclass 5, count 0 2006.285.07:50:37.74#ibcon#read 3, iclass 5, count 0 2006.285.07:50:37.74#ibcon#about to read 4, iclass 5, count 0 2006.285.07:50:37.74#ibcon#read 4, iclass 5, count 0 2006.285.07:50:37.74#ibcon#about to read 5, iclass 5, count 0 2006.285.07:50:37.74#ibcon#read 5, iclass 5, count 0 2006.285.07:50:37.74#ibcon#about to read 6, iclass 5, count 0 2006.285.07:50:37.74#ibcon#read 6, iclass 5, count 0 2006.285.07:50:37.74#ibcon#end of sib2, iclass 5, count 0 2006.285.07:50:37.74#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:50:37.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:50:37.74#ibcon#[27=USB\r\n] 2006.285.07:50:37.74#ibcon#*before write, iclass 5, count 0 2006.285.07:50:37.74#ibcon#enter sib2, iclass 5, count 0 2006.285.07:50:37.74#ibcon#flushed, iclass 5, count 0 2006.285.07:50:37.74#ibcon#about to write, iclass 5, count 0 2006.285.07:50:37.74#ibcon#wrote, iclass 5, count 0 2006.285.07:50:37.74#ibcon#about to read 3, iclass 5, count 0 2006.285.07:50:37.77#ibcon#read 3, iclass 5, count 0 2006.285.07:50:37.77#ibcon#about to read 4, iclass 5, count 0 2006.285.07:50:37.77#ibcon#read 4, iclass 5, count 0 2006.285.07:50:37.77#ibcon#about to read 5, iclass 5, count 0 2006.285.07:50:37.77#ibcon#read 5, iclass 5, count 0 2006.285.07:50:37.77#ibcon#about to read 6, iclass 5, count 0 2006.285.07:50:37.77#ibcon#read 6, iclass 5, count 0 2006.285.07:50:37.77#ibcon#end of sib2, iclass 5, count 0 2006.285.07:50:37.77#ibcon#*after write, iclass 5, count 0 2006.285.07:50:37.77#ibcon#*before return 0, iclass 5, count 0 2006.285.07:50:37.77#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:50:37.77#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.07:50:37.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:50:37.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:50:37.77$vck44/vblo=3,649.99 2006.285.07:50:37.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.07:50:37.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.07:50:37.77#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:37.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:50:37.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:50:37.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:50:37.77#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:50:37.77#ibcon#first serial, iclass 7, count 0 2006.285.07:50:37.77#ibcon#enter sib2, iclass 7, count 0 2006.285.07:50:37.77#ibcon#flushed, iclass 7, count 0 2006.285.07:50:37.77#ibcon#about to write, iclass 7, count 0 2006.285.07:50:37.77#ibcon#wrote, iclass 7, count 0 2006.285.07:50:37.77#ibcon#about to read 3, iclass 7, count 0 2006.285.07:50:37.79#ibcon#read 3, iclass 7, count 0 2006.285.07:50:37.79#ibcon#about to read 4, iclass 7, count 0 2006.285.07:50:37.79#ibcon#read 4, iclass 7, count 0 2006.285.07:50:37.79#ibcon#about to read 5, iclass 7, count 0 2006.285.07:50:37.79#ibcon#read 5, iclass 7, count 0 2006.285.07:50:37.79#ibcon#about to read 6, iclass 7, count 0 2006.285.07:50:37.79#ibcon#read 6, iclass 7, count 0 2006.285.07:50:37.79#ibcon#end of sib2, iclass 7, count 0 2006.285.07:50:37.79#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:50:37.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:50:37.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:50:37.79#ibcon#*before write, iclass 7, count 0 2006.285.07:50:37.79#ibcon#enter sib2, iclass 7, count 0 2006.285.07:50:37.79#ibcon#flushed, iclass 7, count 0 2006.285.07:50:37.79#ibcon#about to write, iclass 7, count 0 2006.285.07:50:37.79#ibcon#wrote, iclass 7, count 0 2006.285.07:50:37.79#ibcon#about to read 3, iclass 7, count 0 2006.285.07:50:37.83#ibcon#read 3, iclass 7, count 0 2006.285.07:50:37.83#ibcon#about to read 4, iclass 7, count 0 2006.285.07:50:37.83#ibcon#read 4, iclass 7, count 0 2006.285.07:50:37.83#ibcon#about to read 5, iclass 7, count 0 2006.285.07:50:37.83#ibcon#read 5, iclass 7, count 0 2006.285.07:50:37.83#ibcon#about to read 6, iclass 7, count 0 2006.285.07:50:37.83#ibcon#read 6, iclass 7, count 0 2006.285.07:50:37.83#ibcon#end of sib2, iclass 7, count 0 2006.285.07:50:37.83#ibcon#*after write, iclass 7, count 0 2006.285.07:50:37.83#ibcon#*before return 0, iclass 7, count 0 2006.285.07:50:37.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:50:37.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.07:50:37.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:50:37.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:50:37.83$vck44/vb=3,4 2006.285.07:50:37.83#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.07:50:37.83#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.07:50:37.83#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:37.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:50:37.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:50:37.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:50:37.89#ibcon#enter wrdev, iclass 11, count 2 2006.285.07:50:37.89#ibcon#first serial, iclass 11, count 2 2006.285.07:50:37.89#ibcon#enter sib2, iclass 11, count 2 2006.285.07:50:37.89#ibcon#flushed, iclass 11, count 2 2006.285.07:50:37.89#ibcon#about to write, iclass 11, count 2 2006.285.07:50:37.89#ibcon#wrote, iclass 11, count 2 2006.285.07:50:37.89#ibcon#about to read 3, iclass 11, count 2 2006.285.07:50:37.91#ibcon#read 3, iclass 11, count 2 2006.285.07:50:37.91#ibcon#about to read 4, iclass 11, count 2 2006.285.07:50:37.91#ibcon#read 4, iclass 11, count 2 2006.285.07:50:37.91#ibcon#about to read 5, iclass 11, count 2 2006.285.07:50:37.91#ibcon#read 5, iclass 11, count 2 2006.285.07:50:37.91#ibcon#about to read 6, iclass 11, count 2 2006.285.07:50:37.91#ibcon#read 6, iclass 11, count 2 2006.285.07:50:37.91#ibcon#end of sib2, iclass 11, count 2 2006.285.07:50:37.91#ibcon#*mode == 0, iclass 11, count 2 2006.285.07:50:37.91#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.07:50:37.91#ibcon#[27=AT03-04\r\n] 2006.285.07:50:37.91#ibcon#*before write, iclass 11, count 2 2006.285.07:50:37.91#ibcon#enter sib2, iclass 11, count 2 2006.285.07:50:37.91#ibcon#flushed, iclass 11, count 2 2006.285.07:50:37.91#ibcon#about to write, iclass 11, count 2 2006.285.07:50:37.91#ibcon#wrote, iclass 11, count 2 2006.285.07:50:37.91#ibcon#about to read 3, iclass 11, count 2 2006.285.07:50:37.94#ibcon#read 3, iclass 11, count 2 2006.285.07:50:37.94#ibcon#about to read 4, iclass 11, count 2 2006.285.07:50:37.94#ibcon#read 4, iclass 11, count 2 2006.285.07:50:37.94#ibcon#about to read 5, iclass 11, count 2 2006.285.07:50:37.94#ibcon#read 5, iclass 11, count 2 2006.285.07:50:37.94#ibcon#about to read 6, iclass 11, count 2 2006.285.07:50:37.94#ibcon#read 6, iclass 11, count 2 2006.285.07:50:37.94#ibcon#end of sib2, iclass 11, count 2 2006.285.07:50:37.94#ibcon#*after write, iclass 11, count 2 2006.285.07:50:37.94#ibcon#*before return 0, iclass 11, count 2 2006.285.07:50:37.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:50:37.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.07:50:37.94#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.07:50:37.94#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:37.94#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:50:38.06#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:50:38.06#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:50:38.06#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:50:38.06#ibcon#first serial, iclass 11, count 0 2006.285.07:50:38.06#ibcon#enter sib2, iclass 11, count 0 2006.285.07:50:38.06#ibcon#flushed, iclass 11, count 0 2006.285.07:50:38.06#ibcon#about to write, iclass 11, count 0 2006.285.07:50:38.06#ibcon#wrote, iclass 11, count 0 2006.285.07:50:38.06#ibcon#about to read 3, iclass 11, count 0 2006.285.07:50:38.08#ibcon#read 3, iclass 11, count 0 2006.285.07:50:38.08#ibcon#about to read 4, iclass 11, count 0 2006.285.07:50:38.08#ibcon#read 4, iclass 11, count 0 2006.285.07:50:38.08#ibcon#about to read 5, iclass 11, count 0 2006.285.07:50:38.08#ibcon#read 5, iclass 11, count 0 2006.285.07:50:38.08#ibcon#about to read 6, iclass 11, count 0 2006.285.07:50:38.08#ibcon#read 6, iclass 11, count 0 2006.285.07:50:38.08#ibcon#end of sib2, iclass 11, count 0 2006.285.07:50:38.08#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:50:38.08#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:50:38.08#ibcon#[27=USB\r\n] 2006.285.07:50:38.08#ibcon#*before write, iclass 11, count 0 2006.285.07:50:38.08#ibcon#enter sib2, iclass 11, count 0 2006.285.07:50:38.08#ibcon#flushed, iclass 11, count 0 2006.285.07:50:38.08#ibcon#about to write, iclass 11, count 0 2006.285.07:50:38.08#ibcon#wrote, iclass 11, count 0 2006.285.07:50:38.08#ibcon#about to read 3, iclass 11, count 0 2006.285.07:50:38.11#ibcon#read 3, iclass 11, count 0 2006.285.07:50:38.11#ibcon#about to read 4, iclass 11, count 0 2006.285.07:50:38.11#ibcon#read 4, iclass 11, count 0 2006.285.07:50:38.11#ibcon#about to read 5, iclass 11, count 0 2006.285.07:50:38.11#ibcon#read 5, iclass 11, count 0 2006.285.07:50:38.11#ibcon#about to read 6, iclass 11, count 0 2006.285.07:50:38.11#ibcon#read 6, iclass 11, count 0 2006.285.07:50:38.11#ibcon#end of sib2, iclass 11, count 0 2006.285.07:50:38.11#ibcon#*after write, iclass 11, count 0 2006.285.07:50:38.11#ibcon#*before return 0, iclass 11, count 0 2006.285.07:50:38.11#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:50:38.11#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.07:50:38.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:50:38.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:50:38.11$vck44/vblo=4,679.99 2006.285.07:50:38.11#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.07:50:38.11#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.07:50:38.11#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:38.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:50:38.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:50:38.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:50:38.11#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:50:38.11#ibcon#first serial, iclass 13, count 0 2006.285.07:50:38.11#ibcon#enter sib2, iclass 13, count 0 2006.285.07:50:38.11#ibcon#flushed, iclass 13, count 0 2006.285.07:50:38.11#ibcon#about to write, iclass 13, count 0 2006.285.07:50:38.11#ibcon#wrote, iclass 13, count 0 2006.285.07:50:38.11#ibcon#about to read 3, iclass 13, count 0 2006.285.07:50:38.13#ibcon#read 3, iclass 13, count 0 2006.285.07:50:38.13#ibcon#about to read 4, iclass 13, count 0 2006.285.07:50:38.13#ibcon#read 4, iclass 13, count 0 2006.285.07:50:38.13#ibcon#about to read 5, iclass 13, count 0 2006.285.07:50:38.13#ibcon#read 5, iclass 13, count 0 2006.285.07:50:38.13#ibcon#about to read 6, iclass 13, count 0 2006.285.07:50:38.13#ibcon#read 6, iclass 13, count 0 2006.285.07:50:38.13#ibcon#end of sib2, iclass 13, count 0 2006.285.07:50:38.13#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:50:38.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:50:38.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:50:38.13#ibcon#*before write, iclass 13, count 0 2006.285.07:50:38.13#ibcon#enter sib2, iclass 13, count 0 2006.285.07:50:38.13#ibcon#flushed, iclass 13, count 0 2006.285.07:50:38.13#ibcon#about to write, iclass 13, count 0 2006.285.07:50:38.13#ibcon#wrote, iclass 13, count 0 2006.285.07:50:38.13#ibcon#about to read 3, iclass 13, count 0 2006.285.07:50:38.17#ibcon#read 3, iclass 13, count 0 2006.285.07:50:38.17#ibcon#about to read 4, iclass 13, count 0 2006.285.07:50:38.17#ibcon#read 4, iclass 13, count 0 2006.285.07:50:38.17#ibcon#about to read 5, iclass 13, count 0 2006.285.07:50:38.17#ibcon#read 5, iclass 13, count 0 2006.285.07:50:38.17#ibcon#about to read 6, iclass 13, count 0 2006.285.07:50:38.17#ibcon#read 6, iclass 13, count 0 2006.285.07:50:38.17#ibcon#end of sib2, iclass 13, count 0 2006.285.07:50:38.17#ibcon#*after write, iclass 13, count 0 2006.285.07:50:38.17#ibcon#*before return 0, iclass 13, count 0 2006.285.07:50:38.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:50:38.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.07:50:38.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:50:38.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:50:38.17$vck44/vb=4,5 2006.285.07:50:38.17#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.07:50:38.17#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.07:50:38.17#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:38.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:50:38.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:50:38.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:50:38.23#ibcon#enter wrdev, iclass 15, count 2 2006.285.07:50:38.23#ibcon#first serial, iclass 15, count 2 2006.285.07:50:38.23#ibcon#enter sib2, iclass 15, count 2 2006.285.07:50:38.23#ibcon#flushed, iclass 15, count 2 2006.285.07:50:38.23#ibcon#about to write, iclass 15, count 2 2006.285.07:50:38.23#ibcon#wrote, iclass 15, count 2 2006.285.07:50:38.23#ibcon#about to read 3, iclass 15, count 2 2006.285.07:50:38.25#ibcon#read 3, iclass 15, count 2 2006.285.07:50:38.25#ibcon#about to read 4, iclass 15, count 2 2006.285.07:50:38.25#ibcon#read 4, iclass 15, count 2 2006.285.07:50:38.25#ibcon#about to read 5, iclass 15, count 2 2006.285.07:50:38.25#ibcon#read 5, iclass 15, count 2 2006.285.07:50:38.25#ibcon#about to read 6, iclass 15, count 2 2006.285.07:50:38.25#ibcon#read 6, iclass 15, count 2 2006.285.07:50:38.25#ibcon#end of sib2, iclass 15, count 2 2006.285.07:50:38.25#ibcon#*mode == 0, iclass 15, count 2 2006.285.07:50:38.25#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.07:50:38.25#ibcon#[27=AT04-05\r\n] 2006.285.07:50:38.25#ibcon#*before write, iclass 15, count 2 2006.285.07:50:38.25#ibcon#enter sib2, iclass 15, count 2 2006.285.07:50:38.25#ibcon#flushed, iclass 15, count 2 2006.285.07:50:38.25#ibcon#about to write, iclass 15, count 2 2006.285.07:50:38.25#ibcon#wrote, iclass 15, count 2 2006.285.07:50:38.25#ibcon#about to read 3, iclass 15, count 2 2006.285.07:50:38.28#ibcon#read 3, iclass 15, count 2 2006.285.07:50:38.28#ibcon#about to read 4, iclass 15, count 2 2006.285.07:50:38.28#ibcon#read 4, iclass 15, count 2 2006.285.07:50:38.28#ibcon#about to read 5, iclass 15, count 2 2006.285.07:50:38.28#ibcon#read 5, iclass 15, count 2 2006.285.07:50:38.28#ibcon#about to read 6, iclass 15, count 2 2006.285.07:50:38.28#ibcon#read 6, iclass 15, count 2 2006.285.07:50:38.28#ibcon#end of sib2, iclass 15, count 2 2006.285.07:50:38.28#ibcon#*after write, iclass 15, count 2 2006.285.07:50:38.28#ibcon#*before return 0, iclass 15, count 2 2006.285.07:50:38.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:50:38.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.07:50:38.28#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.07:50:38.28#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:38.28#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:50:38.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:50:38.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:50:38.40#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:50:38.40#ibcon#first serial, iclass 15, count 0 2006.285.07:50:38.40#ibcon#enter sib2, iclass 15, count 0 2006.285.07:50:38.40#ibcon#flushed, iclass 15, count 0 2006.285.07:50:38.40#ibcon#about to write, iclass 15, count 0 2006.285.07:50:38.40#ibcon#wrote, iclass 15, count 0 2006.285.07:50:38.40#ibcon#about to read 3, iclass 15, count 0 2006.285.07:50:38.42#ibcon#read 3, iclass 15, count 0 2006.285.07:50:38.42#ibcon#about to read 4, iclass 15, count 0 2006.285.07:50:38.42#ibcon#read 4, iclass 15, count 0 2006.285.07:50:38.42#ibcon#about to read 5, iclass 15, count 0 2006.285.07:50:38.42#ibcon#read 5, iclass 15, count 0 2006.285.07:50:38.42#ibcon#about to read 6, iclass 15, count 0 2006.285.07:50:38.42#ibcon#read 6, iclass 15, count 0 2006.285.07:50:38.42#ibcon#end of sib2, iclass 15, count 0 2006.285.07:50:38.42#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:50:38.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:50:38.42#ibcon#[27=USB\r\n] 2006.285.07:50:38.42#ibcon#*before write, iclass 15, count 0 2006.285.07:50:38.42#ibcon#enter sib2, iclass 15, count 0 2006.285.07:50:38.42#ibcon#flushed, iclass 15, count 0 2006.285.07:50:38.42#ibcon#about to write, iclass 15, count 0 2006.285.07:50:38.42#ibcon#wrote, iclass 15, count 0 2006.285.07:50:38.42#ibcon#about to read 3, iclass 15, count 0 2006.285.07:50:38.45#ibcon#read 3, iclass 15, count 0 2006.285.07:50:38.45#ibcon#about to read 4, iclass 15, count 0 2006.285.07:50:38.45#ibcon#read 4, iclass 15, count 0 2006.285.07:50:38.45#ibcon#about to read 5, iclass 15, count 0 2006.285.07:50:38.45#ibcon#read 5, iclass 15, count 0 2006.285.07:50:38.45#ibcon#about to read 6, iclass 15, count 0 2006.285.07:50:38.45#ibcon#read 6, iclass 15, count 0 2006.285.07:50:38.45#ibcon#end of sib2, iclass 15, count 0 2006.285.07:50:38.45#ibcon#*after write, iclass 15, count 0 2006.285.07:50:38.45#ibcon#*before return 0, iclass 15, count 0 2006.285.07:50:38.45#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:50:38.45#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.07:50:38.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:50:38.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:50:38.45$vck44/vblo=5,709.99 2006.285.07:50:38.45#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.07:50:38.45#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.07:50:38.45#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:38.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:50:38.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:50:38.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:50:38.45#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:50:38.45#ibcon#first serial, iclass 17, count 0 2006.285.07:50:38.45#ibcon#enter sib2, iclass 17, count 0 2006.285.07:50:38.45#ibcon#flushed, iclass 17, count 0 2006.285.07:50:38.45#ibcon#about to write, iclass 17, count 0 2006.285.07:50:38.45#ibcon#wrote, iclass 17, count 0 2006.285.07:50:38.45#ibcon#about to read 3, iclass 17, count 0 2006.285.07:50:38.47#ibcon#read 3, iclass 17, count 0 2006.285.07:50:38.47#ibcon#about to read 4, iclass 17, count 0 2006.285.07:50:38.47#ibcon#read 4, iclass 17, count 0 2006.285.07:50:38.47#ibcon#about to read 5, iclass 17, count 0 2006.285.07:50:38.47#ibcon#read 5, iclass 17, count 0 2006.285.07:50:38.47#ibcon#about to read 6, iclass 17, count 0 2006.285.07:50:38.47#ibcon#read 6, iclass 17, count 0 2006.285.07:50:38.47#ibcon#end of sib2, iclass 17, count 0 2006.285.07:50:38.47#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:50:38.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:50:38.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:50:38.47#ibcon#*before write, iclass 17, count 0 2006.285.07:50:38.47#ibcon#enter sib2, iclass 17, count 0 2006.285.07:50:38.47#ibcon#flushed, iclass 17, count 0 2006.285.07:50:38.47#ibcon#about to write, iclass 17, count 0 2006.285.07:50:38.47#ibcon#wrote, iclass 17, count 0 2006.285.07:50:38.47#ibcon#about to read 3, iclass 17, count 0 2006.285.07:50:38.51#ibcon#read 3, iclass 17, count 0 2006.285.07:50:38.51#ibcon#about to read 4, iclass 17, count 0 2006.285.07:50:38.51#ibcon#read 4, iclass 17, count 0 2006.285.07:50:38.51#ibcon#about to read 5, iclass 17, count 0 2006.285.07:50:38.51#ibcon#read 5, iclass 17, count 0 2006.285.07:50:38.51#ibcon#about to read 6, iclass 17, count 0 2006.285.07:50:38.51#ibcon#read 6, iclass 17, count 0 2006.285.07:50:38.51#ibcon#end of sib2, iclass 17, count 0 2006.285.07:50:38.51#ibcon#*after write, iclass 17, count 0 2006.285.07:50:38.51#ibcon#*before return 0, iclass 17, count 0 2006.285.07:50:38.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:50:38.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.07:50:38.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:50:38.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:50:38.51$vck44/vb=5,4 2006.285.07:50:38.51#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.07:50:38.51#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.07:50:38.51#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:38.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:50:38.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:50:38.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:50:38.57#ibcon#enter wrdev, iclass 19, count 2 2006.285.07:50:38.57#ibcon#first serial, iclass 19, count 2 2006.285.07:50:38.57#ibcon#enter sib2, iclass 19, count 2 2006.285.07:50:38.57#ibcon#flushed, iclass 19, count 2 2006.285.07:50:38.57#ibcon#about to write, iclass 19, count 2 2006.285.07:50:38.57#ibcon#wrote, iclass 19, count 2 2006.285.07:50:38.57#ibcon#about to read 3, iclass 19, count 2 2006.285.07:50:38.59#ibcon#read 3, iclass 19, count 2 2006.285.07:50:38.59#ibcon#about to read 4, iclass 19, count 2 2006.285.07:50:38.59#ibcon#read 4, iclass 19, count 2 2006.285.07:50:38.59#ibcon#about to read 5, iclass 19, count 2 2006.285.07:50:38.59#ibcon#read 5, iclass 19, count 2 2006.285.07:50:38.59#ibcon#about to read 6, iclass 19, count 2 2006.285.07:50:38.59#ibcon#read 6, iclass 19, count 2 2006.285.07:50:38.59#ibcon#end of sib2, iclass 19, count 2 2006.285.07:50:38.59#ibcon#*mode == 0, iclass 19, count 2 2006.285.07:50:38.59#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.07:50:38.59#ibcon#[27=AT05-04\r\n] 2006.285.07:50:38.59#ibcon#*before write, iclass 19, count 2 2006.285.07:50:38.59#ibcon#enter sib2, iclass 19, count 2 2006.285.07:50:38.59#ibcon#flushed, iclass 19, count 2 2006.285.07:50:38.59#ibcon#about to write, iclass 19, count 2 2006.285.07:50:38.59#ibcon#wrote, iclass 19, count 2 2006.285.07:50:38.59#ibcon#about to read 3, iclass 19, count 2 2006.285.07:50:38.62#ibcon#read 3, iclass 19, count 2 2006.285.07:50:38.62#ibcon#about to read 4, iclass 19, count 2 2006.285.07:50:38.62#ibcon#read 4, iclass 19, count 2 2006.285.07:50:38.62#ibcon#about to read 5, iclass 19, count 2 2006.285.07:50:38.62#ibcon#read 5, iclass 19, count 2 2006.285.07:50:38.62#ibcon#about to read 6, iclass 19, count 2 2006.285.07:50:38.62#ibcon#read 6, iclass 19, count 2 2006.285.07:50:38.62#ibcon#end of sib2, iclass 19, count 2 2006.285.07:50:38.62#ibcon#*after write, iclass 19, count 2 2006.285.07:50:38.62#ibcon#*before return 0, iclass 19, count 2 2006.285.07:50:38.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:50:38.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.07:50:38.62#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.07:50:38.62#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:38.62#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:50:38.74#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:50:38.74#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:50:38.74#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:50:38.74#ibcon#first serial, iclass 19, count 0 2006.285.07:50:38.74#ibcon#enter sib2, iclass 19, count 0 2006.285.07:50:38.74#ibcon#flushed, iclass 19, count 0 2006.285.07:50:38.74#ibcon#about to write, iclass 19, count 0 2006.285.07:50:38.74#ibcon#wrote, iclass 19, count 0 2006.285.07:50:38.74#ibcon#about to read 3, iclass 19, count 0 2006.285.07:50:38.76#ibcon#read 3, iclass 19, count 0 2006.285.07:50:38.76#ibcon#about to read 4, iclass 19, count 0 2006.285.07:50:38.76#ibcon#read 4, iclass 19, count 0 2006.285.07:50:38.76#ibcon#about to read 5, iclass 19, count 0 2006.285.07:50:38.76#ibcon#read 5, iclass 19, count 0 2006.285.07:50:38.76#ibcon#about to read 6, iclass 19, count 0 2006.285.07:50:38.76#ibcon#read 6, iclass 19, count 0 2006.285.07:50:38.76#ibcon#end of sib2, iclass 19, count 0 2006.285.07:50:38.76#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:50:38.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:50:38.76#ibcon#[27=USB\r\n] 2006.285.07:50:38.76#ibcon#*before write, iclass 19, count 0 2006.285.07:50:38.76#ibcon#enter sib2, iclass 19, count 0 2006.285.07:50:38.76#ibcon#flushed, iclass 19, count 0 2006.285.07:50:38.76#ibcon#about to write, iclass 19, count 0 2006.285.07:50:38.76#ibcon#wrote, iclass 19, count 0 2006.285.07:50:38.76#ibcon#about to read 3, iclass 19, count 0 2006.285.07:50:38.79#ibcon#read 3, iclass 19, count 0 2006.285.07:50:38.79#ibcon#about to read 4, iclass 19, count 0 2006.285.07:50:38.79#ibcon#read 4, iclass 19, count 0 2006.285.07:50:38.79#ibcon#about to read 5, iclass 19, count 0 2006.285.07:50:38.79#ibcon#read 5, iclass 19, count 0 2006.285.07:50:38.79#ibcon#about to read 6, iclass 19, count 0 2006.285.07:50:38.79#ibcon#read 6, iclass 19, count 0 2006.285.07:50:38.79#ibcon#end of sib2, iclass 19, count 0 2006.285.07:50:38.79#ibcon#*after write, iclass 19, count 0 2006.285.07:50:38.79#ibcon#*before return 0, iclass 19, count 0 2006.285.07:50:38.79#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:50:38.79#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.07:50:38.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:50:38.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:50:38.79$vck44/vblo=6,719.99 2006.285.07:50:38.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.07:50:38.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.07:50:38.79#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:38.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:50:38.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:50:38.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:50:38.79#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:50:38.79#ibcon#first serial, iclass 21, count 0 2006.285.07:50:38.79#ibcon#enter sib2, iclass 21, count 0 2006.285.07:50:38.79#ibcon#flushed, iclass 21, count 0 2006.285.07:50:38.79#ibcon#about to write, iclass 21, count 0 2006.285.07:50:38.79#ibcon#wrote, iclass 21, count 0 2006.285.07:50:38.79#ibcon#about to read 3, iclass 21, count 0 2006.285.07:50:38.81#ibcon#read 3, iclass 21, count 0 2006.285.07:50:38.81#ibcon#about to read 4, iclass 21, count 0 2006.285.07:50:38.81#ibcon#read 4, iclass 21, count 0 2006.285.07:50:38.81#ibcon#about to read 5, iclass 21, count 0 2006.285.07:50:38.81#ibcon#read 5, iclass 21, count 0 2006.285.07:50:38.81#ibcon#about to read 6, iclass 21, count 0 2006.285.07:50:38.81#ibcon#read 6, iclass 21, count 0 2006.285.07:50:38.81#ibcon#end of sib2, iclass 21, count 0 2006.285.07:50:38.81#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:50:38.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:50:38.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:50:38.81#ibcon#*before write, iclass 21, count 0 2006.285.07:50:38.81#ibcon#enter sib2, iclass 21, count 0 2006.285.07:50:38.81#ibcon#flushed, iclass 21, count 0 2006.285.07:50:38.81#ibcon#about to write, iclass 21, count 0 2006.285.07:50:38.81#ibcon#wrote, iclass 21, count 0 2006.285.07:50:38.81#ibcon#about to read 3, iclass 21, count 0 2006.285.07:50:38.85#ibcon#read 3, iclass 21, count 0 2006.285.07:50:38.85#ibcon#about to read 4, iclass 21, count 0 2006.285.07:50:38.85#ibcon#read 4, iclass 21, count 0 2006.285.07:50:38.85#ibcon#about to read 5, iclass 21, count 0 2006.285.07:50:38.85#ibcon#read 5, iclass 21, count 0 2006.285.07:50:38.85#ibcon#about to read 6, iclass 21, count 0 2006.285.07:50:38.85#ibcon#read 6, iclass 21, count 0 2006.285.07:50:38.85#ibcon#end of sib2, iclass 21, count 0 2006.285.07:50:38.85#ibcon#*after write, iclass 21, count 0 2006.285.07:50:38.85#ibcon#*before return 0, iclass 21, count 0 2006.285.07:50:38.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:50:38.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.07:50:38.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:50:38.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:50:38.85$vck44/vb=6,3 2006.285.07:50:38.85#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.07:50:38.85#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.07:50:38.85#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:38.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:50:38.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:50:38.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:50:38.91#ibcon#enter wrdev, iclass 23, count 2 2006.285.07:50:38.91#ibcon#first serial, iclass 23, count 2 2006.285.07:50:38.91#ibcon#enter sib2, iclass 23, count 2 2006.285.07:50:38.91#ibcon#flushed, iclass 23, count 2 2006.285.07:50:38.91#ibcon#about to write, iclass 23, count 2 2006.285.07:50:38.91#ibcon#wrote, iclass 23, count 2 2006.285.07:50:38.91#ibcon#about to read 3, iclass 23, count 2 2006.285.07:50:38.93#ibcon#read 3, iclass 23, count 2 2006.285.07:50:38.93#ibcon#about to read 4, iclass 23, count 2 2006.285.07:50:38.93#ibcon#read 4, iclass 23, count 2 2006.285.07:50:38.93#ibcon#about to read 5, iclass 23, count 2 2006.285.07:50:38.93#ibcon#read 5, iclass 23, count 2 2006.285.07:50:38.93#ibcon#about to read 6, iclass 23, count 2 2006.285.07:50:38.93#ibcon#read 6, iclass 23, count 2 2006.285.07:50:38.93#ibcon#end of sib2, iclass 23, count 2 2006.285.07:50:38.93#ibcon#*mode == 0, iclass 23, count 2 2006.285.07:50:38.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.07:50:38.93#ibcon#[27=AT06-03\r\n] 2006.285.07:50:38.93#ibcon#*before write, iclass 23, count 2 2006.285.07:50:38.93#ibcon#enter sib2, iclass 23, count 2 2006.285.07:50:38.93#ibcon#flushed, iclass 23, count 2 2006.285.07:50:38.93#ibcon#about to write, iclass 23, count 2 2006.285.07:50:38.93#ibcon#wrote, iclass 23, count 2 2006.285.07:50:38.93#ibcon#about to read 3, iclass 23, count 2 2006.285.07:50:38.96#ibcon#read 3, iclass 23, count 2 2006.285.07:50:38.96#ibcon#about to read 4, iclass 23, count 2 2006.285.07:50:38.96#ibcon#read 4, iclass 23, count 2 2006.285.07:50:38.96#ibcon#about to read 5, iclass 23, count 2 2006.285.07:50:38.96#ibcon#read 5, iclass 23, count 2 2006.285.07:50:38.96#ibcon#about to read 6, iclass 23, count 2 2006.285.07:50:38.96#ibcon#read 6, iclass 23, count 2 2006.285.07:50:38.96#ibcon#end of sib2, iclass 23, count 2 2006.285.07:50:38.96#ibcon#*after write, iclass 23, count 2 2006.285.07:50:38.96#ibcon#*before return 0, iclass 23, count 2 2006.285.07:50:38.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:50:38.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.07:50:38.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.07:50:38.96#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:38.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:50:39.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:50:39.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:50:39.08#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:50:39.08#ibcon#first serial, iclass 23, count 0 2006.285.07:50:39.08#ibcon#enter sib2, iclass 23, count 0 2006.285.07:50:39.08#ibcon#flushed, iclass 23, count 0 2006.285.07:50:39.08#ibcon#about to write, iclass 23, count 0 2006.285.07:50:39.08#ibcon#wrote, iclass 23, count 0 2006.285.07:50:39.08#ibcon#about to read 3, iclass 23, count 0 2006.285.07:50:39.10#ibcon#read 3, iclass 23, count 0 2006.285.07:50:39.10#ibcon#about to read 4, iclass 23, count 0 2006.285.07:50:39.10#ibcon#read 4, iclass 23, count 0 2006.285.07:50:39.10#ibcon#about to read 5, iclass 23, count 0 2006.285.07:50:39.10#ibcon#read 5, iclass 23, count 0 2006.285.07:50:39.10#ibcon#about to read 6, iclass 23, count 0 2006.285.07:50:39.10#ibcon#read 6, iclass 23, count 0 2006.285.07:50:39.10#ibcon#end of sib2, iclass 23, count 0 2006.285.07:50:39.10#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:50:39.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:50:39.10#ibcon#[27=USB\r\n] 2006.285.07:50:39.10#ibcon#*before write, iclass 23, count 0 2006.285.07:50:39.10#ibcon#enter sib2, iclass 23, count 0 2006.285.07:50:39.10#ibcon#flushed, iclass 23, count 0 2006.285.07:50:39.10#ibcon#about to write, iclass 23, count 0 2006.285.07:50:39.10#ibcon#wrote, iclass 23, count 0 2006.285.07:50:39.10#ibcon#about to read 3, iclass 23, count 0 2006.285.07:50:39.13#ibcon#read 3, iclass 23, count 0 2006.285.07:50:39.13#ibcon#about to read 4, iclass 23, count 0 2006.285.07:50:39.13#ibcon#read 4, iclass 23, count 0 2006.285.07:50:39.13#ibcon#about to read 5, iclass 23, count 0 2006.285.07:50:39.13#ibcon#read 5, iclass 23, count 0 2006.285.07:50:39.13#ibcon#about to read 6, iclass 23, count 0 2006.285.07:50:39.13#ibcon#read 6, iclass 23, count 0 2006.285.07:50:39.13#ibcon#end of sib2, iclass 23, count 0 2006.285.07:50:39.13#ibcon#*after write, iclass 23, count 0 2006.285.07:50:39.13#ibcon#*before return 0, iclass 23, count 0 2006.285.07:50:39.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:50:39.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.07:50:39.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:50:39.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:50:39.13$vck44/vblo=7,734.99 2006.285.07:50:39.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.07:50:39.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.07:50:39.13#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:39.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:50:39.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:50:39.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:50:39.13#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:50:39.13#ibcon#first serial, iclass 25, count 0 2006.285.07:50:39.13#ibcon#enter sib2, iclass 25, count 0 2006.285.07:50:39.13#ibcon#flushed, iclass 25, count 0 2006.285.07:50:39.13#ibcon#about to write, iclass 25, count 0 2006.285.07:50:39.13#ibcon#wrote, iclass 25, count 0 2006.285.07:50:39.13#ibcon#about to read 3, iclass 25, count 0 2006.285.07:50:39.15#ibcon#read 3, iclass 25, count 0 2006.285.07:50:39.15#ibcon#about to read 4, iclass 25, count 0 2006.285.07:50:39.15#ibcon#read 4, iclass 25, count 0 2006.285.07:50:39.15#ibcon#about to read 5, iclass 25, count 0 2006.285.07:50:39.15#ibcon#read 5, iclass 25, count 0 2006.285.07:50:39.15#ibcon#about to read 6, iclass 25, count 0 2006.285.07:50:39.15#ibcon#read 6, iclass 25, count 0 2006.285.07:50:39.15#ibcon#end of sib2, iclass 25, count 0 2006.285.07:50:39.15#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:50:39.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:50:39.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:50:39.15#ibcon#*before write, iclass 25, count 0 2006.285.07:50:39.15#ibcon#enter sib2, iclass 25, count 0 2006.285.07:50:39.15#ibcon#flushed, iclass 25, count 0 2006.285.07:50:39.15#ibcon#about to write, iclass 25, count 0 2006.285.07:50:39.15#ibcon#wrote, iclass 25, count 0 2006.285.07:50:39.15#ibcon#about to read 3, iclass 25, count 0 2006.285.07:50:39.19#ibcon#read 3, iclass 25, count 0 2006.285.07:50:39.19#ibcon#about to read 4, iclass 25, count 0 2006.285.07:50:39.19#ibcon#read 4, iclass 25, count 0 2006.285.07:50:39.19#ibcon#about to read 5, iclass 25, count 0 2006.285.07:50:39.19#ibcon#read 5, iclass 25, count 0 2006.285.07:50:39.19#ibcon#about to read 6, iclass 25, count 0 2006.285.07:50:39.19#ibcon#read 6, iclass 25, count 0 2006.285.07:50:39.19#ibcon#end of sib2, iclass 25, count 0 2006.285.07:50:39.19#ibcon#*after write, iclass 25, count 0 2006.285.07:50:39.19#ibcon#*before return 0, iclass 25, count 0 2006.285.07:50:39.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:50:39.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.07:50:39.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:50:39.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:50:39.19$vck44/vb=7,4 2006.285.07:50:39.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.07:50:39.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.07:50:39.19#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:39.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:50:39.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:50:39.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:50:39.25#ibcon#enter wrdev, iclass 27, count 2 2006.285.07:50:39.25#ibcon#first serial, iclass 27, count 2 2006.285.07:50:39.25#ibcon#enter sib2, iclass 27, count 2 2006.285.07:50:39.25#ibcon#flushed, iclass 27, count 2 2006.285.07:50:39.25#ibcon#about to write, iclass 27, count 2 2006.285.07:50:39.25#ibcon#wrote, iclass 27, count 2 2006.285.07:50:39.25#ibcon#about to read 3, iclass 27, count 2 2006.285.07:50:39.27#ibcon#read 3, iclass 27, count 2 2006.285.07:50:39.27#ibcon#about to read 4, iclass 27, count 2 2006.285.07:50:39.27#ibcon#read 4, iclass 27, count 2 2006.285.07:50:39.27#ibcon#about to read 5, iclass 27, count 2 2006.285.07:50:39.27#ibcon#read 5, iclass 27, count 2 2006.285.07:50:39.27#ibcon#about to read 6, iclass 27, count 2 2006.285.07:50:39.27#ibcon#read 6, iclass 27, count 2 2006.285.07:50:39.27#ibcon#end of sib2, iclass 27, count 2 2006.285.07:50:39.27#ibcon#*mode == 0, iclass 27, count 2 2006.285.07:50:39.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.07:50:39.27#ibcon#[27=AT07-04\r\n] 2006.285.07:50:39.27#ibcon#*before write, iclass 27, count 2 2006.285.07:50:39.27#ibcon#enter sib2, iclass 27, count 2 2006.285.07:50:39.27#ibcon#flushed, iclass 27, count 2 2006.285.07:50:39.27#ibcon#about to write, iclass 27, count 2 2006.285.07:50:39.27#ibcon#wrote, iclass 27, count 2 2006.285.07:50:39.27#ibcon#about to read 3, iclass 27, count 2 2006.285.07:50:39.30#ibcon#read 3, iclass 27, count 2 2006.285.07:50:39.30#ibcon#about to read 4, iclass 27, count 2 2006.285.07:50:39.30#ibcon#read 4, iclass 27, count 2 2006.285.07:50:39.30#ibcon#about to read 5, iclass 27, count 2 2006.285.07:50:39.30#ibcon#read 5, iclass 27, count 2 2006.285.07:50:39.30#ibcon#about to read 6, iclass 27, count 2 2006.285.07:50:39.30#ibcon#read 6, iclass 27, count 2 2006.285.07:50:39.30#ibcon#end of sib2, iclass 27, count 2 2006.285.07:50:39.30#ibcon#*after write, iclass 27, count 2 2006.285.07:50:39.30#ibcon#*before return 0, iclass 27, count 2 2006.285.07:50:39.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:50:39.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.07:50:39.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.07:50:39.30#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:39.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:50:39.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:50:39.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:50:39.42#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:50:39.42#ibcon#first serial, iclass 27, count 0 2006.285.07:50:39.42#ibcon#enter sib2, iclass 27, count 0 2006.285.07:50:39.42#ibcon#flushed, iclass 27, count 0 2006.285.07:50:39.42#ibcon#about to write, iclass 27, count 0 2006.285.07:50:39.42#ibcon#wrote, iclass 27, count 0 2006.285.07:50:39.42#ibcon#about to read 3, iclass 27, count 0 2006.285.07:50:39.44#ibcon#read 3, iclass 27, count 0 2006.285.07:50:39.44#ibcon#about to read 4, iclass 27, count 0 2006.285.07:50:39.44#ibcon#read 4, iclass 27, count 0 2006.285.07:50:39.44#ibcon#about to read 5, iclass 27, count 0 2006.285.07:50:39.44#ibcon#read 5, iclass 27, count 0 2006.285.07:50:39.44#ibcon#about to read 6, iclass 27, count 0 2006.285.07:50:39.44#ibcon#read 6, iclass 27, count 0 2006.285.07:50:39.44#ibcon#end of sib2, iclass 27, count 0 2006.285.07:50:39.44#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:50:39.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:50:39.44#ibcon#[27=USB\r\n] 2006.285.07:50:39.44#ibcon#*before write, iclass 27, count 0 2006.285.07:50:39.44#ibcon#enter sib2, iclass 27, count 0 2006.285.07:50:39.44#ibcon#flushed, iclass 27, count 0 2006.285.07:50:39.44#ibcon#about to write, iclass 27, count 0 2006.285.07:50:39.44#ibcon#wrote, iclass 27, count 0 2006.285.07:50:39.44#ibcon#about to read 3, iclass 27, count 0 2006.285.07:50:39.47#ibcon#read 3, iclass 27, count 0 2006.285.07:50:39.47#ibcon#about to read 4, iclass 27, count 0 2006.285.07:50:39.47#ibcon#read 4, iclass 27, count 0 2006.285.07:50:39.47#ibcon#about to read 5, iclass 27, count 0 2006.285.07:50:39.47#ibcon#read 5, iclass 27, count 0 2006.285.07:50:39.47#ibcon#about to read 6, iclass 27, count 0 2006.285.07:50:39.47#ibcon#read 6, iclass 27, count 0 2006.285.07:50:39.47#ibcon#end of sib2, iclass 27, count 0 2006.285.07:50:39.47#ibcon#*after write, iclass 27, count 0 2006.285.07:50:39.47#ibcon#*before return 0, iclass 27, count 0 2006.285.07:50:39.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:50:39.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.07:50:39.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:50:39.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:50:39.47$vck44/vblo=8,744.99 2006.285.07:50:39.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.07:50:39.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.07:50:39.47#ibcon#ireg 17 cls_cnt 0 2006.285.07:50:39.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:50:39.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:50:39.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:50:39.47#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:50:39.47#ibcon#first serial, iclass 29, count 0 2006.285.07:50:39.47#ibcon#enter sib2, iclass 29, count 0 2006.285.07:50:39.47#ibcon#flushed, iclass 29, count 0 2006.285.07:50:39.47#ibcon#about to write, iclass 29, count 0 2006.285.07:50:39.47#ibcon#wrote, iclass 29, count 0 2006.285.07:50:39.47#ibcon#about to read 3, iclass 29, count 0 2006.285.07:50:39.49#ibcon#read 3, iclass 29, count 0 2006.285.07:50:39.49#ibcon#about to read 4, iclass 29, count 0 2006.285.07:50:39.49#ibcon#read 4, iclass 29, count 0 2006.285.07:50:39.49#ibcon#about to read 5, iclass 29, count 0 2006.285.07:50:39.49#ibcon#read 5, iclass 29, count 0 2006.285.07:50:39.49#ibcon#about to read 6, iclass 29, count 0 2006.285.07:50:39.49#ibcon#read 6, iclass 29, count 0 2006.285.07:50:39.49#ibcon#end of sib2, iclass 29, count 0 2006.285.07:50:39.49#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:50:39.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:50:39.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:50:39.49#ibcon#*before write, iclass 29, count 0 2006.285.07:50:39.49#ibcon#enter sib2, iclass 29, count 0 2006.285.07:50:39.49#ibcon#flushed, iclass 29, count 0 2006.285.07:50:39.49#ibcon#about to write, iclass 29, count 0 2006.285.07:50:39.49#ibcon#wrote, iclass 29, count 0 2006.285.07:50:39.49#ibcon#about to read 3, iclass 29, count 0 2006.285.07:50:39.53#ibcon#read 3, iclass 29, count 0 2006.285.07:50:39.53#ibcon#about to read 4, iclass 29, count 0 2006.285.07:50:39.53#ibcon#read 4, iclass 29, count 0 2006.285.07:50:39.53#ibcon#about to read 5, iclass 29, count 0 2006.285.07:50:39.53#ibcon#read 5, iclass 29, count 0 2006.285.07:50:39.53#ibcon#about to read 6, iclass 29, count 0 2006.285.07:50:39.53#ibcon#read 6, iclass 29, count 0 2006.285.07:50:39.53#ibcon#end of sib2, iclass 29, count 0 2006.285.07:50:39.53#ibcon#*after write, iclass 29, count 0 2006.285.07:50:39.53#ibcon#*before return 0, iclass 29, count 0 2006.285.07:50:39.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:50:39.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:50:39.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:50:39.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:50:39.53$vck44/vb=8,4 2006.285.07:50:39.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.07:50:39.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.07:50:39.53#ibcon#ireg 11 cls_cnt 2 2006.285.07:50:39.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:50:39.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:50:39.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:50:39.59#ibcon#enter wrdev, iclass 31, count 2 2006.285.07:50:39.59#ibcon#first serial, iclass 31, count 2 2006.285.07:50:39.59#ibcon#enter sib2, iclass 31, count 2 2006.285.07:50:39.59#ibcon#flushed, iclass 31, count 2 2006.285.07:50:39.59#ibcon#about to write, iclass 31, count 2 2006.285.07:50:39.59#ibcon#wrote, iclass 31, count 2 2006.285.07:50:39.59#ibcon#about to read 3, iclass 31, count 2 2006.285.07:50:39.61#ibcon#read 3, iclass 31, count 2 2006.285.07:50:39.61#ibcon#about to read 4, iclass 31, count 2 2006.285.07:50:39.61#ibcon#read 4, iclass 31, count 2 2006.285.07:50:39.61#ibcon#about to read 5, iclass 31, count 2 2006.285.07:50:39.61#ibcon#read 5, iclass 31, count 2 2006.285.07:50:39.61#ibcon#about to read 6, iclass 31, count 2 2006.285.07:50:39.61#ibcon#read 6, iclass 31, count 2 2006.285.07:50:39.61#ibcon#end of sib2, iclass 31, count 2 2006.285.07:50:39.61#ibcon#*mode == 0, iclass 31, count 2 2006.285.07:50:39.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.07:50:39.61#ibcon#[27=AT08-04\r\n] 2006.285.07:50:39.61#ibcon#*before write, iclass 31, count 2 2006.285.07:50:39.61#ibcon#enter sib2, iclass 31, count 2 2006.285.07:50:39.61#ibcon#flushed, iclass 31, count 2 2006.285.07:50:39.61#ibcon#about to write, iclass 31, count 2 2006.285.07:50:39.61#ibcon#wrote, iclass 31, count 2 2006.285.07:50:39.61#ibcon#about to read 3, iclass 31, count 2 2006.285.07:50:39.64#ibcon#read 3, iclass 31, count 2 2006.285.07:50:39.64#ibcon#about to read 4, iclass 31, count 2 2006.285.07:50:39.64#ibcon#read 4, iclass 31, count 2 2006.285.07:50:39.64#ibcon#about to read 5, iclass 31, count 2 2006.285.07:50:39.64#ibcon#read 5, iclass 31, count 2 2006.285.07:50:39.64#ibcon#about to read 6, iclass 31, count 2 2006.285.07:50:39.64#ibcon#read 6, iclass 31, count 2 2006.285.07:50:39.64#ibcon#end of sib2, iclass 31, count 2 2006.285.07:50:39.64#ibcon#*after write, iclass 31, count 2 2006.285.07:50:39.64#ibcon#*before return 0, iclass 31, count 2 2006.285.07:50:39.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:50:39.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.07:50:39.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.07:50:39.64#ibcon#ireg 7 cls_cnt 0 2006.285.07:50:39.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:50:39.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:50:39.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:50:39.76#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:50:39.76#ibcon#first serial, iclass 31, count 0 2006.285.07:50:39.76#ibcon#enter sib2, iclass 31, count 0 2006.285.07:50:39.76#ibcon#flushed, iclass 31, count 0 2006.285.07:50:39.76#ibcon#about to write, iclass 31, count 0 2006.285.07:50:39.76#ibcon#wrote, iclass 31, count 0 2006.285.07:50:39.76#ibcon#about to read 3, iclass 31, count 0 2006.285.07:50:39.78#ibcon#read 3, iclass 31, count 0 2006.285.07:50:39.78#ibcon#about to read 4, iclass 31, count 0 2006.285.07:50:39.78#ibcon#read 4, iclass 31, count 0 2006.285.07:50:39.78#ibcon#about to read 5, iclass 31, count 0 2006.285.07:50:39.78#ibcon#read 5, iclass 31, count 0 2006.285.07:50:39.78#ibcon#about to read 6, iclass 31, count 0 2006.285.07:50:39.78#ibcon#read 6, iclass 31, count 0 2006.285.07:50:39.78#ibcon#end of sib2, iclass 31, count 0 2006.285.07:50:39.78#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:50:39.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:50:39.78#ibcon#[27=USB\r\n] 2006.285.07:50:39.78#ibcon#*before write, iclass 31, count 0 2006.285.07:50:39.78#ibcon#enter sib2, iclass 31, count 0 2006.285.07:50:39.78#ibcon#flushed, iclass 31, count 0 2006.285.07:50:39.78#ibcon#about to write, iclass 31, count 0 2006.285.07:50:39.78#ibcon#wrote, iclass 31, count 0 2006.285.07:50:39.78#ibcon#about to read 3, iclass 31, count 0 2006.285.07:50:39.81#ibcon#read 3, iclass 31, count 0 2006.285.07:50:39.81#ibcon#about to read 4, iclass 31, count 0 2006.285.07:50:39.81#ibcon#read 4, iclass 31, count 0 2006.285.07:50:39.81#ibcon#about to read 5, iclass 31, count 0 2006.285.07:50:39.81#ibcon#read 5, iclass 31, count 0 2006.285.07:50:39.81#ibcon#about to read 6, iclass 31, count 0 2006.285.07:50:39.81#ibcon#read 6, iclass 31, count 0 2006.285.07:50:39.81#ibcon#end of sib2, iclass 31, count 0 2006.285.07:50:39.81#ibcon#*after write, iclass 31, count 0 2006.285.07:50:39.81#ibcon#*before return 0, iclass 31, count 0 2006.285.07:50:39.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:50:39.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.07:50:39.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:50:39.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:50:39.81$vck44/vabw=wide 2006.285.07:50:39.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.07:50:39.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.07:50:39.81#ibcon#ireg 8 cls_cnt 0 2006.285.07:50:39.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:50:39.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:50:39.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:50:39.81#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:50:39.81#ibcon#first serial, iclass 33, count 0 2006.285.07:50:39.81#ibcon#enter sib2, iclass 33, count 0 2006.285.07:50:39.81#ibcon#flushed, iclass 33, count 0 2006.285.07:50:39.81#ibcon#about to write, iclass 33, count 0 2006.285.07:50:39.81#ibcon#wrote, iclass 33, count 0 2006.285.07:50:39.81#ibcon#about to read 3, iclass 33, count 0 2006.285.07:50:39.83#ibcon#read 3, iclass 33, count 0 2006.285.07:50:39.83#ibcon#about to read 4, iclass 33, count 0 2006.285.07:50:39.83#ibcon#read 4, iclass 33, count 0 2006.285.07:50:39.83#ibcon#about to read 5, iclass 33, count 0 2006.285.07:50:39.83#ibcon#read 5, iclass 33, count 0 2006.285.07:50:39.83#ibcon#about to read 6, iclass 33, count 0 2006.285.07:50:39.83#ibcon#read 6, iclass 33, count 0 2006.285.07:50:39.83#ibcon#end of sib2, iclass 33, count 0 2006.285.07:50:39.83#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:50:39.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:50:39.83#ibcon#[25=BW32\r\n] 2006.285.07:50:39.83#ibcon#*before write, iclass 33, count 0 2006.285.07:50:39.83#ibcon#enter sib2, iclass 33, count 0 2006.285.07:50:39.83#ibcon#flushed, iclass 33, count 0 2006.285.07:50:39.83#ibcon#about to write, iclass 33, count 0 2006.285.07:50:39.83#ibcon#wrote, iclass 33, count 0 2006.285.07:50:39.83#ibcon#about to read 3, iclass 33, count 0 2006.285.07:50:39.86#ibcon#read 3, iclass 33, count 0 2006.285.07:50:39.86#ibcon#about to read 4, iclass 33, count 0 2006.285.07:50:39.86#ibcon#read 4, iclass 33, count 0 2006.285.07:50:39.86#ibcon#about to read 5, iclass 33, count 0 2006.285.07:50:39.86#ibcon#read 5, iclass 33, count 0 2006.285.07:50:39.86#ibcon#about to read 6, iclass 33, count 0 2006.285.07:50:39.86#ibcon#read 6, iclass 33, count 0 2006.285.07:50:39.86#ibcon#end of sib2, iclass 33, count 0 2006.285.07:50:39.86#ibcon#*after write, iclass 33, count 0 2006.285.07:50:39.86#ibcon#*before return 0, iclass 33, count 0 2006.285.07:50:39.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:50:39.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.07:50:39.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:50:39.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:50:39.86$vck44/vbbw=wide 2006.285.07:50:39.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.07:50:39.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.07:50:39.86#ibcon#ireg 8 cls_cnt 0 2006.285.07:50:39.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:50:39.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:50:39.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:50:39.93#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:50:39.93#ibcon#first serial, iclass 35, count 0 2006.285.07:50:39.93#ibcon#enter sib2, iclass 35, count 0 2006.285.07:50:39.93#ibcon#flushed, iclass 35, count 0 2006.285.07:50:39.93#ibcon#about to write, iclass 35, count 0 2006.285.07:50:39.93#ibcon#wrote, iclass 35, count 0 2006.285.07:50:39.93#ibcon#about to read 3, iclass 35, count 0 2006.285.07:50:39.95#ibcon#read 3, iclass 35, count 0 2006.285.07:50:39.95#ibcon#about to read 4, iclass 35, count 0 2006.285.07:50:39.95#ibcon#read 4, iclass 35, count 0 2006.285.07:50:39.95#ibcon#about to read 5, iclass 35, count 0 2006.285.07:50:39.95#ibcon#read 5, iclass 35, count 0 2006.285.07:50:39.95#ibcon#about to read 6, iclass 35, count 0 2006.285.07:50:39.95#ibcon#read 6, iclass 35, count 0 2006.285.07:50:39.95#ibcon#end of sib2, iclass 35, count 0 2006.285.07:50:39.95#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:50:39.95#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:50:39.95#ibcon#[27=BW32\r\n] 2006.285.07:50:39.95#ibcon#*before write, iclass 35, count 0 2006.285.07:50:39.95#ibcon#enter sib2, iclass 35, count 0 2006.285.07:50:39.95#ibcon#flushed, iclass 35, count 0 2006.285.07:50:39.95#ibcon#about to write, iclass 35, count 0 2006.285.07:50:39.95#ibcon#wrote, iclass 35, count 0 2006.285.07:50:39.95#ibcon#about to read 3, iclass 35, count 0 2006.285.07:50:39.98#ibcon#read 3, iclass 35, count 0 2006.285.07:50:39.98#ibcon#about to read 4, iclass 35, count 0 2006.285.07:50:39.98#ibcon#read 4, iclass 35, count 0 2006.285.07:50:39.98#ibcon#about to read 5, iclass 35, count 0 2006.285.07:50:39.98#ibcon#read 5, iclass 35, count 0 2006.285.07:50:39.98#ibcon#about to read 6, iclass 35, count 0 2006.285.07:50:39.98#ibcon#read 6, iclass 35, count 0 2006.285.07:50:39.98#ibcon#end of sib2, iclass 35, count 0 2006.285.07:50:39.98#ibcon#*after write, iclass 35, count 0 2006.285.07:50:39.98#ibcon#*before return 0, iclass 35, count 0 2006.285.07:50:39.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:50:39.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:50:39.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:50:39.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:50:39.98$setupk4/ifdk4 2006.285.07:50:39.98$ifdk4/lo= 2006.285.07:50:39.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:50:39.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:50:39.98$ifdk4/patch= 2006.285.07:50:39.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:50:39.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:50:39.98$setupk4/!*+20s 2006.285.07:50:41.37#abcon#<5=/04 2.3 4.4 23.23 781014.5\r\n> 2006.285.07:50:41.39#abcon#{5=INTERFACE CLEAR} 2006.285.07:50:41.45#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:50:51.54#abcon#<5=/04 2.3 4.4 23.22 781014.4\r\n> 2006.285.07:50:51.56#abcon#{5=INTERFACE CLEAR} 2006.285.07:50:51.62#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:50:54.49$setupk4/"tpicd 2006.285.07:50:54.49$setupk4/echo=off 2006.285.07:50:54.49$setupk4/xlog=off 2006.285.07:50:54.49:!2006.285.07:53:25 2006.285.07:50:58.14#trakl#Source acquired 2006.285.07:51:00.14#flagr#flagr/antenna,acquired 2006.285.07:53:25.00:preob 2006.285.07:53:25.14/onsource/TRACKING 2006.285.07:53:25.14:!2006.285.07:53:35 2006.285.07:53:35.00:"tape 2006.285.07:53:35.00:"st=record 2006.285.07:53:35.00:data_valid=on 2006.285.07:53:35.00:midob 2006.285.07:53:36.14/onsource/TRACKING 2006.285.07:53:36.14/wx/23.16,1014.5,78 2006.285.07:53:36.31/cable/+6.4737E-03 2006.285.07:53:37.40/va/01,07,usb,yes,32,35 2006.285.07:53:37.40/va/02,06,usb,yes,32,32 2006.285.07:53:37.40/va/03,07,usb,yes,31,33 2006.285.07:53:37.40/va/04,06,usb,yes,33,34 2006.285.07:53:37.40/va/05,03,usb,yes,32,33 2006.285.07:53:37.40/va/06,04,usb,yes,29,29 2006.285.07:53:37.40/va/07,04,usb,yes,30,30 2006.285.07:53:37.40/va/08,03,usb,yes,30,37 2006.285.07:53:37.63/valo/01,524.99,yes,locked 2006.285.07:53:37.63/valo/02,534.99,yes,locked 2006.285.07:53:37.63/valo/03,564.99,yes,locked 2006.285.07:53:37.63/valo/04,624.99,yes,locked 2006.285.07:53:37.63/valo/05,734.99,yes,locked 2006.285.07:53:37.63/valo/06,814.99,yes,locked 2006.285.07:53:37.63/valo/07,864.99,yes,locked 2006.285.07:53:37.63/valo/08,884.99,yes,locked 2006.285.07:53:38.72/vb/01,04,usb,yes,30,28 2006.285.07:53:38.72/vb/02,05,usb,yes,28,28 2006.285.07:53:38.72/vb/03,04,usb,yes,29,32 2006.285.07:53:38.72/vb/04,05,usb,yes,30,29 2006.285.07:53:38.72/vb/05,04,usb,yes,26,29 2006.285.07:53:38.72/vb/06,03,usb,yes,38,34 2006.285.07:53:38.72/vb/07,04,usb,yes,31,31 2006.285.07:53:38.72/vb/08,04,usb,yes,28,31 2006.285.07:53:38.95/vblo/01,629.99,yes,locked 2006.285.07:53:38.95/vblo/02,634.99,yes,locked 2006.285.07:53:38.95/vblo/03,649.99,yes,locked 2006.285.07:53:38.95/vblo/04,679.99,yes,locked 2006.285.07:53:38.95/vblo/05,709.99,yes,locked 2006.285.07:53:38.95/vblo/06,719.99,yes,locked 2006.285.07:53:38.95/vblo/07,734.99,yes,locked 2006.285.07:53:38.95/vblo/08,744.99,yes,locked 2006.285.07:53:39.10/vabw/8 2006.285.07:53:39.25/vbbw/8 2006.285.07:53:39.34/xfe/off,on,12.2 2006.285.07:53:39.71/ifatt/23,28,28,28 2006.285.07:53:40.07/fmout-gps/S +2.80E-07 2006.285.07:53:40.09:!2006.285.07:54:55 2006.285.07:54:55.00:data_valid=off 2006.285.07:54:55.00:"et 2006.285.07:54:55.00:!+3s 2006.285.07:54:58.01:"tape 2006.285.07:54:58.01:postob 2006.285.07:54:58.23/cable/+6.4716E-03 2006.285.07:54:58.23/wx/23.14,1014.5,78 2006.285.07:54:59.07/fmout-gps/S +2.80E-07 2006.285.07:54:59.07:scan_name=285-0759,jd0610,160 2006.285.07:54:59.07:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.285.07:55:00.14#flagr#flagr/antenna,new-source 2006.285.07:55:00.14:checkk5 2006.285.07:55:00.58/chk_autoobs//k5ts1/ autoobs is running! 2006.285.07:55:00.97/chk_autoobs//k5ts2/ autoobs is running! 2006.285.07:55:01.37/chk_autoobs//k5ts3/ autoobs is running! 2006.285.07:55:01.79/chk_autoobs//k5ts4/ autoobs is running! 2006.285.07:55:02.15/chk_obsdata//k5ts1/T2850753??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.07:55:02.55/chk_obsdata//k5ts2/T2850753??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.07:55:02.90/chk_obsdata//k5ts3/T2850753??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.07:55:03.29/chk_obsdata//k5ts4/T2850753??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.07:55:04.10/k5log//k5ts1_log_newline 2006.285.07:55:05.15/k5log//k5ts2_log_newline 2006.285.07:55:05.90/k5log//k5ts3_log_newline 2006.285.07:55:06.71/k5log//k5ts4_log_newline 2006.285.07:55:06.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.07:55:06.73:setupk4=1 2006.285.07:55:06.73$setupk4/echo=on 2006.285.07:55:06.73$setupk4/pcalon 2006.285.07:55:06.73$pcalon/"no phase cal control is implemented here 2006.285.07:55:06.73$setupk4/"tpicd=stop 2006.285.07:55:06.73$setupk4/"rec=synch_on 2006.285.07:55:06.73$setupk4/"rec_mode=128 2006.285.07:55:06.73$setupk4/!* 2006.285.07:55:06.74$setupk4/recpk4 2006.285.07:55:06.74$recpk4/recpatch= 2006.285.07:55:06.74$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.07:55:06.74$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.07:55:06.74$setupk4/vck44 2006.285.07:55:06.74$vck44/valo=1,524.99 2006.285.07:55:06.74#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.07:55:06.74#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.07:55:06.74#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:06.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:55:06.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:55:06.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:55:06.74#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:55:06.74#ibcon#first serial, iclass 31, count 0 2006.285.07:55:06.74#ibcon#enter sib2, iclass 31, count 0 2006.285.07:55:06.74#ibcon#flushed, iclass 31, count 0 2006.285.07:55:06.74#ibcon#about to write, iclass 31, count 0 2006.285.07:55:06.74#ibcon#wrote, iclass 31, count 0 2006.285.07:55:06.74#ibcon#about to read 3, iclass 31, count 0 2006.285.07:55:06.76#ibcon#read 3, iclass 31, count 0 2006.285.07:55:06.76#ibcon#about to read 4, iclass 31, count 0 2006.285.07:55:06.76#ibcon#read 4, iclass 31, count 0 2006.285.07:55:06.76#ibcon#about to read 5, iclass 31, count 0 2006.285.07:55:06.76#ibcon#read 5, iclass 31, count 0 2006.285.07:55:06.76#ibcon#about to read 6, iclass 31, count 0 2006.285.07:55:06.76#ibcon#read 6, iclass 31, count 0 2006.285.07:55:06.76#ibcon#end of sib2, iclass 31, count 0 2006.285.07:55:06.76#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:55:06.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:55:06.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.07:55:06.76#ibcon#*before write, iclass 31, count 0 2006.285.07:55:06.76#ibcon#enter sib2, iclass 31, count 0 2006.285.07:55:06.76#ibcon#flushed, iclass 31, count 0 2006.285.07:55:06.76#ibcon#about to write, iclass 31, count 0 2006.285.07:55:06.76#ibcon#wrote, iclass 31, count 0 2006.285.07:55:06.76#ibcon#about to read 3, iclass 31, count 0 2006.285.07:55:06.81#ibcon#read 3, iclass 31, count 0 2006.285.07:55:06.81#ibcon#about to read 4, iclass 31, count 0 2006.285.07:55:06.81#ibcon#read 4, iclass 31, count 0 2006.285.07:55:06.81#ibcon#about to read 5, iclass 31, count 0 2006.285.07:55:06.81#ibcon#read 5, iclass 31, count 0 2006.285.07:55:06.81#ibcon#about to read 6, iclass 31, count 0 2006.285.07:55:06.81#ibcon#read 6, iclass 31, count 0 2006.285.07:55:06.81#ibcon#end of sib2, iclass 31, count 0 2006.285.07:55:06.81#ibcon#*after write, iclass 31, count 0 2006.285.07:55:06.81#ibcon#*before return 0, iclass 31, count 0 2006.285.07:55:06.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:55:06.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:55:06.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:55:06.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:55:06.81$vck44/va=1,7 2006.285.07:55:06.81#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.07:55:06.81#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.07:55:06.81#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:06.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:55:06.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:55:06.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:55:06.81#ibcon#enter wrdev, iclass 33, count 2 2006.285.07:55:06.81#ibcon#first serial, iclass 33, count 2 2006.285.07:55:06.81#ibcon#enter sib2, iclass 33, count 2 2006.285.07:55:06.81#ibcon#flushed, iclass 33, count 2 2006.285.07:55:06.81#ibcon#about to write, iclass 33, count 2 2006.285.07:55:06.81#ibcon#wrote, iclass 33, count 2 2006.285.07:55:06.81#ibcon#about to read 3, iclass 33, count 2 2006.285.07:55:06.83#ibcon#read 3, iclass 33, count 2 2006.285.07:55:06.83#ibcon#about to read 4, iclass 33, count 2 2006.285.07:55:06.83#ibcon#read 4, iclass 33, count 2 2006.285.07:55:06.83#ibcon#about to read 5, iclass 33, count 2 2006.285.07:55:06.83#ibcon#read 5, iclass 33, count 2 2006.285.07:55:06.83#ibcon#about to read 6, iclass 33, count 2 2006.285.07:55:06.83#ibcon#read 6, iclass 33, count 2 2006.285.07:55:06.83#ibcon#end of sib2, iclass 33, count 2 2006.285.07:55:06.83#ibcon#*mode == 0, iclass 33, count 2 2006.285.07:55:06.83#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.07:55:06.83#ibcon#[25=AT01-07\r\n] 2006.285.07:55:06.83#ibcon#*before write, iclass 33, count 2 2006.285.07:55:06.83#ibcon#enter sib2, iclass 33, count 2 2006.285.07:55:06.83#ibcon#flushed, iclass 33, count 2 2006.285.07:55:06.83#ibcon#about to write, iclass 33, count 2 2006.285.07:55:06.83#ibcon#wrote, iclass 33, count 2 2006.285.07:55:06.83#ibcon#about to read 3, iclass 33, count 2 2006.285.07:55:06.86#ibcon#read 3, iclass 33, count 2 2006.285.07:55:06.86#ibcon#about to read 4, iclass 33, count 2 2006.285.07:55:06.86#ibcon#read 4, iclass 33, count 2 2006.285.07:55:06.86#ibcon#about to read 5, iclass 33, count 2 2006.285.07:55:06.86#ibcon#read 5, iclass 33, count 2 2006.285.07:55:06.86#ibcon#about to read 6, iclass 33, count 2 2006.285.07:55:06.86#ibcon#read 6, iclass 33, count 2 2006.285.07:55:06.86#ibcon#end of sib2, iclass 33, count 2 2006.285.07:55:06.86#ibcon#*after write, iclass 33, count 2 2006.285.07:55:06.86#ibcon#*before return 0, iclass 33, count 2 2006.285.07:55:06.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:55:06.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:55:06.86#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.07:55:06.86#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:06.86#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:55:06.98#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:55:06.98#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:55:06.98#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:55:06.98#ibcon#first serial, iclass 33, count 0 2006.285.07:55:06.98#ibcon#enter sib2, iclass 33, count 0 2006.285.07:55:06.98#ibcon#flushed, iclass 33, count 0 2006.285.07:55:06.98#ibcon#about to write, iclass 33, count 0 2006.285.07:55:06.98#ibcon#wrote, iclass 33, count 0 2006.285.07:55:06.98#ibcon#about to read 3, iclass 33, count 0 2006.285.07:55:07.00#ibcon#read 3, iclass 33, count 0 2006.285.07:55:07.00#ibcon#about to read 4, iclass 33, count 0 2006.285.07:55:07.00#ibcon#read 4, iclass 33, count 0 2006.285.07:55:07.00#ibcon#about to read 5, iclass 33, count 0 2006.285.07:55:07.00#ibcon#read 5, iclass 33, count 0 2006.285.07:55:07.00#ibcon#about to read 6, iclass 33, count 0 2006.285.07:55:07.00#ibcon#read 6, iclass 33, count 0 2006.285.07:55:07.00#ibcon#end of sib2, iclass 33, count 0 2006.285.07:55:07.00#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:55:07.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:55:07.00#ibcon#[25=USB\r\n] 2006.285.07:55:07.00#ibcon#*before write, iclass 33, count 0 2006.285.07:55:07.00#ibcon#enter sib2, iclass 33, count 0 2006.285.07:55:07.00#ibcon#flushed, iclass 33, count 0 2006.285.07:55:07.00#ibcon#about to write, iclass 33, count 0 2006.285.07:55:07.00#ibcon#wrote, iclass 33, count 0 2006.285.07:55:07.00#ibcon#about to read 3, iclass 33, count 0 2006.285.07:55:07.03#ibcon#read 3, iclass 33, count 0 2006.285.07:55:07.03#ibcon#about to read 4, iclass 33, count 0 2006.285.07:55:07.03#ibcon#read 4, iclass 33, count 0 2006.285.07:55:07.03#ibcon#about to read 5, iclass 33, count 0 2006.285.07:55:07.03#ibcon#read 5, iclass 33, count 0 2006.285.07:55:07.03#ibcon#about to read 6, iclass 33, count 0 2006.285.07:55:07.03#ibcon#read 6, iclass 33, count 0 2006.285.07:55:07.03#ibcon#end of sib2, iclass 33, count 0 2006.285.07:55:07.03#ibcon#*after write, iclass 33, count 0 2006.285.07:55:07.03#ibcon#*before return 0, iclass 33, count 0 2006.285.07:55:07.03#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:55:07.03#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:55:07.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:55:07.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:55:07.03$vck44/valo=2,534.99 2006.285.07:55:07.03#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.07:55:07.03#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.07:55:07.03#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:07.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:55:07.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:55:07.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:55:07.03#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:55:07.03#ibcon#first serial, iclass 35, count 0 2006.285.07:55:07.03#ibcon#enter sib2, iclass 35, count 0 2006.285.07:55:07.03#ibcon#flushed, iclass 35, count 0 2006.285.07:55:07.03#ibcon#about to write, iclass 35, count 0 2006.285.07:55:07.03#ibcon#wrote, iclass 35, count 0 2006.285.07:55:07.03#ibcon#about to read 3, iclass 35, count 0 2006.285.07:55:07.05#ibcon#read 3, iclass 35, count 0 2006.285.07:55:07.05#ibcon#about to read 4, iclass 35, count 0 2006.285.07:55:07.05#ibcon#read 4, iclass 35, count 0 2006.285.07:55:07.05#ibcon#about to read 5, iclass 35, count 0 2006.285.07:55:07.05#ibcon#read 5, iclass 35, count 0 2006.285.07:55:07.05#ibcon#about to read 6, iclass 35, count 0 2006.285.07:55:07.05#ibcon#read 6, iclass 35, count 0 2006.285.07:55:07.05#ibcon#end of sib2, iclass 35, count 0 2006.285.07:55:07.05#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:55:07.05#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:55:07.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.07:55:07.05#ibcon#*before write, iclass 35, count 0 2006.285.07:55:07.05#ibcon#enter sib2, iclass 35, count 0 2006.285.07:55:07.05#ibcon#flushed, iclass 35, count 0 2006.285.07:55:07.05#ibcon#about to write, iclass 35, count 0 2006.285.07:55:07.05#ibcon#wrote, iclass 35, count 0 2006.285.07:55:07.05#ibcon#about to read 3, iclass 35, count 0 2006.285.07:55:07.09#ibcon#read 3, iclass 35, count 0 2006.285.07:55:07.09#ibcon#about to read 4, iclass 35, count 0 2006.285.07:55:07.09#ibcon#read 4, iclass 35, count 0 2006.285.07:55:07.09#ibcon#about to read 5, iclass 35, count 0 2006.285.07:55:07.09#ibcon#read 5, iclass 35, count 0 2006.285.07:55:07.09#ibcon#about to read 6, iclass 35, count 0 2006.285.07:55:07.09#ibcon#read 6, iclass 35, count 0 2006.285.07:55:07.09#ibcon#end of sib2, iclass 35, count 0 2006.285.07:55:07.09#ibcon#*after write, iclass 35, count 0 2006.285.07:55:07.09#ibcon#*before return 0, iclass 35, count 0 2006.285.07:55:07.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:55:07.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:55:07.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:55:07.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:55:07.09$vck44/va=2,6 2006.285.07:55:07.09#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.07:55:07.09#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.07:55:07.09#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:07.09#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:55:07.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:55:07.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:55:07.15#ibcon#enter wrdev, iclass 37, count 2 2006.285.07:55:07.15#ibcon#first serial, iclass 37, count 2 2006.285.07:55:07.15#ibcon#enter sib2, iclass 37, count 2 2006.285.07:55:07.15#ibcon#flushed, iclass 37, count 2 2006.285.07:55:07.15#ibcon#about to write, iclass 37, count 2 2006.285.07:55:07.15#ibcon#wrote, iclass 37, count 2 2006.285.07:55:07.15#ibcon#about to read 3, iclass 37, count 2 2006.285.07:55:07.17#ibcon#read 3, iclass 37, count 2 2006.285.07:55:07.17#ibcon#about to read 4, iclass 37, count 2 2006.285.07:55:07.17#ibcon#read 4, iclass 37, count 2 2006.285.07:55:07.17#ibcon#about to read 5, iclass 37, count 2 2006.285.07:55:07.17#ibcon#read 5, iclass 37, count 2 2006.285.07:55:07.17#ibcon#about to read 6, iclass 37, count 2 2006.285.07:55:07.17#ibcon#read 6, iclass 37, count 2 2006.285.07:55:07.17#ibcon#end of sib2, iclass 37, count 2 2006.285.07:55:07.17#ibcon#*mode == 0, iclass 37, count 2 2006.285.07:55:07.17#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.07:55:07.17#ibcon#[25=AT02-06\r\n] 2006.285.07:55:07.17#ibcon#*before write, iclass 37, count 2 2006.285.07:55:07.17#ibcon#enter sib2, iclass 37, count 2 2006.285.07:55:07.17#ibcon#flushed, iclass 37, count 2 2006.285.07:55:07.17#ibcon#about to write, iclass 37, count 2 2006.285.07:55:07.17#ibcon#wrote, iclass 37, count 2 2006.285.07:55:07.17#ibcon#about to read 3, iclass 37, count 2 2006.285.07:55:07.20#ibcon#read 3, iclass 37, count 2 2006.285.07:55:07.20#ibcon#about to read 4, iclass 37, count 2 2006.285.07:55:07.20#ibcon#read 4, iclass 37, count 2 2006.285.07:55:07.20#ibcon#about to read 5, iclass 37, count 2 2006.285.07:55:07.20#ibcon#read 5, iclass 37, count 2 2006.285.07:55:07.20#ibcon#about to read 6, iclass 37, count 2 2006.285.07:55:07.20#ibcon#read 6, iclass 37, count 2 2006.285.07:55:07.20#ibcon#end of sib2, iclass 37, count 2 2006.285.07:55:07.20#ibcon#*after write, iclass 37, count 2 2006.285.07:55:07.20#ibcon#*before return 0, iclass 37, count 2 2006.285.07:55:07.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:55:07.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:55:07.20#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.07:55:07.20#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:07.20#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:55:07.32#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:55:07.32#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:55:07.32#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:55:07.32#ibcon#first serial, iclass 37, count 0 2006.285.07:55:07.32#ibcon#enter sib2, iclass 37, count 0 2006.285.07:55:07.32#ibcon#flushed, iclass 37, count 0 2006.285.07:55:07.32#ibcon#about to write, iclass 37, count 0 2006.285.07:55:07.32#ibcon#wrote, iclass 37, count 0 2006.285.07:55:07.32#ibcon#about to read 3, iclass 37, count 0 2006.285.07:55:07.34#ibcon#read 3, iclass 37, count 0 2006.285.07:55:07.34#ibcon#about to read 4, iclass 37, count 0 2006.285.07:55:07.34#ibcon#read 4, iclass 37, count 0 2006.285.07:55:07.34#ibcon#about to read 5, iclass 37, count 0 2006.285.07:55:07.34#ibcon#read 5, iclass 37, count 0 2006.285.07:55:07.34#ibcon#about to read 6, iclass 37, count 0 2006.285.07:55:07.34#ibcon#read 6, iclass 37, count 0 2006.285.07:55:07.34#ibcon#end of sib2, iclass 37, count 0 2006.285.07:55:07.34#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:55:07.34#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:55:07.34#ibcon#[25=USB\r\n] 2006.285.07:55:07.34#ibcon#*before write, iclass 37, count 0 2006.285.07:55:07.34#ibcon#enter sib2, iclass 37, count 0 2006.285.07:55:07.34#ibcon#flushed, iclass 37, count 0 2006.285.07:55:07.34#ibcon#about to write, iclass 37, count 0 2006.285.07:55:07.34#ibcon#wrote, iclass 37, count 0 2006.285.07:55:07.34#ibcon#about to read 3, iclass 37, count 0 2006.285.07:55:07.37#ibcon#read 3, iclass 37, count 0 2006.285.07:55:07.37#ibcon#about to read 4, iclass 37, count 0 2006.285.07:55:07.37#ibcon#read 4, iclass 37, count 0 2006.285.07:55:07.37#ibcon#about to read 5, iclass 37, count 0 2006.285.07:55:07.37#ibcon#read 5, iclass 37, count 0 2006.285.07:55:07.37#ibcon#about to read 6, iclass 37, count 0 2006.285.07:55:07.37#ibcon#read 6, iclass 37, count 0 2006.285.07:55:07.37#ibcon#end of sib2, iclass 37, count 0 2006.285.07:55:07.37#ibcon#*after write, iclass 37, count 0 2006.285.07:55:07.37#ibcon#*before return 0, iclass 37, count 0 2006.285.07:55:07.37#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:55:07.37#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:55:07.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:55:07.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:55:07.37$vck44/valo=3,564.99 2006.285.07:55:07.37#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.07:55:07.37#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.07:55:07.37#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:07.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:55:07.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:55:07.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:55:07.37#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:55:07.37#ibcon#first serial, iclass 39, count 0 2006.285.07:55:07.37#ibcon#enter sib2, iclass 39, count 0 2006.285.07:55:07.37#ibcon#flushed, iclass 39, count 0 2006.285.07:55:07.37#ibcon#about to write, iclass 39, count 0 2006.285.07:55:07.37#ibcon#wrote, iclass 39, count 0 2006.285.07:55:07.37#ibcon#about to read 3, iclass 39, count 0 2006.285.07:55:07.39#ibcon#read 3, iclass 39, count 0 2006.285.07:55:07.39#ibcon#about to read 4, iclass 39, count 0 2006.285.07:55:07.39#ibcon#read 4, iclass 39, count 0 2006.285.07:55:07.39#ibcon#about to read 5, iclass 39, count 0 2006.285.07:55:07.39#ibcon#read 5, iclass 39, count 0 2006.285.07:55:07.39#ibcon#about to read 6, iclass 39, count 0 2006.285.07:55:07.39#ibcon#read 6, iclass 39, count 0 2006.285.07:55:07.39#ibcon#end of sib2, iclass 39, count 0 2006.285.07:55:07.39#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:55:07.39#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:55:07.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.07:55:07.39#ibcon#*before write, iclass 39, count 0 2006.285.07:55:07.39#ibcon#enter sib2, iclass 39, count 0 2006.285.07:55:07.39#ibcon#flushed, iclass 39, count 0 2006.285.07:55:07.39#ibcon#about to write, iclass 39, count 0 2006.285.07:55:07.39#ibcon#wrote, iclass 39, count 0 2006.285.07:55:07.39#ibcon#about to read 3, iclass 39, count 0 2006.285.07:55:07.43#ibcon#read 3, iclass 39, count 0 2006.285.07:55:07.43#ibcon#about to read 4, iclass 39, count 0 2006.285.07:55:07.43#ibcon#read 4, iclass 39, count 0 2006.285.07:55:07.43#ibcon#about to read 5, iclass 39, count 0 2006.285.07:55:07.43#ibcon#read 5, iclass 39, count 0 2006.285.07:55:07.43#ibcon#about to read 6, iclass 39, count 0 2006.285.07:55:07.43#ibcon#read 6, iclass 39, count 0 2006.285.07:55:07.43#ibcon#end of sib2, iclass 39, count 0 2006.285.07:55:07.43#ibcon#*after write, iclass 39, count 0 2006.285.07:55:07.43#ibcon#*before return 0, iclass 39, count 0 2006.285.07:55:07.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:55:07.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:55:07.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:55:07.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:55:07.43$vck44/va=3,7 2006.285.07:55:07.43#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.07:55:07.43#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.07:55:07.43#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:07.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:55:07.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:55:07.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:55:07.49#ibcon#enter wrdev, iclass 3, count 2 2006.285.07:55:07.49#ibcon#first serial, iclass 3, count 2 2006.285.07:55:07.49#ibcon#enter sib2, iclass 3, count 2 2006.285.07:55:07.49#ibcon#flushed, iclass 3, count 2 2006.285.07:55:07.49#ibcon#about to write, iclass 3, count 2 2006.285.07:55:07.49#ibcon#wrote, iclass 3, count 2 2006.285.07:55:07.49#ibcon#about to read 3, iclass 3, count 2 2006.285.07:55:07.51#ibcon#read 3, iclass 3, count 2 2006.285.07:55:07.51#ibcon#about to read 4, iclass 3, count 2 2006.285.07:55:07.51#ibcon#read 4, iclass 3, count 2 2006.285.07:55:07.51#ibcon#about to read 5, iclass 3, count 2 2006.285.07:55:07.51#ibcon#read 5, iclass 3, count 2 2006.285.07:55:07.51#ibcon#about to read 6, iclass 3, count 2 2006.285.07:55:07.51#ibcon#read 6, iclass 3, count 2 2006.285.07:55:07.51#ibcon#end of sib2, iclass 3, count 2 2006.285.07:55:07.51#ibcon#*mode == 0, iclass 3, count 2 2006.285.07:55:07.51#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.07:55:07.51#ibcon#[25=AT03-07\r\n] 2006.285.07:55:07.51#ibcon#*before write, iclass 3, count 2 2006.285.07:55:07.51#ibcon#enter sib2, iclass 3, count 2 2006.285.07:55:07.51#ibcon#flushed, iclass 3, count 2 2006.285.07:55:07.51#ibcon#about to write, iclass 3, count 2 2006.285.07:55:07.51#ibcon#wrote, iclass 3, count 2 2006.285.07:55:07.51#ibcon#about to read 3, iclass 3, count 2 2006.285.07:55:07.54#ibcon#read 3, iclass 3, count 2 2006.285.07:55:07.54#ibcon#about to read 4, iclass 3, count 2 2006.285.07:55:07.54#ibcon#read 4, iclass 3, count 2 2006.285.07:55:07.54#ibcon#about to read 5, iclass 3, count 2 2006.285.07:55:07.54#ibcon#read 5, iclass 3, count 2 2006.285.07:55:07.54#ibcon#about to read 6, iclass 3, count 2 2006.285.07:55:07.54#ibcon#read 6, iclass 3, count 2 2006.285.07:55:07.54#ibcon#end of sib2, iclass 3, count 2 2006.285.07:55:07.54#ibcon#*after write, iclass 3, count 2 2006.285.07:55:07.54#ibcon#*before return 0, iclass 3, count 2 2006.285.07:55:07.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:55:07.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:55:07.54#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.07:55:07.54#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:07.54#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:55:07.66#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:55:07.66#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:55:07.66#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:55:07.66#ibcon#first serial, iclass 3, count 0 2006.285.07:55:07.66#ibcon#enter sib2, iclass 3, count 0 2006.285.07:55:07.66#ibcon#flushed, iclass 3, count 0 2006.285.07:55:07.66#ibcon#about to write, iclass 3, count 0 2006.285.07:55:07.66#ibcon#wrote, iclass 3, count 0 2006.285.07:55:07.66#ibcon#about to read 3, iclass 3, count 0 2006.285.07:55:07.68#ibcon#read 3, iclass 3, count 0 2006.285.07:55:07.68#ibcon#about to read 4, iclass 3, count 0 2006.285.07:55:07.68#ibcon#read 4, iclass 3, count 0 2006.285.07:55:07.68#ibcon#about to read 5, iclass 3, count 0 2006.285.07:55:07.68#ibcon#read 5, iclass 3, count 0 2006.285.07:55:07.68#ibcon#about to read 6, iclass 3, count 0 2006.285.07:55:07.68#ibcon#read 6, iclass 3, count 0 2006.285.07:55:07.68#ibcon#end of sib2, iclass 3, count 0 2006.285.07:55:07.68#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:55:07.68#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:55:07.68#ibcon#[25=USB\r\n] 2006.285.07:55:07.68#ibcon#*before write, iclass 3, count 0 2006.285.07:55:07.68#ibcon#enter sib2, iclass 3, count 0 2006.285.07:55:07.68#ibcon#flushed, iclass 3, count 0 2006.285.07:55:07.68#ibcon#about to write, iclass 3, count 0 2006.285.07:55:07.68#ibcon#wrote, iclass 3, count 0 2006.285.07:55:07.68#ibcon#about to read 3, iclass 3, count 0 2006.285.07:55:07.71#ibcon#read 3, iclass 3, count 0 2006.285.07:55:07.71#ibcon#about to read 4, iclass 3, count 0 2006.285.07:55:07.71#ibcon#read 4, iclass 3, count 0 2006.285.07:55:07.71#ibcon#about to read 5, iclass 3, count 0 2006.285.07:55:07.71#ibcon#read 5, iclass 3, count 0 2006.285.07:55:07.71#ibcon#about to read 6, iclass 3, count 0 2006.285.07:55:07.71#ibcon#read 6, iclass 3, count 0 2006.285.07:55:07.71#ibcon#end of sib2, iclass 3, count 0 2006.285.07:55:07.71#ibcon#*after write, iclass 3, count 0 2006.285.07:55:07.71#ibcon#*before return 0, iclass 3, count 0 2006.285.07:55:07.71#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:55:07.71#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:55:07.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:55:07.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:55:07.71$vck44/valo=4,624.99 2006.285.07:55:07.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.07:55:07.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.07:55:07.71#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:07.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:55:07.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:55:07.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:55:07.71#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:55:07.71#ibcon#first serial, iclass 5, count 0 2006.285.07:55:07.71#ibcon#enter sib2, iclass 5, count 0 2006.285.07:55:07.71#ibcon#flushed, iclass 5, count 0 2006.285.07:55:07.71#ibcon#about to write, iclass 5, count 0 2006.285.07:55:07.71#ibcon#wrote, iclass 5, count 0 2006.285.07:55:07.71#ibcon#about to read 3, iclass 5, count 0 2006.285.07:55:07.73#ibcon#read 3, iclass 5, count 0 2006.285.07:55:07.73#ibcon#about to read 4, iclass 5, count 0 2006.285.07:55:07.73#ibcon#read 4, iclass 5, count 0 2006.285.07:55:07.73#ibcon#about to read 5, iclass 5, count 0 2006.285.07:55:07.73#ibcon#read 5, iclass 5, count 0 2006.285.07:55:07.73#ibcon#about to read 6, iclass 5, count 0 2006.285.07:55:07.73#ibcon#read 6, iclass 5, count 0 2006.285.07:55:07.73#ibcon#end of sib2, iclass 5, count 0 2006.285.07:55:07.73#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:55:07.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:55:07.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.07:55:07.73#ibcon#*before write, iclass 5, count 0 2006.285.07:55:07.73#ibcon#enter sib2, iclass 5, count 0 2006.285.07:55:07.73#ibcon#flushed, iclass 5, count 0 2006.285.07:55:07.73#ibcon#about to write, iclass 5, count 0 2006.285.07:55:07.73#ibcon#wrote, iclass 5, count 0 2006.285.07:55:07.73#ibcon#about to read 3, iclass 5, count 0 2006.285.07:55:07.77#ibcon#read 3, iclass 5, count 0 2006.285.07:55:07.77#ibcon#about to read 4, iclass 5, count 0 2006.285.07:55:07.77#ibcon#read 4, iclass 5, count 0 2006.285.07:55:07.77#ibcon#about to read 5, iclass 5, count 0 2006.285.07:55:07.77#ibcon#read 5, iclass 5, count 0 2006.285.07:55:07.77#ibcon#about to read 6, iclass 5, count 0 2006.285.07:55:07.77#ibcon#read 6, iclass 5, count 0 2006.285.07:55:07.77#ibcon#end of sib2, iclass 5, count 0 2006.285.07:55:07.77#ibcon#*after write, iclass 5, count 0 2006.285.07:55:07.77#ibcon#*before return 0, iclass 5, count 0 2006.285.07:55:07.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:55:07.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:55:07.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:55:07.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:55:07.77$vck44/va=4,6 2006.285.07:55:07.77#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.07:55:07.77#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.07:55:07.77#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:07.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:55:07.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:55:07.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:55:07.83#ibcon#enter wrdev, iclass 7, count 2 2006.285.07:55:07.83#ibcon#first serial, iclass 7, count 2 2006.285.07:55:07.83#ibcon#enter sib2, iclass 7, count 2 2006.285.07:55:07.83#ibcon#flushed, iclass 7, count 2 2006.285.07:55:07.83#ibcon#about to write, iclass 7, count 2 2006.285.07:55:07.83#ibcon#wrote, iclass 7, count 2 2006.285.07:55:07.83#ibcon#about to read 3, iclass 7, count 2 2006.285.07:55:07.85#ibcon#read 3, iclass 7, count 2 2006.285.07:55:07.85#ibcon#about to read 4, iclass 7, count 2 2006.285.07:55:07.85#ibcon#read 4, iclass 7, count 2 2006.285.07:55:07.85#ibcon#about to read 5, iclass 7, count 2 2006.285.07:55:07.85#ibcon#read 5, iclass 7, count 2 2006.285.07:55:07.85#ibcon#about to read 6, iclass 7, count 2 2006.285.07:55:07.85#ibcon#read 6, iclass 7, count 2 2006.285.07:55:07.85#ibcon#end of sib2, iclass 7, count 2 2006.285.07:55:07.85#ibcon#*mode == 0, iclass 7, count 2 2006.285.07:55:07.85#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.07:55:07.85#ibcon#[25=AT04-06\r\n] 2006.285.07:55:07.85#ibcon#*before write, iclass 7, count 2 2006.285.07:55:07.85#ibcon#enter sib2, iclass 7, count 2 2006.285.07:55:07.85#ibcon#flushed, iclass 7, count 2 2006.285.07:55:07.85#ibcon#about to write, iclass 7, count 2 2006.285.07:55:07.85#ibcon#wrote, iclass 7, count 2 2006.285.07:55:07.85#ibcon#about to read 3, iclass 7, count 2 2006.285.07:55:07.88#ibcon#read 3, iclass 7, count 2 2006.285.07:55:07.88#ibcon#about to read 4, iclass 7, count 2 2006.285.07:55:07.88#ibcon#read 4, iclass 7, count 2 2006.285.07:55:07.88#ibcon#about to read 5, iclass 7, count 2 2006.285.07:55:07.88#ibcon#read 5, iclass 7, count 2 2006.285.07:55:07.88#ibcon#about to read 6, iclass 7, count 2 2006.285.07:55:07.88#ibcon#read 6, iclass 7, count 2 2006.285.07:55:07.88#ibcon#end of sib2, iclass 7, count 2 2006.285.07:55:07.88#ibcon#*after write, iclass 7, count 2 2006.285.07:55:07.88#ibcon#*before return 0, iclass 7, count 2 2006.285.07:55:07.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:55:07.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:55:07.88#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.07:55:07.88#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:07.88#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:55:08.00#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:55:08.00#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:55:08.00#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:55:08.00#ibcon#first serial, iclass 7, count 0 2006.285.07:55:08.00#ibcon#enter sib2, iclass 7, count 0 2006.285.07:55:08.00#ibcon#flushed, iclass 7, count 0 2006.285.07:55:08.00#ibcon#about to write, iclass 7, count 0 2006.285.07:55:08.00#ibcon#wrote, iclass 7, count 0 2006.285.07:55:08.00#ibcon#about to read 3, iclass 7, count 0 2006.285.07:55:08.02#ibcon#read 3, iclass 7, count 0 2006.285.07:55:08.02#ibcon#about to read 4, iclass 7, count 0 2006.285.07:55:08.02#ibcon#read 4, iclass 7, count 0 2006.285.07:55:08.02#ibcon#about to read 5, iclass 7, count 0 2006.285.07:55:08.02#ibcon#read 5, iclass 7, count 0 2006.285.07:55:08.02#ibcon#about to read 6, iclass 7, count 0 2006.285.07:55:08.02#ibcon#read 6, iclass 7, count 0 2006.285.07:55:08.02#ibcon#end of sib2, iclass 7, count 0 2006.285.07:55:08.02#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:55:08.02#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:55:08.02#ibcon#[25=USB\r\n] 2006.285.07:55:08.02#ibcon#*before write, iclass 7, count 0 2006.285.07:55:08.02#ibcon#enter sib2, iclass 7, count 0 2006.285.07:55:08.02#ibcon#flushed, iclass 7, count 0 2006.285.07:55:08.02#ibcon#about to write, iclass 7, count 0 2006.285.07:55:08.02#ibcon#wrote, iclass 7, count 0 2006.285.07:55:08.02#ibcon#about to read 3, iclass 7, count 0 2006.285.07:55:08.05#ibcon#read 3, iclass 7, count 0 2006.285.07:55:08.05#ibcon#about to read 4, iclass 7, count 0 2006.285.07:55:08.05#ibcon#read 4, iclass 7, count 0 2006.285.07:55:08.05#ibcon#about to read 5, iclass 7, count 0 2006.285.07:55:08.05#ibcon#read 5, iclass 7, count 0 2006.285.07:55:08.05#ibcon#about to read 6, iclass 7, count 0 2006.285.07:55:08.05#ibcon#read 6, iclass 7, count 0 2006.285.07:55:08.05#ibcon#end of sib2, iclass 7, count 0 2006.285.07:55:08.05#ibcon#*after write, iclass 7, count 0 2006.285.07:55:08.05#ibcon#*before return 0, iclass 7, count 0 2006.285.07:55:08.05#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:55:08.05#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:55:08.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:55:08.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:55:08.05$vck44/valo=5,734.99 2006.285.07:55:08.05#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.07:55:08.05#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.07:55:08.05#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:08.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:55:08.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:55:08.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:55:08.05#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:55:08.05#ibcon#first serial, iclass 11, count 0 2006.285.07:55:08.05#ibcon#enter sib2, iclass 11, count 0 2006.285.07:55:08.05#ibcon#flushed, iclass 11, count 0 2006.285.07:55:08.05#ibcon#about to write, iclass 11, count 0 2006.285.07:55:08.05#ibcon#wrote, iclass 11, count 0 2006.285.07:55:08.05#ibcon#about to read 3, iclass 11, count 0 2006.285.07:55:08.07#ibcon#read 3, iclass 11, count 0 2006.285.07:55:08.07#ibcon#about to read 4, iclass 11, count 0 2006.285.07:55:08.07#ibcon#read 4, iclass 11, count 0 2006.285.07:55:08.07#ibcon#about to read 5, iclass 11, count 0 2006.285.07:55:08.07#ibcon#read 5, iclass 11, count 0 2006.285.07:55:08.07#ibcon#about to read 6, iclass 11, count 0 2006.285.07:55:08.07#ibcon#read 6, iclass 11, count 0 2006.285.07:55:08.07#ibcon#end of sib2, iclass 11, count 0 2006.285.07:55:08.07#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:55:08.07#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:55:08.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.07:55:08.07#ibcon#*before write, iclass 11, count 0 2006.285.07:55:08.07#ibcon#enter sib2, iclass 11, count 0 2006.285.07:55:08.07#ibcon#flushed, iclass 11, count 0 2006.285.07:55:08.07#ibcon#about to write, iclass 11, count 0 2006.285.07:55:08.07#ibcon#wrote, iclass 11, count 0 2006.285.07:55:08.07#ibcon#about to read 3, iclass 11, count 0 2006.285.07:55:08.11#ibcon#read 3, iclass 11, count 0 2006.285.07:55:08.11#ibcon#about to read 4, iclass 11, count 0 2006.285.07:55:08.11#ibcon#read 4, iclass 11, count 0 2006.285.07:55:08.11#ibcon#about to read 5, iclass 11, count 0 2006.285.07:55:08.11#ibcon#read 5, iclass 11, count 0 2006.285.07:55:08.11#ibcon#about to read 6, iclass 11, count 0 2006.285.07:55:08.11#ibcon#read 6, iclass 11, count 0 2006.285.07:55:08.11#ibcon#end of sib2, iclass 11, count 0 2006.285.07:55:08.11#ibcon#*after write, iclass 11, count 0 2006.285.07:55:08.11#ibcon#*before return 0, iclass 11, count 0 2006.285.07:55:08.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:55:08.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:55:08.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:55:08.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:55:08.11$vck44/va=5,3 2006.285.07:55:08.11#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.07:55:08.11#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.07:55:08.11#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:08.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:55:08.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:55:08.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:55:08.17#ibcon#enter wrdev, iclass 13, count 2 2006.285.07:55:08.17#ibcon#first serial, iclass 13, count 2 2006.285.07:55:08.17#ibcon#enter sib2, iclass 13, count 2 2006.285.07:55:08.17#ibcon#flushed, iclass 13, count 2 2006.285.07:55:08.17#ibcon#about to write, iclass 13, count 2 2006.285.07:55:08.17#ibcon#wrote, iclass 13, count 2 2006.285.07:55:08.17#ibcon#about to read 3, iclass 13, count 2 2006.285.07:55:08.19#ibcon#read 3, iclass 13, count 2 2006.285.07:55:08.19#ibcon#about to read 4, iclass 13, count 2 2006.285.07:55:08.19#ibcon#read 4, iclass 13, count 2 2006.285.07:55:08.19#ibcon#about to read 5, iclass 13, count 2 2006.285.07:55:08.19#ibcon#read 5, iclass 13, count 2 2006.285.07:55:08.19#ibcon#about to read 6, iclass 13, count 2 2006.285.07:55:08.19#ibcon#read 6, iclass 13, count 2 2006.285.07:55:08.19#ibcon#end of sib2, iclass 13, count 2 2006.285.07:55:08.19#ibcon#*mode == 0, iclass 13, count 2 2006.285.07:55:08.19#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.07:55:08.19#ibcon#[25=AT05-03\r\n] 2006.285.07:55:08.19#ibcon#*before write, iclass 13, count 2 2006.285.07:55:08.19#ibcon#enter sib2, iclass 13, count 2 2006.285.07:55:08.19#ibcon#flushed, iclass 13, count 2 2006.285.07:55:08.19#ibcon#about to write, iclass 13, count 2 2006.285.07:55:08.19#ibcon#wrote, iclass 13, count 2 2006.285.07:55:08.19#ibcon#about to read 3, iclass 13, count 2 2006.285.07:55:08.22#ibcon#read 3, iclass 13, count 2 2006.285.07:55:08.22#ibcon#about to read 4, iclass 13, count 2 2006.285.07:55:08.22#ibcon#read 4, iclass 13, count 2 2006.285.07:55:08.22#ibcon#about to read 5, iclass 13, count 2 2006.285.07:55:08.22#ibcon#read 5, iclass 13, count 2 2006.285.07:55:08.22#ibcon#about to read 6, iclass 13, count 2 2006.285.07:55:08.22#ibcon#read 6, iclass 13, count 2 2006.285.07:55:08.22#ibcon#end of sib2, iclass 13, count 2 2006.285.07:55:08.22#ibcon#*after write, iclass 13, count 2 2006.285.07:55:08.22#ibcon#*before return 0, iclass 13, count 2 2006.285.07:55:08.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:55:08.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:55:08.22#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.07:55:08.22#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:08.22#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:55:08.34#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:55:08.34#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:55:08.34#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:55:08.34#ibcon#first serial, iclass 13, count 0 2006.285.07:55:08.34#ibcon#enter sib2, iclass 13, count 0 2006.285.07:55:08.34#ibcon#flushed, iclass 13, count 0 2006.285.07:55:08.34#ibcon#about to write, iclass 13, count 0 2006.285.07:55:08.34#ibcon#wrote, iclass 13, count 0 2006.285.07:55:08.34#ibcon#about to read 3, iclass 13, count 0 2006.285.07:55:08.36#ibcon#read 3, iclass 13, count 0 2006.285.07:55:08.36#ibcon#about to read 4, iclass 13, count 0 2006.285.07:55:08.36#ibcon#read 4, iclass 13, count 0 2006.285.07:55:08.36#ibcon#about to read 5, iclass 13, count 0 2006.285.07:55:08.36#ibcon#read 5, iclass 13, count 0 2006.285.07:55:08.36#ibcon#about to read 6, iclass 13, count 0 2006.285.07:55:08.36#ibcon#read 6, iclass 13, count 0 2006.285.07:55:08.36#ibcon#end of sib2, iclass 13, count 0 2006.285.07:55:08.36#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:55:08.36#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:55:08.36#ibcon#[25=USB\r\n] 2006.285.07:55:08.36#ibcon#*before write, iclass 13, count 0 2006.285.07:55:08.36#ibcon#enter sib2, iclass 13, count 0 2006.285.07:55:08.36#ibcon#flushed, iclass 13, count 0 2006.285.07:55:08.36#ibcon#about to write, iclass 13, count 0 2006.285.07:55:08.36#ibcon#wrote, iclass 13, count 0 2006.285.07:55:08.36#ibcon#about to read 3, iclass 13, count 0 2006.285.07:55:08.39#ibcon#read 3, iclass 13, count 0 2006.285.07:55:08.39#ibcon#about to read 4, iclass 13, count 0 2006.285.07:55:08.39#ibcon#read 4, iclass 13, count 0 2006.285.07:55:08.39#ibcon#about to read 5, iclass 13, count 0 2006.285.07:55:08.39#ibcon#read 5, iclass 13, count 0 2006.285.07:55:08.39#ibcon#about to read 6, iclass 13, count 0 2006.285.07:55:08.39#ibcon#read 6, iclass 13, count 0 2006.285.07:55:08.39#ibcon#end of sib2, iclass 13, count 0 2006.285.07:55:08.39#ibcon#*after write, iclass 13, count 0 2006.285.07:55:08.39#ibcon#*before return 0, iclass 13, count 0 2006.285.07:55:08.39#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:55:08.39#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:55:08.39#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:55:08.39#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:55:08.39$vck44/valo=6,814.99 2006.285.07:55:08.39#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.07:55:08.39#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.07:55:08.39#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:08.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:55:08.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:55:08.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:55:08.39#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:55:08.39#ibcon#first serial, iclass 15, count 0 2006.285.07:55:08.39#ibcon#enter sib2, iclass 15, count 0 2006.285.07:55:08.39#ibcon#flushed, iclass 15, count 0 2006.285.07:55:08.39#ibcon#about to write, iclass 15, count 0 2006.285.07:55:08.39#ibcon#wrote, iclass 15, count 0 2006.285.07:55:08.39#ibcon#about to read 3, iclass 15, count 0 2006.285.07:55:08.41#ibcon#read 3, iclass 15, count 0 2006.285.07:55:08.41#ibcon#about to read 4, iclass 15, count 0 2006.285.07:55:08.41#ibcon#read 4, iclass 15, count 0 2006.285.07:55:08.41#ibcon#about to read 5, iclass 15, count 0 2006.285.07:55:08.41#ibcon#read 5, iclass 15, count 0 2006.285.07:55:08.41#ibcon#about to read 6, iclass 15, count 0 2006.285.07:55:08.41#ibcon#read 6, iclass 15, count 0 2006.285.07:55:08.41#ibcon#end of sib2, iclass 15, count 0 2006.285.07:55:08.41#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:55:08.41#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:55:08.41#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.07:55:08.41#ibcon#*before write, iclass 15, count 0 2006.285.07:55:08.41#ibcon#enter sib2, iclass 15, count 0 2006.285.07:55:08.41#ibcon#flushed, iclass 15, count 0 2006.285.07:55:08.41#ibcon#about to write, iclass 15, count 0 2006.285.07:55:08.41#ibcon#wrote, iclass 15, count 0 2006.285.07:55:08.41#ibcon#about to read 3, iclass 15, count 0 2006.285.07:55:08.45#ibcon#read 3, iclass 15, count 0 2006.285.07:55:08.45#ibcon#about to read 4, iclass 15, count 0 2006.285.07:55:08.45#ibcon#read 4, iclass 15, count 0 2006.285.07:55:08.45#ibcon#about to read 5, iclass 15, count 0 2006.285.07:55:08.45#ibcon#read 5, iclass 15, count 0 2006.285.07:55:08.45#ibcon#about to read 6, iclass 15, count 0 2006.285.07:55:08.45#ibcon#read 6, iclass 15, count 0 2006.285.07:55:08.45#ibcon#end of sib2, iclass 15, count 0 2006.285.07:55:08.45#ibcon#*after write, iclass 15, count 0 2006.285.07:55:08.45#ibcon#*before return 0, iclass 15, count 0 2006.285.07:55:08.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:55:08.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:55:08.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:55:08.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:55:08.45$vck44/va=6,4 2006.285.07:55:08.45#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.07:55:08.45#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.07:55:08.45#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:08.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:55:08.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:55:08.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:55:08.51#ibcon#enter wrdev, iclass 17, count 2 2006.285.07:55:08.51#ibcon#first serial, iclass 17, count 2 2006.285.07:55:08.51#ibcon#enter sib2, iclass 17, count 2 2006.285.07:55:08.51#ibcon#flushed, iclass 17, count 2 2006.285.07:55:08.51#ibcon#about to write, iclass 17, count 2 2006.285.07:55:08.51#ibcon#wrote, iclass 17, count 2 2006.285.07:55:08.51#ibcon#about to read 3, iclass 17, count 2 2006.285.07:55:08.53#ibcon#read 3, iclass 17, count 2 2006.285.07:55:08.53#ibcon#about to read 4, iclass 17, count 2 2006.285.07:55:08.53#ibcon#read 4, iclass 17, count 2 2006.285.07:55:08.53#ibcon#about to read 5, iclass 17, count 2 2006.285.07:55:08.53#ibcon#read 5, iclass 17, count 2 2006.285.07:55:08.53#ibcon#about to read 6, iclass 17, count 2 2006.285.07:55:08.53#ibcon#read 6, iclass 17, count 2 2006.285.07:55:08.53#ibcon#end of sib2, iclass 17, count 2 2006.285.07:55:08.53#ibcon#*mode == 0, iclass 17, count 2 2006.285.07:55:08.53#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.07:55:08.53#ibcon#[25=AT06-04\r\n] 2006.285.07:55:08.53#ibcon#*before write, iclass 17, count 2 2006.285.07:55:08.53#ibcon#enter sib2, iclass 17, count 2 2006.285.07:55:08.53#ibcon#flushed, iclass 17, count 2 2006.285.07:55:08.53#ibcon#about to write, iclass 17, count 2 2006.285.07:55:08.53#ibcon#wrote, iclass 17, count 2 2006.285.07:55:08.53#ibcon#about to read 3, iclass 17, count 2 2006.285.07:55:08.56#ibcon#read 3, iclass 17, count 2 2006.285.07:55:08.56#ibcon#about to read 4, iclass 17, count 2 2006.285.07:55:08.56#ibcon#read 4, iclass 17, count 2 2006.285.07:55:08.56#ibcon#about to read 5, iclass 17, count 2 2006.285.07:55:08.56#ibcon#read 5, iclass 17, count 2 2006.285.07:55:08.56#ibcon#about to read 6, iclass 17, count 2 2006.285.07:55:08.56#ibcon#read 6, iclass 17, count 2 2006.285.07:55:08.56#ibcon#end of sib2, iclass 17, count 2 2006.285.07:55:08.56#ibcon#*after write, iclass 17, count 2 2006.285.07:55:08.56#ibcon#*before return 0, iclass 17, count 2 2006.285.07:55:08.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:55:08.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:55:08.56#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.07:55:08.56#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:08.56#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:55:08.68#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:55:08.68#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:55:08.68#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:55:08.68#ibcon#first serial, iclass 17, count 0 2006.285.07:55:08.68#ibcon#enter sib2, iclass 17, count 0 2006.285.07:55:08.68#ibcon#flushed, iclass 17, count 0 2006.285.07:55:08.68#ibcon#about to write, iclass 17, count 0 2006.285.07:55:08.68#ibcon#wrote, iclass 17, count 0 2006.285.07:55:08.68#ibcon#about to read 3, iclass 17, count 0 2006.285.07:55:08.70#ibcon#read 3, iclass 17, count 0 2006.285.07:55:08.70#ibcon#about to read 4, iclass 17, count 0 2006.285.07:55:08.70#ibcon#read 4, iclass 17, count 0 2006.285.07:55:08.70#ibcon#about to read 5, iclass 17, count 0 2006.285.07:55:08.70#ibcon#read 5, iclass 17, count 0 2006.285.07:55:08.70#ibcon#about to read 6, iclass 17, count 0 2006.285.07:55:08.70#ibcon#read 6, iclass 17, count 0 2006.285.07:55:08.70#ibcon#end of sib2, iclass 17, count 0 2006.285.07:55:08.70#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:55:08.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:55:08.70#ibcon#[25=USB\r\n] 2006.285.07:55:08.70#ibcon#*before write, iclass 17, count 0 2006.285.07:55:08.70#ibcon#enter sib2, iclass 17, count 0 2006.285.07:55:08.70#ibcon#flushed, iclass 17, count 0 2006.285.07:55:08.70#ibcon#about to write, iclass 17, count 0 2006.285.07:55:08.70#ibcon#wrote, iclass 17, count 0 2006.285.07:55:08.70#ibcon#about to read 3, iclass 17, count 0 2006.285.07:55:08.71#abcon#<5=/04 2.2 3.6 23.11 781014.5\r\n> 2006.285.07:55:08.73#abcon#{5=INTERFACE CLEAR} 2006.285.07:55:08.73#ibcon#read 3, iclass 17, count 0 2006.285.07:55:08.73#ibcon#about to read 4, iclass 17, count 0 2006.285.07:55:08.73#ibcon#read 4, iclass 17, count 0 2006.285.07:55:08.73#ibcon#about to read 5, iclass 17, count 0 2006.285.07:55:08.73#ibcon#read 5, iclass 17, count 0 2006.285.07:55:08.73#ibcon#about to read 6, iclass 17, count 0 2006.285.07:55:08.73#ibcon#read 6, iclass 17, count 0 2006.285.07:55:08.73#ibcon#end of sib2, iclass 17, count 0 2006.285.07:55:08.73#ibcon#*after write, iclass 17, count 0 2006.285.07:55:08.73#ibcon#*before return 0, iclass 17, count 0 2006.285.07:55:08.73#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:55:08.73#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:55:08.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:55:08.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:55:08.73$vck44/valo=7,864.99 2006.285.07:55:08.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.07:55:08.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.07:55:08.73#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:08.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:55:08.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:55:08.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:55:08.73#ibcon#enter wrdev, iclass 22, count 0 2006.285.07:55:08.73#ibcon#first serial, iclass 22, count 0 2006.285.07:55:08.73#ibcon#enter sib2, iclass 22, count 0 2006.285.07:55:08.73#ibcon#flushed, iclass 22, count 0 2006.285.07:55:08.73#ibcon#about to write, iclass 22, count 0 2006.285.07:55:08.73#ibcon#wrote, iclass 22, count 0 2006.285.07:55:08.73#ibcon#about to read 3, iclass 22, count 0 2006.285.07:55:08.75#ibcon#read 3, iclass 22, count 0 2006.285.07:55:08.75#ibcon#about to read 4, iclass 22, count 0 2006.285.07:55:08.75#ibcon#read 4, iclass 22, count 0 2006.285.07:55:08.75#ibcon#about to read 5, iclass 22, count 0 2006.285.07:55:08.75#ibcon#read 5, iclass 22, count 0 2006.285.07:55:08.75#ibcon#about to read 6, iclass 22, count 0 2006.285.07:55:08.75#ibcon#read 6, iclass 22, count 0 2006.285.07:55:08.75#ibcon#end of sib2, iclass 22, count 0 2006.285.07:55:08.75#ibcon#*mode == 0, iclass 22, count 0 2006.285.07:55:08.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.07:55:08.75#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.07:55:08.75#ibcon#*before write, iclass 22, count 0 2006.285.07:55:08.75#ibcon#enter sib2, iclass 22, count 0 2006.285.07:55:08.75#ibcon#flushed, iclass 22, count 0 2006.285.07:55:08.75#ibcon#about to write, iclass 22, count 0 2006.285.07:55:08.75#ibcon#wrote, iclass 22, count 0 2006.285.07:55:08.75#ibcon#about to read 3, iclass 22, count 0 2006.285.07:55:08.79#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:55:08.79#ibcon#read 3, iclass 22, count 0 2006.285.07:55:08.79#ibcon#about to read 4, iclass 22, count 0 2006.285.07:55:08.79#ibcon#read 4, iclass 22, count 0 2006.285.07:55:08.79#ibcon#about to read 5, iclass 22, count 0 2006.285.07:55:08.79#ibcon#read 5, iclass 22, count 0 2006.285.07:55:08.79#ibcon#about to read 6, iclass 22, count 0 2006.285.07:55:08.79#ibcon#read 6, iclass 22, count 0 2006.285.07:55:08.79#ibcon#end of sib2, iclass 22, count 0 2006.285.07:55:08.79#ibcon#*after write, iclass 22, count 0 2006.285.07:55:08.79#ibcon#*before return 0, iclass 22, count 0 2006.285.07:55:08.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:55:08.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.07:55:08.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.07:55:08.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.07:55:08.79$vck44/va=7,4 2006.285.07:55:08.79#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.07:55:08.79#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.07:55:08.79#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:08.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:55:08.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:55:08.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:55:08.85#ibcon#enter wrdev, iclass 25, count 2 2006.285.07:55:08.85#ibcon#first serial, iclass 25, count 2 2006.285.07:55:08.85#ibcon#enter sib2, iclass 25, count 2 2006.285.07:55:08.85#ibcon#flushed, iclass 25, count 2 2006.285.07:55:08.85#ibcon#about to write, iclass 25, count 2 2006.285.07:55:08.85#ibcon#wrote, iclass 25, count 2 2006.285.07:55:08.85#ibcon#about to read 3, iclass 25, count 2 2006.285.07:55:08.87#ibcon#read 3, iclass 25, count 2 2006.285.07:55:08.87#ibcon#about to read 4, iclass 25, count 2 2006.285.07:55:08.87#ibcon#read 4, iclass 25, count 2 2006.285.07:55:08.87#ibcon#about to read 5, iclass 25, count 2 2006.285.07:55:08.87#ibcon#read 5, iclass 25, count 2 2006.285.07:55:08.87#ibcon#about to read 6, iclass 25, count 2 2006.285.07:55:08.87#ibcon#read 6, iclass 25, count 2 2006.285.07:55:08.87#ibcon#end of sib2, iclass 25, count 2 2006.285.07:55:08.87#ibcon#*mode == 0, iclass 25, count 2 2006.285.07:55:08.87#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.07:55:08.87#ibcon#[25=AT07-04\r\n] 2006.285.07:55:08.87#ibcon#*before write, iclass 25, count 2 2006.285.07:55:08.87#ibcon#enter sib2, iclass 25, count 2 2006.285.07:55:08.87#ibcon#flushed, iclass 25, count 2 2006.285.07:55:08.87#ibcon#about to write, iclass 25, count 2 2006.285.07:55:08.87#ibcon#wrote, iclass 25, count 2 2006.285.07:55:08.87#ibcon#about to read 3, iclass 25, count 2 2006.285.07:55:08.90#ibcon#read 3, iclass 25, count 2 2006.285.07:55:08.90#ibcon#about to read 4, iclass 25, count 2 2006.285.07:55:08.90#ibcon#read 4, iclass 25, count 2 2006.285.07:55:08.90#ibcon#about to read 5, iclass 25, count 2 2006.285.07:55:08.90#ibcon#read 5, iclass 25, count 2 2006.285.07:55:08.90#ibcon#about to read 6, iclass 25, count 2 2006.285.07:55:08.90#ibcon#read 6, iclass 25, count 2 2006.285.07:55:08.90#ibcon#end of sib2, iclass 25, count 2 2006.285.07:55:08.90#ibcon#*after write, iclass 25, count 2 2006.285.07:55:08.90#ibcon#*before return 0, iclass 25, count 2 2006.285.07:55:08.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:55:08.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:55:08.90#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.07:55:08.90#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:08.90#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:55:09.02#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:55:09.02#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:55:09.02#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:55:09.02#ibcon#first serial, iclass 25, count 0 2006.285.07:55:09.02#ibcon#enter sib2, iclass 25, count 0 2006.285.07:55:09.02#ibcon#flushed, iclass 25, count 0 2006.285.07:55:09.02#ibcon#about to write, iclass 25, count 0 2006.285.07:55:09.02#ibcon#wrote, iclass 25, count 0 2006.285.07:55:09.02#ibcon#about to read 3, iclass 25, count 0 2006.285.07:55:09.04#ibcon#read 3, iclass 25, count 0 2006.285.07:55:09.04#ibcon#about to read 4, iclass 25, count 0 2006.285.07:55:09.04#ibcon#read 4, iclass 25, count 0 2006.285.07:55:09.04#ibcon#about to read 5, iclass 25, count 0 2006.285.07:55:09.04#ibcon#read 5, iclass 25, count 0 2006.285.07:55:09.04#ibcon#about to read 6, iclass 25, count 0 2006.285.07:55:09.04#ibcon#read 6, iclass 25, count 0 2006.285.07:55:09.04#ibcon#end of sib2, iclass 25, count 0 2006.285.07:55:09.04#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:55:09.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:55:09.04#ibcon#[25=USB\r\n] 2006.285.07:55:09.04#ibcon#*before write, iclass 25, count 0 2006.285.07:55:09.04#ibcon#enter sib2, iclass 25, count 0 2006.285.07:55:09.04#ibcon#flushed, iclass 25, count 0 2006.285.07:55:09.04#ibcon#about to write, iclass 25, count 0 2006.285.07:55:09.04#ibcon#wrote, iclass 25, count 0 2006.285.07:55:09.04#ibcon#about to read 3, iclass 25, count 0 2006.285.07:55:09.07#ibcon#read 3, iclass 25, count 0 2006.285.07:55:09.07#ibcon#about to read 4, iclass 25, count 0 2006.285.07:55:09.07#ibcon#read 4, iclass 25, count 0 2006.285.07:55:09.07#ibcon#about to read 5, iclass 25, count 0 2006.285.07:55:09.07#ibcon#read 5, iclass 25, count 0 2006.285.07:55:09.07#ibcon#about to read 6, iclass 25, count 0 2006.285.07:55:09.07#ibcon#read 6, iclass 25, count 0 2006.285.07:55:09.07#ibcon#end of sib2, iclass 25, count 0 2006.285.07:55:09.07#ibcon#*after write, iclass 25, count 0 2006.285.07:55:09.07#ibcon#*before return 0, iclass 25, count 0 2006.285.07:55:09.07#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:55:09.07#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:55:09.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:55:09.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:55:09.07$vck44/valo=8,884.99 2006.285.07:55:09.07#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.07:55:09.07#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.07:55:09.07#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:09.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:55:09.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:55:09.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:55:09.07#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:55:09.07#ibcon#first serial, iclass 27, count 0 2006.285.07:55:09.07#ibcon#enter sib2, iclass 27, count 0 2006.285.07:55:09.07#ibcon#flushed, iclass 27, count 0 2006.285.07:55:09.07#ibcon#about to write, iclass 27, count 0 2006.285.07:55:09.07#ibcon#wrote, iclass 27, count 0 2006.285.07:55:09.07#ibcon#about to read 3, iclass 27, count 0 2006.285.07:55:09.09#ibcon#read 3, iclass 27, count 0 2006.285.07:55:09.09#ibcon#about to read 4, iclass 27, count 0 2006.285.07:55:09.09#ibcon#read 4, iclass 27, count 0 2006.285.07:55:09.09#ibcon#about to read 5, iclass 27, count 0 2006.285.07:55:09.09#ibcon#read 5, iclass 27, count 0 2006.285.07:55:09.09#ibcon#about to read 6, iclass 27, count 0 2006.285.07:55:09.09#ibcon#read 6, iclass 27, count 0 2006.285.07:55:09.09#ibcon#end of sib2, iclass 27, count 0 2006.285.07:55:09.09#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:55:09.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:55:09.09#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.07:55:09.09#ibcon#*before write, iclass 27, count 0 2006.285.07:55:09.09#ibcon#enter sib2, iclass 27, count 0 2006.285.07:55:09.09#ibcon#flushed, iclass 27, count 0 2006.285.07:55:09.09#ibcon#about to write, iclass 27, count 0 2006.285.07:55:09.09#ibcon#wrote, iclass 27, count 0 2006.285.07:55:09.09#ibcon#about to read 3, iclass 27, count 0 2006.285.07:55:09.13#ibcon#read 3, iclass 27, count 0 2006.285.07:55:09.13#ibcon#about to read 4, iclass 27, count 0 2006.285.07:55:09.13#ibcon#read 4, iclass 27, count 0 2006.285.07:55:09.13#ibcon#about to read 5, iclass 27, count 0 2006.285.07:55:09.13#ibcon#read 5, iclass 27, count 0 2006.285.07:55:09.13#ibcon#about to read 6, iclass 27, count 0 2006.285.07:55:09.13#ibcon#read 6, iclass 27, count 0 2006.285.07:55:09.13#ibcon#end of sib2, iclass 27, count 0 2006.285.07:55:09.13#ibcon#*after write, iclass 27, count 0 2006.285.07:55:09.13#ibcon#*before return 0, iclass 27, count 0 2006.285.07:55:09.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:55:09.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:55:09.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:55:09.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:55:09.13$vck44/va=8,3 2006.285.07:55:09.13#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.07:55:09.13#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.07:55:09.13#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:09.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:55:09.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:55:09.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:55:09.19#ibcon#enter wrdev, iclass 29, count 2 2006.285.07:55:09.19#ibcon#first serial, iclass 29, count 2 2006.285.07:55:09.19#ibcon#enter sib2, iclass 29, count 2 2006.285.07:55:09.19#ibcon#flushed, iclass 29, count 2 2006.285.07:55:09.19#ibcon#about to write, iclass 29, count 2 2006.285.07:55:09.19#ibcon#wrote, iclass 29, count 2 2006.285.07:55:09.19#ibcon#about to read 3, iclass 29, count 2 2006.285.07:55:09.21#ibcon#read 3, iclass 29, count 2 2006.285.07:55:09.21#ibcon#about to read 4, iclass 29, count 2 2006.285.07:55:09.21#ibcon#read 4, iclass 29, count 2 2006.285.07:55:09.21#ibcon#about to read 5, iclass 29, count 2 2006.285.07:55:09.21#ibcon#read 5, iclass 29, count 2 2006.285.07:55:09.21#ibcon#about to read 6, iclass 29, count 2 2006.285.07:55:09.21#ibcon#read 6, iclass 29, count 2 2006.285.07:55:09.21#ibcon#end of sib2, iclass 29, count 2 2006.285.07:55:09.21#ibcon#*mode == 0, iclass 29, count 2 2006.285.07:55:09.21#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.07:55:09.21#ibcon#[25=AT08-03\r\n] 2006.285.07:55:09.21#ibcon#*before write, iclass 29, count 2 2006.285.07:55:09.21#ibcon#enter sib2, iclass 29, count 2 2006.285.07:55:09.21#ibcon#flushed, iclass 29, count 2 2006.285.07:55:09.21#ibcon#about to write, iclass 29, count 2 2006.285.07:55:09.21#ibcon#wrote, iclass 29, count 2 2006.285.07:55:09.21#ibcon#about to read 3, iclass 29, count 2 2006.285.07:55:09.24#ibcon#read 3, iclass 29, count 2 2006.285.07:55:09.24#ibcon#about to read 4, iclass 29, count 2 2006.285.07:55:09.24#ibcon#read 4, iclass 29, count 2 2006.285.07:55:09.24#ibcon#about to read 5, iclass 29, count 2 2006.285.07:55:09.24#ibcon#read 5, iclass 29, count 2 2006.285.07:55:09.24#ibcon#about to read 6, iclass 29, count 2 2006.285.07:55:09.24#ibcon#read 6, iclass 29, count 2 2006.285.07:55:09.24#ibcon#end of sib2, iclass 29, count 2 2006.285.07:55:09.24#ibcon#*after write, iclass 29, count 2 2006.285.07:55:09.24#ibcon#*before return 0, iclass 29, count 2 2006.285.07:55:09.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:55:09.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.07:55:09.24#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.07:55:09.24#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:09.24#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:55:09.36#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:55:09.36#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:55:09.36#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:55:09.36#ibcon#first serial, iclass 29, count 0 2006.285.07:55:09.36#ibcon#enter sib2, iclass 29, count 0 2006.285.07:55:09.36#ibcon#flushed, iclass 29, count 0 2006.285.07:55:09.36#ibcon#about to write, iclass 29, count 0 2006.285.07:55:09.36#ibcon#wrote, iclass 29, count 0 2006.285.07:55:09.36#ibcon#about to read 3, iclass 29, count 0 2006.285.07:55:09.38#ibcon#read 3, iclass 29, count 0 2006.285.07:55:09.38#ibcon#about to read 4, iclass 29, count 0 2006.285.07:55:09.38#ibcon#read 4, iclass 29, count 0 2006.285.07:55:09.38#ibcon#about to read 5, iclass 29, count 0 2006.285.07:55:09.38#ibcon#read 5, iclass 29, count 0 2006.285.07:55:09.38#ibcon#about to read 6, iclass 29, count 0 2006.285.07:55:09.38#ibcon#read 6, iclass 29, count 0 2006.285.07:55:09.38#ibcon#end of sib2, iclass 29, count 0 2006.285.07:55:09.38#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:55:09.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:55:09.38#ibcon#[25=USB\r\n] 2006.285.07:55:09.38#ibcon#*before write, iclass 29, count 0 2006.285.07:55:09.38#ibcon#enter sib2, iclass 29, count 0 2006.285.07:55:09.38#ibcon#flushed, iclass 29, count 0 2006.285.07:55:09.38#ibcon#about to write, iclass 29, count 0 2006.285.07:55:09.38#ibcon#wrote, iclass 29, count 0 2006.285.07:55:09.38#ibcon#about to read 3, iclass 29, count 0 2006.285.07:55:09.41#ibcon#read 3, iclass 29, count 0 2006.285.07:55:09.41#ibcon#about to read 4, iclass 29, count 0 2006.285.07:55:09.41#ibcon#read 4, iclass 29, count 0 2006.285.07:55:09.41#ibcon#about to read 5, iclass 29, count 0 2006.285.07:55:09.41#ibcon#read 5, iclass 29, count 0 2006.285.07:55:09.41#ibcon#about to read 6, iclass 29, count 0 2006.285.07:55:09.41#ibcon#read 6, iclass 29, count 0 2006.285.07:55:09.41#ibcon#end of sib2, iclass 29, count 0 2006.285.07:55:09.41#ibcon#*after write, iclass 29, count 0 2006.285.07:55:09.41#ibcon#*before return 0, iclass 29, count 0 2006.285.07:55:09.41#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:55:09.41#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.07:55:09.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:55:09.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:55:09.41$vck44/vblo=1,629.99 2006.285.07:55:09.41#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.07:55:09.41#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.07:55:09.41#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:09.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:55:09.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:55:09.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:55:09.41#ibcon#enter wrdev, iclass 31, count 0 2006.285.07:55:09.41#ibcon#first serial, iclass 31, count 0 2006.285.07:55:09.41#ibcon#enter sib2, iclass 31, count 0 2006.285.07:55:09.41#ibcon#flushed, iclass 31, count 0 2006.285.07:55:09.41#ibcon#about to write, iclass 31, count 0 2006.285.07:55:09.41#ibcon#wrote, iclass 31, count 0 2006.285.07:55:09.41#ibcon#about to read 3, iclass 31, count 0 2006.285.07:55:09.43#ibcon#read 3, iclass 31, count 0 2006.285.07:55:09.43#ibcon#about to read 4, iclass 31, count 0 2006.285.07:55:09.43#ibcon#read 4, iclass 31, count 0 2006.285.07:55:09.43#ibcon#about to read 5, iclass 31, count 0 2006.285.07:55:09.43#ibcon#read 5, iclass 31, count 0 2006.285.07:55:09.43#ibcon#about to read 6, iclass 31, count 0 2006.285.07:55:09.43#ibcon#read 6, iclass 31, count 0 2006.285.07:55:09.43#ibcon#end of sib2, iclass 31, count 0 2006.285.07:55:09.43#ibcon#*mode == 0, iclass 31, count 0 2006.285.07:55:09.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.07:55:09.43#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.07:55:09.43#ibcon#*before write, iclass 31, count 0 2006.285.07:55:09.43#ibcon#enter sib2, iclass 31, count 0 2006.285.07:55:09.43#ibcon#flushed, iclass 31, count 0 2006.285.07:55:09.43#ibcon#about to write, iclass 31, count 0 2006.285.07:55:09.43#ibcon#wrote, iclass 31, count 0 2006.285.07:55:09.43#ibcon#about to read 3, iclass 31, count 0 2006.285.07:55:09.47#ibcon#read 3, iclass 31, count 0 2006.285.07:55:09.47#ibcon#about to read 4, iclass 31, count 0 2006.285.07:55:09.47#ibcon#read 4, iclass 31, count 0 2006.285.07:55:09.47#ibcon#about to read 5, iclass 31, count 0 2006.285.07:55:09.47#ibcon#read 5, iclass 31, count 0 2006.285.07:55:09.47#ibcon#about to read 6, iclass 31, count 0 2006.285.07:55:09.47#ibcon#read 6, iclass 31, count 0 2006.285.07:55:09.47#ibcon#end of sib2, iclass 31, count 0 2006.285.07:55:09.47#ibcon#*after write, iclass 31, count 0 2006.285.07:55:09.47#ibcon#*before return 0, iclass 31, count 0 2006.285.07:55:09.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:55:09.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.07:55:09.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.07:55:09.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.07:55:09.47$vck44/vb=1,4 2006.285.07:55:09.47#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.07:55:09.47#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.07:55:09.47#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:09.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:55:09.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:55:09.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:55:09.47#ibcon#enter wrdev, iclass 33, count 2 2006.285.07:55:09.47#ibcon#first serial, iclass 33, count 2 2006.285.07:55:09.47#ibcon#enter sib2, iclass 33, count 2 2006.285.07:55:09.47#ibcon#flushed, iclass 33, count 2 2006.285.07:55:09.47#ibcon#about to write, iclass 33, count 2 2006.285.07:55:09.47#ibcon#wrote, iclass 33, count 2 2006.285.07:55:09.47#ibcon#about to read 3, iclass 33, count 2 2006.285.07:55:09.49#ibcon#read 3, iclass 33, count 2 2006.285.07:55:09.49#ibcon#about to read 4, iclass 33, count 2 2006.285.07:55:09.49#ibcon#read 4, iclass 33, count 2 2006.285.07:55:09.49#ibcon#about to read 5, iclass 33, count 2 2006.285.07:55:09.49#ibcon#read 5, iclass 33, count 2 2006.285.07:55:09.49#ibcon#about to read 6, iclass 33, count 2 2006.285.07:55:09.49#ibcon#read 6, iclass 33, count 2 2006.285.07:55:09.49#ibcon#end of sib2, iclass 33, count 2 2006.285.07:55:09.49#ibcon#*mode == 0, iclass 33, count 2 2006.285.07:55:09.49#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.07:55:09.49#ibcon#[27=AT01-04\r\n] 2006.285.07:55:09.49#ibcon#*before write, iclass 33, count 2 2006.285.07:55:09.49#ibcon#enter sib2, iclass 33, count 2 2006.285.07:55:09.49#ibcon#flushed, iclass 33, count 2 2006.285.07:55:09.49#ibcon#about to write, iclass 33, count 2 2006.285.07:55:09.49#ibcon#wrote, iclass 33, count 2 2006.285.07:55:09.49#ibcon#about to read 3, iclass 33, count 2 2006.285.07:55:09.52#ibcon#read 3, iclass 33, count 2 2006.285.07:55:09.52#ibcon#about to read 4, iclass 33, count 2 2006.285.07:55:09.52#ibcon#read 4, iclass 33, count 2 2006.285.07:55:09.52#ibcon#about to read 5, iclass 33, count 2 2006.285.07:55:09.52#ibcon#read 5, iclass 33, count 2 2006.285.07:55:09.52#ibcon#about to read 6, iclass 33, count 2 2006.285.07:55:09.52#ibcon#read 6, iclass 33, count 2 2006.285.07:55:09.52#ibcon#end of sib2, iclass 33, count 2 2006.285.07:55:09.52#ibcon#*after write, iclass 33, count 2 2006.285.07:55:09.52#ibcon#*before return 0, iclass 33, count 2 2006.285.07:55:09.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:55:09.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.07:55:09.52#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.07:55:09.52#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:09.52#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:55:09.64#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:55:09.64#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:55:09.64#ibcon#enter wrdev, iclass 33, count 0 2006.285.07:55:09.64#ibcon#first serial, iclass 33, count 0 2006.285.07:55:09.64#ibcon#enter sib2, iclass 33, count 0 2006.285.07:55:09.64#ibcon#flushed, iclass 33, count 0 2006.285.07:55:09.64#ibcon#about to write, iclass 33, count 0 2006.285.07:55:09.64#ibcon#wrote, iclass 33, count 0 2006.285.07:55:09.64#ibcon#about to read 3, iclass 33, count 0 2006.285.07:55:09.66#ibcon#read 3, iclass 33, count 0 2006.285.07:55:09.66#ibcon#about to read 4, iclass 33, count 0 2006.285.07:55:09.66#ibcon#read 4, iclass 33, count 0 2006.285.07:55:09.66#ibcon#about to read 5, iclass 33, count 0 2006.285.07:55:09.66#ibcon#read 5, iclass 33, count 0 2006.285.07:55:09.66#ibcon#about to read 6, iclass 33, count 0 2006.285.07:55:09.66#ibcon#read 6, iclass 33, count 0 2006.285.07:55:09.66#ibcon#end of sib2, iclass 33, count 0 2006.285.07:55:09.66#ibcon#*mode == 0, iclass 33, count 0 2006.285.07:55:09.66#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.07:55:09.66#ibcon#[27=USB\r\n] 2006.285.07:55:09.66#ibcon#*before write, iclass 33, count 0 2006.285.07:55:09.66#ibcon#enter sib2, iclass 33, count 0 2006.285.07:55:09.66#ibcon#flushed, iclass 33, count 0 2006.285.07:55:09.66#ibcon#about to write, iclass 33, count 0 2006.285.07:55:09.66#ibcon#wrote, iclass 33, count 0 2006.285.07:55:09.66#ibcon#about to read 3, iclass 33, count 0 2006.285.07:55:09.69#ibcon#read 3, iclass 33, count 0 2006.285.07:55:09.69#ibcon#about to read 4, iclass 33, count 0 2006.285.07:55:09.69#ibcon#read 4, iclass 33, count 0 2006.285.07:55:09.69#ibcon#about to read 5, iclass 33, count 0 2006.285.07:55:09.69#ibcon#read 5, iclass 33, count 0 2006.285.07:55:09.69#ibcon#about to read 6, iclass 33, count 0 2006.285.07:55:09.69#ibcon#read 6, iclass 33, count 0 2006.285.07:55:09.69#ibcon#end of sib2, iclass 33, count 0 2006.285.07:55:09.69#ibcon#*after write, iclass 33, count 0 2006.285.07:55:09.69#ibcon#*before return 0, iclass 33, count 0 2006.285.07:55:09.69#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:55:09.69#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.07:55:09.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.07:55:09.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.07:55:09.69$vck44/vblo=2,634.99 2006.285.07:55:09.69#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.07:55:09.69#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.07:55:09.69#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:09.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:55:09.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:55:09.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:55:09.69#ibcon#enter wrdev, iclass 35, count 0 2006.285.07:55:09.69#ibcon#first serial, iclass 35, count 0 2006.285.07:55:09.69#ibcon#enter sib2, iclass 35, count 0 2006.285.07:55:09.69#ibcon#flushed, iclass 35, count 0 2006.285.07:55:09.69#ibcon#about to write, iclass 35, count 0 2006.285.07:55:09.69#ibcon#wrote, iclass 35, count 0 2006.285.07:55:09.69#ibcon#about to read 3, iclass 35, count 0 2006.285.07:55:09.71#ibcon#read 3, iclass 35, count 0 2006.285.07:55:09.71#ibcon#about to read 4, iclass 35, count 0 2006.285.07:55:09.71#ibcon#read 4, iclass 35, count 0 2006.285.07:55:09.71#ibcon#about to read 5, iclass 35, count 0 2006.285.07:55:09.71#ibcon#read 5, iclass 35, count 0 2006.285.07:55:09.71#ibcon#about to read 6, iclass 35, count 0 2006.285.07:55:09.71#ibcon#read 6, iclass 35, count 0 2006.285.07:55:09.71#ibcon#end of sib2, iclass 35, count 0 2006.285.07:55:09.71#ibcon#*mode == 0, iclass 35, count 0 2006.285.07:55:09.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.07:55:09.71#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.07:55:09.71#ibcon#*before write, iclass 35, count 0 2006.285.07:55:09.71#ibcon#enter sib2, iclass 35, count 0 2006.285.07:55:09.71#ibcon#flushed, iclass 35, count 0 2006.285.07:55:09.71#ibcon#about to write, iclass 35, count 0 2006.285.07:55:09.71#ibcon#wrote, iclass 35, count 0 2006.285.07:55:09.71#ibcon#about to read 3, iclass 35, count 0 2006.285.07:55:09.75#ibcon#read 3, iclass 35, count 0 2006.285.07:55:09.75#ibcon#about to read 4, iclass 35, count 0 2006.285.07:55:09.75#ibcon#read 4, iclass 35, count 0 2006.285.07:55:09.75#ibcon#about to read 5, iclass 35, count 0 2006.285.07:55:09.75#ibcon#read 5, iclass 35, count 0 2006.285.07:55:09.75#ibcon#about to read 6, iclass 35, count 0 2006.285.07:55:09.75#ibcon#read 6, iclass 35, count 0 2006.285.07:55:09.75#ibcon#end of sib2, iclass 35, count 0 2006.285.07:55:09.75#ibcon#*after write, iclass 35, count 0 2006.285.07:55:09.75#ibcon#*before return 0, iclass 35, count 0 2006.285.07:55:09.75#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:55:09.75#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.07:55:09.75#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.07:55:09.75#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.07:55:09.75$vck44/vb=2,5 2006.285.07:55:09.75#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.07:55:09.75#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.07:55:09.75#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:09.75#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:55:09.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:55:09.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:55:09.81#ibcon#enter wrdev, iclass 37, count 2 2006.285.07:55:09.81#ibcon#first serial, iclass 37, count 2 2006.285.07:55:09.81#ibcon#enter sib2, iclass 37, count 2 2006.285.07:55:09.81#ibcon#flushed, iclass 37, count 2 2006.285.07:55:09.81#ibcon#about to write, iclass 37, count 2 2006.285.07:55:09.81#ibcon#wrote, iclass 37, count 2 2006.285.07:55:09.81#ibcon#about to read 3, iclass 37, count 2 2006.285.07:55:09.83#ibcon#read 3, iclass 37, count 2 2006.285.07:55:09.83#ibcon#about to read 4, iclass 37, count 2 2006.285.07:55:09.83#ibcon#read 4, iclass 37, count 2 2006.285.07:55:09.83#ibcon#about to read 5, iclass 37, count 2 2006.285.07:55:09.83#ibcon#read 5, iclass 37, count 2 2006.285.07:55:09.83#ibcon#about to read 6, iclass 37, count 2 2006.285.07:55:09.83#ibcon#read 6, iclass 37, count 2 2006.285.07:55:09.83#ibcon#end of sib2, iclass 37, count 2 2006.285.07:55:09.83#ibcon#*mode == 0, iclass 37, count 2 2006.285.07:55:09.83#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.07:55:09.83#ibcon#[27=AT02-05\r\n] 2006.285.07:55:09.83#ibcon#*before write, iclass 37, count 2 2006.285.07:55:09.83#ibcon#enter sib2, iclass 37, count 2 2006.285.07:55:09.83#ibcon#flushed, iclass 37, count 2 2006.285.07:55:09.83#ibcon#about to write, iclass 37, count 2 2006.285.07:55:09.83#ibcon#wrote, iclass 37, count 2 2006.285.07:55:09.83#ibcon#about to read 3, iclass 37, count 2 2006.285.07:55:09.86#ibcon#read 3, iclass 37, count 2 2006.285.07:55:09.86#ibcon#about to read 4, iclass 37, count 2 2006.285.07:55:09.86#ibcon#read 4, iclass 37, count 2 2006.285.07:55:09.86#ibcon#about to read 5, iclass 37, count 2 2006.285.07:55:09.86#ibcon#read 5, iclass 37, count 2 2006.285.07:55:09.86#ibcon#about to read 6, iclass 37, count 2 2006.285.07:55:09.86#ibcon#read 6, iclass 37, count 2 2006.285.07:55:09.86#ibcon#end of sib2, iclass 37, count 2 2006.285.07:55:09.86#ibcon#*after write, iclass 37, count 2 2006.285.07:55:09.86#ibcon#*before return 0, iclass 37, count 2 2006.285.07:55:09.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:55:09.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.07:55:09.86#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.07:55:09.86#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:09.86#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:55:09.98#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:55:09.98#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:55:09.98#ibcon#enter wrdev, iclass 37, count 0 2006.285.07:55:09.98#ibcon#first serial, iclass 37, count 0 2006.285.07:55:09.98#ibcon#enter sib2, iclass 37, count 0 2006.285.07:55:09.98#ibcon#flushed, iclass 37, count 0 2006.285.07:55:09.98#ibcon#about to write, iclass 37, count 0 2006.285.07:55:09.98#ibcon#wrote, iclass 37, count 0 2006.285.07:55:09.98#ibcon#about to read 3, iclass 37, count 0 2006.285.07:55:10.00#ibcon#read 3, iclass 37, count 0 2006.285.07:55:10.00#ibcon#about to read 4, iclass 37, count 0 2006.285.07:55:10.00#ibcon#read 4, iclass 37, count 0 2006.285.07:55:10.00#ibcon#about to read 5, iclass 37, count 0 2006.285.07:55:10.00#ibcon#read 5, iclass 37, count 0 2006.285.07:55:10.00#ibcon#about to read 6, iclass 37, count 0 2006.285.07:55:10.00#ibcon#read 6, iclass 37, count 0 2006.285.07:55:10.00#ibcon#end of sib2, iclass 37, count 0 2006.285.07:55:10.00#ibcon#*mode == 0, iclass 37, count 0 2006.285.07:55:10.00#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.07:55:10.00#ibcon#[27=USB\r\n] 2006.285.07:55:10.00#ibcon#*before write, iclass 37, count 0 2006.285.07:55:10.00#ibcon#enter sib2, iclass 37, count 0 2006.285.07:55:10.00#ibcon#flushed, iclass 37, count 0 2006.285.07:55:10.00#ibcon#about to write, iclass 37, count 0 2006.285.07:55:10.00#ibcon#wrote, iclass 37, count 0 2006.285.07:55:10.00#ibcon#about to read 3, iclass 37, count 0 2006.285.07:55:10.03#ibcon#read 3, iclass 37, count 0 2006.285.07:55:10.03#ibcon#about to read 4, iclass 37, count 0 2006.285.07:55:10.03#ibcon#read 4, iclass 37, count 0 2006.285.07:55:10.03#ibcon#about to read 5, iclass 37, count 0 2006.285.07:55:10.03#ibcon#read 5, iclass 37, count 0 2006.285.07:55:10.03#ibcon#about to read 6, iclass 37, count 0 2006.285.07:55:10.03#ibcon#read 6, iclass 37, count 0 2006.285.07:55:10.03#ibcon#end of sib2, iclass 37, count 0 2006.285.07:55:10.03#ibcon#*after write, iclass 37, count 0 2006.285.07:55:10.03#ibcon#*before return 0, iclass 37, count 0 2006.285.07:55:10.03#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:55:10.03#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.07:55:10.03#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.07:55:10.03#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.07:55:10.03$vck44/vblo=3,649.99 2006.285.07:55:10.03#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.07:55:10.03#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.07:55:10.03#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:10.03#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:55:10.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:55:10.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:55:10.03#ibcon#enter wrdev, iclass 39, count 0 2006.285.07:55:10.03#ibcon#first serial, iclass 39, count 0 2006.285.07:55:10.03#ibcon#enter sib2, iclass 39, count 0 2006.285.07:55:10.03#ibcon#flushed, iclass 39, count 0 2006.285.07:55:10.03#ibcon#about to write, iclass 39, count 0 2006.285.07:55:10.03#ibcon#wrote, iclass 39, count 0 2006.285.07:55:10.03#ibcon#about to read 3, iclass 39, count 0 2006.285.07:55:10.05#ibcon#read 3, iclass 39, count 0 2006.285.07:55:10.05#ibcon#about to read 4, iclass 39, count 0 2006.285.07:55:10.05#ibcon#read 4, iclass 39, count 0 2006.285.07:55:10.05#ibcon#about to read 5, iclass 39, count 0 2006.285.07:55:10.05#ibcon#read 5, iclass 39, count 0 2006.285.07:55:10.05#ibcon#about to read 6, iclass 39, count 0 2006.285.07:55:10.05#ibcon#read 6, iclass 39, count 0 2006.285.07:55:10.05#ibcon#end of sib2, iclass 39, count 0 2006.285.07:55:10.05#ibcon#*mode == 0, iclass 39, count 0 2006.285.07:55:10.05#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.07:55:10.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.07:55:10.05#ibcon#*before write, iclass 39, count 0 2006.285.07:55:10.05#ibcon#enter sib2, iclass 39, count 0 2006.285.07:55:10.05#ibcon#flushed, iclass 39, count 0 2006.285.07:55:10.05#ibcon#about to write, iclass 39, count 0 2006.285.07:55:10.05#ibcon#wrote, iclass 39, count 0 2006.285.07:55:10.05#ibcon#about to read 3, iclass 39, count 0 2006.285.07:55:10.09#ibcon#read 3, iclass 39, count 0 2006.285.07:55:10.09#ibcon#about to read 4, iclass 39, count 0 2006.285.07:55:10.09#ibcon#read 4, iclass 39, count 0 2006.285.07:55:10.09#ibcon#about to read 5, iclass 39, count 0 2006.285.07:55:10.09#ibcon#read 5, iclass 39, count 0 2006.285.07:55:10.09#ibcon#about to read 6, iclass 39, count 0 2006.285.07:55:10.09#ibcon#read 6, iclass 39, count 0 2006.285.07:55:10.09#ibcon#end of sib2, iclass 39, count 0 2006.285.07:55:10.09#ibcon#*after write, iclass 39, count 0 2006.285.07:55:10.09#ibcon#*before return 0, iclass 39, count 0 2006.285.07:55:10.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:55:10.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.07:55:10.09#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.07:55:10.09#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.07:55:10.09$vck44/vb=3,4 2006.285.07:55:10.09#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.07:55:10.09#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.07:55:10.09#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:10.09#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:55:10.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:55:10.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:55:10.15#ibcon#enter wrdev, iclass 3, count 2 2006.285.07:55:10.15#ibcon#first serial, iclass 3, count 2 2006.285.07:55:10.15#ibcon#enter sib2, iclass 3, count 2 2006.285.07:55:10.15#ibcon#flushed, iclass 3, count 2 2006.285.07:55:10.15#ibcon#about to write, iclass 3, count 2 2006.285.07:55:10.15#ibcon#wrote, iclass 3, count 2 2006.285.07:55:10.15#ibcon#about to read 3, iclass 3, count 2 2006.285.07:55:10.17#ibcon#read 3, iclass 3, count 2 2006.285.07:55:10.17#ibcon#about to read 4, iclass 3, count 2 2006.285.07:55:10.17#ibcon#read 4, iclass 3, count 2 2006.285.07:55:10.17#ibcon#about to read 5, iclass 3, count 2 2006.285.07:55:10.17#ibcon#read 5, iclass 3, count 2 2006.285.07:55:10.17#ibcon#about to read 6, iclass 3, count 2 2006.285.07:55:10.17#ibcon#read 6, iclass 3, count 2 2006.285.07:55:10.17#ibcon#end of sib2, iclass 3, count 2 2006.285.07:55:10.17#ibcon#*mode == 0, iclass 3, count 2 2006.285.07:55:10.17#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.07:55:10.17#ibcon#[27=AT03-04\r\n] 2006.285.07:55:10.17#ibcon#*before write, iclass 3, count 2 2006.285.07:55:10.17#ibcon#enter sib2, iclass 3, count 2 2006.285.07:55:10.17#ibcon#flushed, iclass 3, count 2 2006.285.07:55:10.17#ibcon#about to write, iclass 3, count 2 2006.285.07:55:10.17#ibcon#wrote, iclass 3, count 2 2006.285.07:55:10.17#ibcon#about to read 3, iclass 3, count 2 2006.285.07:55:10.20#ibcon#read 3, iclass 3, count 2 2006.285.07:55:10.20#ibcon#about to read 4, iclass 3, count 2 2006.285.07:55:10.20#ibcon#read 4, iclass 3, count 2 2006.285.07:55:10.20#ibcon#about to read 5, iclass 3, count 2 2006.285.07:55:10.20#ibcon#read 5, iclass 3, count 2 2006.285.07:55:10.20#ibcon#about to read 6, iclass 3, count 2 2006.285.07:55:10.20#ibcon#read 6, iclass 3, count 2 2006.285.07:55:10.20#ibcon#end of sib2, iclass 3, count 2 2006.285.07:55:10.20#ibcon#*after write, iclass 3, count 2 2006.285.07:55:10.20#ibcon#*before return 0, iclass 3, count 2 2006.285.07:55:10.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:55:10.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.07:55:10.20#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.07:55:10.20#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:10.20#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:55:10.32#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:55:10.32#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:55:10.32#ibcon#enter wrdev, iclass 3, count 0 2006.285.07:55:10.32#ibcon#first serial, iclass 3, count 0 2006.285.07:55:10.32#ibcon#enter sib2, iclass 3, count 0 2006.285.07:55:10.32#ibcon#flushed, iclass 3, count 0 2006.285.07:55:10.32#ibcon#about to write, iclass 3, count 0 2006.285.07:55:10.32#ibcon#wrote, iclass 3, count 0 2006.285.07:55:10.32#ibcon#about to read 3, iclass 3, count 0 2006.285.07:55:10.34#ibcon#read 3, iclass 3, count 0 2006.285.07:55:10.34#ibcon#about to read 4, iclass 3, count 0 2006.285.07:55:10.34#ibcon#read 4, iclass 3, count 0 2006.285.07:55:10.34#ibcon#about to read 5, iclass 3, count 0 2006.285.07:55:10.34#ibcon#read 5, iclass 3, count 0 2006.285.07:55:10.34#ibcon#about to read 6, iclass 3, count 0 2006.285.07:55:10.34#ibcon#read 6, iclass 3, count 0 2006.285.07:55:10.34#ibcon#end of sib2, iclass 3, count 0 2006.285.07:55:10.34#ibcon#*mode == 0, iclass 3, count 0 2006.285.07:55:10.34#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.07:55:10.34#ibcon#[27=USB\r\n] 2006.285.07:55:10.34#ibcon#*before write, iclass 3, count 0 2006.285.07:55:10.34#ibcon#enter sib2, iclass 3, count 0 2006.285.07:55:10.34#ibcon#flushed, iclass 3, count 0 2006.285.07:55:10.34#ibcon#about to write, iclass 3, count 0 2006.285.07:55:10.34#ibcon#wrote, iclass 3, count 0 2006.285.07:55:10.34#ibcon#about to read 3, iclass 3, count 0 2006.285.07:55:10.37#ibcon#read 3, iclass 3, count 0 2006.285.07:55:10.37#ibcon#about to read 4, iclass 3, count 0 2006.285.07:55:10.37#ibcon#read 4, iclass 3, count 0 2006.285.07:55:10.37#ibcon#about to read 5, iclass 3, count 0 2006.285.07:55:10.37#ibcon#read 5, iclass 3, count 0 2006.285.07:55:10.37#ibcon#about to read 6, iclass 3, count 0 2006.285.07:55:10.37#ibcon#read 6, iclass 3, count 0 2006.285.07:55:10.37#ibcon#end of sib2, iclass 3, count 0 2006.285.07:55:10.37#ibcon#*after write, iclass 3, count 0 2006.285.07:55:10.37#ibcon#*before return 0, iclass 3, count 0 2006.285.07:55:10.37#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:55:10.37#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.07:55:10.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.07:55:10.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.07:55:10.37$vck44/vblo=4,679.99 2006.285.07:55:10.37#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.07:55:10.37#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.07:55:10.37#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:10.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:55:10.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:55:10.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:55:10.37#ibcon#enter wrdev, iclass 5, count 0 2006.285.07:55:10.37#ibcon#first serial, iclass 5, count 0 2006.285.07:55:10.37#ibcon#enter sib2, iclass 5, count 0 2006.285.07:55:10.37#ibcon#flushed, iclass 5, count 0 2006.285.07:55:10.37#ibcon#about to write, iclass 5, count 0 2006.285.07:55:10.37#ibcon#wrote, iclass 5, count 0 2006.285.07:55:10.37#ibcon#about to read 3, iclass 5, count 0 2006.285.07:55:10.39#ibcon#read 3, iclass 5, count 0 2006.285.07:55:10.39#ibcon#about to read 4, iclass 5, count 0 2006.285.07:55:10.39#ibcon#read 4, iclass 5, count 0 2006.285.07:55:10.39#ibcon#about to read 5, iclass 5, count 0 2006.285.07:55:10.39#ibcon#read 5, iclass 5, count 0 2006.285.07:55:10.39#ibcon#about to read 6, iclass 5, count 0 2006.285.07:55:10.39#ibcon#read 6, iclass 5, count 0 2006.285.07:55:10.39#ibcon#end of sib2, iclass 5, count 0 2006.285.07:55:10.39#ibcon#*mode == 0, iclass 5, count 0 2006.285.07:55:10.39#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.07:55:10.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.07:55:10.39#ibcon#*before write, iclass 5, count 0 2006.285.07:55:10.39#ibcon#enter sib2, iclass 5, count 0 2006.285.07:55:10.39#ibcon#flushed, iclass 5, count 0 2006.285.07:55:10.39#ibcon#about to write, iclass 5, count 0 2006.285.07:55:10.39#ibcon#wrote, iclass 5, count 0 2006.285.07:55:10.39#ibcon#about to read 3, iclass 5, count 0 2006.285.07:55:10.43#ibcon#read 3, iclass 5, count 0 2006.285.07:55:10.43#ibcon#about to read 4, iclass 5, count 0 2006.285.07:55:10.43#ibcon#read 4, iclass 5, count 0 2006.285.07:55:10.43#ibcon#about to read 5, iclass 5, count 0 2006.285.07:55:10.43#ibcon#read 5, iclass 5, count 0 2006.285.07:55:10.43#ibcon#about to read 6, iclass 5, count 0 2006.285.07:55:10.43#ibcon#read 6, iclass 5, count 0 2006.285.07:55:10.43#ibcon#end of sib2, iclass 5, count 0 2006.285.07:55:10.43#ibcon#*after write, iclass 5, count 0 2006.285.07:55:10.43#ibcon#*before return 0, iclass 5, count 0 2006.285.07:55:10.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:55:10.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.07:55:10.43#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.07:55:10.43#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.07:55:10.43$vck44/vb=4,5 2006.285.07:55:10.43#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.07:55:10.43#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.07:55:10.43#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:10.43#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:55:10.49#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:55:10.49#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:55:10.49#ibcon#enter wrdev, iclass 7, count 2 2006.285.07:55:10.49#ibcon#first serial, iclass 7, count 2 2006.285.07:55:10.49#ibcon#enter sib2, iclass 7, count 2 2006.285.07:55:10.49#ibcon#flushed, iclass 7, count 2 2006.285.07:55:10.49#ibcon#about to write, iclass 7, count 2 2006.285.07:55:10.49#ibcon#wrote, iclass 7, count 2 2006.285.07:55:10.49#ibcon#about to read 3, iclass 7, count 2 2006.285.07:55:10.51#ibcon#read 3, iclass 7, count 2 2006.285.07:55:10.51#ibcon#about to read 4, iclass 7, count 2 2006.285.07:55:10.51#ibcon#read 4, iclass 7, count 2 2006.285.07:55:10.51#ibcon#about to read 5, iclass 7, count 2 2006.285.07:55:10.51#ibcon#read 5, iclass 7, count 2 2006.285.07:55:10.51#ibcon#about to read 6, iclass 7, count 2 2006.285.07:55:10.51#ibcon#read 6, iclass 7, count 2 2006.285.07:55:10.51#ibcon#end of sib2, iclass 7, count 2 2006.285.07:55:10.51#ibcon#*mode == 0, iclass 7, count 2 2006.285.07:55:10.51#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.07:55:10.51#ibcon#[27=AT04-05\r\n] 2006.285.07:55:10.51#ibcon#*before write, iclass 7, count 2 2006.285.07:55:10.51#ibcon#enter sib2, iclass 7, count 2 2006.285.07:55:10.51#ibcon#flushed, iclass 7, count 2 2006.285.07:55:10.51#ibcon#about to write, iclass 7, count 2 2006.285.07:55:10.51#ibcon#wrote, iclass 7, count 2 2006.285.07:55:10.51#ibcon#about to read 3, iclass 7, count 2 2006.285.07:55:10.54#ibcon#read 3, iclass 7, count 2 2006.285.07:55:10.54#ibcon#about to read 4, iclass 7, count 2 2006.285.07:55:10.54#ibcon#read 4, iclass 7, count 2 2006.285.07:55:10.54#ibcon#about to read 5, iclass 7, count 2 2006.285.07:55:10.54#ibcon#read 5, iclass 7, count 2 2006.285.07:55:10.54#ibcon#about to read 6, iclass 7, count 2 2006.285.07:55:10.54#ibcon#read 6, iclass 7, count 2 2006.285.07:55:10.54#ibcon#end of sib2, iclass 7, count 2 2006.285.07:55:10.54#ibcon#*after write, iclass 7, count 2 2006.285.07:55:10.54#ibcon#*before return 0, iclass 7, count 2 2006.285.07:55:10.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:55:10.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.07:55:10.54#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.07:55:10.54#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:10.54#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:55:10.66#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:55:10.66#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:55:10.66#ibcon#enter wrdev, iclass 7, count 0 2006.285.07:55:10.66#ibcon#first serial, iclass 7, count 0 2006.285.07:55:10.66#ibcon#enter sib2, iclass 7, count 0 2006.285.07:55:10.66#ibcon#flushed, iclass 7, count 0 2006.285.07:55:10.66#ibcon#about to write, iclass 7, count 0 2006.285.07:55:10.66#ibcon#wrote, iclass 7, count 0 2006.285.07:55:10.66#ibcon#about to read 3, iclass 7, count 0 2006.285.07:55:10.68#ibcon#read 3, iclass 7, count 0 2006.285.07:55:10.68#ibcon#about to read 4, iclass 7, count 0 2006.285.07:55:10.68#ibcon#read 4, iclass 7, count 0 2006.285.07:55:10.68#ibcon#about to read 5, iclass 7, count 0 2006.285.07:55:10.68#ibcon#read 5, iclass 7, count 0 2006.285.07:55:10.68#ibcon#about to read 6, iclass 7, count 0 2006.285.07:55:10.68#ibcon#read 6, iclass 7, count 0 2006.285.07:55:10.68#ibcon#end of sib2, iclass 7, count 0 2006.285.07:55:10.68#ibcon#*mode == 0, iclass 7, count 0 2006.285.07:55:10.68#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.07:55:10.68#ibcon#[27=USB\r\n] 2006.285.07:55:10.68#ibcon#*before write, iclass 7, count 0 2006.285.07:55:10.68#ibcon#enter sib2, iclass 7, count 0 2006.285.07:55:10.68#ibcon#flushed, iclass 7, count 0 2006.285.07:55:10.68#ibcon#about to write, iclass 7, count 0 2006.285.07:55:10.68#ibcon#wrote, iclass 7, count 0 2006.285.07:55:10.68#ibcon#about to read 3, iclass 7, count 0 2006.285.07:55:10.71#ibcon#read 3, iclass 7, count 0 2006.285.07:55:10.71#ibcon#about to read 4, iclass 7, count 0 2006.285.07:55:10.71#ibcon#read 4, iclass 7, count 0 2006.285.07:55:10.71#ibcon#about to read 5, iclass 7, count 0 2006.285.07:55:10.71#ibcon#read 5, iclass 7, count 0 2006.285.07:55:10.71#ibcon#about to read 6, iclass 7, count 0 2006.285.07:55:10.71#ibcon#read 6, iclass 7, count 0 2006.285.07:55:10.71#ibcon#end of sib2, iclass 7, count 0 2006.285.07:55:10.71#ibcon#*after write, iclass 7, count 0 2006.285.07:55:10.71#ibcon#*before return 0, iclass 7, count 0 2006.285.07:55:10.71#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:55:10.71#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.07:55:10.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.07:55:10.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.07:55:10.71$vck44/vblo=5,709.99 2006.285.07:55:10.71#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.07:55:10.71#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.07:55:10.71#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:10.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:55:10.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:55:10.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:55:10.71#ibcon#enter wrdev, iclass 11, count 0 2006.285.07:55:10.71#ibcon#first serial, iclass 11, count 0 2006.285.07:55:10.71#ibcon#enter sib2, iclass 11, count 0 2006.285.07:55:10.71#ibcon#flushed, iclass 11, count 0 2006.285.07:55:10.71#ibcon#about to write, iclass 11, count 0 2006.285.07:55:10.71#ibcon#wrote, iclass 11, count 0 2006.285.07:55:10.71#ibcon#about to read 3, iclass 11, count 0 2006.285.07:55:10.73#ibcon#read 3, iclass 11, count 0 2006.285.07:55:10.73#ibcon#about to read 4, iclass 11, count 0 2006.285.07:55:10.73#ibcon#read 4, iclass 11, count 0 2006.285.07:55:10.73#ibcon#about to read 5, iclass 11, count 0 2006.285.07:55:10.73#ibcon#read 5, iclass 11, count 0 2006.285.07:55:10.73#ibcon#about to read 6, iclass 11, count 0 2006.285.07:55:10.73#ibcon#read 6, iclass 11, count 0 2006.285.07:55:10.73#ibcon#end of sib2, iclass 11, count 0 2006.285.07:55:10.73#ibcon#*mode == 0, iclass 11, count 0 2006.285.07:55:10.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.07:55:10.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.07:55:10.73#ibcon#*before write, iclass 11, count 0 2006.285.07:55:10.73#ibcon#enter sib2, iclass 11, count 0 2006.285.07:55:10.73#ibcon#flushed, iclass 11, count 0 2006.285.07:55:10.73#ibcon#about to write, iclass 11, count 0 2006.285.07:55:10.73#ibcon#wrote, iclass 11, count 0 2006.285.07:55:10.73#ibcon#about to read 3, iclass 11, count 0 2006.285.07:55:10.77#ibcon#read 3, iclass 11, count 0 2006.285.07:55:10.77#ibcon#about to read 4, iclass 11, count 0 2006.285.07:55:10.77#ibcon#read 4, iclass 11, count 0 2006.285.07:55:10.77#ibcon#about to read 5, iclass 11, count 0 2006.285.07:55:10.77#ibcon#read 5, iclass 11, count 0 2006.285.07:55:10.77#ibcon#about to read 6, iclass 11, count 0 2006.285.07:55:10.77#ibcon#read 6, iclass 11, count 0 2006.285.07:55:10.77#ibcon#end of sib2, iclass 11, count 0 2006.285.07:55:10.77#ibcon#*after write, iclass 11, count 0 2006.285.07:55:10.77#ibcon#*before return 0, iclass 11, count 0 2006.285.07:55:10.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:55:10.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.07:55:10.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.07:55:10.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.07:55:10.77$vck44/vb=5,4 2006.285.07:55:10.77#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.07:55:10.77#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.07:55:10.77#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:10.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:55:10.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:55:10.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:55:10.83#ibcon#enter wrdev, iclass 13, count 2 2006.285.07:55:10.83#ibcon#first serial, iclass 13, count 2 2006.285.07:55:10.83#ibcon#enter sib2, iclass 13, count 2 2006.285.07:55:10.83#ibcon#flushed, iclass 13, count 2 2006.285.07:55:10.83#ibcon#about to write, iclass 13, count 2 2006.285.07:55:10.83#ibcon#wrote, iclass 13, count 2 2006.285.07:55:10.83#ibcon#about to read 3, iclass 13, count 2 2006.285.07:55:10.85#ibcon#read 3, iclass 13, count 2 2006.285.07:55:10.85#ibcon#about to read 4, iclass 13, count 2 2006.285.07:55:10.85#ibcon#read 4, iclass 13, count 2 2006.285.07:55:10.85#ibcon#about to read 5, iclass 13, count 2 2006.285.07:55:10.85#ibcon#read 5, iclass 13, count 2 2006.285.07:55:10.85#ibcon#about to read 6, iclass 13, count 2 2006.285.07:55:10.85#ibcon#read 6, iclass 13, count 2 2006.285.07:55:10.85#ibcon#end of sib2, iclass 13, count 2 2006.285.07:55:10.85#ibcon#*mode == 0, iclass 13, count 2 2006.285.07:55:10.85#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.07:55:10.85#ibcon#[27=AT05-04\r\n] 2006.285.07:55:10.85#ibcon#*before write, iclass 13, count 2 2006.285.07:55:10.85#ibcon#enter sib2, iclass 13, count 2 2006.285.07:55:10.85#ibcon#flushed, iclass 13, count 2 2006.285.07:55:10.85#ibcon#about to write, iclass 13, count 2 2006.285.07:55:10.85#ibcon#wrote, iclass 13, count 2 2006.285.07:55:10.85#ibcon#about to read 3, iclass 13, count 2 2006.285.07:55:10.88#ibcon#read 3, iclass 13, count 2 2006.285.07:55:10.88#ibcon#about to read 4, iclass 13, count 2 2006.285.07:55:10.88#ibcon#read 4, iclass 13, count 2 2006.285.07:55:10.88#ibcon#about to read 5, iclass 13, count 2 2006.285.07:55:10.88#ibcon#read 5, iclass 13, count 2 2006.285.07:55:10.88#ibcon#about to read 6, iclass 13, count 2 2006.285.07:55:10.88#ibcon#read 6, iclass 13, count 2 2006.285.07:55:10.88#ibcon#end of sib2, iclass 13, count 2 2006.285.07:55:10.88#ibcon#*after write, iclass 13, count 2 2006.285.07:55:10.88#ibcon#*before return 0, iclass 13, count 2 2006.285.07:55:10.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:55:10.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.07:55:10.88#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.07:55:10.88#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:10.88#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:55:11.00#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:55:11.00#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:55:11.00#ibcon#enter wrdev, iclass 13, count 0 2006.285.07:55:11.00#ibcon#first serial, iclass 13, count 0 2006.285.07:55:11.00#ibcon#enter sib2, iclass 13, count 0 2006.285.07:55:11.00#ibcon#flushed, iclass 13, count 0 2006.285.07:55:11.00#ibcon#about to write, iclass 13, count 0 2006.285.07:55:11.00#ibcon#wrote, iclass 13, count 0 2006.285.07:55:11.00#ibcon#about to read 3, iclass 13, count 0 2006.285.07:55:11.02#ibcon#read 3, iclass 13, count 0 2006.285.07:55:11.02#ibcon#about to read 4, iclass 13, count 0 2006.285.07:55:11.02#ibcon#read 4, iclass 13, count 0 2006.285.07:55:11.02#ibcon#about to read 5, iclass 13, count 0 2006.285.07:55:11.02#ibcon#read 5, iclass 13, count 0 2006.285.07:55:11.02#ibcon#about to read 6, iclass 13, count 0 2006.285.07:55:11.02#ibcon#read 6, iclass 13, count 0 2006.285.07:55:11.02#ibcon#end of sib2, iclass 13, count 0 2006.285.07:55:11.02#ibcon#*mode == 0, iclass 13, count 0 2006.285.07:55:11.02#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.07:55:11.02#ibcon#[27=USB\r\n] 2006.285.07:55:11.02#ibcon#*before write, iclass 13, count 0 2006.285.07:55:11.02#ibcon#enter sib2, iclass 13, count 0 2006.285.07:55:11.02#ibcon#flushed, iclass 13, count 0 2006.285.07:55:11.02#ibcon#about to write, iclass 13, count 0 2006.285.07:55:11.02#ibcon#wrote, iclass 13, count 0 2006.285.07:55:11.02#ibcon#about to read 3, iclass 13, count 0 2006.285.07:55:11.05#ibcon#read 3, iclass 13, count 0 2006.285.07:55:11.05#ibcon#about to read 4, iclass 13, count 0 2006.285.07:55:11.05#ibcon#read 4, iclass 13, count 0 2006.285.07:55:11.05#ibcon#about to read 5, iclass 13, count 0 2006.285.07:55:11.05#ibcon#read 5, iclass 13, count 0 2006.285.07:55:11.05#ibcon#about to read 6, iclass 13, count 0 2006.285.07:55:11.05#ibcon#read 6, iclass 13, count 0 2006.285.07:55:11.05#ibcon#end of sib2, iclass 13, count 0 2006.285.07:55:11.05#ibcon#*after write, iclass 13, count 0 2006.285.07:55:11.05#ibcon#*before return 0, iclass 13, count 0 2006.285.07:55:11.05#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:55:11.05#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.07:55:11.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.07:55:11.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.07:55:11.05$vck44/vblo=6,719.99 2006.285.07:55:11.05#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.07:55:11.05#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.07:55:11.05#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:11.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:55:11.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:55:11.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:55:11.05#ibcon#enter wrdev, iclass 15, count 0 2006.285.07:55:11.05#ibcon#first serial, iclass 15, count 0 2006.285.07:55:11.05#ibcon#enter sib2, iclass 15, count 0 2006.285.07:55:11.05#ibcon#flushed, iclass 15, count 0 2006.285.07:55:11.05#ibcon#about to write, iclass 15, count 0 2006.285.07:55:11.05#ibcon#wrote, iclass 15, count 0 2006.285.07:55:11.05#ibcon#about to read 3, iclass 15, count 0 2006.285.07:55:11.07#ibcon#read 3, iclass 15, count 0 2006.285.07:55:11.07#ibcon#about to read 4, iclass 15, count 0 2006.285.07:55:11.07#ibcon#read 4, iclass 15, count 0 2006.285.07:55:11.07#ibcon#about to read 5, iclass 15, count 0 2006.285.07:55:11.07#ibcon#read 5, iclass 15, count 0 2006.285.07:55:11.07#ibcon#about to read 6, iclass 15, count 0 2006.285.07:55:11.07#ibcon#read 6, iclass 15, count 0 2006.285.07:55:11.07#ibcon#end of sib2, iclass 15, count 0 2006.285.07:55:11.07#ibcon#*mode == 0, iclass 15, count 0 2006.285.07:55:11.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.07:55:11.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.07:55:11.07#ibcon#*before write, iclass 15, count 0 2006.285.07:55:11.07#ibcon#enter sib2, iclass 15, count 0 2006.285.07:55:11.07#ibcon#flushed, iclass 15, count 0 2006.285.07:55:11.07#ibcon#about to write, iclass 15, count 0 2006.285.07:55:11.07#ibcon#wrote, iclass 15, count 0 2006.285.07:55:11.07#ibcon#about to read 3, iclass 15, count 0 2006.285.07:55:11.11#ibcon#read 3, iclass 15, count 0 2006.285.07:55:11.11#ibcon#about to read 4, iclass 15, count 0 2006.285.07:55:11.11#ibcon#read 4, iclass 15, count 0 2006.285.07:55:11.11#ibcon#about to read 5, iclass 15, count 0 2006.285.07:55:11.11#ibcon#read 5, iclass 15, count 0 2006.285.07:55:11.11#ibcon#about to read 6, iclass 15, count 0 2006.285.07:55:11.11#ibcon#read 6, iclass 15, count 0 2006.285.07:55:11.11#ibcon#end of sib2, iclass 15, count 0 2006.285.07:55:11.11#ibcon#*after write, iclass 15, count 0 2006.285.07:55:11.11#ibcon#*before return 0, iclass 15, count 0 2006.285.07:55:11.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:55:11.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.07:55:11.11#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.07:55:11.11#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.07:55:11.11$vck44/vb=6,3 2006.285.07:55:11.11#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.07:55:11.11#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.07:55:11.11#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:11.11#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:55:11.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:55:11.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:55:11.17#ibcon#enter wrdev, iclass 17, count 2 2006.285.07:55:11.17#ibcon#first serial, iclass 17, count 2 2006.285.07:55:11.17#ibcon#enter sib2, iclass 17, count 2 2006.285.07:55:11.17#ibcon#flushed, iclass 17, count 2 2006.285.07:55:11.17#ibcon#about to write, iclass 17, count 2 2006.285.07:55:11.17#ibcon#wrote, iclass 17, count 2 2006.285.07:55:11.17#ibcon#about to read 3, iclass 17, count 2 2006.285.07:55:11.19#ibcon#read 3, iclass 17, count 2 2006.285.07:55:11.19#ibcon#about to read 4, iclass 17, count 2 2006.285.07:55:11.19#ibcon#read 4, iclass 17, count 2 2006.285.07:55:11.19#ibcon#about to read 5, iclass 17, count 2 2006.285.07:55:11.19#ibcon#read 5, iclass 17, count 2 2006.285.07:55:11.19#ibcon#about to read 6, iclass 17, count 2 2006.285.07:55:11.19#ibcon#read 6, iclass 17, count 2 2006.285.07:55:11.19#ibcon#end of sib2, iclass 17, count 2 2006.285.07:55:11.19#ibcon#*mode == 0, iclass 17, count 2 2006.285.07:55:11.19#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.07:55:11.19#ibcon#[27=AT06-03\r\n] 2006.285.07:55:11.19#ibcon#*before write, iclass 17, count 2 2006.285.07:55:11.19#ibcon#enter sib2, iclass 17, count 2 2006.285.07:55:11.19#ibcon#flushed, iclass 17, count 2 2006.285.07:55:11.19#ibcon#about to write, iclass 17, count 2 2006.285.07:55:11.19#ibcon#wrote, iclass 17, count 2 2006.285.07:55:11.19#ibcon#about to read 3, iclass 17, count 2 2006.285.07:55:11.22#ibcon#read 3, iclass 17, count 2 2006.285.07:55:11.22#ibcon#about to read 4, iclass 17, count 2 2006.285.07:55:11.22#ibcon#read 4, iclass 17, count 2 2006.285.07:55:11.22#ibcon#about to read 5, iclass 17, count 2 2006.285.07:55:11.22#ibcon#read 5, iclass 17, count 2 2006.285.07:55:11.22#ibcon#about to read 6, iclass 17, count 2 2006.285.07:55:11.22#ibcon#read 6, iclass 17, count 2 2006.285.07:55:11.22#ibcon#end of sib2, iclass 17, count 2 2006.285.07:55:11.22#ibcon#*after write, iclass 17, count 2 2006.285.07:55:11.22#ibcon#*before return 0, iclass 17, count 2 2006.285.07:55:11.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:55:11.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.07:55:11.22#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.07:55:11.22#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:11.22#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:55:11.34#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:55:11.34#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:55:11.34#ibcon#enter wrdev, iclass 17, count 0 2006.285.07:55:11.34#ibcon#first serial, iclass 17, count 0 2006.285.07:55:11.34#ibcon#enter sib2, iclass 17, count 0 2006.285.07:55:11.34#ibcon#flushed, iclass 17, count 0 2006.285.07:55:11.34#ibcon#about to write, iclass 17, count 0 2006.285.07:55:11.34#ibcon#wrote, iclass 17, count 0 2006.285.07:55:11.34#ibcon#about to read 3, iclass 17, count 0 2006.285.07:55:11.36#ibcon#read 3, iclass 17, count 0 2006.285.07:55:11.36#ibcon#about to read 4, iclass 17, count 0 2006.285.07:55:11.36#ibcon#read 4, iclass 17, count 0 2006.285.07:55:11.36#ibcon#about to read 5, iclass 17, count 0 2006.285.07:55:11.36#ibcon#read 5, iclass 17, count 0 2006.285.07:55:11.36#ibcon#about to read 6, iclass 17, count 0 2006.285.07:55:11.36#ibcon#read 6, iclass 17, count 0 2006.285.07:55:11.36#ibcon#end of sib2, iclass 17, count 0 2006.285.07:55:11.36#ibcon#*mode == 0, iclass 17, count 0 2006.285.07:55:11.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.07:55:11.36#ibcon#[27=USB\r\n] 2006.285.07:55:11.36#ibcon#*before write, iclass 17, count 0 2006.285.07:55:11.36#ibcon#enter sib2, iclass 17, count 0 2006.285.07:55:11.36#ibcon#flushed, iclass 17, count 0 2006.285.07:55:11.36#ibcon#about to write, iclass 17, count 0 2006.285.07:55:11.36#ibcon#wrote, iclass 17, count 0 2006.285.07:55:11.36#ibcon#about to read 3, iclass 17, count 0 2006.285.07:55:11.39#ibcon#read 3, iclass 17, count 0 2006.285.07:55:11.39#ibcon#about to read 4, iclass 17, count 0 2006.285.07:55:11.39#ibcon#read 4, iclass 17, count 0 2006.285.07:55:11.39#ibcon#about to read 5, iclass 17, count 0 2006.285.07:55:11.39#ibcon#read 5, iclass 17, count 0 2006.285.07:55:11.39#ibcon#about to read 6, iclass 17, count 0 2006.285.07:55:11.39#ibcon#read 6, iclass 17, count 0 2006.285.07:55:11.39#ibcon#end of sib2, iclass 17, count 0 2006.285.07:55:11.39#ibcon#*after write, iclass 17, count 0 2006.285.07:55:11.39#ibcon#*before return 0, iclass 17, count 0 2006.285.07:55:11.39#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:55:11.39#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.07:55:11.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.07:55:11.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.07:55:11.39$vck44/vblo=7,734.99 2006.285.07:55:11.39#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.07:55:11.39#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.07:55:11.39#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:11.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:55:11.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:55:11.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:55:11.39#ibcon#enter wrdev, iclass 19, count 0 2006.285.07:55:11.39#ibcon#first serial, iclass 19, count 0 2006.285.07:55:11.39#ibcon#enter sib2, iclass 19, count 0 2006.285.07:55:11.39#ibcon#flushed, iclass 19, count 0 2006.285.07:55:11.39#ibcon#about to write, iclass 19, count 0 2006.285.07:55:11.39#ibcon#wrote, iclass 19, count 0 2006.285.07:55:11.39#ibcon#about to read 3, iclass 19, count 0 2006.285.07:55:11.41#ibcon#read 3, iclass 19, count 0 2006.285.07:55:11.41#ibcon#about to read 4, iclass 19, count 0 2006.285.07:55:11.41#ibcon#read 4, iclass 19, count 0 2006.285.07:55:11.41#ibcon#about to read 5, iclass 19, count 0 2006.285.07:55:11.41#ibcon#read 5, iclass 19, count 0 2006.285.07:55:11.41#ibcon#about to read 6, iclass 19, count 0 2006.285.07:55:11.41#ibcon#read 6, iclass 19, count 0 2006.285.07:55:11.41#ibcon#end of sib2, iclass 19, count 0 2006.285.07:55:11.41#ibcon#*mode == 0, iclass 19, count 0 2006.285.07:55:11.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.07:55:11.41#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.07:55:11.41#ibcon#*before write, iclass 19, count 0 2006.285.07:55:11.41#ibcon#enter sib2, iclass 19, count 0 2006.285.07:55:11.41#ibcon#flushed, iclass 19, count 0 2006.285.07:55:11.41#ibcon#about to write, iclass 19, count 0 2006.285.07:55:11.41#ibcon#wrote, iclass 19, count 0 2006.285.07:55:11.41#ibcon#about to read 3, iclass 19, count 0 2006.285.07:55:11.45#ibcon#read 3, iclass 19, count 0 2006.285.07:55:11.45#ibcon#about to read 4, iclass 19, count 0 2006.285.07:55:11.45#ibcon#read 4, iclass 19, count 0 2006.285.07:55:11.45#ibcon#about to read 5, iclass 19, count 0 2006.285.07:55:11.45#ibcon#read 5, iclass 19, count 0 2006.285.07:55:11.45#ibcon#about to read 6, iclass 19, count 0 2006.285.07:55:11.45#ibcon#read 6, iclass 19, count 0 2006.285.07:55:11.45#ibcon#end of sib2, iclass 19, count 0 2006.285.07:55:11.45#ibcon#*after write, iclass 19, count 0 2006.285.07:55:11.45#ibcon#*before return 0, iclass 19, count 0 2006.285.07:55:11.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:55:11.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.07:55:11.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.07:55:11.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.07:55:11.45$vck44/vb=7,4 2006.285.07:55:11.45#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.07:55:11.45#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.07:55:11.45#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:11.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:55:11.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:55:11.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:55:11.51#ibcon#enter wrdev, iclass 21, count 2 2006.285.07:55:11.51#ibcon#first serial, iclass 21, count 2 2006.285.07:55:11.51#ibcon#enter sib2, iclass 21, count 2 2006.285.07:55:11.51#ibcon#flushed, iclass 21, count 2 2006.285.07:55:11.51#ibcon#about to write, iclass 21, count 2 2006.285.07:55:11.51#ibcon#wrote, iclass 21, count 2 2006.285.07:55:11.51#ibcon#about to read 3, iclass 21, count 2 2006.285.07:55:11.53#ibcon#read 3, iclass 21, count 2 2006.285.07:55:11.53#ibcon#about to read 4, iclass 21, count 2 2006.285.07:55:11.53#ibcon#read 4, iclass 21, count 2 2006.285.07:55:11.53#ibcon#about to read 5, iclass 21, count 2 2006.285.07:55:11.53#ibcon#read 5, iclass 21, count 2 2006.285.07:55:11.53#ibcon#about to read 6, iclass 21, count 2 2006.285.07:55:11.53#ibcon#read 6, iclass 21, count 2 2006.285.07:55:11.53#ibcon#end of sib2, iclass 21, count 2 2006.285.07:55:11.53#ibcon#*mode == 0, iclass 21, count 2 2006.285.07:55:11.53#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.07:55:11.53#ibcon#[27=AT07-04\r\n] 2006.285.07:55:11.53#ibcon#*before write, iclass 21, count 2 2006.285.07:55:11.53#ibcon#enter sib2, iclass 21, count 2 2006.285.07:55:11.53#ibcon#flushed, iclass 21, count 2 2006.285.07:55:11.53#ibcon#about to write, iclass 21, count 2 2006.285.07:55:11.53#ibcon#wrote, iclass 21, count 2 2006.285.07:55:11.53#ibcon#about to read 3, iclass 21, count 2 2006.285.07:55:11.56#ibcon#read 3, iclass 21, count 2 2006.285.07:55:11.56#ibcon#about to read 4, iclass 21, count 2 2006.285.07:55:11.56#ibcon#read 4, iclass 21, count 2 2006.285.07:55:11.56#ibcon#about to read 5, iclass 21, count 2 2006.285.07:55:11.56#ibcon#read 5, iclass 21, count 2 2006.285.07:55:11.56#ibcon#about to read 6, iclass 21, count 2 2006.285.07:55:11.56#ibcon#read 6, iclass 21, count 2 2006.285.07:55:11.56#ibcon#end of sib2, iclass 21, count 2 2006.285.07:55:11.56#ibcon#*after write, iclass 21, count 2 2006.285.07:55:11.56#ibcon#*before return 0, iclass 21, count 2 2006.285.07:55:11.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:55:11.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.07:55:11.56#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.07:55:11.56#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:11.56#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:55:11.68#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:55:11.68#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:55:11.68#ibcon#enter wrdev, iclass 21, count 0 2006.285.07:55:11.68#ibcon#first serial, iclass 21, count 0 2006.285.07:55:11.68#ibcon#enter sib2, iclass 21, count 0 2006.285.07:55:11.68#ibcon#flushed, iclass 21, count 0 2006.285.07:55:11.68#ibcon#about to write, iclass 21, count 0 2006.285.07:55:11.68#ibcon#wrote, iclass 21, count 0 2006.285.07:55:11.68#ibcon#about to read 3, iclass 21, count 0 2006.285.07:55:11.70#ibcon#read 3, iclass 21, count 0 2006.285.07:55:11.70#ibcon#about to read 4, iclass 21, count 0 2006.285.07:55:11.70#ibcon#read 4, iclass 21, count 0 2006.285.07:55:11.70#ibcon#about to read 5, iclass 21, count 0 2006.285.07:55:11.70#ibcon#read 5, iclass 21, count 0 2006.285.07:55:11.70#ibcon#about to read 6, iclass 21, count 0 2006.285.07:55:11.70#ibcon#read 6, iclass 21, count 0 2006.285.07:55:11.70#ibcon#end of sib2, iclass 21, count 0 2006.285.07:55:11.70#ibcon#*mode == 0, iclass 21, count 0 2006.285.07:55:11.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.07:55:11.70#ibcon#[27=USB\r\n] 2006.285.07:55:11.70#ibcon#*before write, iclass 21, count 0 2006.285.07:55:11.70#ibcon#enter sib2, iclass 21, count 0 2006.285.07:55:11.70#ibcon#flushed, iclass 21, count 0 2006.285.07:55:11.70#ibcon#about to write, iclass 21, count 0 2006.285.07:55:11.70#ibcon#wrote, iclass 21, count 0 2006.285.07:55:11.70#ibcon#about to read 3, iclass 21, count 0 2006.285.07:55:11.73#ibcon#read 3, iclass 21, count 0 2006.285.07:55:11.73#ibcon#about to read 4, iclass 21, count 0 2006.285.07:55:11.73#ibcon#read 4, iclass 21, count 0 2006.285.07:55:11.73#ibcon#about to read 5, iclass 21, count 0 2006.285.07:55:11.73#ibcon#read 5, iclass 21, count 0 2006.285.07:55:11.73#ibcon#about to read 6, iclass 21, count 0 2006.285.07:55:11.73#ibcon#read 6, iclass 21, count 0 2006.285.07:55:11.73#ibcon#end of sib2, iclass 21, count 0 2006.285.07:55:11.73#ibcon#*after write, iclass 21, count 0 2006.285.07:55:11.73#ibcon#*before return 0, iclass 21, count 0 2006.285.07:55:11.73#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:55:11.73#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.07:55:11.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.07:55:11.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.07:55:11.73$vck44/vblo=8,744.99 2006.285.07:55:11.73#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.07:55:11.73#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.07:55:11.73#ibcon#ireg 17 cls_cnt 0 2006.285.07:55:11.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:55:11.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:55:11.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:55:11.73#ibcon#enter wrdev, iclass 23, count 0 2006.285.07:55:11.73#ibcon#first serial, iclass 23, count 0 2006.285.07:55:11.73#ibcon#enter sib2, iclass 23, count 0 2006.285.07:55:11.73#ibcon#flushed, iclass 23, count 0 2006.285.07:55:11.73#ibcon#about to write, iclass 23, count 0 2006.285.07:55:11.73#ibcon#wrote, iclass 23, count 0 2006.285.07:55:11.73#ibcon#about to read 3, iclass 23, count 0 2006.285.07:55:11.75#ibcon#read 3, iclass 23, count 0 2006.285.07:55:11.75#ibcon#about to read 4, iclass 23, count 0 2006.285.07:55:11.75#ibcon#read 4, iclass 23, count 0 2006.285.07:55:11.75#ibcon#about to read 5, iclass 23, count 0 2006.285.07:55:11.75#ibcon#read 5, iclass 23, count 0 2006.285.07:55:11.75#ibcon#about to read 6, iclass 23, count 0 2006.285.07:55:11.75#ibcon#read 6, iclass 23, count 0 2006.285.07:55:11.75#ibcon#end of sib2, iclass 23, count 0 2006.285.07:55:11.75#ibcon#*mode == 0, iclass 23, count 0 2006.285.07:55:11.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.07:55:11.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.07:55:11.75#ibcon#*before write, iclass 23, count 0 2006.285.07:55:11.75#ibcon#enter sib2, iclass 23, count 0 2006.285.07:55:11.75#ibcon#flushed, iclass 23, count 0 2006.285.07:55:11.75#ibcon#about to write, iclass 23, count 0 2006.285.07:55:11.75#ibcon#wrote, iclass 23, count 0 2006.285.07:55:11.75#ibcon#about to read 3, iclass 23, count 0 2006.285.07:55:11.79#ibcon#read 3, iclass 23, count 0 2006.285.07:55:11.79#ibcon#about to read 4, iclass 23, count 0 2006.285.07:55:11.79#ibcon#read 4, iclass 23, count 0 2006.285.07:55:11.79#ibcon#about to read 5, iclass 23, count 0 2006.285.07:55:11.79#ibcon#read 5, iclass 23, count 0 2006.285.07:55:11.79#ibcon#about to read 6, iclass 23, count 0 2006.285.07:55:11.79#ibcon#read 6, iclass 23, count 0 2006.285.07:55:11.79#ibcon#end of sib2, iclass 23, count 0 2006.285.07:55:11.79#ibcon#*after write, iclass 23, count 0 2006.285.07:55:11.79#ibcon#*before return 0, iclass 23, count 0 2006.285.07:55:11.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:55:11.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.07:55:11.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.07:55:11.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.07:55:11.79$vck44/vb=8,4 2006.285.07:55:11.79#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.07:55:11.79#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.07:55:11.79#ibcon#ireg 11 cls_cnt 2 2006.285.07:55:11.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:55:11.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:55:11.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:55:11.85#ibcon#enter wrdev, iclass 25, count 2 2006.285.07:55:11.85#ibcon#first serial, iclass 25, count 2 2006.285.07:55:11.85#ibcon#enter sib2, iclass 25, count 2 2006.285.07:55:11.85#ibcon#flushed, iclass 25, count 2 2006.285.07:55:11.85#ibcon#about to write, iclass 25, count 2 2006.285.07:55:11.85#ibcon#wrote, iclass 25, count 2 2006.285.07:55:11.85#ibcon#about to read 3, iclass 25, count 2 2006.285.07:55:11.87#ibcon#read 3, iclass 25, count 2 2006.285.07:55:11.87#ibcon#about to read 4, iclass 25, count 2 2006.285.07:55:11.87#ibcon#read 4, iclass 25, count 2 2006.285.07:55:11.87#ibcon#about to read 5, iclass 25, count 2 2006.285.07:55:11.87#ibcon#read 5, iclass 25, count 2 2006.285.07:55:11.87#ibcon#about to read 6, iclass 25, count 2 2006.285.07:55:11.87#ibcon#read 6, iclass 25, count 2 2006.285.07:55:11.87#ibcon#end of sib2, iclass 25, count 2 2006.285.07:55:11.87#ibcon#*mode == 0, iclass 25, count 2 2006.285.07:55:11.87#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.07:55:11.87#ibcon#[27=AT08-04\r\n] 2006.285.07:55:11.87#ibcon#*before write, iclass 25, count 2 2006.285.07:55:11.87#ibcon#enter sib2, iclass 25, count 2 2006.285.07:55:11.87#ibcon#flushed, iclass 25, count 2 2006.285.07:55:11.87#ibcon#about to write, iclass 25, count 2 2006.285.07:55:11.87#ibcon#wrote, iclass 25, count 2 2006.285.07:55:11.87#ibcon#about to read 3, iclass 25, count 2 2006.285.07:55:11.90#ibcon#read 3, iclass 25, count 2 2006.285.07:55:11.90#ibcon#about to read 4, iclass 25, count 2 2006.285.07:55:11.90#ibcon#read 4, iclass 25, count 2 2006.285.07:55:11.90#ibcon#about to read 5, iclass 25, count 2 2006.285.07:55:11.90#ibcon#read 5, iclass 25, count 2 2006.285.07:55:11.90#ibcon#about to read 6, iclass 25, count 2 2006.285.07:55:11.90#ibcon#read 6, iclass 25, count 2 2006.285.07:55:11.90#ibcon#end of sib2, iclass 25, count 2 2006.285.07:55:11.90#ibcon#*after write, iclass 25, count 2 2006.285.07:55:11.90#ibcon#*before return 0, iclass 25, count 2 2006.285.07:55:11.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:55:11.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.07:55:11.90#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.07:55:11.90#ibcon#ireg 7 cls_cnt 0 2006.285.07:55:11.90#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:55:12.02#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:55:12.02#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:55:12.02#ibcon#enter wrdev, iclass 25, count 0 2006.285.07:55:12.02#ibcon#first serial, iclass 25, count 0 2006.285.07:55:12.02#ibcon#enter sib2, iclass 25, count 0 2006.285.07:55:12.02#ibcon#flushed, iclass 25, count 0 2006.285.07:55:12.02#ibcon#about to write, iclass 25, count 0 2006.285.07:55:12.02#ibcon#wrote, iclass 25, count 0 2006.285.07:55:12.02#ibcon#about to read 3, iclass 25, count 0 2006.285.07:55:12.04#ibcon#read 3, iclass 25, count 0 2006.285.07:55:12.04#ibcon#about to read 4, iclass 25, count 0 2006.285.07:55:12.04#ibcon#read 4, iclass 25, count 0 2006.285.07:55:12.04#ibcon#about to read 5, iclass 25, count 0 2006.285.07:55:12.04#ibcon#read 5, iclass 25, count 0 2006.285.07:55:12.04#ibcon#about to read 6, iclass 25, count 0 2006.285.07:55:12.04#ibcon#read 6, iclass 25, count 0 2006.285.07:55:12.04#ibcon#end of sib2, iclass 25, count 0 2006.285.07:55:12.04#ibcon#*mode == 0, iclass 25, count 0 2006.285.07:55:12.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.07:55:12.04#ibcon#[27=USB\r\n] 2006.285.07:55:12.04#ibcon#*before write, iclass 25, count 0 2006.285.07:55:12.04#ibcon#enter sib2, iclass 25, count 0 2006.285.07:55:12.04#ibcon#flushed, iclass 25, count 0 2006.285.07:55:12.04#ibcon#about to write, iclass 25, count 0 2006.285.07:55:12.04#ibcon#wrote, iclass 25, count 0 2006.285.07:55:12.04#ibcon#about to read 3, iclass 25, count 0 2006.285.07:55:12.07#ibcon#read 3, iclass 25, count 0 2006.285.07:55:12.07#ibcon#about to read 4, iclass 25, count 0 2006.285.07:55:12.07#ibcon#read 4, iclass 25, count 0 2006.285.07:55:12.07#ibcon#about to read 5, iclass 25, count 0 2006.285.07:55:12.07#ibcon#read 5, iclass 25, count 0 2006.285.07:55:12.07#ibcon#about to read 6, iclass 25, count 0 2006.285.07:55:12.07#ibcon#read 6, iclass 25, count 0 2006.285.07:55:12.07#ibcon#end of sib2, iclass 25, count 0 2006.285.07:55:12.07#ibcon#*after write, iclass 25, count 0 2006.285.07:55:12.07#ibcon#*before return 0, iclass 25, count 0 2006.285.07:55:12.07#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:55:12.07#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.07:55:12.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.07:55:12.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.07:55:12.07$vck44/vabw=wide 2006.285.07:55:12.07#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.07:55:12.07#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.07:55:12.07#ibcon#ireg 8 cls_cnt 0 2006.285.07:55:12.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:55:12.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:55:12.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:55:12.07#ibcon#enter wrdev, iclass 27, count 0 2006.285.07:55:12.07#ibcon#first serial, iclass 27, count 0 2006.285.07:55:12.07#ibcon#enter sib2, iclass 27, count 0 2006.285.07:55:12.07#ibcon#flushed, iclass 27, count 0 2006.285.07:55:12.07#ibcon#about to write, iclass 27, count 0 2006.285.07:55:12.07#ibcon#wrote, iclass 27, count 0 2006.285.07:55:12.07#ibcon#about to read 3, iclass 27, count 0 2006.285.07:55:12.09#ibcon#read 3, iclass 27, count 0 2006.285.07:55:12.09#ibcon#about to read 4, iclass 27, count 0 2006.285.07:55:12.09#ibcon#read 4, iclass 27, count 0 2006.285.07:55:12.09#ibcon#about to read 5, iclass 27, count 0 2006.285.07:55:12.09#ibcon#read 5, iclass 27, count 0 2006.285.07:55:12.09#ibcon#about to read 6, iclass 27, count 0 2006.285.07:55:12.09#ibcon#read 6, iclass 27, count 0 2006.285.07:55:12.09#ibcon#end of sib2, iclass 27, count 0 2006.285.07:55:12.09#ibcon#*mode == 0, iclass 27, count 0 2006.285.07:55:12.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.07:55:12.09#ibcon#[25=BW32\r\n] 2006.285.07:55:12.09#ibcon#*before write, iclass 27, count 0 2006.285.07:55:12.09#ibcon#enter sib2, iclass 27, count 0 2006.285.07:55:12.09#ibcon#flushed, iclass 27, count 0 2006.285.07:55:12.09#ibcon#about to write, iclass 27, count 0 2006.285.07:55:12.09#ibcon#wrote, iclass 27, count 0 2006.285.07:55:12.09#ibcon#about to read 3, iclass 27, count 0 2006.285.07:55:12.12#ibcon#read 3, iclass 27, count 0 2006.285.07:55:12.12#ibcon#about to read 4, iclass 27, count 0 2006.285.07:55:12.12#ibcon#read 4, iclass 27, count 0 2006.285.07:55:12.12#ibcon#about to read 5, iclass 27, count 0 2006.285.07:55:12.12#ibcon#read 5, iclass 27, count 0 2006.285.07:55:12.12#ibcon#about to read 6, iclass 27, count 0 2006.285.07:55:12.12#ibcon#read 6, iclass 27, count 0 2006.285.07:55:12.12#ibcon#end of sib2, iclass 27, count 0 2006.285.07:55:12.12#ibcon#*after write, iclass 27, count 0 2006.285.07:55:12.12#ibcon#*before return 0, iclass 27, count 0 2006.285.07:55:12.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:55:12.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.07:55:12.12#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.07:55:12.12#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.07:55:12.12$vck44/vbbw=wide 2006.285.07:55:12.12#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.07:55:12.12#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.07:55:12.12#ibcon#ireg 8 cls_cnt 0 2006.285.07:55:12.12#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:55:12.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:55:12.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:55:12.19#ibcon#enter wrdev, iclass 29, count 0 2006.285.07:55:12.19#ibcon#first serial, iclass 29, count 0 2006.285.07:55:12.19#ibcon#enter sib2, iclass 29, count 0 2006.285.07:55:12.19#ibcon#flushed, iclass 29, count 0 2006.285.07:55:12.19#ibcon#about to write, iclass 29, count 0 2006.285.07:55:12.19#ibcon#wrote, iclass 29, count 0 2006.285.07:55:12.19#ibcon#about to read 3, iclass 29, count 0 2006.285.07:55:12.21#ibcon#read 3, iclass 29, count 0 2006.285.07:55:12.21#ibcon#about to read 4, iclass 29, count 0 2006.285.07:55:12.21#ibcon#read 4, iclass 29, count 0 2006.285.07:55:12.21#ibcon#about to read 5, iclass 29, count 0 2006.285.07:55:12.21#ibcon#read 5, iclass 29, count 0 2006.285.07:55:12.21#ibcon#about to read 6, iclass 29, count 0 2006.285.07:55:12.21#ibcon#read 6, iclass 29, count 0 2006.285.07:55:12.21#ibcon#end of sib2, iclass 29, count 0 2006.285.07:55:12.21#ibcon#*mode == 0, iclass 29, count 0 2006.285.07:55:12.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.07:55:12.21#ibcon#[27=BW32\r\n] 2006.285.07:55:12.21#ibcon#*before write, iclass 29, count 0 2006.285.07:55:12.21#ibcon#enter sib2, iclass 29, count 0 2006.285.07:55:12.21#ibcon#flushed, iclass 29, count 0 2006.285.07:55:12.21#ibcon#about to write, iclass 29, count 0 2006.285.07:55:12.21#ibcon#wrote, iclass 29, count 0 2006.285.07:55:12.21#ibcon#about to read 3, iclass 29, count 0 2006.285.07:55:12.24#ibcon#read 3, iclass 29, count 0 2006.285.07:55:12.24#ibcon#about to read 4, iclass 29, count 0 2006.285.07:55:12.24#ibcon#read 4, iclass 29, count 0 2006.285.07:55:12.24#ibcon#about to read 5, iclass 29, count 0 2006.285.07:55:12.24#ibcon#read 5, iclass 29, count 0 2006.285.07:55:12.24#ibcon#about to read 6, iclass 29, count 0 2006.285.07:55:12.24#ibcon#read 6, iclass 29, count 0 2006.285.07:55:12.24#ibcon#end of sib2, iclass 29, count 0 2006.285.07:55:12.24#ibcon#*after write, iclass 29, count 0 2006.285.07:55:12.24#ibcon#*before return 0, iclass 29, count 0 2006.285.07:55:12.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:55:12.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.07:55:12.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.07:55:12.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.07:55:12.24$setupk4/ifdk4 2006.285.07:55:12.24$ifdk4/lo= 2006.285.07:55:12.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.07:55:12.24$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.07:55:12.24$ifdk4/patch= 2006.285.07:55:12.24$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.07:55:12.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.07:55:12.24$setupk4/!*+20s 2006.285.07:55:18.14#trakl#Source acquired 2006.285.07:55:18.88#abcon#<5=/04 2.3 3.7 23.11 781014.5\r\n> 2006.285.07:55:18.90#abcon#{5=INTERFACE CLEAR} 2006.285.07:55:18.96#abcon#[5=S1D000X0/0*\r\n] 2006.285.07:55:20.14#flagr#flagr/antenna,acquired 2006.285.07:55:26.74$setupk4/"tpicd 2006.285.07:55:26.74$setupk4/echo=off 2006.285.07:55:26.74$setupk4/xlog=off 2006.285.07:55:26.74:!2006.285.07:58:52 2006.285.07:58:52.00:preob 2006.285.07:58:52.14/onsource/TRACKING 2006.285.07:58:52.14:!2006.285.07:59:02 2006.285.07:59:02.00:"tape 2006.285.07:59:02.00:"st=record 2006.285.07:59:02.00:data_valid=on 2006.285.07:59:02.00:midob 2006.285.07:59:02.14/onsource/TRACKING 2006.285.07:59:02.14/wx/23.02,1014.5,78 2006.285.07:59:02.19/cable/+6.4729E-03 2006.285.07:59:03.28/va/01,07,usb,yes,32,34 2006.285.07:59:03.28/va/02,06,usb,yes,32,32 2006.285.07:59:03.28/va/03,07,usb,yes,31,33 2006.285.07:59:03.28/va/04,06,usb,yes,33,34 2006.285.07:59:03.28/va/05,03,usb,yes,32,33 2006.285.07:59:03.28/va/06,04,usb,yes,29,28 2006.285.07:59:03.28/va/07,04,usb,yes,29,30 2006.285.07:59:03.28/va/08,03,usb,yes,30,37 2006.285.07:59:03.51/valo/01,524.99,yes,locked 2006.285.07:59:03.51/valo/02,534.99,yes,locked 2006.285.07:59:03.51/valo/03,564.99,yes,locked 2006.285.07:59:03.51/valo/04,624.99,yes,locked 2006.285.07:59:03.51/valo/05,734.99,yes,locked 2006.285.07:59:03.51/valo/06,814.99,yes,locked 2006.285.07:59:03.51/valo/07,864.99,yes,locked 2006.285.07:59:03.51/valo/08,884.99,yes,locked 2006.285.07:59:04.60/vb/01,04,usb,yes,30,28 2006.285.07:59:04.60/vb/02,05,usb,yes,29,29 2006.285.07:59:04.60/vb/03,04,usb,yes,30,33 2006.285.07:59:04.60/vb/04,05,usb,yes,30,29 2006.285.07:59:04.60/vb/05,04,usb,yes,26,29 2006.285.07:59:04.60/vb/06,03,usb,yes,38,34 2006.285.07:59:04.60/vb/07,04,usb,yes,31,31 2006.285.07:59:04.60/vb/08,04,usb,yes,28,31 2006.285.07:59:04.83/vblo/01,629.99,yes,locked 2006.285.07:59:04.83/vblo/02,634.99,yes,locked 2006.285.07:59:04.83/vblo/03,649.99,yes,locked 2006.285.07:59:04.83/vblo/04,679.99,yes,locked 2006.285.07:59:04.83/vblo/05,709.99,yes,locked 2006.285.07:59:04.83/vblo/06,719.99,yes,locked 2006.285.07:59:04.83/vblo/07,734.99,yes,locked 2006.285.07:59:04.83/vblo/08,744.99,yes,locked 2006.285.07:59:04.98/vabw/8 2006.285.07:59:05.13/vbbw/8 2006.285.07:59:05.22/xfe/off,on,12.2 2006.285.07:59:05.60/ifatt/23,28,28,28 2006.285.07:59:06.07/fmout-gps/S +2.76E-07 2006.285.07:59:06.09:!2006.285.08:01:42 2006.285.08:01:42.00:data_valid=off 2006.285.08:01:42.00:"et 2006.285.08:01:42.00:!+3s 2006.285.08:01:45.01:"tape 2006.285.08:01:45.01:postob 2006.285.08:01:45.10/cable/+6.4730E-03 2006.285.08:01:45.10/wx/22.96,1014.5,79 2006.285.08:01:46.07/fmout-gps/S +2.74E-07 2006.285.08:01:46.07:scan_name=285-0808,jd0610,320 2006.285.08:01:46.07:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.285.08:01:47.14#flagr#flagr/antenna,new-source 2006.285.08:01:47.14:checkk5 2006.285.08:01:47.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:01:47.96/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:01:48.36/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:01:48.80/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:01:49.66/chk_obsdata//k5ts1/T2850759??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.08:01:50.02/chk_obsdata//k5ts2/T2850759??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.08:01:50.43/chk_obsdata//k5ts3/T2850759??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.08:01:51.05/chk_obsdata//k5ts4/T2850759??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.08:01:54.79/k5log//k5ts1_log_newline 2006.285.08:01:55.55/k5log//k5ts2_log_newline 2006.285.08:01:56.34/k5log//k5ts3_log_newline 2006.285.08:01:57.12/k5log//k5ts4_log_newline 2006.285.08:01:57.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:01:57.14:setupk4=1 2006.285.08:01:57.14$setupk4/echo=on 2006.285.08:01:57.14$setupk4/pcalon 2006.285.08:01:57.14$pcalon/"no phase cal control is implemented here 2006.285.08:01:57.14$setupk4/"tpicd=stop 2006.285.08:01:57.14$setupk4/"rec=synch_on 2006.285.08:01:57.14$setupk4/"rec_mode=128 2006.285.08:01:57.14$setupk4/!* 2006.285.08:01:57.15$setupk4/recpk4 2006.285.08:01:57.15$recpk4/recpatch= 2006.285.08:01:57.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:01:57.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:01:57.15$setupk4/vck44 2006.285.08:01:57.15$vck44/valo=1,524.99 2006.285.08:01:57.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.08:01:57.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.08:01:57.15#ibcon#ireg 17 cls_cnt 0 2006.285.08:01:57.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:01:57.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:01:57.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:01:57.15#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:01:57.15#ibcon#first serial, iclass 14, count 0 2006.285.08:01:57.15#ibcon#enter sib2, iclass 14, count 0 2006.285.08:01:57.15#ibcon#flushed, iclass 14, count 0 2006.285.08:01:57.15#ibcon#about to write, iclass 14, count 0 2006.285.08:01:57.15#ibcon#wrote, iclass 14, count 0 2006.285.08:01:57.15#ibcon#about to read 3, iclass 14, count 0 2006.285.08:01:57.17#ibcon#read 3, iclass 14, count 0 2006.285.08:01:57.17#ibcon#about to read 4, iclass 14, count 0 2006.285.08:01:57.17#ibcon#read 4, iclass 14, count 0 2006.285.08:01:57.17#ibcon#about to read 5, iclass 14, count 0 2006.285.08:01:57.17#ibcon#read 5, iclass 14, count 0 2006.285.08:01:57.17#ibcon#about to read 6, iclass 14, count 0 2006.285.08:01:57.17#ibcon#read 6, iclass 14, count 0 2006.285.08:01:57.17#ibcon#end of sib2, iclass 14, count 0 2006.285.08:01:57.17#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:01:57.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:01:57.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:01:57.17#ibcon#*before write, iclass 14, count 0 2006.285.08:01:57.17#ibcon#enter sib2, iclass 14, count 0 2006.285.08:01:57.17#ibcon#flushed, iclass 14, count 0 2006.285.08:01:57.17#ibcon#about to write, iclass 14, count 0 2006.285.08:01:57.17#ibcon#wrote, iclass 14, count 0 2006.285.08:01:57.17#ibcon#about to read 3, iclass 14, count 0 2006.285.08:01:57.22#ibcon#read 3, iclass 14, count 0 2006.285.08:01:57.22#ibcon#about to read 4, iclass 14, count 0 2006.285.08:01:57.22#ibcon#read 4, iclass 14, count 0 2006.285.08:01:57.22#ibcon#about to read 5, iclass 14, count 0 2006.285.08:01:57.22#ibcon#read 5, iclass 14, count 0 2006.285.08:01:57.22#ibcon#about to read 6, iclass 14, count 0 2006.285.08:01:57.22#ibcon#read 6, iclass 14, count 0 2006.285.08:01:57.22#ibcon#end of sib2, iclass 14, count 0 2006.285.08:01:57.22#ibcon#*after write, iclass 14, count 0 2006.285.08:01:57.22#ibcon#*before return 0, iclass 14, count 0 2006.285.08:01:57.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:01:57.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:01:57.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:01:57.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:01:57.22$vck44/va=1,7 2006.285.08:01:57.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.08:01:57.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.08:01:57.22#ibcon#ireg 11 cls_cnt 2 2006.285.08:01:57.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:01:57.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:01:57.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:01:57.22#ibcon#enter wrdev, iclass 16, count 2 2006.285.08:01:57.22#ibcon#first serial, iclass 16, count 2 2006.285.08:01:57.22#ibcon#enter sib2, iclass 16, count 2 2006.285.08:01:57.22#ibcon#flushed, iclass 16, count 2 2006.285.08:01:57.22#ibcon#about to write, iclass 16, count 2 2006.285.08:01:57.22#ibcon#wrote, iclass 16, count 2 2006.285.08:01:57.22#ibcon#about to read 3, iclass 16, count 2 2006.285.08:01:57.24#ibcon#read 3, iclass 16, count 2 2006.285.08:01:57.24#ibcon#about to read 4, iclass 16, count 2 2006.285.08:01:57.24#ibcon#read 4, iclass 16, count 2 2006.285.08:01:57.24#ibcon#about to read 5, iclass 16, count 2 2006.285.08:01:57.24#ibcon#read 5, iclass 16, count 2 2006.285.08:01:57.24#ibcon#about to read 6, iclass 16, count 2 2006.285.08:01:57.24#ibcon#read 6, iclass 16, count 2 2006.285.08:01:57.24#ibcon#end of sib2, iclass 16, count 2 2006.285.08:01:57.24#ibcon#*mode == 0, iclass 16, count 2 2006.285.08:01:57.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.08:01:57.24#ibcon#[25=AT01-07\r\n] 2006.285.08:01:57.24#ibcon#*before write, iclass 16, count 2 2006.285.08:01:57.24#ibcon#enter sib2, iclass 16, count 2 2006.285.08:01:57.24#ibcon#flushed, iclass 16, count 2 2006.285.08:01:57.24#ibcon#about to write, iclass 16, count 2 2006.285.08:01:57.24#ibcon#wrote, iclass 16, count 2 2006.285.08:01:57.24#ibcon#about to read 3, iclass 16, count 2 2006.285.08:01:57.27#ibcon#read 3, iclass 16, count 2 2006.285.08:01:57.27#ibcon#about to read 4, iclass 16, count 2 2006.285.08:01:57.27#ibcon#read 4, iclass 16, count 2 2006.285.08:01:57.27#ibcon#about to read 5, iclass 16, count 2 2006.285.08:01:57.27#ibcon#read 5, iclass 16, count 2 2006.285.08:01:57.27#ibcon#about to read 6, iclass 16, count 2 2006.285.08:01:57.27#ibcon#read 6, iclass 16, count 2 2006.285.08:01:57.27#ibcon#end of sib2, iclass 16, count 2 2006.285.08:01:57.27#ibcon#*after write, iclass 16, count 2 2006.285.08:01:57.27#ibcon#*before return 0, iclass 16, count 2 2006.285.08:01:57.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:01:57.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:01:57.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.08:01:57.27#ibcon#ireg 7 cls_cnt 0 2006.285.08:01:57.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:01:57.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:01:57.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:01:57.39#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:01:57.39#ibcon#first serial, iclass 16, count 0 2006.285.08:01:57.39#ibcon#enter sib2, iclass 16, count 0 2006.285.08:01:57.39#ibcon#flushed, iclass 16, count 0 2006.285.08:01:57.39#ibcon#about to write, iclass 16, count 0 2006.285.08:01:57.39#ibcon#wrote, iclass 16, count 0 2006.285.08:01:57.39#ibcon#about to read 3, iclass 16, count 0 2006.285.08:01:57.41#ibcon#read 3, iclass 16, count 0 2006.285.08:01:57.41#ibcon#about to read 4, iclass 16, count 0 2006.285.08:01:57.41#ibcon#read 4, iclass 16, count 0 2006.285.08:01:57.41#ibcon#about to read 5, iclass 16, count 0 2006.285.08:01:57.41#ibcon#read 5, iclass 16, count 0 2006.285.08:01:57.41#ibcon#about to read 6, iclass 16, count 0 2006.285.08:01:57.41#ibcon#read 6, iclass 16, count 0 2006.285.08:01:57.41#ibcon#end of sib2, iclass 16, count 0 2006.285.08:01:57.41#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:01:57.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:01:57.41#ibcon#[25=USB\r\n] 2006.285.08:01:57.41#ibcon#*before write, iclass 16, count 0 2006.285.08:01:57.41#ibcon#enter sib2, iclass 16, count 0 2006.285.08:01:57.41#ibcon#flushed, iclass 16, count 0 2006.285.08:01:57.41#ibcon#about to write, iclass 16, count 0 2006.285.08:01:57.41#ibcon#wrote, iclass 16, count 0 2006.285.08:01:57.41#ibcon#about to read 3, iclass 16, count 0 2006.285.08:01:57.44#ibcon#read 3, iclass 16, count 0 2006.285.08:01:57.44#ibcon#about to read 4, iclass 16, count 0 2006.285.08:01:57.44#ibcon#read 4, iclass 16, count 0 2006.285.08:01:57.44#ibcon#about to read 5, iclass 16, count 0 2006.285.08:01:57.44#ibcon#read 5, iclass 16, count 0 2006.285.08:01:57.44#ibcon#about to read 6, iclass 16, count 0 2006.285.08:01:57.44#ibcon#read 6, iclass 16, count 0 2006.285.08:01:57.44#ibcon#end of sib2, iclass 16, count 0 2006.285.08:01:57.44#ibcon#*after write, iclass 16, count 0 2006.285.08:01:57.44#ibcon#*before return 0, iclass 16, count 0 2006.285.08:01:57.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:01:57.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:01:57.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:01:57.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:01:57.44$vck44/valo=2,534.99 2006.285.08:01:57.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.08:01:57.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.08:01:57.44#ibcon#ireg 17 cls_cnt 0 2006.285.08:01:57.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:01:57.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:01:57.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:01:57.44#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:01:57.44#ibcon#first serial, iclass 18, count 0 2006.285.08:01:57.44#ibcon#enter sib2, iclass 18, count 0 2006.285.08:01:57.44#ibcon#flushed, iclass 18, count 0 2006.285.08:01:57.44#ibcon#about to write, iclass 18, count 0 2006.285.08:01:57.44#ibcon#wrote, iclass 18, count 0 2006.285.08:01:57.44#ibcon#about to read 3, iclass 18, count 0 2006.285.08:01:57.46#ibcon#read 3, iclass 18, count 0 2006.285.08:01:57.46#ibcon#about to read 4, iclass 18, count 0 2006.285.08:01:57.46#ibcon#read 4, iclass 18, count 0 2006.285.08:01:57.46#ibcon#about to read 5, iclass 18, count 0 2006.285.08:01:57.46#ibcon#read 5, iclass 18, count 0 2006.285.08:01:57.46#ibcon#about to read 6, iclass 18, count 0 2006.285.08:01:57.46#ibcon#read 6, iclass 18, count 0 2006.285.08:01:57.46#ibcon#end of sib2, iclass 18, count 0 2006.285.08:01:57.46#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:01:57.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:01:57.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:01:57.46#ibcon#*before write, iclass 18, count 0 2006.285.08:01:57.46#ibcon#enter sib2, iclass 18, count 0 2006.285.08:01:57.46#ibcon#flushed, iclass 18, count 0 2006.285.08:01:57.46#ibcon#about to write, iclass 18, count 0 2006.285.08:01:57.46#ibcon#wrote, iclass 18, count 0 2006.285.08:01:57.46#ibcon#about to read 3, iclass 18, count 0 2006.285.08:01:57.50#ibcon#read 3, iclass 18, count 0 2006.285.08:01:57.50#ibcon#about to read 4, iclass 18, count 0 2006.285.08:01:57.50#ibcon#read 4, iclass 18, count 0 2006.285.08:01:57.50#ibcon#about to read 5, iclass 18, count 0 2006.285.08:01:57.50#ibcon#read 5, iclass 18, count 0 2006.285.08:01:57.50#ibcon#about to read 6, iclass 18, count 0 2006.285.08:01:57.50#ibcon#read 6, iclass 18, count 0 2006.285.08:01:57.50#ibcon#end of sib2, iclass 18, count 0 2006.285.08:01:57.50#ibcon#*after write, iclass 18, count 0 2006.285.08:01:57.50#ibcon#*before return 0, iclass 18, count 0 2006.285.08:01:57.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:01:57.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:01:57.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:01:57.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:01:57.51$vck44/va=2,6 2006.285.08:01:57.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.08:01:57.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.08:01:57.51#ibcon#ireg 11 cls_cnt 2 2006.285.08:01:57.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:01:57.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:01:57.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:01:57.56#ibcon#enter wrdev, iclass 20, count 2 2006.285.08:01:57.56#ibcon#first serial, iclass 20, count 2 2006.285.08:01:57.56#ibcon#enter sib2, iclass 20, count 2 2006.285.08:01:57.56#ibcon#flushed, iclass 20, count 2 2006.285.08:01:57.56#ibcon#about to write, iclass 20, count 2 2006.285.08:01:57.56#ibcon#wrote, iclass 20, count 2 2006.285.08:01:57.56#ibcon#about to read 3, iclass 20, count 2 2006.285.08:01:57.58#ibcon#read 3, iclass 20, count 2 2006.285.08:01:57.58#ibcon#about to read 4, iclass 20, count 2 2006.285.08:01:57.58#ibcon#read 4, iclass 20, count 2 2006.285.08:01:57.58#ibcon#about to read 5, iclass 20, count 2 2006.285.08:01:57.58#ibcon#read 5, iclass 20, count 2 2006.285.08:01:57.58#ibcon#about to read 6, iclass 20, count 2 2006.285.08:01:57.58#ibcon#read 6, iclass 20, count 2 2006.285.08:01:57.58#ibcon#end of sib2, iclass 20, count 2 2006.285.08:01:57.58#ibcon#*mode == 0, iclass 20, count 2 2006.285.08:01:57.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.08:01:57.58#ibcon#[25=AT02-06\r\n] 2006.285.08:01:57.58#ibcon#*before write, iclass 20, count 2 2006.285.08:01:57.58#ibcon#enter sib2, iclass 20, count 2 2006.285.08:01:57.58#ibcon#flushed, iclass 20, count 2 2006.285.08:01:57.58#ibcon#about to write, iclass 20, count 2 2006.285.08:01:57.58#ibcon#wrote, iclass 20, count 2 2006.285.08:01:57.58#ibcon#about to read 3, iclass 20, count 2 2006.285.08:01:57.61#ibcon#read 3, iclass 20, count 2 2006.285.08:01:57.61#ibcon#about to read 4, iclass 20, count 2 2006.285.08:01:57.61#ibcon#read 4, iclass 20, count 2 2006.285.08:01:57.61#ibcon#about to read 5, iclass 20, count 2 2006.285.08:01:57.61#ibcon#read 5, iclass 20, count 2 2006.285.08:01:57.61#ibcon#about to read 6, iclass 20, count 2 2006.285.08:01:57.61#ibcon#read 6, iclass 20, count 2 2006.285.08:01:57.61#ibcon#end of sib2, iclass 20, count 2 2006.285.08:01:57.61#ibcon#*after write, iclass 20, count 2 2006.285.08:01:57.61#ibcon#*before return 0, iclass 20, count 2 2006.285.08:01:57.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:01:57.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:01:57.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.08:01:57.61#ibcon#ireg 7 cls_cnt 0 2006.285.08:01:57.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:01:57.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:01:57.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:01:57.73#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:01:57.73#ibcon#first serial, iclass 20, count 0 2006.285.08:01:57.73#ibcon#enter sib2, iclass 20, count 0 2006.285.08:01:57.73#ibcon#flushed, iclass 20, count 0 2006.285.08:01:57.73#ibcon#about to write, iclass 20, count 0 2006.285.08:01:57.73#ibcon#wrote, iclass 20, count 0 2006.285.08:01:57.73#ibcon#about to read 3, iclass 20, count 0 2006.285.08:01:57.75#ibcon#read 3, iclass 20, count 0 2006.285.08:01:57.75#ibcon#about to read 4, iclass 20, count 0 2006.285.08:01:57.75#ibcon#read 4, iclass 20, count 0 2006.285.08:01:57.75#ibcon#about to read 5, iclass 20, count 0 2006.285.08:01:57.75#ibcon#read 5, iclass 20, count 0 2006.285.08:01:57.75#ibcon#about to read 6, iclass 20, count 0 2006.285.08:01:57.75#ibcon#read 6, iclass 20, count 0 2006.285.08:01:57.75#ibcon#end of sib2, iclass 20, count 0 2006.285.08:01:57.75#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:01:57.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:01:57.75#ibcon#[25=USB\r\n] 2006.285.08:01:57.75#ibcon#*before write, iclass 20, count 0 2006.285.08:01:57.75#ibcon#enter sib2, iclass 20, count 0 2006.285.08:01:57.75#ibcon#flushed, iclass 20, count 0 2006.285.08:01:57.75#ibcon#about to write, iclass 20, count 0 2006.285.08:01:57.75#ibcon#wrote, iclass 20, count 0 2006.285.08:01:57.75#ibcon#about to read 3, iclass 20, count 0 2006.285.08:01:57.78#ibcon#read 3, iclass 20, count 0 2006.285.08:01:57.78#ibcon#about to read 4, iclass 20, count 0 2006.285.08:01:57.78#ibcon#read 4, iclass 20, count 0 2006.285.08:01:57.78#ibcon#about to read 5, iclass 20, count 0 2006.285.08:01:57.78#ibcon#read 5, iclass 20, count 0 2006.285.08:01:57.78#ibcon#about to read 6, iclass 20, count 0 2006.285.08:01:57.78#ibcon#read 6, iclass 20, count 0 2006.285.08:01:57.78#ibcon#end of sib2, iclass 20, count 0 2006.285.08:01:57.78#ibcon#*after write, iclass 20, count 0 2006.285.08:01:57.78#ibcon#*before return 0, iclass 20, count 0 2006.285.08:01:57.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:01:57.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:01:57.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:01:57.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:01:57.78$vck44/valo=3,564.99 2006.285.08:01:57.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.08:01:57.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.08:01:57.78#ibcon#ireg 17 cls_cnt 0 2006.285.08:01:57.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:01:57.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:01:57.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:01:57.78#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:01:57.78#ibcon#first serial, iclass 22, count 0 2006.285.08:01:57.78#ibcon#enter sib2, iclass 22, count 0 2006.285.08:01:57.78#ibcon#flushed, iclass 22, count 0 2006.285.08:01:57.78#ibcon#about to write, iclass 22, count 0 2006.285.08:01:57.78#ibcon#wrote, iclass 22, count 0 2006.285.08:01:57.78#ibcon#about to read 3, iclass 22, count 0 2006.285.08:01:57.80#ibcon#read 3, iclass 22, count 0 2006.285.08:01:57.80#ibcon#about to read 4, iclass 22, count 0 2006.285.08:01:57.80#ibcon#read 4, iclass 22, count 0 2006.285.08:01:57.80#ibcon#about to read 5, iclass 22, count 0 2006.285.08:01:57.80#ibcon#read 5, iclass 22, count 0 2006.285.08:01:57.80#ibcon#about to read 6, iclass 22, count 0 2006.285.08:01:57.80#ibcon#read 6, iclass 22, count 0 2006.285.08:01:57.80#ibcon#end of sib2, iclass 22, count 0 2006.285.08:01:57.80#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:01:57.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:01:57.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:01:57.80#ibcon#*before write, iclass 22, count 0 2006.285.08:01:57.80#ibcon#enter sib2, iclass 22, count 0 2006.285.08:01:57.80#ibcon#flushed, iclass 22, count 0 2006.285.08:01:57.80#ibcon#about to write, iclass 22, count 0 2006.285.08:01:57.80#ibcon#wrote, iclass 22, count 0 2006.285.08:01:57.80#ibcon#about to read 3, iclass 22, count 0 2006.285.08:01:57.84#ibcon#read 3, iclass 22, count 0 2006.285.08:01:57.84#ibcon#about to read 4, iclass 22, count 0 2006.285.08:01:57.84#ibcon#read 4, iclass 22, count 0 2006.285.08:01:57.84#ibcon#about to read 5, iclass 22, count 0 2006.285.08:01:57.84#ibcon#read 5, iclass 22, count 0 2006.285.08:01:57.84#ibcon#about to read 6, iclass 22, count 0 2006.285.08:01:57.84#ibcon#read 6, iclass 22, count 0 2006.285.08:01:57.84#ibcon#end of sib2, iclass 22, count 0 2006.285.08:01:57.84#ibcon#*after write, iclass 22, count 0 2006.285.08:01:57.84#ibcon#*before return 0, iclass 22, count 0 2006.285.08:01:57.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:01:57.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:01:57.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:01:57.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:01:57.84$vck44/va=3,7 2006.285.08:01:57.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.08:01:57.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.08:01:57.84#ibcon#ireg 11 cls_cnt 2 2006.285.08:01:57.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:01:57.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:01:57.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:01:57.90#ibcon#enter wrdev, iclass 24, count 2 2006.285.08:01:57.90#ibcon#first serial, iclass 24, count 2 2006.285.08:01:57.90#ibcon#enter sib2, iclass 24, count 2 2006.285.08:01:57.90#ibcon#flushed, iclass 24, count 2 2006.285.08:01:57.90#ibcon#about to write, iclass 24, count 2 2006.285.08:01:57.90#ibcon#wrote, iclass 24, count 2 2006.285.08:01:57.90#ibcon#about to read 3, iclass 24, count 2 2006.285.08:01:57.92#ibcon#read 3, iclass 24, count 2 2006.285.08:01:57.92#ibcon#about to read 4, iclass 24, count 2 2006.285.08:01:57.92#ibcon#read 4, iclass 24, count 2 2006.285.08:01:57.92#ibcon#about to read 5, iclass 24, count 2 2006.285.08:01:57.92#ibcon#read 5, iclass 24, count 2 2006.285.08:01:57.92#ibcon#about to read 6, iclass 24, count 2 2006.285.08:01:57.92#ibcon#read 6, iclass 24, count 2 2006.285.08:01:57.92#ibcon#end of sib2, iclass 24, count 2 2006.285.08:01:57.92#ibcon#*mode == 0, iclass 24, count 2 2006.285.08:01:57.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.08:01:57.92#ibcon#[25=AT03-07\r\n] 2006.285.08:01:57.92#ibcon#*before write, iclass 24, count 2 2006.285.08:01:57.92#ibcon#enter sib2, iclass 24, count 2 2006.285.08:01:57.92#ibcon#flushed, iclass 24, count 2 2006.285.08:01:57.92#ibcon#about to write, iclass 24, count 2 2006.285.08:01:57.92#ibcon#wrote, iclass 24, count 2 2006.285.08:01:57.92#ibcon#about to read 3, iclass 24, count 2 2006.285.08:01:57.95#ibcon#read 3, iclass 24, count 2 2006.285.08:01:57.95#ibcon#about to read 4, iclass 24, count 2 2006.285.08:01:57.95#ibcon#read 4, iclass 24, count 2 2006.285.08:01:57.95#ibcon#about to read 5, iclass 24, count 2 2006.285.08:01:57.95#ibcon#read 5, iclass 24, count 2 2006.285.08:01:57.95#ibcon#about to read 6, iclass 24, count 2 2006.285.08:01:57.95#ibcon#read 6, iclass 24, count 2 2006.285.08:01:57.95#ibcon#end of sib2, iclass 24, count 2 2006.285.08:01:57.95#ibcon#*after write, iclass 24, count 2 2006.285.08:01:57.95#ibcon#*before return 0, iclass 24, count 2 2006.285.08:01:57.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:01:57.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:01:57.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.08:01:57.95#ibcon#ireg 7 cls_cnt 0 2006.285.08:01:57.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:01:58.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:01:58.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:01:58.07#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:01:58.07#ibcon#first serial, iclass 24, count 0 2006.285.08:01:58.07#ibcon#enter sib2, iclass 24, count 0 2006.285.08:01:58.07#ibcon#flushed, iclass 24, count 0 2006.285.08:01:58.07#ibcon#about to write, iclass 24, count 0 2006.285.08:01:58.07#ibcon#wrote, iclass 24, count 0 2006.285.08:01:58.07#ibcon#about to read 3, iclass 24, count 0 2006.285.08:01:58.09#ibcon#read 3, iclass 24, count 0 2006.285.08:01:58.09#ibcon#about to read 4, iclass 24, count 0 2006.285.08:01:58.09#ibcon#read 4, iclass 24, count 0 2006.285.08:01:58.09#ibcon#about to read 5, iclass 24, count 0 2006.285.08:01:58.09#ibcon#read 5, iclass 24, count 0 2006.285.08:01:58.09#ibcon#about to read 6, iclass 24, count 0 2006.285.08:01:58.09#ibcon#read 6, iclass 24, count 0 2006.285.08:01:58.09#ibcon#end of sib2, iclass 24, count 0 2006.285.08:01:58.09#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:01:58.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:01:58.09#ibcon#[25=USB\r\n] 2006.285.08:01:58.09#ibcon#*before write, iclass 24, count 0 2006.285.08:01:58.09#ibcon#enter sib2, iclass 24, count 0 2006.285.08:01:58.09#ibcon#flushed, iclass 24, count 0 2006.285.08:01:58.09#ibcon#about to write, iclass 24, count 0 2006.285.08:01:58.09#ibcon#wrote, iclass 24, count 0 2006.285.08:01:58.09#ibcon#about to read 3, iclass 24, count 0 2006.285.08:01:58.12#ibcon#read 3, iclass 24, count 0 2006.285.08:01:58.12#ibcon#about to read 4, iclass 24, count 0 2006.285.08:01:58.12#ibcon#read 4, iclass 24, count 0 2006.285.08:01:58.12#ibcon#about to read 5, iclass 24, count 0 2006.285.08:01:58.12#ibcon#read 5, iclass 24, count 0 2006.285.08:01:58.12#ibcon#about to read 6, iclass 24, count 0 2006.285.08:01:58.12#ibcon#read 6, iclass 24, count 0 2006.285.08:01:58.12#ibcon#end of sib2, iclass 24, count 0 2006.285.08:01:58.12#ibcon#*after write, iclass 24, count 0 2006.285.08:01:58.12#ibcon#*before return 0, iclass 24, count 0 2006.285.08:01:58.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:01:58.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:01:58.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:01:58.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:01:58.12$vck44/valo=4,624.99 2006.285.08:01:58.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.08:01:58.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.08:01:58.12#ibcon#ireg 17 cls_cnt 0 2006.285.08:01:58.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:01:58.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:01:58.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:01:58.12#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:01:58.12#ibcon#first serial, iclass 26, count 0 2006.285.08:01:58.12#ibcon#enter sib2, iclass 26, count 0 2006.285.08:01:58.12#ibcon#flushed, iclass 26, count 0 2006.285.08:01:58.12#ibcon#about to write, iclass 26, count 0 2006.285.08:01:58.12#ibcon#wrote, iclass 26, count 0 2006.285.08:01:58.12#ibcon#about to read 3, iclass 26, count 0 2006.285.08:01:58.14#ibcon#read 3, iclass 26, count 0 2006.285.08:01:58.14#ibcon#about to read 4, iclass 26, count 0 2006.285.08:01:58.14#ibcon#read 4, iclass 26, count 0 2006.285.08:01:58.14#ibcon#about to read 5, iclass 26, count 0 2006.285.08:01:58.14#ibcon#read 5, iclass 26, count 0 2006.285.08:01:58.14#ibcon#about to read 6, iclass 26, count 0 2006.285.08:01:58.14#ibcon#read 6, iclass 26, count 0 2006.285.08:01:58.14#ibcon#end of sib2, iclass 26, count 0 2006.285.08:01:58.14#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:01:58.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:01:58.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:01:58.14#ibcon#*before write, iclass 26, count 0 2006.285.08:01:58.14#ibcon#enter sib2, iclass 26, count 0 2006.285.08:01:58.14#ibcon#flushed, iclass 26, count 0 2006.285.08:01:58.14#ibcon#about to write, iclass 26, count 0 2006.285.08:01:58.14#ibcon#wrote, iclass 26, count 0 2006.285.08:01:58.14#ibcon#about to read 3, iclass 26, count 0 2006.285.08:01:58.18#ibcon#read 3, iclass 26, count 0 2006.285.08:01:58.18#ibcon#about to read 4, iclass 26, count 0 2006.285.08:01:58.18#ibcon#read 4, iclass 26, count 0 2006.285.08:01:58.18#ibcon#about to read 5, iclass 26, count 0 2006.285.08:01:58.18#ibcon#read 5, iclass 26, count 0 2006.285.08:01:58.18#ibcon#about to read 6, iclass 26, count 0 2006.285.08:01:58.18#ibcon#read 6, iclass 26, count 0 2006.285.08:01:58.18#ibcon#end of sib2, iclass 26, count 0 2006.285.08:01:58.18#ibcon#*after write, iclass 26, count 0 2006.285.08:01:58.18#ibcon#*before return 0, iclass 26, count 0 2006.285.08:01:58.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:01:58.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:01:58.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:01:58.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:01:58.18$vck44/va=4,6 2006.285.08:01:58.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.08:01:58.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.08:01:58.18#ibcon#ireg 11 cls_cnt 2 2006.285.08:01:58.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:01:58.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:01:58.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:01:58.24#ibcon#enter wrdev, iclass 28, count 2 2006.285.08:01:58.24#ibcon#first serial, iclass 28, count 2 2006.285.08:01:58.24#ibcon#enter sib2, iclass 28, count 2 2006.285.08:01:58.24#ibcon#flushed, iclass 28, count 2 2006.285.08:01:58.24#ibcon#about to write, iclass 28, count 2 2006.285.08:01:58.24#ibcon#wrote, iclass 28, count 2 2006.285.08:01:58.24#ibcon#about to read 3, iclass 28, count 2 2006.285.08:01:58.26#ibcon#read 3, iclass 28, count 2 2006.285.08:01:58.26#ibcon#about to read 4, iclass 28, count 2 2006.285.08:01:58.26#ibcon#read 4, iclass 28, count 2 2006.285.08:01:58.26#ibcon#about to read 5, iclass 28, count 2 2006.285.08:01:58.26#ibcon#read 5, iclass 28, count 2 2006.285.08:01:58.26#ibcon#about to read 6, iclass 28, count 2 2006.285.08:01:58.26#ibcon#read 6, iclass 28, count 2 2006.285.08:01:58.26#ibcon#end of sib2, iclass 28, count 2 2006.285.08:01:58.26#ibcon#*mode == 0, iclass 28, count 2 2006.285.08:01:58.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.08:01:58.26#ibcon#[25=AT04-06\r\n] 2006.285.08:01:58.26#ibcon#*before write, iclass 28, count 2 2006.285.08:01:58.26#ibcon#enter sib2, iclass 28, count 2 2006.285.08:01:58.26#ibcon#flushed, iclass 28, count 2 2006.285.08:01:58.26#ibcon#about to write, iclass 28, count 2 2006.285.08:01:58.26#ibcon#wrote, iclass 28, count 2 2006.285.08:01:58.26#ibcon#about to read 3, iclass 28, count 2 2006.285.08:01:58.29#ibcon#read 3, iclass 28, count 2 2006.285.08:01:58.29#ibcon#about to read 4, iclass 28, count 2 2006.285.08:01:58.29#ibcon#read 4, iclass 28, count 2 2006.285.08:01:58.29#ibcon#about to read 5, iclass 28, count 2 2006.285.08:01:58.29#ibcon#read 5, iclass 28, count 2 2006.285.08:01:58.29#ibcon#about to read 6, iclass 28, count 2 2006.285.08:01:58.29#ibcon#read 6, iclass 28, count 2 2006.285.08:01:58.29#ibcon#end of sib2, iclass 28, count 2 2006.285.08:01:58.29#ibcon#*after write, iclass 28, count 2 2006.285.08:01:58.29#ibcon#*before return 0, iclass 28, count 2 2006.285.08:01:58.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:01:58.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:01:58.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.08:01:58.29#ibcon#ireg 7 cls_cnt 0 2006.285.08:01:58.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:01:58.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:01:58.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:01:58.41#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:01:58.41#ibcon#first serial, iclass 28, count 0 2006.285.08:01:58.41#ibcon#enter sib2, iclass 28, count 0 2006.285.08:01:58.41#ibcon#flushed, iclass 28, count 0 2006.285.08:01:58.41#ibcon#about to write, iclass 28, count 0 2006.285.08:01:58.41#ibcon#wrote, iclass 28, count 0 2006.285.08:01:58.41#ibcon#about to read 3, iclass 28, count 0 2006.285.08:01:58.43#ibcon#read 3, iclass 28, count 0 2006.285.08:01:58.43#ibcon#about to read 4, iclass 28, count 0 2006.285.08:01:58.43#ibcon#read 4, iclass 28, count 0 2006.285.08:01:58.43#ibcon#about to read 5, iclass 28, count 0 2006.285.08:01:58.43#ibcon#read 5, iclass 28, count 0 2006.285.08:01:58.43#ibcon#about to read 6, iclass 28, count 0 2006.285.08:01:58.43#ibcon#read 6, iclass 28, count 0 2006.285.08:01:58.43#ibcon#end of sib2, iclass 28, count 0 2006.285.08:01:58.43#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:01:58.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:01:58.43#ibcon#[25=USB\r\n] 2006.285.08:01:58.43#ibcon#*before write, iclass 28, count 0 2006.285.08:01:58.43#ibcon#enter sib2, iclass 28, count 0 2006.285.08:01:58.43#ibcon#flushed, iclass 28, count 0 2006.285.08:01:58.43#ibcon#about to write, iclass 28, count 0 2006.285.08:01:58.43#ibcon#wrote, iclass 28, count 0 2006.285.08:01:58.43#ibcon#about to read 3, iclass 28, count 0 2006.285.08:01:58.46#ibcon#read 3, iclass 28, count 0 2006.285.08:01:58.46#ibcon#about to read 4, iclass 28, count 0 2006.285.08:01:58.46#ibcon#read 4, iclass 28, count 0 2006.285.08:01:58.46#ibcon#about to read 5, iclass 28, count 0 2006.285.08:01:58.46#ibcon#read 5, iclass 28, count 0 2006.285.08:01:58.46#ibcon#about to read 6, iclass 28, count 0 2006.285.08:01:58.46#ibcon#read 6, iclass 28, count 0 2006.285.08:01:58.46#ibcon#end of sib2, iclass 28, count 0 2006.285.08:01:58.46#ibcon#*after write, iclass 28, count 0 2006.285.08:01:58.46#ibcon#*before return 0, iclass 28, count 0 2006.285.08:01:58.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:01:58.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:01:58.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:01:58.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:01:58.46$vck44/valo=5,734.99 2006.285.08:01:58.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.08:01:58.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.08:01:58.46#ibcon#ireg 17 cls_cnt 0 2006.285.08:01:58.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:01:58.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:01:58.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:01:58.46#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:01:58.46#ibcon#first serial, iclass 30, count 0 2006.285.08:01:58.46#ibcon#enter sib2, iclass 30, count 0 2006.285.08:01:58.46#ibcon#flushed, iclass 30, count 0 2006.285.08:01:58.46#ibcon#about to write, iclass 30, count 0 2006.285.08:01:58.46#ibcon#wrote, iclass 30, count 0 2006.285.08:01:58.46#ibcon#about to read 3, iclass 30, count 0 2006.285.08:01:58.48#ibcon#read 3, iclass 30, count 0 2006.285.08:01:58.48#ibcon#about to read 4, iclass 30, count 0 2006.285.08:01:58.48#ibcon#read 4, iclass 30, count 0 2006.285.08:01:58.48#ibcon#about to read 5, iclass 30, count 0 2006.285.08:01:58.48#ibcon#read 5, iclass 30, count 0 2006.285.08:01:58.48#ibcon#about to read 6, iclass 30, count 0 2006.285.08:01:58.48#ibcon#read 6, iclass 30, count 0 2006.285.08:01:58.48#ibcon#end of sib2, iclass 30, count 0 2006.285.08:01:58.48#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:01:58.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:01:58.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:01:58.48#ibcon#*before write, iclass 30, count 0 2006.285.08:01:58.48#ibcon#enter sib2, iclass 30, count 0 2006.285.08:01:58.48#ibcon#flushed, iclass 30, count 0 2006.285.08:01:58.48#ibcon#about to write, iclass 30, count 0 2006.285.08:01:58.48#ibcon#wrote, iclass 30, count 0 2006.285.08:01:58.48#ibcon#about to read 3, iclass 30, count 0 2006.285.08:01:58.52#ibcon#read 3, iclass 30, count 0 2006.285.08:01:58.52#ibcon#about to read 4, iclass 30, count 0 2006.285.08:01:58.52#ibcon#read 4, iclass 30, count 0 2006.285.08:01:58.52#ibcon#about to read 5, iclass 30, count 0 2006.285.08:01:58.52#ibcon#read 5, iclass 30, count 0 2006.285.08:01:58.52#ibcon#about to read 6, iclass 30, count 0 2006.285.08:01:58.52#ibcon#read 6, iclass 30, count 0 2006.285.08:01:58.52#ibcon#end of sib2, iclass 30, count 0 2006.285.08:01:58.52#ibcon#*after write, iclass 30, count 0 2006.285.08:01:58.52#ibcon#*before return 0, iclass 30, count 0 2006.285.08:01:58.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:01:58.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:01:58.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:01:58.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:01:58.52$vck44/va=5,3 2006.285.08:01:58.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.08:01:58.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.08:01:58.52#ibcon#ireg 11 cls_cnt 2 2006.285.08:01:58.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:01:58.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:01:58.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:01:58.58#ibcon#enter wrdev, iclass 32, count 2 2006.285.08:01:58.58#ibcon#first serial, iclass 32, count 2 2006.285.08:01:58.58#ibcon#enter sib2, iclass 32, count 2 2006.285.08:01:58.58#ibcon#flushed, iclass 32, count 2 2006.285.08:01:58.58#ibcon#about to write, iclass 32, count 2 2006.285.08:01:58.58#ibcon#wrote, iclass 32, count 2 2006.285.08:01:58.58#ibcon#about to read 3, iclass 32, count 2 2006.285.08:01:58.60#ibcon#read 3, iclass 32, count 2 2006.285.08:01:58.60#ibcon#about to read 4, iclass 32, count 2 2006.285.08:01:58.60#ibcon#read 4, iclass 32, count 2 2006.285.08:01:58.60#ibcon#about to read 5, iclass 32, count 2 2006.285.08:01:58.60#ibcon#read 5, iclass 32, count 2 2006.285.08:01:58.60#ibcon#about to read 6, iclass 32, count 2 2006.285.08:01:58.60#ibcon#read 6, iclass 32, count 2 2006.285.08:01:58.60#ibcon#end of sib2, iclass 32, count 2 2006.285.08:01:58.60#ibcon#*mode == 0, iclass 32, count 2 2006.285.08:01:58.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.08:01:58.60#ibcon#[25=AT05-03\r\n] 2006.285.08:01:58.60#ibcon#*before write, iclass 32, count 2 2006.285.08:01:58.60#ibcon#enter sib2, iclass 32, count 2 2006.285.08:01:58.60#ibcon#flushed, iclass 32, count 2 2006.285.08:01:58.60#ibcon#about to write, iclass 32, count 2 2006.285.08:01:58.60#ibcon#wrote, iclass 32, count 2 2006.285.08:01:58.60#ibcon#about to read 3, iclass 32, count 2 2006.285.08:01:58.63#ibcon#read 3, iclass 32, count 2 2006.285.08:01:58.63#ibcon#about to read 4, iclass 32, count 2 2006.285.08:01:58.63#ibcon#read 4, iclass 32, count 2 2006.285.08:01:58.63#ibcon#about to read 5, iclass 32, count 2 2006.285.08:01:58.63#ibcon#read 5, iclass 32, count 2 2006.285.08:01:58.63#ibcon#about to read 6, iclass 32, count 2 2006.285.08:01:58.63#ibcon#read 6, iclass 32, count 2 2006.285.08:01:58.63#ibcon#end of sib2, iclass 32, count 2 2006.285.08:01:58.63#ibcon#*after write, iclass 32, count 2 2006.285.08:01:58.63#ibcon#*before return 0, iclass 32, count 2 2006.285.08:01:58.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:01:58.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:01:58.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.08:01:58.63#ibcon#ireg 7 cls_cnt 0 2006.285.08:01:58.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:01:58.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:01:58.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:01:58.75#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:01:58.75#ibcon#first serial, iclass 32, count 0 2006.285.08:01:58.75#ibcon#enter sib2, iclass 32, count 0 2006.285.08:01:58.75#ibcon#flushed, iclass 32, count 0 2006.285.08:01:58.75#ibcon#about to write, iclass 32, count 0 2006.285.08:01:58.75#ibcon#wrote, iclass 32, count 0 2006.285.08:01:58.75#ibcon#about to read 3, iclass 32, count 0 2006.285.08:01:58.77#ibcon#read 3, iclass 32, count 0 2006.285.08:01:58.77#ibcon#about to read 4, iclass 32, count 0 2006.285.08:01:58.77#ibcon#read 4, iclass 32, count 0 2006.285.08:01:58.77#ibcon#about to read 5, iclass 32, count 0 2006.285.08:01:58.77#ibcon#read 5, iclass 32, count 0 2006.285.08:01:58.77#ibcon#about to read 6, iclass 32, count 0 2006.285.08:01:58.77#ibcon#read 6, iclass 32, count 0 2006.285.08:01:58.77#ibcon#end of sib2, iclass 32, count 0 2006.285.08:01:58.77#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:01:58.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:01:58.77#ibcon#[25=USB\r\n] 2006.285.08:01:58.77#ibcon#*before write, iclass 32, count 0 2006.285.08:01:58.77#ibcon#enter sib2, iclass 32, count 0 2006.285.08:01:58.77#ibcon#flushed, iclass 32, count 0 2006.285.08:01:58.77#ibcon#about to write, iclass 32, count 0 2006.285.08:01:58.77#ibcon#wrote, iclass 32, count 0 2006.285.08:01:58.77#ibcon#about to read 3, iclass 32, count 0 2006.285.08:01:58.80#ibcon#read 3, iclass 32, count 0 2006.285.08:01:58.80#ibcon#about to read 4, iclass 32, count 0 2006.285.08:01:58.80#ibcon#read 4, iclass 32, count 0 2006.285.08:01:58.80#ibcon#about to read 5, iclass 32, count 0 2006.285.08:01:58.80#ibcon#read 5, iclass 32, count 0 2006.285.08:01:58.80#ibcon#about to read 6, iclass 32, count 0 2006.285.08:01:58.80#ibcon#read 6, iclass 32, count 0 2006.285.08:01:58.80#ibcon#end of sib2, iclass 32, count 0 2006.285.08:01:58.80#ibcon#*after write, iclass 32, count 0 2006.285.08:01:58.80#ibcon#*before return 0, iclass 32, count 0 2006.285.08:01:58.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:01:58.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:01:58.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:01:58.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:01:58.80$vck44/valo=6,814.99 2006.285.08:01:58.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.08:01:58.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.08:01:58.80#ibcon#ireg 17 cls_cnt 0 2006.285.08:01:58.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:01:58.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:01:58.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:01:58.80#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:01:58.80#ibcon#first serial, iclass 34, count 0 2006.285.08:01:58.80#ibcon#enter sib2, iclass 34, count 0 2006.285.08:01:58.80#ibcon#flushed, iclass 34, count 0 2006.285.08:01:58.80#ibcon#about to write, iclass 34, count 0 2006.285.08:01:58.80#ibcon#wrote, iclass 34, count 0 2006.285.08:01:58.80#ibcon#about to read 3, iclass 34, count 0 2006.285.08:01:58.82#ibcon#read 3, iclass 34, count 0 2006.285.08:01:58.82#ibcon#about to read 4, iclass 34, count 0 2006.285.08:01:58.82#ibcon#read 4, iclass 34, count 0 2006.285.08:01:58.82#ibcon#about to read 5, iclass 34, count 0 2006.285.08:01:58.82#ibcon#read 5, iclass 34, count 0 2006.285.08:01:58.82#ibcon#about to read 6, iclass 34, count 0 2006.285.08:01:58.82#ibcon#read 6, iclass 34, count 0 2006.285.08:01:58.82#ibcon#end of sib2, iclass 34, count 0 2006.285.08:01:58.82#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:01:58.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:01:58.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:01:58.82#ibcon#*before write, iclass 34, count 0 2006.285.08:01:58.82#ibcon#enter sib2, iclass 34, count 0 2006.285.08:01:58.82#ibcon#flushed, iclass 34, count 0 2006.285.08:01:58.82#ibcon#about to write, iclass 34, count 0 2006.285.08:01:58.82#ibcon#wrote, iclass 34, count 0 2006.285.08:01:58.82#ibcon#about to read 3, iclass 34, count 0 2006.285.08:01:58.86#ibcon#read 3, iclass 34, count 0 2006.285.08:01:58.86#ibcon#about to read 4, iclass 34, count 0 2006.285.08:01:58.86#ibcon#read 4, iclass 34, count 0 2006.285.08:01:58.86#ibcon#about to read 5, iclass 34, count 0 2006.285.08:01:58.86#ibcon#read 5, iclass 34, count 0 2006.285.08:01:58.86#ibcon#about to read 6, iclass 34, count 0 2006.285.08:01:58.86#ibcon#read 6, iclass 34, count 0 2006.285.08:01:58.86#ibcon#end of sib2, iclass 34, count 0 2006.285.08:01:58.86#ibcon#*after write, iclass 34, count 0 2006.285.08:01:58.86#ibcon#*before return 0, iclass 34, count 0 2006.285.08:01:58.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:01:58.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:01:58.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:01:58.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:01:58.86$vck44/va=6,4 2006.285.08:01:58.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.08:01:58.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.08:01:58.86#ibcon#ireg 11 cls_cnt 2 2006.285.08:01:58.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:01:58.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:01:58.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:01:58.92#ibcon#enter wrdev, iclass 36, count 2 2006.285.08:01:58.92#ibcon#first serial, iclass 36, count 2 2006.285.08:01:58.92#ibcon#enter sib2, iclass 36, count 2 2006.285.08:01:58.92#ibcon#flushed, iclass 36, count 2 2006.285.08:01:58.92#ibcon#about to write, iclass 36, count 2 2006.285.08:01:58.92#ibcon#wrote, iclass 36, count 2 2006.285.08:01:58.92#ibcon#about to read 3, iclass 36, count 2 2006.285.08:01:58.94#ibcon#read 3, iclass 36, count 2 2006.285.08:01:58.94#ibcon#about to read 4, iclass 36, count 2 2006.285.08:01:58.94#ibcon#read 4, iclass 36, count 2 2006.285.08:01:58.94#ibcon#about to read 5, iclass 36, count 2 2006.285.08:01:58.94#ibcon#read 5, iclass 36, count 2 2006.285.08:01:58.94#ibcon#about to read 6, iclass 36, count 2 2006.285.08:01:58.94#ibcon#read 6, iclass 36, count 2 2006.285.08:01:58.94#ibcon#end of sib2, iclass 36, count 2 2006.285.08:01:58.94#ibcon#*mode == 0, iclass 36, count 2 2006.285.08:01:58.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.08:01:58.94#ibcon#[25=AT06-04\r\n] 2006.285.08:01:58.94#ibcon#*before write, iclass 36, count 2 2006.285.08:01:58.94#ibcon#enter sib2, iclass 36, count 2 2006.285.08:01:58.94#ibcon#flushed, iclass 36, count 2 2006.285.08:01:58.94#ibcon#about to write, iclass 36, count 2 2006.285.08:01:58.94#ibcon#wrote, iclass 36, count 2 2006.285.08:01:58.94#ibcon#about to read 3, iclass 36, count 2 2006.285.08:01:58.97#ibcon#read 3, iclass 36, count 2 2006.285.08:01:58.97#ibcon#about to read 4, iclass 36, count 2 2006.285.08:01:58.97#ibcon#read 4, iclass 36, count 2 2006.285.08:01:58.97#ibcon#about to read 5, iclass 36, count 2 2006.285.08:01:58.97#ibcon#read 5, iclass 36, count 2 2006.285.08:01:58.97#ibcon#about to read 6, iclass 36, count 2 2006.285.08:01:58.97#ibcon#read 6, iclass 36, count 2 2006.285.08:01:58.97#ibcon#end of sib2, iclass 36, count 2 2006.285.08:01:58.97#ibcon#*after write, iclass 36, count 2 2006.285.08:01:58.97#ibcon#*before return 0, iclass 36, count 2 2006.285.08:01:58.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:01:58.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:01:58.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.08:01:58.97#ibcon#ireg 7 cls_cnt 0 2006.285.08:01:58.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:01:59.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:01:59.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:01:59.09#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:01:59.09#ibcon#first serial, iclass 36, count 0 2006.285.08:01:59.09#ibcon#enter sib2, iclass 36, count 0 2006.285.08:01:59.09#ibcon#flushed, iclass 36, count 0 2006.285.08:01:59.09#ibcon#about to write, iclass 36, count 0 2006.285.08:01:59.09#ibcon#wrote, iclass 36, count 0 2006.285.08:01:59.09#ibcon#about to read 3, iclass 36, count 0 2006.285.08:01:59.11#ibcon#read 3, iclass 36, count 0 2006.285.08:01:59.11#ibcon#about to read 4, iclass 36, count 0 2006.285.08:01:59.11#ibcon#read 4, iclass 36, count 0 2006.285.08:01:59.11#ibcon#about to read 5, iclass 36, count 0 2006.285.08:01:59.11#ibcon#read 5, iclass 36, count 0 2006.285.08:01:59.11#ibcon#about to read 6, iclass 36, count 0 2006.285.08:01:59.11#ibcon#read 6, iclass 36, count 0 2006.285.08:01:59.11#ibcon#end of sib2, iclass 36, count 0 2006.285.08:01:59.11#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:01:59.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:01:59.11#ibcon#[25=USB\r\n] 2006.285.08:01:59.11#ibcon#*before write, iclass 36, count 0 2006.285.08:01:59.11#ibcon#enter sib2, iclass 36, count 0 2006.285.08:01:59.11#ibcon#flushed, iclass 36, count 0 2006.285.08:01:59.11#ibcon#about to write, iclass 36, count 0 2006.285.08:01:59.11#ibcon#wrote, iclass 36, count 0 2006.285.08:01:59.11#ibcon#about to read 3, iclass 36, count 0 2006.285.08:01:59.14#ibcon#read 3, iclass 36, count 0 2006.285.08:01:59.14#ibcon#about to read 4, iclass 36, count 0 2006.285.08:01:59.14#ibcon#read 4, iclass 36, count 0 2006.285.08:01:59.14#ibcon#about to read 5, iclass 36, count 0 2006.285.08:01:59.14#ibcon#read 5, iclass 36, count 0 2006.285.08:01:59.14#ibcon#about to read 6, iclass 36, count 0 2006.285.08:01:59.14#ibcon#read 6, iclass 36, count 0 2006.285.08:01:59.14#ibcon#end of sib2, iclass 36, count 0 2006.285.08:01:59.14#ibcon#*after write, iclass 36, count 0 2006.285.08:01:59.14#ibcon#*before return 0, iclass 36, count 0 2006.285.08:01:59.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:01:59.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:01:59.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:01:59.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:01:59.14$vck44/valo=7,864.99 2006.285.08:01:59.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.08:01:59.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.08:01:59.14#ibcon#ireg 17 cls_cnt 0 2006.285.08:01:59.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:01:59.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:01:59.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:01:59.14#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:01:59.14#ibcon#first serial, iclass 38, count 0 2006.285.08:01:59.14#ibcon#enter sib2, iclass 38, count 0 2006.285.08:01:59.14#ibcon#flushed, iclass 38, count 0 2006.285.08:01:59.14#ibcon#about to write, iclass 38, count 0 2006.285.08:01:59.14#ibcon#wrote, iclass 38, count 0 2006.285.08:01:59.14#ibcon#about to read 3, iclass 38, count 0 2006.285.08:01:59.16#ibcon#read 3, iclass 38, count 0 2006.285.08:01:59.16#ibcon#about to read 4, iclass 38, count 0 2006.285.08:01:59.16#ibcon#read 4, iclass 38, count 0 2006.285.08:01:59.16#ibcon#about to read 5, iclass 38, count 0 2006.285.08:01:59.16#ibcon#read 5, iclass 38, count 0 2006.285.08:01:59.16#ibcon#about to read 6, iclass 38, count 0 2006.285.08:01:59.16#ibcon#read 6, iclass 38, count 0 2006.285.08:01:59.16#ibcon#end of sib2, iclass 38, count 0 2006.285.08:01:59.16#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:01:59.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:01:59.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:01:59.16#ibcon#*before write, iclass 38, count 0 2006.285.08:01:59.16#ibcon#enter sib2, iclass 38, count 0 2006.285.08:01:59.16#ibcon#flushed, iclass 38, count 0 2006.285.08:01:59.16#ibcon#about to write, iclass 38, count 0 2006.285.08:01:59.16#ibcon#wrote, iclass 38, count 0 2006.285.08:01:59.16#ibcon#about to read 3, iclass 38, count 0 2006.285.08:01:59.20#ibcon#read 3, iclass 38, count 0 2006.285.08:01:59.20#ibcon#about to read 4, iclass 38, count 0 2006.285.08:01:59.20#ibcon#read 4, iclass 38, count 0 2006.285.08:01:59.20#ibcon#about to read 5, iclass 38, count 0 2006.285.08:01:59.20#ibcon#read 5, iclass 38, count 0 2006.285.08:01:59.20#ibcon#about to read 6, iclass 38, count 0 2006.285.08:01:59.20#ibcon#read 6, iclass 38, count 0 2006.285.08:01:59.20#ibcon#end of sib2, iclass 38, count 0 2006.285.08:01:59.20#ibcon#*after write, iclass 38, count 0 2006.285.08:01:59.20#ibcon#*before return 0, iclass 38, count 0 2006.285.08:01:59.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:01:59.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:01:59.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:01:59.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:01:59.20$vck44/va=7,4 2006.285.08:01:59.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.08:01:59.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.08:01:59.20#ibcon#ireg 11 cls_cnt 2 2006.285.08:01:59.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:01:59.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:01:59.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:01:59.26#ibcon#enter wrdev, iclass 40, count 2 2006.285.08:01:59.26#ibcon#first serial, iclass 40, count 2 2006.285.08:01:59.26#ibcon#enter sib2, iclass 40, count 2 2006.285.08:01:59.26#ibcon#flushed, iclass 40, count 2 2006.285.08:01:59.26#ibcon#about to write, iclass 40, count 2 2006.285.08:01:59.26#ibcon#wrote, iclass 40, count 2 2006.285.08:01:59.26#ibcon#about to read 3, iclass 40, count 2 2006.285.08:01:59.28#ibcon#read 3, iclass 40, count 2 2006.285.08:01:59.28#ibcon#about to read 4, iclass 40, count 2 2006.285.08:01:59.28#ibcon#read 4, iclass 40, count 2 2006.285.08:01:59.28#ibcon#about to read 5, iclass 40, count 2 2006.285.08:01:59.28#ibcon#read 5, iclass 40, count 2 2006.285.08:01:59.28#ibcon#about to read 6, iclass 40, count 2 2006.285.08:01:59.28#ibcon#read 6, iclass 40, count 2 2006.285.08:01:59.28#ibcon#end of sib2, iclass 40, count 2 2006.285.08:01:59.28#ibcon#*mode == 0, iclass 40, count 2 2006.285.08:01:59.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.08:01:59.28#ibcon#[25=AT07-04\r\n] 2006.285.08:01:59.28#ibcon#*before write, iclass 40, count 2 2006.285.08:01:59.28#ibcon#enter sib2, iclass 40, count 2 2006.285.08:01:59.28#ibcon#flushed, iclass 40, count 2 2006.285.08:01:59.28#ibcon#about to write, iclass 40, count 2 2006.285.08:01:59.28#ibcon#wrote, iclass 40, count 2 2006.285.08:01:59.28#ibcon#about to read 3, iclass 40, count 2 2006.285.08:01:59.31#ibcon#read 3, iclass 40, count 2 2006.285.08:01:59.31#ibcon#about to read 4, iclass 40, count 2 2006.285.08:01:59.31#ibcon#read 4, iclass 40, count 2 2006.285.08:01:59.31#ibcon#about to read 5, iclass 40, count 2 2006.285.08:01:59.31#ibcon#read 5, iclass 40, count 2 2006.285.08:01:59.31#ibcon#about to read 6, iclass 40, count 2 2006.285.08:01:59.31#ibcon#read 6, iclass 40, count 2 2006.285.08:01:59.31#ibcon#end of sib2, iclass 40, count 2 2006.285.08:01:59.31#ibcon#*after write, iclass 40, count 2 2006.285.08:01:59.31#ibcon#*before return 0, iclass 40, count 2 2006.285.08:01:59.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:01:59.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:01:59.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.08:01:59.31#ibcon#ireg 7 cls_cnt 0 2006.285.08:01:59.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:01:59.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:01:59.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:01:59.43#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:01:59.43#ibcon#first serial, iclass 40, count 0 2006.285.08:01:59.43#ibcon#enter sib2, iclass 40, count 0 2006.285.08:01:59.43#ibcon#flushed, iclass 40, count 0 2006.285.08:01:59.43#ibcon#about to write, iclass 40, count 0 2006.285.08:01:59.43#ibcon#wrote, iclass 40, count 0 2006.285.08:01:59.43#ibcon#about to read 3, iclass 40, count 0 2006.285.08:01:59.45#ibcon#read 3, iclass 40, count 0 2006.285.08:01:59.45#ibcon#about to read 4, iclass 40, count 0 2006.285.08:01:59.45#ibcon#read 4, iclass 40, count 0 2006.285.08:01:59.45#ibcon#about to read 5, iclass 40, count 0 2006.285.08:01:59.45#ibcon#read 5, iclass 40, count 0 2006.285.08:01:59.45#ibcon#about to read 6, iclass 40, count 0 2006.285.08:01:59.45#ibcon#read 6, iclass 40, count 0 2006.285.08:01:59.45#ibcon#end of sib2, iclass 40, count 0 2006.285.08:01:59.45#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:01:59.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:01:59.45#ibcon#[25=USB\r\n] 2006.285.08:01:59.45#ibcon#*before write, iclass 40, count 0 2006.285.08:01:59.45#ibcon#enter sib2, iclass 40, count 0 2006.285.08:01:59.45#ibcon#flushed, iclass 40, count 0 2006.285.08:01:59.45#ibcon#about to write, iclass 40, count 0 2006.285.08:01:59.45#ibcon#wrote, iclass 40, count 0 2006.285.08:01:59.45#ibcon#about to read 3, iclass 40, count 0 2006.285.08:01:59.48#ibcon#read 3, iclass 40, count 0 2006.285.08:01:59.48#ibcon#about to read 4, iclass 40, count 0 2006.285.08:01:59.48#ibcon#read 4, iclass 40, count 0 2006.285.08:01:59.48#ibcon#about to read 5, iclass 40, count 0 2006.285.08:01:59.48#ibcon#read 5, iclass 40, count 0 2006.285.08:01:59.48#ibcon#about to read 6, iclass 40, count 0 2006.285.08:01:59.48#ibcon#read 6, iclass 40, count 0 2006.285.08:01:59.48#ibcon#end of sib2, iclass 40, count 0 2006.285.08:01:59.48#ibcon#*after write, iclass 40, count 0 2006.285.08:01:59.48#ibcon#*before return 0, iclass 40, count 0 2006.285.08:01:59.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:01:59.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:01:59.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:01:59.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:01:59.48$vck44/valo=8,884.99 2006.285.08:01:59.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.08:01:59.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.08:01:59.48#ibcon#ireg 17 cls_cnt 0 2006.285.08:01:59.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:01:59.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:01:59.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:01:59.48#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:01:59.48#ibcon#first serial, iclass 4, count 0 2006.285.08:01:59.48#ibcon#enter sib2, iclass 4, count 0 2006.285.08:01:59.48#ibcon#flushed, iclass 4, count 0 2006.285.08:01:59.48#ibcon#about to write, iclass 4, count 0 2006.285.08:01:59.48#ibcon#wrote, iclass 4, count 0 2006.285.08:01:59.48#ibcon#about to read 3, iclass 4, count 0 2006.285.08:01:59.50#ibcon#read 3, iclass 4, count 0 2006.285.08:01:59.50#ibcon#about to read 4, iclass 4, count 0 2006.285.08:01:59.50#ibcon#read 4, iclass 4, count 0 2006.285.08:01:59.50#ibcon#about to read 5, iclass 4, count 0 2006.285.08:01:59.50#ibcon#read 5, iclass 4, count 0 2006.285.08:01:59.50#ibcon#about to read 6, iclass 4, count 0 2006.285.08:01:59.50#ibcon#read 6, iclass 4, count 0 2006.285.08:01:59.50#ibcon#end of sib2, iclass 4, count 0 2006.285.08:01:59.50#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:01:59.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:01:59.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:01:59.50#ibcon#*before write, iclass 4, count 0 2006.285.08:01:59.50#ibcon#enter sib2, iclass 4, count 0 2006.285.08:01:59.50#ibcon#flushed, iclass 4, count 0 2006.285.08:01:59.50#ibcon#about to write, iclass 4, count 0 2006.285.08:01:59.50#ibcon#wrote, iclass 4, count 0 2006.285.08:01:59.50#ibcon#about to read 3, iclass 4, count 0 2006.285.08:01:59.54#ibcon#read 3, iclass 4, count 0 2006.285.08:01:59.54#ibcon#about to read 4, iclass 4, count 0 2006.285.08:01:59.54#ibcon#read 4, iclass 4, count 0 2006.285.08:01:59.54#ibcon#about to read 5, iclass 4, count 0 2006.285.08:01:59.54#ibcon#read 5, iclass 4, count 0 2006.285.08:01:59.54#ibcon#about to read 6, iclass 4, count 0 2006.285.08:01:59.54#ibcon#read 6, iclass 4, count 0 2006.285.08:01:59.54#ibcon#end of sib2, iclass 4, count 0 2006.285.08:01:59.54#ibcon#*after write, iclass 4, count 0 2006.285.08:01:59.54#ibcon#*before return 0, iclass 4, count 0 2006.285.08:01:59.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:01:59.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:01:59.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:01:59.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:01:59.54$vck44/va=8,3 2006.285.08:01:59.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.08:01:59.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.08:01:59.54#ibcon#ireg 11 cls_cnt 2 2006.285.08:01:59.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:01:59.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:01:59.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:01:59.60#ibcon#enter wrdev, iclass 6, count 2 2006.285.08:01:59.60#ibcon#first serial, iclass 6, count 2 2006.285.08:01:59.60#ibcon#enter sib2, iclass 6, count 2 2006.285.08:01:59.60#ibcon#flushed, iclass 6, count 2 2006.285.08:01:59.60#ibcon#about to write, iclass 6, count 2 2006.285.08:01:59.60#ibcon#wrote, iclass 6, count 2 2006.285.08:01:59.60#ibcon#about to read 3, iclass 6, count 2 2006.285.08:01:59.62#ibcon#read 3, iclass 6, count 2 2006.285.08:01:59.62#ibcon#about to read 4, iclass 6, count 2 2006.285.08:01:59.62#ibcon#read 4, iclass 6, count 2 2006.285.08:01:59.62#ibcon#about to read 5, iclass 6, count 2 2006.285.08:01:59.62#ibcon#read 5, iclass 6, count 2 2006.285.08:01:59.62#ibcon#about to read 6, iclass 6, count 2 2006.285.08:01:59.62#ibcon#read 6, iclass 6, count 2 2006.285.08:01:59.62#ibcon#end of sib2, iclass 6, count 2 2006.285.08:01:59.62#ibcon#*mode == 0, iclass 6, count 2 2006.285.08:01:59.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.08:01:59.62#ibcon#[25=AT08-03\r\n] 2006.285.08:01:59.62#ibcon#*before write, iclass 6, count 2 2006.285.08:01:59.62#ibcon#enter sib2, iclass 6, count 2 2006.285.08:01:59.62#ibcon#flushed, iclass 6, count 2 2006.285.08:01:59.62#ibcon#about to write, iclass 6, count 2 2006.285.08:01:59.62#ibcon#wrote, iclass 6, count 2 2006.285.08:01:59.62#ibcon#about to read 3, iclass 6, count 2 2006.285.08:01:59.65#ibcon#read 3, iclass 6, count 2 2006.285.08:01:59.65#ibcon#about to read 4, iclass 6, count 2 2006.285.08:01:59.65#ibcon#read 4, iclass 6, count 2 2006.285.08:01:59.65#ibcon#about to read 5, iclass 6, count 2 2006.285.08:01:59.65#ibcon#read 5, iclass 6, count 2 2006.285.08:01:59.65#ibcon#about to read 6, iclass 6, count 2 2006.285.08:01:59.65#ibcon#read 6, iclass 6, count 2 2006.285.08:01:59.65#ibcon#end of sib2, iclass 6, count 2 2006.285.08:01:59.65#ibcon#*after write, iclass 6, count 2 2006.285.08:01:59.65#ibcon#*before return 0, iclass 6, count 2 2006.285.08:01:59.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:01:59.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:01:59.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.08:01:59.65#ibcon#ireg 7 cls_cnt 0 2006.285.08:01:59.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:01:59.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:01:59.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:01:59.77#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:01:59.77#ibcon#first serial, iclass 6, count 0 2006.285.08:01:59.77#ibcon#enter sib2, iclass 6, count 0 2006.285.08:01:59.77#ibcon#flushed, iclass 6, count 0 2006.285.08:01:59.77#ibcon#about to write, iclass 6, count 0 2006.285.08:01:59.77#ibcon#wrote, iclass 6, count 0 2006.285.08:01:59.77#ibcon#about to read 3, iclass 6, count 0 2006.285.08:01:59.79#ibcon#read 3, iclass 6, count 0 2006.285.08:01:59.79#ibcon#about to read 4, iclass 6, count 0 2006.285.08:01:59.79#ibcon#read 4, iclass 6, count 0 2006.285.08:01:59.79#ibcon#about to read 5, iclass 6, count 0 2006.285.08:01:59.79#ibcon#read 5, iclass 6, count 0 2006.285.08:01:59.79#ibcon#about to read 6, iclass 6, count 0 2006.285.08:01:59.79#ibcon#read 6, iclass 6, count 0 2006.285.08:01:59.79#ibcon#end of sib2, iclass 6, count 0 2006.285.08:01:59.79#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:01:59.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:01:59.79#ibcon#[25=USB\r\n] 2006.285.08:01:59.79#ibcon#*before write, iclass 6, count 0 2006.285.08:01:59.79#ibcon#enter sib2, iclass 6, count 0 2006.285.08:01:59.79#ibcon#flushed, iclass 6, count 0 2006.285.08:01:59.79#ibcon#about to write, iclass 6, count 0 2006.285.08:01:59.79#ibcon#wrote, iclass 6, count 0 2006.285.08:01:59.79#ibcon#about to read 3, iclass 6, count 0 2006.285.08:01:59.82#ibcon#read 3, iclass 6, count 0 2006.285.08:01:59.82#ibcon#about to read 4, iclass 6, count 0 2006.285.08:01:59.82#ibcon#read 4, iclass 6, count 0 2006.285.08:01:59.82#ibcon#about to read 5, iclass 6, count 0 2006.285.08:01:59.82#ibcon#read 5, iclass 6, count 0 2006.285.08:01:59.82#ibcon#about to read 6, iclass 6, count 0 2006.285.08:01:59.82#ibcon#read 6, iclass 6, count 0 2006.285.08:01:59.82#ibcon#end of sib2, iclass 6, count 0 2006.285.08:01:59.82#ibcon#*after write, iclass 6, count 0 2006.285.08:01:59.82#ibcon#*before return 0, iclass 6, count 0 2006.285.08:01:59.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:01:59.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:01:59.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:01:59.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:01:59.82$vck44/vblo=1,629.99 2006.285.08:01:59.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.08:01:59.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.08:01:59.82#ibcon#ireg 17 cls_cnt 0 2006.285.08:01:59.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:01:59.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:01:59.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:01:59.82#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:01:59.82#ibcon#first serial, iclass 10, count 0 2006.285.08:01:59.82#ibcon#enter sib2, iclass 10, count 0 2006.285.08:01:59.82#ibcon#flushed, iclass 10, count 0 2006.285.08:01:59.82#ibcon#about to write, iclass 10, count 0 2006.285.08:01:59.82#ibcon#wrote, iclass 10, count 0 2006.285.08:01:59.82#ibcon#about to read 3, iclass 10, count 0 2006.285.08:01:59.84#ibcon#read 3, iclass 10, count 0 2006.285.08:01:59.84#ibcon#about to read 4, iclass 10, count 0 2006.285.08:01:59.84#ibcon#read 4, iclass 10, count 0 2006.285.08:01:59.84#ibcon#about to read 5, iclass 10, count 0 2006.285.08:01:59.84#ibcon#read 5, iclass 10, count 0 2006.285.08:01:59.84#ibcon#about to read 6, iclass 10, count 0 2006.285.08:01:59.84#ibcon#read 6, iclass 10, count 0 2006.285.08:01:59.84#ibcon#end of sib2, iclass 10, count 0 2006.285.08:01:59.84#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:01:59.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:01:59.84#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:01:59.84#ibcon#*before write, iclass 10, count 0 2006.285.08:01:59.84#ibcon#enter sib2, iclass 10, count 0 2006.285.08:01:59.84#ibcon#flushed, iclass 10, count 0 2006.285.08:01:59.84#ibcon#about to write, iclass 10, count 0 2006.285.08:01:59.84#ibcon#wrote, iclass 10, count 0 2006.285.08:01:59.84#ibcon#about to read 3, iclass 10, count 0 2006.285.08:01:59.88#ibcon#read 3, iclass 10, count 0 2006.285.08:01:59.88#ibcon#about to read 4, iclass 10, count 0 2006.285.08:01:59.88#ibcon#read 4, iclass 10, count 0 2006.285.08:01:59.88#ibcon#about to read 5, iclass 10, count 0 2006.285.08:01:59.88#ibcon#read 5, iclass 10, count 0 2006.285.08:01:59.88#ibcon#about to read 6, iclass 10, count 0 2006.285.08:01:59.88#ibcon#read 6, iclass 10, count 0 2006.285.08:01:59.88#ibcon#end of sib2, iclass 10, count 0 2006.285.08:01:59.88#ibcon#*after write, iclass 10, count 0 2006.285.08:01:59.88#ibcon#*before return 0, iclass 10, count 0 2006.285.08:01:59.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:01:59.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:01:59.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:01:59.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:01:59.88$vck44/vb=1,4 2006.285.08:01:59.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.08:01:59.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.08:01:59.88#ibcon#ireg 11 cls_cnt 2 2006.285.08:01:59.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:01:59.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:01:59.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:01:59.88#ibcon#enter wrdev, iclass 12, count 2 2006.285.08:01:59.88#ibcon#first serial, iclass 12, count 2 2006.285.08:01:59.88#ibcon#enter sib2, iclass 12, count 2 2006.285.08:01:59.88#ibcon#flushed, iclass 12, count 2 2006.285.08:01:59.88#ibcon#about to write, iclass 12, count 2 2006.285.08:01:59.88#ibcon#wrote, iclass 12, count 2 2006.285.08:01:59.88#ibcon#about to read 3, iclass 12, count 2 2006.285.08:01:59.90#ibcon#read 3, iclass 12, count 2 2006.285.08:01:59.90#ibcon#about to read 4, iclass 12, count 2 2006.285.08:01:59.90#ibcon#read 4, iclass 12, count 2 2006.285.08:01:59.90#ibcon#about to read 5, iclass 12, count 2 2006.285.08:01:59.90#ibcon#read 5, iclass 12, count 2 2006.285.08:01:59.90#ibcon#about to read 6, iclass 12, count 2 2006.285.08:01:59.90#ibcon#read 6, iclass 12, count 2 2006.285.08:01:59.90#ibcon#end of sib2, iclass 12, count 2 2006.285.08:01:59.90#ibcon#*mode == 0, iclass 12, count 2 2006.285.08:01:59.90#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.08:01:59.90#ibcon#[27=AT01-04\r\n] 2006.285.08:01:59.90#ibcon#*before write, iclass 12, count 2 2006.285.08:01:59.90#ibcon#enter sib2, iclass 12, count 2 2006.285.08:01:59.90#ibcon#flushed, iclass 12, count 2 2006.285.08:01:59.90#ibcon#about to write, iclass 12, count 2 2006.285.08:01:59.90#ibcon#wrote, iclass 12, count 2 2006.285.08:01:59.90#ibcon#about to read 3, iclass 12, count 2 2006.285.08:01:59.93#ibcon#read 3, iclass 12, count 2 2006.285.08:01:59.93#ibcon#about to read 4, iclass 12, count 2 2006.285.08:01:59.93#ibcon#read 4, iclass 12, count 2 2006.285.08:01:59.93#ibcon#about to read 5, iclass 12, count 2 2006.285.08:01:59.93#ibcon#read 5, iclass 12, count 2 2006.285.08:01:59.93#ibcon#about to read 6, iclass 12, count 2 2006.285.08:01:59.93#ibcon#read 6, iclass 12, count 2 2006.285.08:01:59.93#ibcon#end of sib2, iclass 12, count 2 2006.285.08:01:59.93#ibcon#*after write, iclass 12, count 2 2006.285.08:01:59.93#ibcon#*before return 0, iclass 12, count 2 2006.285.08:01:59.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:01:59.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:01:59.93#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.08:01:59.93#ibcon#ireg 7 cls_cnt 0 2006.285.08:01:59.93#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:02:00.05#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:02:00.05#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:02:00.05#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:02:00.05#ibcon#first serial, iclass 12, count 0 2006.285.08:02:00.05#ibcon#enter sib2, iclass 12, count 0 2006.285.08:02:00.05#ibcon#flushed, iclass 12, count 0 2006.285.08:02:00.05#ibcon#about to write, iclass 12, count 0 2006.285.08:02:00.05#ibcon#wrote, iclass 12, count 0 2006.285.08:02:00.05#ibcon#about to read 3, iclass 12, count 0 2006.285.08:02:00.07#ibcon#read 3, iclass 12, count 0 2006.285.08:02:00.07#ibcon#about to read 4, iclass 12, count 0 2006.285.08:02:00.07#ibcon#read 4, iclass 12, count 0 2006.285.08:02:00.07#ibcon#about to read 5, iclass 12, count 0 2006.285.08:02:00.07#ibcon#read 5, iclass 12, count 0 2006.285.08:02:00.07#ibcon#about to read 6, iclass 12, count 0 2006.285.08:02:00.07#ibcon#read 6, iclass 12, count 0 2006.285.08:02:00.07#ibcon#end of sib2, iclass 12, count 0 2006.285.08:02:00.07#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:02:00.07#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:02:00.07#ibcon#[27=USB\r\n] 2006.285.08:02:00.07#ibcon#*before write, iclass 12, count 0 2006.285.08:02:00.07#ibcon#enter sib2, iclass 12, count 0 2006.285.08:02:00.07#ibcon#flushed, iclass 12, count 0 2006.285.08:02:00.07#ibcon#about to write, iclass 12, count 0 2006.285.08:02:00.07#ibcon#wrote, iclass 12, count 0 2006.285.08:02:00.07#ibcon#about to read 3, iclass 12, count 0 2006.285.08:02:00.10#ibcon#read 3, iclass 12, count 0 2006.285.08:02:00.10#ibcon#about to read 4, iclass 12, count 0 2006.285.08:02:00.10#ibcon#read 4, iclass 12, count 0 2006.285.08:02:00.10#ibcon#about to read 5, iclass 12, count 0 2006.285.08:02:00.10#ibcon#read 5, iclass 12, count 0 2006.285.08:02:00.10#ibcon#about to read 6, iclass 12, count 0 2006.285.08:02:00.10#ibcon#read 6, iclass 12, count 0 2006.285.08:02:00.10#ibcon#end of sib2, iclass 12, count 0 2006.285.08:02:00.10#ibcon#*after write, iclass 12, count 0 2006.285.08:02:00.10#ibcon#*before return 0, iclass 12, count 0 2006.285.08:02:00.10#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:02:00.10#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:02:00.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:02:00.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:02:00.10$vck44/vblo=2,634.99 2006.285.08:02:00.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.08:02:00.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.08:02:00.10#ibcon#ireg 17 cls_cnt 0 2006.285.08:02:00.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:02:00.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:02:00.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:02:00.10#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:02:00.10#ibcon#first serial, iclass 14, count 0 2006.285.08:02:00.10#ibcon#enter sib2, iclass 14, count 0 2006.285.08:02:00.10#ibcon#flushed, iclass 14, count 0 2006.285.08:02:00.10#ibcon#about to write, iclass 14, count 0 2006.285.08:02:00.10#ibcon#wrote, iclass 14, count 0 2006.285.08:02:00.10#ibcon#about to read 3, iclass 14, count 0 2006.285.08:02:00.12#ibcon#read 3, iclass 14, count 0 2006.285.08:02:00.12#ibcon#about to read 4, iclass 14, count 0 2006.285.08:02:00.12#ibcon#read 4, iclass 14, count 0 2006.285.08:02:00.12#ibcon#about to read 5, iclass 14, count 0 2006.285.08:02:00.12#ibcon#read 5, iclass 14, count 0 2006.285.08:02:00.12#ibcon#about to read 6, iclass 14, count 0 2006.285.08:02:00.12#ibcon#read 6, iclass 14, count 0 2006.285.08:02:00.12#ibcon#end of sib2, iclass 14, count 0 2006.285.08:02:00.12#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:02:00.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:02:00.12#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:02:00.12#ibcon#*before write, iclass 14, count 0 2006.285.08:02:00.12#ibcon#enter sib2, iclass 14, count 0 2006.285.08:02:00.12#ibcon#flushed, iclass 14, count 0 2006.285.08:02:00.12#ibcon#about to write, iclass 14, count 0 2006.285.08:02:00.12#ibcon#wrote, iclass 14, count 0 2006.285.08:02:00.12#ibcon#about to read 3, iclass 14, count 0 2006.285.08:02:00.16#ibcon#read 3, iclass 14, count 0 2006.285.08:02:00.16#ibcon#about to read 4, iclass 14, count 0 2006.285.08:02:00.16#ibcon#read 4, iclass 14, count 0 2006.285.08:02:00.16#ibcon#about to read 5, iclass 14, count 0 2006.285.08:02:00.16#ibcon#read 5, iclass 14, count 0 2006.285.08:02:00.16#ibcon#about to read 6, iclass 14, count 0 2006.285.08:02:00.16#ibcon#read 6, iclass 14, count 0 2006.285.08:02:00.16#ibcon#end of sib2, iclass 14, count 0 2006.285.08:02:00.16#ibcon#*after write, iclass 14, count 0 2006.285.08:02:00.16#ibcon#*before return 0, iclass 14, count 0 2006.285.08:02:00.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:02:00.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:02:00.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:02:00.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:02:00.16$vck44/vb=2,5 2006.285.08:02:00.16#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.08:02:00.16#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.08:02:00.16#ibcon#ireg 11 cls_cnt 2 2006.285.08:02:00.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:02:00.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:02:00.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:02:00.22#ibcon#enter wrdev, iclass 16, count 2 2006.285.08:02:00.22#ibcon#first serial, iclass 16, count 2 2006.285.08:02:00.22#ibcon#enter sib2, iclass 16, count 2 2006.285.08:02:00.22#ibcon#flushed, iclass 16, count 2 2006.285.08:02:00.22#ibcon#about to write, iclass 16, count 2 2006.285.08:02:00.22#ibcon#wrote, iclass 16, count 2 2006.285.08:02:00.22#ibcon#about to read 3, iclass 16, count 2 2006.285.08:02:00.24#ibcon#read 3, iclass 16, count 2 2006.285.08:02:00.24#ibcon#about to read 4, iclass 16, count 2 2006.285.08:02:00.24#ibcon#read 4, iclass 16, count 2 2006.285.08:02:00.24#ibcon#about to read 5, iclass 16, count 2 2006.285.08:02:00.24#ibcon#read 5, iclass 16, count 2 2006.285.08:02:00.24#ibcon#about to read 6, iclass 16, count 2 2006.285.08:02:00.24#ibcon#read 6, iclass 16, count 2 2006.285.08:02:00.24#ibcon#end of sib2, iclass 16, count 2 2006.285.08:02:00.24#ibcon#*mode == 0, iclass 16, count 2 2006.285.08:02:00.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.08:02:00.24#ibcon#[27=AT02-05\r\n] 2006.285.08:02:00.24#ibcon#*before write, iclass 16, count 2 2006.285.08:02:00.24#ibcon#enter sib2, iclass 16, count 2 2006.285.08:02:00.24#ibcon#flushed, iclass 16, count 2 2006.285.08:02:00.24#ibcon#about to write, iclass 16, count 2 2006.285.08:02:00.24#ibcon#wrote, iclass 16, count 2 2006.285.08:02:00.24#ibcon#about to read 3, iclass 16, count 2 2006.285.08:02:00.27#ibcon#read 3, iclass 16, count 2 2006.285.08:02:00.27#ibcon#about to read 4, iclass 16, count 2 2006.285.08:02:00.27#ibcon#read 4, iclass 16, count 2 2006.285.08:02:00.27#ibcon#about to read 5, iclass 16, count 2 2006.285.08:02:00.27#ibcon#read 5, iclass 16, count 2 2006.285.08:02:00.27#ibcon#about to read 6, iclass 16, count 2 2006.285.08:02:00.27#ibcon#read 6, iclass 16, count 2 2006.285.08:02:00.27#ibcon#end of sib2, iclass 16, count 2 2006.285.08:02:00.27#ibcon#*after write, iclass 16, count 2 2006.285.08:02:00.27#ibcon#*before return 0, iclass 16, count 2 2006.285.08:02:00.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:02:00.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:02:00.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.08:02:00.27#ibcon#ireg 7 cls_cnt 0 2006.285.08:02:00.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:02:00.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:02:00.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:02:00.39#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:02:00.39#ibcon#first serial, iclass 16, count 0 2006.285.08:02:00.39#ibcon#enter sib2, iclass 16, count 0 2006.285.08:02:00.39#ibcon#flushed, iclass 16, count 0 2006.285.08:02:00.39#ibcon#about to write, iclass 16, count 0 2006.285.08:02:00.39#ibcon#wrote, iclass 16, count 0 2006.285.08:02:00.39#ibcon#about to read 3, iclass 16, count 0 2006.285.08:02:00.41#ibcon#read 3, iclass 16, count 0 2006.285.08:02:00.41#ibcon#about to read 4, iclass 16, count 0 2006.285.08:02:00.41#ibcon#read 4, iclass 16, count 0 2006.285.08:02:00.41#ibcon#about to read 5, iclass 16, count 0 2006.285.08:02:00.41#ibcon#read 5, iclass 16, count 0 2006.285.08:02:00.41#ibcon#about to read 6, iclass 16, count 0 2006.285.08:02:00.41#ibcon#read 6, iclass 16, count 0 2006.285.08:02:00.41#ibcon#end of sib2, iclass 16, count 0 2006.285.08:02:00.41#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:02:00.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:02:00.41#ibcon#[27=USB\r\n] 2006.285.08:02:00.41#ibcon#*before write, iclass 16, count 0 2006.285.08:02:00.41#ibcon#enter sib2, iclass 16, count 0 2006.285.08:02:00.41#ibcon#flushed, iclass 16, count 0 2006.285.08:02:00.41#ibcon#about to write, iclass 16, count 0 2006.285.08:02:00.41#ibcon#wrote, iclass 16, count 0 2006.285.08:02:00.41#ibcon#about to read 3, iclass 16, count 0 2006.285.08:02:00.44#ibcon#read 3, iclass 16, count 0 2006.285.08:02:00.44#ibcon#about to read 4, iclass 16, count 0 2006.285.08:02:00.44#ibcon#read 4, iclass 16, count 0 2006.285.08:02:00.44#ibcon#about to read 5, iclass 16, count 0 2006.285.08:02:00.44#ibcon#read 5, iclass 16, count 0 2006.285.08:02:00.44#ibcon#about to read 6, iclass 16, count 0 2006.285.08:02:00.44#ibcon#read 6, iclass 16, count 0 2006.285.08:02:00.44#ibcon#end of sib2, iclass 16, count 0 2006.285.08:02:00.44#ibcon#*after write, iclass 16, count 0 2006.285.08:02:00.44#ibcon#*before return 0, iclass 16, count 0 2006.285.08:02:00.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:02:00.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:02:00.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:02:00.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:02:00.44$vck44/vblo=3,649.99 2006.285.08:02:00.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.08:02:00.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.08:02:00.44#ibcon#ireg 17 cls_cnt 0 2006.285.08:02:00.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:02:00.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:02:00.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:02:00.44#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:02:00.44#ibcon#first serial, iclass 18, count 0 2006.285.08:02:00.44#ibcon#enter sib2, iclass 18, count 0 2006.285.08:02:00.44#ibcon#flushed, iclass 18, count 0 2006.285.08:02:00.44#ibcon#about to write, iclass 18, count 0 2006.285.08:02:00.44#ibcon#wrote, iclass 18, count 0 2006.285.08:02:00.44#ibcon#about to read 3, iclass 18, count 0 2006.285.08:02:00.46#ibcon#read 3, iclass 18, count 0 2006.285.08:02:00.46#ibcon#about to read 4, iclass 18, count 0 2006.285.08:02:00.46#ibcon#read 4, iclass 18, count 0 2006.285.08:02:00.46#ibcon#about to read 5, iclass 18, count 0 2006.285.08:02:00.46#ibcon#read 5, iclass 18, count 0 2006.285.08:02:00.46#ibcon#about to read 6, iclass 18, count 0 2006.285.08:02:00.46#ibcon#read 6, iclass 18, count 0 2006.285.08:02:00.46#ibcon#end of sib2, iclass 18, count 0 2006.285.08:02:00.46#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:02:00.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:02:00.46#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:02:00.46#ibcon#*before write, iclass 18, count 0 2006.285.08:02:00.46#ibcon#enter sib2, iclass 18, count 0 2006.285.08:02:00.46#ibcon#flushed, iclass 18, count 0 2006.285.08:02:00.46#ibcon#about to write, iclass 18, count 0 2006.285.08:02:00.46#ibcon#wrote, iclass 18, count 0 2006.285.08:02:00.46#ibcon#about to read 3, iclass 18, count 0 2006.285.08:02:00.50#ibcon#read 3, iclass 18, count 0 2006.285.08:02:00.50#ibcon#about to read 4, iclass 18, count 0 2006.285.08:02:00.50#ibcon#read 4, iclass 18, count 0 2006.285.08:02:00.50#ibcon#about to read 5, iclass 18, count 0 2006.285.08:02:00.50#ibcon#read 5, iclass 18, count 0 2006.285.08:02:00.50#ibcon#about to read 6, iclass 18, count 0 2006.285.08:02:00.50#ibcon#read 6, iclass 18, count 0 2006.285.08:02:00.50#ibcon#end of sib2, iclass 18, count 0 2006.285.08:02:00.50#ibcon#*after write, iclass 18, count 0 2006.285.08:02:00.50#ibcon#*before return 0, iclass 18, count 0 2006.285.08:02:00.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:02:00.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:02:00.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:02:00.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:02:00.50$vck44/vb=3,4 2006.285.08:02:00.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.08:02:00.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.08:02:00.50#ibcon#ireg 11 cls_cnt 2 2006.285.08:02:00.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:02:00.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:02:00.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:02:00.56#ibcon#enter wrdev, iclass 20, count 2 2006.285.08:02:00.56#ibcon#first serial, iclass 20, count 2 2006.285.08:02:00.56#ibcon#enter sib2, iclass 20, count 2 2006.285.08:02:00.56#ibcon#flushed, iclass 20, count 2 2006.285.08:02:00.56#ibcon#about to write, iclass 20, count 2 2006.285.08:02:00.56#ibcon#wrote, iclass 20, count 2 2006.285.08:02:00.56#ibcon#about to read 3, iclass 20, count 2 2006.285.08:02:00.58#ibcon#read 3, iclass 20, count 2 2006.285.08:02:00.58#ibcon#about to read 4, iclass 20, count 2 2006.285.08:02:00.58#ibcon#read 4, iclass 20, count 2 2006.285.08:02:00.58#ibcon#about to read 5, iclass 20, count 2 2006.285.08:02:00.58#ibcon#read 5, iclass 20, count 2 2006.285.08:02:00.58#ibcon#about to read 6, iclass 20, count 2 2006.285.08:02:00.58#ibcon#read 6, iclass 20, count 2 2006.285.08:02:00.58#ibcon#end of sib2, iclass 20, count 2 2006.285.08:02:00.58#ibcon#*mode == 0, iclass 20, count 2 2006.285.08:02:00.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.08:02:00.58#ibcon#[27=AT03-04\r\n] 2006.285.08:02:00.58#ibcon#*before write, iclass 20, count 2 2006.285.08:02:00.58#ibcon#enter sib2, iclass 20, count 2 2006.285.08:02:00.58#ibcon#flushed, iclass 20, count 2 2006.285.08:02:00.58#ibcon#about to write, iclass 20, count 2 2006.285.08:02:00.58#ibcon#wrote, iclass 20, count 2 2006.285.08:02:00.58#ibcon#about to read 3, iclass 20, count 2 2006.285.08:02:00.61#ibcon#read 3, iclass 20, count 2 2006.285.08:02:00.61#ibcon#about to read 4, iclass 20, count 2 2006.285.08:02:00.61#ibcon#read 4, iclass 20, count 2 2006.285.08:02:00.61#ibcon#about to read 5, iclass 20, count 2 2006.285.08:02:00.61#ibcon#read 5, iclass 20, count 2 2006.285.08:02:00.61#ibcon#about to read 6, iclass 20, count 2 2006.285.08:02:00.61#ibcon#read 6, iclass 20, count 2 2006.285.08:02:00.61#ibcon#end of sib2, iclass 20, count 2 2006.285.08:02:00.61#ibcon#*after write, iclass 20, count 2 2006.285.08:02:00.61#ibcon#*before return 0, iclass 20, count 2 2006.285.08:02:00.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:02:00.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:02:00.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.08:02:00.61#ibcon#ireg 7 cls_cnt 0 2006.285.08:02:00.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:02:00.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:02:00.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:02:00.73#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:02:00.73#ibcon#first serial, iclass 20, count 0 2006.285.08:02:00.73#ibcon#enter sib2, iclass 20, count 0 2006.285.08:02:00.73#ibcon#flushed, iclass 20, count 0 2006.285.08:02:00.73#ibcon#about to write, iclass 20, count 0 2006.285.08:02:00.73#ibcon#wrote, iclass 20, count 0 2006.285.08:02:00.73#ibcon#about to read 3, iclass 20, count 0 2006.285.08:02:00.75#ibcon#read 3, iclass 20, count 0 2006.285.08:02:00.75#ibcon#about to read 4, iclass 20, count 0 2006.285.08:02:00.75#ibcon#read 4, iclass 20, count 0 2006.285.08:02:00.75#ibcon#about to read 5, iclass 20, count 0 2006.285.08:02:00.75#ibcon#read 5, iclass 20, count 0 2006.285.08:02:00.75#ibcon#about to read 6, iclass 20, count 0 2006.285.08:02:00.75#ibcon#read 6, iclass 20, count 0 2006.285.08:02:00.75#ibcon#end of sib2, iclass 20, count 0 2006.285.08:02:00.75#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:02:00.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:02:00.75#ibcon#[27=USB\r\n] 2006.285.08:02:00.75#ibcon#*before write, iclass 20, count 0 2006.285.08:02:00.75#ibcon#enter sib2, iclass 20, count 0 2006.285.08:02:00.75#ibcon#flushed, iclass 20, count 0 2006.285.08:02:00.75#ibcon#about to write, iclass 20, count 0 2006.285.08:02:00.75#ibcon#wrote, iclass 20, count 0 2006.285.08:02:00.75#ibcon#about to read 3, iclass 20, count 0 2006.285.08:02:00.78#ibcon#read 3, iclass 20, count 0 2006.285.08:02:00.78#ibcon#about to read 4, iclass 20, count 0 2006.285.08:02:00.78#ibcon#read 4, iclass 20, count 0 2006.285.08:02:00.78#ibcon#about to read 5, iclass 20, count 0 2006.285.08:02:00.78#ibcon#read 5, iclass 20, count 0 2006.285.08:02:00.78#ibcon#about to read 6, iclass 20, count 0 2006.285.08:02:00.78#ibcon#read 6, iclass 20, count 0 2006.285.08:02:00.78#ibcon#end of sib2, iclass 20, count 0 2006.285.08:02:00.78#ibcon#*after write, iclass 20, count 0 2006.285.08:02:00.78#ibcon#*before return 0, iclass 20, count 0 2006.285.08:02:00.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:02:00.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:02:00.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:02:00.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:02:00.78$vck44/vblo=4,679.99 2006.285.08:02:00.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.08:02:00.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.08:02:00.78#ibcon#ireg 17 cls_cnt 0 2006.285.08:02:00.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:02:00.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:02:00.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:02:00.78#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:02:00.78#ibcon#first serial, iclass 22, count 0 2006.285.08:02:00.78#ibcon#enter sib2, iclass 22, count 0 2006.285.08:02:00.78#ibcon#flushed, iclass 22, count 0 2006.285.08:02:00.78#ibcon#about to write, iclass 22, count 0 2006.285.08:02:00.78#ibcon#wrote, iclass 22, count 0 2006.285.08:02:00.78#ibcon#about to read 3, iclass 22, count 0 2006.285.08:02:00.80#ibcon#read 3, iclass 22, count 0 2006.285.08:02:00.80#ibcon#about to read 4, iclass 22, count 0 2006.285.08:02:00.80#ibcon#read 4, iclass 22, count 0 2006.285.08:02:00.80#ibcon#about to read 5, iclass 22, count 0 2006.285.08:02:00.80#ibcon#read 5, iclass 22, count 0 2006.285.08:02:00.80#ibcon#about to read 6, iclass 22, count 0 2006.285.08:02:00.80#ibcon#read 6, iclass 22, count 0 2006.285.08:02:00.80#ibcon#end of sib2, iclass 22, count 0 2006.285.08:02:00.80#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:02:00.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:02:00.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:02:00.80#ibcon#*before write, iclass 22, count 0 2006.285.08:02:00.80#ibcon#enter sib2, iclass 22, count 0 2006.285.08:02:00.80#ibcon#flushed, iclass 22, count 0 2006.285.08:02:00.80#ibcon#about to write, iclass 22, count 0 2006.285.08:02:00.80#ibcon#wrote, iclass 22, count 0 2006.285.08:02:00.80#ibcon#about to read 3, iclass 22, count 0 2006.285.08:02:00.84#ibcon#read 3, iclass 22, count 0 2006.285.08:02:00.84#ibcon#about to read 4, iclass 22, count 0 2006.285.08:02:00.84#ibcon#read 4, iclass 22, count 0 2006.285.08:02:00.84#ibcon#about to read 5, iclass 22, count 0 2006.285.08:02:00.84#ibcon#read 5, iclass 22, count 0 2006.285.08:02:00.84#ibcon#about to read 6, iclass 22, count 0 2006.285.08:02:00.84#ibcon#read 6, iclass 22, count 0 2006.285.08:02:00.84#ibcon#end of sib2, iclass 22, count 0 2006.285.08:02:00.84#ibcon#*after write, iclass 22, count 0 2006.285.08:02:00.84#ibcon#*before return 0, iclass 22, count 0 2006.285.08:02:00.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:02:00.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:02:00.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:02:00.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:02:00.84$vck44/vb=4,5 2006.285.08:02:00.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.08:02:00.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.08:02:00.84#ibcon#ireg 11 cls_cnt 2 2006.285.08:02:00.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:02:00.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:02:00.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:02:00.90#ibcon#enter wrdev, iclass 24, count 2 2006.285.08:02:00.90#ibcon#first serial, iclass 24, count 2 2006.285.08:02:00.90#ibcon#enter sib2, iclass 24, count 2 2006.285.08:02:00.90#ibcon#flushed, iclass 24, count 2 2006.285.08:02:00.90#ibcon#about to write, iclass 24, count 2 2006.285.08:02:00.90#ibcon#wrote, iclass 24, count 2 2006.285.08:02:00.90#ibcon#about to read 3, iclass 24, count 2 2006.285.08:02:00.92#ibcon#read 3, iclass 24, count 2 2006.285.08:02:00.92#ibcon#about to read 4, iclass 24, count 2 2006.285.08:02:00.92#ibcon#read 4, iclass 24, count 2 2006.285.08:02:00.92#ibcon#about to read 5, iclass 24, count 2 2006.285.08:02:00.92#ibcon#read 5, iclass 24, count 2 2006.285.08:02:00.92#ibcon#about to read 6, iclass 24, count 2 2006.285.08:02:00.92#ibcon#read 6, iclass 24, count 2 2006.285.08:02:00.92#ibcon#end of sib2, iclass 24, count 2 2006.285.08:02:00.92#ibcon#*mode == 0, iclass 24, count 2 2006.285.08:02:00.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.08:02:00.92#ibcon#[27=AT04-05\r\n] 2006.285.08:02:00.92#ibcon#*before write, iclass 24, count 2 2006.285.08:02:00.92#ibcon#enter sib2, iclass 24, count 2 2006.285.08:02:00.92#ibcon#flushed, iclass 24, count 2 2006.285.08:02:00.92#ibcon#about to write, iclass 24, count 2 2006.285.08:02:00.92#ibcon#wrote, iclass 24, count 2 2006.285.08:02:00.92#ibcon#about to read 3, iclass 24, count 2 2006.285.08:02:00.95#ibcon#read 3, iclass 24, count 2 2006.285.08:02:00.95#ibcon#about to read 4, iclass 24, count 2 2006.285.08:02:00.95#ibcon#read 4, iclass 24, count 2 2006.285.08:02:00.95#ibcon#about to read 5, iclass 24, count 2 2006.285.08:02:00.95#ibcon#read 5, iclass 24, count 2 2006.285.08:02:00.95#ibcon#about to read 6, iclass 24, count 2 2006.285.08:02:00.95#ibcon#read 6, iclass 24, count 2 2006.285.08:02:00.95#ibcon#end of sib2, iclass 24, count 2 2006.285.08:02:00.95#ibcon#*after write, iclass 24, count 2 2006.285.08:02:00.95#ibcon#*before return 0, iclass 24, count 2 2006.285.08:02:00.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:02:00.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:02:00.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.08:02:00.95#ibcon#ireg 7 cls_cnt 0 2006.285.08:02:00.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:02:01.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:02:01.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:02:01.07#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:02:01.07#ibcon#first serial, iclass 24, count 0 2006.285.08:02:01.07#ibcon#enter sib2, iclass 24, count 0 2006.285.08:02:01.07#ibcon#flushed, iclass 24, count 0 2006.285.08:02:01.07#ibcon#about to write, iclass 24, count 0 2006.285.08:02:01.07#ibcon#wrote, iclass 24, count 0 2006.285.08:02:01.07#ibcon#about to read 3, iclass 24, count 0 2006.285.08:02:01.09#ibcon#read 3, iclass 24, count 0 2006.285.08:02:01.09#ibcon#about to read 4, iclass 24, count 0 2006.285.08:02:01.09#ibcon#read 4, iclass 24, count 0 2006.285.08:02:01.09#ibcon#about to read 5, iclass 24, count 0 2006.285.08:02:01.09#ibcon#read 5, iclass 24, count 0 2006.285.08:02:01.09#ibcon#about to read 6, iclass 24, count 0 2006.285.08:02:01.09#ibcon#read 6, iclass 24, count 0 2006.285.08:02:01.09#ibcon#end of sib2, iclass 24, count 0 2006.285.08:02:01.09#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:02:01.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:02:01.09#ibcon#[27=USB\r\n] 2006.285.08:02:01.09#ibcon#*before write, iclass 24, count 0 2006.285.08:02:01.09#ibcon#enter sib2, iclass 24, count 0 2006.285.08:02:01.09#ibcon#flushed, iclass 24, count 0 2006.285.08:02:01.09#ibcon#about to write, iclass 24, count 0 2006.285.08:02:01.09#ibcon#wrote, iclass 24, count 0 2006.285.08:02:01.09#ibcon#about to read 3, iclass 24, count 0 2006.285.08:02:01.12#ibcon#read 3, iclass 24, count 0 2006.285.08:02:01.12#ibcon#about to read 4, iclass 24, count 0 2006.285.08:02:01.12#ibcon#read 4, iclass 24, count 0 2006.285.08:02:01.12#ibcon#about to read 5, iclass 24, count 0 2006.285.08:02:01.12#ibcon#read 5, iclass 24, count 0 2006.285.08:02:01.12#ibcon#about to read 6, iclass 24, count 0 2006.285.08:02:01.12#ibcon#read 6, iclass 24, count 0 2006.285.08:02:01.12#ibcon#end of sib2, iclass 24, count 0 2006.285.08:02:01.12#ibcon#*after write, iclass 24, count 0 2006.285.08:02:01.12#ibcon#*before return 0, iclass 24, count 0 2006.285.08:02:01.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:02:01.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:02:01.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:02:01.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:02:01.12$vck44/vblo=5,709.99 2006.285.08:02:01.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.08:02:01.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.08:02:01.12#ibcon#ireg 17 cls_cnt 0 2006.285.08:02:01.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:02:01.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:02:01.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:02:01.12#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:02:01.12#ibcon#first serial, iclass 26, count 0 2006.285.08:02:01.12#ibcon#enter sib2, iclass 26, count 0 2006.285.08:02:01.12#ibcon#flushed, iclass 26, count 0 2006.285.08:02:01.12#ibcon#about to write, iclass 26, count 0 2006.285.08:02:01.12#ibcon#wrote, iclass 26, count 0 2006.285.08:02:01.12#ibcon#about to read 3, iclass 26, count 0 2006.285.08:02:01.14#ibcon#read 3, iclass 26, count 0 2006.285.08:02:01.14#ibcon#about to read 4, iclass 26, count 0 2006.285.08:02:01.14#ibcon#read 4, iclass 26, count 0 2006.285.08:02:01.14#ibcon#about to read 5, iclass 26, count 0 2006.285.08:02:01.14#ibcon#read 5, iclass 26, count 0 2006.285.08:02:01.14#ibcon#about to read 6, iclass 26, count 0 2006.285.08:02:01.14#ibcon#read 6, iclass 26, count 0 2006.285.08:02:01.14#ibcon#end of sib2, iclass 26, count 0 2006.285.08:02:01.14#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:02:01.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:02:01.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:02:01.14#ibcon#*before write, iclass 26, count 0 2006.285.08:02:01.14#ibcon#enter sib2, iclass 26, count 0 2006.285.08:02:01.14#ibcon#flushed, iclass 26, count 0 2006.285.08:02:01.14#ibcon#about to write, iclass 26, count 0 2006.285.08:02:01.14#ibcon#wrote, iclass 26, count 0 2006.285.08:02:01.14#ibcon#about to read 3, iclass 26, count 0 2006.285.08:02:01.18#ibcon#read 3, iclass 26, count 0 2006.285.08:02:01.18#ibcon#about to read 4, iclass 26, count 0 2006.285.08:02:01.18#ibcon#read 4, iclass 26, count 0 2006.285.08:02:01.18#ibcon#about to read 5, iclass 26, count 0 2006.285.08:02:01.18#ibcon#read 5, iclass 26, count 0 2006.285.08:02:01.18#ibcon#about to read 6, iclass 26, count 0 2006.285.08:02:01.18#ibcon#read 6, iclass 26, count 0 2006.285.08:02:01.18#ibcon#end of sib2, iclass 26, count 0 2006.285.08:02:01.18#ibcon#*after write, iclass 26, count 0 2006.285.08:02:01.18#ibcon#*before return 0, iclass 26, count 0 2006.285.08:02:01.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:02:01.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:02:01.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:02:01.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:02:01.18$vck44/vb=5,4 2006.285.08:02:01.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.08:02:01.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.08:02:01.18#ibcon#ireg 11 cls_cnt 2 2006.285.08:02:01.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:02:01.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:02:01.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:02:01.24#ibcon#enter wrdev, iclass 28, count 2 2006.285.08:02:01.24#ibcon#first serial, iclass 28, count 2 2006.285.08:02:01.24#ibcon#enter sib2, iclass 28, count 2 2006.285.08:02:01.24#ibcon#flushed, iclass 28, count 2 2006.285.08:02:01.24#ibcon#about to write, iclass 28, count 2 2006.285.08:02:01.24#ibcon#wrote, iclass 28, count 2 2006.285.08:02:01.24#ibcon#about to read 3, iclass 28, count 2 2006.285.08:02:01.26#ibcon#read 3, iclass 28, count 2 2006.285.08:02:01.26#ibcon#about to read 4, iclass 28, count 2 2006.285.08:02:01.26#ibcon#read 4, iclass 28, count 2 2006.285.08:02:01.26#ibcon#about to read 5, iclass 28, count 2 2006.285.08:02:01.26#ibcon#read 5, iclass 28, count 2 2006.285.08:02:01.26#ibcon#about to read 6, iclass 28, count 2 2006.285.08:02:01.26#ibcon#read 6, iclass 28, count 2 2006.285.08:02:01.26#ibcon#end of sib2, iclass 28, count 2 2006.285.08:02:01.26#ibcon#*mode == 0, iclass 28, count 2 2006.285.08:02:01.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.08:02:01.26#ibcon#[27=AT05-04\r\n] 2006.285.08:02:01.26#ibcon#*before write, iclass 28, count 2 2006.285.08:02:01.26#ibcon#enter sib2, iclass 28, count 2 2006.285.08:02:01.26#ibcon#flushed, iclass 28, count 2 2006.285.08:02:01.26#ibcon#about to write, iclass 28, count 2 2006.285.08:02:01.26#ibcon#wrote, iclass 28, count 2 2006.285.08:02:01.26#ibcon#about to read 3, iclass 28, count 2 2006.285.08:02:01.29#ibcon#read 3, iclass 28, count 2 2006.285.08:02:01.29#ibcon#about to read 4, iclass 28, count 2 2006.285.08:02:01.29#ibcon#read 4, iclass 28, count 2 2006.285.08:02:01.29#ibcon#about to read 5, iclass 28, count 2 2006.285.08:02:01.29#ibcon#read 5, iclass 28, count 2 2006.285.08:02:01.29#ibcon#about to read 6, iclass 28, count 2 2006.285.08:02:01.29#ibcon#read 6, iclass 28, count 2 2006.285.08:02:01.29#ibcon#end of sib2, iclass 28, count 2 2006.285.08:02:01.29#ibcon#*after write, iclass 28, count 2 2006.285.08:02:01.29#ibcon#*before return 0, iclass 28, count 2 2006.285.08:02:01.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:02:01.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:02:01.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.08:02:01.29#ibcon#ireg 7 cls_cnt 0 2006.285.08:02:01.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:02:01.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:02:01.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:02:01.41#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:02:01.41#ibcon#first serial, iclass 28, count 0 2006.285.08:02:01.41#ibcon#enter sib2, iclass 28, count 0 2006.285.08:02:01.41#ibcon#flushed, iclass 28, count 0 2006.285.08:02:01.41#ibcon#about to write, iclass 28, count 0 2006.285.08:02:01.41#ibcon#wrote, iclass 28, count 0 2006.285.08:02:01.41#ibcon#about to read 3, iclass 28, count 0 2006.285.08:02:01.43#ibcon#read 3, iclass 28, count 0 2006.285.08:02:01.43#ibcon#about to read 4, iclass 28, count 0 2006.285.08:02:01.43#ibcon#read 4, iclass 28, count 0 2006.285.08:02:01.43#ibcon#about to read 5, iclass 28, count 0 2006.285.08:02:01.43#ibcon#read 5, iclass 28, count 0 2006.285.08:02:01.43#ibcon#about to read 6, iclass 28, count 0 2006.285.08:02:01.43#ibcon#read 6, iclass 28, count 0 2006.285.08:02:01.43#ibcon#end of sib2, iclass 28, count 0 2006.285.08:02:01.43#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:02:01.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:02:01.43#ibcon#[27=USB\r\n] 2006.285.08:02:01.43#ibcon#*before write, iclass 28, count 0 2006.285.08:02:01.43#ibcon#enter sib2, iclass 28, count 0 2006.285.08:02:01.43#ibcon#flushed, iclass 28, count 0 2006.285.08:02:01.43#ibcon#about to write, iclass 28, count 0 2006.285.08:02:01.43#ibcon#wrote, iclass 28, count 0 2006.285.08:02:01.43#ibcon#about to read 3, iclass 28, count 0 2006.285.08:02:01.46#ibcon#read 3, iclass 28, count 0 2006.285.08:02:01.46#ibcon#about to read 4, iclass 28, count 0 2006.285.08:02:01.46#ibcon#read 4, iclass 28, count 0 2006.285.08:02:01.46#ibcon#about to read 5, iclass 28, count 0 2006.285.08:02:01.46#ibcon#read 5, iclass 28, count 0 2006.285.08:02:01.46#ibcon#about to read 6, iclass 28, count 0 2006.285.08:02:01.46#ibcon#read 6, iclass 28, count 0 2006.285.08:02:01.46#ibcon#end of sib2, iclass 28, count 0 2006.285.08:02:01.46#ibcon#*after write, iclass 28, count 0 2006.285.08:02:01.46#ibcon#*before return 0, iclass 28, count 0 2006.285.08:02:01.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:02:01.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:02:01.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:02:01.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:02:01.46$vck44/vblo=6,719.99 2006.285.08:02:01.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.08:02:01.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.08:02:01.46#ibcon#ireg 17 cls_cnt 0 2006.285.08:02:01.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:02:01.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:02:01.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:02:01.46#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:02:01.46#ibcon#first serial, iclass 30, count 0 2006.285.08:02:01.46#ibcon#enter sib2, iclass 30, count 0 2006.285.08:02:01.46#ibcon#flushed, iclass 30, count 0 2006.285.08:02:01.46#ibcon#about to write, iclass 30, count 0 2006.285.08:02:01.46#ibcon#wrote, iclass 30, count 0 2006.285.08:02:01.46#ibcon#about to read 3, iclass 30, count 0 2006.285.08:02:01.48#ibcon#read 3, iclass 30, count 0 2006.285.08:02:01.48#ibcon#about to read 4, iclass 30, count 0 2006.285.08:02:01.48#ibcon#read 4, iclass 30, count 0 2006.285.08:02:01.48#ibcon#about to read 5, iclass 30, count 0 2006.285.08:02:01.48#ibcon#read 5, iclass 30, count 0 2006.285.08:02:01.48#ibcon#about to read 6, iclass 30, count 0 2006.285.08:02:01.48#ibcon#read 6, iclass 30, count 0 2006.285.08:02:01.48#ibcon#end of sib2, iclass 30, count 0 2006.285.08:02:01.48#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:02:01.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:02:01.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:02:01.48#ibcon#*before write, iclass 30, count 0 2006.285.08:02:01.48#ibcon#enter sib2, iclass 30, count 0 2006.285.08:02:01.48#ibcon#flushed, iclass 30, count 0 2006.285.08:02:01.48#ibcon#about to write, iclass 30, count 0 2006.285.08:02:01.48#ibcon#wrote, iclass 30, count 0 2006.285.08:02:01.48#ibcon#about to read 3, iclass 30, count 0 2006.285.08:02:01.52#ibcon#read 3, iclass 30, count 0 2006.285.08:02:01.52#ibcon#about to read 4, iclass 30, count 0 2006.285.08:02:01.52#ibcon#read 4, iclass 30, count 0 2006.285.08:02:01.52#ibcon#about to read 5, iclass 30, count 0 2006.285.08:02:01.52#ibcon#read 5, iclass 30, count 0 2006.285.08:02:01.52#ibcon#about to read 6, iclass 30, count 0 2006.285.08:02:01.52#ibcon#read 6, iclass 30, count 0 2006.285.08:02:01.52#ibcon#end of sib2, iclass 30, count 0 2006.285.08:02:01.52#ibcon#*after write, iclass 30, count 0 2006.285.08:02:01.52#ibcon#*before return 0, iclass 30, count 0 2006.285.08:02:01.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:02:01.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:02:01.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:02:01.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:02:01.52$vck44/vb=6,3 2006.285.08:02:01.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.08:02:01.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.08:02:01.52#ibcon#ireg 11 cls_cnt 2 2006.285.08:02:01.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:02:01.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:02:01.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:02:01.58#ibcon#enter wrdev, iclass 32, count 2 2006.285.08:02:01.58#ibcon#first serial, iclass 32, count 2 2006.285.08:02:01.58#ibcon#enter sib2, iclass 32, count 2 2006.285.08:02:01.58#ibcon#flushed, iclass 32, count 2 2006.285.08:02:01.58#ibcon#about to write, iclass 32, count 2 2006.285.08:02:01.58#ibcon#wrote, iclass 32, count 2 2006.285.08:02:01.58#ibcon#about to read 3, iclass 32, count 2 2006.285.08:02:01.60#ibcon#read 3, iclass 32, count 2 2006.285.08:02:01.60#ibcon#about to read 4, iclass 32, count 2 2006.285.08:02:01.60#ibcon#read 4, iclass 32, count 2 2006.285.08:02:01.60#ibcon#about to read 5, iclass 32, count 2 2006.285.08:02:01.60#ibcon#read 5, iclass 32, count 2 2006.285.08:02:01.60#ibcon#about to read 6, iclass 32, count 2 2006.285.08:02:01.60#ibcon#read 6, iclass 32, count 2 2006.285.08:02:01.60#ibcon#end of sib2, iclass 32, count 2 2006.285.08:02:01.60#ibcon#*mode == 0, iclass 32, count 2 2006.285.08:02:01.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.08:02:01.60#ibcon#[27=AT06-03\r\n] 2006.285.08:02:01.60#ibcon#*before write, iclass 32, count 2 2006.285.08:02:01.60#ibcon#enter sib2, iclass 32, count 2 2006.285.08:02:01.60#ibcon#flushed, iclass 32, count 2 2006.285.08:02:01.60#ibcon#about to write, iclass 32, count 2 2006.285.08:02:01.60#ibcon#wrote, iclass 32, count 2 2006.285.08:02:01.60#ibcon#about to read 3, iclass 32, count 2 2006.285.08:02:01.63#ibcon#read 3, iclass 32, count 2 2006.285.08:02:01.63#ibcon#about to read 4, iclass 32, count 2 2006.285.08:02:01.63#ibcon#read 4, iclass 32, count 2 2006.285.08:02:01.63#ibcon#about to read 5, iclass 32, count 2 2006.285.08:02:01.63#ibcon#read 5, iclass 32, count 2 2006.285.08:02:01.63#ibcon#about to read 6, iclass 32, count 2 2006.285.08:02:01.63#ibcon#read 6, iclass 32, count 2 2006.285.08:02:01.63#ibcon#end of sib2, iclass 32, count 2 2006.285.08:02:01.63#ibcon#*after write, iclass 32, count 2 2006.285.08:02:01.63#ibcon#*before return 0, iclass 32, count 2 2006.285.08:02:01.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:02:01.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:02:01.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.08:02:01.63#ibcon#ireg 7 cls_cnt 0 2006.285.08:02:01.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:02:01.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:02:01.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:02:01.75#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:02:01.75#ibcon#first serial, iclass 32, count 0 2006.285.08:02:01.75#ibcon#enter sib2, iclass 32, count 0 2006.285.08:02:01.75#ibcon#flushed, iclass 32, count 0 2006.285.08:02:01.75#ibcon#about to write, iclass 32, count 0 2006.285.08:02:01.75#ibcon#wrote, iclass 32, count 0 2006.285.08:02:01.75#ibcon#about to read 3, iclass 32, count 0 2006.285.08:02:01.77#ibcon#read 3, iclass 32, count 0 2006.285.08:02:01.77#ibcon#about to read 4, iclass 32, count 0 2006.285.08:02:01.77#ibcon#read 4, iclass 32, count 0 2006.285.08:02:01.77#ibcon#about to read 5, iclass 32, count 0 2006.285.08:02:01.77#ibcon#read 5, iclass 32, count 0 2006.285.08:02:01.77#ibcon#about to read 6, iclass 32, count 0 2006.285.08:02:01.77#ibcon#read 6, iclass 32, count 0 2006.285.08:02:01.77#ibcon#end of sib2, iclass 32, count 0 2006.285.08:02:01.77#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:02:01.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:02:01.77#ibcon#[27=USB\r\n] 2006.285.08:02:01.77#ibcon#*before write, iclass 32, count 0 2006.285.08:02:01.77#ibcon#enter sib2, iclass 32, count 0 2006.285.08:02:01.77#ibcon#flushed, iclass 32, count 0 2006.285.08:02:01.77#ibcon#about to write, iclass 32, count 0 2006.285.08:02:01.77#ibcon#wrote, iclass 32, count 0 2006.285.08:02:01.77#ibcon#about to read 3, iclass 32, count 0 2006.285.08:02:01.80#ibcon#read 3, iclass 32, count 0 2006.285.08:02:01.80#ibcon#about to read 4, iclass 32, count 0 2006.285.08:02:01.80#ibcon#read 4, iclass 32, count 0 2006.285.08:02:01.80#ibcon#about to read 5, iclass 32, count 0 2006.285.08:02:01.80#ibcon#read 5, iclass 32, count 0 2006.285.08:02:01.80#ibcon#about to read 6, iclass 32, count 0 2006.285.08:02:01.80#ibcon#read 6, iclass 32, count 0 2006.285.08:02:01.80#ibcon#end of sib2, iclass 32, count 0 2006.285.08:02:01.80#ibcon#*after write, iclass 32, count 0 2006.285.08:02:01.80#ibcon#*before return 0, iclass 32, count 0 2006.285.08:02:01.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:02:01.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:02:01.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:02:01.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:02:01.80$vck44/vblo=7,734.99 2006.285.08:02:01.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.08:02:01.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.08:02:01.80#ibcon#ireg 17 cls_cnt 0 2006.285.08:02:01.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:02:01.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:02:01.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:02:01.80#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:02:01.80#ibcon#first serial, iclass 34, count 0 2006.285.08:02:01.80#ibcon#enter sib2, iclass 34, count 0 2006.285.08:02:01.80#ibcon#flushed, iclass 34, count 0 2006.285.08:02:01.80#ibcon#about to write, iclass 34, count 0 2006.285.08:02:01.80#ibcon#wrote, iclass 34, count 0 2006.285.08:02:01.80#ibcon#about to read 3, iclass 34, count 0 2006.285.08:02:01.82#ibcon#read 3, iclass 34, count 0 2006.285.08:02:01.82#ibcon#about to read 4, iclass 34, count 0 2006.285.08:02:01.82#ibcon#read 4, iclass 34, count 0 2006.285.08:02:01.82#ibcon#about to read 5, iclass 34, count 0 2006.285.08:02:01.82#ibcon#read 5, iclass 34, count 0 2006.285.08:02:01.82#ibcon#about to read 6, iclass 34, count 0 2006.285.08:02:01.82#ibcon#read 6, iclass 34, count 0 2006.285.08:02:01.82#ibcon#end of sib2, iclass 34, count 0 2006.285.08:02:01.82#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:02:01.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:02:01.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:02:01.82#ibcon#*before write, iclass 34, count 0 2006.285.08:02:01.82#ibcon#enter sib2, iclass 34, count 0 2006.285.08:02:01.82#ibcon#flushed, iclass 34, count 0 2006.285.08:02:01.82#ibcon#about to write, iclass 34, count 0 2006.285.08:02:01.82#ibcon#wrote, iclass 34, count 0 2006.285.08:02:01.82#ibcon#about to read 3, iclass 34, count 0 2006.285.08:02:01.86#ibcon#read 3, iclass 34, count 0 2006.285.08:02:01.86#ibcon#about to read 4, iclass 34, count 0 2006.285.08:02:01.86#ibcon#read 4, iclass 34, count 0 2006.285.08:02:01.86#ibcon#about to read 5, iclass 34, count 0 2006.285.08:02:01.86#ibcon#read 5, iclass 34, count 0 2006.285.08:02:01.86#ibcon#about to read 6, iclass 34, count 0 2006.285.08:02:01.86#ibcon#read 6, iclass 34, count 0 2006.285.08:02:01.86#ibcon#end of sib2, iclass 34, count 0 2006.285.08:02:01.86#ibcon#*after write, iclass 34, count 0 2006.285.08:02:01.86#ibcon#*before return 0, iclass 34, count 0 2006.285.08:02:01.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:02:01.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:02:01.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:02:01.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:02:01.86$vck44/vb=7,4 2006.285.08:02:01.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.08:02:01.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.08:02:01.86#ibcon#ireg 11 cls_cnt 2 2006.285.08:02:01.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:02:01.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:02:01.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:02:01.92#ibcon#enter wrdev, iclass 36, count 2 2006.285.08:02:01.92#ibcon#first serial, iclass 36, count 2 2006.285.08:02:01.92#ibcon#enter sib2, iclass 36, count 2 2006.285.08:02:01.92#ibcon#flushed, iclass 36, count 2 2006.285.08:02:01.92#ibcon#about to write, iclass 36, count 2 2006.285.08:02:01.92#ibcon#wrote, iclass 36, count 2 2006.285.08:02:01.92#ibcon#about to read 3, iclass 36, count 2 2006.285.08:02:01.94#ibcon#read 3, iclass 36, count 2 2006.285.08:02:01.94#ibcon#about to read 4, iclass 36, count 2 2006.285.08:02:01.94#ibcon#read 4, iclass 36, count 2 2006.285.08:02:01.94#ibcon#about to read 5, iclass 36, count 2 2006.285.08:02:01.94#ibcon#read 5, iclass 36, count 2 2006.285.08:02:01.94#ibcon#about to read 6, iclass 36, count 2 2006.285.08:02:01.94#ibcon#read 6, iclass 36, count 2 2006.285.08:02:01.94#ibcon#end of sib2, iclass 36, count 2 2006.285.08:02:01.94#ibcon#*mode == 0, iclass 36, count 2 2006.285.08:02:01.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.08:02:01.94#ibcon#[27=AT07-04\r\n] 2006.285.08:02:01.94#ibcon#*before write, iclass 36, count 2 2006.285.08:02:01.94#ibcon#enter sib2, iclass 36, count 2 2006.285.08:02:01.94#ibcon#flushed, iclass 36, count 2 2006.285.08:02:01.94#ibcon#about to write, iclass 36, count 2 2006.285.08:02:01.94#ibcon#wrote, iclass 36, count 2 2006.285.08:02:01.94#ibcon#about to read 3, iclass 36, count 2 2006.285.08:02:01.97#ibcon#read 3, iclass 36, count 2 2006.285.08:02:01.97#ibcon#about to read 4, iclass 36, count 2 2006.285.08:02:01.97#ibcon#read 4, iclass 36, count 2 2006.285.08:02:01.97#ibcon#about to read 5, iclass 36, count 2 2006.285.08:02:01.97#ibcon#read 5, iclass 36, count 2 2006.285.08:02:01.97#ibcon#about to read 6, iclass 36, count 2 2006.285.08:02:01.97#ibcon#read 6, iclass 36, count 2 2006.285.08:02:01.97#ibcon#end of sib2, iclass 36, count 2 2006.285.08:02:01.97#ibcon#*after write, iclass 36, count 2 2006.285.08:02:01.97#ibcon#*before return 0, iclass 36, count 2 2006.285.08:02:01.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:02:01.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:02:01.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.08:02:01.97#ibcon#ireg 7 cls_cnt 0 2006.285.08:02:01.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:02:02.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:02:02.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:02:02.09#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:02:02.09#ibcon#first serial, iclass 36, count 0 2006.285.08:02:02.09#ibcon#enter sib2, iclass 36, count 0 2006.285.08:02:02.09#ibcon#flushed, iclass 36, count 0 2006.285.08:02:02.09#ibcon#about to write, iclass 36, count 0 2006.285.08:02:02.09#ibcon#wrote, iclass 36, count 0 2006.285.08:02:02.09#ibcon#about to read 3, iclass 36, count 0 2006.285.08:02:02.11#ibcon#read 3, iclass 36, count 0 2006.285.08:02:02.11#ibcon#about to read 4, iclass 36, count 0 2006.285.08:02:02.11#ibcon#read 4, iclass 36, count 0 2006.285.08:02:02.11#ibcon#about to read 5, iclass 36, count 0 2006.285.08:02:02.11#ibcon#read 5, iclass 36, count 0 2006.285.08:02:02.11#ibcon#about to read 6, iclass 36, count 0 2006.285.08:02:02.11#ibcon#read 6, iclass 36, count 0 2006.285.08:02:02.11#ibcon#end of sib2, iclass 36, count 0 2006.285.08:02:02.11#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:02:02.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:02:02.11#ibcon#[27=USB\r\n] 2006.285.08:02:02.11#ibcon#*before write, iclass 36, count 0 2006.285.08:02:02.11#ibcon#enter sib2, iclass 36, count 0 2006.285.08:02:02.11#ibcon#flushed, iclass 36, count 0 2006.285.08:02:02.11#ibcon#about to write, iclass 36, count 0 2006.285.08:02:02.11#ibcon#wrote, iclass 36, count 0 2006.285.08:02:02.11#ibcon#about to read 3, iclass 36, count 0 2006.285.08:02:02.14#ibcon#read 3, iclass 36, count 0 2006.285.08:02:02.14#ibcon#about to read 4, iclass 36, count 0 2006.285.08:02:02.14#ibcon#read 4, iclass 36, count 0 2006.285.08:02:02.14#ibcon#about to read 5, iclass 36, count 0 2006.285.08:02:02.14#ibcon#read 5, iclass 36, count 0 2006.285.08:02:02.14#ibcon#about to read 6, iclass 36, count 0 2006.285.08:02:02.14#ibcon#read 6, iclass 36, count 0 2006.285.08:02:02.14#ibcon#end of sib2, iclass 36, count 0 2006.285.08:02:02.14#ibcon#*after write, iclass 36, count 0 2006.285.08:02:02.14#ibcon#*before return 0, iclass 36, count 0 2006.285.08:02:02.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:02:02.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:02:02.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:02:02.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:02:02.14$vck44/vblo=8,744.99 2006.285.08:02:02.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.08:02:02.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.08:02:02.14#ibcon#ireg 17 cls_cnt 0 2006.285.08:02:02.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:02:02.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:02:02.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:02:02.14#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:02:02.14#ibcon#first serial, iclass 38, count 0 2006.285.08:02:02.14#ibcon#enter sib2, iclass 38, count 0 2006.285.08:02:02.14#ibcon#flushed, iclass 38, count 0 2006.285.08:02:02.14#ibcon#about to write, iclass 38, count 0 2006.285.08:02:02.14#ibcon#wrote, iclass 38, count 0 2006.285.08:02:02.14#ibcon#about to read 3, iclass 38, count 0 2006.285.08:02:02.16#ibcon#read 3, iclass 38, count 0 2006.285.08:02:02.16#ibcon#about to read 4, iclass 38, count 0 2006.285.08:02:02.16#ibcon#read 4, iclass 38, count 0 2006.285.08:02:02.16#ibcon#about to read 5, iclass 38, count 0 2006.285.08:02:02.16#ibcon#read 5, iclass 38, count 0 2006.285.08:02:02.16#ibcon#about to read 6, iclass 38, count 0 2006.285.08:02:02.16#ibcon#read 6, iclass 38, count 0 2006.285.08:02:02.16#ibcon#end of sib2, iclass 38, count 0 2006.285.08:02:02.16#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:02:02.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:02:02.16#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:02:02.16#ibcon#*before write, iclass 38, count 0 2006.285.08:02:02.16#ibcon#enter sib2, iclass 38, count 0 2006.285.08:02:02.16#ibcon#flushed, iclass 38, count 0 2006.285.08:02:02.16#ibcon#about to write, iclass 38, count 0 2006.285.08:02:02.16#ibcon#wrote, iclass 38, count 0 2006.285.08:02:02.16#ibcon#about to read 3, iclass 38, count 0 2006.285.08:02:02.20#ibcon#read 3, iclass 38, count 0 2006.285.08:02:02.20#ibcon#about to read 4, iclass 38, count 0 2006.285.08:02:02.20#ibcon#read 4, iclass 38, count 0 2006.285.08:02:02.20#ibcon#about to read 5, iclass 38, count 0 2006.285.08:02:02.20#ibcon#read 5, iclass 38, count 0 2006.285.08:02:02.20#ibcon#about to read 6, iclass 38, count 0 2006.285.08:02:02.20#ibcon#read 6, iclass 38, count 0 2006.285.08:02:02.20#ibcon#end of sib2, iclass 38, count 0 2006.285.08:02:02.20#ibcon#*after write, iclass 38, count 0 2006.285.08:02:02.20#ibcon#*before return 0, iclass 38, count 0 2006.285.08:02:02.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:02:02.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:02:02.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:02:02.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:02:02.20$vck44/vb=8,4 2006.285.08:02:02.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.08:02:02.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.08:02:02.20#ibcon#ireg 11 cls_cnt 2 2006.285.08:02:02.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:02:02.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:02:02.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:02:02.26#ibcon#enter wrdev, iclass 40, count 2 2006.285.08:02:02.26#ibcon#first serial, iclass 40, count 2 2006.285.08:02:02.26#ibcon#enter sib2, iclass 40, count 2 2006.285.08:02:02.26#ibcon#flushed, iclass 40, count 2 2006.285.08:02:02.26#ibcon#about to write, iclass 40, count 2 2006.285.08:02:02.26#ibcon#wrote, iclass 40, count 2 2006.285.08:02:02.26#ibcon#about to read 3, iclass 40, count 2 2006.285.08:02:02.28#ibcon#read 3, iclass 40, count 2 2006.285.08:02:02.28#ibcon#about to read 4, iclass 40, count 2 2006.285.08:02:02.28#ibcon#read 4, iclass 40, count 2 2006.285.08:02:02.28#ibcon#about to read 5, iclass 40, count 2 2006.285.08:02:02.28#ibcon#read 5, iclass 40, count 2 2006.285.08:02:02.28#ibcon#about to read 6, iclass 40, count 2 2006.285.08:02:02.28#ibcon#read 6, iclass 40, count 2 2006.285.08:02:02.28#ibcon#end of sib2, iclass 40, count 2 2006.285.08:02:02.28#ibcon#*mode == 0, iclass 40, count 2 2006.285.08:02:02.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.08:02:02.28#ibcon#[27=AT08-04\r\n] 2006.285.08:02:02.28#ibcon#*before write, iclass 40, count 2 2006.285.08:02:02.28#ibcon#enter sib2, iclass 40, count 2 2006.285.08:02:02.28#ibcon#flushed, iclass 40, count 2 2006.285.08:02:02.28#ibcon#about to write, iclass 40, count 2 2006.285.08:02:02.28#ibcon#wrote, iclass 40, count 2 2006.285.08:02:02.28#ibcon#about to read 3, iclass 40, count 2 2006.285.08:02:02.31#ibcon#read 3, iclass 40, count 2 2006.285.08:02:02.31#ibcon#about to read 4, iclass 40, count 2 2006.285.08:02:02.31#ibcon#read 4, iclass 40, count 2 2006.285.08:02:02.31#ibcon#about to read 5, iclass 40, count 2 2006.285.08:02:02.31#ibcon#read 5, iclass 40, count 2 2006.285.08:02:02.31#ibcon#about to read 6, iclass 40, count 2 2006.285.08:02:02.31#ibcon#read 6, iclass 40, count 2 2006.285.08:02:02.31#ibcon#end of sib2, iclass 40, count 2 2006.285.08:02:02.31#ibcon#*after write, iclass 40, count 2 2006.285.08:02:02.31#ibcon#*before return 0, iclass 40, count 2 2006.285.08:02:02.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:02:02.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:02:02.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.08:02:02.31#ibcon#ireg 7 cls_cnt 0 2006.285.08:02:02.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:02:02.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:02:02.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:02:02.43#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:02:02.43#ibcon#first serial, iclass 40, count 0 2006.285.08:02:02.43#ibcon#enter sib2, iclass 40, count 0 2006.285.08:02:02.43#ibcon#flushed, iclass 40, count 0 2006.285.08:02:02.43#ibcon#about to write, iclass 40, count 0 2006.285.08:02:02.43#ibcon#wrote, iclass 40, count 0 2006.285.08:02:02.43#ibcon#about to read 3, iclass 40, count 0 2006.285.08:02:02.45#ibcon#read 3, iclass 40, count 0 2006.285.08:02:02.45#ibcon#about to read 4, iclass 40, count 0 2006.285.08:02:02.45#ibcon#read 4, iclass 40, count 0 2006.285.08:02:02.45#ibcon#about to read 5, iclass 40, count 0 2006.285.08:02:02.45#ibcon#read 5, iclass 40, count 0 2006.285.08:02:02.45#ibcon#about to read 6, iclass 40, count 0 2006.285.08:02:02.45#ibcon#read 6, iclass 40, count 0 2006.285.08:02:02.45#ibcon#end of sib2, iclass 40, count 0 2006.285.08:02:02.45#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:02:02.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:02:02.45#ibcon#[27=USB\r\n] 2006.285.08:02:02.45#ibcon#*before write, iclass 40, count 0 2006.285.08:02:02.45#ibcon#enter sib2, iclass 40, count 0 2006.285.08:02:02.45#ibcon#flushed, iclass 40, count 0 2006.285.08:02:02.45#ibcon#about to write, iclass 40, count 0 2006.285.08:02:02.45#ibcon#wrote, iclass 40, count 0 2006.285.08:02:02.45#ibcon#about to read 3, iclass 40, count 0 2006.285.08:02:02.48#ibcon#read 3, iclass 40, count 0 2006.285.08:02:02.48#ibcon#about to read 4, iclass 40, count 0 2006.285.08:02:02.48#ibcon#read 4, iclass 40, count 0 2006.285.08:02:02.48#ibcon#about to read 5, iclass 40, count 0 2006.285.08:02:02.48#ibcon#read 5, iclass 40, count 0 2006.285.08:02:02.48#ibcon#about to read 6, iclass 40, count 0 2006.285.08:02:02.48#ibcon#read 6, iclass 40, count 0 2006.285.08:02:02.48#ibcon#end of sib2, iclass 40, count 0 2006.285.08:02:02.48#ibcon#*after write, iclass 40, count 0 2006.285.08:02:02.48#ibcon#*before return 0, iclass 40, count 0 2006.285.08:02:02.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:02:02.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:02:02.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:02:02.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:02:02.48$vck44/vabw=wide 2006.285.08:02:02.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.08:02:02.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.08:02:02.48#ibcon#ireg 8 cls_cnt 0 2006.285.08:02:02.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:02:02.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:02:02.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:02:02.48#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:02:02.48#ibcon#first serial, iclass 4, count 0 2006.285.08:02:02.48#ibcon#enter sib2, iclass 4, count 0 2006.285.08:02:02.48#ibcon#flushed, iclass 4, count 0 2006.285.08:02:02.48#ibcon#about to write, iclass 4, count 0 2006.285.08:02:02.48#ibcon#wrote, iclass 4, count 0 2006.285.08:02:02.48#ibcon#about to read 3, iclass 4, count 0 2006.285.08:02:02.50#ibcon#read 3, iclass 4, count 0 2006.285.08:02:02.50#ibcon#about to read 4, iclass 4, count 0 2006.285.08:02:02.50#ibcon#read 4, iclass 4, count 0 2006.285.08:02:02.50#ibcon#about to read 5, iclass 4, count 0 2006.285.08:02:02.50#ibcon#read 5, iclass 4, count 0 2006.285.08:02:02.50#ibcon#about to read 6, iclass 4, count 0 2006.285.08:02:02.50#ibcon#read 6, iclass 4, count 0 2006.285.08:02:02.50#ibcon#end of sib2, iclass 4, count 0 2006.285.08:02:02.50#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:02:02.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:02:02.50#ibcon#[25=BW32\r\n] 2006.285.08:02:02.50#ibcon#*before write, iclass 4, count 0 2006.285.08:02:02.50#ibcon#enter sib2, iclass 4, count 0 2006.285.08:02:02.50#ibcon#flushed, iclass 4, count 0 2006.285.08:02:02.50#ibcon#about to write, iclass 4, count 0 2006.285.08:02:02.50#ibcon#wrote, iclass 4, count 0 2006.285.08:02:02.50#ibcon#about to read 3, iclass 4, count 0 2006.285.08:02:02.53#ibcon#read 3, iclass 4, count 0 2006.285.08:02:02.53#ibcon#about to read 4, iclass 4, count 0 2006.285.08:02:02.53#ibcon#read 4, iclass 4, count 0 2006.285.08:02:02.53#ibcon#about to read 5, iclass 4, count 0 2006.285.08:02:02.53#ibcon#read 5, iclass 4, count 0 2006.285.08:02:02.53#ibcon#about to read 6, iclass 4, count 0 2006.285.08:02:02.53#ibcon#read 6, iclass 4, count 0 2006.285.08:02:02.53#ibcon#end of sib2, iclass 4, count 0 2006.285.08:02:02.53#ibcon#*after write, iclass 4, count 0 2006.285.08:02:02.53#ibcon#*before return 0, iclass 4, count 0 2006.285.08:02:02.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:02:02.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:02:02.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:02:02.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:02:02.53$vck44/vbbw=wide 2006.285.08:02:02.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.08:02:02.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.08:02:02.53#ibcon#ireg 8 cls_cnt 0 2006.285.08:02:02.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:02:02.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:02:02.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:02:02.60#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:02:02.60#ibcon#first serial, iclass 6, count 0 2006.285.08:02:02.60#ibcon#enter sib2, iclass 6, count 0 2006.285.08:02:02.60#ibcon#flushed, iclass 6, count 0 2006.285.08:02:02.60#ibcon#about to write, iclass 6, count 0 2006.285.08:02:02.60#ibcon#wrote, iclass 6, count 0 2006.285.08:02:02.60#ibcon#about to read 3, iclass 6, count 0 2006.285.08:02:02.62#ibcon#read 3, iclass 6, count 0 2006.285.08:02:02.62#ibcon#about to read 4, iclass 6, count 0 2006.285.08:02:02.62#ibcon#read 4, iclass 6, count 0 2006.285.08:02:02.62#ibcon#about to read 5, iclass 6, count 0 2006.285.08:02:02.62#ibcon#read 5, iclass 6, count 0 2006.285.08:02:02.62#ibcon#about to read 6, iclass 6, count 0 2006.285.08:02:02.62#ibcon#read 6, iclass 6, count 0 2006.285.08:02:02.62#ibcon#end of sib2, iclass 6, count 0 2006.285.08:02:02.62#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:02:02.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:02:02.62#ibcon#[27=BW32\r\n] 2006.285.08:02:02.62#ibcon#*before write, iclass 6, count 0 2006.285.08:02:02.62#ibcon#enter sib2, iclass 6, count 0 2006.285.08:02:02.62#ibcon#flushed, iclass 6, count 0 2006.285.08:02:02.62#ibcon#about to write, iclass 6, count 0 2006.285.08:02:02.62#ibcon#wrote, iclass 6, count 0 2006.285.08:02:02.62#ibcon#about to read 3, iclass 6, count 0 2006.285.08:02:02.65#ibcon#read 3, iclass 6, count 0 2006.285.08:02:02.65#ibcon#about to read 4, iclass 6, count 0 2006.285.08:02:02.65#ibcon#read 4, iclass 6, count 0 2006.285.08:02:02.65#ibcon#about to read 5, iclass 6, count 0 2006.285.08:02:02.65#ibcon#read 5, iclass 6, count 0 2006.285.08:02:02.65#ibcon#about to read 6, iclass 6, count 0 2006.285.08:02:02.65#ibcon#read 6, iclass 6, count 0 2006.285.08:02:02.65#ibcon#end of sib2, iclass 6, count 0 2006.285.08:02:02.65#ibcon#*after write, iclass 6, count 0 2006.285.08:02:02.65#ibcon#*before return 0, iclass 6, count 0 2006.285.08:02:02.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:02:02.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:02:02.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:02:02.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:02:02.65$setupk4/ifdk4 2006.285.08:02:02.65$ifdk4/lo= 2006.285.08:02:02.65$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:02:02.65$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:02:02.65$ifdk4/patch= 2006.285.08:02:02.65$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:02:02.65$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:02:02.65$setupk4/!*+20s 2006.285.08:02:05.83#abcon#<5=/05 2.5 4.0 22.95 781014.5\r\n> 2006.285.08:02:05.85#abcon#{5=INTERFACE CLEAR} 2006.285.08:02:05.91#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:02:16.00#abcon#<5=/05 2.5 4.0 22.94 781014.5\r\n> 2006.285.08:02:16.02#abcon#{5=INTERFACE CLEAR} 2006.285.08:02:16.08#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:02:17.15$setupk4/"tpicd 2006.285.08:02:17.15$setupk4/echo=off 2006.285.08:02:17.15$setupk4/xlog=off 2006.285.08:02:17.15:!2006.285.08:08:17 2006.285.08:02:37.14#trakl#Source acquired 2006.285.08:02:39.14#flagr#flagr/antenna,acquired 2006.285.08:08:17.00:preob 2006.285.08:08:17.14/onsource/TRACKING 2006.285.08:08:17.14:!2006.285.08:08:27 2006.285.08:08:27.00:"tape 2006.285.08:08:27.00:"st=record 2006.285.08:08:27.00:data_valid=on 2006.285.08:08:27.00:midob 2006.285.08:08:27.14/onsource/TRACKING 2006.285.08:08:27.14/wx/22.79,1014.5,79 2006.285.08:08:27.35/cable/+6.4767E-03 2006.285.08:08:28.44/va/01,07,usb,yes,34,36 2006.285.08:08:28.44/va/02,06,usb,yes,34,34 2006.285.08:08:28.44/va/03,07,usb,yes,33,35 2006.285.08:08:28.44/va/04,06,usb,yes,35,36 2006.285.08:08:28.44/va/05,03,usb,yes,34,35 2006.285.08:08:28.44/va/06,04,usb,yes,31,30 2006.285.08:08:28.44/va/07,04,usb,yes,32,32 2006.285.08:08:28.44/va/08,03,usb,yes,32,39 2006.285.08:08:28.67/valo/01,524.99,yes,locked 2006.285.08:08:28.67/valo/02,534.99,yes,locked 2006.285.08:08:28.67/valo/03,564.99,yes,locked 2006.285.08:08:28.67/valo/04,624.99,yes,locked 2006.285.08:08:28.67/valo/05,734.99,yes,locked 2006.285.08:08:28.67/valo/06,814.99,yes,locked 2006.285.08:08:28.67/valo/07,864.99,yes,locked 2006.285.08:08:28.67/valo/08,884.99,yes,locked 2006.285.08:08:29.76/vb/01,04,usb,yes,32,29 2006.285.08:08:29.76/vb/02,05,usb,yes,30,30 2006.285.08:08:29.76/vb/03,04,usb,yes,31,34 2006.285.08:08:29.76/vb/04,05,usb,yes,31,30 2006.285.08:08:29.76/vb/05,04,usb,yes,27,30 2006.285.08:08:29.76/vb/06,03,usb,yes,39,35 2006.285.08:08:29.76/vb/07,04,usb,yes,32,32 2006.285.08:08:29.76/vb/08,04,usb,yes,29,33 2006.285.08:08:29.99/vblo/01,629.99,yes,locked 2006.285.08:08:29.99/vblo/02,634.99,yes,locked 2006.285.08:08:29.99/vblo/03,649.99,yes,locked 2006.285.08:08:29.99/vblo/04,679.99,yes,locked 2006.285.08:08:29.99/vblo/05,709.99,yes,locked 2006.285.08:08:29.99/vblo/06,719.99,yes,locked 2006.285.08:08:29.99/vblo/07,734.99,yes,locked 2006.285.08:08:29.99/vblo/08,744.99,yes,locked 2006.285.08:08:30.14/vabw/8 2006.285.08:08:30.29/vbbw/8 2006.285.08:08:30.49/xfe/off,on,12.2 2006.285.08:08:30.86/ifatt/23,28,28,28 2006.285.08:08:31.08/fmout-gps/S +2.83E-07 2006.285.08:08:31.10:!2006.285.08:13:47 2006.285.08:13:47.00:data_valid=off 2006.285.08:13:47.01:"et 2006.285.08:13:47.01:!+3s 2006.285.08:13:50.02:"tape 2006.285.08:13:50.02:postob 2006.285.08:13:50.15/cable/+6.4756E-03 2006.285.08:13:50.16/wx/22.65,1014.6,81 2006.285.08:13:51.07/fmout-gps/S +2.80E-07 2006.285.08:13:51.08:scan_name=285-0817,jd0610,40 2006.285.08:13:51.08:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.285.08:13:52.14#flagr#flagr/antenna,new-source 2006.285.08:13:52.14:checkk5 2006.285.08:13:52.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:13:52.93/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:13:53.36/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:13:53.80/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:13:54.21/chk_obsdata//k5ts1/T2850808??a.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.285.08:13:54.59/chk_obsdata//k5ts2/T2850808??b.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.285.08:13:54.94/chk_obsdata//k5ts3/T2850808??c.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.285.08:13:55.28/chk_obsdata//k5ts4/T2850808??d.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.285.08:13:56.07/k5log//k5ts1_log_newline 2006.285.08:13:56.92/k5log//k5ts2_log_newline 2006.285.08:13:57.66/k5log//k5ts3_log_newline 2006.285.08:13:58.40/k5log//k5ts4_log_newline 2006.285.08:13:58.42/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:13:58.42:setupk4=1 2006.285.08:13:58.42$setupk4/echo=on 2006.285.08:13:58.42$setupk4/pcalon 2006.285.08:13:58.42$pcalon/"no phase cal control is implemented here 2006.285.08:13:58.42$setupk4/"tpicd=stop 2006.285.08:13:58.42$setupk4/"rec=synch_on 2006.285.08:13:58.42$setupk4/"rec_mode=128 2006.285.08:13:58.42$setupk4/!* 2006.285.08:13:58.42$setupk4/recpk4 2006.285.08:13:58.42$recpk4/recpatch= 2006.285.08:13:58.42$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:13:58.42$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:13:58.42$setupk4/vck44 2006.285.08:13:58.42$vck44/valo=1,524.99 2006.285.08:13:58.42#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.08:13:58.42#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.08:13:58.42#ibcon#ireg 17 cls_cnt 0 2006.285.08:13:58.42#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:13:58.42#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:13:58.42#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:13:58.42#ibcon#enter wrdev, iclass 7, count 0 2006.285.08:13:58.42#ibcon#first serial, iclass 7, count 0 2006.285.08:13:58.42#ibcon#enter sib2, iclass 7, count 0 2006.285.08:13:58.42#ibcon#flushed, iclass 7, count 0 2006.285.08:13:58.43#ibcon#about to write, iclass 7, count 0 2006.285.08:13:58.43#ibcon#wrote, iclass 7, count 0 2006.285.08:13:58.43#ibcon#about to read 3, iclass 7, count 0 2006.285.08:13:58.44#ibcon#read 3, iclass 7, count 0 2006.285.08:13:58.44#ibcon#about to read 4, iclass 7, count 0 2006.285.08:13:58.44#ibcon#read 4, iclass 7, count 0 2006.285.08:13:58.44#ibcon#about to read 5, iclass 7, count 0 2006.285.08:13:58.44#ibcon#read 5, iclass 7, count 0 2006.285.08:13:58.44#ibcon#about to read 6, iclass 7, count 0 2006.285.08:13:58.44#ibcon#read 6, iclass 7, count 0 2006.285.08:13:58.44#ibcon#end of sib2, iclass 7, count 0 2006.285.08:13:58.44#ibcon#*mode == 0, iclass 7, count 0 2006.285.08:13:58.44#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.08:13:58.44#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:13:58.44#ibcon#*before write, iclass 7, count 0 2006.285.08:13:58.44#ibcon#enter sib2, iclass 7, count 0 2006.285.08:13:58.44#ibcon#flushed, iclass 7, count 0 2006.285.08:13:58.44#ibcon#about to write, iclass 7, count 0 2006.285.08:13:58.44#ibcon#wrote, iclass 7, count 0 2006.285.08:13:58.44#ibcon#about to read 3, iclass 7, count 0 2006.285.08:13:58.49#ibcon#read 3, iclass 7, count 0 2006.285.08:13:58.49#ibcon#about to read 4, iclass 7, count 0 2006.285.08:13:58.49#ibcon#read 4, iclass 7, count 0 2006.285.08:13:58.49#ibcon#about to read 5, iclass 7, count 0 2006.285.08:13:58.49#ibcon#read 5, iclass 7, count 0 2006.285.08:13:58.49#ibcon#about to read 6, iclass 7, count 0 2006.285.08:13:58.49#ibcon#read 6, iclass 7, count 0 2006.285.08:13:58.49#ibcon#end of sib2, iclass 7, count 0 2006.285.08:13:58.49#ibcon#*after write, iclass 7, count 0 2006.285.08:13:58.49#ibcon#*before return 0, iclass 7, count 0 2006.285.08:13:58.49#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:13:58.49#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:13:58.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.08:13:58.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.08:13:58.49$vck44/va=1,7 2006.285.08:13:58.50#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.08:13:58.50#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.08:13:58.50#ibcon#ireg 11 cls_cnt 2 2006.285.08:13:58.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:13:58.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:13:58.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:13:58.50#ibcon#enter wrdev, iclass 11, count 2 2006.285.08:13:58.50#ibcon#first serial, iclass 11, count 2 2006.285.08:13:58.50#ibcon#enter sib2, iclass 11, count 2 2006.285.08:13:58.50#ibcon#flushed, iclass 11, count 2 2006.285.08:13:58.50#ibcon#about to write, iclass 11, count 2 2006.285.08:13:58.50#ibcon#wrote, iclass 11, count 2 2006.285.08:13:58.50#ibcon#about to read 3, iclass 11, count 2 2006.285.08:13:58.51#ibcon#read 3, iclass 11, count 2 2006.285.08:13:58.51#ibcon#about to read 4, iclass 11, count 2 2006.285.08:13:58.51#ibcon#read 4, iclass 11, count 2 2006.285.08:13:58.51#ibcon#about to read 5, iclass 11, count 2 2006.285.08:13:58.51#ibcon#read 5, iclass 11, count 2 2006.285.08:13:58.51#ibcon#about to read 6, iclass 11, count 2 2006.285.08:13:58.51#ibcon#read 6, iclass 11, count 2 2006.285.08:13:58.51#ibcon#end of sib2, iclass 11, count 2 2006.285.08:13:58.51#ibcon#*mode == 0, iclass 11, count 2 2006.285.08:13:58.51#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.08:13:58.51#ibcon#[25=AT01-07\r\n] 2006.285.08:13:58.51#ibcon#*before write, iclass 11, count 2 2006.285.08:13:58.51#ibcon#enter sib2, iclass 11, count 2 2006.285.08:13:58.51#ibcon#flushed, iclass 11, count 2 2006.285.08:13:58.51#ibcon#about to write, iclass 11, count 2 2006.285.08:13:58.51#ibcon#wrote, iclass 11, count 2 2006.285.08:13:58.51#ibcon#about to read 3, iclass 11, count 2 2006.285.08:13:58.54#ibcon#read 3, iclass 11, count 2 2006.285.08:13:58.54#ibcon#about to read 4, iclass 11, count 2 2006.285.08:13:58.54#ibcon#read 4, iclass 11, count 2 2006.285.08:13:58.54#ibcon#about to read 5, iclass 11, count 2 2006.285.08:13:58.54#ibcon#read 5, iclass 11, count 2 2006.285.08:13:58.54#ibcon#about to read 6, iclass 11, count 2 2006.285.08:13:58.54#ibcon#read 6, iclass 11, count 2 2006.285.08:13:58.54#ibcon#end of sib2, iclass 11, count 2 2006.285.08:13:58.54#ibcon#*after write, iclass 11, count 2 2006.285.08:13:58.54#ibcon#*before return 0, iclass 11, count 2 2006.285.08:13:58.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:13:58.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:13:58.54#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.08:13:58.54#ibcon#ireg 7 cls_cnt 0 2006.285.08:13:58.54#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:13:58.66#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:13:58.66#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:13:58.66#ibcon#enter wrdev, iclass 11, count 0 2006.285.08:13:58.66#ibcon#first serial, iclass 11, count 0 2006.285.08:13:58.66#ibcon#enter sib2, iclass 11, count 0 2006.285.08:13:58.66#ibcon#flushed, iclass 11, count 0 2006.285.08:13:58.66#ibcon#about to write, iclass 11, count 0 2006.285.08:13:58.66#ibcon#wrote, iclass 11, count 0 2006.285.08:13:58.66#ibcon#about to read 3, iclass 11, count 0 2006.285.08:13:58.68#ibcon#read 3, iclass 11, count 0 2006.285.08:13:58.68#ibcon#about to read 4, iclass 11, count 0 2006.285.08:13:58.68#ibcon#read 4, iclass 11, count 0 2006.285.08:13:58.68#ibcon#about to read 5, iclass 11, count 0 2006.285.08:13:58.68#ibcon#read 5, iclass 11, count 0 2006.285.08:13:58.68#ibcon#about to read 6, iclass 11, count 0 2006.285.08:13:58.68#ibcon#read 6, iclass 11, count 0 2006.285.08:13:58.68#ibcon#end of sib2, iclass 11, count 0 2006.285.08:13:58.68#ibcon#*mode == 0, iclass 11, count 0 2006.285.08:13:58.68#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.08:13:58.68#ibcon#[25=USB\r\n] 2006.285.08:13:58.68#ibcon#*before write, iclass 11, count 0 2006.285.08:13:58.68#ibcon#enter sib2, iclass 11, count 0 2006.285.08:13:58.68#ibcon#flushed, iclass 11, count 0 2006.285.08:13:58.68#ibcon#about to write, iclass 11, count 0 2006.285.08:13:58.68#ibcon#wrote, iclass 11, count 0 2006.285.08:13:58.68#ibcon#about to read 3, iclass 11, count 0 2006.285.08:13:58.71#ibcon#read 3, iclass 11, count 0 2006.285.08:13:58.71#ibcon#about to read 4, iclass 11, count 0 2006.285.08:13:58.71#ibcon#read 4, iclass 11, count 0 2006.285.08:13:58.71#ibcon#about to read 5, iclass 11, count 0 2006.285.08:13:58.71#ibcon#read 5, iclass 11, count 0 2006.285.08:13:58.71#ibcon#about to read 6, iclass 11, count 0 2006.285.08:13:58.71#ibcon#read 6, iclass 11, count 0 2006.285.08:13:58.71#ibcon#end of sib2, iclass 11, count 0 2006.285.08:13:58.71#ibcon#*after write, iclass 11, count 0 2006.285.08:13:58.71#ibcon#*before return 0, iclass 11, count 0 2006.285.08:13:58.71#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:13:58.71#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:13:58.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.08:13:58.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.08:13:58.72$vck44/valo=2,534.99 2006.285.08:13:58.72#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.08:13:58.72#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.08:13:58.72#ibcon#ireg 17 cls_cnt 0 2006.285.08:13:58.72#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:13:58.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:13:58.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:13:58.72#ibcon#enter wrdev, iclass 13, count 0 2006.285.08:13:58.72#ibcon#first serial, iclass 13, count 0 2006.285.08:13:58.72#ibcon#enter sib2, iclass 13, count 0 2006.285.08:13:58.72#ibcon#flushed, iclass 13, count 0 2006.285.08:13:58.72#ibcon#about to write, iclass 13, count 0 2006.285.08:13:58.72#ibcon#wrote, iclass 13, count 0 2006.285.08:13:58.72#ibcon#about to read 3, iclass 13, count 0 2006.285.08:13:58.73#ibcon#read 3, iclass 13, count 0 2006.285.08:13:58.73#ibcon#about to read 4, iclass 13, count 0 2006.285.08:13:58.73#ibcon#read 4, iclass 13, count 0 2006.285.08:13:58.73#ibcon#about to read 5, iclass 13, count 0 2006.285.08:13:58.73#ibcon#read 5, iclass 13, count 0 2006.285.08:13:58.73#ibcon#about to read 6, iclass 13, count 0 2006.285.08:13:58.73#ibcon#read 6, iclass 13, count 0 2006.285.08:13:58.73#ibcon#end of sib2, iclass 13, count 0 2006.285.08:13:58.73#ibcon#*mode == 0, iclass 13, count 0 2006.285.08:13:58.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.08:13:58.73#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:13:58.73#ibcon#*before write, iclass 13, count 0 2006.285.08:13:58.73#ibcon#enter sib2, iclass 13, count 0 2006.285.08:13:58.73#ibcon#flushed, iclass 13, count 0 2006.285.08:13:58.73#ibcon#about to write, iclass 13, count 0 2006.285.08:13:58.73#ibcon#wrote, iclass 13, count 0 2006.285.08:13:58.73#ibcon#about to read 3, iclass 13, count 0 2006.285.08:13:58.77#ibcon#read 3, iclass 13, count 0 2006.285.08:13:58.77#ibcon#about to read 4, iclass 13, count 0 2006.285.08:13:58.77#ibcon#read 4, iclass 13, count 0 2006.285.08:13:58.77#ibcon#about to read 5, iclass 13, count 0 2006.285.08:13:58.77#ibcon#read 5, iclass 13, count 0 2006.285.08:13:58.77#ibcon#about to read 6, iclass 13, count 0 2006.285.08:13:58.77#ibcon#read 6, iclass 13, count 0 2006.285.08:13:58.77#ibcon#end of sib2, iclass 13, count 0 2006.285.08:13:58.77#ibcon#*after write, iclass 13, count 0 2006.285.08:13:58.77#ibcon#*before return 0, iclass 13, count 0 2006.285.08:13:58.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:13:58.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:13:58.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.08:13:58.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.08:13:58.78$vck44/va=2,6 2006.285.08:13:58.78#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.08:13:58.78#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.08:13:58.78#ibcon#ireg 11 cls_cnt 2 2006.285.08:13:58.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:13:58.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:13:58.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:13:58.82#ibcon#enter wrdev, iclass 15, count 2 2006.285.08:13:58.82#ibcon#first serial, iclass 15, count 2 2006.285.08:13:58.82#ibcon#enter sib2, iclass 15, count 2 2006.285.08:13:58.82#ibcon#flushed, iclass 15, count 2 2006.285.08:13:58.82#ibcon#about to write, iclass 15, count 2 2006.285.08:13:58.82#ibcon#wrote, iclass 15, count 2 2006.285.08:13:58.82#ibcon#about to read 3, iclass 15, count 2 2006.285.08:13:58.84#ibcon#read 3, iclass 15, count 2 2006.285.08:13:58.84#ibcon#about to read 4, iclass 15, count 2 2006.285.08:13:58.84#ibcon#read 4, iclass 15, count 2 2006.285.08:13:58.84#ibcon#about to read 5, iclass 15, count 2 2006.285.08:13:58.84#ibcon#read 5, iclass 15, count 2 2006.285.08:13:58.84#ibcon#about to read 6, iclass 15, count 2 2006.285.08:13:58.84#ibcon#read 6, iclass 15, count 2 2006.285.08:13:58.84#ibcon#end of sib2, iclass 15, count 2 2006.285.08:13:58.84#ibcon#*mode == 0, iclass 15, count 2 2006.285.08:13:58.84#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.08:13:58.84#ibcon#[25=AT02-06\r\n] 2006.285.08:13:58.84#ibcon#*before write, iclass 15, count 2 2006.285.08:13:58.84#ibcon#enter sib2, iclass 15, count 2 2006.285.08:13:58.84#ibcon#flushed, iclass 15, count 2 2006.285.08:13:58.84#ibcon#about to write, iclass 15, count 2 2006.285.08:13:58.84#ibcon#wrote, iclass 15, count 2 2006.285.08:13:58.84#ibcon#about to read 3, iclass 15, count 2 2006.285.08:13:58.87#ibcon#read 3, iclass 15, count 2 2006.285.08:13:58.87#ibcon#about to read 4, iclass 15, count 2 2006.285.08:13:58.87#ibcon#read 4, iclass 15, count 2 2006.285.08:13:58.87#ibcon#about to read 5, iclass 15, count 2 2006.285.08:13:58.87#ibcon#read 5, iclass 15, count 2 2006.285.08:13:58.87#ibcon#about to read 6, iclass 15, count 2 2006.285.08:13:58.87#ibcon#read 6, iclass 15, count 2 2006.285.08:13:58.87#ibcon#end of sib2, iclass 15, count 2 2006.285.08:13:58.87#ibcon#*after write, iclass 15, count 2 2006.285.08:13:58.87#ibcon#*before return 0, iclass 15, count 2 2006.285.08:13:58.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:13:58.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:13:58.87#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.08:13:58.87#ibcon#ireg 7 cls_cnt 0 2006.285.08:13:58.87#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:13:58.99#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:13:58.99#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:13:58.99#ibcon#enter wrdev, iclass 15, count 0 2006.285.08:13:58.99#ibcon#first serial, iclass 15, count 0 2006.285.08:13:58.99#ibcon#enter sib2, iclass 15, count 0 2006.285.08:13:58.99#ibcon#flushed, iclass 15, count 0 2006.285.08:13:58.99#ibcon#about to write, iclass 15, count 0 2006.285.08:13:58.99#ibcon#wrote, iclass 15, count 0 2006.285.08:13:58.99#ibcon#about to read 3, iclass 15, count 0 2006.285.08:13:59.01#ibcon#read 3, iclass 15, count 0 2006.285.08:13:59.01#ibcon#about to read 4, iclass 15, count 0 2006.285.08:13:59.01#ibcon#read 4, iclass 15, count 0 2006.285.08:13:59.01#ibcon#about to read 5, iclass 15, count 0 2006.285.08:13:59.01#ibcon#read 5, iclass 15, count 0 2006.285.08:13:59.01#ibcon#about to read 6, iclass 15, count 0 2006.285.08:13:59.01#ibcon#read 6, iclass 15, count 0 2006.285.08:13:59.01#ibcon#end of sib2, iclass 15, count 0 2006.285.08:13:59.01#ibcon#*mode == 0, iclass 15, count 0 2006.285.08:13:59.01#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.08:13:59.01#ibcon#[25=USB\r\n] 2006.285.08:13:59.01#ibcon#*before write, iclass 15, count 0 2006.285.08:13:59.01#ibcon#enter sib2, iclass 15, count 0 2006.285.08:13:59.01#ibcon#flushed, iclass 15, count 0 2006.285.08:13:59.01#ibcon#about to write, iclass 15, count 0 2006.285.08:13:59.01#ibcon#wrote, iclass 15, count 0 2006.285.08:13:59.01#ibcon#about to read 3, iclass 15, count 0 2006.285.08:13:59.04#ibcon#read 3, iclass 15, count 0 2006.285.08:13:59.04#ibcon#about to read 4, iclass 15, count 0 2006.285.08:13:59.04#ibcon#read 4, iclass 15, count 0 2006.285.08:13:59.04#ibcon#about to read 5, iclass 15, count 0 2006.285.08:13:59.04#ibcon#read 5, iclass 15, count 0 2006.285.08:13:59.04#ibcon#about to read 6, iclass 15, count 0 2006.285.08:13:59.04#ibcon#read 6, iclass 15, count 0 2006.285.08:13:59.04#ibcon#end of sib2, iclass 15, count 0 2006.285.08:13:59.04#ibcon#*after write, iclass 15, count 0 2006.285.08:13:59.04#ibcon#*before return 0, iclass 15, count 0 2006.285.08:13:59.04#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:13:59.04#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:13:59.04#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.08:13:59.04#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.08:13:59.05$vck44/valo=3,564.99 2006.285.08:13:59.05#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.08:13:59.05#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.08:13:59.05#ibcon#ireg 17 cls_cnt 0 2006.285.08:13:59.05#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:13:59.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:13:59.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:13:59.05#ibcon#enter wrdev, iclass 17, count 0 2006.285.08:13:59.05#ibcon#first serial, iclass 17, count 0 2006.285.08:13:59.05#ibcon#enter sib2, iclass 17, count 0 2006.285.08:13:59.05#ibcon#flushed, iclass 17, count 0 2006.285.08:13:59.05#ibcon#about to write, iclass 17, count 0 2006.285.08:13:59.05#ibcon#wrote, iclass 17, count 0 2006.285.08:13:59.05#ibcon#about to read 3, iclass 17, count 0 2006.285.08:13:59.06#ibcon#read 3, iclass 17, count 0 2006.285.08:13:59.06#ibcon#about to read 4, iclass 17, count 0 2006.285.08:13:59.06#ibcon#read 4, iclass 17, count 0 2006.285.08:13:59.06#ibcon#about to read 5, iclass 17, count 0 2006.285.08:13:59.06#ibcon#read 5, iclass 17, count 0 2006.285.08:13:59.06#ibcon#about to read 6, iclass 17, count 0 2006.285.08:13:59.06#ibcon#read 6, iclass 17, count 0 2006.285.08:13:59.06#ibcon#end of sib2, iclass 17, count 0 2006.285.08:13:59.06#ibcon#*mode == 0, iclass 17, count 0 2006.285.08:13:59.06#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.08:13:59.06#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:13:59.06#ibcon#*before write, iclass 17, count 0 2006.285.08:13:59.06#ibcon#enter sib2, iclass 17, count 0 2006.285.08:13:59.06#ibcon#flushed, iclass 17, count 0 2006.285.08:13:59.06#ibcon#about to write, iclass 17, count 0 2006.285.08:13:59.06#ibcon#wrote, iclass 17, count 0 2006.285.08:13:59.06#ibcon#about to read 3, iclass 17, count 0 2006.285.08:13:59.10#ibcon#read 3, iclass 17, count 0 2006.285.08:13:59.10#ibcon#about to read 4, iclass 17, count 0 2006.285.08:13:59.10#ibcon#read 4, iclass 17, count 0 2006.285.08:13:59.10#ibcon#about to read 5, iclass 17, count 0 2006.285.08:13:59.10#ibcon#read 5, iclass 17, count 0 2006.285.08:13:59.10#ibcon#about to read 6, iclass 17, count 0 2006.285.08:13:59.10#ibcon#read 6, iclass 17, count 0 2006.285.08:13:59.10#ibcon#end of sib2, iclass 17, count 0 2006.285.08:13:59.10#ibcon#*after write, iclass 17, count 0 2006.285.08:13:59.10#ibcon#*before return 0, iclass 17, count 0 2006.285.08:13:59.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:13:59.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:13:59.10#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.08:13:59.10#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.08:13:59.11$vck44/va=3,7 2006.285.08:13:59.11#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.08:13:59.11#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.08:13:59.11#ibcon#ireg 11 cls_cnt 2 2006.285.08:13:59.11#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:13:59.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:13:59.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:13:59.15#ibcon#enter wrdev, iclass 19, count 2 2006.285.08:13:59.15#ibcon#first serial, iclass 19, count 2 2006.285.08:13:59.15#ibcon#enter sib2, iclass 19, count 2 2006.285.08:13:59.15#ibcon#flushed, iclass 19, count 2 2006.285.08:13:59.15#ibcon#about to write, iclass 19, count 2 2006.285.08:13:59.15#ibcon#wrote, iclass 19, count 2 2006.285.08:13:59.15#ibcon#about to read 3, iclass 19, count 2 2006.285.08:13:59.17#ibcon#read 3, iclass 19, count 2 2006.285.08:13:59.17#ibcon#about to read 4, iclass 19, count 2 2006.285.08:13:59.17#ibcon#read 4, iclass 19, count 2 2006.285.08:13:59.17#ibcon#about to read 5, iclass 19, count 2 2006.285.08:13:59.17#ibcon#read 5, iclass 19, count 2 2006.285.08:13:59.17#ibcon#about to read 6, iclass 19, count 2 2006.285.08:13:59.17#ibcon#read 6, iclass 19, count 2 2006.285.08:13:59.17#ibcon#end of sib2, iclass 19, count 2 2006.285.08:13:59.17#ibcon#*mode == 0, iclass 19, count 2 2006.285.08:13:59.17#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.08:13:59.17#ibcon#[25=AT03-07\r\n] 2006.285.08:13:59.17#ibcon#*before write, iclass 19, count 2 2006.285.08:13:59.17#ibcon#enter sib2, iclass 19, count 2 2006.285.08:13:59.17#ibcon#flushed, iclass 19, count 2 2006.285.08:13:59.17#ibcon#about to write, iclass 19, count 2 2006.285.08:13:59.17#ibcon#wrote, iclass 19, count 2 2006.285.08:13:59.17#ibcon#about to read 3, iclass 19, count 2 2006.285.08:13:59.20#ibcon#read 3, iclass 19, count 2 2006.285.08:13:59.20#ibcon#about to read 4, iclass 19, count 2 2006.285.08:13:59.20#ibcon#read 4, iclass 19, count 2 2006.285.08:13:59.20#ibcon#about to read 5, iclass 19, count 2 2006.285.08:13:59.20#ibcon#read 5, iclass 19, count 2 2006.285.08:13:59.20#ibcon#about to read 6, iclass 19, count 2 2006.285.08:13:59.20#ibcon#read 6, iclass 19, count 2 2006.285.08:13:59.20#ibcon#end of sib2, iclass 19, count 2 2006.285.08:13:59.20#ibcon#*after write, iclass 19, count 2 2006.285.08:13:59.20#ibcon#*before return 0, iclass 19, count 2 2006.285.08:13:59.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:13:59.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:13:59.20#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.08:13:59.20#ibcon#ireg 7 cls_cnt 0 2006.285.08:13:59.20#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:13:59.32#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:13:59.32#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:13:59.32#ibcon#enter wrdev, iclass 19, count 0 2006.285.08:13:59.32#ibcon#first serial, iclass 19, count 0 2006.285.08:13:59.32#ibcon#enter sib2, iclass 19, count 0 2006.285.08:13:59.32#ibcon#flushed, iclass 19, count 0 2006.285.08:13:59.32#ibcon#about to write, iclass 19, count 0 2006.285.08:13:59.32#ibcon#wrote, iclass 19, count 0 2006.285.08:13:59.32#ibcon#about to read 3, iclass 19, count 0 2006.285.08:13:59.34#ibcon#read 3, iclass 19, count 0 2006.285.08:13:59.34#ibcon#about to read 4, iclass 19, count 0 2006.285.08:13:59.34#ibcon#read 4, iclass 19, count 0 2006.285.08:13:59.34#ibcon#about to read 5, iclass 19, count 0 2006.285.08:13:59.34#ibcon#read 5, iclass 19, count 0 2006.285.08:13:59.34#ibcon#about to read 6, iclass 19, count 0 2006.285.08:13:59.34#ibcon#read 6, iclass 19, count 0 2006.285.08:13:59.34#ibcon#end of sib2, iclass 19, count 0 2006.285.08:13:59.34#ibcon#*mode == 0, iclass 19, count 0 2006.285.08:13:59.34#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.08:13:59.34#ibcon#[25=USB\r\n] 2006.285.08:13:59.34#ibcon#*before write, iclass 19, count 0 2006.285.08:13:59.34#ibcon#enter sib2, iclass 19, count 0 2006.285.08:13:59.34#ibcon#flushed, iclass 19, count 0 2006.285.08:13:59.34#ibcon#about to write, iclass 19, count 0 2006.285.08:13:59.34#ibcon#wrote, iclass 19, count 0 2006.285.08:13:59.34#ibcon#about to read 3, iclass 19, count 0 2006.285.08:13:59.37#ibcon#read 3, iclass 19, count 0 2006.285.08:13:59.37#ibcon#about to read 4, iclass 19, count 0 2006.285.08:13:59.37#ibcon#read 4, iclass 19, count 0 2006.285.08:13:59.37#ibcon#about to read 5, iclass 19, count 0 2006.285.08:13:59.37#ibcon#read 5, iclass 19, count 0 2006.285.08:13:59.37#ibcon#about to read 6, iclass 19, count 0 2006.285.08:13:59.37#ibcon#read 6, iclass 19, count 0 2006.285.08:13:59.37#ibcon#end of sib2, iclass 19, count 0 2006.285.08:13:59.37#ibcon#*after write, iclass 19, count 0 2006.285.08:13:59.37#ibcon#*before return 0, iclass 19, count 0 2006.285.08:13:59.37#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:13:59.37#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:13:59.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.08:13:59.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.08:13:59.38$vck44/valo=4,624.99 2006.285.08:13:59.38#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.08:13:59.38#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.08:13:59.38#ibcon#ireg 17 cls_cnt 0 2006.285.08:13:59.38#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:13:59.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:13:59.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:13:59.38#ibcon#enter wrdev, iclass 21, count 0 2006.285.08:13:59.38#ibcon#first serial, iclass 21, count 0 2006.285.08:13:59.38#ibcon#enter sib2, iclass 21, count 0 2006.285.08:13:59.38#ibcon#flushed, iclass 21, count 0 2006.285.08:13:59.38#ibcon#about to write, iclass 21, count 0 2006.285.08:13:59.38#ibcon#wrote, iclass 21, count 0 2006.285.08:13:59.38#ibcon#about to read 3, iclass 21, count 0 2006.285.08:13:59.39#ibcon#read 3, iclass 21, count 0 2006.285.08:13:59.39#ibcon#about to read 4, iclass 21, count 0 2006.285.08:13:59.39#ibcon#read 4, iclass 21, count 0 2006.285.08:13:59.39#ibcon#about to read 5, iclass 21, count 0 2006.285.08:13:59.39#ibcon#read 5, iclass 21, count 0 2006.285.08:13:59.39#ibcon#about to read 6, iclass 21, count 0 2006.285.08:13:59.39#ibcon#read 6, iclass 21, count 0 2006.285.08:13:59.39#ibcon#end of sib2, iclass 21, count 0 2006.285.08:13:59.39#ibcon#*mode == 0, iclass 21, count 0 2006.285.08:13:59.39#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.08:13:59.39#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:13:59.39#ibcon#*before write, iclass 21, count 0 2006.285.08:13:59.39#ibcon#enter sib2, iclass 21, count 0 2006.285.08:13:59.39#ibcon#flushed, iclass 21, count 0 2006.285.08:13:59.39#ibcon#about to write, iclass 21, count 0 2006.285.08:13:59.39#ibcon#wrote, iclass 21, count 0 2006.285.08:13:59.39#ibcon#about to read 3, iclass 21, count 0 2006.285.08:13:59.43#ibcon#read 3, iclass 21, count 0 2006.285.08:13:59.43#ibcon#about to read 4, iclass 21, count 0 2006.285.08:13:59.43#ibcon#read 4, iclass 21, count 0 2006.285.08:13:59.43#ibcon#about to read 5, iclass 21, count 0 2006.285.08:13:59.43#ibcon#read 5, iclass 21, count 0 2006.285.08:13:59.43#ibcon#about to read 6, iclass 21, count 0 2006.285.08:13:59.43#ibcon#read 6, iclass 21, count 0 2006.285.08:13:59.43#ibcon#end of sib2, iclass 21, count 0 2006.285.08:13:59.43#ibcon#*after write, iclass 21, count 0 2006.285.08:13:59.43#ibcon#*before return 0, iclass 21, count 0 2006.285.08:13:59.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:13:59.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:13:59.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.08:13:59.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.08:13:59.44$vck44/va=4,6 2006.285.08:13:59.44#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.08:13:59.44#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.08:13:59.44#ibcon#ireg 11 cls_cnt 2 2006.285.08:13:59.44#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:13:59.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:13:59.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:13:59.48#ibcon#enter wrdev, iclass 23, count 2 2006.285.08:13:59.48#ibcon#first serial, iclass 23, count 2 2006.285.08:13:59.48#ibcon#enter sib2, iclass 23, count 2 2006.285.08:13:59.48#ibcon#flushed, iclass 23, count 2 2006.285.08:13:59.48#ibcon#about to write, iclass 23, count 2 2006.285.08:13:59.48#ibcon#wrote, iclass 23, count 2 2006.285.08:13:59.48#ibcon#about to read 3, iclass 23, count 2 2006.285.08:13:59.50#ibcon#read 3, iclass 23, count 2 2006.285.08:13:59.50#ibcon#about to read 4, iclass 23, count 2 2006.285.08:13:59.50#ibcon#read 4, iclass 23, count 2 2006.285.08:13:59.50#ibcon#about to read 5, iclass 23, count 2 2006.285.08:13:59.50#ibcon#read 5, iclass 23, count 2 2006.285.08:13:59.50#ibcon#about to read 6, iclass 23, count 2 2006.285.08:13:59.50#ibcon#read 6, iclass 23, count 2 2006.285.08:13:59.50#ibcon#end of sib2, iclass 23, count 2 2006.285.08:13:59.50#ibcon#*mode == 0, iclass 23, count 2 2006.285.08:13:59.50#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.08:13:59.50#ibcon#[25=AT04-06\r\n] 2006.285.08:13:59.50#ibcon#*before write, iclass 23, count 2 2006.285.08:13:59.50#ibcon#enter sib2, iclass 23, count 2 2006.285.08:13:59.50#ibcon#flushed, iclass 23, count 2 2006.285.08:13:59.50#ibcon#about to write, iclass 23, count 2 2006.285.08:13:59.50#ibcon#wrote, iclass 23, count 2 2006.285.08:13:59.50#ibcon#about to read 3, iclass 23, count 2 2006.285.08:13:59.53#ibcon#read 3, iclass 23, count 2 2006.285.08:13:59.53#ibcon#about to read 4, iclass 23, count 2 2006.285.08:13:59.53#ibcon#read 4, iclass 23, count 2 2006.285.08:13:59.53#ibcon#about to read 5, iclass 23, count 2 2006.285.08:13:59.53#ibcon#read 5, iclass 23, count 2 2006.285.08:13:59.53#ibcon#about to read 6, iclass 23, count 2 2006.285.08:13:59.53#ibcon#read 6, iclass 23, count 2 2006.285.08:13:59.53#ibcon#end of sib2, iclass 23, count 2 2006.285.08:13:59.53#ibcon#*after write, iclass 23, count 2 2006.285.08:13:59.53#ibcon#*before return 0, iclass 23, count 2 2006.285.08:13:59.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:13:59.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:13:59.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.08:13:59.53#ibcon#ireg 7 cls_cnt 0 2006.285.08:13:59.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:13:59.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:13:59.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:13:59.65#ibcon#enter wrdev, iclass 23, count 0 2006.285.08:13:59.65#ibcon#first serial, iclass 23, count 0 2006.285.08:13:59.65#ibcon#enter sib2, iclass 23, count 0 2006.285.08:13:59.65#ibcon#flushed, iclass 23, count 0 2006.285.08:13:59.65#ibcon#about to write, iclass 23, count 0 2006.285.08:13:59.65#ibcon#wrote, iclass 23, count 0 2006.285.08:13:59.65#ibcon#about to read 3, iclass 23, count 0 2006.285.08:13:59.67#ibcon#read 3, iclass 23, count 0 2006.285.08:13:59.67#ibcon#about to read 4, iclass 23, count 0 2006.285.08:13:59.67#ibcon#read 4, iclass 23, count 0 2006.285.08:13:59.67#ibcon#about to read 5, iclass 23, count 0 2006.285.08:13:59.67#ibcon#read 5, iclass 23, count 0 2006.285.08:13:59.67#ibcon#about to read 6, iclass 23, count 0 2006.285.08:13:59.67#ibcon#read 6, iclass 23, count 0 2006.285.08:13:59.67#ibcon#end of sib2, iclass 23, count 0 2006.285.08:13:59.67#ibcon#*mode == 0, iclass 23, count 0 2006.285.08:13:59.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.08:13:59.67#ibcon#[25=USB\r\n] 2006.285.08:13:59.67#ibcon#*before write, iclass 23, count 0 2006.285.08:13:59.67#ibcon#enter sib2, iclass 23, count 0 2006.285.08:13:59.67#ibcon#flushed, iclass 23, count 0 2006.285.08:13:59.67#ibcon#about to write, iclass 23, count 0 2006.285.08:13:59.67#ibcon#wrote, iclass 23, count 0 2006.285.08:13:59.67#ibcon#about to read 3, iclass 23, count 0 2006.285.08:13:59.70#ibcon#read 3, iclass 23, count 0 2006.285.08:13:59.70#ibcon#about to read 4, iclass 23, count 0 2006.285.08:13:59.70#ibcon#read 4, iclass 23, count 0 2006.285.08:13:59.70#ibcon#about to read 5, iclass 23, count 0 2006.285.08:13:59.70#ibcon#read 5, iclass 23, count 0 2006.285.08:13:59.70#ibcon#about to read 6, iclass 23, count 0 2006.285.08:13:59.70#ibcon#read 6, iclass 23, count 0 2006.285.08:13:59.70#ibcon#end of sib2, iclass 23, count 0 2006.285.08:13:59.70#ibcon#*after write, iclass 23, count 0 2006.285.08:13:59.70#ibcon#*before return 0, iclass 23, count 0 2006.285.08:13:59.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:13:59.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:13:59.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.08:13:59.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.08:13:59.71$vck44/valo=5,734.99 2006.285.08:13:59.71#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.08:13:59.71#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.08:13:59.71#ibcon#ireg 17 cls_cnt 0 2006.285.08:13:59.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:13:59.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:13:59.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:13:59.71#ibcon#enter wrdev, iclass 25, count 0 2006.285.08:13:59.71#ibcon#first serial, iclass 25, count 0 2006.285.08:13:59.71#ibcon#enter sib2, iclass 25, count 0 2006.285.08:13:59.71#ibcon#flushed, iclass 25, count 0 2006.285.08:13:59.71#ibcon#about to write, iclass 25, count 0 2006.285.08:13:59.71#ibcon#wrote, iclass 25, count 0 2006.285.08:13:59.71#ibcon#about to read 3, iclass 25, count 0 2006.285.08:13:59.72#ibcon#read 3, iclass 25, count 0 2006.285.08:13:59.72#ibcon#about to read 4, iclass 25, count 0 2006.285.08:13:59.72#ibcon#read 4, iclass 25, count 0 2006.285.08:13:59.72#ibcon#about to read 5, iclass 25, count 0 2006.285.08:13:59.72#ibcon#read 5, iclass 25, count 0 2006.285.08:13:59.72#ibcon#about to read 6, iclass 25, count 0 2006.285.08:13:59.72#ibcon#read 6, iclass 25, count 0 2006.285.08:13:59.72#ibcon#end of sib2, iclass 25, count 0 2006.285.08:13:59.72#ibcon#*mode == 0, iclass 25, count 0 2006.285.08:13:59.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.08:13:59.72#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:13:59.72#ibcon#*before write, iclass 25, count 0 2006.285.08:13:59.72#ibcon#enter sib2, iclass 25, count 0 2006.285.08:13:59.72#ibcon#flushed, iclass 25, count 0 2006.285.08:13:59.72#ibcon#about to write, iclass 25, count 0 2006.285.08:13:59.72#ibcon#wrote, iclass 25, count 0 2006.285.08:13:59.72#ibcon#about to read 3, iclass 25, count 0 2006.285.08:13:59.76#ibcon#read 3, iclass 25, count 0 2006.285.08:13:59.76#ibcon#about to read 4, iclass 25, count 0 2006.285.08:13:59.76#ibcon#read 4, iclass 25, count 0 2006.285.08:13:59.76#ibcon#about to read 5, iclass 25, count 0 2006.285.08:13:59.76#ibcon#read 5, iclass 25, count 0 2006.285.08:13:59.76#ibcon#about to read 6, iclass 25, count 0 2006.285.08:13:59.76#ibcon#read 6, iclass 25, count 0 2006.285.08:13:59.76#ibcon#end of sib2, iclass 25, count 0 2006.285.08:13:59.76#ibcon#*after write, iclass 25, count 0 2006.285.08:13:59.76#ibcon#*before return 0, iclass 25, count 0 2006.285.08:13:59.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:13:59.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:13:59.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.08:13:59.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.08:13:59.77$vck44/va=5,3 2006.285.08:13:59.77#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.08:13:59.77#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.08:13:59.77#ibcon#ireg 11 cls_cnt 2 2006.285.08:13:59.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:13:59.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:13:59.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:13:59.81#ibcon#enter wrdev, iclass 27, count 2 2006.285.08:13:59.81#ibcon#first serial, iclass 27, count 2 2006.285.08:13:59.81#ibcon#enter sib2, iclass 27, count 2 2006.285.08:13:59.81#ibcon#flushed, iclass 27, count 2 2006.285.08:13:59.81#ibcon#about to write, iclass 27, count 2 2006.285.08:13:59.81#ibcon#wrote, iclass 27, count 2 2006.285.08:13:59.81#ibcon#about to read 3, iclass 27, count 2 2006.285.08:13:59.83#ibcon#read 3, iclass 27, count 2 2006.285.08:13:59.83#ibcon#about to read 4, iclass 27, count 2 2006.285.08:13:59.83#ibcon#read 4, iclass 27, count 2 2006.285.08:13:59.83#ibcon#about to read 5, iclass 27, count 2 2006.285.08:13:59.83#ibcon#read 5, iclass 27, count 2 2006.285.08:13:59.83#ibcon#about to read 6, iclass 27, count 2 2006.285.08:13:59.83#ibcon#read 6, iclass 27, count 2 2006.285.08:13:59.83#ibcon#end of sib2, iclass 27, count 2 2006.285.08:13:59.83#ibcon#*mode == 0, iclass 27, count 2 2006.285.08:13:59.83#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.08:13:59.83#ibcon#[25=AT05-03\r\n] 2006.285.08:13:59.83#ibcon#*before write, iclass 27, count 2 2006.285.08:13:59.83#ibcon#enter sib2, iclass 27, count 2 2006.285.08:13:59.83#ibcon#flushed, iclass 27, count 2 2006.285.08:13:59.83#ibcon#about to write, iclass 27, count 2 2006.285.08:13:59.83#ibcon#wrote, iclass 27, count 2 2006.285.08:13:59.83#ibcon#about to read 3, iclass 27, count 2 2006.285.08:13:59.86#ibcon#read 3, iclass 27, count 2 2006.285.08:13:59.86#ibcon#about to read 4, iclass 27, count 2 2006.285.08:13:59.86#ibcon#read 4, iclass 27, count 2 2006.285.08:13:59.86#ibcon#about to read 5, iclass 27, count 2 2006.285.08:13:59.86#ibcon#read 5, iclass 27, count 2 2006.285.08:13:59.86#ibcon#about to read 6, iclass 27, count 2 2006.285.08:13:59.86#ibcon#read 6, iclass 27, count 2 2006.285.08:13:59.86#ibcon#end of sib2, iclass 27, count 2 2006.285.08:13:59.86#ibcon#*after write, iclass 27, count 2 2006.285.08:13:59.86#ibcon#*before return 0, iclass 27, count 2 2006.285.08:13:59.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:13:59.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:13:59.86#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.08:13:59.86#ibcon#ireg 7 cls_cnt 0 2006.285.08:13:59.86#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:13:59.98#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:13:59.98#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:13:59.98#ibcon#enter wrdev, iclass 27, count 0 2006.285.08:13:59.98#ibcon#first serial, iclass 27, count 0 2006.285.08:13:59.98#ibcon#enter sib2, iclass 27, count 0 2006.285.08:13:59.98#ibcon#flushed, iclass 27, count 0 2006.285.08:13:59.98#ibcon#about to write, iclass 27, count 0 2006.285.08:13:59.98#ibcon#wrote, iclass 27, count 0 2006.285.08:13:59.98#ibcon#about to read 3, iclass 27, count 0 2006.285.08:14:00.00#ibcon#read 3, iclass 27, count 0 2006.285.08:14:00.00#ibcon#about to read 4, iclass 27, count 0 2006.285.08:14:00.00#ibcon#read 4, iclass 27, count 0 2006.285.08:14:00.00#ibcon#about to read 5, iclass 27, count 0 2006.285.08:14:00.00#ibcon#read 5, iclass 27, count 0 2006.285.08:14:00.00#ibcon#about to read 6, iclass 27, count 0 2006.285.08:14:00.00#ibcon#read 6, iclass 27, count 0 2006.285.08:14:00.00#ibcon#end of sib2, iclass 27, count 0 2006.285.08:14:00.00#ibcon#*mode == 0, iclass 27, count 0 2006.285.08:14:00.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.08:14:00.00#ibcon#[25=USB\r\n] 2006.285.08:14:00.00#ibcon#*before write, iclass 27, count 0 2006.285.08:14:00.00#ibcon#enter sib2, iclass 27, count 0 2006.285.08:14:00.00#ibcon#flushed, iclass 27, count 0 2006.285.08:14:00.00#ibcon#about to write, iclass 27, count 0 2006.285.08:14:00.00#ibcon#wrote, iclass 27, count 0 2006.285.08:14:00.00#ibcon#about to read 3, iclass 27, count 0 2006.285.08:14:00.03#ibcon#read 3, iclass 27, count 0 2006.285.08:14:00.03#ibcon#about to read 4, iclass 27, count 0 2006.285.08:14:00.03#ibcon#read 4, iclass 27, count 0 2006.285.08:14:00.03#ibcon#about to read 5, iclass 27, count 0 2006.285.08:14:00.03#ibcon#read 5, iclass 27, count 0 2006.285.08:14:00.03#ibcon#about to read 6, iclass 27, count 0 2006.285.08:14:00.03#ibcon#read 6, iclass 27, count 0 2006.285.08:14:00.03#ibcon#end of sib2, iclass 27, count 0 2006.285.08:14:00.03#ibcon#*after write, iclass 27, count 0 2006.285.08:14:00.03#ibcon#*before return 0, iclass 27, count 0 2006.285.08:14:00.03#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:14:00.03#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:14:00.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.08:14:00.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.08:14:00.04$vck44/valo=6,814.99 2006.285.08:14:00.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.08:14:00.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.08:14:00.04#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:00.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:14:00.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:14:00.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:14:00.04#ibcon#enter wrdev, iclass 29, count 0 2006.285.08:14:00.04#ibcon#first serial, iclass 29, count 0 2006.285.08:14:00.04#ibcon#enter sib2, iclass 29, count 0 2006.285.08:14:00.04#ibcon#flushed, iclass 29, count 0 2006.285.08:14:00.04#ibcon#about to write, iclass 29, count 0 2006.285.08:14:00.04#ibcon#wrote, iclass 29, count 0 2006.285.08:14:00.04#ibcon#about to read 3, iclass 29, count 0 2006.285.08:14:00.05#ibcon#read 3, iclass 29, count 0 2006.285.08:14:00.05#ibcon#about to read 4, iclass 29, count 0 2006.285.08:14:00.05#ibcon#read 4, iclass 29, count 0 2006.285.08:14:00.05#ibcon#about to read 5, iclass 29, count 0 2006.285.08:14:00.05#ibcon#read 5, iclass 29, count 0 2006.285.08:14:00.05#ibcon#about to read 6, iclass 29, count 0 2006.285.08:14:00.05#ibcon#read 6, iclass 29, count 0 2006.285.08:14:00.05#ibcon#end of sib2, iclass 29, count 0 2006.285.08:14:00.05#ibcon#*mode == 0, iclass 29, count 0 2006.285.08:14:00.05#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.08:14:00.05#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:14:00.05#ibcon#*before write, iclass 29, count 0 2006.285.08:14:00.05#ibcon#enter sib2, iclass 29, count 0 2006.285.08:14:00.05#ibcon#flushed, iclass 29, count 0 2006.285.08:14:00.05#ibcon#about to write, iclass 29, count 0 2006.285.08:14:00.05#ibcon#wrote, iclass 29, count 0 2006.285.08:14:00.05#ibcon#about to read 3, iclass 29, count 0 2006.285.08:14:00.09#ibcon#read 3, iclass 29, count 0 2006.285.08:14:00.09#ibcon#about to read 4, iclass 29, count 0 2006.285.08:14:00.09#ibcon#read 4, iclass 29, count 0 2006.285.08:14:00.09#ibcon#about to read 5, iclass 29, count 0 2006.285.08:14:00.09#ibcon#read 5, iclass 29, count 0 2006.285.08:14:00.09#ibcon#about to read 6, iclass 29, count 0 2006.285.08:14:00.09#ibcon#read 6, iclass 29, count 0 2006.285.08:14:00.09#ibcon#end of sib2, iclass 29, count 0 2006.285.08:14:00.09#ibcon#*after write, iclass 29, count 0 2006.285.08:14:00.09#ibcon#*before return 0, iclass 29, count 0 2006.285.08:14:00.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:14:00.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:14:00.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.08:14:00.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.08:14:00.10$vck44/va=6,4 2006.285.08:14:00.10#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.08:14:00.10#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.08:14:00.10#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:00.10#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:14:00.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:14:00.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:14:00.14#ibcon#enter wrdev, iclass 31, count 2 2006.285.08:14:00.14#ibcon#first serial, iclass 31, count 2 2006.285.08:14:00.14#ibcon#enter sib2, iclass 31, count 2 2006.285.08:14:00.14#ibcon#flushed, iclass 31, count 2 2006.285.08:14:00.14#ibcon#about to write, iclass 31, count 2 2006.285.08:14:00.14#ibcon#wrote, iclass 31, count 2 2006.285.08:14:00.14#ibcon#about to read 3, iclass 31, count 2 2006.285.08:14:00.16#ibcon#read 3, iclass 31, count 2 2006.285.08:14:00.16#ibcon#about to read 4, iclass 31, count 2 2006.285.08:14:00.16#ibcon#read 4, iclass 31, count 2 2006.285.08:14:00.16#ibcon#about to read 5, iclass 31, count 2 2006.285.08:14:00.16#ibcon#read 5, iclass 31, count 2 2006.285.08:14:00.16#ibcon#about to read 6, iclass 31, count 2 2006.285.08:14:00.16#ibcon#read 6, iclass 31, count 2 2006.285.08:14:00.16#ibcon#end of sib2, iclass 31, count 2 2006.285.08:14:00.16#ibcon#*mode == 0, iclass 31, count 2 2006.285.08:14:00.16#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.08:14:00.16#ibcon#[25=AT06-04\r\n] 2006.285.08:14:00.16#ibcon#*before write, iclass 31, count 2 2006.285.08:14:00.16#ibcon#enter sib2, iclass 31, count 2 2006.285.08:14:00.16#ibcon#flushed, iclass 31, count 2 2006.285.08:14:00.16#ibcon#about to write, iclass 31, count 2 2006.285.08:14:00.16#ibcon#wrote, iclass 31, count 2 2006.285.08:14:00.16#ibcon#about to read 3, iclass 31, count 2 2006.285.08:14:00.19#ibcon#read 3, iclass 31, count 2 2006.285.08:14:00.19#ibcon#about to read 4, iclass 31, count 2 2006.285.08:14:00.19#ibcon#read 4, iclass 31, count 2 2006.285.08:14:00.19#ibcon#about to read 5, iclass 31, count 2 2006.285.08:14:00.19#ibcon#read 5, iclass 31, count 2 2006.285.08:14:00.19#ibcon#about to read 6, iclass 31, count 2 2006.285.08:14:00.19#ibcon#read 6, iclass 31, count 2 2006.285.08:14:00.19#ibcon#end of sib2, iclass 31, count 2 2006.285.08:14:00.19#ibcon#*after write, iclass 31, count 2 2006.285.08:14:00.19#ibcon#*before return 0, iclass 31, count 2 2006.285.08:14:00.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:14:00.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:14:00.19#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.08:14:00.19#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:00.19#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:14:00.31#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:14:00.31#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:14:00.31#ibcon#enter wrdev, iclass 31, count 0 2006.285.08:14:00.31#ibcon#first serial, iclass 31, count 0 2006.285.08:14:00.31#ibcon#enter sib2, iclass 31, count 0 2006.285.08:14:00.31#ibcon#flushed, iclass 31, count 0 2006.285.08:14:00.31#ibcon#about to write, iclass 31, count 0 2006.285.08:14:00.31#ibcon#wrote, iclass 31, count 0 2006.285.08:14:00.31#ibcon#about to read 3, iclass 31, count 0 2006.285.08:14:00.33#ibcon#read 3, iclass 31, count 0 2006.285.08:14:00.33#ibcon#about to read 4, iclass 31, count 0 2006.285.08:14:00.33#ibcon#read 4, iclass 31, count 0 2006.285.08:14:00.33#ibcon#about to read 5, iclass 31, count 0 2006.285.08:14:00.33#ibcon#read 5, iclass 31, count 0 2006.285.08:14:00.33#ibcon#about to read 6, iclass 31, count 0 2006.285.08:14:00.33#ibcon#read 6, iclass 31, count 0 2006.285.08:14:00.33#ibcon#end of sib2, iclass 31, count 0 2006.285.08:14:00.33#ibcon#*mode == 0, iclass 31, count 0 2006.285.08:14:00.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.08:14:00.33#ibcon#[25=USB\r\n] 2006.285.08:14:00.33#ibcon#*before write, iclass 31, count 0 2006.285.08:14:00.33#ibcon#enter sib2, iclass 31, count 0 2006.285.08:14:00.33#ibcon#flushed, iclass 31, count 0 2006.285.08:14:00.33#ibcon#about to write, iclass 31, count 0 2006.285.08:14:00.33#ibcon#wrote, iclass 31, count 0 2006.285.08:14:00.33#ibcon#about to read 3, iclass 31, count 0 2006.285.08:14:00.36#ibcon#read 3, iclass 31, count 0 2006.285.08:14:00.36#ibcon#about to read 4, iclass 31, count 0 2006.285.08:14:00.36#ibcon#read 4, iclass 31, count 0 2006.285.08:14:00.36#ibcon#about to read 5, iclass 31, count 0 2006.285.08:14:00.36#ibcon#read 5, iclass 31, count 0 2006.285.08:14:00.36#ibcon#about to read 6, iclass 31, count 0 2006.285.08:14:00.36#ibcon#read 6, iclass 31, count 0 2006.285.08:14:00.36#ibcon#end of sib2, iclass 31, count 0 2006.285.08:14:00.36#ibcon#*after write, iclass 31, count 0 2006.285.08:14:00.36#ibcon#*before return 0, iclass 31, count 0 2006.285.08:14:00.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:14:00.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:14:00.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.08:14:00.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.08:14:00.36$vck44/valo=7,864.99 2006.285.08:14:00.37#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.08:14:00.37#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.08:14:00.37#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:00.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:14:00.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:14:00.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:14:00.37#ibcon#enter wrdev, iclass 33, count 0 2006.285.08:14:00.37#ibcon#first serial, iclass 33, count 0 2006.285.08:14:00.37#ibcon#enter sib2, iclass 33, count 0 2006.285.08:14:00.37#ibcon#flushed, iclass 33, count 0 2006.285.08:14:00.37#ibcon#about to write, iclass 33, count 0 2006.285.08:14:00.37#ibcon#wrote, iclass 33, count 0 2006.285.08:14:00.37#ibcon#about to read 3, iclass 33, count 0 2006.285.08:14:00.38#ibcon#read 3, iclass 33, count 0 2006.285.08:14:00.38#ibcon#about to read 4, iclass 33, count 0 2006.285.08:14:00.38#ibcon#read 4, iclass 33, count 0 2006.285.08:14:00.38#ibcon#about to read 5, iclass 33, count 0 2006.285.08:14:00.38#ibcon#read 5, iclass 33, count 0 2006.285.08:14:00.38#ibcon#about to read 6, iclass 33, count 0 2006.285.08:14:00.38#ibcon#read 6, iclass 33, count 0 2006.285.08:14:00.38#ibcon#end of sib2, iclass 33, count 0 2006.285.08:14:00.38#ibcon#*mode == 0, iclass 33, count 0 2006.285.08:14:00.38#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.08:14:00.38#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:14:00.38#ibcon#*before write, iclass 33, count 0 2006.285.08:14:00.38#ibcon#enter sib2, iclass 33, count 0 2006.285.08:14:00.38#ibcon#flushed, iclass 33, count 0 2006.285.08:14:00.38#ibcon#about to write, iclass 33, count 0 2006.285.08:14:00.38#ibcon#wrote, iclass 33, count 0 2006.285.08:14:00.38#ibcon#about to read 3, iclass 33, count 0 2006.285.08:14:00.42#ibcon#read 3, iclass 33, count 0 2006.285.08:14:00.42#ibcon#about to read 4, iclass 33, count 0 2006.285.08:14:00.42#ibcon#read 4, iclass 33, count 0 2006.285.08:14:00.42#ibcon#about to read 5, iclass 33, count 0 2006.285.08:14:00.42#ibcon#read 5, iclass 33, count 0 2006.285.08:14:00.42#ibcon#about to read 6, iclass 33, count 0 2006.285.08:14:00.42#ibcon#read 6, iclass 33, count 0 2006.285.08:14:00.42#ibcon#end of sib2, iclass 33, count 0 2006.285.08:14:00.42#ibcon#*after write, iclass 33, count 0 2006.285.08:14:00.42#ibcon#*before return 0, iclass 33, count 0 2006.285.08:14:00.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:14:00.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:14:00.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.08:14:00.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.08:14:00.43$vck44/va=7,4 2006.285.08:14:00.43#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.08:14:00.43#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.08:14:00.43#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:00.43#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:14:00.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:14:00.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:14:00.47#ibcon#enter wrdev, iclass 35, count 2 2006.285.08:14:00.47#ibcon#first serial, iclass 35, count 2 2006.285.08:14:00.47#ibcon#enter sib2, iclass 35, count 2 2006.285.08:14:00.47#ibcon#flushed, iclass 35, count 2 2006.285.08:14:00.47#ibcon#about to write, iclass 35, count 2 2006.285.08:14:00.47#ibcon#wrote, iclass 35, count 2 2006.285.08:14:00.47#ibcon#about to read 3, iclass 35, count 2 2006.285.08:14:00.49#ibcon#read 3, iclass 35, count 2 2006.285.08:14:00.49#ibcon#about to read 4, iclass 35, count 2 2006.285.08:14:00.49#ibcon#read 4, iclass 35, count 2 2006.285.08:14:00.49#ibcon#about to read 5, iclass 35, count 2 2006.285.08:14:00.49#ibcon#read 5, iclass 35, count 2 2006.285.08:14:00.49#ibcon#about to read 6, iclass 35, count 2 2006.285.08:14:00.49#ibcon#read 6, iclass 35, count 2 2006.285.08:14:00.49#ibcon#end of sib2, iclass 35, count 2 2006.285.08:14:00.49#ibcon#*mode == 0, iclass 35, count 2 2006.285.08:14:00.49#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.08:14:00.49#ibcon#[25=AT07-04\r\n] 2006.285.08:14:00.49#ibcon#*before write, iclass 35, count 2 2006.285.08:14:00.49#ibcon#enter sib2, iclass 35, count 2 2006.285.08:14:00.49#ibcon#flushed, iclass 35, count 2 2006.285.08:14:00.49#ibcon#about to write, iclass 35, count 2 2006.285.08:14:00.49#ibcon#wrote, iclass 35, count 2 2006.285.08:14:00.49#ibcon#about to read 3, iclass 35, count 2 2006.285.08:14:00.52#ibcon#read 3, iclass 35, count 2 2006.285.08:14:00.52#ibcon#about to read 4, iclass 35, count 2 2006.285.08:14:00.52#ibcon#read 4, iclass 35, count 2 2006.285.08:14:00.52#ibcon#about to read 5, iclass 35, count 2 2006.285.08:14:00.52#ibcon#read 5, iclass 35, count 2 2006.285.08:14:00.52#ibcon#about to read 6, iclass 35, count 2 2006.285.08:14:00.52#ibcon#read 6, iclass 35, count 2 2006.285.08:14:00.52#ibcon#end of sib2, iclass 35, count 2 2006.285.08:14:00.52#ibcon#*after write, iclass 35, count 2 2006.285.08:14:00.52#ibcon#*before return 0, iclass 35, count 2 2006.285.08:14:00.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:14:00.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:14:00.52#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.08:14:00.52#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:00.52#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:14:00.64#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:14:00.64#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:14:00.64#ibcon#enter wrdev, iclass 35, count 0 2006.285.08:14:00.64#ibcon#first serial, iclass 35, count 0 2006.285.08:14:00.64#ibcon#enter sib2, iclass 35, count 0 2006.285.08:14:00.64#ibcon#flushed, iclass 35, count 0 2006.285.08:14:00.64#ibcon#about to write, iclass 35, count 0 2006.285.08:14:00.64#ibcon#wrote, iclass 35, count 0 2006.285.08:14:00.64#ibcon#about to read 3, iclass 35, count 0 2006.285.08:14:00.66#ibcon#read 3, iclass 35, count 0 2006.285.08:14:00.66#ibcon#about to read 4, iclass 35, count 0 2006.285.08:14:00.66#ibcon#read 4, iclass 35, count 0 2006.285.08:14:00.66#ibcon#about to read 5, iclass 35, count 0 2006.285.08:14:00.66#ibcon#read 5, iclass 35, count 0 2006.285.08:14:00.66#ibcon#about to read 6, iclass 35, count 0 2006.285.08:14:00.66#ibcon#read 6, iclass 35, count 0 2006.285.08:14:00.66#ibcon#end of sib2, iclass 35, count 0 2006.285.08:14:00.66#ibcon#*mode == 0, iclass 35, count 0 2006.285.08:14:00.66#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.08:14:00.66#ibcon#[25=USB\r\n] 2006.285.08:14:00.66#ibcon#*before write, iclass 35, count 0 2006.285.08:14:00.66#ibcon#enter sib2, iclass 35, count 0 2006.285.08:14:00.66#ibcon#flushed, iclass 35, count 0 2006.285.08:14:00.66#ibcon#about to write, iclass 35, count 0 2006.285.08:14:00.66#ibcon#wrote, iclass 35, count 0 2006.285.08:14:00.66#ibcon#about to read 3, iclass 35, count 0 2006.285.08:14:00.69#ibcon#read 3, iclass 35, count 0 2006.285.08:14:00.69#ibcon#about to read 4, iclass 35, count 0 2006.285.08:14:00.69#ibcon#read 4, iclass 35, count 0 2006.285.08:14:00.69#ibcon#about to read 5, iclass 35, count 0 2006.285.08:14:00.69#ibcon#read 5, iclass 35, count 0 2006.285.08:14:00.69#ibcon#about to read 6, iclass 35, count 0 2006.285.08:14:00.69#ibcon#read 6, iclass 35, count 0 2006.285.08:14:00.69#ibcon#end of sib2, iclass 35, count 0 2006.285.08:14:00.69#ibcon#*after write, iclass 35, count 0 2006.285.08:14:00.69#ibcon#*before return 0, iclass 35, count 0 2006.285.08:14:00.69#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:14:00.69#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:14:00.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.08:14:00.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.08:14:00.70$vck44/valo=8,884.99 2006.285.08:14:00.70#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.08:14:00.70#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.08:14:00.70#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:00.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:14:00.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:14:00.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:14:00.70#ibcon#enter wrdev, iclass 37, count 0 2006.285.08:14:00.70#ibcon#first serial, iclass 37, count 0 2006.285.08:14:00.70#ibcon#enter sib2, iclass 37, count 0 2006.285.08:14:00.70#ibcon#flushed, iclass 37, count 0 2006.285.08:14:00.70#ibcon#about to write, iclass 37, count 0 2006.285.08:14:00.70#ibcon#wrote, iclass 37, count 0 2006.285.08:14:00.70#ibcon#about to read 3, iclass 37, count 0 2006.285.08:14:00.71#ibcon#read 3, iclass 37, count 0 2006.285.08:14:00.71#ibcon#about to read 4, iclass 37, count 0 2006.285.08:14:00.71#ibcon#read 4, iclass 37, count 0 2006.285.08:14:00.71#ibcon#about to read 5, iclass 37, count 0 2006.285.08:14:00.71#ibcon#read 5, iclass 37, count 0 2006.285.08:14:00.71#ibcon#about to read 6, iclass 37, count 0 2006.285.08:14:00.71#ibcon#read 6, iclass 37, count 0 2006.285.08:14:00.71#ibcon#end of sib2, iclass 37, count 0 2006.285.08:14:00.71#ibcon#*mode == 0, iclass 37, count 0 2006.285.08:14:00.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.08:14:00.71#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:14:00.71#ibcon#*before write, iclass 37, count 0 2006.285.08:14:00.71#ibcon#enter sib2, iclass 37, count 0 2006.285.08:14:00.71#ibcon#flushed, iclass 37, count 0 2006.285.08:14:00.71#ibcon#about to write, iclass 37, count 0 2006.285.08:14:00.71#ibcon#wrote, iclass 37, count 0 2006.285.08:14:00.71#ibcon#about to read 3, iclass 37, count 0 2006.285.08:14:00.75#ibcon#read 3, iclass 37, count 0 2006.285.08:14:00.75#ibcon#about to read 4, iclass 37, count 0 2006.285.08:14:00.75#ibcon#read 4, iclass 37, count 0 2006.285.08:14:00.75#ibcon#about to read 5, iclass 37, count 0 2006.285.08:14:00.75#ibcon#read 5, iclass 37, count 0 2006.285.08:14:00.75#ibcon#about to read 6, iclass 37, count 0 2006.285.08:14:00.75#ibcon#read 6, iclass 37, count 0 2006.285.08:14:00.75#ibcon#end of sib2, iclass 37, count 0 2006.285.08:14:00.75#ibcon#*after write, iclass 37, count 0 2006.285.08:14:00.75#ibcon#*before return 0, iclass 37, count 0 2006.285.08:14:00.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:14:00.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:14:00.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.08:14:00.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.08:14:00.76$vck44/va=8,3 2006.285.08:14:00.76#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.08:14:00.76#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.08:14:00.76#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:00.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:14:00.80#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:14:00.80#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:14:00.80#ibcon#enter wrdev, iclass 39, count 2 2006.285.08:14:00.80#ibcon#first serial, iclass 39, count 2 2006.285.08:14:00.80#ibcon#enter sib2, iclass 39, count 2 2006.285.08:14:00.80#ibcon#flushed, iclass 39, count 2 2006.285.08:14:00.80#ibcon#about to write, iclass 39, count 2 2006.285.08:14:00.80#ibcon#wrote, iclass 39, count 2 2006.285.08:14:00.80#ibcon#about to read 3, iclass 39, count 2 2006.285.08:14:00.82#ibcon#read 3, iclass 39, count 2 2006.285.08:14:00.82#ibcon#about to read 4, iclass 39, count 2 2006.285.08:14:00.82#ibcon#read 4, iclass 39, count 2 2006.285.08:14:00.82#ibcon#about to read 5, iclass 39, count 2 2006.285.08:14:00.82#ibcon#read 5, iclass 39, count 2 2006.285.08:14:00.82#ibcon#about to read 6, iclass 39, count 2 2006.285.08:14:00.82#ibcon#read 6, iclass 39, count 2 2006.285.08:14:00.82#ibcon#end of sib2, iclass 39, count 2 2006.285.08:14:00.82#ibcon#*mode == 0, iclass 39, count 2 2006.285.08:14:00.82#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.08:14:00.82#ibcon#[25=AT08-03\r\n] 2006.285.08:14:00.82#ibcon#*before write, iclass 39, count 2 2006.285.08:14:00.82#ibcon#enter sib2, iclass 39, count 2 2006.285.08:14:00.82#ibcon#flushed, iclass 39, count 2 2006.285.08:14:00.82#ibcon#about to write, iclass 39, count 2 2006.285.08:14:00.82#ibcon#wrote, iclass 39, count 2 2006.285.08:14:00.82#ibcon#about to read 3, iclass 39, count 2 2006.285.08:14:00.85#ibcon#read 3, iclass 39, count 2 2006.285.08:14:00.85#ibcon#about to read 4, iclass 39, count 2 2006.285.08:14:00.85#ibcon#read 4, iclass 39, count 2 2006.285.08:14:00.85#ibcon#about to read 5, iclass 39, count 2 2006.285.08:14:00.85#ibcon#read 5, iclass 39, count 2 2006.285.08:14:00.85#ibcon#about to read 6, iclass 39, count 2 2006.285.08:14:00.85#ibcon#read 6, iclass 39, count 2 2006.285.08:14:00.85#ibcon#end of sib2, iclass 39, count 2 2006.285.08:14:00.85#ibcon#*after write, iclass 39, count 2 2006.285.08:14:00.85#ibcon#*before return 0, iclass 39, count 2 2006.285.08:14:00.85#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:14:00.85#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:14:00.85#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.08:14:00.85#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:00.85#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:14:00.97#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:14:00.97#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:14:00.97#ibcon#enter wrdev, iclass 39, count 0 2006.285.08:14:00.97#ibcon#first serial, iclass 39, count 0 2006.285.08:14:00.97#ibcon#enter sib2, iclass 39, count 0 2006.285.08:14:00.97#ibcon#flushed, iclass 39, count 0 2006.285.08:14:00.97#ibcon#about to write, iclass 39, count 0 2006.285.08:14:00.97#ibcon#wrote, iclass 39, count 0 2006.285.08:14:00.97#ibcon#about to read 3, iclass 39, count 0 2006.285.08:14:00.99#ibcon#read 3, iclass 39, count 0 2006.285.08:14:00.99#ibcon#about to read 4, iclass 39, count 0 2006.285.08:14:00.99#ibcon#read 4, iclass 39, count 0 2006.285.08:14:00.99#ibcon#about to read 5, iclass 39, count 0 2006.285.08:14:00.99#ibcon#read 5, iclass 39, count 0 2006.285.08:14:00.99#ibcon#about to read 6, iclass 39, count 0 2006.285.08:14:00.99#ibcon#read 6, iclass 39, count 0 2006.285.08:14:00.99#ibcon#end of sib2, iclass 39, count 0 2006.285.08:14:00.99#ibcon#*mode == 0, iclass 39, count 0 2006.285.08:14:00.99#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.08:14:00.99#ibcon#[25=USB\r\n] 2006.285.08:14:00.99#ibcon#*before write, iclass 39, count 0 2006.285.08:14:00.99#ibcon#enter sib2, iclass 39, count 0 2006.285.08:14:00.99#ibcon#flushed, iclass 39, count 0 2006.285.08:14:00.99#ibcon#about to write, iclass 39, count 0 2006.285.08:14:00.99#ibcon#wrote, iclass 39, count 0 2006.285.08:14:00.99#ibcon#about to read 3, iclass 39, count 0 2006.285.08:14:01.02#ibcon#read 3, iclass 39, count 0 2006.285.08:14:01.02#ibcon#about to read 4, iclass 39, count 0 2006.285.08:14:01.02#ibcon#read 4, iclass 39, count 0 2006.285.08:14:01.02#ibcon#about to read 5, iclass 39, count 0 2006.285.08:14:01.02#ibcon#read 5, iclass 39, count 0 2006.285.08:14:01.02#ibcon#about to read 6, iclass 39, count 0 2006.285.08:14:01.02#ibcon#read 6, iclass 39, count 0 2006.285.08:14:01.02#ibcon#end of sib2, iclass 39, count 0 2006.285.08:14:01.02#ibcon#*after write, iclass 39, count 0 2006.285.08:14:01.02#ibcon#*before return 0, iclass 39, count 0 2006.285.08:14:01.02#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:14:01.02#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:14:01.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.08:14:01.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.08:14:01.03$vck44/vblo=1,629.99 2006.285.08:14:01.03#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.08:14:01.03#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.08:14:01.03#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:01.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:14:01.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:14:01.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:14:01.03#ibcon#enter wrdev, iclass 3, count 0 2006.285.08:14:01.03#ibcon#first serial, iclass 3, count 0 2006.285.08:14:01.03#ibcon#enter sib2, iclass 3, count 0 2006.285.08:14:01.03#ibcon#flushed, iclass 3, count 0 2006.285.08:14:01.03#ibcon#about to write, iclass 3, count 0 2006.285.08:14:01.03#ibcon#wrote, iclass 3, count 0 2006.285.08:14:01.03#ibcon#about to read 3, iclass 3, count 0 2006.285.08:14:01.04#ibcon#read 3, iclass 3, count 0 2006.285.08:14:01.04#ibcon#about to read 4, iclass 3, count 0 2006.285.08:14:01.04#ibcon#read 4, iclass 3, count 0 2006.285.08:14:01.04#ibcon#about to read 5, iclass 3, count 0 2006.285.08:14:01.04#ibcon#read 5, iclass 3, count 0 2006.285.08:14:01.04#ibcon#about to read 6, iclass 3, count 0 2006.285.08:14:01.04#ibcon#read 6, iclass 3, count 0 2006.285.08:14:01.04#ibcon#end of sib2, iclass 3, count 0 2006.285.08:14:01.04#ibcon#*mode == 0, iclass 3, count 0 2006.285.08:14:01.04#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.08:14:01.04#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:14:01.04#ibcon#*before write, iclass 3, count 0 2006.285.08:14:01.04#ibcon#enter sib2, iclass 3, count 0 2006.285.08:14:01.04#ibcon#flushed, iclass 3, count 0 2006.285.08:14:01.04#ibcon#about to write, iclass 3, count 0 2006.285.08:14:01.04#ibcon#wrote, iclass 3, count 0 2006.285.08:14:01.04#ibcon#about to read 3, iclass 3, count 0 2006.285.08:14:01.08#ibcon#read 3, iclass 3, count 0 2006.285.08:14:01.08#ibcon#about to read 4, iclass 3, count 0 2006.285.08:14:01.08#ibcon#read 4, iclass 3, count 0 2006.285.08:14:01.08#ibcon#about to read 5, iclass 3, count 0 2006.285.08:14:01.08#ibcon#read 5, iclass 3, count 0 2006.285.08:14:01.08#ibcon#about to read 6, iclass 3, count 0 2006.285.08:14:01.08#ibcon#read 6, iclass 3, count 0 2006.285.08:14:01.08#ibcon#end of sib2, iclass 3, count 0 2006.285.08:14:01.08#ibcon#*after write, iclass 3, count 0 2006.285.08:14:01.08#ibcon#*before return 0, iclass 3, count 0 2006.285.08:14:01.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:14:01.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:14:01.08#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.08:14:01.08#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.08:14:01.09$vck44/vb=1,4 2006.285.08:14:01.09#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.08:14:01.09#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.08:14:01.09#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:01.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:14:01.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:14:01.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:14:01.09#ibcon#enter wrdev, iclass 5, count 2 2006.285.08:14:01.09#ibcon#first serial, iclass 5, count 2 2006.285.08:14:01.09#ibcon#enter sib2, iclass 5, count 2 2006.285.08:14:01.09#ibcon#flushed, iclass 5, count 2 2006.285.08:14:01.09#ibcon#about to write, iclass 5, count 2 2006.285.08:14:01.09#ibcon#wrote, iclass 5, count 2 2006.285.08:14:01.09#ibcon#about to read 3, iclass 5, count 2 2006.285.08:14:01.10#ibcon#read 3, iclass 5, count 2 2006.285.08:14:01.10#ibcon#about to read 4, iclass 5, count 2 2006.285.08:14:01.10#ibcon#read 4, iclass 5, count 2 2006.285.08:14:01.10#ibcon#about to read 5, iclass 5, count 2 2006.285.08:14:01.10#ibcon#read 5, iclass 5, count 2 2006.285.08:14:01.10#ibcon#about to read 6, iclass 5, count 2 2006.285.08:14:01.10#ibcon#read 6, iclass 5, count 2 2006.285.08:14:01.10#ibcon#end of sib2, iclass 5, count 2 2006.285.08:14:01.10#ibcon#*mode == 0, iclass 5, count 2 2006.285.08:14:01.10#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.08:14:01.10#ibcon#[27=AT01-04\r\n] 2006.285.08:14:01.10#ibcon#*before write, iclass 5, count 2 2006.285.08:14:01.10#ibcon#enter sib2, iclass 5, count 2 2006.285.08:14:01.10#ibcon#flushed, iclass 5, count 2 2006.285.08:14:01.10#ibcon#about to write, iclass 5, count 2 2006.285.08:14:01.10#ibcon#wrote, iclass 5, count 2 2006.285.08:14:01.10#ibcon#about to read 3, iclass 5, count 2 2006.285.08:14:01.13#ibcon#read 3, iclass 5, count 2 2006.285.08:14:01.13#ibcon#about to read 4, iclass 5, count 2 2006.285.08:14:01.13#ibcon#read 4, iclass 5, count 2 2006.285.08:14:01.13#ibcon#about to read 5, iclass 5, count 2 2006.285.08:14:01.13#ibcon#read 5, iclass 5, count 2 2006.285.08:14:01.13#ibcon#about to read 6, iclass 5, count 2 2006.285.08:14:01.13#ibcon#read 6, iclass 5, count 2 2006.285.08:14:01.13#ibcon#end of sib2, iclass 5, count 2 2006.285.08:14:01.13#ibcon#*after write, iclass 5, count 2 2006.285.08:14:01.13#ibcon#*before return 0, iclass 5, count 2 2006.285.08:14:01.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:14:01.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:14:01.13#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.08:14:01.13#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:01.13#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:14:01.25#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:14:01.25#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:14:01.25#ibcon#enter wrdev, iclass 5, count 0 2006.285.08:14:01.25#ibcon#first serial, iclass 5, count 0 2006.285.08:14:01.25#ibcon#enter sib2, iclass 5, count 0 2006.285.08:14:01.25#ibcon#flushed, iclass 5, count 0 2006.285.08:14:01.25#ibcon#about to write, iclass 5, count 0 2006.285.08:14:01.25#ibcon#wrote, iclass 5, count 0 2006.285.08:14:01.25#ibcon#about to read 3, iclass 5, count 0 2006.285.08:14:01.27#ibcon#read 3, iclass 5, count 0 2006.285.08:14:01.27#ibcon#about to read 4, iclass 5, count 0 2006.285.08:14:01.27#ibcon#read 4, iclass 5, count 0 2006.285.08:14:01.27#ibcon#about to read 5, iclass 5, count 0 2006.285.08:14:01.27#ibcon#read 5, iclass 5, count 0 2006.285.08:14:01.27#ibcon#about to read 6, iclass 5, count 0 2006.285.08:14:01.27#ibcon#read 6, iclass 5, count 0 2006.285.08:14:01.27#ibcon#end of sib2, iclass 5, count 0 2006.285.08:14:01.27#ibcon#*mode == 0, iclass 5, count 0 2006.285.08:14:01.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.08:14:01.27#ibcon#[27=USB\r\n] 2006.285.08:14:01.27#ibcon#*before write, iclass 5, count 0 2006.285.08:14:01.27#ibcon#enter sib2, iclass 5, count 0 2006.285.08:14:01.27#ibcon#flushed, iclass 5, count 0 2006.285.08:14:01.27#ibcon#about to write, iclass 5, count 0 2006.285.08:14:01.27#ibcon#wrote, iclass 5, count 0 2006.285.08:14:01.27#ibcon#about to read 3, iclass 5, count 0 2006.285.08:14:01.30#ibcon#read 3, iclass 5, count 0 2006.285.08:14:01.30#ibcon#about to read 4, iclass 5, count 0 2006.285.08:14:01.30#ibcon#read 4, iclass 5, count 0 2006.285.08:14:01.30#ibcon#about to read 5, iclass 5, count 0 2006.285.08:14:01.30#ibcon#read 5, iclass 5, count 0 2006.285.08:14:01.30#ibcon#about to read 6, iclass 5, count 0 2006.285.08:14:01.30#ibcon#read 6, iclass 5, count 0 2006.285.08:14:01.30#ibcon#end of sib2, iclass 5, count 0 2006.285.08:14:01.30#ibcon#*after write, iclass 5, count 0 2006.285.08:14:01.30#ibcon#*before return 0, iclass 5, count 0 2006.285.08:14:01.30#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:14:01.30#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:14:01.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.08:14:01.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.08:14:01.30$vck44/vblo=2,634.99 2006.285.08:14:01.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.08:14:01.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.08:14:01.31#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:01.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:14:01.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:14:01.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:14:01.31#ibcon#enter wrdev, iclass 7, count 0 2006.285.08:14:01.31#ibcon#first serial, iclass 7, count 0 2006.285.08:14:01.31#ibcon#enter sib2, iclass 7, count 0 2006.285.08:14:01.31#ibcon#flushed, iclass 7, count 0 2006.285.08:14:01.31#ibcon#about to write, iclass 7, count 0 2006.285.08:14:01.31#ibcon#wrote, iclass 7, count 0 2006.285.08:14:01.31#ibcon#about to read 3, iclass 7, count 0 2006.285.08:14:01.32#ibcon#read 3, iclass 7, count 0 2006.285.08:14:01.32#ibcon#about to read 4, iclass 7, count 0 2006.285.08:14:01.32#ibcon#read 4, iclass 7, count 0 2006.285.08:14:01.32#ibcon#about to read 5, iclass 7, count 0 2006.285.08:14:01.32#ibcon#read 5, iclass 7, count 0 2006.285.08:14:01.32#ibcon#about to read 6, iclass 7, count 0 2006.285.08:14:01.32#ibcon#read 6, iclass 7, count 0 2006.285.08:14:01.32#ibcon#end of sib2, iclass 7, count 0 2006.285.08:14:01.32#ibcon#*mode == 0, iclass 7, count 0 2006.285.08:14:01.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.08:14:01.32#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:14:01.32#ibcon#*before write, iclass 7, count 0 2006.285.08:14:01.32#ibcon#enter sib2, iclass 7, count 0 2006.285.08:14:01.32#ibcon#flushed, iclass 7, count 0 2006.285.08:14:01.32#ibcon#about to write, iclass 7, count 0 2006.285.08:14:01.32#ibcon#wrote, iclass 7, count 0 2006.285.08:14:01.32#ibcon#about to read 3, iclass 7, count 0 2006.285.08:14:01.36#ibcon#read 3, iclass 7, count 0 2006.285.08:14:01.36#ibcon#about to read 4, iclass 7, count 0 2006.285.08:14:01.36#ibcon#read 4, iclass 7, count 0 2006.285.08:14:01.36#ibcon#about to read 5, iclass 7, count 0 2006.285.08:14:01.36#ibcon#read 5, iclass 7, count 0 2006.285.08:14:01.36#ibcon#about to read 6, iclass 7, count 0 2006.285.08:14:01.36#ibcon#read 6, iclass 7, count 0 2006.285.08:14:01.36#ibcon#end of sib2, iclass 7, count 0 2006.285.08:14:01.36#ibcon#*after write, iclass 7, count 0 2006.285.08:14:01.36#ibcon#*before return 0, iclass 7, count 0 2006.285.08:14:01.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:14:01.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:14:01.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.08:14:01.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.08:14:01.37$vck44/vb=2,5 2006.285.08:14:01.37#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.08:14:01.37#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.08:14:01.37#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:01.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:14:01.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:14:01.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:14:01.41#ibcon#enter wrdev, iclass 11, count 2 2006.285.08:14:01.41#ibcon#first serial, iclass 11, count 2 2006.285.08:14:01.41#ibcon#enter sib2, iclass 11, count 2 2006.285.08:14:01.41#ibcon#flushed, iclass 11, count 2 2006.285.08:14:01.41#ibcon#about to write, iclass 11, count 2 2006.285.08:14:01.41#ibcon#wrote, iclass 11, count 2 2006.285.08:14:01.41#ibcon#about to read 3, iclass 11, count 2 2006.285.08:14:01.43#ibcon#read 3, iclass 11, count 2 2006.285.08:14:01.43#ibcon#about to read 4, iclass 11, count 2 2006.285.08:14:01.43#ibcon#read 4, iclass 11, count 2 2006.285.08:14:01.43#ibcon#about to read 5, iclass 11, count 2 2006.285.08:14:01.43#ibcon#read 5, iclass 11, count 2 2006.285.08:14:01.43#ibcon#about to read 6, iclass 11, count 2 2006.285.08:14:01.43#ibcon#read 6, iclass 11, count 2 2006.285.08:14:01.43#ibcon#end of sib2, iclass 11, count 2 2006.285.08:14:01.43#ibcon#*mode == 0, iclass 11, count 2 2006.285.08:14:01.43#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.08:14:01.43#ibcon#[27=AT02-05\r\n] 2006.285.08:14:01.43#ibcon#*before write, iclass 11, count 2 2006.285.08:14:01.43#ibcon#enter sib2, iclass 11, count 2 2006.285.08:14:01.43#ibcon#flushed, iclass 11, count 2 2006.285.08:14:01.43#ibcon#about to write, iclass 11, count 2 2006.285.08:14:01.43#ibcon#wrote, iclass 11, count 2 2006.285.08:14:01.43#ibcon#about to read 3, iclass 11, count 2 2006.285.08:14:01.46#ibcon#read 3, iclass 11, count 2 2006.285.08:14:01.46#ibcon#about to read 4, iclass 11, count 2 2006.285.08:14:01.46#ibcon#read 4, iclass 11, count 2 2006.285.08:14:01.46#ibcon#about to read 5, iclass 11, count 2 2006.285.08:14:01.46#ibcon#read 5, iclass 11, count 2 2006.285.08:14:01.46#ibcon#about to read 6, iclass 11, count 2 2006.285.08:14:01.46#ibcon#read 6, iclass 11, count 2 2006.285.08:14:01.46#ibcon#end of sib2, iclass 11, count 2 2006.285.08:14:01.46#ibcon#*after write, iclass 11, count 2 2006.285.08:14:01.46#ibcon#*before return 0, iclass 11, count 2 2006.285.08:14:01.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:14:01.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:14:01.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.08:14:01.46#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:01.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:14:01.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:14:01.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:14:01.58#ibcon#enter wrdev, iclass 11, count 0 2006.285.08:14:01.58#ibcon#first serial, iclass 11, count 0 2006.285.08:14:01.58#ibcon#enter sib2, iclass 11, count 0 2006.285.08:14:01.58#ibcon#flushed, iclass 11, count 0 2006.285.08:14:01.58#ibcon#about to write, iclass 11, count 0 2006.285.08:14:01.58#ibcon#wrote, iclass 11, count 0 2006.285.08:14:01.58#ibcon#about to read 3, iclass 11, count 0 2006.285.08:14:01.60#ibcon#read 3, iclass 11, count 0 2006.285.08:14:01.60#ibcon#about to read 4, iclass 11, count 0 2006.285.08:14:01.60#ibcon#read 4, iclass 11, count 0 2006.285.08:14:01.60#ibcon#about to read 5, iclass 11, count 0 2006.285.08:14:01.60#ibcon#read 5, iclass 11, count 0 2006.285.08:14:01.60#ibcon#about to read 6, iclass 11, count 0 2006.285.08:14:01.60#ibcon#read 6, iclass 11, count 0 2006.285.08:14:01.60#ibcon#end of sib2, iclass 11, count 0 2006.285.08:14:01.60#ibcon#*mode == 0, iclass 11, count 0 2006.285.08:14:01.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.08:14:01.60#ibcon#[27=USB\r\n] 2006.285.08:14:01.60#ibcon#*before write, iclass 11, count 0 2006.285.08:14:01.60#ibcon#enter sib2, iclass 11, count 0 2006.285.08:14:01.60#ibcon#flushed, iclass 11, count 0 2006.285.08:14:01.60#ibcon#about to write, iclass 11, count 0 2006.285.08:14:01.60#ibcon#wrote, iclass 11, count 0 2006.285.08:14:01.60#ibcon#about to read 3, iclass 11, count 0 2006.285.08:14:01.63#ibcon#read 3, iclass 11, count 0 2006.285.08:14:01.63#ibcon#about to read 4, iclass 11, count 0 2006.285.08:14:01.63#ibcon#read 4, iclass 11, count 0 2006.285.08:14:01.63#ibcon#about to read 5, iclass 11, count 0 2006.285.08:14:01.63#ibcon#read 5, iclass 11, count 0 2006.285.08:14:01.63#ibcon#about to read 6, iclass 11, count 0 2006.285.08:14:01.63#ibcon#read 6, iclass 11, count 0 2006.285.08:14:01.63#ibcon#end of sib2, iclass 11, count 0 2006.285.08:14:01.63#ibcon#*after write, iclass 11, count 0 2006.285.08:14:01.63#ibcon#*before return 0, iclass 11, count 0 2006.285.08:14:01.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:14:01.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:14:01.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.08:14:01.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.08:14:01.63$vck44/vblo=3,649.99 2006.285.08:14:01.64#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.08:14:01.64#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.08:14:01.64#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:01.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:14:01.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:14:01.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:14:01.64#ibcon#enter wrdev, iclass 13, count 0 2006.285.08:14:01.64#ibcon#first serial, iclass 13, count 0 2006.285.08:14:01.64#ibcon#enter sib2, iclass 13, count 0 2006.285.08:14:01.64#ibcon#flushed, iclass 13, count 0 2006.285.08:14:01.64#ibcon#about to write, iclass 13, count 0 2006.285.08:14:01.64#ibcon#wrote, iclass 13, count 0 2006.285.08:14:01.64#ibcon#about to read 3, iclass 13, count 0 2006.285.08:14:01.65#ibcon#read 3, iclass 13, count 0 2006.285.08:14:01.65#ibcon#about to read 4, iclass 13, count 0 2006.285.08:14:01.65#ibcon#read 4, iclass 13, count 0 2006.285.08:14:01.65#ibcon#about to read 5, iclass 13, count 0 2006.285.08:14:01.65#ibcon#read 5, iclass 13, count 0 2006.285.08:14:01.65#ibcon#about to read 6, iclass 13, count 0 2006.285.08:14:01.65#ibcon#read 6, iclass 13, count 0 2006.285.08:14:01.65#ibcon#end of sib2, iclass 13, count 0 2006.285.08:14:01.65#ibcon#*mode == 0, iclass 13, count 0 2006.285.08:14:01.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.08:14:01.65#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:14:01.65#ibcon#*before write, iclass 13, count 0 2006.285.08:14:01.65#ibcon#enter sib2, iclass 13, count 0 2006.285.08:14:01.65#ibcon#flushed, iclass 13, count 0 2006.285.08:14:01.65#ibcon#about to write, iclass 13, count 0 2006.285.08:14:01.65#ibcon#wrote, iclass 13, count 0 2006.285.08:14:01.65#ibcon#about to read 3, iclass 13, count 0 2006.285.08:14:01.69#ibcon#read 3, iclass 13, count 0 2006.285.08:14:01.69#ibcon#about to read 4, iclass 13, count 0 2006.285.08:14:01.69#ibcon#read 4, iclass 13, count 0 2006.285.08:14:01.69#ibcon#about to read 5, iclass 13, count 0 2006.285.08:14:01.69#ibcon#read 5, iclass 13, count 0 2006.285.08:14:01.69#ibcon#about to read 6, iclass 13, count 0 2006.285.08:14:01.69#ibcon#read 6, iclass 13, count 0 2006.285.08:14:01.69#ibcon#end of sib2, iclass 13, count 0 2006.285.08:14:01.69#ibcon#*after write, iclass 13, count 0 2006.285.08:14:01.69#ibcon#*before return 0, iclass 13, count 0 2006.285.08:14:01.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:14:01.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:14:01.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.08:14:01.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.08:14:01.70$vck44/vb=3,4 2006.285.08:14:01.70#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.08:14:01.70#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.08:14:01.70#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:01.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:14:01.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:14:01.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:14:01.74#ibcon#enter wrdev, iclass 15, count 2 2006.285.08:14:01.74#ibcon#first serial, iclass 15, count 2 2006.285.08:14:01.74#ibcon#enter sib2, iclass 15, count 2 2006.285.08:14:01.74#ibcon#flushed, iclass 15, count 2 2006.285.08:14:01.74#ibcon#about to write, iclass 15, count 2 2006.285.08:14:01.74#ibcon#wrote, iclass 15, count 2 2006.285.08:14:01.74#ibcon#about to read 3, iclass 15, count 2 2006.285.08:14:01.76#ibcon#read 3, iclass 15, count 2 2006.285.08:14:01.76#ibcon#about to read 4, iclass 15, count 2 2006.285.08:14:01.76#ibcon#read 4, iclass 15, count 2 2006.285.08:14:01.76#ibcon#about to read 5, iclass 15, count 2 2006.285.08:14:01.76#ibcon#read 5, iclass 15, count 2 2006.285.08:14:01.76#ibcon#about to read 6, iclass 15, count 2 2006.285.08:14:01.76#ibcon#read 6, iclass 15, count 2 2006.285.08:14:01.76#ibcon#end of sib2, iclass 15, count 2 2006.285.08:14:01.76#ibcon#*mode == 0, iclass 15, count 2 2006.285.08:14:01.76#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.08:14:01.76#ibcon#[27=AT03-04\r\n] 2006.285.08:14:01.76#ibcon#*before write, iclass 15, count 2 2006.285.08:14:01.76#ibcon#enter sib2, iclass 15, count 2 2006.285.08:14:01.76#ibcon#flushed, iclass 15, count 2 2006.285.08:14:01.76#ibcon#about to write, iclass 15, count 2 2006.285.08:14:01.76#ibcon#wrote, iclass 15, count 2 2006.285.08:14:01.76#ibcon#about to read 3, iclass 15, count 2 2006.285.08:14:01.79#ibcon#read 3, iclass 15, count 2 2006.285.08:14:01.79#ibcon#about to read 4, iclass 15, count 2 2006.285.08:14:01.79#ibcon#read 4, iclass 15, count 2 2006.285.08:14:01.79#ibcon#about to read 5, iclass 15, count 2 2006.285.08:14:01.79#ibcon#read 5, iclass 15, count 2 2006.285.08:14:01.79#ibcon#about to read 6, iclass 15, count 2 2006.285.08:14:01.79#ibcon#read 6, iclass 15, count 2 2006.285.08:14:01.79#ibcon#end of sib2, iclass 15, count 2 2006.285.08:14:01.79#ibcon#*after write, iclass 15, count 2 2006.285.08:14:01.79#ibcon#*before return 0, iclass 15, count 2 2006.285.08:14:01.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:14:01.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:14:01.79#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.08:14:01.79#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:01.79#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:14:01.91#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:14:01.91#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:14:01.91#ibcon#enter wrdev, iclass 15, count 0 2006.285.08:14:01.91#ibcon#first serial, iclass 15, count 0 2006.285.08:14:01.91#ibcon#enter sib2, iclass 15, count 0 2006.285.08:14:01.91#ibcon#flushed, iclass 15, count 0 2006.285.08:14:01.91#ibcon#about to write, iclass 15, count 0 2006.285.08:14:01.91#ibcon#wrote, iclass 15, count 0 2006.285.08:14:01.91#ibcon#about to read 3, iclass 15, count 0 2006.285.08:14:01.93#ibcon#read 3, iclass 15, count 0 2006.285.08:14:01.93#ibcon#about to read 4, iclass 15, count 0 2006.285.08:14:01.93#ibcon#read 4, iclass 15, count 0 2006.285.08:14:01.93#ibcon#about to read 5, iclass 15, count 0 2006.285.08:14:01.93#ibcon#read 5, iclass 15, count 0 2006.285.08:14:01.93#ibcon#about to read 6, iclass 15, count 0 2006.285.08:14:01.93#ibcon#read 6, iclass 15, count 0 2006.285.08:14:01.93#ibcon#end of sib2, iclass 15, count 0 2006.285.08:14:01.93#ibcon#*mode == 0, iclass 15, count 0 2006.285.08:14:01.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.08:14:01.93#ibcon#[27=USB\r\n] 2006.285.08:14:01.93#ibcon#*before write, iclass 15, count 0 2006.285.08:14:01.93#ibcon#enter sib2, iclass 15, count 0 2006.285.08:14:01.93#ibcon#flushed, iclass 15, count 0 2006.285.08:14:01.93#ibcon#about to write, iclass 15, count 0 2006.285.08:14:01.93#ibcon#wrote, iclass 15, count 0 2006.285.08:14:01.93#ibcon#about to read 3, iclass 15, count 0 2006.285.08:14:01.96#ibcon#read 3, iclass 15, count 0 2006.285.08:14:01.96#ibcon#about to read 4, iclass 15, count 0 2006.285.08:14:01.96#ibcon#read 4, iclass 15, count 0 2006.285.08:14:01.96#ibcon#about to read 5, iclass 15, count 0 2006.285.08:14:01.96#ibcon#read 5, iclass 15, count 0 2006.285.08:14:01.96#ibcon#about to read 6, iclass 15, count 0 2006.285.08:14:01.96#ibcon#read 6, iclass 15, count 0 2006.285.08:14:01.96#ibcon#end of sib2, iclass 15, count 0 2006.285.08:14:01.96#ibcon#*after write, iclass 15, count 0 2006.285.08:14:01.96#ibcon#*before return 0, iclass 15, count 0 2006.285.08:14:01.96#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:14:01.96#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:14:01.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.08:14:01.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.08:14:01.97$vck44/vblo=4,679.99 2006.285.08:14:01.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.08:14:01.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.08:14:01.97#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:01.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:14:01.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:14:01.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:14:01.97#ibcon#enter wrdev, iclass 17, count 0 2006.285.08:14:01.97#ibcon#first serial, iclass 17, count 0 2006.285.08:14:01.97#ibcon#enter sib2, iclass 17, count 0 2006.285.08:14:01.97#ibcon#flushed, iclass 17, count 0 2006.285.08:14:01.97#ibcon#about to write, iclass 17, count 0 2006.285.08:14:01.97#ibcon#wrote, iclass 17, count 0 2006.285.08:14:01.97#ibcon#about to read 3, iclass 17, count 0 2006.285.08:14:01.98#ibcon#read 3, iclass 17, count 0 2006.285.08:14:01.98#ibcon#about to read 4, iclass 17, count 0 2006.285.08:14:01.98#ibcon#read 4, iclass 17, count 0 2006.285.08:14:01.98#ibcon#about to read 5, iclass 17, count 0 2006.285.08:14:01.98#ibcon#read 5, iclass 17, count 0 2006.285.08:14:01.98#ibcon#about to read 6, iclass 17, count 0 2006.285.08:14:01.98#ibcon#read 6, iclass 17, count 0 2006.285.08:14:01.98#ibcon#end of sib2, iclass 17, count 0 2006.285.08:14:01.98#ibcon#*mode == 0, iclass 17, count 0 2006.285.08:14:01.98#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.08:14:01.98#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:14:01.98#ibcon#*before write, iclass 17, count 0 2006.285.08:14:01.98#ibcon#enter sib2, iclass 17, count 0 2006.285.08:14:01.98#ibcon#flushed, iclass 17, count 0 2006.285.08:14:01.98#ibcon#about to write, iclass 17, count 0 2006.285.08:14:01.98#ibcon#wrote, iclass 17, count 0 2006.285.08:14:01.98#ibcon#about to read 3, iclass 17, count 0 2006.285.08:14:02.02#ibcon#read 3, iclass 17, count 0 2006.285.08:14:02.02#ibcon#about to read 4, iclass 17, count 0 2006.285.08:14:02.02#ibcon#read 4, iclass 17, count 0 2006.285.08:14:02.02#ibcon#about to read 5, iclass 17, count 0 2006.285.08:14:02.02#ibcon#read 5, iclass 17, count 0 2006.285.08:14:02.02#ibcon#about to read 6, iclass 17, count 0 2006.285.08:14:02.02#ibcon#read 6, iclass 17, count 0 2006.285.08:14:02.02#ibcon#end of sib2, iclass 17, count 0 2006.285.08:14:02.02#ibcon#*after write, iclass 17, count 0 2006.285.08:14:02.02#ibcon#*before return 0, iclass 17, count 0 2006.285.08:14:02.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:14:02.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:14:02.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.08:14:02.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.08:14:02.02$vck44/vb=4,5 2006.285.08:14:02.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.08:14:02.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.08:14:02.03#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:02.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:14:02.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:14:02.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:14:02.07#ibcon#enter wrdev, iclass 19, count 2 2006.285.08:14:02.07#ibcon#first serial, iclass 19, count 2 2006.285.08:14:02.07#ibcon#enter sib2, iclass 19, count 2 2006.285.08:14:02.07#ibcon#flushed, iclass 19, count 2 2006.285.08:14:02.07#ibcon#about to write, iclass 19, count 2 2006.285.08:14:02.07#ibcon#wrote, iclass 19, count 2 2006.285.08:14:02.07#ibcon#about to read 3, iclass 19, count 2 2006.285.08:14:02.09#ibcon#read 3, iclass 19, count 2 2006.285.08:14:02.09#ibcon#about to read 4, iclass 19, count 2 2006.285.08:14:02.09#ibcon#read 4, iclass 19, count 2 2006.285.08:14:02.09#ibcon#about to read 5, iclass 19, count 2 2006.285.08:14:02.09#ibcon#read 5, iclass 19, count 2 2006.285.08:14:02.09#ibcon#about to read 6, iclass 19, count 2 2006.285.08:14:02.09#ibcon#read 6, iclass 19, count 2 2006.285.08:14:02.09#ibcon#end of sib2, iclass 19, count 2 2006.285.08:14:02.09#ibcon#*mode == 0, iclass 19, count 2 2006.285.08:14:02.09#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.08:14:02.09#ibcon#[27=AT04-05\r\n] 2006.285.08:14:02.09#ibcon#*before write, iclass 19, count 2 2006.285.08:14:02.09#ibcon#enter sib2, iclass 19, count 2 2006.285.08:14:02.09#ibcon#flushed, iclass 19, count 2 2006.285.08:14:02.09#ibcon#about to write, iclass 19, count 2 2006.285.08:14:02.09#ibcon#wrote, iclass 19, count 2 2006.285.08:14:02.09#ibcon#about to read 3, iclass 19, count 2 2006.285.08:14:02.12#ibcon#read 3, iclass 19, count 2 2006.285.08:14:02.12#ibcon#about to read 4, iclass 19, count 2 2006.285.08:14:02.12#ibcon#read 4, iclass 19, count 2 2006.285.08:14:02.12#ibcon#about to read 5, iclass 19, count 2 2006.285.08:14:02.12#ibcon#read 5, iclass 19, count 2 2006.285.08:14:02.12#ibcon#about to read 6, iclass 19, count 2 2006.285.08:14:02.12#ibcon#read 6, iclass 19, count 2 2006.285.08:14:02.12#ibcon#end of sib2, iclass 19, count 2 2006.285.08:14:02.12#ibcon#*after write, iclass 19, count 2 2006.285.08:14:02.12#ibcon#*before return 0, iclass 19, count 2 2006.285.08:14:02.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:14:02.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:14:02.12#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.08:14:02.12#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:02.12#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:14:02.24#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:14:02.24#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:14:02.24#ibcon#enter wrdev, iclass 19, count 0 2006.285.08:14:02.24#ibcon#first serial, iclass 19, count 0 2006.285.08:14:02.24#ibcon#enter sib2, iclass 19, count 0 2006.285.08:14:02.24#ibcon#flushed, iclass 19, count 0 2006.285.08:14:02.24#ibcon#about to write, iclass 19, count 0 2006.285.08:14:02.24#ibcon#wrote, iclass 19, count 0 2006.285.08:14:02.24#ibcon#about to read 3, iclass 19, count 0 2006.285.08:14:02.26#ibcon#read 3, iclass 19, count 0 2006.285.08:14:02.26#ibcon#about to read 4, iclass 19, count 0 2006.285.08:14:02.26#ibcon#read 4, iclass 19, count 0 2006.285.08:14:02.26#ibcon#about to read 5, iclass 19, count 0 2006.285.08:14:02.26#ibcon#read 5, iclass 19, count 0 2006.285.08:14:02.26#ibcon#about to read 6, iclass 19, count 0 2006.285.08:14:02.26#ibcon#read 6, iclass 19, count 0 2006.285.08:14:02.26#ibcon#end of sib2, iclass 19, count 0 2006.285.08:14:02.26#ibcon#*mode == 0, iclass 19, count 0 2006.285.08:14:02.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.08:14:02.26#ibcon#[27=USB\r\n] 2006.285.08:14:02.26#ibcon#*before write, iclass 19, count 0 2006.285.08:14:02.26#ibcon#enter sib2, iclass 19, count 0 2006.285.08:14:02.26#ibcon#flushed, iclass 19, count 0 2006.285.08:14:02.26#ibcon#about to write, iclass 19, count 0 2006.285.08:14:02.26#ibcon#wrote, iclass 19, count 0 2006.285.08:14:02.26#ibcon#about to read 3, iclass 19, count 0 2006.285.08:14:02.29#ibcon#read 3, iclass 19, count 0 2006.285.08:14:02.29#ibcon#about to read 4, iclass 19, count 0 2006.285.08:14:02.29#ibcon#read 4, iclass 19, count 0 2006.285.08:14:02.29#ibcon#about to read 5, iclass 19, count 0 2006.285.08:14:02.29#ibcon#read 5, iclass 19, count 0 2006.285.08:14:02.29#ibcon#about to read 6, iclass 19, count 0 2006.285.08:14:02.29#ibcon#read 6, iclass 19, count 0 2006.285.08:14:02.29#ibcon#end of sib2, iclass 19, count 0 2006.285.08:14:02.29#ibcon#*after write, iclass 19, count 0 2006.285.08:14:02.29#ibcon#*before return 0, iclass 19, count 0 2006.285.08:14:02.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:14:02.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:14:02.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.08:14:02.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.08:14:02.30$vck44/vblo=5,709.99 2006.285.08:14:02.30#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.08:14:02.30#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.08:14:02.30#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:02.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:14:02.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:14:02.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:14:02.30#ibcon#enter wrdev, iclass 21, count 0 2006.285.08:14:02.30#ibcon#first serial, iclass 21, count 0 2006.285.08:14:02.30#ibcon#enter sib2, iclass 21, count 0 2006.285.08:14:02.30#ibcon#flushed, iclass 21, count 0 2006.285.08:14:02.30#ibcon#about to write, iclass 21, count 0 2006.285.08:14:02.30#ibcon#wrote, iclass 21, count 0 2006.285.08:14:02.30#ibcon#about to read 3, iclass 21, count 0 2006.285.08:14:02.31#ibcon#read 3, iclass 21, count 0 2006.285.08:14:02.31#ibcon#about to read 4, iclass 21, count 0 2006.285.08:14:02.31#ibcon#read 4, iclass 21, count 0 2006.285.08:14:02.31#ibcon#about to read 5, iclass 21, count 0 2006.285.08:14:02.31#ibcon#read 5, iclass 21, count 0 2006.285.08:14:02.31#ibcon#about to read 6, iclass 21, count 0 2006.285.08:14:02.31#ibcon#read 6, iclass 21, count 0 2006.285.08:14:02.31#ibcon#end of sib2, iclass 21, count 0 2006.285.08:14:02.31#ibcon#*mode == 0, iclass 21, count 0 2006.285.08:14:02.31#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.08:14:02.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:14:02.31#ibcon#*before write, iclass 21, count 0 2006.285.08:14:02.31#ibcon#enter sib2, iclass 21, count 0 2006.285.08:14:02.31#ibcon#flushed, iclass 21, count 0 2006.285.08:14:02.31#ibcon#about to write, iclass 21, count 0 2006.285.08:14:02.31#ibcon#wrote, iclass 21, count 0 2006.285.08:14:02.31#ibcon#about to read 3, iclass 21, count 0 2006.285.08:14:02.35#ibcon#read 3, iclass 21, count 0 2006.285.08:14:02.35#ibcon#about to read 4, iclass 21, count 0 2006.285.08:14:02.35#ibcon#read 4, iclass 21, count 0 2006.285.08:14:02.35#ibcon#about to read 5, iclass 21, count 0 2006.285.08:14:02.35#ibcon#read 5, iclass 21, count 0 2006.285.08:14:02.35#ibcon#about to read 6, iclass 21, count 0 2006.285.08:14:02.35#ibcon#read 6, iclass 21, count 0 2006.285.08:14:02.35#ibcon#end of sib2, iclass 21, count 0 2006.285.08:14:02.35#ibcon#*after write, iclass 21, count 0 2006.285.08:14:02.35#ibcon#*before return 0, iclass 21, count 0 2006.285.08:14:02.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:14:02.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:14:02.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.08:14:02.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.08:14:02.35$vck44/vb=5,4 2006.285.08:14:02.36#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.08:14:02.36#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.08:14:02.36#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:02.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:14:02.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:14:02.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:14:02.40#ibcon#enter wrdev, iclass 23, count 2 2006.285.08:14:02.40#ibcon#first serial, iclass 23, count 2 2006.285.08:14:02.40#ibcon#enter sib2, iclass 23, count 2 2006.285.08:14:02.40#ibcon#flushed, iclass 23, count 2 2006.285.08:14:02.40#ibcon#about to write, iclass 23, count 2 2006.285.08:14:02.40#ibcon#wrote, iclass 23, count 2 2006.285.08:14:02.40#ibcon#about to read 3, iclass 23, count 2 2006.285.08:14:02.42#ibcon#read 3, iclass 23, count 2 2006.285.08:14:02.42#ibcon#about to read 4, iclass 23, count 2 2006.285.08:14:02.42#ibcon#read 4, iclass 23, count 2 2006.285.08:14:02.42#ibcon#about to read 5, iclass 23, count 2 2006.285.08:14:02.42#ibcon#read 5, iclass 23, count 2 2006.285.08:14:02.42#ibcon#about to read 6, iclass 23, count 2 2006.285.08:14:02.42#ibcon#read 6, iclass 23, count 2 2006.285.08:14:02.42#ibcon#end of sib2, iclass 23, count 2 2006.285.08:14:02.42#ibcon#*mode == 0, iclass 23, count 2 2006.285.08:14:02.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.08:14:02.42#ibcon#[27=AT05-04\r\n] 2006.285.08:14:02.42#ibcon#*before write, iclass 23, count 2 2006.285.08:14:02.42#ibcon#enter sib2, iclass 23, count 2 2006.285.08:14:02.42#ibcon#flushed, iclass 23, count 2 2006.285.08:14:02.42#ibcon#about to write, iclass 23, count 2 2006.285.08:14:02.42#ibcon#wrote, iclass 23, count 2 2006.285.08:14:02.42#ibcon#about to read 3, iclass 23, count 2 2006.285.08:14:02.45#ibcon#read 3, iclass 23, count 2 2006.285.08:14:02.45#ibcon#about to read 4, iclass 23, count 2 2006.285.08:14:02.45#ibcon#read 4, iclass 23, count 2 2006.285.08:14:02.45#ibcon#about to read 5, iclass 23, count 2 2006.285.08:14:02.45#ibcon#read 5, iclass 23, count 2 2006.285.08:14:02.45#ibcon#about to read 6, iclass 23, count 2 2006.285.08:14:02.45#ibcon#read 6, iclass 23, count 2 2006.285.08:14:02.45#ibcon#end of sib2, iclass 23, count 2 2006.285.08:14:02.45#ibcon#*after write, iclass 23, count 2 2006.285.08:14:02.45#ibcon#*before return 0, iclass 23, count 2 2006.285.08:14:02.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:14:02.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:14:02.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.08:14:02.45#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:02.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:14:02.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:14:02.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:14:02.57#ibcon#enter wrdev, iclass 23, count 0 2006.285.08:14:02.57#ibcon#first serial, iclass 23, count 0 2006.285.08:14:02.57#ibcon#enter sib2, iclass 23, count 0 2006.285.08:14:02.57#ibcon#flushed, iclass 23, count 0 2006.285.08:14:02.57#ibcon#about to write, iclass 23, count 0 2006.285.08:14:02.57#ibcon#wrote, iclass 23, count 0 2006.285.08:14:02.57#ibcon#about to read 3, iclass 23, count 0 2006.285.08:14:02.59#ibcon#read 3, iclass 23, count 0 2006.285.08:14:02.59#ibcon#about to read 4, iclass 23, count 0 2006.285.08:14:02.59#ibcon#read 4, iclass 23, count 0 2006.285.08:14:02.59#ibcon#about to read 5, iclass 23, count 0 2006.285.08:14:02.59#ibcon#read 5, iclass 23, count 0 2006.285.08:14:02.59#ibcon#about to read 6, iclass 23, count 0 2006.285.08:14:02.59#ibcon#read 6, iclass 23, count 0 2006.285.08:14:02.59#ibcon#end of sib2, iclass 23, count 0 2006.285.08:14:02.59#ibcon#*mode == 0, iclass 23, count 0 2006.285.08:14:02.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.08:14:02.59#ibcon#[27=USB\r\n] 2006.285.08:14:02.59#ibcon#*before write, iclass 23, count 0 2006.285.08:14:02.59#ibcon#enter sib2, iclass 23, count 0 2006.285.08:14:02.59#ibcon#flushed, iclass 23, count 0 2006.285.08:14:02.59#ibcon#about to write, iclass 23, count 0 2006.285.08:14:02.59#ibcon#wrote, iclass 23, count 0 2006.285.08:14:02.59#ibcon#about to read 3, iclass 23, count 0 2006.285.08:14:02.62#ibcon#read 3, iclass 23, count 0 2006.285.08:14:02.62#ibcon#about to read 4, iclass 23, count 0 2006.285.08:14:02.62#ibcon#read 4, iclass 23, count 0 2006.285.08:14:02.62#ibcon#about to read 5, iclass 23, count 0 2006.285.08:14:02.62#ibcon#read 5, iclass 23, count 0 2006.285.08:14:02.62#ibcon#about to read 6, iclass 23, count 0 2006.285.08:14:02.62#ibcon#read 6, iclass 23, count 0 2006.285.08:14:02.62#ibcon#end of sib2, iclass 23, count 0 2006.285.08:14:02.62#ibcon#*after write, iclass 23, count 0 2006.285.08:14:02.62#ibcon#*before return 0, iclass 23, count 0 2006.285.08:14:02.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:14:02.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:14:02.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.08:14:02.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.08:14:02.62$vck44/vblo=6,719.99 2006.285.08:14:02.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.08:14:02.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.08:14:02.63#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:02.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:14:02.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:14:02.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:14:02.63#ibcon#enter wrdev, iclass 25, count 0 2006.285.08:14:02.63#ibcon#first serial, iclass 25, count 0 2006.285.08:14:02.63#ibcon#enter sib2, iclass 25, count 0 2006.285.08:14:02.63#ibcon#flushed, iclass 25, count 0 2006.285.08:14:02.63#ibcon#about to write, iclass 25, count 0 2006.285.08:14:02.63#ibcon#wrote, iclass 25, count 0 2006.285.08:14:02.63#ibcon#about to read 3, iclass 25, count 0 2006.285.08:14:02.64#ibcon#read 3, iclass 25, count 0 2006.285.08:14:02.64#ibcon#about to read 4, iclass 25, count 0 2006.285.08:14:02.64#ibcon#read 4, iclass 25, count 0 2006.285.08:14:02.64#ibcon#about to read 5, iclass 25, count 0 2006.285.08:14:02.64#ibcon#read 5, iclass 25, count 0 2006.285.08:14:02.64#ibcon#about to read 6, iclass 25, count 0 2006.285.08:14:02.64#ibcon#read 6, iclass 25, count 0 2006.285.08:14:02.64#ibcon#end of sib2, iclass 25, count 0 2006.285.08:14:02.64#ibcon#*mode == 0, iclass 25, count 0 2006.285.08:14:02.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.08:14:02.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:14:02.64#ibcon#*before write, iclass 25, count 0 2006.285.08:14:02.64#ibcon#enter sib2, iclass 25, count 0 2006.285.08:14:02.64#ibcon#flushed, iclass 25, count 0 2006.285.08:14:02.64#ibcon#about to write, iclass 25, count 0 2006.285.08:14:02.64#ibcon#wrote, iclass 25, count 0 2006.285.08:14:02.64#ibcon#about to read 3, iclass 25, count 0 2006.285.08:14:02.68#ibcon#read 3, iclass 25, count 0 2006.285.08:14:02.68#ibcon#about to read 4, iclass 25, count 0 2006.285.08:14:02.68#ibcon#read 4, iclass 25, count 0 2006.285.08:14:02.68#ibcon#about to read 5, iclass 25, count 0 2006.285.08:14:02.68#ibcon#read 5, iclass 25, count 0 2006.285.08:14:02.68#ibcon#about to read 6, iclass 25, count 0 2006.285.08:14:02.68#ibcon#read 6, iclass 25, count 0 2006.285.08:14:02.68#ibcon#end of sib2, iclass 25, count 0 2006.285.08:14:02.68#ibcon#*after write, iclass 25, count 0 2006.285.08:14:02.68#ibcon#*before return 0, iclass 25, count 0 2006.285.08:14:02.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:14:02.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:14:02.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.08:14:02.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.08:14:02.68$vck44/vb=6,3 2006.285.08:14:02.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.08:14:02.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.08:14:02.69#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:02.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:14:02.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:14:02.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:14:02.73#ibcon#enter wrdev, iclass 27, count 2 2006.285.08:14:02.73#ibcon#first serial, iclass 27, count 2 2006.285.08:14:02.73#ibcon#enter sib2, iclass 27, count 2 2006.285.08:14:02.73#ibcon#flushed, iclass 27, count 2 2006.285.08:14:02.73#ibcon#about to write, iclass 27, count 2 2006.285.08:14:02.73#ibcon#wrote, iclass 27, count 2 2006.285.08:14:02.73#ibcon#about to read 3, iclass 27, count 2 2006.285.08:14:02.75#ibcon#read 3, iclass 27, count 2 2006.285.08:14:02.75#ibcon#about to read 4, iclass 27, count 2 2006.285.08:14:02.75#ibcon#read 4, iclass 27, count 2 2006.285.08:14:02.75#ibcon#about to read 5, iclass 27, count 2 2006.285.08:14:02.75#ibcon#read 5, iclass 27, count 2 2006.285.08:14:02.75#ibcon#about to read 6, iclass 27, count 2 2006.285.08:14:02.75#ibcon#read 6, iclass 27, count 2 2006.285.08:14:02.75#ibcon#end of sib2, iclass 27, count 2 2006.285.08:14:02.75#ibcon#*mode == 0, iclass 27, count 2 2006.285.08:14:02.75#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.08:14:02.75#ibcon#[27=AT06-03\r\n] 2006.285.08:14:02.75#ibcon#*before write, iclass 27, count 2 2006.285.08:14:02.75#ibcon#enter sib2, iclass 27, count 2 2006.285.08:14:02.75#ibcon#flushed, iclass 27, count 2 2006.285.08:14:02.75#ibcon#about to write, iclass 27, count 2 2006.285.08:14:02.75#ibcon#wrote, iclass 27, count 2 2006.285.08:14:02.75#ibcon#about to read 3, iclass 27, count 2 2006.285.08:14:02.78#ibcon#read 3, iclass 27, count 2 2006.285.08:14:02.78#ibcon#about to read 4, iclass 27, count 2 2006.285.08:14:02.78#ibcon#read 4, iclass 27, count 2 2006.285.08:14:02.78#ibcon#about to read 5, iclass 27, count 2 2006.285.08:14:02.78#ibcon#read 5, iclass 27, count 2 2006.285.08:14:02.78#ibcon#about to read 6, iclass 27, count 2 2006.285.08:14:02.78#ibcon#read 6, iclass 27, count 2 2006.285.08:14:02.78#ibcon#end of sib2, iclass 27, count 2 2006.285.08:14:02.78#ibcon#*after write, iclass 27, count 2 2006.285.08:14:02.78#ibcon#*before return 0, iclass 27, count 2 2006.285.08:14:02.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:14:02.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:14:02.78#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.08:14:02.78#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:02.78#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:14:02.90#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:14:02.90#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:14:02.90#ibcon#enter wrdev, iclass 27, count 0 2006.285.08:14:02.90#ibcon#first serial, iclass 27, count 0 2006.285.08:14:02.90#ibcon#enter sib2, iclass 27, count 0 2006.285.08:14:02.90#ibcon#flushed, iclass 27, count 0 2006.285.08:14:02.90#ibcon#about to write, iclass 27, count 0 2006.285.08:14:02.90#ibcon#wrote, iclass 27, count 0 2006.285.08:14:02.90#ibcon#about to read 3, iclass 27, count 0 2006.285.08:14:02.92#ibcon#read 3, iclass 27, count 0 2006.285.08:14:02.92#ibcon#about to read 4, iclass 27, count 0 2006.285.08:14:02.92#ibcon#read 4, iclass 27, count 0 2006.285.08:14:02.92#ibcon#about to read 5, iclass 27, count 0 2006.285.08:14:02.92#ibcon#read 5, iclass 27, count 0 2006.285.08:14:02.92#ibcon#about to read 6, iclass 27, count 0 2006.285.08:14:02.92#ibcon#read 6, iclass 27, count 0 2006.285.08:14:02.92#ibcon#end of sib2, iclass 27, count 0 2006.285.08:14:02.92#ibcon#*mode == 0, iclass 27, count 0 2006.285.08:14:02.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.08:14:02.92#ibcon#[27=USB\r\n] 2006.285.08:14:02.92#ibcon#*before write, iclass 27, count 0 2006.285.08:14:02.92#ibcon#enter sib2, iclass 27, count 0 2006.285.08:14:02.92#ibcon#flushed, iclass 27, count 0 2006.285.08:14:02.92#ibcon#about to write, iclass 27, count 0 2006.285.08:14:02.92#ibcon#wrote, iclass 27, count 0 2006.285.08:14:02.92#ibcon#about to read 3, iclass 27, count 0 2006.285.08:14:02.95#ibcon#read 3, iclass 27, count 0 2006.285.08:14:02.95#ibcon#about to read 4, iclass 27, count 0 2006.285.08:14:02.95#ibcon#read 4, iclass 27, count 0 2006.285.08:14:02.95#ibcon#about to read 5, iclass 27, count 0 2006.285.08:14:02.95#ibcon#read 5, iclass 27, count 0 2006.285.08:14:02.95#ibcon#about to read 6, iclass 27, count 0 2006.285.08:14:02.95#ibcon#read 6, iclass 27, count 0 2006.285.08:14:02.95#ibcon#end of sib2, iclass 27, count 0 2006.285.08:14:02.95#ibcon#*after write, iclass 27, count 0 2006.285.08:14:02.95#ibcon#*before return 0, iclass 27, count 0 2006.285.08:14:02.95#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:14:02.95#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:14:02.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.08:14:02.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.08:14:02.95$vck44/vblo=7,734.99 2006.285.08:14:02.96#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.08:14:02.96#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.08:14:02.96#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:02.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:14:02.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:14:02.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:14:02.96#ibcon#enter wrdev, iclass 29, count 0 2006.285.08:14:02.96#ibcon#first serial, iclass 29, count 0 2006.285.08:14:02.96#ibcon#enter sib2, iclass 29, count 0 2006.285.08:14:02.96#ibcon#flushed, iclass 29, count 0 2006.285.08:14:02.96#ibcon#about to write, iclass 29, count 0 2006.285.08:14:02.96#ibcon#wrote, iclass 29, count 0 2006.285.08:14:02.96#ibcon#about to read 3, iclass 29, count 0 2006.285.08:14:02.97#ibcon#read 3, iclass 29, count 0 2006.285.08:14:02.97#ibcon#about to read 4, iclass 29, count 0 2006.285.08:14:02.97#ibcon#read 4, iclass 29, count 0 2006.285.08:14:02.97#ibcon#about to read 5, iclass 29, count 0 2006.285.08:14:02.97#ibcon#read 5, iclass 29, count 0 2006.285.08:14:02.97#ibcon#about to read 6, iclass 29, count 0 2006.285.08:14:02.97#ibcon#read 6, iclass 29, count 0 2006.285.08:14:02.97#ibcon#end of sib2, iclass 29, count 0 2006.285.08:14:02.97#ibcon#*mode == 0, iclass 29, count 0 2006.285.08:14:02.97#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.08:14:02.97#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:14:02.97#ibcon#*before write, iclass 29, count 0 2006.285.08:14:02.97#ibcon#enter sib2, iclass 29, count 0 2006.285.08:14:02.97#ibcon#flushed, iclass 29, count 0 2006.285.08:14:02.97#ibcon#about to write, iclass 29, count 0 2006.285.08:14:02.97#ibcon#wrote, iclass 29, count 0 2006.285.08:14:02.97#ibcon#about to read 3, iclass 29, count 0 2006.285.08:14:03.01#ibcon#read 3, iclass 29, count 0 2006.285.08:14:03.01#ibcon#about to read 4, iclass 29, count 0 2006.285.08:14:03.01#ibcon#read 4, iclass 29, count 0 2006.285.08:14:03.01#ibcon#about to read 5, iclass 29, count 0 2006.285.08:14:03.01#ibcon#read 5, iclass 29, count 0 2006.285.08:14:03.01#ibcon#about to read 6, iclass 29, count 0 2006.285.08:14:03.01#ibcon#read 6, iclass 29, count 0 2006.285.08:14:03.01#ibcon#end of sib2, iclass 29, count 0 2006.285.08:14:03.01#ibcon#*after write, iclass 29, count 0 2006.285.08:14:03.01#ibcon#*before return 0, iclass 29, count 0 2006.285.08:14:03.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:14:03.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:14:03.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.08:14:03.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.08:14:03.01$vck44/vb=7,4 2006.285.08:14:03.02#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.08:14:03.02#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.08:14:03.02#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:03.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:14:03.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:14:03.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:14:03.06#ibcon#enter wrdev, iclass 31, count 2 2006.285.08:14:03.06#ibcon#first serial, iclass 31, count 2 2006.285.08:14:03.06#ibcon#enter sib2, iclass 31, count 2 2006.285.08:14:03.06#ibcon#flushed, iclass 31, count 2 2006.285.08:14:03.06#ibcon#about to write, iclass 31, count 2 2006.285.08:14:03.06#ibcon#wrote, iclass 31, count 2 2006.285.08:14:03.06#ibcon#about to read 3, iclass 31, count 2 2006.285.08:14:03.08#ibcon#read 3, iclass 31, count 2 2006.285.08:14:03.08#ibcon#about to read 4, iclass 31, count 2 2006.285.08:14:03.08#ibcon#read 4, iclass 31, count 2 2006.285.08:14:03.08#ibcon#about to read 5, iclass 31, count 2 2006.285.08:14:03.08#ibcon#read 5, iclass 31, count 2 2006.285.08:14:03.08#ibcon#about to read 6, iclass 31, count 2 2006.285.08:14:03.08#ibcon#read 6, iclass 31, count 2 2006.285.08:14:03.08#ibcon#end of sib2, iclass 31, count 2 2006.285.08:14:03.08#ibcon#*mode == 0, iclass 31, count 2 2006.285.08:14:03.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.08:14:03.08#ibcon#[27=AT07-04\r\n] 2006.285.08:14:03.08#ibcon#*before write, iclass 31, count 2 2006.285.08:14:03.08#ibcon#enter sib2, iclass 31, count 2 2006.285.08:14:03.08#ibcon#flushed, iclass 31, count 2 2006.285.08:14:03.08#ibcon#about to write, iclass 31, count 2 2006.285.08:14:03.08#ibcon#wrote, iclass 31, count 2 2006.285.08:14:03.08#ibcon#about to read 3, iclass 31, count 2 2006.285.08:14:03.11#ibcon#read 3, iclass 31, count 2 2006.285.08:14:03.11#ibcon#about to read 4, iclass 31, count 2 2006.285.08:14:03.11#ibcon#read 4, iclass 31, count 2 2006.285.08:14:03.11#ibcon#about to read 5, iclass 31, count 2 2006.285.08:14:03.11#ibcon#read 5, iclass 31, count 2 2006.285.08:14:03.11#ibcon#about to read 6, iclass 31, count 2 2006.285.08:14:03.11#ibcon#read 6, iclass 31, count 2 2006.285.08:14:03.11#ibcon#end of sib2, iclass 31, count 2 2006.285.08:14:03.11#ibcon#*after write, iclass 31, count 2 2006.285.08:14:03.11#ibcon#*before return 0, iclass 31, count 2 2006.285.08:14:03.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:14:03.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:14:03.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.08:14:03.11#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:03.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:14:03.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:14:03.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:14:03.23#ibcon#enter wrdev, iclass 31, count 0 2006.285.08:14:03.23#ibcon#first serial, iclass 31, count 0 2006.285.08:14:03.23#ibcon#enter sib2, iclass 31, count 0 2006.285.08:14:03.23#ibcon#flushed, iclass 31, count 0 2006.285.08:14:03.23#ibcon#about to write, iclass 31, count 0 2006.285.08:14:03.23#ibcon#wrote, iclass 31, count 0 2006.285.08:14:03.23#ibcon#about to read 3, iclass 31, count 0 2006.285.08:14:03.25#ibcon#read 3, iclass 31, count 0 2006.285.08:14:03.25#ibcon#about to read 4, iclass 31, count 0 2006.285.08:14:03.25#ibcon#read 4, iclass 31, count 0 2006.285.08:14:03.25#ibcon#about to read 5, iclass 31, count 0 2006.285.08:14:03.25#ibcon#read 5, iclass 31, count 0 2006.285.08:14:03.25#ibcon#about to read 6, iclass 31, count 0 2006.285.08:14:03.25#ibcon#read 6, iclass 31, count 0 2006.285.08:14:03.25#ibcon#end of sib2, iclass 31, count 0 2006.285.08:14:03.25#ibcon#*mode == 0, iclass 31, count 0 2006.285.08:14:03.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.08:14:03.25#ibcon#[27=USB\r\n] 2006.285.08:14:03.25#ibcon#*before write, iclass 31, count 0 2006.285.08:14:03.25#ibcon#enter sib2, iclass 31, count 0 2006.285.08:14:03.25#ibcon#flushed, iclass 31, count 0 2006.285.08:14:03.25#ibcon#about to write, iclass 31, count 0 2006.285.08:14:03.25#ibcon#wrote, iclass 31, count 0 2006.285.08:14:03.25#ibcon#about to read 3, iclass 31, count 0 2006.285.08:14:03.28#ibcon#read 3, iclass 31, count 0 2006.285.08:14:03.28#ibcon#about to read 4, iclass 31, count 0 2006.285.08:14:03.28#ibcon#read 4, iclass 31, count 0 2006.285.08:14:03.28#ibcon#about to read 5, iclass 31, count 0 2006.285.08:14:03.28#ibcon#read 5, iclass 31, count 0 2006.285.08:14:03.28#ibcon#about to read 6, iclass 31, count 0 2006.285.08:14:03.28#ibcon#read 6, iclass 31, count 0 2006.285.08:14:03.28#ibcon#end of sib2, iclass 31, count 0 2006.285.08:14:03.28#ibcon#*after write, iclass 31, count 0 2006.285.08:14:03.28#ibcon#*before return 0, iclass 31, count 0 2006.285.08:14:03.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:14:03.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:14:03.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.08:14:03.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.08:14:03.29$vck44/vblo=8,744.99 2006.285.08:14:03.29#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.08:14:03.29#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.08:14:03.29#ibcon#ireg 17 cls_cnt 0 2006.285.08:14:03.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:14:03.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:14:03.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:14:03.29#ibcon#enter wrdev, iclass 33, count 0 2006.285.08:14:03.29#ibcon#first serial, iclass 33, count 0 2006.285.08:14:03.29#ibcon#enter sib2, iclass 33, count 0 2006.285.08:14:03.29#ibcon#flushed, iclass 33, count 0 2006.285.08:14:03.29#ibcon#about to write, iclass 33, count 0 2006.285.08:14:03.29#ibcon#wrote, iclass 33, count 0 2006.285.08:14:03.29#ibcon#about to read 3, iclass 33, count 0 2006.285.08:14:03.30#ibcon#read 3, iclass 33, count 0 2006.285.08:14:03.30#ibcon#about to read 4, iclass 33, count 0 2006.285.08:14:03.30#ibcon#read 4, iclass 33, count 0 2006.285.08:14:03.30#ibcon#about to read 5, iclass 33, count 0 2006.285.08:14:03.30#ibcon#read 5, iclass 33, count 0 2006.285.08:14:03.30#ibcon#about to read 6, iclass 33, count 0 2006.285.08:14:03.30#ibcon#read 6, iclass 33, count 0 2006.285.08:14:03.30#ibcon#end of sib2, iclass 33, count 0 2006.285.08:14:03.30#ibcon#*mode == 0, iclass 33, count 0 2006.285.08:14:03.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.08:14:03.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:14:03.30#ibcon#*before write, iclass 33, count 0 2006.285.08:14:03.30#ibcon#enter sib2, iclass 33, count 0 2006.285.08:14:03.30#ibcon#flushed, iclass 33, count 0 2006.285.08:14:03.30#ibcon#about to write, iclass 33, count 0 2006.285.08:14:03.30#ibcon#wrote, iclass 33, count 0 2006.285.08:14:03.30#ibcon#about to read 3, iclass 33, count 0 2006.285.08:14:03.34#ibcon#read 3, iclass 33, count 0 2006.285.08:14:03.34#ibcon#about to read 4, iclass 33, count 0 2006.285.08:14:03.34#ibcon#read 4, iclass 33, count 0 2006.285.08:14:03.34#ibcon#about to read 5, iclass 33, count 0 2006.285.08:14:03.34#ibcon#read 5, iclass 33, count 0 2006.285.08:14:03.34#ibcon#about to read 6, iclass 33, count 0 2006.285.08:14:03.34#ibcon#read 6, iclass 33, count 0 2006.285.08:14:03.34#ibcon#end of sib2, iclass 33, count 0 2006.285.08:14:03.34#ibcon#*after write, iclass 33, count 0 2006.285.08:14:03.34#ibcon#*before return 0, iclass 33, count 0 2006.285.08:14:03.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:14:03.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:14:03.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.08:14:03.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.08:14:03.34$vck44/vb=8,4 2006.285.08:14:03.35#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.08:14:03.35#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.08:14:03.35#ibcon#ireg 11 cls_cnt 2 2006.285.08:14:03.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:14:03.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:14:03.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:14:03.39#ibcon#enter wrdev, iclass 35, count 2 2006.285.08:14:03.39#ibcon#first serial, iclass 35, count 2 2006.285.08:14:03.39#ibcon#enter sib2, iclass 35, count 2 2006.285.08:14:03.39#ibcon#flushed, iclass 35, count 2 2006.285.08:14:03.39#ibcon#about to write, iclass 35, count 2 2006.285.08:14:03.39#ibcon#wrote, iclass 35, count 2 2006.285.08:14:03.39#ibcon#about to read 3, iclass 35, count 2 2006.285.08:14:03.41#ibcon#read 3, iclass 35, count 2 2006.285.08:14:03.41#ibcon#about to read 4, iclass 35, count 2 2006.285.08:14:03.41#ibcon#read 4, iclass 35, count 2 2006.285.08:14:03.41#ibcon#about to read 5, iclass 35, count 2 2006.285.08:14:03.41#ibcon#read 5, iclass 35, count 2 2006.285.08:14:03.41#ibcon#about to read 6, iclass 35, count 2 2006.285.08:14:03.41#ibcon#read 6, iclass 35, count 2 2006.285.08:14:03.41#ibcon#end of sib2, iclass 35, count 2 2006.285.08:14:03.41#ibcon#*mode == 0, iclass 35, count 2 2006.285.08:14:03.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.08:14:03.41#ibcon#[27=AT08-04\r\n] 2006.285.08:14:03.41#ibcon#*before write, iclass 35, count 2 2006.285.08:14:03.41#ibcon#enter sib2, iclass 35, count 2 2006.285.08:14:03.41#ibcon#flushed, iclass 35, count 2 2006.285.08:14:03.41#ibcon#about to write, iclass 35, count 2 2006.285.08:14:03.41#ibcon#wrote, iclass 35, count 2 2006.285.08:14:03.41#ibcon#about to read 3, iclass 35, count 2 2006.285.08:14:03.44#ibcon#read 3, iclass 35, count 2 2006.285.08:14:03.44#ibcon#about to read 4, iclass 35, count 2 2006.285.08:14:03.44#ibcon#read 4, iclass 35, count 2 2006.285.08:14:03.44#ibcon#about to read 5, iclass 35, count 2 2006.285.08:14:03.44#ibcon#read 5, iclass 35, count 2 2006.285.08:14:03.44#ibcon#about to read 6, iclass 35, count 2 2006.285.08:14:03.44#ibcon#read 6, iclass 35, count 2 2006.285.08:14:03.44#ibcon#end of sib2, iclass 35, count 2 2006.285.08:14:03.44#ibcon#*after write, iclass 35, count 2 2006.285.08:14:03.44#ibcon#*before return 0, iclass 35, count 2 2006.285.08:14:03.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:14:03.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:14:03.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.08:14:03.44#ibcon#ireg 7 cls_cnt 0 2006.285.08:14:03.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:14:03.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:14:03.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:14:03.56#ibcon#enter wrdev, iclass 35, count 0 2006.285.08:14:03.56#ibcon#first serial, iclass 35, count 0 2006.285.08:14:03.56#ibcon#enter sib2, iclass 35, count 0 2006.285.08:14:03.56#ibcon#flushed, iclass 35, count 0 2006.285.08:14:03.56#ibcon#about to write, iclass 35, count 0 2006.285.08:14:03.56#ibcon#wrote, iclass 35, count 0 2006.285.08:14:03.56#ibcon#about to read 3, iclass 35, count 0 2006.285.08:14:03.58#ibcon#read 3, iclass 35, count 0 2006.285.08:14:03.58#ibcon#about to read 4, iclass 35, count 0 2006.285.08:14:03.58#ibcon#read 4, iclass 35, count 0 2006.285.08:14:03.58#ibcon#about to read 5, iclass 35, count 0 2006.285.08:14:03.58#ibcon#read 5, iclass 35, count 0 2006.285.08:14:03.58#ibcon#about to read 6, iclass 35, count 0 2006.285.08:14:03.58#ibcon#read 6, iclass 35, count 0 2006.285.08:14:03.58#ibcon#end of sib2, iclass 35, count 0 2006.285.08:14:03.58#ibcon#*mode == 0, iclass 35, count 0 2006.285.08:14:03.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.08:14:03.58#ibcon#[27=USB\r\n] 2006.285.08:14:03.58#ibcon#*before write, iclass 35, count 0 2006.285.08:14:03.58#ibcon#enter sib2, iclass 35, count 0 2006.285.08:14:03.58#ibcon#flushed, iclass 35, count 0 2006.285.08:14:03.58#ibcon#about to write, iclass 35, count 0 2006.285.08:14:03.58#ibcon#wrote, iclass 35, count 0 2006.285.08:14:03.58#ibcon#about to read 3, iclass 35, count 0 2006.285.08:14:03.61#ibcon#read 3, iclass 35, count 0 2006.285.08:14:03.61#ibcon#about to read 4, iclass 35, count 0 2006.285.08:14:03.61#ibcon#read 4, iclass 35, count 0 2006.285.08:14:03.61#ibcon#about to read 5, iclass 35, count 0 2006.285.08:14:03.61#ibcon#read 5, iclass 35, count 0 2006.285.08:14:03.61#ibcon#about to read 6, iclass 35, count 0 2006.285.08:14:03.61#ibcon#read 6, iclass 35, count 0 2006.285.08:14:03.61#ibcon#end of sib2, iclass 35, count 0 2006.285.08:14:03.61#ibcon#*after write, iclass 35, count 0 2006.285.08:14:03.61#ibcon#*before return 0, iclass 35, count 0 2006.285.08:14:03.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:14:03.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:14:03.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.08:14:03.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.08:14:03.61$vck44/vabw=wide 2006.285.08:14:03.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.08:14:03.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.08:14:03.62#ibcon#ireg 8 cls_cnt 0 2006.285.08:14:03.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:14:03.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:14:03.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:14:03.62#ibcon#enter wrdev, iclass 37, count 0 2006.285.08:14:03.62#ibcon#first serial, iclass 37, count 0 2006.285.08:14:03.62#ibcon#enter sib2, iclass 37, count 0 2006.285.08:14:03.62#ibcon#flushed, iclass 37, count 0 2006.285.08:14:03.62#ibcon#about to write, iclass 37, count 0 2006.285.08:14:03.62#ibcon#wrote, iclass 37, count 0 2006.285.08:14:03.62#ibcon#about to read 3, iclass 37, count 0 2006.285.08:14:03.63#ibcon#read 3, iclass 37, count 0 2006.285.08:14:03.63#ibcon#about to read 4, iclass 37, count 0 2006.285.08:14:03.63#ibcon#read 4, iclass 37, count 0 2006.285.08:14:03.63#ibcon#about to read 5, iclass 37, count 0 2006.285.08:14:03.63#ibcon#read 5, iclass 37, count 0 2006.285.08:14:03.63#ibcon#about to read 6, iclass 37, count 0 2006.285.08:14:03.63#ibcon#read 6, iclass 37, count 0 2006.285.08:14:03.63#ibcon#end of sib2, iclass 37, count 0 2006.285.08:14:03.63#ibcon#*mode == 0, iclass 37, count 0 2006.285.08:14:03.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.08:14:03.63#ibcon#[25=BW32\r\n] 2006.285.08:14:03.63#ibcon#*before write, iclass 37, count 0 2006.285.08:14:03.63#ibcon#enter sib2, iclass 37, count 0 2006.285.08:14:03.63#ibcon#flushed, iclass 37, count 0 2006.285.08:14:03.63#ibcon#about to write, iclass 37, count 0 2006.285.08:14:03.63#ibcon#wrote, iclass 37, count 0 2006.285.08:14:03.63#ibcon#about to read 3, iclass 37, count 0 2006.285.08:14:03.66#ibcon#read 3, iclass 37, count 0 2006.285.08:14:03.66#ibcon#about to read 4, iclass 37, count 0 2006.285.08:14:03.66#ibcon#read 4, iclass 37, count 0 2006.285.08:14:03.66#ibcon#about to read 5, iclass 37, count 0 2006.285.08:14:03.66#ibcon#read 5, iclass 37, count 0 2006.285.08:14:03.66#ibcon#about to read 6, iclass 37, count 0 2006.285.08:14:03.66#ibcon#read 6, iclass 37, count 0 2006.285.08:14:03.66#ibcon#end of sib2, iclass 37, count 0 2006.285.08:14:03.66#ibcon#*after write, iclass 37, count 0 2006.285.08:14:03.66#ibcon#*before return 0, iclass 37, count 0 2006.285.08:14:03.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:14:03.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:14:03.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.08:14:03.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.08:14:03.66$vck44/vbbw=wide 2006.285.08:14:03.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.08:14:03.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.08:14:03.67#ibcon#ireg 8 cls_cnt 0 2006.285.08:14:03.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:14:03.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:14:03.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:14:03.72#ibcon#enter wrdev, iclass 39, count 0 2006.285.08:14:03.72#ibcon#first serial, iclass 39, count 0 2006.285.08:14:03.72#ibcon#enter sib2, iclass 39, count 0 2006.285.08:14:03.72#ibcon#flushed, iclass 39, count 0 2006.285.08:14:03.72#ibcon#about to write, iclass 39, count 0 2006.285.08:14:03.72#ibcon#wrote, iclass 39, count 0 2006.285.08:14:03.72#ibcon#about to read 3, iclass 39, count 0 2006.285.08:14:03.74#ibcon#read 3, iclass 39, count 0 2006.285.08:14:03.74#ibcon#about to read 4, iclass 39, count 0 2006.285.08:14:03.74#ibcon#read 4, iclass 39, count 0 2006.285.08:14:03.74#ibcon#about to read 5, iclass 39, count 0 2006.285.08:14:03.74#ibcon#read 5, iclass 39, count 0 2006.285.08:14:03.74#ibcon#about to read 6, iclass 39, count 0 2006.285.08:14:03.74#ibcon#read 6, iclass 39, count 0 2006.285.08:14:03.74#ibcon#end of sib2, iclass 39, count 0 2006.285.08:14:03.74#ibcon#*mode == 0, iclass 39, count 0 2006.285.08:14:03.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.08:14:03.74#ibcon#[27=BW32\r\n] 2006.285.08:14:03.74#ibcon#*before write, iclass 39, count 0 2006.285.08:14:03.74#ibcon#enter sib2, iclass 39, count 0 2006.285.08:14:03.74#ibcon#flushed, iclass 39, count 0 2006.285.08:14:03.74#ibcon#about to write, iclass 39, count 0 2006.285.08:14:03.74#ibcon#wrote, iclass 39, count 0 2006.285.08:14:03.74#ibcon#about to read 3, iclass 39, count 0 2006.285.08:14:03.77#ibcon#read 3, iclass 39, count 0 2006.285.08:14:03.77#ibcon#about to read 4, iclass 39, count 0 2006.285.08:14:03.77#ibcon#read 4, iclass 39, count 0 2006.285.08:14:03.77#ibcon#about to read 5, iclass 39, count 0 2006.285.08:14:03.77#ibcon#read 5, iclass 39, count 0 2006.285.08:14:03.77#ibcon#about to read 6, iclass 39, count 0 2006.285.08:14:03.77#ibcon#read 6, iclass 39, count 0 2006.285.08:14:03.77#ibcon#end of sib2, iclass 39, count 0 2006.285.08:14:03.77#ibcon#*after write, iclass 39, count 0 2006.285.08:14:03.77#ibcon#*before return 0, iclass 39, count 0 2006.285.08:14:03.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:14:03.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:14:03.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.08:14:03.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.08:14:03.78$setupk4/ifdk4 2006.285.08:14:03.78$ifdk4/lo= 2006.285.08:14:03.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:14:03.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:14:03.78$ifdk4/patch= 2006.285.08:14:03.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:14:03.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:14:03.78$setupk4/!*+20s 2006.285.08:14:08.03#abcon#<5=/05 1.9 3.9 22.64 811014.6\r\n> 2006.285.08:14:08.05#abcon#{5=INTERFACE CLEAR} 2006.285.08:14:08.11#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:14:11.13#trakl#Source acquired 2006.285.08:14:12.14#flagr#flagr/antenna,acquired 2006.285.08:14:18.20#abcon#<5=/04 1.9 3.9 22.63 811014.6\r\n> 2006.285.08:14:18.22#abcon#{5=INTERFACE CLEAR} 2006.285.08:14:18.28#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:14:18.44$setupk4/"tpicd 2006.285.08:14:18.44$setupk4/echo=off 2006.285.08:14:18.44$setupk4/xlog=off 2006.285.08:14:18.44:!2006.285.08:16:54 2006.285.08:16:54.00:preob 2006.285.08:16:55.14/onsource/TRACKING 2006.285.08:16:55.14:!2006.285.08:17:04 2006.285.08:17:04.00:"tape 2006.285.08:17:04.00:"st=record 2006.285.08:17:04.00:data_valid=on 2006.285.08:17:04.00:midob 2006.285.08:17:04.14/onsource/TRACKING 2006.285.08:17:04.15/wx/22.55,1014.6,80 2006.285.08:17:04.22/cable/+6.4766E-03 2006.285.08:17:05.31/va/01,07,usb,yes,32,35 2006.285.08:17:05.31/va/02,06,usb,yes,32,32 2006.285.08:17:05.31/va/03,07,usb,yes,32,33 2006.285.08:17:05.31/va/04,06,usb,yes,33,34 2006.285.08:17:05.31/va/05,03,usb,yes,32,33 2006.285.08:17:05.31/va/06,04,usb,yes,29,29 2006.285.08:17:05.31/va/07,04,usb,yes,30,30 2006.285.08:17:05.31/va/08,03,usb,yes,30,37 2006.285.08:17:05.54/valo/01,524.99,yes,locked 2006.285.08:17:05.54/valo/02,534.99,yes,locked 2006.285.08:17:05.54/valo/03,564.99,yes,locked 2006.285.08:17:05.54/valo/04,624.99,yes,locked 2006.285.08:17:05.54/valo/05,734.99,yes,locked 2006.285.08:17:05.54/valo/06,814.99,yes,locked 2006.285.08:17:05.54/valo/07,864.99,yes,locked 2006.285.08:17:05.54/valo/08,884.99,yes,locked 2006.285.08:17:06.63/vb/01,04,usb,yes,30,28 2006.285.08:17:06.63/vb/02,05,usb,yes,29,29 2006.285.08:17:06.63/vb/03,04,usb,yes,30,33 2006.285.08:17:06.63/vb/04,05,usb,yes,30,29 2006.285.08:17:06.63/vb/05,04,usb,yes,26,29 2006.285.08:17:06.63/vb/06,03,usb,yes,38,33 2006.285.08:17:06.63/vb/07,04,usb,yes,30,30 2006.285.08:17:06.63/vb/08,04,usb,yes,28,31 2006.285.08:17:06.86/vblo/01,629.99,yes,locked 2006.285.08:17:06.86/vblo/02,634.99,yes,locked 2006.285.08:17:06.86/vblo/03,649.99,yes,locked 2006.285.08:17:06.86/vblo/04,679.99,yes,locked 2006.285.08:17:06.86/vblo/05,709.99,yes,locked 2006.285.08:17:06.86/vblo/06,719.99,yes,locked 2006.285.08:17:06.86/vblo/07,734.99,yes,locked 2006.285.08:17:06.86/vblo/08,744.99,yes,locked 2006.285.08:17:07.01/vabw/8 2006.285.08:17:07.16/vbbw/8 2006.285.08:17:07.25/xfe/off,on,12.2 2006.285.08:17:07.66/ifatt/23,28,28,28 2006.285.08:17:08.07/fmout-gps/S +2.73E-07 2006.285.08:17:08.09:!2006.285.08:17:44 2006.285.08:17:44.00:data_valid=off 2006.285.08:17:44.00:"et 2006.285.08:17:44.00:!+3s 2006.285.08:17:47.02:"tape 2006.285.08:17:47.02:postob 2006.285.08:17:47.11/cable/+6.4757E-03 2006.285.08:17:47.11/wx/22.53,1014.7,81 2006.285.08:17:47.17/fmout-gps/S +2.75E-07 2006.285.08:17:47.17:scan_name=285-0819,jd0610,50 2006.285.08:17:47.17:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.285.08:17:49.14#flagr#flagr/antenna,new-source 2006.285.08:17:49.14:checkk5 2006.285.08:17:49.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:17:49.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:17:50.35/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:17:50.68/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:17:51.02/chk_obsdata//k5ts1/T2850817??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:17:51.42/chk_obsdata//k5ts2/T2850817??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:17:51.98/chk_obsdata//k5ts3/T2850817??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:17:52.61/chk_obsdata//k5ts4/T2850817??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:17:53.48/k5log//k5ts1_log_newline 2006.285.08:17:54.42/k5log//k5ts2_log_newline 2006.285.08:17:55.18/k5log//k5ts3_log_newline 2006.285.08:17:55.92/k5log//k5ts4_log_newline 2006.285.08:17:55.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:17:55.94:setupk4=1 2006.285.08:17:55.94$setupk4/echo=on 2006.285.08:17:55.94$setupk4/pcalon 2006.285.08:17:55.94$pcalon/"no phase cal control is implemented here 2006.285.08:17:55.94$setupk4/"tpicd=stop 2006.285.08:17:55.94$setupk4/"rec=synch_on 2006.285.08:17:55.94$setupk4/"rec_mode=128 2006.285.08:17:55.94$setupk4/!* 2006.285.08:17:55.94$setupk4/recpk4 2006.285.08:17:55.94$recpk4/recpatch= 2006.285.08:17:55.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:17:55.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:17:55.94$setupk4/vck44 2006.285.08:17:55.94$vck44/valo=1,524.99 2006.285.08:17:55.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.08:17:55.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.08:17:55.94#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:55.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:17:55.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:17:55.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:17:55.94#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:17:55.94#ibcon#first serial, iclass 28, count 0 2006.285.08:17:55.94#ibcon#enter sib2, iclass 28, count 0 2006.285.08:17:55.94#ibcon#flushed, iclass 28, count 0 2006.285.08:17:55.94#ibcon#about to write, iclass 28, count 0 2006.285.08:17:55.94#ibcon#wrote, iclass 28, count 0 2006.285.08:17:55.94#ibcon#about to read 3, iclass 28, count 0 2006.285.08:17:55.95#ibcon#read 3, iclass 28, count 0 2006.285.08:17:55.95#ibcon#about to read 4, iclass 28, count 0 2006.285.08:17:55.95#ibcon#read 4, iclass 28, count 0 2006.285.08:17:55.95#ibcon#about to read 5, iclass 28, count 0 2006.285.08:17:55.95#ibcon#read 5, iclass 28, count 0 2006.285.08:17:55.95#ibcon#about to read 6, iclass 28, count 0 2006.285.08:17:55.95#ibcon#read 6, iclass 28, count 0 2006.285.08:17:55.95#ibcon#end of sib2, iclass 28, count 0 2006.285.08:17:55.95#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:17:55.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:17:55.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:17:55.95#ibcon#*before write, iclass 28, count 0 2006.285.08:17:55.95#ibcon#enter sib2, iclass 28, count 0 2006.285.08:17:55.95#ibcon#flushed, iclass 28, count 0 2006.285.08:17:55.95#ibcon#about to write, iclass 28, count 0 2006.285.08:17:55.95#ibcon#wrote, iclass 28, count 0 2006.285.08:17:55.95#ibcon#about to read 3, iclass 28, count 0 2006.285.08:17:56.00#ibcon#read 3, iclass 28, count 0 2006.285.08:17:56.00#ibcon#about to read 4, iclass 28, count 0 2006.285.08:17:56.00#ibcon#read 4, iclass 28, count 0 2006.285.08:17:56.00#ibcon#about to read 5, iclass 28, count 0 2006.285.08:17:56.00#ibcon#read 5, iclass 28, count 0 2006.285.08:17:56.00#ibcon#about to read 6, iclass 28, count 0 2006.285.08:17:56.00#ibcon#read 6, iclass 28, count 0 2006.285.08:17:56.00#ibcon#end of sib2, iclass 28, count 0 2006.285.08:17:56.00#ibcon#*after write, iclass 28, count 0 2006.285.08:17:56.00#ibcon#*before return 0, iclass 28, count 0 2006.285.08:17:56.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:17:56.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:17:56.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:17:56.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:17:56.00$vck44/va=1,7 2006.285.08:17:56.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.08:17:56.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.08:17:56.00#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:56.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:17:56.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:17:56.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:17:56.00#ibcon#enter wrdev, iclass 30, count 2 2006.285.08:17:56.00#ibcon#first serial, iclass 30, count 2 2006.285.08:17:56.00#ibcon#enter sib2, iclass 30, count 2 2006.285.08:17:56.00#ibcon#flushed, iclass 30, count 2 2006.285.08:17:56.00#ibcon#about to write, iclass 30, count 2 2006.285.08:17:56.00#ibcon#wrote, iclass 30, count 2 2006.285.08:17:56.00#ibcon#about to read 3, iclass 30, count 2 2006.285.08:17:56.02#ibcon#read 3, iclass 30, count 2 2006.285.08:17:56.02#ibcon#about to read 4, iclass 30, count 2 2006.285.08:17:56.02#ibcon#read 4, iclass 30, count 2 2006.285.08:17:56.02#ibcon#about to read 5, iclass 30, count 2 2006.285.08:17:56.02#ibcon#read 5, iclass 30, count 2 2006.285.08:17:56.02#ibcon#about to read 6, iclass 30, count 2 2006.285.08:17:56.02#ibcon#read 6, iclass 30, count 2 2006.285.08:17:56.02#ibcon#end of sib2, iclass 30, count 2 2006.285.08:17:56.02#ibcon#*mode == 0, iclass 30, count 2 2006.285.08:17:56.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.08:17:56.02#ibcon#[25=AT01-07\r\n] 2006.285.08:17:56.02#ibcon#*before write, iclass 30, count 2 2006.285.08:17:56.02#ibcon#enter sib2, iclass 30, count 2 2006.285.08:17:56.02#ibcon#flushed, iclass 30, count 2 2006.285.08:17:56.02#ibcon#about to write, iclass 30, count 2 2006.285.08:17:56.02#ibcon#wrote, iclass 30, count 2 2006.285.08:17:56.02#ibcon#about to read 3, iclass 30, count 2 2006.285.08:17:56.05#ibcon#read 3, iclass 30, count 2 2006.285.08:17:56.05#ibcon#about to read 4, iclass 30, count 2 2006.285.08:17:56.05#ibcon#read 4, iclass 30, count 2 2006.285.08:17:56.05#ibcon#about to read 5, iclass 30, count 2 2006.285.08:17:56.05#ibcon#read 5, iclass 30, count 2 2006.285.08:17:56.05#ibcon#about to read 6, iclass 30, count 2 2006.285.08:17:56.05#ibcon#read 6, iclass 30, count 2 2006.285.08:17:56.05#ibcon#end of sib2, iclass 30, count 2 2006.285.08:17:56.05#ibcon#*after write, iclass 30, count 2 2006.285.08:17:56.05#ibcon#*before return 0, iclass 30, count 2 2006.285.08:17:56.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:17:56.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:17:56.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.08:17:56.05#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:56.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:17:56.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:17:56.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:17:56.17#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:17:56.17#ibcon#first serial, iclass 30, count 0 2006.285.08:17:56.17#ibcon#enter sib2, iclass 30, count 0 2006.285.08:17:56.17#ibcon#flushed, iclass 30, count 0 2006.285.08:17:56.17#ibcon#about to write, iclass 30, count 0 2006.285.08:17:56.17#ibcon#wrote, iclass 30, count 0 2006.285.08:17:56.17#ibcon#about to read 3, iclass 30, count 0 2006.285.08:17:56.19#ibcon#read 3, iclass 30, count 0 2006.285.08:17:56.19#ibcon#about to read 4, iclass 30, count 0 2006.285.08:17:56.19#ibcon#read 4, iclass 30, count 0 2006.285.08:17:56.19#ibcon#about to read 5, iclass 30, count 0 2006.285.08:17:56.19#ibcon#read 5, iclass 30, count 0 2006.285.08:17:56.19#ibcon#about to read 6, iclass 30, count 0 2006.285.08:17:56.19#ibcon#read 6, iclass 30, count 0 2006.285.08:17:56.19#ibcon#end of sib2, iclass 30, count 0 2006.285.08:17:56.19#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:17:56.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:17:56.19#ibcon#[25=USB\r\n] 2006.285.08:17:56.19#ibcon#*before write, iclass 30, count 0 2006.285.08:17:56.19#ibcon#enter sib2, iclass 30, count 0 2006.285.08:17:56.19#ibcon#flushed, iclass 30, count 0 2006.285.08:17:56.19#ibcon#about to write, iclass 30, count 0 2006.285.08:17:56.19#ibcon#wrote, iclass 30, count 0 2006.285.08:17:56.19#ibcon#about to read 3, iclass 30, count 0 2006.285.08:17:56.22#ibcon#read 3, iclass 30, count 0 2006.285.08:17:56.22#ibcon#about to read 4, iclass 30, count 0 2006.285.08:17:56.22#ibcon#read 4, iclass 30, count 0 2006.285.08:17:56.22#ibcon#about to read 5, iclass 30, count 0 2006.285.08:17:56.22#ibcon#read 5, iclass 30, count 0 2006.285.08:17:56.22#ibcon#about to read 6, iclass 30, count 0 2006.285.08:17:56.22#ibcon#read 6, iclass 30, count 0 2006.285.08:17:56.22#ibcon#end of sib2, iclass 30, count 0 2006.285.08:17:56.22#ibcon#*after write, iclass 30, count 0 2006.285.08:17:56.22#ibcon#*before return 0, iclass 30, count 0 2006.285.08:17:56.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:17:56.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:17:56.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:17:56.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:17:56.22$vck44/valo=2,534.99 2006.285.08:17:56.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.08:17:56.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.08:17:56.22#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:56.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:17:56.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:17:56.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:17:56.22#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:17:56.22#ibcon#first serial, iclass 32, count 0 2006.285.08:17:56.22#ibcon#enter sib2, iclass 32, count 0 2006.285.08:17:56.22#ibcon#flushed, iclass 32, count 0 2006.285.08:17:56.22#ibcon#about to write, iclass 32, count 0 2006.285.08:17:56.22#ibcon#wrote, iclass 32, count 0 2006.285.08:17:56.22#ibcon#about to read 3, iclass 32, count 0 2006.285.08:17:56.24#ibcon#read 3, iclass 32, count 0 2006.285.08:17:56.24#ibcon#about to read 4, iclass 32, count 0 2006.285.08:17:56.24#ibcon#read 4, iclass 32, count 0 2006.285.08:17:56.24#ibcon#about to read 5, iclass 32, count 0 2006.285.08:17:56.24#ibcon#read 5, iclass 32, count 0 2006.285.08:17:56.24#ibcon#about to read 6, iclass 32, count 0 2006.285.08:17:56.24#ibcon#read 6, iclass 32, count 0 2006.285.08:17:56.24#ibcon#end of sib2, iclass 32, count 0 2006.285.08:17:56.24#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:17:56.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:17:56.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:17:56.24#ibcon#*before write, iclass 32, count 0 2006.285.08:17:56.24#ibcon#enter sib2, iclass 32, count 0 2006.285.08:17:56.24#ibcon#flushed, iclass 32, count 0 2006.285.08:17:56.24#ibcon#about to write, iclass 32, count 0 2006.285.08:17:56.24#ibcon#wrote, iclass 32, count 0 2006.285.08:17:56.24#ibcon#about to read 3, iclass 32, count 0 2006.285.08:17:56.28#ibcon#read 3, iclass 32, count 0 2006.285.08:17:56.28#ibcon#about to read 4, iclass 32, count 0 2006.285.08:17:56.28#ibcon#read 4, iclass 32, count 0 2006.285.08:17:56.28#ibcon#about to read 5, iclass 32, count 0 2006.285.08:17:56.28#ibcon#read 5, iclass 32, count 0 2006.285.08:17:56.28#ibcon#about to read 6, iclass 32, count 0 2006.285.08:17:56.28#ibcon#read 6, iclass 32, count 0 2006.285.08:17:56.28#ibcon#end of sib2, iclass 32, count 0 2006.285.08:17:56.28#ibcon#*after write, iclass 32, count 0 2006.285.08:17:56.28#ibcon#*before return 0, iclass 32, count 0 2006.285.08:17:56.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:17:56.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:17:56.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:17:56.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:17:56.28$vck44/va=2,6 2006.285.08:17:56.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.08:17:56.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.08:17:56.28#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:56.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:17:56.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:17:56.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:17:56.34#ibcon#enter wrdev, iclass 34, count 2 2006.285.08:17:56.34#ibcon#first serial, iclass 34, count 2 2006.285.08:17:56.34#ibcon#enter sib2, iclass 34, count 2 2006.285.08:17:56.34#ibcon#flushed, iclass 34, count 2 2006.285.08:17:56.34#ibcon#about to write, iclass 34, count 2 2006.285.08:17:56.34#ibcon#wrote, iclass 34, count 2 2006.285.08:17:56.34#ibcon#about to read 3, iclass 34, count 2 2006.285.08:17:56.36#ibcon#read 3, iclass 34, count 2 2006.285.08:17:56.36#ibcon#about to read 4, iclass 34, count 2 2006.285.08:17:56.36#ibcon#read 4, iclass 34, count 2 2006.285.08:17:56.36#ibcon#about to read 5, iclass 34, count 2 2006.285.08:17:56.36#ibcon#read 5, iclass 34, count 2 2006.285.08:17:56.36#ibcon#about to read 6, iclass 34, count 2 2006.285.08:17:56.36#ibcon#read 6, iclass 34, count 2 2006.285.08:17:56.36#ibcon#end of sib2, iclass 34, count 2 2006.285.08:17:56.36#ibcon#*mode == 0, iclass 34, count 2 2006.285.08:17:56.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.08:17:56.36#ibcon#[25=AT02-06\r\n] 2006.285.08:17:56.36#ibcon#*before write, iclass 34, count 2 2006.285.08:17:56.36#ibcon#enter sib2, iclass 34, count 2 2006.285.08:17:56.36#ibcon#flushed, iclass 34, count 2 2006.285.08:17:56.36#ibcon#about to write, iclass 34, count 2 2006.285.08:17:56.36#ibcon#wrote, iclass 34, count 2 2006.285.08:17:56.36#ibcon#about to read 3, iclass 34, count 2 2006.285.08:17:56.39#ibcon#read 3, iclass 34, count 2 2006.285.08:17:56.39#ibcon#about to read 4, iclass 34, count 2 2006.285.08:17:56.39#ibcon#read 4, iclass 34, count 2 2006.285.08:17:56.39#ibcon#about to read 5, iclass 34, count 2 2006.285.08:17:56.39#ibcon#read 5, iclass 34, count 2 2006.285.08:17:56.39#ibcon#about to read 6, iclass 34, count 2 2006.285.08:17:56.39#ibcon#read 6, iclass 34, count 2 2006.285.08:17:56.39#ibcon#end of sib2, iclass 34, count 2 2006.285.08:17:56.39#ibcon#*after write, iclass 34, count 2 2006.285.08:17:56.39#ibcon#*before return 0, iclass 34, count 2 2006.285.08:17:56.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:17:56.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:17:56.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.08:17:56.39#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:56.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:17:56.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:17:56.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:17:56.51#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:17:56.51#ibcon#first serial, iclass 34, count 0 2006.285.08:17:56.51#ibcon#enter sib2, iclass 34, count 0 2006.285.08:17:56.51#ibcon#flushed, iclass 34, count 0 2006.285.08:17:56.51#ibcon#about to write, iclass 34, count 0 2006.285.08:17:56.51#ibcon#wrote, iclass 34, count 0 2006.285.08:17:56.51#ibcon#about to read 3, iclass 34, count 0 2006.285.08:17:56.53#ibcon#read 3, iclass 34, count 0 2006.285.08:17:56.53#ibcon#about to read 4, iclass 34, count 0 2006.285.08:17:56.53#ibcon#read 4, iclass 34, count 0 2006.285.08:17:56.53#ibcon#about to read 5, iclass 34, count 0 2006.285.08:17:56.53#ibcon#read 5, iclass 34, count 0 2006.285.08:17:56.53#ibcon#about to read 6, iclass 34, count 0 2006.285.08:17:56.53#ibcon#read 6, iclass 34, count 0 2006.285.08:17:56.53#ibcon#end of sib2, iclass 34, count 0 2006.285.08:17:56.53#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:17:56.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:17:56.53#ibcon#[25=USB\r\n] 2006.285.08:17:56.53#ibcon#*before write, iclass 34, count 0 2006.285.08:17:56.53#ibcon#enter sib2, iclass 34, count 0 2006.285.08:17:56.53#ibcon#flushed, iclass 34, count 0 2006.285.08:17:56.53#ibcon#about to write, iclass 34, count 0 2006.285.08:17:56.53#ibcon#wrote, iclass 34, count 0 2006.285.08:17:56.53#ibcon#about to read 3, iclass 34, count 0 2006.285.08:17:56.56#ibcon#read 3, iclass 34, count 0 2006.285.08:17:56.56#ibcon#about to read 4, iclass 34, count 0 2006.285.08:17:56.56#ibcon#read 4, iclass 34, count 0 2006.285.08:17:56.56#ibcon#about to read 5, iclass 34, count 0 2006.285.08:17:56.56#ibcon#read 5, iclass 34, count 0 2006.285.08:17:56.56#ibcon#about to read 6, iclass 34, count 0 2006.285.08:17:56.56#ibcon#read 6, iclass 34, count 0 2006.285.08:17:56.56#ibcon#end of sib2, iclass 34, count 0 2006.285.08:17:56.56#ibcon#*after write, iclass 34, count 0 2006.285.08:17:56.56#ibcon#*before return 0, iclass 34, count 0 2006.285.08:17:56.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:17:56.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:17:56.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:17:56.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:17:56.56$vck44/valo=3,564.99 2006.285.08:17:56.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.08:17:56.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.08:17:56.56#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:56.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:17:56.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:17:56.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:17:56.56#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:17:56.56#ibcon#first serial, iclass 36, count 0 2006.285.08:17:56.56#ibcon#enter sib2, iclass 36, count 0 2006.285.08:17:56.56#ibcon#flushed, iclass 36, count 0 2006.285.08:17:56.56#ibcon#about to write, iclass 36, count 0 2006.285.08:17:56.56#ibcon#wrote, iclass 36, count 0 2006.285.08:17:56.56#ibcon#about to read 3, iclass 36, count 0 2006.285.08:17:56.58#ibcon#read 3, iclass 36, count 0 2006.285.08:17:56.58#ibcon#about to read 4, iclass 36, count 0 2006.285.08:17:56.58#ibcon#read 4, iclass 36, count 0 2006.285.08:17:56.58#ibcon#about to read 5, iclass 36, count 0 2006.285.08:17:56.58#ibcon#read 5, iclass 36, count 0 2006.285.08:17:56.58#ibcon#about to read 6, iclass 36, count 0 2006.285.08:17:56.58#ibcon#read 6, iclass 36, count 0 2006.285.08:17:56.58#ibcon#end of sib2, iclass 36, count 0 2006.285.08:17:56.58#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:17:56.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:17:56.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:17:56.58#ibcon#*before write, iclass 36, count 0 2006.285.08:17:56.58#ibcon#enter sib2, iclass 36, count 0 2006.285.08:17:56.58#ibcon#flushed, iclass 36, count 0 2006.285.08:17:56.58#ibcon#about to write, iclass 36, count 0 2006.285.08:17:56.58#ibcon#wrote, iclass 36, count 0 2006.285.08:17:56.58#ibcon#about to read 3, iclass 36, count 0 2006.285.08:17:56.62#ibcon#read 3, iclass 36, count 0 2006.285.08:17:56.62#ibcon#about to read 4, iclass 36, count 0 2006.285.08:17:56.62#ibcon#read 4, iclass 36, count 0 2006.285.08:17:56.62#ibcon#about to read 5, iclass 36, count 0 2006.285.08:17:56.62#ibcon#read 5, iclass 36, count 0 2006.285.08:17:56.62#ibcon#about to read 6, iclass 36, count 0 2006.285.08:17:56.62#ibcon#read 6, iclass 36, count 0 2006.285.08:17:56.62#ibcon#end of sib2, iclass 36, count 0 2006.285.08:17:56.62#ibcon#*after write, iclass 36, count 0 2006.285.08:17:56.62#ibcon#*before return 0, iclass 36, count 0 2006.285.08:17:56.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:17:56.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:17:56.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:17:56.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:17:56.62$vck44/va=3,7 2006.285.08:17:56.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.08:17:56.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.08:17:56.62#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:56.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:17:56.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:17:56.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:17:56.68#ibcon#enter wrdev, iclass 38, count 2 2006.285.08:17:56.68#ibcon#first serial, iclass 38, count 2 2006.285.08:17:56.68#ibcon#enter sib2, iclass 38, count 2 2006.285.08:17:56.68#ibcon#flushed, iclass 38, count 2 2006.285.08:17:56.68#ibcon#about to write, iclass 38, count 2 2006.285.08:17:56.68#ibcon#wrote, iclass 38, count 2 2006.285.08:17:56.68#ibcon#about to read 3, iclass 38, count 2 2006.285.08:17:56.70#ibcon#read 3, iclass 38, count 2 2006.285.08:17:56.70#ibcon#about to read 4, iclass 38, count 2 2006.285.08:17:56.70#ibcon#read 4, iclass 38, count 2 2006.285.08:17:56.70#ibcon#about to read 5, iclass 38, count 2 2006.285.08:17:56.70#ibcon#read 5, iclass 38, count 2 2006.285.08:17:56.70#ibcon#about to read 6, iclass 38, count 2 2006.285.08:17:56.70#ibcon#read 6, iclass 38, count 2 2006.285.08:17:56.70#ibcon#end of sib2, iclass 38, count 2 2006.285.08:17:56.70#ibcon#*mode == 0, iclass 38, count 2 2006.285.08:17:56.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.08:17:56.70#ibcon#[25=AT03-07\r\n] 2006.285.08:17:56.70#ibcon#*before write, iclass 38, count 2 2006.285.08:17:56.70#ibcon#enter sib2, iclass 38, count 2 2006.285.08:17:56.70#ibcon#flushed, iclass 38, count 2 2006.285.08:17:56.70#ibcon#about to write, iclass 38, count 2 2006.285.08:17:56.70#ibcon#wrote, iclass 38, count 2 2006.285.08:17:56.70#ibcon#about to read 3, iclass 38, count 2 2006.285.08:17:56.73#ibcon#read 3, iclass 38, count 2 2006.285.08:17:56.73#ibcon#about to read 4, iclass 38, count 2 2006.285.08:17:56.73#ibcon#read 4, iclass 38, count 2 2006.285.08:17:56.73#ibcon#about to read 5, iclass 38, count 2 2006.285.08:17:56.73#ibcon#read 5, iclass 38, count 2 2006.285.08:17:56.73#ibcon#about to read 6, iclass 38, count 2 2006.285.08:17:56.73#ibcon#read 6, iclass 38, count 2 2006.285.08:17:56.73#ibcon#end of sib2, iclass 38, count 2 2006.285.08:17:56.73#ibcon#*after write, iclass 38, count 2 2006.285.08:17:56.73#ibcon#*before return 0, iclass 38, count 2 2006.285.08:17:56.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:17:56.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:17:56.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.08:17:56.73#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:56.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:17:56.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:17:56.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:17:56.85#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:17:56.85#ibcon#first serial, iclass 38, count 0 2006.285.08:17:56.85#ibcon#enter sib2, iclass 38, count 0 2006.285.08:17:56.85#ibcon#flushed, iclass 38, count 0 2006.285.08:17:56.85#ibcon#about to write, iclass 38, count 0 2006.285.08:17:56.85#ibcon#wrote, iclass 38, count 0 2006.285.08:17:56.85#ibcon#about to read 3, iclass 38, count 0 2006.285.08:17:56.87#ibcon#read 3, iclass 38, count 0 2006.285.08:17:56.87#ibcon#about to read 4, iclass 38, count 0 2006.285.08:17:56.87#ibcon#read 4, iclass 38, count 0 2006.285.08:17:56.87#ibcon#about to read 5, iclass 38, count 0 2006.285.08:17:56.87#ibcon#read 5, iclass 38, count 0 2006.285.08:17:56.87#ibcon#about to read 6, iclass 38, count 0 2006.285.08:17:56.87#ibcon#read 6, iclass 38, count 0 2006.285.08:17:56.87#ibcon#end of sib2, iclass 38, count 0 2006.285.08:17:56.87#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:17:56.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:17:56.87#ibcon#[25=USB\r\n] 2006.285.08:17:56.87#ibcon#*before write, iclass 38, count 0 2006.285.08:17:56.87#ibcon#enter sib2, iclass 38, count 0 2006.285.08:17:56.87#ibcon#flushed, iclass 38, count 0 2006.285.08:17:56.87#ibcon#about to write, iclass 38, count 0 2006.285.08:17:56.87#ibcon#wrote, iclass 38, count 0 2006.285.08:17:56.87#ibcon#about to read 3, iclass 38, count 0 2006.285.08:17:56.90#ibcon#read 3, iclass 38, count 0 2006.285.08:17:56.90#ibcon#about to read 4, iclass 38, count 0 2006.285.08:17:56.90#ibcon#read 4, iclass 38, count 0 2006.285.08:17:56.90#ibcon#about to read 5, iclass 38, count 0 2006.285.08:17:56.90#ibcon#read 5, iclass 38, count 0 2006.285.08:17:56.90#ibcon#about to read 6, iclass 38, count 0 2006.285.08:17:56.90#ibcon#read 6, iclass 38, count 0 2006.285.08:17:56.90#ibcon#end of sib2, iclass 38, count 0 2006.285.08:17:56.90#ibcon#*after write, iclass 38, count 0 2006.285.08:17:56.90#ibcon#*before return 0, iclass 38, count 0 2006.285.08:17:56.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:17:56.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:17:56.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:17:56.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:17:56.90$vck44/valo=4,624.99 2006.285.08:17:56.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.08:17:56.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.08:17:56.90#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:56.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:17:56.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:17:56.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:17:56.90#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:17:56.90#ibcon#first serial, iclass 40, count 0 2006.285.08:17:56.90#ibcon#enter sib2, iclass 40, count 0 2006.285.08:17:56.90#ibcon#flushed, iclass 40, count 0 2006.285.08:17:56.90#ibcon#about to write, iclass 40, count 0 2006.285.08:17:56.90#ibcon#wrote, iclass 40, count 0 2006.285.08:17:56.90#ibcon#about to read 3, iclass 40, count 0 2006.285.08:17:56.92#ibcon#read 3, iclass 40, count 0 2006.285.08:17:56.92#ibcon#about to read 4, iclass 40, count 0 2006.285.08:17:56.92#ibcon#read 4, iclass 40, count 0 2006.285.08:17:56.92#ibcon#about to read 5, iclass 40, count 0 2006.285.08:17:56.92#ibcon#read 5, iclass 40, count 0 2006.285.08:17:56.92#ibcon#about to read 6, iclass 40, count 0 2006.285.08:17:56.92#ibcon#read 6, iclass 40, count 0 2006.285.08:17:56.92#ibcon#end of sib2, iclass 40, count 0 2006.285.08:17:56.92#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:17:56.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:17:56.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:17:56.92#ibcon#*before write, iclass 40, count 0 2006.285.08:17:56.92#ibcon#enter sib2, iclass 40, count 0 2006.285.08:17:56.92#ibcon#flushed, iclass 40, count 0 2006.285.08:17:56.92#ibcon#about to write, iclass 40, count 0 2006.285.08:17:56.92#ibcon#wrote, iclass 40, count 0 2006.285.08:17:56.92#ibcon#about to read 3, iclass 40, count 0 2006.285.08:17:56.96#ibcon#read 3, iclass 40, count 0 2006.285.08:17:56.96#ibcon#about to read 4, iclass 40, count 0 2006.285.08:17:56.96#ibcon#read 4, iclass 40, count 0 2006.285.08:17:56.96#ibcon#about to read 5, iclass 40, count 0 2006.285.08:17:56.96#ibcon#read 5, iclass 40, count 0 2006.285.08:17:56.96#ibcon#about to read 6, iclass 40, count 0 2006.285.08:17:56.96#ibcon#read 6, iclass 40, count 0 2006.285.08:17:56.96#ibcon#end of sib2, iclass 40, count 0 2006.285.08:17:56.96#ibcon#*after write, iclass 40, count 0 2006.285.08:17:56.96#ibcon#*before return 0, iclass 40, count 0 2006.285.08:17:56.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:17:56.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:17:56.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:17:56.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:17:56.96$vck44/va=4,6 2006.285.08:17:56.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.08:17:56.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.08:17:56.96#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:56.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:17:57.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:17:57.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:17:57.02#ibcon#enter wrdev, iclass 4, count 2 2006.285.08:17:57.02#ibcon#first serial, iclass 4, count 2 2006.285.08:17:57.02#ibcon#enter sib2, iclass 4, count 2 2006.285.08:17:57.02#ibcon#flushed, iclass 4, count 2 2006.285.08:17:57.02#ibcon#about to write, iclass 4, count 2 2006.285.08:17:57.02#ibcon#wrote, iclass 4, count 2 2006.285.08:17:57.02#ibcon#about to read 3, iclass 4, count 2 2006.285.08:17:57.04#ibcon#read 3, iclass 4, count 2 2006.285.08:17:57.04#ibcon#about to read 4, iclass 4, count 2 2006.285.08:17:57.04#ibcon#read 4, iclass 4, count 2 2006.285.08:17:57.04#ibcon#about to read 5, iclass 4, count 2 2006.285.08:17:57.04#ibcon#read 5, iclass 4, count 2 2006.285.08:17:57.04#ibcon#about to read 6, iclass 4, count 2 2006.285.08:17:57.04#ibcon#read 6, iclass 4, count 2 2006.285.08:17:57.04#ibcon#end of sib2, iclass 4, count 2 2006.285.08:17:57.04#ibcon#*mode == 0, iclass 4, count 2 2006.285.08:17:57.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.08:17:57.04#ibcon#[25=AT04-06\r\n] 2006.285.08:17:57.04#ibcon#*before write, iclass 4, count 2 2006.285.08:17:57.04#ibcon#enter sib2, iclass 4, count 2 2006.285.08:17:57.04#ibcon#flushed, iclass 4, count 2 2006.285.08:17:57.04#ibcon#about to write, iclass 4, count 2 2006.285.08:17:57.04#ibcon#wrote, iclass 4, count 2 2006.285.08:17:57.04#ibcon#about to read 3, iclass 4, count 2 2006.285.08:17:57.07#ibcon#read 3, iclass 4, count 2 2006.285.08:17:57.07#ibcon#about to read 4, iclass 4, count 2 2006.285.08:17:57.07#ibcon#read 4, iclass 4, count 2 2006.285.08:17:57.07#ibcon#about to read 5, iclass 4, count 2 2006.285.08:17:57.07#ibcon#read 5, iclass 4, count 2 2006.285.08:17:57.07#ibcon#about to read 6, iclass 4, count 2 2006.285.08:17:57.07#ibcon#read 6, iclass 4, count 2 2006.285.08:17:57.07#ibcon#end of sib2, iclass 4, count 2 2006.285.08:17:57.07#ibcon#*after write, iclass 4, count 2 2006.285.08:17:57.07#ibcon#*before return 0, iclass 4, count 2 2006.285.08:17:57.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:17:57.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:17:57.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.08:17:57.07#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:57.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:17:57.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:17:57.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:17:57.19#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:17:57.19#ibcon#first serial, iclass 4, count 0 2006.285.08:17:57.19#ibcon#enter sib2, iclass 4, count 0 2006.285.08:17:57.19#ibcon#flushed, iclass 4, count 0 2006.285.08:17:57.19#ibcon#about to write, iclass 4, count 0 2006.285.08:17:57.19#ibcon#wrote, iclass 4, count 0 2006.285.08:17:57.19#ibcon#about to read 3, iclass 4, count 0 2006.285.08:17:57.21#ibcon#read 3, iclass 4, count 0 2006.285.08:17:57.21#ibcon#about to read 4, iclass 4, count 0 2006.285.08:17:57.21#ibcon#read 4, iclass 4, count 0 2006.285.08:17:57.21#ibcon#about to read 5, iclass 4, count 0 2006.285.08:17:57.21#ibcon#read 5, iclass 4, count 0 2006.285.08:17:57.21#ibcon#about to read 6, iclass 4, count 0 2006.285.08:17:57.21#ibcon#read 6, iclass 4, count 0 2006.285.08:17:57.21#ibcon#end of sib2, iclass 4, count 0 2006.285.08:17:57.21#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:17:57.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:17:57.21#ibcon#[25=USB\r\n] 2006.285.08:17:57.21#ibcon#*before write, iclass 4, count 0 2006.285.08:17:57.21#ibcon#enter sib2, iclass 4, count 0 2006.285.08:17:57.21#ibcon#flushed, iclass 4, count 0 2006.285.08:17:57.21#ibcon#about to write, iclass 4, count 0 2006.285.08:17:57.21#ibcon#wrote, iclass 4, count 0 2006.285.08:17:57.21#ibcon#about to read 3, iclass 4, count 0 2006.285.08:17:57.24#ibcon#read 3, iclass 4, count 0 2006.285.08:17:57.24#ibcon#about to read 4, iclass 4, count 0 2006.285.08:17:57.24#ibcon#read 4, iclass 4, count 0 2006.285.08:17:57.24#ibcon#about to read 5, iclass 4, count 0 2006.285.08:17:57.24#ibcon#read 5, iclass 4, count 0 2006.285.08:17:57.24#ibcon#about to read 6, iclass 4, count 0 2006.285.08:17:57.24#ibcon#read 6, iclass 4, count 0 2006.285.08:17:57.24#ibcon#end of sib2, iclass 4, count 0 2006.285.08:17:57.24#ibcon#*after write, iclass 4, count 0 2006.285.08:17:57.24#ibcon#*before return 0, iclass 4, count 0 2006.285.08:17:57.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:17:57.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:17:57.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:17:57.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:17:57.24$vck44/valo=5,734.99 2006.285.08:17:57.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.08:17:57.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.08:17:57.24#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:57.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:17:57.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:17:57.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:17:57.24#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:17:57.24#ibcon#first serial, iclass 6, count 0 2006.285.08:17:57.24#ibcon#enter sib2, iclass 6, count 0 2006.285.08:17:57.24#ibcon#flushed, iclass 6, count 0 2006.285.08:17:57.24#ibcon#about to write, iclass 6, count 0 2006.285.08:17:57.24#ibcon#wrote, iclass 6, count 0 2006.285.08:17:57.24#ibcon#about to read 3, iclass 6, count 0 2006.285.08:17:57.26#ibcon#read 3, iclass 6, count 0 2006.285.08:17:57.26#ibcon#about to read 4, iclass 6, count 0 2006.285.08:17:57.26#ibcon#read 4, iclass 6, count 0 2006.285.08:17:57.26#ibcon#about to read 5, iclass 6, count 0 2006.285.08:17:57.26#ibcon#read 5, iclass 6, count 0 2006.285.08:17:57.26#ibcon#about to read 6, iclass 6, count 0 2006.285.08:17:57.26#ibcon#read 6, iclass 6, count 0 2006.285.08:17:57.26#ibcon#end of sib2, iclass 6, count 0 2006.285.08:17:57.26#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:17:57.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:17:57.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:17:57.26#ibcon#*before write, iclass 6, count 0 2006.285.08:17:57.26#ibcon#enter sib2, iclass 6, count 0 2006.285.08:17:57.26#ibcon#flushed, iclass 6, count 0 2006.285.08:17:57.26#ibcon#about to write, iclass 6, count 0 2006.285.08:17:57.26#ibcon#wrote, iclass 6, count 0 2006.285.08:17:57.26#ibcon#about to read 3, iclass 6, count 0 2006.285.08:17:57.30#ibcon#read 3, iclass 6, count 0 2006.285.08:17:57.30#ibcon#about to read 4, iclass 6, count 0 2006.285.08:17:57.30#ibcon#read 4, iclass 6, count 0 2006.285.08:17:57.30#ibcon#about to read 5, iclass 6, count 0 2006.285.08:17:57.30#ibcon#read 5, iclass 6, count 0 2006.285.08:17:57.30#ibcon#about to read 6, iclass 6, count 0 2006.285.08:17:57.30#ibcon#read 6, iclass 6, count 0 2006.285.08:17:57.30#ibcon#end of sib2, iclass 6, count 0 2006.285.08:17:57.30#ibcon#*after write, iclass 6, count 0 2006.285.08:17:57.30#ibcon#*before return 0, iclass 6, count 0 2006.285.08:17:57.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:17:57.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:17:57.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:17:57.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:17:57.30$vck44/va=5,3 2006.285.08:17:57.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.08:17:57.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.08:17:57.30#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:57.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:17:57.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:17:57.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:17:57.36#ibcon#enter wrdev, iclass 10, count 2 2006.285.08:17:57.36#ibcon#first serial, iclass 10, count 2 2006.285.08:17:57.36#ibcon#enter sib2, iclass 10, count 2 2006.285.08:17:57.36#ibcon#flushed, iclass 10, count 2 2006.285.08:17:57.36#ibcon#about to write, iclass 10, count 2 2006.285.08:17:57.36#ibcon#wrote, iclass 10, count 2 2006.285.08:17:57.36#ibcon#about to read 3, iclass 10, count 2 2006.285.08:17:57.38#ibcon#read 3, iclass 10, count 2 2006.285.08:17:57.38#ibcon#about to read 4, iclass 10, count 2 2006.285.08:17:57.38#ibcon#read 4, iclass 10, count 2 2006.285.08:17:57.38#ibcon#about to read 5, iclass 10, count 2 2006.285.08:17:57.38#ibcon#read 5, iclass 10, count 2 2006.285.08:17:57.38#ibcon#about to read 6, iclass 10, count 2 2006.285.08:17:57.38#ibcon#read 6, iclass 10, count 2 2006.285.08:17:57.38#ibcon#end of sib2, iclass 10, count 2 2006.285.08:17:57.38#ibcon#*mode == 0, iclass 10, count 2 2006.285.08:17:57.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.08:17:57.38#ibcon#[25=AT05-03\r\n] 2006.285.08:17:57.38#ibcon#*before write, iclass 10, count 2 2006.285.08:17:57.38#ibcon#enter sib2, iclass 10, count 2 2006.285.08:17:57.38#ibcon#flushed, iclass 10, count 2 2006.285.08:17:57.38#ibcon#about to write, iclass 10, count 2 2006.285.08:17:57.38#ibcon#wrote, iclass 10, count 2 2006.285.08:17:57.38#ibcon#about to read 3, iclass 10, count 2 2006.285.08:17:57.41#ibcon#read 3, iclass 10, count 2 2006.285.08:17:57.41#ibcon#about to read 4, iclass 10, count 2 2006.285.08:17:57.41#ibcon#read 4, iclass 10, count 2 2006.285.08:17:57.41#ibcon#about to read 5, iclass 10, count 2 2006.285.08:17:57.41#ibcon#read 5, iclass 10, count 2 2006.285.08:17:57.41#ibcon#about to read 6, iclass 10, count 2 2006.285.08:17:57.41#ibcon#read 6, iclass 10, count 2 2006.285.08:17:57.41#ibcon#end of sib2, iclass 10, count 2 2006.285.08:17:57.41#ibcon#*after write, iclass 10, count 2 2006.285.08:17:57.41#ibcon#*before return 0, iclass 10, count 2 2006.285.08:17:57.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:17:57.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:17:57.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.08:17:57.41#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:57.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:17:57.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:17:57.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:17:57.53#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:17:57.53#ibcon#first serial, iclass 10, count 0 2006.285.08:17:57.53#ibcon#enter sib2, iclass 10, count 0 2006.285.08:17:57.53#ibcon#flushed, iclass 10, count 0 2006.285.08:17:57.53#ibcon#about to write, iclass 10, count 0 2006.285.08:17:57.53#ibcon#wrote, iclass 10, count 0 2006.285.08:17:57.53#ibcon#about to read 3, iclass 10, count 0 2006.285.08:17:57.55#ibcon#read 3, iclass 10, count 0 2006.285.08:17:57.55#ibcon#about to read 4, iclass 10, count 0 2006.285.08:17:57.55#ibcon#read 4, iclass 10, count 0 2006.285.08:17:57.55#ibcon#about to read 5, iclass 10, count 0 2006.285.08:17:57.55#ibcon#read 5, iclass 10, count 0 2006.285.08:17:57.55#ibcon#about to read 6, iclass 10, count 0 2006.285.08:17:57.55#ibcon#read 6, iclass 10, count 0 2006.285.08:17:57.55#ibcon#end of sib2, iclass 10, count 0 2006.285.08:17:57.55#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:17:57.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:17:57.55#ibcon#[25=USB\r\n] 2006.285.08:17:57.55#ibcon#*before write, iclass 10, count 0 2006.285.08:17:57.55#ibcon#enter sib2, iclass 10, count 0 2006.285.08:17:57.55#ibcon#flushed, iclass 10, count 0 2006.285.08:17:57.55#ibcon#about to write, iclass 10, count 0 2006.285.08:17:57.55#ibcon#wrote, iclass 10, count 0 2006.285.08:17:57.55#ibcon#about to read 3, iclass 10, count 0 2006.285.08:17:57.58#ibcon#read 3, iclass 10, count 0 2006.285.08:17:57.58#ibcon#about to read 4, iclass 10, count 0 2006.285.08:17:57.58#ibcon#read 4, iclass 10, count 0 2006.285.08:17:57.58#ibcon#about to read 5, iclass 10, count 0 2006.285.08:17:57.58#ibcon#read 5, iclass 10, count 0 2006.285.08:17:57.58#ibcon#about to read 6, iclass 10, count 0 2006.285.08:17:57.58#ibcon#read 6, iclass 10, count 0 2006.285.08:17:57.58#ibcon#end of sib2, iclass 10, count 0 2006.285.08:17:57.58#ibcon#*after write, iclass 10, count 0 2006.285.08:17:57.58#ibcon#*before return 0, iclass 10, count 0 2006.285.08:17:57.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:17:57.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:17:57.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:17:57.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:17:57.58$vck44/valo=6,814.99 2006.285.08:17:57.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.08:17:57.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.08:17:57.58#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:57.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:17:57.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:17:57.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:17:57.58#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:17:57.58#ibcon#first serial, iclass 12, count 0 2006.285.08:17:57.58#ibcon#enter sib2, iclass 12, count 0 2006.285.08:17:57.58#ibcon#flushed, iclass 12, count 0 2006.285.08:17:57.58#ibcon#about to write, iclass 12, count 0 2006.285.08:17:57.58#ibcon#wrote, iclass 12, count 0 2006.285.08:17:57.58#ibcon#about to read 3, iclass 12, count 0 2006.285.08:17:57.60#ibcon#read 3, iclass 12, count 0 2006.285.08:17:57.60#ibcon#about to read 4, iclass 12, count 0 2006.285.08:17:57.60#ibcon#read 4, iclass 12, count 0 2006.285.08:17:57.60#ibcon#about to read 5, iclass 12, count 0 2006.285.08:17:57.60#ibcon#read 5, iclass 12, count 0 2006.285.08:17:57.60#ibcon#about to read 6, iclass 12, count 0 2006.285.08:17:57.60#ibcon#read 6, iclass 12, count 0 2006.285.08:17:57.60#ibcon#end of sib2, iclass 12, count 0 2006.285.08:17:57.60#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:17:57.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:17:57.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:17:57.60#ibcon#*before write, iclass 12, count 0 2006.285.08:17:57.60#ibcon#enter sib2, iclass 12, count 0 2006.285.08:17:57.60#ibcon#flushed, iclass 12, count 0 2006.285.08:17:57.60#ibcon#about to write, iclass 12, count 0 2006.285.08:17:57.60#ibcon#wrote, iclass 12, count 0 2006.285.08:17:57.60#ibcon#about to read 3, iclass 12, count 0 2006.285.08:17:57.64#ibcon#read 3, iclass 12, count 0 2006.285.08:17:57.64#ibcon#about to read 4, iclass 12, count 0 2006.285.08:17:57.64#ibcon#read 4, iclass 12, count 0 2006.285.08:17:57.64#ibcon#about to read 5, iclass 12, count 0 2006.285.08:17:57.64#ibcon#read 5, iclass 12, count 0 2006.285.08:17:57.64#ibcon#about to read 6, iclass 12, count 0 2006.285.08:17:57.64#ibcon#read 6, iclass 12, count 0 2006.285.08:17:57.64#ibcon#end of sib2, iclass 12, count 0 2006.285.08:17:57.64#ibcon#*after write, iclass 12, count 0 2006.285.08:17:57.64#ibcon#*before return 0, iclass 12, count 0 2006.285.08:17:57.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:17:57.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:17:57.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:17:57.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:17:57.64$vck44/va=6,4 2006.285.08:17:57.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.08:17:57.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.08:17:57.64#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:57.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:17:57.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:17:57.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:17:57.70#ibcon#enter wrdev, iclass 14, count 2 2006.285.08:17:57.70#ibcon#first serial, iclass 14, count 2 2006.285.08:17:57.70#ibcon#enter sib2, iclass 14, count 2 2006.285.08:17:57.70#ibcon#flushed, iclass 14, count 2 2006.285.08:17:57.70#ibcon#about to write, iclass 14, count 2 2006.285.08:17:57.70#ibcon#wrote, iclass 14, count 2 2006.285.08:17:57.70#ibcon#about to read 3, iclass 14, count 2 2006.285.08:17:57.72#ibcon#read 3, iclass 14, count 2 2006.285.08:17:57.72#ibcon#about to read 4, iclass 14, count 2 2006.285.08:17:57.72#ibcon#read 4, iclass 14, count 2 2006.285.08:17:57.72#ibcon#about to read 5, iclass 14, count 2 2006.285.08:17:57.72#ibcon#read 5, iclass 14, count 2 2006.285.08:17:57.72#ibcon#about to read 6, iclass 14, count 2 2006.285.08:17:57.72#ibcon#read 6, iclass 14, count 2 2006.285.08:17:57.72#ibcon#end of sib2, iclass 14, count 2 2006.285.08:17:57.72#ibcon#*mode == 0, iclass 14, count 2 2006.285.08:17:57.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.08:17:57.72#ibcon#[25=AT06-04\r\n] 2006.285.08:17:57.72#ibcon#*before write, iclass 14, count 2 2006.285.08:17:57.72#ibcon#enter sib2, iclass 14, count 2 2006.285.08:17:57.72#ibcon#flushed, iclass 14, count 2 2006.285.08:17:57.72#ibcon#about to write, iclass 14, count 2 2006.285.08:17:57.72#ibcon#wrote, iclass 14, count 2 2006.285.08:17:57.72#ibcon#about to read 3, iclass 14, count 2 2006.285.08:17:57.75#ibcon#read 3, iclass 14, count 2 2006.285.08:17:57.75#ibcon#about to read 4, iclass 14, count 2 2006.285.08:17:57.75#ibcon#read 4, iclass 14, count 2 2006.285.08:17:57.75#ibcon#about to read 5, iclass 14, count 2 2006.285.08:17:57.75#ibcon#read 5, iclass 14, count 2 2006.285.08:17:57.75#ibcon#about to read 6, iclass 14, count 2 2006.285.08:17:57.75#ibcon#read 6, iclass 14, count 2 2006.285.08:17:57.75#ibcon#end of sib2, iclass 14, count 2 2006.285.08:17:57.75#ibcon#*after write, iclass 14, count 2 2006.285.08:17:57.75#ibcon#*before return 0, iclass 14, count 2 2006.285.08:17:57.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:17:57.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:17:57.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.08:17:57.75#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:57.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:17:57.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:17:57.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:17:57.87#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:17:57.87#ibcon#first serial, iclass 14, count 0 2006.285.08:17:57.87#ibcon#enter sib2, iclass 14, count 0 2006.285.08:17:57.87#ibcon#flushed, iclass 14, count 0 2006.285.08:17:57.87#ibcon#about to write, iclass 14, count 0 2006.285.08:17:57.87#ibcon#wrote, iclass 14, count 0 2006.285.08:17:57.87#ibcon#about to read 3, iclass 14, count 0 2006.285.08:17:57.89#ibcon#read 3, iclass 14, count 0 2006.285.08:17:57.89#ibcon#about to read 4, iclass 14, count 0 2006.285.08:17:57.89#ibcon#read 4, iclass 14, count 0 2006.285.08:17:57.89#ibcon#about to read 5, iclass 14, count 0 2006.285.08:17:57.89#ibcon#read 5, iclass 14, count 0 2006.285.08:17:57.89#ibcon#about to read 6, iclass 14, count 0 2006.285.08:17:57.89#ibcon#read 6, iclass 14, count 0 2006.285.08:17:57.89#ibcon#end of sib2, iclass 14, count 0 2006.285.08:17:57.89#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:17:57.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:17:57.89#ibcon#[25=USB\r\n] 2006.285.08:17:57.89#ibcon#*before write, iclass 14, count 0 2006.285.08:17:57.89#ibcon#enter sib2, iclass 14, count 0 2006.285.08:17:57.89#ibcon#flushed, iclass 14, count 0 2006.285.08:17:57.89#ibcon#about to write, iclass 14, count 0 2006.285.08:17:57.89#ibcon#wrote, iclass 14, count 0 2006.285.08:17:57.89#ibcon#about to read 3, iclass 14, count 0 2006.285.08:17:57.92#ibcon#read 3, iclass 14, count 0 2006.285.08:17:57.92#ibcon#about to read 4, iclass 14, count 0 2006.285.08:17:57.92#ibcon#read 4, iclass 14, count 0 2006.285.08:17:57.92#ibcon#about to read 5, iclass 14, count 0 2006.285.08:17:57.92#ibcon#read 5, iclass 14, count 0 2006.285.08:17:57.92#ibcon#about to read 6, iclass 14, count 0 2006.285.08:17:57.92#ibcon#read 6, iclass 14, count 0 2006.285.08:17:57.92#ibcon#end of sib2, iclass 14, count 0 2006.285.08:17:57.92#ibcon#*after write, iclass 14, count 0 2006.285.08:17:57.92#ibcon#*before return 0, iclass 14, count 0 2006.285.08:17:57.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:17:57.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:17:57.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:17:57.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:17:57.92$vck44/valo=7,864.99 2006.285.08:17:57.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.08:17:57.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.08:17:57.92#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:57.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:17:57.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:17:57.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:17:57.92#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:17:57.92#ibcon#first serial, iclass 16, count 0 2006.285.08:17:57.92#ibcon#enter sib2, iclass 16, count 0 2006.285.08:17:57.92#ibcon#flushed, iclass 16, count 0 2006.285.08:17:57.92#ibcon#about to write, iclass 16, count 0 2006.285.08:17:57.92#ibcon#wrote, iclass 16, count 0 2006.285.08:17:57.92#ibcon#about to read 3, iclass 16, count 0 2006.285.08:17:57.94#ibcon#read 3, iclass 16, count 0 2006.285.08:17:57.94#ibcon#about to read 4, iclass 16, count 0 2006.285.08:17:57.94#ibcon#read 4, iclass 16, count 0 2006.285.08:17:57.94#ibcon#about to read 5, iclass 16, count 0 2006.285.08:17:57.94#ibcon#read 5, iclass 16, count 0 2006.285.08:17:57.94#ibcon#about to read 6, iclass 16, count 0 2006.285.08:17:57.94#ibcon#read 6, iclass 16, count 0 2006.285.08:17:57.94#ibcon#end of sib2, iclass 16, count 0 2006.285.08:17:57.94#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:17:57.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:17:57.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:17:57.94#ibcon#*before write, iclass 16, count 0 2006.285.08:17:57.94#ibcon#enter sib2, iclass 16, count 0 2006.285.08:17:57.94#ibcon#flushed, iclass 16, count 0 2006.285.08:17:57.94#ibcon#about to write, iclass 16, count 0 2006.285.08:17:57.94#ibcon#wrote, iclass 16, count 0 2006.285.08:17:57.94#ibcon#about to read 3, iclass 16, count 0 2006.285.08:17:57.98#ibcon#read 3, iclass 16, count 0 2006.285.08:17:57.98#ibcon#about to read 4, iclass 16, count 0 2006.285.08:17:57.98#ibcon#read 4, iclass 16, count 0 2006.285.08:17:57.98#ibcon#about to read 5, iclass 16, count 0 2006.285.08:17:57.98#ibcon#read 5, iclass 16, count 0 2006.285.08:17:57.98#ibcon#about to read 6, iclass 16, count 0 2006.285.08:17:57.98#ibcon#read 6, iclass 16, count 0 2006.285.08:17:57.98#ibcon#end of sib2, iclass 16, count 0 2006.285.08:17:57.98#ibcon#*after write, iclass 16, count 0 2006.285.08:17:57.98#ibcon#*before return 0, iclass 16, count 0 2006.285.08:17:57.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:17:57.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:17:57.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:17:57.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:17:57.98$vck44/va=7,4 2006.285.08:17:57.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.08:17:57.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.08:17:57.98#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:57.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:17:58.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:17:58.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:17:58.04#ibcon#enter wrdev, iclass 18, count 2 2006.285.08:17:58.04#ibcon#first serial, iclass 18, count 2 2006.285.08:17:58.04#ibcon#enter sib2, iclass 18, count 2 2006.285.08:17:58.04#ibcon#flushed, iclass 18, count 2 2006.285.08:17:58.04#ibcon#about to write, iclass 18, count 2 2006.285.08:17:58.04#ibcon#wrote, iclass 18, count 2 2006.285.08:17:58.04#ibcon#about to read 3, iclass 18, count 2 2006.285.08:17:58.06#ibcon#read 3, iclass 18, count 2 2006.285.08:17:58.06#ibcon#about to read 4, iclass 18, count 2 2006.285.08:17:58.06#ibcon#read 4, iclass 18, count 2 2006.285.08:17:58.06#ibcon#about to read 5, iclass 18, count 2 2006.285.08:17:58.06#ibcon#read 5, iclass 18, count 2 2006.285.08:17:58.06#ibcon#about to read 6, iclass 18, count 2 2006.285.08:17:58.06#ibcon#read 6, iclass 18, count 2 2006.285.08:17:58.06#ibcon#end of sib2, iclass 18, count 2 2006.285.08:17:58.06#ibcon#*mode == 0, iclass 18, count 2 2006.285.08:17:58.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.08:17:58.06#ibcon#[25=AT07-04\r\n] 2006.285.08:17:58.06#ibcon#*before write, iclass 18, count 2 2006.285.08:17:58.06#ibcon#enter sib2, iclass 18, count 2 2006.285.08:17:58.06#ibcon#flushed, iclass 18, count 2 2006.285.08:17:58.06#ibcon#about to write, iclass 18, count 2 2006.285.08:17:58.06#ibcon#wrote, iclass 18, count 2 2006.285.08:17:58.06#ibcon#about to read 3, iclass 18, count 2 2006.285.08:17:58.09#ibcon#read 3, iclass 18, count 2 2006.285.08:17:58.09#ibcon#about to read 4, iclass 18, count 2 2006.285.08:17:58.09#ibcon#read 4, iclass 18, count 2 2006.285.08:17:58.09#ibcon#about to read 5, iclass 18, count 2 2006.285.08:17:58.09#ibcon#read 5, iclass 18, count 2 2006.285.08:17:58.09#ibcon#about to read 6, iclass 18, count 2 2006.285.08:17:58.09#ibcon#read 6, iclass 18, count 2 2006.285.08:17:58.09#ibcon#end of sib2, iclass 18, count 2 2006.285.08:17:58.09#ibcon#*after write, iclass 18, count 2 2006.285.08:17:58.09#ibcon#*before return 0, iclass 18, count 2 2006.285.08:17:58.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:17:58.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:17:58.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.08:17:58.09#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:58.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:17:58.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:17:58.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:17:58.21#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:17:58.21#ibcon#first serial, iclass 18, count 0 2006.285.08:17:58.21#ibcon#enter sib2, iclass 18, count 0 2006.285.08:17:58.21#ibcon#flushed, iclass 18, count 0 2006.285.08:17:58.21#ibcon#about to write, iclass 18, count 0 2006.285.08:17:58.21#ibcon#wrote, iclass 18, count 0 2006.285.08:17:58.21#ibcon#about to read 3, iclass 18, count 0 2006.285.08:17:58.23#ibcon#read 3, iclass 18, count 0 2006.285.08:17:58.23#ibcon#about to read 4, iclass 18, count 0 2006.285.08:17:58.23#ibcon#read 4, iclass 18, count 0 2006.285.08:17:58.23#ibcon#about to read 5, iclass 18, count 0 2006.285.08:17:58.23#ibcon#read 5, iclass 18, count 0 2006.285.08:17:58.23#ibcon#about to read 6, iclass 18, count 0 2006.285.08:17:58.23#ibcon#read 6, iclass 18, count 0 2006.285.08:17:58.23#ibcon#end of sib2, iclass 18, count 0 2006.285.08:17:58.23#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:17:58.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:17:58.23#ibcon#[25=USB\r\n] 2006.285.08:17:58.23#ibcon#*before write, iclass 18, count 0 2006.285.08:17:58.23#ibcon#enter sib2, iclass 18, count 0 2006.285.08:17:58.23#ibcon#flushed, iclass 18, count 0 2006.285.08:17:58.23#ibcon#about to write, iclass 18, count 0 2006.285.08:17:58.23#ibcon#wrote, iclass 18, count 0 2006.285.08:17:58.23#ibcon#about to read 3, iclass 18, count 0 2006.285.08:17:58.26#ibcon#read 3, iclass 18, count 0 2006.285.08:17:58.26#ibcon#about to read 4, iclass 18, count 0 2006.285.08:17:58.26#ibcon#read 4, iclass 18, count 0 2006.285.08:17:58.26#ibcon#about to read 5, iclass 18, count 0 2006.285.08:17:58.26#ibcon#read 5, iclass 18, count 0 2006.285.08:17:58.26#ibcon#about to read 6, iclass 18, count 0 2006.285.08:17:58.26#ibcon#read 6, iclass 18, count 0 2006.285.08:17:58.26#ibcon#end of sib2, iclass 18, count 0 2006.285.08:17:58.26#ibcon#*after write, iclass 18, count 0 2006.285.08:17:58.26#ibcon#*before return 0, iclass 18, count 0 2006.285.08:17:58.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:17:58.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:17:58.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:17:58.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:17:58.26$vck44/valo=8,884.99 2006.285.08:17:58.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.08:17:58.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.08:17:58.26#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:58.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:17:58.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:17:58.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:17:58.26#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:17:58.26#ibcon#first serial, iclass 20, count 0 2006.285.08:17:58.26#ibcon#enter sib2, iclass 20, count 0 2006.285.08:17:58.26#ibcon#flushed, iclass 20, count 0 2006.285.08:17:58.26#ibcon#about to write, iclass 20, count 0 2006.285.08:17:58.26#ibcon#wrote, iclass 20, count 0 2006.285.08:17:58.26#ibcon#about to read 3, iclass 20, count 0 2006.285.08:17:58.28#ibcon#read 3, iclass 20, count 0 2006.285.08:17:58.28#ibcon#about to read 4, iclass 20, count 0 2006.285.08:17:58.28#ibcon#read 4, iclass 20, count 0 2006.285.08:17:58.28#ibcon#about to read 5, iclass 20, count 0 2006.285.08:17:58.28#ibcon#read 5, iclass 20, count 0 2006.285.08:17:58.28#ibcon#about to read 6, iclass 20, count 0 2006.285.08:17:58.28#ibcon#read 6, iclass 20, count 0 2006.285.08:17:58.28#ibcon#end of sib2, iclass 20, count 0 2006.285.08:17:58.28#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:17:58.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:17:58.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:17:58.28#ibcon#*before write, iclass 20, count 0 2006.285.08:17:58.28#ibcon#enter sib2, iclass 20, count 0 2006.285.08:17:58.28#ibcon#flushed, iclass 20, count 0 2006.285.08:17:58.28#ibcon#about to write, iclass 20, count 0 2006.285.08:17:58.28#ibcon#wrote, iclass 20, count 0 2006.285.08:17:58.28#ibcon#about to read 3, iclass 20, count 0 2006.285.08:17:58.32#ibcon#read 3, iclass 20, count 0 2006.285.08:17:58.32#ibcon#about to read 4, iclass 20, count 0 2006.285.08:17:58.32#ibcon#read 4, iclass 20, count 0 2006.285.08:17:58.32#ibcon#about to read 5, iclass 20, count 0 2006.285.08:17:58.32#ibcon#read 5, iclass 20, count 0 2006.285.08:17:58.32#ibcon#about to read 6, iclass 20, count 0 2006.285.08:17:58.32#ibcon#read 6, iclass 20, count 0 2006.285.08:17:58.32#ibcon#end of sib2, iclass 20, count 0 2006.285.08:17:58.32#ibcon#*after write, iclass 20, count 0 2006.285.08:17:58.32#ibcon#*before return 0, iclass 20, count 0 2006.285.08:17:58.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:17:58.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:17:58.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:17:58.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:17:58.32$vck44/va=8,3 2006.285.08:17:58.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.08:17:58.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.08:17:58.32#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:58.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:17:58.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:17:58.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:17:58.38#ibcon#enter wrdev, iclass 22, count 2 2006.285.08:17:58.38#ibcon#first serial, iclass 22, count 2 2006.285.08:17:58.38#ibcon#enter sib2, iclass 22, count 2 2006.285.08:17:58.38#ibcon#flushed, iclass 22, count 2 2006.285.08:17:58.38#ibcon#about to write, iclass 22, count 2 2006.285.08:17:58.38#ibcon#wrote, iclass 22, count 2 2006.285.08:17:58.38#ibcon#about to read 3, iclass 22, count 2 2006.285.08:17:58.40#ibcon#read 3, iclass 22, count 2 2006.285.08:17:58.40#ibcon#about to read 4, iclass 22, count 2 2006.285.08:17:58.40#ibcon#read 4, iclass 22, count 2 2006.285.08:17:58.40#ibcon#about to read 5, iclass 22, count 2 2006.285.08:17:58.40#ibcon#read 5, iclass 22, count 2 2006.285.08:17:58.40#ibcon#about to read 6, iclass 22, count 2 2006.285.08:17:58.40#ibcon#read 6, iclass 22, count 2 2006.285.08:17:58.40#ibcon#end of sib2, iclass 22, count 2 2006.285.08:17:58.40#ibcon#*mode == 0, iclass 22, count 2 2006.285.08:17:58.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.08:17:58.40#ibcon#[25=AT08-03\r\n] 2006.285.08:17:58.40#ibcon#*before write, iclass 22, count 2 2006.285.08:17:58.40#ibcon#enter sib2, iclass 22, count 2 2006.285.08:17:58.40#ibcon#flushed, iclass 22, count 2 2006.285.08:17:58.40#ibcon#about to write, iclass 22, count 2 2006.285.08:17:58.40#ibcon#wrote, iclass 22, count 2 2006.285.08:17:58.40#ibcon#about to read 3, iclass 22, count 2 2006.285.08:17:58.43#ibcon#read 3, iclass 22, count 2 2006.285.08:17:58.43#ibcon#about to read 4, iclass 22, count 2 2006.285.08:17:58.43#ibcon#read 4, iclass 22, count 2 2006.285.08:17:58.43#ibcon#about to read 5, iclass 22, count 2 2006.285.08:17:58.43#ibcon#read 5, iclass 22, count 2 2006.285.08:17:58.43#ibcon#about to read 6, iclass 22, count 2 2006.285.08:17:58.43#ibcon#read 6, iclass 22, count 2 2006.285.08:17:58.43#ibcon#end of sib2, iclass 22, count 2 2006.285.08:17:58.43#ibcon#*after write, iclass 22, count 2 2006.285.08:17:58.43#ibcon#*before return 0, iclass 22, count 2 2006.285.08:17:58.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:17:58.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:17:58.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.08:17:58.43#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:58.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:17:58.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:17:58.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:17:58.55#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:17:58.55#ibcon#first serial, iclass 22, count 0 2006.285.08:17:58.55#ibcon#enter sib2, iclass 22, count 0 2006.285.08:17:58.55#ibcon#flushed, iclass 22, count 0 2006.285.08:17:58.55#ibcon#about to write, iclass 22, count 0 2006.285.08:17:58.55#ibcon#wrote, iclass 22, count 0 2006.285.08:17:58.55#ibcon#about to read 3, iclass 22, count 0 2006.285.08:17:58.57#ibcon#read 3, iclass 22, count 0 2006.285.08:17:58.57#ibcon#about to read 4, iclass 22, count 0 2006.285.08:17:58.57#ibcon#read 4, iclass 22, count 0 2006.285.08:17:58.57#ibcon#about to read 5, iclass 22, count 0 2006.285.08:17:58.57#ibcon#read 5, iclass 22, count 0 2006.285.08:17:58.57#ibcon#about to read 6, iclass 22, count 0 2006.285.08:17:58.57#ibcon#read 6, iclass 22, count 0 2006.285.08:17:58.57#ibcon#end of sib2, iclass 22, count 0 2006.285.08:17:58.57#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:17:58.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:17:58.57#ibcon#[25=USB\r\n] 2006.285.08:17:58.57#ibcon#*before write, iclass 22, count 0 2006.285.08:17:58.57#ibcon#enter sib2, iclass 22, count 0 2006.285.08:17:58.57#ibcon#flushed, iclass 22, count 0 2006.285.08:17:58.57#ibcon#about to write, iclass 22, count 0 2006.285.08:17:58.57#ibcon#wrote, iclass 22, count 0 2006.285.08:17:58.57#ibcon#about to read 3, iclass 22, count 0 2006.285.08:17:58.60#ibcon#read 3, iclass 22, count 0 2006.285.08:17:58.60#ibcon#about to read 4, iclass 22, count 0 2006.285.08:17:58.60#ibcon#read 4, iclass 22, count 0 2006.285.08:17:58.60#ibcon#about to read 5, iclass 22, count 0 2006.285.08:17:58.60#ibcon#read 5, iclass 22, count 0 2006.285.08:17:58.60#ibcon#about to read 6, iclass 22, count 0 2006.285.08:17:58.60#ibcon#read 6, iclass 22, count 0 2006.285.08:17:58.60#ibcon#end of sib2, iclass 22, count 0 2006.285.08:17:58.60#ibcon#*after write, iclass 22, count 0 2006.285.08:17:58.60#ibcon#*before return 0, iclass 22, count 0 2006.285.08:17:58.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:17:58.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:17:58.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:17:58.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:17:58.60$vck44/vblo=1,629.99 2006.285.08:17:58.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.08:17:58.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.08:17:58.60#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:58.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:17:58.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:17:58.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:17:58.60#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:17:58.60#ibcon#first serial, iclass 24, count 0 2006.285.08:17:58.60#ibcon#enter sib2, iclass 24, count 0 2006.285.08:17:58.60#ibcon#flushed, iclass 24, count 0 2006.285.08:17:58.60#ibcon#about to write, iclass 24, count 0 2006.285.08:17:58.60#ibcon#wrote, iclass 24, count 0 2006.285.08:17:58.60#ibcon#about to read 3, iclass 24, count 0 2006.285.08:17:58.62#ibcon#read 3, iclass 24, count 0 2006.285.08:17:58.62#ibcon#about to read 4, iclass 24, count 0 2006.285.08:17:58.62#ibcon#read 4, iclass 24, count 0 2006.285.08:17:58.62#ibcon#about to read 5, iclass 24, count 0 2006.285.08:17:58.62#ibcon#read 5, iclass 24, count 0 2006.285.08:17:58.62#ibcon#about to read 6, iclass 24, count 0 2006.285.08:17:58.62#ibcon#read 6, iclass 24, count 0 2006.285.08:17:58.62#ibcon#end of sib2, iclass 24, count 0 2006.285.08:17:58.62#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:17:58.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:17:58.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:17:58.62#ibcon#*before write, iclass 24, count 0 2006.285.08:17:58.62#ibcon#enter sib2, iclass 24, count 0 2006.285.08:17:58.62#ibcon#flushed, iclass 24, count 0 2006.285.08:17:58.62#ibcon#about to write, iclass 24, count 0 2006.285.08:17:58.62#ibcon#wrote, iclass 24, count 0 2006.285.08:17:58.62#ibcon#about to read 3, iclass 24, count 0 2006.285.08:17:58.66#ibcon#read 3, iclass 24, count 0 2006.285.08:17:58.66#ibcon#about to read 4, iclass 24, count 0 2006.285.08:17:58.66#ibcon#read 4, iclass 24, count 0 2006.285.08:17:58.66#ibcon#about to read 5, iclass 24, count 0 2006.285.08:17:58.66#ibcon#read 5, iclass 24, count 0 2006.285.08:17:58.66#ibcon#about to read 6, iclass 24, count 0 2006.285.08:17:58.66#ibcon#read 6, iclass 24, count 0 2006.285.08:17:58.66#ibcon#end of sib2, iclass 24, count 0 2006.285.08:17:58.66#ibcon#*after write, iclass 24, count 0 2006.285.08:17:58.66#ibcon#*before return 0, iclass 24, count 0 2006.285.08:17:58.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:17:58.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:17:58.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:17:58.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:17:58.66$vck44/vb=1,4 2006.285.08:17:58.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.08:17:58.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.08:17:58.66#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:58.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:17:58.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:17:58.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:17:58.66#ibcon#enter wrdev, iclass 26, count 2 2006.285.08:17:58.66#ibcon#first serial, iclass 26, count 2 2006.285.08:17:58.66#ibcon#enter sib2, iclass 26, count 2 2006.285.08:17:58.66#ibcon#flushed, iclass 26, count 2 2006.285.08:17:58.66#ibcon#about to write, iclass 26, count 2 2006.285.08:17:58.66#ibcon#wrote, iclass 26, count 2 2006.285.08:17:58.66#ibcon#about to read 3, iclass 26, count 2 2006.285.08:17:58.68#ibcon#read 3, iclass 26, count 2 2006.285.08:17:58.68#ibcon#about to read 4, iclass 26, count 2 2006.285.08:17:58.68#ibcon#read 4, iclass 26, count 2 2006.285.08:17:58.68#ibcon#about to read 5, iclass 26, count 2 2006.285.08:17:58.68#ibcon#read 5, iclass 26, count 2 2006.285.08:17:58.68#ibcon#about to read 6, iclass 26, count 2 2006.285.08:17:58.68#ibcon#read 6, iclass 26, count 2 2006.285.08:17:58.68#ibcon#end of sib2, iclass 26, count 2 2006.285.08:17:58.68#ibcon#*mode == 0, iclass 26, count 2 2006.285.08:17:58.68#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.08:17:58.68#ibcon#[27=AT01-04\r\n] 2006.285.08:17:58.68#ibcon#*before write, iclass 26, count 2 2006.285.08:17:58.68#ibcon#enter sib2, iclass 26, count 2 2006.285.08:17:58.68#ibcon#flushed, iclass 26, count 2 2006.285.08:17:58.68#ibcon#about to write, iclass 26, count 2 2006.285.08:17:58.68#ibcon#wrote, iclass 26, count 2 2006.285.08:17:58.68#ibcon#about to read 3, iclass 26, count 2 2006.285.08:17:58.71#ibcon#read 3, iclass 26, count 2 2006.285.08:17:58.71#ibcon#about to read 4, iclass 26, count 2 2006.285.08:17:58.71#ibcon#read 4, iclass 26, count 2 2006.285.08:17:58.71#ibcon#about to read 5, iclass 26, count 2 2006.285.08:17:58.71#ibcon#read 5, iclass 26, count 2 2006.285.08:17:58.71#ibcon#about to read 6, iclass 26, count 2 2006.285.08:17:58.71#ibcon#read 6, iclass 26, count 2 2006.285.08:17:58.71#ibcon#end of sib2, iclass 26, count 2 2006.285.08:17:58.71#ibcon#*after write, iclass 26, count 2 2006.285.08:17:58.71#ibcon#*before return 0, iclass 26, count 2 2006.285.08:17:58.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:17:58.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:17:58.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.08:17:58.71#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:58.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:17:58.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:17:58.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:17:58.83#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:17:58.83#ibcon#first serial, iclass 26, count 0 2006.285.08:17:58.83#ibcon#enter sib2, iclass 26, count 0 2006.285.08:17:58.83#ibcon#flushed, iclass 26, count 0 2006.285.08:17:58.83#ibcon#about to write, iclass 26, count 0 2006.285.08:17:58.83#ibcon#wrote, iclass 26, count 0 2006.285.08:17:58.83#ibcon#about to read 3, iclass 26, count 0 2006.285.08:17:58.85#ibcon#read 3, iclass 26, count 0 2006.285.08:17:58.85#ibcon#about to read 4, iclass 26, count 0 2006.285.08:17:58.85#ibcon#read 4, iclass 26, count 0 2006.285.08:17:58.85#ibcon#about to read 5, iclass 26, count 0 2006.285.08:17:58.85#ibcon#read 5, iclass 26, count 0 2006.285.08:17:58.85#ibcon#about to read 6, iclass 26, count 0 2006.285.08:17:58.85#ibcon#read 6, iclass 26, count 0 2006.285.08:17:58.85#ibcon#end of sib2, iclass 26, count 0 2006.285.08:17:58.85#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:17:58.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:17:58.85#ibcon#[27=USB\r\n] 2006.285.08:17:58.85#ibcon#*before write, iclass 26, count 0 2006.285.08:17:58.85#ibcon#enter sib2, iclass 26, count 0 2006.285.08:17:58.85#ibcon#flushed, iclass 26, count 0 2006.285.08:17:58.85#ibcon#about to write, iclass 26, count 0 2006.285.08:17:58.85#ibcon#wrote, iclass 26, count 0 2006.285.08:17:58.85#ibcon#about to read 3, iclass 26, count 0 2006.285.08:17:58.88#ibcon#read 3, iclass 26, count 0 2006.285.08:17:58.88#ibcon#about to read 4, iclass 26, count 0 2006.285.08:17:58.88#ibcon#read 4, iclass 26, count 0 2006.285.08:17:58.88#ibcon#about to read 5, iclass 26, count 0 2006.285.08:17:58.88#ibcon#read 5, iclass 26, count 0 2006.285.08:17:58.88#ibcon#about to read 6, iclass 26, count 0 2006.285.08:17:58.88#ibcon#read 6, iclass 26, count 0 2006.285.08:17:58.88#ibcon#end of sib2, iclass 26, count 0 2006.285.08:17:58.88#ibcon#*after write, iclass 26, count 0 2006.285.08:17:58.88#ibcon#*before return 0, iclass 26, count 0 2006.285.08:17:58.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:17:58.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:17:58.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:17:58.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:17:58.88$vck44/vblo=2,634.99 2006.285.08:17:58.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.08:17:58.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.08:17:58.88#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:58.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:17:58.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:17:58.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:17:58.88#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:17:58.88#ibcon#first serial, iclass 28, count 0 2006.285.08:17:58.88#ibcon#enter sib2, iclass 28, count 0 2006.285.08:17:58.88#ibcon#flushed, iclass 28, count 0 2006.285.08:17:58.88#ibcon#about to write, iclass 28, count 0 2006.285.08:17:58.88#ibcon#wrote, iclass 28, count 0 2006.285.08:17:58.88#ibcon#about to read 3, iclass 28, count 0 2006.285.08:17:58.90#ibcon#read 3, iclass 28, count 0 2006.285.08:17:58.90#ibcon#about to read 4, iclass 28, count 0 2006.285.08:17:58.90#ibcon#read 4, iclass 28, count 0 2006.285.08:17:58.90#ibcon#about to read 5, iclass 28, count 0 2006.285.08:17:58.90#ibcon#read 5, iclass 28, count 0 2006.285.08:17:58.90#ibcon#about to read 6, iclass 28, count 0 2006.285.08:17:58.90#ibcon#read 6, iclass 28, count 0 2006.285.08:17:58.90#ibcon#end of sib2, iclass 28, count 0 2006.285.08:17:58.90#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:17:58.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:17:58.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:17:58.90#ibcon#*before write, iclass 28, count 0 2006.285.08:17:58.90#ibcon#enter sib2, iclass 28, count 0 2006.285.08:17:58.90#ibcon#flushed, iclass 28, count 0 2006.285.08:17:58.90#ibcon#about to write, iclass 28, count 0 2006.285.08:17:58.90#ibcon#wrote, iclass 28, count 0 2006.285.08:17:58.90#ibcon#about to read 3, iclass 28, count 0 2006.285.08:17:58.94#ibcon#read 3, iclass 28, count 0 2006.285.08:17:58.94#ibcon#about to read 4, iclass 28, count 0 2006.285.08:17:58.94#ibcon#read 4, iclass 28, count 0 2006.285.08:17:58.94#ibcon#about to read 5, iclass 28, count 0 2006.285.08:17:58.94#ibcon#read 5, iclass 28, count 0 2006.285.08:17:58.94#ibcon#about to read 6, iclass 28, count 0 2006.285.08:17:58.94#ibcon#read 6, iclass 28, count 0 2006.285.08:17:58.94#ibcon#end of sib2, iclass 28, count 0 2006.285.08:17:58.94#ibcon#*after write, iclass 28, count 0 2006.285.08:17:58.94#ibcon#*before return 0, iclass 28, count 0 2006.285.08:17:58.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:17:58.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:17:58.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:17:58.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:17:58.94$vck44/vb=2,5 2006.285.08:17:58.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.08:17:58.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.08:17:58.94#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:58.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:17:59.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:17:59.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:17:59.00#ibcon#enter wrdev, iclass 30, count 2 2006.285.08:17:59.00#ibcon#first serial, iclass 30, count 2 2006.285.08:17:59.00#ibcon#enter sib2, iclass 30, count 2 2006.285.08:17:59.00#ibcon#flushed, iclass 30, count 2 2006.285.08:17:59.00#ibcon#about to write, iclass 30, count 2 2006.285.08:17:59.00#ibcon#wrote, iclass 30, count 2 2006.285.08:17:59.00#ibcon#about to read 3, iclass 30, count 2 2006.285.08:17:59.02#ibcon#read 3, iclass 30, count 2 2006.285.08:17:59.02#ibcon#about to read 4, iclass 30, count 2 2006.285.08:17:59.02#ibcon#read 4, iclass 30, count 2 2006.285.08:17:59.02#ibcon#about to read 5, iclass 30, count 2 2006.285.08:17:59.02#ibcon#read 5, iclass 30, count 2 2006.285.08:17:59.02#ibcon#about to read 6, iclass 30, count 2 2006.285.08:17:59.02#ibcon#read 6, iclass 30, count 2 2006.285.08:17:59.02#ibcon#end of sib2, iclass 30, count 2 2006.285.08:17:59.02#ibcon#*mode == 0, iclass 30, count 2 2006.285.08:17:59.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.08:17:59.02#ibcon#[27=AT02-05\r\n] 2006.285.08:17:59.02#ibcon#*before write, iclass 30, count 2 2006.285.08:17:59.02#ibcon#enter sib2, iclass 30, count 2 2006.285.08:17:59.02#ibcon#flushed, iclass 30, count 2 2006.285.08:17:59.02#ibcon#about to write, iclass 30, count 2 2006.285.08:17:59.02#ibcon#wrote, iclass 30, count 2 2006.285.08:17:59.02#ibcon#about to read 3, iclass 30, count 2 2006.285.08:17:59.05#ibcon#read 3, iclass 30, count 2 2006.285.08:17:59.05#ibcon#about to read 4, iclass 30, count 2 2006.285.08:17:59.05#ibcon#read 4, iclass 30, count 2 2006.285.08:17:59.05#ibcon#about to read 5, iclass 30, count 2 2006.285.08:17:59.05#ibcon#read 5, iclass 30, count 2 2006.285.08:17:59.05#ibcon#about to read 6, iclass 30, count 2 2006.285.08:17:59.05#ibcon#read 6, iclass 30, count 2 2006.285.08:17:59.05#ibcon#end of sib2, iclass 30, count 2 2006.285.08:17:59.05#ibcon#*after write, iclass 30, count 2 2006.285.08:17:59.05#ibcon#*before return 0, iclass 30, count 2 2006.285.08:17:59.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:17:59.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:17:59.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.08:17:59.05#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:59.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:17:59.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:17:59.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:17:59.17#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:17:59.17#ibcon#first serial, iclass 30, count 0 2006.285.08:17:59.17#ibcon#enter sib2, iclass 30, count 0 2006.285.08:17:59.17#ibcon#flushed, iclass 30, count 0 2006.285.08:17:59.17#ibcon#about to write, iclass 30, count 0 2006.285.08:17:59.17#ibcon#wrote, iclass 30, count 0 2006.285.08:17:59.17#ibcon#about to read 3, iclass 30, count 0 2006.285.08:17:59.19#ibcon#read 3, iclass 30, count 0 2006.285.08:17:59.19#ibcon#about to read 4, iclass 30, count 0 2006.285.08:17:59.19#ibcon#read 4, iclass 30, count 0 2006.285.08:17:59.19#ibcon#about to read 5, iclass 30, count 0 2006.285.08:17:59.19#ibcon#read 5, iclass 30, count 0 2006.285.08:17:59.19#ibcon#about to read 6, iclass 30, count 0 2006.285.08:17:59.19#ibcon#read 6, iclass 30, count 0 2006.285.08:17:59.19#ibcon#end of sib2, iclass 30, count 0 2006.285.08:17:59.19#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:17:59.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:17:59.19#ibcon#[27=USB\r\n] 2006.285.08:17:59.19#ibcon#*before write, iclass 30, count 0 2006.285.08:17:59.19#ibcon#enter sib2, iclass 30, count 0 2006.285.08:17:59.19#ibcon#flushed, iclass 30, count 0 2006.285.08:17:59.19#ibcon#about to write, iclass 30, count 0 2006.285.08:17:59.19#ibcon#wrote, iclass 30, count 0 2006.285.08:17:59.19#ibcon#about to read 3, iclass 30, count 0 2006.285.08:17:59.22#ibcon#read 3, iclass 30, count 0 2006.285.08:17:59.22#ibcon#about to read 4, iclass 30, count 0 2006.285.08:17:59.22#ibcon#read 4, iclass 30, count 0 2006.285.08:17:59.22#ibcon#about to read 5, iclass 30, count 0 2006.285.08:17:59.22#ibcon#read 5, iclass 30, count 0 2006.285.08:17:59.22#ibcon#about to read 6, iclass 30, count 0 2006.285.08:17:59.22#ibcon#read 6, iclass 30, count 0 2006.285.08:17:59.22#ibcon#end of sib2, iclass 30, count 0 2006.285.08:17:59.22#ibcon#*after write, iclass 30, count 0 2006.285.08:17:59.22#ibcon#*before return 0, iclass 30, count 0 2006.285.08:17:59.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:17:59.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:17:59.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:17:59.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:17:59.22$vck44/vblo=3,649.99 2006.285.08:17:59.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.08:17:59.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.08:17:59.22#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:59.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:17:59.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:17:59.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:17:59.22#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:17:59.22#ibcon#first serial, iclass 32, count 0 2006.285.08:17:59.22#ibcon#enter sib2, iclass 32, count 0 2006.285.08:17:59.22#ibcon#flushed, iclass 32, count 0 2006.285.08:17:59.22#ibcon#about to write, iclass 32, count 0 2006.285.08:17:59.22#ibcon#wrote, iclass 32, count 0 2006.285.08:17:59.22#ibcon#about to read 3, iclass 32, count 0 2006.285.08:17:59.24#ibcon#read 3, iclass 32, count 0 2006.285.08:17:59.24#ibcon#about to read 4, iclass 32, count 0 2006.285.08:17:59.24#ibcon#read 4, iclass 32, count 0 2006.285.08:17:59.24#ibcon#about to read 5, iclass 32, count 0 2006.285.08:17:59.24#ibcon#read 5, iclass 32, count 0 2006.285.08:17:59.24#ibcon#about to read 6, iclass 32, count 0 2006.285.08:17:59.24#ibcon#read 6, iclass 32, count 0 2006.285.08:17:59.24#ibcon#end of sib2, iclass 32, count 0 2006.285.08:17:59.24#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:17:59.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:17:59.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:17:59.24#ibcon#*before write, iclass 32, count 0 2006.285.08:17:59.24#ibcon#enter sib2, iclass 32, count 0 2006.285.08:17:59.24#ibcon#flushed, iclass 32, count 0 2006.285.08:17:59.24#ibcon#about to write, iclass 32, count 0 2006.285.08:17:59.24#ibcon#wrote, iclass 32, count 0 2006.285.08:17:59.24#ibcon#about to read 3, iclass 32, count 0 2006.285.08:17:59.28#ibcon#read 3, iclass 32, count 0 2006.285.08:17:59.28#ibcon#about to read 4, iclass 32, count 0 2006.285.08:17:59.28#ibcon#read 4, iclass 32, count 0 2006.285.08:17:59.28#ibcon#about to read 5, iclass 32, count 0 2006.285.08:17:59.28#ibcon#read 5, iclass 32, count 0 2006.285.08:17:59.28#ibcon#about to read 6, iclass 32, count 0 2006.285.08:17:59.28#ibcon#read 6, iclass 32, count 0 2006.285.08:17:59.28#ibcon#end of sib2, iclass 32, count 0 2006.285.08:17:59.28#ibcon#*after write, iclass 32, count 0 2006.285.08:17:59.28#ibcon#*before return 0, iclass 32, count 0 2006.285.08:17:59.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:17:59.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:17:59.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:17:59.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:17:59.28$vck44/vb=3,4 2006.285.08:17:59.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.08:17:59.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.08:17:59.28#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:59.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:17:59.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:17:59.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:17:59.34#ibcon#enter wrdev, iclass 34, count 2 2006.285.08:17:59.34#ibcon#first serial, iclass 34, count 2 2006.285.08:17:59.34#ibcon#enter sib2, iclass 34, count 2 2006.285.08:17:59.34#ibcon#flushed, iclass 34, count 2 2006.285.08:17:59.34#ibcon#about to write, iclass 34, count 2 2006.285.08:17:59.34#ibcon#wrote, iclass 34, count 2 2006.285.08:17:59.34#ibcon#about to read 3, iclass 34, count 2 2006.285.08:17:59.36#ibcon#read 3, iclass 34, count 2 2006.285.08:17:59.36#ibcon#about to read 4, iclass 34, count 2 2006.285.08:17:59.36#ibcon#read 4, iclass 34, count 2 2006.285.08:17:59.36#ibcon#about to read 5, iclass 34, count 2 2006.285.08:17:59.36#ibcon#read 5, iclass 34, count 2 2006.285.08:17:59.36#ibcon#about to read 6, iclass 34, count 2 2006.285.08:17:59.36#ibcon#read 6, iclass 34, count 2 2006.285.08:17:59.36#ibcon#end of sib2, iclass 34, count 2 2006.285.08:17:59.36#ibcon#*mode == 0, iclass 34, count 2 2006.285.08:17:59.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.08:17:59.36#ibcon#[27=AT03-04\r\n] 2006.285.08:17:59.36#ibcon#*before write, iclass 34, count 2 2006.285.08:17:59.36#ibcon#enter sib2, iclass 34, count 2 2006.285.08:17:59.36#ibcon#flushed, iclass 34, count 2 2006.285.08:17:59.36#ibcon#about to write, iclass 34, count 2 2006.285.08:17:59.36#ibcon#wrote, iclass 34, count 2 2006.285.08:17:59.36#ibcon#about to read 3, iclass 34, count 2 2006.285.08:17:59.39#ibcon#read 3, iclass 34, count 2 2006.285.08:17:59.39#ibcon#about to read 4, iclass 34, count 2 2006.285.08:17:59.39#ibcon#read 4, iclass 34, count 2 2006.285.08:17:59.39#ibcon#about to read 5, iclass 34, count 2 2006.285.08:17:59.39#ibcon#read 5, iclass 34, count 2 2006.285.08:17:59.39#ibcon#about to read 6, iclass 34, count 2 2006.285.08:17:59.39#ibcon#read 6, iclass 34, count 2 2006.285.08:17:59.39#ibcon#end of sib2, iclass 34, count 2 2006.285.08:17:59.39#ibcon#*after write, iclass 34, count 2 2006.285.08:17:59.39#ibcon#*before return 0, iclass 34, count 2 2006.285.08:17:59.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:17:59.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:17:59.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.08:17:59.39#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:59.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:17:59.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:17:59.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:17:59.51#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:17:59.51#ibcon#first serial, iclass 34, count 0 2006.285.08:17:59.51#ibcon#enter sib2, iclass 34, count 0 2006.285.08:17:59.51#ibcon#flushed, iclass 34, count 0 2006.285.08:17:59.51#ibcon#about to write, iclass 34, count 0 2006.285.08:17:59.51#ibcon#wrote, iclass 34, count 0 2006.285.08:17:59.51#ibcon#about to read 3, iclass 34, count 0 2006.285.08:17:59.53#ibcon#read 3, iclass 34, count 0 2006.285.08:17:59.53#ibcon#about to read 4, iclass 34, count 0 2006.285.08:17:59.53#ibcon#read 4, iclass 34, count 0 2006.285.08:17:59.53#ibcon#about to read 5, iclass 34, count 0 2006.285.08:17:59.53#ibcon#read 5, iclass 34, count 0 2006.285.08:17:59.53#ibcon#about to read 6, iclass 34, count 0 2006.285.08:17:59.53#ibcon#read 6, iclass 34, count 0 2006.285.08:17:59.53#ibcon#end of sib2, iclass 34, count 0 2006.285.08:17:59.53#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:17:59.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:17:59.53#ibcon#[27=USB\r\n] 2006.285.08:17:59.53#ibcon#*before write, iclass 34, count 0 2006.285.08:17:59.53#ibcon#enter sib2, iclass 34, count 0 2006.285.08:17:59.53#ibcon#flushed, iclass 34, count 0 2006.285.08:17:59.53#ibcon#about to write, iclass 34, count 0 2006.285.08:17:59.53#ibcon#wrote, iclass 34, count 0 2006.285.08:17:59.53#ibcon#about to read 3, iclass 34, count 0 2006.285.08:17:59.56#ibcon#read 3, iclass 34, count 0 2006.285.08:17:59.56#ibcon#about to read 4, iclass 34, count 0 2006.285.08:17:59.56#ibcon#read 4, iclass 34, count 0 2006.285.08:17:59.56#ibcon#about to read 5, iclass 34, count 0 2006.285.08:17:59.56#ibcon#read 5, iclass 34, count 0 2006.285.08:17:59.56#ibcon#about to read 6, iclass 34, count 0 2006.285.08:17:59.56#ibcon#read 6, iclass 34, count 0 2006.285.08:17:59.56#ibcon#end of sib2, iclass 34, count 0 2006.285.08:17:59.56#ibcon#*after write, iclass 34, count 0 2006.285.08:17:59.56#ibcon#*before return 0, iclass 34, count 0 2006.285.08:17:59.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:17:59.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:17:59.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:17:59.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:17:59.56$vck44/vblo=4,679.99 2006.285.08:17:59.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.08:17:59.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.08:17:59.56#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:59.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:17:59.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:17:59.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:17:59.56#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:17:59.56#ibcon#first serial, iclass 36, count 0 2006.285.08:17:59.56#ibcon#enter sib2, iclass 36, count 0 2006.285.08:17:59.56#ibcon#flushed, iclass 36, count 0 2006.285.08:17:59.56#ibcon#about to write, iclass 36, count 0 2006.285.08:17:59.56#ibcon#wrote, iclass 36, count 0 2006.285.08:17:59.56#ibcon#about to read 3, iclass 36, count 0 2006.285.08:17:59.58#ibcon#read 3, iclass 36, count 0 2006.285.08:17:59.58#ibcon#about to read 4, iclass 36, count 0 2006.285.08:17:59.58#ibcon#read 4, iclass 36, count 0 2006.285.08:17:59.58#ibcon#about to read 5, iclass 36, count 0 2006.285.08:17:59.58#ibcon#read 5, iclass 36, count 0 2006.285.08:17:59.58#ibcon#about to read 6, iclass 36, count 0 2006.285.08:17:59.58#ibcon#read 6, iclass 36, count 0 2006.285.08:17:59.58#ibcon#end of sib2, iclass 36, count 0 2006.285.08:17:59.58#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:17:59.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:17:59.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:17:59.58#ibcon#*before write, iclass 36, count 0 2006.285.08:17:59.58#ibcon#enter sib2, iclass 36, count 0 2006.285.08:17:59.58#ibcon#flushed, iclass 36, count 0 2006.285.08:17:59.58#ibcon#about to write, iclass 36, count 0 2006.285.08:17:59.58#ibcon#wrote, iclass 36, count 0 2006.285.08:17:59.58#ibcon#about to read 3, iclass 36, count 0 2006.285.08:17:59.62#ibcon#read 3, iclass 36, count 0 2006.285.08:17:59.62#ibcon#about to read 4, iclass 36, count 0 2006.285.08:17:59.62#ibcon#read 4, iclass 36, count 0 2006.285.08:17:59.62#ibcon#about to read 5, iclass 36, count 0 2006.285.08:17:59.62#ibcon#read 5, iclass 36, count 0 2006.285.08:17:59.62#ibcon#about to read 6, iclass 36, count 0 2006.285.08:17:59.62#ibcon#read 6, iclass 36, count 0 2006.285.08:17:59.62#ibcon#end of sib2, iclass 36, count 0 2006.285.08:17:59.62#ibcon#*after write, iclass 36, count 0 2006.285.08:17:59.62#ibcon#*before return 0, iclass 36, count 0 2006.285.08:17:59.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:17:59.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:17:59.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:17:59.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:17:59.62$vck44/vb=4,5 2006.285.08:17:59.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.08:17:59.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.08:17:59.62#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:59.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:17:59.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:17:59.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:17:59.68#ibcon#enter wrdev, iclass 38, count 2 2006.285.08:17:59.68#ibcon#first serial, iclass 38, count 2 2006.285.08:17:59.68#ibcon#enter sib2, iclass 38, count 2 2006.285.08:17:59.68#ibcon#flushed, iclass 38, count 2 2006.285.08:17:59.68#ibcon#about to write, iclass 38, count 2 2006.285.08:17:59.68#ibcon#wrote, iclass 38, count 2 2006.285.08:17:59.68#ibcon#about to read 3, iclass 38, count 2 2006.285.08:17:59.70#ibcon#read 3, iclass 38, count 2 2006.285.08:17:59.70#ibcon#about to read 4, iclass 38, count 2 2006.285.08:17:59.70#ibcon#read 4, iclass 38, count 2 2006.285.08:17:59.70#ibcon#about to read 5, iclass 38, count 2 2006.285.08:17:59.70#ibcon#read 5, iclass 38, count 2 2006.285.08:17:59.70#ibcon#about to read 6, iclass 38, count 2 2006.285.08:17:59.70#ibcon#read 6, iclass 38, count 2 2006.285.08:17:59.70#ibcon#end of sib2, iclass 38, count 2 2006.285.08:17:59.70#ibcon#*mode == 0, iclass 38, count 2 2006.285.08:17:59.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.08:17:59.70#ibcon#[27=AT04-05\r\n] 2006.285.08:17:59.70#ibcon#*before write, iclass 38, count 2 2006.285.08:17:59.70#ibcon#enter sib2, iclass 38, count 2 2006.285.08:17:59.70#ibcon#flushed, iclass 38, count 2 2006.285.08:17:59.70#ibcon#about to write, iclass 38, count 2 2006.285.08:17:59.70#ibcon#wrote, iclass 38, count 2 2006.285.08:17:59.70#ibcon#about to read 3, iclass 38, count 2 2006.285.08:17:59.73#ibcon#read 3, iclass 38, count 2 2006.285.08:17:59.73#ibcon#about to read 4, iclass 38, count 2 2006.285.08:17:59.73#ibcon#read 4, iclass 38, count 2 2006.285.08:17:59.73#ibcon#about to read 5, iclass 38, count 2 2006.285.08:17:59.73#ibcon#read 5, iclass 38, count 2 2006.285.08:17:59.73#ibcon#about to read 6, iclass 38, count 2 2006.285.08:17:59.73#ibcon#read 6, iclass 38, count 2 2006.285.08:17:59.73#ibcon#end of sib2, iclass 38, count 2 2006.285.08:17:59.73#ibcon#*after write, iclass 38, count 2 2006.285.08:17:59.73#ibcon#*before return 0, iclass 38, count 2 2006.285.08:17:59.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:17:59.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:17:59.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.08:17:59.73#ibcon#ireg 7 cls_cnt 0 2006.285.08:17:59.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:17:59.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:17:59.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:17:59.85#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:17:59.85#ibcon#first serial, iclass 38, count 0 2006.285.08:17:59.85#ibcon#enter sib2, iclass 38, count 0 2006.285.08:17:59.85#ibcon#flushed, iclass 38, count 0 2006.285.08:17:59.85#ibcon#about to write, iclass 38, count 0 2006.285.08:17:59.85#ibcon#wrote, iclass 38, count 0 2006.285.08:17:59.85#ibcon#about to read 3, iclass 38, count 0 2006.285.08:17:59.87#ibcon#read 3, iclass 38, count 0 2006.285.08:17:59.87#ibcon#about to read 4, iclass 38, count 0 2006.285.08:17:59.87#ibcon#read 4, iclass 38, count 0 2006.285.08:17:59.87#ibcon#about to read 5, iclass 38, count 0 2006.285.08:17:59.87#ibcon#read 5, iclass 38, count 0 2006.285.08:17:59.87#ibcon#about to read 6, iclass 38, count 0 2006.285.08:17:59.87#ibcon#read 6, iclass 38, count 0 2006.285.08:17:59.87#ibcon#end of sib2, iclass 38, count 0 2006.285.08:17:59.87#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:17:59.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:17:59.87#ibcon#[27=USB\r\n] 2006.285.08:17:59.87#ibcon#*before write, iclass 38, count 0 2006.285.08:17:59.87#ibcon#enter sib2, iclass 38, count 0 2006.285.08:17:59.87#ibcon#flushed, iclass 38, count 0 2006.285.08:17:59.87#ibcon#about to write, iclass 38, count 0 2006.285.08:17:59.87#ibcon#wrote, iclass 38, count 0 2006.285.08:17:59.87#ibcon#about to read 3, iclass 38, count 0 2006.285.08:17:59.90#ibcon#read 3, iclass 38, count 0 2006.285.08:17:59.90#ibcon#about to read 4, iclass 38, count 0 2006.285.08:17:59.90#ibcon#read 4, iclass 38, count 0 2006.285.08:17:59.90#ibcon#about to read 5, iclass 38, count 0 2006.285.08:17:59.90#ibcon#read 5, iclass 38, count 0 2006.285.08:17:59.90#ibcon#about to read 6, iclass 38, count 0 2006.285.08:17:59.90#ibcon#read 6, iclass 38, count 0 2006.285.08:17:59.90#ibcon#end of sib2, iclass 38, count 0 2006.285.08:17:59.90#ibcon#*after write, iclass 38, count 0 2006.285.08:17:59.90#ibcon#*before return 0, iclass 38, count 0 2006.285.08:17:59.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:17:59.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:17:59.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:17:59.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:17:59.90$vck44/vblo=5,709.99 2006.285.08:17:59.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.08:17:59.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.08:17:59.90#ibcon#ireg 17 cls_cnt 0 2006.285.08:17:59.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:17:59.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:17:59.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:17:59.90#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:17:59.90#ibcon#first serial, iclass 40, count 0 2006.285.08:17:59.90#ibcon#enter sib2, iclass 40, count 0 2006.285.08:17:59.90#ibcon#flushed, iclass 40, count 0 2006.285.08:17:59.90#ibcon#about to write, iclass 40, count 0 2006.285.08:17:59.90#ibcon#wrote, iclass 40, count 0 2006.285.08:17:59.90#ibcon#about to read 3, iclass 40, count 0 2006.285.08:17:59.92#ibcon#read 3, iclass 40, count 0 2006.285.08:17:59.92#ibcon#about to read 4, iclass 40, count 0 2006.285.08:17:59.92#ibcon#read 4, iclass 40, count 0 2006.285.08:17:59.92#ibcon#about to read 5, iclass 40, count 0 2006.285.08:17:59.92#ibcon#read 5, iclass 40, count 0 2006.285.08:17:59.92#ibcon#about to read 6, iclass 40, count 0 2006.285.08:17:59.92#ibcon#read 6, iclass 40, count 0 2006.285.08:17:59.92#ibcon#end of sib2, iclass 40, count 0 2006.285.08:17:59.92#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:17:59.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:17:59.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:17:59.92#ibcon#*before write, iclass 40, count 0 2006.285.08:17:59.92#ibcon#enter sib2, iclass 40, count 0 2006.285.08:17:59.92#ibcon#flushed, iclass 40, count 0 2006.285.08:17:59.92#ibcon#about to write, iclass 40, count 0 2006.285.08:17:59.92#ibcon#wrote, iclass 40, count 0 2006.285.08:17:59.92#ibcon#about to read 3, iclass 40, count 0 2006.285.08:17:59.96#ibcon#read 3, iclass 40, count 0 2006.285.08:17:59.96#ibcon#about to read 4, iclass 40, count 0 2006.285.08:17:59.96#ibcon#read 4, iclass 40, count 0 2006.285.08:17:59.96#ibcon#about to read 5, iclass 40, count 0 2006.285.08:17:59.96#ibcon#read 5, iclass 40, count 0 2006.285.08:17:59.96#ibcon#about to read 6, iclass 40, count 0 2006.285.08:17:59.96#ibcon#read 6, iclass 40, count 0 2006.285.08:17:59.96#ibcon#end of sib2, iclass 40, count 0 2006.285.08:17:59.96#ibcon#*after write, iclass 40, count 0 2006.285.08:17:59.96#ibcon#*before return 0, iclass 40, count 0 2006.285.08:17:59.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:17:59.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:17:59.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:17:59.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:17:59.96$vck44/vb=5,4 2006.285.08:17:59.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.08:17:59.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.08:17:59.96#ibcon#ireg 11 cls_cnt 2 2006.285.08:17:59.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:18:00.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:18:00.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:18:00.02#ibcon#enter wrdev, iclass 4, count 2 2006.285.08:18:00.02#ibcon#first serial, iclass 4, count 2 2006.285.08:18:00.02#ibcon#enter sib2, iclass 4, count 2 2006.285.08:18:00.02#ibcon#flushed, iclass 4, count 2 2006.285.08:18:00.02#ibcon#about to write, iclass 4, count 2 2006.285.08:18:00.02#ibcon#wrote, iclass 4, count 2 2006.285.08:18:00.02#ibcon#about to read 3, iclass 4, count 2 2006.285.08:18:00.04#ibcon#read 3, iclass 4, count 2 2006.285.08:18:00.04#ibcon#about to read 4, iclass 4, count 2 2006.285.08:18:00.04#ibcon#read 4, iclass 4, count 2 2006.285.08:18:00.04#ibcon#about to read 5, iclass 4, count 2 2006.285.08:18:00.04#ibcon#read 5, iclass 4, count 2 2006.285.08:18:00.04#ibcon#about to read 6, iclass 4, count 2 2006.285.08:18:00.04#ibcon#read 6, iclass 4, count 2 2006.285.08:18:00.04#ibcon#end of sib2, iclass 4, count 2 2006.285.08:18:00.04#ibcon#*mode == 0, iclass 4, count 2 2006.285.08:18:00.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.08:18:00.04#ibcon#[27=AT05-04\r\n] 2006.285.08:18:00.04#ibcon#*before write, iclass 4, count 2 2006.285.08:18:00.04#ibcon#enter sib2, iclass 4, count 2 2006.285.08:18:00.04#ibcon#flushed, iclass 4, count 2 2006.285.08:18:00.04#ibcon#about to write, iclass 4, count 2 2006.285.08:18:00.04#ibcon#wrote, iclass 4, count 2 2006.285.08:18:00.04#ibcon#about to read 3, iclass 4, count 2 2006.285.08:18:00.07#ibcon#read 3, iclass 4, count 2 2006.285.08:18:00.07#ibcon#about to read 4, iclass 4, count 2 2006.285.08:18:00.07#ibcon#read 4, iclass 4, count 2 2006.285.08:18:00.07#ibcon#about to read 5, iclass 4, count 2 2006.285.08:18:00.07#ibcon#read 5, iclass 4, count 2 2006.285.08:18:00.07#ibcon#about to read 6, iclass 4, count 2 2006.285.08:18:00.07#ibcon#read 6, iclass 4, count 2 2006.285.08:18:00.07#ibcon#end of sib2, iclass 4, count 2 2006.285.08:18:00.07#ibcon#*after write, iclass 4, count 2 2006.285.08:18:00.07#ibcon#*before return 0, iclass 4, count 2 2006.285.08:18:00.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:18:00.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:18:00.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.08:18:00.07#ibcon#ireg 7 cls_cnt 0 2006.285.08:18:00.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:18:00.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:18:00.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:18:00.19#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:18:00.19#ibcon#first serial, iclass 4, count 0 2006.285.08:18:00.19#ibcon#enter sib2, iclass 4, count 0 2006.285.08:18:00.19#ibcon#flushed, iclass 4, count 0 2006.285.08:18:00.19#ibcon#about to write, iclass 4, count 0 2006.285.08:18:00.19#ibcon#wrote, iclass 4, count 0 2006.285.08:18:00.19#ibcon#about to read 3, iclass 4, count 0 2006.285.08:18:00.21#ibcon#read 3, iclass 4, count 0 2006.285.08:18:00.21#ibcon#about to read 4, iclass 4, count 0 2006.285.08:18:00.21#ibcon#read 4, iclass 4, count 0 2006.285.08:18:00.21#ibcon#about to read 5, iclass 4, count 0 2006.285.08:18:00.21#ibcon#read 5, iclass 4, count 0 2006.285.08:18:00.21#ibcon#about to read 6, iclass 4, count 0 2006.285.08:18:00.21#ibcon#read 6, iclass 4, count 0 2006.285.08:18:00.21#ibcon#end of sib2, iclass 4, count 0 2006.285.08:18:00.21#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:18:00.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:18:00.21#ibcon#[27=USB\r\n] 2006.285.08:18:00.21#ibcon#*before write, iclass 4, count 0 2006.285.08:18:00.21#ibcon#enter sib2, iclass 4, count 0 2006.285.08:18:00.21#ibcon#flushed, iclass 4, count 0 2006.285.08:18:00.21#ibcon#about to write, iclass 4, count 0 2006.285.08:18:00.21#ibcon#wrote, iclass 4, count 0 2006.285.08:18:00.21#ibcon#about to read 3, iclass 4, count 0 2006.285.08:18:00.24#ibcon#read 3, iclass 4, count 0 2006.285.08:18:00.24#ibcon#about to read 4, iclass 4, count 0 2006.285.08:18:00.24#ibcon#read 4, iclass 4, count 0 2006.285.08:18:00.24#ibcon#about to read 5, iclass 4, count 0 2006.285.08:18:00.24#ibcon#read 5, iclass 4, count 0 2006.285.08:18:00.24#ibcon#about to read 6, iclass 4, count 0 2006.285.08:18:00.24#ibcon#read 6, iclass 4, count 0 2006.285.08:18:00.24#ibcon#end of sib2, iclass 4, count 0 2006.285.08:18:00.24#ibcon#*after write, iclass 4, count 0 2006.285.08:18:00.24#ibcon#*before return 0, iclass 4, count 0 2006.285.08:18:00.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:18:00.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:18:00.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:18:00.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:18:00.24$vck44/vblo=6,719.99 2006.285.08:18:00.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.08:18:00.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.08:18:00.24#ibcon#ireg 17 cls_cnt 0 2006.285.08:18:00.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:18:00.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:18:00.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:18:00.24#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:18:00.24#ibcon#first serial, iclass 6, count 0 2006.285.08:18:00.24#ibcon#enter sib2, iclass 6, count 0 2006.285.08:18:00.24#ibcon#flushed, iclass 6, count 0 2006.285.08:18:00.24#ibcon#about to write, iclass 6, count 0 2006.285.08:18:00.24#ibcon#wrote, iclass 6, count 0 2006.285.08:18:00.24#ibcon#about to read 3, iclass 6, count 0 2006.285.08:18:00.26#ibcon#read 3, iclass 6, count 0 2006.285.08:18:00.26#ibcon#about to read 4, iclass 6, count 0 2006.285.08:18:00.26#ibcon#read 4, iclass 6, count 0 2006.285.08:18:00.26#ibcon#about to read 5, iclass 6, count 0 2006.285.08:18:00.26#ibcon#read 5, iclass 6, count 0 2006.285.08:18:00.26#ibcon#about to read 6, iclass 6, count 0 2006.285.08:18:00.26#ibcon#read 6, iclass 6, count 0 2006.285.08:18:00.26#ibcon#end of sib2, iclass 6, count 0 2006.285.08:18:00.26#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:18:00.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:18:00.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:18:00.26#ibcon#*before write, iclass 6, count 0 2006.285.08:18:00.26#ibcon#enter sib2, iclass 6, count 0 2006.285.08:18:00.26#ibcon#flushed, iclass 6, count 0 2006.285.08:18:00.26#ibcon#about to write, iclass 6, count 0 2006.285.08:18:00.26#ibcon#wrote, iclass 6, count 0 2006.285.08:18:00.26#ibcon#about to read 3, iclass 6, count 0 2006.285.08:18:00.30#ibcon#read 3, iclass 6, count 0 2006.285.08:18:00.30#ibcon#about to read 4, iclass 6, count 0 2006.285.08:18:00.30#ibcon#read 4, iclass 6, count 0 2006.285.08:18:00.30#ibcon#about to read 5, iclass 6, count 0 2006.285.08:18:00.30#ibcon#read 5, iclass 6, count 0 2006.285.08:18:00.30#ibcon#about to read 6, iclass 6, count 0 2006.285.08:18:00.30#ibcon#read 6, iclass 6, count 0 2006.285.08:18:00.30#ibcon#end of sib2, iclass 6, count 0 2006.285.08:18:00.30#ibcon#*after write, iclass 6, count 0 2006.285.08:18:00.30#ibcon#*before return 0, iclass 6, count 0 2006.285.08:18:00.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:18:00.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:18:00.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:18:00.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:18:00.30$vck44/vb=6,3 2006.285.08:18:00.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.08:18:00.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.08:18:00.30#ibcon#ireg 11 cls_cnt 2 2006.285.08:18:00.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:18:00.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:18:00.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:18:00.36#ibcon#enter wrdev, iclass 10, count 2 2006.285.08:18:00.36#ibcon#first serial, iclass 10, count 2 2006.285.08:18:00.36#ibcon#enter sib2, iclass 10, count 2 2006.285.08:18:00.36#ibcon#flushed, iclass 10, count 2 2006.285.08:18:00.36#ibcon#about to write, iclass 10, count 2 2006.285.08:18:00.36#ibcon#wrote, iclass 10, count 2 2006.285.08:18:00.36#ibcon#about to read 3, iclass 10, count 2 2006.285.08:18:00.38#ibcon#read 3, iclass 10, count 2 2006.285.08:18:00.38#ibcon#about to read 4, iclass 10, count 2 2006.285.08:18:00.38#ibcon#read 4, iclass 10, count 2 2006.285.08:18:00.38#ibcon#about to read 5, iclass 10, count 2 2006.285.08:18:00.38#ibcon#read 5, iclass 10, count 2 2006.285.08:18:00.38#ibcon#about to read 6, iclass 10, count 2 2006.285.08:18:00.38#ibcon#read 6, iclass 10, count 2 2006.285.08:18:00.38#ibcon#end of sib2, iclass 10, count 2 2006.285.08:18:00.38#ibcon#*mode == 0, iclass 10, count 2 2006.285.08:18:00.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.08:18:00.38#ibcon#[27=AT06-03\r\n] 2006.285.08:18:00.38#ibcon#*before write, iclass 10, count 2 2006.285.08:18:00.38#ibcon#enter sib2, iclass 10, count 2 2006.285.08:18:00.38#ibcon#flushed, iclass 10, count 2 2006.285.08:18:00.38#ibcon#about to write, iclass 10, count 2 2006.285.08:18:00.38#ibcon#wrote, iclass 10, count 2 2006.285.08:18:00.38#ibcon#about to read 3, iclass 10, count 2 2006.285.08:18:00.41#ibcon#read 3, iclass 10, count 2 2006.285.08:18:00.41#ibcon#about to read 4, iclass 10, count 2 2006.285.08:18:00.41#ibcon#read 4, iclass 10, count 2 2006.285.08:18:00.41#ibcon#about to read 5, iclass 10, count 2 2006.285.08:18:00.41#ibcon#read 5, iclass 10, count 2 2006.285.08:18:00.41#ibcon#about to read 6, iclass 10, count 2 2006.285.08:18:00.41#ibcon#read 6, iclass 10, count 2 2006.285.08:18:00.41#ibcon#end of sib2, iclass 10, count 2 2006.285.08:18:00.41#ibcon#*after write, iclass 10, count 2 2006.285.08:18:00.41#ibcon#*before return 0, iclass 10, count 2 2006.285.08:18:00.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:18:00.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:18:00.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.08:18:00.41#ibcon#ireg 7 cls_cnt 0 2006.285.08:18:00.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:18:00.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:18:00.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:18:00.53#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:18:00.53#ibcon#first serial, iclass 10, count 0 2006.285.08:18:00.53#ibcon#enter sib2, iclass 10, count 0 2006.285.08:18:00.53#ibcon#flushed, iclass 10, count 0 2006.285.08:18:00.53#ibcon#about to write, iclass 10, count 0 2006.285.08:18:00.53#ibcon#wrote, iclass 10, count 0 2006.285.08:18:00.53#ibcon#about to read 3, iclass 10, count 0 2006.285.08:18:00.55#ibcon#read 3, iclass 10, count 0 2006.285.08:18:00.55#ibcon#about to read 4, iclass 10, count 0 2006.285.08:18:00.55#ibcon#read 4, iclass 10, count 0 2006.285.08:18:00.55#ibcon#about to read 5, iclass 10, count 0 2006.285.08:18:00.55#ibcon#read 5, iclass 10, count 0 2006.285.08:18:00.55#ibcon#about to read 6, iclass 10, count 0 2006.285.08:18:00.55#ibcon#read 6, iclass 10, count 0 2006.285.08:18:00.55#ibcon#end of sib2, iclass 10, count 0 2006.285.08:18:00.55#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:18:00.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:18:00.55#ibcon#[27=USB\r\n] 2006.285.08:18:00.55#ibcon#*before write, iclass 10, count 0 2006.285.08:18:00.55#ibcon#enter sib2, iclass 10, count 0 2006.285.08:18:00.55#ibcon#flushed, iclass 10, count 0 2006.285.08:18:00.55#ibcon#about to write, iclass 10, count 0 2006.285.08:18:00.55#ibcon#wrote, iclass 10, count 0 2006.285.08:18:00.55#ibcon#about to read 3, iclass 10, count 0 2006.285.08:18:00.58#ibcon#read 3, iclass 10, count 0 2006.285.08:18:00.58#ibcon#about to read 4, iclass 10, count 0 2006.285.08:18:00.58#ibcon#read 4, iclass 10, count 0 2006.285.08:18:00.58#ibcon#about to read 5, iclass 10, count 0 2006.285.08:18:00.58#ibcon#read 5, iclass 10, count 0 2006.285.08:18:00.58#ibcon#about to read 6, iclass 10, count 0 2006.285.08:18:00.58#ibcon#read 6, iclass 10, count 0 2006.285.08:18:00.58#ibcon#end of sib2, iclass 10, count 0 2006.285.08:18:00.58#ibcon#*after write, iclass 10, count 0 2006.285.08:18:00.58#ibcon#*before return 0, iclass 10, count 0 2006.285.08:18:00.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:18:00.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:18:00.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:18:00.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:18:00.58$vck44/vblo=7,734.99 2006.285.08:18:00.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.08:18:00.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.08:18:00.58#ibcon#ireg 17 cls_cnt 0 2006.285.08:18:00.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:18:00.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:18:00.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:18:00.58#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:18:00.58#ibcon#first serial, iclass 12, count 0 2006.285.08:18:00.58#ibcon#enter sib2, iclass 12, count 0 2006.285.08:18:00.58#ibcon#flushed, iclass 12, count 0 2006.285.08:18:00.58#ibcon#about to write, iclass 12, count 0 2006.285.08:18:00.58#ibcon#wrote, iclass 12, count 0 2006.285.08:18:00.58#ibcon#about to read 3, iclass 12, count 0 2006.285.08:18:00.60#ibcon#read 3, iclass 12, count 0 2006.285.08:18:00.60#ibcon#about to read 4, iclass 12, count 0 2006.285.08:18:00.60#ibcon#read 4, iclass 12, count 0 2006.285.08:18:00.60#ibcon#about to read 5, iclass 12, count 0 2006.285.08:18:00.60#ibcon#read 5, iclass 12, count 0 2006.285.08:18:00.60#ibcon#about to read 6, iclass 12, count 0 2006.285.08:18:00.60#ibcon#read 6, iclass 12, count 0 2006.285.08:18:00.60#ibcon#end of sib2, iclass 12, count 0 2006.285.08:18:00.60#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:18:00.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:18:00.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:18:00.60#ibcon#*before write, iclass 12, count 0 2006.285.08:18:00.60#ibcon#enter sib2, iclass 12, count 0 2006.285.08:18:00.60#ibcon#flushed, iclass 12, count 0 2006.285.08:18:00.60#ibcon#about to write, iclass 12, count 0 2006.285.08:18:00.60#ibcon#wrote, iclass 12, count 0 2006.285.08:18:00.60#ibcon#about to read 3, iclass 12, count 0 2006.285.08:18:00.64#ibcon#read 3, iclass 12, count 0 2006.285.08:18:00.64#ibcon#about to read 4, iclass 12, count 0 2006.285.08:18:00.64#ibcon#read 4, iclass 12, count 0 2006.285.08:18:00.64#ibcon#about to read 5, iclass 12, count 0 2006.285.08:18:00.64#ibcon#read 5, iclass 12, count 0 2006.285.08:18:00.64#ibcon#about to read 6, iclass 12, count 0 2006.285.08:18:00.64#ibcon#read 6, iclass 12, count 0 2006.285.08:18:00.64#ibcon#end of sib2, iclass 12, count 0 2006.285.08:18:00.64#ibcon#*after write, iclass 12, count 0 2006.285.08:18:00.64#ibcon#*before return 0, iclass 12, count 0 2006.285.08:18:00.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:18:00.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:18:00.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:18:00.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:18:00.64$vck44/vb=7,4 2006.285.08:18:00.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.08:18:00.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.08:18:00.64#ibcon#ireg 11 cls_cnt 2 2006.285.08:18:00.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:18:00.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:18:00.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:18:00.70#ibcon#enter wrdev, iclass 14, count 2 2006.285.08:18:00.70#ibcon#first serial, iclass 14, count 2 2006.285.08:18:00.70#ibcon#enter sib2, iclass 14, count 2 2006.285.08:18:00.70#ibcon#flushed, iclass 14, count 2 2006.285.08:18:00.70#ibcon#about to write, iclass 14, count 2 2006.285.08:18:00.70#ibcon#wrote, iclass 14, count 2 2006.285.08:18:00.70#ibcon#about to read 3, iclass 14, count 2 2006.285.08:18:00.72#ibcon#read 3, iclass 14, count 2 2006.285.08:18:00.72#ibcon#about to read 4, iclass 14, count 2 2006.285.08:18:00.72#ibcon#read 4, iclass 14, count 2 2006.285.08:18:00.72#ibcon#about to read 5, iclass 14, count 2 2006.285.08:18:00.72#ibcon#read 5, iclass 14, count 2 2006.285.08:18:00.72#ibcon#about to read 6, iclass 14, count 2 2006.285.08:18:00.72#ibcon#read 6, iclass 14, count 2 2006.285.08:18:00.72#ibcon#end of sib2, iclass 14, count 2 2006.285.08:18:00.72#ibcon#*mode == 0, iclass 14, count 2 2006.285.08:18:00.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.08:18:00.72#ibcon#[27=AT07-04\r\n] 2006.285.08:18:00.72#ibcon#*before write, iclass 14, count 2 2006.285.08:18:00.72#ibcon#enter sib2, iclass 14, count 2 2006.285.08:18:00.72#ibcon#flushed, iclass 14, count 2 2006.285.08:18:00.72#ibcon#about to write, iclass 14, count 2 2006.285.08:18:00.72#ibcon#wrote, iclass 14, count 2 2006.285.08:18:00.72#ibcon#about to read 3, iclass 14, count 2 2006.285.08:18:00.75#ibcon#read 3, iclass 14, count 2 2006.285.08:18:00.75#ibcon#about to read 4, iclass 14, count 2 2006.285.08:18:00.75#ibcon#read 4, iclass 14, count 2 2006.285.08:18:00.75#ibcon#about to read 5, iclass 14, count 2 2006.285.08:18:00.75#ibcon#read 5, iclass 14, count 2 2006.285.08:18:00.75#ibcon#about to read 6, iclass 14, count 2 2006.285.08:18:00.75#ibcon#read 6, iclass 14, count 2 2006.285.08:18:00.75#ibcon#end of sib2, iclass 14, count 2 2006.285.08:18:00.75#ibcon#*after write, iclass 14, count 2 2006.285.08:18:00.75#ibcon#*before return 0, iclass 14, count 2 2006.285.08:18:00.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:18:00.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:18:00.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.08:18:00.75#ibcon#ireg 7 cls_cnt 0 2006.285.08:18:00.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:18:00.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:18:00.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:18:00.87#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:18:00.87#ibcon#first serial, iclass 14, count 0 2006.285.08:18:00.87#ibcon#enter sib2, iclass 14, count 0 2006.285.08:18:00.87#ibcon#flushed, iclass 14, count 0 2006.285.08:18:00.87#ibcon#about to write, iclass 14, count 0 2006.285.08:18:00.87#ibcon#wrote, iclass 14, count 0 2006.285.08:18:00.87#ibcon#about to read 3, iclass 14, count 0 2006.285.08:18:00.89#ibcon#read 3, iclass 14, count 0 2006.285.08:18:00.89#ibcon#about to read 4, iclass 14, count 0 2006.285.08:18:00.89#ibcon#read 4, iclass 14, count 0 2006.285.08:18:00.89#ibcon#about to read 5, iclass 14, count 0 2006.285.08:18:00.89#ibcon#read 5, iclass 14, count 0 2006.285.08:18:00.89#ibcon#about to read 6, iclass 14, count 0 2006.285.08:18:00.89#ibcon#read 6, iclass 14, count 0 2006.285.08:18:00.89#ibcon#end of sib2, iclass 14, count 0 2006.285.08:18:00.89#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:18:00.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:18:00.89#ibcon#[27=USB\r\n] 2006.285.08:18:00.89#ibcon#*before write, iclass 14, count 0 2006.285.08:18:00.89#ibcon#enter sib2, iclass 14, count 0 2006.285.08:18:00.89#ibcon#flushed, iclass 14, count 0 2006.285.08:18:00.89#ibcon#about to write, iclass 14, count 0 2006.285.08:18:00.89#ibcon#wrote, iclass 14, count 0 2006.285.08:18:00.89#ibcon#about to read 3, iclass 14, count 0 2006.285.08:18:00.92#ibcon#read 3, iclass 14, count 0 2006.285.08:18:00.92#ibcon#about to read 4, iclass 14, count 0 2006.285.08:18:00.92#ibcon#read 4, iclass 14, count 0 2006.285.08:18:00.92#ibcon#about to read 5, iclass 14, count 0 2006.285.08:18:00.92#ibcon#read 5, iclass 14, count 0 2006.285.08:18:00.92#ibcon#about to read 6, iclass 14, count 0 2006.285.08:18:00.92#ibcon#read 6, iclass 14, count 0 2006.285.08:18:00.92#ibcon#end of sib2, iclass 14, count 0 2006.285.08:18:00.92#ibcon#*after write, iclass 14, count 0 2006.285.08:18:00.92#ibcon#*before return 0, iclass 14, count 0 2006.285.08:18:00.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:18:00.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:18:00.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:18:00.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:18:00.92$vck44/vblo=8,744.99 2006.285.08:18:00.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.08:18:00.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.08:18:00.92#ibcon#ireg 17 cls_cnt 0 2006.285.08:18:00.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:18:00.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:18:00.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:18:00.92#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:18:00.92#ibcon#first serial, iclass 16, count 0 2006.285.08:18:00.92#ibcon#enter sib2, iclass 16, count 0 2006.285.08:18:00.92#ibcon#flushed, iclass 16, count 0 2006.285.08:18:00.92#ibcon#about to write, iclass 16, count 0 2006.285.08:18:00.92#ibcon#wrote, iclass 16, count 0 2006.285.08:18:00.92#ibcon#about to read 3, iclass 16, count 0 2006.285.08:18:00.94#ibcon#read 3, iclass 16, count 0 2006.285.08:18:00.94#ibcon#about to read 4, iclass 16, count 0 2006.285.08:18:00.94#ibcon#read 4, iclass 16, count 0 2006.285.08:18:00.94#ibcon#about to read 5, iclass 16, count 0 2006.285.08:18:00.94#ibcon#read 5, iclass 16, count 0 2006.285.08:18:00.94#ibcon#about to read 6, iclass 16, count 0 2006.285.08:18:00.94#ibcon#read 6, iclass 16, count 0 2006.285.08:18:00.94#ibcon#end of sib2, iclass 16, count 0 2006.285.08:18:00.94#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:18:00.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:18:00.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:18:00.94#ibcon#*before write, iclass 16, count 0 2006.285.08:18:00.94#ibcon#enter sib2, iclass 16, count 0 2006.285.08:18:00.94#ibcon#flushed, iclass 16, count 0 2006.285.08:18:00.94#ibcon#about to write, iclass 16, count 0 2006.285.08:18:00.94#ibcon#wrote, iclass 16, count 0 2006.285.08:18:00.94#ibcon#about to read 3, iclass 16, count 0 2006.285.08:18:00.98#ibcon#read 3, iclass 16, count 0 2006.285.08:18:00.98#ibcon#about to read 4, iclass 16, count 0 2006.285.08:18:00.98#ibcon#read 4, iclass 16, count 0 2006.285.08:18:00.98#ibcon#about to read 5, iclass 16, count 0 2006.285.08:18:00.98#ibcon#read 5, iclass 16, count 0 2006.285.08:18:00.98#ibcon#about to read 6, iclass 16, count 0 2006.285.08:18:00.98#ibcon#read 6, iclass 16, count 0 2006.285.08:18:00.98#ibcon#end of sib2, iclass 16, count 0 2006.285.08:18:00.98#ibcon#*after write, iclass 16, count 0 2006.285.08:18:00.98#ibcon#*before return 0, iclass 16, count 0 2006.285.08:18:00.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:18:00.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:18:00.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:18:00.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:18:00.98$vck44/vb=8,4 2006.285.08:18:00.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.08:18:00.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.08:18:00.98#ibcon#ireg 11 cls_cnt 2 2006.285.08:18:00.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:18:01.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:18:01.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:18:01.04#ibcon#enter wrdev, iclass 18, count 2 2006.285.08:18:01.04#ibcon#first serial, iclass 18, count 2 2006.285.08:18:01.04#ibcon#enter sib2, iclass 18, count 2 2006.285.08:18:01.04#ibcon#flushed, iclass 18, count 2 2006.285.08:18:01.04#ibcon#about to write, iclass 18, count 2 2006.285.08:18:01.04#ibcon#wrote, iclass 18, count 2 2006.285.08:18:01.04#ibcon#about to read 3, iclass 18, count 2 2006.285.08:18:01.06#ibcon#read 3, iclass 18, count 2 2006.285.08:18:01.06#ibcon#about to read 4, iclass 18, count 2 2006.285.08:18:01.06#ibcon#read 4, iclass 18, count 2 2006.285.08:18:01.06#ibcon#about to read 5, iclass 18, count 2 2006.285.08:18:01.06#ibcon#read 5, iclass 18, count 2 2006.285.08:18:01.06#ibcon#about to read 6, iclass 18, count 2 2006.285.08:18:01.06#ibcon#read 6, iclass 18, count 2 2006.285.08:18:01.06#ibcon#end of sib2, iclass 18, count 2 2006.285.08:18:01.06#ibcon#*mode == 0, iclass 18, count 2 2006.285.08:18:01.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.08:18:01.06#ibcon#[27=AT08-04\r\n] 2006.285.08:18:01.06#ibcon#*before write, iclass 18, count 2 2006.285.08:18:01.06#ibcon#enter sib2, iclass 18, count 2 2006.285.08:18:01.06#ibcon#flushed, iclass 18, count 2 2006.285.08:18:01.06#ibcon#about to write, iclass 18, count 2 2006.285.08:18:01.06#ibcon#wrote, iclass 18, count 2 2006.285.08:18:01.06#ibcon#about to read 3, iclass 18, count 2 2006.285.08:18:01.09#ibcon#read 3, iclass 18, count 2 2006.285.08:18:01.09#ibcon#about to read 4, iclass 18, count 2 2006.285.08:18:01.09#ibcon#read 4, iclass 18, count 2 2006.285.08:18:01.09#ibcon#about to read 5, iclass 18, count 2 2006.285.08:18:01.09#ibcon#read 5, iclass 18, count 2 2006.285.08:18:01.09#ibcon#about to read 6, iclass 18, count 2 2006.285.08:18:01.09#ibcon#read 6, iclass 18, count 2 2006.285.08:18:01.09#ibcon#end of sib2, iclass 18, count 2 2006.285.08:18:01.09#ibcon#*after write, iclass 18, count 2 2006.285.08:18:01.09#ibcon#*before return 0, iclass 18, count 2 2006.285.08:18:01.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:18:01.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:18:01.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.08:18:01.09#ibcon#ireg 7 cls_cnt 0 2006.285.08:18:01.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:18:01.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:18:01.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:18:01.21#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:18:01.21#ibcon#first serial, iclass 18, count 0 2006.285.08:18:01.21#ibcon#enter sib2, iclass 18, count 0 2006.285.08:18:01.21#ibcon#flushed, iclass 18, count 0 2006.285.08:18:01.21#ibcon#about to write, iclass 18, count 0 2006.285.08:18:01.21#ibcon#wrote, iclass 18, count 0 2006.285.08:18:01.21#ibcon#about to read 3, iclass 18, count 0 2006.285.08:18:01.23#ibcon#read 3, iclass 18, count 0 2006.285.08:18:01.23#ibcon#about to read 4, iclass 18, count 0 2006.285.08:18:01.23#ibcon#read 4, iclass 18, count 0 2006.285.08:18:01.23#ibcon#about to read 5, iclass 18, count 0 2006.285.08:18:01.23#ibcon#read 5, iclass 18, count 0 2006.285.08:18:01.23#ibcon#about to read 6, iclass 18, count 0 2006.285.08:18:01.23#ibcon#read 6, iclass 18, count 0 2006.285.08:18:01.23#ibcon#end of sib2, iclass 18, count 0 2006.285.08:18:01.23#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:18:01.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:18:01.23#ibcon#[27=USB\r\n] 2006.285.08:18:01.23#ibcon#*before write, iclass 18, count 0 2006.285.08:18:01.23#ibcon#enter sib2, iclass 18, count 0 2006.285.08:18:01.23#ibcon#flushed, iclass 18, count 0 2006.285.08:18:01.23#ibcon#about to write, iclass 18, count 0 2006.285.08:18:01.23#ibcon#wrote, iclass 18, count 0 2006.285.08:18:01.23#ibcon#about to read 3, iclass 18, count 0 2006.285.08:18:01.26#ibcon#read 3, iclass 18, count 0 2006.285.08:18:01.26#ibcon#about to read 4, iclass 18, count 0 2006.285.08:18:01.26#ibcon#read 4, iclass 18, count 0 2006.285.08:18:01.26#ibcon#about to read 5, iclass 18, count 0 2006.285.08:18:01.26#ibcon#read 5, iclass 18, count 0 2006.285.08:18:01.26#ibcon#about to read 6, iclass 18, count 0 2006.285.08:18:01.26#ibcon#read 6, iclass 18, count 0 2006.285.08:18:01.26#ibcon#end of sib2, iclass 18, count 0 2006.285.08:18:01.26#ibcon#*after write, iclass 18, count 0 2006.285.08:18:01.26#ibcon#*before return 0, iclass 18, count 0 2006.285.08:18:01.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:18:01.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:18:01.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:18:01.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:18:01.26$vck44/vabw=wide 2006.285.08:18:01.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.08:18:01.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.08:18:01.26#ibcon#ireg 8 cls_cnt 0 2006.285.08:18:01.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:18:01.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:18:01.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:18:01.26#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:18:01.26#ibcon#first serial, iclass 20, count 0 2006.285.08:18:01.26#ibcon#enter sib2, iclass 20, count 0 2006.285.08:18:01.26#ibcon#flushed, iclass 20, count 0 2006.285.08:18:01.26#ibcon#about to write, iclass 20, count 0 2006.285.08:18:01.26#ibcon#wrote, iclass 20, count 0 2006.285.08:18:01.26#ibcon#about to read 3, iclass 20, count 0 2006.285.08:18:01.28#ibcon#read 3, iclass 20, count 0 2006.285.08:18:01.28#ibcon#about to read 4, iclass 20, count 0 2006.285.08:18:01.28#ibcon#read 4, iclass 20, count 0 2006.285.08:18:01.28#ibcon#about to read 5, iclass 20, count 0 2006.285.08:18:01.28#ibcon#read 5, iclass 20, count 0 2006.285.08:18:01.28#ibcon#about to read 6, iclass 20, count 0 2006.285.08:18:01.28#ibcon#read 6, iclass 20, count 0 2006.285.08:18:01.28#ibcon#end of sib2, iclass 20, count 0 2006.285.08:18:01.28#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:18:01.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:18:01.28#ibcon#[25=BW32\r\n] 2006.285.08:18:01.28#ibcon#*before write, iclass 20, count 0 2006.285.08:18:01.28#ibcon#enter sib2, iclass 20, count 0 2006.285.08:18:01.28#ibcon#flushed, iclass 20, count 0 2006.285.08:18:01.28#ibcon#about to write, iclass 20, count 0 2006.285.08:18:01.28#ibcon#wrote, iclass 20, count 0 2006.285.08:18:01.28#ibcon#about to read 3, iclass 20, count 0 2006.285.08:18:01.31#ibcon#read 3, iclass 20, count 0 2006.285.08:18:01.31#ibcon#about to read 4, iclass 20, count 0 2006.285.08:18:01.31#ibcon#read 4, iclass 20, count 0 2006.285.08:18:01.31#ibcon#about to read 5, iclass 20, count 0 2006.285.08:18:01.31#ibcon#read 5, iclass 20, count 0 2006.285.08:18:01.31#ibcon#about to read 6, iclass 20, count 0 2006.285.08:18:01.31#ibcon#read 6, iclass 20, count 0 2006.285.08:18:01.31#ibcon#end of sib2, iclass 20, count 0 2006.285.08:18:01.31#ibcon#*after write, iclass 20, count 0 2006.285.08:18:01.31#ibcon#*before return 0, iclass 20, count 0 2006.285.08:18:01.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:18:01.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:18:01.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:18:01.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:18:01.31$vck44/vbbw=wide 2006.285.08:18:01.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.08:18:01.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.08:18:01.31#ibcon#ireg 8 cls_cnt 0 2006.285.08:18:01.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:18:01.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:18:01.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:18:01.38#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:18:01.38#ibcon#first serial, iclass 22, count 0 2006.285.08:18:01.38#ibcon#enter sib2, iclass 22, count 0 2006.285.08:18:01.38#ibcon#flushed, iclass 22, count 0 2006.285.08:18:01.38#ibcon#about to write, iclass 22, count 0 2006.285.08:18:01.38#ibcon#wrote, iclass 22, count 0 2006.285.08:18:01.38#ibcon#about to read 3, iclass 22, count 0 2006.285.08:18:01.40#ibcon#read 3, iclass 22, count 0 2006.285.08:18:01.40#ibcon#about to read 4, iclass 22, count 0 2006.285.08:18:01.40#ibcon#read 4, iclass 22, count 0 2006.285.08:18:01.40#ibcon#about to read 5, iclass 22, count 0 2006.285.08:18:01.40#ibcon#read 5, iclass 22, count 0 2006.285.08:18:01.40#ibcon#about to read 6, iclass 22, count 0 2006.285.08:18:01.40#ibcon#read 6, iclass 22, count 0 2006.285.08:18:01.40#ibcon#end of sib2, iclass 22, count 0 2006.285.08:18:01.40#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:18:01.40#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:18:01.40#ibcon#[27=BW32\r\n] 2006.285.08:18:01.40#ibcon#*before write, iclass 22, count 0 2006.285.08:18:01.40#ibcon#enter sib2, iclass 22, count 0 2006.285.08:18:01.40#ibcon#flushed, iclass 22, count 0 2006.285.08:18:01.40#ibcon#about to write, iclass 22, count 0 2006.285.08:18:01.40#ibcon#wrote, iclass 22, count 0 2006.285.08:18:01.40#ibcon#about to read 3, iclass 22, count 0 2006.285.08:18:01.43#ibcon#read 3, iclass 22, count 0 2006.285.08:18:01.43#ibcon#about to read 4, iclass 22, count 0 2006.285.08:18:01.43#ibcon#read 4, iclass 22, count 0 2006.285.08:18:01.43#ibcon#about to read 5, iclass 22, count 0 2006.285.08:18:01.43#ibcon#read 5, iclass 22, count 0 2006.285.08:18:01.43#ibcon#about to read 6, iclass 22, count 0 2006.285.08:18:01.43#ibcon#read 6, iclass 22, count 0 2006.285.08:18:01.43#ibcon#end of sib2, iclass 22, count 0 2006.285.08:18:01.43#ibcon#*after write, iclass 22, count 0 2006.285.08:18:01.43#ibcon#*before return 0, iclass 22, count 0 2006.285.08:18:01.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:18:01.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:18:01.43#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:18:01.43#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:18:01.43$setupk4/ifdk4 2006.285.08:18:01.43$ifdk4/lo= 2006.285.08:18:01.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:18:01.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:18:01.43$ifdk4/patch= 2006.285.08:18:01.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:18:01.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:18:01.44$setupk4/!*+20s 2006.285.08:18:01.94#abcon#<5=/04 1.6 3.6 22.52 811014.7\r\n> 2006.285.08:18:01.96#abcon#{5=INTERFACE CLEAR} 2006.285.08:18:02.02#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:18:12.11#abcon#<5=/04 1.7 3.6 22.52 811014.6\r\n> 2006.285.08:18:12.13#abcon#{5=INTERFACE CLEAR} 2006.285.08:18:12.19#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:18:15.96$setupk4/"tpicd 2006.285.08:18:15.96$setupk4/echo=off 2006.285.08:18:15.96$setupk4/xlog=off 2006.285.08:18:15.96:!2006.285.08:19:10 2006.285.08:18:21.14#trakl#Source acquired 2006.285.08:18:23.14#flagr#flagr/antenna,acquired 2006.285.08:19:10.00:preob 2006.285.08:19:10.14/onsource/TRACKING 2006.285.08:19:10.14:!2006.285.08:19:20 2006.285.08:19:20.00:"tape 2006.285.08:19:20.00:"st=record 2006.285.08:19:20.00:data_valid=on 2006.285.08:19:20.00:midob 2006.285.08:19:20.14/onsource/TRACKING 2006.285.08:19:20.14/wx/22.49,1014.7,81 2006.285.08:19:20.23/cable/+6.4746E-03 2006.285.08:19:21.32/va/01,07,usb,yes,32,34 2006.285.08:19:21.32/va/02,06,usb,yes,32,32 2006.285.08:19:21.32/va/03,07,usb,yes,31,33 2006.285.08:19:21.32/va/04,06,usb,yes,33,34 2006.285.08:19:21.32/va/05,03,usb,yes,32,33 2006.285.08:19:21.32/va/06,04,usb,yes,29,28 2006.285.08:19:21.32/va/07,04,usb,yes,29,30 2006.285.08:19:21.32/va/08,03,usb,yes,30,37 2006.285.08:19:21.55/valo/01,524.99,yes,locked 2006.285.08:19:21.55/valo/02,534.99,yes,locked 2006.285.08:19:21.55/valo/03,564.99,yes,locked 2006.285.08:19:21.55/valo/04,624.99,yes,locked 2006.285.08:19:21.55/valo/05,734.99,yes,locked 2006.285.08:19:21.55/valo/06,814.99,yes,locked 2006.285.08:19:21.55/valo/07,864.99,yes,locked 2006.285.08:19:21.55/valo/08,884.99,yes,locked 2006.285.08:19:22.64/vb/01,04,usb,yes,30,28 2006.285.08:19:22.64/vb/02,05,usb,yes,29,29 2006.285.08:19:22.64/vb/03,04,usb,yes,30,33 2006.285.08:19:22.64/vb/04,05,usb,yes,30,29 2006.285.08:19:22.64/vb/05,04,usb,yes,26,29 2006.285.08:19:22.64/vb/06,03,usb,yes,38,34 2006.285.08:19:22.64/vb/07,04,usb,yes,31,31 2006.285.08:19:22.64/vb/08,04,usb,yes,28,31 2006.285.08:19:22.87/vblo/01,629.99,yes,locked 2006.285.08:19:22.87/vblo/02,634.99,yes,locked 2006.285.08:19:22.87/vblo/03,649.99,yes,locked 2006.285.08:19:22.87/vblo/04,679.99,yes,locked 2006.285.08:19:22.87/vblo/05,709.99,yes,locked 2006.285.08:19:22.87/vblo/06,719.99,yes,locked 2006.285.08:19:22.87/vblo/07,734.99,yes,locked 2006.285.08:19:22.87/vblo/08,744.99,yes,locked 2006.285.08:19:23.02/vabw/8 2006.285.08:19:23.17/vbbw/8 2006.285.08:19:23.26/xfe/off,on,12.0 2006.285.08:19:23.68/ifatt/23,28,28,28 2006.285.08:19:24.07/fmout-gps/S +2.79E-07 2006.285.08:19:24.09:!2006.285.08:20:10 2006.285.08:20:10.00:data_valid=off 2006.285.08:20:10.00:"et 2006.285.08:20:10.00:!+3s 2006.285.08:20:13.01:"tape 2006.285.08:20:13.01:postob 2006.285.08:20:13.23/cable/+6.4775E-03 2006.285.08:20:13.23/wx/22.47,1014.7,81 2006.285.08:20:14.07/fmout-gps/S +2.81E-07 2006.285.08:20:14.07:scan_name=285-0825,jd0610,40 2006.285.08:20:14.07:source=1921-293,192451.06,-291430.1,2000.0,ccw 2006.285.08:20:15.14#flagr#flagr/antenna,new-source 2006.285.08:20:15.14:checkk5 2006.285.08:20:15.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:20:16.15/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:20:16.58/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:20:16.97/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:20:17.47/chk_obsdata//k5ts1/T2850819??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.08:20:17.88/chk_obsdata//k5ts2/T2850819??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.08:20:18.26/chk_obsdata//k5ts3/T2850819??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.08:20:18.62/chk_obsdata//k5ts4/T2850819??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.08:20:19.41/k5log//k5ts1_log_newline 2006.285.08:20:20.25/k5log//k5ts2_log_newline 2006.285.08:20:21.26/k5log//k5ts3_log_newline 2006.285.08:20:22.03/k5log//k5ts4_log_newline 2006.285.08:20:22.05/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:20:22.05:setupk4=1 2006.285.08:20:22.05$setupk4/echo=on 2006.285.08:20:22.05$setupk4/pcalon 2006.285.08:20:22.05$pcalon/"no phase cal control is implemented here 2006.285.08:20:22.05$setupk4/"tpicd=stop 2006.285.08:20:22.05$setupk4/"rec=synch_on 2006.285.08:20:22.05$setupk4/"rec_mode=128 2006.285.08:20:22.05$setupk4/!* 2006.285.08:20:22.05$setupk4/recpk4 2006.285.08:20:22.05$recpk4/recpatch= 2006.285.08:20:22.05$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:20:22.05$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:20:22.05$setupk4/vck44 2006.285.08:20:22.05$vck44/valo=1,524.99 2006.285.08:20:22.05#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.08:20:22.05#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.08:20:22.05#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:22.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:20:22.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:20:22.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:20:22.05#ibcon#enter wrdev, iclass 11, count 0 2006.285.08:20:22.05#ibcon#first serial, iclass 11, count 0 2006.285.08:20:22.05#ibcon#enter sib2, iclass 11, count 0 2006.285.08:20:22.05#ibcon#flushed, iclass 11, count 0 2006.285.08:20:22.05#ibcon#about to write, iclass 11, count 0 2006.285.08:20:22.05#ibcon#wrote, iclass 11, count 0 2006.285.08:20:22.05#ibcon#about to read 3, iclass 11, count 0 2006.285.08:20:22.07#ibcon#read 3, iclass 11, count 0 2006.285.08:20:22.07#ibcon#about to read 4, iclass 11, count 0 2006.285.08:20:22.07#ibcon#read 4, iclass 11, count 0 2006.285.08:20:22.07#ibcon#about to read 5, iclass 11, count 0 2006.285.08:20:22.07#ibcon#read 5, iclass 11, count 0 2006.285.08:20:22.07#ibcon#about to read 6, iclass 11, count 0 2006.285.08:20:22.07#ibcon#read 6, iclass 11, count 0 2006.285.08:20:22.07#ibcon#end of sib2, iclass 11, count 0 2006.285.08:20:22.07#ibcon#*mode == 0, iclass 11, count 0 2006.285.08:20:22.07#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.08:20:22.07#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:20:22.07#ibcon#*before write, iclass 11, count 0 2006.285.08:20:22.07#ibcon#enter sib2, iclass 11, count 0 2006.285.08:20:22.07#ibcon#flushed, iclass 11, count 0 2006.285.08:20:22.07#ibcon#about to write, iclass 11, count 0 2006.285.08:20:22.07#ibcon#wrote, iclass 11, count 0 2006.285.08:20:22.07#ibcon#about to read 3, iclass 11, count 0 2006.285.08:20:22.12#ibcon#read 3, iclass 11, count 0 2006.285.08:20:22.12#ibcon#about to read 4, iclass 11, count 0 2006.285.08:20:22.12#ibcon#read 4, iclass 11, count 0 2006.285.08:20:22.12#ibcon#about to read 5, iclass 11, count 0 2006.285.08:20:22.12#ibcon#read 5, iclass 11, count 0 2006.285.08:20:22.12#ibcon#about to read 6, iclass 11, count 0 2006.285.08:20:22.12#ibcon#read 6, iclass 11, count 0 2006.285.08:20:22.12#ibcon#end of sib2, iclass 11, count 0 2006.285.08:20:22.12#ibcon#*after write, iclass 11, count 0 2006.285.08:20:22.12#ibcon#*before return 0, iclass 11, count 0 2006.285.08:20:22.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:20:22.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:20:22.12#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.08:20:22.12#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.08:20:22.12$vck44/va=1,7 2006.285.08:20:22.12#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.08:20:22.12#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.08:20:22.12#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:22.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:20:22.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:20:22.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:20:22.12#ibcon#enter wrdev, iclass 13, count 2 2006.285.08:20:22.12#ibcon#first serial, iclass 13, count 2 2006.285.08:20:22.12#ibcon#enter sib2, iclass 13, count 2 2006.285.08:20:22.12#ibcon#flushed, iclass 13, count 2 2006.285.08:20:22.12#ibcon#about to write, iclass 13, count 2 2006.285.08:20:22.12#ibcon#wrote, iclass 13, count 2 2006.285.08:20:22.12#ibcon#about to read 3, iclass 13, count 2 2006.285.08:20:22.14#ibcon#read 3, iclass 13, count 2 2006.285.08:20:22.14#ibcon#about to read 4, iclass 13, count 2 2006.285.08:20:22.14#ibcon#read 4, iclass 13, count 2 2006.285.08:20:22.14#ibcon#about to read 5, iclass 13, count 2 2006.285.08:20:22.14#ibcon#read 5, iclass 13, count 2 2006.285.08:20:22.14#ibcon#about to read 6, iclass 13, count 2 2006.285.08:20:22.14#ibcon#read 6, iclass 13, count 2 2006.285.08:20:22.14#ibcon#end of sib2, iclass 13, count 2 2006.285.08:20:22.14#ibcon#*mode == 0, iclass 13, count 2 2006.285.08:20:22.14#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.08:20:22.14#ibcon#[25=AT01-07\r\n] 2006.285.08:20:22.14#ibcon#*before write, iclass 13, count 2 2006.285.08:20:22.14#ibcon#enter sib2, iclass 13, count 2 2006.285.08:20:22.14#ibcon#flushed, iclass 13, count 2 2006.285.08:20:22.14#ibcon#about to write, iclass 13, count 2 2006.285.08:20:22.14#ibcon#wrote, iclass 13, count 2 2006.285.08:20:22.14#ibcon#about to read 3, iclass 13, count 2 2006.285.08:20:22.17#ibcon#read 3, iclass 13, count 2 2006.285.08:20:22.17#ibcon#about to read 4, iclass 13, count 2 2006.285.08:20:22.17#ibcon#read 4, iclass 13, count 2 2006.285.08:20:22.17#ibcon#about to read 5, iclass 13, count 2 2006.285.08:20:22.17#ibcon#read 5, iclass 13, count 2 2006.285.08:20:22.17#ibcon#about to read 6, iclass 13, count 2 2006.285.08:20:22.17#ibcon#read 6, iclass 13, count 2 2006.285.08:20:22.17#ibcon#end of sib2, iclass 13, count 2 2006.285.08:20:22.17#ibcon#*after write, iclass 13, count 2 2006.285.08:20:22.17#ibcon#*before return 0, iclass 13, count 2 2006.285.08:20:22.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:20:22.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:20:22.17#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.08:20:22.17#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:22.17#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:20:22.29#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:20:22.29#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:20:22.29#ibcon#enter wrdev, iclass 13, count 0 2006.285.08:20:22.29#ibcon#first serial, iclass 13, count 0 2006.285.08:20:22.29#ibcon#enter sib2, iclass 13, count 0 2006.285.08:20:22.29#ibcon#flushed, iclass 13, count 0 2006.285.08:20:22.29#ibcon#about to write, iclass 13, count 0 2006.285.08:20:22.29#ibcon#wrote, iclass 13, count 0 2006.285.08:20:22.29#ibcon#about to read 3, iclass 13, count 0 2006.285.08:20:22.31#ibcon#read 3, iclass 13, count 0 2006.285.08:20:22.31#ibcon#about to read 4, iclass 13, count 0 2006.285.08:20:22.31#ibcon#read 4, iclass 13, count 0 2006.285.08:20:22.31#ibcon#about to read 5, iclass 13, count 0 2006.285.08:20:22.31#ibcon#read 5, iclass 13, count 0 2006.285.08:20:22.31#ibcon#about to read 6, iclass 13, count 0 2006.285.08:20:22.31#ibcon#read 6, iclass 13, count 0 2006.285.08:20:22.31#ibcon#end of sib2, iclass 13, count 0 2006.285.08:20:22.31#ibcon#*mode == 0, iclass 13, count 0 2006.285.08:20:22.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.08:20:22.31#ibcon#[25=USB\r\n] 2006.285.08:20:22.31#ibcon#*before write, iclass 13, count 0 2006.285.08:20:22.31#ibcon#enter sib2, iclass 13, count 0 2006.285.08:20:22.31#ibcon#flushed, iclass 13, count 0 2006.285.08:20:22.31#ibcon#about to write, iclass 13, count 0 2006.285.08:20:22.31#ibcon#wrote, iclass 13, count 0 2006.285.08:20:22.31#ibcon#about to read 3, iclass 13, count 0 2006.285.08:20:22.34#ibcon#read 3, iclass 13, count 0 2006.285.08:20:22.34#ibcon#about to read 4, iclass 13, count 0 2006.285.08:20:22.34#ibcon#read 4, iclass 13, count 0 2006.285.08:20:22.34#ibcon#about to read 5, iclass 13, count 0 2006.285.08:20:22.34#ibcon#read 5, iclass 13, count 0 2006.285.08:20:22.34#ibcon#about to read 6, iclass 13, count 0 2006.285.08:20:22.34#ibcon#read 6, iclass 13, count 0 2006.285.08:20:22.34#ibcon#end of sib2, iclass 13, count 0 2006.285.08:20:22.34#ibcon#*after write, iclass 13, count 0 2006.285.08:20:22.34#ibcon#*before return 0, iclass 13, count 0 2006.285.08:20:22.34#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:20:22.34#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:20:22.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.08:20:22.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.08:20:22.34$vck44/valo=2,534.99 2006.285.08:20:22.34#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.08:20:22.34#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.08:20:22.34#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:22.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:20:22.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:20:22.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:20:22.34#ibcon#enter wrdev, iclass 15, count 0 2006.285.08:20:22.34#ibcon#first serial, iclass 15, count 0 2006.285.08:20:22.34#ibcon#enter sib2, iclass 15, count 0 2006.285.08:20:22.34#ibcon#flushed, iclass 15, count 0 2006.285.08:20:22.34#ibcon#about to write, iclass 15, count 0 2006.285.08:20:22.34#ibcon#wrote, iclass 15, count 0 2006.285.08:20:22.34#ibcon#about to read 3, iclass 15, count 0 2006.285.08:20:22.36#ibcon#read 3, iclass 15, count 0 2006.285.08:20:22.36#ibcon#about to read 4, iclass 15, count 0 2006.285.08:20:22.36#ibcon#read 4, iclass 15, count 0 2006.285.08:20:22.36#ibcon#about to read 5, iclass 15, count 0 2006.285.08:20:22.36#ibcon#read 5, iclass 15, count 0 2006.285.08:20:22.36#ibcon#about to read 6, iclass 15, count 0 2006.285.08:20:22.36#ibcon#read 6, iclass 15, count 0 2006.285.08:20:22.36#ibcon#end of sib2, iclass 15, count 0 2006.285.08:20:22.36#ibcon#*mode == 0, iclass 15, count 0 2006.285.08:20:22.36#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.08:20:22.36#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:20:22.36#ibcon#*before write, iclass 15, count 0 2006.285.08:20:22.36#ibcon#enter sib2, iclass 15, count 0 2006.285.08:20:22.36#ibcon#flushed, iclass 15, count 0 2006.285.08:20:22.36#ibcon#about to write, iclass 15, count 0 2006.285.08:20:22.36#ibcon#wrote, iclass 15, count 0 2006.285.08:20:22.36#ibcon#about to read 3, iclass 15, count 0 2006.285.08:20:22.40#ibcon#read 3, iclass 15, count 0 2006.285.08:20:22.40#ibcon#about to read 4, iclass 15, count 0 2006.285.08:20:22.40#ibcon#read 4, iclass 15, count 0 2006.285.08:20:22.40#ibcon#about to read 5, iclass 15, count 0 2006.285.08:20:22.40#ibcon#read 5, iclass 15, count 0 2006.285.08:20:22.40#ibcon#about to read 6, iclass 15, count 0 2006.285.08:20:22.40#ibcon#read 6, iclass 15, count 0 2006.285.08:20:22.40#ibcon#end of sib2, iclass 15, count 0 2006.285.08:20:22.40#ibcon#*after write, iclass 15, count 0 2006.285.08:20:22.40#ibcon#*before return 0, iclass 15, count 0 2006.285.08:20:22.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:20:22.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:20:22.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.08:20:22.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.08:20:22.40$vck44/va=2,6 2006.285.08:20:22.40#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.08:20:22.40#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.08:20:22.40#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:22.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:20:22.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:20:22.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:20:22.46#ibcon#enter wrdev, iclass 17, count 2 2006.285.08:20:22.46#ibcon#first serial, iclass 17, count 2 2006.285.08:20:22.46#ibcon#enter sib2, iclass 17, count 2 2006.285.08:20:22.46#ibcon#flushed, iclass 17, count 2 2006.285.08:20:22.46#ibcon#about to write, iclass 17, count 2 2006.285.08:20:22.46#ibcon#wrote, iclass 17, count 2 2006.285.08:20:22.46#ibcon#about to read 3, iclass 17, count 2 2006.285.08:20:22.48#ibcon#read 3, iclass 17, count 2 2006.285.08:20:22.48#ibcon#about to read 4, iclass 17, count 2 2006.285.08:20:22.48#ibcon#read 4, iclass 17, count 2 2006.285.08:20:22.48#ibcon#about to read 5, iclass 17, count 2 2006.285.08:20:22.48#ibcon#read 5, iclass 17, count 2 2006.285.08:20:22.48#ibcon#about to read 6, iclass 17, count 2 2006.285.08:20:22.48#ibcon#read 6, iclass 17, count 2 2006.285.08:20:22.48#ibcon#end of sib2, iclass 17, count 2 2006.285.08:20:22.48#ibcon#*mode == 0, iclass 17, count 2 2006.285.08:20:22.48#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.08:20:22.48#ibcon#[25=AT02-06\r\n] 2006.285.08:20:22.48#ibcon#*before write, iclass 17, count 2 2006.285.08:20:22.48#ibcon#enter sib2, iclass 17, count 2 2006.285.08:20:22.48#ibcon#flushed, iclass 17, count 2 2006.285.08:20:22.48#ibcon#about to write, iclass 17, count 2 2006.285.08:20:22.48#ibcon#wrote, iclass 17, count 2 2006.285.08:20:22.48#ibcon#about to read 3, iclass 17, count 2 2006.285.08:20:22.51#ibcon#read 3, iclass 17, count 2 2006.285.08:20:22.51#ibcon#about to read 4, iclass 17, count 2 2006.285.08:20:22.51#ibcon#read 4, iclass 17, count 2 2006.285.08:20:22.51#ibcon#about to read 5, iclass 17, count 2 2006.285.08:20:22.51#ibcon#read 5, iclass 17, count 2 2006.285.08:20:22.51#ibcon#about to read 6, iclass 17, count 2 2006.285.08:20:22.51#ibcon#read 6, iclass 17, count 2 2006.285.08:20:22.51#ibcon#end of sib2, iclass 17, count 2 2006.285.08:20:22.51#ibcon#*after write, iclass 17, count 2 2006.285.08:20:22.51#ibcon#*before return 0, iclass 17, count 2 2006.285.08:20:22.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:20:22.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:20:22.51#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.08:20:22.51#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:22.51#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:20:22.63#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:20:22.63#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:20:22.63#ibcon#enter wrdev, iclass 17, count 0 2006.285.08:20:22.63#ibcon#first serial, iclass 17, count 0 2006.285.08:20:22.63#ibcon#enter sib2, iclass 17, count 0 2006.285.08:20:22.63#ibcon#flushed, iclass 17, count 0 2006.285.08:20:22.63#ibcon#about to write, iclass 17, count 0 2006.285.08:20:22.63#ibcon#wrote, iclass 17, count 0 2006.285.08:20:22.63#ibcon#about to read 3, iclass 17, count 0 2006.285.08:20:22.65#ibcon#read 3, iclass 17, count 0 2006.285.08:20:22.65#ibcon#about to read 4, iclass 17, count 0 2006.285.08:20:22.65#ibcon#read 4, iclass 17, count 0 2006.285.08:20:22.65#ibcon#about to read 5, iclass 17, count 0 2006.285.08:20:22.65#ibcon#read 5, iclass 17, count 0 2006.285.08:20:22.65#ibcon#about to read 6, iclass 17, count 0 2006.285.08:20:22.65#ibcon#read 6, iclass 17, count 0 2006.285.08:20:22.65#ibcon#end of sib2, iclass 17, count 0 2006.285.08:20:22.65#ibcon#*mode == 0, iclass 17, count 0 2006.285.08:20:22.65#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.08:20:22.65#ibcon#[25=USB\r\n] 2006.285.08:20:22.65#ibcon#*before write, iclass 17, count 0 2006.285.08:20:22.65#ibcon#enter sib2, iclass 17, count 0 2006.285.08:20:22.65#ibcon#flushed, iclass 17, count 0 2006.285.08:20:22.65#ibcon#about to write, iclass 17, count 0 2006.285.08:20:22.65#ibcon#wrote, iclass 17, count 0 2006.285.08:20:22.65#ibcon#about to read 3, iclass 17, count 0 2006.285.08:20:22.68#ibcon#read 3, iclass 17, count 0 2006.285.08:20:22.68#ibcon#about to read 4, iclass 17, count 0 2006.285.08:20:22.68#ibcon#read 4, iclass 17, count 0 2006.285.08:20:22.68#ibcon#about to read 5, iclass 17, count 0 2006.285.08:20:22.68#ibcon#read 5, iclass 17, count 0 2006.285.08:20:22.68#ibcon#about to read 6, iclass 17, count 0 2006.285.08:20:22.68#ibcon#read 6, iclass 17, count 0 2006.285.08:20:22.68#ibcon#end of sib2, iclass 17, count 0 2006.285.08:20:22.68#ibcon#*after write, iclass 17, count 0 2006.285.08:20:22.68#ibcon#*before return 0, iclass 17, count 0 2006.285.08:20:22.68#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:20:22.68#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:20:22.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.08:20:22.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.08:20:22.68$vck44/valo=3,564.99 2006.285.08:20:22.68#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.08:20:22.68#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.08:20:22.68#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:22.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:20:22.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:20:22.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:20:22.68#ibcon#enter wrdev, iclass 19, count 0 2006.285.08:20:22.68#ibcon#first serial, iclass 19, count 0 2006.285.08:20:22.68#ibcon#enter sib2, iclass 19, count 0 2006.285.08:20:22.68#ibcon#flushed, iclass 19, count 0 2006.285.08:20:22.68#ibcon#about to write, iclass 19, count 0 2006.285.08:20:22.68#ibcon#wrote, iclass 19, count 0 2006.285.08:20:22.68#ibcon#about to read 3, iclass 19, count 0 2006.285.08:20:22.70#ibcon#read 3, iclass 19, count 0 2006.285.08:20:22.70#ibcon#about to read 4, iclass 19, count 0 2006.285.08:20:22.70#ibcon#read 4, iclass 19, count 0 2006.285.08:20:22.70#ibcon#about to read 5, iclass 19, count 0 2006.285.08:20:22.70#ibcon#read 5, iclass 19, count 0 2006.285.08:20:22.70#ibcon#about to read 6, iclass 19, count 0 2006.285.08:20:22.70#ibcon#read 6, iclass 19, count 0 2006.285.08:20:22.70#ibcon#end of sib2, iclass 19, count 0 2006.285.08:20:22.70#ibcon#*mode == 0, iclass 19, count 0 2006.285.08:20:22.70#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.08:20:22.70#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:20:22.70#ibcon#*before write, iclass 19, count 0 2006.285.08:20:22.70#ibcon#enter sib2, iclass 19, count 0 2006.285.08:20:22.70#ibcon#flushed, iclass 19, count 0 2006.285.08:20:22.70#ibcon#about to write, iclass 19, count 0 2006.285.08:20:22.70#ibcon#wrote, iclass 19, count 0 2006.285.08:20:22.70#ibcon#about to read 3, iclass 19, count 0 2006.285.08:20:22.74#ibcon#read 3, iclass 19, count 0 2006.285.08:20:22.74#ibcon#about to read 4, iclass 19, count 0 2006.285.08:20:22.74#ibcon#read 4, iclass 19, count 0 2006.285.08:20:22.74#ibcon#about to read 5, iclass 19, count 0 2006.285.08:20:22.74#ibcon#read 5, iclass 19, count 0 2006.285.08:20:22.74#ibcon#about to read 6, iclass 19, count 0 2006.285.08:20:22.74#ibcon#read 6, iclass 19, count 0 2006.285.08:20:22.74#ibcon#end of sib2, iclass 19, count 0 2006.285.08:20:22.74#ibcon#*after write, iclass 19, count 0 2006.285.08:20:22.74#ibcon#*before return 0, iclass 19, count 0 2006.285.08:20:22.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:20:22.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:20:22.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.08:20:22.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.08:20:22.74$vck44/va=3,7 2006.285.08:20:22.74#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.08:20:22.74#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.08:20:22.74#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:22.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:20:22.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:20:22.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:20:22.80#ibcon#enter wrdev, iclass 21, count 2 2006.285.08:20:22.80#ibcon#first serial, iclass 21, count 2 2006.285.08:20:22.80#ibcon#enter sib2, iclass 21, count 2 2006.285.08:20:22.80#ibcon#flushed, iclass 21, count 2 2006.285.08:20:22.80#ibcon#about to write, iclass 21, count 2 2006.285.08:20:22.80#ibcon#wrote, iclass 21, count 2 2006.285.08:20:22.80#ibcon#about to read 3, iclass 21, count 2 2006.285.08:20:22.82#ibcon#read 3, iclass 21, count 2 2006.285.08:20:22.82#ibcon#about to read 4, iclass 21, count 2 2006.285.08:20:22.82#ibcon#read 4, iclass 21, count 2 2006.285.08:20:22.82#ibcon#about to read 5, iclass 21, count 2 2006.285.08:20:22.82#ibcon#read 5, iclass 21, count 2 2006.285.08:20:22.82#ibcon#about to read 6, iclass 21, count 2 2006.285.08:20:22.82#ibcon#read 6, iclass 21, count 2 2006.285.08:20:22.82#ibcon#end of sib2, iclass 21, count 2 2006.285.08:20:22.82#ibcon#*mode == 0, iclass 21, count 2 2006.285.08:20:22.82#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.08:20:22.82#ibcon#[25=AT03-07\r\n] 2006.285.08:20:22.82#ibcon#*before write, iclass 21, count 2 2006.285.08:20:22.82#ibcon#enter sib2, iclass 21, count 2 2006.285.08:20:22.82#ibcon#flushed, iclass 21, count 2 2006.285.08:20:22.82#ibcon#about to write, iclass 21, count 2 2006.285.08:20:22.82#ibcon#wrote, iclass 21, count 2 2006.285.08:20:22.82#ibcon#about to read 3, iclass 21, count 2 2006.285.08:20:22.85#ibcon#read 3, iclass 21, count 2 2006.285.08:20:22.85#ibcon#about to read 4, iclass 21, count 2 2006.285.08:20:22.85#ibcon#read 4, iclass 21, count 2 2006.285.08:20:22.85#ibcon#about to read 5, iclass 21, count 2 2006.285.08:20:22.85#ibcon#read 5, iclass 21, count 2 2006.285.08:20:22.85#ibcon#about to read 6, iclass 21, count 2 2006.285.08:20:22.85#ibcon#read 6, iclass 21, count 2 2006.285.08:20:22.85#ibcon#end of sib2, iclass 21, count 2 2006.285.08:20:22.85#ibcon#*after write, iclass 21, count 2 2006.285.08:20:22.85#ibcon#*before return 0, iclass 21, count 2 2006.285.08:20:22.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:20:22.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:20:22.85#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.08:20:22.85#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:22.85#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:20:22.97#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:20:22.97#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:20:22.97#ibcon#enter wrdev, iclass 21, count 0 2006.285.08:20:22.97#ibcon#first serial, iclass 21, count 0 2006.285.08:20:22.97#ibcon#enter sib2, iclass 21, count 0 2006.285.08:20:22.97#ibcon#flushed, iclass 21, count 0 2006.285.08:20:22.97#ibcon#about to write, iclass 21, count 0 2006.285.08:20:22.97#ibcon#wrote, iclass 21, count 0 2006.285.08:20:22.97#ibcon#about to read 3, iclass 21, count 0 2006.285.08:20:22.99#ibcon#read 3, iclass 21, count 0 2006.285.08:20:22.99#ibcon#about to read 4, iclass 21, count 0 2006.285.08:20:22.99#ibcon#read 4, iclass 21, count 0 2006.285.08:20:22.99#ibcon#about to read 5, iclass 21, count 0 2006.285.08:20:22.99#ibcon#read 5, iclass 21, count 0 2006.285.08:20:22.99#ibcon#about to read 6, iclass 21, count 0 2006.285.08:20:22.99#ibcon#read 6, iclass 21, count 0 2006.285.08:20:22.99#ibcon#end of sib2, iclass 21, count 0 2006.285.08:20:22.99#ibcon#*mode == 0, iclass 21, count 0 2006.285.08:20:22.99#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.08:20:22.99#ibcon#[25=USB\r\n] 2006.285.08:20:22.99#ibcon#*before write, iclass 21, count 0 2006.285.08:20:22.99#ibcon#enter sib2, iclass 21, count 0 2006.285.08:20:22.99#ibcon#flushed, iclass 21, count 0 2006.285.08:20:22.99#ibcon#about to write, iclass 21, count 0 2006.285.08:20:22.99#ibcon#wrote, iclass 21, count 0 2006.285.08:20:22.99#ibcon#about to read 3, iclass 21, count 0 2006.285.08:20:23.02#ibcon#read 3, iclass 21, count 0 2006.285.08:20:23.02#ibcon#about to read 4, iclass 21, count 0 2006.285.08:20:23.02#ibcon#read 4, iclass 21, count 0 2006.285.08:20:23.02#ibcon#about to read 5, iclass 21, count 0 2006.285.08:20:23.02#ibcon#read 5, iclass 21, count 0 2006.285.08:20:23.02#ibcon#about to read 6, iclass 21, count 0 2006.285.08:20:23.02#ibcon#read 6, iclass 21, count 0 2006.285.08:20:23.02#ibcon#end of sib2, iclass 21, count 0 2006.285.08:20:23.02#ibcon#*after write, iclass 21, count 0 2006.285.08:20:23.02#ibcon#*before return 0, iclass 21, count 0 2006.285.08:20:23.02#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:20:23.02#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:20:23.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.08:20:23.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.08:20:23.02$vck44/valo=4,624.99 2006.285.08:20:23.02#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.08:20:23.02#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.08:20:23.02#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:23.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:20:23.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:20:23.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:20:23.02#ibcon#enter wrdev, iclass 23, count 0 2006.285.08:20:23.02#ibcon#first serial, iclass 23, count 0 2006.285.08:20:23.02#ibcon#enter sib2, iclass 23, count 0 2006.285.08:20:23.02#ibcon#flushed, iclass 23, count 0 2006.285.08:20:23.02#ibcon#about to write, iclass 23, count 0 2006.285.08:20:23.02#ibcon#wrote, iclass 23, count 0 2006.285.08:20:23.02#ibcon#about to read 3, iclass 23, count 0 2006.285.08:20:23.04#ibcon#read 3, iclass 23, count 0 2006.285.08:20:23.04#ibcon#about to read 4, iclass 23, count 0 2006.285.08:20:23.04#ibcon#read 4, iclass 23, count 0 2006.285.08:20:23.04#ibcon#about to read 5, iclass 23, count 0 2006.285.08:20:23.04#ibcon#read 5, iclass 23, count 0 2006.285.08:20:23.04#ibcon#about to read 6, iclass 23, count 0 2006.285.08:20:23.04#ibcon#read 6, iclass 23, count 0 2006.285.08:20:23.04#ibcon#end of sib2, iclass 23, count 0 2006.285.08:20:23.04#ibcon#*mode == 0, iclass 23, count 0 2006.285.08:20:23.04#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.08:20:23.04#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:20:23.04#ibcon#*before write, iclass 23, count 0 2006.285.08:20:23.04#ibcon#enter sib2, iclass 23, count 0 2006.285.08:20:23.04#ibcon#flushed, iclass 23, count 0 2006.285.08:20:23.04#ibcon#about to write, iclass 23, count 0 2006.285.08:20:23.04#ibcon#wrote, iclass 23, count 0 2006.285.08:20:23.04#ibcon#about to read 3, iclass 23, count 0 2006.285.08:20:23.08#ibcon#read 3, iclass 23, count 0 2006.285.08:20:23.08#ibcon#about to read 4, iclass 23, count 0 2006.285.08:20:23.08#ibcon#read 4, iclass 23, count 0 2006.285.08:20:23.08#ibcon#about to read 5, iclass 23, count 0 2006.285.08:20:23.08#ibcon#read 5, iclass 23, count 0 2006.285.08:20:23.08#ibcon#about to read 6, iclass 23, count 0 2006.285.08:20:23.08#ibcon#read 6, iclass 23, count 0 2006.285.08:20:23.08#ibcon#end of sib2, iclass 23, count 0 2006.285.08:20:23.08#ibcon#*after write, iclass 23, count 0 2006.285.08:20:23.08#ibcon#*before return 0, iclass 23, count 0 2006.285.08:20:23.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:20:23.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:20:23.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.08:20:23.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.08:20:23.08$vck44/va=4,6 2006.285.08:20:23.08#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.08:20:23.08#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.08:20:23.08#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:23.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:20:23.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:20:23.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:20:23.14#ibcon#enter wrdev, iclass 25, count 2 2006.285.08:20:23.14#ibcon#first serial, iclass 25, count 2 2006.285.08:20:23.14#ibcon#enter sib2, iclass 25, count 2 2006.285.08:20:23.14#ibcon#flushed, iclass 25, count 2 2006.285.08:20:23.14#ibcon#about to write, iclass 25, count 2 2006.285.08:20:23.14#ibcon#wrote, iclass 25, count 2 2006.285.08:20:23.14#ibcon#about to read 3, iclass 25, count 2 2006.285.08:20:23.16#ibcon#read 3, iclass 25, count 2 2006.285.08:20:23.16#ibcon#about to read 4, iclass 25, count 2 2006.285.08:20:23.16#ibcon#read 4, iclass 25, count 2 2006.285.08:20:23.16#ibcon#about to read 5, iclass 25, count 2 2006.285.08:20:23.16#ibcon#read 5, iclass 25, count 2 2006.285.08:20:23.16#ibcon#about to read 6, iclass 25, count 2 2006.285.08:20:23.16#ibcon#read 6, iclass 25, count 2 2006.285.08:20:23.16#ibcon#end of sib2, iclass 25, count 2 2006.285.08:20:23.16#ibcon#*mode == 0, iclass 25, count 2 2006.285.08:20:23.16#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.08:20:23.16#ibcon#[25=AT04-06\r\n] 2006.285.08:20:23.16#ibcon#*before write, iclass 25, count 2 2006.285.08:20:23.16#ibcon#enter sib2, iclass 25, count 2 2006.285.08:20:23.16#ibcon#flushed, iclass 25, count 2 2006.285.08:20:23.16#ibcon#about to write, iclass 25, count 2 2006.285.08:20:23.16#ibcon#wrote, iclass 25, count 2 2006.285.08:20:23.16#ibcon#about to read 3, iclass 25, count 2 2006.285.08:20:23.19#ibcon#read 3, iclass 25, count 2 2006.285.08:20:23.19#ibcon#about to read 4, iclass 25, count 2 2006.285.08:20:23.19#ibcon#read 4, iclass 25, count 2 2006.285.08:20:23.19#ibcon#about to read 5, iclass 25, count 2 2006.285.08:20:23.19#ibcon#read 5, iclass 25, count 2 2006.285.08:20:23.19#ibcon#about to read 6, iclass 25, count 2 2006.285.08:20:23.19#ibcon#read 6, iclass 25, count 2 2006.285.08:20:23.19#ibcon#end of sib2, iclass 25, count 2 2006.285.08:20:23.19#ibcon#*after write, iclass 25, count 2 2006.285.08:20:23.19#ibcon#*before return 0, iclass 25, count 2 2006.285.08:20:23.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:20:23.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:20:23.19#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.08:20:23.19#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:23.19#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:20:23.31#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:20:23.31#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:20:23.31#ibcon#enter wrdev, iclass 25, count 0 2006.285.08:20:23.31#ibcon#first serial, iclass 25, count 0 2006.285.08:20:23.31#ibcon#enter sib2, iclass 25, count 0 2006.285.08:20:23.31#ibcon#flushed, iclass 25, count 0 2006.285.08:20:23.31#ibcon#about to write, iclass 25, count 0 2006.285.08:20:23.31#ibcon#wrote, iclass 25, count 0 2006.285.08:20:23.31#ibcon#about to read 3, iclass 25, count 0 2006.285.08:20:23.33#ibcon#read 3, iclass 25, count 0 2006.285.08:20:23.33#ibcon#about to read 4, iclass 25, count 0 2006.285.08:20:23.33#ibcon#read 4, iclass 25, count 0 2006.285.08:20:23.33#ibcon#about to read 5, iclass 25, count 0 2006.285.08:20:23.33#ibcon#read 5, iclass 25, count 0 2006.285.08:20:23.33#ibcon#about to read 6, iclass 25, count 0 2006.285.08:20:23.33#ibcon#read 6, iclass 25, count 0 2006.285.08:20:23.33#ibcon#end of sib2, iclass 25, count 0 2006.285.08:20:23.33#ibcon#*mode == 0, iclass 25, count 0 2006.285.08:20:23.33#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.08:20:23.33#ibcon#[25=USB\r\n] 2006.285.08:20:23.33#ibcon#*before write, iclass 25, count 0 2006.285.08:20:23.33#ibcon#enter sib2, iclass 25, count 0 2006.285.08:20:23.33#ibcon#flushed, iclass 25, count 0 2006.285.08:20:23.33#ibcon#about to write, iclass 25, count 0 2006.285.08:20:23.33#ibcon#wrote, iclass 25, count 0 2006.285.08:20:23.33#ibcon#about to read 3, iclass 25, count 0 2006.285.08:20:23.36#ibcon#read 3, iclass 25, count 0 2006.285.08:20:23.36#ibcon#about to read 4, iclass 25, count 0 2006.285.08:20:23.36#ibcon#read 4, iclass 25, count 0 2006.285.08:20:23.36#ibcon#about to read 5, iclass 25, count 0 2006.285.08:20:23.36#ibcon#read 5, iclass 25, count 0 2006.285.08:20:23.36#ibcon#about to read 6, iclass 25, count 0 2006.285.08:20:23.36#ibcon#read 6, iclass 25, count 0 2006.285.08:20:23.36#ibcon#end of sib2, iclass 25, count 0 2006.285.08:20:23.36#ibcon#*after write, iclass 25, count 0 2006.285.08:20:23.36#ibcon#*before return 0, iclass 25, count 0 2006.285.08:20:23.36#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:20:23.36#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:20:23.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.08:20:23.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.08:20:23.36$vck44/valo=5,734.99 2006.285.08:20:23.36#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.08:20:23.36#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.08:20:23.36#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:23.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:20:23.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:20:23.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:20:23.36#ibcon#enter wrdev, iclass 27, count 0 2006.285.08:20:23.36#ibcon#first serial, iclass 27, count 0 2006.285.08:20:23.36#ibcon#enter sib2, iclass 27, count 0 2006.285.08:20:23.36#ibcon#flushed, iclass 27, count 0 2006.285.08:20:23.36#ibcon#about to write, iclass 27, count 0 2006.285.08:20:23.36#ibcon#wrote, iclass 27, count 0 2006.285.08:20:23.36#ibcon#about to read 3, iclass 27, count 0 2006.285.08:20:23.38#ibcon#read 3, iclass 27, count 0 2006.285.08:20:23.38#ibcon#about to read 4, iclass 27, count 0 2006.285.08:20:23.38#ibcon#read 4, iclass 27, count 0 2006.285.08:20:23.38#ibcon#about to read 5, iclass 27, count 0 2006.285.08:20:23.38#ibcon#read 5, iclass 27, count 0 2006.285.08:20:23.38#ibcon#about to read 6, iclass 27, count 0 2006.285.08:20:23.38#ibcon#read 6, iclass 27, count 0 2006.285.08:20:23.38#ibcon#end of sib2, iclass 27, count 0 2006.285.08:20:23.38#ibcon#*mode == 0, iclass 27, count 0 2006.285.08:20:23.38#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.08:20:23.38#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:20:23.38#ibcon#*before write, iclass 27, count 0 2006.285.08:20:23.38#ibcon#enter sib2, iclass 27, count 0 2006.285.08:20:23.38#ibcon#flushed, iclass 27, count 0 2006.285.08:20:23.38#ibcon#about to write, iclass 27, count 0 2006.285.08:20:23.38#ibcon#wrote, iclass 27, count 0 2006.285.08:20:23.38#ibcon#about to read 3, iclass 27, count 0 2006.285.08:20:23.42#ibcon#read 3, iclass 27, count 0 2006.285.08:20:23.42#ibcon#about to read 4, iclass 27, count 0 2006.285.08:20:23.42#ibcon#read 4, iclass 27, count 0 2006.285.08:20:23.42#ibcon#about to read 5, iclass 27, count 0 2006.285.08:20:23.42#ibcon#read 5, iclass 27, count 0 2006.285.08:20:23.42#ibcon#about to read 6, iclass 27, count 0 2006.285.08:20:23.42#ibcon#read 6, iclass 27, count 0 2006.285.08:20:23.42#ibcon#end of sib2, iclass 27, count 0 2006.285.08:20:23.42#ibcon#*after write, iclass 27, count 0 2006.285.08:20:23.42#ibcon#*before return 0, iclass 27, count 0 2006.285.08:20:23.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:20:23.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:20:23.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.08:20:23.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.08:20:23.42$vck44/va=5,3 2006.285.08:20:23.42#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.08:20:23.42#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.08:20:23.42#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:23.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:20:23.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:20:23.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:20:23.48#ibcon#enter wrdev, iclass 29, count 2 2006.285.08:20:23.48#ibcon#first serial, iclass 29, count 2 2006.285.08:20:23.48#ibcon#enter sib2, iclass 29, count 2 2006.285.08:20:23.48#ibcon#flushed, iclass 29, count 2 2006.285.08:20:23.48#ibcon#about to write, iclass 29, count 2 2006.285.08:20:23.48#ibcon#wrote, iclass 29, count 2 2006.285.08:20:23.48#ibcon#about to read 3, iclass 29, count 2 2006.285.08:20:23.50#ibcon#read 3, iclass 29, count 2 2006.285.08:20:23.50#ibcon#about to read 4, iclass 29, count 2 2006.285.08:20:23.50#ibcon#read 4, iclass 29, count 2 2006.285.08:20:23.50#ibcon#about to read 5, iclass 29, count 2 2006.285.08:20:23.50#ibcon#read 5, iclass 29, count 2 2006.285.08:20:23.50#ibcon#about to read 6, iclass 29, count 2 2006.285.08:20:23.50#ibcon#read 6, iclass 29, count 2 2006.285.08:20:23.50#ibcon#end of sib2, iclass 29, count 2 2006.285.08:20:23.50#ibcon#*mode == 0, iclass 29, count 2 2006.285.08:20:23.50#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.08:20:23.50#ibcon#[25=AT05-03\r\n] 2006.285.08:20:23.50#ibcon#*before write, iclass 29, count 2 2006.285.08:20:23.50#ibcon#enter sib2, iclass 29, count 2 2006.285.08:20:23.50#ibcon#flushed, iclass 29, count 2 2006.285.08:20:23.50#ibcon#about to write, iclass 29, count 2 2006.285.08:20:23.50#ibcon#wrote, iclass 29, count 2 2006.285.08:20:23.50#ibcon#about to read 3, iclass 29, count 2 2006.285.08:20:23.53#ibcon#read 3, iclass 29, count 2 2006.285.08:20:23.53#ibcon#about to read 4, iclass 29, count 2 2006.285.08:20:23.53#ibcon#read 4, iclass 29, count 2 2006.285.08:20:23.53#ibcon#about to read 5, iclass 29, count 2 2006.285.08:20:23.53#ibcon#read 5, iclass 29, count 2 2006.285.08:20:23.53#ibcon#about to read 6, iclass 29, count 2 2006.285.08:20:23.53#ibcon#read 6, iclass 29, count 2 2006.285.08:20:23.53#ibcon#end of sib2, iclass 29, count 2 2006.285.08:20:23.53#ibcon#*after write, iclass 29, count 2 2006.285.08:20:23.53#ibcon#*before return 0, iclass 29, count 2 2006.285.08:20:23.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:20:23.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:20:23.53#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.08:20:23.53#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:23.53#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:20:23.65#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:20:23.65#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:20:23.65#ibcon#enter wrdev, iclass 29, count 0 2006.285.08:20:23.65#ibcon#first serial, iclass 29, count 0 2006.285.08:20:23.65#ibcon#enter sib2, iclass 29, count 0 2006.285.08:20:23.65#ibcon#flushed, iclass 29, count 0 2006.285.08:20:23.65#ibcon#about to write, iclass 29, count 0 2006.285.08:20:23.65#ibcon#wrote, iclass 29, count 0 2006.285.08:20:23.65#ibcon#about to read 3, iclass 29, count 0 2006.285.08:20:23.67#ibcon#read 3, iclass 29, count 0 2006.285.08:20:23.67#ibcon#about to read 4, iclass 29, count 0 2006.285.08:20:23.67#ibcon#read 4, iclass 29, count 0 2006.285.08:20:23.67#ibcon#about to read 5, iclass 29, count 0 2006.285.08:20:23.67#ibcon#read 5, iclass 29, count 0 2006.285.08:20:23.67#ibcon#about to read 6, iclass 29, count 0 2006.285.08:20:23.67#ibcon#read 6, iclass 29, count 0 2006.285.08:20:23.67#ibcon#end of sib2, iclass 29, count 0 2006.285.08:20:23.67#ibcon#*mode == 0, iclass 29, count 0 2006.285.08:20:23.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.08:20:23.67#ibcon#[25=USB\r\n] 2006.285.08:20:23.67#ibcon#*before write, iclass 29, count 0 2006.285.08:20:23.67#ibcon#enter sib2, iclass 29, count 0 2006.285.08:20:23.67#ibcon#flushed, iclass 29, count 0 2006.285.08:20:23.67#ibcon#about to write, iclass 29, count 0 2006.285.08:20:23.67#ibcon#wrote, iclass 29, count 0 2006.285.08:20:23.67#ibcon#about to read 3, iclass 29, count 0 2006.285.08:20:23.70#ibcon#read 3, iclass 29, count 0 2006.285.08:20:23.70#ibcon#about to read 4, iclass 29, count 0 2006.285.08:20:23.70#ibcon#read 4, iclass 29, count 0 2006.285.08:20:23.70#ibcon#about to read 5, iclass 29, count 0 2006.285.08:20:23.70#ibcon#read 5, iclass 29, count 0 2006.285.08:20:23.70#ibcon#about to read 6, iclass 29, count 0 2006.285.08:20:23.70#ibcon#read 6, iclass 29, count 0 2006.285.08:20:23.70#ibcon#end of sib2, iclass 29, count 0 2006.285.08:20:23.70#ibcon#*after write, iclass 29, count 0 2006.285.08:20:23.70#ibcon#*before return 0, iclass 29, count 0 2006.285.08:20:23.70#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:20:23.70#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:20:23.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.08:20:23.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.08:20:23.70$vck44/valo=6,814.99 2006.285.08:20:23.70#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.08:20:23.70#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.08:20:23.70#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:23.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:20:23.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:20:23.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:20:23.70#ibcon#enter wrdev, iclass 31, count 0 2006.285.08:20:23.70#ibcon#first serial, iclass 31, count 0 2006.285.08:20:23.70#ibcon#enter sib2, iclass 31, count 0 2006.285.08:20:23.70#ibcon#flushed, iclass 31, count 0 2006.285.08:20:23.70#ibcon#about to write, iclass 31, count 0 2006.285.08:20:23.70#ibcon#wrote, iclass 31, count 0 2006.285.08:20:23.70#ibcon#about to read 3, iclass 31, count 0 2006.285.08:20:23.72#ibcon#read 3, iclass 31, count 0 2006.285.08:20:23.72#ibcon#about to read 4, iclass 31, count 0 2006.285.08:20:23.72#ibcon#read 4, iclass 31, count 0 2006.285.08:20:23.72#ibcon#about to read 5, iclass 31, count 0 2006.285.08:20:23.72#ibcon#read 5, iclass 31, count 0 2006.285.08:20:23.72#ibcon#about to read 6, iclass 31, count 0 2006.285.08:20:23.72#ibcon#read 6, iclass 31, count 0 2006.285.08:20:23.72#ibcon#end of sib2, iclass 31, count 0 2006.285.08:20:23.72#ibcon#*mode == 0, iclass 31, count 0 2006.285.08:20:23.72#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.08:20:23.72#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:20:23.72#ibcon#*before write, iclass 31, count 0 2006.285.08:20:23.72#ibcon#enter sib2, iclass 31, count 0 2006.285.08:20:23.72#ibcon#flushed, iclass 31, count 0 2006.285.08:20:23.72#ibcon#about to write, iclass 31, count 0 2006.285.08:20:23.72#ibcon#wrote, iclass 31, count 0 2006.285.08:20:23.72#ibcon#about to read 3, iclass 31, count 0 2006.285.08:20:23.76#ibcon#read 3, iclass 31, count 0 2006.285.08:20:23.76#ibcon#about to read 4, iclass 31, count 0 2006.285.08:20:23.76#ibcon#read 4, iclass 31, count 0 2006.285.08:20:23.76#ibcon#about to read 5, iclass 31, count 0 2006.285.08:20:23.76#ibcon#read 5, iclass 31, count 0 2006.285.08:20:23.76#ibcon#about to read 6, iclass 31, count 0 2006.285.08:20:23.76#ibcon#read 6, iclass 31, count 0 2006.285.08:20:23.76#ibcon#end of sib2, iclass 31, count 0 2006.285.08:20:23.76#ibcon#*after write, iclass 31, count 0 2006.285.08:20:23.76#ibcon#*before return 0, iclass 31, count 0 2006.285.08:20:23.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:20:23.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:20:23.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.08:20:23.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.08:20:23.76$vck44/va=6,4 2006.285.08:20:23.76#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.08:20:23.76#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.08:20:23.76#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:23.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:20:23.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:20:23.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:20:23.82#ibcon#enter wrdev, iclass 33, count 2 2006.285.08:20:23.82#ibcon#first serial, iclass 33, count 2 2006.285.08:20:23.82#ibcon#enter sib2, iclass 33, count 2 2006.285.08:20:23.82#ibcon#flushed, iclass 33, count 2 2006.285.08:20:23.82#ibcon#about to write, iclass 33, count 2 2006.285.08:20:23.82#ibcon#wrote, iclass 33, count 2 2006.285.08:20:23.82#ibcon#about to read 3, iclass 33, count 2 2006.285.08:20:23.84#ibcon#read 3, iclass 33, count 2 2006.285.08:20:23.84#ibcon#about to read 4, iclass 33, count 2 2006.285.08:20:23.84#ibcon#read 4, iclass 33, count 2 2006.285.08:20:23.84#ibcon#about to read 5, iclass 33, count 2 2006.285.08:20:23.84#ibcon#read 5, iclass 33, count 2 2006.285.08:20:23.84#ibcon#about to read 6, iclass 33, count 2 2006.285.08:20:23.84#ibcon#read 6, iclass 33, count 2 2006.285.08:20:23.84#ibcon#end of sib2, iclass 33, count 2 2006.285.08:20:23.84#ibcon#*mode == 0, iclass 33, count 2 2006.285.08:20:23.84#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.08:20:23.84#ibcon#[25=AT06-04\r\n] 2006.285.08:20:23.84#ibcon#*before write, iclass 33, count 2 2006.285.08:20:23.84#ibcon#enter sib2, iclass 33, count 2 2006.285.08:20:23.84#ibcon#flushed, iclass 33, count 2 2006.285.08:20:23.84#ibcon#about to write, iclass 33, count 2 2006.285.08:20:23.84#ibcon#wrote, iclass 33, count 2 2006.285.08:20:23.84#ibcon#about to read 3, iclass 33, count 2 2006.285.08:20:23.87#ibcon#read 3, iclass 33, count 2 2006.285.08:20:23.87#ibcon#about to read 4, iclass 33, count 2 2006.285.08:20:23.87#ibcon#read 4, iclass 33, count 2 2006.285.08:20:23.87#ibcon#about to read 5, iclass 33, count 2 2006.285.08:20:23.87#ibcon#read 5, iclass 33, count 2 2006.285.08:20:23.87#ibcon#about to read 6, iclass 33, count 2 2006.285.08:20:23.87#ibcon#read 6, iclass 33, count 2 2006.285.08:20:23.87#ibcon#end of sib2, iclass 33, count 2 2006.285.08:20:23.87#ibcon#*after write, iclass 33, count 2 2006.285.08:20:23.87#ibcon#*before return 0, iclass 33, count 2 2006.285.08:20:23.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:20:23.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:20:23.87#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.08:20:23.87#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:23.87#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:20:23.99#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:20:23.99#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:20:23.99#ibcon#enter wrdev, iclass 33, count 0 2006.285.08:20:23.99#ibcon#first serial, iclass 33, count 0 2006.285.08:20:23.99#ibcon#enter sib2, iclass 33, count 0 2006.285.08:20:23.99#ibcon#flushed, iclass 33, count 0 2006.285.08:20:23.99#ibcon#about to write, iclass 33, count 0 2006.285.08:20:23.99#ibcon#wrote, iclass 33, count 0 2006.285.08:20:23.99#ibcon#about to read 3, iclass 33, count 0 2006.285.08:20:24.01#ibcon#read 3, iclass 33, count 0 2006.285.08:20:24.01#ibcon#about to read 4, iclass 33, count 0 2006.285.08:20:24.01#ibcon#read 4, iclass 33, count 0 2006.285.08:20:24.01#ibcon#about to read 5, iclass 33, count 0 2006.285.08:20:24.01#ibcon#read 5, iclass 33, count 0 2006.285.08:20:24.01#ibcon#about to read 6, iclass 33, count 0 2006.285.08:20:24.01#ibcon#read 6, iclass 33, count 0 2006.285.08:20:24.01#ibcon#end of sib2, iclass 33, count 0 2006.285.08:20:24.01#ibcon#*mode == 0, iclass 33, count 0 2006.285.08:20:24.01#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.08:20:24.01#ibcon#[25=USB\r\n] 2006.285.08:20:24.01#ibcon#*before write, iclass 33, count 0 2006.285.08:20:24.01#ibcon#enter sib2, iclass 33, count 0 2006.285.08:20:24.01#ibcon#flushed, iclass 33, count 0 2006.285.08:20:24.01#ibcon#about to write, iclass 33, count 0 2006.285.08:20:24.01#ibcon#wrote, iclass 33, count 0 2006.285.08:20:24.01#ibcon#about to read 3, iclass 33, count 0 2006.285.08:20:24.04#ibcon#read 3, iclass 33, count 0 2006.285.08:20:24.04#ibcon#about to read 4, iclass 33, count 0 2006.285.08:20:24.04#ibcon#read 4, iclass 33, count 0 2006.285.08:20:24.04#ibcon#about to read 5, iclass 33, count 0 2006.285.08:20:24.04#ibcon#read 5, iclass 33, count 0 2006.285.08:20:24.04#ibcon#about to read 6, iclass 33, count 0 2006.285.08:20:24.04#ibcon#read 6, iclass 33, count 0 2006.285.08:20:24.04#ibcon#end of sib2, iclass 33, count 0 2006.285.08:20:24.04#ibcon#*after write, iclass 33, count 0 2006.285.08:20:24.04#ibcon#*before return 0, iclass 33, count 0 2006.285.08:20:24.04#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:20:24.04#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:20:24.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.08:20:24.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.08:20:24.04$vck44/valo=7,864.99 2006.285.08:20:24.04#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.08:20:24.04#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.08:20:24.04#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:24.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:20:24.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:20:24.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:20:24.04#ibcon#enter wrdev, iclass 35, count 0 2006.285.08:20:24.04#ibcon#first serial, iclass 35, count 0 2006.285.08:20:24.04#ibcon#enter sib2, iclass 35, count 0 2006.285.08:20:24.04#ibcon#flushed, iclass 35, count 0 2006.285.08:20:24.04#ibcon#about to write, iclass 35, count 0 2006.285.08:20:24.04#ibcon#wrote, iclass 35, count 0 2006.285.08:20:24.04#ibcon#about to read 3, iclass 35, count 0 2006.285.08:20:24.06#ibcon#read 3, iclass 35, count 0 2006.285.08:20:24.06#ibcon#about to read 4, iclass 35, count 0 2006.285.08:20:24.06#ibcon#read 4, iclass 35, count 0 2006.285.08:20:24.06#ibcon#about to read 5, iclass 35, count 0 2006.285.08:20:24.06#ibcon#read 5, iclass 35, count 0 2006.285.08:20:24.06#ibcon#about to read 6, iclass 35, count 0 2006.285.08:20:24.06#ibcon#read 6, iclass 35, count 0 2006.285.08:20:24.06#ibcon#end of sib2, iclass 35, count 0 2006.285.08:20:24.06#ibcon#*mode == 0, iclass 35, count 0 2006.285.08:20:24.06#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.08:20:24.06#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:20:24.06#ibcon#*before write, iclass 35, count 0 2006.285.08:20:24.06#ibcon#enter sib2, iclass 35, count 0 2006.285.08:20:24.06#ibcon#flushed, iclass 35, count 0 2006.285.08:20:24.06#ibcon#about to write, iclass 35, count 0 2006.285.08:20:24.06#ibcon#wrote, iclass 35, count 0 2006.285.08:20:24.06#ibcon#about to read 3, iclass 35, count 0 2006.285.08:20:24.10#ibcon#read 3, iclass 35, count 0 2006.285.08:20:24.10#ibcon#about to read 4, iclass 35, count 0 2006.285.08:20:24.10#ibcon#read 4, iclass 35, count 0 2006.285.08:20:24.10#ibcon#about to read 5, iclass 35, count 0 2006.285.08:20:24.10#ibcon#read 5, iclass 35, count 0 2006.285.08:20:24.10#ibcon#about to read 6, iclass 35, count 0 2006.285.08:20:24.10#ibcon#read 6, iclass 35, count 0 2006.285.08:20:24.10#ibcon#end of sib2, iclass 35, count 0 2006.285.08:20:24.10#ibcon#*after write, iclass 35, count 0 2006.285.08:20:24.10#ibcon#*before return 0, iclass 35, count 0 2006.285.08:20:24.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:20:24.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:20:24.10#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.08:20:24.10#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.08:20:24.10$vck44/va=7,4 2006.285.08:20:24.10#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.08:20:24.10#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.08:20:24.10#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:24.10#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:20:24.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:20:24.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:20:24.16#ibcon#enter wrdev, iclass 37, count 2 2006.285.08:20:24.16#ibcon#first serial, iclass 37, count 2 2006.285.08:20:24.16#ibcon#enter sib2, iclass 37, count 2 2006.285.08:20:24.16#ibcon#flushed, iclass 37, count 2 2006.285.08:20:24.16#ibcon#about to write, iclass 37, count 2 2006.285.08:20:24.16#ibcon#wrote, iclass 37, count 2 2006.285.08:20:24.16#ibcon#about to read 3, iclass 37, count 2 2006.285.08:20:24.18#ibcon#read 3, iclass 37, count 2 2006.285.08:20:24.18#ibcon#about to read 4, iclass 37, count 2 2006.285.08:20:24.18#ibcon#read 4, iclass 37, count 2 2006.285.08:20:24.18#ibcon#about to read 5, iclass 37, count 2 2006.285.08:20:24.18#ibcon#read 5, iclass 37, count 2 2006.285.08:20:24.18#ibcon#about to read 6, iclass 37, count 2 2006.285.08:20:24.18#ibcon#read 6, iclass 37, count 2 2006.285.08:20:24.18#ibcon#end of sib2, iclass 37, count 2 2006.285.08:20:24.18#ibcon#*mode == 0, iclass 37, count 2 2006.285.08:20:24.18#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.08:20:24.18#ibcon#[25=AT07-04\r\n] 2006.285.08:20:24.18#ibcon#*before write, iclass 37, count 2 2006.285.08:20:24.18#ibcon#enter sib2, iclass 37, count 2 2006.285.08:20:24.18#ibcon#flushed, iclass 37, count 2 2006.285.08:20:24.18#ibcon#about to write, iclass 37, count 2 2006.285.08:20:24.18#ibcon#wrote, iclass 37, count 2 2006.285.08:20:24.18#ibcon#about to read 3, iclass 37, count 2 2006.285.08:20:24.21#ibcon#read 3, iclass 37, count 2 2006.285.08:20:24.21#ibcon#about to read 4, iclass 37, count 2 2006.285.08:20:24.21#ibcon#read 4, iclass 37, count 2 2006.285.08:20:24.21#ibcon#about to read 5, iclass 37, count 2 2006.285.08:20:24.21#ibcon#read 5, iclass 37, count 2 2006.285.08:20:24.21#ibcon#about to read 6, iclass 37, count 2 2006.285.08:20:24.21#ibcon#read 6, iclass 37, count 2 2006.285.08:20:24.21#ibcon#end of sib2, iclass 37, count 2 2006.285.08:20:24.21#ibcon#*after write, iclass 37, count 2 2006.285.08:20:24.21#ibcon#*before return 0, iclass 37, count 2 2006.285.08:20:24.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:20:24.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:20:24.21#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.08:20:24.21#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:24.21#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:20:24.33#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:20:24.33#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:20:24.33#ibcon#enter wrdev, iclass 37, count 0 2006.285.08:20:24.33#ibcon#first serial, iclass 37, count 0 2006.285.08:20:24.33#ibcon#enter sib2, iclass 37, count 0 2006.285.08:20:24.33#ibcon#flushed, iclass 37, count 0 2006.285.08:20:24.33#ibcon#about to write, iclass 37, count 0 2006.285.08:20:24.33#ibcon#wrote, iclass 37, count 0 2006.285.08:20:24.33#ibcon#about to read 3, iclass 37, count 0 2006.285.08:20:24.35#ibcon#read 3, iclass 37, count 0 2006.285.08:20:24.35#ibcon#about to read 4, iclass 37, count 0 2006.285.08:20:24.35#ibcon#read 4, iclass 37, count 0 2006.285.08:20:24.35#ibcon#about to read 5, iclass 37, count 0 2006.285.08:20:24.35#ibcon#read 5, iclass 37, count 0 2006.285.08:20:24.35#ibcon#about to read 6, iclass 37, count 0 2006.285.08:20:24.35#ibcon#read 6, iclass 37, count 0 2006.285.08:20:24.35#ibcon#end of sib2, iclass 37, count 0 2006.285.08:20:24.35#ibcon#*mode == 0, iclass 37, count 0 2006.285.08:20:24.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.08:20:24.35#ibcon#[25=USB\r\n] 2006.285.08:20:24.35#ibcon#*before write, iclass 37, count 0 2006.285.08:20:24.35#ibcon#enter sib2, iclass 37, count 0 2006.285.08:20:24.35#ibcon#flushed, iclass 37, count 0 2006.285.08:20:24.35#ibcon#about to write, iclass 37, count 0 2006.285.08:20:24.35#ibcon#wrote, iclass 37, count 0 2006.285.08:20:24.35#ibcon#about to read 3, iclass 37, count 0 2006.285.08:20:24.38#ibcon#read 3, iclass 37, count 0 2006.285.08:20:24.38#ibcon#about to read 4, iclass 37, count 0 2006.285.08:20:24.38#ibcon#read 4, iclass 37, count 0 2006.285.08:20:24.38#ibcon#about to read 5, iclass 37, count 0 2006.285.08:20:24.38#ibcon#read 5, iclass 37, count 0 2006.285.08:20:24.38#ibcon#about to read 6, iclass 37, count 0 2006.285.08:20:24.38#ibcon#read 6, iclass 37, count 0 2006.285.08:20:24.38#ibcon#end of sib2, iclass 37, count 0 2006.285.08:20:24.38#ibcon#*after write, iclass 37, count 0 2006.285.08:20:24.38#ibcon#*before return 0, iclass 37, count 0 2006.285.08:20:24.38#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:20:24.38#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:20:24.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.08:20:24.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.08:20:24.38$vck44/valo=8,884.99 2006.285.08:20:24.38#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.08:20:24.38#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.08:20:24.38#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:24.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:20:24.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:20:24.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:20:24.38#ibcon#enter wrdev, iclass 39, count 0 2006.285.08:20:24.38#ibcon#first serial, iclass 39, count 0 2006.285.08:20:24.38#ibcon#enter sib2, iclass 39, count 0 2006.285.08:20:24.38#ibcon#flushed, iclass 39, count 0 2006.285.08:20:24.38#ibcon#about to write, iclass 39, count 0 2006.285.08:20:24.38#ibcon#wrote, iclass 39, count 0 2006.285.08:20:24.38#ibcon#about to read 3, iclass 39, count 0 2006.285.08:20:24.40#ibcon#read 3, iclass 39, count 0 2006.285.08:20:24.40#ibcon#about to read 4, iclass 39, count 0 2006.285.08:20:24.40#ibcon#read 4, iclass 39, count 0 2006.285.08:20:24.40#ibcon#about to read 5, iclass 39, count 0 2006.285.08:20:24.40#ibcon#read 5, iclass 39, count 0 2006.285.08:20:24.40#ibcon#about to read 6, iclass 39, count 0 2006.285.08:20:24.40#ibcon#read 6, iclass 39, count 0 2006.285.08:20:24.40#ibcon#end of sib2, iclass 39, count 0 2006.285.08:20:24.40#ibcon#*mode == 0, iclass 39, count 0 2006.285.08:20:24.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.08:20:24.40#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:20:24.40#ibcon#*before write, iclass 39, count 0 2006.285.08:20:24.40#ibcon#enter sib2, iclass 39, count 0 2006.285.08:20:24.40#ibcon#flushed, iclass 39, count 0 2006.285.08:20:24.40#ibcon#about to write, iclass 39, count 0 2006.285.08:20:24.40#ibcon#wrote, iclass 39, count 0 2006.285.08:20:24.40#ibcon#about to read 3, iclass 39, count 0 2006.285.08:20:24.44#ibcon#read 3, iclass 39, count 0 2006.285.08:20:24.44#ibcon#about to read 4, iclass 39, count 0 2006.285.08:20:24.44#ibcon#read 4, iclass 39, count 0 2006.285.08:20:24.44#ibcon#about to read 5, iclass 39, count 0 2006.285.08:20:24.44#ibcon#read 5, iclass 39, count 0 2006.285.08:20:24.44#ibcon#about to read 6, iclass 39, count 0 2006.285.08:20:24.44#ibcon#read 6, iclass 39, count 0 2006.285.08:20:24.44#ibcon#end of sib2, iclass 39, count 0 2006.285.08:20:24.44#ibcon#*after write, iclass 39, count 0 2006.285.08:20:24.44#ibcon#*before return 0, iclass 39, count 0 2006.285.08:20:24.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:20:24.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:20:24.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.08:20:24.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.08:20:24.44$vck44/va=8,3 2006.285.08:20:24.44#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.08:20:24.44#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.08:20:24.44#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:24.44#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:20:24.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:20:24.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:20:24.50#ibcon#enter wrdev, iclass 3, count 2 2006.285.08:20:24.50#ibcon#first serial, iclass 3, count 2 2006.285.08:20:24.50#ibcon#enter sib2, iclass 3, count 2 2006.285.08:20:24.50#ibcon#flushed, iclass 3, count 2 2006.285.08:20:24.50#ibcon#about to write, iclass 3, count 2 2006.285.08:20:24.50#ibcon#wrote, iclass 3, count 2 2006.285.08:20:24.50#ibcon#about to read 3, iclass 3, count 2 2006.285.08:20:24.52#ibcon#read 3, iclass 3, count 2 2006.285.08:20:24.52#ibcon#about to read 4, iclass 3, count 2 2006.285.08:20:24.52#ibcon#read 4, iclass 3, count 2 2006.285.08:20:24.52#ibcon#about to read 5, iclass 3, count 2 2006.285.08:20:24.52#ibcon#read 5, iclass 3, count 2 2006.285.08:20:24.52#ibcon#about to read 6, iclass 3, count 2 2006.285.08:20:24.52#ibcon#read 6, iclass 3, count 2 2006.285.08:20:24.52#ibcon#end of sib2, iclass 3, count 2 2006.285.08:20:24.52#ibcon#*mode == 0, iclass 3, count 2 2006.285.08:20:24.52#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.08:20:24.52#ibcon#[25=AT08-03\r\n] 2006.285.08:20:24.52#ibcon#*before write, iclass 3, count 2 2006.285.08:20:24.52#ibcon#enter sib2, iclass 3, count 2 2006.285.08:20:24.52#ibcon#flushed, iclass 3, count 2 2006.285.08:20:24.52#ibcon#about to write, iclass 3, count 2 2006.285.08:20:24.52#ibcon#wrote, iclass 3, count 2 2006.285.08:20:24.52#ibcon#about to read 3, iclass 3, count 2 2006.285.08:20:24.55#ibcon#read 3, iclass 3, count 2 2006.285.08:20:24.55#ibcon#about to read 4, iclass 3, count 2 2006.285.08:20:24.55#ibcon#read 4, iclass 3, count 2 2006.285.08:20:24.55#ibcon#about to read 5, iclass 3, count 2 2006.285.08:20:24.55#ibcon#read 5, iclass 3, count 2 2006.285.08:20:24.55#ibcon#about to read 6, iclass 3, count 2 2006.285.08:20:24.55#ibcon#read 6, iclass 3, count 2 2006.285.08:20:24.55#ibcon#end of sib2, iclass 3, count 2 2006.285.08:20:24.55#ibcon#*after write, iclass 3, count 2 2006.285.08:20:24.55#ibcon#*before return 0, iclass 3, count 2 2006.285.08:20:24.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:20:24.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:20:24.55#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.08:20:24.55#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:24.55#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:20:24.67#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:20:24.67#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:20:24.67#ibcon#enter wrdev, iclass 3, count 0 2006.285.08:20:24.67#ibcon#first serial, iclass 3, count 0 2006.285.08:20:24.67#ibcon#enter sib2, iclass 3, count 0 2006.285.08:20:24.67#ibcon#flushed, iclass 3, count 0 2006.285.08:20:24.67#ibcon#about to write, iclass 3, count 0 2006.285.08:20:24.67#ibcon#wrote, iclass 3, count 0 2006.285.08:20:24.67#ibcon#about to read 3, iclass 3, count 0 2006.285.08:20:24.69#ibcon#read 3, iclass 3, count 0 2006.285.08:20:24.69#ibcon#about to read 4, iclass 3, count 0 2006.285.08:20:24.69#ibcon#read 4, iclass 3, count 0 2006.285.08:20:24.69#ibcon#about to read 5, iclass 3, count 0 2006.285.08:20:24.69#ibcon#read 5, iclass 3, count 0 2006.285.08:20:24.69#ibcon#about to read 6, iclass 3, count 0 2006.285.08:20:24.69#ibcon#read 6, iclass 3, count 0 2006.285.08:20:24.69#ibcon#end of sib2, iclass 3, count 0 2006.285.08:20:24.69#ibcon#*mode == 0, iclass 3, count 0 2006.285.08:20:24.69#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.08:20:24.69#ibcon#[25=USB\r\n] 2006.285.08:20:24.69#ibcon#*before write, iclass 3, count 0 2006.285.08:20:24.69#ibcon#enter sib2, iclass 3, count 0 2006.285.08:20:24.69#ibcon#flushed, iclass 3, count 0 2006.285.08:20:24.69#ibcon#about to write, iclass 3, count 0 2006.285.08:20:24.69#ibcon#wrote, iclass 3, count 0 2006.285.08:20:24.69#ibcon#about to read 3, iclass 3, count 0 2006.285.08:20:24.70#abcon#<5=/04 1.6 3.3 22.46 811014.7\r\n> 2006.285.08:20:24.72#abcon#{5=INTERFACE CLEAR} 2006.285.08:20:24.72#ibcon#read 3, iclass 3, count 0 2006.285.08:20:24.72#ibcon#about to read 4, iclass 3, count 0 2006.285.08:20:24.72#ibcon#read 4, iclass 3, count 0 2006.285.08:20:24.72#ibcon#about to read 5, iclass 3, count 0 2006.285.08:20:24.72#ibcon#read 5, iclass 3, count 0 2006.285.08:20:24.72#ibcon#about to read 6, iclass 3, count 0 2006.285.08:20:24.72#ibcon#read 6, iclass 3, count 0 2006.285.08:20:24.72#ibcon#end of sib2, iclass 3, count 0 2006.285.08:20:24.72#ibcon#*after write, iclass 3, count 0 2006.285.08:20:24.72#ibcon#*before return 0, iclass 3, count 0 2006.285.08:20:24.72#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:20:24.72#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:20:24.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.08:20:24.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.08:20:24.72$vck44/vblo=1,629.99 2006.285.08:20:24.72#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.08:20:24.72#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.08:20:24.72#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:24.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:20:24.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:20:24.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:20:24.72#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:20:24.72#ibcon#first serial, iclass 10, count 0 2006.285.08:20:24.72#ibcon#enter sib2, iclass 10, count 0 2006.285.08:20:24.72#ibcon#flushed, iclass 10, count 0 2006.285.08:20:24.72#ibcon#about to write, iclass 10, count 0 2006.285.08:20:24.72#ibcon#wrote, iclass 10, count 0 2006.285.08:20:24.72#ibcon#about to read 3, iclass 10, count 0 2006.285.08:20:24.74#ibcon#read 3, iclass 10, count 0 2006.285.08:20:24.74#ibcon#about to read 4, iclass 10, count 0 2006.285.08:20:24.74#ibcon#read 4, iclass 10, count 0 2006.285.08:20:24.74#ibcon#about to read 5, iclass 10, count 0 2006.285.08:20:24.74#ibcon#read 5, iclass 10, count 0 2006.285.08:20:24.74#ibcon#about to read 6, iclass 10, count 0 2006.285.08:20:24.74#ibcon#read 6, iclass 10, count 0 2006.285.08:20:24.74#ibcon#end of sib2, iclass 10, count 0 2006.285.08:20:24.74#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:20:24.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:20:24.74#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:20:24.74#ibcon#*before write, iclass 10, count 0 2006.285.08:20:24.74#ibcon#enter sib2, iclass 10, count 0 2006.285.08:20:24.74#ibcon#flushed, iclass 10, count 0 2006.285.08:20:24.74#ibcon#about to write, iclass 10, count 0 2006.285.08:20:24.74#ibcon#wrote, iclass 10, count 0 2006.285.08:20:24.74#ibcon#about to read 3, iclass 10, count 0 2006.285.08:20:24.78#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:20:24.78#ibcon#read 3, iclass 10, count 0 2006.285.08:20:24.78#ibcon#about to read 4, iclass 10, count 0 2006.285.08:20:24.78#ibcon#read 4, iclass 10, count 0 2006.285.08:20:24.78#ibcon#about to read 5, iclass 10, count 0 2006.285.08:20:24.78#ibcon#read 5, iclass 10, count 0 2006.285.08:20:24.78#ibcon#about to read 6, iclass 10, count 0 2006.285.08:20:24.78#ibcon#read 6, iclass 10, count 0 2006.285.08:20:24.78#ibcon#end of sib2, iclass 10, count 0 2006.285.08:20:24.78#ibcon#*after write, iclass 10, count 0 2006.285.08:20:24.78#ibcon#*before return 0, iclass 10, count 0 2006.285.08:20:24.78#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:20:24.78#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:20:24.78#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:20:24.78#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:20:24.78$vck44/vb=1,4 2006.285.08:20:24.78#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.08:20:24.78#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.08:20:24.78#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:24.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:20:24.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:20:24.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:20:24.78#ibcon#enter wrdev, iclass 13, count 2 2006.285.08:20:24.78#ibcon#first serial, iclass 13, count 2 2006.285.08:20:24.78#ibcon#enter sib2, iclass 13, count 2 2006.285.08:20:24.78#ibcon#flushed, iclass 13, count 2 2006.285.08:20:24.78#ibcon#about to write, iclass 13, count 2 2006.285.08:20:24.78#ibcon#wrote, iclass 13, count 2 2006.285.08:20:24.78#ibcon#about to read 3, iclass 13, count 2 2006.285.08:20:24.80#ibcon#read 3, iclass 13, count 2 2006.285.08:20:24.80#ibcon#about to read 4, iclass 13, count 2 2006.285.08:20:24.80#ibcon#read 4, iclass 13, count 2 2006.285.08:20:24.80#ibcon#about to read 5, iclass 13, count 2 2006.285.08:20:24.80#ibcon#read 5, iclass 13, count 2 2006.285.08:20:24.80#ibcon#about to read 6, iclass 13, count 2 2006.285.08:20:24.80#ibcon#read 6, iclass 13, count 2 2006.285.08:20:24.80#ibcon#end of sib2, iclass 13, count 2 2006.285.08:20:24.80#ibcon#*mode == 0, iclass 13, count 2 2006.285.08:20:24.80#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.08:20:24.80#ibcon#[27=AT01-04\r\n] 2006.285.08:20:24.80#ibcon#*before write, iclass 13, count 2 2006.285.08:20:24.80#ibcon#enter sib2, iclass 13, count 2 2006.285.08:20:24.80#ibcon#flushed, iclass 13, count 2 2006.285.08:20:24.80#ibcon#about to write, iclass 13, count 2 2006.285.08:20:24.80#ibcon#wrote, iclass 13, count 2 2006.285.08:20:24.80#ibcon#about to read 3, iclass 13, count 2 2006.285.08:20:24.83#ibcon#read 3, iclass 13, count 2 2006.285.08:20:24.83#ibcon#about to read 4, iclass 13, count 2 2006.285.08:20:24.83#ibcon#read 4, iclass 13, count 2 2006.285.08:20:24.83#ibcon#about to read 5, iclass 13, count 2 2006.285.08:20:24.83#ibcon#read 5, iclass 13, count 2 2006.285.08:20:24.83#ibcon#about to read 6, iclass 13, count 2 2006.285.08:20:24.83#ibcon#read 6, iclass 13, count 2 2006.285.08:20:24.83#ibcon#end of sib2, iclass 13, count 2 2006.285.08:20:24.83#ibcon#*after write, iclass 13, count 2 2006.285.08:20:24.83#ibcon#*before return 0, iclass 13, count 2 2006.285.08:20:24.83#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:20:24.83#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:20:24.83#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.08:20:24.83#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:24.83#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:20:24.95#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:20:24.95#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:20:24.95#ibcon#enter wrdev, iclass 13, count 0 2006.285.08:20:24.95#ibcon#first serial, iclass 13, count 0 2006.285.08:20:24.95#ibcon#enter sib2, iclass 13, count 0 2006.285.08:20:24.95#ibcon#flushed, iclass 13, count 0 2006.285.08:20:24.95#ibcon#about to write, iclass 13, count 0 2006.285.08:20:24.95#ibcon#wrote, iclass 13, count 0 2006.285.08:20:24.95#ibcon#about to read 3, iclass 13, count 0 2006.285.08:20:24.97#ibcon#read 3, iclass 13, count 0 2006.285.08:20:24.97#ibcon#about to read 4, iclass 13, count 0 2006.285.08:20:24.97#ibcon#read 4, iclass 13, count 0 2006.285.08:20:24.97#ibcon#about to read 5, iclass 13, count 0 2006.285.08:20:24.97#ibcon#read 5, iclass 13, count 0 2006.285.08:20:24.97#ibcon#about to read 6, iclass 13, count 0 2006.285.08:20:24.97#ibcon#read 6, iclass 13, count 0 2006.285.08:20:24.97#ibcon#end of sib2, iclass 13, count 0 2006.285.08:20:24.97#ibcon#*mode == 0, iclass 13, count 0 2006.285.08:20:24.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.08:20:24.97#ibcon#[27=USB\r\n] 2006.285.08:20:24.97#ibcon#*before write, iclass 13, count 0 2006.285.08:20:24.97#ibcon#enter sib2, iclass 13, count 0 2006.285.08:20:24.97#ibcon#flushed, iclass 13, count 0 2006.285.08:20:24.97#ibcon#about to write, iclass 13, count 0 2006.285.08:20:24.97#ibcon#wrote, iclass 13, count 0 2006.285.08:20:24.97#ibcon#about to read 3, iclass 13, count 0 2006.285.08:20:25.00#ibcon#read 3, iclass 13, count 0 2006.285.08:20:25.00#ibcon#about to read 4, iclass 13, count 0 2006.285.08:20:25.00#ibcon#read 4, iclass 13, count 0 2006.285.08:20:25.00#ibcon#about to read 5, iclass 13, count 0 2006.285.08:20:25.00#ibcon#read 5, iclass 13, count 0 2006.285.08:20:25.00#ibcon#about to read 6, iclass 13, count 0 2006.285.08:20:25.00#ibcon#read 6, iclass 13, count 0 2006.285.08:20:25.00#ibcon#end of sib2, iclass 13, count 0 2006.285.08:20:25.00#ibcon#*after write, iclass 13, count 0 2006.285.08:20:25.00#ibcon#*before return 0, iclass 13, count 0 2006.285.08:20:25.00#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:20:25.00#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:20:25.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.08:20:25.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.08:20:25.00$vck44/vblo=2,634.99 2006.285.08:20:25.00#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.08:20:25.00#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.08:20:25.00#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:25.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:20:25.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:20:25.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:20:25.00#ibcon#enter wrdev, iclass 15, count 0 2006.285.08:20:25.00#ibcon#first serial, iclass 15, count 0 2006.285.08:20:25.00#ibcon#enter sib2, iclass 15, count 0 2006.285.08:20:25.00#ibcon#flushed, iclass 15, count 0 2006.285.08:20:25.00#ibcon#about to write, iclass 15, count 0 2006.285.08:20:25.00#ibcon#wrote, iclass 15, count 0 2006.285.08:20:25.00#ibcon#about to read 3, iclass 15, count 0 2006.285.08:20:25.02#ibcon#read 3, iclass 15, count 0 2006.285.08:20:25.02#ibcon#about to read 4, iclass 15, count 0 2006.285.08:20:25.02#ibcon#read 4, iclass 15, count 0 2006.285.08:20:25.02#ibcon#about to read 5, iclass 15, count 0 2006.285.08:20:25.02#ibcon#read 5, iclass 15, count 0 2006.285.08:20:25.02#ibcon#about to read 6, iclass 15, count 0 2006.285.08:20:25.02#ibcon#read 6, iclass 15, count 0 2006.285.08:20:25.02#ibcon#end of sib2, iclass 15, count 0 2006.285.08:20:25.02#ibcon#*mode == 0, iclass 15, count 0 2006.285.08:20:25.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.08:20:25.02#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:20:25.02#ibcon#*before write, iclass 15, count 0 2006.285.08:20:25.02#ibcon#enter sib2, iclass 15, count 0 2006.285.08:20:25.02#ibcon#flushed, iclass 15, count 0 2006.285.08:20:25.02#ibcon#about to write, iclass 15, count 0 2006.285.08:20:25.02#ibcon#wrote, iclass 15, count 0 2006.285.08:20:25.02#ibcon#about to read 3, iclass 15, count 0 2006.285.08:20:25.06#ibcon#read 3, iclass 15, count 0 2006.285.08:20:25.06#ibcon#about to read 4, iclass 15, count 0 2006.285.08:20:25.06#ibcon#read 4, iclass 15, count 0 2006.285.08:20:25.06#ibcon#about to read 5, iclass 15, count 0 2006.285.08:20:25.06#ibcon#read 5, iclass 15, count 0 2006.285.08:20:25.06#ibcon#about to read 6, iclass 15, count 0 2006.285.08:20:25.06#ibcon#read 6, iclass 15, count 0 2006.285.08:20:25.06#ibcon#end of sib2, iclass 15, count 0 2006.285.08:20:25.06#ibcon#*after write, iclass 15, count 0 2006.285.08:20:25.06#ibcon#*before return 0, iclass 15, count 0 2006.285.08:20:25.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:20:25.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:20:25.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.08:20:25.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.08:20:25.06$vck44/vb=2,5 2006.285.08:20:25.06#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.08:20:25.06#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.08:20:25.06#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:25.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:20:25.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:20:25.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:20:25.12#ibcon#enter wrdev, iclass 17, count 2 2006.285.08:20:25.12#ibcon#first serial, iclass 17, count 2 2006.285.08:20:25.12#ibcon#enter sib2, iclass 17, count 2 2006.285.08:20:25.12#ibcon#flushed, iclass 17, count 2 2006.285.08:20:25.12#ibcon#about to write, iclass 17, count 2 2006.285.08:20:25.12#ibcon#wrote, iclass 17, count 2 2006.285.08:20:25.12#ibcon#about to read 3, iclass 17, count 2 2006.285.08:20:25.14#ibcon#read 3, iclass 17, count 2 2006.285.08:20:25.14#ibcon#about to read 4, iclass 17, count 2 2006.285.08:20:25.14#ibcon#read 4, iclass 17, count 2 2006.285.08:20:25.14#ibcon#about to read 5, iclass 17, count 2 2006.285.08:20:25.14#ibcon#read 5, iclass 17, count 2 2006.285.08:20:25.14#ibcon#about to read 6, iclass 17, count 2 2006.285.08:20:25.14#ibcon#read 6, iclass 17, count 2 2006.285.08:20:25.14#ibcon#end of sib2, iclass 17, count 2 2006.285.08:20:25.14#ibcon#*mode == 0, iclass 17, count 2 2006.285.08:20:25.14#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.08:20:25.14#ibcon#[27=AT02-05\r\n] 2006.285.08:20:25.14#ibcon#*before write, iclass 17, count 2 2006.285.08:20:25.14#ibcon#enter sib2, iclass 17, count 2 2006.285.08:20:25.14#ibcon#flushed, iclass 17, count 2 2006.285.08:20:25.14#ibcon#about to write, iclass 17, count 2 2006.285.08:20:25.14#ibcon#wrote, iclass 17, count 2 2006.285.08:20:25.14#ibcon#about to read 3, iclass 17, count 2 2006.285.08:20:25.17#ibcon#read 3, iclass 17, count 2 2006.285.08:20:25.17#ibcon#about to read 4, iclass 17, count 2 2006.285.08:20:25.17#ibcon#read 4, iclass 17, count 2 2006.285.08:20:25.17#ibcon#about to read 5, iclass 17, count 2 2006.285.08:20:25.17#ibcon#read 5, iclass 17, count 2 2006.285.08:20:25.17#ibcon#about to read 6, iclass 17, count 2 2006.285.08:20:25.17#ibcon#read 6, iclass 17, count 2 2006.285.08:20:25.17#ibcon#end of sib2, iclass 17, count 2 2006.285.08:20:25.17#ibcon#*after write, iclass 17, count 2 2006.285.08:20:25.17#ibcon#*before return 0, iclass 17, count 2 2006.285.08:20:25.17#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:20:25.17#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:20:25.17#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.08:20:25.17#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:25.17#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:20:25.29#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:20:25.29#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:20:25.29#ibcon#enter wrdev, iclass 17, count 0 2006.285.08:20:25.29#ibcon#first serial, iclass 17, count 0 2006.285.08:20:25.29#ibcon#enter sib2, iclass 17, count 0 2006.285.08:20:25.29#ibcon#flushed, iclass 17, count 0 2006.285.08:20:25.29#ibcon#about to write, iclass 17, count 0 2006.285.08:20:25.29#ibcon#wrote, iclass 17, count 0 2006.285.08:20:25.29#ibcon#about to read 3, iclass 17, count 0 2006.285.08:20:25.31#ibcon#read 3, iclass 17, count 0 2006.285.08:20:25.31#ibcon#about to read 4, iclass 17, count 0 2006.285.08:20:25.31#ibcon#read 4, iclass 17, count 0 2006.285.08:20:25.31#ibcon#about to read 5, iclass 17, count 0 2006.285.08:20:25.31#ibcon#read 5, iclass 17, count 0 2006.285.08:20:25.31#ibcon#about to read 6, iclass 17, count 0 2006.285.08:20:25.31#ibcon#read 6, iclass 17, count 0 2006.285.08:20:25.31#ibcon#end of sib2, iclass 17, count 0 2006.285.08:20:25.31#ibcon#*mode == 0, iclass 17, count 0 2006.285.08:20:25.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.08:20:25.31#ibcon#[27=USB\r\n] 2006.285.08:20:25.31#ibcon#*before write, iclass 17, count 0 2006.285.08:20:25.31#ibcon#enter sib2, iclass 17, count 0 2006.285.08:20:25.31#ibcon#flushed, iclass 17, count 0 2006.285.08:20:25.31#ibcon#about to write, iclass 17, count 0 2006.285.08:20:25.31#ibcon#wrote, iclass 17, count 0 2006.285.08:20:25.31#ibcon#about to read 3, iclass 17, count 0 2006.285.08:20:25.34#ibcon#read 3, iclass 17, count 0 2006.285.08:20:25.34#ibcon#about to read 4, iclass 17, count 0 2006.285.08:20:25.34#ibcon#read 4, iclass 17, count 0 2006.285.08:20:25.34#ibcon#about to read 5, iclass 17, count 0 2006.285.08:20:25.34#ibcon#read 5, iclass 17, count 0 2006.285.08:20:25.34#ibcon#about to read 6, iclass 17, count 0 2006.285.08:20:25.34#ibcon#read 6, iclass 17, count 0 2006.285.08:20:25.34#ibcon#end of sib2, iclass 17, count 0 2006.285.08:20:25.34#ibcon#*after write, iclass 17, count 0 2006.285.08:20:25.34#ibcon#*before return 0, iclass 17, count 0 2006.285.08:20:25.34#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:20:25.34#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:20:25.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.08:20:25.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.08:20:25.34$vck44/vblo=3,649.99 2006.285.08:20:25.34#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.08:20:25.34#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.08:20:25.34#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:25.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:20:25.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:20:25.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:20:25.34#ibcon#enter wrdev, iclass 19, count 0 2006.285.08:20:25.34#ibcon#first serial, iclass 19, count 0 2006.285.08:20:25.34#ibcon#enter sib2, iclass 19, count 0 2006.285.08:20:25.34#ibcon#flushed, iclass 19, count 0 2006.285.08:20:25.34#ibcon#about to write, iclass 19, count 0 2006.285.08:20:25.34#ibcon#wrote, iclass 19, count 0 2006.285.08:20:25.34#ibcon#about to read 3, iclass 19, count 0 2006.285.08:20:25.36#ibcon#read 3, iclass 19, count 0 2006.285.08:20:25.36#ibcon#about to read 4, iclass 19, count 0 2006.285.08:20:25.36#ibcon#read 4, iclass 19, count 0 2006.285.08:20:25.36#ibcon#about to read 5, iclass 19, count 0 2006.285.08:20:25.36#ibcon#read 5, iclass 19, count 0 2006.285.08:20:25.36#ibcon#about to read 6, iclass 19, count 0 2006.285.08:20:25.36#ibcon#read 6, iclass 19, count 0 2006.285.08:20:25.36#ibcon#end of sib2, iclass 19, count 0 2006.285.08:20:25.36#ibcon#*mode == 0, iclass 19, count 0 2006.285.08:20:25.36#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.08:20:25.36#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:20:25.36#ibcon#*before write, iclass 19, count 0 2006.285.08:20:25.36#ibcon#enter sib2, iclass 19, count 0 2006.285.08:20:25.36#ibcon#flushed, iclass 19, count 0 2006.285.08:20:25.36#ibcon#about to write, iclass 19, count 0 2006.285.08:20:25.36#ibcon#wrote, iclass 19, count 0 2006.285.08:20:25.36#ibcon#about to read 3, iclass 19, count 0 2006.285.08:20:25.40#ibcon#read 3, iclass 19, count 0 2006.285.08:20:25.40#ibcon#about to read 4, iclass 19, count 0 2006.285.08:20:25.40#ibcon#read 4, iclass 19, count 0 2006.285.08:20:25.40#ibcon#about to read 5, iclass 19, count 0 2006.285.08:20:25.40#ibcon#read 5, iclass 19, count 0 2006.285.08:20:25.40#ibcon#about to read 6, iclass 19, count 0 2006.285.08:20:25.40#ibcon#read 6, iclass 19, count 0 2006.285.08:20:25.40#ibcon#end of sib2, iclass 19, count 0 2006.285.08:20:25.40#ibcon#*after write, iclass 19, count 0 2006.285.08:20:25.40#ibcon#*before return 0, iclass 19, count 0 2006.285.08:20:25.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:20:25.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:20:25.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.08:20:25.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.08:20:25.40$vck44/vb=3,4 2006.285.08:20:25.40#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.08:20:25.40#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.08:20:25.40#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:25.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:20:25.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:20:25.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:20:25.46#ibcon#enter wrdev, iclass 21, count 2 2006.285.08:20:25.46#ibcon#first serial, iclass 21, count 2 2006.285.08:20:25.46#ibcon#enter sib2, iclass 21, count 2 2006.285.08:20:25.46#ibcon#flushed, iclass 21, count 2 2006.285.08:20:25.46#ibcon#about to write, iclass 21, count 2 2006.285.08:20:25.46#ibcon#wrote, iclass 21, count 2 2006.285.08:20:25.46#ibcon#about to read 3, iclass 21, count 2 2006.285.08:20:25.48#ibcon#read 3, iclass 21, count 2 2006.285.08:20:25.48#ibcon#about to read 4, iclass 21, count 2 2006.285.08:20:25.48#ibcon#read 4, iclass 21, count 2 2006.285.08:20:25.48#ibcon#about to read 5, iclass 21, count 2 2006.285.08:20:25.48#ibcon#read 5, iclass 21, count 2 2006.285.08:20:25.48#ibcon#about to read 6, iclass 21, count 2 2006.285.08:20:25.48#ibcon#read 6, iclass 21, count 2 2006.285.08:20:25.48#ibcon#end of sib2, iclass 21, count 2 2006.285.08:20:25.48#ibcon#*mode == 0, iclass 21, count 2 2006.285.08:20:25.48#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.08:20:25.48#ibcon#[27=AT03-04\r\n] 2006.285.08:20:25.48#ibcon#*before write, iclass 21, count 2 2006.285.08:20:25.48#ibcon#enter sib2, iclass 21, count 2 2006.285.08:20:25.48#ibcon#flushed, iclass 21, count 2 2006.285.08:20:25.48#ibcon#about to write, iclass 21, count 2 2006.285.08:20:25.48#ibcon#wrote, iclass 21, count 2 2006.285.08:20:25.48#ibcon#about to read 3, iclass 21, count 2 2006.285.08:20:25.51#ibcon#read 3, iclass 21, count 2 2006.285.08:20:25.51#ibcon#about to read 4, iclass 21, count 2 2006.285.08:20:25.51#ibcon#read 4, iclass 21, count 2 2006.285.08:20:25.51#ibcon#about to read 5, iclass 21, count 2 2006.285.08:20:25.51#ibcon#read 5, iclass 21, count 2 2006.285.08:20:25.51#ibcon#about to read 6, iclass 21, count 2 2006.285.08:20:25.51#ibcon#read 6, iclass 21, count 2 2006.285.08:20:25.51#ibcon#end of sib2, iclass 21, count 2 2006.285.08:20:25.51#ibcon#*after write, iclass 21, count 2 2006.285.08:20:25.51#ibcon#*before return 0, iclass 21, count 2 2006.285.08:20:25.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:20:25.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:20:25.51#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.08:20:25.51#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:25.51#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:20:25.63#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:20:25.63#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:20:25.63#ibcon#enter wrdev, iclass 21, count 0 2006.285.08:20:25.63#ibcon#first serial, iclass 21, count 0 2006.285.08:20:25.63#ibcon#enter sib2, iclass 21, count 0 2006.285.08:20:25.63#ibcon#flushed, iclass 21, count 0 2006.285.08:20:25.63#ibcon#about to write, iclass 21, count 0 2006.285.08:20:25.63#ibcon#wrote, iclass 21, count 0 2006.285.08:20:25.63#ibcon#about to read 3, iclass 21, count 0 2006.285.08:20:25.65#ibcon#read 3, iclass 21, count 0 2006.285.08:20:25.65#ibcon#about to read 4, iclass 21, count 0 2006.285.08:20:25.65#ibcon#read 4, iclass 21, count 0 2006.285.08:20:25.65#ibcon#about to read 5, iclass 21, count 0 2006.285.08:20:25.65#ibcon#read 5, iclass 21, count 0 2006.285.08:20:25.65#ibcon#about to read 6, iclass 21, count 0 2006.285.08:20:25.65#ibcon#read 6, iclass 21, count 0 2006.285.08:20:25.65#ibcon#end of sib2, iclass 21, count 0 2006.285.08:20:25.65#ibcon#*mode == 0, iclass 21, count 0 2006.285.08:20:25.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.08:20:25.65#ibcon#[27=USB\r\n] 2006.285.08:20:25.65#ibcon#*before write, iclass 21, count 0 2006.285.08:20:25.65#ibcon#enter sib2, iclass 21, count 0 2006.285.08:20:25.65#ibcon#flushed, iclass 21, count 0 2006.285.08:20:25.65#ibcon#about to write, iclass 21, count 0 2006.285.08:20:25.65#ibcon#wrote, iclass 21, count 0 2006.285.08:20:25.65#ibcon#about to read 3, iclass 21, count 0 2006.285.08:20:25.68#ibcon#read 3, iclass 21, count 0 2006.285.08:20:25.68#ibcon#about to read 4, iclass 21, count 0 2006.285.08:20:25.68#ibcon#read 4, iclass 21, count 0 2006.285.08:20:25.68#ibcon#about to read 5, iclass 21, count 0 2006.285.08:20:25.68#ibcon#read 5, iclass 21, count 0 2006.285.08:20:25.68#ibcon#about to read 6, iclass 21, count 0 2006.285.08:20:25.68#ibcon#read 6, iclass 21, count 0 2006.285.08:20:25.68#ibcon#end of sib2, iclass 21, count 0 2006.285.08:20:25.68#ibcon#*after write, iclass 21, count 0 2006.285.08:20:25.68#ibcon#*before return 0, iclass 21, count 0 2006.285.08:20:25.68#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:20:25.68#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:20:25.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.08:20:25.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.08:20:25.68$vck44/vblo=4,679.99 2006.285.08:20:25.68#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.08:20:25.68#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.08:20:25.68#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:25.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:20:25.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:20:25.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:20:25.68#ibcon#enter wrdev, iclass 23, count 0 2006.285.08:20:25.68#ibcon#first serial, iclass 23, count 0 2006.285.08:20:25.68#ibcon#enter sib2, iclass 23, count 0 2006.285.08:20:25.68#ibcon#flushed, iclass 23, count 0 2006.285.08:20:25.68#ibcon#about to write, iclass 23, count 0 2006.285.08:20:25.68#ibcon#wrote, iclass 23, count 0 2006.285.08:20:25.68#ibcon#about to read 3, iclass 23, count 0 2006.285.08:20:25.70#ibcon#read 3, iclass 23, count 0 2006.285.08:20:25.70#ibcon#about to read 4, iclass 23, count 0 2006.285.08:20:25.70#ibcon#read 4, iclass 23, count 0 2006.285.08:20:25.70#ibcon#about to read 5, iclass 23, count 0 2006.285.08:20:25.70#ibcon#read 5, iclass 23, count 0 2006.285.08:20:25.70#ibcon#about to read 6, iclass 23, count 0 2006.285.08:20:25.70#ibcon#read 6, iclass 23, count 0 2006.285.08:20:25.70#ibcon#end of sib2, iclass 23, count 0 2006.285.08:20:25.70#ibcon#*mode == 0, iclass 23, count 0 2006.285.08:20:25.70#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.08:20:25.70#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:20:25.70#ibcon#*before write, iclass 23, count 0 2006.285.08:20:25.70#ibcon#enter sib2, iclass 23, count 0 2006.285.08:20:25.70#ibcon#flushed, iclass 23, count 0 2006.285.08:20:25.70#ibcon#about to write, iclass 23, count 0 2006.285.08:20:25.70#ibcon#wrote, iclass 23, count 0 2006.285.08:20:25.70#ibcon#about to read 3, iclass 23, count 0 2006.285.08:20:25.74#ibcon#read 3, iclass 23, count 0 2006.285.08:20:25.74#ibcon#about to read 4, iclass 23, count 0 2006.285.08:20:25.74#ibcon#read 4, iclass 23, count 0 2006.285.08:20:25.74#ibcon#about to read 5, iclass 23, count 0 2006.285.08:20:25.74#ibcon#read 5, iclass 23, count 0 2006.285.08:20:25.74#ibcon#about to read 6, iclass 23, count 0 2006.285.08:20:25.74#ibcon#read 6, iclass 23, count 0 2006.285.08:20:25.74#ibcon#end of sib2, iclass 23, count 0 2006.285.08:20:25.74#ibcon#*after write, iclass 23, count 0 2006.285.08:20:25.74#ibcon#*before return 0, iclass 23, count 0 2006.285.08:20:25.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:20:25.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:20:25.74#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.08:20:25.74#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.08:20:25.74$vck44/vb=4,5 2006.285.08:20:25.74#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.08:20:25.74#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.08:20:25.74#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:25.74#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:20:25.80#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:20:25.80#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:20:25.80#ibcon#enter wrdev, iclass 25, count 2 2006.285.08:20:25.80#ibcon#first serial, iclass 25, count 2 2006.285.08:20:25.80#ibcon#enter sib2, iclass 25, count 2 2006.285.08:20:25.80#ibcon#flushed, iclass 25, count 2 2006.285.08:20:25.80#ibcon#about to write, iclass 25, count 2 2006.285.08:20:25.80#ibcon#wrote, iclass 25, count 2 2006.285.08:20:25.80#ibcon#about to read 3, iclass 25, count 2 2006.285.08:20:25.82#ibcon#read 3, iclass 25, count 2 2006.285.08:20:25.82#ibcon#about to read 4, iclass 25, count 2 2006.285.08:20:25.82#ibcon#read 4, iclass 25, count 2 2006.285.08:20:25.82#ibcon#about to read 5, iclass 25, count 2 2006.285.08:20:25.82#ibcon#read 5, iclass 25, count 2 2006.285.08:20:25.82#ibcon#about to read 6, iclass 25, count 2 2006.285.08:20:25.82#ibcon#read 6, iclass 25, count 2 2006.285.08:20:25.82#ibcon#end of sib2, iclass 25, count 2 2006.285.08:20:25.82#ibcon#*mode == 0, iclass 25, count 2 2006.285.08:20:25.82#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.08:20:25.82#ibcon#[27=AT04-05\r\n] 2006.285.08:20:25.82#ibcon#*before write, iclass 25, count 2 2006.285.08:20:25.82#ibcon#enter sib2, iclass 25, count 2 2006.285.08:20:25.82#ibcon#flushed, iclass 25, count 2 2006.285.08:20:25.82#ibcon#about to write, iclass 25, count 2 2006.285.08:20:25.82#ibcon#wrote, iclass 25, count 2 2006.285.08:20:25.82#ibcon#about to read 3, iclass 25, count 2 2006.285.08:20:25.85#ibcon#read 3, iclass 25, count 2 2006.285.08:20:25.85#ibcon#about to read 4, iclass 25, count 2 2006.285.08:20:25.85#ibcon#read 4, iclass 25, count 2 2006.285.08:20:25.85#ibcon#about to read 5, iclass 25, count 2 2006.285.08:20:25.85#ibcon#read 5, iclass 25, count 2 2006.285.08:20:25.85#ibcon#about to read 6, iclass 25, count 2 2006.285.08:20:25.85#ibcon#read 6, iclass 25, count 2 2006.285.08:20:25.85#ibcon#end of sib2, iclass 25, count 2 2006.285.08:20:25.85#ibcon#*after write, iclass 25, count 2 2006.285.08:20:25.85#ibcon#*before return 0, iclass 25, count 2 2006.285.08:20:25.85#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:20:25.85#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:20:25.85#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.08:20:25.85#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:25.85#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:20:25.97#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:20:25.97#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:20:25.97#ibcon#enter wrdev, iclass 25, count 0 2006.285.08:20:25.97#ibcon#first serial, iclass 25, count 0 2006.285.08:20:25.97#ibcon#enter sib2, iclass 25, count 0 2006.285.08:20:25.97#ibcon#flushed, iclass 25, count 0 2006.285.08:20:25.97#ibcon#about to write, iclass 25, count 0 2006.285.08:20:25.97#ibcon#wrote, iclass 25, count 0 2006.285.08:20:25.97#ibcon#about to read 3, iclass 25, count 0 2006.285.08:20:25.99#ibcon#read 3, iclass 25, count 0 2006.285.08:20:25.99#ibcon#about to read 4, iclass 25, count 0 2006.285.08:20:25.99#ibcon#read 4, iclass 25, count 0 2006.285.08:20:25.99#ibcon#about to read 5, iclass 25, count 0 2006.285.08:20:25.99#ibcon#read 5, iclass 25, count 0 2006.285.08:20:25.99#ibcon#about to read 6, iclass 25, count 0 2006.285.08:20:25.99#ibcon#read 6, iclass 25, count 0 2006.285.08:20:25.99#ibcon#end of sib2, iclass 25, count 0 2006.285.08:20:25.99#ibcon#*mode == 0, iclass 25, count 0 2006.285.08:20:25.99#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.08:20:25.99#ibcon#[27=USB\r\n] 2006.285.08:20:25.99#ibcon#*before write, iclass 25, count 0 2006.285.08:20:25.99#ibcon#enter sib2, iclass 25, count 0 2006.285.08:20:25.99#ibcon#flushed, iclass 25, count 0 2006.285.08:20:25.99#ibcon#about to write, iclass 25, count 0 2006.285.08:20:25.99#ibcon#wrote, iclass 25, count 0 2006.285.08:20:25.99#ibcon#about to read 3, iclass 25, count 0 2006.285.08:20:26.02#ibcon#read 3, iclass 25, count 0 2006.285.08:20:26.02#ibcon#about to read 4, iclass 25, count 0 2006.285.08:20:26.02#ibcon#read 4, iclass 25, count 0 2006.285.08:20:26.02#ibcon#about to read 5, iclass 25, count 0 2006.285.08:20:26.02#ibcon#read 5, iclass 25, count 0 2006.285.08:20:26.02#ibcon#about to read 6, iclass 25, count 0 2006.285.08:20:26.02#ibcon#read 6, iclass 25, count 0 2006.285.08:20:26.02#ibcon#end of sib2, iclass 25, count 0 2006.285.08:20:26.02#ibcon#*after write, iclass 25, count 0 2006.285.08:20:26.02#ibcon#*before return 0, iclass 25, count 0 2006.285.08:20:26.02#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:20:26.02#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:20:26.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.08:20:26.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.08:20:26.02$vck44/vblo=5,709.99 2006.285.08:20:26.02#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.08:20:26.02#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.08:20:26.02#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:26.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:20:26.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:20:26.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:20:26.02#ibcon#enter wrdev, iclass 27, count 0 2006.285.08:20:26.02#ibcon#first serial, iclass 27, count 0 2006.285.08:20:26.02#ibcon#enter sib2, iclass 27, count 0 2006.285.08:20:26.02#ibcon#flushed, iclass 27, count 0 2006.285.08:20:26.02#ibcon#about to write, iclass 27, count 0 2006.285.08:20:26.02#ibcon#wrote, iclass 27, count 0 2006.285.08:20:26.02#ibcon#about to read 3, iclass 27, count 0 2006.285.08:20:26.04#ibcon#read 3, iclass 27, count 0 2006.285.08:20:26.04#ibcon#about to read 4, iclass 27, count 0 2006.285.08:20:26.04#ibcon#read 4, iclass 27, count 0 2006.285.08:20:26.04#ibcon#about to read 5, iclass 27, count 0 2006.285.08:20:26.04#ibcon#read 5, iclass 27, count 0 2006.285.08:20:26.04#ibcon#about to read 6, iclass 27, count 0 2006.285.08:20:26.04#ibcon#read 6, iclass 27, count 0 2006.285.08:20:26.04#ibcon#end of sib2, iclass 27, count 0 2006.285.08:20:26.04#ibcon#*mode == 0, iclass 27, count 0 2006.285.08:20:26.04#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.08:20:26.04#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:20:26.04#ibcon#*before write, iclass 27, count 0 2006.285.08:20:26.04#ibcon#enter sib2, iclass 27, count 0 2006.285.08:20:26.04#ibcon#flushed, iclass 27, count 0 2006.285.08:20:26.04#ibcon#about to write, iclass 27, count 0 2006.285.08:20:26.04#ibcon#wrote, iclass 27, count 0 2006.285.08:20:26.04#ibcon#about to read 3, iclass 27, count 0 2006.285.08:20:26.08#ibcon#read 3, iclass 27, count 0 2006.285.08:20:26.08#ibcon#about to read 4, iclass 27, count 0 2006.285.08:20:26.08#ibcon#read 4, iclass 27, count 0 2006.285.08:20:26.08#ibcon#about to read 5, iclass 27, count 0 2006.285.08:20:26.08#ibcon#read 5, iclass 27, count 0 2006.285.08:20:26.08#ibcon#about to read 6, iclass 27, count 0 2006.285.08:20:26.08#ibcon#read 6, iclass 27, count 0 2006.285.08:20:26.08#ibcon#end of sib2, iclass 27, count 0 2006.285.08:20:26.08#ibcon#*after write, iclass 27, count 0 2006.285.08:20:26.08#ibcon#*before return 0, iclass 27, count 0 2006.285.08:20:26.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:20:26.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:20:26.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.08:20:26.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.08:20:26.08$vck44/vb=5,4 2006.285.08:20:26.08#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.08:20:26.08#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.08:20:26.08#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:26.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:20:26.14#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:20:26.14#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:20:26.14#ibcon#enter wrdev, iclass 29, count 2 2006.285.08:20:26.14#ibcon#first serial, iclass 29, count 2 2006.285.08:20:26.14#ibcon#enter sib2, iclass 29, count 2 2006.285.08:20:26.14#ibcon#flushed, iclass 29, count 2 2006.285.08:20:26.14#ibcon#about to write, iclass 29, count 2 2006.285.08:20:26.14#ibcon#wrote, iclass 29, count 2 2006.285.08:20:26.14#ibcon#about to read 3, iclass 29, count 2 2006.285.08:20:26.16#ibcon#read 3, iclass 29, count 2 2006.285.08:20:26.16#ibcon#about to read 4, iclass 29, count 2 2006.285.08:20:26.16#ibcon#read 4, iclass 29, count 2 2006.285.08:20:26.16#ibcon#about to read 5, iclass 29, count 2 2006.285.08:20:26.16#ibcon#read 5, iclass 29, count 2 2006.285.08:20:26.16#ibcon#about to read 6, iclass 29, count 2 2006.285.08:20:26.16#ibcon#read 6, iclass 29, count 2 2006.285.08:20:26.16#ibcon#end of sib2, iclass 29, count 2 2006.285.08:20:26.16#ibcon#*mode == 0, iclass 29, count 2 2006.285.08:20:26.16#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.08:20:26.16#ibcon#[27=AT05-04\r\n] 2006.285.08:20:26.16#ibcon#*before write, iclass 29, count 2 2006.285.08:20:26.16#ibcon#enter sib2, iclass 29, count 2 2006.285.08:20:26.16#ibcon#flushed, iclass 29, count 2 2006.285.08:20:26.16#ibcon#about to write, iclass 29, count 2 2006.285.08:20:26.16#ibcon#wrote, iclass 29, count 2 2006.285.08:20:26.16#ibcon#about to read 3, iclass 29, count 2 2006.285.08:20:26.19#ibcon#read 3, iclass 29, count 2 2006.285.08:20:26.19#ibcon#about to read 4, iclass 29, count 2 2006.285.08:20:26.19#ibcon#read 4, iclass 29, count 2 2006.285.08:20:26.19#ibcon#about to read 5, iclass 29, count 2 2006.285.08:20:26.19#ibcon#read 5, iclass 29, count 2 2006.285.08:20:26.19#ibcon#about to read 6, iclass 29, count 2 2006.285.08:20:26.19#ibcon#read 6, iclass 29, count 2 2006.285.08:20:26.19#ibcon#end of sib2, iclass 29, count 2 2006.285.08:20:26.19#ibcon#*after write, iclass 29, count 2 2006.285.08:20:26.19#ibcon#*before return 0, iclass 29, count 2 2006.285.08:20:26.19#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:20:26.19#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:20:26.19#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.08:20:26.19#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:26.19#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:20:26.31#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:20:26.31#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:20:26.31#ibcon#enter wrdev, iclass 29, count 0 2006.285.08:20:26.31#ibcon#first serial, iclass 29, count 0 2006.285.08:20:26.31#ibcon#enter sib2, iclass 29, count 0 2006.285.08:20:26.31#ibcon#flushed, iclass 29, count 0 2006.285.08:20:26.31#ibcon#about to write, iclass 29, count 0 2006.285.08:20:26.31#ibcon#wrote, iclass 29, count 0 2006.285.08:20:26.31#ibcon#about to read 3, iclass 29, count 0 2006.285.08:20:26.33#ibcon#read 3, iclass 29, count 0 2006.285.08:20:26.33#ibcon#about to read 4, iclass 29, count 0 2006.285.08:20:26.33#ibcon#read 4, iclass 29, count 0 2006.285.08:20:26.33#ibcon#about to read 5, iclass 29, count 0 2006.285.08:20:26.33#ibcon#read 5, iclass 29, count 0 2006.285.08:20:26.33#ibcon#about to read 6, iclass 29, count 0 2006.285.08:20:26.33#ibcon#read 6, iclass 29, count 0 2006.285.08:20:26.33#ibcon#end of sib2, iclass 29, count 0 2006.285.08:20:26.33#ibcon#*mode == 0, iclass 29, count 0 2006.285.08:20:26.33#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.08:20:26.33#ibcon#[27=USB\r\n] 2006.285.08:20:26.33#ibcon#*before write, iclass 29, count 0 2006.285.08:20:26.33#ibcon#enter sib2, iclass 29, count 0 2006.285.08:20:26.33#ibcon#flushed, iclass 29, count 0 2006.285.08:20:26.33#ibcon#about to write, iclass 29, count 0 2006.285.08:20:26.33#ibcon#wrote, iclass 29, count 0 2006.285.08:20:26.33#ibcon#about to read 3, iclass 29, count 0 2006.285.08:20:26.36#ibcon#read 3, iclass 29, count 0 2006.285.08:20:26.36#ibcon#about to read 4, iclass 29, count 0 2006.285.08:20:26.36#ibcon#read 4, iclass 29, count 0 2006.285.08:20:26.36#ibcon#about to read 5, iclass 29, count 0 2006.285.08:20:26.36#ibcon#read 5, iclass 29, count 0 2006.285.08:20:26.36#ibcon#about to read 6, iclass 29, count 0 2006.285.08:20:26.36#ibcon#read 6, iclass 29, count 0 2006.285.08:20:26.36#ibcon#end of sib2, iclass 29, count 0 2006.285.08:20:26.36#ibcon#*after write, iclass 29, count 0 2006.285.08:20:26.36#ibcon#*before return 0, iclass 29, count 0 2006.285.08:20:26.36#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:20:26.36#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:20:26.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.08:20:26.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.08:20:26.36$vck44/vblo=6,719.99 2006.285.08:20:26.36#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.08:20:26.36#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.08:20:26.36#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:26.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:20:26.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:20:26.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:20:26.36#ibcon#enter wrdev, iclass 31, count 0 2006.285.08:20:26.36#ibcon#first serial, iclass 31, count 0 2006.285.08:20:26.36#ibcon#enter sib2, iclass 31, count 0 2006.285.08:20:26.36#ibcon#flushed, iclass 31, count 0 2006.285.08:20:26.36#ibcon#about to write, iclass 31, count 0 2006.285.08:20:26.36#ibcon#wrote, iclass 31, count 0 2006.285.08:20:26.36#ibcon#about to read 3, iclass 31, count 0 2006.285.08:20:26.38#ibcon#read 3, iclass 31, count 0 2006.285.08:20:26.38#ibcon#about to read 4, iclass 31, count 0 2006.285.08:20:26.38#ibcon#read 4, iclass 31, count 0 2006.285.08:20:26.38#ibcon#about to read 5, iclass 31, count 0 2006.285.08:20:26.38#ibcon#read 5, iclass 31, count 0 2006.285.08:20:26.38#ibcon#about to read 6, iclass 31, count 0 2006.285.08:20:26.38#ibcon#read 6, iclass 31, count 0 2006.285.08:20:26.38#ibcon#end of sib2, iclass 31, count 0 2006.285.08:20:26.38#ibcon#*mode == 0, iclass 31, count 0 2006.285.08:20:26.38#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.08:20:26.38#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:20:26.38#ibcon#*before write, iclass 31, count 0 2006.285.08:20:26.38#ibcon#enter sib2, iclass 31, count 0 2006.285.08:20:26.38#ibcon#flushed, iclass 31, count 0 2006.285.08:20:26.38#ibcon#about to write, iclass 31, count 0 2006.285.08:20:26.38#ibcon#wrote, iclass 31, count 0 2006.285.08:20:26.38#ibcon#about to read 3, iclass 31, count 0 2006.285.08:20:26.42#ibcon#read 3, iclass 31, count 0 2006.285.08:20:26.42#ibcon#about to read 4, iclass 31, count 0 2006.285.08:20:26.42#ibcon#read 4, iclass 31, count 0 2006.285.08:20:26.42#ibcon#about to read 5, iclass 31, count 0 2006.285.08:20:26.42#ibcon#read 5, iclass 31, count 0 2006.285.08:20:26.42#ibcon#about to read 6, iclass 31, count 0 2006.285.08:20:26.42#ibcon#read 6, iclass 31, count 0 2006.285.08:20:26.42#ibcon#end of sib2, iclass 31, count 0 2006.285.08:20:26.42#ibcon#*after write, iclass 31, count 0 2006.285.08:20:26.42#ibcon#*before return 0, iclass 31, count 0 2006.285.08:20:26.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:20:26.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:20:26.42#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.08:20:26.42#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.08:20:26.42$vck44/vb=6,3 2006.285.08:20:26.42#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.08:20:26.42#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.08:20:26.42#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:26.42#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:20:26.48#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:20:26.48#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:20:26.48#ibcon#enter wrdev, iclass 33, count 2 2006.285.08:20:26.48#ibcon#first serial, iclass 33, count 2 2006.285.08:20:26.48#ibcon#enter sib2, iclass 33, count 2 2006.285.08:20:26.48#ibcon#flushed, iclass 33, count 2 2006.285.08:20:26.48#ibcon#about to write, iclass 33, count 2 2006.285.08:20:26.48#ibcon#wrote, iclass 33, count 2 2006.285.08:20:26.48#ibcon#about to read 3, iclass 33, count 2 2006.285.08:20:26.50#ibcon#read 3, iclass 33, count 2 2006.285.08:20:26.50#ibcon#about to read 4, iclass 33, count 2 2006.285.08:20:26.50#ibcon#read 4, iclass 33, count 2 2006.285.08:20:26.50#ibcon#about to read 5, iclass 33, count 2 2006.285.08:20:26.50#ibcon#read 5, iclass 33, count 2 2006.285.08:20:26.50#ibcon#about to read 6, iclass 33, count 2 2006.285.08:20:26.50#ibcon#read 6, iclass 33, count 2 2006.285.08:20:26.50#ibcon#end of sib2, iclass 33, count 2 2006.285.08:20:26.50#ibcon#*mode == 0, iclass 33, count 2 2006.285.08:20:26.50#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.08:20:26.50#ibcon#[27=AT06-03\r\n] 2006.285.08:20:26.50#ibcon#*before write, iclass 33, count 2 2006.285.08:20:26.50#ibcon#enter sib2, iclass 33, count 2 2006.285.08:20:26.50#ibcon#flushed, iclass 33, count 2 2006.285.08:20:26.50#ibcon#about to write, iclass 33, count 2 2006.285.08:20:26.50#ibcon#wrote, iclass 33, count 2 2006.285.08:20:26.50#ibcon#about to read 3, iclass 33, count 2 2006.285.08:20:26.53#ibcon#read 3, iclass 33, count 2 2006.285.08:20:26.53#ibcon#about to read 4, iclass 33, count 2 2006.285.08:20:26.53#ibcon#read 4, iclass 33, count 2 2006.285.08:20:26.53#ibcon#about to read 5, iclass 33, count 2 2006.285.08:20:26.53#ibcon#read 5, iclass 33, count 2 2006.285.08:20:26.53#ibcon#about to read 6, iclass 33, count 2 2006.285.08:20:26.53#ibcon#read 6, iclass 33, count 2 2006.285.08:20:26.53#ibcon#end of sib2, iclass 33, count 2 2006.285.08:20:26.53#ibcon#*after write, iclass 33, count 2 2006.285.08:20:26.53#ibcon#*before return 0, iclass 33, count 2 2006.285.08:20:26.53#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:20:26.53#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:20:26.53#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.08:20:26.53#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:26.53#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:20:26.65#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:20:26.65#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:20:26.65#ibcon#enter wrdev, iclass 33, count 0 2006.285.08:20:26.65#ibcon#first serial, iclass 33, count 0 2006.285.08:20:26.65#ibcon#enter sib2, iclass 33, count 0 2006.285.08:20:26.65#ibcon#flushed, iclass 33, count 0 2006.285.08:20:26.65#ibcon#about to write, iclass 33, count 0 2006.285.08:20:26.65#ibcon#wrote, iclass 33, count 0 2006.285.08:20:26.65#ibcon#about to read 3, iclass 33, count 0 2006.285.08:20:26.67#ibcon#read 3, iclass 33, count 0 2006.285.08:20:26.67#ibcon#about to read 4, iclass 33, count 0 2006.285.08:20:26.67#ibcon#read 4, iclass 33, count 0 2006.285.08:20:26.67#ibcon#about to read 5, iclass 33, count 0 2006.285.08:20:26.67#ibcon#read 5, iclass 33, count 0 2006.285.08:20:26.67#ibcon#about to read 6, iclass 33, count 0 2006.285.08:20:26.67#ibcon#read 6, iclass 33, count 0 2006.285.08:20:26.67#ibcon#end of sib2, iclass 33, count 0 2006.285.08:20:26.67#ibcon#*mode == 0, iclass 33, count 0 2006.285.08:20:26.67#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.08:20:26.67#ibcon#[27=USB\r\n] 2006.285.08:20:26.67#ibcon#*before write, iclass 33, count 0 2006.285.08:20:26.67#ibcon#enter sib2, iclass 33, count 0 2006.285.08:20:26.67#ibcon#flushed, iclass 33, count 0 2006.285.08:20:26.67#ibcon#about to write, iclass 33, count 0 2006.285.08:20:26.67#ibcon#wrote, iclass 33, count 0 2006.285.08:20:26.67#ibcon#about to read 3, iclass 33, count 0 2006.285.08:20:26.70#ibcon#read 3, iclass 33, count 0 2006.285.08:20:26.70#ibcon#about to read 4, iclass 33, count 0 2006.285.08:20:26.70#ibcon#read 4, iclass 33, count 0 2006.285.08:20:26.70#ibcon#about to read 5, iclass 33, count 0 2006.285.08:20:26.70#ibcon#read 5, iclass 33, count 0 2006.285.08:20:26.70#ibcon#about to read 6, iclass 33, count 0 2006.285.08:20:26.70#ibcon#read 6, iclass 33, count 0 2006.285.08:20:26.70#ibcon#end of sib2, iclass 33, count 0 2006.285.08:20:26.70#ibcon#*after write, iclass 33, count 0 2006.285.08:20:26.70#ibcon#*before return 0, iclass 33, count 0 2006.285.08:20:26.70#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:20:26.70#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:20:26.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.08:20:26.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.08:20:26.70$vck44/vblo=7,734.99 2006.285.08:20:26.70#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.08:20:26.70#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.08:20:26.70#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:26.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:20:26.70#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:20:26.70#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:20:26.70#ibcon#enter wrdev, iclass 35, count 0 2006.285.08:20:26.70#ibcon#first serial, iclass 35, count 0 2006.285.08:20:26.70#ibcon#enter sib2, iclass 35, count 0 2006.285.08:20:26.70#ibcon#flushed, iclass 35, count 0 2006.285.08:20:26.70#ibcon#about to write, iclass 35, count 0 2006.285.08:20:26.70#ibcon#wrote, iclass 35, count 0 2006.285.08:20:26.70#ibcon#about to read 3, iclass 35, count 0 2006.285.08:20:26.72#ibcon#read 3, iclass 35, count 0 2006.285.08:20:26.72#ibcon#about to read 4, iclass 35, count 0 2006.285.08:20:26.72#ibcon#read 4, iclass 35, count 0 2006.285.08:20:26.72#ibcon#about to read 5, iclass 35, count 0 2006.285.08:20:26.72#ibcon#read 5, iclass 35, count 0 2006.285.08:20:26.72#ibcon#about to read 6, iclass 35, count 0 2006.285.08:20:26.72#ibcon#read 6, iclass 35, count 0 2006.285.08:20:26.72#ibcon#end of sib2, iclass 35, count 0 2006.285.08:20:26.72#ibcon#*mode == 0, iclass 35, count 0 2006.285.08:20:26.72#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.08:20:26.72#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:20:26.72#ibcon#*before write, iclass 35, count 0 2006.285.08:20:26.72#ibcon#enter sib2, iclass 35, count 0 2006.285.08:20:26.72#ibcon#flushed, iclass 35, count 0 2006.285.08:20:26.72#ibcon#about to write, iclass 35, count 0 2006.285.08:20:26.72#ibcon#wrote, iclass 35, count 0 2006.285.08:20:26.72#ibcon#about to read 3, iclass 35, count 0 2006.285.08:20:26.76#ibcon#read 3, iclass 35, count 0 2006.285.08:20:26.76#ibcon#about to read 4, iclass 35, count 0 2006.285.08:20:26.76#ibcon#read 4, iclass 35, count 0 2006.285.08:20:26.76#ibcon#about to read 5, iclass 35, count 0 2006.285.08:20:26.76#ibcon#read 5, iclass 35, count 0 2006.285.08:20:26.76#ibcon#about to read 6, iclass 35, count 0 2006.285.08:20:26.76#ibcon#read 6, iclass 35, count 0 2006.285.08:20:26.76#ibcon#end of sib2, iclass 35, count 0 2006.285.08:20:26.76#ibcon#*after write, iclass 35, count 0 2006.285.08:20:26.76#ibcon#*before return 0, iclass 35, count 0 2006.285.08:20:26.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:20:26.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:20:26.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.08:20:26.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.08:20:26.76$vck44/vb=7,4 2006.285.08:20:26.76#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.08:20:26.76#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.08:20:26.76#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:26.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:20:26.82#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:20:26.82#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:20:26.82#ibcon#enter wrdev, iclass 37, count 2 2006.285.08:20:26.82#ibcon#first serial, iclass 37, count 2 2006.285.08:20:26.82#ibcon#enter sib2, iclass 37, count 2 2006.285.08:20:26.82#ibcon#flushed, iclass 37, count 2 2006.285.08:20:26.82#ibcon#about to write, iclass 37, count 2 2006.285.08:20:26.82#ibcon#wrote, iclass 37, count 2 2006.285.08:20:26.82#ibcon#about to read 3, iclass 37, count 2 2006.285.08:20:26.84#ibcon#read 3, iclass 37, count 2 2006.285.08:20:26.84#ibcon#about to read 4, iclass 37, count 2 2006.285.08:20:26.84#ibcon#read 4, iclass 37, count 2 2006.285.08:20:26.84#ibcon#about to read 5, iclass 37, count 2 2006.285.08:20:26.84#ibcon#read 5, iclass 37, count 2 2006.285.08:20:26.84#ibcon#about to read 6, iclass 37, count 2 2006.285.08:20:26.84#ibcon#read 6, iclass 37, count 2 2006.285.08:20:26.84#ibcon#end of sib2, iclass 37, count 2 2006.285.08:20:26.84#ibcon#*mode == 0, iclass 37, count 2 2006.285.08:20:26.84#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.08:20:26.84#ibcon#[27=AT07-04\r\n] 2006.285.08:20:26.84#ibcon#*before write, iclass 37, count 2 2006.285.08:20:26.84#ibcon#enter sib2, iclass 37, count 2 2006.285.08:20:26.84#ibcon#flushed, iclass 37, count 2 2006.285.08:20:26.84#ibcon#about to write, iclass 37, count 2 2006.285.08:20:26.84#ibcon#wrote, iclass 37, count 2 2006.285.08:20:26.84#ibcon#about to read 3, iclass 37, count 2 2006.285.08:20:26.87#ibcon#read 3, iclass 37, count 2 2006.285.08:20:26.87#ibcon#about to read 4, iclass 37, count 2 2006.285.08:20:26.87#ibcon#read 4, iclass 37, count 2 2006.285.08:20:26.87#ibcon#about to read 5, iclass 37, count 2 2006.285.08:20:26.87#ibcon#read 5, iclass 37, count 2 2006.285.08:20:26.87#ibcon#about to read 6, iclass 37, count 2 2006.285.08:20:26.87#ibcon#read 6, iclass 37, count 2 2006.285.08:20:26.87#ibcon#end of sib2, iclass 37, count 2 2006.285.08:20:26.87#ibcon#*after write, iclass 37, count 2 2006.285.08:20:26.87#ibcon#*before return 0, iclass 37, count 2 2006.285.08:20:26.87#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:20:26.87#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:20:26.87#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.08:20:26.87#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:26.87#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:20:26.99#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:20:26.99#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:20:26.99#ibcon#enter wrdev, iclass 37, count 0 2006.285.08:20:26.99#ibcon#first serial, iclass 37, count 0 2006.285.08:20:26.99#ibcon#enter sib2, iclass 37, count 0 2006.285.08:20:26.99#ibcon#flushed, iclass 37, count 0 2006.285.08:20:26.99#ibcon#about to write, iclass 37, count 0 2006.285.08:20:26.99#ibcon#wrote, iclass 37, count 0 2006.285.08:20:26.99#ibcon#about to read 3, iclass 37, count 0 2006.285.08:20:27.01#ibcon#read 3, iclass 37, count 0 2006.285.08:20:27.01#ibcon#about to read 4, iclass 37, count 0 2006.285.08:20:27.01#ibcon#read 4, iclass 37, count 0 2006.285.08:20:27.01#ibcon#about to read 5, iclass 37, count 0 2006.285.08:20:27.01#ibcon#read 5, iclass 37, count 0 2006.285.08:20:27.01#ibcon#about to read 6, iclass 37, count 0 2006.285.08:20:27.01#ibcon#read 6, iclass 37, count 0 2006.285.08:20:27.01#ibcon#end of sib2, iclass 37, count 0 2006.285.08:20:27.01#ibcon#*mode == 0, iclass 37, count 0 2006.285.08:20:27.01#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.08:20:27.01#ibcon#[27=USB\r\n] 2006.285.08:20:27.01#ibcon#*before write, iclass 37, count 0 2006.285.08:20:27.01#ibcon#enter sib2, iclass 37, count 0 2006.285.08:20:27.01#ibcon#flushed, iclass 37, count 0 2006.285.08:20:27.01#ibcon#about to write, iclass 37, count 0 2006.285.08:20:27.01#ibcon#wrote, iclass 37, count 0 2006.285.08:20:27.01#ibcon#about to read 3, iclass 37, count 0 2006.285.08:20:27.04#ibcon#read 3, iclass 37, count 0 2006.285.08:20:27.04#ibcon#about to read 4, iclass 37, count 0 2006.285.08:20:27.04#ibcon#read 4, iclass 37, count 0 2006.285.08:20:27.04#ibcon#about to read 5, iclass 37, count 0 2006.285.08:20:27.04#ibcon#read 5, iclass 37, count 0 2006.285.08:20:27.04#ibcon#about to read 6, iclass 37, count 0 2006.285.08:20:27.04#ibcon#read 6, iclass 37, count 0 2006.285.08:20:27.04#ibcon#end of sib2, iclass 37, count 0 2006.285.08:20:27.04#ibcon#*after write, iclass 37, count 0 2006.285.08:20:27.04#ibcon#*before return 0, iclass 37, count 0 2006.285.08:20:27.04#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:20:27.04#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:20:27.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.08:20:27.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.08:20:27.04$vck44/vblo=8,744.99 2006.285.08:20:27.04#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.08:20:27.04#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.08:20:27.04#ibcon#ireg 17 cls_cnt 0 2006.285.08:20:27.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:20:27.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:20:27.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:20:27.04#ibcon#enter wrdev, iclass 39, count 0 2006.285.08:20:27.04#ibcon#first serial, iclass 39, count 0 2006.285.08:20:27.04#ibcon#enter sib2, iclass 39, count 0 2006.285.08:20:27.04#ibcon#flushed, iclass 39, count 0 2006.285.08:20:27.04#ibcon#about to write, iclass 39, count 0 2006.285.08:20:27.04#ibcon#wrote, iclass 39, count 0 2006.285.08:20:27.04#ibcon#about to read 3, iclass 39, count 0 2006.285.08:20:27.06#ibcon#read 3, iclass 39, count 0 2006.285.08:20:27.06#ibcon#about to read 4, iclass 39, count 0 2006.285.08:20:27.06#ibcon#read 4, iclass 39, count 0 2006.285.08:20:27.06#ibcon#about to read 5, iclass 39, count 0 2006.285.08:20:27.06#ibcon#read 5, iclass 39, count 0 2006.285.08:20:27.06#ibcon#about to read 6, iclass 39, count 0 2006.285.08:20:27.06#ibcon#read 6, iclass 39, count 0 2006.285.08:20:27.06#ibcon#end of sib2, iclass 39, count 0 2006.285.08:20:27.06#ibcon#*mode == 0, iclass 39, count 0 2006.285.08:20:27.06#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.08:20:27.06#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:20:27.06#ibcon#*before write, iclass 39, count 0 2006.285.08:20:27.06#ibcon#enter sib2, iclass 39, count 0 2006.285.08:20:27.06#ibcon#flushed, iclass 39, count 0 2006.285.08:20:27.06#ibcon#about to write, iclass 39, count 0 2006.285.08:20:27.06#ibcon#wrote, iclass 39, count 0 2006.285.08:20:27.06#ibcon#about to read 3, iclass 39, count 0 2006.285.08:20:27.10#ibcon#read 3, iclass 39, count 0 2006.285.08:20:27.10#ibcon#about to read 4, iclass 39, count 0 2006.285.08:20:27.10#ibcon#read 4, iclass 39, count 0 2006.285.08:20:27.10#ibcon#about to read 5, iclass 39, count 0 2006.285.08:20:27.10#ibcon#read 5, iclass 39, count 0 2006.285.08:20:27.10#ibcon#about to read 6, iclass 39, count 0 2006.285.08:20:27.10#ibcon#read 6, iclass 39, count 0 2006.285.08:20:27.10#ibcon#end of sib2, iclass 39, count 0 2006.285.08:20:27.10#ibcon#*after write, iclass 39, count 0 2006.285.08:20:27.10#ibcon#*before return 0, iclass 39, count 0 2006.285.08:20:27.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:20:27.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:20:27.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.08:20:27.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.08:20:27.10$vck44/vb=8,4 2006.285.08:20:27.10#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.08:20:27.10#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.08:20:27.10#ibcon#ireg 11 cls_cnt 2 2006.285.08:20:27.10#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:20:27.16#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:20:27.16#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:20:27.16#ibcon#enter wrdev, iclass 3, count 2 2006.285.08:20:27.16#ibcon#first serial, iclass 3, count 2 2006.285.08:20:27.16#ibcon#enter sib2, iclass 3, count 2 2006.285.08:20:27.16#ibcon#flushed, iclass 3, count 2 2006.285.08:20:27.16#ibcon#about to write, iclass 3, count 2 2006.285.08:20:27.16#ibcon#wrote, iclass 3, count 2 2006.285.08:20:27.16#ibcon#about to read 3, iclass 3, count 2 2006.285.08:20:27.18#ibcon#read 3, iclass 3, count 2 2006.285.08:20:27.18#ibcon#about to read 4, iclass 3, count 2 2006.285.08:20:27.18#ibcon#read 4, iclass 3, count 2 2006.285.08:20:27.18#ibcon#about to read 5, iclass 3, count 2 2006.285.08:20:27.18#ibcon#read 5, iclass 3, count 2 2006.285.08:20:27.18#ibcon#about to read 6, iclass 3, count 2 2006.285.08:20:27.18#ibcon#read 6, iclass 3, count 2 2006.285.08:20:27.18#ibcon#end of sib2, iclass 3, count 2 2006.285.08:20:27.18#ibcon#*mode == 0, iclass 3, count 2 2006.285.08:20:27.18#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.08:20:27.18#ibcon#[27=AT08-04\r\n] 2006.285.08:20:27.18#ibcon#*before write, iclass 3, count 2 2006.285.08:20:27.18#ibcon#enter sib2, iclass 3, count 2 2006.285.08:20:27.18#ibcon#flushed, iclass 3, count 2 2006.285.08:20:27.18#ibcon#about to write, iclass 3, count 2 2006.285.08:20:27.18#ibcon#wrote, iclass 3, count 2 2006.285.08:20:27.18#ibcon#about to read 3, iclass 3, count 2 2006.285.08:20:27.21#ibcon#read 3, iclass 3, count 2 2006.285.08:20:27.21#ibcon#about to read 4, iclass 3, count 2 2006.285.08:20:27.21#ibcon#read 4, iclass 3, count 2 2006.285.08:20:27.21#ibcon#about to read 5, iclass 3, count 2 2006.285.08:20:27.21#ibcon#read 5, iclass 3, count 2 2006.285.08:20:27.21#ibcon#about to read 6, iclass 3, count 2 2006.285.08:20:27.21#ibcon#read 6, iclass 3, count 2 2006.285.08:20:27.21#ibcon#end of sib2, iclass 3, count 2 2006.285.08:20:27.21#ibcon#*after write, iclass 3, count 2 2006.285.08:20:27.21#ibcon#*before return 0, iclass 3, count 2 2006.285.08:20:27.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:20:27.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:20:27.21#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.08:20:27.21#ibcon#ireg 7 cls_cnt 0 2006.285.08:20:27.21#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:20:27.33#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:20:27.33#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:20:27.33#ibcon#enter wrdev, iclass 3, count 0 2006.285.08:20:27.33#ibcon#first serial, iclass 3, count 0 2006.285.08:20:27.33#ibcon#enter sib2, iclass 3, count 0 2006.285.08:20:27.33#ibcon#flushed, iclass 3, count 0 2006.285.08:20:27.33#ibcon#about to write, iclass 3, count 0 2006.285.08:20:27.33#ibcon#wrote, iclass 3, count 0 2006.285.08:20:27.33#ibcon#about to read 3, iclass 3, count 0 2006.285.08:20:27.35#ibcon#read 3, iclass 3, count 0 2006.285.08:20:27.35#ibcon#about to read 4, iclass 3, count 0 2006.285.08:20:27.35#ibcon#read 4, iclass 3, count 0 2006.285.08:20:27.35#ibcon#about to read 5, iclass 3, count 0 2006.285.08:20:27.35#ibcon#read 5, iclass 3, count 0 2006.285.08:20:27.35#ibcon#about to read 6, iclass 3, count 0 2006.285.08:20:27.35#ibcon#read 6, iclass 3, count 0 2006.285.08:20:27.35#ibcon#end of sib2, iclass 3, count 0 2006.285.08:20:27.35#ibcon#*mode == 0, iclass 3, count 0 2006.285.08:20:27.35#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.08:20:27.35#ibcon#[27=USB\r\n] 2006.285.08:20:27.35#ibcon#*before write, iclass 3, count 0 2006.285.08:20:27.35#ibcon#enter sib2, iclass 3, count 0 2006.285.08:20:27.35#ibcon#flushed, iclass 3, count 0 2006.285.08:20:27.35#ibcon#about to write, iclass 3, count 0 2006.285.08:20:27.35#ibcon#wrote, iclass 3, count 0 2006.285.08:20:27.35#ibcon#about to read 3, iclass 3, count 0 2006.285.08:20:27.38#ibcon#read 3, iclass 3, count 0 2006.285.08:20:27.38#ibcon#about to read 4, iclass 3, count 0 2006.285.08:20:27.38#ibcon#read 4, iclass 3, count 0 2006.285.08:20:27.38#ibcon#about to read 5, iclass 3, count 0 2006.285.08:20:27.38#ibcon#read 5, iclass 3, count 0 2006.285.08:20:27.38#ibcon#about to read 6, iclass 3, count 0 2006.285.08:20:27.38#ibcon#read 6, iclass 3, count 0 2006.285.08:20:27.38#ibcon#end of sib2, iclass 3, count 0 2006.285.08:20:27.38#ibcon#*after write, iclass 3, count 0 2006.285.08:20:27.38#ibcon#*before return 0, iclass 3, count 0 2006.285.08:20:27.38#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:20:27.38#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:20:27.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.08:20:27.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.08:20:27.38$vck44/vabw=wide 2006.285.08:20:27.38#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.08:20:27.38#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.08:20:27.38#ibcon#ireg 8 cls_cnt 0 2006.285.08:20:27.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:20:27.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:20:27.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:20:27.38#ibcon#enter wrdev, iclass 5, count 0 2006.285.08:20:27.38#ibcon#first serial, iclass 5, count 0 2006.285.08:20:27.38#ibcon#enter sib2, iclass 5, count 0 2006.285.08:20:27.38#ibcon#flushed, iclass 5, count 0 2006.285.08:20:27.38#ibcon#about to write, iclass 5, count 0 2006.285.08:20:27.38#ibcon#wrote, iclass 5, count 0 2006.285.08:20:27.38#ibcon#about to read 3, iclass 5, count 0 2006.285.08:20:27.40#ibcon#read 3, iclass 5, count 0 2006.285.08:20:27.40#ibcon#about to read 4, iclass 5, count 0 2006.285.08:20:27.40#ibcon#read 4, iclass 5, count 0 2006.285.08:20:27.40#ibcon#about to read 5, iclass 5, count 0 2006.285.08:20:27.40#ibcon#read 5, iclass 5, count 0 2006.285.08:20:27.40#ibcon#about to read 6, iclass 5, count 0 2006.285.08:20:27.40#ibcon#read 6, iclass 5, count 0 2006.285.08:20:27.40#ibcon#end of sib2, iclass 5, count 0 2006.285.08:20:27.40#ibcon#*mode == 0, iclass 5, count 0 2006.285.08:20:27.40#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.08:20:27.40#ibcon#[25=BW32\r\n] 2006.285.08:20:27.40#ibcon#*before write, iclass 5, count 0 2006.285.08:20:27.40#ibcon#enter sib2, iclass 5, count 0 2006.285.08:20:27.40#ibcon#flushed, iclass 5, count 0 2006.285.08:20:27.40#ibcon#about to write, iclass 5, count 0 2006.285.08:20:27.40#ibcon#wrote, iclass 5, count 0 2006.285.08:20:27.40#ibcon#about to read 3, iclass 5, count 0 2006.285.08:20:27.43#ibcon#read 3, iclass 5, count 0 2006.285.08:20:27.43#ibcon#about to read 4, iclass 5, count 0 2006.285.08:20:27.43#ibcon#read 4, iclass 5, count 0 2006.285.08:20:27.43#ibcon#about to read 5, iclass 5, count 0 2006.285.08:20:27.43#ibcon#read 5, iclass 5, count 0 2006.285.08:20:27.43#ibcon#about to read 6, iclass 5, count 0 2006.285.08:20:27.43#ibcon#read 6, iclass 5, count 0 2006.285.08:20:27.43#ibcon#end of sib2, iclass 5, count 0 2006.285.08:20:27.43#ibcon#*after write, iclass 5, count 0 2006.285.08:20:27.43#ibcon#*before return 0, iclass 5, count 0 2006.285.08:20:27.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:20:27.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:20:27.43#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.08:20:27.43#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.08:20:27.43$vck44/vbbw=wide 2006.285.08:20:27.43#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.08:20:27.43#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.08:20:27.43#ibcon#ireg 8 cls_cnt 0 2006.285.08:20:27.43#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:20:27.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:20:27.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:20:27.50#ibcon#enter wrdev, iclass 7, count 0 2006.285.08:20:27.50#ibcon#first serial, iclass 7, count 0 2006.285.08:20:27.50#ibcon#enter sib2, iclass 7, count 0 2006.285.08:20:27.50#ibcon#flushed, iclass 7, count 0 2006.285.08:20:27.50#ibcon#about to write, iclass 7, count 0 2006.285.08:20:27.50#ibcon#wrote, iclass 7, count 0 2006.285.08:20:27.50#ibcon#about to read 3, iclass 7, count 0 2006.285.08:20:27.52#ibcon#read 3, iclass 7, count 0 2006.285.08:20:27.52#ibcon#about to read 4, iclass 7, count 0 2006.285.08:20:27.52#ibcon#read 4, iclass 7, count 0 2006.285.08:20:27.52#ibcon#about to read 5, iclass 7, count 0 2006.285.08:20:27.52#ibcon#read 5, iclass 7, count 0 2006.285.08:20:27.52#ibcon#about to read 6, iclass 7, count 0 2006.285.08:20:27.52#ibcon#read 6, iclass 7, count 0 2006.285.08:20:27.52#ibcon#end of sib2, iclass 7, count 0 2006.285.08:20:27.52#ibcon#*mode == 0, iclass 7, count 0 2006.285.08:20:27.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.08:20:27.52#ibcon#[27=BW32\r\n] 2006.285.08:20:27.52#ibcon#*before write, iclass 7, count 0 2006.285.08:20:27.52#ibcon#enter sib2, iclass 7, count 0 2006.285.08:20:27.52#ibcon#flushed, iclass 7, count 0 2006.285.08:20:27.52#ibcon#about to write, iclass 7, count 0 2006.285.08:20:27.52#ibcon#wrote, iclass 7, count 0 2006.285.08:20:27.52#ibcon#about to read 3, iclass 7, count 0 2006.285.08:20:27.55#ibcon#read 3, iclass 7, count 0 2006.285.08:20:27.55#ibcon#about to read 4, iclass 7, count 0 2006.285.08:20:27.55#ibcon#read 4, iclass 7, count 0 2006.285.08:20:27.55#ibcon#about to read 5, iclass 7, count 0 2006.285.08:20:27.55#ibcon#read 5, iclass 7, count 0 2006.285.08:20:27.55#ibcon#about to read 6, iclass 7, count 0 2006.285.08:20:27.55#ibcon#read 6, iclass 7, count 0 2006.285.08:20:27.55#ibcon#end of sib2, iclass 7, count 0 2006.285.08:20:27.55#ibcon#*after write, iclass 7, count 0 2006.285.08:20:27.55#ibcon#*before return 0, iclass 7, count 0 2006.285.08:20:27.55#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:20:27.55#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:20:27.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.08:20:27.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.08:20:27.55$setupk4/ifdk4 2006.285.08:20:27.55$ifdk4/lo= 2006.285.08:20:27.55$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:20:27.55$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:20:27.55$ifdk4/patch= 2006.285.08:20:27.55$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:20:27.55$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:20:27.55$setupk4/!*+20s 2006.285.08:20:34.87#abcon#<5=/04 1.6 3.3 22.46 811014.7\r\n> 2006.285.08:20:34.89#abcon#{5=INTERFACE CLEAR} 2006.285.08:20:34.95#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:20:42.06$setupk4/"tpicd 2006.285.08:20:42.06$setupk4/echo=off 2006.285.08:20:42.06$setupk4/xlog=off 2006.285.08:20:42.06:!2006.285.08:25:06 2006.285.08:20:57.14#trakl#Source acquired 2006.285.08:20:59.14#flagr#flagr/antenna,acquired 2006.285.08:25:06.00:preob 2006.285.08:25:06.14/onsource/TRACKING 2006.285.08:25:06.14:!2006.285.08:25:16 2006.285.08:25:16.00:"tape 2006.285.08:25:16.00:"st=record 2006.285.08:25:16.00:data_valid=on 2006.285.08:25:16.00:midob 2006.285.08:25:17.14/onsource/TRACKING 2006.285.08:25:17.14/wx/22.35,1014.7,80 2006.285.08:25:17.22/cable/+6.4752E-03 2006.285.08:25:18.31/va/01,07,usb,yes,33,36 2006.285.08:25:18.31/va/02,06,usb,yes,34,34 2006.285.08:25:18.31/va/03,07,usb,yes,33,35 2006.285.08:25:18.31/va/04,06,usb,yes,34,36 2006.285.08:25:18.31/va/05,03,usb,yes,34,34 2006.285.08:25:18.31/va/06,04,usb,yes,31,30 2006.285.08:25:18.31/va/07,04,usb,yes,31,32 2006.285.08:25:18.31/va/08,03,usb,yes,32,39 2006.285.08:25:18.54/valo/01,524.99,yes,locked 2006.285.08:25:18.54/valo/02,534.99,yes,locked 2006.285.08:25:18.54/valo/03,564.99,yes,locked 2006.285.08:25:18.54/valo/04,624.99,yes,locked 2006.285.08:25:18.54/valo/05,734.99,yes,locked 2006.285.08:25:18.54/valo/06,814.99,yes,locked 2006.285.08:25:18.54/valo/07,864.99,yes,locked 2006.285.08:25:18.54/valo/08,884.99,yes,locked 2006.285.08:25:19.63/vb/01,04,usb,yes,32,29 2006.285.08:25:19.63/vb/02,05,usb,yes,30,30 2006.285.08:25:19.63/vb/03,04,usb,yes,31,34 2006.285.08:25:19.63/vb/04,05,usb,yes,31,30 2006.285.08:25:19.63/vb/05,04,usb,yes,27,30 2006.285.08:25:19.63/vb/06,03,usb,yes,39,35 2006.285.08:25:19.63/vb/07,04,usb,yes,32,32 2006.285.08:25:19.63/vb/08,04,usb,yes,29,33 2006.285.08:25:19.87/vblo/01,629.99,yes,locked 2006.285.08:25:19.87/vblo/02,634.99,yes,locked 2006.285.08:25:19.87/vblo/03,649.99,yes,locked 2006.285.08:25:19.87/vblo/04,679.99,yes,locked 2006.285.08:25:19.87/vblo/05,709.99,yes,locked 2006.285.08:25:19.87/vblo/06,719.99,yes,locked 2006.285.08:25:19.87/vblo/07,734.99,yes,locked 2006.285.08:25:19.87/vblo/08,744.99,yes,locked 2006.285.08:25:20.02/vabw/8 2006.285.08:25:20.17/vbbw/8 2006.285.08:25:20.35/xfe/off,on,12.2 2006.285.08:25:20.72/ifatt/23,28,28,28 2006.285.08:25:21.07/fmout-gps/S +2.79E-07 2006.285.08:25:21.09:!2006.285.08:25:56 2006.285.08:25:56.00:data_valid=off 2006.285.08:25:56.00:"et 2006.285.08:25:56.00:!+3s 2006.285.08:25:59.01:"tape 2006.285.08:25:59.01:postob 2006.285.08:25:59.07/cable/+6.4758E-03 2006.285.08:25:59.07/wx/22.33,1014.8,81 2006.285.08:26:00.07/fmout-gps/S +2.78E-07 2006.285.08:26:00.07:scan_name=285-0827,jd0610,40 2006.285.08:26:00.07:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.285.08:26:01.14#flagr#flagr/antenna,new-source 2006.285.08:26:01.14:checkk5 2006.285.08:26:01.50/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:26:02.09/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:26:02.45/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:26:02.82/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:26:03.27/chk_obsdata//k5ts1/T2850825??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:26:03.65/chk_obsdata//k5ts2/T2850825??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:26:04.06/chk_obsdata//k5ts3/T2850825??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:26:04.42/chk_obsdata//k5ts4/T2850825??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:26:05.27/k5log//k5ts1_log_newline 2006.285.08:26:06.05/k5log//k5ts2_log_newline 2006.285.08:26:07.00/k5log//k5ts3_log_newline 2006.285.08:26:07.71/k5log//k5ts4_log_newline 2006.285.08:26:07.74/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:26:07.74:setupk4=1 2006.285.08:26:07.74$setupk4/echo=on 2006.285.08:26:07.74$setupk4/pcalon 2006.285.08:26:07.74$pcalon/"no phase cal control is implemented here 2006.285.08:26:07.74$setupk4/"tpicd=stop 2006.285.08:26:07.74$setupk4/"rec=synch_on 2006.285.08:26:07.74$setupk4/"rec_mode=128 2006.285.08:26:07.74$setupk4/!* 2006.285.08:26:07.74$setupk4/recpk4 2006.285.08:26:07.74$recpk4/recpatch= 2006.285.08:26:07.74$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:26:07.74$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:26:07.74$setupk4/vck44 2006.285.08:26:07.74$vck44/valo=1,524.99 2006.285.08:26:07.74#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.08:26:07.74#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.08:26:07.74#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:07.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:26:07.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:26:07.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:26:07.74#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:26:07.74#ibcon#first serial, iclass 38, count 0 2006.285.08:26:07.74#ibcon#enter sib2, iclass 38, count 0 2006.285.08:26:07.74#ibcon#flushed, iclass 38, count 0 2006.285.08:26:07.74#ibcon#about to write, iclass 38, count 0 2006.285.08:26:07.74#ibcon#wrote, iclass 38, count 0 2006.285.08:26:07.74#ibcon#about to read 3, iclass 38, count 0 2006.285.08:26:07.76#ibcon#read 3, iclass 38, count 0 2006.285.08:26:07.76#ibcon#about to read 4, iclass 38, count 0 2006.285.08:26:07.76#ibcon#read 4, iclass 38, count 0 2006.285.08:26:07.76#ibcon#about to read 5, iclass 38, count 0 2006.285.08:26:07.76#ibcon#read 5, iclass 38, count 0 2006.285.08:26:07.76#ibcon#about to read 6, iclass 38, count 0 2006.285.08:26:07.76#ibcon#read 6, iclass 38, count 0 2006.285.08:26:07.76#ibcon#end of sib2, iclass 38, count 0 2006.285.08:26:07.76#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:26:07.76#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:26:07.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:26:07.76#ibcon#*before write, iclass 38, count 0 2006.285.08:26:07.76#ibcon#enter sib2, iclass 38, count 0 2006.285.08:26:07.76#ibcon#flushed, iclass 38, count 0 2006.285.08:26:07.76#ibcon#about to write, iclass 38, count 0 2006.285.08:26:07.76#ibcon#wrote, iclass 38, count 0 2006.285.08:26:07.76#ibcon#about to read 3, iclass 38, count 0 2006.285.08:26:07.81#ibcon#read 3, iclass 38, count 0 2006.285.08:26:07.81#ibcon#about to read 4, iclass 38, count 0 2006.285.08:26:07.81#ibcon#read 4, iclass 38, count 0 2006.285.08:26:07.81#ibcon#about to read 5, iclass 38, count 0 2006.285.08:26:07.81#ibcon#read 5, iclass 38, count 0 2006.285.08:26:07.81#ibcon#about to read 6, iclass 38, count 0 2006.285.08:26:07.81#ibcon#read 6, iclass 38, count 0 2006.285.08:26:07.81#ibcon#end of sib2, iclass 38, count 0 2006.285.08:26:07.81#ibcon#*after write, iclass 38, count 0 2006.285.08:26:07.81#ibcon#*before return 0, iclass 38, count 0 2006.285.08:26:07.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:26:07.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:26:07.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:26:07.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:26:07.81$vck44/va=1,7 2006.285.08:26:07.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.08:26:07.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.08:26:07.81#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:07.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:26:07.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:26:07.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:26:07.81#ibcon#enter wrdev, iclass 40, count 2 2006.285.08:26:07.81#ibcon#first serial, iclass 40, count 2 2006.285.08:26:07.81#ibcon#enter sib2, iclass 40, count 2 2006.285.08:26:07.81#ibcon#flushed, iclass 40, count 2 2006.285.08:26:07.81#ibcon#about to write, iclass 40, count 2 2006.285.08:26:07.81#ibcon#wrote, iclass 40, count 2 2006.285.08:26:07.81#ibcon#about to read 3, iclass 40, count 2 2006.285.08:26:07.83#ibcon#read 3, iclass 40, count 2 2006.285.08:26:07.83#ibcon#about to read 4, iclass 40, count 2 2006.285.08:26:07.83#ibcon#read 4, iclass 40, count 2 2006.285.08:26:07.83#ibcon#about to read 5, iclass 40, count 2 2006.285.08:26:07.83#ibcon#read 5, iclass 40, count 2 2006.285.08:26:07.83#ibcon#about to read 6, iclass 40, count 2 2006.285.08:26:07.83#ibcon#read 6, iclass 40, count 2 2006.285.08:26:07.83#ibcon#end of sib2, iclass 40, count 2 2006.285.08:26:07.83#ibcon#*mode == 0, iclass 40, count 2 2006.285.08:26:07.83#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.08:26:07.83#ibcon#[25=AT01-07\r\n] 2006.285.08:26:07.83#ibcon#*before write, iclass 40, count 2 2006.285.08:26:07.83#ibcon#enter sib2, iclass 40, count 2 2006.285.08:26:07.83#ibcon#flushed, iclass 40, count 2 2006.285.08:26:07.83#ibcon#about to write, iclass 40, count 2 2006.285.08:26:07.83#ibcon#wrote, iclass 40, count 2 2006.285.08:26:07.83#ibcon#about to read 3, iclass 40, count 2 2006.285.08:26:07.86#ibcon#read 3, iclass 40, count 2 2006.285.08:26:07.86#ibcon#about to read 4, iclass 40, count 2 2006.285.08:26:07.86#ibcon#read 4, iclass 40, count 2 2006.285.08:26:07.86#ibcon#about to read 5, iclass 40, count 2 2006.285.08:26:07.86#ibcon#read 5, iclass 40, count 2 2006.285.08:26:07.86#ibcon#about to read 6, iclass 40, count 2 2006.285.08:26:07.86#ibcon#read 6, iclass 40, count 2 2006.285.08:26:07.86#ibcon#end of sib2, iclass 40, count 2 2006.285.08:26:07.86#ibcon#*after write, iclass 40, count 2 2006.285.08:26:07.86#ibcon#*before return 0, iclass 40, count 2 2006.285.08:26:07.86#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:26:07.86#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:26:07.86#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.08:26:07.86#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:07.86#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:26:07.98#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:26:07.98#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:26:07.98#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:26:07.98#ibcon#first serial, iclass 40, count 0 2006.285.08:26:07.98#ibcon#enter sib2, iclass 40, count 0 2006.285.08:26:07.98#ibcon#flushed, iclass 40, count 0 2006.285.08:26:07.98#ibcon#about to write, iclass 40, count 0 2006.285.08:26:07.98#ibcon#wrote, iclass 40, count 0 2006.285.08:26:07.98#ibcon#about to read 3, iclass 40, count 0 2006.285.08:26:08.00#ibcon#read 3, iclass 40, count 0 2006.285.08:26:08.00#ibcon#about to read 4, iclass 40, count 0 2006.285.08:26:08.00#ibcon#read 4, iclass 40, count 0 2006.285.08:26:08.00#ibcon#about to read 5, iclass 40, count 0 2006.285.08:26:08.00#ibcon#read 5, iclass 40, count 0 2006.285.08:26:08.00#ibcon#about to read 6, iclass 40, count 0 2006.285.08:26:08.00#ibcon#read 6, iclass 40, count 0 2006.285.08:26:08.00#ibcon#end of sib2, iclass 40, count 0 2006.285.08:26:08.00#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:26:08.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:26:08.00#ibcon#[25=USB\r\n] 2006.285.08:26:08.00#ibcon#*before write, iclass 40, count 0 2006.285.08:26:08.00#ibcon#enter sib2, iclass 40, count 0 2006.285.08:26:08.00#ibcon#flushed, iclass 40, count 0 2006.285.08:26:08.00#ibcon#about to write, iclass 40, count 0 2006.285.08:26:08.00#ibcon#wrote, iclass 40, count 0 2006.285.08:26:08.00#ibcon#about to read 3, iclass 40, count 0 2006.285.08:26:08.03#ibcon#read 3, iclass 40, count 0 2006.285.08:26:08.03#ibcon#about to read 4, iclass 40, count 0 2006.285.08:26:08.03#ibcon#read 4, iclass 40, count 0 2006.285.08:26:08.03#ibcon#about to read 5, iclass 40, count 0 2006.285.08:26:08.03#ibcon#read 5, iclass 40, count 0 2006.285.08:26:08.03#ibcon#about to read 6, iclass 40, count 0 2006.285.08:26:08.03#ibcon#read 6, iclass 40, count 0 2006.285.08:26:08.03#ibcon#end of sib2, iclass 40, count 0 2006.285.08:26:08.03#ibcon#*after write, iclass 40, count 0 2006.285.08:26:08.03#ibcon#*before return 0, iclass 40, count 0 2006.285.08:26:08.03#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:26:08.03#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:26:08.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:26:08.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:26:08.03$vck44/valo=2,534.99 2006.285.08:26:08.03#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.08:26:08.03#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.08:26:08.03#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:08.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:26:08.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:26:08.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:26:08.03#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:26:08.03#ibcon#first serial, iclass 4, count 0 2006.285.08:26:08.03#ibcon#enter sib2, iclass 4, count 0 2006.285.08:26:08.03#ibcon#flushed, iclass 4, count 0 2006.285.08:26:08.03#ibcon#about to write, iclass 4, count 0 2006.285.08:26:08.03#ibcon#wrote, iclass 4, count 0 2006.285.08:26:08.03#ibcon#about to read 3, iclass 4, count 0 2006.285.08:26:08.05#ibcon#read 3, iclass 4, count 0 2006.285.08:26:08.05#ibcon#about to read 4, iclass 4, count 0 2006.285.08:26:08.05#ibcon#read 4, iclass 4, count 0 2006.285.08:26:08.05#ibcon#about to read 5, iclass 4, count 0 2006.285.08:26:08.05#ibcon#read 5, iclass 4, count 0 2006.285.08:26:08.05#ibcon#about to read 6, iclass 4, count 0 2006.285.08:26:08.05#ibcon#read 6, iclass 4, count 0 2006.285.08:26:08.05#ibcon#end of sib2, iclass 4, count 0 2006.285.08:26:08.05#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:26:08.05#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:26:08.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:26:08.05#ibcon#*before write, iclass 4, count 0 2006.285.08:26:08.05#ibcon#enter sib2, iclass 4, count 0 2006.285.08:26:08.05#ibcon#flushed, iclass 4, count 0 2006.285.08:26:08.05#ibcon#about to write, iclass 4, count 0 2006.285.08:26:08.05#ibcon#wrote, iclass 4, count 0 2006.285.08:26:08.05#ibcon#about to read 3, iclass 4, count 0 2006.285.08:26:08.09#ibcon#read 3, iclass 4, count 0 2006.285.08:26:08.09#ibcon#about to read 4, iclass 4, count 0 2006.285.08:26:08.09#ibcon#read 4, iclass 4, count 0 2006.285.08:26:08.09#ibcon#about to read 5, iclass 4, count 0 2006.285.08:26:08.09#ibcon#read 5, iclass 4, count 0 2006.285.08:26:08.09#ibcon#about to read 6, iclass 4, count 0 2006.285.08:26:08.09#ibcon#read 6, iclass 4, count 0 2006.285.08:26:08.09#ibcon#end of sib2, iclass 4, count 0 2006.285.08:26:08.09#ibcon#*after write, iclass 4, count 0 2006.285.08:26:08.09#ibcon#*before return 0, iclass 4, count 0 2006.285.08:26:08.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:26:08.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:26:08.09#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:26:08.09#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:26:08.09$vck44/va=2,6 2006.285.08:26:08.09#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.08:26:08.09#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.08:26:08.09#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:08.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:26:08.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:26:08.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:26:08.15#ibcon#enter wrdev, iclass 6, count 2 2006.285.08:26:08.15#ibcon#first serial, iclass 6, count 2 2006.285.08:26:08.15#ibcon#enter sib2, iclass 6, count 2 2006.285.08:26:08.15#ibcon#flushed, iclass 6, count 2 2006.285.08:26:08.15#ibcon#about to write, iclass 6, count 2 2006.285.08:26:08.15#ibcon#wrote, iclass 6, count 2 2006.285.08:26:08.15#ibcon#about to read 3, iclass 6, count 2 2006.285.08:26:08.17#ibcon#read 3, iclass 6, count 2 2006.285.08:26:08.17#ibcon#about to read 4, iclass 6, count 2 2006.285.08:26:08.17#ibcon#read 4, iclass 6, count 2 2006.285.08:26:08.17#ibcon#about to read 5, iclass 6, count 2 2006.285.08:26:08.17#ibcon#read 5, iclass 6, count 2 2006.285.08:26:08.17#ibcon#about to read 6, iclass 6, count 2 2006.285.08:26:08.17#ibcon#read 6, iclass 6, count 2 2006.285.08:26:08.17#ibcon#end of sib2, iclass 6, count 2 2006.285.08:26:08.17#ibcon#*mode == 0, iclass 6, count 2 2006.285.08:26:08.17#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.08:26:08.17#ibcon#[25=AT02-06\r\n] 2006.285.08:26:08.17#ibcon#*before write, iclass 6, count 2 2006.285.08:26:08.17#ibcon#enter sib2, iclass 6, count 2 2006.285.08:26:08.17#ibcon#flushed, iclass 6, count 2 2006.285.08:26:08.17#ibcon#about to write, iclass 6, count 2 2006.285.08:26:08.17#ibcon#wrote, iclass 6, count 2 2006.285.08:26:08.17#ibcon#about to read 3, iclass 6, count 2 2006.285.08:26:08.20#ibcon#read 3, iclass 6, count 2 2006.285.08:26:08.20#ibcon#about to read 4, iclass 6, count 2 2006.285.08:26:08.20#ibcon#read 4, iclass 6, count 2 2006.285.08:26:08.20#ibcon#about to read 5, iclass 6, count 2 2006.285.08:26:08.20#ibcon#read 5, iclass 6, count 2 2006.285.08:26:08.20#ibcon#about to read 6, iclass 6, count 2 2006.285.08:26:08.20#ibcon#read 6, iclass 6, count 2 2006.285.08:26:08.20#ibcon#end of sib2, iclass 6, count 2 2006.285.08:26:08.20#ibcon#*after write, iclass 6, count 2 2006.285.08:26:08.20#ibcon#*before return 0, iclass 6, count 2 2006.285.08:26:08.20#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:26:08.20#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:26:08.20#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.08:26:08.20#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:08.20#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:26:08.32#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:26:08.32#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:26:08.32#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:26:08.32#ibcon#first serial, iclass 6, count 0 2006.285.08:26:08.32#ibcon#enter sib2, iclass 6, count 0 2006.285.08:26:08.32#ibcon#flushed, iclass 6, count 0 2006.285.08:26:08.32#ibcon#about to write, iclass 6, count 0 2006.285.08:26:08.32#ibcon#wrote, iclass 6, count 0 2006.285.08:26:08.32#ibcon#about to read 3, iclass 6, count 0 2006.285.08:26:08.34#ibcon#read 3, iclass 6, count 0 2006.285.08:26:08.34#ibcon#about to read 4, iclass 6, count 0 2006.285.08:26:08.34#ibcon#read 4, iclass 6, count 0 2006.285.08:26:08.34#ibcon#about to read 5, iclass 6, count 0 2006.285.08:26:08.34#ibcon#read 5, iclass 6, count 0 2006.285.08:26:08.34#ibcon#about to read 6, iclass 6, count 0 2006.285.08:26:08.34#ibcon#read 6, iclass 6, count 0 2006.285.08:26:08.34#ibcon#end of sib2, iclass 6, count 0 2006.285.08:26:08.34#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:26:08.34#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:26:08.34#ibcon#[25=USB\r\n] 2006.285.08:26:08.34#ibcon#*before write, iclass 6, count 0 2006.285.08:26:08.34#ibcon#enter sib2, iclass 6, count 0 2006.285.08:26:08.34#ibcon#flushed, iclass 6, count 0 2006.285.08:26:08.34#ibcon#about to write, iclass 6, count 0 2006.285.08:26:08.34#ibcon#wrote, iclass 6, count 0 2006.285.08:26:08.34#ibcon#about to read 3, iclass 6, count 0 2006.285.08:26:08.37#ibcon#read 3, iclass 6, count 0 2006.285.08:26:08.37#ibcon#about to read 4, iclass 6, count 0 2006.285.08:26:08.37#ibcon#read 4, iclass 6, count 0 2006.285.08:26:08.37#ibcon#about to read 5, iclass 6, count 0 2006.285.08:26:08.37#ibcon#read 5, iclass 6, count 0 2006.285.08:26:08.37#ibcon#about to read 6, iclass 6, count 0 2006.285.08:26:08.37#ibcon#read 6, iclass 6, count 0 2006.285.08:26:08.37#ibcon#end of sib2, iclass 6, count 0 2006.285.08:26:08.37#ibcon#*after write, iclass 6, count 0 2006.285.08:26:08.37#ibcon#*before return 0, iclass 6, count 0 2006.285.08:26:08.37#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:26:08.37#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:26:08.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:26:08.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:26:08.37$vck44/valo=3,564.99 2006.285.08:26:08.37#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.08:26:08.37#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.08:26:08.37#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:08.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:26:08.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:26:08.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:26:08.37#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:26:08.37#ibcon#first serial, iclass 10, count 0 2006.285.08:26:08.37#ibcon#enter sib2, iclass 10, count 0 2006.285.08:26:08.37#ibcon#flushed, iclass 10, count 0 2006.285.08:26:08.37#ibcon#about to write, iclass 10, count 0 2006.285.08:26:08.37#ibcon#wrote, iclass 10, count 0 2006.285.08:26:08.37#ibcon#about to read 3, iclass 10, count 0 2006.285.08:26:08.39#ibcon#read 3, iclass 10, count 0 2006.285.08:26:08.39#ibcon#about to read 4, iclass 10, count 0 2006.285.08:26:08.39#ibcon#read 4, iclass 10, count 0 2006.285.08:26:08.39#ibcon#about to read 5, iclass 10, count 0 2006.285.08:26:08.39#ibcon#read 5, iclass 10, count 0 2006.285.08:26:08.39#ibcon#about to read 6, iclass 10, count 0 2006.285.08:26:08.39#ibcon#read 6, iclass 10, count 0 2006.285.08:26:08.39#ibcon#end of sib2, iclass 10, count 0 2006.285.08:26:08.39#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:26:08.39#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:26:08.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:26:08.39#ibcon#*before write, iclass 10, count 0 2006.285.08:26:08.39#ibcon#enter sib2, iclass 10, count 0 2006.285.08:26:08.39#ibcon#flushed, iclass 10, count 0 2006.285.08:26:08.39#ibcon#about to write, iclass 10, count 0 2006.285.08:26:08.39#ibcon#wrote, iclass 10, count 0 2006.285.08:26:08.39#ibcon#about to read 3, iclass 10, count 0 2006.285.08:26:08.43#ibcon#read 3, iclass 10, count 0 2006.285.08:26:08.43#ibcon#about to read 4, iclass 10, count 0 2006.285.08:26:08.43#ibcon#read 4, iclass 10, count 0 2006.285.08:26:08.43#ibcon#about to read 5, iclass 10, count 0 2006.285.08:26:08.43#ibcon#read 5, iclass 10, count 0 2006.285.08:26:08.43#ibcon#about to read 6, iclass 10, count 0 2006.285.08:26:08.43#ibcon#read 6, iclass 10, count 0 2006.285.08:26:08.43#ibcon#end of sib2, iclass 10, count 0 2006.285.08:26:08.43#ibcon#*after write, iclass 10, count 0 2006.285.08:26:08.43#ibcon#*before return 0, iclass 10, count 0 2006.285.08:26:08.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:26:08.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:26:08.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:26:08.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:26:08.43$vck44/va=3,7 2006.285.08:26:08.43#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.08:26:08.43#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.08:26:08.43#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:08.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:26:08.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:26:08.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:26:08.49#ibcon#enter wrdev, iclass 12, count 2 2006.285.08:26:08.49#ibcon#first serial, iclass 12, count 2 2006.285.08:26:08.49#ibcon#enter sib2, iclass 12, count 2 2006.285.08:26:08.49#ibcon#flushed, iclass 12, count 2 2006.285.08:26:08.49#ibcon#about to write, iclass 12, count 2 2006.285.08:26:08.49#ibcon#wrote, iclass 12, count 2 2006.285.08:26:08.49#ibcon#about to read 3, iclass 12, count 2 2006.285.08:26:08.51#ibcon#read 3, iclass 12, count 2 2006.285.08:26:08.51#ibcon#about to read 4, iclass 12, count 2 2006.285.08:26:08.51#ibcon#read 4, iclass 12, count 2 2006.285.08:26:08.51#ibcon#about to read 5, iclass 12, count 2 2006.285.08:26:08.51#ibcon#read 5, iclass 12, count 2 2006.285.08:26:08.51#ibcon#about to read 6, iclass 12, count 2 2006.285.08:26:08.51#ibcon#read 6, iclass 12, count 2 2006.285.08:26:08.51#ibcon#end of sib2, iclass 12, count 2 2006.285.08:26:08.51#ibcon#*mode == 0, iclass 12, count 2 2006.285.08:26:08.51#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.08:26:08.51#ibcon#[25=AT03-07\r\n] 2006.285.08:26:08.51#ibcon#*before write, iclass 12, count 2 2006.285.08:26:08.51#ibcon#enter sib2, iclass 12, count 2 2006.285.08:26:08.51#ibcon#flushed, iclass 12, count 2 2006.285.08:26:08.51#ibcon#about to write, iclass 12, count 2 2006.285.08:26:08.51#ibcon#wrote, iclass 12, count 2 2006.285.08:26:08.51#ibcon#about to read 3, iclass 12, count 2 2006.285.08:26:08.54#ibcon#read 3, iclass 12, count 2 2006.285.08:26:08.54#ibcon#about to read 4, iclass 12, count 2 2006.285.08:26:08.54#ibcon#read 4, iclass 12, count 2 2006.285.08:26:08.54#ibcon#about to read 5, iclass 12, count 2 2006.285.08:26:08.54#ibcon#read 5, iclass 12, count 2 2006.285.08:26:08.54#ibcon#about to read 6, iclass 12, count 2 2006.285.08:26:08.54#ibcon#read 6, iclass 12, count 2 2006.285.08:26:08.54#ibcon#end of sib2, iclass 12, count 2 2006.285.08:26:08.54#ibcon#*after write, iclass 12, count 2 2006.285.08:26:08.54#ibcon#*before return 0, iclass 12, count 2 2006.285.08:26:08.54#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:26:08.54#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:26:08.54#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.08:26:08.54#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:08.54#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:26:08.66#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:26:08.66#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:26:08.66#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:26:08.66#ibcon#first serial, iclass 12, count 0 2006.285.08:26:08.66#ibcon#enter sib2, iclass 12, count 0 2006.285.08:26:08.66#ibcon#flushed, iclass 12, count 0 2006.285.08:26:08.66#ibcon#about to write, iclass 12, count 0 2006.285.08:26:08.66#ibcon#wrote, iclass 12, count 0 2006.285.08:26:08.66#ibcon#about to read 3, iclass 12, count 0 2006.285.08:26:08.68#ibcon#read 3, iclass 12, count 0 2006.285.08:26:08.68#ibcon#about to read 4, iclass 12, count 0 2006.285.08:26:08.68#ibcon#read 4, iclass 12, count 0 2006.285.08:26:08.68#ibcon#about to read 5, iclass 12, count 0 2006.285.08:26:08.68#ibcon#read 5, iclass 12, count 0 2006.285.08:26:08.68#ibcon#about to read 6, iclass 12, count 0 2006.285.08:26:08.68#ibcon#read 6, iclass 12, count 0 2006.285.08:26:08.68#ibcon#end of sib2, iclass 12, count 0 2006.285.08:26:08.68#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:26:08.68#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:26:08.68#ibcon#[25=USB\r\n] 2006.285.08:26:08.68#ibcon#*before write, iclass 12, count 0 2006.285.08:26:08.68#ibcon#enter sib2, iclass 12, count 0 2006.285.08:26:08.68#ibcon#flushed, iclass 12, count 0 2006.285.08:26:08.68#ibcon#about to write, iclass 12, count 0 2006.285.08:26:08.68#ibcon#wrote, iclass 12, count 0 2006.285.08:26:08.68#ibcon#about to read 3, iclass 12, count 0 2006.285.08:26:08.71#ibcon#read 3, iclass 12, count 0 2006.285.08:26:08.71#ibcon#about to read 4, iclass 12, count 0 2006.285.08:26:08.71#ibcon#read 4, iclass 12, count 0 2006.285.08:26:08.71#ibcon#about to read 5, iclass 12, count 0 2006.285.08:26:08.71#ibcon#read 5, iclass 12, count 0 2006.285.08:26:08.71#ibcon#about to read 6, iclass 12, count 0 2006.285.08:26:08.71#ibcon#read 6, iclass 12, count 0 2006.285.08:26:08.71#ibcon#end of sib2, iclass 12, count 0 2006.285.08:26:08.71#ibcon#*after write, iclass 12, count 0 2006.285.08:26:08.71#ibcon#*before return 0, iclass 12, count 0 2006.285.08:26:08.71#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:26:08.71#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:26:08.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:26:08.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:26:08.71$vck44/valo=4,624.99 2006.285.08:26:08.71#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.08:26:08.71#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.08:26:08.71#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:08.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:26:08.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:26:08.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:26:08.71#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:26:08.71#ibcon#first serial, iclass 14, count 0 2006.285.08:26:08.71#ibcon#enter sib2, iclass 14, count 0 2006.285.08:26:08.71#ibcon#flushed, iclass 14, count 0 2006.285.08:26:08.71#ibcon#about to write, iclass 14, count 0 2006.285.08:26:08.71#ibcon#wrote, iclass 14, count 0 2006.285.08:26:08.71#ibcon#about to read 3, iclass 14, count 0 2006.285.08:26:08.73#ibcon#read 3, iclass 14, count 0 2006.285.08:26:08.73#ibcon#about to read 4, iclass 14, count 0 2006.285.08:26:08.73#ibcon#read 4, iclass 14, count 0 2006.285.08:26:08.73#ibcon#about to read 5, iclass 14, count 0 2006.285.08:26:08.73#ibcon#read 5, iclass 14, count 0 2006.285.08:26:08.73#ibcon#about to read 6, iclass 14, count 0 2006.285.08:26:08.73#ibcon#read 6, iclass 14, count 0 2006.285.08:26:08.73#ibcon#end of sib2, iclass 14, count 0 2006.285.08:26:08.73#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:26:08.73#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:26:08.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:26:08.73#ibcon#*before write, iclass 14, count 0 2006.285.08:26:08.73#ibcon#enter sib2, iclass 14, count 0 2006.285.08:26:08.73#ibcon#flushed, iclass 14, count 0 2006.285.08:26:08.73#ibcon#about to write, iclass 14, count 0 2006.285.08:26:08.73#ibcon#wrote, iclass 14, count 0 2006.285.08:26:08.73#ibcon#about to read 3, iclass 14, count 0 2006.285.08:26:08.77#ibcon#read 3, iclass 14, count 0 2006.285.08:26:08.77#ibcon#about to read 4, iclass 14, count 0 2006.285.08:26:08.77#ibcon#read 4, iclass 14, count 0 2006.285.08:26:08.77#ibcon#about to read 5, iclass 14, count 0 2006.285.08:26:08.77#ibcon#read 5, iclass 14, count 0 2006.285.08:26:08.77#ibcon#about to read 6, iclass 14, count 0 2006.285.08:26:08.77#ibcon#read 6, iclass 14, count 0 2006.285.08:26:08.77#ibcon#end of sib2, iclass 14, count 0 2006.285.08:26:08.77#ibcon#*after write, iclass 14, count 0 2006.285.08:26:08.77#ibcon#*before return 0, iclass 14, count 0 2006.285.08:26:08.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:26:08.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:26:08.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:26:08.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:26:08.77$vck44/va=4,6 2006.285.08:26:08.77#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.08:26:08.77#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.08:26:08.77#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:08.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:26:08.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:26:08.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:26:08.83#ibcon#enter wrdev, iclass 16, count 2 2006.285.08:26:08.83#ibcon#first serial, iclass 16, count 2 2006.285.08:26:08.83#ibcon#enter sib2, iclass 16, count 2 2006.285.08:26:08.83#ibcon#flushed, iclass 16, count 2 2006.285.08:26:08.83#ibcon#about to write, iclass 16, count 2 2006.285.08:26:08.83#ibcon#wrote, iclass 16, count 2 2006.285.08:26:08.83#ibcon#about to read 3, iclass 16, count 2 2006.285.08:26:08.85#ibcon#read 3, iclass 16, count 2 2006.285.08:26:08.85#ibcon#about to read 4, iclass 16, count 2 2006.285.08:26:08.85#ibcon#read 4, iclass 16, count 2 2006.285.08:26:08.85#ibcon#about to read 5, iclass 16, count 2 2006.285.08:26:08.85#ibcon#read 5, iclass 16, count 2 2006.285.08:26:08.85#ibcon#about to read 6, iclass 16, count 2 2006.285.08:26:08.85#ibcon#read 6, iclass 16, count 2 2006.285.08:26:08.85#ibcon#end of sib2, iclass 16, count 2 2006.285.08:26:08.85#ibcon#*mode == 0, iclass 16, count 2 2006.285.08:26:08.85#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.08:26:08.85#ibcon#[25=AT04-06\r\n] 2006.285.08:26:08.85#ibcon#*before write, iclass 16, count 2 2006.285.08:26:08.85#ibcon#enter sib2, iclass 16, count 2 2006.285.08:26:08.85#ibcon#flushed, iclass 16, count 2 2006.285.08:26:08.85#ibcon#about to write, iclass 16, count 2 2006.285.08:26:08.85#ibcon#wrote, iclass 16, count 2 2006.285.08:26:08.85#ibcon#about to read 3, iclass 16, count 2 2006.285.08:26:08.88#ibcon#read 3, iclass 16, count 2 2006.285.08:26:08.88#ibcon#about to read 4, iclass 16, count 2 2006.285.08:26:08.88#ibcon#read 4, iclass 16, count 2 2006.285.08:26:08.88#ibcon#about to read 5, iclass 16, count 2 2006.285.08:26:08.88#ibcon#read 5, iclass 16, count 2 2006.285.08:26:08.88#ibcon#about to read 6, iclass 16, count 2 2006.285.08:26:08.88#ibcon#read 6, iclass 16, count 2 2006.285.08:26:08.88#ibcon#end of sib2, iclass 16, count 2 2006.285.08:26:08.88#ibcon#*after write, iclass 16, count 2 2006.285.08:26:08.88#ibcon#*before return 0, iclass 16, count 2 2006.285.08:26:08.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:26:08.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:26:08.88#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.08:26:08.88#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:08.88#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:26:09.00#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:26:09.00#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:26:09.00#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:26:09.00#ibcon#first serial, iclass 16, count 0 2006.285.08:26:09.00#ibcon#enter sib2, iclass 16, count 0 2006.285.08:26:09.00#ibcon#flushed, iclass 16, count 0 2006.285.08:26:09.00#ibcon#about to write, iclass 16, count 0 2006.285.08:26:09.00#ibcon#wrote, iclass 16, count 0 2006.285.08:26:09.00#ibcon#about to read 3, iclass 16, count 0 2006.285.08:26:09.02#ibcon#read 3, iclass 16, count 0 2006.285.08:26:09.02#ibcon#about to read 4, iclass 16, count 0 2006.285.08:26:09.02#ibcon#read 4, iclass 16, count 0 2006.285.08:26:09.02#ibcon#about to read 5, iclass 16, count 0 2006.285.08:26:09.02#ibcon#read 5, iclass 16, count 0 2006.285.08:26:09.02#ibcon#about to read 6, iclass 16, count 0 2006.285.08:26:09.02#ibcon#read 6, iclass 16, count 0 2006.285.08:26:09.02#ibcon#end of sib2, iclass 16, count 0 2006.285.08:26:09.02#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:26:09.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:26:09.02#ibcon#[25=USB\r\n] 2006.285.08:26:09.02#ibcon#*before write, iclass 16, count 0 2006.285.08:26:09.02#ibcon#enter sib2, iclass 16, count 0 2006.285.08:26:09.02#ibcon#flushed, iclass 16, count 0 2006.285.08:26:09.02#ibcon#about to write, iclass 16, count 0 2006.285.08:26:09.02#ibcon#wrote, iclass 16, count 0 2006.285.08:26:09.02#ibcon#about to read 3, iclass 16, count 0 2006.285.08:26:09.05#ibcon#read 3, iclass 16, count 0 2006.285.08:26:09.05#ibcon#about to read 4, iclass 16, count 0 2006.285.08:26:09.05#ibcon#read 4, iclass 16, count 0 2006.285.08:26:09.05#ibcon#about to read 5, iclass 16, count 0 2006.285.08:26:09.05#ibcon#read 5, iclass 16, count 0 2006.285.08:26:09.05#ibcon#about to read 6, iclass 16, count 0 2006.285.08:26:09.05#ibcon#read 6, iclass 16, count 0 2006.285.08:26:09.05#ibcon#end of sib2, iclass 16, count 0 2006.285.08:26:09.05#ibcon#*after write, iclass 16, count 0 2006.285.08:26:09.05#ibcon#*before return 0, iclass 16, count 0 2006.285.08:26:09.05#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:26:09.05#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:26:09.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:26:09.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:26:09.05$vck44/valo=5,734.99 2006.285.08:26:09.05#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.08:26:09.05#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.08:26:09.05#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:09.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:26:09.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:26:09.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:26:09.05#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:26:09.05#ibcon#first serial, iclass 18, count 0 2006.285.08:26:09.05#ibcon#enter sib2, iclass 18, count 0 2006.285.08:26:09.05#ibcon#flushed, iclass 18, count 0 2006.285.08:26:09.05#ibcon#about to write, iclass 18, count 0 2006.285.08:26:09.05#ibcon#wrote, iclass 18, count 0 2006.285.08:26:09.05#ibcon#about to read 3, iclass 18, count 0 2006.285.08:26:09.07#ibcon#read 3, iclass 18, count 0 2006.285.08:26:09.07#ibcon#about to read 4, iclass 18, count 0 2006.285.08:26:09.07#ibcon#read 4, iclass 18, count 0 2006.285.08:26:09.07#ibcon#about to read 5, iclass 18, count 0 2006.285.08:26:09.07#ibcon#read 5, iclass 18, count 0 2006.285.08:26:09.07#ibcon#about to read 6, iclass 18, count 0 2006.285.08:26:09.07#ibcon#read 6, iclass 18, count 0 2006.285.08:26:09.07#ibcon#end of sib2, iclass 18, count 0 2006.285.08:26:09.07#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:26:09.07#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:26:09.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:26:09.07#ibcon#*before write, iclass 18, count 0 2006.285.08:26:09.07#ibcon#enter sib2, iclass 18, count 0 2006.285.08:26:09.07#ibcon#flushed, iclass 18, count 0 2006.285.08:26:09.07#ibcon#about to write, iclass 18, count 0 2006.285.08:26:09.07#ibcon#wrote, iclass 18, count 0 2006.285.08:26:09.07#ibcon#about to read 3, iclass 18, count 0 2006.285.08:26:09.11#ibcon#read 3, iclass 18, count 0 2006.285.08:26:09.11#ibcon#about to read 4, iclass 18, count 0 2006.285.08:26:09.11#ibcon#read 4, iclass 18, count 0 2006.285.08:26:09.11#ibcon#about to read 5, iclass 18, count 0 2006.285.08:26:09.11#ibcon#read 5, iclass 18, count 0 2006.285.08:26:09.11#ibcon#about to read 6, iclass 18, count 0 2006.285.08:26:09.11#ibcon#read 6, iclass 18, count 0 2006.285.08:26:09.11#ibcon#end of sib2, iclass 18, count 0 2006.285.08:26:09.11#ibcon#*after write, iclass 18, count 0 2006.285.08:26:09.11#ibcon#*before return 0, iclass 18, count 0 2006.285.08:26:09.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:26:09.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:26:09.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:26:09.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:26:09.11$vck44/va=5,3 2006.285.08:26:09.11#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.08:26:09.11#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.08:26:09.11#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:09.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:26:09.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:26:09.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:26:09.17#ibcon#enter wrdev, iclass 20, count 2 2006.285.08:26:09.17#ibcon#first serial, iclass 20, count 2 2006.285.08:26:09.17#ibcon#enter sib2, iclass 20, count 2 2006.285.08:26:09.17#ibcon#flushed, iclass 20, count 2 2006.285.08:26:09.17#ibcon#about to write, iclass 20, count 2 2006.285.08:26:09.17#ibcon#wrote, iclass 20, count 2 2006.285.08:26:09.17#ibcon#about to read 3, iclass 20, count 2 2006.285.08:26:09.19#ibcon#read 3, iclass 20, count 2 2006.285.08:26:09.19#ibcon#about to read 4, iclass 20, count 2 2006.285.08:26:09.19#ibcon#read 4, iclass 20, count 2 2006.285.08:26:09.19#ibcon#about to read 5, iclass 20, count 2 2006.285.08:26:09.19#ibcon#read 5, iclass 20, count 2 2006.285.08:26:09.19#ibcon#about to read 6, iclass 20, count 2 2006.285.08:26:09.19#ibcon#read 6, iclass 20, count 2 2006.285.08:26:09.19#ibcon#end of sib2, iclass 20, count 2 2006.285.08:26:09.19#ibcon#*mode == 0, iclass 20, count 2 2006.285.08:26:09.19#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.08:26:09.19#ibcon#[25=AT05-03\r\n] 2006.285.08:26:09.19#ibcon#*before write, iclass 20, count 2 2006.285.08:26:09.19#ibcon#enter sib2, iclass 20, count 2 2006.285.08:26:09.19#ibcon#flushed, iclass 20, count 2 2006.285.08:26:09.19#ibcon#about to write, iclass 20, count 2 2006.285.08:26:09.19#ibcon#wrote, iclass 20, count 2 2006.285.08:26:09.19#ibcon#about to read 3, iclass 20, count 2 2006.285.08:26:09.22#ibcon#read 3, iclass 20, count 2 2006.285.08:26:09.22#ibcon#about to read 4, iclass 20, count 2 2006.285.08:26:09.22#ibcon#read 4, iclass 20, count 2 2006.285.08:26:09.22#ibcon#about to read 5, iclass 20, count 2 2006.285.08:26:09.22#ibcon#read 5, iclass 20, count 2 2006.285.08:26:09.22#ibcon#about to read 6, iclass 20, count 2 2006.285.08:26:09.22#ibcon#read 6, iclass 20, count 2 2006.285.08:26:09.22#ibcon#end of sib2, iclass 20, count 2 2006.285.08:26:09.22#ibcon#*after write, iclass 20, count 2 2006.285.08:26:09.22#ibcon#*before return 0, iclass 20, count 2 2006.285.08:26:09.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:26:09.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:26:09.22#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.08:26:09.22#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:09.22#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:26:09.34#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:26:09.34#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:26:09.34#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:26:09.34#ibcon#first serial, iclass 20, count 0 2006.285.08:26:09.34#ibcon#enter sib2, iclass 20, count 0 2006.285.08:26:09.34#ibcon#flushed, iclass 20, count 0 2006.285.08:26:09.34#ibcon#about to write, iclass 20, count 0 2006.285.08:26:09.34#ibcon#wrote, iclass 20, count 0 2006.285.08:26:09.34#ibcon#about to read 3, iclass 20, count 0 2006.285.08:26:09.36#ibcon#read 3, iclass 20, count 0 2006.285.08:26:09.36#ibcon#about to read 4, iclass 20, count 0 2006.285.08:26:09.36#ibcon#read 4, iclass 20, count 0 2006.285.08:26:09.36#ibcon#about to read 5, iclass 20, count 0 2006.285.08:26:09.36#ibcon#read 5, iclass 20, count 0 2006.285.08:26:09.36#ibcon#about to read 6, iclass 20, count 0 2006.285.08:26:09.36#ibcon#read 6, iclass 20, count 0 2006.285.08:26:09.36#ibcon#end of sib2, iclass 20, count 0 2006.285.08:26:09.36#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:26:09.36#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:26:09.36#ibcon#[25=USB\r\n] 2006.285.08:26:09.36#ibcon#*before write, iclass 20, count 0 2006.285.08:26:09.36#ibcon#enter sib2, iclass 20, count 0 2006.285.08:26:09.36#ibcon#flushed, iclass 20, count 0 2006.285.08:26:09.36#ibcon#about to write, iclass 20, count 0 2006.285.08:26:09.36#ibcon#wrote, iclass 20, count 0 2006.285.08:26:09.36#ibcon#about to read 3, iclass 20, count 0 2006.285.08:26:09.39#ibcon#read 3, iclass 20, count 0 2006.285.08:26:09.39#ibcon#about to read 4, iclass 20, count 0 2006.285.08:26:09.39#ibcon#read 4, iclass 20, count 0 2006.285.08:26:09.39#ibcon#about to read 5, iclass 20, count 0 2006.285.08:26:09.39#ibcon#read 5, iclass 20, count 0 2006.285.08:26:09.39#ibcon#about to read 6, iclass 20, count 0 2006.285.08:26:09.39#ibcon#read 6, iclass 20, count 0 2006.285.08:26:09.39#ibcon#end of sib2, iclass 20, count 0 2006.285.08:26:09.39#ibcon#*after write, iclass 20, count 0 2006.285.08:26:09.39#ibcon#*before return 0, iclass 20, count 0 2006.285.08:26:09.39#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:26:09.39#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:26:09.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:26:09.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:26:09.39$vck44/valo=6,814.99 2006.285.08:26:09.39#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.08:26:09.39#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.08:26:09.39#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:09.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:26:09.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:26:09.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:26:09.39#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:26:09.39#ibcon#first serial, iclass 22, count 0 2006.285.08:26:09.39#ibcon#enter sib2, iclass 22, count 0 2006.285.08:26:09.39#ibcon#flushed, iclass 22, count 0 2006.285.08:26:09.39#ibcon#about to write, iclass 22, count 0 2006.285.08:26:09.39#ibcon#wrote, iclass 22, count 0 2006.285.08:26:09.39#ibcon#about to read 3, iclass 22, count 0 2006.285.08:26:09.41#ibcon#read 3, iclass 22, count 0 2006.285.08:26:09.41#ibcon#about to read 4, iclass 22, count 0 2006.285.08:26:09.41#ibcon#read 4, iclass 22, count 0 2006.285.08:26:09.41#ibcon#about to read 5, iclass 22, count 0 2006.285.08:26:09.41#ibcon#read 5, iclass 22, count 0 2006.285.08:26:09.41#ibcon#about to read 6, iclass 22, count 0 2006.285.08:26:09.41#ibcon#read 6, iclass 22, count 0 2006.285.08:26:09.41#ibcon#end of sib2, iclass 22, count 0 2006.285.08:26:09.41#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:26:09.41#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:26:09.41#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:26:09.41#ibcon#*before write, iclass 22, count 0 2006.285.08:26:09.41#ibcon#enter sib2, iclass 22, count 0 2006.285.08:26:09.41#ibcon#flushed, iclass 22, count 0 2006.285.08:26:09.41#ibcon#about to write, iclass 22, count 0 2006.285.08:26:09.41#ibcon#wrote, iclass 22, count 0 2006.285.08:26:09.41#ibcon#about to read 3, iclass 22, count 0 2006.285.08:26:09.45#ibcon#read 3, iclass 22, count 0 2006.285.08:26:09.45#ibcon#about to read 4, iclass 22, count 0 2006.285.08:26:09.45#ibcon#read 4, iclass 22, count 0 2006.285.08:26:09.45#ibcon#about to read 5, iclass 22, count 0 2006.285.08:26:09.45#ibcon#read 5, iclass 22, count 0 2006.285.08:26:09.45#ibcon#about to read 6, iclass 22, count 0 2006.285.08:26:09.45#ibcon#read 6, iclass 22, count 0 2006.285.08:26:09.45#ibcon#end of sib2, iclass 22, count 0 2006.285.08:26:09.45#ibcon#*after write, iclass 22, count 0 2006.285.08:26:09.45#ibcon#*before return 0, iclass 22, count 0 2006.285.08:26:09.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:26:09.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:26:09.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:26:09.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:26:09.45$vck44/va=6,4 2006.285.08:26:09.45#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.08:26:09.45#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.08:26:09.45#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:09.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:26:09.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:26:09.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:26:09.51#ibcon#enter wrdev, iclass 24, count 2 2006.285.08:26:09.51#ibcon#first serial, iclass 24, count 2 2006.285.08:26:09.51#ibcon#enter sib2, iclass 24, count 2 2006.285.08:26:09.51#ibcon#flushed, iclass 24, count 2 2006.285.08:26:09.51#ibcon#about to write, iclass 24, count 2 2006.285.08:26:09.51#ibcon#wrote, iclass 24, count 2 2006.285.08:26:09.51#ibcon#about to read 3, iclass 24, count 2 2006.285.08:26:09.53#ibcon#read 3, iclass 24, count 2 2006.285.08:26:09.53#ibcon#about to read 4, iclass 24, count 2 2006.285.08:26:09.53#ibcon#read 4, iclass 24, count 2 2006.285.08:26:09.53#ibcon#about to read 5, iclass 24, count 2 2006.285.08:26:09.53#ibcon#read 5, iclass 24, count 2 2006.285.08:26:09.53#ibcon#about to read 6, iclass 24, count 2 2006.285.08:26:09.53#ibcon#read 6, iclass 24, count 2 2006.285.08:26:09.53#ibcon#end of sib2, iclass 24, count 2 2006.285.08:26:09.53#ibcon#*mode == 0, iclass 24, count 2 2006.285.08:26:09.53#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.08:26:09.53#ibcon#[25=AT06-04\r\n] 2006.285.08:26:09.53#ibcon#*before write, iclass 24, count 2 2006.285.08:26:09.53#ibcon#enter sib2, iclass 24, count 2 2006.285.08:26:09.53#ibcon#flushed, iclass 24, count 2 2006.285.08:26:09.53#ibcon#about to write, iclass 24, count 2 2006.285.08:26:09.53#ibcon#wrote, iclass 24, count 2 2006.285.08:26:09.53#ibcon#about to read 3, iclass 24, count 2 2006.285.08:26:09.56#ibcon#read 3, iclass 24, count 2 2006.285.08:26:09.56#ibcon#about to read 4, iclass 24, count 2 2006.285.08:26:09.56#ibcon#read 4, iclass 24, count 2 2006.285.08:26:09.56#ibcon#about to read 5, iclass 24, count 2 2006.285.08:26:09.56#ibcon#read 5, iclass 24, count 2 2006.285.08:26:09.56#ibcon#about to read 6, iclass 24, count 2 2006.285.08:26:09.56#ibcon#read 6, iclass 24, count 2 2006.285.08:26:09.56#ibcon#end of sib2, iclass 24, count 2 2006.285.08:26:09.56#ibcon#*after write, iclass 24, count 2 2006.285.08:26:09.56#ibcon#*before return 0, iclass 24, count 2 2006.285.08:26:09.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:26:09.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:26:09.56#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.08:26:09.56#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:09.56#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:26:09.68#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:26:09.68#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:26:09.68#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:26:09.68#ibcon#first serial, iclass 24, count 0 2006.285.08:26:09.68#ibcon#enter sib2, iclass 24, count 0 2006.285.08:26:09.68#ibcon#flushed, iclass 24, count 0 2006.285.08:26:09.68#ibcon#about to write, iclass 24, count 0 2006.285.08:26:09.68#ibcon#wrote, iclass 24, count 0 2006.285.08:26:09.68#ibcon#about to read 3, iclass 24, count 0 2006.285.08:26:09.70#ibcon#read 3, iclass 24, count 0 2006.285.08:26:09.70#ibcon#about to read 4, iclass 24, count 0 2006.285.08:26:09.70#ibcon#read 4, iclass 24, count 0 2006.285.08:26:09.70#ibcon#about to read 5, iclass 24, count 0 2006.285.08:26:09.70#ibcon#read 5, iclass 24, count 0 2006.285.08:26:09.70#ibcon#about to read 6, iclass 24, count 0 2006.285.08:26:09.70#ibcon#read 6, iclass 24, count 0 2006.285.08:26:09.70#ibcon#end of sib2, iclass 24, count 0 2006.285.08:26:09.70#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:26:09.70#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:26:09.70#ibcon#[25=USB\r\n] 2006.285.08:26:09.70#ibcon#*before write, iclass 24, count 0 2006.285.08:26:09.70#ibcon#enter sib2, iclass 24, count 0 2006.285.08:26:09.70#ibcon#flushed, iclass 24, count 0 2006.285.08:26:09.70#ibcon#about to write, iclass 24, count 0 2006.285.08:26:09.70#ibcon#wrote, iclass 24, count 0 2006.285.08:26:09.70#ibcon#about to read 3, iclass 24, count 0 2006.285.08:26:09.73#ibcon#read 3, iclass 24, count 0 2006.285.08:26:09.73#ibcon#about to read 4, iclass 24, count 0 2006.285.08:26:09.73#ibcon#read 4, iclass 24, count 0 2006.285.08:26:09.73#ibcon#about to read 5, iclass 24, count 0 2006.285.08:26:09.73#ibcon#read 5, iclass 24, count 0 2006.285.08:26:09.73#ibcon#about to read 6, iclass 24, count 0 2006.285.08:26:09.73#ibcon#read 6, iclass 24, count 0 2006.285.08:26:09.73#ibcon#end of sib2, iclass 24, count 0 2006.285.08:26:09.73#ibcon#*after write, iclass 24, count 0 2006.285.08:26:09.73#ibcon#*before return 0, iclass 24, count 0 2006.285.08:26:09.73#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:26:09.73#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:26:09.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:26:09.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:26:09.73$vck44/valo=7,864.99 2006.285.08:26:09.73#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.08:26:09.73#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.08:26:09.73#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:09.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:26:09.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:26:09.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:26:09.73#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:26:09.73#ibcon#first serial, iclass 26, count 0 2006.285.08:26:09.73#ibcon#enter sib2, iclass 26, count 0 2006.285.08:26:09.73#ibcon#flushed, iclass 26, count 0 2006.285.08:26:09.73#ibcon#about to write, iclass 26, count 0 2006.285.08:26:09.73#ibcon#wrote, iclass 26, count 0 2006.285.08:26:09.73#ibcon#about to read 3, iclass 26, count 0 2006.285.08:26:09.75#ibcon#read 3, iclass 26, count 0 2006.285.08:26:09.75#ibcon#about to read 4, iclass 26, count 0 2006.285.08:26:09.75#ibcon#read 4, iclass 26, count 0 2006.285.08:26:09.75#ibcon#about to read 5, iclass 26, count 0 2006.285.08:26:09.75#ibcon#read 5, iclass 26, count 0 2006.285.08:26:09.75#ibcon#about to read 6, iclass 26, count 0 2006.285.08:26:09.75#ibcon#read 6, iclass 26, count 0 2006.285.08:26:09.75#ibcon#end of sib2, iclass 26, count 0 2006.285.08:26:09.75#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:26:09.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:26:09.75#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:26:09.75#ibcon#*before write, iclass 26, count 0 2006.285.08:26:09.75#ibcon#enter sib2, iclass 26, count 0 2006.285.08:26:09.75#ibcon#flushed, iclass 26, count 0 2006.285.08:26:09.75#ibcon#about to write, iclass 26, count 0 2006.285.08:26:09.75#ibcon#wrote, iclass 26, count 0 2006.285.08:26:09.75#ibcon#about to read 3, iclass 26, count 0 2006.285.08:26:09.79#ibcon#read 3, iclass 26, count 0 2006.285.08:26:09.79#ibcon#about to read 4, iclass 26, count 0 2006.285.08:26:09.79#ibcon#read 4, iclass 26, count 0 2006.285.08:26:09.79#ibcon#about to read 5, iclass 26, count 0 2006.285.08:26:09.79#ibcon#read 5, iclass 26, count 0 2006.285.08:26:09.79#ibcon#about to read 6, iclass 26, count 0 2006.285.08:26:09.79#ibcon#read 6, iclass 26, count 0 2006.285.08:26:09.79#ibcon#end of sib2, iclass 26, count 0 2006.285.08:26:09.79#ibcon#*after write, iclass 26, count 0 2006.285.08:26:09.79#ibcon#*before return 0, iclass 26, count 0 2006.285.08:26:09.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:26:09.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:26:09.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:26:09.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:26:09.79$vck44/va=7,4 2006.285.08:26:09.79#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.08:26:09.79#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.08:26:09.79#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:09.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:26:09.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:26:09.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:26:09.85#ibcon#enter wrdev, iclass 28, count 2 2006.285.08:26:09.85#ibcon#first serial, iclass 28, count 2 2006.285.08:26:09.85#ibcon#enter sib2, iclass 28, count 2 2006.285.08:26:09.85#ibcon#flushed, iclass 28, count 2 2006.285.08:26:09.85#ibcon#about to write, iclass 28, count 2 2006.285.08:26:09.85#ibcon#wrote, iclass 28, count 2 2006.285.08:26:09.85#ibcon#about to read 3, iclass 28, count 2 2006.285.08:26:09.87#ibcon#read 3, iclass 28, count 2 2006.285.08:26:09.87#ibcon#about to read 4, iclass 28, count 2 2006.285.08:26:09.87#ibcon#read 4, iclass 28, count 2 2006.285.08:26:09.87#ibcon#about to read 5, iclass 28, count 2 2006.285.08:26:09.87#ibcon#read 5, iclass 28, count 2 2006.285.08:26:09.87#ibcon#about to read 6, iclass 28, count 2 2006.285.08:26:09.87#ibcon#read 6, iclass 28, count 2 2006.285.08:26:09.87#ibcon#end of sib2, iclass 28, count 2 2006.285.08:26:09.87#ibcon#*mode == 0, iclass 28, count 2 2006.285.08:26:09.87#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.08:26:09.87#ibcon#[25=AT07-04\r\n] 2006.285.08:26:09.87#ibcon#*before write, iclass 28, count 2 2006.285.08:26:09.87#ibcon#enter sib2, iclass 28, count 2 2006.285.08:26:09.87#ibcon#flushed, iclass 28, count 2 2006.285.08:26:09.87#ibcon#about to write, iclass 28, count 2 2006.285.08:26:09.87#ibcon#wrote, iclass 28, count 2 2006.285.08:26:09.87#ibcon#about to read 3, iclass 28, count 2 2006.285.08:26:09.90#ibcon#read 3, iclass 28, count 2 2006.285.08:26:09.90#ibcon#about to read 4, iclass 28, count 2 2006.285.08:26:09.90#ibcon#read 4, iclass 28, count 2 2006.285.08:26:09.90#ibcon#about to read 5, iclass 28, count 2 2006.285.08:26:09.90#ibcon#read 5, iclass 28, count 2 2006.285.08:26:09.90#ibcon#about to read 6, iclass 28, count 2 2006.285.08:26:09.90#ibcon#read 6, iclass 28, count 2 2006.285.08:26:09.90#ibcon#end of sib2, iclass 28, count 2 2006.285.08:26:09.90#ibcon#*after write, iclass 28, count 2 2006.285.08:26:09.90#ibcon#*before return 0, iclass 28, count 2 2006.285.08:26:09.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:26:09.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:26:09.90#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.08:26:09.90#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:09.90#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:26:10.02#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:26:10.02#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:26:10.02#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:26:10.02#ibcon#first serial, iclass 28, count 0 2006.285.08:26:10.02#ibcon#enter sib2, iclass 28, count 0 2006.285.08:26:10.02#ibcon#flushed, iclass 28, count 0 2006.285.08:26:10.02#ibcon#about to write, iclass 28, count 0 2006.285.08:26:10.02#ibcon#wrote, iclass 28, count 0 2006.285.08:26:10.02#ibcon#about to read 3, iclass 28, count 0 2006.285.08:26:10.04#ibcon#read 3, iclass 28, count 0 2006.285.08:26:10.04#ibcon#about to read 4, iclass 28, count 0 2006.285.08:26:10.04#ibcon#read 4, iclass 28, count 0 2006.285.08:26:10.04#ibcon#about to read 5, iclass 28, count 0 2006.285.08:26:10.04#ibcon#read 5, iclass 28, count 0 2006.285.08:26:10.04#ibcon#about to read 6, iclass 28, count 0 2006.285.08:26:10.04#ibcon#read 6, iclass 28, count 0 2006.285.08:26:10.04#ibcon#end of sib2, iclass 28, count 0 2006.285.08:26:10.04#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:26:10.04#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:26:10.04#ibcon#[25=USB\r\n] 2006.285.08:26:10.04#ibcon#*before write, iclass 28, count 0 2006.285.08:26:10.04#ibcon#enter sib2, iclass 28, count 0 2006.285.08:26:10.04#ibcon#flushed, iclass 28, count 0 2006.285.08:26:10.04#ibcon#about to write, iclass 28, count 0 2006.285.08:26:10.04#ibcon#wrote, iclass 28, count 0 2006.285.08:26:10.04#ibcon#about to read 3, iclass 28, count 0 2006.285.08:26:10.07#ibcon#read 3, iclass 28, count 0 2006.285.08:26:10.07#ibcon#about to read 4, iclass 28, count 0 2006.285.08:26:10.07#ibcon#read 4, iclass 28, count 0 2006.285.08:26:10.07#ibcon#about to read 5, iclass 28, count 0 2006.285.08:26:10.07#ibcon#read 5, iclass 28, count 0 2006.285.08:26:10.07#ibcon#about to read 6, iclass 28, count 0 2006.285.08:26:10.07#ibcon#read 6, iclass 28, count 0 2006.285.08:26:10.07#ibcon#end of sib2, iclass 28, count 0 2006.285.08:26:10.07#ibcon#*after write, iclass 28, count 0 2006.285.08:26:10.07#ibcon#*before return 0, iclass 28, count 0 2006.285.08:26:10.07#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:26:10.07#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:26:10.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:26:10.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:26:10.07$vck44/valo=8,884.99 2006.285.08:26:10.07#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.08:26:10.07#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.08:26:10.07#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:10.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:26:10.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:26:10.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:26:10.07#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:26:10.07#ibcon#first serial, iclass 30, count 0 2006.285.08:26:10.07#ibcon#enter sib2, iclass 30, count 0 2006.285.08:26:10.07#ibcon#flushed, iclass 30, count 0 2006.285.08:26:10.07#ibcon#about to write, iclass 30, count 0 2006.285.08:26:10.07#ibcon#wrote, iclass 30, count 0 2006.285.08:26:10.07#ibcon#about to read 3, iclass 30, count 0 2006.285.08:26:10.09#ibcon#read 3, iclass 30, count 0 2006.285.08:26:10.09#ibcon#about to read 4, iclass 30, count 0 2006.285.08:26:10.09#ibcon#read 4, iclass 30, count 0 2006.285.08:26:10.09#ibcon#about to read 5, iclass 30, count 0 2006.285.08:26:10.09#ibcon#read 5, iclass 30, count 0 2006.285.08:26:10.09#ibcon#about to read 6, iclass 30, count 0 2006.285.08:26:10.09#ibcon#read 6, iclass 30, count 0 2006.285.08:26:10.09#ibcon#end of sib2, iclass 30, count 0 2006.285.08:26:10.09#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:26:10.09#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:26:10.09#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:26:10.09#ibcon#*before write, iclass 30, count 0 2006.285.08:26:10.09#ibcon#enter sib2, iclass 30, count 0 2006.285.08:26:10.09#ibcon#flushed, iclass 30, count 0 2006.285.08:26:10.09#ibcon#about to write, iclass 30, count 0 2006.285.08:26:10.09#ibcon#wrote, iclass 30, count 0 2006.285.08:26:10.09#ibcon#about to read 3, iclass 30, count 0 2006.285.08:26:10.13#ibcon#read 3, iclass 30, count 0 2006.285.08:26:10.13#ibcon#about to read 4, iclass 30, count 0 2006.285.08:26:10.13#ibcon#read 4, iclass 30, count 0 2006.285.08:26:10.13#ibcon#about to read 5, iclass 30, count 0 2006.285.08:26:10.13#ibcon#read 5, iclass 30, count 0 2006.285.08:26:10.13#ibcon#about to read 6, iclass 30, count 0 2006.285.08:26:10.13#ibcon#read 6, iclass 30, count 0 2006.285.08:26:10.13#ibcon#end of sib2, iclass 30, count 0 2006.285.08:26:10.13#ibcon#*after write, iclass 30, count 0 2006.285.08:26:10.13#ibcon#*before return 0, iclass 30, count 0 2006.285.08:26:10.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:26:10.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:26:10.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:26:10.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:26:10.13$vck44/va=8,3 2006.285.08:26:10.13#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.08:26:10.13#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.08:26:10.13#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:10.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:26:10.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:26:10.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:26:10.19#ibcon#enter wrdev, iclass 32, count 2 2006.285.08:26:10.19#ibcon#first serial, iclass 32, count 2 2006.285.08:26:10.19#ibcon#enter sib2, iclass 32, count 2 2006.285.08:26:10.19#ibcon#flushed, iclass 32, count 2 2006.285.08:26:10.19#ibcon#about to write, iclass 32, count 2 2006.285.08:26:10.19#ibcon#wrote, iclass 32, count 2 2006.285.08:26:10.19#ibcon#about to read 3, iclass 32, count 2 2006.285.08:26:10.21#ibcon#read 3, iclass 32, count 2 2006.285.08:26:10.21#ibcon#about to read 4, iclass 32, count 2 2006.285.08:26:10.21#ibcon#read 4, iclass 32, count 2 2006.285.08:26:10.21#ibcon#about to read 5, iclass 32, count 2 2006.285.08:26:10.21#ibcon#read 5, iclass 32, count 2 2006.285.08:26:10.21#ibcon#about to read 6, iclass 32, count 2 2006.285.08:26:10.21#ibcon#read 6, iclass 32, count 2 2006.285.08:26:10.21#ibcon#end of sib2, iclass 32, count 2 2006.285.08:26:10.21#ibcon#*mode == 0, iclass 32, count 2 2006.285.08:26:10.21#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.08:26:10.21#ibcon#[25=AT08-03\r\n] 2006.285.08:26:10.21#ibcon#*before write, iclass 32, count 2 2006.285.08:26:10.21#ibcon#enter sib2, iclass 32, count 2 2006.285.08:26:10.21#ibcon#flushed, iclass 32, count 2 2006.285.08:26:10.21#ibcon#about to write, iclass 32, count 2 2006.285.08:26:10.21#ibcon#wrote, iclass 32, count 2 2006.285.08:26:10.21#ibcon#about to read 3, iclass 32, count 2 2006.285.08:26:10.24#ibcon#read 3, iclass 32, count 2 2006.285.08:26:10.24#ibcon#about to read 4, iclass 32, count 2 2006.285.08:26:10.24#ibcon#read 4, iclass 32, count 2 2006.285.08:26:10.24#ibcon#about to read 5, iclass 32, count 2 2006.285.08:26:10.24#ibcon#read 5, iclass 32, count 2 2006.285.08:26:10.24#ibcon#about to read 6, iclass 32, count 2 2006.285.08:26:10.24#ibcon#read 6, iclass 32, count 2 2006.285.08:26:10.24#ibcon#end of sib2, iclass 32, count 2 2006.285.08:26:10.24#ibcon#*after write, iclass 32, count 2 2006.285.08:26:10.24#ibcon#*before return 0, iclass 32, count 2 2006.285.08:26:10.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:26:10.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:26:10.24#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.08:26:10.24#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:10.24#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:26:10.36#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:26:10.36#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:26:10.36#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:26:10.36#ibcon#first serial, iclass 32, count 0 2006.285.08:26:10.36#ibcon#enter sib2, iclass 32, count 0 2006.285.08:26:10.36#ibcon#flushed, iclass 32, count 0 2006.285.08:26:10.36#ibcon#about to write, iclass 32, count 0 2006.285.08:26:10.36#ibcon#wrote, iclass 32, count 0 2006.285.08:26:10.36#ibcon#about to read 3, iclass 32, count 0 2006.285.08:26:10.38#ibcon#read 3, iclass 32, count 0 2006.285.08:26:10.38#ibcon#about to read 4, iclass 32, count 0 2006.285.08:26:10.38#ibcon#read 4, iclass 32, count 0 2006.285.08:26:10.38#ibcon#about to read 5, iclass 32, count 0 2006.285.08:26:10.38#ibcon#read 5, iclass 32, count 0 2006.285.08:26:10.38#ibcon#about to read 6, iclass 32, count 0 2006.285.08:26:10.38#ibcon#read 6, iclass 32, count 0 2006.285.08:26:10.38#ibcon#end of sib2, iclass 32, count 0 2006.285.08:26:10.38#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:26:10.38#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:26:10.38#ibcon#[25=USB\r\n] 2006.285.08:26:10.38#ibcon#*before write, iclass 32, count 0 2006.285.08:26:10.38#ibcon#enter sib2, iclass 32, count 0 2006.285.08:26:10.38#ibcon#flushed, iclass 32, count 0 2006.285.08:26:10.38#ibcon#about to write, iclass 32, count 0 2006.285.08:26:10.38#ibcon#wrote, iclass 32, count 0 2006.285.08:26:10.38#ibcon#about to read 3, iclass 32, count 0 2006.285.08:26:10.41#ibcon#read 3, iclass 32, count 0 2006.285.08:26:10.41#ibcon#about to read 4, iclass 32, count 0 2006.285.08:26:10.41#ibcon#read 4, iclass 32, count 0 2006.285.08:26:10.41#ibcon#about to read 5, iclass 32, count 0 2006.285.08:26:10.41#ibcon#read 5, iclass 32, count 0 2006.285.08:26:10.41#ibcon#about to read 6, iclass 32, count 0 2006.285.08:26:10.41#ibcon#read 6, iclass 32, count 0 2006.285.08:26:10.41#ibcon#end of sib2, iclass 32, count 0 2006.285.08:26:10.41#ibcon#*after write, iclass 32, count 0 2006.285.08:26:10.41#ibcon#*before return 0, iclass 32, count 0 2006.285.08:26:10.41#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:26:10.41#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:26:10.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:26:10.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:26:10.41$vck44/vblo=1,629.99 2006.285.08:26:10.41#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.08:26:10.41#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.08:26:10.41#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:10.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:26:10.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:26:10.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:26:10.41#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:26:10.41#ibcon#first serial, iclass 34, count 0 2006.285.08:26:10.41#ibcon#enter sib2, iclass 34, count 0 2006.285.08:26:10.41#ibcon#flushed, iclass 34, count 0 2006.285.08:26:10.41#ibcon#about to write, iclass 34, count 0 2006.285.08:26:10.41#ibcon#wrote, iclass 34, count 0 2006.285.08:26:10.41#ibcon#about to read 3, iclass 34, count 0 2006.285.08:26:10.43#ibcon#read 3, iclass 34, count 0 2006.285.08:26:10.43#ibcon#about to read 4, iclass 34, count 0 2006.285.08:26:10.43#ibcon#read 4, iclass 34, count 0 2006.285.08:26:10.43#ibcon#about to read 5, iclass 34, count 0 2006.285.08:26:10.43#ibcon#read 5, iclass 34, count 0 2006.285.08:26:10.43#ibcon#about to read 6, iclass 34, count 0 2006.285.08:26:10.43#ibcon#read 6, iclass 34, count 0 2006.285.08:26:10.43#ibcon#end of sib2, iclass 34, count 0 2006.285.08:26:10.43#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:26:10.43#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:26:10.43#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:26:10.43#ibcon#*before write, iclass 34, count 0 2006.285.08:26:10.43#ibcon#enter sib2, iclass 34, count 0 2006.285.08:26:10.43#ibcon#flushed, iclass 34, count 0 2006.285.08:26:10.43#ibcon#about to write, iclass 34, count 0 2006.285.08:26:10.43#ibcon#wrote, iclass 34, count 0 2006.285.08:26:10.43#ibcon#about to read 3, iclass 34, count 0 2006.285.08:26:10.47#ibcon#read 3, iclass 34, count 0 2006.285.08:26:10.47#ibcon#about to read 4, iclass 34, count 0 2006.285.08:26:10.47#ibcon#read 4, iclass 34, count 0 2006.285.08:26:10.47#ibcon#about to read 5, iclass 34, count 0 2006.285.08:26:10.47#ibcon#read 5, iclass 34, count 0 2006.285.08:26:10.47#ibcon#about to read 6, iclass 34, count 0 2006.285.08:26:10.47#ibcon#read 6, iclass 34, count 0 2006.285.08:26:10.47#ibcon#end of sib2, iclass 34, count 0 2006.285.08:26:10.47#ibcon#*after write, iclass 34, count 0 2006.285.08:26:10.47#ibcon#*before return 0, iclass 34, count 0 2006.285.08:26:10.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:26:10.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:26:10.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:26:10.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:26:10.47$vck44/vb=1,4 2006.285.08:26:10.47#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.08:26:10.47#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.08:26:10.47#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:10.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:26:10.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:26:10.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:26:10.47#ibcon#enter wrdev, iclass 36, count 2 2006.285.08:26:10.47#ibcon#first serial, iclass 36, count 2 2006.285.08:26:10.47#ibcon#enter sib2, iclass 36, count 2 2006.285.08:26:10.47#ibcon#flushed, iclass 36, count 2 2006.285.08:26:10.47#ibcon#about to write, iclass 36, count 2 2006.285.08:26:10.47#ibcon#wrote, iclass 36, count 2 2006.285.08:26:10.47#ibcon#about to read 3, iclass 36, count 2 2006.285.08:26:10.49#ibcon#read 3, iclass 36, count 2 2006.285.08:26:10.49#ibcon#about to read 4, iclass 36, count 2 2006.285.08:26:10.49#ibcon#read 4, iclass 36, count 2 2006.285.08:26:10.49#ibcon#about to read 5, iclass 36, count 2 2006.285.08:26:10.49#ibcon#read 5, iclass 36, count 2 2006.285.08:26:10.49#ibcon#about to read 6, iclass 36, count 2 2006.285.08:26:10.49#ibcon#read 6, iclass 36, count 2 2006.285.08:26:10.49#ibcon#end of sib2, iclass 36, count 2 2006.285.08:26:10.49#ibcon#*mode == 0, iclass 36, count 2 2006.285.08:26:10.49#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.08:26:10.49#ibcon#[27=AT01-04\r\n] 2006.285.08:26:10.49#ibcon#*before write, iclass 36, count 2 2006.285.08:26:10.49#ibcon#enter sib2, iclass 36, count 2 2006.285.08:26:10.49#ibcon#flushed, iclass 36, count 2 2006.285.08:26:10.49#ibcon#about to write, iclass 36, count 2 2006.285.08:26:10.49#ibcon#wrote, iclass 36, count 2 2006.285.08:26:10.49#ibcon#about to read 3, iclass 36, count 2 2006.285.08:26:10.52#ibcon#read 3, iclass 36, count 2 2006.285.08:26:10.52#ibcon#about to read 4, iclass 36, count 2 2006.285.08:26:10.52#ibcon#read 4, iclass 36, count 2 2006.285.08:26:10.52#ibcon#about to read 5, iclass 36, count 2 2006.285.08:26:10.52#ibcon#read 5, iclass 36, count 2 2006.285.08:26:10.52#ibcon#about to read 6, iclass 36, count 2 2006.285.08:26:10.52#ibcon#read 6, iclass 36, count 2 2006.285.08:26:10.52#ibcon#end of sib2, iclass 36, count 2 2006.285.08:26:10.52#ibcon#*after write, iclass 36, count 2 2006.285.08:26:10.52#ibcon#*before return 0, iclass 36, count 2 2006.285.08:26:10.52#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:26:10.52#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:26:10.52#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.08:26:10.52#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:10.52#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:26:10.59#abcon#<5=/05 1.9 3.3 22.32 811014.8\r\n> 2006.285.08:26:10.61#abcon#{5=INTERFACE CLEAR} 2006.285.08:26:10.64#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:26:10.64#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:26:10.64#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:26:10.64#ibcon#first serial, iclass 36, count 0 2006.285.08:26:10.64#ibcon#enter sib2, iclass 36, count 0 2006.285.08:26:10.64#ibcon#flushed, iclass 36, count 0 2006.285.08:26:10.64#ibcon#about to write, iclass 36, count 0 2006.285.08:26:10.64#ibcon#wrote, iclass 36, count 0 2006.285.08:26:10.64#ibcon#about to read 3, iclass 36, count 0 2006.285.08:26:10.66#ibcon#read 3, iclass 36, count 0 2006.285.08:26:10.66#ibcon#about to read 4, iclass 36, count 0 2006.285.08:26:10.66#ibcon#read 4, iclass 36, count 0 2006.285.08:26:10.66#ibcon#about to read 5, iclass 36, count 0 2006.285.08:26:10.66#ibcon#read 5, iclass 36, count 0 2006.285.08:26:10.66#ibcon#about to read 6, iclass 36, count 0 2006.285.08:26:10.66#ibcon#read 6, iclass 36, count 0 2006.285.08:26:10.66#ibcon#end of sib2, iclass 36, count 0 2006.285.08:26:10.66#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:26:10.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:26:10.66#ibcon#[27=USB\r\n] 2006.285.08:26:10.66#ibcon#*before write, iclass 36, count 0 2006.285.08:26:10.66#ibcon#enter sib2, iclass 36, count 0 2006.285.08:26:10.66#ibcon#flushed, iclass 36, count 0 2006.285.08:26:10.66#ibcon#about to write, iclass 36, count 0 2006.285.08:26:10.66#ibcon#wrote, iclass 36, count 0 2006.285.08:26:10.66#ibcon#about to read 3, iclass 36, count 0 2006.285.08:26:10.67#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:26:10.69#ibcon#read 3, iclass 36, count 0 2006.285.08:26:10.69#ibcon#about to read 4, iclass 36, count 0 2006.285.08:26:10.69#ibcon#read 4, iclass 36, count 0 2006.285.08:26:10.69#ibcon#about to read 5, iclass 36, count 0 2006.285.08:26:10.69#ibcon#read 5, iclass 36, count 0 2006.285.08:26:10.69#ibcon#about to read 6, iclass 36, count 0 2006.285.08:26:10.69#ibcon#read 6, iclass 36, count 0 2006.285.08:26:10.69#ibcon#end of sib2, iclass 36, count 0 2006.285.08:26:10.69#ibcon#*after write, iclass 36, count 0 2006.285.08:26:10.69#ibcon#*before return 0, iclass 36, count 0 2006.285.08:26:10.69#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:26:10.69#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:26:10.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:26:10.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:26:10.69$vck44/vblo=2,634.99 2006.285.08:26:10.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.08:26:10.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.08:26:10.69#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:10.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:26:10.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:26:10.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:26:10.69#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:26:10.69#ibcon#first serial, iclass 4, count 0 2006.285.08:26:10.69#ibcon#enter sib2, iclass 4, count 0 2006.285.08:26:10.69#ibcon#flushed, iclass 4, count 0 2006.285.08:26:10.69#ibcon#about to write, iclass 4, count 0 2006.285.08:26:10.69#ibcon#wrote, iclass 4, count 0 2006.285.08:26:10.69#ibcon#about to read 3, iclass 4, count 0 2006.285.08:26:10.71#ibcon#read 3, iclass 4, count 0 2006.285.08:26:10.71#ibcon#about to read 4, iclass 4, count 0 2006.285.08:26:10.71#ibcon#read 4, iclass 4, count 0 2006.285.08:26:10.71#ibcon#about to read 5, iclass 4, count 0 2006.285.08:26:10.71#ibcon#read 5, iclass 4, count 0 2006.285.08:26:10.71#ibcon#about to read 6, iclass 4, count 0 2006.285.08:26:10.71#ibcon#read 6, iclass 4, count 0 2006.285.08:26:10.71#ibcon#end of sib2, iclass 4, count 0 2006.285.08:26:10.71#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:26:10.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:26:10.71#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:26:10.71#ibcon#*before write, iclass 4, count 0 2006.285.08:26:10.71#ibcon#enter sib2, iclass 4, count 0 2006.285.08:26:10.71#ibcon#flushed, iclass 4, count 0 2006.285.08:26:10.71#ibcon#about to write, iclass 4, count 0 2006.285.08:26:10.71#ibcon#wrote, iclass 4, count 0 2006.285.08:26:10.71#ibcon#about to read 3, iclass 4, count 0 2006.285.08:26:10.75#ibcon#read 3, iclass 4, count 0 2006.285.08:26:10.75#ibcon#about to read 4, iclass 4, count 0 2006.285.08:26:10.75#ibcon#read 4, iclass 4, count 0 2006.285.08:26:10.75#ibcon#about to read 5, iclass 4, count 0 2006.285.08:26:10.75#ibcon#read 5, iclass 4, count 0 2006.285.08:26:10.75#ibcon#about to read 6, iclass 4, count 0 2006.285.08:26:10.75#ibcon#read 6, iclass 4, count 0 2006.285.08:26:10.75#ibcon#end of sib2, iclass 4, count 0 2006.285.08:26:10.75#ibcon#*after write, iclass 4, count 0 2006.285.08:26:10.75#ibcon#*before return 0, iclass 4, count 0 2006.285.08:26:10.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:26:10.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:26:10.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:26:10.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:26:10.75$vck44/vb=2,5 2006.285.08:26:10.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.08:26:10.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.08:26:10.75#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:10.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:26:10.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:26:10.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:26:10.81#ibcon#enter wrdev, iclass 6, count 2 2006.285.08:26:10.81#ibcon#first serial, iclass 6, count 2 2006.285.08:26:10.81#ibcon#enter sib2, iclass 6, count 2 2006.285.08:26:10.81#ibcon#flushed, iclass 6, count 2 2006.285.08:26:10.81#ibcon#about to write, iclass 6, count 2 2006.285.08:26:10.81#ibcon#wrote, iclass 6, count 2 2006.285.08:26:10.81#ibcon#about to read 3, iclass 6, count 2 2006.285.08:26:10.83#ibcon#read 3, iclass 6, count 2 2006.285.08:26:10.83#ibcon#about to read 4, iclass 6, count 2 2006.285.08:26:10.83#ibcon#read 4, iclass 6, count 2 2006.285.08:26:10.83#ibcon#about to read 5, iclass 6, count 2 2006.285.08:26:10.83#ibcon#read 5, iclass 6, count 2 2006.285.08:26:10.83#ibcon#about to read 6, iclass 6, count 2 2006.285.08:26:10.83#ibcon#read 6, iclass 6, count 2 2006.285.08:26:10.83#ibcon#end of sib2, iclass 6, count 2 2006.285.08:26:10.83#ibcon#*mode == 0, iclass 6, count 2 2006.285.08:26:10.83#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.08:26:10.83#ibcon#[27=AT02-05\r\n] 2006.285.08:26:10.83#ibcon#*before write, iclass 6, count 2 2006.285.08:26:10.83#ibcon#enter sib2, iclass 6, count 2 2006.285.08:26:10.83#ibcon#flushed, iclass 6, count 2 2006.285.08:26:10.83#ibcon#about to write, iclass 6, count 2 2006.285.08:26:10.83#ibcon#wrote, iclass 6, count 2 2006.285.08:26:10.83#ibcon#about to read 3, iclass 6, count 2 2006.285.08:26:10.86#ibcon#read 3, iclass 6, count 2 2006.285.08:26:10.86#ibcon#about to read 4, iclass 6, count 2 2006.285.08:26:10.86#ibcon#read 4, iclass 6, count 2 2006.285.08:26:10.86#ibcon#about to read 5, iclass 6, count 2 2006.285.08:26:10.86#ibcon#read 5, iclass 6, count 2 2006.285.08:26:10.86#ibcon#about to read 6, iclass 6, count 2 2006.285.08:26:10.86#ibcon#read 6, iclass 6, count 2 2006.285.08:26:10.86#ibcon#end of sib2, iclass 6, count 2 2006.285.08:26:10.86#ibcon#*after write, iclass 6, count 2 2006.285.08:26:10.86#ibcon#*before return 0, iclass 6, count 2 2006.285.08:26:10.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:26:10.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:26:10.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.08:26:10.86#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:10.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:26:10.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:26:10.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:26:10.98#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:26:10.98#ibcon#first serial, iclass 6, count 0 2006.285.08:26:10.98#ibcon#enter sib2, iclass 6, count 0 2006.285.08:26:10.98#ibcon#flushed, iclass 6, count 0 2006.285.08:26:10.98#ibcon#about to write, iclass 6, count 0 2006.285.08:26:10.98#ibcon#wrote, iclass 6, count 0 2006.285.08:26:10.98#ibcon#about to read 3, iclass 6, count 0 2006.285.08:26:11.00#ibcon#read 3, iclass 6, count 0 2006.285.08:26:11.00#ibcon#about to read 4, iclass 6, count 0 2006.285.08:26:11.00#ibcon#read 4, iclass 6, count 0 2006.285.08:26:11.00#ibcon#about to read 5, iclass 6, count 0 2006.285.08:26:11.00#ibcon#read 5, iclass 6, count 0 2006.285.08:26:11.00#ibcon#about to read 6, iclass 6, count 0 2006.285.08:26:11.00#ibcon#read 6, iclass 6, count 0 2006.285.08:26:11.00#ibcon#end of sib2, iclass 6, count 0 2006.285.08:26:11.00#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:26:11.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:26:11.00#ibcon#[27=USB\r\n] 2006.285.08:26:11.00#ibcon#*before write, iclass 6, count 0 2006.285.08:26:11.00#ibcon#enter sib2, iclass 6, count 0 2006.285.08:26:11.00#ibcon#flushed, iclass 6, count 0 2006.285.08:26:11.00#ibcon#about to write, iclass 6, count 0 2006.285.08:26:11.00#ibcon#wrote, iclass 6, count 0 2006.285.08:26:11.00#ibcon#about to read 3, iclass 6, count 0 2006.285.08:26:11.03#ibcon#read 3, iclass 6, count 0 2006.285.08:26:11.03#ibcon#about to read 4, iclass 6, count 0 2006.285.08:26:11.03#ibcon#read 4, iclass 6, count 0 2006.285.08:26:11.03#ibcon#about to read 5, iclass 6, count 0 2006.285.08:26:11.03#ibcon#read 5, iclass 6, count 0 2006.285.08:26:11.03#ibcon#about to read 6, iclass 6, count 0 2006.285.08:26:11.03#ibcon#read 6, iclass 6, count 0 2006.285.08:26:11.03#ibcon#end of sib2, iclass 6, count 0 2006.285.08:26:11.03#ibcon#*after write, iclass 6, count 0 2006.285.08:26:11.03#ibcon#*before return 0, iclass 6, count 0 2006.285.08:26:11.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:26:11.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:26:11.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:26:11.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:26:11.03$vck44/vblo=3,649.99 2006.285.08:26:11.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.08:26:11.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.08:26:11.03#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:11.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:26:11.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:26:11.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:26:11.03#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:26:11.03#ibcon#first serial, iclass 10, count 0 2006.285.08:26:11.03#ibcon#enter sib2, iclass 10, count 0 2006.285.08:26:11.03#ibcon#flushed, iclass 10, count 0 2006.285.08:26:11.03#ibcon#about to write, iclass 10, count 0 2006.285.08:26:11.03#ibcon#wrote, iclass 10, count 0 2006.285.08:26:11.03#ibcon#about to read 3, iclass 10, count 0 2006.285.08:26:11.05#ibcon#read 3, iclass 10, count 0 2006.285.08:26:11.05#ibcon#about to read 4, iclass 10, count 0 2006.285.08:26:11.05#ibcon#read 4, iclass 10, count 0 2006.285.08:26:11.05#ibcon#about to read 5, iclass 10, count 0 2006.285.08:26:11.05#ibcon#read 5, iclass 10, count 0 2006.285.08:26:11.05#ibcon#about to read 6, iclass 10, count 0 2006.285.08:26:11.05#ibcon#read 6, iclass 10, count 0 2006.285.08:26:11.05#ibcon#end of sib2, iclass 10, count 0 2006.285.08:26:11.05#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:26:11.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:26:11.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:26:11.05#ibcon#*before write, iclass 10, count 0 2006.285.08:26:11.05#ibcon#enter sib2, iclass 10, count 0 2006.285.08:26:11.05#ibcon#flushed, iclass 10, count 0 2006.285.08:26:11.05#ibcon#about to write, iclass 10, count 0 2006.285.08:26:11.05#ibcon#wrote, iclass 10, count 0 2006.285.08:26:11.05#ibcon#about to read 3, iclass 10, count 0 2006.285.08:26:11.09#ibcon#read 3, iclass 10, count 0 2006.285.08:26:11.09#ibcon#about to read 4, iclass 10, count 0 2006.285.08:26:11.09#ibcon#read 4, iclass 10, count 0 2006.285.08:26:11.09#ibcon#about to read 5, iclass 10, count 0 2006.285.08:26:11.09#ibcon#read 5, iclass 10, count 0 2006.285.08:26:11.09#ibcon#about to read 6, iclass 10, count 0 2006.285.08:26:11.09#ibcon#read 6, iclass 10, count 0 2006.285.08:26:11.09#ibcon#end of sib2, iclass 10, count 0 2006.285.08:26:11.09#ibcon#*after write, iclass 10, count 0 2006.285.08:26:11.09#ibcon#*before return 0, iclass 10, count 0 2006.285.08:26:11.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:26:11.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:26:11.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:26:11.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:26:11.09$vck44/vb=3,4 2006.285.08:26:11.09#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.08:26:11.09#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.08:26:11.09#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:11.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:26:11.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:26:11.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:26:11.15#ibcon#enter wrdev, iclass 12, count 2 2006.285.08:26:11.15#ibcon#first serial, iclass 12, count 2 2006.285.08:26:11.15#ibcon#enter sib2, iclass 12, count 2 2006.285.08:26:11.15#ibcon#flushed, iclass 12, count 2 2006.285.08:26:11.15#ibcon#about to write, iclass 12, count 2 2006.285.08:26:11.15#ibcon#wrote, iclass 12, count 2 2006.285.08:26:11.15#ibcon#about to read 3, iclass 12, count 2 2006.285.08:26:11.17#ibcon#read 3, iclass 12, count 2 2006.285.08:26:11.17#ibcon#about to read 4, iclass 12, count 2 2006.285.08:26:11.17#ibcon#read 4, iclass 12, count 2 2006.285.08:26:11.17#ibcon#about to read 5, iclass 12, count 2 2006.285.08:26:11.17#ibcon#read 5, iclass 12, count 2 2006.285.08:26:11.17#ibcon#about to read 6, iclass 12, count 2 2006.285.08:26:11.17#ibcon#read 6, iclass 12, count 2 2006.285.08:26:11.17#ibcon#end of sib2, iclass 12, count 2 2006.285.08:26:11.17#ibcon#*mode == 0, iclass 12, count 2 2006.285.08:26:11.17#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.08:26:11.17#ibcon#[27=AT03-04\r\n] 2006.285.08:26:11.17#ibcon#*before write, iclass 12, count 2 2006.285.08:26:11.17#ibcon#enter sib2, iclass 12, count 2 2006.285.08:26:11.17#ibcon#flushed, iclass 12, count 2 2006.285.08:26:11.17#ibcon#about to write, iclass 12, count 2 2006.285.08:26:11.17#ibcon#wrote, iclass 12, count 2 2006.285.08:26:11.17#ibcon#about to read 3, iclass 12, count 2 2006.285.08:26:11.20#ibcon#read 3, iclass 12, count 2 2006.285.08:26:11.20#ibcon#about to read 4, iclass 12, count 2 2006.285.08:26:11.20#ibcon#read 4, iclass 12, count 2 2006.285.08:26:11.20#ibcon#about to read 5, iclass 12, count 2 2006.285.08:26:11.20#ibcon#read 5, iclass 12, count 2 2006.285.08:26:11.20#ibcon#about to read 6, iclass 12, count 2 2006.285.08:26:11.20#ibcon#read 6, iclass 12, count 2 2006.285.08:26:11.20#ibcon#end of sib2, iclass 12, count 2 2006.285.08:26:11.20#ibcon#*after write, iclass 12, count 2 2006.285.08:26:11.20#ibcon#*before return 0, iclass 12, count 2 2006.285.08:26:11.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:26:11.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:26:11.20#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.08:26:11.20#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:11.20#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:26:11.32#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:26:11.32#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:26:11.32#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:26:11.32#ibcon#first serial, iclass 12, count 0 2006.285.08:26:11.32#ibcon#enter sib2, iclass 12, count 0 2006.285.08:26:11.32#ibcon#flushed, iclass 12, count 0 2006.285.08:26:11.32#ibcon#about to write, iclass 12, count 0 2006.285.08:26:11.32#ibcon#wrote, iclass 12, count 0 2006.285.08:26:11.32#ibcon#about to read 3, iclass 12, count 0 2006.285.08:26:11.34#ibcon#read 3, iclass 12, count 0 2006.285.08:26:11.34#ibcon#about to read 4, iclass 12, count 0 2006.285.08:26:11.34#ibcon#read 4, iclass 12, count 0 2006.285.08:26:11.34#ibcon#about to read 5, iclass 12, count 0 2006.285.08:26:11.34#ibcon#read 5, iclass 12, count 0 2006.285.08:26:11.34#ibcon#about to read 6, iclass 12, count 0 2006.285.08:26:11.34#ibcon#read 6, iclass 12, count 0 2006.285.08:26:11.34#ibcon#end of sib2, iclass 12, count 0 2006.285.08:26:11.34#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:26:11.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:26:11.34#ibcon#[27=USB\r\n] 2006.285.08:26:11.34#ibcon#*before write, iclass 12, count 0 2006.285.08:26:11.34#ibcon#enter sib2, iclass 12, count 0 2006.285.08:26:11.34#ibcon#flushed, iclass 12, count 0 2006.285.08:26:11.34#ibcon#about to write, iclass 12, count 0 2006.285.08:26:11.34#ibcon#wrote, iclass 12, count 0 2006.285.08:26:11.34#ibcon#about to read 3, iclass 12, count 0 2006.285.08:26:11.37#ibcon#read 3, iclass 12, count 0 2006.285.08:26:11.37#ibcon#about to read 4, iclass 12, count 0 2006.285.08:26:11.37#ibcon#read 4, iclass 12, count 0 2006.285.08:26:11.37#ibcon#about to read 5, iclass 12, count 0 2006.285.08:26:11.37#ibcon#read 5, iclass 12, count 0 2006.285.08:26:11.37#ibcon#about to read 6, iclass 12, count 0 2006.285.08:26:11.37#ibcon#read 6, iclass 12, count 0 2006.285.08:26:11.37#ibcon#end of sib2, iclass 12, count 0 2006.285.08:26:11.37#ibcon#*after write, iclass 12, count 0 2006.285.08:26:11.37#ibcon#*before return 0, iclass 12, count 0 2006.285.08:26:11.37#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:26:11.37#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:26:11.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:26:11.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:26:11.37$vck44/vblo=4,679.99 2006.285.08:26:11.37#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.08:26:11.37#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.08:26:11.37#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:11.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:26:11.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:26:11.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:26:11.37#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:26:11.37#ibcon#first serial, iclass 14, count 0 2006.285.08:26:11.37#ibcon#enter sib2, iclass 14, count 0 2006.285.08:26:11.37#ibcon#flushed, iclass 14, count 0 2006.285.08:26:11.37#ibcon#about to write, iclass 14, count 0 2006.285.08:26:11.37#ibcon#wrote, iclass 14, count 0 2006.285.08:26:11.37#ibcon#about to read 3, iclass 14, count 0 2006.285.08:26:11.39#ibcon#read 3, iclass 14, count 0 2006.285.08:26:11.39#ibcon#about to read 4, iclass 14, count 0 2006.285.08:26:11.39#ibcon#read 4, iclass 14, count 0 2006.285.08:26:11.39#ibcon#about to read 5, iclass 14, count 0 2006.285.08:26:11.39#ibcon#read 5, iclass 14, count 0 2006.285.08:26:11.39#ibcon#about to read 6, iclass 14, count 0 2006.285.08:26:11.39#ibcon#read 6, iclass 14, count 0 2006.285.08:26:11.39#ibcon#end of sib2, iclass 14, count 0 2006.285.08:26:11.39#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:26:11.39#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:26:11.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:26:11.39#ibcon#*before write, iclass 14, count 0 2006.285.08:26:11.39#ibcon#enter sib2, iclass 14, count 0 2006.285.08:26:11.39#ibcon#flushed, iclass 14, count 0 2006.285.08:26:11.39#ibcon#about to write, iclass 14, count 0 2006.285.08:26:11.39#ibcon#wrote, iclass 14, count 0 2006.285.08:26:11.39#ibcon#about to read 3, iclass 14, count 0 2006.285.08:26:11.43#ibcon#read 3, iclass 14, count 0 2006.285.08:26:11.43#ibcon#about to read 4, iclass 14, count 0 2006.285.08:26:11.43#ibcon#read 4, iclass 14, count 0 2006.285.08:26:11.43#ibcon#about to read 5, iclass 14, count 0 2006.285.08:26:11.43#ibcon#read 5, iclass 14, count 0 2006.285.08:26:11.43#ibcon#about to read 6, iclass 14, count 0 2006.285.08:26:11.43#ibcon#read 6, iclass 14, count 0 2006.285.08:26:11.43#ibcon#end of sib2, iclass 14, count 0 2006.285.08:26:11.43#ibcon#*after write, iclass 14, count 0 2006.285.08:26:11.43#ibcon#*before return 0, iclass 14, count 0 2006.285.08:26:11.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:26:11.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:26:11.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:26:11.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:26:11.43$vck44/vb=4,5 2006.285.08:26:11.43#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.08:26:11.43#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.08:26:11.43#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:11.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:26:11.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:26:11.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:26:11.49#ibcon#enter wrdev, iclass 16, count 2 2006.285.08:26:11.49#ibcon#first serial, iclass 16, count 2 2006.285.08:26:11.49#ibcon#enter sib2, iclass 16, count 2 2006.285.08:26:11.49#ibcon#flushed, iclass 16, count 2 2006.285.08:26:11.49#ibcon#about to write, iclass 16, count 2 2006.285.08:26:11.49#ibcon#wrote, iclass 16, count 2 2006.285.08:26:11.49#ibcon#about to read 3, iclass 16, count 2 2006.285.08:26:11.51#ibcon#read 3, iclass 16, count 2 2006.285.08:26:11.51#ibcon#about to read 4, iclass 16, count 2 2006.285.08:26:11.51#ibcon#read 4, iclass 16, count 2 2006.285.08:26:11.51#ibcon#about to read 5, iclass 16, count 2 2006.285.08:26:11.51#ibcon#read 5, iclass 16, count 2 2006.285.08:26:11.51#ibcon#about to read 6, iclass 16, count 2 2006.285.08:26:11.51#ibcon#read 6, iclass 16, count 2 2006.285.08:26:11.51#ibcon#end of sib2, iclass 16, count 2 2006.285.08:26:11.51#ibcon#*mode == 0, iclass 16, count 2 2006.285.08:26:11.51#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.08:26:11.51#ibcon#[27=AT04-05\r\n] 2006.285.08:26:11.51#ibcon#*before write, iclass 16, count 2 2006.285.08:26:11.51#ibcon#enter sib2, iclass 16, count 2 2006.285.08:26:11.51#ibcon#flushed, iclass 16, count 2 2006.285.08:26:11.51#ibcon#about to write, iclass 16, count 2 2006.285.08:26:11.51#ibcon#wrote, iclass 16, count 2 2006.285.08:26:11.51#ibcon#about to read 3, iclass 16, count 2 2006.285.08:26:11.54#ibcon#read 3, iclass 16, count 2 2006.285.08:26:11.54#ibcon#about to read 4, iclass 16, count 2 2006.285.08:26:11.54#ibcon#read 4, iclass 16, count 2 2006.285.08:26:11.54#ibcon#about to read 5, iclass 16, count 2 2006.285.08:26:11.54#ibcon#read 5, iclass 16, count 2 2006.285.08:26:11.54#ibcon#about to read 6, iclass 16, count 2 2006.285.08:26:11.54#ibcon#read 6, iclass 16, count 2 2006.285.08:26:11.54#ibcon#end of sib2, iclass 16, count 2 2006.285.08:26:11.54#ibcon#*after write, iclass 16, count 2 2006.285.08:26:11.54#ibcon#*before return 0, iclass 16, count 2 2006.285.08:26:11.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:26:11.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:26:11.54#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.08:26:11.54#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:11.54#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:26:11.66#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:26:11.66#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:26:11.66#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:26:11.66#ibcon#first serial, iclass 16, count 0 2006.285.08:26:11.66#ibcon#enter sib2, iclass 16, count 0 2006.285.08:26:11.66#ibcon#flushed, iclass 16, count 0 2006.285.08:26:11.66#ibcon#about to write, iclass 16, count 0 2006.285.08:26:11.66#ibcon#wrote, iclass 16, count 0 2006.285.08:26:11.66#ibcon#about to read 3, iclass 16, count 0 2006.285.08:26:11.68#ibcon#read 3, iclass 16, count 0 2006.285.08:26:11.68#ibcon#about to read 4, iclass 16, count 0 2006.285.08:26:11.68#ibcon#read 4, iclass 16, count 0 2006.285.08:26:11.68#ibcon#about to read 5, iclass 16, count 0 2006.285.08:26:11.68#ibcon#read 5, iclass 16, count 0 2006.285.08:26:11.68#ibcon#about to read 6, iclass 16, count 0 2006.285.08:26:11.68#ibcon#read 6, iclass 16, count 0 2006.285.08:26:11.68#ibcon#end of sib2, iclass 16, count 0 2006.285.08:26:11.68#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:26:11.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:26:11.68#ibcon#[27=USB\r\n] 2006.285.08:26:11.68#ibcon#*before write, iclass 16, count 0 2006.285.08:26:11.68#ibcon#enter sib2, iclass 16, count 0 2006.285.08:26:11.68#ibcon#flushed, iclass 16, count 0 2006.285.08:26:11.68#ibcon#about to write, iclass 16, count 0 2006.285.08:26:11.68#ibcon#wrote, iclass 16, count 0 2006.285.08:26:11.68#ibcon#about to read 3, iclass 16, count 0 2006.285.08:26:11.71#ibcon#read 3, iclass 16, count 0 2006.285.08:26:11.71#ibcon#about to read 4, iclass 16, count 0 2006.285.08:26:11.71#ibcon#read 4, iclass 16, count 0 2006.285.08:26:11.71#ibcon#about to read 5, iclass 16, count 0 2006.285.08:26:11.71#ibcon#read 5, iclass 16, count 0 2006.285.08:26:11.71#ibcon#about to read 6, iclass 16, count 0 2006.285.08:26:11.71#ibcon#read 6, iclass 16, count 0 2006.285.08:26:11.71#ibcon#end of sib2, iclass 16, count 0 2006.285.08:26:11.71#ibcon#*after write, iclass 16, count 0 2006.285.08:26:11.71#ibcon#*before return 0, iclass 16, count 0 2006.285.08:26:11.71#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:26:11.71#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:26:11.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:26:11.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:26:11.71$vck44/vblo=5,709.99 2006.285.08:26:11.71#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.08:26:11.71#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.08:26:11.71#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:11.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:26:11.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:26:11.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:26:11.71#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:26:11.71#ibcon#first serial, iclass 18, count 0 2006.285.08:26:11.71#ibcon#enter sib2, iclass 18, count 0 2006.285.08:26:11.71#ibcon#flushed, iclass 18, count 0 2006.285.08:26:11.71#ibcon#about to write, iclass 18, count 0 2006.285.08:26:11.71#ibcon#wrote, iclass 18, count 0 2006.285.08:26:11.71#ibcon#about to read 3, iclass 18, count 0 2006.285.08:26:11.73#ibcon#read 3, iclass 18, count 0 2006.285.08:26:11.73#ibcon#about to read 4, iclass 18, count 0 2006.285.08:26:11.73#ibcon#read 4, iclass 18, count 0 2006.285.08:26:11.73#ibcon#about to read 5, iclass 18, count 0 2006.285.08:26:11.73#ibcon#read 5, iclass 18, count 0 2006.285.08:26:11.73#ibcon#about to read 6, iclass 18, count 0 2006.285.08:26:11.73#ibcon#read 6, iclass 18, count 0 2006.285.08:26:11.73#ibcon#end of sib2, iclass 18, count 0 2006.285.08:26:11.73#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:26:11.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:26:11.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:26:11.73#ibcon#*before write, iclass 18, count 0 2006.285.08:26:11.73#ibcon#enter sib2, iclass 18, count 0 2006.285.08:26:11.73#ibcon#flushed, iclass 18, count 0 2006.285.08:26:11.73#ibcon#about to write, iclass 18, count 0 2006.285.08:26:11.73#ibcon#wrote, iclass 18, count 0 2006.285.08:26:11.73#ibcon#about to read 3, iclass 18, count 0 2006.285.08:26:11.77#ibcon#read 3, iclass 18, count 0 2006.285.08:26:11.77#ibcon#about to read 4, iclass 18, count 0 2006.285.08:26:11.77#ibcon#read 4, iclass 18, count 0 2006.285.08:26:11.77#ibcon#about to read 5, iclass 18, count 0 2006.285.08:26:11.77#ibcon#read 5, iclass 18, count 0 2006.285.08:26:11.77#ibcon#about to read 6, iclass 18, count 0 2006.285.08:26:11.77#ibcon#read 6, iclass 18, count 0 2006.285.08:26:11.77#ibcon#end of sib2, iclass 18, count 0 2006.285.08:26:11.77#ibcon#*after write, iclass 18, count 0 2006.285.08:26:11.77#ibcon#*before return 0, iclass 18, count 0 2006.285.08:26:11.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:26:11.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:26:11.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:26:11.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:26:11.77$vck44/vb=5,4 2006.285.08:26:11.77#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.08:26:11.77#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.08:26:11.77#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:11.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:26:11.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:26:11.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:26:11.83#ibcon#enter wrdev, iclass 20, count 2 2006.285.08:26:11.83#ibcon#first serial, iclass 20, count 2 2006.285.08:26:11.83#ibcon#enter sib2, iclass 20, count 2 2006.285.08:26:11.83#ibcon#flushed, iclass 20, count 2 2006.285.08:26:11.83#ibcon#about to write, iclass 20, count 2 2006.285.08:26:11.83#ibcon#wrote, iclass 20, count 2 2006.285.08:26:11.83#ibcon#about to read 3, iclass 20, count 2 2006.285.08:26:11.85#ibcon#read 3, iclass 20, count 2 2006.285.08:26:11.85#ibcon#about to read 4, iclass 20, count 2 2006.285.08:26:11.85#ibcon#read 4, iclass 20, count 2 2006.285.08:26:11.85#ibcon#about to read 5, iclass 20, count 2 2006.285.08:26:11.85#ibcon#read 5, iclass 20, count 2 2006.285.08:26:11.85#ibcon#about to read 6, iclass 20, count 2 2006.285.08:26:11.85#ibcon#read 6, iclass 20, count 2 2006.285.08:26:11.85#ibcon#end of sib2, iclass 20, count 2 2006.285.08:26:11.85#ibcon#*mode == 0, iclass 20, count 2 2006.285.08:26:11.85#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.08:26:11.85#ibcon#[27=AT05-04\r\n] 2006.285.08:26:11.85#ibcon#*before write, iclass 20, count 2 2006.285.08:26:11.85#ibcon#enter sib2, iclass 20, count 2 2006.285.08:26:11.85#ibcon#flushed, iclass 20, count 2 2006.285.08:26:11.85#ibcon#about to write, iclass 20, count 2 2006.285.08:26:11.85#ibcon#wrote, iclass 20, count 2 2006.285.08:26:11.85#ibcon#about to read 3, iclass 20, count 2 2006.285.08:26:11.88#ibcon#read 3, iclass 20, count 2 2006.285.08:26:11.88#ibcon#about to read 4, iclass 20, count 2 2006.285.08:26:11.88#ibcon#read 4, iclass 20, count 2 2006.285.08:26:11.88#ibcon#about to read 5, iclass 20, count 2 2006.285.08:26:11.88#ibcon#read 5, iclass 20, count 2 2006.285.08:26:11.88#ibcon#about to read 6, iclass 20, count 2 2006.285.08:26:11.88#ibcon#read 6, iclass 20, count 2 2006.285.08:26:11.88#ibcon#end of sib2, iclass 20, count 2 2006.285.08:26:11.88#ibcon#*after write, iclass 20, count 2 2006.285.08:26:11.88#ibcon#*before return 0, iclass 20, count 2 2006.285.08:26:11.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:26:11.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:26:11.88#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.08:26:11.88#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:11.88#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:26:12.00#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:26:12.00#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:26:12.00#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:26:12.00#ibcon#first serial, iclass 20, count 0 2006.285.08:26:12.00#ibcon#enter sib2, iclass 20, count 0 2006.285.08:26:12.00#ibcon#flushed, iclass 20, count 0 2006.285.08:26:12.00#ibcon#about to write, iclass 20, count 0 2006.285.08:26:12.00#ibcon#wrote, iclass 20, count 0 2006.285.08:26:12.00#ibcon#about to read 3, iclass 20, count 0 2006.285.08:26:12.02#ibcon#read 3, iclass 20, count 0 2006.285.08:26:12.02#ibcon#about to read 4, iclass 20, count 0 2006.285.08:26:12.02#ibcon#read 4, iclass 20, count 0 2006.285.08:26:12.02#ibcon#about to read 5, iclass 20, count 0 2006.285.08:26:12.02#ibcon#read 5, iclass 20, count 0 2006.285.08:26:12.02#ibcon#about to read 6, iclass 20, count 0 2006.285.08:26:12.02#ibcon#read 6, iclass 20, count 0 2006.285.08:26:12.02#ibcon#end of sib2, iclass 20, count 0 2006.285.08:26:12.02#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:26:12.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:26:12.02#ibcon#[27=USB\r\n] 2006.285.08:26:12.02#ibcon#*before write, iclass 20, count 0 2006.285.08:26:12.02#ibcon#enter sib2, iclass 20, count 0 2006.285.08:26:12.02#ibcon#flushed, iclass 20, count 0 2006.285.08:26:12.02#ibcon#about to write, iclass 20, count 0 2006.285.08:26:12.02#ibcon#wrote, iclass 20, count 0 2006.285.08:26:12.02#ibcon#about to read 3, iclass 20, count 0 2006.285.08:26:12.05#ibcon#read 3, iclass 20, count 0 2006.285.08:26:12.05#ibcon#about to read 4, iclass 20, count 0 2006.285.08:26:12.05#ibcon#read 4, iclass 20, count 0 2006.285.08:26:12.05#ibcon#about to read 5, iclass 20, count 0 2006.285.08:26:12.05#ibcon#read 5, iclass 20, count 0 2006.285.08:26:12.05#ibcon#about to read 6, iclass 20, count 0 2006.285.08:26:12.05#ibcon#read 6, iclass 20, count 0 2006.285.08:26:12.05#ibcon#end of sib2, iclass 20, count 0 2006.285.08:26:12.05#ibcon#*after write, iclass 20, count 0 2006.285.08:26:12.05#ibcon#*before return 0, iclass 20, count 0 2006.285.08:26:12.05#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:26:12.05#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:26:12.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:26:12.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:26:12.05$vck44/vblo=6,719.99 2006.285.08:26:12.05#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.08:26:12.05#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.08:26:12.05#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:12.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:26:12.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:26:12.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:26:12.05#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:26:12.05#ibcon#first serial, iclass 22, count 0 2006.285.08:26:12.05#ibcon#enter sib2, iclass 22, count 0 2006.285.08:26:12.05#ibcon#flushed, iclass 22, count 0 2006.285.08:26:12.05#ibcon#about to write, iclass 22, count 0 2006.285.08:26:12.05#ibcon#wrote, iclass 22, count 0 2006.285.08:26:12.05#ibcon#about to read 3, iclass 22, count 0 2006.285.08:26:12.07#ibcon#read 3, iclass 22, count 0 2006.285.08:26:12.07#ibcon#about to read 4, iclass 22, count 0 2006.285.08:26:12.07#ibcon#read 4, iclass 22, count 0 2006.285.08:26:12.07#ibcon#about to read 5, iclass 22, count 0 2006.285.08:26:12.07#ibcon#read 5, iclass 22, count 0 2006.285.08:26:12.07#ibcon#about to read 6, iclass 22, count 0 2006.285.08:26:12.07#ibcon#read 6, iclass 22, count 0 2006.285.08:26:12.07#ibcon#end of sib2, iclass 22, count 0 2006.285.08:26:12.07#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:26:12.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:26:12.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:26:12.07#ibcon#*before write, iclass 22, count 0 2006.285.08:26:12.07#ibcon#enter sib2, iclass 22, count 0 2006.285.08:26:12.07#ibcon#flushed, iclass 22, count 0 2006.285.08:26:12.07#ibcon#about to write, iclass 22, count 0 2006.285.08:26:12.07#ibcon#wrote, iclass 22, count 0 2006.285.08:26:12.07#ibcon#about to read 3, iclass 22, count 0 2006.285.08:26:12.11#ibcon#read 3, iclass 22, count 0 2006.285.08:26:12.11#ibcon#about to read 4, iclass 22, count 0 2006.285.08:26:12.11#ibcon#read 4, iclass 22, count 0 2006.285.08:26:12.11#ibcon#about to read 5, iclass 22, count 0 2006.285.08:26:12.11#ibcon#read 5, iclass 22, count 0 2006.285.08:26:12.11#ibcon#about to read 6, iclass 22, count 0 2006.285.08:26:12.11#ibcon#read 6, iclass 22, count 0 2006.285.08:26:12.11#ibcon#end of sib2, iclass 22, count 0 2006.285.08:26:12.11#ibcon#*after write, iclass 22, count 0 2006.285.08:26:12.11#ibcon#*before return 0, iclass 22, count 0 2006.285.08:26:12.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:26:12.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:26:12.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:26:12.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:26:12.11$vck44/vb=6,3 2006.285.08:26:12.11#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.08:26:12.11#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.08:26:12.11#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:12.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:26:12.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:26:12.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:26:12.17#ibcon#enter wrdev, iclass 24, count 2 2006.285.08:26:12.17#ibcon#first serial, iclass 24, count 2 2006.285.08:26:12.17#ibcon#enter sib2, iclass 24, count 2 2006.285.08:26:12.17#ibcon#flushed, iclass 24, count 2 2006.285.08:26:12.17#ibcon#about to write, iclass 24, count 2 2006.285.08:26:12.17#ibcon#wrote, iclass 24, count 2 2006.285.08:26:12.17#ibcon#about to read 3, iclass 24, count 2 2006.285.08:26:12.19#ibcon#read 3, iclass 24, count 2 2006.285.08:26:12.19#ibcon#about to read 4, iclass 24, count 2 2006.285.08:26:12.19#ibcon#read 4, iclass 24, count 2 2006.285.08:26:12.19#ibcon#about to read 5, iclass 24, count 2 2006.285.08:26:12.19#ibcon#read 5, iclass 24, count 2 2006.285.08:26:12.19#ibcon#about to read 6, iclass 24, count 2 2006.285.08:26:12.19#ibcon#read 6, iclass 24, count 2 2006.285.08:26:12.19#ibcon#end of sib2, iclass 24, count 2 2006.285.08:26:12.19#ibcon#*mode == 0, iclass 24, count 2 2006.285.08:26:12.19#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.08:26:12.19#ibcon#[27=AT06-03\r\n] 2006.285.08:26:12.19#ibcon#*before write, iclass 24, count 2 2006.285.08:26:12.19#ibcon#enter sib2, iclass 24, count 2 2006.285.08:26:12.19#ibcon#flushed, iclass 24, count 2 2006.285.08:26:12.19#ibcon#about to write, iclass 24, count 2 2006.285.08:26:12.19#ibcon#wrote, iclass 24, count 2 2006.285.08:26:12.19#ibcon#about to read 3, iclass 24, count 2 2006.285.08:26:12.22#ibcon#read 3, iclass 24, count 2 2006.285.08:26:12.22#ibcon#about to read 4, iclass 24, count 2 2006.285.08:26:12.22#ibcon#read 4, iclass 24, count 2 2006.285.08:26:12.22#ibcon#about to read 5, iclass 24, count 2 2006.285.08:26:12.22#ibcon#read 5, iclass 24, count 2 2006.285.08:26:12.22#ibcon#about to read 6, iclass 24, count 2 2006.285.08:26:12.22#ibcon#read 6, iclass 24, count 2 2006.285.08:26:12.22#ibcon#end of sib2, iclass 24, count 2 2006.285.08:26:12.22#ibcon#*after write, iclass 24, count 2 2006.285.08:26:12.22#ibcon#*before return 0, iclass 24, count 2 2006.285.08:26:12.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:26:12.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:26:12.22#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.08:26:12.22#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:12.22#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:26:12.34#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:26:12.34#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:26:12.34#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:26:12.34#ibcon#first serial, iclass 24, count 0 2006.285.08:26:12.34#ibcon#enter sib2, iclass 24, count 0 2006.285.08:26:12.34#ibcon#flushed, iclass 24, count 0 2006.285.08:26:12.34#ibcon#about to write, iclass 24, count 0 2006.285.08:26:12.34#ibcon#wrote, iclass 24, count 0 2006.285.08:26:12.34#ibcon#about to read 3, iclass 24, count 0 2006.285.08:26:12.36#ibcon#read 3, iclass 24, count 0 2006.285.08:26:12.36#ibcon#about to read 4, iclass 24, count 0 2006.285.08:26:12.36#ibcon#read 4, iclass 24, count 0 2006.285.08:26:12.36#ibcon#about to read 5, iclass 24, count 0 2006.285.08:26:12.36#ibcon#read 5, iclass 24, count 0 2006.285.08:26:12.36#ibcon#about to read 6, iclass 24, count 0 2006.285.08:26:12.36#ibcon#read 6, iclass 24, count 0 2006.285.08:26:12.36#ibcon#end of sib2, iclass 24, count 0 2006.285.08:26:12.36#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:26:12.36#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:26:12.36#ibcon#[27=USB\r\n] 2006.285.08:26:12.36#ibcon#*before write, iclass 24, count 0 2006.285.08:26:12.36#ibcon#enter sib2, iclass 24, count 0 2006.285.08:26:12.36#ibcon#flushed, iclass 24, count 0 2006.285.08:26:12.36#ibcon#about to write, iclass 24, count 0 2006.285.08:26:12.36#ibcon#wrote, iclass 24, count 0 2006.285.08:26:12.36#ibcon#about to read 3, iclass 24, count 0 2006.285.08:26:12.39#ibcon#read 3, iclass 24, count 0 2006.285.08:26:12.39#ibcon#about to read 4, iclass 24, count 0 2006.285.08:26:12.39#ibcon#read 4, iclass 24, count 0 2006.285.08:26:12.39#ibcon#about to read 5, iclass 24, count 0 2006.285.08:26:12.39#ibcon#read 5, iclass 24, count 0 2006.285.08:26:12.39#ibcon#about to read 6, iclass 24, count 0 2006.285.08:26:12.39#ibcon#read 6, iclass 24, count 0 2006.285.08:26:12.39#ibcon#end of sib2, iclass 24, count 0 2006.285.08:26:12.39#ibcon#*after write, iclass 24, count 0 2006.285.08:26:12.39#ibcon#*before return 0, iclass 24, count 0 2006.285.08:26:12.39#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:26:12.39#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:26:12.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:26:12.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:26:12.39$vck44/vblo=7,734.99 2006.285.08:26:12.39#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.08:26:12.39#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.08:26:12.39#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:12.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:26:12.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:26:12.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:26:12.39#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:26:12.39#ibcon#first serial, iclass 26, count 0 2006.285.08:26:12.39#ibcon#enter sib2, iclass 26, count 0 2006.285.08:26:12.39#ibcon#flushed, iclass 26, count 0 2006.285.08:26:12.39#ibcon#about to write, iclass 26, count 0 2006.285.08:26:12.39#ibcon#wrote, iclass 26, count 0 2006.285.08:26:12.39#ibcon#about to read 3, iclass 26, count 0 2006.285.08:26:12.41#ibcon#read 3, iclass 26, count 0 2006.285.08:26:12.41#ibcon#about to read 4, iclass 26, count 0 2006.285.08:26:12.41#ibcon#read 4, iclass 26, count 0 2006.285.08:26:12.41#ibcon#about to read 5, iclass 26, count 0 2006.285.08:26:12.41#ibcon#read 5, iclass 26, count 0 2006.285.08:26:12.41#ibcon#about to read 6, iclass 26, count 0 2006.285.08:26:12.41#ibcon#read 6, iclass 26, count 0 2006.285.08:26:12.41#ibcon#end of sib2, iclass 26, count 0 2006.285.08:26:12.41#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:26:12.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:26:12.41#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:26:12.41#ibcon#*before write, iclass 26, count 0 2006.285.08:26:12.41#ibcon#enter sib2, iclass 26, count 0 2006.285.08:26:12.41#ibcon#flushed, iclass 26, count 0 2006.285.08:26:12.41#ibcon#about to write, iclass 26, count 0 2006.285.08:26:12.41#ibcon#wrote, iclass 26, count 0 2006.285.08:26:12.41#ibcon#about to read 3, iclass 26, count 0 2006.285.08:26:12.45#ibcon#read 3, iclass 26, count 0 2006.285.08:26:12.45#ibcon#about to read 4, iclass 26, count 0 2006.285.08:26:12.45#ibcon#read 4, iclass 26, count 0 2006.285.08:26:12.45#ibcon#about to read 5, iclass 26, count 0 2006.285.08:26:12.45#ibcon#read 5, iclass 26, count 0 2006.285.08:26:12.45#ibcon#about to read 6, iclass 26, count 0 2006.285.08:26:12.45#ibcon#read 6, iclass 26, count 0 2006.285.08:26:12.45#ibcon#end of sib2, iclass 26, count 0 2006.285.08:26:12.45#ibcon#*after write, iclass 26, count 0 2006.285.08:26:12.45#ibcon#*before return 0, iclass 26, count 0 2006.285.08:26:12.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:26:12.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:26:12.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:26:12.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:26:12.45$vck44/vb=7,4 2006.285.08:26:12.45#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.08:26:12.45#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.08:26:12.45#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:12.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:26:12.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:26:12.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:26:12.51#ibcon#enter wrdev, iclass 28, count 2 2006.285.08:26:12.51#ibcon#first serial, iclass 28, count 2 2006.285.08:26:12.51#ibcon#enter sib2, iclass 28, count 2 2006.285.08:26:12.51#ibcon#flushed, iclass 28, count 2 2006.285.08:26:12.51#ibcon#about to write, iclass 28, count 2 2006.285.08:26:12.51#ibcon#wrote, iclass 28, count 2 2006.285.08:26:12.51#ibcon#about to read 3, iclass 28, count 2 2006.285.08:26:12.53#ibcon#read 3, iclass 28, count 2 2006.285.08:26:12.53#ibcon#about to read 4, iclass 28, count 2 2006.285.08:26:12.53#ibcon#read 4, iclass 28, count 2 2006.285.08:26:12.53#ibcon#about to read 5, iclass 28, count 2 2006.285.08:26:12.53#ibcon#read 5, iclass 28, count 2 2006.285.08:26:12.53#ibcon#about to read 6, iclass 28, count 2 2006.285.08:26:12.53#ibcon#read 6, iclass 28, count 2 2006.285.08:26:12.53#ibcon#end of sib2, iclass 28, count 2 2006.285.08:26:12.53#ibcon#*mode == 0, iclass 28, count 2 2006.285.08:26:12.53#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.08:26:12.53#ibcon#[27=AT07-04\r\n] 2006.285.08:26:12.53#ibcon#*before write, iclass 28, count 2 2006.285.08:26:12.53#ibcon#enter sib2, iclass 28, count 2 2006.285.08:26:12.53#ibcon#flushed, iclass 28, count 2 2006.285.08:26:12.53#ibcon#about to write, iclass 28, count 2 2006.285.08:26:12.53#ibcon#wrote, iclass 28, count 2 2006.285.08:26:12.53#ibcon#about to read 3, iclass 28, count 2 2006.285.08:26:12.56#ibcon#read 3, iclass 28, count 2 2006.285.08:26:12.56#ibcon#about to read 4, iclass 28, count 2 2006.285.08:26:12.56#ibcon#read 4, iclass 28, count 2 2006.285.08:26:12.56#ibcon#about to read 5, iclass 28, count 2 2006.285.08:26:12.56#ibcon#read 5, iclass 28, count 2 2006.285.08:26:12.56#ibcon#about to read 6, iclass 28, count 2 2006.285.08:26:12.56#ibcon#read 6, iclass 28, count 2 2006.285.08:26:12.56#ibcon#end of sib2, iclass 28, count 2 2006.285.08:26:12.56#ibcon#*after write, iclass 28, count 2 2006.285.08:26:12.56#ibcon#*before return 0, iclass 28, count 2 2006.285.08:26:12.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:26:12.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:26:12.56#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.08:26:12.56#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:12.56#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:26:12.68#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:26:12.68#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:26:12.68#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:26:12.68#ibcon#first serial, iclass 28, count 0 2006.285.08:26:12.68#ibcon#enter sib2, iclass 28, count 0 2006.285.08:26:12.68#ibcon#flushed, iclass 28, count 0 2006.285.08:26:12.68#ibcon#about to write, iclass 28, count 0 2006.285.08:26:12.68#ibcon#wrote, iclass 28, count 0 2006.285.08:26:12.68#ibcon#about to read 3, iclass 28, count 0 2006.285.08:26:12.70#ibcon#read 3, iclass 28, count 0 2006.285.08:26:12.70#ibcon#about to read 4, iclass 28, count 0 2006.285.08:26:12.70#ibcon#read 4, iclass 28, count 0 2006.285.08:26:12.70#ibcon#about to read 5, iclass 28, count 0 2006.285.08:26:12.70#ibcon#read 5, iclass 28, count 0 2006.285.08:26:12.70#ibcon#about to read 6, iclass 28, count 0 2006.285.08:26:12.70#ibcon#read 6, iclass 28, count 0 2006.285.08:26:12.70#ibcon#end of sib2, iclass 28, count 0 2006.285.08:26:12.70#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:26:12.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:26:12.70#ibcon#[27=USB\r\n] 2006.285.08:26:12.70#ibcon#*before write, iclass 28, count 0 2006.285.08:26:12.70#ibcon#enter sib2, iclass 28, count 0 2006.285.08:26:12.70#ibcon#flushed, iclass 28, count 0 2006.285.08:26:12.70#ibcon#about to write, iclass 28, count 0 2006.285.08:26:12.70#ibcon#wrote, iclass 28, count 0 2006.285.08:26:12.70#ibcon#about to read 3, iclass 28, count 0 2006.285.08:26:12.73#ibcon#read 3, iclass 28, count 0 2006.285.08:26:12.73#ibcon#about to read 4, iclass 28, count 0 2006.285.08:26:12.73#ibcon#read 4, iclass 28, count 0 2006.285.08:26:12.73#ibcon#about to read 5, iclass 28, count 0 2006.285.08:26:12.73#ibcon#read 5, iclass 28, count 0 2006.285.08:26:12.73#ibcon#about to read 6, iclass 28, count 0 2006.285.08:26:12.73#ibcon#read 6, iclass 28, count 0 2006.285.08:26:12.73#ibcon#end of sib2, iclass 28, count 0 2006.285.08:26:12.73#ibcon#*after write, iclass 28, count 0 2006.285.08:26:12.73#ibcon#*before return 0, iclass 28, count 0 2006.285.08:26:12.73#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:26:12.73#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:26:12.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:26:12.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:26:12.73$vck44/vblo=8,744.99 2006.285.08:26:12.73#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.08:26:12.73#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.08:26:12.73#ibcon#ireg 17 cls_cnt 0 2006.285.08:26:12.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:26:12.73#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:26:12.73#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:26:12.73#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:26:12.73#ibcon#first serial, iclass 30, count 0 2006.285.08:26:12.73#ibcon#enter sib2, iclass 30, count 0 2006.285.08:26:12.73#ibcon#flushed, iclass 30, count 0 2006.285.08:26:12.73#ibcon#about to write, iclass 30, count 0 2006.285.08:26:12.73#ibcon#wrote, iclass 30, count 0 2006.285.08:26:12.73#ibcon#about to read 3, iclass 30, count 0 2006.285.08:26:12.75#ibcon#read 3, iclass 30, count 0 2006.285.08:26:12.75#ibcon#about to read 4, iclass 30, count 0 2006.285.08:26:12.75#ibcon#read 4, iclass 30, count 0 2006.285.08:26:12.75#ibcon#about to read 5, iclass 30, count 0 2006.285.08:26:12.75#ibcon#read 5, iclass 30, count 0 2006.285.08:26:12.75#ibcon#about to read 6, iclass 30, count 0 2006.285.08:26:12.75#ibcon#read 6, iclass 30, count 0 2006.285.08:26:12.75#ibcon#end of sib2, iclass 30, count 0 2006.285.08:26:12.75#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:26:12.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:26:12.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:26:12.75#ibcon#*before write, iclass 30, count 0 2006.285.08:26:12.75#ibcon#enter sib2, iclass 30, count 0 2006.285.08:26:12.75#ibcon#flushed, iclass 30, count 0 2006.285.08:26:12.75#ibcon#about to write, iclass 30, count 0 2006.285.08:26:12.75#ibcon#wrote, iclass 30, count 0 2006.285.08:26:12.75#ibcon#about to read 3, iclass 30, count 0 2006.285.08:26:12.79#ibcon#read 3, iclass 30, count 0 2006.285.08:26:12.79#ibcon#about to read 4, iclass 30, count 0 2006.285.08:26:12.79#ibcon#read 4, iclass 30, count 0 2006.285.08:26:12.79#ibcon#about to read 5, iclass 30, count 0 2006.285.08:26:12.79#ibcon#read 5, iclass 30, count 0 2006.285.08:26:12.79#ibcon#about to read 6, iclass 30, count 0 2006.285.08:26:12.79#ibcon#read 6, iclass 30, count 0 2006.285.08:26:12.79#ibcon#end of sib2, iclass 30, count 0 2006.285.08:26:12.79#ibcon#*after write, iclass 30, count 0 2006.285.08:26:12.79#ibcon#*before return 0, iclass 30, count 0 2006.285.08:26:12.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:26:12.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:26:12.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:26:12.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:26:12.79$vck44/vb=8,4 2006.285.08:26:12.79#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.08:26:12.79#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.08:26:12.79#ibcon#ireg 11 cls_cnt 2 2006.285.08:26:12.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:26:12.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:26:12.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:26:12.85#ibcon#enter wrdev, iclass 32, count 2 2006.285.08:26:12.85#ibcon#first serial, iclass 32, count 2 2006.285.08:26:12.85#ibcon#enter sib2, iclass 32, count 2 2006.285.08:26:12.85#ibcon#flushed, iclass 32, count 2 2006.285.08:26:12.85#ibcon#about to write, iclass 32, count 2 2006.285.08:26:12.85#ibcon#wrote, iclass 32, count 2 2006.285.08:26:12.85#ibcon#about to read 3, iclass 32, count 2 2006.285.08:26:12.87#ibcon#read 3, iclass 32, count 2 2006.285.08:26:12.87#ibcon#about to read 4, iclass 32, count 2 2006.285.08:26:12.87#ibcon#read 4, iclass 32, count 2 2006.285.08:26:12.87#ibcon#about to read 5, iclass 32, count 2 2006.285.08:26:12.87#ibcon#read 5, iclass 32, count 2 2006.285.08:26:12.87#ibcon#about to read 6, iclass 32, count 2 2006.285.08:26:12.87#ibcon#read 6, iclass 32, count 2 2006.285.08:26:12.87#ibcon#end of sib2, iclass 32, count 2 2006.285.08:26:12.87#ibcon#*mode == 0, iclass 32, count 2 2006.285.08:26:12.87#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.08:26:12.87#ibcon#[27=AT08-04\r\n] 2006.285.08:26:12.87#ibcon#*before write, iclass 32, count 2 2006.285.08:26:12.87#ibcon#enter sib2, iclass 32, count 2 2006.285.08:26:12.87#ibcon#flushed, iclass 32, count 2 2006.285.08:26:12.87#ibcon#about to write, iclass 32, count 2 2006.285.08:26:12.87#ibcon#wrote, iclass 32, count 2 2006.285.08:26:12.87#ibcon#about to read 3, iclass 32, count 2 2006.285.08:26:12.90#ibcon#read 3, iclass 32, count 2 2006.285.08:26:12.90#ibcon#about to read 4, iclass 32, count 2 2006.285.08:26:12.90#ibcon#read 4, iclass 32, count 2 2006.285.08:26:12.90#ibcon#about to read 5, iclass 32, count 2 2006.285.08:26:12.90#ibcon#read 5, iclass 32, count 2 2006.285.08:26:12.90#ibcon#about to read 6, iclass 32, count 2 2006.285.08:26:12.90#ibcon#read 6, iclass 32, count 2 2006.285.08:26:12.90#ibcon#end of sib2, iclass 32, count 2 2006.285.08:26:12.90#ibcon#*after write, iclass 32, count 2 2006.285.08:26:12.90#ibcon#*before return 0, iclass 32, count 2 2006.285.08:26:12.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:26:12.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:26:12.90#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.08:26:12.90#ibcon#ireg 7 cls_cnt 0 2006.285.08:26:12.90#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:26:13.02#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:26:13.02#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:26:13.02#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:26:13.02#ibcon#first serial, iclass 32, count 0 2006.285.08:26:13.02#ibcon#enter sib2, iclass 32, count 0 2006.285.08:26:13.02#ibcon#flushed, iclass 32, count 0 2006.285.08:26:13.02#ibcon#about to write, iclass 32, count 0 2006.285.08:26:13.02#ibcon#wrote, iclass 32, count 0 2006.285.08:26:13.02#ibcon#about to read 3, iclass 32, count 0 2006.285.08:26:13.04#ibcon#read 3, iclass 32, count 0 2006.285.08:26:13.04#ibcon#about to read 4, iclass 32, count 0 2006.285.08:26:13.04#ibcon#read 4, iclass 32, count 0 2006.285.08:26:13.04#ibcon#about to read 5, iclass 32, count 0 2006.285.08:26:13.04#ibcon#read 5, iclass 32, count 0 2006.285.08:26:13.04#ibcon#about to read 6, iclass 32, count 0 2006.285.08:26:13.04#ibcon#read 6, iclass 32, count 0 2006.285.08:26:13.04#ibcon#end of sib2, iclass 32, count 0 2006.285.08:26:13.04#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:26:13.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:26:13.04#ibcon#[27=USB\r\n] 2006.285.08:26:13.04#ibcon#*before write, iclass 32, count 0 2006.285.08:26:13.04#ibcon#enter sib2, iclass 32, count 0 2006.285.08:26:13.04#ibcon#flushed, iclass 32, count 0 2006.285.08:26:13.04#ibcon#about to write, iclass 32, count 0 2006.285.08:26:13.04#ibcon#wrote, iclass 32, count 0 2006.285.08:26:13.04#ibcon#about to read 3, iclass 32, count 0 2006.285.08:26:13.07#ibcon#read 3, iclass 32, count 0 2006.285.08:26:13.07#ibcon#about to read 4, iclass 32, count 0 2006.285.08:26:13.07#ibcon#read 4, iclass 32, count 0 2006.285.08:26:13.07#ibcon#about to read 5, iclass 32, count 0 2006.285.08:26:13.07#ibcon#read 5, iclass 32, count 0 2006.285.08:26:13.07#ibcon#about to read 6, iclass 32, count 0 2006.285.08:26:13.07#ibcon#read 6, iclass 32, count 0 2006.285.08:26:13.07#ibcon#end of sib2, iclass 32, count 0 2006.285.08:26:13.07#ibcon#*after write, iclass 32, count 0 2006.285.08:26:13.07#ibcon#*before return 0, iclass 32, count 0 2006.285.08:26:13.07#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:26:13.07#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:26:13.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:26:13.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:26:13.07$vck44/vabw=wide 2006.285.08:26:13.07#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.08:26:13.07#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.08:26:13.07#ibcon#ireg 8 cls_cnt 0 2006.285.08:26:13.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:26:13.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:26:13.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:26:13.07#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:26:13.07#ibcon#first serial, iclass 34, count 0 2006.285.08:26:13.07#ibcon#enter sib2, iclass 34, count 0 2006.285.08:26:13.07#ibcon#flushed, iclass 34, count 0 2006.285.08:26:13.07#ibcon#about to write, iclass 34, count 0 2006.285.08:26:13.07#ibcon#wrote, iclass 34, count 0 2006.285.08:26:13.07#ibcon#about to read 3, iclass 34, count 0 2006.285.08:26:13.09#ibcon#read 3, iclass 34, count 0 2006.285.08:26:13.09#ibcon#about to read 4, iclass 34, count 0 2006.285.08:26:13.09#ibcon#read 4, iclass 34, count 0 2006.285.08:26:13.09#ibcon#about to read 5, iclass 34, count 0 2006.285.08:26:13.09#ibcon#read 5, iclass 34, count 0 2006.285.08:26:13.09#ibcon#about to read 6, iclass 34, count 0 2006.285.08:26:13.09#ibcon#read 6, iclass 34, count 0 2006.285.08:26:13.09#ibcon#end of sib2, iclass 34, count 0 2006.285.08:26:13.09#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:26:13.09#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:26:13.09#ibcon#[25=BW32\r\n] 2006.285.08:26:13.09#ibcon#*before write, iclass 34, count 0 2006.285.08:26:13.09#ibcon#enter sib2, iclass 34, count 0 2006.285.08:26:13.09#ibcon#flushed, iclass 34, count 0 2006.285.08:26:13.09#ibcon#about to write, iclass 34, count 0 2006.285.08:26:13.09#ibcon#wrote, iclass 34, count 0 2006.285.08:26:13.09#ibcon#about to read 3, iclass 34, count 0 2006.285.08:26:13.12#ibcon#read 3, iclass 34, count 0 2006.285.08:26:13.12#ibcon#about to read 4, iclass 34, count 0 2006.285.08:26:13.12#ibcon#read 4, iclass 34, count 0 2006.285.08:26:13.12#ibcon#about to read 5, iclass 34, count 0 2006.285.08:26:13.12#ibcon#read 5, iclass 34, count 0 2006.285.08:26:13.12#ibcon#about to read 6, iclass 34, count 0 2006.285.08:26:13.12#ibcon#read 6, iclass 34, count 0 2006.285.08:26:13.12#ibcon#end of sib2, iclass 34, count 0 2006.285.08:26:13.12#ibcon#*after write, iclass 34, count 0 2006.285.08:26:13.12#ibcon#*before return 0, iclass 34, count 0 2006.285.08:26:13.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:26:13.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:26:13.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:26:13.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:26:13.12$vck44/vbbw=wide 2006.285.08:26:13.12#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.08:26:13.12#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.08:26:13.12#ibcon#ireg 8 cls_cnt 0 2006.285.08:26:13.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:26:13.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:26:13.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:26:13.19#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:26:13.19#ibcon#first serial, iclass 36, count 0 2006.285.08:26:13.19#ibcon#enter sib2, iclass 36, count 0 2006.285.08:26:13.19#ibcon#flushed, iclass 36, count 0 2006.285.08:26:13.19#ibcon#about to write, iclass 36, count 0 2006.285.08:26:13.19#ibcon#wrote, iclass 36, count 0 2006.285.08:26:13.19#ibcon#about to read 3, iclass 36, count 0 2006.285.08:26:13.21#ibcon#read 3, iclass 36, count 0 2006.285.08:26:13.21#ibcon#about to read 4, iclass 36, count 0 2006.285.08:26:13.21#ibcon#read 4, iclass 36, count 0 2006.285.08:26:13.21#ibcon#about to read 5, iclass 36, count 0 2006.285.08:26:13.21#ibcon#read 5, iclass 36, count 0 2006.285.08:26:13.21#ibcon#about to read 6, iclass 36, count 0 2006.285.08:26:13.21#ibcon#read 6, iclass 36, count 0 2006.285.08:26:13.21#ibcon#end of sib2, iclass 36, count 0 2006.285.08:26:13.21#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:26:13.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:26:13.21#ibcon#[27=BW32\r\n] 2006.285.08:26:13.21#ibcon#*before write, iclass 36, count 0 2006.285.08:26:13.21#ibcon#enter sib2, iclass 36, count 0 2006.285.08:26:13.21#ibcon#flushed, iclass 36, count 0 2006.285.08:26:13.21#ibcon#about to write, iclass 36, count 0 2006.285.08:26:13.21#ibcon#wrote, iclass 36, count 0 2006.285.08:26:13.21#ibcon#about to read 3, iclass 36, count 0 2006.285.08:26:13.24#ibcon#read 3, iclass 36, count 0 2006.285.08:26:13.24#ibcon#about to read 4, iclass 36, count 0 2006.285.08:26:13.24#ibcon#read 4, iclass 36, count 0 2006.285.08:26:13.24#ibcon#about to read 5, iclass 36, count 0 2006.285.08:26:13.24#ibcon#read 5, iclass 36, count 0 2006.285.08:26:13.24#ibcon#about to read 6, iclass 36, count 0 2006.285.08:26:13.24#ibcon#read 6, iclass 36, count 0 2006.285.08:26:13.24#ibcon#end of sib2, iclass 36, count 0 2006.285.08:26:13.24#ibcon#*after write, iclass 36, count 0 2006.285.08:26:13.24#ibcon#*before return 0, iclass 36, count 0 2006.285.08:26:13.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:26:13.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:26:13.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:26:13.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:26:13.24$setupk4/ifdk4 2006.285.08:26:13.24$ifdk4/lo= 2006.285.08:26:13.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:26:13.24$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:26:13.24$ifdk4/patch= 2006.285.08:26:13.24$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:26:13.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:26:13.24$setupk4/!*+20s 2006.285.08:26:20.76#abcon#<5=/05 1.9 3.3 22.32 811014.8\r\n> 2006.285.08:26:20.78#abcon#{5=INTERFACE CLEAR} 2006.285.08:26:20.84#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:26:27.75$setupk4/"tpicd 2006.285.08:26:27.75$setupk4/echo=off 2006.285.08:26:27.75$setupk4/xlog=off 2006.285.08:26:27.75:!2006.285.08:27:42 2006.285.08:26:35.14#trakl#Source acquired 2006.285.08:26:35.14#flagr#flagr/antenna,acquired 2006.285.08:27:42.00:preob 2006.285.08:27:42.14/onsource/TRACKING 2006.285.08:27:42.14:!2006.285.08:27:52 2006.285.08:27:52.00:"tape 2006.285.08:27:52.00:"st=record 2006.285.08:27:52.00:data_valid=on 2006.285.08:27:52.00:midob 2006.285.08:27:53.14/onsource/TRACKING 2006.285.08:27:53.14/wx/22.28,1014.8,81 2006.285.08:27:53.26/cable/+6.4748E-03 2006.285.08:27:54.35/va/01,07,usb,yes,32,35 2006.285.08:27:54.35/va/02,06,usb,yes,33,33 2006.285.08:27:54.35/va/03,07,usb,yes,32,34 2006.285.08:27:54.35/va/04,06,usb,yes,34,35 2006.285.08:27:54.35/va/05,03,usb,yes,33,34 2006.285.08:27:54.35/va/06,04,usb,yes,30,29 2006.285.08:27:54.35/va/07,04,usb,yes,30,31 2006.285.08:27:54.35/va/08,03,usb,yes,31,38 2006.285.08:27:54.58/valo/01,524.99,yes,locked 2006.285.08:27:54.58/valo/02,534.99,yes,locked 2006.285.08:27:54.58/valo/03,564.99,yes,locked 2006.285.08:27:54.58/valo/04,624.99,yes,locked 2006.285.08:27:54.58/valo/05,734.99,yes,locked 2006.285.08:27:54.58/valo/06,814.99,yes,locked 2006.285.08:27:54.58/valo/07,864.99,yes,locked 2006.285.08:27:54.58/valo/08,884.99,yes,locked 2006.285.08:27:55.67/vb/01,04,usb,yes,30,28 2006.285.08:27:55.67/vb/02,05,usb,yes,29,28 2006.285.08:27:55.67/vb/03,04,usb,yes,30,32 2006.285.08:27:55.67/vb/04,05,usb,yes,30,29 2006.285.08:27:55.67/vb/05,04,usb,yes,26,29 2006.285.08:27:55.67/vb/06,03,usb,yes,38,33 2006.285.08:27:55.67/vb/07,04,usb,yes,30,30 2006.285.08:27:55.67/vb/08,04,usb,yes,27,31 2006.285.08:27:55.90/vblo/01,629.99,yes,locked 2006.285.08:27:55.90/vblo/02,634.99,yes,locked 2006.285.08:27:55.90/vblo/03,649.99,yes,locked 2006.285.08:27:55.90/vblo/04,679.99,yes,locked 2006.285.08:27:55.90/vblo/05,709.99,yes,locked 2006.285.08:27:55.90/vblo/06,719.99,yes,locked 2006.285.08:27:55.90/vblo/07,734.99,yes,locked 2006.285.08:27:55.90/vblo/08,744.99,yes,locked 2006.285.08:27:56.05/vabw/8 2006.285.08:27:56.20/vbbw/8 2006.285.08:27:56.29/xfe/off,on,12.2 2006.285.08:27:56.67/ifatt/23,28,28,28 2006.285.08:27:57.07/fmout-gps/S +2.79E-07 2006.285.08:27:57.09:!2006.285.08:28:32 2006.285.08:28:32.00:data_valid=off 2006.285.08:28:32.00:"et 2006.285.08:28:32.00:!+3s 2006.285.08:28:35.01:"tape 2006.285.08:28:35.01:postob 2006.285.08:28:35.19/cable/+6.4757E-03 2006.285.08:28:35.19/wx/22.27,1014.9,81 2006.285.08:28:36.07/fmout-gps/S +2.80E-07 2006.285.08:28:36.07:scan_name=285-0829,jd0610,80 2006.285.08:28:36.07:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.285.08:28:37.14#flagr#flagr/antenna,new-source 2006.285.08:28:37.14:checkk5 2006.285.08:28:37.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:28:37.93/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:28:38.31/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:28:38.68/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:28:39.08/chk_obsdata//k5ts1/T2850827??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:28:39.47/chk_obsdata//k5ts2/T2850827??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:28:40.23/chk_obsdata//k5ts3/T2850827??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:28:40.86/chk_obsdata//k5ts4/T2850827??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:28:41.65/k5log//k5ts1_log_newline 2006.285.08:28:42.40/k5log//k5ts2_log_newline 2006.285.08:28:43.14/k5log//k5ts3_log_newline 2006.285.08:28:44.11/k5log//k5ts4_log_newline 2006.285.08:28:44.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:28:44.13:setupk4=1 2006.285.08:28:44.13$setupk4/echo=on 2006.285.08:28:44.13$setupk4/pcalon 2006.285.08:28:44.13$pcalon/"no phase cal control is implemented here 2006.285.08:28:44.13$setupk4/"tpicd=stop 2006.285.08:28:44.13$setupk4/"rec=synch_on 2006.285.08:28:44.13$setupk4/"rec_mode=128 2006.285.08:28:44.13$setupk4/!* 2006.285.08:28:44.13$setupk4/recpk4 2006.285.08:28:44.13$recpk4/recpatch= 2006.285.08:28:44.13$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:28:44.13$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:28:44.13$setupk4/vck44 2006.285.08:28:44.13$vck44/valo=1,524.99 2006.285.08:28:44.13#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.08:28:44.13#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.08:28:44.13#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:44.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:28:44.13#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:28:44.13#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:28:44.13#ibcon#enter wrdev, iclass 29, count 0 2006.285.08:28:44.13#ibcon#first serial, iclass 29, count 0 2006.285.08:28:44.13#ibcon#enter sib2, iclass 29, count 0 2006.285.08:28:44.13#ibcon#flushed, iclass 29, count 0 2006.285.08:28:44.13#ibcon#about to write, iclass 29, count 0 2006.285.08:28:44.13#ibcon#wrote, iclass 29, count 0 2006.285.08:28:44.13#ibcon#about to read 3, iclass 29, count 0 2006.285.08:28:44.15#ibcon#read 3, iclass 29, count 0 2006.285.08:28:44.15#ibcon#about to read 4, iclass 29, count 0 2006.285.08:28:44.15#ibcon#read 4, iclass 29, count 0 2006.285.08:28:44.15#ibcon#about to read 5, iclass 29, count 0 2006.285.08:28:44.15#ibcon#read 5, iclass 29, count 0 2006.285.08:28:44.15#ibcon#about to read 6, iclass 29, count 0 2006.285.08:28:44.15#ibcon#read 6, iclass 29, count 0 2006.285.08:28:44.15#ibcon#end of sib2, iclass 29, count 0 2006.285.08:28:44.15#ibcon#*mode == 0, iclass 29, count 0 2006.285.08:28:44.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.08:28:44.15#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:28:44.15#ibcon#*before write, iclass 29, count 0 2006.285.08:28:44.15#ibcon#enter sib2, iclass 29, count 0 2006.285.08:28:44.15#ibcon#flushed, iclass 29, count 0 2006.285.08:28:44.15#ibcon#about to write, iclass 29, count 0 2006.285.08:28:44.15#ibcon#wrote, iclass 29, count 0 2006.285.08:28:44.15#ibcon#about to read 3, iclass 29, count 0 2006.285.08:28:44.20#ibcon#read 3, iclass 29, count 0 2006.285.08:28:44.20#ibcon#about to read 4, iclass 29, count 0 2006.285.08:28:44.20#ibcon#read 4, iclass 29, count 0 2006.285.08:28:44.20#ibcon#about to read 5, iclass 29, count 0 2006.285.08:28:44.20#ibcon#read 5, iclass 29, count 0 2006.285.08:28:44.20#ibcon#about to read 6, iclass 29, count 0 2006.285.08:28:44.20#ibcon#read 6, iclass 29, count 0 2006.285.08:28:44.20#ibcon#end of sib2, iclass 29, count 0 2006.285.08:28:44.20#ibcon#*after write, iclass 29, count 0 2006.285.08:28:44.20#ibcon#*before return 0, iclass 29, count 0 2006.285.08:28:44.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:28:44.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:28:44.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.08:28:44.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.08:28:44.20$vck44/va=1,7 2006.285.08:28:44.20#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.08:28:44.20#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.08:28:44.20#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:44.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:28:44.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:28:44.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:28:44.20#ibcon#enter wrdev, iclass 31, count 2 2006.285.08:28:44.20#ibcon#first serial, iclass 31, count 2 2006.285.08:28:44.20#ibcon#enter sib2, iclass 31, count 2 2006.285.08:28:44.20#ibcon#flushed, iclass 31, count 2 2006.285.08:28:44.20#ibcon#about to write, iclass 31, count 2 2006.285.08:28:44.20#ibcon#wrote, iclass 31, count 2 2006.285.08:28:44.20#ibcon#about to read 3, iclass 31, count 2 2006.285.08:28:44.22#ibcon#read 3, iclass 31, count 2 2006.285.08:28:44.22#ibcon#about to read 4, iclass 31, count 2 2006.285.08:28:44.22#ibcon#read 4, iclass 31, count 2 2006.285.08:28:44.22#ibcon#about to read 5, iclass 31, count 2 2006.285.08:28:44.22#ibcon#read 5, iclass 31, count 2 2006.285.08:28:44.22#ibcon#about to read 6, iclass 31, count 2 2006.285.08:28:44.22#ibcon#read 6, iclass 31, count 2 2006.285.08:28:44.22#ibcon#end of sib2, iclass 31, count 2 2006.285.08:28:44.22#ibcon#*mode == 0, iclass 31, count 2 2006.285.08:28:44.22#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.08:28:44.22#ibcon#[25=AT01-07\r\n] 2006.285.08:28:44.22#ibcon#*before write, iclass 31, count 2 2006.285.08:28:44.22#ibcon#enter sib2, iclass 31, count 2 2006.285.08:28:44.22#ibcon#flushed, iclass 31, count 2 2006.285.08:28:44.22#ibcon#about to write, iclass 31, count 2 2006.285.08:28:44.22#ibcon#wrote, iclass 31, count 2 2006.285.08:28:44.22#ibcon#about to read 3, iclass 31, count 2 2006.285.08:28:44.25#ibcon#read 3, iclass 31, count 2 2006.285.08:28:44.25#ibcon#about to read 4, iclass 31, count 2 2006.285.08:28:44.25#ibcon#read 4, iclass 31, count 2 2006.285.08:28:44.25#ibcon#about to read 5, iclass 31, count 2 2006.285.08:28:44.25#ibcon#read 5, iclass 31, count 2 2006.285.08:28:44.25#ibcon#about to read 6, iclass 31, count 2 2006.285.08:28:44.25#ibcon#read 6, iclass 31, count 2 2006.285.08:28:44.25#ibcon#end of sib2, iclass 31, count 2 2006.285.08:28:44.25#ibcon#*after write, iclass 31, count 2 2006.285.08:28:44.25#ibcon#*before return 0, iclass 31, count 2 2006.285.08:28:44.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:28:44.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:28:44.25#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.08:28:44.25#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:44.25#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:28:44.37#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:28:44.37#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:28:44.37#ibcon#enter wrdev, iclass 31, count 0 2006.285.08:28:44.37#ibcon#first serial, iclass 31, count 0 2006.285.08:28:44.37#ibcon#enter sib2, iclass 31, count 0 2006.285.08:28:44.37#ibcon#flushed, iclass 31, count 0 2006.285.08:28:44.37#ibcon#about to write, iclass 31, count 0 2006.285.08:28:44.37#ibcon#wrote, iclass 31, count 0 2006.285.08:28:44.37#ibcon#about to read 3, iclass 31, count 0 2006.285.08:28:44.39#ibcon#read 3, iclass 31, count 0 2006.285.08:28:44.39#ibcon#about to read 4, iclass 31, count 0 2006.285.08:28:44.39#ibcon#read 4, iclass 31, count 0 2006.285.08:28:44.39#ibcon#about to read 5, iclass 31, count 0 2006.285.08:28:44.39#ibcon#read 5, iclass 31, count 0 2006.285.08:28:44.39#ibcon#about to read 6, iclass 31, count 0 2006.285.08:28:44.39#ibcon#read 6, iclass 31, count 0 2006.285.08:28:44.39#ibcon#end of sib2, iclass 31, count 0 2006.285.08:28:44.39#ibcon#*mode == 0, iclass 31, count 0 2006.285.08:28:44.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.08:28:44.39#ibcon#[25=USB\r\n] 2006.285.08:28:44.39#ibcon#*before write, iclass 31, count 0 2006.285.08:28:44.39#ibcon#enter sib2, iclass 31, count 0 2006.285.08:28:44.39#ibcon#flushed, iclass 31, count 0 2006.285.08:28:44.39#ibcon#about to write, iclass 31, count 0 2006.285.08:28:44.39#ibcon#wrote, iclass 31, count 0 2006.285.08:28:44.39#ibcon#about to read 3, iclass 31, count 0 2006.285.08:28:44.42#ibcon#read 3, iclass 31, count 0 2006.285.08:28:44.42#ibcon#about to read 4, iclass 31, count 0 2006.285.08:28:44.42#ibcon#read 4, iclass 31, count 0 2006.285.08:28:44.42#ibcon#about to read 5, iclass 31, count 0 2006.285.08:28:44.42#ibcon#read 5, iclass 31, count 0 2006.285.08:28:44.42#ibcon#about to read 6, iclass 31, count 0 2006.285.08:28:44.42#ibcon#read 6, iclass 31, count 0 2006.285.08:28:44.42#ibcon#end of sib2, iclass 31, count 0 2006.285.08:28:44.42#ibcon#*after write, iclass 31, count 0 2006.285.08:28:44.42#ibcon#*before return 0, iclass 31, count 0 2006.285.08:28:44.42#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:28:44.42#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:28:44.42#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.08:28:44.42#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.08:28:44.42$vck44/valo=2,534.99 2006.285.08:28:44.42#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.08:28:44.42#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.08:28:44.42#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:44.42#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:28:44.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:28:44.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:28:44.42#ibcon#enter wrdev, iclass 33, count 0 2006.285.08:28:44.42#ibcon#first serial, iclass 33, count 0 2006.285.08:28:44.42#ibcon#enter sib2, iclass 33, count 0 2006.285.08:28:44.42#ibcon#flushed, iclass 33, count 0 2006.285.08:28:44.42#ibcon#about to write, iclass 33, count 0 2006.285.08:28:44.42#ibcon#wrote, iclass 33, count 0 2006.285.08:28:44.42#ibcon#about to read 3, iclass 33, count 0 2006.285.08:28:44.44#ibcon#read 3, iclass 33, count 0 2006.285.08:28:44.44#ibcon#about to read 4, iclass 33, count 0 2006.285.08:28:44.44#ibcon#read 4, iclass 33, count 0 2006.285.08:28:44.44#ibcon#about to read 5, iclass 33, count 0 2006.285.08:28:44.44#ibcon#read 5, iclass 33, count 0 2006.285.08:28:44.44#ibcon#about to read 6, iclass 33, count 0 2006.285.08:28:44.44#ibcon#read 6, iclass 33, count 0 2006.285.08:28:44.44#ibcon#end of sib2, iclass 33, count 0 2006.285.08:28:44.44#ibcon#*mode == 0, iclass 33, count 0 2006.285.08:28:44.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.08:28:44.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:28:44.44#ibcon#*before write, iclass 33, count 0 2006.285.08:28:44.44#ibcon#enter sib2, iclass 33, count 0 2006.285.08:28:44.44#ibcon#flushed, iclass 33, count 0 2006.285.08:28:44.44#ibcon#about to write, iclass 33, count 0 2006.285.08:28:44.44#ibcon#wrote, iclass 33, count 0 2006.285.08:28:44.44#ibcon#about to read 3, iclass 33, count 0 2006.285.08:28:44.48#ibcon#read 3, iclass 33, count 0 2006.285.08:28:44.48#ibcon#about to read 4, iclass 33, count 0 2006.285.08:28:44.48#ibcon#read 4, iclass 33, count 0 2006.285.08:28:44.48#ibcon#about to read 5, iclass 33, count 0 2006.285.08:28:44.48#ibcon#read 5, iclass 33, count 0 2006.285.08:28:44.48#ibcon#about to read 6, iclass 33, count 0 2006.285.08:28:44.48#ibcon#read 6, iclass 33, count 0 2006.285.08:28:44.48#ibcon#end of sib2, iclass 33, count 0 2006.285.08:28:44.48#ibcon#*after write, iclass 33, count 0 2006.285.08:28:44.48#ibcon#*before return 0, iclass 33, count 0 2006.285.08:28:44.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:28:44.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:28:44.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.08:28:44.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.08:28:44.48$vck44/va=2,6 2006.285.08:28:44.48#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.08:28:44.48#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.08:28:44.48#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:44.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:28:44.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:28:44.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:28:44.54#ibcon#enter wrdev, iclass 35, count 2 2006.285.08:28:44.54#ibcon#first serial, iclass 35, count 2 2006.285.08:28:44.54#ibcon#enter sib2, iclass 35, count 2 2006.285.08:28:44.54#ibcon#flushed, iclass 35, count 2 2006.285.08:28:44.54#ibcon#about to write, iclass 35, count 2 2006.285.08:28:44.54#ibcon#wrote, iclass 35, count 2 2006.285.08:28:44.54#ibcon#about to read 3, iclass 35, count 2 2006.285.08:28:44.56#ibcon#read 3, iclass 35, count 2 2006.285.08:28:44.56#ibcon#about to read 4, iclass 35, count 2 2006.285.08:28:44.56#ibcon#read 4, iclass 35, count 2 2006.285.08:28:44.56#ibcon#about to read 5, iclass 35, count 2 2006.285.08:28:44.56#ibcon#read 5, iclass 35, count 2 2006.285.08:28:44.56#ibcon#about to read 6, iclass 35, count 2 2006.285.08:28:44.56#ibcon#read 6, iclass 35, count 2 2006.285.08:28:44.56#ibcon#end of sib2, iclass 35, count 2 2006.285.08:28:44.56#ibcon#*mode == 0, iclass 35, count 2 2006.285.08:28:44.56#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.08:28:44.56#ibcon#[25=AT02-06\r\n] 2006.285.08:28:44.56#ibcon#*before write, iclass 35, count 2 2006.285.08:28:44.56#ibcon#enter sib2, iclass 35, count 2 2006.285.08:28:44.56#ibcon#flushed, iclass 35, count 2 2006.285.08:28:44.56#ibcon#about to write, iclass 35, count 2 2006.285.08:28:44.56#ibcon#wrote, iclass 35, count 2 2006.285.08:28:44.56#ibcon#about to read 3, iclass 35, count 2 2006.285.08:28:44.59#ibcon#read 3, iclass 35, count 2 2006.285.08:28:44.59#ibcon#about to read 4, iclass 35, count 2 2006.285.08:28:44.59#ibcon#read 4, iclass 35, count 2 2006.285.08:28:44.59#ibcon#about to read 5, iclass 35, count 2 2006.285.08:28:44.59#ibcon#read 5, iclass 35, count 2 2006.285.08:28:44.59#ibcon#about to read 6, iclass 35, count 2 2006.285.08:28:44.59#ibcon#read 6, iclass 35, count 2 2006.285.08:28:44.59#ibcon#end of sib2, iclass 35, count 2 2006.285.08:28:44.59#ibcon#*after write, iclass 35, count 2 2006.285.08:28:44.59#ibcon#*before return 0, iclass 35, count 2 2006.285.08:28:44.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:28:44.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:28:44.59#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.08:28:44.59#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:44.59#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:28:44.71#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:28:44.71#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:28:44.71#ibcon#enter wrdev, iclass 35, count 0 2006.285.08:28:44.71#ibcon#first serial, iclass 35, count 0 2006.285.08:28:44.71#ibcon#enter sib2, iclass 35, count 0 2006.285.08:28:44.71#ibcon#flushed, iclass 35, count 0 2006.285.08:28:44.71#ibcon#about to write, iclass 35, count 0 2006.285.08:28:44.71#ibcon#wrote, iclass 35, count 0 2006.285.08:28:44.71#ibcon#about to read 3, iclass 35, count 0 2006.285.08:28:44.73#ibcon#read 3, iclass 35, count 0 2006.285.08:28:44.73#ibcon#about to read 4, iclass 35, count 0 2006.285.08:28:44.73#ibcon#read 4, iclass 35, count 0 2006.285.08:28:44.73#ibcon#about to read 5, iclass 35, count 0 2006.285.08:28:44.73#ibcon#read 5, iclass 35, count 0 2006.285.08:28:44.73#ibcon#about to read 6, iclass 35, count 0 2006.285.08:28:44.73#ibcon#read 6, iclass 35, count 0 2006.285.08:28:44.73#ibcon#end of sib2, iclass 35, count 0 2006.285.08:28:44.73#ibcon#*mode == 0, iclass 35, count 0 2006.285.08:28:44.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.08:28:44.73#ibcon#[25=USB\r\n] 2006.285.08:28:44.73#ibcon#*before write, iclass 35, count 0 2006.285.08:28:44.73#ibcon#enter sib2, iclass 35, count 0 2006.285.08:28:44.73#ibcon#flushed, iclass 35, count 0 2006.285.08:28:44.73#ibcon#about to write, iclass 35, count 0 2006.285.08:28:44.73#ibcon#wrote, iclass 35, count 0 2006.285.08:28:44.73#ibcon#about to read 3, iclass 35, count 0 2006.285.08:28:44.76#ibcon#read 3, iclass 35, count 0 2006.285.08:28:44.76#ibcon#about to read 4, iclass 35, count 0 2006.285.08:28:44.76#ibcon#read 4, iclass 35, count 0 2006.285.08:28:44.76#ibcon#about to read 5, iclass 35, count 0 2006.285.08:28:44.76#ibcon#read 5, iclass 35, count 0 2006.285.08:28:44.76#ibcon#about to read 6, iclass 35, count 0 2006.285.08:28:44.76#ibcon#read 6, iclass 35, count 0 2006.285.08:28:44.76#ibcon#end of sib2, iclass 35, count 0 2006.285.08:28:44.76#ibcon#*after write, iclass 35, count 0 2006.285.08:28:44.76#ibcon#*before return 0, iclass 35, count 0 2006.285.08:28:44.76#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:28:44.76#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:28:44.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.08:28:44.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.08:28:44.76$vck44/valo=3,564.99 2006.285.08:28:44.76#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.08:28:44.76#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.08:28:44.76#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:44.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:28:44.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:28:44.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:28:44.76#ibcon#enter wrdev, iclass 37, count 0 2006.285.08:28:44.76#ibcon#first serial, iclass 37, count 0 2006.285.08:28:44.76#ibcon#enter sib2, iclass 37, count 0 2006.285.08:28:44.76#ibcon#flushed, iclass 37, count 0 2006.285.08:28:44.76#ibcon#about to write, iclass 37, count 0 2006.285.08:28:44.76#ibcon#wrote, iclass 37, count 0 2006.285.08:28:44.76#ibcon#about to read 3, iclass 37, count 0 2006.285.08:28:44.78#ibcon#read 3, iclass 37, count 0 2006.285.08:28:44.78#ibcon#about to read 4, iclass 37, count 0 2006.285.08:28:44.78#ibcon#read 4, iclass 37, count 0 2006.285.08:28:44.78#ibcon#about to read 5, iclass 37, count 0 2006.285.08:28:44.78#ibcon#read 5, iclass 37, count 0 2006.285.08:28:44.78#ibcon#about to read 6, iclass 37, count 0 2006.285.08:28:44.78#ibcon#read 6, iclass 37, count 0 2006.285.08:28:44.78#ibcon#end of sib2, iclass 37, count 0 2006.285.08:28:44.78#ibcon#*mode == 0, iclass 37, count 0 2006.285.08:28:44.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.08:28:44.78#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:28:44.78#ibcon#*before write, iclass 37, count 0 2006.285.08:28:44.78#ibcon#enter sib2, iclass 37, count 0 2006.285.08:28:44.78#ibcon#flushed, iclass 37, count 0 2006.285.08:28:44.78#ibcon#about to write, iclass 37, count 0 2006.285.08:28:44.78#ibcon#wrote, iclass 37, count 0 2006.285.08:28:44.78#ibcon#about to read 3, iclass 37, count 0 2006.285.08:28:44.82#ibcon#read 3, iclass 37, count 0 2006.285.08:28:44.82#ibcon#about to read 4, iclass 37, count 0 2006.285.08:28:44.82#ibcon#read 4, iclass 37, count 0 2006.285.08:28:44.82#ibcon#about to read 5, iclass 37, count 0 2006.285.08:28:44.82#ibcon#read 5, iclass 37, count 0 2006.285.08:28:44.82#ibcon#about to read 6, iclass 37, count 0 2006.285.08:28:44.82#ibcon#read 6, iclass 37, count 0 2006.285.08:28:44.82#ibcon#end of sib2, iclass 37, count 0 2006.285.08:28:44.82#ibcon#*after write, iclass 37, count 0 2006.285.08:28:44.82#ibcon#*before return 0, iclass 37, count 0 2006.285.08:28:44.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:28:44.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:28:44.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.08:28:44.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.08:28:44.82$vck44/va=3,7 2006.285.08:28:44.82#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.08:28:44.82#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.08:28:44.82#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:44.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:28:44.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:28:44.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:28:44.88#ibcon#enter wrdev, iclass 39, count 2 2006.285.08:28:44.88#ibcon#first serial, iclass 39, count 2 2006.285.08:28:44.88#ibcon#enter sib2, iclass 39, count 2 2006.285.08:28:44.88#ibcon#flushed, iclass 39, count 2 2006.285.08:28:44.88#ibcon#about to write, iclass 39, count 2 2006.285.08:28:44.88#ibcon#wrote, iclass 39, count 2 2006.285.08:28:44.88#ibcon#about to read 3, iclass 39, count 2 2006.285.08:28:44.90#ibcon#read 3, iclass 39, count 2 2006.285.08:28:44.90#ibcon#about to read 4, iclass 39, count 2 2006.285.08:28:44.90#ibcon#read 4, iclass 39, count 2 2006.285.08:28:44.90#ibcon#about to read 5, iclass 39, count 2 2006.285.08:28:44.90#ibcon#read 5, iclass 39, count 2 2006.285.08:28:44.90#ibcon#about to read 6, iclass 39, count 2 2006.285.08:28:44.90#ibcon#read 6, iclass 39, count 2 2006.285.08:28:44.90#ibcon#end of sib2, iclass 39, count 2 2006.285.08:28:44.90#ibcon#*mode == 0, iclass 39, count 2 2006.285.08:28:44.90#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.08:28:44.90#ibcon#[25=AT03-07\r\n] 2006.285.08:28:44.90#ibcon#*before write, iclass 39, count 2 2006.285.08:28:44.90#ibcon#enter sib2, iclass 39, count 2 2006.285.08:28:44.90#ibcon#flushed, iclass 39, count 2 2006.285.08:28:44.90#ibcon#about to write, iclass 39, count 2 2006.285.08:28:44.90#ibcon#wrote, iclass 39, count 2 2006.285.08:28:44.90#ibcon#about to read 3, iclass 39, count 2 2006.285.08:28:44.93#ibcon#read 3, iclass 39, count 2 2006.285.08:28:44.93#ibcon#about to read 4, iclass 39, count 2 2006.285.08:28:44.93#ibcon#read 4, iclass 39, count 2 2006.285.08:28:44.93#ibcon#about to read 5, iclass 39, count 2 2006.285.08:28:44.93#ibcon#read 5, iclass 39, count 2 2006.285.08:28:44.93#ibcon#about to read 6, iclass 39, count 2 2006.285.08:28:44.93#ibcon#read 6, iclass 39, count 2 2006.285.08:28:44.93#ibcon#end of sib2, iclass 39, count 2 2006.285.08:28:44.93#ibcon#*after write, iclass 39, count 2 2006.285.08:28:44.93#ibcon#*before return 0, iclass 39, count 2 2006.285.08:28:44.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:28:44.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:28:44.93#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.08:28:44.93#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:44.93#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:28:45.05#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:28:45.05#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:28:45.05#ibcon#enter wrdev, iclass 39, count 0 2006.285.08:28:45.05#ibcon#first serial, iclass 39, count 0 2006.285.08:28:45.05#ibcon#enter sib2, iclass 39, count 0 2006.285.08:28:45.05#ibcon#flushed, iclass 39, count 0 2006.285.08:28:45.05#ibcon#about to write, iclass 39, count 0 2006.285.08:28:45.05#ibcon#wrote, iclass 39, count 0 2006.285.08:28:45.05#ibcon#about to read 3, iclass 39, count 0 2006.285.08:28:45.07#ibcon#read 3, iclass 39, count 0 2006.285.08:28:45.07#ibcon#about to read 4, iclass 39, count 0 2006.285.08:28:45.07#ibcon#read 4, iclass 39, count 0 2006.285.08:28:45.07#ibcon#about to read 5, iclass 39, count 0 2006.285.08:28:45.07#ibcon#read 5, iclass 39, count 0 2006.285.08:28:45.07#ibcon#about to read 6, iclass 39, count 0 2006.285.08:28:45.07#ibcon#read 6, iclass 39, count 0 2006.285.08:28:45.07#ibcon#end of sib2, iclass 39, count 0 2006.285.08:28:45.07#ibcon#*mode == 0, iclass 39, count 0 2006.285.08:28:45.07#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.08:28:45.07#ibcon#[25=USB\r\n] 2006.285.08:28:45.07#ibcon#*before write, iclass 39, count 0 2006.285.08:28:45.07#ibcon#enter sib2, iclass 39, count 0 2006.285.08:28:45.07#ibcon#flushed, iclass 39, count 0 2006.285.08:28:45.07#ibcon#about to write, iclass 39, count 0 2006.285.08:28:45.07#ibcon#wrote, iclass 39, count 0 2006.285.08:28:45.07#ibcon#about to read 3, iclass 39, count 0 2006.285.08:28:45.10#ibcon#read 3, iclass 39, count 0 2006.285.08:28:45.10#ibcon#about to read 4, iclass 39, count 0 2006.285.08:28:45.10#ibcon#read 4, iclass 39, count 0 2006.285.08:28:45.10#ibcon#about to read 5, iclass 39, count 0 2006.285.08:28:45.10#ibcon#read 5, iclass 39, count 0 2006.285.08:28:45.10#ibcon#about to read 6, iclass 39, count 0 2006.285.08:28:45.10#ibcon#read 6, iclass 39, count 0 2006.285.08:28:45.10#ibcon#end of sib2, iclass 39, count 0 2006.285.08:28:45.10#ibcon#*after write, iclass 39, count 0 2006.285.08:28:45.10#ibcon#*before return 0, iclass 39, count 0 2006.285.08:28:45.10#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:28:45.10#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:28:45.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.08:28:45.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.08:28:45.10$vck44/valo=4,624.99 2006.285.08:28:45.10#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.08:28:45.10#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.08:28:45.10#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:45.10#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:28:45.10#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:28:45.10#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:28:45.10#ibcon#enter wrdev, iclass 3, count 0 2006.285.08:28:45.10#ibcon#first serial, iclass 3, count 0 2006.285.08:28:45.10#ibcon#enter sib2, iclass 3, count 0 2006.285.08:28:45.10#ibcon#flushed, iclass 3, count 0 2006.285.08:28:45.10#ibcon#about to write, iclass 3, count 0 2006.285.08:28:45.10#ibcon#wrote, iclass 3, count 0 2006.285.08:28:45.10#ibcon#about to read 3, iclass 3, count 0 2006.285.08:28:45.12#ibcon#read 3, iclass 3, count 0 2006.285.08:28:45.12#ibcon#about to read 4, iclass 3, count 0 2006.285.08:28:45.12#ibcon#read 4, iclass 3, count 0 2006.285.08:28:45.12#ibcon#about to read 5, iclass 3, count 0 2006.285.08:28:45.12#ibcon#read 5, iclass 3, count 0 2006.285.08:28:45.12#ibcon#about to read 6, iclass 3, count 0 2006.285.08:28:45.12#ibcon#read 6, iclass 3, count 0 2006.285.08:28:45.12#ibcon#end of sib2, iclass 3, count 0 2006.285.08:28:45.12#ibcon#*mode == 0, iclass 3, count 0 2006.285.08:28:45.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.08:28:45.12#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:28:45.12#ibcon#*before write, iclass 3, count 0 2006.285.08:28:45.12#ibcon#enter sib2, iclass 3, count 0 2006.285.08:28:45.12#ibcon#flushed, iclass 3, count 0 2006.285.08:28:45.12#ibcon#about to write, iclass 3, count 0 2006.285.08:28:45.12#ibcon#wrote, iclass 3, count 0 2006.285.08:28:45.12#ibcon#about to read 3, iclass 3, count 0 2006.285.08:28:45.16#ibcon#read 3, iclass 3, count 0 2006.285.08:28:45.16#ibcon#about to read 4, iclass 3, count 0 2006.285.08:28:45.16#ibcon#read 4, iclass 3, count 0 2006.285.08:28:45.16#ibcon#about to read 5, iclass 3, count 0 2006.285.08:28:45.16#ibcon#read 5, iclass 3, count 0 2006.285.08:28:45.16#ibcon#about to read 6, iclass 3, count 0 2006.285.08:28:45.16#ibcon#read 6, iclass 3, count 0 2006.285.08:28:45.16#ibcon#end of sib2, iclass 3, count 0 2006.285.08:28:45.16#ibcon#*after write, iclass 3, count 0 2006.285.08:28:45.16#ibcon#*before return 0, iclass 3, count 0 2006.285.08:28:45.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:28:45.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:28:45.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.08:28:45.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.08:28:45.16$vck44/va=4,6 2006.285.08:28:45.16#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.08:28:45.16#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.08:28:45.16#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:45.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:28:45.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:28:45.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:28:45.22#ibcon#enter wrdev, iclass 5, count 2 2006.285.08:28:45.22#ibcon#first serial, iclass 5, count 2 2006.285.08:28:45.22#ibcon#enter sib2, iclass 5, count 2 2006.285.08:28:45.22#ibcon#flushed, iclass 5, count 2 2006.285.08:28:45.22#ibcon#about to write, iclass 5, count 2 2006.285.08:28:45.22#ibcon#wrote, iclass 5, count 2 2006.285.08:28:45.22#ibcon#about to read 3, iclass 5, count 2 2006.285.08:28:45.24#ibcon#read 3, iclass 5, count 2 2006.285.08:28:45.24#ibcon#about to read 4, iclass 5, count 2 2006.285.08:28:45.24#ibcon#read 4, iclass 5, count 2 2006.285.08:28:45.24#ibcon#about to read 5, iclass 5, count 2 2006.285.08:28:45.24#ibcon#read 5, iclass 5, count 2 2006.285.08:28:45.24#ibcon#about to read 6, iclass 5, count 2 2006.285.08:28:45.24#ibcon#read 6, iclass 5, count 2 2006.285.08:28:45.24#ibcon#end of sib2, iclass 5, count 2 2006.285.08:28:45.24#ibcon#*mode == 0, iclass 5, count 2 2006.285.08:28:45.24#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.08:28:45.24#ibcon#[25=AT04-06\r\n] 2006.285.08:28:45.24#ibcon#*before write, iclass 5, count 2 2006.285.08:28:45.24#ibcon#enter sib2, iclass 5, count 2 2006.285.08:28:45.24#ibcon#flushed, iclass 5, count 2 2006.285.08:28:45.24#ibcon#about to write, iclass 5, count 2 2006.285.08:28:45.24#ibcon#wrote, iclass 5, count 2 2006.285.08:28:45.24#ibcon#about to read 3, iclass 5, count 2 2006.285.08:28:45.27#ibcon#read 3, iclass 5, count 2 2006.285.08:28:45.27#ibcon#about to read 4, iclass 5, count 2 2006.285.08:28:45.27#ibcon#read 4, iclass 5, count 2 2006.285.08:28:45.27#ibcon#about to read 5, iclass 5, count 2 2006.285.08:28:45.27#ibcon#read 5, iclass 5, count 2 2006.285.08:28:45.27#ibcon#about to read 6, iclass 5, count 2 2006.285.08:28:45.27#ibcon#read 6, iclass 5, count 2 2006.285.08:28:45.27#ibcon#end of sib2, iclass 5, count 2 2006.285.08:28:45.27#ibcon#*after write, iclass 5, count 2 2006.285.08:28:45.27#ibcon#*before return 0, iclass 5, count 2 2006.285.08:28:45.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:28:45.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:28:45.27#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.08:28:45.27#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:45.27#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:28:45.39#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:28:45.39#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:28:45.39#ibcon#enter wrdev, iclass 5, count 0 2006.285.08:28:45.39#ibcon#first serial, iclass 5, count 0 2006.285.08:28:45.39#ibcon#enter sib2, iclass 5, count 0 2006.285.08:28:45.39#ibcon#flushed, iclass 5, count 0 2006.285.08:28:45.39#ibcon#about to write, iclass 5, count 0 2006.285.08:28:45.39#ibcon#wrote, iclass 5, count 0 2006.285.08:28:45.39#ibcon#about to read 3, iclass 5, count 0 2006.285.08:28:45.41#ibcon#read 3, iclass 5, count 0 2006.285.08:28:45.41#ibcon#about to read 4, iclass 5, count 0 2006.285.08:28:45.41#ibcon#read 4, iclass 5, count 0 2006.285.08:28:45.41#ibcon#about to read 5, iclass 5, count 0 2006.285.08:28:45.41#ibcon#read 5, iclass 5, count 0 2006.285.08:28:45.41#ibcon#about to read 6, iclass 5, count 0 2006.285.08:28:45.41#ibcon#read 6, iclass 5, count 0 2006.285.08:28:45.41#ibcon#end of sib2, iclass 5, count 0 2006.285.08:28:45.41#ibcon#*mode == 0, iclass 5, count 0 2006.285.08:28:45.41#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.08:28:45.41#ibcon#[25=USB\r\n] 2006.285.08:28:45.41#ibcon#*before write, iclass 5, count 0 2006.285.08:28:45.41#ibcon#enter sib2, iclass 5, count 0 2006.285.08:28:45.41#ibcon#flushed, iclass 5, count 0 2006.285.08:28:45.41#ibcon#about to write, iclass 5, count 0 2006.285.08:28:45.41#ibcon#wrote, iclass 5, count 0 2006.285.08:28:45.41#ibcon#about to read 3, iclass 5, count 0 2006.285.08:28:45.44#ibcon#read 3, iclass 5, count 0 2006.285.08:28:45.44#ibcon#about to read 4, iclass 5, count 0 2006.285.08:28:45.44#ibcon#read 4, iclass 5, count 0 2006.285.08:28:45.44#ibcon#about to read 5, iclass 5, count 0 2006.285.08:28:45.44#ibcon#read 5, iclass 5, count 0 2006.285.08:28:45.44#ibcon#about to read 6, iclass 5, count 0 2006.285.08:28:45.44#ibcon#read 6, iclass 5, count 0 2006.285.08:28:45.44#ibcon#end of sib2, iclass 5, count 0 2006.285.08:28:45.44#ibcon#*after write, iclass 5, count 0 2006.285.08:28:45.44#ibcon#*before return 0, iclass 5, count 0 2006.285.08:28:45.44#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:28:45.44#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:28:45.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.08:28:45.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.08:28:45.44$vck44/valo=5,734.99 2006.285.08:28:45.44#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.08:28:45.44#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.08:28:45.44#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:45.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:28:45.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:28:45.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:28:45.44#ibcon#enter wrdev, iclass 7, count 0 2006.285.08:28:45.44#ibcon#first serial, iclass 7, count 0 2006.285.08:28:45.44#ibcon#enter sib2, iclass 7, count 0 2006.285.08:28:45.44#ibcon#flushed, iclass 7, count 0 2006.285.08:28:45.44#ibcon#about to write, iclass 7, count 0 2006.285.08:28:45.44#ibcon#wrote, iclass 7, count 0 2006.285.08:28:45.44#ibcon#about to read 3, iclass 7, count 0 2006.285.08:28:45.46#ibcon#read 3, iclass 7, count 0 2006.285.08:28:45.46#ibcon#about to read 4, iclass 7, count 0 2006.285.08:28:45.46#ibcon#read 4, iclass 7, count 0 2006.285.08:28:45.46#ibcon#about to read 5, iclass 7, count 0 2006.285.08:28:45.46#ibcon#read 5, iclass 7, count 0 2006.285.08:28:45.46#ibcon#about to read 6, iclass 7, count 0 2006.285.08:28:45.46#ibcon#read 6, iclass 7, count 0 2006.285.08:28:45.46#ibcon#end of sib2, iclass 7, count 0 2006.285.08:28:45.46#ibcon#*mode == 0, iclass 7, count 0 2006.285.08:28:45.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.08:28:45.46#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:28:45.46#ibcon#*before write, iclass 7, count 0 2006.285.08:28:45.46#ibcon#enter sib2, iclass 7, count 0 2006.285.08:28:45.46#ibcon#flushed, iclass 7, count 0 2006.285.08:28:45.46#ibcon#about to write, iclass 7, count 0 2006.285.08:28:45.46#ibcon#wrote, iclass 7, count 0 2006.285.08:28:45.46#ibcon#about to read 3, iclass 7, count 0 2006.285.08:28:45.50#ibcon#read 3, iclass 7, count 0 2006.285.08:28:45.50#ibcon#about to read 4, iclass 7, count 0 2006.285.08:28:45.50#ibcon#read 4, iclass 7, count 0 2006.285.08:28:45.50#ibcon#about to read 5, iclass 7, count 0 2006.285.08:28:45.50#ibcon#read 5, iclass 7, count 0 2006.285.08:28:45.50#ibcon#about to read 6, iclass 7, count 0 2006.285.08:28:45.50#ibcon#read 6, iclass 7, count 0 2006.285.08:28:45.50#ibcon#end of sib2, iclass 7, count 0 2006.285.08:28:45.50#ibcon#*after write, iclass 7, count 0 2006.285.08:28:45.50#ibcon#*before return 0, iclass 7, count 0 2006.285.08:28:45.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:28:45.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:28:45.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.08:28:45.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.08:28:45.50$vck44/va=5,3 2006.285.08:28:45.50#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.08:28:45.50#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.08:28:45.50#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:45.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:28:45.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:28:45.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:28:45.56#ibcon#enter wrdev, iclass 11, count 2 2006.285.08:28:45.56#ibcon#first serial, iclass 11, count 2 2006.285.08:28:45.56#ibcon#enter sib2, iclass 11, count 2 2006.285.08:28:45.56#ibcon#flushed, iclass 11, count 2 2006.285.08:28:45.56#ibcon#about to write, iclass 11, count 2 2006.285.08:28:45.56#ibcon#wrote, iclass 11, count 2 2006.285.08:28:45.56#ibcon#about to read 3, iclass 11, count 2 2006.285.08:28:45.58#ibcon#read 3, iclass 11, count 2 2006.285.08:28:45.58#ibcon#about to read 4, iclass 11, count 2 2006.285.08:28:45.58#ibcon#read 4, iclass 11, count 2 2006.285.08:28:45.58#ibcon#about to read 5, iclass 11, count 2 2006.285.08:28:45.58#ibcon#read 5, iclass 11, count 2 2006.285.08:28:45.58#ibcon#about to read 6, iclass 11, count 2 2006.285.08:28:45.58#ibcon#read 6, iclass 11, count 2 2006.285.08:28:45.58#ibcon#end of sib2, iclass 11, count 2 2006.285.08:28:45.58#ibcon#*mode == 0, iclass 11, count 2 2006.285.08:28:45.58#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.08:28:45.58#ibcon#[25=AT05-03\r\n] 2006.285.08:28:45.58#ibcon#*before write, iclass 11, count 2 2006.285.08:28:45.58#ibcon#enter sib2, iclass 11, count 2 2006.285.08:28:45.58#ibcon#flushed, iclass 11, count 2 2006.285.08:28:45.58#ibcon#about to write, iclass 11, count 2 2006.285.08:28:45.58#ibcon#wrote, iclass 11, count 2 2006.285.08:28:45.58#ibcon#about to read 3, iclass 11, count 2 2006.285.08:28:45.61#ibcon#read 3, iclass 11, count 2 2006.285.08:28:45.61#ibcon#about to read 4, iclass 11, count 2 2006.285.08:28:45.61#ibcon#read 4, iclass 11, count 2 2006.285.08:28:45.61#ibcon#about to read 5, iclass 11, count 2 2006.285.08:28:45.61#ibcon#read 5, iclass 11, count 2 2006.285.08:28:45.61#ibcon#about to read 6, iclass 11, count 2 2006.285.08:28:45.61#ibcon#read 6, iclass 11, count 2 2006.285.08:28:45.61#ibcon#end of sib2, iclass 11, count 2 2006.285.08:28:45.61#ibcon#*after write, iclass 11, count 2 2006.285.08:28:45.61#ibcon#*before return 0, iclass 11, count 2 2006.285.08:28:45.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:28:45.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:28:45.61#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.08:28:45.61#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:45.61#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:28:45.73#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:28:45.73#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:28:45.73#ibcon#enter wrdev, iclass 11, count 0 2006.285.08:28:45.73#ibcon#first serial, iclass 11, count 0 2006.285.08:28:45.73#ibcon#enter sib2, iclass 11, count 0 2006.285.08:28:45.73#ibcon#flushed, iclass 11, count 0 2006.285.08:28:45.73#ibcon#about to write, iclass 11, count 0 2006.285.08:28:45.73#ibcon#wrote, iclass 11, count 0 2006.285.08:28:45.73#ibcon#about to read 3, iclass 11, count 0 2006.285.08:28:45.75#ibcon#read 3, iclass 11, count 0 2006.285.08:28:45.75#ibcon#about to read 4, iclass 11, count 0 2006.285.08:28:45.75#ibcon#read 4, iclass 11, count 0 2006.285.08:28:45.75#ibcon#about to read 5, iclass 11, count 0 2006.285.08:28:45.75#ibcon#read 5, iclass 11, count 0 2006.285.08:28:45.75#ibcon#about to read 6, iclass 11, count 0 2006.285.08:28:45.75#ibcon#read 6, iclass 11, count 0 2006.285.08:28:45.75#ibcon#end of sib2, iclass 11, count 0 2006.285.08:28:45.75#ibcon#*mode == 0, iclass 11, count 0 2006.285.08:28:45.75#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.08:28:45.75#ibcon#[25=USB\r\n] 2006.285.08:28:45.75#ibcon#*before write, iclass 11, count 0 2006.285.08:28:45.75#ibcon#enter sib2, iclass 11, count 0 2006.285.08:28:45.75#ibcon#flushed, iclass 11, count 0 2006.285.08:28:45.75#ibcon#about to write, iclass 11, count 0 2006.285.08:28:45.75#ibcon#wrote, iclass 11, count 0 2006.285.08:28:45.75#ibcon#about to read 3, iclass 11, count 0 2006.285.08:28:45.78#ibcon#read 3, iclass 11, count 0 2006.285.08:28:45.78#ibcon#about to read 4, iclass 11, count 0 2006.285.08:28:45.78#ibcon#read 4, iclass 11, count 0 2006.285.08:28:45.78#ibcon#about to read 5, iclass 11, count 0 2006.285.08:28:45.78#ibcon#read 5, iclass 11, count 0 2006.285.08:28:45.78#ibcon#about to read 6, iclass 11, count 0 2006.285.08:28:45.78#ibcon#read 6, iclass 11, count 0 2006.285.08:28:45.78#ibcon#end of sib2, iclass 11, count 0 2006.285.08:28:45.78#ibcon#*after write, iclass 11, count 0 2006.285.08:28:45.78#ibcon#*before return 0, iclass 11, count 0 2006.285.08:28:45.78#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:28:45.78#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:28:45.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.08:28:45.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.08:28:45.78$vck44/valo=6,814.99 2006.285.08:28:45.78#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.08:28:45.78#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.08:28:45.78#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:45.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:28:45.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:28:45.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:28:45.78#ibcon#enter wrdev, iclass 13, count 0 2006.285.08:28:45.78#ibcon#first serial, iclass 13, count 0 2006.285.08:28:45.78#ibcon#enter sib2, iclass 13, count 0 2006.285.08:28:45.78#ibcon#flushed, iclass 13, count 0 2006.285.08:28:45.78#ibcon#about to write, iclass 13, count 0 2006.285.08:28:45.78#ibcon#wrote, iclass 13, count 0 2006.285.08:28:45.78#ibcon#about to read 3, iclass 13, count 0 2006.285.08:28:45.80#ibcon#read 3, iclass 13, count 0 2006.285.08:28:45.80#ibcon#about to read 4, iclass 13, count 0 2006.285.08:28:45.80#ibcon#read 4, iclass 13, count 0 2006.285.08:28:45.80#ibcon#about to read 5, iclass 13, count 0 2006.285.08:28:45.80#ibcon#read 5, iclass 13, count 0 2006.285.08:28:45.80#ibcon#about to read 6, iclass 13, count 0 2006.285.08:28:45.80#ibcon#read 6, iclass 13, count 0 2006.285.08:28:45.80#ibcon#end of sib2, iclass 13, count 0 2006.285.08:28:45.80#ibcon#*mode == 0, iclass 13, count 0 2006.285.08:28:45.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.08:28:45.80#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:28:45.80#ibcon#*before write, iclass 13, count 0 2006.285.08:28:45.80#ibcon#enter sib2, iclass 13, count 0 2006.285.08:28:45.80#ibcon#flushed, iclass 13, count 0 2006.285.08:28:45.80#ibcon#about to write, iclass 13, count 0 2006.285.08:28:45.80#ibcon#wrote, iclass 13, count 0 2006.285.08:28:45.80#ibcon#about to read 3, iclass 13, count 0 2006.285.08:28:45.84#ibcon#read 3, iclass 13, count 0 2006.285.08:28:45.84#ibcon#about to read 4, iclass 13, count 0 2006.285.08:28:45.84#ibcon#read 4, iclass 13, count 0 2006.285.08:28:45.84#ibcon#about to read 5, iclass 13, count 0 2006.285.08:28:45.84#ibcon#read 5, iclass 13, count 0 2006.285.08:28:45.84#ibcon#about to read 6, iclass 13, count 0 2006.285.08:28:45.84#ibcon#read 6, iclass 13, count 0 2006.285.08:28:45.84#ibcon#end of sib2, iclass 13, count 0 2006.285.08:28:45.84#ibcon#*after write, iclass 13, count 0 2006.285.08:28:45.84#ibcon#*before return 0, iclass 13, count 0 2006.285.08:28:45.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:28:45.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:28:45.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.08:28:45.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.08:28:45.84$vck44/va=6,4 2006.285.08:28:45.84#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.08:28:45.84#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.08:28:45.84#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:45.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:28:45.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:28:45.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:28:45.90#ibcon#enter wrdev, iclass 15, count 2 2006.285.08:28:45.90#ibcon#first serial, iclass 15, count 2 2006.285.08:28:45.90#ibcon#enter sib2, iclass 15, count 2 2006.285.08:28:45.90#ibcon#flushed, iclass 15, count 2 2006.285.08:28:45.90#ibcon#about to write, iclass 15, count 2 2006.285.08:28:45.90#ibcon#wrote, iclass 15, count 2 2006.285.08:28:45.90#ibcon#about to read 3, iclass 15, count 2 2006.285.08:28:45.92#ibcon#read 3, iclass 15, count 2 2006.285.08:28:45.92#ibcon#about to read 4, iclass 15, count 2 2006.285.08:28:45.92#ibcon#read 4, iclass 15, count 2 2006.285.08:28:45.92#ibcon#about to read 5, iclass 15, count 2 2006.285.08:28:45.92#ibcon#read 5, iclass 15, count 2 2006.285.08:28:45.92#ibcon#about to read 6, iclass 15, count 2 2006.285.08:28:45.92#ibcon#read 6, iclass 15, count 2 2006.285.08:28:45.92#ibcon#end of sib2, iclass 15, count 2 2006.285.08:28:45.92#ibcon#*mode == 0, iclass 15, count 2 2006.285.08:28:45.92#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.08:28:45.92#ibcon#[25=AT06-04\r\n] 2006.285.08:28:45.92#ibcon#*before write, iclass 15, count 2 2006.285.08:28:45.92#ibcon#enter sib2, iclass 15, count 2 2006.285.08:28:45.92#ibcon#flushed, iclass 15, count 2 2006.285.08:28:45.92#ibcon#about to write, iclass 15, count 2 2006.285.08:28:45.92#ibcon#wrote, iclass 15, count 2 2006.285.08:28:45.92#ibcon#about to read 3, iclass 15, count 2 2006.285.08:28:45.95#ibcon#read 3, iclass 15, count 2 2006.285.08:28:45.95#ibcon#about to read 4, iclass 15, count 2 2006.285.08:28:45.95#ibcon#read 4, iclass 15, count 2 2006.285.08:28:45.95#ibcon#about to read 5, iclass 15, count 2 2006.285.08:28:45.95#ibcon#read 5, iclass 15, count 2 2006.285.08:28:45.95#ibcon#about to read 6, iclass 15, count 2 2006.285.08:28:45.95#ibcon#read 6, iclass 15, count 2 2006.285.08:28:45.95#ibcon#end of sib2, iclass 15, count 2 2006.285.08:28:45.95#ibcon#*after write, iclass 15, count 2 2006.285.08:28:45.95#ibcon#*before return 0, iclass 15, count 2 2006.285.08:28:45.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:28:45.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:28:45.95#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.08:28:45.95#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:45.95#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:28:46.07#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:28:46.07#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:28:46.07#ibcon#enter wrdev, iclass 15, count 0 2006.285.08:28:46.07#ibcon#first serial, iclass 15, count 0 2006.285.08:28:46.07#ibcon#enter sib2, iclass 15, count 0 2006.285.08:28:46.07#ibcon#flushed, iclass 15, count 0 2006.285.08:28:46.07#ibcon#about to write, iclass 15, count 0 2006.285.08:28:46.07#ibcon#wrote, iclass 15, count 0 2006.285.08:28:46.07#ibcon#about to read 3, iclass 15, count 0 2006.285.08:28:46.09#ibcon#read 3, iclass 15, count 0 2006.285.08:28:46.09#ibcon#about to read 4, iclass 15, count 0 2006.285.08:28:46.09#ibcon#read 4, iclass 15, count 0 2006.285.08:28:46.09#ibcon#about to read 5, iclass 15, count 0 2006.285.08:28:46.09#ibcon#read 5, iclass 15, count 0 2006.285.08:28:46.09#ibcon#about to read 6, iclass 15, count 0 2006.285.08:28:46.09#ibcon#read 6, iclass 15, count 0 2006.285.08:28:46.09#ibcon#end of sib2, iclass 15, count 0 2006.285.08:28:46.09#ibcon#*mode == 0, iclass 15, count 0 2006.285.08:28:46.09#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.08:28:46.09#ibcon#[25=USB\r\n] 2006.285.08:28:46.09#ibcon#*before write, iclass 15, count 0 2006.285.08:28:46.09#ibcon#enter sib2, iclass 15, count 0 2006.285.08:28:46.09#ibcon#flushed, iclass 15, count 0 2006.285.08:28:46.09#ibcon#about to write, iclass 15, count 0 2006.285.08:28:46.09#ibcon#wrote, iclass 15, count 0 2006.285.08:28:46.09#ibcon#about to read 3, iclass 15, count 0 2006.285.08:28:46.12#ibcon#read 3, iclass 15, count 0 2006.285.08:28:46.12#ibcon#about to read 4, iclass 15, count 0 2006.285.08:28:46.12#ibcon#read 4, iclass 15, count 0 2006.285.08:28:46.12#ibcon#about to read 5, iclass 15, count 0 2006.285.08:28:46.12#ibcon#read 5, iclass 15, count 0 2006.285.08:28:46.12#ibcon#about to read 6, iclass 15, count 0 2006.285.08:28:46.12#ibcon#read 6, iclass 15, count 0 2006.285.08:28:46.12#ibcon#end of sib2, iclass 15, count 0 2006.285.08:28:46.12#ibcon#*after write, iclass 15, count 0 2006.285.08:28:46.12#ibcon#*before return 0, iclass 15, count 0 2006.285.08:28:46.12#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:28:46.12#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:28:46.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.08:28:46.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.08:28:46.12$vck44/valo=7,864.99 2006.285.08:28:46.12#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.08:28:46.12#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.08:28:46.12#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:46.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:28:46.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:28:46.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:28:46.12#ibcon#enter wrdev, iclass 17, count 0 2006.285.08:28:46.12#ibcon#first serial, iclass 17, count 0 2006.285.08:28:46.12#ibcon#enter sib2, iclass 17, count 0 2006.285.08:28:46.12#ibcon#flushed, iclass 17, count 0 2006.285.08:28:46.12#ibcon#about to write, iclass 17, count 0 2006.285.08:28:46.12#ibcon#wrote, iclass 17, count 0 2006.285.08:28:46.12#ibcon#about to read 3, iclass 17, count 0 2006.285.08:28:46.14#ibcon#read 3, iclass 17, count 0 2006.285.08:28:46.14#ibcon#about to read 4, iclass 17, count 0 2006.285.08:28:46.14#ibcon#read 4, iclass 17, count 0 2006.285.08:28:46.14#ibcon#about to read 5, iclass 17, count 0 2006.285.08:28:46.14#ibcon#read 5, iclass 17, count 0 2006.285.08:28:46.14#ibcon#about to read 6, iclass 17, count 0 2006.285.08:28:46.14#ibcon#read 6, iclass 17, count 0 2006.285.08:28:46.14#ibcon#end of sib2, iclass 17, count 0 2006.285.08:28:46.14#ibcon#*mode == 0, iclass 17, count 0 2006.285.08:28:46.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.08:28:46.14#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:28:46.14#ibcon#*before write, iclass 17, count 0 2006.285.08:28:46.14#ibcon#enter sib2, iclass 17, count 0 2006.285.08:28:46.14#ibcon#flushed, iclass 17, count 0 2006.285.08:28:46.14#ibcon#about to write, iclass 17, count 0 2006.285.08:28:46.14#ibcon#wrote, iclass 17, count 0 2006.285.08:28:46.14#ibcon#about to read 3, iclass 17, count 0 2006.285.08:28:46.18#ibcon#read 3, iclass 17, count 0 2006.285.08:28:46.18#ibcon#about to read 4, iclass 17, count 0 2006.285.08:28:46.18#ibcon#read 4, iclass 17, count 0 2006.285.08:28:46.18#ibcon#about to read 5, iclass 17, count 0 2006.285.08:28:46.18#ibcon#read 5, iclass 17, count 0 2006.285.08:28:46.18#ibcon#about to read 6, iclass 17, count 0 2006.285.08:28:46.18#ibcon#read 6, iclass 17, count 0 2006.285.08:28:46.18#ibcon#end of sib2, iclass 17, count 0 2006.285.08:28:46.18#ibcon#*after write, iclass 17, count 0 2006.285.08:28:46.18#ibcon#*before return 0, iclass 17, count 0 2006.285.08:28:46.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:28:46.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:28:46.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.08:28:46.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.08:28:46.18$vck44/va=7,4 2006.285.08:28:46.18#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.08:28:46.18#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.08:28:46.18#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:46.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:28:46.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:28:46.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:28:46.24#ibcon#enter wrdev, iclass 19, count 2 2006.285.08:28:46.24#ibcon#first serial, iclass 19, count 2 2006.285.08:28:46.24#ibcon#enter sib2, iclass 19, count 2 2006.285.08:28:46.24#ibcon#flushed, iclass 19, count 2 2006.285.08:28:46.24#ibcon#about to write, iclass 19, count 2 2006.285.08:28:46.24#ibcon#wrote, iclass 19, count 2 2006.285.08:28:46.24#ibcon#about to read 3, iclass 19, count 2 2006.285.08:28:46.26#ibcon#read 3, iclass 19, count 2 2006.285.08:28:46.26#ibcon#about to read 4, iclass 19, count 2 2006.285.08:28:46.26#ibcon#read 4, iclass 19, count 2 2006.285.08:28:46.26#ibcon#about to read 5, iclass 19, count 2 2006.285.08:28:46.26#ibcon#read 5, iclass 19, count 2 2006.285.08:28:46.26#ibcon#about to read 6, iclass 19, count 2 2006.285.08:28:46.26#ibcon#read 6, iclass 19, count 2 2006.285.08:28:46.26#ibcon#end of sib2, iclass 19, count 2 2006.285.08:28:46.26#ibcon#*mode == 0, iclass 19, count 2 2006.285.08:28:46.26#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.08:28:46.26#ibcon#[25=AT07-04\r\n] 2006.285.08:28:46.26#ibcon#*before write, iclass 19, count 2 2006.285.08:28:46.26#ibcon#enter sib2, iclass 19, count 2 2006.285.08:28:46.26#ibcon#flushed, iclass 19, count 2 2006.285.08:28:46.26#ibcon#about to write, iclass 19, count 2 2006.285.08:28:46.26#ibcon#wrote, iclass 19, count 2 2006.285.08:28:46.26#ibcon#about to read 3, iclass 19, count 2 2006.285.08:28:46.29#ibcon#read 3, iclass 19, count 2 2006.285.08:28:46.29#ibcon#about to read 4, iclass 19, count 2 2006.285.08:28:46.29#ibcon#read 4, iclass 19, count 2 2006.285.08:28:46.29#ibcon#about to read 5, iclass 19, count 2 2006.285.08:28:46.29#ibcon#read 5, iclass 19, count 2 2006.285.08:28:46.29#ibcon#about to read 6, iclass 19, count 2 2006.285.08:28:46.29#ibcon#read 6, iclass 19, count 2 2006.285.08:28:46.29#ibcon#end of sib2, iclass 19, count 2 2006.285.08:28:46.29#ibcon#*after write, iclass 19, count 2 2006.285.08:28:46.29#ibcon#*before return 0, iclass 19, count 2 2006.285.08:28:46.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:28:46.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:28:46.29#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.08:28:46.29#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:46.29#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:28:46.41#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:28:46.41#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:28:46.41#ibcon#enter wrdev, iclass 19, count 0 2006.285.08:28:46.41#ibcon#first serial, iclass 19, count 0 2006.285.08:28:46.41#ibcon#enter sib2, iclass 19, count 0 2006.285.08:28:46.41#ibcon#flushed, iclass 19, count 0 2006.285.08:28:46.41#ibcon#about to write, iclass 19, count 0 2006.285.08:28:46.41#ibcon#wrote, iclass 19, count 0 2006.285.08:28:46.41#ibcon#about to read 3, iclass 19, count 0 2006.285.08:28:46.43#ibcon#read 3, iclass 19, count 0 2006.285.08:28:46.43#ibcon#about to read 4, iclass 19, count 0 2006.285.08:28:46.43#ibcon#read 4, iclass 19, count 0 2006.285.08:28:46.43#ibcon#about to read 5, iclass 19, count 0 2006.285.08:28:46.43#ibcon#read 5, iclass 19, count 0 2006.285.08:28:46.43#ibcon#about to read 6, iclass 19, count 0 2006.285.08:28:46.43#ibcon#read 6, iclass 19, count 0 2006.285.08:28:46.43#ibcon#end of sib2, iclass 19, count 0 2006.285.08:28:46.43#ibcon#*mode == 0, iclass 19, count 0 2006.285.08:28:46.43#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.08:28:46.43#ibcon#[25=USB\r\n] 2006.285.08:28:46.43#ibcon#*before write, iclass 19, count 0 2006.285.08:28:46.43#ibcon#enter sib2, iclass 19, count 0 2006.285.08:28:46.43#ibcon#flushed, iclass 19, count 0 2006.285.08:28:46.43#ibcon#about to write, iclass 19, count 0 2006.285.08:28:46.43#ibcon#wrote, iclass 19, count 0 2006.285.08:28:46.43#ibcon#about to read 3, iclass 19, count 0 2006.285.08:28:46.46#ibcon#read 3, iclass 19, count 0 2006.285.08:28:46.46#ibcon#about to read 4, iclass 19, count 0 2006.285.08:28:46.46#ibcon#read 4, iclass 19, count 0 2006.285.08:28:46.46#ibcon#about to read 5, iclass 19, count 0 2006.285.08:28:46.46#ibcon#read 5, iclass 19, count 0 2006.285.08:28:46.46#ibcon#about to read 6, iclass 19, count 0 2006.285.08:28:46.46#ibcon#read 6, iclass 19, count 0 2006.285.08:28:46.46#ibcon#end of sib2, iclass 19, count 0 2006.285.08:28:46.46#ibcon#*after write, iclass 19, count 0 2006.285.08:28:46.46#ibcon#*before return 0, iclass 19, count 0 2006.285.08:28:46.46#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:28:46.46#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:28:46.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.08:28:46.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.08:28:46.46$vck44/valo=8,884.99 2006.285.08:28:46.46#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.08:28:46.46#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.08:28:46.46#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:46.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:28:46.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:28:46.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:28:46.46#ibcon#enter wrdev, iclass 21, count 0 2006.285.08:28:46.46#ibcon#first serial, iclass 21, count 0 2006.285.08:28:46.46#ibcon#enter sib2, iclass 21, count 0 2006.285.08:28:46.46#ibcon#flushed, iclass 21, count 0 2006.285.08:28:46.46#ibcon#about to write, iclass 21, count 0 2006.285.08:28:46.46#ibcon#wrote, iclass 21, count 0 2006.285.08:28:46.46#ibcon#about to read 3, iclass 21, count 0 2006.285.08:28:46.48#ibcon#read 3, iclass 21, count 0 2006.285.08:28:46.48#ibcon#about to read 4, iclass 21, count 0 2006.285.08:28:46.48#ibcon#read 4, iclass 21, count 0 2006.285.08:28:46.48#ibcon#about to read 5, iclass 21, count 0 2006.285.08:28:46.48#ibcon#read 5, iclass 21, count 0 2006.285.08:28:46.48#ibcon#about to read 6, iclass 21, count 0 2006.285.08:28:46.48#ibcon#read 6, iclass 21, count 0 2006.285.08:28:46.48#ibcon#end of sib2, iclass 21, count 0 2006.285.08:28:46.48#ibcon#*mode == 0, iclass 21, count 0 2006.285.08:28:46.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.08:28:46.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:28:46.48#ibcon#*before write, iclass 21, count 0 2006.285.08:28:46.48#ibcon#enter sib2, iclass 21, count 0 2006.285.08:28:46.48#ibcon#flushed, iclass 21, count 0 2006.285.08:28:46.48#ibcon#about to write, iclass 21, count 0 2006.285.08:28:46.48#ibcon#wrote, iclass 21, count 0 2006.285.08:28:46.48#ibcon#about to read 3, iclass 21, count 0 2006.285.08:28:46.52#ibcon#read 3, iclass 21, count 0 2006.285.08:28:46.52#ibcon#about to read 4, iclass 21, count 0 2006.285.08:28:46.52#ibcon#read 4, iclass 21, count 0 2006.285.08:28:46.52#ibcon#about to read 5, iclass 21, count 0 2006.285.08:28:46.52#ibcon#read 5, iclass 21, count 0 2006.285.08:28:46.52#ibcon#about to read 6, iclass 21, count 0 2006.285.08:28:46.52#ibcon#read 6, iclass 21, count 0 2006.285.08:28:46.52#ibcon#end of sib2, iclass 21, count 0 2006.285.08:28:46.52#ibcon#*after write, iclass 21, count 0 2006.285.08:28:46.52#ibcon#*before return 0, iclass 21, count 0 2006.285.08:28:46.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:28:46.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:28:46.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.08:28:46.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.08:28:46.52$vck44/va=8,3 2006.285.08:28:46.52#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.08:28:46.52#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.08:28:46.52#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:46.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:28:46.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:28:46.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:28:46.58#ibcon#enter wrdev, iclass 23, count 2 2006.285.08:28:46.58#ibcon#first serial, iclass 23, count 2 2006.285.08:28:46.58#ibcon#enter sib2, iclass 23, count 2 2006.285.08:28:46.58#ibcon#flushed, iclass 23, count 2 2006.285.08:28:46.58#ibcon#about to write, iclass 23, count 2 2006.285.08:28:46.58#ibcon#wrote, iclass 23, count 2 2006.285.08:28:46.58#ibcon#about to read 3, iclass 23, count 2 2006.285.08:28:46.60#ibcon#read 3, iclass 23, count 2 2006.285.08:28:46.60#ibcon#about to read 4, iclass 23, count 2 2006.285.08:28:46.60#ibcon#read 4, iclass 23, count 2 2006.285.08:28:46.60#ibcon#about to read 5, iclass 23, count 2 2006.285.08:28:46.60#ibcon#read 5, iclass 23, count 2 2006.285.08:28:46.60#ibcon#about to read 6, iclass 23, count 2 2006.285.08:28:46.60#ibcon#read 6, iclass 23, count 2 2006.285.08:28:46.60#ibcon#end of sib2, iclass 23, count 2 2006.285.08:28:46.60#ibcon#*mode == 0, iclass 23, count 2 2006.285.08:28:46.60#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.08:28:46.60#ibcon#[25=AT08-03\r\n] 2006.285.08:28:46.60#ibcon#*before write, iclass 23, count 2 2006.285.08:28:46.60#ibcon#enter sib2, iclass 23, count 2 2006.285.08:28:46.60#ibcon#flushed, iclass 23, count 2 2006.285.08:28:46.60#ibcon#about to write, iclass 23, count 2 2006.285.08:28:46.60#ibcon#wrote, iclass 23, count 2 2006.285.08:28:46.60#ibcon#about to read 3, iclass 23, count 2 2006.285.08:28:46.63#ibcon#read 3, iclass 23, count 2 2006.285.08:28:46.63#ibcon#about to read 4, iclass 23, count 2 2006.285.08:28:46.63#ibcon#read 4, iclass 23, count 2 2006.285.08:28:46.63#ibcon#about to read 5, iclass 23, count 2 2006.285.08:28:46.63#ibcon#read 5, iclass 23, count 2 2006.285.08:28:46.63#ibcon#about to read 6, iclass 23, count 2 2006.285.08:28:46.63#ibcon#read 6, iclass 23, count 2 2006.285.08:28:46.63#ibcon#end of sib2, iclass 23, count 2 2006.285.08:28:46.63#ibcon#*after write, iclass 23, count 2 2006.285.08:28:46.63#ibcon#*before return 0, iclass 23, count 2 2006.285.08:28:46.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:28:46.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:28:46.63#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.08:28:46.63#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:46.63#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:28:46.75#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:28:46.75#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:28:46.75#ibcon#enter wrdev, iclass 23, count 0 2006.285.08:28:46.75#ibcon#first serial, iclass 23, count 0 2006.285.08:28:46.75#ibcon#enter sib2, iclass 23, count 0 2006.285.08:28:46.75#ibcon#flushed, iclass 23, count 0 2006.285.08:28:46.75#ibcon#about to write, iclass 23, count 0 2006.285.08:28:46.75#ibcon#wrote, iclass 23, count 0 2006.285.08:28:46.75#ibcon#about to read 3, iclass 23, count 0 2006.285.08:28:46.77#ibcon#read 3, iclass 23, count 0 2006.285.08:28:46.77#ibcon#about to read 4, iclass 23, count 0 2006.285.08:28:46.77#ibcon#read 4, iclass 23, count 0 2006.285.08:28:46.77#ibcon#about to read 5, iclass 23, count 0 2006.285.08:28:46.77#ibcon#read 5, iclass 23, count 0 2006.285.08:28:46.77#ibcon#about to read 6, iclass 23, count 0 2006.285.08:28:46.77#ibcon#read 6, iclass 23, count 0 2006.285.08:28:46.77#ibcon#end of sib2, iclass 23, count 0 2006.285.08:28:46.77#ibcon#*mode == 0, iclass 23, count 0 2006.285.08:28:46.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.08:28:46.77#ibcon#[25=USB\r\n] 2006.285.08:28:46.77#ibcon#*before write, iclass 23, count 0 2006.285.08:28:46.77#ibcon#enter sib2, iclass 23, count 0 2006.285.08:28:46.77#ibcon#flushed, iclass 23, count 0 2006.285.08:28:46.77#ibcon#about to write, iclass 23, count 0 2006.285.08:28:46.77#ibcon#wrote, iclass 23, count 0 2006.285.08:28:46.77#ibcon#about to read 3, iclass 23, count 0 2006.285.08:28:46.80#ibcon#read 3, iclass 23, count 0 2006.285.08:28:46.80#ibcon#about to read 4, iclass 23, count 0 2006.285.08:28:46.80#ibcon#read 4, iclass 23, count 0 2006.285.08:28:46.80#ibcon#about to read 5, iclass 23, count 0 2006.285.08:28:46.80#ibcon#read 5, iclass 23, count 0 2006.285.08:28:46.80#ibcon#about to read 6, iclass 23, count 0 2006.285.08:28:46.80#ibcon#read 6, iclass 23, count 0 2006.285.08:28:46.80#ibcon#end of sib2, iclass 23, count 0 2006.285.08:28:46.80#ibcon#*after write, iclass 23, count 0 2006.285.08:28:46.80#ibcon#*before return 0, iclass 23, count 0 2006.285.08:28:46.80#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:28:46.80#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:28:46.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.08:28:46.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.08:28:46.80$vck44/vblo=1,629.99 2006.285.08:28:46.80#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.08:28:46.80#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.08:28:46.80#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:46.80#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:28:46.80#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:28:46.80#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:28:46.80#ibcon#enter wrdev, iclass 25, count 0 2006.285.08:28:46.80#ibcon#first serial, iclass 25, count 0 2006.285.08:28:46.80#ibcon#enter sib2, iclass 25, count 0 2006.285.08:28:46.80#ibcon#flushed, iclass 25, count 0 2006.285.08:28:46.80#ibcon#about to write, iclass 25, count 0 2006.285.08:28:46.80#ibcon#wrote, iclass 25, count 0 2006.285.08:28:46.80#ibcon#about to read 3, iclass 25, count 0 2006.285.08:28:46.82#ibcon#read 3, iclass 25, count 0 2006.285.08:28:46.82#ibcon#about to read 4, iclass 25, count 0 2006.285.08:28:46.82#ibcon#read 4, iclass 25, count 0 2006.285.08:28:46.82#ibcon#about to read 5, iclass 25, count 0 2006.285.08:28:46.82#ibcon#read 5, iclass 25, count 0 2006.285.08:28:46.82#ibcon#about to read 6, iclass 25, count 0 2006.285.08:28:46.82#ibcon#read 6, iclass 25, count 0 2006.285.08:28:46.82#ibcon#end of sib2, iclass 25, count 0 2006.285.08:28:46.82#ibcon#*mode == 0, iclass 25, count 0 2006.285.08:28:46.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.08:28:46.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:28:46.82#ibcon#*before write, iclass 25, count 0 2006.285.08:28:46.82#ibcon#enter sib2, iclass 25, count 0 2006.285.08:28:46.82#ibcon#flushed, iclass 25, count 0 2006.285.08:28:46.82#ibcon#about to write, iclass 25, count 0 2006.285.08:28:46.82#ibcon#wrote, iclass 25, count 0 2006.285.08:28:46.82#ibcon#about to read 3, iclass 25, count 0 2006.285.08:28:46.86#ibcon#read 3, iclass 25, count 0 2006.285.08:28:46.86#ibcon#about to read 4, iclass 25, count 0 2006.285.08:28:46.86#ibcon#read 4, iclass 25, count 0 2006.285.08:28:46.86#ibcon#about to read 5, iclass 25, count 0 2006.285.08:28:46.86#ibcon#read 5, iclass 25, count 0 2006.285.08:28:46.86#ibcon#about to read 6, iclass 25, count 0 2006.285.08:28:46.86#ibcon#read 6, iclass 25, count 0 2006.285.08:28:46.86#ibcon#end of sib2, iclass 25, count 0 2006.285.08:28:46.86#ibcon#*after write, iclass 25, count 0 2006.285.08:28:46.86#ibcon#*before return 0, iclass 25, count 0 2006.285.08:28:46.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:28:46.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:28:46.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.08:28:46.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.08:28:46.86$vck44/vb=1,4 2006.285.08:28:46.86#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.08:28:46.86#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.08:28:46.86#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:46.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:28:46.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:28:46.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:28:46.86#ibcon#enter wrdev, iclass 27, count 2 2006.285.08:28:46.86#ibcon#first serial, iclass 27, count 2 2006.285.08:28:46.86#ibcon#enter sib2, iclass 27, count 2 2006.285.08:28:46.86#ibcon#flushed, iclass 27, count 2 2006.285.08:28:46.86#ibcon#about to write, iclass 27, count 2 2006.285.08:28:46.86#ibcon#wrote, iclass 27, count 2 2006.285.08:28:46.86#ibcon#about to read 3, iclass 27, count 2 2006.285.08:28:46.88#ibcon#read 3, iclass 27, count 2 2006.285.08:28:46.88#ibcon#about to read 4, iclass 27, count 2 2006.285.08:28:46.88#ibcon#read 4, iclass 27, count 2 2006.285.08:28:46.88#ibcon#about to read 5, iclass 27, count 2 2006.285.08:28:46.88#ibcon#read 5, iclass 27, count 2 2006.285.08:28:46.88#ibcon#about to read 6, iclass 27, count 2 2006.285.08:28:46.88#ibcon#read 6, iclass 27, count 2 2006.285.08:28:46.88#ibcon#end of sib2, iclass 27, count 2 2006.285.08:28:46.88#ibcon#*mode == 0, iclass 27, count 2 2006.285.08:28:46.88#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.08:28:46.88#ibcon#[27=AT01-04\r\n] 2006.285.08:28:46.88#ibcon#*before write, iclass 27, count 2 2006.285.08:28:46.88#ibcon#enter sib2, iclass 27, count 2 2006.285.08:28:46.88#ibcon#flushed, iclass 27, count 2 2006.285.08:28:46.88#ibcon#about to write, iclass 27, count 2 2006.285.08:28:46.88#ibcon#wrote, iclass 27, count 2 2006.285.08:28:46.88#ibcon#about to read 3, iclass 27, count 2 2006.285.08:28:46.91#ibcon#read 3, iclass 27, count 2 2006.285.08:28:46.91#ibcon#about to read 4, iclass 27, count 2 2006.285.08:28:46.91#ibcon#read 4, iclass 27, count 2 2006.285.08:28:46.91#ibcon#about to read 5, iclass 27, count 2 2006.285.08:28:46.91#ibcon#read 5, iclass 27, count 2 2006.285.08:28:46.91#ibcon#about to read 6, iclass 27, count 2 2006.285.08:28:46.91#ibcon#read 6, iclass 27, count 2 2006.285.08:28:46.91#ibcon#end of sib2, iclass 27, count 2 2006.285.08:28:46.91#ibcon#*after write, iclass 27, count 2 2006.285.08:28:46.91#ibcon#*before return 0, iclass 27, count 2 2006.285.08:28:46.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:28:46.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:28:46.91#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.08:28:46.91#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:46.91#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:28:47.03#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:28:47.03#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:28:47.03#ibcon#enter wrdev, iclass 27, count 0 2006.285.08:28:47.03#ibcon#first serial, iclass 27, count 0 2006.285.08:28:47.03#ibcon#enter sib2, iclass 27, count 0 2006.285.08:28:47.03#ibcon#flushed, iclass 27, count 0 2006.285.08:28:47.03#ibcon#about to write, iclass 27, count 0 2006.285.08:28:47.03#ibcon#wrote, iclass 27, count 0 2006.285.08:28:47.03#ibcon#about to read 3, iclass 27, count 0 2006.285.08:28:47.05#ibcon#read 3, iclass 27, count 0 2006.285.08:28:47.05#ibcon#about to read 4, iclass 27, count 0 2006.285.08:28:47.05#ibcon#read 4, iclass 27, count 0 2006.285.08:28:47.05#ibcon#about to read 5, iclass 27, count 0 2006.285.08:28:47.05#ibcon#read 5, iclass 27, count 0 2006.285.08:28:47.05#ibcon#about to read 6, iclass 27, count 0 2006.285.08:28:47.05#ibcon#read 6, iclass 27, count 0 2006.285.08:28:47.05#ibcon#end of sib2, iclass 27, count 0 2006.285.08:28:47.05#ibcon#*mode == 0, iclass 27, count 0 2006.285.08:28:47.05#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.08:28:47.05#ibcon#[27=USB\r\n] 2006.285.08:28:47.05#ibcon#*before write, iclass 27, count 0 2006.285.08:28:47.05#ibcon#enter sib2, iclass 27, count 0 2006.285.08:28:47.05#ibcon#flushed, iclass 27, count 0 2006.285.08:28:47.05#ibcon#about to write, iclass 27, count 0 2006.285.08:28:47.05#ibcon#wrote, iclass 27, count 0 2006.285.08:28:47.05#ibcon#about to read 3, iclass 27, count 0 2006.285.08:28:47.08#ibcon#read 3, iclass 27, count 0 2006.285.08:28:47.08#ibcon#about to read 4, iclass 27, count 0 2006.285.08:28:47.08#ibcon#read 4, iclass 27, count 0 2006.285.08:28:47.08#ibcon#about to read 5, iclass 27, count 0 2006.285.08:28:47.08#ibcon#read 5, iclass 27, count 0 2006.285.08:28:47.08#ibcon#about to read 6, iclass 27, count 0 2006.285.08:28:47.08#ibcon#read 6, iclass 27, count 0 2006.285.08:28:47.08#ibcon#end of sib2, iclass 27, count 0 2006.285.08:28:47.08#ibcon#*after write, iclass 27, count 0 2006.285.08:28:47.08#ibcon#*before return 0, iclass 27, count 0 2006.285.08:28:47.08#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:28:47.08#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:28:47.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.08:28:47.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.08:28:47.08$vck44/vblo=2,634.99 2006.285.08:28:47.08#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.08:28:47.08#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.08:28:47.08#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:47.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:28:47.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:28:47.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:28:47.08#ibcon#enter wrdev, iclass 29, count 0 2006.285.08:28:47.08#ibcon#first serial, iclass 29, count 0 2006.285.08:28:47.08#ibcon#enter sib2, iclass 29, count 0 2006.285.08:28:47.08#ibcon#flushed, iclass 29, count 0 2006.285.08:28:47.08#ibcon#about to write, iclass 29, count 0 2006.285.08:28:47.08#ibcon#wrote, iclass 29, count 0 2006.285.08:28:47.08#ibcon#about to read 3, iclass 29, count 0 2006.285.08:28:47.10#ibcon#read 3, iclass 29, count 0 2006.285.08:28:47.10#ibcon#about to read 4, iclass 29, count 0 2006.285.08:28:47.10#ibcon#read 4, iclass 29, count 0 2006.285.08:28:47.10#ibcon#about to read 5, iclass 29, count 0 2006.285.08:28:47.10#ibcon#read 5, iclass 29, count 0 2006.285.08:28:47.10#ibcon#about to read 6, iclass 29, count 0 2006.285.08:28:47.10#ibcon#read 6, iclass 29, count 0 2006.285.08:28:47.10#ibcon#end of sib2, iclass 29, count 0 2006.285.08:28:47.10#ibcon#*mode == 0, iclass 29, count 0 2006.285.08:28:47.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.08:28:47.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:28:47.10#ibcon#*before write, iclass 29, count 0 2006.285.08:28:47.10#ibcon#enter sib2, iclass 29, count 0 2006.285.08:28:47.10#ibcon#flushed, iclass 29, count 0 2006.285.08:28:47.10#ibcon#about to write, iclass 29, count 0 2006.285.08:28:47.10#ibcon#wrote, iclass 29, count 0 2006.285.08:28:47.10#ibcon#about to read 3, iclass 29, count 0 2006.285.08:28:47.14#ibcon#read 3, iclass 29, count 0 2006.285.08:28:47.14#ibcon#about to read 4, iclass 29, count 0 2006.285.08:28:47.14#ibcon#read 4, iclass 29, count 0 2006.285.08:28:47.14#ibcon#about to read 5, iclass 29, count 0 2006.285.08:28:47.14#ibcon#read 5, iclass 29, count 0 2006.285.08:28:47.14#ibcon#about to read 6, iclass 29, count 0 2006.285.08:28:47.14#ibcon#read 6, iclass 29, count 0 2006.285.08:28:47.14#ibcon#end of sib2, iclass 29, count 0 2006.285.08:28:47.14#ibcon#*after write, iclass 29, count 0 2006.285.08:28:47.14#ibcon#*before return 0, iclass 29, count 0 2006.285.08:28:47.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:28:47.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:28:47.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.08:28:47.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.08:28:47.14$vck44/vb=2,5 2006.285.08:28:47.14#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.08:28:47.14#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.08:28:47.14#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:47.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:28:47.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:28:47.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:28:47.20#ibcon#enter wrdev, iclass 31, count 2 2006.285.08:28:47.20#ibcon#first serial, iclass 31, count 2 2006.285.08:28:47.20#ibcon#enter sib2, iclass 31, count 2 2006.285.08:28:47.20#ibcon#flushed, iclass 31, count 2 2006.285.08:28:47.20#ibcon#about to write, iclass 31, count 2 2006.285.08:28:47.20#ibcon#wrote, iclass 31, count 2 2006.285.08:28:47.20#ibcon#about to read 3, iclass 31, count 2 2006.285.08:28:47.22#ibcon#read 3, iclass 31, count 2 2006.285.08:28:47.22#ibcon#about to read 4, iclass 31, count 2 2006.285.08:28:47.22#ibcon#read 4, iclass 31, count 2 2006.285.08:28:47.22#ibcon#about to read 5, iclass 31, count 2 2006.285.08:28:47.22#ibcon#read 5, iclass 31, count 2 2006.285.08:28:47.22#ibcon#about to read 6, iclass 31, count 2 2006.285.08:28:47.22#ibcon#read 6, iclass 31, count 2 2006.285.08:28:47.22#ibcon#end of sib2, iclass 31, count 2 2006.285.08:28:47.22#ibcon#*mode == 0, iclass 31, count 2 2006.285.08:28:47.22#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.08:28:47.22#ibcon#[27=AT02-05\r\n] 2006.285.08:28:47.22#ibcon#*before write, iclass 31, count 2 2006.285.08:28:47.22#ibcon#enter sib2, iclass 31, count 2 2006.285.08:28:47.22#ibcon#flushed, iclass 31, count 2 2006.285.08:28:47.22#ibcon#about to write, iclass 31, count 2 2006.285.08:28:47.22#ibcon#wrote, iclass 31, count 2 2006.285.08:28:47.22#ibcon#about to read 3, iclass 31, count 2 2006.285.08:28:47.25#ibcon#read 3, iclass 31, count 2 2006.285.08:28:47.25#ibcon#about to read 4, iclass 31, count 2 2006.285.08:28:47.25#ibcon#read 4, iclass 31, count 2 2006.285.08:28:47.25#ibcon#about to read 5, iclass 31, count 2 2006.285.08:28:47.25#ibcon#read 5, iclass 31, count 2 2006.285.08:28:47.25#ibcon#about to read 6, iclass 31, count 2 2006.285.08:28:47.25#ibcon#read 6, iclass 31, count 2 2006.285.08:28:47.25#ibcon#end of sib2, iclass 31, count 2 2006.285.08:28:47.25#ibcon#*after write, iclass 31, count 2 2006.285.08:28:47.25#ibcon#*before return 0, iclass 31, count 2 2006.285.08:28:47.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:28:47.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:28:47.25#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.08:28:47.25#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:47.25#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:28:47.37#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:28:47.37#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:28:47.37#ibcon#enter wrdev, iclass 31, count 0 2006.285.08:28:47.37#ibcon#first serial, iclass 31, count 0 2006.285.08:28:47.37#ibcon#enter sib2, iclass 31, count 0 2006.285.08:28:47.37#ibcon#flushed, iclass 31, count 0 2006.285.08:28:47.37#ibcon#about to write, iclass 31, count 0 2006.285.08:28:47.37#ibcon#wrote, iclass 31, count 0 2006.285.08:28:47.37#ibcon#about to read 3, iclass 31, count 0 2006.285.08:28:47.39#ibcon#read 3, iclass 31, count 0 2006.285.08:28:47.39#ibcon#about to read 4, iclass 31, count 0 2006.285.08:28:47.39#ibcon#read 4, iclass 31, count 0 2006.285.08:28:47.39#ibcon#about to read 5, iclass 31, count 0 2006.285.08:28:47.39#ibcon#read 5, iclass 31, count 0 2006.285.08:28:47.39#ibcon#about to read 6, iclass 31, count 0 2006.285.08:28:47.39#ibcon#read 6, iclass 31, count 0 2006.285.08:28:47.39#ibcon#end of sib2, iclass 31, count 0 2006.285.08:28:47.39#ibcon#*mode == 0, iclass 31, count 0 2006.285.08:28:47.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.08:28:47.39#ibcon#[27=USB\r\n] 2006.285.08:28:47.39#ibcon#*before write, iclass 31, count 0 2006.285.08:28:47.39#ibcon#enter sib2, iclass 31, count 0 2006.285.08:28:47.39#ibcon#flushed, iclass 31, count 0 2006.285.08:28:47.39#ibcon#about to write, iclass 31, count 0 2006.285.08:28:47.39#ibcon#wrote, iclass 31, count 0 2006.285.08:28:47.39#ibcon#about to read 3, iclass 31, count 0 2006.285.08:28:47.42#ibcon#read 3, iclass 31, count 0 2006.285.08:28:47.42#ibcon#about to read 4, iclass 31, count 0 2006.285.08:28:47.42#ibcon#read 4, iclass 31, count 0 2006.285.08:28:47.42#ibcon#about to read 5, iclass 31, count 0 2006.285.08:28:47.42#ibcon#read 5, iclass 31, count 0 2006.285.08:28:47.42#ibcon#about to read 6, iclass 31, count 0 2006.285.08:28:47.42#ibcon#read 6, iclass 31, count 0 2006.285.08:28:47.42#ibcon#end of sib2, iclass 31, count 0 2006.285.08:28:47.42#ibcon#*after write, iclass 31, count 0 2006.285.08:28:47.42#ibcon#*before return 0, iclass 31, count 0 2006.285.08:28:47.42#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:28:47.42#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:28:47.42#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.08:28:47.42#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.08:28:47.42$vck44/vblo=3,649.99 2006.285.08:28:47.42#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.08:28:47.42#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.08:28:47.42#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:47.42#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:28:47.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:28:47.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:28:47.42#ibcon#enter wrdev, iclass 33, count 0 2006.285.08:28:47.42#ibcon#first serial, iclass 33, count 0 2006.285.08:28:47.42#ibcon#enter sib2, iclass 33, count 0 2006.285.08:28:47.42#ibcon#flushed, iclass 33, count 0 2006.285.08:28:47.42#ibcon#about to write, iclass 33, count 0 2006.285.08:28:47.42#ibcon#wrote, iclass 33, count 0 2006.285.08:28:47.42#ibcon#about to read 3, iclass 33, count 0 2006.285.08:28:47.44#ibcon#read 3, iclass 33, count 0 2006.285.08:28:47.44#ibcon#about to read 4, iclass 33, count 0 2006.285.08:28:47.44#ibcon#read 4, iclass 33, count 0 2006.285.08:28:47.44#ibcon#about to read 5, iclass 33, count 0 2006.285.08:28:47.44#ibcon#read 5, iclass 33, count 0 2006.285.08:28:47.44#ibcon#about to read 6, iclass 33, count 0 2006.285.08:28:47.44#ibcon#read 6, iclass 33, count 0 2006.285.08:28:47.44#ibcon#end of sib2, iclass 33, count 0 2006.285.08:28:47.44#ibcon#*mode == 0, iclass 33, count 0 2006.285.08:28:47.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.08:28:47.44#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:28:47.44#ibcon#*before write, iclass 33, count 0 2006.285.08:28:47.44#ibcon#enter sib2, iclass 33, count 0 2006.285.08:28:47.44#ibcon#flushed, iclass 33, count 0 2006.285.08:28:47.44#ibcon#about to write, iclass 33, count 0 2006.285.08:28:47.44#ibcon#wrote, iclass 33, count 0 2006.285.08:28:47.44#ibcon#about to read 3, iclass 33, count 0 2006.285.08:28:47.48#ibcon#read 3, iclass 33, count 0 2006.285.08:28:47.48#ibcon#about to read 4, iclass 33, count 0 2006.285.08:28:47.48#ibcon#read 4, iclass 33, count 0 2006.285.08:28:47.48#ibcon#about to read 5, iclass 33, count 0 2006.285.08:28:47.48#ibcon#read 5, iclass 33, count 0 2006.285.08:28:47.48#ibcon#about to read 6, iclass 33, count 0 2006.285.08:28:47.48#ibcon#read 6, iclass 33, count 0 2006.285.08:28:47.48#ibcon#end of sib2, iclass 33, count 0 2006.285.08:28:47.48#ibcon#*after write, iclass 33, count 0 2006.285.08:28:47.48#ibcon#*before return 0, iclass 33, count 0 2006.285.08:28:47.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:28:47.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:28:47.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.08:28:47.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.08:28:47.48$vck44/vb=3,4 2006.285.08:28:47.48#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.08:28:47.48#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.08:28:47.48#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:47.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:28:47.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:28:47.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:28:47.54#ibcon#enter wrdev, iclass 35, count 2 2006.285.08:28:47.54#ibcon#first serial, iclass 35, count 2 2006.285.08:28:47.54#ibcon#enter sib2, iclass 35, count 2 2006.285.08:28:47.54#ibcon#flushed, iclass 35, count 2 2006.285.08:28:47.54#ibcon#about to write, iclass 35, count 2 2006.285.08:28:47.54#ibcon#wrote, iclass 35, count 2 2006.285.08:28:47.54#ibcon#about to read 3, iclass 35, count 2 2006.285.08:28:47.56#ibcon#read 3, iclass 35, count 2 2006.285.08:28:47.56#ibcon#about to read 4, iclass 35, count 2 2006.285.08:28:47.56#ibcon#read 4, iclass 35, count 2 2006.285.08:28:47.56#ibcon#about to read 5, iclass 35, count 2 2006.285.08:28:47.56#ibcon#read 5, iclass 35, count 2 2006.285.08:28:47.56#ibcon#about to read 6, iclass 35, count 2 2006.285.08:28:47.56#ibcon#read 6, iclass 35, count 2 2006.285.08:28:47.56#ibcon#end of sib2, iclass 35, count 2 2006.285.08:28:47.56#ibcon#*mode == 0, iclass 35, count 2 2006.285.08:28:47.56#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.08:28:47.56#ibcon#[27=AT03-04\r\n] 2006.285.08:28:47.56#ibcon#*before write, iclass 35, count 2 2006.285.08:28:47.56#ibcon#enter sib2, iclass 35, count 2 2006.285.08:28:47.56#ibcon#flushed, iclass 35, count 2 2006.285.08:28:47.56#ibcon#about to write, iclass 35, count 2 2006.285.08:28:47.56#ibcon#wrote, iclass 35, count 2 2006.285.08:28:47.56#ibcon#about to read 3, iclass 35, count 2 2006.285.08:28:47.59#ibcon#read 3, iclass 35, count 2 2006.285.08:28:47.59#ibcon#about to read 4, iclass 35, count 2 2006.285.08:28:47.59#ibcon#read 4, iclass 35, count 2 2006.285.08:28:47.59#ibcon#about to read 5, iclass 35, count 2 2006.285.08:28:47.59#ibcon#read 5, iclass 35, count 2 2006.285.08:28:47.59#ibcon#about to read 6, iclass 35, count 2 2006.285.08:28:47.59#ibcon#read 6, iclass 35, count 2 2006.285.08:28:47.59#ibcon#end of sib2, iclass 35, count 2 2006.285.08:28:47.59#ibcon#*after write, iclass 35, count 2 2006.285.08:28:47.59#ibcon#*before return 0, iclass 35, count 2 2006.285.08:28:47.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:28:47.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:28:47.59#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.08:28:47.59#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:47.59#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:28:47.71#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:28:47.71#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:28:47.71#ibcon#enter wrdev, iclass 35, count 0 2006.285.08:28:47.71#ibcon#first serial, iclass 35, count 0 2006.285.08:28:47.71#ibcon#enter sib2, iclass 35, count 0 2006.285.08:28:47.71#ibcon#flushed, iclass 35, count 0 2006.285.08:28:47.71#ibcon#about to write, iclass 35, count 0 2006.285.08:28:47.71#ibcon#wrote, iclass 35, count 0 2006.285.08:28:47.71#ibcon#about to read 3, iclass 35, count 0 2006.285.08:28:47.73#ibcon#read 3, iclass 35, count 0 2006.285.08:28:47.73#ibcon#about to read 4, iclass 35, count 0 2006.285.08:28:47.73#ibcon#read 4, iclass 35, count 0 2006.285.08:28:47.73#ibcon#about to read 5, iclass 35, count 0 2006.285.08:28:47.73#ibcon#read 5, iclass 35, count 0 2006.285.08:28:47.73#ibcon#about to read 6, iclass 35, count 0 2006.285.08:28:47.73#ibcon#read 6, iclass 35, count 0 2006.285.08:28:47.73#ibcon#end of sib2, iclass 35, count 0 2006.285.08:28:47.73#ibcon#*mode == 0, iclass 35, count 0 2006.285.08:28:47.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.08:28:47.73#ibcon#[27=USB\r\n] 2006.285.08:28:47.73#ibcon#*before write, iclass 35, count 0 2006.285.08:28:47.73#ibcon#enter sib2, iclass 35, count 0 2006.285.08:28:47.73#ibcon#flushed, iclass 35, count 0 2006.285.08:28:47.73#ibcon#about to write, iclass 35, count 0 2006.285.08:28:47.73#ibcon#wrote, iclass 35, count 0 2006.285.08:28:47.73#ibcon#about to read 3, iclass 35, count 0 2006.285.08:28:47.76#ibcon#read 3, iclass 35, count 0 2006.285.08:28:47.76#ibcon#about to read 4, iclass 35, count 0 2006.285.08:28:47.76#ibcon#read 4, iclass 35, count 0 2006.285.08:28:47.76#ibcon#about to read 5, iclass 35, count 0 2006.285.08:28:47.76#ibcon#read 5, iclass 35, count 0 2006.285.08:28:47.76#ibcon#about to read 6, iclass 35, count 0 2006.285.08:28:47.76#ibcon#read 6, iclass 35, count 0 2006.285.08:28:47.76#ibcon#end of sib2, iclass 35, count 0 2006.285.08:28:47.76#ibcon#*after write, iclass 35, count 0 2006.285.08:28:47.76#ibcon#*before return 0, iclass 35, count 0 2006.285.08:28:47.76#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:28:47.76#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:28:47.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.08:28:47.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.08:28:47.76$vck44/vblo=4,679.99 2006.285.08:28:47.76#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.08:28:47.76#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.08:28:47.76#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:47.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:28:47.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:28:47.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:28:47.76#ibcon#enter wrdev, iclass 37, count 0 2006.285.08:28:47.76#ibcon#first serial, iclass 37, count 0 2006.285.08:28:47.76#ibcon#enter sib2, iclass 37, count 0 2006.285.08:28:47.76#ibcon#flushed, iclass 37, count 0 2006.285.08:28:47.76#ibcon#about to write, iclass 37, count 0 2006.285.08:28:47.76#ibcon#wrote, iclass 37, count 0 2006.285.08:28:47.76#ibcon#about to read 3, iclass 37, count 0 2006.285.08:28:47.78#ibcon#read 3, iclass 37, count 0 2006.285.08:28:47.78#ibcon#about to read 4, iclass 37, count 0 2006.285.08:28:47.78#ibcon#read 4, iclass 37, count 0 2006.285.08:28:47.78#ibcon#about to read 5, iclass 37, count 0 2006.285.08:28:47.78#ibcon#read 5, iclass 37, count 0 2006.285.08:28:47.78#ibcon#about to read 6, iclass 37, count 0 2006.285.08:28:47.78#ibcon#read 6, iclass 37, count 0 2006.285.08:28:47.78#ibcon#end of sib2, iclass 37, count 0 2006.285.08:28:47.78#ibcon#*mode == 0, iclass 37, count 0 2006.285.08:28:47.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.08:28:47.78#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:28:47.78#ibcon#*before write, iclass 37, count 0 2006.285.08:28:47.78#ibcon#enter sib2, iclass 37, count 0 2006.285.08:28:47.78#ibcon#flushed, iclass 37, count 0 2006.285.08:28:47.78#ibcon#about to write, iclass 37, count 0 2006.285.08:28:47.78#ibcon#wrote, iclass 37, count 0 2006.285.08:28:47.78#ibcon#about to read 3, iclass 37, count 0 2006.285.08:28:47.82#ibcon#read 3, iclass 37, count 0 2006.285.08:28:47.82#ibcon#about to read 4, iclass 37, count 0 2006.285.08:28:47.82#ibcon#read 4, iclass 37, count 0 2006.285.08:28:47.82#ibcon#about to read 5, iclass 37, count 0 2006.285.08:28:47.82#ibcon#read 5, iclass 37, count 0 2006.285.08:28:47.82#ibcon#about to read 6, iclass 37, count 0 2006.285.08:28:47.82#ibcon#read 6, iclass 37, count 0 2006.285.08:28:47.82#ibcon#end of sib2, iclass 37, count 0 2006.285.08:28:47.82#ibcon#*after write, iclass 37, count 0 2006.285.08:28:47.82#ibcon#*before return 0, iclass 37, count 0 2006.285.08:28:47.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:28:47.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:28:47.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.08:28:47.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.08:28:47.82$vck44/vb=4,5 2006.285.08:28:47.82#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.08:28:47.82#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.08:28:47.82#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:47.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:28:47.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:28:47.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:28:47.88#ibcon#enter wrdev, iclass 39, count 2 2006.285.08:28:47.88#ibcon#first serial, iclass 39, count 2 2006.285.08:28:47.88#ibcon#enter sib2, iclass 39, count 2 2006.285.08:28:47.88#ibcon#flushed, iclass 39, count 2 2006.285.08:28:47.88#ibcon#about to write, iclass 39, count 2 2006.285.08:28:47.88#ibcon#wrote, iclass 39, count 2 2006.285.08:28:47.88#ibcon#about to read 3, iclass 39, count 2 2006.285.08:28:47.90#ibcon#read 3, iclass 39, count 2 2006.285.08:28:47.90#ibcon#about to read 4, iclass 39, count 2 2006.285.08:28:47.90#ibcon#read 4, iclass 39, count 2 2006.285.08:28:47.90#ibcon#about to read 5, iclass 39, count 2 2006.285.08:28:47.90#ibcon#read 5, iclass 39, count 2 2006.285.08:28:47.90#ibcon#about to read 6, iclass 39, count 2 2006.285.08:28:47.90#ibcon#read 6, iclass 39, count 2 2006.285.08:28:47.90#ibcon#end of sib2, iclass 39, count 2 2006.285.08:28:47.90#ibcon#*mode == 0, iclass 39, count 2 2006.285.08:28:47.90#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.08:28:47.90#ibcon#[27=AT04-05\r\n] 2006.285.08:28:47.90#ibcon#*before write, iclass 39, count 2 2006.285.08:28:47.90#ibcon#enter sib2, iclass 39, count 2 2006.285.08:28:47.90#ibcon#flushed, iclass 39, count 2 2006.285.08:28:47.90#ibcon#about to write, iclass 39, count 2 2006.285.08:28:47.90#ibcon#wrote, iclass 39, count 2 2006.285.08:28:47.90#ibcon#about to read 3, iclass 39, count 2 2006.285.08:28:47.93#ibcon#read 3, iclass 39, count 2 2006.285.08:28:47.93#ibcon#about to read 4, iclass 39, count 2 2006.285.08:28:47.93#ibcon#read 4, iclass 39, count 2 2006.285.08:28:47.93#ibcon#about to read 5, iclass 39, count 2 2006.285.08:28:47.93#ibcon#read 5, iclass 39, count 2 2006.285.08:28:47.93#ibcon#about to read 6, iclass 39, count 2 2006.285.08:28:47.93#ibcon#read 6, iclass 39, count 2 2006.285.08:28:47.93#ibcon#end of sib2, iclass 39, count 2 2006.285.08:28:47.93#ibcon#*after write, iclass 39, count 2 2006.285.08:28:47.93#ibcon#*before return 0, iclass 39, count 2 2006.285.08:28:47.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:28:47.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:28:47.93#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.08:28:47.93#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:47.93#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:28:48.05#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:28:48.05#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:28:48.05#ibcon#enter wrdev, iclass 39, count 0 2006.285.08:28:48.05#ibcon#first serial, iclass 39, count 0 2006.285.08:28:48.05#ibcon#enter sib2, iclass 39, count 0 2006.285.08:28:48.05#ibcon#flushed, iclass 39, count 0 2006.285.08:28:48.05#ibcon#about to write, iclass 39, count 0 2006.285.08:28:48.05#ibcon#wrote, iclass 39, count 0 2006.285.08:28:48.05#ibcon#about to read 3, iclass 39, count 0 2006.285.08:28:48.07#ibcon#read 3, iclass 39, count 0 2006.285.08:28:48.07#ibcon#about to read 4, iclass 39, count 0 2006.285.08:28:48.07#ibcon#read 4, iclass 39, count 0 2006.285.08:28:48.07#ibcon#about to read 5, iclass 39, count 0 2006.285.08:28:48.07#ibcon#read 5, iclass 39, count 0 2006.285.08:28:48.07#ibcon#about to read 6, iclass 39, count 0 2006.285.08:28:48.07#ibcon#read 6, iclass 39, count 0 2006.285.08:28:48.07#ibcon#end of sib2, iclass 39, count 0 2006.285.08:28:48.07#ibcon#*mode == 0, iclass 39, count 0 2006.285.08:28:48.07#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.08:28:48.07#ibcon#[27=USB\r\n] 2006.285.08:28:48.07#ibcon#*before write, iclass 39, count 0 2006.285.08:28:48.07#ibcon#enter sib2, iclass 39, count 0 2006.285.08:28:48.07#ibcon#flushed, iclass 39, count 0 2006.285.08:28:48.07#ibcon#about to write, iclass 39, count 0 2006.285.08:28:48.07#ibcon#wrote, iclass 39, count 0 2006.285.08:28:48.07#ibcon#about to read 3, iclass 39, count 0 2006.285.08:28:48.10#ibcon#read 3, iclass 39, count 0 2006.285.08:28:48.10#ibcon#about to read 4, iclass 39, count 0 2006.285.08:28:48.10#ibcon#read 4, iclass 39, count 0 2006.285.08:28:48.10#ibcon#about to read 5, iclass 39, count 0 2006.285.08:28:48.10#ibcon#read 5, iclass 39, count 0 2006.285.08:28:48.10#ibcon#about to read 6, iclass 39, count 0 2006.285.08:28:48.10#ibcon#read 6, iclass 39, count 0 2006.285.08:28:48.10#ibcon#end of sib2, iclass 39, count 0 2006.285.08:28:48.10#ibcon#*after write, iclass 39, count 0 2006.285.08:28:48.10#ibcon#*before return 0, iclass 39, count 0 2006.285.08:28:48.10#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:28:48.10#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:28:48.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.08:28:48.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.08:28:48.10$vck44/vblo=5,709.99 2006.285.08:28:48.10#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.08:28:48.10#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.08:28:48.10#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:48.10#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:28:48.10#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:28:48.10#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:28:48.10#ibcon#enter wrdev, iclass 3, count 0 2006.285.08:28:48.10#ibcon#first serial, iclass 3, count 0 2006.285.08:28:48.10#ibcon#enter sib2, iclass 3, count 0 2006.285.08:28:48.10#ibcon#flushed, iclass 3, count 0 2006.285.08:28:48.10#ibcon#about to write, iclass 3, count 0 2006.285.08:28:48.10#ibcon#wrote, iclass 3, count 0 2006.285.08:28:48.10#ibcon#about to read 3, iclass 3, count 0 2006.285.08:28:48.12#ibcon#read 3, iclass 3, count 0 2006.285.08:28:48.12#ibcon#about to read 4, iclass 3, count 0 2006.285.08:28:48.12#ibcon#read 4, iclass 3, count 0 2006.285.08:28:48.12#ibcon#about to read 5, iclass 3, count 0 2006.285.08:28:48.12#ibcon#read 5, iclass 3, count 0 2006.285.08:28:48.12#ibcon#about to read 6, iclass 3, count 0 2006.285.08:28:48.12#ibcon#read 6, iclass 3, count 0 2006.285.08:28:48.12#ibcon#end of sib2, iclass 3, count 0 2006.285.08:28:48.12#ibcon#*mode == 0, iclass 3, count 0 2006.285.08:28:48.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.08:28:48.12#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:28:48.12#ibcon#*before write, iclass 3, count 0 2006.285.08:28:48.12#ibcon#enter sib2, iclass 3, count 0 2006.285.08:28:48.12#ibcon#flushed, iclass 3, count 0 2006.285.08:28:48.12#ibcon#about to write, iclass 3, count 0 2006.285.08:28:48.12#ibcon#wrote, iclass 3, count 0 2006.285.08:28:48.12#ibcon#about to read 3, iclass 3, count 0 2006.285.08:28:48.16#ibcon#read 3, iclass 3, count 0 2006.285.08:28:48.16#ibcon#about to read 4, iclass 3, count 0 2006.285.08:28:48.16#ibcon#read 4, iclass 3, count 0 2006.285.08:28:48.16#ibcon#about to read 5, iclass 3, count 0 2006.285.08:28:48.16#ibcon#read 5, iclass 3, count 0 2006.285.08:28:48.16#ibcon#about to read 6, iclass 3, count 0 2006.285.08:28:48.16#ibcon#read 6, iclass 3, count 0 2006.285.08:28:48.16#ibcon#end of sib2, iclass 3, count 0 2006.285.08:28:48.16#ibcon#*after write, iclass 3, count 0 2006.285.08:28:48.16#ibcon#*before return 0, iclass 3, count 0 2006.285.08:28:48.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:28:48.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:28:48.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.08:28:48.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.08:28:48.16$vck44/vb=5,4 2006.285.08:28:48.16#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.08:28:48.16#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.08:28:48.16#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:48.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:28:48.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:28:48.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:28:48.22#ibcon#enter wrdev, iclass 5, count 2 2006.285.08:28:48.22#ibcon#first serial, iclass 5, count 2 2006.285.08:28:48.22#ibcon#enter sib2, iclass 5, count 2 2006.285.08:28:48.22#ibcon#flushed, iclass 5, count 2 2006.285.08:28:48.22#ibcon#about to write, iclass 5, count 2 2006.285.08:28:48.22#ibcon#wrote, iclass 5, count 2 2006.285.08:28:48.22#ibcon#about to read 3, iclass 5, count 2 2006.285.08:28:48.24#ibcon#read 3, iclass 5, count 2 2006.285.08:28:48.24#ibcon#about to read 4, iclass 5, count 2 2006.285.08:28:48.24#ibcon#read 4, iclass 5, count 2 2006.285.08:28:48.24#ibcon#about to read 5, iclass 5, count 2 2006.285.08:28:48.24#ibcon#read 5, iclass 5, count 2 2006.285.08:28:48.24#ibcon#about to read 6, iclass 5, count 2 2006.285.08:28:48.24#ibcon#read 6, iclass 5, count 2 2006.285.08:28:48.24#ibcon#end of sib2, iclass 5, count 2 2006.285.08:28:48.24#ibcon#*mode == 0, iclass 5, count 2 2006.285.08:28:48.24#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.08:28:48.24#ibcon#[27=AT05-04\r\n] 2006.285.08:28:48.24#ibcon#*before write, iclass 5, count 2 2006.285.08:28:48.24#ibcon#enter sib2, iclass 5, count 2 2006.285.08:28:48.24#ibcon#flushed, iclass 5, count 2 2006.285.08:28:48.24#ibcon#about to write, iclass 5, count 2 2006.285.08:28:48.24#ibcon#wrote, iclass 5, count 2 2006.285.08:28:48.24#ibcon#about to read 3, iclass 5, count 2 2006.285.08:28:48.27#ibcon#read 3, iclass 5, count 2 2006.285.08:28:48.27#ibcon#about to read 4, iclass 5, count 2 2006.285.08:28:48.27#ibcon#read 4, iclass 5, count 2 2006.285.08:28:48.27#ibcon#about to read 5, iclass 5, count 2 2006.285.08:28:48.27#ibcon#read 5, iclass 5, count 2 2006.285.08:28:48.27#ibcon#about to read 6, iclass 5, count 2 2006.285.08:28:48.27#ibcon#read 6, iclass 5, count 2 2006.285.08:28:48.27#ibcon#end of sib2, iclass 5, count 2 2006.285.08:28:48.27#ibcon#*after write, iclass 5, count 2 2006.285.08:28:48.27#ibcon#*before return 0, iclass 5, count 2 2006.285.08:28:48.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:28:48.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:28:48.27#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.08:28:48.27#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:48.27#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:28:48.39#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:28:48.39#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:28:48.39#ibcon#enter wrdev, iclass 5, count 0 2006.285.08:28:48.39#ibcon#first serial, iclass 5, count 0 2006.285.08:28:48.39#ibcon#enter sib2, iclass 5, count 0 2006.285.08:28:48.39#ibcon#flushed, iclass 5, count 0 2006.285.08:28:48.39#ibcon#about to write, iclass 5, count 0 2006.285.08:28:48.39#ibcon#wrote, iclass 5, count 0 2006.285.08:28:48.39#ibcon#about to read 3, iclass 5, count 0 2006.285.08:28:48.41#ibcon#read 3, iclass 5, count 0 2006.285.08:28:48.41#ibcon#about to read 4, iclass 5, count 0 2006.285.08:28:48.41#ibcon#read 4, iclass 5, count 0 2006.285.08:28:48.41#ibcon#about to read 5, iclass 5, count 0 2006.285.08:28:48.41#ibcon#read 5, iclass 5, count 0 2006.285.08:28:48.41#ibcon#about to read 6, iclass 5, count 0 2006.285.08:28:48.41#ibcon#read 6, iclass 5, count 0 2006.285.08:28:48.41#ibcon#end of sib2, iclass 5, count 0 2006.285.08:28:48.41#ibcon#*mode == 0, iclass 5, count 0 2006.285.08:28:48.41#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.08:28:48.41#ibcon#[27=USB\r\n] 2006.285.08:28:48.41#ibcon#*before write, iclass 5, count 0 2006.285.08:28:48.41#ibcon#enter sib2, iclass 5, count 0 2006.285.08:28:48.41#ibcon#flushed, iclass 5, count 0 2006.285.08:28:48.41#ibcon#about to write, iclass 5, count 0 2006.285.08:28:48.41#ibcon#wrote, iclass 5, count 0 2006.285.08:28:48.41#ibcon#about to read 3, iclass 5, count 0 2006.285.08:28:48.44#ibcon#read 3, iclass 5, count 0 2006.285.08:28:48.44#ibcon#about to read 4, iclass 5, count 0 2006.285.08:28:48.44#ibcon#read 4, iclass 5, count 0 2006.285.08:28:48.44#ibcon#about to read 5, iclass 5, count 0 2006.285.08:28:48.44#ibcon#read 5, iclass 5, count 0 2006.285.08:28:48.44#ibcon#about to read 6, iclass 5, count 0 2006.285.08:28:48.44#ibcon#read 6, iclass 5, count 0 2006.285.08:28:48.44#ibcon#end of sib2, iclass 5, count 0 2006.285.08:28:48.44#ibcon#*after write, iclass 5, count 0 2006.285.08:28:48.44#ibcon#*before return 0, iclass 5, count 0 2006.285.08:28:48.44#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:28:48.44#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:28:48.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.08:28:48.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.08:28:48.44$vck44/vblo=6,719.99 2006.285.08:28:48.44#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.08:28:48.44#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.08:28:48.44#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:48.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:28:48.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:28:48.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:28:48.44#ibcon#enter wrdev, iclass 7, count 0 2006.285.08:28:48.44#ibcon#first serial, iclass 7, count 0 2006.285.08:28:48.44#ibcon#enter sib2, iclass 7, count 0 2006.285.08:28:48.44#ibcon#flushed, iclass 7, count 0 2006.285.08:28:48.44#ibcon#about to write, iclass 7, count 0 2006.285.08:28:48.44#ibcon#wrote, iclass 7, count 0 2006.285.08:28:48.44#ibcon#about to read 3, iclass 7, count 0 2006.285.08:28:48.46#ibcon#read 3, iclass 7, count 0 2006.285.08:28:48.46#ibcon#about to read 4, iclass 7, count 0 2006.285.08:28:48.46#ibcon#read 4, iclass 7, count 0 2006.285.08:28:48.46#ibcon#about to read 5, iclass 7, count 0 2006.285.08:28:48.46#ibcon#read 5, iclass 7, count 0 2006.285.08:28:48.46#ibcon#about to read 6, iclass 7, count 0 2006.285.08:28:48.46#ibcon#read 6, iclass 7, count 0 2006.285.08:28:48.46#ibcon#end of sib2, iclass 7, count 0 2006.285.08:28:48.46#ibcon#*mode == 0, iclass 7, count 0 2006.285.08:28:48.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.08:28:48.46#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:28:48.46#ibcon#*before write, iclass 7, count 0 2006.285.08:28:48.46#ibcon#enter sib2, iclass 7, count 0 2006.285.08:28:48.46#ibcon#flushed, iclass 7, count 0 2006.285.08:28:48.46#ibcon#about to write, iclass 7, count 0 2006.285.08:28:48.46#ibcon#wrote, iclass 7, count 0 2006.285.08:28:48.46#ibcon#about to read 3, iclass 7, count 0 2006.285.08:28:48.50#ibcon#read 3, iclass 7, count 0 2006.285.08:28:48.50#ibcon#about to read 4, iclass 7, count 0 2006.285.08:28:48.50#ibcon#read 4, iclass 7, count 0 2006.285.08:28:48.50#ibcon#about to read 5, iclass 7, count 0 2006.285.08:28:48.50#ibcon#read 5, iclass 7, count 0 2006.285.08:28:48.50#ibcon#about to read 6, iclass 7, count 0 2006.285.08:28:48.50#ibcon#read 6, iclass 7, count 0 2006.285.08:28:48.50#ibcon#end of sib2, iclass 7, count 0 2006.285.08:28:48.50#ibcon#*after write, iclass 7, count 0 2006.285.08:28:48.50#ibcon#*before return 0, iclass 7, count 0 2006.285.08:28:48.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:28:48.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:28:48.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.08:28:48.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.08:28:48.50$vck44/vb=6,3 2006.285.08:28:48.50#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.08:28:48.50#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.08:28:48.50#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:48.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:28:48.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:28:48.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:28:48.56#ibcon#enter wrdev, iclass 11, count 2 2006.285.08:28:48.56#ibcon#first serial, iclass 11, count 2 2006.285.08:28:48.56#ibcon#enter sib2, iclass 11, count 2 2006.285.08:28:48.56#ibcon#flushed, iclass 11, count 2 2006.285.08:28:48.56#ibcon#about to write, iclass 11, count 2 2006.285.08:28:48.56#ibcon#wrote, iclass 11, count 2 2006.285.08:28:48.56#ibcon#about to read 3, iclass 11, count 2 2006.285.08:28:48.58#ibcon#read 3, iclass 11, count 2 2006.285.08:28:48.58#ibcon#about to read 4, iclass 11, count 2 2006.285.08:28:48.58#ibcon#read 4, iclass 11, count 2 2006.285.08:28:48.58#ibcon#about to read 5, iclass 11, count 2 2006.285.08:28:48.58#ibcon#read 5, iclass 11, count 2 2006.285.08:28:48.58#ibcon#about to read 6, iclass 11, count 2 2006.285.08:28:48.58#ibcon#read 6, iclass 11, count 2 2006.285.08:28:48.58#ibcon#end of sib2, iclass 11, count 2 2006.285.08:28:48.58#ibcon#*mode == 0, iclass 11, count 2 2006.285.08:28:48.58#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.08:28:48.58#ibcon#[27=AT06-03\r\n] 2006.285.08:28:48.58#ibcon#*before write, iclass 11, count 2 2006.285.08:28:48.58#ibcon#enter sib2, iclass 11, count 2 2006.285.08:28:48.58#ibcon#flushed, iclass 11, count 2 2006.285.08:28:48.58#ibcon#about to write, iclass 11, count 2 2006.285.08:28:48.58#ibcon#wrote, iclass 11, count 2 2006.285.08:28:48.58#ibcon#about to read 3, iclass 11, count 2 2006.285.08:28:48.61#ibcon#read 3, iclass 11, count 2 2006.285.08:28:48.61#ibcon#about to read 4, iclass 11, count 2 2006.285.08:28:48.61#ibcon#read 4, iclass 11, count 2 2006.285.08:28:48.61#ibcon#about to read 5, iclass 11, count 2 2006.285.08:28:48.61#ibcon#read 5, iclass 11, count 2 2006.285.08:28:48.61#ibcon#about to read 6, iclass 11, count 2 2006.285.08:28:48.61#ibcon#read 6, iclass 11, count 2 2006.285.08:28:48.61#ibcon#end of sib2, iclass 11, count 2 2006.285.08:28:48.61#ibcon#*after write, iclass 11, count 2 2006.285.08:28:48.61#ibcon#*before return 0, iclass 11, count 2 2006.285.08:28:48.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:28:48.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:28:48.61#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.08:28:48.61#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:48.61#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:28:48.73#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:28:48.73#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:28:48.73#ibcon#enter wrdev, iclass 11, count 0 2006.285.08:28:48.73#ibcon#first serial, iclass 11, count 0 2006.285.08:28:48.73#ibcon#enter sib2, iclass 11, count 0 2006.285.08:28:48.73#ibcon#flushed, iclass 11, count 0 2006.285.08:28:48.73#ibcon#about to write, iclass 11, count 0 2006.285.08:28:48.73#ibcon#wrote, iclass 11, count 0 2006.285.08:28:48.73#ibcon#about to read 3, iclass 11, count 0 2006.285.08:28:48.75#ibcon#read 3, iclass 11, count 0 2006.285.08:28:48.75#ibcon#about to read 4, iclass 11, count 0 2006.285.08:28:48.75#ibcon#read 4, iclass 11, count 0 2006.285.08:28:48.75#ibcon#about to read 5, iclass 11, count 0 2006.285.08:28:48.75#ibcon#read 5, iclass 11, count 0 2006.285.08:28:48.75#ibcon#about to read 6, iclass 11, count 0 2006.285.08:28:48.75#ibcon#read 6, iclass 11, count 0 2006.285.08:28:48.75#ibcon#end of sib2, iclass 11, count 0 2006.285.08:28:48.75#ibcon#*mode == 0, iclass 11, count 0 2006.285.08:28:48.75#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.08:28:48.75#ibcon#[27=USB\r\n] 2006.285.08:28:48.75#ibcon#*before write, iclass 11, count 0 2006.285.08:28:48.75#ibcon#enter sib2, iclass 11, count 0 2006.285.08:28:48.75#ibcon#flushed, iclass 11, count 0 2006.285.08:28:48.75#ibcon#about to write, iclass 11, count 0 2006.285.08:28:48.75#ibcon#wrote, iclass 11, count 0 2006.285.08:28:48.75#ibcon#about to read 3, iclass 11, count 0 2006.285.08:28:48.78#ibcon#read 3, iclass 11, count 0 2006.285.08:28:48.78#ibcon#about to read 4, iclass 11, count 0 2006.285.08:28:48.78#ibcon#read 4, iclass 11, count 0 2006.285.08:28:48.78#ibcon#about to read 5, iclass 11, count 0 2006.285.08:28:48.78#ibcon#read 5, iclass 11, count 0 2006.285.08:28:48.78#ibcon#about to read 6, iclass 11, count 0 2006.285.08:28:48.78#ibcon#read 6, iclass 11, count 0 2006.285.08:28:48.78#ibcon#end of sib2, iclass 11, count 0 2006.285.08:28:48.78#ibcon#*after write, iclass 11, count 0 2006.285.08:28:48.78#ibcon#*before return 0, iclass 11, count 0 2006.285.08:28:48.78#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:28:48.78#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:28:48.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.08:28:48.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.08:28:48.78$vck44/vblo=7,734.99 2006.285.08:28:48.78#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.08:28:48.78#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.08:28:48.78#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:48.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:28:48.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:28:48.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:28:48.78#ibcon#enter wrdev, iclass 13, count 0 2006.285.08:28:48.78#ibcon#first serial, iclass 13, count 0 2006.285.08:28:48.78#ibcon#enter sib2, iclass 13, count 0 2006.285.08:28:48.78#ibcon#flushed, iclass 13, count 0 2006.285.08:28:48.78#ibcon#about to write, iclass 13, count 0 2006.285.08:28:48.78#ibcon#wrote, iclass 13, count 0 2006.285.08:28:48.78#ibcon#about to read 3, iclass 13, count 0 2006.285.08:28:48.80#ibcon#read 3, iclass 13, count 0 2006.285.08:28:48.80#ibcon#about to read 4, iclass 13, count 0 2006.285.08:28:48.80#ibcon#read 4, iclass 13, count 0 2006.285.08:28:48.80#ibcon#about to read 5, iclass 13, count 0 2006.285.08:28:48.80#ibcon#read 5, iclass 13, count 0 2006.285.08:28:48.80#ibcon#about to read 6, iclass 13, count 0 2006.285.08:28:48.80#ibcon#read 6, iclass 13, count 0 2006.285.08:28:48.80#ibcon#end of sib2, iclass 13, count 0 2006.285.08:28:48.80#ibcon#*mode == 0, iclass 13, count 0 2006.285.08:28:48.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.08:28:48.80#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:28:48.80#ibcon#*before write, iclass 13, count 0 2006.285.08:28:48.80#ibcon#enter sib2, iclass 13, count 0 2006.285.08:28:48.80#ibcon#flushed, iclass 13, count 0 2006.285.08:28:48.80#ibcon#about to write, iclass 13, count 0 2006.285.08:28:48.80#ibcon#wrote, iclass 13, count 0 2006.285.08:28:48.80#ibcon#about to read 3, iclass 13, count 0 2006.285.08:28:48.84#ibcon#read 3, iclass 13, count 0 2006.285.08:28:48.84#ibcon#about to read 4, iclass 13, count 0 2006.285.08:28:48.84#ibcon#read 4, iclass 13, count 0 2006.285.08:28:48.84#ibcon#about to read 5, iclass 13, count 0 2006.285.08:28:48.84#ibcon#read 5, iclass 13, count 0 2006.285.08:28:48.84#ibcon#about to read 6, iclass 13, count 0 2006.285.08:28:48.84#ibcon#read 6, iclass 13, count 0 2006.285.08:28:48.84#ibcon#end of sib2, iclass 13, count 0 2006.285.08:28:48.84#ibcon#*after write, iclass 13, count 0 2006.285.08:28:48.84#ibcon#*before return 0, iclass 13, count 0 2006.285.08:28:48.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:28:48.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:28:48.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.08:28:48.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.08:28:48.84$vck44/vb=7,4 2006.285.08:28:48.84#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.08:28:48.84#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.08:28:48.84#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:48.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:28:48.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:28:48.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:28:48.90#ibcon#enter wrdev, iclass 15, count 2 2006.285.08:28:48.90#ibcon#first serial, iclass 15, count 2 2006.285.08:28:48.90#ibcon#enter sib2, iclass 15, count 2 2006.285.08:28:48.90#ibcon#flushed, iclass 15, count 2 2006.285.08:28:48.90#ibcon#about to write, iclass 15, count 2 2006.285.08:28:48.90#ibcon#wrote, iclass 15, count 2 2006.285.08:28:48.90#ibcon#about to read 3, iclass 15, count 2 2006.285.08:28:48.92#ibcon#read 3, iclass 15, count 2 2006.285.08:28:48.92#ibcon#about to read 4, iclass 15, count 2 2006.285.08:28:48.92#ibcon#read 4, iclass 15, count 2 2006.285.08:28:48.92#ibcon#about to read 5, iclass 15, count 2 2006.285.08:28:48.92#ibcon#read 5, iclass 15, count 2 2006.285.08:28:48.92#ibcon#about to read 6, iclass 15, count 2 2006.285.08:28:48.92#ibcon#read 6, iclass 15, count 2 2006.285.08:28:48.92#ibcon#end of sib2, iclass 15, count 2 2006.285.08:28:48.92#ibcon#*mode == 0, iclass 15, count 2 2006.285.08:28:48.92#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.08:28:48.92#ibcon#[27=AT07-04\r\n] 2006.285.08:28:48.92#ibcon#*before write, iclass 15, count 2 2006.285.08:28:48.92#ibcon#enter sib2, iclass 15, count 2 2006.285.08:28:48.92#ibcon#flushed, iclass 15, count 2 2006.285.08:28:48.92#ibcon#about to write, iclass 15, count 2 2006.285.08:28:48.92#ibcon#wrote, iclass 15, count 2 2006.285.08:28:48.92#ibcon#about to read 3, iclass 15, count 2 2006.285.08:28:48.95#ibcon#read 3, iclass 15, count 2 2006.285.08:28:48.95#ibcon#about to read 4, iclass 15, count 2 2006.285.08:28:48.95#ibcon#read 4, iclass 15, count 2 2006.285.08:28:48.95#ibcon#about to read 5, iclass 15, count 2 2006.285.08:28:48.95#ibcon#read 5, iclass 15, count 2 2006.285.08:28:48.95#ibcon#about to read 6, iclass 15, count 2 2006.285.08:28:48.95#ibcon#read 6, iclass 15, count 2 2006.285.08:28:48.95#ibcon#end of sib2, iclass 15, count 2 2006.285.08:28:48.95#ibcon#*after write, iclass 15, count 2 2006.285.08:28:48.95#ibcon#*before return 0, iclass 15, count 2 2006.285.08:28:48.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:28:48.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:28:48.95#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.08:28:48.95#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:48.95#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:28:49.07#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:28:49.07#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:28:49.07#ibcon#enter wrdev, iclass 15, count 0 2006.285.08:28:49.07#ibcon#first serial, iclass 15, count 0 2006.285.08:28:49.07#ibcon#enter sib2, iclass 15, count 0 2006.285.08:28:49.07#ibcon#flushed, iclass 15, count 0 2006.285.08:28:49.07#ibcon#about to write, iclass 15, count 0 2006.285.08:28:49.07#ibcon#wrote, iclass 15, count 0 2006.285.08:28:49.07#ibcon#about to read 3, iclass 15, count 0 2006.285.08:28:49.09#ibcon#read 3, iclass 15, count 0 2006.285.08:28:49.09#ibcon#about to read 4, iclass 15, count 0 2006.285.08:28:49.09#ibcon#read 4, iclass 15, count 0 2006.285.08:28:49.09#ibcon#about to read 5, iclass 15, count 0 2006.285.08:28:49.09#ibcon#read 5, iclass 15, count 0 2006.285.08:28:49.09#ibcon#about to read 6, iclass 15, count 0 2006.285.08:28:49.09#ibcon#read 6, iclass 15, count 0 2006.285.08:28:49.09#ibcon#end of sib2, iclass 15, count 0 2006.285.08:28:49.09#ibcon#*mode == 0, iclass 15, count 0 2006.285.08:28:49.09#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.08:28:49.09#ibcon#[27=USB\r\n] 2006.285.08:28:49.09#ibcon#*before write, iclass 15, count 0 2006.285.08:28:49.09#ibcon#enter sib2, iclass 15, count 0 2006.285.08:28:49.09#ibcon#flushed, iclass 15, count 0 2006.285.08:28:49.09#ibcon#about to write, iclass 15, count 0 2006.285.08:28:49.09#ibcon#wrote, iclass 15, count 0 2006.285.08:28:49.09#ibcon#about to read 3, iclass 15, count 0 2006.285.08:28:49.12#ibcon#read 3, iclass 15, count 0 2006.285.08:28:49.12#ibcon#about to read 4, iclass 15, count 0 2006.285.08:28:49.12#ibcon#read 4, iclass 15, count 0 2006.285.08:28:49.12#ibcon#about to read 5, iclass 15, count 0 2006.285.08:28:49.12#ibcon#read 5, iclass 15, count 0 2006.285.08:28:49.12#ibcon#about to read 6, iclass 15, count 0 2006.285.08:28:49.12#ibcon#read 6, iclass 15, count 0 2006.285.08:28:49.12#ibcon#end of sib2, iclass 15, count 0 2006.285.08:28:49.12#ibcon#*after write, iclass 15, count 0 2006.285.08:28:49.12#ibcon#*before return 0, iclass 15, count 0 2006.285.08:28:49.12#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:28:49.12#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:28:49.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.08:28:49.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.08:28:49.12$vck44/vblo=8,744.99 2006.285.08:28:49.12#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.08:28:49.12#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.08:28:49.12#ibcon#ireg 17 cls_cnt 0 2006.285.08:28:49.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:28:49.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:28:49.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:28:49.12#ibcon#enter wrdev, iclass 17, count 0 2006.285.08:28:49.12#ibcon#first serial, iclass 17, count 0 2006.285.08:28:49.12#ibcon#enter sib2, iclass 17, count 0 2006.285.08:28:49.12#ibcon#flushed, iclass 17, count 0 2006.285.08:28:49.12#ibcon#about to write, iclass 17, count 0 2006.285.08:28:49.12#ibcon#wrote, iclass 17, count 0 2006.285.08:28:49.12#ibcon#about to read 3, iclass 17, count 0 2006.285.08:28:49.14#ibcon#read 3, iclass 17, count 0 2006.285.08:28:49.14#ibcon#about to read 4, iclass 17, count 0 2006.285.08:28:49.14#ibcon#read 4, iclass 17, count 0 2006.285.08:28:49.14#ibcon#about to read 5, iclass 17, count 0 2006.285.08:28:49.14#ibcon#read 5, iclass 17, count 0 2006.285.08:28:49.14#ibcon#about to read 6, iclass 17, count 0 2006.285.08:28:49.14#ibcon#read 6, iclass 17, count 0 2006.285.08:28:49.14#ibcon#end of sib2, iclass 17, count 0 2006.285.08:28:49.14#ibcon#*mode == 0, iclass 17, count 0 2006.285.08:28:49.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.08:28:49.14#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:28:49.14#ibcon#*before write, iclass 17, count 0 2006.285.08:28:49.14#ibcon#enter sib2, iclass 17, count 0 2006.285.08:28:49.14#ibcon#flushed, iclass 17, count 0 2006.285.08:28:49.14#ibcon#about to write, iclass 17, count 0 2006.285.08:28:49.14#ibcon#wrote, iclass 17, count 0 2006.285.08:28:49.14#ibcon#about to read 3, iclass 17, count 0 2006.285.08:28:49.18#ibcon#read 3, iclass 17, count 0 2006.285.08:28:49.18#ibcon#about to read 4, iclass 17, count 0 2006.285.08:28:49.18#ibcon#read 4, iclass 17, count 0 2006.285.08:28:49.18#ibcon#about to read 5, iclass 17, count 0 2006.285.08:28:49.18#ibcon#read 5, iclass 17, count 0 2006.285.08:28:49.18#ibcon#about to read 6, iclass 17, count 0 2006.285.08:28:49.18#ibcon#read 6, iclass 17, count 0 2006.285.08:28:49.18#ibcon#end of sib2, iclass 17, count 0 2006.285.08:28:49.18#ibcon#*after write, iclass 17, count 0 2006.285.08:28:49.18#ibcon#*before return 0, iclass 17, count 0 2006.285.08:28:49.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:28:49.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:28:49.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.08:28:49.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.08:28:49.18$vck44/vb=8,4 2006.285.08:28:49.18#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.08:28:49.18#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.08:28:49.18#ibcon#ireg 11 cls_cnt 2 2006.285.08:28:49.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:28:49.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:28:49.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:28:49.24#ibcon#enter wrdev, iclass 19, count 2 2006.285.08:28:49.24#ibcon#first serial, iclass 19, count 2 2006.285.08:28:49.24#ibcon#enter sib2, iclass 19, count 2 2006.285.08:28:49.24#ibcon#flushed, iclass 19, count 2 2006.285.08:28:49.24#ibcon#about to write, iclass 19, count 2 2006.285.08:28:49.24#ibcon#wrote, iclass 19, count 2 2006.285.08:28:49.24#ibcon#about to read 3, iclass 19, count 2 2006.285.08:28:49.26#ibcon#read 3, iclass 19, count 2 2006.285.08:28:49.26#ibcon#about to read 4, iclass 19, count 2 2006.285.08:28:49.26#ibcon#read 4, iclass 19, count 2 2006.285.08:28:49.26#ibcon#about to read 5, iclass 19, count 2 2006.285.08:28:49.26#ibcon#read 5, iclass 19, count 2 2006.285.08:28:49.26#ibcon#about to read 6, iclass 19, count 2 2006.285.08:28:49.26#ibcon#read 6, iclass 19, count 2 2006.285.08:28:49.26#ibcon#end of sib2, iclass 19, count 2 2006.285.08:28:49.26#ibcon#*mode == 0, iclass 19, count 2 2006.285.08:28:49.26#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.08:28:49.26#ibcon#[27=AT08-04\r\n] 2006.285.08:28:49.26#ibcon#*before write, iclass 19, count 2 2006.285.08:28:49.26#ibcon#enter sib2, iclass 19, count 2 2006.285.08:28:49.26#ibcon#flushed, iclass 19, count 2 2006.285.08:28:49.26#ibcon#about to write, iclass 19, count 2 2006.285.08:28:49.26#ibcon#wrote, iclass 19, count 2 2006.285.08:28:49.26#ibcon#about to read 3, iclass 19, count 2 2006.285.08:28:49.29#ibcon#read 3, iclass 19, count 2 2006.285.08:28:49.29#ibcon#about to read 4, iclass 19, count 2 2006.285.08:28:49.29#ibcon#read 4, iclass 19, count 2 2006.285.08:28:49.29#ibcon#about to read 5, iclass 19, count 2 2006.285.08:28:49.29#ibcon#read 5, iclass 19, count 2 2006.285.08:28:49.29#ibcon#about to read 6, iclass 19, count 2 2006.285.08:28:49.29#ibcon#read 6, iclass 19, count 2 2006.285.08:28:49.29#ibcon#end of sib2, iclass 19, count 2 2006.285.08:28:49.29#ibcon#*after write, iclass 19, count 2 2006.285.08:28:49.29#ibcon#*before return 0, iclass 19, count 2 2006.285.08:28:49.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:28:49.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:28:49.29#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.08:28:49.29#ibcon#ireg 7 cls_cnt 0 2006.285.08:28:49.29#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:28:49.41#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:28:49.41#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:28:49.41#ibcon#enter wrdev, iclass 19, count 0 2006.285.08:28:49.41#ibcon#first serial, iclass 19, count 0 2006.285.08:28:49.41#ibcon#enter sib2, iclass 19, count 0 2006.285.08:28:49.41#ibcon#flushed, iclass 19, count 0 2006.285.08:28:49.41#ibcon#about to write, iclass 19, count 0 2006.285.08:28:49.41#ibcon#wrote, iclass 19, count 0 2006.285.08:28:49.41#ibcon#about to read 3, iclass 19, count 0 2006.285.08:28:49.43#ibcon#read 3, iclass 19, count 0 2006.285.08:28:49.43#ibcon#about to read 4, iclass 19, count 0 2006.285.08:28:49.43#ibcon#read 4, iclass 19, count 0 2006.285.08:28:49.43#ibcon#about to read 5, iclass 19, count 0 2006.285.08:28:49.43#ibcon#read 5, iclass 19, count 0 2006.285.08:28:49.43#ibcon#about to read 6, iclass 19, count 0 2006.285.08:28:49.43#ibcon#read 6, iclass 19, count 0 2006.285.08:28:49.43#ibcon#end of sib2, iclass 19, count 0 2006.285.08:28:49.43#ibcon#*mode == 0, iclass 19, count 0 2006.285.08:28:49.43#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.08:28:49.43#ibcon#[27=USB\r\n] 2006.285.08:28:49.43#ibcon#*before write, iclass 19, count 0 2006.285.08:28:49.43#ibcon#enter sib2, iclass 19, count 0 2006.285.08:28:49.43#ibcon#flushed, iclass 19, count 0 2006.285.08:28:49.43#ibcon#about to write, iclass 19, count 0 2006.285.08:28:49.43#ibcon#wrote, iclass 19, count 0 2006.285.08:28:49.43#ibcon#about to read 3, iclass 19, count 0 2006.285.08:28:49.46#ibcon#read 3, iclass 19, count 0 2006.285.08:28:49.46#ibcon#about to read 4, iclass 19, count 0 2006.285.08:28:49.46#ibcon#read 4, iclass 19, count 0 2006.285.08:28:49.46#ibcon#about to read 5, iclass 19, count 0 2006.285.08:28:49.46#ibcon#read 5, iclass 19, count 0 2006.285.08:28:49.46#ibcon#about to read 6, iclass 19, count 0 2006.285.08:28:49.46#ibcon#read 6, iclass 19, count 0 2006.285.08:28:49.46#ibcon#end of sib2, iclass 19, count 0 2006.285.08:28:49.46#ibcon#*after write, iclass 19, count 0 2006.285.08:28:49.46#ibcon#*before return 0, iclass 19, count 0 2006.285.08:28:49.46#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:28:49.46#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:28:49.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.08:28:49.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.08:28:49.46$vck44/vabw=wide 2006.285.08:28:49.46#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.08:28:49.46#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.08:28:49.46#ibcon#ireg 8 cls_cnt 0 2006.285.08:28:49.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:28:49.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:28:49.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:28:49.46#ibcon#enter wrdev, iclass 21, count 0 2006.285.08:28:49.46#ibcon#first serial, iclass 21, count 0 2006.285.08:28:49.46#ibcon#enter sib2, iclass 21, count 0 2006.285.08:28:49.46#ibcon#flushed, iclass 21, count 0 2006.285.08:28:49.46#ibcon#about to write, iclass 21, count 0 2006.285.08:28:49.46#ibcon#wrote, iclass 21, count 0 2006.285.08:28:49.46#ibcon#about to read 3, iclass 21, count 0 2006.285.08:28:49.48#ibcon#read 3, iclass 21, count 0 2006.285.08:28:49.48#ibcon#about to read 4, iclass 21, count 0 2006.285.08:28:49.48#ibcon#read 4, iclass 21, count 0 2006.285.08:28:49.48#ibcon#about to read 5, iclass 21, count 0 2006.285.08:28:49.48#ibcon#read 5, iclass 21, count 0 2006.285.08:28:49.48#ibcon#about to read 6, iclass 21, count 0 2006.285.08:28:49.48#ibcon#read 6, iclass 21, count 0 2006.285.08:28:49.48#ibcon#end of sib2, iclass 21, count 0 2006.285.08:28:49.48#ibcon#*mode == 0, iclass 21, count 0 2006.285.08:28:49.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.08:28:49.48#ibcon#[25=BW32\r\n] 2006.285.08:28:49.48#ibcon#*before write, iclass 21, count 0 2006.285.08:28:49.48#ibcon#enter sib2, iclass 21, count 0 2006.285.08:28:49.48#ibcon#flushed, iclass 21, count 0 2006.285.08:28:49.48#ibcon#about to write, iclass 21, count 0 2006.285.08:28:49.48#ibcon#wrote, iclass 21, count 0 2006.285.08:28:49.48#ibcon#about to read 3, iclass 21, count 0 2006.285.08:28:49.51#ibcon#read 3, iclass 21, count 0 2006.285.08:28:49.51#ibcon#about to read 4, iclass 21, count 0 2006.285.08:28:49.51#ibcon#read 4, iclass 21, count 0 2006.285.08:28:49.51#ibcon#about to read 5, iclass 21, count 0 2006.285.08:28:49.51#ibcon#read 5, iclass 21, count 0 2006.285.08:28:49.51#ibcon#about to read 6, iclass 21, count 0 2006.285.08:28:49.51#ibcon#read 6, iclass 21, count 0 2006.285.08:28:49.51#ibcon#end of sib2, iclass 21, count 0 2006.285.08:28:49.51#ibcon#*after write, iclass 21, count 0 2006.285.08:28:49.51#ibcon#*before return 0, iclass 21, count 0 2006.285.08:28:49.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:28:49.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:28:49.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.08:28:49.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.08:28:49.51$vck44/vbbw=wide 2006.285.08:28:49.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.08:28:49.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.08:28:49.51#ibcon#ireg 8 cls_cnt 0 2006.285.08:28:49.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:28:49.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:28:49.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:28:49.58#ibcon#enter wrdev, iclass 23, count 0 2006.285.08:28:49.58#ibcon#first serial, iclass 23, count 0 2006.285.08:28:49.58#ibcon#enter sib2, iclass 23, count 0 2006.285.08:28:49.58#ibcon#flushed, iclass 23, count 0 2006.285.08:28:49.58#ibcon#about to write, iclass 23, count 0 2006.285.08:28:49.58#ibcon#wrote, iclass 23, count 0 2006.285.08:28:49.58#ibcon#about to read 3, iclass 23, count 0 2006.285.08:28:49.60#ibcon#read 3, iclass 23, count 0 2006.285.08:28:49.60#ibcon#about to read 4, iclass 23, count 0 2006.285.08:28:49.60#ibcon#read 4, iclass 23, count 0 2006.285.08:28:49.60#ibcon#about to read 5, iclass 23, count 0 2006.285.08:28:49.60#ibcon#read 5, iclass 23, count 0 2006.285.08:28:49.60#ibcon#about to read 6, iclass 23, count 0 2006.285.08:28:49.60#ibcon#read 6, iclass 23, count 0 2006.285.08:28:49.60#ibcon#end of sib2, iclass 23, count 0 2006.285.08:28:49.60#ibcon#*mode == 0, iclass 23, count 0 2006.285.08:28:49.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.08:28:49.60#ibcon#[27=BW32\r\n] 2006.285.08:28:49.60#ibcon#*before write, iclass 23, count 0 2006.285.08:28:49.60#ibcon#enter sib2, iclass 23, count 0 2006.285.08:28:49.60#ibcon#flushed, iclass 23, count 0 2006.285.08:28:49.60#ibcon#about to write, iclass 23, count 0 2006.285.08:28:49.60#ibcon#wrote, iclass 23, count 0 2006.285.08:28:49.60#ibcon#about to read 3, iclass 23, count 0 2006.285.08:28:49.63#ibcon#read 3, iclass 23, count 0 2006.285.08:28:49.63#ibcon#about to read 4, iclass 23, count 0 2006.285.08:28:49.63#ibcon#read 4, iclass 23, count 0 2006.285.08:28:49.63#ibcon#about to read 5, iclass 23, count 0 2006.285.08:28:49.63#ibcon#read 5, iclass 23, count 0 2006.285.08:28:49.63#ibcon#about to read 6, iclass 23, count 0 2006.285.08:28:49.63#ibcon#read 6, iclass 23, count 0 2006.285.08:28:49.63#ibcon#end of sib2, iclass 23, count 0 2006.285.08:28:49.63#ibcon#*after write, iclass 23, count 0 2006.285.08:28:49.63#ibcon#*before return 0, iclass 23, count 0 2006.285.08:28:49.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:28:49.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:28:49.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.08:28:49.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.08:28:49.63$setupk4/ifdk4 2006.285.08:28:49.63$ifdk4/lo= 2006.285.08:28:49.63$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:28:49.63$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:28:49.63$ifdk4/patch= 2006.285.08:28:49.63$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:28:49.63$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:28:49.63$setupk4/!*+20s 2006.285.08:28:53.31#abcon#<5=/04 1.7 3.0 22.26 811014.9\r\n> 2006.285.08:28:53.33#abcon#{5=INTERFACE CLEAR} 2006.285.08:28:53.39#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:28:56.14#trakl#Source acquired 2006.285.08:28:56.14#flagr#flagr/antenna,acquired 2006.285.08:29:03.48#abcon#<5=/04 1.7 3.0 22.25 811014.9\r\n> 2006.285.08:29:03.50#abcon#{5=INTERFACE CLEAR} 2006.285.08:29:03.56#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:29:04.14$setupk4/"tpicd 2006.285.08:29:04.14$setupk4/echo=off 2006.285.08:29:04.14$setupk4/xlog=off 2006.285.08:29:04.14:!2006.285.08:29:20 2006.285.08:29:20.00:preob 2006.285.08:29:21.14/onsource/TRACKING 2006.285.08:29:21.14:!2006.285.08:29:30 2006.285.08:29:30.00:"tape 2006.285.08:29:30.00:"st=record 2006.285.08:29:30.00:data_valid=on 2006.285.08:29:30.00:midob 2006.285.08:29:30.14/onsource/TRACKING 2006.285.08:29:30.14/wx/22.25,1014.9,81 2006.285.08:29:30.26/cable/+6.4766E-03 2006.285.08:29:31.35/va/01,07,usb,yes,32,34 2006.285.08:29:31.35/va/02,06,usb,yes,32,32 2006.285.08:29:31.35/va/03,07,usb,yes,31,33 2006.285.08:29:31.35/va/04,06,usb,yes,33,34 2006.285.08:29:31.35/va/05,03,usb,yes,32,33 2006.285.08:29:31.35/va/06,04,usb,yes,29,28 2006.285.08:29:31.35/va/07,04,usb,yes,29,30 2006.285.08:29:31.35/va/08,03,usb,yes,30,37 2006.285.08:29:31.58/valo/01,524.99,yes,locked 2006.285.08:29:31.58/valo/02,534.99,yes,locked 2006.285.08:29:31.58/valo/03,564.99,yes,locked 2006.285.08:29:31.58/valo/04,624.99,yes,locked 2006.285.08:29:31.58/valo/05,734.99,yes,locked 2006.285.08:29:31.58/valo/06,814.99,yes,locked 2006.285.08:29:31.58/valo/07,864.99,yes,locked 2006.285.08:29:31.58/valo/08,884.99,yes,locked 2006.285.08:29:32.67/vb/01,04,usb,yes,30,28 2006.285.08:29:32.67/vb/02,05,usb,yes,28,28 2006.285.08:29:32.67/vb/03,04,usb,yes,29,32 2006.285.08:29:32.67/vb/04,05,usb,yes,30,29 2006.285.08:29:32.67/vb/05,04,usb,yes,26,29 2006.285.08:29:32.67/vb/06,03,usb,yes,38,33 2006.285.08:29:32.67/vb/07,04,usb,yes,30,30 2006.285.08:29:32.67/vb/08,04,usb,yes,28,31 2006.285.08:29:32.90/vblo/01,629.99,yes,locked 2006.285.08:29:32.90/vblo/02,634.99,yes,locked 2006.285.08:29:32.90/vblo/03,649.99,yes,locked 2006.285.08:29:32.90/vblo/04,679.99,yes,locked 2006.285.08:29:32.90/vblo/05,709.99,yes,locked 2006.285.08:29:32.90/vblo/06,719.99,yes,locked 2006.285.08:29:32.90/vblo/07,734.99,yes,locked 2006.285.08:29:32.90/vblo/08,744.99,yes,locked 2006.285.08:29:33.05/vabw/8 2006.285.08:29:33.20/vbbw/8 2006.285.08:29:33.33/xfe/off,on,12.0 2006.285.08:29:33.71/ifatt/23,28,28,28 2006.285.08:29:34.07/fmout-gps/S +2.77E-07 2006.285.08:29:34.09:!2006.285.08:30:50 2006.285.08:30:50.00:data_valid=off 2006.285.08:30:50.00:"et 2006.285.08:30:50.00:!+3s 2006.285.08:30:53.01:"tape 2006.285.08:30:53.01:postob 2006.285.08:30:53.19/cable/+6.4758E-03 2006.285.08:30:53.19/wx/22.22,1014.9,81 2006.285.08:30:54.07/fmout-gps/S +2.80E-07 2006.285.08:30:54.07:scan_name=285-0832,jd0610,120 2006.285.08:30:54.07:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.285.08:30:55.13#flagr#flagr/antenna,new-source 2006.285.08:30:55.13:checkk5 2006.285.08:30:55.48/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:30:56.03/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:30:56.39/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:30:56.79/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:30:57.21/chk_obsdata//k5ts1/T2850829??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.285.08:30:57.60/chk_obsdata//k5ts2/T2850829??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.285.08:30:58.02/chk_obsdata//k5ts3/T2850829??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.285.08:30:58.38/chk_obsdata//k5ts4/T2850829??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.285.08:30:59.37/k5log//k5ts1_log_newline 2006.285.08:31:00.11/k5log//k5ts2_log_newline 2006.285.08:31:00.88/k5log//k5ts3_log_newline 2006.285.08:31:01.80/k5log//k5ts4_log_newline 2006.285.08:31:01.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:31:01.83:setupk4=1 2006.285.08:31:01.83$setupk4/echo=on 2006.285.08:31:01.83$setupk4/pcalon 2006.285.08:31:01.83$pcalon/"no phase cal control is implemented here 2006.285.08:31:01.83$setupk4/"tpicd=stop 2006.285.08:31:01.83$setupk4/"rec=synch_on 2006.285.08:31:01.83$setupk4/"rec_mode=128 2006.285.08:31:01.83$setupk4/!* 2006.285.08:31:01.83$setupk4/recpk4 2006.285.08:31:01.83$recpk4/recpatch= 2006.285.08:31:01.83$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:31:01.83$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:31:01.83$setupk4/vck44 2006.285.08:31:01.83$vck44/valo=1,524.99 2006.285.08:31:01.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.08:31:01.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.08:31:01.83#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:01.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:31:01.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:31:01.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:31:01.83#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:31:01.83#ibcon#first serial, iclass 6, count 0 2006.285.08:31:01.83#ibcon#enter sib2, iclass 6, count 0 2006.285.08:31:01.83#ibcon#flushed, iclass 6, count 0 2006.285.08:31:01.83#ibcon#about to write, iclass 6, count 0 2006.285.08:31:01.83#ibcon#wrote, iclass 6, count 0 2006.285.08:31:01.83#ibcon#about to read 3, iclass 6, count 0 2006.285.08:31:01.85#ibcon#read 3, iclass 6, count 0 2006.285.08:31:01.85#ibcon#about to read 4, iclass 6, count 0 2006.285.08:31:01.85#ibcon#read 4, iclass 6, count 0 2006.285.08:31:01.85#ibcon#about to read 5, iclass 6, count 0 2006.285.08:31:01.85#ibcon#read 5, iclass 6, count 0 2006.285.08:31:01.85#ibcon#about to read 6, iclass 6, count 0 2006.285.08:31:01.85#ibcon#read 6, iclass 6, count 0 2006.285.08:31:01.85#ibcon#end of sib2, iclass 6, count 0 2006.285.08:31:01.85#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:31:01.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:31:01.85#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:31:01.85#ibcon#*before write, iclass 6, count 0 2006.285.08:31:01.85#ibcon#enter sib2, iclass 6, count 0 2006.285.08:31:01.85#ibcon#flushed, iclass 6, count 0 2006.285.08:31:01.85#ibcon#about to write, iclass 6, count 0 2006.285.08:31:01.85#ibcon#wrote, iclass 6, count 0 2006.285.08:31:01.85#ibcon#about to read 3, iclass 6, count 0 2006.285.08:31:01.90#ibcon#read 3, iclass 6, count 0 2006.285.08:31:01.90#ibcon#about to read 4, iclass 6, count 0 2006.285.08:31:01.90#ibcon#read 4, iclass 6, count 0 2006.285.08:31:01.90#ibcon#about to read 5, iclass 6, count 0 2006.285.08:31:01.90#ibcon#read 5, iclass 6, count 0 2006.285.08:31:01.90#ibcon#about to read 6, iclass 6, count 0 2006.285.08:31:01.90#ibcon#read 6, iclass 6, count 0 2006.285.08:31:01.90#ibcon#end of sib2, iclass 6, count 0 2006.285.08:31:01.90#ibcon#*after write, iclass 6, count 0 2006.285.08:31:01.90#ibcon#*before return 0, iclass 6, count 0 2006.285.08:31:01.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:31:01.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:31:01.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:31:01.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:31:01.90$vck44/va=1,7 2006.285.08:31:01.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.08:31:01.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.08:31:01.90#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:01.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:31:01.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:31:01.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:31:01.90#ibcon#enter wrdev, iclass 10, count 2 2006.285.08:31:01.90#ibcon#first serial, iclass 10, count 2 2006.285.08:31:01.90#ibcon#enter sib2, iclass 10, count 2 2006.285.08:31:01.90#ibcon#flushed, iclass 10, count 2 2006.285.08:31:01.90#ibcon#about to write, iclass 10, count 2 2006.285.08:31:01.90#ibcon#wrote, iclass 10, count 2 2006.285.08:31:01.90#ibcon#about to read 3, iclass 10, count 2 2006.285.08:31:01.92#ibcon#read 3, iclass 10, count 2 2006.285.08:31:01.92#ibcon#about to read 4, iclass 10, count 2 2006.285.08:31:01.92#ibcon#read 4, iclass 10, count 2 2006.285.08:31:01.92#ibcon#about to read 5, iclass 10, count 2 2006.285.08:31:01.92#ibcon#read 5, iclass 10, count 2 2006.285.08:31:01.92#ibcon#about to read 6, iclass 10, count 2 2006.285.08:31:01.92#ibcon#read 6, iclass 10, count 2 2006.285.08:31:01.92#ibcon#end of sib2, iclass 10, count 2 2006.285.08:31:01.92#ibcon#*mode == 0, iclass 10, count 2 2006.285.08:31:01.92#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.08:31:01.92#ibcon#[25=AT01-07\r\n] 2006.285.08:31:01.92#ibcon#*before write, iclass 10, count 2 2006.285.08:31:01.92#ibcon#enter sib2, iclass 10, count 2 2006.285.08:31:01.92#ibcon#flushed, iclass 10, count 2 2006.285.08:31:01.92#ibcon#about to write, iclass 10, count 2 2006.285.08:31:01.92#ibcon#wrote, iclass 10, count 2 2006.285.08:31:01.92#ibcon#about to read 3, iclass 10, count 2 2006.285.08:31:01.95#ibcon#read 3, iclass 10, count 2 2006.285.08:31:01.95#ibcon#about to read 4, iclass 10, count 2 2006.285.08:31:01.95#ibcon#read 4, iclass 10, count 2 2006.285.08:31:01.95#ibcon#about to read 5, iclass 10, count 2 2006.285.08:31:01.95#ibcon#read 5, iclass 10, count 2 2006.285.08:31:01.95#ibcon#about to read 6, iclass 10, count 2 2006.285.08:31:01.95#ibcon#read 6, iclass 10, count 2 2006.285.08:31:01.95#ibcon#end of sib2, iclass 10, count 2 2006.285.08:31:01.95#ibcon#*after write, iclass 10, count 2 2006.285.08:31:01.95#ibcon#*before return 0, iclass 10, count 2 2006.285.08:31:01.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:31:01.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:31:01.95#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.08:31:01.95#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:01.95#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:31:02.07#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:31:02.07#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:31:02.07#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:31:02.07#ibcon#first serial, iclass 10, count 0 2006.285.08:31:02.07#ibcon#enter sib2, iclass 10, count 0 2006.285.08:31:02.07#ibcon#flushed, iclass 10, count 0 2006.285.08:31:02.07#ibcon#about to write, iclass 10, count 0 2006.285.08:31:02.07#ibcon#wrote, iclass 10, count 0 2006.285.08:31:02.07#ibcon#about to read 3, iclass 10, count 0 2006.285.08:31:02.09#ibcon#read 3, iclass 10, count 0 2006.285.08:31:02.09#ibcon#about to read 4, iclass 10, count 0 2006.285.08:31:02.09#ibcon#read 4, iclass 10, count 0 2006.285.08:31:02.09#ibcon#about to read 5, iclass 10, count 0 2006.285.08:31:02.09#ibcon#read 5, iclass 10, count 0 2006.285.08:31:02.09#ibcon#about to read 6, iclass 10, count 0 2006.285.08:31:02.09#ibcon#read 6, iclass 10, count 0 2006.285.08:31:02.09#ibcon#end of sib2, iclass 10, count 0 2006.285.08:31:02.09#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:31:02.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:31:02.09#ibcon#[25=USB\r\n] 2006.285.08:31:02.09#ibcon#*before write, iclass 10, count 0 2006.285.08:31:02.09#ibcon#enter sib2, iclass 10, count 0 2006.285.08:31:02.09#ibcon#flushed, iclass 10, count 0 2006.285.08:31:02.09#ibcon#about to write, iclass 10, count 0 2006.285.08:31:02.09#ibcon#wrote, iclass 10, count 0 2006.285.08:31:02.09#ibcon#about to read 3, iclass 10, count 0 2006.285.08:31:02.12#ibcon#read 3, iclass 10, count 0 2006.285.08:31:02.12#ibcon#about to read 4, iclass 10, count 0 2006.285.08:31:02.12#ibcon#read 4, iclass 10, count 0 2006.285.08:31:02.12#ibcon#about to read 5, iclass 10, count 0 2006.285.08:31:02.12#ibcon#read 5, iclass 10, count 0 2006.285.08:31:02.12#ibcon#about to read 6, iclass 10, count 0 2006.285.08:31:02.12#ibcon#read 6, iclass 10, count 0 2006.285.08:31:02.12#ibcon#end of sib2, iclass 10, count 0 2006.285.08:31:02.12#ibcon#*after write, iclass 10, count 0 2006.285.08:31:02.12#ibcon#*before return 0, iclass 10, count 0 2006.285.08:31:02.12#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:31:02.12#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:31:02.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:31:02.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:31:02.12$vck44/valo=2,534.99 2006.285.08:31:02.12#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.08:31:02.12#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.08:31:02.12#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:02.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:31:02.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:31:02.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:31:02.12#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:31:02.12#ibcon#first serial, iclass 12, count 0 2006.285.08:31:02.12#ibcon#enter sib2, iclass 12, count 0 2006.285.08:31:02.12#ibcon#flushed, iclass 12, count 0 2006.285.08:31:02.12#ibcon#about to write, iclass 12, count 0 2006.285.08:31:02.12#ibcon#wrote, iclass 12, count 0 2006.285.08:31:02.12#ibcon#about to read 3, iclass 12, count 0 2006.285.08:31:02.14#ibcon#read 3, iclass 12, count 0 2006.285.08:31:02.14#ibcon#about to read 4, iclass 12, count 0 2006.285.08:31:02.14#ibcon#read 4, iclass 12, count 0 2006.285.08:31:02.14#ibcon#about to read 5, iclass 12, count 0 2006.285.08:31:02.14#ibcon#read 5, iclass 12, count 0 2006.285.08:31:02.14#ibcon#about to read 6, iclass 12, count 0 2006.285.08:31:02.14#ibcon#read 6, iclass 12, count 0 2006.285.08:31:02.14#ibcon#end of sib2, iclass 12, count 0 2006.285.08:31:02.14#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:31:02.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:31:02.14#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:31:02.14#ibcon#*before write, iclass 12, count 0 2006.285.08:31:02.14#ibcon#enter sib2, iclass 12, count 0 2006.285.08:31:02.14#ibcon#flushed, iclass 12, count 0 2006.285.08:31:02.14#ibcon#about to write, iclass 12, count 0 2006.285.08:31:02.14#ibcon#wrote, iclass 12, count 0 2006.285.08:31:02.14#ibcon#about to read 3, iclass 12, count 0 2006.285.08:31:02.18#ibcon#read 3, iclass 12, count 0 2006.285.08:31:02.18#ibcon#about to read 4, iclass 12, count 0 2006.285.08:31:02.18#ibcon#read 4, iclass 12, count 0 2006.285.08:31:02.18#ibcon#about to read 5, iclass 12, count 0 2006.285.08:31:02.18#ibcon#read 5, iclass 12, count 0 2006.285.08:31:02.18#ibcon#about to read 6, iclass 12, count 0 2006.285.08:31:02.18#ibcon#read 6, iclass 12, count 0 2006.285.08:31:02.18#ibcon#end of sib2, iclass 12, count 0 2006.285.08:31:02.18#ibcon#*after write, iclass 12, count 0 2006.285.08:31:02.18#ibcon#*before return 0, iclass 12, count 0 2006.285.08:31:02.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:31:02.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:31:02.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:31:02.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:31:02.18$vck44/va=2,6 2006.285.08:31:02.18#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.08:31:02.18#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.08:31:02.18#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:02.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:31:02.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:31:02.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:31:02.24#ibcon#enter wrdev, iclass 14, count 2 2006.285.08:31:02.24#ibcon#first serial, iclass 14, count 2 2006.285.08:31:02.24#ibcon#enter sib2, iclass 14, count 2 2006.285.08:31:02.24#ibcon#flushed, iclass 14, count 2 2006.285.08:31:02.24#ibcon#about to write, iclass 14, count 2 2006.285.08:31:02.24#ibcon#wrote, iclass 14, count 2 2006.285.08:31:02.24#ibcon#about to read 3, iclass 14, count 2 2006.285.08:31:02.26#ibcon#read 3, iclass 14, count 2 2006.285.08:31:02.26#ibcon#about to read 4, iclass 14, count 2 2006.285.08:31:02.26#ibcon#read 4, iclass 14, count 2 2006.285.08:31:02.26#ibcon#about to read 5, iclass 14, count 2 2006.285.08:31:02.26#ibcon#read 5, iclass 14, count 2 2006.285.08:31:02.26#ibcon#about to read 6, iclass 14, count 2 2006.285.08:31:02.26#ibcon#read 6, iclass 14, count 2 2006.285.08:31:02.26#ibcon#end of sib2, iclass 14, count 2 2006.285.08:31:02.26#ibcon#*mode == 0, iclass 14, count 2 2006.285.08:31:02.26#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.08:31:02.26#ibcon#[25=AT02-06\r\n] 2006.285.08:31:02.26#ibcon#*before write, iclass 14, count 2 2006.285.08:31:02.26#ibcon#enter sib2, iclass 14, count 2 2006.285.08:31:02.26#ibcon#flushed, iclass 14, count 2 2006.285.08:31:02.26#ibcon#about to write, iclass 14, count 2 2006.285.08:31:02.26#ibcon#wrote, iclass 14, count 2 2006.285.08:31:02.26#ibcon#about to read 3, iclass 14, count 2 2006.285.08:31:02.29#ibcon#read 3, iclass 14, count 2 2006.285.08:31:02.29#ibcon#about to read 4, iclass 14, count 2 2006.285.08:31:02.29#ibcon#read 4, iclass 14, count 2 2006.285.08:31:02.29#ibcon#about to read 5, iclass 14, count 2 2006.285.08:31:02.29#ibcon#read 5, iclass 14, count 2 2006.285.08:31:02.29#ibcon#about to read 6, iclass 14, count 2 2006.285.08:31:02.29#ibcon#read 6, iclass 14, count 2 2006.285.08:31:02.29#ibcon#end of sib2, iclass 14, count 2 2006.285.08:31:02.29#ibcon#*after write, iclass 14, count 2 2006.285.08:31:02.29#ibcon#*before return 0, iclass 14, count 2 2006.285.08:31:02.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:31:02.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:31:02.29#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.08:31:02.29#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:02.29#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:31:02.41#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:31:02.41#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:31:02.41#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:31:02.41#ibcon#first serial, iclass 14, count 0 2006.285.08:31:02.41#ibcon#enter sib2, iclass 14, count 0 2006.285.08:31:02.41#ibcon#flushed, iclass 14, count 0 2006.285.08:31:02.41#ibcon#about to write, iclass 14, count 0 2006.285.08:31:02.41#ibcon#wrote, iclass 14, count 0 2006.285.08:31:02.41#ibcon#about to read 3, iclass 14, count 0 2006.285.08:31:02.43#ibcon#read 3, iclass 14, count 0 2006.285.08:31:02.43#ibcon#about to read 4, iclass 14, count 0 2006.285.08:31:02.43#ibcon#read 4, iclass 14, count 0 2006.285.08:31:02.43#ibcon#about to read 5, iclass 14, count 0 2006.285.08:31:02.43#ibcon#read 5, iclass 14, count 0 2006.285.08:31:02.43#ibcon#about to read 6, iclass 14, count 0 2006.285.08:31:02.43#ibcon#read 6, iclass 14, count 0 2006.285.08:31:02.43#ibcon#end of sib2, iclass 14, count 0 2006.285.08:31:02.43#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:31:02.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:31:02.43#ibcon#[25=USB\r\n] 2006.285.08:31:02.43#ibcon#*before write, iclass 14, count 0 2006.285.08:31:02.43#ibcon#enter sib2, iclass 14, count 0 2006.285.08:31:02.43#ibcon#flushed, iclass 14, count 0 2006.285.08:31:02.43#ibcon#about to write, iclass 14, count 0 2006.285.08:31:02.43#ibcon#wrote, iclass 14, count 0 2006.285.08:31:02.43#ibcon#about to read 3, iclass 14, count 0 2006.285.08:31:02.46#ibcon#read 3, iclass 14, count 0 2006.285.08:31:02.46#ibcon#about to read 4, iclass 14, count 0 2006.285.08:31:02.46#ibcon#read 4, iclass 14, count 0 2006.285.08:31:02.46#ibcon#about to read 5, iclass 14, count 0 2006.285.08:31:02.46#ibcon#read 5, iclass 14, count 0 2006.285.08:31:02.46#ibcon#about to read 6, iclass 14, count 0 2006.285.08:31:02.46#ibcon#read 6, iclass 14, count 0 2006.285.08:31:02.46#ibcon#end of sib2, iclass 14, count 0 2006.285.08:31:02.46#ibcon#*after write, iclass 14, count 0 2006.285.08:31:02.46#ibcon#*before return 0, iclass 14, count 0 2006.285.08:31:02.46#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:31:02.46#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:31:02.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:31:02.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:31:02.46$vck44/valo=3,564.99 2006.285.08:31:02.46#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.08:31:02.46#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.08:31:02.46#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:02.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:31:02.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:31:02.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:31:02.46#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:31:02.46#ibcon#first serial, iclass 16, count 0 2006.285.08:31:02.46#ibcon#enter sib2, iclass 16, count 0 2006.285.08:31:02.46#ibcon#flushed, iclass 16, count 0 2006.285.08:31:02.46#ibcon#about to write, iclass 16, count 0 2006.285.08:31:02.46#ibcon#wrote, iclass 16, count 0 2006.285.08:31:02.46#ibcon#about to read 3, iclass 16, count 0 2006.285.08:31:02.48#ibcon#read 3, iclass 16, count 0 2006.285.08:31:02.48#ibcon#about to read 4, iclass 16, count 0 2006.285.08:31:02.48#ibcon#read 4, iclass 16, count 0 2006.285.08:31:02.48#ibcon#about to read 5, iclass 16, count 0 2006.285.08:31:02.48#ibcon#read 5, iclass 16, count 0 2006.285.08:31:02.48#ibcon#about to read 6, iclass 16, count 0 2006.285.08:31:02.48#ibcon#read 6, iclass 16, count 0 2006.285.08:31:02.48#ibcon#end of sib2, iclass 16, count 0 2006.285.08:31:02.48#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:31:02.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:31:02.48#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:31:02.48#ibcon#*before write, iclass 16, count 0 2006.285.08:31:02.48#ibcon#enter sib2, iclass 16, count 0 2006.285.08:31:02.48#ibcon#flushed, iclass 16, count 0 2006.285.08:31:02.48#ibcon#about to write, iclass 16, count 0 2006.285.08:31:02.48#ibcon#wrote, iclass 16, count 0 2006.285.08:31:02.48#ibcon#about to read 3, iclass 16, count 0 2006.285.08:31:02.52#ibcon#read 3, iclass 16, count 0 2006.285.08:31:02.52#ibcon#about to read 4, iclass 16, count 0 2006.285.08:31:02.52#ibcon#read 4, iclass 16, count 0 2006.285.08:31:02.52#ibcon#about to read 5, iclass 16, count 0 2006.285.08:31:02.52#ibcon#read 5, iclass 16, count 0 2006.285.08:31:02.52#ibcon#about to read 6, iclass 16, count 0 2006.285.08:31:02.52#ibcon#read 6, iclass 16, count 0 2006.285.08:31:02.52#ibcon#end of sib2, iclass 16, count 0 2006.285.08:31:02.52#ibcon#*after write, iclass 16, count 0 2006.285.08:31:02.52#ibcon#*before return 0, iclass 16, count 0 2006.285.08:31:02.52#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:31:02.52#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:31:02.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:31:02.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:31:02.52$vck44/va=3,7 2006.285.08:31:02.52#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.08:31:02.52#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.08:31:02.52#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:02.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:31:02.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:31:02.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:31:02.58#ibcon#enter wrdev, iclass 18, count 2 2006.285.08:31:02.58#ibcon#first serial, iclass 18, count 2 2006.285.08:31:02.58#ibcon#enter sib2, iclass 18, count 2 2006.285.08:31:02.58#ibcon#flushed, iclass 18, count 2 2006.285.08:31:02.58#ibcon#about to write, iclass 18, count 2 2006.285.08:31:02.58#ibcon#wrote, iclass 18, count 2 2006.285.08:31:02.58#ibcon#about to read 3, iclass 18, count 2 2006.285.08:31:02.60#ibcon#read 3, iclass 18, count 2 2006.285.08:31:02.60#ibcon#about to read 4, iclass 18, count 2 2006.285.08:31:02.60#ibcon#read 4, iclass 18, count 2 2006.285.08:31:02.60#ibcon#about to read 5, iclass 18, count 2 2006.285.08:31:02.60#ibcon#read 5, iclass 18, count 2 2006.285.08:31:02.60#ibcon#about to read 6, iclass 18, count 2 2006.285.08:31:02.60#ibcon#read 6, iclass 18, count 2 2006.285.08:31:02.60#ibcon#end of sib2, iclass 18, count 2 2006.285.08:31:02.60#ibcon#*mode == 0, iclass 18, count 2 2006.285.08:31:02.60#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.08:31:02.60#ibcon#[25=AT03-07\r\n] 2006.285.08:31:02.60#ibcon#*before write, iclass 18, count 2 2006.285.08:31:02.60#ibcon#enter sib2, iclass 18, count 2 2006.285.08:31:02.60#ibcon#flushed, iclass 18, count 2 2006.285.08:31:02.60#ibcon#about to write, iclass 18, count 2 2006.285.08:31:02.60#ibcon#wrote, iclass 18, count 2 2006.285.08:31:02.60#ibcon#about to read 3, iclass 18, count 2 2006.285.08:31:02.63#ibcon#read 3, iclass 18, count 2 2006.285.08:31:02.63#ibcon#about to read 4, iclass 18, count 2 2006.285.08:31:02.63#ibcon#read 4, iclass 18, count 2 2006.285.08:31:02.63#ibcon#about to read 5, iclass 18, count 2 2006.285.08:31:02.63#ibcon#read 5, iclass 18, count 2 2006.285.08:31:02.63#ibcon#about to read 6, iclass 18, count 2 2006.285.08:31:02.63#ibcon#read 6, iclass 18, count 2 2006.285.08:31:02.63#ibcon#end of sib2, iclass 18, count 2 2006.285.08:31:02.63#ibcon#*after write, iclass 18, count 2 2006.285.08:31:02.63#ibcon#*before return 0, iclass 18, count 2 2006.285.08:31:02.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:31:02.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:31:02.63#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.08:31:02.63#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:02.63#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:31:02.75#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:31:02.75#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:31:02.75#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:31:02.75#ibcon#first serial, iclass 18, count 0 2006.285.08:31:02.75#ibcon#enter sib2, iclass 18, count 0 2006.285.08:31:02.75#ibcon#flushed, iclass 18, count 0 2006.285.08:31:02.75#ibcon#about to write, iclass 18, count 0 2006.285.08:31:02.75#ibcon#wrote, iclass 18, count 0 2006.285.08:31:02.75#ibcon#about to read 3, iclass 18, count 0 2006.285.08:31:02.77#ibcon#read 3, iclass 18, count 0 2006.285.08:31:02.77#ibcon#about to read 4, iclass 18, count 0 2006.285.08:31:02.77#ibcon#read 4, iclass 18, count 0 2006.285.08:31:02.77#ibcon#about to read 5, iclass 18, count 0 2006.285.08:31:02.77#ibcon#read 5, iclass 18, count 0 2006.285.08:31:02.77#ibcon#about to read 6, iclass 18, count 0 2006.285.08:31:02.77#ibcon#read 6, iclass 18, count 0 2006.285.08:31:02.77#ibcon#end of sib2, iclass 18, count 0 2006.285.08:31:02.77#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:31:02.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:31:02.77#ibcon#[25=USB\r\n] 2006.285.08:31:02.77#ibcon#*before write, iclass 18, count 0 2006.285.08:31:02.77#ibcon#enter sib2, iclass 18, count 0 2006.285.08:31:02.77#ibcon#flushed, iclass 18, count 0 2006.285.08:31:02.77#ibcon#about to write, iclass 18, count 0 2006.285.08:31:02.77#ibcon#wrote, iclass 18, count 0 2006.285.08:31:02.77#ibcon#about to read 3, iclass 18, count 0 2006.285.08:31:02.80#ibcon#read 3, iclass 18, count 0 2006.285.08:31:02.80#ibcon#about to read 4, iclass 18, count 0 2006.285.08:31:02.80#ibcon#read 4, iclass 18, count 0 2006.285.08:31:02.80#ibcon#about to read 5, iclass 18, count 0 2006.285.08:31:02.80#ibcon#read 5, iclass 18, count 0 2006.285.08:31:02.80#ibcon#about to read 6, iclass 18, count 0 2006.285.08:31:02.80#ibcon#read 6, iclass 18, count 0 2006.285.08:31:02.80#ibcon#end of sib2, iclass 18, count 0 2006.285.08:31:02.80#ibcon#*after write, iclass 18, count 0 2006.285.08:31:02.80#ibcon#*before return 0, iclass 18, count 0 2006.285.08:31:02.80#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:31:02.80#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:31:02.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:31:02.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:31:02.80$vck44/valo=4,624.99 2006.285.08:31:02.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.08:31:02.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.08:31:02.80#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:02.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:31:02.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:31:02.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:31:02.80#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:31:02.80#ibcon#first serial, iclass 20, count 0 2006.285.08:31:02.80#ibcon#enter sib2, iclass 20, count 0 2006.285.08:31:02.80#ibcon#flushed, iclass 20, count 0 2006.285.08:31:02.80#ibcon#about to write, iclass 20, count 0 2006.285.08:31:02.80#ibcon#wrote, iclass 20, count 0 2006.285.08:31:02.80#ibcon#about to read 3, iclass 20, count 0 2006.285.08:31:02.82#ibcon#read 3, iclass 20, count 0 2006.285.08:31:02.82#ibcon#about to read 4, iclass 20, count 0 2006.285.08:31:02.82#ibcon#read 4, iclass 20, count 0 2006.285.08:31:02.82#ibcon#about to read 5, iclass 20, count 0 2006.285.08:31:02.82#ibcon#read 5, iclass 20, count 0 2006.285.08:31:02.82#ibcon#about to read 6, iclass 20, count 0 2006.285.08:31:02.82#ibcon#read 6, iclass 20, count 0 2006.285.08:31:02.82#ibcon#end of sib2, iclass 20, count 0 2006.285.08:31:02.82#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:31:02.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:31:02.82#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:31:02.82#ibcon#*before write, iclass 20, count 0 2006.285.08:31:02.82#ibcon#enter sib2, iclass 20, count 0 2006.285.08:31:02.82#ibcon#flushed, iclass 20, count 0 2006.285.08:31:02.82#ibcon#about to write, iclass 20, count 0 2006.285.08:31:02.82#ibcon#wrote, iclass 20, count 0 2006.285.08:31:02.82#ibcon#about to read 3, iclass 20, count 0 2006.285.08:31:02.86#ibcon#read 3, iclass 20, count 0 2006.285.08:31:02.86#ibcon#about to read 4, iclass 20, count 0 2006.285.08:31:02.86#ibcon#read 4, iclass 20, count 0 2006.285.08:31:02.86#ibcon#about to read 5, iclass 20, count 0 2006.285.08:31:02.86#ibcon#read 5, iclass 20, count 0 2006.285.08:31:02.86#ibcon#about to read 6, iclass 20, count 0 2006.285.08:31:02.86#ibcon#read 6, iclass 20, count 0 2006.285.08:31:02.86#ibcon#end of sib2, iclass 20, count 0 2006.285.08:31:02.86#ibcon#*after write, iclass 20, count 0 2006.285.08:31:02.86#ibcon#*before return 0, iclass 20, count 0 2006.285.08:31:02.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:31:02.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:31:02.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:31:02.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:31:02.86$vck44/va=4,6 2006.285.08:31:02.86#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.08:31:02.86#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.08:31:02.86#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:02.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:31:02.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:31:02.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:31:02.92#ibcon#enter wrdev, iclass 22, count 2 2006.285.08:31:02.92#ibcon#first serial, iclass 22, count 2 2006.285.08:31:02.92#ibcon#enter sib2, iclass 22, count 2 2006.285.08:31:02.92#ibcon#flushed, iclass 22, count 2 2006.285.08:31:02.92#ibcon#about to write, iclass 22, count 2 2006.285.08:31:02.92#ibcon#wrote, iclass 22, count 2 2006.285.08:31:02.92#ibcon#about to read 3, iclass 22, count 2 2006.285.08:31:02.94#ibcon#read 3, iclass 22, count 2 2006.285.08:31:02.94#ibcon#about to read 4, iclass 22, count 2 2006.285.08:31:02.94#ibcon#read 4, iclass 22, count 2 2006.285.08:31:02.94#ibcon#about to read 5, iclass 22, count 2 2006.285.08:31:02.94#ibcon#read 5, iclass 22, count 2 2006.285.08:31:02.94#ibcon#about to read 6, iclass 22, count 2 2006.285.08:31:02.94#ibcon#read 6, iclass 22, count 2 2006.285.08:31:02.94#ibcon#end of sib2, iclass 22, count 2 2006.285.08:31:02.94#ibcon#*mode == 0, iclass 22, count 2 2006.285.08:31:02.94#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.08:31:02.94#ibcon#[25=AT04-06\r\n] 2006.285.08:31:02.94#ibcon#*before write, iclass 22, count 2 2006.285.08:31:02.94#ibcon#enter sib2, iclass 22, count 2 2006.285.08:31:02.94#ibcon#flushed, iclass 22, count 2 2006.285.08:31:02.94#ibcon#about to write, iclass 22, count 2 2006.285.08:31:02.94#ibcon#wrote, iclass 22, count 2 2006.285.08:31:02.94#ibcon#about to read 3, iclass 22, count 2 2006.285.08:31:02.97#ibcon#read 3, iclass 22, count 2 2006.285.08:31:02.97#ibcon#about to read 4, iclass 22, count 2 2006.285.08:31:02.97#ibcon#read 4, iclass 22, count 2 2006.285.08:31:02.97#ibcon#about to read 5, iclass 22, count 2 2006.285.08:31:02.97#ibcon#read 5, iclass 22, count 2 2006.285.08:31:02.97#ibcon#about to read 6, iclass 22, count 2 2006.285.08:31:02.97#ibcon#read 6, iclass 22, count 2 2006.285.08:31:02.97#ibcon#end of sib2, iclass 22, count 2 2006.285.08:31:02.97#ibcon#*after write, iclass 22, count 2 2006.285.08:31:02.97#ibcon#*before return 0, iclass 22, count 2 2006.285.08:31:02.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:31:02.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:31:02.97#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.08:31:02.97#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:02.97#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:31:03.09#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:31:03.09#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:31:03.09#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:31:03.09#ibcon#first serial, iclass 22, count 0 2006.285.08:31:03.09#ibcon#enter sib2, iclass 22, count 0 2006.285.08:31:03.09#ibcon#flushed, iclass 22, count 0 2006.285.08:31:03.09#ibcon#about to write, iclass 22, count 0 2006.285.08:31:03.09#ibcon#wrote, iclass 22, count 0 2006.285.08:31:03.09#ibcon#about to read 3, iclass 22, count 0 2006.285.08:31:03.11#ibcon#read 3, iclass 22, count 0 2006.285.08:31:03.11#ibcon#about to read 4, iclass 22, count 0 2006.285.08:31:03.11#ibcon#read 4, iclass 22, count 0 2006.285.08:31:03.11#ibcon#about to read 5, iclass 22, count 0 2006.285.08:31:03.11#ibcon#read 5, iclass 22, count 0 2006.285.08:31:03.11#ibcon#about to read 6, iclass 22, count 0 2006.285.08:31:03.11#ibcon#read 6, iclass 22, count 0 2006.285.08:31:03.11#ibcon#end of sib2, iclass 22, count 0 2006.285.08:31:03.11#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:31:03.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:31:03.11#ibcon#[25=USB\r\n] 2006.285.08:31:03.11#ibcon#*before write, iclass 22, count 0 2006.285.08:31:03.11#ibcon#enter sib2, iclass 22, count 0 2006.285.08:31:03.11#ibcon#flushed, iclass 22, count 0 2006.285.08:31:03.11#ibcon#about to write, iclass 22, count 0 2006.285.08:31:03.11#ibcon#wrote, iclass 22, count 0 2006.285.08:31:03.11#ibcon#about to read 3, iclass 22, count 0 2006.285.08:31:03.14#ibcon#read 3, iclass 22, count 0 2006.285.08:31:03.14#ibcon#about to read 4, iclass 22, count 0 2006.285.08:31:03.14#ibcon#read 4, iclass 22, count 0 2006.285.08:31:03.14#ibcon#about to read 5, iclass 22, count 0 2006.285.08:31:03.14#ibcon#read 5, iclass 22, count 0 2006.285.08:31:03.14#ibcon#about to read 6, iclass 22, count 0 2006.285.08:31:03.14#ibcon#read 6, iclass 22, count 0 2006.285.08:31:03.14#ibcon#end of sib2, iclass 22, count 0 2006.285.08:31:03.14#ibcon#*after write, iclass 22, count 0 2006.285.08:31:03.14#ibcon#*before return 0, iclass 22, count 0 2006.285.08:31:03.14#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:31:03.14#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:31:03.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:31:03.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:31:03.14$vck44/valo=5,734.99 2006.285.08:31:03.14#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.08:31:03.14#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.08:31:03.14#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:03.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:31:03.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:31:03.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:31:03.14#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:31:03.14#ibcon#first serial, iclass 24, count 0 2006.285.08:31:03.14#ibcon#enter sib2, iclass 24, count 0 2006.285.08:31:03.14#ibcon#flushed, iclass 24, count 0 2006.285.08:31:03.14#ibcon#about to write, iclass 24, count 0 2006.285.08:31:03.14#ibcon#wrote, iclass 24, count 0 2006.285.08:31:03.14#ibcon#about to read 3, iclass 24, count 0 2006.285.08:31:03.16#ibcon#read 3, iclass 24, count 0 2006.285.08:31:03.16#ibcon#about to read 4, iclass 24, count 0 2006.285.08:31:03.16#ibcon#read 4, iclass 24, count 0 2006.285.08:31:03.16#ibcon#about to read 5, iclass 24, count 0 2006.285.08:31:03.16#ibcon#read 5, iclass 24, count 0 2006.285.08:31:03.16#ibcon#about to read 6, iclass 24, count 0 2006.285.08:31:03.16#ibcon#read 6, iclass 24, count 0 2006.285.08:31:03.16#ibcon#end of sib2, iclass 24, count 0 2006.285.08:31:03.16#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:31:03.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:31:03.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:31:03.16#ibcon#*before write, iclass 24, count 0 2006.285.08:31:03.16#ibcon#enter sib2, iclass 24, count 0 2006.285.08:31:03.16#ibcon#flushed, iclass 24, count 0 2006.285.08:31:03.16#ibcon#about to write, iclass 24, count 0 2006.285.08:31:03.16#ibcon#wrote, iclass 24, count 0 2006.285.08:31:03.16#ibcon#about to read 3, iclass 24, count 0 2006.285.08:31:03.20#ibcon#read 3, iclass 24, count 0 2006.285.08:31:03.20#ibcon#about to read 4, iclass 24, count 0 2006.285.08:31:03.20#ibcon#read 4, iclass 24, count 0 2006.285.08:31:03.20#ibcon#about to read 5, iclass 24, count 0 2006.285.08:31:03.20#ibcon#read 5, iclass 24, count 0 2006.285.08:31:03.20#ibcon#about to read 6, iclass 24, count 0 2006.285.08:31:03.20#ibcon#read 6, iclass 24, count 0 2006.285.08:31:03.20#ibcon#end of sib2, iclass 24, count 0 2006.285.08:31:03.20#ibcon#*after write, iclass 24, count 0 2006.285.08:31:03.20#ibcon#*before return 0, iclass 24, count 0 2006.285.08:31:03.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:31:03.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:31:03.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:31:03.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:31:03.20$vck44/va=5,3 2006.285.08:31:03.20#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.08:31:03.20#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.08:31:03.20#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:03.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:31:03.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:31:03.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:31:03.26#ibcon#enter wrdev, iclass 26, count 2 2006.285.08:31:03.26#ibcon#first serial, iclass 26, count 2 2006.285.08:31:03.26#ibcon#enter sib2, iclass 26, count 2 2006.285.08:31:03.26#ibcon#flushed, iclass 26, count 2 2006.285.08:31:03.26#ibcon#about to write, iclass 26, count 2 2006.285.08:31:03.26#ibcon#wrote, iclass 26, count 2 2006.285.08:31:03.26#ibcon#about to read 3, iclass 26, count 2 2006.285.08:31:03.28#ibcon#read 3, iclass 26, count 2 2006.285.08:31:03.28#ibcon#about to read 4, iclass 26, count 2 2006.285.08:31:03.28#ibcon#read 4, iclass 26, count 2 2006.285.08:31:03.28#ibcon#about to read 5, iclass 26, count 2 2006.285.08:31:03.28#ibcon#read 5, iclass 26, count 2 2006.285.08:31:03.28#ibcon#about to read 6, iclass 26, count 2 2006.285.08:31:03.28#ibcon#read 6, iclass 26, count 2 2006.285.08:31:03.28#ibcon#end of sib2, iclass 26, count 2 2006.285.08:31:03.28#ibcon#*mode == 0, iclass 26, count 2 2006.285.08:31:03.28#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.08:31:03.28#ibcon#[25=AT05-03\r\n] 2006.285.08:31:03.28#ibcon#*before write, iclass 26, count 2 2006.285.08:31:03.28#ibcon#enter sib2, iclass 26, count 2 2006.285.08:31:03.28#ibcon#flushed, iclass 26, count 2 2006.285.08:31:03.28#ibcon#about to write, iclass 26, count 2 2006.285.08:31:03.28#ibcon#wrote, iclass 26, count 2 2006.285.08:31:03.28#ibcon#about to read 3, iclass 26, count 2 2006.285.08:31:03.31#ibcon#read 3, iclass 26, count 2 2006.285.08:31:03.31#ibcon#about to read 4, iclass 26, count 2 2006.285.08:31:03.31#ibcon#read 4, iclass 26, count 2 2006.285.08:31:03.31#ibcon#about to read 5, iclass 26, count 2 2006.285.08:31:03.31#ibcon#read 5, iclass 26, count 2 2006.285.08:31:03.31#ibcon#about to read 6, iclass 26, count 2 2006.285.08:31:03.31#ibcon#read 6, iclass 26, count 2 2006.285.08:31:03.31#ibcon#end of sib2, iclass 26, count 2 2006.285.08:31:03.31#ibcon#*after write, iclass 26, count 2 2006.285.08:31:03.31#ibcon#*before return 0, iclass 26, count 2 2006.285.08:31:03.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:31:03.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:31:03.31#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.08:31:03.31#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:03.31#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:31:03.43#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:31:03.43#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:31:03.43#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:31:03.43#ibcon#first serial, iclass 26, count 0 2006.285.08:31:03.43#ibcon#enter sib2, iclass 26, count 0 2006.285.08:31:03.43#ibcon#flushed, iclass 26, count 0 2006.285.08:31:03.43#ibcon#about to write, iclass 26, count 0 2006.285.08:31:03.43#ibcon#wrote, iclass 26, count 0 2006.285.08:31:03.43#ibcon#about to read 3, iclass 26, count 0 2006.285.08:31:03.45#ibcon#read 3, iclass 26, count 0 2006.285.08:31:03.45#ibcon#about to read 4, iclass 26, count 0 2006.285.08:31:03.45#ibcon#read 4, iclass 26, count 0 2006.285.08:31:03.45#ibcon#about to read 5, iclass 26, count 0 2006.285.08:31:03.45#ibcon#read 5, iclass 26, count 0 2006.285.08:31:03.45#ibcon#about to read 6, iclass 26, count 0 2006.285.08:31:03.45#ibcon#read 6, iclass 26, count 0 2006.285.08:31:03.45#ibcon#end of sib2, iclass 26, count 0 2006.285.08:31:03.45#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:31:03.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:31:03.45#ibcon#[25=USB\r\n] 2006.285.08:31:03.45#ibcon#*before write, iclass 26, count 0 2006.285.08:31:03.45#ibcon#enter sib2, iclass 26, count 0 2006.285.08:31:03.45#ibcon#flushed, iclass 26, count 0 2006.285.08:31:03.45#ibcon#about to write, iclass 26, count 0 2006.285.08:31:03.45#ibcon#wrote, iclass 26, count 0 2006.285.08:31:03.45#ibcon#about to read 3, iclass 26, count 0 2006.285.08:31:03.48#ibcon#read 3, iclass 26, count 0 2006.285.08:31:03.48#ibcon#about to read 4, iclass 26, count 0 2006.285.08:31:03.48#ibcon#read 4, iclass 26, count 0 2006.285.08:31:03.48#ibcon#about to read 5, iclass 26, count 0 2006.285.08:31:03.48#ibcon#read 5, iclass 26, count 0 2006.285.08:31:03.48#ibcon#about to read 6, iclass 26, count 0 2006.285.08:31:03.48#ibcon#read 6, iclass 26, count 0 2006.285.08:31:03.48#ibcon#end of sib2, iclass 26, count 0 2006.285.08:31:03.48#ibcon#*after write, iclass 26, count 0 2006.285.08:31:03.48#ibcon#*before return 0, iclass 26, count 0 2006.285.08:31:03.48#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:31:03.48#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:31:03.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:31:03.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:31:03.48$vck44/valo=6,814.99 2006.285.08:31:03.48#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.08:31:03.48#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.08:31:03.48#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:03.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:31:03.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:31:03.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:31:03.48#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:31:03.48#ibcon#first serial, iclass 28, count 0 2006.285.08:31:03.48#ibcon#enter sib2, iclass 28, count 0 2006.285.08:31:03.48#ibcon#flushed, iclass 28, count 0 2006.285.08:31:03.48#ibcon#about to write, iclass 28, count 0 2006.285.08:31:03.48#ibcon#wrote, iclass 28, count 0 2006.285.08:31:03.48#ibcon#about to read 3, iclass 28, count 0 2006.285.08:31:03.50#ibcon#read 3, iclass 28, count 0 2006.285.08:31:03.50#ibcon#about to read 4, iclass 28, count 0 2006.285.08:31:03.50#ibcon#read 4, iclass 28, count 0 2006.285.08:31:03.50#ibcon#about to read 5, iclass 28, count 0 2006.285.08:31:03.50#ibcon#read 5, iclass 28, count 0 2006.285.08:31:03.50#ibcon#about to read 6, iclass 28, count 0 2006.285.08:31:03.50#ibcon#read 6, iclass 28, count 0 2006.285.08:31:03.50#ibcon#end of sib2, iclass 28, count 0 2006.285.08:31:03.50#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:31:03.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:31:03.50#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:31:03.50#ibcon#*before write, iclass 28, count 0 2006.285.08:31:03.50#ibcon#enter sib2, iclass 28, count 0 2006.285.08:31:03.50#ibcon#flushed, iclass 28, count 0 2006.285.08:31:03.50#ibcon#about to write, iclass 28, count 0 2006.285.08:31:03.50#ibcon#wrote, iclass 28, count 0 2006.285.08:31:03.50#ibcon#about to read 3, iclass 28, count 0 2006.285.08:31:03.54#ibcon#read 3, iclass 28, count 0 2006.285.08:31:03.54#ibcon#about to read 4, iclass 28, count 0 2006.285.08:31:03.54#ibcon#read 4, iclass 28, count 0 2006.285.08:31:03.54#ibcon#about to read 5, iclass 28, count 0 2006.285.08:31:03.54#ibcon#read 5, iclass 28, count 0 2006.285.08:31:03.54#ibcon#about to read 6, iclass 28, count 0 2006.285.08:31:03.54#ibcon#read 6, iclass 28, count 0 2006.285.08:31:03.54#ibcon#end of sib2, iclass 28, count 0 2006.285.08:31:03.54#ibcon#*after write, iclass 28, count 0 2006.285.08:31:03.54#ibcon#*before return 0, iclass 28, count 0 2006.285.08:31:03.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:31:03.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:31:03.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:31:03.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:31:03.54$vck44/va=6,4 2006.285.08:31:03.54#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.08:31:03.54#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.08:31:03.54#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:03.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:31:03.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:31:03.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:31:03.60#ibcon#enter wrdev, iclass 30, count 2 2006.285.08:31:03.60#ibcon#first serial, iclass 30, count 2 2006.285.08:31:03.60#ibcon#enter sib2, iclass 30, count 2 2006.285.08:31:03.60#ibcon#flushed, iclass 30, count 2 2006.285.08:31:03.60#ibcon#about to write, iclass 30, count 2 2006.285.08:31:03.60#ibcon#wrote, iclass 30, count 2 2006.285.08:31:03.60#ibcon#about to read 3, iclass 30, count 2 2006.285.08:31:03.62#ibcon#read 3, iclass 30, count 2 2006.285.08:31:03.62#ibcon#about to read 4, iclass 30, count 2 2006.285.08:31:03.62#ibcon#read 4, iclass 30, count 2 2006.285.08:31:03.62#ibcon#about to read 5, iclass 30, count 2 2006.285.08:31:03.62#ibcon#read 5, iclass 30, count 2 2006.285.08:31:03.62#ibcon#about to read 6, iclass 30, count 2 2006.285.08:31:03.62#ibcon#read 6, iclass 30, count 2 2006.285.08:31:03.62#ibcon#end of sib2, iclass 30, count 2 2006.285.08:31:03.62#ibcon#*mode == 0, iclass 30, count 2 2006.285.08:31:03.62#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.08:31:03.62#ibcon#[25=AT06-04\r\n] 2006.285.08:31:03.62#ibcon#*before write, iclass 30, count 2 2006.285.08:31:03.62#ibcon#enter sib2, iclass 30, count 2 2006.285.08:31:03.62#ibcon#flushed, iclass 30, count 2 2006.285.08:31:03.62#ibcon#about to write, iclass 30, count 2 2006.285.08:31:03.62#ibcon#wrote, iclass 30, count 2 2006.285.08:31:03.62#ibcon#about to read 3, iclass 30, count 2 2006.285.08:31:03.65#ibcon#read 3, iclass 30, count 2 2006.285.08:31:03.65#ibcon#about to read 4, iclass 30, count 2 2006.285.08:31:03.65#ibcon#read 4, iclass 30, count 2 2006.285.08:31:03.65#ibcon#about to read 5, iclass 30, count 2 2006.285.08:31:03.65#ibcon#read 5, iclass 30, count 2 2006.285.08:31:03.65#ibcon#about to read 6, iclass 30, count 2 2006.285.08:31:03.65#ibcon#read 6, iclass 30, count 2 2006.285.08:31:03.65#ibcon#end of sib2, iclass 30, count 2 2006.285.08:31:03.65#ibcon#*after write, iclass 30, count 2 2006.285.08:31:03.65#ibcon#*before return 0, iclass 30, count 2 2006.285.08:31:03.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:31:03.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:31:03.65#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.08:31:03.65#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:03.65#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:31:03.77#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:31:03.77#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:31:03.77#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:31:03.77#ibcon#first serial, iclass 30, count 0 2006.285.08:31:03.77#ibcon#enter sib2, iclass 30, count 0 2006.285.08:31:03.77#ibcon#flushed, iclass 30, count 0 2006.285.08:31:03.77#ibcon#about to write, iclass 30, count 0 2006.285.08:31:03.77#ibcon#wrote, iclass 30, count 0 2006.285.08:31:03.77#ibcon#about to read 3, iclass 30, count 0 2006.285.08:31:03.79#ibcon#read 3, iclass 30, count 0 2006.285.08:31:03.79#ibcon#about to read 4, iclass 30, count 0 2006.285.08:31:03.79#ibcon#read 4, iclass 30, count 0 2006.285.08:31:03.79#ibcon#about to read 5, iclass 30, count 0 2006.285.08:31:03.79#ibcon#read 5, iclass 30, count 0 2006.285.08:31:03.79#ibcon#about to read 6, iclass 30, count 0 2006.285.08:31:03.79#ibcon#read 6, iclass 30, count 0 2006.285.08:31:03.79#ibcon#end of sib2, iclass 30, count 0 2006.285.08:31:03.79#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:31:03.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:31:03.79#ibcon#[25=USB\r\n] 2006.285.08:31:03.79#ibcon#*before write, iclass 30, count 0 2006.285.08:31:03.79#ibcon#enter sib2, iclass 30, count 0 2006.285.08:31:03.79#ibcon#flushed, iclass 30, count 0 2006.285.08:31:03.79#ibcon#about to write, iclass 30, count 0 2006.285.08:31:03.79#ibcon#wrote, iclass 30, count 0 2006.285.08:31:03.79#ibcon#about to read 3, iclass 30, count 0 2006.285.08:31:03.82#ibcon#read 3, iclass 30, count 0 2006.285.08:31:03.82#ibcon#about to read 4, iclass 30, count 0 2006.285.08:31:03.82#ibcon#read 4, iclass 30, count 0 2006.285.08:31:03.82#ibcon#about to read 5, iclass 30, count 0 2006.285.08:31:03.82#ibcon#read 5, iclass 30, count 0 2006.285.08:31:03.82#ibcon#about to read 6, iclass 30, count 0 2006.285.08:31:03.82#ibcon#read 6, iclass 30, count 0 2006.285.08:31:03.82#ibcon#end of sib2, iclass 30, count 0 2006.285.08:31:03.82#ibcon#*after write, iclass 30, count 0 2006.285.08:31:03.82#ibcon#*before return 0, iclass 30, count 0 2006.285.08:31:03.82#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:31:03.82#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:31:03.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:31:03.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:31:03.82$vck44/valo=7,864.99 2006.285.08:31:03.82#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.08:31:03.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.08:31:03.82#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:03.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:31:03.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:31:03.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:31:03.82#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:31:03.82#ibcon#first serial, iclass 32, count 0 2006.285.08:31:03.82#ibcon#enter sib2, iclass 32, count 0 2006.285.08:31:03.82#ibcon#flushed, iclass 32, count 0 2006.285.08:31:03.82#ibcon#about to write, iclass 32, count 0 2006.285.08:31:03.82#ibcon#wrote, iclass 32, count 0 2006.285.08:31:03.82#ibcon#about to read 3, iclass 32, count 0 2006.285.08:31:03.84#ibcon#read 3, iclass 32, count 0 2006.285.08:31:03.84#ibcon#about to read 4, iclass 32, count 0 2006.285.08:31:03.84#ibcon#read 4, iclass 32, count 0 2006.285.08:31:03.84#ibcon#about to read 5, iclass 32, count 0 2006.285.08:31:03.84#ibcon#read 5, iclass 32, count 0 2006.285.08:31:03.84#ibcon#about to read 6, iclass 32, count 0 2006.285.08:31:03.84#ibcon#read 6, iclass 32, count 0 2006.285.08:31:03.84#ibcon#end of sib2, iclass 32, count 0 2006.285.08:31:03.84#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:31:03.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:31:03.84#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:31:03.84#ibcon#*before write, iclass 32, count 0 2006.285.08:31:03.84#ibcon#enter sib2, iclass 32, count 0 2006.285.08:31:03.84#ibcon#flushed, iclass 32, count 0 2006.285.08:31:03.84#ibcon#about to write, iclass 32, count 0 2006.285.08:31:03.84#ibcon#wrote, iclass 32, count 0 2006.285.08:31:03.84#ibcon#about to read 3, iclass 32, count 0 2006.285.08:31:03.88#ibcon#read 3, iclass 32, count 0 2006.285.08:31:03.88#ibcon#about to read 4, iclass 32, count 0 2006.285.08:31:03.88#ibcon#read 4, iclass 32, count 0 2006.285.08:31:03.88#ibcon#about to read 5, iclass 32, count 0 2006.285.08:31:03.88#ibcon#read 5, iclass 32, count 0 2006.285.08:31:03.88#ibcon#about to read 6, iclass 32, count 0 2006.285.08:31:03.88#ibcon#read 6, iclass 32, count 0 2006.285.08:31:03.88#ibcon#end of sib2, iclass 32, count 0 2006.285.08:31:03.88#ibcon#*after write, iclass 32, count 0 2006.285.08:31:03.88#ibcon#*before return 0, iclass 32, count 0 2006.285.08:31:03.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:31:03.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:31:03.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:31:03.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:31:03.88$vck44/va=7,4 2006.285.08:31:03.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.08:31:03.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.08:31:03.88#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:03.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:31:03.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:31:03.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:31:03.94#ibcon#enter wrdev, iclass 34, count 2 2006.285.08:31:03.94#ibcon#first serial, iclass 34, count 2 2006.285.08:31:03.94#ibcon#enter sib2, iclass 34, count 2 2006.285.08:31:03.94#ibcon#flushed, iclass 34, count 2 2006.285.08:31:03.94#ibcon#about to write, iclass 34, count 2 2006.285.08:31:03.94#ibcon#wrote, iclass 34, count 2 2006.285.08:31:03.94#ibcon#about to read 3, iclass 34, count 2 2006.285.08:31:03.96#ibcon#read 3, iclass 34, count 2 2006.285.08:31:03.96#ibcon#about to read 4, iclass 34, count 2 2006.285.08:31:03.96#ibcon#read 4, iclass 34, count 2 2006.285.08:31:03.96#ibcon#about to read 5, iclass 34, count 2 2006.285.08:31:03.96#ibcon#read 5, iclass 34, count 2 2006.285.08:31:03.96#ibcon#about to read 6, iclass 34, count 2 2006.285.08:31:03.96#ibcon#read 6, iclass 34, count 2 2006.285.08:31:03.96#ibcon#end of sib2, iclass 34, count 2 2006.285.08:31:03.96#ibcon#*mode == 0, iclass 34, count 2 2006.285.08:31:03.96#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.08:31:03.96#ibcon#[25=AT07-04\r\n] 2006.285.08:31:03.96#ibcon#*before write, iclass 34, count 2 2006.285.08:31:03.96#ibcon#enter sib2, iclass 34, count 2 2006.285.08:31:03.96#ibcon#flushed, iclass 34, count 2 2006.285.08:31:03.96#ibcon#about to write, iclass 34, count 2 2006.285.08:31:03.96#ibcon#wrote, iclass 34, count 2 2006.285.08:31:03.96#ibcon#about to read 3, iclass 34, count 2 2006.285.08:31:03.99#ibcon#read 3, iclass 34, count 2 2006.285.08:31:03.99#ibcon#about to read 4, iclass 34, count 2 2006.285.08:31:03.99#ibcon#read 4, iclass 34, count 2 2006.285.08:31:03.99#ibcon#about to read 5, iclass 34, count 2 2006.285.08:31:03.99#ibcon#read 5, iclass 34, count 2 2006.285.08:31:03.99#ibcon#about to read 6, iclass 34, count 2 2006.285.08:31:03.99#ibcon#read 6, iclass 34, count 2 2006.285.08:31:03.99#ibcon#end of sib2, iclass 34, count 2 2006.285.08:31:03.99#ibcon#*after write, iclass 34, count 2 2006.285.08:31:03.99#ibcon#*before return 0, iclass 34, count 2 2006.285.08:31:03.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:31:03.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:31:03.99#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.08:31:03.99#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:03.99#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:31:04.11#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:31:04.11#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:31:04.11#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:31:04.11#ibcon#first serial, iclass 34, count 0 2006.285.08:31:04.11#ibcon#enter sib2, iclass 34, count 0 2006.285.08:31:04.11#ibcon#flushed, iclass 34, count 0 2006.285.08:31:04.11#ibcon#about to write, iclass 34, count 0 2006.285.08:31:04.11#ibcon#wrote, iclass 34, count 0 2006.285.08:31:04.11#ibcon#about to read 3, iclass 34, count 0 2006.285.08:31:04.13#ibcon#read 3, iclass 34, count 0 2006.285.08:31:04.13#ibcon#about to read 4, iclass 34, count 0 2006.285.08:31:04.13#ibcon#read 4, iclass 34, count 0 2006.285.08:31:04.13#ibcon#about to read 5, iclass 34, count 0 2006.285.08:31:04.13#ibcon#read 5, iclass 34, count 0 2006.285.08:31:04.13#ibcon#about to read 6, iclass 34, count 0 2006.285.08:31:04.13#ibcon#read 6, iclass 34, count 0 2006.285.08:31:04.13#ibcon#end of sib2, iclass 34, count 0 2006.285.08:31:04.13#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:31:04.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:31:04.13#ibcon#[25=USB\r\n] 2006.285.08:31:04.13#ibcon#*before write, iclass 34, count 0 2006.285.08:31:04.13#ibcon#enter sib2, iclass 34, count 0 2006.285.08:31:04.13#ibcon#flushed, iclass 34, count 0 2006.285.08:31:04.13#ibcon#about to write, iclass 34, count 0 2006.285.08:31:04.13#ibcon#wrote, iclass 34, count 0 2006.285.08:31:04.13#ibcon#about to read 3, iclass 34, count 0 2006.285.08:31:04.16#ibcon#read 3, iclass 34, count 0 2006.285.08:31:04.16#ibcon#about to read 4, iclass 34, count 0 2006.285.08:31:04.16#ibcon#read 4, iclass 34, count 0 2006.285.08:31:04.16#ibcon#about to read 5, iclass 34, count 0 2006.285.08:31:04.16#ibcon#read 5, iclass 34, count 0 2006.285.08:31:04.16#ibcon#about to read 6, iclass 34, count 0 2006.285.08:31:04.16#ibcon#read 6, iclass 34, count 0 2006.285.08:31:04.16#ibcon#end of sib2, iclass 34, count 0 2006.285.08:31:04.16#ibcon#*after write, iclass 34, count 0 2006.285.08:31:04.16#ibcon#*before return 0, iclass 34, count 0 2006.285.08:31:04.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:31:04.16#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:31:04.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:31:04.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:31:04.16$vck44/valo=8,884.99 2006.285.08:31:04.16#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.08:31:04.16#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.08:31:04.16#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:04.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:31:04.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:31:04.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:31:04.16#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:31:04.16#ibcon#first serial, iclass 36, count 0 2006.285.08:31:04.16#ibcon#enter sib2, iclass 36, count 0 2006.285.08:31:04.16#ibcon#flushed, iclass 36, count 0 2006.285.08:31:04.16#ibcon#about to write, iclass 36, count 0 2006.285.08:31:04.16#ibcon#wrote, iclass 36, count 0 2006.285.08:31:04.16#ibcon#about to read 3, iclass 36, count 0 2006.285.08:31:04.18#ibcon#read 3, iclass 36, count 0 2006.285.08:31:04.18#ibcon#about to read 4, iclass 36, count 0 2006.285.08:31:04.18#ibcon#read 4, iclass 36, count 0 2006.285.08:31:04.18#ibcon#about to read 5, iclass 36, count 0 2006.285.08:31:04.18#ibcon#read 5, iclass 36, count 0 2006.285.08:31:04.18#ibcon#about to read 6, iclass 36, count 0 2006.285.08:31:04.18#ibcon#read 6, iclass 36, count 0 2006.285.08:31:04.18#ibcon#end of sib2, iclass 36, count 0 2006.285.08:31:04.18#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:31:04.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:31:04.18#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:31:04.18#ibcon#*before write, iclass 36, count 0 2006.285.08:31:04.18#ibcon#enter sib2, iclass 36, count 0 2006.285.08:31:04.18#ibcon#flushed, iclass 36, count 0 2006.285.08:31:04.18#ibcon#about to write, iclass 36, count 0 2006.285.08:31:04.18#ibcon#wrote, iclass 36, count 0 2006.285.08:31:04.18#ibcon#about to read 3, iclass 36, count 0 2006.285.08:31:04.22#ibcon#read 3, iclass 36, count 0 2006.285.08:31:04.22#ibcon#about to read 4, iclass 36, count 0 2006.285.08:31:04.22#ibcon#read 4, iclass 36, count 0 2006.285.08:31:04.22#ibcon#about to read 5, iclass 36, count 0 2006.285.08:31:04.22#ibcon#read 5, iclass 36, count 0 2006.285.08:31:04.22#ibcon#about to read 6, iclass 36, count 0 2006.285.08:31:04.22#ibcon#read 6, iclass 36, count 0 2006.285.08:31:04.22#ibcon#end of sib2, iclass 36, count 0 2006.285.08:31:04.22#ibcon#*after write, iclass 36, count 0 2006.285.08:31:04.22#ibcon#*before return 0, iclass 36, count 0 2006.285.08:31:04.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:31:04.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:31:04.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:31:04.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:31:04.22$vck44/va=8,3 2006.285.08:31:04.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.08:31:04.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.08:31:04.22#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:04.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:31:04.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:31:04.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:31:04.28#ibcon#enter wrdev, iclass 38, count 2 2006.285.08:31:04.28#ibcon#first serial, iclass 38, count 2 2006.285.08:31:04.28#ibcon#enter sib2, iclass 38, count 2 2006.285.08:31:04.28#ibcon#flushed, iclass 38, count 2 2006.285.08:31:04.28#ibcon#about to write, iclass 38, count 2 2006.285.08:31:04.28#ibcon#wrote, iclass 38, count 2 2006.285.08:31:04.28#ibcon#about to read 3, iclass 38, count 2 2006.285.08:31:04.30#ibcon#read 3, iclass 38, count 2 2006.285.08:31:04.30#ibcon#about to read 4, iclass 38, count 2 2006.285.08:31:04.30#ibcon#read 4, iclass 38, count 2 2006.285.08:31:04.30#ibcon#about to read 5, iclass 38, count 2 2006.285.08:31:04.30#ibcon#read 5, iclass 38, count 2 2006.285.08:31:04.30#ibcon#about to read 6, iclass 38, count 2 2006.285.08:31:04.30#ibcon#read 6, iclass 38, count 2 2006.285.08:31:04.30#ibcon#end of sib2, iclass 38, count 2 2006.285.08:31:04.30#ibcon#*mode == 0, iclass 38, count 2 2006.285.08:31:04.30#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.08:31:04.30#ibcon#[25=AT08-03\r\n] 2006.285.08:31:04.30#ibcon#*before write, iclass 38, count 2 2006.285.08:31:04.30#ibcon#enter sib2, iclass 38, count 2 2006.285.08:31:04.30#ibcon#flushed, iclass 38, count 2 2006.285.08:31:04.30#ibcon#about to write, iclass 38, count 2 2006.285.08:31:04.30#ibcon#wrote, iclass 38, count 2 2006.285.08:31:04.30#ibcon#about to read 3, iclass 38, count 2 2006.285.08:31:04.33#ibcon#read 3, iclass 38, count 2 2006.285.08:31:04.33#ibcon#about to read 4, iclass 38, count 2 2006.285.08:31:04.33#ibcon#read 4, iclass 38, count 2 2006.285.08:31:04.33#ibcon#about to read 5, iclass 38, count 2 2006.285.08:31:04.33#ibcon#read 5, iclass 38, count 2 2006.285.08:31:04.33#ibcon#about to read 6, iclass 38, count 2 2006.285.08:31:04.33#ibcon#read 6, iclass 38, count 2 2006.285.08:31:04.33#ibcon#end of sib2, iclass 38, count 2 2006.285.08:31:04.33#ibcon#*after write, iclass 38, count 2 2006.285.08:31:04.33#ibcon#*before return 0, iclass 38, count 2 2006.285.08:31:04.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:31:04.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:31:04.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.08:31:04.33#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:04.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:31:04.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:31:04.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:31:04.45#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:31:04.45#ibcon#first serial, iclass 38, count 0 2006.285.08:31:04.45#ibcon#enter sib2, iclass 38, count 0 2006.285.08:31:04.45#ibcon#flushed, iclass 38, count 0 2006.285.08:31:04.45#ibcon#about to write, iclass 38, count 0 2006.285.08:31:04.45#ibcon#wrote, iclass 38, count 0 2006.285.08:31:04.45#ibcon#about to read 3, iclass 38, count 0 2006.285.08:31:04.47#ibcon#read 3, iclass 38, count 0 2006.285.08:31:04.47#ibcon#about to read 4, iclass 38, count 0 2006.285.08:31:04.47#ibcon#read 4, iclass 38, count 0 2006.285.08:31:04.47#ibcon#about to read 5, iclass 38, count 0 2006.285.08:31:04.47#ibcon#read 5, iclass 38, count 0 2006.285.08:31:04.47#ibcon#about to read 6, iclass 38, count 0 2006.285.08:31:04.47#ibcon#read 6, iclass 38, count 0 2006.285.08:31:04.47#ibcon#end of sib2, iclass 38, count 0 2006.285.08:31:04.47#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:31:04.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:31:04.47#ibcon#[25=USB\r\n] 2006.285.08:31:04.47#ibcon#*before write, iclass 38, count 0 2006.285.08:31:04.47#ibcon#enter sib2, iclass 38, count 0 2006.285.08:31:04.47#ibcon#flushed, iclass 38, count 0 2006.285.08:31:04.47#ibcon#about to write, iclass 38, count 0 2006.285.08:31:04.47#ibcon#wrote, iclass 38, count 0 2006.285.08:31:04.47#ibcon#about to read 3, iclass 38, count 0 2006.285.08:31:04.50#ibcon#read 3, iclass 38, count 0 2006.285.08:31:04.50#ibcon#about to read 4, iclass 38, count 0 2006.285.08:31:04.50#ibcon#read 4, iclass 38, count 0 2006.285.08:31:04.50#ibcon#about to read 5, iclass 38, count 0 2006.285.08:31:04.50#ibcon#read 5, iclass 38, count 0 2006.285.08:31:04.50#ibcon#about to read 6, iclass 38, count 0 2006.285.08:31:04.50#ibcon#read 6, iclass 38, count 0 2006.285.08:31:04.50#ibcon#end of sib2, iclass 38, count 0 2006.285.08:31:04.50#ibcon#*after write, iclass 38, count 0 2006.285.08:31:04.50#ibcon#*before return 0, iclass 38, count 0 2006.285.08:31:04.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:31:04.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:31:04.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:31:04.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:31:04.50$vck44/vblo=1,629.99 2006.285.08:31:04.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.08:31:04.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.08:31:04.50#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:04.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:31:04.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:31:04.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:31:04.50#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:31:04.50#ibcon#first serial, iclass 40, count 0 2006.285.08:31:04.50#ibcon#enter sib2, iclass 40, count 0 2006.285.08:31:04.50#ibcon#flushed, iclass 40, count 0 2006.285.08:31:04.50#ibcon#about to write, iclass 40, count 0 2006.285.08:31:04.50#ibcon#wrote, iclass 40, count 0 2006.285.08:31:04.50#ibcon#about to read 3, iclass 40, count 0 2006.285.08:31:04.52#ibcon#read 3, iclass 40, count 0 2006.285.08:31:04.52#ibcon#about to read 4, iclass 40, count 0 2006.285.08:31:04.52#ibcon#read 4, iclass 40, count 0 2006.285.08:31:04.52#ibcon#about to read 5, iclass 40, count 0 2006.285.08:31:04.52#ibcon#read 5, iclass 40, count 0 2006.285.08:31:04.52#ibcon#about to read 6, iclass 40, count 0 2006.285.08:31:04.52#ibcon#read 6, iclass 40, count 0 2006.285.08:31:04.52#ibcon#end of sib2, iclass 40, count 0 2006.285.08:31:04.52#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:31:04.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:31:04.52#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:31:04.52#ibcon#*before write, iclass 40, count 0 2006.285.08:31:04.52#ibcon#enter sib2, iclass 40, count 0 2006.285.08:31:04.52#ibcon#flushed, iclass 40, count 0 2006.285.08:31:04.52#ibcon#about to write, iclass 40, count 0 2006.285.08:31:04.52#ibcon#wrote, iclass 40, count 0 2006.285.08:31:04.52#ibcon#about to read 3, iclass 40, count 0 2006.285.08:31:04.56#ibcon#read 3, iclass 40, count 0 2006.285.08:31:04.56#ibcon#about to read 4, iclass 40, count 0 2006.285.08:31:04.56#ibcon#read 4, iclass 40, count 0 2006.285.08:31:04.56#ibcon#about to read 5, iclass 40, count 0 2006.285.08:31:04.56#ibcon#read 5, iclass 40, count 0 2006.285.08:31:04.56#ibcon#about to read 6, iclass 40, count 0 2006.285.08:31:04.56#ibcon#read 6, iclass 40, count 0 2006.285.08:31:04.56#ibcon#end of sib2, iclass 40, count 0 2006.285.08:31:04.56#ibcon#*after write, iclass 40, count 0 2006.285.08:31:04.56#ibcon#*before return 0, iclass 40, count 0 2006.285.08:31:04.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:31:04.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:31:04.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:31:04.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:31:04.56$vck44/vb=1,4 2006.285.08:31:04.56#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.08:31:04.56#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.08:31:04.56#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:04.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:31:04.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:31:04.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:31:04.56#ibcon#enter wrdev, iclass 4, count 2 2006.285.08:31:04.56#ibcon#first serial, iclass 4, count 2 2006.285.08:31:04.56#ibcon#enter sib2, iclass 4, count 2 2006.285.08:31:04.56#ibcon#flushed, iclass 4, count 2 2006.285.08:31:04.56#ibcon#about to write, iclass 4, count 2 2006.285.08:31:04.56#ibcon#wrote, iclass 4, count 2 2006.285.08:31:04.56#ibcon#about to read 3, iclass 4, count 2 2006.285.08:31:04.58#ibcon#read 3, iclass 4, count 2 2006.285.08:31:04.58#ibcon#about to read 4, iclass 4, count 2 2006.285.08:31:04.58#ibcon#read 4, iclass 4, count 2 2006.285.08:31:04.58#ibcon#about to read 5, iclass 4, count 2 2006.285.08:31:04.58#ibcon#read 5, iclass 4, count 2 2006.285.08:31:04.58#ibcon#about to read 6, iclass 4, count 2 2006.285.08:31:04.58#ibcon#read 6, iclass 4, count 2 2006.285.08:31:04.58#ibcon#end of sib2, iclass 4, count 2 2006.285.08:31:04.58#ibcon#*mode == 0, iclass 4, count 2 2006.285.08:31:04.58#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.08:31:04.58#ibcon#[27=AT01-04\r\n] 2006.285.08:31:04.58#ibcon#*before write, iclass 4, count 2 2006.285.08:31:04.58#ibcon#enter sib2, iclass 4, count 2 2006.285.08:31:04.58#ibcon#flushed, iclass 4, count 2 2006.285.08:31:04.58#ibcon#about to write, iclass 4, count 2 2006.285.08:31:04.58#ibcon#wrote, iclass 4, count 2 2006.285.08:31:04.58#ibcon#about to read 3, iclass 4, count 2 2006.285.08:31:04.61#ibcon#read 3, iclass 4, count 2 2006.285.08:31:04.61#ibcon#about to read 4, iclass 4, count 2 2006.285.08:31:04.61#ibcon#read 4, iclass 4, count 2 2006.285.08:31:04.61#ibcon#about to read 5, iclass 4, count 2 2006.285.08:31:04.61#ibcon#read 5, iclass 4, count 2 2006.285.08:31:04.61#ibcon#about to read 6, iclass 4, count 2 2006.285.08:31:04.61#ibcon#read 6, iclass 4, count 2 2006.285.08:31:04.61#ibcon#end of sib2, iclass 4, count 2 2006.285.08:31:04.61#ibcon#*after write, iclass 4, count 2 2006.285.08:31:04.61#ibcon#*before return 0, iclass 4, count 2 2006.285.08:31:04.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:31:04.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:31:04.61#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.08:31:04.61#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:04.61#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:31:04.73#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:31:04.73#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:31:04.73#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:31:04.73#ibcon#first serial, iclass 4, count 0 2006.285.08:31:04.73#ibcon#enter sib2, iclass 4, count 0 2006.285.08:31:04.73#ibcon#flushed, iclass 4, count 0 2006.285.08:31:04.73#ibcon#about to write, iclass 4, count 0 2006.285.08:31:04.73#ibcon#wrote, iclass 4, count 0 2006.285.08:31:04.73#ibcon#about to read 3, iclass 4, count 0 2006.285.08:31:04.75#ibcon#read 3, iclass 4, count 0 2006.285.08:31:04.75#ibcon#about to read 4, iclass 4, count 0 2006.285.08:31:04.75#ibcon#read 4, iclass 4, count 0 2006.285.08:31:04.75#ibcon#about to read 5, iclass 4, count 0 2006.285.08:31:04.75#ibcon#read 5, iclass 4, count 0 2006.285.08:31:04.75#ibcon#about to read 6, iclass 4, count 0 2006.285.08:31:04.75#ibcon#read 6, iclass 4, count 0 2006.285.08:31:04.75#ibcon#end of sib2, iclass 4, count 0 2006.285.08:31:04.75#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:31:04.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:31:04.75#ibcon#[27=USB\r\n] 2006.285.08:31:04.75#ibcon#*before write, iclass 4, count 0 2006.285.08:31:04.75#ibcon#enter sib2, iclass 4, count 0 2006.285.08:31:04.75#ibcon#flushed, iclass 4, count 0 2006.285.08:31:04.75#ibcon#about to write, iclass 4, count 0 2006.285.08:31:04.75#ibcon#wrote, iclass 4, count 0 2006.285.08:31:04.75#ibcon#about to read 3, iclass 4, count 0 2006.285.08:31:04.78#ibcon#read 3, iclass 4, count 0 2006.285.08:31:04.78#ibcon#about to read 4, iclass 4, count 0 2006.285.08:31:04.78#ibcon#read 4, iclass 4, count 0 2006.285.08:31:04.78#ibcon#about to read 5, iclass 4, count 0 2006.285.08:31:04.78#ibcon#read 5, iclass 4, count 0 2006.285.08:31:04.78#ibcon#about to read 6, iclass 4, count 0 2006.285.08:31:04.78#ibcon#read 6, iclass 4, count 0 2006.285.08:31:04.78#ibcon#end of sib2, iclass 4, count 0 2006.285.08:31:04.78#ibcon#*after write, iclass 4, count 0 2006.285.08:31:04.78#ibcon#*before return 0, iclass 4, count 0 2006.285.08:31:04.78#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:31:04.78#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:31:04.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:31:04.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:31:04.78$vck44/vblo=2,634.99 2006.285.08:31:04.78#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.08:31:04.78#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.08:31:04.78#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:04.78#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:31:04.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:31:04.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:31:04.78#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:31:04.78#ibcon#first serial, iclass 6, count 0 2006.285.08:31:04.78#ibcon#enter sib2, iclass 6, count 0 2006.285.08:31:04.78#ibcon#flushed, iclass 6, count 0 2006.285.08:31:04.78#ibcon#about to write, iclass 6, count 0 2006.285.08:31:04.78#ibcon#wrote, iclass 6, count 0 2006.285.08:31:04.78#ibcon#about to read 3, iclass 6, count 0 2006.285.08:31:04.80#ibcon#read 3, iclass 6, count 0 2006.285.08:31:04.80#ibcon#about to read 4, iclass 6, count 0 2006.285.08:31:04.80#ibcon#read 4, iclass 6, count 0 2006.285.08:31:04.80#ibcon#about to read 5, iclass 6, count 0 2006.285.08:31:04.80#ibcon#read 5, iclass 6, count 0 2006.285.08:31:04.80#ibcon#about to read 6, iclass 6, count 0 2006.285.08:31:04.80#ibcon#read 6, iclass 6, count 0 2006.285.08:31:04.80#ibcon#end of sib2, iclass 6, count 0 2006.285.08:31:04.80#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:31:04.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:31:04.80#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:31:04.80#ibcon#*before write, iclass 6, count 0 2006.285.08:31:04.80#ibcon#enter sib2, iclass 6, count 0 2006.285.08:31:04.80#ibcon#flushed, iclass 6, count 0 2006.285.08:31:04.80#ibcon#about to write, iclass 6, count 0 2006.285.08:31:04.80#ibcon#wrote, iclass 6, count 0 2006.285.08:31:04.80#ibcon#about to read 3, iclass 6, count 0 2006.285.08:31:04.84#ibcon#read 3, iclass 6, count 0 2006.285.08:31:04.84#ibcon#about to read 4, iclass 6, count 0 2006.285.08:31:04.84#ibcon#read 4, iclass 6, count 0 2006.285.08:31:04.84#ibcon#about to read 5, iclass 6, count 0 2006.285.08:31:04.84#ibcon#read 5, iclass 6, count 0 2006.285.08:31:04.84#ibcon#about to read 6, iclass 6, count 0 2006.285.08:31:04.84#ibcon#read 6, iclass 6, count 0 2006.285.08:31:04.84#ibcon#end of sib2, iclass 6, count 0 2006.285.08:31:04.84#ibcon#*after write, iclass 6, count 0 2006.285.08:31:04.84#ibcon#*before return 0, iclass 6, count 0 2006.285.08:31:04.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:31:04.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:31:04.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:31:04.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:31:04.84$vck44/vb=2,5 2006.285.08:31:04.84#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.08:31:04.84#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.08:31:04.84#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:04.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:31:04.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:31:04.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:31:04.90#ibcon#enter wrdev, iclass 10, count 2 2006.285.08:31:04.90#ibcon#first serial, iclass 10, count 2 2006.285.08:31:04.90#ibcon#enter sib2, iclass 10, count 2 2006.285.08:31:04.90#ibcon#flushed, iclass 10, count 2 2006.285.08:31:04.90#ibcon#about to write, iclass 10, count 2 2006.285.08:31:04.90#ibcon#wrote, iclass 10, count 2 2006.285.08:31:04.90#ibcon#about to read 3, iclass 10, count 2 2006.285.08:31:04.92#ibcon#read 3, iclass 10, count 2 2006.285.08:31:04.92#ibcon#about to read 4, iclass 10, count 2 2006.285.08:31:04.92#ibcon#read 4, iclass 10, count 2 2006.285.08:31:04.92#ibcon#about to read 5, iclass 10, count 2 2006.285.08:31:04.92#ibcon#read 5, iclass 10, count 2 2006.285.08:31:04.92#ibcon#about to read 6, iclass 10, count 2 2006.285.08:31:04.92#ibcon#read 6, iclass 10, count 2 2006.285.08:31:04.92#ibcon#end of sib2, iclass 10, count 2 2006.285.08:31:04.92#ibcon#*mode == 0, iclass 10, count 2 2006.285.08:31:04.92#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.08:31:04.92#ibcon#[27=AT02-05\r\n] 2006.285.08:31:04.92#ibcon#*before write, iclass 10, count 2 2006.285.08:31:04.92#ibcon#enter sib2, iclass 10, count 2 2006.285.08:31:04.92#ibcon#flushed, iclass 10, count 2 2006.285.08:31:04.92#ibcon#about to write, iclass 10, count 2 2006.285.08:31:04.92#ibcon#wrote, iclass 10, count 2 2006.285.08:31:04.92#ibcon#about to read 3, iclass 10, count 2 2006.285.08:31:04.95#ibcon#read 3, iclass 10, count 2 2006.285.08:31:04.95#ibcon#about to read 4, iclass 10, count 2 2006.285.08:31:04.95#ibcon#read 4, iclass 10, count 2 2006.285.08:31:04.95#ibcon#about to read 5, iclass 10, count 2 2006.285.08:31:04.95#ibcon#read 5, iclass 10, count 2 2006.285.08:31:04.95#ibcon#about to read 6, iclass 10, count 2 2006.285.08:31:04.95#ibcon#read 6, iclass 10, count 2 2006.285.08:31:04.95#ibcon#end of sib2, iclass 10, count 2 2006.285.08:31:04.95#ibcon#*after write, iclass 10, count 2 2006.285.08:31:04.95#ibcon#*before return 0, iclass 10, count 2 2006.285.08:31:04.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:31:04.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:31:04.95#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.08:31:04.95#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:04.95#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:31:05.07#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:31:05.07#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:31:05.07#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:31:05.07#ibcon#first serial, iclass 10, count 0 2006.285.08:31:05.07#ibcon#enter sib2, iclass 10, count 0 2006.285.08:31:05.07#ibcon#flushed, iclass 10, count 0 2006.285.08:31:05.07#ibcon#about to write, iclass 10, count 0 2006.285.08:31:05.07#ibcon#wrote, iclass 10, count 0 2006.285.08:31:05.07#ibcon#about to read 3, iclass 10, count 0 2006.285.08:31:05.09#ibcon#read 3, iclass 10, count 0 2006.285.08:31:05.09#ibcon#about to read 4, iclass 10, count 0 2006.285.08:31:05.09#ibcon#read 4, iclass 10, count 0 2006.285.08:31:05.09#ibcon#about to read 5, iclass 10, count 0 2006.285.08:31:05.09#ibcon#read 5, iclass 10, count 0 2006.285.08:31:05.09#ibcon#about to read 6, iclass 10, count 0 2006.285.08:31:05.09#ibcon#read 6, iclass 10, count 0 2006.285.08:31:05.09#ibcon#end of sib2, iclass 10, count 0 2006.285.08:31:05.09#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:31:05.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:31:05.09#ibcon#[27=USB\r\n] 2006.285.08:31:05.09#ibcon#*before write, iclass 10, count 0 2006.285.08:31:05.09#ibcon#enter sib2, iclass 10, count 0 2006.285.08:31:05.09#ibcon#flushed, iclass 10, count 0 2006.285.08:31:05.09#ibcon#about to write, iclass 10, count 0 2006.285.08:31:05.09#ibcon#wrote, iclass 10, count 0 2006.285.08:31:05.09#ibcon#about to read 3, iclass 10, count 0 2006.285.08:31:05.12#ibcon#read 3, iclass 10, count 0 2006.285.08:31:05.12#ibcon#about to read 4, iclass 10, count 0 2006.285.08:31:05.12#ibcon#read 4, iclass 10, count 0 2006.285.08:31:05.12#ibcon#about to read 5, iclass 10, count 0 2006.285.08:31:05.12#ibcon#read 5, iclass 10, count 0 2006.285.08:31:05.12#ibcon#about to read 6, iclass 10, count 0 2006.285.08:31:05.12#ibcon#read 6, iclass 10, count 0 2006.285.08:31:05.12#ibcon#end of sib2, iclass 10, count 0 2006.285.08:31:05.12#ibcon#*after write, iclass 10, count 0 2006.285.08:31:05.12#ibcon#*before return 0, iclass 10, count 0 2006.285.08:31:05.12#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:31:05.12#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:31:05.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:31:05.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:31:05.12$vck44/vblo=3,649.99 2006.285.08:31:05.12#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.08:31:05.12#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.08:31:05.12#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:05.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:31:05.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:31:05.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:31:05.12#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:31:05.12#ibcon#first serial, iclass 12, count 0 2006.285.08:31:05.12#ibcon#enter sib2, iclass 12, count 0 2006.285.08:31:05.12#ibcon#flushed, iclass 12, count 0 2006.285.08:31:05.12#ibcon#about to write, iclass 12, count 0 2006.285.08:31:05.12#ibcon#wrote, iclass 12, count 0 2006.285.08:31:05.12#ibcon#about to read 3, iclass 12, count 0 2006.285.08:31:05.14#ibcon#read 3, iclass 12, count 0 2006.285.08:31:05.14#ibcon#about to read 4, iclass 12, count 0 2006.285.08:31:05.14#ibcon#read 4, iclass 12, count 0 2006.285.08:31:05.14#ibcon#about to read 5, iclass 12, count 0 2006.285.08:31:05.14#ibcon#read 5, iclass 12, count 0 2006.285.08:31:05.14#ibcon#about to read 6, iclass 12, count 0 2006.285.08:31:05.14#ibcon#read 6, iclass 12, count 0 2006.285.08:31:05.14#ibcon#end of sib2, iclass 12, count 0 2006.285.08:31:05.14#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:31:05.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:31:05.14#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:31:05.14#ibcon#*before write, iclass 12, count 0 2006.285.08:31:05.14#ibcon#enter sib2, iclass 12, count 0 2006.285.08:31:05.14#ibcon#flushed, iclass 12, count 0 2006.285.08:31:05.14#ibcon#about to write, iclass 12, count 0 2006.285.08:31:05.14#ibcon#wrote, iclass 12, count 0 2006.285.08:31:05.14#ibcon#about to read 3, iclass 12, count 0 2006.285.08:31:05.18#ibcon#read 3, iclass 12, count 0 2006.285.08:31:05.18#ibcon#about to read 4, iclass 12, count 0 2006.285.08:31:05.18#ibcon#read 4, iclass 12, count 0 2006.285.08:31:05.18#ibcon#about to read 5, iclass 12, count 0 2006.285.08:31:05.18#ibcon#read 5, iclass 12, count 0 2006.285.08:31:05.18#ibcon#about to read 6, iclass 12, count 0 2006.285.08:31:05.18#ibcon#read 6, iclass 12, count 0 2006.285.08:31:05.18#ibcon#end of sib2, iclass 12, count 0 2006.285.08:31:05.18#ibcon#*after write, iclass 12, count 0 2006.285.08:31:05.18#ibcon#*before return 0, iclass 12, count 0 2006.285.08:31:05.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:31:05.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:31:05.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:31:05.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:31:05.18$vck44/vb=3,4 2006.285.08:31:05.18#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.08:31:05.18#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.08:31:05.18#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:05.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:31:05.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:31:05.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:31:05.24#ibcon#enter wrdev, iclass 14, count 2 2006.285.08:31:05.24#ibcon#first serial, iclass 14, count 2 2006.285.08:31:05.24#ibcon#enter sib2, iclass 14, count 2 2006.285.08:31:05.24#ibcon#flushed, iclass 14, count 2 2006.285.08:31:05.24#ibcon#about to write, iclass 14, count 2 2006.285.08:31:05.24#ibcon#wrote, iclass 14, count 2 2006.285.08:31:05.24#ibcon#about to read 3, iclass 14, count 2 2006.285.08:31:05.26#ibcon#read 3, iclass 14, count 2 2006.285.08:31:05.26#ibcon#about to read 4, iclass 14, count 2 2006.285.08:31:05.26#ibcon#read 4, iclass 14, count 2 2006.285.08:31:05.26#ibcon#about to read 5, iclass 14, count 2 2006.285.08:31:05.26#ibcon#read 5, iclass 14, count 2 2006.285.08:31:05.26#ibcon#about to read 6, iclass 14, count 2 2006.285.08:31:05.26#ibcon#read 6, iclass 14, count 2 2006.285.08:31:05.26#ibcon#end of sib2, iclass 14, count 2 2006.285.08:31:05.26#ibcon#*mode == 0, iclass 14, count 2 2006.285.08:31:05.26#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.08:31:05.26#ibcon#[27=AT03-04\r\n] 2006.285.08:31:05.26#ibcon#*before write, iclass 14, count 2 2006.285.08:31:05.26#ibcon#enter sib2, iclass 14, count 2 2006.285.08:31:05.26#ibcon#flushed, iclass 14, count 2 2006.285.08:31:05.26#ibcon#about to write, iclass 14, count 2 2006.285.08:31:05.26#ibcon#wrote, iclass 14, count 2 2006.285.08:31:05.26#ibcon#about to read 3, iclass 14, count 2 2006.285.08:31:05.29#ibcon#read 3, iclass 14, count 2 2006.285.08:31:05.29#ibcon#about to read 4, iclass 14, count 2 2006.285.08:31:05.29#ibcon#read 4, iclass 14, count 2 2006.285.08:31:05.29#ibcon#about to read 5, iclass 14, count 2 2006.285.08:31:05.29#ibcon#read 5, iclass 14, count 2 2006.285.08:31:05.29#ibcon#about to read 6, iclass 14, count 2 2006.285.08:31:05.29#ibcon#read 6, iclass 14, count 2 2006.285.08:31:05.29#ibcon#end of sib2, iclass 14, count 2 2006.285.08:31:05.29#ibcon#*after write, iclass 14, count 2 2006.285.08:31:05.29#ibcon#*before return 0, iclass 14, count 2 2006.285.08:31:05.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:31:05.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:31:05.29#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.08:31:05.29#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:05.29#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:31:05.41#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:31:05.41#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:31:05.41#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:31:05.41#ibcon#first serial, iclass 14, count 0 2006.285.08:31:05.41#ibcon#enter sib2, iclass 14, count 0 2006.285.08:31:05.41#ibcon#flushed, iclass 14, count 0 2006.285.08:31:05.41#ibcon#about to write, iclass 14, count 0 2006.285.08:31:05.41#ibcon#wrote, iclass 14, count 0 2006.285.08:31:05.41#ibcon#about to read 3, iclass 14, count 0 2006.285.08:31:05.43#ibcon#read 3, iclass 14, count 0 2006.285.08:31:05.43#ibcon#about to read 4, iclass 14, count 0 2006.285.08:31:05.43#ibcon#read 4, iclass 14, count 0 2006.285.08:31:05.43#ibcon#about to read 5, iclass 14, count 0 2006.285.08:31:05.43#ibcon#read 5, iclass 14, count 0 2006.285.08:31:05.43#ibcon#about to read 6, iclass 14, count 0 2006.285.08:31:05.43#ibcon#read 6, iclass 14, count 0 2006.285.08:31:05.43#ibcon#end of sib2, iclass 14, count 0 2006.285.08:31:05.43#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:31:05.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:31:05.43#ibcon#[27=USB\r\n] 2006.285.08:31:05.43#ibcon#*before write, iclass 14, count 0 2006.285.08:31:05.43#ibcon#enter sib2, iclass 14, count 0 2006.285.08:31:05.43#ibcon#flushed, iclass 14, count 0 2006.285.08:31:05.43#ibcon#about to write, iclass 14, count 0 2006.285.08:31:05.43#ibcon#wrote, iclass 14, count 0 2006.285.08:31:05.43#ibcon#about to read 3, iclass 14, count 0 2006.285.08:31:05.46#ibcon#read 3, iclass 14, count 0 2006.285.08:31:05.46#ibcon#about to read 4, iclass 14, count 0 2006.285.08:31:05.46#ibcon#read 4, iclass 14, count 0 2006.285.08:31:05.46#ibcon#about to read 5, iclass 14, count 0 2006.285.08:31:05.46#ibcon#read 5, iclass 14, count 0 2006.285.08:31:05.46#ibcon#about to read 6, iclass 14, count 0 2006.285.08:31:05.46#ibcon#read 6, iclass 14, count 0 2006.285.08:31:05.46#ibcon#end of sib2, iclass 14, count 0 2006.285.08:31:05.46#ibcon#*after write, iclass 14, count 0 2006.285.08:31:05.46#ibcon#*before return 0, iclass 14, count 0 2006.285.08:31:05.46#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:31:05.46#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:31:05.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:31:05.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:31:05.46$vck44/vblo=4,679.99 2006.285.08:31:05.46#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.08:31:05.46#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.08:31:05.46#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:05.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:31:05.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:31:05.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:31:05.46#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:31:05.46#ibcon#first serial, iclass 16, count 0 2006.285.08:31:05.46#ibcon#enter sib2, iclass 16, count 0 2006.285.08:31:05.46#ibcon#flushed, iclass 16, count 0 2006.285.08:31:05.46#ibcon#about to write, iclass 16, count 0 2006.285.08:31:05.46#ibcon#wrote, iclass 16, count 0 2006.285.08:31:05.46#ibcon#about to read 3, iclass 16, count 0 2006.285.08:31:05.48#ibcon#read 3, iclass 16, count 0 2006.285.08:31:05.48#ibcon#about to read 4, iclass 16, count 0 2006.285.08:31:05.48#ibcon#read 4, iclass 16, count 0 2006.285.08:31:05.48#ibcon#about to read 5, iclass 16, count 0 2006.285.08:31:05.48#ibcon#read 5, iclass 16, count 0 2006.285.08:31:05.48#ibcon#about to read 6, iclass 16, count 0 2006.285.08:31:05.48#ibcon#read 6, iclass 16, count 0 2006.285.08:31:05.48#ibcon#end of sib2, iclass 16, count 0 2006.285.08:31:05.48#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:31:05.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:31:05.48#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:31:05.48#ibcon#*before write, iclass 16, count 0 2006.285.08:31:05.48#ibcon#enter sib2, iclass 16, count 0 2006.285.08:31:05.48#ibcon#flushed, iclass 16, count 0 2006.285.08:31:05.48#ibcon#about to write, iclass 16, count 0 2006.285.08:31:05.48#ibcon#wrote, iclass 16, count 0 2006.285.08:31:05.48#ibcon#about to read 3, iclass 16, count 0 2006.285.08:31:05.52#ibcon#read 3, iclass 16, count 0 2006.285.08:31:05.52#ibcon#about to read 4, iclass 16, count 0 2006.285.08:31:05.52#ibcon#read 4, iclass 16, count 0 2006.285.08:31:05.52#ibcon#about to read 5, iclass 16, count 0 2006.285.08:31:05.52#ibcon#read 5, iclass 16, count 0 2006.285.08:31:05.52#ibcon#about to read 6, iclass 16, count 0 2006.285.08:31:05.52#ibcon#read 6, iclass 16, count 0 2006.285.08:31:05.52#ibcon#end of sib2, iclass 16, count 0 2006.285.08:31:05.52#ibcon#*after write, iclass 16, count 0 2006.285.08:31:05.52#ibcon#*before return 0, iclass 16, count 0 2006.285.08:31:05.52#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:31:05.52#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:31:05.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:31:05.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:31:05.52$vck44/vb=4,5 2006.285.08:31:05.52#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.08:31:05.52#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.08:31:05.52#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:05.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:31:05.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:31:05.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:31:05.58#ibcon#enter wrdev, iclass 18, count 2 2006.285.08:31:05.58#ibcon#first serial, iclass 18, count 2 2006.285.08:31:05.58#ibcon#enter sib2, iclass 18, count 2 2006.285.08:31:05.58#ibcon#flushed, iclass 18, count 2 2006.285.08:31:05.58#ibcon#about to write, iclass 18, count 2 2006.285.08:31:05.58#ibcon#wrote, iclass 18, count 2 2006.285.08:31:05.58#ibcon#about to read 3, iclass 18, count 2 2006.285.08:31:05.60#ibcon#read 3, iclass 18, count 2 2006.285.08:31:05.60#ibcon#about to read 4, iclass 18, count 2 2006.285.08:31:05.60#ibcon#read 4, iclass 18, count 2 2006.285.08:31:05.60#ibcon#about to read 5, iclass 18, count 2 2006.285.08:31:05.60#ibcon#read 5, iclass 18, count 2 2006.285.08:31:05.60#ibcon#about to read 6, iclass 18, count 2 2006.285.08:31:05.60#ibcon#read 6, iclass 18, count 2 2006.285.08:31:05.60#ibcon#end of sib2, iclass 18, count 2 2006.285.08:31:05.60#ibcon#*mode == 0, iclass 18, count 2 2006.285.08:31:05.60#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.08:31:05.60#ibcon#[27=AT04-05\r\n] 2006.285.08:31:05.60#ibcon#*before write, iclass 18, count 2 2006.285.08:31:05.60#ibcon#enter sib2, iclass 18, count 2 2006.285.08:31:05.60#ibcon#flushed, iclass 18, count 2 2006.285.08:31:05.60#ibcon#about to write, iclass 18, count 2 2006.285.08:31:05.60#ibcon#wrote, iclass 18, count 2 2006.285.08:31:05.60#ibcon#about to read 3, iclass 18, count 2 2006.285.08:31:05.63#ibcon#read 3, iclass 18, count 2 2006.285.08:31:05.63#ibcon#about to read 4, iclass 18, count 2 2006.285.08:31:05.63#ibcon#read 4, iclass 18, count 2 2006.285.08:31:05.63#ibcon#about to read 5, iclass 18, count 2 2006.285.08:31:05.63#ibcon#read 5, iclass 18, count 2 2006.285.08:31:05.63#ibcon#about to read 6, iclass 18, count 2 2006.285.08:31:05.63#ibcon#read 6, iclass 18, count 2 2006.285.08:31:05.63#ibcon#end of sib2, iclass 18, count 2 2006.285.08:31:05.63#ibcon#*after write, iclass 18, count 2 2006.285.08:31:05.63#ibcon#*before return 0, iclass 18, count 2 2006.285.08:31:05.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:31:05.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:31:05.63#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.08:31:05.63#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:05.63#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:31:05.66#abcon#<5=/04 1.6 3.0 22.20 811014.8\r\n> 2006.285.08:31:05.68#abcon#{5=INTERFACE CLEAR} 2006.285.08:31:05.74#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:31:05.75#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:31:05.75#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:31:05.75#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:31:05.75#ibcon#first serial, iclass 18, count 0 2006.285.08:31:05.75#ibcon#enter sib2, iclass 18, count 0 2006.285.08:31:05.75#ibcon#flushed, iclass 18, count 0 2006.285.08:31:05.75#ibcon#about to write, iclass 18, count 0 2006.285.08:31:05.75#ibcon#wrote, iclass 18, count 0 2006.285.08:31:05.75#ibcon#about to read 3, iclass 18, count 0 2006.285.08:31:05.77#ibcon#read 3, iclass 18, count 0 2006.285.08:31:05.77#ibcon#about to read 4, iclass 18, count 0 2006.285.08:31:05.77#ibcon#read 4, iclass 18, count 0 2006.285.08:31:05.77#ibcon#about to read 5, iclass 18, count 0 2006.285.08:31:05.77#ibcon#read 5, iclass 18, count 0 2006.285.08:31:05.77#ibcon#about to read 6, iclass 18, count 0 2006.285.08:31:05.77#ibcon#read 6, iclass 18, count 0 2006.285.08:31:05.77#ibcon#end of sib2, iclass 18, count 0 2006.285.08:31:05.77#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:31:05.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:31:05.77#ibcon#[27=USB\r\n] 2006.285.08:31:05.77#ibcon#*before write, iclass 18, count 0 2006.285.08:31:05.77#ibcon#enter sib2, iclass 18, count 0 2006.285.08:31:05.77#ibcon#flushed, iclass 18, count 0 2006.285.08:31:05.77#ibcon#about to write, iclass 18, count 0 2006.285.08:31:05.77#ibcon#wrote, iclass 18, count 0 2006.285.08:31:05.77#ibcon#about to read 3, iclass 18, count 0 2006.285.08:31:05.80#ibcon#read 3, iclass 18, count 0 2006.285.08:31:05.80#ibcon#about to read 4, iclass 18, count 0 2006.285.08:31:05.80#ibcon#read 4, iclass 18, count 0 2006.285.08:31:05.80#ibcon#about to read 5, iclass 18, count 0 2006.285.08:31:05.80#ibcon#read 5, iclass 18, count 0 2006.285.08:31:05.80#ibcon#about to read 6, iclass 18, count 0 2006.285.08:31:05.80#ibcon#read 6, iclass 18, count 0 2006.285.08:31:05.80#ibcon#end of sib2, iclass 18, count 0 2006.285.08:31:05.80#ibcon#*after write, iclass 18, count 0 2006.285.08:31:05.80#ibcon#*before return 0, iclass 18, count 0 2006.285.08:31:05.80#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:31:05.80#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:31:05.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:31:05.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:31:05.80$vck44/vblo=5,709.99 2006.285.08:31:05.80#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.08:31:05.80#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.08:31:05.80#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:05.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:31:05.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:31:05.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:31:05.80#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:31:05.80#ibcon#first serial, iclass 24, count 0 2006.285.08:31:05.80#ibcon#enter sib2, iclass 24, count 0 2006.285.08:31:05.80#ibcon#flushed, iclass 24, count 0 2006.285.08:31:05.80#ibcon#about to write, iclass 24, count 0 2006.285.08:31:05.80#ibcon#wrote, iclass 24, count 0 2006.285.08:31:05.80#ibcon#about to read 3, iclass 24, count 0 2006.285.08:31:05.82#ibcon#read 3, iclass 24, count 0 2006.285.08:31:05.82#ibcon#about to read 4, iclass 24, count 0 2006.285.08:31:05.82#ibcon#read 4, iclass 24, count 0 2006.285.08:31:05.82#ibcon#about to read 5, iclass 24, count 0 2006.285.08:31:05.82#ibcon#read 5, iclass 24, count 0 2006.285.08:31:05.82#ibcon#about to read 6, iclass 24, count 0 2006.285.08:31:05.82#ibcon#read 6, iclass 24, count 0 2006.285.08:31:05.82#ibcon#end of sib2, iclass 24, count 0 2006.285.08:31:05.82#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:31:05.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:31:05.82#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:31:05.82#ibcon#*before write, iclass 24, count 0 2006.285.08:31:05.82#ibcon#enter sib2, iclass 24, count 0 2006.285.08:31:05.82#ibcon#flushed, iclass 24, count 0 2006.285.08:31:05.82#ibcon#about to write, iclass 24, count 0 2006.285.08:31:05.82#ibcon#wrote, iclass 24, count 0 2006.285.08:31:05.82#ibcon#about to read 3, iclass 24, count 0 2006.285.08:31:05.86#ibcon#read 3, iclass 24, count 0 2006.285.08:31:05.86#ibcon#about to read 4, iclass 24, count 0 2006.285.08:31:05.86#ibcon#read 4, iclass 24, count 0 2006.285.08:31:05.86#ibcon#about to read 5, iclass 24, count 0 2006.285.08:31:05.86#ibcon#read 5, iclass 24, count 0 2006.285.08:31:05.86#ibcon#about to read 6, iclass 24, count 0 2006.285.08:31:05.86#ibcon#read 6, iclass 24, count 0 2006.285.08:31:05.86#ibcon#end of sib2, iclass 24, count 0 2006.285.08:31:05.86#ibcon#*after write, iclass 24, count 0 2006.285.08:31:05.86#ibcon#*before return 0, iclass 24, count 0 2006.285.08:31:05.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:31:05.86#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:31:05.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:31:05.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:31:05.86$vck44/vb=5,4 2006.285.08:31:05.86#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.08:31:05.86#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.08:31:05.86#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:05.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:31:05.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:31:05.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:31:05.92#ibcon#enter wrdev, iclass 26, count 2 2006.285.08:31:05.92#ibcon#first serial, iclass 26, count 2 2006.285.08:31:05.92#ibcon#enter sib2, iclass 26, count 2 2006.285.08:31:05.92#ibcon#flushed, iclass 26, count 2 2006.285.08:31:05.92#ibcon#about to write, iclass 26, count 2 2006.285.08:31:05.92#ibcon#wrote, iclass 26, count 2 2006.285.08:31:05.92#ibcon#about to read 3, iclass 26, count 2 2006.285.08:31:05.94#ibcon#read 3, iclass 26, count 2 2006.285.08:31:05.94#ibcon#about to read 4, iclass 26, count 2 2006.285.08:31:05.94#ibcon#read 4, iclass 26, count 2 2006.285.08:31:05.94#ibcon#about to read 5, iclass 26, count 2 2006.285.08:31:05.94#ibcon#read 5, iclass 26, count 2 2006.285.08:31:05.94#ibcon#about to read 6, iclass 26, count 2 2006.285.08:31:05.94#ibcon#read 6, iclass 26, count 2 2006.285.08:31:05.94#ibcon#end of sib2, iclass 26, count 2 2006.285.08:31:05.94#ibcon#*mode == 0, iclass 26, count 2 2006.285.08:31:05.94#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.08:31:05.94#ibcon#[27=AT05-04\r\n] 2006.285.08:31:05.94#ibcon#*before write, iclass 26, count 2 2006.285.08:31:05.94#ibcon#enter sib2, iclass 26, count 2 2006.285.08:31:05.94#ibcon#flushed, iclass 26, count 2 2006.285.08:31:05.94#ibcon#about to write, iclass 26, count 2 2006.285.08:31:05.94#ibcon#wrote, iclass 26, count 2 2006.285.08:31:05.94#ibcon#about to read 3, iclass 26, count 2 2006.285.08:31:05.97#ibcon#read 3, iclass 26, count 2 2006.285.08:31:05.97#ibcon#about to read 4, iclass 26, count 2 2006.285.08:31:05.97#ibcon#read 4, iclass 26, count 2 2006.285.08:31:05.97#ibcon#about to read 5, iclass 26, count 2 2006.285.08:31:05.97#ibcon#read 5, iclass 26, count 2 2006.285.08:31:05.97#ibcon#about to read 6, iclass 26, count 2 2006.285.08:31:05.97#ibcon#read 6, iclass 26, count 2 2006.285.08:31:05.97#ibcon#end of sib2, iclass 26, count 2 2006.285.08:31:05.97#ibcon#*after write, iclass 26, count 2 2006.285.08:31:05.97#ibcon#*before return 0, iclass 26, count 2 2006.285.08:31:05.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:31:05.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:31:05.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.08:31:05.97#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:05.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:31:06.09#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:31:06.09#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:31:06.09#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:31:06.09#ibcon#first serial, iclass 26, count 0 2006.285.08:31:06.09#ibcon#enter sib2, iclass 26, count 0 2006.285.08:31:06.09#ibcon#flushed, iclass 26, count 0 2006.285.08:31:06.09#ibcon#about to write, iclass 26, count 0 2006.285.08:31:06.09#ibcon#wrote, iclass 26, count 0 2006.285.08:31:06.09#ibcon#about to read 3, iclass 26, count 0 2006.285.08:31:06.11#ibcon#read 3, iclass 26, count 0 2006.285.08:31:06.11#ibcon#about to read 4, iclass 26, count 0 2006.285.08:31:06.11#ibcon#read 4, iclass 26, count 0 2006.285.08:31:06.11#ibcon#about to read 5, iclass 26, count 0 2006.285.08:31:06.11#ibcon#read 5, iclass 26, count 0 2006.285.08:31:06.11#ibcon#about to read 6, iclass 26, count 0 2006.285.08:31:06.11#ibcon#read 6, iclass 26, count 0 2006.285.08:31:06.11#ibcon#end of sib2, iclass 26, count 0 2006.285.08:31:06.11#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:31:06.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:31:06.11#ibcon#[27=USB\r\n] 2006.285.08:31:06.11#ibcon#*before write, iclass 26, count 0 2006.285.08:31:06.11#ibcon#enter sib2, iclass 26, count 0 2006.285.08:31:06.11#ibcon#flushed, iclass 26, count 0 2006.285.08:31:06.11#ibcon#about to write, iclass 26, count 0 2006.285.08:31:06.11#ibcon#wrote, iclass 26, count 0 2006.285.08:31:06.11#ibcon#about to read 3, iclass 26, count 0 2006.285.08:31:06.14#ibcon#read 3, iclass 26, count 0 2006.285.08:31:06.14#ibcon#about to read 4, iclass 26, count 0 2006.285.08:31:06.14#ibcon#read 4, iclass 26, count 0 2006.285.08:31:06.14#ibcon#about to read 5, iclass 26, count 0 2006.285.08:31:06.14#ibcon#read 5, iclass 26, count 0 2006.285.08:31:06.14#ibcon#about to read 6, iclass 26, count 0 2006.285.08:31:06.14#ibcon#read 6, iclass 26, count 0 2006.285.08:31:06.14#ibcon#end of sib2, iclass 26, count 0 2006.285.08:31:06.14#ibcon#*after write, iclass 26, count 0 2006.285.08:31:06.14#ibcon#*before return 0, iclass 26, count 0 2006.285.08:31:06.14#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:31:06.14#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:31:06.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:31:06.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:31:06.14$vck44/vblo=6,719.99 2006.285.08:31:06.14#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.08:31:06.14#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.08:31:06.14#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:06.14#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:31:06.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:31:06.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:31:06.14#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:31:06.14#ibcon#first serial, iclass 28, count 0 2006.285.08:31:06.14#ibcon#enter sib2, iclass 28, count 0 2006.285.08:31:06.14#ibcon#flushed, iclass 28, count 0 2006.285.08:31:06.14#ibcon#about to write, iclass 28, count 0 2006.285.08:31:06.14#ibcon#wrote, iclass 28, count 0 2006.285.08:31:06.14#ibcon#about to read 3, iclass 28, count 0 2006.285.08:31:06.16#ibcon#read 3, iclass 28, count 0 2006.285.08:31:06.16#ibcon#about to read 4, iclass 28, count 0 2006.285.08:31:06.16#ibcon#read 4, iclass 28, count 0 2006.285.08:31:06.16#ibcon#about to read 5, iclass 28, count 0 2006.285.08:31:06.16#ibcon#read 5, iclass 28, count 0 2006.285.08:31:06.16#ibcon#about to read 6, iclass 28, count 0 2006.285.08:31:06.16#ibcon#read 6, iclass 28, count 0 2006.285.08:31:06.16#ibcon#end of sib2, iclass 28, count 0 2006.285.08:31:06.16#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:31:06.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:31:06.16#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:31:06.16#ibcon#*before write, iclass 28, count 0 2006.285.08:31:06.16#ibcon#enter sib2, iclass 28, count 0 2006.285.08:31:06.16#ibcon#flushed, iclass 28, count 0 2006.285.08:31:06.16#ibcon#about to write, iclass 28, count 0 2006.285.08:31:06.16#ibcon#wrote, iclass 28, count 0 2006.285.08:31:06.16#ibcon#about to read 3, iclass 28, count 0 2006.285.08:31:06.20#ibcon#read 3, iclass 28, count 0 2006.285.08:31:06.20#ibcon#about to read 4, iclass 28, count 0 2006.285.08:31:06.20#ibcon#read 4, iclass 28, count 0 2006.285.08:31:06.20#ibcon#about to read 5, iclass 28, count 0 2006.285.08:31:06.20#ibcon#read 5, iclass 28, count 0 2006.285.08:31:06.20#ibcon#about to read 6, iclass 28, count 0 2006.285.08:31:06.20#ibcon#read 6, iclass 28, count 0 2006.285.08:31:06.20#ibcon#end of sib2, iclass 28, count 0 2006.285.08:31:06.20#ibcon#*after write, iclass 28, count 0 2006.285.08:31:06.20#ibcon#*before return 0, iclass 28, count 0 2006.285.08:31:06.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:31:06.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:31:06.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:31:06.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:31:06.20$vck44/vb=6,3 2006.285.08:31:06.20#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.08:31:06.20#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.08:31:06.20#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:06.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:31:06.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:31:06.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:31:06.26#ibcon#enter wrdev, iclass 30, count 2 2006.285.08:31:06.26#ibcon#first serial, iclass 30, count 2 2006.285.08:31:06.26#ibcon#enter sib2, iclass 30, count 2 2006.285.08:31:06.26#ibcon#flushed, iclass 30, count 2 2006.285.08:31:06.26#ibcon#about to write, iclass 30, count 2 2006.285.08:31:06.26#ibcon#wrote, iclass 30, count 2 2006.285.08:31:06.26#ibcon#about to read 3, iclass 30, count 2 2006.285.08:31:06.28#ibcon#read 3, iclass 30, count 2 2006.285.08:31:06.28#ibcon#about to read 4, iclass 30, count 2 2006.285.08:31:06.28#ibcon#read 4, iclass 30, count 2 2006.285.08:31:06.28#ibcon#about to read 5, iclass 30, count 2 2006.285.08:31:06.28#ibcon#read 5, iclass 30, count 2 2006.285.08:31:06.28#ibcon#about to read 6, iclass 30, count 2 2006.285.08:31:06.28#ibcon#read 6, iclass 30, count 2 2006.285.08:31:06.28#ibcon#end of sib2, iclass 30, count 2 2006.285.08:31:06.28#ibcon#*mode == 0, iclass 30, count 2 2006.285.08:31:06.28#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.08:31:06.28#ibcon#[27=AT06-03\r\n] 2006.285.08:31:06.28#ibcon#*before write, iclass 30, count 2 2006.285.08:31:06.28#ibcon#enter sib2, iclass 30, count 2 2006.285.08:31:06.28#ibcon#flushed, iclass 30, count 2 2006.285.08:31:06.28#ibcon#about to write, iclass 30, count 2 2006.285.08:31:06.28#ibcon#wrote, iclass 30, count 2 2006.285.08:31:06.28#ibcon#about to read 3, iclass 30, count 2 2006.285.08:31:06.31#ibcon#read 3, iclass 30, count 2 2006.285.08:31:06.31#ibcon#about to read 4, iclass 30, count 2 2006.285.08:31:06.31#ibcon#read 4, iclass 30, count 2 2006.285.08:31:06.31#ibcon#about to read 5, iclass 30, count 2 2006.285.08:31:06.31#ibcon#read 5, iclass 30, count 2 2006.285.08:31:06.31#ibcon#about to read 6, iclass 30, count 2 2006.285.08:31:06.31#ibcon#read 6, iclass 30, count 2 2006.285.08:31:06.31#ibcon#end of sib2, iclass 30, count 2 2006.285.08:31:06.31#ibcon#*after write, iclass 30, count 2 2006.285.08:31:06.31#ibcon#*before return 0, iclass 30, count 2 2006.285.08:31:06.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:31:06.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:31:06.31#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.08:31:06.31#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:06.31#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:31:06.43#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:31:06.43#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:31:06.43#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:31:06.43#ibcon#first serial, iclass 30, count 0 2006.285.08:31:06.43#ibcon#enter sib2, iclass 30, count 0 2006.285.08:31:06.43#ibcon#flushed, iclass 30, count 0 2006.285.08:31:06.43#ibcon#about to write, iclass 30, count 0 2006.285.08:31:06.43#ibcon#wrote, iclass 30, count 0 2006.285.08:31:06.43#ibcon#about to read 3, iclass 30, count 0 2006.285.08:31:06.45#ibcon#read 3, iclass 30, count 0 2006.285.08:31:06.45#ibcon#about to read 4, iclass 30, count 0 2006.285.08:31:06.45#ibcon#read 4, iclass 30, count 0 2006.285.08:31:06.45#ibcon#about to read 5, iclass 30, count 0 2006.285.08:31:06.45#ibcon#read 5, iclass 30, count 0 2006.285.08:31:06.45#ibcon#about to read 6, iclass 30, count 0 2006.285.08:31:06.45#ibcon#read 6, iclass 30, count 0 2006.285.08:31:06.45#ibcon#end of sib2, iclass 30, count 0 2006.285.08:31:06.45#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:31:06.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:31:06.45#ibcon#[27=USB\r\n] 2006.285.08:31:06.45#ibcon#*before write, iclass 30, count 0 2006.285.08:31:06.45#ibcon#enter sib2, iclass 30, count 0 2006.285.08:31:06.45#ibcon#flushed, iclass 30, count 0 2006.285.08:31:06.45#ibcon#about to write, iclass 30, count 0 2006.285.08:31:06.45#ibcon#wrote, iclass 30, count 0 2006.285.08:31:06.45#ibcon#about to read 3, iclass 30, count 0 2006.285.08:31:06.48#ibcon#read 3, iclass 30, count 0 2006.285.08:31:06.48#ibcon#about to read 4, iclass 30, count 0 2006.285.08:31:06.48#ibcon#read 4, iclass 30, count 0 2006.285.08:31:06.48#ibcon#about to read 5, iclass 30, count 0 2006.285.08:31:06.48#ibcon#read 5, iclass 30, count 0 2006.285.08:31:06.48#ibcon#about to read 6, iclass 30, count 0 2006.285.08:31:06.48#ibcon#read 6, iclass 30, count 0 2006.285.08:31:06.48#ibcon#end of sib2, iclass 30, count 0 2006.285.08:31:06.48#ibcon#*after write, iclass 30, count 0 2006.285.08:31:06.48#ibcon#*before return 0, iclass 30, count 0 2006.285.08:31:06.48#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:31:06.48#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:31:06.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:31:06.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:31:06.48$vck44/vblo=7,734.99 2006.285.08:31:06.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.08:31:06.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.08:31:06.48#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:06.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:31:06.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:31:06.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:31:06.48#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:31:06.48#ibcon#first serial, iclass 32, count 0 2006.285.08:31:06.48#ibcon#enter sib2, iclass 32, count 0 2006.285.08:31:06.48#ibcon#flushed, iclass 32, count 0 2006.285.08:31:06.48#ibcon#about to write, iclass 32, count 0 2006.285.08:31:06.48#ibcon#wrote, iclass 32, count 0 2006.285.08:31:06.48#ibcon#about to read 3, iclass 32, count 0 2006.285.08:31:06.50#ibcon#read 3, iclass 32, count 0 2006.285.08:31:06.50#ibcon#about to read 4, iclass 32, count 0 2006.285.08:31:06.50#ibcon#read 4, iclass 32, count 0 2006.285.08:31:06.50#ibcon#about to read 5, iclass 32, count 0 2006.285.08:31:06.50#ibcon#read 5, iclass 32, count 0 2006.285.08:31:06.50#ibcon#about to read 6, iclass 32, count 0 2006.285.08:31:06.50#ibcon#read 6, iclass 32, count 0 2006.285.08:31:06.50#ibcon#end of sib2, iclass 32, count 0 2006.285.08:31:06.50#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:31:06.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:31:06.50#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:31:06.50#ibcon#*before write, iclass 32, count 0 2006.285.08:31:06.50#ibcon#enter sib2, iclass 32, count 0 2006.285.08:31:06.50#ibcon#flushed, iclass 32, count 0 2006.285.08:31:06.50#ibcon#about to write, iclass 32, count 0 2006.285.08:31:06.50#ibcon#wrote, iclass 32, count 0 2006.285.08:31:06.50#ibcon#about to read 3, iclass 32, count 0 2006.285.08:31:06.54#ibcon#read 3, iclass 32, count 0 2006.285.08:31:06.54#ibcon#about to read 4, iclass 32, count 0 2006.285.08:31:06.54#ibcon#read 4, iclass 32, count 0 2006.285.08:31:06.54#ibcon#about to read 5, iclass 32, count 0 2006.285.08:31:06.54#ibcon#read 5, iclass 32, count 0 2006.285.08:31:06.54#ibcon#about to read 6, iclass 32, count 0 2006.285.08:31:06.54#ibcon#read 6, iclass 32, count 0 2006.285.08:31:06.54#ibcon#end of sib2, iclass 32, count 0 2006.285.08:31:06.54#ibcon#*after write, iclass 32, count 0 2006.285.08:31:06.54#ibcon#*before return 0, iclass 32, count 0 2006.285.08:31:06.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:31:06.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:31:06.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:31:06.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:31:06.54$vck44/vb=7,4 2006.285.08:31:06.54#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.08:31:06.54#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.08:31:06.54#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:06.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:31:06.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:31:06.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:31:06.60#ibcon#enter wrdev, iclass 34, count 2 2006.285.08:31:06.60#ibcon#first serial, iclass 34, count 2 2006.285.08:31:06.60#ibcon#enter sib2, iclass 34, count 2 2006.285.08:31:06.60#ibcon#flushed, iclass 34, count 2 2006.285.08:31:06.60#ibcon#about to write, iclass 34, count 2 2006.285.08:31:06.60#ibcon#wrote, iclass 34, count 2 2006.285.08:31:06.60#ibcon#about to read 3, iclass 34, count 2 2006.285.08:31:06.62#ibcon#read 3, iclass 34, count 2 2006.285.08:31:06.62#ibcon#about to read 4, iclass 34, count 2 2006.285.08:31:06.62#ibcon#read 4, iclass 34, count 2 2006.285.08:31:06.62#ibcon#about to read 5, iclass 34, count 2 2006.285.08:31:06.62#ibcon#read 5, iclass 34, count 2 2006.285.08:31:06.62#ibcon#about to read 6, iclass 34, count 2 2006.285.08:31:06.62#ibcon#read 6, iclass 34, count 2 2006.285.08:31:06.62#ibcon#end of sib2, iclass 34, count 2 2006.285.08:31:06.62#ibcon#*mode == 0, iclass 34, count 2 2006.285.08:31:06.62#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.08:31:06.62#ibcon#[27=AT07-04\r\n] 2006.285.08:31:06.62#ibcon#*before write, iclass 34, count 2 2006.285.08:31:06.62#ibcon#enter sib2, iclass 34, count 2 2006.285.08:31:06.62#ibcon#flushed, iclass 34, count 2 2006.285.08:31:06.62#ibcon#about to write, iclass 34, count 2 2006.285.08:31:06.62#ibcon#wrote, iclass 34, count 2 2006.285.08:31:06.62#ibcon#about to read 3, iclass 34, count 2 2006.285.08:31:06.65#ibcon#read 3, iclass 34, count 2 2006.285.08:31:06.65#ibcon#about to read 4, iclass 34, count 2 2006.285.08:31:06.65#ibcon#read 4, iclass 34, count 2 2006.285.08:31:06.65#ibcon#about to read 5, iclass 34, count 2 2006.285.08:31:06.65#ibcon#read 5, iclass 34, count 2 2006.285.08:31:06.65#ibcon#about to read 6, iclass 34, count 2 2006.285.08:31:06.65#ibcon#read 6, iclass 34, count 2 2006.285.08:31:06.65#ibcon#end of sib2, iclass 34, count 2 2006.285.08:31:06.65#ibcon#*after write, iclass 34, count 2 2006.285.08:31:06.65#ibcon#*before return 0, iclass 34, count 2 2006.285.08:31:06.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:31:06.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:31:06.65#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.08:31:06.65#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:06.65#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:31:06.77#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:31:06.77#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:31:06.77#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:31:06.77#ibcon#first serial, iclass 34, count 0 2006.285.08:31:06.77#ibcon#enter sib2, iclass 34, count 0 2006.285.08:31:06.77#ibcon#flushed, iclass 34, count 0 2006.285.08:31:06.77#ibcon#about to write, iclass 34, count 0 2006.285.08:31:06.77#ibcon#wrote, iclass 34, count 0 2006.285.08:31:06.77#ibcon#about to read 3, iclass 34, count 0 2006.285.08:31:06.79#ibcon#read 3, iclass 34, count 0 2006.285.08:31:06.79#ibcon#about to read 4, iclass 34, count 0 2006.285.08:31:06.79#ibcon#read 4, iclass 34, count 0 2006.285.08:31:06.79#ibcon#about to read 5, iclass 34, count 0 2006.285.08:31:06.79#ibcon#read 5, iclass 34, count 0 2006.285.08:31:06.79#ibcon#about to read 6, iclass 34, count 0 2006.285.08:31:06.79#ibcon#read 6, iclass 34, count 0 2006.285.08:31:06.79#ibcon#end of sib2, iclass 34, count 0 2006.285.08:31:06.79#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:31:06.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:31:06.79#ibcon#[27=USB\r\n] 2006.285.08:31:06.79#ibcon#*before write, iclass 34, count 0 2006.285.08:31:06.79#ibcon#enter sib2, iclass 34, count 0 2006.285.08:31:06.79#ibcon#flushed, iclass 34, count 0 2006.285.08:31:06.79#ibcon#about to write, iclass 34, count 0 2006.285.08:31:06.79#ibcon#wrote, iclass 34, count 0 2006.285.08:31:06.79#ibcon#about to read 3, iclass 34, count 0 2006.285.08:31:06.82#ibcon#read 3, iclass 34, count 0 2006.285.08:31:06.82#ibcon#about to read 4, iclass 34, count 0 2006.285.08:31:06.82#ibcon#read 4, iclass 34, count 0 2006.285.08:31:06.82#ibcon#about to read 5, iclass 34, count 0 2006.285.08:31:06.82#ibcon#read 5, iclass 34, count 0 2006.285.08:31:06.82#ibcon#about to read 6, iclass 34, count 0 2006.285.08:31:06.82#ibcon#read 6, iclass 34, count 0 2006.285.08:31:06.82#ibcon#end of sib2, iclass 34, count 0 2006.285.08:31:06.82#ibcon#*after write, iclass 34, count 0 2006.285.08:31:06.82#ibcon#*before return 0, iclass 34, count 0 2006.285.08:31:06.82#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:31:06.82#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:31:06.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:31:06.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:31:06.82$vck44/vblo=8,744.99 2006.285.08:31:06.82#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.08:31:06.82#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.08:31:06.82#ibcon#ireg 17 cls_cnt 0 2006.285.08:31:06.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:31:06.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:31:06.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:31:06.82#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:31:06.82#ibcon#first serial, iclass 36, count 0 2006.285.08:31:06.82#ibcon#enter sib2, iclass 36, count 0 2006.285.08:31:06.82#ibcon#flushed, iclass 36, count 0 2006.285.08:31:06.82#ibcon#about to write, iclass 36, count 0 2006.285.08:31:06.82#ibcon#wrote, iclass 36, count 0 2006.285.08:31:06.82#ibcon#about to read 3, iclass 36, count 0 2006.285.08:31:06.84#ibcon#read 3, iclass 36, count 0 2006.285.08:31:06.84#ibcon#about to read 4, iclass 36, count 0 2006.285.08:31:06.84#ibcon#read 4, iclass 36, count 0 2006.285.08:31:06.84#ibcon#about to read 5, iclass 36, count 0 2006.285.08:31:06.84#ibcon#read 5, iclass 36, count 0 2006.285.08:31:06.84#ibcon#about to read 6, iclass 36, count 0 2006.285.08:31:06.84#ibcon#read 6, iclass 36, count 0 2006.285.08:31:06.84#ibcon#end of sib2, iclass 36, count 0 2006.285.08:31:06.84#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:31:06.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:31:06.84#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:31:06.84#ibcon#*before write, iclass 36, count 0 2006.285.08:31:06.84#ibcon#enter sib2, iclass 36, count 0 2006.285.08:31:06.84#ibcon#flushed, iclass 36, count 0 2006.285.08:31:06.84#ibcon#about to write, iclass 36, count 0 2006.285.08:31:06.84#ibcon#wrote, iclass 36, count 0 2006.285.08:31:06.84#ibcon#about to read 3, iclass 36, count 0 2006.285.08:31:06.88#ibcon#read 3, iclass 36, count 0 2006.285.08:31:06.88#ibcon#about to read 4, iclass 36, count 0 2006.285.08:31:06.88#ibcon#read 4, iclass 36, count 0 2006.285.08:31:06.88#ibcon#about to read 5, iclass 36, count 0 2006.285.08:31:06.88#ibcon#read 5, iclass 36, count 0 2006.285.08:31:06.88#ibcon#about to read 6, iclass 36, count 0 2006.285.08:31:06.88#ibcon#read 6, iclass 36, count 0 2006.285.08:31:06.88#ibcon#end of sib2, iclass 36, count 0 2006.285.08:31:06.88#ibcon#*after write, iclass 36, count 0 2006.285.08:31:06.88#ibcon#*before return 0, iclass 36, count 0 2006.285.08:31:06.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:31:06.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:31:06.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:31:06.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:31:06.88$vck44/vb=8,4 2006.285.08:31:06.88#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.08:31:06.88#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.08:31:06.88#ibcon#ireg 11 cls_cnt 2 2006.285.08:31:06.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:31:06.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:31:06.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:31:06.94#ibcon#enter wrdev, iclass 38, count 2 2006.285.08:31:06.94#ibcon#first serial, iclass 38, count 2 2006.285.08:31:06.94#ibcon#enter sib2, iclass 38, count 2 2006.285.08:31:06.94#ibcon#flushed, iclass 38, count 2 2006.285.08:31:06.94#ibcon#about to write, iclass 38, count 2 2006.285.08:31:06.94#ibcon#wrote, iclass 38, count 2 2006.285.08:31:06.94#ibcon#about to read 3, iclass 38, count 2 2006.285.08:31:06.96#ibcon#read 3, iclass 38, count 2 2006.285.08:31:06.96#ibcon#about to read 4, iclass 38, count 2 2006.285.08:31:06.96#ibcon#read 4, iclass 38, count 2 2006.285.08:31:06.96#ibcon#about to read 5, iclass 38, count 2 2006.285.08:31:06.96#ibcon#read 5, iclass 38, count 2 2006.285.08:31:06.96#ibcon#about to read 6, iclass 38, count 2 2006.285.08:31:06.96#ibcon#read 6, iclass 38, count 2 2006.285.08:31:06.96#ibcon#end of sib2, iclass 38, count 2 2006.285.08:31:06.96#ibcon#*mode == 0, iclass 38, count 2 2006.285.08:31:06.96#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.08:31:06.96#ibcon#[27=AT08-04\r\n] 2006.285.08:31:06.96#ibcon#*before write, iclass 38, count 2 2006.285.08:31:06.96#ibcon#enter sib2, iclass 38, count 2 2006.285.08:31:06.96#ibcon#flushed, iclass 38, count 2 2006.285.08:31:06.96#ibcon#about to write, iclass 38, count 2 2006.285.08:31:06.96#ibcon#wrote, iclass 38, count 2 2006.285.08:31:06.96#ibcon#about to read 3, iclass 38, count 2 2006.285.08:31:06.99#ibcon#read 3, iclass 38, count 2 2006.285.08:31:06.99#ibcon#about to read 4, iclass 38, count 2 2006.285.08:31:06.99#ibcon#read 4, iclass 38, count 2 2006.285.08:31:06.99#ibcon#about to read 5, iclass 38, count 2 2006.285.08:31:06.99#ibcon#read 5, iclass 38, count 2 2006.285.08:31:06.99#ibcon#about to read 6, iclass 38, count 2 2006.285.08:31:06.99#ibcon#read 6, iclass 38, count 2 2006.285.08:31:06.99#ibcon#end of sib2, iclass 38, count 2 2006.285.08:31:06.99#ibcon#*after write, iclass 38, count 2 2006.285.08:31:06.99#ibcon#*before return 0, iclass 38, count 2 2006.285.08:31:06.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:31:06.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:31:06.99#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.08:31:06.99#ibcon#ireg 7 cls_cnt 0 2006.285.08:31:06.99#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:31:07.11#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:31:07.11#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:31:07.11#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:31:07.11#ibcon#first serial, iclass 38, count 0 2006.285.08:31:07.11#ibcon#enter sib2, iclass 38, count 0 2006.285.08:31:07.11#ibcon#flushed, iclass 38, count 0 2006.285.08:31:07.11#ibcon#about to write, iclass 38, count 0 2006.285.08:31:07.11#ibcon#wrote, iclass 38, count 0 2006.285.08:31:07.11#ibcon#about to read 3, iclass 38, count 0 2006.285.08:31:07.13#ibcon#read 3, iclass 38, count 0 2006.285.08:31:07.13#ibcon#about to read 4, iclass 38, count 0 2006.285.08:31:07.13#ibcon#read 4, iclass 38, count 0 2006.285.08:31:07.13#ibcon#about to read 5, iclass 38, count 0 2006.285.08:31:07.13#ibcon#read 5, iclass 38, count 0 2006.285.08:31:07.13#ibcon#about to read 6, iclass 38, count 0 2006.285.08:31:07.13#ibcon#read 6, iclass 38, count 0 2006.285.08:31:07.13#ibcon#end of sib2, iclass 38, count 0 2006.285.08:31:07.13#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:31:07.13#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:31:07.13#ibcon#[27=USB\r\n] 2006.285.08:31:07.13#ibcon#*before write, iclass 38, count 0 2006.285.08:31:07.13#ibcon#enter sib2, iclass 38, count 0 2006.285.08:31:07.13#ibcon#flushed, iclass 38, count 0 2006.285.08:31:07.13#ibcon#about to write, iclass 38, count 0 2006.285.08:31:07.13#ibcon#wrote, iclass 38, count 0 2006.285.08:31:07.13#ibcon#about to read 3, iclass 38, count 0 2006.285.08:31:07.16#ibcon#read 3, iclass 38, count 0 2006.285.08:31:07.16#ibcon#about to read 4, iclass 38, count 0 2006.285.08:31:07.16#ibcon#read 4, iclass 38, count 0 2006.285.08:31:07.16#ibcon#about to read 5, iclass 38, count 0 2006.285.08:31:07.16#ibcon#read 5, iclass 38, count 0 2006.285.08:31:07.16#ibcon#about to read 6, iclass 38, count 0 2006.285.08:31:07.16#ibcon#read 6, iclass 38, count 0 2006.285.08:31:07.16#ibcon#end of sib2, iclass 38, count 0 2006.285.08:31:07.16#ibcon#*after write, iclass 38, count 0 2006.285.08:31:07.16#ibcon#*before return 0, iclass 38, count 0 2006.285.08:31:07.16#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:31:07.16#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:31:07.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:31:07.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:31:07.16$vck44/vabw=wide 2006.285.08:31:07.16#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.08:31:07.16#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.08:31:07.16#ibcon#ireg 8 cls_cnt 0 2006.285.08:31:07.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:31:07.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:31:07.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:31:07.16#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:31:07.16#ibcon#first serial, iclass 40, count 0 2006.285.08:31:07.16#ibcon#enter sib2, iclass 40, count 0 2006.285.08:31:07.16#ibcon#flushed, iclass 40, count 0 2006.285.08:31:07.16#ibcon#about to write, iclass 40, count 0 2006.285.08:31:07.16#ibcon#wrote, iclass 40, count 0 2006.285.08:31:07.16#ibcon#about to read 3, iclass 40, count 0 2006.285.08:31:07.18#ibcon#read 3, iclass 40, count 0 2006.285.08:31:07.18#ibcon#about to read 4, iclass 40, count 0 2006.285.08:31:07.18#ibcon#read 4, iclass 40, count 0 2006.285.08:31:07.18#ibcon#about to read 5, iclass 40, count 0 2006.285.08:31:07.18#ibcon#read 5, iclass 40, count 0 2006.285.08:31:07.18#ibcon#about to read 6, iclass 40, count 0 2006.285.08:31:07.18#ibcon#read 6, iclass 40, count 0 2006.285.08:31:07.18#ibcon#end of sib2, iclass 40, count 0 2006.285.08:31:07.18#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:31:07.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:31:07.18#ibcon#[25=BW32\r\n] 2006.285.08:31:07.18#ibcon#*before write, iclass 40, count 0 2006.285.08:31:07.18#ibcon#enter sib2, iclass 40, count 0 2006.285.08:31:07.18#ibcon#flushed, iclass 40, count 0 2006.285.08:31:07.18#ibcon#about to write, iclass 40, count 0 2006.285.08:31:07.18#ibcon#wrote, iclass 40, count 0 2006.285.08:31:07.18#ibcon#about to read 3, iclass 40, count 0 2006.285.08:31:07.21#ibcon#read 3, iclass 40, count 0 2006.285.08:31:07.21#ibcon#about to read 4, iclass 40, count 0 2006.285.08:31:07.21#ibcon#read 4, iclass 40, count 0 2006.285.08:31:07.21#ibcon#about to read 5, iclass 40, count 0 2006.285.08:31:07.21#ibcon#read 5, iclass 40, count 0 2006.285.08:31:07.21#ibcon#about to read 6, iclass 40, count 0 2006.285.08:31:07.21#ibcon#read 6, iclass 40, count 0 2006.285.08:31:07.21#ibcon#end of sib2, iclass 40, count 0 2006.285.08:31:07.21#ibcon#*after write, iclass 40, count 0 2006.285.08:31:07.21#ibcon#*before return 0, iclass 40, count 0 2006.285.08:31:07.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:31:07.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:31:07.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:31:07.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:31:07.21$vck44/vbbw=wide 2006.285.08:31:07.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.08:31:07.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.08:31:07.21#ibcon#ireg 8 cls_cnt 0 2006.285.08:31:07.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:31:07.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:31:07.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:31:07.28#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:31:07.28#ibcon#first serial, iclass 4, count 0 2006.285.08:31:07.28#ibcon#enter sib2, iclass 4, count 0 2006.285.08:31:07.28#ibcon#flushed, iclass 4, count 0 2006.285.08:31:07.28#ibcon#about to write, iclass 4, count 0 2006.285.08:31:07.28#ibcon#wrote, iclass 4, count 0 2006.285.08:31:07.28#ibcon#about to read 3, iclass 4, count 0 2006.285.08:31:07.30#ibcon#read 3, iclass 4, count 0 2006.285.08:31:07.30#ibcon#about to read 4, iclass 4, count 0 2006.285.08:31:07.30#ibcon#read 4, iclass 4, count 0 2006.285.08:31:07.30#ibcon#about to read 5, iclass 4, count 0 2006.285.08:31:07.30#ibcon#read 5, iclass 4, count 0 2006.285.08:31:07.30#ibcon#about to read 6, iclass 4, count 0 2006.285.08:31:07.30#ibcon#read 6, iclass 4, count 0 2006.285.08:31:07.30#ibcon#end of sib2, iclass 4, count 0 2006.285.08:31:07.30#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:31:07.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:31:07.30#ibcon#[27=BW32\r\n] 2006.285.08:31:07.30#ibcon#*before write, iclass 4, count 0 2006.285.08:31:07.30#ibcon#enter sib2, iclass 4, count 0 2006.285.08:31:07.30#ibcon#flushed, iclass 4, count 0 2006.285.08:31:07.30#ibcon#about to write, iclass 4, count 0 2006.285.08:31:07.30#ibcon#wrote, iclass 4, count 0 2006.285.08:31:07.30#ibcon#about to read 3, iclass 4, count 0 2006.285.08:31:07.33#ibcon#read 3, iclass 4, count 0 2006.285.08:31:07.33#ibcon#about to read 4, iclass 4, count 0 2006.285.08:31:07.33#ibcon#read 4, iclass 4, count 0 2006.285.08:31:07.33#ibcon#about to read 5, iclass 4, count 0 2006.285.08:31:07.33#ibcon#read 5, iclass 4, count 0 2006.285.08:31:07.33#ibcon#about to read 6, iclass 4, count 0 2006.285.08:31:07.33#ibcon#read 6, iclass 4, count 0 2006.285.08:31:07.33#ibcon#end of sib2, iclass 4, count 0 2006.285.08:31:07.33#ibcon#*after write, iclass 4, count 0 2006.285.08:31:07.33#ibcon#*before return 0, iclass 4, count 0 2006.285.08:31:07.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:31:07.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:31:07.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:31:07.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:31:07.33$setupk4/ifdk4 2006.285.08:31:07.33$ifdk4/lo= 2006.285.08:31:07.33$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:31:07.33$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:31:07.33$ifdk4/patch= 2006.285.08:31:07.33$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:31:07.33$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:31:07.33$setupk4/!*+20s 2006.285.08:31:15.83#abcon#<5=/04 1.6 2.8 22.20 811014.8\r\n> 2006.285.08:31:15.85#abcon#{5=INTERFACE CLEAR} 2006.285.08:31:15.91#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:31:21.84$setupk4/"tpicd 2006.285.08:31:21.84$setupk4/echo=off 2006.285.08:31:21.84$setupk4/xlog=off 2006.285.08:31:21.84:!2006.285.08:32:40 2006.285.08:31:32.13#trakl#Source acquired 2006.285.08:31:33.13#flagr#flagr/antenna,acquired 2006.285.08:32:40.00:preob 2006.285.08:32:40.14/onsource/TRACKING 2006.285.08:32:40.14:!2006.285.08:32:50 2006.285.08:32:50.00:"tape 2006.285.08:32:50.00:"st=record 2006.285.08:32:50.00:data_valid=on 2006.285.08:32:50.00:midob 2006.285.08:32:51.14/onsource/TRACKING 2006.285.08:32:51.14/wx/22.17,1014.8,81 2006.285.08:32:51.35/cable/+6.4767E-03 2006.285.08:32:52.44/va/01,07,usb,yes,32,35 2006.285.08:32:52.44/va/02,06,usb,yes,32,33 2006.285.08:32:52.44/va/03,07,usb,yes,32,34 2006.285.08:32:52.44/va/04,06,usb,yes,33,35 2006.285.08:32:52.44/va/05,03,usb,yes,33,33 2006.285.08:32:52.44/va/06,04,usb,yes,30,29 2006.285.08:32:52.44/va/07,04,usb,yes,30,31 2006.285.08:32:52.44/va/08,03,usb,yes,31,38 2006.285.08:32:52.67/valo/01,524.99,yes,locked 2006.285.08:32:52.67/valo/02,534.99,yes,locked 2006.285.08:32:52.67/valo/03,564.99,yes,locked 2006.285.08:32:52.67/valo/04,624.99,yes,locked 2006.285.08:32:52.67/valo/05,734.99,yes,locked 2006.285.08:32:52.67/valo/06,814.99,yes,locked 2006.285.08:32:52.67/valo/07,864.99,yes,locked 2006.285.08:32:52.67/valo/08,884.99,yes,locked 2006.285.08:32:53.76/vb/01,04,usb,yes,31,29 2006.285.08:32:53.76/vb/02,05,usb,yes,29,29 2006.285.08:32:53.76/vb/03,04,usb,yes,30,33 2006.285.08:32:53.76/vb/04,05,usb,yes,30,30 2006.285.08:32:53.76/vb/05,04,usb,yes,27,29 2006.285.08:32:53.76/vb/06,03,usb,yes,39,34 2006.285.08:32:53.76/vb/07,04,usb,yes,31,31 2006.285.08:32:53.76/vb/08,04,usb,yes,28,32 2006.285.08:32:53.99/vblo/01,629.99,yes,locked 2006.285.08:32:53.99/vblo/02,634.99,yes,locked 2006.285.08:32:53.99/vblo/03,649.99,yes,locked 2006.285.08:32:53.99/vblo/04,679.99,yes,locked 2006.285.08:32:53.99/vblo/05,709.99,yes,locked 2006.285.08:32:53.99/vblo/06,719.99,yes,locked 2006.285.08:32:53.99/vblo/07,734.99,yes,locked 2006.285.08:32:53.99/vblo/08,744.99,yes,locked 2006.285.08:32:54.14/vabw/8 2006.285.08:32:54.29/vbbw/8 2006.285.08:32:54.38/xfe/off,on,12.2 2006.285.08:32:54.76/ifatt/23,28,28,28 2006.285.08:32:55.07/fmout-gps/S +2.74E-07 2006.285.08:32:55.09:!2006.285.08:34:50 2006.285.08:34:50.00:data_valid=off 2006.285.08:34:50.00:"et 2006.285.08:34:50.00:!+3s 2006.285.08:34:53.01:"tape 2006.285.08:34:53.01:postob 2006.285.08:34:53.11/cable/+6.4763E-03 2006.285.08:34:53.11/wx/22.13,1014.8,82 2006.285.08:34:54.07/fmout-gps/S +2.72E-07 2006.285.08:34:54.07:scan_name=285-0835,jd0610,520 2006.285.08:34:54.07:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.285.08:34:54.14#flagr#flagr/antenna,new-source 2006.285.08:34:55.14:checkk5 2006.285.08:34:55.49/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:34:55.91/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:34:56.58/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:34:56.97/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:34:57.62/chk_obsdata//k5ts1/T2850832??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.08:34:58.02/chk_obsdata//k5ts2/T2850832??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.08:34:58.43/chk_obsdata//k5ts3/T2850832??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.08:34:58.83/chk_obsdata//k5ts4/T2850832??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.08:34:59.67/k5log//k5ts1_log_newline 2006.285.08:35:00.90/k5log//k5ts2_log_newline 2006.285.08:35:01.74/k5log//k5ts3_log_newline 2006.285.08:35:02.57/k5log//k5ts4_log_newline 2006.285.08:35:02.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:35:02.59:setupk4=1 2006.285.08:35:02.59$setupk4/echo=on 2006.285.08:35:02.59$setupk4/pcalon 2006.285.08:35:02.59$pcalon/"no phase cal control is implemented here 2006.285.08:35:02.59$setupk4/"tpicd=stop 2006.285.08:35:02.59$setupk4/"rec=synch_on 2006.285.08:35:02.59$setupk4/"rec_mode=128 2006.285.08:35:02.59$setupk4/!* 2006.285.08:35:02.59$setupk4/recpk4 2006.285.08:35:02.59$recpk4/recpatch= 2006.285.08:35:02.59$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:35:02.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:35:02.59$setupk4/vck44 2006.285.08:35:02.59$vck44/valo=1,524.99 2006.285.08:35:02.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.08:35:02.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.08:35:02.60#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:02.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:35:02.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:35:02.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:35:02.60#ibcon#enter wrdev, iclass 31, count 0 2006.285.08:35:02.60#ibcon#first serial, iclass 31, count 0 2006.285.08:35:02.60#ibcon#enter sib2, iclass 31, count 0 2006.285.08:35:02.60#ibcon#flushed, iclass 31, count 0 2006.285.08:35:02.60#ibcon#about to write, iclass 31, count 0 2006.285.08:35:02.60#ibcon#wrote, iclass 31, count 0 2006.285.08:35:02.60#ibcon#about to read 3, iclass 31, count 0 2006.285.08:35:02.61#ibcon#read 3, iclass 31, count 0 2006.285.08:35:02.61#ibcon#about to read 4, iclass 31, count 0 2006.285.08:35:02.61#ibcon#read 4, iclass 31, count 0 2006.285.08:35:02.61#ibcon#about to read 5, iclass 31, count 0 2006.285.08:35:02.61#ibcon#read 5, iclass 31, count 0 2006.285.08:35:02.61#ibcon#about to read 6, iclass 31, count 0 2006.285.08:35:02.61#ibcon#read 6, iclass 31, count 0 2006.285.08:35:02.61#ibcon#end of sib2, iclass 31, count 0 2006.285.08:35:02.61#ibcon#*mode == 0, iclass 31, count 0 2006.285.08:35:02.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.08:35:02.61#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:35:02.61#ibcon#*before write, iclass 31, count 0 2006.285.08:35:02.61#ibcon#enter sib2, iclass 31, count 0 2006.285.08:35:02.61#ibcon#flushed, iclass 31, count 0 2006.285.08:35:02.61#ibcon#about to write, iclass 31, count 0 2006.285.08:35:02.61#ibcon#wrote, iclass 31, count 0 2006.285.08:35:02.61#ibcon#about to read 3, iclass 31, count 0 2006.285.08:35:02.66#ibcon#read 3, iclass 31, count 0 2006.285.08:35:02.66#ibcon#about to read 4, iclass 31, count 0 2006.285.08:35:02.66#ibcon#read 4, iclass 31, count 0 2006.285.08:35:02.66#ibcon#about to read 5, iclass 31, count 0 2006.285.08:35:02.66#ibcon#read 5, iclass 31, count 0 2006.285.08:35:02.66#ibcon#about to read 6, iclass 31, count 0 2006.285.08:35:02.66#ibcon#read 6, iclass 31, count 0 2006.285.08:35:02.66#ibcon#end of sib2, iclass 31, count 0 2006.285.08:35:02.66#ibcon#*after write, iclass 31, count 0 2006.285.08:35:02.66#ibcon#*before return 0, iclass 31, count 0 2006.285.08:35:02.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:35:02.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:35:02.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.08:35:02.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.08:35:02.66$vck44/va=1,7 2006.285.08:35:02.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.08:35:02.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.08:35:02.66#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:02.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:35:02.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:35:02.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:35:02.66#ibcon#enter wrdev, iclass 33, count 2 2006.285.08:35:02.66#ibcon#first serial, iclass 33, count 2 2006.285.08:35:02.66#ibcon#enter sib2, iclass 33, count 2 2006.285.08:35:02.66#ibcon#flushed, iclass 33, count 2 2006.285.08:35:02.66#ibcon#about to write, iclass 33, count 2 2006.285.08:35:02.66#ibcon#wrote, iclass 33, count 2 2006.285.08:35:02.66#ibcon#about to read 3, iclass 33, count 2 2006.285.08:35:02.68#ibcon#read 3, iclass 33, count 2 2006.285.08:35:02.68#ibcon#about to read 4, iclass 33, count 2 2006.285.08:35:02.68#ibcon#read 4, iclass 33, count 2 2006.285.08:35:02.68#ibcon#about to read 5, iclass 33, count 2 2006.285.08:35:02.68#ibcon#read 5, iclass 33, count 2 2006.285.08:35:02.68#ibcon#about to read 6, iclass 33, count 2 2006.285.08:35:02.68#ibcon#read 6, iclass 33, count 2 2006.285.08:35:02.68#ibcon#end of sib2, iclass 33, count 2 2006.285.08:35:02.68#ibcon#*mode == 0, iclass 33, count 2 2006.285.08:35:02.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.08:35:02.68#ibcon#[25=AT01-07\r\n] 2006.285.08:35:02.68#ibcon#*before write, iclass 33, count 2 2006.285.08:35:02.68#ibcon#enter sib2, iclass 33, count 2 2006.285.08:35:02.68#ibcon#flushed, iclass 33, count 2 2006.285.08:35:02.68#ibcon#about to write, iclass 33, count 2 2006.285.08:35:02.68#ibcon#wrote, iclass 33, count 2 2006.285.08:35:02.68#ibcon#about to read 3, iclass 33, count 2 2006.285.08:35:02.71#ibcon#read 3, iclass 33, count 2 2006.285.08:35:02.71#ibcon#about to read 4, iclass 33, count 2 2006.285.08:35:02.71#ibcon#read 4, iclass 33, count 2 2006.285.08:35:02.71#ibcon#about to read 5, iclass 33, count 2 2006.285.08:35:02.71#ibcon#read 5, iclass 33, count 2 2006.285.08:35:02.71#ibcon#about to read 6, iclass 33, count 2 2006.285.08:35:02.71#ibcon#read 6, iclass 33, count 2 2006.285.08:35:02.71#ibcon#end of sib2, iclass 33, count 2 2006.285.08:35:02.71#ibcon#*after write, iclass 33, count 2 2006.285.08:35:02.71#ibcon#*before return 0, iclass 33, count 2 2006.285.08:35:02.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:35:02.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:35:02.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.08:35:02.71#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:02.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:35:02.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:35:02.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:35:02.83#ibcon#enter wrdev, iclass 33, count 0 2006.285.08:35:02.83#ibcon#first serial, iclass 33, count 0 2006.285.08:35:02.83#ibcon#enter sib2, iclass 33, count 0 2006.285.08:35:02.83#ibcon#flushed, iclass 33, count 0 2006.285.08:35:02.83#ibcon#about to write, iclass 33, count 0 2006.285.08:35:02.83#ibcon#wrote, iclass 33, count 0 2006.285.08:35:02.83#ibcon#about to read 3, iclass 33, count 0 2006.285.08:35:02.85#ibcon#read 3, iclass 33, count 0 2006.285.08:35:02.85#ibcon#about to read 4, iclass 33, count 0 2006.285.08:35:02.85#ibcon#read 4, iclass 33, count 0 2006.285.08:35:02.85#ibcon#about to read 5, iclass 33, count 0 2006.285.08:35:02.85#ibcon#read 5, iclass 33, count 0 2006.285.08:35:02.85#ibcon#about to read 6, iclass 33, count 0 2006.285.08:35:02.85#ibcon#read 6, iclass 33, count 0 2006.285.08:35:02.85#ibcon#end of sib2, iclass 33, count 0 2006.285.08:35:02.85#ibcon#*mode == 0, iclass 33, count 0 2006.285.08:35:02.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.08:35:02.85#ibcon#[25=USB\r\n] 2006.285.08:35:02.85#ibcon#*before write, iclass 33, count 0 2006.285.08:35:02.85#ibcon#enter sib2, iclass 33, count 0 2006.285.08:35:02.85#ibcon#flushed, iclass 33, count 0 2006.285.08:35:02.85#ibcon#about to write, iclass 33, count 0 2006.285.08:35:02.85#ibcon#wrote, iclass 33, count 0 2006.285.08:35:02.85#ibcon#about to read 3, iclass 33, count 0 2006.285.08:35:02.88#ibcon#read 3, iclass 33, count 0 2006.285.08:35:02.88#ibcon#about to read 4, iclass 33, count 0 2006.285.08:35:02.88#ibcon#read 4, iclass 33, count 0 2006.285.08:35:02.88#ibcon#about to read 5, iclass 33, count 0 2006.285.08:35:02.88#ibcon#read 5, iclass 33, count 0 2006.285.08:35:02.88#ibcon#about to read 6, iclass 33, count 0 2006.285.08:35:02.88#ibcon#read 6, iclass 33, count 0 2006.285.08:35:02.88#ibcon#end of sib2, iclass 33, count 0 2006.285.08:35:02.88#ibcon#*after write, iclass 33, count 0 2006.285.08:35:02.88#ibcon#*before return 0, iclass 33, count 0 2006.285.08:35:02.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:35:02.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:35:02.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.08:35:02.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.08:35:02.88$vck44/valo=2,534.99 2006.285.08:35:02.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.08:35:02.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.08:35:02.88#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:02.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:35:02.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:35:02.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:35:02.88#ibcon#enter wrdev, iclass 35, count 0 2006.285.08:35:02.88#ibcon#first serial, iclass 35, count 0 2006.285.08:35:02.88#ibcon#enter sib2, iclass 35, count 0 2006.285.08:35:02.88#ibcon#flushed, iclass 35, count 0 2006.285.08:35:02.88#ibcon#about to write, iclass 35, count 0 2006.285.08:35:02.88#ibcon#wrote, iclass 35, count 0 2006.285.08:35:02.88#ibcon#about to read 3, iclass 35, count 0 2006.285.08:35:02.90#ibcon#read 3, iclass 35, count 0 2006.285.08:35:02.90#ibcon#about to read 4, iclass 35, count 0 2006.285.08:35:02.90#ibcon#read 4, iclass 35, count 0 2006.285.08:35:02.90#ibcon#about to read 5, iclass 35, count 0 2006.285.08:35:02.90#ibcon#read 5, iclass 35, count 0 2006.285.08:35:02.90#ibcon#about to read 6, iclass 35, count 0 2006.285.08:35:02.90#ibcon#read 6, iclass 35, count 0 2006.285.08:35:02.90#ibcon#end of sib2, iclass 35, count 0 2006.285.08:35:02.90#ibcon#*mode == 0, iclass 35, count 0 2006.285.08:35:02.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.08:35:02.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:35:02.90#ibcon#*before write, iclass 35, count 0 2006.285.08:35:02.90#ibcon#enter sib2, iclass 35, count 0 2006.285.08:35:02.90#ibcon#flushed, iclass 35, count 0 2006.285.08:35:02.90#ibcon#about to write, iclass 35, count 0 2006.285.08:35:02.90#ibcon#wrote, iclass 35, count 0 2006.285.08:35:02.90#ibcon#about to read 3, iclass 35, count 0 2006.285.08:35:02.94#ibcon#read 3, iclass 35, count 0 2006.285.08:35:02.94#ibcon#about to read 4, iclass 35, count 0 2006.285.08:35:02.94#ibcon#read 4, iclass 35, count 0 2006.285.08:35:02.94#ibcon#about to read 5, iclass 35, count 0 2006.285.08:35:02.94#ibcon#read 5, iclass 35, count 0 2006.285.08:35:02.94#ibcon#about to read 6, iclass 35, count 0 2006.285.08:35:02.94#ibcon#read 6, iclass 35, count 0 2006.285.08:35:02.94#ibcon#end of sib2, iclass 35, count 0 2006.285.08:35:02.94#ibcon#*after write, iclass 35, count 0 2006.285.08:35:02.94#ibcon#*before return 0, iclass 35, count 0 2006.285.08:35:02.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:35:02.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:35:02.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.08:35:02.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.08:35:02.94$vck44/va=2,6 2006.285.08:35:02.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.08:35:02.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.08:35:02.94#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:02.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:35:03.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:35:03.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:35:03.00#ibcon#enter wrdev, iclass 37, count 2 2006.285.08:35:03.00#ibcon#first serial, iclass 37, count 2 2006.285.08:35:03.00#ibcon#enter sib2, iclass 37, count 2 2006.285.08:35:03.00#ibcon#flushed, iclass 37, count 2 2006.285.08:35:03.00#ibcon#about to write, iclass 37, count 2 2006.285.08:35:03.00#ibcon#wrote, iclass 37, count 2 2006.285.08:35:03.00#ibcon#about to read 3, iclass 37, count 2 2006.285.08:35:03.02#ibcon#read 3, iclass 37, count 2 2006.285.08:35:03.02#ibcon#about to read 4, iclass 37, count 2 2006.285.08:35:03.02#ibcon#read 4, iclass 37, count 2 2006.285.08:35:03.02#ibcon#about to read 5, iclass 37, count 2 2006.285.08:35:03.02#ibcon#read 5, iclass 37, count 2 2006.285.08:35:03.02#ibcon#about to read 6, iclass 37, count 2 2006.285.08:35:03.02#ibcon#read 6, iclass 37, count 2 2006.285.08:35:03.02#ibcon#end of sib2, iclass 37, count 2 2006.285.08:35:03.02#ibcon#*mode == 0, iclass 37, count 2 2006.285.08:35:03.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.08:35:03.02#ibcon#[25=AT02-06\r\n] 2006.285.08:35:03.02#ibcon#*before write, iclass 37, count 2 2006.285.08:35:03.02#ibcon#enter sib2, iclass 37, count 2 2006.285.08:35:03.02#ibcon#flushed, iclass 37, count 2 2006.285.08:35:03.02#ibcon#about to write, iclass 37, count 2 2006.285.08:35:03.02#ibcon#wrote, iclass 37, count 2 2006.285.08:35:03.02#ibcon#about to read 3, iclass 37, count 2 2006.285.08:35:03.05#ibcon#read 3, iclass 37, count 2 2006.285.08:35:03.05#ibcon#about to read 4, iclass 37, count 2 2006.285.08:35:03.05#ibcon#read 4, iclass 37, count 2 2006.285.08:35:03.05#ibcon#about to read 5, iclass 37, count 2 2006.285.08:35:03.05#ibcon#read 5, iclass 37, count 2 2006.285.08:35:03.05#ibcon#about to read 6, iclass 37, count 2 2006.285.08:35:03.05#ibcon#read 6, iclass 37, count 2 2006.285.08:35:03.05#ibcon#end of sib2, iclass 37, count 2 2006.285.08:35:03.05#ibcon#*after write, iclass 37, count 2 2006.285.08:35:03.05#ibcon#*before return 0, iclass 37, count 2 2006.285.08:35:03.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:35:03.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:35:03.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.08:35:03.05#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:03.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:35:03.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:35:03.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:35:03.17#ibcon#enter wrdev, iclass 37, count 0 2006.285.08:35:03.17#ibcon#first serial, iclass 37, count 0 2006.285.08:35:03.17#ibcon#enter sib2, iclass 37, count 0 2006.285.08:35:03.17#ibcon#flushed, iclass 37, count 0 2006.285.08:35:03.17#ibcon#about to write, iclass 37, count 0 2006.285.08:35:03.17#ibcon#wrote, iclass 37, count 0 2006.285.08:35:03.17#ibcon#about to read 3, iclass 37, count 0 2006.285.08:35:03.19#ibcon#read 3, iclass 37, count 0 2006.285.08:35:03.19#ibcon#about to read 4, iclass 37, count 0 2006.285.08:35:03.19#ibcon#read 4, iclass 37, count 0 2006.285.08:35:03.19#ibcon#about to read 5, iclass 37, count 0 2006.285.08:35:03.19#ibcon#read 5, iclass 37, count 0 2006.285.08:35:03.19#ibcon#about to read 6, iclass 37, count 0 2006.285.08:35:03.19#ibcon#read 6, iclass 37, count 0 2006.285.08:35:03.19#ibcon#end of sib2, iclass 37, count 0 2006.285.08:35:03.19#ibcon#*mode == 0, iclass 37, count 0 2006.285.08:35:03.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.08:35:03.19#ibcon#[25=USB\r\n] 2006.285.08:35:03.19#ibcon#*before write, iclass 37, count 0 2006.285.08:35:03.19#ibcon#enter sib2, iclass 37, count 0 2006.285.08:35:03.19#ibcon#flushed, iclass 37, count 0 2006.285.08:35:03.19#ibcon#about to write, iclass 37, count 0 2006.285.08:35:03.19#ibcon#wrote, iclass 37, count 0 2006.285.08:35:03.19#ibcon#about to read 3, iclass 37, count 0 2006.285.08:35:03.22#ibcon#read 3, iclass 37, count 0 2006.285.08:35:03.22#ibcon#about to read 4, iclass 37, count 0 2006.285.08:35:03.22#ibcon#read 4, iclass 37, count 0 2006.285.08:35:03.22#ibcon#about to read 5, iclass 37, count 0 2006.285.08:35:03.22#ibcon#read 5, iclass 37, count 0 2006.285.08:35:03.22#ibcon#about to read 6, iclass 37, count 0 2006.285.08:35:03.22#ibcon#read 6, iclass 37, count 0 2006.285.08:35:03.22#ibcon#end of sib2, iclass 37, count 0 2006.285.08:35:03.22#ibcon#*after write, iclass 37, count 0 2006.285.08:35:03.22#ibcon#*before return 0, iclass 37, count 0 2006.285.08:35:03.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:35:03.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:35:03.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.08:35:03.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.08:35:03.22$vck44/valo=3,564.99 2006.285.08:35:03.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.08:35:03.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.08:35:03.22#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:03.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:35:03.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:35:03.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:35:03.22#ibcon#enter wrdev, iclass 39, count 0 2006.285.08:35:03.22#ibcon#first serial, iclass 39, count 0 2006.285.08:35:03.22#ibcon#enter sib2, iclass 39, count 0 2006.285.08:35:03.22#ibcon#flushed, iclass 39, count 0 2006.285.08:35:03.22#ibcon#about to write, iclass 39, count 0 2006.285.08:35:03.22#ibcon#wrote, iclass 39, count 0 2006.285.08:35:03.22#ibcon#about to read 3, iclass 39, count 0 2006.285.08:35:03.24#ibcon#read 3, iclass 39, count 0 2006.285.08:35:03.24#ibcon#about to read 4, iclass 39, count 0 2006.285.08:35:03.24#ibcon#read 4, iclass 39, count 0 2006.285.08:35:03.24#ibcon#about to read 5, iclass 39, count 0 2006.285.08:35:03.24#ibcon#read 5, iclass 39, count 0 2006.285.08:35:03.24#ibcon#about to read 6, iclass 39, count 0 2006.285.08:35:03.24#ibcon#read 6, iclass 39, count 0 2006.285.08:35:03.24#ibcon#end of sib2, iclass 39, count 0 2006.285.08:35:03.24#ibcon#*mode == 0, iclass 39, count 0 2006.285.08:35:03.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.08:35:03.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:35:03.24#ibcon#*before write, iclass 39, count 0 2006.285.08:35:03.24#ibcon#enter sib2, iclass 39, count 0 2006.285.08:35:03.24#ibcon#flushed, iclass 39, count 0 2006.285.08:35:03.24#ibcon#about to write, iclass 39, count 0 2006.285.08:35:03.24#ibcon#wrote, iclass 39, count 0 2006.285.08:35:03.24#ibcon#about to read 3, iclass 39, count 0 2006.285.08:35:03.28#ibcon#read 3, iclass 39, count 0 2006.285.08:35:03.28#ibcon#about to read 4, iclass 39, count 0 2006.285.08:35:03.28#ibcon#read 4, iclass 39, count 0 2006.285.08:35:03.28#ibcon#about to read 5, iclass 39, count 0 2006.285.08:35:03.28#ibcon#read 5, iclass 39, count 0 2006.285.08:35:03.28#ibcon#about to read 6, iclass 39, count 0 2006.285.08:35:03.28#ibcon#read 6, iclass 39, count 0 2006.285.08:35:03.28#ibcon#end of sib2, iclass 39, count 0 2006.285.08:35:03.28#ibcon#*after write, iclass 39, count 0 2006.285.08:35:03.28#ibcon#*before return 0, iclass 39, count 0 2006.285.08:35:03.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:35:03.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:35:03.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.08:35:03.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.08:35:03.28$vck44/va=3,7 2006.285.08:35:03.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.08:35:03.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.08:35:03.28#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:03.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:35:03.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:35:03.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:35:03.34#ibcon#enter wrdev, iclass 3, count 2 2006.285.08:35:03.34#ibcon#first serial, iclass 3, count 2 2006.285.08:35:03.34#ibcon#enter sib2, iclass 3, count 2 2006.285.08:35:03.34#ibcon#flushed, iclass 3, count 2 2006.285.08:35:03.34#ibcon#about to write, iclass 3, count 2 2006.285.08:35:03.34#ibcon#wrote, iclass 3, count 2 2006.285.08:35:03.34#ibcon#about to read 3, iclass 3, count 2 2006.285.08:35:03.36#ibcon#read 3, iclass 3, count 2 2006.285.08:35:03.36#ibcon#about to read 4, iclass 3, count 2 2006.285.08:35:03.36#ibcon#read 4, iclass 3, count 2 2006.285.08:35:03.36#ibcon#about to read 5, iclass 3, count 2 2006.285.08:35:03.36#ibcon#read 5, iclass 3, count 2 2006.285.08:35:03.36#ibcon#about to read 6, iclass 3, count 2 2006.285.08:35:03.36#ibcon#read 6, iclass 3, count 2 2006.285.08:35:03.36#ibcon#end of sib2, iclass 3, count 2 2006.285.08:35:03.36#ibcon#*mode == 0, iclass 3, count 2 2006.285.08:35:03.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.08:35:03.36#ibcon#[25=AT03-07\r\n] 2006.285.08:35:03.36#ibcon#*before write, iclass 3, count 2 2006.285.08:35:03.36#ibcon#enter sib2, iclass 3, count 2 2006.285.08:35:03.36#ibcon#flushed, iclass 3, count 2 2006.285.08:35:03.36#ibcon#about to write, iclass 3, count 2 2006.285.08:35:03.36#ibcon#wrote, iclass 3, count 2 2006.285.08:35:03.36#ibcon#about to read 3, iclass 3, count 2 2006.285.08:35:03.39#ibcon#read 3, iclass 3, count 2 2006.285.08:35:03.39#ibcon#about to read 4, iclass 3, count 2 2006.285.08:35:03.39#ibcon#read 4, iclass 3, count 2 2006.285.08:35:03.39#ibcon#about to read 5, iclass 3, count 2 2006.285.08:35:03.39#ibcon#read 5, iclass 3, count 2 2006.285.08:35:03.39#ibcon#about to read 6, iclass 3, count 2 2006.285.08:35:03.39#ibcon#read 6, iclass 3, count 2 2006.285.08:35:03.39#ibcon#end of sib2, iclass 3, count 2 2006.285.08:35:03.39#ibcon#*after write, iclass 3, count 2 2006.285.08:35:03.39#ibcon#*before return 0, iclass 3, count 2 2006.285.08:35:03.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:35:03.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:35:03.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.08:35:03.39#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:03.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:35:03.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:35:03.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:35:03.51#ibcon#enter wrdev, iclass 3, count 0 2006.285.08:35:03.51#ibcon#first serial, iclass 3, count 0 2006.285.08:35:03.51#ibcon#enter sib2, iclass 3, count 0 2006.285.08:35:03.51#ibcon#flushed, iclass 3, count 0 2006.285.08:35:03.51#ibcon#about to write, iclass 3, count 0 2006.285.08:35:03.51#ibcon#wrote, iclass 3, count 0 2006.285.08:35:03.51#ibcon#about to read 3, iclass 3, count 0 2006.285.08:35:03.53#ibcon#read 3, iclass 3, count 0 2006.285.08:35:03.53#ibcon#about to read 4, iclass 3, count 0 2006.285.08:35:03.53#ibcon#read 4, iclass 3, count 0 2006.285.08:35:03.53#ibcon#about to read 5, iclass 3, count 0 2006.285.08:35:03.53#ibcon#read 5, iclass 3, count 0 2006.285.08:35:03.53#ibcon#about to read 6, iclass 3, count 0 2006.285.08:35:03.53#ibcon#read 6, iclass 3, count 0 2006.285.08:35:03.53#ibcon#end of sib2, iclass 3, count 0 2006.285.08:35:03.53#ibcon#*mode == 0, iclass 3, count 0 2006.285.08:35:03.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.08:35:03.53#ibcon#[25=USB\r\n] 2006.285.08:35:03.53#ibcon#*before write, iclass 3, count 0 2006.285.08:35:03.53#ibcon#enter sib2, iclass 3, count 0 2006.285.08:35:03.53#ibcon#flushed, iclass 3, count 0 2006.285.08:35:03.53#ibcon#about to write, iclass 3, count 0 2006.285.08:35:03.53#ibcon#wrote, iclass 3, count 0 2006.285.08:35:03.53#ibcon#about to read 3, iclass 3, count 0 2006.285.08:35:03.56#ibcon#read 3, iclass 3, count 0 2006.285.08:35:03.56#ibcon#about to read 4, iclass 3, count 0 2006.285.08:35:03.56#ibcon#read 4, iclass 3, count 0 2006.285.08:35:03.56#ibcon#about to read 5, iclass 3, count 0 2006.285.08:35:03.56#ibcon#read 5, iclass 3, count 0 2006.285.08:35:03.56#ibcon#about to read 6, iclass 3, count 0 2006.285.08:35:03.56#ibcon#read 6, iclass 3, count 0 2006.285.08:35:03.56#ibcon#end of sib2, iclass 3, count 0 2006.285.08:35:03.56#ibcon#*after write, iclass 3, count 0 2006.285.08:35:03.56#ibcon#*before return 0, iclass 3, count 0 2006.285.08:35:03.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:35:03.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:35:03.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.08:35:03.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.08:35:03.56$vck44/valo=4,624.99 2006.285.08:35:03.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.08:35:03.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.08:35:03.56#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:03.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:35:03.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:35:03.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:35:03.56#ibcon#enter wrdev, iclass 5, count 0 2006.285.08:35:03.56#ibcon#first serial, iclass 5, count 0 2006.285.08:35:03.56#ibcon#enter sib2, iclass 5, count 0 2006.285.08:35:03.56#ibcon#flushed, iclass 5, count 0 2006.285.08:35:03.56#ibcon#about to write, iclass 5, count 0 2006.285.08:35:03.56#ibcon#wrote, iclass 5, count 0 2006.285.08:35:03.56#ibcon#about to read 3, iclass 5, count 0 2006.285.08:35:03.58#ibcon#read 3, iclass 5, count 0 2006.285.08:35:03.58#ibcon#about to read 4, iclass 5, count 0 2006.285.08:35:03.58#ibcon#read 4, iclass 5, count 0 2006.285.08:35:03.58#ibcon#about to read 5, iclass 5, count 0 2006.285.08:35:03.58#ibcon#read 5, iclass 5, count 0 2006.285.08:35:03.58#ibcon#about to read 6, iclass 5, count 0 2006.285.08:35:03.58#ibcon#read 6, iclass 5, count 0 2006.285.08:35:03.58#ibcon#end of sib2, iclass 5, count 0 2006.285.08:35:03.58#ibcon#*mode == 0, iclass 5, count 0 2006.285.08:35:03.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.08:35:03.58#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:35:03.58#ibcon#*before write, iclass 5, count 0 2006.285.08:35:03.58#ibcon#enter sib2, iclass 5, count 0 2006.285.08:35:03.58#ibcon#flushed, iclass 5, count 0 2006.285.08:35:03.58#ibcon#about to write, iclass 5, count 0 2006.285.08:35:03.58#ibcon#wrote, iclass 5, count 0 2006.285.08:35:03.58#ibcon#about to read 3, iclass 5, count 0 2006.285.08:35:03.62#ibcon#read 3, iclass 5, count 0 2006.285.08:35:03.62#ibcon#about to read 4, iclass 5, count 0 2006.285.08:35:03.62#ibcon#read 4, iclass 5, count 0 2006.285.08:35:03.62#ibcon#about to read 5, iclass 5, count 0 2006.285.08:35:03.62#ibcon#read 5, iclass 5, count 0 2006.285.08:35:03.62#ibcon#about to read 6, iclass 5, count 0 2006.285.08:35:03.62#ibcon#read 6, iclass 5, count 0 2006.285.08:35:03.62#ibcon#end of sib2, iclass 5, count 0 2006.285.08:35:03.62#ibcon#*after write, iclass 5, count 0 2006.285.08:35:03.62#ibcon#*before return 0, iclass 5, count 0 2006.285.08:35:03.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:35:03.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:35:03.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.08:35:03.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.08:35:03.62$vck44/va=4,6 2006.285.08:35:03.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.08:35:03.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.08:35:03.62#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:03.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.08:35:03.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.08:35:03.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.08:35:03.68#ibcon#enter wrdev, iclass 7, count 2 2006.285.08:35:03.68#ibcon#first serial, iclass 7, count 2 2006.285.08:35:03.68#ibcon#enter sib2, iclass 7, count 2 2006.285.08:35:03.68#ibcon#flushed, iclass 7, count 2 2006.285.08:35:03.68#ibcon#about to write, iclass 7, count 2 2006.285.08:35:03.68#ibcon#wrote, iclass 7, count 2 2006.285.08:35:03.68#ibcon#about to read 3, iclass 7, count 2 2006.285.08:35:03.70#ibcon#read 3, iclass 7, count 2 2006.285.08:35:03.70#ibcon#about to read 4, iclass 7, count 2 2006.285.08:35:03.70#ibcon#read 4, iclass 7, count 2 2006.285.08:35:03.70#ibcon#about to read 5, iclass 7, count 2 2006.285.08:35:03.70#ibcon#read 5, iclass 7, count 2 2006.285.08:35:03.70#ibcon#about to read 6, iclass 7, count 2 2006.285.08:35:03.70#ibcon#read 6, iclass 7, count 2 2006.285.08:35:03.70#ibcon#end of sib2, iclass 7, count 2 2006.285.08:35:03.70#ibcon#*mode == 0, iclass 7, count 2 2006.285.08:35:03.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.08:35:03.70#ibcon#[25=AT04-06\r\n] 2006.285.08:35:03.70#ibcon#*before write, iclass 7, count 2 2006.285.08:35:03.70#ibcon#enter sib2, iclass 7, count 2 2006.285.08:35:03.70#ibcon#flushed, iclass 7, count 2 2006.285.08:35:03.70#ibcon#about to write, iclass 7, count 2 2006.285.08:35:03.70#ibcon#wrote, iclass 7, count 2 2006.285.08:35:03.70#ibcon#about to read 3, iclass 7, count 2 2006.285.08:35:03.73#ibcon#read 3, iclass 7, count 2 2006.285.08:35:03.73#ibcon#about to read 4, iclass 7, count 2 2006.285.08:35:03.73#ibcon#read 4, iclass 7, count 2 2006.285.08:35:03.73#ibcon#about to read 5, iclass 7, count 2 2006.285.08:35:03.73#ibcon#read 5, iclass 7, count 2 2006.285.08:35:03.73#ibcon#about to read 6, iclass 7, count 2 2006.285.08:35:03.73#ibcon#read 6, iclass 7, count 2 2006.285.08:35:03.73#ibcon#end of sib2, iclass 7, count 2 2006.285.08:35:03.73#ibcon#*after write, iclass 7, count 2 2006.285.08:35:03.73#ibcon#*before return 0, iclass 7, count 2 2006.285.08:35:03.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.08:35:03.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.08:35:03.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.08:35:03.73#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:03.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.08:35:03.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.08:35:03.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.08:35:03.85#ibcon#enter wrdev, iclass 7, count 0 2006.285.08:35:03.85#ibcon#first serial, iclass 7, count 0 2006.285.08:35:03.85#ibcon#enter sib2, iclass 7, count 0 2006.285.08:35:03.85#ibcon#flushed, iclass 7, count 0 2006.285.08:35:03.85#ibcon#about to write, iclass 7, count 0 2006.285.08:35:03.85#ibcon#wrote, iclass 7, count 0 2006.285.08:35:03.85#ibcon#about to read 3, iclass 7, count 0 2006.285.08:35:03.87#ibcon#read 3, iclass 7, count 0 2006.285.08:35:03.87#ibcon#about to read 4, iclass 7, count 0 2006.285.08:35:03.87#ibcon#read 4, iclass 7, count 0 2006.285.08:35:03.87#ibcon#about to read 5, iclass 7, count 0 2006.285.08:35:03.87#ibcon#read 5, iclass 7, count 0 2006.285.08:35:03.87#ibcon#about to read 6, iclass 7, count 0 2006.285.08:35:03.87#ibcon#read 6, iclass 7, count 0 2006.285.08:35:03.87#ibcon#end of sib2, iclass 7, count 0 2006.285.08:35:03.87#ibcon#*mode == 0, iclass 7, count 0 2006.285.08:35:03.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.08:35:03.87#ibcon#[25=USB\r\n] 2006.285.08:35:03.87#ibcon#*before write, iclass 7, count 0 2006.285.08:35:03.87#ibcon#enter sib2, iclass 7, count 0 2006.285.08:35:03.87#ibcon#flushed, iclass 7, count 0 2006.285.08:35:03.87#ibcon#about to write, iclass 7, count 0 2006.285.08:35:03.87#ibcon#wrote, iclass 7, count 0 2006.285.08:35:03.87#ibcon#about to read 3, iclass 7, count 0 2006.285.08:35:03.90#ibcon#read 3, iclass 7, count 0 2006.285.08:35:03.90#ibcon#about to read 4, iclass 7, count 0 2006.285.08:35:03.90#ibcon#read 4, iclass 7, count 0 2006.285.08:35:03.90#ibcon#about to read 5, iclass 7, count 0 2006.285.08:35:03.90#ibcon#read 5, iclass 7, count 0 2006.285.08:35:03.90#ibcon#about to read 6, iclass 7, count 0 2006.285.08:35:03.90#ibcon#read 6, iclass 7, count 0 2006.285.08:35:03.90#ibcon#end of sib2, iclass 7, count 0 2006.285.08:35:03.90#ibcon#*after write, iclass 7, count 0 2006.285.08:35:03.90#ibcon#*before return 0, iclass 7, count 0 2006.285.08:35:03.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.08:35:03.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.08:35:03.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.08:35:03.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.08:35:03.90$vck44/valo=5,734.99 2006.285.08:35:03.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.08:35:03.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.08:35:03.90#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:03.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:35:03.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:35:03.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:35:03.90#ibcon#enter wrdev, iclass 11, count 0 2006.285.08:35:03.90#ibcon#first serial, iclass 11, count 0 2006.285.08:35:03.90#ibcon#enter sib2, iclass 11, count 0 2006.285.08:35:03.90#ibcon#flushed, iclass 11, count 0 2006.285.08:35:03.90#ibcon#about to write, iclass 11, count 0 2006.285.08:35:03.90#ibcon#wrote, iclass 11, count 0 2006.285.08:35:03.90#ibcon#about to read 3, iclass 11, count 0 2006.285.08:35:03.92#ibcon#read 3, iclass 11, count 0 2006.285.08:35:03.92#ibcon#about to read 4, iclass 11, count 0 2006.285.08:35:03.92#ibcon#read 4, iclass 11, count 0 2006.285.08:35:03.92#ibcon#about to read 5, iclass 11, count 0 2006.285.08:35:03.92#ibcon#read 5, iclass 11, count 0 2006.285.08:35:03.92#ibcon#about to read 6, iclass 11, count 0 2006.285.08:35:03.92#ibcon#read 6, iclass 11, count 0 2006.285.08:35:03.92#ibcon#end of sib2, iclass 11, count 0 2006.285.08:35:03.92#ibcon#*mode == 0, iclass 11, count 0 2006.285.08:35:03.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.08:35:03.92#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:35:03.92#ibcon#*before write, iclass 11, count 0 2006.285.08:35:03.92#ibcon#enter sib2, iclass 11, count 0 2006.285.08:35:03.92#ibcon#flushed, iclass 11, count 0 2006.285.08:35:03.92#ibcon#about to write, iclass 11, count 0 2006.285.08:35:03.92#ibcon#wrote, iclass 11, count 0 2006.285.08:35:03.92#ibcon#about to read 3, iclass 11, count 0 2006.285.08:35:03.96#ibcon#read 3, iclass 11, count 0 2006.285.08:35:03.96#ibcon#about to read 4, iclass 11, count 0 2006.285.08:35:03.96#ibcon#read 4, iclass 11, count 0 2006.285.08:35:03.96#ibcon#about to read 5, iclass 11, count 0 2006.285.08:35:03.96#ibcon#read 5, iclass 11, count 0 2006.285.08:35:03.96#ibcon#about to read 6, iclass 11, count 0 2006.285.08:35:03.96#ibcon#read 6, iclass 11, count 0 2006.285.08:35:03.96#ibcon#end of sib2, iclass 11, count 0 2006.285.08:35:03.96#ibcon#*after write, iclass 11, count 0 2006.285.08:35:03.96#ibcon#*before return 0, iclass 11, count 0 2006.285.08:35:03.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:35:03.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:35:03.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.08:35:03.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.08:35:03.96$vck44/va=5,3 2006.285.08:35:03.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.08:35:03.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.08:35:03.96#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:03.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:35:04.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:35:04.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:35:04.02#ibcon#enter wrdev, iclass 13, count 2 2006.285.08:35:04.02#ibcon#first serial, iclass 13, count 2 2006.285.08:35:04.02#ibcon#enter sib2, iclass 13, count 2 2006.285.08:35:04.02#ibcon#flushed, iclass 13, count 2 2006.285.08:35:04.02#ibcon#about to write, iclass 13, count 2 2006.285.08:35:04.02#ibcon#wrote, iclass 13, count 2 2006.285.08:35:04.02#ibcon#about to read 3, iclass 13, count 2 2006.285.08:35:04.04#ibcon#read 3, iclass 13, count 2 2006.285.08:35:04.04#ibcon#about to read 4, iclass 13, count 2 2006.285.08:35:04.04#ibcon#read 4, iclass 13, count 2 2006.285.08:35:04.04#ibcon#about to read 5, iclass 13, count 2 2006.285.08:35:04.04#ibcon#read 5, iclass 13, count 2 2006.285.08:35:04.04#ibcon#about to read 6, iclass 13, count 2 2006.285.08:35:04.04#ibcon#read 6, iclass 13, count 2 2006.285.08:35:04.04#ibcon#end of sib2, iclass 13, count 2 2006.285.08:35:04.04#ibcon#*mode == 0, iclass 13, count 2 2006.285.08:35:04.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.08:35:04.04#ibcon#[25=AT05-03\r\n] 2006.285.08:35:04.04#ibcon#*before write, iclass 13, count 2 2006.285.08:35:04.04#ibcon#enter sib2, iclass 13, count 2 2006.285.08:35:04.04#ibcon#flushed, iclass 13, count 2 2006.285.08:35:04.04#ibcon#about to write, iclass 13, count 2 2006.285.08:35:04.04#ibcon#wrote, iclass 13, count 2 2006.285.08:35:04.04#ibcon#about to read 3, iclass 13, count 2 2006.285.08:35:04.07#ibcon#read 3, iclass 13, count 2 2006.285.08:35:04.07#ibcon#about to read 4, iclass 13, count 2 2006.285.08:35:04.07#ibcon#read 4, iclass 13, count 2 2006.285.08:35:04.07#ibcon#about to read 5, iclass 13, count 2 2006.285.08:35:04.07#ibcon#read 5, iclass 13, count 2 2006.285.08:35:04.07#ibcon#about to read 6, iclass 13, count 2 2006.285.08:35:04.07#ibcon#read 6, iclass 13, count 2 2006.285.08:35:04.07#ibcon#end of sib2, iclass 13, count 2 2006.285.08:35:04.07#ibcon#*after write, iclass 13, count 2 2006.285.08:35:04.07#ibcon#*before return 0, iclass 13, count 2 2006.285.08:35:04.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:35:04.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:35:04.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.08:35:04.07#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:04.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:35:04.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:35:04.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:35:04.19#ibcon#enter wrdev, iclass 13, count 0 2006.285.08:35:04.19#ibcon#first serial, iclass 13, count 0 2006.285.08:35:04.19#ibcon#enter sib2, iclass 13, count 0 2006.285.08:35:04.19#ibcon#flushed, iclass 13, count 0 2006.285.08:35:04.19#ibcon#about to write, iclass 13, count 0 2006.285.08:35:04.19#ibcon#wrote, iclass 13, count 0 2006.285.08:35:04.19#ibcon#about to read 3, iclass 13, count 0 2006.285.08:35:04.21#ibcon#read 3, iclass 13, count 0 2006.285.08:35:04.21#ibcon#about to read 4, iclass 13, count 0 2006.285.08:35:04.21#ibcon#read 4, iclass 13, count 0 2006.285.08:35:04.21#ibcon#about to read 5, iclass 13, count 0 2006.285.08:35:04.21#ibcon#read 5, iclass 13, count 0 2006.285.08:35:04.21#ibcon#about to read 6, iclass 13, count 0 2006.285.08:35:04.21#ibcon#read 6, iclass 13, count 0 2006.285.08:35:04.21#ibcon#end of sib2, iclass 13, count 0 2006.285.08:35:04.21#ibcon#*mode == 0, iclass 13, count 0 2006.285.08:35:04.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.08:35:04.21#ibcon#[25=USB\r\n] 2006.285.08:35:04.21#ibcon#*before write, iclass 13, count 0 2006.285.08:35:04.21#ibcon#enter sib2, iclass 13, count 0 2006.285.08:35:04.21#ibcon#flushed, iclass 13, count 0 2006.285.08:35:04.21#ibcon#about to write, iclass 13, count 0 2006.285.08:35:04.21#ibcon#wrote, iclass 13, count 0 2006.285.08:35:04.21#ibcon#about to read 3, iclass 13, count 0 2006.285.08:35:04.24#ibcon#read 3, iclass 13, count 0 2006.285.08:35:04.24#ibcon#about to read 4, iclass 13, count 0 2006.285.08:35:04.24#ibcon#read 4, iclass 13, count 0 2006.285.08:35:04.24#ibcon#about to read 5, iclass 13, count 0 2006.285.08:35:04.24#ibcon#read 5, iclass 13, count 0 2006.285.08:35:04.24#ibcon#about to read 6, iclass 13, count 0 2006.285.08:35:04.24#ibcon#read 6, iclass 13, count 0 2006.285.08:35:04.24#ibcon#end of sib2, iclass 13, count 0 2006.285.08:35:04.24#ibcon#*after write, iclass 13, count 0 2006.285.08:35:04.24#ibcon#*before return 0, iclass 13, count 0 2006.285.08:35:04.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:35:04.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:35:04.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.08:35:04.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.08:35:04.24$vck44/valo=6,814.99 2006.285.08:35:04.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.08:35:04.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.08:35:04.24#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:04.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:35:04.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:35:04.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:35:04.24#ibcon#enter wrdev, iclass 15, count 0 2006.285.08:35:04.24#ibcon#first serial, iclass 15, count 0 2006.285.08:35:04.24#ibcon#enter sib2, iclass 15, count 0 2006.285.08:35:04.24#ibcon#flushed, iclass 15, count 0 2006.285.08:35:04.24#ibcon#about to write, iclass 15, count 0 2006.285.08:35:04.24#ibcon#wrote, iclass 15, count 0 2006.285.08:35:04.24#ibcon#about to read 3, iclass 15, count 0 2006.285.08:35:04.26#ibcon#read 3, iclass 15, count 0 2006.285.08:35:04.26#ibcon#about to read 4, iclass 15, count 0 2006.285.08:35:04.26#ibcon#read 4, iclass 15, count 0 2006.285.08:35:04.26#ibcon#about to read 5, iclass 15, count 0 2006.285.08:35:04.26#ibcon#read 5, iclass 15, count 0 2006.285.08:35:04.26#ibcon#about to read 6, iclass 15, count 0 2006.285.08:35:04.26#ibcon#read 6, iclass 15, count 0 2006.285.08:35:04.26#ibcon#end of sib2, iclass 15, count 0 2006.285.08:35:04.26#ibcon#*mode == 0, iclass 15, count 0 2006.285.08:35:04.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.08:35:04.26#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:35:04.26#ibcon#*before write, iclass 15, count 0 2006.285.08:35:04.26#ibcon#enter sib2, iclass 15, count 0 2006.285.08:35:04.26#ibcon#flushed, iclass 15, count 0 2006.285.08:35:04.26#ibcon#about to write, iclass 15, count 0 2006.285.08:35:04.26#ibcon#wrote, iclass 15, count 0 2006.285.08:35:04.26#ibcon#about to read 3, iclass 15, count 0 2006.285.08:35:04.30#ibcon#read 3, iclass 15, count 0 2006.285.08:35:04.30#ibcon#about to read 4, iclass 15, count 0 2006.285.08:35:04.30#ibcon#read 4, iclass 15, count 0 2006.285.08:35:04.30#ibcon#about to read 5, iclass 15, count 0 2006.285.08:35:04.30#ibcon#read 5, iclass 15, count 0 2006.285.08:35:04.30#ibcon#about to read 6, iclass 15, count 0 2006.285.08:35:04.30#ibcon#read 6, iclass 15, count 0 2006.285.08:35:04.30#ibcon#end of sib2, iclass 15, count 0 2006.285.08:35:04.30#ibcon#*after write, iclass 15, count 0 2006.285.08:35:04.30#ibcon#*before return 0, iclass 15, count 0 2006.285.08:35:04.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:35:04.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:35:04.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.08:35:04.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.08:35:04.30$vck44/va=6,4 2006.285.08:35:04.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.08:35:04.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.08:35:04.30#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:04.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:35:04.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:35:04.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:35:04.36#ibcon#enter wrdev, iclass 17, count 2 2006.285.08:35:04.36#ibcon#first serial, iclass 17, count 2 2006.285.08:35:04.36#ibcon#enter sib2, iclass 17, count 2 2006.285.08:35:04.36#ibcon#flushed, iclass 17, count 2 2006.285.08:35:04.36#ibcon#about to write, iclass 17, count 2 2006.285.08:35:04.36#ibcon#wrote, iclass 17, count 2 2006.285.08:35:04.36#ibcon#about to read 3, iclass 17, count 2 2006.285.08:35:04.38#ibcon#read 3, iclass 17, count 2 2006.285.08:35:04.38#ibcon#about to read 4, iclass 17, count 2 2006.285.08:35:04.38#ibcon#read 4, iclass 17, count 2 2006.285.08:35:04.38#ibcon#about to read 5, iclass 17, count 2 2006.285.08:35:04.38#ibcon#read 5, iclass 17, count 2 2006.285.08:35:04.38#ibcon#about to read 6, iclass 17, count 2 2006.285.08:35:04.38#ibcon#read 6, iclass 17, count 2 2006.285.08:35:04.38#ibcon#end of sib2, iclass 17, count 2 2006.285.08:35:04.38#ibcon#*mode == 0, iclass 17, count 2 2006.285.08:35:04.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.08:35:04.38#ibcon#[25=AT06-04\r\n] 2006.285.08:35:04.38#ibcon#*before write, iclass 17, count 2 2006.285.08:35:04.38#ibcon#enter sib2, iclass 17, count 2 2006.285.08:35:04.38#ibcon#flushed, iclass 17, count 2 2006.285.08:35:04.38#ibcon#about to write, iclass 17, count 2 2006.285.08:35:04.38#ibcon#wrote, iclass 17, count 2 2006.285.08:35:04.38#ibcon#about to read 3, iclass 17, count 2 2006.285.08:35:04.41#ibcon#read 3, iclass 17, count 2 2006.285.08:35:04.41#ibcon#about to read 4, iclass 17, count 2 2006.285.08:35:04.41#ibcon#read 4, iclass 17, count 2 2006.285.08:35:04.41#ibcon#about to read 5, iclass 17, count 2 2006.285.08:35:04.41#ibcon#read 5, iclass 17, count 2 2006.285.08:35:04.41#ibcon#about to read 6, iclass 17, count 2 2006.285.08:35:04.41#ibcon#read 6, iclass 17, count 2 2006.285.08:35:04.41#ibcon#end of sib2, iclass 17, count 2 2006.285.08:35:04.41#ibcon#*after write, iclass 17, count 2 2006.285.08:35:04.41#ibcon#*before return 0, iclass 17, count 2 2006.285.08:35:04.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:35:04.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:35:04.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.08:35:04.41#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:04.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:35:04.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:35:04.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:35:04.53#ibcon#enter wrdev, iclass 17, count 0 2006.285.08:35:04.53#ibcon#first serial, iclass 17, count 0 2006.285.08:35:04.53#ibcon#enter sib2, iclass 17, count 0 2006.285.08:35:04.53#ibcon#flushed, iclass 17, count 0 2006.285.08:35:04.53#ibcon#about to write, iclass 17, count 0 2006.285.08:35:04.53#ibcon#wrote, iclass 17, count 0 2006.285.08:35:04.53#ibcon#about to read 3, iclass 17, count 0 2006.285.08:35:04.55#ibcon#read 3, iclass 17, count 0 2006.285.08:35:04.55#ibcon#about to read 4, iclass 17, count 0 2006.285.08:35:04.55#ibcon#read 4, iclass 17, count 0 2006.285.08:35:04.55#ibcon#about to read 5, iclass 17, count 0 2006.285.08:35:04.55#ibcon#read 5, iclass 17, count 0 2006.285.08:35:04.55#ibcon#about to read 6, iclass 17, count 0 2006.285.08:35:04.55#ibcon#read 6, iclass 17, count 0 2006.285.08:35:04.55#ibcon#end of sib2, iclass 17, count 0 2006.285.08:35:04.55#ibcon#*mode == 0, iclass 17, count 0 2006.285.08:35:04.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.08:35:04.55#ibcon#[25=USB\r\n] 2006.285.08:35:04.55#ibcon#*before write, iclass 17, count 0 2006.285.08:35:04.55#ibcon#enter sib2, iclass 17, count 0 2006.285.08:35:04.55#ibcon#flushed, iclass 17, count 0 2006.285.08:35:04.55#ibcon#about to write, iclass 17, count 0 2006.285.08:35:04.55#ibcon#wrote, iclass 17, count 0 2006.285.08:35:04.55#ibcon#about to read 3, iclass 17, count 0 2006.285.08:35:04.58#ibcon#read 3, iclass 17, count 0 2006.285.08:35:04.58#ibcon#about to read 4, iclass 17, count 0 2006.285.08:35:04.58#ibcon#read 4, iclass 17, count 0 2006.285.08:35:04.58#ibcon#about to read 5, iclass 17, count 0 2006.285.08:35:04.58#ibcon#read 5, iclass 17, count 0 2006.285.08:35:04.58#ibcon#about to read 6, iclass 17, count 0 2006.285.08:35:04.58#ibcon#read 6, iclass 17, count 0 2006.285.08:35:04.58#ibcon#end of sib2, iclass 17, count 0 2006.285.08:35:04.58#ibcon#*after write, iclass 17, count 0 2006.285.08:35:04.58#ibcon#*before return 0, iclass 17, count 0 2006.285.08:35:04.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:35:04.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:35:04.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.08:35:04.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.08:35:04.58$vck44/valo=7,864.99 2006.285.08:35:04.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.08:35:04.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.08:35:04.58#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:04.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:35:04.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:35:04.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:35:04.58#ibcon#enter wrdev, iclass 19, count 0 2006.285.08:35:04.58#ibcon#first serial, iclass 19, count 0 2006.285.08:35:04.58#ibcon#enter sib2, iclass 19, count 0 2006.285.08:35:04.58#ibcon#flushed, iclass 19, count 0 2006.285.08:35:04.58#ibcon#about to write, iclass 19, count 0 2006.285.08:35:04.58#ibcon#wrote, iclass 19, count 0 2006.285.08:35:04.58#ibcon#about to read 3, iclass 19, count 0 2006.285.08:35:04.60#ibcon#read 3, iclass 19, count 0 2006.285.08:35:04.60#ibcon#about to read 4, iclass 19, count 0 2006.285.08:35:04.60#ibcon#read 4, iclass 19, count 0 2006.285.08:35:04.60#ibcon#about to read 5, iclass 19, count 0 2006.285.08:35:04.60#ibcon#read 5, iclass 19, count 0 2006.285.08:35:04.60#ibcon#about to read 6, iclass 19, count 0 2006.285.08:35:04.60#ibcon#read 6, iclass 19, count 0 2006.285.08:35:04.60#ibcon#end of sib2, iclass 19, count 0 2006.285.08:35:04.60#ibcon#*mode == 0, iclass 19, count 0 2006.285.08:35:04.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.08:35:04.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:35:04.60#ibcon#*before write, iclass 19, count 0 2006.285.08:35:04.60#ibcon#enter sib2, iclass 19, count 0 2006.285.08:35:04.60#ibcon#flushed, iclass 19, count 0 2006.285.08:35:04.60#ibcon#about to write, iclass 19, count 0 2006.285.08:35:04.60#ibcon#wrote, iclass 19, count 0 2006.285.08:35:04.60#ibcon#about to read 3, iclass 19, count 0 2006.285.08:35:04.64#ibcon#read 3, iclass 19, count 0 2006.285.08:35:04.64#ibcon#about to read 4, iclass 19, count 0 2006.285.08:35:04.64#ibcon#read 4, iclass 19, count 0 2006.285.08:35:04.64#ibcon#about to read 5, iclass 19, count 0 2006.285.08:35:04.64#ibcon#read 5, iclass 19, count 0 2006.285.08:35:04.64#ibcon#about to read 6, iclass 19, count 0 2006.285.08:35:04.64#ibcon#read 6, iclass 19, count 0 2006.285.08:35:04.64#ibcon#end of sib2, iclass 19, count 0 2006.285.08:35:04.64#ibcon#*after write, iclass 19, count 0 2006.285.08:35:04.64#ibcon#*before return 0, iclass 19, count 0 2006.285.08:35:04.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:35:04.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:35:04.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.08:35:04.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.08:35:04.64$vck44/va=7,4 2006.285.08:35:04.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.08:35:04.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.08:35:04.64#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:04.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:35:04.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:35:04.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:35:04.70#ibcon#enter wrdev, iclass 21, count 2 2006.285.08:35:04.70#ibcon#first serial, iclass 21, count 2 2006.285.08:35:04.70#ibcon#enter sib2, iclass 21, count 2 2006.285.08:35:04.70#ibcon#flushed, iclass 21, count 2 2006.285.08:35:04.70#ibcon#about to write, iclass 21, count 2 2006.285.08:35:04.70#ibcon#wrote, iclass 21, count 2 2006.285.08:35:04.70#ibcon#about to read 3, iclass 21, count 2 2006.285.08:35:04.72#ibcon#read 3, iclass 21, count 2 2006.285.08:35:04.72#ibcon#about to read 4, iclass 21, count 2 2006.285.08:35:04.72#ibcon#read 4, iclass 21, count 2 2006.285.08:35:04.72#ibcon#about to read 5, iclass 21, count 2 2006.285.08:35:04.72#ibcon#read 5, iclass 21, count 2 2006.285.08:35:04.72#ibcon#about to read 6, iclass 21, count 2 2006.285.08:35:04.72#ibcon#read 6, iclass 21, count 2 2006.285.08:35:04.72#ibcon#end of sib2, iclass 21, count 2 2006.285.08:35:04.72#ibcon#*mode == 0, iclass 21, count 2 2006.285.08:35:04.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.08:35:04.72#ibcon#[25=AT07-04\r\n] 2006.285.08:35:04.72#ibcon#*before write, iclass 21, count 2 2006.285.08:35:04.72#ibcon#enter sib2, iclass 21, count 2 2006.285.08:35:04.72#ibcon#flushed, iclass 21, count 2 2006.285.08:35:04.72#ibcon#about to write, iclass 21, count 2 2006.285.08:35:04.72#ibcon#wrote, iclass 21, count 2 2006.285.08:35:04.72#ibcon#about to read 3, iclass 21, count 2 2006.285.08:35:04.75#ibcon#read 3, iclass 21, count 2 2006.285.08:35:04.75#ibcon#about to read 4, iclass 21, count 2 2006.285.08:35:04.75#ibcon#read 4, iclass 21, count 2 2006.285.08:35:04.75#ibcon#about to read 5, iclass 21, count 2 2006.285.08:35:04.75#ibcon#read 5, iclass 21, count 2 2006.285.08:35:04.75#ibcon#about to read 6, iclass 21, count 2 2006.285.08:35:04.75#ibcon#read 6, iclass 21, count 2 2006.285.08:35:04.75#ibcon#end of sib2, iclass 21, count 2 2006.285.08:35:04.75#ibcon#*after write, iclass 21, count 2 2006.285.08:35:04.75#ibcon#*before return 0, iclass 21, count 2 2006.285.08:35:04.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:35:04.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:35:04.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.08:35:04.75#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:04.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:35:04.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:35:04.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:35:04.87#ibcon#enter wrdev, iclass 21, count 0 2006.285.08:35:04.87#ibcon#first serial, iclass 21, count 0 2006.285.08:35:04.87#ibcon#enter sib2, iclass 21, count 0 2006.285.08:35:04.87#ibcon#flushed, iclass 21, count 0 2006.285.08:35:04.87#ibcon#about to write, iclass 21, count 0 2006.285.08:35:04.87#ibcon#wrote, iclass 21, count 0 2006.285.08:35:04.87#ibcon#about to read 3, iclass 21, count 0 2006.285.08:35:04.89#ibcon#read 3, iclass 21, count 0 2006.285.08:35:04.89#ibcon#about to read 4, iclass 21, count 0 2006.285.08:35:04.89#ibcon#read 4, iclass 21, count 0 2006.285.08:35:04.89#ibcon#about to read 5, iclass 21, count 0 2006.285.08:35:04.89#ibcon#read 5, iclass 21, count 0 2006.285.08:35:04.89#ibcon#about to read 6, iclass 21, count 0 2006.285.08:35:04.89#ibcon#read 6, iclass 21, count 0 2006.285.08:35:04.89#ibcon#end of sib2, iclass 21, count 0 2006.285.08:35:04.89#ibcon#*mode == 0, iclass 21, count 0 2006.285.08:35:04.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.08:35:04.89#ibcon#[25=USB\r\n] 2006.285.08:35:04.89#ibcon#*before write, iclass 21, count 0 2006.285.08:35:04.89#ibcon#enter sib2, iclass 21, count 0 2006.285.08:35:04.89#ibcon#flushed, iclass 21, count 0 2006.285.08:35:04.89#ibcon#about to write, iclass 21, count 0 2006.285.08:35:04.89#ibcon#wrote, iclass 21, count 0 2006.285.08:35:04.89#ibcon#about to read 3, iclass 21, count 0 2006.285.08:35:04.92#ibcon#read 3, iclass 21, count 0 2006.285.08:35:04.92#ibcon#about to read 4, iclass 21, count 0 2006.285.08:35:04.92#ibcon#read 4, iclass 21, count 0 2006.285.08:35:04.92#ibcon#about to read 5, iclass 21, count 0 2006.285.08:35:04.92#ibcon#read 5, iclass 21, count 0 2006.285.08:35:04.92#ibcon#about to read 6, iclass 21, count 0 2006.285.08:35:04.92#ibcon#read 6, iclass 21, count 0 2006.285.08:35:04.92#ibcon#end of sib2, iclass 21, count 0 2006.285.08:35:04.92#ibcon#*after write, iclass 21, count 0 2006.285.08:35:04.92#ibcon#*before return 0, iclass 21, count 0 2006.285.08:35:04.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:35:04.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:35:04.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.08:35:04.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.08:35:04.92$vck44/valo=8,884.99 2006.285.08:35:04.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.08:35:04.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.08:35:04.92#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:04.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:35:04.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:35:04.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:35:04.92#ibcon#enter wrdev, iclass 23, count 0 2006.285.08:35:04.92#ibcon#first serial, iclass 23, count 0 2006.285.08:35:04.92#ibcon#enter sib2, iclass 23, count 0 2006.285.08:35:04.92#ibcon#flushed, iclass 23, count 0 2006.285.08:35:04.92#ibcon#about to write, iclass 23, count 0 2006.285.08:35:04.92#ibcon#wrote, iclass 23, count 0 2006.285.08:35:04.92#ibcon#about to read 3, iclass 23, count 0 2006.285.08:35:04.94#ibcon#read 3, iclass 23, count 0 2006.285.08:35:04.94#ibcon#about to read 4, iclass 23, count 0 2006.285.08:35:04.94#ibcon#read 4, iclass 23, count 0 2006.285.08:35:04.94#ibcon#about to read 5, iclass 23, count 0 2006.285.08:35:04.94#ibcon#read 5, iclass 23, count 0 2006.285.08:35:04.94#ibcon#about to read 6, iclass 23, count 0 2006.285.08:35:04.94#ibcon#read 6, iclass 23, count 0 2006.285.08:35:04.94#ibcon#end of sib2, iclass 23, count 0 2006.285.08:35:04.94#ibcon#*mode == 0, iclass 23, count 0 2006.285.08:35:04.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.08:35:04.94#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:35:04.94#ibcon#*before write, iclass 23, count 0 2006.285.08:35:04.94#ibcon#enter sib2, iclass 23, count 0 2006.285.08:35:04.94#ibcon#flushed, iclass 23, count 0 2006.285.08:35:04.94#ibcon#about to write, iclass 23, count 0 2006.285.08:35:04.94#ibcon#wrote, iclass 23, count 0 2006.285.08:35:04.94#ibcon#about to read 3, iclass 23, count 0 2006.285.08:35:04.98#ibcon#read 3, iclass 23, count 0 2006.285.08:35:04.98#ibcon#about to read 4, iclass 23, count 0 2006.285.08:35:04.98#ibcon#read 4, iclass 23, count 0 2006.285.08:35:04.98#ibcon#about to read 5, iclass 23, count 0 2006.285.08:35:04.98#ibcon#read 5, iclass 23, count 0 2006.285.08:35:04.98#ibcon#about to read 6, iclass 23, count 0 2006.285.08:35:04.98#ibcon#read 6, iclass 23, count 0 2006.285.08:35:04.98#ibcon#end of sib2, iclass 23, count 0 2006.285.08:35:04.98#ibcon#*after write, iclass 23, count 0 2006.285.08:35:04.98#ibcon#*before return 0, iclass 23, count 0 2006.285.08:35:04.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:35:04.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:35:04.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.08:35:04.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.08:35:04.98$vck44/va=8,3 2006.285.08:35:04.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.08:35:04.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.08:35:04.98#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:04.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:35:05.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:35:05.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:35:05.04#ibcon#enter wrdev, iclass 25, count 2 2006.285.08:35:05.04#ibcon#first serial, iclass 25, count 2 2006.285.08:35:05.04#ibcon#enter sib2, iclass 25, count 2 2006.285.08:35:05.04#ibcon#flushed, iclass 25, count 2 2006.285.08:35:05.04#ibcon#about to write, iclass 25, count 2 2006.285.08:35:05.04#ibcon#wrote, iclass 25, count 2 2006.285.08:35:05.04#ibcon#about to read 3, iclass 25, count 2 2006.285.08:35:05.06#ibcon#read 3, iclass 25, count 2 2006.285.08:35:05.06#ibcon#about to read 4, iclass 25, count 2 2006.285.08:35:05.06#ibcon#read 4, iclass 25, count 2 2006.285.08:35:05.06#ibcon#about to read 5, iclass 25, count 2 2006.285.08:35:05.06#ibcon#read 5, iclass 25, count 2 2006.285.08:35:05.06#ibcon#about to read 6, iclass 25, count 2 2006.285.08:35:05.06#ibcon#read 6, iclass 25, count 2 2006.285.08:35:05.06#ibcon#end of sib2, iclass 25, count 2 2006.285.08:35:05.06#ibcon#*mode == 0, iclass 25, count 2 2006.285.08:35:05.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.08:35:05.06#ibcon#[25=AT08-03\r\n] 2006.285.08:35:05.06#ibcon#*before write, iclass 25, count 2 2006.285.08:35:05.06#ibcon#enter sib2, iclass 25, count 2 2006.285.08:35:05.06#ibcon#flushed, iclass 25, count 2 2006.285.08:35:05.06#ibcon#about to write, iclass 25, count 2 2006.285.08:35:05.06#ibcon#wrote, iclass 25, count 2 2006.285.08:35:05.06#ibcon#about to read 3, iclass 25, count 2 2006.285.08:35:05.09#ibcon#read 3, iclass 25, count 2 2006.285.08:35:05.09#ibcon#about to read 4, iclass 25, count 2 2006.285.08:35:05.09#ibcon#read 4, iclass 25, count 2 2006.285.08:35:05.09#ibcon#about to read 5, iclass 25, count 2 2006.285.08:35:05.09#ibcon#read 5, iclass 25, count 2 2006.285.08:35:05.09#ibcon#about to read 6, iclass 25, count 2 2006.285.08:35:05.09#ibcon#read 6, iclass 25, count 2 2006.285.08:35:05.09#ibcon#end of sib2, iclass 25, count 2 2006.285.08:35:05.09#ibcon#*after write, iclass 25, count 2 2006.285.08:35:05.09#ibcon#*before return 0, iclass 25, count 2 2006.285.08:35:05.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:35:05.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.08:35:05.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.08:35:05.09#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:05.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:35:05.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:35:05.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:35:05.21#ibcon#enter wrdev, iclass 25, count 0 2006.285.08:35:05.21#ibcon#first serial, iclass 25, count 0 2006.285.08:35:05.21#ibcon#enter sib2, iclass 25, count 0 2006.285.08:35:05.21#ibcon#flushed, iclass 25, count 0 2006.285.08:35:05.21#ibcon#about to write, iclass 25, count 0 2006.285.08:35:05.21#ibcon#wrote, iclass 25, count 0 2006.285.08:35:05.21#ibcon#about to read 3, iclass 25, count 0 2006.285.08:35:05.23#ibcon#read 3, iclass 25, count 0 2006.285.08:35:05.23#ibcon#about to read 4, iclass 25, count 0 2006.285.08:35:05.23#ibcon#read 4, iclass 25, count 0 2006.285.08:35:05.23#ibcon#about to read 5, iclass 25, count 0 2006.285.08:35:05.23#ibcon#read 5, iclass 25, count 0 2006.285.08:35:05.23#ibcon#about to read 6, iclass 25, count 0 2006.285.08:35:05.23#ibcon#read 6, iclass 25, count 0 2006.285.08:35:05.23#ibcon#end of sib2, iclass 25, count 0 2006.285.08:35:05.23#ibcon#*mode == 0, iclass 25, count 0 2006.285.08:35:05.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.08:35:05.23#ibcon#[25=USB\r\n] 2006.285.08:35:05.23#ibcon#*before write, iclass 25, count 0 2006.285.08:35:05.23#ibcon#enter sib2, iclass 25, count 0 2006.285.08:35:05.23#ibcon#flushed, iclass 25, count 0 2006.285.08:35:05.23#ibcon#about to write, iclass 25, count 0 2006.285.08:35:05.23#ibcon#wrote, iclass 25, count 0 2006.285.08:35:05.23#ibcon#about to read 3, iclass 25, count 0 2006.285.08:35:05.26#ibcon#read 3, iclass 25, count 0 2006.285.08:35:05.26#ibcon#about to read 4, iclass 25, count 0 2006.285.08:35:05.26#ibcon#read 4, iclass 25, count 0 2006.285.08:35:05.26#ibcon#about to read 5, iclass 25, count 0 2006.285.08:35:05.26#ibcon#read 5, iclass 25, count 0 2006.285.08:35:05.26#ibcon#about to read 6, iclass 25, count 0 2006.285.08:35:05.26#ibcon#read 6, iclass 25, count 0 2006.285.08:35:05.26#ibcon#end of sib2, iclass 25, count 0 2006.285.08:35:05.26#ibcon#*after write, iclass 25, count 0 2006.285.08:35:05.26#ibcon#*before return 0, iclass 25, count 0 2006.285.08:35:05.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:35:05.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.08:35:05.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.08:35:05.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.08:35:05.26$vck44/vblo=1,629.99 2006.285.08:35:05.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.08:35:05.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.08:35:05.26#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:05.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:35:05.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:35:05.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:35:05.26#ibcon#enter wrdev, iclass 27, count 0 2006.285.08:35:05.26#ibcon#first serial, iclass 27, count 0 2006.285.08:35:05.26#ibcon#enter sib2, iclass 27, count 0 2006.285.08:35:05.26#ibcon#flushed, iclass 27, count 0 2006.285.08:35:05.26#ibcon#about to write, iclass 27, count 0 2006.285.08:35:05.26#ibcon#wrote, iclass 27, count 0 2006.285.08:35:05.26#ibcon#about to read 3, iclass 27, count 0 2006.285.08:35:05.28#ibcon#read 3, iclass 27, count 0 2006.285.08:35:05.28#ibcon#about to read 4, iclass 27, count 0 2006.285.08:35:05.28#ibcon#read 4, iclass 27, count 0 2006.285.08:35:05.28#ibcon#about to read 5, iclass 27, count 0 2006.285.08:35:05.28#ibcon#read 5, iclass 27, count 0 2006.285.08:35:05.28#ibcon#about to read 6, iclass 27, count 0 2006.285.08:35:05.28#ibcon#read 6, iclass 27, count 0 2006.285.08:35:05.28#ibcon#end of sib2, iclass 27, count 0 2006.285.08:35:05.28#ibcon#*mode == 0, iclass 27, count 0 2006.285.08:35:05.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.08:35:05.28#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:35:05.28#ibcon#*before write, iclass 27, count 0 2006.285.08:35:05.28#ibcon#enter sib2, iclass 27, count 0 2006.285.08:35:05.28#ibcon#flushed, iclass 27, count 0 2006.285.08:35:05.28#ibcon#about to write, iclass 27, count 0 2006.285.08:35:05.28#ibcon#wrote, iclass 27, count 0 2006.285.08:35:05.28#ibcon#about to read 3, iclass 27, count 0 2006.285.08:35:05.32#ibcon#read 3, iclass 27, count 0 2006.285.08:35:05.32#ibcon#about to read 4, iclass 27, count 0 2006.285.08:35:05.32#ibcon#read 4, iclass 27, count 0 2006.285.08:35:05.32#ibcon#about to read 5, iclass 27, count 0 2006.285.08:35:05.32#ibcon#read 5, iclass 27, count 0 2006.285.08:35:05.32#ibcon#about to read 6, iclass 27, count 0 2006.285.08:35:05.32#ibcon#read 6, iclass 27, count 0 2006.285.08:35:05.32#ibcon#end of sib2, iclass 27, count 0 2006.285.08:35:05.32#ibcon#*after write, iclass 27, count 0 2006.285.08:35:05.32#ibcon#*before return 0, iclass 27, count 0 2006.285.08:35:05.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:35:05.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.08:35:05.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.08:35:05.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.08:35:05.32$vck44/vb=1,4 2006.285.08:35:05.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.08:35:05.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.08:35:05.32#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:05.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:35:05.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:35:05.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:35:05.32#ibcon#enter wrdev, iclass 29, count 2 2006.285.08:35:05.32#ibcon#first serial, iclass 29, count 2 2006.285.08:35:05.32#ibcon#enter sib2, iclass 29, count 2 2006.285.08:35:05.32#ibcon#flushed, iclass 29, count 2 2006.285.08:35:05.32#ibcon#about to write, iclass 29, count 2 2006.285.08:35:05.32#ibcon#wrote, iclass 29, count 2 2006.285.08:35:05.32#ibcon#about to read 3, iclass 29, count 2 2006.285.08:35:05.34#ibcon#read 3, iclass 29, count 2 2006.285.08:35:05.34#ibcon#about to read 4, iclass 29, count 2 2006.285.08:35:05.34#ibcon#read 4, iclass 29, count 2 2006.285.08:35:05.34#ibcon#about to read 5, iclass 29, count 2 2006.285.08:35:05.34#ibcon#read 5, iclass 29, count 2 2006.285.08:35:05.34#ibcon#about to read 6, iclass 29, count 2 2006.285.08:35:05.34#ibcon#read 6, iclass 29, count 2 2006.285.08:35:05.34#ibcon#end of sib2, iclass 29, count 2 2006.285.08:35:05.34#ibcon#*mode == 0, iclass 29, count 2 2006.285.08:35:05.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.08:35:05.34#ibcon#[27=AT01-04\r\n] 2006.285.08:35:05.34#ibcon#*before write, iclass 29, count 2 2006.285.08:35:05.34#ibcon#enter sib2, iclass 29, count 2 2006.285.08:35:05.34#ibcon#flushed, iclass 29, count 2 2006.285.08:35:05.34#ibcon#about to write, iclass 29, count 2 2006.285.08:35:05.34#ibcon#wrote, iclass 29, count 2 2006.285.08:35:05.34#ibcon#about to read 3, iclass 29, count 2 2006.285.08:35:05.37#ibcon#read 3, iclass 29, count 2 2006.285.08:35:05.37#ibcon#about to read 4, iclass 29, count 2 2006.285.08:35:05.37#ibcon#read 4, iclass 29, count 2 2006.285.08:35:05.37#ibcon#about to read 5, iclass 29, count 2 2006.285.08:35:05.37#ibcon#read 5, iclass 29, count 2 2006.285.08:35:05.37#ibcon#about to read 6, iclass 29, count 2 2006.285.08:35:05.37#ibcon#read 6, iclass 29, count 2 2006.285.08:35:05.37#ibcon#end of sib2, iclass 29, count 2 2006.285.08:35:05.37#ibcon#*after write, iclass 29, count 2 2006.285.08:35:05.37#ibcon#*before return 0, iclass 29, count 2 2006.285.08:35:05.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:35:05.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.08:35:05.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.08:35:05.37#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:05.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:35:05.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:35:05.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:35:05.49#ibcon#enter wrdev, iclass 29, count 0 2006.285.08:35:05.49#ibcon#first serial, iclass 29, count 0 2006.285.08:35:05.49#ibcon#enter sib2, iclass 29, count 0 2006.285.08:35:05.49#ibcon#flushed, iclass 29, count 0 2006.285.08:35:05.49#ibcon#about to write, iclass 29, count 0 2006.285.08:35:05.49#ibcon#wrote, iclass 29, count 0 2006.285.08:35:05.49#ibcon#about to read 3, iclass 29, count 0 2006.285.08:35:05.51#ibcon#read 3, iclass 29, count 0 2006.285.08:35:05.51#ibcon#about to read 4, iclass 29, count 0 2006.285.08:35:05.51#ibcon#read 4, iclass 29, count 0 2006.285.08:35:05.51#ibcon#about to read 5, iclass 29, count 0 2006.285.08:35:05.51#ibcon#read 5, iclass 29, count 0 2006.285.08:35:05.51#ibcon#about to read 6, iclass 29, count 0 2006.285.08:35:05.51#ibcon#read 6, iclass 29, count 0 2006.285.08:35:05.51#ibcon#end of sib2, iclass 29, count 0 2006.285.08:35:05.51#ibcon#*mode == 0, iclass 29, count 0 2006.285.08:35:05.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.08:35:05.51#ibcon#[27=USB\r\n] 2006.285.08:35:05.51#ibcon#*before write, iclass 29, count 0 2006.285.08:35:05.51#ibcon#enter sib2, iclass 29, count 0 2006.285.08:35:05.51#ibcon#flushed, iclass 29, count 0 2006.285.08:35:05.51#ibcon#about to write, iclass 29, count 0 2006.285.08:35:05.51#ibcon#wrote, iclass 29, count 0 2006.285.08:35:05.51#ibcon#about to read 3, iclass 29, count 0 2006.285.08:35:05.54#ibcon#read 3, iclass 29, count 0 2006.285.08:35:05.54#ibcon#about to read 4, iclass 29, count 0 2006.285.08:35:05.54#ibcon#read 4, iclass 29, count 0 2006.285.08:35:05.54#ibcon#about to read 5, iclass 29, count 0 2006.285.08:35:05.54#ibcon#read 5, iclass 29, count 0 2006.285.08:35:05.54#ibcon#about to read 6, iclass 29, count 0 2006.285.08:35:05.54#ibcon#read 6, iclass 29, count 0 2006.285.08:35:05.54#ibcon#end of sib2, iclass 29, count 0 2006.285.08:35:05.54#ibcon#*after write, iclass 29, count 0 2006.285.08:35:05.54#ibcon#*before return 0, iclass 29, count 0 2006.285.08:35:05.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:35:05.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.08:35:05.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.08:35:05.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.08:35:05.54$vck44/vblo=2,634.99 2006.285.08:35:05.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.08:35:05.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.08:35:05.54#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:05.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:35:05.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:35:05.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:35:05.54#ibcon#enter wrdev, iclass 31, count 0 2006.285.08:35:05.54#ibcon#first serial, iclass 31, count 0 2006.285.08:35:05.54#ibcon#enter sib2, iclass 31, count 0 2006.285.08:35:05.54#ibcon#flushed, iclass 31, count 0 2006.285.08:35:05.54#ibcon#about to write, iclass 31, count 0 2006.285.08:35:05.54#ibcon#wrote, iclass 31, count 0 2006.285.08:35:05.54#ibcon#about to read 3, iclass 31, count 0 2006.285.08:35:05.56#ibcon#read 3, iclass 31, count 0 2006.285.08:35:05.56#ibcon#about to read 4, iclass 31, count 0 2006.285.08:35:05.56#ibcon#read 4, iclass 31, count 0 2006.285.08:35:05.56#ibcon#about to read 5, iclass 31, count 0 2006.285.08:35:05.56#ibcon#read 5, iclass 31, count 0 2006.285.08:35:05.56#ibcon#about to read 6, iclass 31, count 0 2006.285.08:35:05.56#ibcon#read 6, iclass 31, count 0 2006.285.08:35:05.56#ibcon#end of sib2, iclass 31, count 0 2006.285.08:35:05.56#ibcon#*mode == 0, iclass 31, count 0 2006.285.08:35:05.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.08:35:05.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:35:05.56#ibcon#*before write, iclass 31, count 0 2006.285.08:35:05.56#ibcon#enter sib2, iclass 31, count 0 2006.285.08:35:05.56#ibcon#flushed, iclass 31, count 0 2006.285.08:35:05.56#ibcon#about to write, iclass 31, count 0 2006.285.08:35:05.56#ibcon#wrote, iclass 31, count 0 2006.285.08:35:05.56#ibcon#about to read 3, iclass 31, count 0 2006.285.08:35:05.60#ibcon#read 3, iclass 31, count 0 2006.285.08:35:05.60#ibcon#about to read 4, iclass 31, count 0 2006.285.08:35:05.60#ibcon#read 4, iclass 31, count 0 2006.285.08:35:05.60#ibcon#about to read 5, iclass 31, count 0 2006.285.08:35:05.60#ibcon#read 5, iclass 31, count 0 2006.285.08:35:05.60#ibcon#about to read 6, iclass 31, count 0 2006.285.08:35:05.60#ibcon#read 6, iclass 31, count 0 2006.285.08:35:05.60#ibcon#end of sib2, iclass 31, count 0 2006.285.08:35:05.60#ibcon#*after write, iclass 31, count 0 2006.285.08:35:05.60#ibcon#*before return 0, iclass 31, count 0 2006.285.08:35:05.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:35:05.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.08:35:05.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.08:35:05.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.08:35:05.60$vck44/vb=2,5 2006.285.08:35:05.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.08:35:05.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.08:35:05.60#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:05.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:35:05.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:35:05.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:35:05.66#ibcon#enter wrdev, iclass 33, count 2 2006.285.08:35:05.66#ibcon#first serial, iclass 33, count 2 2006.285.08:35:05.66#ibcon#enter sib2, iclass 33, count 2 2006.285.08:35:05.66#ibcon#flushed, iclass 33, count 2 2006.285.08:35:05.66#ibcon#about to write, iclass 33, count 2 2006.285.08:35:05.66#ibcon#wrote, iclass 33, count 2 2006.285.08:35:05.66#ibcon#about to read 3, iclass 33, count 2 2006.285.08:35:05.68#ibcon#read 3, iclass 33, count 2 2006.285.08:35:05.68#ibcon#about to read 4, iclass 33, count 2 2006.285.08:35:05.68#ibcon#read 4, iclass 33, count 2 2006.285.08:35:05.68#ibcon#about to read 5, iclass 33, count 2 2006.285.08:35:05.68#ibcon#read 5, iclass 33, count 2 2006.285.08:35:05.68#ibcon#about to read 6, iclass 33, count 2 2006.285.08:35:05.68#ibcon#read 6, iclass 33, count 2 2006.285.08:35:05.68#ibcon#end of sib2, iclass 33, count 2 2006.285.08:35:05.68#ibcon#*mode == 0, iclass 33, count 2 2006.285.08:35:05.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.08:35:05.68#ibcon#[27=AT02-05\r\n] 2006.285.08:35:05.68#ibcon#*before write, iclass 33, count 2 2006.285.08:35:05.68#ibcon#enter sib2, iclass 33, count 2 2006.285.08:35:05.68#ibcon#flushed, iclass 33, count 2 2006.285.08:35:05.68#ibcon#about to write, iclass 33, count 2 2006.285.08:35:05.68#ibcon#wrote, iclass 33, count 2 2006.285.08:35:05.68#ibcon#about to read 3, iclass 33, count 2 2006.285.08:35:05.71#ibcon#read 3, iclass 33, count 2 2006.285.08:35:05.71#ibcon#about to read 4, iclass 33, count 2 2006.285.08:35:05.71#ibcon#read 4, iclass 33, count 2 2006.285.08:35:05.71#ibcon#about to read 5, iclass 33, count 2 2006.285.08:35:05.71#ibcon#read 5, iclass 33, count 2 2006.285.08:35:05.71#ibcon#about to read 6, iclass 33, count 2 2006.285.08:35:05.71#ibcon#read 6, iclass 33, count 2 2006.285.08:35:05.71#ibcon#end of sib2, iclass 33, count 2 2006.285.08:35:05.71#ibcon#*after write, iclass 33, count 2 2006.285.08:35:05.71#ibcon#*before return 0, iclass 33, count 2 2006.285.08:35:05.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:35:05.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.08:35:05.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.08:35:05.71#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:05.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:35:05.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:35:05.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:35:05.83#ibcon#enter wrdev, iclass 33, count 0 2006.285.08:35:05.83#ibcon#first serial, iclass 33, count 0 2006.285.08:35:05.83#ibcon#enter sib2, iclass 33, count 0 2006.285.08:35:05.83#ibcon#flushed, iclass 33, count 0 2006.285.08:35:05.83#ibcon#about to write, iclass 33, count 0 2006.285.08:35:05.83#ibcon#wrote, iclass 33, count 0 2006.285.08:35:05.83#ibcon#about to read 3, iclass 33, count 0 2006.285.08:35:05.85#ibcon#read 3, iclass 33, count 0 2006.285.08:35:05.85#ibcon#about to read 4, iclass 33, count 0 2006.285.08:35:05.85#ibcon#read 4, iclass 33, count 0 2006.285.08:35:05.85#ibcon#about to read 5, iclass 33, count 0 2006.285.08:35:05.85#ibcon#read 5, iclass 33, count 0 2006.285.08:35:05.85#ibcon#about to read 6, iclass 33, count 0 2006.285.08:35:05.85#ibcon#read 6, iclass 33, count 0 2006.285.08:35:05.85#ibcon#end of sib2, iclass 33, count 0 2006.285.08:35:05.85#ibcon#*mode == 0, iclass 33, count 0 2006.285.08:35:05.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.08:35:05.85#ibcon#[27=USB\r\n] 2006.285.08:35:05.85#ibcon#*before write, iclass 33, count 0 2006.285.08:35:05.85#ibcon#enter sib2, iclass 33, count 0 2006.285.08:35:05.85#ibcon#flushed, iclass 33, count 0 2006.285.08:35:05.85#ibcon#about to write, iclass 33, count 0 2006.285.08:35:05.85#ibcon#wrote, iclass 33, count 0 2006.285.08:35:05.85#ibcon#about to read 3, iclass 33, count 0 2006.285.08:35:05.88#ibcon#read 3, iclass 33, count 0 2006.285.08:35:05.88#ibcon#about to read 4, iclass 33, count 0 2006.285.08:35:05.88#ibcon#read 4, iclass 33, count 0 2006.285.08:35:05.88#ibcon#about to read 5, iclass 33, count 0 2006.285.08:35:05.88#ibcon#read 5, iclass 33, count 0 2006.285.08:35:05.88#ibcon#about to read 6, iclass 33, count 0 2006.285.08:35:05.88#ibcon#read 6, iclass 33, count 0 2006.285.08:35:05.88#ibcon#end of sib2, iclass 33, count 0 2006.285.08:35:05.88#ibcon#*after write, iclass 33, count 0 2006.285.08:35:05.88#ibcon#*before return 0, iclass 33, count 0 2006.285.08:35:05.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:35:05.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.08:35:05.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.08:35:05.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.08:35:05.88$vck44/vblo=3,649.99 2006.285.08:35:05.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.08:35:05.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.08:35:05.88#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:05.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:35:05.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:35:05.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:35:05.88#ibcon#enter wrdev, iclass 35, count 0 2006.285.08:35:05.88#ibcon#first serial, iclass 35, count 0 2006.285.08:35:05.88#ibcon#enter sib2, iclass 35, count 0 2006.285.08:35:05.88#ibcon#flushed, iclass 35, count 0 2006.285.08:35:05.88#ibcon#about to write, iclass 35, count 0 2006.285.08:35:05.88#ibcon#wrote, iclass 35, count 0 2006.285.08:35:05.88#ibcon#about to read 3, iclass 35, count 0 2006.285.08:35:05.90#ibcon#read 3, iclass 35, count 0 2006.285.08:35:05.90#ibcon#about to read 4, iclass 35, count 0 2006.285.08:35:05.90#ibcon#read 4, iclass 35, count 0 2006.285.08:35:05.90#ibcon#about to read 5, iclass 35, count 0 2006.285.08:35:05.90#ibcon#read 5, iclass 35, count 0 2006.285.08:35:05.90#ibcon#about to read 6, iclass 35, count 0 2006.285.08:35:05.90#ibcon#read 6, iclass 35, count 0 2006.285.08:35:05.90#ibcon#end of sib2, iclass 35, count 0 2006.285.08:35:05.90#ibcon#*mode == 0, iclass 35, count 0 2006.285.08:35:05.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.08:35:05.90#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:35:05.90#ibcon#*before write, iclass 35, count 0 2006.285.08:35:05.90#ibcon#enter sib2, iclass 35, count 0 2006.285.08:35:05.90#ibcon#flushed, iclass 35, count 0 2006.285.08:35:05.90#ibcon#about to write, iclass 35, count 0 2006.285.08:35:05.90#ibcon#wrote, iclass 35, count 0 2006.285.08:35:05.90#ibcon#about to read 3, iclass 35, count 0 2006.285.08:35:05.94#ibcon#read 3, iclass 35, count 0 2006.285.08:35:05.94#ibcon#about to read 4, iclass 35, count 0 2006.285.08:35:05.94#ibcon#read 4, iclass 35, count 0 2006.285.08:35:05.94#ibcon#about to read 5, iclass 35, count 0 2006.285.08:35:05.94#ibcon#read 5, iclass 35, count 0 2006.285.08:35:05.94#ibcon#about to read 6, iclass 35, count 0 2006.285.08:35:05.94#ibcon#read 6, iclass 35, count 0 2006.285.08:35:05.94#ibcon#end of sib2, iclass 35, count 0 2006.285.08:35:05.94#ibcon#*after write, iclass 35, count 0 2006.285.08:35:05.94#ibcon#*before return 0, iclass 35, count 0 2006.285.08:35:05.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:35:05.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.08:35:05.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.08:35:05.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.08:35:05.94$vck44/vb=3,4 2006.285.08:35:05.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.08:35:05.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.08:35:05.94#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:05.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:35:06.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:35:06.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:35:06.00#ibcon#enter wrdev, iclass 37, count 2 2006.285.08:35:06.00#ibcon#first serial, iclass 37, count 2 2006.285.08:35:06.00#ibcon#enter sib2, iclass 37, count 2 2006.285.08:35:06.00#ibcon#flushed, iclass 37, count 2 2006.285.08:35:06.00#ibcon#about to write, iclass 37, count 2 2006.285.08:35:06.00#ibcon#wrote, iclass 37, count 2 2006.285.08:35:06.00#ibcon#about to read 3, iclass 37, count 2 2006.285.08:35:06.02#ibcon#read 3, iclass 37, count 2 2006.285.08:35:06.02#ibcon#about to read 4, iclass 37, count 2 2006.285.08:35:06.02#ibcon#read 4, iclass 37, count 2 2006.285.08:35:06.02#ibcon#about to read 5, iclass 37, count 2 2006.285.08:35:06.02#ibcon#read 5, iclass 37, count 2 2006.285.08:35:06.02#ibcon#about to read 6, iclass 37, count 2 2006.285.08:35:06.02#ibcon#read 6, iclass 37, count 2 2006.285.08:35:06.02#ibcon#end of sib2, iclass 37, count 2 2006.285.08:35:06.02#ibcon#*mode == 0, iclass 37, count 2 2006.285.08:35:06.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.08:35:06.02#ibcon#[27=AT03-04\r\n] 2006.285.08:35:06.02#ibcon#*before write, iclass 37, count 2 2006.285.08:35:06.02#ibcon#enter sib2, iclass 37, count 2 2006.285.08:35:06.02#ibcon#flushed, iclass 37, count 2 2006.285.08:35:06.02#ibcon#about to write, iclass 37, count 2 2006.285.08:35:06.02#ibcon#wrote, iclass 37, count 2 2006.285.08:35:06.02#ibcon#about to read 3, iclass 37, count 2 2006.285.08:35:06.05#ibcon#read 3, iclass 37, count 2 2006.285.08:35:06.05#ibcon#about to read 4, iclass 37, count 2 2006.285.08:35:06.05#ibcon#read 4, iclass 37, count 2 2006.285.08:35:06.05#ibcon#about to read 5, iclass 37, count 2 2006.285.08:35:06.05#ibcon#read 5, iclass 37, count 2 2006.285.08:35:06.05#ibcon#about to read 6, iclass 37, count 2 2006.285.08:35:06.05#ibcon#read 6, iclass 37, count 2 2006.285.08:35:06.05#ibcon#end of sib2, iclass 37, count 2 2006.285.08:35:06.05#ibcon#*after write, iclass 37, count 2 2006.285.08:35:06.05#ibcon#*before return 0, iclass 37, count 2 2006.285.08:35:06.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:35:06.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.08:35:06.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.08:35:06.05#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:06.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:35:06.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:35:06.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:35:06.17#ibcon#enter wrdev, iclass 37, count 0 2006.285.08:35:06.17#ibcon#first serial, iclass 37, count 0 2006.285.08:35:06.17#ibcon#enter sib2, iclass 37, count 0 2006.285.08:35:06.17#ibcon#flushed, iclass 37, count 0 2006.285.08:35:06.17#ibcon#about to write, iclass 37, count 0 2006.285.08:35:06.17#ibcon#wrote, iclass 37, count 0 2006.285.08:35:06.17#ibcon#about to read 3, iclass 37, count 0 2006.285.08:35:06.19#ibcon#read 3, iclass 37, count 0 2006.285.08:35:06.19#ibcon#about to read 4, iclass 37, count 0 2006.285.08:35:06.19#ibcon#read 4, iclass 37, count 0 2006.285.08:35:06.19#ibcon#about to read 5, iclass 37, count 0 2006.285.08:35:06.19#ibcon#read 5, iclass 37, count 0 2006.285.08:35:06.19#ibcon#about to read 6, iclass 37, count 0 2006.285.08:35:06.19#ibcon#read 6, iclass 37, count 0 2006.285.08:35:06.19#ibcon#end of sib2, iclass 37, count 0 2006.285.08:35:06.19#ibcon#*mode == 0, iclass 37, count 0 2006.285.08:35:06.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.08:35:06.19#ibcon#[27=USB\r\n] 2006.285.08:35:06.19#ibcon#*before write, iclass 37, count 0 2006.285.08:35:06.19#ibcon#enter sib2, iclass 37, count 0 2006.285.08:35:06.19#ibcon#flushed, iclass 37, count 0 2006.285.08:35:06.19#ibcon#about to write, iclass 37, count 0 2006.285.08:35:06.19#ibcon#wrote, iclass 37, count 0 2006.285.08:35:06.19#ibcon#about to read 3, iclass 37, count 0 2006.285.08:35:06.22#ibcon#read 3, iclass 37, count 0 2006.285.08:35:06.22#ibcon#about to read 4, iclass 37, count 0 2006.285.08:35:06.22#ibcon#read 4, iclass 37, count 0 2006.285.08:35:06.22#ibcon#about to read 5, iclass 37, count 0 2006.285.08:35:06.22#ibcon#read 5, iclass 37, count 0 2006.285.08:35:06.22#ibcon#about to read 6, iclass 37, count 0 2006.285.08:35:06.22#ibcon#read 6, iclass 37, count 0 2006.285.08:35:06.22#ibcon#end of sib2, iclass 37, count 0 2006.285.08:35:06.22#ibcon#*after write, iclass 37, count 0 2006.285.08:35:06.22#ibcon#*before return 0, iclass 37, count 0 2006.285.08:35:06.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:35:06.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.08:35:06.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.08:35:06.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.08:35:06.22$vck44/vblo=4,679.99 2006.285.08:35:06.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.08:35:06.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.08:35:06.22#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:06.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:35:06.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:35:06.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:35:06.22#ibcon#enter wrdev, iclass 39, count 0 2006.285.08:35:06.22#ibcon#first serial, iclass 39, count 0 2006.285.08:35:06.22#ibcon#enter sib2, iclass 39, count 0 2006.285.08:35:06.22#ibcon#flushed, iclass 39, count 0 2006.285.08:35:06.22#ibcon#about to write, iclass 39, count 0 2006.285.08:35:06.22#ibcon#wrote, iclass 39, count 0 2006.285.08:35:06.22#ibcon#about to read 3, iclass 39, count 0 2006.285.08:35:06.24#ibcon#read 3, iclass 39, count 0 2006.285.08:35:06.24#ibcon#about to read 4, iclass 39, count 0 2006.285.08:35:06.24#ibcon#read 4, iclass 39, count 0 2006.285.08:35:06.24#ibcon#about to read 5, iclass 39, count 0 2006.285.08:35:06.24#ibcon#read 5, iclass 39, count 0 2006.285.08:35:06.24#ibcon#about to read 6, iclass 39, count 0 2006.285.08:35:06.24#ibcon#read 6, iclass 39, count 0 2006.285.08:35:06.24#ibcon#end of sib2, iclass 39, count 0 2006.285.08:35:06.24#ibcon#*mode == 0, iclass 39, count 0 2006.285.08:35:06.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.08:35:06.24#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:35:06.24#ibcon#*before write, iclass 39, count 0 2006.285.08:35:06.24#ibcon#enter sib2, iclass 39, count 0 2006.285.08:35:06.24#ibcon#flushed, iclass 39, count 0 2006.285.08:35:06.24#ibcon#about to write, iclass 39, count 0 2006.285.08:35:06.24#ibcon#wrote, iclass 39, count 0 2006.285.08:35:06.24#ibcon#about to read 3, iclass 39, count 0 2006.285.08:35:06.28#ibcon#read 3, iclass 39, count 0 2006.285.08:35:06.28#ibcon#about to read 4, iclass 39, count 0 2006.285.08:35:06.28#ibcon#read 4, iclass 39, count 0 2006.285.08:35:06.28#ibcon#about to read 5, iclass 39, count 0 2006.285.08:35:06.28#ibcon#read 5, iclass 39, count 0 2006.285.08:35:06.28#ibcon#about to read 6, iclass 39, count 0 2006.285.08:35:06.28#ibcon#read 6, iclass 39, count 0 2006.285.08:35:06.28#ibcon#end of sib2, iclass 39, count 0 2006.285.08:35:06.28#ibcon#*after write, iclass 39, count 0 2006.285.08:35:06.28#ibcon#*before return 0, iclass 39, count 0 2006.285.08:35:06.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:35:06.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.08:35:06.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.08:35:06.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.08:35:06.28$vck44/vb=4,5 2006.285.08:35:06.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.08:35:06.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.08:35:06.28#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:06.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:35:06.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:35:06.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:35:06.34#ibcon#enter wrdev, iclass 3, count 2 2006.285.08:35:06.34#ibcon#first serial, iclass 3, count 2 2006.285.08:35:06.34#ibcon#enter sib2, iclass 3, count 2 2006.285.08:35:06.34#ibcon#flushed, iclass 3, count 2 2006.285.08:35:06.34#ibcon#about to write, iclass 3, count 2 2006.285.08:35:06.34#ibcon#wrote, iclass 3, count 2 2006.285.08:35:06.34#ibcon#about to read 3, iclass 3, count 2 2006.285.08:35:06.36#ibcon#read 3, iclass 3, count 2 2006.285.08:35:06.36#ibcon#about to read 4, iclass 3, count 2 2006.285.08:35:06.36#ibcon#read 4, iclass 3, count 2 2006.285.08:35:06.36#ibcon#about to read 5, iclass 3, count 2 2006.285.08:35:06.36#ibcon#read 5, iclass 3, count 2 2006.285.08:35:06.36#ibcon#about to read 6, iclass 3, count 2 2006.285.08:35:06.36#ibcon#read 6, iclass 3, count 2 2006.285.08:35:06.36#ibcon#end of sib2, iclass 3, count 2 2006.285.08:35:06.36#ibcon#*mode == 0, iclass 3, count 2 2006.285.08:35:06.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.08:35:06.36#ibcon#[27=AT04-05\r\n] 2006.285.08:35:06.36#ibcon#*before write, iclass 3, count 2 2006.285.08:35:06.36#ibcon#enter sib2, iclass 3, count 2 2006.285.08:35:06.36#ibcon#flushed, iclass 3, count 2 2006.285.08:35:06.36#ibcon#about to write, iclass 3, count 2 2006.285.08:35:06.36#ibcon#wrote, iclass 3, count 2 2006.285.08:35:06.36#ibcon#about to read 3, iclass 3, count 2 2006.285.08:35:06.39#ibcon#read 3, iclass 3, count 2 2006.285.08:35:06.39#ibcon#about to read 4, iclass 3, count 2 2006.285.08:35:06.39#ibcon#read 4, iclass 3, count 2 2006.285.08:35:06.39#ibcon#about to read 5, iclass 3, count 2 2006.285.08:35:06.39#ibcon#read 5, iclass 3, count 2 2006.285.08:35:06.39#ibcon#about to read 6, iclass 3, count 2 2006.285.08:35:06.39#ibcon#read 6, iclass 3, count 2 2006.285.08:35:06.39#ibcon#end of sib2, iclass 3, count 2 2006.285.08:35:06.39#ibcon#*after write, iclass 3, count 2 2006.285.08:35:06.39#ibcon#*before return 0, iclass 3, count 2 2006.285.08:35:06.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:35:06.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.08:35:06.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.08:35:06.39#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:06.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:35:06.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:35:06.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:35:06.51#ibcon#enter wrdev, iclass 3, count 0 2006.285.08:35:06.51#ibcon#first serial, iclass 3, count 0 2006.285.08:35:06.51#ibcon#enter sib2, iclass 3, count 0 2006.285.08:35:06.51#ibcon#flushed, iclass 3, count 0 2006.285.08:35:06.51#ibcon#about to write, iclass 3, count 0 2006.285.08:35:06.51#ibcon#wrote, iclass 3, count 0 2006.285.08:35:06.51#ibcon#about to read 3, iclass 3, count 0 2006.285.08:35:06.53#ibcon#read 3, iclass 3, count 0 2006.285.08:35:06.53#ibcon#about to read 4, iclass 3, count 0 2006.285.08:35:06.53#ibcon#read 4, iclass 3, count 0 2006.285.08:35:06.53#ibcon#about to read 5, iclass 3, count 0 2006.285.08:35:06.53#ibcon#read 5, iclass 3, count 0 2006.285.08:35:06.53#ibcon#about to read 6, iclass 3, count 0 2006.285.08:35:06.53#ibcon#read 6, iclass 3, count 0 2006.285.08:35:06.53#ibcon#end of sib2, iclass 3, count 0 2006.285.08:35:06.53#ibcon#*mode == 0, iclass 3, count 0 2006.285.08:35:06.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.08:35:06.53#ibcon#[27=USB\r\n] 2006.285.08:35:06.53#ibcon#*before write, iclass 3, count 0 2006.285.08:35:06.53#ibcon#enter sib2, iclass 3, count 0 2006.285.08:35:06.53#ibcon#flushed, iclass 3, count 0 2006.285.08:35:06.53#ibcon#about to write, iclass 3, count 0 2006.285.08:35:06.53#ibcon#wrote, iclass 3, count 0 2006.285.08:35:06.53#ibcon#about to read 3, iclass 3, count 0 2006.285.08:35:06.56#ibcon#read 3, iclass 3, count 0 2006.285.08:35:06.56#ibcon#about to read 4, iclass 3, count 0 2006.285.08:35:06.56#ibcon#read 4, iclass 3, count 0 2006.285.08:35:06.56#ibcon#about to read 5, iclass 3, count 0 2006.285.08:35:06.56#ibcon#read 5, iclass 3, count 0 2006.285.08:35:06.56#ibcon#about to read 6, iclass 3, count 0 2006.285.08:35:06.56#ibcon#read 6, iclass 3, count 0 2006.285.08:35:06.56#ibcon#end of sib2, iclass 3, count 0 2006.285.08:35:06.56#ibcon#*after write, iclass 3, count 0 2006.285.08:35:06.56#ibcon#*before return 0, iclass 3, count 0 2006.285.08:35:06.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:35:06.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.08:35:06.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.08:35:06.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.08:35:06.56$vck44/vblo=5,709.99 2006.285.08:35:06.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.08:35:06.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.08:35:06.56#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:06.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:35:06.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:35:06.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:35:06.56#ibcon#enter wrdev, iclass 5, count 0 2006.285.08:35:06.56#ibcon#first serial, iclass 5, count 0 2006.285.08:35:06.56#ibcon#enter sib2, iclass 5, count 0 2006.285.08:35:06.56#ibcon#flushed, iclass 5, count 0 2006.285.08:35:06.56#ibcon#about to write, iclass 5, count 0 2006.285.08:35:06.56#ibcon#wrote, iclass 5, count 0 2006.285.08:35:06.56#ibcon#about to read 3, iclass 5, count 0 2006.285.08:35:06.58#ibcon#read 3, iclass 5, count 0 2006.285.08:35:06.58#ibcon#about to read 4, iclass 5, count 0 2006.285.08:35:06.58#ibcon#read 4, iclass 5, count 0 2006.285.08:35:06.58#ibcon#about to read 5, iclass 5, count 0 2006.285.08:35:06.58#ibcon#read 5, iclass 5, count 0 2006.285.08:35:06.58#ibcon#about to read 6, iclass 5, count 0 2006.285.08:35:06.58#ibcon#read 6, iclass 5, count 0 2006.285.08:35:06.58#ibcon#end of sib2, iclass 5, count 0 2006.285.08:35:06.58#ibcon#*mode == 0, iclass 5, count 0 2006.285.08:35:06.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.08:35:06.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:35:06.58#ibcon#*before write, iclass 5, count 0 2006.285.08:35:06.58#ibcon#enter sib2, iclass 5, count 0 2006.285.08:35:06.58#ibcon#flushed, iclass 5, count 0 2006.285.08:35:06.58#ibcon#about to write, iclass 5, count 0 2006.285.08:35:06.58#ibcon#wrote, iclass 5, count 0 2006.285.08:35:06.58#ibcon#about to read 3, iclass 5, count 0 2006.285.08:35:06.62#ibcon#read 3, iclass 5, count 0 2006.285.08:35:06.62#ibcon#about to read 4, iclass 5, count 0 2006.285.08:35:06.62#ibcon#read 4, iclass 5, count 0 2006.285.08:35:06.62#ibcon#about to read 5, iclass 5, count 0 2006.285.08:35:06.62#ibcon#read 5, iclass 5, count 0 2006.285.08:35:06.62#ibcon#about to read 6, iclass 5, count 0 2006.285.08:35:06.62#ibcon#read 6, iclass 5, count 0 2006.285.08:35:06.62#ibcon#end of sib2, iclass 5, count 0 2006.285.08:35:06.62#ibcon#*after write, iclass 5, count 0 2006.285.08:35:06.62#ibcon#*before return 0, iclass 5, count 0 2006.285.08:35:06.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:35:06.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.08:35:06.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.08:35:06.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.08:35:06.62$vck44/vb=5,4 2006.285.08:35:06.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.08:35:06.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.08:35:06.62#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:06.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.08:35:06.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.08:35:06.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.08:35:06.68#ibcon#enter wrdev, iclass 7, count 2 2006.285.08:35:06.68#ibcon#first serial, iclass 7, count 2 2006.285.08:35:06.68#ibcon#enter sib2, iclass 7, count 2 2006.285.08:35:06.68#ibcon#flushed, iclass 7, count 2 2006.285.08:35:06.68#ibcon#about to write, iclass 7, count 2 2006.285.08:35:06.68#ibcon#wrote, iclass 7, count 2 2006.285.08:35:06.68#ibcon#about to read 3, iclass 7, count 2 2006.285.08:35:06.70#ibcon#read 3, iclass 7, count 2 2006.285.08:35:06.70#ibcon#about to read 4, iclass 7, count 2 2006.285.08:35:06.70#ibcon#read 4, iclass 7, count 2 2006.285.08:35:06.70#ibcon#about to read 5, iclass 7, count 2 2006.285.08:35:06.70#ibcon#read 5, iclass 7, count 2 2006.285.08:35:06.70#ibcon#about to read 6, iclass 7, count 2 2006.285.08:35:06.70#ibcon#read 6, iclass 7, count 2 2006.285.08:35:06.70#ibcon#end of sib2, iclass 7, count 2 2006.285.08:35:06.70#ibcon#*mode == 0, iclass 7, count 2 2006.285.08:35:06.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.08:35:06.70#ibcon#[27=AT05-04\r\n] 2006.285.08:35:06.70#ibcon#*before write, iclass 7, count 2 2006.285.08:35:06.70#ibcon#enter sib2, iclass 7, count 2 2006.285.08:35:06.70#ibcon#flushed, iclass 7, count 2 2006.285.08:35:06.70#ibcon#about to write, iclass 7, count 2 2006.285.08:35:06.70#ibcon#wrote, iclass 7, count 2 2006.285.08:35:06.70#ibcon#about to read 3, iclass 7, count 2 2006.285.08:35:06.73#ibcon#read 3, iclass 7, count 2 2006.285.08:35:06.73#ibcon#about to read 4, iclass 7, count 2 2006.285.08:35:06.73#ibcon#read 4, iclass 7, count 2 2006.285.08:35:06.73#ibcon#about to read 5, iclass 7, count 2 2006.285.08:35:06.73#ibcon#read 5, iclass 7, count 2 2006.285.08:35:06.73#ibcon#about to read 6, iclass 7, count 2 2006.285.08:35:06.73#ibcon#read 6, iclass 7, count 2 2006.285.08:35:06.73#ibcon#end of sib2, iclass 7, count 2 2006.285.08:35:06.73#ibcon#*after write, iclass 7, count 2 2006.285.08:35:06.73#ibcon#*before return 0, iclass 7, count 2 2006.285.08:35:06.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.08:35:06.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.08:35:06.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.08:35:06.73#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:06.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.08:35:06.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.08:35:06.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.08:35:06.85#ibcon#enter wrdev, iclass 7, count 0 2006.285.08:35:06.85#ibcon#first serial, iclass 7, count 0 2006.285.08:35:06.85#ibcon#enter sib2, iclass 7, count 0 2006.285.08:35:06.85#ibcon#flushed, iclass 7, count 0 2006.285.08:35:06.85#ibcon#about to write, iclass 7, count 0 2006.285.08:35:06.85#ibcon#wrote, iclass 7, count 0 2006.285.08:35:06.85#ibcon#about to read 3, iclass 7, count 0 2006.285.08:35:06.87#ibcon#read 3, iclass 7, count 0 2006.285.08:35:06.87#ibcon#about to read 4, iclass 7, count 0 2006.285.08:35:06.87#ibcon#read 4, iclass 7, count 0 2006.285.08:35:06.87#ibcon#about to read 5, iclass 7, count 0 2006.285.08:35:06.87#ibcon#read 5, iclass 7, count 0 2006.285.08:35:06.87#ibcon#about to read 6, iclass 7, count 0 2006.285.08:35:06.87#ibcon#read 6, iclass 7, count 0 2006.285.08:35:06.87#ibcon#end of sib2, iclass 7, count 0 2006.285.08:35:06.87#ibcon#*mode == 0, iclass 7, count 0 2006.285.08:35:06.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.08:35:06.87#ibcon#[27=USB\r\n] 2006.285.08:35:06.87#ibcon#*before write, iclass 7, count 0 2006.285.08:35:06.87#ibcon#enter sib2, iclass 7, count 0 2006.285.08:35:06.87#ibcon#flushed, iclass 7, count 0 2006.285.08:35:06.87#ibcon#about to write, iclass 7, count 0 2006.285.08:35:06.87#ibcon#wrote, iclass 7, count 0 2006.285.08:35:06.87#ibcon#about to read 3, iclass 7, count 0 2006.285.08:35:06.90#ibcon#read 3, iclass 7, count 0 2006.285.08:35:06.90#ibcon#about to read 4, iclass 7, count 0 2006.285.08:35:06.90#ibcon#read 4, iclass 7, count 0 2006.285.08:35:06.90#ibcon#about to read 5, iclass 7, count 0 2006.285.08:35:06.90#ibcon#read 5, iclass 7, count 0 2006.285.08:35:06.90#ibcon#about to read 6, iclass 7, count 0 2006.285.08:35:06.90#ibcon#read 6, iclass 7, count 0 2006.285.08:35:06.90#ibcon#end of sib2, iclass 7, count 0 2006.285.08:35:06.90#ibcon#*after write, iclass 7, count 0 2006.285.08:35:06.90#ibcon#*before return 0, iclass 7, count 0 2006.285.08:35:06.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.08:35:06.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.08:35:06.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.08:35:06.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.08:35:06.90$vck44/vblo=6,719.99 2006.285.08:35:06.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.08:35:06.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.08:35:06.90#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:06.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:35:06.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:35:06.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:35:06.90#ibcon#enter wrdev, iclass 11, count 0 2006.285.08:35:06.90#ibcon#first serial, iclass 11, count 0 2006.285.08:35:06.90#ibcon#enter sib2, iclass 11, count 0 2006.285.08:35:06.90#ibcon#flushed, iclass 11, count 0 2006.285.08:35:06.90#ibcon#about to write, iclass 11, count 0 2006.285.08:35:06.90#ibcon#wrote, iclass 11, count 0 2006.285.08:35:06.90#ibcon#about to read 3, iclass 11, count 0 2006.285.08:35:06.92#ibcon#read 3, iclass 11, count 0 2006.285.08:35:06.92#ibcon#about to read 4, iclass 11, count 0 2006.285.08:35:06.92#ibcon#read 4, iclass 11, count 0 2006.285.08:35:06.92#ibcon#about to read 5, iclass 11, count 0 2006.285.08:35:06.92#ibcon#read 5, iclass 11, count 0 2006.285.08:35:06.92#ibcon#about to read 6, iclass 11, count 0 2006.285.08:35:06.92#ibcon#read 6, iclass 11, count 0 2006.285.08:35:06.92#ibcon#end of sib2, iclass 11, count 0 2006.285.08:35:06.92#ibcon#*mode == 0, iclass 11, count 0 2006.285.08:35:06.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.08:35:06.92#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:35:06.92#ibcon#*before write, iclass 11, count 0 2006.285.08:35:06.92#ibcon#enter sib2, iclass 11, count 0 2006.285.08:35:06.92#ibcon#flushed, iclass 11, count 0 2006.285.08:35:06.92#ibcon#about to write, iclass 11, count 0 2006.285.08:35:06.92#ibcon#wrote, iclass 11, count 0 2006.285.08:35:06.92#ibcon#about to read 3, iclass 11, count 0 2006.285.08:35:06.96#ibcon#read 3, iclass 11, count 0 2006.285.08:35:06.96#ibcon#about to read 4, iclass 11, count 0 2006.285.08:35:06.96#ibcon#read 4, iclass 11, count 0 2006.285.08:35:06.96#ibcon#about to read 5, iclass 11, count 0 2006.285.08:35:06.96#ibcon#read 5, iclass 11, count 0 2006.285.08:35:06.96#ibcon#about to read 6, iclass 11, count 0 2006.285.08:35:06.96#ibcon#read 6, iclass 11, count 0 2006.285.08:35:06.96#ibcon#end of sib2, iclass 11, count 0 2006.285.08:35:06.96#ibcon#*after write, iclass 11, count 0 2006.285.08:35:06.96#ibcon#*before return 0, iclass 11, count 0 2006.285.08:35:06.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:35:06.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.08:35:06.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.08:35:06.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.08:35:06.96$vck44/vb=6,3 2006.285.08:35:06.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.08:35:06.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.08:35:06.96#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:06.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:35:07.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:35:07.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:35:07.02#ibcon#enter wrdev, iclass 13, count 2 2006.285.08:35:07.02#ibcon#first serial, iclass 13, count 2 2006.285.08:35:07.02#ibcon#enter sib2, iclass 13, count 2 2006.285.08:35:07.02#ibcon#flushed, iclass 13, count 2 2006.285.08:35:07.02#ibcon#about to write, iclass 13, count 2 2006.285.08:35:07.02#ibcon#wrote, iclass 13, count 2 2006.285.08:35:07.02#ibcon#about to read 3, iclass 13, count 2 2006.285.08:35:07.04#ibcon#read 3, iclass 13, count 2 2006.285.08:35:07.04#ibcon#about to read 4, iclass 13, count 2 2006.285.08:35:07.04#ibcon#read 4, iclass 13, count 2 2006.285.08:35:07.04#ibcon#about to read 5, iclass 13, count 2 2006.285.08:35:07.04#ibcon#read 5, iclass 13, count 2 2006.285.08:35:07.04#ibcon#about to read 6, iclass 13, count 2 2006.285.08:35:07.04#ibcon#read 6, iclass 13, count 2 2006.285.08:35:07.04#ibcon#end of sib2, iclass 13, count 2 2006.285.08:35:07.04#ibcon#*mode == 0, iclass 13, count 2 2006.285.08:35:07.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.08:35:07.04#ibcon#[27=AT06-03\r\n] 2006.285.08:35:07.04#ibcon#*before write, iclass 13, count 2 2006.285.08:35:07.04#ibcon#enter sib2, iclass 13, count 2 2006.285.08:35:07.04#ibcon#flushed, iclass 13, count 2 2006.285.08:35:07.04#ibcon#about to write, iclass 13, count 2 2006.285.08:35:07.04#ibcon#wrote, iclass 13, count 2 2006.285.08:35:07.04#ibcon#about to read 3, iclass 13, count 2 2006.285.08:35:07.07#ibcon#read 3, iclass 13, count 2 2006.285.08:35:07.07#ibcon#about to read 4, iclass 13, count 2 2006.285.08:35:07.07#ibcon#read 4, iclass 13, count 2 2006.285.08:35:07.07#ibcon#about to read 5, iclass 13, count 2 2006.285.08:35:07.07#ibcon#read 5, iclass 13, count 2 2006.285.08:35:07.07#ibcon#about to read 6, iclass 13, count 2 2006.285.08:35:07.07#ibcon#read 6, iclass 13, count 2 2006.285.08:35:07.07#ibcon#end of sib2, iclass 13, count 2 2006.285.08:35:07.07#ibcon#*after write, iclass 13, count 2 2006.285.08:35:07.07#ibcon#*before return 0, iclass 13, count 2 2006.285.08:35:07.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:35:07.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.08:35:07.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.08:35:07.07#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:07.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:35:07.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:35:07.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:35:07.19#ibcon#enter wrdev, iclass 13, count 0 2006.285.08:35:07.19#ibcon#first serial, iclass 13, count 0 2006.285.08:35:07.19#ibcon#enter sib2, iclass 13, count 0 2006.285.08:35:07.19#ibcon#flushed, iclass 13, count 0 2006.285.08:35:07.19#ibcon#about to write, iclass 13, count 0 2006.285.08:35:07.19#ibcon#wrote, iclass 13, count 0 2006.285.08:35:07.19#ibcon#about to read 3, iclass 13, count 0 2006.285.08:35:07.21#ibcon#read 3, iclass 13, count 0 2006.285.08:35:07.21#ibcon#about to read 4, iclass 13, count 0 2006.285.08:35:07.21#ibcon#read 4, iclass 13, count 0 2006.285.08:35:07.21#ibcon#about to read 5, iclass 13, count 0 2006.285.08:35:07.21#ibcon#read 5, iclass 13, count 0 2006.285.08:35:07.21#ibcon#about to read 6, iclass 13, count 0 2006.285.08:35:07.21#ibcon#read 6, iclass 13, count 0 2006.285.08:35:07.21#ibcon#end of sib2, iclass 13, count 0 2006.285.08:35:07.21#ibcon#*mode == 0, iclass 13, count 0 2006.285.08:35:07.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.08:35:07.21#ibcon#[27=USB\r\n] 2006.285.08:35:07.21#ibcon#*before write, iclass 13, count 0 2006.285.08:35:07.21#ibcon#enter sib2, iclass 13, count 0 2006.285.08:35:07.21#ibcon#flushed, iclass 13, count 0 2006.285.08:35:07.21#ibcon#about to write, iclass 13, count 0 2006.285.08:35:07.21#ibcon#wrote, iclass 13, count 0 2006.285.08:35:07.21#ibcon#about to read 3, iclass 13, count 0 2006.285.08:35:07.24#ibcon#read 3, iclass 13, count 0 2006.285.08:35:07.24#ibcon#about to read 4, iclass 13, count 0 2006.285.08:35:07.24#ibcon#read 4, iclass 13, count 0 2006.285.08:35:07.24#ibcon#about to read 5, iclass 13, count 0 2006.285.08:35:07.24#ibcon#read 5, iclass 13, count 0 2006.285.08:35:07.24#ibcon#about to read 6, iclass 13, count 0 2006.285.08:35:07.24#ibcon#read 6, iclass 13, count 0 2006.285.08:35:07.24#ibcon#end of sib2, iclass 13, count 0 2006.285.08:35:07.24#ibcon#*after write, iclass 13, count 0 2006.285.08:35:07.24#ibcon#*before return 0, iclass 13, count 0 2006.285.08:35:07.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:35:07.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.08:35:07.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.08:35:07.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.08:35:07.24$vck44/vblo=7,734.99 2006.285.08:35:07.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.08:35:07.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.08:35:07.24#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:07.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:35:07.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:35:07.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:35:07.24#ibcon#enter wrdev, iclass 15, count 0 2006.285.08:35:07.24#ibcon#first serial, iclass 15, count 0 2006.285.08:35:07.24#ibcon#enter sib2, iclass 15, count 0 2006.285.08:35:07.24#ibcon#flushed, iclass 15, count 0 2006.285.08:35:07.24#ibcon#about to write, iclass 15, count 0 2006.285.08:35:07.24#ibcon#wrote, iclass 15, count 0 2006.285.08:35:07.24#ibcon#about to read 3, iclass 15, count 0 2006.285.08:35:07.26#ibcon#read 3, iclass 15, count 0 2006.285.08:35:07.26#ibcon#about to read 4, iclass 15, count 0 2006.285.08:35:07.26#ibcon#read 4, iclass 15, count 0 2006.285.08:35:07.26#ibcon#about to read 5, iclass 15, count 0 2006.285.08:35:07.26#ibcon#read 5, iclass 15, count 0 2006.285.08:35:07.26#ibcon#about to read 6, iclass 15, count 0 2006.285.08:35:07.26#ibcon#read 6, iclass 15, count 0 2006.285.08:35:07.26#ibcon#end of sib2, iclass 15, count 0 2006.285.08:35:07.26#ibcon#*mode == 0, iclass 15, count 0 2006.285.08:35:07.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.08:35:07.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:35:07.26#ibcon#*before write, iclass 15, count 0 2006.285.08:35:07.26#ibcon#enter sib2, iclass 15, count 0 2006.285.08:35:07.26#ibcon#flushed, iclass 15, count 0 2006.285.08:35:07.26#ibcon#about to write, iclass 15, count 0 2006.285.08:35:07.26#ibcon#wrote, iclass 15, count 0 2006.285.08:35:07.26#ibcon#about to read 3, iclass 15, count 0 2006.285.08:35:07.30#ibcon#read 3, iclass 15, count 0 2006.285.08:35:07.30#ibcon#about to read 4, iclass 15, count 0 2006.285.08:35:07.30#ibcon#read 4, iclass 15, count 0 2006.285.08:35:07.30#ibcon#about to read 5, iclass 15, count 0 2006.285.08:35:07.30#ibcon#read 5, iclass 15, count 0 2006.285.08:35:07.30#ibcon#about to read 6, iclass 15, count 0 2006.285.08:35:07.30#ibcon#read 6, iclass 15, count 0 2006.285.08:35:07.30#ibcon#end of sib2, iclass 15, count 0 2006.285.08:35:07.30#ibcon#*after write, iclass 15, count 0 2006.285.08:35:07.30#ibcon#*before return 0, iclass 15, count 0 2006.285.08:35:07.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:35:07.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.08:35:07.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.08:35:07.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.08:35:07.30$vck44/vb=7,4 2006.285.08:35:07.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.08:35:07.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.08:35:07.30#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:07.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:35:07.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:35:07.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:35:07.36#ibcon#enter wrdev, iclass 17, count 2 2006.285.08:35:07.36#ibcon#first serial, iclass 17, count 2 2006.285.08:35:07.36#ibcon#enter sib2, iclass 17, count 2 2006.285.08:35:07.36#ibcon#flushed, iclass 17, count 2 2006.285.08:35:07.36#ibcon#about to write, iclass 17, count 2 2006.285.08:35:07.36#ibcon#wrote, iclass 17, count 2 2006.285.08:35:07.36#ibcon#about to read 3, iclass 17, count 2 2006.285.08:35:07.38#ibcon#read 3, iclass 17, count 2 2006.285.08:35:07.38#ibcon#about to read 4, iclass 17, count 2 2006.285.08:35:07.38#ibcon#read 4, iclass 17, count 2 2006.285.08:35:07.38#ibcon#about to read 5, iclass 17, count 2 2006.285.08:35:07.38#ibcon#read 5, iclass 17, count 2 2006.285.08:35:07.38#ibcon#about to read 6, iclass 17, count 2 2006.285.08:35:07.38#ibcon#read 6, iclass 17, count 2 2006.285.08:35:07.38#ibcon#end of sib2, iclass 17, count 2 2006.285.08:35:07.38#ibcon#*mode == 0, iclass 17, count 2 2006.285.08:35:07.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.08:35:07.38#ibcon#[27=AT07-04\r\n] 2006.285.08:35:07.38#ibcon#*before write, iclass 17, count 2 2006.285.08:35:07.38#ibcon#enter sib2, iclass 17, count 2 2006.285.08:35:07.38#ibcon#flushed, iclass 17, count 2 2006.285.08:35:07.38#ibcon#about to write, iclass 17, count 2 2006.285.08:35:07.38#ibcon#wrote, iclass 17, count 2 2006.285.08:35:07.38#ibcon#about to read 3, iclass 17, count 2 2006.285.08:35:07.41#ibcon#read 3, iclass 17, count 2 2006.285.08:35:07.41#ibcon#about to read 4, iclass 17, count 2 2006.285.08:35:07.41#ibcon#read 4, iclass 17, count 2 2006.285.08:35:07.41#ibcon#about to read 5, iclass 17, count 2 2006.285.08:35:07.41#ibcon#read 5, iclass 17, count 2 2006.285.08:35:07.41#ibcon#about to read 6, iclass 17, count 2 2006.285.08:35:07.41#ibcon#read 6, iclass 17, count 2 2006.285.08:35:07.41#ibcon#end of sib2, iclass 17, count 2 2006.285.08:35:07.41#ibcon#*after write, iclass 17, count 2 2006.285.08:35:07.41#ibcon#*before return 0, iclass 17, count 2 2006.285.08:35:07.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:35:07.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.08:35:07.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.08:35:07.41#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:07.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:35:07.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:35:07.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:35:07.53#ibcon#enter wrdev, iclass 17, count 0 2006.285.08:35:07.53#ibcon#first serial, iclass 17, count 0 2006.285.08:35:07.53#ibcon#enter sib2, iclass 17, count 0 2006.285.08:35:07.53#ibcon#flushed, iclass 17, count 0 2006.285.08:35:07.53#ibcon#about to write, iclass 17, count 0 2006.285.08:35:07.53#ibcon#wrote, iclass 17, count 0 2006.285.08:35:07.53#ibcon#about to read 3, iclass 17, count 0 2006.285.08:35:07.55#ibcon#read 3, iclass 17, count 0 2006.285.08:35:07.55#ibcon#about to read 4, iclass 17, count 0 2006.285.08:35:07.55#ibcon#read 4, iclass 17, count 0 2006.285.08:35:07.55#ibcon#about to read 5, iclass 17, count 0 2006.285.08:35:07.55#ibcon#read 5, iclass 17, count 0 2006.285.08:35:07.55#ibcon#about to read 6, iclass 17, count 0 2006.285.08:35:07.55#ibcon#read 6, iclass 17, count 0 2006.285.08:35:07.55#ibcon#end of sib2, iclass 17, count 0 2006.285.08:35:07.55#ibcon#*mode == 0, iclass 17, count 0 2006.285.08:35:07.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.08:35:07.55#ibcon#[27=USB\r\n] 2006.285.08:35:07.55#ibcon#*before write, iclass 17, count 0 2006.285.08:35:07.55#ibcon#enter sib2, iclass 17, count 0 2006.285.08:35:07.55#ibcon#flushed, iclass 17, count 0 2006.285.08:35:07.55#ibcon#about to write, iclass 17, count 0 2006.285.08:35:07.55#ibcon#wrote, iclass 17, count 0 2006.285.08:35:07.55#ibcon#about to read 3, iclass 17, count 0 2006.285.08:35:07.58#ibcon#read 3, iclass 17, count 0 2006.285.08:35:07.58#ibcon#about to read 4, iclass 17, count 0 2006.285.08:35:07.58#ibcon#read 4, iclass 17, count 0 2006.285.08:35:07.58#ibcon#about to read 5, iclass 17, count 0 2006.285.08:35:07.58#ibcon#read 5, iclass 17, count 0 2006.285.08:35:07.58#ibcon#about to read 6, iclass 17, count 0 2006.285.08:35:07.58#ibcon#read 6, iclass 17, count 0 2006.285.08:35:07.58#ibcon#end of sib2, iclass 17, count 0 2006.285.08:35:07.58#ibcon#*after write, iclass 17, count 0 2006.285.08:35:07.58#ibcon#*before return 0, iclass 17, count 0 2006.285.08:35:07.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:35:07.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.08:35:07.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.08:35:07.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.08:35:07.58$vck44/vblo=8,744.99 2006.285.08:35:07.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.08:35:07.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.08:35:07.58#ibcon#ireg 17 cls_cnt 0 2006.285.08:35:07.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:35:07.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:35:07.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:35:07.58#ibcon#enter wrdev, iclass 19, count 0 2006.285.08:35:07.58#ibcon#first serial, iclass 19, count 0 2006.285.08:35:07.58#ibcon#enter sib2, iclass 19, count 0 2006.285.08:35:07.58#ibcon#flushed, iclass 19, count 0 2006.285.08:35:07.58#ibcon#about to write, iclass 19, count 0 2006.285.08:35:07.58#ibcon#wrote, iclass 19, count 0 2006.285.08:35:07.58#ibcon#about to read 3, iclass 19, count 0 2006.285.08:35:07.60#ibcon#read 3, iclass 19, count 0 2006.285.08:35:07.60#ibcon#about to read 4, iclass 19, count 0 2006.285.08:35:07.60#ibcon#read 4, iclass 19, count 0 2006.285.08:35:07.60#ibcon#about to read 5, iclass 19, count 0 2006.285.08:35:07.60#ibcon#read 5, iclass 19, count 0 2006.285.08:35:07.60#ibcon#about to read 6, iclass 19, count 0 2006.285.08:35:07.60#ibcon#read 6, iclass 19, count 0 2006.285.08:35:07.60#ibcon#end of sib2, iclass 19, count 0 2006.285.08:35:07.60#ibcon#*mode == 0, iclass 19, count 0 2006.285.08:35:07.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.08:35:07.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:35:07.60#ibcon#*before write, iclass 19, count 0 2006.285.08:35:07.60#ibcon#enter sib2, iclass 19, count 0 2006.285.08:35:07.60#ibcon#flushed, iclass 19, count 0 2006.285.08:35:07.60#ibcon#about to write, iclass 19, count 0 2006.285.08:35:07.60#ibcon#wrote, iclass 19, count 0 2006.285.08:35:07.60#ibcon#about to read 3, iclass 19, count 0 2006.285.08:35:07.64#ibcon#read 3, iclass 19, count 0 2006.285.08:35:07.64#ibcon#about to read 4, iclass 19, count 0 2006.285.08:35:07.64#ibcon#read 4, iclass 19, count 0 2006.285.08:35:07.64#ibcon#about to read 5, iclass 19, count 0 2006.285.08:35:07.64#ibcon#read 5, iclass 19, count 0 2006.285.08:35:07.64#ibcon#about to read 6, iclass 19, count 0 2006.285.08:35:07.64#ibcon#read 6, iclass 19, count 0 2006.285.08:35:07.64#ibcon#end of sib2, iclass 19, count 0 2006.285.08:35:07.64#ibcon#*after write, iclass 19, count 0 2006.285.08:35:07.64#ibcon#*before return 0, iclass 19, count 0 2006.285.08:35:07.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:35:07.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.08:35:07.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.08:35:07.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.08:35:07.64$vck44/vb=8,4 2006.285.08:35:07.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.08:35:07.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.08:35:07.64#ibcon#ireg 11 cls_cnt 2 2006.285.08:35:07.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:35:07.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:35:07.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:35:07.70#ibcon#enter wrdev, iclass 21, count 2 2006.285.08:35:07.70#ibcon#first serial, iclass 21, count 2 2006.285.08:35:07.70#ibcon#enter sib2, iclass 21, count 2 2006.285.08:35:07.70#ibcon#flushed, iclass 21, count 2 2006.285.08:35:07.70#ibcon#about to write, iclass 21, count 2 2006.285.08:35:07.70#ibcon#wrote, iclass 21, count 2 2006.285.08:35:07.70#ibcon#about to read 3, iclass 21, count 2 2006.285.08:35:07.72#ibcon#read 3, iclass 21, count 2 2006.285.08:35:07.72#ibcon#about to read 4, iclass 21, count 2 2006.285.08:35:07.72#ibcon#read 4, iclass 21, count 2 2006.285.08:35:07.72#ibcon#about to read 5, iclass 21, count 2 2006.285.08:35:07.72#ibcon#read 5, iclass 21, count 2 2006.285.08:35:07.72#ibcon#about to read 6, iclass 21, count 2 2006.285.08:35:07.72#ibcon#read 6, iclass 21, count 2 2006.285.08:35:07.72#ibcon#end of sib2, iclass 21, count 2 2006.285.08:35:07.72#ibcon#*mode == 0, iclass 21, count 2 2006.285.08:35:07.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.08:35:07.72#ibcon#[27=AT08-04\r\n] 2006.285.08:35:07.72#ibcon#*before write, iclass 21, count 2 2006.285.08:35:07.72#ibcon#enter sib2, iclass 21, count 2 2006.285.08:35:07.72#ibcon#flushed, iclass 21, count 2 2006.285.08:35:07.72#ibcon#about to write, iclass 21, count 2 2006.285.08:35:07.72#ibcon#wrote, iclass 21, count 2 2006.285.08:35:07.72#ibcon#about to read 3, iclass 21, count 2 2006.285.08:35:07.75#ibcon#read 3, iclass 21, count 2 2006.285.08:35:07.75#ibcon#about to read 4, iclass 21, count 2 2006.285.08:35:07.75#ibcon#read 4, iclass 21, count 2 2006.285.08:35:07.75#ibcon#about to read 5, iclass 21, count 2 2006.285.08:35:07.75#ibcon#read 5, iclass 21, count 2 2006.285.08:35:07.75#ibcon#about to read 6, iclass 21, count 2 2006.285.08:35:07.75#ibcon#read 6, iclass 21, count 2 2006.285.08:35:07.75#ibcon#end of sib2, iclass 21, count 2 2006.285.08:35:07.75#ibcon#*after write, iclass 21, count 2 2006.285.08:35:07.75#ibcon#*before return 0, iclass 21, count 2 2006.285.08:35:07.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:35:07.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.08:35:07.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.08:35:07.75#ibcon#ireg 7 cls_cnt 0 2006.285.08:35:07.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:35:07.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:35:07.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:35:07.87#ibcon#enter wrdev, iclass 21, count 0 2006.285.08:35:07.87#ibcon#first serial, iclass 21, count 0 2006.285.08:35:07.87#ibcon#enter sib2, iclass 21, count 0 2006.285.08:35:07.87#ibcon#flushed, iclass 21, count 0 2006.285.08:35:07.87#ibcon#about to write, iclass 21, count 0 2006.285.08:35:07.87#ibcon#wrote, iclass 21, count 0 2006.285.08:35:07.87#ibcon#about to read 3, iclass 21, count 0 2006.285.08:35:07.89#ibcon#read 3, iclass 21, count 0 2006.285.08:35:07.89#ibcon#about to read 4, iclass 21, count 0 2006.285.08:35:07.89#ibcon#read 4, iclass 21, count 0 2006.285.08:35:07.89#ibcon#about to read 5, iclass 21, count 0 2006.285.08:35:07.89#ibcon#read 5, iclass 21, count 0 2006.285.08:35:07.89#ibcon#about to read 6, iclass 21, count 0 2006.285.08:35:07.89#ibcon#read 6, iclass 21, count 0 2006.285.08:35:07.89#ibcon#end of sib2, iclass 21, count 0 2006.285.08:35:07.89#ibcon#*mode == 0, iclass 21, count 0 2006.285.08:35:07.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.08:35:07.89#ibcon#[27=USB\r\n] 2006.285.08:35:07.89#ibcon#*before write, iclass 21, count 0 2006.285.08:35:07.89#ibcon#enter sib2, iclass 21, count 0 2006.285.08:35:07.89#ibcon#flushed, iclass 21, count 0 2006.285.08:35:07.89#ibcon#about to write, iclass 21, count 0 2006.285.08:35:07.89#ibcon#wrote, iclass 21, count 0 2006.285.08:35:07.89#ibcon#about to read 3, iclass 21, count 0 2006.285.08:35:07.92#ibcon#read 3, iclass 21, count 0 2006.285.08:35:07.92#ibcon#about to read 4, iclass 21, count 0 2006.285.08:35:07.92#ibcon#read 4, iclass 21, count 0 2006.285.08:35:07.92#ibcon#about to read 5, iclass 21, count 0 2006.285.08:35:07.92#ibcon#read 5, iclass 21, count 0 2006.285.08:35:07.92#ibcon#about to read 6, iclass 21, count 0 2006.285.08:35:07.92#ibcon#read 6, iclass 21, count 0 2006.285.08:35:07.92#ibcon#end of sib2, iclass 21, count 0 2006.285.08:35:07.92#ibcon#*after write, iclass 21, count 0 2006.285.08:35:07.92#ibcon#*before return 0, iclass 21, count 0 2006.285.08:35:07.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:35:07.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.08:35:07.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.08:35:07.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.08:35:07.92$vck44/vabw=wide 2006.285.08:35:07.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.08:35:07.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.08:35:07.92#ibcon#ireg 8 cls_cnt 0 2006.285.08:35:07.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:35:07.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:35:07.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:35:07.92#ibcon#enter wrdev, iclass 23, count 0 2006.285.08:35:07.92#ibcon#first serial, iclass 23, count 0 2006.285.08:35:07.92#ibcon#enter sib2, iclass 23, count 0 2006.285.08:35:07.92#ibcon#flushed, iclass 23, count 0 2006.285.08:35:07.92#ibcon#about to write, iclass 23, count 0 2006.285.08:35:07.92#ibcon#wrote, iclass 23, count 0 2006.285.08:35:07.92#ibcon#about to read 3, iclass 23, count 0 2006.285.08:35:07.94#ibcon#read 3, iclass 23, count 0 2006.285.08:35:07.94#ibcon#about to read 4, iclass 23, count 0 2006.285.08:35:07.94#ibcon#read 4, iclass 23, count 0 2006.285.08:35:07.94#ibcon#about to read 5, iclass 23, count 0 2006.285.08:35:07.94#ibcon#read 5, iclass 23, count 0 2006.285.08:35:07.94#ibcon#about to read 6, iclass 23, count 0 2006.285.08:35:07.94#ibcon#read 6, iclass 23, count 0 2006.285.08:35:07.94#ibcon#end of sib2, iclass 23, count 0 2006.285.08:35:07.94#ibcon#*mode == 0, iclass 23, count 0 2006.285.08:35:07.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.08:35:07.94#ibcon#[25=BW32\r\n] 2006.285.08:35:07.94#ibcon#*before write, iclass 23, count 0 2006.285.08:35:07.94#ibcon#enter sib2, iclass 23, count 0 2006.285.08:35:07.94#ibcon#flushed, iclass 23, count 0 2006.285.08:35:07.94#ibcon#about to write, iclass 23, count 0 2006.285.08:35:07.94#ibcon#wrote, iclass 23, count 0 2006.285.08:35:07.94#ibcon#about to read 3, iclass 23, count 0 2006.285.08:35:07.97#ibcon#read 3, iclass 23, count 0 2006.285.08:35:07.97#ibcon#about to read 4, iclass 23, count 0 2006.285.08:35:07.97#ibcon#read 4, iclass 23, count 0 2006.285.08:35:07.97#ibcon#about to read 5, iclass 23, count 0 2006.285.08:35:07.97#ibcon#read 5, iclass 23, count 0 2006.285.08:35:07.97#ibcon#about to read 6, iclass 23, count 0 2006.285.08:35:07.97#ibcon#read 6, iclass 23, count 0 2006.285.08:35:07.97#ibcon#end of sib2, iclass 23, count 0 2006.285.08:35:07.97#ibcon#*after write, iclass 23, count 0 2006.285.08:35:07.97#ibcon#*before return 0, iclass 23, count 0 2006.285.08:35:07.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:35:07.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:35:07.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.08:35:07.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.08:35:07.97$vck44/vbbw=wide 2006.285.08:35:07.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.08:35:07.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.08:35:07.97#ibcon#ireg 8 cls_cnt 0 2006.285.08:35:07.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:35:08.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:35:08.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:35:08.04#ibcon#enter wrdev, iclass 25, count 0 2006.285.08:35:08.04#ibcon#first serial, iclass 25, count 0 2006.285.08:35:08.04#ibcon#enter sib2, iclass 25, count 0 2006.285.08:35:08.04#ibcon#flushed, iclass 25, count 0 2006.285.08:35:08.04#ibcon#about to write, iclass 25, count 0 2006.285.08:35:08.04#ibcon#wrote, iclass 25, count 0 2006.285.08:35:08.04#ibcon#about to read 3, iclass 25, count 0 2006.285.08:35:08.06#ibcon#read 3, iclass 25, count 0 2006.285.08:35:08.06#ibcon#about to read 4, iclass 25, count 0 2006.285.08:35:08.06#ibcon#read 4, iclass 25, count 0 2006.285.08:35:08.06#ibcon#about to read 5, iclass 25, count 0 2006.285.08:35:08.06#ibcon#read 5, iclass 25, count 0 2006.285.08:35:08.06#ibcon#about to read 6, iclass 25, count 0 2006.285.08:35:08.06#ibcon#read 6, iclass 25, count 0 2006.285.08:35:08.06#ibcon#end of sib2, iclass 25, count 0 2006.285.08:35:08.06#ibcon#*mode == 0, iclass 25, count 0 2006.285.08:35:08.06#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.08:35:08.06#ibcon#[27=BW32\r\n] 2006.285.08:35:08.06#ibcon#*before write, iclass 25, count 0 2006.285.08:35:08.06#ibcon#enter sib2, iclass 25, count 0 2006.285.08:35:08.06#ibcon#flushed, iclass 25, count 0 2006.285.08:35:08.06#ibcon#about to write, iclass 25, count 0 2006.285.08:35:08.06#ibcon#wrote, iclass 25, count 0 2006.285.08:35:08.06#ibcon#about to read 3, iclass 25, count 0 2006.285.08:35:08.09#ibcon#read 3, iclass 25, count 0 2006.285.08:35:08.09#ibcon#about to read 4, iclass 25, count 0 2006.285.08:35:08.09#ibcon#read 4, iclass 25, count 0 2006.285.08:35:08.09#ibcon#about to read 5, iclass 25, count 0 2006.285.08:35:08.09#ibcon#read 5, iclass 25, count 0 2006.285.08:35:08.09#ibcon#about to read 6, iclass 25, count 0 2006.285.08:35:08.09#ibcon#read 6, iclass 25, count 0 2006.285.08:35:08.09#ibcon#end of sib2, iclass 25, count 0 2006.285.08:35:08.09#ibcon#*after write, iclass 25, count 0 2006.285.08:35:08.09#ibcon#*before return 0, iclass 25, count 0 2006.285.08:35:08.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:35:08.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:35:08.09#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.08:35:08.09#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.08:35:08.09$setupk4/ifdk4 2006.285.08:35:08.09$ifdk4/lo= 2006.285.08:35:08.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:35:08.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:35:08.09$ifdk4/patch= 2006.285.08:35:08.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:35:08.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:35:08.09$setupk4/!*+20s 2006.285.08:35:09.84#abcon#<5=/04 1.4 2.0 22.12 821014.8\r\n> 2006.285.08:35:09.86#abcon#{5=INTERFACE CLEAR} 2006.285.08:35:09.92#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:35:15.14#trakl#Source acquired 2006.285.08:35:15.14#flagr#flagr/antenna,acquired 2006.285.08:35:20.01#abcon#<5=/04 1.4 2.0 22.12 821014.8\r\n> 2006.285.08:35:20.03#abcon#{5=INTERFACE CLEAR} 2006.285.08:35:20.09#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:35:22.60$setupk4/"tpicd 2006.285.08:35:22.60$setupk4/echo=off 2006.285.08:35:22.60$setupk4/xlog=off 2006.285.08:35:22.60:!2006.285.08:35:31 2006.285.08:35:31.00:preob 2006.285.08:35:31.14/onsource/TRACKING 2006.285.08:35:31.14:!2006.285.08:35:41 2006.285.08:35:41.00:"tape 2006.285.08:35:41.00:"st=record 2006.285.08:35:41.00:data_valid=on 2006.285.08:35:41.00:midob 2006.285.08:35:42.14/onsource/TRACKING 2006.285.08:35:42.14/wx/22.11,1014.8,82 2006.285.08:35:42.22/cable/+6.4742E-03 2006.285.08:35:43.31/va/01,07,usb,yes,39,43 2006.285.08:35:43.31/va/02,06,usb,yes,40,40 2006.285.08:35:43.31/va/03,07,usb,yes,39,41 2006.285.08:35:43.31/va/04,06,usb,yes,41,43 2006.285.08:35:43.31/va/05,03,usb,yes,40,41 2006.285.08:35:43.31/va/06,04,usb,yes,36,36 2006.285.08:35:43.31/va/07,04,usb,yes,37,38 2006.285.08:35:43.31/va/08,03,usb,yes,38,46 2006.285.08:35:43.54/valo/01,524.99,yes,locked 2006.285.08:35:43.54/valo/02,534.99,yes,locked 2006.285.08:35:43.54/valo/03,564.99,yes,locked 2006.285.08:35:43.54/valo/04,624.99,yes,locked 2006.285.08:35:43.54/valo/05,734.99,yes,locked 2006.285.08:35:43.54/valo/06,814.99,yes,locked 2006.285.08:35:43.54/valo/07,864.99,yes,locked 2006.285.08:35:43.54/valo/08,884.99,yes,locked 2006.285.08:35:44.63/vb/01,04,usb,yes,35,33 2006.285.08:35:44.63/vb/02,05,usb,yes,33,33 2006.285.08:35:44.63/vb/03,04,usb,yes,34,38 2006.285.08:35:44.63/vb/04,05,usb,yes,35,34 2006.285.08:35:44.63/vb/05,04,usb,yes,31,34 2006.285.08:35:44.63/vb/06,03,usb,yes,45,40 2006.285.08:35:44.63/vb/07,04,usb,yes,36,36 2006.285.08:35:44.63/vb/08,04,usb,yes,33,37 2006.285.08:35:44.86/vblo/01,629.99,yes,locked 2006.285.08:35:44.86/vblo/02,634.99,yes,locked 2006.285.08:35:44.86/vblo/03,649.99,yes,locked 2006.285.08:35:44.86/vblo/04,679.99,yes,locked 2006.285.08:35:44.86/vblo/05,709.99,yes,locked 2006.285.08:35:44.86/vblo/06,719.99,yes,locked 2006.285.08:35:44.86/vblo/07,734.99,yes,locked 2006.285.08:35:44.86/vblo/08,744.99,yes,locked 2006.285.08:35:45.01/vabw/8 2006.285.08:35:45.16/vbbw/8 2006.285.08:35:45.25/xfe/off,on,12.2 2006.285.08:35:45.62/ifatt/23,28,28,28 2006.285.08:35:46.07/fmout-gps/S +2.72E-07 2006.285.08:35:46.09:!2006.285.08:44:21 2006.285.08:44:21.00:data_valid=off 2006.285.08:44:21.00:"et 2006.285.08:44:21.00:!+3s 2006.285.08:44:24.01:"tape 2006.285.08:44:24.01:postob 2006.285.08:44:24.18/cable/+6.4770E-03 2006.285.08:44:24.18/wx/21.89,1014.9,82 2006.285.08:44:25.07/fmout-gps/S +2.69E-07 2006.285.08:44:25.07:scan_name=285-0845,jd0610,160 2006.285.08:44:25.07:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.285.08:44:26.14#flagr#flagr/antenna,new-source 2006.285.08:44:26.14:checkk5 2006.285.08:44:26.58/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:44:27.01/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:44:27.37/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:44:27.86/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:44:28.61/chk_obsdata//k5ts1/T2850835??a.dat file size is correct (nominal:2080MB, actual:2080MB). 2006.285.08:44:29.29/chk_obsdata//k5ts2/T2850835??b.dat file size is correct (nominal:2080MB, actual:2080MB). 2006.285.08:44:30.02/chk_obsdata//k5ts3/T2850835??c.dat file size is correct (nominal:2080MB, actual:2080MB). 2006.285.08:44:30.73/chk_obsdata//k5ts4/T2850835??d.dat file size is correct (nominal:2080MB, actual:2080MB). 2006.285.08:44:31.50/k5log//k5ts1_log_newline 2006.285.08:44:32.30/k5log//k5ts2_log_newline 2006.285.08:44:33.02/k5log//k5ts3_log_newline 2006.285.08:44:33.88/k5log//k5ts4_log_newline 2006.285.08:44:33.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:44:33.91:setupk4=1 2006.285.08:44:33.91$setupk4/echo=on 2006.285.08:44:33.91$setupk4/pcalon 2006.285.08:44:33.91$pcalon/"no phase cal control is implemented here 2006.285.08:44:33.91$setupk4/"tpicd=stop 2006.285.08:44:33.91$setupk4/"rec=synch_on 2006.285.08:44:33.91$setupk4/"rec_mode=128 2006.285.08:44:33.91$setupk4/!* 2006.285.08:44:33.91$setupk4/recpk4 2006.285.08:44:33.91$recpk4/recpatch= 2006.285.08:44:33.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:44:33.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:44:33.91$setupk4/vck44 2006.285.08:44:33.91$vck44/valo=1,524.99 2006.285.08:44:33.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.08:44:33.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.08:44:33.91#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:33.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:44:33.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:44:33.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:44:33.91#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:44:33.91#ibcon#first serial, iclass 38, count 0 2006.285.08:44:33.91#ibcon#enter sib2, iclass 38, count 0 2006.285.08:44:33.91#ibcon#flushed, iclass 38, count 0 2006.285.08:44:33.91#ibcon#about to write, iclass 38, count 0 2006.285.08:44:33.91#ibcon#wrote, iclass 38, count 0 2006.285.08:44:33.91#ibcon#about to read 3, iclass 38, count 0 2006.285.08:44:33.93#ibcon#read 3, iclass 38, count 0 2006.285.08:44:33.93#ibcon#about to read 4, iclass 38, count 0 2006.285.08:44:33.93#ibcon#read 4, iclass 38, count 0 2006.285.08:44:33.93#ibcon#about to read 5, iclass 38, count 0 2006.285.08:44:33.93#ibcon#read 5, iclass 38, count 0 2006.285.08:44:33.93#ibcon#about to read 6, iclass 38, count 0 2006.285.08:44:33.93#ibcon#read 6, iclass 38, count 0 2006.285.08:44:33.93#ibcon#end of sib2, iclass 38, count 0 2006.285.08:44:33.93#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:44:33.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:44:33.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:44:33.93#ibcon#*before write, iclass 38, count 0 2006.285.08:44:33.93#ibcon#enter sib2, iclass 38, count 0 2006.285.08:44:33.93#ibcon#flushed, iclass 38, count 0 2006.285.08:44:33.93#ibcon#about to write, iclass 38, count 0 2006.285.08:44:33.93#ibcon#wrote, iclass 38, count 0 2006.285.08:44:33.93#ibcon#about to read 3, iclass 38, count 0 2006.285.08:44:33.98#ibcon#read 3, iclass 38, count 0 2006.285.08:44:33.98#ibcon#about to read 4, iclass 38, count 0 2006.285.08:44:33.98#ibcon#read 4, iclass 38, count 0 2006.285.08:44:33.98#ibcon#about to read 5, iclass 38, count 0 2006.285.08:44:33.98#ibcon#read 5, iclass 38, count 0 2006.285.08:44:33.98#ibcon#about to read 6, iclass 38, count 0 2006.285.08:44:33.98#ibcon#read 6, iclass 38, count 0 2006.285.08:44:33.98#ibcon#end of sib2, iclass 38, count 0 2006.285.08:44:33.98#ibcon#*after write, iclass 38, count 0 2006.285.08:44:33.98#ibcon#*before return 0, iclass 38, count 0 2006.285.08:44:33.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:44:33.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:44:33.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:44:33.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:44:33.98$vck44/va=1,7 2006.285.08:44:33.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.08:44:33.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.08:44:33.98#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:33.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:44:33.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:44:33.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:44:33.98#ibcon#enter wrdev, iclass 40, count 2 2006.285.08:44:33.98#ibcon#first serial, iclass 40, count 2 2006.285.08:44:33.98#ibcon#enter sib2, iclass 40, count 2 2006.285.08:44:33.98#ibcon#flushed, iclass 40, count 2 2006.285.08:44:33.98#ibcon#about to write, iclass 40, count 2 2006.285.08:44:33.98#ibcon#wrote, iclass 40, count 2 2006.285.08:44:33.98#ibcon#about to read 3, iclass 40, count 2 2006.285.08:44:34.00#ibcon#read 3, iclass 40, count 2 2006.285.08:44:34.00#ibcon#about to read 4, iclass 40, count 2 2006.285.08:44:34.00#ibcon#read 4, iclass 40, count 2 2006.285.08:44:34.00#ibcon#about to read 5, iclass 40, count 2 2006.285.08:44:34.00#ibcon#read 5, iclass 40, count 2 2006.285.08:44:34.00#ibcon#about to read 6, iclass 40, count 2 2006.285.08:44:34.00#ibcon#read 6, iclass 40, count 2 2006.285.08:44:34.00#ibcon#end of sib2, iclass 40, count 2 2006.285.08:44:34.00#ibcon#*mode == 0, iclass 40, count 2 2006.285.08:44:34.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.08:44:34.00#ibcon#[25=AT01-07\r\n] 2006.285.08:44:34.00#ibcon#*before write, iclass 40, count 2 2006.285.08:44:34.00#ibcon#enter sib2, iclass 40, count 2 2006.285.08:44:34.00#ibcon#flushed, iclass 40, count 2 2006.285.08:44:34.00#ibcon#about to write, iclass 40, count 2 2006.285.08:44:34.00#ibcon#wrote, iclass 40, count 2 2006.285.08:44:34.00#ibcon#about to read 3, iclass 40, count 2 2006.285.08:44:34.03#ibcon#read 3, iclass 40, count 2 2006.285.08:44:34.03#ibcon#about to read 4, iclass 40, count 2 2006.285.08:44:34.03#ibcon#read 4, iclass 40, count 2 2006.285.08:44:34.03#ibcon#about to read 5, iclass 40, count 2 2006.285.08:44:34.03#ibcon#read 5, iclass 40, count 2 2006.285.08:44:34.03#ibcon#about to read 6, iclass 40, count 2 2006.285.08:44:34.03#ibcon#read 6, iclass 40, count 2 2006.285.08:44:34.03#ibcon#end of sib2, iclass 40, count 2 2006.285.08:44:34.03#ibcon#*after write, iclass 40, count 2 2006.285.08:44:34.03#ibcon#*before return 0, iclass 40, count 2 2006.285.08:44:34.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:44:34.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:44:34.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.08:44:34.03#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:34.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:44:34.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:44:34.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:44:34.15#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:44:34.15#ibcon#first serial, iclass 40, count 0 2006.285.08:44:34.15#ibcon#enter sib2, iclass 40, count 0 2006.285.08:44:34.15#ibcon#flushed, iclass 40, count 0 2006.285.08:44:34.15#ibcon#about to write, iclass 40, count 0 2006.285.08:44:34.15#ibcon#wrote, iclass 40, count 0 2006.285.08:44:34.15#ibcon#about to read 3, iclass 40, count 0 2006.285.08:44:34.17#ibcon#read 3, iclass 40, count 0 2006.285.08:44:34.17#ibcon#about to read 4, iclass 40, count 0 2006.285.08:44:34.17#ibcon#read 4, iclass 40, count 0 2006.285.08:44:34.17#ibcon#about to read 5, iclass 40, count 0 2006.285.08:44:34.17#ibcon#read 5, iclass 40, count 0 2006.285.08:44:34.17#ibcon#about to read 6, iclass 40, count 0 2006.285.08:44:34.17#ibcon#read 6, iclass 40, count 0 2006.285.08:44:34.17#ibcon#end of sib2, iclass 40, count 0 2006.285.08:44:34.17#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:44:34.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:44:34.17#ibcon#[25=USB\r\n] 2006.285.08:44:34.17#ibcon#*before write, iclass 40, count 0 2006.285.08:44:34.17#ibcon#enter sib2, iclass 40, count 0 2006.285.08:44:34.17#ibcon#flushed, iclass 40, count 0 2006.285.08:44:34.17#ibcon#about to write, iclass 40, count 0 2006.285.08:44:34.17#ibcon#wrote, iclass 40, count 0 2006.285.08:44:34.17#ibcon#about to read 3, iclass 40, count 0 2006.285.08:44:34.20#ibcon#read 3, iclass 40, count 0 2006.285.08:44:34.20#ibcon#about to read 4, iclass 40, count 0 2006.285.08:44:34.20#ibcon#read 4, iclass 40, count 0 2006.285.08:44:34.20#ibcon#about to read 5, iclass 40, count 0 2006.285.08:44:34.20#ibcon#read 5, iclass 40, count 0 2006.285.08:44:34.20#ibcon#about to read 6, iclass 40, count 0 2006.285.08:44:34.20#ibcon#read 6, iclass 40, count 0 2006.285.08:44:34.20#ibcon#end of sib2, iclass 40, count 0 2006.285.08:44:34.20#ibcon#*after write, iclass 40, count 0 2006.285.08:44:34.20#ibcon#*before return 0, iclass 40, count 0 2006.285.08:44:34.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:44:34.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:44:34.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:44:34.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:44:34.20$vck44/valo=2,534.99 2006.285.08:44:34.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.08:44:34.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.08:44:34.20#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:34.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:44:34.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:44:34.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:44:34.20#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:44:34.20#ibcon#first serial, iclass 4, count 0 2006.285.08:44:34.20#ibcon#enter sib2, iclass 4, count 0 2006.285.08:44:34.20#ibcon#flushed, iclass 4, count 0 2006.285.08:44:34.20#ibcon#about to write, iclass 4, count 0 2006.285.08:44:34.20#ibcon#wrote, iclass 4, count 0 2006.285.08:44:34.20#ibcon#about to read 3, iclass 4, count 0 2006.285.08:44:34.22#ibcon#read 3, iclass 4, count 0 2006.285.08:44:34.22#ibcon#about to read 4, iclass 4, count 0 2006.285.08:44:34.22#ibcon#read 4, iclass 4, count 0 2006.285.08:44:34.22#ibcon#about to read 5, iclass 4, count 0 2006.285.08:44:34.22#ibcon#read 5, iclass 4, count 0 2006.285.08:44:34.22#ibcon#about to read 6, iclass 4, count 0 2006.285.08:44:34.22#ibcon#read 6, iclass 4, count 0 2006.285.08:44:34.22#ibcon#end of sib2, iclass 4, count 0 2006.285.08:44:34.22#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:44:34.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:44:34.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:44:34.22#ibcon#*before write, iclass 4, count 0 2006.285.08:44:34.22#ibcon#enter sib2, iclass 4, count 0 2006.285.08:44:34.22#ibcon#flushed, iclass 4, count 0 2006.285.08:44:34.22#ibcon#about to write, iclass 4, count 0 2006.285.08:44:34.22#ibcon#wrote, iclass 4, count 0 2006.285.08:44:34.22#ibcon#about to read 3, iclass 4, count 0 2006.285.08:44:34.26#ibcon#read 3, iclass 4, count 0 2006.285.08:44:34.26#ibcon#about to read 4, iclass 4, count 0 2006.285.08:44:34.26#ibcon#read 4, iclass 4, count 0 2006.285.08:44:34.26#ibcon#about to read 5, iclass 4, count 0 2006.285.08:44:34.26#ibcon#read 5, iclass 4, count 0 2006.285.08:44:34.26#ibcon#about to read 6, iclass 4, count 0 2006.285.08:44:34.26#ibcon#read 6, iclass 4, count 0 2006.285.08:44:34.26#ibcon#end of sib2, iclass 4, count 0 2006.285.08:44:34.26#ibcon#*after write, iclass 4, count 0 2006.285.08:44:34.26#ibcon#*before return 0, iclass 4, count 0 2006.285.08:44:34.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:44:34.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:44:34.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:44:34.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:44:34.26$vck44/va=2,6 2006.285.08:44:34.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.08:44:34.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.08:44:34.26#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:34.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:44:34.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:44:34.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:44:34.32#ibcon#enter wrdev, iclass 6, count 2 2006.285.08:44:34.32#ibcon#first serial, iclass 6, count 2 2006.285.08:44:34.32#ibcon#enter sib2, iclass 6, count 2 2006.285.08:44:34.32#ibcon#flushed, iclass 6, count 2 2006.285.08:44:34.32#ibcon#about to write, iclass 6, count 2 2006.285.08:44:34.32#ibcon#wrote, iclass 6, count 2 2006.285.08:44:34.32#ibcon#about to read 3, iclass 6, count 2 2006.285.08:44:34.34#ibcon#read 3, iclass 6, count 2 2006.285.08:44:34.34#ibcon#about to read 4, iclass 6, count 2 2006.285.08:44:34.34#ibcon#read 4, iclass 6, count 2 2006.285.08:44:34.34#ibcon#about to read 5, iclass 6, count 2 2006.285.08:44:34.34#ibcon#read 5, iclass 6, count 2 2006.285.08:44:34.34#ibcon#about to read 6, iclass 6, count 2 2006.285.08:44:34.34#ibcon#read 6, iclass 6, count 2 2006.285.08:44:34.34#ibcon#end of sib2, iclass 6, count 2 2006.285.08:44:34.34#ibcon#*mode == 0, iclass 6, count 2 2006.285.08:44:34.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.08:44:34.34#ibcon#[25=AT02-06\r\n] 2006.285.08:44:34.34#ibcon#*before write, iclass 6, count 2 2006.285.08:44:34.34#ibcon#enter sib2, iclass 6, count 2 2006.285.08:44:34.34#ibcon#flushed, iclass 6, count 2 2006.285.08:44:34.34#ibcon#about to write, iclass 6, count 2 2006.285.08:44:34.34#ibcon#wrote, iclass 6, count 2 2006.285.08:44:34.34#ibcon#about to read 3, iclass 6, count 2 2006.285.08:44:34.37#ibcon#read 3, iclass 6, count 2 2006.285.08:44:34.37#ibcon#about to read 4, iclass 6, count 2 2006.285.08:44:34.37#ibcon#read 4, iclass 6, count 2 2006.285.08:44:34.37#ibcon#about to read 5, iclass 6, count 2 2006.285.08:44:34.37#ibcon#read 5, iclass 6, count 2 2006.285.08:44:34.37#ibcon#about to read 6, iclass 6, count 2 2006.285.08:44:34.37#ibcon#read 6, iclass 6, count 2 2006.285.08:44:34.37#ibcon#end of sib2, iclass 6, count 2 2006.285.08:44:34.37#ibcon#*after write, iclass 6, count 2 2006.285.08:44:34.37#ibcon#*before return 0, iclass 6, count 2 2006.285.08:44:34.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:44:34.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:44:34.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.08:44:34.37#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:34.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:44:34.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:44:34.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:44:34.49#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:44:34.49#ibcon#first serial, iclass 6, count 0 2006.285.08:44:34.49#ibcon#enter sib2, iclass 6, count 0 2006.285.08:44:34.49#ibcon#flushed, iclass 6, count 0 2006.285.08:44:34.49#ibcon#about to write, iclass 6, count 0 2006.285.08:44:34.49#ibcon#wrote, iclass 6, count 0 2006.285.08:44:34.49#ibcon#about to read 3, iclass 6, count 0 2006.285.08:44:34.51#ibcon#read 3, iclass 6, count 0 2006.285.08:44:34.51#ibcon#about to read 4, iclass 6, count 0 2006.285.08:44:34.51#ibcon#read 4, iclass 6, count 0 2006.285.08:44:34.51#ibcon#about to read 5, iclass 6, count 0 2006.285.08:44:34.51#ibcon#read 5, iclass 6, count 0 2006.285.08:44:34.51#ibcon#about to read 6, iclass 6, count 0 2006.285.08:44:34.51#ibcon#read 6, iclass 6, count 0 2006.285.08:44:34.51#ibcon#end of sib2, iclass 6, count 0 2006.285.08:44:34.51#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:44:34.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:44:34.51#ibcon#[25=USB\r\n] 2006.285.08:44:34.51#ibcon#*before write, iclass 6, count 0 2006.285.08:44:34.51#ibcon#enter sib2, iclass 6, count 0 2006.285.08:44:34.51#ibcon#flushed, iclass 6, count 0 2006.285.08:44:34.51#ibcon#about to write, iclass 6, count 0 2006.285.08:44:34.51#ibcon#wrote, iclass 6, count 0 2006.285.08:44:34.51#ibcon#about to read 3, iclass 6, count 0 2006.285.08:44:34.54#ibcon#read 3, iclass 6, count 0 2006.285.08:44:34.54#ibcon#about to read 4, iclass 6, count 0 2006.285.08:44:34.54#ibcon#read 4, iclass 6, count 0 2006.285.08:44:34.54#ibcon#about to read 5, iclass 6, count 0 2006.285.08:44:34.54#ibcon#read 5, iclass 6, count 0 2006.285.08:44:34.54#ibcon#about to read 6, iclass 6, count 0 2006.285.08:44:34.54#ibcon#read 6, iclass 6, count 0 2006.285.08:44:34.54#ibcon#end of sib2, iclass 6, count 0 2006.285.08:44:34.54#ibcon#*after write, iclass 6, count 0 2006.285.08:44:34.54#ibcon#*before return 0, iclass 6, count 0 2006.285.08:44:34.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:44:34.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:44:34.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:44:34.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:44:34.54$vck44/valo=3,564.99 2006.285.08:44:34.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.08:44:34.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.08:44:34.54#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:34.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:44:34.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:44:34.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:44:34.54#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:44:34.54#ibcon#first serial, iclass 10, count 0 2006.285.08:44:34.54#ibcon#enter sib2, iclass 10, count 0 2006.285.08:44:34.54#ibcon#flushed, iclass 10, count 0 2006.285.08:44:34.54#ibcon#about to write, iclass 10, count 0 2006.285.08:44:34.54#ibcon#wrote, iclass 10, count 0 2006.285.08:44:34.54#ibcon#about to read 3, iclass 10, count 0 2006.285.08:44:34.56#ibcon#read 3, iclass 10, count 0 2006.285.08:44:34.56#ibcon#about to read 4, iclass 10, count 0 2006.285.08:44:34.56#ibcon#read 4, iclass 10, count 0 2006.285.08:44:34.56#ibcon#about to read 5, iclass 10, count 0 2006.285.08:44:34.56#ibcon#read 5, iclass 10, count 0 2006.285.08:44:34.56#ibcon#about to read 6, iclass 10, count 0 2006.285.08:44:34.56#ibcon#read 6, iclass 10, count 0 2006.285.08:44:34.56#ibcon#end of sib2, iclass 10, count 0 2006.285.08:44:34.56#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:44:34.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:44:34.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:44:34.56#ibcon#*before write, iclass 10, count 0 2006.285.08:44:34.56#ibcon#enter sib2, iclass 10, count 0 2006.285.08:44:34.56#ibcon#flushed, iclass 10, count 0 2006.285.08:44:34.56#ibcon#about to write, iclass 10, count 0 2006.285.08:44:34.56#ibcon#wrote, iclass 10, count 0 2006.285.08:44:34.56#ibcon#about to read 3, iclass 10, count 0 2006.285.08:44:34.60#ibcon#read 3, iclass 10, count 0 2006.285.08:44:34.60#ibcon#about to read 4, iclass 10, count 0 2006.285.08:44:34.60#ibcon#read 4, iclass 10, count 0 2006.285.08:44:34.60#ibcon#about to read 5, iclass 10, count 0 2006.285.08:44:34.60#ibcon#read 5, iclass 10, count 0 2006.285.08:44:34.60#ibcon#about to read 6, iclass 10, count 0 2006.285.08:44:34.60#ibcon#read 6, iclass 10, count 0 2006.285.08:44:34.60#ibcon#end of sib2, iclass 10, count 0 2006.285.08:44:34.60#ibcon#*after write, iclass 10, count 0 2006.285.08:44:34.60#ibcon#*before return 0, iclass 10, count 0 2006.285.08:44:34.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:44:34.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:44:34.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:44:34.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:44:34.60$vck44/va=3,7 2006.285.08:44:34.60#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.08:44:34.60#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.08:44:34.60#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:34.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:44:34.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:44:34.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:44:34.66#ibcon#enter wrdev, iclass 12, count 2 2006.285.08:44:34.66#ibcon#first serial, iclass 12, count 2 2006.285.08:44:34.66#ibcon#enter sib2, iclass 12, count 2 2006.285.08:44:34.66#ibcon#flushed, iclass 12, count 2 2006.285.08:44:34.66#ibcon#about to write, iclass 12, count 2 2006.285.08:44:34.66#ibcon#wrote, iclass 12, count 2 2006.285.08:44:34.66#ibcon#about to read 3, iclass 12, count 2 2006.285.08:44:34.68#ibcon#read 3, iclass 12, count 2 2006.285.08:44:34.68#ibcon#about to read 4, iclass 12, count 2 2006.285.08:44:34.68#ibcon#read 4, iclass 12, count 2 2006.285.08:44:34.68#ibcon#about to read 5, iclass 12, count 2 2006.285.08:44:34.68#ibcon#read 5, iclass 12, count 2 2006.285.08:44:34.68#ibcon#about to read 6, iclass 12, count 2 2006.285.08:44:34.68#ibcon#read 6, iclass 12, count 2 2006.285.08:44:34.68#ibcon#end of sib2, iclass 12, count 2 2006.285.08:44:34.68#ibcon#*mode == 0, iclass 12, count 2 2006.285.08:44:34.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.08:44:34.68#ibcon#[25=AT03-07\r\n] 2006.285.08:44:34.68#ibcon#*before write, iclass 12, count 2 2006.285.08:44:34.68#ibcon#enter sib2, iclass 12, count 2 2006.285.08:44:34.68#ibcon#flushed, iclass 12, count 2 2006.285.08:44:34.68#ibcon#about to write, iclass 12, count 2 2006.285.08:44:34.68#ibcon#wrote, iclass 12, count 2 2006.285.08:44:34.68#ibcon#about to read 3, iclass 12, count 2 2006.285.08:44:34.71#ibcon#read 3, iclass 12, count 2 2006.285.08:44:34.71#ibcon#about to read 4, iclass 12, count 2 2006.285.08:44:34.71#ibcon#read 4, iclass 12, count 2 2006.285.08:44:34.71#ibcon#about to read 5, iclass 12, count 2 2006.285.08:44:34.71#ibcon#read 5, iclass 12, count 2 2006.285.08:44:34.71#ibcon#about to read 6, iclass 12, count 2 2006.285.08:44:34.71#ibcon#read 6, iclass 12, count 2 2006.285.08:44:34.71#ibcon#end of sib2, iclass 12, count 2 2006.285.08:44:34.71#ibcon#*after write, iclass 12, count 2 2006.285.08:44:34.71#ibcon#*before return 0, iclass 12, count 2 2006.285.08:44:34.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:44:34.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:44:34.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.08:44:34.71#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:34.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:44:34.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:44:34.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:44:34.83#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:44:34.83#ibcon#first serial, iclass 12, count 0 2006.285.08:44:34.83#ibcon#enter sib2, iclass 12, count 0 2006.285.08:44:34.83#ibcon#flushed, iclass 12, count 0 2006.285.08:44:34.83#ibcon#about to write, iclass 12, count 0 2006.285.08:44:34.83#ibcon#wrote, iclass 12, count 0 2006.285.08:44:34.83#ibcon#about to read 3, iclass 12, count 0 2006.285.08:44:34.85#ibcon#read 3, iclass 12, count 0 2006.285.08:44:34.85#ibcon#about to read 4, iclass 12, count 0 2006.285.08:44:34.85#ibcon#read 4, iclass 12, count 0 2006.285.08:44:34.85#ibcon#about to read 5, iclass 12, count 0 2006.285.08:44:34.85#ibcon#read 5, iclass 12, count 0 2006.285.08:44:34.85#ibcon#about to read 6, iclass 12, count 0 2006.285.08:44:34.85#ibcon#read 6, iclass 12, count 0 2006.285.08:44:34.85#ibcon#end of sib2, iclass 12, count 0 2006.285.08:44:34.85#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:44:34.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:44:34.85#ibcon#[25=USB\r\n] 2006.285.08:44:34.85#ibcon#*before write, iclass 12, count 0 2006.285.08:44:34.85#ibcon#enter sib2, iclass 12, count 0 2006.285.08:44:34.85#ibcon#flushed, iclass 12, count 0 2006.285.08:44:34.85#ibcon#about to write, iclass 12, count 0 2006.285.08:44:34.85#ibcon#wrote, iclass 12, count 0 2006.285.08:44:34.85#ibcon#about to read 3, iclass 12, count 0 2006.285.08:44:34.88#ibcon#read 3, iclass 12, count 0 2006.285.08:44:34.88#ibcon#about to read 4, iclass 12, count 0 2006.285.08:44:34.88#ibcon#read 4, iclass 12, count 0 2006.285.08:44:34.88#ibcon#about to read 5, iclass 12, count 0 2006.285.08:44:34.88#ibcon#read 5, iclass 12, count 0 2006.285.08:44:34.88#ibcon#about to read 6, iclass 12, count 0 2006.285.08:44:34.88#ibcon#read 6, iclass 12, count 0 2006.285.08:44:34.88#ibcon#end of sib2, iclass 12, count 0 2006.285.08:44:34.88#ibcon#*after write, iclass 12, count 0 2006.285.08:44:34.88#ibcon#*before return 0, iclass 12, count 0 2006.285.08:44:34.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:44:34.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:44:34.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:44:34.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:44:34.89$vck44/valo=4,624.99 2006.285.08:44:34.89#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.08:44:34.89#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.08:44:34.89#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:34.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:44:34.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:44:34.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:44:34.89#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:44:34.89#ibcon#first serial, iclass 14, count 0 2006.285.08:44:34.89#ibcon#enter sib2, iclass 14, count 0 2006.285.08:44:34.89#ibcon#flushed, iclass 14, count 0 2006.285.08:44:34.89#ibcon#about to write, iclass 14, count 0 2006.285.08:44:34.89#ibcon#wrote, iclass 14, count 0 2006.285.08:44:34.89#ibcon#about to read 3, iclass 14, count 0 2006.285.08:44:34.91#ibcon#read 3, iclass 14, count 0 2006.285.08:44:34.91#ibcon#about to read 4, iclass 14, count 0 2006.285.08:44:34.91#ibcon#read 4, iclass 14, count 0 2006.285.08:44:34.91#ibcon#about to read 5, iclass 14, count 0 2006.285.08:44:34.91#ibcon#read 5, iclass 14, count 0 2006.285.08:44:34.91#ibcon#about to read 6, iclass 14, count 0 2006.285.08:44:34.91#ibcon#read 6, iclass 14, count 0 2006.285.08:44:34.91#ibcon#end of sib2, iclass 14, count 0 2006.285.08:44:34.91#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:44:34.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:44:34.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:44:34.91#ibcon#*before write, iclass 14, count 0 2006.285.08:44:34.91#ibcon#enter sib2, iclass 14, count 0 2006.285.08:44:34.91#ibcon#flushed, iclass 14, count 0 2006.285.08:44:34.91#ibcon#about to write, iclass 14, count 0 2006.285.08:44:34.91#ibcon#wrote, iclass 14, count 0 2006.285.08:44:34.91#ibcon#about to read 3, iclass 14, count 0 2006.285.08:44:34.95#ibcon#read 3, iclass 14, count 0 2006.285.08:44:34.95#ibcon#about to read 4, iclass 14, count 0 2006.285.08:44:34.95#ibcon#read 4, iclass 14, count 0 2006.285.08:44:34.95#ibcon#about to read 5, iclass 14, count 0 2006.285.08:44:34.95#ibcon#read 5, iclass 14, count 0 2006.285.08:44:34.95#ibcon#about to read 6, iclass 14, count 0 2006.285.08:44:34.95#ibcon#read 6, iclass 14, count 0 2006.285.08:44:34.95#ibcon#end of sib2, iclass 14, count 0 2006.285.08:44:34.95#ibcon#*after write, iclass 14, count 0 2006.285.08:44:34.95#ibcon#*before return 0, iclass 14, count 0 2006.285.08:44:34.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:44:34.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:44:34.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:44:34.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:44:34.95$vck44/va=4,6 2006.285.08:44:34.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.08:44:34.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.08:44:34.95#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:34.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:44:35.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:44:35.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:44:35.00#ibcon#enter wrdev, iclass 16, count 2 2006.285.08:44:35.00#ibcon#first serial, iclass 16, count 2 2006.285.08:44:35.00#ibcon#enter sib2, iclass 16, count 2 2006.285.08:44:35.00#ibcon#flushed, iclass 16, count 2 2006.285.08:44:35.00#ibcon#about to write, iclass 16, count 2 2006.285.08:44:35.00#ibcon#wrote, iclass 16, count 2 2006.285.08:44:35.00#ibcon#about to read 3, iclass 16, count 2 2006.285.08:44:35.02#ibcon#read 3, iclass 16, count 2 2006.285.08:44:35.02#ibcon#about to read 4, iclass 16, count 2 2006.285.08:44:35.02#ibcon#read 4, iclass 16, count 2 2006.285.08:44:35.02#ibcon#about to read 5, iclass 16, count 2 2006.285.08:44:35.02#ibcon#read 5, iclass 16, count 2 2006.285.08:44:35.02#ibcon#about to read 6, iclass 16, count 2 2006.285.08:44:35.02#ibcon#read 6, iclass 16, count 2 2006.285.08:44:35.02#ibcon#end of sib2, iclass 16, count 2 2006.285.08:44:35.02#ibcon#*mode == 0, iclass 16, count 2 2006.285.08:44:35.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.08:44:35.02#ibcon#[25=AT04-06\r\n] 2006.285.08:44:35.02#ibcon#*before write, iclass 16, count 2 2006.285.08:44:35.02#ibcon#enter sib2, iclass 16, count 2 2006.285.08:44:35.02#ibcon#flushed, iclass 16, count 2 2006.285.08:44:35.02#ibcon#about to write, iclass 16, count 2 2006.285.08:44:35.02#ibcon#wrote, iclass 16, count 2 2006.285.08:44:35.02#ibcon#about to read 3, iclass 16, count 2 2006.285.08:44:35.05#ibcon#read 3, iclass 16, count 2 2006.285.08:44:35.05#ibcon#about to read 4, iclass 16, count 2 2006.285.08:44:35.05#ibcon#read 4, iclass 16, count 2 2006.285.08:44:35.05#ibcon#about to read 5, iclass 16, count 2 2006.285.08:44:35.05#ibcon#read 5, iclass 16, count 2 2006.285.08:44:35.05#ibcon#about to read 6, iclass 16, count 2 2006.285.08:44:35.05#ibcon#read 6, iclass 16, count 2 2006.285.08:44:35.05#ibcon#end of sib2, iclass 16, count 2 2006.285.08:44:35.05#ibcon#*after write, iclass 16, count 2 2006.285.08:44:35.05#ibcon#*before return 0, iclass 16, count 2 2006.285.08:44:35.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:44:35.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:44:35.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.08:44:35.05#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:35.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:44:35.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:44:35.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:44:35.17#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:44:35.17#ibcon#first serial, iclass 16, count 0 2006.285.08:44:35.17#ibcon#enter sib2, iclass 16, count 0 2006.285.08:44:35.17#ibcon#flushed, iclass 16, count 0 2006.285.08:44:35.17#ibcon#about to write, iclass 16, count 0 2006.285.08:44:35.17#ibcon#wrote, iclass 16, count 0 2006.285.08:44:35.17#ibcon#about to read 3, iclass 16, count 0 2006.285.08:44:35.19#ibcon#read 3, iclass 16, count 0 2006.285.08:44:35.19#ibcon#about to read 4, iclass 16, count 0 2006.285.08:44:35.19#ibcon#read 4, iclass 16, count 0 2006.285.08:44:35.19#ibcon#about to read 5, iclass 16, count 0 2006.285.08:44:35.19#ibcon#read 5, iclass 16, count 0 2006.285.08:44:35.19#ibcon#about to read 6, iclass 16, count 0 2006.285.08:44:35.19#ibcon#read 6, iclass 16, count 0 2006.285.08:44:35.19#ibcon#end of sib2, iclass 16, count 0 2006.285.08:44:35.19#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:44:35.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:44:35.19#ibcon#[25=USB\r\n] 2006.285.08:44:35.19#ibcon#*before write, iclass 16, count 0 2006.285.08:44:35.19#ibcon#enter sib2, iclass 16, count 0 2006.285.08:44:35.19#ibcon#flushed, iclass 16, count 0 2006.285.08:44:35.19#ibcon#about to write, iclass 16, count 0 2006.285.08:44:35.19#ibcon#wrote, iclass 16, count 0 2006.285.08:44:35.19#ibcon#about to read 3, iclass 16, count 0 2006.285.08:44:35.22#ibcon#read 3, iclass 16, count 0 2006.285.08:44:35.22#ibcon#about to read 4, iclass 16, count 0 2006.285.08:44:35.22#ibcon#read 4, iclass 16, count 0 2006.285.08:44:35.22#ibcon#about to read 5, iclass 16, count 0 2006.285.08:44:35.22#ibcon#read 5, iclass 16, count 0 2006.285.08:44:35.22#ibcon#about to read 6, iclass 16, count 0 2006.285.08:44:35.22#ibcon#read 6, iclass 16, count 0 2006.285.08:44:35.22#ibcon#end of sib2, iclass 16, count 0 2006.285.08:44:35.22#ibcon#*after write, iclass 16, count 0 2006.285.08:44:35.22#ibcon#*before return 0, iclass 16, count 0 2006.285.08:44:35.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:44:35.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:44:35.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:44:35.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:44:35.22$vck44/valo=5,734.99 2006.285.08:44:35.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.08:44:35.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.08:44:35.22#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:35.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:44:35.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:44:35.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:44:35.22#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:44:35.22#ibcon#first serial, iclass 18, count 0 2006.285.08:44:35.22#ibcon#enter sib2, iclass 18, count 0 2006.285.08:44:35.22#ibcon#flushed, iclass 18, count 0 2006.285.08:44:35.22#ibcon#about to write, iclass 18, count 0 2006.285.08:44:35.22#ibcon#wrote, iclass 18, count 0 2006.285.08:44:35.22#ibcon#about to read 3, iclass 18, count 0 2006.285.08:44:35.24#ibcon#read 3, iclass 18, count 0 2006.285.08:44:35.24#ibcon#about to read 4, iclass 18, count 0 2006.285.08:44:35.24#ibcon#read 4, iclass 18, count 0 2006.285.08:44:35.24#ibcon#about to read 5, iclass 18, count 0 2006.285.08:44:35.24#ibcon#read 5, iclass 18, count 0 2006.285.08:44:35.24#ibcon#about to read 6, iclass 18, count 0 2006.285.08:44:35.24#ibcon#read 6, iclass 18, count 0 2006.285.08:44:35.24#ibcon#end of sib2, iclass 18, count 0 2006.285.08:44:35.24#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:44:35.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:44:35.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:44:35.24#ibcon#*before write, iclass 18, count 0 2006.285.08:44:35.24#ibcon#enter sib2, iclass 18, count 0 2006.285.08:44:35.24#ibcon#flushed, iclass 18, count 0 2006.285.08:44:35.24#ibcon#about to write, iclass 18, count 0 2006.285.08:44:35.24#ibcon#wrote, iclass 18, count 0 2006.285.08:44:35.24#ibcon#about to read 3, iclass 18, count 0 2006.285.08:44:35.28#ibcon#read 3, iclass 18, count 0 2006.285.08:44:35.28#ibcon#about to read 4, iclass 18, count 0 2006.285.08:44:35.28#ibcon#read 4, iclass 18, count 0 2006.285.08:44:35.28#ibcon#about to read 5, iclass 18, count 0 2006.285.08:44:35.28#ibcon#read 5, iclass 18, count 0 2006.285.08:44:35.28#ibcon#about to read 6, iclass 18, count 0 2006.285.08:44:35.28#ibcon#read 6, iclass 18, count 0 2006.285.08:44:35.28#ibcon#end of sib2, iclass 18, count 0 2006.285.08:44:35.28#ibcon#*after write, iclass 18, count 0 2006.285.08:44:35.28#ibcon#*before return 0, iclass 18, count 0 2006.285.08:44:35.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:44:35.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:44:35.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:44:35.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:44:35.28$vck44/va=5,3 2006.285.08:44:35.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.08:44:35.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.08:44:35.28#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:35.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:44:35.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:44:35.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:44:35.34#ibcon#enter wrdev, iclass 20, count 2 2006.285.08:44:35.34#ibcon#first serial, iclass 20, count 2 2006.285.08:44:35.34#ibcon#enter sib2, iclass 20, count 2 2006.285.08:44:35.34#ibcon#flushed, iclass 20, count 2 2006.285.08:44:35.34#ibcon#about to write, iclass 20, count 2 2006.285.08:44:35.34#ibcon#wrote, iclass 20, count 2 2006.285.08:44:35.34#ibcon#about to read 3, iclass 20, count 2 2006.285.08:44:35.36#ibcon#read 3, iclass 20, count 2 2006.285.08:44:35.36#ibcon#about to read 4, iclass 20, count 2 2006.285.08:44:35.36#ibcon#read 4, iclass 20, count 2 2006.285.08:44:35.36#ibcon#about to read 5, iclass 20, count 2 2006.285.08:44:35.36#ibcon#read 5, iclass 20, count 2 2006.285.08:44:35.36#ibcon#about to read 6, iclass 20, count 2 2006.285.08:44:35.36#ibcon#read 6, iclass 20, count 2 2006.285.08:44:35.36#ibcon#end of sib2, iclass 20, count 2 2006.285.08:44:35.36#ibcon#*mode == 0, iclass 20, count 2 2006.285.08:44:35.36#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.08:44:35.36#ibcon#[25=AT05-03\r\n] 2006.285.08:44:35.36#ibcon#*before write, iclass 20, count 2 2006.285.08:44:35.36#ibcon#enter sib2, iclass 20, count 2 2006.285.08:44:35.36#ibcon#flushed, iclass 20, count 2 2006.285.08:44:35.36#ibcon#about to write, iclass 20, count 2 2006.285.08:44:35.36#ibcon#wrote, iclass 20, count 2 2006.285.08:44:35.36#ibcon#about to read 3, iclass 20, count 2 2006.285.08:44:35.39#ibcon#read 3, iclass 20, count 2 2006.285.08:44:35.39#ibcon#about to read 4, iclass 20, count 2 2006.285.08:44:35.39#ibcon#read 4, iclass 20, count 2 2006.285.08:44:35.39#ibcon#about to read 5, iclass 20, count 2 2006.285.08:44:35.39#ibcon#read 5, iclass 20, count 2 2006.285.08:44:35.39#ibcon#about to read 6, iclass 20, count 2 2006.285.08:44:35.39#ibcon#read 6, iclass 20, count 2 2006.285.08:44:35.39#ibcon#end of sib2, iclass 20, count 2 2006.285.08:44:35.39#ibcon#*after write, iclass 20, count 2 2006.285.08:44:35.39#ibcon#*before return 0, iclass 20, count 2 2006.285.08:44:35.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:44:35.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:44:35.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.08:44:35.39#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:35.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:44:35.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:44:35.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:44:35.51#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:44:35.51#ibcon#first serial, iclass 20, count 0 2006.285.08:44:35.51#ibcon#enter sib2, iclass 20, count 0 2006.285.08:44:35.51#ibcon#flushed, iclass 20, count 0 2006.285.08:44:35.51#ibcon#about to write, iclass 20, count 0 2006.285.08:44:35.51#ibcon#wrote, iclass 20, count 0 2006.285.08:44:35.51#ibcon#about to read 3, iclass 20, count 0 2006.285.08:44:35.53#ibcon#read 3, iclass 20, count 0 2006.285.08:44:35.53#ibcon#about to read 4, iclass 20, count 0 2006.285.08:44:35.53#ibcon#read 4, iclass 20, count 0 2006.285.08:44:35.53#ibcon#about to read 5, iclass 20, count 0 2006.285.08:44:35.53#ibcon#read 5, iclass 20, count 0 2006.285.08:44:35.53#ibcon#about to read 6, iclass 20, count 0 2006.285.08:44:35.53#ibcon#read 6, iclass 20, count 0 2006.285.08:44:35.53#ibcon#end of sib2, iclass 20, count 0 2006.285.08:44:35.53#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:44:35.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:44:35.53#ibcon#[25=USB\r\n] 2006.285.08:44:35.53#ibcon#*before write, iclass 20, count 0 2006.285.08:44:35.53#ibcon#enter sib2, iclass 20, count 0 2006.285.08:44:35.53#ibcon#flushed, iclass 20, count 0 2006.285.08:44:35.53#ibcon#about to write, iclass 20, count 0 2006.285.08:44:35.53#ibcon#wrote, iclass 20, count 0 2006.285.08:44:35.53#ibcon#about to read 3, iclass 20, count 0 2006.285.08:44:35.56#ibcon#read 3, iclass 20, count 0 2006.285.08:44:35.56#ibcon#about to read 4, iclass 20, count 0 2006.285.08:44:35.56#ibcon#read 4, iclass 20, count 0 2006.285.08:44:35.56#ibcon#about to read 5, iclass 20, count 0 2006.285.08:44:35.56#ibcon#read 5, iclass 20, count 0 2006.285.08:44:35.56#ibcon#about to read 6, iclass 20, count 0 2006.285.08:44:35.56#ibcon#read 6, iclass 20, count 0 2006.285.08:44:35.56#ibcon#end of sib2, iclass 20, count 0 2006.285.08:44:35.56#ibcon#*after write, iclass 20, count 0 2006.285.08:44:35.56#ibcon#*before return 0, iclass 20, count 0 2006.285.08:44:35.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:44:35.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:44:35.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:44:35.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:44:35.56$vck44/valo=6,814.99 2006.285.08:44:35.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.08:44:35.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.08:44:35.56#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:35.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:44:35.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:44:35.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:44:35.56#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:44:35.56#ibcon#first serial, iclass 22, count 0 2006.285.08:44:35.56#ibcon#enter sib2, iclass 22, count 0 2006.285.08:44:35.56#ibcon#flushed, iclass 22, count 0 2006.285.08:44:35.56#ibcon#about to write, iclass 22, count 0 2006.285.08:44:35.56#ibcon#wrote, iclass 22, count 0 2006.285.08:44:35.56#ibcon#about to read 3, iclass 22, count 0 2006.285.08:44:35.58#ibcon#read 3, iclass 22, count 0 2006.285.08:44:35.58#ibcon#about to read 4, iclass 22, count 0 2006.285.08:44:35.58#ibcon#read 4, iclass 22, count 0 2006.285.08:44:35.58#ibcon#about to read 5, iclass 22, count 0 2006.285.08:44:35.58#ibcon#read 5, iclass 22, count 0 2006.285.08:44:35.58#ibcon#about to read 6, iclass 22, count 0 2006.285.08:44:35.58#ibcon#read 6, iclass 22, count 0 2006.285.08:44:35.58#ibcon#end of sib2, iclass 22, count 0 2006.285.08:44:35.58#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:44:35.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:44:35.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:44:35.58#ibcon#*before write, iclass 22, count 0 2006.285.08:44:35.58#ibcon#enter sib2, iclass 22, count 0 2006.285.08:44:35.58#ibcon#flushed, iclass 22, count 0 2006.285.08:44:35.58#ibcon#about to write, iclass 22, count 0 2006.285.08:44:35.58#ibcon#wrote, iclass 22, count 0 2006.285.08:44:35.58#ibcon#about to read 3, iclass 22, count 0 2006.285.08:44:35.62#ibcon#read 3, iclass 22, count 0 2006.285.08:44:35.62#ibcon#about to read 4, iclass 22, count 0 2006.285.08:44:35.62#ibcon#read 4, iclass 22, count 0 2006.285.08:44:35.62#ibcon#about to read 5, iclass 22, count 0 2006.285.08:44:35.62#ibcon#read 5, iclass 22, count 0 2006.285.08:44:35.62#ibcon#about to read 6, iclass 22, count 0 2006.285.08:44:35.62#ibcon#read 6, iclass 22, count 0 2006.285.08:44:35.62#ibcon#end of sib2, iclass 22, count 0 2006.285.08:44:35.62#ibcon#*after write, iclass 22, count 0 2006.285.08:44:35.62#ibcon#*before return 0, iclass 22, count 0 2006.285.08:44:35.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:44:35.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:44:35.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:44:35.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:44:35.62$vck44/va=6,4 2006.285.08:44:35.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.08:44:35.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.08:44:35.62#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:35.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:44:35.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:44:35.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:44:35.68#ibcon#enter wrdev, iclass 24, count 2 2006.285.08:44:35.68#ibcon#first serial, iclass 24, count 2 2006.285.08:44:35.68#ibcon#enter sib2, iclass 24, count 2 2006.285.08:44:35.68#ibcon#flushed, iclass 24, count 2 2006.285.08:44:35.68#ibcon#about to write, iclass 24, count 2 2006.285.08:44:35.68#ibcon#wrote, iclass 24, count 2 2006.285.08:44:35.68#ibcon#about to read 3, iclass 24, count 2 2006.285.08:44:35.70#ibcon#read 3, iclass 24, count 2 2006.285.08:44:35.70#ibcon#about to read 4, iclass 24, count 2 2006.285.08:44:35.70#ibcon#read 4, iclass 24, count 2 2006.285.08:44:35.70#ibcon#about to read 5, iclass 24, count 2 2006.285.08:44:35.70#ibcon#read 5, iclass 24, count 2 2006.285.08:44:35.70#ibcon#about to read 6, iclass 24, count 2 2006.285.08:44:35.70#ibcon#read 6, iclass 24, count 2 2006.285.08:44:35.70#ibcon#end of sib2, iclass 24, count 2 2006.285.08:44:35.70#ibcon#*mode == 0, iclass 24, count 2 2006.285.08:44:35.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.08:44:35.70#ibcon#[25=AT06-04\r\n] 2006.285.08:44:35.70#ibcon#*before write, iclass 24, count 2 2006.285.08:44:35.70#ibcon#enter sib2, iclass 24, count 2 2006.285.08:44:35.70#ibcon#flushed, iclass 24, count 2 2006.285.08:44:35.70#ibcon#about to write, iclass 24, count 2 2006.285.08:44:35.70#ibcon#wrote, iclass 24, count 2 2006.285.08:44:35.70#ibcon#about to read 3, iclass 24, count 2 2006.285.08:44:35.73#ibcon#read 3, iclass 24, count 2 2006.285.08:44:35.73#ibcon#about to read 4, iclass 24, count 2 2006.285.08:44:35.73#ibcon#read 4, iclass 24, count 2 2006.285.08:44:35.73#ibcon#about to read 5, iclass 24, count 2 2006.285.08:44:35.73#ibcon#read 5, iclass 24, count 2 2006.285.08:44:35.73#ibcon#about to read 6, iclass 24, count 2 2006.285.08:44:35.73#ibcon#read 6, iclass 24, count 2 2006.285.08:44:35.73#ibcon#end of sib2, iclass 24, count 2 2006.285.08:44:35.73#ibcon#*after write, iclass 24, count 2 2006.285.08:44:35.73#ibcon#*before return 0, iclass 24, count 2 2006.285.08:44:35.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:44:35.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:44:35.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.08:44:35.73#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:35.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:44:35.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:44:35.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:44:35.85#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:44:35.85#ibcon#first serial, iclass 24, count 0 2006.285.08:44:35.85#ibcon#enter sib2, iclass 24, count 0 2006.285.08:44:35.85#ibcon#flushed, iclass 24, count 0 2006.285.08:44:35.85#ibcon#about to write, iclass 24, count 0 2006.285.08:44:35.85#ibcon#wrote, iclass 24, count 0 2006.285.08:44:35.85#ibcon#about to read 3, iclass 24, count 0 2006.285.08:44:35.87#ibcon#read 3, iclass 24, count 0 2006.285.08:44:35.87#ibcon#about to read 4, iclass 24, count 0 2006.285.08:44:35.87#ibcon#read 4, iclass 24, count 0 2006.285.08:44:35.87#ibcon#about to read 5, iclass 24, count 0 2006.285.08:44:35.87#ibcon#read 5, iclass 24, count 0 2006.285.08:44:35.87#ibcon#about to read 6, iclass 24, count 0 2006.285.08:44:35.87#ibcon#read 6, iclass 24, count 0 2006.285.08:44:35.87#ibcon#end of sib2, iclass 24, count 0 2006.285.08:44:35.87#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:44:35.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:44:35.87#ibcon#[25=USB\r\n] 2006.285.08:44:35.87#ibcon#*before write, iclass 24, count 0 2006.285.08:44:35.87#ibcon#enter sib2, iclass 24, count 0 2006.285.08:44:35.87#ibcon#flushed, iclass 24, count 0 2006.285.08:44:35.87#ibcon#about to write, iclass 24, count 0 2006.285.08:44:35.87#ibcon#wrote, iclass 24, count 0 2006.285.08:44:35.87#ibcon#about to read 3, iclass 24, count 0 2006.285.08:44:35.90#ibcon#read 3, iclass 24, count 0 2006.285.08:44:35.90#ibcon#about to read 4, iclass 24, count 0 2006.285.08:44:35.90#ibcon#read 4, iclass 24, count 0 2006.285.08:44:35.90#ibcon#about to read 5, iclass 24, count 0 2006.285.08:44:35.90#ibcon#read 5, iclass 24, count 0 2006.285.08:44:35.90#ibcon#about to read 6, iclass 24, count 0 2006.285.08:44:35.90#ibcon#read 6, iclass 24, count 0 2006.285.08:44:35.90#ibcon#end of sib2, iclass 24, count 0 2006.285.08:44:35.90#ibcon#*after write, iclass 24, count 0 2006.285.08:44:35.90#ibcon#*before return 0, iclass 24, count 0 2006.285.08:44:35.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:44:35.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:44:35.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:44:35.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:44:35.90$vck44/valo=7,864.99 2006.285.08:44:35.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.08:44:35.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.08:44:35.90#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:35.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:44:35.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:44:35.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:44:35.90#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:44:35.90#ibcon#first serial, iclass 26, count 0 2006.285.08:44:35.90#ibcon#enter sib2, iclass 26, count 0 2006.285.08:44:35.90#ibcon#flushed, iclass 26, count 0 2006.285.08:44:35.90#ibcon#about to write, iclass 26, count 0 2006.285.08:44:35.90#ibcon#wrote, iclass 26, count 0 2006.285.08:44:35.90#ibcon#about to read 3, iclass 26, count 0 2006.285.08:44:35.92#ibcon#read 3, iclass 26, count 0 2006.285.08:44:35.92#ibcon#about to read 4, iclass 26, count 0 2006.285.08:44:35.92#ibcon#read 4, iclass 26, count 0 2006.285.08:44:35.92#ibcon#about to read 5, iclass 26, count 0 2006.285.08:44:35.92#ibcon#read 5, iclass 26, count 0 2006.285.08:44:35.92#ibcon#about to read 6, iclass 26, count 0 2006.285.08:44:35.92#ibcon#read 6, iclass 26, count 0 2006.285.08:44:35.92#ibcon#end of sib2, iclass 26, count 0 2006.285.08:44:35.92#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:44:35.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:44:35.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:44:35.92#ibcon#*before write, iclass 26, count 0 2006.285.08:44:35.92#ibcon#enter sib2, iclass 26, count 0 2006.285.08:44:35.92#ibcon#flushed, iclass 26, count 0 2006.285.08:44:35.92#ibcon#about to write, iclass 26, count 0 2006.285.08:44:35.92#ibcon#wrote, iclass 26, count 0 2006.285.08:44:35.92#ibcon#about to read 3, iclass 26, count 0 2006.285.08:44:35.96#ibcon#read 3, iclass 26, count 0 2006.285.08:44:35.96#ibcon#about to read 4, iclass 26, count 0 2006.285.08:44:35.96#ibcon#read 4, iclass 26, count 0 2006.285.08:44:35.96#ibcon#about to read 5, iclass 26, count 0 2006.285.08:44:35.96#ibcon#read 5, iclass 26, count 0 2006.285.08:44:35.96#ibcon#about to read 6, iclass 26, count 0 2006.285.08:44:35.96#ibcon#read 6, iclass 26, count 0 2006.285.08:44:35.96#ibcon#end of sib2, iclass 26, count 0 2006.285.08:44:35.96#ibcon#*after write, iclass 26, count 0 2006.285.08:44:35.96#ibcon#*before return 0, iclass 26, count 0 2006.285.08:44:35.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:44:35.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:44:35.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:44:35.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:44:35.96$vck44/va=7,4 2006.285.08:44:35.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.08:44:35.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.08:44:35.96#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:35.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:44:36.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:44:36.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:44:36.02#ibcon#enter wrdev, iclass 28, count 2 2006.285.08:44:36.02#ibcon#first serial, iclass 28, count 2 2006.285.08:44:36.02#ibcon#enter sib2, iclass 28, count 2 2006.285.08:44:36.02#ibcon#flushed, iclass 28, count 2 2006.285.08:44:36.02#ibcon#about to write, iclass 28, count 2 2006.285.08:44:36.02#ibcon#wrote, iclass 28, count 2 2006.285.08:44:36.02#ibcon#about to read 3, iclass 28, count 2 2006.285.08:44:36.04#ibcon#read 3, iclass 28, count 2 2006.285.08:44:36.04#ibcon#about to read 4, iclass 28, count 2 2006.285.08:44:36.04#ibcon#read 4, iclass 28, count 2 2006.285.08:44:36.04#ibcon#about to read 5, iclass 28, count 2 2006.285.08:44:36.04#ibcon#read 5, iclass 28, count 2 2006.285.08:44:36.04#ibcon#about to read 6, iclass 28, count 2 2006.285.08:44:36.04#ibcon#read 6, iclass 28, count 2 2006.285.08:44:36.04#ibcon#end of sib2, iclass 28, count 2 2006.285.08:44:36.04#ibcon#*mode == 0, iclass 28, count 2 2006.285.08:44:36.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.08:44:36.04#ibcon#[25=AT07-04\r\n] 2006.285.08:44:36.04#ibcon#*before write, iclass 28, count 2 2006.285.08:44:36.04#ibcon#enter sib2, iclass 28, count 2 2006.285.08:44:36.04#ibcon#flushed, iclass 28, count 2 2006.285.08:44:36.04#ibcon#about to write, iclass 28, count 2 2006.285.08:44:36.04#ibcon#wrote, iclass 28, count 2 2006.285.08:44:36.04#ibcon#about to read 3, iclass 28, count 2 2006.285.08:44:36.07#ibcon#read 3, iclass 28, count 2 2006.285.08:44:36.07#ibcon#about to read 4, iclass 28, count 2 2006.285.08:44:36.07#ibcon#read 4, iclass 28, count 2 2006.285.08:44:36.07#ibcon#about to read 5, iclass 28, count 2 2006.285.08:44:36.07#ibcon#read 5, iclass 28, count 2 2006.285.08:44:36.07#ibcon#about to read 6, iclass 28, count 2 2006.285.08:44:36.07#ibcon#read 6, iclass 28, count 2 2006.285.08:44:36.07#ibcon#end of sib2, iclass 28, count 2 2006.285.08:44:36.07#ibcon#*after write, iclass 28, count 2 2006.285.08:44:36.07#ibcon#*before return 0, iclass 28, count 2 2006.285.08:44:36.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:44:36.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:44:36.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.08:44:36.07#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:36.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:44:36.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:44:36.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:44:36.19#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:44:36.19#ibcon#first serial, iclass 28, count 0 2006.285.08:44:36.19#ibcon#enter sib2, iclass 28, count 0 2006.285.08:44:36.19#ibcon#flushed, iclass 28, count 0 2006.285.08:44:36.19#ibcon#about to write, iclass 28, count 0 2006.285.08:44:36.19#ibcon#wrote, iclass 28, count 0 2006.285.08:44:36.19#ibcon#about to read 3, iclass 28, count 0 2006.285.08:44:36.21#ibcon#read 3, iclass 28, count 0 2006.285.08:44:36.21#ibcon#about to read 4, iclass 28, count 0 2006.285.08:44:36.21#ibcon#read 4, iclass 28, count 0 2006.285.08:44:36.21#ibcon#about to read 5, iclass 28, count 0 2006.285.08:44:36.21#ibcon#read 5, iclass 28, count 0 2006.285.08:44:36.21#ibcon#about to read 6, iclass 28, count 0 2006.285.08:44:36.21#ibcon#read 6, iclass 28, count 0 2006.285.08:44:36.21#ibcon#end of sib2, iclass 28, count 0 2006.285.08:44:36.21#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:44:36.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:44:36.21#ibcon#[25=USB\r\n] 2006.285.08:44:36.21#ibcon#*before write, iclass 28, count 0 2006.285.08:44:36.21#ibcon#enter sib2, iclass 28, count 0 2006.285.08:44:36.21#ibcon#flushed, iclass 28, count 0 2006.285.08:44:36.21#ibcon#about to write, iclass 28, count 0 2006.285.08:44:36.21#ibcon#wrote, iclass 28, count 0 2006.285.08:44:36.21#ibcon#about to read 3, iclass 28, count 0 2006.285.08:44:36.24#ibcon#read 3, iclass 28, count 0 2006.285.08:44:36.24#ibcon#about to read 4, iclass 28, count 0 2006.285.08:44:36.24#ibcon#read 4, iclass 28, count 0 2006.285.08:44:36.24#ibcon#about to read 5, iclass 28, count 0 2006.285.08:44:36.24#ibcon#read 5, iclass 28, count 0 2006.285.08:44:36.24#ibcon#about to read 6, iclass 28, count 0 2006.285.08:44:36.24#ibcon#read 6, iclass 28, count 0 2006.285.08:44:36.24#ibcon#end of sib2, iclass 28, count 0 2006.285.08:44:36.24#ibcon#*after write, iclass 28, count 0 2006.285.08:44:36.24#ibcon#*before return 0, iclass 28, count 0 2006.285.08:44:36.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:44:36.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:44:36.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:44:36.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:44:36.24$vck44/valo=8,884.99 2006.285.08:44:36.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.08:44:36.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.08:44:36.24#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:36.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:44:36.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:44:36.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:44:36.24#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:44:36.24#ibcon#first serial, iclass 30, count 0 2006.285.08:44:36.24#ibcon#enter sib2, iclass 30, count 0 2006.285.08:44:36.24#ibcon#flushed, iclass 30, count 0 2006.285.08:44:36.24#ibcon#about to write, iclass 30, count 0 2006.285.08:44:36.24#ibcon#wrote, iclass 30, count 0 2006.285.08:44:36.24#ibcon#about to read 3, iclass 30, count 0 2006.285.08:44:36.26#ibcon#read 3, iclass 30, count 0 2006.285.08:44:36.26#ibcon#about to read 4, iclass 30, count 0 2006.285.08:44:36.26#ibcon#read 4, iclass 30, count 0 2006.285.08:44:36.26#ibcon#about to read 5, iclass 30, count 0 2006.285.08:44:36.26#ibcon#read 5, iclass 30, count 0 2006.285.08:44:36.26#ibcon#about to read 6, iclass 30, count 0 2006.285.08:44:36.26#ibcon#read 6, iclass 30, count 0 2006.285.08:44:36.26#ibcon#end of sib2, iclass 30, count 0 2006.285.08:44:36.26#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:44:36.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:44:36.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:44:36.26#ibcon#*before write, iclass 30, count 0 2006.285.08:44:36.26#ibcon#enter sib2, iclass 30, count 0 2006.285.08:44:36.26#ibcon#flushed, iclass 30, count 0 2006.285.08:44:36.26#ibcon#about to write, iclass 30, count 0 2006.285.08:44:36.26#ibcon#wrote, iclass 30, count 0 2006.285.08:44:36.26#ibcon#about to read 3, iclass 30, count 0 2006.285.08:44:36.30#ibcon#read 3, iclass 30, count 0 2006.285.08:44:36.30#ibcon#about to read 4, iclass 30, count 0 2006.285.08:44:36.30#ibcon#read 4, iclass 30, count 0 2006.285.08:44:36.30#ibcon#about to read 5, iclass 30, count 0 2006.285.08:44:36.30#ibcon#read 5, iclass 30, count 0 2006.285.08:44:36.30#ibcon#about to read 6, iclass 30, count 0 2006.285.08:44:36.30#ibcon#read 6, iclass 30, count 0 2006.285.08:44:36.30#ibcon#end of sib2, iclass 30, count 0 2006.285.08:44:36.30#ibcon#*after write, iclass 30, count 0 2006.285.08:44:36.30#ibcon#*before return 0, iclass 30, count 0 2006.285.08:44:36.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:44:36.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:44:36.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:44:36.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:44:36.30$vck44/va=8,3 2006.285.08:44:36.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.08:44:36.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.08:44:36.30#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:36.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:44:36.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:44:36.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:44:36.36#ibcon#enter wrdev, iclass 32, count 2 2006.285.08:44:36.36#ibcon#first serial, iclass 32, count 2 2006.285.08:44:36.36#ibcon#enter sib2, iclass 32, count 2 2006.285.08:44:36.36#ibcon#flushed, iclass 32, count 2 2006.285.08:44:36.36#ibcon#about to write, iclass 32, count 2 2006.285.08:44:36.36#ibcon#wrote, iclass 32, count 2 2006.285.08:44:36.36#ibcon#about to read 3, iclass 32, count 2 2006.285.08:44:36.38#ibcon#read 3, iclass 32, count 2 2006.285.08:44:36.38#ibcon#about to read 4, iclass 32, count 2 2006.285.08:44:36.38#ibcon#read 4, iclass 32, count 2 2006.285.08:44:36.38#ibcon#about to read 5, iclass 32, count 2 2006.285.08:44:36.38#ibcon#read 5, iclass 32, count 2 2006.285.08:44:36.38#ibcon#about to read 6, iclass 32, count 2 2006.285.08:44:36.38#ibcon#read 6, iclass 32, count 2 2006.285.08:44:36.38#ibcon#end of sib2, iclass 32, count 2 2006.285.08:44:36.38#ibcon#*mode == 0, iclass 32, count 2 2006.285.08:44:36.38#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.08:44:36.38#ibcon#[25=AT08-03\r\n] 2006.285.08:44:36.38#ibcon#*before write, iclass 32, count 2 2006.285.08:44:36.38#ibcon#enter sib2, iclass 32, count 2 2006.285.08:44:36.38#ibcon#flushed, iclass 32, count 2 2006.285.08:44:36.38#ibcon#about to write, iclass 32, count 2 2006.285.08:44:36.38#ibcon#wrote, iclass 32, count 2 2006.285.08:44:36.38#ibcon#about to read 3, iclass 32, count 2 2006.285.08:44:36.41#ibcon#read 3, iclass 32, count 2 2006.285.08:44:36.41#ibcon#about to read 4, iclass 32, count 2 2006.285.08:44:36.41#ibcon#read 4, iclass 32, count 2 2006.285.08:44:36.41#ibcon#about to read 5, iclass 32, count 2 2006.285.08:44:36.41#ibcon#read 5, iclass 32, count 2 2006.285.08:44:36.41#ibcon#about to read 6, iclass 32, count 2 2006.285.08:44:36.41#ibcon#read 6, iclass 32, count 2 2006.285.08:44:36.41#ibcon#end of sib2, iclass 32, count 2 2006.285.08:44:36.41#ibcon#*after write, iclass 32, count 2 2006.285.08:44:36.41#ibcon#*before return 0, iclass 32, count 2 2006.285.08:44:36.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:44:36.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.08:44:36.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.08:44:36.41#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:36.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:44:36.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:44:36.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:44:36.53#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:44:36.53#ibcon#first serial, iclass 32, count 0 2006.285.08:44:36.53#ibcon#enter sib2, iclass 32, count 0 2006.285.08:44:36.53#ibcon#flushed, iclass 32, count 0 2006.285.08:44:36.53#ibcon#about to write, iclass 32, count 0 2006.285.08:44:36.53#ibcon#wrote, iclass 32, count 0 2006.285.08:44:36.53#ibcon#about to read 3, iclass 32, count 0 2006.285.08:44:36.55#ibcon#read 3, iclass 32, count 0 2006.285.08:44:36.55#ibcon#about to read 4, iclass 32, count 0 2006.285.08:44:36.55#ibcon#read 4, iclass 32, count 0 2006.285.08:44:36.55#ibcon#about to read 5, iclass 32, count 0 2006.285.08:44:36.55#ibcon#read 5, iclass 32, count 0 2006.285.08:44:36.55#ibcon#about to read 6, iclass 32, count 0 2006.285.08:44:36.55#ibcon#read 6, iclass 32, count 0 2006.285.08:44:36.55#ibcon#end of sib2, iclass 32, count 0 2006.285.08:44:36.55#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:44:36.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:44:36.55#ibcon#[25=USB\r\n] 2006.285.08:44:36.55#ibcon#*before write, iclass 32, count 0 2006.285.08:44:36.55#ibcon#enter sib2, iclass 32, count 0 2006.285.08:44:36.55#ibcon#flushed, iclass 32, count 0 2006.285.08:44:36.55#ibcon#about to write, iclass 32, count 0 2006.285.08:44:36.55#ibcon#wrote, iclass 32, count 0 2006.285.08:44:36.55#ibcon#about to read 3, iclass 32, count 0 2006.285.08:44:36.58#ibcon#read 3, iclass 32, count 0 2006.285.08:44:36.58#ibcon#about to read 4, iclass 32, count 0 2006.285.08:44:36.58#ibcon#read 4, iclass 32, count 0 2006.285.08:44:36.58#ibcon#about to read 5, iclass 32, count 0 2006.285.08:44:36.58#ibcon#read 5, iclass 32, count 0 2006.285.08:44:36.58#ibcon#about to read 6, iclass 32, count 0 2006.285.08:44:36.58#ibcon#read 6, iclass 32, count 0 2006.285.08:44:36.58#ibcon#end of sib2, iclass 32, count 0 2006.285.08:44:36.58#ibcon#*after write, iclass 32, count 0 2006.285.08:44:36.58#ibcon#*before return 0, iclass 32, count 0 2006.285.08:44:36.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:44:36.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.08:44:36.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:44:36.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:44:36.58$vck44/vblo=1,629.99 2006.285.08:44:36.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.08:44:36.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.08:44:36.58#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:36.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:44:36.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:44:36.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:44:36.58#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:44:36.58#ibcon#first serial, iclass 34, count 0 2006.285.08:44:36.58#ibcon#enter sib2, iclass 34, count 0 2006.285.08:44:36.58#ibcon#flushed, iclass 34, count 0 2006.285.08:44:36.58#ibcon#about to write, iclass 34, count 0 2006.285.08:44:36.58#ibcon#wrote, iclass 34, count 0 2006.285.08:44:36.58#ibcon#about to read 3, iclass 34, count 0 2006.285.08:44:36.60#ibcon#read 3, iclass 34, count 0 2006.285.08:44:36.60#ibcon#about to read 4, iclass 34, count 0 2006.285.08:44:36.60#ibcon#read 4, iclass 34, count 0 2006.285.08:44:36.60#ibcon#about to read 5, iclass 34, count 0 2006.285.08:44:36.60#ibcon#read 5, iclass 34, count 0 2006.285.08:44:36.60#ibcon#about to read 6, iclass 34, count 0 2006.285.08:44:36.60#ibcon#read 6, iclass 34, count 0 2006.285.08:44:36.60#ibcon#end of sib2, iclass 34, count 0 2006.285.08:44:36.60#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:44:36.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:44:36.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:44:36.60#ibcon#*before write, iclass 34, count 0 2006.285.08:44:36.60#ibcon#enter sib2, iclass 34, count 0 2006.285.08:44:36.60#ibcon#flushed, iclass 34, count 0 2006.285.08:44:36.60#ibcon#about to write, iclass 34, count 0 2006.285.08:44:36.60#ibcon#wrote, iclass 34, count 0 2006.285.08:44:36.60#ibcon#about to read 3, iclass 34, count 0 2006.285.08:44:36.64#ibcon#read 3, iclass 34, count 0 2006.285.08:44:36.64#ibcon#about to read 4, iclass 34, count 0 2006.285.08:44:36.64#ibcon#read 4, iclass 34, count 0 2006.285.08:44:36.64#ibcon#about to read 5, iclass 34, count 0 2006.285.08:44:36.64#ibcon#read 5, iclass 34, count 0 2006.285.08:44:36.64#ibcon#about to read 6, iclass 34, count 0 2006.285.08:44:36.64#ibcon#read 6, iclass 34, count 0 2006.285.08:44:36.64#ibcon#end of sib2, iclass 34, count 0 2006.285.08:44:36.64#ibcon#*after write, iclass 34, count 0 2006.285.08:44:36.64#ibcon#*before return 0, iclass 34, count 0 2006.285.08:44:36.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:44:36.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.08:44:36.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:44:36.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:44:36.64$vck44/vb=1,4 2006.285.08:44:36.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.08:44:36.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.08:44:36.64#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:36.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:44:36.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:44:36.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:44:36.64#ibcon#enter wrdev, iclass 36, count 2 2006.285.08:44:36.64#ibcon#first serial, iclass 36, count 2 2006.285.08:44:36.64#ibcon#enter sib2, iclass 36, count 2 2006.285.08:44:36.64#ibcon#flushed, iclass 36, count 2 2006.285.08:44:36.64#ibcon#about to write, iclass 36, count 2 2006.285.08:44:36.64#ibcon#wrote, iclass 36, count 2 2006.285.08:44:36.64#ibcon#about to read 3, iclass 36, count 2 2006.285.08:44:36.66#ibcon#read 3, iclass 36, count 2 2006.285.08:44:36.66#ibcon#about to read 4, iclass 36, count 2 2006.285.08:44:36.66#ibcon#read 4, iclass 36, count 2 2006.285.08:44:36.66#ibcon#about to read 5, iclass 36, count 2 2006.285.08:44:36.66#ibcon#read 5, iclass 36, count 2 2006.285.08:44:36.66#ibcon#about to read 6, iclass 36, count 2 2006.285.08:44:36.66#ibcon#read 6, iclass 36, count 2 2006.285.08:44:36.66#ibcon#end of sib2, iclass 36, count 2 2006.285.08:44:36.66#ibcon#*mode == 0, iclass 36, count 2 2006.285.08:44:36.66#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.08:44:36.66#ibcon#[27=AT01-04\r\n] 2006.285.08:44:36.66#ibcon#*before write, iclass 36, count 2 2006.285.08:44:36.66#ibcon#enter sib2, iclass 36, count 2 2006.285.08:44:36.66#ibcon#flushed, iclass 36, count 2 2006.285.08:44:36.66#ibcon#about to write, iclass 36, count 2 2006.285.08:44:36.66#ibcon#wrote, iclass 36, count 2 2006.285.08:44:36.66#ibcon#about to read 3, iclass 36, count 2 2006.285.08:44:36.69#ibcon#read 3, iclass 36, count 2 2006.285.08:44:36.69#ibcon#about to read 4, iclass 36, count 2 2006.285.08:44:36.69#ibcon#read 4, iclass 36, count 2 2006.285.08:44:36.69#ibcon#about to read 5, iclass 36, count 2 2006.285.08:44:36.69#ibcon#read 5, iclass 36, count 2 2006.285.08:44:36.69#ibcon#about to read 6, iclass 36, count 2 2006.285.08:44:36.69#ibcon#read 6, iclass 36, count 2 2006.285.08:44:36.69#ibcon#end of sib2, iclass 36, count 2 2006.285.08:44:36.69#ibcon#*after write, iclass 36, count 2 2006.285.08:44:36.69#ibcon#*before return 0, iclass 36, count 2 2006.285.08:44:36.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:44:36.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.08:44:36.69#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.08:44:36.69#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:36.69#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:44:36.81#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:44:36.81#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:44:36.81#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:44:36.81#ibcon#first serial, iclass 36, count 0 2006.285.08:44:36.81#ibcon#enter sib2, iclass 36, count 0 2006.285.08:44:36.81#ibcon#flushed, iclass 36, count 0 2006.285.08:44:36.81#ibcon#about to write, iclass 36, count 0 2006.285.08:44:36.81#ibcon#wrote, iclass 36, count 0 2006.285.08:44:36.81#ibcon#about to read 3, iclass 36, count 0 2006.285.08:44:36.83#ibcon#read 3, iclass 36, count 0 2006.285.08:44:36.83#ibcon#about to read 4, iclass 36, count 0 2006.285.08:44:36.83#ibcon#read 4, iclass 36, count 0 2006.285.08:44:36.83#ibcon#about to read 5, iclass 36, count 0 2006.285.08:44:36.83#ibcon#read 5, iclass 36, count 0 2006.285.08:44:36.83#ibcon#about to read 6, iclass 36, count 0 2006.285.08:44:36.83#ibcon#read 6, iclass 36, count 0 2006.285.08:44:36.83#ibcon#end of sib2, iclass 36, count 0 2006.285.08:44:36.83#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:44:36.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:44:36.83#ibcon#[27=USB\r\n] 2006.285.08:44:36.83#ibcon#*before write, iclass 36, count 0 2006.285.08:44:36.83#ibcon#enter sib2, iclass 36, count 0 2006.285.08:44:36.83#ibcon#flushed, iclass 36, count 0 2006.285.08:44:36.83#ibcon#about to write, iclass 36, count 0 2006.285.08:44:36.83#ibcon#wrote, iclass 36, count 0 2006.285.08:44:36.83#ibcon#about to read 3, iclass 36, count 0 2006.285.08:44:36.86#ibcon#read 3, iclass 36, count 0 2006.285.08:44:36.86#ibcon#about to read 4, iclass 36, count 0 2006.285.08:44:36.86#ibcon#read 4, iclass 36, count 0 2006.285.08:44:36.86#ibcon#about to read 5, iclass 36, count 0 2006.285.08:44:36.86#ibcon#read 5, iclass 36, count 0 2006.285.08:44:36.86#ibcon#about to read 6, iclass 36, count 0 2006.285.08:44:36.86#ibcon#read 6, iclass 36, count 0 2006.285.08:44:36.86#ibcon#end of sib2, iclass 36, count 0 2006.285.08:44:36.86#ibcon#*after write, iclass 36, count 0 2006.285.08:44:36.86#ibcon#*before return 0, iclass 36, count 0 2006.285.08:44:36.86#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:44:36.86#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.08:44:36.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:44:36.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:44:36.86$vck44/vblo=2,634.99 2006.285.08:44:36.86#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.08:44:36.86#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.08:44:36.86#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:36.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:44:36.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:44:36.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:44:36.86#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:44:36.86#ibcon#first serial, iclass 38, count 0 2006.285.08:44:36.86#ibcon#enter sib2, iclass 38, count 0 2006.285.08:44:36.86#ibcon#flushed, iclass 38, count 0 2006.285.08:44:36.86#ibcon#about to write, iclass 38, count 0 2006.285.08:44:36.86#ibcon#wrote, iclass 38, count 0 2006.285.08:44:36.86#ibcon#about to read 3, iclass 38, count 0 2006.285.08:44:36.88#ibcon#read 3, iclass 38, count 0 2006.285.08:44:36.88#ibcon#about to read 4, iclass 38, count 0 2006.285.08:44:36.88#ibcon#read 4, iclass 38, count 0 2006.285.08:44:36.88#ibcon#about to read 5, iclass 38, count 0 2006.285.08:44:36.88#ibcon#read 5, iclass 38, count 0 2006.285.08:44:36.88#ibcon#about to read 6, iclass 38, count 0 2006.285.08:44:36.88#ibcon#read 6, iclass 38, count 0 2006.285.08:44:36.88#ibcon#end of sib2, iclass 38, count 0 2006.285.08:44:36.88#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:44:36.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:44:36.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:44:36.88#ibcon#*before write, iclass 38, count 0 2006.285.08:44:36.88#ibcon#enter sib2, iclass 38, count 0 2006.285.08:44:36.88#ibcon#flushed, iclass 38, count 0 2006.285.08:44:36.88#ibcon#about to write, iclass 38, count 0 2006.285.08:44:36.88#ibcon#wrote, iclass 38, count 0 2006.285.08:44:36.88#ibcon#about to read 3, iclass 38, count 0 2006.285.08:44:36.92#ibcon#read 3, iclass 38, count 0 2006.285.08:44:36.92#ibcon#about to read 4, iclass 38, count 0 2006.285.08:44:36.92#ibcon#read 4, iclass 38, count 0 2006.285.08:44:36.92#ibcon#about to read 5, iclass 38, count 0 2006.285.08:44:36.92#ibcon#read 5, iclass 38, count 0 2006.285.08:44:36.92#ibcon#about to read 6, iclass 38, count 0 2006.285.08:44:36.92#ibcon#read 6, iclass 38, count 0 2006.285.08:44:36.92#ibcon#end of sib2, iclass 38, count 0 2006.285.08:44:36.92#ibcon#*after write, iclass 38, count 0 2006.285.08:44:36.92#ibcon#*before return 0, iclass 38, count 0 2006.285.08:44:36.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:44:36.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.08:44:36.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:44:36.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:44:36.92$vck44/vb=2,5 2006.285.08:44:36.92#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.08:44:36.92#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.08:44:36.92#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:36.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:44:36.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:44:36.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:44:36.98#ibcon#enter wrdev, iclass 40, count 2 2006.285.08:44:36.98#ibcon#first serial, iclass 40, count 2 2006.285.08:44:36.98#ibcon#enter sib2, iclass 40, count 2 2006.285.08:44:36.98#ibcon#flushed, iclass 40, count 2 2006.285.08:44:36.98#ibcon#about to write, iclass 40, count 2 2006.285.08:44:36.98#ibcon#wrote, iclass 40, count 2 2006.285.08:44:36.98#ibcon#about to read 3, iclass 40, count 2 2006.285.08:44:37.00#ibcon#read 3, iclass 40, count 2 2006.285.08:44:37.00#ibcon#about to read 4, iclass 40, count 2 2006.285.08:44:37.00#ibcon#read 4, iclass 40, count 2 2006.285.08:44:37.00#ibcon#about to read 5, iclass 40, count 2 2006.285.08:44:37.00#ibcon#read 5, iclass 40, count 2 2006.285.08:44:37.00#ibcon#about to read 6, iclass 40, count 2 2006.285.08:44:37.00#ibcon#read 6, iclass 40, count 2 2006.285.08:44:37.00#ibcon#end of sib2, iclass 40, count 2 2006.285.08:44:37.00#ibcon#*mode == 0, iclass 40, count 2 2006.285.08:44:37.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.08:44:37.00#ibcon#[27=AT02-05\r\n] 2006.285.08:44:37.00#ibcon#*before write, iclass 40, count 2 2006.285.08:44:37.00#ibcon#enter sib2, iclass 40, count 2 2006.285.08:44:37.00#ibcon#flushed, iclass 40, count 2 2006.285.08:44:37.00#ibcon#about to write, iclass 40, count 2 2006.285.08:44:37.00#ibcon#wrote, iclass 40, count 2 2006.285.08:44:37.00#ibcon#about to read 3, iclass 40, count 2 2006.285.08:44:37.03#ibcon#read 3, iclass 40, count 2 2006.285.08:44:37.03#ibcon#about to read 4, iclass 40, count 2 2006.285.08:44:37.03#ibcon#read 4, iclass 40, count 2 2006.285.08:44:37.03#ibcon#about to read 5, iclass 40, count 2 2006.285.08:44:37.03#ibcon#read 5, iclass 40, count 2 2006.285.08:44:37.03#ibcon#about to read 6, iclass 40, count 2 2006.285.08:44:37.03#ibcon#read 6, iclass 40, count 2 2006.285.08:44:37.03#ibcon#end of sib2, iclass 40, count 2 2006.285.08:44:37.03#ibcon#*after write, iclass 40, count 2 2006.285.08:44:37.03#ibcon#*before return 0, iclass 40, count 2 2006.285.08:44:37.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:44:37.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.08:44:37.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.08:44:37.03#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:37.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:44:37.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:44:37.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:44:37.15#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:44:37.15#ibcon#first serial, iclass 40, count 0 2006.285.08:44:37.15#ibcon#enter sib2, iclass 40, count 0 2006.285.08:44:37.15#ibcon#flushed, iclass 40, count 0 2006.285.08:44:37.15#ibcon#about to write, iclass 40, count 0 2006.285.08:44:37.15#ibcon#wrote, iclass 40, count 0 2006.285.08:44:37.15#ibcon#about to read 3, iclass 40, count 0 2006.285.08:44:37.17#ibcon#read 3, iclass 40, count 0 2006.285.08:44:37.17#ibcon#about to read 4, iclass 40, count 0 2006.285.08:44:37.17#ibcon#read 4, iclass 40, count 0 2006.285.08:44:37.17#ibcon#about to read 5, iclass 40, count 0 2006.285.08:44:37.17#ibcon#read 5, iclass 40, count 0 2006.285.08:44:37.17#ibcon#about to read 6, iclass 40, count 0 2006.285.08:44:37.17#ibcon#read 6, iclass 40, count 0 2006.285.08:44:37.17#ibcon#end of sib2, iclass 40, count 0 2006.285.08:44:37.17#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:44:37.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:44:37.17#ibcon#[27=USB\r\n] 2006.285.08:44:37.17#ibcon#*before write, iclass 40, count 0 2006.285.08:44:37.17#ibcon#enter sib2, iclass 40, count 0 2006.285.08:44:37.17#ibcon#flushed, iclass 40, count 0 2006.285.08:44:37.17#ibcon#about to write, iclass 40, count 0 2006.285.08:44:37.17#ibcon#wrote, iclass 40, count 0 2006.285.08:44:37.17#ibcon#about to read 3, iclass 40, count 0 2006.285.08:44:37.20#ibcon#read 3, iclass 40, count 0 2006.285.08:44:37.20#ibcon#about to read 4, iclass 40, count 0 2006.285.08:44:37.20#ibcon#read 4, iclass 40, count 0 2006.285.08:44:37.20#ibcon#about to read 5, iclass 40, count 0 2006.285.08:44:37.20#ibcon#read 5, iclass 40, count 0 2006.285.08:44:37.20#ibcon#about to read 6, iclass 40, count 0 2006.285.08:44:37.20#ibcon#read 6, iclass 40, count 0 2006.285.08:44:37.20#ibcon#end of sib2, iclass 40, count 0 2006.285.08:44:37.20#ibcon#*after write, iclass 40, count 0 2006.285.08:44:37.20#ibcon#*before return 0, iclass 40, count 0 2006.285.08:44:37.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:44:37.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.08:44:37.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:44:37.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:44:37.20$vck44/vblo=3,649.99 2006.285.08:44:37.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.08:44:37.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.08:44:37.20#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:37.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:44:37.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:44:37.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:44:37.20#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:44:37.20#ibcon#first serial, iclass 4, count 0 2006.285.08:44:37.20#ibcon#enter sib2, iclass 4, count 0 2006.285.08:44:37.20#ibcon#flushed, iclass 4, count 0 2006.285.08:44:37.20#ibcon#about to write, iclass 4, count 0 2006.285.08:44:37.20#ibcon#wrote, iclass 4, count 0 2006.285.08:44:37.20#ibcon#about to read 3, iclass 4, count 0 2006.285.08:44:37.22#ibcon#read 3, iclass 4, count 0 2006.285.08:44:37.22#ibcon#about to read 4, iclass 4, count 0 2006.285.08:44:37.22#ibcon#read 4, iclass 4, count 0 2006.285.08:44:37.22#ibcon#about to read 5, iclass 4, count 0 2006.285.08:44:37.22#ibcon#read 5, iclass 4, count 0 2006.285.08:44:37.22#ibcon#about to read 6, iclass 4, count 0 2006.285.08:44:37.22#ibcon#read 6, iclass 4, count 0 2006.285.08:44:37.22#ibcon#end of sib2, iclass 4, count 0 2006.285.08:44:37.22#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:44:37.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:44:37.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:44:37.22#ibcon#*before write, iclass 4, count 0 2006.285.08:44:37.22#ibcon#enter sib2, iclass 4, count 0 2006.285.08:44:37.22#ibcon#flushed, iclass 4, count 0 2006.285.08:44:37.22#ibcon#about to write, iclass 4, count 0 2006.285.08:44:37.22#ibcon#wrote, iclass 4, count 0 2006.285.08:44:37.22#ibcon#about to read 3, iclass 4, count 0 2006.285.08:44:37.26#ibcon#read 3, iclass 4, count 0 2006.285.08:44:37.26#ibcon#about to read 4, iclass 4, count 0 2006.285.08:44:37.26#ibcon#read 4, iclass 4, count 0 2006.285.08:44:37.26#ibcon#about to read 5, iclass 4, count 0 2006.285.08:44:37.26#ibcon#read 5, iclass 4, count 0 2006.285.08:44:37.26#ibcon#about to read 6, iclass 4, count 0 2006.285.08:44:37.26#ibcon#read 6, iclass 4, count 0 2006.285.08:44:37.26#ibcon#end of sib2, iclass 4, count 0 2006.285.08:44:37.26#ibcon#*after write, iclass 4, count 0 2006.285.08:44:37.26#ibcon#*before return 0, iclass 4, count 0 2006.285.08:44:37.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:44:37.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:44:37.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:44:37.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:44:37.26$vck44/vb=3,4 2006.285.08:44:37.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.08:44:37.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.08:44:37.26#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:37.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:44:37.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:44:37.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:44:37.32#ibcon#enter wrdev, iclass 6, count 2 2006.285.08:44:37.32#ibcon#first serial, iclass 6, count 2 2006.285.08:44:37.32#ibcon#enter sib2, iclass 6, count 2 2006.285.08:44:37.32#ibcon#flushed, iclass 6, count 2 2006.285.08:44:37.32#ibcon#about to write, iclass 6, count 2 2006.285.08:44:37.32#ibcon#wrote, iclass 6, count 2 2006.285.08:44:37.32#ibcon#about to read 3, iclass 6, count 2 2006.285.08:44:37.34#ibcon#read 3, iclass 6, count 2 2006.285.08:44:37.34#ibcon#about to read 4, iclass 6, count 2 2006.285.08:44:37.34#ibcon#read 4, iclass 6, count 2 2006.285.08:44:37.34#ibcon#about to read 5, iclass 6, count 2 2006.285.08:44:37.34#ibcon#read 5, iclass 6, count 2 2006.285.08:44:37.34#ibcon#about to read 6, iclass 6, count 2 2006.285.08:44:37.34#ibcon#read 6, iclass 6, count 2 2006.285.08:44:37.34#ibcon#end of sib2, iclass 6, count 2 2006.285.08:44:37.34#ibcon#*mode == 0, iclass 6, count 2 2006.285.08:44:37.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.08:44:37.34#ibcon#[27=AT03-04\r\n] 2006.285.08:44:37.34#ibcon#*before write, iclass 6, count 2 2006.285.08:44:37.34#ibcon#enter sib2, iclass 6, count 2 2006.285.08:44:37.34#ibcon#flushed, iclass 6, count 2 2006.285.08:44:37.34#ibcon#about to write, iclass 6, count 2 2006.285.08:44:37.34#ibcon#wrote, iclass 6, count 2 2006.285.08:44:37.34#ibcon#about to read 3, iclass 6, count 2 2006.285.08:44:37.37#ibcon#read 3, iclass 6, count 2 2006.285.08:44:37.37#ibcon#about to read 4, iclass 6, count 2 2006.285.08:44:37.37#ibcon#read 4, iclass 6, count 2 2006.285.08:44:37.37#ibcon#about to read 5, iclass 6, count 2 2006.285.08:44:37.37#ibcon#read 5, iclass 6, count 2 2006.285.08:44:37.37#ibcon#about to read 6, iclass 6, count 2 2006.285.08:44:37.37#ibcon#read 6, iclass 6, count 2 2006.285.08:44:37.37#ibcon#end of sib2, iclass 6, count 2 2006.285.08:44:37.37#ibcon#*after write, iclass 6, count 2 2006.285.08:44:37.37#ibcon#*before return 0, iclass 6, count 2 2006.285.08:44:37.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:44:37.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.08:44:37.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.08:44:37.37#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:37.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:44:37.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:44:37.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:44:37.49#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:44:37.49#ibcon#first serial, iclass 6, count 0 2006.285.08:44:37.49#ibcon#enter sib2, iclass 6, count 0 2006.285.08:44:37.49#ibcon#flushed, iclass 6, count 0 2006.285.08:44:37.49#ibcon#about to write, iclass 6, count 0 2006.285.08:44:37.49#ibcon#wrote, iclass 6, count 0 2006.285.08:44:37.49#ibcon#about to read 3, iclass 6, count 0 2006.285.08:44:37.51#ibcon#read 3, iclass 6, count 0 2006.285.08:44:37.51#ibcon#about to read 4, iclass 6, count 0 2006.285.08:44:37.51#ibcon#read 4, iclass 6, count 0 2006.285.08:44:37.51#ibcon#about to read 5, iclass 6, count 0 2006.285.08:44:37.51#ibcon#read 5, iclass 6, count 0 2006.285.08:44:37.51#ibcon#about to read 6, iclass 6, count 0 2006.285.08:44:37.51#ibcon#read 6, iclass 6, count 0 2006.285.08:44:37.51#ibcon#end of sib2, iclass 6, count 0 2006.285.08:44:37.51#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:44:37.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:44:37.51#ibcon#[27=USB\r\n] 2006.285.08:44:37.51#ibcon#*before write, iclass 6, count 0 2006.285.08:44:37.51#ibcon#enter sib2, iclass 6, count 0 2006.285.08:44:37.51#ibcon#flushed, iclass 6, count 0 2006.285.08:44:37.51#ibcon#about to write, iclass 6, count 0 2006.285.08:44:37.51#ibcon#wrote, iclass 6, count 0 2006.285.08:44:37.51#ibcon#about to read 3, iclass 6, count 0 2006.285.08:44:37.54#ibcon#read 3, iclass 6, count 0 2006.285.08:44:37.54#ibcon#about to read 4, iclass 6, count 0 2006.285.08:44:37.54#ibcon#read 4, iclass 6, count 0 2006.285.08:44:37.54#ibcon#about to read 5, iclass 6, count 0 2006.285.08:44:37.54#ibcon#read 5, iclass 6, count 0 2006.285.08:44:37.54#ibcon#about to read 6, iclass 6, count 0 2006.285.08:44:37.54#ibcon#read 6, iclass 6, count 0 2006.285.08:44:37.54#ibcon#end of sib2, iclass 6, count 0 2006.285.08:44:37.54#ibcon#*after write, iclass 6, count 0 2006.285.08:44:37.54#ibcon#*before return 0, iclass 6, count 0 2006.285.08:44:37.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:44:37.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.08:44:37.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:44:37.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:44:37.54$vck44/vblo=4,679.99 2006.285.08:44:37.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.08:44:37.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.08:44:37.54#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:37.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:44:37.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:44:37.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:44:37.54#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:44:37.54#ibcon#first serial, iclass 10, count 0 2006.285.08:44:37.54#ibcon#enter sib2, iclass 10, count 0 2006.285.08:44:37.54#ibcon#flushed, iclass 10, count 0 2006.285.08:44:37.54#ibcon#about to write, iclass 10, count 0 2006.285.08:44:37.54#ibcon#wrote, iclass 10, count 0 2006.285.08:44:37.54#ibcon#about to read 3, iclass 10, count 0 2006.285.08:44:37.56#ibcon#read 3, iclass 10, count 0 2006.285.08:44:37.56#ibcon#about to read 4, iclass 10, count 0 2006.285.08:44:37.56#ibcon#read 4, iclass 10, count 0 2006.285.08:44:37.56#ibcon#about to read 5, iclass 10, count 0 2006.285.08:44:37.56#ibcon#read 5, iclass 10, count 0 2006.285.08:44:37.56#ibcon#about to read 6, iclass 10, count 0 2006.285.08:44:37.56#ibcon#read 6, iclass 10, count 0 2006.285.08:44:37.56#ibcon#end of sib2, iclass 10, count 0 2006.285.08:44:37.56#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:44:37.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:44:37.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:44:37.56#ibcon#*before write, iclass 10, count 0 2006.285.08:44:37.56#ibcon#enter sib2, iclass 10, count 0 2006.285.08:44:37.56#ibcon#flushed, iclass 10, count 0 2006.285.08:44:37.56#ibcon#about to write, iclass 10, count 0 2006.285.08:44:37.56#ibcon#wrote, iclass 10, count 0 2006.285.08:44:37.56#ibcon#about to read 3, iclass 10, count 0 2006.285.08:44:37.60#ibcon#read 3, iclass 10, count 0 2006.285.08:44:37.60#ibcon#about to read 4, iclass 10, count 0 2006.285.08:44:37.60#ibcon#read 4, iclass 10, count 0 2006.285.08:44:37.60#ibcon#about to read 5, iclass 10, count 0 2006.285.08:44:37.60#ibcon#read 5, iclass 10, count 0 2006.285.08:44:37.60#ibcon#about to read 6, iclass 10, count 0 2006.285.08:44:37.60#ibcon#read 6, iclass 10, count 0 2006.285.08:44:37.60#ibcon#end of sib2, iclass 10, count 0 2006.285.08:44:37.60#ibcon#*after write, iclass 10, count 0 2006.285.08:44:37.60#ibcon#*before return 0, iclass 10, count 0 2006.285.08:44:37.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:44:37.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.08:44:37.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:44:37.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:44:37.60$vck44/vb=4,5 2006.285.08:44:37.60#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.08:44:37.60#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.08:44:37.60#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:37.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:44:37.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:44:37.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:44:37.66#ibcon#enter wrdev, iclass 12, count 2 2006.285.08:44:37.66#ibcon#first serial, iclass 12, count 2 2006.285.08:44:37.66#ibcon#enter sib2, iclass 12, count 2 2006.285.08:44:37.66#ibcon#flushed, iclass 12, count 2 2006.285.08:44:37.66#ibcon#about to write, iclass 12, count 2 2006.285.08:44:37.66#ibcon#wrote, iclass 12, count 2 2006.285.08:44:37.66#ibcon#about to read 3, iclass 12, count 2 2006.285.08:44:37.68#ibcon#read 3, iclass 12, count 2 2006.285.08:44:37.68#ibcon#about to read 4, iclass 12, count 2 2006.285.08:44:37.68#ibcon#read 4, iclass 12, count 2 2006.285.08:44:37.68#ibcon#about to read 5, iclass 12, count 2 2006.285.08:44:37.68#ibcon#read 5, iclass 12, count 2 2006.285.08:44:37.68#ibcon#about to read 6, iclass 12, count 2 2006.285.08:44:37.68#ibcon#read 6, iclass 12, count 2 2006.285.08:44:37.68#ibcon#end of sib2, iclass 12, count 2 2006.285.08:44:37.68#ibcon#*mode == 0, iclass 12, count 2 2006.285.08:44:37.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.08:44:37.68#ibcon#[27=AT04-05\r\n] 2006.285.08:44:37.68#ibcon#*before write, iclass 12, count 2 2006.285.08:44:37.68#ibcon#enter sib2, iclass 12, count 2 2006.285.08:44:37.68#ibcon#flushed, iclass 12, count 2 2006.285.08:44:37.68#ibcon#about to write, iclass 12, count 2 2006.285.08:44:37.68#ibcon#wrote, iclass 12, count 2 2006.285.08:44:37.68#ibcon#about to read 3, iclass 12, count 2 2006.285.08:44:37.71#ibcon#read 3, iclass 12, count 2 2006.285.08:44:37.71#ibcon#about to read 4, iclass 12, count 2 2006.285.08:44:37.71#ibcon#read 4, iclass 12, count 2 2006.285.08:44:37.71#ibcon#about to read 5, iclass 12, count 2 2006.285.08:44:37.71#ibcon#read 5, iclass 12, count 2 2006.285.08:44:37.71#ibcon#about to read 6, iclass 12, count 2 2006.285.08:44:37.71#ibcon#read 6, iclass 12, count 2 2006.285.08:44:37.71#ibcon#end of sib2, iclass 12, count 2 2006.285.08:44:37.71#ibcon#*after write, iclass 12, count 2 2006.285.08:44:37.71#ibcon#*before return 0, iclass 12, count 2 2006.285.08:44:37.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:44:37.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.08:44:37.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.08:44:37.71#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:37.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:44:37.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:44:37.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:44:37.83#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:44:37.83#ibcon#first serial, iclass 12, count 0 2006.285.08:44:37.83#ibcon#enter sib2, iclass 12, count 0 2006.285.08:44:37.83#ibcon#flushed, iclass 12, count 0 2006.285.08:44:37.83#ibcon#about to write, iclass 12, count 0 2006.285.08:44:37.83#ibcon#wrote, iclass 12, count 0 2006.285.08:44:37.83#ibcon#about to read 3, iclass 12, count 0 2006.285.08:44:37.85#ibcon#read 3, iclass 12, count 0 2006.285.08:44:37.85#ibcon#about to read 4, iclass 12, count 0 2006.285.08:44:37.85#ibcon#read 4, iclass 12, count 0 2006.285.08:44:37.85#ibcon#about to read 5, iclass 12, count 0 2006.285.08:44:37.85#ibcon#read 5, iclass 12, count 0 2006.285.08:44:37.85#ibcon#about to read 6, iclass 12, count 0 2006.285.08:44:37.85#ibcon#read 6, iclass 12, count 0 2006.285.08:44:37.85#ibcon#end of sib2, iclass 12, count 0 2006.285.08:44:37.85#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:44:37.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:44:37.85#ibcon#[27=USB\r\n] 2006.285.08:44:37.85#ibcon#*before write, iclass 12, count 0 2006.285.08:44:37.85#ibcon#enter sib2, iclass 12, count 0 2006.285.08:44:37.85#ibcon#flushed, iclass 12, count 0 2006.285.08:44:37.85#ibcon#about to write, iclass 12, count 0 2006.285.08:44:37.85#ibcon#wrote, iclass 12, count 0 2006.285.08:44:37.85#ibcon#about to read 3, iclass 12, count 0 2006.285.08:44:37.88#ibcon#read 3, iclass 12, count 0 2006.285.08:44:37.88#ibcon#about to read 4, iclass 12, count 0 2006.285.08:44:37.88#ibcon#read 4, iclass 12, count 0 2006.285.08:44:37.88#ibcon#about to read 5, iclass 12, count 0 2006.285.08:44:37.88#ibcon#read 5, iclass 12, count 0 2006.285.08:44:37.88#ibcon#about to read 6, iclass 12, count 0 2006.285.08:44:37.88#ibcon#read 6, iclass 12, count 0 2006.285.08:44:37.88#ibcon#end of sib2, iclass 12, count 0 2006.285.08:44:37.88#ibcon#*after write, iclass 12, count 0 2006.285.08:44:37.88#ibcon#*before return 0, iclass 12, count 0 2006.285.08:44:37.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:44:37.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.08:44:37.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:44:37.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:44:37.88$vck44/vblo=5,709.99 2006.285.08:44:37.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.08:44:37.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.08:44:37.88#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:37.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:44:37.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:44:37.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:44:37.88#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:44:37.88#ibcon#first serial, iclass 14, count 0 2006.285.08:44:37.88#ibcon#enter sib2, iclass 14, count 0 2006.285.08:44:37.88#ibcon#flushed, iclass 14, count 0 2006.285.08:44:37.88#ibcon#about to write, iclass 14, count 0 2006.285.08:44:37.88#ibcon#wrote, iclass 14, count 0 2006.285.08:44:37.88#ibcon#about to read 3, iclass 14, count 0 2006.285.08:44:37.90#ibcon#read 3, iclass 14, count 0 2006.285.08:44:37.90#ibcon#about to read 4, iclass 14, count 0 2006.285.08:44:37.90#ibcon#read 4, iclass 14, count 0 2006.285.08:44:37.90#ibcon#about to read 5, iclass 14, count 0 2006.285.08:44:37.90#ibcon#read 5, iclass 14, count 0 2006.285.08:44:37.90#ibcon#about to read 6, iclass 14, count 0 2006.285.08:44:37.90#ibcon#read 6, iclass 14, count 0 2006.285.08:44:37.90#ibcon#end of sib2, iclass 14, count 0 2006.285.08:44:37.90#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:44:37.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:44:37.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:44:37.90#ibcon#*before write, iclass 14, count 0 2006.285.08:44:37.90#ibcon#enter sib2, iclass 14, count 0 2006.285.08:44:37.90#ibcon#flushed, iclass 14, count 0 2006.285.08:44:37.90#ibcon#about to write, iclass 14, count 0 2006.285.08:44:37.90#ibcon#wrote, iclass 14, count 0 2006.285.08:44:37.90#ibcon#about to read 3, iclass 14, count 0 2006.285.08:44:37.94#ibcon#read 3, iclass 14, count 0 2006.285.08:44:37.94#ibcon#about to read 4, iclass 14, count 0 2006.285.08:44:37.94#ibcon#read 4, iclass 14, count 0 2006.285.08:44:37.94#ibcon#about to read 5, iclass 14, count 0 2006.285.08:44:37.94#ibcon#read 5, iclass 14, count 0 2006.285.08:44:37.94#ibcon#about to read 6, iclass 14, count 0 2006.285.08:44:37.94#ibcon#read 6, iclass 14, count 0 2006.285.08:44:37.94#ibcon#end of sib2, iclass 14, count 0 2006.285.08:44:37.94#ibcon#*after write, iclass 14, count 0 2006.285.08:44:37.94#ibcon#*before return 0, iclass 14, count 0 2006.285.08:44:37.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:44:37.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.08:44:37.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:44:37.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:44:37.94$vck44/vb=5,4 2006.285.08:44:37.94#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.08:44:37.94#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.08:44:37.94#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:37.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:44:38.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:44:38.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:44:38.00#ibcon#enter wrdev, iclass 16, count 2 2006.285.08:44:38.00#ibcon#first serial, iclass 16, count 2 2006.285.08:44:38.00#ibcon#enter sib2, iclass 16, count 2 2006.285.08:44:38.00#ibcon#flushed, iclass 16, count 2 2006.285.08:44:38.00#ibcon#about to write, iclass 16, count 2 2006.285.08:44:38.00#ibcon#wrote, iclass 16, count 2 2006.285.08:44:38.00#ibcon#about to read 3, iclass 16, count 2 2006.285.08:44:38.02#ibcon#read 3, iclass 16, count 2 2006.285.08:44:38.02#ibcon#about to read 4, iclass 16, count 2 2006.285.08:44:38.02#ibcon#read 4, iclass 16, count 2 2006.285.08:44:38.02#ibcon#about to read 5, iclass 16, count 2 2006.285.08:44:38.02#ibcon#read 5, iclass 16, count 2 2006.285.08:44:38.02#ibcon#about to read 6, iclass 16, count 2 2006.285.08:44:38.02#ibcon#read 6, iclass 16, count 2 2006.285.08:44:38.02#ibcon#end of sib2, iclass 16, count 2 2006.285.08:44:38.02#ibcon#*mode == 0, iclass 16, count 2 2006.285.08:44:38.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.08:44:38.02#ibcon#[27=AT05-04\r\n] 2006.285.08:44:38.02#ibcon#*before write, iclass 16, count 2 2006.285.08:44:38.02#ibcon#enter sib2, iclass 16, count 2 2006.285.08:44:38.02#ibcon#flushed, iclass 16, count 2 2006.285.08:44:38.02#ibcon#about to write, iclass 16, count 2 2006.285.08:44:38.02#ibcon#wrote, iclass 16, count 2 2006.285.08:44:38.02#ibcon#about to read 3, iclass 16, count 2 2006.285.08:44:38.05#ibcon#read 3, iclass 16, count 2 2006.285.08:44:38.05#ibcon#about to read 4, iclass 16, count 2 2006.285.08:44:38.05#ibcon#read 4, iclass 16, count 2 2006.285.08:44:38.05#ibcon#about to read 5, iclass 16, count 2 2006.285.08:44:38.05#ibcon#read 5, iclass 16, count 2 2006.285.08:44:38.05#ibcon#about to read 6, iclass 16, count 2 2006.285.08:44:38.05#ibcon#read 6, iclass 16, count 2 2006.285.08:44:38.05#ibcon#end of sib2, iclass 16, count 2 2006.285.08:44:38.05#ibcon#*after write, iclass 16, count 2 2006.285.08:44:38.05#ibcon#*before return 0, iclass 16, count 2 2006.285.08:44:38.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:44:38.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.08:44:38.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.08:44:38.05#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:38.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:44:38.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:44:38.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:44:38.17#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:44:38.17#ibcon#first serial, iclass 16, count 0 2006.285.08:44:38.17#ibcon#enter sib2, iclass 16, count 0 2006.285.08:44:38.17#ibcon#flushed, iclass 16, count 0 2006.285.08:44:38.17#ibcon#about to write, iclass 16, count 0 2006.285.08:44:38.17#ibcon#wrote, iclass 16, count 0 2006.285.08:44:38.17#ibcon#about to read 3, iclass 16, count 0 2006.285.08:44:38.19#ibcon#read 3, iclass 16, count 0 2006.285.08:44:38.19#ibcon#about to read 4, iclass 16, count 0 2006.285.08:44:38.19#ibcon#read 4, iclass 16, count 0 2006.285.08:44:38.19#ibcon#about to read 5, iclass 16, count 0 2006.285.08:44:38.19#ibcon#read 5, iclass 16, count 0 2006.285.08:44:38.19#ibcon#about to read 6, iclass 16, count 0 2006.285.08:44:38.19#ibcon#read 6, iclass 16, count 0 2006.285.08:44:38.19#ibcon#end of sib2, iclass 16, count 0 2006.285.08:44:38.19#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:44:38.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:44:38.19#ibcon#[27=USB\r\n] 2006.285.08:44:38.19#ibcon#*before write, iclass 16, count 0 2006.285.08:44:38.19#ibcon#enter sib2, iclass 16, count 0 2006.285.08:44:38.19#ibcon#flushed, iclass 16, count 0 2006.285.08:44:38.19#ibcon#about to write, iclass 16, count 0 2006.285.08:44:38.19#ibcon#wrote, iclass 16, count 0 2006.285.08:44:38.19#ibcon#about to read 3, iclass 16, count 0 2006.285.08:44:38.22#ibcon#read 3, iclass 16, count 0 2006.285.08:44:38.22#ibcon#about to read 4, iclass 16, count 0 2006.285.08:44:38.22#ibcon#read 4, iclass 16, count 0 2006.285.08:44:38.22#ibcon#about to read 5, iclass 16, count 0 2006.285.08:44:38.22#ibcon#read 5, iclass 16, count 0 2006.285.08:44:38.22#ibcon#about to read 6, iclass 16, count 0 2006.285.08:44:38.22#ibcon#read 6, iclass 16, count 0 2006.285.08:44:38.22#ibcon#end of sib2, iclass 16, count 0 2006.285.08:44:38.22#ibcon#*after write, iclass 16, count 0 2006.285.08:44:38.22#ibcon#*before return 0, iclass 16, count 0 2006.285.08:44:38.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:44:38.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.08:44:38.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:44:38.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:44:38.22$vck44/vblo=6,719.99 2006.285.08:44:38.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.08:44:38.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.08:44:38.22#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:38.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:44:38.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:44:38.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:44:38.22#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:44:38.22#ibcon#first serial, iclass 18, count 0 2006.285.08:44:38.22#ibcon#enter sib2, iclass 18, count 0 2006.285.08:44:38.22#ibcon#flushed, iclass 18, count 0 2006.285.08:44:38.22#ibcon#about to write, iclass 18, count 0 2006.285.08:44:38.22#ibcon#wrote, iclass 18, count 0 2006.285.08:44:38.22#ibcon#about to read 3, iclass 18, count 0 2006.285.08:44:38.24#ibcon#read 3, iclass 18, count 0 2006.285.08:44:38.24#ibcon#about to read 4, iclass 18, count 0 2006.285.08:44:38.24#ibcon#read 4, iclass 18, count 0 2006.285.08:44:38.24#ibcon#about to read 5, iclass 18, count 0 2006.285.08:44:38.24#ibcon#read 5, iclass 18, count 0 2006.285.08:44:38.24#ibcon#about to read 6, iclass 18, count 0 2006.285.08:44:38.24#ibcon#read 6, iclass 18, count 0 2006.285.08:44:38.24#ibcon#end of sib2, iclass 18, count 0 2006.285.08:44:38.24#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:44:38.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:44:38.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:44:38.24#ibcon#*before write, iclass 18, count 0 2006.285.08:44:38.24#ibcon#enter sib2, iclass 18, count 0 2006.285.08:44:38.24#ibcon#flushed, iclass 18, count 0 2006.285.08:44:38.24#ibcon#about to write, iclass 18, count 0 2006.285.08:44:38.24#ibcon#wrote, iclass 18, count 0 2006.285.08:44:38.24#ibcon#about to read 3, iclass 18, count 0 2006.285.08:44:38.28#ibcon#read 3, iclass 18, count 0 2006.285.08:44:38.28#ibcon#about to read 4, iclass 18, count 0 2006.285.08:44:38.28#ibcon#read 4, iclass 18, count 0 2006.285.08:44:38.28#ibcon#about to read 5, iclass 18, count 0 2006.285.08:44:38.28#ibcon#read 5, iclass 18, count 0 2006.285.08:44:38.28#ibcon#about to read 6, iclass 18, count 0 2006.285.08:44:38.28#ibcon#read 6, iclass 18, count 0 2006.285.08:44:38.28#ibcon#end of sib2, iclass 18, count 0 2006.285.08:44:38.28#ibcon#*after write, iclass 18, count 0 2006.285.08:44:38.28#ibcon#*before return 0, iclass 18, count 0 2006.285.08:44:38.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:44:38.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.08:44:38.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:44:38.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:44:38.28$vck44/vb=6,3 2006.285.08:44:38.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.08:44:38.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.08:44:38.28#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:38.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:44:38.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:44:38.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:44:38.34#ibcon#enter wrdev, iclass 20, count 2 2006.285.08:44:38.34#ibcon#first serial, iclass 20, count 2 2006.285.08:44:38.34#ibcon#enter sib2, iclass 20, count 2 2006.285.08:44:38.34#ibcon#flushed, iclass 20, count 2 2006.285.08:44:38.34#ibcon#about to write, iclass 20, count 2 2006.285.08:44:38.34#ibcon#wrote, iclass 20, count 2 2006.285.08:44:38.34#ibcon#about to read 3, iclass 20, count 2 2006.285.08:44:38.36#ibcon#read 3, iclass 20, count 2 2006.285.08:44:38.36#ibcon#about to read 4, iclass 20, count 2 2006.285.08:44:38.36#ibcon#read 4, iclass 20, count 2 2006.285.08:44:38.36#ibcon#about to read 5, iclass 20, count 2 2006.285.08:44:38.36#ibcon#read 5, iclass 20, count 2 2006.285.08:44:38.36#ibcon#about to read 6, iclass 20, count 2 2006.285.08:44:38.36#ibcon#read 6, iclass 20, count 2 2006.285.08:44:38.36#ibcon#end of sib2, iclass 20, count 2 2006.285.08:44:38.36#ibcon#*mode == 0, iclass 20, count 2 2006.285.08:44:38.36#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.08:44:38.36#ibcon#[27=AT06-03\r\n] 2006.285.08:44:38.36#ibcon#*before write, iclass 20, count 2 2006.285.08:44:38.36#ibcon#enter sib2, iclass 20, count 2 2006.285.08:44:38.36#ibcon#flushed, iclass 20, count 2 2006.285.08:44:38.36#ibcon#about to write, iclass 20, count 2 2006.285.08:44:38.36#ibcon#wrote, iclass 20, count 2 2006.285.08:44:38.36#ibcon#about to read 3, iclass 20, count 2 2006.285.08:44:38.39#ibcon#read 3, iclass 20, count 2 2006.285.08:44:38.39#ibcon#about to read 4, iclass 20, count 2 2006.285.08:44:38.39#ibcon#read 4, iclass 20, count 2 2006.285.08:44:38.39#ibcon#about to read 5, iclass 20, count 2 2006.285.08:44:38.39#ibcon#read 5, iclass 20, count 2 2006.285.08:44:38.39#ibcon#about to read 6, iclass 20, count 2 2006.285.08:44:38.39#ibcon#read 6, iclass 20, count 2 2006.285.08:44:38.39#ibcon#end of sib2, iclass 20, count 2 2006.285.08:44:38.39#ibcon#*after write, iclass 20, count 2 2006.285.08:44:38.39#ibcon#*before return 0, iclass 20, count 2 2006.285.08:44:38.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:44:38.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.08:44:38.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.08:44:38.39#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:38.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:44:38.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:44:38.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:44:38.51#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:44:38.51#ibcon#first serial, iclass 20, count 0 2006.285.08:44:38.51#ibcon#enter sib2, iclass 20, count 0 2006.285.08:44:38.51#ibcon#flushed, iclass 20, count 0 2006.285.08:44:38.51#ibcon#about to write, iclass 20, count 0 2006.285.08:44:38.51#ibcon#wrote, iclass 20, count 0 2006.285.08:44:38.51#ibcon#about to read 3, iclass 20, count 0 2006.285.08:44:38.53#ibcon#read 3, iclass 20, count 0 2006.285.08:44:38.53#ibcon#about to read 4, iclass 20, count 0 2006.285.08:44:38.53#ibcon#read 4, iclass 20, count 0 2006.285.08:44:38.53#ibcon#about to read 5, iclass 20, count 0 2006.285.08:44:38.53#ibcon#read 5, iclass 20, count 0 2006.285.08:44:38.53#ibcon#about to read 6, iclass 20, count 0 2006.285.08:44:38.53#ibcon#read 6, iclass 20, count 0 2006.285.08:44:38.53#ibcon#end of sib2, iclass 20, count 0 2006.285.08:44:38.53#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:44:38.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:44:38.53#ibcon#[27=USB\r\n] 2006.285.08:44:38.53#ibcon#*before write, iclass 20, count 0 2006.285.08:44:38.53#ibcon#enter sib2, iclass 20, count 0 2006.285.08:44:38.53#ibcon#flushed, iclass 20, count 0 2006.285.08:44:38.53#ibcon#about to write, iclass 20, count 0 2006.285.08:44:38.53#ibcon#wrote, iclass 20, count 0 2006.285.08:44:38.53#ibcon#about to read 3, iclass 20, count 0 2006.285.08:44:38.56#ibcon#read 3, iclass 20, count 0 2006.285.08:44:38.56#ibcon#about to read 4, iclass 20, count 0 2006.285.08:44:38.56#ibcon#read 4, iclass 20, count 0 2006.285.08:44:38.56#ibcon#about to read 5, iclass 20, count 0 2006.285.08:44:38.56#ibcon#read 5, iclass 20, count 0 2006.285.08:44:38.56#ibcon#about to read 6, iclass 20, count 0 2006.285.08:44:38.56#ibcon#read 6, iclass 20, count 0 2006.285.08:44:38.56#ibcon#end of sib2, iclass 20, count 0 2006.285.08:44:38.56#ibcon#*after write, iclass 20, count 0 2006.285.08:44:38.56#ibcon#*before return 0, iclass 20, count 0 2006.285.08:44:38.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:44:38.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.08:44:38.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:44:38.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:44:38.56$vck44/vblo=7,734.99 2006.285.08:44:38.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.08:44:38.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.08:44:38.56#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:38.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:44:38.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:44:38.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:44:38.56#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:44:38.56#ibcon#first serial, iclass 22, count 0 2006.285.08:44:38.56#ibcon#enter sib2, iclass 22, count 0 2006.285.08:44:38.56#ibcon#flushed, iclass 22, count 0 2006.285.08:44:38.56#ibcon#about to write, iclass 22, count 0 2006.285.08:44:38.56#ibcon#wrote, iclass 22, count 0 2006.285.08:44:38.56#ibcon#about to read 3, iclass 22, count 0 2006.285.08:44:38.58#ibcon#read 3, iclass 22, count 0 2006.285.08:44:38.58#ibcon#about to read 4, iclass 22, count 0 2006.285.08:44:38.58#ibcon#read 4, iclass 22, count 0 2006.285.08:44:38.58#ibcon#about to read 5, iclass 22, count 0 2006.285.08:44:38.58#ibcon#read 5, iclass 22, count 0 2006.285.08:44:38.58#ibcon#about to read 6, iclass 22, count 0 2006.285.08:44:38.58#ibcon#read 6, iclass 22, count 0 2006.285.08:44:38.58#ibcon#end of sib2, iclass 22, count 0 2006.285.08:44:38.58#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:44:38.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:44:38.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:44:38.58#ibcon#*before write, iclass 22, count 0 2006.285.08:44:38.58#ibcon#enter sib2, iclass 22, count 0 2006.285.08:44:38.58#ibcon#flushed, iclass 22, count 0 2006.285.08:44:38.58#ibcon#about to write, iclass 22, count 0 2006.285.08:44:38.58#ibcon#wrote, iclass 22, count 0 2006.285.08:44:38.58#ibcon#about to read 3, iclass 22, count 0 2006.285.08:44:38.62#ibcon#read 3, iclass 22, count 0 2006.285.08:44:38.62#ibcon#about to read 4, iclass 22, count 0 2006.285.08:44:38.62#ibcon#read 4, iclass 22, count 0 2006.285.08:44:38.62#ibcon#about to read 5, iclass 22, count 0 2006.285.08:44:38.62#ibcon#read 5, iclass 22, count 0 2006.285.08:44:38.62#ibcon#about to read 6, iclass 22, count 0 2006.285.08:44:38.62#ibcon#read 6, iclass 22, count 0 2006.285.08:44:38.62#ibcon#end of sib2, iclass 22, count 0 2006.285.08:44:38.62#ibcon#*after write, iclass 22, count 0 2006.285.08:44:38.62#ibcon#*before return 0, iclass 22, count 0 2006.285.08:44:38.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:44:38.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.08:44:38.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:44:38.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:44:38.62$vck44/vb=7,4 2006.285.08:44:38.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.08:44:38.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.08:44:38.62#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:38.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:44:38.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:44:38.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:44:38.68#ibcon#enter wrdev, iclass 24, count 2 2006.285.08:44:38.68#ibcon#first serial, iclass 24, count 2 2006.285.08:44:38.68#ibcon#enter sib2, iclass 24, count 2 2006.285.08:44:38.68#ibcon#flushed, iclass 24, count 2 2006.285.08:44:38.68#ibcon#about to write, iclass 24, count 2 2006.285.08:44:38.68#ibcon#wrote, iclass 24, count 2 2006.285.08:44:38.68#ibcon#about to read 3, iclass 24, count 2 2006.285.08:44:38.70#ibcon#read 3, iclass 24, count 2 2006.285.08:44:38.70#ibcon#about to read 4, iclass 24, count 2 2006.285.08:44:38.70#ibcon#read 4, iclass 24, count 2 2006.285.08:44:38.70#ibcon#about to read 5, iclass 24, count 2 2006.285.08:44:38.70#ibcon#read 5, iclass 24, count 2 2006.285.08:44:38.70#ibcon#about to read 6, iclass 24, count 2 2006.285.08:44:38.70#ibcon#read 6, iclass 24, count 2 2006.285.08:44:38.70#ibcon#end of sib2, iclass 24, count 2 2006.285.08:44:38.70#ibcon#*mode == 0, iclass 24, count 2 2006.285.08:44:38.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.08:44:38.70#ibcon#[27=AT07-04\r\n] 2006.285.08:44:38.70#ibcon#*before write, iclass 24, count 2 2006.285.08:44:38.70#ibcon#enter sib2, iclass 24, count 2 2006.285.08:44:38.70#ibcon#flushed, iclass 24, count 2 2006.285.08:44:38.70#ibcon#about to write, iclass 24, count 2 2006.285.08:44:38.70#ibcon#wrote, iclass 24, count 2 2006.285.08:44:38.70#ibcon#about to read 3, iclass 24, count 2 2006.285.08:44:38.73#ibcon#read 3, iclass 24, count 2 2006.285.08:44:38.73#ibcon#about to read 4, iclass 24, count 2 2006.285.08:44:38.73#ibcon#read 4, iclass 24, count 2 2006.285.08:44:38.73#ibcon#about to read 5, iclass 24, count 2 2006.285.08:44:38.73#ibcon#read 5, iclass 24, count 2 2006.285.08:44:38.73#ibcon#about to read 6, iclass 24, count 2 2006.285.08:44:38.73#ibcon#read 6, iclass 24, count 2 2006.285.08:44:38.73#ibcon#end of sib2, iclass 24, count 2 2006.285.08:44:38.73#ibcon#*after write, iclass 24, count 2 2006.285.08:44:38.73#ibcon#*before return 0, iclass 24, count 2 2006.285.08:44:38.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:44:38.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.08:44:38.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.08:44:38.73#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:38.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:44:38.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:44:38.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:44:38.85#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:44:38.85#ibcon#first serial, iclass 24, count 0 2006.285.08:44:38.85#ibcon#enter sib2, iclass 24, count 0 2006.285.08:44:38.85#ibcon#flushed, iclass 24, count 0 2006.285.08:44:38.85#ibcon#about to write, iclass 24, count 0 2006.285.08:44:38.85#ibcon#wrote, iclass 24, count 0 2006.285.08:44:38.85#ibcon#about to read 3, iclass 24, count 0 2006.285.08:44:38.87#ibcon#read 3, iclass 24, count 0 2006.285.08:44:38.87#ibcon#about to read 4, iclass 24, count 0 2006.285.08:44:38.87#ibcon#read 4, iclass 24, count 0 2006.285.08:44:38.87#ibcon#about to read 5, iclass 24, count 0 2006.285.08:44:38.87#ibcon#read 5, iclass 24, count 0 2006.285.08:44:38.87#ibcon#about to read 6, iclass 24, count 0 2006.285.08:44:38.87#ibcon#read 6, iclass 24, count 0 2006.285.08:44:38.87#ibcon#end of sib2, iclass 24, count 0 2006.285.08:44:38.87#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:44:38.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:44:38.87#ibcon#[27=USB\r\n] 2006.285.08:44:38.87#ibcon#*before write, iclass 24, count 0 2006.285.08:44:38.87#ibcon#enter sib2, iclass 24, count 0 2006.285.08:44:38.87#ibcon#flushed, iclass 24, count 0 2006.285.08:44:38.87#ibcon#about to write, iclass 24, count 0 2006.285.08:44:38.87#ibcon#wrote, iclass 24, count 0 2006.285.08:44:38.87#ibcon#about to read 3, iclass 24, count 0 2006.285.08:44:38.90#ibcon#read 3, iclass 24, count 0 2006.285.08:44:38.90#ibcon#about to read 4, iclass 24, count 0 2006.285.08:44:38.90#ibcon#read 4, iclass 24, count 0 2006.285.08:44:38.90#ibcon#about to read 5, iclass 24, count 0 2006.285.08:44:38.90#ibcon#read 5, iclass 24, count 0 2006.285.08:44:38.90#ibcon#about to read 6, iclass 24, count 0 2006.285.08:44:38.90#ibcon#read 6, iclass 24, count 0 2006.285.08:44:38.90#ibcon#end of sib2, iclass 24, count 0 2006.285.08:44:38.90#ibcon#*after write, iclass 24, count 0 2006.285.08:44:38.90#ibcon#*before return 0, iclass 24, count 0 2006.285.08:44:38.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:44:38.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.08:44:38.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:44:38.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:44:38.90$vck44/vblo=8,744.99 2006.285.08:44:38.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.08:44:38.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.08:44:38.90#ibcon#ireg 17 cls_cnt 0 2006.285.08:44:38.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:44:38.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:44:38.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:44:38.90#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:44:38.90#ibcon#first serial, iclass 26, count 0 2006.285.08:44:38.90#ibcon#enter sib2, iclass 26, count 0 2006.285.08:44:38.90#ibcon#flushed, iclass 26, count 0 2006.285.08:44:38.90#ibcon#about to write, iclass 26, count 0 2006.285.08:44:38.90#ibcon#wrote, iclass 26, count 0 2006.285.08:44:38.90#ibcon#about to read 3, iclass 26, count 0 2006.285.08:44:38.92#ibcon#read 3, iclass 26, count 0 2006.285.08:44:38.92#ibcon#about to read 4, iclass 26, count 0 2006.285.08:44:38.92#ibcon#read 4, iclass 26, count 0 2006.285.08:44:38.92#ibcon#about to read 5, iclass 26, count 0 2006.285.08:44:38.92#ibcon#read 5, iclass 26, count 0 2006.285.08:44:38.92#ibcon#about to read 6, iclass 26, count 0 2006.285.08:44:38.92#ibcon#read 6, iclass 26, count 0 2006.285.08:44:38.92#ibcon#end of sib2, iclass 26, count 0 2006.285.08:44:38.92#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:44:38.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:44:38.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:44:38.92#ibcon#*before write, iclass 26, count 0 2006.285.08:44:38.92#ibcon#enter sib2, iclass 26, count 0 2006.285.08:44:38.92#ibcon#flushed, iclass 26, count 0 2006.285.08:44:38.92#ibcon#about to write, iclass 26, count 0 2006.285.08:44:38.92#ibcon#wrote, iclass 26, count 0 2006.285.08:44:38.92#ibcon#about to read 3, iclass 26, count 0 2006.285.08:44:38.96#ibcon#read 3, iclass 26, count 0 2006.285.08:44:38.96#ibcon#about to read 4, iclass 26, count 0 2006.285.08:44:38.96#ibcon#read 4, iclass 26, count 0 2006.285.08:44:38.96#ibcon#about to read 5, iclass 26, count 0 2006.285.08:44:38.96#ibcon#read 5, iclass 26, count 0 2006.285.08:44:38.96#ibcon#about to read 6, iclass 26, count 0 2006.285.08:44:38.96#ibcon#read 6, iclass 26, count 0 2006.285.08:44:38.96#ibcon#end of sib2, iclass 26, count 0 2006.285.08:44:38.96#ibcon#*after write, iclass 26, count 0 2006.285.08:44:38.96#ibcon#*before return 0, iclass 26, count 0 2006.285.08:44:38.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:44:38.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.08:44:38.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:44:38.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:44:38.96$vck44/vb=8,4 2006.285.08:44:38.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.08:44:38.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.08:44:38.96#ibcon#ireg 11 cls_cnt 2 2006.285.08:44:38.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:44:39.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:44:39.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:44:39.02#ibcon#enter wrdev, iclass 28, count 2 2006.285.08:44:39.02#ibcon#first serial, iclass 28, count 2 2006.285.08:44:39.02#ibcon#enter sib2, iclass 28, count 2 2006.285.08:44:39.02#ibcon#flushed, iclass 28, count 2 2006.285.08:44:39.02#ibcon#about to write, iclass 28, count 2 2006.285.08:44:39.02#ibcon#wrote, iclass 28, count 2 2006.285.08:44:39.02#ibcon#about to read 3, iclass 28, count 2 2006.285.08:44:39.04#ibcon#read 3, iclass 28, count 2 2006.285.08:44:39.04#ibcon#about to read 4, iclass 28, count 2 2006.285.08:44:39.04#ibcon#read 4, iclass 28, count 2 2006.285.08:44:39.04#ibcon#about to read 5, iclass 28, count 2 2006.285.08:44:39.04#ibcon#read 5, iclass 28, count 2 2006.285.08:44:39.04#ibcon#about to read 6, iclass 28, count 2 2006.285.08:44:39.04#ibcon#read 6, iclass 28, count 2 2006.285.08:44:39.04#ibcon#end of sib2, iclass 28, count 2 2006.285.08:44:39.04#ibcon#*mode == 0, iclass 28, count 2 2006.285.08:44:39.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.08:44:39.04#ibcon#[27=AT08-04\r\n] 2006.285.08:44:39.04#ibcon#*before write, iclass 28, count 2 2006.285.08:44:39.04#ibcon#enter sib2, iclass 28, count 2 2006.285.08:44:39.04#ibcon#flushed, iclass 28, count 2 2006.285.08:44:39.04#ibcon#about to write, iclass 28, count 2 2006.285.08:44:39.04#ibcon#wrote, iclass 28, count 2 2006.285.08:44:39.04#ibcon#about to read 3, iclass 28, count 2 2006.285.08:44:39.07#ibcon#read 3, iclass 28, count 2 2006.285.08:44:39.07#ibcon#about to read 4, iclass 28, count 2 2006.285.08:44:39.07#ibcon#read 4, iclass 28, count 2 2006.285.08:44:39.07#ibcon#about to read 5, iclass 28, count 2 2006.285.08:44:39.07#ibcon#read 5, iclass 28, count 2 2006.285.08:44:39.07#ibcon#about to read 6, iclass 28, count 2 2006.285.08:44:39.07#ibcon#read 6, iclass 28, count 2 2006.285.08:44:39.07#ibcon#end of sib2, iclass 28, count 2 2006.285.08:44:39.07#ibcon#*after write, iclass 28, count 2 2006.285.08:44:39.07#ibcon#*before return 0, iclass 28, count 2 2006.285.08:44:39.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:44:39.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.08:44:39.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.08:44:39.07#ibcon#ireg 7 cls_cnt 0 2006.285.08:44:39.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:44:39.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:44:39.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:44:39.19#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:44:39.19#ibcon#first serial, iclass 28, count 0 2006.285.08:44:39.19#ibcon#enter sib2, iclass 28, count 0 2006.285.08:44:39.19#ibcon#flushed, iclass 28, count 0 2006.285.08:44:39.19#ibcon#about to write, iclass 28, count 0 2006.285.08:44:39.19#ibcon#wrote, iclass 28, count 0 2006.285.08:44:39.19#ibcon#about to read 3, iclass 28, count 0 2006.285.08:44:39.21#ibcon#read 3, iclass 28, count 0 2006.285.08:44:39.21#ibcon#about to read 4, iclass 28, count 0 2006.285.08:44:39.21#ibcon#read 4, iclass 28, count 0 2006.285.08:44:39.21#ibcon#about to read 5, iclass 28, count 0 2006.285.08:44:39.21#ibcon#read 5, iclass 28, count 0 2006.285.08:44:39.21#ibcon#about to read 6, iclass 28, count 0 2006.285.08:44:39.21#ibcon#read 6, iclass 28, count 0 2006.285.08:44:39.21#ibcon#end of sib2, iclass 28, count 0 2006.285.08:44:39.21#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:44:39.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:44:39.21#ibcon#[27=USB\r\n] 2006.285.08:44:39.21#ibcon#*before write, iclass 28, count 0 2006.285.08:44:39.21#ibcon#enter sib2, iclass 28, count 0 2006.285.08:44:39.21#ibcon#flushed, iclass 28, count 0 2006.285.08:44:39.21#ibcon#about to write, iclass 28, count 0 2006.285.08:44:39.21#ibcon#wrote, iclass 28, count 0 2006.285.08:44:39.21#ibcon#about to read 3, iclass 28, count 0 2006.285.08:44:39.24#ibcon#read 3, iclass 28, count 0 2006.285.08:44:39.24#ibcon#about to read 4, iclass 28, count 0 2006.285.08:44:39.24#ibcon#read 4, iclass 28, count 0 2006.285.08:44:39.24#ibcon#about to read 5, iclass 28, count 0 2006.285.08:44:39.24#ibcon#read 5, iclass 28, count 0 2006.285.08:44:39.24#ibcon#about to read 6, iclass 28, count 0 2006.285.08:44:39.24#ibcon#read 6, iclass 28, count 0 2006.285.08:44:39.24#ibcon#end of sib2, iclass 28, count 0 2006.285.08:44:39.24#ibcon#*after write, iclass 28, count 0 2006.285.08:44:39.24#ibcon#*before return 0, iclass 28, count 0 2006.285.08:44:39.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:44:39.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.08:44:39.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:44:39.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:44:39.24$vck44/vabw=wide 2006.285.08:44:39.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.08:44:39.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.08:44:39.24#ibcon#ireg 8 cls_cnt 0 2006.285.08:44:39.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:44:39.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:44:39.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:44:39.24#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:44:39.24#ibcon#first serial, iclass 30, count 0 2006.285.08:44:39.24#ibcon#enter sib2, iclass 30, count 0 2006.285.08:44:39.24#ibcon#flushed, iclass 30, count 0 2006.285.08:44:39.24#ibcon#about to write, iclass 30, count 0 2006.285.08:44:39.24#ibcon#wrote, iclass 30, count 0 2006.285.08:44:39.24#ibcon#about to read 3, iclass 30, count 0 2006.285.08:44:39.26#ibcon#read 3, iclass 30, count 0 2006.285.08:44:39.26#ibcon#about to read 4, iclass 30, count 0 2006.285.08:44:39.26#ibcon#read 4, iclass 30, count 0 2006.285.08:44:39.26#ibcon#about to read 5, iclass 30, count 0 2006.285.08:44:39.26#ibcon#read 5, iclass 30, count 0 2006.285.08:44:39.26#ibcon#about to read 6, iclass 30, count 0 2006.285.08:44:39.26#ibcon#read 6, iclass 30, count 0 2006.285.08:44:39.26#ibcon#end of sib2, iclass 30, count 0 2006.285.08:44:39.26#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:44:39.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:44:39.26#ibcon#[25=BW32\r\n] 2006.285.08:44:39.26#ibcon#*before write, iclass 30, count 0 2006.285.08:44:39.26#ibcon#enter sib2, iclass 30, count 0 2006.285.08:44:39.26#ibcon#flushed, iclass 30, count 0 2006.285.08:44:39.26#ibcon#about to write, iclass 30, count 0 2006.285.08:44:39.26#ibcon#wrote, iclass 30, count 0 2006.285.08:44:39.26#ibcon#about to read 3, iclass 30, count 0 2006.285.08:44:39.29#ibcon#read 3, iclass 30, count 0 2006.285.08:44:39.29#ibcon#about to read 4, iclass 30, count 0 2006.285.08:44:39.29#ibcon#read 4, iclass 30, count 0 2006.285.08:44:39.29#ibcon#about to read 5, iclass 30, count 0 2006.285.08:44:39.29#ibcon#read 5, iclass 30, count 0 2006.285.08:44:39.29#ibcon#about to read 6, iclass 30, count 0 2006.285.08:44:39.29#ibcon#read 6, iclass 30, count 0 2006.285.08:44:39.29#ibcon#end of sib2, iclass 30, count 0 2006.285.08:44:39.29#ibcon#*after write, iclass 30, count 0 2006.285.08:44:39.29#ibcon#*before return 0, iclass 30, count 0 2006.285.08:44:39.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:44:39.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.08:44:39.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:44:39.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:44:39.29$vck44/vbbw=wide 2006.285.08:44:39.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.08:44:39.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.08:44:39.29#ibcon#ireg 8 cls_cnt 0 2006.285.08:44:39.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:44:39.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:44:39.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:44:39.36#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:44:39.36#ibcon#first serial, iclass 32, count 0 2006.285.08:44:39.36#ibcon#enter sib2, iclass 32, count 0 2006.285.08:44:39.36#ibcon#flushed, iclass 32, count 0 2006.285.08:44:39.36#ibcon#about to write, iclass 32, count 0 2006.285.08:44:39.36#ibcon#wrote, iclass 32, count 0 2006.285.08:44:39.36#ibcon#about to read 3, iclass 32, count 0 2006.285.08:44:39.38#ibcon#read 3, iclass 32, count 0 2006.285.08:44:39.38#ibcon#about to read 4, iclass 32, count 0 2006.285.08:44:39.38#ibcon#read 4, iclass 32, count 0 2006.285.08:44:39.38#ibcon#about to read 5, iclass 32, count 0 2006.285.08:44:39.38#ibcon#read 5, iclass 32, count 0 2006.285.08:44:39.38#ibcon#about to read 6, iclass 32, count 0 2006.285.08:44:39.38#ibcon#read 6, iclass 32, count 0 2006.285.08:44:39.38#ibcon#end of sib2, iclass 32, count 0 2006.285.08:44:39.38#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:44:39.38#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:44:39.38#ibcon#[27=BW32\r\n] 2006.285.08:44:39.38#ibcon#*before write, iclass 32, count 0 2006.285.08:44:39.38#ibcon#enter sib2, iclass 32, count 0 2006.285.08:44:39.38#ibcon#flushed, iclass 32, count 0 2006.285.08:44:39.38#ibcon#about to write, iclass 32, count 0 2006.285.08:44:39.38#ibcon#wrote, iclass 32, count 0 2006.285.08:44:39.38#ibcon#about to read 3, iclass 32, count 0 2006.285.08:44:39.41#ibcon#read 3, iclass 32, count 0 2006.285.08:44:39.41#ibcon#about to read 4, iclass 32, count 0 2006.285.08:44:39.41#ibcon#read 4, iclass 32, count 0 2006.285.08:44:39.41#ibcon#about to read 5, iclass 32, count 0 2006.285.08:44:39.41#ibcon#read 5, iclass 32, count 0 2006.285.08:44:39.41#ibcon#about to read 6, iclass 32, count 0 2006.285.08:44:39.41#ibcon#read 6, iclass 32, count 0 2006.285.08:44:39.41#ibcon#end of sib2, iclass 32, count 0 2006.285.08:44:39.41#ibcon#*after write, iclass 32, count 0 2006.285.08:44:39.41#ibcon#*before return 0, iclass 32, count 0 2006.285.08:44:39.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:44:39.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:44:39.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:44:39.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:44:39.41$setupk4/ifdk4 2006.285.08:44:39.41$ifdk4/lo= 2006.285.08:44:39.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:44:39.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:44:39.41$ifdk4/patch= 2006.285.08:44:39.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:44:39.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:44:39.41$setupk4/!*+20s 2006.285.08:44:39.68#abcon#<5=/04 1.0 1.9 21.88 821014.9\r\n> 2006.285.08:44:39.70#abcon#{5=INTERFACE CLEAR} 2006.285.08:44:39.76#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:44:49.85#abcon#<5=/04 1.0 2.0 21.88 821014.8\r\n> 2006.285.08:44:49.87#abcon#{5=INTERFACE CLEAR} 2006.285.08:44:49.93#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:44:53.92$setupk4/"tpicd 2006.285.08:44:53.92$setupk4/echo=off 2006.285.08:44:53.92$setupk4/xlog=off 2006.285.08:44:53.92:!2006.285.08:45:45 2006.285.08:44:54.14#trakl#Source acquired 2006.285.08:44:54.14#flagr#flagr/antenna,acquired 2006.285.08:45:45.00:preob 2006.285.08:45:46.14/onsource/TRACKING 2006.285.08:45:46.14:!2006.285.08:45:55 2006.285.08:45:55.00:"tape 2006.285.08:45:55.00:"st=record 2006.285.08:45:55.00:data_valid=on 2006.285.08:45:55.00:midob 2006.285.08:45:55.14/onsource/TRACKING 2006.285.08:45:55.14/wx/21.86,1014.8,82 2006.285.08:45:55.28/cable/+6.4764E-03 2006.285.08:45:56.37/va/01,07,usb,yes,31,34 2006.285.08:45:56.37/va/02,06,usb,yes,31,32 2006.285.08:45:56.37/va/03,07,usb,yes,31,33 2006.285.08:45:56.37/va/04,06,usb,yes,32,34 2006.285.08:45:56.37/va/05,03,usb,yes,32,32 2006.285.08:45:56.37/va/06,04,usb,yes,29,28 2006.285.08:45:56.37/va/07,04,usb,yes,29,30 2006.285.08:45:56.37/va/08,03,usb,yes,30,37 2006.285.08:45:56.60/valo/01,524.99,yes,locked 2006.285.08:45:56.60/valo/02,534.99,yes,locked 2006.285.08:45:56.60/valo/03,564.99,yes,locked 2006.285.08:45:56.60/valo/04,624.99,yes,locked 2006.285.08:45:56.60/valo/05,734.99,yes,locked 2006.285.08:45:56.60/valo/06,814.99,yes,locked 2006.285.08:45:56.60/valo/07,864.99,yes,locked 2006.285.08:45:56.60/valo/08,884.99,yes,locked 2006.285.08:45:57.69/vb/01,04,usb,yes,30,28 2006.285.08:45:57.69/vb/02,05,usb,yes,28,28 2006.285.08:45:57.69/vb/03,04,usb,yes,29,32 2006.285.08:45:57.69/vb/04,05,usb,yes,29,28 2006.285.08:45:57.69/vb/05,04,usb,yes,26,28 2006.285.08:45:57.69/vb/06,03,usb,yes,37,33 2006.285.08:45:57.69/vb/07,04,usb,yes,30,30 2006.285.08:45:57.69/vb/08,04,usb,yes,27,31 2006.285.08:45:57.92/vblo/01,629.99,yes,locked 2006.285.08:45:57.92/vblo/02,634.99,yes,locked 2006.285.08:45:57.92/vblo/03,649.99,yes,locked 2006.285.08:45:57.92/vblo/04,679.99,yes,locked 2006.285.08:45:57.92/vblo/05,709.99,yes,locked 2006.285.08:45:57.92/vblo/06,719.99,yes,locked 2006.285.08:45:57.92/vblo/07,734.99,yes,locked 2006.285.08:45:57.92/vblo/08,744.99,yes,locked 2006.285.08:45:58.07/vabw/8 2006.285.08:45:58.22/vbbw/8 2006.285.08:45:58.31/xfe/off,on,12.2 2006.285.08:45:58.68/ifatt/23,28,28,28 2006.285.08:45:59.08/fmout-gps/S +2.72E-07 2006.285.08:45:59.10:!2006.285.08:48:35 2006.285.08:48:35.00:data_valid=off 2006.285.08:48:35.00:"et 2006.285.08:48:35.00:!+3s 2006.285.08:48:38.01:"tape 2006.285.08:48:38.01:postob 2006.285.08:48:38.15/cable/+6.4774E-03 2006.285.08:48:38.15/wx/21.80,1014.9,82 2006.285.08:48:39.08/fmout-gps/S +2.70E-07 2006.285.08:48:39.08:scan_name=285-0854,jd0610,40 2006.285.08:48:39.08:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.285.08:48:40.13#flagr#flagr/antenna,new-source 2006.285.08:48:40.13:checkk5 2006.285.08:48:40.51/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:48:40.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:48:41.29/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:48:41.89/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:48:42.30/chk_obsdata//k5ts1/T2850845??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.08:48:42.67/chk_obsdata//k5ts2/T2850845??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.08:48:43.06/chk_obsdata//k5ts3/T2850845??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.08:48:43.44/chk_obsdata//k5ts4/T2850845??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.08:48:44.14/k5log//k5ts1_log_newline 2006.285.08:48:45.11/k5log//k5ts2_log_newline 2006.285.08:48:46.16/k5log//k5ts3_log_newline 2006.285.08:48:46.88/k5log//k5ts4_log_newline 2006.285.08:48:46.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:48:46.90:setupk4=1 2006.285.08:48:46.90$setupk4/echo=on 2006.285.08:48:46.90$setupk4/pcalon 2006.285.08:48:46.90$pcalon/"no phase cal control is implemented here 2006.285.08:48:46.90$setupk4/"tpicd=stop 2006.285.08:48:46.90$setupk4/"rec=synch_on 2006.285.08:48:46.90$setupk4/"rec_mode=128 2006.285.08:48:46.90$setupk4/!* 2006.285.08:48:46.90$setupk4/recpk4 2006.285.08:48:46.90$recpk4/recpatch= 2006.285.08:48:46.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:48:46.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:48:46.90$setupk4/vck44 2006.285.08:48:46.90$vck44/valo=1,524.99 2006.285.08:48:46.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.08:48:46.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.08:48:46.91#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:46.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:48:46.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:48:46.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:48:46.91#ibcon#enter wrdev, iclass 29, count 0 2006.285.08:48:46.91#ibcon#first serial, iclass 29, count 0 2006.285.08:48:46.91#ibcon#enter sib2, iclass 29, count 0 2006.285.08:48:46.91#ibcon#flushed, iclass 29, count 0 2006.285.08:48:46.91#ibcon#about to write, iclass 29, count 0 2006.285.08:48:46.91#ibcon#wrote, iclass 29, count 0 2006.285.08:48:46.91#ibcon#about to read 3, iclass 29, count 0 2006.285.08:48:46.93#ibcon#read 3, iclass 29, count 0 2006.285.08:48:46.93#ibcon#about to read 4, iclass 29, count 0 2006.285.08:48:46.93#ibcon#read 4, iclass 29, count 0 2006.285.08:48:46.93#ibcon#about to read 5, iclass 29, count 0 2006.285.08:48:46.93#ibcon#read 5, iclass 29, count 0 2006.285.08:48:46.93#ibcon#about to read 6, iclass 29, count 0 2006.285.08:48:46.93#ibcon#read 6, iclass 29, count 0 2006.285.08:48:46.93#ibcon#end of sib2, iclass 29, count 0 2006.285.08:48:46.93#ibcon#*mode == 0, iclass 29, count 0 2006.285.08:48:46.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.08:48:46.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:48:46.93#ibcon#*before write, iclass 29, count 0 2006.285.08:48:46.93#ibcon#enter sib2, iclass 29, count 0 2006.285.08:48:46.93#ibcon#flushed, iclass 29, count 0 2006.285.08:48:46.93#ibcon#about to write, iclass 29, count 0 2006.285.08:48:46.93#ibcon#wrote, iclass 29, count 0 2006.285.08:48:46.93#ibcon#about to read 3, iclass 29, count 0 2006.285.08:48:46.97#ibcon#read 3, iclass 29, count 0 2006.285.08:48:46.97#ibcon#about to read 4, iclass 29, count 0 2006.285.08:48:46.97#ibcon#read 4, iclass 29, count 0 2006.285.08:48:46.98#ibcon#about to read 5, iclass 29, count 0 2006.285.08:48:46.98#ibcon#read 5, iclass 29, count 0 2006.285.08:48:46.98#ibcon#about to read 6, iclass 29, count 0 2006.285.08:48:46.98#ibcon#read 6, iclass 29, count 0 2006.285.08:48:46.98#ibcon#end of sib2, iclass 29, count 0 2006.285.08:48:46.98#ibcon#*after write, iclass 29, count 0 2006.285.08:48:46.98#ibcon#*before return 0, iclass 29, count 0 2006.285.08:48:46.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:48:46.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:48:46.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.08:48:46.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.08:48:46.98$vck44/va=1,7 2006.285.08:48:46.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.08:48:46.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.08:48:46.98#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:46.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:48:46.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:48:46.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:48:46.98#ibcon#enter wrdev, iclass 31, count 2 2006.285.08:48:46.98#ibcon#first serial, iclass 31, count 2 2006.285.08:48:46.98#ibcon#enter sib2, iclass 31, count 2 2006.285.08:48:46.98#ibcon#flushed, iclass 31, count 2 2006.285.08:48:46.98#ibcon#about to write, iclass 31, count 2 2006.285.08:48:46.98#ibcon#wrote, iclass 31, count 2 2006.285.08:48:46.98#ibcon#about to read 3, iclass 31, count 2 2006.285.08:48:46.99#ibcon#read 3, iclass 31, count 2 2006.285.08:48:46.99#ibcon#about to read 4, iclass 31, count 2 2006.285.08:48:46.99#ibcon#read 4, iclass 31, count 2 2006.285.08:48:47.00#ibcon#about to read 5, iclass 31, count 2 2006.285.08:48:47.00#ibcon#read 5, iclass 31, count 2 2006.285.08:48:47.00#ibcon#about to read 6, iclass 31, count 2 2006.285.08:48:47.00#ibcon#read 6, iclass 31, count 2 2006.285.08:48:47.00#ibcon#end of sib2, iclass 31, count 2 2006.285.08:48:47.00#ibcon#*mode == 0, iclass 31, count 2 2006.285.08:48:47.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.08:48:47.00#ibcon#[25=AT01-07\r\n] 2006.285.08:48:47.00#ibcon#*before write, iclass 31, count 2 2006.285.08:48:47.00#ibcon#enter sib2, iclass 31, count 2 2006.285.08:48:47.00#ibcon#flushed, iclass 31, count 2 2006.285.08:48:47.00#ibcon#about to write, iclass 31, count 2 2006.285.08:48:47.00#ibcon#wrote, iclass 31, count 2 2006.285.08:48:47.00#ibcon#about to read 3, iclass 31, count 2 2006.285.08:48:47.02#ibcon#read 3, iclass 31, count 2 2006.285.08:48:47.02#ibcon#about to read 4, iclass 31, count 2 2006.285.08:48:47.02#ibcon#read 4, iclass 31, count 2 2006.285.08:48:47.03#ibcon#about to read 5, iclass 31, count 2 2006.285.08:48:47.03#ibcon#read 5, iclass 31, count 2 2006.285.08:48:47.03#ibcon#about to read 6, iclass 31, count 2 2006.285.08:48:47.03#ibcon#read 6, iclass 31, count 2 2006.285.08:48:47.03#ibcon#end of sib2, iclass 31, count 2 2006.285.08:48:47.03#ibcon#*after write, iclass 31, count 2 2006.285.08:48:47.03#ibcon#*before return 0, iclass 31, count 2 2006.285.08:48:47.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:48:47.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:48:47.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.08:48:47.03#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:47.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:48:47.14#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:48:47.14#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:48:47.14#ibcon#enter wrdev, iclass 31, count 0 2006.285.08:48:47.15#ibcon#first serial, iclass 31, count 0 2006.285.08:48:47.15#ibcon#enter sib2, iclass 31, count 0 2006.285.08:48:47.15#ibcon#flushed, iclass 31, count 0 2006.285.08:48:47.15#ibcon#about to write, iclass 31, count 0 2006.285.08:48:47.15#ibcon#wrote, iclass 31, count 0 2006.285.08:48:47.15#ibcon#about to read 3, iclass 31, count 0 2006.285.08:48:47.16#ibcon#read 3, iclass 31, count 0 2006.285.08:48:47.16#ibcon#about to read 4, iclass 31, count 0 2006.285.08:48:47.16#ibcon#read 4, iclass 31, count 0 2006.285.08:48:47.16#ibcon#about to read 5, iclass 31, count 0 2006.285.08:48:47.17#ibcon#read 5, iclass 31, count 0 2006.285.08:48:47.17#ibcon#about to read 6, iclass 31, count 0 2006.285.08:48:47.17#ibcon#read 6, iclass 31, count 0 2006.285.08:48:47.17#ibcon#end of sib2, iclass 31, count 0 2006.285.08:48:47.17#ibcon#*mode == 0, iclass 31, count 0 2006.285.08:48:47.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.08:48:47.17#ibcon#[25=USB\r\n] 2006.285.08:48:47.17#ibcon#*before write, iclass 31, count 0 2006.285.08:48:47.17#ibcon#enter sib2, iclass 31, count 0 2006.285.08:48:47.17#ibcon#flushed, iclass 31, count 0 2006.285.08:48:47.17#ibcon#about to write, iclass 31, count 0 2006.285.08:48:47.17#ibcon#wrote, iclass 31, count 0 2006.285.08:48:47.17#ibcon#about to read 3, iclass 31, count 0 2006.285.08:48:47.19#ibcon#read 3, iclass 31, count 0 2006.285.08:48:47.19#ibcon#about to read 4, iclass 31, count 0 2006.285.08:48:47.20#ibcon#read 4, iclass 31, count 0 2006.285.08:48:47.20#ibcon#about to read 5, iclass 31, count 0 2006.285.08:48:47.20#ibcon#read 5, iclass 31, count 0 2006.285.08:48:47.20#ibcon#about to read 6, iclass 31, count 0 2006.285.08:48:47.20#ibcon#read 6, iclass 31, count 0 2006.285.08:48:47.20#ibcon#end of sib2, iclass 31, count 0 2006.285.08:48:47.20#ibcon#*after write, iclass 31, count 0 2006.285.08:48:47.20#ibcon#*before return 0, iclass 31, count 0 2006.285.08:48:47.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:48:47.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:48:47.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.08:48:47.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.08:48:47.20$vck44/valo=2,534.99 2006.285.08:48:47.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.08:48:47.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.08:48:47.20#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:47.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:48:47.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:48:47.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:48:47.20#ibcon#enter wrdev, iclass 33, count 0 2006.285.08:48:47.20#ibcon#first serial, iclass 33, count 0 2006.285.08:48:47.20#ibcon#enter sib2, iclass 33, count 0 2006.285.08:48:47.20#ibcon#flushed, iclass 33, count 0 2006.285.08:48:47.20#ibcon#about to write, iclass 33, count 0 2006.285.08:48:47.20#ibcon#wrote, iclass 33, count 0 2006.285.08:48:47.20#ibcon#about to read 3, iclass 33, count 0 2006.285.08:48:47.21#ibcon#read 3, iclass 33, count 0 2006.285.08:48:47.21#ibcon#about to read 4, iclass 33, count 0 2006.285.08:48:47.21#ibcon#read 4, iclass 33, count 0 2006.285.08:48:47.22#ibcon#about to read 5, iclass 33, count 0 2006.285.08:48:47.22#ibcon#read 5, iclass 33, count 0 2006.285.08:48:47.22#ibcon#about to read 6, iclass 33, count 0 2006.285.08:48:47.22#ibcon#read 6, iclass 33, count 0 2006.285.08:48:47.22#ibcon#end of sib2, iclass 33, count 0 2006.285.08:48:47.22#ibcon#*mode == 0, iclass 33, count 0 2006.285.08:48:47.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.08:48:47.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:48:47.22#ibcon#*before write, iclass 33, count 0 2006.285.08:48:47.22#ibcon#enter sib2, iclass 33, count 0 2006.285.08:48:47.22#ibcon#flushed, iclass 33, count 0 2006.285.08:48:47.22#ibcon#about to write, iclass 33, count 0 2006.285.08:48:47.22#ibcon#wrote, iclass 33, count 0 2006.285.08:48:47.22#ibcon#about to read 3, iclass 33, count 0 2006.285.08:48:47.25#ibcon#read 3, iclass 33, count 0 2006.285.08:48:47.25#ibcon#about to read 4, iclass 33, count 0 2006.285.08:48:47.25#ibcon#read 4, iclass 33, count 0 2006.285.08:48:47.25#ibcon#about to read 5, iclass 33, count 0 2006.285.08:48:47.26#ibcon#read 5, iclass 33, count 0 2006.285.08:48:47.26#ibcon#about to read 6, iclass 33, count 0 2006.285.08:48:47.26#ibcon#read 6, iclass 33, count 0 2006.285.08:48:47.26#ibcon#end of sib2, iclass 33, count 0 2006.285.08:48:47.26#ibcon#*after write, iclass 33, count 0 2006.285.08:48:47.26#ibcon#*before return 0, iclass 33, count 0 2006.285.08:48:47.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:48:47.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:48:47.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.08:48:47.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.08:48:47.26$vck44/va=2,6 2006.285.08:48:47.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.08:48:47.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.08:48:47.26#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:47.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:48:47.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:48:47.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:48:47.31#ibcon#enter wrdev, iclass 35, count 2 2006.285.08:48:47.31#ibcon#first serial, iclass 35, count 2 2006.285.08:48:47.32#ibcon#enter sib2, iclass 35, count 2 2006.285.08:48:47.32#ibcon#flushed, iclass 35, count 2 2006.285.08:48:47.32#ibcon#about to write, iclass 35, count 2 2006.285.08:48:47.32#ibcon#wrote, iclass 35, count 2 2006.285.08:48:47.32#ibcon#about to read 3, iclass 35, count 2 2006.285.08:48:47.33#ibcon#read 3, iclass 35, count 2 2006.285.08:48:47.33#ibcon#about to read 4, iclass 35, count 2 2006.285.08:48:47.33#ibcon#read 4, iclass 35, count 2 2006.285.08:48:47.33#ibcon#about to read 5, iclass 35, count 2 2006.285.08:48:47.34#ibcon#read 5, iclass 35, count 2 2006.285.08:48:47.34#ibcon#about to read 6, iclass 35, count 2 2006.285.08:48:47.34#ibcon#read 6, iclass 35, count 2 2006.285.08:48:47.34#ibcon#end of sib2, iclass 35, count 2 2006.285.08:48:47.34#ibcon#*mode == 0, iclass 35, count 2 2006.285.08:48:47.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.08:48:47.34#ibcon#[25=AT02-06\r\n] 2006.285.08:48:47.34#ibcon#*before write, iclass 35, count 2 2006.285.08:48:47.34#ibcon#enter sib2, iclass 35, count 2 2006.285.08:48:47.34#ibcon#flushed, iclass 35, count 2 2006.285.08:48:47.34#ibcon#about to write, iclass 35, count 2 2006.285.08:48:47.34#ibcon#wrote, iclass 35, count 2 2006.285.08:48:47.34#ibcon#about to read 3, iclass 35, count 2 2006.285.08:48:47.36#ibcon#read 3, iclass 35, count 2 2006.285.08:48:47.36#ibcon#about to read 4, iclass 35, count 2 2006.285.08:48:47.36#ibcon#read 4, iclass 35, count 2 2006.285.08:48:47.37#ibcon#about to read 5, iclass 35, count 2 2006.285.08:48:47.37#ibcon#read 5, iclass 35, count 2 2006.285.08:48:47.37#ibcon#about to read 6, iclass 35, count 2 2006.285.08:48:47.37#ibcon#read 6, iclass 35, count 2 2006.285.08:48:47.37#ibcon#end of sib2, iclass 35, count 2 2006.285.08:48:47.37#ibcon#*after write, iclass 35, count 2 2006.285.08:48:47.37#ibcon#*before return 0, iclass 35, count 2 2006.285.08:48:47.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:48:47.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:48:47.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.08:48:47.37#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:47.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:48:47.48#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:48:47.48#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:48:47.49#ibcon#enter wrdev, iclass 35, count 0 2006.285.08:48:47.49#ibcon#first serial, iclass 35, count 0 2006.285.08:48:47.49#ibcon#enter sib2, iclass 35, count 0 2006.285.08:48:47.49#ibcon#flushed, iclass 35, count 0 2006.285.08:48:47.49#ibcon#about to write, iclass 35, count 0 2006.285.08:48:47.49#ibcon#wrote, iclass 35, count 0 2006.285.08:48:47.49#ibcon#about to read 3, iclass 35, count 0 2006.285.08:48:47.50#ibcon#read 3, iclass 35, count 0 2006.285.08:48:47.51#ibcon#about to read 4, iclass 35, count 0 2006.285.08:48:47.51#ibcon#read 4, iclass 35, count 0 2006.285.08:48:47.51#ibcon#about to read 5, iclass 35, count 0 2006.285.08:48:47.51#ibcon#read 5, iclass 35, count 0 2006.285.08:48:47.51#ibcon#about to read 6, iclass 35, count 0 2006.285.08:48:47.51#ibcon#read 6, iclass 35, count 0 2006.285.08:48:47.51#ibcon#end of sib2, iclass 35, count 0 2006.285.08:48:47.51#ibcon#*mode == 0, iclass 35, count 0 2006.285.08:48:47.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.08:48:47.51#ibcon#[25=USB\r\n] 2006.285.08:48:47.51#ibcon#*before write, iclass 35, count 0 2006.285.08:48:47.51#ibcon#enter sib2, iclass 35, count 0 2006.285.08:48:47.51#ibcon#flushed, iclass 35, count 0 2006.285.08:48:47.51#ibcon#about to write, iclass 35, count 0 2006.285.08:48:47.51#ibcon#wrote, iclass 35, count 0 2006.285.08:48:47.51#ibcon#about to read 3, iclass 35, count 0 2006.285.08:48:47.53#ibcon#read 3, iclass 35, count 0 2006.285.08:48:47.54#ibcon#about to read 4, iclass 35, count 0 2006.285.08:48:47.54#ibcon#read 4, iclass 35, count 0 2006.285.08:48:47.54#ibcon#about to read 5, iclass 35, count 0 2006.285.08:48:47.54#ibcon#read 5, iclass 35, count 0 2006.285.08:48:47.54#ibcon#about to read 6, iclass 35, count 0 2006.285.08:48:47.54#ibcon#read 6, iclass 35, count 0 2006.285.08:48:47.54#ibcon#end of sib2, iclass 35, count 0 2006.285.08:48:47.54#ibcon#*after write, iclass 35, count 0 2006.285.08:48:47.54#ibcon#*before return 0, iclass 35, count 0 2006.285.08:48:47.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:48:47.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:48:47.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.08:48:47.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.08:48:47.54$vck44/valo=3,564.99 2006.285.08:48:47.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.08:48:47.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.08:48:47.54#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:47.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:48:47.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:48:47.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:48:47.54#ibcon#enter wrdev, iclass 37, count 0 2006.285.08:48:47.54#ibcon#first serial, iclass 37, count 0 2006.285.08:48:47.54#ibcon#enter sib2, iclass 37, count 0 2006.285.08:48:47.54#ibcon#flushed, iclass 37, count 0 2006.285.08:48:47.54#ibcon#about to write, iclass 37, count 0 2006.285.08:48:47.54#ibcon#wrote, iclass 37, count 0 2006.285.08:48:47.54#ibcon#about to read 3, iclass 37, count 0 2006.285.08:48:47.55#ibcon#read 3, iclass 37, count 0 2006.285.08:48:47.55#ibcon#about to read 4, iclass 37, count 0 2006.285.08:48:47.56#ibcon#read 4, iclass 37, count 0 2006.285.08:48:47.56#ibcon#about to read 5, iclass 37, count 0 2006.285.08:48:47.56#ibcon#read 5, iclass 37, count 0 2006.285.08:48:47.56#ibcon#about to read 6, iclass 37, count 0 2006.285.08:48:47.56#ibcon#read 6, iclass 37, count 0 2006.285.08:48:47.56#ibcon#end of sib2, iclass 37, count 0 2006.285.08:48:47.56#ibcon#*mode == 0, iclass 37, count 0 2006.285.08:48:47.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.08:48:47.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:48:47.56#ibcon#*before write, iclass 37, count 0 2006.285.08:48:47.56#ibcon#enter sib2, iclass 37, count 0 2006.285.08:48:47.56#ibcon#flushed, iclass 37, count 0 2006.285.08:48:47.56#ibcon#about to write, iclass 37, count 0 2006.285.08:48:47.56#ibcon#wrote, iclass 37, count 0 2006.285.08:48:47.56#ibcon#about to read 3, iclass 37, count 0 2006.285.08:48:47.59#ibcon#read 3, iclass 37, count 0 2006.285.08:48:47.59#ibcon#about to read 4, iclass 37, count 0 2006.285.08:48:47.60#ibcon#read 4, iclass 37, count 0 2006.285.08:48:47.60#ibcon#about to read 5, iclass 37, count 0 2006.285.08:48:47.60#ibcon#read 5, iclass 37, count 0 2006.285.08:48:47.60#ibcon#about to read 6, iclass 37, count 0 2006.285.08:48:47.60#ibcon#read 6, iclass 37, count 0 2006.285.08:48:47.60#ibcon#end of sib2, iclass 37, count 0 2006.285.08:48:47.60#ibcon#*after write, iclass 37, count 0 2006.285.08:48:47.60#ibcon#*before return 0, iclass 37, count 0 2006.285.08:48:47.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:48:47.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:48:47.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.08:48:47.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.08:48:47.60$vck44/va=3,7 2006.285.08:48:47.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.08:48:47.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.08:48:47.60#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:47.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:48:47.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:48:47.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:48:47.65#ibcon#enter wrdev, iclass 39, count 2 2006.285.08:48:47.66#ibcon#first serial, iclass 39, count 2 2006.285.08:48:47.66#ibcon#enter sib2, iclass 39, count 2 2006.285.08:48:47.66#ibcon#flushed, iclass 39, count 2 2006.285.08:48:47.66#ibcon#about to write, iclass 39, count 2 2006.285.08:48:47.66#ibcon#wrote, iclass 39, count 2 2006.285.08:48:47.66#ibcon#about to read 3, iclass 39, count 2 2006.285.08:48:47.67#ibcon#read 3, iclass 39, count 2 2006.285.08:48:47.67#ibcon#about to read 4, iclass 39, count 2 2006.285.08:48:47.67#ibcon#read 4, iclass 39, count 2 2006.285.08:48:47.68#ibcon#about to read 5, iclass 39, count 2 2006.285.08:48:47.68#ibcon#read 5, iclass 39, count 2 2006.285.08:48:47.68#ibcon#about to read 6, iclass 39, count 2 2006.285.08:48:47.68#ibcon#read 6, iclass 39, count 2 2006.285.08:48:47.68#ibcon#end of sib2, iclass 39, count 2 2006.285.08:48:47.68#ibcon#*mode == 0, iclass 39, count 2 2006.285.08:48:47.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.08:48:47.68#ibcon#[25=AT03-07\r\n] 2006.285.08:48:47.68#ibcon#*before write, iclass 39, count 2 2006.285.08:48:47.68#ibcon#enter sib2, iclass 39, count 2 2006.285.08:48:47.68#ibcon#flushed, iclass 39, count 2 2006.285.08:48:47.68#ibcon#about to write, iclass 39, count 2 2006.285.08:48:47.68#ibcon#wrote, iclass 39, count 2 2006.285.08:48:47.68#ibcon#about to read 3, iclass 39, count 2 2006.285.08:48:47.70#ibcon#read 3, iclass 39, count 2 2006.285.08:48:47.70#ibcon#about to read 4, iclass 39, count 2 2006.285.08:48:47.70#ibcon#read 4, iclass 39, count 2 2006.285.08:48:47.70#ibcon#about to read 5, iclass 39, count 2 2006.285.08:48:47.71#ibcon#read 5, iclass 39, count 2 2006.285.08:48:47.71#ibcon#about to read 6, iclass 39, count 2 2006.285.08:48:47.71#ibcon#read 6, iclass 39, count 2 2006.285.08:48:47.71#ibcon#end of sib2, iclass 39, count 2 2006.285.08:48:47.71#ibcon#*after write, iclass 39, count 2 2006.285.08:48:47.71#ibcon#*before return 0, iclass 39, count 2 2006.285.08:48:47.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:48:47.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:48:47.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.08:48:47.71#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:47.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:48:47.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:48:47.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:48:47.82#ibcon#enter wrdev, iclass 39, count 0 2006.285.08:48:47.82#ibcon#first serial, iclass 39, count 0 2006.285.08:48:47.83#ibcon#enter sib2, iclass 39, count 0 2006.285.08:48:47.83#ibcon#flushed, iclass 39, count 0 2006.285.08:48:47.83#ibcon#about to write, iclass 39, count 0 2006.285.08:48:47.83#ibcon#wrote, iclass 39, count 0 2006.285.08:48:47.83#ibcon#about to read 3, iclass 39, count 0 2006.285.08:48:47.84#ibcon#read 3, iclass 39, count 0 2006.285.08:48:47.84#ibcon#about to read 4, iclass 39, count 0 2006.285.08:48:47.84#ibcon#read 4, iclass 39, count 0 2006.285.08:48:47.84#ibcon#about to read 5, iclass 39, count 0 2006.285.08:48:47.85#ibcon#read 5, iclass 39, count 0 2006.285.08:48:47.85#ibcon#about to read 6, iclass 39, count 0 2006.285.08:48:47.85#ibcon#read 6, iclass 39, count 0 2006.285.08:48:47.85#ibcon#end of sib2, iclass 39, count 0 2006.285.08:48:47.85#ibcon#*mode == 0, iclass 39, count 0 2006.285.08:48:47.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.08:48:47.85#ibcon#[25=USB\r\n] 2006.285.08:48:47.85#ibcon#*before write, iclass 39, count 0 2006.285.08:48:47.85#ibcon#enter sib2, iclass 39, count 0 2006.285.08:48:47.85#ibcon#flushed, iclass 39, count 0 2006.285.08:48:47.85#ibcon#about to write, iclass 39, count 0 2006.285.08:48:47.85#ibcon#wrote, iclass 39, count 0 2006.285.08:48:47.85#ibcon#about to read 3, iclass 39, count 0 2006.285.08:48:47.87#ibcon#read 3, iclass 39, count 0 2006.285.08:48:47.87#ibcon#about to read 4, iclass 39, count 0 2006.285.08:48:47.87#ibcon#read 4, iclass 39, count 0 2006.285.08:48:47.87#ibcon#about to read 5, iclass 39, count 0 2006.285.08:48:47.88#ibcon#read 5, iclass 39, count 0 2006.285.08:48:47.88#ibcon#about to read 6, iclass 39, count 0 2006.285.08:48:47.88#ibcon#read 6, iclass 39, count 0 2006.285.08:48:47.88#ibcon#end of sib2, iclass 39, count 0 2006.285.08:48:47.88#ibcon#*after write, iclass 39, count 0 2006.285.08:48:47.88#ibcon#*before return 0, iclass 39, count 0 2006.285.08:48:47.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:48:47.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:48:47.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.08:48:47.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.08:48:47.88$vck44/valo=4,624.99 2006.285.08:48:47.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.08:48:47.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.08:48:47.88#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:47.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:48:47.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:48:47.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:48:47.88#ibcon#enter wrdev, iclass 3, count 0 2006.285.08:48:47.88#ibcon#first serial, iclass 3, count 0 2006.285.08:48:47.88#ibcon#enter sib2, iclass 3, count 0 2006.285.08:48:47.88#ibcon#flushed, iclass 3, count 0 2006.285.08:48:47.88#ibcon#about to write, iclass 3, count 0 2006.285.08:48:47.88#ibcon#wrote, iclass 3, count 0 2006.285.08:48:47.88#ibcon#about to read 3, iclass 3, count 0 2006.285.08:48:47.89#ibcon#read 3, iclass 3, count 0 2006.285.08:48:47.89#ibcon#about to read 4, iclass 3, count 0 2006.285.08:48:47.89#ibcon#read 4, iclass 3, count 0 2006.285.08:48:47.90#ibcon#about to read 5, iclass 3, count 0 2006.285.08:48:47.90#ibcon#read 5, iclass 3, count 0 2006.285.08:48:47.90#ibcon#about to read 6, iclass 3, count 0 2006.285.08:48:47.90#ibcon#read 6, iclass 3, count 0 2006.285.08:48:47.90#ibcon#end of sib2, iclass 3, count 0 2006.285.08:48:47.90#ibcon#*mode == 0, iclass 3, count 0 2006.285.08:48:47.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.08:48:47.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:48:47.90#ibcon#*before write, iclass 3, count 0 2006.285.08:48:47.90#ibcon#enter sib2, iclass 3, count 0 2006.285.08:48:47.90#ibcon#flushed, iclass 3, count 0 2006.285.08:48:47.90#ibcon#about to write, iclass 3, count 0 2006.285.08:48:47.90#ibcon#wrote, iclass 3, count 0 2006.285.08:48:47.90#ibcon#about to read 3, iclass 3, count 0 2006.285.08:48:47.93#ibcon#read 3, iclass 3, count 0 2006.285.08:48:47.93#ibcon#about to read 4, iclass 3, count 0 2006.285.08:48:47.93#ibcon#read 4, iclass 3, count 0 2006.285.08:48:47.93#ibcon#about to read 5, iclass 3, count 0 2006.285.08:48:47.94#ibcon#read 5, iclass 3, count 0 2006.285.08:48:47.94#ibcon#about to read 6, iclass 3, count 0 2006.285.08:48:47.94#ibcon#read 6, iclass 3, count 0 2006.285.08:48:47.94#ibcon#end of sib2, iclass 3, count 0 2006.285.08:48:47.94#ibcon#*after write, iclass 3, count 0 2006.285.08:48:47.94#ibcon#*before return 0, iclass 3, count 0 2006.285.08:48:47.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:48:47.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:48:47.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.08:48:47.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.08:48:47.94$vck44/va=4,6 2006.285.08:48:47.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.08:48:47.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.08:48:47.94#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:47.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:48:47.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:48:47.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:48:47.99#ibcon#enter wrdev, iclass 5, count 2 2006.285.08:48:48.00#ibcon#first serial, iclass 5, count 2 2006.285.08:48:48.00#ibcon#enter sib2, iclass 5, count 2 2006.285.08:48:48.00#ibcon#flushed, iclass 5, count 2 2006.285.08:48:48.00#ibcon#about to write, iclass 5, count 2 2006.285.08:48:48.00#ibcon#wrote, iclass 5, count 2 2006.285.08:48:48.00#ibcon#about to read 3, iclass 5, count 2 2006.285.08:48:48.01#ibcon#read 3, iclass 5, count 2 2006.285.08:48:48.01#ibcon#about to read 4, iclass 5, count 2 2006.285.08:48:48.01#ibcon#read 4, iclass 5, count 2 2006.285.08:48:48.02#ibcon#about to read 5, iclass 5, count 2 2006.285.08:48:48.02#ibcon#read 5, iclass 5, count 2 2006.285.08:48:48.02#ibcon#about to read 6, iclass 5, count 2 2006.285.08:48:48.02#ibcon#read 6, iclass 5, count 2 2006.285.08:48:48.02#ibcon#end of sib2, iclass 5, count 2 2006.285.08:48:48.02#ibcon#*mode == 0, iclass 5, count 2 2006.285.08:48:48.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.08:48:48.02#ibcon#[25=AT04-06\r\n] 2006.285.08:48:48.02#ibcon#*before write, iclass 5, count 2 2006.285.08:48:48.02#ibcon#enter sib2, iclass 5, count 2 2006.285.08:48:48.02#ibcon#flushed, iclass 5, count 2 2006.285.08:48:48.02#ibcon#about to write, iclass 5, count 2 2006.285.08:48:48.02#ibcon#wrote, iclass 5, count 2 2006.285.08:48:48.02#ibcon#about to read 3, iclass 5, count 2 2006.285.08:48:48.04#ibcon#read 3, iclass 5, count 2 2006.285.08:48:48.04#ibcon#about to read 4, iclass 5, count 2 2006.285.08:48:48.04#ibcon#read 4, iclass 5, count 2 2006.285.08:48:48.05#ibcon#about to read 5, iclass 5, count 2 2006.285.08:48:48.05#ibcon#read 5, iclass 5, count 2 2006.285.08:48:48.05#ibcon#about to read 6, iclass 5, count 2 2006.285.08:48:48.05#ibcon#read 6, iclass 5, count 2 2006.285.08:48:48.05#ibcon#end of sib2, iclass 5, count 2 2006.285.08:48:48.05#ibcon#*after write, iclass 5, count 2 2006.285.08:48:48.05#ibcon#*before return 0, iclass 5, count 2 2006.285.08:48:48.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:48:48.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:48:48.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.08:48:48.05#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:48.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:48:48.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:48:48.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:48:48.16#ibcon#enter wrdev, iclass 5, count 0 2006.285.08:48:48.17#ibcon#first serial, iclass 5, count 0 2006.285.08:48:48.17#ibcon#enter sib2, iclass 5, count 0 2006.285.08:48:48.17#ibcon#flushed, iclass 5, count 0 2006.285.08:48:48.17#ibcon#about to write, iclass 5, count 0 2006.285.08:48:48.17#ibcon#wrote, iclass 5, count 0 2006.285.08:48:48.17#ibcon#about to read 3, iclass 5, count 0 2006.285.08:48:48.18#ibcon#read 3, iclass 5, count 0 2006.285.08:48:48.18#ibcon#about to read 4, iclass 5, count 0 2006.285.08:48:48.19#ibcon#read 4, iclass 5, count 0 2006.285.08:48:48.19#ibcon#about to read 5, iclass 5, count 0 2006.285.08:48:48.19#ibcon#read 5, iclass 5, count 0 2006.285.08:48:48.19#ibcon#about to read 6, iclass 5, count 0 2006.285.08:48:48.19#ibcon#read 6, iclass 5, count 0 2006.285.08:48:48.19#ibcon#end of sib2, iclass 5, count 0 2006.285.08:48:48.19#ibcon#*mode == 0, iclass 5, count 0 2006.285.08:48:48.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.08:48:48.19#ibcon#[25=USB\r\n] 2006.285.08:48:48.19#ibcon#*before write, iclass 5, count 0 2006.285.08:48:48.19#ibcon#enter sib2, iclass 5, count 0 2006.285.08:48:48.19#ibcon#flushed, iclass 5, count 0 2006.285.08:48:48.19#ibcon#about to write, iclass 5, count 0 2006.285.08:48:48.19#ibcon#wrote, iclass 5, count 0 2006.285.08:48:48.19#ibcon#about to read 3, iclass 5, count 0 2006.285.08:48:48.21#ibcon#read 3, iclass 5, count 0 2006.285.08:48:48.21#ibcon#about to read 4, iclass 5, count 0 2006.285.08:48:48.21#ibcon#read 4, iclass 5, count 0 2006.285.08:48:48.21#ibcon#about to read 5, iclass 5, count 0 2006.285.08:48:48.22#ibcon#read 5, iclass 5, count 0 2006.285.08:48:48.22#ibcon#about to read 6, iclass 5, count 0 2006.285.08:48:48.22#ibcon#read 6, iclass 5, count 0 2006.285.08:48:48.22#ibcon#end of sib2, iclass 5, count 0 2006.285.08:48:48.22#ibcon#*after write, iclass 5, count 0 2006.285.08:48:48.22#ibcon#*before return 0, iclass 5, count 0 2006.285.08:48:48.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:48:48.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:48:48.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.08:48:48.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.08:48:48.22$vck44/valo=5,734.99 2006.285.08:48:48.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.08:48:48.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.08:48:48.22#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:48.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:48:48.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:48:48.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:48:48.22#ibcon#enter wrdev, iclass 7, count 0 2006.285.08:48:48.22#ibcon#first serial, iclass 7, count 0 2006.285.08:48:48.22#ibcon#enter sib2, iclass 7, count 0 2006.285.08:48:48.22#ibcon#flushed, iclass 7, count 0 2006.285.08:48:48.22#ibcon#about to write, iclass 7, count 0 2006.285.08:48:48.22#ibcon#wrote, iclass 7, count 0 2006.285.08:48:48.22#ibcon#about to read 3, iclass 7, count 0 2006.285.08:48:48.23#ibcon#read 3, iclass 7, count 0 2006.285.08:48:48.23#ibcon#about to read 4, iclass 7, count 0 2006.285.08:48:48.23#ibcon#read 4, iclass 7, count 0 2006.285.08:48:48.24#ibcon#about to read 5, iclass 7, count 0 2006.285.08:48:48.24#ibcon#read 5, iclass 7, count 0 2006.285.08:48:48.24#ibcon#about to read 6, iclass 7, count 0 2006.285.08:48:48.24#ibcon#read 6, iclass 7, count 0 2006.285.08:48:48.24#ibcon#end of sib2, iclass 7, count 0 2006.285.08:48:48.24#ibcon#*mode == 0, iclass 7, count 0 2006.285.08:48:48.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.08:48:48.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:48:48.24#ibcon#*before write, iclass 7, count 0 2006.285.08:48:48.24#ibcon#enter sib2, iclass 7, count 0 2006.285.08:48:48.24#ibcon#flushed, iclass 7, count 0 2006.285.08:48:48.24#ibcon#about to write, iclass 7, count 0 2006.285.08:48:48.24#ibcon#wrote, iclass 7, count 0 2006.285.08:48:48.24#ibcon#about to read 3, iclass 7, count 0 2006.285.08:48:48.27#ibcon#read 3, iclass 7, count 0 2006.285.08:48:48.27#ibcon#about to read 4, iclass 7, count 0 2006.285.08:48:48.27#ibcon#read 4, iclass 7, count 0 2006.285.08:48:48.27#ibcon#about to read 5, iclass 7, count 0 2006.285.08:48:48.28#ibcon#read 5, iclass 7, count 0 2006.285.08:48:48.28#ibcon#about to read 6, iclass 7, count 0 2006.285.08:48:48.28#ibcon#read 6, iclass 7, count 0 2006.285.08:48:48.28#ibcon#end of sib2, iclass 7, count 0 2006.285.08:48:48.28#ibcon#*after write, iclass 7, count 0 2006.285.08:48:48.28#ibcon#*before return 0, iclass 7, count 0 2006.285.08:48:48.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:48:48.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:48:48.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.08:48:48.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.08:48:48.28$vck44/va=5,3 2006.285.08:48:48.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.08:48:48.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.08:48:48.28#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:48.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:48:48.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:48:48.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:48:48.33#ibcon#enter wrdev, iclass 11, count 2 2006.285.08:48:48.33#ibcon#first serial, iclass 11, count 2 2006.285.08:48:48.34#ibcon#enter sib2, iclass 11, count 2 2006.285.08:48:48.34#ibcon#flushed, iclass 11, count 2 2006.285.08:48:48.34#ibcon#about to write, iclass 11, count 2 2006.285.08:48:48.34#ibcon#wrote, iclass 11, count 2 2006.285.08:48:48.34#ibcon#about to read 3, iclass 11, count 2 2006.285.08:48:48.35#ibcon#read 3, iclass 11, count 2 2006.285.08:48:48.35#ibcon#about to read 4, iclass 11, count 2 2006.285.08:48:48.35#ibcon#read 4, iclass 11, count 2 2006.285.08:48:48.35#ibcon#about to read 5, iclass 11, count 2 2006.285.08:48:48.36#ibcon#read 5, iclass 11, count 2 2006.285.08:48:48.36#ibcon#about to read 6, iclass 11, count 2 2006.285.08:48:48.36#ibcon#read 6, iclass 11, count 2 2006.285.08:48:48.36#ibcon#end of sib2, iclass 11, count 2 2006.285.08:48:48.36#ibcon#*mode == 0, iclass 11, count 2 2006.285.08:48:48.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.08:48:48.36#ibcon#[25=AT05-03\r\n] 2006.285.08:48:48.36#ibcon#*before write, iclass 11, count 2 2006.285.08:48:48.36#ibcon#enter sib2, iclass 11, count 2 2006.285.08:48:48.36#ibcon#flushed, iclass 11, count 2 2006.285.08:48:48.36#ibcon#about to write, iclass 11, count 2 2006.285.08:48:48.36#ibcon#wrote, iclass 11, count 2 2006.285.08:48:48.36#ibcon#about to read 3, iclass 11, count 2 2006.285.08:48:48.38#ibcon#read 3, iclass 11, count 2 2006.285.08:48:48.38#ibcon#about to read 4, iclass 11, count 2 2006.285.08:48:48.38#ibcon#read 4, iclass 11, count 2 2006.285.08:48:48.38#ibcon#about to read 5, iclass 11, count 2 2006.285.08:48:48.39#ibcon#read 5, iclass 11, count 2 2006.285.08:48:48.39#ibcon#about to read 6, iclass 11, count 2 2006.285.08:48:48.39#ibcon#read 6, iclass 11, count 2 2006.285.08:48:48.39#ibcon#end of sib2, iclass 11, count 2 2006.285.08:48:48.39#ibcon#*after write, iclass 11, count 2 2006.285.08:48:48.39#ibcon#*before return 0, iclass 11, count 2 2006.285.08:48:48.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:48:48.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:48:48.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.08:48:48.39#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:48.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:48:48.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:48:48.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:48:48.50#ibcon#enter wrdev, iclass 11, count 0 2006.285.08:48:48.51#ibcon#first serial, iclass 11, count 0 2006.285.08:48:48.51#ibcon#enter sib2, iclass 11, count 0 2006.285.08:48:48.51#ibcon#flushed, iclass 11, count 0 2006.285.08:48:48.51#ibcon#about to write, iclass 11, count 0 2006.285.08:48:48.51#ibcon#wrote, iclass 11, count 0 2006.285.08:48:48.51#ibcon#about to read 3, iclass 11, count 0 2006.285.08:48:48.52#ibcon#read 3, iclass 11, count 0 2006.285.08:48:48.52#ibcon#about to read 4, iclass 11, count 0 2006.285.08:48:48.53#ibcon#read 4, iclass 11, count 0 2006.285.08:48:48.53#ibcon#about to read 5, iclass 11, count 0 2006.285.08:48:48.53#ibcon#read 5, iclass 11, count 0 2006.285.08:48:48.53#ibcon#about to read 6, iclass 11, count 0 2006.285.08:48:48.53#ibcon#read 6, iclass 11, count 0 2006.285.08:48:48.53#ibcon#end of sib2, iclass 11, count 0 2006.285.08:48:48.53#ibcon#*mode == 0, iclass 11, count 0 2006.285.08:48:48.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.08:48:48.53#ibcon#[25=USB\r\n] 2006.285.08:48:48.53#ibcon#*before write, iclass 11, count 0 2006.285.08:48:48.53#ibcon#enter sib2, iclass 11, count 0 2006.285.08:48:48.53#ibcon#flushed, iclass 11, count 0 2006.285.08:48:48.53#ibcon#about to write, iclass 11, count 0 2006.285.08:48:48.53#ibcon#wrote, iclass 11, count 0 2006.285.08:48:48.53#ibcon#about to read 3, iclass 11, count 0 2006.285.08:48:48.55#ibcon#read 3, iclass 11, count 0 2006.285.08:48:48.55#ibcon#about to read 4, iclass 11, count 0 2006.285.08:48:48.56#ibcon#read 4, iclass 11, count 0 2006.285.08:48:48.56#ibcon#about to read 5, iclass 11, count 0 2006.285.08:48:48.56#ibcon#read 5, iclass 11, count 0 2006.285.08:48:48.56#ibcon#about to read 6, iclass 11, count 0 2006.285.08:48:48.56#ibcon#read 6, iclass 11, count 0 2006.285.08:48:48.56#ibcon#end of sib2, iclass 11, count 0 2006.285.08:48:48.56#ibcon#*after write, iclass 11, count 0 2006.285.08:48:48.56#ibcon#*before return 0, iclass 11, count 0 2006.285.08:48:48.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:48:48.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:48:48.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.08:48:48.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.08:48:48.56$vck44/valo=6,814.99 2006.285.08:48:48.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.08:48:48.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.08:48:48.56#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:48.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:48:48.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:48:48.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:48:48.56#ibcon#enter wrdev, iclass 13, count 0 2006.285.08:48:48.56#ibcon#first serial, iclass 13, count 0 2006.285.08:48:48.56#ibcon#enter sib2, iclass 13, count 0 2006.285.08:48:48.56#ibcon#flushed, iclass 13, count 0 2006.285.08:48:48.56#ibcon#about to write, iclass 13, count 0 2006.285.08:48:48.56#ibcon#wrote, iclass 13, count 0 2006.285.08:48:48.56#ibcon#about to read 3, iclass 13, count 0 2006.285.08:48:48.57#ibcon#read 3, iclass 13, count 0 2006.285.08:48:48.57#ibcon#about to read 4, iclass 13, count 0 2006.285.08:48:48.57#ibcon#read 4, iclass 13, count 0 2006.285.08:48:48.58#ibcon#about to read 5, iclass 13, count 0 2006.285.08:48:48.58#ibcon#read 5, iclass 13, count 0 2006.285.08:48:48.58#ibcon#about to read 6, iclass 13, count 0 2006.285.08:48:48.58#ibcon#read 6, iclass 13, count 0 2006.285.08:48:48.58#ibcon#end of sib2, iclass 13, count 0 2006.285.08:48:48.58#ibcon#*mode == 0, iclass 13, count 0 2006.285.08:48:48.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.08:48:48.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:48:48.58#ibcon#*before write, iclass 13, count 0 2006.285.08:48:48.58#ibcon#enter sib2, iclass 13, count 0 2006.285.08:48:48.58#ibcon#flushed, iclass 13, count 0 2006.285.08:48:48.58#ibcon#about to write, iclass 13, count 0 2006.285.08:48:48.58#ibcon#wrote, iclass 13, count 0 2006.285.08:48:48.58#ibcon#about to read 3, iclass 13, count 0 2006.285.08:48:48.61#ibcon#read 3, iclass 13, count 0 2006.285.08:48:48.61#ibcon#about to read 4, iclass 13, count 0 2006.285.08:48:48.61#ibcon#read 4, iclass 13, count 0 2006.285.08:48:48.61#ibcon#about to read 5, iclass 13, count 0 2006.285.08:48:48.62#ibcon#read 5, iclass 13, count 0 2006.285.08:48:48.62#ibcon#about to read 6, iclass 13, count 0 2006.285.08:48:48.62#ibcon#read 6, iclass 13, count 0 2006.285.08:48:48.62#ibcon#end of sib2, iclass 13, count 0 2006.285.08:48:48.62#ibcon#*after write, iclass 13, count 0 2006.285.08:48:48.62#ibcon#*before return 0, iclass 13, count 0 2006.285.08:48:48.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:48:48.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:48:48.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.08:48:48.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.08:48:48.62$vck44/va=6,4 2006.285.08:48:48.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.08:48:48.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.08:48:48.62#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:48.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:48:48.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:48:48.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:48:48.67#ibcon#enter wrdev, iclass 15, count 2 2006.285.08:48:48.67#ibcon#first serial, iclass 15, count 2 2006.285.08:48:48.68#ibcon#enter sib2, iclass 15, count 2 2006.285.08:48:48.68#ibcon#flushed, iclass 15, count 2 2006.285.08:48:48.68#ibcon#about to write, iclass 15, count 2 2006.285.08:48:48.68#ibcon#wrote, iclass 15, count 2 2006.285.08:48:48.68#ibcon#about to read 3, iclass 15, count 2 2006.285.08:48:48.69#ibcon#read 3, iclass 15, count 2 2006.285.08:48:48.69#ibcon#about to read 4, iclass 15, count 2 2006.285.08:48:48.69#ibcon#read 4, iclass 15, count 2 2006.285.08:48:48.69#ibcon#about to read 5, iclass 15, count 2 2006.285.08:48:48.70#ibcon#read 5, iclass 15, count 2 2006.285.08:48:48.70#ibcon#about to read 6, iclass 15, count 2 2006.285.08:48:48.70#ibcon#read 6, iclass 15, count 2 2006.285.08:48:48.70#ibcon#end of sib2, iclass 15, count 2 2006.285.08:48:48.70#ibcon#*mode == 0, iclass 15, count 2 2006.285.08:48:48.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.08:48:48.70#ibcon#[25=AT06-04\r\n] 2006.285.08:48:48.70#ibcon#*before write, iclass 15, count 2 2006.285.08:48:48.70#ibcon#enter sib2, iclass 15, count 2 2006.285.08:48:48.70#ibcon#flushed, iclass 15, count 2 2006.285.08:48:48.70#ibcon#about to write, iclass 15, count 2 2006.285.08:48:48.70#ibcon#wrote, iclass 15, count 2 2006.285.08:48:48.70#ibcon#about to read 3, iclass 15, count 2 2006.285.08:48:48.72#ibcon#read 3, iclass 15, count 2 2006.285.08:48:48.72#ibcon#about to read 4, iclass 15, count 2 2006.285.08:48:48.72#ibcon#read 4, iclass 15, count 2 2006.285.08:48:48.72#ibcon#about to read 5, iclass 15, count 2 2006.285.08:48:48.73#ibcon#read 5, iclass 15, count 2 2006.285.08:48:48.73#ibcon#about to read 6, iclass 15, count 2 2006.285.08:48:48.73#ibcon#read 6, iclass 15, count 2 2006.285.08:48:48.73#ibcon#end of sib2, iclass 15, count 2 2006.285.08:48:48.73#ibcon#*after write, iclass 15, count 2 2006.285.08:48:48.73#ibcon#*before return 0, iclass 15, count 2 2006.285.08:48:48.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:48:48.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:48:48.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.08:48:48.73#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:48.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:48:48.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:48:48.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:48:48.84#ibcon#enter wrdev, iclass 15, count 0 2006.285.08:48:48.84#ibcon#first serial, iclass 15, count 0 2006.285.08:48:48.85#ibcon#enter sib2, iclass 15, count 0 2006.285.08:48:48.85#ibcon#flushed, iclass 15, count 0 2006.285.08:48:48.85#ibcon#about to write, iclass 15, count 0 2006.285.08:48:48.85#ibcon#wrote, iclass 15, count 0 2006.285.08:48:48.85#ibcon#about to read 3, iclass 15, count 0 2006.285.08:48:48.86#ibcon#read 3, iclass 15, count 0 2006.285.08:48:48.86#ibcon#about to read 4, iclass 15, count 0 2006.285.08:48:48.86#ibcon#read 4, iclass 15, count 0 2006.285.08:48:48.86#ibcon#about to read 5, iclass 15, count 0 2006.285.08:48:48.87#ibcon#read 5, iclass 15, count 0 2006.285.08:48:48.87#ibcon#about to read 6, iclass 15, count 0 2006.285.08:48:48.87#ibcon#read 6, iclass 15, count 0 2006.285.08:48:48.87#ibcon#end of sib2, iclass 15, count 0 2006.285.08:48:48.87#ibcon#*mode == 0, iclass 15, count 0 2006.285.08:48:48.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.08:48:48.87#ibcon#[25=USB\r\n] 2006.285.08:48:48.87#ibcon#*before write, iclass 15, count 0 2006.285.08:48:48.87#ibcon#enter sib2, iclass 15, count 0 2006.285.08:48:48.87#ibcon#flushed, iclass 15, count 0 2006.285.08:48:48.87#ibcon#about to write, iclass 15, count 0 2006.285.08:48:48.87#ibcon#wrote, iclass 15, count 0 2006.285.08:48:48.87#ibcon#about to read 3, iclass 15, count 0 2006.285.08:48:48.89#ibcon#read 3, iclass 15, count 0 2006.285.08:48:48.89#ibcon#about to read 4, iclass 15, count 0 2006.285.08:48:48.89#ibcon#read 4, iclass 15, count 0 2006.285.08:48:48.89#ibcon#about to read 5, iclass 15, count 0 2006.285.08:48:48.90#ibcon#read 5, iclass 15, count 0 2006.285.08:48:48.90#ibcon#about to read 6, iclass 15, count 0 2006.285.08:48:48.90#ibcon#read 6, iclass 15, count 0 2006.285.08:48:48.90#ibcon#end of sib2, iclass 15, count 0 2006.285.08:48:48.90#ibcon#*after write, iclass 15, count 0 2006.285.08:48:48.90#ibcon#*before return 0, iclass 15, count 0 2006.285.08:48:48.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:48:48.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:48:48.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.08:48:48.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.08:48:48.90$vck44/valo=7,864.99 2006.285.08:48:48.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.08:48:48.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.08:48:48.90#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:48.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:48:48.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:48:48.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:48:48.90#ibcon#enter wrdev, iclass 17, count 0 2006.285.08:48:48.90#ibcon#first serial, iclass 17, count 0 2006.285.08:48:48.90#ibcon#enter sib2, iclass 17, count 0 2006.285.08:48:48.90#ibcon#flushed, iclass 17, count 0 2006.285.08:48:48.90#ibcon#about to write, iclass 17, count 0 2006.285.08:48:48.90#ibcon#wrote, iclass 17, count 0 2006.285.08:48:48.90#ibcon#about to read 3, iclass 17, count 0 2006.285.08:48:48.91#ibcon#read 3, iclass 17, count 0 2006.285.08:48:48.91#ibcon#about to read 4, iclass 17, count 0 2006.285.08:48:48.91#ibcon#read 4, iclass 17, count 0 2006.285.08:48:48.92#ibcon#about to read 5, iclass 17, count 0 2006.285.08:48:48.92#ibcon#read 5, iclass 17, count 0 2006.285.08:48:48.92#ibcon#about to read 6, iclass 17, count 0 2006.285.08:48:48.92#ibcon#read 6, iclass 17, count 0 2006.285.08:48:48.92#ibcon#end of sib2, iclass 17, count 0 2006.285.08:48:48.92#ibcon#*mode == 0, iclass 17, count 0 2006.285.08:48:48.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.08:48:48.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:48:48.92#ibcon#*before write, iclass 17, count 0 2006.285.08:48:48.92#ibcon#enter sib2, iclass 17, count 0 2006.285.08:48:48.92#ibcon#flushed, iclass 17, count 0 2006.285.08:48:48.92#ibcon#about to write, iclass 17, count 0 2006.285.08:48:48.92#ibcon#wrote, iclass 17, count 0 2006.285.08:48:48.92#ibcon#about to read 3, iclass 17, count 0 2006.285.08:48:48.95#ibcon#read 3, iclass 17, count 0 2006.285.08:48:48.95#ibcon#about to read 4, iclass 17, count 0 2006.285.08:48:48.95#ibcon#read 4, iclass 17, count 0 2006.285.08:48:48.96#ibcon#about to read 5, iclass 17, count 0 2006.285.08:48:48.96#ibcon#read 5, iclass 17, count 0 2006.285.08:48:48.96#ibcon#about to read 6, iclass 17, count 0 2006.285.08:48:48.96#ibcon#read 6, iclass 17, count 0 2006.285.08:48:48.96#ibcon#end of sib2, iclass 17, count 0 2006.285.08:48:48.96#ibcon#*after write, iclass 17, count 0 2006.285.08:48:48.96#ibcon#*before return 0, iclass 17, count 0 2006.285.08:48:48.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:48:48.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:48:48.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.08:48:48.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.08:48:48.96$vck44/va=7,4 2006.285.08:48:48.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.08:48:48.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.08:48:48.96#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:48.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:48:49.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:48:49.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:48:49.01#ibcon#enter wrdev, iclass 19, count 2 2006.285.08:48:49.02#ibcon#first serial, iclass 19, count 2 2006.285.08:48:49.02#ibcon#enter sib2, iclass 19, count 2 2006.285.08:48:49.02#ibcon#flushed, iclass 19, count 2 2006.285.08:48:49.02#ibcon#about to write, iclass 19, count 2 2006.285.08:48:49.02#ibcon#wrote, iclass 19, count 2 2006.285.08:48:49.02#ibcon#about to read 3, iclass 19, count 2 2006.285.08:48:49.03#ibcon#read 3, iclass 19, count 2 2006.285.08:48:49.03#ibcon#about to read 4, iclass 19, count 2 2006.285.08:48:49.03#ibcon#read 4, iclass 19, count 2 2006.285.08:48:49.03#ibcon#about to read 5, iclass 19, count 2 2006.285.08:48:49.04#ibcon#read 5, iclass 19, count 2 2006.285.08:48:49.04#ibcon#about to read 6, iclass 19, count 2 2006.285.08:48:49.04#ibcon#read 6, iclass 19, count 2 2006.285.08:48:49.04#ibcon#end of sib2, iclass 19, count 2 2006.285.08:48:49.04#ibcon#*mode == 0, iclass 19, count 2 2006.285.08:48:49.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.08:48:49.04#ibcon#[25=AT07-04\r\n] 2006.285.08:48:49.04#ibcon#*before write, iclass 19, count 2 2006.285.08:48:49.04#ibcon#enter sib2, iclass 19, count 2 2006.285.08:48:49.04#ibcon#flushed, iclass 19, count 2 2006.285.08:48:49.04#ibcon#about to write, iclass 19, count 2 2006.285.08:48:49.04#ibcon#wrote, iclass 19, count 2 2006.285.08:48:49.04#ibcon#about to read 3, iclass 19, count 2 2006.285.08:48:49.06#ibcon#read 3, iclass 19, count 2 2006.285.08:48:49.06#ibcon#about to read 4, iclass 19, count 2 2006.285.08:48:49.07#ibcon#read 4, iclass 19, count 2 2006.285.08:48:49.07#ibcon#about to read 5, iclass 19, count 2 2006.285.08:48:49.07#ibcon#read 5, iclass 19, count 2 2006.285.08:48:49.07#ibcon#about to read 6, iclass 19, count 2 2006.285.08:48:49.07#ibcon#read 6, iclass 19, count 2 2006.285.08:48:49.07#ibcon#end of sib2, iclass 19, count 2 2006.285.08:48:49.07#ibcon#*after write, iclass 19, count 2 2006.285.08:48:49.07#ibcon#*before return 0, iclass 19, count 2 2006.285.08:48:49.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:48:49.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:48:49.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.08:48:49.07#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:49.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:48:49.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:48:49.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:48:49.18#ibcon#enter wrdev, iclass 19, count 0 2006.285.08:48:49.19#ibcon#first serial, iclass 19, count 0 2006.285.08:48:49.19#ibcon#enter sib2, iclass 19, count 0 2006.285.08:48:49.19#ibcon#flushed, iclass 19, count 0 2006.285.08:48:49.19#ibcon#about to write, iclass 19, count 0 2006.285.08:48:49.19#ibcon#wrote, iclass 19, count 0 2006.285.08:48:49.19#ibcon#about to read 3, iclass 19, count 0 2006.285.08:48:49.20#ibcon#read 3, iclass 19, count 0 2006.285.08:48:49.20#ibcon#about to read 4, iclass 19, count 0 2006.285.08:48:49.20#ibcon#read 4, iclass 19, count 0 2006.285.08:48:49.21#ibcon#about to read 5, iclass 19, count 0 2006.285.08:48:49.21#ibcon#read 5, iclass 19, count 0 2006.285.08:48:49.21#ibcon#about to read 6, iclass 19, count 0 2006.285.08:48:49.21#ibcon#read 6, iclass 19, count 0 2006.285.08:48:49.21#ibcon#end of sib2, iclass 19, count 0 2006.285.08:48:49.21#ibcon#*mode == 0, iclass 19, count 0 2006.285.08:48:49.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.08:48:49.21#ibcon#[25=USB\r\n] 2006.285.08:48:49.21#ibcon#*before write, iclass 19, count 0 2006.285.08:48:49.21#ibcon#enter sib2, iclass 19, count 0 2006.285.08:48:49.21#ibcon#flushed, iclass 19, count 0 2006.285.08:48:49.21#ibcon#about to write, iclass 19, count 0 2006.285.08:48:49.21#ibcon#wrote, iclass 19, count 0 2006.285.08:48:49.21#ibcon#about to read 3, iclass 19, count 0 2006.285.08:48:49.23#ibcon#read 3, iclass 19, count 0 2006.285.08:48:49.23#ibcon#about to read 4, iclass 19, count 0 2006.285.08:48:49.23#ibcon#read 4, iclass 19, count 0 2006.285.08:48:49.23#ibcon#about to read 5, iclass 19, count 0 2006.285.08:48:49.24#ibcon#read 5, iclass 19, count 0 2006.285.08:48:49.24#ibcon#about to read 6, iclass 19, count 0 2006.285.08:48:49.24#ibcon#read 6, iclass 19, count 0 2006.285.08:48:49.24#ibcon#end of sib2, iclass 19, count 0 2006.285.08:48:49.24#ibcon#*after write, iclass 19, count 0 2006.285.08:48:49.24#ibcon#*before return 0, iclass 19, count 0 2006.285.08:48:49.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:48:49.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:48:49.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.08:48:49.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.08:48:49.24$vck44/valo=8,884.99 2006.285.08:48:49.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.08:48:49.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.08:48:49.24#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:49.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:48:49.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:48:49.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:48:49.24#ibcon#enter wrdev, iclass 21, count 0 2006.285.08:48:49.24#ibcon#first serial, iclass 21, count 0 2006.285.08:48:49.24#ibcon#enter sib2, iclass 21, count 0 2006.285.08:48:49.24#ibcon#flushed, iclass 21, count 0 2006.285.08:48:49.24#ibcon#about to write, iclass 21, count 0 2006.285.08:48:49.24#ibcon#wrote, iclass 21, count 0 2006.285.08:48:49.24#ibcon#about to read 3, iclass 21, count 0 2006.285.08:48:49.25#ibcon#read 3, iclass 21, count 0 2006.285.08:48:49.25#ibcon#about to read 4, iclass 21, count 0 2006.285.08:48:49.25#ibcon#read 4, iclass 21, count 0 2006.285.08:48:49.26#ibcon#about to read 5, iclass 21, count 0 2006.285.08:48:49.26#ibcon#read 5, iclass 21, count 0 2006.285.08:48:49.26#ibcon#about to read 6, iclass 21, count 0 2006.285.08:48:49.26#ibcon#read 6, iclass 21, count 0 2006.285.08:48:49.26#ibcon#end of sib2, iclass 21, count 0 2006.285.08:48:49.26#ibcon#*mode == 0, iclass 21, count 0 2006.285.08:48:49.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.08:48:49.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:48:49.26#ibcon#*before write, iclass 21, count 0 2006.285.08:48:49.26#ibcon#enter sib2, iclass 21, count 0 2006.285.08:48:49.26#ibcon#flushed, iclass 21, count 0 2006.285.08:48:49.26#ibcon#about to write, iclass 21, count 0 2006.285.08:48:49.26#ibcon#wrote, iclass 21, count 0 2006.285.08:48:49.26#ibcon#about to read 3, iclass 21, count 0 2006.285.08:48:49.29#ibcon#read 3, iclass 21, count 0 2006.285.08:48:49.29#ibcon#about to read 4, iclass 21, count 0 2006.285.08:48:49.29#ibcon#read 4, iclass 21, count 0 2006.285.08:48:49.29#ibcon#about to read 5, iclass 21, count 0 2006.285.08:48:49.30#ibcon#read 5, iclass 21, count 0 2006.285.08:48:49.30#ibcon#about to read 6, iclass 21, count 0 2006.285.08:48:49.30#ibcon#read 6, iclass 21, count 0 2006.285.08:48:49.30#ibcon#end of sib2, iclass 21, count 0 2006.285.08:48:49.30#ibcon#*after write, iclass 21, count 0 2006.285.08:48:49.30#ibcon#*before return 0, iclass 21, count 0 2006.285.08:48:49.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:48:49.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:48:49.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.08:48:49.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.08:48:49.30$vck44/va=8,3 2006.285.08:48:49.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.08:48:49.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.08:48:49.30#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:49.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:48:49.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:48:49.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:48:49.35#ibcon#enter wrdev, iclass 23, count 2 2006.285.08:48:49.35#ibcon#first serial, iclass 23, count 2 2006.285.08:48:49.36#ibcon#enter sib2, iclass 23, count 2 2006.285.08:48:49.36#ibcon#flushed, iclass 23, count 2 2006.285.08:48:49.36#ibcon#about to write, iclass 23, count 2 2006.285.08:48:49.36#ibcon#wrote, iclass 23, count 2 2006.285.08:48:49.36#ibcon#about to read 3, iclass 23, count 2 2006.285.08:48:49.37#ibcon#read 3, iclass 23, count 2 2006.285.08:48:49.37#ibcon#about to read 4, iclass 23, count 2 2006.285.08:48:49.37#ibcon#read 4, iclass 23, count 2 2006.285.08:48:49.37#ibcon#about to read 5, iclass 23, count 2 2006.285.08:48:49.38#ibcon#read 5, iclass 23, count 2 2006.285.08:48:49.38#ibcon#about to read 6, iclass 23, count 2 2006.285.08:48:49.38#ibcon#read 6, iclass 23, count 2 2006.285.08:48:49.38#ibcon#end of sib2, iclass 23, count 2 2006.285.08:48:49.38#ibcon#*mode == 0, iclass 23, count 2 2006.285.08:48:49.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.08:48:49.38#ibcon#[25=AT08-03\r\n] 2006.285.08:48:49.38#ibcon#*before write, iclass 23, count 2 2006.285.08:48:49.38#ibcon#enter sib2, iclass 23, count 2 2006.285.08:48:49.38#ibcon#flushed, iclass 23, count 2 2006.285.08:48:49.38#ibcon#about to write, iclass 23, count 2 2006.285.08:48:49.38#ibcon#wrote, iclass 23, count 2 2006.285.08:48:49.38#ibcon#about to read 3, iclass 23, count 2 2006.285.08:48:49.40#ibcon#read 3, iclass 23, count 2 2006.285.08:48:49.40#ibcon#about to read 4, iclass 23, count 2 2006.285.08:48:49.40#ibcon#read 4, iclass 23, count 2 2006.285.08:48:49.40#ibcon#about to read 5, iclass 23, count 2 2006.285.08:48:49.41#ibcon#read 5, iclass 23, count 2 2006.285.08:48:49.41#ibcon#about to read 6, iclass 23, count 2 2006.285.08:48:49.41#ibcon#read 6, iclass 23, count 2 2006.285.08:48:49.41#ibcon#end of sib2, iclass 23, count 2 2006.285.08:48:49.41#ibcon#*after write, iclass 23, count 2 2006.285.08:48:49.41#ibcon#*before return 0, iclass 23, count 2 2006.285.08:48:49.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:48:49.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.08:48:49.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.08:48:49.41#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:49.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:48:49.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:48:49.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:48:49.53#ibcon#enter wrdev, iclass 23, count 0 2006.285.08:48:49.53#ibcon#first serial, iclass 23, count 0 2006.285.08:48:49.53#ibcon#enter sib2, iclass 23, count 0 2006.285.08:48:49.53#ibcon#flushed, iclass 23, count 0 2006.285.08:48:49.53#ibcon#about to write, iclass 23, count 0 2006.285.08:48:49.53#ibcon#wrote, iclass 23, count 0 2006.285.08:48:49.53#ibcon#about to read 3, iclass 23, count 0 2006.285.08:48:49.54#ibcon#read 3, iclass 23, count 0 2006.285.08:48:49.54#ibcon#about to read 4, iclass 23, count 0 2006.285.08:48:49.54#ibcon#read 4, iclass 23, count 0 2006.285.08:48:49.54#ibcon#about to read 5, iclass 23, count 0 2006.285.08:48:49.55#ibcon#read 5, iclass 23, count 0 2006.285.08:48:49.55#ibcon#about to read 6, iclass 23, count 0 2006.285.08:48:49.55#ibcon#read 6, iclass 23, count 0 2006.285.08:48:49.55#ibcon#end of sib2, iclass 23, count 0 2006.285.08:48:49.55#ibcon#*mode == 0, iclass 23, count 0 2006.285.08:48:49.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.08:48:49.55#ibcon#[25=USB\r\n] 2006.285.08:48:49.55#ibcon#*before write, iclass 23, count 0 2006.285.08:48:49.55#ibcon#enter sib2, iclass 23, count 0 2006.285.08:48:49.55#ibcon#flushed, iclass 23, count 0 2006.285.08:48:49.55#ibcon#about to write, iclass 23, count 0 2006.285.08:48:49.55#ibcon#wrote, iclass 23, count 0 2006.285.08:48:49.55#ibcon#about to read 3, iclass 23, count 0 2006.285.08:48:49.57#ibcon#read 3, iclass 23, count 0 2006.285.08:48:49.57#ibcon#about to read 4, iclass 23, count 0 2006.285.08:48:49.57#ibcon#read 4, iclass 23, count 0 2006.285.08:48:49.57#ibcon#about to read 5, iclass 23, count 0 2006.285.08:48:49.58#ibcon#read 5, iclass 23, count 0 2006.285.08:48:49.58#ibcon#about to read 6, iclass 23, count 0 2006.285.08:48:49.58#ibcon#read 6, iclass 23, count 0 2006.285.08:48:49.58#ibcon#end of sib2, iclass 23, count 0 2006.285.08:48:49.58#ibcon#*after write, iclass 23, count 0 2006.285.08:48:49.58#ibcon#*before return 0, iclass 23, count 0 2006.285.08:48:49.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:48:49.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.08:48:49.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.08:48:49.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.08:48:49.58$vck44/vblo=1,629.99 2006.285.08:48:49.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.08:48:49.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.08:48:49.58#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:49.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:48:49.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:48:49.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:48:49.58#ibcon#enter wrdev, iclass 25, count 0 2006.285.08:48:49.58#ibcon#first serial, iclass 25, count 0 2006.285.08:48:49.58#ibcon#enter sib2, iclass 25, count 0 2006.285.08:48:49.58#ibcon#flushed, iclass 25, count 0 2006.285.08:48:49.58#ibcon#about to write, iclass 25, count 0 2006.285.08:48:49.58#ibcon#wrote, iclass 25, count 0 2006.285.08:48:49.58#ibcon#about to read 3, iclass 25, count 0 2006.285.08:48:49.59#ibcon#read 3, iclass 25, count 0 2006.285.08:48:49.59#ibcon#about to read 4, iclass 25, count 0 2006.285.08:48:49.59#ibcon#read 4, iclass 25, count 0 2006.285.08:48:49.60#ibcon#about to read 5, iclass 25, count 0 2006.285.08:48:49.60#ibcon#read 5, iclass 25, count 0 2006.285.08:48:49.60#ibcon#about to read 6, iclass 25, count 0 2006.285.08:48:49.60#ibcon#read 6, iclass 25, count 0 2006.285.08:48:49.60#ibcon#end of sib2, iclass 25, count 0 2006.285.08:48:49.60#ibcon#*mode == 0, iclass 25, count 0 2006.285.08:48:49.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.08:48:49.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:48:49.60#ibcon#*before write, iclass 25, count 0 2006.285.08:48:49.60#ibcon#enter sib2, iclass 25, count 0 2006.285.08:48:49.60#ibcon#flushed, iclass 25, count 0 2006.285.08:48:49.60#ibcon#about to write, iclass 25, count 0 2006.285.08:48:49.60#ibcon#wrote, iclass 25, count 0 2006.285.08:48:49.60#ibcon#about to read 3, iclass 25, count 0 2006.285.08:48:49.63#ibcon#read 3, iclass 25, count 0 2006.285.08:48:49.63#ibcon#about to read 4, iclass 25, count 0 2006.285.08:48:49.63#ibcon#read 4, iclass 25, count 0 2006.285.08:48:49.63#ibcon#about to read 5, iclass 25, count 0 2006.285.08:48:49.64#ibcon#read 5, iclass 25, count 0 2006.285.08:48:49.64#ibcon#about to read 6, iclass 25, count 0 2006.285.08:48:49.64#ibcon#read 6, iclass 25, count 0 2006.285.08:48:49.64#ibcon#end of sib2, iclass 25, count 0 2006.285.08:48:49.64#ibcon#*after write, iclass 25, count 0 2006.285.08:48:49.64#ibcon#*before return 0, iclass 25, count 0 2006.285.08:48:49.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:48:49.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.08:48:49.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.08:48:49.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.08:48:49.64$vck44/vb=1,4 2006.285.08:48:49.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.08:48:49.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.08:48:49.64#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:49.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:48:49.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:48:49.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:48:49.64#ibcon#enter wrdev, iclass 27, count 2 2006.285.08:48:49.64#ibcon#first serial, iclass 27, count 2 2006.285.08:48:49.64#ibcon#enter sib2, iclass 27, count 2 2006.285.08:48:49.64#ibcon#flushed, iclass 27, count 2 2006.285.08:48:49.64#ibcon#about to write, iclass 27, count 2 2006.285.08:48:49.64#ibcon#wrote, iclass 27, count 2 2006.285.08:48:49.64#ibcon#about to read 3, iclass 27, count 2 2006.285.08:48:49.65#ibcon#read 3, iclass 27, count 2 2006.285.08:48:49.65#ibcon#about to read 4, iclass 27, count 2 2006.285.08:48:49.65#ibcon#read 4, iclass 27, count 2 2006.285.08:48:49.66#ibcon#about to read 5, iclass 27, count 2 2006.285.08:48:49.66#ibcon#read 5, iclass 27, count 2 2006.285.08:48:49.66#ibcon#about to read 6, iclass 27, count 2 2006.285.08:48:49.66#ibcon#read 6, iclass 27, count 2 2006.285.08:48:49.66#ibcon#end of sib2, iclass 27, count 2 2006.285.08:48:49.66#ibcon#*mode == 0, iclass 27, count 2 2006.285.08:48:49.66#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.08:48:49.66#ibcon#[27=AT01-04\r\n] 2006.285.08:48:49.66#ibcon#*before write, iclass 27, count 2 2006.285.08:48:49.66#ibcon#enter sib2, iclass 27, count 2 2006.285.08:48:49.66#ibcon#flushed, iclass 27, count 2 2006.285.08:48:49.66#ibcon#about to write, iclass 27, count 2 2006.285.08:48:49.66#ibcon#wrote, iclass 27, count 2 2006.285.08:48:49.66#ibcon#about to read 3, iclass 27, count 2 2006.285.08:48:49.68#ibcon#read 3, iclass 27, count 2 2006.285.08:48:49.68#ibcon#about to read 4, iclass 27, count 2 2006.285.08:48:49.68#ibcon#read 4, iclass 27, count 2 2006.285.08:48:49.68#ibcon#about to read 5, iclass 27, count 2 2006.285.08:48:49.69#ibcon#read 5, iclass 27, count 2 2006.285.08:48:49.69#ibcon#about to read 6, iclass 27, count 2 2006.285.08:48:49.69#ibcon#read 6, iclass 27, count 2 2006.285.08:48:49.69#ibcon#end of sib2, iclass 27, count 2 2006.285.08:48:49.69#ibcon#*after write, iclass 27, count 2 2006.285.08:48:49.69#ibcon#*before return 0, iclass 27, count 2 2006.285.08:48:49.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:48:49.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.08:48:49.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.08:48:49.69#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:49.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:48:49.80#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:48:49.80#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:48:49.80#ibcon#enter wrdev, iclass 27, count 0 2006.285.08:48:49.80#ibcon#first serial, iclass 27, count 0 2006.285.08:48:49.81#ibcon#enter sib2, iclass 27, count 0 2006.285.08:48:49.81#ibcon#flushed, iclass 27, count 0 2006.285.08:48:49.81#ibcon#about to write, iclass 27, count 0 2006.285.08:48:49.81#ibcon#wrote, iclass 27, count 0 2006.285.08:48:49.81#ibcon#about to read 3, iclass 27, count 0 2006.285.08:48:49.82#ibcon#read 3, iclass 27, count 0 2006.285.08:48:49.82#ibcon#about to read 4, iclass 27, count 0 2006.285.08:48:49.82#ibcon#read 4, iclass 27, count 0 2006.285.08:48:49.82#ibcon#about to read 5, iclass 27, count 0 2006.285.08:48:49.83#ibcon#read 5, iclass 27, count 0 2006.285.08:48:49.83#ibcon#about to read 6, iclass 27, count 0 2006.285.08:48:49.83#ibcon#read 6, iclass 27, count 0 2006.285.08:48:49.83#ibcon#end of sib2, iclass 27, count 0 2006.285.08:48:49.83#ibcon#*mode == 0, iclass 27, count 0 2006.285.08:48:49.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.08:48:49.83#ibcon#[27=USB\r\n] 2006.285.08:48:49.83#ibcon#*before write, iclass 27, count 0 2006.285.08:48:49.83#ibcon#enter sib2, iclass 27, count 0 2006.285.08:48:49.83#ibcon#flushed, iclass 27, count 0 2006.285.08:48:49.83#ibcon#about to write, iclass 27, count 0 2006.285.08:48:49.83#ibcon#wrote, iclass 27, count 0 2006.285.08:48:49.83#ibcon#about to read 3, iclass 27, count 0 2006.285.08:48:49.85#ibcon#read 3, iclass 27, count 0 2006.285.08:48:49.85#ibcon#about to read 4, iclass 27, count 0 2006.285.08:48:49.85#ibcon#read 4, iclass 27, count 0 2006.285.08:48:49.85#ibcon#about to read 5, iclass 27, count 0 2006.285.08:48:49.86#ibcon#read 5, iclass 27, count 0 2006.285.08:48:49.86#ibcon#about to read 6, iclass 27, count 0 2006.285.08:48:49.86#ibcon#read 6, iclass 27, count 0 2006.285.08:48:49.86#ibcon#end of sib2, iclass 27, count 0 2006.285.08:48:49.86#ibcon#*after write, iclass 27, count 0 2006.285.08:48:49.86#ibcon#*before return 0, iclass 27, count 0 2006.285.08:48:49.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:48:49.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.08:48:49.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.08:48:49.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.08:48:49.86$vck44/vblo=2,634.99 2006.285.08:48:49.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.08:48:49.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.08:48:49.86#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:49.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:48:49.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:48:49.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:48:49.86#ibcon#enter wrdev, iclass 29, count 0 2006.285.08:48:49.86#ibcon#first serial, iclass 29, count 0 2006.285.08:48:49.86#ibcon#enter sib2, iclass 29, count 0 2006.285.08:48:49.86#ibcon#flushed, iclass 29, count 0 2006.285.08:48:49.86#ibcon#about to write, iclass 29, count 0 2006.285.08:48:49.86#ibcon#wrote, iclass 29, count 0 2006.285.08:48:49.86#ibcon#about to read 3, iclass 29, count 0 2006.285.08:48:49.87#ibcon#read 3, iclass 29, count 0 2006.285.08:48:49.87#ibcon#about to read 4, iclass 29, count 0 2006.285.08:48:49.87#ibcon#read 4, iclass 29, count 0 2006.285.08:48:49.88#ibcon#about to read 5, iclass 29, count 0 2006.285.08:48:49.88#ibcon#read 5, iclass 29, count 0 2006.285.08:48:49.88#ibcon#about to read 6, iclass 29, count 0 2006.285.08:48:49.88#ibcon#read 6, iclass 29, count 0 2006.285.08:48:49.88#ibcon#end of sib2, iclass 29, count 0 2006.285.08:48:49.88#ibcon#*mode == 0, iclass 29, count 0 2006.285.08:48:49.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.08:48:49.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:48:49.88#ibcon#*before write, iclass 29, count 0 2006.285.08:48:49.88#ibcon#enter sib2, iclass 29, count 0 2006.285.08:48:49.88#ibcon#flushed, iclass 29, count 0 2006.285.08:48:49.88#ibcon#about to write, iclass 29, count 0 2006.285.08:48:49.88#ibcon#wrote, iclass 29, count 0 2006.285.08:48:49.88#ibcon#about to read 3, iclass 29, count 0 2006.285.08:48:49.91#ibcon#read 3, iclass 29, count 0 2006.285.08:48:49.91#ibcon#about to read 4, iclass 29, count 0 2006.285.08:48:49.91#ibcon#read 4, iclass 29, count 0 2006.285.08:48:49.91#ibcon#about to read 5, iclass 29, count 0 2006.285.08:48:49.92#ibcon#read 5, iclass 29, count 0 2006.285.08:48:49.92#ibcon#about to read 6, iclass 29, count 0 2006.285.08:48:49.92#ibcon#read 6, iclass 29, count 0 2006.285.08:48:49.92#ibcon#end of sib2, iclass 29, count 0 2006.285.08:48:49.92#ibcon#*after write, iclass 29, count 0 2006.285.08:48:49.92#ibcon#*before return 0, iclass 29, count 0 2006.285.08:48:49.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:48:49.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.08:48:49.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.08:48:49.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.08:48:49.92$vck44/vb=2,5 2006.285.08:48:49.92#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.08:48:49.92#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.08:48:49.92#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:49.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:48:49.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:48:49.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:48:49.97#ibcon#enter wrdev, iclass 31, count 2 2006.285.08:48:49.98#ibcon#first serial, iclass 31, count 2 2006.285.08:48:49.98#ibcon#enter sib2, iclass 31, count 2 2006.285.08:48:49.98#ibcon#flushed, iclass 31, count 2 2006.285.08:48:49.98#ibcon#about to write, iclass 31, count 2 2006.285.08:48:49.98#ibcon#wrote, iclass 31, count 2 2006.285.08:48:49.98#ibcon#about to read 3, iclass 31, count 2 2006.285.08:48:49.99#ibcon#read 3, iclass 31, count 2 2006.285.08:48:49.99#ibcon#about to read 4, iclass 31, count 2 2006.285.08:48:49.99#ibcon#read 4, iclass 31, count 2 2006.285.08:48:49.99#ibcon#about to read 5, iclass 31, count 2 2006.285.08:48:50.00#ibcon#read 5, iclass 31, count 2 2006.285.08:48:50.00#ibcon#about to read 6, iclass 31, count 2 2006.285.08:48:50.00#ibcon#read 6, iclass 31, count 2 2006.285.08:48:50.00#ibcon#end of sib2, iclass 31, count 2 2006.285.08:48:50.00#ibcon#*mode == 0, iclass 31, count 2 2006.285.08:48:50.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.08:48:50.00#ibcon#[27=AT02-05\r\n] 2006.285.08:48:50.00#ibcon#*before write, iclass 31, count 2 2006.285.08:48:50.00#ibcon#enter sib2, iclass 31, count 2 2006.285.08:48:50.00#ibcon#flushed, iclass 31, count 2 2006.285.08:48:50.00#ibcon#about to write, iclass 31, count 2 2006.285.08:48:50.00#ibcon#wrote, iclass 31, count 2 2006.285.08:48:50.00#ibcon#about to read 3, iclass 31, count 2 2006.285.08:48:50.02#ibcon#read 3, iclass 31, count 2 2006.285.08:48:50.02#ibcon#about to read 4, iclass 31, count 2 2006.285.08:48:50.02#ibcon#read 4, iclass 31, count 2 2006.285.08:48:50.03#ibcon#about to read 5, iclass 31, count 2 2006.285.08:48:50.03#ibcon#read 5, iclass 31, count 2 2006.285.08:48:50.03#ibcon#about to read 6, iclass 31, count 2 2006.285.08:48:50.03#ibcon#read 6, iclass 31, count 2 2006.285.08:48:50.03#ibcon#end of sib2, iclass 31, count 2 2006.285.08:48:50.03#ibcon#*after write, iclass 31, count 2 2006.285.08:48:50.03#ibcon#*before return 0, iclass 31, count 2 2006.285.08:48:50.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:48:50.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.08:48:50.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.08:48:50.03#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:50.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:48:50.14#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:48:50.14#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:48:50.14#ibcon#enter wrdev, iclass 31, count 0 2006.285.08:48:50.14#ibcon#first serial, iclass 31, count 0 2006.285.08:48:50.15#ibcon#enter sib2, iclass 31, count 0 2006.285.08:48:50.15#ibcon#flushed, iclass 31, count 0 2006.285.08:48:50.15#ibcon#about to write, iclass 31, count 0 2006.285.08:48:50.15#ibcon#wrote, iclass 31, count 0 2006.285.08:48:50.15#ibcon#about to read 3, iclass 31, count 0 2006.285.08:48:50.16#ibcon#read 3, iclass 31, count 0 2006.285.08:48:50.16#ibcon#about to read 4, iclass 31, count 0 2006.285.08:48:50.16#ibcon#read 4, iclass 31, count 0 2006.285.08:48:50.16#ibcon#about to read 5, iclass 31, count 0 2006.285.08:48:50.17#ibcon#read 5, iclass 31, count 0 2006.285.08:48:50.17#ibcon#about to read 6, iclass 31, count 0 2006.285.08:48:50.17#ibcon#read 6, iclass 31, count 0 2006.285.08:48:50.17#ibcon#end of sib2, iclass 31, count 0 2006.285.08:48:50.17#ibcon#*mode == 0, iclass 31, count 0 2006.285.08:48:50.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.08:48:50.17#ibcon#[27=USB\r\n] 2006.285.08:48:50.17#ibcon#*before write, iclass 31, count 0 2006.285.08:48:50.17#ibcon#enter sib2, iclass 31, count 0 2006.285.08:48:50.17#ibcon#flushed, iclass 31, count 0 2006.285.08:48:50.17#ibcon#about to write, iclass 31, count 0 2006.285.08:48:50.17#ibcon#wrote, iclass 31, count 0 2006.285.08:48:50.17#ibcon#about to read 3, iclass 31, count 0 2006.285.08:48:50.19#ibcon#read 3, iclass 31, count 0 2006.285.08:48:50.19#ibcon#about to read 4, iclass 31, count 0 2006.285.08:48:50.19#ibcon#read 4, iclass 31, count 0 2006.285.08:48:50.20#ibcon#about to read 5, iclass 31, count 0 2006.285.08:48:50.20#ibcon#read 5, iclass 31, count 0 2006.285.08:48:50.20#ibcon#about to read 6, iclass 31, count 0 2006.285.08:48:50.20#ibcon#read 6, iclass 31, count 0 2006.285.08:48:50.20#ibcon#end of sib2, iclass 31, count 0 2006.285.08:48:50.20#ibcon#*after write, iclass 31, count 0 2006.285.08:48:50.20#ibcon#*before return 0, iclass 31, count 0 2006.285.08:48:50.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:48:50.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.08:48:50.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.08:48:50.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.08:48:50.20$vck44/vblo=3,649.99 2006.285.08:48:50.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.08:48:50.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.08:48:50.20#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:50.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:48:50.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:48:50.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:48:50.20#ibcon#enter wrdev, iclass 33, count 0 2006.285.08:48:50.20#ibcon#first serial, iclass 33, count 0 2006.285.08:48:50.20#ibcon#enter sib2, iclass 33, count 0 2006.285.08:48:50.20#ibcon#flushed, iclass 33, count 0 2006.285.08:48:50.20#ibcon#about to write, iclass 33, count 0 2006.285.08:48:50.20#ibcon#wrote, iclass 33, count 0 2006.285.08:48:50.20#ibcon#about to read 3, iclass 33, count 0 2006.285.08:48:50.21#ibcon#read 3, iclass 33, count 0 2006.285.08:48:50.21#ibcon#about to read 4, iclass 33, count 0 2006.285.08:48:50.21#ibcon#read 4, iclass 33, count 0 2006.285.08:48:50.22#ibcon#about to read 5, iclass 33, count 0 2006.285.08:48:50.22#ibcon#read 5, iclass 33, count 0 2006.285.08:48:50.22#ibcon#about to read 6, iclass 33, count 0 2006.285.08:48:50.22#ibcon#read 6, iclass 33, count 0 2006.285.08:48:50.22#ibcon#end of sib2, iclass 33, count 0 2006.285.08:48:50.22#ibcon#*mode == 0, iclass 33, count 0 2006.285.08:48:50.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.08:48:50.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:48:50.22#ibcon#*before write, iclass 33, count 0 2006.285.08:48:50.22#ibcon#enter sib2, iclass 33, count 0 2006.285.08:48:50.22#ibcon#flushed, iclass 33, count 0 2006.285.08:48:50.22#ibcon#about to write, iclass 33, count 0 2006.285.08:48:50.22#ibcon#wrote, iclass 33, count 0 2006.285.08:48:50.22#ibcon#about to read 3, iclass 33, count 0 2006.285.08:48:50.25#ibcon#read 3, iclass 33, count 0 2006.285.08:48:50.25#ibcon#about to read 4, iclass 33, count 0 2006.285.08:48:50.25#ibcon#read 4, iclass 33, count 0 2006.285.08:48:50.25#ibcon#about to read 5, iclass 33, count 0 2006.285.08:48:50.26#ibcon#read 5, iclass 33, count 0 2006.285.08:48:50.26#ibcon#about to read 6, iclass 33, count 0 2006.285.08:48:50.26#ibcon#read 6, iclass 33, count 0 2006.285.08:48:50.26#ibcon#end of sib2, iclass 33, count 0 2006.285.08:48:50.26#ibcon#*after write, iclass 33, count 0 2006.285.08:48:50.26#ibcon#*before return 0, iclass 33, count 0 2006.285.08:48:50.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:48:50.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.08:48:50.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.08:48:50.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.08:48:50.26$vck44/vb=3,4 2006.285.08:48:50.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.08:48:50.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.08:48:50.26#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:50.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:48:50.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:48:50.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:48:50.31#ibcon#enter wrdev, iclass 35, count 2 2006.285.08:48:50.31#ibcon#first serial, iclass 35, count 2 2006.285.08:48:50.32#ibcon#enter sib2, iclass 35, count 2 2006.285.08:48:50.32#ibcon#flushed, iclass 35, count 2 2006.285.08:48:50.32#ibcon#about to write, iclass 35, count 2 2006.285.08:48:50.32#ibcon#wrote, iclass 35, count 2 2006.285.08:48:50.32#ibcon#about to read 3, iclass 35, count 2 2006.285.08:48:50.33#ibcon#read 3, iclass 35, count 2 2006.285.08:48:50.33#ibcon#about to read 4, iclass 35, count 2 2006.285.08:48:50.33#ibcon#read 4, iclass 35, count 2 2006.285.08:48:50.33#ibcon#about to read 5, iclass 35, count 2 2006.285.08:48:50.34#ibcon#read 5, iclass 35, count 2 2006.285.08:48:50.34#ibcon#about to read 6, iclass 35, count 2 2006.285.08:48:50.34#ibcon#read 6, iclass 35, count 2 2006.285.08:48:50.34#ibcon#end of sib2, iclass 35, count 2 2006.285.08:48:50.34#ibcon#*mode == 0, iclass 35, count 2 2006.285.08:48:50.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.08:48:50.34#ibcon#[27=AT03-04\r\n] 2006.285.08:48:50.34#ibcon#*before write, iclass 35, count 2 2006.285.08:48:50.34#ibcon#enter sib2, iclass 35, count 2 2006.285.08:48:50.34#ibcon#flushed, iclass 35, count 2 2006.285.08:48:50.34#ibcon#about to write, iclass 35, count 2 2006.285.08:48:50.34#ibcon#wrote, iclass 35, count 2 2006.285.08:48:50.34#ibcon#about to read 3, iclass 35, count 2 2006.285.08:48:50.36#ibcon#read 3, iclass 35, count 2 2006.285.08:48:50.36#ibcon#about to read 4, iclass 35, count 2 2006.285.08:48:50.36#ibcon#read 4, iclass 35, count 2 2006.285.08:48:50.36#ibcon#about to read 5, iclass 35, count 2 2006.285.08:48:50.37#ibcon#read 5, iclass 35, count 2 2006.285.08:48:50.37#ibcon#about to read 6, iclass 35, count 2 2006.285.08:48:50.37#ibcon#read 6, iclass 35, count 2 2006.285.08:48:50.37#ibcon#end of sib2, iclass 35, count 2 2006.285.08:48:50.37#ibcon#*after write, iclass 35, count 2 2006.285.08:48:50.37#ibcon#*before return 0, iclass 35, count 2 2006.285.08:48:50.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:48:50.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.08:48:50.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.08:48:50.37#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:50.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:48:50.48#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:48:50.48#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:48:50.48#ibcon#enter wrdev, iclass 35, count 0 2006.285.08:48:50.49#ibcon#first serial, iclass 35, count 0 2006.285.08:48:50.49#ibcon#enter sib2, iclass 35, count 0 2006.285.08:48:50.49#ibcon#flushed, iclass 35, count 0 2006.285.08:48:50.49#ibcon#about to write, iclass 35, count 0 2006.285.08:48:50.49#ibcon#wrote, iclass 35, count 0 2006.285.08:48:50.49#ibcon#about to read 3, iclass 35, count 0 2006.285.08:48:50.50#ibcon#read 3, iclass 35, count 0 2006.285.08:48:50.50#ibcon#about to read 4, iclass 35, count 0 2006.285.08:48:50.51#ibcon#read 4, iclass 35, count 0 2006.285.08:48:50.51#ibcon#about to read 5, iclass 35, count 0 2006.285.08:48:50.51#ibcon#read 5, iclass 35, count 0 2006.285.08:48:50.51#ibcon#about to read 6, iclass 35, count 0 2006.285.08:48:50.51#ibcon#read 6, iclass 35, count 0 2006.285.08:48:50.51#ibcon#end of sib2, iclass 35, count 0 2006.285.08:48:50.51#ibcon#*mode == 0, iclass 35, count 0 2006.285.08:48:50.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.08:48:50.51#ibcon#[27=USB\r\n] 2006.285.08:48:50.51#ibcon#*before write, iclass 35, count 0 2006.285.08:48:50.51#ibcon#enter sib2, iclass 35, count 0 2006.285.08:48:50.51#ibcon#flushed, iclass 35, count 0 2006.285.08:48:50.51#ibcon#about to write, iclass 35, count 0 2006.285.08:48:50.51#ibcon#wrote, iclass 35, count 0 2006.285.08:48:50.51#ibcon#about to read 3, iclass 35, count 0 2006.285.08:48:50.53#ibcon#read 3, iclass 35, count 0 2006.285.08:48:50.53#ibcon#about to read 4, iclass 35, count 0 2006.285.08:48:50.54#ibcon#read 4, iclass 35, count 0 2006.285.08:48:50.54#ibcon#about to read 5, iclass 35, count 0 2006.285.08:48:50.54#ibcon#read 5, iclass 35, count 0 2006.285.08:48:50.54#ibcon#about to read 6, iclass 35, count 0 2006.285.08:48:50.54#ibcon#read 6, iclass 35, count 0 2006.285.08:48:50.54#ibcon#end of sib2, iclass 35, count 0 2006.285.08:48:50.54#ibcon#*after write, iclass 35, count 0 2006.285.08:48:50.54#ibcon#*before return 0, iclass 35, count 0 2006.285.08:48:50.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:48:50.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.08:48:50.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.08:48:50.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.08:48:50.54$vck44/vblo=4,679.99 2006.285.08:48:50.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.08:48:50.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.08:48:50.54#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:50.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:48:50.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:48:50.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:48:50.54#ibcon#enter wrdev, iclass 37, count 0 2006.285.08:48:50.54#ibcon#first serial, iclass 37, count 0 2006.285.08:48:50.54#ibcon#enter sib2, iclass 37, count 0 2006.285.08:48:50.54#ibcon#flushed, iclass 37, count 0 2006.285.08:48:50.54#ibcon#about to write, iclass 37, count 0 2006.285.08:48:50.54#ibcon#wrote, iclass 37, count 0 2006.285.08:48:50.54#ibcon#about to read 3, iclass 37, count 0 2006.285.08:48:50.55#ibcon#read 3, iclass 37, count 0 2006.285.08:48:50.55#ibcon#about to read 4, iclass 37, count 0 2006.285.08:48:50.56#ibcon#read 4, iclass 37, count 0 2006.285.08:48:50.56#ibcon#about to read 5, iclass 37, count 0 2006.285.08:48:50.56#ibcon#read 5, iclass 37, count 0 2006.285.08:48:50.56#ibcon#about to read 6, iclass 37, count 0 2006.285.08:48:50.56#ibcon#read 6, iclass 37, count 0 2006.285.08:48:50.56#ibcon#end of sib2, iclass 37, count 0 2006.285.08:48:50.56#ibcon#*mode == 0, iclass 37, count 0 2006.285.08:48:50.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.08:48:50.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:48:50.56#ibcon#*before write, iclass 37, count 0 2006.285.08:48:50.56#ibcon#enter sib2, iclass 37, count 0 2006.285.08:48:50.56#ibcon#flushed, iclass 37, count 0 2006.285.08:48:50.56#ibcon#about to write, iclass 37, count 0 2006.285.08:48:50.56#ibcon#wrote, iclass 37, count 0 2006.285.08:48:50.56#ibcon#about to read 3, iclass 37, count 0 2006.285.08:48:50.59#ibcon#read 3, iclass 37, count 0 2006.285.08:48:50.59#ibcon#about to read 4, iclass 37, count 0 2006.285.08:48:50.59#ibcon#read 4, iclass 37, count 0 2006.285.08:48:50.59#ibcon#about to read 5, iclass 37, count 0 2006.285.08:48:50.60#ibcon#read 5, iclass 37, count 0 2006.285.08:48:50.60#ibcon#about to read 6, iclass 37, count 0 2006.285.08:48:50.60#ibcon#read 6, iclass 37, count 0 2006.285.08:48:50.60#ibcon#end of sib2, iclass 37, count 0 2006.285.08:48:50.60#ibcon#*after write, iclass 37, count 0 2006.285.08:48:50.60#ibcon#*before return 0, iclass 37, count 0 2006.285.08:48:50.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:48:50.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.08:48:50.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.08:48:50.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.08:48:50.60$vck44/vb=4,5 2006.285.08:48:50.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.08:48:50.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.08:48:50.60#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:50.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:48:50.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:48:50.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:48:50.65#ibcon#enter wrdev, iclass 39, count 2 2006.285.08:48:50.65#ibcon#first serial, iclass 39, count 2 2006.285.08:48:50.66#ibcon#enter sib2, iclass 39, count 2 2006.285.08:48:50.66#ibcon#flushed, iclass 39, count 2 2006.285.08:48:50.66#ibcon#about to write, iclass 39, count 2 2006.285.08:48:50.66#ibcon#wrote, iclass 39, count 2 2006.285.08:48:50.66#ibcon#about to read 3, iclass 39, count 2 2006.285.08:48:50.67#ibcon#read 3, iclass 39, count 2 2006.285.08:48:50.67#ibcon#about to read 4, iclass 39, count 2 2006.285.08:48:50.67#ibcon#read 4, iclass 39, count 2 2006.285.08:48:50.67#ibcon#about to read 5, iclass 39, count 2 2006.285.08:48:50.67#ibcon#read 5, iclass 39, count 2 2006.285.08:48:50.68#ibcon#about to read 6, iclass 39, count 2 2006.285.08:48:50.68#ibcon#read 6, iclass 39, count 2 2006.285.08:48:50.68#ibcon#end of sib2, iclass 39, count 2 2006.285.08:48:50.68#ibcon#*mode == 0, iclass 39, count 2 2006.285.08:48:50.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.08:48:50.68#ibcon#[27=AT04-05\r\n] 2006.285.08:48:50.68#ibcon#*before write, iclass 39, count 2 2006.285.08:48:50.68#ibcon#enter sib2, iclass 39, count 2 2006.285.08:48:50.68#ibcon#flushed, iclass 39, count 2 2006.285.08:48:50.68#ibcon#about to write, iclass 39, count 2 2006.285.08:48:50.68#ibcon#wrote, iclass 39, count 2 2006.285.08:48:50.68#ibcon#about to read 3, iclass 39, count 2 2006.285.08:48:50.70#ibcon#read 3, iclass 39, count 2 2006.285.08:48:50.70#ibcon#about to read 4, iclass 39, count 2 2006.285.08:48:50.70#ibcon#read 4, iclass 39, count 2 2006.285.08:48:50.70#ibcon#about to read 5, iclass 39, count 2 2006.285.08:48:50.71#ibcon#read 5, iclass 39, count 2 2006.285.08:48:50.71#ibcon#about to read 6, iclass 39, count 2 2006.285.08:48:50.71#ibcon#read 6, iclass 39, count 2 2006.285.08:48:50.71#ibcon#end of sib2, iclass 39, count 2 2006.285.08:48:50.71#ibcon#*after write, iclass 39, count 2 2006.285.08:48:50.71#ibcon#*before return 0, iclass 39, count 2 2006.285.08:48:50.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:48:50.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.08:48:50.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.08:48:50.71#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:50.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:48:50.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:48:50.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:48:50.82#ibcon#enter wrdev, iclass 39, count 0 2006.285.08:48:50.82#ibcon#first serial, iclass 39, count 0 2006.285.08:48:50.83#ibcon#enter sib2, iclass 39, count 0 2006.285.08:48:50.83#ibcon#flushed, iclass 39, count 0 2006.285.08:48:50.83#ibcon#about to write, iclass 39, count 0 2006.285.08:48:50.83#ibcon#wrote, iclass 39, count 0 2006.285.08:48:50.83#ibcon#about to read 3, iclass 39, count 0 2006.285.08:48:50.84#ibcon#read 3, iclass 39, count 0 2006.285.08:48:50.84#ibcon#about to read 4, iclass 39, count 0 2006.285.08:48:50.84#ibcon#read 4, iclass 39, count 0 2006.285.08:48:50.84#ibcon#about to read 5, iclass 39, count 0 2006.285.08:48:50.85#ibcon#read 5, iclass 39, count 0 2006.285.08:48:50.85#ibcon#about to read 6, iclass 39, count 0 2006.285.08:48:50.85#ibcon#read 6, iclass 39, count 0 2006.285.08:48:50.85#ibcon#end of sib2, iclass 39, count 0 2006.285.08:48:50.85#ibcon#*mode == 0, iclass 39, count 0 2006.285.08:48:50.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.08:48:50.85#ibcon#[27=USB\r\n] 2006.285.08:48:50.85#ibcon#*before write, iclass 39, count 0 2006.285.08:48:50.85#ibcon#enter sib2, iclass 39, count 0 2006.285.08:48:50.85#ibcon#flushed, iclass 39, count 0 2006.285.08:48:50.85#ibcon#about to write, iclass 39, count 0 2006.285.08:48:50.85#ibcon#wrote, iclass 39, count 0 2006.285.08:48:50.85#ibcon#about to read 3, iclass 39, count 0 2006.285.08:48:50.87#ibcon#read 3, iclass 39, count 0 2006.285.08:48:50.87#ibcon#about to read 4, iclass 39, count 0 2006.285.08:48:50.87#ibcon#read 4, iclass 39, count 0 2006.285.08:48:50.87#ibcon#about to read 5, iclass 39, count 0 2006.285.08:48:50.88#ibcon#read 5, iclass 39, count 0 2006.285.08:48:50.88#ibcon#about to read 6, iclass 39, count 0 2006.285.08:48:50.88#ibcon#read 6, iclass 39, count 0 2006.285.08:48:50.88#ibcon#end of sib2, iclass 39, count 0 2006.285.08:48:50.88#ibcon#*after write, iclass 39, count 0 2006.285.08:48:50.88#ibcon#*before return 0, iclass 39, count 0 2006.285.08:48:50.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:48:50.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.08:48:50.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.08:48:50.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.08:48:50.88$vck44/vblo=5,709.99 2006.285.08:48:50.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.08:48:50.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.08:48:50.88#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:50.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:48:50.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:48:50.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:48:50.88#ibcon#enter wrdev, iclass 3, count 0 2006.285.08:48:50.88#ibcon#first serial, iclass 3, count 0 2006.285.08:48:50.88#ibcon#enter sib2, iclass 3, count 0 2006.285.08:48:50.88#ibcon#flushed, iclass 3, count 0 2006.285.08:48:50.88#ibcon#about to write, iclass 3, count 0 2006.285.08:48:50.88#ibcon#wrote, iclass 3, count 0 2006.285.08:48:50.88#ibcon#about to read 3, iclass 3, count 0 2006.285.08:48:50.89#ibcon#read 3, iclass 3, count 0 2006.285.08:48:50.89#ibcon#about to read 4, iclass 3, count 0 2006.285.08:48:50.89#ibcon#read 4, iclass 3, count 0 2006.285.08:48:50.90#ibcon#about to read 5, iclass 3, count 0 2006.285.08:48:50.90#ibcon#read 5, iclass 3, count 0 2006.285.08:48:50.90#ibcon#about to read 6, iclass 3, count 0 2006.285.08:48:50.90#ibcon#read 6, iclass 3, count 0 2006.285.08:48:50.90#ibcon#end of sib2, iclass 3, count 0 2006.285.08:48:50.90#ibcon#*mode == 0, iclass 3, count 0 2006.285.08:48:50.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.08:48:50.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:48:50.90#ibcon#*before write, iclass 3, count 0 2006.285.08:48:50.90#ibcon#enter sib2, iclass 3, count 0 2006.285.08:48:50.90#ibcon#flushed, iclass 3, count 0 2006.285.08:48:50.90#ibcon#about to write, iclass 3, count 0 2006.285.08:48:50.90#ibcon#wrote, iclass 3, count 0 2006.285.08:48:50.90#ibcon#about to read 3, iclass 3, count 0 2006.285.08:48:50.93#ibcon#read 3, iclass 3, count 0 2006.285.08:48:50.93#ibcon#about to read 4, iclass 3, count 0 2006.285.08:48:50.93#ibcon#read 4, iclass 3, count 0 2006.285.08:48:50.93#ibcon#about to read 5, iclass 3, count 0 2006.285.08:48:50.94#ibcon#read 5, iclass 3, count 0 2006.285.08:48:50.94#ibcon#about to read 6, iclass 3, count 0 2006.285.08:48:50.94#ibcon#read 6, iclass 3, count 0 2006.285.08:48:50.94#ibcon#end of sib2, iclass 3, count 0 2006.285.08:48:50.94#ibcon#*after write, iclass 3, count 0 2006.285.08:48:50.94#ibcon#*before return 0, iclass 3, count 0 2006.285.08:48:50.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:48:50.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.08:48:50.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.08:48:50.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.08:48:50.94$vck44/vb=5,4 2006.285.08:48:50.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.08:48:50.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.08:48:50.94#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:50.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:48:50.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:48:50.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:48:50.99#ibcon#enter wrdev, iclass 5, count 2 2006.285.08:48:50.99#ibcon#first serial, iclass 5, count 2 2006.285.08:48:51.00#ibcon#enter sib2, iclass 5, count 2 2006.285.08:48:51.00#ibcon#flushed, iclass 5, count 2 2006.285.08:48:51.00#ibcon#about to write, iclass 5, count 2 2006.285.08:48:51.00#ibcon#wrote, iclass 5, count 2 2006.285.08:48:51.00#ibcon#about to read 3, iclass 5, count 2 2006.285.08:48:51.01#ibcon#read 3, iclass 5, count 2 2006.285.08:48:51.01#ibcon#about to read 4, iclass 5, count 2 2006.285.08:48:51.01#ibcon#read 4, iclass 5, count 2 2006.285.08:48:51.01#ibcon#about to read 5, iclass 5, count 2 2006.285.08:48:51.02#ibcon#read 5, iclass 5, count 2 2006.285.08:48:51.02#ibcon#about to read 6, iclass 5, count 2 2006.285.08:48:51.02#ibcon#read 6, iclass 5, count 2 2006.285.08:48:51.02#ibcon#end of sib2, iclass 5, count 2 2006.285.08:48:51.02#ibcon#*mode == 0, iclass 5, count 2 2006.285.08:48:51.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.08:48:51.02#ibcon#[27=AT05-04\r\n] 2006.285.08:48:51.02#ibcon#*before write, iclass 5, count 2 2006.285.08:48:51.02#ibcon#enter sib2, iclass 5, count 2 2006.285.08:48:51.02#ibcon#flushed, iclass 5, count 2 2006.285.08:48:51.02#ibcon#about to write, iclass 5, count 2 2006.285.08:48:51.02#ibcon#wrote, iclass 5, count 2 2006.285.08:48:51.02#ibcon#about to read 3, iclass 5, count 2 2006.285.08:48:51.04#ibcon#read 3, iclass 5, count 2 2006.285.08:48:51.04#ibcon#about to read 4, iclass 5, count 2 2006.285.08:48:51.04#ibcon#read 4, iclass 5, count 2 2006.285.08:48:51.04#ibcon#about to read 5, iclass 5, count 2 2006.285.08:48:51.05#ibcon#read 5, iclass 5, count 2 2006.285.08:48:51.05#ibcon#about to read 6, iclass 5, count 2 2006.285.08:48:51.05#ibcon#read 6, iclass 5, count 2 2006.285.08:48:51.05#ibcon#end of sib2, iclass 5, count 2 2006.285.08:48:51.05#ibcon#*after write, iclass 5, count 2 2006.285.08:48:51.05#ibcon#*before return 0, iclass 5, count 2 2006.285.08:48:51.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:48:51.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.08:48:51.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.08:48:51.05#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:51.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:48:51.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:48:51.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:48:51.16#ibcon#enter wrdev, iclass 5, count 0 2006.285.08:48:51.16#ibcon#first serial, iclass 5, count 0 2006.285.08:48:51.17#ibcon#enter sib2, iclass 5, count 0 2006.285.08:48:51.17#ibcon#flushed, iclass 5, count 0 2006.285.08:48:51.17#ibcon#about to write, iclass 5, count 0 2006.285.08:48:51.17#ibcon#wrote, iclass 5, count 0 2006.285.08:48:51.17#ibcon#about to read 3, iclass 5, count 0 2006.285.08:48:51.18#ibcon#read 3, iclass 5, count 0 2006.285.08:48:51.18#ibcon#about to read 4, iclass 5, count 0 2006.285.08:48:51.19#ibcon#read 4, iclass 5, count 0 2006.285.08:48:51.19#ibcon#about to read 5, iclass 5, count 0 2006.285.08:48:51.19#ibcon#read 5, iclass 5, count 0 2006.285.08:48:51.19#ibcon#about to read 6, iclass 5, count 0 2006.285.08:48:51.19#ibcon#read 6, iclass 5, count 0 2006.285.08:48:51.19#ibcon#end of sib2, iclass 5, count 0 2006.285.08:48:51.19#ibcon#*mode == 0, iclass 5, count 0 2006.285.08:48:51.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.08:48:51.19#ibcon#[27=USB\r\n] 2006.285.08:48:51.19#ibcon#*before write, iclass 5, count 0 2006.285.08:48:51.19#ibcon#enter sib2, iclass 5, count 0 2006.285.08:48:51.19#ibcon#flushed, iclass 5, count 0 2006.285.08:48:51.19#ibcon#about to write, iclass 5, count 0 2006.285.08:48:51.19#ibcon#wrote, iclass 5, count 0 2006.285.08:48:51.19#ibcon#about to read 3, iclass 5, count 0 2006.285.08:48:51.21#ibcon#read 3, iclass 5, count 0 2006.285.08:48:51.21#ibcon#about to read 4, iclass 5, count 0 2006.285.08:48:51.21#ibcon#read 4, iclass 5, count 0 2006.285.08:48:51.21#ibcon#about to read 5, iclass 5, count 0 2006.285.08:48:51.22#ibcon#read 5, iclass 5, count 0 2006.285.08:48:51.22#ibcon#about to read 6, iclass 5, count 0 2006.285.08:48:51.22#ibcon#read 6, iclass 5, count 0 2006.285.08:48:51.22#ibcon#end of sib2, iclass 5, count 0 2006.285.08:48:51.22#ibcon#*after write, iclass 5, count 0 2006.285.08:48:51.22#ibcon#*before return 0, iclass 5, count 0 2006.285.08:48:51.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:48:51.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.08:48:51.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.08:48:51.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.08:48:51.22$vck44/vblo=6,719.99 2006.285.08:48:51.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.08:48:51.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.08:48:51.22#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:51.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:48:51.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:48:51.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:48:51.22#ibcon#enter wrdev, iclass 7, count 0 2006.285.08:48:51.22#ibcon#first serial, iclass 7, count 0 2006.285.08:48:51.22#ibcon#enter sib2, iclass 7, count 0 2006.285.08:48:51.22#ibcon#flushed, iclass 7, count 0 2006.285.08:48:51.22#ibcon#about to write, iclass 7, count 0 2006.285.08:48:51.22#ibcon#wrote, iclass 7, count 0 2006.285.08:48:51.22#ibcon#about to read 3, iclass 7, count 0 2006.285.08:48:51.23#ibcon#read 3, iclass 7, count 0 2006.285.08:48:51.23#ibcon#about to read 4, iclass 7, count 0 2006.285.08:48:51.23#ibcon#read 4, iclass 7, count 0 2006.285.08:48:51.24#ibcon#about to read 5, iclass 7, count 0 2006.285.08:48:51.24#ibcon#read 5, iclass 7, count 0 2006.285.08:48:51.24#ibcon#about to read 6, iclass 7, count 0 2006.285.08:48:51.24#ibcon#read 6, iclass 7, count 0 2006.285.08:48:51.24#ibcon#end of sib2, iclass 7, count 0 2006.285.08:48:51.24#ibcon#*mode == 0, iclass 7, count 0 2006.285.08:48:51.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.08:48:51.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:48:51.24#ibcon#*before write, iclass 7, count 0 2006.285.08:48:51.24#ibcon#enter sib2, iclass 7, count 0 2006.285.08:48:51.24#ibcon#flushed, iclass 7, count 0 2006.285.08:48:51.24#ibcon#about to write, iclass 7, count 0 2006.285.08:48:51.24#ibcon#wrote, iclass 7, count 0 2006.285.08:48:51.24#ibcon#about to read 3, iclass 7, count 0 2006.285.08:48:51.27#ibcon#read 3, iclass 7, count 0 2006.285.08:48:51.27#ibcon#about to read 4, iclass 7, count 0 2006.285.08:48:51.27#ibcon#read 4, iclass 7, count 0 2006.285.08:48:51.27#ibcon#about to read 5, iclass 7, count 0 2006.285.08:48:51.28#ibcon#read 5, iclass 7, count 0 2006.285.08:48:51.28#ibcon#about to read 6, iclass 7, count 0 2006.285.08:48:51.28#ibcon#read 6, iclass 7, count 0 2006.285.08:48:51.28#ibcon#end of sib2, iclass 7, count 0 2006.285.08:48:51.28#ibcon#*after write, iclass 7, count 0 2006.285.08:48:51.28#ibcon#*before return 0, iclass 7, count 0 2006.285.08:48:51.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:48:51.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.08:48:51.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.08:48:51.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.08:48:51.28$vck44/vb=6,3 2006.285.08:48:51.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.08:48:51.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.08:48:51.28#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:51.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:48:51.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:48:51.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:48:51.33#ibcon#enter wrdev, iclass 11, count 2 2006.285.08:48:51.33#ibcon#first serial, iclass 11, count 2 2006.285.08:48:51.34#ibcon#enter sib2, iclass 11, count 2 2006.285.08:48:51.34#ibcon#flushed, iclass 11, count 2 2006.285.08:48:51.34#ibcon#about to write, iclass 11, count 2 2006.285.08:48:51.34#ibcon#wrote, iclass 11, count 2 2006.285.08:48:51.34#ibcon#about to read 3, iclass 11, count 2 2006.285.08:48:51.35#ibcon#read 3, iclass 11, count 2 2006.285.08:48:51.35#ibcon#about to read 4, iclass 11, count 2 2006.285.08:48:51.35#ibcon#read 4, iclass 11, count 2 2006.285.08:48:51.35#ibcon#about to read 5, iclass 11, count 2 2006.285.08:48:51.35#ibcon#read 5, iclass 11, count 2 2006.285.08:48:51.36#ibcon#about to read 6, iclass 11, count 2 2006.285.08:48:51.36#ibcon#read 6, iclass 11, count 2 2006.285.08:48:51.36#ibcon#end of sib2, iclass 11, count 2 2006.285.08:48:51.36#ibcon#*mode == 0, iclass 11, count 2 2006.285.08:48:51.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.08:48:51.36#ibcon#[27=AT06-03\r\n] 2006.285.08:48:51.36#ibcon#*before write, iclass 11, count 2 2006.285.08:48:51.36#ibcon#enter sib2, iclass 11, count 2 2006.285.08:48:51.36#ibcon#flushed, iclass 11, count 2 2006.285.08:48:51.36#ibcon#about to write, iclass 11, count 2 2006.285.08:48:51.36#ibcon#wrote, iclass 11, count 2 2006.285.08:48:51.36#ibcon#about to read 3, iclass 11, count 2 2006.285.08:48:51.38#ibcon#read 3, iclass 11, count 2 2006.285.08:48:51.38#ibcon#about to read 4, iclass 11, count 2 2006.285.08:48:51.38#ibcon#read 4, iclass 11, count 2 2006.285.08:48:51.38#ibcon#about to read 5, iclass 11, count 2 2006.285.08:48:51.39#ibcon#read 5, iclass 11, count 2 2006.285.08:48:51.39#ibcon#about to read 6, iclass 11, count 2 2006.285.08:48:51.39#ibcon#read 6, iclass 11, count 2 2006.285.08:48:51.39#ibcon#end of sib2, iclass 11, count 2 2006.285.08:48:51.39#ibcon#*after write, iclass 11, count 2 2006.285.08:48:51.39#ibcon#*before return 0, iclass 11, count 2 2006.285.08:48:51.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:48:51.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.08:48:51.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.08:48:51.39#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:51.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:48:51.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:48:51.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:48:51.50#ibcon#enter wrdev, iclass 11, count 0 2006.285.08:48:51.51#ibcon#first serial, iclass 11, count 0 2006.285.08:48:51.51#ibcon#enter sib2, iclass 11, count 0 2006.285.08:48:51.51#ibcon#flushed, iclass 11, count 0 2006.285.08:48:51.51#ibcon#about to write, iclass 11, count 0 2006.285.08:48:51.51#ibcon#wrote, iclass 11, count 0 2006.285.08:48:51.51#ibcon#about to read 3, iclass 11, count 0 2006.285.08:48:51.52#ibcon#read 3, iclass 11, count 0 2006.285.08:48:51.52#ibcon#about to read 4, iclass 11, count 0 2006.285.08:48:51.53#ibcon#read 4, iclass 11, count 0 2006.285.08:48:51.53#ibcon#about to read 5, iclass 11, count 0 2006.285.08:48:51.53#ibcon#read 5, iclass 11, count 0 2006.285.08:48:51.53#ibcon#about to read 6, iclass 11, count 0 2006.285.08:48:51.53#ibcon#read 6, iclass 11, count 0 2006.285.08:48:51.53#ibcon#end of sib2, iclass 11, count 0 2006.285.08:48:51.53#ibcon#*mode == 0, iclass 11, count 0 2006.285.08:48:51.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.08:48:51.53#ibcon#[27=USB\r\n] 2006.285.08:48:51.53#ibcon#*before write, iclass 11, count 0 2006.285.08:48:51.53#ibcon#enter sib2, iclass 11, count 0 2006.285.08:48:51.53#ibcon#flushed, iclass 11, count 0 2006.285.08:48:51.53#ibcon#about to write, iclass 11, count 0 2006.285.08:48:51.53#ibcon#wrote, iclass 11, count 0 2006.285.08:48:51.53#ibcon#about to read 3, iclass 11, count 0 2006.285.08:48:51.55#ibcon#read 3, iclass 11, count 0 2006.285.08:48:51.55#ibcon#about to read 4, iclass 11, count 0 2006.285.08:48:51.56#ibcon#read 4, iclass 11, count 0 2006.285.08:48:51.56#ibcon#about to read 5, iclass 11, count 0 2006.285.08:48:51.56#ibcon#read 5, iclass 11, count 0 2006.285.08:48:51.56#ibcon#about to read 6, iclass 11, count 0 2006.285.08:48:51.56#ibcon#read 6, iclass 11, count 0 2006.285.08:48:51.56#ibcon#end of sib2, iclass 11, count 0 2006.285.08:48:51.56#ibcon#*after write, iclass 11, count 0 2006.285.08:48:51.56#ibcon#*before return 0, iclass 11, count 0 2006.285.08:48:51.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:48:51.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.08:48:51.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.08:48:51.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.08:48:51.56$vck44/vblo=7,734.99 2006.285.08:48:51.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.08:48:51.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.08:48:51.56#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:51.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:48:51.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:48:51.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:48:51.56#ibcon#enter wrdev, iclass 13, count 0 2006.285.08:48:51.56#ibcon#first serial, iclass 13, count 0 2006.285.08:48:51.56#ibcon#enter sib2, iclass 13, count 0 2006.285.08:48:51.56#ibcon#flushed, iclass 13, count 0 2006.285.08:48:51.56#ibcon#about to write, iclass 13, count 0 2006.285.08:48:51.56#ibcon#wrote, iclass 13, count 0 2006.285.08:48:51.56#ibcon#about to read 3, iclass 13, count 0 2006.285.08:48:51.57#ibcon#read 3, iclass 13, count 0 2006.285.08:48:51.57#ibcon#about to read 4, iclass 13, count 0 2006.285.08:48:51.57#ibcon#read 4, iclass 13, count 0 2006.285.08:48:51.57#ibcon#about to read 5, iclass 13, count 0 2006.285.08:48:51.58#ibcon#read 5, iclass 13, count 0 2006.285.08:48:51.58#ibcon#about to read 6, iclass 13, count 0 2006.285.08:48:51.58#ibcon#read 6, iclass 13, count 0 2006.285.08:48:51.58#ibcon#end of sib2, iclass 13, count 0 2006.285.08:48:51.58#ibcon#*mode == 0, iclass 13, count 0 2006.285.08:48:51.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.08:48:51.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:48:51.58#ibcon#*before write, iclass 13, count 0 2006.285.08:48:51.58#ibcon#enter sib2, iclass 13, count 0 2006.285.08:48:51.58#ibcon#flushed, iclass 13, count 0 2006.285.08:48:51.58#ibcon#about to write, iclass 13, count 0 2006.285.08:48:51.58#ibcon#wrote, iclass 13, count 0 2006.285.08:48:51.58#ibcon#about to read 3, iclass 13, count 0 2006.285.08:48:51.61#ibcon#read 3, iclass 13, count 0 2006.285.08:48:51.61#ibcon#about to read 4, iclass 13, count 0 2006.285.08:48:51.61#ibcon#read 4, iclass 13, count 0 2006.285.08:48:51.61#ibcon#about to read 5, iclass 13, count 0 2006.285.08:48:51.62#ibcon#read 5, iclass 13, count 0 2006.285.08:48:51.62#ibcon#about to read 6, iclass 13, count 0 2006.285.08:48:51.62#ibcon#read 6, iclass 13, count 0 2006.285.08:48:51.62#ibcon#end of sib2, iclass 13, count 0 2006.285.08:48:51.62#ibcon#*after write, iclass 13, count 0 2006.285.08:48:51.62#ibcon#*before return 0, iclass 13, count 0 2006.285.08:48:51.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:48:51.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.08:48:51.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.08:48:51.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.08:48:51.62$vck44/vb=7,4 2006.285.08:48:51.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.08:48:51.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.08:48:51.62#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:51.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:48:51.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:48:51.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:48:51.67#ibcon#enter wrdev, iclass 15, count 2 2006.285.08:48:51.67#ibcon#first serial, iclass 15, count 2 2006.285.08:48:51.67#ibcon#enter sib2, iclass 15, count 2 2006.285.08:48:51.68#ibcon#flushed, iclass 15, count 2 2006.285.08:48:51.68#ibcon#about to write, iclass 15, count 2 2006.285.08:48:51.68#ibcon#wrote, iclass 15, count 2 2006.285.08:48:51.68#ibcon#about to read 3, iclass 15, count 2 2006.285.08:48:51.69#ibcon#read 3, iclass 15, count 2 2006.285.08:48:51.69#ibcon#about to read 4, iclass 15, count 2 2006.285.08:48:51.69#ibcon#read 4, iclass 15, count 2 2006.285.08:48:51.69#ibcon#about to read 5, iclass 15, count 2 2006.285.08:48:51.69#ibcon#read 5, iclass 15, count 2 2006.285.08:48:51.70#ibcon#about to read 6, iclass 15, count 2 2006.285.08:48:51.70#ibcon#read 6, iclass 15, count 2 2006.285.08:48:51.70#ibcon#end of sib2, iclass 15, count 2 2006.285.08:48:51.70#ibcon#*mode == 0, iclass 15, count 2 2006.285.08:48:51.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.08:48:51.70#ibcon#[27=AT07-04\r\n] 2006.285.08:48:51.70#ibcon#*before write, iclass 15, count 2 2006.285.08:48:51.70#ibcon#enter sib2, iclass 15, count 2 2006.285.08:48:51.70#ibcon#flushed, iclass 15, count 2 2006.285.08:48:51.70#ibcon#about to write, iclass 15, count 2 2006.285.08:48:51.70#ibcon#wrote, iclass 15, count 2 2006.285.08:48:51.70#ibcon#about to read 3, iclass 15, count 2 2006.285.08:48:51.72#ibcon#read 3, iclass 15, count 2 2006.285.08:48:51.72#ibcon#about to read 4, iclass 15, count 2 2006.285.08:48:51.72#ibcon#read 4, iclass 15, count 2 2006.285.08:48:51.72#ibcon#about to read 5, iclass 15, count 2 2006.285.08:48:51.73#ibcon#read 5, iclass 15, count 2 2006.285.08:48:51.73#ibcon#about to read 6, iclass 15, count 2 2006.285.08:48:51.73#ibcon#read 6, iclass 15, count 2 2006.285.08:48:51.73#ibcon#end of sib2, iclass 15, count 2 2006.285.08:48:51.73#ibcon#*after write, iclass 15, count 2 2006.285.08:48:51.73#ibcon#*before return 0, iclass 15, count 2 2006.285.08:48:51.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:48:51.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.08:48:51.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.08:48:51.73#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:51.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:48:51.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:48:51.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:48:51.84#ibcon#enter wrdev, iclass 15, count 0 2006.285.08:48:51.84#ibcon#first serial, iclass 15, count 0 2006.285.08:48:51.85#ibcon#enter sib2, iclass 15, count 0 2006.285.08:48:51.85#ibcon#flushed, iclass 15, count 0 2006.285.08:48:51.85#ibcon#about to write, iclass 15, count 0 2006.285.08:48:51.85#ibcon#wrote, iclass 15, count 0 2006.285.08:48:51.85#ibcon#about to read 3, iclass 15, count 0 2006.285.08:48:51.86#ibcon#read 3, iclass 15, count 0 2006.285.08:48:51.86#ibcon#about to read 4, iclass 15, count 0 2006.285.08:48:51.86#ibcon#read 4, iclass 15, count 0 2006.285.08:48:51.86#ibcon#about to read 5, iclass 15, count 0 2006.285.08:48:51.86#ibcon#read 5, iclass 15, count 0 2006.285.08:48:51.87#ibcon#about to read 6, iclass 15, count 0 2006.285.08:48:51.87#ibcon#read 6, iclass 15, count 0 2006.285.08:48:51.87#ibcon#end of sib2, iclass 15, count 0 2006.285.08:48:51.87#ibcon#*mode == 0, iclass 15, count 0 2006.285.08:48:51.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.08:48:51.87#ibcon#[27=USB\r\n] 2006.285.08:48:51.87#ibcon#*before write, iclass 15, count 0 2006.285.08:48:51.87#ibcon#enter sib2, iclass 15, count 0 2006.285.08:48:51.87#ibcon#flushed, iclass 15, count 0 2006.285.08:48:51.87#ibcon#about to write, iclass 15, count 0 2006.285.08:48:51.87#ibcon#wrote, iclass 15, count 0 2006.285.08:48:51.87#ibcon#about to read 3, iclass 15, count 0 2006.285.08:48:51.89#ibcon#read 3, iclass 15, count 0 2006.285.08:48:51.89#ibcon#about to read 4, iclass 15, count 0 2006.285.08:48:51.89#ibcon#read 4, iclass 15, count 0 2006.285.08:48:51.89#ibcon#about to read 5, iclass 15, count 0 2006.285.08:48:51.89#ibcon#read 5, iclass 15, count 0 2006.285.08:48:51.90#ibcon#about to read 6, iclass 15, count 0 2006.285.08:48:51.90#ibcon#read 6, iclass 15, count 0 2006.285.08:48:51.90#ibcon#end of sib2, iclass 15, count 0 2006.285.08:48:51.90#ibcon#*after write, iclass 15, count 0 2006.285.08:48:51.90#ibcon#*before return 0, iclass 15, count 0 2006.285.08:48:51.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:48:51.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.08:48:51.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.08:48:51.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.08:48:51.90$vck44/vblo=8,744.99 2006.285.08:48:51.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.08:48:51.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.08:48:51.90#ibcon#ireg 17 cls_cnt 0 2006.285.08:48:51.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:48:51.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:48:51.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:48:51.90#ibcon#enter wrdev, iclass 17, count 0 2006.285.08:48:51.90#ibcon#first serial, iclass 17, count 0 2006.285.08:48:51.90#ibcon#enter sib2, iclass 17, count 0 2006.285.08:48:51.90#ibcon#flushed, iclass 17, count 0 2006.285.08:48:51.90#ibcon#about to write, iclass 17, count 0 2006.285.08:48:51.90#ibcon#wrote, iclass 17, count 0 2006.285.08:48:51.90#ibcon#about to read 3, iclass 17, count 0 2006.285.08:48:51.91#ibcon#read 3, iclass 17, count 0 2006.285.08:48:51.91#ibcon#about to read 4, iclass 17, count 0 2006.285.08:48:51.91#ibcon#read 4, iclass 17, count 0 2006.285.08:48:51.91#ibcon#about to read 5, iclass 17, count 0 2006.285.08:48:51.92#ibcon#read 5, iclass 17, count 0 2006.285.08:48:51.92#ibcon#about to read 6, iclass 17, count 0 2006.285.08:48:51.92#ibcon#read 6, iclass 17, count 0 2006.285.08:48:51.92#ibcon#end of sib2, iclass 17, count 0 2006.285.08:48:51.92#ibcon#*mode == 0, iclass 17, count 0 2006.285.08:48:51.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.08:48:51.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:48:51.92#ibcon#*before write, iclass 17, count 0 2006.285.08:48:51.92#ibcon#enter sib2, iclass 17, count 0 2006.285.08:48:51.92#ibcon#flushed, iclass 17, count 0 2006.285.08:48:51.92#ibcon#about to write, iclass 17, count 0 2006.285.08:48:51.92#ibcon#wrote, iclass 17, count 0 2006.285.08:48:51.92#ibcon#about to read 3, iclass 17, count 0 2006.285.08:48:51.95#ibcon#read 3, iclass 17, count 0 2006.285.08:48:51.95#ibcon#about to read 4, iclass 17, count 0 2006.285.08:48:51.95#ibcon#read 4, iclass 17, count 0 2006.285.08:48:51.95#ibcon#about to read 5, iclass 17, count 0 2006.285.08:48:51.96#ibcon#read 5, iclass 17, count 0 2006.285.08:48:51.96#ibcon#about to read 6, iclass 17, count 0 2006.285.08:48:51.96#ibcon#read 6, iclass 17, count 0 2006.285.08:48:51.96#ibcon#end of sib2, iclass 17, count 0 2006.285.08:48:51.96#ibcon#*after write, iclass 17, count 0 2006.285.08:48:51.96#ibcon#*before return 0, iclass 17, count 0 2006.285.08:48:51.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:48:51.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.08:48:51.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.08:48:51.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.08:48:51.96$vck44/vb=8,4 2006.285.08:48:51.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.08:48:51.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.08:48:51.96#ibcon#ireg 11 cls_cnt 2 2006.285.08:48:51.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:48:52.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:48:52.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:48:52.01#ibcon#enter wrdev, iclass 19, count 2 2006.285.08:48:52.01#ibcon#first serial, iclass 19, count 2 2006.285.08:48:52.02#ibcon#enter sib2, iclass 19, count 2 2006.285.08:48:52.02#ibcon#flushed, iclass 19, count 2 2006.285.08:48:52.02#ibcon#about to write, iclass 19, count 2 2006.285.08:48:52.02#ibcon#wrote, iclass 19, count 2 2006.285.08:48:52.02#ibcon#about to read 3, iclass 19, count 2 2006.285.08:48:52.03#ibcon#read 3, iclass 19, count 2 2006.285.08:48:52.03#ibcon#about to read 4, iclass 19, count 2 2006.285.08:48:52.03#ibcon#read 4, iclass 19, count 2 2006.285.08:48:52.03#ibcon#about to read 5, iclass 19, count 2 2006.285.08:48:52.03#ibcon#read 5, iclass 19, count 2 2006.285.08:48:52.04#ibcon#about to read 6, iclass 19, count 2 2006.285.08:48:52.04#ibcon#read 6, iclass 19, count 2 2006.285.08:48:52.04#ibcon#end of sib2, iclass 19, count 2 2006.285.08:48:52.04#ibcon#*mode == 0, iclass 19, count 2 2006.285.08:48:52.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.08:48:52.04#ibcon#[27=AT08-04\r\n] 2006.285.08:48:52.04#ibcon#*before write, iclass 19, count 2 2006.285.08:48:52.04#ibcon#enter sib2, iclass 19, count 2 2006.285.08:48:52.04#ibcon#flushed, iclass 19, count 2 2006.285.08:48:52.04#ibcon#about to write, iclass 19, count 2 2006.285.08:48:52.04#ibcon#wrote, iclass 19, count 2 2006.285.08:48:52.04#ibcon#about to read 3, iclass 19, count 2 2006.285.08:48:52.06#ibcon#read 3, iclass 19, count 2 2006.285.08:48:52.06#ibcon#about to read 4, iclass 19, count 2 2006.285.08:48:52.06#ibcon#read 4, iclass 19, count 2 2006.285.08:48:52.07#ibcon#about to read 5, iclass 19, count 2 2006.285.08:48:52.07#ibcon#read 5, iclass 19, count 2 2006.285.08:48:52.07#ibcon#about to read 6, iclass 19, count 2 2006.285.08:48:52.07#ibcon#read 6, iclass 19, count 2 2006.285.08:48:52.07#ibcon#end of sib2, iclass 19, count 2 2006.285.08:48:52.07#ibcon#*after write, iclass 19, count 2 2006.285.08:48:52.07#ibcon#*before return 0, iclass 19, count 2 2006.285.08:48:52.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:48:52.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.08:48:52.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.08:48:52.07#ibcon#ireg 7 cls_cnt 0 2006.285.08:48:52.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:48:52.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:48:52.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:48:52.18#ibcon#enter wrdev, iclass 19, count 0 2006.285.08:48:52.18#ibcon#first serial, iclass 19, count 0 2006.285.08:48:52.19#ibcon#enter sib2, iclass 19, count 0 2006.285.08:48:52.19#ibcon#flushed, iclass 19, count 0 2006.285.08:48:52.19#ibcon#about to write, iclass 19, count 0 2006.285.08:48:52.19#ibcon#wrote, iclass 19, count 0 2006.285.08:48:52.19#ibcon#about to read 3, iclass 19, count 0 2006.285.08:48:52.20#ibcon#read 3, iclass 19, count 0 2006.285.08:48:52.20#ibcon#about to read 4, iclass 19, count 0 2006.285.08:48:52.21#ibcon#read 4, iclass 19, count 0 2006.285.08:48:52.21#ibcon#about to read 5, iclass 19, count 0 2006.285.08:48:52.21#ibcon#read 5, iclass 19, count 0 2006.285.08:48:52.21#ibcon#about to read 6, iclass 19, count 0 2006.285.08:48:52.21#ibcon#read 6, iclass 19, count 0 2006.285.08:48:52.21#ibcon#end of sib2, iclass 19, count 0 2006.285.08:48:52.21#ibcon#*mode == 0, iclass 19, count 0 2006.285.08:48:52.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.08:48:52.21#ibcon#[27=USB\r\n] 2006.285.08:48:52.21#ibcon#*before write, iclass 19, count 0 2006.285.08:48:52.21#ibcon#enter sib2, iclass 19, count 0 2006.285.08:48:52.21#ibcon#flushed, iclass 19, count 0 2006.285.08:48:52.21#ibcon#about to write, iclass 19, count 0 2006.285.08:48:52.21#ibcon#wrote, iclass 19, count 0 2006.285.08:48:52.21#ibcon#about to read 3, iclass 19, count 0 2006.285.08:48:52.23#ibcon#read 3, iclass 19, count 0 2006.285.08:48:52.23#ibcon#about to read 4, iclass 19, count 0 2006.285.08:48:52.23#ibcon#read 4, iclass 19, count 0 2006.285.08:48:52.23#ibcon#about to read 5, iclass 19, count 0 2006.285.08:48:52.24#ibcon#read 5, iclass 19, count 0 2006.285.08:48:52.24#ibcon#about to read 6, iclass 19, count 0 2006.285.08:48:52.24#ibcon#read 6, iclass 19, count 0 2006.285.08:48:52.24#ibcon#end of sib2, iclass 19, count 0 2006.285.08:48:52.24#ibcon#*after write, iclass 19, count 0 2006.285.08:48:52.24#ibcon#*before return 0, iclass 19, count 0 2006.285.08:48:52.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:48:52.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.08:48:52.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.08:48:52.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.08:48:52.24$vck44/vabw=wide 2006.285.08:48:52.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.08:48:52.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.08:48:52.24#ibcon#ireg 8 cls_cnt 0 2006.285.08:48:52.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:48:52.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:48:52.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:48:52.24#ibcon#enter wrdev, iclass 21, count 0 2006.285.08:48:52.24#ibcon#first serial, iclass 21, count 0 2006.285.08:48:52.24#ibcon#enter sib2, iclass 21, count 0 2006.285.08:48:52.24#ibcon#flushed, iclass 21, count 0 2006.285.08:48:52.24#ibcon#about to write, iclass 21, count 0 2006.285.08:48:52.24#ibcon#wrote, iclass 21, count 0 2006.285.08:48:52.24#ibcon#about to read 3, iclass 21, count 0 2006.285.08:48:52.25#ibcon#read 3, iclass 21, count 0 2006.285.08:48:52.25#ibcon#about to read 4, iclass 21, count 0 2006.285.08:48:52.25#ibcon#read 4, iclass 21, count 0 2006.285.08:48:52.25#ibcon#about to read 5, iclass 21, count 0 2006.285.08:48:52.26#ibcon#read 5, iclass 21, count 0 2006.285.08:48:52.26#ibcon#about to read 6, iclass 21, count 0 2006.285.08:48:52.26#ibcon#read 6, iclass 21, count 0 2006.285.08:48:52.26#ibcon#end of sib2, iclass 21, count 0 2006.285.08:48:52.26#ibcon#*mode == 0, iclass 21, count 0 2006.285.08:48:52.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.08:48:52.26#ibcon#[25=BW32\r\n] 2006.285.08:48:52.26#ibcon#*before write, iclass 21, count 0 2006.285.08:48:52.26#ibcon#enter sib2, iclass 21, count 0 2006.285.08:48:52.26#ibcon#flushed, iclass 21, count 0 2006.285.08:48:52.26#ibcon#about to write, iclass 21, count 0 2006.285.08:48:52.26#ibcon#wrote, iclass 21, count 0 2006.285.08:48:52.26#ibcon#about to read 3, iclass 21, count 0 2006.285.08:48:52.28#ibcon#read 3, iclass 21, count 0 2006.285.08:48:52.28#ibcon#about to read 4, iclass 21, count 0 2006.285.08:48:52.28#ibcon#read 4, iclass 21, count 0 2006.285.08:48:52.28#ibcon#about to read 5, iclass 21, count 0 2006.285.08:48:52.29#ibcon#read 5, iclass 21, count 0 2006.285.08:48:52.29#ibcon#about to read 6, iclass 21, count 0 2006.285.08:48:52.29#ibcon#read 6, iclass 21, count 0 2006.285.08:48:52.29#ibcon#end of sib2, iclass 21, count 0 2006.285.08:48:52.29#ibcon#*after write, iclass 21, count 0 2006.285.08:48:52.29#ibcon#*before return 0, iclass 21, count 0 2006.285.08:48:52.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:48:52.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.08:48:52.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.08:48:52.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.08:48:52.29$vck44/vbbw=wide 2006.285.08:48:52.29#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.08:48:52.29#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.08:48:52.29#ibcon#ireg 8 cls_cnt 0 2006.285.08:48:52.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:48:52.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:48:52.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:48:52.35#ibcon#enter wrdev, iclass 23, count 0 2006.285.08:48:52.35#ibcon#first serial, iclass 23, count 0 2006.285.08:48:52.35#ibcon#enter sib2, iclass 23, count 0 2006.285.08:48:52.36#ibcon#flushed, iclass 23, count 0 2006.285.08:48:52.36#ibcon#about to write, iclass 23, count 0 2006.285.08:48:52.36#ibcon#wrote, iclass 23, count 0 2006.285.08:48:52.36#ibcon#about to read 3, iclass 23, count 0 2006.285.08:48:52.37#ibcon#read 3, iclass 23, count 0 2006.285.08:48:52.37#ibcon#about to read 4, iclass 23, count 0 2006.285.08:48:52.37#ibcon#read 4, iclass 23, count 0 2006.285.08:48:52.37#ibcon#about to read 5, iclass 23, count 0 2006.285.08:48:52.38#ibcon#read 5, iclass 23, count 0 2006.285.08:48:52.38#ibcon#about to read 6, iclass 23, count 0 2006.285.08:48:52.38#ibcon#read 6, iclass 23, count 0 2006.285.08:48:52.38#ibcon#end of sib2, iclass 23, count 0 2006.285.08:48:52.38#ibcon#*mode == 0, iclass 23, count 0 2006.285.08:48:52.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.08:48:52.38#ibcon#[27=BW32\r\n] 2006.285.08:48:52.38#ibcon#*before write, iclass 23, count 0 2006.285.08:48:52.38#ibcon#enter sib2, iclass 23, count 0 2006.285.08:48:52.38#ibcon#flushed, iclass 23, count 0 2006.285.08:48:52.38#ibcon#about to write, iclass 23, count 0 2006.285.08:48:52.38#ibcon#wrote, iclass 23, count 0 2006.285.08:48:52.38#ibcon#about to read 3, iclass 23, count 0 2006.285.08:48:52.40#ibcon#read 3, iclass 23, count 0 2006.285.08:48:52.40#ibcon#about to read 4, iclass 23, count 0 2006.285.08:48:52.40#ibcon#read 4, iclass 23, count 0 2006.285.08:48:52.40#ibcon#about to read 5, iclass 23, count 0 2006.285.08:48:52.41#ibcon#read 5, iclass 23, count 0 2006.285.08:48:52.41#ibcon#about to read 6, iclass 23, count 0 2006.285.08:48:52.41#ibcon#read 6, iclass 23, count 0 2006.285.08:48:52.41#ibcon#end of sib2, iclass 23, count 0 2006.285.08:48:52.41#ibcon#*after write, iclass 23, count 0 2006.285.08:48:52.41#ibcon#*before return 0, iclass 23, count 0 2006.285.08:48:52.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:48:52.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.08:48:52.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.08:48:52.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.08:48:52.41$setupk4/ifdk4 2006.285.08:48:52.41$ifdk4/lo= 2006.285.08:48:52.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:48:52.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:48:52.41$ifdk4/patch= 2006.285.08:48:52.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:48:52.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:48:52.41$setupk4/!*+20s 2006.285.08:48:54.01#abcon#<5=/04 1.2 2.0 21.79 821014.9\r\n> 2006.285.08:48:54.03#abcon#{5=INTERFACE CLEAR} 2006.285.08:48:54.09#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:49:04.18#abcon#<5=/04 1.2 2.0 21.79 821014.9\r\n> 2006.285.08:49:04.20#abcon#{5=INTERFACE CLEAR} 2006.285.08:49:04.26#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:49:06.92$setupk4/"tpicd 2006.285.08:49:06.93$setupk4/echo=off 2006.285.08:49:06.93$setupk4/xlog=off 2006.285.08:49:06.93:!2006.285.08:54:43 2006.285.08:49:31.14#trakl#Source acquired 2006.285.08:49:32.15#flagr#flagr/antenna,acquired 2006.285.08:54:43.00:preob 2006.285.08:54:43.14/onsource/TRACKING 2006.285.08:54:43.14:!2006.285.08:54:53 2006.285.08:54:53.00:"tape 2006.285.08:54:53.00:"st=record 2006.285.08:54:53.00:data_valid=on 2006.285.08:54:53.00:midob 2006.285.08:54:53.14/onsource/TRACKING 2006.285.08:54:53.15/wx/21.66,1014.9,82 2006.285.08:54:53.35/cable/+6.4794E-03 2006.285.08:54:54.44/va/01,07,usb,yes,35,38 2006.285.08:54:54.44/va/02,06,usb,yes,35,36 2006.285.08:54:54.44/va/03,07,usb,yes,35,37 2006.285.08:54:54.44/va/04,06,usb,yes,36,38 2006.285.08:54:54.44/va/05,03,usb,yes,36,36 2006.285.08:54:54.44/va/06,04,usb,yes,32,32 2006.285.08:54:54.44/va/07,04,usb,yes,33,34 2006.285.08:54:54.44/va/08,03,usb,yes,34,41 2006.285.08:54:54.67/valo/01,524.99,yes,locked 2006.285.08:54:54.67/valo/02,534.99,yes,locked 2006.285.08:54:54.67/valo/03,564.99,yes,locked 2006.285.08:54:54.67/valo/04,624.99,yes,locked 2006.285.08:54:54.67/valo/05,734.99,yes,locked 2006.285.08:54:54.67/valo/06,814.99,yes,locked 2006.285.08:54:54.67/valo/07,864.99,yes,locked 2006.285.08:54:54.67/valo/08,884.99,yes,locked 2006.285.08:54:55.76/vb/01,04,usb,yes,32,30 2006.285.08:54:55.76/vb/02,05,usb,yes,31,30 2006.285.08:54:55.76/vb/03,04,usb,yes,32,35 2006.285.08:54:55.76/vb/04,05,usb,yes,32,31 2006.285.08:54:55.76/vb/05,04,usb,yes,28,31 2006.285.08:54:55.76/vb/06,03,usb,yes,40,36 2006.285.08:54:55.76/vb/07,04,usb,yes,33,33 2006.285.08:54:55.76/vb/08,04,usb,yes,30,33 2006.285.08:54:55.99/vblo/01,629.99,yes,locked 2006.285.08:54:55.99/vblo/02,634.99,yes,locked 2006.285.08:54:55.99/vblo/03,649.99,yes,locked 2006.285.08:54:55.99/vblo/04,679.99,yes,locked 2006.285.08:54:55.99/vblo/05,709.99,yes,locked 2006.285.08:54:55.99/vblo/06,719.99,yes,locked 2006.285.08:54:55.99/vblo/07,734.99,yes,locked 2006.285.08:54:55.99/vblo/08,744.99,yes,locked 2006.285.08:54:56.14/vabw/8 2006.285.08:54:56.29/vbbw/8 2006.285.08:54:56.50/xfe/off,on,12.2 2006.285.08:54:56.87/ifatt/23,28,28,28 2006.285.08:54:57.07/fmout-gps/S +2.49E-07 2006.285.08:54:57.09:!2006.285.08:55:33 2006.285.08:55:33.00:data_valid=off 2006.285.08:55:33.00:"et 2006.285.08:55:33.00:!+3s 2006.285.08:55:36.01:"tape 2006.285.08:55:36.01:postob 2006.285.08:55:36.10/cable/+6.4792E-03 2006.285.08:55:36.10/wx/21.64,1014.9,82 2006.285.08:55:37.07/fmout-gps/S +2.49E-07 2006.285.08:55:37.07:scan_name=285-0904,jd0610,40 2006.285.08:55:37.07:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.285.08:55:38.13#flagr#flagr/antenna,new-source 2006.285.08:55:38.13:checkk5 2006.285.08:55:38.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.08:55:38.91/chk_autoobs//k5ts2/ autoobs is running! 2006.285.08:55:39.35/chk_autoobs//k5ts3/ autoobs is running! 2006.285.08:55:39.72/chk_autoobs//k5ts4/ autoobs is running! 2006.285.08:55:40.07/chk_obsdata//k5ts1/T2850854??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:55:40.45/chk_obsdata//k5ts2/T2850854??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:55:40.88/chk_obsdata//k5ts3/T2850854??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:55:41.21/chk_obsdata//k5ts4/T2850854??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.08:55:41.93/k5log//k5ts1_log_newline 2006.285.08:55:42.70/k5log//k5ts2_log_newline 2006.285.08:55:43.71/k5log//k5ts3_log_newline 2006.285.08:55:44.39/k5log//k5ts4_log_newline 2006.285.08:55:44.41/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.08:55:44.41:setupk4=1 2006.285.08:55:44.41$setupk4/echo=on 2006.285.08:55:44.41$setupk4/pcalon 2006.285.08:55:44.41$pcalon/"no phase cal control is implemented here 2006.285.08:55:44.41$setupk4/"tpicd=stop 2006.285.08:55:44.41$setupk4/"rec=synch_on 2006.285.08:55:44.41$setupk4/"rec_mode=128 2006.285.08:55:44.41$setupk4/!* 2006.285.08:55:44.41$setupk4/recpk4 2006.285.08:55:44.41$recpk4/recpatch= 2006.285.08:55:44.42$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.08:55:44.42$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.08:55:44.42$setupk4/vck44 2006.285.08:55:44.42$vck44/valo=1,524.99 2006.285.08:55:44.42#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.08:55:44.42#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.08:55:44.42#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:44.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:55:44.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:55:44.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:55:44.42#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:55:44.42#ibcon#first serial, iclass 12, count 0 2006.285.08:55:44.42#ibcon#enter sib2, iclass 12, count 0 2006.285.08:55:44.42#ibcon#flushed, iclass 12, count 0 2006.285.08:55:44.42#ibcon#about to write, iclass 12, count 0 2006.285.08:55:44.42#ibcon#wrote, iclass 12, count 0 2006.285.08:55:44.42#ibcon#about to read 3, iclass 12, count 0 2006.285.08:55:44.43#ibcon#read 3, iclass 12, count 0 2006.285.08:55:44.43#ibcon#about to read 4, iclass 12, count 0 2006.285.08:55:44.43#ibcon#read 4, iclass 12, count 0 2006.285.08:55:44.43#ibcon#about to read 5, iclass 12, count 0 2006.285.08:55:44.43#ibcon#read 5, iclass 12, count 0 2006.285.08:55:44.43#ibcon#about to read 6, iclass 12, count 0 2006.285.08:55:44.43#ibcon#read 6, iclass 12, count 0 2006.285.08:55:44.43#ibcon#end of sib2, iclass 12, count 0 2006.285.08:55:44.43#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:55:44.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:55:44.43#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.08:55:44.43#ibcon#*before write, iclass 12, count 0 2006.285.08:55:44.43#ibcon#enter sib2, iclass 12, count 0 2006.285.08:55:44.43#ibcon#flushed, iclass 12, count 0 2006.285.08:55:44.43#ibcon#about to write, iclass 12, count 0 2006.285.08:55:44.43#ibcon#wrote, iclass 12, count 0 2006.285.08:55:44.43#ibcon#about to read 3, iclass 12, count 0 2006.285.08:55:44.48#ibcon#read 3, iclass 12, count 0 2006.285.08:55:44.48#ibcon#about to read 4, iclass 12, count 0 2006.285.08:55:44.48#ibcon#read 4, iclass 12, count 0 2006.285.08:55:44.48#ibcon#about to read 5, iclass 12, count 0 2006.285.08:55:44.48#ibcon#read 5, iclass 12, count 0 2006.285.08:55:44.48#ibcon#about to read 6, iclass 12, count 0 2006.285.08:55:44.48#ibcon#read 6, iclass 12, count 0 2006.285.08:55:44.48#ibcon#end of sib2, iclass 12, count 0 2006.285.08:55:44.48#ibcon#*after write, iclass 12, count 0 2006.285.08:55:44.48#ibcon#*before return 0, iclass 12, count 0 2006.285.08:55:44.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:55:44.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:55:44.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:55:44.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:55:44.49$vck44/va=1,7 2006.285.08:55:44.49#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.08:55:44.49#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.08:55:44.49#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:44.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:55:44.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:55:44.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:55:44.49#ibcon#enter wrdev, iclass 14, count 2 2006.285.08:55:44.49#ibcon#first serial, iclass 14, count 2 2006.285.08:55:44.49#ibcon#enter sib2, iclass 14, count 2 2006.285.08:55:44.49#ibcon#flushed, iclass 14, count 2 2006.285.08:55:44.49#ibcon#about to write, iclass 14, count 2 2006.285.08:55:44.49#ibcon#wrote, iclass 14, count 2 2006.285.08:55:44.49#ibcon#about to read 3, iclass 14, count 2 2006.285.08:55:44.50#ibcon#read 3, iclass 14, count 2 2006.285.08:55:44.50#ibcon#about to read 4, iclass 14, count 2 2006.285.08:55:44.50#ibcon#read 4, iclass 14, count 2 2006.285.08:55:44.50#ibcon#about to read 5, iclass 14, count 2 2006.285.08:55:44.50#ibcon#read 5, iclass 14, count 2 2006.285.08:55:44.50#ibcon#about to read 6, iclass 14, count 2 2006.285.08:55:44.50#ibcon#read 6, iclass 14, count 2 2006.285.08:55:44.50#ibcon#end of sib2, iclass 14, count 2 2006.285.08:55:44.50#ibcon#*mode == 0, iclass 14, count 2 2006.285.08:55:44.50#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.08:55:44.50#ibcon#[25=AT01-07\r\n] 2006.285.08:55:44.50#ibcon#*before write, iclass 14, count 2 2006.285.08:55:44.50#ibcon#enter sib2, iclass 14, count 2 2006.285.08:55:44.50#ibcon#flushed, iclass 14, count 2 2006.285.08:55:44.50#ibcon#about to write, iclass 14, count 2 2006.285.08:55:44.50#ibcon#wrote, iclass 14, count 2 2006.285.08:55:44.50#ibcon#about to read 3, iclass 14, count 2 2006.285.08:55:44.53#ibcon#read 3, iclass 14, count 2 2006.285.08:55:44.53#ibcon#about to read 4, iclass 14, count 2 2006.285.08:55:44.53#ibcon#read 4, iclass 14, count 2 2006.285.08:55:44.53#ibcon#about to read 5, iclass 14, count 2 2006.285.08:55:44.53#ibcon#read 5, iclass 14, count 2 2006.285.08:55:44.53#ibcon#about to read 6, iclass 14, count 2 2006.285.08:55:44.53#ibcon#read 6, iclass 14, count 2 2006.285.08:55:44.53#ibcon#end of sib2, iclass 14, count 2 2006.285.08:55:44.53#ibcon#*after write, iclass 14, count 2 2006.285.08:55:44.53#ibcon#*before return 0, iclass 14, count 2 2006.285.08:55:44.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:55:44.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:55:44.53#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.08:55:44.53#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:44.53#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:55:44.65#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:55:44.65#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:55:44.65#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:55:44.65#ibcon#first serial, iclass 14, count 0 2006.285.08:55:44.65#ibcon#enter sib2, iclass 14, count 0 2006.285.08:55:44.65#ibcon#flushed, iclass 14, count 0 2006.285.08:55:44.65#ibcon#about to write, iclass 14, count 0 2006.285.08:55:44.65#ibcon#wrote, iclass 14, count 0 2006.285.08:55:44.65#ibcon#about to read 3, iclass 14, count 0 2006.285.08:55:44.67#ibcon#read 3, iclass 14, count 0 2006.285.08:55:44.67#ibcon#about to read 4, iclass 14, count 0 2006.285.08:55:44.67#ibcon#read 4, iclass 14, count 0 2006.285.08:55:44.67#ibcon#about to read 5, iclass 14, count 0 2006.285.08:55:44.67#ibcon#read 5, iclass 14, count 0 2006.285.08:55:44.67#ibcon#about to read 6, iclass 14, count 0 2006.285.08:55:44.67#ibcon#read 6, iclass 14, count 0 2006.285.08:55:44.67#ibcon#end of sib2, iclass 14, count 0 2006.285.08:55:44.67#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:55:44.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:55:44.67#ibcon#[25=USB\r\n] 2006.285.08:55:44.67#ibcon#*before write, iclass 14, count 0 2006.285.08:55:44.67#ibcon#enter sib2, iclass 14, count 0 2006.285.08:55:44.67#ibcon#flushed, iclass 14, count 0 2006.285.08:55:44.67#ibcon#about to write, iclass 14, count 0 2006.285.08:55:44.67#ibcon#wrote, iclass 14, count 0 2006.285.08:55:44.67#ibcon#about to read 3, iclass 14, count 0 2006.285.08:55:44.70#ibcon#read 3, iclass 14, count 0 2006.285.08:55:44.70#ibcon#about to read 4, iclass 14, count 0 2006.285.08:55:44.70#ibcon#read 4, iclass 14, count 0 2006.285.08:55:44.70#ibcon#about to read 5, iclass 14, count 0 2006.285.08:55:44.70#ibcon#read 5, iclass 14, count 0 2006.285.08:55:44.70#ibcon#about to read 6, iclass 14, count 0 2006.285.08:55:44.70#ibcon#read 6, iclass 14, count 0 2006.285.08:55:44.70#ibcon#end of sib2, iclass 14, count 0 2006.285.08:55:44.70#ibcon#*after write, iclass 14, count 0 2006.285.08:55:44.70#ibcon#*before return 0, iclass 14, count 0 2006.285.08:55:44.70#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:55:44.70#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:55:44.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:55:44.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:55:44.70$vck44/valo=2,534.99 2006.285.08:55:44.70#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.08:55:44.70#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.08:55:44.70#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:44.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:55:44.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:55:44.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:55:44.70#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:55:44.70#ibcon#first serial, iclass 16, count 0 2006.285.08:55:44.70#ibcon#enter sib2, iclass 16, count 0 2006.285.08:55:44.70#ibcon#flushed, iclass 16, count 0 2006.285.08:55:44.70#ibcon#about to write, iclass 16, count 0 2006.285.08:55:44.70#ibcon#wrote, iclass 16, count 0 2006.285.08:55:44.70#ibcon#about to read 3, iclass 16, count 0 2006.285.08:55:44.72#ibcon#read 3, iclass 16, count 0 2006.285.08:55:44.72#ibcon#about to read 4, iclass 16, count 0 2006.285.08:55:44.72#ibcon#read 4, iclass 16, count 0 2006.285.08:55:44.72#ibcon#about to read 5, iclass 16, count 0 2006.285.08:55:44.72#ibcon#read 5, iclass 16, count 0 2006.285.08:55:44.72#ibcon#about to read 6, iclass 16, count 0 2006.285.08:55:44.72#ibcon#read 6, iclass 16, count 0 2006.285.08:55:44.72#ibcon#end of sib2, iclass 16, count 0 2006.285.08:55:44.72#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:55:44.72#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:55:44.72#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.08:55:44.72#ibcon#*before write, iclass 16, count 0 2006.285.08:55:44.72#ibcon#enter sib2, iclass 16, count 0 2006.285.08:55:44.72#ibcon#flushed, iclass 16, count 0 2006.285.08:55:44.72#ibcon#about to write, iclass 16, count 0 2006.285.08:55:44.72#ibcon#wrote, iclass 16, count 0 2006.285.08:55:44.72#ibcon#about to read 3, iclass 16, count 0 2006.285.08:55:44.76#ibcon#read 3, iclass 16, count 0 2006.285.08:55:44.76#ibcon#about to read 4, iclass 16, count 0 2006.285.08:55:44.76#ibcon#read 4, iclass 16, count 0 2006.285.08:55:44.76#ibcon#about to read 5, iclass 16, count 0 2006.285.08:55:44.76#ibcon#read 5, iclass 16, count 0 2006.285.08:55:44.76#ibcon#about to read 6, iclass 16, count 0 2006.285.08:55:44.76#ibcon#read 6, iclass 16, count 0 2006.285.08:55:44.76#ibcon#end of sib2, iclass 16, count 0 2006.285.08:55:44.76#ibcon#*after write, iclass 16, count 0 2006.285.08:55:44.76#ibcon#*before return 0, iclass 16, count 0 2006.285.08:55:44.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:55:44.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:55:44.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:55:44.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:55:44.76$vck44/va=2,6 2006.285.08:55:44.76#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.08:55:44.76#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.08:55:44.76#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:44.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:55:44.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:55:44.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:55:44.82#ibcon#enter wrdev, iclass 18, count 2 2006.285.08:55:44.82#ibcon#first serial, iclass 18, count 2 2006.285.08:55:44.82#ibcon#enter sib2, iclass 18, count 2 2006.285.08:55:44.82#ibcon#flushed, iclass 18, count 2 2006.285.08:55:44.82#ibcon#about to write, iclass 18, count 2 2006.285.08:55:44.82#ibcon#wrote, iclass 18, count 2 2006.285.08:55:44.82#ibcon#about to read 3, iclass 18, count 2 2006.285.08:55:44.84#ibcon#read 3, iclass 18, count 2 2006.285.08:55:44.84#ibcon#about to read 4, iclass 18, count 2 2006.285.08:55:44.84#ibcon#read 4, iclass 18, count 2 2006.285.08:55:44.84#ibcon#about to read 5, iclass 18, count 2 2006.285.08:55:44.84#ibcon#read 5, iclass 18, count 2 2006.285.08:55:44.84#ibcon#about to read 6, iclass 18, count 2 2006.285.08:55:44.84#ibcon#read 6, iclass 18, count 2 2006.285.08:55:44.84#ibcon#end of sib2, iclass 18, count 2 2006.285.08:55:44.84#ibcon#*mode == 0, iclass 18, count 2 2006.285.08:55:44.84#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.08:55:44.84#ibcon#[25=AT02-06\r\n] 2006.285.08:55:44.84#ibcon#*before write, iclass 18, count 2 2006.285.08:55:44.84#ibcon#enter sib2, iclass 18, count 2 2006.285.08:55:44.84#ibcon#flushed, iclass 18, count 2 2006.285.08:55:44.84#ibcon#about to write, iclass 18, count 2 2006.285.08:55:44.84#ibcon#wrote, iclass 18, count 2 2006.285.08:55:44.84#ibcon#about to read 3, iclass 18, count 2 2006.285.08:55:44.87#ibcon#read 3, iclass 18, count 2 2006.285.08:55:44.87#ibcon#about to read 4, iclass 18, count 2 2006.285.08:55:44.87#ibcon#read 4, iclass 18, count 2 2006.285.08:55:44.87#ibcon#about to read 5, iclass 18, count 2 2006.285.08:55:44.87#ibcon#read 5, iclass 18, count 2 2006.285.08:55:44.87#ibcon#about to read 6, iclass 18, count 2 2006.285.08:55:44.87#ibcon#read 6, iclass 18, count 2 2006.285.08:55:44.87#ibcon#end of sib2, iclass 18, count 2 2006.285.08:55:44.87#ibcon#*after write, iclass 18, count 2 2006.285.08:55:44.87#ibcon#*before return 0, iclass 18, count 2 2006.285.08:55:44.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:55:44.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:55:44.87#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.08:55:44.87#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:44.87#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:55:44.99#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:55:44.99#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:55:44.99#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:55:44.99#ibcon#first serial, iclass 18, count 0 2006.285.08:55:44.99#ibcon#enter sib2, iclass 18, count 0 2006.285.08:55:44.99#ibcon#flushed, iclass 18, count 0 2006.285.08:55:44.99#ibcon#about to write, iclass 18, count 0 2006.285.08:55:44.99#ibcon#wrote, iclass 18, count 0 2006.285.08:55:44.99#ibcon#about to read 3, iclass 18, count 0 2006.285.08:55:45.01#ibcon#read 3, iclass 18, count 0 2006.285.08:55:45.01#ibcon#about to read 4, iclass 18, count 0 2006.285.08:55:45.01#ibcon#read 4, iclass 18, count 0 2006.285.08:55:45.01#ibcon#about to read 5, iclass 18, count 0 2006.285.08:55:45.01#ibcon#read 5, iclass 18, count 0 2006.285.08:55:45.01#ibcon#about to read 6, iclass 18, count 0 2006.285.08:55:45.01#ibcon#read 6, iclass 18, count 0 2006.285.08:55:45.01#ibcon#end of sib2, iclass 18, count 0 2006.285.08:55:45.01#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:55:45.01#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:55:45.01#ibcon#[25=USB\r\n] 2006.285.08:55:45.01#ibcon#*before write, iclass 18, count 0 2006.285.08:55:45.01#ibcon#enter sib2, iclass 18, count 0 2006.285.08:55:45.01#ibcon#flushed, iclass 18, count 0 2006.285.08:55:45.01#ibcon#about to write, iclass 18, count 0 2006.285.08:55:45.01#ibcon#wrote, iclass 18, count 0 2006.285.08:55:45.01#ibcon#about to read 3, iclass 18, count 0 2006.285.08:55:45.04#ibcon#read 3, iclass 18, count 0 2006.285.08:55:45.04#ibcon#about to read 4, iclass 18, count 0 2006.285.08:55:45.04#ibcon#read 4, iclass 18, count 0 2006.285.08:55:45.04#ibcon#about to read 5, iclass 18, count 0 2006.285.08:55:45.04#ibcon#read 5, iclass 18, count 0 2006.285.08:55:45.04#ibcon#about to read 6, iclass 18, count 0 2006.285.08:55:45.04#ibcon#read 6, iclass 18, count 0 2006.285.08:55:45.04#ibcon#end of sib2, iclass 18, count 0 2006.285.08:55:45.04#ibcon#*after write, iclass 18, count 0 2006.285.08:55:45.04#ibcon#*before return 0, iclass 18, count 0 2006.285.08:55:45.04#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:55:45.04#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:55:45.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:55:45.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:55:45.04$vck44/valo=3,564.99 2006.285.08:55:45.04#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.08:55:45.04#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.08:55:45.04#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:45.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:55:45.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:55:45.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:55:45.04#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:55:45.05#ibcon#first serial, iclass 20, count 0 2006.285.08:55:45.05#ibcon#enter sib2, iclass 20, count 0 2006.285.08:55:45.05#ibcon#flushed, iclass 20, count 0 2006.285.08:55:45.05#ibcon#about to write, iclass 20, count 0 2006.285.08:55:45.05#ibcon#wrote, iclass 20, count 0 2006.285.08:55:45.05#ibcon#about to read 3, iclass 20, count 0 2006.285.08:55:45.06#ibcon#read 3, iclass 20, count 0 2006.285.08:55:45.06#ibcon#about to read 4, iclass 20, count 0 2006.285.08:55:45.06#ibcon#read 4, iclass 20, count 0 2006.285.08:55:45.06#ibcon#about to read 5, iclass 20, count 0 2006.285.08:55:45.06#ibcon#read 5, iclass 20, count 0 2006.285.08:55:45.06#ibcon#about to read 6, iclass 20, count 0 2006.285.08:55:45.06#ibcon#read 6, iclass 20, count 0 2006.285.08:55:45.06#ibcon#end of sib2, iclass 20, count 0 2006.285.08:55:45.06#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:55:45.06#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:55:45.06#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.08:55:45.06#ibcon#*before write, iclass 20, count 0 2006.285.08:55:45.06#ibcon#enter sib2, iclass 20, count 0 2006.285.08:55:45.06#ibcon#flushed, iclass 20, count 0 2006.285.08:55:45.06#ibcon#about to write, iclass 20, count 0 2006.285.08:55:45.06#ibcon#wrote, iclass 20, count 0 2006.285.08:55:45.06#ibcon#about to read 3, iclass 20, count 0 2006.285.08:55:45.10#ibcon#read 3, iclass 20, count 0 2006.285.08:55:45.10#ibcon#about to read 4, iclass 20, count 0 2006.285.08:55:45.10#ibcon#read 4, iclass 20, count 0 2006.285.08:55:45.10#ibcon#about to read 5, iclass 20, count 0 2006.285.08:55:45.10#ibcon#read 5, iclass 20, count 0 2006.285.08:55:45.10#ibcon#about to read 6, iclass 20, count 0 2006.285.08:55:45.10#ibcon#read 6, iclass 20, count 0 2006.285.08:55:45.10#ibcon#end of sib2, iclass 20, count 0 2006.285.08:55:45.10#ibcon#*after write, iclass 20, count 0 2006.285.08:55:45.10#ibcon#*before return 0, iclass 20, count 0 2006.285.08:55:45.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:55:45.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:55:45.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:55:45.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:55:45.10$vck44/va=3,7 2006.285.08:55:45.10#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.08:55:45.10#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.08:55:45.10#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:45.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:55:45.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:55:45.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:55:45.16#ibcon#enter wrdev, iclass 22, count 2 2006.285.08:55:45.16#ibcon#first serial, iclass 22, count 2 2006.285.08:55:45.16#ibcon#enter sib2, iclass 22, count 2 2006.285.08:55:45.16#ibcon#flushed, iclass 22, count 2 2006.285.08:55:45.16#ibcon#about to write, iclass 22, count 2 2006.285.08:55:45.16#ibcon#wrote, iclass 22, count 2 2006.285.08:55:45.16#ibcon#about to read 3, iclass 22, count 2 2006.285.08:55:45.18#ibcon#read 3, iclass 22, count 2 2006.285.08:55:45.18#ibcon#about to read 4, iclass 22, count 2 2006.285.08:55:45.18#ibcon#read 4, iclass 22, count 2 2006.285.08:55:45.18#ibcon#about to read 5, iclass 22, count 2 2006.285.08:55:45.18#ibcon#read 5, iclass 22, count 2 2006.285.08:55:45.18#ibcon#about to read 6, iclass 22, count 2 2006.285.08:55:45.18#ibcon#read 6, iclass 22, count 2 2006.285.08:55:45.18#ibcon#end of sib2, iclass 22, count 2 2006.285.08:55:45.18#ibcon#*mode == 0, iclass 22, count 2 2006.285.08:55:45.18#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.08:55:45.18#ibcon#[25=AT03-07\r\n] 2006.285.08:55:45.18#ibcon#*before write, iclass 22, count 2 2006.285.08:55:45.18#ibcon#enter sib2, iclass 22, count 2 2006.285.08:55:45.18#ibcon#flushed, iclass 22, count 2 2006.285.08:55:45.18#ibcon#about to write, iclass 22, count 2 2006.285.08:55:45.18#ibcon#wrote, iclass 22, count 2 2006.285.08:55:45.18#ibcon#about to read 3, iclass 22, count 2 2006.285.08:55:45.21#ibcon#read 3, iclass 22, count 2 2006.285.08:55:45.21#ibcon#about to read 4, iclass 22, count 2 2006.285.08:55:45.21#ibcon#read 4, iclass 22, count 2 2006.285.08:55:45.21#ibcon#about to read 5, iclass 22, count 2 2006.285.08:55:45.21#ibcon#read 5, iclass 22, count 2 2006.285.08:55:45.21#ibcon#about to read 6, iclass 22, count 2 2006.285.08:55:45.21#ibcon#read 6, iclass 22, count 2 2006.285.08:55:45.21#ibcon#end of sib2, iclass 22, count 2 2006.285.08:55:45.21#ibcon#*after write, iclass 22, count 2 2006.285.08:55:45.21#ibcon#*before return 0, iclass 22, count 2 2006.285.08:55:45.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:55:45.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:55:45.21#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.08:55:45.21#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:45.21#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:55:45.33#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:55:45.33#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:55:45.33#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:55:45.33#ibcon#first serial, iclass 22, count 0 2006.285.08:55:45.33#ibcon#enter sib2, iclass 22, count 0 2006.285.08:55:45.33#ibcon#flushed, iclass 22, count 0 2006.285.08:55:45.33#ibcon#about to write, iclass 22, count 0 2006.285.08:55:45.33#ibcon#wrote, iclass 22, count 0 2006.285.08:55:45.33#ibcon#about to read 3, iclass 22, count 0 2006.285.08:55:45.35#ibcon#read 3, iclass 22, count 0 2006.285.08:55:45.35#ibcon#about to read 4, iclass 22, count 0 2006.285.08:55:45.35#ibcon#read 4, iclass 22, count 0 2006.285.08:55:45.35#ibcon#about to read 5, iclass 22, count 0 2006.285.08:55:45.35#ibcon#read 5, iclass 22, count 0 2006.285.08:55:45.35#ibcon#about to read 6, iclass 22, count 0 2006.285.08:55:45.35#ibcon#read 6, iclass 22, count 0 2006.285.08:55:45.35#ibcon#end of sib2, iclass 22, count 0 2006.285.08:55:45.35#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:55:45.35#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:55:45.35#ibcon#[25=USB\r\n] 2006.285.08:55:45.35#ibcon#*before write, iclass 22, count 0 2006.285.08:55:45.35#ibcon#enter sib2, iclass 22, count 0 2006.285.08:55:45.35#ibcon#flushed, iclass 22, count 0 2006.285.08:55:45.35#ibcon#about to write, iclass 22, count 0 2006.285.08:55:45.35#ibcon#wrote, iclass 22, count 0 2006.285.08:55:45.35#ibcon#about to read 3, iclass 22, count 0 2006.285.08:55:45.38#ibcon#read 3, iclass 22, count 0 2006.285.08:55:45.38#ibcon#about to read 4, iclass 22, count 0 2006.285.08:55:45.38#ibcon#read 4, iclass 22, count 0 2006.285.08:55:45.38#ibcon#about to read 5, iclass 22, count 0 2006.285.08:55:45.38#ibcon#read 5, iclass 22, count 0 2006.285.08:55:45.38#ibcon#about to read 6, iclass 22, count 0 2006.285.08:55:45.38#ibcon#read 6, iclass 22, count 0 2006.285.08:55:45.38#ibcon#end of sib2, iclass 22, count 0 2006.285.08:55:45.38#ibcon#*after write, iclass 22, count 0 2006.285.08:55:45.38#ibcon#*before return 0, iclass 22, count 0 2006.285.08:55:45.38#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:55:45.38#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:55:45.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:55:45.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:55:45.38$vck44/valo=4,624.99 2006.285.08:55:45.38#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.08:55:45.38#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.08:55:45.38#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:45.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:55:45.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:55:45.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:55:45.38#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:55:45.38#ibcon#first serial, iclass 24, count 0 2006.285.08:55:45.38#ibcon#enter sib2, iclass 24, count 0 2006.285.08:55:45.38#ibcon#flushed, iclass 24, count 0 2006.285.08:55:45.38#ibcon#about to write, iclass 24, count 0 2006.285.08:55:45.38#ibcon#wrote, iclass 24, count 0 2006.285.08:55:45.38#ibcon#about to read 3, iclass 24, count 0 2006.285.08:55:45.40#ibcon#read 3, iclass 24, count 0 2006.285.08:55:45.40#ibcon#about to read 4, iclass 24, count 0 2006.285.08:55:45.40#ibcon#read 4, iclass 24, count 0 2006.285.08:55:45.40#ibcon#about to read 5, iclass 24, count 0 2006.285.08:55:45.40#ibcon#read 5, iclass 24, count 0 2006.285.08:55:45.40#ibcon#about to read 6, iclass 24, count 0 2006.285.08:55:45.40#ibcon#read 6, iclass 24, count 0 2006.285.08:55:45.40#ibcon#end of sib2, iclass 24, count 0 2006.285.08:55:45.40#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:55:45.40#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:55:45.40#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.08:55:45.40#ibcon#*before write, iclass 24, count 0 2006.285.08:55:45.40#ibcon#enter sib2, iclass 24, count 0 2006.285.08:55:45.40#ibcon#flushed, iclass 24, count 0 2006.285.08:55:45.40#ibcon#about to write, iclass 24, count 0 2006.285.08:55:45.40#ibcon#wrote, iclass 24, count 0 2006.285.08:55:45.40#ibcon#about to read 3, iclass 24, count 0 2006.285.08:55:45.44#ibcon#read 3, iclass 24, count 0 2006.285.08:55:45.44#ibcon#about to read 4, iclass 24, count 0 2006.285.08:55:45.44#ibcon#read 4, iclass 24, count 0 2006.285.08:55:45.44#ibcon#about to read 5, iclass 24, count 0 2006.285.08:55:45.44#ibcon#read 5, iclass 24, count 0 2006.285.08:55:45.44#ibcon#about to read 6, iclass 24, count 0 2006.285.08:55:45.44#ibcon#read 6, iclass 24, count 0 2006.285.08:55:45.44#ibcon#end of sib2, iclass 24, count 0 2006.285.08:55:45.44#ibcon#*after write, iclass 24, count 0 2006.285.08:55:45.44#ibcon#*before return 0, iclass 24, count 0 2006.285.08:55:45.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:55:45.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:55:45.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:55:45.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:55:45.44$vck44/va=4,6 2006.285.08:55:45.44#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.08:55:45.44#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.08:55:45.44#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:45.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:55:45.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:55:45.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:55:45.50#ibcon#enter wrdev, iclass 26, count 2 2006.285.08:55:45.50#ibcon#first serial, iclass 26, count 2 2006.285.08:55:45.50#ibcon#enter sib2, iclass 26, count 2 2006.285.08:55:45.50#ibcon#flushed, iclass 26, count 2 2006.285.08:55:45.50#ibcon#about to write, iclass 26, count 2 2006.285.08:55:45.50#ibcon#wrote, iclass 26, count 2 2006.285.08:55:45.50#ibcon#about to read 3, iclass 26, count 2 2006.285.08:55:45.52#ibcon#read 3, iclass 26, count 2 2006.285.08:55:45.52#ibcon#about to read 4, iclass 26, count 2 2006.285.08:55:45.52#ibcon#read 4, iclass 26, count 2 2006.285.08:55:45.52#ibcon#about to read 5, iclass 26, count 2 2006.285.08:55:45.52#ibcon#read 5, iclass 26, count 2 2006.285.08:55:45.52#ibcon#about to read 6, iclass 26, count 2 2006.285.08:55:45.52#ibcon#read 6, iclass 26, count 2 2006.285.08:55:45.52#ibcon#end of sib2, iclass 26, count 2 2006.285.08:55:45.52#ibcon#*mode == 0, iclass 26, count 2 2006.285.08:55:45.52#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.08:55:45.52#ibcon#[25=AT04-06\r\n] 2006.285.08:55:45.52#ibcon#*before write, iclass 26, count 2 2006.285.08:55:45.52#ibcon#enter sib2, iclass 26, count 2 2006.285.08:55:45.52#ibcon#flushed, iclass 26, count 2 2006.285.08:55:45.52#ibcon#about to write, iclass 26, count 2 2006.285.08:55:45.52#ibcon#wrote, iclass 26, count 2 2006.285.08:55:45.52#ibcon#about to read 3, iclass 26, count 2 2006.285.08:55:45.55#ibcon#read 3, iclass 26, count 2 2006.285.08:55:45.55#ibcon#about to read 4, iclass 26, count 2 2006.285.08:55:45.55#ibcon#read 4, iclass 26, count 2 2006.285.08:55:45.55#ibcon#about to read 5, iclass 26, count 2 2006.285.08:55:45.55#ibcon#read 5, iclass 26, count 2 2006.285.08:55:45.55#ibcon#about to read 6, iclass 26, count 2 2006.285.08:55:45.55#ibcon#read 6, iclass 26, count 2 2006.285.08:55:45.55#ibcon#end of sib2, iclass 26, count 2 2006.285.08:55:45.55#ibcon#*after write, iclass 26, count 2 2006.285.08:55:45.55#ibcon#*before return 0, iclass 26, count 2 2006.285.08:55:45.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:55:45.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:55:45.55#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.08:55:45.55#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:45.55#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:55:45.67#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:55:45.67#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:55:45.67#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:55:45.67#ibcon#first serial, iclass 26, count 0 2006.285.08:55:45.67#ibcon#enter sib2, iclass 26, count 0 2006.285.08:55:45.67#ibcon#flushed, iclass 26, count 0 2006.285.08:55:45.67#ibcon#about to write, iclass 26, count 0 2006.285.08:55:45.67#ibcon#wrote, iclass 26, count 0 2006.285.08:55:45.67#ibcon#about to read 3, iclass 26, count 0 2006.285.08:55:45.69#ibcon#read 3, iclass 26, count 0 2006.285.08:55:45.69#ibcon#about to read 4, iclass 26, count 0 2006.285.08:55:45.69#ibcon#read 4, iclass 26, count 0 2006.285.08:55:45.69#ibcon#about to read 5, iclass 26, count 0 2006.285.08:55:45.69#ibcon#read 5, iclass 26, count 0 2006.285.08:55:45.69#ibcon#about to read 6, iclass 26, count 0 2006.285.08:55:45.69#ibcon#read 6, iclass 26, count 0 2006.285.08:55:45.69#ibcon#end of sib2, iclass 26, count 0 2006.285.08:55:45.69#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:55:45.69#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:55:45.69#ibcon#[25=USB\r\n] 2006.285.08:55:45.69#ibcon#*before write, iclass 26, count 0 2006.285.08:55:45.69#ibcon#enter sib2, iclass 26, count 0 2006.285.08:55:45.69#ibcon#flushed, iclass 26, count 0 2006.285.08:55:45.69#ibcon#about to write, iclass 26, count 0 2006.285.08:55:45.69#ibcon#wrote, iclass 26, count 0 2006.285.08:55:45.69#ibcon#about to read 3, iclass 26, count 0 2006.285.08:55:45.72#ibcon#read 3, iclass 26, count 0 2006.285.08:55:45.72#ibcon#about to read 4, iclass 26, count 0 2006.285.08:55:45.72#ibcon#read 4, iclass 26, count 0 2006.285.08:55:45.72#ibcon#about to read 5, iclass 26, count 0 2006.285.08:55:45.72#ibcon#read 5, iclass 26, count 0 2006.285.08:55:45.72#ibcon#about to read 6, iclass 26, count 0 2006.285.08:55:45.72#ibcon#read 6, iclass 26, count 0 2006.285.08:55:45.72#ibcon#end of sib2, iclass 26, count 0 2006.285.08:55:45.72#ibcon#*after write, iclass 26, count 0 2006.285.08:55:45.72#ibcon#*before return 0, iclass 26, count 0 2006.285.08:55:45.72#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:55:45.72#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:55:45.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:55:45.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:55:45.72$vck44/valo=5,734.99 2006.285.08:55:45.72#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.08:55:45.72#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.08:55:45.72#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:45.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:55:45.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:55:45.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:55:45.72#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:55:45.72#ibcon#first serial, iclass 28, count 0 2006.285.08:55:45.72#ibcon#enter sib2, iclass 28, count 0 2006.285.08:55:45.72#ibcon#flushed, iclass 28, count 0 2006.285.08:55:45.72#ibcon#about to write, iclass 28, count 0 2006.285.08:55:45.72#ibcon#wrote, iclass 28, count 0 2006.285.08:55:45.72#ibcon#about to read 3, iclass 28, count 0 2006.285.08:55:45.74#ibcon#read 3, iclass 28, count 0 2006.285.08:55:45.74#ibcon#about to read 4, iclass 28, count 0 2006.285.08:55:45.74#ibcon#read 4, iclass 28, count 0 2006.285.08:55:45.74#ibcon#about to read 5, iclass 28, count 0 2006.285.08:55:45.74#ibcon#read 5, iclass 28, count 0 2006.285.08:55:45.74#ibcon#about to read 6, iclass 28, count 0 2006.285.08:55:45.74#ibcon#read 6, iclass 28, count 0 2006.285.08:55:45.74#ibcon#end of sib2, iclass 28, count 0 2006.285.08:55:45.74#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:55:45.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:55:45.74#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.08:55:45.74#ibcon#*before write, iclass 28, count 0 2006.285.08:55:45.74#ibcon#enter sib2, iclass 28, count 0 2006.285.08:55:45.74#ibcon#flushed, iclass 28, count 0 2006.285.08:55:45.74#ibcon#about to write, iclass 28, count 0 2006.285.08:55:45.74#ibcon#wrote, iclass 28, count 0 2006.285.08:55:45.74#ibcon#about to read 3, iclass 28, count 0 2006.285.08:55:45.78#ibcon#read 3, iclass 28, count 0 2006.285.08:55:45.78#ibcon#about to read 4, iclass 28, count 0 2006.285.08:55:45.78#ibcon#read 4, iclass 28, count 0 2006.285.08:55:45.78#ibcon#about to read 5, iclass 28, count 0 2006.285.08:55:45.78#ibcon#read 5, iclass 28, count 0 2006.285.08:55:45.78#ibcon#about to read 6, iclass 28, count 0 2006.285.08:55:45.78#ibcon#read 6, iclass 28, count 0 2006.285.08:55:45.78#ibcon#end of sib2, iclass 28, count 0 2006.285.08:55:45.78#ibcon#*after write, iclass 28, count 0 2006.285.08:55:45.78#ibcon#*before return 0, iclass 28, count 0 2006.285.08:55:45.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:55:45.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:55:45.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:55:45.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:55:45.78$vck44/va=5,3 2006.285.08:55:45.78#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.08:55:45.78#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.08:55:45.78#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:45.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:55:45.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:55:45.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:55:45.84#ibcon#enter wrdev, iclass 30, count 2 2006.285.08:55:45.84#ibcon#first serial, iclass 30, count 2 2006.285.08:55:45.84#ibcon#enter sib2, iclass 30, count 2 2006.285.08:55:45.84#ibcon#flushed, iclass 30, count 2 2006.285.08:55:45.84#ibcon#about to write, iclass 30, count 2 2006.285.08:55:45.84#ibcon#wrote, iclass 30, count 2 2006.285.08:55:45.84#ibcon#about to read 3, iclass 30, count 2 2006.285.08:55:45.86#ibcon#read 3, iclass 30, count 2 2006.285.08:55:45.86#ibcon#about to read 4, iclass 30, count 2 2006.285.08:55:45.86#ibcon#read 4, iclass 30, count 2 2006.285.08:55:45.86#ibcon#about to read 5, iclass 30, count 2 2006.285.08:55:45.86#ibcon#read 5, iclass 30, count 2 2006.285.08:55:45.86#ibcon#about to read 6, iclass 30, count 2 2006.285.08:55:45.86#ibcon#read 6, iclass 30, count 2 2006.285.08:55:45.86#ibcon#end of sib2, iclass 30, count 2 2006.285.08:55:45.86#ibcon#*mode == 0, iclass 30, count 2 2006.285.08:55:45.86#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.08:55:45.86#ibcon#[25=AT05-03\r\n] 2006.285.08:55:45.86#ibcon#*before write, iclass 30, count 2 2006.285.08:55:45.86#ibcon#enter sib2, iclass 30, count 2 2006.285.08:55:45.86#ibcon#flushed, iclass 30, count 2 2006.285.08:55:45.86#ibcon#about to write, iclass 30, count 2 2006.285.08:55:45.86#ibcon#wrote, iclass 30, count 2 2006.285.08:55:45.86#ibcon#about to read 3, iclass 30, count 2 2006.285.08:55:45.89#ibcon#read 3, iclass 30, count 2 2006.285.08:55:45.89#ibcon#about to read 4, iclass 30, count 2 2006.285.08:55:45.89#ibcon#read 4, iclass 30, count 2 2006.285.08:55:45.89#ibcon#about to read 5, iclass 30, count 2 2006.285.08:55:45.89#ibcon#read 5, iclass 30, count 2 2006.285.08:55:45.89#ibcon#about to read 6, iclass 30, count 2 2006.285.08:55:45.89#ibcon#read 6, iclass 30, count 2 2006.285.08:55:45.89#ibcon#end of sib2, iclass 30, count 2 2006.285.08:55:45.89#ibcon#*after write, iclass 30, count 2 2006.285.08:55:45.89#ibcon#*before return 0, iclass 30, count 2 2006.285.08:55:45.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:55:45.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:55:45.89#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.08:55:45.89#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:45.89#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:55:46.01#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:55:46.01#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:55:46.01#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:55:46.01#ibcon#first serial, iclass 30, count 0 2006.285.08:55:46.01#ibcon#enter sib2, iclass 30, count 0 2006.285.08:55:46.01#ibcon#flushed, iclass 30, count 0 2006.285.08:55:46.01#ibcon#about to write, iclass 30, count 0 2006.285.08:55:46.01#ibcon#wrote, iclass 30, count 0 2006.285.08:55:46.01#ibcon#about to read 3, iclass 30, count 0 2006.285.08:55:46.03#ibcon#read 3, iclass 30, count 0 2006.285.08:55:46.03#ibcon#about to read 4, iclass 30, count 0 2006.285.08:55:46.03#ibcon#read 4, iclass 30, count 0 2006.285.08:55:46.03#ibcon#about to read 5, iclass 30, count 0 2006.285.08:55:46.03#ibcon#read 5, iclass 30, count 0 2006.285.08:55:46.03#ibcon#about to read 6, iclass 30, count 0 2006.285.08:55:46.03#ibcon#read 6, iclass 30, count 0 2006.285.08:55:46.03#ibcon#end of sib2, iclass 30, count 0 2006.285.08:55:46.03#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:55:46.03#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:55:46.03#ibcon#[25=USB\r\n] 2006.285.08:55:46.03#ibcon#*before write, iclass 30, count 0 2006.285.08:55:46.03#ibcon#enter sib2, iclass 30, count 0 2006.285.08:55:46.03#ibcon#flushed, iclass 30, count 0 2006.285.08:55:46.03#ibcon#about to write, iclass 30, count 0 2006.285.08:55:46.03#ibcon#wrote, iclass 30, count 0 2006.285.08:55:46.03#ibcon#about to read 3, iclass 30, count 0 2006.285.08:55:46.06#ibcon#read 3, iclass 30, count 0 2006.285.08:55:46.06#ibcon#about to read 4, iclass 30, count 0 2006.285.08:55:46.06#ibcon#read 4, iclass 30, count 0 2006.285.08:55:46.06#ibcon#about to read 5, iclass 30, count 0 2006.285.08:55:46.06#ibcon#read 5, iclass 30, count 0 2006.285.08:55:46.06#ibcon#about to read 6, iclass 30, count 0 2006.285.08:55:46.06#ibcon#read 6, iclass 30, count 0 2006.285.08:55:46.06#ibcon#end of sib2, iclass 30, count 0 2006.285.08:55:46.06#ibcon#*after write, iclass 30, count 0 2006.285.08:55:46.06#ibcon#*before return 0, iclass 30, count 0 2006.285.08:55:46.06#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:55:46.06#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:55:46.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:55:46.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:55:46.06$vck44/valo=6,814.99 2006.285.08:55:46.06#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.08:55:46.06#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.08:55:46.06#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:46.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:55:46.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:55:46.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:55:46.06#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:55:46.06#ibcon#first serial, iclass 32, count 0 2006.285.08:55:46.06#ibcon#enter sib2, iclass 32, count 0 2006.285.08:55:46.06#ibcon#flushed, iclass 32, count 0 2006.285.08:55:46.06#ibcon#about to write, iclass 32, count 0 2006.285.08:55:46.06#ibcon#wrote, iclass 32, count 0 2006.285.08:55:46.06#ibcon#about to read 3, iclass 32, count 0 2006.285.08:55:46.08#ibcon#read 3, iclass 32, count 0 2006.285.08:55:46.08#ibcon#about to read 4, iclass 32, count 0 2006.285.08:55:46.08#ibcon#read 4, iclass 32, count 0 2006.285.08:55:46.08#ibcon#about to read 5, iclass 32, count 0 2006.285.08:55:46.08#ibcon#read 5, iclass 32, count 0 2006.285.08:55:46.08#ibcon#about to read 6, iclass 32, count 0 2006.285.08:55:46.08#ibcon#read 6, iclass 32, count 0 2006.285.08:55:46.08#ibcon#end of sib2, iclass 32, count 0 2006.285.08:55:46.08#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:55:46.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:55:46.08#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.08:55:46.08#ibcon#*before write, iclass 32, count 0 2006.285.08:55:46.08#ibcon#enter sib2, iclass 32, count 0 2006.285.08:55:46.08#ibcon#flushed, iclass 32, count 0 2006.285.08:55:46.08#ibcon#about to write, iclass 32, count 0 2006.285.08:55:46.08#ibcon#wrote, iclass 32, count 0 2006.285.08:55:46.08#ibcon#about to read 3, iclass 32, count 0 2006.285.08:55:46.12#ibcon#read 3, iclass 32, count 0 2006.285.08:55:46.12#ibcon#about to read 4, iclass 32, count 0 2006.285.08:55:46.12#ibcon#read 4, iclass 32, count 0 2006.285.08:55:46.12#ibcon#about to read 5, iclass 32, count 0 2006.285.08:55:46.12#ibcon#read 5, iclass 32, count 0 2006.285.08:55:46.12#ibcon#about to read 6, iclass 32, count 0 2006.285.08:55:46.12#ibcon#read 6, iclass 32, count 0 2006.285.08:55:46.12#ibcon#end of sib2, iclass 32, count 0 2006.285.08:55:46.12#ibcon#*after write, iclass 32, count 0 2006.285.08:55:46.12#ibcon#*before return 0, iclass 32, count 0 2006.285.08:55:46.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:55:46.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:55:46.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:55:46.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:55:46.12$vck44/va=6,4 2006.285.08:55:46.12#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.08:55:46.12#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.08:55:46.12#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:46.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:55:46.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:55:46.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:55:46.18#ibcon#enter wrdev, iclass 34, count 2 2006.285.08:55:46.18#ibcon#first serial, iclass 34, count 2 2006.285.08:55:46.18#ibcon#enter sib2, iclass 34, count 2 2006.285.08:55:46.18#ibcon#flushed, iclass 34, count 2 2006.285.08:55:46.18#ibcon#about to write, iclass 34, count 2 2006.285.08:55:46.18#ibcon#wrote, iclass 34, count 2 2006.285.08:55:46.18#ibcon#about to read 3, iclass 34, count 2 2006.285.08:55:46.20#ibcon#read 3, iclass 34, count 2 2006.285.08:55:46.20#ibcon#about to read 4, iclass 34, count 2 2006.285.08:55:46.20#ibcon#read 4, iclass 34, count 2 2006.285.08:55:46.20#ibcon#about to read 5, iclass 34, count 2 2006.285.08:55:46.20#ibcon#read 5, iclass 34, count 2 2006.285.08:55:46.20#ibcon#about to read 6, iclass 34, count 2 2006.285.08:55:46.20#ibcon#read 6, iclass 34, count 2 2006.285.08:55:46.20#ibcon#end of sib2, iclass 34, count 2 2006.285.08:55:46.20#ibcon#*mode == 0, iclass 34, count 2 2006.285.08:55:46.20#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.08:55:46.20#ibcon#[25=AT06-04\r\n] 2006.285.08:55:46.20#ibcon#*before write, iclass 34, count 2 2006.285.08:55:46.20#ibcon#enter sib2, iclass 34, count 2 2006.285.08:55:46.20#ibcon#flushed, iclass 34, count 2 2006.285.08:55:46.20#ibcon#about to write, iclass 34, count 2 2006.285.08:55:46.20#ibcon#wrote, iclass 34, count 2 2006.285.08:55:46.20#ibcon#about to read 3, iclass 34, count 2 2006.285.08:55:46.23#ibcon#read 3, iclass 34, count 2 2006.285.08:55:46.23#ibcon#about to read 4, iclass 34, count 2 2006.285.08:55:46.23#ibcon#read 4, iclass 34, count 2 2006.285.08:55:46.23#ibcon#about to read 5, iclass 34, count 2 2006.285.08:55:46.23#ibcon#read 5, iclass 34, count 2 2006.285.08:55:46.23#ibcon#about to read 6, iclass 34, count 2 2006.285.08:55:46.23#ibcon#read 6, iclass 34, count 2 2006.285.08:55:46.23#ibcon#end of sib2, iclass 34, count 2 2006.285.08:55:46.23#ibcon#*after write, iclass 34, count 2 2006.285.08:55:46.23#ibcon#*before return 0, iclass 34, count 2 2006.285.08:55:46.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:55:46.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:55:46.23#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.08:55:46.23#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:46.23#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:55:46.35#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:55:46.35#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:55:46.35#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:55:46.35#ibcon#first serial, iclass 34, count 0 2006.285.08:55:46.35#ibcon#enter sib2, iclass 34, count 0 2006.285.08:55:46.35#ibcon#flushed, iclass 34, count 0 2006.285.08:55:46.35#ibcon#about to write, iclass 34, count 0 2006.285.08:55:46.35#ibcon#wrote, iclass 34, count 0 2006.285.08:55:46.35#ibcon#about to read 3, iclass 34, count 0 2006.285.08:55:46.37#ibcon#read 3, iclass 34, count 0 2006.285.08:55:46.37#ibcon#about to read 4, iclass 34, count 0 2006.285.08:55:46.37#ibcon#read 4, iclass 34, count 0 2006.285.08:55:46.37#ibcon#about to read 5, iclass 34, count 0 2006.285.08:55:46.37#ibcon#read 5, iclass 34, count 0 2006.285.08:55:46.37#ibcon#about to read 6, iclass 34, count 0 2006.285.08:55:46.37#ibcon#read 6, iclass 34, count 0 2006.285.08:55:46.37#ibcon#end of sib2, iclass 34, count 0 2006.285.08:55:46.37#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:55:46.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:55:46.37#ibcon#[25=USB\r\n] 2006.285.08:55:46.37#ibcon#*before write, iclass 34, count 0 2006.285.08:55:46.37#ibcon#enter sib2, iclass 34, count 0 2006.285.08:55:46.37#ibcon#flushed, iclass 34, count 0 2006.285.08:55:46.37#ibcon#about to write, iclass 34, count 0 2006.285.08:55:46.37#ibcon#wrote, iclass 34, count 0 2006.285.08:55:46.37#ibcon#about to read 3, iclass 34, count 0 2006.285.08:55:46.40#ibcon#read 3, iclass 34, count 0 2006.285.08:55:46.40#ibcon#about to read 4, iclass 34, count 0 2006.285.08:55:46.40#ibcon#read 4, iclass 34, count 0 2006.285.08:55:46.40#ibcon#about to read 5, iclass 34, count 0 2006.285.08:55:46.40#ibcon#read 5, iclass 34, count 0 2006.285.08:55:46.40#ibcon#about to read 6, iclass 34, count 0 2006.285.08:55:46.40#ibcon#read 6, iclass 34, count 0 2006.285.08:55:46.40#ibcon#end of sib2, iclass 34, count 0 2006.285.08:55:46.40#ibcon#*after write, iclass 34, count 0 2006.285.08:55:46.40#ibcon#*before return 0, iclass 34, count 0 2006.285.08:55:46.40#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:55:46.40#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:55:46.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:55:46.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:55:46.40$vck44/valo=7,864.99 2006.285.08:55:46.40#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.08:55:46.40#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.08:55:46.40#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:46.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:55:46.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:55:46.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:55:46.40#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:55:46.40#ibcon#first serial, iclass 36, count 0 2006.285.08:55:46.40#ibcon#enter sib2, iclass 36, count 0 2006.285.08:55:46.40#ibcon#flushed, iclass 36, count 0 2006.285.08:55:46.40#ibcon#about to write, iclass 36, count 0 2006.285.08:55:46.40#ibcon#wrote, iclass 36, count 0 2006.285.08:55:46.40#ibcon#about to read 3, iclass 36, count 0 2006.285.08:55:46.42#ibcon#read 3, iclass 36, count 0 2006.285.08:55:46.42#ibcon#about to read 4, iclass 36, count 0 2006.285.08:55:46.42#ibcon#read 4, iclass 36, count 0 2006.285.08:55:46.42#ibcon#about to read 5, iclass 36, count 0 2006.285.08:55:46.42#ibcon#read 5, iclass 36, count 0 2006.285.08:55:46.42#ibcon#about to read 6, iclass 36, count 0 2006.285.08:55:46.42#ibcon#read 6, iclass 36, count 0 2006.285.08:55:46.42#ibcon#end of sib2, iclass 36, count 0 2006.285.08:55:46.42#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:55:46.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:55:46.42#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.08:55:46.42#ibcon#*before write, iclass 36, count 0 2006.285.08:55:46.42#ibcon#enter sib2, iclass 36, count 0 2006.285.08:55:46.42#ibcon#flushed, iclass 36, count 0 2006.285.08:55:46.42#ibcon#about to write, iclass 36, count 0 2006.285.08:55:46.42#ibcon#wrote, iclass 36, count 0 2006.285.08:55:46.42#ibcon#about to read 3, iclass 36, count 0 2006.285.08:55:46.46#ibcon#read 3, iclass 36, count 0 2006.285.08:55:46.46#ibcon#about to read 4, iclass 36, count 0 2006.285.08:55:46.46#ibcon#read 4, iclass 36, count 0 2006.285.08:55:46.46#ibcon#about to read 5, iclass 36, count 0 2006.285.08:55:46.46#ibcon#read 5, iclass 36, count 0 2006.285.08:55:46.46#ibcon#about to read 6, iclass 36, count 0 2006.285.08:55:46.46#ibcon#read 6, iclass 36, count 0 2006.285.08:55:46.46#ibcon#end of sib2, iclass 36, count 0 2006.285.08:55:46.46#ibcon#*after write, iclass 36, count 0 2006.285.08:55:46.46#ibcon#*before return 0, iclass 36, count 0 2006.285.08:55:46.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:55:46.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:55:46.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:55:46.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:55:46.46$vck44/va=7,4 2006.285.08:55:46.46#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.08:55:46.46#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.08:55:46.46#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:46.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:55:46.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:55:46.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:55:46.52#ibcon#enter wrdev, iclass 38, count 2 2006.285.08:55:46.52#ibcon#first serial, iclass 38, count 2 2006.285.08:55:46.52#ibcon#enter sib2, iclass 38, count 2 2006.285.08:55:46.52#ibcon#flushed, iclass 38, count 2 2006.285.08:55:46.52#ibcon#about to write, iclass 38, count 2 2006.285.08:55:46.52#ibcon#wrote, iclass 38, count 2 2006.285.08:55:46.52#ibcon#about to read 3, iclass 38, count 2 2006.285.08:55:46.54#ibcon#read 3, iclass 38, count 2 2006.285.08:55:46.54#ibcon#about to read 4, iclass 38, count 2 2006.285.08:55:46.54#ibcon#read 4, iclass 38, count 2 2006.285.08:55:46.54#ibcon#about to read 5, iclass 38, count 2 2006.285.08:55:46.54#ibcon#read 5, iclass 38, count 2 2006.285.08:55:46.54#ibcon#about to read 6, iclass 38, count 2 2006.285.08:55:46.54#ibcon#read 6, iclass 38, count 2 2006.285.08:55:46.54#ibcon#end of sib2, iclass 38, count 2 2006.285.08:55:46.54#ibcon#*mode == 0, iclass 38, count 2 2006.285.08:55:46.54#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.08:55:46.54#ibcon#[25=AT07-04\r\n] 2006.285.08:55:46.54#ibcon#*before write, iclass 38, count 2 2006.285.08:55:46.54#ibcon#enter sib2, iclass 38, count 2 2006.285.08:55:46.54#ibcon#flushed, iclass 38, count 2 2006.285.08:55:46.54#ibcon#about to write, iclass 38, count 2 2006.285.08:55:46.54#ibcon#wrote, iclass 38, count 2 2006.285.08:55:46.54#ibcon#about to read 3, iclass 38, count 2 2006.285.08:55:46.57#ibcon#read 3, iclass 38, count 2 2006.285.08:55:46.57#ibcon#about to read 4, iclass 38, count 2 2006.285.08:55:46.57#ibcon#read 4, iclass 38, count 2 2006.285.08:55:46.57#ibcon#about to read 5, iclass 38, count 2 2006.285.08:55:46.57#ibcon#read 5, iclass 38, count 2 2006.285.08:55:46.57#ibcon#about to read 6, iclass 38, count 2 2006.285.08:55:46.57#ibcon#read 6, iclass 38, count 2 2006.285.08:55:46.57#ibcon#end of sib2, iclass 38, count 2 2006.285.08:55:46.57#ibcon#*after write, iclass 38, count 2 2006.285.08:55:46.57#ibcon#*before return 0, iclass 38, count 2 2006.285.08:55:46.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:55:46.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:55:46.57#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.08:55:46.57#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:46.57#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:55:46.69#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:55:46.69#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:55:46.69#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:55:46.69#ibcon#first serial, iclass 38, count 0 2006.285.08:55:46.69#ibcon#enter sib2, iclass 38, count 0 2006.285.08:55:46.69#ibcon#flushed, iclass 38, count 0 2006.285.08:55:46.69#ibcon#about to write, iclass 38, count 0 2006.285.08:55:46.69#ibcon#wrote, iclass 38, count 0 2006.285.08:55:46.69#ibcon#about to read 3, iclass 38, count 0 2006.285.08:55:46.71#ibcon#read 3, iclass 38, count 0 2006.285.08:55:46.71#ibcon#about to read 4, iclass 38, count 0 2006.285.08:55:46.71#ibcon#read 4, iclass 38, count 0 2006.285.08:55:46.71#ibcon#about to read 5, iclass 38, count 0 2006.285.08:55:46.71#ibcon#read 5, iclass 38, count 0 2006.285.08:55:46.71#ibcon#about to read 6, iclass 38, count 0 2006.285.08:55:46.71#ibcon#read 6, iclass 38, count 0 2006.285.08:55:46.71#ibcon#end of sib2, iclass 38, count 0 2006.285.08:55:46.71#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:55:46.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:55:46.71#ibcon#[25=USB\r\n] 2006.285.08:55:46.71#ibcon#*before write, iclass 38, count 0 2006.285.08:55:46.71#ibcon#enter sib2, iclass 38, count 0 2006.285.08:55:46.71#ibcon#flushed, iclass 38, count 0 2006.285.08:55:46.71#ibcon#about to write, iclass 38, count 0 2006.285.08:55:46.71#ibcon#wrote, iclass 38, count 0 2006.285.08:55:46.71#ibcon#about to read 3, iclass 38, count 0 2006.285.08:55:46.74#ibcon#read 3, iclass 38, count 0 2006.285.08:55:46.74#ibcon#about to read 4, iclass 38, count 0 2006.285.08:55:46.74#ibcon#read 4, iclass 38, count 0 2006.285.08:55:46.74#ibcon#about to read 5, iclass 38, count 0 2006.285.08:55:46.74#ibcon#read 5, iclass 38, count 0 2006.285.08:55:46.74#ibcon#about to read 6, iclass 38, count 0 2006.285.08:55:46.74#ibcon#read 6, iclass 38, count 0 2006.285.08:55:46.74#ibcon#end of sib2, iclass 38, count 0 2006.285.08:55:46.74#ibcon#*after write, iclass 38, count 0 2006.285.08:55:46.74#ibcon#*before return 0, iclass 38, count 0 2006.285.08:55:46.74#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:55:46.74#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:55:46.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:55:46.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:55:46.74$vck44/valo=8,884.99 2006.285.08:55:46.74#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.08:55:46.74#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.08:55:46.74#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:46.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:55:46.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:55:46.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:55:46.74#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:55:46.74#ibcon#first serial, iclass 40, count 0 2006.285.08:55:46.74#ibcon#enter sib2, iclass 40, count 0 2006.285.08:55:46.74#ibcon#flushed, iclass 40, count 0 2006.285.08:55:46.74#ibcon#about to write, iclass 40, count 0 2006.285.08:55:46.74#ibcon#wrote, iclass 40, count 0 2006.285.08:55:46.74#ibcon#about to read 3, iclass 40, count 0 2006.285.08:55:46.76#ibcon#read 3, iclass 40, count 0 2006.285.08:55:46.76#ibcon#about to read 4, iclass 40, count 0 2006.285.08:55:46.76#ibcon#read 4, iclass 40, count 0 2006.285.08:55:46.76#ibcon#about to read 5, iclass 40, count 0 2006.285.08:55:46.76#ibcon#read 5, iclass 40, count 0 2006.285.08:55:46.76#ibcon#about to read 6, iclass 40, count 0 2006.285.08:55:46.76#ibcon#read 6, iclass 40, count 0 2006.285.08:55:46.76#ibcon#end of sib2, iclass 40, count 0 2006.285.08:55:46.76#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:55:46.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:55:46.76#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.08:55:46.76#ibcon#*before write, iclass 40, count 0 2006.285.08:55:46.76#ibcon#enter sib2, iclass 40, count 0 2006.285.08:55:46.76#ibcon#flushed, iclass 40, count 0 2006.285.08:55:46.76#ibcon#about to write, iclass 40, count 0 2006.285.08:55:46.76#ibcon#wrote, iclass 40, count 0 2006.285.08:55:46.76#ibcon#about to read 3, iclass 40, count 0 2006.285.08:55:46.80#ibcon#read 3, iclass 40, count 0 2006.285.08:55:46.80#ibcon#about to read 4, iclass 40, count 0 2006.285.08:55:46.80#ibcon#read 4, iclass 40, count 0 2006.285.08:55:46.80#ibcon#about to read 5, iclass 40, count 0 2006.285.08:55:46.80#ibcon#read 5, iclass 40, count 0 2006.285.08:55:46.80#ibcon#about to read 6, iclass 40, count 0 2006.285.08:55:46.80#ibcon#read 6, iclass 40, count 0 2006.285.08:55:46.80#ibcon#end of sib2, iclass 40, count 0 2006.285.08:55:46.80#ibcon#*after write, iclass 40, count 0 2006.285.08:55:46.80#ibcon#*before return 0, iclass 40, count 0 2006.285.08:55:46.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:55:46.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:55:46.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:55:46.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:55:46.80$vck44/va=8,3 2006.285.08:55:46.80#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.08:55:46.80#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.08:55:46.80#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:46.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:55:46.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:55:46.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:55:46.86#ibcon#enter wrdev, iclass 4, count 2 2006.285.08:55:46.86#ibcon#first serial, iclass 4, count 2 2006.285.08:55:46.86#ibcon#enter sib2, iclass 4, count 2 2006.285.08:55:46.86#ibcon#flushed, iclass 4, count 2 2006.285.08:55:46.86#ibcon#about to write, iclass 4, count 2 2006.285.08:55:46.86#ibcon#wrote, iclass 4, count 2 2006.285.08:55:46.86#ibcon#about to read 3, iclass 4, count 2 2006.285.08:55:46.88#ibcon#read 3, iclass 4, count 2 2006.285.08:55:46.88#ibcon#about to read 4, iclass 4, count 2 2006.285.08:55:46.88#ibcon#read 4, iclass 4, count 2 2006.285.08:55:46.88#ibcon#about to read 5, iclass 4, count 2 2006.285.08:55:46.88#ibcon#read 5, iclass 4, count 2 2006.285.08:55:46.88#ibcon#about to read 6, iclass 4, count 2 2006.285.08:55:46.88#ibcon#read 6, iclass 4, count 2 2006.285.08:55:46.88#ibcon#end of sib2, iclass 4, count 2 2006.285.08:55:46.88#ibcon#*mode == 0, iclass 4, count 2 2006.285.08:55:46.88#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.08:55:46.88#ibcon#[25=AT08-03\r\n] 2006.285.08:55:46.88#ibcon#*before write, iclass 4, count 2 2006.285.08:55:46.88#ibcon#enter sib2, iclass 4, count 2 2006.285.08:55:46.88#ibcon#flushed, iclass 4, count 2 2006.285.08:55:46.88#ibcon#about to write, iclass 4, count 2 2006.285.08:55:46.88#ibcon#wrote, iclass 4, count 2 2006.285.08:55:46.88#ibcon#about to read 3, iclass 4, count 2 2006.285.08:55:46.91#ibcon#read 3, iclass 4, count 2 2006.285.08:55:46.91#ibcon#about to read 4, iclass 4, count 2 2006.285.08:55:46.91#ibcon#read 4, iclass 4, count 2 2006.285.08:55:46.91#ibcon#about to read 5, iclass 4, count 2 2006.285.08:55:46.91#ibcon#read 5, iclass 4, count 2 2006.285.08:55:46.91#ibcon#about to read 6, iclass 4, count 2 2006.285.08:55:46.91#ibcon#read 6, iclass 4, count 2 2006.285.08:55:46.91#ibcon#end of sib2, iclass 4, count 2 2006.285.08:55:46.91#ibcon#*after write, iclass 4, count 2 2006.285.08:55:46.91#ibcon#*before return 0, iclass 4, count 2 2006.285.08:55:46.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:55:46.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.08:55:46.91#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.08:55:46.91#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:46.91#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:55:47.03#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:55:47.03#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:55:47.03#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:55:47.03#ibcon#first serial, iclass 4, count 0 2006.285.08:55:47.03#ibcon#enter sib2, iclass 4, count 0 2006.285.08:55:47.03#ibcon#flushed, iclass 4, count 0 2006.285.08:55:47.03#ibcon#about to write, iclass 4, count 0 2006.285.08:55:47.03#ibcon#wrote, iclass 4, count 0 2006.285.08:55:47.03#ibcon#about to read 3, iclass 4, count 0 2006.285.08:55:47.05#ibcon#read 3, iclass 4, count 0 2006.285.08:55:47.05#ibcon#about to read 4, iclass 4, count 0 2006.285.08:55:47.05#ibcon#read 4, iclass 4, count 0 2006.285.08:55:47.05#ibcon#about to read 5, iclass 4, count 0 2006.285.08:55:47.05#ibcon#read 5, iclass 4, count 0 2006.285.08:55:47.05#ibcon#about to read 6, iclass 4, count 0 2006.285.08:55:47.05#ibcon#read 6, iclass 4, count 0 2006.285.08:55:47.05#ibcon#end of sib2, iclass 4, count 0 2006.285.08:55:47.05#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:55:47.05#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:55:47.05#ibcon#[25=USB\r\n] 2006.285.08:55:47.05#ibcon#*before write, iclass 4, count 0 2006.285.08:55:47.05#ibcon#enter sib2, iclass 4, count 0 2006.285.08:55:47.05#ibcon#flushed, iclass 4, count 0 2006.285.08:55:47.05#ibcon#about to write, iclass 4, count 0 2006.285.08:55:47.05#ibcon#wrote, iclass 4, count 0 2006.285.08:55:47.05#ibcon#about to read 3, iclass 4, count 0 2006.285.08:55:47.08#ibcon#read 3, iclass 4, count 0 2006.285.08:55:47.08#ibcon#about to read 4, iclass 4, count 0 2006.285.08:55:47.08#ibcon#read 4, iclass 4, count 0 2006.285.08:55:47.08#ibcon#about to read 5, iclass 4, count 0 2006.285.08:55:47.08#ibcon#read 5, iclass 4, count 0 2006.285.08:55:47.08#ibcon#about to read 6, iclass 4, count 0 2006.285.08:55:47.08#ibcon#read 6, iclass 4, count 0 2006.285.08:55:47.08#ibcon#end of sib2, iclass 4, count 0 2006.285.08:55:47.08#ibcon#*after write, iclass 4, count 0 2006.285.08:55:47.08#ibcon#*before return 0, iclass 4, count 0 2006.285.08:55:47.08#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:55:47.08#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.08:55:47.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:55:47.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:55:47.08$vck44/vblo=1,629.99 2006.285.08:55:47.09#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.08:55:47.09#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.08:55:47.09#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:47.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:55:47.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:55:47.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:55:47.09#ibcon#enter wrdev, iclass 6, count 0 2006.285.08:55:47.09#ibcon#first serial, iclass 6, count 0 2006.285.08:55:47.09#ibcon#enter sib2, iclass 6, count 0 2006.285.08:55:47.09#ibcon#flushed, iclass 6, count 0 2006.285.08:55:47.09#ibcon#about to write, iclass 6, count 0 2006.285.08:55:47.09#ibcon#wrote, iclass 6, count 0 2006.285.08:55:47.09#ibcon#about to read 3, iclass 6, count 0 2006.285.08:55:47.10#ibcon#read 3, iclass 6, count 0 2006.285.08:55:47.10#ibcon#about to read 4, iclass 6, count 0 2006.285.08:55:47.10#ibcon#read 4, iclass 6, count 0 2006.285.08:55:47.10#ibcon#about to read 5, iclass 6, count 0 2006.285.08:55:47.10#ibcon#read 5, iclass 6, count 0 2006.285.08:55:47.10#ibcon#about to read 6, iclass 6, count 0 2006.285.08:55:47.10#ibcon#read 6, iclass 6, count 0 2006.285.08:55:47.10#ibcon#end of sib2, iclass 6, count 0 2006.285.08:55:47.10#ibcon#*mode == 0, iclass 6, count 0 2006.285.08:55:47.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.08:55:47.10#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.08:55:47.10#ibcon#*before write, iclass 6, count 0 2006.285.08:55:47.10#ibcon#enter sib2, iclass 6, count 0 2006.285.08:55:47.10#ibcon#flushed, iclass 6, count 0 2006.285.08:55:47.10#ibcon#about to write, iclass 6, count 0 2006.285.08:55:47.10#ibcon#wrote, iclass 6, count 0 2006.285.08:55:47.10#ibcon#about to read 3, iclass 6, count 0 2006.285.08:55:47.14#ibcon#read 3, iclass 6, count 0 2006.285.08:55:47.14#ibcon#about to read 4, iclass 6, count 0 2006.285.08:55:47.14#ibcon#read 4, iclass 6, count 0 2006.285.08:55:47.14#ibcon#about to read 5, iclass 6, count 0 2006.285.08:55:47.14#ibcon#read 5, iclass 6, count 0 2006.285.08:55:47.14#ibcon#about to read 6, iclass 6, count 0 2006.285.08:55:47.14#ibcon#read 6, iclass 6, count 0 2006.285.08:55:47.14#ibcon#end of sib2, iclass 6, count 0 2006.285.08:55:47.14#ibcon#*after write, iclass 6, count 0 2006.285.08:55:47.14#ibcon#*before return 0, iclass 6, count 0 2006.285.08:55:47.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:55:47.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.08:55:47.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.08:55:47.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.08:55:47.14$vck44/vb=1,4 2006.285.08:55:47.14#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.08:55:47.14#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.08:55:47.14#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:47.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:55:47.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:55:47.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:55:47.14#ibcon#enter wrdev, iclass 10, count 2 2006.285.08:55:47.14#ibcon#first serial, iclass 10, count 2 2006.285.08:55:47.14#ibcon#enter sib2, iclass 10, count 2 2006.285.08:55:47.14#ibcon#flushed, iclass 10, count 2 2006.285.08:55:47.14#ibcon#about to write, iclass 10, count 2 2006.285.08:55:47.14#ibcon#wrote, iclass 10, count 2 2006.285.08:55:47.14#ibcon#about to read 3, iclass 10, count 2 2006.285.08:55:47.16#ibcon#read 3, iclass 10, count 2 2006.285.08:55:47.16#ibcon#about to read 4, iclass 10, count 2 2006.285.08:55:47.16#ibcon#read 4, iclass 10, count 2 2006.285.08:55:47.16#ibcon#about to read 5, iclass 10, count 2 2006.285.08:55:47.16#ibcon#read 5, iclass 10, count 2 2006.285.08:55:47.16#ibcon#about to read 6, iclass 10, count 2 2006.285.08:55:47.16#ibcon#read 6, iclass 10, count 2 2006.285.08:55:47.16#ibcon#end of sib2, iclass 10, count 2 2006.285.08:55:47.16#ibcon#*mode == 0, iclass 10, count 2 2006.285.08:55:47.16#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.08:55:47.16#ibcon#[27=AT01-04\r\n] 2006.285.08:55:47.16#ibcon#*before write, iclass 10, count 2 2006.285.08:55:47.16#ibcon#enter sib2, iclass 10, count 2 2006.285.08:55:47.16#ibcon#flushed, iclass 10, count 2 2006.285.08:55:47.16#ibcon#about to write, iclass 10, count 2 2006.285.08:55:47.16#ibcon#wrote, iclass 10, count 2 2006.285.08:55:47.16#ibcon#about to read 3, iclass 10, count 2 2006.285.08:55:47.19#ibcon#read 3, iclass 10, count 2 2006.285.08:55:47.19#ibcon#about to read 4, iclass 10, count 2 2006.285.08:55:47.19#ibcon#read 4, iclass 10, count 2 2006.285.08:55:47.19#ibcon#about to read 5, iclass 10, count 2 2006.285.08:55:47.19#ibcon#read 5, iclass 10, count 2 2006.285.08:55:47.19#ibcon#about to read 6, iclass 10, count 2 2006.285.08:55:47.19#ibcon#read 6, iclass 10, count 2 2006.285.08:55:47.19#ibcon#end of sib2, iclass 10, count 2 2006.285.08:55:47.19#ibcon#*after write, iclass 10, count 2 2006.285.08:55:47.19#ibcon#*before return 0, iclass 10, count 2 2006.285.08:55:47.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:55:47.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.08:55:47.19#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.08:55:47.19#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:47.19#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:55:47.31#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:55:47.31#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:55:47.31#ibcon#enter wrdev, iclass 10, count 0 2006.285.08:55:47.31#ibcon#first serial, iclass 10, count 0 2006.285.08:55:47.31#ibcon#enter sib2, iclass 10, count 0 2006.285.08:55:47.31#ibcon#flushed, iclass 10, count 0 2006.285.08:55:47.31#ibcon#about to write, iclass 10, count 0 2006.285.08:55:47.31#ibcon#wrote, iclass 10, count 0 2006.285.08:55:47.31#ibcon#about to read 3, iclass 10, count 0 2006.285.08:55:47.33#ibcon#read 3, iclass 10, count 0 2006.285.08:55:47.33#ibcon#about to read 4, iclass 10, count 0 2006.285.08:55:47.33#ibcon#read 4, iclass 10, count 0 2006.285.08:55:47.33#ibcon#about to read 5, iclass 10, count 0 2006.285.08:55:47.33#ibcon#read 5, iclass 10, count 0 2006.285.08:55:47.33#ibcon#about to read 6, iclass 10, count 0 2006.285.08:55:47.33#ibcon#read 6, iclass 10, count 0 2006.285.08:55:47.33#ibcon#end of sib2, iclass 10, count 0 2006.285.08:55:47.33#ibcon#*mode == 0, iclass 10, count 0 2006.285.08:55:47.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.08:55:47.33#ibcon#[27=USB\r\n] 2006.285.08:55:47.33#ibcon#*before write, iclass 10, count 0 2006.285.08:55:47.33#ibcon#enter sib2, iclass 10, count 0 2006.285.08:55:47.33#ibcon#flushed, iclass 10, count 0 2006.285.08:55:47.33#ibcon#about to write, iclass 10, count 0 2006.285.08:55:47.33#ibcon#wrote, iclass 10, count 0 2006.285.08:55:47.33#ibcon#about to read 3, iclass 10, count 0 2006.285.08:55:47.36#ibcon#read 3, iclass 10, count 0 2006.285.08:55:47.36#ibcon#about to read 4, iclass 10, count 0 2006.285.08:55:47.36#ibcon#read 4, iclass 10, count 0 2006.285.08:55:47.36#ibcon#about to read 5, iclass 10, count 0 2006.285.08:55:47.36#ibcon#read 5, iclass 10, count 0 2006.285.08:55:47.36#ibcon#about to read 6, iclass 10, count 0 2006.285.08:55:47.36#ibcon#read 6, iclass 10, count 0 2006.285.08:55:47.36#ibcon#end of sib2, iclass 10, count 0 2006.285.08:55:47.36#ibcon#*after write, iclass 10, count 0 2006.285.08:55:47.36#ibcon#*before return 0, iclass 10, count 0 2006.285.08:55:47.36#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:55:47.36#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.08:55:47.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.08:55:47.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.08:55:47.36$vck44/vblo=2,634.99 2006.285.08:55:47.36#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.08:55:47.36#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.08:55:47.36#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:47.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:55:47.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:55:47.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:55:47.36#ibcon#enter wrdev, iclass 12, count 0 2006.285.08:55:47.36#ibcon#first serial, iclass 12, count 0 2006.285.08:55:47.36#ibcon#enter sib2, iclass 12, count 0 2006.285.08:55:47.36#ibcon#flushed, iclass 12, count 0 2006.285.08:55:47.36#ibcon#about to write, iclass 12, count 0 2006.285.08:55:47.36#ibcon#wrote, iclass 12, count 0 2006.285.08:55:47.36#ibcon#about to read 3, iclass 12, count 0 2006.285.08:55:47.38#ibcon#read 3, iclass 12, count 0 2006.285.08:55:47.38#ibcon#about to read 4, iclass 12, count 0 2006.285.08:55:47.38#ibcon#read 4, iclass 12, count 0 2006.285.08:55:47.38#ibcon#about to read 5, iclass 12, count 0 2006.285.08:55:47.38#ibcon#read 5, iclass 12, count 0 2006.285.08:55:47.38#ibcon#about to read 6, iclass 12, count 0 2006.285.08:55:47.38#ibcon#read 6, iclass 12, count 0 2006.285.08:55:47.38#ibcon#end of sib2, iclass 12, count 0 2006.285.08:55:47.38#ibcon#*mode == 0, iclass 12, count 0 2006.285.08:55:47.38#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.08:55:47.38#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.08:55:47.38#ibcon#*before write, iclass 12, count 0 2006.285.08:55:47.38#ibcon#enter sib2, iclass 12, count 0 2006.285.08:55:47.38#ibcon#flushed, iclass 12, count 0 2006.285.08:55:47.38#ibcon#about to write, iclass 12, count 0 2006.285.08:55:47.38#ibcon#wrote, iclass 12, count 0 2006.285.08:55:47.38#ibcon#about to read 3, iclass 12, count 0 2006.285.08:55:47.42#ibcon#read 3, iclass 12, count 0 2006.285.08:55:47.42#ibcon#about to read 4, iclass 12, count 0 2006.285.08:55:47.42#ibcon#read 4, iclass 12, count 0 2006.285.08:55:47.42#ibcon#about to read 5, iclass 12, count 0 2006.285.08:55:47.42#ibcon#read 5, iclass 12, count 0 2006.285.08:55:47.42#ibcon#about to read 6, iclass 12, count 0 2006.285.08:55:47.42#ibcon#read 6, iclass 12, count 0 2006.285.08:55:47.42#ibcon#end of sib2, iclass 12, count 0 2006.285.08:55:47.42#ibcon#*after write, iclass 12, count 0 2006.285.08:55:47.42#ibcon#*before return 0, iclass 12, count 0 2006.285.08:55:47.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:55:47.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.08:55:47.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.08:55:47.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.08:55:47.42$vck44/vb=2,5 2006.285.08:55:47.42#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.08:55:47.42#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.08:55:47.42#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:47.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:55:47.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:55:47.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:55:47.48#ibcon#enter wrdev, iclass 14, count 2 2006.285.08:55:47.48#ibcon#first serial, iclass 14, count 2 2006.285.08:55:47.48#ibcon#enter sib2, iclass 14, count 2 2006.285.08:55:47.48#ibcon#flushed, iclass 14, count 2 2006.285.08:55:47.48#ibcon#about to write, iclass 14, count 2 2006.285.08:55:47.48#ibcon#wrote, iclass 14, count 2 2006.285.08:55:47.48#ibcon#about to read 3, iclass 14, count 2 2006.285.08:55:47.50#ibcon#read 3, iclass 14, count 2 2006.285.08:55:47.50#ibcon#about to read 4, iclass 14, count 2 2006.285.08:55:47.50#ibcon#read 4, iclass 14, count 2 2006.285.08:55:47.50#ibcon#about to read 5, iclass 14, count 2 2006.285.08:55:47.50#ibcon#read 5, iclass 14, count 2 2006.285.08:55:47.50#ibcon#about to read 6, iclass 14, count 2 2006.285.08:55:47.50#ibcon#read 6, iclass 14, count 2 2006.285.08:55:47.50#ibcon#end of sib2, iclass 14, count 2 2006.285.08:55:47.50#ibcon#*mode == 0, iclass 14, count 2 2006.285.08:55:47.50#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.08:55:47.50#ibcon#[27=AT02-05\r\n] 2006.285.08:55:47.50#ibcon#*before write, iclass 14, count 2 2006.285.08:55:47.50#ibcon#enter sib2, iclass 14, count 2 2006.285.08:55:47.50#ibcon#flushed, iclass 14, count 2 2006.285.08:55:47.50#ibcon#about to write, iclass 14, count 2 2006.285.08:55:47.50#ibcon#wrote, iclass 14, count 2 2006.285.08:55:47.50#ibcon#about to read 3, iclass 14, count 2 2006.285.08:55:47.53#ibcon#read 3, iclass 14, count 2 2006.285.08:55:47.53#ibcon#about to read 4, iclass 14, count 2 2006.285.08:55:47.53#ibcon#read 4, iclass 14, count 2 2006.285.08:55:47.53#ibcon#about to read 5, iclass 14, count 2 2006.285.08:55:47.53#ibcon#read 5, iclass 14, count 2 2006.285.08:55:47.53#ibcon#about to read 6, iclass 14, count 2 2006.285.08:55:47.53#ibcon#read 6, iclass 14, count 2 2006.285.08:55:47.53#ibcon#end of sib2, iclass 14, count 2 2006.285.08:55:47.53#ibcon#*after write, iclass 14, count 2 2006.285.08:55:47.53#ibcon#*before return 0, iclass 14, count 2 2006.285.08:55:47.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:55:47.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.08:55:47.53#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.08:55:47.53#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:47.53#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:55:47.65#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:55:47.65#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:55:47.65#ibcon#enter wrdev, iclass 14, count 0 2006.285.08:55:47.65#ibcon#first serial, iclass 14, count 0 2006.285.08:55:47.65#ibcon#enter sib2, iclass 14, count 0 2006.285.08:55:47.65#ibcon#flushed, iclass 14, count 0 2006.285.08:55:47.65#ibcon#about to write, iclass 14, count 0 2006.285.08:55:47.65#ibcon#wrote, iclass 14, count 0 2006.285.08:55:47.65#ibcon#about to read 3, iclass 14, count 0 2006.285.08:55:47.67#ibcon#read 3, iclass 14, count 0 2006.285.08:55:47.67#ibcon#about to read 4, iclass 14, count 0 2006.285.08:55:47.67#ibcon#read 4, iclass 14, count 0 2006.285.08:55:47.67#ibcon#about to read 5, iclass 14, count 0 2006.285.08:55:47.67#ibcon#read 5, iclass 14, count 0 2006.285.08:55:47.67#ibcon#about to read 6, iclass 14, count 0 2006.285.08:55:47.67#ibcon#read 6, iclass 14, count 0 2006.285.08:55:47.67#ibcon#end of sib2, iclass 14, count 0 2006.285.08:55:47.67#ibcon#*mode == 0, iclass 14, count 0 2006.285.08:55:47.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.08:55:47.67#ibcon#[27=USB\r\n] 2006.285.08:55:47.67#ibcon#*before write, iclass 14, count 0 2006.285.08:55:47.67#ibcon#enter sib2, iclass 14, count 0 2006.285.08:55:47.67#ibcon#flushed, iclass 14, count 0 2006.285.08:55:47.67#ibcon#about to write, iclass 14, count 0 2006.285.08:55:47.67#ibcon#wrote, iclass 14, count 0 2006.285.08:55:47.67#ibcon#about to read 3, iclass 14, count 0 2006.285.08:55:47.70#ibcon#read 3, iclass 14, count 0 2006.285.08:55:47.70#ibcon#about to read 4, iclass 14, count 0 2006.285.08:55:47.70#ibcon#read 4, iclass 14, count 0 2006.285.08:55:47.70#ibcon#about to read 5, iclass 14, count 0 2006.285.08:55:47.70#ibcon#read 5, iclass 14, count 0 2006.285.08:55:47.70#ibcon#about to read 6, iclass 14, count 0 2006.285.08:55:47.70#ibcon#read 6, iclass 14, count 0 2006.285.08:55:47.70#ibcon#end of sib2, iclass 14, count 0 2006.285.08:55:47.70#ibcon#*after write, iclass 14, count 0 2006.285.08:55:47.70#ibcon#*before return 0, iclass 14, count 0 2006.285.08:55:47.70#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:55:47.70#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.08:55:47.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.08:55:47.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.08:55:47.70$vck44/vblo=3,649.99 2006.285.08:55:47.70#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.08:55:47.70#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.08:55:47.70#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:47.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:55:47.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:55:47.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:55:47.70#ibcon#enter wrdev, iclass 16, count 0 2006.285.08:55:47.70#ibcon#first serial, iclass 16, count 0 2006.285.08:55:47.70#ibcon#enter sib2, iclass 16, count 0 2006.285.08:55:47.70#ibcon#flushed, iclass 16, count 0 2006.285.08:55:47.70#ibcon#about to write, iclass 16, count 0 2006.285.08:55:47.70#ibcon#wrote, iclass 16, count 0 2006.285.08:55:47.70#ibcon#about to read 3, iclass 16, count 0 2006.285.08:55:47.72#ibcon#read 3, iclass 16, count 0 2006.285.08:55:47.72#ibcon#about to read 4, iclass 16, count 0 2006.285.08:55:47.72#ibcon#read 4, iclass 16, count 0 2006.285.08:55:47.72#ibcon#about to read 5, iclass 16, count 0 2006.285.08:55:47.72#ibcon#read 5, iclass 16, count 0 2006.285.08:55:47.72#ibcon#about to read 6, iclass 16, count 0 2006.285.08:55:47.72#ibcon#read 6, iclass 16, count 0 2006.285.08:55:47.72#ibcon#end of sib2, iclass 16, count 0 2006.285.08:55:47.72#ibcon#*mode == 0, iclass 16, count 0 2006.285.08:55:47.72#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.08:55:47.72#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.08:55:47.72#ibcon#*before write, iclass 16, count 0 2006.285.08:55:47.72#ibcon#enter sib2, iclass 16, count 0 2006.285.08:55:47.72#ibcon#flushed, iclass 16, count 0 2006.285.08:55:47.72#ibcon#about to write, iclass 16, count 0 2006.285.08:55:47.72#ibcon#wrote, iclass 16, count 0 2006.285.08:55:47.72#ibcon#about to read 3, iclass 16, count 0 2006.285.08:55:47.76#ibcon#read 3, iclass 16, count 0 2006.285.08:55:47.76#ibcon#about to read 4, iclass 16, count 0 2006.285.08:55:47.76#ibcon#read 4, iclass 16, count 0 2006.285.08:55:47.76#ibcon#about to read 5, iclass 16, count 0 2006.285.08:55:47.76#ibcon#read 5, iclass 16, count 0 2006.285.08:55:47.76#ibcon#about to read 6, iclass 16, count 0 2006.285.08:55:47.76#ibcon#read 6, iclass 16, count 0 2006.285.08:55:47.76#ibcon#end of sib2, iclass 16, count 0 2006.285.08:55:47.76#ibcon#*after write, iclass 16, count 0 2006.285.08:55:47.76#ibcon#*before return 0, iclass 16, count 0 2006.285.08:55:47.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:55:47.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.08:55:47.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.08:55:47.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.08:55:47.76$vck44/vb=3,4 2006.285.08:55:47.76#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.08:55:47.76#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.08:55:47.76#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:47.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:55:47.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:55:47.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:55:47.82#ibcon#enter wrdev, iclass 18, count 2 2006.285.08:55:47.82#ibcon#first serial, iclass 18, count 2 2006.285.08:55:47.82#ibcon#enter sib2, iclass 18, count 2 2006.285.08:55:47.82#ibcon#flushed, iclass 18, count 2 2006.285.08:55:47.82#ibcon#about to write, iclass 18, count 2 2006.285.08:55:47.82#ibcon#wrote, iclass 18, count 2 2006.285.08:55:47.82#ibcon#about to read 3, iclass 18, count 2 2006.285.08:55:47.84#ibcon#read 3, iclass 18, count 2 2006.285.08:55:47.84#ibcon#about to read 4, iclass 18, count 2 2006.285.08:55:47.84#ibcon#read 4, iclass 18, count 2 2006.285.08:55:47.84#ibcon#about to read 5, iclass 18, count 2 2006.285.08:55:47.84#ibcon#read 5, iclass 18, count 2 2006.285.08:55:47.84#ibcon#about to read 6, iclass 18, count 2 2006.285.08:55:47.84#ibcon#read 6, iclass 18, count 2 2006.285.08:55:47.84#ibcon#end of sib2, iclass 18, count 2 2006.285.08:55:47.84#ibcon#*mode == 0, iclass 18, count 2 2006.285.08:55:47.84#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.08:55:47.84#ibcon#[27=AT03-04\r\n] 2006.285.08:55:47.84#ibcon#*before write, iclass 18, count 2 2006.285.08:55:47.84#ibcon#enter sib2, iclass 18, count 2 2006.285.08:55:47.84#ibcon#flushed, iclass 18, count 2 2006.285.08:55:47.84#ibcon#about to write, iclass 18, count 2 2006.285.08:55:47.84#ibcon#wrote, iclass 18, count 2 2006.285.08:55:47.84#ibcon#about to read 3, iclass 18, count 2 2006.285.08:55:47.87#ibcon#read 3, iclass 18, count 2 2006.285.08:55:47.87#ibcon#about to read 4, iclass 18, count 2 2006.285.08:55:47.87#ibcon#read 4, iclass 18, count 2 2006.285.08:55:47.87#ibcon#about to read 5, iclass 18, count 2 2006.285.08:55:47.87#ibcon#read 5, iclass 18, count 2 2006.285.08:55:47.87#ibcon#about to read 6, iclass 18, count 2 2006.285.08:55:47.87#ibcon#read 6, iclass 18, count 2 2006.285.08:55:47.87#ibcon#end of sib2, iclass 18, count 2 2006.285.08:55:47.87#ibcon#*after write, iclass 18, count 2 2006.285.08:55:47.87#ibcon#*before return 0, iclass 18, count 2 2006.285.08:55:47.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:55:47.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.08:55:47.87#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.08:55:47.87#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:47.87#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:55:47.99#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:55:47.99#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:55:47.99#ibcon#enter wrdev, iclass 18, count 0 2006.285.08:55:47.99#ibcon#first serial, iclass 18, count 0 2006.285.08:55:47.99#ibcon#enter sib2, iclass 18, count 0 2006.285.08:55:47.99#ibcon#flushed, iclass 18, count 0 2006.285.08:55:47.99#ibcon#about to write, iclass 18, count 0 2006.285.08:55:47.99#ibcon#wrote, iclass 18, count 0 2006.285.08:55:47.99#ibcon#about to read 3, iclass 18, count 0 2006.285.08:55:48.01#ibcon#read 3, iclass 18, count 0 2006.285.08:55:48.01#ibcon#about to read 4, iclass 18, count 0 2006.285.08:55:48.01#ibcon#read 4, iclass 18, count 0 2006.285.08:55:48.01#ibcon#about to read 5, iclass 18, count 0 2006.285.08:55:48.01#ibcon#read 5, iclass 18, count 0 2006.285.08:55:48.01#ibcon#about to read 6, iclass 18, count 0 2006.285.08:55:48.01#ibcon#read 6, iclass 18, count 0 2006.285.08:55:48.01#ibcon#end of sib2, iclass 18, count 0 2006.285.08:55:48.01#ibcon#*mode == 0, iclass 18, count 0 2006.285.08:55:48.01#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.08:55:48.01#ibcon#[27=USB\r\n] 2006.285.08:55:48.01#ibcon#*before write, iclass 18, count 0 2006.285.08:55:48.01#ibcon#enter sib2, iclass 18, count 0 2006.285.08:55:48.01#ibcon#flushed, iclass 18, count 0 2006.285.08:55:48.01#ibcon#about to write, iclass 18, count 0 2006.285.08:55:48.01#ibcon#wrote, iclass 18, count 0 2006.285.08:55:48.01#ibcon#about to read 3, iclass 18, count 0 2006.285.08:55:48.04#ibcon#read 3, iclass 18, count 0 2006.285.08:55:48.04#ibcon#about to read 4, iclass 18, count 0 2006.285.08:55:48.04#ibcon#read 4, iclass 18, count 0 2006.285.08:55:48.04#ibcon#about to read 5, iclass 18, count 0 2006.285.08:55:48.04#ibcon#read 5, iclass 18, count 0 2006.285.08:55:48.04#ibcon#about to read 6, iclass 18, count 0 2006.285.08:55:48.04#ibcon#read 6, iclass 18, count 0 2006.285.08:55:48.04#ibcon#end of sib2, iclass 18, count 0 2006.285.08:55:48.04#ibcon#*after write, iclass 18, count 0 2006.285.08:55:48.04#ibcon#*before return 0, iclass 18, count 0 2006.285.08:55:48.04#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:55:48.04#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.08:55:48.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.08:55:48.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.08:55:48.04$vck44/vblo=4,679.99 2006.285.08:55:48.04#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.08:55:48.04#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.08:55:48.04#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:48.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:55:48.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:55:48.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:55:48.04#ibcon#enter wrdev, iclass 20, count 0 2006.285.08:55:48.04#ibcon#first serial, iclass 20, count 0 2006.285.08:55:48.04#ibcon#enter sib2, iclass 20, count 0 2006.285.08:55:48.04#ibcon#flushed, iclass 20, count 0 2006.285.08:55:48.04#ibcon#about to write, iclass 20, count 0 2006.285.08:55:48.04#ibcon#wrote, iclass 20, count 0 2006.285.08:55:48.04#ibcon#about to read 3, iclass 20, count 0 2006.285.08:55:48.06#ibcon#read 3, iclass 20, count 0 2006.285.08:55:48.06#ibcon#about to read 4, iclass 20, count 0 2006.285.08:55:48.06#ibcon#read 4, iclass 20, count 0 2006.285.08:55:48.06#ibcon#about to read 5, iclass 20, count 0 2006.285.08:55:48.06#ibcon#read 5, iclass 20, count 0 2006.285.08:55:48.06#ibcon#about to read 6, iclass 20, count 0 2006.285.08:55:48.06#ibcon#read 6, iclass 20, count 0 2006.285.08:55:48.06#ibcon#end of sib2, iclass 20, count 0 2006.285.08:55:48.06#ibcon#*mode == 0, iclass 20, count 0 2006.285.08:55:48.06#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.08:55:48.06#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.08:55:48.06#ibcon#*before write, iclass 20, count 0 2006.285.08:55:48.06#ibcon#enter sib2, iclass 20, count 0 2006.285.08:55:48.06#ibcon#flushed, iclass 20, count 0 2006.285.08:55:48.06#ibcon#about to write, iclass 20, count 0 2006.285.08:55:48.06#ibcon#wrote, iclass 20, count 0 2006.285.08:55:48.06#ibcon#about to read 3, iclass 20, count 0 2006.285.08:55:48.10#ibcon#read 3, iclass 20, count 0 2006.285.08:55:48.10#ibcon#about to read 4, iclass 20, count 0 2006.285.08:55:48.10#ibcon#read 4, iclass 20, count 0 2006.285.08:55:48.10#ibcon#about to read 5, iclass 20, count 0 2006.285.08:55:48.10#ibcon#read 5, iclass 20, count 0 2006.285.08:55:48.10#ibcon#about to read 6, iclass 20, count 0 2006.285.08:55:48.10#ibcon#read 6, iclass 20, count 0 2006.285.08:55:48.10#ibcon#end of sib2, iclass 20, count 0 2006.285.08:55:48.10#ibcon#*after write, iclass 20, count 0 2006.285.08:55:48.10#ibcon#*before return 0, iclass 20, count 0 2006.285.08:55:48.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:55:48.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.08:55:48.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.08:55:48.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.08:55:48.10$vck44/vb=4,5 2006.285.08:55:48.10#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.08:55:48.10#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.08:55:48.10#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:48.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:55:48.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:55:48.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:55:48.16#ibcon#enter wrdev, iclass 22, count 2 2006.285.08:55:48.16#ibcon#first serial, iclass 22, count 2 2006.285.08:55:48.16#ibcon#enter sib2, iclass 22, count 2 2006.285.08:55:48.16#ibcon#flushed, iclass 22, count 2 2006.285.08:55:48.16#ibcon#about to write, iclass 22, count 2 2006.285.08:55:48.16#ibcon#wrote, iclass 22, count 2 2006.285.08:55:48.16#ibcon#about to read 3, iclass 22, count 2 2006.285.08:55:48.18#ibcon#read 3, iclass 22, count 2 2006.285.08:55:48.18#ibcon#about to read 4, iclass 22, count 2 2006.285.08:55:48.18#ibcon#read 4, iclass 22, count 2 2006.285.08:55:48.18#ibcon#about to read 5, iclass 22, count 2 2006.285.08:55:48.18#ibcon#read 5, iclass 22, count 2 2006.285.08:55:48.18#ibcon#about to read 6, iclass 22, count 2 2006.285.08:55:48.18#ibcon#read 6, iclass 22, count 2 2006.285.08:55:48.18#ibcon#end of sib2, iclass 22, count 2 2006.285.08:55:48.18#ibcon#*mode == 0, iclass 22, count 2 2006.285.08:55:48.18#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.08:55:48.18#ibcon#[27=AT04-05\r\n] 2006.285.08:55:48.18#ibcon#*before write, iclass 22, count 2 2006.285.08:55:48.18#ibcon#enter sib2, iclass 22, count 2 2006.285.08:55:48.18#ibcon#flushed, iclass 22, count 2 2006.285.08:55:48.18#ibcon#about to write, iclass 22, count 2 2006.285.08:55:48.18#ibcon#wrote, iclass 22, count 2 2006.285.08:55:48.18#ibcon#about to read 3, iclass 22, count 2 2006.285.08:55:48.21#ibcon#read 3, iclass 22, count 2 2006.285.08:55:48.21#ibcon#about to read 4, iclass 22, count 2 2006.285.08:55:48.21#ibcon#read 4, iclass 22, count 2 2006.285.08:55:48.21#ibcon#about to read 5, iclass 22, count 2 2006.285.08:55:48.21#ibcon#read 5, iclass 22, count 2 2006.285.08:55:48.21#ibcon#about to read 6, iclass 22, count 2 2006.285.08:55:48.21#ibcon#read 6, iclass 22, count 2 2006.285.08:55:48.21#ibcon#end of sib2, iclass 22, count 2 2006.285.08:55:48.21#ibcon#*after write, iclass 22, count 2 2006.285.08:55:48.21#ibcon#*before return 0, iclass 22, count 2 2006.285.08:55:48.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:55:48.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.08:55:48.21#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.08:55:48.21#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:48.21#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:55:48.33#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:55:48.33#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:55:48.33#ibcon#enter wrdev, iclass 22, count 0 2006.285.08:55:48.33#ibcon#first serial, iclass 22, count 0 2006.285.08:55:48.33#ibcon#enter sib2, iclass 22, count 0 2006.285.08:55:48.33#ibcon#flushed, iclass 22, count 0 2006.285.08:55:48.33#ibcon#about to write, iclass 22, count 0 2006.285.08:55:48.33#ibcon#wrote, iclass 22, count 0 2006.285.08:55:48.33#ibcon#about to read 3, iclass 22, count 0 2006.285.08:55:48.35#ibcon#read 3, iclass 22, count 0 2006.285.08:55:48.35#ibcon#about to read 4, iclass 22, count 0 2006.285.08:55:48.35#ibcon#read 4, iclass 22, count 0 2006.285.08:55:48.35#ibcon#about to read 5, iclass 22, count 0 2006.285.08:55:48.35#ibcon#read 5, iclass 22, count 0 2006.285.08:55:48.35#ibcon#about to read 6, iclass 22, count 0 2006.285.08:55:48.35#ibcon#read 6, iclass 22, count 0 2006.285.08:55:48.35#ibcon#end of sib2, iclass 22, count 0 2006.285.08:55:48.35#ibcon#*mode == 0, iclass 22, count 0 2006.285.08:55:48.35#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.08:55:48.35#ibcon#[27=USB\r\n] 2006.285.08:55:48.35#ibcon#*before write, iclass 22, count 0 2006.285.08:55:48.35#ibcon#enter sib2, iclass 22, count 0 2006.285.08:55:48.35#ibcon#flushed, iclass 22, count 0 2006.285.08:55:48.35#ibcon#about to write, iclass 22, count 0 2006.285.08:55:48.35#ibcon#wrote, iclass 22, count 0 2006.285.08:55:48.35#ibcon#about to read 3, iclass 22, count 0 2006.285.08:55:48.38#ibcon#read 3, iclass 22, count 0 2006.285.08:55:48.38#ibcon#about to read 4, iclass 22, count 0 2006.285.08:55:48.38#ibcon#read 4, iclass 22, count 0 2006.285.08:55:48.38#ibcon#about to read 5, iclass 22, count 0 2006.285.08:55:48.38#ibcon#read 5, iclass 22, count 0 2006.285.08:55:48.38#ibcon#about to read 6, iclass 22, count 0 2006.285.08:55:48.38#ibcon#read 6, iclass 22, count 0 2006.285.08:55:48.38#ibcon#end of sib2, iclass 22, count 0 2006.285.08:55:48.38#ibcon#*after write, iclass 22, count 0 2006.285.08:55:48.38#ibcon#*before return 0, iclass 22, count 0 2006.285.08:55:48.38#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:55:48.38#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.08:55:48.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.08:55:48.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.08:55:48.38$vck44/vblo=5,709.99 2006.285.08:55:48.38#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.08:55:48.38#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.08:55:48.38#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:48.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:55:48.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:55:48.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:55:48.38#ibcon#enter wrdev, iclass 24, count 0 2006.285.08:55:48.38#ibcon#first serial, iclass 24, count 0 2006.285.08:55:48.38#ibcon#enter sib2, iclass 24, count 0 2006.285.08:55:48.38#ibcon#flushed, iclass 24, count 0 2006.285.08:55:48.38#ibcon#about to write, iclass 24, count 0 2006.285.08:55:48.38#ibcon#wrote, iclass 24, count 0 2006.285.08:55:48.38#ibcon#about to read 3, iclass 24, count 0 2006.285.08:55:48.40#ibcon#read 3, iclass 24, count 0 2006.285.08:55:48.40#ibcon#about to read 4, iclass 24, count 0 2006.285.08:55:48.40#ibcon#read 4, iclass 24, count 0 2006.285.08:55:48.40#ibcon#about to read 5, iclass 24, count 0 2006.285.08:55:48.40#ibcon#read 5, iclass 24, count 0 2006.285.08:55:48.40#ibcon#about to read 6, iclass 24, count 0 2006.285.08:55:48.40#ibcon#read 6, iclass 24, count 0 2006.285.08:55:48.40#ibcon#end of sib2, iclass 24, count 0 2006.285.08:55:48.40#ibcon#*mode == 0, iclass 24, count 0 2006.285.08:55:48.40#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.08:55:48.40#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.08:55:48.40#ibcon#*before write, iclass 24, count 0 2006.285.08:55:48.40#ibcon#enter sib2, iclass 24, count 0 2006.285.08:55:48.40#ibcon#flushed, iclass 24, count 0 2006.285.08:55:48.40#ibcon#about to write, iclass 24, count 0 2006.285.08:55:48.40#ibcon#wrote, iclass 24, count 0 2006.285.08:55:48.40#ibcon#about to read 3, iclass 24, count 0 2006.285.08:55:48.44#ibcon#read 3, iclass 24, count 0 2006.285.08:55:48.44#ibcon#about to read 4, iclass 24, count 0 2006.285.08:55:48.44#ibcon#read 4, iclass 24, count 0 2006.285.08:55:48.44#ibcon#about to read 5, iclass 24, count 0 2006.285.08:55:48.44#ibcon#read 5, iclass 24, count 0 2006.285.08:55:48.44#ibcon#about to read 6, iclass 24, count 0 2006.285.08:55:48.44#ibcon#read 6, iclass 24, count 0 2006.285.08:55:48.44#ibcon#end of sib2, iclass 24, count 0 2006.285.08:55:48.44#ibcon#*after write, iclass 24, count 0 2006.285.08:55:48.44#ibcon#*before return 0, iclass 24, count 0 2006.285.08:55:48.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:55:48.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.08:55:48.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.08:55:48.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.08:55:48.44$vck44/vb=5,4 2006.285.08:55:48.44#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.08:55:48.44#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.08:55:48.44#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:48.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:55:48.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:55:48.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:55:48.50#ibcon#enter wrdev, iclass 26, count 2 2006.285.08:55:48.50#ibcon#first serial, iclass 26, count 2 2006.285.08:55:48.50#ibcon#enter sib2, iclass 26, count 2 2006.285.08:55:48.50#ibcon#flushed, iclass 26, count 2 2006.285.08:55:48.50#ibcon#about to write, iclass 26, count 2 2006.285.08:55:48.50#ibcon#wrote, iclass 26, count 2 2006.285.08:55:48.50#ibcon#about to read 3, iclass 26, count 2 2006.285.08:55:48.52#ibcon#read 3, iclass 26, count 2 2006.285.08:55:48.52#ibcon#about to read 4, iclass 26, count 2 2006.285.08:55:48.52#ibcon#read 4, iclass 26, count 2 2006.285.08:55:48.52#ibcon#about to read 5, iclass 26, count 2 2006.285.08:55:48.52#ibcon#read 5, iclass 26, count 2 2006.285.08:55:48.52#ibcon#about to read 6, iclass 26, count 2 2006.285.08:55:48.52#ibcon#read 6, iclass 26, count 2 2006.285.08:55:48.52#ibcon#end of sib2, iclass 26, count 2 2006.285.08:55:48.52#ibcon#*mode == 0, iclass 26, count 2 2006.285.08:55:48.52#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.08:55:48.52#ibcon#[27=AT05-04\r\n] 2006.285.08:55:48.52#ibcon#*before write, iclass 26, count 2 2006.285.08:55:48.52#ibcon#enter sib2, iclass 26, count 2 2006.285.08:55:48.52#ibcon#flushed, iclass 26, count 2 2006.285.08:55:48.52#ibcon#about to write, iclass 26, count 2 2006.285.08:55:48.52#ibcon#wrote, iclass 26, count 2 2006.285.08:55:48.52#ibcon#about to read 3, iclass 26, count 2 2006.285.08:55:48.55#ibcon#read 3, iclass 26, count 2 2006.285.08:55:48.55#ibcon#about to read 4, iclass 26, count 2 2006.285.08:55:48.55#ibcon#read 4, iclass 26, count 2 2006.285.08:55:48.55#ibcon#about to read 5, iclass 26, count 2 2006.285.08:55:48.55#ibcon#read 5, iclass 26, count 2 2006.285.08:55:48.55#ibcon#about to read 6, iclass 26, count 2 2006.285.08:55:48.55#ibcon#read 6, iclass 26, count 2 2006.285.08:55:48.55#ibcon#end of sib2, iclass 26, count 2 2006.285.08:55:48.55#ibcon#*after write, iclass 26, count 2 2006.285.08:55:48.55#ibcon#*before return 0, iclass 26, count 2 2006.285.08:55:48.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:55:48.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.08:55:48.55#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.08:55:48.55#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:48.55#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:55:48.67#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:55:48.67#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:55:48.67#ibcon#enter wrdev, iclass 26, count 0 2006.285.08:55:48.67#ibcon#first serial, iclass 26, count 0 2006.285.08:55:48.67#ibcon#enter sib2, iclass 26, count 0 2006.285.08:55:48.67#ibcon#flushed, iclass 26, count 0 2006.285.08:55:48.67#ibcon#about to write, iclass 26, count 0 2006.285.08:55:48.67#ibcon#wrote, iclass 26, count 0 2006.285.08:55:48.67#ibcon#about to read 3, iclass 26, count 0 2006.285.08:55:48.69#ibcon#read 3, iclass 26, count 0 2006.285.08:55:48.69#ibcon#about to read 4, iclass 26, count 0 2006.285.08:55:48.69#ibcon#read 4, iclass 26, count 0 2006.285.08:55:48.69#ibcon#about to read 5, iclass 26, count 0 2006.285.08:55:48.69#ibcon#read 5, iclass 26, count 0 2006.285.08:55:48.69#ibcon#about to read 6, iclass 26, count 0 2006.285.08:55:48.69#ibcon#read 6, iclass 26, count 0 2006.285.08:55:48.69#ibcon#end of sib2, iclass 26, count 0 2006.285.08:55:48.69#ibcon#*mode == 0, iclass 26, count 0 2006.285.08:55:48.69#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.08:55:48.69#ibcon#[27=USB\r\n] 2006.285.08:55:48.69#ibcon#*before write, iclass 26, count 0 2006.285.08:55:48.69#ibcon#enter sib2, iclass 26, count 0 2006.285.08:55:48.69#ibcon#flushed, iclass 26, count 0 2006.285.08:55:48.69#ibcon#about to write, iclass 26, count 0 2006.285.08:55:48.69#ibcon#wrote, iclass 26, count 0 2006.285.08:55:48.69#ibcon#about to read 3, iclass 26, count 0 2006.285.08:55:48.72#ibcon#read 3, iclass 26, count 0 2006.285.08:55:48.72#ibcon#about to read 4, iclass 26, count 0 2006.285.08:55:48.72#ibcon#read 4, iclass 26, count 0 2006.285.08:55:48.72#ibcon#about to read 5, iclass 26, count 0 2006.285.08:55:48.72#ibcon#read 5, iclass 26, count 0 2006.285.08:55:48.72#ibcon#about to read 6, iclass 26, count 0 2006.285.08:55:48.72#ibcon#read 6, iclass 26, count 0 2006.285.08:55:48.72#ibcon#end of sib2, iclass 26, count 0 2006.285.08:55:48.72#ibcon#*after write, iclass 26, count 0 2006.285.08:55:48.72#ibcon#*before return 0, iclass 26, count 0 2006.285.08:55:48.72#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:55:48.72#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.08:55:48.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.08:55:48.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.08:55:48.72$vck44/vblo=6,719.99 2006.285.08:55:48.72#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.08:55:48.72#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.08:55:48.72#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:48.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:55:48.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:55:48.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:55:48.72#ibcon#enter wrdev, iclass 28, count 0 2006.285.08:55:48.72#ibcon#first serial, iclass 28, count 0 2006.285.08:55:48.72#ibcon#enter sib2, iclass 28, count 0 2006.285.08:55:48.72#ibcon#flushed, iclass 28, count 0 2006.285.08:55:48.72#ibcon#about to write, iclass 28, count 0 2006.285.08:55:48.72#ibcon#wrote, iclass 28, count 0 2006.285.08:55:48.72#ibcon#about to read 3, iclass 28, count 0 2006.285.08:55:48.74#ibcon#read 3, iclass 28, count 0 2006.285.08:55:48.74#ibcon#about to read 4, iclass 28, count 0 2006.285.08:55:48.74#ibcon#read 4, iclass 28, count 0 2006.285.08:55:48.74#ibcon#about to read 5, iclass 28, count 0 2006.285.08:55:48.74#ibcon#read 5, iclass 28, count 0 2006.285.08:55:48.74#ibcon#about to read 6, iclass 28, count 0 2006.285.08:55:48.74#ibcon#read 6, iclass 28, count 0 2006.285.08:55:48.74#ibcon#end of sib2, iclass 28, count 0 2006.285.08:55:48.74#ibcon#*mode == 0, iclass 28, count 0 2006.285.08:55:48.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.08:55:48.74#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.08:55:48.74#ibcon#*before write, iclass 28, count 0 2006.285.08:55:48.74#ibcon#enter sib2, iclass 28, count 0 2006.285.08:55:48.74#ibcon#flushed, iclass 28, count 0 2006.285.08:55:48.74#ibcon#about to write, iclass 28, count 0 2006.285.08:55:48.74#ibcon#wrote, iclass 28, count 0 2006.285.08:55:48.74#ibcon#about to read 3, iclass 28, count 0 2006.285.08:55:48.78#ibcon#read 3, iclass 28, count 0 2006.285.08:55:48.78#ibcon#about to read 4, iclass 28, count 0 2006.285.08:55:48.78#ibcon#read 4, iclass 28, count 0 2006.285.08:55:48.78#ibcon#about to read 5, iclass 28, count 0 2006.285.08:55:48.78#ibcon#read 5, iclass 28, count 0 2006.285.08:55:48.78#ibcon#about to read 6, iclass 28, count 0 2006.285.08:55:48.78#ibcon#read 6, iclass 28, count 0 2006.285.08:55:48.78#ibcon#end of sib2, iclass 28, count 0 2006.285.08:55:48.78#ibcon#*after write, iclass 28, count 0 2006.285.08:55:48.78#ibcon#*before return 0, iclass 28, count 0 2006.285.08:55:48.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:55:48.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.08:55:48.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.08:55:48.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.08:55:48.78$vck44/vb=6,3 2006.285.08:55:48.78#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.08:55:48.78#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.08:55:48.78#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:48.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:55:48.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:55:48.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:55:48.84#ibcon#enter wrdev, iclass 30, count 2 2006.285.08:55:48.84#ibcon#first serial, iclass 30, count 2 2006.285.08:55:48.84#ibcon#enter sib2, iclass 30, count 2 2006.285.08:55:48.84#ibcon#flushed, iclass 30, count 2 2006.285.08:55:48.84#ibcon#about to write, iclass 30, count 2 2006.285.08:55:48.84#ibcon#wrote, iclass 30, count 2 2006.285.08:55:48.84#ibcon#about to read 3, iclass 30, count 2 2006.285.08:55:48.86#ibcon#read 3, iclass 30, count 2 2006.285.08:55:48.86#ibcon#about to read 4, iclass 30, count 2 2006.285.08:55:48.86#ibcon#read 4, iclass 30, count 2 2006.285.08:55:48.86#ibcon#about to read 5, iclass 30, count 2 2006.285.08:55:48.86#ibcon#read 5, iclass 30, count 2 2006.285.08:55:48.86#ibcon#about to read 6, iclass 30, count 2 2006.285.08:55:48.86#ibcon#read 6, iclass 30, count 2 2006.285.08:55:48.86#ibcon#end of sib2, iclass 30, count 2 2006.285.08:55:48.86#ibcon#*mode == 0, iclass 30, count 2 2006.285.08:55:48.86#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.08:55:48.86#ibcon#[27=AT06-03\r\n] 2006.285.08:55:48.86#ibcon#*before write, iclass 30, count 2 2006.285.08:55:48.86#ibcon#enter sib2, iclass 30, count 2 2006.285.08:55:48.86#ibcon#flushed, iclass 30, count 2 2006.285.08:55:48.86#ibcon#about to write, iclass 30, count 2 2006.285.08:55:48.86#ibcon#wrote, iclass 30, count 2 2006.285.08:55:48.86#ibcon#about to read 3, iclass 30, count 2 2006.285.08:55:48.89#ibcon#read 3, iclass 30, count 2 2006.285.08:55:48.89#ibcon#about to read 4, iclass 30, count 2 2006.285.08:55:48.89#ibcon#read 4, iclass 30, count 2 2006.285.08:55:48.89#ibcon#about to read 5, iclass 30, count 2 2006.285.08:55:48.89#ibcon#read 5, iclass 30, count 2 2006.285.08:55:48.89#ibcon#about to read 6, iclass 30, count 2 2006.285.08:55:48.89#ibcon#read 6, iclass 30, count 2 2006.285.08:55:48.89#ibcon#end of sib2, iclass 30, count 2 2006.285.08:55:48.89#ibcon#*after write, iclass 30, count 2 2006.285.08:55:48.89#ibcon#*before return 0, iclass 30, count 2 2006.285.08:55:48.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:55:48.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.08:55:48.89#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.08:55:48.89#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:48.89#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:55:49.01#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:55:49.01#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:55:49.01#ibcon#enter wrdev, iclass 30, count 0 2006.285.08:55:49.01#ibcon#first serial, iclass 30, count 0 2006.285.08:55:49.01#ibcon#enter sib2, iclass 30, count 0 2006.285.08:55:49.01#ibcon#flushed, iclass 30, count 0 2006.285.08:55:49.01#ibcon#about to write, iclass 30, count 0 2006.285.08:55:49.01#ibcon#wrote, iclass 30, count 0 2006.285.08:55:49.01#ibcon#about to read 3, iclass 30, count 0 2006.285.08:55:49.03#ibcon#read 3, iclass 30, count 0 2006.285.08:55:49.03#ibcon#about to read 4, iclass 30, count 0 2006.285.08:55:49.03#ibcon#read 4, iclass 30, count 0 2006.285.08:55:49.03#ibcon#about to read 5, iclass 30, count 0 2006.285.08:55:49.03#ibcon#read 5, iclass 30, count 0 2006.285.08:55:49.03#ibcon#about to read 6, iclass 30, count 0 2006.285.08:55:49.03#ibcon#read 6, iclass 30, count 0 2006.285.08:55:49.03#ibcon#end of sib2, iclass 30, count 0 2006.285.08:55:49.03#ibcon#*mode == 0, iclass 30, count 0 2006.285.08:55:49.03#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.08:55:49.03#ibcon#[27=USB\r\n] 2006.285.08:55:49.03#ibcon#*before write, iclass 30, count 0 2006.285.08:55:49.03#ibcon#enter sib2, iclass 30, count 0 2006.285.08:55:49.03#ibcon#flushed, iclass 30, count 0 2006.285.08:55:49.03#ibcon#about to write, iclass 30, count 0 2006.285.08:55:49.03#ibcon#wrote, iclass 30, count 0 2006.285.08:55:49.03#ibcon#about to read 3, iclass 30, count 0 2006.285.08:55:49.06#ibcon#read 3, iclass 30, count 0 2006.285.08:55:49.06#ibcon#about to read 4, iclass 30, count 0 2006.285.08:55:49.06#ibcon#read 4, iclass 30, count 0 2006.285.08:55:49.06#ibcon#about to read 5, iclass 30, count 0 2006.285.08:55:49.06#ibcon#read 5, iclass 30, count 0 2006.285.08:55:49.06#ibcon#about to read 6, iclass 30, count 0 2006.285.08:55:49.06#ibcon#read 6, iclass 30, count 0 2006.285.08:55:49.06#ibcon#end of sib2, iclass 30, count 0 2006.285.08:55:49.06#ibcon#*after write, iclass 30, count 0 2006.285.08:55:49.06#ibcon#*before return 0, iclass 30, count 0 2006.285.08:55:49.06#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:55:49.06#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.08:55:49.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.08:55:49.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.08:55:49.06$vck44/vblo=7,734.99 2006.285.08:55:49.06#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.08:55:49.06#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.08:55:49.06#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:49.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:55:49.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:55:49.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:55:49.06#ibcon#enter wrdev, iclass 32, count 0 2006.285.08:55:49.06#ibcon#first serial, iclass 32, count 0 2006.285.08:55:49.06#ibcon#enter sib2, iclass 32, count 0 2006.285.08:55:49.06#ibcon#flushed, iclass 32, count 0 2006.285.08:55:49.06#ibcon#about to write, iclass 32, count 0 2006.285.08:55:49.06#ibcon#wrote, iclass 32, count 0 2006.285.08:55:49.06#ibcon#about to read 3, iclass 32, count 0 2006.285.08:55:49.08#ibcon#read 3, iclass 32, count 0 2006.285.08:55:49.08#ibcon#about to read 4, iclass 32, count 0 2006.285.08:55:49.08#ibcon#read 4, iclass 32, count 0 2006.285.08:55:49.08#ibcon#about to read 5, iclass 32, count 0 2006.285.08:55:49.08#ibcon#read 5, iclass 32, count 0 2006.285.08:55:49.08#ibcon#about to read 6, iclass 32, count 0 2006.285.08:55:49.08#ibcon#read 6, iclass 32, count 0 2006.285.08:55:49.08#ibcon#end of sib2, iclass 32, count 0 2006.285.08:55:49.08#ibcon#*mode == 0, iclass 32, count 0 2006.285.08:55:49.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.08:55:49.08#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.08:55:49.08#ibcon#*before write, iclass 32, count 0 2006.285.08:55:49.08#ibcon#enter sib2, iclass 32, count 0 2006.285.08:55:49.08#ibcon#flushed, iclass 32, count 0 2006.285.08:55:49.08#ibcon#about to write, iclass 32, count 0 2006.285.08:55:49.08#ibcon#wrote, iclass 32, count 0 2006.285.08:55:49.08#ibcon#about to read 3, iclass 32, count 0 2006.285.08:55:49.12#ibcon#read 3, iclass 32, count 0 2006.285.08:55:49.12#ibcon#about to read 4, iclass 32, count 0 2006.285.08:55:49.12#ibcon#read 4, iclass 32, count 0 2006.285.08:55:49.12#ibcon#about to read 5, iclass 32, count 0 2006.285.08:55:49.12#ibcon#read 5, iclass 32, count 0 2006.285.08:55:49.12#ibcon#about to read 6, iclass 32, count 0 2006.285.08:55:49.12#ibcon#read 6, iclass 32, count 0 2006.285.08:55:49.12#ibcon#end of sib2, iclass 32, count 0 2006.285.08:55:49.12#ibcon#*after write, iclass 32, count 0 2006.285.08:55:49.12#ibcon#*before return 0, iclass 32, count 0 2006.285.08:55:49.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:55:49.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.08:55:49.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.08:55:49.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.08:55:49.12$vck44/vb=7,4 2006.285.08:55:49.12#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.08:55:49.12#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.08:55:49.12#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:49.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:55:49.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:55:49.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:55:49.18#ibcon#enter wrdev, iclass 34, count 2 2006.285.08:55:49.18#ibcon#first serial, iclass 34, count 2 2006.285.08:55:49.18#ibcon#enter sib2, iclass 34, count 2 2006.285.08:55:49.18#ibcon#flushed, iclass 34, count 2 2006.285.08:55:49.18#ibcon#about to write, iclass 34, count 2 2006.285.08:55:49.18#ibcon#wrote, iclass 34, count 2 2006.285.08:55:49.18#ibcon#about to read 3, iclass 34, count 2 2006.285.08:55:49.20#ibcon#read 3, iclass 34, count 2 2006.285.08:55:49.20#ibcon#about to read 4, iclass 34, count 2 2006.285.08:55:49.20#ibcon#read 4, iclass 34, count 2 2006.285.08:55:49.20#ibcon#about to read 5, iclass 34, count 2 2006.285.08:55:49.20#ibcon#read 5, iclass 34, count 2 2006.285.08:55:49.20#ibcon#about to read 6, iclass 34, count 2 2006.285.08:55:49.20#ibcon#read 6, iclass 34, count 2 2006.285.08:55:49.20#ibcon#end of sib2, iclass 34, count 2 2006.285.08:55:49.20#ibcon#*mode == 0, iclass 34, count 2 2006.285.08:55:49.20#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.08:55:49.20#ibcon#[27=AT07-04\r\n] 2006.285.08:55:49.20#ibcon#*before write, iclass 34, count 2 2006.285.08:55:49.20#ibcon#enter sib2, iclass 34, count 2 2006.285.08:55:49.20#ibcon#flushed, iclass 34, count 2 2006.285.08:55:49.20#ibcon#about to write, iclass 34, count 2 2006.285.08:55:49.20#ibcon#wrote, iclass 34, count 2 2006.285.08:55:49.20#ibcon#about to read 3, iclass 34, count 2 2006.285.08:55:49.23#ibcon#read 3, iclass 34, count 2 2006.285.08:55:49.23#ibcon#about to read 4, iclass 34, count 2 2006.285.08:55:49.23#ibcon#read 4, iclass 34, count 2 2006.285.08:55:49.23#ibcon#about to read 5, iclass 34, count 2 2006.285.08:55:49.23#ibcon#read 5, iclass 34, count 2 2006.285.08:55:49.23#ibcon#about to read 6, iclass 34, count 2 2006.285.08:55:49.23#ibcon#read 6, iclass 34, count 2 2006.285.08:55:49.23#ibcon#end of sib2, iclass 34, count 2 2006.285.08:55:49.23#ibcon#*after write, iclass 34, count 2 2006.285.08:55:49.23#ibcon#*before return 0, iclass 34, count 2 2006.285.08:55:49.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:55:49.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.08:55:49.23#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.08:55:49.23#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:49.23#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:55:49.35#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:55:49.35#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:55:49.35#ibcon#enter wrdev, iclass 34, count 0 2006.285.08:55:49.35#ibcon#first serial, iclass 34, count 0 2006.285.08:55:49.35#ibcon#enter sib2, iclass 34, count 0 2006.285.08:55:49.35#ibcon#flushed, iclass 34, count 0 2006.285.08:55:49.35#ibcon#about to write, iclass 34, count 0 2006.285.08:55:49.35#ibcon#wrote, iclass 34, count 0 2006.285.08:55:49.35#ibcon#about to read 3, iclass 34, count 0 2006.285.08:55:49.37#ibcon#read 3, iclass 34, count 0 2006.285.08:55:49.37#ibcon#about to read 4, iclass 34, count 0 2006.285.08:55:49.37#ibcon#read 4, iclass 34, count 0 2006.285.08:55:49.37#ibcon#about to read 5, iclass 34, count 0 2006.285.08:55:49.37#ibcon#read 5, iclass 34, count 0 2006.285.08:55:49.37#ibcon#about to read 6, iclass 34, count 0 2006.285.08:55:49.37#ibcon#read 6, iclass 34, count 0 2006.285.08:55:49.37#ibcon#end of sib2, iclass 34, count 0 2006.285.08:55:49.37#ibcon#*mode == 0, iclass 34, count 0 2006.285.08:55:49.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.08:55:49.37#ibcon#[27=USB\r\n] 2006.285.08:55:49.37#ibcon#*before write, iclass 34, count 0 2006.285.08:55:49.37#ibcon#enter sib2, iclass 34, count 0 2006.285.08:55:49.37#ibcon#flushed, iclass 34, count 0 2006.285.08:55:49.37#ibcon#about to write, iclass 34, count 0 2006.285.08:55:49.37#ibcon#wrote, iclass 34, count 0 2006.285.08:55:49.37#ibcon#about to read 3, iclass 34, count 0 2006.285.08:55:49.40#ibcon#read 3, iclass 34, count 0 2006.285.08:55:49.40#ibcon#about to read 4, iclass 34, count 0 2006.285.08:55:49.40#ibcon#read 4, iclass 34, count 0 2006.285.08:55:49.40#ibcon#about to read 5, iclass 34, count 0 2006.285.08:55:49.40#ibcon#read 5, iclass 34, count 0 2006.285.08:55:49.40#ibcon#about to read 6, iclass 34, count 0 2006.285.08:55:49.40#ibcon#read 6, iclass 34, count 0 2006.285.08:55:49.40#ibcon#end of sib2, iclass 34, count 0 2006.285.08:55:49.40#ibcon#*after write, iclass 34, count 0 2006.285.08:55:49.40#ibcon#*before return 0, iclass 34, count 0 2006.285.08:55:49.40#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:55:49.40#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.08:55:49.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.08:55:49.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.08:55:49.40$vck44/vblo=8,744.99 2006.285.08:55:49.40#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.08:55:49.40#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.08:55:49.40#ibcon#ireg 17 cls_cnt 0 2006.285.08:55:49.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:55:49.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:55:49.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:55:49.40#ibcon#enter wrdev, iclass 36, count 0 2006.285.08:55:49.40#ibcon#first serial, iclass 36, count 0 2006.285.08:55:49.40#ibcon#enter sib2, iclass 36, count 0 2006.285.08:55:49.40#ibcon#flushed, iclass 36, count 0 2006.285.08:55:49.40#ibcon#about to write, iclass 36, count 0 2006.285.08:55:49.40#ibcon#wrote, iclass 36, count 0 2006.285.08:55:49.40#ibcon#about to read 3, iclass 36, count 0 2006.285.08:55:49.42#ibcon#read 3, iclass 36, count 0 2006.285.08:55:49.42#ibcon#about to read 4, iclass 36, count 0 2006.285.08:55:49.42#ibcon#read 4, iclass 36, count 0 2006.285.08:55:49.42#ibcon#about to read 5, iclass 36, count 0 2006.285.08:55:49.42#ibcon#read 5, iclass 36, count 0 2006.285.08:55:49.42#ibcon#about to read 6, iclass 36, count 0 2006.285.08:55:49.42#ibcon#read 6, iclass 36, count 0 2006.285.08:55:49.42#ibcon#end of sib2, iclass 36, count 0 2006.285.08:55:49.42#ibcon#*mode == 0, iclass 36, count 0 2006.285.08:55:49.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.08:55:49.42#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.08:55:49.42#ibcon#*before write, iclass 36, count 0 2006.285.08:55:49.42#ibcon#enter sib2, iclass 36, count 0 2006.285.08:55:49.42#ibcon#flushed, iclass 36, count 0 2006.285.08:55:49.42#ibcon#about to write, iclass 36, count 0 2006.285.08:55:49.42#ibcon#wrote, iclass 36, count 0 2006.285.08:55:49.42#ibcon#about to read 3, iclass 36, count 0 2006.285.08:55:49.46#ibcon#read 3, iclass 36, count 0 2006.285.08:55:49.46#ibcon#about to read 4, iclass 36, count 0 2006.285.08:55:49.46#ibcon#read 4, iclass 36, count 0 2006.285.08:55:49.46#ibcon#about to read 5, iclass 36, count 0 2006.285.08:55:49.46#ibcon#read 5, iclass 36, count 0 2006.285.08:55:49.46#ibcon#about to read 6, iclass 36, count 0 2006.285.08:55:49.46#ibcon#read 6, iclass 36, count 0 2006.285.08:55:49.46#ibcon#end of sib2, iclass 36, count 0 2006.285.08:55:49.46#ibcon#*after write, iclass 36, count 0 2006.285.08:55:49.46#ibcon#*before return 0, iclass 36, count 0 2006.285.08:55:49.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:55:49.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.08:55:49.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.08:55:49.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.08:55:49.46$vck44/vb=8,4 2006.285.08:55:49.46#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.08:55:49.46#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.08:55:49.46#ibcon#ireg 11 cls_cnt 2 2006.285.08:55:49.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:55:49.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:55:49.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:55:49.52#ibcon#enter wrdev, iclass 38, count 2 2006.285.08:55:49.52#ibcon#first serial, iclass 38, count 2 2006.285.08:55:49.52#ibcon#enter sib2, iclass 38, count 2 2006.285.08:55:49.52#ibcon#flushed, iclass 38, count 2 2006.285.08:55:49.52#ibcon#about to write, iclass 38, count 2 2006.285.08:55:49.52#ibcon#wrote, iclass 38, count 2 2006.285.08:55:49.52#ibcon#about to read 3, iclass 38, count 2 2006.285.08:55:49.54#ibcon#read 3, iclass 38, count 2 2006.285.08:55:49.54#ibcon#about to read 4, iclass 38, count 2 2006.285.08:55:49.54#ibcon#read 4, iclass 38, count 2 2006.285.08:55:49.54#ibcon#about to read 5, iclass 38, count 2 2006.285.08:55:49.54#ibcon#read 5, iclass 38, count 2 2006.285.08:55:49.54#ibcon#about to read 6, iclass 38, count 2 2006.285.08:55:49.54#ibcon#read 6, iclass 38, count 2 2006.285.08:55:49.54#ibcon#end of sib2, iclass 38, count 2 2006.285.08:55:49.54#ibcon#*mode == 0, iclass 38, count 2 2006.285.08:55:49.54#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.08:55:49.54#ibcon#[27=AT08-04\r\n] 2006.285.08:55:49.54#ibcon#*before write, iclass 38, count 2 2006.285.08:55:49.54#ibcon#enter sib2, iclass 38, count 2 2006.285.08:55:49.54#ibcon#flushed, iclass 38, count 2 2006.285.08:55:49.54#ibcon#about to write, iclass 38, count 2 2006.285.08:55:49.54#ibcon#wrote, iclass 38, count 2 2006.285.08:55:49.54#ibcon#about to read 3, iclass 38, count 2 2006.285.08:55:49.57#ibcon#read 3, iclass 38, count 2 2006.285.08:55:49.57#ibcon#about to read 4, iclass 38, count 2 2006.285.08:55:49.57#ibcon#read 4, iclass 38, count 2 2006.285.08:55:49.57#ibcon#about to read 5, iclass 38, count 2 2006.285.08:55:49.57#ibcon#read 5, iclass 38, count 2 2006.285.08:55:49.57#ibcon#about to read 6, iclass 38, count 2 2006.285.08:55:49.57#ibcon#read 6, iclass 38, count 2 2006.285.08:55:49.57#ibcon#end of sib2, iclass 38, count 2 2006.285.08:55:49.57#ibcon#*after write, iclass 38, count 2 2006.285.08:55:49.57#ibcon#*before return 0, iclass 38, count 2 2006.285.08:55:49.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:55:49.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.08:55:49.57#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.08:55:49.57#ibcon#ireg 7 cls_cnt 0 2006.285.08:55:49.57#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:55:49.69#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:55:49.69#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:55:49.69#ibcon#enter wrdev, iclass 38, count 0 2006.285.08:55:49.69#ibcon#first serial, iclass 38, count 0 2006.285.08:55:49.69#ibcon#enter sib2, iclass 38, count 0 2006.285.08:55:49.69#ibcon#flushed, iclass 38, count 0 2006.285.08:55:49.69#ibcon#about to write, iclass 38, count 0 2006.285.08:55:49.69#ibcon#wrote, iclass 38, count 0 2006.285.08:55:49.69#ibcon#about to read 3, iclass 38, count 0 2006.285.08:55:49.71#ibcon#read 3, iclass 38, count 0 2006.285.08:55:49.71#ibcon#about to read 4, iclass 38, count 0 2006.285.08:55:49.71#ibcon#read 4, iclass 38, count 0 2006.285.08:55:49.71#ibcon#about to read 5, iclass 38, count 0 2006.285.08:55:49.71#ibcon#read 5, iclass 38, count 0 2006.285.08:55:49.71#ibcon#about to read 6, iclass 38, count 0 2006.285.08:55:49.71#ibcon#read 6, iclass 38, count 0 2006.285.08:55:49.71#ibcon#end of sib2, iclass 38, count 0 2006.285.08:55:49.71#ibcon#*mode == 0, iclass 38, count 0 2006.285.08:55:49.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.08:55:49.71#ibcon#[27=USB\r\n] 2006.285.08:55:49.71#ibcon#*before write, iclass 38, count 0 2006.285.08:55:49.71#ibcon#enter sib2, iclass 38, count 0 2006.285.08:55:49.71#ibcon#flushed, iclass 38, count 0 2006.285.08:55:49.71#ibcon#about to write, iclass 38, count 0 2006.285.08:55:49.71#ibcon#wrote, iclass 38, count 0 2006.285.08:55:49.71#ibcon#about to read 3, iclass 38, count 0 2006.285.08:55:49.74#ibcon#read 3, iclass 38, count 0 2006.285.08:55:49.74#ibcon#about to read 4, iclass 38, count 0 2006.285.08:55:49.74#ibcon#read 4, iclass 38, count 0 2006.285.08:55:49.74#ibcon#about to read 5, iclass 38, count 0 2006.285.08:55:49.74#ibcon#read 5, iclass 38, count 0 2006.285.08:55:49.74#ibcon#about to read 6, iclass 38, count 0 2006.285.08:55:49.74#ibcon#read 6, iclass 38, count 0 2006.285.08:55:49.74#ibcon#end of sib2, iclass 38, count 0 2006.285.08:55:49.74#ibcon#*after write, iclass 38, count 0 2006.285.08:55:49.74#ibcon#*before return 0, iclass 38, count 0 2006.285.08:55:49.74#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:55:49.74#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.08:55:49.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.08:55:49.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.08:55:49.74$vck44/vabw=wide 2006.285.08:55:49.74#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.08:55:49.74#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.08:55:49.74#ibcon#ireg 8 cls_cnt 0 2006.285.08:55:49.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:55:49.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:55:49.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:55:49.74#ibcon#enter wrdev, iclass 40, count 0 2006.285.08:55:49.74#ibcon#first serial, iclass 40, count 0 2006.285.08:55:49.74#ibcon#enter sib2, iclass 40, count 0 2006.285.08:55:49.74#ibcon#flushed, iclass 40, count 0 2006.285.08:55:49.74#ibcon#about to write, iclass 40, count 0 2006.285.08:55:49.74#ibcon#wrote, iclass 40, count 0 2006.285.08:55:49.74#ibcon#about to read 3, iclass 40, count 0 2006.285.08:55:49.76#ibcon#read 3, iclass 40, count 0 2006.285.08:55:49.76#ibcon#about to read 4, iclass 40, count 0 2006.285.08:55:49.76#ibcon#read 4, iclass 40, count 0 2006.285.08:55:49.76#ibcon#about to read 5, iclass 40, count 0 2006.285.08:55:49.76#ibcon#read 5, iclass 40, count 0 2006.285.08:55:49.76#ibcon#about to read 6, iclass 40, count 0 2006.285.08:55:49.76#ibcon#read 6, iclass 40, count 0 2006.285.08:55:49.76#ibcon#end of sib2, iclass 40, count 0 2006.285.08:55:49.76#ibcon#*mode == 0, iclass 40, count 0 2006.285.08:55:49.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.08:55:49.76#ibcon#[25=BW32\r\n] 2006.285.08:55:49.76#ibcon#*before write, iclass 40, count 0 2006.285.08:55:49.76#ibcon#enter sib2, iclass 40, count 0 2006.285.08:55:49.76#ibcon#flushed, iclass 40, count 0 2006.285.08:55:49.76#ibcon#about to write, iclass 40, count 0 2006.285.08:55:49.76#ibcon#wrote, iclass 40, count 0 2006.285.08:55:49.76#ibcon#about to read 3, iclass 40, count 0 2006.285.08:55:49.79#ibcon#read 3, iclass 40, count 0 2006.285.08:55:49.79#ibcon#about to read 4, iclass 40, count 0 2006.285.08:55:49.79#ibcon#read 4, iclass 40, count 0 2006.285.08:55:49.79#ibcon#about to read 5, iclass 40, count 0 2006.285.08:55:49.79#ibcon#read 5, iclass 40, count 0 2006.285.08:55:49.79#ibcon#about to read 6, iclass 40, count 0 2006.285.08:55:49.79#ibcon#read 6, iclass 40, count 0 2006.285.08:55:49.79#ibcon#end of sib2, iclass 40, count 0 2006.285.08:55:49.79#ibcon#*after write, iclass 40, count 0 2006.285.08:55:49.79#ibcon#*before return 0, iclass 40, count 0 2006.285.08:55:49.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:55:49.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.08:55:49.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.08:55:49.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.08:55:49.79$vck44/vbbw=wide 2006.285.08:55:49.79#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.08:55:49.79#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.08:55:49.79#ibcon#ireg 8 cls_cnt 0 2006.285.08:55:49.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:55:49.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:55:49.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:55:49.86#ibcon#enter wrdev, iclass 4, count 0 2006.285.08:55:49.86#ibcon#first serial, iclass 4, count 0 2006.285.08:55:49.86#ibcon#enter sib2, iclass 4, count 0 2006.285.08:55:49.86#ibcon#flushed, iclass 4, count 0 2006.285.08:55:49.86#ibcon#about to write, iclass 4, count 0 2006.285.08:55:49.86#ibcon#wrote, iclass 4, count 0 2006.285.08:55:49.86#ibcon#about to read 3, iclass 4, count 0 2006.285.08:55:49.88#ibcon#read 3, iclass 4, count 0 2006.285.08:55:49.88#ibcon#about to read 4, iclass 4, count 0 2006.285.08:55:49.88#ibcon#read 4, iclass 4, count 0 2006.285.08:55:49.88#ibcon#about to read 5, iclass 4, count 0 2006.285.08:55:49.88#ibcon#read 5, iclass 4, count 0 2006.285.08:55:49.88#ibcon#about to read 6, iclass 4, count 0 2006.285.08:55:49.88#ibcon#read 6, iclass 4, count 0 2006.285.08:55:49.88#ibcon#end of sib2, iclass 4, count 0 2006.285.08:55:49.88#ibcon#*mode == 0, iclass 4, count 0 2006.285.08:55:49.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.08:55:49.88#ibcon#[27=BW32\r\n] 2006.285.08:55:49.88#ibcon#*before write, iclass 4, count 0 2006.285.08:55:49.88#ibcon#enter sib2, iclass 4, count 0 2006.285.08:55:49.88#ibcon#flushed, iclass 4, count 0 2006.285.08:55:49.88#ibcon#about to write, iclass 4, count 0 2006.285.08:55:49.88#ibcon#wrote, iclass 4, count 0 2006.285.08:55:49.88#ibcon#about to read 3, iclass 4, count 0 2006.285.08:55:49.91#ibcon#read 3, iclass 4, count 0 2006.285.08:55:49.91#ibcon#about to read 4, iclass 4, count 0 2006.285.08:55:49.91#ibcon#read 4, iclass 4, count 0 2006.285.08:55:49.91#ibcon#about to read 5, iclass 4, count 0 2006.285.08:55:49.91#ibcon#read 5, iclass 4, count 0 2006.285.08:55:49.91#ibcon#about to read 6, iclass 4, count 0 2006.285.08:55:49.91#ibcon#read 6, iclass 4, count 0 2006.285.08:55:49.91#ibcon#end of sib2, iclass 4, count 0 2006.285.08:55:49.91#ibcon#*after write, iclass 4, count 0 2006.285.08:55:49.91#ibcon#*before return 0, iclass 4, count 0 2006.285.08:55:49.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:55:49.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.08:55:49.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.08:55:49.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.08:55:49.91$setupk4/ifdk4 2006.285.08:55:49.91$ifdk4/lo= 2006.285.08:55:49.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.08:55:49.92$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.08:55:49.92$ifdk4/patch= 2006.285.08:55:49.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.08:55:49.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.08:55:49.92$setupk4/!*+20s 2006.285.08:55:51.36#abcon#<5=/04 1.1 1.7 21.64 821014.9\r\n> 2006.285.08:55:51.38#abcon#{5=INTERFACE CLEAR} 2006.285.08:55:51.44#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:55:58.13#trakl#Source acquired 2006.285.08:56:00.13#flagr#flagr/antenna,acquired 2006.285.08:56:01.53#abcon#<5=/04 1.1 1.7 21.63 821014.9\r\n> 2006.285.08:56:01.55#abcon#{5=INTERFACE CLEAR} 2006.285.08:56:01.61#abcon#[5=S1D000X0/0*\r\n] 2006.285.08:56:04.43$setupk4/"tpicd 2006.285.08:56:04.43$setupk4/echo=off 2006.285.08:56:04.43$setupk4/xlog=off 2006.285.08:56:04.43:!2006.285.09:03:50 2006.285.09:03:50.00:preob 2006.285.09:03:50.13/onsource/TRACKING 2006.285.09:03:50.13:!2006.285.09:04:00 2006.285.09:04:00.00:"tape 2006.285.09:04:00.00:"st=record 2006.285.09:04:00.00:data_valid=on 2006.285.09:04:00.00:midob 2006.285.09:04:00.13/onsource/TRACKING 2006.285.09:04:00.13/wx/21.24,1014.9,84 2006.285.09:04:00.27/cable/+6.4792E-03 2006.285.09:04:01.36/va/01,07,usb,yes,32,35 2006.285.09:04:01.36/va/02,06,usb,yes,32,33 2006.285.09:04:01.36/va/03,07,usb,yes,32,33 2006.285.09:04:01.36/va/04,06,usb,yes,33,35 2006.285.09:04:01.36/va/05,03,usb,yes,33,33 2006.285.09:04:01.36/va/06,04,usb,yes,29,29 2006.285.09:04:01.36/va/07,04,usb,yes,30,31 2006.285.09:04:01.36/va/08,03,usb,yes,31,37 2006.285.09:04:01.59/valo/01,524.99,yes,locked 2006.285.09:04:01.59/valo/02,534.99,yes,locked 2006.285.09:04:01.59/valo/03,564.99,yes,locked 2006.285.09:04:01.59/valo/04,624.99,yes,locked 2006.285.09:04:01.59/valo/05,734.99,yes,locked 2006.285.09:04:01.59/valo/06,814.99,yes,locked 2006.285.09:04:01.59/valo/07,864.99,yes,locked 2006.285.09:04:01.59/valo/08,884.99,yes,locked 2006.285.09:04:02.68/vb/01,04,usb,yes,30,28 2006.285.09:04:02.68/vb/02,05,usb,yes,29,29 2006.285.09:04:02.68/vb/03,04,usb,yes,30,33 2006.285.09:04:02.68/vb/04,05,usb,yes,30,29 2006.285.09:04:02.68/vb/05,04,usb,yes,26,29 2006.285.09:04:02.68/vb/06,03,usb,yes,38,34 2006.285.09:04:02.68/vb/07,04,usb,yes,31,30 2006.285.09:04:02.68/vb/08,04,usb,yes,28,31 2006.285.09:04:02.91/vblo/01,629.99,yes,locked 2006.285.09:04:02.91/vblo/02,634.99,yes,locked 2006.285.09:04:02.91/vblo/03,649.99,yes,locked 2006.285.09:04:02.91/vblo/04,679.99,yes,locked 2006.285.09:04:02.91/vblo/05,709.99,yes,locked 2006.285.09:04:02.91/vblo/06,719.99,yes,locked 2006.285.09:04:02.91/vblo/07,734.99,yes,locked 2006.285.09:04:02.91/vblo/08,744.99,yes,locked 2006.285.09:04:03.06/vabw/8 2006.285.09:04:03.21/vbbw/8 2006.285.09:04:03.30/xfe/off,on,12.2 2006.285.09:04:03.67/ifatt/23,28,28,28 2006.285.09:04:04.07/fmout-gps/S +2.52E-07 2006.285.09:04:04.09:!2006.285.09:04:40 2006.285.09:04:40.00:data_valid=off 2006.285.09:04:40.00:"et 2006.285.09:04:40.00:!+3s 2006.285.09:04:43.01:"tape 2006.285.09:04:43.01:postob 2006.285.09:04:43.08/cable/+6.4784E-03 2006.285.09:04:43.08/wx/21.19,1014.9,84 2006.285.09:04:44.07/fmout-gps/S +2.53E-07 2006.285.09:04:44.07:scan_name=285-0906,jd0610,170 2006.285.09:04:44.07:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.285.09:04:45.13#flagr#flagr/antenna,new-source 2006.285.09:04:45.13:checkk5 2006.285.09:04:45.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:04:45.92/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:04:46.34/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:04:46.75/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:04:47.21/chk_obsdata//k5ts1/T2850904??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.09:04:47.58/chk_obsdata//k5ts2/T2850904??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.09:04:48.01/chk_obsdata//k5ts3/T2850904??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.09:04:48.39/chk_obsdata//k5ts4/T2850904??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.09:04:49.14/k5log//k5ts1_log_newline 2006.285.09:04:49.93/k5log//k5ts2_log_newline 2006.285.09:04:50.79/k5log//k5ts3_log_newline 2006.285.09:04:51.51/k5log//k5ts4_log_newline 2006.285.09:04:51.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:04:51.53:setupk4=1 2006.285.09:04:51.53$setupk4/echo=on 2006.285.09:04:51.53$setupk4/pcalon 2006.285.09:04:51.53$pcalon/"no phase cal control is implemented here 2006.285.09:04:51.53$setupk4/"tpicd=stop 2006.285.09:04:51.53$setupk4/"rec=synch_on 2006.285.09:04:51.53$setupk4/"rec_mode=128 2006.285.09:04:51.53$setupk4/!* 2006.285.09:04:51.53$setupk4/recpk4 2006.285.09:04:51.53$recpk4/recpatch= 2006.285.09:04:51.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:04:51.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:04:51.53$setupk4/vck44 2006.285.09:04:51.53$vck44/valo=1,524.99 2006.285.09:04:51.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.09:04:51.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.09:04:51.53#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:51.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:04:51.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:04:51.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:04:51.53#ibcon#enter wrdev, iclass 11, count 0 2006.285.09:04:51.53#ibcon#first serial, iclass 11, count 0 2006.285.09:04:51.53#ibcon#enter sib2, iclass 11, count 0 2006.285.09:04:51.53#ibcon#flushed, iclass 11, count 0 2006.285.09:04:51.53#ibcon#about to write, iclass 11, count 0 2006.285.09:04:51.53#ibcon#wrote, iclass 11, count 0 2006.285.09:04:51.53#ibcon#about to read 3, iclass 11, count 0 2006.285.09:04:51.55#ibcon#read 3, iclass 11, count 0 2006.285.09:04:51.55#ibcon#about to read 4, iclass 11, count 0 2006.285.09:04:51.55#ibcon#read 4, iclass 11, count 0 2006.285.09:04:51.55#ibcon#about to read 5, iclass 11, count 0 2006.285.09:04:51.55#ibcon#read 5, iclass 11, count 0 2006.285.09:04:51.55#ibcon#about to read 6, iclass 11, count 0 2006.285.09:04:51.55#ibcon#read 6, iclass 11, count 0 2006.285.09:04:51.55#ibcon#end of sib2, iclass 11, count 0 2006.285.09:04:51.55#ibcon#*mode == 0, iclass 11, count 0 2006.285.09:04:51.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.09:04:51.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:04:51.55#ibcon#*before write, iclass 11, count 0 2006.285.09:04:51.55#ibcon#enter sib2, iclass 11, count 0 2006.285.09:04:51.55#ibcon#flushed, iclass 11, count 0 2006.285.09:04:51.55#ibcon#about to write, iclass 11, count 0 2006.285.09:04:51.55#ibcon#wrote, iclass 11, count 0 2006.285.09:04:51.55#ibcon#about to read 3, iclass 11, count 0 2006.285.09:04:51.60#ibcon#read 3, iclass 11, count 0 2006.285.09:04:51.60#ibcon#about to read 4, iclass 11, count 0 2006.285.09:04:51.60#ibcon#read 4, iclass 11, count 0 2006.285.09:04:51.60#ibcon#about to read 5, iclass 11, count 0 2006.285.09:04:51.60#ibcon#read 5, iclass 11, count 0 2006.285.09:04:51.60#ibcon#about to read 6, iclass 11, count 0 2006.285.09:04:51.60#ibcon#read 6, iclass 11, count 0 2006.285.09:04:51.60#ibcon#end of sib2, iclass 11, count 0 2006.285.09:04:51.60#ibcon#*after write, iclass 11, count 0 2006.285.09:04:51.60#ibcon#*before return 0, iclass 11, count 0 2006.285.09:04:51.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:04:51.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:04:51.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.09:04:51.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.09:04:51.60$vck44/va=1,7 2006.285.09:04:51.60#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.09:04:51.60#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.09:04:51.60#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:51.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:04:51.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:04:51.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:04:51.60#ibcon#enter wrdev, iclass 13, count 2 2006.285.09:04:51.60#ibcon#first serial, iclass 13, count 2 2006.285.09:04:51.60#ibcon#enter sib2, iclass 13, count 2 2006.285.09:04:51.60#ibcon#flushed, iclass 13, count 2 2006.285.09:04:51.60#ibcon#about to write, iclass 13, count 2 2006.285.09:04:51.60#ibcon#wrote, iclass 13, count 2 2006.285.09:04:51.60#ibcon#about to read 3, iclass 13, count 2 2006.285.09:04:51.62#ibcon#read 3, iclass 13, count 2 2006.285.09:04:51.62#ibcon#about to read 4, iclass 13, count 2 2006.285.09:04:51.62#ibcon#read 4, iclass 13, count 2 2006.285.09:04:51.62#ibcon#about to read 5, iclass 13, count 2 2006.285.09:04:51.62#ibcon#read 5, iclass 13, count 2 2006.285.09:04:51.62#ibcon#about to read 6, iclass 13, count 2 2006.285.09:04:51.62#ibcon#read 6, iclass 13, count 2 2006.285.09:04:51.62#ibcon#end of sib2, iclass 13, count 2 2006.285.09:04:51.62#ibcon#*mode == 0, iclass 13, count 2 2006.285.09:04:51.62#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.09:04:51.62#ibcon#[25=AT01-07\r\n] 2006.285.09:04:51.62#ibcon#*before write, iclass 13, count 2 2006.285.09:04:51.62#ibcon#enter sib2, iclass 13, count 2 2006.285.09:04:51.62#ibcon#flushed, iclass 13, count 2 2006.285.09:04:51.62#ibcon#about to write, iclass 13, count 2 2006.285.09:04:51.62#ibcon#wrote, iclass 13, count 2 2006.285.09:04:51.62#ibcon#about to read 3, iclass 13, count 2 2006.285.09:04:51.65#ibcon#read 3, iclass 13, count 2 2006.285.09:04:51.65#ibcon#about to read 4, iclass 13, count 2 2006.285.09:04:51.65#ibcon#read 4, iclass 13, count 2 2006.285.09:04:51.65#ibcon#about to read 5, iclass 13, count 2 2006.285.09:04:51.65#ibcon#read 5, iclass 13, count 2 2006.285.09:04:51.65#ibcon#about to read 6, iclass 13, count 2 2006.285.09:04:51.65#ibcon#read 6, iclass 13, count 2 2006.285.09:04:51.65#ibcon#end of sib2, iclass 13, count 2 2006.285.09:04:51.65#ibcon#*after write, iclass 13, count 2 2006.285.09:04:51.65#ibcon#*before return 0, iclass 13, count 2 2006.285.09:04:51.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:04:51.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:04:51.65#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.09:04:51.65#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:51.65#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:04:51.77#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:04:51.77#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:04:51.77#ibcon#enter wrdev, iclass 13, count 0 2006.285.09:04:51.77#ibcon#first serial, iclass 13, count 0 2006.285.09:04:51.77#ibcon#enter sib2, iclass 13, count 0 2006.285.09:04:51.77#ibcon#flushed, iclass 13, count 0 2006.285.09:04:51.77#ibcon#about to write, iclass 13, count 0 2006.285.09:04:51.77#ibcon#wrote, iclass 13, count 0 2006.285.09:04:51.77#ibcon#about to read 3, iclass 13, count 0 2006.285.09:04:51.79#ibcon#read 3, iclass 13, count 0 2006.285.09:04:51.79#ibcon#about to read 4, iclass 13, count 0 2006.285.09:04:51.79#ibcon#read 4, iclass 13, count 0 2006.285.09:04:51.79#ibcon#about to read 5, iclass 13, count 0 2006.285.09:04:51.79#ibcon#read 5, iclass 13, count 0 2006.285.09:04:51.79#ibcon#about to read 6, iclass 13, count 0 2006.285.09:04:51.79#ibcon#read 6, iclass 13, count 0 2006.285.09:04:51.79#ibcon#end of sib2, iclass 13, count 0 2006.285.09:04:51.79#ibcon#*mode == 0, iclass 13, count 0 2006.285.09:04:51.79#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.09:04:51.79#ibcon#[25=USB\r\n] 2006.285.09:04:51.79#ibcon#*before write, iclass 13, count 0 2006.285.09:04:51.79#ibcon#enter sib2, iclass 13, count 0 2006.285.09:04:51.79#ibcon#flushed, iclass 13, count 0 2006.285.09:04:51.79#ibcon#about to write, iclass 13, count 0 2006.285.09:04:51.79#ibcon#wrote, iclass 13, count 0 2006.285.09:04:51.79#ibcon#about to read 3, iclass 13, count 0 2006.285.09:04:51.82#ibcon#read 3, iclass 13, count 0 2006.285.09:04:51.82#ibcon#about to read 4, iclass 13, count 0 2006.285.09:04:51.82#ibcon#read 4, iclass 13, count 0 2006.285.09:04:51.82#ibcon#about to read 5, iclass 13, count 0 2006.285.09:04:51.82#ibcon#read 5, iclass 13, count 0 2006.285.09:04:51.82#ibcon#about to read 6, iclass 13, count 0 2006.285.09:04:51.82#ibcon#read 6, iclass 13, count 0 2006.285.09:04:51.82#ibcon#end of sib2, iclass 13, count 0 2006.285.09:04:51.82#ibcon#*after write, iclass 13, count 0 2006.285.09:04:51.82#ibcon#*before return 0, iclass 13, count 0 2006.285.09:04:51.82#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:04:51.82#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:04:51.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.09:04:51.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.09:04:51.82$vck44/valo=2,534.99 2006.285.09:04:51.82#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.09:04:51.82#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.09:04:51.82#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:51.82#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:04:51.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:04:51.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:04:51.82#ibcon#enter wrdev, iclass 15, count 0 2006.285.09:04:51.82#ibcon#first serial, iclass 15, count 0 2006.285.09:04:51.82#ibcon#enter sib2, iclass 15, count 0 2006.285.09:04:51.82#ibcon#flushed, iclass 15, count 0 2006.285.09:04:51.82#ibcon#about to write, iclass 15, count 0 2006.285.09:04:51.82#ibcon#wrote, iclass 15, count 0 2006.285.09:04:51.82#ibcon#about to read 3, iclass 15, count 0 2006.285.09:04:51.84#ibcon#read 3, iclass 15, count 0 2006.285.09:04:51.84#ibcon#about to read 4, iclass 15, count 0 2006.285.09:04:51.84#ibcon#read 4, iclass 15, count 0 2006.285.09:04:51.84#ibcon#about to read 5, iclass 15, count 0 2006.285.09:04:51.84#ibcon#read 5, iclass 15, count 0 2006.285.09:04:51.84#ibcon#about to read 6, iclass 15, count 0 2006.285.09:04:51.84#ibcon#read 6, iclass 15, count 0 2006.285.09:04:51.84#ibcon#end of sib2, iclass 15, count 0 2006.285.09:04:51.84#ibcon#*mode == 0, iclass 15, count 0 2006.285.09:04:51.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.09:04:51.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:04:51.84#ibcon#*before write, iclass 15, count 0 2006.285.09:04:51.84#ibcon#enter sib2, iclass 15, count 0 2006.285.09:04:51.84#ibcon#flushed, iclass 15, count 0 2006.285.09:04:51.84#ibcon#about to write, iclass 15, count 0 2006.285.09:04:51.84#ibcon#wrote, iclass 15, count 0 2006.285.09:04:51.84#ibcon#about to read 3, iclass 15, count 0 2006.285.09:04:51.88#ibcon#read 3, iclass 15, count 0 2006.285.09:04:51.88#ibcon#about to read 4, iclass 15, count 0 2006.285.09:04:51.88#ibcon#read 4, iclass 15, count 0 2006.285.09:04:51.88#ibcon#about to read 5, iclass 15, count 0 2006.285.09:04:51.88#ibcon#read 5, iclass 15, count 0 2006.285.09:04:51.88#ibcon#about to read 6, iclass 15, count 0 2006.285.09:04:51.88#ibcon#read 6, iclass 15, count 0 2006.285.09:04:51.88#ibcon#end of sib2, iclass 15, count 0 2006.285.09:04:51.88#ibcon#*after write, iclass 15, count 0 2006.285.09:04:51.88#ibcon#*before return 0, iclass 15, count 0 2006.285.09:04:51.88#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:04:51.88#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:04:51.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.09:04:51.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.09:04:51.88$vck44/va=2,6 2006.285.09:04:51.88#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.09:04:51.88#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.09:04:51.88#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:51.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:04:51.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:04:51.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:04:51.94#ibcon#enter wrdev, iclass 17, count 2 2006.285.09:04:51.94#ibcon#first serial, iclass 17, count 2 2006.285.09:04:51.94#ibcon#enter sib2, iclass 17, count 2 2006.285.09:04:51.94#ibcon#flushed, iclass 17, count 2 2006.285.09:04:51.94#ibcon#about to write, iclass 17, count 2 2006.285.09:04:51.94#ibcon#wrote, iclass 17, count 2 2006.285.09:04:51.94#ibcon#about to read 3, iclass 17, count 2 2006.285.09:04:51.96#ibcon#read 3, iclass 17, count 2 2006.285.09:04:51.96#ibcon#about to read 4, iclass 17, count 2 2006.285.09:04:51.96#ibcon#read 4, iclass 17, count 2 2006.285.09:04:51.96#ibcon#about to read 5, iclass 17, count 2 2006.285.09:04:51.96#ibcon#read 5, iclass 17, count 2 2006.285.09:04:51.96#ibcon#about to read 6, iclass 17, count 2 2006.285.09:04:51.96#ibcon#read 6, iclass 17, count 2 2006.285.09:04:51.96#ibcon#end of sib2, iclass 17, count 2 2006.285.09:04:51.96#ibcon#*mode == 0, iclass 17, count 2 2006.285.09:04:51.96#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.09:04:51.96#ibcon#[25=AT02-06\r\n] 2006.285.09:04:51.96#ibcon#*before write, iclass 17, count 2 2006.285.09:04:51.96#ibcon#enter sib2, iclass 17, count 2 2006.285.09:04:51.96#ibcon#flushed, iclass 17, count 2 2006.285.09:04:51.96#ibcon#about to write, iclass 17, count 2 2006.285.09:04:51.96#ibcon#wrote, iclass 17, count 2 2006.285.09:04:51.96#ibcon#about to read 3, iclass 17, count 2 2006.285.09:04:51.99#ibcon#read 3, iclass 17, count 2 2006.285.09:04:51.99#ibcon#about to read 4, iclass 17, count 2 2006.285.09:04:51.99#ibcon#read 4, iclass 17, count 2 2006.285.09:04:51.99#ibcon#about to read 5, iclass 17, count 2 2006.285.09:04:51.99#ibcon#read 5, iclass 17, count 2 2006.285.09:04:51.99#ibcon#about to read 6, iclass 17, count 2 2006.285.09:04:51.99#ibcon#read 6, iclass 17, count 2 2006.285.09:04:51.99#ibcon#end of sib2, iclass 17, count 2 2006.285.09:04:51.99#ibcon#*after write, iclass 17, count 2 2006.285.09:04:51.99#ibcon#*before return 0, iclass 17, count 2 2006.285.09:04:51.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:04:51.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:04:51.99#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.09:04:51.99#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:51.99#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:04:52.11#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:04:52.11#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:04:52.11#ibcon#enter wrdev, iclass 17, count 0 2006.285.09:04:52.11#ibcon#first serial, iclass 17, count 0 2006.285.09:04:52.11#ibcon#enter sib2, iclass 17, count 0 2006.285.09:04:52.11#ibcon#flushed, iclass 17, count 0 2006.285.09:04:52.11#ibcon#about to write, iclass 17, count 0 2006.285.09:04:52.11#ibcon#wrote, iclass 17, count 0 2006.285.09:04:52.11#ibcon#about to read 3, iclass 17, count 0 2006.285.09:04:52.13#ibcon#read 3, iclass 17, count 0 2006.285.09:04:52.13#ibcon#about to read 4, iclass 17, count 0 2006.285.09:04:52.13#ibcon#read 4, iclass 17, count 0 2006.285.09:04:52.13#ibcon#about to read 5, iclass 17, count 0 2006.285.09:04:52.13#ibcon#read 5, iclass 17, count 0 2006.285.09:04:52.13#ibcon#about to read 6, iclass 17, count 0 2006.285.09:04:52.13#ibcon#read 6, iclass 17, count 0 2006.285.09:04:52.13#ibcon#end of sib2, iclass 17, count 0 2006.285.09:04:52.13#ibcon#*mode == 0, iclass 17, count 0 2006.285.09:04:52.13#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.09:04:52.13#ibcon#[25=USB\r\n] 2006.285.09:04:52.13#ibcon#*before write, iclass 17, count 0 2006.285.09:04:52.13#ibcon#enter sib2, iclass 17, count 0 2006.285.09:04:52.13#ibcon#flushed, iclass 17, count 0 2006.285.09:04:52.13#ibcon#about to write, iclass 17, count 0 2006.285.09:04:52.13#ibcon#wrote, iclass 17, count 0 2006.285.09:04:52.13#ibcon#about to read 3, iclass 17, count 0 2006.285.09:04:52.16#ibcon#read 3, iclass 17, count 0 2006.285.09:04:52.16#ibcon#about to read 4, iclass 17, count 0 2006.285.09:04:52.16#ibcon#read 4, iclass 17, count 0 2006.285.09:04:52.16#ibcon#about to read 5, iclass 17, count 0 2006.285.09:04:52.16#ibcon#read 5, iclass 17, count 0 2006.285.09:04:52.16#ibcon#about to read 6, iclass 17, count 0 2006.285.09:04:52.16#ibcon#read 6, iclass 17, count 0 2006.285.09:04:52.16#ibcon#end of sib2, iclass 17, count 0 2006.285.09:04:52.16#ibcon#*after write, iclass 17, count 0 2006.285.09:04:52.16#ibcon#*before return 0, iclass 17, count 0 2006.285.09:04:52.16#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:04:52.16#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:04:52.16#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.09:04:52.16#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.09:04:52.16$vck44/valo=3,564.99 2006.285.09:04:52.16#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.09:04:52.16#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.09:04:52.16#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:52.16#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:04:52.16#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:04:52.16#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:04:52.16#ibcon#enter wrdev, iclass 19, count 0 2006.285.09:04:52.16#ibcon#first serial, iclass 19, count 0 2006.285.09:04:52.16#ibcon#enter sib2, iclass 19, count 0 2006.285.09:04:52.16#ibcon#flushed, iclass 19, count 0 2006.285.09:04:52.16#ibcon#about to write, iclass 19, count 0 2006.285.09:04:52.16#ibcon#wrote, iclass 19, count 0 2006.285.09:04:52.16#ibcon#about to read 3, iclass 19, count 0 2006.285.09:04:52.18#ibcon#read 3, iclass 19, count 0 2006.285.09:04:52.18#ibcon#about to read 4, iclass 19, count 0 2006.285.09:04:52.18#ibcon#read 4, iclass 19, count 0 2006.285.09:04:52.18#ibcon#about to read 5, iclass 19, count 0 2006.285.09:04:52.18#ibcon#read 5, iclass 19, count 0 2006.285.09:04:52.18#ibcon#about to read 6, iclass 19, count 0 2006.285.09:04:52.18#ibcon#read 6, iclass 19, count 0 2006.285.09:04:52.18#ibcon#end of sib2, iclass 19, count 0 2006.285.09:04:52.18#ibcon#*mode == 0, iclass 19, count 0 2006.285.09:04:52.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.09:04:52.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:04:52.18#ibcon#*before write, iclass 19, count 0 2006.285.09:04:52.18#ibcon#enter sib2, iclass 19, count 0 2006.285.09:04:52.18#ibcon#flushed, iclass 19, count 0 2006.285.09:04:52.18#ibcon#about to write, iclass 19, count 0 2006.285.09:04:52.18#ibcon#wrote, iclass 19, count 0 2006.285.09:04:52.18#ibcon#about to read 3, iclass 19, count 0 2006.285.09:04:52.22#ibcon#read 3, iclass 19, count 0 2006.285.09:04:52.22#ibcon#about to read 4, iclass 19, count 0 2006.285.09:04:52.22#ibcon#read 4, iclass 19, count 0 2006.285.09:04:52.22#ibcon#about to read 5, iclass 19, count 0 2006.285.09:04:52.22#ibcon#read 5, iclass 19, count 0 2006.285.09:04:52.22#ibcon#about to read 6, iclass 19, count 0 2006.285.09:04:52.22#ibcon#read 6, iclass 19, count 0 2006.285.09:04:52.22#ibcon#end of sib2, iclass 19, count 0 2006.285.09:04:52.22#ibcon#*after write, iclass 19, count 0 2006.285.09:04:52.22#ibcon#*before return 0, iclass 19, count 0 2006.285.09:04:52.22#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:04:52.22#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:04:52.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.09:04:52.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.09:04:52.22$vck44/va=3,7 2006.285.09:04:52.22#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.09:04:52.22#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.09:04:52.22#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:52.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:04:52.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:04:52.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:04:52.28#ibcon#enter wrdev, iclass 21, count 2 2006.285.09:04:52.28#ibcon#first serial, iclass 21, count 2 2006.285.09:04:52.28#ibcon#enter sib2, iclass 21, count 2 2006.285.09:04:52.28#ibcon#flushed, iclass 21, count 2 2006.285.09:04:52.28#ibcon#about to write, iclass 21, count 2 2006.285.09:04:52.28#ibcon#wrote, iclass 21, count 2 2006.285.09:04:52.28#ibcon#about to read 3, iclass 21, count 2 2006.285.09:04:52.30#ibcon#read 3, iclass 21, count 2 2006.285.09:04:52.30#ibcon#about to read 4, iclass 21, count 2 2006.285.09:04:52.30#ibcon#read 4, iclass 21, count 2 2006.285.09:04:52.30#ibcon#about to read 5, iclass 21, count 2 2006.285.09:04:52.30#ibcon#read 5, iclass 21, count 2 2006.285.09:04:52.30#ibcon#about to read 6, iclass 21, count 2 2006.285.09:04:52.30#ibcon#read 6, iclass 21, count 2 2006.285.09:04:52.30#ibcon#end of sib2, iclass 21, count 2 2006.285.09:04:52.30#ibcon#*mode == 0, iclass 21, count 2 2006.285.09:04:52.30#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.09:04:52.30#ibcon#[25=AT03-07\r\n] 2006.285.09:04:52.30#ibcon#*before write, iclass 21, count 2 2006.285.09:04:52.30#ibcon#enter sib2, iclass 21, count 2 2006.285.09:04:52.30#ibcon#flushed, iclass 21, count 2 2006.285.09:04:52.30#ibcon#about to write, iclass 21, count 2 2006.285.09:04:52.30#ibcon#wrote, iclass 21, count 2 2006.285.09:04:52.30#ibcon#about to read 3, iclass 21, count 2 2006.285.09:04:52.33#ibcon#read 3, iclass 21, count 2 2006.285.09:04:52.33#ibcon#about to read 4, iclass 21, count 2 2006.285.09:04:52.33#ibcon#read 4, iclass 21, count 2 2006.285.09:04:52.33#ibcon#about to read 5, iclass 21, count 2 2006.285.09:04:52.33#ibcon#read 5, iclass 21, count 2 2006.285.09:04:52.33#ibcon#about to read 6, iclass 21, count 2 2006.285.09:04:52.33#ibcon#read 6, iclass 21, count 2 2006.285.09:04:52.33#ibcon#end of sib2, iclass 21, count 2 2006.285.09:04:52.33#ibcon#*after write, iclass 21, count 2 2006.285.09:04:52.33#ibcon#*before return 0, iclass 21, count 2 2006.285.09:04:52.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:04:52.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:04:52.33#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.09:04:52.33#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:52.33#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:04:52.45#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:04:52.45#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:04:52.45#ibcon#enter wrdev, iclass 21, count 0 2006.285.09:04:52.45#ibcon#first serial, iclass 21, count 0 2006.285.09:04:52.45#ibcon#enter sib2, iclass 21, count 0 2006.285.09:04:52.45#ibcon#flushed, iclass 21, count 0 2006.285.09:04:52.45#ibcon#about to write, iclass 21, count 0 2006.285.09:04:52.45#ibcon#wrote, iclass 21, count 0 2006.285.09:04:52.45#ibcon#about to read 3, iclass 21, count 0 2006.285.09:04:52.47#ibcon#read 3, iclass 21, count 0 2006.285.09:04:52.47#ibcon#about to read 4, iclass 21, count 0 2006.285.09:04:52.47#ibcon#read 4, iclass 21, count 0 2006.285.09:04:52.47#ibcon#about to read 5, iclass 21, count 0 2006.285.09:04:52.47#ibcon#read 5, iclass 21, count 0 2006.285.09:04:52.47#ibcon#about to read 6, iclass 21, count 0 2006.285.09:04:52.47#ibcon#read 6, iclass 21, count 0 2006.285.09:04:52.47#ibcon#end of sib2, iclass 21, count 0 2006.285.09:04:52.47#ibcon#*mode == 0, iclass 21, count 0 2006.285.09:04:52.47#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.09:04:52.47#ibcon#[25=USB\r\n] 2006.285.09:04:52.47#ibcon#*before write, iclass 21, count 0 2006.285.09:04:52.47#ibcon#enter sib2, iclass 21, count 0 2006.285.09:04:52.47#ibcon#flushed, iclass 21, count 0 2006.285.09:04:52.47#ibcon#about to write, iclass 21, count 0 2006.285.09:04:52.47#ibcon#wrote, iclass 21, count 0 2006.285.09:04:52.47#ibcon#about to read 3, iclass 21, count 0 2006.285.09:04:52.50#ibcon#read 3, iclass 21, count 0 2006.285.09:04:52.50#ibcon#about to read 4, iclass 21, count 0 2006.285.09:04:52.50#ibcon#read 4, iclass 21, count 0 2006.285.09:04:52.50#ibcon#about to read 5, iclass 21, count 0 2006.285.09:04:52.50#ibcon#read 5, iclass 21, count 0 2006.285.09:04:52.50#ibcon#about to read 6, iclass 21, count 0 2006.285.09:04:52.50#ibcon#read 6, iclass 21, count 0 2006.285.09:04:52.50#ibcon#end of sib2, iclass 21, count 0 2006.285.09:04:52.50#ibcon#*after write, iclass 21, count 0 2006.285.09:04:52.50#ibcon#*before return 0, iclass 21, count 0 2006.285.09:04:52.50#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:04:52.50#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:04:52.50#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.09:04:52.50#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.09:04:52.50$vck44/valo=4,624.99 2006.285.09:04:52.50#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.09:04:52.50#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.09:04:52.50#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:52.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:04:52.50#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:04:52.50#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:04:52.50#ibcon#enter wrdev, iclass 23, count 0 2006.285.09:04:52.50#ibcon#first serial, iclass 23, count 0 2006.285.09:04:52.50#ibcon#enter sib2, iclass 23, count 0 2006.285.09:04:52.50#ibcon#flushed, iclass 23, count 0 2006.285.09:04:52.50#ibcon#about to write, iclass 23, count 0 2006.285.09:04:52.50#ibcon#wrote, iclass 23, count 0 2006.285.09:04:52.50#ibcon#about to read 3, iclass 23, count 0 2006.285.09:04:52.52#ibcon#read 3, iclass 23, count 0 2006.285.09:04:52.52#ibcon#about to read 4, iclass 23, count 0 2006.285.09:04:52.52#ibcon#read 4, iclass 23, count 0 2006.285.09:04:52.52#ibcon#about to read 5, iclass 23, count 0 2006.285.09:04:52.52#ibcon#read 5, iclass 23, count 0 2006.285.09:04:52.52#ibcon#about to read 6, iclass 23, count 0 2006.285.09:04:52.52#ibcon#read 6, iclass 23, count 0 2006.285.09:04:52.52#ibcon#end of sib2, iclass 23, count 0 2006.285.09:04:52.52#ibcon#*mode == 0, iclass 23, count 0 2006.285.09:04:52.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.09:04:52.52#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:04:52.52#ibcon#*before write, iclass 23, count 0 2006.285.09:04:52.52#ibcon#enter sib2, iclass 23, count 0 2006.285.09:04:52.52#ibcon#flushed, iclass 23, count 0 2006.285.09:04:52.52#ibcon#about to write, iclass 23, count 0 2006.285.09:04:52.52#ibcon#wrote, iclass 23, count 0 2006.285.09:04:52.52#ibcon#about to read 3, iclass 23, count 0 2006.285.09:04:52.56#ibcon#read 3, iclass 23, count 0 2006.285.09:04:52.56#ibcon#about to read 4, iclass 23, count 0 2006.285.09:04:52.56#ibcon#read 4, iclass 23, count 0 2006.285.09:04:52.56#ibcon#about to read 5, iclass 23, count 0 2006.285.09:04:52.56#ibcon#read 5, iclass 23, count 0 2006.285.09:04:52.56#ibcon#about to read 6, iclass 23, count 0 2006.285.09:04:52.56#ibcon#read 6, iclass 23, count 0 2006.285.09:04:52.56#ibcon#end of sib2, iclass 23, count 0 2006.285.09:04:52.56#ibcon#*after write, iclass 23, count 0 2006.285.09:04:52.56#ibcon#*before return 0, iclass 23, count 0 2006.285.09:04:52.56#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:04:52.56#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:04:52.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.09:04:52.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.09:04:52.56$vck44/va=4,6 2006.285.09:04:52.56#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.09:04:52.56#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.09:04:52.56#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:52.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:04:52.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:04:52.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:04:52.62#ibcon#enter wrdev, iclass 25, count 2 2006.285.09:04:52.62#ibcon#first serial, iclass 25, count 2 2006.285.09:04:52.62#ibcon#enter sib2, iclass 25, count 2 2006.285.09:04:52.62#ibcon#flushed, iclass 25, count 2 2006.285.09:04:52.62#ibcon#about to write, iclass 25, count 2 2006.285.09:04:52.62#ibcon#wrote, iclass 25, count 2 2006.285.09:04:52.62#ibcon#about to read 3, iclass 25, count 2 2006.285.09:04:52.64#ibcon#read 3, iclass 25, count 2 2006.285.09:04:52.64#ibcon#about to read 4, iclass 25, count 2 2006.285.09:04:52.64#ibcon#read 4, iclass 25, count 2 2006.285.09:04:52.64#ibcon#about to read 5, iclass 25, count 2 2006.285.09:04:52.64#ibcon#read 5, iclass 25, count 2 2006.285.09:04:52.64#ibcon#about to read 6, iclass 25, count 2 2006.285.09:04:52.64#ibcon#read 6, iclass 25, count 2 2006.285.09:04:52.64#ibcon#end of sib2, iclass 25, count 2 2006.285.09:04:52.64#ibcon#*mode == 0, iclass 25, count 2 2006.285.09:04:52.64#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.09:04:52.64#ibcon#[25=AT04-06\r\n] 2006.285.09:04:52.64#ibcon#*before write, iclass 25, count 2 2006.285.09:04:52.64#ibcon#enter sib2, iclass 25, count 2 2006.285.09:04:52.64#ibcon#flushed, iclass 25, count 2 2006.285.09:04:52.64#ibcon#about to write, iclass 25, count 2 2006.285.09:04:52.64#ibcon#wrote, iclass 25, count 2 2006.285.09:04:52.64#ibcon#about to read 3, iclass 25, count 2 2006.285.09:04:52.67#ibcon#read 3, iclass 25, count 2 2006.285.09:04:52.67#ibcon#about to read 4, iclass 25, count 2 2006.285.09:04:52.67#ibcon#read 4, iclass 25, count 2 2006.285.09:04:52.67#ibcon#about to read 5, iclass 25, count 2 2006.285.09:04:52.67#ibcon#read 5, iclass 25, count 2 2006.285.09:04:52.67#ibcon#about to read 6, iclass 25, count 2 2006.285.09:04:52.67#ibcon#read 6, iclass 25, count 2 2006.285.09:04:52.67#ibcon#end of sib2, iclass 25, count 2 2006.285.09:04:52.67#ibcon#*after write, iclass 25, count 2 2006.285.09:04:52.67#ibcon#*before return 0, iclass 25, count 2 2006.285.09:04:52.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:04:52.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:04:52.67#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.09:04:52.67#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:52.67#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:04:52.79#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:04:52.79#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:04:52.79#ibcon#enter wrdev, iclass 25, count 0 2006.285.09:04:52.79#ibcon#first serial, iclass 25, count 0 2006.285.09:04:52.79#ibcon#enter sib2, iclass 25, count 0 2006.285.09:04:52.79#ibcon#flushed, iclass 25, count 0 2006.285.09:04:52.79#ibcon#about to write, iclass 25, count 0 2006.285.09:04:52.79#ibcon#wrote, iclass 25, count 0 2006.285.09:04:52.79#ibcon#about to read 3, iclass 25, count 0 2006.285.09:04:52.81#ibcon#read 3, iclass 25, count 0 2006.285.09:04:52.81#ibcon#about to read 4, iclass 25, count 0 2006.285.09:04:52.81#ibcon#read 4, iclass 25, count 0 2006.285.09:04:52.81#ibcon#about to read 5, iclass 25, count 0 2006.285.09:04:52.81#ibcon#read 5, iclass 25, count 0 2006.285.09:04:52.81#ibcon#about to read 6, iclass 25, count 0 2006.285.09:04:52.81#ibcon#read 6, iclass 25, count 0 2006.285.09:04:52.81#ibcon#end of sib2, iclass 25, count 0 2006.285.09:04:52.81#ibcon#*mode == 0, iclass 25, count 0 2006.285.09:04:52.81#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.09:04:52.81#ibcon#[25=USB\r\n] 2006.285.09:04:52.81#ibcon#*before write, iclass 25, count 0 2006.285.09:04:52.81#ibcon#enter sib2, iclass 25, count 0 2006.285.09:04:52.81#ibcon#flushed, iclass 25, count 0 2006.285.09:04:52.81#ibcon#about to write, iclass 25, count 0 2006.285.09:04:52.81#ibcon#wrote, iclass 25, count 0 2006.285.09:04:52.81#ibcon#about to read 3, iclass 25, count 0 2006.285.09:04:52.84#ibcon#read 3, iclass 25, count 0 2006.285.09:04:52.84#ibcon#about to read 4, iclass 25, count 0 2006.285.09:04:52.84#ibcon#read 4, iclass 25, count 0 2006.285.09:04:52.84#ibcon#about to read 5, iclass 25, count 0 2006.285.09:04:52.84#ibcon#read 5, iclass 25, count 0 2006.285.09:04:52.84#ibcon#about to read 6, iclass 25, count 0 2006.285.09:04:52.84#ibcon#read 6, iclass 25, count 0 2006.285.09:04:52.84#ibcon#end of sib2, iclass 25, count 0 2006.285.09:04:52.84#ibcon#*after write, iclass 25, count 0 2006.285.09:04:52.84#ibcon#*before return 0, iclass 25, count 0 2006.285.09:04:52.84#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:04:52.84#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:04:52.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.09:04:52.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.09:04:52.84$vck44/valo=5,734.99 2006.285.09:04:52.84#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.09:04:52.84#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.09:04:52.84#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:52.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:04:52.84#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:04:52.84#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:04:52.84#ibcon#enter wrdev, iclass 27, count 0 2006.285.09:04:52.84#ibcon#first serial, iclass 27, count 0 2006.285.09:04:52.84#ibcon#enter sib2, iclass 27, count 0 2006.285.09:04:52.84#ibcon#flushed, iclass 27, count 0 2006.285.09:04:52.84#ibcon#about to write, iclass 27, count 0 2006.285.09:04:52.84#ibcon#wrote, iclass 27, count 0 2006.285.09:04:52.84#ibcon#about to read 3, iclass 27, count 0 2006.285.09:04:52.86#ibcon#read 3, iclass 27, count 0 2006.285.09:04:52.86#ibcon#about to read 4, iclass 27, count 0 2006.285.09:04:52.86#ibcon#read 4, iclass 27, count 0 2006.285.09:04:52.86#ibcon#about to read 5, iclass 27, count 0 2006.285.09:04:52.86#ibcon#read 5, iclass 27, count 0 2006.285.09:04:52.86#ibcon#about to read 6, iclass 27, count 0 2006.285.09:04:52.86#ibcon#read 6, iclass 27, count 0 2006.285.09:04:52.86#ibcon#end of sib2, iclass 27, count 0 2006.285.09:04:52.86#ibcon#*mode == 0, iclass 27, count 0 2006.285.09:04:52.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.09:04:52.86#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:04:52.86#ibcon#*before write, iclass 27, count 0 2006.285.09:04:52.86#ibcon#enter sib2, iclass 27, count 0 2006.285.09:04:52.86#ibcon#flushed, iclass 27, count 0 2006.285.09:04:52.86#ibcon#about to write, iclass 27, count 0 2006.285.09:04:52.86#ibcon#wrote, iclass 27, count 0 2006.285.09:04:52.86#ibcon#about to read 3, iclass 27, count 0 2006.285.09:04:52.90#ibcon#read 3, iclass 27, count 0 2006.285.09:04:52.90#ibcon#about to read 4, iclass 27, count 0 2006.285.09:04:52.90#ibcon#read 4, iclass 27, count 0 2006.285.09:04:52.90#ibcon#about to read 5, iclass 27, count 0 2006.285.09:04:52.90#ibcon#read 5, iclass 27, count 0 2006.285.09:04:52.90#ibcon#about to read 6, iclass 27, count 0 2006.285.09:04:52.90#ibcon#read 6, iclass 27, count 0 2006.285.09:04:52.90#ibcon#end of sib2, iclass 27, count 0 2006.285.09:04:52.90#ibcon#*after write, iclass 27, count 0 2006.285.09:04:52.90#ibcon#*before return 0, iclass 27, count 0 2006.285.09:04:52.90#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:04:52.90#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:04:52.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.09:04:52.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.09:04:52.90$vck44/va=5,3 2006.285.09:04:52.90#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.09:04:52.90#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.09:04:52.90#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:52.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:04:52.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:04:52.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:04:52.96#ibcon#enter wrdev, iclass 29, count 2 2006.285.09:04:52.96#ibcon#first serial, iclass 29, count 2 2006.285.09:04:52.96#ibcon#enter sib2, iclass 29, count 2 2006.285.09:04:52.96#ibcon#flushed, iclass 29, count 2 2006.285.09:04:52.96#ibcon#about to write, iclass 29, count 2 2006.285.09:04:52.96#ibcon#wrote, iclass 29, count 2 2006.285.09:04:52.96#ibcon#about to read 3, iclass 29, count 2 2006.285.09:04:52.98#ibcon#read 3, iclass 29, count 2 2006.285.09:04:52.98#ibcon#about to read 4, iclass 29, count 2 2006.285.09:04:52.98#ibcon#read 4, iclass 29, count 2 2006.285.09:04:52.98#ibcon#about to read 5, iclass 29, count 2 2006.285.09:04:52.98#ibcon#read 5, iclass 29, count 2 2006.285.09:04:52.98#ibcon#about to read 6, iclass 29, count 2 2006.285.09:04:52.98#ibcon#read 6, iclass 29, count 2 2006.285.09:04:52.98#ibcon#end of sib2, iclass 29, count 2 2006.285.09:04:52.98#ibcon#*mode == 0, iclass 29, count 2 2006.285.09:04:52.98#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.09:04:52.98#ibcon#[25=AT05-03\r\n] 2006.285.09:04:52.98#ibcon#*before write, iclass 29, count 2 2006.285.09:04:52.98#ibcon#enter sib2, iclass 29, count 2 2006.285.09:04:52.98#ibcon#flushed, iclass 29, count 2 2006.285.09:04:52.98#ibcon#about to write, iclass 29, count 2 2006.285.09:04:52.98#ibcon#wrote, iclass 29, count 2 2006.285.09:04:52.98#ibcon#about to read 3, iclass 29, count 2 2006.285.09:04:53.01#ibcon#read 3, iclass 29, count 2 2006.285.09:04:53.01#ibcon#about to read 4, iclass 29, count 2 2006.285.09:04:53.01#ibcon#read 4, iclass 29, count 2 2006.285.09:04:53.01#ibcon#about to read 5, iclass 29, count 2 2006.285.09:04:53.01#ibcon#read 5, iclass 29, count 2 2006.285.09:04:53.01#ibcon#about to read 6, iclass 29, count 2 2006.285.09:04:53.01#ibcon#read 6, iclass 29, count 2 2006.285.09:04:53.01#ibcon#end of sib2, iclass 29, count 2 2006.285.09:04:53.01#ibcon#*after write, iclass 29, count 2 2006.285.09:04:53.01#ibcon#*before return 0, iclass 29, count 2 2006.285.09:04:53.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:04:53.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:04:53.01#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.09:04:53.01#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:53.01#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:04:53.13#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:04:53.13#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:04:53.13#ibcon#enter wrdev, iclass 29, count 0 2006.285.09:04:53.13#ibcon#first serial, iclass 29, count 0 2006.285.09:04:53.13#ibcon#enter sib2, iclass 29, count 0 2006.285.09:04:53.13#ibcon#flushed, iclass 29, count 0 2006.285.09:04:53.13#ibcon#about to write, iclass 29, count 0 2006.285.09:04:53.13#ibcon#wrote, iclass 29, count 0 2006.285.09:04:53.13#ibcon#about to read 3, iclass 29, count 0 2006.285.09:04:53.15#ibcon#read 3, iclass 29, count 0 2006.285.09:04:53.15#ibcon#about to read 4, iclass 29, count 0 2006.285.09:04:53.15#ibcon#read 4, iclass 29, count 0 2006.285.09:04:53.15#ibcon#about to read 5, iclass 29, count 0 2006.285.09:04:53.15#ibcon#read 5, iclass 29, count 0 2006.285.09:04:53.15#ibcon#about to read 6, iclass 29, count 0 2006.285.09:04:53.15#ibcon#read 6, iclass 29, count 0 2006.285.09:04:53.15#ibcon#end of sib2, iclass 29, count 0 2006.285.09:04:53.15#ibcon#*mode == 0, iclass 29, count 0 2006.285.09:04:53.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.09:04:53.15#ibcon#[25=USB\r\n] 2006.285.09:04:53.15#ibcon#*before write, iclass 29, count 0 2006.285.09:04:53.15#ibcon#enter sib2, iclass 29, count 0 2006.285.09:04:53.15#ibcon#flushed, iclass 29, count 0 2006.285.09:04:53.15#ibcon#about to write, iclass 29, count 0 2006.285.09:04:53.15#ibcon#wrote, iclass 29, count 0 2006.285.09:04:53.15#ibcon#about to read 3, iclass 29, count 0 2006.285.09:04:53.18#ibcon#read 3, iclass 29, count 0 2006.285.09:04:53.18#ibcon#about to read 4, iclass 29, count 0 2006.285.09:04:53.18#ibcon#read 4, iclass 29, count 0 2006.285.09:04:53.18#ibcon#about to read 5, iclass 29, count 0 2006.285.09:04:53.18#ibcon#read 5, iclass 29, count 0 2006.285.09:04:53.18#ibcon#about to read 6, iclass 29, count 0 2006.285.09:04:53.18#ibcon#read 6, iclass 29, count 0 2006.285.09:04:53.18#ibcon#end of sib2, iclass 29, count 0 2006.285.09:04:53.18#ibcon#*after write, iclass 29, count 0 2006.285.09:04:53.18#ibcon#*before return 0, iclass 29, count 0 2006.285.09:04:53.18#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:04:53.18#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:04:53.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.09:04:53.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.09:04:53.18$vck44/valo=6,814.99 2006.285.09:04:53.18#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.09:04:53.18#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.09:04:53.18#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:53.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:04:53.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:04:53.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:04:53.18#ibcon#enter wrdev, iclass 31, count 0 2006.285.09:04:53.18#ibcon#first serial, iclass 31, count 0 2006.285.09:04:53.18#ibcon#enter sib2, iclass 31, count 0 2006.285.09:04:53.18#ibcon#flushed, iclass 31, count 0 2006.285.09:04:53.18#ibcon#about to write, iclass 31, count 0 2006.285.09:04:53.18#ibcon#wrote, iclass 31, count 0 2006.285.09:04:53.18#ibcon#about to read 3, iclass 31, count 0 2006.285.09:04:53.20#ibcon#read 3, iclass 31, count 0 2006.285.09:04:53.20#ibcon#about to read 4, iclass 31, count 0 2006.285.09:04:53.20#ibcon#read 4, iclass 31, count 0 2006.285.09:04:53.20#ibcon#about to read 5, iclass 31, count 0 2006.285.09:04:53.20#ibcon#read 5, iclass 31, count 0 2006.285.09:04:53.20#ibcon#about to read 6, iclass 31, count 0 2006.285.09:04:53.20#ibcon#read 6, iclass 31, count 0 2006.285.09:04:53.20#ibcon#end of sib2, iclass 31, count 0 2006.285.09:04:53.20#ibcon#*mode == 0, iclass 31, count 0 2006.285.09:04:53.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.09:04:53.20#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:04:53.20#ibcon#*before write, iclass 31, count 0 2006.285.09:04:53.20#ibcon#enter sib2, iclass 31, count 0 2006.285.09:04:53.20#ibcon#flushed, iclass 31, count 0 2006.285.09:04:53.20#ibcon#about to write, iclass 31, count 0 2006.285.09:04:53.20#ibcon#wrote, iclass 31, count 0 2006.285.09:04:53.20#ibcon#about to read 3, iclass 31, count 0 2006.285.09:04:53.24#ibcon#read 3, iclass 31, count 0 2006.285.09:04:53.24#ibcon#about to read 4, iclass 31, count 0 2006.285.09:04:53.24#ibcon#read 4, iclass 31, count 0 2006.285.09:04:53.24#ibcon#about to read 5, iclass 31, count 0 2006.285.09:04:53.24#ibcon#read 5, iclass 31, count 0 2006.285.09:04:53.24#ibcon#about to read 6, iclass 31, count 0 2006.285.09:04:53.24#ibcon#read 6, iclass 31, count 0 2006.285.09:04:53.24#ibcon#end of sib2, iclass 31, count 0 2006.285.09:04:53.24#ibcon#*after write, iclass 31, count 0 2006.285.09:04:53.24#ibcon#*before return 0, iclass 31, count 0 2006.285.09:04:53.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:04:53.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:04:53.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.09:04:53.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.09:04:53.24$vck44/va=6,4 2006.285.09:04:53.24#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.09:04:53.24#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.09:04:53.24#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:53.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:04:53.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:04:53.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:04:53.30#ibcon#enter wrdev, iclass 33, count 2 2006.285.09:04:53.30#ibcon#first serial, iclass 33, count 2 2006.285.09:04:53.30#ibcon#enter sib2, iclass 33, count 2 2006.285.09:04:53.30#ibcon#flushed, iclass 33, count 2 2006.285.09:04:53.30#ibcon#about to write, iclass 33, count 2 2006.285.09:04:53.30#ibcon#wrote, iclass 33, count 2 2006.285.09:04:53.30#ibcon#about to read 3, iclass 33, count 2 2006.285.09:04:53.32#ibcon#read 3, iclass 33, count 2 2006.285.09:04:53.32#ibcon#about to read 4, iclass 33, count 2 2006.285.09:04:53.32#ibcon#read 4, iclass 33, count 2 2006.285.09:04:53.32#ibcon#about to read 5, iclass 33, count 2 2006.285.09:04:53.32#ibcon#read 5, iclass 33, count 2 2006.285.09:04:53.32#ibcon#about to read 6, iclass 33, count 2 2006.285.09:04:53.32#ibcon#read 6, iclass 33, count 2 2006.285.09:04:53.32#ibcon#end of sib2, iclass 33, count 2 2006.285.09:04:53.32#ibcon#*mode == 0, iclass 33, count 2 2006.285.09:04:53.32#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.09:04:53.32#ibcon#[25=AT06-04\r\n] 2006.285.09:04:53.32#ibcon#*before write, iclass 33, count 2 2006.285.09:04:53.32#ibcon#enter sib2, iclass 33, count 2 2006.285.09:04:53.32#ibcon#flushed, iclass 33, count 2 2006.285.09:04:53.32#ibcon#about to write, iclass 33, count 2 2006.285.09:04:53.32#ibcon#wrote, iclass 33, count 2 2006.285.09:04:53.32#ibcon#about to read 3, iclass 33, count 2 2006.285.09:04:53.35#ibcon#read 3, iclass 33, count 2 2006.285.09:04:53.35#ibcon#about to read 4, iclass 33, count 2 2006.285.09:04:53.35#ibcon#read 4, iclass 33, count 2 2006.285.09:04:53.35#ibcon#about to read 5, iclass 33, count 2 2006.285.09:04:53.35#ibcon#read 5, iclass 33, count 2 2006.285.09:04:53.35#ibcon#about to read 6, iclass 33, count 2 2006.285.09:04:53.35#ibcon#read 6, iclass 33, count 2 2006.285.09:04:53.35#ibcon#end of sib2, iclass 33, count 2 2006.285.09:04:53.35#ibcon#*after write, iclass 33, count 2 2006.285.09:04:53.35#ibcon#*before return 0, iclass 33, count 2 2006.285.09:04:53.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:04:53.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:04:53.35#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.09:04:53.35#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:53.35#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:04:53.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:04:53.47#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:04:53.47#ibcon#enter wrdev, iclass 33, count 0 2006.285.09:04:53.47#ibcon#first serial, iclass 33, count 0 2006.285.09:04:53.47#ibcon#enter sib2, iclass 33, count 0 2006.285.09:04:53.47#ibcon#flushed, iclass 33, count 0 2006.285.09:04:53.47#ibcon#about to write, iclass 33, count 0 2006.285.09:04:53.47#ibcon#wrote, iclass 33, count 0 2006.285.09:04:53.47#ibcon#about to read 3, iclass 33, count 0 2006.285.09:04:53.49#ibcon#read 3, iclass 33, count 0 2006.285.09:04:53.49#ibcon#about to read 4, iclass 33, count 0 2006.285.09:04:53.49#ibcon#read 4, iclass 33, count 0 2006.285.09:04:53.49#ibcon#about to read 5, iclass 33, count 0 2006.285.09:04:53.49#ibcon#read 5, iclass 33, count 0 2006.285.09:04:53.49#ibcon#about to read 6, iclass 33, count 0 2006.285.09:04:53.49#ibcon#read 6, iclass 33, count 0 2006.285.09:04:53.49#ibcon#end of sib2, iclass 33, count 0 2006.285.09:04:53.49#ibcon#*mode == 0, iclass 33, count 0 2006.285.09:04:53.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.09:04:53.49#ibcon#[25=USB\r\n] 2006.285.09:04:53.49#ibcon#*before write, iclass 33, count 0 2006.285.09:04:53.49#ibcon#enter sib2, iclass 33, count 0 2006.285.09:04:53.49#ibcon#flushed, iclass 33, count 0 2006.285.09:04:53.49#ibcon#about to write, iclass 33, count 0 2006.285.09:04:53.49#ibcon#wrote, iclass 33, count 0 2006.285.09:04:53.49#ibcon#about to read 3, iclass 33, count 0 2006.285.09:04:53.52#ibcon#read 3, iclass 33, count 0 2006.285.09:04:53.52#ibcon#about to read 4, iclass 33, count 0 2006.285.09:04:53.52#ibcon#read 4, iclass 33, count 0 2006.285.09:04:53.52#ibcon#about to read 5, iclass 33, count 0 2006.285.09:04:53.52#ibcon#read 5, iclass 33, count 0 2006.285.09:04:53.52#ibcon#about to read 6, iclass 33, count 0 2006.285.09:04:53.52#ibcon#read 6, iclass 33, count 0 2006.285.09:04:53.52#ibcon#end of sib2, iclass 33, count 0 2006.285.09:04:53.52#ibcon#*after write, iclass 33, count 0 2006.285.09:04:53.52#ibcon#*before return 0, iclass 33, count 0 2006.285.09:04:53.52#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:04:53.52#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:04:53.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.09:04:53.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.09:04:53.52$vck44/valo=7,864.99 2006.285.09:04:53.52#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.09:04:53.52#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.09:04:53.52#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:53.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:04:53.52#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:04:53.52#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:04:53.52#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:04:53.52#ibcon#first serial, iclass 35, count 0 2006.285.09:04:53.52#ibcon#enter sib2, iclass 35, count 0 2006.285.09:04:53.52#ibcon#flushed, iclass 35, count 0 2006.285.09:04:53.52#ibcon#about to write, iclass 35, count 0 2006.285.09:04:53.52#ibcon#wrote, iclass 35, count 0 2006.285.09:04:53.52#ibcon#about to read 3, iclass 35, count 0 2006.285.09:04:53.54#ibcon#read 3, iclass 35, count 0 2006.285.09:04:53.54#ibcon#about to read 4, iclass 35, count 0 2006.285.09:04:53.54#ibcon#read 4, iclass 35, count 0 2006.285.09:04:53.54#ibcon#about to read 5, iclass 35, count 0 2006.285.09:04:53.54#ibcon#read 5, iclass 35, count 0 2006.285.09:04:53.54#ibcon#about to read 6, iclass 35, count 0 2006.285.09:04:53.54#ibcon#read 6, iclass 35, count 0 2006.285.09:04:53.54#ibcon#end of sib2, iclass 35, count 0 2006.285.09:04:53.54#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:04:53.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:04:53.54#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:04:53.54#ibcon#*before write, iclass 35, count 0 2006.285.09:04:53.54#ibcon#enter sib2, iclass 35, count 0 2006.285.09:04:53.54#ibcon#flushed, iclass 35, count 0 2006.285.09:04:53.54#ibcon#about to write, iclass 35, count 0 2006.285.09:04:53.54#ibcon#wrote, iclass 35, count 0 2006.285.09:04:53.54#ibcon#about to read 3, iclass 35, count 0 2006.285.09:04:53.58#ibcon#read 3, iclass 35, count 0 2006.285.09:04:53.58#ibcon#about to read 4, iclass 35, count 0 2006.285.09:04:53.58#ibcon#read 4, iclass 35, count 0 2006.285.09:04:53.58#ibcon#about to read 5, iclass 35, count 0 2006.285.09:04:53.58#ibcon#read 5, iclass 35, count 0 2006.285.09:04:53.58#ibcon#about to read 6, iclass 35, count 0 2006.285.09:04:53.58#ibcon#read 6, iclass 35, count 0 2006.285.09:04:53.58#ibcon#end of sib2, iclass 35, count 0 2006.285.09:04:53.58#ibcon#*after write, iclass 35, count 0 2006.285.09:04:53.58#ibcon#*before return 0, iclass 35, count 0 2006.285.09:04:53.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:04:53.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:04:53.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:04:53.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:04:53.58$vck44/va=7,4 2006.285.09:04:53.58#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.09:04:53.58#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.09:04:53.58#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:53.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:04:53.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:04:53.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:04:53.64#ibcon#enter wrdev, iclass 37, count 2 2006.285.09:04:53.64#ibcon#first serial, iclass 37, count 2 2006.285.09:04:53.64#ibcon#enter sib2, iclass 37, count 2 2006.285.09:04:53.64#ibcon#flushed, iclass 37, count 2 2006.285.09:04:53.64#ibcon#about to write, iclass 37, count 2 2006.285.09:04:53.64#ibcon#wrote, iclass 37, count 2 2006.285.09:04:53.64#ibcon#about to read 3, iclass 37, count 2 2006.285.09:04:53.66#ibcon#read 3, iclass 37, count 2 2006.285.09:04:53.66#ibcon#about to read 4, iclass 37, count 2 2006.285.09:04:53.66#ibcon#read 4, iclass 37, count 2 2006.285.09:04:53.66#ibcon#about to read 5, iclass 37, count 2 2006.285.09:04:53.66#ibcon#read 5, iclass 37, count 2 2006.285.09:04:53.66#ibcon#about to read 6, iclass 37, count 2 2006.285.09:04:53.66#ibcon#read 6, iclass 37, count 2 2006.285.09:04:53.66#ibcon#end of sib2, iclass 37, count 2 2006.285.09:04:53.66#ibcon#*mode == 0, iclass 37, count 2 2006.285.09:04:53.66#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.09:04:53.66#ibcon#[25=AT07-04\r\n] 2006.285.09:04:53.66#ibcon#*before write, iclass 37, count 2 2006.285.09:04:53.66#ibcon#enter sib2, iclass 37, count 2 2006.285.09:04:53.66#ibcon#flushed, iclass 37, count 2 2006.285.09:04:53.66#ibcon#about to write, iclass 37, count 2 2006.285.09:04:53.66#ibcon#wrote, iclass 37, count 2 2006.285.09:04:53.66#ibcon#about to read 3, iclass 37, count 2 2006.285.09:04:53.69#ibcon#read 3, iclass 37, count 2 2006.285.09:04:53.69#ibcon#about to read 4, iclass 37, count 2 2006.285.09:04:53.69#ibcon#read 4, iclass 37, count 2 2006.285.09:04:53.69#ibcon#about to read 5, iclass 37, count 2 2006.285.09:04:53.69#ibcon#read 5, iclass 37, count 2 2006.285.09:04:53.69#ibcon#about to read 6, iclass 37, count 2 2006.285.09:04:53.69#ibcon#read 6, iclass 37, count 2 2006.285.09:04:53.69#ibcon#end of sib2, iclass 37, count 2 2006.285.09:04:53.69#ibcon#*after write, iclass 37, count 2 2006.285.09:04:53.69#ibcon#*before return 0, iclass 37, count 2 2006.285.09:04:53.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:04:53.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:04:53.69#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.09:04:53.69#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:53.69#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:04:53.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:04:53.81#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:04:53.81#ibcon#enter wrdev, iclass 37, count 0 2006.285.09:04:53.81#ibcon#first serial, iclass 37, count 0 2006.285.09:04:53.81#ibcon#enter sib2, iclass 37, count 0 2006.285.09:04:53.81#ibcon#flushed, iclass 37, count 0 2006.285.09:04:53.81#ibcon#about to write, iclass 37, count 0 2006.285.09:04:53.81#ibcon#wrote, iclass 37, count 0 2006.285.09:04:53.81#ibcon#about to read 3, iclass 37, count 0 2006.285.09:04:53.83#ibcon#read 3, iclass 37, count 0 2006.285.09:04:53.83#ibcon#about to read 4, iclass 37, count 0 2006.285.09:04:53.83#ibcon#read 4, iclass 37, count 0 2006.285.09:04:53.83#ibcon#about to read 5, iclass 37, count 0 2006.285.09:04:53.83#ibcon#read 5, iclass 37, count 0 2006.285.09:04:53.83#ibcon#about to read 6, iclass 37, count 0 2006.285.09:04:53.83#ibcon#read 6, iclass 37, count 0 2006.285.09:04:53.83#ibcon#end of sib2, iclass 37, count 0 2006.285.09:04:53.83#ibcon#*mode == 0, iclass 37, count 0 2006.285.09:04:53.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.09:04:53.83#ibcon#[25=USB\r\n] 2006.285.09:04:53.83#ibcon#*before write, iclass 37, count 0 2006.285.09:04:53.83#ibcon#enter sib2, iclass 37, count 0 2006.285.09:04:53.83#ibcon#flushed, iclass 37, count 0 2006.285.09:04:53.83#ibcon#about to write, iclass 37, count 0 2006.285.09:04:53.83#ibcon#wrote, iclass 37, count 0 2006.285.09:04:53.83#ibcon#about to read 3, iclass 37, count 0 2006.285.09:04:53.86#ibcon#read 3, iclass 37, count 0 2006.285.09:04:53.86#ibcon#about to read 4, iclass 37, count 0 2006.285.09:04:53.86#ibcon#read 4, iclass 37, count 0 2006.285.09:04:53.86#ibcon#about to read 5, iclass 37, count 0 2006.285.09:04:53.86#ibcon#read 5, iclass 37, count 0 2006.285.09:04:53.86#ibcon#about to read 6, iclass 37, count 0 2006.285.09:04:53.86#ibcon#read 6, iclass 37, count 0 2006.285.09:04:53.86#ibcon#end of sib2, iclass 37, count 0 2006.285.09:04:53.86#ibcon#*after write, iclass 37, count 0 2006.285.09:04:53.86#ibcon#*before return 0, iclass 37, count 0 2006.285.09:04:53.86#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:04:53.86#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:04:53.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.09:04:53.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.09:04:53.86$vck44/valo=8,884.99 2006.285.09:04:53.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.09:04:53.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.09:04:53.86#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:53.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:04:53.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:04:53.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:04:53.86#ibcon#enter wrdev, iclass 39, count 0 2006.285.09:04:53.86#ibcon#first serial, iclass 39, count 0 2006.285.09:04:53.86#ibcon#enter sib2, iclass 39, count 0 2006.285.09:04:53.86#ibcon#flushed, iclass 39, count 0 2006.285.09:04:53.86#ibcon#about to write, iclass 39, count 0 2006.285.09:04:53.86#ibcon#wrote, iclass 39, count 0 2006.285.09:04:53.86#ibcon#about to read 3, iclass 39, count 0 2006.285.09:04:53.88#ibcon#read 3, iclass 39, count 0 2006.285.09:04:53.88#ibcon#about to read 4, iclass 39, count 0 2006.285.09:04:53.88#ibcon#read 4, iclass 39, count 0 2006.285.09:04:53.88#ibcon#about to read 5, iclass 39, count 0 2006.285.09:04:53.88#ibcon#read 5, iclass 39, count 0 2006.285.09:04:53.88#ibcon#about to read 6, iclass 39, count 0 2006.285.09:04:53.88#ibcon#read 6, iclass 39, count 0 2006.285.09:04:53.88#ibcon#end of sib2, iclass 39, count 0 2006.285.09:04:53.88#ibcon#*mode == 0, iclass 39, count 0 2006.285.09:04:53.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.09:04:53.88#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:04:53.88#ibcon#*before write, iclass 39, count 0 2006.285.09:04:53.88#ibcon#enter sib2, iclass 39, count 0 2006.285.09:04:53.88#ibcon#flushed, iclass 39, count 0 2006.285.09:04:53.88#ibcon#about to write, iclass 39, count 0 2006.285.09:04:53.88#ibcon#wrote, iclass 39, count 0 2006.285.09:04:53.88#ibcon#about to read 3, iclass 39, count 0 2006.285.09:04:53.92#ibcon#read 3, iclass 39, count 0 2006.285.09:04:53.92#ibcon#about to read 4, iclass 39, count 0 2006.285.09:04:53.92#ibcon#read 4, iclass 39, count 0 2006.285.09:04:53.92#ibcon#about to read 5, iclass 39, count 0 2006.285.09:04:53.92#ibcon#read 5, iclass 39, count 0 2006.285.09:04:53.92#ibcon#about to read 6, iclass 39, count 0 2006.285.09:04:53.92#ibcon#read 6, iclass 39, count 0 2006.285.09:04:53.92#ibcon#end of sib2, iclass 39, count 0 2006.285.09:04:53.92#ibcon#*after write, iclass 39, count 0 2006.285.09:04:53.92#ibcon#*before return 0, iclass 39, count 0 2006.285.09:04:53.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:04:53.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:04:53.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.09:04:53.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.09:04:53.92$vck44/va=8,3 2006.285.09:04:53.92#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.09:04:53.92#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.09:04:53.92#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:53.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:04:53.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:04:53.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:04:53.98#ibcon#enter wrdev, iclass 3, count 2 2006.285.09:04:53.98#ibcon#first serial, iclass 3, count 2 2006.285.09:04:53.98#ibcon#enter sib2, iclass 3, count 2 2006.285.09:04:53.98#ibcon#flushed, iclass 3, count 2 2006.285.09:04:53.98#ibcon#about to write, iclass 3, count 2 2006.285.09:04:53.98#ibcon#wrote, iclass 3, count 2 2006.285.09:04:53.98#ibcon#about to read 3, iclass 3, count 2 2006.285.09:04:54.00#ibcon#read 3, iclass 3, count 2 2006.285.09:04:54.00#ibcon#about to read 4, iclass 3, count 2 2006.285.09:04:54.00#ibcon#read 4, iclass 3, count 2 2006.285.09:04:54.00#ibcon#about to read 5, iclass 3, count 2 2006.285.09:04:54.00#ibcon#read 5, iclass 3, count 2 2006.285.09:04:54.00#ibcon#about to read 6, iclass 3, count 2 2006.285.09:04:54.00#ibcon#read 6, iclass 3, count 2 2006.285.09:04:54.00#ibcon#end of sib2, iclass 3, count 2 2006.285.09:04:54.00#ibcon#*mode == 0, iclass 3, count 2 2006.285.09:04:54.00#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.09:04:54.00#ibcon#[25=AT08-03\r\n] 2006.285.09:04:54.00#ibcon#*before write, iclass 3, count 2 2006.285.09:04:54.00#ibcon#enter sib2, iclass 3, count 2 2006.285.09:04:54.00#ibcon#flushed, iclass 3, count 2 2006.285.09:04:54.00#ibcon#about to write, iclass 3, count 2 2006.285.09:04:54.00#ibcon#wrote, iclass 3, count 2 2006.285.09:04:54.00#ibcon#about to read 3, iclass 3, count 2 2006.285.09:04:54.03#ibcon#read 3, iclass 3, count 2 2006.285.09:04:54.03#ibcon#about to read 4, iclass 3, count 2 2006.285.09:04:54.03#ibcon#read 4, iclass 3, count 2 2006.285.09:04:54.03#ibcon#about to read 5, iclass 3, count 2 2006.285.09:04:54.03#ibcon#read 5, iclass 3, count 2 2006.285.09:04:54.03#ibcon#about to read 6, iclass 3, count 2 2006.285.09:04:54.03#ibcon#read 6, iclass 3, count 2 2006.285.09:04:54.03#ibcon#end of sib2, iclass 3, count 2 2006.285.09:04:54.03#ibcon#*after write, iclass 3, count 2 2006.285.09:04:54.03#ibcon#*before return 0, iclass 3, count 2 2006.285.09:04:54.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:04:54.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:04:54.03#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.09:04:54.03#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:54.03#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:04:54.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:04:54.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:04:54.15#ibcon#enter wrdev, iclass 3, count 0 2006.285.09:04:54.15#ibcon#first serial, iclass 3, count 0 2006.285.09:04:54.15#ibcon#enter sib2, iclass 3, count 0 2006.285.09:04:54.15#ibcon#flushed, iclass 3, count 0 2006.285.09:04:54.15#ibcon#about to write, iclass 3, count 0 2006.285.09:04:54.15#ibcon#wrote, iclass 3, count 0 2006.285.09:04:54.15#ibcon#about to read 3, iclass 3, count 0 2006.285.09:04:54.17#ibcon#read 3, iclass 3, count 0 2006.285.09:04:54.17#ibcon#about to read 4, iclass 3, count 0 2006.285.09:04:54.17#ibcon#read 4, iclass 3, count 0 2006.285.09:04:54.17#ibcon#about to read 5, iclass 3, count 0 2006.285.09:04:54.17#ibcon#read 5, iclass 3, count 0 2006.285.09:04:54.17#ibcon#about to read 6, iclass 3, count 0 2006.285.09:04:54.17#ibcon#read 6, iclass 3, count 0 2006.285.09:04:54.17#ibcon#end of sib2, iclass 3, count 0 2006.285.09:04:54.17#ibcon#*mode == 0, iclass 3, count 0 2006.285.09:04:54.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.09:04:54.17#ibcon#[25=USB\r\n] 2006.285.09:04:54.17#ibcon#*before write, iclass 3, count 0 2006.285.09:04:54.17#ibcon#enter sib2, iclass 3, count 0 2006.285.09:04:54.17#ibcon#flushed, iclass 3, count 0 2006.285.09:04:54.17#ibcon#about to write, iclass 3, count 0 2006.285.09:04:54.17#ibcon#wrote, iclass 3, count 0 2006.285.09:04:54.17#ibcon#about to read 3, iclass 3, count 0 2006.285.09:04:54.20#ibcon#read 3, iclass 3, count 0 2006.285.09:04:54.20#ibcon#about to read 4, iclass 3, count 0 2006.285.09:04:54.20#ibcon#read 4, iclass 3, count 0 2006.285.09:04:54.20#ibcon#about to read 5, iclass 3, count 0 2006.285.09:04:54.20#ibcon#read 5, iclass 3, count 0 2006.285.09:04:54.20#ibcon#about to read 6, iclass 3, count 0 2006.285.09:04:54.20#ibcon#read 6, iclass 3, count 0 2006.285.09:04:54.20#ibcon#end of sib2, iclass 3, count 0 2006.285.09:04:54.20#ibcon#*after write, iclass 3, count 0 2006.285.09:04:54.20#ibcon#*before return 0, iclass 3, count 0 2006.285.09:04:54.20#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:04:54.20#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:04:54.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.09:04:54.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.09:04:54.20$vck44/vblo=1,629.99 2006.285.09:04:54.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.09:04:54.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.09:04:54.20#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:54.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:04:54.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:04:54.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:04:54.20#ibcon#enter wrdev, iclass 5, count 0 2006.285.09:04:54.20#ibcon#first serial, iclass 5, count 0 2006.285.09:04:54.20#ibcon#enter sib2, iclass 5, count 0 2006.285.09:04:54.20#ibcon#flushed, iclass 5, count 0 2006.285.09:04:54.20#ibcon#about to write, iclass 5, count 0 2006.285.09:04:54.20#ibcon#wrote, iclass 5, count 0 2006.285.09:04:54.20#ibcon#about to read 3, iclass 5, count 0 2006.285.09:04:54.22#ibcon#read 3, iclass 5, count 0 2006.285.09:04:54.22#ibcon#about to read 4, iclass 5, count 0 2006.285.09:04:54.22#ibcon#read 4, iclass 5, count 0 2006.285.09:04:54.22#ibcon#about to read 5, iclass 5, count 0 2006.285.09:04:54.22#ibcon#read 5, iclass 5, count 0 2006.285.09:04:54.22#ibcon#about to read 6, iclass 5, count 0 2006.285.09:04:54.22#ibcon#read 6, iclass 5, count 0 2006.285.09:04:54.22#ibcon#end of sib2, iclass 5, count 0 2006.285.09:04:54.22#ibcon#*mode == 0, iclass 5, count 0 2006.285.09:04:54.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.09:04:54.22#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:04:54.22#ibcon#*before write, iclass 5, count 0 2006.285.09:04:54.22#ibcon#enter sib2, iclass 5, count 0 2006.285.09:04:54.22#ibcon#flushed, iclass 5, count 0 2006.285.09:04:54.22#ibcon#about to write, iclass 5, count 0 2006.285.09:04:54.22#ibcon#wrote, iclass 5, count 0 2006.285.09:04:54.22#ibcon#about to read 3, iclass 5, count 0 2006.285.09:04:54.26#ibcon#read 3, iclass 5, count 0 2006.285.09:04:54.26#ibcon#about to read 4, iclass 5, count 0 2006.285.09:04:54.26#ibcon#read 4, iclass 5, count 0 2006.285.09:04:54.26#ibcon#about to read 5, iclass 5, count 0 2006.285.09:04:54.26#ibcon#read 5, iclass 5, count 0 2006.285.09:04:54.26#ibcon#about to read 6, iclass 5, count 0 2006.285.09:04:54.26#ibcon#read 6, iclass 5, count 0 2006.285.09:04:54.26#ibcon#end of sib2, iclass 5, count 0 2006.285.09:04:54.26#ibcon#*after write, iclass 5, count 0 2006.285.09:04:54.26#ibcon#*before return 0, iclass 5, count 0 2006.285.09:04:54.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:04:54.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:04:54.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.09:04:54.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.09:04:54.26$vck44/vb=1,4 2006.285.09:04:54.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.09:04:54.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.09:04:54.26#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:54.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:04:54.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:04:54.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:04:54.26#ibcon#enter wrdev, iclass 7, count 2 2006.285.09:04:54.26#ibcon#first serial, iclass 7, count 2 2006.285.09:04:54.26#ibcon#enter sib2, iclass 7, count 2 2006.285.09:04:54.26#ibcon#flushed, iclass 7, count 2 2006.285.09:04:54.26#ibcon#about to write, iclass 7, count 2 2006.285.09:04:54.26#ibcon#wrote, iclass 7, count 2 2006.285.09:04:54.26#ibcon#about to read 3, iclass 7, count 2 2006.285.09:04:54.28#ibcon#read 3, iclass 7, count 2 2006.285.09:04:54.28#ibcon#about to read 4, iclass 7, count 2 2006.285.09:04:54.28#ibcon#read 4, iclass 7, count 2 2006.285.09:04:54.28#ibcon#about to read 5, iclass 7, count 2 2006.285.09:04:54.28#ibcon#read 5, iclass 7, count 2 2006.285.09:04:54.28#ibcon#about to read 6, iclass 7, count 2 2006.285.09:04:54.28#ibcon#read 6, iclass 7, count 2 2006.285.09:04:54.28#ibcon#end of sib2, iclass 7, count 2 2006.285.09:04:54.28#ibcon#*mode == 0, iclass 7, count 2 2006.285.09:04:54.28#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.09:04:54.28#ibcon#[27=AT01-04\r\n] 2006.285.09:04:54.28#ibcon#*before write, iclass 7, count 2 2006.285.09:04:54.28#ibcon#enter sib2, iclass 7, count 2 2006.285.09:04:54.28#ibcon#flushed, iclass 7, count 2 2006.285.09:04:54.28#ibcon#about to write, iclass 7, count 2 2006.285.09:04:54.28#ibcon#wrote, iclass 7, count 2 2006.285.09:04:54.28#ibcon#about to read 3, iclass 7, count 2 2006.285.09:04:54.31#ibcon#read 3, iclass 7, count 2 2006.285.09:04:54.31#ibcon#about to read 4, iclass 7, count 2 2006.285.09:04:54.31#ibcon#read 4, iclass 7, count 2 2006.285.09:04:54.31#ibcon#about to read 5, iclass 7, count 2 2006.285.09:04:54.31#ibcon#read 5, iclass 7, count 2 2006.285.09:04:54.31#ibcon#about to read 6, iclass 7, count 2 2006.285.09:04:54.31#ibcon#read 6, iclass 7, count 2 2006.285.09:04:54.31#ibcon#end of sib2, iclass 7, count 2 2006.285.09:04:54.31#ibcon#*after write, iclass 7, count 2 2006.285.09:04:54.31#ibcon#*before return 0, iclass 7, count 2 2006.285.09:04:54.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:04:54.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:04:54.31#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.09:04:54.31#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:54.31#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:04:54.43#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:04:54.43#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:04:54.43#ibcon#enter wrdev, iclass 7, count 0 2006.285.09:04:54.43#ibcon#first serial, iclass 7, count 0 2006.285.09:04:54.43#ibcon#enter sib2, iclass 7, count 0 2006.285.09:04:54.43#ibcon#flushed, iclass 7, count 0 2006.285.09:04:54.43#ibcon#about to write, iclass 7, count 0 2006.285.09:04:54.43#ibcon#wrote, iclass 7, count 0 2006.285.09:04:54.43#ibcon#about to read 3, iclass 7, count 0 2006.285.09:04:54.45#ibcon#read 3, iclass 7, count 0 2006.285.09:04:54.45#ibcon#about to read 4, iclass 7, count 0 2006.285.09:04:54.45#ibcon#read 4, iclass 7, count 0 2006.285.09:04:54.45#ibcon#about to read 5, iclass 7, count 0 2006.285.09:04:54.45#ibcon#read 5, iclass 7, count 0 2006.285.09:04:54.45#ibcon#about to read 6, iclass 7, count 0 2006.285.09:04:54.45#ibcon#read 6, iclass 7, count 0 2006.285.09:04:54.45#ibcon#end of sib2, iclass 7, count 0 2006.285.09:04:54.45#ibcon#*mode == 0, iclass 7, count 0 2006.285.09:04:54.45#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.09:04:54.45#ibcon#[27=USB\r\n] 2006.285.09:04:54.45#ibcon#*before write, iclass 7, count 0 2006.285.09:04:54.45#ibcon#enter sib2, iclass 7, count 0 2006.285.09:04:54.45#ibcon#flushed, iclass 7, count 0 2006.285.09:04:54.45#ibcon#about to write, iclass 7, count 0 2006.285.09:04:54.45#ibcon#wrote, iclass 7, count 0 2006.285.09:04:54.45#ibcon#about to read 3, iclass 7, count 0 2006.285.09:04:54.48#ibcon#read 3, iclass 7, count 0 2006.285.09:04:54.48#ibcon#about to read 4, iclass 7, count 0 2006.285.09:04:54.48#ibcon#read 4, iclass 7, count 0 2006.285.09:04:54.48#ibcon#about to read 5, iclass 7, count 0 2006.285.09:04:54.48#ibcon#read 5, iclass 7, count 0 2006.285.09:04:54.48#ibcon#about to read 6, iclass 7, count 0 2006.285.09:04:54.48#ibcon#read 6, iclass 7, count 0 2006.285.09:04:54.48#ibcon#end of sib2, iclass 7, count 0 2006.285.09:04:54.48#ibcon#*after write, iclass 7, count 0 2006.285.09:04:54.48#ibcon#*before return 0, iclass 7, count 0 2006.285.09:04:54.48#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:04:54.48#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:04:54.48#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.09:04:54.48#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.09:04:54.48$vck44/vblo=2,634.99 2006.285.09:04:54.48#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.09:04:54.48#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.09:04:54.48#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:54.48#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:04:54.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:04:54.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:04:54.48#ibcon#enter wrdev, iclass 11, count 0 2006.285.09:04:54.48#ibcon#first serial, iclass 11, count 0 2006.285.09:04:54.48#ibcon#enter sib2, iclass 11, count 0 2006.285.09:04:54.48#ibcon#flushed, iclass 11, count 0 2006.285.09:04:54.48#ibcon#about to write, iclass 11, count 0 2006.285.09:04:54.48#ibcon#wrote, iclass 11, count 0 2006.285.09:04:54.48#ibcon#about to read 3, iclass 11, count 0 2006.285.09:04:54.50#ibcon#read 3, iclass 11, count 0 2006.285.09:04:54.50#ibcon#about to read 4, iclass 11, count 0 2006.285.09:04:54.50#ibcon#read 4, iclass 11, count 0 2006.285.09:04:54.50#ibcon#about to read 5, iclass 11, count 0 2006.285.09:04:54.50#ibcon#read 5, iclass 11, count 0 2006.285.09:04:54.50#ibcon#about to read 6, iclass 11, count 0 2006.285.09:04:54.50#ibcon#read 6, iclass 11, count 0 2006.285.09:04:54.50#ibcon#end of sib2, iclass 11, count 0 2006.285.09:04:54.50#ibcon#*mode == 0, iclass 11, count 0 2006.285.09:04:54.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.09:04:54.50#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:04:54.50#ibcon#*before write, iclass 11, count 0 2006.285.09:04:54.50#ibcon#enter sib2, iclass 11, count 0 2006.285.09:04:54.50#ibcon#flushed, iclass 11, count 0 2006.285.09:04:54.50#ibcon#about to write, iclass 11, count 0 2006.285.09:04:54.50#ibcon#wrote, iclass 11, count 0 2006.285.09:04:54.50#ibcon#about to read 3, iclass 11, count 0 2006.285.09:04:54.54#ibcon#read 3, iclass 11, count 0 2006.285.09:04:54.54#ibcon#about to read 4, iclass 11, count 0 2006.285.09:04:54.54#ibcon#read 4, iclass 11, count 0 2006.285.09:04:54.54#ibcon#about to read 5, iclass 11, count 0 2006.285.09:04:54.54#ibcon#read 5, iclass 11, count 0 2006.285.09:04:54.54#ibcon#about to read 6, iclass 11, count 0 2006.285.09:04:54.54#ibcon#read 6, iclass 11, count 0 2006.285.09:04:54.54#ibcon#end of sib2, iclass 11, count 0 2006.285.09:04:54.54#ibcon#*after write, iclass 11, count 0 2006.285.09:04:54.54#ibcon#*before return 0, iclass 11, count 0 2006.285.09:04:54.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:04:54.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:04:54.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.09:04:54.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.09:04:54.54$vck44/vb=2,5 2006.285.09:04:54.54#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.09:04:54.54#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.09:04:54.54#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:54.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:04:54.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:04:54.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:04:54.60#ibcon#enter wrdev, iclass 13, count 2 2006.285.09:04:54.60#ibcon#first serial, iclass 13, count 2 2006.285.09:04:54.60#ibcon#enter sib2, iclass 13, count 2 2006.285.09:04:54.60#ibcon#flushed, iclass 13, count 2 2006.285.09:04:54.60#ibcon#about to write, iclass 13, count 2 2006.285.09:04:54.60#ibcon#wrote, iclass 13, count 2 2006.285.09:04:54.60#ibcon#about to read 3, iclass 13, count 2 2006.285.09:04:54.62#ibcon#read 3, iclass 13, count 2 2006.285.09:04:54.62#ibcon#about to read 4, iclass 13, count 2 2006.285.09:04:54.62#ibcon#read 4, iclass 13, count 2 2006.285.09:04:54.62#ibcon#about to read 5, iclass 13, count 2 2006.285.09:04:54.62#ibcon#read 5, iclass 13, count 2 2006.285.09:04:54.62#ibcon#about to read 6, iclass 13, count 2 2006.285.09:04:54.62#ibcon#read 6, iclass 13, count 2 2006.285.09:04:54.62#ibcon#end of sib2, iclass 13, count 2 2006.285.09:04:54.62#ibcon#*mode == 0, iclass 13, count 2 2006.285.09:04:54.62#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.09:04:54.62#ibcon#[27=AT02-05\r\n] 2006.285.09:04:54.62#ibcon#*before write, iclass 13, count 2 2006.285.09:04:54.62#ibcon#enter sib2, iclass 13, count 2 2006.285.09:04:54.62#ibcon#flushed, iclass 13, count 2 2006.285.09:04:54.62#ibcon#about to write, iclass 13, count 2 2006.285.09:04:54.62#ibcon#wrote, iclass 13, count 2 2006.285.09:04:54.62#ibcon#about to read 3, iclass 13, count 2 2006.285.09:04:54.65#ibcon#read 3, iclass 13, count 2 2006.285.09:04:54.65#ibcon#about to read 4, iclass 13, count 2 2006.285.09:04:54.65#ibcon#read 4, iclass 13, count 2 2006.285.09:04:54.65#ibcon#about to read 5, iclass 13, count 2 2006.285.09:04:54.65#ibcon#read 5, iclass 13, count 2 2006.285.09:04:54.65#ibcon#about to read 6, iclass 13, count 2 2006.285.09:04:54.65#ibcon#read 6, iclass 13, count 2 2006.285.09:04:54.65#ibcon#end of sib2, iclass 13, count 2 2006.285.09:04:54.65#ibcon#*after write, iclass 13, count 2 2006.285.09:04:54.65#ibcon#*before return 0, iclass 13, count 2 2006.285.09:04:54.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:04:54.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:04:54.65#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.09:04:54.65#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:54.65#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:04:54.77#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:04:54.77#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:04:54.77#ibcon#enter wrdev, iclass 13, count 0 2006.285.09:04:54.77#ibcon#first serial, iclass 13, count 0 2006.285.09:04:54.77#ibcon#enter sib2, iclass 13, count 0 2006.285.09:04:54.77#ibcon#flushed, iclass 13, count 0 2006.285.09:04:54.77#ibcon#about to write, iclass 13, count 0 2006.285.09:04:54.77#ibcon#wrote, iclass 13, count 0 2006.285.09:04:54.77#ibcon#about to read 3, iclass 13, count 0 2006.285.09:04:54.79#ibcon#read 3, iclass 13, count 0 2006.285.09:04:54.79#ibcon#about to read 4, iclass 13, count 0 2006.285.09:04:54.79#ibcon#read 4, iclass 13, count 0 2006.285.09:04:54.79#ibcon#about to read 5, iclass 13, count 0 2006.285.09:04:54.79#ibcon#read 5, iclass 13, count 0 2006.285.09:04:54.79#ibcon#about to read 6, iclass 13, count 0 2006.285.09:04:54.79#ibcon#read 6, iclass 13, count 0 2006.285.09:04:54.79#ibcon#end of sib2, iclass 13, count 0 2006.285.09:04:54.79#ibcon#*mode == 0, iclass 13, count 0 2006.285.09:04:54.79#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.09:04:54.79#ibcon#[27=USB\r\n] 2006.285.09:04:54.79#ibcon#*before write, iclass 13, count 0 2006.285.09:04:54.79#ibcon#enter sib2, iclass 13, count 0 2006.285.09:04:54.79#ibcon#flushed, iclass 13, count 0 2006.285.09:04:54.79#ibcon#about to write, iclass 13, count 0 2006.285.09:04:54.79#ibcon#wrote, iclass 13, count 0 2006.285.09:04:54.79#ibcon#about to read 3, iclass 13, count 0 2006.285.09:04:54.82#ibcon#read 3, iclass 13, count 0 2006.285.09:04:54.82#ibcon#about to read 4, iclass 13, count 0 2006.285.09:04:54.82#ibcon#read 4, iclass 13, count 0 2006.285.09:04:54.82#ibcon#about to read 5, iclass 13, count 0 2006.285.09:04:54.82#ibcon#read 5, iclass 13, count 0 2006.285.09:04:54.82#ibcon#about to read 6, iclass 13, count 0 2006.285.09:04:54.82#ibcon#read 6, iclass 13, count 0 2006.285.09:04:54.82#ibcon#end of sib2, iclass 13, count 0 2006.285.09:04:54.82#ibcon#*after write, iclass 13, count 0 2006.285.09:04:54.82#ibcon#*before return 0, iclass 13, count 0 2006.285.09:04:54.82#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:04:54.82#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:04:54.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.09:04:54.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.09:04:54.82$vck44/vblo=3,649.99 2006.285.09:04:54.82#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.09:04:54.82#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.09:04:54.82#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:54.82#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:04:54.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:04:54.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:04:54.82#ibcon#enter wrdev, iclass 15, count 0 2006.285.09:04:54.82#ibcon#first serial, iclass 15, count 0 2006.285.09:04:54.82#ibcon#enter sib2, iclass 15, count 0 2006.285.09:04:54.82#ibcon#flushed, iclass 15, count 0 2006.285.09:04:54.82#ibcon#about to write, iclass 15, count 0 2006.285.09:04:54.82#ibcon#wrote, iclass 15, count 0 2006.285.09:04:54.82#ibcon#about to read 3, iclass 15, count 0 2006.285.09:04:54.84#ibcon#read 3, iclass 15, count 0 2006.285.09:04:54.84#ibcon#about to read 4, iclass 15, count 0 2006.285.09:04:54.84#ibcon#read 4, iclass 15, count 0 2006.285.09:04:54.84#ibcon#about to read 5, iclass 15, count 0 2006.285.09:04:54.84#ibcon#read 5, iclass 15, count 0 2006.285.09:04:54.84#ibcon#about to read 6, iclass 15, count 0 2006.285.09:04:54.84#ibcon#read 6, iclass 15, count 0 2006.285.09:04:54.84#ibcon#end of sib2, iclass 15, count 0 2006.285.09:04:54.84#ibcon#*mode == 0, iclass 15, count 0 2006.285.09:04:54.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.09:04:54.84#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:04:54.84#ibcon#*before write, iclass 15, count 0 2006.285.09:04:54.84#ibcon#enter sib2, iclass 15, count 0 2006.285.09:04:54.84#ibcon#flushed, iclass 15, count 0 2006.285.09:04:54.84#ibcon#about to write, iclass 15, count 0 2006.285.09:04:54.84#ibcon#wrote, iclass 15, count 0 2006.285.09:04:54.84#ibcon#about to read 3, iclass 15, count 0 2006.285.09:04:54.88#ibcon#read 3, iclass 15, count 0 2006.285.09:04:54.88#ibcon#about to read 4, iclass 15, count 0 2006.285.09:04:54.88#ibcon#read 4, iclass 15, count 0 2006.285.09:04:54.88#ibcon#about to read 5, iclass 15, count 0 2006.285.09:04:54.88#ibcon#read 5, iclass 15, count 0 2006.285.09:04:54.88#ibcon#about to read 6, iclass 15, count 0 2006.285.09:04:54.88#ibcon#read 6, iclass 15, count 0 2006.285.09:04:54.88#ibcon#end of sib2, iclass 15, count 0 2006.285.09:04:54.88#ibcon#*after write, iclass 15, count 0 2006.285.09:04:54.88#ibcon#*before return 0, iclass 15, count 0 2006.285.09:04:54.88#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:04:54.88#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:04:54.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.09:04:54.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.09:04:54.88$vck44/vb=3,4 2006.285.09:04:54.88#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.09:04:54.88#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.09:04:54.88#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:54.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:04:54.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:04:54.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:04:54.94#ibcon#enter wrdev, iclass 17, count 2 2006.285.09:04:54.94#ibcon#first serial, iclass 17, count 2 2006.285.09:04:54.94#ibcon#enter sib2, iclass 17, count 2 2006.285.09:04:54.94#ibcon#flushed, iclass 17, count 2 2006.285.09:04:54.94#ibcon#about to write, iclass 17, count 2 2006.285.09:04:54.94#ibcon#wrote, iclass 17, count 2 2006.285.09:04:54.94#ibcon#about to read 3, iclass 17, count 2 2006.285.09:04:54.96#ibcon#read 3, iclass 17, count 2 2006.285.09:04:54.96#ibcon#about to read 4, iclass 17, count 2 2006.285.09:04:54.96#ibcon#read 4, iclass 17, count 2 2006.285.09:04:54.96#ibcon#about to read 5, iclass 17, count 2 2006.285.09:04:54.96#ibcon#read 5, iclass 17, count 2 2006.285.09:04:54.96#ibcon#about to read 6, iclass 17, count 2 2006.285.09:04:54.96#ibcon#read 6, iclass 17, count 2 2006.285.09:04:54.96#ibcon#end of sib2, iclass 17, count 2 2006.285.09:04:54.96#ibcon#*mode == 0, iclass 17, count 2 2006.285.09:04:54.96#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.09:04:54.96#ibcon#[27=AT03-04\r\n] 2006.285.09:04:54.96#ibcon#*before write, iclass 17, count 2 2006.285.09:04:54.96#ibcon#enter sib2, iclass 17, count 2 2006.285.09:04:54.96#ibcon#flushed, iclass 17, count 2 2006.285.09:04:54.96#ibcon#about to write, iclass 17, count 2 2006.285.09:04:54.96#ibcon#wrote, iclass 17, count 2 2006.285.09:04:54.96#ibcon#about to read 3, iclass 17, count 2 2006.285.09:04:54.99#ibcon#read 3, iclass 17, count 2 2006.285.09:04:54.99#ibcon#about to read 4, iclass 17, count 2 2006.285.09:04:54.99#ibcon#read 4, iclass 17, count 2 2006.285.09:04:54.99#ibcon#about to read 5, iclass 17, count 2 2006.285.09:04:54.99#ibcon#read 5, iclass 17, count 2 2006.285.09:04:54.99#ibcon#about to read 6, iclass 17, count 2 2006.285.09:04:54.99#ibcon#read 6, iclass 17, count 2 2006.285.09:04:54.99#ibcon#end of sib2, iclass 17, count 2 2006.285.09:04:54.99#ibcon#*after write, iclass 17, count 2 2006.285.09:04:54.99#ibcon#*before return 0, iclass 17, count 2 2006.285.09:04:54.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:04:54.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:04:54.99#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.09:04:54.99#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:54.99#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:04:55.11#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:04:55.11#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:04:55.11#ibcon#enter wrdev, iclass 17, count 0 2006.285.09:04:55.11#ibcon#first serial, iclass 17, count 0 2006.285.09:04:55.11#ibcon#enter sib2, iclass 17, count 0 2006.285.09:04:55.11#ibcon#flushed, iclass 17, count 0 2006.285.09:04:55.11#ibcon#about to write, iclass 17, count 0 2006.285.09:04:55.11#ibcon#wrote, iclass 17, count 0 2006.285.09:04:55.11#ibcon#about to read 3, iclass 17, count 0 2006.285.09:04:55.13#ibcon#read 3, iclass 17, count 0 2006.285.09:04:55.13#ibcon#about to read 4, iclass 17, count 0 2006.285.09:04:55.13#ibcon#read 4, iclass 17, count 0 2006.285.09:04:55.13#ibcon#about to read 5, iclass 17, count 0 2006.285.09:04:55.13#ibcon#read 5, iclass 17, count 0 2006.285.09:04:55.13#ibcon#about to read 6, iclass 17, count 0 2006.285.09:04:55.13#ibcon#read 6, iclass 17, count 0 2006.285.09:04:55.13#ibcon#end of sib2, iclass 17, count 0 2006.285.09:04:55.13#ibcon#*mode == 0, iclass 17, count 0 2006.285.09:04:55.13#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.09:04:55.13#ibcon#[27=USB\r\n] 2006.285.09:04:55.13#ibcon#*before write, iclass 17, count 0 2006.285.09:04:55.13#ibcon#enter sib2, iclass 17, count 0 2006.285.09:04:55.13#ibcon#flushed, iclass 17, count 0 2006.285.09:04:55.13#ibcon#about to write, iclass 17, count 0 2006.285.09:04:55.13#ibcon#wrote, iclass 17, count 0 2006.285.09:04:55.13#ibcon#about to read 3, iclass 17, count 0 2006.285.09:04:55.16#ibcon#read 3, iclass 17, count 0 2006.285.09:04:55.16#ibcon#about to read 4, iclass 17, count 0 2006.285.09:04:55.16#ibcon#read 4, iclass 17, count 0 2006.285.09:04:55.16#ibcon#about to read 5, iclass 17, count 0 2006.285.09:04:55.16#ibcon#read 5, iclass 17, count 0 2006.285.09:04:55.16#ibcon#about to read 6, iclass 17, count 0 2006.285.09:04:55.16#ibcon#read 6, iclass 17, count 0 2006.285.09:04:55.16#ibcon#end of sib2, iclass 17, count 0 2006.285.09:04:55.16#ibcon#*after write, iclass 17, count 0 2006.285.09:04:55.16#ibcon#*before return 0, iclass 17, count 0 2006.285.09:04:55.16#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:04:55.16#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:04:55.16#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.09:04:55.16#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.09:04:55.16$vck44/vblo=4,679.99 2006.285.09:04:55.16#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.09:04:55.16#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.09:04:55.16#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:55.16#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:04:55.16#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:04:55.16#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:04:55.16#ibcon#enter wrdev, iclass 19, count 0 2006.285.09:04:55.16#ibcon#first serial, iclass 19, count 0 2006.285.09:04:55.16#ibcon#enter sib2, iclass 19, count 0 2006.285.09:04:55.16#ibcon#flushed, iclass 19, count 0 2006.285.09:04:55.16#ibcon#about to write, iclass 19, count 0 2006.285.09:04:55.16#ibcon#wrote, iclass 19, count 0 2006.285.09:04:55.16#ibcon#about to read 3, iclass 19, count 0 2006.285.09:04:55.18#ibcon#read 3, iclass 19, count 0 2006.285.09:04:55.18#ibcon#about to read 4, iclass 19, count 0 2006.285.09:04:55.18#ibcon#read 4, iclass 19, count 0 2006.285.09:04:55.18#ibcon#about to read 5, iclass 19, count 0 2006.285.09:04:55.18#ibcon#read 5, iclass 19, count 0 2006.285.09:04:55.18#ibcon#about to read 6, iclass 19, count 0 2006.285.09:04:55.18#ibcon#read 6, iclass 19, count 0 2006.285.09:04:55.18#ibcon#end of sib2, iclass 19, count 0 2006.285.09:04:55.18#ibcon#*mode == 0, iclass 19, count 0 2006.285.09:04:55.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.09:04:55.18#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:04:55.18#ibcon#*before write, iclass 19, count 0 2006.285.09:04:55.18#ibcon#enter sib2, iclass 19, count 0 2006.285.09:04:55.18#ibcon#flushed, iclass 19, count 0 2006.285.09:04:55.18#ibcon#about to write, iclass 19, count 0 2006.285.09:04:55.18#ibcon#wrote, iclass 19, count 0 2006.285.09:04:55.18#ibcon#about to read 3, iclass 19, count 0 2006.285.09:04:55.22#ibcon#read 3, iclass 19, count 0 2006.285.09:04:55.22#ibcon#about to read 4, iclass 19, count 0 2006.285.09:04:55.22#ibcon#read 4, iclass 19, count 0 2006.285.09:04:55.22#ibcon#about to read 5, iclass 19, count 0 2006.285.09:04:55.22#ibcon#read 5, iclass 19, count 0 2006.285.09:04:55.22#ibcon#about to read 6, iclass 19, count 0 2006.285.09:04:55.22#ibcon#read 6, iclass 19, count 0 2006.285.09:04:55.22#ibcon#end of sib2, iclass 19, count 0 2006.285.09:04:55.22#ibcon#*after write, iclass 19, count 0 2006.285.09:04:55.22#ibcon#*before return 0, iclass 19, count 0 2006.285.09:04:55.22#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:04:55.22#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:04:55.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.09:04:55.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.09:04:55.22$vck44/vb=4,5 2006.285.09:04:55.22#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.09:04:55.22#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.09:04:55.22#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:55.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:04:55.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:04:55.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:04:55.28#ibcon#enter wrdev, iclass 21, count 2 2006.285.09:04:55.28#ibcon#first serial, iclass 21, count 2 2006.285.09:04:55.28#ibcon#enter sib2, iclass 21, count 2 2006.285.09:04:55.28#ibcon#flushed, iclass 21, count 2 2006.285.09:04:55.28#ibcon#about to write, iclass 21, count 2 2006.285.09:04:55.28#ibcon#wrote, iclass 21, count 2 2006.285.09:04:55.28#ibcon#about to read 3, iclass 21, count 2 2006.285.09:04:55.30#ibcon#read 3, iclass 21, count 2 2006.285.09:04:55.30#ibcon#about to read 4, iclass 21, count 2 2006.285.09:04:55.30#ibcon#read 4, iclass 21, count 2 2006.285.09:04:55.30#ibcon#about to read 5, iclass 21, count 2 2006.285.09:04:55.30#ibcon#read 5, iclass 21, count 2 2006.285.09:04:55.30#ibcon#about to read 6, iclass 21, count 2 2006.285.09:04:55.30#ibcon#read 6, iclass 21, count 2 2006.285.09:04:55.30#ibcon#end of sib2, iclass 21, count 2 2006.285.09:04:55.30#ibcon#*mode == 0, iclass 21, count 2 2006.285.09:04:55.30#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.09:04:55.30#ibcon#[27=AT04-05\r\n] 2006.285.09:04:55.30#ibcon#*before write, iclass 21, count 2 2006.285.09:04:55.30#ibcon#enter sib2, iclass 21, count 2 2006.285.09:04:55.30#ibcon#flushed, iclass 21, count 2 2006.285.09:04:55.30#ibcon#about to write, iclass 21, count 2 2006.285.09:04:55.30#ibcon#wrote, iclass 21, count 2 2006.285.09:04:55.30#ibcon#about to read 3, iclass 21, count 2 2006.285.09:04:55.33#ibcon#read 3, iclass 21, count 2 2006.285.09:04:55.33#ibcon#about to read 4, iclass 21, count 2 2006.285.09:04:55.33#ibcon#read 4, iclass 21, count 2 2006.285.09:04:55.33#ibcon#about to read 5, iclass 21, count 2 2006.285.09:04:55.33#ibcon#read 5, iclass 21, count 2 2006.285.09:04:55.33#ibcon#about to read 6, iclass 21, count 2 2006.285.09:04:55.33#ibcon#read 6, iclass 21, count 2 2006.285.09:04:55.33#ibcon#end of sib2, iclass 21, count 2 2006.285.09:04:55.33#ibcon#*after write, iclass 21, count 2 2006.285.09:04:55.33#ibcon#*before return 0, iclass 21, count 2 2006.285.09:04:55.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:04:55.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:04:55.33#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.09:04:55.33#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:55.33#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:04:55.45#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:04:55.45#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:04:55.45#ibcon#enter wrdev, iclass 21, count 0 2006.285.09:04:55.45#ibcon#first serial, iclass 21, count 0 2006.285.09:04:55.45#ibcon#enter sib2, iclass 21, count 0 2006.285.09:04:55.45#ibcon#flushed, iclass 21, count 0 2006.285.09:04:55.45#ibcon#about to write, iclass 21, count 0 2006.285.09:04:55.45#ibcon#wrote, iclass 21, count 0 2006.285.09:04:55.45#ibcon#about to read 3, iclass 21, count 0 2006.285.09:04:55.47#ibcon#read 3, iclass 21, count 0 2006.285.09:04:55.47#ibcon#about to read 4, iclass 21, count 0 2006.285.09:04:55.47#ibcon#read 4, iclass 21, count 0 2006.285.09:04:55.47#ibcon#about to read 5, iclass 21, count 0 2006.285.09:04:55.47#ibcon#read 5, iclass 21, count 0 2006.285.09:04:55.47#ibcon#about to read 6, iclass 21, count 0 2006.285.09:04:55.47#ibcon#read 6, iclass 21, count 0 2006.285.09:04:55.47#ibcon#end of sib2, iclass 21, count 0 2006.285.09:04:55.47#ibcon#*mode == 0, iclass 21, count 0 2006.285.09:04:55.47#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.09:04:55.47#ibcon#[27=USB\r\n] 2006.285.09:04:55.47#ibcon#*before write, iclass 21, count 0 2006.285.09:04:55.47#ibcon#enter sib2, iclass 21, count 0 2006.285.09:04:55.47#ibcon#flushed, iclass 21, count 0 2006.285.09:04:55.47#ibcon#about to write, iclass 21, count 0 2006.285.09:04:55.47#ibcon#wrote, iclass 21, count 0 2006.285.09:04:55.47#ibcon#about to read 3, iclass 21, count 0 2006.285.09:04:55.50#ibcon#read 3, iclass 21, count 0 2006.285.09:04:55.50#ibcon#about to read 4, iclass 21, count 0 2006.285.09:04:55.50#ibcon#read 4, iclass 21, count 0 2006.285.09:04:55.50#ibcon#about to read 5, iclass 21, count 0 2006.285.09:04:55.50#ibcon#read 5, iclass 21, count 0 2006.285.09:04:55.50#ibcon#about to read 6, iclass 21, count 0 2006.285.09:04:55.50#ibcon#read 6, iclass 21, count 0 2006.285.09:04:55.50#ibcon#end of sib2, iclass 21, count 0 2006.285.09:04:55.50#ibcon#*after write, iclass 21, count 0 2006.285.09:04:55.50#ibcon#*before return 0, iclass 21, count 0 2006.285.09:04:55.50#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:04:55.50#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:04:55.50#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.09:04:55.50#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.09:04:55.50$vck44/vblo=5,709.99 2006.285.09:04:55.50#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.09:04:55.50#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.09:04:55.50#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:55.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:04:55.50#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:04:55.50#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:04:55.50#ibcon#enter wrdev, iclass 23, count 0 2006.285.09:04:55.50#ibcon#first serial, iclass 23, count 0 2006.285.09:04:55.50#ibcon#enter sib2, iclass 23, count 0 2006.285.09:04:55.50#ibcon#flushed, iclass 23, count 0 2006.285.09:04:55.50#ibcon#about to write, iclass 23, count 0 2006.285.09:04:55.50#ibcon#wrote, iclass 23, count 0 2006.285.09:04:55.50#ibcon#about to read 3, iclass 23, count 0 2006.285.09:04:55.52#ibcon#read 3, iclass 23, count 0 2006.285.09:04:55.52#ibcon#about to read 4, iclass 23, count 0 2006.285.09:04:55.52#ibcon#read 4, iclass 23, count 0 2006.285.09:04:55.52#ibcon#about to read 5, iclass 23, count 0 2006.285.09:04:55.52#ibcon#read 5, iclass 23, count 0 2006.285.09:04:55.52#ibcon#about to read 6, iclass 23, count 0 2006.285.09:04:55.52#ibcon#read 6, iclass 23, count 0 2006.285.09:04:55.52#ibcon#end of sib2, iclass 23, count 0 2006.285.09:04:55.52#ibcon#*mode == 0, iclass 23, count 0 2006.285.09:04:55.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.09:04:55.52#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:04:55.52#ibcon#*before write, iclass 23, count 0 2006.285.09:04:55.52#ibcon#enter sib2, iclass 23, count 0 2006.285.09:04:55.52#ibcon#flushed, iclass 23, count 0 2006.285.09:04:55.52#ibcon#about to write, iclass 23, count 0 2006.285.09:04:55.52#ibcon#wrote, iclass 23, count 0 2006.285.09:04:55.52#ibcon#about to read 3, iclass 23, count 0 2006.285.09:04:55.56#ibcon#read 3, iclass 23, count 0 2006.285.09:04:55.56#ibcon#about to read 4, iclass 23, count 0 2006.285.09:04:55.56#ibcon#read 4, iclass 23, count 0 2006.285.09:04:55.56#ibcon#about to read 5, iclass 23, count 0 2006.285.09:04:55.56#ibcon#read 5, iclass 23, count 0 2006.285.09:04:55.56#ibcon#about to read 6, iclass 23, count 0 2006.285.09:04:55.56#ibcon#read 6, iclass 23, count 0 2006.285.09:04:55.56#ibcon#end of sib2, iclass 23, count 0 2006.285.09:04:55.56#ibcon#*after write, iclass 23, count 0 2006.285.09:04:55.56#ibcon#*before return 0, iclass 23, count 0 2006.285.09:04:55.56#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:04:55.56#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:04:55.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.09:04:55.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.09:04:55.56$vck44/vb=5,4 2006.285.09:04:55.56#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.09:04:55.56#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.09:04:55.56#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:55.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:04:55.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:04:55.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:04:55.62#ibcon#enter wrdev, iclass 25, count 2 2006.285.09:04:55.62#ibcon#first serial, iclass 25, count 2 2006.285.09:04:55.62#ibcon#enter sib2, iclass 25, count 2 2006.285.09:04:55.62#ibcon#flushed, iclass 25, count 2 2006.285.09:04:55.62#ibcon#about to write, iclass 25, count 2 2006.285.09:04:55.62#ibcon#wrote, iclass 25, count 2 2006.285.09:04:55.62#ibcon#about to read 3, iclass 25, count 2 2006.285.09:04:55.64#ibcon#read 3, iclass 25, count 2 2006.285.09:04:55.64#ibcon#about to read 4, iclass 25, count 2 2006.285.09:04:55.64#ibcon#read 4, iclass 25, count 2 2006.285.09:04:55.64#ibcon#about to read 5, iclass 25, count 2 2006.285.09:04:55.64#ibcon#read 5, iclass 25, count 2 2006.285.09:04:55.64#ibcon#about to read 6, iclass 25, count 2 2006.285.09:04:55.64#ibcon#read 6, iclass 25, count 2 2006.285.09:04:55.64#ibcon#end of sib2, iclass 25, count 2 2006.285.09:04:55.64#ibcon#*mode == 0, iclass 25, count 2 2006.285.09:04:55.64#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.09:04:55.64#ibcon#[27=AT05-04\r\n] 2006.285.09:04:55.64#ibcon#*before write, iclass 25, count 2 2006.285.09:04:55.64#ibcon#enter sib2, iclass 25, count 2 2006.285.09:04:55.64#ibcon#flushed, iclass 25, count 2 2006.285.09:04:55.64#ibcon#about to write, iclass 25, count 2 2006.285.09:04:55.64#ibcon#wrote, iclass 25, count 2 2006.285.09:04:55.64#ibcon#about to read 3, iclass 25, count 2 2006.285.09:04:55.67#ibcon#read 3, iclass 25, count 2 2006.285.09:04:55.67#ibcon#about to read 4, iclass 25, count 2 2006.285.09:04:55.67#ibcon#read 4, iclass 25, count 2 2006.285.09:04:55.67#ibcon#about to read 5, iclass 25, count 2 2006.285.09:04:55.67#ibcon#read 5, iclass 25, count 2 2006.285.09:04:55.67#ibcon#about to read 6, iclass 25, count 2 2006.285.09:04:55.67#ibcon#read 6, iclass 25, count 2 2006.285.09:04:55.67#ibcon#end of sib2, iclass 25, count 2 2006.285.09:04:55.67#ibcon#*after write, iclass 25, count 2 2006.285.09:04:55.67#ibcon#*before return 0, iclass 25, count 2 2006.285.09:04:55.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:04:55.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:04:55.67#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.09:04:55.67#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:55.67#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:04:55.79#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:04:55.79#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:04:55.79#ibcon#enter wrdev, iclass 25, count 0 2006.285.09:04:55.79#ibcon#first serial, iclass 25, count 0 2006.285.09:04:55.79#ibcon#enter sib2, iclass 25, count 0 2006.285.09:04:55.79#ibcon#flushed, iclass 25, count 0 2006.285.09:04:55.79#ibcon#about to write, iclass 25, count 0 2006.285.09:04:55.79#ibcon#wrote, iclass 25, count 0 2006.285.09:04:55.79#ibcon#about to read 3, iclass 25, count 0 2006.285.09:04:55.81#ibcon#read 3, iclass 25, count 0 2006.285.09:04:55.81#ibcon#about to read 4, iclass 25, count 0 2006.285.09:04:55.81#ibcon#read 4, iclass 25, count 0 2006.285.09:04:55.81#ibcon#about to read 5, iclass 25, count 0 2006.285.09:04:55.81#ibcon#read 5, iclass 25, count 0 2006.285.09:04:55.81#ibcon#about to read 6, iclass 25, count 0 2006.285.09:04:55.81#ibcon#read 6, iclass 25, count 0 2006.285.09:04:55.81#ibcon#end of sib2, iclass 25, count 0 2006.285.09:04:55.81#ibcon#*mode == 0, iclass 25, count 0 2006.285.09:04:55.81#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.09:04:55.81#ibcon#[27=USB\r\n] 2006.285.09:04:55.81#ibcon#*before write, iclass 25, count 0 2006.285.09:04:55.81#ibcon#enter sib2, iclass 25, count 0 2006.285.09:04:55.81#ibcon#flushed, iclass 25, count 0 2006.285.09:04:55.81#ibcon#about to write, iclass 25, count 0 2006.285.09:04:55.81#ibcon#wrote, iclass 25, count 0 2006.285.09:04:55.81#ibcon#about to read 3, iclass 25, count 0 2006.285.09:04:55.84#ibcon#read 3, iclass 25, count 0 2006.285.09:04:55.84#ibcon#about to read 4, iclass 25, count 0 2006.285.09:04:55.84#ibcon#read 4, iclass 25, count 0 2006.285.09:04:55.84#ibcon#about to read 5, iclass 25, count 0 2006.285.09:04:55.84#ibcon#read 5, iclass 25, count 0 2006.285.09:04:55.84#ibcon#about to read 6, iclass 25, count 0 2006.285.09:04:55.84#ibcon#read 6, iclass 25, count 0 2006.285.09:04:55.84#ibcon#end of sib2, iclass 25, count 0 2006.285.09:04:55.84#ibcon#*after write, iclass 25, count 0 2006.285.09:04:55.84#ibcon#*before return 0, iclass 25, count 0 2006.285.09:04:55.84#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:04:55.84#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:04:55.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.09:04:55.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.09:04:55.84$vck44/vblo=6,719.99 2006.285.09:04:55.84#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.09:04:55.84#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.09:04:55.84#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:55.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:04:55.84#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:04:55.84#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:04:55.84#ibcon#enter wrdev, iclass 27, count 0 2006.285.09:04:55.84#ibcon#first serial, iclass 27, count 0 2006.285.09:04:55.84#ibcon#enter sib2, iclass 27, count 0 2006.285.09:04:55.84#ibcon#flushed, iclass 27, count 0 2006.285.09:04:55.84#ibcon#about to write, iclass 27, count 0 2006.285.09:04:55.84#ibcon#wrote, iclass 27, count 0 2006.285.09:04:55.84#ibcon#about to read 3, iclass 27, count 0 2006.285.09:04:55.86#ibcon#read 3, iclass 27, count 0 2006.285.09:04:55.86#ibcon#about to read 4, iclass 27, count 0 2006.285.09:04:55.86#ibcon#read 4, iclass 27, count 0 2006.285.09:04:55.86#ibcon#about to read 5, iclass 27, count 0 2006.285.09:04:55.86#ibcon#read 5, iclass 27, count 0 2006.285.09:04:55.86#ibcon#about to read 6, iclass 27, count 0 2006.285.09:04:55.86#ibcon#read 6, iclass 27, count 0 2006.285.09:04:55.86#ibcon#end of sib2, iclass 27, count 0 2006.285.09:04:55.86#ibcon#*mode == 0, iclass 27, count 0 2006.285.09:04:55.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.09:04:55.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:04:55.86#ibcon#*before write, iclass 27, count 0 2006.285.09:04:55.86#ibcon#enter sib2, iclass 27, count 0 2006.285.09:04:55.86#ibcon#flushed, iclass 27, count 0 2006.285.09:04:55.86#ibcon#about to write, iclass 27, count 0 2006.285.09:04:55.86#ibcon#wrote, iclass 27, count 0 2006.285.09:04:55.86#ibcon#about to read 3, iclass 27, count 0 2006.285.09:04:55.90#ibcon#read 3, iclass 27, count 0 2006.285.09:04:55.90#ibcon#about to read 4, iclass 27, count 0 2006.285.09:04:55.90#ibcon#read 4, iclass 27, count 0 2006.285.09:04:55.90#ibcon#about to read 5, iclass 27, count 0 2006.285.09:04:55.90#ibcon#read 5, iclass 27, count 0 2006.285.09:04:55.90#ibcon#about to read 6, iclass 27, count 0 2006.285.09:04:55.90#ibcon#read 6, iclass 27, count 0 2006.285.09:04:55.90#ibcon#end of sib2, iclass 27, count 0 2006.285.09:04:55.90#ibcon#*after write, iclass 27, count 0 2006.285.09:04:55.90#ibcon#*before return 0, iclass 27, count 0 2006.285.09:04:55.90#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:04:55.90#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:04:55.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.09:04:55.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.09:04:55.90$vck44/vb=6,3 2006.285.09:04:55.90#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.09:04:55.90#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.09:04:55.90#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:55.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:04:55.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:04:55.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:04:55.96#ibcon#enter wrdev, iclass 29, count 2 2006.285.09:04:55.96#ibcon#first serial, iclass 29, count 2 2006.285.09:04:55.96#ibcon#enter sib2, iclass 29, count 2 2006.285.09:04:55.96#ibcon#flushed, iclass 29, count 2 2006.285.09:04:55.96#ibcon#about to write, iclass 29, count 2 2006.285.09:04:55.96#ibcon#wrote, iclass 29, count 2 2006.285.09:04:55.96#ibcon#about to read 3, iclass 29, count 2 2006.285.09:04:55.98#ibcon#read 3, iclass 29, count 2 2006.285.09:04:55.98#ibcon#about to read 4, iclass 29, count 2 2006.285.09:04:55.98#ibcon#read 4, iclass 29, count 2 2006.285.09:04:55.98#ibcon#about to read 5, iclass 29, count 2 2006.285.09:04:55.98#ibcon#read 5, iclass 29, count 2 2006.285.09:04:55.98#ibcon#about to read 6, iclass 29, count 2 2006.285.09:04:55.98#ibcon#read 6, iclass 29, count 2 2006.285.09:04:55.98#ibcon#end of sib2, iclass 29, count 2 2006.285.09:04:55.98#ibcon#*mode == 0, iclass 29, count 2 2006.285.09:04:55.98#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.09:04:55.98#ibcon#[27=AT06-03\r\n] 2006.285.09:04:55.98#ibcon#*before write, iclass 29, count 2 2006.285.09:04:55.98#ibcon#enter sib2, iclass 29, count 2 2006.285.09:04:55.98#ibcon#flushed, iclass 29, count 2 2006.285.09:04:55.98#ibcon#about to write, iclass 29, count 2 2006.285.09:04:55.98#ibcon#wrote, iclass 29, count 2 2006.285.09:04:55.98#ibcon#about to read 3, iclass 29, count 2 2006.285.09:04:56.01#ibcon#read 3, iclass 29, count 2 2006.285.09:04:56.01#ibcon#about to read 4, iclass 29, count 2 2006.285.09:04:56.01#ibcon#read 4, iclass 29, count 2 2006.285.09:04:56.01#ibcon#about to read 5, iclass 29, count 2 2006.285.09:04:56.01#ibcon#read 5, iclass 29, count 2 2006.285.09:04:56.01#ibcon#about to read 6, iclass 29, count 2 2006.285.09:04:56.01#ibcon#read 6, iclass 29, count 2 2006.285.09:04:56.01#ibcon#end of sib2, iclass 29, count 2 2006.285.09:04:56.01#ibcon#*after write, iclass 29, count 2 2006.285.09:04:56.01#ibcon#*before return 0, iclass 29, count 2 2006.285.09:04:56.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:04:56.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:04:56.01#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.09:04:56.01#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:56.01#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:04:56.13#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:04:56.13#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:04:56.13#ibcon#enter wrdev, iclass 29, count 0 2006.285.09:04:56.13#ibcon#first serial, iclass 29, count 0 2006.285.09:04:56.13#ibcon#enter sib2, iclass 29, count 0 2006.285.09:04:56.13#ibcon#flushed, iclass 29, count 0 2006.285.09:04:56.13#ibcon#about to write, iclass 29, count 0 2006.285.09:04:56.13#ibcon#wrote, iclass 29, count 0 2006.285.09:04:56.13#ibcon#about to read 3, iclass 29, count 0 2006.285.09:04:56.15#ibcon#read 3, iclass 29, count 0 2006.285.09:04:56.15#ibcon#about to read 4, iclass 29, count 0 2006.285.09:04:56.15#ibcon#read 4, iclass 29, count 0 2006.285.09:04:56.15#ibcon#about to read 5, iclass 29, count 0 2006.285.09:04:56.15#ibcon#read 5, iclass 29, count 0 2006.285.09:04:56.15#ibcon#about to read 6, iclass 29, count 0 2006.285.09:04:56.15#ibcon#read 6, iclass 29, count 0 2006.285.09:04:56.15#ibcon#end of sib2, iclass 29, count 0 2006.285.09:04:56.15#ibcon#*mode == 0, iclass 29, count 0 2006.285.09:04:56.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.09:04:56.15#ibcon#[27=USB\r\n] 2006.285.09:04:56.15#ibcon#*before write, iclass 29, count 0 2006.285.09:04:56.15#ibcon#enter sib2, iclass 29, count 0 2006.285.09:04:56.15#ibcon#flushed, iclass 29, count 0 2006.285.09:04:56.15#ibcon#about to write, iclass 29, count 0 2006.285.09:04:56.15#ibcon#wrote, iclass 29, count 0 2006.285.09:04:56.15#ibcon#about to read 3, iclass 29, count 0 2006.285.09:04:56.18#ibcon#read 3, iclass 29, count 0 2006.285.09:04:56.18#ibcon#about to read 4, iclass 29, count 0 2006.285.09:04:56.18#ibcon#read 4, iclass 29, count 0 2006.285.09:04:56.18#ibcon#about to read 5, iclass 29, count 0 2006.285.09:04:56.18#ibcon#read 5, iclass 29, count 0 2006.285.09:04:56.18#ibcon#about to read 6, iclass 29, count 0 2006.285.09:04:56.18#ibcon#read 6, iclass 29, count 0 2006.285.09:04:56.18#ibcon#end of sib2, iclass 29, count 0 2006.285.09:04:56.18#ibcon#*after write, iclass 29, count 0 2006.285.09:04:56.18#ibcon#*before return 0, iclass 29, count 0 2006.285.09:04:56.18#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:04:56.18#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:04:56.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.09:04:56.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.09:04:56.18$vck44/vblo=7,734.99 2006.285.09:04:56.18#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.09:04:56.18#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.09:04:56.18#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:56.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:04:56.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:04:56.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:04:56.18#ibcon#enter wrdev, iclass 31, count 0 2006.285.09:04:56.18#ibcon#first serial, iclass 31, count 0 2006.285.09:04:56.18#ibcon#enter sib2, iclass 31, count 0 2006.285.09:04:56.18#ibcon#flushed, iclass 31, count 0 2006.285.09:04:56.18#ibcon#about to write, iclass 31, count 0 2006.285.09:04:56.18#ibcon#wrote, iclass 31, count 0 2006.285.09:04:56.18#ibcon#about to read 3, iclass 31, count 0 2006.285.09:04:56.20#ibcon#read 3, iclass 31, count 0 2006.285.09:04:56.20#ibcon#about to read 4, iclass 31, count 0 2006.285.09:04:56.20#ibcon#read 4, iclass 31, count 0 2006.285.09:04:56.20#ibcon#about to read 5, iclass 31, count 0 2006.285.09:04:56.20#ibcon#read 5, iclass 31, count 0 2006.285.09:04:56.20#ibcon#about to read 6, iclass 31, count 0 2006.285.09:04:56.20#ibcon#read 6, iclass 31, count 0 2006.285.09:04:56.20#ibcon#end of sib2, iclass 31, count 0 2006.285.09:04:56.20#ibcon#*mode == 0, iclass 31, count 0 2006.285.09:04:56.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.09:04:56.20#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:04:56.20#ibcon#*before write, iclass 31, count 0 2006.285.09:04:56.20#ibcon#enter sib2, iclass 31, count 0 2006.285.09:04:56.20#ibcon#flushed, iclass 31, count 0 2006.285.09:04:56.20#ibcon#about to write, iclass 31, count 0 2006.285.09:04:56.20#ibcon#wrote, iclass 31, count 0 2006.285.09:04:56.20#ibcon#about to read 3, iclass 31, count 0 2006.285.09:04:56.24#ibcon#read 3, iclass 31, count 0 2006.285.09:04:56.24#ibcon#about to read 4, iclass 31, count 0 2006.285.09:04:56.24#ibcon#read 4, iclass 31, count 0 2006.285.09:04:56.24#ibcon#about to read 5, iclass 31, count 0 2006.285.09:04:56.24#ibcon#read 5, iclass 31, count 0 2006.285.09:04:56.24#ibcon#about to read 6, iclass 31, count 0 2006.285.09:04:56.24#ibcon#read 6, iclass 31, count 0 2006.285.09:04:56.24#ibcon#end of sib2, iclass 31, count 0 2006.285.09:04:56.24#ibcon#*after write, iclass 31, count 0 2006.285.09:04:56.24#ibcon#*before return 0, iclass 31, count 0 2006.285.09:04:56.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:04:56.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:04:56.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.09:04:56.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.09:04:56.24$vck44/vb=7,4 2006.285.09:04:56.24#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.09:04:56.24#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.09:04:56.24#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:56.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:04:56.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:04:56.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:04:56.30#ibcon#enter wrdev, iclass 33, count 2 2006.285.09:04:56.30#ibcon#first serial, iclass 33, count 2 2006.285.09:04:56.30#ibcon#enter sib2, iclass 33, count 2 2006.285.09:04:56.30#ibcon#flushed, iclass 33, count 2 2006.285.09:04:56.30#ibcon#about to write, iclass 33, count 2 2006.285.09:04:56.30#ibcon#wrote, iclass 33, count 2 2006.285.09:04:56.30#ibcon#about to read 3, iclass 33, count 2 2006.285.09:04:56.32#ibcon#read 3, iclass 33, count 2 2006.285.09:04:56.32#ibcon#about to read 4, iclass 33, count 2 2006.285.09:04:56.32#ibcon#read 4, iclass 33, count 2 2006.285.09:04:56.32#ibcon#about to read 5, iclass 33, count 2 2006.285.09:04:56.32#ibcon#read 5, iclass 33, count 2 2006.285.09:04:56.32#ibcon#about to read 6, iclass 33, count 2 2006.285.09:04:56.32#ibcon#read 6, iclass 33, count 2 2006.285.09:04:56.32#ibcon#end of sib2, iclass 33, count 2 2006.285.09:04:56.32#ibcon#*mode == 0, iclass 33, count 2 2006.285.09:04:56.32#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.09:04:56.32#ibcon#[27=AT07-04\r\n] 2006.285.09:04:56.32#ibcon#*before write, iclass 33, count 2 2006.285.09:04:56.32#ibcon#enter sib2, iclass 33, count 2 2006.285.09:04:56.32#ibcon#flushed, iclass 33, count 2 2006.285.09:04:56.32#ibcon#about to write, iclass 33, count 2 2006.285.09:04:56.32#ibcon#wrote, iclass 33, count 2 2006.285.09:04:56.32#ibcon#about to read 3, iclass 33, count 2 2006.285.09:04:56.35#ibcon#read 3, iclass 33, count 2 2006.285.09:04:56.35#ibcon#about to read 4, iclass 33, count 2 2006.285.09:04:56.35#ibcon#read 4, iclass 33, count 2 2006.285.09:04:56.35#ibcon#about to read 5, iclass 33, count 2 2006.285.09:04:56.35#ibcon#read 5, iclass 33, count 2 2006.285.09:04:56.35#ibcon#about to read 6, iclass 33, count 2 2006.285.09:04:56.35#ibcon#read 6, iclass 33, count 2 2006.285.09:04:56.35#ibcon#end of sib2, iclass 33, count 2 2006.285.09:04:56.35#ibcon#*after write, iclass 33, count 2 2006.285.09:04:56.35#ibcon#*before return 0, iclass 33, count 2 2006.285.09:04:56.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:04:56.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:04:56.35#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.09:04:56.35#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:56.35#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:04:56.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:04:56.47#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:04:56.47#ibcon#enter wrdev, iclass 33, count 0 2006.285.09:04:56.47#ibcon#first serial, iclass 33, count 0 2006.285.09:04:56.47#ibcon#enter sib2, iclass 33, count 0 2006.285.09:04:56.47#ibcon#flushed, iclass 33, count 0 2006.285.09:04:56.47#ibcon#about to write, iclass 33, count 0 2006.285.09:04:56.47#ibcon#wrote, iclass 33, count 0 2006.285.09:04:56.47#ibcon#about to read 3, iclass 33, count 0 2006.285.09:04:56.49#ibcon#read 3, iclass 33, count 0 2006.285.09:04:56.49#ibcon#about to read 4, iclass 33, count 0 2006.285.09:04:56.49#ibcon#read 4, iclass 33, count 0 2006.285.09:04:56.49#ibcon#about to read 5, iclass 33, count 0 2006.285.09:04:56.49#ibcon#read 5, iclass 33, count 0 2006.285.09:04:56.49#ibcon#about to read 6, iclass 33, count 0 2006.285.09:04:56.49#ibcon#read 6, iclass 33, count 0 2006.285.09:04:56.49#ibcon#end of sib2, iclass 33, count 0 2006.285.09:04:56.49#ibcon#*mode == 0, iclass 33, count 0 2006.285.09:04:56.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.09:04:56.49#ibcon#[27=USB\r\n] 2006.285.09:04:56.49#ibcon#*before write, iclass 33, count 0 2006.285.09:04:56.49#ibcon#enter sib2, iclass 33, count 0 2006.285.09:04:56.49#ibcon#flushed, iclass 33, count 0 2006.285.09:04:56.49#ibcon#about to write, iclass 33, count 0 2006.285.09:04:56.49#ibcon#wrote, iclass 33, count 0 2006.285.09:04:56.49#ibcon#about to read 3, iclass 33, count 0 2006.285.09:04:56.52#ibcon#read 3, iclass 33, count 0 2006.285.09:04:56.52#ibcon#about to read 4, iclass 33, count 0 2006.285.09:04:56.52#ibcon#read 4, iclass 33, count 0 2006.285.09:04:56.52#ibcon#about to read 5, iclass 33, count 0 2006.285.09:04:56.52#ibcon#read 5, iclass 33, count 0 2006.285.09:04:56.52#ibcon#about to read 6, iclass 33, count 0 2006.285.09:04:56.52#ibcon#read 6, iclass 33, count 0 2006.285.09:04:56.52#ibcon#end of sib2, iclass 33, count 0 2006.285.09:04:56.52#ibcon#*after write, iclass 33, count 0 2006.285.09:04:56.52#ibcon#*before return 0, iclass 33, count 0 2006.285.09:04:56.52#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:04:56.52#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:04:56.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.09:04:56.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.09:04:56.52$vck44/vblo=8,744.99 2006.285.09:04:56.52#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.09:04:56.52#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.09:04:56.52#ibcon#ireg 17 cls_cnt 0 2006.285.09:04:56.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:04:56.52#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:04:56.52#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:04:56.52#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:04:56.52#ibcon#first serial, iclass 35, count 0 2006.285.09:04:56.52#ibcon#enter sib2, iclass 35, count 0 2006.285.09:04:56.52#ibcon#flushed, iclass 35, count 0 2006.285.09:04:56.52#ibcon#about to write, iclass 35, count 0 2006.285.09:04:56.52#ibcon#wrote, iclass 35, count 0 2006.285.09:04:56.52#ibcon#about to read 3, iclass 35, count 0 2006.285.09:04:56.54#ibcon#read 3, iclass 35, count 0 2006.285.09:04:56.54#ibcon#about to read 4, iclass 35, count 0 2006.285.09:04:56.54#ibcon#read 4, iclass 35, count 0 2006.285.09:04:56.54#ibcon#about to read 5, iclass 35, count 0 2006.285.09:04:56.54#ibcon#read 5, iclass 35, count 0 2006.285.09:04:56.54#ibcon#about to read 6, iclass 35, count 0 2006.285.09:04:56.54#ibcon#read 6, iclass 35, count 0 2006.285.09:04:56.54#ibcon#end of sib2, iclass 35, count 0 2006.285.09:04:56.54#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:04:56.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:04:56.54#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:04:56.54#ibcon#*before write, iclass 35, count 0 2006.285.09:04:56.54#ibcon#enter sib2, iclass 35, count 0 2006.285.09:04:56.54#ibcon#flushed, iclass 35, count 0 2006.285.09:04:56.54#ibcon#about to write, iclass 35, count 0 2006.285.09:04:56.54#ibcon#wrote, iclass 35, count 0 2006.285.09:04:56.54#ibcon#about to read 3, iclass 35, count 0 2006.285.09:04:56.58#ibcon#read 3, iclass 35, count 0 2006.285.09:04:56.58#ibcon#about to read 4, iclass 35, count 0 2006.285.09:04:56.58#ibcon#read 4, iclass 35, count 0 2006.285.09:04:56.58#ibcon#about to read 5, iclass 35, count 0 2006.285.09:04:56.58#ibcon#read 5, iclass 35, count 0 2006.285.09:04:56.58#ibcon#about to read 6, iclass 35, count 0 2006.285.09:04:56.58#ibcon#read 6, iclass 35, count 0 2006.285.09:04:56.58#ibcon#end of sib2, iclass 35, count 0 2006.285.09:04:56.58#ibcon#*after write, iclass 35, count 0 2006.285.09:04:56.58#ibcon#*before return 0, iclass 35, count 0 2006.285.09:04:56.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:04:56.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:04:56.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:04:56.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:04:56.58$vck44/vb=8,4 2006.285.09:04:56.58#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.09:04:56.58#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.09:04:56.58#ibcon#ireg 11 cls_cnt 2 2006.285.09:04:56.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:04:56.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:04:56.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:04:56.64#ibcon#enter wrdev, iclass 37, count 2 2006.285.09:04:56.64#ibcon#first serial, iclass 37, count 2 2006.285.09:04:56.64#ibcon#enter sib2, iclass 37, count 2 2006.285.09:04:56.64#ibcon#flushed, iclass 37, count 2 2006.285.09:04:56.64#ibcon#about to write, iclass 37, count 2 2006.285.09:04:56.64#ibcon#wrote, iclass 37, count 2 2006.285.09:04:56.64#ibcon#about to read 3, iclass 37, count 2 2006.285.09:04:56.66#ibcon#read 3, iclass 37, count 2 2006.285.09:04:56.66#ibcon#about to read 4, iclass 37, count 2 2006.285.09:04:56.66#ibcon#read 4, iclass 37, count 2 2006.285.09:04:56.66#ibcon#about to read 5, iclass 37, count 2 2006.285.09:04:56.66#ibcon#read 5, iclass 37, count 2 2006.285.09:04:56.66#ibcon#about to read 6, iclass 37, count 2 2006.285.09:04:56.66#ibcon#read 6, iclass 37, count 2 2006.285.09:04:56.66#ibcon#end of sib2, iclass 37, count 2 2006.285.09:04:56.66#ibcon#*mode == 0, iclass 37, count 2 2006.285.09:04:56.66#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.09:04:56.66#ibcon#[27=AT08-04\r\n] 2006.285.09:04:56.66#ibcon#*before write, iclass 37, count 2 2006.285.09:04:56.66#ibcon#enter sib2, iclass 37, count 2 2006.285.09:04:56.66#ibcon#flushed, iclass 37, count 2 2006.285.09:04:56.66#ibcon#about to write, iclass 37, count 2 2006.285.09:04:56.66#ibcon#wrote, iclass 37, count 2 2006.285.09:04:56.66#ibcon#about to read 3, iclass 37, count 2 2006.285.09:04:56.69#ibcon#read 3, iclass 37, count 2 2006.285.09:04:56.69#ibcon#about to read 4, iclass 37, count 2 2006.285.09:04:56.69#ibcon#read 4, iclass 37, count 2 2006.285.09:04:56.69#ibcon#about to read 5, iclass 37, count 2 2006.285.09:04:56.69#ibcon#read 5, iclass 37, count 2 2006.285.09:04:56.69#ibcon#about to read 6, iclass 37, count 2 2006.285.09:04:56.69#ibcon#read 6, iclass 37, count 2 2006.285.09:04:56.69#ibcon#end of sib2, iclass 37, count 2 2006.285.09:04:56.69#ibcon#*after write, iclass 37, count 2 2006.285.09:04:56.69#ibcon#*before return 0, iclass 37, count 2 2006.285.09:04:56.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:04:56.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:04:56.69#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.09:04:56.69#ibcon#ireg 7 cls_cnt 0 2006.285.09:04:56.69#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:04:56.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:04:56.81#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:04:56.81#ibcon#enter wrdev, iclass 37, count 0 2006.285.09:04:56.81#ibcon#first serial, iclass 37, count 0 2006.285.09:04:56.81#ibcon#enter sib2, iclass 37, count 0 2006.285.09:04:56.81#ibcon#flushed, iclass 37, count 0 2006.285.09:04:56.81#ibcon#about to write, iclass 37, count 0 2006.285.09:04:56.81#ibcon#wrote, iclass 37, count 0 2006.285.09:04:56.81#ibcon#about to read 3, iclass 37, count 0 2006.285.09:04:56.83#ibcon#read 3, iclass 37, count 0 2006.285.09:04:56.83#ibcon#about to read 4, iclass 37, count 0 2006.285.09:04:56.83#ibcon#read 4, iclass 37, count 0 2006.285.09:04:56.83#ibcon#about to read 5, iclass 37, count 0 2006.285.09:04:56.83#ibcon#read 5, iclass 37, count 0 2006.285.09:04:56.83#ibcon#about to read 6, iclass 37, count 0 2006.285.09:04:56.83#ibcon#read 6, iclass 37, count 0 2006.285.09:04:56.83#ibcon#end of sib2, iclass 37, count 0 2006.285.09:04:56.83#ibcon#*mode == 0, iclass 37, count 0 2006.285.09:04:56.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.09:04:56.83#ibcon#[27=USB\r\n] 2006.285.09:04:56.83#ibcon#*before write, iclass 37, count 0 2006.285.09:04:56.83#ibcon#enter sib2, iclass 37, count 0 2006.285.09:04:56.83#ibcon#flushed, iclass 37, count 0 2006.285.09:04:56.83#ibcon#about to write, iclass 37, count 0 2006.285.09:04:56.83#ibcon#wrote, iclass 37, count 0 2006.285.09:04:56.83#ibcon#about to read 3, iclass 37, count 0 2006.285.09:04:56.86#ibcon#read 3, iclass 37, count 0 2006.285.09:04:56.86#ibcon#about to read 4, iclass 37, count 0 2006.285.09:04:56.86#ibcon#read 4, iclass 37, count 0 2006.285.09:04:56.86#ibcon#about to read 5, iclass 37, count 0 2006.285.09:04:56.86#ibcon#read 5, iclass 37, count 0 2006.285.09:04:56.86#ibcon#about to read 6, iclass 37, count 0 2006.285.09:04:56.86#ibcon#read 6, iclass 37, count 0 2006.285.09:04:56.86#ibcon#end of sib2, iclass 37, count 0 2006.285.09:04:56.86#ibcon#*after write, iclass 37, count 0 2006.285.09:04:56.86#ibcon#*before return 0, iclass 37, count 0 2006.285.09:04:56.86#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:04:56.86#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:04:56.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.09:04:56.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.09:04:56.86$vck44/vabw=wide 2006.285.09:04:56.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.09:04:56.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.09:04:56.86#ibcon#ireg 8 cls_cnt 0 2006.285.09:04:56.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:04:56.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:04:56.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:04:56.86#ibcon#enter wrdev, iclass 39, count 0 2006.285.09:04:56.86#ibcon#first serial, iclass 39, count 0 2006.285.09:04:56.86#ibcon#enter sib2, iclass 39, count 0 2006.285.09:04:56.86#ibcon#flushed, iclass 39, count 0 2006.285.09:04:56.86#ibcon#about to write, iclass 39, count 0 2006.285.09:04:56.86#ibcon#wrote, iclass 39, count 0 2006.285.09:04:56.86#ibcon#about to read 3, iclass 39, count 0 2006.285.09:04:56.88#ibcon#read 3, iclass 39, count 0 2006.285.09:04:56.88#ibcon#about to read 4, iclass 39, count 0 2006.285.09:04:56.88#ibcon#read 4, iclass 39, count 0 2006.285.09:04:56.88#ibcon#about to read 5, iclass 39, count 0 2006.285.09:04:56.88#ibcon#read 5, iclass 39, count 0 2006.285.09:04:56.88#ibcon#about to read 6, iclass 39, count 0 2006.285.09:04:56.88#ibcon#read 6, iclass 39, count 0 2006.285.09:04:56.88#ibcon#end of sib2, iclass 39, count 0 2006.285.09:04:56.88#ibcon#*mode == 0, iclass 39, count 0 2006.285.09:04:56.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.09:04:56.88#ibcon#[25=BW32\r\n] 2006.285.09:04:56.88#ibcon#*before write, iclass 39, count 0 2006.285.09:04:56.88#ibcon#enter sib2, iclass 39, count 0 2006.285.09:04:56.88#ibcon#flushed, iclass 39, count 0 2006.285.09:04:56.88#ibcon#about to write, iclass 39, count 0 2006.285.09:04:56.88#ibcon#wrote, iclass 39, count 0 2006.285.09:04:56.88#ibcon#about to read 3, iclass 39, count 0 2006.285.09:04:56.91#ibcon#read 3, iclass 39, count 0 2006.285.09:04:56.91#ibcon#about to read 4, iclass 39, count 0 2006.285.09:04:56.91#ibcon#read 4, iclass 39, count 0 2006.285.09:04:56.91#ibcon#about to read 5, iclass 39, count 0 2006.285.09:04:56.91#ibcon#read 5, iclass 39, count 0 2006.285.09:04:56.91#ibcon#about to read 6, iclass 39, count 0 2006.285.09:04:56.91#ibcon#read 6, iclass 39, count 0 2006.285.09:04:56.91#ibcon#end of sib2, iclass 39, count 0 2006.285.09:04:56.91#ibcon#*after write, iclass 39, count 0 2006.285.09:04:56.91#ibcon#*before return 0, iclass 39, count 0 2006.285.09:04:56.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:04:56.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:04:56.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.09:04:56.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.09:04:56.91$vck44/vbbw=wide 2006.285.09:04:56.91#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.09:04:56.91#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.09:04:56.91#ibcon#ireg 8 cls_cnt 0 2006.285.09:04:56.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:04:56.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:04:56.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:04:56.98#ibcon#enter wrdev, iclass 3, count 0 2006.285.09:04:56.98#ibcon#first serial, iclass 3, count 0 2006.285.09:04:56.98#ibcon#enter sib2, iclass 3, count 0 2006.285.09:04:56.98#ibcon#flushed, iclass 3, count 0 2006.285.09:04:56.98#ibcon#about to write, iclass 3, count 0 2006.285.09:04:56.98#ibcon#wrote, iclass 3, count 0 2006.285.09:04:56.98#ibcon#about to read 3, iclass 3, count 0 2006.285.09:04:57.00#ibcon#read 3, iclass 3, count 0 2006.285.09:04:57.00#ibcon#about to read 4, iclass 3, count 0 2006.285.09:04:57.00#ibcon#read 4, iclass 3, count 0 2006.285.09:04:57.00#ibcon#about to read 5, iclass 3, count 0 2006.285.09:04:57.00#ibcon#read 5, iclass 3, count 0 2006.285.09:04:57.00#ibcon#about to read 6, iclass 3, count 0 2006.285.09:04:57.00#ibcon#read 6, iclass 3, count 0 2006.285.09:04:57.00#ibcon#end of sib2, iclass 3, count 0 2006.285.09:04:57.00#ibcon#*mode == 0, iclass 3, count 0 2006.285.09:04:57.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.09:04:57.00#ibcon#[27=BW32\r\n] 2006.285.09:04:57.00#ibcon#*before write, iclass 3, count 0 2006.285.09:04:57.00#ibcon#enter sib2, iclass 3, count 0 2006.285.09:04:57.00#ibcon#flushed, iclass 3, count 0 2006.285.09:04:57.00#ibcon#about to write, iclass 3, count 0 2006.285.09:04:57.00#ibcon#wrote, iclass 3, count 0 2006.285.09:04:57.00#ibcon#about to read 3, iclass 3, count 0 2006.285.09:04:57.03#ibcon#read 3, iclass 3, count 0 2006.285.09:04:57.03#ibcon#about to read 4, iclass 3, count 0 2006.285.09:04:57.03#ibcon#read 4, iclass 3, count 0 2006.285.09:04:57.03#ibcon#about to read 5, iclass 3, count 0 2006.285.09:04:57.03#ibcon#read 5, iclass 3, count 0 2006.285.09:04:57.03#ibcon#about to read 6, iclass 3, count 0 2006.285.09:04:57.03#ibcon#read 6, iclass 3, count 0 2006.285.09:04:57.03#ibcon#end of sib2, iclass 3, count 0 2006.285.09:04:57.03#ibcon#*after write, iclass 3, count 0 2006.285.09:04:57.03#ibcon#*before return 0, iclass 3, count 0 2006.285.09:04:57.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:04:57.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:04:57.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.09:04:57.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.09:04:57.03$setupk4/ifdk4 2006.285.09:04:57.03$ifdk4/lo= 2006.285.09:04:57.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:04:57.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:04:57.03$ifdk4/patch= 2006.285.09:04:57.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:04:57.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:04:57.03$setupk4/!*+20s 2006.285.09:05:00.75#abcon#<5=/03 0.7 1.3 21.16 841014.9\r\n> 2006.285.09:05:00.77#abcon#{5=INTERFACE CLEAR} 2006.285.09:05:00.83#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:05:10.92#abcon#<5=/03 0.7 1.4 21.15 841014.9\r\n> 2006.285.09:05:10.94#abcon#{5=INTERFACE CLEAR} 2006.285.09:05:11.00#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:05:11.54$setupk4/"tpicd 2006.285.09:05:11.54$setupk4/echo=off 2006.285.09:05:11.54$setupk4/xlog=off 2006.285.09:05:11.54:!2006.285.09:06:22 2006.285.09:05:23.13#trakl#Source acquired 2006.285.09:05:25.13#flagr#flagr/antenna,acquired 2006.285.09:06:22.00:preob 2006.285.09:06:23.14/onsource/TRACKING 2006.285.09:06:23.14:!2006.285.09:06:32 2006.285.09:06:32.00:"tape 2006.285.09:06:32.00:"st=record 2006.285.09:06:32.00:data_valid=on 2006.285.09:06:32.00:midob 2006.285.09:06:32.14/onsource/TRACKING 2006.285.09:06:32.14/wx/21.05,1014.9,84 2006.285.09:06:32.24/cable/+6.4772E-03 2006.285.09:06:33.33/va/01,07,usb,yes,32,35 2006.285.09:06:33.33/va/02,06,usb,yes,32,33 2006.285.09:06:33.33/va/03,07,usb,yes,32,34 2006.285.09:06:33.33/va/04,06,usb,yes,33,35 2006.285.09:06:33.33/va/05,03,usb,yes,33,33 2006.285.09:06:33.33/va/06,04,usb,yes,30,29 2006.285.09:06:33.33/va/07,04,usb,yes,30,31 2006.285.09:06:33.33/va/08,03,usb,yes,31,38 2006.285.09:06:33.56/valo/01,524.99,yes,locked 2006.285.09:06:33.56/valo/02,534.99,yes,locked 2006.285.09:06:33.56/valo/03,564.99,yes,locked 2006.285.09:06:33.56/valo/04,624.99,yes,locked 2006.285.09:06:33.56/valo/05,734.99,yes,locked 2006.285.09:06:33.56/valo/06,814.99,yes,locked 2006.285.09:06:33.56/valo/07,864.99,yes,locked 2006.285.09:06:33.56/valo/08,884.99,yes,locked 2006.285.09:06:34.65/vb/01,04,usb,yes,30,28 2006.285.09:06:34.65/vb/02,05,usb,yes,29,29 2006.285.09:06:34.65/vb/03,04,usb,yes,30,33 2006.285.09:06:34.65/vb/04,05,usb,yes,30,29 2006.285.09:06:34.65/vb/05,04,usb,yes,26,29 2006.285.09:06:34.65/vb/06,03,usb,yes,38,34 2006.285.09:06:34.65/vb/07,04,usb,yes,31,31 2006.285.09:06:34.65/vb/08,04,usb,yes,28,32 2006.285.09:06:34.88/vblo/01,629.99,yes,locked 2006.285.09:06:34.88/vblo/02,634.99,yes,locked 2006.285.09:06:34.88/vblo/03,649.99,yes,locked 2006.285.09:06:34.88/vblo/04,679.99,yes,locked 2006.285.09:06:34.88/vblo/05,709.99,yes,locked 2006.285.09:06:34.88/vblo/06,719.99,yes,locked 2006.285.09:06:34.88/vblo/07,734.99,yes,locked 2006.285.09:06:34.88/vblo/08,744.99,yes,locked 2006.285.09:06:35.03/vabw/8 2006.285.09:06:35.18/vbbw/8 2006.285.09:06:35.27/xfe/off,on,12.2 2006.285.09:06:35.64/ifatt/23,28,28,28 2006.285.09:06:36.07/fmout-gps/S +2.59E-07 2006.285.09:06:36.09:!2006.285.09:09:22 2006.285.09:09:22.00:data_valid=off 2006.285.09:09:22.00:"et 2006.285.09:09:22.00:!+3s 2006.285.09:09:25.01:"tape 2006.285.09:09:25.01:postob 2006.285.09:09:25.07/cable/+6.4788E-03 2006.285.09:09:25.07/wx/20.84,1014.9,85 2006.285.09:09:26.08/fmout-gps/S +2.67E-07 2006.285.09:09:26.08:scan_name=285-0911,jd0610,70 2006.285.09:09:26.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.285.09:09:27.14#flagr#flagr/antenna,new-source 2006.285.09:09:27.14:checkk5 2006.285.09:09:27.75/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:09:28.11/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:09:28.53/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:09:28.93/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:09:29.29/chk_obsdata//k5ts1/T2850906??a.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.09:09:29.69/chk_obsdata//k5ts2/T2850906??b.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.09:09:30.21/chk_obsdata//k5ts3/T2850906??c.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.09:09:30.59/chk_obsdata//k5ts4/T2850906??d.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.09:09:31.36/k5log//k5ts1_log_newline 2006.285.09:09:32.07/k5log//k5ts2_log_newline 2006.285.09:09:32.99/k5log//k5ts3_log_newline 2006.285.09:09:33.64/k5log//k5ts4_log_newline 2006.285.09:09:33.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:09:33.66:setupk4=1 2006.285.09:09:33.66$setupk4/echo=on 2006.285.09:09:33.66$setupk4/pcalon 2006.285.09:09:33.66$pcalon/"no phase cal control is implemented here 2006.285.09:09:33.66$setupk4/"tpicd=stop 2006.285.09:09:33.66$setupk4/"rec=synch_on 2006.285.09:09:33.66$setupk4/"rec_mode=128 2006.285.09:09:33.66$setupk4/!* 2006.285.09:09:33.66$setupk4/recpk4 2006.285.09:09:33.66$recpk4/recpatch= 2006.285.09:09:33.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:09:33.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:09:33.67$setupk4/vck44 2006.285.09:09:33.67$vck44/valo=1,524.99 2006.285.09:09:33.67#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.09:09:33.67#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.09:09:33.67#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:33.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:09:33.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:09:33.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:09:33.67#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:09:33.67#ibcon#first serial, iclass 10, count 0 2006.285.09:09:33.67#ibcon#enter sib2, iclass 10, count 0 2006.285.09:09:33.67#ibcon#flushed, iclass 10, count 0 2006.285.09:09:33.67#ibcon#about to write, iclass 10, count 0 2006.285.09:09:33.67#ibcon#wrote, iclass 10, count 0 2006.285.09:09:33.67#ibcon#about to read 3, iclass 10, count 0 2006.285.09:09:33.68#ibcon#read 3, iclass 10, count 0 2006.285.09:09:33.68#ibcon#about to read 4, iclass 10, count 0 2006.285.09:09:33.68#ibcon#read 4, iclass 10, count 0 2006.285.09:09:33.68#ibcon#about to read 5, iclass 10, count 0 2006.285.09:09:33.68#ibcon#read 5, iclass 10, count 0 2006.285.09:09:33.68#ibcon#about to read 6, iclass 10, count 0 2006.285.09:09:33.68#ibcon#read 6, iclass 10, count 0 2006.285.09:09:33.68#ibcon#end of sib2, iclass 10, count 0 2006.285.09:09:33.68#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:09:33.68#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:09:33.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:09:33.68#ibcon#*before write, iclass 10, count 0 2006.285.09:09:33.68#ibcon#enter sib2, iclass 10, count 0 2006.285.09:09:33.68#ibcon#flushed, iclass 10, count 0 2006.285.09:09:33.68#ibcon#about to write, iclass 10, count 0 2006.285.09:09:33.68#ibcon#wrote, iclass 10, count 0 2006.285.09:09:33.68#ibcon#about to read 3, iclass 10, count 0 2006.285.09:09:33.73#ibcon#read 3, iclass 10, count 0 2006.285.09:09:33.73#ibcon#about to read 4, iclass 10, count 0 2006.285.09:09:33.73#ibcon#read 4, iclass 10, count 0 2006.285.09:09:33.73#ibcon#about to read 5, iclass 10, count 0 2006.285.09:09:33.73#ibcon#read 5, iclass 10, count 0 2006.285.09:09:33.73#ibcon#about to read 6, iclass 10, count 0 2006.285.09:09:33.73#ibcon#read 6, iclass 10, count 0 2006.285.09:09:33.73#ibcon#end of sib2, iclass 10, count 0 2006.285.09:09:33.73#ibcon#*after write, iclass 10, count 0 2006.285.09:09:33.73#ibcon#*before return 0, iclass 10, count 0 2006.285.09:09:33.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:09:33.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:09:33.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:09:33.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:09:33.73$vck44/va=1,7 2006.285.09:09:33.73#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.09:09:33.73#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.09:09:33.73#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:33.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:09:33.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:09:33.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:09:33.73#ibcon#enter wrdev, iclass 12, count 2 2006.285.09:09:33.73#ibcon#first serial, iclass 12, count 2 2006.285.09:09:33.73#ibcon#enter sib2, iclass 12, count 2 2006.285.09:09:33.73#ibcon#flushed, iclass 12, count 2 2006.285.09:09:33.73#ibcon#about to write, iclass 12, count 2 2006.285.09:09:33.73#ibcon#wrote, iclass 12, count 2 2006.285.09:09:33.73#ibcon#about to read 3, iclass 12, count 2 2006.285.09:09:33.75#ibcon#read 3, iclass 12, count 2 2006.285.09:09:33.75#ibcon#about to read 4, iclass 12, count 2 2006.285.09:09:33.75#ibcon#read 4, iclass 12, count 2 2006.285.09:09:33.75#ibcon#about to read 5, iclass 12, count 2 2006.285.09:09:33.75#ibcon#read 5, iclass 12, count 2 2006.285.09:09:33.75#ibcon#about to read 6, iclass 12, count 2 2006.285.09:09:33.75#ibcon#read 6, iclass 12, count 2 2006.285.09:09:33.75#ibcon#end of sib2, iclass 12, count 2 2006.285.09:09:33.75#ibcon#*mode == 0, iclass 12, count 2 2006.285.09:09:33.75#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.09:09:33.75#ibcon#[25=AT01-07\r\n] 2006.285.09:09:33.75#ibcon#*before write, iclass 12, count 2 2006.285.09:09:33.75#ibcon#enter sib2, iclass 12, count 2 2006.285.09:09:33.75#ibcon#flushed, iclass 12, count 2 2006.285.09:09:33.75#ibcon#about to write, iclass 12, count 2 2006.285.09:09:33.75#ibcon#wrote, iclass 12, count 2 2006.285.09:09:33.75#ibcon#about to read 3, iclass 12, count 2 2006.285.09:09:33.78#ibcon#read 3, iclass 12, count 2 2006.285.09:09:33.78#ibcon#about to read 4, iclass 12, count 2 2006.285.09:09:33.78#ibcon#read 4, iclass 12, count 2 2006.285.09:09:33.78#ibcon#about to read 5, iclass 12, count 2 2006.285.09:09:33.78#ibcon#read 5, iclass 12, count 2 2006.285.09:09:33.78#ibcon#about to read 6, iclass 12, count 2 2006.285.09:09:33.78#ibcon#read 6, iclass 12, count 2 2006.285.09:09:33.78#ibcon#end of sib2, iclass 12, count 2 2006.285.09:09:33.78#ibcon#*after write, iclass 12, count 2 2006.285.09:09:33.78#ibcon#*before return 0, iclass 12, count 2 2006.285.09:09:33.78#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:09:33.78#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:09:33.78#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.09:09:33.78#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:33.78#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:09:33.90#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:09:33.90#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:09:33.90#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:09:33.90#ibcon#first serial, iclass 12, count 0 2006.285.09:09:33.90#ibcon#enter sib2, iclass 12, count 0 2006.285.09:09:33.90#ibcon#flushed, iclass 12, count 0 2006.285.09:09:33.90#ibcon#about to write, iclass 12, count 0 2006.285.09:09:33.90#ibcon#wrote, iclass 12, count 0 2006.285.09:09:33.90#ibcon#about to read 3, iclass 12, count 0 2006.285.09:09:33.92#ibcon#read 3, iclass 12, count 0 2006.285.09:09:33.92#ibcon#about to read 4, iclass 12, count 0 2006.285.09:09:33.92#ibcon#read 4, iclass 12, count 0 2006.285.09:09:33.92#ibcon#about to read 5, iclass 12, count 0 2006.285.09:09:33.92#ibcon#read 5, iclass 12, count 0 2006.285.09:09:33.92#ibcon#about to read 6, iclass 12, count 0 2006.285.09:09:33.92#ibcon#read 6, iclass 12, count 0 2006.285.09:09:33.92#ibcon#end of sib2, iclass 12, count 0 2006.285.09:09:33.92#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:09:33.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:09:33.92#ibcon#[25=USB\r\n] 2006.285.09:09:33.92#ibcon#*before write, iclass 12, count 0 2006.285.09:09:33.92#ibcon#enter sib2, iclass 12, count 0 2006.285.09:09:33.92#ibcon#flushed, iclass 12, count 0 2006.285.09:09:33.92#ibcon#about to write, iclass 12, count 0 2006.285.09:09:33.92#ibcon#wrote, iclass 12, count 0 2006.285.09:09:33.92#ibcon#about to read 3, iclass 12, count 0 2006.285.09:09:33.95#ibcon#read 3, iclass 12, count 0 2006.285.09:09:33.95#ibcon#about to read 4, iclass 12, count 0 2006.285.09:09:33.95#ibcon#read 4, iclass 12, count 0 2006.285.09:09:33.95#ibcon#about to read 5, iclass 12, count 0 2006.285.09:09:33.95#ibcon#read 5, iclass 12, count 0 2006.285.09:09:33.95#ibcon#about to read 6, iclass 12, count 0 2006.285.09:09:33.95#ibcon#read 6, iclass 12, count 0 2006.285.09:09:33.95#ibcon#end of sib2, iclass 12, count 0 2006.285.09:09:33.95#ibcon#*after write, iclass 12, count 0 2006.285.09:09:33.95#ibcon#*before return 0, iclass 12, count 0 2006.285.09:09:33.95#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:09:33.95#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:09:33.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:09:33.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:09:33.95$vck44/valo=2,534.99 2006.285.09:09:33.95#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.09:09:33.95#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.09:09:33.95#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:33.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:09:33.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:09:33.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:09:33.95#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:09:33.95#ibcon#first serial, iclass 14, count 0 2006.285.09:09:33.95#ibcon#enter sib2, iclass 14, count 0 2006.285.09:09:33.95#ibcon#flushed, iclass 14, count 0 2006.285.09:09:33.95#ibcon#about to write, iclass 14, count 0 2006.285.09:09:33.95#ibcon#wrote, iclass 14, count 0 2006.285.09:09:33.95#ibcon#about to read 3, iclass 14, count 0 2006.285.09:09:33.97#ibcon#read 3, iclass 14, count 0 2006.285.09:09:33.97#ibcon#about to read 4, iclass 14, count 0 2006.285.09:09:33.97#ibcon#read 4, iclass 14, count 0 2006.285.09:09:33.97#ibcon#about to read 5, iclass 14, count 0 2006.285.09:09:33.97#ibcon#read 5, iclass 14, count 0 2006.285.09:09:33.97#ibcon#about to read 6, iclass 14, count 0 2006.285.09:09:33.97#ibcon#read 6, iclass 14, count 0 2006.285.09:09:33.97#ibcon#end of sib2, iclass 14, count 0 2006.285.09:09:33.97#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:09:33.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:09:33.97#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:09:33.97#ibcon#*before write, iclass 14, count 0 2006.285.09:09:33.97#ibcon#enter sib2, iclass 14, count 0 2006.285.09:09:33.97#ibcon#flushed, iclass 14, count 0 2006.285.09:09:33.97#ibcon#about to write, iclass 14, count 0 2006.285.09:09:33.97#ibcon#wrote, iclass 14, count 0 2006.285.09:09:33.97#ibcon#about to read 3, iclass 14, count 0 2006.285.09:09:34.01#ibcon#read 3, iclass 14, count 0 2006.285.09:09:34.01#ibcon#about to read 4, iclass 14, count 0 2006.285.09:09:34.01#ibcon#read 4, iclass 14, count 0 2006.285.09:09:34.01#ibcon#about to read 5, iclass 14, count 0 2006.285.09:09:34.01#ibcon#read 5, iclass 14, count 0 2006.285.09:09:34.01#ibcon#about to read 6, iclass 14, count 0 2006.285.09:09:34.01#ibcon#read 6, iclass 14, count 0 2006.285.09:09:34.01#ibcon#end of sib2, iclass 14, count 0 2006.285.09:09:34.01#ibcon#*after write, iclass 14, count 0 2006.285.09:09:34.01#ibcon#*before return 0, iclass 14, count 0 2006.285.09:09:34.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:09:34.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:09:34.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:09:34.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:09:34.01$vck44/va=2,6 2006.285.09:09:34.01#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.09:09:34.01#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.09:09:34.01#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:34.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:09:34.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:09:34.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:09:34.07#ibcon#enter wrdev, iclass 16, count 2 2006.285.09:09:34.07#ibcon#first serial, iclass 16, count 2 2006.285.09:09:34.07#ibcon#enter sib2, iclass 16, count 2 2006.285.09:09:34.07#ibcon#flushed, iclass 16, count 2 2006.285.09:09:34.07#ibcon#about to write, iclass 16, count 2 2006.285.09:09:34.07#ibcon#wrote, iclass 16, count 2 2006.285.09:09:34.07#ibcon#about to read 3, iclass 16, count 2 2006.285.09:09:34.09#ibcon#read 3, iclass 16, count 2 2006.285.09:09:34.09#ibcon#about to read 4, iclass 16, count 2 2006.285.09:09:34.09#ibcon#read 4, iclass 16, count 2 2006.285.09:09:34.09#ibcon#about to read 5, iclass 16, count 2 2006.285.09:09:34.09#ibcon#read 5, iclass 16, count 2 2006.285.09:09:34.09#ibcon#about to read 6, iclass 16, count 2 2006.285.09:09:34.09#ibcon#read 6, iclass 16, count 2 2006.285.09:09:34.09#ibcon#end of sib2, iclass 16, count 2 2006.285.09:09:34.09#ibcon#*mode == 0, iclass 16, count 2 2006.285.09:09:34.09#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.09:09:34.09#ibcon#[25=AT02-06\r\n] 2006.285.09:09:34.09#ibcon#*before write, iclass 16, count 2 2006.285.09:09:34.09#ibcon#enter sib2, iclass 16, count 2 2006.285.09:09:34.09#ibcon#flushed, iclass 16, count 2 2006.285.09:09:34.09#ibcon#about to write, iclass 16, count 2 2006.285.09:09:34.09#ibcon#wrote, iclass 16, count 2 2006.285.09:09:34.09#ibcon#about to read 3, iclass 16, count 2 2006.285.09:09:34.12#ibcon#read 3, iclass 16, count 2 2006.285.09:09:34.12#ibcon#about to read 4, iclass 16, count 2 2006.285.09:09:34.12#ibcon#read 4, iclass 16, count 2 2006.285.09:09:34.12#ibcon#about to read 5, iclass 16, count 2 2006.285.09:09:34.12#ibcon#read 5, iclass 16, count 2 2006.285.09:09:34.12#ibcon#about to read 6, iclass 16, count 2 2006.285.09:09:34.12#ibcon#read 6, iclass 16, count 2 2006.285.09:09:34.12#ibcon#end of sib2, iclass 16, count 2 2006.285.09:09:34.12#ibcon#*after write, iclass 16, count 2 2006.285.09:09:34.12#ibcon#*before return 0, iclass 16, count 2 2006.285.09:09:34.12#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:09:34.12#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:09:34.12#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.09:09:34.12#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:34.12#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:09:34.24#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:09:34.24#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:09:34.24#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:09:34.24#ibcon#first serial, iclass 16, count 0 2006.285.09:09:34.24#ibcon#enter sib2, iclass 16, count 0 2006.285.09:09:34.24#ibcon#flushed, iclass 16, count 0 2006.285.09:09:34.24#ibcon#about to write, iclass 16, count 0 2006.285.09:09:34.24#ibcon#wrote, iclass 16, count 0 2006.285.09:09:34.24#ibcon#about to read 3, iclass 16, count 0 2006.285.09:09:34.26#ibcon#read 3, iclass 16, count 0 2006.285.09:09:34.26#ibcon#about to read 4, iclass 16, count 0 2006.285.09:09:34.26#ibcon#read 4, iclass 16, count 0 2006.285.09:09:34.26#ibcon#about to read 5, iclass 16, count 0 2006.285.09:09:34.26#ibcon#read 5, iclass 16, count 0 2006.285.09:09:34.26#ibcon#about to read 6, iclass 16, count 0 2006.285.09:09:34.26#ibcon#read 6, iclass 16, count 0 2006.285.09:09:34.26#ibcon#end of sib2, iclass 16, count 0 2006.285.09:09:34.26#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:09:34.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:09:34.26#ibcon#[25=USB\r\n] 2006.285.09:09:34.26#ibcon#*before write, iclass 16, count 0 2006.285.09:09:34.26#ibcon#enter sib2, iclass 16, count 0 2006.285.09:09:34.26#ibcon#flushed, iclass 16, count 0 2006.285.09:09:34.26#ibcon#about to write, iclass 16, count 0 2006.285.09:09:34.26#ibcon#wrote, iclass 16, count 0 2006.285.09:09:34.26#ibcon#about to read 3, iclass 16, count 0 2006.285.09:09:34.29#ibcon#read 3, iclass 16, count 0 2006.285.09:09:34.29#ibcon#about to read 4, iclass 16, count 0 2006.285.09:09:34.29#ibcon#read 4, iclass 16, count 0 2006.285.09:09:34.29#ibcon#about to read 5, iclass 16, count 0 2006.285.09:09:34.29#ibcon#read 5, iclass 16, count 0 2006.285.09:09:34.29#ibcon#about to read 6, iclass 16, count 0 2006.285.09:09:34.29#ibcon#read 6, iclass 16, count 0 2006.285.09:09:34.29#ibcon#end of sib2, iclass 16, count 0 2006.285.09:09:34.29#ibcon#*after write, iclass 16, count 0 2006.285.09:09:34.29#ibcon#*before return 0, iclass 16, count 0 2006.285.09:09:34.29#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:09:34.29#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:09:34.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:09:34.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:09:34.29$vck44/valo=3,564.99 2006.285.09:09:34.29#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.09:09:34.29#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.09:09:34.29#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:34.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:09:34.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:09:34.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:09:34.29#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:09:34.29#ibcon#first serial, iclass 18, count 0 2006.285.09:09:34.29#ibcon#enter sib2, iclass 18, count 0 2006.285.09:09:34.29#ibcon#flushed, iclass 18, count 0 2006.285.09:09:34.29#ibcon#about to write, iclass 18, count 0 2006.285.09:09:34.29#ibcon#wrote, iclass 18, count 0 2006.285.09:09:34.29#ibcon#about to read 3, iclass 18, count 0 2006.285.09:09:34.31#ibcon#read 3, iclass 18, count 0 2006.285.09:09:34.31#ibcon#about to read 4, iclass 18, count 0 2006.285.09:09:34.31#ibcon#read 4, iclass 18, count 0 2006.285.09:09:34.31#ibcon#about to read 5, iclass 18, count 0 2006.285.09:09:34.31#ibcon#read 5, iclass 18, count 0 2006.285.09:09:34.31#ibcon#about to read 6, iclass 18, count 0 2006.285.09:09:34.31#ibcon#read 6, iclass 18, count 0 2006.285.09:09:34.31#ibcon#end of sib2, iclass 18, count 0 2006.285.09:09:34.31#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:09:34.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:09:34.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:09:34.31#ibcon#*before write, iclass 18, count 0 2006.285.09:09:34.31#ibcon#enter sib2, iclass 18, count 0 2006.285.09:09:34.31#ibcon#flushed, iclass 18, count 0 2006.285.09:09:34.31#ibcon#about to write, iclass 18, count 0 2006.285.09:09:34.31#ibcon#wrote, iclass 18, count 0 2006.285.09:09:34.31#ibcon#about to read 3, iclass 18, count 0 2006.285.09:09:34.35#ibcon#read 3, iclass 18, count 0 2006.285.09:09:34.35#ibcon#about to read 4, iclass 18, count 0 2006.285.09:09:34.35#ibcon#read 4, iclass 18, count 0 2006.285.09:09:34.35#ibcon#about to read 5, iclass 18, count 0 2006.285.09:09:34.35#ibcon#read 5, iclass 18, count 0 2006.285.09:09:34.35#ibcon#about to read 6, iclass 18, count 0 2006.285.09:09:34.35#ibcon#read 6, iclass 18, count 0 2006.285.09:09:34.35#ibcon#end of sib2, iclass 18, count 0 2006.285.09:09:34.35#ibcon#*after write, iclass 18, count 0 2006.285.09:09:34.35#ibcon#*before return 0, iclass 18, count 0 2006.285.09:09:34.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:09:34.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:09:34.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:09:34.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:09:34.35$vck44/va=3,7 2006.285.09:09:34.35#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.09:09:34.35#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.09:09:34.35#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:34.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:09:34.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:09:34.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:09:34.41#ibcon#enter wrdev, iclass 20, count 2 2006.285.09:09:34.41#ibcon#first serial, iclass 20, count 2 2006.285.09:09:34.41#ibcon#enter sib2, iclass 20, count 2 2006.285.09:09:34.41#ibcon#flushed, iclass 20, count 2 2006.285.09:09:34.41#ibcon#about to write, iclass 20, count 2 2006.285.09:09:34.41#ibcon#wrote, iclass 20, count 2 2006.285.09:09:34.41#ibcon#about to read 3, iclass 20, count 2 2006.285.09:09:34.43#ibcon#read 3, iclass 20, count 2 2006.285.09:09:34.43#ibcon#about to read 4, iclass 20, count 2 2006.285.09:09:34.43#ibcon#read 4, iclass 20, count 2 2006.285.09:09:34.43#ibcon#about to read 5, iclass 20, count 2 2006.285.09:09:34.43#ibcon#read 5, iclass 20, count 2 2006.285.09:09:34.43#ibcon#about to read 6, iclass 20, count 2 2006.285.09:09:34.43#ibcon#read 6, iclass 20, count 2 2006.285.09:09:34.43#ibcon#end of sib2, iclass 20, count 2 2006.285.09:09:34.43#ibcon#*mode == 0, iclass 20, count 2 2006.285.09:09:34.43#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.09:09:34.43#ibcon#[25=AT03-07\r\n] 2006.285.09:09:34.43#ibcon#*before write, iclass 20, count 2 2006.285.09:09:34.43#ibcon#enter sib2, iclass 20, count 2 2006.285.09:09:34.43#ibcon#flushed, iclass 20, count 2 2006.285.09:09:34.43#ibcon#about to write, iclass 20, count 2 2006.285.09:09:34.43#ibcon#wrote, iclass 20, count 2 2006.285.09:09:34.43#ibcon#about to read 3, iclass 20, count 2 2006.285.09:09:34.46#ibcon#read 3, iclass 20, count 2 2006.285.09:09:34.46#ibcon#about to read 4, iclass 20, count 2 2006.285.09:09:34.46#ibcon#read 4, iclass 20, count 2 2006.285.09:09:34.46#ibcon#about to read 5, iclass 20, count 2 2006.285.09:09:34.46#ibcon#read 5, iclass 20, count 2 2006.285.09:09:34.46#ibcon#about to read 6, iclass 20, count 2 2006.285.09:09:34.46#ibcon#read 6, iclass 20, count 2 2006.285.09:09:34.46#ibcon#end of sib2, iclass 20, count 2 2006.285.09:09:34.46#ibcon#*after write, iclass 20, count 2 2006.285.09:09:34.46#ibcon#*before return 0, iclass 20, count 2 2006.285.09:09:34.46#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:09:34.46#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:09:34.46#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.09:09:34.46#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:34.46#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:09:34.58#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:09:34.58#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:09:34.58#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:09:34.58#ibcon#first serial, iclass 20, count 0 2006.285.09:09:34.58#ibcon#enter sib2, iclass 20, count 0 2006.285.09:09:34.58#ibcon#flushed, iclass 20, count 0 2006.285.09:09:34.58#ibcon#about to write, iclass 20, count 0 2006.285.09:09:34.58#ibcon#wrote, iclass 20, count 0 2006.285.09:09:34.58#ibcon#about to read 3, iclass 20, count 0 2006.285.09:09:34.60#ibcon#read 3, iclass 20, count 0 2006.285.09:09:34.60#ibcon#about to read 4, iclass 20, count 0 2006.285.09:09:34.60#ibcon#read 4, iclass 20, count 0 2006.285.09:09:34.60#ibcon#about to read 5, iclass 20, count 0 2006.285.09:09:34.60#ibcon#read 5, iclass 20, count 0 2006.285.09:09:34.60#ibcon#about to read 6, iclass 20, count 0 2006.285.09:09:34.60#ibcon#read 6, iclass 20, count 0 2006.285.09:09:34.60#ibcon#end of sib2, iclass 20, count 0 2006.285.09:09:34.60#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:09:34.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:09:34.60#ibcon#[25=USB\r\n] 2006.285.09:09:34.60#ibcon#*before write, iclass 20, count 0 2006.285.09:09:34.60#ibcon#enter sib2, iclass 20, count 0 2006.285.09:09:34.60#ibcon#flushed, iclass 20, count 0 2006.285.09:09:34.60#ibcon#about to write, iclass 20, count 0 2006.285.09:09:34.60#ibcon#wrote, iclass 20, count 0 2006.285.09:09:34.60#ibcon#about to read 3, iclass 20, count 0 2006.285.09:09:34.63#ibcon#read 3, iclass 20, count 0 2006.285.09:09:34.63#ibcon#about to read 4, iclass 20, count 0 2006.285.09:09:34.63#ibcon#read 4, iclass 20, count 0 2006.285.09:09:34.63#ibcon#about to read 5, iclass 20, count 0 2006.285.09:09:34.63#ibcon#read 5, iclass 20, count 0 2006.285.09:09:34.63#ibcon#about to read 6, iclass 20, count 0 2006.285.09:09:34.63#ibcon#read 6, iclass 20, count 0 2006.285.09:09:34.63#ibcon#end of sib2, iclass 20, count 0 2006.285.09:09:34.63#ibcon#*after write, iclass 20, count 0 2006.285.09:09:34.63#ibcon#*before return 0, iclass 20, count 0 2006.285.09:09:34.63#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:09:34.63#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:09:34.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:09:34.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:09:34.63$vck44/valo=4,624.99 2006.285.09:09:34.63#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.09:09:34.63#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.09:09:34.63#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:34.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:09:34.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:09:34.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:09:34.63#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:09:34.63#ibcon#first serial, iclass 22, count 0 2006.285.09:09:34.63#ibcon#enter sib2, iclass 22, count 0 2006.285.09:09:34.63#ibcon#flushed, iclass 22, count 0 2006.285.09:09:34.63#ibcon#about to write, iclass 22, count 0 2006.285.09:09:34.63#ibcon#wrote, iclass 22, count 0 2006.285.09:09:34.63#ibcon#about to read 3, iclass 22, count 0 2006.285.09:09:34.65#ibcon#read 3, iclass 22, count 0 2006.285.09:09:34.65#ibcon#about to read 4, iclass 22, count 0 2006.285.09:09:34.65#ibcon#read 4, iclass 22, count 0 2006.285.09:09:34.65#ibcon#about to read 5, iclass 22, count 0 2006.285.09:09:34.65#ibcon#read 5, iclass 22, count 0 2006.285.09:09:34.65#ibcon#about to read 6, iclass 22, count 0 2006.285.09:09:34.65#ibcon#read 6, iclass 22, count 0 2006.285.09:09:34.65#ibcon#end of sib2, iclass 22, count 0 2006.285.09:09:34.65#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:09:34.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:09:34.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:09:34.65#ibcon#*before write, iclass 22, count 0 2006.285.09:09:34.65#ibcon#enter sib2, iclass 22, count 0 2006.285.09:09:34.65#ibcon#flushed, iclass 22, count 0 2006.285.09:09:34.65#ibcon#about to write, iclass 22, count 0 2006.285.09:09:34.65#ibcon#wrote, iclass 22, count 0 2006.285.09:09:34.65#ibcon#about to read 3, iclass 22, count 0 2006.285.09:09:34.69#ibcon#read 3, iclass 22, count 0 2006.285.09:09:34.69#ibcon#about to read 4, iclass 22, count 0 2006.285.09:09:34.69#ibcon#read 4, iclass 22, count 0 2006.285.09:09:34.69#ibcon#about to read 5, iclass 22, count 0 2006.285.09:09:34.69#ibcon#read 5, iclass 22, count 0 2006.285.09:09:34.69#ibcon#about to read 6, iclass 22, count 0 2006.285.09:09:34.69#ibcon#read 6, iclass 22, count 0 2006.285.09:09:34.69#ibcon#end of sib2, iclass 22, count 0 2006.285.09:09:34.69#ibcon#*after write, iclass 22, count 0 2006.285.09:09:34.69#ibcon#*before return 0, iclass 22, count 0 2006.285.09:09:34.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:09:34.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:09:34.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:09:34.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:09:34.69$vck44/va=4,6 2006.285.09:09:34.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.09:09:34.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.09:09:34.69#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:34.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:09:34.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:09:34.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:09:34.75#ibcon#enter wrdev, iclass 24, count 2 2006.285.09:09:34.75#ibcon#first serial, iclass 24, count 2 2006.285.09:09:34.75#ibcon#enter sib2, iclass 24, count 2 2006.285.09:09:34.75#ibcon#flushed, iclass 24, count 2 2006.285.09:09:34.75#ibcon#about to write, iclass 24, count 2 2006.285.09:09:34.75#ibcon#wrote, iclass 24, count 2 2006.285.09:09:34.75#ibcon#about to read 3, iclass 24, count 2 2006.285.09:09:34.77#ibcon#read 3, iclass 24, count 2 2006.285.09:09:34.77#ibcon#about to read 4, iclass 24, count 2 2006.285.09:09:34.77#ibcon#read 4, iclass 24, count 2 2006.285.09:09:34.77#ibcon#about to read 5, iclass 24, count 2 2006.285.09:09:34.77#ibcon#read 5, iclass 24, count 2 2006.285.09:09:34.77#ibcon#about to read 6, iclass 24, count 2 2006.285.09:09:34.77#ibcon#read 6, iclass 24, count 2 2006.285.09:09:34.77#ibcon#end of sib2, iclass 24, count 2 2006.285.09:09:34.77#ibcon#*mode == 0, iclass 24, count 2 2006.285.09:09:34.77#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.09:09:34.77#ibcon#[25=AT04-06\r\n] 2006.285.09:09:34.77#ibcon#*before write, iclass 24, count 2 2006.285.09:09:34.77#ibcon#enter sib2, iclass 24, count 2 2006.285.09:09:34.77#ibcon#flushed, iclass 24, count 2 2006.285.09:09:34.77#ibcon#about to write, iclass 24, count 2 2006.285.09:09:34.77#ibcon#wrote, iclass 24, count 2 2006.285.09:09:34.77#ibcon#about to read 3, iclass 24, count 2 2006.285.09:09:34.80#ibcon#read 3, iclass 24, count 2 2006.285.09:09:34.80#ibcon#about to read 4, iclass 24, count 2 2006.285.09:09:34.80#ibcon#read 4, iclass 24, count 2 2006.285.09:09:34.80#ibcon#about to read 5, iclass 24, count 2 2006.285.09:09:34.80#ibcon#read 5, iclass 24, count 2 2006.285.09:09:34.80#ibcon#about to read 6, iclass 24, count 2 2006.285.09:09:34.80#ibcon#read 6, iclass 24, count 2 2006.285.09:09:34.80#ibcon#end of sib2, iclass 24, count 2 2006.285.09:09:34.80#ibcon#*after write, iclass 24, count 2 2006.285.09:09:34.80#ibcon#*before return 0, iclass 24, count 2 2006.285.09:09:34.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:09:34.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:09:34.80#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.09:09:34.80#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:34.80#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:09:34.92#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:09:34.92#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:09:34.92#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:09:34.92#ibcon#first serial, iclass 24, count 0 2006.285.09:09:34.92#ibcon#enter sib2, iclass 24, count 0 2006.285.09:09:34.92#ibcon#flushed, iclass 24, count 0 2006.285.09:09:34.92#ibcon#about to write, iclass 24, count 0 2006.285.09:09:34.92#ibcon#wrote, iclass 24, count 0 2006.285.09:09:34.92#ibcon#about to read 3, iclass 24, count 0 2006.285.09:09:34.94#ibcon#read 3, iclass 24, count 0 2006.285.09:09:34.94#ibcon#about to read 4, iclass 24, count 0 2006.285.09:09:34.94#ibcon#read 4, iclass 24, count 0 2006.285.09:09:34.94#ibcon#about to read 5, iclass 24, count 0 2006.285.09:09:34.94#ibcon#read 5, iclass 24, count 0 2006.285.09:09:34.94#ibcon#about to read 6, iclass 24, count 0 2006.285.09:09:34.94#ibcon#read 6, iclass 24, count 0 2006.285.09:09:34.94#ibcon#end of sib2, iclass 24, count 0 2006.285.09:09:34.94#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:09:34.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:09:34.94#ibcon#[25=USB\r\n] 2006.285.09:09:34.94#ibcon#*before write, iclass 24, count 0 2006.285.09:09:34.94#ibcon#enter sib2, iclass 24, count 0 2006.285.09:09:34.94#ibcon#flushed, iclass 24, count 0 2006.285.09:09:34.94#ibcon#about to write, iclass 24, count 0 2006.285.09:09:34.94#ibcon#wrote, iclass 24, count 0 2006.285.09:09:34.94#ibcon#about to read 3, iclass 24, count 0 2006.285.09:09:34.97#ibcon#read 3, iclass 24, count 0 2006.285.09:09:34.97#ibcon#about to read 4, iclass 24, count 0 2006.285.09:09:34.97#ibcon#read 4, iclass 24, count 0 2006.285.09:09:34.97#ibcon#about to read 5, iclass 24, count 0 2006.285.09:09:34.97#ibcon#read 5, iclass 24, count 0 2006.285.09:09:34.97#ibcon#about to read 6, iclass 24, count 0 2006.285.09:09:34.97#ibcon#read 6, iclass 24, count 0 2006.285.09:09:34.97#ibcon#end of sib2, iclass 24, count 0 2006.285.09:09:34.97#ibcon#*after write, iclass 24, count 0 2006.285.09:09:34.97#ibcon#*before return 0, iclass 24, count 0 2006.285.09:09:34.97#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:09:34.97#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:09:34.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:09:34.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:09:34.97$vck44/valo=5,734.99 2006.285.09:09:34.97#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.09:09:34.97#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.09:09:34.97#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:34.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:09:34.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:09:34.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:09:34.97#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:09:34.97#ibcon#first serial, iclass 26, count 0 2006.285.09:09:34.97#ibcon#enter sib2, iclass 26, count 0 2006.285.09:09:34.97#ibcon#flushed, iclass 26, count 0 2006.285.09:09:34.97#ibcon#about to write, iclass 26, count 0 2006.285.09:09:34.97#ibcon#wrote, iclass 26, count 0 2006.285.09:09:34.97#ibcon#about to read 3, iclass 26, count 0 2006.285.09:09:34.99#ibcon#read 3, iclass 26, count 0 2006.285.09:09:34.99#ibcon#about to read 4, iclass 26, count 0 2006.285.09:09:34.99#ibcon#read 4, iclass 26, count 0 2006.285.09:09:34.99#ibcon#about to read 5, iclass 26, count 0 2006.285.09:09:34.99#ibcon#read 5, iclass 26, count 0 2006.285.09:09:34.99#ibcon#about to read 6, iclass 26, count 0 2006.285.09:09:34.99#ibcon#read 6, iclass 26, count 0 2006.285.09:09:34.99#ibcon#end of sib2, iclass 26, count 0 2006.285.09:09:34.99#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:09:34.99#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:09:34.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:09:34.99#ibcon#*before write, iclass 26, count 0 2006.285.09:09:34.99#ibcon#enter sib2, iclass 26, count 0 2006.285.09:09:34.99#ibcon#flushed, iclass 26, count 0 2006.285.09:09:34.99#ibcon#about to write, iclass 26, count 0 2006.285.09:09:34.99#ibcon#wrote, iclass 26, count 0 2006.285.09:09:34.99#ibcon#about to read 3, iclass 26, count 0 2006.285.09:09:35.03#ibcon#read 3, iclass 26, count 0 2006.285.09:09:35.03#ibcon#about to read 4, iclass 26, count 0 2006.285.09:09:35.03#ibcon#read 4, iclass 26, count 0 2006.285.09:09:35.03#ibcon#about to read 5, iclass 26, count 0 2006.285.09:09:35.03#ibcon#read 5, iclass 26, count 0 2006.285.09:09:35.03#ibcon#about to read 6, iclass 26, count 0 2006.285.09:09:35.03#ibcon#read 6, iclass 26, count 0 2006.285.09:09:35.03#ibcon#end of sib2, iclass 26, count 0 2006.285.09:09:35.03#ibcon#*after write, iclass 26, count 0 2006.285.09:09:35.03#ibcon#*before return 0, iclass 26, count 0 2006.285.09:09:35.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:09:35.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:09:35.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:09:35.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:09:35.03$vck44/va=5,3 2006.285.09:09:35.03#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.09:09:35.03#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.09:09:35.03#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:35.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:09:35.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:09:35.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:09:35.09#ibcon#enter wrdev, iclass 28, count 2 2006.285.09:09:35.09#ibcon#first serial, iclass 28, count 2 2006.285.09:09:35.09#ibcon#enter sib2, iclass 28, count 2 2006.285.09:09:35.09#ibcon#flushed, iclass 28, count 2 2006.285.09:09:35.09#ibcon#about to write, iclass 28, count 2 2006.285.09:09:35.09#ibcon#wrote, iclass 28, count 2 2006.285.09:09:35.09#ibcon#about to read 3, iclass 28, count 2 2006.285.09:09:35.11#ibcon#read 3, iclass 28, count 2 2006.285.09:09:35.11#ibcon#about to read 4, iclass 28, count 2 2006.285.09:09:35.11#ibcon#read 4, iclass 28, count 2 2006.285.09:09:35.11#ibcon#about to read 5, iclass 28, count 2 2006.285.09:09:35.11#ibcon#read 5, iclass 28, count 2 2006.285.09:09:35.11#ibcon#about to read 6, iclass 28, count 2 2006.285.09:09:35.11#ibcon#read 6, iclass 28, count 2 2006.285.09:09:35.11#ibcon#end of sib2, iclass 28, count 2 2006.285.09:09:35.11#ibcon#*mode == 0, iclass 28, count 2 2006.285.09:09:35.11#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.09:09:35.11#ibcon#[25=AT05-03\r\n] 2006.285.09:09:35.11#ibcon#*before write, iclass 28, count 2 2006.285.09:09:35.11#ibcon#enter sib2, iclass 28, count 2 2006.285.09:09:35.11#ibcon#flushed, iclass 28, count 2 2006.285.09:09:35.11#ibcon#about to write, iclass 28, count 2 2006.285.09:09:35.11#ibcon#wrote, iclass 28, count 2 2006.285.09:09:35.11#ibcon#about to read 3, iclass 28, count 2 2006.285.09:09:35.14#ibcon#read 3, iclass 28, count 2 2006.285.09:09:35.14#ibcon#about to read 4, iclass 28, count 2 2006.285.09:09:35.14#ibcon#read 4, iclass 28, count 2 2006.285.09:09:35.14#ibcon#about to read 5, iclass 28, count 2 2006.285.09:09:35.14#ibcon#read 5, iclass 28, count 2 2006.285.09:09:35.14#ibcon#about to read 6, iclass 28, count 2 2006.285.09:09:35.14#ibcon#read 6, iclass 28, count 2 2006.285.09:09:35.14#ibcon#end of sib2, iclass 28, count 2 2006.285.09:09:35.14#ibcon#*after write, iclass 28, count 2 2006.285.09:09:35.14#ibcon#*before return 0, iclass 28, count 2 2006.285.09:09:35.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:09:35.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:09:35.14#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.09:09:35.14#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:35.14#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:09:35.26#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:09:35.26#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:09:35.26#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:09:35.26#ibcon#first serial, iclass 28, count 0 2006.285.09:09:35.26#ibcon#enter sib2, iclass 28, count 0 2006.285.09:09:35.26#ibcon#flushed, iclass 28, count 0 2006.285.09:09:35.26#ibcon#about to write, iclass 28, count 0 2006.285.09:09:35.26#ibcon#wrote, iclass 28, count 0 2006.285.09:09:35.26#ibcon#about to read 3, iclass 28, count 0 2006.285.09:09:35.28#ibcon#read 3, iclass 28, count 0 2006.285.09:09:35.28#ibcon#about to read 4, iclass 28, count 0 2006.285.09:09:35.28#ibcon#read 4, iclass 28, count 0 2006.285.09:09:35.28#ibcon#about to read 5, iclass 28, count 0 2006.285.09:09:35.28#ibcon#read 5, iclass 28, count 0 2006.285.09:09:35.28#ibcon#about to read 6, iclass 28, count 0 2006.285.09:09:35.28#ibcon#read 6, iclass 28, count 0 2006.285.09:09:35.28#ibcon#end of sib2, iclass 28, count 0 2006.285.09:09:35.28#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:09:35.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:09:35.28#ibcon#[25=USB\r\n] 2006.285.09:09:35.28#ibcon#*before write, iclass 28, count 0 2006.285.09:09:35.28#ibcon#enter sib2, iclass 28, count 0 2006.285.09:09:35.28#ibcon#flushed, iclass 28, count 0 2006.285.09:09:35.28#ibcon#about to write, iclass 28, count 0 2006.285.09:09:35.28#ibcon#wrote, iclass 28, count 0 2006.285.09:09:35.28#ibcon#about to read 3, iclass 28, count 0 2006.285.09:09:35.31#ibcon#read 3, iclass 28, count 0 2006.285.09:09:35.31#ibcon#about to read 4, iclass 28, count 0 2006.285.09:09:35.31#ibcon#read 4, iclass 28, count 0 2006.285.09:09:35.31#ibcon#about to read 5, iclass 28, count 0 2006.285.09:09:35.31#ibcon#read 5, iclass 28, count 0 2006.285.09:09:35.31#ibcon#about to read 6, iclass 28, count 0 2006.285.09:09:35.31#ibcon#read 6, iclass 28, count 0 2006.285.09:09:35.31#ibcon#end of sib2, iclass 28, count 0 2006.285.09:09:35.31#ibcon#*after write, iclass 28, count 0 2006.285.09:09:35.31#ibcon#*before return 0, iclass 28, count 0 2006.285.09:09:35.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:09:35.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:09:35.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:09:35.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:09:35.31$vck44/valo=6,814.99 2006.285.09:09:35.31#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.09:09:35.31#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.09:09:35.31#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:35.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:09:35.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:09:35.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:09:35.31#ibcon#enter wrdev, iclass 31, count 0 2006.285.09:09:35.31#ibcon#first serial, iclass 31, count 0 2006.285.09:09:35.31#ibcon#enter sib2, iclass 31, count 0 2006.285.09:09:35.31#ibcon#flushed, iclass 31, count 0 2006.285.09:09:35.31#ibcon#about to write, iclass 31, count 0 2006.285.09:09:35.31#ibcon#wrote, iclass 31, count 0 2006.285.09:09:35.31#ibcon#about to read 3, iclass 31, count 0 2006.285.09:09:35.33#ibcon#read 3, iclass 31, count 0 2006.285.09:09:35.33#ibcon#about to read 4, iclass 31, count 0 2006.285.09:09:35.33#ibcon#read 4, iclass 31, count 0 2006.285.09:09:35.33#ibcon#about to read 5, iclass 31, count 0 2006.285.09:09:35.33#ibcon#read 5, iclass 31, count 0 2006.285.09:09:35.33#ibcon#about to read 6, iclass 31, count 0 2006.285.09:09:35.33#ibcon#read 6, iclass 31, count 0 2006.285.09:09:35.33#ibcon#end of sib2, iclass 31, count 0 2006.285.09:09:35.33#ibcon#*mode == 0, iclass 31, count 0 2006.285.09:09:35.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.09:09:35.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:09:35.33#ibcon#*before write, iclass 31, count 0 2006.285.09:09:35.33#ibcon#enter sib2, iclass 31, count 0 2006.285.09:09:35.33#ibcon#flushed, iclass 31, count 0 2006.285.09:09:35.33#ibcon#about to write, iclass 31, count 0 2006.285.09:09:35.33#ibcon#wrote, iclass 31, count 0 2006.285.09:09:35.33#ibcon#about to read 3, iclass 31, count 0 2006.285.09:09:35.37#ibcon#read 3, iclass 31, count 0 2006.285.09:09:35.37#ibcon#about to read 4, iclass 31, count 0 2006.285.09:09:35.37#ibcon#read 4, iclass 31, count 0 2006.285.09:09:35.37#ibcon#about to read 5, iclass 31, count 0 2006.285.09:09:35.37#ibcon#read 5, iclass 31, count 0 2006.285.09:09:35.37#ibcon#about to read 6, iclass 31, count 0 2006.285.09:09:35.37#ibcon#read 6, iclass 31, count 0 2006.285.09:09:35.37#ibcon#end of sib2, iclass 31, count 0 2006.285.09:09:35.37#ibcon#*after write, iclass 31, count 0 2006.285.09:09:35.37#ibcon#*before return 0, iclass 31, count 0 2006.285.09:09:35.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:09:35.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:09:35.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.09:09:35.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.09:09:35.37$vck44/va=6,4 2006.285.09:09:35.37#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.09:09:35.37#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.09:09:35.37#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:35.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:09:35.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:09:35.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:09:35.43#ibcon#enter wrdev, iclass 33, count 2 2006.285.09:09:35.43#ibcon#first serial, iclass 33, count 2 2006.285.09:09:35.43#ibcon#enter sib2, iclass 33, count 2 2006.285.09:09:35.43#ibcon#flushed, iclass 33, count 2 2006.285.09:09:35.43#ibcon#about to write, iclass 33, count 2 2006.285.09:09:35.43#ibcon#wrote, iclass 33, count 2 2006.285.09:09:35.43#ibcon#about to read 3, iclass 33, count 2 2006.285.09:09:35.45#ibcon#read 3, iclass 33, count 2 2006.285.09:09:35.45#ibcon#about to read 4, iclass 33, count 2 2006.285.09:09:35.45#ibcon#read 4, iclass 33, count 2 2006.285.09:09:35.45#ibcon#about to read 5, iclass 33, count 2 2006.285.09:09:35.45#ibcon#read 5, iclass 33, count 2 2006.285.09:09:35.45#ibcon#about to read 6, iclass 33, count 2 2006.285.09:09:35.45#ibcon#read 6, iclass 33, count 2 2006.285.09:09:35.45#ibcon#end of sib2, iclass 33, count 2 2006.285.09:09:35.45#ibcon#*mode == 0, iclass 33, count 2 2006.285.09:09:35.45#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.09:09:35.45#ibcon#[25=AT06-04\r\n] 2006.285.09:09:35.45#ibcon#*before write, iclass 33, count 2 2006.285.09:09:35.45#ibcon#enter sib2, iclass 33, count 2 2006.285.09:09:35.45#ibcon#flushed, iclass 33, count 2 2006.285.09:09:35.45#ibcon#about to write, iclass 33, count 2 2006.285.09:09:35.45#ibcon#wrote, iclass 33, count 2 2006.285.09:09:35.45#ibcon#about to read 3, iclass 33, count 2 2006.285.09:09:35.48#abcon#<5=/03 0.7 1.6 20.81 861014.9\r\n> 2006.285.09:09:35.48#ibcon#read 3, iclass 33, count 2 2006.285.09:09:35.48#ibcon#about to read 4, iclass 33, count 2 2006.285.09:09:35.48#ibcon#read 4, iclass 33, count 2 2006.285.09:09:35.48#ibcon#about to read 5, iclass 33, count 2 2006.285.09:09:35.48#ibcon#read 5, iclass 33, count 2 2006.285.09:09:35.48#ibcon#about to read 6, iclass 33, count 2 2006.285.09:09:35.48#ibcon#read 6, iclass 33, count 2 2006.285.09:09:35.48#ibcon#end of sib2, iclass 33, count 2 2006.285.09:09:35.48#ibcon#*after write, iclass 33, count 2 2006.285.09:09:35.48#ibcon#*before return 0, iclass 33, count 2 2006.285.09:09:35.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:09:35.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:09:35.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.09:09:35.48#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:35.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:09:35.50#abcon#{5=INTERFACE CLEAR} 2006.285.09:09:35.56#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:09:35.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:09:35.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:09:35.60#ibcon#enter wrdev, iclass 33, count 0 2006.285.09:09:35.60#ibcon#first serial, iclass 33, count 0 2006.285.09:09:35.60#ibcon#enter sib2, iclass 33, count 0 2006.285.09:09:35.60#ibcon#flushed, iclass 33, count 0 2006.285.09:09:35.60#ibcon#about to write, iclass 33, count 0 2006.285.09:09:35.60#ibcon#wrote, iclass 33, count 0 2006.285.09:09:35.60#ibcon#about to read 3, iclass 33, count 0 2006.285.09:09:35.62#ibcon#read 3, iclass 33, count 0 2006.285.09:09:35.62#ibcon#about to read 4, iclass 33, count 0 2006.285.09:09:35.62#ibcon#read 4, iclass 33, count 0 2006.285.09:09:35.62#ibcon#about to read 5, iclass 33, count 0 2006.285.09:09:35.62#ibcon#read 5, iclass 33, count 0 2006.285.09:09:35.62#ibcon#about to read 6, iclass 33, count 0 2006.285.09:09:35.62#ibcon#read 6, iclass 33, count 0 2006.285.09:09:35.62#ibcon#end of sib2, iclass 33, count 0 2006.285.09:09:35.62#ibcon#*mode == 0, iclass 33, count 0 2006.285.09:09:35.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.09:09:35.62#ibcon#[25=USB\r\n] 2006.285.09:09:35.62#ibcon#*before write, iclass 33, count 0 2006.285.09:09:35.62#ibcon#enter sib2, iclass 33, count 0 2006.285.09:09:35.62#ibcon#flushed, iclass 33, count 0 2006.285.09:09:35.62#ibcon#about to write, iclass 33, count 0 2006.285.09:09:35.62#ibcon#wrote, iclass 33, count 0 2006.285.09:09:35.62#ibcon#about to read 3, iclass 33, count 0 2006.285.09:09:35.65#ibcon#read 3, iclass 33, count 0 2006.285.09:09:35.65#ibcon#about to read 4, iclass 33, count 0 2006.285.09:09:35.65#ibcon#read 4, iclass 33, count 0 2006.285.09:09:35.65#ibcon#about to read 5, iclass 33, count 0 2006.285.09:09:35.65#ibcon#read 5, iclass 33, count 0 2006.285.09:09:35.65#ibcon#about to read 6, iclass 33, count 0 2006.285.09:09:35.65#ibcon#read 6, iclass 33, count 0 2006.285.09:09:35.65#ibcon#end of sib2, iclass 33, count 0 2006.285.09:09:35.65#ibcon#*after write, iclass 33, count 0 2006.285.09:09:35.65#ibcon#*before return 0, iclass 33, count 0 2006.285.09:09:35.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:09:35.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:09:35.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.09:09:35.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.09:09:35.65$vck44/valo=7,864.99 2006.285.09:09:35.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.09:09:35.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.09:09:35.65#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:35.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:09:35.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:09:35.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:09:35.65#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:09:35.65#ibcon#first serial, iclass 38, count 0 2006.285.09:09:35.65#ibcon#enter sib2, iclass 38, count 0 2006.285.09:09:35.65#ibcon#flushed, iclass 38, count 0 2006.285.09:09:35.65#ibcon#about to write, iclass 38, count 0 2006.285.09:09:35.65#ibcon#wrote, iclass 38, count 0 2006.285.09:09:35.65#ibcon#about to read 3, iclass 38, count 0 2006.285.09:09:35.67#ibcon#read 3, iclass 38, count 0 2006.285.09:09:35.67#ibcon#about to read 4, iclass 38, count 0 2006.285.09:09:35.67#ibcon#read 4, iclass 38, count 0 2006.285.09:09:35.67#ibcon#about to read 5, iclass 38, count 0 2006.285.09:09:35.67#ibcon#read 5, iclass 38, count 0 2006.285.09:09:35.67#ibcon#about to read 6, iclass 38, count 0 2006.285.09:09:35.67#ibcon#read 6, iclass 38, count 0 2006.285.09:09:35.67#ibcon#end of sib2, iclass 38, count 0 2006.285.09:09:35.67#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:09:35.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:09:35.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:09:35.67#ibcon#*before write, iclass 38, count 0 2006.285.09:09:35.67#ibcon#enter sib2, iclass 38, count 0 2006.285.09:09:35.67#ibcon#flushed, iclass 38, count 0 2006.285.09:09:35.67#ibcon#about to write, iclass 38, count 0 2006.285.09:09:35.67#ibcon#wrote, iclass 38, count 0 2006.285.09:09:35.67#ibcon#about to read 3, iclass 38, count 0 2006.285.09:09:35.71#ibcon#read 3, iclass 38, count 0 2006.285.09:09:35.71#ibcon#about to read 4, iclass 38, count 0 2006.285.09:09:35.71#ibcon#read 4, iclass 38, count 0 2006.285.09:09:35.71#ibcon#about to read 5, iclass 38, count 0 2006.285.09:09:35.71#ibcon#read 5, iclass 38, count 0 2006.285.09:09:35.71#ibcon#about to read 6, iclass 38, count 0 2006.285.09:09:35.71#ibcon#read 6, iclass 38, count 0 2006.285.09:09:35.71#ibcon#end of sib2, iclass 38, count 0 2006.285.09:09:35.71#ibcon#*after write, iclass 38, count 0 2006.285.09:09:35.71#ibcon#*before return 0, iclass 38, count 0 2006.285.09:09:35.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:09:35.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:09:35.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:09:35.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:09:35.71$vck44/va=7,4 2006.285.09:09:35.71#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.09:09:35.71#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.09:09:35.71#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:35.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:09:35.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:09:35.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:09:35.77#ibcon#enter wrdev, iclass 40, count 2 2006.285.09:09:35.77#ibcon#first serial, iclass 40, count 2 2006.285.09:09:35.77#ibcon#enter sib2, iclass 40, count 2 2006.285.09:09:35.77#ibcon#flushed, iclass 40, count 2 2006.285.09:09:35.77#ibcon#about to write, iclass 40, count 2 2006.285.09:09:35.77#ibcon#wrote, iclass 40, count 2 2006.285.09:09:35.77#ibcon#about to read 3, iclass 40, count 2 2006.285.09:09:35.79#ibcon#read 3, iclass 40, count 2 2006.285.09:09:35.79#ibcon#about to read 4, iclass 40, count 2 2006.285.09:09:35.79#ibcon#read 4, iclass 40, count 2 2006.285.09:09:35.79#ibcon#about to read 5, iclass 40, count 2 2006.285.09:09:35.79#ibcon#read 5, iclass 40, count 2 2006.285.09:09:35.79#ibcon#about to read 6, iclass 40, count 2 2006.285.09:09:35.79#ibcon#read 6, iclass 40, count 2 2006.285.09:09:35.79#ibcon#end of sib2, iclass 40, count 2 2006.285.09:09:35.79#ibcon#*mode == 0, iclass 40, count 2 2006.285.09:09:35.79#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.09:09:35.79#ibcon#[25=AT07-04\r\n] 2006.285.09:09:35.79#ibcon#*before write, iclass 40, count 2 2006.285.09:09:35.79#ibcon#enter sib2, iclass 40, count 2 2006.285.09:09:35.79#ibcon#flushed, iclass 40, count 2 2006.285.09:09:35.79#ibcon#about to write, iclass 40, count 2 2006.285.09:09:35.79#ibcon#wrote, iclass 40, count 2 2006.285.09:09:35.79#ibcon#about to read 3, iclass 40, count 2 2006.285.09:09:35.82#ibcon#read 3, iclass 40, count 2 2006.285.09:09:35.82#ibcon#about to read 4, iclass 40, count 2 2006.285.09:09:35.82#ibcon#read 4, iclass 40, count 2 2006.285.09:09:35.82#ibcon#about to read 5, iclass 40, count 2 2006.285.09:09:35.82#ibcon#read 5, iclass 40, count 2 2006.285.09:09:35.82#ibcon#about to read 6, iclass 40, count 2 2006.285.09:09:35.82#ibcon#read 6, iclass 40, count 2 2006.285.09:09:35.82#ibcon#end of sib2, iclass 40, count 2 2006.285.09:09:35.82#ibcon#*after write, iclass 40, count 2 2006.285.09:09:35.82#ibcon#*before return 0, iclass 40, count 2 2006.285.09:09:35.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:09:35.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:09:35.82#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.09:09:35.82#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:35.82#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:09:35.94#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:09:35.94#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:09:35.94#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:09:35.94#ibcon#first serial, iclass 40, count 0 2006.285.09:09:35.94#ibcon#enter sib2, iclass 40, count 0 2006.285.09:09:35.94#ibcon#flushed, iclass 40, count 0 2006.285.09:09:35.94#ibcon#about to write, iclass 40, count 0 2006.285.09:09:35.94#ibcon#wrote, iclass 40, count 0 2006.285.09:09:35.94#ibcon#about to read 3, iclass 40, count 0 2006.285.09:09:35.96#ibcon#read 3, iclass 40, count 0 2006.285.09:09:35.96#ibcon#about to read 4, iclass 40, count 0 2006.285.09:09:35.96#ibcon#read 4, iclass 40, count 0 2006.285.09:09:35.96#ibcon#about to read 5, iclass 40, count 0 2006.285.09:09:35.96#ibcon#read 5, iclass 40, count 0 2006.285.09:09:35.96#ibcon#about to read 6, iclass 40, count 0 2006.285.09:09:35.96#ibcon#read 6, iclass 40, count 0 2006.285.09:09:35.96#ibcon#end of sib2, iclass 40, count 0 2006.285.09:09:35.96#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:09:35.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:09:35.96#ibcon#[25=USB\r\n] 2006.285.09:09:35.96#ibcon#*before write, iclass 40, count 0 2006.285.09:09:35.96#ibcon#enter sib2, iclass 40, count 0 2006.285.09:09:35.96#ibcon#flushed, iclass 40, count 0 2006.285.09:09:35.96#ibcon#about to write, iclass 40, count 0 2006.285.09:09:35.96#ibcon#wrote, iclass 40, count 0 2006.285.09:09:35.96#ibcon#about to read 3, iclass 40, count 0 2006.285.09:09:35.99#ibcon#read 3, iclass 40, count 0 2006.285.09:09:35.99#ibcon#about to read 4, iclass 40, count 0 2006.285.09:09:35.99#ibcon#read 4, iclass 40, count 0 2006.285.09:09:35.99#ibcon#about to read 5, iclass 40, count 0 2006.285.09:09:35.99#ibcon#read 5, iclass 40, count 0 2006.285.09:09:35.99#ibcon#about to read 6, iclass 40, count 0 2006.285.09:09:35.99#ibcon#read 6, iclass 40, count 0 2006.285.09:09:35.99#ibcon#end of sib2, iclass 40, count 0 2006.285.09:09:35.99#ibcon#*after write, iclass 40, count 0 2006.285.09:09:35.99#ibcon#*before return 0, iclass 40, count 0 2006.285.09:09:35.99#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:09:35.99#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:09:35.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:09:35.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:09:35.99$vck44/valo=8,884.99 2006.285.09:09:35.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.09:09:35.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.09:09:35.99#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:35.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:09:35.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:09:35.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:09:35.99#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:09:35.99#ibcon#first serial, iclass 4, count 0 2006.285.09:09:35.99#ibcon#enter sib2, iclass 4, count 0 2006.285.09:09:35.99#ibcon#flushed, iclass 4, count 0 2006.285.09:09:35.99#ibcon#about to write, iclass 4, count 0 2006.285.09:09:35.99#ibcon#wrote, iclass 4, count 0 2006.285.09:09:35.99#ibcon#about to read 3, iclass 4, count 0 2006.285.09:09:36.01#ibcon#read 3, iclass 4, count 0 2006.285.09:09:36.01#ibcon#about to read 4, iclass 4, count 0 2006.285.09:09:36.01#ibcon#read 4, iclass 4, count 0 2006.285.09:09:36.01#ibcon#about to read 5, iclass 4, count 0 2006.285.09:09:36.01#ibcon#read 5, iclass 4, count 0 2006.285.09:09:36.01#ibcon#about to read 6, iclass 4, count 0 2006.285.09:09:36.01#ibcon#read 6, iclass 4, count 0 2006.285.09:09:36.01#ibcon#end of sib2, iclass 4, count 0 2006.285.09:09:36.01#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:09:36.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:09:36.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:09:36.01#ibcon#*before write, iclass 4, count 0 2006.285.09:09:36.01#ibcon#enter sib2, iclass 4, count 0 2006.285.09:09:36.01#ibcon#flushed, iclass 4, count 0 2006.285.09:09:36.01#ibcon#about to write, iclass 4, count 0 2006.285.09:09:36.01#ibcon#wrote, iclass 4, count 0 2006.285.09:09:36.01#ibcon#about to read 3, iclass 4, count 0 2006.285.09:09:36.05#ibcon#read 3, iclass 4, count 0 2006.285.09:09:36.05#ibcon#about to read 4, iclass 4, count 0 2006.285.09:09:36.05#ibcon#read 4, iclass 4, count 0 2006.285.09:09:36.05#ibcon#about to read 5, iclass 4, count 0 2006.285.09:09:36.05#ibcon#read 5, iclass 4, count 0 2006.285.09:09:36.05#ibcon#about to read 6, iclass 4, count 0 2006.285.09:09:36.05#ibcon#read 6, iclass 4, count 0 2006.285.09:09:36.05#ibcon#end of sib2, iclass 4, count 0 2006.285.09:09:36.05#ibcon#*after write, iclass 4, count 0 2006.285.09:09:36.05#ibcon#*before return 0, iclass 4, count 0 2006.285.09:09:36.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:09:36.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:09:36.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:09:36.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:09:36.05$vck44/va=8,3 2006.285.09:09:36.05#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.09:09:36.05#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.09:09:36.05#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:36.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:09:36.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:09:36.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:09:36.11#ibcon#enter wrdev, iclass 6, count 2 2006.285.09:09:36.11#ibcon#first serial, iclass 6, count 2 2006.285.09:09:36.11#ibcon#enter sib2, iclass 6, count 2 2006.285.09:09:36.11#ibcon#flushed, iclass 6, count 2 2006.285.09:09:36.11#ibcon#about to write, iclass 6, count 2 2006.285.09:09:36.11#ibcon#wrote, iclass 6, count 2 2006.285.09:09:36.11#ibcon#about to read 3, iclass 6, count 2 2006.285.09:09:36.13#ibcon#read 3, iclass 6, count 2 2006.285.09:09:36.13#ibcon#about to read 4, iclass 6, count 2 2006.285.09:09:36.13#ibcon#read 4, iclass 6, count 2 2006.285.09:09:36.13#ibcon#about to read 5, iclass 6, count 2 2006.285.09:09:36.13#ibcon#read 5, iclass 6, count 2 2006.285.09:09:36.13#ibcon#about to read 6, iclass 6, count 2 2006.285.09:09:36.13#ibcon#read 6, iclass 6, count 2 2006.285.09:09:36.13#ibcon#end of sib2, iclass 6, count 2 2006.285.09:09:36.13#ibcon#*mode == 0, iclass 6, count 2 2006.285.09:09:36.13#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.09:09:36.13#ibcon#[25=AT08-03\r\n] 2006.285.09:09:36.13#ibcon#*before write, iclass 6, count 2 2006.285.09:09:36.13#ibcon#enter sib2, iclass 6, count 2 2006.285.09:09:36.13#ibcon#flushed, iclass 6, count 2 2006.285.09:09:36.13#ibcon#about to write, iclass 6, count 2 2006.285.09:09:36.13#ibcon#wrote, iclass 6, count 2 2006.285.09:09:36.13#ibcon#about to read 3, iclass 6, count 2 2006.285.09:09:36.16#ibcon#read 3, iclass 6, count 2 2006.285.09:09:36.16#ibcon#about to read 4, iclass 6, count 2 2006.285.09:09:36.16#ibcon#read 4, iclass 6, count 2 2006.285.09:09:36.16#ibcon#about to read 5, iclass 6, count 2 2006.285.09:09:36.16#ibcon#read 5, iclass 6, count 2 2006.285.09:09:36.16#ibcon#about to read 6, iclass 6, count 2 2006.285.09:09:36.16#ibcon#read 6, iclass 6, count 2 2006.285.09:09:36.16#ibcon#end of sib2, iclass 6, count 2 2006.285.09:09:36.16#ibcon#*after write, iclass 6, count 2 2006.285.09:09:36.16#ibcon#*before return 0, iclass 6, count 2 2006.285.09:09:36.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:09:36.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:09:36.16#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.09:09:36.16#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:36.16#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:09:36.28#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:09:36.28#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:09:36.28#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:09:36.28#ibcon#first serial, iclass 6, count 0 2006.285.09:09:36.28#ibcon#enter sib2, iclass 6, count 0 2006.285.09:09:36.28#ibcon#flushed, iclass 6, count 0 2006.285.09:09:36.28#ibcon#about to write, iclass 6, count 0 2006.285.09:09:36.28#ibcon#wrote, iclass 6, count 0 2006.285.09:09:36.28#ibcon#about to read 3, iclass 6, count 0 2006.285.09:09:36.30#ibcon#read 3, iclass 6, count 0 2006.285.09:09:36.30#ibcon#about to read 4, iclass 6, count 0 2006.285.09:09:36.30#ibcon#read 4, iclass 6, count 0 2006.285.09:09:36.30#ibcon#about to read 5, iclass 6, count 0 2006.285.09:09:36.30#ibcon#read 5, iclass 6, count 0 2006.285.09:09:36.30#ibcon#about to read 6, iclass 6, count 0 2006.285.09:09:36.30#ibcon#read 6, iclass 6, count 0 2006.285.09:09:36.30#ibcon#end of sib2, iclass 6, count 0 2006.285.09:09:36.30#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:09:36.30#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:09:36.30#ibcon#[25=USB\r\n] 2006.285.09:09:36.30#ibcon#*before write, iclass 6, count 0 2006.285.09:09:36.30#ibcon#enter sib2, iclass 6, count 0 2006.285.09:09:36.30#ibcon#flushed, iclass 6, count 0 2006.285.09:09:36.30#ibcon#about to write, iclass 6, count 0 2006.285.09:09:36.30#ibcon#wrote, iclass 6, count 0 2006.285.09:09:36.30#ibcon#about to read 3, iclass 6, count 0 2006.285.09:09:36.33#ibcon#read 3, iclass 6, count 0 2006.285.09:09:36.33#ibcon#about to read 4, iclass 6, count 0 2006.285.09:09:36.33#ibcon#read 4, iclass 6, count 0 2006.285.09:09:36.33#ibcon#about to read 5, iclass 6, count 0 2006.285.09:09:36.33#ibcon#read 5, iclass 6, count 0 2006.285.09:09:36.33#ibcon#about to read 6, iclass 6, count 0 2006.285.09:09:36.33#ibcon#read 6, iclass 6, count 0 2006.285.09:09:36.33#ibcon#end of sib2, iclass 6, count 0 2006.285.09:09:36.33#ibcon#*after write, iclass 6, count 0 2006.285.09:09:36.33#ibcon#*before return 0, iclass 6, count 0 2006.285.09:09:36.33#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:09:36.33#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:09:36.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:09:36.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:09:36.33$vck44/vblo=1,629.99 2006.285.09:09:36.33#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.09:09:36.33#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.09:09:36.33#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:36.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:09:36.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:09:36.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:09:36.33#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:09:36.33#ibcon#first serial, iclass 10, count 0 2006.285.09:09:36.33#ibcon#enter sib2, iclass 10, count 0 2006.285.09:09:36.33#ibcon#flushed, iclass 10, count 0 2006.285.09:09:36.33#ibcon#about to write, iclass 10, count 0 2006.285.09:09:36.33#ibcon#wrote, iclass 10, count 0 2006.285.09:09:36.33#ibcon#about to read 3, iclass 10, count 0 2006.285.09:09:36.35#ibcon#read 3, iclass 10, count 0 2006.285.09:09:36.35#ibcon#about to read 4, iclass 10, count 0 2006.285.09:09:36.35#ibcon#read 4, iclass 10, count 0 2006.285.09:09:36.35#ibcon#about to read 5, iclass 10, count 0 2006.285.09:09:36.35#ibcon#read 5, iclass 10, count 0 2006.285.09:09:36.35#ibcon#about to read 6, iclass 10, count 0 2006.285.09:09:36.35#ibcon#read 6, iclass 10, count 0 2006.285.09:09:36.35#ibcon#end of sib2, iclass 10, count 0 2006.285.09:09:36.35#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:09:36.35#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:09:36.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:09:36.35#ibcon#*before write, iclass 10, count 0 2006.285.09:09:36.35#ibcon#enter sib2, iclass 10, count 0 2006.285.09:09:36.35#ibcon#flushed, iclass 10, count 0 2006.285.09:09:36.35#ibcon#about to write, iclass 10, count 0 2006.285.09:09:36.35#ibcon#wrote, iclass 10, count 0 2006.285.09:09:36.35#ibcon#about to read 3, iclass 10, count 0 2006.285.09:09:36.39#ibcon#read 3, iclass 10, count 0 2006.285.09:09:36.39#ibcon#about to read 4, iclass 10, count 0 2006.285.09:09:36.39#ibcon#read 4, iclass 10, count 0 2006.285.09:09:36.39#ibcon#about to read 5, iclass 10, count 0 2006.285.09:09:36.39#ibcon#read 5, iclass 10, count 0 2006.285.09:09:36.39#ibcon#about to read 6, iclass 10, count 0 2006.285.09:09:36.39#ibcon#read 6, iclass 10, count 0 2006.285.09:09:36.39#ibcon#end of sib2, iclass 10, count 0 2006.285.09:09:36.39#ibcon#*after write, iclass 10, count 0 2006.285.09:09:36.39#ibcon#*before return 0, iclass 10, count 0 2006.285.09:09:36.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:09:36.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:09:36.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:09:36.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:09:36.39$vck44/vb=1,4 2006.285.09:09:36.39#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.09:09:36.39#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.09:09:36.39#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:36.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:09:36.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:09:36.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:09:36.39#ibcon#enter wrdev, iclass 12, count 2 2006.285.09:09:36.39#ibcon#first serial, iclass 12, count 2 2006.285.09:09:36.39#ibcon#enter sib2, iclass 12, count 2 2006.285.09:09:36.39#ibcon#flushed, iclass 12, count 2 2006.285.09:09:36.39#ibcon#about to write, iclass 12, count 2 2006.285.09:09:36.39#ibcon#wrote, iclass 12, count 2 2006.285.09:09:36.39#ibcon#about to read 3, iclass 12, count 2 2006.285.09:09:36.41#ibcon#read 3, iclass 12, count 2 2006.285.09:09:36.41#ibcon#about to read 4, iclass 12, count 2 2006.285.09:09:36.41#ibcon#read 4, iclass 12, count 2 2006.285.09:09:36.41#ibcon#about to read 5, iclass 12, count 2 2006.285.09:09:36.41#ibcon#read 5, iclass 12, count 2 2006.285.09:09:36.41#ibcon#about to read 6, iclass 12, count 2 2006.285.09:09:36.41#ibcon#read 6, iclass 12, count 2 2006.285.09:09:36.41#ibcon#end of sib2, iclass 12, count 2 2006.285.09:09:36.41#ibcon#*mode == 0, iclass 12, count 2 2006.285.09:09:36.41#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.09:09:36.41#ibcon#[27=AT01-04\r\n] 2006.285.09:09:36.41#ibcon#*before write, iclass 12, count 2 2006.285.09:09:36.41#ibcon#enter sib2, iclass 12, count 2 2006.285.09:09:36.41#ibcon#flushed, iclass 12, count 2 2006.285.09:09:36.41#ibcon#about to write, iclass 12, count 2 2006.285.09:09:36.41#ibcon#wrote, iclass 12, count 2 2006.285.09:09:36.41#ibcon#about to read 3, iclass 12, count 2 2006.285.09:09:36.44#ibcon#read 3, iclass 12, count 2 2006.285.09:09:36.44#ibcon#about to read 4, iclass 12, count 2 2006.285.09:09:36.44#ibcon#read 4, iclass 12, count 2 2006.285.09:09:36.44#ibcon#about to read 5, iclass 12, count 2 2006.285.09:09:36.44#ibcon#read 5, iclass 12, count 2 2006.285.09:09:36.44#ibcon#about to read 6, iclass 12, count 2 2006.285.09:09:36.44#ibcon#read 6, iclass 12, count 2 2006.285.09:09:36.44#ibcon#end of sib2, iclass 12, count 2 2006.285.09:09:36.44#ibcon#*after write, iclass 12, count 2 2006.285.09:09:36.44#ibcon#*before return 0, iclass 12, count 2 2006.285.09:09:36.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:09:36.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:09:36.44#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.09:09:36.44#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:36.44#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:09:36.56#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:09:36.56#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:09:36.56#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:09:36.56#ibcon#first serial, iclass 12, count 0 2006.285.09:09:36.56#ibcon#enter sib2, iclass 12, count 0 2006.285.09:09:36.56#ibcon#flushed, iclass 12, count 0 2006.285.09:09:36.56#ibcon#about to write, iclass 12, count 0 2006.285.09:09:36.56#ibcon#wrote, iclass 12, count 0 2006.285.09:09:36.56#ibcon#about to read 3, iclass 12, count 0 2006.285.09:09:36.58#ibcon#read 3, iclass 12, count 0 2006.285.09:09:36.58#ibcon#about to read 4, iclass 12, count 0 2006.285.09:09:36.58#ibcon#read 4, iclass 12, count 0 2006.285.09:09:36.58#ibcon#about to read 5, iclass 12, count 0 2006.285.09:09:36.58#ibcon#read 5, iclass 12, count 0 2006.285.09:09:36.58#ibcon#about to read 6, iclass 12, count 0 2006.285.09:09:36.58#ibcon#read 6, iclass 12, count 0 2006.285.09:09:36.58#ibcon#end of sib2, iclass 12, count 0 2006.285.09:09:36.58#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:09:36.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:09:36.58#ibcon#[27=USB\r\n] 2006.285.09:09:36.58#ibcon#*before write, iclass 12, count 0 2006.285.09:09:36.58#ibcon#enter sib2, iclass 12, count 0 2006.285.09:09:36.58#ibcon#flushed, iclass 12, count 0 2006.285.09:09:36.58#ibcon#about to write, iclass 12, count 0 2006.285.09:09:36.58#ibcon#wrote, iclass 12, count 0 2006.285.09:09:36.58#ibcon#about to read 3, iclass 12, count 0 2006.285.09:09:36.61#ibcon#read 3, iclass 12, count 0 2006.285.09:09:36.61#ibcon#about to read 4, iclass 12, count 0 2006.285.09:09:36.61#ibcon#read 4, iclass 12, count 0 2006.285.09:09:36.61#ibcon#about to read 5, iclass 12, count 0 2006.285.09:09:36.61#ibcon#read 5, iclass 12, count 0 2006.285.09:09:36.61#ibcon#about to read 6, iclass 12, count 0 2006.285.09:09:36.61#ibcon#read 6, iclass 12, count 0 2006.285.09:09:36.61#ibcon#end of sib2, iclass 12, count 0 2006.285.09:09:36.61#ibcon#*after write, iclass 12, count 0 2006.285.09:09:36.61#ibcon#*before return 0, iclass 12, count 0 2006.285.09:09:36.61#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:09:36.61#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:09:36.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:09:36.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:09:36.61$vck44/vblo=2,634.99 2006.285.09:09:36.61#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.09:09:36.61#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.09:09:36.61#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:36.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:09:36.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:09:36.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:09:36.61#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:09:36.61#ibcon#first serial, iclass 14, count 0 2006.285.09:09:36.61#ibcon#enter sib2, iclass 14, count 0 2006.285.09:09:36.61#ibcon#flushed, iclass 14, count 0 2006.285.09:09:36.61#ibcon#about to write, iclass 14, count 0 2006.285.09:09:36.61#ibcon#wrote, iclass 14, count 0 2006.285.09:09:36.61#ibcon#about to read 3, iclass 14, count 0 2006.285.09:09:36.63#ibcon#read 3, iclass 14, count 0 2006.285.09:09:36.63#ibcon#about to read 4, iclass 14, count 0 2006.285.09:09:36.63#ibcon#read 4, iclass 14, count 0 2006.285.09:09:36.63#ibcon#about to read 5, iclass 14, count 0 2006.285.09:09:36.63#ibcon#read 5, iclass 14, count 0 2006.285.09:09:36.63#ibcon#about to read 6, iclass 14, count 0 2006.285.09:09:36.63#ibcon#read 6, iclass 14, count 0 2006.285.09:09:36.63#ibcon#end of sib2, iclass 14, count 0 2006.285.09:09:36.63#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:09:36.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:09:36.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:09:36.63#ibcon#*before write, iclass 14, count 0 2006.285.09:09:36.63#ibcon#enter sib2, iclass 14, count 0 2006.285.09:09:36.63#ibcon#flushed, iclass 14, count 0 2006.285.09:09:36.63#ibcon#about to write, iclass 14, count 0 2006.285.09:09:36.63#ibcon#wrote, iclass 14, count 0 2006.285.09:09:36.63#ibcon#about to read 3, iclass 14, count 0 2006.285.09:09:36.67#ibcon#read 3, iclass 14, count 0 2006.285.09:09:36.67#ibcon#about to read 4, iclass 14, count 0 2006.285.09:09:36.67#ibcon#read 4, iclass 14, count 0 2006.285.09:09:36.67#ibcon#about to read 5, iclass 14, count 0 2006.285.09:09:36.67#ibcon#read 5, iclass 14, count 0 2006.285.09:09:36.67#ibcon#about to read 6, iclass 14, count 0 2006.285.09:09:36.67#ibcon#read 6, iclass 14, count 0 2006.285.09:09:36.67#ibcon#end of sib2, iclass 14, count 0 2006.285.09:09:36.67#ibcon#*after write, iclass 14, count 0 2006.285.09:09:36.67#ibcon#*before return 0, iclass 14, count 0 2006.285.09:09:36.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:09:36.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:09:36.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:09:36.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:09:36.67$vck44/vb=2,5 2006.285.09:09:36.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.09:09:36.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.09:09:36.67#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:36.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:09:36.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:09:36.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:09:36.73#ibcon#enter wrdev, iclass 16, count 2 2006.285.09:09:36.73#ibcon#first serial, iclass 16, count 2 2006.285.09:09:36.73#ibcon#enter sib2, iclass 16, count 2 2006.285.09:09:36.73#ibcon#flushed, iclass 16, count 2 2006.285.09:09:36.73#ibcon#about to write, iclass 16, count 2 2006.285.09:09:36.73#ibcon#wrote, iclass 16, count 2 2006.285.09:09:36.73#ibcon#about to read 3, iclass 16, count 2 2006.285.09:09:36.75#ibcon#read 3, iclass 16, count 2 2006.285.09:09:36.75#ibcon#about to read 4, iclass 16, count 2 2006.285.09:09:36.75#ibcon#read 4, iclass 16, count 2 2006.285.09:09:36.75#ibcon#about to read 5, iclass 16, count 2 2006.285.09:09:36.75#ibcon#read 5, iclass 16, count 2 2006.285.09:09:36.75#ibcon#about to read 6, iclass 16, count 2 2006.285.09:09:36.75#ibcon#read 6, iclass 16, count 2 2006.285.09:09:36.75#ibcon#end of sib2, iclass 16, count 2 2006.285.09:09:36.75#ibcon#*mode == 0, iclass 16, count 2 2006.285.09:09:36.75#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.09:09:36.75#ibcon#[27=AT02-05\r\n] 2006.285.09:09:36.75#ibcon#*before write, iclass 16, count 2 2006.285.09:09:36.75#ibcon#enter sib2, iclass 16, count 2 2006.285.09:09:36.75#ibcon#flushed, iclass 16, count 2 2006.285.09:09:36.75#ibcon#about to write, iclass 16, count 2 2006.285.09:09:36.75#ibcon#wrote, iclass 16, count 2 2006.285.09:09:36.75#ibcon#about to read 3, iclass 16, count 2 2006.285.09:09:36.78#ibcon#read 3, iclass 16, count 2 2006.285.09:09:36.78#ibcon#about to read 4, iclass 16, count 2 2006.285.09:09:36.78#ibcon#read 4, iclass 16, count 2 2006.285.09:09:36.78#ibcon#about to read 5, iclass 16, count 2 2006.285.09:09:36.78#ibcon#read 5, iclass 16, count 2 2006.285.09:09:36.78#ibcon#about to read 6, iclass 16, count 2 2006.285.09:09:36.78#ibcon#read 6, iclass 16, count 2 2006.285.09:09:36.78#ibcon#end of sib2, iclass 16, count 2 2006.285.09:09:36.78#ibcon#*after write, iclass 16, count 2 2006.285.09:09:36.78#ibcon#*before return 0, iclass 16, count 2 2006.285.09:09:36.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:09:36.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:09:36.78#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.09:09:36.78#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:36.78#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:09:36.90#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:09:36.90#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:09:36.90#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:09:36.90#ibcon#first serial, iclass 16, count 0 2006.285.09:09:36.90#ibcon#enter sib2, iclass 16, count 0 2006.285.09:09:36.90#ibcon#flushed, iclass 16, count 0 2006.285.09:09:36.90#ibcon#about to write, iclass 16, count 0 2006.285.09:09:36.90#ibcon#wrote, iclass 16, count 0 2006.285.09:09:36.90#ibcon#about to read 3, iclass 16, count 0 2006.285.09:09:36.92#ibcon#read 3, iclass 16, count 0 2006.285.09:09:36.92#ibcon#about to read 4, iclass 16, count 0 2006.285.09:09:36.92#ibcon#read 4, iclass 16, count 0 2006.285.09:09:36.92#ibcon#about to read 5, iclass 16, count 0 2006.285.09:09:36.92#ibcon#read 5, iclass 16, count 0 2006.285.09:09:36.92#ibcon#about to read 6, iclass 16, count 0 2006.285.09:09:36.92#ibcon#read 6, iclass 16, count 0 2006.285.09:09:36.92#ibcon#end of sib2, iclass 16, count 0 2006.285.09:09:36.92#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:09:36.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:09:36.92#ibcon#[27=USB\r\n] 2006.285.09:09:36.92#ibcon#*before write, iclass 16, count 0 2006.285.09:09:36.92#ibcon#enter sib2, iclass 16, count 0 2006.285.09:09:36.92#ibcon#flushed, iclass 16, count 0 2006.285.09:09:36.92#ibcon#about to write, iclass 16, count 0 2006.285.09:09:36.92#ibcon#wrote, iclass 16, count 0 2006.285.09:09:36.92#ibcon#about to read 3, iclass 16, count 0 2006.285.09:09:36.95#ibcon#read 3, iclass 16, count 0 2006.285.09:09:36.95#ibcon#about to read 4, iclass 16, count 0 2006.285.09:09:36.95#ibcon#read 4, iclass 16, count 0 2006.285.09:09:36.95#ibcon#about to read 5, iclass 16, count 0 2006.285.09:09:36.95#ibcon#read 5, iclass 16, count 0 2006.285.09:09:36.95#ibcon#about to read 6, iclass 16, count 0 2006.285.09:09:36.95#ibcon#read 6, iclass 16, count 0 2006.285.09:09:36.95#ibcon#end of sib2, iclass 16, count 0 2006.285.09:09:36.95#ibcon#*after write, iclass 16, count 0 2006.285.09:09:36.95#ibcon#*before return 0, iclass 16, count 0 2006.285.09:09:36.95#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:09:36.95#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:09:36.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:09:36.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:09:36.95$vck44/vblo=3,649.99 2006.285.09:09:36.95#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.09:09:36.95#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.09:09:36.95#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:36.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:09:36.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:09:36.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:09:36.95#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:09:36.95#ibcon#first serial, iclass 18, count 0 2006.285.09:09:36.95#ibcon#enter sib2, iclass 18, count 0 2006.285.09:09:36.95#ibcon#flushed, iclass 18, count 0 2006.285.09:09:36.95#ibcon#about to write, iclass 18, count 0 2006.285.09:09:36.95#ibcon#wrote, iclass 18, count 0 2006.285.09:09:36.95#ibcon#about to read 3, iclass 18, count 0 2006.285.09:09:36.97#ibcon#read 3, iclass 18, count 0 2006.285.09:09:36.97#ibcon#about to read 4, iclass 18, count 0 2006.285.09:09:36.97#ibcon#read 4, iclass 18, count 0 2006.285.09:09:36.97#ibcon#about to read 5, iclass 18, count 0 2006.285.09:09:36.97#ibcon#read 5, iclass 18, count 0 2006.285.09:09:36.97#ibcon#about to read 6, iclass 18, count 0 2006.285.09:09:36.97#ibcon#read 6, iclass 18, count 0 2006.285.09:09:36.97#ibcon#end of sib2, iclass 18, count 0 2006.285.09:09:36.97#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:09:36.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:09:36.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:09:36.97#ibcon#*before write, iclass 18, count 0 2006.285.09:09:36.97#ibcon#enter sib2, iclass 18, count 0 2006.285.09:09:36.97#ibcon#flushed, iclass 18, count 0 2006.285.09:09:36.97#ibcon#about to write, iclass 18, count 0 2006.285.09:09:36.97#ibcon#wrote, iclass 18, count 0 2006.285.09:09:36.97#ibcon#about to read 3, iclass 18, count 0 2006.285.09:09:37.01#ibcon#read 3, iclass 18, count 0 2006.285.09:09:37.01#ibcon#about to read 4, iclass 18, count 0 2006.285.09:09:37.01#ibcon#read 4, iclass 18, count 0 2006.285.09:09:37.01#ibcon#about to read 5, iclass 18, count 0 2006.285.09:09:37.01#ibcon#read 5, iclass 18, count 0 2006.285.09:09:37.01#ibcon#about to read 6, iclass 18, count 0 2006.285.09:09:37.01#ibcon#read 6, iclass 18, count 0 2006.285.09:09:37.01#ibcon#end of sib2, iclass 18, count 0 2006.285.09:09:37.01#ibcon#*after write, iclass 18, count 0 2006.285.09:09:37.01#ibcon#*before return 0, iclass 18, count 0 2006.285.09:09:37.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:09:37.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:09:37.01#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:09:37.01#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:09:37.01$vck44/vb=3,4 2006.285.09:09:37.01#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.09:09:37.01#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.09:09:37.01#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:37.01#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:09:37.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:09:37.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:09:37.07#ibcon#enter wrdev, iclass 20, count 2 2006.285.09:09:37.07#ibcon#first serial, iclass 20, count 2 2006.285.09:09:37.07#ibcon#enter sib2, iclass 20, count 2 2006.285.09:09:37.07#ibcon#flushed, iclass 20, count 2 2006.285.09:09:37.07#ibcon#about to write, iclass 20, count 2 2006.285.09:09:37.07#ibcon#wrote, iclass 20, count 2 2006.285.09:09:37.07#ibcon#about to read 3, iclass 20, count 2 2006.285.09:09:37.09#ibcon#read 3, iclass 20, count 2 2006.285.09:09:37.09#ibcon#about to read 4, iclass 20, count 2 2006.285.09:09:37.09#ibcon#read 4, iclass 20, count 2 2006.285.09:09:37.09#ibcon#about to read 5, iclass 20, count 2 2006.285.09:09:37.09#ibcon#read 5, iclass 20, count 2 2006.285.09:09:37.09#ibcon#about to read 6, iclass 20, count 2 2006.285.09:09:37.09#ibcon#read 6, iclass 20, count 2 2006.285.09:09:37.09#ibcon#end of sib2, iclass 20, count 2 2006.285.09:09:37.09#ibcon#*mode == 0, iclass 20, count 2 2006.285.09:09:37.09#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.09:09:37.09#ibcon#[27=AT03-04\r\n] 2006.285.09:09:37.09#ibcon#*before write, iclass 20, count 2 2006.285.09:09:37.09#ibcon#enter sib2, iclass 20, count 2 2006.285.09:09:37.09#ibcon#flushed, iclass 20, count 2 2006.285.09:09:37.09#ibcon#about to write, iclass 20, count 2 2006.285.09:09:37.09#ibcon#wrote, iclass 20, count 2 2006.285.09:09:37.09#ibcon#about to read 3, iclass 20, count 2 2006.285.09:09:37.12#ibcon#read 3, iclass 20, count 2 2006.285.09:09:37.12#ibcon#about to read 4, iclass 20, count 2 2006.285.09:09:37.12#ibcon#read 4, iclass 20, count 2 2006.285.09:09:37.12#ibcon#about to read 5, iclass 20, count 2 2006.285.09:09:37.12#ibcon#read 5, iclass 20, count 2 2006.285.09:09:37.12#ibcon#about to read 6, iclass 20, count 2 2006.285.09:09:37.12#ibcon#read 6, iclass 20, count 2 2006.285.09:09:37.12#ibcon#end of sib2, iclass 20, count 2 2006.285.09:09:37.12#ibcon#*after write, iclass 20, count 2 2006.285.09:09:37.12#ibcon#*before return 0, iclass 20, count 2 2006.285.09:09:37.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:09:37.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:09:37.12#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.09:09:37.12#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:37.12#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:09:37.24#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:09:37.24#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:09:37.24#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:09:37.24#ibcon#first serial, iclass 20, count 0 2006.285.09:09:37.24#ibcon#enter sib2, iclass 20, count 0 2006.285.09:09:37.24#ibcon#flushed, iclass 20, count 0 2006.285.09:09:37.24#ibcon#about to write, iclass 20, count 0 2006.285.09:09:37.24#ibcon#wrote, iclass 20, count 0 2006.285.09:09:37.24#ibcon#about to read 3, iclass 20, count 0 2006.285.09:09:37.26#ibcon#read 3, iclass 20, count 0 2006.285.09:09:37.26#ibcon#about to read 4, iclass 20, count 0 2006.285.09:09:37.26#ibcon#read 4, iclass 20, count 0 2006.285.09:09:37.26#ibcon#about to read 5, iclass 20, count 0 2006.285.09:09:37.26#ibcon#read 5, iclass 20, count 0 2006.285.09:09:37.26#ibcon#about to read 6, iclass 20, count 0 2006.285.09:09:37.26#ibcon#read 6, iclass 20, count 0 2006.285.09:09:37.26#ibcon#end of sib2, iclass 20, count 0 2006.285.09:09:37.26#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:09:37.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:09:37.26#ibcon#[27=USB\r\n] 2006.285.09:09:37.26#ibcon#*before write, iclass 20, count 0 2006.285.09:09:37.26#ibcon#enter sib2, iclass 20, count 0 2006.285.09:09:37.26#ibcon#flushed, iclass 20, count 0 2006.285.09:09:37.26#ibcon#about to write, iclass 20, count 0 2006.285.09:09:37.26#ibcon#wrote, iclass 20, count 0 2006.285.09:09:37.26#ibcon#about to read 3, iclass 20, count 0 2006.285.09:09:37.29#ibcon#read 3, iclass 20, count 0 2006.285.09:09:37.29#ibcon#about to read 4, iclass 20, count 0 2006.285.09:09:37.29#ibcon#read 4, iclass 20, count 0 2006.285.09:09:37.29#ibcon#about to read 5, iclass 20, count 0 2006.285.09:09:37.29#ibcon#read 5, iclass 20, count 0 2006.285.09:09:37.29#ibcon#about to read 6, iclass 20, count 0 2006.285.09:09:37.29#ibcon#read 6, iclass 20, count 0 2006.285.09:09:37.29#ibcon#end of sib2, iclass 20, count 0 2006.285.09:09:37.29#ibcon#*after write, iclass 20, count 0 2006.285.09:09:37.29#ibcon#*before return 0, iclass 20, count 0 2006.285.09:09:37.29#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:09:37.29#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:09:37.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:09:37.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:09:37.29$vck44/vblo=4,679.99 2006.285.09:09:37.29#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.09:09:37.29#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.09:09:37.29#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:37.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:09:37.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:09:37.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:09:37.29#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:09:37.29#ibcon#first serial, iclass 22, count 0 2006.285.09:09:37.29#ibcon#enter sib2, iclass 22, count 0 2006.285.09:09:37.29#ibcon#flushed, iclass 22, count 0 2006.285.09:09:37.29#ibcon#about to write, iclass 22, count 0 2006.285.09:09:37.29#ibcon#wrote, iclass 22, count 0 2006.285.09:09:37.29#ibcon#about to read 3, iclass 22, count 0 2006.285.09:09:37.31#ibcon#read 3, iclass 22, count 0 2006.285.09:09:37.31#ibcon#about to read 4, iclass 22, count 0 2006.285.09:09:37.31#ibcon#read 4, iclass 22, count 0 2006.285.09:09:37.31#ibcon#about to read 5, iclass 22, count 0 2006.285.09:09:37.31#ibcon#read 5, iclass 22, count 0 2006.285.09:09:37.31#ibcon#about to read 6, iclass 22, count 0 2006.285.09:09:37.31#ibcon#read 6, iclass 22, count 0 2006.285.09:09:37.31#ibcon#end of sib2, iclass 22, count 0 2006.285.09:09:37.31#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:09:37.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:09:37.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:09:37.31#ibcon#*before write, iclass 22, count 0 2006.285.09:09:37.31#ibcon#enter sib2, iclass 22, count 0 2006.285.09:09:37.31#ibcon#flushed, iclass 22, count 0 2006.285.09:09:37.31#ibcon#about to write, iclass 22, count 0 2006.285.09:09:37.31#ibcon#wrote, iclass 22, count 0 2006.285.09:09:37.31#ibcon#about to read 3, iclass 22, count 0 2006.285.09:09:37.35#ibcon#read 3, iclass 22, count 0 2006.285.09:09:37.35#ibcon#about to read 4, iclass 22, count 0 2006.285.09:09:37.35#ibcon#read 4, iclass 22, count 0 2006.285.09:09:37.35#ibcon#about to read 5, iclass 22, count 0 2006.285.09:09:37.35#ibcon#read 5, iclass 22, count 0 2006.285.09:09:37.35#ibcon#about to read 6, iclass 22, count 0 2006.285.09:09:37.35#ibcon#read 6, iclass 22, count 0 2006.285.09:09:37.35#ibcon#end of sib2, iclass 22, count 0 2006.285.09:09:37.35#ibcon#*after write, iclass 22, count 0 2006.285.09:09:37.35#ibcon#*before return 0, iclass 22, count 0 2006.285.09:09:37.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:09:37.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:09:37.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:09:37.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:09:37.35$vck44/vb=4,5 2006.285.09:09:37.35#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.09:09:37.35#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.09:09:37.35#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:37.35#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:09:37.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:09:37.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:09:37.41#ibcon#enter wrdev, iclass 24, count 2 2006.285.09:09:37.41#ibcon#first serial, iclass 24, count 2 2006.285.09:09:37.41#ibcon#enter sib2, iclass 24, count 2 2006.285.09:09:37.41#ibcon#flushed, iclass 24, count 2 2006.285.09:09:37.41#ibcon#about to write, iclass 24, count 2 2006.285.09:09:37.41#ibcon#wrote, iclass 24, count 2 2006.285.09:09:37.41#ibcon#about to read 3, iclass 24, count 2 2006.285.09:09:37.43#ibcon#read 3, iclass 24, count 2 2006.285.09:09:37.43#ibcon#about to read 4, iclass 24, count 2 2006.285.09:09:37.43#ibcon#read 4, iclass 24, count 2 2006.285.09:09:37.43#ibcon#about to read 5, iclass 24, count 2 2006.285.09:09:37.43#ibcon#read 5, iclass 24, count 2 2006.285.09:09:37.43#ibcon#about to read 6, iclass 24, count 2 2006.285.09:09:37.43#ibcon#read 6, iclass 24, count 2 2006.285.09:09:37.43#ibcon#end of sib2, iclass 24, count 2 2006.285.09:09:37.43#ibcon#*mode == 0, iclass 24, count 2 2006.285.09:09:37.43#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.09:09:37.43#ibcon#[27=AT04-05\r\n] 2006.285.09:09:37.43#ibcon#*before write, iclass 24, count 2 2006.285.09:09:37.43#ibcon#enter sib2, iclass 24, count 2 2006.285.09:09:37.43#ibcon#flushed, iclass 24, count 2 2006.285.09:09:37.43#ibcon#about to write, iclass 24, count 2 2006.285.09:09:37.43#ibcon#wrote, iclass 24, count 2 2006.285.09:09:37.43#ibcon#about to read 3, iclass 24, count 2 2006.285.09:09:37.46#ibcon#read 3, iclass 24, count 2 2006.285.09:09:37.46#ibcon#about to read 4, iclass 24, count 2 2006.285.09:09:37.46#ibcon#read 4, iclass 24, count 2 2006.285.09:09:37.46#ibcon#about to read 5, iclass 24, count 2 2006.285.09:09:37.46#ibcon#read 5, iclass 24, count 2 2006.285.09:09:37.46#ibcon#about to read 6, iclass 24, count 2 2006.285.09:09:37.46#ibcon#read 6, iclass 24, count 2 2006.285.09:09:37.46#ibcon#end of sib2, iclass 24, count 2 2006.285.09:09:37.46#ibcon#*after write, iclass 24, count 2 2006.285.09:09:37.46#ibcon#*before return 0, iclass 24, count 2 2006.285.09:09:37.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:09:37.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:09:37.46#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.09:09:37.46#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:37.46#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:09:37.58#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:09:37.58#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:09:37.58#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:09:37.58#ibcon#first serial, iclass 24, count 0 2006.285.09:09:37.58#ibcon#enter sib2, iclass 24, count 0 2006.285.09:09:37.58#ibcon#flushed, iclass 24, count 0 2006.285.09:09:37.58#ibcon#about to write, iclass 24, count 0 2006.285.09:09:37.58#ibcon#wrote, iclass 24, count 0 2006.285.09:09:37.58#ibcon#about to read 3, iclass 24, count 0 2006.285.09:09:37.60#ibcon#read 3, iclass 24, count 0 2006.285.09:09:37.60#ibcon#about to read 4, iclass 24, count 0 2006.285.09:09:37.60#ibcon#read 4, iclass 24, count 0 2006.285.09:09:37.60#ibcon#about to read 5, iclass 24, count 0 2006.285.09:09:37.60#ibcon#read 5, iclass 24, count 0 2006.285.09:09:37.60#ibcon#about to read 6, iclass 24, count 0 2006.285.09:09:37.60#ibcon#read 6, iclass 24, count 0 2006.285.09:09:37.60#ibcon#end of sib2, iclass 24, count 0 2006.285.09:09:37.60#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:09:37.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:09:37.60#ibcon#[27=USB\r\n] 2006.285.09:09:37.60#ibcon#*before write, iclass 24, count 0 2006.285.09:09:37.60#ibcon#enter sib2, iclass 24, count 0 2006.285.09:09:37.60#ibcon#flushed, iclass 24, count 0 2006.285.09:09:37.60#ibcon#about to write, iclass 24, count 0 2006.285.09:09:37.60#ibcon#wrote, iclass 24, count 0 2006.285.09:09:37.60#ibcon#about to read 3, iclass 24, count 0 2006.285.09:09:37.63#ibcon#read 3, iclass 24, count 0 2006.285.09:09:37.63#ibcon#about to read 4, iclass 24, count 0 2006.285.09:09:37.63#ibcon#read 4, iclass 24, count 0 2006.285.09:09:37.63#ibcon#about to read 5, iclass 24, count 0 2006.285.09:09:37.63#ibcon#read 5, iclass 24, count 0 2006.285.09:09:37.63#ibcon#about to read 6, iclass 24, count 0 2006.285.09:09:37.63#ibcon#read 6, iclass 24, count 0 2006.285.09:09:37.63#ibcon#end of sib2, iclass 24, count 0 2006.285.09:09:37.63#ibcon#*after write, iclass 24, count 0 2006.285.09:09:37.63#ibcon#*before return 0, iclass 24, count 0 2006.285.09:09:37.63#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:09:37.63#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:09:37.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:09:37.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:09:37.63$vck44/vblo=5,709.99 2006.285.09:09:37.63#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.09:09:37.63#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.09:09:37.63#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:37.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:09:37.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:09:37.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:09:37.63#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:09:37.63#ibcon#first serial, iclass 26, count 0 2006.285.09:09:37.63#ibcon#enter sib2, iclass 26, count 0 2006.285.09:09:37.63#ibcon#flushed, iclass 26, count 0 2006.285.09:09:37.63#ibcon#about to write, iclass 26, count 0 2006.285.09:09:37.63#ibcon#wrote, iclass 26, count 0 2006.285.09:09:37.63#ibcon#about to read 3, iclass 26, count 0 2006.285.09:09:37.65#ibcon#read 3, iclass 26, count 0 2006.285.09:09:37.65#ibcon#about to read 4, iclass 26, count 0 2006.285.09:09:37.65#ibcon#read 4, iclass 26, count 0 2006.285.09:09:37.65#ibcon#about to read 5, iclass 26, count 0 2006.285.09:09:37.65#ibcon#read 5, iclass 26, count 0 2006.285.09:09:37.65#ibcon#about to read 6, iclass 26, count 0 2006.285.09:09:37.65#ibcon#read 6, iclass 26, count 0 2006.285.09:09:37.65#ibcon#end of sib2, iclass 26, count 0 2006.285.09:09:37.65#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:09:37.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:09:37.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:09:37.65#ibcon#*before write, iclass 26, count 0 2006.285.09:09:37.65#ibcon#enter sib2, iclass 26, count 0 2006.285.09:09:37.65#ibcon#flushed, iclass 26, count 0 2006.285.09:09:37.65#ibcon#about to write, iclass 26, count 0 2006.285.09:09:37.65#ibcon#wrote, iclass 26, count 0 2006.285.09:09:37.65#ibcon#about to read 3, iclass 26, count 0 2006.285.09:09:37.69#ibcon#read 3, iclass 26, count 0 2006.285.09:09:37.69#ibcon#about to read 4, iclass 26, count 0 2006.285.09:09:37.69#ibcon#read 4, iclass 26, count 0 2006.285.09:09:37.69#ibcon#about to read 5, iclass 26, count 0 2006.285.09:09:37.69#ibcon#read 5, iclass 26, count 0 2006.285.09:09:37.69#ibcon#about to read 6, iclass 26, count 0 2006.285.09:09:37.69#ibcon#read 6, iclass 26, count 0 2006.285.09:09:37.69#ibcon#end of sib2, iclass 26, count 0 2006.285.09:09:37.69#ibcon#*after write, iclass 26, count 0 2006.285.09:09:37.69#ibcon#*before return 0, iclass 26, count 0 2006.285.09:09:37.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:09:37.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:09:37.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:09:37.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:09:37.69$vck44/vb=5,4 2006.285.09:09:37.69#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.09:09:37.69#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.09:09:37.69#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:37.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:09:37.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:09:37.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:09:37.75#ibcon#enter wrdev, iclass 28, count 2 2006.285.09:09:37.75#ibcon#first serial, iclass 28, count 2 2006.285.09:09:37.75#ibcon#enter sib2, iclass 28, count 2 2006.285.09:09:37.75#ibcon#flushed, iclass 28, count 2 2006.285.09:09:37.75#ibcon#about to write, iclass 28, count 2 2006.285.09:09:37.75#ibcon#wrote, iclass 28, count 2 2006.285.09:09:37.75#ibcon#about to read 3, iclass 28, count 2 2006.285.09:09:37.77#ibcon#read 3, iclass 28, count 2 2006.285.09:09:37.77#ibcon#about to read 4, iclass 28, count 2 2006.285.09:09:37.77#ibcon#read 4, iclass 28, count 2 2006.285.09:09:37.77#ibcon#about to read 5, iclass 28, count 2 2006.285.09:09:37.77#ibcon#read 5, iclass 28, count 2 2006.285.09:09:37.77#ibcon#about to read 6, iclass 28, count 2 2006.285.09:09:37.77#ibcon#read 6, iclass 28, count 2 2006.285.09:09:37.77#ibcon#end of sib2, iclass 28, count 2 2006.285.09:09:37.77#ibcon#*mode == 0, iclass 28, count 2 2006.285.09:09:37.77#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.09:09:37.77#ibcon#[27=AT05-04\r\n] 2006.285.09:09:37.77#ibcon#*before write, iclass 28, count 2 2006.285.09:09:37.77#ibcon#enter sib2, iclass 28, count 2 2006.285.09:09:37.77#ibcon#flushed, iclass 28, count 2 2006.285.09:09:37.77#ibcon#about to write, iclass 28, count 2 2006.285.09:09:37.77#ibcon#wrote, iclass 28, count 2 2006.285.09:09:37.77#ibcon#about to read 3, iclass 28, count 2 2006.285.09:09:37.80#ibcon#read 3, iclass 28, count 2 2006.285.09:09:37.80#ibcon#about to read 4, iclass 28, count 2 2006.285.09:09:37.80#ibcon#read 4, iclass 28, count 2 2006.285.09:09:37.80#ibcon#about to read 5, iclass 28, count 2 2006.285.09:09:37.80#ibcon#read 5, iclass 28, count 2 2006.285.09:09:37.80#ibcon#about to read 6, iclass 28, count 2 2006.285.09:09:37.80#ibcon#read 6, iclass 28, count 2 2006.285.09:09:37.80#ibcon#end of sib2, iclass 28, count 2 2006.285.09:09:37.80#ibcon#*after write, iclass 28, count 2 2006.285.09:09:37.80#ibcon#*before return 0, iclass 28, count 2 2006.285.09:09:37.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:09:37.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:09:37.80#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.09:09:37.80#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:37.80#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:09:37.92#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:09:37.92#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:09:37.92#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:09:37.92#ibcon#first serial, iclass 28, count 0 2006.285.09:09:37.92#ibcon#enter sib2, iclass 28, count 0 2006.285.09:09:37.92#ibcon#flushed, iclass 28, count 0 2006.285.09:09:37.92#ibcon#about to write, iclass 28, count 0 2006.285.09:09:37.92#ibcon#wrote, iclass 28, count 0 2006.285.09:09:37.92#ibcon#about to read 3, iclass 28, count 0 2006.285.09:09:37.94#ibcon#read 3, iclass 28, count 0 2006.285.09:09:37.94#ibcon#about to read 4, iclass 28, count 0 2006.285.09:09:37.94#ibcon#read 4, iclass 28, count 0 2006.285.09:09:37.94#ibcon#about to read 5, iclass 28, count 0 2006.285.09:09:37.94#ibcon#read 5, iclass 28, count 0 2006.285.09:09:37.94#ibcon#about to read 6, iclass 28, count 0 2006.285.09:09:37.94#ibcon#read 6, iclass 28, count 0 2006.285.09:09:37.94#ibcon#end of sib2, iclass 28, count 0 2006.285.09:09:37.94#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:09:37.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:09:37.94#ibcon#[27=USB\r\n] 2006.285.09:09:37.94#ibcon#*before write, iclass 28, count 0 2006.285.09:09:37.94#ibcon#enter sib2, iclass 28, count 0 2006.285.09:09:37.94#ibcon#flushed, iclass 28, count 0 2006.285.09:09:37.94#ibcon#about to write, iclass 28, count 0 2006.285.09:09:37.94#ibcon#wrote, iclass 28, count 0 2006.285.09:09:37.94#ibcon#about to read 3, iclass 28, count 0 2006.285.09:09:37.97#ibcon#read 3, iclass 28, count 0 2006.285.09:09:37.97#ibcon#about to read 4, iclass 28, count 0 2006.285.09:09:37.97#ibcon#read 4, iclass 28, count 0 2006.285.09:09:37.97#ibcon#about to read 5, iclass 28, count 0 2006.285.09:09:37.97#ibcon#read 5, iclass 28, count 0 2006.285.09:09:37.97#ibcon#about to read 6, iclass 28, count 0 2006.285.09:09:37.97#ibcon#read 6, iclass 28, count 0 2006.285.09:09:37.97#ibcon#end of sib2, iclass 28, count 0 2006.285.09:09:37.97#ibcon#*after write, iclass 28, count 0 2006.285.09:09:37.97#ibcon#*before return 0, iclass 28, count 0 2006.285.09:09:37.97#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:09:37.97#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:09:37.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:09:37.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:09:37.97$vck44/vblo=6,719.99 2006.285.09:09:37.97#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.09:09:37.97#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.09:09:37.97#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:37.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:09:37.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:09:37.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:09:37.97#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:09:37.97#ibcon#first serial, iclass 30, count 0 2006.285.09:09:37.97#ibcon#enter sib2, iclass 30, count 0 2006.285.09:09:37.97#ibcon#flushed, iclass 30, count 0 2006.285.09:09:37.97#ibcon#about to write, iclass 30, count 0 2006.285.09:09:37.97#ibcon#wrote, iclass 30, count 0 2006.285.09:09:37.97#ibcon#about to read 3, iclass 30, count 0 2006.285.09:09:37.99#ibcon#read 3, iclass 30, count 0 2006.285.09:09:37.99#ibcon#about to read 4, iclass 30, count 0 2006.285.09:09:37.99#ibcon#read 4, iclass 30, count 0 2006.285.09:09:37.99#ibcon#about to read 5, iclass 30, count 0 2006.285.09:09:37.99#ibcon#read 5, iclass 30, count 0 2006.285.09:09:37.99#ibcon#about to read 6, iclass 30, count 0 2006.285.09:09:37.99#ibcon#read 6, iclass 30, count 0 2006.285.09:09:37.99#ibcon#end of sib2, iclass 30, count 0 2006.285.09:09:37.99#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:09:37.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:09:37.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:09:37.99#ibcon#*before write, iclass 30, count 0 2006.285.09:09:37.99#ibcon#enter sib2, iclass 30, count 0 2006.285.09:09:37.99#ibcon#flushed, iclass 30, count 0 2006.285.09:09:37.99#ibcon#about to write, iclass 30, count 0 2006.285.09:09:37.99#ibcon#wrote, iclass 30, count 0 2006.285.09:09:37.99#ibcon#about to read 3, iclass 30, count 0 2006.285.09:09:38.03#ibcon#read 3, iclass 30, count 0 2006.285.09:09:38.03#ibcon#about to read 4, iclass 30, count 0 2006.285.09:09:38.03#ibcon#read 4, iclass 30, count 0 2006.285.09:09:38.03#ibcon#about to read 5, iclass 30, count 0 2006.285.09:09:38.03#ibcon#read 5, iclass 30, count 0 2006.285.09:09:38.03#ibcon#about to read 6, iclass 30, count 0 2006.285.09:09:38.03#ibcon#read 6, iclass 30, count 0 2006.285.09:09:38.03#ibcon#end of sib2, iclass 30, count 0 2006.285.09:09:38.03#ibcon#*after write, iclass 30, count 0 2006.285.09:09:38.03#ibcon#*before return 0, iclass 30, count 0 2006.285.09:09:38.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:09:38.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:09:38.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:09:38.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:09:38.03$vck44/vb=6,3 2006.285.09:09:38.03#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.09:09:38.03#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.09:09:38.03#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:38.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:09:38.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:09:38.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:09:38.09#ibcon#enter wrdev, iclass 32, count 2 2006.285.09:09:38.09#ibcon#first serial, iclass 32, count 2 2006.285.09:09:38.09#ibcon#enter sib2, iclass 32, count 2 2006.285.09:09:38.09#ibcon#flushed, iclass 32, count 2 2006.285.09:09:38.09#ibcon#about to write, iclass 32, count 2 2006.285.09:09:38.09#ibcon#wrote, iclass 32, count 2 2006.285.09:09:38.09#ibcon#about to read 3, iclass 32, count 2 2006.285.09:09:38.11#ibcon#read 3, iclass 32, count 2 2006.285.09:09:38.11#ibcon#about to read 4, iclass 32, count 2 2006.285.09:09:38.11#ibcon#read 4, iclass 32, count 2 2006.285.09:09:38.11#ibcon#about to read 5, iclass 32, count 2 2006.285.09:09:38.11#ibcon#read 5, iclass 32, count 2 2006.285.09:09:38.11#ibcon#about to read 6, iclass 32, count 2 2006.285.09:09:38.11#ibcon#read 6, iclass 32, count 2 2006.285.09:09:38.11#ibcon#end of sib2, iclass 32, count 2 2006.285.09:09:38.11#ibcon#*mode == 0, iclass 32, count 2 2006.285.09:09:38.11#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.09:09:38.11#ibcon#[27=AT06-03\r\n] 2006.285.09:09:38.11#ibcon#*before write, iclass 32, count 2 2006.285.09:09:38.11#ibcon#enter sib2, iclass 32, count 2 2006.285.09:09:38.11#ibcon#flushed, iclass 32, count 2 2006.285.09:09:38.11#ibcon#about to write, iclass 32, count 2 2006.285.09:09:38.11#ibcon#wrote, iclass 32, count 2 2006.285.09:09:38.11#ibcon#about to read 3, iclass 32, count 2 2006.285.09:09:38.14#ibcon#read 3, iclass 32, count 2 2006.285.09:09:38.14#ibcon#about to read 4, iclass 32, count 2 2006.285.09:09:38.14#ibcon#read 4, iclass 32, count 2 2006.285.09:09:38.14#ibcon#about to read 5, iclass 32, count 2 2006.285.09:09:38.14#ibcon#read 5, iclass 32, count 2 2006.285.09:09:38.14#ibcon#about to read 6, iclass 32, count 2 2006.285.09:09:38.14#ibcon#read 6, iclass 32, count 2 2006.285.09:09:38.14#ibcon#end of sib2, iclass 32, count 2 2006.285.09:09:38.14#ibcon#*after write, iclass 32, count 2 2006.285.09:09:38.14#ibcon#*before return 0, iclass 32, count 2 2006.285.09:09:38.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:09:38.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:09:38.14#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.09:09:38.14#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:38.14#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:09:38.26#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:09:38.26#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:09:38.26#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:09:38.26#ibcon#first serial, iclass 32, count 0 2006.285.09:09:38.26#ibcon#enter sib2, iclass 32, count 0 2006.285.09:09:38.26#ibcon#flushed, iclass 32, count 0 2006.285.09:09:38.26#ibcon#about to write, iclass 32, count 0 2006.285.09:09:38.26#ibcon#wrote, iclass 32, count 0 2006.285.09:09:38.26#ibcon#about to read 3, iclass 32, count 0 2006.285.09:09:38.28#ibcon#read 3, iclass 32, count 0 2006.285.09:09:38.28#ibcon#about to read 4, iclass 32, count 0 2006.285.09:09:38.28#ibcon#read 4, iclass 32, count 0 2006.285.09:09:38.28#ibcon#about to read 5, iclass 32, count 0 2006.285.09:09:38.28#ibcon#read 5, iclass 32, count 0 2006.285.09:09:38.28#ibcon#about to read 6, iclass 32, count 0 2006.285.09:09:38.28#ibcon#read 6, iclass 32, count 0 2006.285.09:09:38.28#ibcon#end of sib2, iclass 32, count 0 2006.285.09:09:38.28#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:09:38.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:09:38.28#ibcon#[27=USB\r\n] 2006.285.09:09:38.28#ibcon#*before write, iclass 32, count 0 2006.285.09:09:38.28#ibcon#enter sib2, iclass 32, count 0 2006.285.09:09:38.28#ibcon#flushed, iclass 32, count 0 2006.285.09:09:38.28#ibcon#about to write, iclass 32, count 0 2006.285.09:09:38.28#ibcon#wrote, iclass 32, count 0 2006.285.09:09:38.28#ibcon#about to read 3, iclass 32, count 0 2006.285.09:09:38.31#ibcon#read 3, iclass 32, count 0 2006.285.09:09:38.31#ibcon#about to read 4, iclass 32, count 0 2006.285.09:09:38.31#ibcon#read 4, iclass 32, count 0 2006.285.09:09:38.31#ibcon#about to read 5, iclass 32, count 0 2006.285.09:09:38.31#ibcon#read 5, iclass 32, count 0 2006.285.09:09:38.31#ibcon#about to read 6, iclass 32, count 0 2006.285.09:09:38.31#ibcon#read 6, iclass 32, count 0 2006.285.09:09:38.31#ibcon#end of sib2, iclass 32, count 0 2006.285.09:09:38.31#ibcon#*after write, iclass 32, count 0 2006.285.09:09:38.31#ibcon#*before return 0, iclass 32, count 0 2006.285.09:09:38.31#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:09:38.31#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:09:38.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:09:38.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:09:38.31$vck44/vblo=7,734.99 2006.285.09:09:38.31#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.09:09:38.31#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.09:09:38.31#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:38.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:09:38.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:09:38.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:09:38.31#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:09:38.31#ibcon#first serial, iclass 34, count 0 2006.285.09:09:38.31#ibcon#enter sib2, iclass 34, count 0 2006.285.09:09:38.31#ibcon#flushed, iclass 34, count 0 2006.285.09:09:38.31#ibcon#about to write, iclass 34, count 0 2006.285.09:09:38.31#ibcon#wrote, iclass 34, count 0 2006.285.09:09:38.31#ibcon#about to read 3, iclass 34, count 0 2006.285.09:09:38.33#ibcon#read 3, iclass 34, count 0 2006.285.09:09:38.33#ibcon#about to read 4, iclass 34, count 0 2006.285.09:09:38.33#ibcon#read 4, iclass 34, count 0 2006.285.09:09:38.33#ibcon#about to read 5, iclass 34, count 0 2006.285.09:09:38.33#ibcon#read 5, iclass 34, count 0 2006.285.09:09:38.33#ibcon#about to read 6, iclass 34, count 0 2006.285.09:09:38.33#ibcon#read 6, iclass 34, count 0 2006.285.09:09:38.33#ibcon#end of sib2, iclass 34, count 0 2006.285.09:09:38.33#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:09:38.33#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:09:38.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:09:38.33#ibcon#*before write, iclass 34, count 0 2006.285.09:09:38.33#ibcon#enter sib2, iclass 34, count 0 2006.285.09:09:38.33#ibcon#flushed, iclass 34, count 0 2006.285.09:09:38.33#ibcon#about to write, iclass 34, count 0 2006.285.09:09:38.33#ibcon#wrote, iclass 34, count 0 2006.285.09:09:38.33#ibcon#about to read 3, iclass 34, count 0 2006.285.09:09:38.37#ibcon#read 3, iclass 34, count 0 2006.285.09:09:38.37#ibcon#about to read 4, iclass 34, count 0 2006.285.09:09:38.37#ibcon#read 4, iclass 34, count 0 2006.285.09:09:38.37#ibcon#about to read 5, iclass 34, count 0 2006.285.09:09:38.37#ibcon#read 5, iclass 34, count 0 2006.285.09:09:38.37#ibcon#about to read 6, iclass 34, count 0 2006.285.09:09:38.37#ibcon#read 6, iclass 34, count 0 2006.285.09:09:38.37#ibcon#end of sib2, iclass 34, count 0 2006.285.09:09:38.37#ibcon#*after write, iclass 34, count 0 2006.285.09:09:38.37#ibcon#*before return 0, iclass 34, count 0 2006.285.09:09:38.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:09:38.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:09:38.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:09:38.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:09:38.37$vck44/vb=7,4 2006.285.09:09:38.37#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.09:09:38.37#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.09:09:38.37#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:38.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:09:38.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:09:38.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:09:38.43#ibcon#enter wrdev, iclass 36, count 2 2006.285.09:09:38.43#ibcon#first serial, iclass 36, count 2 2006.285.09:09:38.43#ibcon#enter sib2, iclass 36, count 2 2006.285.09:09:38.43#ibcon#flushed, iclass 36, count 2 2006.285.09:09:38.43#ibcon#about to write, iclass 36, count 2 2006.285.09:09:38.43#ibcon#wrote, iclass 36, count 2 2006.285.09:09:38.43#ibcon#about to read 3, iclass 36, count 2 2006.285.09:09:38.45#ibcon#read 3, iclass 36, count 2 2006.285.09:09:38.45#ibcon#about to read 4, iclass 36, count 2 2006.285.09:09:38.45#ibcon#read 4, iclass 36, count 2 2006.285.09:09:38.45#ibcon#about to read 5, iclass 36, count 2 2006.285.09:09:38.45#ibcon#read 5, iclass 36, count 2 2006.285.09:09:38.45#ibcon#about to read 6, iclass 36, count 2 2006.285.09:09:38.45#ibcon#read 6, iclass 36, count 2 2006.285.09:09:38.45#ibcon#end of sib2, iclass 36, count 2 2006.285.09:09:38.45#ibcon#*mode == 0, iclass 36, count 2 2006.285.09:09:38.45#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.09:09:38.45#ibcon#[27=AT07-04\r\n] 2006.285.09:09:38.45#ibcon#*before write, iclass 36, count 2 2006.285.09:09:38.45#ibcon#enter sib2, iclass 36, count 2 2006.285.09:09:38.45#ibcon#flushed, iclass 36, count 2 2006.285.09:09:38.45#ibcon#about to write, iclass 36, count 2 2006.285.09:09:38.45#ibcon#wrote, iclass 36, count 2 2006.285.09:09:38.45#ibcon#about to read 3, iclass 36, count 2 2006.285.09:09:38.48#ibcon#read 3, iclass 36, count 2 2006.285.09:09:38.48#ibcon#about to read 4, iclass 36, count 2 2006.285.09:09:38.48#ibcon#read 4, iclass 36, count 2 2006.285.09:09:38.48#ibcon#about to read 5, iclass 36, count 2 2006.285.09:09:38.48#ibcon#read 5, iclass 36, count 2 2006.285.09:09:38.48#ibcon#about to read 6, iclass 36, count 2 2006.285.09:09:38.48#ibcon#read 6, iclass 36, count 2 2006.285.09:09:38.48#ibcon#end of sib2, iclass 36, count 2 2006.285.09:09:38.48#ibcon#*after write, iclass 36, count 2 2006.285.09:09:38.48#ibcon#*before return 0, iclass 36, count 2 2006.285.09:09:38.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:09:38.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:09:38.48#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.09:09:38.48#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:38.48#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:09:38.60#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:09:38.60#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:09:38.60#ibcon#enter wrdev, iclass 36, count 0 2006.285.09:09:38.60#ibcon#first serial, iclass 36, count 0 2006.285.09:09:38.60#ibcon#enter sib2, iclass 36, count 0 2006.285.09:09:38.60#ibcon#flushed, iclass 36, count 0 2006.285.09:09:38.60#ibcon#about to write, iclass 36, count 0 2006.285.09:09:38.60#ibcon#wrote, iclass 36, count 0 2006.285.09:09:38.60#ibcon#about to read 3, iclass 36, count 0 2006.285.09:09:38.62#ibcon#read 3, iclass 36, count 0 2006.285.09:09:38.62#ibcon#about to read 4, iclass 36, count 0 2006.285.09:09:38.62#ibcon#read 4, iclass 36, count 0 2006.285.09:09:38.62#ibcon#about to read 5, iclass 36, count 0 2006.285.09:09:38.62#ibcon#read 5, iclass 36, count 0 2006.285.09:09:38.62#ibcon#about to read 6, iclass 36, count 0 2006.285.09:09:38.62#ibcon#read 6, iclass 36, count 0 2006.285.09:09:38.62#ibcon#end of sib2, iclass 36, count 0 2006.285.09:09:38.62#ibcon#*mode == 0, iclass 36, count 0 2006.285.09:09:38.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.09:09:38.62#ibcon#[27=USB\r\n] 2006.285.09:09:38.62#ibcon#*before write, iclass 36, count 0 2006.285.09:09:38.62#ibcon#enter sib2, iclass 36, count 0 2006.285.09:09:38.62#ibcon#flushed, iclass 36, count 0 2006.285.09:09:38.62#ibcon#about to write, iclass 36, count 0 2006.285.09:09:38.62#ibcon#wrote, iclass 36, count 0 2006.285.09:09:38.62#ibcon#about to read 3, iclass 36, count 0 2006.285.09:09:38.65#ibcon#read 3, iclass 36, count 0 2006.285.09:09:38.65#ibcon#about to read 4, iclass 36, count 0 2006.285.09:09:38.65#ibcon#read 4, iclass 36, count 0 2006.285.09:09:38.65#ibcon#about to read 5, iclass 36, count 0 2006.285.09:09:38.65#ibcon#read 5, iclass 36, count 0 2006.285.09:09:38.65#ibcon#about to read 6, iclass 36, count 0 2006.285.09:09:38.65#ibcon#read 6, iclass 36, count 0 2006.285.09:09:38.65#ibcon#end of sib2, iclass 36, count 0 2006.285.09:09:38.65#ibcon#*after write, iclass 36, count 0 2006.285.09:09:38.65#ibcon#*before return 0, iclass 36, count 0 2006.285.09:09:38.65#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:09:38.65#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:09:38.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.09:09:38.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.09:09:38.65$vck44/vblo=8,744.99 2006.285.09:09:38.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.09:09:38.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.09:09:38.65#ibcon#ireg 17 cls_cnt 0 2006.285.09:09:38.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:09:38.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:09:38.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:09:38.65#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:09:38.65#ibcon#first serial, iclass 38, count 0 2006.285.09:09:38.65#ibcon#enter sib2, iclass 38, count 0 2006.285.09:09:38.65#ibcon#flushed, iclass 38, count 0 2006.285.09:09:38.65#ibcon#about to write, iclass 38, count 0 2006.285.09:09:38.65#ibcon#wrote, iclass 38, count 0 2006.285.09:09:38.65#ibcon#about to read 3, iclass 38, count 0 2006.285.09:09:38.67#ibcon#read 3, iclass 38, count 0 2006.285.09:09:38.67#ibcon#about to read 4, iclass 38, count 0 2006.285.09:09:38.67#ibcon#read 4, iclass 38, count 0 2006.285.09:09:38.67#ibcon#about to read 5, iclass 38, count 0 2006.285.09:09:38.67#ibcon#read 5, iclass 38, count 0 2006.285.09:09:38.67#ibcon#about to read 6, iclass 38, count 0 2006.285.09:09:38.67#ibcon#read 6, iclass 38, count 0 2006.285.09:09:38.67#ibcon#end of sib2, iclass 38, count 0 2006.285.09:09:38.67#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:09:38.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:09:38.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:09:38.67#ibcon#*before write, iclass 38, count 0 2006.285.09:09:38.67#ibcon#enter sib2, iclass 38, count 0 2006.285.09:09:38.67#ibcon#flushed, iclass 38, count 0 2006.285.09:09:38.67#ibcon#about to write, iclass 38, count 0 2006.285.09:09:38.67#ibcon#wrote, iclass 38, count 0 2006.285.09:09:38.67#ibcon#about to read 3, iclass 38, count 0 2006.285.09:09:38.71#ibcon#read 3, iclass 38, count 0 2006.285.09:09:38.71#ibcon#about to read 4, iclass 38, count 0 2006.285.09:09:38.71#ibcon#read 4, iclass 38, count 0 2006.285.09:09:38.71#ibcon#about to read 5, iclass 38, count 0 2006.285.09:09:38.71#ibcon#read 5, iclass 38, count 0 2006.285.09:09:38.71#ibcon#about to read 6, iclass 38, count 0 2006.285.09:09:38.71#ibcon#read 6, iclass 38, count 0 2006.285.09:09:38.71#ibcon#end of sib2, iclass 38, count 0 2006.285.09:09:38.71#ibcon#*after write, iclass 38, count 0 2006.285.09:09:38.71#ibcon#*before return 0, iclass 38, count 0 2006.285.09:09:38.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:09:38.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:09:38.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:09:38.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:09:38.71$vck44/vb=8,4 2006.285.09:09:38.71#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.09:09:38.71#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.09:09:38.71#ibcon#ireg 11 cls_cnt 2 2006.285.09:09:38.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:09:38.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:09:38.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:09:38.77#ibcon#enter wrdev, iclass 40, count 2 2006.285.09:09:38.77#ibcon#first serial, iclass 40, count 2 2006.285.09:09:38.77#ibcon#enter sib2, iclass 40, count 2 2006.285.09:09:38.77#ibcon#flushed, iclass 40, count 2 2006.285.09:09:38.77#ibcon#about to write, iclass 40, count 2 2006.285.09:09:38.77#ibcon#wrote, iclass 40, count 2 2006.285.09:09:38.77#ibcon#about to read 3, iclass 40, count 2 2006.285.09:09:38.79#ibcon#read 3, iclass 40, count 2 2006.285.09:09:38.79#ibcon#about to read 4, iclass 40, count 2 2006.285.09:09:38.79#ibcon#read 4, iclass 40, count 2 2006.285.09:09:38.79#ibcon#about to read 5, iclass 40, count 2 2006.285.09:09:38.79#ibcon#read 5, iclass 40, count 2 2006.285.09:09:38.79#ibcon#about to read 6, iclass 40, count 2 2006.285.09:09:38.79#ibcon#read 6, iclass 40, count 2 2006.285.09:09:38.79#ibcon#end of sib2, iclass 40, count 2 2006.285.09:09:38.79#ibcon#*mode == 0, iclass 40, count 2 2006.285.09:09:38.79#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.09:09:38.79#ibcon#[27=AT08-04\r\n] 2006.285.09:09:38.79#ibcon#*before write, iclass 40, count 2 2006.285.09:09:38.79#ibcon#enter sib2, iclass 40, count 2 2006.285.09:09:38.79#ibcon#flushed, iclass 40, count 2 2006.285.09:09:38.79#ibcon#about to write, iclass 40, count 2 2006.285.09:09:38.79#ibcon#wrote, iclass 40, count 2 2006.285.09:09:38.79#ibcon#about to read 3, iclass 40, count 2 2006.285.09:09:38.82#ibcon#read 3, iclass 40, count 2 2006.285.09:09:38.82#ibcon#about to read 4, iclass 40, count 2 2006.285.09:09:38.82#ibcon#read 4, iclass 40, count 2 2006.285.09:09:38.82#ibcon#about to read 5, iclass 40, count 2 2006.285.09:09:38.82#ibcon#read 5, iclass 40, count 2 2006.285.09:09:38.82#ibcon#about to read 6, iclass 40, count 2 2006.285.09:09:38.82#ibcon#read 6, iclass 40, count 2 2006.285.09:09:38.82#ibcon#end of sib2, iclass 40, count 2 2006.285.09:09:38.82#ibcon#*after write, iclass 40, count 2 2006.285.09:09:38.82#ibcon#*before return 0, iclass 40, count 2 2006.285.09:09:38.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:09:38.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:09:38.82#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.09:09:38.82#ibcon#ireg 7 cls_cnt 0 2006.285.09:09:38.82#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:09:38.94#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:09:38.94#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:09:38.94#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:09:38.94#ibcon#first serial, iclass 40, count 0 2006.285.09:09:38.94#ibcon#enter sib2, iclass 40, count 0 2006.285.09:09:38.94#ibcon#flushed, iclass 40, count 0 2006.285.09:09:38.94#ibcon#about to write, iclass 40, count 0 2006.285.09:09:38.94#ibcon#wrote, iclass 40, count 0 2006.285.09:09:38.94#ibcon#about to read 3, iclass 40, count 0 2006.285.09:09:38.96#ibcon#read 3, iclass 40, count 0 2006.285.09:09:38.96#ibcon#about to read 4, iclass 40, count 0 2006.285.09:09:38.96#ibcon#read 4, iclass 40, count 0 2006.285.09:09:38.96#ibcon#about to read 5, iclass 40, count 0 2006.285.09:09:38.96#ibcon#read 5, iclass 40, count 0 2006.285.09:09:38.96#ibcon#about to read 6, iclass 40, count 0 2006.285.09:09:38.96#ibcon#read 6, iclass 40, count 0 2006.285.09:09:38.96#ibcon#end of sib2, iclass 40, count 0 2006.285.09:09:38.96#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:09:38.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:09:38.96#ibcon#[27=USB\r\n] 2006.285.09:09:38.96#ibcon#*before write, iclass 40, count 0 2006.285.09:09:38.96#ibcon#enter sib2, iclass 40, count 0 2006.285.09:09:38.96#ibcon#flushed, iclass 40, count 0 2006.285.09:09:38.96#ibcon#about to write, iclass 40, count 0 2006.285.09:09:38.96#ibcon#wrote, iclass 40, count 0 2006.285.09:09:38.96#ibcon#about to read 3, iclass 40, count 0 2006.285.09:09:38.99#ibcon#read 3, iclass 40, count 0 2006.285.09:09:38.99#ibcon#about to read 4, iclass 40, count 0 2006.285.09:09:38.99#ibcon#read 4, iclass 40, count 0 2006.285.09:09:38.99#ibcon#about to read 5, iclass 40, count 0 2006.285.09:09:38.99#ibcon#read 5, iclass 40, count 0 2006.285.09:09:38.99#ibcon#about to read 6, iclass 40, count 0 2006.285.09:09:38.99#ibcon#read 6, iclass 40, count 0 2006.285.09:09:38.99#ibcon#end of sib2, iclass 40, count 0 2006.285.09:09:38.99#ibcon#*after write, iclass 40, count 0 2006.285.09:09:38.99#ibcon#*before return 0, iclass 40, count 0 2006.285.09:09:38.99#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:09:38.99#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:09:38.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:09:38.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:09:38.99$vck44/vabw=wide 2006.285.09:09:38.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.09:09:38.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.09:09:38.99#ibcon#ireg 8 cls_cnt 0 2006.285.09:09:38.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:09:38.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:09:38.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:09:38.99#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:09:38.99#ibcon#first serial, iclass 4, count 0 2006.285.09:09:38.99#ibcon#enter sib2, iclass 4, count 0 2006.285.09:09:38.99#ibcon#flushed, iclass 4, count 0 2006.285.09:09:38.99#ibcon#about to write, iclass 4, count 0 2006.285.09:09:38.99#ibcon#wrote, iclass 4, count 0 2006.285.09:09:38.99#ibcon#about to read 3, iclass 4, count 0 2006.285.09:09:39.01#ibcon#read 3, iclass 4, count 0 2006.285.09:09:39.01#ibcon#about to read 4, iclass 4, count 0 2006.285.09:09:39.01#ibcon#read 4, iclass 4, count 0 2006.285.09:09:39.01#ibcon#about to read 5, iclass 4, count 0 2006.285.09:09:39.01#ibcon#read 5, iclass 4, count 0 2006.285.09:09:39.01#ibcon#about to read 6, iclass 4, count 0 2006.285.09:09:39.01#ibcon#read 6, iclass 4, count 0 2006.285.09:09:39.01#ibcon#end of sib2, iclass 4, count 0 2006.285.09:09:39.01#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:09:39.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:09:39.01#ibcon#[25=BW32\r\n] 2006.285.09:09:39.01#ibcon#*before write, iclass 4, count 0 2006.285.09:09:39.01#ibcon#enter sib2, iclass 4, count 0 2006.285.09:09:39.01#ibcon#flushed, iclass 4, count 0 2006.285.09:09:39.01#ibcon#about to write, iclass 4, count 0 2006.285.09:09:39.01#ibcon#wrote, iclass 4, count 0 2006.285.09:09:39.01#ibcon#about to read 3, iclass 4, count 0 2006.285.09:09:39.04#ibcon#read 3, iclass 4, count 0 2006.285.09:09:39.04#ibcon#about to read 4, iclass 4, count 0 2006.285.09:09:39.04#ibcon#read 4, iclass 4, count 0 2006.285.09:09:39.04#ibcon#about to read 5, iclass 4, count 0 2006.285.09:09:39.04#ibcon#read 5, iclass 4, count 0 2006.285.09:09:39.04#ibcon#about to read 6, iclass 4, count 0 2006.285.09:09:39.04#ibcon#read 6, iclass 4, count 0 2006.285.09:09:39.04#ibcon#end of sib2, iclass 4, count 0 2006.285.09:09:39.04#ibcon#*after write, iclass 4, count 0 2006.285.09:09:39.04#ibcon#*before return 0, iclass 4, count 0 2006.285.09:09:39.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:09:39.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:09:39.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:09:39.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:09:39.04$vck44/vbbw=wide 2006.285.09:09:39.04#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.09:09:39.04#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.09:09:39.04#ibcon#ireg 8 cls_cnt 0 2006.285.09:09:39.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:09:39.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:09:39.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:09:39.11#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:09:39.11#ibcon#first serial, iclass 6, count 0 2006.285.09:09:39.11#ibcon#enter sib2, iclass 6, count 0 2006.285.09:09:39.11#ibcon#flushed, iclass 6, count 0 2006.285.09:09:39.11#ibcon#about to write, iclass 6, count 0 2006.285.09:09:39.11#ibcon#wrote, iclass 6, count 0 2006.285.09:09:39.11#ibcon#about to read 3, iclass 6, count 0 2006.285.09:09:39.13#ibcon#read 3, iclass 6, count 0 2006.285.09:09:39.13#ibcon#about to read 4, iclass 6, count 0 2006.285.09:09:39.13#ibcon#read 4, iclass 6, count 0 2006.285.09:09:39.13#ibcon#about to read 5, iclass 6, count 0 2006.285.09:09:39.13#ibcon#read 5, iclass 6, count 0 2006.285.09:09:39.13#ibcon#about to read 6, iclass 6, count 0 2006.285.09:09:39.13#ibcon#read 6, iclass 6, count 0 2006.285.09:09:39.13#ibcon#end of sib2, iclass 6, count 0 2006.285.09:09:39.13#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:09:39.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:09:39.13#ibcon#[27=BW32\r\n] 2006.285.09:09:39.13#ibcon#*before write, iclass 6, count 0 2006.285.09:09:39.13#ibcon#enter sib2, iclass 6, count 0 2006.285.09:09:39.13#ibcon#flushed, iclass 6, count 0 2006.285.09:09:39.13#ibcon#about to write, iclass 6, count 0 2006.285.09:09:39.13#ibcon#wrote, iclass 6, count 0 2006.285.09:09:39.13#ibcon#about to read 3, iclass 6, count 0 2006.285.09:09:39.16#ibcon#read 3, iclass 6, count 0 2006.285.09:09:39.16#ibcon#about to read 4, iclass 6, count 0 2006.285.09:09:39.16#ibcon#read 4, iclass 6, count 0 2006.285.09:09:39.16#ibcon#about to read 5, iclass 6, count 0 2006.285.09:09:39.16#ibcon#read 5, iclass 6, count 0 2006.285.09:09:39.16#ibcon#about to read 6, iclass 6, count 0 2006.285.09:09:39.16#ibcon#read 6, iclass 6, count 0 2006.285.09:09:39.16#ibcon#end of sib2, iclass 6, count 0 2006.285.09:09:39.16#ibcon#*after write, iclass 6, count 0 2006.285.09:09:39.16#ibcon#*before return 0, iclass 6, count 0 2006.285.09:09:39.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:09:39.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:09:39.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:09:39.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:09:39.16$setupk4/ifdk4 2006.285.09:09:39.16$ifdk4/lo= 2006.285.09:09:39.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:09:39.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:09:39.16$ifdk4/patch= 2006.285.09:09:39.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:09:39.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:09:39.16$setupk4/!*+20s 2006.285.09:09:45.14#trakl#Source acquired 2006.285.09:09:45.65#abcon#<5=/03 0.7 1.5 20.79 861014.9\r\n> 2006.285.09:09:45.67#abcon#{5=INTERFACE CLEAR} 2006.285.09:09:45.73#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:09:47.14#flagr#flagr/antenna,acquired 2006.285.09:09:53.67$setupk4/"tpicd 2006.285.09:09:53.67$setupk4/echo=off 2006.285.09:09:53.67$setupk4/xlog=off 2006.285.09:09:53.67:!2006.285.09:11:39 2006.285.09:11:39.00:preob 2006.285.09:11:39.14/onsource/TRACKING 2006.285.09:11:39.14:!2006.285.09:11:49 2006.285.09:11:49.00:"tape 2006.285.09:11:49.00:"st=record 2006.285.09:11:49.00:data_valid=on 2006.285.09:11:49.00:midob 2006.285.09:11:50.14/onsource/TRACKING 2006.285.09:11:50.14/wx/20.64,1014.9,86 2006.285.09:11:50.28/cable/+6.4774E-03 2006.285.09:11:51.37/va/01,07,usb,yes,31,34 2006.285.09:11:51.37/va/02,06,usb,yes,31,32 2006.285.09:11:51.37/va/03,07,usb,yes,31,33 2006.285.09:11:51.37/va/04,06,usb,yes,32,34 2006.285.09:11:51.37/va/05,03,usb,yes,32,32 2006.285.09:11:51.37/va/06,04,usb,yes,29,28 2006.285.09:11:51.37/va/07,04,usb,yes,29,30 2006.285.09:11:51.37/va/08,03,usb,yes,30,36 2006.285.09:11:51.60/valo/01,524.99,yes,locked 2006.285.09:11:51.60/valo/02,534.99,yes,locked 2006.285.09:11:51.60/valo/03,564.99,yes,locked 2006.285.09:11:51.60/valo/04,624.99,yes,locked 2006.285.09:11:51.60/valo/05,734.99,yes,locked 2006.285.09:11:51.60/valo/06,814.99,yes,locked 2006.285.09:11:51.60/valo/07,864.99,yes,locked 2006.285.09:11:51.60/valo/08,884.99,yes,locked 2006.285.09:11:52.69/vb/01,04,usb,yes,30,28 2006.285.09:11:52.69/vb/02,05,usb,yes,28,28 2006.285.09:11:52.69/vb/03,04,usb,yes,29,32 2006.285.09:11:52.69/vb/04,05,usb,yes,29,28 2006.285.09:11:52.69/vb/05,04,usb,yes,26,28 2006.285.09:11:52.69/vb/06,03,usb,yes,37,33 2006.285.09:11:52.69/vb/07,04,usb,yes,30,30 2006.285.09:11:52.69/vb/08,04,usb,yes,27,31 2006.285.09:11:52.92/vblo/01,629.99,yes,locked 2006.285.09:11:52.92/vblo/02,634.99,yes,locked 2006.285.09:11:52.92/vblo/03,649.99,yes,locked 2006.285.09:11:52.92/vblo/04,679.99,yes,locked 2006.285.09:11:52.92/vblo/05,709.99,yes,locked 2006.285.09:11:52.92/vblo/06,719.99,yes,locked 2006.285.09:11:52.92/vblo/07,734.99,yes,locked 2006.285.09:11:52.92/vblo/08,744.99,yes,locked 2006.285.09:11:53.07/vabw/8 2006.285.09:11:53.22/vbbw/8 2006.285.09:11:53.31/xfe/off,on,12.2 2006.285.09:11:53.69/ifatt/23,28,28,28 2006.285.09:11:54.07/fmout-gps/S +2.74E-07 2006.285.09:11:54.09:!2006.285.09:12:59 2006.285.09:12:59.00:data_valid=off 2006.285.09:12:59.00:"et 2006.285.09:12:59.00:!+3s 2006.285.09:13:02.01:"tape 2006.285.09:13:02.01:postob 2006.285.09:13:02.23/cable/+6.4776E-03 2006.285.09:13:02.23/wx/20.56,1014.9,86 2006.285.09:13:03.08/fmout-gps/S +2.77E-07 2006.285.09:13:03.08:scan_name=285-0918,jd0610,50 2006.285.09:13:03.08:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.285.09:13:04.13#flagr#flagr/antenna,new-source 2006.285.09:13:04.13:checkk5 2006.285.09:13:04.76/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:13:05.19/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:13:05.80/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:13:06.23/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:13:06.62/chk_obsdata//k5ts1/T2850911??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.09:13:07.00/chk_obsdata//k5ts2/T2850911??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.09:13:07.42/chk_obsdata//k5ts3/T2850911??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.09:13:07.83/chk_obsdata//k5ts4/T2850911??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.09:13:08.84/k5log//k5ts1_log_newline 2006.285.09:13:09.63/k5log//k5ts2_log_newline 2006.285.09:13:10.44/k5log//k5ts3_log_newline 2006.285.09:13:11.38/k5log//k5ts4_log_newline 2006.285.09:13:11.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:13:11.40:setupk4=1 2006.285.09:13:11.40$setupk4/echo=on 2006.285.09:13:11.40$setupk4/pcalon 2006.285.09:13:11.40$pcalon/"no phase cal control is implemented here 2006.285.09:13:11.40$setupk4/"tpicd=stop 2006.285.09:13:11.40$setupk4/"rec=synch_on 2006.285.09:13:11.40$setupk4/"rec_mode=128 2006.285.09:13:11.40$setupk4/!* 2006.285.09:13:11.40$setupk4/recpk4 2006.285.09:13:11.40$recpk4/recpatch= 2006.285.09:13:11.40$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:13:11.40$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:13:11.40$setupk4/vck44 2006.285.09:13:11.40$vck44/valo=1,524.99 2006.285.09:13:11.40#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.09:13:11.40#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.09:13:11.40#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:11.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:13:11.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:13:11.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:13:11.40#ibcon#enter wrdev, iclass 25, count 0 2006.285.09:13:11.40#ibcon#first serial, iclass 25, count 0 2006.285.09:13:11.40#ibcon#enter sib2, iclass 25, count 0 2006.285.09:13:11.40#ibcon#flushed, iclass 25, count 0 2006.285.09:13:11.40#ibcon#about to write, iclass 25, count 0 2006.285.09:13:11.40#ibcon#wrote, iclass 25, count 0 2006.285.09:13:11.40#ibcon#about to read 3, iclass 25, count 0 2006.285.09:13:11.42#ibcon#read 3, iclass 25, count 0 2006.285.09:13:11.42#ibcon#about to read 4, iclass 25, count 0 2006.285.09:13:11.42#ibcon#read 4, iclass 25, count 0 2006.285.09:13:11.42#ibcon#about to read 5, iclass 25, count 0 2006.285.09:13:11.42#ibcon#read 5, iclass 25, count 0 2006.285.09:13:11.42#ibcon#about to read 6, iclass 25, count 0 2006.285.09:13:11.42#ibcon#read 6, iclass 25, count 0 2006.285.09:13:11.42#ibcon#end of sib2, iclass 25, count 0 2006.285.09:13:11.42#ibcon#*mode == 0, iclass 25, count 0 2006.285.09:13:11.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.09:13:11.42#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:13:11.42#ibcon#*before write, iclass 25, count 0 2006.285.09:13:11.42#ibcon#enter sib2, iclass 25, count 0 2006.285.09:13:11.42#ibcon#flushed, iclass 25, count 0 2006.285.09:13:11.42#ibcon#about to write, iclass 25, count 0 2006.285.09:13:11.42#ibcon#wrote, iclass 25, count 0 2006.285.09:13:11.42#ibcon#about to read 3, iclass 25, count 0 2006.285.09:13:11.47#ibcon#read 3, iclass 25, count 0 2006.285.09:13:11.47#ibcon#about to read 4, iclass 25, count 0 2006.285.09:13:11.47#ibcon#read 4, iclass 25, count 0 2006.285.09:13:11.47#ibcon#about to read 5, iclass 25, count 0 2006.285.09:13:11.47#ibcon#read 5, iclass 25, count 0 2006.285.09:13:11.47#ibcon#about to read 6, iclass 25, count 0 2006.285.09:13:11.47#ibcon#read 6, iclass 25, count 0 2006.285.09:13:11.47#ibcon#end of sib2, iclass 25, count 0 2006.285.09:13:11.47#ibcon#*after write, iclass 25, count 0 2006.285.09:13:11.47#ibcon#*before return 0, iclass 25, count 0 2006.285.09:13:11.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:13:11.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:13:11.47#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.09:13:11.47#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.09:13:11.47$vck44/va=1,7 2006.285.09:13:11.47#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.09:13:11.47#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.09:13:11.47#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:11.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:13:11.47#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:13:11.47#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:13:11.47#ibcon#enter wrdev, iclass 27, count 2 2006.285.09:13:11.47#ibcon#first serial, iclass 27, count 2 2006.285.09:13:11.47#ibcon#enter sib2, iclass 27, count 2 2006.285.09:13:11.47#ibcon#flushed, iclass 27, count 2 2006.285.09:13:11.47#ibcon#about to write, iclass 27, count 2 2006.285.09:13:11.47#ibcon#wrote, iclass 27, count 2 2006.285.09:13:11.47#ibcon#about to read 3, iclass 27, count 2 2006.285.09:13:11.49#ibcon#read 3, iclass 27, count 2 2006.285.09:13:11.49#ibcon#about to read 4, iclass 27, count 2 2006.285.09:13:11.49#ibcon#read 4, iclass 27, count 2 2006.285.09:13:11.49#ibcon#about to read 5, iclass 27, count 2 2006.285.09:13:11.49#ibcon#read 5, iclass 27, count 2 2006.285.09:13:11.49#ibcon#about to read 6, iclass 27, count 2 2006.285.09:13:11.49#ibcon#read 6, iclass 27, count 2 2006.285.09:13:11.49#ibcon#end of sib2, iclass 27, count 2 2006.285.09:13:11.49#ibcon#*mode == 0, iclass 27, count 2 2006.285.09:13:11.49#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.09:13:11.49#ibcon#[25=AT01-07\r\n] 2006.285.09:13:11.49#ibcon#*before write, iclass 27, count 2 2006.285.09:13:11.49#ibcon#enter sib2, iclass 27, count 2 2006.285.09:13:11.49#ibcon#flushed, iclass 27, count 2 2006.285.09:13:11.49#ibcon#about to write, iclass 27, count 2 2006.285.09:13:11.49#ibcon#wrote, iclass 27, count 2 2006.285.09:13:11.49#ibcon#about to read 3, iclass 27, count 2 2006.285.09:13:11.52#ibcon#read 3, iclass 27, count 2 2006.285.09:13:11.52#ibcon#about to read 4, iclass 27, count 2 2006.285.09:13:11.52#ibcon#read 4, iclass 27, count 2 2006.285.09:13:11.52#ibcon#about to read 5, iclass 27, count 2 2006.285.09:13:11.52#ibcon#read 5, iclass 27, count 2 2006.285.09:13:11.52#ibcon#about to read 6, iclass 27, count 2 2006.285.09:13:11.52#ibcon#read 6, iclass 27, count 2 2006.285.09:13:11.52#ibcon#end of sib2, iclass 27, count 2 2006.285.09:13:11.52#ibcon#*after write, iclass 27, count 2 2006.285.09:13:11.52#ibcon#*before return 0, iclass 27, count 2 2006.285.09:13:11.52#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:13:11.52#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:13:11.52#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.09:13:11.52#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:11.52#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:13:11.64#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:13:11.64#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:13:11.64#ibcon#enter wrdev, iclass 27, count 0 2006.285.09:13:11.64#ibcon#first serial, iclass 27, count 0 2006.285.09:13:11.64#ibcon#enter sib2, iclass 27, count 0 2006.285.09:13:11.64#ibcon#flushed, iclass 27, count 0 2006.285.09:13:11.64#ibcon#about to write, iclass 27, count 0 2006.285.09:13:11.64#ibcon#wrote, iclass 27, count 0 2006.285.09:13:11.64#ibcon#about to read 3, iclass 27, count 0 2006.285.09:13:11.66#ibcon#read 3, iclass 27, count 0 2006.285.09:13:11.66#ibcon#about to read 4, iclass 27, count 0 2006.285.09:13:11.66#ibcon#read 4, iclass 27, count 0 2006.285.09:13:11.66#ibcon#about to read 5, iclass 27, count 0 2006.285.09:13:11.66#ibcon#read 5, iclass 27, count 0 2006.285.09:13:11.66#ibcon#about to read 6, iclass 27, count 0 2006.285.09:13:11.66#ibcon#read 6, iclass 27, count 0 2006.285.09:13:11.66#ibcon#end of sib2, iclass 27, count 0 2006.285.09:13:11.66#ibcon#*mode == 0, iclass 27, count 0 2006.285.09:13:11.66#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.09:13:11.66#ibcon#[25=USB\r\n] 2006.285.09:13:11.66#ibcon#*before write, iclass 27, count 0 2006.285.09:13:11.66#ibcon#enter sib2, iclass 27, count 0 2006.285.09:13:11.66#ibcon#flushed, iclass 27, count 0 2006.285.09:13:11.66#ibcon#about to write, iclass 27, count 0 2006.285.09:13:11.66#ibcon#wrote, iclass 27, count 0 2006.285.09:13:11.66#ibcon#about to read 3, iclass 27, count 0 2006.285.09:13:11.69#ibcon#read 3, iclass 27, count 0 2006.285.09:13:11.69#ibcon#about to read 4, iclass 27, count 0 2006.285.09:13:11.69#ibcon#read 4, iclass 27, count 0 2006.285.09:13:11.69#ibcon#about to read 5, iclass 27, count 0 2006.285.09:13:11.69#ibcon#read 5, iclass 27, count 0 2006.285.09:13:11.69#ibcon#about to read 6, iclass 27, count 0 2006.285.09:13:11.69#ibcon#read 6, iclass 27, count 0 2006.285.09:13:11.69#ibcon#end of sib2, iclass 27, count 0 2006.285.09:13:11.69#ibcon#*after write, iclass 27, count 0 2006.285.09:13:11.69#ibcon#*before return 0, iclass 27, count 0 2006.285.09:13:11.69#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:13:11.69#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:13:11.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.09:13:11.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.09:13:11.69$vck44/valo=2,534.99 2006.285.09:13:11.69#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.09:13:11.69#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.09:13:11.69#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:11.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:13:11.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:13:11.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:13:11.69#ibcon#enter wrdev, iclass 29, count 0 2006.285.09:13:11.69#ibcon#first serial, iclass 29, count 0 2006.285.09:13:11.69#ibcon#enter sib2, iclass 29, count 0 2006.285.09:13:11.69#ibcon#flushed, iclass 29, count 0 2006.285.09:13:11.69#ibcon#about to write, iclass 29, count 0 2006.285.09:13:11.69#ibcon#wrote, iclass 29, count 0 2006.285.09:13:11.69#ibcon#about to read 3, iclass 29, count 0 2006.285.09:13:11.71#ibcon#read 3, iclass 29, count 0 2006.285.09:13:11.71#ibcon#about to read 4, iclass 29, count 0 2006.285.09:13:11.71#ibcon#read 4, iclass 29, count 0 2006.285.09:13:11.71#ibcon#about to read 5, iclass 29, count 0 2006.285.09:13:11.71#ibcon#read 5, iclass 29, count 0 2006.285.09:13:11.71#ibcon#about to read 6, iclass 29, count 0 2006.285.09:13:11.71#ibcon#read 6, iclass 29, count 0 2006.285.09:13:11.71#ibcon#end of sib2, iclass 29, count 0 2006.285.09:13:11.71#ibcon#*mode == 0, iclass 29, count 0 2006.285.09:13:11.71#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.09:13:11.71#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:13:11.71#ibcon#*before write, iclass 29, count 0 2006.285.09:13:11.71#ibcon#enter sib2, iclass 29, count 0 2006.285.09:13:11.71#ibcon#flushed, iclass 29, count 0 2006.285.09:13:11.71#ibcon#about to write, iclass 29, count 0 2006.285.09:13:11.71#ibcon#wrote, iclass 29, count 0 2006.285.09:13:11.71#ibcon#about to read 3, iclass 29, count 0 2006.285.09:13:11.75#ibcon#read 3, iclass 29, count 0 2006.285.09:13:11.75#ibcon#about to read 4, iclass 29, count 0 2006.285.09:13:11.75#ibcon#read 4, iclass 29, count 0 2006.285.09:13:11.75#ibcon#about to read 5, iclass 29, count 0 2006.285.09:13:11.75#ibcon#read 5, iclass 29, count 0 2006.285.09:13:11.75#ibcon#about to read 6, iclass 29, count 0 2006.285.09:13:11.75#ibcon#read 6, iclass 29, count 0 2006.285.09:13:11.75#ibcon#end of sib2, iclass 29, count 0 2006.285.09:13:11.75#ibcon#*after write, iclass 29, count 0 2006.285.09:13:11.75#ibcon#*before return 0, iclass 29, count 0 2006.285.09:13:11.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:13:11.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:13:11.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.09:13:11.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.09:13:11.75$vck44/va=2,6 2006.285.09:13:11.75#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.09:13:11.75#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.09:13:11.75#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:11.75#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:13:11.81#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:13:11.81#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:13:11.81#ibcon#enter wrdev, iclass 31, count 2 2006.285.09:13:11.81#ibcon#first serial, iclass 31, count 2 2006.285.09:13:11.81#ibcon#enter sib2, iclass 31, count 2 2006.285.09:13:11.81#ibcon#flushed, iclass 31, count 2 2006.285.09:13:11.81#ibcon#about to write, iclass 31, count 2 2006.285.09:13:11.81#ibcon#wrote, iclass 31, count 2 2006.285.09:13:11.81#ibcon#about to read 3, iclass 31, count 2 2006.285.09:13:11.83#ibcon#read 3, iclass 31, count 2 2006.285.09:13:11.83#ibcon#about to read 4, iclass 31, count 2 2006.285.09:13:11.83#ibcon#read 4, iclass 31, count 2 2006.285.09:13:11.83#ibcon#about to read 5, iclass 31, count 2 2006.285.09:13:11.83#ibcon#read 5, iclass 31, count 2 2006.285.09:13:11.83#ibcon#about to read 6, iclass 31, count 2 2006.285.09:13:11.83#ibcon#read 6, iclass 31, count 2 2006.285.09:13:11.83#ibcon#end of sib2, iclass 31, count 2 2006.285.09:13:11.83#ibcon#*mode == 0, iclass 31, count 2 2006.285.09:13:11.83#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.09:13:11.83#ibcon#[25=AT02-06\r\n] 2006.285.09:13:11.83#ibcon#*before write, iclass 31, count 2 2006.285.09:13:11.83#ibcon#enter sib2, iclass 31, count 2 2006.285.09:13:11.83#ibcon#flushed, iclass 31, count 2 2006.285.09:13:11.83#ibcon#about to write, iclass 31, count 2 2006.285.09:13:11.83#ibcon#wrote, iclass 31, count 2 2006.285.09:13:11.83#ibcon#about to read 3, iclass 31, count 2 2006.285.09:13:11.86#ibcon#read 3, iclass 31, count 2 2006.285.09:13:11.86#ibcon#about to read 4, iclass 31, count 2 2006.285.09:13:11.86#ibcon#read 4, iclass 31, count 2 2006.285.09:13:11.86#ibcon#about to read 5, iclass 31, count 2 2006.285.09:13:11.86#ibcon#read 5, iclass 31, count 2 2006.285.09:13:11.86#ibcon#about to read 6, iclass 31, count 2 2006.285.09:13:11.86#ibcon#read 6, iclass 31, count 2 2006.285.09:13:11.86#ibcon#end of sib2, iclass 31, count 2 2006.285.09:13:11.86#ibcon#*after write, iclass 31, count 2 2006.285.09:13:11.86#ibcon#*before return 0, iclass 31, count 2 2006.285.09:13:11.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:13:11.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:13:11.86#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.09:13:11.86#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:11.86#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:13:11.98#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:13:11.98#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:13:11.98#ibcon#enter wrdev, iclass 31, count 0 2006.285.09:13:11.98#ibcon#first serial, iclass 31, count 0 2006.285.09:13:11.98#ibcon#enter sib2, iclass 31, count 0 2006.285.09:13:11.98#ibcon#flushed, iclass 31, count 0 2006.285.09:13:11.98#ibcon#about to write, iclass 31, count 0 2006.285.09:13:11.98#ibcon#wrote, iclass 31, count 0 2006.285.09:13:11.98#ibcon#about to read 3, iclass 31, count 0 2006.285.09:13:12.00#ibcon#read 3, iclass 31, count 0 2006.285.09:13:12.00#ibcon#about to read 4, iclass 31, count 0 2006.285.09:13:12.00#ibcon#read 4, iclass 31, count 0 2006.285.09:13:12.00#ibcon#about to read 5, iclass 31, count 0 2006.285.09:13:12.00#ibcon#read 5, iclass 31, count 0 2006.285.09:13:12.00#ibcon#about to read 6, iclass 31, count 0 2006.285.09:13:12.00#ibcon#read 6, iclass 31, count 0 2006.285.09:13:12.00#ibcon#end of sib2, iclass 31, count 0 2006.285.09:13:12.00#ibcon#*mode == 0, iclass 31, count 0 2006.285.09:13:12.00#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.09:13:12.00#ibcon#[25=USB\r\n] 2006.285.09:13:12.00#ibcon#*before write, iclass 31, count 0 2006.285.09:13:12.00#ibcon#enter sib2, iclass 31, count 0 2006.285.09:13:12.00#ibcon#flushed, iclass 31, count 0 2006.285.09:13:12.00#ibcon#about to write, iclass 31, count 0 2006.285.09:13:12.00#ibcon#wrote, iclass 31, count 0 2006.285.09:13:12.00#ibcon#about to read 3, iclass 31, count 0 2006.285.09:13:12.03#ibcon#read 3, iclass 31, count 0 2006.285.09:13:12.03#ibcon#about to read 4, iclass 31, count 0 2006.285.09:13:12.03#ibcon#read 4, iclass 31, count 0 2006.285.09:13:12.03#ibcon#about to read 5, iclass 31, count 0 2006.285.09:13:12.03#ibcon#read 5, iclass 31, count 0 2006.285.09:13:12.03#ibcon#about to read 6, iclass 31, count 0 2006.285.09:13:12.03#ibcon#read 6, iclass 31, count 0 2006.285.09:13:12.03#ibcon#end of sib2, iclass 31, count 0 2006.285.09:13:12.03#ibcon#*after write, iclass 31, count 0 2006.285.09:13:12.03#ibcon#*before return 0, iclass 31, count 0 2006.285.09:13:12.03#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:13:12.03#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:13:12.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.09:13:12.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.09:13:12.03$vck44/valo=3,564.99 2006.285.09:13:12.03#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.09:13:12.03#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.09:13:12.03#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:12.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:13:12.03#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:13:12.03#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:13:12.03#ibcon#enter wrdev, iclass 33, count 0 2006.285.09:13:12.03#ibcon#first serial, iclass 33, count 0 2006.285.09:13:12.03#ibcon#enter sib2, iclass 33, count 0 2006.285.09:13:12.03#ibcon#flushed, iclass 33, count 0 2006.285.09:13:12.03#ibcon#about to write, iclass 33, count 0 2006.285.09:13:12.03#ibcon#wrote, iclass 33, count 0 2006.285.09:13:12.03#ibcon#about to read 3, iclass 33, count 0 2006.285.09:13:12.05#ibcon#read 3, iclass 33, count 0 2006.285.09:13:12.05#ibcon#about to read 4, iclass 33, count 0 2006.285.09:13:12.05#ibcon#read 4, iclass 33, count 0 2006.285.09:13:12.05#ibcon#about to read 5, iclass 33, count 0 2006.285.09:13:12.05#ibcon#read 5, iclass 33, count 0 2006.285.09:13:12.05#ibcon#about to read 6, iclass 33, count 0 2006.285.09:13:12.05#ibcon#read 6, iclass 33, count 0 2006.285.09:13:12.05#ibcon#end of sib2, iclass 33, count 0 2006.285.09:13:12.05#ibcon#*mode == 0, iclass 33, count 0 2006.285.09:13:12.05#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.09:13:12.05#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:13:12.05#ibcon#*before write, iclass 33, count 0 2006.285.09:13:12.05#ibcon#enter sib2, iclass 33, count 0 2006.285.09:13:12.05#ibcon#flushed, iclass 33, count 0 2006.285.09:13:12.05#ibcon#about to write, iclass 33, count 0 2006.285.09:13:12.05#ibcon#wrote, iclass 33, count 0 2006.285.09:13:12.05#ibcon#about to read 3, iclass 33, count 0 2006.285.09:13:12.09#ibcon#read 3, iclass 33, count 0 2006.285.09:13:12.09#ibcon#about to read 4, iclass 33, count 0 2006.285.09:13:12.09#ibcon#read 4, iclass 33, count 0 2006.285.09:13:12.09#ibcon#about to read 5, iclass 33, count 0 2006.285.09:13:12.09#ibcon#read 5, iclass 33, count 0 2006.285.09:13:12.09#ibcon#about to read 6, iclass 33, count 0 2006.285.09:13:12.09#ibcon#read 6, iclass 33, count 0 2006.285.09:13:12.09#ibcon#end of sib2, iclass 33, count 0 2006.285.09:13:12.09#ibcon#*after write, iclass 33, count 0 2006.285.09:13:12.09#ibcon#*before return 0, iclass 33, count 0 2006.285.09:13:12.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:13:12.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:13:12.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.09:13:12.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.09:13:12.09$vck44/va=3,7 2006.285.09:13:12.09#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.09:13:12.09#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.09:13:12.09#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:12.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:13:12.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:13:12.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:13:12.15#ibcon#enter wrdev, iclass 35, count 2 2006.285.09:13:12.15#ibcon#first serial, iclass 35, count 2 2006.285.09:13:12.15#ibcon#enter sib2, iclass 35, count 2 2006.285.09:13:12.15#ibcon#flushed, iclass 35, count 2 2006.285.09:13:12.15#ibcon#about to write, iclass 35, count 2 2006.285.09:13:12.15#ibcon#wrote, iclass 35, count 2 2006.285.09:13:12.15#ibcon#about to read 3, iclass 35, count 2 2006.285.09:13:12.17#ibcon#read 3, iclass 35, count 2 2006.285.09:13:12.17#ibcon#about to read 4, iclass 35, count 2 2006.285.09:13:12.17#ibcon#read 4, iclass 35, count 2 2006.285.09:13:12.17#ibcon#about to read 5, iclass 35, count 2 2006.285.09:13:12.17#ibcon#read 5, iclass 35, count 2 2006.285.09:13:12.17#ibcon#about to read 6, iclass 35, count 2 2006.285.09:13:12.17#ibcon#read 6, iclass 35, count 2 2006.285.09:13:12.17#ibcon#end of sib2, iclass 35, count 2 2006.285.09:13:12.17#ibcon#*mode == 0, iclass 35, count 2 2006.285.09:13:12.17#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.09:13:12.17#ibcon#[25=AT03-07\r\n] 2006.285.09:13:12.17#ibcon#*before write, iclass 35, count 2 2006.285.09:13:12.17#ibcon#enter sib2, iclass 35, count 2 2006.285.09:13:12.17#ibcon#flushed, iclass 35, count 2 2006.285.09:13:12.17#ibcon#about to write, iclass 35, count 2 2006.285.09:13:12.17#ibcon#wrote, iclass 35, count 2 2006.285.09:13:12.17#ibcon#about to read 3, iclass 35, count 2 2006.285.09:13:12.20#ibcon#read 3, iclass 35, count 2 2006.285.09:13:12.20#ibcon#about to read 4, iclass 35, count 2 2006.285.09:13:12.20#ibcon#read 4, iclass 35, count 2 2006.285.09:13:12.20#ibcon#about to read 5, iclass 35, count 2 2006.285.09:13:12.20#ibcon#read 5, iclass 35, count 2 2006.285.09:13:12.20#ibcon#about to read 6, iclass 35, count 2 2006.285.09:13:12.20#ibcon#read 6, iclass 35, count 2 2006.285.09:13:12.20#ibcon#end of sib2, iclass 35, count 2 2006.285.09:13:12.20#ibcon#*after write, iclass 35, count 2 2006.285.09:13:12.20#ibcon#*before return 0, iclass 35, count 2 2006.285.09:13:12.20#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:13:12.20#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:13:12.20#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.09:13:12.20#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:12.20#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:13:12.32#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:13:12.32#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:13:12.32#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:13:12.32#ibcon#first serial, iclass 35, count 0 2006.285.09:13:12.32#ibcon#enter sib2, iclass 35, count 0 2006.285.09:13:12.32#ibcon#flushed, iclass 35, count 0 2006.285.09:13:12.32#ibcon#about to write, iclass 35, count 0 2006.285.09:13:12.32#ibcon#wrote, iclass 35, count 0 2006.285.09:13:12.32#ibcon#about to read 3, iclass 35, count 0 2006.285.09:13:12.34#ibcon#read 3, iclass 35, count 0 2006.285.09:13:12.34#ibcon#about to read 4, iclass 35, count 0 2006.285.09:13:12.34#ibcon#read 4, iclass 35, count 0 2006.285.09:13:12.34#ibcon#about to read 5, iclass 35, count 0 2006.285.09:13:12.34#ibcon#read 5, iclass 35, count 0 2006.285.09:13:12.34#ibcon#about to read 6, iclass 35, count 0 2006.285.09:13:12.34#ibcon#read 6, iclass 35, count 0 2006.285.09:13:12.34#ibcon#end of sib2, iclass 35, count 0 2006.285.09:13:12.34#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:13:12.34#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:13:12.34#ibcon#[25=USB\r\n] 2006.285.09:13:12.34#ibcon#*before write, iclass 35, count 0 2006.285.09:13:12.34#ibcon#enter sib2, iclass 35, count 0 2006.285.09:13:12.34#ibcon#flushed, iclass 35, count 0 2006.285.09:13:12.34#ibcon#about to write, iclass 35, count 0 2006.285.09:13:12.34#ibcon#wrote, iclass 35, count 0 2006.285.09:13:12.34#ibcon#about to read 3, iclass 35, count 0 2006.285.09:13:12.37#ibcon#read 3, iclass 35, count 0 2006.285.09:13:12.37#ibcon#about to read 4, iclass 35, count 0 2006.285.09:13:12.37#ibcon#read 4, iclass 35, count 0 2006.285.09:13:12.37#ibcon#about to read 5, iclass 35, count 0 2006.285.09:13:12.37#ibcon#read 5, iclass 35, count 0 2006.285.09:13:12.37#ibcon#about to read 6, iclass 35, count 0 2006.285.09:13:12.37#ibcon#read 6, iclass 35, count 0 2006.285.09:13:12.37#ibcon#end of sib2, iclass 35, count 0 2006.285.09:13:12.37#ibcon#*after write, iclass 35, count 0 2006.285.09:13:12.37#ibcon#*before return 0, iclass 35, count 0 2006.285.09:13:12.37#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:13:12.37#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:13:12.37#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:13:12.37#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:13:12.37$vck44/valo=4,624.99 2006.285.09:13:12.37#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.09:13:12.37#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.09:13:12.37#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:12.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:13:12.37#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:13:12.37#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:13:12.37#ibcon#enter wrdev, iclass 37, count 0 2006.285.09:13:12.37#ibcon#first serial, iclass 37, count 0 2006.285.09:13:12.37#ibcon#enter sib2, iclass 37, count 0 2006.285.09:13:12.37#ibcon#flushed, iclass 37, count 0 2006.285.09:13:12.37#ibcon#about to write, iclass 37, count 0 2006.285.09:13:12.37#ibcon#wrote, iclass 37, count 0 2006.285.09:13:12.37#ibcon#about to read 3, iclass 37, count 0 2006.285.09:13:12.39#ibcon#read 3, iclass 37, count 0 2006.285.09:13:12.39#ibcon#about to read 4, iclass 37, count 0 2006.285.09:13:12.39#ibcon#read 4, iclass 37, count 0 2006.285.09:13:12.39#ibcon#about to read 5, iclass 37, count 0 2006.285.09:13:12.39#ibcon#read 5, iclass 37, count 0 2006.285.09:13:12.39#ibcon#about to read 6, iclass 37, count 0 2006.285.09:13:12.39#ibcon#read 6, iclass 37, count 0 2006.285.09:13:12.39#ibcon#end of sib2, iclass 37, count 0 2006.285.09:13:12.39#ibcon#*mode == 0, iclass 37, count 0 2006.285.09:13:12.39#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.09:13:12.39#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:13:12.39#ibcon#*before write, iclass 37, count 0 2006.285.09:13:12.39#ibcon#enter sib2, iclass 37, count 0 2006.285.09:13:12.39#ibcon#flushed, iclass 37, count 0 2006.285.09:13:12.39#ibcon#about to write, iclass 37, count 0 2006.285.09:13:12.39#ibcon#wrote, iclass 37, count 0 2006.285.09:13:12.39#ibcon#about to read 3, iclass 37, count 0 2006.285.09:13:12.43#ibcon#read 3, iclass 37, count 0 2006.285.09:13:12.43#ibcon#about to read 4, iclass 37, count 0 2006.285.09:13:12.43#ibcon#read 4, iclass 37, count 0 2006.285.09:13:12.43#ibcon#about to read 5, iclass 37, count 0 2006.285.09:13:12.43#ibcon#read 5, iclass 37, count 0 2006.285.09:13:12.43#ibcon#about to read 6, iclass 37, count 0 2006.285.09:13:12.43#ibcon#read 6, iclass 37, count 0 2006.285.09:13:12.43#ibcon#end of sib2, iclass 37, count 0 2006.285.09:13:12.43#ibcon#*after write, iclass 37, count 0 2006.285.09:13:12.43#ibcon#*before return 0, iclass 37, count 0 2006.285.09:13:12.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:13:12.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:13:12.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.09:13:12.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.09:13:12.43$vck44/va=4,6 2006.285.09:13:12.43#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.09:13:12.43#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.09:13:12.43#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:12.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:13:12.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:13:12.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:13:12.49#ibcon#enter wrdev, iclass 39, count 2 2006.285.09:13:12.49#ibcon#first serial, iclass 39, count 2 2006.285.09:13:12.49#ibcon#enter sib2, iclass 39, count 2 2006.285.09:13:12.49#ibcon#flushed, iclass 39, count 2 2006.285.09:13:12.49#ibcon#about to write, iclass 39, count 2 2006.285.09:13:12.49#ibcon#wrote, iclass 39, count 2 2006.285.09:13:12.49#ibcon#about to read 3, iclass 39, count 2 2006.285.09:13:12.51#ibcon#read 3, iclass 39, count 2 2006.285.09:13:12.51#ibcon#about to read 4, iclass 39, count 2 2006.285.09:13:12.51#ibcon#read 4, iclass 39, count 2 2006.285.09:13:12.51#ibcon#about to read 5, iclass 39, count 2 2006.285.09:13:12.51#ibcon#read 5, iclass 39, count 2 2006.285.09:13:12.51#ibcon#about to read 6, iclass 39, count 2 2006.285.09:13:12.51#ibcon#read 6, iclass 39, count 2 2006.285.09:13:12.51#ibcon#end of sib2, iclass 39, count 2 2006.285.09:13:12.51#ibcon#*mode == 0, iclass 39, count 2 2006.285.09:13:12.51#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.09:13:12.51#ibcon#[25=AT04-06\r\n] 2006.285.09:13:12.51#ibcon#*before write, iclass 39, count 2 2006.285.09:13:12.51#ibcon#enter sib2, iclass 39, count 2 2006.285.09:13:12.51#ibcon#flushed, iclass 39, count 2 2006.285.09:13:12.51#ibcon#about to write, iclass 39, count 2 2006.285.09:13:12.51#ibcon#wrote, iclass 39, count 2 2006.285.09:13:12.51#ibcon#about to read 3, iclass 39, count 2 2006.285.09:13:12.54#ibcon#read 3, iclass 39, count 2 2006.285.09:13:12.54#ibcon#about to read 4, iclass 39, count 2 2006.285.09:13:12.54#ibcon#read 4, iclass 39, count 2 2006.285.09:13:12.54#ibcon#about to read 5, iclass 39, count 2 2006.285.09:13:12.54#ibcon#read 5, iclass 39, count 2 2006.285.09:13:12.54#ibcon#about to read 6, iclass 39, count 2 2006.285.09:13:12.54#ibcon#read 6, iclass 39, count 2 2006.285.09:13:12.54#ibcon#end of sib2, iclass 39, count 2 2006.285.09:13:12.54#ibcon#*after write, iclass 39, count 2 2006.285.09:13:12.54#ibcon#*before return 0, iclass 39, count 2 2006.285.09:13:12.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:13:12.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:13:12.54#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.09:13:12.54#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:12.54#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:13:12.66#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:13:12.66#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:13:12.66#ibcon#enter wrdev, iclass 39, count 0 2006.285.09:13:12.66#ibcon#first serial, iclass 39, count 0 2006.285.09:13:12.66#ibcon#enter sib2, iclass 39, count 0 2006.285.09:13:12.66#ibcon#flushed, iclass 39, count 0 2006.285.09:13:12.66#ibcon#about to write, iclass 39, count 0 2006.285.09:13:12.66#ibcon#wrote, iclass 39, count 0 2006.285.09:13:12.66#ibcon#about to read 3, iclass 39, count 0 2006.285.09:13:12.68#ibcon#read 3, iclass 39, count 0 2006.285.09:13:12.68#ibcon#about to read 4, iclass 39, count 0 2006.285.09:13:12.68#ibcon#read 4, iclass 39, count 0 2006.285.09:13:12.68#ibcon#about to read 5, iclass 39, count 0 2006.285.09:13:12.68#ibcon#read 5, iclass 39, count 0 2006.285.09:13:12.68#ibcon#about to read 6, iclass 39, count 0 2006.285.09:13:12.68#ibcon#read 6, iclass 39, count 0 2006.285.09:13:12.68#ibcon#end of sib2, iclass 39, count 0 2006.285.09:13:12.68#ibcon#*mode == 0, iclass 39, count 0 2006.285.09:13:12.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.09:13:12.68#ibcon#[25=USB\r\n] 2006.285.09:13:12.68#ibcon#*before write, iclass 39, count 0 2006.285.09:13:12.68#ibcon#enter sib2, iclass 39, count 0 2006.285.09:13:12.68#ibcon#flushed, iclass 39, count 0 2006.285.09:13:12.68#ibcon#about to write, iclass 39, count 0 2006.285.09:13:12.68#ibcon#wrote, iclass 39, count 0 2006.285.09:13:12.68#ibcon#about to read 3, iclass 39, count 0 2006.285.09:13:12.71#ibcon#read 3, iclass 39, count 0 2006.285.09:13:12.71#ibcon#about to read 4, iclass 39, count 0 2006.285.09:13:12.71#ibcon#read 4, iclass 39, count 0 2006.285.09:13:12.71#ibcon#about to read 5, iclass 39, count 0 2006.285.09:13:12.71#ibcon#read 5, iclass 39, count 0 2006.285.09:13:12.71#ibcon#about to read 6, iclass 39, count 0 2006.285.09:13:12.71#ibcon#read 6, iclass 39, count 0 2006.285.09:13:12.71#ibcon#end of sib2, iclass 39, count 0 2006.285.09:13:12.71#ibcon#*after write, iclass 39, count 0 2006.285.09:13:12.71#ibcon#*before return 0, iclass 39, count 0 2006.285.09:13:12.71#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:13:12.71#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:13:12.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.09:13:12.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.09:13:12.71$vck44/valo=5,734.99 2006.285.09:13:12.71#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.09:13:12.71#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.09:13:12.71#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:12.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:13:12.71#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:13:12.71#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:13:12.71#ibcon#enter wrdev, iclass 3, count 0 2006.285.09:13:12.71#ibcon#first serial, iclass 3, count 0 2006.285.09:13:12.71#ibcon#enter sib2, iclass 3, count 0 2006.285.09:13:12.71#ibcon#flushed, iclass 3, count 0 2006.285.09:13:12.71#ibcon#about to write, iclass 3, count 0 2006.285.09:13:12.71#ibcon#wrote, iclass 3, count 0 2006.285.09:13:12.71#ibcon#about to read 3, iclass 3, count 0 2006.285.09:13:12.73#ibcon#read 3, iclass 3, count 0 2006.285.09:13:12.73#ibcon#about to read 4, iclass 3, count 0 2006.285.09:13:12.73#ibcon#read 4, iclass 3, count 0 2006.285.09:13:12.73#ibcon#about to read 5, iclass 3, count 0 2006.285.09:13:12.73#ibcon#read 5, iclass 3, count 0 2006.285.09:13:12.73#ibcon#about to read 6, iclass 3, count 0 2006.285.09:13:12.73#ibcon#read 6, iclass 3, count 0 2006.285.09:13:12.73#ibcon#end of sib2, iclass 3, count 0 2006.285.09:13:12.73#ibcon#*mode == 0, iclass 3, count 0 2006.285.09:13:12.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.09:13:12.73#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:13:12.73#ibcon#*before write, iclass 3, count 0 2006.285.09:13:12.73#ibcon#enter sib2, iclass 3, count 0 2006.285.09:13:12.73#ibcon#flushed, iclass 3, count 0 2006.285.09:13:12.73#ibcon#about to write, iclass 3, count 0 2006.285.09:13:12.73#ibcon#wrote, iclass 3, count 0 2006.285.09:13:12.73#ibcon#about to read 3, iclass 3, count 0 2006.285.09:13:12.77#ibcon#read 3, iclass 3, count 0 2006.285.09:13:12.77#ibcon#about to read 4, iclass 3, count 0 2006.285.09:13:12.77#ibcon#read 4, iclass 3, count 0 2006.285.09:13:12.77#ibcon#about to read 5, iclass 3, count 0 2006.285.09:13:12.77#ibcon#read 5, iclass 3, count 0 2006.285.09:13:12.77#ibcon#about to read 6, iclass 3, count 0 2006.285.09:13:12.77#ibcon#read 6, iclass 3, count 0 2006.285.09:13:12.77#ibcon#end of sib2, iclass 3, count 0 2006.285.09:13:12.77#ibcon#*after write, iclass 3, count 0 2006.285.09:13:12.77#ibcon#*before return 0, iclass 3, count 0 2006.285.09:13:12.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:13:12.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:13:12.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.09:13:12.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.09:13:12.77$vck44/va=5,3 2006.285.09:13:12.77#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.09:13:12.77#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.09:13:12.77#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:12.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:13:12.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:13:12.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:13:12.83#ibcon#enter wrdev, iclass 5, count 2 2006.285.09:13:12.83#ibcon#first serial, iclass 5, count 2 2006.285.09:13:12.83#ibcon#enter sib2, iclass 5, count 2 2006.285.09:13:12.83#ibcon#flushed, iclass 5, count 2 2006.285.09:13:12.83#ibcon#about to write, iclass 5, count 2 2006.285.09:13:12.83#ibcon#wrote, iclass 5, count 2 2006.285.09:13:12.83#ibcon#about to read 3, iclass 5, count 2 2006.285.09:13:12.85#ibcon#read 3, iclass 5, count 2 2006.285.09:13:12.85#ibcon#about to read 4, iclass 5, count 2 2006.285.09:13:12.85#ibcon#read 4, iclass 5, count 2 2006.285.09:13:12.85#ibcon#about to read 5, iclass 5, count 2 2006.285.09:13:12.85#ibcon#read 5, iclass 5, count 2 2006.285.09:13:12.85#ibcon#about to read 6, iclass 5, count 2 2006.285.09:13:12.85#ibcon#read 6, iclass 5, count 2 2006.285.09:13:12.85#ibcon#end of sib2, iclass 5, count 2 2006.285.09:13:12.85#ibcon#*mode == 0, iclass 5, count 2 2006.285.09:13:12.85#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.09:13:12.85#ibcon#[25=AT05-03\r\n] 2006.285.09:13:12.85#ibcon#*before write, iclass 5, count 2 2006.285.09:13:12.85#ibcon#enter sib2, iclass 5, count 2 2006.285.09:13:12.85#ibcon#flushed, iclass 5, count 2 2006.285.09:13:12.85#ibcon#about to write, iclass 5, count 2 2006.285.09:13:12.85#ibcon#wrote, iclass 5, count 2 2006.285.09:13:12.85#ibcon#about to read 3, iclass 5, count 2 2006.285.09:13:12.88#ibcon#read 3, iclass 5, count 2 2006.285.09:13:12.88#ibcon#about to read 4, iclass 5, count 2 2006.285.09:13:12.88#ibcon#read 4, iclass 5, count 2 2006.285.09:13:12.88#ibcon#about to read 5, iclass 5, count 2 2006.285.09:13:12.88#ibcon#read 5, iclass 5, count 2 2006.285.09:13:12.88#ibcon#about to read 6, iclass 5, count 2 2006.285.09:13:12.88#ibcon#read 6, iclass 5, count 2 2006.285.09:13:12.88#ibcon#end of sib2, iclass 5, count 2 2006.285.09:13:12.88#ibcon#*after write, iclass 5, count 2 2006.285.09:13:12.88#ibcon#*before return 0, iclass 5, count 2 2006.285.09:13:12.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:13:12.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:13:12.88#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.09:13:12.88#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:12.88#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:13:13.00#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:13:13.00#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:13:13.00#ibcon#enter wrdev, iclass 5, count 0 2006.285.09:13:13.00#ibcon#first serial, iclass 5, count 0 2006.285.09:13:13.00#ibcon#enter sib2, iclass 5, count 0 2006.285.09:13:13.00#ibcon#flushed, iclass 5, count 0 2006.285.09:13:13.00#ibcon#about to write, iclass 5, count 0 2006.285.09:13:13.00#ibcon#wrote, iclass 5, count 0 2006.285.09:13:13.00#ibcon#about to read 3, iclass 5, count 0 2006.285.09:13:13.02#ibcon#read 3, iclass 5, count 0 2006.285.09:13:13.02#ibcon#about to read 4, iclass 5, count 0 2006.285.09:13:13.02#ibcon#read 4, iclass 5, count 0 2006.285.09:13:13.02#ibcon#about to read 5, iclass 5, count 0 2006.285.09:13:13.02#ibcon#read 5, iclass 5, count 0 2006.285.09:13:13.02#ibcon#about to read 6, iclass 5, count 0 2006.285.09:13:13.02#ibcon#read 6, iclass 5, count 0 2006.285.09:13:13.02#ibcon#end of sib2, iclass 5, count 0 2006.285.09:13:13.02#ibcon#*mode == 0, iclass 5, count 0 2006.285.09:13:13.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.09:13:13.02#ibcon#[25=USB\r\n] 2006.285.09:13:13.02#ibcon#*before write, iclass 5, count 0 2006.285.09:13:13.02#ibcon#enter sib2, iclass 5, count 0 2006.285.09:13:13.02#ibcon#flushed, iclass 5, count 0 2006.285.09:13:13.02#ibcon#about to write, iclass 5, count 0 2006.285.09:13:13.02#ibcon#wrote, iclass 5, count 0 2006.285.09:13:13.02#ibcon#about to read 3, iclass 5, count 0 2006.285.09:13:13.05#ibcon#read 3, iclass 5, count 0 2006.285.09:13:13.05#ibcon#about to read 4, iclass 5, count 0 2006.285.09:13:13.05#ibcon#read 4, iclass 5, count 0 2006.285.09:13:13.05#ibcon#about to read 5, iclass 5, count 0 2006.285.09:13:13.05#ibcon#read 5, iclass 5, count 0 2006.285.09:13:13.05#ibcon#about to read 6, iclass 5, count 0 2006.285.09:13:13.05#ibcon#read 6, iclass 5, count 0 2006.285.09:13:13.05#ibcon#end of sib2, iclass 5, count 0 2006.285.09:13:13.05#ibcon#*after write, iclass 5, count 0 2006.285.09:13:13.05#ibcon#*before return 0, iclass 5, count 0 2006.285.09:13:13.05#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:13:13.05#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:13:13.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.09:13:13.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.09:13:13.05$vck44/valo=6,814.99 2006.285.09:13:13.05#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.09:13:13.05#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.09:13:13.05#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:13.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:13:13.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:13:13.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:13:13.05#ibcon#enter wrdev, iclass 7, count 0 2006.285.09:13:13.05#ibcon#first serial, iclass 7, count 0 2006.285.09:13:13.05#ibcon#enter sib2, iclass 7, count 0 2006.285.09:13:13.05#ibcon#flushed, iclass 7, count 0 2006.285.09:13:13.05#ibcon#about to write, iclass 7, count 0 2006.285.09:13:13.05#ibcon#wrote, iclass 7, count 0 2006.285.09:13:13.05#ibcon#about to read 3, iclass 7, count 0 2006.285.09:13:13.07#ibcon#read 3, iclass 7, count 0 2006.285.09:13:13.07#ibcon#about to read 4, iclass 7, count 0 2006.285.09:13:13.07#ibcon#read 4, iclass 7, count 0 2006.285.09:13:13.07#ibcon#about to read 5, iclass 7, count 0 2006.285.09:13:13.07#ibcon#read 5, iclass 7, count 0 2006.285.09:13:13.07#ibcon#about to read 6, iclass 7, count 0 2006.285.09:13:13.07#ibcon#read 6, iclass 7, count 0 2006.285.09:13:13.07#ibcon#end of sib2, iclass 7, count 0 2006.285.09:13:13.07#ibcon#*mode == 0, iclass 7, count 0 2006.285.09:13:13.07#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.09:13:13.07#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:13:13.07#ibcon#*before write, iclass 7, count 0 2006.285.09:13:13.07#ibcon#enter sib2, iclass 7, count 0 2006.285.09:13:13.07#ibcon#flushed, iclass 7, count 0 2006.285.09:13:13.07#ibcon#about to write, iclass 7, count 0 2006.285.09:13:13.07#ibcon#wrote, iclass 7, count 0 2006.285.09:13:13.07#ibcon#about to read 3, iclass 7, count 0 2006.285.09:13:13.11#ibcon#read 3, iclass 7, count 0 2006.285.09:13:13.11#ibcon#about to read 4, iclass 7, count 0 2006.285.09:13:13.11#ibcon#read 4, iclass 7, count 0 2006.285.09:13:13.11#ibcon#about to read 5, iclass 7, count 0 2006.285.09:13:13.11#ibcon#read 5, iclass 7, count 0 2006.285.09:13:13.11#ibcon#about to read 6, iclass 7, count 0 2006.285.09:13:13.11#ibcon#read 6, iclass 7, count 0 2006.285.09:13:13.11#ibcon#end of sib2, iclass 7, count 0 2006.285.09:13:13.11#ibcon#*after write, iclass 7, count 0 2006.285.09:13:13.11#ibcon#*before return 0, iclass 7, count 0 2006.285.09:13:13.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:13:13.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:13:13.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.09:13:13.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.09:13:13.11$vck44/va=6,4 2006.285.09:13:13.11#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.09:13:13.11#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.09:13:13.11#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:13.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:13:13.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:13:13.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:13:13.17#ibcon#enter wrdev, iclass 11, count 2 2006.285.09:13:13.17#ibcon#first serial, iclass 11, count 2 2006.285.09:13:13.17#ibcon#enter sib2, iclass 11, count 2 2006.285.09:13:13.17#ibcon#flushed, iclass 11, count 2 2006.285.09:13:13.17#ibcon#about to write, iclass 11, count 2 2006.285.09:13:13.17#ibcon#wrote, iclass 11, count 2 2006.285.09:13:13.17#ibcon#about to read 3, iclass 11, count 2 2006.285.09:13:13.19#ibcon#read 3, iclass 11, count 2 2006.285.09:13:13.19#ibcon#about to read 4, iclass 11, count 2 2006.285.09:13:13.19#ibcon#read 4, iclass 11, count 2 2006.285.09:13:13.19#ibcon#about to read 5, iclass 11, count 2 2006.285.09:13:13.19#ibcon#read 5, iclass 11, count 2 2006.285.09:13:13.19#ibcon#about to read 6, iclass 11, count 2 2006.285.09:13:13.19#ibcon#read 6, iclass 11, count 2 2006.285.09:13:13.19#ibcon#end of sib2, iclass 11, count 2 2006.285.09:13:13.19#ibcon#*mode == 0, iclass 11, count 2 2006.285.09:13:13.19#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.09:13:13.19#ibcon#[25=AT06-04\r\n] 2006.285.09:13:13.19#ibcon#*before write, iclass 11, count 2 2006.285.09:13:13.19#ibcon#enter sib2, iclass 11, count 2 2006.285.09:13:13.19#ibcon#flushed, iclass 11, count 2 2006.285.09:13:13.19#ibcon#about to write, iclass 11, count 2 2006.285.09:13:13.19#ibcon#wrote, iclass 11, count 2 2006.285.09:13:13.19#ibcon#about to read 3, iclass 11, count 2 2006.285.09:13:13.22#ibcon#read 3, iclass 11, count 2 2006.285.09:13:13.22#ibcon#about to read 4, iclass 11, count 2 2006.285.09:13:13.22#ibcon#read 4, iclass 11, count 2 2006.285.09:13:13.22#ibcon#about to read 5, iclass 11, count 2 2006.285.09:13:13.22#ibcon#read 5, iclass 11, count 2 2006.285.09:13:13.22#ibcon#about to read 6, iclass 11, count 2 2006.285.09:13:13.22#ibcon#read 6, iclass 11, count 2 2006.285.09:13:13.22#ibcon#end of sib2, iclass 11, count 2 2006.285.09:13:13.22#ibcon#*after write, iclass 11, count 2 2006.285.09:13:13.22#ibcon#*before return 0, iclass 11, count 2 2006.285.09:13:13.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:13:13.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:13:13.22#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.09:13:13.22#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:13.22#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:13:13.34#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:13:13.34#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:13:13.34#ibcon#enter wrdev, iclass 11, count 0 2006.285.09:13:13.34#ibcon#first serial, iclass 11, count 0 2006.285.09:13:13.34#ibcon#enter sib2, iclass 11, count 0 2006.285.09:13:13.34#ibcon#flushed, iclass 11, count 0 2006.285.09:13:13.34#ibcon#about to write, iclass 11, count 0 2006.285.09:13:13.34#ibcon#wrote, iclass 11, count 0 2006.285.09:13:13.34#ibcon#about to read 3, iclass 11, count 0 2006.285.09:13:13.36#ibcon#read 3, iclass 11, count 0 2006.285.09:13:13.36#ibcon#about to read 4, iclass 11, count 0 2006.285.09:13:13.36#ibcon#read 4, iclass 11, count 0 2006.285.09:13:13.36#ibcon#about to read 5, iclass 11, count 0 2006.285.09:13:13.36#ibcon#read 5, iclass 11, count 0 2006.285.09:13:13.36#ibcon#about to read 6, iclass 11, count 0 2006.285.09:13:13.36#ibcon#read 6, iclass 11, count 0 2006.285.09:13:13.36#ibcon#end of sib2, iclass 11, count 0 2006.285.09:13:13.36#ibcon#*mode == 0, iclass 11, count 0 2006.285.09:13:13.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.09:13:13.36#ibcon#[25=USB\r\n] 2006.285.09:13:13.36#ibcon#*before write, iclass 11, count 0 2006.285.09:13:13.36#ibcon#enter sib2, iclass 11, count 0 2006.285.09:13:13.36#ibcon#flushed, iclass 11, count 0 2006.285.09:13:13.36#ibcon#about to write, iclass 11, count 0 2006.285.09:13:13.36#ibcon#wrote, iclass 11, count 0 2006.285.09:13:13.36#ibcon#about to read 3, iclass 11, count 0 2006.285.09:13:13.39#ibcon#read 3, iclass 11, count 0 2006.285.09:13:13.39#ibcon#about to read 4, iclass 11, count 0 2006.285.09:13:13.39#ibcon#read 4, iclass 11, count 0 2006.285.09:13:13.39#ibcon#about to read 5, iclass 11, count 0 2006.285.09:13:13.39#ibcon#read 5, iclass 11, count 0 2006.285.09:13:13.39#ibcon#about to read 6, iclass 11, count 0 2006.285.09:13:13.39#ibcon#read 6, iclass 11, count 0 2006.285.09:13:13.39#ibcon#end of sib2, iclass 11, count 0 2006.285.09:13:13.39#ibcon#*after write, iclass 11, count 0 2006.285.09:13:13.39#ibcon#*before return 0, iclass 11, count 0 2006.285.09:13:13.39#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:13:13.39#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:13:13.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.09:13:13.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.09:13:13.39$vck44/valo=7,864.99 2006.285.09:13:13.39#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.09:13:13.39#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.09:13:13.39#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:13.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:13:13.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:13:13.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:13:13.39#ibcon#enter wrdev, iclass 13, count 0 2006.285.09:13:13.39#ibcon#first serial, iclass 13, count 0 2006.285.09:13:13.39#ibcon#enter sib2, iclass 13, count 0 2006.285.09:13:13.39#ibcon#flushed, iclass 13, count 0 2006.285.09:13:13.39#ibcon#about to write, iclass 13, count 0 2006.285.09:13:13.39#ibcon#wrote, iclass 13, count 0 2006.285.09:13:13.39#ibcon#about to read 3, iclass 13, count 0 2006.285.09:13:13.41#ibcon#read 3, iclass 13, count 0 2006.285.09:13:13.41#ibcon#about to read 4, iclass 13, count 0 2006.285.09:13:13.41#ibcon#read 4, iclass 13, count 0 2006.285.09:13:13.41#ibcon#about to read 5, iclass 13, count 0 2006.285.09:13:13.41#ibcon#read 5, iclass 13, count 0 2006.285.09:13:13.41#ibcon#about to read 6, iclass 13, count 0 2006.285.09:13:13.41#ibcon#read 6, iclass 13, count 0 2006.285.09:13:13.41#ibcon#end of sib2, iclass 13, count 0 2006.285.09:13:13.41#ibcon#*mode == 0, iclass 13, count 0 2006.285.09:13:13.41#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.09:13:13.41#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:13:13.41#ibcon#*before write, iclass 13, count 0 2006.285.09:13:13.41#ibcon#enter sib2, iclass 13, count 0 2006.285.09:13:13.41#ibcon#flushed, iclass 13, count 0 2006.285.09:13:13.41#ibcon#about to write, iclass 13, count 0 2006.285.09:13:13.41#ibcon#wrote, iclass 13, count 0 2006.285.09:13:13.41#ibcon#about to read 3, iclass 13, count 0 2006.285.09:13:13.45#ibcon#read 3, iclass 13, count 0 2006.285.09:13:13.45#ibcon#about to read 4, iclass 13, count 0 2006.285.09:13:13.45#ibcon#read 4, iclass 13, count 0 2006.285.09:13:13.45#ibcon#about to read 5, iclass 13, count 0 2006.285.09:13:13.45#ibcon#read 5, iclass 13, count 0 2006.285.09:13:13.45#ibcon#about to read 6, iclass 13, count 0 2006.285.09:13:13.45#ibcon#read 6, iclass 13, count 0 2006.285.09:13:13.45#ibcon#end of sib2, iclass 13, count 0 2006.285.09:13:13.45#ibcon#*after write, iclass 13, count 0 2006.285.09:13:13.45#ibcon#*before return 0, iclass 13, count 0 2006.285.09:13:13.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:13:13.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:13:13.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.09:13:13.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.09:13:13.45$vck44/va=7,4 2006.285.09:13:13.45#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.09:13:13.45#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.09:13:13.45#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:13.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:13:13.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:13:13.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:13:13.51#ibcon#enter wrdev, iclass 15, count 2 2006.285.09:13:13.51#ibcon#first serial, iclass 15, count 2 2006.285.09:13:13.51#ibcon#enter sib2, iclass 15, count 2 2006.285.09:13:13.51#ibcon#flushed, iclass 15, count 2 2006.285.09:13:13.51#ibcon#about to write, iclass 15, count 2 2006.285.09:13:13.51#ibcon#wrote, iclass 15, count 2 2006.285.09:13:13.51#ibcon#about to read 3, iclass 15, count 2 2006.285.09:13:13.53#ibcon#read 3, iclass 15, count 2 2006.285.09:13:13.53#ibcon#about to read 4, iclass 15, count 2 2006.285.09:13:13.53#ibcon#read 4, iclass 15, count 2 2006.285.09:13:13.53#ibcon#about to read 5, iclass 15, count 2 2006.285.09:13:13.53#ibcon#read 5, iclass 15, count 2 2006.285.09:13:13.53#ibcon#about to read 6, iclass 15, count 2 2006.285.09:13:13.53#ibcon#read 6, iclass 15, count 2 2006.285.09:13:13.53#ibcon#end of sib2, iclass 15, count 2 2006.285.09:13:13.53#ibcon#*mode == 0, iclass 15, count 2 2006.285.09:13:13.53#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.09:13:13.53#ibcon#[25=AT07-04\r\n] 2006.285.09:13:13.53#ibcon#*before write, iclass 15, count 2 2006.285.09:13:13.53#ibcon#enter sib2, iclass 15, count 2 2006.285.09:13:13.53#ibcon#flushed, iclass 15, count 2 2006.285.09:13:13.53#ibcon#about to write, iclass 15, count 2 2006.285.09:13:13.53#ibcon#wrote, iclass 15, count 2 2006.285.09:13:13.53#ibcon#about to read 3, iclass 15, count 2 2006.285.09:13:13.56#ibcon#read 3, iclass 15, count 2 2006.285.09:13:13.56#ibcon#about to read 4, iclass 15, count 2 2006.285.09:13:13.56#ibcon#read 4, iclass 15, count 2 2006.285.09:13:13.56#ibcon#about to read 5, iclass 15, count 2 2006.285.09:13:13.56#ibcon#read 5, iclass 15, count 2 2006.285.09:13:13.56#ibcon#about to read 6, iclass 15, count 2 2006.285.09:13:13.56#ibcon#read 6, iclass 15, count 2 2006.285.09:13:13.56#ibcon#end of sib2, iclass 15, count 2 2006.285.09:13:13.56#ibcon#*after write, iclass 15, count 2 2006.285.09:13:13.56#ibcon#*before return 0, iclass 15, count 2 2006.285.09:13:13.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:13:13.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:13:13.56#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.09:13:13.56#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:13.56#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:13:13.68#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:13:13.68#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:13:13.68#ibcon#enter wrdev, iclass 15, count 0 2006.285.09:13:13.68#ibcon#first serial, iclass 15, count 0 2006.285.09:13:13.68#ibcon#enter sib2, iclass 15, count 0 2006.285.09:13:13.68#ibcon#flushed, iclass 15, count 0 2006.285.09:13:13.68#ibcon#about to write, iclass 15, count 0 2006.285.09:13:13.68#ibcon#wrote, iclass 15, count 0 2006.285.09:13:13.68#ibcon#about to read 3, iclass 15, count 0 2006.285.09:13:13.70#ibcon#read 3, iclass 15, count 0 2006.285.09:13:13.70#ibcon#about to read 4, iclass 15, count 0 2006.285.09:13:13.70#ibcon#read 4, iclass 15, count 0 2006.285.09:13:13.70#ibcon#about to read 5, iclass 15, count 0 2006.285.09:13:13.70#ibcon#read 5, iclass 15, count 0 2006.285.09:13:13.70#ibcon#about to read 6, iclass 15, count 0 2006.285.09:13:13.70#ibcon#read 6, iclass 15, count 0 2006.285.09:13:13.70#ibcon#end of sib2, iclass 15, count 0 2006.285.09:13:13.70#ibcon#*mode == 0, iclass 15, count 0 2006.285.09:13:13.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.09:13:13.70#ibcon#[25=USB\r\n] 2006.285.09:13:13.70#ibcon#*before write, iclass 15, count 0 2006.285.09:13:13.70#ibcon#enter sib2, iclass 15, count 0 2006.285.09:13:13.70#ibcon#flushed, iclass 15, count 0 2006.285.09:13:13.70#ibcon#about to write, iclass 15, count 0 2006.285.09:13:13.70#ibcon#wrote, iclass 15, count 0 2006.285.09:13:13.70#ibcon#about to read 3, iclass 15, count 0 2006.285.09:13:13.73#ibcon#read 3, iclass 15, count 0 2006.285.09:13:13.73#ibcon#about to read 4, iclass 15, count 0 2006.285.09:13:13.73#ibcon#read 4, iclass 15, count 0 2006.285.09:13:13.73#ibcon#about to read 5, iclass 15, count 0 2006.285.09:13:13.73#ibcon#read 5, iclass 15, count 0 2006.285.09:13:13.73#ibcon#about to read 6, iclass 15, count 0 2006.285.09:13:13.73#ibcon#read 6, iclass 15, count 0 2006.285.09:13:13.73#ibcon#end of sib2, iclass 15, count 0 2006.285.09:13:13.73#ibcon#*after write, iclass 15, count 0 2006.285.09:13:13.73#ibcon#*before return 0, iclass 15, count 0 2006.285.09:13:13.73#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:13:13.73#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:13:13.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.09:13:13.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.09:13:13.73$vck44/valo=8,884.99 2006.285.09:13:13.73#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.09:13:13.73#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.09:13:13.73#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:13.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:13:13.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:13:13.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:13:13.73#ibcon#enter wrdev, iclass 17, count 0 2006.285.09:13:13.73#ibcon#first serial, iclass 17, count 0 2006.285.09:13:13.73#ibcon#enter sib2, iclass 17, count 0 2006.285.09:13:13.73#ibcon#flushed, iclass 17, count 0 2006.285.09:13:13.73#ibcon#about to write, iclass 17, count 0 2006.285.09:13:13.73#ibcon#wrote, iclass 17, count 0 2006.285.09:13:13.73#ibcon#about to read 3, iclass 17, count 0 2006.285.09:13:13.75#ibcon#read 3, iclass 17, count 0 2006.285.09:13:13.75#ibcon#about to read 4, iclass 17, count 0 2006.285.09:13:13.75#ibcon#read 4, iclass 17, count 0 2006.285.09:13:13.75#ibcon#about to read 5, iclass 17, count 0 2006.285.09:13:13.75#ibcon#read 5, iclass 17, count 0 2006.285.09:13:13.75#ibcon#about to read 6, iclass 17, count 0 2006.285.09:13:13.75#ibcon#read 6, iclass 17, count 0 2006.285.09:13:13.75#ibcon#end of sib2, iclass 17, count 0 2006.285.09:13:13.75#ibcon#*mode == 0, iclass 17, count 0 2006.285.09:13:13.75#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.09:13:13.75#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:13:13.75#ibcon#*before write, iclass 17, count 0 2006.285.09:13:13.75#ibcon#enter sib2, iclass 17, count 0 2006.285.09:13:13.75#ibcon#flushed, iclass 17, count 0 2006.285.09:13:13.75#ibcon#about to write, iclass 17, count 0 2006.285.09:13:13.75#ibcon#wrote, iclass 17, count 0 2006.285.09:13:13.75#ibcon#about to read 3, iclass 17, count 0 2006.285.09:13:13.79#ibcon#read 3, iclass 17, count 0 2006.285.09:13:13.79#ibcon#about to read 4, iclass 17, count 0 2006.285.09:13:13.79#ibcon#read 4, iclass 17, count 0 2006.285.09:13:13.79#ibcon#about to read 5, iclass 17, count 0 2006.285.09:13:13.79#ibcon#read 5, iclass 17, count 0 2006.285.09:13:13.79#ibcon#about to read 6, iclass 17, count 0 2006.285.09:13:13.79#ibcon#read 6, iclass 17, count 0 2006.285.09:13:13.79#ibcon#end of sib2, iclass 17, count 0 2006.285.09:13:13.79#ibcon#*after write, iclass 17, count 0 2006.285.09:13:13.79#ibcon#*before return 0, iclass 17, count 0 2006.285.09:13:13.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:13:13.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:13:13.79#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.09:13:13.79#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.09:13:13.79$vck44/va=8,3 2006.285.09:13:13.79#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.09:13:13.79#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.09:13:13.79#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:13.79#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:13:13.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:13:13.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:13:13.85#ibcon#enter wrdev, iclass 19, count 2 2006.285.09:13:13.85#ibcon#first serial, iclass 19, count 2 2006.285.09:13:13.85#ibcon#enter sib2, iclass 19, count 2 2006.285.09:13:13.85#ibcon#flushed, iclass 19, count 2 2006.285.09:13:13.85#ibcon#about to write, iclass 19, count 2 2006.285.09:13:13.85#ibcon#wrote, iclass 19, count 2 2006.285.09:13:13.85#ibcon#about to read 3, iclass 19, count 2 2006.285.09:13:13.87#ibcon#read 3, iclass 19, count 2 2006.285.09:13:13.87#ibcon#about to read 4, iclass 19, count 2 2006.285.09:13:13.87#ibcon#read 4, iclass 19, count 2 2006.285.09:13:13.87#ibcon#about to read 5, iclass 19, count 2 2006.285.09:13:13.87#ibcon#read 5, iclass 19, count 2 2006.285.09:13:13.87#ibcon#about to read 6, iclass 19, count 2 2006.285.09:13:13.87#ibcon#read 6, iclass 19, count 2 2006.285.09:13:13.87#ibcon#end of sib2, iclass 19, count 2 2006.285.09:13:13.87#ibcon#*mode == 0, iclass 19, count 2 2006.285.09:13:13.87#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.09:13:13.87#ibcon#[25=AT08-03\r\n] 2006.285.09:13:13.87#ibcon#*before write, iclass 19, count 2 2006.285.09:13:13.87#ibcon#enter sib2, iclass 19, count 2 2006.285.09:13:13.87#ibcon#flushed, iclass 19, count 2 2006.285.09:13:13.87#ibcon#about to write, iclass 19, count 2 2006.285.09:13:13.87#ibcon#wrote, iclass 19, count 2 2006.285.09:13:13.87#ibcon#about to read 3, iclass 19, count 2 2006.285.09:13:13.90#ibcon#read 3, iclass 19, count 2 2006.285.09:13:13.90#ibcon#about to read 4, iclass 19, count 2 2006.285.09:13:13.90#ibcon#read 4, iclass 19, count 2 2006.285.09:13:13.90#ibcon#about to read 5, iclass 19, count 2 2006.285.09:13:13.90#ibcon#read 5, iclass 19, count 2 2006.285.09:13:13.90#ibcon#about to read 6, iclass 19, count 2 2006.285.09:13:13.90#ibcon#read 6, iclass 19, count 2 2006.285.09:13:13.90#ibcon#end of sib2, iclass 19, count 2 2006.285.09:13:13.90#ibcon#*after write, iclass 19, count 2 2006.285.09:13:13.90#ibcon#*before return 0, iclass 19, count 2 2006.285.09:13:13.90#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:13:13.90#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:13:13.90#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.09:13:13.90#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:13.90#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:13:14.02#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:13:14.02#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:13:14.02#ibcon#enter wrdev, iclass 19, count 0 2006.285.09:13:14.02#ibcon#first serial, iclass 19, count 0 2006.285.09:13:14.02#ibcon#enter sib2, iclass 19, count 0 2006.285.09:13:14.02#ibcon#flushed, iclass 19, count 0 2006.285.09:13:14.02#ibcon#about to write, iclass 19, count 0 2006.285.09:13:14.02#ibcon#wrote, iclass 19, count 0 2006.285.09:13:14.02#ibcon#about to read 3, iclass 19, count 0 2006.285.09:13:14.04#ibcon#read 3, iclass 19, count 0 2006.285.09:13:14.04#ibcon#about to read 4, iclass 19, count 0 2006.285.09:13:14.04#ibcon#read 4, iclass 19, count 0 2006.285.09:13:14.04#ibcon#about to read 5, iclass 19, count 0 2006.285.09:13:14.04#ibcon#read 5, iclass 19, count 0 2006.285.09:13:14.04#ibcon#about to read 6, iclass 19, count 0 2006.285.09:13:14.04#ibcon#read 6, iclass 19, count 0 2006.285.09:13:14.04#ibcon#end of sib2, iclass 19, count 0 2006.285.09:13:14.04#ibcon#*mode == 0, iclass 19, count 0 2006.285.09:13:14.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.09:13:14.04#ibcon#[25=USB\r\n] 2006.285.09:13:14.04#ibcon#*before write, iclass 19, count 0 2006.285.09:13:14.04#ibcon#enter sib2, iclass 19, count 0 2006.285.09:13:14.04#ibcon#flushed, iclass 19, count 0 2006.285.09:13:14.04#ibcon#about to write, iclass 19, count 0 2006.285.09:13:14.04#ibcon#wrote, iclass 19, count 0 2006.285.09:13:14.04#ibcon#about to read 3, iclass 19, count 0 2006.285.09:13:14.07#ibcon#read 3, iclass 19, count 0 2006.285.09:13:14.07#ibcon#about to read 4, iclass 19, count 0 2006.285.09:13:14.07#ibcon#read 4, iclass 19, count 0 2006.285.09:13:14.07#ibcon#about to read 5, iclass 19, count 0 2006.285.09:13:14.07#ibcon#read 5, iclass 19, count 0 2006.285.09:13:14.07#ibcon#about to read 6, iclass 19, count 0 2006.285.09:13:14.07#ibcon#read 6, iclass 19, count 0 2006.285.09:13:14.07#ibcon#end of sib2, iclass 19, count 0 2006.285.09:13:14.07#ibcon#*after write, iclass 19, count 0 2006.285.09:13:14.07#ibcon#*before return 0, iclass 19, count 0 2006.285.09:13:14.07#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:13:14.07#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:13:14.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.09:13:14.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.09:13:14.07$vck44/vblo=1,629.99 2006.285.09:13:14.07#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.09:13:14.07#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.09:13:14.07#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:14.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:13:14.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:13:14.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:13:14.07#ibcon#enter wrdev, iclass 21, count 0 2006.285.09:13:14.07#ibcon#first serial, iclass 21, count 0 2006.285.09:13:14.07#ibcon#enter sib2, iclass 21, count 0 2006.285.09:13:14.07#ibcon#flushed, iclass 21, count 0 2006.285.09:13:14.07#ibcon#about to write, iclass 21, count 0 2006.285.09:13:14.07#ibcon#wrote, iclass 21, count 0 2006.285.09:13:14.07#ibcon#about to read 3, iclass 21, count 0 2006.285.09:13:14.09#ibcon#read 3, iclass 21, count 0 2006.285.09:13:14.09#ibcon#about to read 4, iclass 21, count 0 2006.285.09:13:14.09#ibcon#read 4, iclass 21, count 0 2006.285.09:13:14.09#ibcon#about to read 5, iclass 21, count 0 2006.285.09:13:14.09#ibcon#read 5, iclass 21, count 0 2006.285.09:13:14.09#ibcon#about to read 6, iclass 21, count 0 2006.285.09:13:14.09#ibcon#read 6, iclass 21, count 0 2006.285.09:13:14.09#ibcon#end of sib2, iclass 21, count 0 2006.285.09:13:14.09#ibcon#*mode == 0, iclass 21, count 0 2006.285.09:13:14.09#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.09:13:14.09#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:13:14.09#ibcon#*before write, iclass 21, count 0 2006.285.09:13:14.09#ibcon#enter sib2, iclass 21, count 0 2006.285.09:13:14.09#ibcon#flushed, iclass 21, count 0 2006.285.09:13:14.09#ibcon#about to write, iclass 21, count 0 2006.285.09:13:14.09#ibcon#wrote, iclass 21, count 0 2006.285.09:13:14.09#ibcon#about to read 3, iclass 21, count 0 2006.285.09:13:14.13#ibcon#read 3, iclass 21, count 0 2006.285.09:13:14.13#ibcon#about to read 4, iclass 21, count 0 2006.285.09:13:14.13#ibcon#read 4, iclass 21, count 0 2006.285.09:13:14.13#ibcon#about to read 5, iclass 21, count 0 2006.285.09:13:14.13#ibcon#read 5, iclass 21, count 0 2006.285.09:13:14.13#ibcon#about to read 6, iclass 21, count 0 2006.285.09:13:14.13#ibcon#read 6, iclass 21, count 0 2006.285.09:13:14.13#ibcon#end of sib2, iclass 21, count 0 2006.285.09:13:14.13#ibcon#*after write, iclass 21, count 0 2006.285.09:13:14.13#ibcon#*before return 0, iclass 21, count 0 2006.285.09:13:14.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:13:14.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:13:14.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.09:13:14.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.09:13:14.13$vck44/vb=1,4 2006.285.09:13:14.13#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.09:13:14.13#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.09:13:14.13#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:14.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:13:14.13#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:13:14.13#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:13:14.13#ibcon#enter wrdev, iclass 23, count 2 2006.285.09:13:14.13#ibcon#first serial, iclass 23, count 2 2006.285.09:13:14.13#ibcon#enter sib2, iclass 23, count 2 2006.285.09:13:14.13#ibcon#flushed, iclass 23, count 2 2006.285.09:13:14.13#ibcon#about to write, iclass 23, count 2 2006.285.09:13:14.13#ibcon#wrote, iclass 23, count 2 2006.285.09:13:14.13#ibcon#about to read 3, iclass 23, count 2 2006.285.09:13:14.15#ibcon#read 3, iclass 23, count 2 2006.285.09:13:14.15#ibcon#about to read 4, iclass 23, count 2 2006.285.09:13:14.15#ibcon#read 4, iclass 23, count 2 2006.285.09:13:14.15#ibcon#about to read 5, iclass 23, count 2 2006.285.09:13:14.15#ibcon#read 5, iclass 23, count 2 2006.285.09:13:14.15#ibcon#about to read 6, iclass 23, count 2 2006.285.09:13:14.15#ibcon#read 6, iclass 23, count 2 2006.285.09:13:14.15#ibcon#end of sib2, iclass 23, count 2 2006.285.09:13:14.15#ibcon#*mode == 0, iclass 23, count 2 2006.285.09:13:14.15#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.09:13:14.15#ibcon#[27=AT01-04\r\n] 2006.285.09:13:14.15#ibcon#*before write, iclass 23, count 2 2006.285.09:13:14.15#ibcon#enter sib2, iclass 23, count 2 2006.285.09:13:14.15#ibcon#flushed, iclass 23, count 2 2006.285.09:13:14.15#ibcon#about to write, iclass 23, count 2 2006.285.09:13:14.15#ibcon#wrote, iclass 23, count 2 2006.285.09:13:14.15#ibcon#about to read 3, iclass 23, count 2 2006.285.09:13:14.18#ibcon#read 3, iclass 23, count 2 2006.285.09:13:14.18#ibcon#about to read 4, iclass 23, count 2 2006.285.09:13:14.18#ibcon#read 4, iclass 23, count 2 2006.285.09:13:14.18#ibcon#about to read 5, iclass 23, count 2 2006.285.09:13:14.18#ibcon#read 5, iclass 23, count 2 2006.285.09:13:14.18#ibcon#about to read 6, iclass 23, count 2 2006.285.09:13:14.18#ibcon#read 6, iclass 23, count 2 2006.285.09:13:14.18#ibcon#end of sib2, iclass 23, count 2 2006.285.09:13:14.18#ibcon#*after write, iclass 23, count 2 2006.285.09:13:14.18#ibcon#*before return 0, iclass 23, count 2 2006.285.09:13:14.18#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:13:14.18#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:13:14.18#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.09:13:14.18#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:14.18#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:13:14.30#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:13:14.30#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:13:14.30#ibcon#enter wrdev, iclass 23, count 0 2006.285.09:13:14.30#ibcon#first serial, iclass 23, count 0 2006.285.09:13:14.30#ibcon#enter sib2, iclass 23, count 0 2006.285.09:13:14.30#ibcon#flushed, iclass 23, count 0 2006.285.09:13:14.30#ibcon#about to write, iclass 23, count 0 2006.285.09:13:14.30#ibcon#wrote, iclass 23, count 0 2006.285.09:13:14.30#ibcon#about to read 3, iclass 23, count 0 2006.285.09:13:14.32#ibcon#read 3, iclass 23, count 0 2006.285.09:13:14.32#ibcon#about to read 4, iclass 23, count 0 2006.285.09:13:14.32#ibcon#read 4, iclass 23, count 0 2006.285.09:13:14.32#ibcon#about to read 5, iclass 23, count 0 2006.285.09:13:14.32#ibcon#read 5, iclass 23, count 0 2006.285.09:13:14.32#ibcon#about to read 6, iclass 23, count 0 2006.285.09:13:14.32#ibcon#read 6, iclass 23, count 0 2006.285.09:13:14.32#ibcon#end of sib2, iclass 23, count 0 2006.285.09:13:14.32#ibcon#*mode == 0, iclass 23, count 0 2006.285.09:13:14.32#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.09:13:14.32#ibcon#[27=USB\r\n] 2006.285.09:13:14.32#ibcon#*before write, iclass 23, count 0 2006.285.09:13:14.32#ibcon#enter sib2, iclass 23, count 0 2006.285.09:13:14.32#ibcon#flushed, iclass 23, count 0 2006.285.09:13:14.32#ibcon#about to write, iclass 23, count 0 2006.285.09:13:14.32#ibcon#wrote, iclass 23, count 0 2006.285.09:13:14.32#ibcon#about to read 3, iclass 23, count 0 2006.285.09:13:14.35#ibcon#read 3, iclass 23, count 0 2006.285.09:13:14.35#ibcon#about to read 4, iclass 23, count 0 2006.285.09:13:14.35#ibcon#read 4, iclass 23, count 0 2006.285.09:13:14.35#ibcon#about to read 5, iclass 23, count 0 2006.285.09:13:14.35#ibcon#read 5, iclass 23, count 0 2006.285.09:13:14.35#ibcon#about to read 6, iclass 23, count 0 2006.285.09:13:14.35#ibcon#read 6, iclass 23, count 0 2006.285.09:13:14.35#ibcon#end of sib2, iclass 23, count 0 2006.285.09:13:14.35#ibcon#*after write, iclass 23, count 0 2006.285.09:13:14.35#ibcon#*before return 0, iclass 23, count 0 2006.285.09:13:14.35#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:13:14.35#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:13:14.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.09:13:14.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.09:13:14.35$vck44/vblo=2,634.99 2006.285.09:13:14.35#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.09:13:14.35#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.09:13:14.35#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:14.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:13:14.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:13:14.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:13:14.35#ibcon#enter wrdev, iclass 25, count 0 2006.285.09:13:14.35#ibcon#first serial, iclass 25, count 0 2006.285.09:13:14.35#ibcon#enter sib2, iclass 25, count 0 2006.285.09:13:14.35#ibcon#flushed, iclass 25, count 0 2006.285.09:13:14.35#ibcon#about to write, iclass 25, count 0 2006.285.09:13:14.35#ibcon#wrote, iclass 25, count 0 2006.285.09:13:14.35#ibcon#about to read 3, iclass 25, count 0 2006.285.09:13:14.37#ibcon#read 3, iclass 25, count 0 2006.285.09:13:14.37#ibcon#about to read 4, iclass 25, count 0 2006.285.09:13:14.37#ibcon#read 4, iclass 25, count 0 2006.285.09:13:14.37#ibcon#about to read 5, iclass 25, count 0 2006.285.09:13:14.37#ibcon#read 5, iclass 25, count 0 2006.285.09:13:14.37#ibcon#about to read 6, iclass 25, count 0 2006.285.09:13:14.37#ibcon#read 6, iclass 25, count 0 2006.285.09:13:14.37#ibcon#end of sib2, iclass 25, count 0 2006.285.09:13:14.37#ibcon#*mode == 0, iclass 25, count 0 2006.285.09:13:14.37#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.09:13:14.37#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:13:14.37#ibcon#*before write, iclass 25, count 0 2006.285.09:13:14.37#ibcon#enter sib2, iclass 25, count 0 2006.285.09:13:14.37#ibcon#flushed, iclass 25, count 0 2006.285.09:13:14.37#ibcon#about to write, iclass 25, count 0 2006.285.09:13:14.37#ibcon#wrote, iclass 25, count 0 2006.285.09:13:14.37#ibcon#about to read 3, iclass 25, count 0 2006.285.09:13:14.41#ibcon#read 3, iclass 25, count 0 2006.285.09:13:14.41#ibcon#about to read 4, iclass 25, count 0 2006.285.09:13:14.41#ibcon#read 4, iclass 25, count 0 2006.285.09:13:14.41#ibcon#about to read 5, iclass 25, count 0 2006.285.09:13:14.41#ibcon#read 5, iclass 25, count 0 2006.285.09:13:14.41#ibcon#about to read 6, iclass 25, count 0 2006.285.09:13:14.41#ibcon#read 6, iclass 25, count 0 2006.285.09:13:14.41#ibcon#end of sib2, iclass 25, count 0 2006.285.09:13:14.41#ibcon#*after write, iclass 25, count 0 2006.285.09:13:14.41#ibcon#*before return 0, iclass 25, count 0 2006.285.09:13:14.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:13:14.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:13:14.41#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.09:13:14.41#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.09:13:14.41$vck44/vb=2,5 2006.285.09:13:14.41#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.09:13:14.41#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.09:13:14.41#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:14.41#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:13:14.47#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:13:14.47#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:13:14.47#ibcon#enter wrdev, iclass 27, count 2 2006.285.09:13:14.47#ibcon#first serial, iclass 27, count 2 2006.285.09:13:14.47#ibcon#enter sib2, iclass 27, count 2 2006.285.09:13:14.47#ibcon#flushed, iclass 27, count 2 2006.285.09:13:14.47#ibcon#about to write, iclass 27, count 2 2006.285.09:13:14.47#ibcon#wrote, iclass 27, count 2 2006.285.09:13:14.47#ibcon#about to read 3, iclass 27, count 2 2006.285.09:13:14.49#ibcon#read 3, iclass 27, count 2 2006.285.09:13:14.49#ibcon#about to read 4, iclass 27, count 2 2006.285.09:13:14.49#ibcon#read 4, iclass 27, count 2 2006.285.09:13:14.49#ibcon#about to read 5, iclass 27, count 2 2006.285.09:13:14.49#ibcon#read 5, iclass 27, count 2 2006.285.09:13:14.49#ibcon#about to read 6, iclass 27, count 2 2006.285.09:13:14.49#ibcon#read 6, iclass 27, count 2 2006.285.09:13:14.49#ibcon#end of sib2, iclass 27, count 2 2006.285.09:13:14.49#ibcon#*mode == 0, iclass 27, count 2 2006.285.09:13:14.49#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.09:13:14.49#ibcon#[27=AT02-05\r\n] 2006.285.09:13:14.49#ibcon#*before write, iclass 27, count 2 2006.285.09:13:14.49#ibcon#enter sib2, iclass 27, count 2 2006.285.09:13:14.49#ibcon#flushed, iclass 27, count 2 2006.285.09:13:14.49#ibcon#about to write, iclass 27, count 2 2006.285.09:13:14.49#ibcon#wrote, iclass 27, count 2 2006.285.09:13:14.49#ibcon#about to read 3, iclass 27, count 2 2006.285.09:13:14.52#ibcon#read 3, iclass 27, count 2 2006.285.09:13:14.52#ibcon#about to read 4, iclass 27, count 2 2006.285.09:13:14.52#ibcon#read 4, iclass 27, count 2 2006.285.09:13:14.52#ibcon#about to read 5, iclass 27, count 2 2006.285.09:13:14.52#ibcon#read 5, iclass 27, count 2 2006.285.09:13:14.52#ibcon#about to read 6, iclass 27, count 2 2006.285.09:13:14.52#ibcon#read 6, iclass 27, count 2 2006.285.09:13:14.52#ibcon#end of sib2, iclass 27, count 2 2006.285.09:13:14.52#ibcon#*after write, iclass 27, count 2 2006.285.09:13:14.52#ibcon#*before return 0, iclass 27, count 2 2006.285.09:13:14.52#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:13:14.52#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:13:14.52#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.09:13:14.52#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:14.52#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:13:14.64#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:13:14.64#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:13:14.64#ibcon#enter wrdev, iclass 27, count 0 2006.285.09:13:14.64#ibcon#first serial, iclass 27, count 0 2006.285.09:13:14.64#ibcon#enter sib2, iclass 27, count 0 2006.285.09:13:14.64#ibcon#flushed, iclass 27, count 0 2006.285.09:13:14.64#ibcon#about to write, iclass 27, count 0 2006.285.09:13:14.64#ibcon#wrote, iclass 27, count 0 2006.285.09:13:14.64#ibcon#about to read 3, iclass 27, count 0 2006.285.09:13:14.66#ibcon#read 3, iclass 27, count 0 2006.285.09:13:14.66#ibcon#about to read 4, iclass 27, count 0 2006.285.09:13:14.66#ibcon#read 4, iclass 27, count 0 2006.285.09:13:14.66#ibcon#about to read 5, iclass 27, count 0 2006.285.09:13:14.66#ibcon#read 5, iclass 27, count 0 2006.285.09:13:14.66#ibcon#about to read 6, iclass 27, count 0 2006.285.09:13:14.66#ibcon#read 6, iclass 27, count 0 2006.285.09:13:14.66#ibcon#end of sib2, iclass 27, count 0 2006.285.09:13:14.66#ibcon#*mode == 0, iclass 27, count 0 2006.285.09:13:14.66#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.09:13:14.66#ibcon#[27=USB\r\n] 2006.285.09:13:14.66#ibcon#*before write, iclass 27, count 0 2006.285.09:13:14.66#ibcon#enter sib2, iclass 27, count 0 2006.285.09:13:14.66#ibcon#flushed, iclass 27, count 0 2006.285.09:13:14.66#ibcon#about to write, iclass 27, count 0 2006.285.09:13:14.66#ibcon#wrote, iclass 27, count 0 2006.285.09:13:14.66#ibcon#about to read 3, iclass 27, count 0 2006.285.09:13:14.69#ibcon#read 3, iclass 27, count 0 2006.285.09:13:14.69#ibcon#about to read 4, iclass 27, count 0 2006.285.09:13:14.69#ibcon#read 4, iclass 27, count 0 2006.285.09:13:14.69#ibcon#about to read 5, iclass 27, count 0 2006.285.09:13:14.69#ibcon#read 5, iclass 27, count 0 2006.285.09:13:14.69#ibcon#about to read 6, iclass 27, count 0 2006.285.09:13:14.69#ibcon#read 6, iclass 27, count 0 2006.285.09:13:14.69#ibcon#end of sib2, iclass 27, count 0 2006.285.09:13:14.69#ibcon#*after write, iclass 27, count 0 2006.285.09:13:14.69#ibcon#*before return 0, iclass 27, count 0 2006.285.09:13:14.69#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:13:14.69#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:13:14.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.09:13:14.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.09:13:14.69$vck44/vblo=3,649.99 2006.285.09:13:14.69#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.09:13:14.69#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.09:13:14.69#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:14.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:13:14.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:13:14.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:13:14.69#ibcon#enter wrdev, iclass 29, count 0 2006.285.09:13:14.69#ibcon#first serial, iclass 29, count 0 2006.285.09:13:14.69#ibcon#enter sib2, iclass 29, count 0 2006.285.09:13:14.69#ibcon#flushed, iclass 29, count 0 2006.285.09:13:14.69#ibcon#about to write, iclass 29, count 0 2006.285.09:13:14.69#ibcon#wrote, iclass 29, count 0 2006.285.09:13:14.69#ibcon#about to read 3, iclass 29, count 0 2006.285.09:13:14.71#ibcon#read 3, iclass 29, count 0 2006.285.09:13:14.71#ibcon#about to read 4, iclass 29, count 0 2006.285.09:13:14.71#ibcon#read 4, iclass 29, count 0 2006.285.09:13:14.71#ibcon#about to read 5, iclass 29, count 0 2006.285.09:13:14.71#ibcon#read 5, iclass 29, count 0 2006.285.09:13:14.71#ibcon#about to read 6, iclass 29, count 0 2006.285.09:13:14.71#ibcon#read 6, iclass 29, count 0 2006.285.09:13:14.71#ibcon#end of sib2, iclass 29, count 0 2006.285.09:13:14.71#ibcon#*mode == 0, iclass 29, count 0 2006.285.09:13:14.71#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.09:13:14.71#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:13:14.71#ibcon#*before write, iclass 29, count 0 2006.285.09:13:14.71#ibcon#enter sib2, iclass 29, count 0 2006.285.09:13:14.71#ibcon#flushed, iclass 29, count 0 2006.285.09:13:14.71#ibcon#about to write, iclass 29, count 0 2006.285.09:13:14.71#ibcon#wrote, iclass 29, count 0 2006.285.09:13:14.71#ibcon#about to read 3, iclass 29, count 0 2006.285.09:13:14.75#ibcon#read 3, iclass 29, count 0 2006.285.09:13:14.75#ibcon#about to read 4, iclass 29, count 0 2006.285.09:13:14.75#ibcon#read 4, iclass 29, count 0 2006.285.09:13:14.75#ibcon#about to read 5, iclass 29, count 0 2006.285.09:13:14.75#ibcon#read 5, iclass 29, count 0 2006.285.09:13:14.75#ibcon#about to read 6, iclass 29, count 0 2006.285.09:13:14.75#ibcon#read 6, iclass 29, count 0 2006.285.09:13:14.75#ibcon#end of sib2, iclass 29, count 0 2006.285.09:13:14.75#ibcon#*after write, iclass 29, count 0 2006.285.09:13:14.75#ibcon#*before return 0, iclass 29, count 0 2006.285.09:13:14.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:13:14.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:13:14.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.09:13:14.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.09:13:14.75$vck44/vb=3,4 2006.285.09:13:14.75#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.09:13:14.75#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.09:13:14.75#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:14.75#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:13:14.81#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:13:14.81#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:13:14.81#ibcon#enter wrdev, iclass 31, count 2 2006.285.09:13:14.81#ibcon#first serial, iclass 31, count 2 2006.285.09:13:14.81#ibcon#enter sib2, iclass 31, count 2 2006.285.09:13:14.81#ibcon#flushed, iclass 31, count 2 2006.285.09:13:14.81#ibcon#about to write, iclass 31, count 2 2006.285.09:13:14.81#ibcon#wrote, iclass 31, count 2 2006.285.09:13:14.81#ibcon#about to read 3, iclass 31, count 2 2006.285.09:13:14.83#ibcon#read 3, iclass 31, count 2 2006.285.09:13:14.83#ibcon#about to read 4, iclass 31, count 2 2006.285.09:13:14.83#ibcon#read 4, iclass 31, count 2 2006.285.09:13:14.83#ibcon#about to read 5, iclass 31, count 2 2006.285.09:13:14.83#ibcon#read 5, iclass 31, count 2 2006.285.09:13:14.83#ibcon#about to read 6, iclass 31, count 2 2006.285.09:13:14.83#ibcon#read 6, iclass 31, count 2 2006.285.09:13:14.83#ibcon#end of sib2, iclass 31, count 2 2006.285.09:13:14.83#ibcon#*mode == 0, iclass 31, count 2 2006.285.09:13:14.83#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.09:13:14.83#ibcon#[27=AT03-04\r\n] 2006.285.09:13:14.83#ibcon#*before write, iclass 31, count 2 2006.285.09:13:14.83#ibcon#enter sib2, iclass 31, count 2 2006.285.09:13:14.83#ibcon#flushed, iclass 31, count 2 2006.285.09:13:14.83#ibcon#about to write, iclass 31, count 2 2006.285.09:13:14.83#ibcon#wrote, iclass 31, count 2 2006.285.09:13:14.83#ibcon#about to read 3, iclass 31, count 2 2006.285.09:13:14.86#ibcon#read 3, iclass 31, count 2 2006.285.09:13:14.86#ibcon#about to read 4, iclass 31, count 2 2006.285.09:13:14.86#ibcon#read 4, iclass 31, count 2 2006.285.09:13:14.86#ibcon#about to read 5, iclass 31, count 2 2006.285.09:13:14.86#ibcon#read 5, iclass 31, count 2 2006.285.09:13:14.86#ibcon#about to read 6, iclass 31, count 2 2006.285.09:13:14.86#ibcon#read 6, iclass 31, count 2 2006.285.09:13:14.86#ibcon#end of sib2, iclass 31, count 2 2006.285.09:13:14.86#ibcon#*after write, iclass 31, count 2 2006.285.09:13:14.86#ibcon#*before return 0, iclass 31, count 2 2006.285.09:13:14.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:13:14.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:13:14.86#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.09:13:14.86#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:14.86#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:13:14.98#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:13:14.98#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:13:14.98#ibcon#enter wrdev, iclass 31, count 0 2006.285.09:13:14.98#ibcon#first serial, iclass 31, count 0 2006.285.09:13:14.98#ibcon#enter sib2, iclass 31, count 0 2006.285.09:13:14.98#ibcon#flushed, iclass 31, count 0 2006.285.09:13:14.98#ibcon#about to write, iclass 31, count 0 2006.285.09:13:14.98#ibcon#wrote, iclass 31, count 0 2006.285.09:13:14.98#ibcon#about to read 3, iclass 31, count 0 2006.285.09:13:15.00#ibcon#read 3, iclass 31, count 0 2006.285.09:13:15.00#ibcon#about to read 4, iclass 31, count 0 2006.285.09:13:15.00#ibcon#read 4, iclass 31, count 0 2006.285.09:13:15.00#ibcon#about to read 5, iclass 31, count 0 2006.285.09:13:15.00#ibcon#read 5, iclass 31, count 0 2006.285.09:13:15.00#ibcon#about to read 6, iclass 31, count 0 2006.285.09:13:15.00#ibcon#read 6, iclass 31, count 0 2006.285.09:13:15.00#ibcon#end of sib2, iclass 31, count 0 2006.285.09:13:15.00#ibcon#*mode == 0, iclass 31, count 0 2006.285.09:13:15.00#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.09:13:15.00#ibcon#[27=USB\r\n] 2006.285.09:13:15.00#ibcon#*before write, iclass 31, count 0 2006.285.09:13:15.00#ibcon#enter sib2, iclass 31, count 0 2006.285.09:13:15.00#ibcon#flushed, iclass 31, count 0 2006.285.09:13:15.00#ibcon#about to write, iclass 31, count 0 2006.285.09:13:15.00#ibcon#wrote, iclass 31, count 0 2006.285.09:13:15.00#ibcon#about to read 3, iclass 31, count 0 2006.285.09:13:15.03#ibcon#read 3, iclass 31, count 0 2006.285.09:13:15.03#ibcon#about to read 4, iclass 31, count 0 2006.285.09:13:15.03#ibcon#read 4, iclass 31, count 0 2006.285.09:13:15.03#ibcon#about to read 5, iclass 31, count 0 2006.285.09:13:15.03#ibcon#read 5, iclass 31, count 0 2006.285.09:13:15.03#ibcon#about to read 6, iclass 31, count 0 2006.285.09:13:15.03#ibcon#read 6, iclass 31, count 0 2006.285.09:13:15.03#ibcon#end of sib2, iclass 31, count 0 2006.285.09:13:15.03#ibcon#*after write, iclass 31, count 0 2006.285.09:13:15.03#ibcon#*before return 0, iclass 31, count 0 2006.285.09:13:15.03#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:13:15.03#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:13:15.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.09:13:15.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.09:13:15.03$vck44/vblo=4,679.99 2006.285.09:13:15.03#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.09:13:15.03#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.09:13:15.03#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:15.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:13:15.03#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:13:15.03#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:13:15.03#ibcon#enter wrdev, iclass 33, count 0 2006.285.09:13:15.03#ibcon#first serial, iclass 33, count 0 2006.285.09:13:15.03#ibcon#enter sib2, iclass 33, count 0 2006.285.09:13:15.03#ibcon#flushed, iclass 33, count 0 2006.285.09:13:15.03#ibcon#about to write, iclass 33, count 0 2006.285.09:13:15.03#ibcon#wrote, iclass 33, count 0 2006.285.09:13:15.03#ibcon#about to read 3, iclass 33, count 0 2006.285.09:13:15.05#ibcon#read 3, iclass 33, count 0 2006.285.09:13:15.05#ibcon#about to read 4, iclass 33, count 0 2006.285.09:13:15.05#ibcon#read 4, iclass 33, count 0 2006.285.09:13:15.05#ibcon#about to read 5, iclass 33, count 0 2006.285.09:13:15.05#ibcon#read 5, iclass 33, count 0 2006.285.09:13:15.05#ibcon#about to read 6, iclass 33, count 0 2006.285.09:13:15.05#ibcon#read 6, iclass 33, count 0 2006.285.09:13:15.05#ibcon#end of sib2, iclass 33, count 0 2006.285.09:13:15.05#ibcon#*mode == 0, iclass 33, count 0 2006.285.09:13:15.05#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.09:13:15.05#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:13:15.05#ibcon#*before write, iclass 33, count 0 2006.285.09:13:15.05#ibcon#enter sib2, iclass 33, count 0 2006.285.09:13:15.05#ibcon#flushed, iclass 33, count 0 2006.285.09:13:15.05#ibcon#about to write, iclass 33, count 0 2006.285.09:13:15.05#ibcon#wrote, iclass 33, count 0 2006.285.09:13:15.05#ibcon#about to read 3, iclass 33, count 0 2006.285.09:13:15.09#ibcon#read 3, iclass 33, count 0 2006.285.09:13:15.09#ibcon#about to read 4, iclass 33, count 0 2006.285.09:13:15.09#ibcon#read 4, iclass 33, count 0 2006.285.09:13:15.09#ibcon#about to read 5, iclass 33, count 0 2006.285.09:13:15.09#ibcon#read 5, iclass 33, count 0 2006.285.09:13:15.09#ibcon#about to read 6, iclass 33, count 0 2006.285.09:13:15.09#ibcon#read 6, iclass 33, count 0 2006.285.09:13:15.09#ibcon#end of sib2, iclass 33, count 0 2006.285.09:13:15.09#ibcon#*after write, iclass 33, count 0 2006.285.09:13:15.09#ibcon#*before return 0, iclass 33, count 0 2006.285.09:13:15.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:13:15.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:13:15.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.09:13:15.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.09:13:15.09$vck44/vb=4,5 2006.285.09:13:15.09#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.09:13:15.09#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.09:13:15.09#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:15.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:13:15.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:13:15.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:13:15.15#ibcon#enter wrdev, iclass 35, count 2 2006.285.09:13:15.15#ibcon#first serial, iclass 35, count 2 2006.285.09:13:15.15#ibcon#enter sib2, iclass 35, count 2 2006.285.09:13:15.15#ibcon#flushed, iclass 35, count 2 2006.285.09:13:15.15#ibcon#about to write, iclass 35, count 2 2006.285.09:13:15.15#ibcon#wrote, iclass 35, count 2 2006.285.09:13:15.15#ibcon#about to read 3, iclass 35, count 2 2006.285.09:13:15.17#ibcon#read 3, iclass 35, count 2 2006.285.09:13:15.17#ibcon#about to read 4, iclass 35, count 2 2006.285.09:13:15.17#ibcon#read 4, iclass 35, count 2 2006.285.09:13:15.17#ibcon#about to read 5, iclass 35, count 2 2006.285.09:13:15.17#ibcon#read 5, iclass 35, count 2 2006.285.09:13:15.17#ibcon#about to read 6, iclass 35, count 2 2006.285.09:13:15.17#ibcon#read 6, iclass 35, count 2 2006.285.09:13:15.17#ibcon#end of sib2, iclass 35, count 2 2006.285.09:13:15.17#ibcon#*mode == 0, iclass 35, count 2 2006.285.09:13:15.17#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.09:13:15.17#ibcon#[27=AT04-05\r\n] 2006.285.09:13:15.17#ibcon#*before write, iclass 35, count 2 2006.285.09:13:15.17#ibcon#enter sib2, iclass 35, count 2 2006.285.09:13:15.17#ibcon#flushed, iclass 35, count 2 2006.285.09:13:15.17#ibcon#about to write, iclass 35, count 2 2006.285.09:13:15.17#ibcon#wrote, iclass 35, count 2 2006.285.09:13:15.17#ibcon#about to read 3, iclass 35, count 2 2006.285.09:13:15.20#ibcon#read 3, iclass 35, count 2 2006.285.09:13:15.20#ibcon#about to read 4, iclass 35, count 2 2006.285.09:13:15.20#ibcon#read 4, iclass 35, count 2 2006.285.09:13:15.20#ibcon#about to read 5, iclass 35, count 2 2006.285.09:13:15.20#ibcon#read 5, iclass 35, count 2 2006.285.09:13:15.20#ibcon#about to read 6, iclass 35, count 2 2006.285.09:13:15.20#ibcon#read 6, iclass 35, count 2 2006.285.09:13:15.20#ibcon#end of sib2, iclass 35, count 2 2006.285.09:13:15.20#ibcon#*after write, iclass 35, count 2 2006.285.09:13:15.20#ibcon#*before return 0, iclass 35, count 2 2006.285.09:13:15.20#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:13:15.20#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:13:15.20#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.09:13:15.20#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:15.20#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:13:15.32#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:13:15.32#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:13:15.32#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:13:15.32#ibcon#first serial, iclass 35, count 0 2006.285.09:13:15.32#ibcon#enter sib2, iclass 35, count 0 2006.285.09:13:15.32#ibcon#flushed, iclass 35, count 0 2006.285.09:13:15.32#ibcon#about to write, iclass 35, count 0 2006.285.09:13:15.32#ibcon#wrote, iclass 35, count 0 2006.285.09:13:15.32#ibcon#about to read 3, iclass 35, count 0 2006.285.09:13:15.34#ibcon#read 3, iclass 35, count 0 2006.285.09:13:15.34#ibcon#about to read 4, iclass 35, count 0 2006.285.09:13:15.34#ibcon#read 4, iclass 35, count 0 2006.285.09:13:15.34#ibcon#about to read 5, iclass 35, count 0 2006.285.09:13:15.34#ibcon#read 5, iclass 35, count 0 2006.285.09:13:15.34#ibcon#about to read 6, iclass 35, count 0 2006.285.09:13:15.34#ibcon#read 6, iclass 35, count 0 2006.285.09:13:15.34#ibcon#end of sib2, iclass 35, count 0 2006.285.09:13:15.34#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:13:15.34#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:13:15.34#ibcon#[27=USB\r\n] 2006.285.09:13:15.34#ibcon#*before write, iclass 35, count 0 2006.285.09:13:15.34#ibcon#enter sib2, iclass 35, count 0 2006.285.09:13:15.34#ibcon#flushed, iclass 35, count 0 2006.285.09:13:15.34#ibcon#about to write, iclass 35, count 0 2006.285.09:13:15.34#ibcon#wrote, iclass 35, count 0 2006.285.09:13:15.34#ibcon#about to read 3, iclass 35, count 0 2006.285.09:13:15.37#ibcon#read 3, iclass 35, count 0 2006.285.09:13:15.37#ibcon#about to read 4, iclass 35, count 0 2006.285.09:13:15.37#ibcon#read 4, iclass 35, count 0 2006.285.09:13:15.37#ibcon#about to read 5, iclass 35, count 0 2006.285.09:13:15.37#ibcon#read 5, iclass 35, count 0 2006.285.09:13:15.37#ibcon#about to read 6, iclass 35, count 0 2006.285.09:13:15.37#ibcon#read 6, iclass 35, count 0 2006.285.09:13:15.37#ibcon#end of sib2, iclass 35, count 0 2006.285.09:13:15.37#ibcon#*after write, iclass 35, count 0 2006.285.09:13:15.37#ibcon#*before return 0, iclass 35, count 0 2006.285.09:13:15.37#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:13:15.37#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:13:15.37#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:13:15.37#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:13:15.37$vck44/vblo=5,709.99 2006.285.09:13:15.37#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.09:13:15.37#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.09:13:15.37#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:15.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:13:15.37#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:13:15.37#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:13:15.37#ibcon#enter wrdev, iclass 37, count 0 2006.285.09:13:15.37#ibcon#first serial, iclass 37, count 0 2006.285.09:13:15.37#ibcon#enter sib2, iclass 37, count 0 2006.285.09:13:15.37#ibcon#flushed, iclass 37, count 0 2006.285.09:13:15.37#ibcon#about to write, iclass 37, count 0 2006.285.09:13:15.37#ibcon#wrote, iclass 37, count 0 2006.285.09:13:15.37#ibcon#about to read 3, iclass 37, count 0 2006.285.09:13:15.39#ibcon#read 3, iclass 37, count 0 2006.285.09:13:15.39#ibcon#about to read 4, iclass 37, count 0 2006.285.09:13:15.39#ibcon#read 4, iclass 37, count 0 2006.285.09:13:15.39#ibcon#about to read 5, iclass 37, count 0 2006.285.09:13:15.39#ibcon#read 5, iclass 37, count 0 2006.285.09:13:15.39#ibcon#about to read 6, iclass 37, count 0 2006.285.09:13:15.39#ibcon#read 6, iclass 37, count 0 2006.285.09:13:15.39#ibcon#end of sib2, iclass 37, count 0 2006.285.09:13:15.39#ibcon#*mode == 0, iclass 37, count 0 2006.285.09:13:15.39#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.09:13:15.39#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:13:15.39#ibcon#*before write, iclass 37, count 0 2006.285.09:13:15.39#ibcon#enter sib2, iclass 37, count 0 2006.285.09:13:15.39#ibcon#flushed, iclass 37, count 0 2006.285.09:13:15.39#ibcon#about to write, iclass 37, count 0 2006.285.09:13:15.39#ibcon#wrote, iclass 37, count 0 2006.285.09:13:15.39#ibcon#about to read 3, iclass 37, count 0 2006.285.09:13:15.43#ibcon#read 3, iclass 37, count 0 2006.285.09:13:15.43#ibcon#about to read 4, iclass 37, count 0 2006.285.09:13:15.43#ibcon#read 4, iclass 37, count 0 2006.285.09:13:15.43#ibcon#about to read 5, iclass 37, count 0 2006.285.09:13:15.43#ibcon#read 5, iclass 37, count 0 2006.285.09:13:15.43#ibcon#about to read 6, iclass 37, count 0 2006.285.09:13:15.43#ibcon#read 6, iclass 37, count 0 2006.285.09:13:15.43#ibcon#end of sib2, iclass 37, count 0 2006.285.09:13:15.43#ibcon#*after write, iclass 37, count 0 2006.285.09:13:15.43#ibcon#*before return 0, iclass 37, count 0 2006.285.09:13:15.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:13:15.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:13:15.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.09:13:15.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.09:13:15.43$vck44/vb=5,4 2006.285.09:13:15.43#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.09:13:15.43#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.09:13:15.43#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:15.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:13:15.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:13:15.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:13:15.49#ibcon#enter wrdev, iclass 39, count 2 2006.285.09:13:15.49#ibcon#first serial, iclass 39, count 2 2006.285.09:13:15.49#ibcon#enter sib2, iclass 39, count 2 2006.285.09:13:15.49#ibcon#flushed, iclass 39, count 2 2006.285.09:13:15.49#ibcon#about to write, iclass 39, count 2 2006.285.09:13:15.49#ibcon#wrote, iclass 39, count 2 2006.285.09:13:15.49#ibcon#about to read 3, iclass 39, count 2 2006.285.09:13:15.51#ibcon#read 3, iclass 39, count 2 2006.285.09:13:15.51#ibcon#about to read 4, iclass 39, count 2 2006.285.09:13:15.51#ibcon#read 4, iclass 39, count 2 2006.285.09:13:15.51#ibcon#about to read 5, iclass 39, count 2 2006.285.09:13:15.51#ibcon#read 5, iclass 39, count 2 2006.285.09:13:15.51#ibcon#about to read 6, iclass 39, count 2 2006.285.09:13:15.51#ibcon#read 6, iclass 39, count 2 2006.285.09:13:15.51#ibcon#end of sib2, iclass 39, count 2 2006.285.09:13:15.51#ibcon#*mode == 0, iclass 39, count 2 2006.285.09:13:15.51#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.09:13:15.51#ibcon#[27=AT05-04\r\n] 2006.285.09:13:15.51#ibcon#*before write, iclass 39, count 2 2006.285.09:13:15.51#ibcon#enter sib2, iclass 39, count 2 2006.285.09:13:15.51#ibcon#flushed, iclass 39, count 2 2006.285.09:13:15.51#ibcon#about to write, iclass 39, count 2 2006.285.09:13:15.51#ibcon#wrote, iclass 39, count 2 2006.285.09:13:15.51#ibcon#about to read 3, iclass 39, count 2 2006.285.09:13:15.54#ibcon#read 3, iclass 39, count 2 2006.285.09:13:15.54#ibcon#about to read 4, iclass 39, count 2 2006.285.09:13:15.54#ibcon#read 4, iclass 39, count 2 2006.285.09:13:15.54#ibcon#about to read 5, iclass 39, count 2 2006.285.09:13:15.54#ibcon#read 5, iclass 39, count 2 2006.285.09:13:15.54#ibcon#about to read 6, iclass 39, count 2 2006.285.09:13:15.54#ibcon#read 6, iclass 39, count 2 2006.285.09:13:15.54#ibcon#end of sib2, iclass 39, count 2 2006.285.09:13:15.54#ibcon#*after write, iclass 39, count 2 2006.285.09:13:15.54#ibcon#*before return 0, iclass 39, count 2 2006.285.09:13:15.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:13:15.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:13:15.54#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.09:13:15.54#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:15.54#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:13:15.66#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:13:15.66#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:13:15.66#ibcon#enter wrdev, iclass 39, count 0 2006.285.09:13:15.66#ibcon#first serial, iclass 39, count 0 2006.285.09:13:15.66#ibcon#enter sib2, iclass 39, count 0 2006.285.09:13:15.66#ibcon#flushed, iclass 39, count 0 2006.285.09:13:15.66#ibcon#about to write, iclass 39, count 0 2006.285.09:13:15.66#ibcon#wrote, iclass 39, count 0 2006.285.09:13:15.66#ibcon#about to read 3, iclass 39, count 0 2006.285.09:13:15.68#ibcon#read 3, iclass 39, count 0 2006.285.09:13:15.68#ibcon#about to read 4, iclass 39, count 0 2006.285.09:13:15.68#ibcon#read 4, iclass 39, count 0 2006.285.09:13:15.68#ibcon#about to read 5, iclass 39, count 0 2006.285.09:13:15.68#ibcon#read 5, iclass 39, count 0 2006.285.09:13:15.68#ibcon#about to read 6, iclass 39, count 0 2006.285.09:13:15.68#ibcon#read 6, iclass 39, count 0 2006.285.09:13:15.68#ibcon#end of sib2, iclass 39, count 0 2006.285.09:13:15.68#ibcon#*mode == 0, iclass 39, count 0 2006.285.09:13:15.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.09:13:15.68#ibcon#[27=USB\r\n] 2006.285.09:13:15.68#ibcon#*before write, iclass 39, count 0 2006.285.09:13:15.68#ibcon#enter sib2, iclass 39, count 0 2006.285.09:13:15.68#ibcon#flushed, iclass 39, count 0 2006.285.09:13:15.68#ibcon#about to write, iclass 39, count 0 2006.285.09:13:15.68#ibcon#wrote, iclass 39, count 0 2006.285.09:13:15.68#ibcon#about to read 3, iclass 39, count 0 2006.285.09:13:15.71#ibcon#read 3, iclass 39, count 0 2006.285.09:13:15.71#ibcon#about to read 4, iclass 39, count 0 2006.285.09:13:15.71#ibcon#read 4, iclass 39, count 0 2006.285.09:13:15.71#ibcon#about to read 5, iclass 39, count 0 2006.285.09:13:15.71#ibcon#read 5, iclass 39, count 0 2006.285.09:13:15.71#ibcon#about to read 6, iclass 39, count 0 2006.285.09:13:15.71#ibcon#read 6, iclass 39, count 0 2006.285.09:13:15.71#ibcon#end of sib2, iclass 39, count 0 2006.285.09:13:15.71#ibcon#*after write, iclass 39, count 0 2006.285.09:13:15.71#ibcon#*before return 0, iclass 39, count 0 2006.285.09:13:15.71#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:13:15.71#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:13:15.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.09:13:15.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.09:13:15.71$vck44/vblo=6,719.99 2006.285.09:13:15.71#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.09:13:15.71#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.09:13:15.71#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:15.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:13:15.71#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:13:15.71#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:13:15.71#ibcon#enter wrdev, iclass 3, count 0 2006.285.09:13:15.71#ibcon#first serial, iclass 3, count 0 2006.285.09:13:15.71#ibcon#enter sib2, iclass 3, count 0 2006.285.09:13:15.71#ibcon#flushed, iclass 3, count 0 2006.285.09:13:15.71#ibcon#about to write, iclass 3, count 0 2006.285.09:13:15.71#ibcon#wrote, iclass 3, count 0 2006.285.09:13:15.71#ibcon#about to read 3, iclass 3, count 0 2006.285.09:13:15.73#ibcon#read 3, iclass 3, count 0 2006.285.09:13:15.73#ibcon#about to read 4, iclass 3, count 0 2006.285.09:13:15.73#ibcon#read 4, iclass 3, count 0 2006.285.09:13:15.73#ibcon#about to read 5, iclass 3, count 0 2006.285.09:13:15.73#ibcon#read 5, iclass 3, count 0 2006.285.09:13:15.73#ibcon#about to read 6, iclass 3, count 0 2006.285.09:13:15.73#ibcon#read 6, iclass 3, count 0 2006.285.09:13:15.73#ibcon#end of sib2, iclass 3, count 0 2006.285.09:13:15.73#ibcon#*mode == 0, iclass 3, count 0 2006.285.09:13:15.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.09:13:15.73#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:13:15.73#ibcon#*before write, iclass 3, count 0 2006.285.09:13:15.73#ibcon#enter sib2, iclass 3, count 0 2006.285.09:13:15.73#ibcon#flushed, iclass 3, count 0 2006.285.09:13:15.73#ibcon#about to write, iclass 3, count 0 2006.285.09:13:15.73#ibcon#wrote, iclass 3, count 0 2006.285.09:13:15.73#ibcon#about to read 3, iclass 3, count 0 2006.285.09:13:15.77#ibcon#read 3, iclass 3, count 0 2006.285.09:13:15.77#ibcon#about to read 4, iclass 3, count 0 2006.285.09:13:15.77#ibcon#read 4, iclass 3, count 0 2006.285.09:13:15.77#ibcon#about to read 5, iclass 3, count 0 2006.285.09:13:15.77#ibcon#read 5, iclass 3, count 0 2006.285.09:13:15.77#ibcon#about to read 6, iclass 3, count 0 2006.285.09:13:15.77#ibcon#read 6, iclass 3, count 0 2006.285.09:13:15.77#ibcon#end of sib2, iclass 3, count 0 2006.285.09:13:15.77#ibcon#*after write, iclass 3, count 0 2006.285.09:13:15.77#ibcon#*before return 0, iclass 3, count 0 2006.285.09:13:15.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:13:15.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:13:15.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.09:13:15.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.09:13:15.77$vck44/vb=6,3 2006.285.09:13:15.77#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.09:13:15.77#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.09:13:15.77#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:15.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:13:15.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:13:15.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:13:15.83#ibcon#enter wrdev, iclass 5, count 2 2006.285.09:13:15.83#ibcon#first serial, iclass 5, count 2 2006.285.09:13:15.83#ibcon#enter sib2, iclass 5, count 2 2006.285.09:13:15.83#ibcon#flushed, iclass 5, count 2 2006.285.09:13:15.83#ibcon#about to write, iclass 5, count 2 2006.285.09:13:15.83#ibcon#wrote, iclass 5, count 2 2006.285.09:13:15.83#ibcon#about to read 3, iclass 5, count 2 2006.285.09:13:15.85#ibcon#read 3, iclass 5, count 2 2006.285.09:13:15.85#ibcon#about to read 4, iclass 5, count 2 2006.285.09:13:15.85#ibcon#read 4, iclass 5, count 2 2006.285.09:13:15.85#ibcon#about to read 5, iclass 5, count 2 2006.285.09:13:15.85#ibcon#read 5, iclass 5, count 2 2006.285.09:13:15.85#ibcon#about to read 6, iclass 5, count 2 2006.285.09:13:15.85#ibcon#read 6, iclass 5, count 2 2006.285.09:13:15.85#ibcon#end of sib2, iclass 5, count 2 2006.285.09:13:15.85#ibcon#*mode == 0, iclass 5, count 2 2006.285.09:13:15.85#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.09:13:15.85#ibcon#[27=AT06-03\r\n] 2006.285.09:13:15.85#ibcon#*before write, iclass 5, count 2 2006.285.09:13:15.85#ibcon#enter sib2, iclass 5, count 2 2006.285.09:13:15.85#ibcon#flushed, iclass 5, count 2 2006.285.09:13:15.85#ibcon#about to write, iclass 5, count 2 2006.285.09:13:15.85#ibcon#wrote, iclass 5, count 2 2006.285.09:13:15.85#ibcon#about to read 3, iclass 5, count 2 2006.285.09:13:15.88#ibcon#read 3, iclass 5, count 2 2006.285.09:13:15.88#ibcon#about to read 4, iclass 5, count 2 2006.285.09:13:15.88#ibcon#read 4, iclass 5, count 2 2006.285.09:13:15.88#ibcon#about to read 5, iclass 5, count 2 2006.285.09:13:15.88#ibcon#read 5, iclass 5, count 2 2006.285.09:13:15.88#ibcon#about to read 6, iclass 5, count 2 2006.285.09:13:15.88#ibcon#read 6, iclass 5, count 2 2006.285.09:13:15.88#ibcon#end of sib2, iclass 5, count 2 2006.285.09:13:15.88#ibcon#*after write, iclass 5, count 2 2006.285.09:13:15.88#ibcon#*before return 0, iclass 5, count 2 2006.285.09:13:15.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:13:15.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:13:15.88#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.09:13:15.88#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:15.88#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:13:16.00#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:13:16.00#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:13:16.00#ibcon#enter wrdev, iclass 5, count 0 2006.285.09:13:16.00#ibcon#first serial, iclass 5, count 0 2006.285.09:13:16.00#ibcon#enter sib2, iclass 5, count 0 2006.285.09:13:16.00#ibcon#flushed, iclass 5, count 0 2006.285.09:13:16.00#ibcon#about to write, iclass 5, count 0 2006.285.09:13:16.00#ibcon#wrote, iclass 5, count 0 2006.285.09:13:16.00#ibcon#about to read 3, iclass 5, count 0 2006.285.09:13:16.02#ibcon#read 3, iclass 5, count 0 2006.285.09:13:16.02#ibcon#about to read 4, iclass 5, count 0 2006.285.09:13:16.02#ibcon#read 4, iclass 5, count 0 2006.285.09:13:16.02#ibcon#about to read 5, iclass 5, count 0 2006.285.09:13:16.02#ibcon#read 5, iclass 5, count 0 2006.285.09:13:16.02#ibcon#about to read 6, iclass 5, count 0 2006.285.09:13:16.02#ibcon#read 6, iclass 5, count 0 2006.285.09:13:16.02#ibcon#end of sib2, iclass 5, count 0 2006.285.09:13:16.02#ibcon#*mode == 0, iclass 5, count 0 2006.285.09:13:16.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.09:13:16.02#ibcon#[27=USB\r\n] 2006.285.09:13:16.02#ibcon#*before write, iclass 5, count 0 2006.285.09:13:16.02#ibcon#enter sib2, iclass 5, count 0 2006.285.09:13:16.02#ibcon#flushed, iclass 5, count 0 2006.285.09:13:16.02#ibcon#about to write, iclass 5, count 0 2006.285.09:13:16.02#ibcon#wrote, iclass 5, count 0 2006.285.09:13:16.02#ibcon#about to read 3, iclass 5, count 0 2006.285.09:13:16.05#ibcon#read 3, iclass 5, count 0 2006.285.09:13:16.05#ibcon#about to read 4, iclass 5, count 0 2006.285.09:13:16.05#ibcon#read 4, iclass 5, count 0 2006.285.09:13:16.05#ibcon#about to read 5, iclass 5, count 0 2006.285.09:13:16.05#ibcon#read 5, iclass 5, count 0 2006.285.09:13:16.05#ibcon#about to read 6, iclass 5, count 0 2006.285.09:13:16.05#ibcon#read 6, iclass 5, count 0 2006.285.09:13:16.05#ibcon#end of sib2, iclass 5, count 0 2006.285.09:13:16.05#ibcon#*after write, iclass 5, count 0 2006.285.09:13:16.05#ibcon#*before return 0, iclass 5, count 0 2006.285.09:13:16.05#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:13:16.05#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:13:16.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.09:13:16.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.09:13:16.05$vck44/vblo=7,734.99 2006.285.09:13:16.05#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.09:13:16.05#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.09:13:16.05#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:16.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:13:16.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:13:16.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:13:16.05#ibcon#enter wrdev, iclass 7, count 0 2006.285.09:13:16.05#ibcon#first serial, iclass 7, count 0 2006.285.09:13:16.05#ibcon#enter sib2, iclass 7, count 0 2006.285.09:13:16.05#ibcon#flushed, iclass 7, count 0 2006.285.09:13:16.05#ibcon#about to write, iclass 7, count 0 2006.285.09:13:16.05#ibcon#wrote, iclass 7, count 0 2006.285.09:13:16.05#ibcon#about to read 3, iclass 7, count 0 2006.285.09:13:16.07#ibcon#read 3, iclass 7, count 0 2006.285.09:13:16.07#ibcon#about to read 4, iclass 7, count 0 2006.285.09:13:16.07#ibcon#read 4, iclass 7, count 0 2006.285.09:13:16.07#ibcon#about to read 5, iclass 7, count 0 2006.285.09:13:16.07#ibcon#read 5, iclass 7, count 0 2006.285.09:13:16.07#ibcon#about to read 6, iclass 7, count 0 2006.285.09:13:16.07#ibcon#read 6, iclass 7, count 0 2006.285.09:13:16.07#ibcon#end of sib2, iclass 7, count 0 2006.285.09:13:16.07#ibcon#*mode == 0, iclass 7, count 0 2006.285.09:13:16.07#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.09:13:16.07#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:13:16.07#ibcon#*before write, iclass 7, count 0 2006.285.09:13:16.07#ibcon#enter sib2, iclass 7, count 0 2006.285.09:13:16.07#ibcon#flushed, iclass 7, count 0 2006.285.09:13:16.07#ibcon#about to write, iclass 7, count 0 2006.285.09:13:16.07#ibcon#wrote, iclass 7, count 0 2006.285.09:13:16.07#ibcon#about to read 3, iclass 7, count 0 2006.285.09:13:16.11#ibcon#read 3, iclass 7, count 0 2006.285.09:13:16.11#ibcon#about to read 4, iclass 7, count 0 2006.285.09:13:16.11#ibcon#read 4, iclass 7, count 0 2006.285.09:13:16.11#ibcon#about to read 5, iclass 7, count 0 2006.285.09:13:16.11#ibcon#read 5, iclass 7, count 0 2006.285.09:13:16.11#ibcon#about to read 6, iclass 7, count 0 2006.285.09:13:16.11#ibcon#read 6, iclass 7, count 0 2006.285.09:13:16.11#ibcon#end of sib2, iclass 7, count 0 2006.285.09:13:16.11#ibcon#*after write, iclass 7, count 0 2006.285.09:13:16.11#ibcon#*before return 0, iclass 7, count 0 2006.285.09:13:16.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:13:16.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:13:16.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.09:13:16.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.09:13:16.11$vck44/vb=7,4 2006.285.09:13:16.11#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.09:13:16.11#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.09:13:16.11#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:16.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:13:16.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:13:16.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:13:16.17#ibcon#enter wrdev, iclass 11, count 2 2006.285.09:13:16.17#ibcon#first serial, iclass 11, count 2 2006.285.09:13:16.17#ibcon#enter sib2, iclass 11, count 2 2006.285.09:13:16.17#ibcon#flushed, iclass 11, count 2 2006.285.09:13:16.17#ibcon#about to write, iclass 11, count 2 2006.285.09:13:16.17#ibcon#wrote, iclass 11, count 2 2006.285.09:13:16.17#ibcon#about to read 3, iclass 11, count 2 2006.285.09:13:16.19#ibcon#read 3, iclass 11, count 2 2006.285.09:13:16.19#ibcon#about to read 4, iclass 11, count 2 2006.285.09:13:16.19#ibcon#read 4, iclass 11, count 2 2006.285.09:13:16.19#ibcon#about to read 5, iclass 11, count 2 2006.285.09:13:16.19#ibcon#read 5, iclass 11, count 2 2006.285.09:13:16.19#ibcon#about to read 6, iclass 11, count 2 2006.285.09:13:16.19#ibcon#read 6, iclass 11, count 2 2006.285.09:13:16.19#ibcon#end of sib2, iclass 11, count 2 2006.285.09:13:16.19#ibcon#*mode == 0, iclass 11, count 2 2006.285.09:13:16.19#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.09:13:16.19#ibcon#[27=AT07-04\r\n] 2006.285.09:13:16.19#ibcon#*before write, iclass 11, count 2 2006.285.09:13:16.19#ibcon#enter sib2, iclass 11, count 2 2006.285.09:13:16.19#ibcon#flushed, iclass 11, count 2 2006.285.09:13:16.19#ibcon#about to write, iclass 11, count 2 2006.285.09:13:16.19#ibcon#wrote, iclass 11, count 2 2006.285.09:13:16.19#ibcon#about to read 3, iclass 11, count 2 2006.285.09:13:16.22#ibcon#read 3, iclass 11, count 2 2006.285.09:13:16.22#ibcon#about to read 4, iclass 11, count 2 2006.285.09:13:16.22#ibcon#read 4, iclass 11, count 2 2006.285.09:13:16.22#ibcon#about to read 5, iclass 11, count 2 2006.285.09:13:16.22#ibcon#read 5, iclass 11, count 2 2006.285.09:13:16.22#ibcon#about to read 6, iclass 11, count 2 2006.285.09:13:16.22#ibcon#read 6, iclass 11, count 2 2006.285.09:13:16.22#ibcon#end of sib2, iclass 11, count 2 2006.285.09:13:16.22#ibcon#*after write, iclass 11, count 2 2006.285.09:13:16.22#ibcon#*before return 0, iclass 11, count 2 2006.285.09:13:16.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:13:16.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:13:16.22#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.09:13:16.22#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:16.22#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:13:16.34#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:13:16.34#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:13:16.34#ibcon#enter wrdev, iclass 11, count 0 2006.285.09:13:16.34#ibcon#first serial, iclass 11, count 0 2006.285.09:13:16.34#ibcon#enter sib2, iclass 11, count 0 2006.285.09:13:16.34#ibcon#flushed, iclass 11, count 0 2006.285.09:13:16.34#ibcon#about to write, iclass 11, count 0 2006.285.09:13:16.34#ibcon#wrote, iclass 11, count 0 2006.285.09:13:16.34#ibcon#about to read 3, iclass 11, count 0 2006.285.09:13:16.36#ibcon#read 3, iclass 11, count 0 2006.285.09:13:16.36#ibcon#about to read 4, iclass 11, count 0 2006.285.09:13:16.36#ibcon#read 4, iclass 11, count 0 2006.285.09:13:16.36#ibcon#about to read 5, iclass 11, count 0 2006.285.09:13:16.36#ibcon#read 5, iclass 11, count 0 2006.285.09:13:16.36#ibcon#about to read 6, iclass 11, count 0 2006.285.09:13:16.36#ibcon#read 6, iclass 11, count 0 2006.285.09:13:16.36#ibcon#end of sib2, iclass 11, count 0 2006.285.09:13:16.36#ibcon#*mode == 0, iclass 11, count 0 2006.285.09:13:16.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.09:13:16.36#ibcon#[27=USB\r\n] 2006.285.09:13:16.36#ibcon#*before write, iclass 11, count 0 2006.285.09:13:16.36#ibcon#enter sib2, iclass 11, count 0 2006.285.09:13:16.36#ibcon#flushed, iclass 11, count 0 2006.285.09:13:16.36#ibcon#about to write, iclass 11, count 0 2006.285.09:13:16.36#ibcon#wrote, iclass 11, count 0 2006.285.09:13:16.36#ibcon#about to read 3, iclass 11, count 0 2006.285.09:13:16.39#ibcon#read 3, iclass 11, count 0 2006.285.09:13:16.39#ibcon#about to read 4, iclass 11, count 0 2006.285.09:13:16.39#ibcon#read 4, iclass 11, count 0 2006.285.09:13:16.39#ibcon#about to read 5, iclass 11, count 0 2006.285.09:13:16.39#ibcon#read 5, iclass 11, count 0 2006.285.09:13:16.39#ibcon#about to read 6, iclass 11, count 0 2006.285.09:13:16.39#ibcon#read 6, iclass 11, count 0 2006.285.09:13:16.39#ibcon#end of sib2, iclass 11, count 0 2006.285.09:13:16.39#ibcon#*after write, iclass 11, count 0 2006.285.09:13:16.39#ibcon#*before return 0, iclass 11, count 0 2006.285.09:13:16.39#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:13:16.39#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:13:16.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.09:13:16.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.09:13:16.39$vck44/vblo=8,744.99 2006.285.09:13:16.39#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.09:13:16.39#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.09:13:16.39#ibcon#ireg 17 cls_cnt 0 2006.285.09:13:16.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:13:16.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:13:16.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:13:16.39#ibcon#enter wrdev, iclass 13, count 0 2006.285.09:13:16.39#ibcon#first serial, iclass 13, count 0 2006.285.09:13:16.39#ibcon#enter sib2, iclass 13, count 0 2006.285.09:13:16.39#ibcon#flushed, iclass 13, count 0 2006.285.09:13:16.39#ibcon#about to write, iclass 13, count 0 2006.285.09:13:16.39#ibcon#wrote, iclass 13, count 0 2006.285.09:13:16.39#ibcon#about to read 3, iclass 13, count 0 2006.285.09:13:16.41#ibcon#read 3, iclass 13, count 0 2006.285.09:13:16.41#ibcon#about to read 4, iclass 13, count 0 2006.285.09:13:16.41#ibcon#read 4, iclass 13, count 0 2006.285.09:13:16.41#ibcon#about to read 5, iclass 13, count 0 2006.285.09:13:16.41#ibcon#read 5, iclass 13, count 0 2006.285.09:13:16.41#ibcon#about to read 6, iclass 13, count 0 2006.285.09:13:16.41#ibcon#read 6, iclass 13, count 0 2006.285.09:13:16.41#ibcon#end of sib2, iclass 13, count 0 2006.285.09:13:16.41#ibcon#*mode == 0, iclass 13, count 0 2006.285.09:13:16.41#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.09:13:16.41#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:13:16.41#ibcon#*before write, iclass 13, count 0 2006.285.09:13:16.41#ibcon#enter sib2, iclass 13, count 0 2006.285.09:13:16.41#ibcon#flushed, iclass 13, count 0 2006.285.09:13:16.41#ibcon#about to write, iclass 13, count 0 2006.285.09:13:16.41#ibcon#wrote, iclass 13, count 0 2006.285.09:13:16.41#ibcon#about to read 3, iclass 13, count 0 2006.285.09:13:16.45#ibcon#read 3, iclass 13, count 0 2006.285.09:13:16.45#ibcon#about to read 4, iclass 13, count 0 2006.285.09:13:16.45#ibcon#read 4, iclass 13, count 0 2006.285.09:13:16.45#ibcon#about to read 5, iclass 13, count 0 2006.285.09:13:16.45#ibcon#read 5, iclass 13, count 0 2006.285.09:13:16.45#ibcon#about to read 6, iclass 13, count 0 2006.285.09:13:16.45#ibcon#read 6, iclass 13, count 0 2006.285.09:13:16.45#ibcon#end of sib2, iclass 13, count 0 2006.285.09:13:16.45#ibcon#*after write, iclass 13, count 0 2006.285.09:13:16.45#ibcon#*before return 0, iclass 13, count 0 2006.285.09:13:16.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:13:16.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:13:16.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.09:13:16.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.09:13:16.45$vck44/vb=8,4 2006.285.09:13:16.45#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.09:13:16.45#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.09:13:16.45#ibcon#ireg 11 cls_cnt 2 2006.285.09:13:16.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:13:16.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:13:16.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:13:16.51#ibcon#enter wrdev, iclass 15, count 2 2006.285.09:13:16.51#ibcon#first serial, iclass 15, count 2 2006.285.09:13:16.51#ibcon#enter sib2, iclass 15, count 2 2006.285.09:13:16.51#ibcon#flushed, iclass 15, count 2 2006.285.09:13:16.51#ibcon#about to write, iclass 15, count 2 2006.285.09:13:16.51#ibcon#wrote, iclass 15, count 2 2006.285.09:13:16.51#ibcon#about to read 3, iclass 15, count 2 2006.285.09:13:16.53#ibcon#read 3, iclass 15, count 2 2006.285.09:13:16.53#ibcon#about to read 4, iclass 15, count 2 2006.285.09:13:16.53#ibcon#read 4, iclass 15, count 2 2006.285.09:13:16.53#ibcon#about to read 5, iclass 15, count 2 2006.285.09:13:16.53#ibcon#read 5, iclass 15, count 2 2006.285.09:13:16.53#ibcon#about to read 6, iclass 15, count 2 2006.285.09:13:16.53#ibcon#read 6, iclass 15, count 2 2006.285.09:13:16.53#ibcon#end of sib2, iclass 15, count 2 2006.285.09:13:16.53#ibcon#*mode == 0, iclass 15, count 2 2006.285.09:13:16.53#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.09:13:16.53#ibcon#[27=AT08-04\r\n] 2006.285.09:13:16.53#ibcon#*before write, iclass 15, count 2 2006.285.09:13:16.53#ibcon#enter sib2, iclass 15, count 2 2006.285.09:13:16.53#ibcon#flushed, iclass 15, count 2 2006.285.09:13:16.53#ibcon#about to write, iclass 15, count 2 2006.285.09:13:16.53#ibcon#wrote, iclass 15, count 2 2006.285.09:13:16.53#ibcon#about to read 3, iclass 15, count 2 2006.285.09:13:16.56#ibcon#read 3, iclass 15, count 2 2006.285.09:13:16.56#ibcon#about to read 4, iclass 15, count 2 2006.285.09:13:16.56#ibcon#read 4, iclass 15, count 2 2006.285.09:13:16.56#ibcon#about to read 5, iclass 15, count 2 2006.285.09:13:16.56#ibcon#read 5, iclass 15, count 2 2006.285.09:13:16.56#ibcon#about to read 6, iclass 15, count 2 2006.285.09:13:16.56#ibcon#read 6, iclass 15, count 2 2006.285.09:13:16.56#ibcon#end of sib2, iclass 15, count 2 2006.285.09:13:16.56#ibcon#*after write, iclass 15, count 2 2006.285.09:13:16.56#ibcon#*before return 0, iclass 15, count 2 2006.285.09:13:16.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:13:16.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:13:16.56#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.09:13:16.56#ibcon#ireg 7 cls_cnt 0 2006.285.09:13:16.56#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:13:16.68#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:13:16.68#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:13:16.68#ibcon#enter wrdev, iclass 15, count 0 2006.285.09:13:16.68#ibcon#first serial, iclass 15, count 0 2006.285.09:13:16.68#ibcon#enter sib2, iclass 15, count 0 2006.285.09:13:16.68#ibcon#flushed, iclass 15, count 0 2006.285.09:13:16.68#ibcon#about to write, iclass 15, count 0 2006.285.09:13:16.68#ibcon#wrote, iclass 15, count 0 2006.285.09:13:16.68#ibcon#about to read 3, iclass 15, count 0 2006.285.09:13:16.70#ibcon#read 3, iclass 15, count 0 2006.285.09:13:16.70#ibcon#about to read 4, iclass 15, count 0 2006.285.09:13:16.70#ibcon#read 4, iclass 15, count 0 2006.285.09:13:16.70#ibcon#about to read 5, iclass 15, count 0 2006.285.09:13:16.70#ibcon#read 5, iclass 15, count 0 2006.285.09:13:16.70#ibcon#about to read 6, iclass 15, count 0 2006.285.09:13:16.70#ibcon#read 6, iclass 15, count 0 2006.285.09:13:16.70#ibcon#end of sib2, iclass 15, count 0 2006.285.09:13:16.70#ibcon#*mode == 0, iclass 15, count 0 2006.285.09:13:16.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.09:13:16.70#ibcon#[27=USB\r\n] 2006.285.09:13:16.70#ibcon#*before write, iclass 15, count 0 2006.285.09:13:16.70#ibcon#enter sib2, iclass 15, count 0 2006.285.09:13:16.70#ibcon#flushed, iclass 15, count 0 2006.285.09:13:16.70#ibcon#about to write, iclass 15, count 0 2006.285.09:13:16.70#ibcon#wrote, iclass 15, count 0 2006.285.09:13:16.70#ibcon#about to read 3, iclass 15, count 0 2006.285.09:13:16.73#ibcon#read 3, iclass 15, count 0 2006.285.09:13:16.73#ibcon#about to read 4, iclass 15, count 0 2006.285.09:13:16.73#ibcon#read 4, iclass 15, count 0 2006.285.09:13:16.73#ibcon#about to read 5, iclass 15, count 0 2006.285.09:13:16.73#ibcon#read 5, iclass 15, count 0 2006.285.09:13:16.73#ibcon#about to read 6, iclass 15, count 0 2006.285.09:13:16.73#ibcon#read 6, iclass 15, count 0 2006.285.09:13:16.73#ibcon#end of sib2, iclass 15, count 0 2006.285.09:13:16.73#ibcon#*after write, iclass 15, count 0 2006.285.09:13:16.73#ibcon#*before return 0, iclass 15, count 0 2006.285.09:13:16.73#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:13:16.73#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:13:16.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.09:13:16.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.09:13:16.73$vck44/vabw=wide 2006.285.09:13:16.73#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.09:13:16.73#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.09:13:16.73#ibcon#ireg 8 cls_cnt 0 2006.285.09:13:16.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:13:16.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:13:16.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:13:16.73#ibcon#enter wrdev, iclass 17, count 0 2006.285.09:13:16.73#ibcon#first serial, iclass 17, count 0 2006.285.09:13:16.73#ibcon#enter sib2, iclass 17, count 0 2006.285.09:13:16.73#ibcon#flushed, iclass 17, count 0 2006.285.09:13:16.73#ibcon#about to write, iclass 17, count 0 2006.285.09:13:16.73#ibcon#wrote, iclass 17, count 0 2006.285.09:13:16.73#ibcon#about to read 3, iclass 17, count 0 2006.285.09:13:16.75#ibcon#read 3, iclass 17, count 0 2006.285.09:13:16.75#ibcon#about to read 4, iclass 17, count 0 2006.285.09:13:16.75#ibcon#read 4, iclass 17, count 0 2006.285.09:13:16.75#ibcon#about to read 5, iclass 17, count 0 2006.285.09:13:16.75#ibcon#read 5, iclass 17, count 0 2006.285.09:13:16.75#ibcon#about to read 6, iclass 17, count 0 2006.285.09:13:16.75#ibcon#read 6, iclass 17, count 0 2006.285.09:13:16.75#ibcon#end of sib2, iclass 17, count 0 2006.285.09:13:16.75#ibcon#*mode == 0, iclass 17, count 0 2006.285.09:13:16.75#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.09:13:16.75#ibcon#[25=BW32\r\n] 2006.285.09:13:16.75#ibcon#*before write, iclass 17, count 0 2006.285.09:13:16.75#ibcon#enter sib2, iclass 17, count 0 2006.285.09:13:16.75#ibcon#flushed, iclass 17, count 0 2006.285.09:13:16.75#ibcon#about to write, iclass 17, count 0 2006.285.09:13:16.75#ibcon#wrote, iclass 17, count 0 2006.285.09:13:16.75#ibcon#about to read 3, iclass 17, count 0 2006.285.09:13:16.78#ibcon#read 3, iclass 17, count 0 2006.285.09:13:16.78#ibcon#about to read 4, iclass 17, count 0 2006.285.09:13:16.78#ibcon#read 4, iclass 17, count 0 2006.285.09:13:16.78#ibcon#about to read 5, iclass 17, count 0 2006.285.09:13:16.78#ibcon#read 5, iclass 17, count 0 2006.285.09:13:16.78#ibcon#about to read 6, iclass 17, count 0 2006.285.09:13:16.78#ibcon#read 6, iclass 17, count 0 2006.285.09:13:16.78#ibcon#end of sib2, iclass 17, count 0 2006.285.09:13:16.78#ibcon#*after write, iclass 17, count 0 2006.285.09:13:16.78#ibcon#*before return 0, iclass 17, count 0 2006.285.09:13:16.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:13:16.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:13:16.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.09:13:16.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.09:13:16.78$vck44/vbbw=wide 2006.285.09:13:16.78#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.09:13:16.78#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.09:13:16.78#ibcon#ireg 8 cls_cnt 0 2006.285.09:13:16.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:13:16.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:13:16.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:13:16.85#ibcon#enter wrdev, iclass 19, count 0 2006.285.09:13:16.85#ibcon#first serial, iclass 19, count 0 2006.285.09:13:16.85#ibcon#enter sib2, iclass 19, count 0 2006.285.09:13:16.85#ibcon#flushed, iclass 19, count 0 2006.285.09:13:16.85#ibcon#about to write, iclass 19, count 0 2006.285.09:13:16.85#ibcon#wrote, iclass 19, count 0 2006.285.09:13:16.85#ibcon#about to read 3, iclass 19, count 0 2006.285.09:13:16.87#ibcon#read 3, iclass 19, count 0 2006.285.09:13:16.87#ibcon#about to read 4, iclass 19, count 0 2006.285.09:13:16.87#ibcon#read 4, iclass 19, count 0 2006.285.09:13:16.87#ibcon#about to read 5, iclass 19, count 0 2006.285.09:13:16.87#ibcon#read 5, iclass 19, count 0 2006.285.09:13:16.87#ibcon#about to read 6, iclass 19, count 0 2006.285.09:13:16.87#ibcon#read 6, iclass 19, count 0 2006.285.09:13:16.87#ibcon#end of sib2, iclass 19, count 0 2006.285.09:13:16.87#ibcon#*mode == 0, iclass 19, count 0 2006.285.09:13:16.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.09:13:16.87#ibcon#[27=BW32\r\n] 2006.285.09:13:16.87#ibcon#*before write, iclass 19, count 0 2006.285.09:13:16.87#ibcon#enter sib2, iclass 19, count 0 2006.285.09:13:16.87#ibcon#flushed, iclass 19, count 0 2006.285.09:13:16.87#ibcon#about to write, iclass 19, count 0 2006.285.09:13:16.87#ibcon#wrote, iclass 19, count 0 2006.285.09:13:16.87#ibcon#about to read 3, iclass 19, count 0 2006.285.09:13:16.90#ibcon#read 3, iclass 19, count 0 2006.285.09:13:16.90#ibcon#about to read 4, iclass 19, count 0 2006.285.09:13:16.90#ibcon#read 4, iclass 19, count 0 2006.285.09:13:16.90#ibcon#about to read 5, iclass 19, count 0 2006.285.09:13:16.90#ibcon#read 5, iclass 19, count 0 2006.285.09:13:16.90#ibcon#about to read 6, iclass 19, count 0 2006.285.09:13:16.90#ibcon#read 6, iclass 19, count 0 2006.285.09:13:16.90#ibcon#end of sib2, iclass 19, count 0 2006.285.09:13:16.90#ibcon#*after write, iclass 19, count 0 2006.285.09:13:16.90#ibcon#*before return 0, iclass 19, count 0 2006.285.09:13:16.90#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:13:16.90#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:13:16.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.09:13:16.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.09:13:16.90$setupk4/ifdk4 2006.285.09:13:16.90$ifdk4/lo= 2006.285.09:13:16.90$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:13:16.90$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:13:16.90$ifdk4/patch= 2006.285.09:13:16.90$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:13:16.90$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:13:16.90$setupk4/!*+20s 2006.285.09:13:19.22#abcon#<5=/02 0.8 1.6 20.53 861014.9\r\n> 2006.285.09:13:19.24#abcon#{5=INTERFACE CLEAR} 2006.285.09:13:19.30#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:13:29.39#abcon#<5=/02 0.7 1.5 20.52 861014.9\r\n> 2006.285.09:13:29.41#abcon#{5=INTERFACE CLEAR} 2006.285.09:13:29.47#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:13:31.41$setupk4/"tpicd 2006.285.09:13:31.41$setupk4/echo=off 2006.285.09:13:31.41$setupk4/xlog=off 2006.285.09:13:31.41:!2006.285.09:17:55 2006.285.09:14:02.13#trakl#Source acquired 2006.285.09:14:02.13#flagr#flagr/antenna,acquired 2006.285.09:17:55.00:preob 2006.285.09:17:55.14/onsource/TRACKING 2006.285.09:17:55.14:!2006.285.09:18:05 2006.285.09:18:05.00:"tape 2006.285.09:18:05.00:"st=record 2006.285.09:18:05.00:data_valid=on 2006.285.09:18:05.00:midob 2006.285.09:18:05.14/onsource/TRACKING 2006.285.09:18:05.14/wx/20.23,1014.9,88 2006.285.09:18:05.28/cable/+6.4790E-03 2006.285.09:18:06.37/va/01,07,usb,yes,32,35 2006.285.09:18:06.37/va/02,06,usb,yes,32,32 2006.285.09:18:06.37/va/03,07,usb,yes,31,33 2006.285.09:18:06.37/va/04,06,usb,yes,33,34 2006.285.09:18:06.37/va/05,03,usb,yes,32,33 2006.285.09:18:06.37/va/06,04,usb,yes,29,29 2006.285.09:18:06.37/va/07,04,usb,yes,30,30 2006.285.09:18:06.37/va/08,03,usb,yes,30,37 2006.285.09:18:06.60/valo/01,524.99,yes,locked 2006.285.09:18:06.60/valo/02,534.99,yes,locked 2006.285.09:18:06.60/valo/03,564.99,yes,locked 2006.285.09:18:06.60/valo/04,624.99,yes,locked 2006.285.09:18:06.60/valo/05,734.99,yes,locked 2006.285.09:18:06.60/valo/06,814.99,yes,locked 2006.285.09:18:06.60/valo/07,864.99,yes,locked 2006.285.09:18:06.60/valo/08,884.99,yes,locked 2006.285.09:18:07.69/vb/01,04,usb,yes,30,28 2006.285.09:18:07.69/vb/02,05,usb,yes,29,29 2006.285.09:18:07.69/vb/03,04,usb,yes,30,33 2006.285.09:18:07.69/vb/04,05,usb,yes,30,29 2006.285.09:18:07.69/vb/05,04,usb,yes,26,29 2006.285.09:18:07.69/vb/06,03,usb,yes,38,34 2006.285.09:18:07.69/vb/07,04,usb,yes,31,31 2006.285.09:18:07.69/vb/08,04,usb,yes,28,32 2006.285.09:18:07.92/vblo/01,629.99,yes,locked 2006.285.09:18:07.92/vblo/02,634.99,yes,locked 2006.285.09:18:07.92/vblo/03,649.99,yes,locked 2006.285.09:18:07.92/vblo/04,679.99,yes,locked 2006.285.09:18:07.92/vblo/05,709.99,yes,locked 2006.285.09:18:07.92/vblo/06,719.99,yes,locked 2006.285.09:18:07.92/vblo/07,734.99,yes,locked 2006.285.09:18:07.92/vblo/08,744.99,yes,locked 2006.285.09:18:08.07/vabw/8 2006.285.09:18:08.22/vbbw/8 2006.285.09:18:08.31/xfe/off,on,12.2 2006.285.09:18:08.69/ifatt/23,28,28,28 2006.285.09:18:09.08/fmout-gps/S +2.83E-07 2006.285.09:18:09.10:!2006.285.09:18:55 2006.285.09:18:55.00:data_valid=off 2006.285.09:18:55.00:"et 2006.285.09:18:55.00:!+3s 2006.285.09:18:58.01:"tape 2006.285.09:18:58.01:postob 2006.285.09:18:58.18/cable/+6.4807E-03 2006.285.09:18:58.18/wx/20.19,1014.9,88 2006.285.09:18:59.07/fmout-gps/S +2.84E-07 2006.285.09:18:59.07:scan_name=285-0921,jd0610,230 2006.285.09:18:59.07:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.285.09:19:00.14#flagr#flagr/antenna,new-source 2006.285.09:19:00.14:checkk5 2006.285.09:19:00.50/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:19:00.88/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:19:01.25/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:19:01.62/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:19:02.19/chk_obsdata//k5ts1/T2850918??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.09:19:02.77/chk_obsdata//k5ts2/T2850918??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.09:19:03.28/chk_obsdata//k5ts3/T2850918??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.09:19:03.67/chk_obsdata//k5ts4/T2850918??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.09:19:04.42/k5log//k5ts1_log_newline 2006.285.09:19:05.25/k5log//k5ts2_log_newline 2006.285.09:19:06.02/k5log//k5ts3_log_newline 2006.285.09:19:06.83/k5log//k5ts4_log_newline 2006.285.09:19:06.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:19:06.85:setupk4=1 2006.285.09:19:06.85$setupk4/echo=on 2006.285.09:19:06.85$setupk4/pcalon 2006.285.09:19:06.85$pcalon/"no phase cal control is implemented here 2006.285.09:19:06.85$setupk4/"tpicd=stop 2006.285.09:19:06.85$setupk4/"rec=synch_on 2006.285.09:19:06.85$setupk4/"rec_mode=128 2006.285.09:19:06.85$setupk4/!* 2006.285.09:19:06.85$setupk4/recpk4 2006.285.09:19:06.85$recpk4/recpatch= 2006.285.09:19:06.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:19:06.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:19:06.86$setupk4/vck44 2006.285.09:19:06.86$vck44/valo=1,524.99 2006.285.09:19:06.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.09:19:06.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.09:19:06.86#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:06.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:19:06.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:19:06.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:19:06.86#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:19:06.86#ibcon#first serial, iclass 20, count 0 2006.285.09:19:06.86#ibcon#enter sib2, iclass 20, count 0 2006.285.09:19:06.86#ibcon#flushed, iclass 20, count 0 2006.285.09:19:06.86#ibcon#about to write, iclass 20, count 0 2006.285.09:19:06.86#ibcon#wrote, iclass 20, count 0 2006.285.09:19:06.86#ibcon#about to read 3, iclass 20, count 0 2006.285.09:19:06.88#ibcon#read 3, iclass 20, count 0 2006.285.09:19:06.88#ibcon#about to read 4, iclass 20, count 0 2006.285.09:19:06.88#ibcon#read 4, iclass 20, count 0 2006.285.09:19:06.88#ibcon#about to read 5, iclass 20, count 0 2006.285.09:19:06.88#ibcon#read 5, iclass 20, count 0 2006.285.09:19:06.88#ibcon#about to read 6, iclass 20, count 0 2006.285.09:19:06.88#ibcon#read 6, iclass 20, count 0 2006.285.09:19:06.88#ibcon#end of sib2, iclass 20, count 0 2006.285.09:19:06.88#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:19:06.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:19:06.88#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:19:06.88#ibcon#*before write, iclass 20, count 0 2006.285.09:19:06.88#ibcon#enter sib2, iclass 20, count 0 2006.285.09:19:06.88#ibcon#flushed, iclass 20, count 0 2006.285.09:19:06.88#ibcon#about to write, iclass 20, count 0 2006.285.09:19:06.88#ibcon#wrote, iclass 20, count 0 2006.285.09:19:06.88#ibcon#about to read 3, iclass 20, count 0 2006.285.09:19:06.93#ibcon#read 3, iclass 20, count 0 2006.285.09:19:06.93#ibcon#about to read 4, iclass 20, count 0 2006.285.09:19:06.93#ibcon#read 4, iclass 20, count 0 2006.285.09:19:06.93#ibcon#about to read 5, iclass 20, count 0 2006.285.09:19:06.93#ibcon#read 5, iclass 20, count 0 2006.285.09:19:06.93#ibcon#about to read 6, iclass 20, count 0 2006.285.09:19:06.93#ibcon#read 6, iclass 20, count 0 2006.285.09:19:06.93#ibcon#end of sib2, iclass 20, count 0 2006.285.09:19:06.93#ibcon#*after write, iclass 20, count 0 2006.285.09:19:06.93#ibcon#*before return 0, iclass 20, count 0 2006.285.09:19:06.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:19:06.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:19:06.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:19:06.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:19:06.93$vck44/va=1,7 2006.285.09:19:06.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.09:19:06.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.09:19:06.93#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:06.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:19:06.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:19:06.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:19:06.93#ibcon#enter wrdev, iclass 22, count 2 2006.285.09:19:06.93#ibcon#first serial, iclass 22, count 2 2006.285.09:19:06.93#ibcon#enter sib2, iclass 22, count 2 2006.285.09:19:06.93#ibcon#flushed, iclass 22, count 2 2006.285.09:19:06.93#ibcon#about to write, iclass 22, count 2 2006.285.09:19:06.93#ibcon#wrote, iclass 22, count 2 2006.285.09:19:06.93#ibcon#about to read 3, iclass 22, count 2 2006.285.09:19:06.95#ibcon#read 3, iclass 22, count 2 2006.285.09:19:06.95#ibcon#about to read 4, iclass 22, count 2 2006.285.09:19:06.95#ibcon#read 4, iclass 22, count 2 2006.285.09:19:06.95#ibcon#about to read 5, iclass 22, count 2 2006.285.09:19:06.95#ibcon#read 5, iclass 22, count 2 2006.285.09:19:06.95#ibcon#about to read 6, iclass 22, count 2 2006.285.09:19:06.95#ibcon#read 6, iclass 22, count 2 2006.285.09:19:06.95#ibcon#end of sib2, iclass 22, count 2 2006.285.09:19:06.95#ibcon#*mode == 0, iclass 22, count 2 2006.285.09:19:06.95#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.09:19:06.95#ibcon#[25=AT01-07\r\n] 2006.285.09:19:06.95#ibcon#*before write, iclass 22, count 2 2006.285.09:19:06.95#ibcon#enter sib2, iclass 22, count 2 2006.285.09:19:06.95#ibcon#flushed, iclass 22, count 2 2006.285.09:19:06.95#ibcon#about to write, iclass 22, count 2 2006.285.09:19:06.95#ibcon#wrote, iclass 22, count 2 2006.285.09:19:06.95#ibcon#about to read 3, iclass 22, count 2 2006.285.09:19:06.98#ibcon#read 3, iclass 22, count 2 2006.285.09:19:06.98#ibcon#about to read 4, iclass 22, count 2 2006.285.09:19:06.98#ibcon#read 4, iclass 22, count 2 2006.285.09:19:06.98#ibcon#about to read 5, iclass 22, count 2 2006.285.09:19:06.98#ibcon#read 5, iclass 22, count 2 2006.285.09:19:06.98#ibcon#about to read 6, iclass 22, count 2 2006.285.09:19:06.98#ibcon#read 6, iclass 22, count 2 2006.285.09:19:06.98#ibcon#end of sib2, iclass 22, count 2 2006.285.09:19:06.98#ibcon#*after write, iclass 22, count 2 2006.285.09:19:06.98#ibcon#*before return 0, iclass 22, count 2 2006.285.09:19:06.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:19:06.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:19:06.98#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.09:19:06.98#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:06.98#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:19:07.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:19:07.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:19:07.10#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:19:07.10#ibcon#first serial, iclass 22, count 0 2006.285.09:19:07.10#ibcon#enter sib2, iclass 22, count 0 2006.285.09:19:07.10#ibcon#flushed, iclass 22, count 0 2006.285.09:19:07.10#ibcon#about to write, iclass 22, count 0 2006.285.09:19:07.10#ibcon#wrote, iclass 22, count 0 2006.285.09:19:07.10#ibcon#about to read 3, iclass 22, count 0 2006.285.09:19:07.12#ibcon#read 3, iclass 22, count 0 2006.285.09:19:07.12#ibcon#about to read 4, iclass 22, count 0 2006.285.09:19:07.12#ibcon#read 4, iclass 22, count 0 2006.285.09:19:07.12#ibcon#about to read 5, iclass 22, count 0 2006.285.09:19:07.12#ibcon#read 5, iclass 22, count 0 2006.285.09:19:07.12#ibcon#about to read 6, iclass 22, count 0 2006.285.09:19:07.12#ibcon#read 6, iclass 22, count 0 2006.285.09:19:07.12#ibcon#end of sib2, iclass 22, count 0 2006.285.09:19:07.12#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:19:07.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:19:07.12#ibcon#[25=USB\r\n] 2006.285.09:19:07.12#ibcon#*before write, iclass 22, count 0 2006.285.09:19:07.12#ibcon#enter sib2, iclass 22, count 0 2006.285.09:19:07.12#ibcon#flushed, iclass 22, count 0 2006.285.09:19:07.12#ibcon#about to write, iclass 22, count 0 2006.285.09:19:07.12#ibcon#wrote, iclass 22, count 0 2006.285.09:19:07.12#ibcon#about to read 3, iclass 22, count 0 2006.285.09:19:07.15#ibcon#read 3, iclass 22, count 0 2006.285.09:19:07.15#ibcon#about to read 4, iclass 22, count 0 2006.285.09:19:07.15#ibcon#read 4, iclass 22, count 0 2006.285.09:19:07.15#ibcon#about to read 5, iclass 22, count 0 2006.285.09:19:07.15#ibcon#read 5, iclass 22, count 0 2006.285.09:19:07.15#ibcon#about to read 6, iclass 22, count 0 2006.285.09:19:07.15#ibcon#read 6, iclass 22, count 0 2006.285.09:19:07.15#ibcon#end of sib2, iclass 22, count 0 2006.285.09:19:07.15#ibcon#*after write, iclass 22, count 0 2006.285.09:19:07.15#ibcon#*before return 0, iclass 22, count 0 2006.285.09:19:07.15#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:19:07.15#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:19:07.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:19:07.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:19:07.15$vck44/valo=2,534.99 2006.285.09:19:07.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.09:19:07.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.09:19:07.15#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:07.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:19:07.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:19:07.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:19:07.15#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:19:07.15#ibcon#first serial, iclass 24, count 0 2006.285.09:19:07.15#ibcon#enter sib2, iclass 24, count 0 2006.285.09:19:07.15#ibcon#flushed, iclass 24, count 0 2006.285.09:19:07.15#ibcon#about to write, iclass 24, count 0 2006.285.09:19:07.15#ibcon#wrote, iclass 24, count 0 2006.285.09:19:07.15#ibcon#about to read 3, iclass 24, count 0 2006.285.09:19:07.17#ibcon#read 3, iclass 24, count 0 2006.285.09:19:07.17#ibcon#about to read 4, iclass 24, count 0 2006.285.09:19:07.17#ibcon#read 4, iclass 24, count 0 2006.285.09:19:07.17#ibcon#about to read 5, iclass 24, count 0 2006.285.09:19:07.17#ibcon#read 5, iclass 24, count 0 2006.285.09:19:07.17#ibcon#about to read 6, iclass 24, count 0 2006.285.09:19:07.17#ibcon#read 6, iclass 24, count 0 2006.285.09:19:07.17#ibcon#end of sib2, iclass 24, count 0 2006.285.09:19:07.17#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:19:07.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:19:07.17#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:19:07.17#ibcon#*before write, iclass 24, count 0 2006.285.09:19:07.17#ibcon#enter sib2, iclass 24, count 0 2006.285.09:19:07.17#ibcon#flushed, iclass 24, count 0 2006.285.09:19:07.17#ibcon#about to write, iclass 24, count 0 2006.285.09:19:07.17#ibcon#wrote, iclass 24, count 0 2006.285.09:19:07.17#ibcon#about to read 3, iclass 24, count 0 2006.285.09:19:07.21#ibcon#read 3, iclass 24, count 0 2006.285.09:19:07.21#ibcon#about to read 4, iclass 24, count 0 2006.285.09:19:07.21#ibcon#read 4, iclass 24, count 0 2006.285.09:19:07.21#ibcon#about to read 5, iclass 24, count 0 2006.285.09:19:07.21#ibcon#read 5, iclass 24, count 0 2006.285.09:19:07.21#ibcon#about to read 6, iclass 24, count 0 2006.285.09:19:07.21#ibcon#read 6, iclass 24, count 0 2006.285.09:19:07.21#ibcon#end of sib2, iclass 24, count 0 2006.285.09:19:07.21#ibcon#*after write, iclass 24, count 0 2006.285.09:19:07.21#ibcon#*before return 0, iclass 24, count 0 2006.285.09:19:07.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:19:07.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:19:07.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:19:07.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:19:07.21$vck44/va=2,6 2006.285.09:19:07.21#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.09:19:07.21#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.09:19:07.21#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:07.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:19:07.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:19:07.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:19:07.27#ibcon#enter wrdev, iclass 26, count 2 2006.285.09:19:07.27#ibcon#first serial, iclass 26, count 2 2006.285.09:19:07.27#ibcon#enter sib2, iclass 26, count 2 2006.285.09:19:07.27#ibcon#flushed, iclass 26, count 2 2006.285.09:19:07.27#ibcon#about to write, iclass 26, count 2 2006.285.09:19:07.27#ibcon#wrote, iclass 26, count 2 2006.285.09:19:07.27#ibcon#about to read 3, iclass 26, count 2 2006.285.09:19:07.29#ibcon#read 3, iclass 26, count 2 2006.285.09:19:07.29#ibcon#about to read 4, iclass 26, count 2 2006.285.09:19:07.29#ibcon#read 4, iclass 26, count 2 2006.285.09:19:07.29#ibcon#about to read 5, iclass 26, count 2 2006.285.09:19:07.29#ibcon#read 5, iclass 26, count 2 2006.285.09:19:07.29#ibcon#about to read 6, iclass 26, count 2 2006.285.09:19:07.29#ibcon#read 6, iclass 26, count 2 2006.285.09:19:07.29#ibcon#end of sib2, iclass 26, count 2 2006.285.09:19:07.29#ibcon#*mode == 0, iclass 26, count 2 2006.285.09:19:07.29#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.09:19:07.29#ibcon#[25=AT02-06\r\n] 2006.285.09:19:07.29#ibcon#*before write, iclass 26, count 2 2006.285.09:19:07.29#ibcon#enter sib2, iclass 26, count 2 2006.285.09:19:07.29#ibcon#flushed, iclass 26, count 2 2006.285.09:19:07.29#ibcon#about to write, iclass 26, count 2 2006.285.09:19:07.29#ibcon#wrote, iclass 26, count 2 2006.285.09:19:07.29#ibcon#about to read 3, iclass 26, count 2 2006.285.09:19:07.32#ibcon#read 3, iclass 26, count 2 2006.285.09:19:07.32#ibcon#about to read 4, iclass 26, count 2 2006.285.09:19:07.32#ibcon#read 4, iclass 26, count 2 2006.285.09:19:07.32#ibcon#about to read 5, iclass 26, count 2 2006.285.09:19:07.32#ibcon#read 5, iclass 26, count 2 2006.285.09:19:07.32#ibcon#about to read 6, iclass 26, count 2 2006.285.09:19:07.32#ibcon#read 6, iclass 26, count 2 2006.285.09:19:07.32#ibcon#end of sib2, iclass 26, count 2 2006.285.09:19:07.32#ibcon#*after write, iclass 26, count 2 2006.285.09:19:07.32#ibcon#*before return 0, iclass 26, count 2 2006.285.09:19:07.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:19:07.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:19:07.32#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.09:19:07.32#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:07.32#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:19:07.45#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:19:07.45#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:19:07.45#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:19:07.45#ibcon#first serial, iclass 26, count 0 2006.285.09:19:07.45#ibcon#enter sib2, iclass 26, count 0 2006.285.09:19:07.45#ibcon#flushed, iclass 26, count 0 2006.285.09:19:07.45#ibcon#about to write, iclass 26, count 0 2006.285.09:19:07.45#ibcon#wrote, iclass 26, count 0 2006.285.09:19:07.45#ibcon#about to read 3, iclass 26, count 0 2006.285.09:19:07.47#ibcon#read 3, iclass 26, count 0 2006.285.09:19:07.47#ibcon#about to read 4, iclass 26, count 0 2006.285.09:19:07.47#ibcon#read 4, iclass 26, count 0 2006.285.09:19:07.47#ibcon#about to read 5, iclass 26, count 0 2006.285.09:19:07.47#ibcon#read 5, iclass 26, count 0 2006.285.09:19:07.47#ibcon#about to read 6, iclass 26, count 0 2006.285.09:19:07.47#ibcon#read 6, iclass 26, count 0 2006.285.09:19:07.47#ibcon#end of sib2, iclass 26, count 0 2006.285.09:19:07.47#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:19:07.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:19:07.47#ibcon#[25=USB\r\n] 2006.285.09:19:07.47#ibcon#*before write, iclass 26, count 0 2006.285.09:19:07.47#ibcon#enter sib2, iclass 26, count 0 2006.285.09:19:07.47#ibcon#flushed, iclass 26, count 0 2006.285.09:19:07.47#ibcon#about to write, iclass 26, count 0 2006.285.09:19:07.47#ibcon#wrote, iclass 26, count 0 2006.285.09:19:07.47#ibcon#about to read 3, iclass 26, count 0 2006.285.09:19:07.50#ibcon#read 3, iclass 26, count 0 2006.285.09:19:07.50#ibcon#about to read 4, iclass 26, count 0 2006.285.09:19:07.50#ibcon#read 4, iclass 26, count 0 2006.285.09:19:07.50#ibcon#about to read 5, iclass 26, count 0 2006.285.09:19:07.50#ibcon#read 5, iclass 26, count 0 2006.285.09:19:07.50#ibcon#about to read 6, iclass 26, count 0 2006.285.09:19:07.50#ibcon#read 6, iclass 26, count 0 2006.285.09:19:07.50#ibcon#end of sib2, iclass 26, count 0 2006.285.09:19:07.50#ibcon#*after write, iclass 26, count 0 2006.285.09:19:07.50#ibcon#*before return 0, iclass 26, count 0 2006.285.09:19:07.50#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:19:07.50#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:19:07.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:19:07.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:19:07.50$vck44/valo=3,564.99 2006.285.09:19:07.50#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.09:19:07.50#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.09:19:07.50#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:07.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:19:07.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:19:07.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:19:07.50#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:19:07.50#ibcon#first serial, iclass 28, count 0 2006.285.09:19:07.50#ibcon#enter sib2, iclass 28, count 0 2006.285.09:19:07.50#ibcon#flushed, iclass 28, count 0 2006.285.09:19:07.50#ibcon#about to write, iclass 28, count 0 2006.285.09:19:07.50#ibcon#wrote, iclass 28, count 0 2006.285.09:19:07.50#ibcon#about to read 3, iclass 28, count 0 2006.285.09:19:07.52#ibcon#read 3, iclass 28, count 0 2006.285.09:19:07.52#ibcon#about to read 4, iclass 28, count 0 2006.285.09:19:07.52#ibcon#read 4, iclass 28, count 0 2006.285.09:19:07.52#ibcon#about to read 5, iclass 28, count 0 2006.285.09:19:07.52#ibcon#read 5, iclass 28, count 0 2006.285.09:19:07.52#ibcon#about to read 6, iclass 28, count 0 2006.285.09:19:07.52#ibcon#read 6, iclass 28, count 0 2006.285.09:19:07.52#ibcon#end of sib2, iclass 28, count 0 2006.285.09:19:07.52#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:19:07.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:19:07.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:19:07.52#ibcon#*before write, iclass 28, count 0 2006.285.09:19:07.52#ibcon#enter sib2, iclass 28, count 0 2006.285.09:19:07.52#ibcon#flushed, iclass 28, count 0 2006.285.09:19:07.52#ibcon#about to write, iclass 28, count 0 2006.285.09:19:07.52#ibcon#wrote, iclass 28, count 0 2006.285.09:19:07.52#ibcon#about to read 3, iclass 28, count 0 2006.285.09:19:07.56#ibcon#read 3, iclass 28, count 0 2006.285.09:19:07.56#ibcon#about to read 4, iclass 28, count 0 2006.285.09:19:07.56#ibcon#read 4, iclass 28, count 0 2006.285.09:19:07.56#ibcon#about to read 5, iclass 28, count 0 2006.285.09:19:07.56#ibcon#read 5, iclass 28, count 0 2006.285.09:19:07.56#ibcon#about to read 6, iclass 28, count 0 2006.285.09:19:07.56#ibcon#read 6, iclass 28, count 0 2006.285.09:19:07.56#ibcon#end of sib2, iclass 28, count 0 2006.285.09:19:07.56#ibcon#*after write, iclass 28, count 0 2006.285.09:19:07.56#ibcon#*before return 0, iclass 28, count 0 2006.285.09:19:07.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:19:07.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:19:07.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:19:07.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:19:07.56$vck44/va=3,7 2006.285.09:19:07.56#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.09:19:07.56#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.09:19:07.56#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:07.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:19:07.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:19:07.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:19:07.62#ibcon#enter wrdev, iclass 30, count 2 2006.285.09:19:07.62#ibcon#first serial, iclass 30, count 2 2006.285.09:19:07.62#ibcon#enter sib2, iclass 30, count 2 2006.285.09:19:07.62#ibcon#flushed, iclass 30, count 2 2006.285.09:19:07.62#ibcon#about to write, iclass 30, count 2 2006.285.09:19:07.62#ibcon#wrote, iclass 30, count 2 2006.285.09:19:07.62#ibcon#about to read 3, iclass 30, count 2 2006.285.09:19:07.64#ibcon#read 3, iclass 30, count 2 2006.285.09:19:07.64#ibcon#about to read 4, iclass 30, count 2 2006.285.09:19:07.64#ibcon#read 4, iclass 30, count 2 2006.285.09:19:07.64#ibcon#about to read 5, iclass 30, count 2 2006.285.09:19:07.64#ibcon#read 5, iclass 30, count 2 2006.285.09:19:07.64#ibcon#about to read 6, iclass 30, count 2 2006.285.09:19:07.64#ibcon#read 6, iclass 30, count 2 2006.285.09:19:07.64#ibcon#end of sib2, iclass 30, count 2 2006.285.09:19:07.64#ibcon#*mode == 0, iclass 30, count 2 2006.285.09:19:07.64#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.09:19:07.64#ibcon#[25=AT03-07\r\n] 2006.285.09:19:07.64#ibcon#*before write, iclass 30, count 2 2006.285.09:19:07.64#ibcon#enter sib2, iclass 30, count 2 2006.285.09:19:07.64#ibcon#flushed, iclass 30, count 2 2006.285.09:19:07.64#ibcon#about to write, iclass 30, count 2 2006.285.09:19:07.64#ibcon#wrote, iclass 30, count 2 2006.285.09:19:07.64#ibcon#about to read 3, iclass 30, count 2 2006.285.09:19:07.67#ibcon#read 3, iclass 30, count 2 2006.285.09:19:07.67#ibcon#about to read 4, iclass 30, count 2 2006.285.09:19:07.67#ibcon#read 4, iclass 30, count 2 2006.285.09:19:07.67#ibcon#about to read 5, iclass 30, count 2 2006.285.09:19:07.67#ibcon#read 5, iclass 30, count 2 2006.285.09:19:07.67#ibcon#about to read 6, iclass 30, count 2 2006.285.09:19:07.67#ibcon#read 6, iclass 30, count 2 2006.285.09:19:07.67#ibcon#end of sib2, iclass 30, count 2 2006.285.09:19:07.67#ibcon#*after write, iclass 30, count 2 2006.285.09:19:07.67#ibcon#*before return 0, iclass 30, count 2 2006.285.09:19:07.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:19:07.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:19:07.67#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.09:19:07.67#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:07.67#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:19:07.79#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:19:07.79#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:19:07.79#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:19:07.79#ibcon#first serial, iclass 30, count 0 2006.285.09:19:07.79#ibcon#enter sib2, iclass 30, count 0 2006.285.09:19:07.79#ibcon#flushed, iclass 30, count 0 2006.285.09:19:07.79#ibcon#about to write, iclass 30, count 0 2006.285.09:19:07.79#ibcon#wrote, iclass 30, count 0 2006.285.09:19:07.79#ibcon#about to read 3, iclass 30, count 0 2006.285.09:19:07.81#ibcon#read 3, iclass 30, count 0 2006.285.09:19:07.81#ibcon#about to read 4, iclass 30, count 0 2006.285.09:19:07.81#ibcon#read 4, iclass 30, count 0 2006.285.09:19:07.81#ibcon#about to read 5, iclass 30, count 0 2006.285.09:19:07.81#ibcon#read 5, iclass 30, count 0 2006.285.09:19:07.81#ibcon#about to read 6, iclass 30, count 0 2006.285.09:19:07.81#ibcon#read 6, iclass 30, count 0 2006.285.09:19:07.81#ibcon#end of sib2, iclass 30, count 0 2006.285.09:19:07.81#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:19:07.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:19:07.81#ibcon#[25=USB\r\n] 2006.285.09:19:07.81#ibcon#*before write, iclass 30, count 0 2006.285.09:19:07.81#ibcon#enter sib2, iclass 30, count 0 2006.285.09:19:07.81#ibcon#flushed, iclass 30, count 0 2006.285.09:19:07.81#ibcon#about to write, iclass 30, count 0 2006.285.09:19:07.81#ibcon#wrote, iclass 30, count 0 2006.285.09:19:07.81#ibcon#about to read 3, iclass 30, count 0 2006.285.09:19:07.84#ibcon#read 3, iclass 30, count 0 2006.285.09:19:07.84#ibcon#about to read 4, iclass 30, count 0 2006.285.09:19:07.84#ibcon#read 4, iclass 30, count 0 2006.285.09:19:07.84#ibcon#about to read 5, iclass 30, count 0 2006.285.09:19:07.84#ibcon#read 5, iclass 30, count 0 2006.285.09:19:07.84#ibcon#about to read 6, iclass 30, count 0 2006.285.09:19:07.84#ibcon#read 6, iclass 30, count 0 2006.285.09:19:07.84#ibcon#end of sib2, iclass 30, count 0 2006.285.09:19:07.84#ibcon#*after write, iclass 30, count 0 2006.285.09:19:07.84#ibcon#*before return 0, iclass 30, count 0 2006.285.09:19:07.84#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:19:07.84#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:19:07.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:19:07.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:19:07.84$vck44/valo=4,624.99 2006.285.09:19:07.84#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.09:19:07.84#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.09:19:07.84#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:07.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:19:07.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:19:07.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:19:07.84#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:19:07.84#ibcon#first serial, iclass 32, count 0 2006.285.09:19:07.84#ibcon#enter sib2, iclass 32, count 0 2006.285.09:19:07.84#ibcon#flushed, iclass 32, count 0 2006.285.09:19:07.84#ibcon#about to write, iclass 32, count 0 2006.285.09:19:07.84#ibcon#wrote, iclass 32, count 0 2006.285.09:19:07.84#ibcon#about to read 3, iclass 32, count 0 2006.285.09:19:07.86#ibcon#read 3, iclass 32, count 0 2006.285.09:19:07.86#ibcon#about to read 4, iclass 32, count 0 2006.285.09:19:07.86#ibcon#read 4, iclass 32, count 0 2006.285.09:19:07.86#ibcon#about to read 5, iclass 32, count 0 2006.285.09:19:07.86#ibcon#read 5, iclass 32, count 0 2006.285.09:19:07.86#ibcon#about to read 6, iclass 32, count 0 2006.285.09:19:07.86#ibcon#read 6, iclass 32, count 0 2006.285.09:19:07.86#ibcon#end of sib2, iclass 32, count 0 2006.285.09:19:07.86#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:19:07.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:19:07.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:19:07.86#ibcon#*before write, iclass 32, count 0 2006.285.09:19:07.86#ibcon#enter sib2, iclass 32, count 0 2006.285.09:19:07.86#ibcon#flushed, iclass 32, count 0 2006.285.09:19:07.86#ibcon#about to write, iclass 32, count 0 2006.285.09:19:07.86#ibcon#wrote, iclass 32, count 0 2006.285.09:19:07.86#ibcon#about to read 3, iclass 32, count 0 2006.285.09:19:07.90#ibcon#read 3, iclass 32, count 0 2006.285.09:19:07.90#ibcon#about to read 4, iclass 32, count 0 2006.285.09:19:07.90#ibcon#read 4, iclass 32, count 0 2006.285.09:19:07.90#ibcon#about to read 5, iclass 32, count 0 2006.285.09:19:07.90#ibcon#read 5, iclass 32, count 0 2006.285.09:19:07.90#ibcon#about to read 6, iclass 32, count 0 2006.285.09:19:07.90#ibcon#read 6, iclass 32, count 0 2006.285.09:19:07.90#ibcon#end of sib2, iclass 32, count 0 2006.285.09:19:07.90#ibcon#*after write, iclass 32, count 0 2006.285.09:19:07.90#ibcon#*before return 0, iclass 32, count 0 2006.285.09:19:07.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:19:07.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:19:07.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:19:07.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:19:07.90$vck44/va=4,6 2006.285.09:19:07.90#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.09:19:07.90#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.09:19:07.90#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:07.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:19:07.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:19:07.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:19:07.96#ibcon#enter wrdev, iclass 34, count 2 2006.285.09:19:07.96#ibcon#first serial, iclass 34, count 2 2006.285.09:19:07.96#ibcon#enter sib2, iclass 34, count 2 2006.285.09:19:07.96#ibcon#flushed, iclass 34, count 2 2006.285.09:19:07.96#ibcon#about to write, iclass 34, count 2 2006.285.09:19:07.96#ibcon#wrote, iclass 34, count 2 2006.285.09:19:07.96#ibcon#about to read 3, iclass 34, count 2 2006.285.09:19:07.98#ibcon#read 3, iclass 34, count 2 2006.285.09:19:07.98#ibcon#about to read 4, iclass 34, count 2 2006.285.09:19:07.98#ibcon#read 4, iclass 34, count 2 2006.285.09:19:07.98#ibcon#about to read 5, iclass 34, count 2 2006.285.09:19:07.98#ibcon#read 5, iclass 34, count 2 2006.285.09:19:07.98#ibcon#about to read 6, iclass 34, count 2 2006.285.09:19:07.98#ibcon#read 6, iclass 34, count 2 2006.285.09:19:07.98#ibcon#end of sib2, iclass 34, count 2 2006.285.09:19:07.98#ibcon#*mode == 0, iclass 34, count 2 2006.285.09:19:07.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.09:19:07.98#ibcon#[25=AT04-06\r\n] 2006.285.09:19:07.98#ibcon#*before write, iclass 34, count 2 2006.285.09:19:07.98#ibcon#enter sib2, iclass 34, count 2 2006.285.09:19:07.98#ibcon#flushed, iclass 34, count 2 2006.285.09:19:07.98#ibcon#about to write, iclass 34, count 2 2006.285.09:19:07.98#ibcon#wrote, iclass 34, count 2 2006.285.09:19:07.98#ibcon#about to read 3, iclass 34, count 2 2006.285.09:19:08.01#ibcon#read 3, iclass 34, count 2 2006.285.09:19:08.01#ibcon#about to read 4, iclass 34, count 2 2006.285.09:19:08.01#ibcon#read 4, iclass 34, count 2 2006.285.09:19:08.01#ibcon#about to read 5, iclass 34, count 2 2006.285.09:19:08.01#ibcon#read 5, iclass 34, count 2 2006.285.09:19:08.01#ibcon#about to read 6, iclass 34, count 2 2006.285.09:19:08.01#ibcon#read 6, iclass 34, count 2 2006.285.09:19:08.01#ibcon#end of sib2, iclass 34, count 2 2006.285.09:19:08.01#ibcon#*after write, iclass 34, count 2 2006.285.09:19:08.01#ibcon#*before return 0, iclass 34, count 2 2006.285.09:19:08.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:19:08.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:19:08.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.09:19:08.01#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:08.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:19:08.13#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:19:08.13#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:19:08.13#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:19:08.13#ibcon#first serial, iclass 34, count 0 2006.285.09:19:08.13#ibcon#enter sib2, iclass 34, count 0 2006.285.09:19:08.13#ibcon#flushed, iclass 34, count 0 2006.285.09:19:08.13#ibcon#about to write, iclass 34, count 0 2006.285.09:19:08.13#ibcon#wrote, iclass 34, count 0 2006.285.09:19:08.13#ibcon#about to read 3, iclass 34, count 0 2006.285.09:19:08.15#ibcon#read 3, iclass 34, count 0 2006.285.09:19:08.15#ibcon#about to read 4, iclass 34, count 0 2006.285.09:19:08.15#ibcon#read 4, iclass 34, count 0 2006.285.09:19:08.15#ibcon#about to read 5, iclass 34, count 0 2006.285.09:19:08.15#ibcon#read 5, iclass 34, count 0 2006.285.09:19:08.15#ibcon#about to read 6, iclass 34, count 0 2006.285.09:19:08.15#ibcon#read 6, iclass 34, count 0 2006.285.09:19:08.15#ibcon#end of sib2, iclass 34, count 0 2006.285.09:19:08.15#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:19:08.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:19:08.15#ibcon#[25=USB\r\n] 2006.285.09:19:08.15#ibcon#*before write, iclass 34, count 0 2006.285.09:19:08.15#ibcon#enter sib2, iclass 34, count 0 2006.285.09:19:08.15#ibcon#flushed, iclass 34, count 0 2006.285.09:19:08.15#ibcon#about to write, iclass 34, count 0 2006.285.09:19:08.15#ibcon#wrote, iclass 34, count 0 2006.285.09:19:08.15#ibcon#about to read 3, iclass 34, count 0 2006.285.09:19:08.18#ibcon#read 3, iclass 34, count 0 2006.285.09:19:08.18#ibcon#about to read 4, iclass 34, count 0 2006.285.09:19:08.18#ibcon#read 4, iclass 34, count 0 2006.285.09:19:08.18#ibcon#about to read 5, iclass 34, count 0 2006.285.09:19:08.18#ibcon#read 5, iclass 34, count 0 2006.285.09:19:08.18#ibcon#about to read 6, iclass 34, count 0 2006.285.09:19:08.18#ibcon#read 6, iclass 34, count 0 2006.285.09:19:08.18#ibcon#end of sib2, iclass 34, count 0 2006.285.09:19:08.18#ibcon#*after write, iclass 34, count 0 2006.285.09:19:08.18#ibcon#*before return 0, iclass 34, count 0 2006.285.09:19:08.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:19:08.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:19:08.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:19:08.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:19:08.18$vck44/valo=5,734.99 2006.285.09:19:08.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.09:19:08.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.09:19:08.18#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:08.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:19:08.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:19:08.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:19:08.18#ibcon#enter wrdev, iclass 36, count 0 2006.285.09:19:08.18#ibcon#first serial, iclass 36, count 0 2006.285.09:19:08.18#ibcon#enter sib2, iclass 36, count 0 2006.285.09:19:08.18#ibcon#flushed, iclass 36, count 0 2006.285.09:19:08.18#ibcon#about to write, iclass 36, count 0 2006.285.09:19:08.18#ibcon#wrote, iclass 36, count 0 2006.285.09:19:08.18#ibcon#about to read 3, iclass 36, count 0 2006.285.09:19:08.20#ibcon#read 3, iclass 36, count 0 2006.285.09:19:08.20#ibcon#about to read 4, iclass 36, count 0 2006.285.09:19:08.20#ibcon#read 4, iclass 36, count 0 2006.285.09:19:08.20#ibcon#about to read 5, iclass 36, count 0 2006.285.09:19:08.20#ibcon#read 5, iclass 36, count 0 2006.285.09:19:08.20#ibcon#about to read 6, iclass 36, count 0 2006.285.09:19:08.20#ibcon#read 6, iclass 36, count 0 2006.285.09:19:08.20#ibcon#end of sib2, iclass 36, count 0 2006.285.09:19:08.20#ibcon#*mode == 0, iclass 36, count 0 2006.285.09:19:08.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.09:19:08.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:19:08.20#ibcon#*before write, iclass 36, count 0 2006.285.09:19:08.20#ibcon#enter sib2, iclass 36, count 0 2006.285.09:19:08.20#ibcon#flushed, iclass 36, count 0 2006.285.09:19:08.20#ibcon#about to write, iclass 36, count 0 2006.285.09:19:08.20#ibcon#wrote, iclass 36, count 0 2006.285.09:19:08.20#ibcon#about to read 3, iclass 36, count 0 2006.285.09:19:08.24#ibcon#read 3, iclass 36, count 0 2006.285.09:19:08.24#ibcon#about to read 4, iclass 36, count 0 2006.285.09:19:08.24#ibcon#read 4, iclass 36, count 0 2006.285.09:19:08.24#ibcon#about to read 5, iclass 36, count 0 2006.285.09:19:08.24#ibcon#read 5, iclass 36, count 0 2006.285.09:19:08.24#ibcon#about to read 6, iclass 36, count 0 2006.285.09:19:08.24#ibcon#read 6, iclass 36, count 0 2006.285.09:19:08.24#ibcon#end of sib2, iclass 36, count 0 2006.285.09:19:08.24#ibcon#*after write, iclass 36, count 0 2006.285.09:19:08.24#ibcon#*before return 0, iclass 36, count 0 2006.285.09:19:08.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:19:08.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:19:08.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.09:19:08.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.09:19:08.24$vck44/va=5,3 2006.285.09:19:08.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.09:19:08.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.09:19:08.24#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:08.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:19:08.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:19:08.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:19:08.30#ibcon#enter wrdev, iclass 38, count 2 2006.285.09:19:08.30#ibcon#first serial, iclass 38, count 2 2006.285.09:19:08.30#ibcon#enter sib2, iclass 38, count 2 2006.285.09:19:08.30#ibcon#flushed, iclass 38, count 2 2006.285.09:19:08.30#ibcon#about to write, iclass 38, count 2 2006.285.09:19:08.30#ibcon#wrote, iclass 38, count 2 2006.285.09:19:08.30#ibcon#about to read 3, iclass 38, count 2 2006.285.09:19:08.32#ibcon#read 3, iclass 38, count 2 2006.285.09:19:08.32#ibcon#about to read 4, iclass 38, count 2 2006.285.09:19:08.32#ibcon#read 4, iclass 38, count 2 2006.285.09:19:08.32#ibcon#about to read 5, iclass 38, count 2 2006.285.09:19:08.32#ibcon#read 5, iclass 38, count 2 2006.285.09:19:08.32#ibcon#about to read 6, iclass 38, count 2 2006.285.09:19:08.32#ibcon#read 6, iclass 38, count 2 2006.285.09:19:08.32#ibcon#end of sib2, iclass 38, count 2 2006.285.09:19:08.32#ibcon#*mode == 0, iclass 38, count 2 2006.285.09:19:08.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.09:19:08.32#ibcon#[25=AT05-03\r\n] 2006.285.09:19:08.32#ibcon#*before write, iclass 38, count 2 2006.285.09:19:08.32#ibcon#enter sib2, iclass 38, count 2 2006.285.09:19:08.32#ibcon#flushed, iclass 38, count 2 2006.285.09:19:08.32#ibcon#about to write, iclass 38, count 2 2006.285.09:19:08.32#ibcon#wrote, iclass 38, count 2 2006.285.09:19:08.32#ibcon#about to read 3, iclass 38, count 2 2006.285.09:19:08.35#ibcon#read 3, iclass 38, count 2 2006.285.09:19:08.35#ibcon#about to read 4, iclass 38, count 2 2006.285.09:19:08.35#ibcon#read 4, iclass 38, count 2 2006.285.09:19:08.35#ibcon#about to read 5, iclass 38, count 2 2006.285.09:19:08.35#ibcon#read 5, iclass 38, count 2 2006.285.09:19:08.35#ibcon#about to read 6, iclass 38, count 2 2006.285.09:19:08.35#ibcon#read 6, iclass 38, count 2 2006.285.09:19:08.35#ibcon#end of sib2, iclass 38, count 2 2006.285.09:19:08.35#ibcon#*after write, iclass 38, count 2 2006.285.09:19:08.35#ibcon#*before return 0, iclass 38, count 2 2006.285.09:19:08.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:19:08.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:19:08.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.09:19:08.35#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:08.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:19:08.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:19:08.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:19:08.47#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:19:08.47#ibcon#first serial, iclass 38, count 0 2006.285.09:19:08.47#ibcon#enter sib2, iclass 38, count 0 2006.285.09:19:08.47#ibcon#flushed, iclass 38, count 0 2006.285.09:19:08.47#ibcon#about to write, iclass 38, count 0 2006.285.09:19:08.47#ibcon#wrote, iclass 38, count 0 2006.285.09:19:08.47#ibcon#about to read 3, iclass 38, count 0 2006.285.09:19:08.49#ibcon#read 3, iclass 38, count 0 2006.285.09:19:08.49#ibcon#about to read 4, iclass 38, count 0 2006.285.09:19:08.49#ibcon#read 4, iclass 38, count 0 2006.285.09:19:08.49#ibcon#about to read 5, iclass 38, count 0 2006.285.09:19:08.49#ibcon#read 5, iclass 38, count 0 2006.285.09:19:08.49#ibcon#about to read 6, iclass 38, count 0 2006.285.09:19:08.49#ibcon#read 6, iclass 38, count 0 2006.285.09:19:08.49#ibcon#end of sib2, iclass 38, count 0 2006.285.09:19:08.49#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:19:08.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:19:08.49#ibcon#[25=USB\r\n] 2006.285.09:19:08.49#ibcon#*before write, iclass 38, count 0 2006.285.09:19:08.49#ibcon#enter sib2, iclass 38, count 0 2006.285.09:19:08.49#ibcon#flushed, iclass 38, count 0 2006.285.09:19:08.49#ibcon#about to write, iclass 38, count 0 2006.285.09:19:08.49#ibcon#wrote, iclass 38, count 0 2006.285.09:19:08.49#ibcon#about to read 3, iclass 38, count 0 2006.285.09:19:08.52#ibcon#read 3, iclass 38, count 0 2006.285.09:19:08.52#ibcon#about to read 4, iclass 38, count 0 2006.285.09:19:08.52#ibcon#read 4, iclass 38, count 0 2006.285.09:19:08.52#ibcon#about to read 5, iclass 38, count 0 2006.285.09:19:08.52#ibcon#read 5, iclass 38, count 0 2006.285.09:19:08.52#ibcon#about to read 6, iclass 38, count 0 2006.285.09:19:08.52#ibcon#read 6, iclass 38, count 0 2006.285.09:19:08.52#ibcon#end of sib2, iclass 38, count 0 2006.285.09:19:08.52#ibcon#*after write, iclass 38, count 0 2006.285.09:19:08.52#ibcon#*before return 0, iclass 38, count 0 2006.285.09:19:08.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:19:08.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:19:08.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:19:08.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:19:08.52$vck44/valo=6,814.99 2006.285.09:19:08.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.09:19:08.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.09:19:08.52#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:08.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:19:08.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:19:08.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:19:08.52#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:19:08.52#ibcon#first serial, iclass 40, count 0 2006.285.09:19:08.52#ibcon#enter sib2, iclass 40, count 0 2006.285.09:19:08.52#ibcon#flushed, iclass 40, count 0 2006.285.09:19:08.52#ibcon#about to write, iclass 40, count 0 2006.285.09:19:08.52#ibcon#wrote, iclass 40, count 0 2006.285.09:19:08.52#ibcon#about to read 3, iclass 40, count 0 2006.285.09:19:08.54#ibcon#read 3, iclass 40, count 0 2006.285.09:19:08.54#ibcon#about to read 4, iclass 40, count 0 2006.285.09:19:08.54#ibcon#read 4, iclass 40, count 0 2006.285.09:19:08.54#ibcon#about to read 5, iclass 40, count 0 2006.285.09:19:08.54#ibcon#read 5, iclass 40, count 0 2006.285.09:19:08.54#ibcon#about to read 6, iclass 40, count 0 2006.285.09:19:08.54#ibcon#read 6, iclass 40, count 0 2006.285.09:19:08.54#ibcon#end of sib2, iclass 40, count 0 2006.285.09:19:08.54#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:19:08.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:19:08.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:19:08.54#ibcon#*before write, iclass 40, count 0 2006.285.09:19:08.54#ibcon#enter sib2, iclass 40, count 0 2006.285.09:19:08.54#ibcon#flushed, iclass 40, count 0 2006.285.09:19:08.54#ibcon#about to write, iclass 40, count 0 2006.285.09:19:08.54#ibcon#wrote, iclass 40, count 0 2006.285.09:19:08.54#ibcon#about to read 3, iclass 40, count 0 2006.285.09:19:08.58#ibcon#read 3, iclass 40, count 0 2006.285.09:19:08.58#ibcon#about to read 4, iclass 40, count 0 2006.285.09:19:08.58#ibcon#read 4, iclass 40, count 0 2006.285.09:19:08.58#ibcon#about to read 5, iclass 40, count 0 2006.285.09:19:08.58#ibcon#read 5, iclass 40, count 0 2006.285.09:19:08.58#ibcon#about to read 6, iclass 40, count 0 2006.285.09:19:08.58#ibcon#read 6, iclass 40, count 0 2006.285.09:19:08.58#ibcon#end of sib2, iclass 40, count 0 2006.285.09:19:08.58#ibcon#*after write, iclass 40, count 0 2006.285.09:19:08.58#ibcon#*before return 0, iclass 40, count 0 2006.285.09:19:08.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:19:08.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:19:08.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:19:08.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:19:08.58$vck44/va=6,4 2006.285.09:19:08.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.09:19:08.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.09:19:08.58#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:08.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:19:08.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:19:08.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:19:08.64#ibcon#enter wrdev, iclass 4, count 2 2006.285.09:19:08.64#ibcon#first serial, iclass 4, count 2 2006.285.09:19:08.64#ibcon#enter sib2, iclass 4, count 2 2006.285.09:19:08.64#ibcon#flushed, iclass 4, count 2 2006.285.09:19:08.64#ibcon#about to write, iclass 4, count 2 2006.285.09:19:08.64#ibcon#wrote, iclass 4, count 2 2006.285.09:19:08.64#ibcon#about to read 3, iclass 4, count 2 2006.285.09:19:08.66#ibcon#read 3, iclass 4, count 2 2006.285.09:19:08.66#ibcon#about to read 4, iclass 4, count 2 2006.285.09:19:08.66#ibcon#read 4, iclass 4, count 2 2006.285.09:19:08.66#ibcon#about to read 5, iclass 4, count 2 2006.285.09:19:08.66#ibcon#read 5, iclass 4, count 2 2006.285.09:19:08.66#ibcon#about to read 6, iclass 4, count 2 2006.285.09:19:08.66#ibcon#read 6, iclass 4, count 2 2006.285.09:19:08.66#ibcon#end of sib2, iclass 4, count 2 2006.285.09:19:08.66#ibcon#*mode == 0, iclass 4, count 2 2006.285.09:19:08.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.09:19:08.66#ibcon#[25=AT06-04\r\n] 2006.285.09:19:08.66#ibcon#*before write, iclass 4, count 2 2006.285.09:19:08.66#ibcon#enter sib2, iclass 4, count 2 2006.285.09:19:08.66#ibcon#flushed, iclass 4, count 2 2006.285.09:19:08.66#ibcon#about to write, iclass 4, count 2 2006.285.09:19:08.66#ibcon#wrote, iclass 4, count 2 2006.285.09:19:08.66#ibcon#about to read 3, iclass 4, count 2 2006.285.09:19:08.69#ibcon#read 3, iclass 4, count 2 2006.285.09:19:08.69#ibcon#about to read 4, iclass 4, count 2 2006.285.09:19:08.69#ibcon#read 4, iclass 4, count 2 2006.285.09:19:08.69#ibcon#about to read 5, iclass 4, count 2 2006.285.09:19:08.69#ibcon#read 5, iclass 4, count 2 2006.285.09:19:08.69#ibcon#about to read 6, iclass 4, count 2 2006.285.09:19:08.69#ibcon#read 6, iclass 4, count 2 2006.285.09:19:08.69#ibcon#end of sib2, iclass 4, count 2 2006.285.09:19:08.69#ibcon#*after write, iclass 4, count 2 2006.285.09:19:08.69#ibcon#*before return 0, iclass 4, count 2 2006.285.09:19:08.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:19:08.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:19:08.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.09:19:08.69#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:08.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:19:08.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:19:08.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:19:08.81#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:19:08.81#ibcon#first serial, iclass 4, count 0 2006.285.09:19:08.81#ibcon#enter sib2, iclass 4, count 0 2006.285.09:19:08.81#ibcon#flushed, iclass 4, count 0 2006.285.09:19:08.81#ibcon#about to write, iclass 4, count 0 2006.285.09:19:08.81#ibcon#wrote, iclass 4, count 0 2006.285.09:19:08.81#ibcon#about to read 3, iclass 4, count 0 2006.285.09:19:08.83#ibcon#read 3, iclass 4, count 0 2006.285.09:19:08.83#ibcon#about to read 4, iclass 4, count 0 2006.285.09:19:08.83#ibcon#read 4, iclass 4, count 0 2006.285.09:19:08.83#ibcon#about to read 5, iclass 4, count 0 2006.285.09:19:08.83#ibcon#read 5, iclass 4, count 0 2006.285.09:19:08.83#ibcon#about to read 6, iclass 4, count 0 2006.285.09:19:08.83#ibcon#read 6, iclass 4, count 0 2006.285.09:19:08.83#ibcon#end of sib2, iclass 4, count 0 2006.285.09:19:08.83#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:19:08.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:19:08.83#ibcon#[25=USB\r\n] 2006.285.09:19:08.83#ibcon#*before write, iclass 4, count 0 2006.285.09:19:08.83#ibcon#enter sib2, iclass 4, count 0 2006.285.09:19:08.83#ibcon#flushed, iclass 4, count 0 2006.285.09:19:08.83#ibcon#about to write, iclass 4, count 0 2006.285.09:19:08.83#ibcon#wrote, iclass 4, count 0 2006.285.09:19:08.83#ibcon#about to read 3, iclass 4, count 0 2006.285.09:19:08.86#ibcon#read 3, iclass 4, count 0 2006.285.09:19:08.86#ibcon#about to read 4, iclass 4, count 0 2006.285.09:19:08.86#ibcon#read 4, iclass 4, count 0 2006.285.09:19:08.86#ibcon#about to read 5, iclass 4, count 0 2006.285.09:19:08.86#ibcon#read 5, iclass 4, count 0 2006.285.09:19:08.86#ibcon#about to read 6, iclass 4, count 0 2006.285.09:19:08.86#ibcon#read 6, iclass 4, count 0 2006.285.09:19:08.86#ibcon#end of sib2, iclass 4, count 0 2006.285.09:19:08.86#ibcon#*after write, iclass 4, count 0 2006.285.09:19:08.86#ibcon#*before return 0, iclass 4, count 0 2006.285.09:19:08.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:19:08.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:19:08.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:19:08.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:19:08.86$vck44/valo=7,864.99 2006.285.09:19:08.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.09:19:08.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.09:19:08.86#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:08.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:19:08.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:19:08.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:19:08.86#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:19:08.86#ibcon#first serial, iclass 6, count 0 2006.285.09:19:08.86#ibcon#enter sib2, iclass 6, count 0 2006.285.09:19:08.86#ibcon#flushed, iclass 6, count 0 2006.285.09:19:08.86#ibcon#about to write, iclass 6, count 0 2006.285.09:19:08.86#ibcon#wrote, iclass 6, count 0 2006.285.09:19:08.86#ibcon#about to read 3, iclass 6, count 0 2006.285.09:19:08.88#ibcon#read 3, iclass 6, count 0 2006.285.09:19:08.88#ibcon#about to read 4, iclass 6, count 0 2006.285.09:19:08.88#ibcon#read 4, iclass 6, count 0 2006.285.09:19:08.88#ibcon#about to read 5, iclass 6, count 0 2006.285.09:19:08.88#ibcon#read 5, iclass 6, count 0 2006.285.09:19:08.88#ibcon#about to read 6, iclass 6, count 0 2006.285.09:19:08.88#ibcon#read 6, iclass 6, count 0 2006.285.09:19:08.88#ibcon#end of sib2, iclass 6, count 0 2006.285.09:19:08.88#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:19:08.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:19:08.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:19:08.88#ibcon#*before write, iclass 6, count 0 2006.285.09:19:08.88#ibcon#enter sib2, iclass 6, count 0 2006.285.09:19:08.88#ibcon#flushed, iclass 6, count 0 2006.285.09:19:08.88#ibcon#about to write, iclass 6, count 0 2006.285.09:19:08.88#ibcon#wrote, iclass 6, count 0 2006.285.09:19:08.88#ibcon#about to read 3, iclass 6, count 0 2006.285.09:19:08.92#ibcon#read 3, iclass 6, count 0 2006.285.09:19:08.92#ibcon#about to read 4, iclass 6, count 0 2006.285.09:19:08.92#ibcon#read 4, iclass 6, count 0 2006.285.09:19:08.92#ibcon#about to read 5, iclass 6, count 0 2006.285.09:19:08.92#ibcon#read 5, iclass 6, count 0 2006.285.09:19:08.92#ibcon#about to read 6, iclass 6, count 0 2006.285.09:19:08.92#ibcon#read 6, iclass 6, count 0 2006.285.09:19:08.92#ibcon#end of sib2, iclass 6, count 0 2006.285.09:19:08.92#ibcon#*after write, iclass 6, count 0 2006.285.09:19:08.92#ibcon#*before return 0, iclass 6, count 0 2006.285.09:19:08.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:19:08.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:19:08.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:19:08.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:19:08.92$vck44/va=7,4 2006.285.09:19:08.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.09:19:08.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.09:19:08.92#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:08.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:19:08.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:19:08.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:19:08.98#ibcon#enter wrdev, iclass 10, count 2 2006.285.09:19:08.98#ibcon#first serial, iclass 10, count 2 2006.285.09:19:08.98#ibcon#enter sib2, iclass 10, count 2 2006.285.09:19:08.98#ibcon#flushed, iclass 10, count 2 2006.285.09:19:08.98#ibcon#about to write, iclass 10, count 2 2006.285.09:19:08.98#ibcon#wrote, iclass 10, count 2 2006.285.09:19:08.98#ibcon#about to read 3, iclass 10, count 2 2006.285.09:19:09.00#ibcon#read 3, iclass 10, count 2 2006.285.09:19:09.00#ibcon#about to read 4, iclass 10, count 2 2006.285.09:19:09.00#ibcon#read 4, iclass 10, count 2 2006.285.09:19:09.00#ibcon#about to read 5, iclass 10, count 2 2006.285.09:19:09.00#ibcon#read 5, iclass 10, count 2 2006.285.09:19:09.00#ibcon#about to read 6, iclass 10, count 2 2006.285.09:19:09.00#ibcon#read 6, iclass 10, count 2 2006.285.09:19:09.00#ibcon#end of sib2, iclass 10, count 2 2006.285.09:19:09.00#ibcon#*mode == 0, iclass 10, count 2 2006.285.09:19:09.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.09:19:09.00#ibcon#[25=AT07-04\r\n] 2006.285.09:19:09.00#ibcon#*before write, iclass 10, count 2 2006.285.09:19:09.00#ibcon#enter sib2, iclass 10, count 2 2006.285.09:19:09.00#ibcon#flushed, iclass 10, count 2 2006.285.09:19:09.00#ibcon#about to write, iclass 10, count 2 2006.285.09:19:09.00#ibcon#wrote, iclass 10, count 2 2006.285.09:19:09.00#ibcon#about to read 3, iclass 10, count 2 2006.285.09:19:09.03#ibcon#read 3, iclass 10, count 2 2006.285.09:19:09.03#ibcon#about to read 4, iclass 10, count 2 2006.285.09:19:09.03#ibcon#read 4, iclass 10, count 2 2006.285.09:19:09.03#ibcon#about to read 5, iclass 10, count 2 2006.285.09:19:09.03#ibcon#read 5, iclass 10, count 2 2006.285.09:19:09.03#ibcon#about to read 6, iclass 10, count 2 2006.285.09:19:09.03#ibcon#read 6, iclass 10, count 2 2006.285.09:19:09.03#ibcon#end of sib2, iclass 10, count 2 2006.285.09:19:09.03#ibcon#*after write, iclass 10, count 2 2006.285.09:19:09.03#ibcon#*before return 0, iclass 10, count 2 2006.285.09:19:09.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:19:09.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:19:09.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.09:19:09.03#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:09.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:19:09.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:19:09.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:19:09.15#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:19:09.15#ibcon#first serial, iclass 10, count 0 2006.285.09:19:09.15#ibcon#enter sib2, iclass 10, count 0 2006.285.09:19:09.15#ibcon#flushed, iclass 10, count 0 2006.285.09:19:09.15#ibcon#about to write, iclass 10, count 0 2006.285.09:19:09.15#ibcon#wrote, iclass 10, count 0 2006.285.09:19:09.15#ibcon#about to read 3, iclass 10, count 0 2006.285.09:19:09.17#ibcon#read 3, iclass 10, count 0 2006.285.09:19:09.17#ibcon#about to read 4, iclass 10, count 0 2006.285.09:19:09.17#ibcon#read 4, iclass 10, count 0 2006.285.09:19:09.17#ibcon#about to read 5, iclass 10, count 0 2006.285.09:19:09.17#ibcon#read 5, iclass 10, count 0 2006.285.09:19:09.17#ibcon#about to read 6, iclass 10, count 0 2006.285.09:19:09.17#ibcon#read 6, iclass 10, count 0 2006.285.09:19:09.17#ibcon#end of sib2, iclass 10, count 0 2006.285.09:19:09.17#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:19:09.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:19:09.17#ibcon#[25=USB\r\n] 2006.285.09:19:09.17#ibcon#*before write, iclass 10, count 0 2006.285.09:19:09.17#ibcon#enter sib2, iclass 10, count 0 2006.285.09:19:09.17#ibcon#flushed, iclass 10, count 0 2006.285.09:19:09.17#ibcon#about to write, iclass 10, count 0 2006.285.09:19:09.17#ibcon#wrote, iclass 10, count 0 2006.285.09:19:09.17#ibcon#about to read 3, iclass 10, count 0 2006.285.09:19:09.20#ibcon#read 3, iclass 10, count 0 2006.285.09:19:09.20#ibcon#about to read 4, iclass 10, count 0 2006.285.09:19:09.20#ibcon#read 4, iclass 10, count 0 2006.285.09:19:09.20#ibcon#about to read 5, iclass 10, count 0 2006.285.09:19:09.20#ibcon#read 5, iclass 10, count 0 2006.285.09:19:09.20#ibcon#about to read 6, iclass 10, count 0 2006.285.09:19:09.20#ibcon#read 6, iclass 10, count 0 2006.285.09:19:09.20#ibcon#end of sib2, iclass 10, count 0 2006.285.09:19:09.20#ibcon#*after write, iclass 10, count 0 2006.285.09:19:09.20#ibcon#*before return 0, iclass 10, count 0 2006.285.09:19:09.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:19:09.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:19:09.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:19:09.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:19:09.20$vck44/valo=8,884.99 2006.285.09:19:09.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.09:19:09.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.09:19:09.20#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:09.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:19:09.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:19:09.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:19:09.20#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:19:09.20#ibcon#first serial, iclass 12, count 0 2006.285.09:19:09.20#ibcon#enter sib2, iclass 12, count 0 2006.285.09:19:09.20#ibcon#flushed, iclass 12, count 0 2006.285.09:19:09.20#ibcon#about to write, iclass 12, count 0 2006.285.09:19:09.20#ibcon#wrote, iclass 12, count 0 2006.285.09:19:09.20#ibcon#about to read 3, iclass 12, count 0 2006.285.09:19:09.22#ibcon#read 3, iclass 12, count 0 2006.285.09:19:09.22#ibcon#about to read 4, iclass 12, count 0 2006.285.09:19:09.22#ibcon#read 4, iclass 12, count 0 2006.285.09:19:09.22#ibcon#about to read 5, iclass 12, count 0 2006.285.09:19:09.22#ibcon#read 5, iclass 12, count 0 2006.285.09:19:09.22#ibcon#about to read 6, iclass 12, count 0 2006.285.09:19:09.22#ibcon#read 6, iclass 12, count 0 2006.285.09:19:09.22#ibcon#end of sib2, iclass 12, count 0 2006.285.09:19:09.22#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:19:09.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:19:09.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:19:09.22#ibcon#*before write, iclass 12, count 0 2006.285.09:19:09.22#ibcon#enter sib2, iclass 12, count 0 2006.285.09:19:09.22#ibcon#flushed, iclass 12, count 0 2006.285.09:19:09.22#ibcon#about to write, iclass 12, count 0 2006.285.09:19:09.22#ibcon#wrote, iclass 12, count 0 2006.285.09:19:09.22#ibcon#about to read 3, iclass 12, count 0 2006.285.09:19:09.26#ibcon#read 3, iclass 12, count 0 2006.285.09:19:09.26#ibcon#about to read 4, iclass 12, count 0 2006.285.09:19:09.26#ibcon#read 4, iclass 12, count 0 2006.285.09:19:09.26#ibcon#about to read 5, iclass 12, count 0 2006.285.09:19:09.26#ibcon#read 5, iclass 12, count 0 2006.285.09:19:09.26#ibcon#about to read 6, iclass 12, count 0 2006.285.09:19:09.26#ibcon#read 6, iclass 12, count 0 2006.285.09:19:09.26#ibcon#end of sib2, iclass 12, count 0 2006.285.09:19:09.26#ibcon#*after write, iclass 12, count 0 2006.285.09:19:09.26#ibcon#*before return 0, iclass 12, count 0 2006.285.09:19:09.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:19:09.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:19:09.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:19:09.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:19:09.26$vck44/va=8,3 2006.285.09:19:09.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.09:19:09.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.09:19:09.26#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:09.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:19:09.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:19:09.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:19:09.32#ibcon#enter wrdev, iclass 14, count 2 2006.285.09:19:09.32#ibcon#first serial, iclass 14, count 2 2006.285.09:19:09.32#ibcon#enter sib2, iclass 14, count 2 2006.285.09:19:09.32#ibcon#flushed, iclass 14, count 2 2006.285.09:19:09.32#ibcon#about to write, iclass 14, count 2 2006.285.09:19:09.32#ibcon#wrote, iclass 14, count 2 2006.285.09:19:09.32#ibcon#about to read 3, iclass 14, count 2 2006.285.09:19:09.34#ibcon#read 3, iclass 14, count 2 2006.285.09:19:09.34#ibcon#about to read 4, iclass 14, count 2 2006.285.09:19:09.34#ibcon#read 4, iclass 14, count 2 2006.285.09:19:09.34#ibcon#about to read 5, iclass 14, count 2 2006.285.09:19:09.34#ibcon#read 5, iclass 14, count 2 2006.285.09:19:09.34#ibcon#about to read 6, iclass 14, count 2 2006.285.09:19:09.34#ibcon#read 6, iclass 14, count 2 2006.285.09:19:09.34#ibcon#end of sib2, iclass 14, count 2 2006.285.09:19:09.34#ibcon#*mode == 0, iclass 14, count 2 2006.285.09:19:09.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.09:19:09.34#ibcon#[25=AT08-03\r\n] 2006.285.09:19:09.34#ibcon#*before write, iclass 14, count 2 2006.285.09:19:09.34#ibcon#enter sib2, iclass 14, count 2 2006.285.09:19:09.34#ibcon#flushed, iclass 14, count 2 2006.285.09:19:09.34#ibcon#about to write, iclass 14, count 2 2006.285.09:19:09.34#ibcon#wrote, iclass 14, count 2 2006.285.09:19:09.34#ibcon#about to read 3, iclass 14, count 2 2006.285.09:19:09.37#ibcon#read 3, iclass 14, count 2 2006.285.09:19:09.37#ibcon#about to read 4, iclass 14, count 2 2006.285.09:19:09.37#ibcon#read 4, iclass 14, count 2 2006.285.09:19:09.37#ibcon#about to read 5, iclass 14, count 2 2006.285.09:19:09.37#ibcon#read 5, iclass 14, count 2 2006.285.09:19:09.37#ibcon#about to read 6, iclass 14, count 2 2006.285.09:19:09.37#ibcon#read 6, iclass 14, count 2 2006.285.09:19:09.37#ibcon#end of sib2, iclass 14, count 2 2006.285.09:19:09.37#ibcon#*after write, iclass 14, count 2 2006.285.09:19:09.37#ibcon#*before return 0, iclass 14, count 2 2006.285.09:19:09.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:19:09.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:19:09.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.09:19:09.37#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:09.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:19:09.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:19:09.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:19:09.49#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:19:09.49#ibcon#first serial, iclass 14, count 0 2006.285.09:19:09.49#ibcon#enter sib2, iclass 14, count 0 2006.285.09:19:09.49#ibcon#flushed, iclass 14, count 0 2006.285.09:19:09.49#ibcon#about to write, iclass 14, count 0 2006.285.09:19:09.49#ibcon#wrote, iclass 14, count 0 2006.285.09:19:09.49#ibcon#about to read 3, iclass 14, count 0 2006.285.09:19:09.51#ibcon#read 3, iclass 14, count 0 2006.285.09:19:09.51#ibcon#about to read 4, iclass 14, count 0 2006.285.09:19:09.51#ibcon#read 4, iclass 14, count 0 2006.285.09:19:09.51#ibcon#about to read 5, iclass 14, count 0 2006.285.09:19:09.51#ibcon#read 5, iclass 14, count 0 2006.285.09:19:09.51#ibcon#about to read 6, iclass 14, count 0 2006.285.09:19:09.51#ibcon#read 6, iclass 14, count 0 2006.285.09:19:09.51#ibcon#end of sib2, iclass 14, count 0 2006.285.09:19:09.51#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:19:09.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:19:09.51#ibcon#[25=USB\r\n] 2006.285.09:19:09.51#ibcon#*before write, iclass 14, count 0 2006.285.09:19:09.51#ibcon#enter sib2, iclass 14, count 0 2006.285.09:19:09.51#ibcon#flushed, iclass 14, count 0 2006.285.09:19:09.51#ibcon#about to write, iclass 14, count 0 2006.285.09:19:09.51#ibcon#wrote, iclass 14, count 0 2006.285.09:19:09.51#ibcon#about to read 3, iclass 14, count 0 2006.285.09:19:09.54#ibcon#read 3, iclass 14, count 0 2006.285.09:19:09.54#ibcon#about to read 4, iclass 14, count 0 2006.285.09:19:09.54#ibcon#read 4, iclass 14, count 0 2006.285.09:19:09.54#ibcon#about to read 5, iclass 14, count 0 2006.285.09:19:09.54#ibcon#read 5, iclass 14, count 0 2006.285.09:19:09.54#ibcon#about to read 6, iclass 14, count 0 2006.285.09:19:09.54#ibcon#read 6, iclass 14, count 0 2006.285.09:19:09.54#ibcon#end of sib2, iclass 14, count 0 2006.285.09:19:09.54#ibcon#*after write, iclass 14, count 0 2006.285.09:19:09.54#ibcon#*before return 0, iclass 14, count 0 2006.285.09:19:09.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:19:09.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:19:09.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:19:09.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:19:09.54$vck44/vblo=1,629.99 2006.285.09:19:09.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.09:19:09.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.09:19:09.54#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:09.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:19:09.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:19:09.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:19:09.54#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:19:09.54#ibcon#first serial, iclass 16, count 0 2006.285.09:19:09.54#ibcon#enter sib2, iclass 16, count 0 2006.285.09:19:09.54#ibcon#flushed, iclass 16, count 0 2006.285.09:19:09.54#ibcon#about to write, iclass 16, count 0 2006.285.09:19:09.54#ibcon#wrote, iclass 16, count 0 2006.285.09:19:09.54#ibcon#about to read 3, iclass 16, count 0 2006.285.09:19:09.56#ibcon#read 3, iclass 16, count 0 2006.285.09:19:09.56#ibcon#about to read 4, iclass 16, count 0 2006.285.09:19:09.56#ibcon#read 4, iclass 16, count 0 2006.285.09:19:09.56#ibcon#about to read 5, iclass 16, count 0 2006.285.09:19:09.56#ibcon#read 5, iclass 16, count 0 2006.285.09:19:09.56#ibcon#about to read 6, iclass 16, count 0 2006.285.09:19:09.56#ibcon#read 6, iclass 16, count 0 2006.285.09:19:09.56#ibcon#end of sib2, iclass 16, count 0 2006.285.09:19:09.56#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:19:09.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:19:09.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:19:09.56#ibcon#*before write, iclass 16, count 0 2006.285.09:19:09.56#ibcon#enter sib2, iclass 16, count 0 2006.285.09:19:09.56#ibcon#flushed, iclass 16, count 0 2006.285.09:19:09.56#ibcon#about to write, iclass 16, count 0 2006.285.09:19:09.56#ibcon#wrote, iclass 16, count 0 2006.285.09:19:09.56#ibcon#about to read 3, iclass 16, count 0 2006.285.09:19:09.60#ibcon#read 3, iclass 16, count 0 2006.285.09:19:09.60#ibcon#about to read 4, iclass 16, count 0 2006.285.09:19:09.60#ibcon#read 4, iclass 16, count 0 2006.285.09:19:09.60#ibcon#about to read 5, iclass 16, count 0 2006.285.09:19:09.60#ibcon#read 5, iclass 16, count 0 2006.285.09:19:09.60#ibcon#about to read 6, iclass 16, count 0 2006.285.09:19:09.60#ibcon#read 6, iclass 16, count 0 2006.285.09:19:09.60#ibcon#end of sib2, iclass 16, count 0 2006.285.09:19:09.60#ibcon#*after write, iclass 16, count 0 2006.285.09:19:09.60#ibcon#*before return 0, iclass 16, count 0 2006.285.09:19:09.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:19:09.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:19:09.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:19:09.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:19:09.60$vck44/vb=1,4 2006.285.09:19:09.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.09:19:09.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.09:19:09.60#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:09.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:19:09.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:19:09.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:19:09.60#ibcon#enter wrdev, iclass 18, count 2 2006.285.09:19:09.60#ibcon#first serial, iclass 18, count 2 2006.285.09:19:09.60#ibcon#enter sib2, iclass 18, count 2 2006.285.09:19:09.60#ibcon#flushed, iclass 18, count 2 2006.285.09:19:09.60#ibcon#about to write, iclass 18, count 2 2006.285.09:19:09.60#ibcon#wrote, iclass 18, count 2 2006.285.09:19:09.60#ibcon#about to read 3, iclass 18, count 2 2006.285.09:19:09.62#ibcon#read 3, iclass 18, count 2 2006.285.09:19:09.62#ibcon#about to read 4, iclass 18, count 2 2006.285.09:19:09.62#ibcon#read 4, iclass 18, count 2 2006.285.09:19:09.62#ibcon#about to read 5, iclass 18, count 2 2006.285.09:19:09.62#ibcon#read 5, iclass 18, count 2 2006.285.09:19:09.62#ibcon#about to read 6, iclass 18, count 2 2006.285.09:19:09.62#ibcon#read 6, iclass 18, count 2 2006.285.09:19:09.62#ibcon#end of sib2, iclass 18, count 2 2006.285.09:19:09.62#ibcon#*mode == 0, iclass 18, count 2 2006.285.09:19:09.62#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.09:19:09.62#ibcon#[27=AT01-04\r\n] 2006.285.09:19:09.62#ibcon#*before write, iclass 18, count 2 2006.285.09:19:09.62#ibcon#enter sib2, iclass 18, count 2 2006.285.09:19:09.62#ibcon#flushed, iclass 18, count 2 2006.285.09:19:09.62#ibcon#about to write, iclass 18, count 2 2006.285.09:19:09.62#ibcon#wrote, iclass 18, count 2 2006.285.09:19:09.62#ibcon#about to read 3, iclass 18, count 2 2006.285.09:19:09.65#ibcon#read 3, iclass 18, count 2 2006.285.09:19:09.65#ibcon#about to read 4, iclass 18, count 2 2006.285.09:19:09.65#ibcon#read 4, iclass 18, count 2 2006.285.09:19:09.65#ibcon#about to read 5, iclass 18, count 2 2006.285.09:19:09.65#ibcon#read 5, iclass 18, count 2 2006.285.09:19:09.65#ibcon#about to read 6, iclass 18, count 2 2006.285.09:19:09.65#ibcon#read 6, iclass 18, count 2 2006.285.09:19:09.65#ibcon#end of sib2, iclass 18, count 2 2006.285.09:19:09.65#ibcon#*after write, iclass 18, count 2 2006.285.09:19:09.65#ibcon#*before return 0, iclass 18, count 2 2006.285.09:19:09.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:19:09.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:19:09.65#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.09:19:09.65#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:09.65#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:19:09.77#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:19:09.77#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:19:09.77#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:19:09.77#ibcon#first serial, iclass 18, count 0 2006.285.09:19:09.77#ibcon#enter sib2, iclass 18, count 0 2006.285.09:19:09.77#ibcon#flushed, iclass 18, count 0 2006.285.09:19:09.77#ibcon#about to write, iclass 18, count 0 2006.285.09:19:09.77#ibcon#wrote, iclass 18, count 0 2006.285.09:19:09.77#ibcon#about to read 3, iclass 18, count 0 2006.285.09:19:09.79#ibcon#read 3, iclass 18, count 0 2006.285.09:19:09.79#ibcon#about to read 4, iclass 18, count 0 2006.285.09:19:09.79#ibcon#read 4, iclass 18, count 0 2006.285.09:19:09.79#ibcon#about to read 5, iclass 18, count 0 2006.285.09:19:09.79#ibcon#read 5, iclass 18, count 0 2006.285.09:19:09.79#ibcon#about to read 6, iclass 18, count 0 2006.285.09:19:09.79#ibcon#read 6, iclass 18, count 0 2006.285.09:19:09.79#ibcon#end of sib2, iclass 18, count 0 2006.285.09:19:09.79#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:19:09.79#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:19:09.79#ibcon#[27=USB\r\n] 2006.285.09:19:09.79#ibcon#*before write, iclass 18, count 0 2006.285.09:19:09.79#ibcon#enter sib2, iclass 18, count 0 2006.285.09:19:09.79#ibcon#flushed, iclass 18, count 0 2006.285.09:19:09.79#ibcon#about to write, iclass 18, count 0 2006.285.09:19:09.79#ibcon#wrote, iclass 18, count 0 2006.285.09:19:09.79#ibcon#about to read 3, iclass 18, count 0 2006.285.09:19:09.82#ibcon#read 3, iclass 18, count 0 2006.285.09:19:09.82#ibcon#about to read 4, iclass 18, count 0 2006.285.09:19:09.82#ibcon#read 4, iclass 18, count 0 2006.285.09:19:09.82#ibcon#about to read 5, iclass 18, count 0 2006.285.09:19:09.82#ibcon#read 5, iclass 18, count 0 2006.285.09:19:09.82#ibcon#about to read 6, iclass 18, count 0 2006.285.09:19:09.82#ibcon#read 6, iclass 18, count 0 2006.285.09:19:09.82#ibcon#end of sib2, iclass 18, count 0 2006.285.09:19:09.82#ibcon#*after write, iclass 18, count 0 2006.285.09:19:09.82#ibcon#*before return 0, iclass 18, count 0 2006.285.09:19:09.82#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:19:09.82#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:19:09.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:19:09.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:19:09.82$vck44/vblo=2,634.99 2006.285.09:19:09.82#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.09:19:09.82#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.09:19:09.82#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:09.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:19:09.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:19:09.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:19:09.82#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:19:09.82#ibcon#first serial, iclass 20, count 0 2006.285.09:19:09.82#ibcon#enter sib2, iclass 20, count 0 2006.285.09:19:09.82#ibcon#flushed, iclass 20, count 0 2006.285.09:19:09.82#ibcon#about to write, iclass 20, count 0 2006.285.09:19:09.82#ibcon#wrote, iclass 20, count 0 2006.285.09:19:09.82#ibcon#about to read 3, iclass 20, count 0 2006.285.09:19:09.84#ibcon#read 3, iclass 20, count 0 2006.285.09:19:09.84#ibcon#about to read 4, iclass 20, count 0 2006.285.09:19:09.84#ibcon#read 4, iclass 20, count 0 2006.285.09:19:09.84#ibcon#about to read 5, iclass 20, count 0 2006.285.09:19:09.84#ibcon#read 5, iclass 20, count 0 2006.285.09:19:09.84#ibcon#about to read 6, iclass 20, count 0 2006.285.09:19:09.84#ibcon#read 6, iclass 20, count 0 2006.285.09:19:09.84#ibcon#end of sib2, iclass 20, count 0 2006.285.09:19:09.84#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:19:09.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:19:09.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:19:09.84#ibcon#*before write, iclass 20, count 0 2006.285.09:19:09.84#ibcon#enter sib2, iclass 20, count 0 2006.285.09:19:09.84#ibcon#flushed, iclass 20, count 0 2006.285.09:19:09.84#ibcon#about to write, iclass 20, count 0 2006.285.09:19:09.84#ibcon#wrote, iclass 20, count 0 2006.285.09:19:09.84#ibcon#about to read 3, iclass 20, count 0 2006.285.09:19:09.88#ibcon#read 3, iclass 20, count 0 2006.285.09:19:09.88#ibcon#about to read 4, iclass 20, count 0 2006.285.09:19:09.88#ibcon#read 4, iclass 20, count 0 2006.285.09:19:09.88#ibcon#about to read 5, iclass 20, count 0 2006.285.09:19:09.88#ibcon#read 5, iclass 20, count 0 2006.285.09:19:09.88#ibcon#about to read 6, iclass 20, count 0 2006.285.09:19:09.88#ibcon#read 6, iclass 20, count 0 2006.285.09:19:09.88#ibcon#end of sib2, iclass 20, count 0 2006.285.09:19:09.88#ibcon#*after write, iclass 20, count 0 2006.285.09:19:09.88#ibcon#*before return 0, iclass 20, count 0 2006.285.09:19:09.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:19:09.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:19:09.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:19:09.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:19:09.88$vck44/vb=2,5 2006.285.09:19:09.88#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.09:19:09.88#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.09:19:09.88#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:09.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:19:09.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:19:09.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:19:09.94#ibcon#enter wrdev, iclass 22, count 2 2006.285.09:19:09.94#ibcon#first serial, iclass 22, count 2 2006.285.09:19:09.94#ibcon#enter sib2, iclass 22, count 2 2006.285.09:19:09.94#ibcon#flushed, iclass 22, count 2 2006.285.09:19:09.94#ibcon#about to write, iclass 22, count 2 2006.285.09:19:09.94#ibcon#wrote, iclass 22, count 2 2006.285.09:19:09.94#ibcon#about to read 3, iclass 22, count 2 2006.285.09:19:09.96#ibcon#read 3, iclass 22, count 2 2006.285.09:19:09.96#ibcon#about to read 4, iclass 22, count 2 2006.285.09:19:09.96#ibcon#read 4, iclass 22, count 2 2006.285.09:19:09.96#ibcon#about to read 5, iclass 22, count 2 2006.285.09:19:09.96#ibcon#read 5, iclass 22, count 2 2006.285.09:19:09.96#ibcon#about to read 6, iclass 22, count 2 2006.285.09:19:09.96#ibcon#read 6, iclass 22, count 2 2006.285.09:19:09.96#ibcon#end of sib2, iclass 22, count 2 2006.285.09:19:09.96#ibcon#*mode == 0, iclass 22, count 2 2006.285.09:19:09.96#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.09:19:09.96#ibcon#[27=AT02-05\r\n] 2006.285.09:19:09.96#ibcon#*before write, iclass 22, count 2 2006.285.09:19:09.96#ibcon#enter sib2, iclass 22, count 2 2006.285.09:19:09.96#ibcon#flushed, iclass 22, count 2 2006.285.09:19:09.96#ibcon#about to write, iclass 22, count 2 2006.285.09:19:09.96#ibcon#wrote, iclass 22, count 2 2006.285.09:19:09.96#ibcon#about to read 3, iclass 22, count 2 2006.285.09:19:09.99#ibcon#read 3, iclass 22, count 2 2006.285.09:19:09.99#ibcon#about to read 4, iclass 22, count 2 2006.285.09:19:09.99#ibcon#read 4, iclass 22, count 2 2006.285.09:19:09.99#ibcon#about to read 5, iclass 22, count 2 2006.285.09:19:09.99#ibcon#read 5, iclass 22, count 2 2006.285.09:19:09.99#ibcon#about to read 6, iclass 22, count 2 2006.285.09:19:09.99#ibcon#read 6, iclass 22, count 2 2006.285.09:19:09.99#ibcon#end of sib2, iclass 22, count 2 2006.285.09:19:09.99#ibcon#*after write, iclass 22, count 2 2006.285.09:19:09.99#ibcon#*before return 0, iclass 22, count 2 2006.285.09:19:09.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:19:09.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:19:09.99#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.09:19:09.99#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:09.99#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:19:10.11#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:19:10.11#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:19:10.11#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:19:10.11#ibcon#first serial, iclass 22, count 0 2006.285.09:19:10.11#ibcon#enter sib2, iclass 22, count 0 2006.285.09:19:10.11#ibcon#flushed, iclass 22, count 0 2006.285.09:19:10.11#ibcon#about to write, iclass 22, count 0 2006.285.09:19:10.11#ibcon#wrote, iclass 22, count 0 2006.285.09:19:10.11#ibcon#about to read 3, iclass 22, count 0 2006.285.09:19:10.13#ibcon#read 3, iclass 22, count 0 2006.285.09:19:10.13#ibcon#about to read 4, iclass 22, count 0 2006.285.09:19:10.13#ibcon#read 4, iclass 22, count 0 2006.285.09:19:10.13#ibcon#about to read 5, iclass 22, count 0 2006.285.09:19:10.13#ibcon#read 5, iclass 22, count 0 2006.285.09:19:10.13#ibcon#about to read 6, iclass 22, count 0 2006.285.09:19:10.13#ibcon#read 6, iclass 22, count 0 2006.285.09:19:10.13#ibcon#end of sib2, iclass 22, count 0 2006.285.09:19:10.13#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:19:10.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:19:10.13#ibcon#[27=USB\r\n] 2006.285.09:19:10.13#ibcon#*before write, iclass 22, count 0 2006.285.09:19:10.13#ibcon#enter sib2, iclass 22, count 0 2006.285.09:19:10.13#ibcon#flushed, iclass 22, count 0 2006.285.09:19:10.13#ibcon#about to write, iclass 22, count 0 2006.285.09:19:10.13#ibcon#wrote, iclass 22, count 0 2006.285.09:19:10.13#ibcon#about to read 3, iclass 22, count 0 2006.285.09:19:10.16#ibcon#read 3, iclass 22, count 0 2006.285.09:19:10.16#ibcon#about to read 4, iclass 22, count 0 2006.285.09:19:10.16#ibcon#read 4, iclass 22, count 0 2006.285.09:19:10.16#ibcon#about to read 5, iclass 22, count 0 2006.285.09:19:10.16#ibcon#read 5, iclass 22, count 0 2006.285.09:19:10.16#ibcon#about to read 6, iclass 22, count 0 2006.285.09:19:10.16#ibcon#read 6, iclass 22, count 0 2006.285.09:19:10.16#ibcon#end of sib2, iclass 22, count 0 2006.285.09:19:10.16#ibcon#*after write, iclass 22, count 0 2006.285.09:19:10.16#ibcon#*before return 0, iclass 22, count 0 2006.285.09:19:10.16#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:19:10.16#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:19:10.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:19:10.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:19:10.16$vck44/vblo=3,649.99 2006.285.09:19:10.16#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.09:19:10.16#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.09:19:10.16#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:10.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:19:10.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:19:10.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:19:10.16#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:19:10.16#ibcon#first serial, iclass 24, count 0 2006.285.09:19:10.16#ibcon#enter sib2, iclass 24, count 0 2006.285.09:19:10.16#ibcon#flushed, iclass 24, count 0 2006.285.09:19:10.16#ibcon#about to write, iclass 24, count 0 2006.285.09:19:10.16#ibcon#wrote, iclass 24, count 0 2006.285.09:19:10.16#ibcon#about to read 3, iclass 24, count 0 2006.285.09:19:10.18#ibcon#read 3, iclass 24, count 0 2006.285.09:19:10.18#ibcon#about to read 4, iclass 24, count 0 2006.285.09:19:10.18#ibcon#read 4, iclass 24, count 0 2006.285.09:19:10.18#ibcon#about to read 5, iclass 24, count 0 2006.285.09:19:10.18#ibcon#read 5, iclass 24, count 0 2006.285.09:19:10.18#ibcon#about to read 6, iclass 24, count 0 2006.285.09:19:10.18#ibcon#read 6, iclass 24, count 0 2006.285.09:19:10.18#ibcon#end of sib2, iclass 24, count 0 2006.285.09:19:10.18#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:19:10.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:19:10.18#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:19:10.18#ibcon#*before write, iclass 24, count 0 2006.285.09:19:10.18#ibcon#enter sib2, iclass 24, count 0 2006.285.09:19:10.18#ibcon#flushed, iclass 24, count 0 2006.285.09:19:10.18#ibcon#about to write, iclass 24, count 0 2006.285.09:19:10.18#ibcon#wrote, iclass 24, count 0 2006.285.09:19:10.18#ibcon#about to read 3, iclass 24, count 0 2006.285.09:19:10.22#ibcon#read 3, iclass 24, count 0 2006.285.09:19:10.22#ibcon#about to read 4, iclass 24, count 0 2006.285.09:19:10.22#ibcon#read 4, iclass 24, count 0 2006.285.09:19:10.22#ibcon#about to read 5, iclass 24, count 0 2006.285.09:19:10.22#ibcon#read 5, iclass 24, count 0 2006.285.09:19:10.22#ibcon#about to read 6, iclass 24, count 0 2006.285.09:19:10.22#ibcon#read 6, iclass 24, count 0 2006.285.09:19:10.22#ibcon#end of sib2, iclass 24, count 0 2006.285.09:19:10.22#ibcon#*after write, iclass 24, count 0 2006.285.09:19:10.22#ibcon#*before return 0, iclass 24, count 0 2006.285.09:19:10.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:19:10.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:19:10.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:19:10.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:19:10.22$vck44/vb=3,4 2006.285.09:19:10.22#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.09:19:10.22#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.09:19:10.22#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:10.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:19:10.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:19:10.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:19:10.28#ibcon#enter wrdev, iclass 26, count 2 2006.285.09:19:10.28#ibcon#first serial, iclass 26, count 2 2006.285.09:19:10.28#ibcon#enter sib2, iclass 26, count 2 2006.285.09:19:10.28#ibcon#flushed, iclass 26, count 2 2006.285.09:19:10.28#ibcon#about to write, iclass 26, count 2 2006.285.09:19:10.28#ibcon#wrote, iclass 26, count 2 2006.285.09:19:10.28#ibcon#about to read 3, iclass 26, count 2 2006.285.09:19:10.30#ibcon#read 3, iclass 26, count 2 2006.285.09:19:10.30#ibcon#about to read 4, iclass 26, count 2 2006.285.09:19:10.30#ibcon#read 4, iclass 26, count 2 2006.285.09:19:10.30#ibcon#about to read 5, iclass 26, count 2 2006.285.09:19:10.30#ibcon#read 5, iclass 26, count 2 2006.285.09:19:10.30#ibcon#about to read 6, iclass 26, count 2 2006.285.09:19:10.30#ibcon#read 6, iclass 26, count 2 2006.285.09:19:10.30#ibcon#end of sib2, iclass 26, count 2 2006.285.09:19:10.30#ibcon#*mode == 0, iclass 26, count 2 2006.285.09:19:10.30#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.09:19:10.30#ibcon#[27=AT03-04\r\n] 2006.285.09:19:10.30#ibcon#*before write, iclass 26, count 2 2006.285.09:19:10.30#ibcon#enter sib2, iclass 26, count 2 2006.285.09:19:10.30#ibcon#flushed, iclass 26, count 2 2006.285.09:19:10.30#ibcon#about to write, iclass 26, count 2 2006.285.09:19:10.30#ibcon#wrote, iclass 26, count 2 2006.285.09:19:10.30#ibcon#about to read 3, iclass 26, count 2 2006.285.09:19:10.33#ibcon#read 3, iclass 26, count 2 2006.285.09:19:10.33#ibcon#about to read 4, iclass 26, count 2 2006.285.09:19:10.33#ibcon#read 4, iclass 26, count 2 2006.285.09:19:10.33#ibcon#about to read 5, iclass 26, count 2 2006.285.09:19:10.33#ibcon#read 5, iclass 26, count 2 2006.285.09:19:10.33#ibcon#about to read 6, iclass 26, count 2 2006.285.09:19:10.33#ibcon#read 6, iclass 26, count 2 2006.285.09:19:10.33#ibcon#end of sib2, iclass 26, count 2 2006.285.09:19:10.33#ibcon#*after write, iclass 26, count 2 2006.285.09:19:10.33#ibcon#*before return 0, iclass 26, count 2 2006.285.09:19:10.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:19:10.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:19:10.33#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.09:19:10.33#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:10.33#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:19:10.45#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:19:10.45#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:19:10.45#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:19:10.45#ibcon#first serial, iclass 26, count 0 2006.285.09:19:10.45#ibcon#enter sib2, iclass 26, count 0 2006.285.09:19:10.45#ibcon#flushed, iclass 26, count 0 2006.285.09:19:10.45#ibcon#about to write, iclass 26, count 0 2006.285.09:19:10.45#ibcon#wrote, iclass 26, count 0 2006.285.09:19:10.45#ibcon#about to read 3, iclass 26, count 0 2006.285.09:19:10.47#ibcon#read 3, iclass 26, count 0 2006.285.09:19:10.47#ibcon#about to read 4, iclass 26, count 0 2006.285.09:19:10.47#ibcon#read 4, iclass 26, count 0 2006.285.09:19:10.47#ibcon#about to read 5, iclass 26, count 0 2006.285.09:19:10.47#ibcon#read 5, iclass 26, count 0 2006.285.09:19:10.47#ibcon#about to read 6, iclass 26, count 0 2006.285.09:19:10.47#ibcon#read 6, iclass 26, count 0 2006.285.09:19:10.47#ibcon#end of sib2, iclass 26, count 0 2006.285.09:19:10.47#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:19:10.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:19:10.47#ibcon#[27=USB\r\n] 2006.285.09:19:10.47#ibcon#*before write, iclass 26, count 0 2006.285.09:19:10.47#ibcon#enter sib2, iclass 26, count 0 2006.285.09:19:10.47#ibcon#flushed, iclass 26, count 0 2006.285.09:19:10.47#ibcon#about to write, iclass 26, count 0 2006.285.09:19:10.47#ibcon#wrote, iclass 26, count 0 2006.285.09:19:10.47#ibcon#about to read 3, iclass 26, count 0 2006.285.09:19:10.50#ibcon#read 3, iclass 26, count 0 2006.285.09:19:10.50#ibcon#about to read 4, iclass 26, count 0 2006.285.09:19:10.50#ibcon#read 4, iclass 26, count 0 2006.285.09:19:10.50#ibcon#about to read 5, iclass 26, count 0 2006.285.09:19:10.50#ibcon#read 5, iclass 26, count 0 2006.285.09:19:10.50#ibcon#about to read 6, iclass 26, count 0 2006.285.09:19:10.50#ibcon#read 6, iclass 26, count 0 2006.285.09:19:10.50#ibcon#end of sib2, iclass 26, count 0 2006.285.09:19:10.50#ibcon#*after write, iclass 26, count 0 2006.285.09:19:10.50#ibcon#*before return 0, iclass 26, count 0 2006.285.09:19:10.50#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:19:10.50#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:19:10.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:19:10.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:19:10.50$vck44/vblo=4,679.99 2006.285.09:19:10.50#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.09:19:10.50#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.09:19:10.50#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:10.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:19:10.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:19:10.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:19:10.50#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:19:10.50#ibcon#first serial, iclass 28, count 0 2006.285.09:19:10.50#ibcon#enter sib2, iclass 28, count 0 2006.285.09:19:10.50#ibcon#flushed, iclass 28, count 0 2006.285.09:19:10.50#ibcon#about to write, iclass 28, count 0 2006.285.09:19:10.50#ibcon#wrote, iclass 28, count 0 2006.285.09:19:10.50#ibcon#about to read 3, iclass 28, count 0 2006.285.09:19:10.52#ibcon#read 3, iclass 28, count 0 2006.285.09:19:10.52#ibcon#about to read 4, iclass 28, count 0 2006.285.09:19:10.52#ibcon#read 4, iclass 28, count 0 2006.285.09:19:10.52#ibcon#about to read 5, iclass 28, count 0 2006.285.09:19:10.52#ibcon#read 5, iclass 28, count 0 2006.285.09:19:10.52#ibcon#about to read 6, iclass 28, count 0 2006.285.09:19:10.52#ibcon#read 6, iclass 28, count 0 2006.285.09:19:10.52#ibcon#end of sib2, iclass 28, count 0 2006.285.09:19:10.52#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:19:10.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:19:10.52#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:19:10.52#ibcon#*before write, iclass 28, count 0 2006.285.09:19:10.52#ibcon#enter sib2, iclass 28, count 0 2006.285.09:19:10.52#ibcon#flushed, iclass 28, count 0 2006.285.09:19:10.52#ibcon#about to write, iclass 28, count 0 2006.285.09:19:10.52#ibcon#wrote, iclass 28, count 0 2006.285.09:19:10.52#ibcon#about to read 3, iclass 28, count 0 2006.285.09:19:10.56#ibcon#read 3, iclass 28, count 0 2006.285.09:19:10.56#ibcon#about to read 4, iclass 28, count 0 2006.285.09:19:10.56#ibcon#read 4, iclass 28, count 0 2006.285.09:19:10.56#ibcon#about to read 5, iclass 28, count 0 2006.285.09:19:10.56#ibcon#read 5, iclass 28, count 0 2006.285.09:19:10.56#ibcon#about to read 6, iclass 28, count 0 2006.285.09:19:10.56#ibcon#read 6, iclass 28, count 0 2006.285.09:19:10.56#ibcon#end of sib2, iclass 28, count 0 2006.285.09:19:10.56#ibcon#*after write, iclass 28, count 0 2006.285.09:19:10.56#ibcon#*before return 0, iclass 28, count 0 2006.285.09:19:10.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:19:10.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:19:10.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:19:10.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:19:10.56$vck44/vb=4,5 2006.285.09:19:10.56#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.09:19:10.56#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.09:19:10.56#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:10.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:19:10.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:19:10.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:19:10.62#ibcon#enter wrdev, iclass 30, count 2 2006.285.09:19:10.62#ibcon#first serial, iclass 30, count 2 2006.285.09:19:10.62#ibcon#enter sib2, iclass 30, count 2 2006.285.09:19:10.62#ibcon#flushed, iclass 30, count 2 2006.285.09:19:10.62#ibcon#about to write, iclass 30, count 2 2006.285.09:19:10.62#ibcon#wrote, iclass 30, count 2 2006.285.09:19:10.62#ibcon#about to read 3, iclass 30, count 2 2006.285.09:19:10.64#ibcon#read 3, iclass 30, count 2 2006.285.09:19:10.64#ibcon#about to read 4, iclass 30, count 2 2006.285.09:19:10.64#ibcon#read 4, iclass 30, count 2 2006.285.09:19:10.64#ibcon#about to read 5, iclass 30, count 2 2006.285.09:19:10.64#ibcon#read 5, iclass 30, count 2 2006.285.09:19:10.64#ibcon#about to read 6, iclass 30, count 2 2006.285.09:19:10.64#ibcon#read 6, iclass 30, count 2 2006.285.09:19:10.64#ibcon#end of sib2, iclass 30, count 2 2006.285.09:19:10.64#ibcon#*mode == 0, iclass 30, count 2 2006.285.09:19:10.64#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.09:19:10.64#ibcon#[27=AT04-05\r\n] 2006.285.09:19:10.64#ibcon#*before write, iclass 30, count 2 2006.285.09:19:10.64#ibcon#enter sib2, iclass 30, count 2 2006.285.09:19:10.64#ibcon#flushed, iclass 30, count 2 2006.285.09:19:10.64#ibcon#about to write, iclass 30, count 2 2006.285.09:19:10.64#ibcon#wrote, iclass 30, count 2 2006.285.09:19:10.64#ibcon#about to read 3, iclass 30, count 2 2006.285.09:19:10.67#ibcon#read 3, iclass 30, count 2 2006.285.09:19:10.67#ibcon#about to read 4, iclass 30, count 2 2006.285.09:19:10.67#ibcon#read 4, iclass 30, count 2 2006.285.09:19:10.67#ibcon#about to read 5, iclass 30, count 2 2006.285.09:19:10.67#ibcon#read 5, iclass 30, count 2 2006.285.09:19:10.67#ibcon#about to read 6, iclass 30, count 2 2006.285.09:19:10.67#ibcon#read 6, iclass 30, count 2 2006.285.09:19:10.67#ibcon#end of sib2, iclass 30, count 2 2006.285.09:19:10.67#ibcon#*after write, iclass 30, count 2 2006.285.09:19:10.67#ibcon#*before return 0, iclass 30, count 2 2006.285.09:19:10.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:19:10.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:19:10.67#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.09:19:10.67#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:10.67#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:19:10.79#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:19:10.79#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:19:10.79#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:19:10.79#ibcon#first serial, iclass 30, count 0 2006.285.09:19:10.79#ibcon#enter sib2, iclass 30, count 0 2006.285.09:19:10.79#ibcon#flushed, iclass 30, count 0 2006.285.09:19:10.79#ibcon#about to write, iclass 30, count 0 2006.285.09:19:10.79#ibcon#wrote, iclass 30, count 0 2006.285.09:19:10.79#ibcon#about to read 3, iclass 30, count 0 2006.285.09:19:10.81#ibcon#read 3, iclass 30, count 0 2006.285.09:19:10.81#ibcon#about to read 4, iclass 30, count 0 2006.285.09:19:10.81#ibcon#read 4, iclass 30, count 0 2006.285.09:19:10.81#ibcon#about to read 5, iclass 30, count 0 2006.285.09:19:10.81#ibcon#read 5, iclass 30, count 0 2006.285.09:19:10.81#ibcon#about to read 6, iclass 30, count 0 2006.285.09:19:10.81#ibcon#read 6, iclass 30, count 0 2006.285.09:19:10.81#ibcon#end of sib2, iclass 30, count 0 2006.285.09:19:10.81#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:19:10.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:19:10.81#ibcon#[27=USB\r\n] 2006.285.09:19:10.81#ibcon#*before write, iclass 30, count 0 2006.285.09:19:10.81#ibcon#enter sib2, iclass 30, count 0 2006.285.09:19:10.81#ibcon#flushed, iclass 30, count 0 2006.285.09:19:10.81#ibcon#about to write, iclass 30, count 0 2006.285.09:19:10.81#ibcon#wrote, iclass 30, count 0 2006.285.09:19:10.81#ibcon#about to read 3, iclass 30, count 0 2006.285.09:19:10.84#ibcon#read 3, iclass 30, count 0 2006.285.09:19:10.84#ibcon#about to read 4, iclass 30, count 0 2006.285.09:19:10.84#ibcon#read 4, iclass 30, count 0 2006.285.09:19:10.84#ibcon#about to read 5, iclass 30, count 0 2006.285.09:19:10.84#ibcon#read 5, iclass 30, count 0 2006.285.09:19:10.84#ibcon#about to read 6, iclass 30, count 0 2006.285.09:19:10.84#ibcon#read 6, iclass 30, count 0 2006.285.09:19:10.84#ibcon#end of sib2, iclass 30, count 0 2006.285.09:19:10.84#ibcon#*after write, iclass 30, count 0 2006.285.09:19:10.84#ibcon#*before return 0, iclass 30, count 0 2006.285.09:19:10.84#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:19:10.84#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:19:10.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:19:10.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:19:10.84$vck44/vblo=5,709.99 2006.285.09:19:10.84#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.09:19:10.84#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.09:19:10.84#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:10.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:19:10.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:19:10.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:19:10.84#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:19:10.84#ibcon#first serial, iclass 32, count 0 2006.285.09:19:10.84#ibcon#enter sib2, iclass 32, count 0 2006.285.09:19:10.84#ibcon#flushed, iclass 32, count 0 2006.285.09:19:10.84#ibcon#about to write, iclass 32, count 0 2006.285.09:19:10.84#ibcon#wrote, iclass 32, count 0 2006.285.09:19:10.84#ibcon#about to read 3, iclass 32, count 0 2006.285.09:19:10.86#ibcon#read 3, iclass 32, count 0 2006.285.09:19:10.86#ibcon#about to read 4, iclass 32, count 0 2006.285.09:19:10.86#ibcon#read 4, iclass 32, count 0 2006.285.09:19:10.86#ibcon#about to read 5, iclass 32, count 0 2006.285.09:19:10.86#ibcon#read 5, iclass 32, count 0 2006.285.09:19:10.86#ibcon#about to read 6, iclass 32, count 0 2006.285.09:19:10.86#ibcon#read 6, iclass 32, count 0 2006.285.09:19:10.86#ibcon#end of sib2, iclass 32, count 0 2006.285.09:19:10.86#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:19:10.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:19:10.86#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:19:10.86#ibcon#*before write, iclass 32, count 0 2006.285.09:19:10.86#ibcon#enter sib2, iclass 32, count 0 2006.285.09:19:10.86#ibcon#flushed, iclass 32, count 0 2006.285.09:19:10.86#ibcon#about to write, iclass 32, count 0 2006.285.09:19:10.86#ibcon#wrote, iclass 32, count 0 2006.285.09:19:10.86#ibcon#about to read 3, iclass 32, count 0 2006.285.09:19:10.90#ibcon#read 3, iclass 32, count 0 2006.285.09:19:10.90#ibcon#about to read 4, iclass 32, count 0 2006.285.09:19:10.90#ibcon#read 4, iclass 32, count 0 2006.285.09:19:10.90#ibcon#about to read 5, iclass 32, count 0 2006.285.09:19:10.90#ibcon#read 5, iclass 32, count 0 2006.285.09:19:10.90#ibcon#about to read 6, iclass 32, count 0 2006.285.09:19:10.90#ibcon#read 6, iclass 32, count 0 2006.285.09:19:10.90#ibcon#end of sib2, iclass 32, count 0 2006.285.09:19:10.90#ibcon#*after write, iclass 32, count 0 2006.285.09:19:10.90#ibcon#*before return 0, iclass 32, count 0 2006.285.09:19:10.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:19:10.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:19:10.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:19:10.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:19:10.90$vck44/vb=5,4 2006.285.09:19:10.90#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.09:19:10.90#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.09:19:10.90#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:10.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:19:10.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:19:10.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:19:10.96#ibcon#enter wrdev, iclass 34, count 2 2006.285.09:19:10.96#ibcon#first serial, iclass 34, count 2 2006.285.09:19:10.96#ibcon#enter sib2, iclass 34, count 2 2006.285.09:19:10.96#ibcon#flushed, iclass 34, count 2 2006.285.09:19:10.96#ibcon#about to write, iclass 34, count 2 2006.285.09:19:10.96#ibcon#wrote, iclass 34, count 2 2006.285.09:19:10.96#ibcon#about to read 3, iclass 34, count 2 2006.285.09:19:10.98#ibcon#read 3, iclass 34, count 2 2006.285.09:19:10.98#ibcon#about to read 4, iclass 34, count 2 2006.285.09:19:10.98#ibcon#read 4, iclass 34, count 2 2006.285.09:19:10.98#ibcon#about to read 5, iclass 34, count 2 2006.285.09:19:10.98#ibcon#read 5, iclass 34, count 2 2006.285.09:19:10.98#ibcon#about to read 6, iclass 34, count 2 2006.285.09:19:10.98#ibcon#read 6, iclass 34, count 2 2006.285.09:19:10.98#ibcon#end of sib2, iclass 34, count 2 2006.285.09:19:10.98#ibcon#*mode == 0, iclass 34, count 2 2006.285.09:19:10.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.09:19:10.98#ibcon#[27=AT05-04\r\n] 2006.285.09:19:10.98#ibcon#*before write, iclass 34, count 2 2006.285.09:19:10.98#ibcon#enter sib2, iclass 34, count 2 2006.285.09:19:10.98#ibcon#flushed, iclass 34, count 2 2006.285.09:19:10.98#ibcon#about to write, iclass 34, count 2 2006.285.09:19:10.98#ibcon#wrote, iclass 34, count 2 2006.285.09:19:10.98#ibcon#about to read 3, iclass 34, count 2 2006.285.09:19:11.01#ibcon#read 3, iclass 34, count 2 2006.285.09:19:11.01#ibcon#about to read 4, iclass 34, count 2 2006.285.09:19:11.01#ibcon#read 4, iclass 34, count 2 2006.285.09:19:11.01#ibcon#about to read 5, iclass 34, count 2 2006.285.09:19:11.01#ibcon#read 5, iclass 34, count 2 2006.285.09:19:11.01#ibcon#about to read 6, iclass 34, count 2 2006.285.09:19:11.01#ibcon#read 6, iclass 34, count 2 2006.285.09:19:11.01#ibcon#end of sib2, iclass 34, count 2 2006.285.09:19:11.01#ibcon#*after write, iclass 34, count 2 2006.285.09:19:11.01#ibcon#*before return 0, iclass 34, count 2 2006.285.09:19:11.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:19:11.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:19:11.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.09:19:11.01#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:11.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:19:11.13#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:19:11.13#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:19:11.13#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:19:11.13#ibcon#first serial, iclass 34, count 0 2006.285.09:19:11.13#ibcon#enter sib2, iclass 34, count 0 2006.285.09:19:11.13#ibcon#flushed, iclass 34, count 0 2006.285.09:19:11.13#ibcon#about to write, iclass 34, count 0 2006.285.09:19:11.13#ibcon#wrote, iclass 34, count 0 2006.285.09:19:11.13#ibcon#about to read 3, iclass 34, count 0 2006.285.09:19:11.15#ibcon#read 3, iclass 34, count 0 2006.285.09:19:11.15#ibcon#about to read 4, iclass 34, count 0 2006.285.09:19:11.15#ibcon#read 4, iclass 34, count 0 2006.285.09:19:11.15#ibcon#about to read 5, iclass 34, count 0 2006.285.09:19:11.15#ibcon#read 5, iclass 34, count 0 2006.285.09:19:11.15#ibcon#about to read 6, iclass 34, count 0 2006.285.09:19:11.15#ibcon#read 6, iclass 34, count 0 2006.285.09:19:11.15#ibcon#end of sib2, iclass 34, count 0 2006.285.09:19:11.15#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:19:11.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:19:11.15#ibcon#[27=USB\r\n] 2006.285.09:19:11.15#ibcon#*before write, iclass 34, count 0 2006.285.09:19:11.15#ibcon#enter sib2, iclass 34, count 0 2006.285.09:19:11.15#ibcon#flushed, iclass 34, count 0 2006.285.09:19:11.15#ibcon#about to write, iclass 34, count 0 2006.285.09:19:11.15#ibcon#wrote, iclass 34, count 0 2006.285.09:19:11.15#ibcon#about to read 3, iclass 34, count 0 2006.285.09:19:11.18#ibcon#read 3, iclass 34, count 0 2006.285.09:19:11.18#ibcon#about to read 4, iclass 34, count 0 2006.285.09:19:11.18#ibcon#read 4, iclass 34, count 0 2006.285.09:19:11.18#ibcon#about to read 5, iclass 34, count 0 2006.285.09:19:11.18#ibcon#read 5, iclass 34, count 0 2006.285.09:19:11.18#ibcon#about to read 6, iclass 34, count 0 2006.285.09:19:11.18#ibcon#read 6, iclass 34, count 0 2006.285.09:19:11.18#ibcon#end of sib2, iclass 34, count 0 2006.285.09:19:11.18#ibcon#*after write, iclass 34, count 0 2006.285.09:19:11.18#ibcon#*before return 0, iclass 34, count 0 2006.285.09:19:11.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:19:11.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:19:11.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:19:11.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:19:11.18$vck44/vblo=6,719.99 2006.285.09:19:11.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.09:19:11.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.09:19:11.18#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:11.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:19:11.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:19:11.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:19:11.18#ibcon#enter wrdev, iclass 36, count 0 2006.285.09:19:11.18#ibcon#first serial, iclass 36, count 0 2006.285.09:19:11.18#ibcon#enter sib2, iclass 36, count 0 2006.285.09:19:11.18#ibcon#flushed, iclass 36, count 0 2006.285.09:19:11.18#ibcon#about to write, iclass 36, count 0 2006.285.09:19:11.18#ibcon#wrote, iclass 36, count 0 2006.285.09:19:11.18#ibcon#about to read 3, iclass 36, count 0 2006.285.09:19:11.20#ibcon#read 3, iclass 36, count 0 2006.285.09:19:11.20#ibcon#about to read 4, iclass 36, count 0 2006.285.09:19:11.20#ibcon#read 4, iclass 36, count 0 2006.285.09:19:11.20#ibcon#about to read 5, iclass 36, count 0 2006.285.09:19:11.20#ibcon#read 5, iclass 36, count 0 2006.285.09:19:11.20#ibcon#about to read 6, iclass 36, count 0 2006.285.09:19:11.20#ibcon#read 6, iclass 36, count 0 2006.285.09:19:11.20#ibcon#end of sib2, iclass 36, count 0 2006.285.09:19:11.20#ibcon#*mode == 0, iclass 36, count 0 2006.285.09:19:11.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.09:19:11.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:19:11.20#ibcon#*before write, iclass 36, count 0 2006.285.09:19:11.20#ibcon#enter sib2, iclass 36, count 0 2006.285.09:19:11.20#ibcon#flushed, iclass 36, count 0 2006.285.09:19:11.20#ibcon#about to write, iclass 36, count 0 2006.285.09:19:11.20#ibcon#wrote, iclass 36, count 0 2006.285.09:19:11.20#ibcon#about to read 3, iclass 36, count 0 2006.285.09:19:11.24#ibcon#read 3, iclass 36, count 0 2006.285.09:19:11.24#ibcon#about to read 4, iclass 36, count 0 2006.285.09:19:11.24#ibcon#read 4, iclass 36, count 0 2006.285.09:19:11.24#ibcon#about to read 5, iclass 36, count 0 2006.285.09:19:11.24#ibcon#read 5, iclass 36, count 0 2006.285.09:19:11.24#ibcon#about to read 6, iclass 36, count 0 2006.285.09:19:11.24#ibcon#read 6, iclass 36, count 0 2006.285.09:19:11.24#ibcon#end of sib2, iclass 36, count 0 2006.285.09:19:11.24#ibcon#*after write, iclass 36, count 0 2006.285.09:19:11.24#ibcon#*before return 0, iclass 36, count 0 2006.285.09:19:11.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:19:11.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:19:11.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.09:19:11.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.09:19:11.24$vck44/vb=6,3 2006.285.09:19:11.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.09:19:11.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.09:19:11.24#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:11.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:19:11.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:19:11.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:19:11.30#ibcon#enter wrdev, iclass 38, count 2 2006.285.09:19:11.30#ibcon#first serial, iclass 38, count 2 2006.285.09:19:11.30#ibcon#enter sib2, iclass 38, count 2 2006.285.09:19:11.30#ibcon#flushed, iclass 38, count 2 2006.285.09:19:11.30#ibcon#about to write, iclass 38, count 2 2006.285.09:19:11.30#ibcon#wrote, iclass 38, count 2 2006.285.09:19:11.30#ibcon#about to read 3, iclass 38, count 2 2006.285.09:19:11.32#ibcon#read 3, iclass 38, count 2 2006.285.09:19:11.32#ibcon#about to read 4, iclass 38, count 2 2006.285.09:19:11.32#ibcon#read 4, iclass 38, count 2 2006.285.09:19:11.32#ibcon#about to read 5, iclass 38, count 2 2006.285.09:19:11.32#ibcon#read 5, iclass 38, count 2 2006.285.09:19:11.32#ibcon#about to read 6, iclass 38, count 2 2006.285.09:19:11.32#ibcon#read 6, iclass 38, count 2 2006.285.09:19:11.32#ibcon#end of sib2, iclass 38, count 2 2006.285.09:19:11.32#ibcon#*mode == 0, iclass 38, count 2 2006.285.09:19:11.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.09:19:11.32#ibcon#[27=AT06-03\r\n] 2006.285.09:19:11.32#ibcon#*before write, iclass 38, count 2 2006.285.09:19:11.32#ibcon#enter sib2, iclass 38, count 2 2006.285.09:19:11.32#ibcon#flushed, iclass 38, count 2 2006.285.09:19:11.32#ibcon#about to write, iclass 38, count 2 2006.285.09:19:11.32#ibcon#wrote, iclass 38, count 2 2006.285.09:19:11.32#ibcon#about to read 3, iclass 38, count 2 2006.285.09:19:11.35#ibcon#read 3, iclass 38, count 2 2006.285.09:19:11.35#ibcon#about to read 4, iclass 38, count 2 2006.285.09:19:11.35#ibcon#read 4, iclass 38, count 2 2006.285.09:19:11.35#ibcon#about to read 5, iclass 38, count 2 2006.285.09:19:11.35#ibcon#read 5, iclass 38, count 2 2006.285.09:19:11.35#ibcon#about to read 6, iclass 38, count 2 2006.285.09:19:11.35#ibcon#read 6, iclass 38, count 2 2006.285.09:19:11.35#ibcon#end of sib2, iclass 38, count 2 2006.285.09:19:11.35#ibcon#*after write, iclass 38, count 2 2006.285.09:19:11.35#ibcon#*before return 0, iclass 38, count 2 2006.285.09:19:11.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:19:11.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:19:11.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.09:19:11.35#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:11.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:19:11.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:19:11.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:19:11.47#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:19:11.47#ibcon#first serial, iclass 38, count 0 2006.285.09:19:11.47#ibcon#enter sib2, iclass 38, count 0 2006.285.09:19:11.47#ibcon#flushed, iclass 38, count 0 2006.285.09:19:11.47#ibcon#about to write, iclass 38, count 0 2006.285.09:19:11.47#ibcon#wrote, iclass 38, count 0 2006.285.09:19:11.47#ibcon#about to read 3, iclass 38, count 0 2006.285.09:19:11.49#ibcon#read 3, iclass 38, count 0 2006.285.09:19:11.49#ibcon#about to read 4, iclass 38, count 0 2006.285.09:19:11.49#ibcon#read 4, iclass 38, count 0 2006.285.09:19:11.49#ibcon#about to read 5, iclass 38, count 0 2006.285.09:19:11.49#ibcon#read 5, iclass 38, count 0 2006.285.09:19:11.49#ibcon#about to read 6, iclass 38, count 0 2006.285.09:19:11.49#ibcon#read 6, iclass 38, count 0 2006.285.09:19:11.49#ibcon#end of sib2, iclass 38, count 0 2006.285.09:19:11.49#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:19:11.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:19:11.49#ibcon#[27=USB\r\n] 2006.285.09:19:11.49#ibcon#*before write, iclass 38, count 0 2006.285.09:19:11.49#ibcon#enter sib2, iclass 38, count 0 2006.285.09:19:11.49#ibcon#flushed, iclass 38, count 0 2006.285.09:19:11.49#ibcon#about to write, iclass 38, count 0 2006.285.09:19:11.49#ibcon#wrote, iclass 38, count 0 2006.285.09:19:11.49#ibcon#about to read 3, iclass 38, count 0 2006.285.09:19:11.52#ibcon#read 3, iclass 38, count 0 2006.285.09:19:11.52#ibcon#about to read 4, iclass 38, count 0 2006.285.09:19:11.52#ibcon#read 4, iclass 38, count 0 2006.285.09:19:11.52#ibcon#about to read 5, iclass 38, count 0 2006.285.09:19:11.52#ibcon#read 5, iclass 38, count 0 2006.285.09:19:11.52#ibcon#about to read 6, iclass 38, count 0 2006.285.09:19:11.52#ibcon#read 6, iclass 38, count 0 2006.285.09:19:11.52#ibcon#end of sib2, iclass 38, count 0 2006.285.09:19:11.52#ibcon#*after write, iclass 38, count 0 2006.285.09:19:11.52#ibcon#*before return 0, iclass 38, count 0 2006.285.09:19:11.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:19:11.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:19:11.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:19:11.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:19:11.52$vck44/vblo=7,734.99 2006.285.09:19:11.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.09:19:11.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.09:19:11.52#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:11.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:19:11.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:19:11.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:19:11.52#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:19:11.52#ibcon#first serial, iclass 40, count 0 2006.285.09:19:11.52#ibcon#enter sib2, iclass 40, count 0 2006.285.09:19:11.52#ibcon#flushed, iclass 40, count 0 2006.285.09:19:11.52#ibcon#about to write, iclass 40, count 0 2006.285.09:19:11.52#ibcon#wrote, iclass 40, count 0 2006.285.09:19:11.52#ibcon#about to read 3, iclass 40, count 0 2006.285.09:19:11.54#ibcon#read 3, iclass 40, count 0 2006.285.09:19:11.54#ibcon#about to read 4, iclass 40, count 0 2006.285.09:19:11.54#ibcon#read 4, iclass 40, count 0 2006.285.09:19:11.54#ibcon#about to read 5, iclass 40, count 0 2006.285.09:19:11.54#ibcon#read 5, iclass 40, count 0 2006.285.09:19:11.54#ibcon#about to read 6, iclass 40, count 0 2006.285.09:19:11.54#ibcon#read 6, iclass 40, count 0 2006.285.09:19:11.54#ibcon#end of sib2, iclass 40, count 0 2006.285.09:19:11.54#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:19:11.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:19:11.54#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:19:11.54#ibcon#*before write, iclass 40, count 0 2006.285.09:19:11.54#ibcon#enter sib2, iclass 40, count 0 2006.285.09:19:11.54#ibcon#flushed, iclass 40, count 0 2006.285.09:19:11.54#ibcon#about to write, iclass 40, count 0 2006.285.09:19:11.54#ibcon#wrote, iclass 40, count 0 2006.285.09:19:11.54#ibcon#about to read 3, iclass 40, count 0 2006.285.09:19:11.58#ibcon#read 3, iclass 40, count 0 2006.285.09:19:11.58#ibcon#about to read 4, iclass 40, count 0 2006.285.09:19:11.58#ibcon#read 4, iclass 40, count 0 2006.285.09:19:11.58#ibcon#about to read 5, iclass 40, count 0 2006.285.09:19:11.58#ibcon#read 5, iclass 40, count 0 2006.285.09:19:11.58#ibcon#about to read 6, iclass 40, count 0 2006.285.09:19:11.58#ibcon#read 6, iclass 40, count 0 2006.285.09:19:11.58#ibcon#end of sib2, iclass 40, count 0 2006.285.09:19:11.58#ibcon#*after write, iclass 40, count 0 2006.285.09:19:11.58#ibcon#*before return 0, iclass 40, count 0 2006.285.09:19:11.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:19:11.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:19:11.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:19:11.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:19:11.58$vck44/vb=7,4 2006.285.09:19:11.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.09:19:11.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.09:19:11.58#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:11.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:19:11.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:19:11.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:19:11.64#ibcon#enter wrdev, iclass 4, count 2 2006.285.09:19:11.64#ibcon#first serial, iclass 4, count 2 2006.285.09:19:11.64#ibcon#enter sib2, iclass 4, count 2 2006.285.09:19:11.64#ibcon#flushed, iclass 4, count 2 2006.285.09:19:11.64#ibcon#about to write, iclass 4, count 2 2006.285.09:19:11.64#ibcon#wrote, iclass 4, count 2 2006.285.09:19:11.64#ibcon#about to read 3, iclass 4, count 2 2006.285.09:19:11.66#ibcon#read 3, iclass 4, count 2 2006.285.09:19:11.66#ibcon#about to read 4, iclass 4, count 2 2006.285.09:19:11.66#ibcon#read 4, iclass 4, count 2 2006.285.09:19:11.66#ibcon#about to read 5, iclass 4, count 2 2006.285.09:19:11.66#ibcon#read 5, iclass 4, count 2 2006.285.09:19:11.66#ibcon#about to read 6, iclass 4, count 2 2006.285.09:19:11.66#ibcon#read 6, iclass 4, count 2 2006.285.09:19:11.66#ibcon#end of sib2, iclass 4, count 2 2006.285.09:19:11.66#ibcon#*mode == 0, iclass 4, count 2 2006.285.09:19:11.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.09:19:11.66#ibcon#[27=AT07-04\r\n] 2006.285.09:19:11.66#ibcon#*before write, iclass 4, count 2 2006.285.09:19:11.66#ibcon#enter sib2, iclass 4, count 2 2006.285.09:19:11.66#ibcon#flushed, iclass 4, count 2 2006.285.09:19:11.66#ibcon#about to write, iclass 4, count 2 2006.285.09:19:11.66#ibcon#wrote, iclass 4, count 2 2006.285.09:19:11.66#ibcon#about to read 3, iclass 4, count 2 2006.285.09:19:11.69#ibcon#read 3, iclass 4, count 2 2006.285.09:19:11.69#ibcon#about to read 4, iclass 4, count 2 2006.285.09:19:11.69#ibcon#read 4, iclass 4, count 2 2006.285.09:19:11.69#ibcon#about to read 5, iclass 4, count 2 2006.285.09:19:11.69#ibcon#read 5, iclass 4, count 2 2006.285.09:19:11.69#ibcon#about to read 6, iclass 4, count 2 2006.285.09:19:11.69#ibcon#read 6, iclass 4, count 2 2006.285.09:19:11.69#ibcon#end of sib2, iclass 4, count 2 2006.285.09:19:11.69#ibcon#*after write, iclass 4, count 2 2006.285.09:19:11.69#ibcon#*before return 0, iclass 4, count 2 2006.285.09:19:11.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:19:11.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:19:11.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.09:19:11.69#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:11.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:19:11.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:19:11.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:19:11.81#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:19:11.81#ibcon#first serial, iclass 4, count 0 2006.285.09:19:11.81#ibcon#enter sib2, iclass 4, count 0 2006.285.09:19:11.81#ibcon#flushed, iclass 4, count 0 2006.285.09:19:11.81#ibcon#about to write, iclass 4, count 0 2006.285.09:19:11.81#ibcon#wrote, iclass 4, count 0 2006.285.09:19:11.81#ibcon#about to read 3, iclass 4, count 0 2006.285.09:19:11.83#ibcon#read 3, iclass 4, count 0 2006.285.09:19:11.83#ibcon#about to read 4, iclass 4, count 0 2006.285.09:19:11.83#ibcon#read 4, iclass 4, count 0 2006.285.09:19:11.83#ibcon#about to read 5, iclass 4, count 0 2006.285.09:19:11.83#ibcon#read 5, iclass 4, count 0 2006.285.09:19:11.83#ibcon#about to read 6, iclass 4, count 0 2006.285.09:19:11.83#ibcon#read 6, iclass 4, count 0 2006.285.09:19:11.83#ibcon#end of sib2, iclass 4, count 0 2006.285.09:19:11.83#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:19:11.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:19:11.83#ibcon#[27=USB\r\n] 2006.285.09:19:11.83#ibcon#*before write, iclass 4, count 0 2006.285.09:19:11.83#ibcon#enter sib2, iclass 4, count 0 2006.285.09:19:11.83#ibcon#flushed, iclass 4, count 0 2006.285.09:19:11.83#ibcon#about to write, iclass 4, count 0 2006.285.09:19:11.83#ibcon#wrote, iclass 4, count 0 2006.285.09:19:11.83#ibcon#about to read 3, iclass 4, count 0 2006.285.09:19:11.86#ibcon#read 3, iclass 4, count 0 2006.285.09:19:11.86#ibcon#about to read 4, iclass 4, count 0 2006.285.09:19:11.86#ibcon#read 4, iclass 4, count 0 2006.285.09:19:11.86#ibcon#about to read 5, iclass 4, count 0 2006.285.09:19:11.86#ibcon#read 5, iclass 4, count 0 2006.285.09:19:11.86#ibcon#about to read 6, iclass 4, count 0 2006.285.09:19:11.86#ibcon#read 6, iclass 4, count 0 2006.285.09:19:11.86#ibcon#end of sib2, iclass 4, count 0 2006.285.09:19:11.86#ibcon#*after write, iclass 4, count 0 2006.285.09:19:11.86#ibcon#*before return 0, iclass 4, count 0 2006.285.09:19:11.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:19:11.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:19:11.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:19:11.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:19:11.86$vck44/vblo=8,744.99 2006.285.09:19:11.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.09:19:11.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.09:19:11.86#ibcon#ireg 17 cls_cnt 0 2006.285.09:19:11.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:19:11.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:19:11.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:19:11.86#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:19:11.86#ibcon#first serial, iclass 6, count 0 2006.285.09:19:11.86#ibcon#enter sib2, iclass 6, count 0 2006.285.09:19:11.86#ibcon#flushed, iclass 6, count 0 2006.285.09:19:11.86#ibcon#about to write, iclass 6, count 0 2006.285.09:19:11.86#ibcon#wrote, iclass 6, count 0 2006.285.09:19:11.86#ibcon#about to read 3, iclass 6, count 0 2006.285.09:19:11.88#ibcon#read 3, iclass 6, count 0 2006.285.09:19:11.88#ibcon#about to read 4, iclass 6, count 0 2006.285.09:19:11.88#ibcon#read 4, iclass 6, count 0 2006.285.09:19:11.88#ibcon#about to read 5, iclass 6, count 0 2006.285.09:19:11.88#ibcon#read 5, iclass 6, count 0 2006.285.09:19:11.88#ibcon#about to read 6, iclass 6, count 0 2006.285.09:19:11.88#ibcon#read 6, iclass 6, count 0 2006.285.09:19:11.88#ibcon#end of sib2, iclass 6, count 0 2006.285.09:19:11.88#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:19:11.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:19:11.88#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:19:11.88#ibcon#*before write, iclass 6, count 0 2006.285.09:19:11.88#ibcon#enter sib2, iclass 6, count 0 2006.285.09:19:11.88#ibcon#flushed, iclass 6, count 0 2006.285.09:19:11.88#ibcon#about to write, iclass 6, count 0 2006.285.09:19:11.88#ibcon#wrote, iclass 6, count 0 2006.285.09:19:11.88#ibcon#about to read 3, iclass 6, count 0 2006.285.09:19:11.92#ibcon#read 3, iclass 6, count 0 2006.285.09:19:11.92#ibcon#about to read 4, iclass 6, count 0 2006.285.09:19:11.92#ibcon#read 4, iclass 6, count 0 2006.285.09:19:11.92#ibcon#about to read 5, iclass 6, count 0 2006.285.09:19:11.92#ibcon#read 5, iclass 6, count 0 2006.285.09:19:11.92#ibcon#about to read 6, iclass 6, count 0 2006.285.09:19:11.92#ibcon#read 6, iclass 6, count 0 2006.285.09:19:11.92#ibcon#end of sib2, iclass 6, count 0 2006.285.09:19:11.92#ibcon#*after write, iclass 6, count 0 2006.285.09:19:11.92#ibcon#*before return 0, iclass 6, count 0 2006.285.09:19:11.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:19:11.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:19:11.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:19:11.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:19:11.92$vck44/vb=8,4 2006.285.09:19:11.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.09:19:11.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.09:19:11.92#ibcon#ireg 11 cls_cnt 2 2006.285.09:19:11.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:19:11.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:19:11.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:19:11.98#ibcon#enter wrdev, iclass 10, count 2 2006.285.09:19:11.98#ibcon#first serial, iclass 10, count 2 2006.285.09:19:11.98#ibcon#enter sib2, iclass 10, count 2 2006.285.09:19:11.98#ibcon#flushed, iclass 10, count 2 2006.285.09:19:11.98#ibcon#about to write, iclass 10, count 2 2006.285.09:19:11.98#ibcon#wrote, iclass 10, count 2 2006.285.09:19:11.98#ibcon#about to read 3, iclass 10, count 2 2006.285.09:19:12.00#ibcon#read 3, iclass 10, count 2 2006.285.09:19:12.00#ibcon#about to read 4, iclass 10, count 2 2006.285.09:19:12.00#ibcon#read 4, iclass 10, count 2 2006.285.09:19:12.00#ibcon#about to read 5, iclass 10, count 2 2006.285.09:19:12.00#ibcon#read 5, iclass 10, count 2 2006.285.09:19:12.00#ibcon#about to read 6, iclass 10, count 2 2006.285.09:19:12.00#ibcon#read 6, iclass 10, count 2 2006.285.09:19:12.00#ibcon#end of sib2, iclass 10, count 2 2006.285.09:19:12.00#ibcon#*mode == 0, iclass 10, count 2 2006.285.09:19:12.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.09:19:12.00#ibcon#[27=AT08-04\r\n] 2006.285.09:19:12.00#ibcon#*before write, iclass 10, count 2 2006.285.09:19:12.00#ibcon#enter sib2, iclass 10, count 2 2006.285.09:19:12.00#ibcon#flushed, iclass 10, count 2 2006.285.09:19:12.00#ibcon#about to write, iclass 10, count 2 2006.285.09:19:12.00#ibcon#wrote, iclass 10, count 2 2006.285.09:19:12.00#ibcon#about to read 3, iclass 10, count 2 2006.285.09:19:12.03#ibcon#read 3, iclass 10, count 2 2006.285.09:19:12.03#ibcon#about to read 4, iclass 10, count 2 2006.285.09:19:12.03#ibcon#read 4, iclass 10, count 2 2006.285.09:19:12.03#ibcon#about to read 5, iclass 10, count 2 2006.285.09:19:12.03#ibcon#read 5, iclass 10, count 2 2006.285.09:19:12.03#ibcon#about to read 6, iclass 10, count 2 2006.285.09:19:12.03#ibcon#read 6, iclass 10, count 2 2006.285.09:19:12.03#ibcon#end of sib2, iclass 10, count 2 2006.285.09:19:12.03#ibcon#*after write, iclass 10, count 2 2006.285.09:19:12.03#ibcon#*before return 0, iclass 10, count 2 2006.285.09:19:12.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:19:12.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:19:12.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.09:19:12.03#ibcon#ireg 7 cls_cnt 0 2006.285.09:19:12.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:19:12.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:19:12.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:19:12.15#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:19:12.15#ibcon#first serial, iclass 10, count 0 2006.285.09:19:12.15#ibcon#enter sib2, iclass 10, count 0 2006.285.09:19:12.15#ibcon#flushed, iclass 10, count 0 2006.285.09:19:12.15#ibcon#about to write, iclass 10, count 0 2006.285.09:19:12.15#ibcon#wrote, iclass 10, count 0 2006.285.09:19:12.15#ibcon#about to read 3, iclass 10, count 0 2006.285.09:19:12.17#ibcon#read 3, iclass 10, count 0 2006.285.09:19:12.17#ibcon#about to read 4, iclass 10, count 0 2006.285.09:19:12.17#ibcon#read 4, iclass 10, count 0 2006.285.09:19:12.17#ibcon#about to read 5, iclass 10, count 0 2006.285.09:19:12.17#ibcon#read 5, iclass 10, count 0 2006.285.09:19:12.17#ibcon#about to read 6, iclass 10, count 0 2006.285.09:19:12.17#ibcon#read 6, iclass 10, count 0 2006.285.09:19:12.17#ibcon#end of sib2, iclass 10, count 0 2006.285.09:19:12.17#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:19:12.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:19:12.17#ibcon#[27=USB\r\n] 2006.285.09:19:12.17#ibcon#*before write, iclass 10, count 0 2006.285.09:19:12.17#ibcon#enter sib2, iclass 10, count 0 2006.285.09:19:12.17#ibcon#flushed, iclass 10, count 0 2006.285.09:19:12.17#ibcon#about to write, iclass 10, count 0 2006.285.09:19:12.17#ibcon#wrote, iclass 10, count 0 2006.285.09:19:12.17#ibcon#about to read 3, iclass 10, count 0 2006.285.09:19:12.20#ibcon#read 3, iclass 10, count 0 2006.285.09:19:12.20#ibcon#about to read 4, iclass 10, count 0 2006.285.09:19:12.20#ibcon#read 4, iclass 10, count 0 2006.285.09:19:12.20#ibcon#about to read 5, iclass 10, count 0 2006.285.09:19:12.20#ibcon#read 5, iclass 10, count 0 2006.285.09:19:12.20#ibcon#about to read 6, iclass 10, count 0 2006.285.09:19:12.20#ibcon#read 6, iclass 10, count 0 2006.285.09:19:12.20#ibcon#end of sib2, iclass 10, count 0 2006.285.09:19:12.20#ibcon#*after write, iclass 10, count 0 2006.285.09:19:12.20#ibcon#*before return 0, iclass 10, count 0 2006.285.09:19:12.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:19:12.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:19:12.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:19:12.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:19:12.20$vck44/vabw=wide 2006.285.09:19:12.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.09:19:12.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.09:19:12.20#ibcon#ireg 8 cls_cnt 0 2006.285.09:19:12.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:19:12.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:19:12.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:19:12.20#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:19:12.20#ibcon#first serial, iclass 12, count 0 2006.285.09:19:12.20#ibcon#enter sib2, iclass 12, count 0 2006.285.09:19:12.20#ibcon#flushed, iclass 12, count 0 2006.285.09:19:12.20#ibcon#about to write, iclass 12, count 0 2006.285.09:19:12.20#ibcon#wrote, iclass 12, count 0 2006.285.09:19:12.20#ibcon#about to read 3, iclass 12, count 0 2006.285.09:19:12.22#ibcon#read 3, iclass 12, count 0 2006.285.09:19:12.22#ibcon#about to read 4, iclass 12, count 0 2006.285.09:19:12.22#ibcon#read 4, iclass 12, count 0 2006.285.09:19:12.22#ibcon#about to read 5, iclass 12, count 0 2006.285.09:19:12.22#ibcon#read 5, iclass 12, count 0 2006.285.09:19:12.22#ibcon#about to read 6, iclass 12, count 0 2006.285.09:19:12.22#ibcon#read 6, iclass 12, count 0 2006.285.09:19:12.22#ibcon#end of sib2, iclass 12, count 0 2006.285.09:19:12.22#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:19:12.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:19:12.22#ibcon#[25=BW32\r\n] 2006.285.09:19:12.22#ibcon#*before write, iclass 12, count 0 2006.285.09:19:12.22#ibcon#enter sib2, iclass 12, count 0 2006.285.09:19:12.22#ibcon#flushed, iclass 12, count 0 2006.285.09:19:12.22#ibcon#about to write, iclass 12, count 0 2006.285.09:19:12.22#ibcon#wrote, iclass 12, count 0 2006.285.09:19:12.22#ibcon#about to read 3, iclass 12, count 0 2006.285.09:19:12.25#ibcon#read 3, iclass 12, count 0 2006.285.09:19:12.25#ibcon#about to read 4, iclass 12, count 0 2006.285.09:19:12.25#ibcon#read 4, iclass 12, count 0 2006.285.09:19:12.25#ibcon#about to read 5, iclass 12, count 0 2006.285.09:19:12.25#ibcon#read 5, iclass 12, count 0 2006.285.09:19:12.25#ibcon#about to read 6, iclass 12, count 0 2006.285.09:19:12.25#ibcon#read 6, iclass 12, count 0 2006.285.09:19:12.25#ibcon#end of sib2, iclass 12, count 0 2006.285.09:19:12.25#ibcon#*after write, iclass 12, count 0 2006.285.09:19:12.25#ibcon#*before return 0, iclass 12, count 0 2006.285.09:19:12.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:19:12.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:19:12.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:19:12.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:19:12.25$vck44/vbbw=wide 2006.285.09:19:12.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.09:19:12.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.09:19:12.25#ibcon#ireg 8 cls_cnt 0 2006.285.09:19:12.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:19:12.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:19:12.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:19:12.32#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:19:12.32#ibcon#first serial, iclass 14, count 0 2006.285.09:19:12.32#ibcon#enter sib2, iclass 14, count 0 2006.285.09:19:12.32#ibcon#flushed, iclass 14, count 0 2006.285.09:19:12.32#ibcon#about to write, iclass 14, count 0 2006.285.09:19:12.32#ibcon#wrote, iclass 14, count 0 2006.285.09:19:12.32#ibcon#about to read 3, iclass 14, count 0 2006.285.09:19:12.34#ibcon#read 3, iclass 14, count 0 2006.285.09:19:12.34#ibcon#about to read 4, iclass 14, count 0 2006.285.09:19:12.34#ibcon#read 4, iclass 14, count 0 2006.285.09:19:12.34#ibcon#about to read 5, iclass 14, count 0 2006.285.09:19:12.34#ibcon#read 5, iclass 14, count 0 2006.285.09:19:12.34#ibcon#about to read 6, iclass 14, count 0 2006.285.09:19:12.34#ibcon#read 6, iclass 14, count 0 2006.285.09:19:12.34#ibcon#end of sib2, iclass 14, count 0 2006.285.09:19:12.34#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:19:12.34#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:19:12.34#ibcon#[27=BW32\r\n] 2006.285.09:19:12.34#ibcon#*before write, iclass 14, count 0 2006.285.09:19:12.34#ibcon#enter sib2, iclass 14, count 0 2006.285.09:19:12.34#ibcon#flushed, iclass 14, count 0 2006.285.09:19:12.34#ibcon#about to write, iclass 14, count 0 2006.285.09:19:12.34#ibcon#wrote, iclass 14, count 0 2006.285.09:19:12.34#ibcon#about to read 3, iclass 14, count 0 2006.285.09:19:12.37#ibcon#read 3, iclass 14, count 0 2006.285.09:19:12.37#ibcon#about to read 4, iclass 14, count 0 2006.285.09:19:12.37#ibcon#read 4, iclass 14, count 0 2006.285.09:19:12.37#ibcon#about to read 5, iclass 14, count 0 2006.285.09:19:12.37#ibcon#read 5, iclass 14, count 0 2006.285.09:19:12.37#ibcon#about to read 6, iclass 14, count 0 2006.285.09:19:12.37#ibcon#read 6, iclass 14, count 0 2006.285.09:19:12.37#ibcon#end of sib2, iclass 14, count 0 2006.285.09:19:12.37#ibcon#*after write, iclass 14, count 0 2006.285.09:19:12.37#ibcon#*before return 0, iclass 14, count 0 2006.285.09:19:12.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:19:12.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:19:12.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:19:12.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:19:12.37$setupk4/ifdk4 2006.285.09:19:12.37$ifdk4/lo= 2006.285.09:19:12.37$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:19:12.37$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:19:12.37$ifdk4/patch= 2006.285.09:19:12.37$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:19:12.37$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:19:12.37$setupk4/!*+20s 2006.285.09:19:15.17#abcon#<5=/01 0.7 1.1 20.17 881014.9\r\n> 2006.285.09:19:15.19#abcon#{5=INTERFACE CLEAR} 2006.285.09:19:15.25#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:19:25.49#abcon#<5=/01 0.6 1.1 20.16 881014.9\r\n> 2006.285.09:19:25.51#abcon#{5=INTERFACE CLEAR} 2006.285.09:19:25.57#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:19:26.86$setupk4/"tpicd 2006.285.09:19:26.86$setupk4/echo=off 2006.285.09:19:26.86$setupk4/xlog=off 2006.285.09:19:26.86:!2006.285.09:21:42 2006.285.09:19:29.14#trakl#Source acquired 2006.285.09:19:29.14#flagr#flagr/antenna,acquired 2006.285.09:21:42.00:preob 2006.285.09:21:42.13/onsource/TRACKING 2006.285.09:21:42.13:!2006.285.09:21:52 2006.285.09:21:52.00:"tape 2006.285.09:21:52.00:"st=record 2006.285.09:21:52.00:data_valid=on 2006.285.09:21:52.00:midob 2006.285.09:21:53.13/onsource/TRACKING 2006.285.09:21:53.13/wx/20.06,1014.9,89 2006.285.09:21:53.31/cable/+6.4814E-03 2006.285.09:21:54.40/va/01,07,usb,yes,33,36 2006.285.09:21:54.40/va/02,06,usb,yes,33,34 2006.285.09:21:54.40/va/03,07,usb,yes,33,35 2006.285.09:21:54.40/va/04,06,usb,yes,34,36 2006.285.09:21:54.40/va/05,03,usb,yes,34,34 2006.285.09:21:54.40/va/06,04,usb,yes,30,30 2006.285.09:21:54.40/va/07,04,usb,yes,31,32 2006.285.09:21:54.40/va/08,03,usb,yes,32,39 2006.285.09:21:54.63/valo/01,524.99,yes,locked 2006.285.09:21:54.63/valo/02,534.99,yes,locked 2006.285.09:21:54.63/valo/03,564.99,yes,locked 2006.285.09:21:54.63/valo/04,624.99,yes,locked 2006.285.09:21:54.63/valo/05,734.99,yes,locked 2006.285.09:21:54.63/valo/06,814.99,yes,locked 2006.285.09:21:54.63/valo/07,864.99,yes,locked 2006.285.09:21:54.63/valo/08,884.99,yes,locked 2006.285.09:21:55.72/vb/01,04,usb,yes,31,29 2006.285.09:21:55.72/vb/02,05,usb,yes,29,29 2006.285.09:21:55.72/vb/03,04,usb,yes,30,33 2006.285.09:21:55.72/vb/04,05,usb,yes,30,29 2006.285.09:21:55.72/vb/05,04,usb,yes,27,29 2006.285.09:21:55.72/vb/06,03,usb,yes,39,35 2006.285.09:21:55.72/vb/07,04,usb,yes,31,31 2006.285.09:21:55.72/vb/08,04,usb,yes,28,32 2006.285.09:21:55.95/vblo/01,629.99,yes,locked 2006.285.09:21:55.95/vblo/02,634.99,yes,locked 2006.285.09:21:55.95/vblo/03,649.99,yes,locked 2006.285.09:21:55.95/vblo/04,679.99,yes,locked 2006.285.09:21:55.95/vblo/05,709.99,yes,locked 2006.285.09:21:55.95/vblo/06,719.99,yes,locked 2006.285.09:21:55.95/vblo/07,734.99,yes,locked 2006.285.09:21:55.95/vblo/08,744.99,yes,locked 2006.285.09:21:56.10/vabw/8 2006.285.09:21:56.25/vbbw/8 2006.285.09:21:56.34/xfe/off,on,12.2 2006.285.09:21:56.71/ifatt/23,28,28,28 2006.285.09:21:57.08/fmout-gps/S +2.84E-07 2006.285.09:21:57.10:!2006.285.09:25:42 2006.285.09:25:42.00:data_valid=off 2006.285.09:25:42.00:"et 2006.285.09:25:42.00:!+3s 2006.285.09:25:45.01:"tape 2006.285.09:25:45.01:postob 2006.285.09:25:45.11/cable/+6.4815E-03 2006.285.09:25:45.11/wx/19.86,1015.0,90 2006.285.09:25:46.08/fmout-gps/S +2.77E-07 2006.285.09:25:46.08:scan_name=285-0928,jd0610,40 2006.285.09:25:46.08:source=2134+00,213638.59,004154.2,2000.0,cw 2006.285.09:25:47.14#flagr#flagr/antenna,new-source 2006.285.09:25:47.14:checkk5 2006.285.09:25:47.64/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:25:48.35/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:25:48.76/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:25:49.13/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:25:49.50/chk_obsdata//k5ts1/T2850921??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.285.09:25:49.83/chk_obsdata//k5ts2/T2850921??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.285.09:25:50.21/chk_obsdata//k5ts3/T2850921??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.285.09:25:50.82/chk_obsdata//k5ts4/T2850921??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.285.09:25:51.73/k5log//k5ts1_log_newline 2006.285.09:25:52.48/k5log//k5ts2_log_newline 2006.285.09:25:53.32/k5log//k5ts3_log_newline 2006.285.09:25:54.09/k5log//k5ts4_log_newline 2006.285.09:25:54.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:25:54.11:setupk4=1 2006.285.09:25:54.11$setupk4/echo=on 2006.285.09:25:54.11$setupk4/pcalon 2006.285.09:25:54.11$pcalon/"no phase cal control is implemented here 2006.285.09:25:54.11$setupk4/"tpicd=stop 2006.285.09:25:54.11$setupk4/"rec=synch_on 2006.285.09:25:54.11$setupk4/"rec_mode=128 2006.285.09:25:54.11$setupk4/!* 2006.285.09:25:54.12$setupk4/recpk4 2006.285.09:25:54.12$recpk4/recpatch= 2006.285.09:25:54.12$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:25:54.12$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:25:54.12$setupk4/vck44 2006.285.09:25:54.12$vck44/valo=1,524.99 2006.285.09:25:54.12#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.09:25:54.12#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.09:25:54.12#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:54.12#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:25:54.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:25:54.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:25:54.12#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:25:54.12#ibcon#first serial, iclass 35, count 0 2006.285.09:25:54.12#ibcon#enter sib2, iclass 35, count 0 2006.285.09:25:54.12#ibcon#flushed, iclass 35, count 0 2006.285.09:25:54.12#ibcon#about to write, iclass 35, count 0 2006.285.09:25:54.12#ibcon#wrote, iclass 35, count 0 2006.285.09:25:54.12#ibcon#about to read 3, iclass 35, count 0 2006.285.09:25:54.14#ibcon#read 3, iclass 35, count 0 2006.285.09:25:54.14#ibcon#about to read 4, iclass 35, count 0 2006.285.09:25:54.14#ibcon#read 4, iclass 35, count 0 2006.285.09:25:54.14#ibcon#about to read 5, iclass 35, count 0 2006.285.09:25:54.14#ibcon#read 5, iclass 35, count 0 2006.285.09:25:54.14#ibcon#about to read 6, iclass 35, count 0 2006.285.09:25:54.14#ibcon#read 6, iclass 35, count 0 2006.285.09:25:54.14#ibcon#end of sib2, iclass 35, count 0 2006.285.09:25:54.14#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:25:54.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:25:54.14#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:25:54.14#ibcon#*before write, iclass 35, count 0 2006.285.09:25:54.14#ibcon#enter sib2, iclass 35, count 0 2006.285.09:25:54.14#ibcon#flushed, iclass 35, count 0 2006.285.09:25:54.14#ibcon#about to write, iclass 35, count 0 2006.285.09:25:54.14#ibcon#wrote, iclass 35, count 0 2006.285.09:25:54.14#ibcon#about to read 3, iclass 35, count 0 2006.285.09:25:54.19#ibcon#read 3, iclass 35, count 0 2006.285.09:25:54.19#ibcon#about to read 4, iclass 35, count 0 2006.285.09:25:54.19#ibcon#read 4, iclass 35, count 0 2006.285.09:25:54.19#ibcon#about to read 5, iclass 35, count 0 2006.285.09:25:54.19#ibcon#read 5, iclass 35, count 0 2006.285.09:25:54.19#ibcon#about to read 6, iclass 35, count 0 2006.285.09:25:54.19#ibcon#read 6, iclass 35, count 0 2006.285.09:25:54.19#ibcon#end of sib2, iclass 35, count 0 2006.285.09:25:54.19#ibcon#*after write, iclass 35, count 0 2006.285.09:25:54.19#ibcon#*before return 0, iclass 35, count 0 2006.285.09:25:54.19#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:25:54.19#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:25:54.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:25:54.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:25:54.19$vck44/va=1,7 2006.285.09:25:54.19#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.09:25:54.19#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.09:25:54.19#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:54.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:25:54.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:25:54.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:25:54.19#ibcon#enter wrdev, iclass 37, count 2 2006.285.09:25:54.19#ibcon#first serial, iclass 37, count 2 2006.285.09:25:54.19#ibcon#enter sib2, iclass 37, count 2 2006.285.09:25:54.19#ibcon#flushed, iclass 37, count 2 2006.285.09:25:54.19#ibcon#about to write, iclass 37, count 2 2006.285.09:25:54.19#ibcon#wrote, iclass 37, count 2 2006.285.09:25:54.19#ibcon#about to read 3, iclass 37, count 2 2006.285.09:25:54.21#ibcon#read 3, iclass 37, count 2 2006.285.09:25:54.21#ibcon#about to read 4, iclass 37, count 2 2006.285.09:25:54.21#ibcon#read 4, iclass 37, count 2 2006.285.09:25:54.21#ibcon#about to read 5, iclass 37, count 2 2006.285.09:25:54.21#ibcon#read 5, iclass 37, count 2 2006.285.09:25:54.21#ibcon#about to read 6, iclass 37, count 2 2006.285.09:25:54.21#ibcon#read 6, iclass 37, count 2 2006.285.09:25:54.21#ibcon#end of sib2, iclass 37, count 2 2006.285.09:25:54.21#ibcon#*mode == 0, iclass 37, count 2 2006.285.09:25:54.21#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.09:25:54.21#ibcon#[25=AT01-07\r\n] 2006.285.09:25:54.21#ibcon#*before write, iclass 37, count 2 2006.285.09:25:54.21#ibcon#enter sib2, iclass 37, count 2 2006.285.09:25:54.21#ibcon#flushed, iclass 37, count 2 2006.285.09:25:54.21#ibcon#about to write, iclass 37, count 2 2006.285.09:25:54.21#ibcon#wrote, iclass 37, count 2 2006.285.09:25:54.21#ibcon#about to read 3, iclass 37, count 2 2006.285.09:25:54.24#ibcon#read 3, iclass 37, count 2 2006.285.09:25:54.24#ibcon#about to read 4, iclass 37, count 2 2006.285.09:25:54.24#ibcon#read 4, iclass 37, count 2 2006.285.09:25:54.24#ibcon#about to read 5, iclass 37, count 2 2006.285.09:25:54.24#ibcon#read 5, iclass 37, count 2 2006.285.09:25:54.24#ibcon#about to read 6, iclass 37, count 2 2006.285.09:25:54.24#ibcon#read 6, iclass 37, count 2 2006.285.09:25:54.24#ibcon#end of sib2, iclass 37, count 2 2006.285.09:25:54.24#ibcon#*after write, iclass 37, count 2 2006.285.09:25:54.24#ibcon#*before return 0, iclass 37, count 2 2006.285.09:25:54.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:25:54.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:25:54.24#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.09:25:54.24#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:54.24#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:25:54.36#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:25:54.36#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:25:54.36#ibcon#enter wrdev, iclass 37, count 0 2006.285.09:25:54.36#ibcon#first serial, iclass 37, count 0 2006.285.09:25:54.36#ibcon#enter sib2, iclass 37, count 0 2006.285.09:25:54.36#ibcon#flushed, iclass 37, count 0 2006.285.09:25:54.36#ibcon#about to write, iclass 37, count 0 2006.285.09:25:54.36#ibcon#wrote, iclass 37, count 0 2006.285.09:25:54.36#ibcon#about to read 3, iclass 37, count 0 2006.285.09:25:54.38#ibcon#read 3, iclass 37, count 0 2006.285.09:25:54.38#ibcon#about to read 4, iclass 37, count 0 2006.285.09:25:54.38#ibcon#read 4, iclass 37, count 0 2006.285.09:25:54.38#ibcon#about to read 5, iclass 37, count 0 2006.285.09:25:54.38#ibcon#read 5, iclass 37, count 0 2006.285.09:25:54.38#ibcon#about to read 6, iclass 37, count 0 2006.285.09:25:54.38#ibcon#read 6, iclass 37, count 0 2006.285.09:25:54.38#ibcon#end of sib2, iclass 37, count 0 2006.285.09:25:54.38#ibcon#*mode == 0, iclass 37, count 0 2006.285.09:25:54.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.09:25:54.38#ibcon#[25=USB\r\n] 2006.285.09:25:54.38#ibcon#*before write, iclass 37, count 0 2006.285.09:25:54.38#ibcon#enter sib2, iclass 37, count 0 2006.285.09:25:54.38#ibcon#flushed, iclass 37, count 0 2006.285.09:25:54.38#ibcon#about to write, iclass 37, count 0 2006.285.09:25:54.38#ibcon#wrote, iclass 37, count 0 2006.285.09:25:54.38#ibcon#about to read 3, iclass 37, count 0 2006.285.09:25:54.41#ibcon#read 3, iclass 37, count 0 2006.285.09:25:54.41#ibcon#about to read 4, iclass 37, count 0 2006.285.09:25:54.41#ibcon#read 4, iclass 37, count 0 2006.285.09:25:54.41#ibcon#about to read 5, iclass 37, count 0 2006.285.09:25:54.41#ibcon#read 5, iclass 37, count 0 2006.285.09:25:54.41#ibcon#about to read 6, iclass 37, count 0 2006.285.09:25:54.41#ibcon#read 6, iclass 37, count 0 2006.285.09:25:54.41#ibcon#end of sib2, iclass 37, count 0 2006.285.09:25:54.41#ibcon#*after write, iclass 37, count 0 2006.285.09:25:54.41#ibcon#*before return 0, iclass 37, count 0 2006.285.09:25:54.41#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:25:54.41#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:25:54.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.09:25:54.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.09:25:54.41$vck44/valo=2,534.99 2006.285.09:25:54.41#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.09:25:54.41#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.09:25:54.41#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:54.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:25:54.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:25:54.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:25:54.41#ibcon#enter wrdev, iclass 39, count 0 2006.285.09:25:54.41#ibcon#first serial, iclass 39, count 0 2006.285.09:25:54.41#ibcon#enter sib2, iclass 39, count 0 2006.285.09:25:54.41#ibcon#flushed, iclass 39, count 0 2006.285.09:25:54.41#ibcon#about to write, iclass 39, count 0 2006.285.09:25:54.41#ibcon#wrote, iclass 39, count 0 2006.285.09:25:54.41#ibcon#about to read 3, iclass 39, count 0 2006.285.09:25:54.43#ibcon#read 3, iclass 39, count 0 2006.285.09:25:54.43#ibcon#about to read 4, iclass 39, count 0 2006.285.09:25:54.43#ibcon#read 4, iclass 39, count 0 2006.285.09:25:54.43#ibcon#about to read 5, iclass 39, count 0 2006.285.09:25:54.43#ibcon#read 5, iclass 39, count 0 2006.285.09:25:54.43#ibcon#about to read 6, iclass 39, count 0 2006.285.09:25:54.43#ibcon#read 6, iclass 39, count 0 2006.285.09:25:54.43#ibcon#end of sib2, iclass 39, count 0 2006.285.09:25:54.43#ibcon#*mode == 0, iclass 39, count 0 2006.285.09:25:54.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.09:25:54.43#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:25:54.43#ibcon#*before write, iclass 39, count 0 2006.285.09:25:54.43#ibcon#enter sib2, iclass 39, count 0 2006.285.09:25:54.43#ibcon#flushed, iclass 39, count 0 2006.285.09:25:54.43#ibcon#about to write, iclass 39, count 0 2006.285.09:25:54.43#ibcon#wrote, iclass 39, count 0 2006.285.09:25:54.43#ibcon#about to read 3, iclass 39, count 0 2006.285.09:25:54.47#ibcon#read 3, iclass 39, count 0 2006.285.09:25:54.47#ibcon#about to read 4, iclass 39, count 0 2006.285.09:25:54.47#ibcon#read 4, iclass 39, count 0 2006.285.09:25:54.47#ibcon#about to read 5, iclass 39, count 0 2006.285.09:25:54.47#ibcon#read 5, iclass 39, count 0 2006.285.09:25:54.47#ibcon#about to read 6, iclass 39, count 0 2006.285.09:25:54.47#ibcon#read 6, iclass 39, count 0 2006.285.09:25:54.47#ibcon#end of sib2, iclass 39, count 0 2006.285.09:25:54.47#ibcon#*after write, iclass 39, count 0 2006.285.09:25:54.47#ibcon#*before return 0, iclass 39, count 0 2006.285.09:25:54.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:25:54.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:25:54.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.09:25:54.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.09:25:54.47$vck44/va=2,6 2006.285.09:25:54.47#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.09:25:54.47#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.09:25:54.47#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:54.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:25:54.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:25:54.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:25:54.53#ibcon#enter wrdev, iclass 3, count 2 2006.285.09:25:54.53#ibcon#first serial, iclass 3, count 2 2006.285.09:25:54.53#ibcon#enter sib2, iclass 3, count 2 2006.285.09:25:54.53#ibcon#flushed, iclass 3, count 2 2006.285.09:25:54.53#ibcon#about to write, iclass 3, count 2 2006.285.09:25:54.53#ibcon#wrote, iclass 3, count 2 2006.285.09:25:54.53#ibcon#about to read 3, iclass 3, count 2 2006.285.09:25:54.55#ibcon#read 3, iclass 3, count 2 2006.285.09:25:54.55#ibcon#about to read 4, iclass 3, count 2 2006.285.09:25:54.55#ibcon#read 4, iclass 3, count 2 2006.285.09:25:54.55#ibcon#about to read 5, iclass 3, count 2 2006.285.09:25:54.55#ibcon#read 5, iclass 3, count 2 2006.285.09:25:54.55#ibcon#about to read 6, iclass 3, count 2 2006.285.09:25:54.55#ibcon#read 6, iclass 3, count 2 2006.285.09:25:54.55#ibcon#end of sib2, iclass 3, count 2 2006.285.09:25:54.55#ibcon#*mode == 0, iclass 3, count 2 2006.285.09:25:54.55#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.09:25:54.55#ibcon#[25=AT02-06\r\n] 2006.285.09:25:54.55#ibcon#*before write, iclass 3, count 2 2006.285.09:25:54.55#ibcon#enter sib2, iclass 3, count 2 2006.285.09:25:54.55#ibcon#flushed, iclass 3, count 2 2006.285.09:25:54.55#ibcon#about to write, iclass 3, count 2 2006.285.09:25:54.55#ibcon#wrote, iclass 3, count 2 2006.285.09:25:54.55#ibcon#about to read 3, iclass 3, count 2 2006.285.09:25:54.58#ibcon#read 3, iclass 3, count 2 2006.285.09:25:54.58#ibcon#about to read 4, iclass 3, count 2 2006.285.09:25:54.58#ibcon#read 4, iclass 3, count 2 2006.285.09:25:54.58#ibcon#about to read 5, iclass 3, count 2 2006.285.09:25:54.58#ibcon#read 5, iclass 3, count 2 2006.285.09:25:54.58#ibcon#about to read 6, iclass 3, count 2 2006.285.09:25:54.58#ibcon#read 6, iclass 3, count 2 2006.285.09:25:54.58#ibcon#end of sib2, iclass 3, count 2 2006.285.09:25:54.58#ibcon#*after write, iclass 3, count 2 2006.285.09:25:54.58#ibcon#*before return 0, iclass 3, count 2 2006.285.09:25:54.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:25:54.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:25:54.58#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.09:25:54.58#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:54.58#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:25:54.70#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:25:54.70#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:25:54.70#ibcon#enter wrdev, iclass 3, count 0 2006.285.09:25:54.70#ibcon#first serial, iclass 3, count 0 2006.285.09:25:54.70#ibcon#enter sib2, iclass 3, count 0 2006.285.09:25:54.70#ibcon#flushed, iclass 3, count 0 2006.285.09:25:54.70#ibcon#about to write, iclass 3, count 0 2006.285.09:25:54.70#ibcon#wrote, iclass 3, count 0 2006.285.09:25:54.70#ibcon#about to read 3, iclass 3, count 0 2006.285.09:25:54.72#ibcon#read 3, iclass 3, count 0 2006.285.09:25:54.72#ibcon#about to read 4, iclass 3, count 0 2006.285.09:25:54.72#ibcon#read 4, iclass 3, count 0 2006.285.09:25:54.72#ibcon#about to read 5, iclass 3, count 0 2006.285.09:25:54.72#ibcon#read 5, iclass 3, count 0 2006.285.09:25:54.72#ibcon#about to read 6, iclass 3, count 0 2006.285.09:25:54.72#ibcon#read 6, iclass 3, count 0 2006.285.09:25:54.72#ibcon#end of sib2, iclass 3, count 0 2006.285.09:25:54.72#ibcon#*mode == 0, iclass 3, count 0 2006.285.09:25:54.72#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.09:25:54.72#ibcon#[25=USB\r\n] 2006.285.09:25:54.72#ibcon#*before write, iclass 3, count 0 2006.285.09:25:54.72#ibcon#enter sib2, iclass 3, count 0 2006.285.09:25:54.72#ibcon#flushed, iclass 3, count 0 2006.285.09:25:54.72#ibcon#about to write, iclass 3, count 0 2006.285.09:25:54.72#ibcon#wrote, iclass 3, count 0 2006.285.09:25:54.72#ibcon#about to read 3, iclass 3, count 0 2006.285.09:25:54.75#ibcon#read 3, iclass 3, count 0 2006.285.09:25:54.75#ibcon#about to read 4, iclass 3, count 0 2006.285.09:25:54.75#ibcon#read 4, iclass 3, count 0 2006.285.09:25:54.75#ibcon#about to read 5, iclass 3, count 0 2006.285.09:25:54.75#ibcon#read 5, iclass 3, count 0 2006.285.09:25:54.75#ibcon#about to read 6, iclass 3, count 0 2006.285.09:25:54.75#ibcon#read 6, iclass 3, count 0 2006.285.09:25:54.75#ibcon#end of sib2, iclass 3, count 0 2006.285.09:25:54.75#ibcon#*after write, iclass 3, count 0 2006.285.09:25:54.75#ibcon#*before return 0, iclass 3, count 0 2006.285.09:25:54.75#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:25:54.75#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:25:54.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.09:25:54.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.09:25:54.75$vck44/valo=3,564.99 2006.285.09:25:54.75#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.09:25:54.75#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.09:25:54.75#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:54.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:25:54.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:25:54.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:25:54.75#ibcon#enter wrdev, iclass 5, count 0 2006.285.09:25:54.75#ibcon#first serial, iclass 5, count 0 2006.285.09:25:54.75#ibcon#enter sib2, iclass 5, count 0 2006.285.09:25:54.75#ibcon#flushed, iclass 5, count 0 2006.285.09:25:54.75#ibcon#about to write, iclass 5, count 0 2006.285.09:25:54.75#ibcon#wrote, iclass 5, count 0 2006.285.09:25:54.75#ibcon#about to read 3, iclass 5, count 0 2006.285.09:25:54.77#ibcon#read 3, iclass 5, count 0 2006.285.09:25:54.77#ibcon#about to read 4, iclass 5, count 0 2006.285.09:25:54.77#ibcon#read 4, iclass 5, count 0 2006.285.09:25:54.77#ibcon#about to read 5, iclass 5, count 0 2006.285.09:25:54.77#ibcon#read 5, iclass 5, count 0 2006.285.09:25:54.77#ibcon#about to read 6, iclass 5, count 0 2006.285.09:25:54.77#ibcon#read 6, iclass 5, count 0 2006.285.09:25:54.77#ibcon#end of sib2, iclass 5, count 0 2006.285.09:25:54.77#ibcon#*mode == 0, iclass 5, count 0 2006.285.09:25:54.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.09:25:54.77#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:25:54.77#ibcon#*before write, iclass 5, count 0 2006.285.09:25:54.77#ibcon#enter sib2, iclass 5, count 0 2006.285.09:25:54.77#ibcon#flushed, iclass 5, count 0 2006.285.09:25:54.77#ibcon#about to write, iclass 5, count 0 2006.285.09:25:54.77#ibcon#wrote, iclass 5, count 0 2006.285.09:25:54.77#ibcon#about to read 3, iclass 5, count 0 2006.285.09:25:54.81#ibcon#read 3, iclass 5, count 0 2006.285.09:25:54.81#ibcon#about to read 4, iclass 5, count 0 2006.285.09:25:54.81#ibcon#read 4, iclass 5, count 0 2006.285.09:25:54.81#ibcon#about to read 5, iclass 5, count 0 2006.285.09:25:54.81#ibcon#read 5, iclass 5, count 0 2006.285.09:25:54.81#ibcon#about to read 6, iclass 5, count 0 2006.285.09:25:54.81#ibcon#read 6, iclass 5, count 0 2006.285.09:25:54.81#ibcon#end of sib2, iclass 5, count 0 2006.285.09:25:54.81#ibcon#*after write, iclass 5, count 0 2006.285.09:25:54.81#ibcon#*before return 0, iclass 5, count 0 2006.285.09:25:54.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:25:54.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:25:54.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.09:25:54.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.09:25:54.81$vck44/va=3,7 2006.285.09:25:54.81#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.09:25:54.81#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.09:25:54.81#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:54.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:25:54.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:25:54.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:25:54.87#ibcon#enter wrdev, iclass 7, count 2 2006.285.09:25:54.87#ibcon#first serial, iclass 7, count 2 2006.285.09:25:54.87#ibcon#enter sib2, iclass 7, count 2 2006.285.09:25:54.87#ibcon#flushed, iclass 7, count 2 2006.285.09:25:54.87#ibcon#about to write, iclass 7, count 2 2006.285.09:25:54.87#ibcon#wrote, iclass 7, count 2 2006.285.09:25:54.87#ibcon#about to read 3, iclass 7, count 2 2006.285.09:25:54.89#ibcon#read 3, iclass 7, count 2 2006.285.09:25:54.89#ibcon#about to read 4, iclass 7, count 2 2006.285.09:25:54.89#ibcon#read 4, iclass 7, count 2 2006.285.09:25:54.89#ibcon#about to read 5, iclass 7, count 2 2006.285.09:25:54.89#ibcon#read 5, iclass 7, count 2 2006.285.09:25:54.89#ibcon#about to read 6, iclass 7, count 2 2006.285.09:25:54.89#ibcon#read 6, iclass 7, count 2 2006.285.09:25:54.89#ibcon#end of sib2, iclass 7, count 2 2006.285.09:25:54.89#ibcon#*mode == 0, iclass 7, count 2 2006.285.09:25:54.89#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.09:25:54.89#ibcon#[25=AT03-07\r\n] 2006.285.09:25:54.89#ibcon#*before write, iclass 7, count 2 2006.285.09:25:54.89#ibcon#enter sib2, iclass 7, count 2 2006.285.09:25:54.89#ibcon#flushed, iclass 7, count 2 2006.285.09:25:54.89#ibcon#about to write, iclass 7, count 2 2006.285.09:25:54.89#ibcon#wrote, iclass 7, count 2 2006.285.09:25:54.89#ibcon#about to read 3, iclass 7, count 2 2006.285.09:25:54.92#ibcon#read 3, iclass 7, count 2 2006.285.09:25:54.92#ibcon#about to read 4, iclass 7, count 2 2006.285.09:25:54.92#ibcon#read 4, iclass 7, count 2 2006.285.09:25:54.92#ibcon#about to read 5, iclass 7, count 2 2006.285.09:25:54.92#ibcon#read 5, iclass 7, count 2 2006.285.09:25:54.92#ibcon#about to read 6, iclass 7, count 2 2006.285.09:25:54.92#ibcon#read 6, iclass 7, count 2 2006.285.09:25:54.92#ibcon#end of sib2, iclass 7, count 2 2006.285.09:25:54.92#ibcon#*after write, iclass 7, count 2 2006.285.09:25:54.92#ibcon#*before return 0, iclass 7, count 2 2006.285.09:25:54.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:25:54.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:25:54.92#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.09:25:54.92#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:54.92#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:25:55.04#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:25:55.04#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:25:55.04#ibcon#enter wrdev, iclass 7, count 0 2006.285.09:25:55.04#ibcon#first serial, iclass 7, count 0 2006.285.09:25:55.04#ibcon#enter sib2, iclass 7, count 0 2006.285.09:25:55.04#ibcon#flushed, iclass 7, count 0 2006.285.09:25:55.04#ibcon#about to write, iclass 7, count 0 2006.285.09:25:55.04#ibcon#wrote, iclass 7, count 0 2006.285.09:25:55.04#ibcon#about to read 3, iclass 7, count 0 2006.285.09:25:55.06#ibcon#read 3, iclass 7, count 0 2006.285.09:25:55.06#ibcon#about to read 4, iclass 7, count 0 2006.285.09:25:55.06#ibcon#read 4, iclass 7, count 0 2006.285.09:25:55.06#ibcon#about to read 5, iclass 7, count 0 2006.285.09:25:55.06#ibcon#read 5, iclass 7, count 0 2006.285.09:25:55.06#ibcon#about to read 6, iclass 7, count 0 2006.285.09:25:55.06#ibcon#read 6, iclass 7, count 0 2006.285.09:25:55.06#ibcon#end of sib2, iclass 7, count 0 2006.285.09:25:55.06#ibcon#*mode == 0, iclass 7, count 0 2006.285.09:25:55.06#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.09:25:55.06#ibcon#[25=USB\r\n] 2006.285.09:25:55.06#ibcon#*before write, iclass 7, count 0 2006.285.09:25:55.06#ibcon#enter sib2, iclass 7, count 0 2006.285.09:25:55.06#ibcon#flushed, iclass 7, count 0 2006.285.09:25:55.06#ibcon#about to write, iclass 7, count 0 2006.285.09:25:55.06#ibcon#wrote, iclass 7, count 0 2006.285.09:25:55.06#ibcon#about to read 3, iclass 7, count 0 2006.285.09:25:55.09#ibcon#read 3, iclass 7, count 0 2006.285.09:25:55.09#ibcon#about to read 4, iclass 7, count 0 2006.285.09:25:55.09#ibcon#read 4, iclass 7, count 0 2006.285.09:25:55.09#ibcon#about to read 5, iclass 7, count 0 2006.285.09:25:55.09#ibcon#read 5, iclass 7, count 0 2006.285.09:25:55.09#ibcon#about to read 6, iclass 7, count 0 2006.285.09:25:55.09#ibcon#read 6, iclass 7, count 0 2006.285.09:25:55.09#ibcon#end of sib2, iclass 7, count 0 2006.285.09:25:55.09#ibcon#*after write, iclass 7, count 0 2006.285.09:25:55.09#ibcon#*before return 0, iclass 7, count 0 2006.285.09:25:55.09#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:25:55.09#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:25:55.09#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.09:25:55.09#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.09:25:55.09$vck44/valo=4,624.99 2006.285.09:25:55.09#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.09:25:55.09#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.09:25:55.09#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:55.09#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:25:55.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:25:55.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:25:55.09#ibcon#enter wrdev, iclass 11, count 0 2006.285.09:25:55.09#ibcon#first serial, iclass 11, count 0 2006.285.09:25:55.09#ibcon#enter sib2, iclass 11, count 0 2006.285.09:25:55.09#ibcon#flushed, iclass 11, count 0 2006.285.09:25:55.09#ibcon#about to write, iclass 11, count 0 2006.285.09:25:55.09#ibcon#wrote, iclass 11, count 0 2006.285.09:25:55.09#ibcon#about to read 3, iclass 11, count 0 2006.285.09:25:55.11#ibcon#read 3, iclass 11, count 0 2006.285.09:25:55.11#ibcon#about to read 4, iclass 11, count 0 2006.285.09:25:55.11#ibcon#read 4, iclass 11, count 0 2006.285.09:25:55.11#ibcon#about to read 5, iclass 11, count 0 2006.285.09:25:55.11#ibcon#read 5, iclass 11, count 0 2006.285.09:25:55.11#ibcon#about to read 6, iclass 11, count 0 2006.285.09:25:55.11#ibcon#read 6, iclass 11, count 0 2006.285.09:25:55.11#ibcon#end of sib2, iclass 11, count 0 2006.285.09:25:55.11#ibcon#*mode == 0, iclass 11, count 0 2006.285.09:25:55.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.09:25:55.11#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:25:55.11#ibcon#*before write, iclass 11, count 0 2006.285.09:25:55.11#ibcon#enter sib2, iclass 11, count 0 2006.285.09:25:55.11#ibcon#flushed, iclass 11, count 0 2006.285.09:25:55.11#ibcon#about to write, iclass 11, count 0 2006.285.09:25:55.11#ibcon#wrote, iclass 11, count 0 2006.285.09:25:55.11#ibcon#about to read 3, iclass 11, count 0 2006.285.09:25:55.15#ibcon#read 3, iclass 11, count 0 2006.285.09:25:55.15#ibcon#about to read 4, iclass 11, count 0 2006.285.09:25:55.15#ibcon#read 4, iclass 11, count 0 2006.285.09:25:55.15#ibcon#about to read 5, iclass 11, count 0 2006.285.09:25:55.15#ibcon#read 5, iclass 11, count 0 2006.285.09:25:55.15#ibcon#about to read 6, iclass 11, count 0 2006.285.09:25:55.15#ibcon#read 6, iclass 11, count 0 2006.285.09:25:55.15#ibcon#end of sib2, iclass 11, count 0 2006.285.09:25:55.15#ibcon#*after write, iclass 11, count 0 2006.285.09:25:55.15#ibcon#*before return 0, iclass 11, count 0 2006.285.09:25:55.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:25:55.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:25:55.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.09:25:55.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.09:25:55.15$vck44/va=4,6 2006.285.09:25:55.15#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.09:25:55.15#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.09:25:55.15#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:55.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:25:55.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:25:55.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:25:55.21#ibcon#enter wrdev, iclass 13, count 2 2006.285.09:25:55.21#ibcon#first serial, iclass 13, count 2 2006.285.09:25:55.21#ibcon#enter sib2, iclass 13, count 2 2006.285.09:25:55.21#ibcon#flushed, iclass 13, count 2 2006.285.09:25:55.21#ibcon#about to write, iclass 13, count 2 2006.285.09:25:55.21#ibcon#wrote, iclass 13, count 2 2006.285.09:25:55.21#ibcon#about to read 3, iclass 13, count 2 2006.285.09:25:55.23#ibcon#read 3, iclass 13, count 2 2006.285.09:25:55.23#ibcon#about to read 4, iclass 13, count 2 2006.285.09:25:55.23#ibcon#read 4, iclass 13, count 2 2006.285.09:25:55.23#ibcon#about to read 5, iclass 13, count 2 2006.285.09:25:55.23#ibcon#read 5, iclass 13, count 2 2006.285.09:25:55.23#ibcon#about to read 6, iclass 13, count 2 2006.285.09:25:55.23#ibcon#read 6, iclass 13, count 2 2006.285.09:25:55.23#ibcon#end of sib2, iclass 13, count 2 2006.285.09:25:55.23#ibcon#*mode == 0, iclass 13, count 2 2006.285.09:25:55.23#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.09:25:55.23#ibcon#[25=AT04-06\r\n] 2006.285.09:25:55.23#ibcon#*before write, iclass 13, count 2 2006.285.09:25:55.23#ibcon#enter sib2, iclass 13, count 2 2006.285.09:25:55.23#ibcon#flushed, iclass 13, count 2 2006.285.09:25:55.23#ibcon#about to write, iclass 13, count 2 2006.285.09:25:55.23#ibcon#wrote, iclass 13, count 2 2006.285.09:25:55.23#ibcon#about to read 3, iclass 13, count 2 2006.285.09:25:55.26#ibcon#read 3, iclass 13, count 2 2006.285.09:25:55.26#ibcon#about to read 4, iclass 13, count 2 2006.285.09:25:55.26#ibcon#read 4, iclass 13, count 2 2006.285.09:25:55.26#ibcon#about to read 5, iclass 13, count 2 2006.285.09:25:55.26#ibcon#read 5, iclass 13, count 2 2006.285.09:25:55.26#ibcon#about to read 6, iclass 13, count 2 2006.285.09:25:55.26#ibcon#read 6, iclass 13, count 2 2006.285.09:25:55.26#ibcon#end of sib2, iclass 13, count 2 2006.285.09:25:55.26#ibcon#*after write, iclass 13, count 2 2006.285.09:25:55.26#ibcon#*before return 0, iclass 13, count 2 2006.285.09:25:55.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:25:55.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:25:55.26#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.09:25:55.26#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:55.26#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:25:55.38#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:25:55.38#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:25:55.38#ibcon#enter wrdev, iclass 13, count 0 2006.285.09:25:55.38#ibcon#first serial, iclass 13, count 0 2006.285.09:25:55.38#ibcon#enter sib2, iclass 13, count 0 2006.285.09:25:55.38#ibcon#flushed, iclass 13, count 0 2006.285.09:25:55.38#ibcon#about to write, iclass 13, count 0 2006.285.09:25:55.38#ibcon#wrote, iclass 13, count 0 2006.285.09:25:55.38#ibcon#about to read 3, iclass 13, count 0 2006.285.09:25:55.40#ibcon#read 3, iclass 13, count 0 2006.285.09:25:55.40#ibcon#about to read 4, iclass 13, count 0 2006.285.09:25:55.40#ibcon#read 4, iclass 13, count 0 2006.285.09:25:55.40#ibcon#about to read 5, iclass 13, count 0 2006.285.09:25:55.40#ibcon#read 5, iclass 13, count 0 2006.285.09:25:55.40#ibcon#about to read 6, iclass 13, count 0 2006.285.09:25:55.40#ibcon#read 6, iclass 13, count 0 2006.285.09:25:55.40#ibcon#end of sib2, iclass 13, count 0 2006.285.09:25:55.40#ibcon#*mode == 0, iclass 13, count 0 2006.285.09:25:55.40#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.09:25:55.40#ibcon#[25=USB\r\n] 2006.285.09:25:55.40#ibcon#*before write, iclass 13, count 0 2006.285.09:25:55.40#ibcon#enter sib2, iclass 13, count 0 2006.285.09:25:55.40#ibcon#flushed, iclass 13, count 0 2006.285.09:25:55.40#ibcon#about to write, iclass 13, count 0 2006.285.09:25:55.40#ibcon#wrote, iclass 13, count 0 2006.285.09:25:55.40#ibcon#about to read 3, iclass 13, count 0 2006.285.09:25:55.43#ibcon#read 3, iclass 13, count 0 2006.285.09:25:55.43#ibcon#about to read 4, iclass 13, count 0 2006.285.09:25:55.43#ibcon#read 4, iclass 13, count 0 2006.285.09:25:55.43#ibcon#about to read 5, iclass 13, count 0 2006.285.09:25:55.43#ibcon#read 5, iclass 13, count 0 2006.285.09:25:55.43#ibcon#about to read 6, iclass 13, count 0 2006.285.09:25:55.43#ibcon#read 6, iclass 13, count 0 2006.285.09:25:55.43#ibcon#end of sib2, iclass 13, count 0 2006.285.09:25:55.43#ibcon#*after write, iclass 13, count 0 2006.285.09:25:55.43#ibcon#*before return 0, iclass 13, count 0 2006.285.09:25:55.43#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:25:55.43#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:25:55.43#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.09:25:55.43#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.09:25:55.43$vck44/valo=5,734.99 2006.285.09:25:55.43#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.09:25:55.43#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.09:25:55.43#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:55.43#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:25:55.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:25:55.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:25:55.43#ibcon#enter wrdev, iclass 15, count 0 2006.285.09:25:55.43#ibcon#first serial, iclass 15, count 0 2006.285.09:25:55.43#ibcon#enter sib2, iclass 15, count 0 2006.285.09:25:55.43#ibcon#flushed, iclass 15, count 0 2006.285.09:25:55.43#ibcon#about to write, iclass 15, count 0 2006.285.09:25:55.43#ibcon#wrote, iclass 15, count 0 2006.285.09:25:55.43#ibcon#about to read 3, iclass 15, count 0 2006.285.09:25:55.45#ibcon#read 3, iclass 15, count 0 2006.285.09:25:55.45#ibcon#about to read 4, iclass 15, count 0 2006.285.09:25:55.45#ibcon#read 4, iclass 15, count 0 2006.285.09:25:55.45#ibcon#about to read 5, iclass 15, count 0 2006.285.09:25:55.45#ibcon#read 5, iclass 15, count 0 2006.285.09:25:55.45#ibcon#about to read 6, iclass 15, count 0 2006.285.09:25:55.45#ibcon#read 6, iclass 15, count 0 2006.285.09:25:55.45#ibcon#end of sib2, iclass 15, count 0 2006.285.09:25:55.45#ibcon#*mode == 0, iclass 15, count 0 2006.285.09:25:55.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.09:25:55.45#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:25:55.45#ibcon#*before write, iclass 15, count 0 2006.285.09:25:55.45#ibcon#enter sib2, iclass 15, count 0 2006.285.09:25:55.45#ibcon#flushed, iclass 15, count 0 2006.285.09:25:55.45#ibcon#about to write, iclass 15, count 0 2006.285.09:25:55.45#ibcon#wrote, iclass 15, count 0 2006.285.09:25:55.45#ibcon#about to read 3, iclass 15, count 0 2006.285.09:25:55.49#ibcon#read 3, iclass 15, count 0 2006.285.09:25:55.49#ibcon#about to read 4, iclass 15, count 0 2006.285.09:25:55.49#ibcon#read 4, iclass 15, count 0 2006.285.09:25:55.49#ibcon#about to read 5, iclass 15, count 0 2006.285.09:25:55.49#ibcon#read 5, iclass 15, count 0 2006.285.09:25:55.49#ibcon#about to read 6, iclass 15, count 0 2006.285.09:25:55.49#ibcon#read 6, iclass 15, count 0 2006.285.09:25:55.49#ibcon#end of sib2, iclass 15, count 0 2006.285.09:25:55.49#ibcon#*after write, iclass 15, count 0 2006.285.09:25:55.49#ibcon#*before return 0, iclass 15, count 0 2006.285.09:25:55.49#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:25:55.49#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:25:55.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.09:25:55.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.09:25:55.49$vck44/va=5,3 2006.285.09:25:55.49#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.09:25:55.49#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.09:25:55.49#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:55.49#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:25:55.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:25:55.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:25:55.55#ibcon#enter wrdev, iclass 17, count 2 2006.285.09:25:55.55#ibcon#first serial, iclass 17, count 2 2006.285.09:25:55.55#ibcon#enter sib2, iclass 17, count 2 2006.285.09:25:55.55#ibcon#flushed, iclass 17, count 2 2006.285.09:25:55.55#ibcon#about to write, iclass 17, count 2 2006.285.09:25:55.55#ibcon#wrote, iclass 17, count 2 2006.285.09:25:55.55#ibcon#about to read 3, iclass 17, count 2 2006.285.09:25:55.57#ibcon#read 3, iclass 17, count 2 2006.285.09:25:55.57#ibcon#about to read 4, iclass 17, count 2 2006.285.09:25:55.57#ibcon#read 4, iclass 17, count 2 2006.285.09:25:55.57#ibcon#about to read 5, iclass 17, count 2 2006.285.09:25:55.57#ibcon#read 5, iclass 17, count 2 2006.285.09:25:55.57#ibcon#about to read 6, iclass 17, count 2 2006.285.09:25:55.57#ibcon#read 6, iclass 17, count 2 2006.285.09:25:55.57#ibcon#end of sib2, iclass 17, count 2 2006.285.09:25:55.57#ibcon#*mode == 0, iclass 17, count 2 2006.285.09:25:55.57#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.09:25:55.57#ibcon#[25=AT05-03\r\n] 2006.285.09:25:55.57#ibcon#*before write, iclass 17, count 2 2006.285.09:25:55.57#ibcon#enter sib2, iclass 17, count 2 2006.285.09:25:55.57#ibcon#flushed, iclass 17, count 2 2006.285.09:25:55.57#ibcon#about to write, iclass 17, count 2 2006.285.09:25:55.57#ibcon#wrote, iclass 17, count 2 2006.285.09:25:55.57#ibcon#about to read 3, iclass 17, count 2 2006.285.09:25:55.60#ibcon#read 3, iclass 17, count 2 2006.285.09:25:55.60#ibcon#about to read 4, iclass 17, count 2 2006.285.09:25:55.60#ibcon#read 4, iclass 17, count 2 2006.285.09:25:55.60#ibcon#about to read 5, iclass 17, count 2 2006.285.09:25:55.60#ibcon#read 5, iclass 17, count 2 2006.285.09:25:55.60#ibcon#about to read 6, iclass 17, count 2 2006.285.09:25:55.60#ibcon#read 6, iclass 17, count 2 2006.285.09:25:55.60#ibcon#end of sib2, iclass 17, count 2 2006.285.09:25:55.60#ibcon#*after write, iclass 17, count 2 2006.285.09:25:55.60#ibcon#*before return 0, iclass 17, count 2 2006.285.09:25:55.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:25:55.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:25:55.60#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.09:25:55.60#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:55.60#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:25:55.72#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:25:55.72#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:25:55.72#ibcon#enter wrdev, iclass 17, count 0 2006.285.09:25:55.72#ibcon#first serial, iclass 17, count 0 2006.285.09:25:55.72#ibcon#enter sib2, iclass 17, count 0 2006.285.09:25:55.72#ibcon#flushed, iclass 17, count 0 2006.285.09:25:55.72#ibcon#about to write, iclass 17, count 0 2006.285.09:25:55.72#ibcon#wrote, iclass 17, count 0 2006.285.09:25:55.72#ibcon#about to read 3, iclass 17, count 0 2006.285.09:25:55.74#ibcon#read 3, iclass 17, count 0 2006.285.09:25:55.74#ibcon#about to read 4, iclass 17, count 0 2006.285.09:25:55.74#ibcon#read 4, iclass 17, count 0 2006.285.09:25:55.74#ibcon#about to read 5, iclass 17, count 0 2006.285.09:25:55.74#ibcon#read 5, iclass 17, count 0 2006.285.09:25:55.74#ibcon#about to read 6, iclass 17, count 0 2006.285.09:25:55.74#ibcon#read 6, iclass 17, count 0 2006.285.09:25:55.74#ibcon#end of sib2, iclass 17, count 0 2006.285.09:25:55.74#ibcon#*mode == 0, iclass 17, count 0 2006.285.09:25:55.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.09:25:55.74#ibcon#[25=USB\r\n] 2006.285.09:25:55.74#ibcon#*before write, iclass 17, count 0 2006.285.09:25:55.74#ibcon#enter sib2, iclass 17, count 0 2006.285.09:25:55.74#ibcon#flushed, iclass 17, count 0 2006.285.09:25:55.74#ibcon#about to write, iclass 17, count 0 2006.285.09:25:55.74#ibcon#wrote, iclass 17, count 0 2006.285.09:25:55.74#ibcon#about to read 3, iclass 17, count 0 2006.285.09:25:55.77#ibcon#read 3, iclass 17, count 0 2006.285.09:25:55.77#ibcon#about to read 4, iclass 17, count 0 2006.285.09:25:55.77#ibcon#read 4, iclass 17, count 0 2006.285.09:25:55.77#ibcon#about to read 5, iclass 17, count 0 2006.285.09:25:55.77#ibcon#read 5, iclass 17, count 0 2006.285.09:25:55.77#ibcon#about to read 6, iclass 17, count 0 2006.285.09:25:55.77#ibcon#read 6, iclass 17, count 0 2006.285.09:25:55.77#ibcon#end of sib2, iclass 17, count 0 2006.285.09:25:55.77#ibcon#*after write, iclass 17, count 0 2006.285.09:25:55.77#ibcon#*before return 0, iclass 17, count 0 2006.285.09:25:55.77#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:25:55.77#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:25:55.77#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.09:25:55.77#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.09:25:55.77$vck44/valo=6,814.99 2006.285.09:25:55.77#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.09:25:55.77#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.09:25:55.77#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:55.77#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:25:55.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:25:55.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:25:55.77#ibcon#enter wrdev, iclass 19, count 0 2006.285.09:25:55.77#ibcon#first serial, iclass 19, count 0 2006.285.09:25:55.77#ibcon#enter sib2, iclass 19, count 0 2006.285.09:25:55.77#ibcon#flushed, iclass 19, count 0 2006.285.09:25:55.77#ibcon#about to write, iclass 19, count 0 2006.285.09:25:55.77#ibcon#wrote, iclass 19, count 0 2006.285.09:25:55.77#ibcon#about to read 3, iclass 19, count 0 2006.285.09:25:55.79#ibcon#read 3, iclass 19, count 0 2006.285.09:25:55.79#ibcon#about to read 4, iclass 19, count 0 2006.285.09:25:55.79#ibcon#read 4, iclass 19, count 0 2006.285.09:25:55.79#ibcon#about to read 5, iclass 19, count 0 2006.285.09:25:55.79#ibcon#read 5, iclass 19, count 0 2006.285.09:25:55.79#ibcon#about to read 6, iclass 19, count 0 2006.285.09:25:55.79#ibcon#read 6, iclass 19, count 0 2006.285.09:25:55.79#ibcon#end of sib2, iclass 19, count 0 2006.285.09:25:55.79#ibcon#*mode == 0, iclass 19, count 0 2006.285.09:25:55.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.09:25:55.79#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:25:55.79#ibcon#*before write, iclass 19, count 0 2006.285.09:25:55.79#ibcon#enter sib2, iclass 19, count 0 2006.285.09:25:55.79#ibcon#flushed, iclass 19, count 0 2006.285.09:25:55.79#ibcon#about to write, iclass 19, count 0 2006.285.09:25:55.79#ibcon#wrote, iclass 19, count 0 2006.285.09:25:55.79#ibcon#about to read 3, iclass 19, count 0 2006.285.09:25:55.83#ibcon#read 3, iclass 19, count 0 2006.285.09:25:55.83#ibcon#about to read 4, iclass 19, count 0 2006.285.09:25:55.83#ibcon#read 4, iclass 19, count 0 2006.285.09:25:55.83#ibcon#about to read 5, iclass 19, count 0 2006.285.09:25:55.83#ibcon#read 5, iclass 19, count 0 2006.285.09:25:55.83#ibcon#about to read 6, iclass 19, count 0 2006.285.09:25:55.83#ibcon#read 6, iclass 19, count 0 2006.285.09:25:55.83#ibcon#end of sib2, iclass 19, count 0 2006.285.09:25:55.83#ibcon#*after write, iclass 19, count 0 2006.285.09:25:55.83#ibcon#*before return 0, iclass 19, count 0 2006.285.09:25:55.83#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:25:55.83#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:25:55.83#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.09:25:55.83#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.09:25:55.83$vck44/va=6,4 2006.285.09:25:55.83#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.09:25:55.83#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.09:25:55.83#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:55.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:25:55.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:25:55.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:25:55.89#ibcon#enter wrdev, iclass 21, count 2 2006.285.09:25:55.89#ibcon#first serial, iclass 21, count 2 2006.285.09:25:55.89#ibcon#enter sib2, iclass 21, count 2 2006.285.09:25:55.89#ibcon#flushed, iclass 21, count 2 2006.285.09:25:55.89#ibcon#about to write, iclass 21, count 2 2006.285.09:25:55.89#ibcon#wrote, iclass 21, count 2 2006.285.09:25:55.89#ibcon#about to read 3, iclass 21, count 2 2006.285.09:25:55.91#ibcon#read 3, iclass 21, count 2 2006.285.09:25:55.91#ibcon#about to read 4, iclass 21, count 2 2006.285.09:25:55.91#ibcon#read 4, iclass 21, count 2 2006.285.09:25:55.91#ibcon#about to read 5, iclass 21, count 2 2006.285.09:25:55.91#ibcon#read 5, iclass 21, count 2 2006.285.09:25:55.91#ibcon#about to read 6, iclass 21, count 2 2006.285.09:25:55.91#ibcon#read 6, iclass 21, count 2 2006.285.09:25:55.91#ibcon#end of sib2, iclass 21, count 2 2006.285.09:25:55.91#ibcon#*mode == 0, iclass 21, count 2 2006.285.09:25:55.91#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.09:25:55.91#ibcon#[25=AT06-04\r\n] 2006.285.09:25:55.91#ibcon#*before write, iclass 21, count 2 2006.285.09:25:55.91#ibcon#enter sib2, iclass 21, count 2 2006.285.09:25:55.91#ibcon#flushed, iclass 21, count 2 2006.285.09:25:55.91#ibcon#about to write, iclass 21, count 2 2006.285.09:25:55.91#ibcon#wrote, iclass 21, count 2 2006.285.09:25:55.91#ibcon#about to read 3, iclass 21, count 2 2006.285.09:25:55.94#ibcon#read 3, iclass 21, count 2 2006.285.09:25:55.94#ibcon#about to read 4, iclass 21, count 2 2006.285.09:25:55.94#ibcon#read 4, iclass 21, count 2 2006.285.09:25:55.94#ibcon#about to read 5, iclass 21, count 2 2006.285.09:25:55.94#ibcon#read 5, iclass 21, count 2 2006.285.09:25:55.94#ibcon#about to read 6, iclass 21, count 2 2006.285.09:25:55.94#ibcon#read 6, iclass 21, count 2 2006.285.09:25:55.94#ibcon#end of sib2, iclass 21, count 2 2006.285.09:25:55.94#ibcon#*after write, iclass 21, count 2 2006.285.09:25:55.94#ibcon#*before return 0, iclass 21, count 2 2006.285.09:25:55.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:25:55.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:25:55.94#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.09:25:55.94#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:55.94#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:25:56.06#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:25:56.06#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:25:56.06#ibcon#enter wrdev, iclass 21, count 0 2006.285.09:25:56.06#ibcon#first serial, iclass 21, count 0 2006.285.09:25:56.06#ibcon#enter sib2, iclass 21, count 0 2006.285.09:25:56.06#ibcon#flushed, iclass 21, count 0 2006.285.09:25:56.06#ibcon#about to write, iclass 21, count 0 2006.285.09:25:56.06#ibcon#wrote, iclass 21, count 0 2006.285.09:25:56.06#ibcon#about to read 3, iclass 21, count 0 2006.285.09:25:56.08#ibcon#read 3, iclass 21, count 0 2006.285.09:25:56.08#ibcon#about to read 4, iclass 21, count 0 2006.285.09:25:56.08#ibcon#read 4, iclass 21, count 0 2006.285.09:25:56.08#ibcon#about to read 5, iclass 21, count 0 2006.285.09:25:56.08#ibcon#read 5, iclass 21, count 0 2006.285.09:25:56.08#ibcon#about to read 6, iclass 21, count 0 2006.285.09:25:56.08#ibcon#read 6, iclass 21, count 0 2006.285.09:25:56.08#ibcon#end of sib2, iclass 21, count 0 2006.285.09:25:56.08#ibcon#*mode == 0, iclass 21, count 0 2006.285.09:25:56.08#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.09:25:56.08#ibcon#[25=USB\r\n] 2006.285.09:25:56.08#ibcon#*before write, iclass 21, count 0 2006.285.09:25:56.08#ibcon#enter sib2, iclass 21, count 0 2006.285.09:25:56.08#ibcon#flushed, iclass 21, count 0 2006.285.09:25:56.08#ibcon#about to write, iclass 21, count 0 2006.285.09:25:56.08#ibcon#wrote, iclass 21, count 0 2006.285.09:25:56.08#ibcon#about to read 3, iclass 21, count 0 2006.285.09:25:56.11#ibcon#read 3, iclass 21, count 0 2006.285.09:25:56.11#ibcon#about to read 4, iclass 21, count 0 2006.285.09:25:56.11#ibcon#read 4, iclass 21, count 0 2006.285.09:25:56.11#ibcon#about to read 5, iclass 21, count 0 2006.285.09:25:56.11#ibcon#read 5, iclass 21, count 0 2006.285.09:25:56.11#ibcon#about to read 6, iclass 21, count 0 2006.285.09:25:56.11#ibcon#read 6, iclass 21, count 0 2006.285.09:25:56.11#ibcon#end of sib2, iclass 21, count 0 2006.285.09:25:56.11#ibcon#*after write, iclass 21, count 0 2006.285.09:25:56.11#ibcon#*before return 0, iclass 21, count 0 2006.285.09:25:56.11#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:25:56.11#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:25:56.11#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.09:25:56.11#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.09:25:56.11$vck44/valo=7,864.99 2006.285.09:25:56.11#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.09:25:56.11#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.09:25:56.11#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:56.11#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:25:56.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:25:56.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:25:56.11#ibcon#enter wrdev, iclass 23, count 0 2006.285.09:25:56.11#ibcon#first serial, iclass 23, count 0 2006.285.09:25:56.11#ibcon#enter sib2, iclass 23, count 0 2006.285.09:25:56.11#ibcon#flushed, iclass 23, count 0 2006.285.09:25:56.11#ibcon#about to write, iclass 23, count 0 2006.285.09:25:56.11#ibcon#wrote, iclass 23, count 0 2006.285.09:25:56.11#ibcon#about to read 3, iclass 23, count 0 2006.285.09:25:56.13#ibcon#read 3, iclass 23, count 0 2006.285.09:25:56.13#ibcon#about to read 4, iclass 23, count 0 2006.285.09:25:56.13#ibcon#read 4, iclass 23, count 0 2006.285.09:25:56.13#ibcon#about to read 5, iclass 23, count 0 2006.285.09:25:56.13#ibcon#read 5, iclass 23, count 0 2006.285.09:25:56.13#ibcon#about to read 6, iclass 23, count 0 2006.285.09:25:56.13#ibcon#read 6, iclass 23, count 0 2006.285.09:25:56.13#ibcon#end of sib2, iclass 23, count 0 2006.285.09:25:56.13#ibcon#*mode == 0, iclass 23, count 0 2006.285.09:25:56.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.09:25:56.13#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:25:56.13#ibcon#*before write, iclass 23, count 0 2006.285.09:25:56.13#ibcon#enter sib2, iclass 23, count 0 2006.285.09:25:56.13#ibcon#flushed, iclass 23, count 0 2006.285.09:25:56.13#ibcon#about to write, iclass 23, count 0 2006.285.09:25:56.13#ibcon#wrote, iclass 23, count 0 2006.285.09:25:56.13#ibcon#about to read 3, iclass 23, count 0 2006.285.09:25:56.17#ibcon#read 3, iclass 23, count 0 2006.285.09:25:56.17#ibcon#about to read 4, iclass 23, count 0 2006.285.09:25:56.17#ibcon#read 4, iclass 23, count 0 2006.285.09:25:56.17#ibcon#about to read 5, iclass 23, count 0 2006.285.09:25:56.17#ibcon#read 5, iclass 23, count 0 2006.285.09:25:56.17#ibcon#about to read 6, iclass 23, count 0 2006.285.09:25:56.17#ibcon#read 6, iclass 23, count 0 2006.285.09:25:56.17#ibcon#end of sib2, iclass 23, count 0 2006.285.09:25:56.17#ibcon#*after write, iclass 23, count 0 2006.285.09:25:56.17#ibcon#*before return 0, iclass 23, count 0 2006.285.09:25:56.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:25:56.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:25:56.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.09:25:56.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.09:25:56.17$vck44/va=7,4 2006.285.09:25:56.17#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.09:25:56.17#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.09:25:56.17#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:56.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:25:56.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:25:56.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:25:56.23#ibcon#enter wrdev, iclass 25, count 2 2006.285.09:25:56.23#ibcon#first serial, iclass 25, count 2 2006.285.09:25:56.23#ibcon#enter sib2, iclass 25, count 2 2006.285.09:25:56.23#ibcon#flushed, iclass 25, count 2 2006.285.09:25:56.23#ibcon#about to write, iclass 25, count 2 2006.285.09:25:56.23#ibcon#wrote, iclass 25, count 2 2006.285.09:25:56.23#ibcon#about to read 3, iclass 25, count 2 2006.285.09:25:56.25#ibcon#read 3, iclass 25, count 2 2006.285.09:25:56.25#ibcon#about to read 4, iclass 25, count 2 2006.285.09:25:56.25#ibcon#read 4, iclass 25, count 2 2006.285.09:25:56.25#ibcon#about to read 5, iclass 25, count 2 2006.285.09:25:56.25#ibcon#read 5, iclass 25, count 2 2006.285.09:25:56.25#ibcon#about to read 6, iclass 25, count 2 2006.285.09:25:56.25#ibcon#read 6, iclass 25, count 2 2006.285.09:25:56.25#ibcon#end of sib2, iclass 25, count 2 2006.285.09:25:56.25#ibcon#*mode == 0, iclass 25, count 2 2006.285.09:25:56.25#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.09:25:56.25#ibcon#[25=AT07-04\r\n] 2006.285.09:25:56.25#ibcon#*before write, iclass 25, count 2 2006.285.09:25:56.25#ibcon#enter sib2, iclass 25, count 2 2006.285.09:25:56.25#ibcon#flushed, iclass 25, count 2 2006.285.09:25:56.25#ibcon#about to write, iclass 25, count 2 2006.285.09:25:56.25#ibcon#wrote, iclass 25, count 2 2006.285.09:25:56.25#ibcon#about to read 3, iclass 25, count 2 2006.285.09:25:56.28#ibcon#read 3, iclass 25, count 2 2006.285.09:25:56.28#ibcon#about to read 4, iclass 25, count 2 2006.285.09:25:56.28#ibcon#read 4, iclass 25, count 2 2006.285.09:25:56.28#ibcon#about to read 5, iclass 25, count 2 2006.285.09:25:56.28#ibcon#read 5, iclass 25, count 2 2006.285.09:25:56.28#ibcon#about to read 6, iclass 25, count 2 2006.285.09:25:56.28#ibcon#read 6, iclass 25, count 2 2006.285.09:25:56.28#ibcon#end of sib2, iclass 25, count 2 2006.285.09:25:56.28#ibcon#*after write, iclass 25, count 2 2006.285.09:25:56.28#ibcon#*before return 0, iclass 25, count 2 2006.285.09:25:56.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:25:56.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:25:56.28#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.09:25:56.28#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:56.28#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:25:56.40#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:25:56.40#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:25:56.40#ibcon#enter wrdev, iclass 25, count 0 2006.285.09:25:56.40#ibcon#first serial, iclass 25, count 0 2006.285.09:25:56.40#ibcon#enter sib2, iclass 25, count 0 2006.285.09:25:56.40#ibcon#flushed, iclass 25, count 0 2006.285.09:25:56.40#ibcon#about to write, iclass 25, count 0 2006.285.09:25:56.40#ibcon#wrote, iclass 25, count 0 2006.285.09:25:56.40#ibcon#about to read 3, iclass 25, count 0 2006.285.09:25:56.42#ibcon#read 3, iclass 25, count 0 2006.285.09:25:56.42#ibcon#about to read 4, iclass 25, count 0 2006.285.09:25:56.42#ibcon#read 4, iclass 25, count 0 2006.285.09:25:56.42#ibcon#about to read 5, iclass 25, count 0 2006.285.09:25:56.42#ibcon#read 5, iclass 25, count 0 2006.285.09:25:56.42#ibcon#about to read 6, iclass 25, count 0 2006.285.09:25:56.42#ibcon#read 6, iclass 25, count 0 2006.285.09:25:56.42#ibcon#end of sib2, iclass 25, count 0 2006.285.09:25:56.42#ibcon#*mode == 0, iclass 25, count 0 2006.285.09:25:56.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.09:25:56.42#ibcon#[25=USB\r\n] 2006.285.09:25:56.42#ibcon#*before write, iclass 25, count 0 2006.285.09:25:56.42#ibcon#enter sib2, iclass 25, count 0 2006.285.09:25:56.42#ibcon#flushed, iclass 25, count 0 2006.285.09:25:56.42#ibcon#about to write, iclass 25, count 0 2006.285.09:25:56.42#ibcon#wrote, iclass 25, count 0 2006.285.09:25:56.42#ibcon#about to read 3, iclass 25, count 0 2006.285.09:25:56.45#ibcon#read 3, iclass 25, count 0 2006.285.09:25:56.45#ibcon#about to read 4, iclass 25, count 0 2006.285.09:25:56.45#ibcon#read 4, iclass 25, count 0 2006.285.09:25:56.45#ibcon#about to read 5, iclass 25, count 0 2006.285.09:25:56.45#ibcon#read 5, iclass 25, count 0 2006.285.09:25:56.45#ibcon#about to read 6, iclass 25, count 0 2006.285.09:25:56.45#ibcon#read 6, iclass 25, count 0 2006.285.09:25:56.45#ibcon#end of sib2, iclass 25, count 0 2006.285.09:25:56.45#ibcon#*after write, iclass 25, count 0 2006.285.09:25:56.45#ibcon#*before return 0, iclass 25, count 0 2006.285.09:25:56.45#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:25:56.45#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:25:56.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.09:25:56.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.09:25:56.45$vck44/valo=8,884.99 2006.285.09:25:56.45#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.09:25:56.45#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.09:25:56.45#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:56.45#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:25:56.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:25:56.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:25:56.45#ibcon#enter wrdev, iclass 27, count 0 2006.285.09:25:56.45#ibcon#first serial, iclass 27, count 0 2006.285.09:25:56.45#ibcon#enter sib2, iclass 27, count 0 2006.285.09:25:56.45#ibcon#flushed, iclass 27, count 0 2006.285.09:25:56.45#ibcon#about to write, iclass 27, count 0 2006.285.09:25:56.45#ibcon#wrote, iclass 27, count 0 2006.285.09:25:56.45#ibcon#about to read 3, iclass 27, count 0 2006.285.09:25:56.47#ibcon#read 3, iclass 27, count 0 2006.285.09:25:56.47#ibcon#about to read 4, iclass 27, count 0 2006.285.09:25:56.47#ibcon#read 4, iclass 27, count 0 2006.285.09:25:56.47#ibcon#about to read 5, iclass 27, count 0 2006.285.09:25:56.47#ibcon#read 5, iclass 27, count 0 2006.285.09:25:56.47#ibcon#about to read 6, iclass 27, count 0 2006.285.09:25:56.47#ibcon#read 6, iclass 27, count 0 2006.285.09:25:56.47#ibcon#end of sib2, iclass 27, count 0 2006.285.09:25:56.47#ibcon#*mode == 0, iclass 27, count 0 2006.285.09:25:56.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.09:25:56.47#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:25:56.47#ibcon#*before write, iclass 27, count 0 2006.285.09:25:56.47#ibcon#enter sib2, iclass 27, count 0 2006.285.09:25:56.47#ibcon#flushed, iclass 27, count 0 2006.285.09:25:56.47#ibcon#about to write, iclass 27, count 0 2006.285.09:25:56.47#ibcon#wrote, iclass 27, count 0 2006.285.09:25:56.47#ibcon#about to read 3, iclass 27, count 0 2006.285.09:25:56.51#ibcon#read 3, iclass 27, count 0 2006.285.09:25:56.51#ibcon#about to read 4, iclass 27, count 0 2006.285.09:25:56.51#ibcon#read 4, iclass 27, count 0 2006.285.09:25:56.51#ibcon#about to read 5, iclass 27, count 0 2006.285.09:25:56.51#ibcon#read 5, iclass 27, count 0 2006.285.09:25:56.51#ibcon#about to read 6, iclass 27, count 0 2006.285.09:25:56.51#ibcon#read 6, iclass 27, count 0 2006.285.09:25:56.51#ibcon#end of sib2, iclass 27, count 0 2006.285.09:25:56.51#ibcon#*after write, iclass 27, count 0 2006.285.09:25:56.51#ibcon#*before return 0, iclass 27, count 0 2006.285.09:25:56.51#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:25:56.51#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:25:56.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.09:25:56.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.09:25:56.51$vck44/va=8,3 2006.285.09:25:56.51#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.09:25:56.51#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.09:25:56.51#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:56.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:25:56.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:25:56.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:25:56.57#ibcon#enter wrdev, iclass 29, count 2 2006.285.09:25:56.57#ibcon#first serial, iclass 29, count 2 2006.285.09:25:56.57#ibcon#enter sib2, iclass 29, count 2 2006.285.09:25:56.57#ibcon#flushed, iclass 29, count 2 2006.285.09:25:56.57#ibcon#about to write, iclass 29, count 2 2006.285.09:25:56.57#ibcon#wrote, iclass 29, count 2 2006.285.09:25:56.57#ibcon#about to read 3, iclass 29, count 2 2006.285.09:25:56.59#ibcon#read 3, iclass 29, count 2 2006.285.09:25:56.59#ibcon#about to read 4, iclass 29, count 2 2006.285.09:25:56.59#ibcon#read 4, iclass 29, count 2 2006.285.09:25:56.59#ibcon#about to read 5, iclass 29, count 2 2006.285.09:25:56.59#ibcon#read 5, iclass 29, count 2 2006.285.09:25:56.59#ibcon#about to read 6, iclass 29, count 2 2006.285.09:25:56.59#ibcon#read 6, iclass 29, count 2 2006.285.09:25:56.59#ibcon#end of sib2, iclass 29, count 2 2006.285.09:25:56.59#ibcon#*mode == 0, iclass 29, count 2 2006.285.09:25:56.59#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.09:25:56.59#ibcon#[25=AT08-03\r\n] 2006.285.09:25:56.59#ibcon#*before write, iclass 29, count 2 2006.285.09:25:56.59#ibcon#enter sib2, iclass 29, count 2 2006.285.09:25:56.59#ibcon#flushed, iclass 29, count 2 2006.285.09:25:56.59#ibcon#about to write, iclass 29, count 2 2006.285.09:25:56.59#ibcon#wrote, iclass 29, count 2 2006.285.09:25:56.59#ibcon#about to read 3, iclass 29, count 2 2006.285.09:25:56.62#ibcon#read 3, iclass 29, count 2 2006.285.09:25:56.62#ibcon#about to read 4, iclass 29, count 2 2006.285.09:25:56.62#ibcon#read 4, iclass 29, count 2 2006.285.09:25:56.62#ibcon#about to read 5, iclass 29, count 2 2006.285.09:25:56.62#ibcon#read 5, iclass 29, count 2 2006.285.09:25:56.62#ibcon#about to read 6, iclass 29, count 2 2006.285.09:25:56.62#ibcon#read 6, iclass 29, count 2 2006.285.09:25:56.62#ibcon#end of sib2, iclass 29, count 2 2006.285.09:25:56.62#ibcon#*after write, iclass 29, count 2 2006.285.09:25:56.62#ibcon#*before return 0, iclass 29, count 2 2006.285.09:25:56.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:25:56.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:25:56.62#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.09:25:56.62#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:56.62#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:25:56.74#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:25:56.74#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:25:56.74#ibcon#enter wrdev, iclass 29, count 0 2006.285.09:25:56.74#ibcon#first serial, iclass 29, count 0 2006.285.09:25:56.74#ibcon#enter sib2, iclass 29, count 0 2006.285.09:25:56.74#ibcon#flushed, iclass 29, count 0 2006.285.09:25:56.74#ibcon#about to write, iclass 29, count 0 2006.285.09:25:56.74#ibcon#wrote, iclass 29, count 0 2006.285.09:25:56.74#ibcon#about to read 3, iclass 29, count 0 2006.285.09:25:56.76#ibcon#read 3, iclass 29, count 0 2006.285.09:25:56.76#ibcon#about to read 4, iclass 29, count 0 2006.285.09:25:56.76#ibcon#read 4, iclass 29, count 0 2006.285.09:25:56.76#ibcon#about to read 5, iclass 29, count 0 2006.285.09:25:56.76#ibcon#read 5, iclass 29, count 0 2006.285.09:25:56.76#ibcon#about to read 6, iclass 29, count 0 2006.285.09:25:56.76#ibcon#read 6, iclass 29, count 0 2006.285.09:25:56.76#ibcon#end of sib2, iclass 29, count 0 2006.285.09:25:56.76#ibcon#*mode == 0, iclass 29, count 0 2006.285.09:25:56.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.09:25:56.76#ibcon#[25=USB\r\n] 2006.285.09:25:56.76#ibcon#*before write, iclass 29, count 0 2006.285.09:25:56.76#ibcon#enter sib2, iclass 29, count 0 2006.285.09:25:56.76#ibcon#flushed, iclass 29, count 0 2006.285.09:25:56.76#ibcon#about to write, iclass 29, count 0 2006.285.09:25:56.76#ibcon#wrote, iclass 29, count 0 2006.285.09:25:56.76#ibcon#about to read 3, iclass 29, count 0 2006.285.09:25:56.79#ibcon#read 3, iclass 29, count 0 2006.285.09:25:56.79#ibcon#about to read 4, iclass 29, count 0 2006.285.09:25:56.79#ibcon#read 4, iclass 29, count 0 2006.285.09:25:56.79#ibcon#about to read 5, iclass 29, count 0 2006.285.09:25:56.79#ibcon#read 5, iclass 29, count 0 2006.285.09:25:56.79#ibcon#about to read 6, iclass 29, count 0 2006.285.09:25:56.79#ibcon#read 6, iclass 29, count 0 2006.285.09:25:56.79#ibcon#end of sib2, iclass 29, count 0 2006.285.09:25:56.79#ibcon#*after write, iclass 29, count 0 2006.285.09:25:56.79#ibcon#*before return 0, iclass 29, count 0 2006.285.09:25:56.79#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:25:56.79#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:25:56.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.09:25:56.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.09:25:56.79$vck44/vblo=1,629.99 2006.285.09:25:56.79#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.09:25:56.79#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.09:25:56.79#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:56.79#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:25:56.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:25:56.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:25:56.79#ibcon#enter wrdev, iclass 31, count 0 2006.285.09:25:56.79#ibcon#first serial, iclass 31, count 0 2006.285.09:25:56.79#ibcon#enter sib2, iclass 31, count 0 2006.285.09:25:56.79#ibcon#flushed, iclass 31, count 0 2006.285.09:25:56.79#ibcon#about to write, iclass 31, count 0 2006.285.09:25:56.79#ibcon#wrote, iclass 31, count 0 2006.285.09:25:56.79#ibcon#about to read 3, iclass 31, count 0 2006.285.09:25:56.81#ibcon#read 3, iclass 31, count 0 2006.285.09:25:56.81#ibcon#about to read 4, iclass 31, count 0 2006.285.09:25:56.81#ibcon#read 4, iclass 31, count 0 2006.285.09:25:56.81#ibcon#about to read 5, iclass 31, count 0 2006.285.09:25:56.81#ibcon#read 5, iclass 31, count 0 2006.285.09:25:56.81#ibcon#about to read 6, iclass 31, count 0 2006.285.09:25:56.81#ibcon#read 6, iclass 31, count 0 2006.285.09:25:56.81#ibcon#end of sib2, iclass 31, count 0 2006.285.09:25:56.81#ibcon#*mode == 0, iclass 31, count 0 2006.285.09:25:56.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.09:25:56.81#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:25:56.81#ibcon#*before write, iclass 31, count 0 2006.285.09:25:56.81#ibcon#enter sib2, iclass 31, count 0 2006.285.09:25:56.81#ibcon#flushed, iclass 31, count 0 2006.285.09:25:56.81#ibcon#about to write, iclass 31, count 0 2006.285.09:25:56.81#ibcon#wrote, iclass 31, count 0 2006.285.09:25:56.81#ibcon#about to read 3, iclass 31, count 0 2006.285.09:25:56.85#ibcon#read 3, iclass 31, count 0 2006.285.09:25:56.85#ibcon#about to read 4, iclass 31, count 0 2006.285.09:25:56.85#ibcon#read 4, iclass 31, count 0 2006.285.09:25:56.85#ibcon#about to read 5, iclass 31, count 0 2006.285.09:25:56.85#ibcon#read 5, iclass 31, count 0 2006.285.09:25:56.85#ibcon#about to read 6, iclass 31, count 0 2006.285.09:25:56.85#ibcon#read 6, iclass 31, count 0 2006.285.09:25:56.85#ibcon#end of sib2, iclass 31, count 0 2006.285.09:25:56.85#ibcon#*after write, iclass 31, count 0 2006.285.09:25:56.85#ibcon#*before return 0, iclass 31, count 0 2006.285.09:25:56.85#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:25:56.85#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:25:56.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.09:25:56.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.09:25:56.85$vck44/vb=1,4 2006.285.09:25:56.85#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.09:25:56.85#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.09:25:56.85#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:56.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:25:56.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:25:56.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:25:56.85#ibcon#enter wrdev, iclass 33, count 2 2006.285.09:25:56.85#ibcon#first serial, iclass 33, count 2 2006.285.09:25:56.85#ibcon#enter sib2, iclass 33, count 2 2006.285.09:25:56.85#ibcon#flushed, iclass 33, count 2 2006.285.09:25:56.85#ibcon#about to write, iclass 33, count 2 2006.285.09:25:56.85#ibcon#wrote, iclass 33, count 2 2006.285.09:25:56.85#ibcon#about to read 3, iclass 33, count 2 2006.285.09:25:56.87#ibcon#read 3, iclass 33, count 2 2006.285.09:25:56.87#ibcon#about to read 4, iclass 33, count 2 2006.285.09:25:56.87#ibcon#read 4, iclass 33, count 2 2006.285.09:25:56.87#ibcon#about to read 5, iclass 33, count 2 2006.285.09:25:56.87#ibcon#read 5, iclass 33, count 2 2006.285.09:25:56.87#ibcon#about to read 6, iclass 33, count 2 2006.285.09:25:56.87#ibcon#read 6, iclass 33, count 2 2006.285.09:25:56.87#ibcon#end of sib2, iclass 33, count 2 2006.285.09:25:56.87#ibcon#*mode == 0, iclass 33, count 2 2006.285.09:25:56.87#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.09:25:56.87#ibcon#[27=AT01-04\r\n] 2006.285.09:25:56.87#ibcon#*before write, iclass 33, count 2 2006.285.09:25:56.87#ibcon#enter sib2, iclass 33, count 2 2006.285.09:25:56.87#ibcon#flushed, iclass 33, count 2 2006.285.09:25:56.87#ibcon#about to write, iclass 33, count 2 2006.285.09:25:56.87#ibcon#wrote, iclass 33, count 2 2006.285.09:25:56.87#ibcon#about to read 3, iclass 33, count 2 2006.285.09:25:56.90#ibcon#read 3, iclass 33, count 2 2006.285.09:25:56.90#ibcon#about to read 4, iclass 33, count 2 2006.285.09:25:56.90#ibcon#read 4, iclass 33, count 2 2006.285.09:25:56.90#ibcon#about to read 5, iclass 33, count 2 2006.285.09:25:56.90#ibcon#read 5, iclass 33, count 2 2006.285.09:25:56.90#ibcon#about to read 6, iclass 33, count 2 2006.285.09:25:56.90#ibcon#read 6, iclass 33, count 2 2006.285.09:25:56.90#ibcon#end of sib2, iclass 33, count 2 2006.285.09:25:56.90#ibcon#*after write, iclass 33, count 2 2006.285.09:25:56.90#ibcon#*before return 0, iclass 33, count 2 2006.285.09:25:56.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:25:56.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:25:56.90#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.09:25:56.90#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:56.90#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:25:57.02#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:25:57.02#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:25:57.02#ibcon#enter wrdev, iclass 33, count 0 2006.285.09:25:57.02#ibcon#first serial, iclass 33, count 0 2006.285.09:25:57.02#ibcon#enter sib2, iclass 33, count 0 2006.285.09:25:57.02#ibcon#flushed, iclass 33, count 0 2006.285.09:25:57.02#ibcon#about to write, iclass 33, count 0 2006.285.09:25:57.02#ibcon#wrote, iclass 33, count 0 2006.285.09:25:57.02#ibcon#about to read 3, iclass 33, count 0 2006.285.09:25:57.04#ibcon#read 3, iclass 33, count 0 2006.285.09:25:57.04#ibcon#about to read 4, iclass 33, count 0 2006.285.09:25:57.04#ibcon#read 4, iclass 33, count 0 2006.285.09:25:57.04#ibcon#about to read 5, iclass 33, count 0 2006.285.09:25:57.04#ibcon#read 5, iclass 33, count 0 2006.285.09:25:57.04#ibcon#about to read 6, iclass 33, count 0 2006.285.09:25:57.04#ibcon#read 6, iclass 33, count 0 2006.285.09:25:57.04#ibcon#end of sib2, iclass 33, count 0 2006.285.09:25:57.04#ibcon#*mode == 0, iclass 33, count 0 2006.285.09:25:57.04#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.09:25:57.04#ibcon#[27=USB\r\n] 2006.285.09:25:57.04#ibcon#*before write, iclass 33, count 0 2006.285.09:25:57.04#ibcon#enter sib2, iclass 33, count 0 2006.285.09:25:57.04#ibcon#flushed, iclass 33, count 0 2006.285.09:25:57.04#ibcon#about to write, iclass 33, count 0 2006.285.09:25:57.04#ibcon#wrote, iclass 33, count 0 2006.285.09:25:57.04#ibcon#about to read 3, iclass 33, count 0 2006.285.09:25:57.07#ibcon#read 3, iclass 33, count 0 2006.285.09:25:57.07#ibcon#about to read 4, iclass 33, count 0 2006.285.09:25:57.07#ibcon#read 4, iclass 33, count 0 2006.285.09:25:57.07#ibcon#about to read 5, iclass 33, count 0 2006.285.09:25:57.07#ibcon#read 5, iclass 33, count 0 2006.285.09:25:57.07#ibcon#about to read 6, iclass 33, count 0 2006.285.09:25:57.07#ibcon#read 6, iclass 33, count 0 2006.285.09:25:57.07#ibcon#end of sib2, iclass 33, count 0 2006.285.09:25:57.07#ibcon#*after write, iclass 33, count 0 2006.285.09:25:57.07#ibcon#*before return 0, iclass 33, count 0 2006.285.09:25:57.07#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:25:57.07#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:25:57.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.09:25:57.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.09:25:57.07$vck44/vblo=2,634.99 2006.285.09:25:57.07#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.09:25:57.07#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.09:25:57.07#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:57.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:25:57.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:25:57.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:25:57.07#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:25:57.07#ibcon#first serial, iclass 35, count 0 2006.285.09:25:57.07#ibcon#enter sib2, iclass 35, count 0 2006.285.09:25:57.07#ibcon#flushed, iclass 35, count 0 2006.285.09:25:57.07#ibcon#about to write, iclass 35, count 0 2006.285.09:25:57.07#ibcon#wrote, iclass 35, count 0 2006.285.09:25:57.07#ibcon#about to read 3, iclass 35, count 0 2006.285.09:25:57.09#ibcon#read 3, iclass 35, count 0 2006.285.09:25:57.09#ibcon#about to read 4, iclass 35, count 0 2006.285.09:25:57.09#ibcon#read 4, iclass 35, count 0 2006.285.09:25:57.09#ibcon#about to read 5, iclass 35, count 0 2006.285.09:25:57.09#ibcon#read 5, iclass 35, count 0 2006.285.09:25:57.09#ibcon#about to read 6, iclass 35, count 0 2006.285.09:25:57.09#ibcon#read 6, iclass 35, count 0 2006.285.09:25:57.09#ibcon#end of sib2, iclass 35, count 0 2006.285.09:25:57.09#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:25:57.09#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:25:57.09#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:25:57.09#ibcon#*before write, iclass 35, count 0 2006.285.09:25:57.09#ibcon#enter sib2, iclass 35, count 0 2006.285.09:25:57.09#ibcon#flushed, iclass 35, count 0 2006.285.09:25:57.09#ibcon#about to write, iclass 35, count 0 2006.285.09:25:57.09#ibcon#wrote, iclass 35, count 0 2006.285.09:25:57.09#ibcon#about to read 3, iclass 35, count 0 2006.285.09:25:57.13#ibcon#read 3, iclass 35, count 0 2006.285.09:25:57.13#ibcon#about to read 4, iclass 35, count 0 2006.285.09:25:57.13#ibcon#read 4, iclass 35, count 0 2006.285.09:25:57.13#ibcon#about to read 5, iclass 35, count 0 2006.285.09:25:57.13#ibcon#read 5, iclass 35, count 0 2006.285.09:25:57.13#ibcon#about to read 6, iclass 35, count 0 2006.285.09:25:57.13#ibcon#read 6, iclass 35, count 0 2006.285.09:25:57.13#ibcon#end of sib2, iclass 35, count 0 2006.285.09:25:57.13#ibcon#*after write, iclass 35, count 0 2006.285.09:25:57.13#ibcon#*before return 0, iclass 35, count 0 2006.285.09:25:57.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:25:57.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:25:57.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:25:57.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:25:57.13$vck44/vb=2,5 2006.285.09:25:57.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.09:25:57.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.09:25:57.13#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:57.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:25:57.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:25:57.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:25:57.19#ibcon#enter wrdev, iclass 37, count 2 2006.285.09:25:57.19#ibcon#first serial, iclass 37, count 2 2006.285.09:25:57.19#ibcon#enter sib2, iclass 37, count 2 2006.285.09:25:57.19#ibcon#flushed, iclass 37, count 2 2006.285.09:25:57.19#ibcon#about to write, iclass 37, count 2 2006.285.09:25:57.19#ibcon#wrote, iclass 37, count 2 2006.285.09:25:57.19#ibcon#about to read 3, iclass 37, count 2 2006.285.09:25:57.21#ibcon#read 3, iclass 37, count 2 2006.285.09:25:57.21#ibcon#about to read 4, iclass 37, count 2 2006.285.09:25:57.21#ibcon#read 4, iclass 37, count 2 2006.285.09:25:57.21#ibcon#about to read 5, iclass 37, count 2 2006.285.09:25:57.21#ibcon#read 5, iclass 37, count 2 2006.285.09:25:57.21#ibcon#about to read 6, iclass 37, count 2 2006.285.09:25:57.21#ibcon#read 6, iclass 37, count 2 2006.285.09:25:57.21#ibcon#end of sib2, iclass 37, count 2 2006.285.09:25:57.21#ibcon#*mode == 0, iclass 37, count 2 2006.285.09:25:57.21#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.09:25:57.21#ibcon#[27=AT02-05\r\n] 2006.285.09:25:57.21#ibcon#*before write, iclass 37, count 2 2006.285.09:25:57.21#ibcon#enter sib2, iclass 37, count 2 2006.285.09:25:57.21#ibcon#flushed, iclass 37, count 2 2006.285.09:25:57.21#ibcon#about to write, iclass 37, count 2 2006.285.09:25:57.21#ibcon#wrote, iclass 37, count 2 2006.285.09:25:57.21#ibcon#about to read 3, iclass 37, count 2 2006.285.09:25:57.24#ibcon#read 3, iclass 37, count 2 2006.285.09:25:57.24#ibcon#about to read 4, iclass 37, count 2 2006.285.09:25:57.24#ibcon#read 4, iclass 37, count 2 2006.285.09:25:57.24#ibcon#about to read 5, iclass 37, count 2 2006.285.09:25:57.24#ibcon#read 5, iclass 37, count 2 2006.285.09:25:57.24#ibcon#about to read 6, iclass 37, count 2 2006.285.09:25:57.24#ibcon#read 6, iclass 37, count 2 2006.285.09:25:57.24#ibcon#end of sib2, iclass 37, count 2 2006.285.09:25:57.24#ibcon#*after write, iclass 37, count 2 2006.285.09:25:57.24#ibcon#*before return 0, iclass 37, count 2 2006.285.09:25:57.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:25:57.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:25:57.24#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.09:25:57.24#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:57.24#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:25:57.36#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:25:57.36#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:25:57.36#ibcon#enter wrdev, iclass 37, count 0 2006.285.09:25:57.36#ibcon#first serial, iclass 37, count 0 2006.285.09:25:57.36#ibcon#enter sib2, iclass 37, count 0 2006.285.09:25:57.36#ibcon#flushed, iclass 37, count 0 2006.285.09:25:57.36#ibcon#about to write, iclass 37, count 0 2006.285.09:25:57.36#ibcon#wrote, iclass 37, count 0 2006.285.09:25:57.36#ibcon#about to read 3, iclass 37, count 0 2006.285.09:25:57.38#ibcon#read 3, iclass 37, count 0 2006.285.09:25:57.38#ibcon#about to read 4, iclass 37, count 0 2006.285.09:25:57.38#ibcon#read 4, iclass 37, count 0 2006.285.09:25:57.38#ibcon#about to read 5, iclass 37, count 0 2006.285.09:25:57.38#ibcon#read 5, iclass 37, count 0 2006.285.09:25:57.38#ibcon#about to read 6, iclass 37, count 0 2006.285.09:25:57.38#ibcon#read 6, iclass 37, count 0 2006.285.09:25:57.38#ibcon#end of sib2, iclass 37, count 0 2006.285.09:25:57.38#ibcon#*mode == 0, iclass 37, count 0 2006.285.09:25:57.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.09:25:57.38#ibcon#[27=USB\r\n] 2006.285.09:25:57.38#ibcon#*before write, iclass 37, count 0 2006.285.09:25:57.38#ibcon#enter sib2, iclass 37, count 0 2006.285.09:25:57.38#ibcon#flushed, iclass 37, count 0 2006.285.09:25:57.38#ibcon#about to write, iclass 37, count 0 2006.285.09:25:57.38#ibcon#wrote, iclass 37, count 0 2006.285.09:25:57.38#ibcon#about to read 3, iclass 37, count 0 2006.285.09:25:57.41#ibcon#read 3, iclass 37, count 0 2006.285.09:25:57.41#ibcon#about to read 4, iclass 37, count 0 2006.285.09:25:57.41#ibcon#read 4, iclass 37, count 0 2006.285.09:25:57.41#ibcon#about to read 5, iclass 37, count 0 2006.285.09:25:57.41#ibcon#read 5, iclass 37, count 0 2006.285.09:25:57.41#ibcon#about to read 6, iclass 37, count 0 2006.285.09:25:57.41#ibcon#read 6, iclass 37, count 0 2006.285.09:25:57.41#ibcon#end of sib2, iclass 37, count 0 2006.285.09:25:57.41#ibcon#*after write, iclass 37, count 0 2006.285.09:25:57.41#ibcon#*before return 0, iclass 37, count 0 2006.285.09:25:57.41#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:25:57.41#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:25:57.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.09:25:57.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.09:25:57.41$vck44/vblo=3,649.99 2006.285.09:25:57.41#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.09:25:57.41#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.09:25:57.41#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:57.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:25:57.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:25:57.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:25:57.41#ibcon#enter wrdev, iclass 39, count 0 2006.285.09:25:57.41#ibcon#first serial, iclass 39, count 0 2006.285.09:25:57.41#ibcon#enter sib2, iclass 39, count 0 2006.285.09:25:57.41#ibcon#flushed, iclass 39, count 0 2006.285.09:25:57.41#ibcon#about to write, iclass 39, count 0 2006.285.09:25:57.41#ibcon#wrote, iclass 39, count 0 2006.285.09:25:57.41#ibcon#about to read 3, iclass 39, count 0 2006.285.09:25:57.43#ibcon#read 3, iclass 39, count 0 2006.285.09:25:57.43#ibcon#about to read 4, iclass 39, count 0 2006.285.09:25:57.43#ibcon#read 4, iclass 39, count 0 2006.285.09:25:57.43#ibcon#about to read 5, iclass 39, count 0 2006.285.09:25:57.43#ibcon#read 5, iclass 39, count 0 2006.285.09:25:57.43#ibcon#about to read 6, iclass 39, count 0 2006.285.09:25:57.43#ibcon#read 6, iclass 39, count 0 2006.285.09:25:57.43#ibcon#end of sib2, iclass 39, count 0 2006.285.09:25:57.43#ibcon#*mode == 0, iclass 39, count 0 2006.285.09:25:57.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.09:25:57.43#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:25:57.43#ibcon#*before write, iclass 39, count 0 2006.285.09:25:57.43#ibcon#enter sib2, iclass 39, count 0 2006.285.09:25:57.43#ibcon#flushed, iclass 39, count 0 2006.285.09:25:57.43#ibcon#about to write, iclass 39, count 0 2006.285.09:25:57.43#ibcon#wrote, iclass 39, count 0 2006.285.09:25:57.43#ibcon#about to read 3, iclass 39, count 0 2006.285.09:25:57.47#ibcon#read 3, iclass 39, count 0 2006.285.09:25:57.47#ibcon#about to read 4, iclass 39, count 0 2006.285.09:25:57.47#ibcon#read 4, iclass 39, count 0 2006.285.09:25:57.47#ibcon#about to read 5, iclass 39, count 0 2006.285.09:25:57.47#ibcon#read 5, iclass 39, count 0 2006.285.09:25:57.47#ibcon#about to read 6, iclass 39, count 0 2006.285.09:25:57.47#ibcon#read 6, iclass 39, count 0 2006.285.09:25:57.47#ibcon#end of sib2, iclass 39, count 0 2006.285.09:25:57.47#ibcon#*after write, iclass 39, count 0 2006.285.09:25:57.47#ibcon#*before return 0, iclass 39, count 0 2006.285.09:25:57.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:25:57.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:25:57.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.09:25:57.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.09:25:57.47$vck44/vb=3,4 2006.285.09:25:57.47#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.09:25:57.47#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.09:25:57.47#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:57.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:25:57.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:25:57.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:25:57.53#ibcon#enter wrdev, iclass 3, count 2 2006.285.09:25:57.53#ibcon#first serial, iclass 3, count 2 2006.285.09:25:57.53#ibcon#enter sib2, iclass 3, count 2 2006.285.09:25:57.53#ibcon#flushed, iclass 3, count 2 2006.285.09:25:57.53#ibcon#about to write, iclass 3, count 2 2006.285.09:25:57.53#ibcon#wrote, iclass 3, count 2 2006.285.09:25:57.53#ibcon#about to read 3, iclass 3, count 2 2006.285.09:25:57.55#ibcon#read 3, iclass 3, count 2 2006.285.09:25:57.55#ibcon#about to read 4, iclass 3, count 2 2006.285.09:25:57.55#ibcon#read 4, iclass 3, count 2 2006.285.09:25:57.55#ibcon#about to read 5, iclass 3, count 2 2006.285.09:25:57.55#ibcon#read 5, iclass 3, count 2 2006.285.09:25:57.55#ibcon#about to read 6, iclass 3, count 2 2006.285.09:25:57.55#ibcon#read 6, iclass 3, count 2 2006.285.09:25:57.55#ibcon#end of sib2, iclass 3, count 2 2006.285.09:25:57.55#ibcon#*mode == 0, iclass 3, count 2 2006.285.09:25:57.55#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.09:25:57.55#ibcon#[27=AT03-04\r\n] 2006.285.09:25:57.55#ibcon#*before write, iclass 3, count 2 2006.285.09:25:57.55#ibcon#enter sib2, iclass 3, count 2 2006.285.09:25:57.55#ibcon#flushed, iclass 3, count 2 2006.285.09:25:57.55#ibcon#about to write, iclass 3, count 2 2006.285.09:25:57.55#ibcon#wrote, iclass 3, count 2 2006.285.09:25:57.55#ibcon#about to read 3, iclass 3, count 2 2006.285.09:25:57.58#ibcon#read 3, iclass 3, count 2 2006.285.09:25:57.58#ibcon#about to read 4, iclass 3, count 2 2006.285.09:25:57.58#ibcon#read 4, iclass 3, count 2 2006.285.09:25:57.58#ibcon#about to read 5, iclass 3, count 2 2006.285.09:25:57.58#ibcon#read 5, iclass 3, count 2 2006.285.09:25:57.58#ibcon#about to read 6, iclass 3, count 2 2006.285.09:25:57.58#ibcon#read 6, iclass 3, count 2 2006.285.09:25:57.58#ibcon#end of sib2, iclass 3, count 2 2006.285.09:25:57.58#ibcon#*after write, iclass 3, count 2 2006.285.09:25:57.58#ibcon#*before return 0, iclass 3, count 2 2006.285.09:25:57.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:25:57.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:25:57.58#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.09:25:57.58#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:57.58#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:25:57.70#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:25:57.70#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:25:57.70#ibcon#enter wrdev, iclass 3, count 0 2006.285.09:25:57.70#ibcon#first serial, iclass 3, count 0 2006.285.09:25:57.70#ibcon#enter sib2, iclass 3, count 0 2006.285.09:25:57.70#ibcon#flushed, iclass 3, count 0 2006.285.09:25:57.70#ibcon#about to write, iclass 3, count 0 2006.285.09:25:57.70#ibcon#wrote, iclass 3, count 0 2006.285.09:25:57.70#ibcon#about to read 3, iclass 3, count 0 2006.285.09:25:57.72#ibcon#read 3, iclass 3, count 0 2006.285.09:25:57.72#ibcon#about to read 4, iclass 3, count 0 2006.285.09:25:57.72#ibcon#read 4, iclass 3, count 0 2006.285.09:25:57.72#ibcon#about to read 5, iclass 3, count 0 2006.285.09:25:57.72#ibcon#read 5, iclass 3, count 0 2006.285.09:25:57.72#ibcon#about to read 6, iclass 3, count 0 2006.285.09:25:57.72#ibcon#read 6, iclass 3, count 0 2006.285.09:25:57.72#ibcon#end of sib2, iclass 3, count 0 2006.285.09:25:57.72#ibcon#*mode == 0, iclass 3, count 0 2006.285.09:25:57.72#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.09:25:57.72#ibcon#[27=USB\r\n] 2006.285.09:25:57.72#ibcon#*before write, iclass 3, count 0 2006.285.09:25:57.72#ibcon#enter sib2, iclass 3, count 0 2006.285.09:25:57.72#ibcon#flushed, iclass 3, count 0 2006.285.09:25:57.72#ibcon#about to write, iclass 3, count 0 2006.285.09:25:57.72#ibcon#wrote, iclass 3, count 0 2006.285.09:25:57.72#ibcon#about to read 3, iclass 3, count 0 2006.285.09:25:57.75#ibcon#read 3, iclass 3, count 0 2006.285.09:25:57.75#ibcon#about to read 4, iclass 3, count 0 2006.285.09:25:57.75#ibcon#read 4, iclass 3, count 0 2006.285.09:25:57.75#ibcon#about to read 5, iclass 3, count 0 2006.285.09:25:57.75#ibcon#read 5, iclass 3, count 0 2006.285.09:25:57.75#ibcon#about to read 6, iclass 3, count 0 2006.285.09:25:57.75#ibcon#read 6, iclass 3, count 0 2006.285.09:25:57.75#ibcon#end of sib2, iclass 3, count 0 2006.285.09:25:57.75#ibcon#*after write, iclass 3, count 0 2006.285.09:25:57.75#ibcon#*before return 0, iclass 3, count 0 2006.285.09:25:57.75#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:25:57.75#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:25:57.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.09:25:57.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.09:25:57.75$vck44/vblo=4,679.99 2006.285.09:25:57.75#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.09:25:57.75#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.09:25:57.75#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:57.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:25:57.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:25:57.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:25:57.75#ibcon#enter wrdev, iclass 5, count 0 2006.285.09:25:57.75#ibcon#first serial, iclass 5, count 0 2006.285.09:25:57.75#ibcon#enter sib2, iclass 5, count 0 2006.285.09:25:57.75#ibcon#flushed, iclass 5, count 0 2006.285.09:25:57.75#ibcon#about to write, iclass 5, count 0 2006.285.09:25:57.75#ibcon#wrote, iclass 5, count 0 2006.285.09:25:57.75#ibcon#about to read 3, iclass 5, count 0 2006.285.09:25:57.77#ibcon#read 3, iclass 5, count 0 2006.285.09:25:57.77#ibcon#about to read 4, iclass 5, count 0 2006.285.09:25:57.77#ibcon#read 4, iclass 5, count 0 2006.285.09:25:57.77#ibcon#about to read 5, iclass 5, count 0 2006.285.09:25:57.77#ibcon#read 5, iclass 5, count 0 2006.285.09:25:57.77#ibcon#about to read 6, iclass 5, count 0 2006.285.09:25:57.77#ibcon#read 6, iclass 5, count 0 2006.285.09:25:57.77#ibcon#end of sib2, iclass 5, count 0 2006.285.09:25:57.77#ibcon#*mode == 0, iclass 5, count 0 2006.285.09:25:57.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.09:25:57.77#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:25:57.77#ibcon#*before write, iclass 5, count 0 2006.285.09:25:57.77#ibcon#enter sib2, iclass 5, count 0 2006.285.09:25:57.77#ibcon#flushed, iclass 5, count 0 2006.285.09:25:57.77#ibcon#about to write, iclass 5, count 0 2006.285.09:25:57.77#ibcon#wrote, iclass 5, count 0 2006.285.09:25:57.77#ibcon#about to read 3, iclass 5, count 0 2006.285.09:25:57.81#ibcon#read 3, iclass 5, count 0 2006.285.09:25:57.81#ibcon#about to read 4, iclass 5, count 0 2006.285.09:25:57.81#ibcon#read 4, iclass 5, count 0 2006.285.09:25:57.81#ibcon#about to read 5, iclass 5, count 0 2006.285.09:25:57.81#ibcon#read 5, iclass 5, count 0 2006.285.09:25:57.81#ibcon#about to read 6, iclass 5, count 0 2006.285.09:25:57.81#ibcon#read 6, iclass 5, count 0 2006.285.09:25:57.81#ibcon#end of sib2, iclass 5, count 0 2006.285.09:25:57.81#ibcon#*after write, iclass 5, count 0 2006.285.09:25:57.81#ibcon#*before return 0, iclass 5, count 0 2006.285.09:25:57.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:25:57.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:25:57.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.09:25:57.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.09:25:57.81$vck44/vb=4,5 2006.285.09:25:57.81#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.09:25:57.81#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.09:25:57.81#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:57.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:25:57.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:25:57.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:25:57.87#ibcon#enter wrdev, iclass 7, count 2 2006.285.09:25:57.87#ibcon#first serial, iclass 7, count 2 2006.285.09:25:57.87#ibcon#enter sib2, iclass 7, count 2 2006.285.09:25:57.87#ibcon#flushed, iclass 7, count 2 2006.285.09:25:57.87#ibcon#about to write, iclass 7, count 2 2006.285.09:25:57.87#ibcon#wrote, iclass 7, count 2 2006.285.09:25:57.87#ibcon#about to read 3, iclass 7, count 2 2006.285.09:25:57.89#ibcon#read 3, iclass 7, count 2 2006.285.09:25:57.89#ibcon#about to read 4, iclass 7, count 2 2006.285.09:25:57.89#ibcon#read 4, iclass 7, count 2 2006.285.09:25:57.89#ibcon#about to read 5, iclass 7, count 2 2006.285.09:25:57.89#ibcon#read 5, iclass 7, count 2 2006.285.09:25:57.89#ibcon#about to read 6, iclass 7, count 2 2006.285.09:25:57.89#ibcon#read 6, iclass 7, count 2 2006.285.09:25:57.89#ibcon#end of sib2, iclass 7, count 2 2006.285.09:25:57.89#ibcon#*mode == 0, iclass 7, count 2 2006.285.09:25:57.89#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.09:25:57.89#ibcon#[27=AT04-05\r\n] 2006.285.09:25:57.89#ibcon#*before write, iclass 7, count 2 2006.285.09:25:57.89#ibcon#enter sib2, iclass 7, count 2 2006.285.09:25:57.89#ibcon#flushed, iclass 7, count 2 2006.285.09:25:57.89#ibcon#about to write, iclass 7, count 2 2006.285.09:25:57.89#ibcon#wrote, iclass 7, count 2 2006.285.09:25:57.89#ibcon#about to read 3, iclass 7, count 2 2006.285.09:25:57.92#ibcon#read 3, iclass 7, count 2 2006.285.09:25:57.92#ibcon#about to read 4, iclass 7, count 2 2006.285.09:25:57.92#ibcon#read 4, iclass 7, count 2 2006.285.09:25:57.92#ibcon#about to read 5, iclass 7, count 2 2006.285.09:25:57.92#ibcon#read 5, iclass 7, count 2 2006.285.09:25:57.92#ibcon#about to read 6, iclass 7, count 2 2006.285.09:25:57.92#ibcon#read 6, iclass 7, count 2 2006.285.09:25:57.92#ibcon#end of sib2, iclass 7, count 2 2006.285.09:25:57.92#ibcon#*after write, iclass 7, count 2 2006.285.09:25:57.92#ibcon#*before return 0, iclass 7, count 2 2006.285.09:25:57.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:25:57.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:25:57.92#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.09:25:57.92#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:57.92#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:25:58.04#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:25:58.04#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:25:58.04#ibcon#enter wrdev, iclass 7, count 0 2006.285.09:25:58.04#ibcon#first serial, iclass 7, count 0 2006.285.09:25:58.04#ibcon#enter sib2, iclass 7, count 0 2006.285.09:25:58.04#ibcon#flushed, iclass 7, count 0 2006.285.09:25:58.04#ibcon#about to write, iclass 7, count 0 2006.285.09:25:58.04#ibcon#wrote, iclass 7, count 0 2006.285.09:25:58.04#ibcon#about to read 3, iclass 7, count 0 2006.285.09:25:58.06#ibcon#read 3, iclass 7, count 0 2006.285.09:25:58.06#ibcon#about to read 4, iclass 7, count 0 2006.285.09:25:58.06#ibcon#read 4, iclass 7, count 0 2006.285.09:25:58.06#ibcon#about to read 5, iclass 7, count 0 2006.285.09:25:58.06#ibcon#read 5, iclass 7, count 0 2006.285.09:25:58.06#ibcon#about to read 6, iclass 7, count 0 2006.285.09:25:58.06#ibcon#read 6, iclass 7, count 0 2006.285.09:25:58.06#ibcon#end of sib2, iclass 7, count 0 2006.285.09:25:58.06#ibcon#*mode == 0, iclass 7, count 0 2006.285.09:25:58.06#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.09:25:58.06#ibcon#[27=USB\r\n] 2006.285.09:25:58.06#ibcon#*before write, iclass 7, count 0 2006.285.09:25:58.06#ibcon#enter sib2, iclass 7, count 0 2006.285.09:25:58.06#ibcon#flushed, iclass 7, count 0 2006.285.09:25:58.06#ibcon#about to write, iclass 7, count 0 2006.285.09:25:58.06#ibcon#wrote, iclass 7, count 0 2006.285.09:25:58.06#ibcon#about to read 3, iclass 7, count 0 2006.285.09:25:58.09#ibcon#read 3, iclass 7, count 0 2006.285.09:25:58.09#ibcon#about to read 4, iclass 7, count 0 2006.285.09:25:58.09#ibcon#read 4, iclass 7, count 0 2006.285.09:25:58.09#ibcon#about to read 5, iclass 7, count 0 2006.285.09:25:58.09#ibcon#read 5, iclass 7, count 0 2006.285.09:25:58.09#ibcon#about to read 6, iclass 7, count 0 2006.285.09:25:58.09#ibcon#read 6, iclass 7, count 0 2006.285.09:25:58.09#ibcon#end of sib2, iclass 7, count 0 2006.285.09:25:58.09#ibcon#*after write, iclass 7, count 0 2006.285.09:25:58.09#ibcon#*before return 0, iclass 7, count 0 2006.285.09:25:58.09#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:25:58.09#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:25:58.09#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.09:25:58.09#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.09:25:58.09$vck44/vblo=5,709.99 2006.285.09:25:58.09#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.09:25:58.09#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.09:25:58.09#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:58.09#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:25:58.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:25:58.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:25:58.09#ibcon#enter wrdev, iclass 11, count 0 2006.285.09:25:58.09#ibcon#first serial, iclass 11, count 0 2006.285.09:25:58.09#ibcon#enter sib2, iclass 11, count 0 2006.285.09:25:58.09#ibcon#flushed, iclass 11, count 0 2006.285.09:25:58.09#ibcon#about to write, iclass 11, count 0 2006.285.09:25:58.09#ibcon#wrote, iclass 11, count 0 2006.285.09:25:58.09#ibcon#about to read 3, iclass 11, count 0 2006.285.09:25:58.11#ibcon#read 3, iclass 11, count 0 2006.285.09:25:58.11#ibcon#about to read 4, iclass 11, count 0 2006.285.09:25:58.11#ibcon#read 4, iclass 11, count 0 2006.285.09:25:58.11#ibcon#about to read 5, iclass 11, count 0 2006.285.09:25:58.11#ibcon#read 5, iclass 11, count 0 2006.285.09:25:58.11#ibcon#about to read 6, iclass 11, count 0 2006.285.09:25:58.11#ibcon#read 6, iclass 11, count 0 2006.285.09:25:58.11#ibcon#end of sib2, iclass 11, count 0 2006.285.09:25:58.11#ibcon#*mode == 0, iclass 11, count 0 2006.285.09:25:58.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.09:25:58.11#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:25:58.11#ibcon#*before write, iclass 11, count 0 2006.285.09:25:58.11#ibcon#enter sib2, iclass 11, count 0 2006.285.09:25:58.11#ibcon#flushed, iclass 11, count 0 2006.285.09:25:58.11#ibcon#about to write, iclass 11, count 0 2006.285.09:25:58.11#ibcon#wrote, iclass 11, count 0 2006.285.09:25:58.11#ibcon#about to read 3, iclass 11, count 0 2006.285.09:25:58.15#ibcon#read 3, iclass 11, count 0 2006.285.09:25:58.15#ibcon#about to read 4, iclass 11, count 0 2006.285.09:25:58.15#ibcon#read 4, iclass 11, count 0 2006.285.09:25:58.15#ibcon#about to read 5, iclass 11, count 0 2006.285.09:25:58.15#ibcon#read 5, iclass 11, count 0 2006.285.09:25:58.15#ibcon#about to read 6, iclass 11, count 0 2006.285.09:25:58.15#ibcon#read 6, iclass 11, count 0 2006.285.09:25:58.15#ibcon#end of sib2, iclass 11, count 0 2006.285.09:25:58.15#ibcon#*after write, iclass 11, count 0 2006.285.09:25:58.15#ibcon#*before return 0, iclass 11, count 0 2006.285.09:25:58.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:25:58.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:25:58.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.09:25:58.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.09:25:58.15$vck44/vb=5,4 2006.285.09:25:58.15#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.09:25:58.15#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.09:25:58.15#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:58.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:25:58.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:25:58.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:25:58.21#ibcon#enter wrdev, iclass 13, count 2 2006.285.09:25:58.21#ibcon#first serial, iclass 13, count 2 2006.285.09:25:58.21#ibcon#enter sib2, iclass 13, count 2 2006.285.09:25:58.21#ibcon#flushed, iclass 13, count 2 2006.285.09:25:58.21#ibcon#about to write, iclass 13, count 2 2006.285.09:25:58.21#ibcon#wrote, iclass 13, count 2 2006.285.09:25:58.21#ibcon#about to read 3, iclass 13, count 2 2006.285.09:25:58.23#ibcon#read 3, iclass 13, count 2 2006.285.09:25:58.23#ibcon#about to read 4, iclass 13, count 2 2006.285.09:25:58.23#ibcon#read 4, iclass 13, count 2 2006.285.09:25:58.23#ibcon#about to read 5, iclass 13, count 2 2006.285.09:25:58.23#ibcon#read 5, iclass 13, count 2 2006.285.09:25:58.23#ibcon#about to read 6, iclass 13, count 2 2006.285.09:25:58.23#ibcon#read 6, iclass 13, count 2 2006.285.09:25:58.23#ibcon#end of sib2, iclass 13, count 2 2006.285.09:25:58.23#ibcon#*mode == 0, iclass 13, count 2 2006.285.09:25:58.23#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.09:25:58.23#ibcon#[27=AT05-04\r\n] 2006.285.09:25:58.23#ibcon#*before write, iclass 13, count 2 2006.285.09:25:58.23#ibcon#enter sib2, iclass 13, count 2 2006.285.09:25:58.23#ibcon#flushed, iclass 13, count 2 2006.285.09:25:58.23#ibcon#about to write, iclass 13, count 2 2006.285.09:25:58.23#ibcon#wrote, iclass 13, count 2 2006.285.09:25:58.23#ibcon#about to read 3, iclass 13, count 2 2006.285.09:25:58.26#ibcon#read 3, iclass 13, count 2 2006.285.09:25:58.26#ibcon#about to read 4, iclass 13, count 2 2006.285.09:25:58.26#ibcon#read 4, iclass 13, count 2 2006.285.09:25:58.26#ibcon#about to read 5, iclass 13, count 2 2006.285.09:25:58.26#ibcon#read 5, iclass 13, count 2 2006.285.09:25:58.26#ibcon#about to read 6, iclass 13, count 2 2006.285.09:25:58.26#ibcon#read 6, iclass 13, count 2 2006.285.09:25:58.26#ibcon#end of sib2, iclass 13, count 2 2006.285.09:25:58.26#ibcon#*after write, iclass 13, count 2 2006.285.09:25:58.26#ibcon#*before return 0, iclass 13, count 2 2006.285.09:25:58.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:25:58.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:25:58.26#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.09:25:58.26#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:58.26#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:25:58.38#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:25:58.38#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:25:58.38#ibcon#enter wrdev, iclass 13, count 0 2006.285.09:25:58.38#ibcon#first serial, iclass 13, count 0 2006.285.09:25:58.38#ibcon#enter sib2, iclass 13, count 0 2006.285.09:25:58.38#ibcon#flushed, iclass 13, count 0 2006.285.09:25:58.38#ibcon#about to write, iclass 13, count 0 2006.285.09:25:58.38#ibcon#wrote, iclass 13, count 0 2006.285.09:25:58.38#ibcon#about to read 3, iclass 13, count 0 2006.285.09:25:58.40#ibcon#read 3, iclass 13, count 0 2006.285.09:25:58.40#ibcon#about to read 4, iclass 13, count 0 2006.285.09:25:58.40#ibcon#read 4, iclass 13, count 0 2006.285.09:25:58.40#ibcon#about to read 5, iclass 13, count 0 2006.285.09:25:58.40#ibcon#read 5, iclass 13, count 0 2006.285.09:25:58.40#ibcon#about to read 6, iclass 13, count 0 2006.285.09:25:58.40#ibcon#read 6, iclass 13, count 0 2006.285.09:25:58.40#ibcon#end of sib2, iclass 13, count 0 2006.285.09:25:58.40#ibcon#*mode == 0, iclass 13, count 0 2006.285.09:25:58.40#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.09:25:58.40#ibcon#[27=USB\r\n] 2006.285.09:25:58.40#ibcon#*before write, iclass 13, count 0 2006.285.09:25:58.40#ibcon#enter sib2, iclass 13, count 0 2006.285.09:25:58.40#ibcon#flushed, iclass 13, count 0 2006.285.09:25:58.40#ibcon#about to write, iclass 13, count 0 2006.285.09:25:58.40#ibcon#wrote, iclass 13, count 0 2006.285.09:25:58.40#ibcon#about to read 3, iclass 13, count 0 2006.285.09:25:58.43#ibcon#read 3, iclass 13, count 0 2006.285.09:25:58.43#ibcon#about to read 4, iclass 13, count 0 2006.285.09:25:58.43#ibcon#read 4, iclass 13, count 0 2006.285.09:25:58.43#ibcon#about to read 5, iclass 13, count 0 2006.285.09:25:58.43#ibcon#read 5, iclass 13, count 0 2006.285.09:25:58.43#ibcon#about to read 6, iclass 13, count 0 2006.285.09:25:58.43#ibcon#read 6, iclass 13, count 0 2006.285.09:25:58.43#ibcon#end of sib2, iclass 13, count 0 2006.285.09:25:58.43#ibcon#*after write, iclass 13, count 0 2006.285.09:25:58.43#ibcon#*before return 0, iclass 13, count 0 2006.285.09:25:58.43#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:25:58.43#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:25:58.43#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.09:25:58.43#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.09:25:58.43$vck44/vblo=6,719.99 2006.285.09:25:58.43#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.09:25:58.43#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.09:25:58.43#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:58.43#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:25:58.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:25:58.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:25:58.43#ibcon#enter wrdev, iclass 15, count 0 2006.285.09:25:58.43#ibcon#first serial, iclass 15, count 0 2006.285.09:25:58.43#ibcon#enter sib2, iclass 15, count 0 2006.285.09:25:58.43#ibcon#flushed, iclass 15, count 0 2006.285.09:25:58.43#ibcon#about to write, iclass 15, count 0 2006.285.09:25:58.43#ibcon#wrote, iclass 15, count 0 2006.285.09:25:58.43#ibcon#about to read 3, iclass 15, count 0 2006.285.09:25:58.45#ibcon#read 3, iclass 15, count 0 2006.285.09:25:58.45#ibcon#about to read 4, iclass 15, count 0 2006.285.09:25:58.45#ibcon#read 4, iclass 15, count 0 2006.285.09:25:58.45#ibcon#about to read 5, iclass 15, count 0 2006.285.09:25:58.45#ibcon#read 5, iclass 15, count 0 2006.285.09:25:58.45#ibcon#about to read 6, iclass 15, count 0 2006.285.09:25:58.45#ibcon#read 6, iclass 15, count 0 2006.285.09:25:58.45#ibcon#end of sib2, iclass 15, count 0 2006.285.09:25:58.45#ibcon#*mode == 0, iclass 15, count 0 2006.285.09:25:58.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.09:25:58.45#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:25:58.45#ibcon#*before write, iclass 15, count 0 2006.285.09:25:58.45#ibcon#enter sib2, iclass 15, count 0 2006.285.09:25:58.45#ibcon#flushed, iclass 15, count 0 2006.285.09:25:58.45#ibcon#about to write, iclass 15, count 0 2006.285.09:25:58.45#ibcon#wrote, iclass 15, count 0 2006.285.09:25:58.45#ibcon#about to read 3, iclass 15, count 0 2006.285.09:25:58.49#ibcon#read 3, iclass 15, count 0 2006.285.09:25:58.49#ibcon#about to read 4, iclass 15, count 0 2006.285.09:25:58.49#ibcon#read 4, iclass 15, count 0 2006.285.09:25:58.49#ibcon#about to read 5, iclass 15, count 0 2006.285.09:25:58.49#ibcon#read 5, iclass 15, count 0 2006.285.09:25:58.49#ibcon#about to read 6, iclass 15, count 0 2006.285.09:25:58.49#ibcon#read 6, iclass 15, count 0 2006.285.09:25:58.49#ibcon#end of sib2, iclass 15, count 0 2006.285.09:25:58.49#ibcon#*after write, iclass 15, count 0 2006.285.09:25:58.49#ibcon#*before return 0, iclass 15, count 0 2006.285.09:25:58.49#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:25:58.49#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:25:58.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.09:25:58.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.09:25:58.49$vck44/vb=6,3 2006.285.09:25:58.49#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.09:25:58.49#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.09:25:58.49#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:58.49#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:25:58.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:25:58.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:25:58.55#ibcon#enter wrdev, iclass 17, count 2 2006.285.09:25:58.55#ibcon#first serial, iclass 17, count 2 2006.285.09:25:58.55#ibcon#enter sib2, iclass 17, count 2 2006.285.09:25:58.55#ibcon#flushed, iclass 17, count 2 2006.285.09:25:58.55#ibcon#about to write, iclass 17, count 2 2006.285.09:25:58.55#ibcon#wrote, iclass 17, count 2 2006.285.09:25:58.55#ibcon#about to read 3, iclass 17, count 2 2006.285.09:25:58.57#ibcon#read 3, iclass 17, count 2 2006.285.09:25:58.57#ibcon#about to read 4, iclass 17, count 2 2006.285.09:25:58.57#ibcon#read 4, iclass 17, count 2 2006.285.09:25:58.57#ibcon#about to read 5, iclass 17, count 2 2006.285.09:25:58.57#ibcon#read 5, iclass 17, count 2 2006.285.09:25:58.57#ibcon#about to read 6, iclass 17, count 2 2006.285.09:25:58.57#ibcon#read 6, iclass 17, count 2 2006.285.09:25:58.57#ibcon#end of sib2, iclass 17, count 2 2006.285.09:25:58.57#ibcon#*mode == 0, iclass 17, count 2 2006.285.09:25:58.57#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.09:25:58.57#ibcon#[27=AT06-03\r\n] 2006.285.09:25:58.57#ibcon#*before write, iclass 17, count 2 2006.285.09:25:58.57#ibcon#enter sib2, iclass 17, count 2 2006.285.09:25:58.57#ibcon#flushed, iclass 17, count 2 2006.285.09:25:58.57#ibcon#about to write, iclass 17, count 2 2006.285.09:25:58.57#ibcon#wrote, iclass 17, count 2 2006.285.09:25:58.57#ibcon#about to read 3, iclass 17, count 2 2006.285.09:25:58.60#ibcon#read 3, iclass 17, count 2 2006.285.09:25:58.60#ibcon#about to read 4, iclass 17, count 2 2006.285.09:25:58.60#ibcon#read 4, iclass 17, count 2 2006.285.09:25:58.60#ibcon#about to read 5, iclass 17, count 2 2006.285.09:25:58.60#ibcon#read 5, iclass 17, count 2 2006.285.09:25:58.60#ibcon#about to read 6, iclass 17, count 2 2006.285.09:25:58.60#ibcon#read 6, iclass 17, count 2 2006.285.09:25:58.60#ibcon#end of sib2, iclass 17, count 2 2006.285.09:25:58.60#ibcon#*after write, iclass 17, count 2 2006.285.09:25:58.60#ibcon#*before return 0, iclass 17, count 2 2006.285.09:25:58.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:25:58.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:25:58.60#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.09:25:58.60#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:58.60#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:25:58.72#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:25:58.72#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:25:58.72#ibcon#enter wrdev, iclass 17, count 0 2006.285.09:25:58.72#ibcon#first serial, iclass 17, count 0 2006.285.09:25:58.72#ibcon#enter sib2, iclass 17, count 0 2006.285.09:25:58.72#ibcon#flushed, iclass 17, count 0 2006.285.09:25:58.72#ibcon#about to write, iclass 17, count 0 2006.285.09:25:58.72#ibcon#wrote, iclass 17, count 0 2006.285.09:25:58.72#ibcon#about to read 3, iclass 17, count 0 2006.285.09:25:58.74#ibcon#read 3, iclass 17, count 0 2006.285.09:25:58.74#ibcon#about to read 4, iclass 17, count 0 2006.285.09:25:58.74#ibcon#read 4, iclass 17, count 0 2006.285.09:25:58.74#ibcon#about to read 5, iclass 17, count 0 2006.285.09:25:58.74#ibcon#read 5, iclass 17, count 0 2006.285.09:25:58.74#ibcon#about to read 6, iclass 17, count 0 2006.285.09:25:58.74#ibcon#read 6, iclass 17, count 0 2006.285.09:25:58.74#ibcon#end of sib2, iclass 17, count 0 2006.285.09:25:58.74#ibcon#*mode == 0, iclass 17, count 0 2006.285.09:25:58.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.09:25:58.74#ibcon#[27=USB\r\n] 2006.285.09:25:58.74#ibcon#*before write, iclass 17, count 0 2006.285.09:25:58.74#ibcon#enter sib2, iclass 17, count 0 2006.285.09:25:58.74#ibcon#flushed, iclass 17, count 0 2006.285.09:25:58.74#ibcon#about to write, iclass 17, count 0 2006.285.09:25:58.74#ibcon#wrote, iclass 17, count 0 2006.285.09:25:58.74#ibcon#about to read 3, iclass 17, count 0 2006.285.09:25:58.77#ibcon#read 3, iclass 17, count 0 2006.285.09:25:58.77#ibcon#about to read 4, iclass 17, count 0 2006.285.09:25:58.77#ibcon#read 4, iclass 17, count 0 2006.285.09:25:58.77#ibcon#about to read 5, iclass 17, count 0 2006.285.09:25:58.77#ibcon#read 5, iclass 17, count 0 2006.285.09:25:58.77#ibcon#about to read 6, iclass 17, count 0 2006.285.09:25:58.77#ibcon#read 6, iclass 17, count 0 2006.285.09:25:58.77#ibcon#end of sib2, iclass 17, count 0 2006.285.09:25:58.77#ibcon#*after write, iclass 17, count 0 2006.285.09:25:58.77#ibcon#*before return 0, iclass 17, count 0 2006.285.09:25:58.77#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:25:58.77#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:25:58.77#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.09:25:58.77#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.09:25:58.77$vck44/vblo=7,734.99 2006.285.09:25:58.77#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.09:25:58.77#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.09:25:58.77#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:58.77#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:25:58.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:25:58.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:25:58.77#ibcon#enter wrdev, iclass 19, count 0 2006.285.09:25:58.77#ibcon#first serial, iclass 19, count 0 2006.285.09:25:58.77#ibcon#enter sib2, iclass 19, count 0 2006.285.09:25:58.77#ibcon#flushed, iclass 19, count 0 2006.285.09:25:58.77#ibcon#about to write, iclass 19, count 0 2006.285.09:25:58.77#ibcon#wrote, iclass 19, count 0 2006.285.09:25:58.77#ibcon#about to read 3, iclass 19, count 0 2006.285.09:25:58.79#ibcon#read 3, iclass 19, count 0 2006.285.09:25:58.79#ibcon#about to read 4, iclass 19, count 0 2006.285.09:25:58.79#ibcon#read 4, iclass 19, count 0 2006.285.09:25:58.79#ibcon#about to read 5, iclass 19, count 0 2006.285.09:25:58.79#ibcon#read 5, iclass 19, count 0 2006.285.09:25:58.79#ibcon#about to read 6, iclass 19, count 0 2006.285.09:25:58.79#ibcon#read 6, iclass 19, count 0 2006.285.09:25:58.79#ibcon#end of sib2, iclass 19, count 0 2006.285.09:25:58.79#ibcon#*mode == 0, iclass 19, count 0 2006.285.09:25:58.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.09:25:58.79#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:25:58.79#ibcon#*before write, iclass 19, count 0 2006.285.09:25:58.79#ibcon#enter sib2, iclass 19, count 0 2006.285.09:25:58.79#ibcon#flushed, iclass 19, count 0 2006.285.09:25:58.79#ibcon#about to write, iclass 19, count 0 2006.285.09:25:58.79#ibcon#wrote, iclass 19, count 0 2006.285.09:25:58.79#ibcon#about to read 3, iclass 19, count 0 2006.285.09:25:58.83#ibcon#read 3, iclass 19, count 0 2006.285.09:25:58.83#ibcon#about to read 4, iclass 19, count 0 2006.285.09:25:58.83#ibcon#read 4, iclass 19, count 0 2006.285.09:25:58.83#ibcon#about to read 5, iclass 19, count 0 2006.285.09:25:58.83#ibcon#read 5, iclass 19, count 0 2006.285.09:25:58.83#ibcon#about to read 6, iclass 19, count 0 2006.285.09:25:58.83#ibcon#read 6, iclass 19, count 0 2006.285.09:25:58.83#ibcon#end of sib2, iclass 19, count 0 2006.285.09:25:58.83#ibcon#*after write, iclass 19, count 0 2006.285.09:25:58.83#ibcon#*before return 0, iclass 19, count 0 2006.285.09:25:58.83#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:25:58.83#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:25:58.83#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.09:25:58.83#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.09:25:58.83$vck44/vb=7,4 2006.285.09:25:58.83#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.09:25:58.83#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.09:25:58.83#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:58.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:25:58.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:25:58.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:25:58.89#ibcon#enter wrdev, iclass 21, count 2 2006.285.09:25:58.89#ibcon#first serial, iclass 21, count 2 2006.285.09:25:58.89#ibcon#enter sib2, iclass 21, count 2 2006.285.09:25:58.89#ibcon#flushed, iclass 21, count 2 2006.285.09:25:58.89#ibcon#about to write, iclass 21, count 2 2006.285.09:25:58.89#ibcon#wrote, iclass 21, count 2 2006.285.09:25:58.89#ibcon#about to read 3, iclass 21, count 2 2006.285.09:25:58.90#ibcon#read 3, iclass 21, count 2 2006.285.09:25:58.91#ibcon#about to read 4, iclass 21, count 2 2006.285.09:25:58.91#ibcon#read 4, iclass 21, count 2 2006.285.09:25:58.91#ibcon#about to read 5, iclass 21, count 2 2006.285.09:25:58.91#ibcon#read 5, iclass 21, count 2 2006.285.09:25:58.91#ibcon#about to read 6, iclass 21, count 2 2006.285.09:25:58.91#ibcon#read 6, iclass 21, count 2 2006.285.09:25:58.91#ibcon#end of sib2, iclass 21, count 2 2006.285.09:25:58.91#ibcon#*mode == 0, iclass 21, count 2 2006.285.09:25:58.91#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.09:25:58.91#ibcon#[27=AT07-04\r\n] 2006.285.09:25:58.91#ibcon#*before write, iclass 21, count 2 2006.285.09:25:58.91#ibcon#enter sib2, iclass 21, count 2 2006.285.09:25:58.91#ibcon#flushed, iclass 21, count 2 2006.285.09:25:58.91#ibcon#about to write, iclass 21, count 2 2006.285.09:25:58.91#ibcon#wrote, iclass 21, count 2 2006.285.09:25:58.91#ibcon#about to read 3, iclass 21, count 2 2006.285.09:25:58.94#ibcon#read 3, iclass 21, count 2 2006.285.09:25:58.94#ibcon#about to read 4, iclass 21, count 2 2006.285.09:25:58.94#ibcon#read 4, iclass 21, count 2 2006.285.09:25:58.94#ibcon#about to read 5, iclass 21, count 2 2006.285.09:25:58.94#ibcon#read 5, iclass 21, count 2 2006.285.09:25:58.94#ibcon#about to read 6, iclass 21, count 2 2006.285.09:25:58.94#ibcon#read 6, iclass 21, count 2 2006.285.09:25:58.94#ibcon#end of sib2, iclass 21, count 2 2006.285.09:25:58.94#ibcon#*after write, iclass 21, count 2 2006.285.09:25:58.94#ibcon#*before return 0, iclass 21, count 2 2006.285.09:25:58.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:25:58.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:25:58.94#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.09:25:58.94#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:58.94#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:25:59.06#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:25:59.06#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:25:59.06#ibcon#enter wrdev, iclass 21, count 0 2006.285.09:25:59.06#ibcon#first serial, iclass 21, count 0 2006.285.09:25:59.06#ibcon#enter sib2, iclass 21, count 0 2006.285.09:25:59.06#ibcon#flushed, iclass 21, count 0 2006.285.09:25:59.06#ibcon#about to write, iclass 21, count 0 2006.285.09:25:59.06#ibcon#wrote, iclass 21, count 0 2006.285.09:25:59.06#ibcon#about to read 3, iclass 21, count 0 2006.285.09:25:59.08#ibcon#read 3, iclass 21, count 0 2006.285.09:25:59.08#ibcon#about to read 4, iclass 21, count 0 2006.285.09:25:59.08#ibcon#read 4, iclass 21, count 0 2006.285.09:25:59.08#ibcon#about to read 5, iclass 21, count 0 2006.285.09:25:59.08#ibcon#read 5, iclass 21, count 0 2006.285.09:25:59.08#ibcon#about to read 6, iclass 21, count 0 2006.285.09:25:59.08#ibcon#read 6, iclass 21, count 0 2006.285.09:25:59.08#ibcon#end of sib2, iclass 21, count 0 2006.285.09:25:59.08#ibcon#*mode == 0, iclass 21, count 0 2006.285.09:25:59.08#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.09:25:59.08#ibcon#[27=USB\r\n] 2006.285.09:25:59.08#ibcon#*before write, iclass 21, count 0 2006.285.09:25:59.08#ibcon#enter sib2, iclass 21, count 0 2006.285.09:25:59.08#ibcon#flushed, iclass 21, count 0 2006.285.09:25:59.08#ibcon#about to write, iclass 21, count 0 2006.285.09:25:59.08#ibcon#wrote, iclass 21, count 0 2006.285.09:25:59.08#ibcon#about to read 3, iclass 21, count 0 2006.285.09:25:59.11#ibcon#read 3, iclass 21, count 0 2006.285.09:25:59.11#ibcon#about to read 4, iclass 21, count 0 2006.285.09:25:59.11#ibcon#read 4, iclass 21, count 0 2006.285.09:25:59.11#ibcon#about to read 5, iclass 21, count 0 2006.285.09:25:59.11#ibcon#read 5, iclass 21, count 0 2006.285.09:25:59.11#ibcon#about to read 6, iclass 21, count 0 2006.285.09:25:59.11#ibcon#read 6, iclass 21, count 0 2006.285.09:25:59.11#ibcon#end of sib2, iclass 21, count 0 2006.285.09:25:59.11#ibcon#*after write, iclass 21, count 0 2006.285.09:25:59.11#ibcon#*before return 0, iclass 21, count 0 2006.285.09:25:59.11#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:25:59.11#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:25:59.11#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.09:25:59.11#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.09:25:59.11$vck44/vblo=8,744.99 2006.285.09:25:59.11#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.09:25:59.11#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.09:25:59.11#ibcon#ireg 17 cls_cnt 0 2006.285.09:25:59.11#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:25:59.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:25:59.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:25:59.11#ibcon#enter wrdev, iclass 23, count 0 2006.285.09:25:59.11#ibcon#first serial, iclass 23, count 0 2006.285.09:25:59.11#ibcon#enter sib2, iclass 23, count 0 2006.285.09:25:59.11#ibcon#flushed, iclass 23, count 0 2006.285.09:25:59.11#ibcon#about to write, iclass 23, count 0 2006.285.09:25:59.11#ibcon#wrote, iclass 23, count 0 2006.285.09:25:59.11#ibcon#about to read 3, iclass 23, count 0 2006.285.09:25:59.13#ibcon#read 3, iclass 23, count 0 2006.285.09:25:59.13#ibcon#about to read 4, iclass 23, count 0 2006.285.09:25:59.13#ibcon#read 4, iclass 23, count 0 2006.285.09:25:59.13#ibcon#about to read 5, iclass 23, count 0 2006.285.09:25:59.13#ibcon#read 5, iclass 23, count 0 2006.285.09:25:59.13#ibcon#about to read 6, iclass 23, count 0 2006.285.09:25:59.13#ibcon#read 6, iclass 23, count 0 2006.285.09:25:59.13#ibcon#end of sib2, iclass 23, count 0 2006.285.09:25:59.13#ibcon#*mode == 0, iclass 23, count 0 2006.285.09:25:59.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.09:25:59.13#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:25:59.13#ibcon#*before write, iclass 23, count 0 2006.285.09:25:59.13#ibcon#enter sib2, iclass 23, count 0 2006.285.09:25:59.13#ibcon#flushed, iclass 23, count 0 2006.285.09:25:59.13#ibcon#about to write, iclass 23, count 0 2006.285.09:25:59.13#ibcon#wrote, iclass 23, count 0 2006.285.09:25:59.13#ibcon#about to read 3, iclass 23, count 0 2006.285.09:25:59.17#ibcon#read 3, iclass 23, count 0 2006.285.09:25:59.17#ibcon#about to read 4, iclass 23, count 0 2006.285.09:25:59.17#ibcon#read 4, iclass 23, count 0 2006.285.09:25:59.17#ibcon#about to read 5, iclass 23, count 0 2006.285.09:25:59.17#ibcon#read 5, iclass 23, count 0 2006.285.09:25:59.17#ibcon#about to read 6, iclass 23, count 0 2006.285.09:25:59.17#ibcon#read 6, iclass 23, count 0 2006.285.09:25:59.17#ibcon#end of sib2, iclass 23, count 0 2006.285.09:25:59.17#ibcon#*after write, iclass 23, count 0 2006.285.09:25:59.17#ibcon#*before return 0, iclass 23, count 0 2006.285.09:25:59.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:25:59.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:25:59.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.09:25:59.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.09:25:59.17$vck44/vb=8,4 2006.285.09:25:59.17#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.09:25:59.17#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.09:25:59.17#ibcon#ireg 11 cls_cnt 2 2006.285.09:25:59.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:25:59.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:25:59.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:25:59.23#ibcon#enter wrdev, iclass 25, count 2 2006.285.09:25:59.23#ibcon#first serial, iclass 25, count 2 2006.285.09:25:59.23#ibcon#enter sib2, iclass 25, count 2 2006.285.09:25:59.23#ibcon#flushed, iclass 25, count 2 2006.285.09:25:59.23#ibcon#about to write, iclass 25, count 2 2006.285.09:25:59.23#ibcon#wrote, iclass 25, count 2 2006.285.09:25:59.23#ibcon#about to read 3, iclass 25, count 2 2006.285.09:25:59.25#ibcon#read 3, iclass 25, count 2 2006.285.09:25:59.25#ibcon#about to read 4, iclass 25, count 2 2006.285.09:25:59.25#ibcon#read 4, iclass 25, count 2 2006.285.09:25:59.25#ibcon#about to read 5, iclass 25, count 2 2006.285.09:25:59.25#ibcon#read 5, iclass 25, count 2 2006.285.09:25:59.25#ibcon#about to read 6, iclass 25, count 2 2006.285.09:25:59.25#ibcon#read 6, iclass 25, count 2 2006.285.09:25:59.25#ibcon#end of sib2, iclass 25, count 2 2006.285.09:25:59.25#ibcon#*mode == 0, iclass 25, count 2 2006.285.09:25:59.25#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.09:25:59.25#ibcon#[27=AT08-04\r\n] 2006.285.09:25:59.25#ibcon#*before write, iclass 25, count 2 2006.285.09:25:59.25#ibcon#enter sib2, iclass 25, count 2 2006.285.09:25:59.25#ibcon#flushed, iclass 25, count 2 2006.285.09:25:59.25#ibcon#about to write, iclass 25, count 2 2006.285.09:25:59.25#ibcon#wrote, iclass 25, count 2 2006.285.09:25:59.25#ibcon#about to read 3, iclass 25, count 2 2006.285.09:25:59.28#ibcon#read 3, iclass 25, count 2 2006.285.09:25:59.28#ibcon#about to read 4, iclass 25, count 2 2006.285.09:25:59.28#ibcon#read 4, iclass 25, count 2 2006.285.09:25:59.28#ibcon#about to read 5, iclass 25, count 2 2006.285.09:25:59.28#ibcon#read 5, iclass 25, count 2 2006.285.09:25:59.28#ibcon#about to read 6, iclass 25, count 2 2006.285.09:25:59.28#ibcon#read 6, iclass 25, count 2 2006.285.09:25:59.28#ibcon#end of sib2, iclass 25, count 2 2006.285.09:25:59.28#ibcon#*after write, iclass 25, count 2 2006.285.09:25:59.28#ibcon#*before return 0, iclass 25, count 2 2006.285.09:25:59.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:25:59.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:25:59.28#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.09:25:59.28#ibcon#ireg 7 cls_cnt 0 2006.285.09:25:59.28#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:25:59.39#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:25:59.40#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:25:59.40#ibcon#enter wrdev, iclass 25, count 0 2006.285.09:25:59.40#ibcon#first serial, iclass 25, count 0 2006.285.09:25:59.40#ibcon#enter sib2, iclass 25, count 0 2006.285.09:25:59.40#ibcon#flushed, iclass 25, count 0 2006.285.09:25:59.40#ibcon#about to write, iclass 25, count 0 2006.285.09:25:59.40#ibcon#wrote, iclass 25, count 0 2006.285.09:25:59.40#ibcon#about to read 3, iclass 25, count 0 2006.285.09:25:59.41#ibcon#read 3, iclass 25, count 0 2006.285.09:25:59.42#ibcon#about to read 4, iclass 25, count 0 2006.285.09:25:59.42#ibcon#read 4, iclass 25, count 0 2006.285.09:25:59.42#ibcon#about to read 5, iclass 25, count 0 2006.285.09:25:59.42#ibcon#read 5, iclass 25, count 0 2006.285.09:25:59.42#ibcon#about to read 6, iclass 25, count 0 2006.285.09:25:59.42#ibcon#read 6, iclass 25, count 0 2006.285.09:25:59.42#ibcon#end of sib2, iclass 25, count 0 2006.285.09:25:59.42#ibcon#*mode == 0, iclass 25, count 0 2006.285.09:25:59.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.09:25:59.42#ibcon#[27=USB\r\n] 2006.285.09:25:59.42#ibcon#*before write, iclass 25, count 0 2006.285.09:25:59.42#ibcon#enter sib2, iclass 25, count 0 2006.285.09:25:59.42#ibcon#flushed, iclass 25, count 0 2006.285.09:25:59.42#ibcon#about to write, iclass 25, count 0 2006.285.09:25:59.42#ibcon#wrote, iclass 25, count 0 2006.285.09:25:59.42#ibcon#about to read 3, iclass 25, count 0 2006.285.09:25:59.45#ibcon#read 3, iclass 25, count 0 2006.285.09:25:59.45#ibcon#about to read 4, iclass 25, count 0 2006.285.09:25:59.45#ibcon#read 4, iclass 25, count 0 2006.285.09:25:59.45#ibcon#about to read 5, iclass 25, count 0 2006.285.09:25:59.45#ibcon#read 5, iclass 25, count 0 2006.285.09:25:59.45#ibcon#about to read 6, iclass 25, count 0 2006.285.09:25:59.45#ibcon#read 6, iclass 25, count 0 2006.285.09:25:59.45#ibcon#end of sib2, iclass 25, count 0 2006.285.09:25:59.45#ibcon#*after write, iclass 25, count 0 2006.285.09:25:59.45#ibcon#*before return 0, iclass 25, count 0 2006.285.09:25:59.45#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:25:59.45#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:25:59.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.09:25:59.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.09:25:59.45$vck44/vabw=wide 2006.285.09:25:59.45#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.09:25:59.45#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.09:25:59.45#ibcon#ireg 8 cls_cnt 0 2006.285.09:25:59.45#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:25:59.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:25:59.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:25:59.45#ibcon#enter wrdev, iclass 27, count 0 2006.285.09:25:59.45#ibcon#first serial, iclass 27, count 0 2006.285.09:25:59.45#ibcon#enter sib2, iclass 27, count 0 2006.285.09:25:59.45#ibcon#flushed, iclass 27, count 0 2006.285.09:25:59.45#ibcon#about to write, iclass 27, count 0 2006.285.09:25:59.45#ibcon#wrote, iclass 27, count 0 2006.285.09:25:59.45#ibcon#about to read 3, iclass 27, count 0 2006.285.09:25:59.47#ibcon#read 3, iclass 27, count 0 2006.285.09:25:59.47#ibcon#about to read 4, iclass 27, count 0 2006.285.09:25:59.47#ibcon#read 4, iclass 27, count 0 2006.285.09:25:59.47#ibcon#about to read 5, iclass 27, count 0 2006.285.09:25:59.47#ibcon#read 5, iclass 27, count 0 2006.285.09:25:59.47#ibcon#about to read 6, iclass 27, count 0 2006.285.09:25:59.47#ibcon#read 6, iclass 27, count 0 2006.285.09:25:59.47#ibcon#end of sib2, iclass 27, count 0 2006.285.09:25:59.47#ibcon#*mode == 0, iclass 27, count 0 2006.285.09:25:59.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.09:25:59.47#ibcon#[25=BW32\r\n] 2006.285.09:25:59.47#ibcon#*before write, iclass 27, count 0 2006.285.09:25:59.47#ibcon#enter sib2, iclass 27, count 0 2006.285.09:25:59.47#ibcon#flushed, iclass 27, count 0 2006.285.09:25:59.47#ibcon#about to write, iclass 27, count 0 2006.285.09:25:59.47#ibcon#wrote, iclass 27, count 0 2006.285.09:25:59.47#ibcon#about to read 3, iclass 27, count 0 2006.285.09:25:59.50#ibcon#read 3, iclass 27, count 0 2006.285.09:25:59.50#ibcon#about to read 4, iclass 27, count 0 2006.285.09:25:59.50#ibcon#read 4, iclass 27, count 0 2006.285.09:25:59.50#ibcon#about to read 5, iclass 27, count 0 2006.285.09:25:59.50#ibcon#read 5, iclass 27, count 0 2006.285.09:25:59.50#ibcon#about to read 6, iclass 27, count 0 2006.285.09:25:59.50#ibcon#read 6, iclass 27, count 0 2006.285.09:25:59.50#ibcon#end of sib2, iclass 27, count 0 2006.285.09:25:59.50#ibcon#*after write, iclass 27, count 0 2006.285.09:25:59.50#ibcon#*before return 0, iclass 27, count 0 2006.285.09:25:59.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:25:59.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:25:59.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.09:25:59.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.09:25:59.50$vck44/vbbw=wide 2006.285.09:25:59.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.09:25:59.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.09:25:59.50#ibcon#ireg 8 cls_cnt 0 2006.285.09:25:59.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:25:59.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:25:59.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:25:59.57#ibcon#enter wrdev, iclass 29, count 0 2006.285.09:25:59.57#ibcon#first serial, iclass 29, count 0 2006.285.09:25:59.57#ibcon#enter sib2, iclass 29, count 0 2006.285.09:25:59.57#ibcon#flushed, iclass 29, count 0 2006.285.09:25:59.57#ibcon#about to write, iclass 29, count 0 2006.285.09:25:59.57#ibcon#wrote, iclass 29, count 0 2006.285.09:25:59.57#ibcon#about to read 3, iclass 29, count 0 2006.285.09:25:59.58#ibcon#read 3, iclass 29, count 0 2006.285.09:25:59.59#ibcon#about to read 4, iclass 29, count 0 2006.285.09:25:59.59#ibcon#read 4, iclass 29, count 0 2006.285.09:25:59.59#ibcon#about to read 5, iclass 29, count 0 2006.285.09:25:59.59#ibcon#read 5, iclass 29, count 0 2006.285.09:25:59.59#ibcon#about to read 6, iclass 29, count 0 2006.285.09:25:59.59#ibcon#read 6, iclass 29, count 0 2006.285.09:25:59.59#ibcon#end of sib2, iclass 29, count 0 2006.285.09:25:59.59#ibcon#*mode == 0, iclass 29, count 0 2006.285.09:25:59.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.09:25:59.59#ibcon#[27=BW32\r\n] 2006.285.09:25:59.59#ibcon#*before write, iclass 29, count 0 2006.285.09:25:59.59#ibcon#enter sib2, iclass 29, count 0 2006.285.09:25:59.59#ibcon#flushed, iclass 29, count 0 2006.285.09:25:59.59#ibcon#about to write, iclass 29, count 0 2006.285.09:25:59.59#ibcon#wrote, iclass 29, count 0 2006.285.09:25:59.59#ibcon#about to read 3, iclass 29, count 0 2006.285.09:25:59.62#ibcon#read 3, iclass 29, count 0 2006.285.09:25:59.62#ibcon#about to read 4, iclass 29, count 0 2006.285.09:25:59.62#ibcon#read 4, iclass 29, count 0 2006.285.09:25:59.62#ibcon#about to read 5, iclass 29, count 0 2006.285.09:25:59.62#ibcon#read 5, iclass 29, count 0 2006.285.09:25:59.62#ibcon#about to read 6, iclass 29, count 0 2006.285.09:25:59.62#ibcon#read 6, iclass 29, count 0 2006.285.09:25:59.62#ibcon#end of sib2, iclass 29, count 0 2006.285.09:25:59.62#ibcon#*after write, iclass 29, count 0 2006.285.09:25:59.62#ibcon#*before return 0, iclass 29, count 0 2006.285.09:25:59.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:25:59.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:25:59.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.09:25:59.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.09:25:59.62$setupk4/ifdk4 2006.285.09:25:59.62$ifdk4/lo= 2006.285.09:25:59.62$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:25:59.62$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:25:59.62$ifdk4/patch= 2006.285.09:25:59.62$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:25:59.62$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:25:59.62$setupk4/!*+20s 2006.285.09:26:02.11#abcon#<5=/02 0.5 0.9 19.84 901015.0\r\n> 2006.285.09:26:02.14#abcon#{5=INTERFACE CLEAR} 2006.285.09:26:02.20#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:26:12.28#abcon#<5=/02 0.5 0.9 19.83 901015.0\r\n> 2006.285.09:26:12.30#abcon#{5=INTERFACE CLEAR} 2006.285.09:26:12.36#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:26:14.14$setupk4/"tpicd 2006.285.09:26:14.14$setupk4/echo=off 2006.285.09:26:14.14$setupk4/xlog=off 2006.285.09:26:14.14:!2006.285.09:28:44 2006.285.09:26:45.16#trakl#Source acquired 2006.285.09:26:46.14#flagr#flagr/antenna,acquired 2006.285.09:28:44.02:preob 2006.285.09:28:45.15/onsource/TRACKING 2006.285.09:28:45.15:!2006.285.09:28:54 2006.285.09:28:54.01:"tape 2006.285.09:28:54.02:"st=record 2006.285.09:28:54.02:data_valid=on 2006.285.09:28:54.02:midob 2006.285.09:28:55.15/onsource/TRACKING 2006.285.09:28:55.15/wx/19.68,1015.0,91 2006.285.09:28:55.27/cable/+6.4812E-03 2006.285.09:28:56.36/va/01,07,usb,yes,32,35 2006.285.09:28:56.36/va/02,06,usb,yes,32,33 2006.285.09:28:56.36/va/03,07,usb,yes,32,33 2006.285.09:28:56.36/va/04,06,usb,yes,33,34 2006.285.09:28:56.36/va/05,03,usb,yes,33,33 2006.285.09:28:56.36/va/06,04,usb,yes,29,29 2006.285.09:28:56.36/va/07,04,usb,yes,30,30 2006.285.09:28:56.36/va/08,03,usb,yes,30,37 2006.285.09:28:56.59/valo/01,524.99,yes,locked 2006.285.09:28:56.59/valo/02,534.99,yes,locked 2006.285.09:28:56.59/valo/03,564.99,yes,locked 2006.285.09:28:56.59/valo/04,624.99,yes,locked 2006.285.09:28:56.59/valo/05,734.99,yes,locked 2006.285.09:28:56.59/valo/06,814.99,yes,locked 2006.285.09:28:56.59/valo/07,864.99,yes,locked 2006.285.09:28:56.59/valo/08,884.99,yes,locked 2006.285.09:28:57.68/vb/01,04,usb,yes,30,28 2006.285.09:28:57.68/vb/02,05,usb,yes,29,29 2006.285.09:28:57.68/vb/03,04,usb,yes,30,33 2006.285.09:28:57.68/vb/04,05,usb,yes,30,29 2006.285.09:28:57.68/vb/05,04,usb,yes,26,29 2006.285.09:28:57.68/vb/06,03,usb,yes,38,34 2006.285.09:28:57.68/vb/07,04,usb,yes,31,31 2006.285.09:28:57.68/vb/08,04,usb,yes,28,31 2006.285.09:28:57.91/vblo/01,629.99,yes,locked 2006.285.09:28:57.91/vblo/02,634.99,yes,locked 2006.285.09:28:57.91/vblo/03,649.99,yes,locked 2006.285.09:28:57.91/vblo/04,679.99,yes,locked 2006.285.09:28:57.91/vblo/05,709.99,yes,locked 2006.285.09:28:57.91/vblo/06,719.99,yes,locked 2006.285.09:28:57.91/vblo/07,734.99,yes,locked 2006.285.09:28:57.91/vblo/08,744.99,yes,locked 2006.285.09:28:58.06/vabw/8 2006.285.09:28:58.21/vbbw/8 2006.285.09:28:58.36/xfe/off,on,12.2 2006.285.09:28:58.72/ifatt/23,28,28,28 2006.285.09:28:59.07/fmout-gps/S +2.73E-07 2006.285.09:28:59.09:!2006.285.09:29:34 2006.285.09:29:34.00:data_valid=off 2006.285.09:29:34.01:"et 2006.285.09:29:34.01:!+3s 2006.285.09:29:37.03:"tape 2006.285.09:29:37.03:postob 2006.285.09:29:37.18/cable/+6.4822E-03 2006.285.09:29:37.19/wx/19.64,1015.0,91 2006.285.09:29:37.24/fmout-gps/S +2.72E-07 2006.285.09:29:37.24:scan_name=285-0930,jd0610,60 2006.285.09:29:37.25:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.285.09:29:38.13#flagr#flagr/antenna,new-source 2006.285.09:29:38.14:checkk5 2006.285.09:29:38.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:29:39.15/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:29:39.49/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:29:39.86/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:29:40.20/chk_obsdata//k5ts1/T2850928??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.09:29:40.56/chk_obsdata//k5ts2/T2850928??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.09:29:40.96/chk_obsdata//k5ts3/T2850928??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.09:29:41.37/chk_obsdata//k5ts4/T2850928??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.09:29:42.35/k5log//k5ts1_log_newline 2006.285.09:29:43.12/k5log//k5ts2_log_newline 2006.285.09:29:43.83/k5log//k5ts3_log_newline 2006.285.09:29:44.73/k5log//k5ts4_log_newline 2006.285.09:29:44.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:29:44.75:setupk4=1 2006.285.09:29:44.75$setupk4/echo=on 2006.285.09:29:44.75$setupk4/pcalon 2006.285.09:29:44.75$pcalon/"no phase cal control is implemented here 2006.285.09:29:44.75$setupk4/"tpicd=stop 2006.285.09:29:44.75$setupk4/"rec=synch_on 2006.285.09:29:44.75$setupk4/"rec_mode=128 2006.285.09:29:44.75$setupk4/!* 2006.285.09:29:44.75$setupk4/recpk4 2006.285.09:29:44.75$recpk4/recpatch= 2006.285.09:29:44.75$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:29:44.75$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:29:44.75$setupk4/vck44 2006.285.09:29:44.76$vck44/valo=1,524.99 2006.285.09:29:44.76#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.09:29:44.76#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.09:29:44.76#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:44.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:29:44.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:29:44.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:29:44.76#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:29:44.76#ibcon#first serial, iclass 14, count 0 2006.285.09:29:44.76#ibcon#enter sib2, iclass 14, count 0 2006.285.09:29:44.76#ibcon#flushed, iclass 14, count 0 2006.285.09:29:44.76#ibcon#about to write, iclass 14, count 0 2006.285.09:29:44.76#ibcon#wrote, iclass 14, count 0 2006.285.09:29:44.76#ibcon#about to read 3, iclass 14, count 0 2006.285.09:29:44.77#ibcon#read 3, iclass 14, count 0 2006.285.09:29:44.77#ibcon#about to read 4, iclass 14, count 0 2006.285.09:29:44.77#ibcon#read 4, iclass 14, count 0 2006.285.09:29:44.77#ibcon#about to read 5, iclass 14, count 0 2006.285.09:29:44.77#ibcon#read 5, iclass 14, count 0 2006.285.09:29:44.77#ibcon#about to read 6, iclass 14, count 0 2006.285.09:29:44.77#ibcon#read 6, iclass 14, count 0 2006.285.09:29:44.77#ibcon#end of sib2, iclass 14, count 0 2006.285.09:29:44.77#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:29:44.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:29:44.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:29:44.77#ibcon#*before write, iclass 14, count 0 2006.285.09:29:44.77#ibcon#enter sib2, iclass 14, count 0 2006.285.09:29:44.77#ibcon#flushed, iclass 14, count 0 2006.285.09:29:44.77#ibcon#about to write, iclass 14, count 0 2006.285.09:29:44.77#ibcon#wrote, iclass 14, count 0 2006.285.09:29:44.77#ibcon#about to read 3, iclass 14, count 0 2006.285.09:29:44.82#ibcon#read 3, iclass 14, count 0 2006.285.09:29:44.82#ibcon#about to read 4, iclass 14, count 0 2006.285.09:29:44.82#ibcon#read 4, iclass 14, count 0 2006.285.09:29:44.82#ibcon#about to read 5, iclass 14, count 0 2006.285.09:29:44.82#ibcon#read 5, iclass 14, count 0 2006.285.09:29:44.82#ibcon#about to read 6, iclass 14, count 0 2006.285.09:29:44.82#ibcon#read 6, iclass 14, count 0 2006.285.09:29:44.82#ibcon#end of sib2, iclass 14, count 0 2006.285.09:29:44.82#ibcon#*after write, iclass 14, count 0 2006.285.09:29:44.82#ibcon#*before return 0, iclass 14, count 0 2006.285.09:29:44.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:29:44.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:29:44.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:29:44.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:29:44.82$vck44/va=1,7 2006.285.09:29:44.82#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.09:29:44.82#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.09:29:44.82#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:44.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:29:44.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:29:44.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:29:44.82#ibcon#enter wrdev, iclass 16, count 2 2006.285.09:29:44.82#ibcon#first serial, iclass 16, count 2 2006.285.09:29:44.82#ibcon#enter sib2, iclass 16, count 2 2006.285.09:29:44.82#ibcon#flushed, iclass 16, count 2 2006.285.09:29:44.82#ibcon#about to write, iclass 16, count 2 2006.285.09:29:44.83#ibcon#wrote, iclass 16, count 2 2006.285.09:29:44.83#ibcon#about to read 3, iclass 16, count 2 2006.285.09:29:44.84#ibcon#read 3, iclass 16, count 2 2006.285.09:29:44.84#ibcon#about to read 4, iclass 16, count 2 2006.285.09:29:44.84#ibcon#read 4, iclass 16, count 2 2006.285.09:29:44.84#ibcon#about to read 5, iclass 16, count 2 2006.285.09:29:44.84#ibcon#read 5, iclass 16, count 2 2006.285.09:29:44.84#ibcon#about to read 6, iclass 16, count 2 2006.285.09:29:44.84#ibcon#read 6, iclass 16, count 2 2006.285.09:29:44.84#ibcon#end of sib2, iclass 16, count 2 2006.285.09:29:44.84#ibcon#*mode == 0, iclass 16, count 2 2006.285.09:29:44.84#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.09:29:44.84#ibcon#[25=AT01-07\r\n] 2006.285.09:29:44.84#ibcon#*before write, iclass 16, count 2 2006.285.09:29:44.84#ibcon#enter sib2, iclass 16, count 2 2006.285.09:29:44.84#ibcon#flushed, iclass 16, count 2 2006.285.09:29:44.84#ibcon#about to write, iclass 16, count 2 2006.285.09:29:44.84#ibcon#wrote, iclass 16, count 2 2006.285.09:29:44.84#ibcon#about to read 3, iclass 16, count 2 2006.285.09:29:44.87#ibcon#read 3, iclass 16, count 2 2006.285.09:29:44.87#ibcon#about to read 4, iclass 16, count 2 2006.285.09:29:44.87#ibcon#read 4, iclass 16, count 2 2006.285.09:29:44.87#ibcon#about to read 5, iclass 16, count 2 2006.285.09:29:44.87#ibcon#read 5, iclass 16, count 2 2006.285.09:29:44.87#ibcon#about to read 6, iclass 16, count 2 2006.285.09:29:44.87#ibcon#read 6, iclass 16, count 2 2006.285.09:29:44.87#ibcon#end of sib2, iclass 16, count 2 2006.285.09:29:44.87#ibcon#*after write, iclass 16, count 2 2006.285.09:29:44.87#ibcon#*before return 0, iclass 16, count 2 2006.285.09:29:44.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:29:44.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:29:44.87#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.09:29:44.87#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:44.87#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:29:44.99#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:29:44.99#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:29:44.99#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:29:44.99#ibcon#first serial, iclass 16, count 0 2006.285.09:29:44.99#ibcon#enter sib2, iclass 16, count 0 2006.285.09:29:44.99#ibcon#flushed, iclass 16, count 0 2006.285.09:29:44.99#ibcon#about to write, iclass 16, count 0 2006.285.09:29:44.99#ibcon#wrote, iclass 16, count 0 2006.285.09:29:44.99#ibcon#about to read 3, iclass 16, count 0 2006.285.09:29:45.01#ibcon#read 3, iclass 16, count 0 2006.285.09:29:45.01#ibcon#about to read 4, iclass 16, count 0 2006.285.09:29:45.01#ibcon#read 4, iclass 16, count 0 2006.285.09:29:45.01#ibcon#about to read 5, iclass 16, count 0 2006.285.09:29:45.01#ibcon#read 5, iclass 16, count 0 2006.285.09:29:45.01#ibcon#about to read 6, iclass 16, count 0 2006.285.09:29:45.01#ibcon#read 6, iclass 16, count 0 2006.285.09:29:45.01#ibcon#end of sib2, iclass 16, count 0 2006.285.09:29:45.01#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:29:45.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:29:45.01#ibcon#[25=USB\r\n] 2006.285.09:29:45.01#ibcon#*before write, iclass 16, count 0 2006.285.09:29:45.01#ibcon#enter sib2, iclass 16, count 0 2006.285.09:29:45.01#ibcon#flushed, iclass 16, count 0 2006.285.09:29:45.01#ibcon#about to write, iclass 16, count 0 2006.285.09:29:45.01#ibcon#wrote, iclass 16, count 0 2006.285.09:29:45.01#ibcon#about to read 3, iclass 16, count 0 2006.285.09:29:45.04#ibcon#read 3, iclass 16, count 0 2006.285.09:29:45.04#ibcon#about to read 4, iclass 16, count 0 2006.285.09:29:45.04#ibcon#read 4, iclass 16, count 0 2006.285.09:29:45.04#ibcon#about to read 5, iclass 16, count 0 2006.285.09:29:45.04#ibcon#read 5, iclass 16, count 0 2006.285.09:29:45.04#ibcon#about to read 6, iclass 16, count 0 2006.285.09:29:45.04#ibcon#read 6, iclass 16, count 0 2006.285.09:29:45.04#ibcon#end of sib2, iclass 16, count 0 2006.285.09:29:45.04#ibcon#*after write, iclass 16, count 0 2006.285.09:29:45.04#ibcon#*before return 0, iclass 16, count 0 2006.285.09:29:45.04#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:29:45.04#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:29:45.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:29:45.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:29:45.04$vck44/valo=2,534.99 2006.285.09:29:45.04#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.09:29:45.04#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.09:29:45.04#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:45.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:29:45.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:29:45.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:29:45.04#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:29:45.04#ibcon#first serial, iclass 18, count 0 2006.285.09:29:45.04#ibcon#enter sib2, iclass 18, count 0 2006.285.09:29:45.04#ibcon#flushed, iclass 18, count 0 2006.285.09:29:45.04#ibcon#about to write, iclass 18, count 0 2006.285.09:29:45.04#ibcon#wrote, iclass 18, count 0 2006.285.09:29:45.04#ibcon#about to read 3, iclass 18, count 0 2006.285.09:29:45.06#ibcon#read 3, iclass 18, count 0 2006.285.09:29:45.06#ibcon#about to read 4, iclass 18, count 0 2006.285.09:29:45.06#ibcon#read 4, iclass 18, count 0 2006.285.09:29:45.06#ibcon#about to read 5, iclass 18, count 0 2006.285.09:29:45.06#ibcon#read 5, iclass 18, count 0 2006.285.09:29:45.06#ibcon#about to read 6, iclass 18, count 0 2006.285.09:29:45.06#ibcon#read 6, iclass 18, count 0 2006.285.09:29:45.06#ibcon#end of sib2, iclass 18, count 0 2006.285.09:29:45.06#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:29:45.06#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:29:45.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:29:45.06#ibcon#*before write, iclass 18, count 0 2006.285.09:29:45.06#ibcon#enter sib2, iclass 18, count 0 2006.285.09:29:45.06#ibcon#flushed, iclass 18, count 0 2006.285.09:29:45.06#ibcon#about to write, iclass 18, count 0 2006.285.09:29:45.06#ibcon#wrote, iclass 18, count 0 2006.285.09:29:45.06#ibcon#about to read 3, iclass 18, count 0 2006.285.09:29:45.10#ibcon#read 3, iclass 18, count 0 2006.285.09:29:45.10#ibcon#about to read 4, iclass 18, count 0 2006.285.09:29:45.10#ibcon#read 4, iclass 18, count 0 2006.285.09:29:45.10#ibcon#about to read 5, iclass 18, count 0 2006.285.09:29:45.10#ibcon#read 5, iclass 18, count 0 2006.285.09:29:45.10#ibcon#about to read 6, iclass 18, count 0 2006.285.09:29:45.10#ibcon#read 6, iclass 18, count 0 2006.285.09:29:45.10#ibcon#end of sib2, iclass 18, count 0 2006.285.09:29:45.10#ibcon#*after write, iclass 18, count 0 2006.285.09:29:45.10#ibcon#*before return 0, iclass 18, count 0 2006.285.09:29:45.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:29:45.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:29:45.10#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:29:45.10#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:29:45.10$vck44/va=2,6 2006.285.09:29:45.10#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.09:29:45.10#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.09:29:45.10#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:45.10#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:29:45.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:29:45.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:29:45.16#ibcon#enter wrdev, iclass 20, count 2 2006.285.09:29:45.16#ibcon#first serial, iclass 20, count 2 2006.285.09:29:45.16#ibcon#enter sib2, iclass 20, count 2 2006.285.09:29:45.16#ibcon#flushed, iclass 20, count 2 2006.285.09:29:45.16#ibcon#about to write, iclass 20, count 2 2006.285.09:29:45.16#ibcon#wrote, iclass 20, count 2 2006.285.09:29:45.16#ibcon#about to read 3, iclass 20, count 2 2006.285.09:29:45.18#ibcon#read 3, iclass 20, count 2 2006.285.09:29:45.18#ibcon#about to read 4, iclass 20, count 2 2006.285.09:29:45.18#ibcon#read 4, iclass 20, count 2 2006.285.09:29:45.18#ibcon#about to read 5, iclass 20, count 2 2006.285.09:29:45.18#ibcon#read 5, iclass 20, count 2 2006.285.09:29:45.18#ibcon#about to read 6, iclass 20, count 2 2006.285.09:29:45.18#ibcon#read 6, iclass 20, count 2 2006.285.09:29:45.18#ibcon#end of sib2, iclass 20, count 2 2006.285.09:29:45.18#ibcon#*mode == 0, iclass 20, count 2 2006.285.09:29:45.18#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.09:29:45.18#ibcon#[25=AT02-06\r\n] 2006.285.09:29:45.18#ibcon#*before write, iclass 20, count 2 2006.285.09:29:45.18#ibcon#enter sib2, iclass 20, count 2 2006.285.09:29:45.18#ibcon#flushed, iclass 20, count 2 2006.285.09:29:45.18#ibcon#about to write, iclass 20, count 2 2006.285.09:29:45.18#ibcon#wrote, iclass 20, count 2 2006.285.09:29:45.18#ibcon#about to read 3, iclass 20, count 2 2006.285.09:29:45.21#ibcon#read 3, iclass 20, count 2 2006.285.09:29:45.21#ibcon#about to read 4, iclass 20, count 2 2006.285.09:29:45.21#ibcon#read 4, iclass 20, count 2 2006.285.09:29:45.21#ibcon#about to read 5, iclass 20, count 2 2006.285.09:29:45.21#ibcon#read 5, iclass 20, count 2 2006.285.09:29:45.21#ibcon#about to read 6, iclass 20, count 2 2006.285.09:29:45.21#ibcon#read 6, iclass 20, count 2 2006.285.09:29:45.21#ibcon#end of sib2, iclass 20, count 2 2006.285.09:29:45.21#ibcon#*after write, iclass 20, count 2 2006.285.09:29:45.21#ibcon#*before return 0, iclass 20, count 2 2006.285.09:29:45.21#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:29:45.21#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:29:45.21#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.09:29:45.21#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:45.21#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:29:45.33#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:29:45.33#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:29:45.33#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:29:45.33#ibcon#first serial, iclass 20, count 0 2006.285.09:29:45.33#ibcon#enter sib2, iclass 20, count 0 2006.285.09:29:45.33#ibcon#flushed, iclass 20, count 0 2006.285.09:29:45.33#ibcon#about to write, iclass 20, count 0 2006.285.09:29:45.33#ibcon#wrote, iclass 20, count 0 2006.285.09:29:45.33#ibcon#about to read 3, iclass 20, count 0 2006.285.09:29:45.35#ibcon#read 3, iclass 20, count 0 2006.285.09:29:45.35#ibcon#about to read 4, iclass 20, count 0 2006.285.09:29:45.35#ibcon#read 4, iclass 20, count 0 2006.285.09:29:45.35#ibcon#about to read 5, iclass 20, count 0 2006.285.09:29:45.35#ibcon#read 5, iclass 20, count 0 2006.285.09:29:45.35#ibcon#about to read 6, iclass 20, count 0 2006.285.09:29:45.35#ibcon#read 6, iclass 20, count 0 2006.285.09:29:45.35#ibcon#end of sib2, iclass 20, count 0 2006.285.09:29:45.35#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:29:45.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:29:45.35#ibcon#[25=USB\r\n] 2006.285.09:29:45.35#ibcon#*before write, iclass 20, count 0 2006.285.09:29:45.35#ibcon#enter sib2, iclass 20, count 0 2006.285.09:29:45.35#ibcon#flushed, iclass 20, count 0 2006.285.09:29:45.35#ibcon#about to write, iclass 20, count 0 2006.285.09:29:45.35#ibcon#wrote, iclass 20, count 0 2006.285.09:29:45.35#ibcon#about to read 3, iclass 20, count 0 2006.285.09:29:45.38#ibcon#read 3, iclass 20, count 0 2006.285.09:29:45.38#ibcon#about to read 4, iclass 20, count 0 2006.285.09:29:45.38#ibcon#read 4, iclass 20, count 0 2006.285.09:29:45.38#ibcon#about to read 5, iclass 20, count 0 2006.285.09:29:45.38#ibcon#read 5, iclass 20, count 0 2006.285.09:29:45.38#ibcon#about to read 6, iclass 20, count 0 2006.285.09:29:45.38#ibcon#read 6, iclass 20, count 0 2006.285.09:29:45.38#ibcon#end of sib2, iclass 20, count 0 2006.285.09:29:45.38#ibcon#*after write, iclass 20, count 0 2006.285.09:29:45.38#ibcon#*before return 0, iclass 20, count 0 2006.285.09:29:45.38#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:29:45.38#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:29:45.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:29:45.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:29:45.38$vck44/valo=3,564.99 2006.285.09:29:45.38#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.09:29:45.38#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.09:29:45.38#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:45.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:29:45.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:29:45.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:29:45.38#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:29:45.38#ibcon#first serial, iclass 22, count 0 2006.285.09:29:45.38#ibcon#enter sib2, iclass 22, count 0 2006.285.09:29:45.38#ibcon#flushed, iclass 22, count 0 2006.285.09:29:45.38#ibcon#about to write, iclass 22, count 0 2006.285.09:29:45.38#ibcon#wrote, iclass 22, count 0 2006.285.09:29:45.38#ibcon#about to read 3, iclass 22, count 0 2006.285.09:29:45.40#ibcon#read 3, iclass 22, count 0 2006.285.09:29:45.40#ibcon#about to read 4, iclass 22, count 0 2006.285.09:29:45.40#ibcon#read 4, iclass 22, count 0 2006.285.09:29:45.40#ibcon#about to read 5, iclass 22, count 0 2006.285.09:29:45.40#ibcon#read 5, iclass 22, count 0 2006.285.09:29:45.40#ibcon#about to read 6, iclass 22, count 0 2006.285.09:29:45.40#ibcon#read 6, iclass 22, count 0 2006.285.09:29:45.40#ibcon#end of sib2, iclass 22, count 0 2006.285.09:29:45.40#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:29:45.40#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:29:45.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:29:45.40#ibcon#*before write, iclass 22, count 0 2006.285.09:29:45.40#ibcon#enter sib2, iclass 22, count 0 2006.285.09:29:45.40#ibcon#flushed, iclass 22, count 0 2006.285.09:29:45.40#ibcon#about to write, iclass 22, count 0 2006.285.09:29:45.40#ibcon#wrote, iclass 22, count 0 2006.285.09:29:45.40#ibcon#about to read 3, iclass 22, count 0 2006.285.09:29:45.44#ibcon#read 3, iclass 22, count 0 2006.285.09:29:45.44#ibcon#about to read 4, iclass 22, count 0 2006.285.09:29:45.44#ibcon#read 4, iclass 22, count 0 2006.285.09:29:45.44#ibcon#about to read 5, iclass 22, count 0 2006.285.09:29:45.44#ibcon#read 5, iclass 22, count 0 2006.285.09:29:45.44#ibcon#about to read 6, iclass 22, count 0 2006.285.09:29:45.44#ibcon#read 6, iclass 22, count 0 2006.285.09:29:45.44#ibcon#end of sib2, iclass 22, count 0 2006.285.09:29:45.44#ibcon#*after write, iclass 22, count 0 2006.285.09:29:45.44#ibcon#*before return 0, iclass 22, count 0 2006.285.09:29:45.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:29:45.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:29:45.44#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:29:45.44#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:29:45.44$vck44/va=3,7 2006.285.09:29:45.44#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.09:29:45.44#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.09:29:45.44#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:45.44#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:29:45.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:29:45.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:29:45.50#ibcon#enter wrdev, iclass 24, count 2 2006.285.09:29:45.50#ibcon#first serial, iclass 24, count 2 2006.285.09:29:45.50#ibcon#enter sib2, iclass 24, count 2 2006.285.09:29:45.50#ibcon#flushed, iclass 24, count 2 2006.285.09:29:45.50#ibcon#about to write, iclass 24, count 2 2006.285.09:29:45.50#ibcon#wrote, iclass 24, count 2 2006.285.09:29:45.50#ibcon#about to read 3, iclass 24, count 2 2006.285.09:29:45.52#ibcon#read 3, iclass 24, count 2 2006.285.09:29:45.52#ibcon#about to read 4, iclass 24, count 2 2006.285.09:29:45.52#ibcon#read 4, iclass 24, count 2 2006.285.09:29:45.52#ibcon#about to read 5, iclass 24, count 2 2006.285.09:29:45.52#ibcon#read 5, iclass 24, count 2 2006.285.09:29:45.52#ibcon#about to read 6, iclass 24, count 2 2006.285.09:29:45.52#ibcon#read 6, iclass 24, count 2 2006.285.09:29:45.52#ibcon#end of sib2, iclass 24, count 2 2006.285.09:29:45.52#ibcon#*mode == 0, iclass 24, count 2 2006.285.09:29:45.52#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.09:29:45.52#ibcon#[25=AT03-07\r\n] 2006.285.09:29:45.52#ibcon#*before write, iclass 24, count 2 2006.285.09:29:45.52#ibcon#enter sib2, iclass 24, count 2 2006.285.09:29:45.52#ibcon#flushed, iclass 24, count 2 2006.285.09:29:45.52#ibcon#about to write, iclass 24, count 2 2006.285.09:29:45.52#ibcon#wrote, iclass 24, count 2 2006.285.09:29:45.52#ibcon#about to read 3, iclass 24, count 2 2006.285.09:29:45.55#ibcon#read 3, iclass 24, count 2 2006.285.09:29:45.55#ibcon#about to read 4, iclass 24, count 2 2006.285.09:29:45.55#ibcon#read 4, iclass 24, count 2 2006.285.09:29:45.55#ibcon#about to read 5, iclass 24, count 2 2006.285.09:29:45.55#ibcon#read 5, iclass 24, count 2 2006.285.09:29:45.55#ibcon#about to read 6, iclass 24, count 2 2006.285.09:29:45.55#ibcon#read 6, iclass 24, count 2 2006.285.09:29:45.55#ibcon#end of sib2, iclass 24, count 2 2006.285.09:29:45.55#ibcon#*after write, iclass 24, count 2 2006.285.09:29:45.55#ibcon#*before return 0, iclass 24, count 2 2006.285.09:29:45.55#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:29:45.55#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:29:45.55#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.09:29:45.55#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:45.55#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:29:45.67#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:29:45.67#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:29:45.67#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:29:45.67#ibcon#first serial, iclass 24, count 0 2006.285.09:29:45.67#ibcon#enter sib2, iclass 24, count 0 2006.285.09:29:45.67#ibcon#flushed, iclass 24, count 0 2006.285.09:29:45.67#ibcon#about to write, iclass 24, count 0 2006.285.09:29:45.67#ibcon#wrote, iclass 24, count 0 2006.285.09:29:45.67#ibcon#about to read 3, iclass 24, count 0 2006.285.09:29:45.69#ibcon#read 3, iclass 24, count 0 2006.285.09:29:45.69#ibcon#about to read 4, iclass 24, count 0 2006.285.09:29:45.69#ibcon#read 4, iclass 24, count 0 2006.285.09:29:45.69#ibcon#about to read 5, iclass 24, count 0 2006.285.09:29:45.69#ibcon#read 5, iclass 24, count 0 2006.285.09:29:45.69#ibcon#about to read 6, iclass 24, count 0 2006.285.09:29:45.69#ibcon#read 6, iclass 24, count 0 2006.285.09:29:45.69#ibcon#end of sib2, iclass 24, count 0 2006.285.09:29:45.69#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:29:45.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:29:45.69#ibcon#[25=USB\r\n] 2006.285.09:29:45.69#ibcon#*before write, iclass 24, count 0 2006.285.09:29:45.69#ibcon#enter sib2, iclass 24, count 0 2006.285.09:29:45.69#ibcon#flushed, iclass 24, count 0 2006.285.09:29:45.69#ibcon#about to write, iclass 24, count 0 2006.285.09:29:45.69#ibcon#wrote, iclass 24, count 0 2006.285.09:29:45.69#ibcon#about to read 3, iclass 24, count 0 2006.285.09:29:45.72#ibcon#read 3, iclass 24, count 0 2006.285.09:29:45.72#ibcon#about to read 4, iclass 24, count 0 2006.285.09:29:45.72#ibcon#read 4, iclass 24, count 0 2006.285.09:29:45.72#ibcon#about to read 5, iclass 24, count 0 2006.285.09:29:45.72#ibcon#read 5, iclass 24, count 0 2006.285.09:29:45.72#ibcon#about to read 6, iclass 24, count 0 2006.285.09:29:45.72#ibcon#read 6, iclass 24, count 0 2006.285.09:29:45.72#ibcon#end of sib2, iclass 24, count 0 2006.285.09:29:45.72#ibcon#*after write, iclass 24, count 0 2006.285.09:29:45.72#ibcon#*before return 0, iclass 24, count 0 2006.285.09:29:45.72#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:29:45.72#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:29:45.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:29:45.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:29:45.72$vck44/valo=4,624.99 2006.285.09:29:45.72#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.09:29:45.72#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.09:29:45.72#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:45.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:29:45.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:29:45.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:29:45.72#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:29:45.72#ibcon#first serial, iclass 26, count 0 2006.285.09:29:45.72#ibcon#enter sib2, iclass 26, count 0 2006.285.09:29:45.72#ibcon#flushed, iclass 26, count 0 2006.285.09:29:45.72#ibcon#about to write, iclass 26, count 0 2006.285.09:29:45.72#ibcon#wrote, iclass 26, count 0 2006.285.09:29:45.72#ibcon#about to read 3, iclass 26, count 0 2006.285.09:29:45.74#ibcon#read 3, iclass 26, count 0 2006.285.09:29:45.74#ibcon#about to read 4, iclass 26, count 0 2006.285.09:29:45.74#ibcon#read 4, iclass 26, count 0 2006.285.09:29:45.74#ibcon#about to read 5, iclass 26, count 0 2006.285.09:29:45.74#ibcon#read 5, iclass 26, count 0 2006.285.09:29:45.74#ibcon#about to read 6, iclass 26, count 0 2006.285.09:29:45.74#ibcon#read 6, iclass 26, count 0 2006.285.09:29:45.74#ibcon#end of sib2, iclass 26, count 0 2006.285.09:29:45.74#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:29:45.74#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:29:45.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:29:45.74#ibcon#*before write, iclass 26, count 0 2006.285.09:29:45.74#ibcon#enter sib2, iclass 26, count 0 2006.285.09:29:45.74#ibcon#flushed, iclass 26, count 0 2006.285.09:29:45.74#ibcon#about to write, iclass 26, count 0 2006.285.09:29:45.74#ibcon#wrote, iclass 26, count 0 2006.285.09:29:45.74#ibcon#about to read 3, iclass 26, count 0 2006.285.09:29:45.78#ibcon#read 3, iclass 26, count 0 2006.285.09:29:45.78#ibcon#about to read 4, iclass 26, count 0 2006.285.09:29:45.78#ibcon#read 4, iclass 26, count 0 2006.285.09:29:45.78#ibcon#about to read 5, iclass 26, count 0 2006.285.09:29:45.78#ibcon#read 5, iclass 26, count 0 2006.285.09:29:45.78#ibcon#about to read 6, iclass 26, count 0 2006.285.09:29:45.78#ibcon#read 6, iclass 26, count 0 2006.285.09:29:45.78#ibcon#end of sib2, iclass 26, count 0 2006.285.09:29:45.78#ibcon#*after write, iclass 26, count 0 2006.285.09:29:45.78#ibcon#*before return 0, iclass 26, count 0 2006.285.09:29:45.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:29:45.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:29:45.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:29:45.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:29:45.78$vck44/va=4,6 2006.285.09:29:45.78#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.09:29:45.78#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.09:29:45.78#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:45.78#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:29:45.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:29:45.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:29:45.84#ibcon#enter wrdev, iclass 28, count 2 2006.285.09:29:45.84#ibcon#first serial, iclass 28, count 2 2006.285.09:29:45.84#ibcon#enter sib2, iclass 28, count 2 2006.285.09:29:45.84#ibcon#flushed, iclass 28, count 2 2006.285.09:29:45.84#ibcon#about to write, iclass 28, count 2 2006.285.09:29:45.84#ibcon#wrote, iclass 28, count 2 2006.285.09:29:45.84#ibcon#about to read 3, iclass 28, count 2 2006.285.09:29:45.86#ibcon#read 3, iclass 28, count 2 2006.285.09:29:45.86#ibcon#about to read 4, iclass 28, count 2 2006.285.09:29:45.86#ibcon#read 4, iclass 28, count 2 2006.285.09:29:45.86#ibcon#about to read 5, iclass 28, count 2 2006.285.09:29:45.86#ibcon#read 5, iclass 28, count 2 2006.285.09:29:45.86#ibcon#about to read 6, iclass 28, count 2 2006.285.09:29:45.86#ibcon#read 6, iclass 28, count 2 2006.285.09:29:45.86#ibcon#end of sib2, iclass 28, count 2 2006.285.09:29:45.86#ibcon#*mode == 0, iclass 28, count 2 2006.285.09:29:45.86#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.09:29:45.86#ibcon#[25=AT04-06\r\n] 2006.285.09:29:45.86#ibcon#*before write, iclass 28, count 2 2006.285.09:29:45.86#ibcon#enter sib2, iclass 28, count 2 2006.285.09:29:45.86#ibcon#flushed, iclass 28, count 2 2006.285.09:29:45.86#ibcon#about to write, iclass 28, count 2 2006.285.09:29:45.86#ibcon#wrote, iclass 28, count 2 2006.285.09:29:45.86#ibcon#about to read 3, iclass 28, count 2 2006.285.09:29:45.89#ibcon#read 3, iclass 28, count 2 2006.285.09:29:45.89#ibcon#about to read 4, iclass 28, count 2 2006.285.09:29:45.89#ibcon#read 4, iclass 28, count 2 2006.285.09:29:45.89#ibcon#about to read 5, iclass 28, count 2 2006.285.09:29:45.89#ibcon#read 5, iclass 28, count 2 2006.285.09:29:45.89#ibcon#about to read 6, iclass 28, count 2 2006.285.09:29:45.89#ibcon#read 6, iclass 28, count 2 2006.285.09:29:45.89#ibcon#end of sib2, iclass 28, count 2 2006.285.09:29:45.89#ibcon#*after write, iclass 28, count 2 2006.285.09:29:45.89#ibcon#*before return 0, iclass 28, count 2 2006.285.09:29:45.89#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:29:45.89#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:29:45.89#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.09:29:45.89#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:45.89#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:29:45.99#abcon#<5=/02 0.7 1.3 19.63 911015.0\r\n> 2006.285.09:29:46.01#abcon#{5=INTERFACE CLEAR} 2006.285.09:29:46.01#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:29:46.01#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:29:46.01#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:29:46.01#ibcon#first serial, iclass 28, count 0 2006.285.09:29:46.01#ibcon#enter sib2, iclass 28, count 0 2006.285.09:29:46.01#ibcon#flushed, iclass 28, count 0 2006.285.09:29:46.01#ibcon#about to write, iclass 28, count 0 2006.285.09:29:46.01#ibcon#wrote, iclass 28, count 0 2006.285.09:29:46.01#ibcon#about to read 3, iclass 28, count 0 2006.285.09:29:46.03#ibcon#read 3, iclass 28, count 0 2006.285.09:29:46.03#ibcon#about to read 4, iclass 28, count 0 2006.285.09:29:46.03#ibcon#read 4, iclass 28, count 0 2006.285.09:29:46.03#ibcon#about to read 5, iclass 28, count 0 2006.285.09:29:46.03#ibcon#read 5, iclass 28, count 0 2006.285.09:29:46.03#ibcon#about to read 6, iclass 28, count 0 2006.285.09:29:46.03#ibcon#read 6, iclass 28, count 0 2006.285.09:29:46.03#ibcon#end of sib2, iclass 28, count 0 2006.285.09:29:46.03#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:29:46.03#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:29:46.03#ibcon#[25=USB\r\n] 2006.285.09:29:46.03#ibcon#*before write, iclass 28, count 0 2006.285.09:29:46.03#ibcon#enter sib2, iclass 28, count 0 2006.285.09:29:46.03#ibcon#flushed, iclass 28, count 0 2006.285.09:29:46.03#ibcon#about to write, iclass 28, count 0 2006.285.09:29:46.03#ibcon#wrote, iclass 28, count 0 2006.285.09:29:46.03#ibcon#about to read 3, iclass 28, count 0 2006.285.09:29:46.06#ibcon#read 3, iclass 28, count 0 2006.285.09:29:46.06#ibcon#about to read 4, iclass 28, count 0 2006.285.09:29:46.06#ibcon#read 4, iclass 28, count 0 2006.285.09:29:46.06#ibcon#about to read 5, iclass 28, count 0 2006.285.09:29:46.06#ibcon#read 5, iclass 28, count 0 2006.285.09:29:46.06#ibcon#about to read 6, iclass 28, count 0 2006.285.09:29:46.06#ibcon#read 6, iclass 28, count 0 2006.285.09:29:46.06#ibcon#end of sib2, iclass 28, count 0 2006.285.09:29:46.06#ibcon#*after write, iclass 28, count 0 2006.285.09:29:46.06#ibcon#*before return 0, iclass 28, count 0 2006.285.09:29:46.06#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:29:46.06#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:29:46.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:29:46.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:29:46.06$vck44/valo=5,734.99 2006.285.09:29:46.06#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.09:29:46.06#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.09:29:46.06#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:46.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:29:46.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:29:46.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:29:46.06#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:29:46.06#ibcon#first serial, iclass 34, count 0 2006.285.09:29:46.06#ibcon#enter sib2, iclass 34, count 0 2006.285.09:29:46.06#ibcon#flushed, iclass 34, count 0 2006.285.09:29:46.06#ibcon#about to write, iclass 34, count 0 2006.285.09:29:46.07#ibcon#wrote, iclass 34, count 0 2006.285.09:29:46.07#ibcon#about to read 3, iclass 34, count 0 2006.285.09:29:46.07#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:29:46.08#ibcon#read 3, iclass 34, count 0 2006.285.09:29:46.08#ibcon#about to read 4, iclass 34, count 0 2006.285.09:29:46.08#ibcon#read 4, iclass 34, count 0 2006.285.09:29:46.08#ibcon#about to read 5, iclass 34, count 0 2006.285.09:29:46.08#ibcon#read 5, iclass 34, count 0 2006.285.09:29:46.08#ibcon#about to read 6, iclass 34, count 0 2006.285.09:29:46.08#ibcon#read 6, iclass 34, count 0 2006.285.09:29:46.08#ibcon#end of sib2, iclass 34, count 0 2006.285.09:29:46.08#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:29:46.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:29:46.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:29:46.08#ibcon#*before write, iclass 34, count 0 2006.285.09:29:46.08#ibcon#enter sib2, iclass 34, count 0 2006.285.09:29:46.08#ibcon#flushed, iclass 34, count 0 2006.285.09:29:46.08#ibcon#about to write, iclass 34, count 0 2006.285.09:29:46.08#ibcon#wrote, iclass 34, count 0 2006.285.09:29:46.08#ibcon#about to read 3, iclass 34, count 0 2006.285.09:29:46.12#ibcon#read 3, iclass 34, count 0 2006.285.09:29:46.12#ibcon#about to read 4, iclass 34, count 0 2006.285.09:29:46.12#ibcon#read 4, iclass 34, count 0 2006.285.09:29:46.12#ibcon#about to read 5, iclass 34, count 0 2006.285.09:29:46.12#ibcon#read 5, iclass 34, count 0 2006.285.09:29:46.12#ibcon#about to read 6, iclass 34, count 0 2006.285.09:29:46.12#ibcon#read 6, iclass 34, count 0 2006.285.09:29:46.12#ibcon#end of sib2, iclass 34, count 0 2006.285.09:29:46.12#ibcon#*after write, iclass 34, count 0 2006.285.09:29:46.12#ibcon#*before return 0, iclass 34, count 0 2006.285.09:29:46.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:29:46.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:29:46.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:29:46.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:29:46.12$vck44/va=5,3 2006.285.09:29:46.12#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.09:29:46.12#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.09:29:46.12#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:46.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:29:46.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:29:46.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:29:46.18#ibcon#enter wrdev, iclass 36, count 2 2006.285.09:29:46.18#ibcon#first serial, iclass 36, count 2 2006.285.09:29:46.18#ibcon#enter sib2, iclass 36, count 2 2006.285.09:29:46.18#ibcon#flushed, iclass 36, count 2 2006.285.09:29:46.18#ibcon#about to write, iclass 36, count 2 2006.285.09:29:46.18#ibcon#wrote, iclass 36, count 2 2006.285.09:29:46.18#ibcon#about to read 3, iclass 36, count 2 2006.285.09:29:46.20#ibcon#read 3, iclass 36, count 2 2006.285.09:29:46.20#ibcon#about to read 4, iclass 36, count 2 2006.285.09:29:46.20#ibcon#read 4, iclass 36, count 2 2006.285.09:29:46.20#ibcon#about to read 5, iclass 36, count 2 2006.285.09:29:46.20#ibcon#read 5, iclass 36, count 2 2006.285.09:29:46.20#ibcon#about to read 6, iclass 36, count 2 2006.285.09:29:46.20#ibcon#read 6, iclass 36, count 2 2006.285.09:29:46.20#ibcon#end of sib2, iclass 36, count 2 2006.285.09:29:46.20#ibcon#*mode == 0, iclass 36, count 2 2006.285.09:29:46.20#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.09:29:46.20#ibcon#[25=AT05-03\r\n] 2006.285.09:29:46.20#ibcon#*before write, iclass 36, count 2 2006.285.09:29:46.20#ibcon#enter sib2, iclass 36, count 2 2006.285.09:29:46.20#ibcon#flushed, iclass 36, count 2 2006.285.09:29:46.20#ibcon#about to write, iclass 36, count 2 2006.285.09:29:46.20#ibcon#wrote, iclass 36, count 2 2006.285.09:29:46.20#ibcon#about to read 3, iclass 36, count 2 2006.285.09:29:46.23#ibcon#read 3, iclass 36, count 2 2006.285.09:29:46.23#ibcon#about to read 4, iclass 36, count 2 2006.285.09:29:46.23#ibcon#read 4, iclass 36, count 2 2006.285.09:29:46.23#ibcon#about to read 5, iclass 36, count 2 2006.285.09:29:46.23#ibcon#read 5, iclass 36, count 2 2006.285.09:29:46.23#ibcon#about to read 6, iclass 36, count 2 2006.285.09:29:46.23#ibcon#read 6, iclass 36, count 2 2006.285.09:29:46.23#ibcon#end of sib2, iclass 36, count 2 2006.285.09:29:46.23#ibcon#*after write, iclass 36, count 2 2006.285.09:29:46.23#ibcon#*before return 0, iclass 36, count 2 2006.285.09:29:46.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:29:46.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:29:46.23#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.09:29:46.23#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:46.23#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:29:46.35#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:29:46.35#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:29:46.35#ibcon#enter wrdev, iclass 36, count 0 2006.285.09:29:46.35#ibcon#first serial, iclass 36, count 0 2006.285.09:29:46.35#ibcon#enter sib2, iclass 36, count 0 2006.285.09:29:46.35#ibcon#flushed, iclass 36, count 0 2006.285.09:29:46.35#ibcon#about to write, iclass 36, count 0 2006.285.09:29:46.35#ibcon#wrote, iclass 36, count 0 2006.285.09:29:46.35#ibcon#about to read 3, iclass 36, count 0 2006.285.09:29:46.37#ibcon#read 3, iclass 36, count 0 2006.285.09:29:46.37#ibcon#about to read 4, iclass 36, count 0 2006.285.09:29:46.37#ibcon#read 4, iclass 36, count 0 2006.285.09:29:46.37#ibcon#about to read 5, iclass 36, count 0 2006.285.09:29:46.37#ibcon#read 5, iclass 36, count 0 2006.285.09:29:46.37#ibcon#about to read 6, iclass 36, count 0 2006.285.09:29:46.37#ibcon#read 6, iclass 36, count 0 2006.285.09:29:46.37#ibcon#end of sib2, iclass 36, count 0 2006.285.09:29:46.37#ibcon#*mode == 0, iclass 36, count 0 2006.285.09:29:46.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.09:29:46.37#ibcon#[25=USB\r\n] 2006.285.09:29:46.37#ibcon#*before write, iclass 36, count 0 2006.285.09:29:46.37#ibcon#enter sib2, iclass 36, count 0 2006.285.09:29:46.37#ibcon#flushed, iclass 36, count 0 2006.285.09:29:46.37#ibcon#about to write, iclass 36, count 0 2006.285.09:29:46.37#ibcon#wrote, iclass 36, count 0 2006.285.09:29:46.37#ibcon#about to read 3, iclass 36, count 0 2006.285.09:29:46.40#ibcon#read 3, iclass 36, count 0 2006.285.09:29:46.40#ibcon#about to read 4, iclass 36, count 0 2006.285.09:29:46.40#ibcon#read 4, iclass 36, count 0 2006.285.09:29:46.40#ibcon#about to read 5, iclass 36, count 0 2006.285.09:29:46.40#ibcon#read 5, iclass 36, count 0 2006.285.09:29:46.40#ibcon#about to read 6, iclass 36, count 0 2006.285.09:29:46.40#ibcon#read 6, iclass 36, count 0 2006.285.09:29:46.40#ibcon#end of sib2, iclass 36, count 0 2006.285.09:29:46.40#ibcon#*after write, iclass 36, count 0 2006.285.09:29:46.40#ibcon#*before return 0, iclass 36, count 0 2006.285.09:29:46.40#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:29:46.40#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:29:46.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.09:29:46.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.09:29:46.40$vck44/valo=6,814.99 2006.285.09:29:46.40#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.09:29:46.40#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.09:29:46.40#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:46.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:29:46.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:29:46.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:29:46.40#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:29:46.40#ibcon#first serial, iclass 38, count 0 2006.285.09:29:46.40#ibcon#enter sib2, iclass 38, count 0 2006.285.09:29:46.40#ibcon#flushed, iclass 38, count 0 2006.285.09:29:46.40#ibcon#about to write, iclass 38, count 0 2006.285.09:29:46.40#ibcon#wrote, iclass 38, count 0 2006.285.09:29:46.40#ibcon#about to read 3, iclass 38, count 0 2006.285.09:29:46.42#ibcon#read 3, iclass 38, count 0 2006.285.09:29:46.42#ibcon#about to read 4, iclass 38, count 0 2006.285.09:29:46.42#ibcon#read 4, iclass 38, count 0 2006.285.09:29:46.42#ibcon#about to read 5, iclass 38, count 0 2006.285.09:29:46.42#ibcon#read 5, iclass 38, count 0 2006.285.09:29:46.42#ibcon#about to read 6, iclass 38, count 0 2006.285.09:29:46.42#ibcon#read 6, iclass 38, count 0 2006.285.09:29:46.42#ibcon#end of sib2, iclass 38, count 0 2006.285.09:29:46.42#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:29:46.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:29:46.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:29:46.42#ibcon#*before write, iclass 38, count 0 2006.285.09:29:46.42#ibcon#enter sib2, iclass 38, count 0 2006.285.09:29:46.42#ibcon#flushed, iclass 38, count 0 2006.285.09:29:46.42#ibcon#about to write, iclass 38, count 0 2006.285.09:29:46.42#ibcon#wrote, iclass 38, count 0 2006.285.09:29:46.42#ibcon#about to read 3, iclass 38, count 0 2006.285.09:29:46.46#ibcon#read 3, iclass 38, count 0 2006.285.09:29:46.46#ibcon#about to read 4, iclass 38, count 0 2006.285.09:29:46.46#ibcon#read 4, iclass 38, count 0 2006.285.09:29:46.46#ibcon#about to read 5, iclass 38, count 0 2006.285.09:29:46.46#ibcon#read 5, iclass 38, count 0 2006.285.09:29:46.46#ibcon#about to read 6, iclass 38, count 0 2006.285.09:29:46.46#ibcon#read 6, iclass 38, count 0 2006.285.09:29:46.46#ibcon#end of sib2, iclass 38, count 0 2006.285.09:29:46.46#ibcon#*after write, iclass 38, count 0 2006.285.09:29:46.46#ibcon#*before return 0, iclass 38, count 0 2006.285.09:29:46.46#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:29:46.46#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:29:46.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:29:46.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:29:46.46$vck44/va=6,4 2006.285.09:29:46.46#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.09:29:46.46#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.09:29:46.46#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:46.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:29:46.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:29:46.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:29:46.52#ibcon#enter wrdev, iclass 40, count 2 2006.285.09:29:46.52#ibcon#first serial, iclass 40, count 2 2006.285.09:29:46.52#ibcon#enter sib2, iclass 40, count 2 2006.285.09:29:46.52#ibcon#flushed, iclass 40, count 2 2006.285.09:29:46.52#ibcon#about to write, iclass 40, count 2 2006.285.09:29:46.52#ibcon#wrote, iclass 40, count 2 2006.285.09:29:46.52#ibcon#about to read 3, iclass 40, count 2 2006.285.09:29:46.54#ibcon#read 3, iclass 40, count 2 2006.285.09:29:46.54#ibcon#about to read 4, iclass 40, count 2 2006.285.09:29:46.54#ibcon#read 4, iclass 40, count 2 2006.285.09:29:46.54#ibcon#about to read 5, iclass 40, count 2 2006.285.09:29:46.54#ibcon#read 5, iclass 40, count 2 2006.285.09:29:46.54#ibcon#about to read 6, iclass 40, count 2 2006.285.09:29:46.54#ibcon#read 6, iclass 40, count 2 2006.285.09:29:46.54#ibcon#end of sib2, iclass 40, count 2 2006.285.09:29:46.54#ibcon#*mode == 0, iclass 40, count 2 2006.285.09:29:46.54#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.09:29:46.54#ibcon#[25=AT06-04\r\n] 2006.285.09:29:46.54#ibcon#*before write, iclass 40, count 2 2006.285.09:29:46.54#ibcon#enter sib2, iclass 40, count 2 2006.285.09:29:46.54#ibcon#flushed, iclass 40, count 2 2006.285.09:29:46.54#ibcon#about to write, iclass 40, count 2 2006.285.09:29:46.54#ibcon#wrote, iclass 40, count 2 2006.285.09:29:46.54#ibcon#about to read 3, iclass 40, count 2 2006.285.09:29:46.57#ibcon#read 3, iclass 40, count 2 2006.285.09:29:46.57#ibcon#about to read 4, iclass 40, count 2 2006.285.09:29:46.57#ibcon#read 4, iclass 40, count 2 2006.285.09:29:46.57#ibcon#about to read 5, iclass 40, count 2 2006.285.09:29:46.57#ibcon#read 5, iclass 40, count 2 2006.285.09:29:46.57#ibcon#about to read 6, iclass 40, count 2 2006.285.09:29:46.57#ibcon#read 6, iclass 40, count 2 2006.285.09:29:46.57#ibcon#end of sib2, iclass 40, count 2 2006.285.09:29:46.57#ibcon#*after write, iclass 40, count 2 2006.285.09:29:46.57#ibcon#*before return 0, iclass 40, count 2 2006.285.09:29:46.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:29:46.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:29:46.57#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.09:29:46.57#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:46.57#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:29:46.69#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:29:46.69#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:29:46.69#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:29:46.69#ibcon#first serial, iclass 40, count 0 2006.285.09:29:46.69#ibcon#enter sib2, iclass 40, count 0 2006.285.09:29:46.69#ibcon#flushed, iclass 40, count 0 2006.285.09:29:46.69#ibcon#about to write, iclass 40, count 0 2006.285.09:29:46.69#ibcon#wrote, iclass 40, count 0 2006.285.09:29:46.69#ibcon#about to read 3, iclass 40, count 0 2006.285.09:29:46.71#ibcon#read 3, iclass 40, count 0 2006.285.09:29:46.71#ibcon#about to read 4, iclass 40, count 0 2006.285.09:29:46.71#ibcon#read 4, iclass 40, count 0 2006.285.09:29:46.71#ibcon#about to read 5, iclass 40, count 0 2006.285.09:29:46.71#ibcon#read 5, iclass 40, count 0 2006.285.09:29:46.71#ibcon#about to read 6, iclass 40, count 0 2006.285.09:29:46.71#ibcon#read 6, iclass 40, count 0 2006.285.09:29:46.71#ibcon#end of sib2, iclass 40, count 0 2006.285.09:29:46.71#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:29:46.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:29:46.71#ibcon#[25=USB\r\n] 2006.285.09:29:46.71#ibcon#*before write, iclass 40, count 0 2006.285.09:29:46.71#ibcon#enter sib2, iclass 40, count 0 2006.285.09:29:46.71#ibcon#flushed, iclass 40, count 0 2006.285.09:29:46.71#ibcon#about to write, iclass 40, count 0 2006.285.09:29:46.71#ibcon#wrote, iclass 40, count 0 2006.285.09:29:46.71#ibcon#about to read 3, iclass 40, count 0 2006.285.09:29:46.74#ibcon#read 3, iclass 40, count 0 2006.285.09:29:46.74#ibcon#about to read 4, iclass 40, count 0 2006.285.09:29:46.74#ibcon#read 4, iclass 40, count 0 2006.285.09:29:46.74#ibcon#about to read 5, iclass 40, count 0 2006.285.09:29:46.74#ibcon#read 5, iclass 40, count 0 2006.285.09:29:46.74#ibcon#about to read 6, iclass 40, count 0 2006.285.09:29:46.74#ibcon#read 6, iclass 40, count 0 2006.285.09:29:46.74#ibcon#end of sib2, iclass 40, count 0 2006.285.09:29:46.74#ibcon#*after write, iclass 40, count 0 2006.285.09:29:46.74#ibcon#*before return 0, iclass 40, count 0 2006.285.09:29:46.74#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:29:46.74#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:29:46.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:29:46.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:29:46.74$vck44/valo=7,864.99 2006.285.09:29:46.74#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.09:29:46.74#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.09:29:46.74#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:46.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:29:46.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:29:46.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:29:46.74#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:29:46.74#ibcon#first serial, iclass 4, count 0 2006.285.09:29:46.74#ibcon#enter sib2, iclass 4, count 0 2006.285.09:29:46.74#ibcon#flushed, iclass 4, count 0 2006.285.09:29:46.74#ibcon#about to write, iclass 4, count 0 2006.285.09:29:46.74#ibcon#wrote, iclass 4, count 0 2006.285.09:29:46.74#ibcon#about to read 3, iclass 4, count 0 2006.285.09:29:46.76#ibcon#read 3, iclass 4, count 0 2006.285.09:29:46.76#ibcon#about to read 4, iclass 4, count 0 2006.285.09:29:46.76#ibcon#read 4, iclass 4, count 0 2006.285.09:29:46.76#ibcon#about to read 5, iclass 4, count 0 2006.285.09:29:46.76#ibcon#read 5, iclass 4, count 0 2006.285.09:29:46.76#ibcon#about to read 6, iclass 4, count 0 2006.285.09:29:46.76#ibcon#read 6, iclass 4, count 0 2006.285.09:29:46.76#ibcon#end of sib2, iclass 4, count 0 2006.285.09:29:46.76#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:29:46.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:29:46.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:29:46.76#ibcon#*before write, iclass 4, count 0 2006.285.09:29:46.76#ibcon#enter sib2, iclass 4, count 0 2006.285.09:29:46.76#ibcon#flushed, iclass 4, count 0 2006.285.09:29:46.76#ibcon#about to write, iclass 4, count 0 2006.285.09:29:46.76#ibcon#wrote, iclass 4, count 0 2006.285.09:29:46.76#ibcon#about to read 3, iclass 4, count 0 2006.285.09:29:46.80#ibcon#read 3, iclass 4, count 0 2006.285.09:29:46.80#ibcon#about to read 4, iclass 4, count 0 2006.285.09:29:46.80#ibcon#read 4, iclass 4, count 0 2006.285.09:29:46.80#ibcon#about to read 5, iclass 4, count 0 2006.285.09:29:46.80#ibcon#read 5, iclass 4, count 0 2006.285.09:29:46.80#ibcon#about to read 6, iclass 4, count 0 2006.285.09:29:46.80#ibcon#read 6, iclass 4, count 0 2006.285.09:29:46.80#ibcon#end of sib2, iclass 4, count 0 2006.285.09:29:46.80#ibcon#*after write, iclass 4, count 0 2006.285.09:29:46.80#ibcon#*before return 0, iclass 4, count 0 2006.285.09:29:46.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:29:46.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:29:46.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:29:46.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:29:46.80$vck44/va=7,4 2006.285.09:29:46.80#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.09:29:46.80#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.09:29:46.80#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:46.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:29:46.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:29:46.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:29:46.86#ibcon#enter wrdev, iclass 6, count 2 2006.285.09:29:46.86#ibcon#first serial, iclass 6, count 2 2006.285.09:29:46.86#ibcon#enter sib2, iclass 6, count 2 2006.285.09:29:46.86#ibcon#flushed, iclass 6, count 2 2006.285.09:29:46.86#ibcon#about to write, iclass 6, count 2 2006.285.09:29:46.86#ibcon#wrote, iclass 6, count 2 2006.285.09:29:46.86#ibcon#about to read 3, iclass 6, count 2 2006.285.09:29:46.88#ibcon#read 3, iclass 6, count 2 2006.285.09:29:46.88#ibcon#about to read 4, iclass 6, count 2 2006.285.09:29:46.88#ibcon#read 4, iclass 6, count 2 2006.285.09:29:46.88#ibcon#about to read 5, iclass 6, count 2 2006.285.09:29:46.88#ibcon#read 5, iclass 6, count 2 2006.285.09:29:46.88#ibcon#about to read 6, iclass 6, count 2 2006.285.09:29:46.88#ibcon#read 6, iclass 6, count 2 2006.285.09:29:46.88#ibcon#end of sib2, iclass 6, count 2 2006.285.09:29:46.88#ibcon#*mode == 0, iclass 6, count 2 2006.285.09:29:46.88#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.09:29:46.88#ibcon#[25=AT07-04\r\n] 2006.285.09:29:46.88#ibcon#*before write, iclass 6, count 2 2006.285.09:29:46.88#ibcon#enter sib2, iclass 6, count 2 2006.285.09:29:46.88#ibcon#flushed, iclass 6, count 2 2006.285.09:29:46.88#ibcon#about to write, iclass 6, count 2 2006.285.09:29:46.88#ibcon#wrote, iclass 6, count 2 2006.285.09:29:46.88#ibcon#about to read 3, iclass 6, count 2 2006.285.09:29:46.91#ibcon#read 3, iclass 6, count 2 2006.285.09:29:46.91#ibcon#about to read 4, iclass 6, count 2 2006.285.09:29:46.91#ibcon#read 4, iclass 6, count 2 2006.285.09:29:46.91#ibcon#about to read 5, iclass 6, count 2 2006.285.09:29:46.91#ibcon#read 5, iclass 6, count 2 2006.285.09:29:46.91#ibcon#about to read 6, iclass 6, count 2 2006.285.09:29:46.91#ibcon#read 6, iclass 6, count 2 2006.285.09:29:46.91#ibcon#end of sib2, iclass 6, count 2 2006.285.09:29:46.91#ibcon#*after write, iclass 6, count 2 2006.285.09:29:46.91#ibcon#*before return 0, iclass 6, count 2 2006.285.09:29:46.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:29:46.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:29:46.91#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.09:29:46.91#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:46.91#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:29:47.03#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:29:47.03#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:29:47.03#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:29:47.03#ibcon#first serial, iclass 6, count 0 2006.285.09:29:47.03#ibcon#enter sib2, iclass 6, count 0 2006.285.09:29:47.03#ibcon#flushed, iclass 6, count 0 2006.285.09:29:47.03#ibcon#about to write, iclass 6, count 0 2006.285.09:29:47.03#ibcon#wrote, iclass 6, count 0 2006.285.09:29:47.03#ibcon#about to read 3, iclass 6, count 0 2006.285.09:29:47.05#ibcon#read 3, iclass 6, count 0 2006.285.09:29:47.05#ibcon#about to read 4, iclass 6, count 0 2006.285.09:29:47.05#ibcon#read 4, iclass 6, count 0 2006.285.09:29:47.05#ibcon#about to read 5, iclass 6, count 0 2006.285.09:29:47.05#ibcon#read 5, iclass 6, count 0 2006.285.09:29:47.05#ibcon#about to read 6, iclass 6, count 0 2006.285.09:29:47.05#ibcon#read 6, iclass 6, count 0 2006.285.09:29:47.05#ibcon#end of sib2, iclass 6, count 0 2006.285.09:29:47.05#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:29:47.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:29:47.05#ibcon#[25=USB\r\n] 2006.285.09:29:47.05#ibcon#*before write, iclass 6, count 0 2006.285.09:29:47.05#ibcon#enter sib2, iclass 6, count 0 2006.285.09:29:47.05#ibcon#flushed, iclass 6, count 0 2006.285.09:29:47.05#ibcon#about to write, iclass 6, count 0 2006.285.09:29:47.05#ibcon#wrote, iclass 6, count 0 2006.285.09:29:47.05#ibcon#about to read 3, iclass 6, count 0 2006.285.09:29:47.08#ibcon#read 3, iclass 6, count 0 2006.285.09:29:47.08#ibcon#about to read 4, iclass 6, count 0 2006.285.09:29:47.08#ibcon#read 4, iclass 6, count 0 2006.285.09:29:47.08#ibcon#about to read 5, iclass 6, count 0 2006.285.09:29:47.08#ibcon#read 5, iclass 6, count 0 2006.285.09:29:47.08#ibcon#about to read 6, iclass 6, count 0 2006.285.09:29:47.08#ibcon#read 6, iclass 6, count 0 2006.285.09:29:47.08#ibcon#end of sib2, iclass 6, count 0 2006.285.09:29:47.08#ibcon#*after write, iclass 6, count 0 2006.285.09:29:47.08#ibcon#*before return 0, iclass 6, count 0 2006.285.09:29:47.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:29:47.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:29:47.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:29:47.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:29:47.08$vck44/valo=8,884.99 2006.285.09:29:47.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.09:29:47.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.09:29:47.08#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:47.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:29:47.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:29:47.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:29:47.08#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:29:47.08#ibcon#first serial, iclass 10, count 0 2006.285.09:29:47.08#ibcon#enter sib2, iclass 10, count 0 2006.285.09:29:47.08#ibcon#flushed, iclass 10, count 0 2006.285.09:29:47.08#ibcon#about to write, iclass 10, count 0 2006.285.09:29:47.08#ibcon#wrote, iclass 10, count 0 2006.285.09:29:47.08#ibcon#about to read 3, iclass 10, count 0 2006.285.09:29:47.10#ibcon#read 3, iclass 10, count 0 2006.285.09:29:47.10#ibcon#about to read 4, iclass 10, count 0 2006.285.09:29:47.10#ibcon#read 4, iclass 10, count 0 2006.285.09:29:47.10#ibcon#about to read 5, iclass 10, count 0 2006.285.09:29:47.10#ibcon#read 5, iclass 10, count 0 2006.285.09:29:47.10#ibcon#about to read 6, iclass 10, count 0 2006.285.09:29:47.10#ibcon#read 6, iclass 10, count 0 2006.285.09:29:47.10#ibcon#end of sib2, iclass 10, count 0 2006.285.09:29:47.10#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:29:47.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:29:47.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:29:47.10#ibcon#*before write, iclass 10, count 0 2006.285.09:29:47.10#ibcon#enter sib2, iclass 10, count 0 2006.285.09:29:47.10#ibcon#flushed, iclass 10, count 0 2006.285.09:29:47.10#ibcon#about to write, iclass 10, count 0 2006.285.09:29:47.10#ibcon#wrote, iclass 10, count 0 2006.285.09:29:47.10#ibcon#about to read 3, iclass 10, count 0 2006.285.09:29:47.14#ibcon#read 3, iclass 10, count 0 2006.285.09:29:47.14#ibcon#about to read 4, iclass 10, count 0 2006.285.09:29:47.14#ibcon#read 4, iclass 10, count 0 2006.285.09:29:47.14#ibcon#about to read 5, iclass 10, count 0 2006.285.09:29:47.14#ibcon#read 5, iclass 10, count 0 2006.285.09:29:47.14#ibcon#about to read 6, iclass 10, count 0 2006.285.09:29:47.14#ibcon#read 6, iclass 10, count 0 2006.285.09:29:47.14#ibcon#end of sib2, iclass 10, count 0 2006.285.09:29:47.14#ibcon#*after write, iclass 10, count 0 2006.285.09:29:47.14#ibcon#*before return 0, iclass 10, count 0 2006.285.09:29:47.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:29:47.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:29:47.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:29:47.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:29:47.14$vck44/va=8,3 2006.285.09:29:47.14#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.09:29:47.14#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.09:29:47.14#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:47.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:29:47.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:29:47.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:29:47.20#ibcon#enter wrdev, iclass 12, count 2 2006.285.09:29:47.20#ibcon#first serial, iclass 12, count 2 2006.285.09:29:47.20#ibcon#enter sib2, iclass 12, count 2 2006.285.09:29:47.20#ibcon#flushed, iclass 12, count 2 2006.285.09:29:47.20#ibcon#about to write, iclass 12, count 2 2006.285.09:29:47.20#ibcon#wrote, iclass 12, count 2 2006.285.09:29:47.20#ibcon#about to read 3, iclass 12, count 2 2006.285.09:29:47.22#ibcon#read 3, iclass 12, count 2 2006.285.09:29:47.22#ibcon#about to read 4, iclass 12, count 2 2006.285.09:29:47.22#ibcon#read 4, iclass 12, count 2 2006.285.09:29:47.22#ibcon#about to read 5, iclass 12, count 2 2006.285.09:29:47.22#ibcon#read 5, iclass 12, count 2 2006.285.09:29:47.22#ibcon#about to read 6, iclass 12, count 2 2006.285.09:29:47.22#ibcon#read 6, iclass 12, count 2 2006.285.09:29:47.22#ibcon#end of sib2, iclass 12, count 2 2006.285.09:29:47.22#ibcon#*mode == 0, iclass 12, count 2 2006.285.09:29:47.22#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.09:29:47.22#ibcon#[25=AT08-03\r\n] 2006.285.09:29:47.22#ibcon#*before write, iclass 12, count 2 2006.285.09:29:47.22#ibcon#enter sib2, iclass 12, count 2 2006.285.09:29:47.22#ibcon#flushed, iclass 12, count 2 2006.285.09:29:47.22#ibcon#about to write, iclass 12, count 2 2006.285.09:29:47.22#ibcon#wrote, iclass 12, count 2 2006.285.09:29:47.22#ibcon#about to read 3, iclass 12, count 2 2006.285.09:29:47.25#ibcon#read 3, iclass 12, count 2 2006.285.09:29:47.25#ibcon#about to read 4, iclass 12, count 2 2006.285.09:29:47.25#ibcon#read 4, iclass 12, count 2 2006.285.09:29:47.25#ibcon#about to read 5, iclass 12, count 2 2006.285.09:29:47.25#ibcon#read 5, iclass 12, count 2 2006.285.09:29:47.25#ibcon#about to read 6, iclass 12, count 2 2006.285.09:29:47.25#ibcon#read 6, iclass 12, count 2 2006.285.09:29:47.25#ibcon#end of sib2, iclass 12, count 2 2006.285.09:29:47.25#ibcon#*after write, iclass 12, count 2 2006.285.09:29:47.25#ibcon#*before return 0, iclass 12, count 2 2006.285.09:29:47.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:29:47.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:29:47.25#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.09:29:47.25#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:47.25#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:29:47.37#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:29:47.37#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:29:47.37#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:29:47.37#ibcon#first serial, iclass 12, count 0 2006.285.09:29:47.37#ibcon#enter sib2, iclass 12, count 0 2006.285.09:29:47.37#ibcon#flushed, iclass 12, count 0 2006.285.09:29:47.37#ibcon#about to write, iclass 12, count 0 2006.285.09:29:47.37#ibcon#wrote, iclass 12, count 0 2006.285.09:29:47.37#ibcon#about to read 3, iclass 12, count 0 2006.285.09:29:47.39#ibcon#read 3, iclass 12, count 0 2006.285.09:29:47.39#ibcon#about to read 4, iclass 12, count 0 2006.285.09:29:47.39#ibcon#read 4, iclass 12, count 0 2006.285.09:29:47.39#ibcon#about to read 5, iclass 12, count 0 2006.285.09:29:47.39#ibcon#read 5, iclass 12, count 0 2006.285.09:29:47.39#ibcon#about to read 6, iclass 12, count 0 2006.285.09:29:47.39#ibcon#read 6, iclass 12, count 0 2006.285.09:29:47.39#ibcon#end of sib2, iclass 12, count 0 2006.285.09:29:47.39#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:29:47.39#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:29:47.39#ibcon#[25=USB\r\n] 2006.285.09:29:47.39#ibcon#*before write, iclass 12, count 0 2006.285.09:29:47.39#ibcon#enter sib2, iclass 12, count 0 2006.285.09:29:47.39#ibcon#flushed, iclass 12, count 0 2006.285.09:29:47.39#ibcon#about to write, iclass 12, count 0 2006.285.09:29:47.39#ibcon#wrote, iclass 12, count 0 2006.285.09:29:47.39#ibcon#about to read 3, iclass 12, count 0 2006.285.09:29:47.42#ibcon#read 3, iclass 12, count 0 2006.285.09:29:47.42#ibcon#about to read 4, iclass 12, count 0 2006.285.09:29:47.42#ibcon#read 4, iclass 12, count 0 2006.285.09:29:47.42#ibcon#about to read 5, iclass 12, count 0 2006.285.09:29:47.42#ibcon#read 5, iclass 12, count 0 2006.285.09:29:47.42#ibcon#about to read 6, iclass 12, count 0 2006.285.09:29:47.42#ibcon#read 6, iclass 12, count 0 2006.285.09:29:47.42#ibcon#end of sib2, iclass 12, count 0 2006.285.09:29:47.42#ibcon#*after write, iclass 12, count 0 2006.285.09:29:47.42#ibcon#*before return 0, iclass 12, count 0 2006.285.09:29:47.42#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:29:47.42#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:29:47.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:29:47.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:29:47.42$vck44/vblo=1,629.99 2006.285.09:29:47.42#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.09:29:47.42#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.09:29:47.42#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:47.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:29:47.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:29:47.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:29:47.42#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:29:47.42#ibcon#first serial, iclass 14, count 0 2006.285.09:29:47.42#ibcon#enter sib2, iclass 14, count 0 2006.285.09:29:47.42#ibcon#flushed, iclass 14, count 0 2006.285.09:29:47.42#ibcon#about to write, iclass 14, count 0 2006.285.09:29:47.42#ibcon#wrote, iclass 14, count 0 2006.285.09:29:47.42#ibcon#about to read 3, iclass 14, count 0 2006.285.09:29:47.44#ibcon#read 3, iclass 14, count 0 2006.285.09:29:47.44#ibcon#about to read 4, iclass 14, count 0 2006.285.09:29:47.44#ibcon#read 4, iclass 14, count 0 2006.285.09:29:47.44#ibcon#about to read 5, iclass 14, count 0 2006.285.09:29:47.44#ibcon#read 5, iclass 14, count 0 2006.285.09:29:47.44#ibcon#about to read 6, iclass 14, count 0 2006.285.09:29:47.44#ibcon#read 6, iclass 14, count 0 2006.285.09:29:47.44#ibcon#end of sib2, iclass 14, count 0 2006.285.09:29:47.44#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:29:47.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:29:47.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:29:47.44#ibcon#*before write, iclass 14, count 0 2006.285.09:29:47.44#ibcon#enter sib2, iclass 14, count 0 2006.285.09:29:47.44#ibcon#flushed, iclass 14, count 0 2006.285.09:29:47.44#ibcon#about to write, iclass 14, count 0 2006.285.09:29:47.44#ibcon#wrote, iclass 14, count 0 2006.285.09:29:47.44#ibcon#about to read 3, iclass 14, count 0 2006.285.09:29:47.48#ibcon#read 3, iclass 14, count 0 2006.285.09:29:47.48#ibcon#about to read 4, iclass 14, count 0 2006.285.09:29:47.48#ibcon#read 4, iclass 14, count 0 2006.285.09:29:47.48#ibcon#about to read 5, iclass 14, count 0 2006.285.09:29:47.48#ibcon#read 5, iclass 14, count 0 2006.285.09:29:47.48#ibcon#about to read 6, iclass 14, count 0 2006.285.09:29:47.48#ibcon#read 6, iclass 14, count 0 2006.285.09:29:47.48#ibcon#end of sib2, iclass 14, count 0 2006.285.09:29:47.48#ibcon#*after write, iclass 14, count 0 2006.285.09:29:47.48#ibcon#*before return 0, iclass 14, count 0 2006.285.09:29:47.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:29:47.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:29:47.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:29:47.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:29:47.48$vck44/vb=1,4 2006.285.09:29:47.48#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.09:29:47.48#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.09:29:47.48#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:47.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:29:47.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:29:47.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:29:47.48#ibcon#enter wrdev, iclass 16, count 2 2006.285.09:29:47.48#ibcon#first serial, iclass 16, count 2 2006.285.09:29:47.48#ibcon#enter sib2, iclass 16, count 2 2006.285.09:29:47.48#ibcon#flushed, iclass 16, count 2 2006.285.09:29:47.48#ibcon#about to write, iclass 16, count 2 2006.285.09:29:47.48#ibcon#wrote, iclass 16, count 2 2006.285.09:29:47.48#ibcon#about to read 3, iclass 16, count 2 2006.285.09:29:47.50#ibcon#read 3, iclass 16, count 2 2006.285.09:29:47.50#ibcon#about to read 4, iclass 16, count 2 2006.285.09:29:47.50#ibcon#read 4, iclass 16, count 2 2006.285.09:29:47.50#ibcon#about to read 5, iclass 16, count 2 2006.285.09:29:47.50#ibcon#read 5, iclass 16, count 2 2006.285.09:29:47.50#ibcon#about to read 6, iclass 16, count 2 2006.285.09:29:47.50#ibcon#read 6, iclass 16, count 2 2006.285.09:29:47.50#ibcon#end of sib2, iclass 16, count 2 2006.285.09:29:47.50#ibcon#*mode == 0, iclass 16, count 2 2006.285.09:29:47.50#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.09:29:47.50#ibcon#[27=AT01-04\r\n] 2006.285.09:29:47.50#ibcon#*before write, iclass 16, count 2 2006.285.09:29:47.50#ibcon#enter sib2, iclass 16, count 2 2006.285.09:29:47.50#ibcon#flushed, iclass 16, count 2 2006.285.09:29:47.50#ibcon#about to write, iclass 16, count 2 2006.285.09:29:47.50#ibcon#wrote, iclass 16, count 2 2006.285.09:29:47.50#ibcon#about to read 3, iclass 16, count 2 2006.285.09:29:47.53#ibcon#read 3, iclass 16, count 2 2006.285.09:29:47.53#ibcon#about to read 4, iclass 16, count 2 2006.285.09:29:47.53#ibcon#read 4, iclass 16, count 2 2006.285.09:29:47.53#ibcon#about to read 5, iclass 16, count 2 2006.285.09:29:47.53#ibcon#read 5, iclass 16, count 2 2006.285.09:29:47.53#ibcon#about to read 6, iclass 16, count 2 2006.285.09:29:47.53#ibcon#read 6, iclass 16, count 2 2006.285.09:29:47.53#ibcon#end of sib2, iclass 16, count 2 2006.285.09:29:47.53#ibcon#*after write, iclass 16, count 2 2006.285.09:29:47.53#ibcon#*before return 0, iclass 16, count 2 2006.285.09:29:47.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:29:47.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:29:47.53#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.09:29:47.53#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:47.53#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:29:47.65#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:29:47.65#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:29:47.65#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:29:47.65#ibcon#first serial, iclass 16, count 0 2006.285.09:29:47.65#ibcon#enter sib2, iclass 16, count 0 2006.285.09:29:47.65#ibcon#flushed, iclass 16, count 0 2006.285.09:29:47.65#ibcon#about to write, iclass 16, count 0 2006.285.09:29:47.65#ibcon#wrote, iclass 16, count 0 2006.285.09:29:47.65#ibcon#about to read 3, iclass 16, count 0 2006.285.09:29:47.67#ibcon#read 3, iclass 16, count 0 2006.285.09:29:47.67#ibcon#about to read 4, iclass 16, count 0 2006.285.09:29:47.67#ibcon#read 4, iclass 16, count 0 2006.285.09:29:47.67#ibcon#about to read 5, iclass 16, count 0 2006.285.09:29:47.67#ibcon#read 5, iclass 16, count 0 2006.285.09:29:47.67#ibcon#about to read 6, iclass 16, count 0 2006.285.09:29:47.67#ibcon#read 6, iclass 16, count 0 2006.285.09:29:47.67#ibcon#end of sib2, iclass 16, count 0 2006.285.09:29:47.67#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:29:47.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:29:47.67#ibcon#[27=USB\r\n] 2006.285.09:29:47.67#ibcon#*before write, iclass 16, count 0 2006.285.09:29:47.67#ibcon#enter sib2, iclass 16, count 0 2006.285.09:29:47.67#ibcon#flushed, iclass 16, count 0 2006.285.09:29:47.67#ibcon#about to write, iclass 16, count 0 2006.285.09:29:47.67#ibcon#wrote, iclass 16, count 0 2006.285.09:29:47.67#ibcon#about to read 3, iclass 16, count 0 2006.285.09:29:47.70#ibcon#read 3, iclass 16, count 0 2006.285.09:29:47.70#ibcon#about to read 4, iclass 16, count 0 2006.285.09:29:47.70#ibcon#read 4, iclass 16, count 0 2006.285.09:29:47.70#ibcon#about to read 5, iclass 16, count 0 2006.285.09:29:47.70#ibcon#read 5, iclass 16, count 0 2006.285.09:29:47.70#ibcon#about to read 6, iclass 16, count 0 2006.285.09:29:47.70#ibcon#read 6, iclass 16, count 0 2006.285.09:29:47.70#ibcon#end of sib2, iclass 16, count 0 2006.285.09:29:47.70#ibcon#*after write, iclass 16, count 0 2006.285.09:29:47.70#ibcon#*before return 0, iclass 16, count 0 2006.285.09:29:47.70#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:29:47.70#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:29:47.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:29:47.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:29:47.70$vck44/vblo=2,634.99 2006.285.09:29:47.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.09:29:47.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.09:29:47.70#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:47.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:29:47.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:29:47.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:29:47.70#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:29:47.70#ibcon#first serial, iclass 18, count 0 2006.285.09:29:47.70#ibcon#enter sib2, iclass 18, count 0 2006.285.09:29:47.70#ibcon#flushed, iclass 18, count 0 2006.285.09:29:47.70#ibcon#about to write, iclass 18, count 0 2006.285.09:29:47.70#ibcon#wrote, iclass 18, count 0 2006.285.09:29:47.70#ibcon#about to read 3, iclass 18, count 0 2006.285.09:29:47.72#ibcon#read 3, iclass 18, count 0 2006.285.09:29:47.72#ibcon#about to read 4, iclass 18, count 0 2006.285.09:29:47.72#ibcon#read 4, iclass 18, count 0 2006.285.09:29:47.72#ibcon#about to read 5, iclass 18, count 0 2006.285.09:29:47.72#ibcon#read 5, iclass 18, count 0 2006.285.09:29:47.72#ibcon#about to read 6, iclass 18, count 0 2006.285.09:29:47.72#ibcon#read 6, iclass 18, count 0 2006.285.09:29:47.72#ibcon#end of sib2, iclass 18, count 0 2006.285.09:29:47.72#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:29:47.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:29:47.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:29:47.72#ibcon#*before write, iclass 18, count 0 2006.285.09:29:47.72#ibcon#enter sib2, iclass 18, count 0 2006.285.09:29:47.72#ibcon#flushed, iclass 18, count 0 2006.285.09:29:47.72#ibcon#about to write, iclass 18, count 0 2006.285.09:29:47.72#ibcon#wrote, iclass 18, count 0 2006.285.09:29:47.72#ibcon#about to read 3, iclass 18, count 0 2006.285.09:29:47.76#ibcon#read 3, iclass 18, count 0 2006.285.09:29:47.76#ibcon#about to read 4, iclass 18, count 0 2006.285.09:29:47.76#ibcon#read 4, iclass 18, count 0 2006.285.09:29:47.76#ibcon#about to read 5, iclass 18, count 0 2006.285.09:29:47.76#ibcon#read 5, iclass 18, count 0 2006.285.09:29:47.76#ibcon#about to read 6, iclass 18, count 0 2006.285.09:29:47.76#ibcon#read 6, iclass 18, count 0 2006.285.09:29:47.76#ibcon#end of sib2, iclass 18, count 0 2006.285.09:29:47.76#ibcon#*after write, iclass 18, count 0 2006.285.09:29:47.76#ibcon#*before return 0, iclass 18, count 0 2006.285.09:29:47.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:29:47.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:29:47.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:29:47.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:29:47.76$vck44/vb=2,5 2006.285.09:29:47.76#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.09:29:47.76#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.09:29:47.76#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:47.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:29:47.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:29:47.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:29:47.82#ibcon#enter wrdev, iclass 20, count 2 2006.285.09:29:47.82#ibcon#first serial, iclass 20, count 2 2006.285.09:29:47.82#ibcon#enter sib2, iclass 20, count 2 2006.285.09:29:47.82#ibcon#flushed, iclass 20, count 2 2006.285.09:29:47.82#ibcon#about to write, iclass 20, count 2 2006.285.09:29:47.82#ibcon#wrote, iclass 20, count 2 2006.285.09:29:47.82#ibcon#about to read 3, iclass 20, count 2 2006.285.09:29:47.84#ibcon#read 3, iclass 20, count 2 2006.285.09:29:47.84#ibcon#about to read 4, iclass 20, count 2 2006.285.09:29:47.84#ibcon#read 4, iclass 20, count 2 2006.285.09:29:47.84#ibcon#about to read 5, iclass 20, count 2 2006.285.09:29:47.84#ibcon#read 5, iclass 20, count 2 2006.285.09:29:47.84#ibcon#about to read 6, iclass 20, count 2 2006.285.09:29:47.84#ibcon#read 6, iclass 20, count 2 2006.285.09:29:47.84#ibcon#end of sib2, iclass 20, count 2 2006.285.09:29:47.84#ibcon#*mode == 0, iclass 20, count 2 2006.285.09:29:47.84#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.09:29:47.84#ibcon#[27=AT02-05\r\n] 2006.285.09:29:47.84#ibcon#*before write, iclass 20, count 2 2006.285.09:29:47.84#ibcon#enter sib2, iclass 20, count 2 2006.285.09:29:47.84#ibcon#flushed, iclass 20, count 2 2006.285.09:29:47.84#ibcon#about to write, iclass 20, count 2 2006.285.09:29:47.84#ibcon#wrote, iclass 20, count 2 2006.285.09:29:47.84#ibcon#about to read 3, iclass 20, count 2 2006.285.09:29:47.87#ibcon#read 3, iclass 20, count 2 2006.285.09:29:47.87#ibcon#about to read 4, iclass 20, count 2 2006.285.09:29:47.87#ibcon#read 4, iclass 20, count 2 2006.285.09:29:47.87#ibcon#about to read 5, iclass 20, count 2 2006.285.09:29:47.87#ibcon#read 5, iclass 20, count 2 2006.285.09:29:47.87#ibcon#about to read 6, iclass 20, count 2 2006.285.09:29:47.87#ibcon#read 6, iclass 20, count 2 2006.285.09:29:47.87#ibcon#end of sib2, iclass 20, count 2 2006.285.09:29:47.87#ibcon#*after write, iclass 20, count 2 2006.285.09:29:47.87#ibcon#*before return 0, iclass 20, count 2 2006.285.09:29:47.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:29:47.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:29:47.87#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.09:29:47.87#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:47.87#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:29:47.99#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:29:47.99#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:29:47.99#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:29:47.99#ibcon#first serial, iclass 20, count 0 2006.285.09:29:47.99#ibcon#enter sib2, iclass 20, count 0 2006.285.09:29:47.99#ibcon#flushed, iclass 20, count 0 2006.285.09:29:47.99#ibcon#about to write, iclass 20, count 0 2006.285.09:29:47.99#ibcon#wrote, iclass 20, count 0 2006.285.09:29:47.99#ibcon#about to read 3, iclass 20, count 0 2006.285.09:29:48.01#ibcon#read 3, iclass 20, count 0 2006.285.09:29:48.01#ibcon#about to read 4, iclass 20, count 0 2006.285.09:29:48.01#ibcon#read 4, iclass 20, count 0 2006.285.09:29:48.01#ibcon#about to read 5, iclass 20, count 0 2006.285.09:29:48.01#ibcon#read 5, iclass 20, count 0 2006.285.09:29:48.01#ibcon#about to read 6, iclass 20, count 0 2006.285.09:29:48.01#ibcon#read 6, iclass 20, count 0 2006.285.09:29:48.01#ibcon#end of sib2, iclass 20, count 0 2006.285.09:29:48.01#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:29:48.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:29:48.01#ibcon#[27=USB\r\n] 2006.285.09:29:48.01#ibcon#*before write, iclass 20, count 0 2006.285.09:29:48.01#ibcon#enter sib2, iclass 20, count 0 2006.285.09:29:48.01#ibcon#flushed, iclass 20, count 0 2006.285.09:29:48.01#ibcon#about to write, iclass 20, count 0 2006.285.09:29:48.01#ibcon#wrote, iclass 20, count 0 2006.285.09:29:48.01#ibcon#about to read 3, iclass 20, count 0 2006.285.09:29:48.04#ibcon#read 3, iclass 20, count 0 2006.285.09:29:48.04#ibcon#about to read 4, iclass 20, count 0 2006.285.09:29:48.04#ibcon#read 4, iclass 20, count 0 2006.285.09:29:48.04#ibcon#about to read 5, iclass 20, count 0 2006.285.09:29:48.04#ibcon#read 5, iclass 20, count 0 2006.285.09:29:48.04#ibcon#about to read 6, iclass 20, count 0 2006.285.09:29:48.04#ibcon#read 6, iclass 20, count 0 2006.285.09:29:48.04#ibcon#end of sib2, iclass 20, count 0 2006.285.09:29:48.04#ibcon#*after write, iclass 20, count 0 2006.285.09:29:48.04#ibcon#*before return 0, iclass 20, count 0 2006.285.09:29:48.04#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:29:48.04#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:29:48.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:29:48.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:29:48.04$vck44/vblo=3,649.99 2006.285.09:29:48.04#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.09:29:48.04#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.09:29:48.04#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:48.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:29:48.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:29:48.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:29:48.04#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:29:48.04#ibcon#first serial, iclass 22, count 0 2006.285.09:29:48.04#ibcon#enter sib2, iclass 22, count 0 2006.285.09:29:48.04#ibcon#flushed, iclass 22, count 0 2006.285.09:29:48.04#ibcon#about to write, iclass 22, count 0 2006.285.09:29:48.04#ibcon#wrote, iclass 22, count 0 2006.285.09:29:48.04#ibcon#about to read 3, iclass 22, count 0 2006.285.09:29:48.06#ibcon#read 3, iclass 22, count 0 2006.285.09:29:48.06#ibcon#about to read 4, iclass 22, count 0 2006.285.09:29:48.06#ibcon#read 4, iclass 22, count 0 2006.285.09:29:48.06#ibcon#about to read 5, iclass 22, count 0 2006.285.09:29:48.06#ibcon#read 5, iclass 22, count 0 2006.285.09:29:48.06#ibcon#about to read 6, iclass 22, count 0 2006.285.09:29:48.06#ibcon#read 6, iclass 22, count 0 2006.285.09:29:48.06#ibcon#end of sib2, iclass 22, count 0 2006.285.09:29:48.06#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:29:48.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:29:48.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:29:48.06#ibcon#*before write, iclass 22, count 0 2006.285.09:29:48.06#ibcon#enter sib2, iclass 22, count 0 2006.285.09:29:48.06#ibcon#flushed, iclass 22, count 0 2006.285.09:29:48.06#ibcon#about to write, iclass 22, count 0 2006.285.09:29:48.06#ibcon#wrote, iclass 22, count 0 2006.285.09:29:48.06#ibcon#about to read 3, iclass 22, count 0 2006.285.09:29:48.10#ibcon#read 3, iclass 22, count 0 2006.285.09:29:48.10#ibcon#about to read 4, iclass 22, count 0 2006.285.09:29:48.10#ibcon#read 4, iclass 22, count 0 2006.285.09:29:48.10#ibcon#about to read 5, iclass 22, count 0 2006.285.09:29:48.10#ibcon#read 5, iclass 22, count 0 2006.285.09:29:48.10#ibcon#about to read 6, iclass 22, count 0 2006.285.09:29:48.10#ibcon#read 6, iclass 22, count 0 2006.285.09:29:48.10#ibcon#end of sib2, iclass 22, count 0 2006.285.09:29:48.10#ibcon#*after write, iclass 22, count 0 2006.285.09:29:48.10#ibcon#*before return 0, iclass 22, count 0 2006.285.09:29:48.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:29:48.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:29:48.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:29:48.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:29:48.10$vck44/vb=3,4 2006.285.09:29:48.10#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.09:29:48.10#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.09:29:48.10#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:48.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:29:48.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:29:48.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:29:48.16#ibcon#enter wrdev, iclass 24, count 2 2006.285.09:29:48.16#ibcon#first serial, iclass 24, count 2 2006.285.09:29:48.16#ibcon#enter sib2, iclass 24, count 2 2006.285.09:29:48.16#ibcon#flushed, iclass 24, count 2 2006.285.09:29:48.16#ibcon#about to write, iclass 24, count 2 2006.285.09:29:48.16#ibcon#wrote, iclass 24, count 2 2006.285.09:29:48.16#ibcon#about to read 3, iclass 24, count 2 2006.285.09:29:48.18#ibcon#read 3, iclass 24, count 2 2006.285.09:29:48.18#ibcon#about to read 4, iclass 24, count 2 2006.285.09:29:48.18#ibcon#read 4, iclass 24, count 2 2006.285.09:29:48.18#ibcon#about to read 5, iclass 24, count 2 2006.285.09:29:48.18#ibcon#read 5, iclass 24, count 2 2006.285.09:29:48.18#ibcon#about to read 6, iclass 24, count 2 2006.285.09:29:48.18#ibcon#read 6, iclass 24, count 2 2006.285.09:29:48.18#ibcon#end of sib2, iclass 24, count 2 2006.285.09:29:48.18#ibcon#*mode == 0, iclass 24, count 2 2006.285.09:29:48.18#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.09:29:48.18#ibcon#[27=AT03-04\r\n] 2006.285.09:29:48.18#ibcon#*before write, iclass 24, count 2 2006.285.09:29:48.18#ibcon#enter sib2, iclass 24, count 2 2006.285.09:29:48.18#ibcon#flushed, iclass 24, count 2 2006.285.09:29:48.18#ibcon#about to write, iclass 24, count 2 2006.285.09:29:48.18#ibcon#wrote, iclass 24, count 2 2006.285.09:29:48.18#ibcon#about to read 3, iclass 24, count 2 2006.285.09:29:48.21#ibcon#read 3, iclass 24, count 2 2006.285.09:29:48.21#ibcon#about to read 4, iclass 24, count 2 2006.285.09:29:48.21#ibcon#read 4, iclass 24, count 2 2006.285.09:29:48.21#ibcon#about to read 5, iclass 24, count 2 2006.285.09:29:48.21#ibcon#read 5, iclass 24, count 2 2006.285.09:29:48.21#ibcon#about to read 6, iclass 24, count 2 2006.285.09:29:48.21#ibcon#read 6, iclass 24, count 2 2006.285.09:29:48.21#ibcon#end of sib2, iclass 24, count 2 2006.285.09:29:48.21#ibcon#*after write, iclass 24, count 2 2006.285.09:29:48.21#ibcon#*before return 0, iclass 24, count 2 2006.285.09:29:48.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:29:48.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:29:48.21#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.09:29:48.21#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:48.21#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:29:48.33#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:29:48.33#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:29:48.33#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:29:48.33#ibcon#first serial, iclass 24, count 0 2006.285.09:29:48.33#ibcon#enter sib2, iclass 24, count 0 2006.285.09:29:48.33#ibcon#flushed, iclass 24, count 0 2006.285.09:29:48.33#ibcon#about to write, iclass 24, count 0 2006.285.09:29:48.33#ibcon#wrote, iclass 24, count 0 2006.285.09:29:48.33#ibcon#about to read 3, iclass 24, count 0 2006.285.09:29:48.35#ibcon#read 3, iclass 24, count 0 2006.285.09:29:48.35#ibcon#about to read 4, iclass 24, count 0 2006.285.09:29:48.35#ibcon#read 4, iclass 24, count 0 2006.285.09:29:48.35#ibcon#about to read 5, iclass 24, count 0 2006.285.09:29:48.35#ibcon#read 5, iclass 24, count 0 2006.285.09:29:48.35#ibcon#about to read 6, iclass 24, count 0 2006.285.09:29:48.35#ibcon#read 6, iclass 24, count 0 2006.285.09:29:48.35#ibcon#end of sib2, iclass 24, count 0 2006.285.09:29:48.35#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:29:48.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:29:48.35#ibcon#[27=USB\r\n] 2006.285.09:29:48.35#ibcon#*before write, iclass 24, count 0 2006.285.09:29:48.35#ibcon#enter sib2, iclass 24, count 0 2006.285.09:29:48.35#ibcon#flushed, iclass 24, count 0 2006.285.09:29:48.35#ibcon#about to write, iclass 24, count 0 2006.285.09:29:48.35#ibcon#wrote, iclass 24, count 0 2006.285.09:29:48.35#ibcon#about to read 3, iclass 24, count 0 2006.285.09:29:48.38#ibcon#read 3, iclass 24, count 0 2006.285.09:29:48.38#ibcon#about to read 4, iclass 24, count 0 2006.285.09:29:48.38#ibcon#read 4, iclass 24, count 0 2006.285.09:29:48.38#ibcon#about to read 5, iclass 24, count 0 2006.285.09:29:48.38#ibcon#read 5, iclass 24, count 0 2006.285.09:29:48.38#ibcon#about to read 6, iclass 24, count 0 2006.285.09:29:48.38#ibcon#read 6, iclass 24, count 0 2006.285.09:29:48.38#ibcon#end of sib2, iclass 24, count 0 2006.285.09:29:48.38#ibcon#*after write, iclass 24, count 0 2006.285.09:29:48.38#ibcon#*before return 0, iclass 24, count 0 2006.285.09:29:48.38#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:29:48.38#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:29:48.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:29:48.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:29:48.38$vck44/vblo=4,679.99 2006.285.09:29:48.38#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.09:29:48.38#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.09:29:48.38#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:48.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:29:48.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:29:48.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:29:48.38#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:29:48.38#ibcon#first serial, iclass 26, count 0 2006.285.09:29:48.38#ibcon#enter sib2, iclass 26, count 0 2006.285.09:29:48.38#ibcon#flushed, iclass 26, count 0 2006.285.09:29:48.38#ibcon#about to write, iclass 26, count 0 2006.285.09:29:48.38#ibcon#wrote, iclass 26, count 0 2006.285.09:29:48.38#ibcon#about to read 3, iclass 26, count 0 2006.285.09:29:48.40#ibcon#read 3, iclass 26, count 0 2006.285.09:29:48.40#ibcon#about to read 4, iclass 26, count 0 2006.285.09:29:48.40#ibcon#read 4, iclass 26, count 0 2006.285.09:29:48.40#ibcon#about to read 5, iclass 26, count 0 2006.285.09:29:48.40#ibcon#read 5, iclass 26, count 0 2006.285.09:29:48.40#ibcon#about to read 6, iclass 26, count 0 2006.285.09:29:48.40#ibcon#read 6, iclass 26, count 0 2006.285.09:29:48.40#ibcon#end of sib2, iclass 26, count 0 2006.285.09:29:48.40#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:29:48.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:29:48.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:29:48.40#ibcon#*before write, iclass 26, count 0 2006.285.09:29:48.40#ibcon#enter sib2, iclass 26, count 0 2006.285.09:29:48.40#ibcon#flushed, iclass 26, count 0 2006.285.09:29:48.40#ibcon#about to write, iclass 26, count 0 2006.285.09:29:48.40#ibcon#wrote, iclass 26, count 0 2006.285.09:29:48.40#ibcon#about to read 3, iclass 26, count 0 2006.285.09:29:48.44#ibcon#read 3, iclass 26, count 0 2006.285.09:29:48.44#ibcon#about to read 4, iclass 26, count 0 2006.285.09:29:48.44#ibcon#read 4, iclass 26, count 0 2006.285.09:29:48.44#ibcon#about to read 5, iclass 26, count 0 2006.285.09:29:48.44#ibcon#read 5, iclass 26, count 0 2006.285.09:29:48.44#ibcon#about to read 6, iclass 26, count 0 2006.285.09:29:48.44#ibcon#read 6, iclass 26, count 0 2006.285.09:29:48.44#ibcon#end of sib2, iclass 26, count 0 2006.285.09:29:48.44#ibcon#*after write, iclass 26, count 0 2006.285.09:29:48.44#ibcon#*before return 0, iclass 26, count 0 2006.285.09:29:48.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:29:48.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:29:48.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:29:48.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:29:48.44$vck44/vb=4,5 2006.285.09:29:48.44#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.09:29:48.44#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.09:29:48.44#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:48.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:29:48.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:29:48.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:29:48.50#ibcon#enter wrdev, iclass 28, count 2 2006.285.09:29:48.50#ibcon#first serial, iclass 28, count 2 2006.285.09:29:48.50#ibcon#enter sib2, iclass 28, count 2 2006.285.09:29:48.50#ibcon#flushed, iclass 28, count 2 2006.285.09:29:48.50#ibcon#about to write, iclass 28, count 2 2006.285.09:29:48.50#ibcon#wrote, iclass 28, count 2 2006.285.09:29:48.50#ibcon#about to read 3, iclass 28, count 2 2006.285.09:29:48.52#ibcon#read 3, iclass 28, count 2 2006.285.09:29:48.52#ibcon#about to read 4, iclass 28, count 2 2006.285.09:29:48.52#ibcon#read 4, iclass 28, count 2 2006.285.09:29:48.52#ibcon#about to read 5, iclass 28, count 2 2006.285.09:29:48.52#ibcon#read 5, iclass 28, count 2 2006.285.09:29:48.52#ibcon#about to read 6, iclass 28, count 2 2006.285.09:29:48.52#ibcon#read 6, iclass 28, count 2 2006.285.09:29:48.52#ibcon#end of sib2, iclass 28, count 2 2006.285.09:29:48.52#ibcon#*mode == 0, iclass 28, count 2 2006.285.09:29:48.52#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.09:29:48.52#ibcon#[27=AT04-05\r\n] 2006.285.09:29:48.52#ibcon#*before write, iclass 28, count 2 2006.285.09:29:48.52#ibcon#enter sib2, iclass 28, count 2 2006.285.09:29:48.52#ibcon#flushed, iclass 28, count 2 2006.285.09:29:48.52#ibcon#about to write, iclass 28, count 2 2006.285.09:29:48.52#ibcon#wrote, iclass 28, count 2 2006.285.09:29:48.52#ibcon#about to read 3, iclass 28, count 2 2006.285.09:29:48.55#ibcon#read 3, iclass 28, count 2 2006.285.09:29:48.55#ibcon#about to read 4, iclass 28, count 2 2006.285.09:29:48.55#ibcon#read 4, iclass 28, count 2 2006.285.09:29:48.55#ibcon#about to read 5, iclass 28, count 2 2006.285.09:29:48.55#ibcon#read 5, iclass 28, count 2 2006.285.09:29:48.55#ibcon#about to read 6, iclass 28, count 2 2006.285.09:29:48.55#ibcon#read 6, iclass 28, count 2 2006.285.09:29:48.55#ibcon#end of sib2, iclass 28, count 2 2006.285.09:29:48.55#ibcon#*after write, iclass 28, count 2 2006.285.09:29:48.55#ibcon#*before return 0, iclass 28, count 2 2006.285.09:29:48.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:29:48.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:29:48.55#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.09:29:48.55#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:48.55#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:29:48.67#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:29:48.67#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:29:48.67#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:29:48.67#ibcon#first serial, iclass 28, count 0 2006.285.09:29:48.67#ibcon#enter sib2, iclass 28, count 0 2006.285.09:29:48.67#ibcon#flushed, iclass 28, count 0 2006.285.09:29:48.67#ibcon#about to write, iclass 28, count 0 2006.285.09:29:48.67#ibcon#wrote, iclass 28, count 0 2006.285.09:29:48.67#ibcon#about to read 3, iclass 28, count 0 2006.285.09:29:48.69#ibcon#read 3, iclass 28, count 0 2006.285.09:29:48.69#ibcon#about to read 4, iclass 28, count 0 2006.285.09:29:48.69#ibcon#read 4, iclass 28, count 0 2006.285.09:29:48.69#ibcon#about to read 5, iclass 28, count 0 2006.285.09:29:48.69#ibcon#read 5, iclass 28, count 0 2006.285.09:29:48.69#ibcon#about to read 6, iclass 28, count 0 2006.285.09:29:48.69#ibcon#read 6, iclass 28, count 0 2006.285.09:29:48.69#ibcon#end of sib2, iclass 28, count 0 2006.285.09:29:48.69#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:29:48.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:29:48.69#ibcon#[27=USB\r\n] 2006.285.09:29:48.69#ibcon#*before write, iclass 28, count 0 2006.285.09:29:48.69#ibcon#enter sib2, iclass 28, count 0 2006.285.09:29:48.69#ibcon#flushed, iclass 28, count 0 2006.285.09:29:48.69#ibcon#about to write, iclass 28, count 0 2006.285.09:29:48.69#ibcon#wrote, iclass 28, count 0 2006.285.09:29:48.69#ibcon#about to read 3, iclass 28, count 0 2006.285.09:29:48.72#ibcon#read 3, iclass 28, count 0 2006.285.09:29:48.72#ibcon#about to read 4, iclass 28, count 0 2006.285.09:29:48.72#ibcon#read 4, iclass 28, count 0 2006.285.09:29:48.72#ibcon#about to read 5, iclass 28, count 0 2006.285.09:29:48.72#ibcon#read 5, iclass 28, count 0 2006.285.09:29:48.72#ibcon#about to read 6, iclass 28, count 0 2006.285.09:29:48.72#ibcon#read 6, iclass 28, count 0 2006.285.09:29:48.72#ibcon#end of sib2, iclass 28, count 0 2006.285.09:29:48.72#ibcon#*after write, iclass 28, count 0 2006.285.09:29:48.72#ibcon#*before return 0, iclass 28, count 0 2006.285.09:29:48.72#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:29:48.72#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:29:48.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:29:48.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:29:48.72$vck44/vblo=5,709.99 2006.285.09:29:48.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.09:29:48.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.09:29:48.72#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:48.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:29:48.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:29:48.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:29:48.72#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:29:48.72#ibcon#first serial, iclass 30, count 0 2006.285.09:29:48.72#ibcon#enter sib2, iclass 30, count 0 2006.285.09:29:48.72#ibcon#flushed, iclass 30, count 0 2006.285.09:29:48.72#ibcon#about to write, iclass 30, count 0 2006.285.09:29:48.72#ibcon#wrote, iclass 30, count 0 2006.285.09:29:48.72#ibcon#about to read 3, iclass 30, count 0 2006.285.09:29:48.74#ibcon#read 3, iclass 30, count 0 2006.285.09:29:48.74#ibcon#about to read 4, iclass 30, count 0 2006.285.09:29:48.74#ibcon#read 4, iclass 30, count 0 2006.285.09:29:48.74#ibcon#about to read 5, iclass 30, count 0 2006.285.09:29:48.74#ibcon#read 5, iclass 30, count 0 2006.285.09:29:48.74#ibcon#about to read 6, iclass 30, count 0 2006.285.09:29:48.74#ibcon#read 6, iclass 30, count 0 2006.285.09:29:48.74#ibcon#end of sib2, iclass 30, count 0 2006.285.09:29:48.74#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:29:48.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:29:48.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:29:48.74#ibcon#*before write, iclass 30, count 0 2006.285.09:29:48.74#ibcon#enter sib2, iclass 30, count 0 2006.285.09:29:48.74#ibcon#flushed, iclass 30, count 0 2006.285.09:29:48.74#ibcon#about to write, iclass 30, count 0 2006.285.09:29:48.74#ibcon#wrote, iclass 30, count 0 2006.285.09:29:48.74#ibcon#about to read 3, iclass 30, count 0 2006.285.09:29:48.78#ibcon#read 3, iclass 30, count 0 2006.285.09:29:48.78#ibcon#about to read 4, iclass 30, count 0 2006.285.09:29:48.78#ibcon#read 4, iclass 30, count 0 2006.285.09:29:48.78#ibcon#about to read 5, iclass 30, count 0 2006.285.09:29:48.78#ibcon#read 5, iclass 30, count 0 2006.285.09:29:48.78#ibcon#about to read 6, iclass 30, count 0 2006.285.09:29:48.78#ibcon#read 6, iclass 30, count 0 2006.285.09:29:48.78#ibcon#end of sib2, iclass 30, count 0 2006.285.09:29:48.78#ibcon#*after write, iclass 30, count 0 2006.285.09:29:48.78#ibcon#*before return 0, iclass 30, count 0 2006.285.09:29:48.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:29:48.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:29:48.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:29:48.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:29:48.78$vck44/vb=5,4 2006.285.09:29:48.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.09:29:48.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.09:29:48.78#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:48.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:29:48.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:29:48.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:29:48.84#ibcon#enter wrdev, iclass 32, count 2 2006.285.09:29:48.84#ibcon#first serial, iclass 32, count 2 2006.285.09:29:48.84#ibcon#enter sib2, iclass 32, count 2 2006.285.09:29:48.84#ibcon#flushed, iclass 32, count 2 2006.285.09:29:48.84#ibcon#about to write, iclass 32, count 2 2006.285.09:29:48.84#ibcon#wrote, iclass 32, count 2 2006.285.09:29:48.84#ibcon#about to read 3, iclass 32, count 2 2006.285.09:29:48.86#ibcon#read 3, iclass 32, count 2 2006.285.09:29:48.86#ibcon#about to read 4, iclass 32, count 2 2006.285.09:29:48.86#ibcon#read 4, iclass 32, count 2 2006.285.09:29:48.86#ibcon#about to read 5, iclass 32, count 2 2006.285.09:29:48.86#ibcon#read 5, iclass 32, count 2 2006.285.09:29:48.86#ibcon#about to read 6, iclass 32, count 2 2006.285.09:29:48.86#ibcon#read 6, iclass 32, count 2 2006.285.09:29:48.86#ibcon#end of sib2, iclass 32, count 2 2006.285.09:29:48.86#ibcon#*mode == 0, iclass 32, count 2 2006.285.09:29:48.86#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.09:29:48.86#ibcon#[27=AT05-04\r\n] 2006.285.09:29:48.86#ibcon#*before write, iclass 32, count 2 2006.285.09:29:48.86#ibcon#enter sib2, iclass 32, count 2 2006.285.09:29:48.86#ibcon#flushed, iclass 32, count 2 2006.285.09:29:48.86#ibcon#about to write, iclass 32, count 2 2006.285.09:29:48.86#ibcon#wrote, iclass 32, count 2 2006.285.09:29:48.86#ibcon#about to read 3, iclass 32, count 2 2006.285.09:29:48.89#ibcon#read 3, iclass 32, count 2 2006.285.09:29:48.89#ibcon#about to read 4, iclass 32, count 2 2006.285.09:29:48.89#ibcon#read 4, iclass 32, count 2 2006.285.09:29:48.89#ibcon#about to read 5, iclass 32, count 2 2006.285.09:29:48.89#ibcon#read 5, iclass 32, count 2 2006.285.09:29:48.89#ibcon#about to read 6, iclass 32, count 2 2006.285.09:29:48.89#ibcon#read 6, iclass 32, count 2 2006.285.09:29:48.89#ibcon#end of sib2, iclass 32, count 2 2006.285.09:29:48.89#ibcon#*after write, iclass 32, count 2 2006.285.09:29:48.89#ibcon#*before return 0, iclass 32, count 2 2006.285.09:29:48.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:29:48.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:29:48.89#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.09:29:48.89#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:48.89#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:29:49.01#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:29:49.01#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:29:49.01#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:29:49.01#ibcon#first serial, iclass 32, count 0 2006.285.09:29:49.01#ibcon#enter sib2, iclass 32, count 0 2006.285.09:29:49.01#ibcon#flushed, iclass 32, count 0 2006.285.09:29:49.01#ibcon#about to write, iclass 32, count 0 2006.285.09:29:49.01#ibcon#wrote, iclass 32, count 0 2006.285.09:29:49.01#ibcon#about to read 3, iclass 32, count 0 2006.285.09:29:49.03#ibcon#read 3, iclass 32, count 0 2006.285.09:29:49.03#ibcon#about to read 4, iclass 32, count 0 2006.285.09:29:49.03#ibcon#read 4, iclass 32, count 0 2006.285.09:29:49.03#ibcon#about to read 5, iclass 32, count 0 2006.285.09:29:49.03#ibcon#read 5, iclass 32, count 0 2006.285.09:29:49.03#ibcon#about to read 6, iclass 32, count 0 2006.285.09:29:49.03#ibcon#read 6, iclass 32, count 0 2006.285.09:29:49.03#ibcon#end of sib2, iclass 32, count 0 2006.285.09:29:49.03#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:29:49.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:29:49.03#ibcon#[27=USB\r\n] 2006.285.09:29:49.03#ibcon#*before write, iclass 32, count 0 2006.285.09:29:49.03#ibcon#enter sib2, iclass 32, count 0 2006.285.09:29:49.03#ibcon#flushed, iclass 32, count 0 2006.285.09:29:49.03#ibcon#about to write, iclass 32, count 0 2006.285.09:29:49.03#ibcon#wrote, iclass 32, count 0 2006.285.09:29:49.03#ibcon#about to read 3, iclass 32, count 0 2006.285.09:29:49.06#ibcon#read 3, iclass 32, count 0 2006.285.09:29:49.06#ibcon#about to read 4, iclass 32, count 0 2006.285.09:29:49.06#ibcon#read 4, iclass 32, count 0 2006.285.09:29:49.06#ibcon#about to read 5, iclass 32, count 0 2006.285.09:29:49.06#ibcon#read 5, iclass 32, count 0 2006.285.09:29:49.06#ibcon#about to read 6, iclass 32, count 0 2006.285.09:29:49.06#ibcon#read 6, iclass 32, count 0 2006.285.09:29:49.06#ibcon#end of sib2, iclass 32, count 0 2006.285.09:29:49.06#ibcon#*after write, iclass 32, count 0 2006.285.09:29:49.06#ibcon#*before return 0, iclass 32, count 0 2006.285.09:29:49.06#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:29:49.06#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:29:49.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:29:49.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:29:49.06$vck44/vblo=6,719.99 2006.285.09:29:49.06#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.09:29:49.06#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.09:29:49.06#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:49.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:29:49.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:29:49.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:29:49.06#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:29:49.06#ibcon#first serial, iclass 34, count 0 2006.285.09:29:49.06#ibcon#enter sib2, iclass 34, count 0 2006.285.09:29:49.06#ibcon#flushed, iclass 34, count 0 2006.285.09:29:49.06#ibcon#about to write, iclass 34, count 0 2006.285.09:29:49.06#ibcon#wrote, iclass 34, count 0 2006.285.09:29:49.07#ibcon#about to read 3, iclass 34, count 0 2006.285.09:29:49.08#ibcon#read 3, iclass 34, count 0 2006.285.09:29:49.08#ibcon#about to read 4, iclass 34, count 0 2006.285.09:29:49.08#ibcon#read 4, iclass 34, count 0 2006.285.09:29:49.08#ibcon#about to read 5, iclass 34, count 0 2006.285.09:29:49.08#ibcon#read 5, iclass 34, count 0 2006.285.09:29:49.08#ibcon#about to read 6, iclass 34, count 0 2006.285.09:29:49.08#ibcon#read 6, iclass 34, count 0 2006.285.09:29:49.08#ibcon#end of sib2, iclass 34, count 0 2006.285.09:29:49.08#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:29:49.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:29:49.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:29:49.08#ibcon#*before write, iclass 34, count 0 2006.285.09:29:49.08#ibcon#enter sib2, iclass 34, count 0 2006.285.09:29:49.08#ibcon#flushed, iclass 34, count 0 2006.285.09:29:49.08#ibcon#about to write, iclass 34, count 0 2006.285.09:29:49.08#ibcon#wrote, iclass 34, count 0 2006.285.09:29:49.08#ibcon#about to read 3, iclass 34, count 0 2006.285.09:29:49.12#ibcon#read 3, iclass 34, count 0 2006.285.09:29:49.12#ibcon#about to read 4, iclass 34, count 0 2006.285.09:29:49.12#ibcon#read 4, iclass 34, count 0 2006.285.09:29:49.12#ibcon#about to read 5, iclass 34, count 0 2006.285.09:29:49.12#ibcon#read 5, iclass 34, count 0 2006.285.09:29:49.12#ibcon#about to read 6, iclass 34, count 0 2006.285.09:29:49.12#ibcon#read 6, iclass 34, count 0 2006.285.09:29:49.12#ibcon#end of sib2, iclass 34, count 0 2006.285.09:29:49.12#ibcon#*after write, iclass 34, count 0 2006.285.09:29:49.12#ibcon#*before return 0, iclass 34, count 0 2006.285.09:29:49.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:29:49.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:29:49.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:29:49.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:29:49.12$vck44/vb=6,3 2006.285.09:29:49.12#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.09:29:49.12#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.09:29:49.12#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:49.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:29:49.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:29:49.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:29:49.18#ibcon#enter wrdev, iclass 36, count 2 2006.285.09:29:49.18#ibcon#first serial, iclass 36, count 2 2006.285.09:29:49.18#ibcon#enter sib2, iclass 36, count 2 2006.285.09:29:49.18#ibcon#flushed, iclass 36, count 2 2006.285.09:29:49.18#ibcon#about to write, iclass 36, count 2 2006.285.09:29:49.18#ibcon#wrote, iclass 36, count 2 2006.285.09:29:49.18#ibcon#about to read 3, iclass 36, count 2 2006.285.09:29:49.20#ibcon#read 3, iclass 36, count 2 2006.285.09:29:49.20#ibcon#about to read 4, iclass 36, count 2 2006.285.09:29:49.20#ibcon#read 4, iclass 36, count 2 2006.285.09:29:49.20#ibcon#about to read 5, iclass 36, count 2 2006.285.09:29:49.20#ibcon#read 5, iclass 36, count 2 2006.285.09:29:49.20#ibcon#about to read 6, iclass 36, count 2 2006.285.09:29:49.20#ibcon#read 6, iclass 36, count 2 2006.285.09:29:49.20#ibcon#end of sib2, iclass 36, count 2 2006.285.09:29:49.20#ibcon#*mode == 0, iclass 36, count 2 2006.285.09:29:49.20#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.09:29:49.20#ibcon#[27=AT06-03\r\n] 2006.285.09:29:49.20#ibcon#*before write, iclass 36, count 2 2006.285.09:29:49.20#ibcon#enter sib2, iclass 36, count 2 2006.285.09:29:49.20#ibcon#flushed, iclass 36, count 2 2006.285.09:29:49.20#ibcon#about to write, iclass 36, count 2 2006.285.09:29:49.20#ibcon#wrote, iclass 36, count 2 2006.285.09:29:49.20#ibcon#about to read 3, iclass 36, count 2 2006.285.09:29:49.23#ibcon#read 3, iclass 36, count 2 2006.285.09:29:49.23#ibcon#about to read 4, iclass 36, count 2 2006.285.09:29:49.23#ibcon#read 4, iclass 36, count 2 2006.285.09:29:49.23#ibcon#about to read 5, iclass 36, count 2 2006.285.09:29:49.23#ibcon#read 5, iclass 36, count 2 2006.285.09:29:49.23#ibcon#about to read 6, iclass 36, count 2 2006.285.09:29:49.23#ibcon#read 6, iclass 36, count 2 2006.285.09:29:49.23#ibcon#end of sib2, iclass 36, count 2 2006.285.09:29:49.23#ibcon#*after write, iclass 36, count 2 2006.285.09:29:49.23#ibcon#*before return 0, iclass 36, count 2 2006.285.09:29:49.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:29:49.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:29:49.23#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.09:29:49.23#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:49.23#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:29:49.35#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:29:49.35#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:29:49.35#ibcon#enter wrdev, iclass 36, count 0 2006.285.09:29:49.35#ibcon#first serial, iclass 36, count 0 2006.285.09:29:49.35#ibcon#enter sib2, iclass 36, count 0 2006.285.09:29:49.35#ibcon#flushed, iclass 36, count 0 2006.285.09:29:49.35#ibcon#about to write, iclass 36, count 0 2006.285.09:29:49.35#ibcon#wrote, iclass 36, count 0 2006.285.09:29:49.35#ibcon#about to read 3, iclass 36, count 0 2006.285.09:29:49.37#ibcon#read 3, iclass 36, count 0 2006.285.09:29:49.37#ibcon#about to read 4, iclass 36, count 0 2006.285.09:29:49.37#ibcon#read 4, iclass 36, count 0 2006.285.09:29:49.37#ibcon#about to read 5, iclass 36, count 0 2006.285.09:29:49.37#ibcon#read 5, iclass 36, count 0 2006.285.09:29:49.37#ibcon#about to read 6, iclass 36, count 0 2006.285.09:29:49.37#ibcon#read 6, iclass 36, count 0 2006.285.09:29:49.37#ibcon#end of sib2, iclass 36, count 0 2006.285.09:29:49.37#ibcon#*mode == 0, iclass 36, count 0 2006.285.09:29:49.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.09:29:49.37#ibcon#[27=USB\r\n] 2006.285.09:29:49.37#ibcon#*before write, iclass 36, count 0 2006.285.09:29:49.37#ibcon#enter sib2, iclass 36, count 0 2006.285.09:29:49.37#ibcon#flushed, iclass 36, count 0 2006.285.09:29:49.37#ibcon#about to write, iclass 36, count 0 2006.285.09:29:49.37#ibcon#wrote, iclass 36, count 0 2006.285.09:29:49.37#ibcon#about to read 3, iclass 36, count 0 2006.285.09:29:49.40#ibcon#read 3, iclass 36, count 0 2006.285.09:29:49.40#ibcon#about to read 4, iclass 36, count 0 2006.285.09:29:49.40#ibcon#read 4, iclass 36, count 0 2006.285.09:29:49.40#ibcon#about to read 5, iclass 36, count 0 2006.285.09:29:49.40#ibcon#read 5, iclass 36, count 0 2006.285.09:29:49.40#ibcon#about to read 6, iclass 36, count 0 2006.285.09:29:49.40#ibcon#read 6, iclass 36, count 0 2006.285.09:29:49.40#ibcon#end of sib2, iclass 36, count 0 2006.285.09:29:49.40#ibcon#*after write, iclass 36, count 0 2006.285.09:29:49.40#ibcon#*before return 0, iclass 36, count 0 2006.285.09:29:49.40#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:29:49.40#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:29:49.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.09:29:49.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.09:29:49.40$vck44/vblo=7,734.99 2006.285.09:29:49.40#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.09:29:49.40#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.09:29:49.40#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:49.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:29:49.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:29:49.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:29:49.40#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:29:49.40#ibcon#first serial, iclass 38, count 0 2006.285.09:29:49.40#ibcon#enter sib2, iclass 38, count 0 2006.285.09:29:49.40#ibcon#flushed, iclass 38, count 0 2006.285.09:29:49.40#ibcon#about to write, iclass 38, count 0 2006.285.09:29:49.40#ibcon#wrote, iclass 38, count 0 2006.285.09:29:49.40#ibcon#about to read 3, iclass 38, count 0 2006.285.09:29:49.42#ibcon#read 3, iclass 38, count 0 2006.285.09:29:49.42#ibcon#about to read 4, iclass 38, count 0 2006.285.09:29:49.42#ibcon#read 4, iclass 38, count 0 2006.285.09:29:49.42#ibcon#about to read 5, iclass 38, count 0 2006.285.09:29:49.42#ibcon#read 5, iclass 38, count 0 2006.285.09:29:49.42#ibcon#about to read 6, iclass 38, count 0 2006.285.09:29:49.42#ibcon#read 6, iclass 38, count 0 2006.285.09:29:49.42#ibcon#end of sib2, iclass 38, count 0 2006.285.09:29:49.42#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:29:49.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:29:49.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:29:49.42#ibcon#*before write, iclass 38, count 0 2006.285.09:29:49.42#ibcon#enter sib2, iclass 38, count 0 2006.285.09:29:49.42#ibcon#flushed, iclass 38, count 0 2006.285.09:29:49.42#ibcon#about to write, iclass 38, count 0 2006.285.09:29:49.42#ibcon#wrote, iclass 38, count 0 2006.285.09:29:49.42#ibcon#about to read 3, iclass 38, count 0 2006.285.09:29:49.46#ibcon#read 3, iclass 38, count 0 2006.285.09:29:49.46#ibcon#about to read 4, iclass 38, count 0 2006.285.09:29:49.46#ibcon#read 4, iclass 38, count 0 2006.285.09:29:49.46#ibcon#about to read 5, iclass 38, count 0 2006.285.09:29:49.46#ibcon#read 5, iclass 38, count 0 2006.285.09:29:49.46#ibcon#about to read 6, iclass 38, count 0 2006.285.09:29:49.46#ibcon#read 6, iclass 38, count 0 2006.285.09:29:49.46#ibcon#end of sib2, iclass 38, count 0 2006.285.09:29:49.46#ibcon#*after write, iclass 38, count 0 2006.285.09:29:49.46#ibcon#*before return 0, iclass 38, count 0 2006.285.09:29:49.46#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:29:49.46#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:29:49.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:29:49.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:29:49.46$vck44/vb=7,4 2006.285.09:29:49.46#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.09:29:49.46#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.09:29:49.46#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:49.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:29:49.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:29:49.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:29:49.52#ibcon#enter wrdev, iclass 40, count 2 2006.285.09:29:49.52#ibcon#first serial, iclass 40, count 2 2006.285.09:29:49.52#ibcon#enter sib2, iclass 40, count 2 2006.285.09:29:49.52#ibcon#flushed, iclass 40, count 2 2006.285.09:29:49.52#ibcon#about to write, iclass 40, count 2 2006.285.09:29:49.52#ibcon#wrote, iclass 40, count 2 2006.285.09:29:49.52#ibcon#about to read 3, iclass 40, count 2 2006.285.09:29:49.54#ibcon#read 3, iclass 40, count 2 2006.285.09:29:49.54#ibcon#about to read 4, iclass 40, count 2 2006.285.09:29:49.54#ibcon#read 4, iclass 40, count 2 2006.285.09:29:49.54#ibcon#about to read 5, iclass 40, count 2 2006.285.09:29:49.54#ibcon#read 5, iclass 40, count 2 2006.285.09:29:49.54#ibcon#about to read 6, iclass 40, count 2 2006.285.09:29:49.54#ibcon#read 6, iclass 40, count 2 2006.285.09:29:49.54#ibcon#end of sib2, iclass 40, count 2 2006.285.09:29:49.54#ibcon#*mode == 0, iclass 40, count 2 2006.285.09:29:49.54#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.09:29:49.54#ibcon#[27=AT07-04\r\n] 2006.285.09:29:49.54#ibcon#*before write, iclass 40, count 2 2006.285.09:29:49.54#ibcon#enter sib2, iclass 40, count 2 2006.285.09:29:49.54#ibcon#flushed, iclass 40, count 2 2006.285.09:29:49.54#ibcon#about to write, iclass 40, count 2 2006.285.09:29:49.54#ibcon#wrote, iclass 40, count 2 2006.285.09:29:49.54#ibcon#about to read 3, iclass 40, count 2 2006.285.09:29:49.57#ibcon#read 3, iclass 40, count 2 2006.285.09:29:49.57#ibcon#about to read 4, iclass 40, count 2 2006.285.09:29:49.57#ibcon#read 4, iclass 40, count 2 2006.285.09:29:49.57#ibcon#about to read 5, iclass 40, count 2 2006.285.09:29:49.57#ibcon#read 5, iclass 40, count 2 2006.285.09:29:49.57#ibcon#about to read 6, iclass 40, count 2 2006.285.09:29:49.57#ibcon#read 6, iclass 40, count 2 2006.285.09:29:49.57#ibcon#end of sib2, iclass 40, count 2 2006.285.09:29:49.57#ibcon#*after write, iclass 40, count 2 2006.285.09:29:49.57#ibcon#*before return 0, iclass 40, count 2 2006.285.09:29:49.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:29:49.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:29:49.57#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.09:29:49.57#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:49.57#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:29:49.69#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:29:49.69#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:29:49.69#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:29:49.69#ibcon#first serial, iclass 40, count 0 2006.285.09:29:49.69#ibcon#enter sib2, iclass 40, count 0 2006.285.09:29:49.69#ibcon#flushed, iclass 40, count 0 2006.285.09:29:49.69#ibcon#about to write, iclass 40, count 0 2006.285.09:29:49.69#ibcon#wrote, iclass 40, count 0 2006.285.09:29:49.69#ibcon#about to read 3, iclass 40, count 0 2006.285.09:29:49.71#ibcon#read 3, iclass 40, count 0 2006.285.09:29:49.71#ibcon#about to read 4, iclass 40, count 0 2006.285.09:29:49.71#ibcon#read 4, iclass 40, count 0 2006.285.09:29:49.71#ibcon#about to read 5, iclass 40, count 0 2006.285.09:29:49.71#ibcon#read 5, iclass 40, count 0 2006.285.09:29:49.71#ibcon#about to read 6, iclass 40, count 0 2006.285.09:29:49.71#ibcon#read 6, iclass 40, count 0 2006.285.09:29:49.71#ibcon#end of sib2, iclass 40, count 0 2006.285.09:29:49.71#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:29:49.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:29:49.71#ibcon#[27=USB\r\n] 2006.285.09:29:49.71#ibcon#*before write, iclass 40, count 0 2006.285.09:29:49.71#ibcon#enter sib2, iclass 40, count 0 2006.285.09:29:49.71#ibcon#flushed, iclass 40, count 0 2006.285.09:29:49.71#ibcon#about to write, iclass 40, count 0 2006.285.09:29:49.71#ibcon#wrote, iclass 40, count 0 2006.285.09:29:49.71#ibcon#about to read 3, iclass 40, count 0 2006.285.09:29:49.74#ibcon#read 3, iclass 40, count 0 2006.285.09:29:49.74#ibcon#about to read 4, iclass 40, count 0 2006.285.09:29:49.74#ibcon#read 4, iclass 40, count 0 2006.285.09:29:49.74#ibcon#about to read 5, iclass 40, count 0 2006.285.09:29:49.74#ibcon#read 5, iclass 40, count 0 2006.285.09:29:49.74#ibcon#about to read 6, iclass 40, count 0 2006.285.09:29:49.74#ibcon#read 6, iclass 40, count 0 2006.285.09:29:49.74#ibcon#end of sib2, iclass 40, count 0 2006.285.09:29:49.74#ibcon#*after write, iclass 40, count 0 2006.285.09:29:49.74#ibcon#*before return 0, iclass 40, count 0 2006.285.09:29:49.74#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:29:49.74#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:29:49.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:29:49.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:29:49.74$vck44/vblo=8,744.99 2006.285.09:29:49.74#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.09:29:49.74#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.09:29:49.74#ibcon#ireg 17 cls_cnt 0 2006.285.09:29:49.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:29:49.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:29:49.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:29:49.74#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:29:49.74#ibcon#first serial, iclass 4, count 0 2006.285.09:29:49.74#ibcon#enter sib2, iclass 4, count 0 2006.285.09:29:49.74#ibcon#flushed, iclass 4, count 0 2006.285.09:29:49.74#ibcon#about to write, iclass 4, count 0 2006.285.09:29:49.74#ibcon#wrote, iclass 4, count 0 2006.285.09:29:49.74#ibcon#about to read 3, iclass 4, count 0 2006.285.09:29:49.76#ibcon#read 3, iclass 4, count 0 2006.285.09:29:49.76#ibcon#about to read 4, iclass 4, count 0 2006.285.09:29:49.76#ibcon#read 4, iclass 4, count 0 2006.285.09:29:49.76#ibcon#about to read 5, iclass 4, count 0 2006.285.09:29:49.76#ibcon#read 5, iclass 4, count 0 2006.285.09:29:49.76#ibcon#about to read 6, iclass 4, count 0 2006.285.09:29:49.76#ibcon#read 6, iclass 4, count 0 2006.285.09:29:49.76#ibcon#end of sib2, iclass 4, count 0 2006.285.09:29:49.76#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:29:49.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:29:49.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:29:49.76#ibcon#*before write, iclass 4, count 0 2006.285.09:29:49.76#ibcon#enter sib2, iclass 4, count 0 2006.285.09:29:49.76#ibcon#flushed, iclass 4, count 0 2006.285.09:29:49.76#ibcon#about to write, iclass 4, count 0 2006.285.09:29:49.76#ibcon#wrote, iclass 4, count 0 2006.285.09:29:49.76#ibcon#about to read 3, iclass 4, count 0 2006.285.09:29:49.80#ibcon#read 3, iclass 4, count 0 2006.285.09:29:49.80#ibcon#about to read 4, iclass 4, count 0 2006.285.09:29:49.80#ibcon#read 4, iclass 4, count 0 2006.285.09:29:49.80#ibcon#about to read 5, iclass 4, count 0 2006.285.09:29:49.80#ibcon#read 5, iclass 4, count 0 2006.285.09:29:49.80#ibcon#about to read 6, iclass 4, count 0 2006.285.09:29:49.80#ibcon#read 6, iclass 4, count 0 2006.285.09:29:49.80#ibcon#end of sib2, iclass 4, count 0 2006.285.09:29:49.80#ibcon#*after write, iclass 4, count 0 2006.285.09:29:49.80#ibcon#*before return 0, iclass 4, count 0 2006.285.09:29:49.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:29:49.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:29:49.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:29:49.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:29:49.80$vck44/vb=8,4 2006.285.09:29:49.80#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.09:29:49.80#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.09:29:49.80#ibcon#ireg 11 cls_cnt 2 2006.285.09:29:49.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:29:49.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:29:49.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:29:49.86#ibcon#enter wrdev, iclass 6, count 2 2006.285.09:29:49.86#ibcon#first serial, iclass 6, count 2 2006.285.09:29:49.86#ibcon#enter sib2, iclass 6, count 2 2006.285.09:29:49.86#ibcon#flushed, iclass 6, count 2 2006.285.09:29:49.86#ibcon#about to write, iclass 6, count 2 2006.285.09:29:49.86#ibcon#wrote, iclass 6, count 2 2006.285.09:29:49.86#ibcon#about to read 3, iclass 6, count 2 2006.285.09:29:49.88#ibcon#read 3, iclass 6, count 2 2006.285.09:29:49.88#ibcon#about to read 4, iclass 6, count 2 2006.285.09:29:49.88#ibcon#read 4, iclass 6, count 2 2006.285.09:29:49.88#ibcon#about to read 5, iclass 6, count 2 2006.285.09:29:49.88#ibcon#read 5, iclass 6, count 2 2006.285.09:29:49.88#ibcon#about to read 6, iclass 6, count 2 2006.285.09:29:49.88#ibcon#read 6, iclass 6, count 2 2006.285.09:29:49.88#ibcon#end of sib2, iclass 6, count 2 2006.285.09:29:49.88#ibcon#*mode == 0, iclass 6, count 2 2006.285.09:29:49.88#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.09:29:49.88#ibcon#[27=AT08-04\r\n] 2006.285.09:29:49.88#ibcon#*before write, iclass 6, count 2 2006.285.09:29:49.88#ibcon#enter sib2, iclass 6, count 2 2006.285.09:29:49.88#ibcon#flushed, iclass 6, count 2 2006.285.09:29:49.88#ibcon#about to write, iclass 6, count 2 2006.285.09:29:49.88#ibcon#wrote, iclass 6, count 2 2006.285.09:29:49.88#ibcon#about to read 3, iclass 6, count 2 2006.285.09:29:49.91#ibcon#read 3, iclass 6, count 2 2006.285.09:29:49.91#ibcon#about to read 4, iclass 6, count 2 2006.285.09:29:49.91#ibcon#read 4, iclass 6, count 2 2006.285.09:29:49.91#ibcon#about to read 5, iclass 6, count 2 2006.285.09:29:49.91#ibcon#read 5, iclass 6, count 2 2006.285.09:29:49.91#ibcon#about to read 6, iclass 6, count 2 2006.285.09:29:49.91#ibcon#read 6, iclass 6, count 2 2006.285.09:29:49.91#ibcon#end of sib2, iclass 6, count 2 2006.285.09:29:49.91#ibcon#*after write, iclass 6, count 2 2006.285.09:29:49.91#ibcon#*before return 0, iclass 6, count 2 2006.285.09:29:49.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:29:49.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:29:49.91#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.09:29:49.91#ibcon#ireg 7 cls_cnt 0 2006.285.09:29:49.91#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:29:50.03#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:29:50.03#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:29:50.03#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:29:50.03#ibcon#first serial, iclass 6, count 0 2006.285.09:29:50.03#ibcon#enter sib2, iclass 6, count 0 2006.285.09:29:50.03#ibcon#flushed, iclass 6, count 0 2006.285.09:29:50.03#ibcon#about to write, iclass 6, count 0 2006.285.09:29:50.03#ibcon#wrote, iclass 6, count 0 2006.285.09:29:50.03#ibcon#about to read 3, iclass 6, count 0 2006.285.09:29:50.05#ibcon#read 3, iclass 6, count 0 2006.285.09:29:50.05#ibcon#about to read 4, iclass 6, count 0 2006.285.09:29:50.05#ibcon#read 4, iclass 6, count 0 2006.285.09:29:50.05#ibcon#about to read 5, iclass 6, count 0 2006.285.09:29:50.05#ibcon#read 5, iclass 6, count 0 2006.285.09:29:50.05#ibcon#about to read 6, iclass 6, count 0 2006.285.09:29:50.05#ibcon#read 6, iclass 6, count 0 2006.285.09:29:50.05#ibcon#end of sib2, iclass 6, count 0 2006.285.09:29:50.05#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:29:50.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:29:50.05#ibcon#[27=USB\r\n] 2006.285.09:29:50.05#ibcon#*before write, iclass 6, count 0 2006.285.09:29:50.05#ibcon#enter sib2, iclass 6, count 0 2006.285.09:29:50.05#ibcon#flushed, iclass 6, count 0 2006.285.09:29:50.05#ibcon#about to write, iclass 6, count 0 2006.285.09:29:50.05#ibcon#wrote, iclass 6, count 0 2006.285.09:29:50.05#ibcon#about to read 3, iclass 6, count 0 2006.285.09:29:50.08#ibcon#read 3, iclass 6, count 0 2006.285.09:29:50.08#ibcon#about to read 4, iclass 6, count 0 2006.285.09:29:50.08#ibcon#read 4, iclass 6, count 0 2006.285.09:29:50.08#ibcon#about to read 5, iclass 6, count 0 2006.285.09:29:50.08#ibcon#read 5, iclass 6, count 0 2006.285.09:29:50.08#ibcon#about to read 6, iclass 6, count 0 2006.285.09:29:50.08#ibcon#read 6, iclass 6, count 0 2006.285.09:29:50.08#ibcon#end of sib2, iclass 6, count 0 2006.285.09:29:50.08#ibcon#*after write, iclass 6, count 0 2006.285.09:29:50.08#ibcon#*before return 0, iclass 6, count 0 2006.285.09:29:50.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:29:50.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:29:50.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:29:50.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:29:50.08$vck44/vabw=wide 2006.285.09:29:50.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.09:29:50.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.09:29:50.08#ibcon#ireg 8 cls_cnt 0 2006.285.09:29:50.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:29:50.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:29:50.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:29:50.08#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:29:50.08#ibcon#first serial, iclass 10, count 0 2006.285.09:29:50.08#ibcon#enter sib2, iclass 10, count 0 2006.285.09:29:50.08#ibcon#flushed, iclass 10, count 0 2006.285.09:29:50.08#ibcon#about to write, iclass 10, count 0 2006.285.09:29:50.08#ibcon#wrote, iclass 10, count 0 2006.285.09:29:50.08#ibcon#about to read 3, iclass 10, count 0 2006.285.09:29:50.10#ibcon#read 3, iclass 10, count 0 2006.285.09:29:50.10#ibcon#about to read 4, iclass 10, count 0 2006.285.09:29:50.10#ibcon#read 4, iclass 10, count 0 2006.285.09:29:50.10#ibcon#about to read 5, iclass 10, count 0 2006.285.09:29:50.10#ibcon#read 5, iclass 10, count 0 2006.285.09:29:50.10#ibcon#about to read 6, iclass 10, count 0 2006.285.09:29:50.10#ibcon#read 6, iclass 10, count 0 2006.285.09:29:50.10#ibcon#end of sib2, iclass 10, count 0 2006.285.09:29:50.10#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:29:50.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:29:50.10#ibcon#[25=BW32\r\n] 2006.285.09:29:50.10#ibcon#*before write, iclass 10, count 0 2006.285.09:29:50.10#ibcon#enter sib2, iclass 10, count 0 2006.285.09:29:50.10#ibcon#flushed, iclass 10, count 0 2006.285.09:29:50.10#ibcon#about to write, iclass 10, count 0 2006.285.09:29:50.10#ibcon#wrote, iclass 10, count 0 2006.285.09:29:50.10#ibcon#about to read 3, iclass 10, count 0 2006.285.09:29:50.13#ibcon#read 3, iclass 10, count 0 2006.285.09:29:50.13#ibcon#about to read 4, iclass 10, count 0 2006.285.09:29:50.13#ibcon#read 4, iclass 10, count 0 2006.285.09:29:50.13#ibcon#about to read 5, iclass 10, count 0 2006.285.09:29:50.13#ibcon#read 5, iclass 10, count 0 2006.285.09:29:50.13#ibcon#about to read 6, iclass 10, count 0 2006.285.09:29:50.13#ibcon#read 6, iclass 10, count 0 2006.285.09:29:50.13#ibcon#end of sib2, iclass 10, count 0 2006.285.09:29:50.13#ibcon#*after write, iclass 10, count 0 2006.285.09:29:50.13#ibcon#*before return 0, iclass 10, count 0 2006.285.09:29:50.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:29:50.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:29:50.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:29:50.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:29:50.13$vck44/vbbw=wide 2006.285.09:29:50.13#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.09:29:50.13#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.09:29:50.13#ibcon#ireg 8 cls_cnt 0 2006.285.09:29:50.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:29:50.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:29:50.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:29:50.20#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:29:50.20#ibcon#first serial, iclass 12, count 0 2006.285.09:29:50.20#ibcon#enter sib2, iclass 12, count 0 2006.285.09:29:50.20#ibcon#flushed, iclass 12, count 0 2006.285.09:29:50.20#ibcon#about to write, iclass 12, count 0 2006.285.09:29:50.20#ibcon#wrote, iclass 12, count 0 2006.285.09:29:50.20#ibcon#about to read 3, iclass 12, count 0 2006.285.09:29:50.22#ibcon#read 3, iclass 12, count 0 2006.285.09:29:50.22#ibcon#about to read 4, iclass 12, count 0 2006.285.09:29:50.22#ibcon#read 4, iclass 12, count 0 2006.285.09:29:50.22#ibcon#about to read 5, iclass 12, count 0 2006.285.09:29:50.22#ibcon#read 5, iclass 12, count 0 2006.285.09:29:50.22#ibcon#about to read 6, iclass 12, count 0 2006.285.09:29:50.22#ibcon#read 6, iclass 12, count 0 2006.285.09:29:50.22#ibcon#end of sib2, iclass 12, count 0 2006.285.09:29:50.22#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:29:50.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:29:50.22#ibcon#[27=BW32\r\n] 2006.285.09:29:50.22#ibcon#*before write, iclass 12, count 0 2006.285.09:29:50.22#ibcon#enter sib2, iclass 12, count 0 2006.285.09:29:50.22#ibcon#flushed, iclass 12, count 0 2006.285.09:29:50.22#ibcon#about to write, iclass 12, count 0 2006.285.09:29:50.22#ibcon#wrote, iclass 12, count 0 2006.285.09:29:50.22#ibcon#about to read 3, iclass 12, count 0 2006.285.09:29:50.25#ibcon#read 3, iclass 12, count 0 2006.285.09:29:50.25#ibcon#about to read 4, iclass 12, count 0 2006.285.09:29:50.25#ibcon#read 4, iclass 12, count 0 2006.285.09:29:50.25#ibcon#about to read 5, iclass 12, count 0 2006.285.09:29:50.25#ibcon#read 5, iclass 12, count 0 2006.285.09:29:50.25#ibcon#about to read 6, iclass 12, count 0 2006.285.09:29:50.25#ibcon#read 6, iclass 12, count 0 2006.285.09:29:50.25#ibcon#end of sib2, iclass 12, count 0 2006.285.09:29:50.25#ibcon#*after write, iclass 12, count 0 2006.285.09:29:50.25#ibcon#*before return 0, iclass 12, count 0 2006.285.09:29:50.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:29:50.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:29:50.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:29:50.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:29:50.25$setupk4/ifdk4 2006.285.09:29:50.25$ifdk4/lo= 2006.285.09:29:50.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:29:50.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:29:50.26$ifdk4/patch= 2006.285.09:29:50.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:29:50.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:29:50.26$setupk4/!*+20s 2006.285.09:29:56.16#abcon#<5=/02 0.6 1.2 19.62 911015.0\r\n> 2006.285.09:29:56.18#abcon#{5=INTERFACE CLEAR} 2006.285.09:29:56.24#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:30:03.13#trakl#Source acquired 2006.285.09:30:04.13#flagr#flagr/antenna,acquired 2006.285.09:30:04.77$setupk4/"tpicd 2006.285.09:30:04.77$setupk4/echo=off 2006.285.09:30:04.77$setupk4/xlog=off 2006.285.09:30:04.77:!2006.285.09:30:36 2006.285.09:30:36.00:preob 2006.285.09:30:36.13/onsource/TRACKING 2006.285.09:30:36.13:!2006.285.09:30:46 2006.285.09:30:46.00:"tape 2006.285.09:30:46.00:"st=record 2006.285.09:30:46.00:data_valid=on 2006.285.09:30:46.00:midob 2006.285.09:30:46.13/onsource/TRACKING 2006.285.09:30:46.14/wx/19.58,1015.0,91 2006.285.09:30:46.34/cable/+6.4827E-03 2006.285.09:30:47.43/va/01,07,usb,yes,32,35 2006.285.09:30:47.43/va/02,06,usb,yes,32,33 2006.285.09:30:47.43/va/03,07,usb,yes,32,34 2006.285.09:30:47.43/va/04,06,usb,yes,33,35 2006.285.09:30:47.43/va/05,03,usb,yes,33,33 2006.285.09:30:47.43/va/06,04,usb,yes,30,29 2006.285.09:30:47.43/va/07,04,usb,yes,30,31 2006.285.09:30:47.43/va/08,03,usb,yes,31,38 2006.285.09:30:47.66/valo/01,524.99,yes,locked 2006.285.09:30:47.66/valo/02,534.99,yes,locked 2006.285.09:30:47.66/valo/03,564.99,yes,locked 2006.285.09:30:47.66/valo/04,624.99,yes,locked 2006.285.09:30:47.66/valo/05,734.99,yes,locked 2006.285.09:30:47.66/valo/06,814.99,yes,locked 2006.285.09:30:47.66/valo/07,864.99,yes,locked 2006.285.09:30:47.66/valo/08,884.99,yes,locked 2006.285.09:30:48.75/vb/01,04,usb,yes,31,28 2006.285.09:30:48.75/vb/02,05,usb,yes,29,29 2006.285.09:30:48.75/vb/03,04,usb,yes,30,33 2006.285.09:30:48.75/vb/04,05,usb,yes,30,29 2006.285.09:30:48.75/vb/05,04,usb,yes,27,29 2006.285.09:30:48.75/vb/06,03,usb,yes,38,34 2006.285.09:30:48.75/vb/07,04,usb,yes,31,31 2006.285.09:30:48.75/vb/08,04,usb,yes,28,32 2006.285.09:30:48.98/vblo/01,629.99,yes,locked 2006.285.09:30:48.98/vblo/02,634.99,yes,locked 2006.285.09:30:48.98/vblo/03,649.99,yes,locked 2006.285.09:30:48.98/vblo/04,679.99,yes,locked 2006.285.09:30:48.98/vblo/05,709.99,yes,locked 2006.285.09:30:48.98/vblo/06,719.99,yes,locked 2006.285.09:30:48.98/vblo/07,734.99,yes,locked 2006.285.09:30:48.98/vblo/08,744.99,yes,locked 2006.285.09:30:49.13/vabw/8 2006.285.09:30:49.28/vbbw/8 2006.285.09:30:49.47/xfe/off,on,12.0 2006.285.09:30:49.85/ifatt/23,28,28,28 2006.285.09:30:50.07/fmout-gps/S +2.69E-07 2006.285.09:30:50.09:!2006.285.09:31:46 2006.285.09:31:46.00:data_valid=off 2006.285.09:31:46.00:"et 2006.285.09:31:46.00:!+3s 2006.285.09:31:49.03:"tape 2006.285.09:31:49.03:postob 2006.285.09:31:49.22/cable/+6.4824E-03 2006.285.09:31:49.22/wx/19.53,1015.0,91 2006.285.09:31:49.28/fmout-gps/S +2.66E-07 2006.285.09:31:49.28:scan_name=285-0934,jd0610,110 2006.285.09:31:49.28:source=2128-123,213135.26,-120704.8,2000.0,cw 2006.285.09:31:50.14#flagr#flagr/antenna,new-source 2006.285.09:31:50.15:checkk5 2006.285.09:31:50.80/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:31:51.25/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:31:51.63/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:31:52.00/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:31:52.38/chk_obsdata//k5ts1/T2850930??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.09:31:52.79/chk_obsdata//k5ts2/T2850930??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.09:31:53.41/chk_obsdata//k5ts3/T2850930??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.09:31:53.80/chk_obsdata//k5ts4/T2850930??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.09:31:54.67/k5log//k5ts1_log_newline 2006.285.09:31:55.36/k5log//k5ts2_log_newline 2006.285.09:31:56.29/k5log//k5ts3_log_newline 2006.285.09:31:57.05/k5log//k5ts4_log_newline 2006.285.09:31:57.07/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:31:57.07:setupk4=1 2006.285.09:31:57.07$setupk4/echo=on 2006.285.09:31:57.07$setupk4/pcalon 2006.285.09:31:57.07$pcalon/"no phase cal control is implemented here 2006.285.09:31:57.07$setupk4/"tpicd=stop 2006.285.09:31:57.07$setupk4/"rec=synch_on 2006.285.09:31:57.07$setupk4/"rec_mode=128 2006.285.09:31:57.07$setupk4/!* 2006.285.09:31:57.07$setupk4/recpk4 2006.285.09:31:57.07$recpk4/recpatch= 2006.285.09:31:57.07$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:31:57.07$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:31:57.07$setupk4/vck44 2006.285.09:31:57.07$vck44/valo=1,524.99 2006.285.09:31:57.07#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.09:31:57.07#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.09:31:57.07#ibcon#ireg 17 cls_cnt 0 2006.285.09:31:57.07#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:31:57.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:31:57.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:31:57.07#ibcon#enter wrdev, iclass 29, count 0 2006.285.09:31:57.07#ibcon#first serial, iclass 29, count 0 2006.285.09:31:57.07#ibcon#enter sib2, iclass 29, count 0 2006.285.09:31:57.07#ibcon#flushed, iclass 29, count 0 2006.285.09:31:57.07#ibcon#about to write, iclass 29, count 0 2006.285.09:31:57.07#ibcon#wrote, iclass 29, count 0 2006.285.09:31:57.07#ibcon#about to read 3, iclass 29, count 0 2006.285.09:31:57.09#ibcon#read 3, iclass 29, count 0 2006.285.09:31:57.09#ibcon#about to read 4, iclass 29, count 0 2006.285.09:31:57.09#ibcon#read 4, iclass 29, count 0 2006.285.09:31:57.09#ibcon#about to read 5, iclass 29, count 0 2006.285.09:31:57.09#ibcon#read 5, iclass 29, count 0 2006.285.09:31:57.09#ibcon#about to read 6, iclass 29, count 0 2006.285.09:31:57.09#ibcon#read 6, iclass 29, count 0 2006.285.09:31:57.09#ibcon#end of sib2, iclass 29, count 0 2006.285.09:31:57.09#ibcon#*mode == 0, iclass 29, count 0 2006.285.09:31:57.09#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.09:31:57.09#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:31:57.09#ibcon#*before write, iclass 29, count 0 2006.285.09:31:57.09#ibcon#enter sib2, iclass 29, count 0 2006.285.09:31:57.09#ibcon#flushed, iclass 29, count 0 2006.285.09:31:57.09#ibcon#about to write, iclass 29, count 0 2006.285.09:31:57.09#ibcon#wrote, iclass 29, count 0 2006.285.09:31:57.09#ibcon#about to read 3, iclass 29, count 0 2006.285.09:31:57.14#ibcon#read 3, iclass 29, count 0 2006.285.09:31:57.14#ibcon#about to read 4, iclass 29, count 0 2006.285.09:31:57.14#ibcon#read 4, iclass 29, count 0 2006.285.09:31:57.14#ibcon#about to read 5, iclass 29, count 0 2006.285.09:31:57.14#ibcon#read 5, iclass 29, count 0 2006.285.09:31:57.14#ibcon#about to read 6, iclass 29, count 0 2006.285.09:31:57.14#ibcon#read 6, iclass 29, count 0 2006.285.09:31:57.14#ibcon#end of sib2, iclass 29, count 0 2006.285.09:31:57.14#ibcon#*after write, iclass 29, count 0 2006.285.09:31:57.14#ibcon#*before return 0, iclass 29, count 0 2006.285.09:31:57.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:31:57.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:31:57.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.09:31:57.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.09:31:57.14$vck44/va=1,7 2006.285.09:31:57.14#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.09:31:57.14#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.09:31:57.14#ibcon#ireg 11 cls_cnt 2 2006.285.09:31:57.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:31:57.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:31:57.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:31:57.14#ibcon#enter wrdev, iclass 31, count 2 2006.285.09:31:57.14#ibcon#first serial, iclass 31, count 2 2006.285.09:31:57.14#ibcon#enter sib2, iclass 31, count 2 2006.285.09:31:57.14#ibcon#flushed, iclass 31, count 2 2006.285.09:31:57.14#ibcon#about to write, iclass 31, count 2 2006.285.09:31:57.14#ibcon#wrote, iclass 31, count 2 2006.285.09:31:57.14#ibcon#about to read 3, iclass 31, count 2 2006.285.09:31:57.16#ibcon#read 3, iclass 31, count 2 2006.285.09:31:57.16#ibcon#about to read 4, iclass 31, count 2 2006.285.09:31:57.16#ibcon#read 4, iclass 31, count 2 2006.285.09:31:57.16#ibcon#about to read 5, iclass 31, count 2 2006.285.09:31:57.16#ibcon#read 5, iclass 31, count 2 2006.285.09:31:57.16#ibcon#about to read 6, iclass 31, count 2 2006.285.09:31:57.16#ibcon#read 6, iclass 31, count 2 2006.285.09:31:57.16#ibcon#end of sib2, iclass 31, count 2 2006.285.09:31:57.16#ibcon#*mode == 0, iclass 31, count 2 2006.285.09:31:57.16#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.09:31:57.16#ibcon#[25=AT01-07\r\n] 2006.285.09:31:57.16#ibcon#*before write, iclass 31, count 2 2006.285.09:31:57.16#ibcon#enter sib2, iclass 31, count 2 2006.285.09:31:57.16#ibcon#flushed, iclass 31, count 2 2006.285.09:31:57.16#ibcon#about to write, iclass 31, count 2 2006.285.09:31:57.16#ibcon#wrote, iclass 31, count 2 2006.285.09:31:57.16#ibcon#about to read 3, iclass 31, count 2 2006.285.09:31:57.19#ibcon#read 3, iclass 31, count 2 2006.285.09:31:57.19#ibcon#about to read 4, iclass 31, count 2 2006.285.09:31:57.19#ibcon#read 4, iclass 31, count 2 2006.285.09:31:57.19#ibcon#about to read 5, iclass 31, count 2 2006.285.09:31:57.19#ibcon#read 5, iclass 31, count 2 2006.285.09:31:57.19#ibcon#about to read 6, iclass 31, count 2 2006.285.09:31:57.19#ibcon#read 6, iclass 31, count 2 2006.285.09:31:57.19#ibcon#end of sib2, iclass 31, count 2 2006.285.09:31:57.19#ibcon#*after write, iclass 31, count 2 2006.285.09:31:57.19#ibcon#*before return 0, iclass 31, count 2 2006.285.09:31:57.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:31:57.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:31:57.19#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.09:31:57.19#ibcon#ireg 7 cls_cnt 0 2006.285.09:31:57.19#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:31:57.31#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:31:57.31#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:31:57.31#ibcon#enter wrdev, iclass 31, count 0 2006.285.09:31:57.31#ibcon#first serial, iclass 31, count 0 2006.285.09:31:57.31#ibcon#enter sib2, iclass 31, count 0 2006.285.09:31:57.31#ibcon#flushed, iclass 31, count 0 2006.285.09:31:57.31#ibcon#about to write, iclass 31, count 0 2006.285.09:31:57.31#ibcon#wrote, iclass 31, count 0 2006.285.09:31:57.31#ibcon#about to read 3, iclass 31, count 0 2006.285.09:31:57.33#ibcon#read 3, iclass 31, count 0 2006.285.09:31:57.33#ibcon#about to read 4, iclass 31, count 0 2006.285.09:31:57.33#ibcon#read 4, iclass 31, count 0 2006.285.09:31:57.33#ibcon#about to read 5, iclass 31, count 0 2006.285.09:31:57.33#ibcon#read 5, iclass 31, count 0 2006.285.09:31:57.33#ibcon#about to read 6, iclass 31, count 0 2006.285.09:31:57.33#ibcon#read 6, iclass 31, count 0 2006.285.09:31:57.33#ibcon#end of sib2, iclass 31, count 0 2006.285.09:31:57.33#ibcon#*mode == 0, iclass 31, count 0 2006.285.09:31:57.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.09:31:57.33#ibcon#[25=USB\r\n] 2006.285.09:31:57.33#ibcon#*before write, iclass 31, count 0 2006.285.09:31:57.33#ibcon#enter sib2, iclass 31, count 0 2006.285.09:31:57.33#ibcon#flushed, iclass 31, count 0 2006.285.09:31:57.33#ibcon#about to write, iclass 31, count 0 2006.285.09:31:57.33#ibcon#wrote, iclass 31, count 0 2006.285.09:31:57.33#ibcon#about to read 3, iclass 31, count 0 2006.285.09:31:57.36#ibcon#read 3, iclass 31, count 0 2006.285.09:31:57.36#ibcon#about to read 4, iclass 31, count 0 2006.285.09:31:57.36#ibcon#read 4, iclass 31, count 0 2006.285.09:31:57.36#ibcon#about to read 5, iclass 31, count 0 2006.285.09:31:57.36#ibcon#read 5, iclass 31, count 0 2006.285.09:31:57.36#ibcon#about to read 6, iclass 31, count 0 2006.285.09:31:57.36#ibcon#read 6, iclass 31, count 0 2006.285.09:31:57.36#ibcon#end of sib2, iclass 31, count 0 2006.285.09:31:57.36#ibcon#*after write, iclass 31, count 0 2006.285.09:31:57.36#ibcon#*before return 0, iclass 31, count 0 2006.285.09:31:57.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:31:57.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:31:57.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.09:31:57.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.09:31:57.36$vck44/valo=2,534.99 2006.285.09:31:57.36#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.09:31:57.36#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.09:31:57.36#ibcon#ireg 17 cls_cnt 0 2006.285.09:31:57.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:31:57.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:31:57.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:31:57.36#ibcon#enter wrdev, iclass 33, count 0 2006.285.09:31:57.36#ibcon#first serial, iclass 33, count 0 2006.285.09:31:57.36#ibcon#enter sib2, iclass 33, count 0 2006.285.09:31:57.36#ibcon#flushed, iclass 33, count 0 2006.285.09:31:57.36#ibcon#about to write, iclass 33, count 0 2006.285.09:31:57.36#ibcon#wrote, iclass 33, count 0 2006.285.09:31:57.36#ibcon#about to read 3, iclass 33, count 0 2006.285.09:31:57.38#ibcon#read 3, iclass 33, count 0 2006.285.09:31:57.38#ibcon#about to read 4, iclass 33, count 0 2006.285.09:31:57.38#ibcon#read 4, iclass 33, count 0 2006.285.09:31:57.38#ibcon#about to read 5, iclass 33, count 0 2006.285.09:31:57.38#ibcon#read 5, iclass 33, count 0 2006.285.09:31:57.38#ibcon#about to read 6, iclass 33, count 0 2006.285.09:31:57.38#ibcon#read 6, iclass 33, count 0 2006.285.09:31:57.38#ibcon#end of sib2, iclass 33, count 0 2006.285.09:31:57.38#ibcon#*mode == 0, iclass 33, count 0 2006.285.09:31:57.38#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.09:31:57.38#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:31:57.38#ibcon#*before write, iclass 33, count 0 2006.285.09:31:57.38#ibcon#enter sib2, iclass 33, count 0 2006.285.09:31:57.38#ibcon#flushed, iclass 33, count 0 2006.285.09:31:57.38#ibcon#about to write, iclass 33, count 0 2006.285.09:31:57.38#ibcon#wrote, iclass 33, count 0 2006.285.09:31:57.38#ibcon#about to read 3, iclass 33, count 0 2006.285.09:31:57.42#ibcon#read 3, iclass 33, count 0 2006.285.09:31:57.42#ibcon#about to read 4, iclass 33, count 0 2006.285.09:31:57.42#ibcon#read 4, iclass 33, count 0 2006.285.09:31:57.42#ibcon#about to read 5, iclass 33, count 0 2006.285.09:31:57.42#ibcon#read 5, iclass 33, count 0 2006.285.09:31:57.42#ibcon#about to read 6, iclass 33, count 0 2006.285.09:31:57.42#ibcon#read 6, iclass 33, count 0 2006.285.09:31:57.42#ibcon#end of sib2, iclass 33, count 0 2006.285.09:31:57.42#ibcon#*after write, iclass 33, count 0 2006.285.09:31:57.42#ibcon#*before return 0, iclass 33, count 0 2006.285.09:31:57.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:31:57.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:31:57.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.09:31:57.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.09:31:57.42$vck44/va=2,6 2006.285.09:31:57.42#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.09:31:57.42#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.09:31:57.42#ibcon#ireg 11 cls_cnt 2 2006.285.09:31:57.42#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:31:57.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:31:57.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:31:57.48#ibcon#enter wrdev, iclass 35, count 2 2006.285.09:31:57.48#ibcon#first serial, iclass 35, count 2 2006.285.09:31:57.48#ibcon#enter sib2, iclass 35, count 2 2006.285.09:31:57.48#ibcon#flushed, iclass 35, count 2 2006.285.09:31:57.48#ibcon#about to write, iclass 35, count 2 2006.285.09:31:57.48#ibcon#wrote, iclass 35, count 2 2006.285.09:31:57.48#ibcon#about to read 3, iclass 35, count 2 2006.285.09:31:57.50#ibcon#read 3, iclass 35, count 2 2006.285.09:31:57.50#ibcon#about to read 4, iclass 35, count 2 2006.285.09:31:57.50#ibcon#read 4, iclass 35, count 2 2006.285.09:31:57.50#ibcon#about to read 5, iclass 35, count 2 2006.285.09:31:57.50#ibcon#read 5, iclass 35, count 2 2006.285.09:31:57.50#ibcon#about to read 6, iclass 35, count 2 2006.285.09:31:57.50#ibcon#read 6, iclass 35, count 2 2006.285.09:31:57.50#ibcon#end of sib2, iclass 35, count 2 2006.285.09:31:57.50#ibcon#*mode == 0, iclass 35, count 2 2006.285.09:31:57.50#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.09:31:57.50#ibcon#[25=AT02-06\r\n] 2006.285.09:31:57.50#ibcon#*before write, iclass 35, count 2 2006.285.09:31:57.50#ibcon#enter sib2, iclass 35, count 2 2006.285.09:31:57.50#ibcon#flushed, iclass 35, count 2 2006.285.09:31:57.50#ibcon#about to write, iclass 35, count 2 2006.285.09:31:57.50#ibcon#wrote, iclass 35, count 2 2006.285.09:31:57.50#ibcon#about to read 3, iclass 35, count 2 2006.285.09:31:57.53#ibcon#read 3, iclass 35, count 2 2006.285.09:31:57.53#ibcon#about to read 4, iclass 35, count 2 2006.285.09:31:57.53#ibcon#read 4, iclass 35, count 2 2006.285.09:31:57.53#ibcon#about to read 5, iclass 35, count 2 2006.285.09:31:57.53#ibcon#read 5, iclass 35, count 2 2006.285.09:31:57.53#ibcon#about to read 6, iclass 35, count 2 2006.285.09:31:57.53#ibcon#read 6, iclass 35, count 2 2006.285.09:31:57.53#ibcon#end of sib2, iclass 35, count 2 2006.285.09:31:57.53#ibcon#*after write, iclass 35, count 2 2006.285.09:31:57.53#ibcon#*before return 0, iclass 35, count 2 2006.285.09:31:57.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:31:57.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:31:57.53#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.09:31:57.53#ibcon#ireg 7 cls_cnt 0 2006.285.09:31:57.53#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:31:57.65#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:31:57.65#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:31:57.65#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:31:57.65#ibcon#first serial, iclass 35, count 0 2006.285.09:31:57.65#ibcon#enter sib2, iclass 35, count 0 2006.285.09:31:57.65#ibcon#flushed, iclass 35, count 0 2006.285.09:31:57.65#ibcon#about to write, iclass 35, count 0 2006.285.09:31:57.65#ibcon#wrote, iclass 35, count 0 2006.285.09:31:57.65#ibcon#about to read 3, iclass 35, count 0 2006.285.09:31:57.67#ibcon#read 3, iclass 35, count 0 2006.285.09:31:57.67#ibcon#about to read 4, iclass 35, count 0 2006.285.09:31:57.67#ibcon#read 4, iclass 35, count 0 2006.285.09:31:57.67#ibcon#about to read 5, iclass 35, count 0 2006.285.09:31:57.67#ibcon#read 5, iclass 35, count 0 2006.285.09:31:57.67#ibcon#about to read 6, iclass 35, count 0 2006.285.09:31:57.67#ibcon#read 6, iclass 35, count 0 2006.285.09:31:57.67#ibcon#end of sib2, iclass 35, count 0 2006.285.09:31:57.67#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:31:57.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:31:57.67#ibcon#[25=USB\r\n] 2006.285.09:31:57.67#ibcon#*before write, iclass 35, count 0 2006.285.09:31:57.67#ibcon#enter sib2, iclass 35, count 0 2006.285.09:31:57.67#ibcon#flushed, iclass 35, count 0 2006.285.09:31:57.67#ibcon#about to write, iclass 35, count 0 2006.285.09:31:57.67#ibcon#wrote, iclass 35, count 0 2006.285.09:31:57.67#ibcon#about to read 3, iclass 35, count 0 2006.285.09:31:57.70#ibcon#read 3, iclass 35, count 0 2006.285.09:31:57.70#ibcon#about to read 4, iclass 35, count 0 2006.285.09:31:57.70#ibcon#read 4, iclass 35, count 0 2006.285.09:31:57.70#ibcon#about to read 5, iclass 35, count 0 2006.285.09:31:57.70#ibcon#read 5, iclass 35, count 0 2006.285.09:31:57.70#ibcon#about to read 6, iclass 35, count 0 2006.285.09:31:57.70#ibcon#read 6, iclass 35, count 0 2006.285.09:31:57.70#ibcon#end of sib2, iclass 35, count 0 2006.285.09:31:57.70#ibcon#*after write, iclass 35, count 0 2006.285.09:31:57.70#ibcon#*before return 0, iclass 35, count 0 2006.285.09:31:57.70#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:31:57.70#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:31:57.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:31:57.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:31:57.70$vck44/valo=3,564.99 2006.285.09:31:57.70#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.09:31:57.70#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.09:31:57.70#ibcon#ireg 17 cls_cnt 0 2006.285.09:31:57.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:31:57.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:31:57.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:31:57.70#ibcon#enter wrdev, iclass 37, count 0 2006.285.09:31:57.70#ibcon#first serial, iclass 37, count 0 2006.285.09:31:57.70#ibcon#enter sib2, iclass 37, count 0 2006.285.09:31:57.70#ibcon#flushed, iclass 37, count 0 2006.285.09:31:57.70#ibcon#about to write, iclass 37, count 0 2006.285.09:31:57.70#ibcon#wrote, iclass 37, count 0 2006.285.09:31:57.70#ibcon#about to read 3, iclass 37, count 0 2006.285.09:31:57.72#ibcon#read 3, iclass 37, count 0 2006.285.09:31:57.72#ibcon#about to read 4, iclass 37, count 0 2006.285.09:31:57.72#ibcon#read 4, iclass 37, count 0 2006.285.09:31:57.72#ibcon#about to read 5, iclass 37, count 0 2006.285.09:31:57.72#ibcon#read 5, iclass 37, count 0 2006.285.09:31:57.72#ibcon#about to read 6, iclass 37, count 0 2006.285.09:31:57.72#ibcon#read 6, iclass 37, count 0 2006.285.09:31:57.72#ibcon#end of sib2, iclass 37, count 0 2006.285.09:31:57.72#ibcon#*mode == 0, iclass 37, count 0 2006.285.09:31:57.72#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.09:31:57.72#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:31:57.72#ibcon#*before write, iclass 37, count 0 2006.285.09:31:57.72#ibcon#enter sib2, iclass 37, count 0 2006.285.09:31:57.72#ibcon#flushed, iclass 37, count 0 2006.285.09:31:57.72#ibcon#about to write, iclass 37, count 0 2006.285.09:31:57.72#ibcon#wrote, iclass 37, count 0 2006.285.09:31:57.72#ibcon#about to read 3, iclass 37, count 0 2006.285.09:31:57.76#ibcon#read 3, iclass 37, count 0 2006.285.09:31:57.76#ibcon#about to read 4, iclass 37, count 0 2006.285.09:31:57.76#ibcon#read 4, iclass 37, count 0 2006.285.09:31:57.76#ibcon#about to read 5, iclass 37, count 0 2006.285.09:31:57.76#ibcon#read 5, iclass 37, count 0 2006.285.09:31:57.76#ibcon#about to read 6, iclass 37, count 0 2006.285.09:31:57.76#ibcon#read 6, iclass 37, count 0 2006.285.09:31:57.76#ibcon#end of sib2, iclass 37, count 0 2006.285.09:31:57.76#ibcon#*after write, iclass 37, count 0 2006.285.09:31:57.76#ibcon#*before return 0, iclass 37, count 0 2006.285.09:31:57.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:31:57.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:31:57.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.09:31:57.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.09:31:57.76$vck44/va=3,7 2006.285.09:31:57.76#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.09:31:57.76#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.09:31:57.76#ibcon#ireg 11 cls_cnt 2 2006.285.09:31:57.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:31:57.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:31:57.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:31:57.82#ibcon#enter wrdev, iclass 39, count 2 2006.285.09:31:57.82#ibcon#first serial, iclass 39, count 2 2006.285.09:31:57.82#ibcon#enter sib2, iclass 39, count 2 2006.285.09:31:57.82#ibcon#flushed, iclass 39, count 2 2006.285.09:31:57.82#ibcon#about to write, iclass 39, count 2 2006.285.09:31:57.82#ibcon#wrote, iclass 39, count 2 2006.285.09:31:57.82#ibcon#about to read 3, iclass 39, count 2 2006.285.09:31:57.84#ibcon#read 3, iclass 39, count 2 2006.285.09:31:57.84#ibcon#about to read 4, iclass 39, count 2 2006.285.09:31:57.84#ibcon#read 4, iclass 39, count 2 2006.285.09:31:57.84#ibcon#about to read 5, iclass 39, count 2 2006.285.09:31:57.84#ibcon#read 5, iclass 39, count 2 2006.285.09:31:57.84#ibcon#about to read 6, iclass 39, count 2 2006.285.09:31:57.84#ibcon#read 6, iclass 39, count 2 2006.285.09:31:57.84#ibcon#end of sib2, iclass 39, count 2 2006.285.09:31:57.84#ibcon#*mode == 0, iclass 39, count 2 2006.285.09:31:57.84#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.09:31:57.84#ibcon#[25=AT03-07\r\n] 2006.285.09:31:57.84#ibcon#*before write, iclass 39, count 2 2006.285.09:31:57.84#ibcon#enter sib2, iclass 39, count 2 2006.285.09:31:57.84#ibcon#flushed, iclass 39, count 2 2006.285.09:31:57.84#ibcon#about to write, iclass 39, count 2 2006.285.09:31:57.84#ibcon#wrote, iclass 39, count 2 2006.285.09:31:57.84#ibcon#about to read 3, iclass 39, count 2 2006.285.09:31:57.87#ibcon#read 3, iclass 39, count 2 2006.285.09:31:57.87#ibcon#about to read 4, iclass 39, count 2 2006.285.09:31:57.87#ibcon#read 4, iclass 39, count 2 2006.285.09:31:57.87#ibcon#about to read 5, iclass 39, count 2 2006.285.09:31:57.87#ibcon#read 5, iclass 39, count 2 2006.285.09:31:57.87#ibcon#about to read 6, iclass 39, count 2 2006.285.09:31:57.87#ibcon#read 6, iclass 39, count 2 2006.285.09:31:57.87#ibcon#end of sib2, iclass 39, count 2 2006.285.09:31:57.87#ibcon#*after write, iclass 39, count 2 2006.285.09:31:57.87#ibcon#*before return 0, iclass 39, count 2 2006.285.09:31:57.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:31:57.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:31:57.87#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.09:31:57.87#ibcon#ireg 7 cls_cnt 0 2006.285.09:31:57.87#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:31:57.99#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:31:57.99#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:31:57.99#ibcon#enter wrdev, iclass 39, count 0 2006.285.09:31:57.99#ibcon#first serial, iclass 39, count 0 2006.285.09:31:57.99#ibcon#enter sib2, iclass 39, count 0 2006.285.09:31:57.99#ibcon#flushed, iclass 39, count 0 2006.285.09:31:57.99#ibcon#about to write, iclass 39, count 0 2006.285.09:31:57.99#ibcon#wrote, iclass 39, count 0 2006.285.09:31:57.99#ibcon#about to read 3, iclass 39, count 0 2006.285.09:31:58.01#ibcon#read 3, iclass 39, count 0 2006.285.09:31:58.01#ibcon#about to read 4, iclass 39, count 0 2006.285.09:31:58.01#ibcon#read 4, iclass 39, count 0 2006.285.09:31:58.01#ibcon#about to read 5, iclass 39, count 0 2006.285.09:31:58.01#ibcon#read 5, iclass 39, count 0 2006.285.09:31:58.01#ibcon#about to read 6, iclass 39, count 0 2006.285.09:31:58.01#ibcon#read 6, iclass 39, count 0 2006.285.09:31:58.01#ibcon#end of sib2, iclass 39, count 0 2006.285.09:31:58.01#ibcon#*mode == 0, iclass 39, count 0 2006.285.09:31:58.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.09:31:58.01#ibcon#[25=USB\r\n] 2006.285.09:31:58.01#ibcon#*before write, iclass 39, count 0 2006.285.09:31:58.01#ibcon#enter sib2, iclass 39, count 0 2006.285.09:31:58.01#ibcon#flushed, iclass 39, count 0 2006.285.09:31:58.01#ibcon#about to write, iclass 39, count 0 2006.285.09:31:58.01#ibcon#wrote, iclass 39, count 0 2006.285.09:31:58.01#ibcon#about to read 3, iclass 39, count 0 2006.285.09:31:58.04#ibcon#read 3, iclass 39, count 0 2006.285.09:31:58.04#ibcon#about to read 4, iclass 39, count 0 2006.285.09:31:58.04#ibcon#read 4, iclass 39, count 0 2006.285.09:31:58.04#ibcon#about to read 5, iclass 39, count 0 2006.285.09:31:58.04#ibcon#read 5, iclass 39, count 0 2006.285.09:31:58.04#ibcon#about to read 6, iclass 39, count 0 2006.285.09:31:58.04#ibcon#read 6, iclass 39, count 0 2006.285.09:31:58.04#ibcon#end of sib2, iclass 39, count 0 2006.285.09:31:58.04#ibcon#*after write, iclass 39, count 0 2006.285.09:31:58.04#ibcon#*before return 0, iclass 39, count 0 2006.285.09:31:58.04#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:31:58.04#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:31:58.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.09:31:58.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.09:31:58.04$vck44/valo=4,624.99 2006.285.09:31:58.04#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.09:31:58.04#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.09:31:58.04#ibcon#ireg 17 cls_cnt 0 2006.285.09:31:58.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:31:58.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:31:58.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:31:58.04#ibcon#enter wrdev, iclass 3, count 0 2006.285.09:31:58.04#ibcon#first serial, iclass 3, count 0 2006.285.09:31:58.04#ibcon#enter sib2, iclass 3, count 0 2006.285.09:31:58.04#ibcon#flushed, iclass 3, count 0 2006.285.09:31:58.04#ibcon#about to write, iclass 3, count 0 2006.285.09:31:58.04#ibcon#wrote, iclass 3, count 0 2006.285.09:31:58.04#ibcon#about to read 3, iclass 3, count 0 2006.285.09:31:58.06#ibcon#read 3, iclass 3, count 0 2006.285.09:31:58.06#ibcon#about to read 4, iclass 3, count 0 2006.285.09:31:58.06#ibcon#read 4, iclass 3, count 0 2006.285.09:31:58.06#ibcon#about to read 5, iclass 3, count 0 2006.285.09:31:58.06#ibcon#read 5, iclass 3, count 0 2006.285.09:31:58.06#ibcon#about to read 6, iclass 3, count 0 2006.285.09:31:58.06#ibcon#read 6, iclass 3, count 0 2006.285.09:31:58.06#ibcon#end of sib2, iclass 3, count 0 2006.285.09:31:58.06#ibcon#*mode == 0, iclass 3, count 0 2006.285.09:31:58.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.09:31:58.06#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:31:58.06#ibcon#*before write, iclass 3, count 0 2006.285.09:31:58.06#ibcon#enter sib2, iclass 3, count 0 2006.285.09:31:58.06#ibcon#flushed, iclass 3, count 0 2006.285.09:31:58.06#ibcon#about to write, iclass 3, count 0 2006.285.09:31:58.06#ibcon#wrote, iclass 3, count 0 2006.285.09:31:58.06#ibcon#about to read 3, iclass 3, count 0 2006.285.09:31:58.10#ibcon#read 3, iclass 3, count 0 2006.285.09:31:58.10#ibcon#about to read 4, iclass 3, count 0 2006.285.09:31:58.10#ibcon#read 4, iclass 3, count 0 2006.285.09:31:58.10#ibcon#about to read 5, iclass 3, count 0 2006.285.09:31:58.10#ibcon#read 5, iclass 3, count 0 2006.285.09:31:58.10#ibcon#about to read 6, iclass 3, count 0 2006.285.09:31:58.10#ibcon#read 6, iclass 3, count 0 2006.285.09:31:58.10#ibcon#end of sib2, iclass 3, count 0 2006.285.09:31:58.10#ibcon#*after write, iclass 3, count 0 2006.285.09:31:58.10#ibcon#*before return 0, iclass 3, count 0 2006.285.09:31:58.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:31:58.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:31:58.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.09:31:58.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.09:31:58.10$vck44/va=4,6 2006.285.09:31:58.10#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.09:31:58.10#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.09:31:58.10#ibcon#ireg 11 cls_cnt 2 2006.285.09:31:58.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:31:58.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:31:58.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:31:58.16#ibcon#enter wrdev, iclass 5, count 2 2006.285.09:31:58.16#ibcon#first serial, iclass 5, count 2 2006.285.09:31:58.16#ibcon#enter sib2, iclass 5, count 2 2006.285.09:31:58.16#ibcon#flushed, iclass 5, count 2 2006.285.09:31:58.16#ibcon#about to write, iclass 5, count 2 2006.285.09:31:58.16#ibcon#wrote, iclass 5, count 2 2006.285.09:31:58.16#ibcon#about to read 3, iclass 5, count 2 2006.285.09:31:58.18#ibcon#read 3, iclass 5, count 2 2006.285.09:31:58.18#ibcon#about to read 4, iclass 5, count 2 2006.285.09:31:58.18#ibcon#read 4, iclass 5, count 2 2006.285.09:31:58.18#ibcon#about to read 5, iclass 5, count 2 2006.285.09:31:58.18#ibcon#read 5, iclass 5, count 2 2006.285.09:31:58.18#ibcon#about to read 6, iclass 5, count 2 2006.285.09:31:58.18#ibcon#read 6, iclass 5, count 2 2006.285.09:31:58.18#ibcon#end of sib2, iclass 5, count 2 2006.285.09:31:58.18#ibcon#*mode == 0, iclass 5, count 2 2006.285.09:31:58.18#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.09:31:58.18#ibcon#[25=AT04-06\r\n] 2006.285.09:31:58.18#ibcon#*before write, iclass 5, count 2 2006.285.09:31:58.18#ibcon#enter sib2, iclass 5, count 2 2006.285.09:31:58.18#ibcon#flushed, iclass 5, count 2 2006.285.09:31:58.18#ibcon#about to write, iclass 5, count 2 2006.285.09:31:58.18#ibcon#wrote, iclass 5, count 2 2006.285.09:31:58.18#ibcon#about to read 3, iclass 5, count 2 2006.285.09:31:58.20#abcon#<5=/02 0.8 1.3 19.52 911015.0\r\n> 2006.285.09:31:58.21#ibcon#read 3, iclass 5, count 2 2006.285.09:31:58.21#ibcon#about to read 4, iclass 5, count 2 2006.285.09:31:58.21#ibcon#read 4, iclass 5, count 2 2006.285.09:31:58.21#ibcon#about to read 5, iclass 5, count 2 2006.285.09:31:58.21#ibcon#read 5, iclass 5, count 2 2006.285.09:31:58.21#ibcon#about to read 6, iclass 5, count 2 2006.285.09:31:58.21#ibcon#read 6, iclass 5, count 2 2006.285.09:31:58.21#ibcon#end of sib2, iclass 5, count 2 2006.285.09:31:58.21#ibcon#*after write, iclass 5, count 2 2006.285.09:31:58.21#ibcon#*before return 0, iclass 5, count 2 2006.285.09:31:58.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:31:58.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:31:58.21#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.09:31:58.21#ibcon#ireg 7 cls_cnt 0 2006.285.09:31:58.21#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:31:58.22#abcon#{5=INTERFACE CLEAR} 2006.285.09:31:58.28#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:31:58.33#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:31:58.33#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:31:58.33#ibcon#enter wrdev, iclass 5, count 0 2006.285.09:31:58.33#ibcon#first serial, iclass 5, count 0 2006.285.09:31:58.33#ibcon#enter sib2, iclass 5, count 0 2006.285.09:31:58.33#ibcon#flushed, iclass 5, count 0 2006.285.09:31:58.33#ibcon#about to write, iclass 5, count 0 2006.285.09:31:58.33#ibcon#wrote, iclass 5, count 0 2006.285.09:31:58.33#ibcon#about to read 3, iclass 5, count 0 2006.285.09:31:58.35#ibcon#read 3, iclass 5, count 0 2006.285.09:31:58.35#ibcon#about to read 4, iclass 5, count 0 2006.285.09:31:58.35#ibcon#read 4, iclass 5, count 0 2006.285.09:31:58.35#ibcon#about to read 5, iclass 5, count 0 2006.285.09:31:58.35#ibcon#read 5, iclass 5, count 0 2006.285.09:31:58.35#ibcon#about to read 6, iclass 5, count 0 2006.285.09:31:58.35#ibcon#read 6, iclass 5, count 0 2006.285.09:31:58.35#ibcon#end of sib2, iclass 5, count 0 2006.285.09:31:58.35#ibcon#*mode == 0, iclass 5, count 0 2006.285.09:31:58.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.09:31:58.35#ibcon#[25=USB\r\n] 2006.285.09:31:58.35#ibcon#*before write, iclass 5, count 0 2006.285.09:31:58.35#ibcon#enter sib2, iclass 5, count 0 2006.285.09:31:58.35#ibcon#flushed, iclass 5, count 0 2006.285.09:31:58.35#ibcon#about to write, iclass 5, count 0 2006.285.09:31:58.35#ibcon#wrote, iclass 5, count 0 2006.285.09:31:58.35#ibcon#about to read 3, iclass 5, count 0 2006.285.09:31:58.38#ibcon#read 3, iclass 5, count 0 2006.285.09:31:58.38#ibcon#about to read 4, iclass 5, count 0 2006.285.09:31:58.38#ibcon#read 4, iclass 5, count 0 2006.285.09:31:58.38#ibcon#about to read 5, iclass 5, count 0 2006.285.09:31:58.38#ibcon#read 5, iclass 5, count 0 2006.285.09:31:58.38#ibcon#about to read 6, iclass 5, count 0 2006.285.09:31:58.38#ibcon#read 6, iclass 5, count 0 2006.285.09:31:58.38#ibcon#end of sib2, iclass 5, count 0 2006.285.09:31:58.38#ibcon#*after write, iclass 5, count 0 2006.285.09:31:58.38#ibcon#*before return 0, iclass 5, count 0 2006.285.09:31:58.38#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:31:58.38#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:31:58.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.09:31:58.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.09:31:58.38$vck44/valo=5,734.99 2006.285.09:31:58.38#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.09:31:58.38#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.09:31:58.38#ibcon#ireg 17 cls_cnt 0 2006.285.09:31:58.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:31:58.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:31:58.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:31:58.38#ibcon#enter wrdev, iclass 13, count 0 2006.285.09:31:58.38#ibcon#first serial, iclass 13, count 0 2006.285.09:31:58.38#ibcon#enter sib2, iclass 13, count 0 2006.285.09:31:58.38#ibcon#flushed, iclass 13, count 0 2006.285.09:31:58.38#ibcon#about to write, iclass 13, count 0 2006.285.09:31:58.38#ibcon#wrote, iclass 13, count 0 2006.285.09:31:58.38#ibcon#about to read 3, iclass 13, count 0 2006.285.09:31:58.40#ibcon#read 3, iclass 13, count 0 2006.285.09:31:58.40#ibcon#about to read 4, iclass 13, count 0 2006.285.09:31:58.40#ibcon#read 4, iclass 13, count 0 2006.285.09:31:58.40#ibcon#about to read 5, iclass 13, count 0 2006.285.09:31:58.40#ibcon#read 5, iclass 13, count 0 2006.285.09:31:58.40#ibcon#about to read 6, iclass 13, count 0 2006.285.09:31:58.40#ibcon#read 6, iclass 13, count 0 2006.285.09:31:58.40#ibcon#end of sib2, iclass 13, count 0 2006.285.09:31:58.40#ibcon#*mode == 0, iclass 13, count 0 2006.285.09:31:58.40#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.09:31:58.40#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:31:58.40#ibcon#*before write, iclass 13, count 0 2006.285.09:31:58.40#ibcon#enter sib2, iclass 13, count 0 2006.285.09:31:58.40#ibcon#flushed, iclass 13, count 0 2006.285.09:31:58.40#ibcon#about to write, iclass 13, count 0 2006.285.09:31:58.40#ibcon#wrote, iclass 13, count 0 2006.285.09:31:58.40#ibcon#about to read 3, iclass 13, count 0 2006.285.09:31:58.44#ibcon#read 3, iclass 13, count 0 2006.285.09:31:58.44#ibcon#about to read 4, iclass 13, count 0 2006.285.09:31:58.44#ibcon#read 4, iclass 13, count 0 2006.285.09:31:58.44#ibcon#about to read 5, iclass 13, count 0 2006.285.09:31:58.44#ibcon#read 5, iclass 13, count 0 2006.285.09:31:58.44#ibcon#about to read 6, iclass 13, count 0 2006.285.09:31:58.44#ibcon#read 6, iclass 13, count 0 2006.285.09:31:58.44#ibcon#end of sib2, iclass 13, count 0 2006.285.09:31:58.44#ibcon#*after write, iclass 13, count 0 2006.285.09:31:58.44#ibcon#*before return 0, iclass 13, count 0 2006.285.09:31:58.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:31:58.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:31:58.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.09:31:58.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.09:31:58.44$vck44/va=5,3 2006.285.09:31:58.44#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.09:31:58.44#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.09:31:58.44#ibcon#ireg 11 cls_cnt 2 2006.285.09:31:58.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:31:58.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:31:58.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:31:58.50#ibcon#enter wrdev, iclass 15, count 2 2006.285.09:31:58.50#ibcon#first serial, iclass 15, count 2 2006.285.09:31:58.50#ibcon#enter sib2, iclass 15, count 2 2006.285.09:31:58.50#ibcon#flushed, iclass 15, count 2 2006.285.09:31:58.50#ibcon#about to write, iclass 15, count 2 2006.285.09:31:58.50#ibcon#wrote, iclass 15, count 2 2006.285.09:31:58.50#ibcon#about to read 3, iclass 15, count 2 2006.285.09:31:58.52#ibcon#read 3, iclass 15, count 2 2006.285.09:31:58.52#ibcon#about to read 4, iclass 15, count 2 2006.285.09:31:58.52#ibcon#read 4, iclass 15, count 2 2006.285.09:31:58.52#ibcon#about to read 5, iclass 15, count 2 2006.285.09:31:58.52#ibcon#read 5, iclass 15, count 2 2006.285.09:31:58.52#ibcon#about to read 6, iclass 15, count 2 2006.285.09:31:58.52#ibcon#read 6, iclass 15, count 2 2006.285.09:31:58.52#ibcon#end of sib2, iclass 15, count 2 2006.285.09:31:58.52#ibcon#*mode == 0, iclass 15, count 2 2006.285.09:31:58.52#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.09:31:58.52#ibcon#[25=AT05-03\r\n] 2006.285.09:31:58.52#ibcon#*before write, iclass 15, count 2 2006.285.09:31:58.52#ibcon#enter sib2, iclass 15, count 2 2006.285.09:31:58.52#ibcon#flushed, iclass 15, count 2 2006.285.09:31:58.52#ibcon#about to write, iclass 15, count 2 2006.285.09:31:58.52#ibcon#wrote, iclass 15, count 2 2006.285.09:31:58.52#ibcon#about to read 3, iclass 15, count 2 2006.285.09:31:58.55#ibcon#read 3, iclass 15, count 2 2006.285.09:31:58.55#ibcon#about to read 4, iclass 15, count 2 2006.285.09:31:58.55#ibcon#read 4, iclass 15, count 2 2006.285.09:31:58.55#ibcon#about to read 5, iclass 15, count 2 2006.285.09:31:58.55#ibcon#read 5, iclass 15, count 2 2006.285.09:31:58.55#ibcon#about to read 6, iclass 15, count 2 2006.285.09:31:58.55#ibcon#read 6, iclass 15, count 2 2006.285.09:31:58.55#ibcon#end of sib2, iclass 15, count 2 2006.285.09:31:58.55#ibcon#*after write, iclass 15, count 2 2006.285.09:31:58.55#ibcon#*before return 0, iclass 15, count 2 2006.285.09:31:58.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:31:58.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:31:58.55#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.09:31:58.55#ibcon#ireg 7 cls_cnt 0 2006.285.09:31:58.55#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:31:58.67#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:31:58.67#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:31:58.67#ibcon#enter wrdev, iclass 15, count 0 2006.285.09:31:58.67#ibcon#first serial, iclass 15, count 0 2006.285.09:31:58.67#ibcon#enter sib2, iclass 15, count 0 2006.285.09:31:58.67#ibcon#flushed, iclass 15, count 0 2006.285.09:31:58.67#ibcon#about to write, iclass 15, count 0 2006.285.09:31:58.67#ibcon#wrote, iclass 15, count 0 2006.285.09:31:58.67#ibcon#about to read 3, iclass 15, count 0 2006.285.09:31:58.69#ibcon#read 3, iclass 15, count 0 2006.285.09:31:58.69#ibcon#about to read 4, iclass 15, count 0 2006.285.09:31:58.69#ibcon#read 4, iclass 15, count 0 2006.285.09:31:58.69#ibcon#about to read 5, iclass 15, count 0 2006.285.09:31:58.69#ibcon#read 5, iclass 15, count 0 2006.285.09:31:58.69#ibcon#about to read 6, iclass 15, count 0 2006.285.09:31:58.69#ibcon#read 6, iclass 15, count 0 2006.285.09:31:58.69#ibcon#end of sib2, iclass 15, count 0 2006.285.09:31:58.69#ibcon#*mode == 0, iclass 15, count 0 2006.285.09:31:58.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.09:31:58.69#ibcon#[25=USB\r\n] 2006.285.09:31:58.69#ibcon#*before write, iclass 15, count 0 2006.285.09:31:58.69#ibcon#enter sib2, iclass 15, count 0 2006.285.09:31:58.69#ibcon#flushed, iclass 15, count 0 2006.285.09:31:58.69#ibcon#about to write, iclass 15, count 0 2006.285.09:31:58.69#ibcon#wrote, iclass 15, count 0 2006.285.09:31:58.69#ibcon#about to read 3, iclass 15, count 0 2006.285.09:31:58.72#ibcon#read 3, iclass 15, count 0 2006.285.09:31:58.72#ibcon#about to read 4, iclass 15, count 0 2006.285.09:31:58.72#ibcon#read 4, iclass 15, count 0 2006.285.09:31:58.72#ibcon#about to read 5, iclass 15, count 0 2006.285.09:31:58.72#ibcon#read 5, iclass 15, count 0 2006.285.09:31:58.72#ibcon#about to read 6, iclass 15, count 0 2006.285.09:31:58.72#ibcon#read 6, iclass 15, count 0 2006.285.09:31:58.72#ibcon#end of sib2, iclass 15, count 0 2006.285.09:31:58.72#ibcon#*after write, iclass 15, count 0 2006.285.09:31:58.72#ibcon#*before return 0, iclass 15, count 0 2006.285.09:31:58.72#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:31:58.72#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:31:58.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.09:31:58.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.09:31:58.72$vck44/valo=6,814.99 2006.285.09:31:58.72#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.09:31:58.72#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.09:31:58.72#ibcon#ireg 17 cls_cnt 0 2006.285.09:31:58.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:31:58.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:31:58.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:31:58.72#ibcon#enter wrdev, iclass 17, count 0 2006.285.09:31:58.72#ibcon#first serial, iclass 17, count 0 2006.285.09:31:58.72#ibcon#enter sib2, iclass 17, count 0 2006.285.09:31:58.72#ibcon#flushed, iclass 17, count 0 2006.285.09:31:58.72#ibcon#about to write, iclass 17, count 0 2006.285.09:31:58.72#ibcon#wrote, iclass 17, count 0 2006.285.09:31:58.72#ibcon#about to read 3, iclass 17, count 0 2006.285.09:31:58.74#ibcon#read 3, iclass 17, count 0 2006.285.09:31:58.74#ibcon#about to read 4, iclass 17, count 0 2006.285.09:31:58.74#ibcon#read 4, iclass 17, count 0 2006.285.09:31:58.74#ibcon#about to read 5, iclass 17, count 0 2006.285.09:31:58.74#ibcon#read 5, iclass 17, count 0 2006.285.09:31:58.74#ibcon#about to read 6, iclass 17, count 0 2006.285.09:31:58.74#ibcon#read 6, iclass 17, count 0 2006.285.09:31:58.74#ibcon#end of sib2, iclass 17, count 0 2006.285.09:31:58.74#ibcon#*mode == 0, iclass 17, count 0 2006.285.09:31:58.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.09:31:58.74#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:31:58.74#ibcon#*before write, iclass 17, count 0 2006.285.09:31:58.74#ibcon#enter sib2, iclass 17, count 0 2006.285.09:31:58.74#ibcon#flushed, iclass 17, count 0 2006.285.09:31:58.74#ibcon#about to write, iclass 17, count 0 2006.285.09:31:58.74#ibcon#wrote, iclass 17, count 0 2006.285.09:31:58.74#ibcon#about to read 3, iclass 17, count 0 2006.285.09:31:58.78#ibcon#read 3, iclass 17, count 0 2006.285.09:31:58.78#ibcon#about to read 4, iclass 17, count 0 2006.285.09:31:58.78#ibcon#read 4, iclass 17, count 0 2006.285.09:31:58.78#ibcon#about to read 5, iclass 17, count 0 2006.285.09:31:58.78#ibcon#read 5, iclass 17, count 0 2006.285.09:31:58.78#ibcon#about to read 6, iclass 17, count 0 2006.285.09:31:58.78#ibcon#read 6, iclass 17, count 0 2006.285.09:31:58.78#ibcon#end of sib2, iclass 17, count 0 2006.285.09:31:58.78#ibcon#*after write, iclass 17, count 0 2006.285.09:31:58.78#ibcon#*before return 0, iclass 17, count 0 2006.285.09:31:58.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:31:58.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:31:58.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.09:31:58.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.09:31:58.78$vck44/va=6,4 2006.285.09:31:58.78#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.09:31:58.78#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.09:31:58.78#ibcon#ireg 11 cls_cnt 2 2006.285.09:31:58.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:31:58.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:31:58.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:31:58.84#ibcon#enter wrdev, iclass 19, count 2 2006.285.09:31:58.84#ibcon#first serial, iclass 19, count 2 2006.285.09:31:58.84#ibcon#enter sib2, iclass 19, count 2 2006.285.09:31:58.84#ibcon#flushed, iclass 19, count 2 2006.285.09:31:58.84#ibcon#about to write, iclass 19, count 2 2006.285.09:31:58.84#ibcon#wrote, iclass 19, count 2 2006.285.09:31:58.84#ibcon#about to read 3, iclass 19, count 2 2006.285.09:31:58.86#ibcon#read 3, iclass 19, count 2 2006.285.09:31:58.86#ibcon#about to read 4, iclass 19, count 2 2006.285.09:31:58.86#ibcon#read 4, iclass 19, count 2 2006.285.09:31:58.86#ibcon#about to read 5, iclass 19, count 2 2006.285.09:31:58.86#ibcon#read 5, iclass 19, count 2 2006.285.09:31:58.86#ibcon#about to read 6, iclass 19, count 2 2006.285.09:31:58.86#ibcon#read 6, iclass 19, count 2 2006.285.09:31:58.86#ibcon#end of sib2, iclass 19, count 2 2006.285.09:31:58.86#ibcon#*mode == 0, iclass 19, count 2 2006.285.09:31:58.86#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.09:31:58.86#ibcon#[25=AT06-04\r\n] 2006.285.09:31:58.86#ibcon#*before write, iclass 19, count 2 2006.285.09:31:58.86#ibcon#enter sib2, iclass 19, count 2 2006.285.09:31:58.86#ibcon#flushed, iclass 19, count 2 2006.285.09:31:58.86#ibcon#about to write, iclass 19, count 2 2006.285.09:31:58.86#ibcon#wrote, iclass 19, count 2 2006.285.09:31:58.86#ibcon#about to read 3, iclass 19, count 2 2006.285.09:31:58.89#ibcon#read 3, iclass 19, count 2 2006.285.09:31:58.89#ibcon#about to read 4, iclass 19, count 2 2006.285.09:31:58.89#ibcon#read 4, iclass 19, count 2 2006.285.09:31:58.89#ibcon#about to read 5, iclass 19, count 2 2006.285.09:31:58.89#ibcon#read 5, iclass 19, count 2 2006.285.09:31:58.89#ibcon#about to read 6, iclass 19, count 2 2006.285.09:31:58.89#ibcon#read 6, iclass 19, count 2 2006.285.09:31:58.89#ibcon#end of sib2, iclass 19, count 2 2006.285.09:31:58.89#ibcon#*after write, iclass 19, count 2 2006.285.09:31:58.89#ibcon#*before return 0, iclass 19, count 2 2006.285.09:31:58.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:31:58.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:31:58.89#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.09:31:58.89#ibcon#ireg 7 cls_cnt 0 2006.285.09:31:58.89#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:31:59.01#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:31:59.01#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:31:59.01#ibcon#enter wrdev, iclass 19, count 0 2006.285.09:31:59.01#ibcon#first serial, iclass 19, count 0 2006.285.09:31:59.01#ibcon#enter sib2, iclass 19, count 0 2006.285.09:31:59.01#ibcon#flushed, iclass 19, count 0 2006.285.09:31:59.01#ibcon#about to write, iclass 19, count 0 2006.285.09:31:59.01#ibcon#wrote, iclass 19, count 0 2006.285.09:31:59.01#ibcon#about to read 3, iclass 19, count 0 2006.285.09:31:59.03#ibcon#read 3, iclass 19, count 0 2006.285.09:31:59.03#ibcon#about to read 4, iclass 19, count 0 2006.285.09:31:59.03#ibcon#read 4, iclass 19, count 0 2006.285.09:31:59.03#ibcon#about to read 5, iclass 19, count 0 2006.285.09:31:59.03#ibcon#read 5, iclass 19, count 0 2006.285.09:31:59.03#ibcon#about to read 6, iclass 19, count 0 2006.285.09:31:59.03#ibcon#read 6, iclass 19, count 0 2006.285.09:31:59.03#ibcon#end of sib2, iclass 19, count 0 2006.285.09:31:59.03#ibcon#*mode == 0, iclass 19, count 0 2006.285.09:31:59.03#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.09:31:59.03#ibcon#[25=USB\r\n] 2006.285.09:31:59.03#ibcon#*before write, iclass 19, count 0 2006.285.09:31:59.03#ibcon#enter sib2, iclass 19, count 0 2006.285.09:31:59.03#ibcon#flushed, iclass 19, count 0 2006.285.09:31:59.03#ibcon#about to write, iclass 19, count 0 2006.285.09:31:59.03#ibcon#wrote, iclass 19, count 0 2006.285.09:31:59.03#ibcon#about to read 3, iclass 19, count 0 2006.285.09:31:59.06#ibcon#read 3, iclass 19, count 0 2006.285.09:31:59.06#ibcon#about to read 4, iclass 19, count 0 2006.285.09:31:59.06#ibcon#read 4, iclass 19, count 0 2006.285.09:31:59.06#ibcon#about to read 5, iclass 19, count 0 2006.285.09:31:59.06#ibcon#read 5, iclass 19, count 0 2006.285.09:31:59.06#ibcon#about to read 6, iclass 19, count 0 2006.285.09:31:59.06#ibcon#read 6, iclass 19, count 0 2006.285.09:31:59.06#ibcon#end of sib2, iclass 19, count 0 2006.285.09:31:59.06#ibcon#*after write, iclass 19, count 0 2006.285.09:31:59.06#ibcon#*before return 0, iclass 19, count 0 2006.285.09:31:59.06#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:31:59.06#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:31:59.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.09:31:59.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.09:31:59.06$vck44/valo=7,864.99 2006.285.09:31:59.06#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.09:31:59.06#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.09:31:59.06#ibcon#ireg 17 cls_cnt 0 2006.285.09:31:59.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:31:59.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:31:59.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:31:59.06#ibcon#enter wrdev, iclass 21, count 0 2006.285.09:31:59.06#ibcon#first serial, iclass 21, count 0 2006.285.09:31:59.06#ibcon#enter sib2, iclass 21, count 0 2006.285.09:31:59.06#ibcon#flushed, iclass 21, count 0 2006.285.09:31:59.06#ibcon#about to write, iclass 21, count 0 2006.285.09:31:59.06#ibcon#wrote, iclass 21, count 0 2006.285.09:31:59.06#ibcon#about to read 3, iclass 21, count 0 2006.285.09:31:59.08#ibcon#read 3, iclass 21, count 0 2006.285.09:31:59.08#ibcon#about to read 4, iclass 21, count 0 2006.285.09:31:59.08#ibcon#read 4, iclass 21, count 0 2006.285.09:31:59.08#ibcon#about to read 5, iclass 21, count 0 2006.285.09:31:59.08#ibcon#read 5, iclass 21, count 0 2006.285.09:31:59.08#ibcon#about to read 6, iclass 21, count 0 2006.285.09:31:59.08#ibcon#read 6, iclass 21, count 0 2006.285.09:31:59.08#ibcon#end of sib2, iclass 21, count 0 2006.285.09:31:59.08#ibcon#*mode == 0, iclass 21, count 0 2006.285.09:31:59.08#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.09:31:59.08#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:31:59.08#ibcon#*before write, iclass 21, count 0 2006.285.09:31:59.08#ibcon#enter sib2, iclass 21, count 0 2006.285.09:31:59.08#ibcon#flushed, iclass 21, count 0 2006.285.09:31:59.08#ibcon#about to write, iclass 21, count 0 2006.285.09:31:59.08#ibcon#wrote, iclass 21, count 0 2006.285.09:31:59.08#ibcon#about to read 3, iclass 21, count 0 2006.285.09:31:59.12#ibcon#read 3, iclass 21, count 0 2006.285.09:31:59.12#ibcon#about to read 4, iclass 21, count 0 2006.285.09:31:59.12#ibcon#read 4, iclass 21, count 0 2006.285.09:31:59.12#ibcon#about to read 5, iclass 21, count 0 2006.285.09:31:59.12#ibcon#read 5, iclass 21, count 0 2006.285.09:31:59.12#ibcon#about to read 6, iclass 21, count 0 2006.285.09:31:59.12#ibcon#read 6, iclass 21, count 0 2006.285.09:31:59.12#ibcon#end of sib2, iclass 21, count 0 2006.285.09:31:59.12#ibcon#*after write, iclass 21, count 0 2006.285.09:31:59.12#ibcon#*before return 0, iclass 21, count 0 2006.285.09:31:59.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:31:59.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:31:59.12#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.09:31:59.12#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.09:31:59.12$vck44/va=7,4 2006.285.09:31:59.12#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.09:31:59.12#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.09:31:59.12#ibcon#ireg 11 cls_cnt 2 2006.285.09:31:59.12#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:31:59.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:31:59.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:31:59.18#ibcon#enter wrdev, iclass 23, count 2 2006.285.09:31:59.18#ibcon#first serial, iclass 23, count 2 2006.285.09:31:59.18#ibcon#enter sib2, iclass 23, count 2 2006.285.09:31:59.18#ibcon#flushed, iclass 23, count 2 2006.285.09:31:59.18#ibcon#about to write, iclass 23, count 2 2006.285.09:31:59.18#ibcon#wrote, iclass 23, count 2 2006.285.09:31:59.18#ibcon#about to read 3, iclass 23, count 2 2006.285.09:31:59.20#ibcon#read 3, iclass 23, count 2 2006.285.09:31:59.20#ibcon#about to read 4, iclass 23, count 2 2006.285.09:31:59.20#ibcon#read 4, iclass 23, count 2 2006.285.09:31:59.20#ibcon#about to read 5, iclass 23, count 2 2006.285.09:31:59.20#ibcon#read 5, iclass 23, count 2 2006.285.09:31:59.20#ibcon#about to read 6, iclass 23, count 2 2006.285.09:31:59.20#ibcon#read 6, iclass 23, count 2 2006.285.09:31:59.20#ibcon#end of sib2, iclass 23, count 2 2006.285.09:31:59.20#ibcon#*mode == 0, iclass 23, count 2 2006.285.09:31:59.20#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.09:31:59.20#ibcon#[25=AT07-04\r\n] 2006.285.09:31:59.20#ibcon#*before write, iclass 23, count 2 2006.285.09:31:59.20#ibcon#enter sib2, iclass 23, count 2 2006.285.09:31:59.20#ibcon#flushed, iclass 23, count 2 2006.285.09:31:59.20#ibcon#about to write, iclass 23, count 2 2006.285.09:31:59.20#ibcon#wrote, iclass 23, count 2 2006.285.09:31:59.20#ibcon#about to read 3, iclass 23, count 2 2006.285.09:31:59.23#ibcon#read 3, iclass 23, count 2 2006.285.09:31:59.23#ibcon#about to read 4, iclass 23, count 2 2006.285.09:31:59.23#ibcon#read 4, iclass 23, count 2 2006.285.09:31:59.23#ibcon#about to read 5, iclass 23, count 2 2006.285.09:31:59.23#ibcon#read 5, iclass 23, count 2 2006.285.09:31:59.23#ibcon#about to read 6, iclass 23, count 2 2006.285.09:31:59.23#ibcon#read 6, iclass 23, count 2 2006.285.09:31:59.23#ibcon#end of sib2, iclass 23, count 2 2006.285.09:31:59.23#ibcon#*after write, iclass 23, count 2 2006.285.09:31:59.23#ibcon#*before return 0, iclass 23, count 2 2006.285.09:31:59.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:31:59.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:31:59.23#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.09:31:59.23#ibcon#ireg 7 cls_cnt 0 2006.285.09:31:59.23#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:31:59.35#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:31:59.35#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:31:59.35#ibcon#enter wrdev, iclass 23, count 0 2006.285.09:31:59.35#ibcon#first serial, iclass 23, count 0 2006.285.09:31:59.35#ibcon#enter sib2, iclass 23, count 0 2006.285.09:31:59.35#ibcon#flushed, iclass 23, count 0 2006.285.09:31:59.35#ibcon#about to write, iclass 23, count 0 2006.285.09:31:59.35#ibcon#wrote, iclass 23, count 0 2006.285.09:31:59.35#ibcon#about to read 3, iclass 23, count 0 2006.285.09:31:59.37#ibcon#read 3, iclass 23, count 0 2006.285.09:31:59.37#ibcon#about to read 4, iclass 23, count 0 2006.285.09:31:59.37#ibcon#read 4, iclass 23, count 0 2006.285.09:31:59.37#ibcon#about to read 5, iclass 23, count 0 2006.285.09:31:59.37#ibcon#read 5, iclass 23, count 0 2006.285.09:31:59.37#ibcon#about to read 6, iclass 23, count 0 2006.285.09:31:59.37#ibcon#read 6, iclass 23, count 0 2006.285.09:31:59.37#ibcon#end of sib2, iclass 23, count 0 2006.285.09:31:59.37#ibcon#*mode == 0, iclass 23, count 0 2006.285.09:31:59.37#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.09:31:59.37#ibcon#[25=USB\r\n] 2006.285.09:31:59.37#ibcon#*before write, iclass 23, count 0 2006.285.09:31:59.37#ibcon#enter sib2, iclass 23, count 0 2006.285.09:31:59.37#ibcon#flushed, iclass 23, count 0 2006.285.09:31:59.37#ibcon#about to write, iclass 23, count 0 2006.285.09:31:59.37#ibcon#wrote, iclass 23, count 0 2006.285.09:31:59.37#ibcon#about to read 3, iclass 23, count 0 2006.285.09:31:59.40#ibcon#read 3, iclass 23, count 0 2006.285.09:31:59.40#ibcon#about to read 4, iclass 23, count 0 2006.285.09:31:59.40#ibcon#read 4, iclass 23, count 0 2006.285.09:31:59.40#ibcon#about to read 5, iclass 23, count 0 2006.285.09:31:59.40#ibcon#read 5, iclass 23, count 0 2006.285.09:31:59.40#ibcon#about to read 6, iclass 23, count 0 2006.285.09:31:59.40#ibcon#read 6, iclass 23, count 0 2006.285.09:31:59.40#ibcon#end of sib2, iclass 23, count 0 2006.285.09:31:59.40#ibcon#*after write, iclass 23, count 0 2006.285.09:31:59.40#ibcon#*before return 0, iclass 23, count 0 2006.285.09:31:59.40#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:31:59.40#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:31:59.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.09:31:59.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.09:31:59.40$vck44/valo=8,884.99 2006.285.09:31:59.40#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.09:31:59.40#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.09:31:59.40#ibcon#ireg 17 cls_cnt 0 2006.285.09:31:59.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:31:59.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:31:59.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:31:59.40#ibcon#enter wrdev, iclass 25, count 0 2006.285.09:31:59.40#ibcon#first serial, iclass 25, count 0 2006.285.09:31:59.40#ibcon#enter sib2, iclass 25, count 0 2006.285.09:31:59.40#ibcon#flushed, iclass 25, count 0 2006.285.09:31:59.40#ibcon#about to write, iclass 25, count 0 2006.285.09:31:59.40#ibcon#wrote, iclass 25, count 0 2006.285.09:31:59.40#ibcon#about to read 3, iclass 25, count 0 2006.285.09:31:59.42#ibcon#read 3, iclass 25, count 0 2006.285.09:31:59.42#ibcon#about to read 4, iclass 25, count 0 2006.285.09:31:59.42#ibcon#read 4, iclass 25, count 0 2006.285.09:31:59.42#ibcon#about to read 5, iclass 25, count 0 2006.285.09:31:59.42#ibcon#read 5, iclass 25, count 0 2006.285.09:31:59.42#ibcon#about to read 6, iclass 25, count 0 2006.285.09:31:59.42#ibcon#read 6, iclass 25, count 0 2006.285.09:31:59.42#ibcon#end of sib2, iclass 25, count 0 2006.285.09:31:59.42#ibcon#*mode == 0, iclass 25, count 0 2006.285.09:31:59.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.09:31:59.42#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:31:59.42#ibcon#*before write, iclass 25, count 0 2006.285.09:31:59.42#ibcon#enter sib2, iclass 25, count 0 2006.285.09:31:59.42#ibcon#flushed, iclass 25, count 0 2006.285.09:31:59.42#ibcon#about to write, iclass 25, count 0 2006.285.09:31:59.42#ibcon#wrote, iclass 25, count 0 2006.285.09:31:59.42#ibcon#about to read 3, iclass 25, count 0 2006.285.09:31:59.46#ibcon#read 3, iclass 25, count 0 2006.285.09:31:59.46#ibcon#about to read 4, iclass 25, count 0 2006.285.09:31:59.46#ibcon#read 4, iclass 25, count 0 2006.285.09:31:59.46#ibcon#about to read 5, iclass 25, count 0 2006.285.09:31:59.46#ibcon#read 5, iclass 25, count 0 2006.285.09:31:59.46#ibcon#about to read 6, iclass 25, count 0 2006.285.09:31:59.46#ibcon#read 6, iclass 25, count 0 2006.285.09:31:59.46#ibcon#end of sib2, iclass 25, count 0 2006.285.09:31:59.46#ibcon#*after write, iclass 25, count 0 2006.285.09:31:59.46#ibcon#*before return 0, iclass 25, count 0 2006.285.09:31:59.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:31:59.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:31:59.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.09:31:59.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.09:31:59.46$vck44/va=8,3 2006.285.09:31:59.46#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.09:31:59.46#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.09:31:59.46#ibcon#ireg 11 cls_cnt 2 2006.285.09:31:59.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:31:59.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:31:59.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:31:59.52#ibcon#enter wrdev, iclass 27, count 2 2006.285.09:31:59.52#ibcon#first serial, iclass 27, count 2 2006.285.09:31:59.52#ibcon#enter sib2, iclass 27, count 2 2006.285.09:31:59.52#ibcon#flushed, iclass 27, count 2 2006.285.09:31:59.52#ibcon#about to write, iclass 27, count 2 2006.285.09:31:59.52#ibcon#wrote, iclass 27, count 2 2006.285.09:31:59.52#ibcon#about to read 3, iclass 27, count 2 2006.285.09:31:59.54#ibcon#read 3, iclass 27, count 2 2006.285.09:31:59.54#ibcon#about to read 4, iclass 27, count 2 2006.285.09:31:59.54#ibcon#read 4, iclass 27, count 2 2006.285.09:31:59.54#ibcon#about to read 5, iclass 27, count 2 2006.285.09:31:59.54#ibcon#read 5, iclass 27, count 2 2006.285.09:31:59.54#ibcon#about to read 6, iclass 27, count 2 2006.285.09:31:59.54#ibcon#read 6, iclass 27, count 2 2006.285.09:31:59.54#ibcon#end of sib2, iclass 27, count 2 2006.285.09:31:59.54#ibcon#*mode == 0, iclass 27, count 2 2006.285.09:31:59.54#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.09:31:59.54#ibcon#[25=AT08-03\r\n] 2006.285.09:31:59.54#ibcon#*before write, iclass 27, count 2 2006.285.09:31:59.54#ibcon#enter sib2, iclass 27, count 2 2006.285.09:31:59.54#ibcon#flushed, iclass 27, count 2 2006.285.09:31:59.54#ibcon#about to write, iclass 27, count 2 2006.285.09:31:59.54#ibcon#wrote, iclass 27, count 2 2006.285.09:31:59.54#ibcon#about to read 3, iclass 27, count 2 2006.285.09:31:59.57#ibcon#read 3, iclass 27, count 2 2006.285.09:31:59.57#ibcon#about to read 4, iclass 27, count 2 2006.285.09:31:59.57#ibcon#read 4, iclass 27, count 2 2006.285.09:31:59.57#ibcon#about to read 5, iclass 27, count 2 2006.285.09:31:59.57#ibcon#read 5, iclass 27, count 2 2006.285.09:31:59.57#ibcon#about to read 6, iclass 27, count 2 2006.285.09:31:59.57#ibcon#read 6, iclass 27, count 2 2006.285.09:31:59.57#ibcon#end of sib2, iclass 27, count 2 2006.285.09:31:59.57#ibcon#*after write, iclass 27, count 2 2006.285.09:31:59.57#ibcon#*before return 0, iclass 27, count 2 2006.285.09:31:59.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:31:59.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.09:31:59.57#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.09:31:59.57#ibcon#ireg 7 cls_cnt 0 2006.285.09:31:59.57#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:31:59.69#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:31:59.69#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:31:59.69#ibcon#enter wrdev, iclass 27, count 0 2006.285.09:31:59.69#ibcon#first serial, iclass 27, count 0 2006.285.09:31:59.69#ibcon#enter sib2, iclass 27, count 0 2006.285.09:31:59.69#ibcon#flushed, iclass 27, count 0 2006.285.09:31:59.69#ibcon#about to write, iclass 27, count 0 2006.285.09:31:59.69#ibcon#wrote, iclass 27, count 0 2006.285.09:31:59.69#ibcon#about to read 3, iclass 27, count 0 2006.285.09:31:59.71#ibcon#read 3, iclass 27, count 0 2006.285.09:31:59.71#ibcon#about to read 4, iclass 27, count 0 2006.285.09:31:59.71#ibcon#read 4, iclass 27, count 0 2006.285.09:31:59.71#ibcon#about to read 5, iclass 27, count 0 2006.285.09:31:59.71#ibcon#read 5, iclass 27, count 0 2006.285.09:31:59.71#ibcon#about to read 6, iclass 27, count 0 2006.285.09:31:59.71#ibcon#read 6, iclass 27, count 0 2006.285.09:31:59.71#ibcon#end of sib2, iclass 27, count 0 2006.285.09:31:59.71#ibcon#*mode == 0, iclass 27, count 0 2006.285.09:31:59.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.09:31:59.71#ibcon#[25=USB\r\n] 2006.285.09:31:59.71#ibcon#*before write, iclass 27, count 0 2006.285.09:31:59.71#ibcon#enter sib2, iclass 27, count 0 2006.285.09:31:59.71#ibcon#flushed, iclass 27, count 0 2006.285.09:31:59.71#ibcon#about to write, iclass 27, count 0 2006.285.09:31:59.71#ibcon#wrote, iclass 27, count 0 2006.285.09:31:59.71#ibcon#about to read 3, iclass 27, count 0 2006.285.09:31:59.74#ibcon#read 3, iclass 27, count 0 2006.285.09:31:59.74#ibcon#about to read 4, iclass 27, count 0 2006.285.09:31:59.74#ibcon#read 4, iclass 27, count 0 2006.285.09:31:59.74#ibcon#about to read 5, iclass 27, count 0 2006.285.09:31:59.74#ibcon#read 5, iclass 27, count 0 2006.285.09:31:59.74#ibcon#about to read 6, iclass 27, count 0 2006.285.09:31:59.74#ibcon#read 6, iclass 27, count 0 2006.285.09:31:59.74#ibcon#end of sib2, iclass 27, count 0 2006.285.09:31:59.74#ibcon#*after write, iclass 27, count 0 2006.285.09:31:59.74#ibcon#*before return 0, iclass 27, count 0 2006.285.09:31:59.74#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:31:59.74#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.09:31:59.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.09:31:59.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.09:31:59.74$vck44/vblo=1,629.99 2006.285.09:31:59.74#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.09:31:59.74#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.09:31:59.74#ibcon#ireg 17 cls_cnt 0 2006.285.09:31:59.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:31:59.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:31:59.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:31:59.74#ibcon#enter wrdev, iclass 29, count 0 2006.285.09:31:59.74#ibcon#first serial, iclass 29, count 0 2006.285.09:31:59.74#ibcon#enter sib2, iclass 29, count 0 2006.285.09:31:59.74#ibcon#flushed, iclass 29, count 0 2006.285.09:31:59.74#ibcon#about to write, iclass 29, count 0 2006.285.09:31:59.74#ibcon#wrote, iclass 29, count 0 2006.285.09:31:59.74#ibcon#about to read 3, iclass 29, count 0 2006.285.09:31:59.76#ibcon#read 3, iclass 29, count 0 2006.285.09:31:59.76#ibcon#about to read 4, iclass 29, count 0 2006.285.09:31:59.76#ibcon#read 4, iclass 29, count 0 2006.285.09:31:59.76#ibcon#about to read 5, iclass 29, count 0 2006.285.09:31:59.76#ibcon#read 5, iclass 29, count 0 2006.285.09:31:59.76#ibcon#about to read 6, iclass 29, count 0 2006.285.09:31:59.76#ibcon#read 6, iclass 29, count 0 2006.285.09:31:59.76#ibcon#end of sib2, iclass 29, count 0 2006.285.09:31:59.76#ibcon#*mode == 0, iclass 29, count 0 2006.285.09:31:59.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.09:31:59.76#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:31:59.76#ibcon#*before write, iclass 29, count 0 2006.285.09:31:59.76#ibcon#enter sib2, iclass 29, count 0 2006.285.09:31:59.76#ibcon#flushed, iclass 29, count 0 2006.285.09:31:59.76#ibcon#about to write, iclass 29, count 0 2006.285.09:31:59.76#ibcon#wrote, iclass 29, count 0 2006.285.09:31:59.76#ibcon#about to read 3, iclass 29, count 0 2006.285.09:31:59.80#ibcon#read 3, iclass 29, count 0 2006.285.09:31:59.80#ibcon#about to read 4, iclass 29, count 0 2006.285.09:31:59.80#ibcon#read 4, iclass 29, count 0 2006.285.09:31:59.80#ibcon#about to read 5, iclass 29, count 0 2006.285.09:31:59.80#ibcon#read 5, iclass 29, count 0 2006.285.09:31:59.80#ibcon#about to read 6, iclass 29, count 0 2006.285.09:31:59.80#ibcon#read 6, iclass 29, count 0 2006.285.09:31:59.80#ibcon#end of sib2, iclass 29, count 0 2006.285.09:31:59.80#ibcon#*after write, iclass 29, count 0 2006.285.09:31:59.80#ibcon#*before return 0, iclass 29, count 0 2006.285.09:31:59.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:31:59.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.09:31:59.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.09:31:59.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.09:31:59.80$vck44/vb=1,4 2006.285.09:31:59.80#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.09:31:59.80#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.09:31:59.80#ibcon#ireg 11 cls_cnt 2 2006.285.09:31:59.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:31:59.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:31:59.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:31:59.80#ibcon#enter wrdev, iclass 31, count 2 2006.285.09:31:59.80#ibcon#first serial, iclass 31, count 2 2006.285.09:31:59.80#ibcon#enter sib2, iclass 31, count 2 2006.285.09:31:59.80#ibcon#flushed, iclass 31, count 2 2006.285.09:31:59.80#ibcon#about to write, iclass 31, count 2 2006.285.09:31:59.80#ibcon#wrote, iclass 31, count 2 2006.285.09:31:59.80#ibcon#about to read 3, iclass 31, count 2 2006.285.09:31:59.82#ibcon#read 3, iclass 31, count 2 2006.285.09:31:59.82#ibcon#about to read 4, iclass 31, count 2 2006.285.09:31:59.82#ibcon#read 4, iclass 31, count 2 2006.285.09:31:59.82#ibcon#about to read 5, iclass 31, count 2 2006.285.09:31:59.82#ibcon#read 5, iclass 31, count 2 2006.285.09:31:59.82#ibcon#about to read 6, iclass 31, count 2 2006.285.09:31:59.82#ibcon#read 6, iclass 31, count 2 2006.285.09:31:59.82#ibcon#end of sib2, iclass 31, count 2 2006.285.09:31:59.82#ibcon#*mode == 0, iclass 31, count 2 2006.285.09:31:59.82#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.09:31:59.82#ibcon#[27=AT01-04\r\n] 2006.285.09:31:59.82#ibcon#*before write, iclass 31, count 2 2006.285.09:31:59.82#ibcon#enter sib2, iclass 31, count 2 2006.285.09:31:59.82#ibcon#flushed, iclass 31, count 2 2006.285.09:31:59.82#ibcon#about to write, iclass 31, count 2 2006.285.09:31:59.82#ibcon#wrote, iclass 31, count 2 2006.285.09:31:59.82#ibcon#about to read 3, iclass 31, count 2 2006.285.09:31:59.85#ibcon#read 3, iclass 31, count 2 2006.285.09:31:59.85#ibcon#about to read 4, iclass 31, count 2 2006.285.09:31:59.85#ibcon#read 4, iclass 31, count 2 2006.285.09:31:59.85#ibcon#about to read 5, iclass 31, count 2 2006.285.09:31:59.85#ibcon#read 5, iclass 31, count 2 2006.285.09:31:59.85#ibcon#about to read 6, iclass 31, count 2 2006.285.09:31:59.85#ibcon#read 6, iclass 31, count 2 2006.285.09:31:59.85#ibcon#end of sib2, iclass 31, count 2 2006.285.09:31:59.85#ibcon#*after write, iclass 31, count 2 2006.285.09:31:59.85#ibcon#*before return 0, iclass 31, count 2 2006.285.09:31:59.85#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:31:59.85#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.09:31:59.85#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.09:31:59.85#ibcon#ireg 7 cls_cnt 0 2006.285.09:31:59.85#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:31:59.97#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:31:59.97#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:31:59.97#ibcon#enter wrdev, iclass 31, count 0 2006.285.09:31:59.97#ibcon#first serial, iclass 31, count 0 2006.285.09:31:59.97#ibcon#enter sib2, iclass 31, count 0 2006.285.09:31:59.97#ibcon#flushed, iclass 31, count 0 2006.285.09:31:59.97#ibcon#about to write, iclass 31, count 0 2006.285.09:31:59.97#ibcon#wrote, iclass 31, count 0 2006.285.09:31:59.97#ibcon#about to read 3, iclass 31, count 0 2006.285.09:31:59.99#ibcon#read 3, iclass 31, count 0 2006.285.09:31:59.99#ibcon#about to read 4, iclass 31, count 0 2006.285.09:31:59.99#ibcon#read 4, iclass 31, count 0 2006.285.09:31:59.99#ibcon#about to read 5, iclass 31, count 0 2006.285.09:31:59.99#ibcon#read 5, iclass 31, count 0 2006.285.09:31:59.99#ibcon#about to read 6, iclass 31, count 0 2006.285.09:31:59.99#ibcon#read 6, iclass 31, count 0 2006.285.09:31:59.99#ibcon#end of sib2, iclass 31, count 0 2006.285.09:31:59.99#ibcon#*mode == 0, iclass 31, count 0 2006.285.09:31:59.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.09:31:59.99#ibcon#[27=USB\r\n] 2006.285.09:31:59.99#ibcon#*before write, iclass 31, count 0 2006.285.09:31:59.99#ibcon#enter sib2, iclass 31, count 0 2006.285.09:31:59.99#ibcon#flushed, iclass 31, count 0 2006.285.09:31:59.99#ibcon#about to write, iclass 31, count 0 2006.285.09:31:59.99#ibcon#wrote, iclass 31, count 0 2006.285.09:31:59.99#ibcon#about to read 3, iclass 31, count 0 2006.285.09:32:00.02#ibcon#read 3, iclass 31, count 0 2006.285.09:32:00.02#ibcon#about to read 4, iclass 31, count 0 2006.285.09:32:00.02#ibcon#read 4, iclass 31, count 0 2006.285.09:32:00.02#ibcon#about to read 5, iclass 31, count 0 2006.285.09:32:00.02#ibcon#read 5, iclass 31, count 0 2006.285.09:32:00.02#ibcon#about to read 6, iclass 31, count 0 2006.285.09:32:00.02#ibcon#read 6, iclass 31, count 0 2006.285.09:32:00.02#ibcon#end of sib2, iclass 31, count 0 2006.285.09:32:00.02#ibcon#*after write, iclass 31, count 0 2006.285.09:32:00.02#ibcon#*before return 0, iclass 31, count 0 2006.285.09:32:00.02#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:32:00.02#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.09:32:00.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.09:32:00.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.09:32:00.02$vck44/vblo=2,634.99 2006.285.09:32:00.02#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.09:32:00.02#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.09:32:00.02#ibcon#ireg 17 cls_cnt 0 2006.285.09:32:00.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:32:00.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:32:00.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:32:00.02#ibcon#enter wrdev, iclass 33, count 0 2006.285.09:32:00.02#ibcon#first serial, iclass 33, count 0 2006.285.09:32:00.02#ibcon#enter sib2, iclass 33, count 0 2006.285.09:32:00.02#ibcon#flushed, iclass 33, count 0 2006.285.09:32:00.02#ibcon#about to write, iclass 33, count 0 2006.285.09:32:00.02#ibcon#wrote, iclass 33, count 0 2006.285.09:32:00.02#ibcon#about to read 3, iclass 33, count 0 2006.285.09:32:00.04#ibcon#read 3, iclass 33, count 0 2006.285.09:32:00.04#ibcon#about to read 4, iclass 33, count 0 2006.285.09:32:00.04#ibcon#read 4, iclass 33, count 0 2006.285.09:32:00.04#ibcon#about to read 5, iclass 33, count 0 2006.285.09:32:00.04#ibcon#read 5, iclass 33, count 0 2006.285.09:32:00.04#ibcon#about to read 6, iclass 33, count 0 2006.285.09:32:00.04#ibcon#read 6, iclass 33, count 0 2006.285.09:32:00.04#ibcon#end of sib2, iclass 33, count 0 2006.285.09:32:00.04#ibcon#*mode == 0, iclass 33, count 0 2006.285.09:32:00.04#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.09:32:00.04#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:32:00.04#ibcon#*before write, iclass 33, count 0 2006.285.09:32:00.04#ibcon#enter sib2, iclass 33, count 0 2006.285.09:32:00.04#ibcon#flushed, iclass 33, count 0 2006.285.09:32:00.04#ibcon#about to write, iclass 33, count 0 2006.285.09:32:00.04#ibcon#wrote, iclass 33, count 0 2006.285.09:32:00.04#ibcon#about to read 3, iclass 33, count 0 2006.285.09:32:00.08#ibcon#read 3, iclass 33, count 0 2006.285.09:32:00.08#ibcon#about to read 4, iclass 33, count 0 2006.285.09:32:00.08#ibcon#read 4, iclass 33, count 0 2006.285.09:32:00.08#ibcon#about to read 5, iclass 33, count 0 2006.285.09:32:00.08#ibcon#read 5, iclass 33, count 0 2006.285.09:32:00.08#ibcon#about to read 6, iclass 33, count 0 2006.285.09:32:00.08#ibcon#read 6, iclass 33, count 0 2006.285.09:32:00.08#ibcon#end of sib2, iclass 33, count 0 2006.285.09:32:00.08#ibcon#*after write, iclass 33, count 0 2006.285.09:32:00.08#ibcon#*before return 0, iclass 33, count 0 2006.285.09:32:00.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:32:00.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.09:32:00.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.09:32:00.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.09:32:00.08$vck44/vb=2,5 2006.285.09:32:00.08#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.09:32:00.08#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.09:32:00.08#ibcon#ireg 11 cls_cnt 2 2006.285.09:32:00.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:32:00.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:32:00.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:32:00.14#ibcon#enter wrdev, iclass 35, count 2 2006.285.09:32:00.14#ibcon#first serial, iclass 35, count 2 2006.285.09:32:00.14#ibcon#enter sib2, iclass 35, count 2 2006.285.09:32:00.14#ibcon#flushed, iclass 35, count 2 2006.285.09:32:00.14#ibcon#about to write, iclass 35, count 2 2006.285.09:32:00.14#ibcon#wrote, iclass 35, count 2 2006.285.09:32:00.14#ibcon#about to read 3, iclass 35, count 2 2006.285.09:32:00.16#ibcon#read 3, iclass 35, count 2 2006.285.09:32:00.16#ibcon#about to read 4, iclass 35, count 2 2006.285.09:32:00.16#ibcon#read 4, iclass 35, count 2 2006.285.09:32:00.16#ibcon#about to read 5, iclass 35, count 2 2006.285.09:32:00.16#ibcon#read 5, iclass 35, count 2 2006.285.09:32:00.16#ibcon#about to read 6, iclass 35, count 2 2006.285.09:32:00.16#ibcon#read 6, iclass 35, count 2 2006.285.09:32:00.16#ibcon#end of sib2, iclass 35, count 2 2006.285.09:32:00.16#ibcon#*mode == 0, iclass 35, count 2 2006.285.09:32:00.16#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.09:32:00.16#ibcon#[27=AT02-05\r\n] 2006.285.09:32:00.16#ibcon#*before write, iclass 35, count 2 2006.285.09:32:00.16#ibcon#enter sib2, iclass 35, count 2 2006.285.09:32:00.16#ibcon#flushed, iclass 35, count 2 2006.285.09:32:00.16#ibcon#about to write, iclass 35, count 2 2006.285.09:32:00.16#ibcon#wrote, iclass 35, count 2 2006.285.09:32:00.16#ibcon#about to read 3, iclass 35, count 2 2006.285.09:32:00.19#ibcon#read 3, iclass 35, count 2 2006.285.09:32:00.19#ibcon#about to read 4, iclass 35, count 2 2006.285.09:32:00.19#ibcon#read 4, iclass 35, count 2 2006.285.09:32:00.19#ibcon#about to read 5, iclass 35, count 2 2006.285.09:32:00.19#ibcon#read 5, iclass 35, count 2 2006.285.09:32:00.19#ibcon#about to read 6, iclass 35, count 2 2006.285.09:32:00.19#ibcon#read 6, iclass 35, count 2 2006.285.09:32:00.19#ibcon#end of sib2, iclass 35, count 2 2006.285.09:32:00.19#ibcon#*after write, iclass 35, count 2 2006.285.09:32:00.19#ibcon#*before return 0, iclass 35, count 2 2006.285.09:32:00.19#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:32:00.19#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:32:00.19#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.09:32:00.19#ibcon#ireg 7 cls_cnt 0 2006.285.09:32:00.19#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:32:00.31#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:32:00.31#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:32:00.31#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:32:00.31#ibcon#first serial, iclass 35, count 0 2006.285.09:32:00.31#ibcon#enter sib2, iclass 35, count 0 2006.285.09:32:00.31#ibcon#flushed, iclass 35, count 0 2006.285.09:32:00.31#ibcon#about to write, iclass 35, count 0 2006.285.09:32:00.31#ibcon#wrote, iclass 35, count 0 2006.285.09:32:00.31#ibcon#about to read 3, iclass 35, count 0 2006.285.09:32:00.33#ibcon#read 3, iclass 35, count 0 2006.285.09:32:00.33#ibcon#about to read 4, iclass 35, count 0 2006.285.09:32:00.33#ibcon#read 4, iclass 35, count 0 2006.285.09:32:00.33#ibcon#about to read 5, iclass 35, count 0 2006.285.09:32:00.33#ibcon#read 5, iclass 35, count 0 2006.285.09:32:00.33#ibcon#about to read 6, iclass 35, count 0 2006.285.09:32:00.33#ibcon#read 6, iclass 35, count 0 2006.285.09:32:00.33#ibcon#end of sib2, iclass 35, count 0 2006.285.09:32:00.33#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:32:00.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:32:00.33#ibcon#[27=USB\r\n] 2006.285.09:32:00.33#ibcon#*before write, iclass 35, count 0 2006.285.09:32:00.33#ibcon#enter sib2, iclass 35, count 0 2006.285.09:32:00.33#ibcon#flushed, iclass 35, count 0 2006.285.09:32:00.33#ibcon#about to write, iclass 35, count 0 2006.285.09:32:00.33#ibcon#wrote, iclass 35, count 0 2006.285.09:32:00.33#ibcon#about to read 3, iclass 35, count 0 2006.285.09:32:00.36#ibcon#read 3, iclass 35, count 0 2006.285.09:32:00.36#ibcon#about to read 4, iclass 35, count 0 2006.285.09:32:00.36#ibcon#read 4, iclass 35, count 0 2006.285.09:32:00.36#ibcon#about to read 5, iclass 35, count 0 2006.285.09:32:00.36#ibcon#read 5, iclass 35, count 0 2006.285.09:32:00.36#ibcon#about to read 6, iclass 35, count 0 2006.285.09:32:00.36#ibcon#read 6, iclass 35, count 0 2006.285.09:32:00.36#ibcon#end of sib2, iclass 35, count 0 2006.285.09:32:00.36#ibcon#*after write, iclass 35, count 0 2006.285.09:32:00.36#ibcon#*before return 0, iclass 35, count 0 2006.285.09:32:00.36#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:32:00.36#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:32:00.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:32:00.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:32:00.36$vck44/vblo=3,649.99 2006.285.09:32:00.36#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.09:32:00.36#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.09:32:00.36#ibcon#ireg 17 cls_cnt 0 2006.285.09:32:00.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:32:00.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:32:00.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:32:00.36#ibcon#enter wrdev, iclass 37, count 0 2006.285.09:32:00.36#ibcon#first serial, iclass 37, count 0 2006.285.09:32:00.36#ibcon#enter sib2, iclass 37, count 0 2006.285.09:32:00.36#ibcon#flushed, iclass 37, count 0 2006.285.09:32:00.36#ibcon#about to write, iclass 37, count 0 2006.285.09:32:00.36#ibcon#wrote, iclass 37, count 0 2006.285.09:32:00.36#ibcon#about to read 3, iclass 37, count 0 2006.285.09:32:00.38#ibcon#read 3, iclass 37, count 0 2006.285.09:32:00.38#ibcon#about to read 4, iclass 37, count 0 2006.285.09:32:00.38#ibcon#read 4, iclass 37, count 0 2006.285.09:32:00.38#ibcon#about to read 5, iclass 37, count 0 2006.285.09:32:00.38#ibcon#read 5, iclass 37, count 0 2006.285.09:32:00.38#ibcon#about to read 6, iclass 37, count 0 2006.285.09:32:00.38#ibcon#read 6, iclass 37, count 0 2006.285.09:32:00.38#ibcon#end of sib2, iclass 37, count 0 2006.285.09:32:00.38#ibcon#*mode == 0, iclass 37, count 0 2006.285.09:32:00.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.09:32:00.38#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:32:00.38#ibcon#*before write, iclass 37, count 0 2006.285.09:32:00.38#ibcon#enter sib2, iclass 37, count 0 2006.285.09:32:00.38#ibcon#flushed, iclass 37, count 0 2006.285.09:32:00.38#ibcon#about to write, iclass 37, count 0 2006.285.09:32:00.38#ibcon#wrote, iclass 37, count 0 2006.285.09:32:00.38#ibcon#about to read 3, iclass 37, count 0 2006.285.09:32:00.42#ibcon#read 3, iclass 37, count 0 2006.285.09:32:00.42#ibcon#about to read 4, iclass 37, count 0 2006.285.09:32:00.42#ibcon#read 4, iclass 37, count 0 2006.285.09:32:00.42#ibcon#about to read 5, iclass 37, count 0 2006.285.09:32:00.42#ibcon#read 5, iclass 37, count 0 2006.285.09:32:00.42#ibcon#about to read 6, iclass 37, count 0 2006.285.09:32:00.42#ibcon#read 6, iclass 37, count 0 2006.285.09:32:00.42#ibcon#end of sib2, iclass 37, count 0 2006.285.09:32:00.42#ibcon#*after write, iclass 37, count 0 2006.285.09:32:00.42#ibcon#*before return 0, iclass 37, count 0 2006.285.09:32:00.42#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:32:00.42#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.09:32:00.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.09:32:00.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.09:32:00.42$vck44/vb=3,4 2006.285.09:32:00.42#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.09:32:00.42#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.09:32:00.42#ibcon#ireg 11 cls_cnt 2 2006.285.09:32:00.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:32:00.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:32:00.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:32:00.48#ibcon#enter wrdev, iclass 39, count 2 2006.285.09:32:00.48#ibcon#first serial, iclass 39, count 2 2006.285.09:32:00.48#ibcon#enter sib2, iclass 39, count 2 2006.285.09:32:00.48#ibcon#flushed, iclass 39, count 2 2006.285.09:32:00.48#ibcon#about to write, iclass 39, count 2 2006.285.09:32:00.48#ibcon#wrote, iclass 39, count 2 2006.285.09:32:00.48#ibcon#about to read 3, iclass 39, count 2 2006.285.09:32:00.50#ibcon#read 3, iclass 39, count 2 2006.285.09:32:00.50#ibcon#about to read 4, iclass 39, count 2 2006.285.09:32:00.50#ibcon#read 4, iclass 39, count 2 2006.285.09:32:00.50#ibcon#about to read 5, iclass 39, count 2 2006.285.09:32:00.50#ibcon#read 5, iclass 39, count 2 2006.285.09:32:00.50#ibcon#about to read 6, iclass 39, count 2 2006.285.09:32:00.50#ibcon#read 6, iclass 39, count 2 2006.285.09:32:00.50#ibcon#end of sib2, iclass 39, count 2 2006.285.09:32:00.50#ibcon#*mode == 0, iclass 39, count 2 2006.285.09:32:00.50#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.09:32:00.50#ibcon#[27=AT03-04\r\n] 2006.285.09:32:00.50#ibcon#*before write, iclass 39, count 2 2006.285.09:32:00.50#ibcon#enter sib2, iclass 39, count 2 2006.285.09:32:00.50#ibcon#flushed, iclass 39, count 2 2006.285.09:32:00.50#ibcon#about to write, iclass 39, count 2 2006.285.09:32:00.50#ibcon#wrote, iclass 39, count 2 2006.285.09:32:00.50#ibcon#about to read 3, iclass 39, count 2 2006.285.09:32:00.53#ibcon#read 3, iclass 39, count 2 2006.285.09:32:00.53#ibcon#about to read 4, iclass 39, count 2 2006.285.09:32:00.53#ibcon#read 4, iclass 39, count 2 2006.285.09:32:00.53#ibcon#about to read 5, iclass 39, count 2 2006.285.09:32:00.53#ibcon#read 5, iclass 39, count 2 2006.285.09:32:00.53#ibcon#about to read 6, iclass 39, count 2 2006.285.09:32:00.53#ibcon#read 6, iclass 39, count 2 2006.285.09:32:00.53#ibcon#end of sib2, iclass 39, count 2 2006.285.09:32:00.53#ibcon#*after write, iclass 39, count 2 2006.285.09:32:00.53#ibcon#*before return 0, iclass 39, count 2 2006.285.09:32:00.53#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:32:00.53#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.09:32:00.53#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.09:32:00.53#ibcon#ireg 7 cls_cnt 0 2006.285.09:32:00.53#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:32:00.65#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:32:00.65#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:32:00.65#ibcon#enter wrdev, iclass 39, count 0 2006.285.09:32:00.65#ibcon#first serial, iclass 39, count 0 2006.285.09:32:00.65#ibcon#enter sib2, iclass 39, count 0 2006.285.09:32:00.65#ibcon#flushed, iclass 39, count 0 2006.285.09:32:00.65#ibcon#about to write, iclass 39, count 0 2006.285.09:32:00.65#ibcon#wrote, iclass 39, count 0 2006.285.09:32:00.65#ibcon#about to read 3, iclass 39, count 0 2006.285.09:32:00.67#ibcon#read 3, iclass 39, count 0 2006.285.09:32:00.67#ibcon#about to read 4, iclass 39, count 0 2006.285.09:32:00.67#ibcon#read 4, iclass 39, count 0 2006.285.09:32:00.67#ibcon#about to read 5, iclass 39, count 0 2006.285.09:32:00.67#ibcon#read 5, iclass 39, count 0 2006.285.09:32:00.67#ibcon#about to read 6, iclass 39, count 0 2006.285.09:32:00.67#ibcon#read 6, iclass 39, count 0 2006.285.09:32:00.67#ibcon#end of sib2, iclass 39, count 0 2006.285.09:32:00.67#ibcon#*mode == 0, iclass 39, count 0 2006.285.09:32:00.67#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.09:32:00.67#ibcon#[27=USB\r\n] 2006.285.09:32:00.67#ibcon#*before write, iclass 39, count 0 2006.285.09:32:00.67#ibcon#enter sib2, iclass 39, count 0 2006.285.09:32:00.67#ibcon#flushed, iclass 39, count 0 2006.285.09:32:00.67#ibcon#about to write, iclass 39, count 0 2006.285.09:32:00.67#ibcon#wrote, iclass 39, count 0 2006.285.09:32:00.67#ibcon#about to read 3, iclass 39, count 0 2006.285.09:32:00.70#ibcon#read 3, iclass 39, count 0 2006.285.09:32:00.70#ibcon#about to read 4, iclass 39, count 0 2006.285.09:32:00.70#ibcon#read 4, iclass 39, count 0 2006.285.09:32:00.70#ibcon#about to read 5, iclass 39, count 0 2006.285.09:32:00.70#ibcon#read 5, iclass 39, count 0 2006.285.09:32:00.70#ibcon#about to read 6, iclass 39, count 0 2006.285.09:32:00.70#ibcon#read 6, iclass 39, count 0 2006.285.09:32:00.70#ibcon#end of sib2, iclass 39, count 0 2006.285.09:32:00.70#ibcon#*after write, iclass 39, count 0 2006.285.09:32:00.70#ibcon#*before return 0, iclass 39, count 0 2006.285.09:32:00.70#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:32:00.70#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.09:32:00.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.09:32:00.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.09:32:00.70$vck44/vblo=4,679.99 2006.285.09:32:00.70#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.09:32:00.70#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.09:32:00.70#ibcon#ireg 17 cls_cnt 0 2006.285.09:32:00.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:32:00.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:32:00.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:32:00.70#ibcon#enter wrdev, iclass 3, count 0 2006.285.09:32:00.70#ibcon#first serial, iclass 3, count 0 2006.285.09:32:00.70#ibcon#enter sib2, iclass 3, count 0 2006.285.09:32:00.70#ibcon#flushed, iclass 3, count 0 2006.285.09:32:00.70#ibcon#about to write, iclass 3, count 0 2006.285.09:32:00.70#ibcon#wrote, iclass 3, count 0 2006.285.09:32:00.70#ibcon#about to read 3, iclass 3, count 0 2006.285.09:32:00.72#ibcon#read 3, iclass 3, count 0 2006.285.09:32:00.72#ibcon#about to read 4, iclass 3, count 0 2006.285.09:32:00.72#ibcon#read 4, iclass 3, count 0 2006.285.09:32:00.72#ibcon#about to read 5, iclass 3, count 0 2006.285.09:32:00.72#ibcon#read 5, iclass 3, count 0 2006.285.09:32:00.72#ibcon#about to read 6, iclass 3, count 0 2006.285.09:32:00.72#ibcon#read 6, iclass 3, count 0 2006.285.09:32:00.72#ibcon#end of sib2, iclass 3, count 0 2006.285.09:32:00.72#ibcon#*mode == 0, iclass 3, count 0 2006.285.09:32:00.72#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.09:32:00.72#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:32:00.72#ibcon#*before write, iclass 3, count 0 2006.285.09:32:00.72#ibcon#enter sib2, iclass 3, count 0 2006.285.09:32:00.72#ibcon#flushed, iclass 3, count 0 2006.285.09:32:00.72#ibcon#about to write, iclass 3, count 0 2006.285.09:32:00.72#ibcon#wrote, iclass 3, count 0 2006.285.09:32:00.72#ibcon#about to read 3, iclass 3, count 0 2006.285.09:32:00.76#ibcon#read 3, iclass 3, count 0 2006.285.09:32:00.76#ibcon#about to read 4, iclass 3, count 0 2006.285.09:32:00.76#ibcon#read 4, iclass 3, count 0 2006.285.09:32:00.76#ibcon#about to read 5, iclass 3, count 0 2006.285.09:32:00.76#ibcon#read 5, iclass 3, count 0 2006.285.09:32:00.76#ibcon#about to read 6, iclass 3, count 0 2006.285.09:32:00.76#ibcon#read 6, iclass 3, count 0 2006.285.09:32:00.76#ibcon#end of sib2, iclass 3, count 0 2006.285.09:32:00.76#ibcon#*after write, iclass 3, count 0 2006.285.09:32:00.76#ibcon#*before return 0, iclass 3, count 0 2006.285.09:32:00.76#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:32:00.76#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.09:32:00.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.09:32:00.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.09:32:00.76$vck44/vb=4,5 2006.285.09:32:00.76#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.09:32:00.76#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.09:32:00.76#ibcon#ireg 11 cls_cnt 2 2006.285.09:32:00.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:32:00.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:32:00.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:32:00.82#ibcon#enter wrdev, iclass 5, count 2 2006.285.09:32:00.82#ibcon#first serial, iclass 5, count 2 2006.285.09:32:00.82#ibcon#enter sib2, iclass 5, count 2 2006.285.09:32:00.82#ibcon#flushed, iclass 5, count 2 2006.285.09:32:00.82#ibcon#about to write, iclass 5, count 2 2006.285.09:32:00.82#ibcon#wrote, iclass 5, count 2 2006.285.09:32:00.82#ibcon#about to read 3, iclass 5, count 2 2006.285.09:32:00.84#ibcon#read 3, iclass 5, count 2 2006.285.09:32:00.84#ibcon#about to read 4, iclass 5, count 2 2006.285.09:32:00.84#ibcon#read 4, iclass 5, count 2 2006.285.09:32:00.84#ibcon#about to read 5, iclass 5, count 2 2006.285.09:32:00.84#ibcon#read 5, iclass 5, count 2 2006.285.09:32:00.84#ibcon#about to read 6, iclass 5, count 2 2006.285.09:32:00.84#ibcon#read 6, iclass 5, count 2 2006.285.09:32:00.84#ibcon#end of sib2, iclass 5, count 2 2006.285.09:32:00.84#ibcon#*mode == 0, iclass 5, count 2 2006.285.09:32:00.84#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.09:32:00.84#ibcon#[27=AT04-05\r\n] 2006.285.09:32:00.84#ibcon#*before write, iclass 5, count 2 2006.285.09:32:00.84#ibcon#enter sib2, iclass 5, count 2 2006.285.09:32:00.84#ibcon#flushed, iclass 5, count 2 2006.285.09:32:00.84#ibcon#about to write, iclass 5, count 2 2006.285.09:32:00.84#ibcon#wrote, iclass 5, count 2 2006.285.09:32:00.84#ibcon#about to read 3, iclass 5, count 2 2006.285.09:32:00.87#ibcon#read 3, iclass 5, count 2 2006.285.09:32:00.87#ibcon#about to read 4, iclass 5, count 2 2006.285.09:32:00.87#ibcon#read 4, iclass 5, count 2 2006.285.09:32:00.87#ibcon#about to read 5, iclass 5, count 2 2006.285.09:32:00.87#ibcon#read 5, iclass 5, count 2 2006.285.09:32:00.87#ibcon#about to read 6, iclass 5, count 2 2006.285.09:32:00.87#ibcon#read 6, iclass 5, count 2 2006.285.09:32:00.87#ibcon#end of sib2, iclass 5, count 2 2006.285.09:32:00.87#ibcon#*after write, iclass 5, count 2 2006.285.09:32:00.87#ibcon#*before return 0, iclass 5, count 2 2006.285.09:32:00.87#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:32:00.87#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.09:32:00.87#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.09:32:00.87#ibcon#ireg 7 cls_cnt 0 2006.285.09:32:00.87#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:32:00.99#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:32:00.99#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:32:00.99#ibcon#enter wrdev, iclass 5, count 0 2006.285.09:32:00.99#ibcon#first serial, iclass 5, count 0 2006.285.09:32:00.99#ibcon#enter sib2, iclass 5, count 0 2006.285.09:32:00.99#ibcon#flushed, iclass 5, count 0 2006.285.09:32:00.99#ibcon#about to write, iclass 5, count 0 2006.285.09:32:00.99#ibcon#wrote, iclass 5, count 0 2006.285.09:32:00.99#ibcon#about to read 3, iclass 5, count 0 2006.285.09:32:01.01#ibcon#read 3, iclass 5, count 0 2006.285.09:32:01.01#ibcon#about to read 4, iclass 5, count 0 2006.285.09:32:01.01#ibcon#read 4, iclass 5, count 0 2006.285.09:32:01.01#ibcon#about to read 5, iclass 5, count 0 2006.285.09:32:01.01#ibcon#read 5, iclass 5, count 0 2006.285.09:32:01.01#ibcon#about to read 6, iclass 5, count 0 2006.285.09:32:01.01#ibcon#read 6, iclass 5, count 0 2006.285.09:32:01.01#ibcon#end of sib2, iclass 5, count 0 2006.285.09:32:01.01#ibcon#*mode == 0, iclass 5, count 0 2006.285.09:32:01.01#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.09:32:01.01#ibcon#[27=USB\r\n] 2006.285.09:32:01.01#ibcon#*before write, iclass 5, count 0 2006.285.09:32:01.01#ibcon#enter sib2, iclass 5, count 0 2006.285.09:32:01.01#ibcon#flushed, iclass 5, count 0 2006.285.09:32:01.01#ibcon#about to write, iclass 5, count 0 2006.285.09:32:01.01#ibcon#wrote, iclass 5, count 0 2006.285.09:32:01.01#ibcon#about to read 3, iclass 5, count 0 2006.285.09:32:01.04#ibcon#read 3, iclass 5, count 0 2006.285.09:32:01.04#ibcon#about to read 4, iclass 5, count 0 2006.285.09:32:01.04#ibcon#read 4, iclass 5, count 0 2006.285.09:32:01.04#ibcon#about to read 5, iclass 5, count 0 2006.285.09:32:01.04#ibcon#read 5, iclass 5, count 0 2006.285.09:32:01.04#ibcon#about to read 6, iclass 5, count 0 2006.285.09:32:01.04#ibcon#read 6, iclass 5, count 0 2006.285.09:32:01.04#ibcon#end of sib2, iclass 5, count 0 2006.285.09:32:01.04#ibcon#*after write, iclass 5, count 0 2006.285.09:32:01.04#ibcon#*before return 0, iclass 5, count 0 2006.285.09:32:01.04#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:32:01.04#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.09:32:01.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.09:32:01.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.09:32:01.04$vck44/vblo=5,709.99 2006.285.09:32:01.04#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.09:32:01.04#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.09:32:01.04#ibcon#ireg 17 cls_cnt 0 2006.285.09:32:01.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:32:01.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:32:01.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:32:01.04#ibcon#enter wrdev, iclass 7, count 0 2006.285.09:32:01.04#ibcon#first serial, iclass 7, count 0 2006.285.09:32:01.04#ibcon#enter sib2, iclass 7, count 0 2006.285.09:32:01.04#ibcon#flushed, iclass 7, count 0 2006.285.09:32:01.04#ibcon#about to write, iclass 7, count 0 2006.285.09:32:01.04#ibcon#wrote, iclass 7, count 0 2006.285.09:32:01.04#ibcon#about to read 3, iclass 7, count 0 2006.285.09:32:01.06#ibcon#read 3, iclass 7, count 0 2006.285.09:32:01.06#ibcon#about to read 4, iclass 7, count 0 2006.285.09:32:01.06#ibcon#read 4, iclass 7, count 0 2006.285.09:32:01.06#ibcon#about to read 5, iclass 7, count 0 2006.285.09:32:01.06#ibcon#read 5, iclass 7, count 0 2006.285.09:32:01.06#ibcon#about to read 6, iclass 7, count 0 2006.285.09:32:01.06#ibcon#read 6, iclass 7, count 0 2006.285.09:32:01.06#ibcon#end of sib2, iclass 7, count 0 2006.285.09:32:01.06#ibcon#*mode == 0, iclass 7, count 0 2006.285.09:32:01.06#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.09:32:01.06#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:32:01.06#ibcon#*before write, iclass 7, count 0 2006.285.09:32:01.06#ibcon#enter sib2, iclass 7, count 0 2006.285.09:32:01.06#ibcon#flushed, iclass 7, count 0 2006.285.09:32:01.06#ibcon#about to write, iclass 7, count 0 2006.285.09:32:01.06#ibcon#wrote, iclass 7, count 0 2006.285.09:32:01.06#ibcon#about to read 3, iclass 7, count 0 2006.285.09:32:01.10#ibcon#read 3, iclass 7, count 0 2006.285.09:32:01.10#ibcon#about to read 4, iclass 7, count 0 2006.285.09:32:01.10#ibcon#read 4, iclass 7, count 0 2006.285.09:32:01.10#ibcon#about to read 5, iclass 7, count 0 2006.285.09:32:01.10#ibcon#read 5, iclass 7, count 0 2006.285.09:32:01.10#ibcon#about to read 6, iclass 7, count 0 2006.285.09:32:01.10#ibcon#read 6, iclass 7, count 0 2006.285.09:32:01.10#ibcon#end of sib2, iclass 7, count 0 2006.285.09:32:01.10#ibcon#*after write, iclass 7, count 0 2006.285.09:32:01.10#ibcon#*before return 0, iclass 7, count 0 2006.285.09:32:01.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:32:01.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.09:32:01.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.09:32:01.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.09:32:01.10$vck44/vb=5,4 2006.285.09:32:01.10#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.09:32:01.10#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.09:32:01.10#ibcon#ireg 11 cls_cnt 2 2006.285.09:32:01.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:32:01.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:32:01.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:32:01.16#ibcon#enter wrdev, iclass 11, count 2 2006.285.09:32:01.16#ibcon#first serial, iclass 11, count 2 2006.285.09:32:01.16#ibcon#enter sib2, iclass 11, count 2 2006.285.09:32:01.16#ibcon#flushed, iclass 11, count 2 2006.285.09:32:01.16#ibcon#about to write, iclass 11, count 2 2006.285.09:32:01.16#ibcon#wrote, iclass 11, count 2 2006.285.09:32:01.16#ibcon#about to read 3, iclass 11, count 2 2006.285.09:32:01.18#ibcon#read 3, iclass 11, count 2 2006.285.09:32:01.18#ibcon#about to read 4, iclass 11, count 2 2006.285.09:32:01.18#ibcon#read 4, iclass 11, count 2 2006.285.09:32:01.18#ibcon#about to read 5, iclass 11, count 2 2006.285.09:32:01.18#ibcon#read 5, iclass 11, count 2 2006.285.09:32:01.18#ibcon#about to read 6, iclass 11, count 2 2006.285.09:32:01.18#ibcon#read 6, iclass 11, count 2 2006.285.09:32:01.18#ibcon#end of sib2, iclass 11, count 2 2006.285.09:32:01.18#ibcon#*mode == 0, iclass 11, count 2 2006.285.09:32:01.18#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.09:32:01.18#ibcon#[27=AT05-04\r\n] 2006.285.09:32:01.18#ibcon#*before write, iclass 11, count 2 2006.285.09:32:01.18#ibcon#enter sib2, iclass 11, count 2 2006.285.09:32:01.18#ibcon#flushed, iclass 11, count 2 2006.285.09:32:01.18#ibcon#about to write, iclass 11, count 2 2006.285.09:32:01.18#ibcon#wrote, iclass 11, count 2 2006.285.09:32:01.18#ibcon#about to read 3, iclass 11, count 2 2006.285.09:32:01.21#ibcon#read 3, iclass 11, count 2 2006.285.09:32:01.21#ibcon#about to read 4, iclass 11, count 2 2006.285.09:32:01.21#ibcon#read 4, iclass 11, count 2 2006.285.09:32:01.21#ibcon#about to read 5, iclass 11, count 2 2006.285.09:32:01.21#ibcon#read 5, iclass 11, count 2 2006.285.09:32:01.21#ibcon#about to read 6, iclass 11, count 2 2006.285.09:32:01.21#ibcon#read 6, iclass 11, count 2 2006.285.09:32:01.21#ibcon#end of sib2, iclass 11, count 2 2006.285.09:32:01.21#ibcon#*after write, iclass 11, count 2 2006.285.09:32:01.21#ibcon#*before return 0, iclass 11, count 2 2006.285.09:32:01.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:32:01.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.09:32:01.21#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.09:32:01.21#ibcon#ireg 7 cls_cnt 0 2006.285.09:32:01.21#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:32:01.33#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:32:01.33#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:32:01.33#ibcon#enter wrdev, iclass 11, count 0 2006.285.09:32:01.33#ibcon#first serial, iclass 11, count 0 2006.285.09:32:01.33#ibcon#enter sib2, iclass 11, count 0 2006.285.09:32:01.33#ibcon#flushed, iclass 11, count 0 2006.285.09:32:01.33#ibcon#about to write, iclass 11, count 0 2006.285.09:32:01.33#ibcon#wrote, iclass 11, count 0 2006.285.09:32:01.33#ibcon#about to read 3, iclass 11, count 0 2006.285.09:32:01.35#ibcon#read 3, iclass 11, count 0 2006.285.09:32:01.35#ibcon#about to read 4, iclass 11, count 0 2006.285.09:32:01.35#ibcon#read 4, iclass 11, count 0 2006.285.09:32:01.35#ibcon#about to read 5, iclass 11, count 0 2006.285.09:32:01.35#ibcon#read 5, iclass 11, count 0 2006.285.09:32:01.35#ibcon#about to read 6, iclass 11, count 0 2006.285.09:32:01.35#ibcon#read 6, iclass 11, count 0 2006.285.09:32:01.35#ibcon#end of sib2, iclass 11, count 0 2006.285.09:32:01.35#ibcon#*mode == 0, iclass 11, count 0 2006.285.09:32:01.35#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.09:32:01.35#ibcon#[27=USB\r\n] 2006.285.09:32:01.35#ibcon#*before write, iclass 11, count 0 2006.285.09:32:01.35#ibcon#enter sib2, iclass 11, count 0 2006.285.09:32:01.35#ibcon#flushed, iclass 11, count 0 2006.285.09:32:01.35#ibcon#about to write, iclass 11, count 0 2006.285.09:32:01.35#ibcon#wrote, iclass 11, count 0 2006.285.09:32:01.35#ibcon#about to read 3, iclass 11, count 0 2006.285.09:32:01.38#ibcon#read 3, iclass 11, count 0 2006.285.09:32:01.38#ibcon#about to read 4, iclass 11, count 0 2006.285.09:32:01.38#ibcon#read 4, iclass 11, count 0 2006.285.09:32:01.38#ibcon#about to read 5, iclass 11, count 0 2006.285.09:32:01.38#ibcon#read 5, iclass 11, count 0 2006.285.09:32:01.38#ibcon#about to read 6, iclass 11, count 0 2006.285.09:32:01.38#ibcon#read 6, iclass 11, count 0 2006.285.09:32:01.38#ibcon#end of sib2, iclass 11, count 0 2006.285.09:32:01.38#ibcon#*after write, iclass 11, count 0 2006.285.09:32:01.38#ibcon#*before return 0, iclass 11, count 0 2006.285.09:32:01.38#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:32:01.38#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.09:32:01.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.09:32:01.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.09:32:01.38$vck44/vblo=6,719.99 2006.285.09:32:01.38#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.09:32:01.38#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.09:32:01.38#ibcon#ireg 17 cls_cnt 0 2006.285.09:32:01.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:32:01.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:32:01.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:32:01.38#ibcon#enter wrdev, iclass 13, count 0 2006.285.09:32:01.38#ibcon#first serial, iclass 13, count 0 2006.285.09:32:01.38#ibcon#enter sib2, iclass 13, count 0 2006.285.09:32:01.38#ibcon#flushed, iclass 13, count 0 2006.285.09:32:01.38#ibcon#about to write, iclass 13, count 0 2006.285.09:32:01.38#ibcon#wrote, iclass 13, count 0 2006.285.09:32:01.38#ibcon#about to read 3, iclass 13, count 0 2006.285.09:32:01.40#ibcon#read 3, iclass 13, count 0 2006.285.09:32:01.40#ibcon#about to read 4, iclass 13, count 0 2006.285.09:32:01.40#ibcon#read 4, iclass 13, count 0 2006.285.09:32:01.40#ibcon#about to read 5, iclass 13, count 0 2006.285.09:32:01.40#ibcon#read 5, iclass 13, count 0 2006.285.09:32:01.40#ibcon#about to read 6, iclass 13, count 0 2006.285.09:32:01.40#ibcon#read 6, iclass 13, count 0 2006.285.09:32:01.40#ibcon#end of sib2, iclass 13, count 0 2006.285.09:32:01.40#ibcon#*mode == 0, iclass 13, count 0 2006.285.09:32:01.40#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.09:32:01.40#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:32:01.40#ibcon#*before write, iclass 13, count 0 2006.285.09:32:01.40#ibcon#enter sib2, iclass 13, count 0 2006.285.09:32:01.40#ibcon#flushed, iclass 13, count 0 2006.285.09:32:01.40#ibcon#about to write, iclass 13, count 0 2006.285.09:32:01.40#ibcon#wrote, iclass 13, count 0 2006.285.09:32:01.40#ibcon#about to read 3, iclass 13, count 0 2006.285.09:32:01.44#ibcon#read 3, iclass 13, count 0 2006.285.09:32:01.44#ibcon#about to read 4, iclass 13, count 0 2006.285.09:32:01.44#ibcon#read 4, iclass 13, count 0 2006.285.09:32:01.44#ibcon#about to read 5, iclass 13, count 0 2006.285.09:32:01.44#ibcon#read 5, iclass 13, count 0 2006.285.09:32:01.44#ibcon#about to read 6, iclass 13, count 0 2006.285.09:32:01.44#ibcon#read 6, iclass 13, count 0 2006.285.09:32:01.44#ibcon#end of sib2, iclass 13, count 0 2006.285.09:32:01.44#ibcon#*after write, iclass 13, count 0 2006.285.09:32:01.44#ibcon#*before return 0, iclass 13, count 0 2006.285.09:32:01.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:32:01.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.09:32:01.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.09:32:01.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.09:32:01.44$vck44/vb=6,3 2006.285.09:32:01.44#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.09:32:01.44#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.09:32:01.44#ibcon#ireg 11 cls_cnt 2 2006.285.09:32:01.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:32:01.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:32:01.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:32:01.50#ibcon#enter wrdev, iclass 15, count 2 2006.285.09:32:01.50#ibcon#first serial, iclass 15, count 2 2006.285.09:32:01.50#ibcon#enter sib2, iclass 15, count 2 2006.285.09:32:01.50#ibcon#flushed, iclass 15, count 2 2006.285.09:32:01.50#ibcon#about to write, iclass 15, count 2 2006.285.09:32:01.50#ibcon#wrote, iclass 15, count 2 2006.285.09:32:01.50#ibcon#about to read 3, iclass 15, count 2 2006.285.09:32:01.52#ibcon#read 3, iclass 15, count 2 2006.285.09:32:01.52#ibcon#about to read 4, iclass 15, count 2 2006.285.09:32:01.52#ibcon#read 4, iclass 15, count 2 2006.285.09:32:01.52#ibcon#about to read 5, iclass 15, count 2 2006.285.09:32:01.52#ibcon#read 5, iclass 15, count 2 2006.285.09:32:01.52#ibcon#about to read 6, iclass 15, count 2 2006.285.09:32:01.52#ibcon#read 6, iclass 15, count 2 2006.285.09:32:01.52#ibcon#end of sib2, iclass 15, count 2 2006.285.09:32:01.52#ibcon#*mode == 0, iclass 15, count 2 2006.285.09:32:01.52#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.09:32:01.52#ibcon#[27=AT06-03\r\n] 2006.285.09:32:01.52#ibcon#*before write, iclass 15, count 2 2006.285.09:32:01.52#ibcon#enter sib2, iclass 15, count 2 2006.285.09:32:01.52#ibcon#flushed, iclass 15, count 2 2006.285.09:32:01.52#ibcon#about to write, iclass 15, count 2 2006.285.09:32:01.52#ibcon#wrote, iclass 15, count 2 2006.285.09:32:01.52#ibcon#about to read 3, iclass 15, count 2 2006.285.09:32:01.55#ibcon#read 3, iclass 15, count 2 2006.285.09:32:01.55#ibcon#about to read 4, iclass 15, count 2 2006.285.09:32:01.55#ibcon#read 4, iclass 15, count 2 2006.285.09:32:01.55#ibcon#about to read 5, iclass 15, count 2 2006.285.09:32:01.55#ibcon#read 5, iclass 15, count 2 2006.285.09:32:01.55#ibcon#about to read 6, iclass 15, count 2 2006.285.09:32:01.55#ibcon#read 6, iclass 15, count 2 2006.285.09:32:01.55#ibcon#end of sib2, iclass 15, count 2 2006.285.09:32:01.55#ibcon#*after write, iclass 15, count 2 2006.285.09:32:01.55#ibcon#*before return 0, iclass 15, count 2 2006.285.09:32:01.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:32:01.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.09:32:01.55#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.09:32:01.55#ibcon#ireg 7 cls_cnt 0 2006.285.09:32:01.55#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:32:01.67#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:32:01.67#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:32:01.67#ibcon#enter wrdev, iclass 15, count 0 2006.285.09:32:01.67#ibcon#first serial, iclass 15, count 0 2006.285.09:32:01.67#ibcon#enter sib2, iclass 15, count 0 2006.285.09:32:01.67#ibcon#flushed, iclass 15, count 0 2006.285.09:32:01.67#ibcon#about to write, iclass 15, count 0 2006.285.09:32:01.67#ibcon#wrote, iclass 15, count 0 2006.285.09:32:01.67#ibcon#about to read 3, iclass 15, count 0 2006.285.09:32:01.69#ibcon#read 3, iclass 15, count 0 2006.285.09:32:01.69#ibcon#about to read 4, iclass 15, count 0 2006.285.09:32:01.69#ibcon#read 4, iclass 15, count 0 2006.285.09:32:01.69#ibcon#about to read 5, iclass 15, count 0 2006.285.09:32:01.69#ibcon#read 5, iclass 15, count 0 2006.285.09:32:01.69#ibcon#about to read 6, iclass 15, count 0 2006.285.09:32:01.69#ibcon#read 6, iclass 15, count 0 2006.285.09:32:01.69#ibcon#end of sib2, iclass 15, count 0 2006.285.09:32:01.69#ibcon#*mode == 0, iclass 15, count 0 2006.285.09:32:01.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.09:32:01.69#ibcon#[27=USB\r\n] 2006.285.09:32:01.69#ibcon#*before write, iclass 15, count 0 2006.285.09:32:01.69#ibcon#enter sib2, iclass 15, count 0 2006.285.09:32:01.69#ibcon#flushed, iclass 15, count 0 2006.285.09:32:01.69#ibcon#about to write, iclass 15, count 0 2006.285.09:32:01.69#ibcon#wrote, iclass 15, count 0 2006.285.09:32:01.69#ibcon#about to read 3, iclass 15, count 0 2006.285.09:32:01.72#ibcon#read 3, iclass 15, count 0 2006.285.09:32:01.72#ibcon#about to read 4, iclass 15, count 0 2006.285.09:32:01.72#ibcon#read 4, iclass 15, count 0 2006.285.09:32:01.72#ibcon#about to read 5, iclass 15, count 0 2006.285.09:32:01.72#ibcon#read 5, iclass 15, count 0 2006.285.09:32:01.72#ibcon#about to read 6, iclass 15, count 0 2006.285.09:32:01.72#ibcon#read 6, iclass 15, count 0 2006.285.09:32:01.72#ibcon#end of sib2, iclass 15, count 0 2006.285.09:32:01.72#ibcon#*after write, iclass 15, count 0 2006.285.09:32:01.72#ibcon#*before return 0, iclass 15, count 0 2006.285.09:32:01.72#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:32:01.72#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.09:32:01.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.09:32:01.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.09:32:01.72$vck44/vblo=7,734.99 2006.285.09:32:01.72#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.09:32:01.72#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.09:32:01.72#ibcon#ireg 17 cls_cnt 0 2006.285.09:32:01.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:32:01.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:32:01.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:32:01.72#ibcon#enter wrdev, iclass 17, count 0 2006.285.09:32:01.72#ibcon#first serial, iclass 17, count 0 2006.285.09:32:01.72#ibcon#enter sib2, iclass 17, count 0 2006.285.09:32:01.72#ibcon#flushed, iclass 17, count 0 2006.285.09:32:01.72#ibcon#about to write, iclass 17, count 0 2006.285.09:32:01.72#ibcon#wrote, iclass 17, count 0 2006.285.09:32:01.72#ibcon#about to read 3, iclass 17, count 0 2006.285.09:32:01.74#ibcon#read 3, iclass 17, count 0 2006.285.09:32:01.74#ibcon#about to read 4, iclass 17, count 0 2006.285.09:32:01.74#ibcon#read 4, iclass 17, count 0 2006.285.09:32:01.74#ibcon#about to read 5, iclass 17, count 0 2006.285.09:32:01.74#ibcon#read 5, iclass 17, count 0 2006.285.09:32:01.74#ibcon#about to read 6, iclass 17, count 0 2006.285.09:32:01.74#ibcon#read 6, iclass 17, count 0 2006.285.09:32:01.74#ibcon#end of sib2, iclass 17, count 0 2006.285.09:32:01.74#ibcon#*mode == 0, iclass 17, count 0 2006.285.09:32:01.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.09:32:01.74#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:32:01.74#ibcon#*before write, iclass 17, count 0 2006.285.09:32:01.74#ibcon#enter sib2, iclass 17, count 0 2006.285.09:32:01.74#ibcon#flushed, iclass 17, count 0 2006.285.09:32:01.74#ibcon#about to write, iclass 17, count 0 2006.285.09:32:01.74#ibcon#wrote, iclass 17, count 0 2006.285.09:32:01.74#ibcon#about to read 3, iclass 17, count 0 2006.285.09:32:01.78#ibcon#read 3, iclass 17, count 0 2006.285.09:32:01.78#ibcon#about to read 4, iclass 17, count 0 2006.285.09:32:01.78#ibcon#read 4, iclass 17, count 0 2006.285.09:32:01.78#ibcon#about to read 5, iclass 17, count 0 2006.285.09:32:01.78#ibcon#read 5, iclass 17, count 0 2006.285.09:32:01.78#ibcon#about to read 6, iclass 17, count 0 2006.285.09:32:01.78#ibcon#read 6, iclass 17, count 0 2006.285.09:32:01.78#ibcon#end of sib2, iclass 17, count 0 2006.285.09:32:01.78#ibcon#*after write, iclass 17, count 0 2006.285.09:32:01.78#ibcon#*before return 0, iclass 17, count 0 2006.285.09:32:01.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:32:01.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:32:01.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.09:32:01.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.09:32:01.78$vck44/vb=7,4 2006.285.09:32:01.78#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.09:32:01.78#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.09:32:01.78#ibcon#ireg 11 cls_cnt 2 2006.285.09:32:01.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:32:01.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:32:01.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:32:01.84#ibcon#enter wrdev, iclass 19, count 2 2006.285.09:32:01.84#ibcon#first serial, iclass 19, count 2 2006.285.09:32:01.84#ibcon#enter sib2, iclass 19, count 2 2006.285.09:32:01.84#ibcon#flushed, iclass 19, count 2 2006.285.09:32:01.84#ibcon#about to write, iclass 19, count 2 2006.285.09:32:01.84#ibcon#wrote, iclass 19, count 2 2006.285.09:32:01.84#ibcon#about to read 3, iclass 19, count 2 2006.285.09:32:01.86#ibcon#read 3, iclass 19, count 2 2006.285.09:32:01.86#ibcon#about to read 4, iclass 19, count 2 2006.285.09:32:01.86#ibcon#read 4, iclass 19, count 2 2006.285.09:32:01.86#ibcon#about to read 5, iclass 19, count 2 2006.285.09:32:01.86#ibcon#read 5, iclass 19, count 2 2006.285.09:32:01.86#ibcon#about to read 6, iclass 19, count 2 2006.285.09:32:01.86#ibcon#read 6, iclass 19, count 2 2006.285.09:32:01.86#ibcon#end of sib2, iclass 19, count 2 2006.285.09:32:01.86#ibcon#*mode == 0, iclass 19, count 2 2006.285.09:32:01.86#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.09:32:01.86#ibcon#[27=AT07-04\r\n] 2006.285.09:32:01.86#ibcon#*before write, iclass 19, count 2 2006.285.09:32:01.86#ibcon#enter sib2, iclass 19, count 2 2006.285.09:32:01.86#ibcon#flushed, iclass 19, count 2 2006.285.09:32:01.86#ibcon#about to write, iclass 19, count 2 2006.285.09:32:01.86#ibcon#wrote, iclass 19, count 2 2006.285.09:32:01.86#ibcon#about to read 3, iclass 19, count 2 2006.285.09:32:01.89#ibcon#read 3, iclass 19, count 2 2006.285.09:32:01.89#ibcon#about to read 4, iclass 19, count 2 2006.285.09:32:01.89#ibcon#read 4, iclass 19, count 2 2006.285.09:32:01.89#ibcon#about to read 5, iclass 19, count 2 2006.285.09:32:01.89#ibcon#read 5, iclass 19, count 2 2006.285.09:32:01.89#ibcon#about to read 6, iclass 19, count 2 2006.285.09:32:01.89#ibcon#read 6, iclass 19, count 2 2006.285.09:32:01.89#ibcon#end of sib2, iclass 19, count 2 2006.285.09:32:01.89#ibcon#*after write, iclass 19, count 2 2006.285.09:32:01.89#ibcon#*before return 0, iclass 19, count 2 2006.285.09:32:01.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:32:01.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.09:32:01.89#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.09:32:01.89#ibcon#ireg 7 cls_cnt 0 2006.285.09:32:01.89#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:32:02.01#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:32:02.01#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:32:02.01#ibcon#enter wrdev, iclass 19, count 0 2006.285.09:32:02.01#ibcon#first serial, iclass 19, count 0 2006.285.09:32:02.01#ibcon#enter sib2, iclass 19, count 0 2006.285.09:32:02.01#ibcon#flushed, iclass 19, count 0 2006.285.09:32:02.01#ibcon#about to write, iclass 19, count 0 2006.285.09:32:02.01#ibcon#wrote, iclass 19, count 0 2006.285.09:32:02.01#ibcon#about to read 3, iclass 19, count 0 2006.285.09:32:02.03#ibcon#read 3, iclass 19, count 0 2006.285.09:32:02.03#ibcon#about to read 4, iclass 19, count 0 2006.285.09:32:02.03#ibcon#read 4, iclass 19, count 0 2006.285.09:32:02.03#ibcon#about to read 5, iclass 19, count 0 2006.285.09:32:02.03#ibcon#read 5, iclass 19, count 0 2006.285.09:32:02.03#ibcon#about to read 6, iclass 19, count 0 2006.285.09:32:02.03#ibcon#read 6, iclass 19, count 0 2006.285.09:32:02.03#ibcon#end of sib2, iclass 19, count 0 2006.285.09:32:02.03#ibcon#*mode == 0, iclass 19, count 0 2006.285.09:32:02.03#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.09:32:02.03#ibcon#[27=USB\r\n] 2006.285.09:32:02.03#ibcon#*before write, iclass 19, count 0 2006.285.09:32:02.03#ibcon#enter sib2, iclass 19, count 0 2006.285.09:32:02.03#ibcon#flushed, iclass 19, count 0 2006.285.09:32:02.03#ibcon#about to write, iclass 19, count 0 2006.285.09:32:02.03#ibcon#wrote, iclass 19, count 0 2006.285.09:32:02.03#ibcon#about to read 3, iclass 19, count 0 2006.285.09:32:02.06#ibcon#read 3, iclass 19, count 0 2006.285.09:32:02.06#ibcon#about to read 4, iclass 19, count 0 2006.285.09:32:02.06#ibcon#read 4, iclass 19, count 0 2006.285.09:32:02.06#ibcon#about to read 5, iclass 19, count 0 2006.285.09:32:02.06#ibcon#read 5, iclass 19, count 0 2006.285.09:32:02.06#ibcon#about to read 6, iclass 19, count 0 2006.285.09:32:02.06#ibcon#read 6, iclass 19, count 0 2006.285.09:32:02.06#ibcon#end of sib2, iclass 19, count 0 2006.285.09:32:02.06#ibcon#*after write, iclass 19, count 0 2006.285.09:32:02.06#ibcon#*before return 0, iclass 19, count 0 2006.285.09:32:02.06#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:32:02.06#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.09:32:02.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.09:32:02.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.09:32:02.06$vck44/vblo=8,744.99 2006.285.09:32:02.06#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.09:32:02.06#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.09:32:02.06#ibcon#ireg 17 cls_cnt 0 2006.285.09:32:02.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:32:02.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:32:02.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:32:02.06#ibcon#enter wrdev, iclass 21, count 0 2006.285.09:32:02.06#ibcon#first serial, iclass 21, count 0 2006.285.09:32:02.06#ibcon#enter sib2, iclass 21, count 0 2006.285.09:32:02.06#ibcon#flushed, iclass 21, count 0 2006.285.09:32:02.06#ibcon#about to write, iclass 21, count 0 2006.285.09:32:02.06#ibcon#wrote, iclass 21, count 0 2006.285.09:32:02.06#ibcon#about to read 3, iclass 21, count 0 2006.285.09:32:02.08#ibcon#read 3, iclass 21, count 0 2006.285.09:32:02.08#ibcon#about to read 4, iclass 21, count 0 2006.285.09:32:02.08#ibcon#read 4, iclass 21, count 0 2006.285.09:32:02.08#ibcon#about to read 5, iclass 21, count 0 2006.285.09:32:02.08#ibcon#read 5, iclass 21, count 0 2006.285.09:32:02.08#ibcon#about to read 6, iclass 21, count 0 2006.285.09:32:02.08#ibcon#read 6, iclass 21, count 0 2006.285.09:32:02.08#ibcon#end of sib2, iclass 21, count 0 2006.285.09:32:02.08#ibcon#*mode == 0, iclass 21, count 0 2006.285.09:32:02.08#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.09:32:02.08#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:32:02.08#ibcon#*before write, iclass 21, count 0 2006.285.09:32:02.08#ibcon#enter sib2, iclass 21, count 0 2006.285.09:32:02.08#ibcon#flushed, iclass 21, count 0 2006.285.09:32:02.08#ibcon#about to write, iclass 21, count 0 2006.285.09:32:02.08#ibcon#wrote, iclass 21, count 0 2006.285.09:32:02.08#ibcon#about to read 3, iclass 21, count 0 2006.285.09:32:02.12#ibcon#read 3, iclass 21, count 0 2006.285.09:32:02.12#ibcon#about to read 4, iclass 21, count 0 2006.285.09:32:02.12#ibcon#read 4, iclass 21, count 0 2006.285.09:32:02.12#ibcon#about to read 5, iclass 21, count 0 2006.285.09:32:02.12#ibcon#read 5, iclass 21, count 0 2006.285.09:32:02.12#ibcon#about to read 6, iclass 21, count 0 2006.285.09:32:02.12#ibcon#read 6, iclass 21, count 0 2006.285.09:32:02.12#ibcon#end of sib2, iclass 21, count 0 2006.285.09:32:02.12#ibcon#*after write, iclass 21, count 0 2006.285.09:32:02.12#ibcon#*before return 0, iclass 21, count 0 2006.285.09:32:02.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:32:02.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.09:32:02.12#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.09:32:02.12#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.09:32:02.12$vck44/vb=8,4 2006.285.09:32:02.12#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.09:32:02.12#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.09:32:02.12#ibcon#ireg 11 cls_cnt 2 2006.285.09:32:02.12#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:32:02.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:32:02.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:32:02.18#ibcon#enter wrdev, iclass 23, count 2 2006.285.09:32:02.18#ibcon#first serial, iclass 23, count 2 2006.285.09:32:02.18#ibcon#enter sib2, iclass 23, count 2 2006.285.09:32:02.18#ibcon#flushed, iclass 23, count 2 2006.285.09:32:02.18#ibcon#about to write, iclass 23, count 2 2006.285.09:32:02.18#ibcon#wrote, iclass 23, count 2 2006.285.09:32:02.18#ibcon#about to read 3, iclass 23, count 2 2006.285.09:32:02.20#ibcon#read 3, iclass 23, count 2 2006.285.09:32:02.20#ibcon#about to read 4, iclass 23, count 2 2006.285.09:32:02.20#ibcon#read 4, iclass 23, count 2 2006.285.09:32:02.20#ibcon#about to read 5, iclass 23, count 2 2006.285.09:32:02.20#ibcon#read 5, iclass 23, count 2 2006.285.09:32:02.20#ibcon#about to read 6, iclass 23, count 2 2006.285.09:32:02.20#ibcon#read 6, iclass 23, count 2 2006.285.09:32:02.20#ibcon#end of sib2, iclass 23, count 2 2006.285.09:32:02.20#ibcon#*mode == 0, iclass 23, count 2 2006.285.09:32:02.20#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.09:32:02.20#ibcon#[27=AT08-04\r\n] 2006.285.09:32:02.20#ibcon#*before write, iclass 23, count 2 2006.285.09:32:02.20#ibcon#enter sib2, iclass 23, count 2 2006.285.09:32:02.20#ibcon#flushed, iclass 23, count 2 2006.285.09:32:02.20#ibcon#about to write, iclass 23, count 2 2006.285.09:32:02.20#ibcon#wrote, iclass 23, count 2 2006.285.09:32:02.20#ibcon#about to read 3, iclass 23, count 2 2006.285.09:32:02.23#ibcon#read 3, iclass 23, count 2 2006.285.09:32:02.23#ibcon#about to read 4, iclass 23, count 2 2006.285.09:32:02.23#ibcon#read 4, iclass 23, count 2 2006.285.09:32:02.23#ibcon#about to read 5, iclass 23, count 2 2006.285.09:32:02.23#ibcon#read 5, iclass 23, count 2 2006.285.09:32:02.23#ibcon#about to read 6, iclass 23, count 2 2006.285.09:32:02.23#ibcon#read 6, iclass 23, count 2 2006.285.09:32:02.23#ibcon#end of sib2, iclass 23, count 2 2006.285.09:32:02.23#ibcon#*after write, iclass 23, count 2 2006.285.09:32:02.23#ibcon#*before return 0, iclass 23, count 2 2006.285.09:32:02.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:32:02.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.09:32:02.23#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.09:32:02.23#ibcon#ireg 7 cls_cnt 0 2006.285.09:32:02.23#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:32:02.35#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:32:02.35#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:32:02.35#ibcon#enter wrdev, iclass 23, count 0 2006.285.09:32:02.35#ibcon#first serial, iclass 23, count 0 2006.285.09:32:02.35#ibcon#enter sib2, iclass 23, count 0 2006.285.09:32:02.35#ibcon#flushed, iclass 23, count 0 2006.285.09:32:02.35#ibcon#about to write, iclass 23, count 0 2006.285.09:32:02.35#ibcon#wrote, iclass 23, count 0 2006.285.09:32:02.35#ibcon#about to read 3, iclass 23, count 0 2006.285.09:32:02.37#ibcon#read 3, iclass 23, count 0 2006.285.09:32:02.37#ibcon#about to read 4, iclass 23, count 0 2006.285.09:32:02.37#ibcon#read 4, iclass 23, count 0 2006.285.09:32:02.37#ibcon#about to read 5, iclass 23, count 0 2006.285.09:32:02.37#ibcon#read 5, iclass 23, count 0 2006.285.09:32:02.37#ibcon#about to read 6, iclass 23, count 0 2006.285.09:32:02.37#ibcon#read 6, iclass 23, count 0 2006.285.09:32:02.37#ibcon#end of sib2, iclass 23, count 0 2006.285.09:32:02.37#ibcon#*mode == 0, iclass 23, count 0 2006.285.09:32:02.37#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.09:32:02.37#ibcon#[27=USB\r\n] 2006.285.09:32:02.37#ibcon#*before write, iclass 23, count 0 2006.285.09:32:02.37#ibcon#enter sib2, iclass 23, count 0 2006.285.09:32:02.37#ibcon#flushed, iclass 23, count 0 2006.285.09:32:02.37#ibcon#about to write, iclass 23, count 0 2006.285.09:32:02.37#ibcon#wrote, iclass 23, count 0 2006.285.09:32:02.37#ibcon#about to read 3, iclass 23, count 0 2006.285.09:32:02.40#ibcon#read 3, iclass 23, count 0 2006.285.09:32:02.40#ibcon#about to read 4, iclass 23, count 0 2006.285.09:32:02.40#ibcon#read 4, iclass 23, count 0 2006.285.09:32:02.40#ibcon#about to read 5, iclass 23, count 0 2006.285.09:32:02.40#ibcon#read 5, iclass 23, count 0 2006.285.09:32:02.40#ibcon#about to read 6, iclass 23, count 0 2006.285.09:32:02.40#ibcon#read 6, iclass 23, count 0 2006.285.09:32:02.40#ibcon#end of sib2, iclass 23, count 0 2006.285.09:32:02.40#ibcon#*after write, iclass 23, count 0 2006.285.09:32:02.40#ibcon#*before return 0, iclass 23, count 0 2006.285.09:32:02.40#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:32:02.40#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.09:32:02.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.09:32:02.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.09:32:02.40$vck44/vabw=wide 2006.285.09:32:02.40#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.09:32:02.40#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.09:32:02.40#ibcon#ireg 8 cls_cnt 0 2006.285.09:32:02.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:32:02.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:32:02.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:32:02.40#ibcon#enter wrdev, iclass 25, count 0 2006.285.09:32:02.40#ibcon#first serial, iclass 25, count 0 2006.285.09:32:02.40#ibcon#enter sib2, iclass 25, count 0 2006.285.09:32:02.40#ibcon#flushed, iclass 25, count 0 2006.285.09:32:02.40#ibcon#about to write, iclass 25, count 0 2006.285.09:32:02.40#ibcon#wrote, iclass 25, count 0 2006.285.09:32:02.40#ibcon#about to read 3, iclass 25, count 0 2006.285.09:32:02.42#ibcon#read 3, iclass 25, count 0 2006.285.09:32:02.42#ibcon#about to read 4, iclass 25, count 0 2006.285.09:32:02.42#ibcon#read 4, iclass 25, count 0 2006.285.09:32:02.42#ibcon#about to read 5, iclass 25, count 0 2006.285.09:32:02.42#ibcon#read 5, iclass 25, count 0 2006.285.09:32:02.42#ibcon#about to read 6, iclass 25, count 0 2006.285.09:32:02.42#ibcon#read 6, iclass 25, count 0 2006.285.09:32:02.42#ibcon#end of sib2, iclass 25, count 0 2006.285.09:32:02.42#ibcon#*mode == 0, iclass 25, count 0 2006.285.09:32:02.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.09:32:02.42#ibcon#[25=BW32\r\n] 2006.285.09:32:02.42#ibcon#*before write, iclass 25, count 0 2006.285.09:32:02.42#ibcon#enter sib2, iclass 25, count 0 2006.285.09:32:02.42#ibcon#flushed, iclass 25, count 0 2006.285.09:32:02.42#ibcon#about to write, iclass 25, count 0 2006.285.09:32:02.42#ibcon#wrote, iclass 25, count 0 2006.285.09:32:02.42#ibcon#about to read 3, iclass 25, count 0 2006.285.09:32:02.45#ibcon#read 3, iclass 25, count 0 2006.285.09:32:02.45#ibcon#about to read 4, iclass 25, count 0 2006.285.09:32:02.45#ibcon#read 4, iclass 25, count 0 2006.285.09:32:02.45#ibcon#about to read 5, iclass 25, count 0 2006.285.09:32:02.45#ibcon#read 5, iclass 25, count 0 2006.285.09:32:02.45#ibcon#about to read 6, iclass 25, count 0 2006.285.09:32:02.45#ibcon#read 6, iclass 25, count 0 2006.285.09:32:02.45#ibcon#end of sib2, iclass 25, count 0 2006.285.09:32:02.45#ibcon#*after write, iclass 25, count 0 2006.285.09:32:02.45#ibcon#*before return 0, iclass 25, count 0 2006.285.09:32:02.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:32:02.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.09:32:02.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.09:32:02.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.09:32:02.45$vck44/vbbw=wide 2006.285.09:32:02.45#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.09:32:02.45#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.09:32:02.45#ibcon#ireg 8 cls_cnt 0 2006.285.09:32:02.45#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:32:02.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:32:02.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:32:02.52#ibcon#enter wrdev, iclass 27, count 0 2006.285.09:32:02.52#ibcon#first serial, iclass 27, count 0 2006.285.09:32:02.52#ibcon#enter sib2, iclass 27, count 0 2006.285.09:32:02.52#ibcon#flushed, iclass 27, count 0 2006.285.09:32:02.52#ibcon#about to write, iclass 27, count 0 2006.285.09:32:02.52#ibcon#wrote, iclass 27, count 0 2006.285.09:32:02.52#ibcon#about to read 3, iclass 27, count 0 2006.285.09:32:02.54#ibcon#read 3, iclass 27, count 0 2006.285.09:32:02.54#ibcon#about to read 4, iclass 27, count 0 2006.285.09:32:02.54#ibcon#read 4, iclass 27, count 0 2006.285.09:32:02.54#ibcon#about to read 5, iclass 27, count 0 2006.285.09:32:02.54#ibcon#read 5, iclass 27, count 0 2006.285.09:32:02.54#ibcon#about to read 6, iclass 27, count 0 2006.285.09:32:02.54#ibcon#read 6, iclass 27, count 0 2006.285.09:32:02.54#ibcon#end of sib2, iclass 27, count 0 2006.285.09:32:02.54#ibcon#*mode == 0, iclass 27, count 0 2006.285.09:32:02.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.09:32:02.54#ibcon#[27=BW32\r\n] 2006.285.09:32:02.54#ibcon#*before write, iclass 27, count 0 2006.285.09:32:02.54#ibcon#enter sib2, iclass 27, count 0 2006.285.09:32:02.54#ibcon#flushed, iclass 27, count 0 2006.285.09:32:02.54#ibcon#about to write, iclass 27, count 0 2006.285.09:32:02.54#ibcon#wrote, iclass 27, count 0 2006.285.09:32:02.54#ibcon#about to read 3, iclass 27, count 0 2006.285.09:32:02.57#ibcon#read 3, iclass 27, count 0 2006.285.09:32:02.57#ibcon#about to read 4, iclass 27, count 0 2006.285.09:32:02.57#ibcon#read 4, iclass 27, count 0 2006.285.09:32:02.57#ibcon#about to read 5, iclass 27, count 0 2006.285.09:32:02.57#ibcon#read 5, iclass 27, count 0 2006.285.09:32:02.57#ibcon#about to read 6, iclass 27, count 0 2006.285.09:32:02.57#ibcon#read 6, iclass 27, count 0 2006.285.09:32:02.57#ibcon#end of sib2, iclass 27, count 0 2006.285.09:32:02.57#ibcon#*after write, iclass 27, count 0 2006.285.09:32:02.57#ibcon#*before return 0, iclass 27, count 0 2006.285.09:32:02.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:32:02.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:32:02.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.09:32:02.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.09:32:02.57$setupk4/ifdk4 2006.285.09:32:02.57$ifdk4/lo= 2006.285.09:32:02.57$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:32:02.57$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:32:02.57$ifdk4/patch= 2006.285.09:32:02.57$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:32:02.58$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:32:02.58$setupk4/!*+20s 2006.285.09:32:08.37#abcon#<5=/02 0.7 1.3 19.52 911015.0\r\n> 2006.285.09:32:08.39#abcon#{5=INTERFACE CLEAR} 2006.285.09:32:08.45#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:32:13.14#trakl#Source acquired 2006.285.09:32:13.14#flagr#flagr/antenna,acquired 2006.285.09:32:17.09$setupk4/"tpicd 2006.285.09:32:17.09$setupk4/echo=off 2006.285.09:32:17.09$setupk4/xlog=off 2006.285.09:32:17.09:!2006.285.09:34:43 2006.285.09:34:43.00:preob 2006.285.09:34:44.14/onsource/TRACKING 2006.285.09:34:44.14:!2006.285.09:34:53 2006.285.09:34:53.00:"tape 2006.285.09:34:53.00:"st=record 2006.285.09:34:53.00:data_valid=on 2006.285.09:34:53.00:midob 2006.285.09:34:53.14/onsource/TRACKING 2006.285.09:34:53.14/wx/19.45,1015.1,92 2006.285.09:34:53.35/cable/+6.4810E-03 2006.285.09:34:54.44/va/01,07,usb,yes,32,35 2006.285.09:34:54.44/va/02,06,usb,yes,32,32 2006.285.09:34:54.44/va/03,07,usb,yes,32,33 2006.285.09:34:54.44/va/04,06,usb,yes,33,34 2006.285.09:34:54.44/va/05,03,usb,yes,32,33 2006.285.09:34:54.44/va/06,04,usb,yes,29,29 2006.285.09:34:54.44/va/07,04,usb,yes,30,30 2006.285.09:34:54.44/va/08,03,usb,yes,30,37 2006.285.09:34:54.67/valo/01,524.99,yes,locked 2006.285.09:34:54.67/valo/02,534.99,yes,locked 2006.285.09:34:54.67/valo/03,564.99,yes,locked 2006.285.09:34:54.67/valo/04,624.99,yes,locked 2006.285.09:34:54.67/valo/05,734.99,yes,locked 2006.285.09:34:54.67/valo/06,814.99,yes,locked 2006.285.09:34:54.67/valo/07,864.99,yes,locked 2006.285.09:34:54.67/valo/08,884.99,yes,locked 2006.285.09:34:55.76/vb/01,04,usb,yes,30,28 2006.285.09:34:55.76/vb/02,05,usb,yes,29,29 2006.285.09:34:55.76/vb/03,04,usb,yes,30,33 2006.285.09:34:55.76/vb/04,05,usb,yes,30,29 2006.285.09:34:55.76/vb/05,04,usb,yes,26,29 2006.285.09:34:55.76/vb/06,03,usb,yes,38,33 2006.285.09:34:55.76/vb/07,04,usb,yes,30,30 2006.285.09:34:55.76/vb/08,04,usb,yes,28,31 2006.285.09:34:55.99/vblo/01,629.99,yes,locked 2006.285.09:34:55.99/vblo/02,634.99,yes,locked 2006.285.09:34:55.99/vblo/03,649.99,yes,locked 2006.285.09:34:55.99/vblo/04,679.99,yes,locked 2006.285.09:34:55.99/vblo/05,709.99,yes,locked 2006.285.09:34:55.99/vblo/06,719.99,yes,locked 2006.285.09:34:55.99/vblo/07,734.99,yes,locked 2006.285.09:34:55.99/vblo/08,744.99,yes,locked 2006.285.09:34:56.14/vabw/8 2006.285.09:34:56.29/vbbw/8 2006.285.09:34:56.39/xfe/off,on,12.2 2006.285.09:34:56.76/ifatt/23,28,28,28 2006.285.09:34:57.08/fmout-gps/S +2.61E-07 2006.285.09:34:57.10:!2006.285.09:36:43 2006.285.09:36:43.00:data_valid=off 2006.285.09:36:43.00:"et 2006.285.09:36:43.00:!+3s 2006.285.09:36:46.01:"tape 2006.285.09:36:46.01:postob 2006.285.09:36:46.07/cable/+6.4821E-03 2006.285.09:36:46.07/wx/19.43,1015.1,93 2006.285.09:36:47.07/fmout-gps/S +2.55E-07 2006.285.09:36:47.07:scan_name=285-0941,jd0610,160 2006.285.09:36:47.07:source=2201+315,220314.98,314538.3,2000.0,cw 2006.285.09:36:48.14#flagr#flagr/antenna,new-source 2006.285.09:36:48.14:checkk5 2006.285.09:36:48.58/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:36:48.96/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:36:49.91/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:36:50.32/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:36:50.73/chk_obsdata//k5ts1/T2850934??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.09:36:51.09/chk_obsdata//k5ts2/T2850934??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.09:36:51.49/chk_obsdata//k5ts3/T2850934??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.09:36:51.84/chk_obsdata//k5ts4/T2850934??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.09:36:52.77/k5log//k5ts1_log_newline 2006.285.09:36:53.60/k5log//k5ts2_log_newline 2006.285.09:36:54.36/k5log//k5ts3_log_newline 2006.285.09:36:55.04/k5log//k5ts4_log_newline 2006.285.09:36:55.06/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:36:55.06:setupk4=1 2006.285.09:36:55.06$setupk4/echo=on 2006.285.09:36:55.06$setupk4/pcalon 2006.285.09:36:55.06$pcalon/"no phase cal control is implemented here 2006.285.09:36:55.06$setupk4/"tpicd=stop 2006.285.09:36:55.06$setupk4/"rec=synch_on 2006.285.09:36:55.06$setupk4/"rec_mode=128 2006.285.09:36:55.06$setupk4/!* 2006.285.09:36:55.06$setupk4/recpk4 2006.285.09:36:55.06$recpk4/recpatch= 2006.285.09:36:55.07$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:36:55.07$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:36:55.07$setupk4/vck44 2006.285.09:36:55.07$vck44/valo=1,524.99 2006.285.09:36:55.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.09:36:55.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.09:36:55.07#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:55.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:36:55.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:36:55.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:36:55.07#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:36:55.07#ibcon#first serial, iclass 40, count 0 2006.285.09:36:55.07#ibcon#enter sib2, iclass 40, count 0 2006.285.09:36:55.07#ibcon#flushed, iclass 40, count 0 2006.285.09:36:55.07#ibcon#about to write, iclass 40, count 0 2006.285.09:36:55.07#ibcon#wrote, iclass 40, count 0 2006.285.09:36:55.07#ibcon#about to read 3, iclass 40, count 0 2006.285.09:36:55.08#ibcon#read 3, iclass 40, count 0 2006.285.09:36:55.08#ibcon#about to read 4, iclass 40, count 0 2006.285.09:36:55.08#ibcon#read 4, iclass 40, count 0 2006.285.09:36:55.08#ibcon#about to read 5, iclass 40, count 0 2006.285.09:36:55.08#ibcon#read 5, iclass 40, count 0 2006.285.09:36:55.08#ibcon#about to read 6, iclass 40, count 0 2006.285.09:36:55.08#ibcon#read 6, iclass 40, count 0 2006.285.09:36:55.08#ibcon#end of sib2, iclass 40, count 0 2006.285.09:36:55.08#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:36:55.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:36:55.08#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:36:55.08#ibcon#*before write, iclass 40, count 0 2006.285.09:36:55.08#ibcon#enter sib2, iclass 40, count 0 2006.285.09:36:55.08#ibcon#flushed, iclass 40, count 0 2006.285.09:36:55.08#ibcon#about to write, iclass 40, count 0 2006.285.09:36:55.08#ibcon#wrote, iclass 40, count 0 2006.285.09:36:55.08#ibcon#about to read 3, iclass 40, count 0 2006.285.09:36:55.13#ibcon#read 3, iclass 40, count 0 2006.285.09:36:55.13#ibcon#about to read 4, iclass 40, count 0 2006.285.09:36:55.13#ibcon#read 4, iclass 40, count 0 2006.285.09:36:55.13#ibcon#about to read 5, iclass 40, count 0 2006.285.09:36:55.13#ibcon#read 5, iclass 40, count 0 2006.285.09:36:55.13#ibcon#about to read 6, iclass 40, count 0 2006.285.09:36:55.13#ibcon#read 6, iclass 40, count 0 2006.285.09:36:55.13#ibcon#end of sib2, iclass 40, count 0 2006.285.09:36:55.13#ibcon#*after write, iclass 40, count 0 2006.285.09:36:55.13#ibcon#*before return 0, iclass 40, count 0 2006.285.09:36:55.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:36:55.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:36:55.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:36:55.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:36:55.13$vck44/va=1,7 2006.285.09:36:55.13#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.09:36:55.13#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.09:36:55.13#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:55.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:36:55.13#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:36:55.13#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:36:55.13#ibcon#enter wrdev, iclass 4, count 2 2006.285.09:36:55.13#ibcon#first serial, iclass 4, count 2 2006.285.09:36:55.13#ibcon#enter sib2, iclass 4, count 2 2006.285.09:36:55.13#ibcon#flushed, iclass 4, count 2 2006.285.09:36:55.13#ibcon#about to write, iclass 4, count 2 2006.285.09:36:55.13#ibcon#wrote, iclass 4, count 2 2006.285.09:36:55.13#ibcon#about to read 3, iclass 4, count 2 2006.285.09:36:55.15#ibcon#read 3, iclass 4, count 2 2006.285.09:36:55.15#ibcon#about to read 4, iclass 4, count 2 2006.285.09:36:55.15#ibcon#read 4, iclass 4, count 2 2006.285.09:36:55.15#ibcon#about to read 5, iclass 4, count 2 2006.285.09:36:55.15#ibcon#read 5, iclass 4, count 2 2006.285.09:36:55.15#ibcon#about to read 6, iclass 4, count 2 2006.285.09:36:55.15#ibcon#read 6, iclass 4, count 2 2006.285.09:36:55.15#ibcon#end of sib2, iclass 4, count 2 2006.285.09:36:55.15#ibcon#*mode == 0, iclass 4, count 2 2006.285.09:36:55.15#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.09:36:55.15#ibcon#[25=AT01-07\r\n] 2006.285.09:36:55.15#ibcon#*before write, iclass 4, count 2 2006.285.09:36:55.15#ibcon#enter sib2, iclass 4, count 2 2006.285.09:36:55.15#ibcon#flushed, iclass 4, count 2 2006.285.09:36:55.15#ibcon#about to write, iclass 4, count 2 2006.285.09:36:55.15#ibcon#wrote, iclass 4, count 2 2006.285.09:36:55.15#ibcon#about to read 3, iclass 4, count 2 2006.285.09:36:55.18#ibcon#read 3, iclass 4, count 2 2006.285.09:36:55.18#ibcon#about to read 4, iclass 4, count 2 2006.285.09:36:55.18#ibcon#read 4, iclass 4, count 2 2006.285.09:36:55.18#ibcon#about to read 5, iclass 4, count 2 2006.285.09:36:55.18#ibcon#read 5, iclass 4, count 2 2006.285.09:36:55.18#ibcon#about to read 6, iclass 4, count 2 2006.285.09:36:55.18#ibcon#read 6, iclass 4, count 2 2006.285.09:36:55.18#ibcon#end of sib2, iclass 4, count 2 2006.285.09:36:55.18#ibcon#*after write, iclass 4, count 2 2006.285.09:36:55.18#ibcon#*before return 0, iclass 4, count 2 2006.285.09:36:55.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:36:55.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:36:55.18#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.09:36:55.18#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:55.18#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:36:55.30#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:36:55.30#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:36:55.30#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:36:55.30#ibcon#first serial, iclass 4, count 0 2006.285.09:36:55.30#ibcon#enter sib2, iclass 4, count 0 2006.285.09:36:55.30#ibcon#flushed, iclass 4, count 0 2006.285.09:36:55.30#ibcon#about to write, iclass 4, count 0 2006.285.09:36:55.30#ibcon#wrote, iclass 4, count 0 2006.285.09:36:55.30#ibcon#about to read 3, iclass 4, count 0 2006.285.09:36:55.32#ibcon#read 3, iclass 4, count 0 2006.285.09:36:55.32#ibcon#about to read 4, iclass 4, count 0 2006.285.09:36:55.32#ibcon#read 4, iclass 4, count 0 2006.285.09:36:55.32#ibcon#about to read 5, iclass 4, count 0 2006.285.09:36:55.32#ibcon#read 5, iclass 4, count 0 2006.285.09:36:55.32#ibcon#about to read 6, iclass 4, count 0 2006.285.09:36:55.32#ibcon#read 6, iclass 4, count 0 2006.285.09:36:55.32#ibcon#end of sib2, iclass 4, count 0 2006.285.09:36:55.32#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:36:55.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:36:55.32#ibcon#[25=USB\r\n] 2006.285.09:36:55.32#ibcon#*before write, iclass 4, count 0 2006.285.09:36:55.32#ibcon#enter sib2, iclass 4, count 0 2006.285.09:36:55.32#ibcon#flushed, iclass 4, count 0 2006.285.09:36:55.32#ibcon#about to write, iclass 4, count 0 2006.285.09:36:55.32#ibcon#wrote, iclass 4, count 0 2006.285.09:36:55.32#ibcon#about to read 3, iclass 4, count 0 2006.285.09:36:55.35#ibcon#read 3, iclass 4, count 0 2006.285.09:36:55.35#ibcon#about to read 4, iclass 4, count 0 2006.285.09:36:55.35#ibcon#read 4, iclass 4, count 0 2006.285.09:36:55.35#ibcon#about to read 5, iclass 4, count 0 2006.285.09:36:55.35#ibcon#read 5, iclass 4, count 0 2006.285.09:36:55.35#ibcon#about to read 6, iclass 4, count 0 2006.285.09:36:55.35#ibcon#read 6, iclass 4, count 0 2006.285.09:36:55.35#ibcon#end of sib2, iclass 4, count 0 2006.285.09:36:55.35#ibcon#*after write, iclass 4, count 0 2006.285.09:36:55.35#ibcon#*before return 0, iclass 4, count 0 2006.285.09:36:55.35#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:36:55.35#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:36:55.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:36:55.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:36:55.35$vck44/valo=2,534.99 2006.285.09:36:55.35#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.09:36:55.35#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.09:36:55.35#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:55.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:36:55.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:36:55.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:36:55.35#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:36:55.35#ibcon#first serial, iclass 6, count 0 2006.285.09:36:55.35#ibcon#enter sib2, iclass 6, count 0 2006.285.09:36:55.35#ibcon#flushed, iclass 6, count 0 2006.285.09:36:55.35#ibcon#about to write, iclass 6, count 0 2006.285.09:36:55.35#ibcon#wrote, iclass 6, count 0 2006.285.09:36:55.35#ibcon#about to read 3, iclass 6, count 0 2006.285.09:36:55.37#ibcon#read 3, iclass 6, count 0 2006.285.09:36:55.37#ibcon#about to read 4, iclass 6, count 0 2006.285.09:36:55.37#ibcon#read 4, iclass 6, count 0 2006.285.09:36:55.37#ibcon#about to read 5, iclass 6, count 0 2006.285.09:36:55.37#ibcon#read 5, iclass 6, count 0 2006.285.09:36:55.37#ibcon#about to read 6, iclass 6, count 0 2006.285.09:36:55.37#ibcon#read 6, iclass 6, count 0 2006.285.09:36:55.37#ibcon#end of sib2, iclass 6, count 0 2006.285.09:36:55.37#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:36:55.37#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:36:55.37#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:36:55.37#ibcon#*before write, iclass 6, count 0 2006.285.09:36:55.37#ibcon#enter sib2, iclass 6, count 0 2006.285.09:36:55.37#ibcon#flushed, iclass 6, count 0 2006.285.09:36:55.37#ibcon#about to write, iclass 6, count 0 2006.285.09:36:55.37#ibcon#wrote, iclass 6, count 0 2006.285.09:36:55.37#ibcon#about to read 3, iclass 6, count 0 2006.285.09:36:55.41#ibcon#read 3, iclass 6, count 0 2006.285.09:36:55.41#ibcon#about to read 4, iclass 6, count 0 2006.285.09:36:55.41#ibcon#read 4, iclass 6, count 0 2006.285.09:36:55.41#ibcon#about to read 5, iclass 6, count 0 2006.285.09:36:55.41#ibcon#read 5, iclass 6, count 0 2006.285.09:36:55.41#ibcon#about to read 6, iclass 6, count 0 2006.285.09:36:55.41#ibcon#read 6, iclass 6, count 0 2006.285.09:36:55.41#ibcon#end of sib2, iclass 6, count 0 2006.285.09:36:55.41#ibcon#*after write, iclass 6, count 0 2006.285.09:36:55.41#ibcon#*before return 0, iclass 6, count 0 2006.285.09:36:55.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:36:55.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:36:55.41#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:36:55.41#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:36:55.41$vck44/va=2,6 2006.285.09:36:55.41#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.09:36:55.41#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.09:36:55.41#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:55.41#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:36:55.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:36:55.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:36:55.47#ibcon#enter wrdev, iclass 10, count 2 2006.285.09:36:55.47#ibcon#first serial, iclass 10, count 2 2006.285.09:36:55.47#ibcon#enter sib2, iclass 10, count 2 2006.285.09:36:55.47#ibcon#flushed, iclass 10, count 2 2006.285.09:36:55.47#ibcon#about to write, iclass 10, count 2 2006.285.09:36:55.47#ibcon#wrote, iclass 10, count 2 2006.285.09:36:55.47#ibcon#about to read 3, iclass 10, count 2 2006.285.09:36:55.49#ibcon#read 3, iclass 10, count 2 2006.285.09:36:55.49#ibcon#about to read 4, iclass 10, count 2 2006.285.09:36:55.49#ibcon#read 4, iclass 10, count 2 2006.285.09:36:55.49#ibcon#about to read 5, iclass 10, count 2 2006.285.09:36:55.49#ibcon#read 5, iclass 10, count 2 2006.285.09:36:55.49#ibcon#about to read 6, iclass 10, count 2 2006.285.09:36:55.49#ibcon#read 6, iclass 10, count 2 2006.285.09:36:55.49#ibcon#end of sib2, iclass 10, count 2 2006.285.09:36:55.49#ibcon#*mode == 0, iclass 10, count 2 2006.285.09:36:55.49#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.09:36:55.49#ibcon#[25=AT02-06\r\n] 2006.285.09:36:55.49#ibcon#*before write, iclass 10, count 2 2006.285.09:36:55.49#ibcon#enter sib2, iclass 10, count 2 2006.285.09:36:55.49#ibcon#flushed, iclass 10, count 2 2006.285.09:36:55.49#ibcon#about to write, iclass 10, count 2 2006.285.09:36:55.49#ibcon#wrote, iclass 10, count 2 2006.285.09:36:55.49#ibcon#about to read 3, iclass 10, count 2 2006.285.09:36:55.52#ibcon#read 3, iclass 10, count 2 2006.285.09:36:55.52#ibcon#about to read 4, iclass 10, count 2 2006.285.09:36:55.52#ibcon#read 4, iclass 10, count 2 2006.285.09:36:55.52#ibcon#about to read 5, iclass 10, count 2 2006.285.09:36:55.52#ibcon#read 5, iclass 10, count 2 2006.285.09:36:55.52#ibcon#about to read 6, iclass 10, count 2 2006.285.09:36:55.52#ibcon#read 6, iclass 10, count 2 2006.285.09:36:55.52#ibcon#end of sib2, iclass 10, count 2 2006.285.09:36:55.52#ibcon#*after write, iclass 10, count 2 2006.285.09:36:55.52#ibcon#*before return 0, iclass 10, count 2 2006.285.09:36:55.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:36:55.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:36:55.52#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.09:36:55.52#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:55.52#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:36:55.64#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:36:55.64#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:36:55.64#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:36:55.64#ibcon#first serial, iclass 10, count 0 2006.285.09:36:55.64#ibcon#enter sib2, iclass 10, count 0 2006.285.09:36:55.64#ibcon#flushed, iclass 10, count 0 2006.285.09:36:55.64#ibcon#about to write, iclass 10, count 0 2006.285.09:36:55.64#ibcon#wrote, iclass 10, count 0 2006.285.09:36:55.64#ibcon#about to read 3, iclass 10, count 0 2006.285.09:36:55.66#ibcon#read 3, iclass 10, count 0 2006.285.09:36:55.66#ibcon#about to read 4, iclass 10, count 0 2006.285.09:36:55.66#ibcon#read 4, iclass 10, count 0 2006.285.09:36:55.66#ibcon#about to read 5, iclass 10, count 0 2006.285.09:36:55.66#ibcon#read 5, iclass 10, count 0 2006.285.09:36:55.66#ibcon#about to read 6, iclass 10, count 0 2006.285.09:36:55.66#ibcon#read 6, iclass 10, count 0 2006.285.09:36:55.66#ibcon#end of sib2, iclass 10, count 0 2006.285.09:36:55.66#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:36:55.66#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:36:55.66#ibcon#[25=USB\r\n] 2006.285.09:36:55.66#ibcon#*before write, iclass 10, count 0 2006.285.09:36:55.66#ibcon#enter sib2, iclass 10, count 0 2006.285.09:36:55.66#ibcon#flushed, iclass 10, count 0 2006.285.09:36:55.66#ibcon#about to write, iclass 10, count 0 2006.285.09:36:55.66#ibcon#wrote, iclass 10, count 0 2006.285.09:36:55.66#ibcon#about to read 3, iclass 10, count 0 2006.285.09:36:55.69#ibcon#read 3, iclass 10, count 0 2006.285.09:36:55.69#ibcon#about to read 4, iclass 10, count 0 2006.285.09:36:55.69#ibcon#read 4, iclass 10, count 0 2006.285.09:36:55.69#ibcon#about to read 5, iclass 10, count 0 2006.285.09:36:55.69#ibcon#read 5, iclass 10, count 0 2006.285.09:36:55.69#ibcon#about to read 6, iclass 10, count 0 2006.285.09:36:55.69#ibcon#read 6, iclass 10, count 0 2006.285.09:36:55.69#ibcon#end of sib2, iclass 10, count 0 2006.285.09:36:55.69#ibcon#*after write, iclass 10, count 0 2006.285.09:36:55.69#ibcon#*before return 0, iclass 10, count 0 2006.285.09:36:55.69#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:36:55.69#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:36:55.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:36:55.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:36:55.69$vck44/valo=3,564.99 2006.285.09:36:55.69#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.09:36:55.69#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.09:36:55.69#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:55.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:36:55.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:36:55.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:36:55.69#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:36:55.69#ibcon#first serial, iclass 12, count 0 2006.285.09:36:55.69#ibcon#enter sib2, iclass 12, count 0 2006.285.09:36:55.69#ibcon#flushed, iclass 12, count 0 2006.285.09:36:55.69#ibcon#about to write, iclass 12, count 0 2006.285.09:36:55.69#ibcon#wrote, iclass 12, count 0 2006.285.09:36:55.69#ibcon#about to read 3, iclass 12, count 0 2006.285.09:36:55.71#ibcon#read 3, iclass 12, count 0 2006.285.09:36:55.71#ibcon#about to read 4, iclass 12, count 0 2006.285.09:36:55.71#ibcon#read 4, iclass 12, count 0 2006.285.09:36:55.71#ibcon#about to read 5, iclass 12, count 0 2006.285.09:36:55.71#ibcon#read 5, iclass 12, count 0 2006.285.09:36:55.71#ibcon#about to read 6, iclass 12, count 0 2006.285.09:36:55.71#ibcon#read 6, iclass 12, count 0 2006.285.09:36:55.71#ibcon#end of sib2, iclass 12, count 0 2006.285.09:36:55.71#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:36:55.71#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:36:55.71#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:36:55.71#ibcon#*before write, iclass 12, count 0 2006.285.09:36:55.71#ibcon#enter sib2, iclass 12, count 0 2006.285.09:36:55.71#ibcon#flushed, iclass 12, count 0 2006.285.09:36:55.71#ibcon#about to write, iclass 12, count 0 2006.285.09:36:55.71#ibcon#wrote, iclass 12, count 0 2006.285.09:36:55.71#ibcon#about to read 3, iclass 12, count 0 2006.285.09:36:55.75#ibcon#read 3, iclass 12, count 0 2006.285.09:36:55.75#ibcon#about to read 4, iclass 12, count 0 2006.285.09:36:55.75#ibcon#read 4, iclass 12, count 0 2006.285.09:36:55.75#ibcon#about to read 5, iclass 12, count 0 2006.285.09:36:55.75#ibcon#read 5, iclass 12, count 0 2006.285.09:36:55.75#ibcon#about to read 6, iclass 12, count 0 2006.285.09:36:55.75#ibcon#read 6, iclass 12, count 0 2006.285.09:36:55.75#ibcon#end of sib2, iclass 12, count 0 2006.285.09:36:55.75#ibcon#*after write, iclass 12, count 0 2006.285.09:36:55.75#ibcon#*before return 0, iclass 12, count 0 2006.285.09:36:55.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:36:55.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:36:55.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:36:55.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:36:55.75$vck44/va=3,7 2006.285.09:36:55.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.09:36:55.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.09:36:55.75#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:55.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:36:55.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:36:55.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:36:55.81#ibcon#enter wrdev, iclass 14, count 2 2006.285.09:36:55.81#ibcon#first serial, iclass 14, count 2 2006.285.09:36:55.81#ibcon#enter sib2, iclass 14, count 2 2006.285.09:36:55.81#ibcon#flushed, iclass 14, count 2 2006.285.09:36:55.81#ibcon#about to write, iclass 14, count 2 2006.285.09:36:55.81#ibcon#wrote, iclass 14, count 2 2006.285.09:36:55.81#ibcon#about to read 3, iclass 14, count 2 2006.285.09:36:55.83#ibcon#read 3, iclass 14, count 2 2006.285.09:36:55.83#ibcon#about to read 4, iclass 14, count 2 2006.285.09:36:55.83#ibcon#read 4, iclass 14, count 2 2006.285.09:36:55.83#ibcon#about to read 5, iclass 14, count 2 2006.285.09:36:55.83#ibcon#read 5, iclass 14, count 2 2006.285.09:36:55.83#ibcon#about to read 6, iclass 14, count 2 2006.285.09:36:55.83#ibcon#read 6, iclass 14, count 2 2006.285.09:36:55.83#ibcon#end of sib2, iclass 14, count 2 2006.285.09:36:55.83#ibcon#*mode == 0, iclass 14, count 2 2006.285.09:36:55.83#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.09:36:55.83#ibcon#[25=AT03-07\r\n] 2006.285.09:36:55.83#ibcon#*before write, iclass 14, count 2 2006.285.09:36:55.83#ibcon#enter sib2, iclass 14, count 2 2006.285.09:36:55.83#ibcon#flushed, iclass 14, count 2 2006.285.09:36:55.83#ibcon#about to write, iclass 14, count 2 2006.285.09:36:55.83#ibcon#wrote, iclass 14, count 2 2006.285.09:36:55.83#ibcon#about to read 3, iclass 14, count 2 2006.285.09:36:55.86#ibcon#read 3, iclass 14, count 2 2006.285.09:36:55.86#ibcon#about to read 4, iclass 14, count 2 2006.285.09:36:55.86#ibcon#read 4, iclass 14, count 2 2006.285.09:36:55.86#ibcon#about to read 5, iclass 14, count 2 2006.285.09:36:55.86#ibcon#read 5, iclass 14, count 2 2006.285.09:36:55.86#ibcon#about to read 6, iclass 14, count 2 2006.285.09:36:55.86#ibcon#read 6, iclass 14, count 2 2006.285.09:36:55.86#ibcon#end of sib2, iclass 14, count 2 2006.285.09:36:55.86#ibcon#*after write, iclass 14, count 2 2006.285.09:36:55.86#ibcon#*before return 0, iclass 14, count 2 2006.285.09:36:55.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:36:55.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:36:55.86#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.09:36:55.86#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:55.86#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:36:55.98#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:36:55.98#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:36:55.98#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:36:55.98#ibcon#first serial, iclass 14, count 0 2006.285.09:36:55.98#ibcon#enter sib2, iclass 14, count 0 2006.285.09:36:55.98#ibcon#flushed, iclass 14, count 0 2006.285.09:36:55.98#ibcon#about to write, iclass 14, count 0 2006.285.09:36:55.98#ibcon#wrote, iclass 14, count 0 2006.285.09:36:55.98#ibcon#about to read 3, iclass 14, count 0 2006.285.09:36:56.00#ibcon#read 3, iclass 14, count 0 2006.285.09:36:56.00#ibcon#about to read 4, iclass 14, count 0 2006.285.09:36:56.00#ibcon#read 4, iclass 14, count 0 2006.285.09:36:56.00#ibcon#about to read 5, iclass 14, count 0 2006.285.09:36:56.00#ibcon#read 5, iclass 14, count 0 2006.285.09:36:56.00#ibcon#about to read 6, iclass 14, count 0 2006.285.09:36:56.00#ibcon#read 6, iclass 14, count 0 2006.285.09:36:56.00#ibcon#end of sib2, iclass 14, count 0 2006.285.09:36:56.00#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:36:56.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:36:56.00#ibcon#[25=USB\r\n] 2006.285.09:36:56.00#ibcon#*before write, iclass 14, count 0 2006.285.09:36:56.00#ibcon#enter sib2, iclass 14, count 0 2006.285.09:36:56.00#ibcon#flushed, iclass 14, count 0 2006.285.09:36:56.00#ibcon#about to write, iclass 14, count 0 2006.285.09:36:56.00#ibcon#wrote, iclass 14, count 0 2006.285.09:36:56.00#ibcon#about to read 3, iclass 14, count 0 2006.285.09:36:56.03#ibcon#read 3, iclass 14, count 0 2006.285.09:36:56.03#ibcon#about to read 4, iclass 14, count 0 2006.285.09:36:56.03#ibcon#read 4, iclass 14, count 0 2006.285.09:36:56.03#ibcon#about to read 5, iclass 14, count 0 2006.285.09:36:56.03#ibcon#read 5, iclass 14, count 0 2006.285.09:36:56.03#ibcon#about to read 6, iclass 14, count 0 2006.285.09:36:56.03#ibcon#read 6, iclass 14, count 0 2006.285.09:36:56.03#ibcon#end of sib2, iclass 14, count 0 2006.285.09:36:56.03#ibcon#*after write, iclass 14, count 0 2006.285.09:36:56.03#ibcon#*before return 0, iclass 14, count 0 2006.285.09:36:56.03#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:36:56.03#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:36:56.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:36:56.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:36:56.03$vck44/valo=4,624.99 2006.285.09:36:56.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.09:36:56.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.09:36:56.03#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:56.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:36:56.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:36:56.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:36:56.03#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:36:56.03#ibcon#first serial, iclass 16, count 0 2006.285.09:36:56.03#ibcon#enter sib2, iclass 16, count 0 2006.285.09:36:56.03#ibcon#flushed, iclass 16, count 0 2006.285.09:36:56.03#ibcon#about to write, iclass 16, count 0 2006.285.09:36:56.03#ibcon#wrote, iclass 16, count 0 2006.285.09:36:56.03#ibcon#about to read 3, iclass 16, count 0 2006.285.09:36:56.05#ibcon#read 3, iclass 16, count 0 2006.285.09:36:56.05#ibcon#about to read 4, iclass 16, count 0 2006.285.09:36:56.05#ibcon#read 4, iclass 16, count 0 2006.285.09:36:56.05#ibcon#about to read 5, iclass 16, count 0 2006.285.09:36:56.05#ibcon#read 5, iclass 16, count 0 2006.285.09:36:56.05#ibcon#about to read 6, iclass 16, count 0 2006.285.09:36:56.05#ibcon#read 6, iclass 16, count 0 2006.285.09:36:56.05#ibcon#end of sib2, iclass 16, count 0 2006.285.09:36:56.05#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:36:56.05#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:36:56.05#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:36:56.05#ibcon#*before write, iclass 16, count 0 2006.285.09:36:56.05#ibcon#enter sib2, iclass 16, count 0 2006.285.09:36:56.05#ibcon#flushed, iclass 16, count 0 2006.285.09:36:56.05#ibcon#about to write, iclass 16, count 0 2006.285.09:36:56.05#ibcon#wrote, iclass 16, count 0 2006.285.09:36:56.05#ibcon#about to read 3, iclass 16, count 0 2006.285.09:36:56.09#ibcon#read 3, iclass 16, count 0 2006.285.09:36:56.09#ibcon#about to read 4, iclass 16, count 0 2006.285.09:36:56.09#ibcon#read 4, iclass 16, count 0 2006.285.09:36:56.09#ibcon#about to read 5, iclass 16, count 0 2006.285.09:36:56.09#ibcon#read 5, iclass 16, count 0 2006.285.09:36:56.09#ibcon#about to read 6, iclass 16, count 0 2006.285.09:36:56.09#ibcon#read 6, iclass 16, count 0 2006.285.09:36:56.09#ibcon#end of sib2, iclass 16, count 0 2006.285.09:36:56.09#ibcon#*after write, iclass 16, count 0 2006.285.09:36:56.09#ibcon#*before return 0, iclass 16, count 0 2006.285.09:36:56.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:36:56.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:36:56.09#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:36:56.09#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:36:56.09$vck44/va=4,6 2006.285.09:36:56.09#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.09:36:56.09#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.09:36:56.09#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:56.09#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:36:56.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:36:56.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:36:56.15#ibcon#enter wrdev, iclass 18, count 2 2006.285.09:36:56.15#ibcon#first serial, iclass 18, count 2 2006.285.09:36:56.15#ibcon#enter sib2, iclass 18, count 2 2006.285.09:36:56.15#ibcon#flushed, iclass 18, count 2 2006.285.09:36:56.15#ibcon#about to write, iclass 18, count 2 2006.285.09:36:56.15#ibcon#wrote, iclass 18, count 2 2006.285.09:36:56.15#ibcon#about to read 3, iclass 18, count 2 2006.285.09:36:56.17#ibcon#read 3, iclass 18, count 2 2006.285.09:36:56.17#ibcon#about to read 4, iclass 18, count 2 2006.285.09:36:56.17#ibcon#read 4, iclass 18, count 2 2006.285.09:36:56.17#ibcon#about to read 5, iclass 18, count 2 2006.285.09:36:56.17#ibcon#read 5, iclass 18, count 2 2006.285.09:36:56.17#ibcon#about to read 6, iclass 18, count 2 2006.285.09:36:56.17#ibcon#read 6, iclass 18, count 2 2006.285.09:36:56.17#ibcon#end of sib2, iclass 18, count 2 2006.285.09:36:56.17#ibcon#*mode == 0, iclass 18, count 2 2006.285.09:36:56.17#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.09:36:56.17#ibcon#[25=AT04-06\r\n] 2006.285.09:36:56.17#ibcon#*before write, iclass 18, count 2 2006.285.09:36:56.17#ibcon#enter sib2, iclass 18, count 2 2006.285.09:36:56.17#ibcon#flushed, iclass 18, count 2 2006.285.09:36:56.17#ibcon#about to write, iclass 18, count 2 2006.285.09:36:56.17#ibcon#wrote, iclass 18, count 2 2006.285.09:36:56.17#ibcon#about to read 3, iclass 18, count 2 2006.285.09:36:56.20#ibcon#read 3, iclass 18, count 2 2006.285.09:36:56.20#ibcon#about to read 4, iclass 18, count 2 2006.285.09:36:56.20#ibcon#read 4, iclass 18, count 2 2006.285.09:36:56.20#ibcon#about to read 5, iclass 18, count 2 2006.285.09:36:56.20#ibcon#read 5, iclass 18, count 2 2006.285.09:36:56.20#ibcon#about to read 6, iclass 18, count 2 2006.285.09:36:56.20#ibcon#read 6, iclass 18, count 2 2006.285.09:36:56.20#ibcon#end of sib2, iclass 18, count 2 2006.285.09:36:56.20#ibcon#*after write, iclass 18, count 2 2006.285.09:36:56.20#ibcon#*before return 0, iclass 18, count 2 2006.285.09:36:56.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:36:56.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:36:56.20#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.09:36:56.20#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:56.20#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:36:56.32#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:36:56.32#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:36:56.32#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:36:56.32#ibcon#first serial, iclass 18, count 0 2006.285.09:36:56.32#ibcon#enter sib2, iclass 18, count 0 2006.285.09:36:56.32#ibcon#flushed, iclass 18, count 0 2006.285.09:36:56.32#ibcon#about to write, iclass 18, count 0 2006.285.09:36:56.32#ibcon#wrote, iclass 18, count 0 2006.285.09:36:56.32#ibcon#about to read 3, iclass 18, count 0 2006.285.09:36:56.34#ibcon#read 3, iclass 18, count 0 2006.285.09:36:56.34#ibcon#about to read 4, iclass 18, count 0 2006.285.09:36:56.34#ibcon#read 4, iclass 18, count 0 2006.285.09:36:56.34#ibcon#about to read 5, iclass 18, count 0 2006.285.09:36:56.34#ibcon#read 5, iclass 18, count 0 2006.285.09:36:56.34#ibcon#about to read 6, iclass 18, count 0 2006.285.09:36:56.34#ibcon#read 6, iclass 18, count 0 2006.285.09:36:56.34#ibcon#end of sib2, iclass 18, count 0 2006.285.09:36:56.34#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:36:56.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:36:56.34#ibcon#[25=USB\r\n] 2006.285.09:36:56.34#ibcon#*before write, iclass 18, count 0 2006.285.09:36:56.34#ibcon#enter sib2, iclass 18, count 0 2006.285.09:36:56.34#ibcon#flushed, iclass 18, count 0 2006.285.09:36:56.34#ibcon#about to write, iclass 18, count 0 2006.285.09:36:56.34#ibcon#wrote, iclass 18, count 0 2006.285.09:36:56.34#ibcon#about to read 3, iclass 18, count 0 2006.285.09:36:56.37#ibcon#read 3, iclass 18, count 0 2006.285.09:36:56.37#ibcon#about to read 4, iclass 18, count 0 2006.285.09:36:56.37#ibcon#read 4, iclass 18, count 0 2006.285.09:36:56.37#ibcon#about to read 5, iclass 18, count 0 2006.285.09:36:56.37#ibcon#read 5, iclass 18, count 0 2006.285.09:36:56.37#ibcon#about to read 6, iclass 18, count 0 2006.285.09:36:56.37#ibcon#read 6, iclass 18, count 0 2006.285.09:36:56.37#ibcon#end of sib2, iclass 18, count 0 2006.285.09:36:56.37#ibcon#*after write, iclass 18, count 0 2006.285.09:36:56.37#ibcon#*before return 0, iclass 18, count 0 2006.285.09:36:56.37#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:36:56.37#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:36:56.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:36:56.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:36:56.37$vck44/valo=5,734.99 2006.285.09:36:56.37#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.09:36:56.37#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.09:36:56.37#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:56.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:36:56.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:36:56.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:36:56.37#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:36:56.37#ibcon#first serial, iclass 20, count 0 2006.285.09:36:56.37#ibcon#enter sib2, iclass 20, count 0 2006.285.09:36:56.37#ibcon#flushed, iclass 20, count 0 2006.285.09:36:56.37#ibcon#about to write, iclass 20, count 0 2006.285.09:36:56.37#ibcon#wrote, iclass 20, count 0 2006.285.09:36:56.37#ibcon#about to read 3, iclass 20, count 0 2006.285.09:36:56.39#ibcon#read 3, iclass 20, count 0 2006.285.09:36:56.39#ibcon#about to read 4, iclass 20, count 0 2006.285.09:36:56.39#ibcon#read 4, iclass 20, count 0 2006.285.09:36:56.39#ibcon#about to read 5, iclass 20, count 0 2006.285.09:36:56.39#ibcon#read 5, iclass 20, count 0 2006.285.09:36:56.39#ibcon#about to read 6, iclass 20, count 0 2006.285.09:36:56.39#ibcon#read 6, iclass 20, count 0 2006.285.09:36:56.39#ibcon#end of sib2, iclass 20, count 0 2006.285.09:36:56.39#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:36:56.39#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:36:56.39#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:36:56.39#ibcon#*before write, iclass 20, count 0 2006.285.09:36:56.39#ibcon#enter sib2, iclass 20, count 0 2006.285.09:36:56.39#ibcon#flushed, iclass 20, count 0 2006.285.09:36:56.39#ibcon#about to write, iclass 20, count 0 2006.285.09:36:56.39#ibcon#wrote, iclass 20, count 0 2006.285.09:36:56.39#ibcon#about to read 3, iclass 20, count 0 2006.285.09:36:56.43#ibcon#read 3, iclass 20, count 0 2006.285.09:36:56.43#ibcon#about to read 4, iclass 20, count 0 2006.285.09:36:56.43#ibcon#read 4, iclass 20, count 0 2006.285.09:36:56.43#ibcon#about to read 5, iclass 20, count 0 2006.285.09:36:56.43#ibcon#read 5, iclass 20, count 0 2006.285.09:36:56.43#ibcon#about to read 6, iclass 20, count 0 2006.285.09:36:56.43#ibcon#read 6, iclass 20, count 0 2006.285.09:36:56.43#ibcon#end of sib2, iclass 20, count 0 2006.285.09:36:56.43#ibcon#*after write, iclass 20, count 0 2006.285.09:36:56.43#ibcon#*before return 0, iclass 20, count 0 2006.285.09:36:56.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:36:56.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:36:56.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:36:56.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:36:56.43$vck44/va=5,3 2006.285.09:36:56.43#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.09:36:56.43#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.09:36:56.43#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:56.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:36:56.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:36:56.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:36:56.49#ibcon#enter wrdev, iclass 22, count 2 2006.285.09:36:56.49#ibcon#first serial, iclass 22, count 2 2006.285.09:36:56.49#ibcon#enter sib2, iclass 22, count 2 2006.285.09:36:56.49#ibcon#flushed, iclass 22, count 2 2006.285.09:36:56.49#ibcon#about to write, iclass 22, count 2 2006.285.09:36:56.49#ibcon#wrote, iclass 22, count 2 2006.285.09:36:56.49#ibcon#about to read 3, iclass 22, count 2 2006.285.09:36:56.51#ibcon#read 3, iclass 22, count 2 2006.285.09:36:56.51#ibcon#about to read 4, iclass 22, count 2 2006.285.09:36:56.51#ibcon#read 4, iclass 22, count 2 2006.285.09:36:56.51#ibcon#about to read 5, iclass 22, count 2 2006.285.09:36:56.51#ibcon#read 5, iclass 22, count 2 2006.285.09:36:56.51#ibcon#about to read 6, iclass 22, count 2 2006.285.09:36:56.51#ibcon#read 6, iclass 22, count 2 2006.285.09:36:56.51#ibcon#end of sib2, iclass 22, count 2 2006.285.09:36:56.51#ibcon#*mode == 0, iclass 22, count 2 2006.285.09:36:56.51#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.09:36:56.51#ibcon#[25=AT05-03\r\n] 2006.285.09:36:56.51#ibcon#*before write, iclass 22, count 2 2006.285.09:36:56.51#ibcon#enter sib2, iclass 22, count 2 2006.285.09:36:56.51#ibcon#flushed, iclass 22, count 2 2006.285.09:36:56.51#ibcon#about to write, iclass 22, count 2 2006.285.09:36:56.51#ibcon#wrote, iclass 22, count 2 2006.285.09:36:56.51#ibcon#about to read 3, iclass 22, count 2 2006.285.09:36:56.54#ibcon#read 3, iclass 22, count 2 2006.285.09:36:56.54#ibcon#about to read 4, iclass 22, count 2 2006.285.09:36:56.54#ibcon#read 4, iclass 22, count 2 2006.285.09:36:56.54#ibcon#about to read 5, iclass 22, count 2 2006.285.09:36:56.54#ibcon#read 5, iclass 22, count 2 2006.285.09:36:56.54#ibcon#about to read 6, iclass 22, count 2 2006.285.09:36:56.54#ibcon#read 6, iclass 22, count 2 2006.285.09:36:56.54#ibcon#end of sib2, iclass 22, count 2 2006.285.09:36:56.54#ibcon#*after write, iclass 22, count 2 2006.285.09:36:56.54#ibcon#*before return 0, iclass 22, count 2 2006.285.09:36:56.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:36:56.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:36:56.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.09:36:56.54#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:56.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:36:56.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:36:56.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:36:56.66#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:36:56.66#ibcon#first serial, iclass 22, count 0 2006.285.09:36:56.66#ibcon#enter sib2, iclass 22, count 0 2006.285.09:36:56.66#ibcon#flushed, iclass 22, count 0 2006.285.09:36:56.66#ibcon#about to write, iclass 22, count 0 2006.285.09:36:56.66#ibcon#wrote, iclass 22, count 0 2006.285.09:36:56.66#ibcon#about to read 3, iclass 22, count 0 2006.285.09:36:56.68#ibcon#read 3, iclass 22, count 0 2006.285.09:36:56.68#ibcon#about to read 4, iclass 22, count 0 2006.285.09:36:56.68#ibcon#read 4, iclass 22, count 0 2006.285.09:36:56.68#ibcon#about to read 5, iclass 22, count 0 2006.285.09:36:56.68#ibcon#read 5, iclass 22, count 0 2006.285.09:36:56.68#ibcon#about to read 6, iclass 22, count 0 2006.285.09:36:56.68#ibcon#read 6, iclass 22, count 0 2006.285.09:36:56.68#ibcon#end of sib2, iclass 22, count 0 2006.285.09:36:56.68#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:36:56.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:36:56.68#ibcon#[25=USB\r\n] 2006.285.09:36:56.68#ibcon#*before write, iclass 22, count 0 2006.285.09:36:56.68#ibcon#enter sib2, iclass 22, count 0 2006.285.09:36:56.68#ibcon#flushed, iclass 22, count 0 2006.285.09:36:56.68#ibcon#about to write, iclass 22, count 0 2006.285.09:36:56.68#ibcon#wrote, iclass 22, count 0 2006.285.09:36:56.68#ibcon#about to read 3, iclass 22, count 0 2006.285.09:36:56.71#ibcon#read 3, iclass 22, count 0 2006.285.09:36:56.71#ibcon#about to read 4, iclass 22, count 0 2006.285.09:36:56.71#ibcon#read 4, iclass 22, count 0 2006.285.09:36:56.71#ibcon#about to read 5, iclass 22, count 0 2006.285.09:36:56.71#ibcon#read 5, iclass 22, count 0 2006.285.09:36:56.71#ibcon#about to read 6, iclass 22, count 0 2006.285.09:36:56.71#ibcon#read 6, iclass 22, count 0 2006.285.09:36:56.71#ibcon#end of sib2, iclass 22, count 0 2006.285.09:36:56.71#ibcon#*after write, iclass 22, count 0 2006.285.09:36:56.71#ibcon#*before return 0, iclass 22, count 0 2006.285.09:36:56.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:36:56.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:36:56.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:36:56.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:36:56.71$vck44/valo=6,814.99 2006.285.09:36:56.71#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.09:36:56.71#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.09:36:56.71#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:56.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:36:56.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:36:56.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:36:56.71#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:36:56.71#ibcon#first serial, iclass 24, count 0 2006.285.09:36:56.71#ibcon#enter sib2, iclass 24, count 0 2006.285.09:36:56.71#ibcon#flushed, iclass 24, count 0 2006.285.09:36:56.71#ibcon#about to write, iclass 24, count 0 2006.285.09:36:56.71#ibcon#wrote, iclass 24, count 0 2006.285.09:36:56.71#ibcon#about to read 3, iclass 24, count 0 2006.285.09:36:56.73#ibcon#read 3, iclass 24, count 0 2006.285.09:36:56.73#ibcon#about to read 4, iclass 24, count 0 2006.285.09:36:56.73#ibcon#read 4, iclass 24, count 0 2006.285.09:36:56.73#ibcon#about to read 5, iclass 24, count 0 2006.285.09:36:56.73#ibcon#read 5, iclass 24, count 0 2006.285.09:36:56.73#ibcon#about to read 6, iclass 24, count 0 2006.285.09:36:56.73#ibcon#read 6, iclass 24, count 0 2006.285.09:36:56.73#ibcon#end of sib2, iclass 24, count 0 2006.285.09:36:56.73#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:36:56.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:36:56.73#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:36:56.73#ibcon#*before write, iclass 24, count 0 2006.285.09:36:56.73#ibcon#enter sib2, iclass 24, count 0 2006.285.09:36:56.73#ibcon#flushed, iclass 24, count 0 2006.285.09:36:56.73#ibcon#about to write, iclass 24, count 0 2006.285.09:36:56.73#ibcon#wrote, iclass 24, count 0 2006.285.09:36:56.73#ibcon#about to read 3, iclass 24, count 0 2006.285.09:36:56.77#ibcon#read 3, iclass 24, count 0 2006.285.09:36:56.77#ibcon#about to read 4, iclass 24, count 0 2006.285.09:36:56.77#ibcon#read 4, iclass 24, count 0 2006.285.09:36:56.77#ibcon#about to read 5, iclass 24, count 0 2006.285.09:36:56.77#ibcon#read 5, iclass 24, count 0 2006.285.09:36:56.77#ibcon#about to read 6, iclass 24, count 0 2006.285.09:36:56.77#ibcon#read 6, iclass 24, count 0 2006.285.09:36:56.77#ibcon#end of sib2, iclass 24, count 0 2006.285.09:36:56.77#ibcon#*after write, iclass 24, count 0 2006.285.09:36:56.77#ibcon#*before return 0, iclass 24, count 0 2006.285.09:36:56.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:36:56.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:36:56.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:36:56.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:36:56.77$vck44/va=6,4 2006.285.09:36:56.77#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.09:36:56.77#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.09:36:56.77#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:56.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:36:56.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:36:56.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:36:56.83#ibcon#enter wrdev, iclass 26, count 2 2006.285.09:36:56.83#ibcon#first serial, iclass 26, count 2 2006.285.09:36:56.83#ibcon#enter sib2, iclass 26, count 2 2006.285.09:36:56.83#ibcon#flushed, iclass 26, count 2 2006.285.09:36:56.83#ibcon#about to write, iclass 26, count 2 2006.285.09:36:56.83#ibcon#wrote, iclass 26, count 2 2006.285.09:36:56.83#ibcon#about to read 3, iclass 26, count 2 2006.285.09:36:56.85#ibcon#read 3, iclass 26, count 2 2006.285.09:36:56.85#ibcon#about to read 4, iclass 26, count 2 2006.285.09:36:56.85#ibcon#read 4, iclass 26, count 2 2006.285.09:36:56.85#ibcon#about to read 5, iclass 26, count 2 2006.285.09:36:56.85#ibcon#read 5, iclass 26, count 2 2006.285.09:36:56.85#ibcon#about to read 6, iclass 26, count 2 2006.285.09:36:56.85#ibcon#read 6, iclass 26, count 2 2006.285.09:36:56.85#ibcon#end of sib2, iclass 26, count 2 2006.285.09:36:56.85#ibcon#*mode == 0, iclass 26, count 2 2006.285.09:36:56.85#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.09:36:56.85#ibcon#[25=AT06-04\r\n] 2006.285.09:36:56.85#ibcon#*before write, iclass 26, count 2 2006.285.09:36:56.85#ibcon#enter sib2, iclass 26, count 2 2006.285.09:36:56.85#ibcon#flushed, iclass 26, count 2 2006.285.09:36:56.85#ibcon#about to write, iclass 26, count 2 2006.285.09:36:56.85#ibcon#wrote, iclass 26, count 2 2006.285.09:36:56.85#ibcon#about to read 3, iclass 26, count 2 2006.285.09:36:56.88#ibcon#read 3, iclass 26, count 2 2006.285.09:36:56.88#ibcon#about to read 4, iclass 26, count 2 2006.285.09:36:56.88#ibcon#read 4, iclass 26, count 2 2006.285.09:36:56.88#ibcon#about to read 5, iclass 26, count 2 2006.285.09:36:56.88#ibcon#read 5, iclass 26, count 2 2006.285.09:36:56.88#ibcon#about to read 6, iclass 26, count 2 2006.285.09:36:56.88#ibcon#read 6, iclass 26, count 2 2006.285.09:36:56.88#ibcon#end of sib2, iclass 26, count 2 2006.285.09:36:56.88#ibcon#*after write, iclass 26, count 2 2006.285.09:36:56.88#ibcon#*before return 0, iclass 26, count 2 2006.285.09:36:56.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:36:56.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:36:56.88#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.09:36:56.88#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:56.88#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:36:57.00#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:36:57.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:36:57.00#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:36:57.00#ibcon#first serial, iclass 26, count 0 2006.285.09:36:57.00#ibcon#enter sib2, iclass 26, count 0 2006.285.09:36:57.00#ibcon#flushed, iclass 26, count 0 2006.285.09:36:57.00#ibcon#about to write, iclass 26, count 0 2006.285.09:36:57.00#ibcon#wrote, iclass 26, count 0 2006.285.09:36:57.00#ibcon#about to read 3, iclass 26, count 0 2006.285.09:36:57.02#ibcon#read 3, iclass 26, count 0 2006.285.09:36:57.02#ibcon#about to read 4, iclass 26, count 0 2006.285.09:36:57.02#ibcon#read 4, iclass 26, count 0 2006.285.09:36:57.02#ibcon#about to read 5, iclass 26, count 0 2006.285.09:36:57.02#ibcon#read 5, iclass 26, count 0 2006.285.09:36:57.02#ibcon#about to read 6, iclass 26, count 0 2006.285.09:36:57.02#ibcon#read 6, iclass 26, count 0 2006.285.09:36:57.02#ibcon#end of sib2, iclass 26, count 0 2006.285.09:36:57.02#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:36:57.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:36:57.02#ibcon#[25=USB\r\n] 2006.285.09:36:57.02#ibcon#*before write, iclass 26, count 0 2006.285.09:36:57.02#ibcon#enter sib2, iclass 26, count 0 2006.285.09:36:57.02#ibcon#flushed, iclass 26, count 0 2006.285.09:36:57.02#ibcon#about to write, iclass 26, count 0 2006.285.09:36:57.02#ibcon#wrote, iclass 26, count 0 2006.285.09:36:57.02#ibcon#about to read 3, iclass 26, count 0 2006.285.09:36:57.05#ibcon#read 3, iclass 26, count 0 2006.285.09:36:57.05#ibcon#about to read 4, iclass 26, count 0 2006.285.09:36:57.05#ibcon#read 4, iclass 26, count 0 2006.285.09:36:57.05#ibcon#about to read 5, iclass 26, count 0 2006.285.09:36:57.05#ibcon#read 5, iclass 26, count 0 2006.285.09:36:57.05#ibcon#about to read 6, iclass 26, count 0 2006.285.09:36:57.05#ibcon#read 6, iclass 26, count 0 2006.285.09:36:57.05#ibcon#end of sib2, iclass 26, count 0 2006.285.09:36:57.05#ibcon#*after write, iclass 26, count 0 2006.285.09:36:57.05#ibcon#*before return 0, iclass 26, count 0 2006.285.09:36:57.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:36:57.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:36:57.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:36:57.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:36:57.05$vck44/valo=7,864.99 2006.285.09:36:57.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.09:36:57.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.09:36:57.05#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:57.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:36:57.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:36:57.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:36:57.05#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:36:57.05#ibcon#first serial, iclass 28, count 0 2006.285.09:36:57.05#ibcon#enter sib2, iclass 28, count 0 2006.285.09:36:57.05#ibcon#flushed, iclass 28, count 0 2006.285.09:36:57.05#ibcon#about to write, iclass 28, count 0 2006.285.09:36:57.05#ibcon#wrote, iclass 28, count 0 2006.285.09:36:57.05#ibcon#about to read 3, iclass 28, count 0 2006.285.09:36:57.07#ibcon#read 3, iclass 28, count 0 2006.285.09:36:57.07#ibcon#about to read 4, iclass 28, count 0 2006.285.09:36:57.07#ibcon#read 4, iclass 28, count 0 2006.285.09:36:57.07#ibcon#about to read 5, iclass 28, count 0 2006.285.09:36:57.07#ibcon#read 5, iclass 28, count 0 2006.285.09:36:57.07#ibcon#about to read 6, iclass 28, count 0 2006.285.09:36:57.07#ibcon#read 6, iclass 28, count 0 2006.285.09:36:57.07#ibcon#end of sib2, iclass 28, count 0 2006.285.09:36:57.07#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:36:57.07#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:36:57.07#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:36:57.07#ibcon#*before write, iclass 28, count 0 2006.285.09:36:57.07#ibcon#enter sib2, iclass 28, count 0 2006.285.09:36:57.07#ibcon#flushed, iclass 28, count 0 2006.285.09:36:57.07#ibcon#about to write, iclass 28, count 0 2006.285.09:36:57.07#ibcon#wrote, iclass 28, count 0 2006.285.09:36:57.07#ibcon#about to read 3, iclass 28, count 0 2006.285.09:36:57.11#ibcon#read 3, iclass 28, count 0 2006.285.09:36:57.11#ibcon#about to read 4, iclass 28, count 0 2006.285.09:36:57.11#ibcon#read 4, iclass 28, count 0 2006.285.09:36:57.11#ibcon#about to read 5, iclass 28, count 0 2006.285.09:36:57.11#ibcon#read 5, iclass 28, count 0 2006.285.09:36:57.11#ibcon#about to read 6, iclass 28, count 0 2006.285.09:36:57.11#ibcon#read 6, iclass 28, count 0 2006.285.09:36:57.11#ibcon#end of sib2, iclass 28, count 0 2006.285.09:36:57.11#ibcon#*after write, iclass 28, count 0 2006.285.09:36:57.11#ibcon#*before return 0, iclass 28, count 0 2006.285.09:36:57.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:36:57.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:36:57.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:36:57.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:36:57.11$vck44/va=7,4 2006.285.09:36:57.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.09:36:57.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.09:36:57.11#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:57.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:36:57.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:36:57.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:36:57.17#ibcon#enter wrdev, iclass 30, count 2 2006.285.09:36:57.17#ibcon#first serial, iclass 30, count 2 2006.285.09:36:57.17#ibcon#enter sib2, iclass 30, count 2 2006.285.09:36:57.17#ibcon#flushed, iclass 30, count 2 2006.285.09:36:57.17#ibcon#about to write, iclass 30, count 2 2006.285.09:36:57.17#ibcon#wrote, iclass 30, count 2 2006.285.09:36:57.17#ibcon#about to read 3, iclass 30, count 2 2006.285.09:36:57.19#ibcon#read 3, iclass 30, count 2 2006.285.09:36:57.19#ibcon#about to read 4, iclass 30, count 2 2006.285.09:36:57.19#ibcon#read 4, iclass 30, count 2 2006.285.09:36:57.19#ibcon#about to read 5, iclass 30, count 2 2006.285.09:36:57.19#ibcon#read 5, iclass 30, count 2 2006.285.09:36:57.19#ibcon#about to read 6, iclass 30, count 2 2006.285.09:36:57.19#ibcon#read 6, iclass 30, count 2 2006.285.09:36:57.19#ibcon#end of sib2, iclass 30, count 2 2006.285.09:36:57.19#ibcon#*mode == 0, iclass 30, count 2 2006.285.09:36:57.19#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.09:36:57.19#ibcon#[25=AT07-04\r\n] 2006.285.09:36:57.19#ibcon#*before write, iclass 30, count 2 2006.285.09:36:57.19#ibcon#enter sib2, iclass 30, count 2 2006.285.09:36:57.19#ibcon#flushed, iclass 30, count 2 2006.285.09:36:57.19#ibcon#about to write, iclass 30, count 2 2006.285.09:36:57.19#ibcon#wrote, iclass 30, count 2 2006.285.09:36:57.19#ibcon#about to read 3, iclass 30, count 2 2006.285.09:36:57.22#ibcon#read 3, iclass 30, count 2 2006.285.09:36:57.22#ibcon#about to read 4, iclass 30, count 2 2006.285.09:36:57.22#ibcon#read 4, iclass 30, count 2 2006.285.09:36:57.22#ibcon#about to read 5, iclass 30, count 2 2006.285.09:36:57.22#ibcon#read 5, iclass 30, count 2 2006.285.09:36:57.22#ibcon#about to read 6, iclass 30, count 2 2006.285.09:36:57.22#ibcon#read 6, iclass 30, count 2 2006.285.09:36:57.22#ibcon#end of sib2, iclass 30, count 2 2006.285.09:36:57.22#ibcon#*after write, iclass 30, count 2 2006.285.09:36:57.22#ibcon#*before return 0, iclass 30, count 2 2006.285.09:36:57.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:36:57.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:36:57.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.09:36:57.22#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:57.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:36:57.34#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:36:57.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:36:57.34#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:36:57.34#ibcon#first serial, iclass 30, count 0 2006.285.09:36:57.34#ibcon#enter sib2, iclass 30, count 0 2006.285.09:36:57.34#ibcon#flushed, iclass 30, count 0 2006.285.09:36:57.34#ibcon#about to write, iclass 30, count 0 2006.285.09:36:57.34#ibcon#wrote, iclass 30, count 0 2006.285.09:36:57.34#ibcon#about to read 3, iclass 30, count 0 2006.285.09:36:57.36#ibcon#read 3, iclass 30, count 0 2006.285.09:36:57.36#ibcon#about to read 4, iclass 30, count 0 2006.285.09:36:57.36#ibcon#read 4, iclass 30, count 0 2006.285.09:36:57.36#ibcon#about to read 5, iclass 30, count 0 2006.285.09:36:57.36#ibcon#read 5, iclass 30, count 0 2006.285.09:36:57.36#ibcon#about to read 6, iclass 30, count 0 2006.285.09:36:57.36#ibcon#read 6, iclass 30, count 0 2006.285.09:36:57.36#ibcon#end of sib2, iclass 30, count 0 2006.285.09:36:57.36#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:36:57.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:36:57.36#ibcon#[25=USB\r\n] 2006.285.09:36:57.36#ibcon#*before write, iclass 30, count 0 2006.285.09:36:57.36#ibcon#enter sib2, iclass 30, count 0 2006.285.09:36:57.36#ibcon#flushed, iclass 30, count 0 2006.285.09:36:57.36#ibcon#about to write, iclass 30, count 0 2006.285.09:36:57.36#ibcon#wrote, iclass 30, count 0 2006.285.09:36:57.36#ibcon#about to read 3, iclass 30, count 0 2006.285.09:36:57.39#ibcon#read 3, iclass 30, count 0 2006.285.09:36:57.39#ibcon#about to read 4, iclass 30, count 0 2006.285.09:36:57.39#ibcon#read 4, iclass 30, count 0 2006.285.09:36:57.39#ibcon#about to read 5, iclass 30, count 0 2006.285.09:36:57.39#ibcon#read 5, iclass 30, count 0 2006.285.09:36:57.39#ibcon#about to read 6, iclass 30, count 0 2006.285.09:36:57.39#ibcon#read 6, iclass 30, count 0 2006.285.09:36:57.39#ibcon#end of sib2, iclass 30, count 0 2006.285.09:36:57.39#ibcon#*after write, iclass 30, count 0 2006.285.09:36:57.39#ibcon#*before return 0, iclass 30, count 0 2006.285.09:36:57.39#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:36:57.39#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:36:57.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:36:57.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:36:57.39$vck44/valo=8,884.99 2006.285.09:36:57.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.09:36:57.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.09:36:57.39#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:57.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:36:57.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:36:57.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:36:57.39#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:36:57.39#ibcon#first serial, iclass 32, count 0 2006.285.09:36:57.39#ibcon#enter sib2, iclass 32, count 0 2006.285.09:36:57.39#ibcon#flushed, iclass 32, count 0 2006.285.09:36:57.39#ibcon#about to write, iclass 32, count 0 2006.285.09:36:57.39#ibcon#wrote, iclass 32, count 0 2006.285.09:36:57.39#ibcon#about to read 3, iclass 32, count 0 2006.285.09:36:57.41#ibcon#read 3, iclass 32, count 0 2006.285.09:36:57.41#ibcon#about to read 4, iclass 32, count 0 2006.285.09:36:57.41#ibcon#read 4, iclass 32, count 0 2006.285.09:36:57.41#ibcon#about to read 5, iclass 32, count 0 2006.285.09:36:57.41#ibcon#read 5, iclass 32, count 0 2006.285.09:36:57.41#ibcon#about to read 6, iclass 32, count 0 2006.285.09:36:57.41#ibcon#read 6, iclass 32, count 0 2006.285.09:36:57.41#ibcon#end of sib2, iclass 32, count 0 2006.285.09:36:57.41#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:36:57.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:36:57.41#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:36:57.41#ibcon#*before write, iclass 32, count 0 2006.285.09:36:57.41#ibcon#enter sib2, iclass 32, count 0 2006.285.09:36:57.41#ibcon#flushed, iclass 32, count 0 2006.285.09:36:57.41#ibcon#about to write, iclass 32, count 0 2006.285.09:36:57.41#ibcon#wrote, iclass 32, count 0 2006.285.09:36:57.41#ibcon#about to read 3, iclass 32, count 0 2006.285.09:36:57.45#ibcon#read 3, iclass 32, count 0 2006.285.09:36:57.45#ibcon#about to read 4, iclass 32, count 0 2006.285.09:36:57.45#ibcon#read 4, iclass 32, count 0 2006.285.09:36:57.45#ibcon#about to read 5, iclass 32, count 0 2006.285.09:36:57.45#ibcon#read 5, iclass 32, count 0 2006.285.09:36:57.45#ibcon#about to read 6, iclass 32, count 0 2006.285.09:36:57.45#ibcon#read 6, iclass 32, count 0 2006.285.09:36:57.45#ibcon#end of sib2, iclass 32, count 0 2006.285.09:36:57.45#ibcon#*after write, iclass 32, count 0 2006.285.09:36:57.45#ibcon#*before return 0, iclass 32, count 0 2006.285.09:36:57.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:36:57.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:36:57.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:36:57.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:36:57.45$vck44/va=8,3 2006.285.09:36:57.45#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.09:36:57.45#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.09:36:57.45#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:57.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:36:57.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:36:57.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:36:57.51#ibcon#enter wrdev, iclass 34, count 2 2006.285.09:36:57.51#ibcon#first serial, iclass 34, count 2 2006.285.09:36:57.51#ibcon#enter sib2, iclass 34, count 2 2006.285.09:36:57.51#ibcon#flushed, iclass 34, count 2 2006.285.09:36:57.51#ibcon#about to write, iclass 34, count 2 2006.285.09:36:57.51#ibcon#wrote, iclass 34, count 2 2006.285.09:36:57.51#ibcon#about to read 3, iclass 34, count 2 2006.285.09:36:57.53#ibcon#read 3, iclass 34, count 2 2006.285.09:36:57.53#ibcon#about to read 4, iclass 34, count 2 2006.285.09:36:57.53#ibcon#read 4, iclass 34, count 2 2006.285.09:36:57.53#ibcon#about to read 5, iclass 34, count 2 2006.285.09:36:57.53#ibcon#read 5, iclass 34, count 2 2006.285.09:36:57.53#ibcon#about to read 6, iclass 34, count 2 2006.285.09:36:57.53#ibcon#read 6, iclass 34, count 2 2006.285.09:36:57.53#ibcon#end of sib2, iclass 34, count 2 2006.285.09:36:57.53#ibcon#*mode == 0, iclass 34, count 2 2006.285.09:36:57.53#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.09:36:57.53#ibcon#[25=AT08-03\r\n] 2006.285.09:36:57.53#ibcon#*before write, iclass 34, count 2 2006.285.09:36:57.53#ibcon#enter sib2, iclass 34, count 2 2006.285.09:36:57.53#ibcon#flushed, iclass 34, count 2 2006.285.09:36:57.53#ibcon#about to write, iclass 34, count 2 2006.285.09:36:57.53#ibcon#wrote, iclass 34, count 2 2006.285.09:36:57.53#ibcon#about to read 3, iclass 34, count 2 2006.285.09:36:57.56#ibcon#read 3, iclass 34, count 2 2006.285.09:36:57.56#ibcon#about to read 4, iclass 34, count 2 2006.285.09:36:57.56#ibcon#read 4, iclass 34, count 2 2006.285.09:36:57.56#ibcon#about to read 5, iclass 34, count 2 2006.285.09:36:57.56#ibcon#read 5, iclass 34, count 2 2006.285.09:36:57.56#ibcon#about to read 6, iclass 34, count 2 2006.285.09:36:57.56#ibcon#read 6, iclass 34, count 2 2006.285.09:36:57.56#ibcon#end of sib2, iclass 34, count 2 2006.285.09:36:57.56#ibcon#*after write, iclass 34, count 2 2006.285.09:36:57.56#ibcon#*before return 0, iclass 34, count 2 2006.285.09:36:57.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:36:57.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:36:57.56#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.09:36:57.56#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:57.56#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:36:57.68#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:36:57.68#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:36:57.68#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:36:57.68#ibcon#first serial, iclass 34, count 0 2006.285.09:36:57.68#ibcon#enter sib2, iclass 34, count 0 2006.285.09:36:57.68#ibcon#flushed, iclass 34, count 0 2006.285.09:36:57.68#ibcon#about to write, iclass 34, count 0 2006.285.09:36:57.68#ibcon#wrote, iclass 34, count 0 2006.285.09:36:57.68#ibcon#about to read 3, iclass 34, count 0 2006.285.09:36:57.70#ibcon#read 3, iclass 34, count 0 2006.285.09:36:57.70#ibcon#about to read 4, iclass 34, count 0 2006.285.09:36:57.70#ibcon#read 4, iclass 34, count 0 2006.285.09:36:57.70#ibcon#about to read 5, iclass 34, count 0 2006.285.09:36:57.70#ibcon#read 5, iclass 34, count 0 2006.285.09:36:57.70#ibcon#about to read 6, iclass 34, count 0 2006.285.09:36:57.70#ibcon#read 6, iclass 34, count 0 2006.285.09:36:57.70#ibcon#end of sib2, iclass 34, count 0 2006.285.09:36:57.70#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:36:57.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:36:57.70#ibcon#[25=USB\r\n] 2006.285.09:36:57.70#ibcon#*before write, iclass 34, count 0 2006.285.09:36:57.70#ibcon#enter sib2, iclass 34, count 0 2006.285.09:36:57.70#ibcon#flushed, iclass 34, count 0 2006.285.09:36:57.70#ibcon#about to write, iclass 34, count 0 2006.285.09:36:57.70#ibcon#wrote, iclass 34, count 0 2006.285.09:36:57.70#ibcon#about to read 3, iclass 34, count 0 2006.285.09:36:57.73#ibcon#read 3, iclass 34, count 0 2006.285.09:36:57.73#ibcon#about to read 4, iclass 34, count 0 2006.285.09:36:57.73#ibcon#read 4, iclass 34, count 0 2006.285.09:36:57.73#ibcon#about to read 5, iclass 34, count 0 2006.285.09:36:57.73#ibcon#read 5, iclass 34, count 0 2006.285.09:36:57.73#ibcon#about to read 6, iclass 34, count 0 2006.285.09:36:57.73#ibcon#read 6, iclass 34, count 0 2006.285.09:36:57.73#ibcon#end of sib2, iclass 34, count 0 2006.285.09:36:57.73#ibcon#*after write, iclass 34, count 0 2006.285.09:36:57.73#ibcon#*before return 0, iclass 34, count 0 2006.285.09:36:57.73#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:36:57.73#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:36:57.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:36:57.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:36:57.73$vck44/vblo=1,629.99 2006.285.09:36:57.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.09:36:57.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.09:36:57.73#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:57.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:36:57.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:36:57.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:36:57.73#ibcon#enter wrdev, iclass 36, count 0 2006.285.09:36:57.73#ibcon#first serial, iclass 36, count 0 2006.285.09:36:57.73#ibcon#enter sib2, iclass 36, count 0 2006.285.09:36:57.73#ibcon#flushed, iclass 36, count 0 2006.285.09:36:57.73#ibcon#about to write, iclass 36, count 0 2006.285.09:36:57.73#ibcon#wrote, iclass 36, count 0 2006.285.09:36:57.73#ibcon#about to read 3, iclass 36, count 0 2006.285.09:36:57.75#ibcon#read 3, iclass 36, count 0 2006.285.09:36:57.75#ibcon#about to read 4, iclass 36, count 0 2006.285.09:36:57.75#ibcon#read 4, iclass 36, count 0 2006.285.09:36:57.75#ibcon#about to read 5, iclass 36, count 0 2006.285.09:36:57.75#ibcon#read 5, iclass 36, count 0 2006.285.09:36:57.75#ibcon#about to read 6, iclass 36, count 0 2006.285.09:36:57.75#ibcon#read 6, iclass 36, count 0 2006.285.09:36:57.75#ibcon#end of sib2, iclass 36, count 0 2006.285.09:36:57.75#ibcon#*mode == 0, iclass 36, count 0 2006.285.09:36:57.75#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.09:36:57.75#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:36:57.75#ibcon#*before write, iclass 36, count 0 2006.285.09:36:57.75#ibcon#enter sib2, iclass 36, count 0 2006.285.09:36:57.75#ibcon#flushed, iclass 36, count 0 2006.285.09:36:57.75#ibcon#about to write, iclass 36, count 0 2006.285.09:36:57.75#ibcon#wrote, iclass 36, count 0 2006.285.09:36:57.75#ibcon#about to read 3, iclass 36, count 0 2006.285.09:36:57.79#ibcon#read 3, iclass 36, count 0 2006.285.09:36:57.79#ibcon#about to read 4, iclass 36, count 0 2006.285.09:36:57.79#ibcon#read 4, iclass 36, count 0 2006.285.09:36:57.79#ibcon#about to read 5, iclass 36, count 0 2006.285.09:36:57.79#ibcon#read 5, iclass 36, count 0 2006.285.09:36:57.79#ibcon#about to read 6, iclass 36, count 0 2006.285.09:36:57.79#ibcon#read 6, iclass 36, count 0 2006.285.09:36:57.79#ibcon#end of sib2, iclass 36, count 0 2006.285.09:36:57.79#ibcon#*after write, iclass 36, count 0 2006.285.09:36:57.79#ibcon#*before return 0, iclass 36, count 0 2006.285.09:36:57.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:36:57.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:36:57.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.09:36:57.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.09:36:57.79$vck44/vb=1,4 2006.285.09:36:57.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.09:36:57.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.09:36:57.79#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:57.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:36:57.79#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:36:57.79#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:36:57.79#ibcon#enter wrdev, iclass 38, count 2 2006.285.09:36:57.79#ibcon#first serial, iclass 38, count 2 2006.285.09:36:57.79#ibcon#enter sib2, iclass 38, count 2 2006.285.09:36:57.79#ibcon#flushed, iclass 38, count 2 2006.285.09:36:57.79#ibcon#about to write, iclass 38, count 2 2006.285.09:36:57.79#ibcon#wrote, iclass 38, count 2 2006.285.09:36:57.79#ibcon#about to read 3, iclass 38, count 2 2006.285.09:36:57.81#ibcon#read 3, iclass 38, count 2 2006.285.09:36:57.81#ibcon#about to read 4, iclass 38, count 2 2006.285.09:36:57.81#ibcon#read 4, iclass 38, count 2 2006.285.09:36:57.81#ibcon#about to read 5, iclass 38, count 2 2006.285.09:36:57.81#ibcon#read 5, iclass 38, count 2 2006.285.09:36:57.81#ibcon#about to read 6, iclass 38, count 2 2006.285.09:36:57.81#ibcon#read 6, iclass 38, count 2 2006.285.09:36:57.81#ibcon#end of sib2, iclass 38, count 2 2006.285.09:36:57.81#ibcon#*mode == 0, iclass 38, count 2 2006.285.09:36:57.81#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.09:36:57.81#ibcon#[27=AT01-04\r\n] 2006.285.09:36:57.81#ibcon#*before write, iclass 38, count 2 2006.285.09:36:57.81#ibcon#enter sib2, iclass 38, count 2 2006.285.09:36:57.81#ibcon#flushed, iclass 38, count 2 2006.285.09:36:57.81#ibcon#about to write, iclass 38, count 2 2006.285.09:36:57.81#ibcon#wrote, iclass 38, count 2 2006.285.09:36:57.81#ibcon#about to read 3, iclass 38, count 2 2006.285.09:36:57.84#ibcon#read 3, iclass 38, count 2 2006.285.09:36:57.84#ibcon#about to read 4, iclass 38, count 2 2006.285.09:36:57.84#ibcon#read 4, iclass 38, count 2 2006.285.09:36:57.84#ibcon#about to read 5, iclass 38, count 2 2006.285.09:36:57.84#ibcon#read 5, iclass 38, count 2 2006.285.09:36:57.84#ibcon#about to read 6, iclass 38, count 2 2006.285.09:36:57.84#ibcon#read 6, iclass 38, count 2 2006.285.09:36:57.84#ibcon#end of sib2, iclass 38, count 2 2006.285.09:36:57.84#ibcon#*after write, iclass 38, count 2 2006.285.09:36:57.84#ibcon#*before return 0, iclass 38, count 2 2006.285.09:36:57.84#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:36:57.84#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:36:57.84#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.09:36:57.84#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:57.84#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:36:57.96#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:36:57.96#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:36:57.96#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:36:57.96#ibcon#first serial, iclass 38, count 0 2006.285.09:36:57.96#ibcon#enter sib2, iclass 38, count 0 2006.285.09:36:57.96#ibcon#flushed, iclass 38, count 0 2006.285.09:36:57.96#ibcon#about to write, iclass 38, count 0 2006.285.09:36:57.96#ibcon#wrote, iclass 38, count 0 2006.285.09:36:57.96#ibcon#about to read 3, iclass 38, count 0 2006.285.09:36:57.98#ibcon#read 3, iclass 38, count 0 2006.285.09:36:57.98#ibcon#about to read 4, iclass 38, count 0 2006.285.09:36:57.98#ibcon#read 4, iclass 38, count 0 2006.285.09:36:57.98#ibcon#about to read 5, iclass 38, count 0 2006.285.09:36:57.98#ibcon#read 5, iclass 38, count 0 2006.285.09:36:57.98#ibcon#about to read 6, iclass 38, count 0 2006.285.09:36:57.98#ibcon#read 6, iclass 38, count 0 2006.285.09:36:57.98#ibcon#end of sib2, iclass 38, count 0 2006.285.09:36:57.98#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:36:57.98#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:36:57.98#ibcon#[27=USB\r\n] 2006.285.09:36:57.98#ibcon#*before write, iclass 38, count 0 2006.285.09:36:57.98#ibcon#enter sib2, iclass 38, count 0 2006.285.09:36:57.98#ibcon#flushed, iclass 38, count 0 2006.285.09:36:57.98#ibcon#about to write, iclass 38, count 0 2006.285.09:36:57.98#ibcon#wrote, iclass 38, count 0 2006.285.09:36:57.98#ibcon#about to read 3, iclass 38, count 0 2006.285.09:36:58.01#ibcon#read 3, iclass 38, count 0 2006.285.09:36:58.01#ibcon#about to read 4, iclass 38, count 0 2006.285.09:36:58.01#ibcon#read 4, iclass 38, count 0 2006.285.09:36:58.01#ibcon#about to read 5, iclass 38, count 0 2006.285.09:36:58.01#ibcon#read 5, iclass 38, count 0 2006.285.09:36:58.01#ibcon#about to read 6, iclass 38, count 0 2006.285.09:36:58.01#ibcon#read 6, iclass 38, count 0 2006.285.09:36:58.01#ibcon#end of sib2, iclass 38, count 0 2006.285.09:36:58.01#ibcon#*after write, iclass 38, count 0 2006.285.09:36:58.01#ibcon#*before return 0, iclass 38, count 0 2006.285.09:36:58.01#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:36:58.01#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:36:58.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:36:58.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:36:58.01$vck44/vblo=2,634.99 2006.285.09:36:58.01#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.09:36:58.01#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.09:36:58.01#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:58.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:36:58.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:36:58.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:36:58.01#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:36:58.01#ibcon#first serial, iclass 40, count 0 2006.285.09:36:58.01#ibcon#enter sib2, iclass 40, count 0 2006.285.09:36:58.01#ibcon#flushed, iclass 40, count 0 2006.285.09:36:58.01#ibcon#about to write, iclass 40, count 0 2006.285.09:36:58.01#ibcon#wrote, iclass 40, count 0 2006.285.09:36:58.01#ibcon#about to read 3, iclass 40, count 0 2006.285.09:36:58.03#ibcon#read 3, iclass 40, count 0 2006.285.09:36:58.03#ibcon#about to read 4, iclass 40, count 0 2006.285.09:36:58.03#ibcon#read 4, iclass 40, count 0 2006.285.09:36:58.03#ibcon#about to read 5, iclass 40, count 0 2006.285.09:36:58.03#ibcon#read 5, iclass 40, count 0 2006.285.09:36:58.03#ibcon#about to read 6, iclass 40, count 0 2006.285.09:36:58.03#ibcon#read 6, iclass 40, count 0 2006.285.09:36:58.03#ibcon#end of sib2, iclass 40, count 0 2006.285.09:36:58.03#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:36:58.03#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:36:58.03#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:36:58.03#ibcon#*before write, iclass 40, count 0 2006.285.09:36:58.03#ibcon#enter sib2, iclass 40, count 0 2006.285.09:36:58.03#ibcon#flushed, iclass 40, count 0 2006.285.09:36:58.03#ibcon#about to write, iclass 40, count 0 2006.285.09:36:58.03#ibcon#wrote, iclass 40, count 0 2006.285.09:36:58.03#ibcon#about to read 3, iclass 40, count 0 2006.285.09:36:58.07#ibcon#read 3, iclass 40, count 0 2006.285.09:36:58.07#ibcon#about to read 4, iclass 40, count 0 2006.285.09:36:58.07#ibcon#read 4, iclass 40, count 0 2006.285.09:36:58.07#ibcon#about to read 5, iclass 40, count 0 2006.285.09:36:58.07#ibcon#read 5, iclass 40, count 0 2006.285.09:36:58.07#ibcon#about to read 6, iclass 40, count 0 2006.285.09:36:58.07#ibcon#read 6, iclass 40, count 0 2006.285.09:36:58.07#ibcon#end of sib2, iclass 40, count 0 2006.285.09:36:58.07#ibcon#*after write, iclass 40, count 0 2006.285.09:36:58.07#ibcon#*before return 0, iclass 40, count 0 2006.285.09:36:58.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:36:58.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:36:58.07#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:36:58.07#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:36:58.07$vck44/vb=2,5 2006.285.09:36:58.07#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.09:36:58.07#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.09:36:58.07#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:58.07#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:36:58.13#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:36:58.13#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:36:58.13#ibcon#enter wrdev, iclass 4, count 2 2006.285.09:36:58.13#ibcon#first serial, iclass 4, count 2 2006.285.09:36:58.13#ibcon#enter sib2, iclass 4, count 2 2006.285.09:36:58.13#ibcon#flushed, iclass 4, count 2 2006.285.09:36:58.13#ibcon#about to write, iclass 4, count 2 2006.285.09:36:58.13#ibcon#wrote, iclass 4, count 2 2006.285.09:36:58.13#ibcon#about to read 3, iclass 4, count 2 2006.285.09:36:58.15#ibcon#read 3, iclass 4, count 2 2006.285.09:36:58.15#ibcon#about to read 4, iclass 4, count 2 2006.285.09:36:58.15#ibcon#read 4, iclass 4, count 2 2006.285.09:36:58.15#ibcon#about to read 5, iclass 4, count 2 2006.285.09:36:58.15#ibcon#read 5, iclass 4, count 2 2006.285.09:36:58.15#ibcon#about to read 6, iclass 4, count 2 2006.285.09:36:58.15#ibcon#read 6, iclass 4, count 2 2006.285.09:36:58.15#ibcon#end of sib2, iclass 4, count 2 2006.285.09:36:58.15#ibcon#*mode == 0, iclass 4, count 2 2006.285.09:36:58.15#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.09:36:58.15#ibcon#[27=AT02-05\r\n] 2006.285.09:36:58.15#ibcon#*before write, iclass 4, count 2 2006.285.09:36:58.15#ibcon#enter sib2, iclass 4, count 2 2006.285.09:36:58.15#ibcon#flushed, iclass 4, count 2 2006.285.09:36:58.15#ibcon#about to write, iclass 4, count 2 2006.285.09:36:58.15#ibcon#wrote, iclass 4, count 2 2006.285.09:36:58.15#ibcon#about to read 3, iclass 4, count 2 2006.285.09:36:58.18#ibcon#read 3, iclass 4, count 2 2006.285.09:36:58.18#ibcon#about to read 4, iclass 4, count 2 2006.285.09:36:58.18#ibcon#read 4, iclass 4, count 2 2006.285.09:36:58.18#ibcon#about to read 5, iclass 4, count 2 2006.285.09:36:58.18#ibcon#read 5, iclass 4, count 2 2006.285.09:36:58.18#ibcon#about to read 6, iclass 4, count 2 2006.285.09:36:58.18#ibcon#read 6, iclass 4, count 2 2006.285.09:36:58.18#ibcon#end of sib2, iclass 4, count 2 2006.285.09:36:58.18#ibcon#*after write, iclass 4, count 2 2006.285.09:36:58.18#ibcon#*before return 0, iclass 4, count 2 2006.285.09:36:58.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:36:58.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:36:58.18#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.09:36:58.18#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:58.18#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:36:58.30#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:36:58.30#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:36:58.30#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:36:58.30#ibcon#first serial, iclass 4, count 0 2006.285.09:36:58.30#ibcon#enter sib2, iclass 4, count 0 2006.285.09:36:58.30#ibcon#flushed, iclass 4, count 0 2006.285.09:36:58.30#ibcon#about to write, iclass 4, count 0 2006.285.09:36:58.30#ibcon#wrote, iclass 4, count 0 2006.285.09:36:58.30#ibcon#about to read 3, iclass 4, count 0 2006.285.09:36:58.32#ibcon#read 3, iclass 4, count 0 2006.285.09:36:58.32#ibcon#about to read 4, iclass 4, count 0 2006.285.09:36:58.32#ibcon#read 4, iclass 4, count 0 2006.285.09:36:58.32#ibcon#about to read 5, iclass 4, count 0 2006.285.09:36:58.32#ibcon#read 5, iclass 4, count 0 2006.285.09:36:58.32#ibcon#about to read 6, iclass 4, count 0 2006.285.09:36:58.32#ibcon#read 6, iclass 4, count 0 2006.285.09:36:58.32#ibcon#end of sib2, iclass 4, count 0 2006.285.09:36:58.32#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:36:58.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:36:58.32#ibcon#[27=USB\r\n] 2006.285.09:36:58.32#ibcon#*before write, iclass 4, count 0 2006.285.09:36:58.32#ibcon#enter sib2, iclass 4, count 0 2006.285.09:36:58.32#ibcon#flushed, iclass 4, count 0 2006.285.09:36:58.32#ibcon#about to write, iclass 4, count 0 2006.285.09:36:58.32#ibcon#wrote, iclass 4, count 0 2006.285.09:36:58.32#ibcon#about to read 3, iclass 4, count 0 2006.285.09:36:58.35#ibcon#read 3, iclass 4, count 0 2006.285.09:36:58.35#ibcon#about to read 4, iclass 4, count 0 2006.285.09:36:58.35#ibcon#read 4, iclass 4, count 0 2006.285.09:36:58.35#ibcon#about to read 5, iclass 4, count 0 2006.285.09:36:58.35#ibcon#read 5, iclass 4, count 0 2006.285.09:36:58.35#ibcon#about to read 6, iclass 4, count 0 2006.285.09:36:58.35#ibcon#read 6, iclass 4, count 0 2006.285.09:36:58.35#ibcon#end of sib2, iclass 4, count 0 2006.285.09:36:58.35#ibcon#*after write, iclass 4, count 0 2006.285.09:36:58.35#ibcon#*before return 0, iclass 4, count 0 2006.285.09:36:58.35#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:36:58.35#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:36:58.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:36:58.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:36:58.35$vck44/vblo=3,649.99 2006.285.09:36:58.35#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.09:36:58.35#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.09:36:58.35#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:58.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:36:58.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:36:58.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:36:58.35#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:36:58.35#ibcon#first serial, iclass 6, count 0 2006.285.09:36:58.35#ibcon#enter sib2, iclass 6, count 0 2006.285.09:36:58.35#ibcon#flushed, iclass 6, count 0 2006.285.09:36:58.35#ibcon#about to write, iclass 6, count 0 2006.285.09:36:58.35#ibcon#wrote, iclass 6, count 0 2006.285.09:36:58.35#ibcon#about to read 3, iclass 6, count 0 2006.285.09:36:58.37#ibcon#read 3, iclass 6, count 0 2006.285.09:36:58.37#ibcon#about to read 4, iclass 6, count 0 2006.285.09:36:58.37#ibcon#read 4, iclass 6, count 0 2006.285.09:36:58.37#ibcon#about to read 5, iclass 6, count 0 2006.285.09:36:58.37#ibcon#read 5, iclass 6, count 0 2006.285.09:36:58.37#ibcon#about to read 6, iclass 6, count 0 2006.285.09:36:58.37#ibcon#read 6, iclass 6, count 0 2006.285.09:36:58.37#ibcon#end of sib2, iclass 6, count 0 2006.285.09:36:58.37#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:36:58.37#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:36:58.37#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:36:58.37#ibcon#*before write, iclass 6, count 0 2006.285.09:36:58.37#ibcon#enter sib2, iclass 6, count 0 2006.285.09:36:58.37#ibcon#flushed, iclass 6, count 0 2006.285.09:36:58.37#ibcon#about to write, iclass 6, count 0 2006.285.09:36:58.37#ibcon#wrote, iclass 6, count 0 2006.285.09:36:58.37#ibcon#about to read 3, iclass 6, count 0 2006.285.09:36:58.41#ibcon#read 3, iclass 6, count 0 2006.285.09:36:58.41#ibcon#about to read 4, iclass 6, count 0 2006.285.09:36:58.41#ibcon#read 4, iclass 6, count 0 2006.285.09:36:58.41#ibcon#about to read 5, iclass 6, count 0 2006.285.09:36:58.41#ibcon#read 5, iclass 6, count 0 2006.285.09:36:58.41#ibcon#about to read 6, iclass 6, count 0 2006.285.09:36:58.41#ibcon#read 6, iclass 6, count 0 2006.285.09:36:58.41#ibcon#end of sib2, iclass 6, count 0 2006.285.09:36:58.41#ibcon#*after write, iclass 6, count 0 2006.285.09:36:58.41#ibcon#*before return 0, iclass 6, count 0 2006.285.09:36:58.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:36:58.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:36:58.41#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:36:58.41#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:36:58.41$vck44/vb=3,4 2006.285.09:36:58.41#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.09:36:58.41#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.09:36:58.41#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:58.41#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:36:58.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:36:58.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:36:58.47#ibcon#enter wrdev, iclass 10, count 2 2006.285.09:36:58.47#ibcon#first serial, iclass 10, count 2 2006.285.09:36:58.47#ibcon#enter sib2, iclass 10, count 2 2006.285.09:36:58.47#ibcon#flushed, iclass 10, count 2 2006.285.09:36:58.47#ibcon#about to write, iclass 10, count 2 2006.285.09:36:58.47#ibcon#wrote, iclass 10, count 2 2006.285.09:36:58.47#ibcon#about to read 3, iclass 10, count 2 2006.285.09:36:58.49#ibcon#read 3, iclass 10, count 2 2006.285.09:36:58.49#ibcon#about to read 4, iclass 10, count 2 2006.285.09:36:58.49#ibcon#read 4, iclass 10, count 2 2006.285.09:36:58.49#ibcon#about to read 5, iclass 10, count 2 2006.285.09:36:58.49#ibcon#read 5, iclass 10, count 2 2006.285.09:36:58.49#ibcon#about to read 6, iclass 10, count 2 2006.285.09:36:58.49#ibcon#read 6, iclass 10, count 2 2006.285.09:36:58.49#ibcon#end of sib2, iclass 10, count 2 2006.285.09:36:58.49#ibcon#*mode == 0, iclass 10, count 2 2006.285.09:36:58.49#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.09:36:58.49#ibcon#[27=AT03-04\r\n] 2006.285.09:36:58.49#ibcon#*before write, iclass 10, count 2 2006.285.09:36:58.49#ibcon#enter sib2, iclass 10, count 2 2006.285.09:36:58.49#ibcon#flushed, iclass 10, count 2 2006.285.09:36:58.49#ibcon#about to write, iclass 10, count 2 2006.285.09:36:58.49#ibcon#wrote, iclass 10, count 2 2006.285.09:36:58.49#ibcon#about to read 3, iclass 10, count 2 2006.285.09:36:58.52#ibcon#read 3, iclass 10, count 2 2006.285.09:36:58.52#ibcon#about to read 4, iclass 10, count 2 2006.285.09:36:58.52#ibcon#read 4, iclass 10, count 2 2006.285.09:36:58.52#ibcon#about to read 5, iclass 10, count 2 2006.285.09:36:58.52#ibcon#read 5, iclass 10, count 2 2006.285.09:36:58.52#ibcon#about to read 6, iclass 10, count 2 2006.285.09:36:58.52#ibcon#read 6, iclass 10, count 2 2006.285.09:36:58.52#ibcon#end of sib2, iclass 10, count 2 2006.285.09:36:58.52#ibcon#*after write, iclass 10, count 2 2006.285.09:36:58.52#ibcon#*before return 0, iclass 10, count 2 2006.285.09:36:58.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:36:58.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:36:58.52#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.09:36:58.52#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:58.52#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:36:58.64#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:36:58.64#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:36:58.64#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:36:58.64#ibcon#first serial, iclass 10, count 0 2006.285.09:36:58.64#ibcon#enter sib2, iclass 10, count 0 2006.285.09:36:58.64#ibcon#flushed, iclass 10, count 0 2006.285.09:36:58.64#ibcon#about to write, iclass 10, count 0 2006.285.09:36:58.64#ibcon#wrote, iclass 10, count 0 2006.285.09:36:58.64#ibcon#about to read 3, iclass 10, count 0 2006.285.09:36:58.66#ibcon#read 3, iclass 10, count 0 2006.285.09:36:58.66#ibcon#about to read 4, iclass 10, count 0 2006.285.09:36:58.66#ibcon#read 4, iclass 10, count 0 2006.285.09:36:58.66#ibcon#about to read 5, iclass 10, count 0 2006.285.09:36:58.66#ibcon#read 5, iclass 10, count 0 2006.285.09:36:58.66#ibcon#about to read 6, iclass 10, count 0 2006.285.09:36:58.66#ibcon#read 6, iclass 10, count 0 2006.285.09:36:58.66#ibcon#end of sib2, iclass 10, count 0 2006.285.09:36:58.66#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:36:58.66#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:36:58.66#ibcon#[27=USB\r\n] 2006.285.09:36:58.66#ibcon#*before write, iclass 10, count 0 2006.285.09:36:58.66#ibcon#enter sib2, iclass 10, count 0 2006.285.09:36:58.66#ibcon#flushed, iclass 10, count 0 2006.285.09:36:58.66#ibcon#about to write, iclass 10, count 0 2006.285.09:36:58.66#ibcon#wrote, iclass 10, count 0 2006.285.09:36:58.66#ibcon#about to read 3, iclass 10, count 0 2006.285.09:36:58.69#ibcon#read 3, iclass 10, count 0 2006.285.09:36:58.69#ibcon#about to read 4, iclass 10, count 0 2006.285.09:36:58.69#ibcon#read 4, iclass 10, count 0 2006.285.09:36:58.69#ibcon#about to read 5, iclass 10, count 0 2006.285.09:36:58.69#ibcon#read 5, iclass 10, count 0 2006.285.09:36:58.69#ibcon#about to read 6, iclass 10, count 0 2006.285.09:36:58.69#ibcon#read 6, iclass 10, count 0 2006.285.09:36:58.69#ibcon#end of sib2, iclass 10, count 0 2006.285.09:36:58.69#ibcon#*after write, iclass 10, count 0 2006.285.09:36:58.69#ibcon#*before return 0, iclass 10, count 0 2006.285.09:36:58.69#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:36:58.69#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:36:58.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:36:58.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:36:58.69$vck44/vblo=4,679.99 2006.285.09:36:58.69#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.09:36:58.69#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.09:36:58.69#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:58.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:36:58.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:36:58.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:36:58.69#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:36:58.69#ibcon#first serial, iclass 12, count 0 2006.285.09:36:58.69#ibcon#enter sib2, iclass 12, count 0 2006.285.09:36:58.69#ibcon#flushed, iclass 12, count 0 2006.285.09:36:58.69#ibcon#about to write, iclass 12, count 0 2006.285.09:36:58.69#ibcon#wrote, iclass 12, count 0 2006.285.09:36:58.69#ibcon#about to read 3, iclass 12, count 0 2006.285.09:36:58.71#ibcon#read 3, iclass 12, count 0 2006.285.09:36:58.71#ibcon#about to read 4, iclass 12, count 0 2006.285.09:36:58.71#ibcon#read 4, iclass 12, count 0 2006.285.09:36:58.71#ibcon#about to read 5, iclass 12, count 0 2006.285.09:36:58.71#ibcon#read 5, iclass 12, count 0 2006.285.09:36:58.71#ibcon#about to read 6, iclass 12, count 0 2006.285.09:36:58.71#ibcon#read 6, iclass 12, count 0 2006.285.09:36:58.71#ibcon#end of sib2, iclass 12, count 0 2006.285.09:36:58.71#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:36:58.71#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:36:58.71#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:36:58.71#ibcon#*before write, iclass 12, count 0 2006.285.09:36:58.71#ibcon#enter sib2, iclass 12, count 0 2006.285.09:36:58.71#ibcon#flushed, iclass 12, count 0 2006.285.09:36:58.71#ibcon#about to write, iclass 12, count 0 2006.285.09:36:58.71#ibcon#wrote, iclass 12, count 0 2006.285.09:36:58.71#ibcon#about to read 3, iclass 12, count 0 2006.285.09:36:58.75#ibcon#read 3, iclass 12, count 0 2006.285.09:36:58.75#ibcon#about to read 4, iclass 12, count 0 2006.285.09:36:58.75#ibcon#read 4, iclass 12, count 0 2006.285.09:36:58.75#ibcon#about to read 5, iclass 12, count 0 2006.285.09:36:58.75#ibcon#read 5, iclass 12, count 0 2006.285.09:36:58.75#ibcon#about to read 6, iclass 12, count 0 2006.285.09:36:58.75#ibcon#read 6, iclass 12, count 0 2006.285.09:36:58.75#ibcon#end of sib2, iclass 12, count 0 2006.285.09:36:58.75#ibcon#*after write, iclass 12, count 0 2006.285.09:36:58.75#ibcon#*before return 0, iclass 12, count 0 2006.285.09:36:58.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:36:58.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:36:58.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:36:58.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:36:58.75$vck44/vb=4,5 2006.285.09:36:58.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.09:36:58.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.09:36:58.75#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:58.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:36:58.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:36:58.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:36:58.81#ibcon#enter wrdev, iclass 14, count 2 2006.285.09:36:58.81#ibcon#first serial, iclass 14, count 2 2006.285.09:36:58.81#ibcon#enter sib2, iclass 14, count 2 2006.285.09:36:58.81#ibcon#flushed, iclass 14, count 2 2006.285.09:36:58.81#ibcon#about to write, iclass 14, count 2 2006.285.09:36:58.81#ibcon#wrote, iclass 14, count 2 2006.285.09:36:58.81#ibcon#about to read 3, iclass 14, count 2 2006.285.09:36:58.83#ibcon#read 3, iclass 14, count 2 2006.285.09:36:58.83#ibcon#about to read 4, iclass 14, count 2 2006.285.09:36:58.83#ibcon#read 4, iclass 14, count 2 2006.285.09:36:58.83#ibcon#about to read 5, iclass 14, count 2 2006.285.09:36:58.83#ibcon#read 5, iclass 14, count 2 2006.285.09:36:58.83#ibcon#about to read 6, iclass 14, count 2 2006.285.09:36:58.83#ibcon#read 6, iclass 14, count 2 2006.285.09:36:58.83#ibcon#end of sib2, iclass 14, count 2 2006.285.09:36:58.83#ibcon#*mode == 0, iclass 14, count 2 2006.285.09:36:58.83#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.09:36:58.83#ibcon#[27=AT04-05\r\n] 2006.285.09:36:58.83#ibcon#*before write, iclass 14, count 2 2006.285.09:36:58.83#ibcon#enter sib2, iclass 14, count 2 2006.285.09:36:58.83#ibcon#flushed, iclass 14, count 2 2006.285.09:36:58.83#ibcon#about to write, iclass 14, count 2 2006.285.09:36:58.83#ibcon#wrote, iclass 14, count 2 2006.285.09:36:58.83#ibcon#about to read 3, iclass 14, count 2 2006.285.09:36:58.86#ibcon#read 3, iclass 14, count 2 2006.285.09:36:58.86#ibcon#about to read 4, iclass 14, count 2 2006.285.09:36:58.86#ibcon#read 4, iclass 14, count 2 2006.285.09:36:58.86#ibcon#about to read 5, iclass 14, count 2 2006.285.09:36:58.86#ibcon#read 5, iclass 14, count 2 2006.285.09:36:58.86#ibcon#about to read 6, iclass 14, count 2 2006.285.09:36:58.86#ibcon#read 6, iclass 14, count 2 2006.285.09:36:58.86#ibcon#end of sib2, iclass 14, count 2 2006.285.09:36:58.86#ibcon#*after write, iclass 14, count 2 2006.285.09:36:58.86#ibcon#*before return 0, iclass 14, count 2 2006.285.09:36:58.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:36:58.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:36:58.86#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.09:36:58.86#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:58.86#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:36:58.98#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:36:58.98#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:36:58.98#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:36:58.98#ibcon#first serial, iclass 14, count 0 2006.285.09:36:58.98#ibcon#enter sib2, iclass 14, count 0 2006.285.09:36:58.98#ibcon#flushed, iclass 14, count 0 2006.285.09:36:58.98#ibcon#about to write, iclass 14, count 0 2006.285.09:36:58.98#ibcon#wrote, iclass 14, count 0 2006.285.09:36:58.98#ibcon#about to read 3, iclass 14, count 0 2006.285.09:36:59.00#ibcon#read 3, iclass 14, count 0 2006.285.09:36:59.00#ibcon#about to read 4, iclass 14, count 0 2006.285.09:36:59.00#ibcon#read 4, iclass 14, count 0 2006.285.09:36:59.00#ibcon#about to read 5, iclass 14, count 0 2006.285.09:36:59.00#ibcon#read 5, iclass 14, count 0 2006.285.09:36:59.00#ibcon#about to read 6, iclass 14, count 0 2006.285.09:36:59.00#ibcon#read 6, iclass 14, count 0 2006.285.09:36:59.00#ibcon#end of sib2, iclass 14, count 0 2006.285.09:36:59.00#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:36:59.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:36:59.00#ibcon#[27=USB\r\n] 2006.285.09:36:59.00#ibcon#*before write, iclass 14, count 0 2006.285.09:36:59.00#ibcon#enter sib2, iclass 14, count 0 2006.285.09:36:59.00#ibcon#flushed, iclass 14, count 0 2006.285.09:36:59.00#ibcon#about to write, iclass 14, count 0 2006.285.09:36:59.00#ibcon#wrote, iclass 14, count 0 2006.285.09:36:59.00#ibcon#about to read 3, iclass 14, count 0 2006.285.09:36:59.03#ibcon#read 3, iclass 14, count 0 2006.285.09:36:59.03#ibcon#about to read 4, iclass 14, count 0 2006.285.09:36:59.03#ibcon#read 4, iclass 14, count 0 2006.285.09:36:59.03#ibcon#about to read 5, iclass 14, count 0 2006.285.09:36:59.03#ibcon#read 5, iclass 14, count 0 2006.285.09:36:59.03#ibcon#about to read 6, iclass 14, count 0 2006.285.09:36:59.03#ibcon#read 6, iclass 14, count 0 2006.285.09:36:59.03#ibcon#end of sib2, iclass 14, count 0 2006.285.09:36:59.03#ibcon#*after write, iclass 14, count 0 2006.285.09:36:59.03#ibcon#*before return 0, iclass 14, count 0 2006.285.09:36:59.03#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:36:59.03#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:36:59.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:36:59.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:36:59.03$vck44/vblo=5,709.99 2006.285.09:36:59.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.09:36:59.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.09:36:59.03#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:59.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:36:59.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:36:59.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:36:59.03#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:36:59.03#ibcon#first serial, iclass 16, count 0 2006.285.09:36:59.03#ibcon#enter sib2, iclass 16, count 0 2006.285.09:36:59.03#ibcon#flushed, iclass 16, count 0 2006.285.09:36:59.03#ibcon#about to write, iclass 16, count 0 2006.285.09:36:59.03#ibcon#wrote, iclass 16, count 0 2006.285.09:36:59.03#ibcon#about to read 3, iclass 16, count 0 2006.285.09:36:59.05#ibcon#read 3, iclass 16, count 0 2006.285.09:36:59.05#ibcon#about to read 4, iclass 16, count 0 2006.285.09:36:59.05#ibcon#read 4, iclass 16, count 0 2006.285.09:36:59.05#ibcon#about to read 5, iclass 16, count 0 2006.285.09:36:59.05#ibcon#read 5, iclass 16, count 0 2006.285.09:36:59.05#ibcon#about to read 6, iclass 16, count 0 2006.285.09:36:59.05#ibcon#read 6, iclass 16, count 0 2006.285.09:36:59.05#ibcon#end of sib2, iclass 16, count 0 2006.285.09:36:59.05#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:36:59.05#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:36:59.05#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:36:59.05#ibcon#*before write, iclass 16, count 0 2006.285.09:36:59.05#ibcon#enter sib2, iclass 16, count 0 2006.285.09:36:59.05#ibcon#flushed, iclass 16, count 0 2006.285.09:36:59.05#ibcon#about to write, iclass 16, count 0 2006.285.09:36:59.05#ibcon#wrote, iclass 16, count 0 2006.285.09:36:59.05#ibcon#about to read 3, iclass 16, count 0 2006.285.09:36:59.09#ibcon#read 3, iclass 16, count 0 2006.285.09:36:59.09#ibcon#about to read 4, iclass 16, count 0 2006.285.09:36:59.09#ibcon#read 4, iclass 16, count 0 2006.285.09:36:59.09#ibcon#about to read 5, iclass 16, count 0 2006.285.09:36:59.09#ibcon#read 5, iclass 16, count 0 2006.285.09:36:59.09#ibcon#about to read 6, iclass 16, count 0 2006.285.09:36:59.09#ibcon#read 6, iclass 16, count 0 2006.285.09:36:59.09#ibcon#end of sib2, iclass 16, count 0 2006.285.09:36:59.09#ibcon#*after write, iclass 16, count 0 2006.285.09:36:59.09#ibcon#*before return 0, iclass 16, count 0 2006.285.09:36:59.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:36:59.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:36:59.09#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:36:59.09#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:36:59.09$vck44/vb=5,4 2006.285.09:36:59.09#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.09:36:59.09#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.09:36:59.09#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:59.09#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:36:59.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:36:59.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:36:59.15#ibcon#enter wrdev, iclass 18, count 2 2006.285.09:36:59.15#ibcon#first serial, iclass 18, count 2 2006.285.09:36:59.15#ibcon#enter sib2, iclass 18, count 2 2006.285.09:36:59.15#ibcon#flushed, iclass 18, count 2 2006.285.09:36:59.15#ibcon#about to write, iclass 18, count 2 2006.285.09:36:59.15#ibcon#wrote, iclass 18, count 2 2006.285.09:36:59.15#ibcon#about to read 3, iclass 18, count 2 2006.285.09:36:59.17#ibcon#read 3, iclass 18, count 2 2006.285.09:36:59.17#ibcon#about to read 4, iclass 18, count 2 2006.285.09:36:59.17#ibcon#read 4, iclass 18, count 2 2006.285.09:36:59.17#ibcon#about to read 5, iclass 18, count 2 2006.285.09:36:59.17#ibcon#read 5, iclass 18, count 2 2006.285.09:36:59.17#ibcon#about to read 6, iclass 18, count 2 2006.285.09:36:59.17#ibcon#read 6, iclass 18, count 2 2006.285.09:36:59.17#ibcon#end of sib2, iclass 18, count 2 2006.285.09:36:59.17#ibcon#*mode == 0, iclass 18, count 2 2006.285.09:36:59.17#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.09:36:59.17#ibcon#[27=AT05-04\r\n] 2006.285.09:36:59.17#ibcon#*before write, iclass 18, count 2 2006.285.09:36:59.17#ibcon#enter sib2, iclass 18, count 2 2006.285.09:36:59.17#ibcon#flushed, iclass 18, count 2 2006.285.09:36:59.17#ibcon#about to write, iclass 18, count 2 2006.285.09:36:59.17#ibcon#wrote, iclass 18, count 2 2006.285.09:36:59.17#ibcon#about to read 3, iclass 18, count 2 2006.285.09:36:59.20#ibcon#read 3, iclass 18, count 2 2006.285.09:36:59.20#ibcon#about to read 4, iclass 18, count 2 2006.285.09:36:59.20#ibcon#read 4, iclass 18, count 2 2006.285.09:36:59.20#ibcon#about to read 5, iclass 18, count 2 2006.285.09:36:59.20#ibcon#read 5, iclass 18, count 2 2006.285.09:36:59.20#ibcon#about to read 6, iclass 18, count 2 2006.285.09:36:59.20#ibcon#read 6, iclass 18, count 2 2006.285.09:36:59.20#ibcon#end of sib2, iclass 18, count 2 2006.285.09:36:59.20#ibcon#*after write, iclass 18, count 2 2006.285.09:36:59.20#ibcon#*before return 0, iclass 18, count 2 2006.285.09:36:59.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:36:59.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:36:59.20#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.09:36:59.20#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:59.20#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:36:59.32#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:36:59.32#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:36:59.32#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:36:59.32#ibcon#first serial, iclass 18, count 0 2006.285.09:36:59.32#ibcon#enter sib2, iclass 18, count 0 2006.285.09:36:59.32#ibcon#flushed, iclass 18, count 0 2006.285.09:36:59.32#ibcon#about to write, iclass 18, count 0 2006.285.09:36:59.32#ibcon#wrote, iclass 18, count 0 2006.285.09:36:59.32#ibcon#about to read 3, iclass 18, count 0 2006.285.09:36:59.34#ibcon#read 3, iclass 18, count 0 2006.285.09:36:59.34#ibcon#about to read 4, iclass 18, count 0 2006.285.09:36:59.34#ibcon#read 4, iclass 18, count 0 2006.285.09:36:59.34#ibcon#about to read 5, iclass 18, count 0 2006.285.09:36:59.34#ibcon#read 5, iclass 18, count 0 2006.285.09:36:59.34#ibcon#about to read 6, iclass 18, count 0 2006.285.09:36:59.34#ibcon#read 6, iclass 18, count 0 2006.285.09:36:59.34#ibcon#end of sib2, iclass 18, count 0 2006.285.09:36:59.34#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:36:59.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:36:59.34#ibcon#[27=USB\r\n] 2006.285.09:36:59.34#ibcon#*before write, iclass 18, count 0 2006.285.09:36:59.34#ibcon#enter sib2, iclass 18, count 0 2006.285.09:36:59.34#ibcon#flushed, iclass 18, count 0 2006.285.09:36:59.34#ibcon#about to write, iclass 18, count 0 2006.285.09:36:59.34#ibcon#wrote, iclass 18, count 0 2006.285.09:36:59.34#ibcon#about to read 3, iclass 18, count 0 2006.285.09:36:59.37#ibcon#read 3, iclass 18, count 0 2006.285.09:36:59.37#ibcon#about to read 4, iclass 18, count 0 2006.285.09:36:59.37#ibcon#read 4, iclass 18, count 0 2006.285.09:36:59.37#ibcon#about to read 5, iclass 18, count 0 2006.285.09:36:59.37#ibcon#read 5, iclass 18, count 0 2006.285.09:36:59.37#ibcon#about to read 6, iclass 18, count 0 2006.285.09:36:59.37#ibcon#read 6, iclass 18, count 0 2006.285.09:36:59.37#ibcon#end of sib2, iclass 18, count 0 2006.285.09:36:59.37#ibcon#*after write, iclass 18, count 0 2006.285.09:36:59.37#ibcon#*before return 0, iclass 18, count 0 2006.285.09:36:59.37#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:36:59.37#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:36:59.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:36:59.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:36:59.37$vck44/vblo=6,719.99 2006.285.09:36:59.37#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.09:36:59.37#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.09:36:59.37#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:59.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:36:59.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:36:59.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:36:59.37#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:36:59.37#ibcon#first serial, iclass 20, count 0 2006.285.09:36:59.37#ibcon#enter sib2, iclass 20, count 0 2006.285.09:36:59.37#ibcon#flushed, iclass 20, count 0 2006.285.09:36:59.37#ibcon#about to write, iclass 20, count 0 2006.285.09:36:59.37#ibcon#wrote, iclass 20, count 0 2006.285.09:36:59.37#ibcon#about to read 3, iclass 20, count 0 2006.285.09:36:59.39#ibcon#read 3, iclass 20, count 0 2006.285.09:36:59.39#ibcon#about to read 4, iclass 20, count 0 2006.285.09:36:59.39#ibcon#read 4, iclass 20, count 0 2006.285.09:36:59.39#ibcon#about to read 5, iclass 20, count 0 2006.285.09:36:59.39#ibcon#read 5, iclass 20, count 0 2006.285.09:36:59.39#ibcon#about to read 6, iclass 20, count 0 2006.285.09:36:59.39#ibcon#read 6, iclass 20, count 0 2006.285.09:36:59.39#ibcon#end of sib2, iclass 20, count 0 2006.285.09:36:59.39#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:36:59.39#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:36:59.39#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:36:59.39#ibcon#*before write, iclass 20, count 0 2006.285.09:36:59.39#ibcon#enter sib2, iclass 20, count 0 2006.285.09:36:59.39#ibcon#flushed, iclass 20, count 0 2006.285.09:36:59.39#ibcon#about to write, iclass 20, count 0 2006.285.09:36:59.39#ibcon#wrote, iclass 20, count 0 2006.285.09:36:59.39#ibcon#about to read 3, iclass 20, count 0 2006.285.09:36:59.43#ibcon#read 3, iclass 20, count 0 2006.285.09:36:59.43#ibcon#about to read 4, iclass 20, count 0 2006.285.09:36:59.43#ibcon#read 4, iclass 20, count 0 2006.285.09:36:59.43#ibcon#about to read 5, iclass 20, count 0 2006.285.09:36:59.43#ibcon#read 5, iclass 20, count 0 2006.285.09:36:59.43#ibcon#about to read 6, iclass 20, count 0 2006.285.09:36:59.43#ibcon#read 6, iclass 20, count 0 2006.285.09:36:59.43#ibcon#end of sib2, iclass 20, count 0 2006.285.09:36:59.43#ibcon#*after write, iclass 20, count 0 2006.285.09:36:59.43#ibcon#*before return 0, iclass 20, count 0 2006.285.09:36:59.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:36:59.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:36:59.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:36:59.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:36:59.43$vck44/vb=6,3 2006.285.09:36:59.43#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.09:36:59.43#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.09:36:59.43#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:59.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:36:59.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:36:59.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:36:59.49#ibcon#enter wrdev, iclass 22, count 2 2006.285.09:36:59.49#ibcon#first serial, iclass 22, count 2 2006.285.09:36:59.49#ibcon#enter sib2, iclass 22, count 2 2006.285.09:36:59.49#ibcon#flushed, iclass 22, count 2 2006.285.09:36:59.49#ibcon#about to write, iclass 22, count 2 2006.285.09:36:59.49#ibcon#wrote, iclass 22, count 2 2006.285.09:36:59.49#ibcon#about to read 3, iclass 22, count 2 2006.285.09:36:59.51#ibcon#read 3, iclass 22, count 2 2006.285.09:36:59.51#ibcon#about to read 4, iclass 22, count 2 2006.285.09:36:59.51#ibcon#read 4, iclass 22, count 2 2006.285.09:36:59.51#ibcon#about to read 5, iclass 22, count 2 2006.285.09:36:59.51#ibcon#read 5, iclass 22, count 2 2006.285.09:36:59.51#ibcon#about to read 6, iclass 22, count 2 2006.285.09:36:59.51#ibcon#read 6, iclass 22, count 2 2006.285.09:36:59.51#ibcon#end of sib2, iclass 22, count 2 2006.285.09:36:59.51#ibcon#*mode == 0, iclass 22, count 2 2006.285.09:36:59.51#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.09:36:59.51#ibcon#[27=AT06-03\r\n] 2006.285.09:36:59.51#ibcon#*before write, iclass 22, count 2 2006.285.09:36:59.51#ibcon#enter sib2, iclass 22, count 2 2006.285.09:36:59.51#ibcon#flushed, iclass 22, count 2 2006.285.09:36:59.51#ibcon#about to write, iclass 22, count 2 2006.285.09:36:59.51#ibcon#wrote, iclass 22, count 2 2006.285.09:36:59.51#ibcon#about to read 3, iclass 22, count 2 2006.285.09:36:59.54#ibcon#read 3, iclass 22, count 2 2006.285.09:36:59.54#ibcon#about to read 4, iclass 22, count 2 2006.285.09:36:59.54#ibcon#read 4, iclass 22, count 2 2006.285.09:36:59.54#ibcon#about to read 5, iclass 22, count 2 2006.285.09:36:59.54#ibcon#read 5, iclass 22, count 2 2006.285.09:36:59.54#ibcon#about to read 6, iclass 22, count 2 2006.285.09:36:59.54#ibcon#read 6, iclass 22, count 2 2006.285.09:36:59.54#ibcon#end of sib2, iclass 22, count 2 2006.285.09:36:59.54#ibcon#*after write, iclass 22, count 2 2006.285.09:36:59.54#ibcon#*before return 0, iclass 22, count 2 2006.285.09:36:59.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:36:59.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:36:59.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.09:36:59.54#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:59.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:36:59.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:36:59.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:36:59.66#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:36:59.66#ibcon#first serial, iclass 22, count 0 2006.285.09:36:59.66#ibcon#enter sib2, iclass 22, count 0 2006.285.09:36:59.66#ibcon#flushed, iclass 22, count 0 2006.285.09:36:59.66#ibcon#about to write, iclass 22, count 0 2006.285.09:36:59.66#ibcon#wrote, iclass 22, count 0 2006.285.09:36:59.66#ibcon#about to read 3, iclass 22, count 0 2006.285.09:36:59.68#ibcon#read 3, iclass 22, count 0 2006.285.09:36:59.68#ibcon#about to read 4, iclass 22, count 0 2006.285.09:36:59.68#ibcon#read 4, iclass 22, count 0 2006.285.09:36:59.68#ibcon#about to read 5, iclass 22, count 0 2006.285.09:36:59.68#ibcon#read 5, iclass 22, count 0 2006.285.09:36:59.68#ibcon#about to read 6, iclass 22, count 0 2006.285.09:36:59.68#ibcon#read 6, iclass 22, count 0 2006.285.09:36:59.68#ibcon#end of sib2, iclass 22, count 0 2006.285.09:36:59.68#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:36:59.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:36:59.68#ibcon#[27=USB\r\n] 2006.285.09:36:59.68#ibcon#*before write, iclass 22, count 0 2006.285.09:36:59.68#ibcon#enter sib2, iclass 22, count 0 2006.285.09:36:59.68#ibcon#flushed, iclass 22, count 0 2006.285.09:36:59.68#ibcon#about to write, iclass 22, count 0 2006.285.09:36:59.68#ibcon#wrote, iclass 22, count 0 2006.285.09:36:59.68#ibcon#about to read 3, iclass 22, count 0 2006.285.09:36:59.71#ibcon#read 3, iclass 22, count 0 2006.285.09:36:59.71#ibcon#about to read 4, iclass 22, count 0 2006.285.09:36:59.71#ibcon#read 4, iclass 22, count 0 2006.285.09:36:59.71#ibcon#about to read 5, iclass 22, count 0 2006.285.09:36:59.71#ibcon#read 5, iclass 22, count 0 2006.285.09:36:59.71#ibcon#about to read 6, iclass 22, count 0 2006.285.09:36:59.71#ibcon#read 6, iclass 22, count 0 2006.285.09:36:59.71#ibcon#end of sib2, iclass 22, count 0 2006.285.09:36:59.71#ibcon#*after write, iclass 22, count 0 2006.285.09:36:59.71#ibcon#*before return 0, iclass 22, count 0 2006.285.09:36:59.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:36:59.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:36:59.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:36:59.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:36:59.71$vck44/vblo=7,734.99 2006.285.09:36:59.71#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.09:36:59.71#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.09:36:59.71#ibcon#ireg 17 cls_cnt 0 2006.285.09:36:59.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:36:59.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:36:59.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:36:59.71#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:36:59.71#ibcon#first serial, iclass 24, count 0 2006.285.09:36:59.71#ibcon#enter sib2, iclass 24, count 0 2006.285.09:36:59.71#ibcon#flushed, iclass 24, count 0 2006.285.09:36:59.71#ibcon#about to write, iclass 24, count 0 2006.285.09:36:59.71#ibcon#wrote, iclass 24, count 0 2006.285.09:36:59.71#ibcon#about to read 3, iclass 24, count 0 2006.285.09:36:59.73#ibcon#read 3, iclass 24, count 0 2006.285.09:36:59.73#ibcon#about to read 4, iclass 24, count 0 2006.285.09:36:59.73#ibcon#read 4, iclass 24, count 0 2006.285.09:36:59.73#ibcon#about to read 5, iclass 24, count 0 2006.285.09:36:59.73#ibcon#read 5, iclass 24, count 0 2006.285.09:36:59.73#ibcon#about to read 6, iclass 24, count 0 2006.285.09:36:59.73#ibcon#read 6, iclass 24, count 0 2006.285.09:36:59.73#ibcon#end of sib2, iclass 24, count 0 2006.285.09:36:59.73#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:36:59.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:36:59.73#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:36:59.73#ibcon#*before write, iclass 24, count 0 2006.285.09:36:59.73#ibcon#enter sib2, iclass 24, count 0 2006.285.09:36:59.73#ibcon#flushed, iclass 24, count 0 2006.285.09:36:59.73#ibcon#about to write, iclass 24, count 0 2006.285.09:36:59.73#ibcon#wrote, iclass 24, count 0 2006.285.09:36:59.73#ibcon#about to read 3, iclass 24, count 0 2006.285.09:36:59.77#ibcon#read 3, iclass 24, count 0 2006.285.09:36:59.77#ibcon#about to read 4, iclass 24, count 0 2006.285.09:36:59.77#ibcon#read 4, iclass 24, count 0 2006.285.09:36:59.77#ibcon#about to read 5, iclass 24, count 0 2006.285.09:36:59.77#ibcon#read 5, iclass 24, count 0 2006.285.09:36:59.77#ibcon#about to read 6, iclass 24, count 0 2006.285.09:36:59.77#ibcon#read 6, iclass 24, count 0 2006.285.09:36:59.77#ibcon#end of sib2, iclass 24, count 0 2006.285.09:36:59.77#ibcon#*after write, iclass 24, count 0 2006.285.09:36:59.77#ibcon#*before return 0, iclass 24, count 0 2006.285.09:36:59.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:36:59.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:36:59.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:36:59.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:36:59.77$vck44/vb=7,4 2006.285.09:36:59.77#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.09:36:59.77#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.09:36:59.77#ibcon#ireg 11 cls_cnt 2 2006.285.09:36:59.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:36:59.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:36:59.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:36:59.83#ibcon#enter wrdev, iclass 26, count 2 2006.285.09:36:59.83#ibcon#first serial, iclass 26, count 2 2006.285.09:36:59.83#ibcon#enter sib2, iclass 26, count 2 2006.285.09:36:59.83#ibcon#flushed, iclass 26, count 2 2006.285.09:36:59.83#ibcon#about to write, iclass 26, count 2 2006.285.09:36:59.83#ibcon#wrote, iclass 26, count 2 2006.285.09:36:59.83#ibcon#about to read 3, iclass 26, count 2 2006.285.09:36:59.85#ibcon#read 3, iclass 26, count 2 2006.285.09:36:59.85#ibcon#about to read 4, iclass 26, count 2 2006.285.09:36:59.85#ibcon#read 4, iclass 26, count 2 2006.285.09:36:59.85#ibcon#about to read 5, iclass 26, count 2 2006.285.09:36:59.85#ibcon#read 5, iclass 26, count 2 2006.285.09:36:59.85#ibcon#about to read 6, iclass 26, count 2 2006.285.09:36:59.85#ibcon#read 6, iclass 26, count 2 2006.285.09:36:59.85#ibcon#end of sib2, iclass 26, count 2 2006.285.09:36:59.85#ibcon#*mode == 0, iclass 26, count 2 2006.285.09:36:59.85#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.09:36:59.85#ibcon#[27=AT07-04\r\n] 2006.285.09:36:59.85#ibcon#*before write, iclass 26, count 2 2006.285.09:36:59.85#ibcon#enter sib2, iclass 26, count 2 2006.285.09:36:59.85#ibcon#flushed, iclass 26, count 2 2006.285.09:36:59.85#ibcon#about to write, iclass 26, count 2 2006.285.09:36:59.85#ibcon#wrote, iclass 26, count 2 2006.285.09:36:59.85#ibcon#about to read 3, iclass 26, count 2 2006.285.09:36:59.88#ibcon#read 3, iclass 26, count 2 2006.285.09:36:59.88#ibcon#about to read 4, iclass 26, count 2 2006.285.09:36:59.88#ibcon#read 4, iclass 26, count 2 2006.285.09:36:59.88#ibcon#about to read 5, iclass 26, count 2 2006.285.09:36:59.88#ibcon#read 5, iclass 26, count 2 2006.285.09:36:59.88#ibcon#about to read 6, iclass 26, count 2 2006.285.09:36:59.88#ibcon#read 6, iclass 26, count 2 2006.285.09:36:59.88#ibcon#end of sib2, iclass 26, count 2 2006.285.09:36:59.88#ibcon#*after write, iclass 26, count 2 2006.285.09:36:59.88#ibcon#*before return 0, iclass 26, count 2 2006.285.09:36:59.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:36:59.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:36:59.88#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.09:36:59.88#ibcon#ireg 7 cls_cnt 0 2006.285.09:36:59.88#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:37:00.00#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:37:00.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:37:00.00#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:37:00.00#ibcon#first serial, iclass 26, count 0 2006.285.09:37:00.00#ibcon#enter sib2, iclass 26, count 0 2006.285.09:37:00.00#ibcon#flushed, iclass 26, count 0 2006.285.09:37:00.00#ibcon#about to write, iclass 26, count 0 2006.285.09:37:00.00#ibcon#wrote, iclass 26, count 0 2006.285.09:37:00.00#ibcon#about to read 3, iclass 26, count 0 2006.285.09:37:00.02#ibcon#read 3, iclass 26, count 0 2006.285.09:37:00.02#ibcon#about to read 4, iclass 26, count 0 2006.285.09:37:00.02#ibcon#read 4, iclass 26, count 0 2006.285.09:37:00.02#ibcon#about to read 5, iclass 26, count 0 2006.285.09:37:00.02#ibcon#read 5, iclass 26, count 0 2006.285.09:37:00.02#ibcon#about to read 6, iclass 26, count 0 2006.285.09:37:00.02#ibcon#read 6, iclass 26, count 0 2006.285.09:37:00.02#ibcon#end of sib2, iclass 26, count 0 2006.285.09:37:00.02#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:37:00.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:37:00.02#ibcon#[27=USB\r\n] 2006.285.09:37:00.02#ibcon#*before write, iclass 26, count 0 2006.285.09:37:00.02#ibcon#enter sib2, iclass 26, count 0 2006.285.09:37:00.02#ibcon#flushed, iclass 26, count 0 2006.285.09:37:00.02#ibcon#about to write, iclass 26, count 0 2006.285.09:37:00.02#ibcon#wrote, iclass 26, count 0 2006.285.09:37:00.02#ibcon#about to read 3, iclass 26, count 0 2006.285.09:37:00.05#ibcon#read 3, iclass 26, count 0 2006.285.09:37:00.05#ibcon#about to read 4, iclass 26, count 0 2006.285.09:37:00.05#ibcon#read 4, iclass 26, count 0 2006.285.09:37:00.05#ibcon#about to read 5, iclass 26, count 0 2006.285.09:37:00.05#ibcon#read 5, iclass 26, count 0 2006.285.09:37:00.05#ibcon#about to read 6, iclass 26, count 0 2006.285.09:37:00.05#ibcon#read 6, iclass 26, count 0 2006.285.09:37:00.05#ibcon#end of sib2, iclass 26, count 0 2006.285.09:37:00.05#ibcon#*after write, iclass 26, count 0 2006.285.09:37:00.05#ibcon#*before return 0, iclass 26, count 0 2006.285.09:37:00.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:37:00.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:37:00.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:37:00.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:37:00.05$vck44/vblo=8,744.99 2006.285.09:37:00.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.09:37:00.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.09:37:00.05#ibcon#ireg 17 cls_cnt 0 2006.285.09:37:00.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:37:00.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:37:00.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:37:00.05#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:37:00.05#ibcon#first serial, iclass 28, count 0 2006.285.09:37:00.05#ibcon#enter sib2, iclass 28, count 0 2006.285.09:37:00.05#ibcon#flushed, iclass 28, count 0 2006.285.09:37:00.05#ibcon#about to write, iclass 28, count 0 2006.285.09:37:00.05#ibcon#wrote, iclass 28, count 0 2006.285.09:37:00.05#ibcon#about to read 3, iclass 28, count 0 2006.285.09:37:00.07#ibcon#read 3, iclass 28, count 0 2006.285.09:37:00.07#ibcon#about to read 4, iclass 28, count 0 2006.285.09:37:00.07#ibcon#read 4, iclass 28, count 0 2006.285.09:37:00.07#ibcon#about to read 5, iclass 28, count 0 2006.285.09:37:00.07#ibcon#read 5, iclass 28, count 0 2006.285.09:37:00.07#ibcon#about to read 6, iclass 28, count 0 2006.285.09:37:00.07#ibcon#read 6, iclass 28, count 0 2006.285.09:37:00.07#ibcon#end of sib2, iclass 28, count 0 2006.285.09:37:00.07#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:37:00.07#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:37:00.07#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:37:00.07#ibcon#*before write, iclass 28, count 0 2006.285.09:37:00.07#ibcon#enter sib2, iclass 28, count 0 2006.285.09:37:00.07#ibcon#flushed, iclass 28, count 0 2006.285.09:37:00.07#ibcon#about to write, iclass 28, count 0 2006.285.09:37:00.07#ibcon#wrote, iclass 28, count 0 2006.285.09:37:00.07#ibcon#about to read 3, iclass 28, count 0 2006.285.09:37:00.11#ibcon#read 3, iclass 28, count 0 2006.285.09:37:00.11#ibcon#about to read 4, iclass 28, count 0 2006.285.09:37:00.11#ibcon#read 4, iclass 28, count 0 2006.285.09:37:00.11#ibcon#about to read 5, iclass 28, count 0 2006.285.09:37:00.11#ibcon#read 5, iclass 28, count 0 2006.285.09:37:00.11#ibcon#about to read 6, iclass 28, count 0 2006.285.09:37:00.11#ibcon#read 6, iclass 28, count 0 2006.285.09:37:00.11#ibcon#end of sib2, iclass 28, count 0 2006.285.09:37:00.11#ibcon#*after write, iclass 28, count 0 2006.285.09:37:00.11#ibcon#*before return 0, iclass 28, count 0 2006.285.09:37:00.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:37:00.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:37:00.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:37:00.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:37:00.11$vck44/vb=8,4 2006.285.09:37:00.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.09:37:00.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.09:37:00.11#ibcon#ireg 11 cls_cnt 2 2006.285.09:37:00.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:37:00.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:37:00.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:37:00.17#ibcon#enter wrdev, iclass 30, count 2 2006.285.09:37:00.17#ibcon#first serial, iclass 30, count 2 2006.285.09:37:00.17#ibcon#enter sib2, iclass 30, count 2 2006.285.09:37:00.17#ibcon#flushed, iclass 30, count 2 2006.285.09:37:00.17#ibcon#about to write, iclass 30, count 2 2006.285.09:37:00.17#ibcon#wrote, iclass 30, count 2 2006.285.09:37:00.17#ibcon#about to read 3, iclass 30, count 2 2006.285.09:37:00.19#ibcon#read 3, iclass 30, count 2 2006.285.09:37:00.19#ibcon#about to read 4, iclass 30, count 2 2006.285.09:37:00.19#ibcon#read 4, iclass 30, count 2 2006.285.09:37:00.19#ibcon#about to read 5, iclass 30, count 2 2006.285.09:37:00.19#ibcon#read 5, iclass 30, count 2 2006.285.09:37:00.19#ibcon#about to read 6, iclass 30, count 2 2006.285.09:37:00.19#ibcon#read 6, iclass 30, count 2 2006.285.09:37:00.19#ibcon#end of sib2, iclass 30, count 2 2006.285.09:37:00.19#ibcon#*mode == 0, iclass 30, count 2 2006.285.09:37:00.19#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.09:37:00.19#ibcon#[27=AT08-04\r\n] 2006.285.09:37:00.19#ibcon#*before write, iclass 30, count 2 2006.285.09:37:00.19#ibcon#enter sib2, iclass 30, count 2 2006.285.09:37:00.19#ibcon#flushed, iclass 30, count 2 2006.285.09:37:00.19#ibcon#about to write, iclass 30, count 2 2006.285.09:37:00.19#ibcon#wrote, iclass 30, count 2 2006.285.09:37:00.19#ibcon#about to read 3, iclass 30, count 2 2006.285.09:37:00.22#ibcon#read 3, iclass 30, count 2 2006.285.09:37:00.22#ibcon#about to read 4, iclass 30, count 2 2006.285.09:37:00.22#ibcon#read 4, iclass 30, count 2 2006.285.09:37:00.22#ibcon#about to read 5, iclass 30, count 2 2006.285.09:37:00.22#ibcon#read 5, iclass 30, count 2 2006.285.09:37:00.22#ibcon#about to read 6, iclass 30, count 2 2006.285.09:37:00.22#ibcon#read 6, iclass 30, count 2 2006.285.09:37:00.22#ibcon#end of sib2, iclass 30, count 2 2006.285.09:37:00.22#ibcon#*after write, iclass 30, count 2 2006.285.09:37:00.22#ibcon#*before return 0, iclass 30, count 2 2006.285.09:37:00.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:37:00.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:37:00.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.09:37:00.22#ibcon#ireg 7 cls_cnt 0 2006.285.09:37:00.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:37:00.34#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:37:00.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:37:00.34#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:37:00.34#ibcon#first serial, iclass 30, count 0 2006.285.09:37:00.34#ibcon#enter sib2, iclass 30, count 0 2006.285.09:37:00.34#ibcon#flushed, iclass 30, count 0 2006.285.09:37:00.34#ibcon#about to write, iclass 30, count 0 2006.285.09:37:00.34#ibcon#wrote, iclass 30, count 0 2006.285.09:37:00.34#ibcon#about to read 3, iclass 30, count 0 2006.285.09:37:00.36#ibcon#read 3, iclass 30, count 0 2006.285.09:37:00.36#ibcon#about to read 4, iclass 30, count 0 2006.285.09:37:00.36#ibcon#read 4, iclass 30, count 0 2006.285.09:37:00.36#ibcon#about to read 5, iclass 30, count 0 2006.285.09:37:00.36#ibcon#read 5, iclass 30, count 0 2006.285.09:37:00.36#ibcon#about to read 6, iclass 30, count 0 2006.285.09:37:00.36#ibcon#read 6, iclass 30, count 0 2006.285.09:37:00.36#ibcon#end of sib2, iclass 30, count 0 2006.285.09:37:00.36#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:37:00.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:37:00.36#ibcon#[27=USB\r\n] 2006.285.09:37:00.36#ibcon#*before write, iclass 30, count 0 2006.285.09:37:00.36#ibcon#enter sib2, iclass 30, count 0 2006.285.09:37:00.36#ibcon#flushed, iclass 30, count 0 2006.285.09:37:00.36#ibcon#about to write, iclass 30, count 0 2006.285.09:37:00.36#ibcon#wrote, iclass 30, count 0 2006.285.09:37:00.36#ibcon#about to read 3, iclass 30, count 0 2006.285.09:37:00.39#ibcon#read 3, iclass 30, count 0 2006.285.09:37:00.39#ibcon#about to read 4, iclass 30, count 0 2006.285.09:37:00.39#ibcon#read 4, iclass 30, count 0 2006.285.09:37:00.39#ibcon#about to read 5, iclass 30, count 0 2006.285.09:37:00.39#ibcon#read 5, iclass 30, count 0 2006.285.09:37:00.39#ibcon#about to read 6, iclass 30, count 0 2006.285.09:37:00.39#ibcon#read 6, iclass 30, count 0 2006.285.09:37:00.39#ibcon#end of sib2, iclass 30, count 0 2006.285.09:37:00.39#ibcon#*after write, iclass 30, count 0 2006.285.09:37:00.39#ibcon#*before return 0, iclass 30, count 0 2006.285.09:37:00.39#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:37:00.39#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:37:00.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:37:00.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:37:00.39$vck44/vabw=wide 2006.285.09:37:00.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.09:37:00.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.09:37:00.39#ibcon#ireg 8 cls_cnt 0 2006.285.09:37:00.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:37:00.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:37:00.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:37:00.39#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:37:00.39#ibcon#first serial, iclass 32, count 0 2006.285.09:37:00.39#ibcon#enter sib2, iclass 32, count 0 2006.285.09:37:00.39#ibcon#flushed, iclass 32, count 0 2006.285.09:37:00.39#ibcon#about to write, iclass 32, count 0 2006.285.09:37:00.39#ibcon#wrote, iclass 32, count 0 2006.285.09:37:00.39#ibcon#about to read 3, iclass 32, count 0 2006.285.09:37:00.41#ibcon#read 3, iclass 32, count 0 2006.285.09:37:00.41#ibcon#about to read 4, iclass 32, count 0 2006.285.09:37:00.41#ibcon#read 4, iclass 32, count 0 2006.285.09:37:00.41#ibcon#about to read 5, iclass 32, count 0 2006.285.09:37:00.41#ibcon#read 5, iclass 32, count 0 2006.285.09:37:00.41#ibcon#about to read 6, iclass 32, count 0 2006.285.09:37:00.41#ibcon#read 6, iclass 32, count 0 2006.285.09:37:00.41#ibcon#end of sib2, iclass 32, count 0 2006.285.09:37:00.41#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:37:00.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:37:00.41#ibcon#[25=BW32\r\n] 2006.285.09:37:00.41#ibcon#*before write, iclass 32, count 0 2006.285.09:37:00.41#ibcon#enter sib2, iclass 32, count 0 2006.285.09:37:00.41#ibcon#flushed, iclass 32, count 0 2006.285.09:37:00.41#ibcon#about to write, iclass 32, count 0 2006.285.09:37:00.41#ibcon#wrote, iclass 32, count 0 2006.285.09:37:00.41#ibcon#about to read 3, iclass 32, count 0 2006.285.09:37:00.44#ibcon#read 3, iclass 32, count 0 2006.285.09:37:00.44#ibcon#about to read 4, iclass 32, count 0 2006.285.09:37:00.44#ibcon#read 4, iclass 32, count 0 2006.285.09:37:00.44#ibcon#about to read 5, iclass 32, count 0 2006.285.09:37:00.44#ibcon#read 5, iclass 32, count 0 2006.285.09:37:00.44#ibcon#about to read 6, iclass 32, count 0 2006.285.09:37:00.44#ibcon#read 6, iclass 32, count 0 2006.285.09:37:00.44#ibcon#end of sib2, iclass 32, count 0 2006.285.09:37:00.44#ibcon#*after write, iclass 32, count 0 2006.285.09:37:00.44#ibcon#*before return 0, iclass 32, count 0 2006.285.09:37:00.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:37:00.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:37:00.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:37:00.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:37:00.44$vck44/vbbw=wide 2006.285.09:37:00.44#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.09:37:00.44#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.09:37:00.44#ibcon#ireg 8 cls_cnt 0 2006.285.09:37:00.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:37:00.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:37:00.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:37:00.51#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:37:00.51#ibcon#first serial, iclass 34, count 0 2006.285.09:37:00.51#ibcon#enter sib2, iclass 34, count 0 2006.285.09:37:00.51#ibcon#flushed, iclass 34, count 0 2006.285.09:37:00.51#ibcon#about to write, iclass 34, count 0 2006.285.09:37:00.51#ibcon#wrote, iclass 34, count 0 2006.285.09:37:00.51#ibcon#about to read 3, iclass 34, count 0 2006.285.09:37:00.53#ibcon#read 3, iclass 34, count 0 2006.285.09:37:00.53#ibcon#about to read 4, iclass 34, count 0 2006.285.09:37:00.53#ibcon#read 4, iclass 34, count 0 2006.285.09:37:00.53#ibcon#about to read 5, iclass 34, count 0 2006.285.09:37:00.53#ibcon#read 5, iclass 34, count 0 2006.285.09:37:00.53#ibcon#about to read 6, iclass 34, count 0 2006.285.09:37:00.53#ibcon#read 6, iclass 34, count 0 2006.285.09:37:00.53#ibcon#end of sib2, iclass 34, count 0 2006.285.09:37:00.53#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:37:00.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:37:00.53#ibcon#[27=BW32\r\n] 2006.285.09:37:00.53#ibcon#*before write, iclass 34, count 0 2006.285.09:37:00.53#ibcon#enter sib2, iclass 34, count 0 2006.285.09:37:00.53#ibcon#flushed, iclass 34, count 0 2006.285.09:37:00.53#ibcon#about to write, iclass 34, count 0 2006.285.09:37:00.53#ibcon#wrote, iclass 34, count 0 2006.285.09:37:00.53#ibcon#about to read 3, iclass 34, count 0 2006.285.09:37:00.56#ibcon#read 3, iclass 34, count 0 2006.285.09:37:00.56#ibcon#about to read 4, iclass 34, count 0 2006.285.09:37:00.56#ibcon#read 4, iclass 34, count 0 2006.285.09:37:00.56#ibcon#about to read 5, iclass 34, count 0 2006.285.09:37:00.56#ibcon#read 5, iclass 34, count 0 2006.285.09:37:00.56#ibcon#about to read 6, iclass 34, count 0 2006.285.09:37:00.56#ibcon#read 6, iclass 34, count 0 2006.285.09:37:00.56#ibcon#end of sib2, iclass 34, count 0 2006.285.09:37:00.56#ibcon#*after write, iclass 34, count 0 2006.285.09:37:00.56#ibcon#*before return 0, iclass 34, count 0 2006.285.09:37:00.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:37:00.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:37:00.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:37:00.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:37:00.56$setupk4/ifdk4 2006.285.09:37:00.56$ifdk4/lo= 2006.285.09:37:00.56$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:37:00.56$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:37:00.56$ifdk4/patch= 2006.285.09:37:00.56$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:37:00.56$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:37:00.56$setupk4/!*+20s 2006.285.09:37:03.48#abcon#<5=/03 0.8 1.3 19.42 931015.1\r\n> 2006.285.09:37:03.50#abcon#{5=INTERFACE CLEAR} 2006.285.09:37:03.56#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:37:13.65#abcon#<5=/03 0.8 1.3 19.42 931015.1\r\n> 2006.285.09:37:13.67#abcon#{5=INTERFACE CLEAR} 2006.285.09:37:13.73#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:37:15.07$setupk4/"tpicd 2006.285.09:37:15.07$setupk4/echo=off 2006.285.09:37:15.07$setupk4/xlog=off 2006.285.09:37:15.07:!2006.285.09:41:08 2006.285.09:37:17.14#trakl#Source acquired 2006.285.09:37:17.14#flagr#flagr/antenna,acquired 2006.285.09:41:08.00:preob 2006.285.09:41:09.14/onsource/TRACKING 2006.285.09:41:09.14:!2006.285.09:41:18 2006.285.09:41:18.00:"tape 2006.285.09:41:18.00:"st=record 2006.285.09:41:18.00:data_valid=on 2006.285.09:41:18.00:midob 2006.285.09:41:18.14/onsource/TRACKING 2006.285.09:41:18.14/wx/19.37,1015.1,94 2006.285.09:41:18.31/cable/+6.4822E-03 2006.285.09:41:19.40/va/01,07,usb,yes,31,34 2006.285.09:41:19.40/va/02,06,usb,yes,31,32 2006.285.09:41:19.40/va/03,07,usb,yes,31,33 2006.285.09:41:19.40/va/04,06,usb,yes,32,34 2006.285.09:41:19.40/va/05,03,usb,yes,32,32 2006.285.09:41:19.40/va/06,04,usb,yes,29,28 2006.285.09:41:19.40/va/07,04,usb,yes,29,30 2006.285.09:41:19.40/va/08,03,usb,yes,30,36 2006.285.09:41:19.63/valo/01,524.99,yes,locked 2006.285.09:41:19.63/valo/02,534.99,yes,locked 2006.285.09:41:19.63/valo/03,564.99,yes,locked 2006.285.09:41:19.63/valo/04,624.99,yes,locked 2006.285.09:41:19.63/valo/05,734.99,yes,locked 2006.285.09:41:19.63/valo/06,814.99,yes,locked 2006.285.09:41:19.63/valo/07,864.99,yes,locked 2006.285.09:41:19.63/valo/08,884.99,yes,locked 2006.285.09:41:20.72/vb/01,04,usb,yes,30,28 2006.285.09:41:20.72/vb/02,05,usb,yes,28,28 2006.285.09:41:20.72/vb/03,04,usb,yes,29,32 2006.285.09:41:20.72/vb/04,05,usb,yes,30,29 2006.285.09:41:20.72/vb/05,04,usb,yes,26,28 2006.285.09:41:20.72/vb/06,03,usb,yes,37,33 2006.285.09:41:20.72/vb/07,04,usb,yes,30,30 2006.285.09:41:20.72/vb/08,04,usb,yes,27,31 2006.285.09:41:20.96/vblo/01,629.99,yes,locked 2006.285.09:41:20.96/vblo/02,634.99,yes,locked 2006.285.09:41:20.96/vblo/03,649.99,yes,locked 2006.285.09:41:20.96/vblo/04,679.99,yes,locked 2006.285.09:41:20.96/vblo/05,709.99,yes,locked 2006.285.09:41:20.96/vblo/06,719.99,yes,locked 2006.285.09:41:20.96/vblo/07,734.99,yes,locked 2006.285.09:41:20.96/vblo/08,744.99,yes,locked 2006.285.09:41:21.11/vabw/8 2006.285.09:41:21.26/vbbw/8 2006.285.09:41:21.35/xfe/off,on,12.2 2006.285.09:41:21.74/ifatt/23,28,28,28 2006.285.09:41:22.08/fmout-gps/S +2.54E-07 2006.285.09:41:22.10:!2006.285.09:43:58 2006.285.09:43:58.00:data_valid=off 2006.285.09:43:58.00:"et 2006.285.09:43:58.00:!+3s 2006.285.09:44:01.01:"tape 2006.285.09:44:01.01:postob 2006.285.09:44:01.15/cable/+6.4819E-03 2006.285.09:44:01.15/wx/19.38,1015.2,95 2006.285.09:44:02.08/fmout-gps/S +2.51E-07 2006.285.09:44:02.08:scan_name=285-0950,jd0610,40 2006.285.09:44:02.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.285.09:44:03.14#flagr#flagr/antenna,new-source 2006.285.09:44:03.14:checkk5 2006.285.09:44:03.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:44:03.95/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:44:04.36/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:44:04.92/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:44:05.40/chk_obsdata//k5ts1/T2850941??a.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.09:44:05.76/chk_obsdata//k5ts2/T2850941??b.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.09:44:06.19/chk_obsdata//k5ts3/T2850941??c.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.09:44:06.64/chk_obsdata//k5ts4/T2850941??d.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.09:44:07.64/k5log//k5ts1_log_newline 2006.285.09:44:08.59/k5log//k5ts2_log_newline 2006.285.09:44:09.32/k5log//k5ts3_log_newline 2006.285.09:44:10.12/k5log//k5ts4_log_newline 2006.285.09:44:10.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:44:10.14:setupk4=1 2006.285.09:44:10.14$setupk4/echo=on 2006.285.09:44:10.14$setupk4/pcalon 2006.285.09:44:10.14$pcalon/"no phase cal control is implemented here 2006.285.09:44:10.14$setupk4/"tpicd=stop 2006.285.09:44:10.14$setupk4/"rec=synch_on 2006.285.09:44:10.15$setupk4/"rec_mode=128 2006.285.09:44:10.15$setupk4/!* 2006.285.09:44:10.15$setupk4/recpk4 2006.285.09:44:10.15$recpk4/recpatch= 2006.285.09:44:10.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:44:10.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:44:10.15$setupk4/vck44 2006.285.09:44:10.15$vck44/valo=1,524.99 2006.285.09:44:10.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.09:44:10.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.09:44:10.15#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:10.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:44:10.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:44:10.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:44:10.15#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:44:10.15#ibcon#first serial, iclass 22, count 0 2006.285.09:44:10.15#ibcon#enter sib2, iclass 22, count 0 2006.285.09:44:10.15#ibcon#flushed, iclass 22, count 0 2006.285.09:44:10.15#ibcon#about to write, iclass 22, count 0 2006.285.09:44:10.15#ibcon#wrote, iclass 22, count 0 2006.285.09:44:10.15#ibcon#about to read 3, iclass 22, count 0 2006.285.09:44:10.17#ibcon#read 3, iclass 22, count 0 2006.285.09:44:10.17#ibcon#about to read 4, iclass 22, count 0 2006.285.09:44:10.17#ibcon#read 4, iclass 22, count 0 2006.285.09:44:10.17#ibcon#about to read 5, iclass 22, count 0 2006.285.09:44:10.17#ibcon#read 5, iclass 22, count 0 2006.285.09:44:10.17#ibcon#about to read 6, iclass 22, count 0 2006.285.09:44:10.17#ibcon#read 6, iclass 22, count 0 2006.285.09:44:10.17#ibcon#end of sib2, iclass 22, count 0 2006.285.09:44:10.17#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:44:10.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:44:10.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:44:10.17#ibcon#*before write, iclass 22, count 0 2006.285.09:44:10.17#ibcon#enter sib2, iclass 22, count 0 2006.285.09:44:10.17#ibcon#flushed, iclass 22, count 0 2006.285.09:44:10.17#ibcon#about to write, iclass 22, count 0 2006.285.09:44:10.17#ibcon#wrote, iclass 22, count 0 2006.285.09:44:10.17#ibcon#about to read 3, iclass 22, count 0 2006.285.09:44:10.22#ibcon#read 3, iclass 22, count 0 2006.285.09:44:10.22#ibcon#about to read 4, iclass 22, count 0 2006.285.09:44:10.22#ibcon#read 4, iclass 22, count 0 2006.285.09:44:10.22#ibcon#about to read 5, iclass 22, count 0 2006.285.09:44:10.22#ibcon#read 5, iclass 22, count 0 2006.285.09:44:10.22#ibcon#about to read 6, iclass 22, count 0 2006.285.09:44:10.22#ibcon#read 6, iclass 22, count 0 2006.285.09:44:10.22#ibcon#end of sib2, iclass 22, count 0 2006.285.09:44:10.22#ibcon#*after write, iclass 22, count 0 2006.285.09:44:10.22#ibcon#*before return 0, iclass 22, count 0 2006.285.09:44:10.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:44:10.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:44:10.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:44:10.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:44:10.22$vck44/va=1,7 2006.285.09:44:10.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.09:44:10.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.09:44:10.22#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:10.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:44:10.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:44:10.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:44:10.22#ibcon#enter wrdev, iclass 24, count 2 2006.285.09:44:10.22#ibcon#first serial, iclass 24, count 2 2006.285.09:44:10.22#ibcon#enter sib2, iclass 24, count 2 2006.285.09:44:10.22#ibcon#flushed, iclass 24, count 2 2006.285.09:44:10.22#ibcon#about to write, iclass 24, count 2 2006.285.09:44:10.22#ibcon#wrote, iclass 24, count 2 2006.285.09:44:10.22#ibcon#about to read 3, iclass 24, count 2 2006.285.09:44:10.24#ibcon#read 3, iclass 24, count 2 2006.285.09:44:10.24#ibcon#about to read 4, iclass 24, count 2 2006.285.09:44:10.24#ibcon#read 4, iclass 24, count 2 2006.285.09:44:10.24#ibcon#about to read 5, iclass 24, count 2 2006.285.09:44:10.24#ibcon#read 5, iclass 24, count 2 2006.285.09:44:10.24#ibcon#about to read 6, iclass 24, count 2 2006.285.09:44:10.24#ibcon#read 6, iclass 24, count 2 2006.285.09:44:10.24#ibcon#end of sib2, iclass 24, count 2 2006.285.09:44:10.24#ibcon#*mode == 0, iclass 24, count 2 2006.285.09:44:10.24#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.09:44:10.24#ibcon#[25=AT01-07\r\n] 2006.285.09:44:10.24#ibcon#*before write, iclass 24, count 2 2006.285.09:44:10.24#ibcon#enter sib2, iclass 24, count 2 2006.285.09:44:10.24#ibcon#flushed, iclass 24, count 2 2006.285.09:44:10.24#ibcon#about to write, iclass 24, count 2 2006.285.09:44:10.24#ibcon#wrote, iclass 24, count 2 2006.285.09:44:10.24#ibcon#about to read 3, iclass 24, count 2 2006.285.09:44:10.27#ibcon#read 3, iclass 24, count 2 2006.285.09:44:10.27#ibcon#about to read 4, iclass 24, count 2 2006.285.09:44:10.27#ibcon#read 4, iclass 24, count 2 2006.285.09:44:10.27#ibcon#about to read 5, iclass 24, count 2 2006.285.09:44:10.27#ibcon#read 5, iclass 24, count 2 2006.285.09:44:10.27#ibcon#about to read 6, iclass 24, count 2 2006.285.09:44:10.27#ibcon#read 6, iclass 24, count 2 2006.285.09:44:10.27#ibcon#end of sib2, iclass 24, count 2 2006.285.09:44:10.27#ibcon#*after write, iclass 24, count 2 2006.285.09:44:10.27#ibcon#*before return 0, iclass 24, count 2 2006.285.09:44:10.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:44:10.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:44:10.27#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.09:44:10.27#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:10.27#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:44:10.39#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:44:10.39#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:44:10.39#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:44:10.39#ibcon#first serial, iclass 24, count 0 2006.285.09:44:10.39#ibcon#enter sib2, iclass 24, count 0 2006.285.09:44:10.39#ibcon#flushed, iclass 24, count 0 2006.285.09:44:10.39#ibcon#about to write, iclass 24, count 0 2006.285.09:44:10.39#ibcon#wrote, iclass 24, count 0 2006.285.09:44:10.39#ibcon#about to read 3, iclass 24, count 0 2006.285.09:44:10.41#ibcon#read 3, iclass 24, count 0 2006.285.09:44:10.41#ibcon#about to read 4, iclass 24, count 0 2006.285.09:44:10.41#ibcon#read 4, iclass 24, count 0 2006.285.09:44:10.41#ibcon#about to read 5, iclass 24, count 0 2006.285.09:44:10.41#ibcon#read 5, iclass 24, count 0 2006.285.09:44:10.41#ibcon#about to read 6, iclass 24, count 0 2006.285.09:44:10.41#ibcon#read 6, iclass 24, count 0 2006.285.09:44:10.41#ibcon#end of sib2, iclass 24, count 0 2006.285.09:44:10.41#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:44:10.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:44:10.41#ibcon#[25=USB\r\n] 2006.285.09:44:10.41#ibcon#*before write, iclass 24, count 0 2006.285.09:44:10.41#ibcon#enter sib2, iclass 24, count 0 2006.285.09:44:10.41#ibcon#flushed, iclass 24, count 0 2006.285.09:44:10.41#ibcon#about to write, iclass 24, count 0 2006.285.09:44:10.41#ibcon#wrote, iclass 24, count 0 2006.285.09:44:10.41#ibcon#about to read 3, iclass 24, count 0 2006.285.09:44:10.44#ibcon#read 3, iclass 24, count 0 2006.285.09:44:10.44#ibcon#about to read 4, iclass 24, count 0 2006.285.09:44:10.44#ibcon#read 4, iclass 24, count 0 2006.285.09:44:10.44#ibcon#about to read 5, iclass 24, count 0 2006.285.09:44:10.44#ibcon#read 5, iclass 24, count 0 2006.285.09:44:10.44#ibcon#about to read 6, iclass 24, count 0 2006.285.09:44:10.44#ibcon#read 6, iclass 24, count 0 2006.285.09:44:10.44#ibcon#end of sib2, iclass 24, count 0 2006.285.09:44:10.44#ibcon#*after write, iclass 24, count 0 2006.285.09:44:10.44#ibcon#*before return 0, iclass 24, count 0 2006.285.09:44:10.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:44:10.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:44:10.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:44:10.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:44:10.44$vck44/valo=2,534.99 2006.285.09:44:10.44#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.09:44:10.44#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.09:44:10.44#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:10.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:44:10.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:44:10.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:44:10.44#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:44:10.44#ibcon#first serial, iclass 26, count 0 2006.285.09:44:10.44#ibcon#enter sib2, iclass 26, count 0 2006.285.09:44:10.44#ibcon#flushed, iclass 26, count 0 2006.285.09:44:10.44#ibcon#about to write, iclass 26, count 0 2006.285.09:44:10.44#ibcon#wrote, iclass 26, count 0 2006.285.09:44:10.44#ibcon#about to read 3, iclass 26, count 0 2006.285.09:44:10.46#ibcon#read 3, iclass 26, count 0 2006.285.09:44:10.46#ibcon#about to read 4, iclass 26, count 0 2006.285.09:44:10.46#ibcon#read 4, iclass 26, count 0 2006.285.09:44:10.46#ibcon#about to read 5, iclass 26, count 0 2006.285.09:44:10.46#ibcon#read 5, iclass 26, count 0 2006.285.09:44:10.46#ibcon#about to read 6, iclass 26, count 0 2006.285.09:44:10.46#ibcon#read 6, iclass 26, count 0 2006.285.09:44:10.46#ibcon#end of sib2, iclass 26, count 0 2006.285.09:44:10.46#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:44:10.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:44:10.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:44:10.46#ibcon#*before write, iclass 26, count 0 2006.285.09:44:10.46#ibcon#enter sib2, iclass 26, count 0 2006.285.09:44:10.46#ibcon#flushed, iclass 26, count 0 2006.285.09:44:10.46#ibcon#about to write, iclass 26, count 0 2006.285.09:44:10.46#ibcon#wrote, iclass 26, count 0 2006.285.09:44:10.46#ibcon#about to read 3, iclass 26, count 0 2006.285.09:44:10.50#ibcon#read 3, iclass 26, count 0 2006.285.09:44:10.50#ibcon#about to read 4, iclass 26, count 0 2006.285.09:44:10.50#ibcon#read 4, iclass 26, count 0 2006.285.09:44:10.50#ibcon#about to read 5, iclass 26, count 0 2006.285.09:44:10.50#ibcon#read 5, iclass 26, count 0 2006.285.09:44:10.50#ibcon#about to read 6, iclass 26, count 0 2006.285.09:44:10.50#ibcon#read 6, iclass 26, count 0 2006.285.09:44:10.50#ibcon#end of sib2, iclass 26, count 0 2006.285.09:44:10.50#ibcon#*after write, iclass 26, count 0 2006.285.09:44:10.50#ibcon#*before return 0, iclass 26, count 0 2006.285.09:44:10.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:44:10.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:44:10.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:44:10.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:44:10.50$vck44/va=2,6 2006.285.09:44:10.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.09:44:10.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.09:44:10.50#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:10.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:44:10.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:44:10.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:44:10.56#ibcon#enter wrdev, iclass 28, count 2 2006.285.09:44:10.56#ibcon#first serial, iclass 28, count 2 2006.285.09:44:10.56#ibcon#enter sib2, iclass 28, count 2 2006.285.09:44:10.56#ibcon#flushed, iclass 28, count 2 2006.285.09:44:10.56#ibcon#about to write, iclass 28, count 2 2006.285.09:44:10.56#ibcon#wrote, iclass 28, count 2 2006.285.09:44:10.56#ibcon#about to read 3, iclass 28, count 2 2006.285.09:44:10.58#ibcon#read 3, iclass 28, count 2 2006.285.09:44:10.58#ibcon#about to read 4, iclass 28, count 2 2006.285.09:44:10.58#ibcon#read 4, iclass 28, count 2 2006.285.09:44:10.58#ibcon#about to read 5, iclass 28, count 2 2006.285.09:44:10.58#ibcon#read 5, iclass 28, count 2 2006.285.09:44:10.58#ibcon#about to read 6, iclass 28, count 2 2006.285.09:44:10.58#ibcon#read 6, iclass 28, count 2 2006.285.09:44:10.58#ibcon#end of sib2, iclass 28, count 2 2006.285.09:44:10.58#ibcon#*mode == 0, iclass 28, count 2 2006.285.09:44:10.58#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.09:44:10.58#ibcon#[25=AT02-06\r\n] 2006.285.09:44:10.58#ibcon#*before write, iclass 28, count 2 2006.285.09:44:10.58#ibcon#enter sib2, iclass 28, count 2 2006.285.09:44:10.58#ibcon#flushed, iclass 28, count 2 2006.285.09:44:10.58#ibcon#about to write, iclass 28, count 2 2006.285.09:44:10.58#ibcon#wrote, iclass 28, count 2 2006.285.09:44:10.58#ibcon#about to read 3, iclass 28, count 2 2006.285.09:44:10.61#ibcon#read 3, iclass 28, count 2 2006.285.09:44:10.61#ibcon#about to read 4, iclass 28, count 2 2006.285.09:44:10.61#ibcon#read 4, iclass 28, count 2 2006.285.09:44:10.61#ibcon#about to read 5, iclass 28, count 2 2006.285.09:44:10.61#ibcon#read 5, iclass 28, count 2 2006.285.09:44:10.61#ibcon#about to read 6, iclass 28, count 2 2006.285.09:44:10.61#ibcon#read 6, iclass 28, count 2 2006.285.09:44:10.61#ibcon#end of sib2, iclass 28, count 2 2006.285.09:44:10.61#ibcon#*after write, iclass 28, count 2 2006.285.09:44:10.61#ibcon#*before return 0, iclass 28, count 2 2006.285.09:44:10.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:44:10.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:44:10.61#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.09:44:10.61#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:10.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:44:10.73#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:44:10.73#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:44:10.73#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:44:10.73#ibcon#first serial, iclass 28, count 0 2006.285.09:44:10.73#ibcon#enter sib2, iclass 28, count 0 2006.285.09:44:10.73#ibcon#flushed, iclass 28, count 0 2006.285.09:44:10.73#ibcon#about to write, iclass 28, count 0 2006.285.09:44:10.73#ibcon#wrote, iclass 28, count 0 2006.285.09:44:10.73#ibcon#about to read 3, iclass 28, count 0 2006.285.09:44:10.75#ibcon#read 3, iclass 28, count 0 2006.285.09:44:10.75#ibcon#about to read 4, iclass 28, count 0 2006.285.09:44:10.75#ibcon#read 4, iclass 28, count 0 2006.285.09:44:10.75#ibcon#about to read 5, iclass 28, count 0 2006.285.09:44:10.75#ibcon#read 5, iclass 28, count 0 2006.285.09:44:10.75#ibcon#about to read 6, iclass 28, count 0 2006.285.09:44:10.75#ibcon#read 6, iclass 28, count 0 2006.285.09:44:10.75#ibcon#end of sib2, iclass 28, count 0 2006.285.09:44:10.75#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:44:10.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:44:10.75#ibcon#[25=USB\r\n] 2006.285.09:44:10.75#ibcon#*before write, iclass 28, count 0 2006.285.09:44:10.75#ibcon#enter sib2, iclass 28, count 0 2006.285.09:44:10.75#ibcon#flushed, iclass 28, count 0 2006.285.09:44:10.75#ibcon#about to write, iclass 28, count 0 2006.285.09:44:10.75#ibcon#wrote, iclass 28, count 0 2006.285.09:44:10.75#ibcon#about to read 3, iclass 28, count 0 2006.285.09:44:10.78#ibcon#read 3, iclass 28, count 0 2006.285.09:44:10.78#ibcon#about to read 4, iclass 28, count 0 2006.285.09:44:10.78#ibcon#read 4, iclass 28, count 0 2006.285.09:44:10.78#ibcon#about to read 5, iclass 28, count 0 2006.285.09:44:10.78#ibcon#read 5, iclass 28, count 0 2006.285.09:44:10.78#ibcon#about to read 6, iclass 28, count 0 2006.285.09:44:10.78#ibcon#read 6, iclass 28, count 0 2006.285.09:44:10.78#ibcon#end of sib2, iclass 28, count 0 2006.285.09:44:10.78#ibcon#*after write, iclass 28, count 0 2006.285.09:44:10.78#ibcon#*before return 0, iclass 28, count 0 2006.285.09:44:10.78#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:44:10.78#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:44:10.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:44:10.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:44:10.78$vck44/valo=3,564.99 2006.285.09:44:10.78#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.09:44:10.78#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.09:44:10.78#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:10.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:44:10.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:44:10.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:44:10.78#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:44:10.78#ibcon#first serial, iclass 30, count 0 2006.285.09:44:10.78#ibcon#enter sib2, iclass 30, count 0 2006.285.09:44:10.78#ibcon#flushed, iclass 30, count 0 2006.285.09:44:10.78#ibcon#about to write, iclass 30, count 0 2006.285.09:44:10.78#ibcon#wrote, iclass 30, count 0 2006.285.09:44:10.78#ibcon#about to read 3, iclass 30, count 0 2006.285.09:44:10.80#ibcon#read 3, iclass 30, count 0 2006.285.09:44:10.80#ibcon#about to read 4, iclass 30, count 0 2006.285.09:44:10.80#ibcon#read 4, iclass 30, count 0 2006.285.09:44:10.80#ibcon#about to read 5, iclass 30, count 0 2006.285.09:44:10.80#ibcon#read 5, iclass 30, count 0 2006.285.09:44:10.80#ibcon#about to read 6, iclass 30, count 0 2006.285.09:44:10.80#ibcon#read 6, iclass 30, count 0 2006.285.09:44:10.80#ibcon#end of sib2, iclass 30, count 0 2006.285.09:44:10.80#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:44:10.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:44:10.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:44:10.80#ibcon#*before write, iclass 30, count 0 2006.285.09:44:10.80#ibcon#enter sib2, iclass 30, count 0 2006.285.09:44:10.80#ibcon#flushed, iclass 30, count 0 2006.285.09:44:10.80#ibcon#about to write, iclass 30, count 0 2006.285.09:44:10.80#ibcon#wrote, iclass 30, count 0 2006.285.09:44:10.80#ibcon#about to read 3, iclass 30, count 0 2006.285.09:44:10.84#ibcon#read 3, iclass 30, count 0 2006.285.09:44:10.84#ibcon#about to read 4, iclass 30, count 0 2006.285.09:44:10.84#ibcon#read 4, iclass 30, count 0 2006.285.09:44:10.84#ibcon#about to read 5, iclass 30, count 0 2006.285.09:44:10.84#ibcon#read 5, iclass 30, count 0 2006.285.09:44:10.84#ibcon#about to read 6, iclass 30, count 0 2006.285.09:44:10.84#ibcon#read 6, iclass 30, count 0 2006.285.09:44:10.84#ibcon#end of sib2, iclass 30, count 0 2006.285.09:44:10.84#ibcon#*after write, iclass 30, count 0 2006.285.09:44:10.84#ibcon#*before return 0, iclass 30, count 0 2006.285.09:44:10.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:44:10.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:44:10.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:44:10.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:44:10.84$vck44/va=3,7 2006.285.09:44:10.84#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.09:44:10.84#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.09:44:10.84#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:10.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:44:10.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:44:10.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:44:10.90#ibcon#enter wrdev, iclass 32, count 2 2006.285.09:44:10.90#ibcon#first serial, iclass 32, count 2 2006.285.09:44:10.90#ibcon#enter sib2, iclass 32, count 2 2006.285.09:44:10.90#ibcon#flushed, iclass 32, count 2 2006.285.09:44:10.90#ibcon#about to write, iclass 32, count 2 2006.285.09:44:10.90#ibcon#wrote, iclass 32, count 2 2006.285.09:44:10.90#ibcon#about to read 3, iclass 32, count 2 2006.285.09:44:10.92#ibcon#read 3, iclass 32, count 2 2006.285.09:44:10.92#ibcon#about to read 4, iclass 32, count 2 2006.285.09:44:10.92#ibcon#read 4, iclass 32, count 2 2006.285.09:44:10.92#ibcon#about to read 5, iclass 32, count 2 2006.285.09:44:10.92#ibcon#read 5, iclass 32, count 2 2006.285.09:44:10.92#ibcon#about to read 6, iclass 32, count 2 2006.285.09:44:10.92#ibcon#read 6, iclass 32, count 2 2006.285.09:44:10.92#ibcon#end of sib2, iclass 32, count 2 2006.285.09:44:10.92#ibcon#*mode == 0, iclass 32, count 2 2006.285.09:44:10.92#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.09:44:10.92#ibcon#[25=AT03-07\r\n] 2006.285.09:44:10.92#ibcon#*before write, iclass 32, count 2 2006.285.09:44:10.92#ibcon#enter sib2, iclass 32, count 2 2006.285.09:44:10.92#ibcon#flushed, iclass 32, count 2 2006.285.09:44:10.92#ibcon#about to write, iclass 32, count 2 2006.285.09:44:10.92#ibcon#wrote, iclass 32, count 2 2006.285.09:44:10.92#ibcon#about to read 3, iclass 32, count 2 2006.285.09:44:10.95#ibcon#read 3, iclass 32, count 2 2006.285.09:44:10.95#ibcon#about to read 4, iclass 32, count 2 2006.285.09:44:10.95#ibcon#read 4, iclass 32, count 2 2006.285.09:44:10.95#ibcon#about to read 5, iclass 32, count 2 2006.285.09:44:10.95#ibcon#read 5, iclass 32, count 2 2006.285.09:44:10.95#ibcon#about to read 6, iclass 32, count 2 2006.285.09:44:10.95#ibcon#read 6, iclass 32, count 2 2006.285.09:44:10.95#ibcon#end of sib2, iclass 32, count 2 2006.285.09:44:10.95#ibcon#*after write, iclass 32, count 2 2006.285.09:44:10.95#ibcon#*before return 0, iclass 32, count 2 2006.285.09:44:10.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:44:10.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:44:10.95#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.09:44:10.95#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:10.95#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:44:11.07#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:44:11.07#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:44:11.07#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:44:11.07#ibcon#first serial, iclass 32, count 0 2006.285.09:44:11.07#ibcon#enter sib2, iclass 32, count 0 2006.285.09:44:11.07#ibcon#flushed, iclass 32, count 0 2006.285.09:44:11.07#ibcon#about to write, iclass 32, count 0 2006.285.09:44:11.07#ibcon#wrote, iclass 32, count 0 2006.285.09:44:11.07#ibcon#about to read 3, iclass 32, count 0 2006.285.09:44:11.09#ibcon#read 3, iclass 32, count 0 2006.285.09:44:11.09#ibcon#about to read 4, iclass 32, count 0 2006.285.09:44:11.09#ibcon#read 4, iclass 32, count 0 2006.285.09:44:11.09#ibcon#about to read 5, iclass 32, count 0 2006.285.09:44:11.09#ibcon#read 5, iclass 32, count 0 2006.285.09:44:11.09#ibcon#about to read 6, iclass 32, count 0 2006.285.09:44:11.09#ibcon#read 6, iclass 32, count 0 2006.285.09:44:11.09#ibcon#end of sib2, iclass 32, count 0 2006.285.09:44:11.09#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:44:11.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:44:11.09#ibcon#[25=USB\r\n] 2006.285.09:44:11.09#ibcon#*before write, iclass 32, count 0 2006.285.09:44:11.09#ibcon#enter sib2, iclass 32, count 0 2006.285.09:44:11.09#ibcon#flushed, iclass 32, count 0 2006.285.09:44:11.09#ibcon#about to write, iclass 32, count 0 2006.285.09:44:11.09#ibcon#wrote, iclass 32, count 0 2006.285.09:44:11.09#ibcon#about to read 3, iclass 32, count 0 2006.285.09:44:11.12#ibcon#read 3, iclass 32, count 0 2006.285.09:44:11.12#ibcon#about to read 4, iclass 32, count 0 2006.285.09:44:11.12#ibcon#read 4, iclass 32, count 0 2006.285.09:44:11.12#ibcon#about to read 5, iclass 32, count 0 2006.285.09:44:11.12#ibcon#read 5, iclass 32, count 0 2006.285.09:44:11.12#ibcon#about to read 6, iclass 32, count 0 2006.285.09:44:11.12#ibcon#read 6, iclass 32, count 0 2006.285.09:44:11.12#ibcon#end of sib2, iclass 32, count 0 2006.285.09:44:11.12#ibcon#*after write, iclass 32, count 0 2006.285.09:44:11.12#ibcon#*before return 0, iclass 32, count 0 2006.285.09:44:11.12#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:44:11.12#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:44:11.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:44:11.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:44:11.12$vck44/valo=4,624.99 2006.285.09:44:11.12#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.09:44:11.12#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.09:44:11.12#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:11.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:44:11.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:44:11.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:44:11.12#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:44:11.12#ibcon#first serial, iclass 34, count 0 2006.285.09:44:11.12#ibcon#enter sib2, iclass 34, count 0 2006.285.09:44:11.12#ibcon#flushed, iclass 34, count 0 2006.285.09:44:11.12#ibcon#about to write, iclass 34, count 0 2006.285.09:44:11.12#ibcon#wrote, iclass 34, count 0 2006.285.09:44:11.12#ibcon#about to read 3, iclass 34, count 0 2006.285.09:44:11.14#ibcon#read 3, iclass 34, count 0 2006.285.09:44:11.14#ibcon#about to read 4, iclass 34, count 0 2006.285.09:44:11.14#ibcon#read 4, iclass 34, count 0 2006.285.09:44:11.14#ibcon#about to read 5, iclass 34, count 0 2006.285.09:44:11.14#ibcon#read 5, iclass 34, count 0 2006.285.09:44:11.14#ibcon#about to read 6, iclass 34, count 0 2006.285.09:44:11.14#ibcon#read 6, iclass 34, count 0 2006.285.09:44:11.14#ibcon#end of sib2, iclass 34, count 0 2006.285.09:44:11.14#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:44:11.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:44:11.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:44:11.14#ibcon#*before write, iclass 34, count 0 2006.285.09:44:11.14#ibcon#enter sib2, iclass 34, count 0 2006.285.09:44:11.14#ibcon#flushed, iclass 34, count 0 2006.285.09:44:11.14#ibcon#about to write, iclass 34, count 0 2006.285.09:44:11.14#ibcon#wrote, iclass 34, count 0 2006.285.09:44:11.14#ibcon#about to read 3, iclass 34, count 0 2006.285.09:44:11.18#ibcon#read 3, iclass 34, count 0 2006.285.09:44:11.18#ibcon#about to read 4, iclass 34, count 0 2006.285.09:44:11.18#ibcon#read 4, iclass 34, count 0 2006.285.09:44:11.18#ibcon#about to read 5, iclass 34, count 0 2006.285.09:44:11.18#ibcon#read 5, iclass 34, count 0 2006.285.09:44:11.18#ibcon#about to read 6, iclass 34, count 0 2006.285.09:44:11.18#ibcon#read 6, iclass 34, count 0 2006.285.09:44:11.18#ibcon#end of sib2, iclass 34, count 0 2006.285.09:44:11.18#ibcon#*after write, iclass 34, count 0 2006.285.09:44:11.18#ibcon#*before return 0, iclass 34, count 0 2006.285.09:44:11.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:44:11.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:44:11.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:44:11.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:44:11.18$vck44/va=4,6 2006.285.09:44:11.18#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.09:44:11.18#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.09:44:11.18#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:11.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:44:11.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:44:11.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:44:11.24#ibcon#enter wrdev, iclass 36, count 2 2006.285.09:44:11.24#ibcon#first serial, iclass 36, count 2 2006.285.09:44:11.24#ibcon#enter sib2, iclass 36, count 2 2006.285.09:44:11.24#ibcon#flushed, iclass 36, count 2 2006.285.09:44:11.24#ibcon#about to write, iclass 36, count 2 2006.285.09:44:11.24#ibcon#wrote, iclass 36, count 2 2006.285.09:44:11.24#ibcon#about to read 3, iclass 36, count 2 2006.285.09:44:11.26#ibcon#read 3, iclass 36, count 2 2006.285.09:44:11.26#ibcon#about to read 4, iclass 36, count 2 2006.285.09:44:11.26#ibcon#read 4, iclass 36, count 2 2006.285.09:44:11.26#ibcon#about to read 5, iclass 36, count 2 2006.285.09:44:11.26#ibcon#read 5, iclass 36, count 2 2006.285.09:44:11.26#ibcon#about to read 6, iclass 36, count 2 2006.285.09:44:11.26#ibcon#read 6, iclass 36, count 2 2006.285.09:44:11.26#ibcon#end of sib2, iclass 36, count 2 2006.285.09:44:11.26#ibcon#*mode == 0, iclass 36, count 2 2006.285.09:44:11.26#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.09:44:11.26#ibcon#[25=AT04-06\r\n] 2006.285.09:44:11.26#ibcon#*before write, iclass 36, count 2 2006.285.09:44:11.26#ibcon#enter sib2, iclass 36, count 2 2006.285.09:44:11.26#ibcon#flushed, iclass 36, count 2 2006.285.09:44:11.26#ibcon#about to write, iclass 36, count 2 2006.285.09:44:11.26#ibcon#wrote, iclass 36, count 2 2006.285.09:44:11.26#ibcon#about to read 3, iclass 36, count 2 2006.285.09:44:11.29#ibcon#read 3, iclass 36, count 2 2006.285.09:44:11.29#ibcon#about to read 4, iclass 36, count 2 2006.285.09:44:11.29#ibcon#read 4, iclass 36, count 2 2006.285.09:44:11.29#ibcon#about to read 5, iclass 36, count 2 2006.285.09:44:11.29#ibcon#read 5, iclass 36, count 2 2006.285.09:44:11.29#ibcon#about to read 6, iclass 36, count 2 2006.285.09:44:11.29#ibcon#read 6, iclass 36, count 2 2006.285.09:44:11.29#ibcon#end of sib2, iclass 36, count 2 2006.285.09:44:11.29#ibcon#*after write, iclass 36, count 2 2006.285.09:44:11.29#ibcon#*before return 0, iclass 36, count 2 2006.285.09:44:11.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:44:11.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:44:11.29#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.09:44:11.29#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:11.29#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:44:11.41#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:44:11.41#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:44:11.41#ibcon#enter wrdev, iclass 36, count 0 2006.285.09:44:11.41#ibcon#first serial, iclass 36, count 0 2006.285.09:44:11.41#ibcon#enter sib2, iclass 36, count 0 2006.285.09:44:11.41#ibcon#flushed, iclass 36, count 0 2006.285.09:44:11.41#ibcon#about to write, iclass 36, count 0 2006.285.09:44:11.41#ibcon#wrote, iclass 36, count 0 2006.285.09:44:11.41#ibcon#about to read 3, iclass 36, count 0 2006.285.09:44:11.43#ibcon#read 3, iclass 36, count 0 2006.285.09:44:11.43#ibcon#about to read 4, iclass 36, count 0 2006.285.09:44:11.43#ibcon#read 4, iclass 36, count 0 2006.285.09:44:11.43#ibcon#about to read 5, iclass 36, count 0 2006.285.09:44:11.43#ibcon#read 5, iclass 36, count 0 2006.285.09:44:11.43#ibcon#about to read 6, iclass 36, count 0 2006.285.09:44:11.43#ibcon#read 6, iclass 36, count 0 2006.285.09:44:11.43#ibcon#end of sib2, iclass 36, count 0 2006.285.09:44:11.43#ibcon#*mode == 0, iclass 36, count 0 2006.285.09:44:11.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.09:44:11.43#ibcon#[25=USB\r\n] 2006.285.09:44:11.43#ibcon#*before write, iclass 36, count 0 2006.285.09:44:11.43#ibcon#enter sib2, iclass 36, count 0 2006.285.09:44:11.43#ibcon#flushed, iclass 36, count 0 2006.285.09:44:11.43#ibcon#about to write, iclass 36, count 0 2006.285.09:44:11.43#ibcon#wrote, iclass 36, count 0 2006.285.09:44:11.43#ibcon#about to read 3, iclass 36, count 0 2006.285.09:44:11.46#ibcon#read 3, iclass 36, count 0 2006.285.09:44:11.46#ibcon#about to read 4, iclass 36, count 0 2006.285.09:44:11.46#ibcon#read 4, iclass 36, count 0 2006.285.09:44:11.46#ibcon#about to read 5, iclass 36, count 0 2006.285.09:44:11.46#ibcon#read 5, iclass 36, count 0 2006.285.09:44:11.46#ibcon#about to read 6, iclass 36, count 0 2006.285.09:44:11.46#ibcon#read 6, iclass 36, count 0 2006.285.09:44:11.46#ibcon#end of sib2, iclass 36, count 0 2006.285.09:44:11.46#ibcon#*after write, iclass 36, count 0 2006.285.09:44:11.46#ibcon#*before return 0, iclass 36, count 0 2006.285.09:44:11.46#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:44:11.46#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:44:11.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.09:44:11.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.09:44:11.46$vck44/valo=5,734.99 2006.285.09:44:11.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.09:44:11.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.09:44:11.46#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:11.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:44:11.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:44:11.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:44:11.46#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:44:11.46#ibcon#first serial, iclass 38, count 0 2006.285.09:44:11.46#ibcon#enter sib2, iclass 38, count 0 2006.285.09:44:11.46#ibcon#flushed, iclass 38, count 0 2006.285.09:44:11.46#ibcon#about to write, iclass 38, count 0 2006.285.09:44:11.46#ibcon#wrote, iclass 38, count 0 2006.285.09:44:11.46#ibcon#about to read 3, iclass 38, count 0 2006.285.09:44:11.48#ibcon#read 3, iclass 38, count 0 2006.285.09:44:11.48#ibcon#about to read 4, iclass 38, count 0 2006.285.09:44:11.48#ibcon#read 4, iclass 38, count 0 2006.285.09:44:11.48#ibcon#about to read 5, iclass 38, count 0 2006.285.09:44:11.48#ibcon#read 5, iclass 38, count 0 2006.285.09:44:11.48#ibcon#about to read 6, iclass 38, count 0 2006.285.09:44:11.48#ibcon#read 6, iclass 38, count 0 2006.285.09:44:11.48#ibcon#end of sib2, iclass 38, count 0 2006.285.09:44:11.48#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:44:11.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:44:11.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:44:11.48#ibcon#*before write, iclass 38, count 0 2006.285.09:44:11.48#ibcon#enter sib2, iclass 38, count 0 2006.285.09:44:11.48#ibcon#flushed, iclass 38, count 0 2006.285.09:44:11.48#ibcon#about to write, iclass 38, count 0 2006.285.09:44:11.48#ibcon#wrote, iclass 38, count 0 2006.285.09:44:11.48#ibcon#about to read 3, iclass 38, count 0 2006.285.09:44:11.52#ibcon#read 3, iclass 38, count 0 2006.285.09:44:11.52#ibcon#about to read 4, iclass 38, count 0 2006.285.09:44:11.52#ibcon#read 4, iclass 38, count 0 2006.285.09:44:11.52#ibcon#about to read 5, iclass 38, count 0 2006.285.09:44:11.52#ibcon#read 5, iclass 38, count 0 2006.285.09:44:11.52#ibcon#about to read 6, iclass 38, count 0 2006.285.09:44:11.52#ibcon#read 6, iclass 38, count 0 2006.285.09:44:11.52#ibcon#end of sib2, iclass 38, count 0 2006.285.09:44:11.52#ibcon#*after write, iclass 38, count 0 2006.285.09:44:11.52#ibcon#*before return 0, iclass 38, count 0 2006.285.09:44:11.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:44:11.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:44:11.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:44:11.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:44:11.52$vck44/va=5,3 2006.285.09:44:11.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.09:44:11.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.09:44:11.52#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:11.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:44:11.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:44:11.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:44:11.58#ibcon#enter wrdev, iclass 40, count 2 2006.285.09:44:11.58#ibcon#first serial, iclass 40, count 2 2006.285.09:44:11.58#ibcon#enter sib2, iclass 40, count 2 2006.285.09:44:11.58#ibcon#flushed, iclass 40, count 2 2006.285.09:44:11.58#ibcon#about to write, iclass 40, count 2 2006.285.09:44:11.58#ibcon#wrote, iclass 40, count 2 2006.285.09:44:11.58#ibcon#about to read 3, iclass 40, count 2 2006.285.09:44:11.60#ibcon#read 3, iclass 40, count 2 2006.285.09:44:11.60#ibcon#about to read 4, iclass 40, count 2 2006.285.09:44:11.60#ibcon#read 4, iclass 40, count 2 2006.285.09:44:11.60#ibcon#about to read 5, iclass 40, count 2 2006.285.09:44:11.60#ibcon#read 5, iclass 40, count 2 2006.285.09:44:11.60#ibcon#about to read 6, iclass 40, count 2 2006.285.09:44:11.60#ibcon#read 6, iclass 40, count 2 2006.285.09:44:11.60#ibcon#end of sib2, iclass 40, count 2 2006.285.09:44:11.60#ibcon#*mode == 0, iclass 40, count 2 2006.285.09:44:11.60#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.09:44:11.60#ibcon#[25=AT05-03\r\n] 2006.285.09:44:11.60#ibcon#*before write, iclass 40, count 2 2006.285.09:44:11.60#ibcon#enter sib2, iclass 40, count 2 2006.285.09:44:11.60#ibcon#flushed, iclass 40, count 2 2006.285.09:44:11.60#ibcon#about to write, iclass 40, count 2 2006.285.09:44:11.60#ibcon#wrote, iclass 40, count 2 2006.285.09:44:11.60#ibcon#about to read 3, iclass 40, count 2 2006.285.09:44:11.63#ibcon#read 3, iclass 40, count 2 2006.285.09:44:11.63#ibcon#about to read 4, iclass 40, count 2 2006.285.09:44:11.63#ibcon#read 4, iclass 40, count 2 2006.285.09:44:11.63#ibcon#about to read 5, iclass 40, count 2 2006.285.09:44:11.63#ibcon#read 5, iclass 40, count 2 2006.285.09:44:11.63#ibcon#about to read 6, iclass 40, count 2 2006.285.09:44:11.63#ibcon#read 6, iclass 40, count 2 2006.285.09:44:11.63#ibcon#end of sib2, iclass 40, count 2 2006.285.09:44:11.63#ibcon#*after write, iclass 40, count 2 2006.285.09:44:11.63#ibcon#*before return 0, iclass 40, count 2 2006.285.09:44:11.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:44:11.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:44:11.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.09:44:11.63#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:11.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:44:11.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:44:11.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:44:11.75#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:44:11.75#ibcon#first serial, iclass 40, count 0 2006.285.09:44:11.75#ibcon#enter sib2, iclass 40, count 0 2006.285.09:44:11.75#ibcon#flushed, iclass 40, count 0 2006.285.09:44:11.75#ibcon#about to write, iclass 40, count 0 2006.285.09:44:11.75#ibcon#wrote, iclass 40, count 0 2006.285.09:44:11.75#ibcon#about to read 3, iclass 40, count 0 2006.285.09:44:11.77#ibcon#read 3, iclass 40, count 0 2006.285.09:44:11.77#ibcon#about to read 4, iclass 40, count 0 2006.285.09:44:11.77#ibcon#read 4, iclass 40, count 0 2006.285.09:44:11.77#ibcon#about to read 5, iclass 40, count 0 2006.285.09:44:11.77#ibcon#read 5, iclass 40, count 0 2006.285.09:44:11.77#ibcon#about to read 6, iclass 40, count 0 2006.285.09:44:11.77#ibcon#read 6, iclass 40, count 0 2006.285.09:44:11.77#ibcon#end of sib2, iclass 40, count 0 2006.285.09:44:11.77#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:44:11.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:44:11.77#ibcon#[25=USB\r\n] 2006.285.09:44:11.77#ibcon#*before write, iclass 40, count 0 2006.285.09:44:11.77#ibcon#enter sib2, iclass 40, count 0 2006.285.09:44:11.77#ibcon#flushed, iclass 40, count 0 2006.285.09:44:11.77#ibcon#about to write, iclass 40, count 0 2006.285.09:44:11.77#ibcon#wrote, iclass 40, count 0 2006.285.09:44:11.77#ibcon#about to read 3, iclass 40, count 0 2006.285.09:44:11.80#ibcon#read 3, iclass 40, count 0 2006.285.09:44:11.80#ibcon#about to read 4, iclass 40, count 0 2006.285.09:44:11.80#ibcon#read 4, iclass 40, count 0 2006.285.09:44:11.80#ibcon#about to read 5, iclass 40, count 0 2006.285.09:44:11.80#ibcon#read 5, iclass 40, count 0 2006.285.09:44:11.80#ibcon#about to read 6, iclass 40, count 0 2006.285.09:44:11.80#ibcon#read 6, iclass 40, count 0 2006.285.09:44:11.80#ibcon#end of sib2, iclass 40, count 0 2006.285.09:44:11.80#ibcon#*after write, iclass 40, count 0 2006.285.09:44:11.80#ibcon#*before return 0, iclass 40, count 0 2006.285.09:44:11.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:44:11.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:44:11.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:44:11.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:44:11.80$vck44/valo=6,814.99 2006.285.09:44:11.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.09:44:11.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.09:44:11.80#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:11.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:44:11.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:44:11.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:44:11.80#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:44:11.80#ibcon#first serial, iclass 4, count 0 2006.285.09:44:11.80#ibcon#enter sib2, iclass 4, count 0 2006.285.09:44:11.80#ibcon#flushed, iclass 4, count 0 2006.285.09:44:11.80#ibcon#about to write, iclass 4, count 0 2006.285.09:44:11.80#ibcon#wrote, iclass 4, count 0 2006.285.09:44:11.80#ibcon#about to read 3, iclass 4, count 0 2006.285.09:44:11.82#ibcon#read 3, iclass 4, count 0 2006.285.09:44:11.82#ibcon#about to read 4, iclass 4, count 0 2006.285.09:44:11.82#ibcon#read 4, iclass 4, count 0 2006.285.09:44:11.82#ibcon#about to read 5, iclass 4, count 0 2006.285.09:44:11.82#ibcon#read 5, iclass 4, count 0 2006.285.09:44:11.82#ibcon#about to read 6, iclass 4, count 0 2006.285.09:44:11.82#ibcon#read 6, iclass 4, count 0 2006.285.09:44:11.82#ibcon#end of sib2, iclass 4, count 0 2006.285.09:44:11.82#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:44:11.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:44:11.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:44:11.82#ibcon#*before write, iclass 4, count 0 2006.285.09:44:11.82#ibcon#enter sib2, iclass 4, count 0 2006.285.09:44:11.82#ibcon#flushed, iclass 4, count 0 2006.285.09:44:11.82#ibcon#about to write, iclass 4, count 0 2006.285.09:44:11.82#ibcon#wrote, iclass 4, count 0 2006.285.09:44:11.82#ibcon#about to read 3, iclass 4, count 0 2006.285.09:44:11.86#ibcon#read 3, iclass 4, count 0 2006.285.09:44:11.86#ibcon#about to read 4, iclass 4, count 0 2006.285.09:44:11.86#ibcon#read 4, iclass 4, count 0 2006.285.09:44:11.86#ibcon#about to read 5, iclass 4, count 0 2006.285.09:44:11.86#ibcon#read 5, iclass 4, count 0 2006.285.09:44:11.86#ibcon#about to read 6, iclass 4, count 0 2006.285.09:44:11.86#ibcon#read 6, iclass 4, count 0 2006.285.09:44:11.86#ibcon#end of sib2, iclass 4, count 0 2006.285.09:44:11.86#ibcon#*after write, iclass 4, count 0 2006.285.09:44:11.86#ibcon#*before return 0, iclass 4, count 0 2006.285.09:44:11.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:44:11.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:44:11.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:44:11.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:44:11.86$vck44/va=6,4 2006.285.09:44:11.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.09:44:11.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.09:44:11.86#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:11.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:44:11.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:44:11.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:44:11.92#ibcon#enter wrdev, iclass 6, count 2 2006.285.09:44:11.92#ibcon#first serial, iclass 6, count 2 2006.285.09:44:11.92#ibcon#enter sib2, iclass 6, count 2 2006.285.09:44:11.92#ibcon#flushed, iclass 6, count 2 2006.285.09:44:11.92#ibcon#about to write, iclass 6, count 2 2006.285.09:44:11.92#ibcon#wrote, iclass 6, count 2 2006.285.09:44:11.92#ibcon#about to read 3, iclass 6, count 2 2006.285.09:44:11.94#ibcon#read 3, iclass 6, count 2 2006.285.09:44:11.94#ibcon#about to read 4, iclass 6, count 2 2006.285.09:44:11.94#ibcon#read 4, iclass 6, count 2 2006.285.09:44:11.94#ibcon#about to read 5, iclass 6, count 2 2006.285.09:44:11.94#ibcon#read 5, iclass 6, count 2 2006.285.09:44:11.94#ibcon#about to read 6, iclass 6, count 2 2006.285.09:44:11.94#ibcon#read 6, iclass 6, count 2 2006.285.09:44:11.94#ibcon#end of sib2, iclass 6, count 2 2006.285.09:44:11.94#ibcon#*mode == 0, iclass 6, count 2 2006.285.09:44:11.94#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.09:44:11.94#ibcon#[25=AT06-04\r\n] 2006.285.09:44:11.94#ibcon#*before write, iclass 6, count 2 2006.285.09:44:11.94#ibcon#enter sib2, iclass 6, count 2 2006.285.09:44:11.94#ibcon#flushed, iclass 6, count 2 2006.285.09:44:11.94#ibcon#about to write, iclass 6, count 2 2006.285.09:44:11.94#ibcon#wrote, iclass 6, count 2 2006.285.09:44:11.94#ibcon#about to read 3, iclass 6, count 2 2006.285.09:44:11.97#ibcon#read 3, iclass 6, count 2 2006.285.09:44:11.97#ibcon#about to read 4, iclass 6, count 2 2006.285.09:44:11.97#ibcon#read 4, iclass 6, count 2 2006.285.09:44:11.97#ibcon#about to read 5, iclass 6, count 2 2006.285.09:44:11.97#ibcon#read 5, iclass 6, count 2 2006.285.09:44:11.97#ibcon#about to read 6, iclass 6, count 2 2006.285.09:44:11.97#ibcon#read 6, iclass 6, count 2 2006.285.09:44:11.97#ibcon#end of sib2, iclass 6, count 2 2006.285.09:44:11.97#ibcon#*after write, iclass 6, count 2 2006.285.09:44:11.97#ibcon#*before return 0, iclass 6, count 2 2006.285.09:44:11.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:44:11.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:44:11.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.09:44:11.97#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:11.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:44:12.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:44:12.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:44:12.09#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:44:12.09#ibcon#first serial, iclass 6, count 0 2006.285.09:44:12.09#ibcon#enter sib2, iclass 6, count 0 2006.285.09:44:12.09#ibcon#flushed, iclass 6, count 0 2006.285.09:44:12.09#ibcon#about to write, iclass 6, count 0 2006.285.09:44:12.09#ibcon#wrote, iclass 6, count 0 2006.285.09:44:12.09#ibcon#about to read 3, iclass 6, count 0 2006.285.09:44:12.11#ibcon#read 3, iclass 6, count 0 2006.285.09:44:12.11#ibcon#about to read 4, iclass 6, count 0 2006.285.09:44:12.11#ibcon#read 4, iclass 6, count 0 2006.285.09:44:12.11#ibcon#about to read 5, iclass 6, count 0 2006.285.09:44:12.11#ibcon#read 5, iclass 6, count 0 2006.285.09:44:12.11#ibcon#about to read 6, iclass 6, count 0 2006.285.09:44:12.11#ibcon#read 6, iclass 6, count 0 2006.285.09:44:12.11#ibcon#end of sib2, iclass 6, count 0 2006.285.09:44:12.11#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:44:12.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:44:12.11#ibcon#[25=USB\r\n] 2006.285.09:44:12.11#ibcon#*before write, iclass 6, count 0 2006.285.09:44:12.11#ibcon#enter sib2, iclass 6, count 0 2006.285.09:44:12.11#ibcon#flushed, iclass 6, count 0 2006.285.09:44:12.11#ibcon#about to write, iclass 6, count 0 2006.285.09:44:12.11#ibcon#wrote, iclass 6, count 0 2006.285.09:44:12.11#ibcon#about to read 3, iclass 6, count 0 2006.285.09:44:12.14#ibcon#read 3, iclass 6, count 0 2006.285.09:44:12.14#ibcon#about to read 4, iclass 6, count 0 2006.285.09:44:12.14#ibcon#read 4, iclass 6, count 0 2006.285.09:44:12.14#ibcon#about to read 5, iclass 6, count 0 2006.285.09:44:12.14#ibcon#read 5, iclass 6, count 0 2006.285.09:44:12.14#ibcon#about to read 6, iclass 6, count 0 2006.285.09:44:12.14#ibcon#read 6, iclass 6, count 0 2006.285.09:44:12.14#ibcon#end of sib2, iclass 6, count 0 2006.285.09:44:12.14#ibcon#*after write, iclass 6, count 0 2006.285.09:44:12.14#ibcon#*before return 0, iclass 6, count 0 2006.285.09:44:12.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:44:12.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:44:12.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:44:12.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:44:12.14$vck44/valo=7,864.99 2006.285.09:44:12.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.09:44:12.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.09:44:12.14#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:12.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:44:12.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:44:12.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:44:12.14#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:44:12.14#ibcon#first serial, iclass 10, count 0 2006.285.09:44:12.14#ibcon#enter sib2, iclass 10, count 0 2006.285.09:44:12.14#ibcon#flushed, iclass 10, count 0 2006.285.09:44:12.14#ibcon#about to write, iclass 10, count 0 2006.285.09:44:12.14#ibcon#wrote, iclass 10, count 0 2006.285.09:44:12.14#ibcon#about to read 3, iclass 10, count 0 2006.285.09:44:12.16#ibcon#read 3, iclass 10, count 0 2006.285.09:44:12.16#ibcon#about to read 4, iclass 10, count 0 2006.285.09:44:12.16#ibcon#read 4, iclass 10, count 0 2006.285.09:44:12.16#ibcon#about to read 5, iclass 10, count 0 2006.285.09:44:12.16#ibcon#read 5, iclass 10, count 0 2006.285.09:44:12.16#ibcon#about to read 6, iclass 10, count 0 2006.285.09:44:12.16#ibcon#read 6, iclass 10, count 0 2006.285.09:44:12.16#ibcon#end of sib2, iclass 10, count 0 2006.285.09:44:12.16#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:44:12.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:44:12.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:44:12.16#ibcon#*before write, iclass 10, count 0 2006.285.09:44:12.16#ibcon#enter sib2, iclass 10, count 0 2006.285.09:44:12.16#ibcon#flushed, iclass 10, count 0 2006.285.09:44:12.16#ibcon#about to write, iclass 10, count 0 2006.285.09:44:12.16#ibcon#wrote, iclass 10, count 0 2006.285.09:44:12.16#ibcon#about to read 3, iclass 10, count 0 2006.285.09:44:12.20#ibcon#read 3, iclass 10, count 0 2006.285.09:44:12.20#ibcon#about to read 4, iclass 10, count 0 2006.285.09:44:12.20#ibcon#read 4, iclass 10, count 0 2006.285.09:44:12.20#ibcon#about to read 5, iclass 10, count 0 2006.285.09:44:12.20#ibcon#read 5, iclass 10, count 0 2006.285.09:44:12.20#ibcon#about to read 6, iclass 10, count 0 2006.285.09:44:12.20#ibcon#read 6, iclass 10, count 0 2006.285.09:44:12.20#ibcon#end of sib2, iclass 10, count 0 2006.285.09:44:12.20#ibcon#*after write, iclass 10, count 0 2006.285.09:44:12.20#ibcon#*before return 0, iclass 10, count 0 2006.285.09:44:12.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:44:12.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:44:12.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:44:12.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:44:12.20$vck44/va=7,4 2006.285.09:44:12.20#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.09:44:12.20#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.09:44:12.20#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:12.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:44:12.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:44:12.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:44:12.26#ibcon#enter wrdev, iclass 12, count 2 2006.285.09:44:12.26#ibcon#first serial, iclass 12, count 2 2006.285.09:44:12.26#ibcon#enter sib2, iclass 12, count 2 2006.285.09:44:12.26#ibcon#flushed, iclass 12, count 2 2006.285.09:44:12.26#ibcon#about to write, iclass 12, count 2 2006.285.09:44:12.26#ibcon#wrote, iclass 12, count 2 2006.285.09:44:12.26#ibcon#about to read 3, iclass 12, count 2 2006.285.09:44:12.28#ibcon#read 3, iclass 12, count 2 2006.285.09:44:12.28#ibcon#about to read 4, iclass 12, count 2 2006.285.09:44:12.28#ibcon#read 4, iclass 12, count 2 2006.285.09:44:12.28#ibcon#about to read 5, iclass 12, count 2 2006.285.09:44:12.28#ibcon#read 5, iclass 12, count 2 2006.285.09:44:12.28#ibcon#about to read 6, iclass 12, count 2 2006.285.09:44:12.28#ibcon#read 6, iclass 12, count 2 2006.285.09:44:12.28#ibcon#end of sib2, iclass 12, count 2 2006.285.09:44:12.28#ibcon#*mode == 0, iclass 12, count 2 2006.285.09:44:12.28#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.09:44:12.28#ibcon#[25=AT07-04\r\n] 2006.285.09:44:12.28#ibcon#*before write, iclass 12, count 2 2006.285.09:44:12.28#ibcon#enter sib2, iclass 12, count 2 2006.285.09:44:12.28#ibcon#flushed, iclass 12, count 2 2006.285.09:44:12.28#ibcon#about to write, iclass 12, count 2 2006.285.09:44:12.28#ibcon#wrote, iclass 12, count 2 2006.285.09:44:12.28#ibcon#about to read 3, iclass 12, count 2 2006.285.09:44:12.31#ibcon#read 3, iclass 12, count 2 2006.285.09:44:12.31#ibcon#about to read 4, iclass 12, count 2 2006.285.09:44:12.31#ibcon#read 4, iclass 12, count 2 2006.285.09:44:12.31#ibcon#about to read 5, iclass 12, count 2 2006.285.09:44:12.31#ibcon#read 5, iclass 12, count 2 2006.285.09:44:12.31#ibcon#about to read 6, iclass 12, count 2 2006.285.09:44:12.31#ibcon#read 6, iclass 12, count 2 2006.285.09:44:12.31#ibcon#end of sib2, iclass 12, count 2 2006.285.09:44:12.31#ibcon#*after write, iclass 12, count 2 2006.285.09:44:12.31#ibcon#*before return 0, iclass 12, count 2 2006.285.09:44:12.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:44:12.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:44:12.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.09:44:12.31#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:12.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:44:12.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:44:12.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:44:12.43#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:44:12.43#ibcon#first serial, iclass 12, count 0 2006.285.09:44:12.43#ibcon#enter sib2, iclass 12, count 0 2006.285.09:44:12.43#ibcon#flushed, iclass 12, count 0 2006.285.09:44:12.43#ibcon#about to write, iclass 12, count 0 2006.285.09:44:12.43#ibcon#wrote, iclass 12, count 0 2006.285.09:44:12.43#ibcon#about to read 3, iclass 12, count 0 2006.285.09:44:12.45#ibcon#read 3, iclass 12, count 0 2006.285.09:44:12.45#ibcon#about to read 4, iclass 12, count 0 2006.285.09:44:12.45#ibcon#read 4, iclass 12, count 0 2006.285.09:44:12.45#ibcon#about to read 5, iclass 12, count 0 2006.285.09:44:12.45#ibcon#read 5, iclass 12, count 0 2006.285.09:44:12.45#ibcon#about to read 6, iclass 12, count 0 2006.285.09:44:12.45#ibcon#read 6, iclass 12, count 0 2006.285.09:44:12.45#ibcon#end of sib2, iclass 12, count 0 2006.285.09:44:12.45#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:44:12.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:44:12.45#ibcon#[25=USB\r\n] 2006.285.09:44:12.45#ibcon#*before write, iclass 12, count 0 2006.285.09:44:12.45#ibcon#enter sib2, iclass 12, count 0 2006.285.09:44:12.45#ibcon#flushed, iclass 12, count 0 2006.285.09:44:12.45#ibcon#about to write, iclass 12, count 0 2006.285.09:44:12.45#ibcon#wrote, iclass 12, count 0 2006.285.09:44:12.45#ibcon#about to read 3, iclass 12, count 0 2006.285.09:44:12.48#ibcon#read 3, iclass 12, count 0 2006.285.09:44:12.48#ibcon#about to read 4, iclass 12, count 0 2006.285.09:44:12.48#ibcon#read 4, iclass 12, count 0 2006.285.09:44:12.48#ibcon#about to read 5, iclass 12, count 0 2006.285.09:44:12.48#ibcon#read 5, iclass 12, count 0 2006.285.09:44:12.48#ibcon#about to read 6, iclass 12, count 0 2006.285.09:44:12.48#ibcon#read 6, iclass 12, count 0 2006.285.09:44:12.48#ibcon#end of sib2, iclass 12, count 0 2006.285.09:44:12.48#ibcon#*after write, iclass 12, count 0 2006.285.09:44:12.48#ibcon#*before return 0, iclass 12, count 0 2006.285.09:44:12.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:44:12.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:44:12.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:44:12.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:44:12.48$vck44/valo=8,884.99 2006.285.09:44:12.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.09:44:12.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.09:44:12.48#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:12.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:44:12.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:44:12.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:44:12.48#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:44:12.48#ibcon#first serial, iclass 14, count 0 2006.285.09:44:12.48#ibcon#enter sib2, iclass 14, count 0 2006.285.09:44:12.48#ibcon#flushed, iclass 14, count 0 2006.285.09:44:12.48#ibcon#about to write, iclass 14, count 0 2006.285.09:44:12.48#ibcon#wrote, iclass 14, count 0 2006.285.09:44:12.48#ibcon#about to read 3, iclass 14, count 0 2006.285.09:44:12.50#ibcon#read 3, iclass 14, count 0 2006.285.09:44:12.50#ibcon#about to read 4, iclass 14, count 0 2006.285.09:44:12.50#ibcon#read 4, iclass 14, count 0 2006.285.09:44:12.50#ibcon#about to read 5, iclass 14, count 0 2006.285.09:44:12.50#ibcon#read 5, iclass 14, count 0 2006.285.09:44:12.50#ibcon#about to read 6, iclass 14, count 0 2006.285.09:44:12.50#ibcon#read 6, iclass 14, count 0 2006.285.09:44:12.50#ibcon#end of sib2, iclass 14, count 0 2006.285.09:44:12.50#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:44:12.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:44:12.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:44:12.50#ibcon#*before write, iclass 14, count 0 2006.285.09:44:12.50#ibcon#enter sib2, iclass 14, count 0 2006.285.09:44:12.50#ibcon#flushed, iclass 14, count 0 2006.285.09:44:12.50#ibcon#about to write, iclass 14, count 0 2006.285.09:44:12.50#ibcon#wrote, iclass 14, count 0 2006.285.09:44:12.50#ibcon#about to read 3, iclass 14, count 0 2006.285.09:44:12.54#ibcon#read 3, iclass 14, count 0 2006.285.09:44:12.54#ibcon#about to read 4, iclass 14, count 0 2006.285.09:44:12.54#ibcon#read 4, iclass 14, count 0 2006.285.09:44:12.54#ibcon#about to read 5, iclass 14, count 0 2006.285.09:44:12.54#ibcon#read 5, iclass 14, count 0 2006.285.09:44:12.54#ibcon#about to read 6, iclass 14, count 0 2006.285.09:44:12.54#ibcon#read 6, iclass 14, count 0 2006.285.09:44:12.54#ibcon#end of sib2, iclass 14, count 0 2006.285.09:44:12.54#ibcon#*after write, iclass 14, count 0 2006.285.09:44:12.54#ibcon#*before return 0, iclass 14, count 0 2006.285.09:44:12.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:44:12.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:44:12.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:44:12.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:44:12.54$vck44/va=8,3 2006.285.09:44:12.54#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.09:44:12.54#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.09:44:12.54#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:12.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:44:12.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:44:12.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:44:12.60#ibcon#enter wrdev, iclass 16, count 2 2006.285.09:44:12.60#ibcon#first serial, iclass 16, count 2 2006.285.09:44:12.60#ibcon#enter sib2, iclass 16, count 2 2006.285.09:44:12.60#ibcon#flushed, iclass 16, count 2 2006.285.09:44:12.60#ibcon#about to write, iclass 16, count 2 2006.285.09:44:12.60#ibcon#wrote, iclass 16, count 2 2006.285.09:44:12.60#ibcon#about to read 3, iclass 16, count 2 2006.285.09:44:12.62#ibcon#read 3, iclass 16, count 2 2006.285.09:44:12.62#ibcon#about to read 4, iclass 16, count 2 2006.285.09:44:12.62#ibcon#read 4, iclass 16, count 2 2006.285.09:44:12.62#ibcon#about to read 5, iclass 16, count 2 2006.285.09:44:12.62#ibcon#read 5, iclass 16, count 2 2006.285.09:44:12.62#ibcon#about to read 6, iclass 16, count 2 2006.285.09:44:12.62#ibcon#read 6, iclass 16, count 2 2006.285.09:44:12.62#ibcon#end of sib2, iclass 16, count 2 2006.285.09:44:12.62#ibcon#*mode == 0, iclass 16, count 2 2006.285.09:44:12.62#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.09:44:12.62#ibcon#[25=AT08-03\r\n] 2006.285.09:44:12.62#ibcon#*before write, iclass 16, count 2 2006.285.09:44:12.62#ibcon#enter sib2, iclass 16, count 2 2006.285.09:44:12.62#ibcon#flushed, iclass 16, count 2 2006.285.09:44:12.62#ibcon#about to write, iclass 16, count 2 2006.285.09:44:12.62#ibcon#wrote, iclass 16, count 2 2006.285.09:44:12.62#ibcon#about to read 3, iclass 16, count 2 2006.285.09:44:12.65#ibcon#read 3, iclass 16, count 2 2006.285.09:44:12.65#ibcon#about to read 4, iclass 16, count 2 2006.285.09:44:12.65#ibcon#read 4, iclass 16, count 2 2006.285.09:44:12.65#ibcon#about to read 5, iclass 16, count 2 2006.285.09:44:12.65#ibcon#read 5, iclass 16, count 2 2006.285.09:44:12.65#ibcon#about to read 6, iclass 16, count 2 2006.285.09:44:12.65#ibcon#read 6, iclass 16, count 2 2006.285.09:44:12.65#ibcon#end of sib2, iclass 16, count 2 2006.285.09:44:12.65#ibcon#*after write, iclass 16, count 2 2006.285.09:44:12.65#ibcon#*before return 0, iclass 16, count 2 2006.285.09:44:12.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:44:12.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:44:12.65#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.09:44:12.65#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:12.65#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:44:12.77#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:44:12.77#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:44:12.77#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:44:12.77#ibcon#first serial, iclass 16, count 0 2006.285.09:44:12.77#ibcon#enter sib2, iclass 16, count 0 2006.285.09:44:12.77#ibcon#flushed, iclass 16, count 0 2006.285.09:44:12.77#ibcon#about to write, iclass 16, count 0 2006.285.09:44:12.77#ibcon#wrote, iclass 16, count 0 2006.285.09:44:12.77#ibcon#about to read 3, iclass 16, count 0 2006.285.09:44:12.79#ibcon#read 3, iclass 16, count 0 2006.285.09:44:12.79#ibcon#about to read 4, iclass 16, count 0 2006.285.09:44:12.79#ibcon#read 4, iclass 16, count 0 2006.285.09:44:12.79#ibcon#about to read 5, iclass 16, count 0 2006.285.09:44:12.79#ibcon#read 5, iclass 16, count 0 2006.285.09:44:12.79#ibcon#about to read 6, iclass 16, count 0 2006.285.09:44:12.79#ibcon#read 6, iclass 16, count 0 2006.285.09:44:12.79#ibcon#end of sib2, iclass 16, count 0 2006.285.09:44:12.79#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:44:12.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:44:12.79#ibcon#[25=USB\r\n] 2006.285.09:44:12.79#ibcon#*before write, iclass 16, count 0 2006.285.09:44:12.79#ibcon#enter sib2, iclass 16, count 0 2006.285.09:44:12.79#ibcon#flushed, iclass 16, count 0 2006.285.09:44:12.79#ibcon#about to write, iclass 16, count 0 2006.285.09:44:12.79#ibcon#wrote, iclass 16, count 0 2006.285.09:44:12.79#ibcon#about to read 3, iclass 16, count 0 2006.285.09:44:12.82#ibcon#read 3, iclass 16, count 0 2006.285.09:44:12.82#ibcon#about to read 4, iclass 16, count 0 2006.285.09:44:12.82#ibcon#read 4, iclass 16, count 0 2006.285.09:44:12.82#ibcon#about to read 5, iclass 16, count 0 2006.285.09:44:12.82#ibcon#read 5, iclass 16, count 0 2006.285.09:44:12.82#ibcon#about to read 6, iclass 16, count 0 2006.285.09:44:12.82#ibcon#read 6, iclass 16, count 0 2006.285.09:44:12.82#ibcon#end of sib2, iclass 16, count 0 2006.285.09:44:12.82#ibcon#*after write, iclass 16, count 0 2006.285.09:44:12.82#ibcon#*before return 0, iclass 16, count 0 2006.285.09:44:12.82#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:44:12.82#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:44:12.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:44:12.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:44:12.82$vck44/vblo=1,629.99 2006.285.09:44:12.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.09:44:12.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.09:44:12.82#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:12.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:44:12.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:44:12.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:44:12.82#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:44:12.82#ibcon#first serial, iclass 18, count 0 2006.285.09:44:12.82#ibcon#enter sib2, iclass 18, count 0 2006.285.09:44:12.82#ibcon#flushed, iclass 18, count 0 2006.285.09:44:12.82#ibcon#about to write, iclass 18, count 0 2006.285.09:44:12.82#ibcon#wrote, iclass 18, count 0 2006.285.09:44:12.82#ibcon#about to read 3, iclass 18, count 0 2006.285.09:44:12.84#ibcon#read 3, iclass 18, count 0 2006.285.09:44:12.84#ibcon#about to read 4, iclass 18, count 0 2006.285.09:44:12.84#ibcon#read 4, iclass 18, count 0 2006.285.09:44:12.84#ibcon#about to read 5, iclass 18, count 0 2006.285.09:44:12.84#ibcon#read 5, iclass 18, count 0 2006.285.09:44:12.84#ibcon#about to read 6, iclass 18, count 0 2006.285.09:44:12.84#ibcon#read 6, iclass 18, count 0 2006.285.09:44:12.84#ibcon#end of sib2, iclass 18, count 0 2006.285.09:44:12.84#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:44:12.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:44:12.84#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:44:12.84#ibcon#*before write, iclass 18, count 0 2006.285.09:44:12.84#ibcon#enter sib2, iclass 18, count 0 2006.285.09:44:12.84#ibcon#flushed, iclass 18, count 0 2006.285.09:44:12.84#ibcon#about to write, iclass 18, count 0 2006.285.09:44:12.84#ibcon#wrote, iclass 18, count 0 2006.285.09:44:12.84#ibcon#about to read 3, iclass 18, count 0 2006.285.09:44:12.88#ibcon#read 3, iclass 18, count 0 2006.285.09:44:12.88#ibcon#about to read 4, iclass 18, count 0 2006.285.09:44:12.88#ibcon#read 4, iclass 18, count 0 2006.285.09:44:12.88#ibcon#about to read 5, iclass 18, count 0 2006.285.09:44:12.88#ibcon#read 5, iclass 18, count 0 2006.285.09:44:12.88#ibcon#about to read 6, iclass 18, count 0 2006.285.09:44:12.88#ibcon#read 6, iclass 18, count 0 2006.285.09:44:12.88#ibcon#end of sib2, iclass 18, count 0 2006.285.09:44:12.88#ibcon#*after write, iclass 18, count 0 2006.285.09:44:12.88#ibcon#*before return 0, iclass 18, count 0 2006.285.09:44:12.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:44:12.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:44:12.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:44:12.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:44:12.88$vck44/vb=1,4 2006.285.09:44:12.88#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.09:44:12.88#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.09:44:12.88#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:12.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:44:12.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:44:12.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:44:12.88#ibcon#enter wrdev, iclass 20, count 2 2006.285.09:44:12.88#ibcon#first serial, iclass 20, count 2 2006.285.09:44:12.88#ibcon#enter sib2, iclass 20, count 2 2006.285.09:44:12.88#ibcon#flushed, iclass 20, count 2 2006.285.09:44:12.88#ibcon#about to write, iclass 20, count 2 2006.285.09:44:12.88#ibcon#wrote, iclass 20, count 2 2006.285.09:44:12.88#ibcon#about to read 3, iclass 20, count 2 2006.285.09:44:12.90#ibcon#read 3, iclass 20, count 2 2006.285.09:44:12.90#ibcon#about to read 4, iclass 20, count 2 2006.285.09:44:12.90#ibcon#read 4, iclass 20, count 2 2006.285.09:44:12.90#ibcon#about to read 5, iclass 20, count 2 2006.285.09:44:12.90#ibcon#read 5, iclass 20, count 2 2006.285.09:44:12.90#ibcon#about to read 6, iclass 20, count 2 2006.285.09:44:12.90#ibcon#read 6, iclass 20, count 2 2006.285.09:44:12.90#ibcon#end of sib2, iclass 20, count 2 2006.285.09:44:12.90#ibcon#*mode == 0, iclass 20, count 2 2006.285.09:44:12.90#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.09:44:12.90#ibcon#[27=AT01-04\r\n] 2006.285.09:44:12.90#ibcon#*before write, iclass 20, count 2 2006.285.09:44:12.90#ibcon#enter sib2, iclass 20, count 2 2006.285.09:44:12.90#ibcon#flushed, iclass 20, count 2 2006.285.09:44:12.90#ibcon#about to write, iclass 20, count 2 2006.285.09:44:12.90#ibcon#wrote, iclass 20, count 2 2006.285.09:44:12.90#ibcon#about to read 3, iclass 20, count 2 2006.285.09:44:12.93#ibcon#read 3, iclass 20, count 2 2006.285.09:44:12.93#ibcon#about to read 4, iclass 20, count 2 2006.285.09:44:12.93#ibcon#read 4, iclass 20, count 2 2006.285.09:44:12.93#ibcon#about to read 5, iclass 20, count 2 2006.285.09:44:12.93#ibcon#read 5, iclass 20, count 2 2006.285.09:44:12.93#ibcon#about to read 6, iclass 20, count 2 2006.285.09:44:12.93#ibcon#read 6, iclass 20, count 2 2006.285.09:44:12.93#ibcon#end of sib2, iclass 20, count 2 2006.285.09:44:12.93#ibcon#*after write, iclass 20, count 2 2006.285.09:44:12.93#ibcon#*before return 0, iclass 20, count 2 2006.285.09:44:12.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:44:12.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:44:12.93#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.09:44:12.93#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:12.93#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:44:13.05#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:44:13.05#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:44:13.05#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:44:13.05#ibcon#first serial, iclass 20, count 0 2006.285.09:44:13.05#ibcon#enter sib2, iclass 20, count 0 2006.285.09:44:13.05#ibcon#flushed, iclass 20, count 0 2006.285.09:44:13.05#ibcon#about to write, iclass 20, count 0 2006.285.09:44:13.05#ibcon#wrote, iclass 20, count 0 2006.285.09:44:13.05#ibcon#about to read 3, iclass 20, count 0 2006.285.09:44:13.07#ibcon#read 3, iclass 20, count 0 2006.285.09:44:13.07#ibcon#about to read 4, iclass 20, count 0 2006.285.09:44:13.07#ibcon#read 4, iclass 20, count 0 2006.285.09:44:13.07#ibcon#about to read 5, iclass 20, count 0 2006.285.09:44:13.07#ibcon#read 5, iclass 20, count 0 2006.285.09:44:13.07#ibcon#about to read 6, iclass 20, count 0 2006.285.09:44:13.07#ibcon#read 6, iclass 20, count 0 2006.285.09:44:13.07#ibcon#end of sib2, iclass 20, count 0 2006.285.09:44:13.07#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:44:13.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:44:13.07#ibcon#[27=USB\r\n] 2006.285.09:44:13.07#ibcon#*before write, iclass 20, count 0 2006.285.09:44:13.07#ibcon#enter sib2, iclass 20, count 0 2006.285.09:44:13.07#ibcon#flushed, iclass 20, count 0 2006.285.09:44:13.07#ibcon#about to write, iclass 20, count 0 2006.285.09:44:13.07#ibcon#wrote, iclass 20, count 0 2006.285.09:44:13.07#ibcon#about to read 3, iclass 20, count 0 2006.285.09:44:13.10#ibcon#read 3, iclass 20, count 0 2006.285.09:44:13.10#ibcon#about to read 4, iclass 20, count 0 2006.285.09:44:13.10#ibcon#read 4, iclass 20, count 0 2006.285.09:44:13.10#ibcon#about to read 5, iclass 20, count 0 2006.285.09:44:13.10#ibcon#read 5, iclass 20, count 0 2006.285.09:44:13.10#ibcon#about to read 6, iclass 20, count 0 2006.285.09:44:13.10#ibcon#read 6, iclass 20, count 0 2006.285.09:44:13.10#ibcon#end of sib2, iclass 20, count 0 2006.285.09:44:13.10#ibcon#*after write, iclass 20, count 0 2006.285.09:44:13.10#ibcon#*before return 0, iclass 20, count 0 2006.285.09:44:13.10#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:44:13.10#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:44:13.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:44:13.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:44:13.10$vck44/vblo=2,634.99 2006.285.09:44:13.10#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.09:44:13.10#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.09:44:13.10#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:13.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:44:13.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:44:13.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:44:13.10#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:44:13.10#ibcon#first serial, iclass 22, count 0 2006.285.09:44:13.10#ibcon#enter sib2, iclass 22, count 0 2006.285.09:44:13.10#ibcon#flushed, iclass 22, count 0 2006.285.09:44:13.10#ibcon#about to write, iclass 22, count 0 2006.285.09:44:13.10#ibcon#wrote, iclass 22, count 0 2006.285.09:44:13.10#ibcon#about to read 3, iclass 22, count 0 2006.285.09:44:13.12#ibcon#read 3, iclass 22, count 0 2006.285.09:44:13.12#ibcon#about to read 4, iclass 22, count 0 2006.285.09:44:13.12#ibcon#read 4, iclass 22, count 0 2006.285.09:44:13.12#ibcon#about to read 5, iclass 22, count 0 2006.285.09:44:13.12#ibcon#read 5, iclass 22, count 0 2006.285.09:44:13.12#ibcon#about to read 6, iclass 22, count 0 2006.285.09:44:13.12#ibcon#read 6, iclass 22, count 0 2006.285.09:44:13.12#ibcon#end of sib2, iclass 22, count 0 2006.285.09:44:13.12#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:44:13.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:44:13.12#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:44:13.12#ibcon#*before write, iclass 22, count 0 2006.285.09:44:13.12#ibcon#enter sib2, iclass 22, count 0 2006.285.09:44:13.12#ibcon#flushed, iclass 22, count 0 2006.285.09:44:13.12#ibcon#about to write, iclass 22, count 0 2006.285.09:44:13.12#ibcon#wrote, iclass 22, count 0 2006.285.09:44:13.12#ibcon#about to read 3, iclass 22, count 0 2006.285.09:44:13.16#ibcon#read 3, iclass 22, count 0 2006.285.09:44:13.16#ibcon#about to read 4, iclass 22, count 0 2006.285.09:44:13.16#ibcon#read 4, iclass 22, count 0 2006.285.09:44:13.16#ibcon#about to read 5, iclass 22, count 0 2006.285.09:44:13.16#ibcon#read 5, iclass 22, count 0 2006.285.09:44:13.16#ibcon#about to read 6, iclass 22, count 0 2006.285.09:44:13.16#ibcon#read 6, iclass 22, count 0 2006.285.09:44:13.16#ibcon#end of sib2, iclass 22, count 0 2006.285.09:44:13.16#ibcon#*after write, iclass 22, count 0 2006.285.09:44:13.16#ibcon#*before return 0, iclass 22, count 0 2006.285.09:44:13.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:44:13.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:44:13.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:44:13.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:44:13.16$vck44/vb=2,5 2006.285.09:44:13.16#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.09:44:13.16#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.09:44:13.16#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:13.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:44:13.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:44:13.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:44:13.22#ibcon#enter wrdev, iclass 24, count 2 2006.285.09:44:13.22#ibcon#first serial, iclass 24, count 2 2006.285.09:44:13.22#ibcon#enter sib2, iclass 24, count 2 2006.285.09:44:13.22#ibcon#flushed, iclass 24, count 2 2006.285.09:44:13.22#ibcon#about to write, iclass 24, count 2 2006.285.09:44:13.22#ibcon#wrote, iclass 24, count 2 2006.285.09:44:13.22#ibcon#about to read 3, iclass 24, count 2 2006.285.09:44:13.24#ibcon#read 3, iclass 24, count 2 2006.285.09:44:13.24#ibcon#about to read 4, iclass 24, count 2 2006.285.09:44:13.24#ibcon#read 4, iclass 24, count 2 2006.285.09:44:13.24#ibcon#about to read 5, iclass 24, count 2 2006.285.09:44:13.24#ibcon#read 5, iclass 24, count 2 2006.285.09:44:13.24#ibcon#about to read 6, iclass 24, count 2 2006.285.09:44:13.24#ibcon#read 6, iclass 24, count 2 2006.285.09:44:13.24#ibcon#end of sib2, iclass 24, count 2 2006.285.09:44:13.24#ibcon#*mode == 0, iclass 24, count 2 2006.285.09:44:13.24#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.09:44:13.24#ibcon#[27=AT02-05\r\n] 2006.285.09:44:13.24#ibcon#*before write, iclass 24, count 2 2006.285.09:44:13.24#ibcon#enter sib2, iclass 24, count 2 2006.285.09:44:13.24#ibcon#flushed, iclass 24, count 2 2006.285.09:44:13.24#ibcon#about to write, iclass 24, count 2 2006.285.09:44:13.24#ibcon#wrote, iclass 24, count 2 2006.285.09:44:13.24#ibcon#about to read 3, iclass 24, count 2 2006.285.09:44:13.27#ibcon#read 3, iclass 24, count 2 2006.285.09:44:13.27#ibcon#about to read 4, iclass 24, count 2 2006.285.09:44:13.27#ibcon#read 4, iclass 24, count 2 2006.285.09:44:13.27#ibcon#about to read 5, iclass 24, count 2 2006.285.09:44:13.27#ibcon#read 5, iclass 24, count 2 2006.285.09:44:13.27#ibcon#about to read 6, iclass 24, count 2 2006.285.09:44:13.27#ibcon#read 6, iclass 24, count 2 2006.285.09:44:13.27#ibcon#end of sib2, iclass 24, count 2 2006.285.09:44:13.27#ibcon#*after write, iclass 24, count 2 2006.285.09:44:13.27#ibcon#*before return 0, iclass 24, count 2 2006.285.09:44:13.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:44:13.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:44:13.27#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.09:44:13.27#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:13.27#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:44:13.39#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:44:13.39#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:44:13.39#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:44:13.39#ibcon#first serial, iclass 24, count 0 2006.285.09:44:13.39#ibcon#enter sib2, iclass 24, count 0 2006.285.09:44:13.39#ibcon#flushed, iclass 24, count 0 2006.285.09:44:13.39#ibcon#about to write, iclass 24, count 0 2006.285.09:44:13.39#ibcon#wrote, iclass 24, count 0 2006.285.09:44:13.39#ibcon#about to read 3, iclass 24, count 0 2006.285.09:44:13.41#ibcon#read 3, iclass 24, count 0 2006.285.09:44:13.41#ibcon#about to read 4, iclass 24, count 0 2006.285.09:44:13.41#ibcon#read 4, iclass 24, count 0 2006.285.09:44:13.41#ibcon#about to read 5, iclass 24, count 0 2006.285.09:44:13.41#ibcon#read 5, iclass 24, count 0 2006.285.09:44:13.41#ibcon#about to read 6, iclass 24, count 0 2006.285.09:44:13.41#ibcon#read 6, iclass 24, count 0 2006.285.09:44:13.41#ibcon#end of sib2, iclass 24, count 0 2006.285.09:44:13.41#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:44:13.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:44:13.41#ibcon#[27=USB\r\n] 2006.285.09:44:13.41#ibcon#*before write, iclass 24, count 0 2006.285.09:44:13.41#ibcon#enter sib2, iclass 24, count 0 2006.285.09:44:13.41#ibcon#flushed, iclass 24, count 0 2006.285.09:44:13.41#ibcon#about to write, iclass 24, count 0 2006.285.09:44:13.41#ibcon#wrote, iclass 24, count 0 2006.285.09:44:13.41#ibcon#about to read 3, iclass 24, count 0 2006.285.09:44:13.44#ibcon#read 3, iclass 24, count 0 2006.285.09:44:13.44#ibcon#about to read 4, iclass 24, count 0 2006.285.09:44:13.44#ibcon#read 4, iclass 24, count 0 2006.285.09:44:13.44#ibcon#about to read 5, iclass 24, count 0 2006.285.09:44:13.44#ibcon#read 5, iclass 24, count 0 2006.285.09:44:13.44#ibcon#about to read 6, iclass 24, count 0 2006.285.09:44:13.44#ibcon#read 6, iclass 24, count 0 2006.285.09:44:13.44#ibcon#end of sib2, iclass 24, count 0 2006.285.09:44:13.44#ibcon#*after write, iclass 24, count 0 2006.285.09:44:13.44#ibcon#*before return 0, iclass 24, count 0 2006.285.09:44:13.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:44:13.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:44:13.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:44:13.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:44:13.44$vck44/vblo=3,649.99 2006.285.09:44:13.44#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.09:44:13.44#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.09:44:13.44#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:13.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:44:13.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:44:13.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:44:13.44#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:44:13.44#ibcon#first serial, iclass 26, count 0 2006.285.09:44:13.44#ibcon#enter sib2, iclass 26, count 0 2006.285.09:44:13.44#ibcon#flushed, iclass 26, count 0 2006.285.09:44:13.44#ibcon#about to write, iclass 26, count 0 2006.285.09:44:13.44#ibcon#wrote, iclass 26, count 0 2006.285.09:44:13.44#ibcon#about to read 3, iclass 26, count 0 2006.285.09:44:13.46#ibcon#read 3, iclass 26, count 0 2006.285.09:44:13.46#ibcon#about to read 4, iclass 26, count 0 2006.285.09:44:13.46#ibcon#read 4, iclass 26, count 0 2006.285.09:44:13.46#ibcon#about to read 5, iclass 26, count 0 2006.285.09:44:13.46#ibcon#read 5, iclass 26, count 0 2006.285.09:44:13.46#ibcon#about to read 6, iclass 26, count 0 2006.285.09:44:13.46#ibcon#read 6, iclass 26, count 0 2006.285.09:44:13.46#ibcon#end of sib2, iclass 26, count 0 2006.285.09:44:13.46#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:44:13.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:44:13.46#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:44:13.46#ibcon#*before write, iclass 26, count 0 2006.285.09:44:13.46#ibcon#enter sib2, iclass 26, count 0 2006.285.09:44:13.46#ibcon#flushed, iclass 26, count 0 2006.285.09:44:13.46#ibcon#about to write, iclass 26, count 0 2006.285.09:44:13.46#ibcon#wrote, iclass 26, count 0 2006.285.09:44:13.46#ibcon#about to read 3, iclass 26, count 0 2006.285.09:44:13.50#ibcon#read 3, iclass 26, count 0 2006.285.09:44:13.50#ibcon#about to read 4, iclass 26, count 0 2006.285.09:44:13.50#ibcon#read 4, iclass 26, count 0 2006.285.09:44:13.50#ibcon#about to read 5, iclass 26, count 0 2006.285.09:44:13.50#ibcon#read 5, iclass 26, count 0 2006.285.09:44:13.50#ibcon#about to read 6, iclass 26, count 0 2006.285.09:44:13.50#ibcon#read 6, iclass 26, count 0 2006.285.09:44:13.50#ibcon#end of sib2, iclass 26, count 0 2006.285.09:44:13.50#ibcon#*after write, iclass 26, count 0 2006.285.09:44:13.50#ibcon#*before return 0, iclass 26, count 0 2006.285.09:44:13.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:44:13.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:44:13.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:44:13.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:44:13.50$vck44/vb=3,4 2006.285.09:44:13.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.09:44:13.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.09:44:13.50#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:13.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:44:13.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:44:13.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:44:13.56#ibcon#enter wrdev, iclass 28, count 2 2006.285.09:44:13.56#ibcon#first serial, iclass 28, count 2 2006.285.09:44:13.56#ibcon#enter sib2, iclass 28, count 2 2006.285.09:44:13.56#ibcon#flushed, iclass 28, count 2 2006.285.09:44:13.56#ibcon#about to write, iclass 28, count 2 2006.285.09:44:13.56#ibcon#wrote, iclass 28, count 2 2006.285.09:44:13.56#ibcon#about to read 3, iclass 28, count 2 2006.285.09:44:13.58#ibcon#read 3, iclass 28, count 2 2006.285.09:44:13.58#ibcon#about to read 4, iclass 28, count 2 2006.285.09:44:13.58#ibcon#read 4, iclass 28, count 2 2006.285.09:44:13.58#ibcon#about to read 5, iclass 28, count 2 2006.285.09:44:13.58#ibcon#read 5, iclass 28, count 2 2006.285.09:44:13.58#ibcon#about to read 6, iclass 28, count 2 2006.285.09:44:13.58#ibcon#read 6, iclass 28, count 2 2006.285.09:44:13.58#ibcon#end of sib2, iclass 28, count 2 2006.285.09:44:13.58#ibcon#*mode == 0, iclass 28, count 2 2006.285.09:44:13.58#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.09:44:13.58#ibcon#[27=AT03-04\r\n] 2006.285.09:44:13.58#ibcon#*before write, iclass 28, count 2 2006.285.09:44:13.58#ibcon#enter sib2, iclass 28, count 2 2006.285.09:44:13.58#ibcon#flushed, iclass 28, count 2 2006.285.09:44:13.58#ibcon#about to write, iclass 28, count 2 2006.285.09:44:13.58#ibcon#wrote, iclass 28, count 2 2006.285.09:44:13.58#ibcon#about to read 3, iclass 28, count 2 2006.285.09:44:13.61#ibcon#read 3, iclass 28, count 2 2006.285.09:44:13.61#ibcon#about to read 4, iclass 28, count 2 2006.285.09:44:13.61#ibcon#read 4, iclass 28, count 2 2006.285.09:44:13.61#ibcon#about to read 5, iclass 28, count 2 2006.285.09:44:13.61#ibcon#read 5, iclass 28, count 2 2006.285.09:44:13.61#ibcon#about to read 6, iclass 28, count 2 2006.285.09:44:13.61#ibcon#read 6, iclass 28, count 2 2006.285.09:44:13.61#ibcon#end of sib2, iclass 28, count 2 2006.285.09:44:13.61#ibcon#*after write, iclass 28, count 2 2006.285.09:44:13.61#ibcon#*before return 0, iclass 28, count 2 2006.285.09:44:13.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:44:13.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:44:13.61#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.09:44:13.61#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:13.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:44:13.65#abcon#<5=/04 0.6 1.3 19.38 951015.2\r\n> 2006.285.09:44:13.67#abcon#{5=INTERFACE CLEAR} 2006.285.09:44:13.73#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:44:13.73#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:44:13.73#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:44:13.73#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:44:13.73#ibcon#first serial, iclass 28, count 0 2006.285.09:44:13.73#ibcon#enter sib2, iclass 28, count 0 2006.285.09:44:13.73#ibcon#flushed, iclass 28, count 0 2006.285.09:44:13.73#ibcon#about to write, iclass 28, count 0 2006.285.09:44:13.73#ibcon#wrote, iclass 28, count 0 2006.285.09:44:13.73#ibcon#about to read 3, iclass 28, count 0 2006.285.09:44:13.75#ibcon#read 3, iclass 28, count 0 2006.285.09:44:13.75#ibcon#about to read 4, iclass 28, count 0 2006.285.09:44:13.75#ibcon#read 4, iclass 28, count 0 2006.285.09:44:13.75#ibcon#about to read 5, iclass 28, count 0 2006.285.09:44:13.75#ibcon#read 5, iclass 28, count 0 2006.285.09:44:13.75#ibcon#about to read 6, iclass 28, count 0 2006.285.09:44:13.75#ibcon#read 6, iclass 28, count 0 2006.285.09:44:13.75#ibcon#end of sib2, iclass 28, count 0 2006.285.09:44:13.75#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:44:13.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:44:13.75#ibcon#[27=USB\r\n] 2006.285.09:44:13.75#ibcon#*before write, iclass 28, count 0 2006.285.09:44:13.75#ibcon#enter sib2, iclass 28, count 0 2006.285.09:44:13.75#ibcon#flushed, iclass 28, count 0 2006.285.09:44:13.75#ibcon#about to write, iclass 28, count 0 2006.285.09:44:13.75#ibcon#wrote, iclass 28, count 0 2006.285.09:44:13.75#ibcon#about to read 3, iclass 28, count 0 2006.285.09:44:13.78#ibcon#read 3, iclass 28, count 0 2006.285.09:44:13.78#ibcon#about to read 4, iclass 28, count 0 2006.285.09:44:13.78#ibcon#read 4, iclass 28, count 0 2006.285.09:44:13.78#ibcon#about to read 5, iclass 28, count 0 2006.285.09:44:13.78#ibcon#read 5, iclass 28, count 0 2006.285.09:44:13.78#ibcon#about to read 6, iclass 28, count 0 2006.285.09:44:13.78#ibcon#read 6, iclass 28, count 0 2006.285.09:44:13.78#ibcon#end of sib2, iclass 28, count 0 2006.285.09:44:13.78#ibcon#*after write, iclass 28, count 0 2006.285.09:44:13.78#ibcon#*before return 0, iclass 28, count 0 2006.285.09:44:13.78#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:44:13.78#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:44:13.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:44:13.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:44:13.78$vck44/vblo=4,679.99 2006.285.09:44:13.78#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.09:44:13.78#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.09:44:13.78#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:13.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:44:13.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:44:13.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:44:13.78#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:44:13.78#ibcon#first serial, iclass 34, count 0 2006.285.09:44:13.78#ibcon#enter sib2, iclass 34, count 0 2006.285.09:44:13.78#ibcon#flushed, iclass 34, count 0 2006.285.09:44:13.78#ibcon#about to write, iclass 34, count 0 2006.285.09:44:13.78#ibcon#wrote, iclass 34, count 0 2006.285.09:44:13.78#ibcon#about to read 3, iclass 34, count 0 2006.285.09:44:13.80#ibcon#read 3, iclass 34, count 0 2006.285.09:44:13.80#ibcon#about to read 4, iclass 34, count 0 2006.285.09:44:13.80#ibcon#read 4, iclass 34, count 0 2006.285.09:44:13.80#ibcon#about to read 5, iclass 34, count 0 2006.285.09:44:13.80#ibcon#read 5, iclass 34, count 0 2006.285.09:44:13.80#ibcon#about to read 6, iclass 34, count 0 2006.285.09:44:13.80#ibcon#read 6, iclass 34, count 0 2006.285.09:44:13.80#ibcon#end of sib2, iclass 34, count 0 2006.285.09:44:13.80#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:44:13.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:44:13.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:44:13.80#ibcon#*before write, iclass 34, count 0 2006.285.09:44:13.80#ibcon#enter sib2, iclass 34, count 0 2006.285.09:44:13.80#ibcon#flushed, iclass 34, count 0 2006.285.09:44:13.80#ibcon#about to write, iclass 34, count 0 2006.285.09:44:13.80#ibcon#wrote, iclass 34, count 0 2006.285.09:44:13.80#ibcon#about to read 3, iclass 34, count 0 2006.285.09:44:13.84#ibcon#read 3, iclass 34, count 0 2006.285.09:44:13.84#ibcon#about to read 4, iclass 34, count 0 2006.285.09:44:13.84#ibcon#read 4, iclass 34, count 0 2006.285.09:44:13.84#ibcon#about to read 5, iclass 34, count 0 2006.285.09:44:13.84#ibcon#read 5, iclass 34, count 0 2006.285.09:44:13.84#ibcon#about to read 6, iclass 34, count 0 2006.285.09:44:13.84#ibcon#read 6, iclass 34, count 0 2006.285.09:44:13.84#ibcon#end of sib2, iclass 34, count 0 2006.285.09:44:13.84#ibcon#*after write, iclass 34, count 0 2006.285.09:44:13.84#ibcon#*before return 0, iclass 34, count 0 2006.285.09:44:13.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:44:13.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:44:13.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:44:13.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:44:13.84$vck44/vb=4,5 2006.285.09:44:13.84#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.09:44:13.84#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.09:44:13.84#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:13.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:44:13.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:44:13.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:44:13.90#ibcon#enter wrdev, iclass 36, count 2 2006.285.09:44:13.90#ibcon#first serial, iclass 36, count 2 2006.285.09:44:13.90#ibcon#enter sib2, iclass 36, count 2 2006.285.09:44:13.90#ibcon#flushed, iclass 36, count 2 2006.285.09:44:13.90#ibcon#about to write, iclass 36, count 2 2006.285.09:44:13.90#ibcon#wrote, iclass 36, count 2 2006.285.09:44:13.90#ibcon#about to read 3, iclass 36, count 2 2006.285.09:44:13.92#ibcon#read 3, iclass 36, count 2 2006.285.09:44:13.92#ibcon#about to read 4, iclass 36, count 2 2006.285.09:44:13.92#ibcon#read 4, iclass 36, count 2 2006.285.09:44:13.92#ibcon#about to read 5, iclass 36, count 2 2006.285.09:44:13.92#ibcon#read 5, iclass 36, count 2 2006.285.09:44:13.92#ibcon#about to read 6, iclass 36, count 2 2006.285.09:44:13.92#ibcon#read 6, iclass 36, count 2 2006.285.09:44:13.92#ibcon#end of sib2, iclass 36, count 2 2006.285.09:44:13.92#ibcon#*mode == 0, iclass 36, count 2 2006.285.09:44:13.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.09:44:13.92#ibcon#[27=AT04-05\r\n] 2006.285.09:44:13.92#ibcon#*before write, iclass 36, count 2 2006.285.09:44:13.92#ibcon#enter sib2, iclass 36, count 2 2006.285.09:44:13.92#ibcon#flushed, iclass 36, count 2 2006.285.09:44:13.92#ibcon#about to write, iclass 36, count 2 2006.285.09:44:13.92#ibcon#wrote, iclass 36, count 2 2006.285.09:44:13.92#ibcon#about to read 3, iclass 36, count 2 2006.285.09:44:13.95#ibcon#read 3, iclass 36, count 2 2006.285.09:44:13.95#ibcon#about to read 4, iclass 36, count 2 2006.285.09:44:13.95#ibcon#read 4, iclass 36, count 2 2006.285.09:44:13.95#ibcon#about to read 5, iclass 36, count 2 2006.285.09:44:13.95#ibcon#read 5, iclass 36, count 2 2006.285.09:44:13.95#ibcon#about to read 6, iclass 36, count 2 2006.285.09:44:13.95#ibcon#read 6, iclass 36, count 2 2006.285.09:44:13.95#ibcon#end of sib2, iclass 36, count 2 2006.285.09:44:13.95#ibcon#*after write, iclass 36, count 2 2006.285.09:44:13.95#ibcon#*before return 0, iclass 36, count 2 2006.285.09:44:13.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:44:13.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:44:13.95#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.09:44:13.95#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:13.95#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:44:14.07#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:44:14.07#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:44:14.07#ibcon#enter wrdev, iclass 36, count 0 2006.285.09:44:14.07#ibcon#first serial, iclass 36, count 0 2006.285.09:44:14.07#ibcon#enter sib2, iclass 36, count 0 2006.285.09:44:14.07#ibcon#flushed, iclass 36, count 0 2006.285.09:44:14.07#ibcon#about to write, iclass 36, count 0 2006.285.09:44:14.07#ibcon#wrote, iclass 36, count 0 2006.285.09:44:14.07#ibcon#about to read 3, iclass 36, count 0 2006.285.09:44:14.09#ibcon#read 3, iclass 36, count 0 2006.285.09:44:14.09#ibcon#about to read 4, iclass 36, count 0 2006.285.09:44:14.09#ibcon#read 4, iclass 36, count 0 2006.285.09:44:14.09#ibcon#about to read 5, iclass 36, count 0 2006.285.09:44:14.09#ibcon#read 5, iclass 36, count 0 2006.285.09:44:14.09#ibcon#about to read 6, iclass 36, count 0 2006.285.09:44:14.09#ibcon#read 6, iclass 36, count 0 2006.285.09:44:14.09#ibcon#end of sib2, iclass 36, count 0 2006.285.09:44:14.09#ibcon#*mode == 0, iclass 36, count 0 2006.285.09:44:14.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.09:44:14.09#ibcon#[27=USB\r\n] 2006.285.09:44:14.09#ibcon#*before write, iclass 36, count 0 2006.285.09:44:14.09#ibcon#enter sib2, iclass 36, count 0 2006.285.09:44:14.09#ibcon#flushed, iclass 36, count 0 2006.285.09:44:14.09#ibcon#about to write, iclass 36, count 0 2006.285.09:44:14.09#ibcon#wrote, iclass 36, count 0 2006.285.09:44:14.09#ibcon#about to read 3, iclass 36, count 0 2006.285.09:44:14.12#ibcon#read 3, iclass 36, count 0 2006.285.09:44:14.12#ibcon#about to read 4, iclass 36, count 0 2006.285.09:44:14.12#ibcon#read 4, iclass 36, count 0 2006.285.09:44:14.12#ibcon#about to read 5, iclass 36, count 0 2006.285.09:44:14.12#ibcon#read 5, iclass 36, count 0 2006.285.09:44:14.12#ibcon#about to read 6, iclass 36, count 0 2006.285.09:44:14.12#ibcon#read 6, iclass 36, count 0 2006.285.09:44:14.12#ibcon#end of sib2, iclass 36, count 0 2006.285.09:44:14.12#ibcon#*after write, iclass 36, count 0 2006.285.09:44:14.12#ibcon#*before return 0, iclass 36, count 0 2006.285.09:44:14.12#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:44:14.12#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:44:14.12#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.09:44:14.12#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.09:44:14.12$vck44/vblo=5,709.99 2006.285.09:44:14.12#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.09:44:14.12#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.09:44:14.12#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:14.12#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:44:14.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:44:14.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:44:14.12#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:44:14.12#ibcon#first serial, iclass 38, count 0 2006.285.09:44:14.12#ibcon#enter sib2, iclass 38, count 0 2006.285.09:44:14.12#ibcon#flushed, iclass 38, count 0 2006.285.09:44:14.12#ibcon#about to write, iclass 38, count 0 2006.285.09:44:14.12#ibcon#wrote, iclass 38, count 0 2006.285.09:44:14.12#ibcon#about to read 3, iclass 38, count 0 2006.285.09:44:14.14#ibcon#read 3, iclass 38, count 0 2006.285.09:44:14.14#ibcon#about to read 4, iclass 38, count 0 2006.285.09:44:14.14#ibcon#read 4, iclass 38, count 0 2006.285.09:44:14.14#ibcon#about to read 5, iclass 38, count 0 2006.285.09:44:14.14#ibcon#read 5, iclass 38, count 0 2006.285.09:44:14.14#ibcon#about to read 6, iclass 38, count 0 2006.285.09:44:14.14#ibcon#read 6, iclass 38, count 0 2006.285.09:44:14.14#ibcon#end of sib2, iclass 38, count 0 2006.285.09:44:14.14#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:44:14.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:44:14.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:44:14.14#ibcon#*before write, iclass 38, count 0 2006.285.09:44:14.14#ibcon#enter sib2, iclass 38, count 0 2006.285.09:44:14.14#ibcon#flushed, iclass 38, count 0 2006.285.09:44:14.14#ibcon#about to write, iclass 38, count 0 2006.285.09:44:14.14#ibcon#wrote, iclass 38, count 0 2006.285.09:44:14.14#ibcon#about to read 3, iclass 38, count 0 2006.285.09:44:14.18#ibcon#read 3, iclass 38, count 0 2006.285.09:44:14.18#ibcon#about to read 4, iclass 38, count 0 2006.285.09:44:14.18#ibcon#read 4, iclass 38, count 0 2006.285.09:44:14.18#ibcon#about to read 5, iclass 38, count 0 2006.285.09:44:14.18#ibcon#read 5, iclass 38, count 0 2006.285.09:44:14.18#ibcon#about to read 6, iclass 38, count 0 2006.285.09:44:14.18#ibcon#read 6, iclass 38, count 0 2006.285.09:44:14.18#ibcon#end of sib2, iclass 38, count 0 2006.285.09:44:14.18#ibcon#*after write, iclass 38, count 0 2006.285.09:44:14.18#ibcon#*before return 0, iclass 38, count 0 2006.285.09:44:14.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:44:14.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:44:14.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:44:14.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:44:14.18$vck44/vb=5,4 2006.285.09:44:14.18#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.09:44:14.18#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.09:44:14.18#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:14.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:44:14.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:44:14.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:44:14.24#ibcon#enter wrdev, iclass 40, count 2 2006.285.09:44:14.24#ibcon#first serial, iclass 40, count 2 2006.285.09:44:14.24#ibcon#enter sib2, iclass 40, count 2 2006.285.09:44:14.24#ibcon#flushed, iclass 40, count 2 2006.285.09:44:14.24#ibcon#about to write, iclass 40, count 2 2006.285.09:44:14.24#ibcon#wrote, iclass 40, count 2 2006.285.09:44:14.24#ibcon#about to read 3, iclass 40, count 2 2006.285.09:44:14.26#ibcon#read 3, iclass 40, count 2 2006.285.09:44:14.26#ibcon#about to read 4, iclass 40, count 2 2006.285.09:44:14.26#ibcon#read 4, iclass 40, count 2 2006.285.09:44:14.26#ibcon#about to read 5, iclass 40, count 2 2006.285.09:44:14.26#ibcon#read 5, iclass 40, count 2 2006.285.09:44:14.26#ibcon#about to read 6, iclass 40, count 2 2006.285.09:44:14.26#ibcon#read 6, iclass 40, count 2 2006.285.09:44:14.26#ibcon#end of sib2, iclass 40, count 2 2006.285.09:44:14.26#ibcon#*mode == 0, iclass 40, count 2 2006.285.09:44:14.26#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.09:44:14.26#ibcon#[27=AT05-04\r\n] 2006.285.09:44:14.26#ibcon#*before write, iclass 40, count 2 2006.285.09:44:14.26#ibcon#enter sib2, iclass 40, count 2 2006.285.09:44:14.26#ibcon#flushed, iclass 40, count 2 2006.285.09:44:14.26#ibcon#about to write, iclass 40, count 2 2006.285.09:44:14.26#ibcon#wrote, iclass 40, count 2 2006.285.09:44:14.26#ibcon#about to read 3, iclass 40, count 2 2006.285.09:44:14.29#ibcon#read 3, iclass 40, count 2 2006.285.09:44:14.29#ibcon#about to read 4, iclass 40, count 2 2006.285.09:44:14.29#ibcon#read 4, iclass 40, count 2 2006.285.09:44:14.29#ibcon#about to read 5, iclass 40, count 2 2006.285.09:44:14.29#ibcon#read 5, iclass 40, count 2 2006.285.09:44:14.29#ibcon#about to read 6, iclass 40, count 2 2006.285.09:44:14.29#ibcon#read 6, iclass 40, count 2 2006.285.09:44:14.29#ibcon#end of sib2, iclass 40, count 2 2006.285.09:44:14.29#ibcon#*after write, iclass 40, count 2 2006.285.09:44:14.29#ibcon#*before return 0, iclass 40, count 2 2006.285.09:44:14.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:44:14.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:44:14.29#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.09:44:14.29#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:14.29#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:44:14.41#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:44:14.41#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:44:14.41#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:44:14.41#ibcon#first serial, iclass 40, count 0 2006.285.09:44:14.41#ibcon#enter sib2, iclass 40, count 0 2006.285.09:44:14.41#ibcon#flushed, iclass 40, count 0 2006.285.09:44:14.41#ibcon#about to write, iclass 40, count 0 2006.285.09:44:14.41#ibcon#wrote, iclass 40, count 0 2006.285.09:44:14.41#ibcon#about to read 3, iclass 40, count 0 2006.285.09:44:14.43#ibcon#read 3, iclass 40, count 0 2006.285.09:44:14.43#ibcon#about to read 4, iclass 40, count 0 2006.285.09:44:14.43#ibcon#read 4, iclass 40, count 0 2006.285.09:44:14.43#ibcon#about to read 5, iclass 40, count 0 2006.285.09:44:14.43#ibcon#read 5, iclass 40, count 0 2006.285.09:44:14.43#ibcon#about to read 6, iclass 40, count 0 2006.285.09:44:14.43#ibcon#read 6, iclass 40, count 0 2006.285.09:44:14.43#ibcon#end of sib2, iclass 40, count 0 2006.285.09:44:14.43#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:44:14.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:44:14.43#ibcon#[27=USB\r\n] 2006.285.09:44:14.43#ibcon#*before write, iclass 40, count 0 2006.285.09:44:14.43#ibcon#enter sib2, iclass 40, count 0 2006.285.09:44:14.43#ibcon#flushed, iclass 40, count 0 2006.285.09:44:14.43#ibcon#about to write, iclass 40, count 0 2006.285.09:44:14.43#ibcon#wrote, iclass 40, count 0 2006.285.09:44:14.43#ibcon#about to read 3, iclass 40, count 0 2006.285.09:44:14.46#ibcon#read 3, iclass 40, count 0 2006.285.09:44:14.46#ibcon#about to read 4, iclass 40, count 0 2006.285.09:44:14.46#ibcon#read 4, iclass 40, count 0 2006.285.09:44:14.46#ibcon#about to read 5, iclass 40, count 0 2006.285.09:44:14.46#ibcon#read 5, iclass 40, count 0 2006.285.09:44:14.46#ibcon#about to read 6, iclass 40, count 0 2006.285.09:44:14.46#ibcon#read 6, iclass 40, count 0 2006.285.09:44:14.46#ibcon#end of sib2, iclass 40, count 0 2006.285.09:44:14.46#ibcon#*after write, iclass 40, count 0 2006.285.09:44:14.46#ibcon#*before return 0, iclass 40, count 0 2006.285.09:44:14.46#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:44:14.46#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:44:14.46#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:44:14.46#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:44:14.46$vck44/vblo=6,719.99 2006.285.09:44:14.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.09:44:14.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.09:44:14.46#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:14.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:44:14.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:44:14.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:44:14.46#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:44:14.46#ibcon#first serial, iclass 4, count 0 2006.285.09:44:14.46#ibcon#enter sib2, iclass 4, count 0 2006.285.09:44:14.46#ibcon#flushed, iclass 4, count 0 2006.285.09:44:14.46#ibcon#about to write, iclass 4, count 0 2006.285.09:44:14.46#ibcon#wrote, iclass 4, count 0 2006.285.09:44:14.46#ibcon#about to read 3, iclass 4, count 0 2006.285.09:44:14.48#ibcon#read 3, iclass 4, count 0 2006.285.09:44:14.48#ibcon#about to read 4, iclass 4, count 0 2006.285.09:44:14.48#ibcon#read 4, iclass 4, count 0 2006.285.09:44:14.48#ibcon#about to read 5, iclass 4, count 0 2006.285.09:44:14.48#ibcon#read 5, iclass 4, count 0 2006.285.09:44:14.48#ibcon#about to read 6, iclass 4, count 0 2006.285.09:44:14.48#ibcon#read 6, iclass 4, count 0 2006.285.09:44:14.48#ibcon#end of sib2, iclass 4, count 0 2006.285.09:44:14.48#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:44:14.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:44:14.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:44:14.48#ibcon#*before write, iclass 4, count 0 2006.285.09:44:14.48#ibcon#enter sib2, iclass 4, count 0 2006.285.09:44:14.48#ibcon#flushed, iclass 4, count 0 2006.285.09:44:14.48#ibcon#about to write, iclass 4, count 0 2006.285.09:44:14.48#ibcon#wrote, iclass 4, count 0 2006.285.09:44:14.48#ibcon#about to read 3, iclass 4, count 0 2006.285.09:44:14.52#ibcon#read 3, iclass 4, count 0 2006.285.09:44:14.52#ibcon#about to read 4, iclass 4, count 0 2006.285.09:44:14.52#ibcon#read 4, iclass 4, count 0 2006.285.09:44:14.52#ibcon#about to read 5, iclass 4, count 0 2006.285.09:44:14.52#ibcon#read 5, iclass 4, count 0 2006.285.09:44:14.52#ibcon#about to read 6, iclass 4, count 0 2006.285.09:44:14.52#ibcon#read 6, iclass 4, count 0 2006.285.09:44:14.52#ibcon#end of sib2, iclass 4, count 0 2006.285.09:44:14.52#ibcon#*after write, iclass 4, count 0 2006.285.09:44:14.52#ibcon#*before return 0, iclass 4, count 0 2006.285.09:44:14.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:44:14.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:44:14.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:44:14.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:44:14.52$vck44/vb=6,3 2006.285.09:44:14.52#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.09:44:14.52#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.09:44:14.52#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:14.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:44:14.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:44:14.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:44:14.58#ibcon#enter wrdev, iclass 6, count 2 2006.285.09:44:14.58#ibcon#first serial, iclass 6, count 2 2006.285.09:44:14.58#ibcon#enter sib2, iclass 6, count 2 2006.285.09:44:14.58#ibcon#flushed, iclass 6, count 2 2006.285.09:44:14.58#ibcon#about to write, iclass 6, count 2 2006.285.09:44:14.58#ibcon#wrote, iclass 6, count 2 2006.285.09:44:14.58#ibcon#about to read 3, iclass 6, count 2 2006.285.09:44:14.60#ibcon#read 3, iclass 6, count 2 2006.285.09:44:14.60#ibcon#about to read 4, iclass 6, count 2 2006.285.09:44:14.60#ibcon#read 4, iclass 6, count 2 2006.285.09:44:14.60#ibcon#about to read 5, iclass 6, count 2 2006.285.09:44:14.60#ibcon#read 5, iclass 6, count 2 2006.285.09:44:14.60#ibcon#about to read 6, iclass 6, count 2 2006.285.09:44:14.60#ibcon#read 6, iclass 6, count 2 2006.285.09:44:14.60#ibcon#end of sib2, iclass 6, count 2 2006.285.09:44:14.60#ibcon#*mode == 0, iclass 6, count 2 2006.285.09:44:14.60#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.09:44:14.60#ibcon#[27=AT06-03\r\n] 2006.285.09:44:14.60#ibcon#*before write, iclass 6, count 2 2006.285.09:44:14.60#ibcon#enter sib2, iclass 6, count 2 2006.285.09:44:14.60#ibcon#flushed, iclass 6, count 2 2006.285.09:44:14.60#ibcon#about to write, iclass 6, count 2 2006.285.09:44:14.60#ibcon#wrote, iclass 6, count 2 2006.285.09:44:14.60#ibcon#about to read 3, iclass 6, count 2 2006.285.09:44:14.63#ibcon#read 3, iclass 6, count 2 2006.285.09:44:14.63#ibcon#about to read 4, iclass 6, count 2 2006.285.09:44:14.63#ibcon#read 4, iclass 6, count 2 2006.285.09:44:14.63#ibcon#about to read 5, iclass 6, count 2 2006.285.09:44:14.63#ibcon#read 5, iclass 6, count 2 2006.285.09:44:14.63#ibcon#about to read 6, iclass 6, count 2 2006.285.09:44:14.63#ibcon#read 6, iclass 6, count 2 2006.285.09:44:14.63#ibcon#end of sib2, iclass 6, count 2 2006.285.09:44:14.63#ibcon#*after write, iclass 6, count 2 2006.285.09:44:14.63#ibcon#*before return 0, iclass 6, count 2 2006.285.09:44:14.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:44:14.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:44:14.63#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.09:44:14.63#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:14.63#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:44:14.75#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:44:14.75#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:44:14.75#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:44:14.75#ibcon#first serial, iclass 6, count 0 2006.285.09:44:14.75#ibcon#enter sib2, iclass 6, count 0 2006.285.09:44:14.75#ibcon#flushed, iclass 6, count 0 2006.285.09:44:14.75#ibcon#about to write, iclass 6, count 0 2006.285.09:44:14.75#ibcon#wrote, iclass 6, count 0 2006.285.09:44:14.75#ibcon#about to read 3, iclass 6, count 0 2006.285.09:44:14.77#ibcon#read 3, iclass 6, count 0 2006.285.09:44:14.77#ibcon#about to read 4, iclass 6, count 0 2006.285.09:44:14.77#ibcon#read 4, iclass 6, count 0 2006.285.09:44:14.77#ibcon#about to read 5, iclass 6, count 0 2006.285.09:44:14.77#ibcon#read 5, iclass 6, count 0 2006.285.09:44:14.77#ibcon#about to read 6, iclass 6, count 0 2006.285.09:44:14.77#ibcon#read 6, iclass 6, count 0 2006.285.09:44:14.77#ibcon#end of sib2, iclass 6, count 0 2006.285.09:44:14.77#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:44:14.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:44:14.77#ibcon#[27=USB\r\n] 2006.285.09:44:14.77#ibcon#*before write, iclass 6, count 0 2006.285.09:44:14.77#ibcon#enter sib2, iclass 6, count 0 2006.285.09:44:14.77#ibcon#flushed, iclass 6, count 0 2006.285.09:44:14.77#ibcon#about to write, iclass 6, count 0 2006.285.09:44:14.77#ibcon#wrote, iclass 6, count 0 2006.285.09:44:14.77#ibcon#about to read 3, iclass 6, count 0 2006.285.09:44:14.80#ibcon#read 3, iclass 6, count 0 2006.285.09:44:14.80#ibcon#about to read 4, iclass 6, count 0 2006.285.09:44:14.80#ibcon#read 4, iclass 6, count 0 2006.285.09:44:14.80#ibcon#about to read 5, iclass 6, count 0 2006.285.09:44:14.80#ibcon#read 5, iclass 6, count 0 2006.285.09:44:14.80#ibcon#about to read 6, iclass 6, count 0 2006.285.09:44:14.80#ibcon#read 6, iclass 6, count 0 2006.285.09:44:14.80#ibcon#end of sib2, iclass 6, count 0 2006.285.09:44:14.80#ibcon#*after write, iclass 6, count 0 2006.285.09:44:14.80#ibcon#*before return 0, iclass 6, count 0 2006.285.09:44:14.80#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:44:14.80#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:44:14.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:44:14.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:44:14.80$vck44/vblo=7,734.99 2006.285.09:44:14.80#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.09:44:14.80#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.09:44:14.80#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:14.80#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:44:14.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:44:14.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:44:14.80#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:44:14.80#ibcon#first serial, iclass 10, count 0 2006.285.09:44:14.80#ibcon#enter sib2, iclass 10, count 0 2006.285.09:44:14.80#ibcon#flushed, iclass 10, count 0 2006.285.09:44:14.80#ibcon#about to write, iclass 10, count 0 2006.285.09:44:14.80#ibcon#wrote, iclass 10, count 0 2006.285.09:44:14.80#ibcon#about to read 3, iclass 10, count 0 2006.285.09:44:14.82#ibcon#read 3, iclass 10, count 0 2006.285.09:44:14.82#ibcon#about to read 4, iclass 10, count 0 2006.285.09:44:14.82#ibcon#read 4, iclass 10, count 0 2006.285.09:44:14.82#ibcon#about to read 5, iclass 10, count 0 2006.285.09:44:14.82#ibcon#read 5, iclass 10, count 0 2006.285.09:44:14.82#ibcon#about to read 6, iclass 10, count 0 2006.285.09:44:14.82#ibcon#read 6, iclass 10, count 0 2006.285.09:44:14.82#ibcon#end of sib2, iclass 10, count 0 2006.285.09:44:14.82#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:44:14.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:44:14.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:44:14.82#ibcon#*before write, iclass 10, count 0 2006.285.09:44:14.82#ibcon#enter sib2, iclass 10, count 0 2006.285.09:44:14.82#ibcon#flushed, iclass 10, count 0 2006.285.09:44:14.82#ibcon#about to write, iclass 10, count 0 2006.285.09:44:14.82#ibcon#wrote, iclass 10, count 0 2006.285.09:44:14.82#ibcon#about to read 3, iclass 10, count 0 2006.285.09:44:14.86#ibcon#read 3, iclass 10, count 0 2006.285.09:44:14.86#ibcon#about to read 4, iclass 10, count 0 2006.285.09:44:14.86#ibcon#read 4, iclass 10, count 0 2006.285.09:44:14.86#ibcon#about to read 5, iclass 10, count 0 2006.285.09:44:14.86#ibcon#read 5, iclass 10, count 0 2006.285.09:44:14.86#ibcon#about to read 6, iclass 10, count 0 2006.285.09:44:14.86#ibcon#read 6, iclass 10, count 0 2006.285.09:44:14.86#ibcon#end of sib2, iclass 10, count 0 2006.285.09:44:14.86#ibcon#*after write, iclass 10, count 0 2006.285.09:44:14.86#ibcon#*before return 0, iclass 10, count 0 2006.285.09:44:14.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:44:14.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:44:14.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:44:14.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:44:14.86$vck44/vb=7,4 2006.285.09:44:14.86#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.09:44:14.86#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.09:44:14.86#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:14.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:44:14.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:44:14.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:44:14.92#ibcon#enter wrdev, iclass 12, count 2 2006.285.09:44:14.92#ibcon#first serial, iclass 12, count 2 2006.285.09:44:14.92#ibcon#enter sib2, iclass 12, count 2 2006.285.09:44:14.92#ibcon#flushed, iclass 12, count 2 2006.285.09:44:14.92#ibcon#about to write, iclass 12, count 2 2006.285.09:44:14.92#ibcon#wrote, iclass 12, count 2 2006.285.09:44:14.92#ibcon#about to read 3, iclass 12, count 2 2006.285.09:44:14.94#ibcon#read 3, iclass 12, count 2 2006.285.09:44:14.94#ibcon#about to read 4, iclass 12, count 2 2006.285.09:44:14.94#ibcon#read 4, iclass 12, count 2 2006.285.09:44:14.94#ibcon#about to read 5, iclass 12, count 2 2006.285.09:44:14.94#ibcon#read 5, iclass 12, count 2 2006.285.09:44:14.94#ibcon#about to read 6, iclass 12, count 2 2006.285.09:44:14.94#ibcon#read 6, iclass 12, count 2 2006.285.09:44:14.94#ibcon#end of sib2, iclass 12, count 2 2006.285.09:44:14.94#ibcon#*mode == 0, iclass 12, count 2 2006.285.09:44:14.94#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.09:44:14.94#ibcon#[27=AT07-04\r\n] 2006.285.09:44:14.94#ibcon#*before write, iclass 12, count 2 2006.285.09:44:14.94#ibcon#enter sib2, iclass 12, count 2 2006.285.09:44:14.94#ibcon#flushed, iclass 12, count 2 2006.285.09:44:14.94#ibcon#about to write, iclass 12, count 2 2006.285.09:44:14.94#ibcon#wrote, iclass 12, count 2 2006.285.09:44:14.94#ibcon#about to read 3, iclass 12, count 2 2006.285.09:44:14.97#ibcon#read 3, iclass 12, count 2 2006.285.09:44:14.97#ibcon#about to read 4, iclass 12, count 2 2006.285.09:44:14.97#ibcon#read 4, iclass 12, count 2 2006.285.09:44:14.97#ibcon#about to read 5, iclass 12, count 2 2006.285.09:44:14.97#ibcon#read 5, iclass 12, count 2 2006.285.09:44:14.97#ibcon#about to read 6, iclass 12, count 2 2006.285.09:44:14.97#ibcon#read 6, iclass 12, count 2 2006.285.09:44:14.97#ibcon#end of sib2, iclass 12, count 2 2006.285.09:44:14.97#ibcon#*after write, iclass 12, count 2 2006.285.09:44:14.97#ibcon#*before return 0, iclass 12, count 2 2006.285.09:44:14.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:44:14.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:44:14.97#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.09:44:14.97#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:14.97#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:44:15.09#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:44:15.09#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:44:15.09#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:44:15.09#ibcon#first serial, iclass 12, count 0 2006.285.09:44:15.09#ibcon#enter sib2, iclass 12, count 0 2006.285.09:44:15.09#ibcon#flushed, iclass 12, count 0 2006.285.09:44:15.09#ibcon#about to write, iclass 12, count 0 2006.285.09:44:15.09#ibcon#wrote, iclass 12, count 0 2006.285.09:44:15.09#ibcon#about to read 3, iclass 12, count 0 2006.285.09:44:15.11#ibcon#read 3, iclass 12, count 0 2006.285.09:44:15.11#ibcon#about to read 4, iclass 12, count 0 2006.285.09:44:15.11#ibcon#read 4, iclass 12, count 0 2006.285.09:44:15.11#ibcon#about to read 5, iclass 12, count 0 2006.285.09:44:15.11#ibcon#read 5, iclass 12, count 0 2006.285.09:44:15.11#ibcon#about to read 6, iclass 12, count 0 2006.285.09:44:15.11#ibcon#read 6, iclass 12, count 0 2006.285.09:44:15.11#ibcon#end of sib2, iclass 12, count 0 2006.285.09:44:15.11#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:44:15.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:44:15.11#ibcon#[27=USB\r\n] 2006.285.09:44:15.11#ibcon#*before write, iclass 12, count 0 2006.285.09:44:15.11#ibcon#enter sib2, iclass 12, count 0 2006.285.09:44:15.11#ibcon#flushed, iclass 12, count 0 2006.285.09:44:15.11#ibcon#about to write, iclass 12, count 0 2006.285.09:44:15.11#ibcon#wrote, iclass 12, count 0 2006.285.09:44:15.11#ibcon#about to read 3, iclass 12, count 0 2006.285.09:44:15.14#ibcon#read 3, iclass 12, count 0 2006.285.09:44:15.14#ibcon#about to read 4, iclass 12, count 0 2006.285.09:44:15.14#ibcon#read 4, iclass 12, count 0 2006.285.09:44:15.14#ibcon#about to read 5, iclass 12, count 0 2006.285.09:44:15.14#ibcon#read 5, iclass 12, count 0 2006.285.09:44:15.14#ibcon#about to read 6, iclass 12, count 0 2006.285.09:44:15.14#ibcon#read 6, iclass 12, count 0 2006.285.09:44:15.14#ibcon#end of sib2, iclass 12, count 0 2006.285.09:44:15.14#ibcon#*after write, iclass 12, count 0 2006.285.09:44:15.14#ibcon#*before return 0, iclass 12, count 0 2006.285.09:44:15.14#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:44:15.14#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:44:15.14#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:44:15.14#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:44:15.14$vck44/vblo=8,744.99 2006.285.09:44:15.14#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.09:44:15.14#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.09:44:15.14#ibcon#ireg 17 cls_cnt 0 2006.285.09:44:15.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:44:15.14#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:44:15.14#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:44:15.14#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:44:15.14#ibcon#first serial, iclass 14, count 0 2006.285.09:44:15.14#ibcon#enter sib2, iclass 14, count 0 2006.285.09:44:15.14#ibcon#flushed, iclass 14, count 0 2006.285.09:44:15.14#ibcon#about to write, iclass 14, count 0 2006.285.09:44:15.14#ibcon#wrote, iclass 14, count 0 2006.285.09:44:15.14#ibcon#about to read 3, iclass 14, count 0 2006.285.09:44:15.16#ibcon#read 3, iclass 14, count 0 2006.285.09:44:15.16#ibcon#about to read 4, iclass 14, count 0 2006.285.09:44:15.16#ibcon#read 4, iclass 14, count 0 2006.285.09:44:15.16#ibcon#about to read 5, iclass 14, count 0 2006.285.09:44:15.16#ibcon#read 5, iclass 14, count 0 2006.285.09:44:15.16#ibcon#about to read 6, iclass 14, count 0 2006.285.09:44:15.16#ibcon#read 6, iclass 14, count 0 2006.285.09:44:15.16#ibcon#end of sib2, iclass 14, count 0 2006.285.09:44:15.16#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:44:15.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:44:15.16#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:44:15.16#ibcon#*before write, iclass 14, count 0 2006.285.09:44:15.16#ibcon#enter sib2, iclass 14, count 0 2006.285.09:44:15.16#ibcon#flushed, iclass 14, count 0 2006.285.09:44:15.16#ibcon#about to write, iclass 14, count 0 2006.285.09:44:15.16#ibcon#wrote, iclass 14, count 0 2006.285.09:44:15.16#ibcon#about to read 3, iclass 14, count 0 2006.285.09:44:15.20#ibcon#read 3, iclass 14, count 0 2006.285.09:44:15.20#ibcon#about to read 4, iclass 14, count 0 2006.285.09:44:15.20#ibcon#read 4, iclass 14, count 0 2006.285.09:44:15.20#ibcon#about to read 5, iclass 14, count 0 2006.285.09:44:15.20#ibcon#read 5, iclass 14, count 0 2006.285.09:44:15.20#ibcon#about to read 6, iclass 14, count 0 2006.285.09:44:15.20#ibcon#read 6, iclass 14, count 0 2006.285.09:44:15.20#ibcon#end of sib2, iclass 14, count 0 2006.285.09:44:15.20#ibcon#*after write, iclass 14, count 0 2006.285.09:44:15.20#ibcon#*before return 0, iclass 14, count 0 2006.285.09:44:15.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:44:15.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:44:15.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:44:15.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:44:15.20$vck44/vb=8,4 2006.285.09:44:15.20#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.09:44:15.20#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.09:44:15.20#ibcon#ireg 11 cls_cnt 2 2006.285.09:44:15.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:44:15.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:44:15.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:44:15.26#ibcon#enter wrdev, iclass 16, count 2 2006.285.09:44:15.26#ibcon#first serial, iclass 16, count 2 2006.285.09:44:15.26#ibcon#enter sib2, iclass 16, count 2 2006.285.09:44:15.26#ibcon#flushed, iclass 16, count 2 2006.285.09:44:15.26#ibcon#about to write, iclass 16, count 2 2006.285.09:44:15.26#ibcon#wrote, iclass 16, count 2 2006.285.09:44:15.26#ibcon#about to read 3, iclass 16, count 2 2006.285.09:44:15.28#ibcon#read 3, iclass 16, count 2 2006.285.09:44:15.28#ibcon#about to read 4, iclass 16, count 2 2006.285.09:44:15.28#ibcon#read 4, iclass 16, count 2 2006.285.09:44:15.28#ibcon#about to read 5, iclass 16, count 2 2006.285.09:44:15.28#ibcon#read 5, iclass 16, count 2 2006.285.09:44:15.28#ibcon#about to read 6, iclass 16, count 2 2006.285.09:44:15.28#ibcon#read 6, iclass 16, count 2 2006.285.09:44:15.28#ibcon#end of sib2, iclass 16, count 2 2006.285.09:44:15.28#ibcon#*mode == 0, iclass 16, count 2 2006.285.09:44:15.28#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.09:44:15.28#ibcon#[27=AT08-04\r\n] 2006.285.09:44:15.28#ibcon#*before write, iclass 16, count 2 2006.285.09:44:15.28#ibcon#enter sib2, iclass 16, count 2 2006.285.09:44:15.28#ibcon#flushed, iclass 16, count 2 2006.285.09:44:15.28#ibcon#about to write, iclass 16, count 2 2006.285.09:44:15.28#ibcon#wrote, iclass 16, count 2 2006.285.09:44:15.28#ibcon#about to read 3, iclass 16, count 2 2006.285.09:44:15.31#ibcon#read 3, iclass 16, count 2 2006.285.09:44:15.31#ibcon#about to read 4, iclass 16, count 2 2006.285.09:44:15.31#ibcon#read 4, iclass 16, count 2 2006.285.09:44:15.31#ibcon#about to read 5, iclass 16, count 2 2006.285.09:44:15.31#ibcon#read 5, iclass 16, count 2 2006.285.09:44:15.31#ibcon#about to read 6, iclass 16, count 2 2006.285.09:44:15.31#ibcon#read 6, iclass 16, count 2 2006.285.09:44:15.31#ibcon#end of sib2, iclass 16, count 2 2006.285.09:44:15.31#ibcon#*after write, iclass 16, count 2 2006.285.09:44:15.31#ibcon#*before return 0, iclass 16, count 2 2006.285.09:44:15.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:44:15.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:44:15.31#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.09:44:15.31#ibcon#ireg 7 cls_cnt 0 2006.285.09:44:15.31#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:44:15.43#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:44:15.43#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:44:15.43#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:44:15.43#ibcon#first serial, iclass 16, count 0 2006.285.09:44:15.43#ibcon#enter sib2, iclass 16, count 0 2006.285.09:44:15.43#ibcon#flushed, iclass 16, count 0 2006.285.09:44:15.43#ibcon#about to write, iclass 16, count 0 2006.285.09:44:15.43#ibcon#wrote, iclass 16, count 0 2006.285.09:44:15.43#ibcon#about to read 3, iclass 16, count 0 2006.285.09:44:15.45#ibcon#read 3, iclass 16, count 0 2006.285.09:44:15.45#ibcon#about to read 4, iclass 16, count 0 2006.285.09:44:15.45#ibcon#read 4, iclass 16, count 0 2006.285.09:44:15.45#ibcon#about to read 5, iclass 16, count 0 2006.285.09:44:15.45#ibcon#read 5, iclass 16, count 0 2006.285.09:44:15.45#ibcon#about to read 6, iclass 16, count 0 2006.285.09:44:15.45#ibcon#read 6, iclass 16, count 0 2006.285.09:44:15.45#ibcon#end of sib2, iclass 16, count 0 2006.285.09:44:15.45#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:44:15.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:44:15.45#ibcon#[27=USB\r\n] 2006.285.09:44:15.45#ibcon#*before write, iclass 16, count 0 2006.285.09:44:15.45#ibcon#enter sib2, iclass 16, count 0 2006.285.09:44:15.45#ibcon#flushed, iclass 16, count 0 2006.285.09:44:15.45#ibcon#about to write, iclass 16, count 0 2006.285.09:44:15.45#ibcon#wrote, iclass 16, count 0 2006.285.09:44:15.45#ibcon#about to read 3, iclass 16, count 0 2006.285.09:44:15.48#ibcon#read 3, iclass 16, count 0 2006.285.09:44:15.48#ibcon#about to read 4, iclass 16, count 0 2006.285.09:44:15.48#ibcon#read 4, iclass 16, count 0 2006.285.09:44:15.48#ibcon#about to read 5, iclass 16, count 0 2006.285.09:44:15.48#ibcon#read 5, iclass 16, count 0 2006.285.09:44:15.48#ibcon#about to read 6, iclass 16, count 0 2006.285.09:44:15.48#ibcon#read 6, iclass 16, count 0 2006.285.09:44:15.48#ibcon#end of sib2, iclass 16, count 0 2006.285.09:44:15.48#ibcon#*after write, iclass 16, count 0 2006.285.09:44:15.48#ibcon#*before return 0, iclass 16, count 0 2006.285.09:44:15.48#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:44:15.48#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:44:15.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:44:15.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:44:15.48$vck44/vabw=wide 2006.285.09:44:15.48#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.09:44:15.48#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.09:44:15.48#ibcon#ireg 8 cls_cnt 0 2006.285.09:44:15.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:44:15.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:44:15.48#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:44:15.48#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:44:15.48#ibcon#first serial, iclass 18, count 0 2006.285.09:44:15.48#ibcon#enter sib2, iclass 18, count 0 2006.285.09:44:15.48#ibcon#flushed, iclass 18, count 0 2006.285.09:44:15.48#ibcon#about to write, iclass 18, count 0 2006.285.09:44:15.48#ibcon#wrote, iclass 18, count 0 2006.285.09:44:15.48#ibcon#about to read 3, iclass 18, count 0 2006.285.09:44:15.50#ibcon#read 3, iclass 18, count 0 2006.285.09:44:15.50#ibcon#about to read 4, iclass 18, count 0 2006.285.09:44:15.50#ibcon#read 4, iclass 18, count 0 2006.285.09:44:15.50#ibcon#about to read 5, iclass 18, count 0 2006.285.09:44:15.50#ibcon#read 5, iclass 18, count 0 2006.285.09:44:15.50#ibcon#about to read 6, iclass 18, count 0 2006.285.09:44:15.50#ibcon#read 6, iclass 18, count 0 2006.285.09:44:15.50#ibcon#end of sib2, iclass 18, count 0 2006.285.09:44:15.50#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:44:15.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:44:15.50#ibcon#[25=BW32\r\n] 2006.285.09:44:15.50#ibcon#*before write, iclass 18, count 0 2006.285.09:44:15.50#ibcon#enter sib2, iclass 18, count 0 2006.285.09:44:15.50#ibcon#flushed, iclass 18, count 0 2006.285.09:44:15.50#ibcon#about to write, iclass 18, count 0 2006.285.09:44:15.50#ibcon#wrote, iclass 18, count 0 2006.285.09:44:15.50#ibcon#about to read 3, iclass 18, count 0 2006.285.09:44:15.53#ibcon#read 3, iclass 18, count 0 2006.285.09:44:15.53#ibcon#about to read 4, iclass 18, count 0 2006.285.09:44:15.53#ibcon#read 4, iclass 18, count 0 2006.285.09:44:15.53#ibcon#about to read 5, iclass 18, count 0 2006.285.09:44:15.53#ibcon#read 5, iclass 18, count 0 2006.285.09:44:15.53#ibcon#about to read 6, iclass 18, count 0 2006.285.09:44:15.53#ibcon#read 6, iclass 18, count 0 2006.285.09:44:15.53#ibcon#end of sib2, iclass 18, count 0 2006.285.09:44:15.53#ibcon#*after write, iclass 18, count 0 2006.285.09:44:15.53#ibcon#*before return 0, iclass 18, count 0 2006.285.09:44:15.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:44:15.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:44:15.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:44:15.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:44:15.53$vck44/vbbw=wide 2006.285.09:44:15.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.09:44:15.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.09:44:15.53#ibcon#ireg 8 cls_cnt 0 2006.285.09:44:15.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:44:15.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:44:15.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:44:15.60#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:44:15.60#ibcon#first serial, iclass 20, count 0 2006.285.09:44:15.60#ibcon#enter sib2, iclass 20, count 0 2006.285.09:44:15.60#ibcon#flushed, iclass 20, count 0 2006.285.09:44:15.60#ibcon#about to write, iclass 20, count 0 2006.285.09:44:15.60#ibcon#wrote, iclass 20, count 0 2006.285.09:44:15.60#ibcon#about to read 3, iclass 20, count 0 2006.285.09:44:15.62#ibcon#read 3, iclass 20, count 0 2006.285.09:44:15.62#ibcon#about to read 4, iclass 20, count 0 2006.285.09:44:15.62#ibcon#read 4, iclass 20, count 0 2006.285.09:44:15.62#ibcon#about to read 5, iclass 20, count 0 2006.285.09:44:15.62#ibcon#read 5, iclass 20, count 0 2006.285.09:44:15.62#ibcon#about to read 6, iclass 20, count 0 2006.285.09:44:15.62#ibcon#read 6, iclass 20, count 0 2006.285.09:44:15.62#ibcon#end of sib2, iclass 20, count 0 2006.285.09:44:15.62#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:44:15.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:44:15.62#ibcon#[27=BW32\r\n] 2006.285.09:44:15.62#ibcon#*before write, iclass 20, count 0 2006.285.09:44:15.62#ibcon#enter sib2, iclass 20, count 0 2006.285.09:44:15.62#ibcon#flushed, iclass 20, count 0 2006.285.09:44:15.62#ibcon#about to write, iclass 20, count 0 2006.285.09:44:15.62#ibcon#wrote, iclass 20, count 0 2006.285.09:44:15.62#ibcon#about to read 3, iclass 20, count 0 2006.285.09:44:15.65#ibcon#read 3, iclass 20, count 0 2006.285.09:44:15.65#ibcon#about to read 4, iclass 20, count 0 2006.285.09:44:15.65#ibcon#read 4, iclass 20, count 0 2006.285.09:44:15.65#ibcon#about to read 5, iclass 20, count 0 2006.285.09:44:15.65#ibcon#read 5, iclass 20, count 0 2006.285.09:44:15.65#ibcon#about to read 6, iclass 20, count 0 2006.285.09:44:15.65#ibcon#read 6, iclass 20, count 0 2006.285.09:44:15.65#ibcon#end of sib2, iclass 20, count 0 2006.285.09:44:15.65#ibcon#*after write, iclass 20, count 0 2006.285.09:44:15.65#ibcon#*before return 0, iclass 20, count 0 2006.285.09:44:15.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:44:15.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:44:15.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:44:15.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:44:15.65$setupk4/ifdk4 2006.285.09:44:15.65$ifdk4/lo= 2006.285.09:44:15.65$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:44:15.65$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:44:15.65$ifdk4/patch= 2006.285.09:44:15.65$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:44:15.65$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:44:15.65$setupk4/!*+20s 2006.285.09:44:23.82#abcon#<5=/04 0.6 1.3 19.39 951015.2\r\n> 2006.285.09:44:23.84#abcon#{5=INTERFACE CLEAR} 2006.285.09:44:23.90#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:44:30.16$setupk4/"tpicd 2006.285.09:44:30.16$setupk4/echo=off 2006.285.09:44:30.16$setupk4/xlog=off 2006.285.09:44:30.16:!2006.285.09:49:51 2006.285.09:44:55.14#trakl#Source acquired 2006.285.09:44:55.14#flagr#flagr/antenna,acquired 2006.285.09:49:51.00:preob 2006.285.09:49:51.14/onsource/TRACKING 2006.285.09:49:51.14:!2006.285.09:50:01 2006.285.09:50:01.00:"tape 2006.285.09:50:01.00:"st=record 2006.285.09:50:01.00:data_valid=on 2006.285.09:50:01.00:midob 2006.285.09:50:01.14/onsource/TRACKING 2006.285.09:50:01.14/wx/19.39,1015.2,95 2006.285.09:50:01.28/cable/+6.4864E-03 2006.285.09:50:02.37/va/01,07,usb,yes,32,35 2006.285.09:50:02.37/va/02,06,usb,yes,33,33 2006.285.09:50:02.37/va/03,07,usb,yes,32,34 2006.285.09:50:02.37/va/04,06,usb,yes,34,35 2006.285.09:50:02.37/va/05,03,usb,yes,33,33 2006.285.09:50:02.37/va/06,04,usb,yes,30,29 2006.285.09:50:02.37/va/07,04,usb,yes,30,31 2006.285.09:50:02.37/va/08,03,usb,yes,31,38 2006.285.09:50:02.60/valo/01,524.99,yes,locked 2006.285.09:50:02.60/valo/02,534.99,yes,locked 2006.285.09:50:02.60/valo/03,564.99,yes,locked 2006.285.09:50:02.60/valo/04,624.99,yes,locked 2006.285.09:50:02.60/valo/05,734.99,yes,locked 2006.285.09:50:02.60/valo/06,814.99,yes,locked 2006.285.09:50:02.60/valo/07,864.99,yes,locked 2006.285.09:50:02.60/valo/08,884.99,yes,locked 2006.285.09:50:03.69/vb/01,04,usb,yes,32,29 2006.285.09:50:03.69/vb/02,05,usb,yes,29,30 2006.285.09:50:03.69/vb/03,04,usb,yes,30,34 2006.285.09:50:03.69/vb/04,05,usb,yes,30,29 2006.285.09:50:03.69/vb/05,04,usb,yes,27,29 2006.285.09:50:03.69/vb/06,03,usb,yes,38,34 2006.285.09:50:03.69/vb/07,04,usb,yes,31,31 2006.285.09:50:03.69/vb/08,04,usb,yes,28,32 2006.285.09:50:03.93/vblo/01,629.99,yes,locked 2006.285.09:50:03.93/vblo/02,634.99,yes,locked 2006.285.09:50:03.93/vblo/03,649.99,yes,locked 2006.285.09:50:03.93/vblo/04,679.99,yes,locked 2006.285.09:50:03.93/vblo/05,709.99,yes,locked 2006.285.09:50:03.93/vblo/06,719.99,yes,locked 2006.285.09:50:03.93/vblo/07,734.99,yes,locked 2006.285.09:50:03.93/vblo/08,744.99,yes,locked 2006.285.09:50:04.08/vabw/8 2006.285.09:50:04.23/vbbw/8 2006.285.09:50:04.32/xfe/off,on,12.2 2006.285.09:50:04.71/ifatt/23,28,28,28 2006.285.09:50:05.08/fmout-gps/S +2.49E-07 2006.285.09:50:05.10:!2006.285.09:50:41 2006.285.09:50:41.00:data_valid=off 2006.285.09:50:41.00:"et 2006.285.09:50:41.00:!+3s 2006.285.09:50:44.01:"tape 2006.285.09:50:44.01:postob 2006.285.09:50:44.23/cable/+6.4842E-03 2006.285.09:50:44.23/wx/19.38,1015.2,95 2006.285.09:50:45.08/fmout-gps/S +2.47E-07 2006.285.09:50:45.08:scan_name=285-0952,jd0610,70 2006.285.09:50:45.08:source=2121+053,212344.52,053522.1,2000.0,cw 2006.285.09:50:46.14#flagr#flagr/antenna,new-source 2006.285.09:50:46.14:checkk5 2006.285.09:50:46.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:50:46.96/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:50:47.56/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:50:47.96/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:50:48.37/chk_obsdata//k5ts1/T2850950??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.09:50:48.79/chk_obsdata//k5ts2/T2850950??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.09:50:49.17/chk_obsdata//k5ts3/T2850950??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.09:50:49.57/chk_obsdata//k5ts4/T2850950??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.09:50:50.30/k5log//k5ts1_log_newline 2006.285.09:50:51.07/k5log//k5ts2_log_newline 2006.285.09:50:51.83/k5log//k5ts3_log_newline 2006.285.09:50:52.70/k5log//k5ts4_log_newline 2006.285.09:50:52.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:50:52.73:setupk4=1 2006.285.09:50:52.73$setupk4/echo=on 2006.285.09:50:52.73$setupk4/pcalon 2006.285.09:50:52.73$pcalon/"no phase cal control is implemented here 2006.285.09:50:52.73$setupk4/"tpicd=stop 2006.285.09:50:52.73$setupk4/"rec=synch_on 2006.285.09:50:52.73$setupk4/"rec_mode=128 2006.285.09:50:52.73$setupk4/!* 2006.285.09:50:52.73$setupk4/recpk4 2006.285.09:50:52.73$recpk4/recpatch= 2006.285.09:50:52.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:50:52.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:50:52.73$setupk4/vck44 2006.285.09:50:52.73$vck44/valo=1,524.99 2006.285.09:50:52.73#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.09:50:52.73#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.09:50:52.73#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:52.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:50:52.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:50:52.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:50:52.73#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:50:52.73#ibcon#first serial, iclass 28, count 0 2006.285.09:50:52.73#ibcon#enter sib2, iclass 28, count 0 2006.285.09:50:52.73#ibcon#flushed, iclass 28, count 0 2006.285.09:50:52.73#ibcon#about to write, iclass 28, count 0 2006.285.09:50:52.73#ibcon#wrote, iclass 28, count 0 2006.285.09:50:52.73#ibcon#about to read 3, iclass 28, count 0 2006.285.09:50:52.75#ibcon#read 3, iclass 28, count 0 2006.285.09:50:52.75#ibcon#about to read 4, iclass 28, count 0 2006.285.09:50:52.75#ibcon#read 4, iclass 28, count 0 2006.285.09:50:52.75#ibcon#about to read 5, iclass 28, count 0 2006.285.09:50:52.75#ibcon#read 5, iclass 28, count 0 2006.285.09:50:52.75#ibcon#about to read 6, iclass 28, count 0 2006.285.09:50:52.75#ibcon#read 6, iclass 28, count 0 2006.285.09:50:52.75#ibcon#end of sib2, iclass 28, count 0 2006.285.09:50:52.75#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:50:52.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:50:52.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:50:52.75#ibcon#*before write, iclass 28, count 0 2006.285.09:50:52.75#ibcon#enter sib2, iclass 28, count 0 2006.285.09:50:52.75#ibcon#flushed, iclass 28, count 0 2006.285.09:50:52.75#ibcon#about to write, iclass 28, count 0 2006.285.09:50:52.75#ibcon#wrote, iclass 28, count 0 2006.285.09:50:52.75#ibcon#about to read 3, iclass 28, count 0 2006.285.09:50:52.80#ibcon#read 3, iclass 28, count 0 2006.285.09:50:52.80#ibcon#about to read 4, iclass 28, count 0 2006.285.09:50:52.80#ibcon#read 4, iclass 28, count 0 2006.285.09:50:52.80#ibcon#about to read 5, iclass 28, count 0 2006.285.09:50:52.80#ibcon#read 5, iclass 28, count 0 2006.285.09:50:52.80#ibcon#about to read 6, iclass 28, count 0 2006.285.09:50:52.80#ibcon#read 6, iclass 28, count 0 2006.285.09:50:52.80#ibcon#end of sib2, iclass 28, count 0 2006.285.09:50:52.80#ibcon#*after write, iclass 28, count 0 2006.285.09:50:52.80#ibcon#*before return 0, iclass 28, count 0 2006.285.09:50:52.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:50:52.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:50:52.80#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:50:52.80#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:50:52.80$vck44/va=1,7 2006.285.09:50:52.80#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.09:50:52.80#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.09:50:52.80#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:52.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:50:52.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:50:52.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:50:52.80#ibcon#enter wrdev, iclass 30, count 2 2006.285.09:50:52.80#ibcon#first serial, iclass 30, count 2 2006.285.09:50:52.80#ibcon#enter sib2, iclass 30, count 2 2006.285.09:50:52.80#ibcon#flushed, iclass 30, count 2 2006.285.09:50:52.80#ibcon#about to write, iclass 30, count 2 2006.285.09:50:52.80#ibcon#wrote, iclass 30, count 2 2006.285.09:50:52.80#ibcon#about to read 3, iclass 30, count 2 2006.285.09:50:52.82#ibcon#read 3, iclass 30, count 2 2006.285.09:50:52.82#ibcon#about to read 4, iclass 30, count 2 2006.285.09:50:52.82#ibcon#read 4, iclass 30, count 2 2006.285.09:50:52.82#ibcon#about to read 5, iclass 30, count 2 2006.285.09:50:52.82#ibcon#read 5, iclass 30, count 2 2006.285.09:50:52.82#ibcon#about to read 6, iclass 30, count 2 2006.285.09:50:52.82#ibcon#read 6, iclass 30, count 2 2006.285.09:50:52.82#ibcon#end of sib2, iclass 30, count 2 2006.285.09:50:52.82#ibcon#*mode == 0, iclass 30, count 2 2006.285.09:50:52.82#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.09:50:52.82#ibcon#[25=AT01-07\r\n] 2006.285.09:50:52.82#ibcon#*before write, iclass 30, count 2 2006.285.09:50:52.82#ibcon#enter sib2, iclass 30, count 2 2006.285.09:50:52.82#ibcon#flushed, iclass 30, count 2 2006.285.09:50:52.82#ibcon#about to write, iclass 30, count 2 2006.285.09:50:52.82#ibcon#wrote, iclass 30, count 2 2006.285.09:50:52.82#ibcon#about to read 3, iclass 30, count 2 2006.285.09:50:52.85#ibcon#read 3, iclass 30, count 2 2006.285.09:50:52.85#ibcon#about to read 4, iclass 30, count 2 2006.285.09:50:52.85#ibcon#read 4, iclass 30, count 2 2006.285.09:50:52.85#ibcon#about to read 5, iclass 30, count 2 2006.285.09:50:52.85#ibcon#read 5, iclass 30, count 2 2006.285.09:50:52.85#ibcon#about to read 6, iclass 30, count 2 2006.285.09:50:52.85#ibcon#read 6, iclass 30, count 2 2006.285.09:50:52.85#ibcon#end of sib2, iclass 30, count 2 2006.285.09:50:52.85#ibcon#*after write, iclass 30, count 2 2006.285.09:50:52.85#ibcon#*before return 0, iclass 30, count 2 2006.285.09:50:52.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:50:52.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:50:52.85#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.09:50:52.85#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:52.85#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:50:52.97#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:50:52.97#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:50:52.97#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:50:52.97#ibcon#first serial, iclass 30, count 0 2006.285.09:50:52.97#ibcon#enter sib2, iclass 30, count 0 2006.285.09:50:52.97#ibcon#flushed, iclass 30, count 0 2006.285.09:50:52.97#ibcon#about to write, iclass 30, count 0 2006.285.09:50:52.97#ibcon#wrote, iclass 30, count 0 2006.285.09:50:52.97#ibcon#about to read 3, iclass 30, count 0 2006.285.09:50:52.99#ibcon#read 3, iclass 30, count 0 2006.285.09:50:52.99#ibcon#about to read 4, iclass 30, count 0 2006.285.09:50:52.99#ibcon#read 4, iclass 30, count 0 2006.285.09:50:52.99#ibcon#about to read 5, iclass 30, count 0 2006.285.09:50:52.99#ibcon#read 5, iclass 30, count 0 2006.285.09:50:52.99#ibcon#about to read 6, iclass 30, count 0 2006.285.09:50:52.99#ibcon#read 6, iclass 30, count 0 2006.285.09:50:52.99#ibcon#end of sib2, iclass 30, count 0 2006.285.09:50:52.99#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:50:52.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:50:52.99#ibcon#[25=USB\r\n] 2006.285.09:50:52.99#ibcon#*before write, iclass 30, count 0 2006.285.09:50:52.99#ibcon#enter sib2, iclass 30, count 0 2006.285.09:50:52.99#ibcon#flushed, iclass 30, count 0 2006.285.09:50:52.99#ibcon#about to write, iclass 30, count 0 2006.285.09:50:52.99#ibcon#wrote, iclass 30, count 0 2006.285.09:50:52.99#ibcon#about to read 3, iclass 30, count 0 2006.285.09:50:53.02#ibcon#read 3, iclass 30, count 0 2006.285.09:50:53.02#ibcon#about to read 4, iclass 30, count 0 2006.285.09:50:53.02#ibcon#read 4, iclass 30, count 0 2006.285.09:50:53.02#ibcon#about to read 5, iclass 30, count 0 2006.285.09:50:53.02#ibcon#read 5, iclass 30, count 0 2006.285.09:50:53.02#ibcon#about to read 6, iclass 30, count 0 2006.285.09:50:53.02#ibcon#read 6, iclass 30, count 0 2006.285.09:50:53.02#ibcon#end of sib2, iclass 30, count 0 2006.285.09:50:53.02#ibcon#*after write, iclass 30, count 0 2006.285.09:50:53.02#ibcon#*before return 0, iclass 30, count 0 2006.285.09:50:53.02#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:50:53.02#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:50:53.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:50:53.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:50:53.02$vck44/valo=2,534.99 2006.285.09:50:53.02#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.09:50:53.02#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.09:50:53.02#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:53.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:50:53.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:50:53.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:50:53.02#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:50:53.02#ibcon#first serial, iclass 32, count 0 2006.285.09:50:53.02#ibcon#enter sib2, iclass 32, count 0 2006.285.09:50:53.02#ibcon#flushed, iclass 32, count 0 2006.285.09:50:53.02#ibcon#about to write, iclass 32, count 0 2006.285.09:50:53.02#ibcon#wrote, iclass 32, count 0 2006.285.09:50:53.02#ibcon#about to read 3, iclass 32, count 0 2006.285.09:50:53.04#ibcon#read 3, iclass 32, count 0 2006.285.09:50:53.04#ibcon#about to read 4, iclass 32, count 0 2006.285.09:50:53.04#ibcon#read 4, iclass 32, count 0 2006.285.09:50:53.04#ibcon#about to read 5, iclass 32, count 0 2006.285.09:50:53.04#ibcon#read 5, iclass 32, count 0 2006.285.09:50:53.04#ibcon#about to read 6, iclass 32, count 0 2006.285.09:50:53.04#ibcon#read 6, iclass 32, count 0 2006.285.09:50:53.04#ibcon#end of sib2, iclass 32, count 0 2006.285.09:50:53.04#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:50:53.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:50:53.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:50:53.04#ibcon#*before write, iclass 32, count 0 2006.285.09:50:53.04#ibcon#enter sib2, iclass 32, count 0 2006.285.09:50:53.04#ibcon#flushed, iclass 32, count 0 2006.285.09:50:53.04#ibcon#about to write, iclass 32, count 0 2006.285.09:50:53.04#ibcon#wrote, iclass 32, count 0 2006.285.09:50:53.04#ibcon#about to read 3, iclass 32, count 0 2006.285.09:50:53.08#ibcon#read 3, iclass 32, count 0 2006.285.09:50:53.08#ibcon#about to read 4, iclass 32, count 0 2006.285.09:50:53.08#ibcon#read 4, iclass 32, count 0 2006.285.09:50:53.08#ibcon#about to read 5, iclass 32, count 0 2006.285.09:50:53.08#ibcon#read 5, iclass 32, count 0 2006.285.09:50:53.08#ibcon#about to read 6, iclass 32, count 0 2006.285.09:50:53.08#ibcon#read 6, iclass 32, count 0 2006.285.09:50:53.08#ibcon#end of sib2, iclass 32, count 0 2006.285.09:50:53.08#ibcon#*after write, iclass 32, count 0 2006.285.09:50:53.08#ibcon#*before return 0, iclass 32, count 0 2006.285.09:50:53.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:50:53.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:50:53.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:50:53.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:50:53.08$vck44/va=2,6 2006.285.09:50:53.08#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.09:50:53.08#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.09:50:53.08#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:53.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:50:53.11#abcon#<5=/05 0.9 1.3 19.38 951015.2\r\n> 2006.285.09:50:53.13#abcon#{5=INTERFACE CLEAR} 2006.285.09:50:53.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:50:53.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:50:53.14#ibcon#enter wrdev, iclass 35, count 2 2006.285.09:50:53.14#ibcon#first serial, iclass 35, count 2 2006.285.09:50:53.14#ibcon#enter sib2, iclass 35, count 2 2006.285.09:50:53.14#ibcon#flushed, iclass 35, count 2 2006.285.09:50:53.14#ibcon#about to write, iclass 35, count 2 2006.285.09:50:53.14#ibcon#wrote, iclass 35, count 2 2006.285.09:50:53.14#ibcon#about to read 3, iclass 35, count 2 2006.285.09:50:53.16#ibcon#read 3, iclass 35, count 2 2006.285.09:50:53.16#ibcon#about to read 4, iclass 35, count 2 2006.285.09:50:53.16#ibcon#read 4, iclass 35, count 2 2006.285.09:50:53.16#ibcon#about to read 5, iclass 35, count 2 2006.285.09:50:53.16#ibcon#read 5, iclass 35, count 2 2006.285.09:50:53.16#ibcon#about to read 6, iclass 35, count 2 2006.285.09:50:53.16#ibcon#read 6, iclass 35, count 2 2006.285.09:50:53.16#ibcon#end of sib2, iclass 35, count 2 2006.285.09:50:53.16#ibcon#*mode == 0, iclass 35, count 2 2006.285.09:50:53.16#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.09:50:53.16#ibcon#[25=AT02-06\r\n] 2006.285.09:50:53.16#ibcon#*before write, iclass 35, count 2 2006.285.09:50:53.16#ibcon#enter sib2, iclass 35, count 2 2006.285.09:50:53.16#ibcon#flushed, iclass 35, count 2 2006.285.09:50:53.16#ibcon#about to write, iclass 35, count 2 2006.285.09:50:53.16#ibcon#wrote, iclass 35, count 2 2006.285.09:50:53.16#ibcon#about to read 3, iclass 35, count 2 2006.285.09:50:53.19#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:50:53.19#ibcon#read 3, iclass 35, count 2 2006.285.09:50:53.19#ibcon#about to read 4, iclass 35, count 2 2006.285.09:50:53.19#ibcon#read 4, iclass 35, count 2 2006.285.09:50:53.19#ibcon#about to read 5, iclass 35, count 2 2006.285.09:50:53.19#ibcon#read 5, iclass 35, count 2 2006.285.09:50:53.19#ibcon#about to read 6, iclass 35, count 2 2006.285.09:50:53.19#ibcon#read 6, iclass 35, count 2 2006.285.09:50:53.19#ibcon#end of sib2, iclass 35, count 2 2006.285.09:50:53.19#ibcon#*after write, iclass 35, count 2 2006.285.09:50:53.19#ibcon#*before return 0, iclass 35, count 2 2006.285.09:50:53.19#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:50:53.19#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.09:50:53.19#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.09:50:53.19#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:53.19#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:50:53.31#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:50:53.31#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:50:53.31#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:50:53.31#ibcon#first serial, iclass 35, count 0 2006.285.09:50:53.31#ibcon#enter sib2, iclass 35, count 0 2006.285.09:50:53.31#ibcon#flushed, iclass 35, count 0 2006.285.09:50:53.31#ibcon#about to write, iclass 35, count 0 2006.285.09:50:53.31#ibcon#wrote, iclass 35, count 0 2006.285.09:50:53.31#ibcon#about to read 3, iclass 35, count 0 2006.285.09:50:53.33#ibcon#read 3, iclass 35, count 0 2006.285.09:50:53.33#ibcon#about to read 4, iclass 35, count 0 2006.285.09:50:53.33#ibcon#read 4, iclass 35, count 0 2006.285.09:50:53.33#ibcon#about to read 5, iclass 35, count 0 2006.285.09:50:53.33#ibcon#read 5, iclass 35, count 0 2006.285.09:50:53.33#ibcon#about to read 6, iclass 35, count 0 2006.285.09:50:53.33#ibcon#read 6, iclass 35, count 0 2006.285.09:50:53.33#ibcon#end of sib2, iclass 35, count 0 2006.285.09:50:53.33#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:50:53.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:50:53.33#ibcon#[25=USB\r\n] 2006.285.09:50:53.33#ibcon#*before write, iclass 35, count 0 2006.285.09:50:53.33#ibcon#enter sib2, iclass 35, count 0 2006.285.09:50:53.33#ibcon#flushed, iclass 35, count 0 2006.285.09:50:53.33#ibcon#about to write, iclass 35, count 0 2006.285.09:50:53.33#ibcon#wrote, iclass 35, count 0 2006.285.09:50:53.33#ibcon#about to read 3, iclass 35, count 0 2006.285.09:50:53.36#ibcon#read 3, iclass 35, count 0 2006.285.09:50:53.36#ibcon#about to read 4, iclass 35, count 0 2006.285.09:50:53.36#ibcon#read 4, iclass 35, count 0 2006.285.09:50:53.36#ibcon#about to read 5, iclass 35, count 0 2006.285.09:50:53.36#ibcon#read 5, iclass 35, count 0 2006.285.09:50:53.36#ibcon#about to read 6, iclass 35, count 0 2006.285.09:50:53.36#ibcon#read 6, iclass 35, count 0 2006.285.09:50:53.36#ibcon#end of sib2, iclass 35, count 0 2006.285.09:50:53.36#ibcon#*after write, iclass 35, count 0 2006.285.09:50:53.36#ibcon#*before return 0, iclass 35, count 0 2006.285.09:50:53.36#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:50:53.36#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.09:50:53.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:50:53.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:50:53.36$vck44/valo=3,564.99 2006.285.09:50:53.36#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.09:50:53.36#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.09:50:53.36#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:53.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:50:53.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:50:53.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:50:53.36#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:50:53.36#ibcon#first serial, iclass 40, count 0 2006.285.09:50:53.36#ibcon#enter sib2, iclass 40, count 0 2006.285.09:50:53.36#ibcon#flushed, iclass 40, count 0 2006.285.09:50:53.36#ibcon#about to write, iclass 40, count 0 2006.285.09:50:53.36#ibcon#wrote, iclass 40, count 0 2006.285.09:50:53.36#ibcon#about to read 3, iclass 40, count 0 2006.285.09:50:53.38#ibcon#read 3, iclass 40, count 0 2006.285.09:50:53.38#ibcon#about to read 4, iclass 40, count 0 2006.285.09:50:53.38#ibcon#read 4, iclass 40, count 0 2006.285.09:50:53.38#ibcon#about to read 5, iclass 40, count 0 2006.285.09:50:53.38#ibcon#read 5, iclass 40, count 0 2006.285.09:50:53.38#ibcon#about to read 6, iclass 40, count 0 2006.285.09:50:53.38#ibcon#read 6, iclass 40, count 0 2006.285.09:50:53.38#ibcon#end of sib2, iclass 40, count 0 2006.285.09:50:53.38#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:50:53.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:50:53.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:50:53.38#ibcon#*before write, iclass 40, count 0 2006.285.09:50:53.38#ibcon#enter sib2, iclass 40, count 0 2006.285.09:50:53.38#ibcon#flushed, iclass 40, count 0 2006.285.09:50:53.38#ibcon#about to write, iclass 40, count 0 2006.285.09:50:53.38#ibcon#wrote, iclass 40, count 0 2006.285.09:50:53.38#ibcon#about to read 3, iclass 40, count 0 2006.285.09:50:53.42#ibcon#read 3, iclass 40, count 0 2006.285.09:50:53.42#ibcon#about to read 4, iclass 40, count 0 2006.285.09:50:53.42#ibcon#read 4, iclass 40, count 0 2006.285.09:50:53.42#ibcon#about to read 5, iclass 40, count 0 2006.285.09:50:53.42#ibcon#read 5, iclass 40, count 0 2006.285.09:50:53.42#ibcon#about to read 6, iclass 40, count 0 2006.285.09:50:53.42#ibcon#read 6, iclass 40, count 0 2006.285.09:50:53.42#ibcon#end of sib2, iclass 40, count 0 2006.285.09:50:53.42#ibcon#*after write, iclass 40, count 0 2006.285.09:50:53.42#ibcon#*before return 0, iclass 40, count 0 2006.285.09:50:53.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:50:53.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:50:53.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:50:53.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:50:53.42$vck44/va=3,7 2006.285.09:50:53.42#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.09:50:53.42#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.09:50:53.42#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:53.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:50:53.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:50:53.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:50:53.48#ibcon#enter wrdev, iclass 4, count 2 2006.285.09:50:53.48#ibcon#first serial, iclass 4, count 2 2006.285.09:50:53.48#ibcon#enter sib2, iclass 4, count 2 2006.285.09:50:53.48#ibcon#flushed, iclass 4, count 2 2006.285.09:50:53.48#ibcon#about to write, iclass 4, count 2 2006.285.09:50:53.48#ibcon#wrote, iclass 4, count 2 2006.285.09:50:53.48#ibcon#about to read 3, iclass 4, count 2 2006.285.09:50:53.50#ibcon#read 3, iclass 4, count 2 2006.285.09:50:53.50#ibcon#about to read 4, iclass 4, count 2 2006.285.09:50:53.50#ibcon#read 4, iclass 4, count 2 2006.285.09:50:53.50#ibcon#about to read 5, iclass 4, count 2 2006.285.09:50:53.50#ibcon#read 5, iclass 4, count 2 2006.285.09:50:53.50#ibcon#about to read 6, iclass 4, count 2 2006.285.09:50:53.50#ibcon#read 6, iclass 4, count 2 2006.285.09:50:53.50#ibcon#end of sib2, iclass 4, count 2 2006.285.09:50:53.50#ibcon#*mode == 0, iclass 4, count 2 2006.285.09:50:53.50#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.09:50:53.50#ibcon#[25=AT03-07\r\n] 2006.285.09:50:53.50#ibcon#*before write, iclass 4, count 2 2006.285.09:50:53.50#ibcon#enter sib2, iclass 4, count 2 2006.285.09:50:53.50#ibcon#flushed, iclass 4, count 2 2006.285.09:50:53.50#ibcon#about to write, iclass 4, count 2 2006.285.09:50:53.50#ibcon#wrote, iclass 4, count 2 2006.285.09:50:53.50#ibcon#about to read 3, iclass 4, count 2 2006.285.09:50:53.53#ibcon#read 3, iclass 4, count 2 2006.285.09:50:53.53#ibcon#about to read 4, iclass 4, count 2 2006.285.09:50:53.53#ibcon#read 4, iclass 4, count 2 2006.285.09:50:53.53#ibcon#about to read 5, iclass 4, count 2 2006.285.09:50:53.53#ibcon#read 5, iclass 4, count 2 2006.285.09:50:53.53#ibcon#about to read 6, iclass 4, count 2 2006.285.09:50:53.53#ibcon#read 6, iclass 4, count 2 2006.285.09:50:53.53#ibcon#end of sib2, iclass 4, count 2 2006.285.09:50:53.53#ibcon#*after write, iclass 4, count 2 2006.285.09:50:53.53#ibcon#*before return 0, iclass 4, count 2 2006.285.09:50:53.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:50:53.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:50:53.53#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.09:50:53.53#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:53.53#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:50:53.65#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:50:53.65#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:50:53.65#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:50:53.65#ibcon#first serial, iclass 4, count 0 2006.285.09:50:53.65#ibcon#enter sib2, iclass 4, count 0 2006.285.09:50:53.65#ibcon#flushed, iclass 4, count 0 2006.285.09:50:53.65#ibcon#about to write, iclass 4, count 0 2006.285.09:50:53.65#ibcon#wrote, iclass 4, count 0 2006.285.09:50:53.65#ibcon#about to read 3, iclass 4, count 0 2006.285.09:50:53.67#ibcon#read 3, iclass 4, count 0 2006.285.09:50:53.67#ibcon#about to read 4, iclass 4, count 0 2006.285.09:50:53.67#ibcon#read 4, iclass 4, count 0 2006.285.09:50:53.67#ibcon#about to read 5, iclass 4, count 0 2006.285.09:50:53.67#ibcon#read 5, iclass 4, count 0 2006.285.09:50:53.67#ibcon#about to read 6, iclass 4, count 0 2006.285.09:50:53.67#ibcon#read 6, iclass 4, count 0 2006.285.09:50:53.67#ibcon#end of sib2, iclass 4, count 0 2006.285.09:50:53.67#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:50:53.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:50:53.67#ibcon#[25=USB\r\n] 2006.285.09:50:53.67#ibcon#*before write, iclass 4, count 0 2006.285.09:50:53.67#ibcon#enter sib2, iclass 4, count 0 2006.285.09:50:53.67#ibcon#flushed, iclass 4, count 0 2006.285.09:50:53.67#ibcon#about to write, iclass 4, count 0 2006.285.09:50:53.67#ibcon#wrote, iclass 4, count 0 2006.285.09:50:53.67#ibcon#about to read 3, iclass 4, count 0 2006.285.09:50:53.70#ibcon#read 3, iclass 4, count 0 2006.285.09:50:53.70#ibcon#about to read 4, iclass 4, count 0 2006.285.09:50:53.70#ibcon#read 4, iclass 4, count 0 2006.285.09:50:53.70#ibcon#about to read 5, iclass 4, count 0 2006.285.09:50:53.70#ibcon#read 5, iclass 4, count 0 2006.285.09:50:53.70#ibcon#about to read 6, iclass 4, count 0 2006.285.09:50:53.70#ibcon#read 6, iclass 4, count 0 2006.285.09:50:53.70#ibcon#end of sib2, iclass 4, count 0 2006.285.09:50:53.70#ibcon#*after write, iclass 4, count 0 2006.285.09:50:53.70#ibcon#*before return 0, iclass 4, count 0 2006.285.09:50:53.70#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:50:53.70#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:50:53.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:50:53.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:50:53.70$vck44/valo=4,624.99 2006.285.09:50:53.70#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.09:50:53.70#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.09:50:53.70#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:53.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:50:53.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:50:53.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:50:53.70#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:50:53.70#ibcon#first serial, iclass 6, count 0 2006.285.09:50:53.70#ibcon#enter sib2, iclass 6, count 0 2006.285.09:50:53.70#ibcon#flushed, iclass 6, count 0 2006.285.09:50:53.70#ibcon#about to write, iclass 6, count 0 2006.285.09:50:53.70#ibcon#wrote, iclass 6, count 0 2006.285.09:50:53.70#ibcon#about to read 3, iclass 6, count 0 2006.285.09:50:53.72#ibcon#read 3, iclass 6, count 0 2006.285.09:50:53.72#ibcon#about to read 4, iclass 6, count 0 2006.285.09:50:53.72#ibcon#read 4, iclass 6, count 0 2006.285.09:50:53.72#ibcon#about to read 5, iclass 6, count 0 2006.285.09:50:53.72#ibcon#read 5, iclass 6, count 0 2006.285.09:50:53.72#ibcon#about to read 6, iclass 6, count 0 2006.285.09:50:53.72#ibcon#read 6, iclass 6, count 0 2006.285.09:50:53.72#ibcon#end of sib2, iclass 6, count 0 2006.285.09:50:53.72#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:50:53.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:50:53.72#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:50:53.72#ibcon#*before write, iclass 6, count 0 2006.285.09:50:53.72#ibcon#enter sib2, iclass 6, count 0 2006.285.09:50:53.72#ibcon#flushed, iclass 6, count 0 2006.285.09:50:53.72#ibcon#about to write, iclass 6, count 0 2006.285.09:50:53.72#ibcon#wrote, iclass 6, count 0 2006.285.09:50:53.72#ibcon#about to read 3, iclass 6, count 0 2006.285.09:50:53.76#ibcon#read 3, iclass 6, count 0 2006.285.09:50:53.76#ibcon#about to read 4, iclass 6, count 0 2006.285.09:50:53.76#ibcon#read 4, iclass 6, count 0 2006.285.09:50:53.76#ibcon#about to read 5, iclass 6, count 0 2006.285.09:50:53.76#ibcon#read 5, iclass 6, count 0 2006.285.09:50:53.76#ibcon#about to read 6, iclass 6, count 0 2006.285.09:50:53.76#ibcon#read 6, iclass 6, count 0 2006.285.09:50:53.76#ibcon#end of sib2, iclass 6, count 0 2006.285.09:50:53.76#ibcon#*after write, iclass 6, count 0 2006.285.09:50:53.76#ibcon#*before return 0, iclass 6, count 0 2006.285.09:50:53.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:50:53.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:50:53.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:50:53.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:50:53.76$vck44/va=4,6 2006.285.09:50:53.76#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.09:50:53.76#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.09:50:53.76#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:53.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:50:53.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:50:53.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:50:53.82#ibcon#enter wrdev, iclass 10, count 2 2006.285.09:50:53.82#ibcon#first serial, iclass 10, count 2 2006.285.09:50:53.82#ibcon#enter sib2, iclass 10, count 2 2006.285.09:50:53.82#ibcon#flushed, iclass 10, count 2 2006.285.09:50:53.82#ibcon#about to write, iclass 10, count 2 2006.285.09:50:53.82#ibcon#wrote, iclass 10, count 2 2006.285.09:50:53.82#ibcon#about to read 3, iclass 10, count 2 2006.285.09:50:53.84#ibcon#read 3, iclass 10, count 2 2006.285.09:50:53.84#ibcon#about to read 4, iclass 10, count 2 2006.285.09:50:53.84#ibcon#read 4, iclass 10, count 2 2006.285.09:50:53.84#ibcon#about to read 5, iclass 10, count 2 2006.285.09:50:53.84#ibcon#read 5, iclass 10, count 2 2006.285.09:50:53.84#ibcon#about to read 6, iclass 10, count 2 2006.285.09:50:53.84#ibcon#read 6, iclass 10, count 2 2006.285.09:50:53.84#ibcon#end of sib2, iclass 10, count 2 2006.285.09:50:53.84#ibcon#*mode == 0, iclass 10, count 2 2006.285.09:50:53.84#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.09:50:53.84#ibcon#[25=AT04-06\r\n] 2006.285.09:50:53.84#ibcon#*before write, iclass 10, count 2 2006.285.09:50:53.84#ibcon#enter sib2, iclass 10, count 2 2006.285.09:50:53.84#ibcon#flushed, iclass 10, count 2 2006.285.09:50:53.84#ibcon#about to write, iclass 10, count 2 2006.285.09:50:53.84#ibcon#wrote, iclass 10, count 2 2006.285.09:50:53.84#ibcon#about to read 3, iclass 10, count 2 2006.285.09:50:53.87#ibcon#read 3, iclass 10, count 2 2006.285.09:50:53.87#ibcon#about to read 4, iclass 10, count 2 2006.285.09:50:53.87#ibcon#read 4, iclass 10, count 2 2006.285.09:50:53.87#ibcon#about to read 5, iclass 10, count 2 2006.285.09:50:53.87#ibcon#read 5, iclass 10, count 2 2006.285.09:50:53.87#ibcon#about to read 6, iclass 10, count 2 2006.285.09:50:53.87#ibcon#read 6, iclass 10, count 2 2006.285.09:50:53.87#ibcon#end of sib2, iclass 10, count 2 2006.285.09:50:53.87#ibcon#*after write, iclass 10, count 2 2006.285.09:50:53.87#ibcon#*before return 0, iclass 10, count 2 2006.285.09:50:53.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:50:53.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:50:53.87#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.09:50:53.87#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:53.87#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:50:53.99#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:50:53.99#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:50:53.99#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:50:53.99#ibcon#first serial, iclass 10, count 0 2006.285.09:50:53.99#ibcon#enter sib2, iclass 10, count 0 2006.285.09:50:53.99#ibcon#flushed, iclass 10, count 0 2006.285.09:50:53.99#ibcon#about to write, iclass 10, count 0 2006.285.09:50:53.99#ibcon#wrote, iclass 10, count 0 2006.285.09:50:53.99#ibcon#about to read 3, iclass 10, count 0 2006.285.09:50:54.01#ibcon#read 3, iclass 10, count 0 2006.285.09:50:54.01#ibcon#about to read 4, iclass 10, count 0 2006.285.09:50:54.01#ibcon#read 4, iclass 10, count 0 2006.285.09:50:54.01#ibcon#about to read 5, iclass 10, count 0 2006.285.09:50:54.01#ibcon#read 5, iclass 10, count 0 2006.285.09:50:54.01#ibcon#about to read 6, iclass 10, count 0 2006.285.09:50:54.01#ibcon#read 6, iclass 10, count 0 2006.285.09:50:54.01#ibcon#end of sib2, iclass 10, count 0 2006.285.09:50:54.01#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:50:54.01#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:50:54.01#ibcon#[25=USB\r\n] 2006.285.09:50:54.01#ibcon#*before write, iclass 10, count 0 2006.285.09:50:54.01#ibcon#enter sib2, iclass 10, count 0 2006.285.09:50:54.01#ibcon#flushed, iclass 10, count 0 2006.285.09:50:54.01#ibcon#about to write, iclass 10, count 0 2006.285.09:50:54.01#ibcon#wrote, iclass 10, count 0 2006.285.09:50:54.01#ibcon#about to read 3, iclass 10, count 0 2006.285.09:50:54.04#ibcon#read 3, iclass 10, count 0 2006.285.09:50:54.04#ibcon#about to read 4, iclass 10, count 0 2006.285.09:50:54.04#ibcon#read 4, iclass 10, count 0 2006.285.09:50:54.04#ibcon#about to read 5, iclass 10, count 0 2006.285.09:50:54.04#ibcon#read 5, iclass 10, count 0 2006.285.09:50:54.04#ibcon#about to read 6, iclass 10, count 0 2006.285.09:50:54.04#ibcon#read 6, iclass 10, count 0 2006.285.09:50:54.04#ibcon#end of sib2, iclass 10, count 0 2006.285.09:50:54.04#ibcon#*after write, iclass 10, count 0 2006.285.09:50:54.04#ibcon#*before return 0, iclass 10, count 0 2006.285.09:50:54.04#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:50:54.04#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:50:54.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:50:54.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:50:54.04$vck44/valo=5,734.99 2006.285.09:50:54.04#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.09:50:54.04#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.09:50:54.04#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:54.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:50:54.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:50:54.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:50:54.04#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:50:54.04#ibcon#first serial, iclass 12, count 0 2006.285.09:50:54.04#ibcon#enter sib2, iclass 12, count 0 2006.285.09:50:54.04#ibcon#flushed, iclass 12, count 0 2006.285.09:50:54.04#ibcon#about to write, iclass 12, count 0 2006.285.09:50:54.04#ibcon#wrote, iclass 12, count 0 2006.285.09:50:54.04#ibcon#about to read 3, iclass 12, count 0 2006.285.09:50:54.06#ibcon#read 3, iclass 12, count 0 2006.285.09:50:54.06#ibcon#about to read 4, iclass 12, count 0 2006.285.09:50:54.06#ibcon#read 4, iclass 12, count 0 2006.285.09:50:54.06#ibcon#about to read 5, iclass 12, count 0 2006.285.09:50:54.06#ibcon#read 5, iclass 12, count 0 2006.285.09:50:54.06#ibcon#about to read 6, iclass 12, count 0 2006.285.09:50:54.06#ibcon#read 6, iclass 12, count 0 2006.285.09:50:54.06#ibcon#end of sib2, iclass 12, count 0 2006.285.09:50:54.06#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:50:54.06#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:50:54.06#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:50:54.06#ibcon#*before write, iclass 12, count 0 2006.285.09:50:54.06#ibcon#enter sib2, iclass 12, count 0 2006.285.09:50:54.06#ibcon#flushed, iclass 12, count 0 2006.285.09:50:54.06#ibcon#about to write, iclass 12, count 0 2006.285.09:50:54.06#ibcon#wrote, iclass 12, count 0 2006.285.09:50:54.06#ibcon#about to read 3, iclass 12, count 0 2006.285.09:50:54.10#ibcon#read 3, iclass 12, count 0 2006.285.09:50:54.10#ibcon#about to read 4, iclass 12, count 0 2006.285.09:50:54.10#ibcon#read 4, iclass 12, count 0 2006.285.09:50:54.10#ibcon#about to read 5, iclass 12, count 0 2006.285.09:50:54.10#ibcon#read 5, iclass 12, count 0 2006.285.09:50:54.10#ibcon#about to read 6, iclass 12, count 0 2006.285.09:50:54.10#ibcon#read 6, iclass 12, count 0 2006.285.09:50:54.10#ibcon#end of sib2, iclass 12, count 0 2006.285.09:50:54.10#ibcon#*after write, iclass 12, count 0 2006.285.09:50:54.10#ibcon#*before return 0, iclass 12, count 0 2006.285.09:50:54.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:50:54.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:50:54.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:50:54.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:50:54.10$vck44/va=5,3 2006.285.09:50:54.10#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.09:50:54.10#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.09:50:54.10#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:54.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:50:54.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:50:54.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:50:54.16#ibcon#enter wrdev, iclass 14, count 2 2006.285.09:50:54.16#ibcon#first serial, iclass 14, count 2 2006.285.09:50:54.16#ibcon#enter sib2, iclass 14, count 2 2006.285.09:50:54.16#ibcon#flushed, iclass 14, count 2 2006.285.09:50:54.16#ibcon#about to write, iclass 14, count 2 2006.285.09:50:54.16#ibcon#wrote, iclass 14, count 2 2006.285.09:50:54.16#ibcon#about to read 3, iclass 14, count 2 2006.285.09:50:54.18#ibcon#read 3, iclass 14, count 2 2006.285.09:50:54.18#ibcon#about to read 4, iclass 14, count 2 2006.285.09:50:54.18#ibcon#read 4, iclass 14, count 2 2006.285.09:50:54.18#ibcon#about to read 5, iclass 14, count 2 2006.285.09:50:54.18#ibcon#read 5, iclass 14, count 2 2006.285.09:50:54.18#ibcon#about to read 6, iclass 14, count 2 2006.285.09:50:54.18#ibcon#read 6, iclass 14, count 2 2006.285.09:50:54.18#ibcon#end of sib2, iclass 14, count 2 2006.285.09:50:54.18#ibcon#*mode == 0, iclass 14, count 2 2006.285.09:50:54.18#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.09:50:54.18#ibcon#[25=AT05-03\r\n] 2006.285.09:50:54.18#ibcon#*before write, iclass 14, count 2 2006.285.09:50:54.18#ibcon#enter sib2, iclass 14, count 2 2006.285.09:50:54.18#ibcon#flushed, iclass 14, count 2 2006.285.09:50:54.18#ibcon#about to write, iclass 14, count 2 2006.285.09:50:54.18#ibcon#wrote, iclass 14, count 2 2006.285.09:50:54.18#ibcon#about to read 3, iclass 14, count 2 2006.285.09:50:54.21#ibcon#read 3, iclass 14, count 2 2006.285.09:50:54.21#ibcon#about to read 4, iclass 14, count 2 2006.285.09:50:54.21#ibcon#read 4, iclass 14, count 2 2006.285.09:50:54.21#ibcon#about to read 5, iclass 14, count 2 2006.285.09:50:54.21#ibcon#read 5, iclass 14, count 2 2006.285.09:50:54.21#ibcon#about to read 6, iclass 14, count 2 2006.285.09:50:54.21#ibcon#read 6, iclass 14, count 2 2006.285.09:50:54.21#ibcon#end of sib2, iclass 14, count 2 2006.285.09:50:54.21#ibcon#*after write, iclass 14, count 2 2006.285.09:50:54.21#ibcon#*before return 0, iclass 14, count 2 2006.285.09:50:54.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:50:54.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:50:54.21#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.09:50:54.21#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:54.21#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:50:54.33#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:50:54.33#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:50:54.33#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:50:54.33#ibcon#first serial, iclass 14, count 0 2006.285.09:50:54.33#ibcon#enter sib2, iclass 14, count 0 2006.285.09:50:54.33#ibcon#flushed, iclass 14, count 0 2006.285.09:50:54.33#ibcon#about to write, iclass 14, count 0 2006.285.09:50:54.33#ibcon#wrote, iclass 14, count 0 2006.285.09:50:54.33#ibcon#about to read 3, iclass 14, count 0 2006.285.09:50:54.35#ibcon#read 3, iclass 14, count 0 2006.285.09:50:54.35#ibcon#about to read 4, iclass 14, count 0 2006.285.09:50:54.35#ibcon#read 4, iclass 14, count 0 2006.285.09:50:54.35#ibcon#about to read 5, iclass 14, count 0 2006.285.09:50:54.35#ibcon#read 5, iclass 14, count 0 2006.285.09:50:54.35#ibcon#about to read 6, iclass 14, count 0 2006.285.09:50:54.35#ibcon#read 6, iclass 14, count 0 2006.285.09:50:54.35#ibcon#end of sib2, iclass 14, count 0 2006.285.09:50:54.35#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:50:54.35#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:50:54.35#ibcon#[25=USB\r\n] 2006.285.09:50:54.35#ibcon#*before write, iclass 14, count 0 2006.285.09:50:54.35#ibcon#enter sib2, iclass 14, count 0 2006.285.09:50:54.35#ibcon#flushed, iclass 14, count 0 2006.285.09:50:54.35#ibcon#about to write, iclass 14, count 0 2006.285.09:50:54.35#ibcon#wrote, iclass 14, count 0 2006.285.09:50:54.35#ibcon#about to read 3, iclass 14, count 0 2006.285.09:50:54.38#ibcon#read 3, iclass 14, count 0 2006.285.09:50:54.38#ibcon#about to read 4, iclass 14, count 0 2006.285.09:50:54.38#ibcon#read 4, iclass 14, count 0 2006.285.09:50:54.38#ibcon#about to read 5, iclass 14, count 0 2006.285.09:50:54.38#ibcon#read 5, iclass 14, count 0 2006.285.09:50:54.38#ibcon#about to read 6, iclass 14, count 0 2006.285.09:50:54.38#ibcon#read 6, iclass 14, count 0 2006.285.09:50:54.38#ibcon#end of sib2, iclass 14, count 0 2006.285.09:50:54.38#ibcon#*after write, iclass 14, count 0 2006.285.09:50:54.38#ibcon#*before return 0, iclass 14, count 0 2006.285.09:50:54.38#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:50:54.38#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:50:54.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:50:54.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:50:54.38$vck44/valo=6,814.99 2006.285.09:50:54.38#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.09:50:54.38#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.09:50:54.38#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:54.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:50:54.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:50:54.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:50:54.38#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:50:54.38#ibcon#first serial, iclass 16, count 0 2006.285.09:50:54.38#ibcon#enter sib2, iclass 16, count 0 2006.285.09:50:54.38#ibcon#flushed, iclass 16, count 0 2006.285.09:50:54.38#ibcon#about to write, iclass 16, count 0 2006.285.09:50:54.38#ibcon#wrote, iclass 16, count 0 2006.285.09:50:54.38#ibcon#about to read 3, iclass 16, count 0 2006.285.09:50:54.40#ibcon#read 3, iclass 16, count 0 2006.285.09:50:54.40#ibcon#about to read 4, iclass 16, count 0 2006.285.09:50:54.40#ibcon#read 4, iclass 16, count 0 2006.285.09:50:54.40#ibcon#about to read 5, iclass 16, count 0 2006.285.09:50:54.40#ibcon#read 5, iclass 16, count 0 2006.285.09:50:54.40#ibcon#about to read 6, iclass 16, count 0 2006.285.09:50:54.40#ibcon#read 6, iclass 16, count 0 2006.285.09:50:54.40#ibcon#end of sib2, iclass 16, count 0 2006.285.09:50:54.40#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:50:54.40#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:50:54.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:50:54.40#ibcon#*before write, iclass 16, count 0 2006.285.09:50:54.40#ibcon#enter sib2, iclass 16, count 0 2006.285.09:50:54.40#ibcon#flushed, iclass 16, count 0 2006.285.09:50:54.40#ibcon#about to write, iclass 16, count 0 2006.285.09:50:54.40#ibcon#wrote, iclass 16, count 0 2006.285.09:50:54.40#ibcon#about to read 3, iclass 16, count 0 2006.285.09:50:54.44#ibcon#read 3, iclass 16, count 0 2006.285.09:50:54.44#ibcon#about to read 4, iclass 16, count 0 2006.285.09:50:54.44#ibcon#read 4, iclass 16, count 0 2006.285.09:50:54.44#ibcon#about to read 5, iclass 16, count 0 2006.285.09:50:54.44#ibcon#read 5, iclass 16, count 0 2006.285.09:50:54.44#ibcon#about to read 6, iclass 16, count 0 2006.285.09:50:54.44#ibcon#read 6, iclass 16, count 0 2006.285.09:50:54.44#ibcon#end of sib2, iclass 16, count 0 2006.285.09:50:54.44#ibcon#*after write, iclass 16, count 0 2006.285.09:50:54.44#ibcon#*before return 0, iclass 16, count 0 2006.285.09:50:54.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:50:54.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:50:54.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:50:54.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:50:54.44$vck44/va=6,4 2006.285.09:50:54.44#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.09:50:54.44#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.09:50:54.44#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:54.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:50:54.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:50:54.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:50:54.50#ibcon#enter wrdev, iclass 18, count 2 2006.285.09:50:54.50#ibcon#first serial, iclass 18, count 2 2006.285.09:50:54.50#ibcon#enter sib2, iclass 18, count 2 2006.285.09:50:54.50#ibcon#flushed, iclass 18, count 2 2006.285.09:50:54.50#ibcon#about to write, iclass 18, count 2 2006.285.09:50:54.50#ibcon#wrote, iclass 18, count 2 2006.285.09:50:54.50#ibcon#about to read 3, iclass 18, count 2 2006.285.09:50:54.52#ibcon#read 3, iclass 18, count 2 2006.285.09:50:54.52#ibcon#about to read 4, iclass 18, count 2 2006.285.09:50:54.52#ibcon#read 4, iclass 18, count 2 2006.285.09:50:54.52#ibcon#about to read 5, iclass 18, count 2 2006.285.09:50:54.52#ibcon#read 5, iclass 18, count 2 2006.285.09:50:54.52#ibcon#about to read 6, iclass 18, count 2 2006.285.09:50:54.52#ibcon#read 6, iclass 18, count 2 2006.285.09:50:54.52#ibcon#end of sib2, iclass 18, count 2 2006.285.09:50:54.52#ibcon#*mode == 0, iclass 18, count 2 2006.285.09:50:54.52#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.09:50:54.52#ibcon#[25=AT06-04\r\n] 2006.285.09:50:54.52#ibcon#*before write, iclass 18, count 2 2006.285.09:50:54.52#ibcon#enter sib2, iclass 18, count 2 2006.285.09:50:54.52#ibcon#flushed, iclass 18, count 2 2006.285.09:50:54.52#ibcon#about to write, iclass 18, count 2 2006.285.09:50:54.52#ibcon#wrote, iclass 18, count 2 2006.285.09:50:54.52#ibcon#about to read 3, iclass 18, count 2 2006.285.09:50:54.55#ibcon#read 3, iclass 18, count 2 2006.285.09:50:54.55#ibcon#about to read 4, iclass 18, count 2 2006.285.09:50:54.55#ibcon#read 4, iclass 18, count 2 2006.285.09:50:54.55#ibcon#about to read 5, iclass 18, count 2 2006.285.09:50:54.55#ibcon#read 5, iclass 18, count 2 2006.285.09:50:54.55#ibcon#about to read 6, iclass 18, count 2 2006.285.09:50:54.55#ibcon#read 6, iclass 18, count 2 2006.285.09:50:54.55#ibcon#end of sib2, iclass 18, count 2 2006.285.09:50:54.55#ibcon#*after write, iclass 18, count 2 2006.285.09:50:54.55#ibcon#*before return 0, iclass 18, count 2 2006.285.09:50:54.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:50:54.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:50:54.55#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.09:50:54.55#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:54.55#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:50:54.67#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:50:54.67#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:50:54.67#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:50:54.67#ibcon#first serial, iclass 18, count 0 2006.285.09:50:54.67#ibcon#enter sib2, iclass 18, count 0 2006.285.09:50:54.67#ibcon#flushed, iclass 18, count 0 2006.285.09:50:54.67#ibcon#about to write, iclass 18, count 0 2006.285.09:50:54.67#ibcon#wrote, iclass 18, count 0 2006.285.09:50:54.67#ibcon#about to read 3, iclass 18, count 0 2006.285.09:50:54.69#ibcon#read 3, iclass 18, count 0 2006.285.09:50:54.69#ibcon#about to read 4, iclass 18, count 0 2006.285.09:50:54.69#ibcon#read 4, iclass 18, count 0 2006.285.09:50:54.69#ibcon#about to read 5, iclass 18, count 0 2006.285.09:50:54.69#ibcon#read 5, iclass 18, count 0 2006.285.09:50:54.69#ibcon#about to read 6, iclass 18, count 0 2006.285.09:50:54.69#ibcon#read 6, iclass 18, count 0 2006.285.09:50:54.69#ibcon#end of sib2, iclass 18, count 0 2006.285.09:50:54.69#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:50:54.69#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:50:54.69#ibcon#[25=USB\r\n] 2006.285.09:50:54.69#ibcon#*before write, iclass 18, count 0 2006.285.09:50:54.69#ibcon#enter sib2, iclass 18, count 0 2006.285.09:50:54.69#ibcon#flushed, iclass 18, count 0 2006.285.09:50:54.69#ibcon#about to write, iclass 18, count 0 2006.285.09:50:54.69#ibcon#wrote, iclass 18, count 0 2006.285.09:50:54.69#ibcon#about to read 3, iclass 18, count 0 2006.285.09:50:54.72#ibcon#read 3, iclass 18, count 0 2006.285.09:50:54.72#ibcon#about to read 4, iclass 18, count 0 2006.285.09:50:54.72#ibcon#read 4, iclass 18, count 0 2006.285.09:50:54.72#ibcon#about to read 5, iclass 18, count 0 2006.285.09:50:54.72#ibcon#read 5, iclass 18, count 0 2006.285.09:50:54.72#ibcon#about to read 6, iclass 18, count 0 2006.285.09:50:54.72#ibcon#read 6, iclass 18, count 0 2006.285.09:50:54.72#ibcon#end of sib2, iclass 18, count 0 2006.285.09:50:54.72#ibcon#*after write, iclass 18, count 0 2006.285.09:50:54.72#ibcon#*before return 0, iclass 18, count 0 2006.285.09:50:54.72#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:50:54.72#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:50:54.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:50:54.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:50:54.72$vck44/valo=7,864.99 2006.285.09:50:54.72#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.09:50:54.72#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.09:50:54.72#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:54.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:50:54.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:50:54.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:50:54.72#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:50:54.72#ibcon#first serial, iclass 20, count 0 2006.285.09:50:54.72#ibcon#enter sib2, iclass 20, count 0 2006.285.09:50:54.72#ibcon#flushed, iclass 20, count 0 2006.285.09:50:54.72#ibcon#about to write, iclass 20, count 0 2006.285.09:50:54.72#ibcon#wrote, iclass 20, count 0 2006.285.09:50:54.72#ibcon#about to read 3, iclass 20, count 0 2006.285.09:50:54.74#ibcon#read 3, iclass 20, count 0 2006.285.09:50:54.74#ibcon#about to read 4, iclass 20, count 0 2006.285.09:50:54.74#ibcon#read 4, iclass 20, count 0 2006.285.09:50:54.74#ibcon#about to read 5, iclass 20, count 0 2006.285.09:50:54.74#ibcon#read 5, iclass 20, count 0 2006.285.09:50:54.74#ibcon#about to read 6, iclass 20, count 0 2006.285.09:50:54.74#ibcon#read 6, iclass 20, count 0 2006.285.09:50:54.74#ibcon#end of sib2, iclass 20, count 0 2006.285.09:50:54.74#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:50:54.74#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:50:54.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:50:54.74#ibcon#*before write, iclass 20, count 0 2006.285.09:50:54.74#ibcon#enter sib2, iclass 20, count 0 2006.285.09:50:54.74#ibcon#flushed, iclass 20, count 0 2006.285.09:50:54.74#ibcon#about to write, iclass 20, count 0 2006.285.09:50:54.74#ibcon#wrote, iclass 20, count 0 2006.285.09:50:54.74#ibcon#about to read 3, iclass 20, count 0 2006.285.09:50:54.78#ibcon#read 3, iclass 20, count 0 2006.285.09:50:54.78#ibcon#about to read 4, iclass 20, count 0 2006.285.09:50:54.78#ibcon#read 4, iclass 20, count 0 2006.285.09:50:54.78#ibcon#about to read 5, iclass 20, count 0 2006.285.09:50:54.78#ibcon#read 5, iclass 20, count 0 2006.285.09:50:54.78#ibcon#about to read 6, iclass 20, count 0 2006.285.09:50:54.78#ibcon#read 6, iclass 20, count 0 2006.285.09:50:54.78#ibcon#end of sib2, iclass 20, count 0 2006.285.09:50:54.78#ibcon#*after write, iclass 20, count 0 2006.285.09:50:54.78#ibcon#*before return 0, iclass 20, count 0 2006.285.09:50:54.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:50:54.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:50:54.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:50:54.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:50:54.78$vck44/va=7,4 2006.285.09:50:54.78#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.09:50:54.78#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.09:50:54.78#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:54.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:50:54.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:50:54.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:50:54.84#ibcon#enter wrdev, iclass 22, count 2 2006.285.09:50:54.84#ibcon#first serial, iclass 22, count 2 2006.285.09:50:54.84#ibcon#enter sib2, iclass 22, count 2 2006.285.09:50:54.84#ibcon#flushed, iclass 22, count 2 2006.285.09:50:54.84#ibcon#about to write, iclass 22, count 2 2006.285.09:50:54.84#ibcon#wrote, iclass 22, count 2 2006.285.09:50:54.84#ibcon#about to read 3, iclass 22, count 2 2006.285.09:50:54.86#ibcon#read 3, iclass 22, count 2 2006.285.09:50:54.86#ibcon#about to read 4, iclass 22, count 2 2006.285.09:50:54.86#ibcon#read 4, iclass 22, count 2 2006.285.09:50:54.86#ibcon#about to read 5, iclass 22, count 2 2006.285.09:50:54.86#ibcon#read 5, iclass 22, count 2 2006.285.09:50:54.86#ibcon#about to read 6, iclass 22, count 2 2006.285.09:50:54.86#ibcon#read 6, iclass 22, count 2 2006.285.09:50:54.86#ibcon#end of sib2, iclass 22, count 2 2006.285.09:50:54.86#ibcon#*mode == 0, iclass 22, count 2 2006.285.09:50:54.86#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.09:50:54.86#ibcon#[25=AT07-04\r\n] 2006.285.09:50:54.86#ibcon#*before write, iclass 22, count 2 2006.285.09:50:54.86#ibcon#enter sib2, iclass 22, count 2 2006.285.09:50:54.86#ibcon#flushed, iclass 22, count 2 2006.285.09:50:54.86#ibcon#about to write, iclass 22, count 2 2006.285.09:50:54.86#ibcon#wrote, iclass 22, count 2 2006.285.09:50:54.86#ibcon#about to read 3, iclass 22, count 2 2006.285.09:50:54.89#ibcon#read 3, iclass 22, count 2 2006.285.09:50:54.89#ibcon#about to read 4, iclass 22, count 2 2006.285.09:50:54.89#ibcon#read 4, iclass 22, count 2 2006.285.09:50:54.89#ibcon#about to read 5, iclass 22, count 2 2006.285.09:50:54.89#ibcon#read 5, iclass 22, count 2 2006.285.09:50:54.89#ibcon#about to read 6, iclass 22, count 2 2006.285.09:50:54.89#ibcon#read 6, iclass 22, count 2 2006.285.09:50:54.89#ibcon#end of sib2, iclass 22, count 2 2006.285.09:50:54.89#ibcon#*after write, iclass 22, count 2 2006.285.09:50:54.89#ibcon#*before return 0, iclass 22, count 2 2006.285.09:50:54.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:50:54.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:50:54.89#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.09:50:54.89#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:54.89#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:50:55.01#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:50:55.01#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:50:55.01#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:50:55.01#ibcon#first serial, iclass 22, count 0 2006.285.09:50:55.01#ibcon#enter sib2, iclass 22, count 0 2006.285.09:50:55.01#ibcon#flushed, iclass 22, count 0 2006.285.09:50:55.01#ibcon#about to write, iclass 22, count 0 2006.285.09:50:55.01#ibcon#wrote, iclass 22, count 0 2006.285.09:50:55.01#ibcon#about to read 3, iclass 22, count 0 2006.285.09:50:55.03#ibcon#read 3, iclass 22, count 0 2006.285.09:50:55.03#ibcon#about to read 4, iclass 22, count 0 2006.285.09:50:55.03#ibcon#read 4, iclass 22, count 0 2006.285.09:50:55.03#ibcon#about to read 5, iclass 22, count 0 2006.285.09:50:55.03#ibcon#read 5, iclass 22, count 0 2006.285.09:50:55.03#ibcon#about to read 6, iclass 22, count 0 2006.285.09:50:55.03#ibcon#read 6, iclass 22, count 0 2006.285.09:50:55.03#ibcon#end of sib2, iclass 22, count 0 2006.285.09:50:55.03#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:50:55.03#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:50:55.03#ibcon#[25=USB\r\n] 2006.285.09:50:55.03#ibcon#*before write, iclass 22, count 0 2006.285.09:50:55.03#ibcon#enter sib2, iclass 22, count 0 2006.285.09:50:55.03#ibcon#flushed, iclass 22, count 0 2006.285.09:50:55.03#ibcon#about to write, iclass 22, count 0 2006.285.09:50:55.03#ibcon#wrote, iclass 22, count 0 2006.285.09:50:55.03#ibcon#about to read 3, iclass 22, count 0 2006.285.09:50:55.06#ibcon#read 3, iclass 22, count 0 2006.285.09:50:55.06#ibcon#about to read 4, iclass 22, count 0 2006.285.09:50:55.06#ibcon#read 4, iclass 22, count 0 2006.285.09:50:55.06#ibcon#about to read 5, iclass 22, count 0 2006.285.09:50:55.06#ibcon#read 5, iclass 22, count 0 2006.285.09:50:55.06#ibcon#about to read 6, iclass 22, count 0 2006.285.09:50:55.06#ibcon#read 6, iclass 22, count 0 2006.285.09:50:55.06#ibcon#end of sib2, iclass 22, count 0 2006.285.09:50:55.06#ibcon#*after write, iclass 22, count 0 2006.285.09:50:55.06#ibcon#*before return 0, iclass 22, count 0 2006.285.09:50:55.06#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:50:55.06#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:50:55.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:50:55.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:50:55.06$vck44/valo=8,884.99 2006.285.09:50:55.06#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.09:50:55.06#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.09:50:55.06#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:55.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:50:55.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:50:55.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:50:55.06#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:50:55.06#ibcon#first serial, iclass 24, count 0 2006.285.09:50:55.06#ibcon#enter sib2, iclass 24, count 0 2006.285.09:50:55.06#ibcon#flushed, iclass 24, count 0 2006.285.09:50:55.06#ibcon#about to write, iclass 24, count 0 2006.285.09:50:55.06#ibcon#wrote, iclass 24, count 0 2006.285.09:50:55.06#ibcon#about to read 3, iclass 24, count 0 2006.285.09:50:55.08#ibcon#read 3, iclass 24, count 0 2006.285.09:50:55.08#ibcon#about to read 4, iclass 24, count 0 2006.285.09:50:55.08#ibcon#read 4, iclass 24, count 0 2006.285.09:50:55.08#ibcon#about to read 5, iclass 24, count 0 2006.285.09:50:55.08#ibcon#read 5, iclass 24, count 0 2006.285.09:50:55.08#ibcon#about to read 6, iclass 24, count 0 2006.285.09:50:55.08#ibcon#read 6, iclass 24, count 0 2006.285.09:50:55.08#ibcon#end of sib2, iclass 24, count 0 2006.285.09:50:55.08#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:50:55.08#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:50:55.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:50:55.08#ibcon#*before write, iclass 24, count 0 2006.285.09:50:55.08#ibcon#enter sib2, iclass 24, count 0 2006.285.09:50:55.08#ibcon#flushed, iclass 24, count 0 2006.285.09:50:55.08#ibcon#about to write, iclass 24, count 0 2006.285.09:50:55.08#ibcon#wrote, iclass 24, count 0 2006.285.09:50:55.08#ibcon#about to read 3, iclass 24, count 0 2006.285.09:50:55.12#ibcon#read 3, iclass 24, count 0 2006.285.09:50:55.12#ibcon#about to read 4, iclass 24, count 0 2006.285.09:50:55.12#ibcon#read 4, iclass 24, count 0 2006.285.09:50:55.12#ibcon#about to read 5, iclass 24, count 0 2006.285.09:50:55.12#ibcon#read 5, iclass 24, count 0 2006.285.09:50:55.12#ibcon#about to read 6, iclass 24, count 0 2006.285.09:50:55.12#ibcon#read 6, iclass 24, count 0 2006.285.09:50:55.12#ibcon#end of sib2, iclass 24, count 0 2006.285.09:50:55.12#ibcon#*after write, iclass 24, count 0 2006.285.09:50:55.12#ibcon#*before return 0, iclass 24, count 0 2006.285.09:50:55.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:50:55.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:50:55.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:50:55.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:50:55.12$vck44/va=8,3 2006.285.09:50:55.12#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.09:50:55.12#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.09:50:55.12#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:55.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:50:55.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:50:55.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:50:55.18#ibcon#enter wrdev, iclass 26, count 2 2006.285.09:50:55.18#ibcon#first serial, iclass 26, count 2 2006.285.09:50:55.18#ibcon#enter sib2, iclass 26, count 2 2006.285.09:50:55.18#ibcon#flushed, iclass 26, count 2 2006.285.09:50:55.18#ibcon#about to write, iclass 26, count 2 2006.285.09:50:55.18#ibcon#wrote, iclass 26, count 2 2006.285.09:50:55.18#ibcon#about to read 3, iclass 26, count 2 2006.285.09:50:55.20#ibcon#read 3, iclass 26, count 2 2006.285.09:50:55.20#ibcon#about to read 4, iclass 26, count 2 2006.285.09:50:55.20#ibcon#read 4, iclass 26, count 2 2006.285.09:50:55.20#ibcon#about to read 5, iclass 26, count 2 2006.285.09:50:55.20#ibcon#read 5, iclass 26, count 2 2006.285.09:50:55.20#ibcon#about to read 6, iclass 26, count 2 2006.285.09:50:55.20#ibcon#read 6, iclass 26, count 2 2006.285.09:50:55.20#ibcon#end of sib2, iclass 26, count 2 2006.285.09:50:55.20#ibcon#*mode == 0, iclass 26, count 2 2006.285.09:50:55.20#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.09:50:55.20#ibcon#[25=AT08-03\r\n] 2006.285.09:50:55.20#ibcon#*before write, iclass 26, count 2 2006.285.09:50:55.20#ibcon#enter sib2, iclass 26, count 2 2006.285.09:50:55.20#ibcon#flushed, iclass 26, count 2 2006.285.09:50:55.20#ibcon#about to write, iclass 26, count 2 2006.285.09:50:55.20#ibcon#wrote, iclass 26, count 2 2006.285.09:50:55.20#ibcon#about to read 3, iclass 26, count 2 2006.285.09:50:55.23#ibcon#read 3, iclass 26, count 2 2006.285.09:50:55.23#ibcon#about to read 4, iclass 26, count 2 2006.285.09:50:55.23#ibcon#read 4, iclass 26, count 2 2006.285.09:50:55.23#ibcon#about to read 5, iclass 26, count 2 2006.285.09:50:55.23#ibcon#read 5, iclass 26, count 2 2006.285.09:50:55.23#ibcon#about to read 6, iclass 26, count 2 2006.285.09:50:55.23#ibcon#read 6, iclass 26, count 2 2006.285.09:50:55.23#ibcon#end of sib2, iclass 26, count 2 2006.285.09:50:55.23#ibcon#*after write, iclass 26, count 2 2006.285.09:50:55.23#ibcon#*before return 0, iclass 26, count 2 2006.285.09:50:55.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:50:55.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.09:50:55.23#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.09:50:55.23#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:55.23#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:50:55.35#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:50:55.35#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:50:55.35#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:50:55.35#ibcon#first serial, iclass 26, count 0 2006.285.09:50:55.35#ibcon#enter sib2, iclass 26, count 0 2006.285.09:50:55.35#ibcon#flushed, iclass 26, count 0 2006.285.09:50:55.35#ibcon#about to write, iclass 26, count 0 2006.285.09:50:55.35#ibcon#wrote, iclass 26, count 0 2006.285.09:50:55.35#ibcon#about to read 3, iclass 26, count 0 2006.285.09:50:55.37#ibcon#read 3, iclass 26, count 0 2006.285.09:50:55.37#ibcon#about to read 4, iclass 26, count 0 2006.285.09:50:55.37#ibcon#read 4, iclass 26, count 0 2006.285.09:50:55.37#ibcon#about to read 5, iclass 26, count 0 2006.285.09:50:55.37#ibcon#read 5, iclass 26, count 0 2006.285.09:50:55.37#ibcon#about to read 6, iclass 26, count 0 2006.285.09:50:55.37#ibcon#read 6, iclass 26, count 0 2006.285.09:50:55.37#ibcon#end of sib2, iclass 26, count 0 2006.285.09:50:55.37#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:50:55.37#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:50:55.37#ibcon#[25=USB\r\n] 2006.285.09:50:55.37#ibcon#*before write, iclass 26, count 0 2006.285.09:50:55.37#ibcon#enter sib2, iclass 26, count 0 2006.285.09:50:55.37#ibcon#flushed, iclass 26, count 0 2006.285.09:50:55.37#ibcon#about to write, iclass 26, count 0 2006.285.09:50:55.37#ibcon#wrote, iclass 26, count 0 2006.285.09:50:55.37#ibcon#about to read 3, iclass 26, count 0 2006.285.09:50:55.40#ibcon#read 3, iclass 26, count 0 2006.285.09:50:55.40#ibcon#about to read 4, iclass 26, count 0 2006.285.09:50:55.40#ibcon#read 4, iclass 26, count 0 2006.285.09:50:55.40#ibcon#about to read 5, iclass 26, count 0 2006.285.09:50:55.40#ibcon#read 5, iclass 26, count 0 2006.285.09:50:55.40#ibcon#about to read 6, iclass 26, count 0 2006.285.09:50:55.40#ibcon#read 6, iclass 26, count 0 2006.285.09:50:55.40#ibcon#end of sib2, iclass 26, count 0 2006.285.09:50:55.40#ibcon#*after write, iclass 26, count 0 2006.285.09:50:55.40#ibcon#*before return 0, iclass 26, count 0 2006.285.09:50:55.40#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:50:55.40#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.09:50:55.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:50:55.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:50:55.40$vck44/vblo=1,629.99 2006.285.09:50:55.40#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.09:50:55.40#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.09:50:55.40#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:55.40#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:50:55.40#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:50:55.40#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:50:55.40#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:50:55.40#ibcon#first serial, iclass 28, count 0 2006.285.09:50:55.40#ibcon#enter sib2, iclass 28, count 0 2006.285.09:50:55.40#ibcon#flushed, iclass 28, count 0 2006.285.09:50:55.40#ibcon#about to write, iclass 28, count 0 2006.285.09:50:55.40#ibcon#wrote, iclass 28, count 0 2006.285.09:50:55.40#ibcon#about to read 3, iclass 28, count 0 2006.285.09:50:55.42#ibcon#read 3, iclass 28, count 0 2006.285.09:50:55.42#ibcon#about to read 4, iclass 28, count 0 2006.285.09:50:55.42#ibcon#read 4, iclass 28, count 0 2006.285.09:50:55.42#ibcon#about to read 5, iclass 28, count 0 2006.285.09:50:55.42#ibcon#read 5, iclass 28, count 0 2006.285.09:50:55.42#ibcon#about to read 6, iclass 28, count 0 2006.285.09:50:55.42#ibcon#read 6, iclass 28, count 0 2006.285.09:50:55.42#ibcon#end of sib2, iclass 28, count 0 2006.285.09:50:55.42#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:50:55.42#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:50:55.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:50:55.42#ibcon#*before write, iclass 28, count 0 2006.285.09:50:55.42#ibcon#enter sib2, iclass 28, count 0 2006.285.09:50:55.42#ibcon#flushed, iclass 28, count 0 2006.285.09:50:55.42#ibcon#about to write, iclass 28, count 0 2006.285.09:50:55.42#ibcon#wrote, iclass 28, count 0 2006.285.09:50:55.42#ibcon#about to read 3, iclass 28, count 0 2006.285.09:50:55.46#ibcon#read 3, iclass 28, count 0 2006.285.09:50:55.46#ibcon#about to read 4, iclass 28, count 0 2006.285.09:50:55.46#ibcon#read 4, iclass 28, count 0 2006.285.09:50:55.46#ibcon#about to read 5, iclass 28, count 0 2006.285.09:50:55.46#ibcon#read 5, iclass 28, count 0 2006.285.09:50:55.46#ibcon#about to read 6, iclass 28, count 0 2006.285.09:50:55.46#ibcon#read 6, iclass 28, count 0 2006.285.09:50:55.46#ibcon#end of sib2, iclass 28, count 0 2006.285.09:50:55.46#ibcon#*after write, iclass 28, count 0 2006.285.09:50:55.46#ibcon#*before return 0, iclass 28, count 0 2006.285.09:50:55.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:50:55.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.09:50:55.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:50:55.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:50:55.46$vck44/vb=1,4 2006.285.09:50:55.46#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.09:50:55.46#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.09:50:55.46#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:55.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:50:55.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:50:55.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:50:55.46#ibcon#enter wrdev, iclass 30, count 2 2006.285.09:50:55.46#ibcon#first serial, iclass 30, count 2 2006.285.09:50:55.46#ibcon#enter sib2, iclass 30, count 2 2006.285.09:50:55.46#ibcon#flushed, iclass 30, count 2 2006.285.09:50:55.46#ibcon#about to write, iclass 30, count 2 2006.285.09:50:55.46#ibcon#wrote, iclass 30, count 2 2006.285.09:50:55.46#ibcon#about to read 3, iclass 30, count 2 2006.285.09:50:55.48#ibcon#read 3, iclass 30, count 2 2006.285.09:50:55.48#ibcon#about to read 4, iclass 30, count 2 2006.285.09:50:55.48#ibcon#read 4, iclass 30, count 2 2006.285.09:50:55.48#ibcon#about to read 5, iclass 30, count 2 2006.285.09:50:55.48#ibcon#read 5, iclass 30, count 2 2006.285.09:50:55.48#ibcon#about to read 6, iclass 30, count 2 2006.285.09:50:55.48#ibcon#read 6, iclass 30, count 2 2006.285.09:50:55.48#ibcon#end of sib2, iclass 30, count 2 2006.285.09:50:55.48#ibcon#*mode == 0, iclass 30, count 2 2006.285.09:50:55.48#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.09:50:55.48#ibcon#[27=AT01-04\r\n] 2006.285.09:50:55.48#ibcon#*before write, iclass 30, count 2 2006.285.09:50:55.48#ibcon#enter sib2, iclass 30, count 2 2006.285.09:50:55.48#ibcon#flushed, iclass 30, count 2 2006.285.09:50:55.48#ibcon#about to write, iclass 30, count 2 2006.285.09:50:55.48#ibcon#wrote, iclass 30, count 2 2006.285.09:50:55.48#ibcon#about to read 3, iclass 30, count 2 2006.285.09:50:55.51#ibcon#read 3, iclass 30, count 2 2006.285.09:50:55.51#ibcon#about to read 4, iclass 30, count 2 2006.285.09:50:55.51#ibcon#read 4, iclass 30, count 2 2006.285.09:50:55.51#ibcon#about to read 5, iclass 30, count 2 2006.285.09:50:55.51#ibcon#read 5, iclass 30, count 2 2006.285.09:50:55.51#ibcon#about to read 6, iclass 30, count 2 2006.285.09:50:55.51#ibcon#read 6, iclass 30, count 2 2006.285.09:50:55.51#ibcon#end of sib2, iclass 30, count 2 2006.285.09:50:55.51#ibcon#*after write, iclass 30, count 2 2006.285.09:50:55.51#ibcon#*before return 0, iclass 30, count 2 2006.285.09:50:55.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:50:55.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.09:50:55.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.09:50:55.51#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:55.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:50:55.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:50:55.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:50:55.63#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:50:55.63#ibcon#first serial, iclass 30, count 0 2006.285.09:50:55.63#ibcon#enter sib2, iclass 30, count 0 2006.285.09:50:55.63#ibcon#flushed, iclass 30, count 0 2006.285.09:50:55.63#ibcon#about to write, iclass 30, count 0 2006.285.09:50:55.63#ibcon#wrote, iclass 30, count 0 2006.285.09:50:55.63#ibcon#about to read 3, iclass 30, count 0 2006.285.09:50:55.65#ibcon#read 3, iclass 30, count 0 2006.285.09:50:55.65#ibcon#about to read 4, iclass 30, count 0 2006.285.09:50:55.65#ibcon#read 4, iclass 30, count 0 2006.285.09:50:55.65#ibcon#about to read 5, iclass 30, count 0 2006.285.09:50:55.65#ibcon#read 5, iclass 30, count 0 2006.285.09:50:55.65#ibcon#about to read 6, iclass 30, count 0 2006.285.09:50:55.65#ibcon#read 6, iclass 30, count 0 2006.285.09:50:55.65#ibcon#end of sib2, iclass 30, count 0 2006.285.09:50:55.65#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:50:55.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:50:55.65#ibcon#[27=USB\r\n] 2006.285.09:50:55.65#ibcon#*before write, iclass 30, count 0 2006.285.09:50:55.65#ibcon#enter sib2, iclass 30, count 0 2006.285.09:50:55.65#ibcon#flushed, iclass 30, count 0 2006.285.09:50:55.65#ibcon#about to write, iclass 30, count 0 2006.285.09:50:55.65#ibcon#wrote, iclass 30, count 0 2006.285.09:50:55.65#ibcon#about to read 3, iclass 30, count 0 2006.285.09:50:55.68#ibcon#read 3, iclass 30, count 0 2006.285.09:50:55.68#ibcon#about to read 4, iclass 30, count 0 2006.285.09:50:55.68#ibcon#read 4, iclass 30, count 0 2006.285.09:50:55.68#ibcon#about to read 5, iclass 30, count 0 2006.285.09:50:55.68#ibcon#read 5, iclass 30, count 0 2006.285.09:50:55.68#ibcon#about to read 6, iclass 30, count 0 2006.285.09:50:55.68#ibcon#read 6, iclass 30, count 0 2006.285.09:50:55.68#ibcon#end of sib2, iclass 30, count 0 2006.285.09:50:55.68#ibcon#*after write, iclass 30, count 0 2006.285.09:50:55.68#ibcon#*before return 0, iclass 30, count 0 2006.285.09:50:55.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:50:55.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.09:50:55.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:50:55.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:50:55.68$vck44/vblo=2,634.99 2006.285.09:50:55.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.09:50:55.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.09:50:55.68#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:55.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:50:55.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:50:55.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:50:55.68#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:50:55.68#ibcon#first serial, iclass 32, count 0 2006.285.09:50:55.68#ibcon#enter sib2, iclass 32, count 0 2006.285.09:50:55.68#ibcon#flushed, iclass 32, count 0 2006.285.09:50:55.68#ibcon#about to write, iclass 32, count 0 2006.285.09:50:55.68#ibcon#wrote, iclass 32, count 0 2006.285.09:50:55.68#ibcon#about to read 3, iclass 32, count 0 2006.285.09:50:55.70#ibcon#read 3, iclass 32, count 0 2006.285.09:50:55.70#ibcon#about to read 4, iclass 32, count 0 2006.285.09:50:55.70#ibcon#read 4, iclass 32, count 0 2006.285.09:50:55.70#ibcon#about to read 5, iclass 32, count 0 2006.285.09:50:55.70#ibcon#read 5, iclass 32, count 0 2006.285.09:50:55.70#ibcon#about to read 6, iclass 32, count 0 2006.285.09:50:55.70#ibcon#read 6, iclass 32, count 0 2006.285.09:50:55.70#ibcon#end of sib2, iclass 32, count 0 2006.285.09:50:55.70#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:50:55.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:50:55.70#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:50:55.70#ibcon#*before write, iclass 32, count 0 2006.285.09:50:55.70#ibcon#enter sib2, iclass 32, count 0 2006.285.09:50:55.70#ibcon#flushed, iclass 32, count 0 2006.285.09:50:55.70#ibcon#about to write, iclass 32, count 0 2006.285.09:50:55.70#ibcon#wrote, iclass 32, count 0 2006.285.09:50:55.70#ibcon#about to read 3, iclass 32, count 0 2006.285.09:50:55.74#ibcon#read 3, iclass 32, count 0 2006.285.09:50:55.74#ibcon#about to read 4, iclass 32, count 0 2006.285.09:50:55.74#ibcon#read 4, iclass 32, count 0 2006.285.09:50:55.74#ibcon#about to read 5, iclass 32, count 0 2006.285.09:50:55.74#ibcon#read 5, iclass 32, count 0 2006.285.09:50:55.74#ibcon#about to read 6, iclass 32, count 0 2006.285.09:50:55.74#ibcon#read 6, iclass 32, count 0 2006.285.09:50:55.74#ibcon#end of sib2, iclass 32, count 0 2006.285.09:50:55.74#ibcon#*after write, iclass 32, count 0 2006.285.09:50:55.74#ibcon#*before return 0, iclass 32, count 0 2006.285.09:50:55.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:50:55.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.09:50:55.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:50:55.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:50:55.74$vck44/vb=2,5 2006.285.09:50:55.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.09:50:55.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.09:50:55.74#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:55.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:50:55.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:50:55.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:50:55.80#ibcon#enter wrdev, iclass 34, count 2 2006.285.09:50:55.80#ibcon#first serial, iclass 34, count 2 2006.285.09:50:55.80#ibcon#enter sib2, iclass 34, count 2 2006.285.09:50:55.80#ibcon#flushed, iclass 34, count 2 2006.285.09:50:55.80#ibcon#about to write, iclass 34, count 2 2006.285.09:50:55.80#ibcon#wrote, iclass 34, count 2 2006.285.09:50:55.80#ibcon#about to read 3, iclass 34, count 2 2006.285.09:50:55.82#ibcon#read 3, iclass 34, count 2 2006.285.09:50:55.82#ibcon#about to read 4, iclass 34, count 2 2006.285.09:50:55.82#ibcon#read 4, iclass 34, count 2 2006.285.09:50:55.82#ibcon#about to read 5, iclass 34, count 2 2006.285.09:50:55.82#ibcon#read 5, iclass 34, count 2 2006.285.09:50:55.82#ibcon#about to read 6, iclass 34, count 2 2006.285.09:50:55.82#ibcon#read 6, iclass 34, count 2 2006.285.09:50:55.82#ibcon#end of sib2, iclass 34, count 2 2006.285.09:50:55.82#ibcon#*mode == 0, iclass 34, count 2 2006.285.09:50:55.82#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.09:50:55.82#ibcon#[27=AT02-05\r\n] 2006.285.09:50:55.82#ibcon#*before write, iclass 34, count 2 2006.285.09:50:55.82#ibcon#enter sib2, iclass 34, count 2 2006.285.09:50:55.82#ibcon#flushed, iclass 34, count 2 2006.285.09:50:55.82#ibcon#about to write, iclass 34, count 2 2006.285.09:50:55.82#ibcon#wrote, iclass 34, count 2 2006.285.09:50:55.82#ibcon#about to read 3, iclass 34, count 2 2006.285.09:50:55.85#ibcon#read 3, iclass 34, count 2 2006.285.09:50:55.85#ibcon#about to read 4, iclass 34, count 2 2006.285.09:50:55.85#ibcon#read 4, iclass 34, count 2 2006.285.09:50:55.85#ibcon#about to read 5, iclass 34, count 2 2006.285.09:50:55.85#ibcon#read 5, iclass 34, count 2 2006.285.09:50:55.85#ibcon#about to read 6, iclass 34, count 2 2006.285.09:50:55.85#ibcon#read 6, iclass 34, count 2 2006.285.09:50:55.85#ibcon#end of sib2, iclass 34, count 2 2006.285.09:50:55.85#ibcon#*after write, iclass 34, count 2 2006.285.09:50:55.85#ibcon#*before return 0, iclass 34, count 2 2006.285.09:50:55.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:50:55.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.09:50:55.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.09:50:55.85#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:55.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:50:55.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:50:55.97#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:50:55.97#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:50:55.97#ibcon#first serial, iclass 34, count 0 2006.285.09:50:55.97#ibcon#enter sib2, iclass 34, count 0 2006.285.09:50:55.97#ibcon#flushed, iclass 34, count 0 2006.285.09:50:55.97#ibcon#about to write, iclass 34, count 0 2006.285.09:50:55.97#ibcon#wrote, iclass 34, count 0 2006.285.09:50:55.97#ibcon#about to read 3, iclass 34, count 0 2006.285.09:50:55.99#ibcon#read 3, iclass 34, count 0 2006.285.09:50:55.99#ibcon#about to read 4, iclass 34, count 0 2006.285.09:50:55.99#ibcon#read 4, iclass 34, count 0 2006.285.09:50:55.99#ibcon#about to read 5, iclass 34, count 0 2006.285.09:50:55.99#ibcon#read 5, iclass 34, count 0 2006.285.09:50:55.99#ibcon#about to read 6, iclass 34, count 0 2006.285.09:50:55.99#ibcon#read 6, iclass 34, count 0 2006.285.09:50:55.99#ibcon#end of sib2, iclass 34, count 0 2006.285.09:50:55.99#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:50:55.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:50:55.99#ibcon#[27=USB\r\n] 2006.285.09:50:55.99#ibcon#*before write, iclass 34, count 0 2006.285.09:50:55.99#ibcon#enter sib2, iclass 34, count 0 2006.285.09:50:55.99#ibcon#flushed, iclass 34, count 0 2006.285.09:50:55.99#ibcon#about to write, iclass 34, count 0 2006.285.09:50:55.99#ibcon#wrote, iclass 34, count 0 2006.285.09:50:55.99#ibcon#about to read 3, iclass 34, count 0 2006.285.09:50:56.02#ibcon#read 3, iclass 34, count 0 2006.285.09:50:56.02#ibcon#about to read 4, iclass 34, count 0 2006.285.09:50:56.02#ibcon#read 4, iclass 34, count 0 2006.285.09:50:56.02#ibcon#about to read 5, iclass 34, count 0 2006.285.09:50:56.02#ibcon#read 5, iclass 34, count 0 2006.285.09:50:56.02#ibcon#about to read 6, iclass 34, count 0 2006.285.09:50:56.02#ibcon#read 6, iclass 34, count 0 2006.285.09:50:56.02#ibcon#end of sib2, iclass 34, count 0 2006.285.09:50:56.02#ibcon#*after write, iclass 34, count 0 2006.285.09:50:56.02#ibcon#*before return 0, iclass 34, count 0 2006.285.09:50:56.02#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:50:56.02#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.09:50:56.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:50:56.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:50:56.02$vck44/vblo=3,649.99 2006.285.09:50:56.02#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.09:50:56.02#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.09:50:56.02#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:56.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:50:56.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:50:56.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:50:56.02#ibcon#enter wrdev, iclass 36, count 0 2006.285.09:50:56.02#ibcon#first serial, iclass 36, count 0 2006.285.09:50:56.02#ibcon#enter sib2, iclass 36, count 0 2006.285.09:50:56.02#ibcon#flushed, iclass 36, count 0 2006.285.09:50:56.02#ibcon#about to write, iclass 36, count 0 2006.285.09:50:56.02#ibcon#wrote, iclass 36, count 0 2006.285.09:50:56.02#ibcon#about to read 3, iclass 36, count 0 2006.285.09:50:56.04#ibcon#read 3, iclass 36, count 0 2006.285.09:50:56.04#ibcon#about to read 4, iclass 36, count 0 2006.285.09:50:56.04#ibcon#read 4, iclass 36, count 0 2006.285.09:50:56.04#ibcon#about to read 5, iclass 36, count 0 2006.285.09:50:56.04#ibcon#read 5, iclass 36, count 0 2006.285.09:50:56.04#ibcon#about to read 6, iclass 36, count 0 2006.285.09:50:56.04#ibcon#read 6, iclass 36, count 0 2006.285.09:50:56.04#ibcon#end of sib2, iclass 36, count 0 2006.285.09:50:56.04#ibcon#*mode == 0, iclass 36, count 0 2006.285.09:50:56.04#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.09:50:56.04#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:50:56.04#ibcon#*before write, iclass 36, count 0 2006.285.09:50:56.04#ibcon#enter sib2, iclass 36, count 0 2006.285.09:50:56.04#ibcon#flushed, iclass 36, count 0 2006.285.09:50:56.04#ibcon#about to write, iclass 36, count 0 2006.285.09:50:56.04#ibcon#wrote, iclass 36, count 0 2006.285.09:50:56.04#ibcon#about to read 3, iclass 36, count 0 2006.285.09:50:56.08#ibcon#read 3, iclass 36, count 0 2006.285.09:50:56.08#ibcon#about to read 4, iclass 36, count 0 2006.285.09:50:56.08#ibcon#read 4, iclass 36, count 0 2006.285.09:50:56.08#ibcon#about to read 5, iclass 36, count 0 2006.285.09:50:56.08#ibcon#read 5, iclass 36, count 0 2006.285.09:50:56.08#ibcon#about to read 6, iclass 36, count 0 2006.285.09:50:56.08#ibcon#read 6, iclass 36, count 0 2006.285.09:50:56.08#ibcon#end of sib2, iclass 36, count 0 2006.285.09:50:56.08#ibcon#*after write, iclass 36, count 0 2006.285.09:50:56.08#ibcon#*before return 0, iclass 36, count 0 2006.285.09:50:56.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:50:56.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.09:50:56.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.09:50:56.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.09:50:56.08$vck44/vb=3,4 2006.285.09:50:56.08#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.09:50:56.08#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.09:50:56.08#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:56.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:50:56.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:50:56.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:50:56.14#ibcon#enter wrdev, iclass 38, count 2 2006.285.09:50:56.14#ibcon#first serial, iclass 38, count 2 2006.285.09:50:56.14#ibcon#enter sib2, iclass 38, count 2 2006.285.09:50:56.14#ibcon#flushed, iclass 38, count 2 2006.285.09:50:56.14#ibcon#about to write, iclass 38, count 2 2006.285.09:50:56.14#ibcon#wrote, iclass 38, count 2 2006.285.09:50:56.14#ibcon#about to read 3, iclass 38, count 2 2006.285.09:50:56.16#ibcon#read 3, iclass 38, count 2 2006.285.09:50:56.16#ibcon#about to read 4, iclass 38, count 2 2006.285.09:50:56.16#ibcon#read 4, iclass 38, count 2 2006.285.09:50:56.16#ibcon#about to read 5, iclass 38, count 2 2006.285.09:50:56.16#ibcon#read 5, iclass 38, count 2 2006.285.09:50:56.16#ibcon#about to read 6, iclass 38, count 2 2006.285.09:50:56.16#ibcon#read 6, iclass 38, count 2 2006.285.09:50:56.16#ibcon#end of sib2, iclass 38, count 2 2006.285.09:50:56.16#ibcon#*mode == 0, iclass 38, count 2 2006.285.09:50:56.16#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.09:50:56.16#ibcon#[27=AT03-04\r\n] 2006.285.09:50:56.16#ibcon#*before write, iclass 38, count 2 2006.285.09:50:56.16#ibcon#enter sib2, iclass 38, count 2 2006.285.09:50:56.16#ibcon#flushed, iclass 38, count 2 2006.285.09:50:56.16#ibcon#about to write, iclass 38, count 2 2006.285.09:50:56.16#ibcon#wrote, iclass 38, count 2 2006.285.09:50:56.16#ibcon#about to read 3, iclass 38, count 2 2006.285.09:50:56.19#ibcon#read 3, iclass 38, count 2 2006.285.09:50:56.19#ibcon#about to read 4, iclass 38, count 2 2006.285.09:50:56.19#ibcon#read 4, iclass 38, count 2 2006.285.09:50:56.19#ibcon#about to read 5, iclass 38, count 2 2006.285.09:50:56.19#ibcon#read 5, iclass 38, count 2 2006.285.09:50:56.19#ibcon#about to read 6, iclass 38, count 2 2006.285.09:50:56.19#ibcon#read 6, iclass 38, count 2 2006.285.09:50:56.19#ibcon#end of sib2, iclass 38, count 2 2006.285.09:50:56.19#ibcon#*after write, iclass 38, count 2 2006.285.09:50:56.19#ibcon#*before return 0, iclass 38, count 2 2006.285.09:50:56.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:50:56.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.09:50:56.19#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.09:50:56.19#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:56.19#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:50:56.31#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:50:56.31#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:50:56.31#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:50:56.31#ibcon#first serial, iclass 38, count 0 2006.285.09:50:56.31#ibcon#enter sib2, iclass 38, count 0 2006.285.09:50:56.31#ibcon#flushed, iclass 38, count 0 2006.285.09:50:56.31#ibcon#about to write, iclass 38, count 0 2006.285.09:50:56.31#ibcon#wrote, iclass 38, count 0 2006.285.09:50:56.31#ibcon#about to read 3, iclass 38, count 0 2006.285.09:50:56.33#ibcon#read 3, iclass 38, count 0 2006.285.09:50:56.33#ibcon#about to read 4, iclass 38, count 0 2006.285.09:50:56.33#ibcon#read 4, iclass 38, count 0 2006.285.09:50:56.33#ibcon#about to read 5, iclass 38, count 0 2006.285.09:50:56.33#ibcon#read 5, iclass 38, count 0 2006.285.09:50:56.33#ibcon#about to read 6, iclass 38, count 0 2006.285.09:50:56.33#ibcon#read 6, iclass 38, count 0 2006.285.09:50:56.33#ibcon#end of sib2, iclass 38, count 0 2006.285.09:50:56.33#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:50:56.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:50:56.33#ibcon#[27=USB\r\n] 2006.285.09:50:56.33#ibcon#*before write, iclass 38, count 0 2006.285.09:50:56.33#ibcon#enter sib2, iclass 38, count 0 2006.285.09:50:56.33#ibcon#flushed, iclass 38, count 0 2006.285.09:50:56.33#ibcon#about to write, iclass 38, count 0 2006.285.09:50:56.33#ibcon#wrote, iclass 38, count 0 2006.285.09:50:56.33#ibcon#about to read 3, iclass 38, count 0 2006.285.09:50:56.36#ibcon#read 3, iclass 38, count 0 2006.285.09:50:56.36#ibcon#about to read 4, iclass 38, count 0 2006.285.09:50:56.36#ibcon#read 4, iclass 38, count 0 2006.285.09:50:56.36#ibcon#about to read 5, iclass 38, count 0 2006.285.09:50:56.36#ibcon#read 5, iclass 38, count 0 2006.285.09:50:56.36#ibcon#about to read 6, iclass 38, count 0 2006.285.09:50:56.36#ibcon#read 6, iclass 38, count 0 2006.285.09:50:56.36#ibcon#end of sib2, iclass 38, count 0 2006.285.09:50:56.36#ibcon#*after write, iclass 38, count 0 2006.285.09:50:56.36#ibcon#*before return 0, iclass 38, count 0 2006.285.09:50:56.36#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:50:56.36#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.09:50:56.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:50:56.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:50:56.36$vck44/vblo=4,679.99 2006.285.09:50:56.36#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.09:50:56.36#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.09:50:56.36#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:56.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:50:56.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:50:56.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:50:56.36#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:50:56.36#ibcon#first serial, iclass 40, count 0 2006.285.09:50:56.36#ibcon#enter sib2, iclass 40, count 0 2006.285.09:50:56.36#ibcon#flushed, iclass 40, count 0 2006.285.09:50:56.36#ibcon#about to write, iclass 40, count 0 2006.285.09:50:56.36#ibcon#wrote, iclass 40, count 0 2006.285.09:50:56.36#ibcon#about to read 3, iclass 40, count 0 2006.285.09:50:56.38#ibcon#read 3, iclass 40, count 0 2006.285.09:50:56.38#ibcon#about to read 4, iclass 40, count 0 2006.285.09:50:56.38#ibcon#read 4, iclass 40, count 0 2006.285.09:50:56.38#ibcon#about to read 5, iclass 40, count 0 2006.285.09:50:56.38#ibcon#read 5, iclass 40, count 0 2006.285.09:50:56.38#ibcon#about to read 6, iclass 40, count 0 2006.285.09:50:56.38#ibcon#read 6, iclass 40, count 0 2006.285.09:50:56.38#ibcon#end of sib2, iclass 40, count 0 2006.285.09:50:56.38#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:50:56.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:50:56.38#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:50:56.38#ibcon#*before write, iclass 40, count 0 2006.285.09:50:56.38#ibcon#enter sib2, iclass 40, count 0 2006.285.09:50:56.38#ibcon#flushed, iclass 40, count 0 2006.285.09:50:56.38#ibcon#about to write, iclass 40, count 0 2006.285.09:50:56.38#ibcon#wrote, iclass 40, count 0 2006.285.09:50:56.38#ibcon#about to read 3, iclass 40, count 0 2006.285.09:50:56.42#ibcon#read 3, iclass 40, count 0 2006.285.09:50:56.42#ibcon#about to read 4, iclass 40, count 0 2006.285.09:50:56.42#ibcon#read 4, iclass 40, count 0 2006.285.09:50:56.42#ibcon#about to read 5, iclass 40, count 0 2006.285.09:50:56.42#ibcon#read 5, iclass 40, count 0 2006.285.09:50:56.42#ibcon#about to read 6, iclass 40, count 0 2006.285.09:50:56.42#ibcon#read 6, iclass 40, count 0 2006.285.09:50:56.42#ibcon#end of sib2, iclass 40, count 0 2006.285.09:50:56.42#ibcon#*after write, iclass 40, count 0 2006.285.09:50:56.42#ibcon#*before return 0, iclass 40, count 0 2006.285.09:50:56.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:50:56.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.09:50:56.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:50:56.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:50:56.42$vck44/vb=4,5 2006.285.09:50:56.42#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.09:50:56.42#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.09:50:56.42#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:56.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:50:56.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:50:56.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:50:56.48#ibcon#enter wrdev, iclass 4, count 2 2006.285.09:50:56.48#ibcon#first serial, iclass 4, count 2 2006.285.09:50:56.48#ibcon#enter sib2, iclass 4, count 2 2006.285.09:50:56.48#ibcon#flushed, iclass 4, count 2 2006.285.09:50:56.48#ibcon#about to write, iclass 4, count 2 2006.285.09:50:56.48#ibcon#wrote, iclass 4, count 2 2006.285.09:50:56.48#ibcon#about to read 3, iclass 4, count 2 2006.285.09:50:56.50#ibcon#read 3, iclass 4, count 2 2006.285.09:50:56.50#ibcon#about to read 4, iclass 4, count 2 2006.285.09:50:56.50#ibcon#read 4, iclass 4, count 2 2006.285.09:50:56.50#ibcon#about to read 5, iclass 4, count 2 2006.285.09:50:56.50#ibcon#read 5, iclass 4, count 2 2006.285.09:50:56.50#ibcon#about to read 6, iclass 4, count 2 2006.285.09:50:56.50#ibcon#read 6, iclass 4, count 2 2006.285.09:50:56.50#ibcon#end of sib2, iclass 4, count 2 2006.285.09:50:56.50#ibcon#*mode == 0, iclass 4, count 2 2006.285.09:50:56.50#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.09:50:56.50#ibcon#[27=AT04-05\r\n] 2006.285.09:50:56.50#ibcon#*before write, iclass 4, count 2 2006.285.09:50:56.50#ibcon#enter sib2, iclass 4, count 2 2006.285.09:50:56.50#ibcon#flushed, iclass 4, count 2 2006.285.09:50:56.50#ibcon#about to write, iclass 4, count 2 2006.285.09:50:56.50#ibcon#wrote, iclass 4, count 2 2006.285.09:50:56.50#ibcon#about to read 3, iclass 4, count 2 2006.285.09:50:56.53#ibcon#read 3, iclass 4, count 2 2006.285.09:50:56.53#ibcon#about to read 4, iclass 4, count 2 2006.285.09:50:56.53#ibcon#read 4, iclass 4, count 2 2006.285.09:50:56.53#ibcon#about to read 5, iclass 4, count 2 2006.285.09:50:56.53#ibcon#read 5, iclass 4, count 2 2006.285.09:50:56.53#ibcon#about to read 6, iclass 4, count 2 2006.285.09:50:56.53#ibcon#read 6, iclass 4, count 2 2006.285.09:50:56.53#ibcon#end of sib2, iclass 4, count 2 2006.285.09:50:56.53#ibcon#*after write, iclass 4, count 2 2006.285.09:50:56.53#ibcon#*before return 0, iclass 4, count 2 2006.285.09:50:56.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:50:56.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.09:50:56.53#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.09:50:56.53#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:56.53#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:50:56.65#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:50:56.65#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:50:56.65#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:50:56.65#ibcon#first serial, iclass 4, count 0 2006.285.09:50:56.65#ibcon#enter sib2, iclass 4, count 0 2006.285.09:50:56.65#ibcon#flushed, iclass 4, count 0 2006.285.09:50:56.65#ibcon#about to write, iclass 4, count 0 2006.285.09:50:56.65#ibcon#wrote, iclass 4, count 0 2006.285.09:50:56.65#ibcon#about to read 3, iclass 4, count 0 2006.285.09:50:56.67#ibcon#read 3, iclass 4, count 0 2006.285.09:50:56.67#ibcon#about to read 4, iclass 4, count 0 2006.285.09:50:56.67#ibcon#read 4, iclass 4, count 0 2006.285.09:50:56.67#ibcon#about to read 5, iclass 4, count 0 2006.285.09:50:56.67#ibcon#read 5, iclass 4, count 0 2006.285.09:50:56.67#ibcon#about to read 6, iclass 4, count 0 2006.285.09:50:56.67#ibcon#read 6, iclass 4, count 0 2006.285.09:50:56.67#ibcon#end of sib2, iclass 4, count 0 2006.285.09:50:56.67#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:50:56.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:50:56.67#ibcon#[27=USB\r\n] 2006.285.09:50:56.67#ibcon#*before write, iclass 4, count 0 2006.285.09:50:56.67#ibcon#enter sib2, iclass 4, count 0 2006.285.09:50:56.67#ibcon#flushed, iclass 4, count 0 2006.285.09:50:56.67#ibcon#about to write, iclass 4, count 0 2006.285.09:50:56.67#ibcon#wrote, iclass 4, count 0 2006.285.09:50:56.67#ibcon#about to read 3, iclass 4, count 0 2006.285.09:50:56.70#ibcon#read 3, iclass 4, count 0 2006.285.09:50:56.70#ibcon#about to read 4, iclass 4, count 0 2006.285.09:50:56.70#ibcon#read 4, iclass 4, count 0 2006.285.09:50:56.70#ibcon#about to read 5, iclass 4, count 0 2006.285.09:50:56.70#ibcon#read 5, iclass 4, count 0 2006.285.09:50:56.70#ibcon#about to read 6, iclass 4, count 0 2006.285.09:50:56.70#ibcon#read 6, iclass 4, count 0 2006.285.09:50:56.70#ibcon#end of sib2, iclass 4, count 0 2006.285.09:50:56.70#ibcon#*after write, iclass 4, count 0 2006.285.09:50:56.70#ibcon#*before return 0, iclass 4, count 0 2006.285.09:50:56.70#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:50:56.70#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.09:50:56.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:50:56.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:50:56.70$vck44/vblo=5,709.99 2006.285.09:50:56.70#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.09:50:56.70#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.09:50:56.70#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:56.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:50:56.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:50:56.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:50:56.70#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:50:56.70#ibcon#first serial, iclass 6, count 0 2006.285.09:50:56.70#ibcon#enter sib2, iclass 6, count 0 2006.285.09:50:56.70#ibcon#flushed, iclass 6, count 0 2006.285.09:50:56.70#ibcon#about to write, iclass 6, count 0 2006.285.09:50:56.70#ibcon#wrote, iclass 6, count 0 2006.285.09:50:56.70#ibcon#about to read 3, iclass 6, count 0 2006.285.09:50:56.72#ibcon#read 3, iclass 6, count 0 2006.285.09:50:56.72#ibcon#about to read 4, iclass 6, count 0 2006.285.09:50:56.72#ibcon#read 4, iclass 6, count 0 2006.285.09:50:56.72#ibcon#about to read 5, iclass 6, count 0 2006.285.09:50:56.72#ibcon#read 5, iclass 6, count 0 2006.285.09:50:56.72#ibcon#about to read 6, iclass 6, count 0 2006.285.09:50:56.72#ibcon#read 6, iclass 6, count 0 2006.285.09:50:56.72#ibcon#end of sib2, iclass 6, count 0 2006.285.09:50:56.72#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:50:56.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:50:56.72#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:50:56.72#ibcon#*before write, iclass 6, count 0 2006.285.09:50:56.72#ibcon#enter sib2, iclass 6, count 0 2006.285.09:50:56.72#ibcon#flushed, iclass 6, count 0 2006.285.09:50:56.72#ibcon#about to write, iclass 6, count 0 2006.285.09:50:56.72#ibcon#wrote, iclass 6, count 0 2006.285.09:50:56.72#ibcon#about to read 3, iclass 6, count 0 2006.285.09:50:56.76#ibcon#read 3, iclass 6, count 0 2006.285.09:50:56.76#ibcon#about to read 4, iclass 6, count 0 2006.285.09:50:56.76#ibcon#read 4, iclass 6, count 0 2006.285.09:50:56.76#ibcon#about to read 5, iclass 6, count 0 2006.285.09:50:56.76#ibcon#read 5, iclass 6, count 0 2006.285.09:50:56.76#ibcon#about to read 6, iclass 6, count 0 2006.285.09:50:56.76#ibcon#read 6, iclass 6, count 0 2006.285.09:50:56.76#ibcon#end of sib2, iclass 6, count 0 2006.285.09:50:56.76#ibcon#*after write, iclass 6, count 0 2006.285.09:50:56.76#ibcon#*before return 0, iclass 6, count 0 2006.285.09:50:56.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:50:56.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.09:50:56.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:50:56.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:50:56.76$vck44/vb=5,4 2006.285.09:50:56.76#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.09:50:56.76#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.09:50:56.76#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:56.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:50:56.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:50:56.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:50:56.82#ibcon#enter wrdev, iclass 10, count 2 2006.285.09:50:56.82#ibcon#first serial, iclass 10, count 2 2006.285.09:50:56.82#ibcon#enter sib2, iclass 10, count 2 2006.285.09:50:56.82#ibcon#flushed, iclass 10, count 2 2006.285.09:50:56.82#ibcon#about to write, iclass 10, count 2 2006.285.09:50:56.82#ibcon#wrote, iclass 10, count 2 2006.285.09:50:56.82#ibcon#about to read 3, iclass 10, count 2 2006.285.09:50:56.84#ibcon#read 3, iclass 10, count 2 2006.285.09:50:56.84#ibcon#about to read 4, iclass 10, count 2 2006.285.09:50:56.84#ibcon#read 4, iclass 10, count 2 2006.285.09:50:56.84#ibcon#about to read 5, iclass 10, count 2 2006.285.09:50:56.84#ibcon#read 5, iclass 10, count 2 2006.285.09:50:56.84#ibcon#about to read 6, iclass 10, count 2 2006.285.09:50:56.84#ibcon#read 6, iclass 10, count 2 2006.285.09:50:56.84#ibcon#end of sib2, iclass 10, count 2 2006.285.09:50:56.84#ibcon#*mode == 0, iclass 10, count 2 2006.285.09:50:56.84#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.09:50:56.84#ibcon#[27=AT05-04\r\n] 2006.285.09:50:56.84#ibcon#*before write, iclass 10, count 2 2006.285.09:50:56.84#ibcon#enter sib2, iclass 10, count 2 2006.285.09:50:56.84#ibcon#flushed, iclass 10, count 2 2006.285.09:50:56.84#ibcon#about to write, iclass 10, count 2 2006.285.09:50:56.84#ibcon#wrote, iclass 10, count 2 2006.285.09:50:56.84#ibcon#about to read 3, iclass 10, count 2 2006.285.09:50:56.87#ibcon#read 3, iclass 10, count 2 2006.285.09:50:56.87#ibcon#about to read 4, iclass 10, count 2 2006.285.09:50:56.87#ibcon#read 4, iclass 10, count 2 2006.285.09:50:56.87#ibcon#about to read 5, iclass 10, count 2 2006.285.09:50:56.87#ibcon#read 5, iclass 10, count 2 2006.285.09:50:56.87#ibcon#about to read 6, iclass 10, count 2 2006.285.09:50:56.87#ibcon#read 6, iclass 10, count 2 2006.285.09:50:56.87#ibcon#end of sib2, iclass 10, count 2 2006.285.09:50:56.87#ibcon#*after write, iclass 10, count 2 2006.285.09:50:56.87#ibcon#*before return 0, iclass 10, count 2 2006.285.09:50:56.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:50:56.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.09:50:56.87#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.09:50:56.87#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:56.87#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:50:56.99#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:50:56.99#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:50:56.99#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:50:56.99#ibcon#first serial, iclass 10, count 0 2006.285.09:50:56.99#ibcon#enter sib2, iclass 10, count 0 2006.285.09:50:56.99#ibcon#flushed, iclass 10, count 0 2006.285.09:50:56.99#ibcon#about to write, iclass 10, count 0 2006.285.09:50:56.99#ibcon#wrote, iclass 10, count 0 2006.285.09:50:56.99#ibcon#about to read 3, iclass 10, count 0 2006.285.09:50:57.01#ibcon#read 3, iclass 10, count 0 2006.285.09:50:57.01#ibcon#about to read 4, iclass 10, count 0 2006.285.09:50:57.01#ibcon#read 4, iclass 10, count 0 2006.285.09:50:57.01#ibcon#about to read 5, iclass 10, count 0 2006.285.09:50:57.01#ibcon#read 5, iclass 10, count 0 2006.285.09:50:57.01#ibcon#about to read 6, iclass 10, count 0 2006.285.09:50:57.01#ibcon#read 6, iclass 10, count 0 2006.285.09:50:57.01#ibcon#end of sib2, iclass 10, count 0 2006.285.09:50:57.01#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:50:57.01#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:50:57.01#ibcon#[27=USB\r\n] 2006.285.09:50:57.01#ibcon#*before write, iclass 10, count 0 2006.285.09:50:57.01#ibcon#enter sib2, iclass 10, count 0 2006.285.09:50:57.01#ibcon#flushed, iclass 10, count 0 2006.285.09:50:57.01#ibcon#about to write, iclass 10, count 0 2006.285.09:50:57.01#ibcon#wrote, iclass 10, count 0 2006.285.09:50:57.01#ibcon#about to read 3, iclass 10, count 0 2006.285.09:50:57.04#ibcon#read 3, iclass 10, count 0 2006.285.09:50:57.04#ibcon#about to read 4, iclass 10, count 0 2006.285.09:50:57.04#ibcon#read 4, iclass 10, count 0 2006.285.09:50:57.04#ibcon#about to read 5, iclass 10, count 0 2006.285.09:50:57.04#ibcon#read 5, iclass 10, count 0 2006.285.09:50:57.04#ibcon#about to read 6, iclass 10, count 0 2006.285.09:50:57.04#ibcon#read 6, iclass 10, count 0 2006.285.09:50:57.04#ibcon#end of sib2, iclass 10, count 0 2006.285.09:50:57.04#ibcon#*after write, iclass 10, count 0 2006.285.09:50:57.04#ibcon#*before return 0, iclass 10, count 0 2006.285.09:50:57.04#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:50:57.04#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.09:50:57.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:50:57.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:50:57.04$vck44/vblo=6,719.99 2006.285.09:50:57.04#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.09:50:57.04#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.09:50:57.04#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:57.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:50:57.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:50:57.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:50:57.04#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:50:57.04#ibcon#first serial, iclass 12, count 0 2006.285.09:50:57.04#ibcon#enter sib2, iclass 12, count 0 2006.285.09:50:57.04#ibcon#flushed, iclass 12, count 0 2006.285.09:50:57.04#ibcon#about to write, iclass 12, count 0 2006.285.09:50:57.04#ibcon#wrote, iclass 12, count 0 2006.285.09:50:57.04#ibcon#about to read 3, iclass 12, count 0 2006.285.09:50:57.06#ibcon#read 3, iclass 12, count 0 2006.285.09:50:57.06#ibcon#about to read 4, iclass 12, count 0 2006.285.09:50:57.06#ibcon#read 4, iclass 12, count 0 2006.285.09:50:57.06#ibcon#about to read 5, iclass 12, count 0 2006.285.09:50:57.06#ibcon#read 5, iclass 12, count 0 2006.285.09:50:57.06#ibcon#about to read 6, iclass 12, count 0 2006.285.09:50:57.06#ibcon#read 6, iclass 12, count 0 2006.285.09:50:57.06#ibcon#end of sib2, iclass 12, count 0 2006.285.09:50:57.06#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:50:57.06#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:50:57.06#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:50:57.06#ibcon#*before write, iclass 12, count 0 2006.285.09:50:57.06#ibcon#enter sib2, iclass 12, count 0 2006.285.09:50:57.06#ibcon#flushed, iclass 12, count 0 2006.285.09:50:57.06#ibcon#about to write, iclass 12, count 0 2006.285.09:50:57.06#ibcon#wrote, iclass 12, count 0 2006.285.09:50:57.06#ibcon#about to read 3, iclass 12, count 0 2006.285.09:50:57.10#ibcon#read 3, iclass 12, count 0 2006.285.09:50:57.10#ibcon#about to read 4, iclass 12, count 0 2006.285.09:50:57.10#ibcon#read 4, iclass 12, count 0 2006.285.09:50:57.10#ibcon#about to read 5, iclass 12, count 0 2006.285.09:50:57.10#ibcon#read 5, iclass 12, count 0 2006.285.09:50:57.10#ibcon#about to read 6, iclass 12, count 0 2006.285.09:50:57.10#ibcon#read 6, iclass 12, count 0 2006.285.09:50:57.10#ibcon#end of sib2, iclass 12, count 0 2006.285.09:50:57.10#ibcon#*after write, iclass 12, count 0 2006.285.09:50:57.10#ibcon#*before return 0, iclass 12, count 0 2006.285.09:50:57.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:50:57.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:50:57.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:50:57.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:50:57.10$vck44/vb=6,3 2006.285.09:50:57.10#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.09:50:57.10#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.09:50:57.10#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:57.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:50:57.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:50:57.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:50:57.16#ibcon#enter wrdev, iclass 14, count 2 2006.285.09:50:57.16#ibcon#first serial, iclass 14, count 2 2006.285.09:50:57.16#ibcon#enter sib2, iclass 14, count 2 2006.285.09:50:57.16#ibcon#flushed, iclass 14, count 2 2006.285.09:50:57.16#ibcon#about to write, iclass 14, count 2 2006.285.09:50:57.16#ibcon#wrote, iclass 14, count 2 2006.285.09:50:57.16#ibcon#about to read 3, iclass 14, count 2 2006.285.09:50:57.18#ibcon#read 3, iclass 14, count 2 2006.285.09:50:57.18#ibcon#about to read 4, iclass 14, count 2 2006.285.09:50:57.18#ibcon#read 4, iclass 14, count 2 2006.285.09:50:57.18#ibcon#about to read 5, iclass 14, count 2 2006.285.09:50:57.18#ibcon#read 5, iclass 14, count 2 2006.285.09:50:57.18#ibcon#about to read 6, iclass 14, count 2 2006.285.09:50:57.18#ibcon#read 6, iclass 14, count 2 2006.285.09:50:57.18#ibcon#end of sib2, iclass 14, count 2 2006.285.09:50:57.18#ibcon#*mode == 0, iclass 14, count 2 2006.285.09:50:57.18#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.09:50:57.18#ibcon#[27=AT06-03\r\n] 2006.285.09:50:57.18#ibcon#*before write, iclass 14, count 2 2006.285.09:50:57.18#ibcon#enter sib2, iclass 14, count 2 2006.285.09:50:57.18#ibcon#flushed, iclass 14, count 2 2006.285.09:50:57.18#ibcon#about to write, iclass 14, count 2 2006.285.09:50:57.18#ibcon#wrote, iclass 14, count 2 2006.285.09:50:57.18#ibcon#about to read 3, iclass 14, count 2 2006.285.09:50:57.21#ibcon#read 3, iclass 14, count 2 2006.285.09:50:57.21#ibcon#about to read 4, iclass 14, count 2 2006.285.09:50:57.21#ibcon#read 4, iclass 14, count 2 2006.285.09:50:57.21#ibcon#about to read 5, iclass 14, count 2 2006.285.09:50:57.21#ibcon#read 5, iclass 14, count 2 2006.285.09:50:57.21#ibcon#about to read 6, iclass 14, count 2 2006.285.09:50:57.21#ibcon#read 6, iclass 14, count 2 2006.285.09:50:57.21#ibcon#end of sib2, iclass 14, count 2 2006.285.09:50:57.21#ibcon#*after write, iclass 14, count 2 2006.285.09:50:57.21#ibcon#*before return 0, iclass 14, count 2 2006.285.09:50:57.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:50:57.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.09:50:57.21#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.09:50:57.21#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:57.21#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:50:57.33#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:50:57.33#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:50:57.33#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:50:57.33#ibcon#first serial, iclass 14, count 0 2006.285.09:50:57.33#ibcon#enter sib2, iclass 14, count 0 2006.285.09:50:57.33#ibcon#flushed, iclass 14, count 0 2006.285.09:50:57.33#ibcon#about to write, iclass 14, count 0 2006.285.09:50:57.33#ibcon#wrote, iclass 14, count 0 2006.285.09:50:57.33#ibcon#about to read 3, iclass 14, count 0 2006.285.09:50:57.35#ibcon#read 3, iclass 14, count 0 2006.285.09:50:57.35#ibcon#about to read 4, iclass 14, count 0 2006.285.09:50:57.35#ibcon#read 4, iclass 14, count 0 2006.285.09:50:57.35#ibcon#about to read 5, iclass 14, count 0 2006.285.09:50:57.35#ibcon#read 5, iclass 14, count 0 2006.285.09:50:57.35#ibcon#about to read 6, iclass 14, count 0 2006.285.09:50:57.35#ibcon#read 6, iclass 14, count 0 2006.285.09:50:57.35#ibcon#end of sib2, iclass 14, count 0 2006.285.09:50:57.35#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:50:57.35#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:50:57.35#ibcon#[27=USB\r\n] 2006.285.09:50:57.35#ibcon#*before write, iclass 14, count 0 2006.285.09:50:57.35#ibcon#enter sib2, iclass 14, count 0 2006.285.09:50:57.35#ibcon#flushed, iclass 14, count 0 2006.285.09:50:57.35#ibcon#about to write, iclass 14, count 0 2006.285.09:50:57.35#ibcon#wrote, iclass 14, count 0 2006.285.09:50:57.35#ibcon#about to read 3, iclass 14, count 0 2006.285.09:50:57.38#ibcon#read 3, iclass 14, count 0 2006.285.09:50:57.38#ibcon#about to read 4, iclass 14, count 0 2006.285.09:50:57.38#ibcon#read 4, iclass 14, count 0 2006.285.09:50:57.38#ibcon#about to read 5, iclass 14, count 0 2006.285.09:50:57.38#ibcon#read 5, iclass 14, count 0 2006.285.09:50:57.38#ibcon#about to read 6, iclass 14, count 0 2006.285.09:50:57.38#ibcon#read 6, iclass 14, count 0 2006.285.09:50:57.38#ibcon#end of sib2, iclass 14, count 0 2006.285.09:50:57.38#ibcon#*after write, iclass 14, count 0 2006.285.09:50:57.38#ibcon#*before return 0, iclass 14, count 0 2006.285.09:50:57.38#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:50:57.38#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.09:50:57.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:50:57.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:50:57.38$vck44/vblo=7,734.99 2006.285.09:50:57.38#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.09:50:57.38#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.09:50:57.38#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:57.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:50:57.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:50:57.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:50:57.38#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:50:57.38#ibcon#first serial, iclass 16, count 0 2006.285.09:50:57.38#ibcon#enter sib2, iclass 16, count 0 2006.285.09:50:57.38#ibcon#flushed, iclass 16, count 0 2006.285.09:50:57.38#ibcon#about to write, iclass 16, count 0 2006.285.09:50:57.38#ibcon#wrote, iclass 16, count 0 2006.285.09:50:57.38#ibcon#about to read 3, iclass 16, count 0 2006.285.09:50:57.40#ibcon#read 3, iclass 16, count 0 2006.285.09:50:57.40#ibcon#about to read 4, iclass 16, count 0 2006.285.09:50:57.40#ibcon#read 4, iclass 16, count 0 2006.285.09:50:57.40#ibcon#about to read 5, iclass 16, count 0 2006.285.09:50:57.40#ibcon#read 5, iclass 16, count 0 2006.285.09:50:57.40#ibcon#about to read 6, iclass 16, count 0 2006.285.09:50:57.40#ibcon#read 6, iclass 16, count 0 2006.285.09:50:57.40#ibcon#end of sib2, iclass 16, count 0 2006.285.09:50:57.40#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:50:57.40#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:50:57.40#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:50:57.40#ibcon#*before write, iclass 16, count 0 2006.285.09:50:57.40#ibcon#enter sib2, iclass 16, count 0 2006.285.09:50:57.40#ibcon#flushed, iclass 16, count 0 2006.285.09:50:57.40#ibcon#about to write, iclass 16, count 0 2006.285.09:50:57.40#ibcon#wrote, iclass 16, count 0 2006.285.09:50:57.40#ibcon#about to read 3, iclass 16, count 0 2006.285.09:50:57.44#ibcon#read 3, iclass 16, count 0 2006.285.09:50:57.44#ibcon#about to read 4, iclass 16, count 0 2006.285.09:50:57.44#ibcon#read 4, iclass 16, count 0 2006.285.09:50:57.44#ibcon#about to read 5, iclass 16, count 0 2006.285.09:50:57.44#ibcon#read 5, iclass 16, count 0 2006.285.09:50:57.44#ibcon#about to read 6, iclass 16, count 0 2006.285.09:50:57.44#ibcon#read 6, iclass 16, count 0 2006.285.09:50:57.44#ibcon#end of sib2, iclass 16, count 0 2006.285.09:50:57.44#ibcon#*after write, iclass 16, count 0 2006.285.09:50:57.44#ibcon#*before return 0, iclass 16, count 0 2006.285.09:50:57.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:50:57.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.09:50:57.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:50:57.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:50:57.44$vck44/vb=7,4 2006.285.09:50:57.44#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.09:50:57.44#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.09:50:57.44#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:57.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:50:57.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:50:57.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:50:57.50#ibcon#enter wrdev, iclass 18, count 2 2006.285.09:50:57.50#ibcon#first serial, iclass 18, count 2 2006.285.09:50:57.50#ibcon#enter sib2, iclass 18, count 2 2006.285.09:50:57.50#ibcon#flushed, iclass 18, count 2 2006.285.09:50:57.50#ibcon#about to write, iclass 18, count 2 2006.285.09:50:57.50#ibcon#wrote, iclass 18, count 2 2006.285.09:50:57.50#ibcon#about to read 3, iclass 18, count 2 2006.285.09:50:57.52#ibcon#read 3, iclass 18, count 2 2006.285.09:50:57.52#ibcon#about to read 4, iclass 18, count 2 2006.285.09:50:57.52#ibcon#read 4, iclass 18, count 2 2006.285.09:50:57.52#ibcon#about to read 5, iclass 18, count 2 2006.285.09:50:57.52#ibcon#read 5, iclass 18, count 2 2006.285.09:50:57.52#ibcon#about to read 6, iclass 18, count 2 2006.285.09:50:57.52#ibcon#read 6, iclass 18, count 2 2006.285.09:50:57.52#ibcon#end of sib2, iclass 18, count 2 2006.285.09:50:57.52#ibcon#*mode == 0, iclass 18, count 2 2006.285.09:50:57.52#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.09:50:57.52#ibcon#[27=AT07-04\r\n] 2006.285.09:50:57.52#ibcon#*before write, iclass 18, count 2 2006.285.09:50:57.52#ibcon#enter sib2, iclass 18, count 2 2006.285.09:50:57.52#ibcon#flushed, iclass 18, count 2 2006.285.09:50:57.52#ibcon#about to write, iclass 18, count 2 2006.285.09:50:57.52#ibcon#wrote, iclass 18, count 2 2006.285.09:50:57.52#ibcon#about to read 3, iclass 18, count 2 2006.285.09:50:57.55#ibcon#read 3, iclass 18, count 2 2006.285.09:50:57.55#ibcon#about to read 4, iclass 18, count 2 2006.285.09:50:57.55#ibcon#read 4, iclass 18, count 2 2006.285.09:50:57.55#ibcon#about to read 5, iclass 18, count 2 2006.285.09:50:57.55#ibcon#read 5, iclass 18, count 2 2006.285.09:50:57.55#ibcon#about to read 6, iclass 18, count 2 2006.285.09:50:57.55#ibcon#read 6, iclass 18, count 2 2006.285.09:50:57.55#ibcon#end of sib2, iclass 18, count 2 2006.285.09:50:57.55#ibcon#*after write, iclass 18, count 2 2006.285.09:50:57.55#ibcon#*before return 0, iclass 18, count 2 2006.285.09:50:57.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:50:57.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.09:50:57.55#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.09:50:57.55#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:57.55#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:50:57.67#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:50:57.67#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:50:57.67#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:50:57.67#ibcon#first serial, iclass 18, count 0 2006.285.09:50:57.67#ibcon#enter sib2, iclass 18, count 0 2006.285.09:50:57.67#ibcon#flushed, iclass 18, count 0 2006.285.09:50:57.67#ibcon#about to write, iclass 18, count 0 2006.285.09:50:57.67#ibcon#wrote, iclass 18, count 0 2006.285.09:50:57.67#ibcon#about to read 3, iclass 18, count 0 2006.285.09:50:57.69#ibcon#read 3, iclass 18, count 0 2006.285.09:50:57.69#ibcon#about to read 4, iclass 18, count 0 2006.285.09:50:57.69#ibcon#read 4, iclass 18, count 0 2006.285.09:50:57.69#ibcon#about to read 5, iclass 18, count 0 2006.285.09:50:57.69#ibcon#read 5, iclass 18, count 0 2006.285.09:50:57.69#ibcon#about to read 6, iclass 18, count 0 2006.285.09:50:57.69#ibcon#read 6, iclass 18, count 0 2006.285.09:50:57.69#ibcon#end of sib2, iclass 18, count 0 2006.285.09:50:57.69#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:50:57.69#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:50:57.69#ibcon#[27=USB\r\n] 2006.285.09:50:57.69#ibcon#*before write, iclass 18, count 0 2006.285.09:50:57.69#ibcon#enter sib2, iclass 18, count 0 2006.285.09:50:57.69#ibcon#flushed, iclass 18, count 0 2006.285.09:50:57.69#ibcon#about to write, iclass 18, count 0 2006.285.09:50:57.69#ibcon#wrote, iclass 18, count 0 2006.285.09:50:57.69#ibcon#about to read 3, iclass 18, count 0 2006.285.09:50:57.72#ibcon#read 3, iclass 18, count 0 2006.285.09:50:57.72#ibcon#about to read 4, iclass 18, count 0 2006.285.09:50:57.72#ibcon#read 4, iclass 18, count 0 2006.285.09:50:57.72#ibcon#about to read 5, iclass 18, count 0 2006.285.09:50:57.72#ibcon#read 5, iclass 18, count 0 2006.285.09:50:57.72#ibcon#about to read 6, iclass 18, count 0 2006.285.09:50:57.72#ibcon#read 6, iclass 18, count 0 2006.285.09:50:57.72#ibcon#end of sib2, iclass 18, count 0 2006.285.09:50:57.72#ibcon#*after write, iclass 18, count 0 2006.285.09:50:57.72#ibcon#*before return 0, iclass 18, count 0 2006.285.09:50:57.72#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:50:57.72#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.09:50:57.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:50:57.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:50:57.72$vck44/vblo=8,744.99 2006.285.09:50:57.72#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.09:50:57.72#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.09:50:57.72#ibcon#ireg 17 cls_cnt 0 2006.285.09:50:57.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:50:57.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:50:57.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:50:57.72#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:50:57.72#ibcon#first serial, iclass 20, count 0 2006.285.09:50:57.72#ibcon#enter sib2, iclass 20, count 0 2006.285.09:50:57.72#ibcon#flushed, iclass 20, count 0 2006.285.09:50:57.72#ibcon#about to write, iclass 20, count 0 2006.285.09:50:57.72#ibcon#wrote, iclass 20, count 0 2006.285.09:50:57.72#ibcon#about to read 3, iclass 20, count 0 2006.285.09:50:57.74#ibcon#read 3, iclass 20, count 0 2006.285.09:50:57.74#ibcon#about to read 4, iclass 20, count 0 2006.285.09:50:57.74#ibcon#read 4, iclass 20, count 0 2006.285.09:50:57.74#ibcon#about to read 5, iclass 20, count 0 2006.285.09:50:57.74#ibcon#read 5, iclass 20, count 0 2006.285.09:50:57.74#ibcon#about to read 6, iclass 20, count 0 2006.285.09:50:57.74#ibcon#read 6, iclass 20, count 0 2006.285.09:50:57.74#ibcon#end of sib2, iclass 20, count 0 2006.285.09:50:57.74#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:50:57.74#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:50:57.74#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:50:57.74#ibcon#*before write, iclass 20, count 0 2006.285.09:50:57.74#ibcon#enter sib2, iclass 20, count 0 2006.285.09:50:57.74#ibcon#flushed, iclass 20, count 0 2006.285.09:50:57.74#ibcon#about to write, iclass 20, count 0 2006.285.09:50:57.74#ibcon#wrote, iclass 20, count 0 2006.285.09:50:57.74#ibcon#about to read 3, iclass 20, count 0 2006.285.09:50:57.78#ibcon#read 3, iclass 20, count 0 2006.285.09:50:57.78#ibcon#about to read 4, iclass 20, count 0 2006.285.09:50:57.78#ibcon#read 4, iclass 20, count 0 2006.285.09:50:57.78#ibcon#about to read 5, iclass 20, count 0 2006.285.09:50:57.78#ibcon#read 5, iclass 20, count 0 2006.285.09:50:57.78#ibcon#about to read 6, iclass 20, count 0 2006.285.09:50:57.78#ibcon#read 6, iclass 20, count 0 2006.285.09:50:57.78#ibcon#end of sib2, iclass 20, count 0 2006.285.09:50:57.78#ibcon#*after write, iclass 20, count 0 2006.285.09:50:57.78#ibcon#*before return 0, iclass 20, count 0 2006.285.09:50:57.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:50:57.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.09:50:57.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:50:57.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:50:57.78$vck44/vb=8,4 2006.285.09:50:57.78#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.09:50:57.78#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.09:50:57.78#ibcon#ireg 11 cls_cnt 2 2006.285.09:50:57.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:50:57.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:50:57.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:50:57.84#ibcon#enter wrdev, iclass 22, count 2 2006.285.09:50:57.84#ibcon#first serial, iclass 22, count 2 2006.285.09:50:57.84#ibcon#enter sib2, iclass 22, count 2 2006.285.09:50:57.84#ibcon#flushed, iclass 22, count 2 2006.285.09:50:57.84#ibcon#about to write, iclass 22, count 2 2006.285.09:50:57.84#ibcon#wrote, iclass 22, count 2 2006.285.09:50:57.84#ibcon#about to read 3, iclass 22, count 2 2006.285.09:50:57.86#ibcon#read 3, iclass 22, count 2 2006.285.09:50:57.86#ibcon#about to read 4, iclass 22, count 2 2006.285.09:50:57.86#ibcon#read 4, iclass 22, count 2 2006.285.09:50:57.86#ibcon#about to read 5, iclass 22, count 2 2006.285.09:50:57.86#ibcon#read 5, iclass 22, count 2 2006.285.09:50:57.86#ibcon#about to read 6, iclass 22, count 2 2006.285.09:50:57.86#ibcon#read 6, iclass 22, count 2 2006.285.09:50:57.86#ibcon#end of sib2, iclass 22, count 2 2006.285.09:50:57.86#ibcon#*mode == 0, iclass 22, count 2 2006.285.09:50:57.86#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.09:50:57.86#ibcon#[27=AT08-04\r\n] 2006.285.09:50:57.86#ibcon#*before write, iclass 22, count 2 2006.285.09:50:57.86#ibcon#enter sib2, iclass 22, count 2 2006.285.09:50:57.86#ibcon#flushed, iclass 22, count 2 2006.285.09:50:57.86#ibcon#about to write, iclass 22, count 2 2006.285.09:50:57.86#ibcon#wrote, iclass 22, count 2 2006.285.09:50:57.86#ibcon#about to read 3, iclass 22, count 2 2006.285.09:50:57.89#ibcon#read 3, iclass 22, count 2 2006.285.09:50:57.89#ibcon#about to read 4, iclass 22, count 2 2006.285.09:50:57.89#ibcon#read 4, iclass 22, count 2 2006.285.09:50:57.89#ibcon#about to read 5, iclass 22, count 2 2006.285.09:50:57.89#ibcon#read 5, iclass 22, count 2 2006.285.09:50:57.89#ibcon#about to read 6, iclass 22, count 2 2006.285.09:50:57.89#ibcon#read 6, iclass 22, count 2 2006.285.09:50:57.89#ibcon#end of sib2, iclass 22, count 2 2006.285.09:50:57.89#ibcon#*after write, iclass 22, count 2 2006.285.09:50:57.89#ibcon#*before return 0, iclass 22, count 2 2006.285.09:50:57.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:50:57.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.09:50:57.89#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.09:50:57.89#ibcon#ireg 7 cls_cnt 0 2006.285.09:50:57.89#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:50:58.01#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:50:58.01#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:50:58.01#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:50:58.01#ibcon#first serial, iclass 22, count 0 2006.285.09:50:58.01#ibcon#enter sib2, iclass 22, count 0 2006.285.09:50:58.01#ibcon#flushed, iclass 22, count 0 2006.285.09:50:58.01#ibcon#about to write, iclass 22, count 0 2006.285.09:50:58.01#ibcon#wrote, iclass 22, count 0 2006.285.09:50:58.01#ibcon#about to read 3, iclass 22, count 0 2006.285.09:50:58.03#ibcon#read 3, iclass 22, count 0 2006.285.09:50:58.03#ibcon#about to read 4, iclass 22, count 0 2006.285.09:50:58.03#ibcon#read 4, iclass 22, count 0 2006.285.09:50:58.03#ibcon#about to read 5, iclass 22, count 0 2006.285.09:50:58.03#ibcon#read 5, iclass 22, count 0 2006.285.09:50:58.03#ibcon#about to read 6, iclass 22, count 0 2006.285.09:50:58.03#ibcon#read 6, iclass 22, count 0 2006.285.09:50:58.03#ibcon#end of sib2, iclass 22, count 0 2006.285.09:50:58.03#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:50:58.03#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:50:58.03#ibcon#[27=USB\r\n] 2006.285.09:50:58.03#ibcon#*before write, iclass 22, count 0 2006.285.09:50:58.03#ibcon#enter sib2, iclass 22, count 0 2006.285.09:50:58.03#ibcon#flushed, iclass 22, count 0 2006.285.09:50:58.03#ibcon#about to write, iclass 22, count 0 2006.285.09:50:58.03#ibcon#wrote, iclass 22, count 0 2006.285.09:50:58.03#ibcon#about to read 3, iclass 22, count 0 2006.285.09:50:58.06#ibcon#read 3, iclass 22, count 0 2006.285.09:50:58.06#ibcon#about to read 4, iclass 22, count 0 2006.285.09:50:58.06#ibcon#read 4, iclass 22, count 0 2006.285.09:50:58.06#ibcon#about to read 5, iclass 22, count 0 2006.285.09:50:58.06#ibcon#read 5, iclass 22, count 0 2006.285.09:50:58.06#ibcon#about to read 6, iclass 22, count 0 2006.285.09:50:58.06#ibcon#read 6, iclass 22, count 0 2006.285.09:50:58.06#ibcon#end of sib2, iclass 22, count 0 2006.285.09:50:58.06#ibcon#*after write, iclass 22, count 0 2006.285.09:50:58.06#ibcon#*before return 0, iclass 22, count 0 2006.285.09:50:58.06#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:50:58.06#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.09:50:58.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:50:58.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:50:58.06$vck44/vabw=wide 2006.285.09:50:58.06#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.09:50:58.06#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.09:50:58.06#ibcon#ireg 8 cls_cnt 0 2006.285.09:50:58.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:50:58.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:50:58.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:50:58.06#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:50:58.06#ibcon#first serial, iclass 24, count 0 2006.285.09:50:58.06#ibcon#enter sib2, iclass 24, count 0 2006.285.09:50:58.06#ibcon#flushed, iclass 24, count 0 2006.285.09:50:58.06#ibcon#about to write, iclass 24, count 0 2006.285.09:50:58.06#ibcon#wrote, iclass 24, count 0 2006.285.09:50:58.06#ibcon#about to read 3, iclass 24, count 0 2006.285.09:50:58.08#ibcon#read 3, iclass 24, count 0 2006.285.09:50:58.08#ibcon#about to read 4, iclass 24, count 0 2006.285.09:50:58.08#ibcon#read 4, iclass 24, count 0 2006.285.09:50:58.08#ibcon#about to read 5, iclass 24, count 0 2006.285.09:50:58.08#ibcon#read 5, iclass 24, count 0 2006.285.09:50:58.08#ibcon#about to read 6, iclass 24, count 0 2006.285.09:50:58.08#ibcon#read 6, iclass 24, count 0 2006.285.09:50:58.08#ibcon#end of sib2, iclass 24, count 0 2006.285.09:50:58.08#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:50:58.08#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:50:58.08#ibcon#[25=BW32\r\n] 2006.285.09:50:58.08#ibcon#*before write, iclass 24, count 0 2006.285.09:50:58.08#ibcon#enter sib2, iclass 24, count 0 2006.285.09:50:58.08#ibcon#flushed, iclass 24, count 0 2006.285.09:50:58.08#ibcon#about to write, iclass 24, count 0 2006.285.09:50:58.08#ibcon#wrote, iclass 24, count 0 2006.285.09:50:58.08#ibcon#about to read 3, iclass 24, count 0 2006.285.09:50:58.11#ibcon#read 3, iclass 24, count 0 2006.285.09:50:58.11#ibcon#about to read 4, iclass 24, count 0 2006.285.09:50:58.11#ibcon#read 4, iclass 24, count 0 2006.285.09:50:58.11#ibcon#about to read 5, iclass 24, count 0 2006.285.09:50:58.11#ibcon#read 5, iclass 24, count 0 2006.285.09:50:58.11#ibcon#about to read 6, iclass 24, count 0 2006.285.09:50:58.11#ibcon#read 6, iclass 24, count 0 2006.285.09:50:58.11#ibcon#end of sib2, iclass 24, count 0 2006.285.09:50:58.11#ibcon#*after write, iclass 24, count 0 2006.285.09:50:58.11#ibcon#*before return 0, iclass 24, count 0 2006.285.09:50:58.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:50:58.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.09:50:58.11#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:50:58.11#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:50:58.11$vck44/vbbw=wide 2006.285.09:50:58.11#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.09:50:58.11#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.09:50:58.11#ibcon#ireg 8 cls_cnt 0 2006.285.09:50:58.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:50:58.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:50:58.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:50:58.18#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:50:58.18#ibcon#first serial, iclass 26, count 0 2006.285.09:50:58.18#ibcon#enter sib2, iclass 26, count 0 2006.285.09:50:58.18#ibcon#flushed, iclass 26, count 0 2006.285.09:50:58.18#ibcon#about to write, iclass 26, count 0 2006.285.09:50:58.18#ibcon#wrote, iclass 26, count 0 2006.285.09:50:58.18#ibcon#about to read 3, iclass 26, count 0 2006.285.09:50:58.20#ibcon#read 3, iclass 26, count 0 2006.285.09:50:58.20#ibcon#about to read 4, iclass 26, count 0 2006.285.09:50:58.20#ibcon#read 4, iclass 26, count 0 2006.285.09:50:58.20#ibcon#about to read 5, iclass 26, count 0 2006.285.09:50:58.20#ibcon#read 5, iclass 26, count 0 2006.285.09:50:58.20#ibcon#about to read 6, iclass 26, count 0 2006.285.09:50:58.20#ibcon#read 6, iclass 26, count 0 2006.285.09:50:58.20#ibcon#end of sib2, iclass 26, count 0 2006.285.09:50:58.20#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:50:58.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:50:58.20#ibcon#[27=BW32\r\n] 2006.285.09:50:58.20#ibcon#*before write, iclass 26, count 0 2006.285.09:50:58.20#ibcon#enter sib2, iclass 26, count 0 2006.285.09:50:58.20#ibcon#flushed, iclass 26, count 0 2006.285.09:50:58.20#ibcon#about to write, iclass 26, count 0 2006.285.09:50:58.20#ibcon#wrote, iclass 26, count 0 2006.285.09:50:58.20#ibcon#about to read 3, iclass 26, count 0 2006.285.09:50:58.23#ibcon#read 3, iclass 26, count 0 2006.285.09:50:58.23#ibcon#about to read 4, iclass 26, count 0 2006.285.09:50:58.23#ibcon#read 4, iclass 26, count 0 2006.285.09:50:58.23#ibcon#about to read 5, iclass 26, count 0 2006.285.09:50:58.23#ibcon#read 5, iclass 26, count 0 2006.285.09:50:58.23#ibcon#about to read 6, iclass 26, count 0 2006.285.09:50:58.23#ibcon#read 6, iclass 26, count 0 2006.285.09:50:58.23#ibcon#end of sib2, iclass 26, count 0 2006.285.09:50:58.23#ibcon#*after write, iclass 26, count 0 2006.285.09:50:58.23#ibcon#*before return 0, iclass 26, count 0 2006.285.09:50:58.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:50:58.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:50:58.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:50:58.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:50:58.23$setupk4/ifdk4 2006.285.09:50:58.23$ifdk4/lo= 2006.285.09:50:58.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:50:58.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:50:58.23$ifdk4/patch= 2006.285.09:50:58.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:50:58.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:50:58.23$setupk4/!*+20s 2006.285.09:51:03.28#abcon#<5=/05 0.9 1.4 19.38 951015.2\r\n> 2006.285.09:51:03.30#abcon#{5=INTERFACE CLEAR} 2006.285.09:51:03.36#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:51:12.74$setupk4/"tpicd 2006.285.09:51:12.74$setupk4/echo=off 2006.285.09:51:12.74$setupk4/xlog=off 2006.285.09:51:12.74:!2006.285.09:52:07 2006.285.09:51:20.14#trakl#Source acquired 2006.285.09:51:20.14#flagr#flagr/antenna,acquired 2006.285.09:52:07.00:preob 2006.285.09:52:07.14/onsource/TRACKING 2006.285.09:52:07.14:!2006.285.09:52:17 2006.285.09:52:17.00:"tape 2006.285.09:52:17.00:"st=record 2006.285.09:52:17.00:data_valid=on 2006.285.09:52:17.00:midob 2006.285.09:52:17.14/onsource/TRACKING 2006.285.09:52:17.14/wx/19.38,1015.2,95 2006.285.09:52:17.23/cable/+6.4825E-03 2006.285.09:52:18.32/va/01,07,usb,yes,31,34 2006.285.09:52:18.32/va/02,06,usb,yes,31,32 2006.285.09:52:18.32/va/03,07,usb,yes,31,33 2006.285.09:52:18.32/va/04,06,usb,yes,32,34 2006.285.09:52:18.32/va/05,03,usb,yes,32,32 2006.285.09:52:18.32/va/06,04,usb,yes,29,28 2006.285.09:52:18.32/va/07,04,usb,yes,29,30 2006.285.09:52:18.32/va/08,03,usb,yes,30,36 2006.285.09:52:18.55/valo/01,524.99,yes,locked 2006.285.09:52:18.55/valo/02,534.99,yes,locked 2006.285.09:52:18.55/valo/03,564.99,yes,locked 2006.285.09:52:18.55/valo/04,624.99,yes,locked 2006.285.09:52:18.55/valo/05,734.99,yes,locked 2006.285.09:52:18.55/valo/06,814.99,yes,locked 2006.285.09:52:18.55/valo/07,864.99,yes,locked 2006.285.09:52:18.55/valo/08,884.99,yes,locked 2006.285.09:52:19.64/vb/01,04,usb,yes,30,28 2006.285.09:52:19.64/vb/02,05,usb,yes,28,28 2006.285.09:52:19.64/vb/03,04,usb,yes,29,32 2006.285.09:52:19.64/vb/04,05,usb,yes,30,28 2006.285.09:52:19.64/vb/05,04,usb,yes,26,28 2006.285.09:52:19.64/vb/06,03,usb,yes,37,33 2006.285.09:52:19.64/vb/07,04,usb,yes,30,30 2006.285.09:52:19.64/vb/08,04,usb,yes,27,31 2006.285.09:52:19.87/vblo/01,629.99,yes,locked 2006.285.09:52:19.87/vblo/02,634.99,yes,locked 2006.285.09:52:19.87/vblo/03,649.99,yes,locked 2006.285.09:52:19.87/vblo/04,679.99,yes,locked 2006.285.09:52:19.87/vblo/05,709.99,yes,locked 2006.285.09:52:19.87/vblo/06,719.99,yes,locked 2006.285.09:52:19.87/vblo/07,734.99,yes,locked 2006.285.09:52:19.87/vblo/08,744.99,yes,locked 2006.285.09:52:20.02/vabw/8 2006.285.09:52:20.17/vbbw/8 2006.285.09:52:20.27/xfe/off,on,12.2 2006.285.09:52:20.64/ifatt/23,28,28,28 2006.285.09:52:21.08/fmout-gps/S +2.48E-07 2006.285.09:52:21.10:!2006.285.09:53:27 2006.285.09:53:27.01:data_valid=off 2006.285.09:53:27.01:"et 2006.285.09:53:27.01:!+3s 2006.285.09:53:30.02:"tape 2006.285.09:53:30.02:postob 2006.285.09:53:30.08/cable/+6.4830E-03 2006.285.09:53:30.08/wx/19.37,1015.1,95 2006.285.09:53:31.08/fmout-gps/S +2.46E-07 2006.285.09:53:31.08:scan_name=285-0955,jd0610,110 2006.285.09:53:31.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.285.09:53:32.14#flagr#flagr/antenna,new-source 2006.285.09:53:32.14:checkk5 2006.285.09:53:32.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:53:32.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:53:33.62/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:53:34.05/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:53:34.41/chk_obsdata//k5ts1/T2850952??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.09:53:34.78/chk_obsdata//k5ts2/T2850952??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.09:53:35.20/chk_obsdata//k5ts3/T2850952??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.09:53:35.59/chk_obsdata//k5ts4/T2850952??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.09:53:36.77/k5log//k5ts1_log_newline 2006.285.09:53:37.86/k5log//k5ts2_log_newline 2006.285.09:53:38.63/k5log//k5ts3_log_newline 2006.285.09:53:39.40/k5log//k5ts4_log_newline 2006.285.09:53:39.42/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:53:39.42:setupk4=1 2006.285.09:53:39.42$setupk4/echo=on 2006.285.09:53:39.42$setupk4/pcalon 2006.285.09:53:39.42$pcalon/"no phase cal control is implemented here 2006.285.09:53:39.42$setupk4/"tpicd=stop 2006.285.09:53:39.42$setupk4/"rec=synch_on 2006.285.09:53:39.42$setupk4/"rec_mode=128 2006.285.09:53:39.42$setupk4/!* 2006.285.09:53:39.42$setupk4/recpk4 2006.285.09:53:39.42$recpk4/recpatch= 2006.285.09:53:39.42$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:53:39.42$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:53:39.42$setupk4/vck44 2006.285.09:53:39.42$vck44/valo=1,524.99 2006.285.09:53:39.42#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.09:53:39.42#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.09:53:39.42#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:39.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:53:39.42#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:53:39.42#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:53:39.42#ibcon#enter wrdev, iclass 23, count 0 2006.285.09:53:39.42#ibcon#first serial, iclass 23, count 0 2006.285.09:53:39.42#ibcon#enter sib2, iclass 23, count 0 2006.285.09:53:39.42#ibcon#flushed, iclass 23, count 0 2006.285.09:53:39.42#ibcon#about to write, iclass 23, count 0 2006.285.09:53:39.42#ibcon#wrote, iclass 23, count 0 2006.285.09:53:39.42#ibcon#about to read 3, iclass 23, count 0 2006.285.09:53:39.44#ibcon#read 3, iclass 23, count 0 2006.285.09:53:39.44#ibcon#about to read 4, iclass 23, count 0 2006.285.09:53:39.44#ibcon#read 4, iclass 23, count 0 2006.285.09:53:39.44#ibcon#about to read 5, iclass 23, count 0 2006.285.09:53:39.44#ibcon#read 5, iclass 23, count 0 2006.285.09:53:39.44#ibcon#about to read 6, iclass 23, count 0 2006.285.09:53:39.44#ibcon#read 6, iclass 23, count 0 2006.285.09:53:39.44#ibcon#end of sib2, iclass 23, count 0 2006.285.09:53:39.44#ibcon#*mode == 0, iclass 23, count 0 2006.285.09:53:39.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.09:53:39.44#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:53:39.44#ibcon#*before write, iclass 23, count 0 2006.285.09:53:39.44#ibcon#enter sib2, iclass 23, count 0 2006.285.09:53:39.44#ibcon#flushed, iclass 23, count 0 2006.285.09:53:39.44#ibcon#about to write, iclass 23, count 0 2006.285.09:53:39.44#ibcon#wrote, iclass 23, count 0 2006.285.09:53:39.44#ibcon#about to read 3, iclass 23, count 0 2006.285.09:53:39.49#ibcon#read 3, iclass 23, count 0 2006.285.09:53:39.49#ibcon#about to read 4, iclass 23, count 0 2006.285.09:53:39.49#ibcon#read 4, iclass 23, count 0 2006.285.09:53:39.49#ibcon#about to read 5, iclass 23, count 0 2006.285.09:53:39.49#ibcon#read 5, iclass 23, count 0 2006.285.09:53:39.49#ibcon#about to read 6, iclass 23, count 0 2006.285.09:53:39.49#ibcon#read 6, iclass 23, count 0 2006.285.09:53:39.49#ibcon#end of sib2, iclass 23, count 0 2006.285.09:53:39.49#ibcon#*after write, iclass 23, count 0 2006.285.09:53:39.49#ibcon#*before return 0, iclass 23, count 0 2006.285.09:53:39.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:53:39.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:53:39.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.09:53:39.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.09:53:39.49$vck44/va=1,7 2006.285.09:53:39.49#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.09:53:39.49#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.09:53:39.49#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:39.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:53:39.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:53:39.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:53:39.49#ibcon#enter wrdev, iclass 25, count 2 2006.285.09:53:39.49#ibcon#first serial, iclass 25, count 2 2006.285.09:53:39.49#ibcon#enter sib2, iclass 25, count 2 2006.285.09:53:39.49#ibcon#flushed, iclass 25, count 2 2006.285.09:53:39.49#ibcon#about to write, iclass 25, count 2 2006.285.09:53:39.49#ibcon#wrote, iclass 25, count 2 2006.285.09:53:39.49#ibcon#about to read 3, iclass 25, count 2 2006.285.09:53:39.51#ibcon#read 3, iclass 25, count 2 2006.285.09:53:39.51#ibcon#about to read 4, iclass 25, count 2 2006.285.09:53:39.51#ibcon#read 4, iclass 25, count 2 2006.285.09:53:39.51#ibcon#about to read 5, iclass 25, count 2 2006.285.09:53:39.51#ibcon#read 5, iclass 25, count 2 2006.285.09:53:39.51#ibcon#about to read 6, iclass 25, count 2 2006.285.09:53:39.51#ibcon#read 6, iclass 25, count 2 2006.285.09:53:39.51#ibcon#end of sib2, iclass 25, count 2 2006.285.09:53:39.51#ibcon#*mode == 0, iclass 25, count 2 2006.285.09:53:39.51#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.09:53:39.51#ibcon#[25=AT01-07\r\n] 2006.285.09:53:39.51#ibcon#*before write, iclass 25, count 2 2006.285.09:53:39.51#ibcon#enter sib2, iclass 25, count 2 2006.285.09:53:39.51#ibcon#flushed, iclass 25, count 2 2006.285.09:53:39.51#ibcon#about to write, iclass 25, count 2 2006.285.09:53:39.51#ibcon#wrote, iclass 25, count 2 2006.285.09:53:39.51#ibcon#about to read 3, iclass 25, count 2 2006.285.09:53:39.54#ibcon#read 3, iclass 25, count 2 2006.285.09:53:39.54#ibcon#about to read 4, iclass 25, count 2 2006.285.09:53:39.54#ibcon#read 4, iclass 25, count 2 2006.285.09:53:39.54#ibcon#about to read 5, iclass 25, count 2 2006.285.09:53:39.54#ibcon#read 5, iclass 25, count 2 2006.285.09:53:39.54#ibcon#about to read 6, iclass 25, count 2 2006.285.09:53:39.54#ibcon#read 6, iclass 25, count 2 2006.285.09:53:39.54#ibcon#end of sib2, iclass 25, count 2 2006.285.09:53:39.54#ibcon#*after write, iclass 25, count 2 2006.285.09:53:39.54#ibcon#*before return 0, iclass 25, count 2 2006.285.09:53:39.54#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:53:39.54#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:53:39.54#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.09:53:39.54#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:39.54#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:53:39.66#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:53:39.66#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:53:39.66#ibcon#enter wrdev, iclass 25, count 0 2006.285.09:53:39.66#ibcon#first serial, iclass 25, count 0 2006.285.09:53:39.66#ibcon#enter sib2, iclass 25, count 0 2006.285.09:53:39.66#ibcon#flushed, iclass 25, count 0 2006.285.09:53:39.66#ibcon#about to write, iclass 25, count 0 2006.285.09:53:39.66#ibcon#wrote, iclass 25, count 0 2006.285.09:53:39.66#ibcon#about to read 3, iclass 25, count 0 2006.285.09:53:39.68#ibcon#read 3, iclass 25, count 0 2006.285.09:53:39.68#ibcon#about to read 4, iclass 25, count 0 2006.285.09:53:39.68#ibcon#read 4, iclass 25, count 0 2006.285.09:53:39.68#ibcon#about to read 5, iclass 25, count 0 2006.285.09:53:39.68#ibcon#read 5, iclass 25, count 0 2006.285.09:53:39.68#ibcon#about to read 6, iclass 25, count 0 2006.285.09:53:39.68#ibcon#read 6, iclass 25, count 0 2006.285.09:53:39.68#ibcon#end of sib2, iclass 25, count 0 2006.285.09:53:39.68#ibcon#*mode == 0, iclass 25, count 0 2006.285.09:53:39.68#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.09:53:39.68#ibcon#[25=USB\r\n] 2006.285.09:53:39.68#ibcon#*before write, iclass 25, count 0 2006.285.09:53:39.68#ibcon#enter sib2, iclass 25, count 0 2006.285.09:53:39.68#ibcon#flushed, iclass 25, count 0 2006.285.09:53:39.68#ibcon#about to write, iclass 25, count 0 2006.285.09:53:39.68#ibcon#wrote, iclass 25, count 0 2006.285.09:53:39.68#ibcon#about to read 3, iclass 25, count 0 2006.285.09:53:39.71#ibcon#read 3, iclass 25, count 0 2006.285.09:53:39.71#ibcon#about to read 4, iclass 25, count 0 2006.285.09:53:39.71#ibcon#read 4, iclass 25, count 0 2006.285.09:53:39.71#ibcon#about to read 5, iclass 25, count 0 2006.285.09:53:39.71#ibcon#read 5, iclass 25, count 0 2006.285.09:53:39.71#ibcon#about to read 6, iclass 25, count 0 2006.285.09:53:39.71#ibcon#read 6, iclass 25, count 0 2006.285.09:53:39.71#ibcon#end of sib2, iclass 25, count 0 2006.285.09:53:39.71#ibcon#*after write, iclass 25, count 0 2006.285.09:53:39.71#ibcon#*before return 0, iclass 25, count 0 2006.285.09:53:39.71#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:53:39.71#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:53:39.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.09:53:39.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.09:53:39.71$vck44/valo=2,534.99 2006.285.09:53:39.71#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.09:53:39.71#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.09:53:39.71#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:39.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:53:39.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:53:39.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:53:39.71#ibcon#enter wrdev, iclass 27, count 0 2006.285.09:53:39.71#ibcon#first serial, iclass 27, count 0 2006.285.09:53:39.71#ibcon#enter sib2, iclass 27, count 0 2006.285.09:53:39.71#ibcon#flushed, iclass 27, count 0 2006.285.09:53:39.71#ibcon#about to write, iclass 27, count 0 2006.285.09:53:39.71#ibcon#wrote, iclass 27, count 0 2006.285.09:53:39.71#ibcon#about to read 3, iclass 27, count 0 2006.285.09:53:39.73#ibcon#read 3, iclass 27, count 0 2006.285.09:53:39.73#ibcon#about to read 4, iclass 27, count 0 2006.285.09:53:39.73#ibcon#read 4, iclass 27, count 0 2006.285.09:53:39.73#ibcon#about to read 5, iclass 27, count 0 2006.285.09:53:39.73#ibcon#read 5, iclass 27, count 0 2006.285.09:53:39.73#ibcon#about to read 6, iclass 27, count 0 2006.285.09:53:39.73#ibcon#read 6, iclass 27, count 0 2006.285.09:53:39.73#ibcon#end of sib2, iclass 27, count 0 2006.285.09:53:39.73#ibcon#*mode == 0, iclass 27, count 0 2006.285.09:53:39.73#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.09:53:39.73#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:53:39.73#ibcon#*before write, iclass 27, count 0 2006.285.09:53:39.73#ibcon#enter sib2, iclass 27, count 0 2006.285.09:53:39.73#ibcon#flushed, iclass 27, count 0 2006.285.09:53:39.73#ibcon#about to write, iclass 27, count 0 2006.285.09:53:39.73#ibcon#wrote, iclass 27, count 0 2006.285.09:53:39.73#ibcon#about to read 3, iclass 27, count 0 2006.285.09:53:39.77#ibcon#read 3, iclass 27, count 0 2006.285.09:53:39.77#ibcon#about to read 4, iclass 27, count 0 2006.285.09:53:39.77#ibcon#read 4, iclass 27, count 0 2006.285.09:53:39.77#ibcon#about to read 5, iclass 27, count 0 2006.285.09:53:39.77#ibcon#read 5, iclass 27, count 0 2006.285.09:53:39.77#ibcon#about to read 6, iclass 27, count 0 2006.285.09:53:39.77#ibcon#read 6, iclass 27, count 0 2006.285.09:53:39.77#ibcon#end of sib2, iclass 27, count 0 2006.285.09:53:39.77#ibcon#*after write, iclass 27, count 0 2006.285.09:53:39.77#ibcon#*before return 0, iclass 27, count 0 2006.285.09:53:39.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:53:39.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:53:39.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.09:53:39.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.09:53:39.77$vck44/va=2,6 2006.285.09:53:39.77#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.09:53:39.77#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.09:53:39.77#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:39.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:53:39.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:53:39.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:53:39.83#ibcon#enter wrdev, iclass 29, count 2 2006.285.09:53:39.83#ibcon#first serial, iclass 29, count 2 2006.285.09:53:39.83#ibcon#enter sib2, iclass 29, count 2 2006.285.09:53:39.83#ibcon#flushed, iclass 29, count 2 2006.285.09:53:39.83#ibcon#about to write, iclass 29, count 2 2006.285.09:53:39.83#ibcon#wrote, iclass 29, count 2 2006.285.09:53:39.83#ibcon#about to read 3, iclass 29, count 2 2006.285.09:53:39.85#ibcon#read 3, iclass 29, count 2 2006.285.09:53:39.85#ibcon#about to read 4, iclass 29, count 2 2006.285.09:53:39.85#ibcon#read 4, iclass 29, count 2 2006.285.09:53:39.85#ibcon#about to read 5, iclass 29, count 2 2006.285.09:53:39.85#ibcon#read 5, iclass 29, count 2 2006.285.09:53:39.85#ibcon#about to read 6, iclass 29, count 2 2006.285.09:53:39.85#ibcon#read 6, iclass 29, count 2 2006.285.09:53:39.85#ibcon#end of sib2, iclass 29, count 2 2006.285.09:53:39.85#ibcon#*mode == 0, iclass 29, count 2 2006.285.09:53:39.85#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.09:53:39.85#ibcon#[25=AT02-06\r\n] 2006.285.09:53:39.85#ibcon#*before write, iclass 29, count 2 2006.285.09:53:39.85#ibcon#enter sib2, iclass 29, count 2 2006.285.09:53:39.85#ibcon#flushed, iclass 29, count 2 2006.285.09:53:39.85#ibcon#about to write, iclass 29, count 2 2006.285.09:53:39.85#ibcon#wrote, iclass 29, count 2 2006.285.09:53:39.85#ibcon#about to read 3, iclass 29, count 2 2006.285.09:53:39.88#ibcon#read 3, iclass 29, count 2 2006.285.09:53:39.88#ibcon#about to read 4, iclass 29, count 2 2006.285.09:53:39.88#ibcon#read 4, iclass 29, count 2 2006.285.09:53:39.88#ibcon#about to read 5, iclass 29, count 2 2006.285.09:53:39.88#ibcon#read 5, iclass 29, count 2 2006.285.09:53:39.88#ibcon#about to read 6, iclass 29, count 2 2006.285.09:53:39.88#ibcon#read 6, iclass 29, count 2 2006.285.09:53:39.88#ibcon#end of sib2, iclass 29, count 2 2006.285.09:53:39.88#ibcon#*after write, iclass 29, count 2 2006.285.09:53:39.88#ibcon#*before return 0, iclass 29, count 2 2006.285.09:53:39.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:53:39.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:53:39.88#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.09:53:39.88#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:39.88#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:53:40.00#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:53:40.00#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:53:40.00#ibcon#enter wrdev, iclass 29, count 0 2006.285.09:53:40.00#ibcon#first serial, iclass 29, count 0 2006.285.09:53:40.00#ibcon#enter sib2, iclass 29, count 0 2006.285.09:53:40.00#ibcon#flushed, iclass 29, count 0 2006.285.09:53:40.00#ibcon#about to write, iclass 29, count 0 2006.285.09:53:40.00#ibcon#wrote, iclass 29, count 0 2006.285.09:53:40.00#ibcon#about to read 3, iclass 29, count 0 2006.285.09:53:40.02#ibcon#read 3, iclass 29, count 0 2006.285.09:53:40.02#ibcon#about to read 4, iclass 29, count 0 2006.285.09:53:40.02#ibcon#read 4, iclass 29, count 0 2006.285.09:53:40.02#ibcon#about to read 5, iclass 29, count 0 2006.285.09:53:40.02#ibcon#read 5, iclass 29, count 0 2006.285.09:53:40.02#ibcon#about to read 6, iclass 29, count 0 2006.285.09:53:40.02#ibcon#read 6, iclass 29, count 0 2006.285.09:53:40.02#ibcon#end of sib2, iclass 29, count 0 2006.285.09:53:40.02#ibcon#*mode == 0, iclass 29, count 0 2006.285.09:53:40.02#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.09:53:40.02#ibcon#[25=USB\r\n] 2006.285.09:53:40.02#ibcon#*before write, iclass 29, count 0 2006.285.09:53:40.02#ibcon#enter sib2, iclass 29, count 0 2006.285.09:53:40.02#ibcon#flushed, iclass 29, count 0 2006.285.09:53:40.02#ibcon#about to write, iclass 29, count 0 2006.285.09:53:40.02#ibcon#wrote, iclass 29, count 0 2006.285.09:53:40.02#ibcon#about to read 3, iclass 29, count 0 2006.285.09:53:40.05#ibcon#read 3, iclass 29, count 0 2006.285.09:53:40.05#ibcon#about to read 4, iclass 29, count 0 2006.285.09:53:40.05#ibcon#read 4, iclass 29, count 0 2006.285.09:53:40.05#ibcon#about to read 5, iclass 29, count 0 2006.285.09:53:40.05#ibcon#read 5, iclass 29, count 0 2006.285.09:53:40.05#ibcon#about to read 6, iclass 29, count 0 2006.285.09:53:40.05#ibcon#read 6, iclass 29, count 0 2006.285.09:53:40.05#ibcon#end of sib2, iclass 29, count 0 2006.285.09:53:40.05#ibcon#*after write, iclass 29, count 0 2006.285.09:53:40.05#ibcon#*before return 0, iclass 29, count 0 2006.285.09:53:40.05#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:53:40.05#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:53:40.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.09:53:40.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.09:53:40.05$vck44/valo=3,564.99 2006.285.09:53:40.05#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.09:53:40.05#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.09:53:40.05#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:40.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:53:40.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:53:40.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:53:40.05#ibcon#enter wrdev, iclass 31, count 0 2006.285.09:53:40.05#ibcon#first serial, iclass 31, count 0 2006.285.09:53:40.05#ibcon#enter sib2, iclass 31, count 0 2006.285.09:53:40.05#ibcon#flushed, iclass 31, count 0 2006.285.09:53:40.05#ibcon#about to write, iclass 31, count 0 2006.285.09:53:40.05#ibcon#wrote, iclass 31, count 0 2006.285.09:53:40.05#ibcon#about to read 3, iclass 31, count 0 2006.285.09:53:40.07#ibcon#read 3, iclass 31, count 0 2006.285.09:53:40.07#ibcon#about to read 4, iclass 31, count 0 2006.285.09:53:40.07#ibcon#read 4, iclass 31, count 0 2006.285.09:53:40.07#ibcon#about to read 5, iclass 31, count 0 2006.285.09:53:40.07#ibcon#read 5, iclass 31, count 0 2006.285.09:53:40.07#ibcon#about to read 6, iclass 31, count 0 2006.285.09:53:40.07#ibcon#read 6, iclass 31, count 0 2006.285.09:53:40.07#ibcon#end of sib2, iclass 31, count 0 2006.285.09:53:40.07#ibcon#*mode == 0, iclass 31, count 0 2006.285.09:53:40.07#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.09:53:40.07#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:53:40.07#ibcon#*before write, iclass 31, count 0 2006.285.09:53:40.07#ibcon#enter sib2, iclass 31, count 0 2006.285.09:53:40.07#ibcon#flushed, iclass 31, count 0 2006.285.09:53:40.07#ibcon#about to write, iclass 31, count 0 2006.285.09:53:40.07#ibcon#wrote, iclass 31, count 0 2006.285.09:53:40.07#ibcon#about to read 3, iclass 31, count 0 2006.285.09:53:40.11#ibcon#read 3, iclass 31, count 0 2006.285.09:53:40.11#ibcon#about to read 4, iclass 31, count 0 2006.285.09:53:40.11#ibcon#read 4, iclass 31, count 0 2006.285.09:53:40.11#ibcon#about to read 5, iclass 31, count 0 2006.285.09:53:40.11#ibcon#read 5, iclass 31, count 0 2006.285.09:53:40.11#ibcon#about to read 6, iclass 31, count 0 2006.285.09:53:40.11#ibcon#read 6, iclass 31, count 0 2006.285.09:53:40.11#ibcon#end of sib2, iclass 31, count 0 2006.285.09:53:40.11#ibcon#*after write, iclass 31, count 0 2006.285.09:53:40.11#ibcon#*before return 0, iclass 31, count 0 2006.285.09:53:40.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:53:40.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:53:40.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.09:53:40.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.09:53:40.11$vck44/va=3,7 2006.285.09:53:40.11#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.09:53:40.11#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.09:53:40.11#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:40.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:53:40.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:53:40.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:53:40.17#ibcon#enter wrdev, iclass 33, count 2 2006.285.09:53:40.17#ibcon#first serial, iclass 33, count 2 2006.285.09:53:40.17#ibcon#enter sib2, iclass 33, count 2 2006.285.09:53:40.17#ibcon#flushed, iclass 33, count 2 2006.285.09:53:40.17#ibcon#about to write, iclass 33, count 2 2006.285.09:53:40.17#ibcon#wrote, iclass 33, count 2 2006.285.09:53:40.17#ibcon#about to read 3, iclass 33, count 2 2006.285.09:53:40.19#ibcon#read 3, iclass 33, count 2 2006.285.09:53:40.19#ibcon#about to read 4, iclass 33, count 2 2006.285.09:53:40.19#ibcon#read 4, iclass 33, count 2 2006.285.09:53:40.19#ibcon#about to read 5, iclass 33, count 2 2006.285.09:53:40.19#ibcon#read 5, iclass 33, count 2 2006.285.09:53:40.19#ibcon#about to read 6, iclass 33, count 2 2006.285.09:53:40.19#ibcon#read 6, iclass 33, count 2 2006.285.09:53:40.19#ibcon#end of sib2, iclass 33, count 2 2006.285.09:53:40.19#ibcon#*mode == 0, iclass 33, count 2 2006.285.09:53:40.19#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.09:53:40.19#ibcon#[25=AT03-07\r\n] 2006.285.09:53:40.19#ibcon#*before write, iclass 33, count 2 2006.285.09:53:40.19#ibcon#enter sib2, iclass 33, count 2 2006.285.09:53:40.19#ibcon#flushed, iclass 33, count 2 2006.285.09:53:40.19#ibcon#about to write, iclass 33, count 2 2006.285.09:53:40.19#ibcon#wrote, iclass 33, count 2 2006.285.09:53:40.19#ibcon#about to read 3, iclass 33, count 2 2006.285.09:53:40.22#ibcon#read 3, iclass 33, count 2 2006.285.09:53:40.22#ibcon#about to read 4, iclass 33, count 2 2006.285.09:53:40.22#ibcon#read 4, iclass 33, count 2 2006.285.09:53:40.22#ibcon#about to read 5, iclass 33, count 2 2006.285.09:53:40.22#ibcon#read 5, iclass 33, count 2 2006.285.09:53:40.22#ibcon#about to read 6, iclass 33, count 2 2006.285.09:53:40.22#ibcon#read 6, iclass 33, count 2 2006.285.09:53:40.22#ibcon#end of sib2, iclass 33, count 2 2006.285.09:53:40.22#ibcon#*after write, iclass 33, count 2 2006.285.09:53:40.22#ibcon#*before return 0, iclass 33, count 2 2006.285.09:53:40.22#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:53:40.22#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:53:40.22#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.09:53:40.22#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:40.22#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:53:40.34#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:53:40.34#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:53:40.34#ibcon#enter wrdev, iclass 33, count 0 2006.285.09:53:40.34#ibcon#first serial, iclass 33, count 0 2006.285.09:53:40.34#ibcon#enter sib2, iclass 33, count 0 2006.285.09:53:40.34#ibcon#flushed, iclass 33, count 0 2006.285.09:53:40.34#ibcon#about to write, iclass 33, count 0 2006.285.09:53:40.34#ibcon#wrote, iclass 33, count 0 2006.285.09:53:40.34#ibcon#about to read 3, iclass 33, count 0 2006.285.09:53:40.36#ibcon#read 3, iclass 33, count 0 2006.285.09:53:40.36#ibcon#about to read 4, iclass 33, count 0 2006.285.09:53:40.36#ibcon#read 4, iclass 33, count 0 2006.285.09:53:40.36#ibcon#about to read 5, iclass 33, count 0 2006.285.09:53:40.36#ibcon#read 5, iclass 33, count 0 2006.285.09:53:40.36#ibcon#about to read 6, iclass 33, count 0 2006.285.09:53:40.36#ibcon#read 6, iclass 33, count 0 2006.285.09:53:40.36#ibcon#end of sib2, iclass 33, count 0 2006.285.09:53:40.36#ibcon#*mode == 0, iclass 33, count 0 2006.285.09:53:40.36#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.09:53:40.36#ibcon#[25=USB\r\n] 2006.285.09:53:40.36#ibcon#*before write, iclass 33, count 0 2006.285.09:53:40.36#ibcon#enter sib2, iclass 33, count 0 2006.285.09:53:40.36#ibcon#flushed, iclass 33, count 0 2006.285.09:53:40.36#ibcon#about to write, iclass 33, count 0 2006.285.09:53:40.36#ibcon#wrote, iclass 33, count 0 2006.285.09:53:40.36#ibcon#about to read 3, iclass 33, count 0 2006.285.09:53:40.39#ibcon#read 3, iclass 33, count 0 2006.285.09:53:40.39#ibcon#about to read 4, iclass 33, count 0 2006.285.09:53:40.39#ibcon#read 4, iclass 33, count 0 2006.285.09:53:40.39#ibcon#about to read 5, iclass 33, count 0 2006.285.09:53:40.39#ibcon#read 5, iclass 33, count 0 2006.285.09:53:40.39#ibcon#about to read 6, iclass 33, count 0 2006.285.09:53:40.39#ibcon#read 6, iclass 33, count 0 2006.285.09:53:40.39#ibcon#end of sib2, iclass 33, count 0 2006.285.09:53:40.39#ibcon#*after write, iclass 33, count 0 2006.285.09:53:40.39#ibcon#*before return 0, iclass 33, count 0 2006.285.09:53:40.39#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:53:40.39#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:53:40.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.09:53:40.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.09:53:40.39$vck44/valo=4,624.99 2006.285.09:53:40.39#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.09:53:40.39#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.09:53:40.39#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:40.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:53:40.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:53:40.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:53:40.39#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:53:40.39#ibcon#first serial, iclass 35, count 0 2006.285.09:53:40.39#ibcon#enter sib2, iclass 35, count 0 2006.285.09:53:40.39#ibcon#flushed, iclass 35, count 0 2006.285.09:53:40.39#ibcon#about to write, iclass 35, count 0 2006.285.09:53:40.39#ibcon#wrote, iclass 35, count 0 2006.285.09:53:40.39#ibcon#about to read 3, iclass 35, count 0 2006.285.09:53:40.41#ibcon#read 3, iclass 35, count 0 2006.285.09:53:40.41#ibcon#about to read 4, iclass 35, count 0 2006.285.09:53:40.41#ibcon#read 4, iclass 35, count 0 2006.285.09:53:40.41#ibcon#about to read 5, iclass 35, count 0 2006.285.09:53:40.41#ibcon#read 5, iclass 35, count 0 2006.285.09:53:40.41#ibcon#about to read 6, iclass 35, count 0 2006.285.09:53:40.41#ibcon#read 6, iclass 35, count 0 2006.285.09:53:40.41#ibcon#end of sib2, iclass 35, count 0 2006.285.09:53:40.41#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:53:40.41#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:53:40.41#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:53:40.41#ibcon#*before write, iclass 35, count 0 2006.285.09:53:40.41#ibcon#enter sib2, iclass 35, count 0 2006.285.09:53:40.41#ibcon#flushed, iclass 35, count 0 2006.285.09:53:40.41#ibcon#about to write, iclass 35, count 0 2006.285.09:53:40.41#ibcon#wrote, iclass 35, count 0 2006.285.09:53:40.41#ibcon#about to read 3, iclass 35, count 0 2006.285.09:53:40.45#ibcon#read 3, iclass 35, count 0 2006.285.09:53:40.45#ibcon#about to read 4, iclass 35, count 0 2006.285.09:53:40.45#ibcon#read 4, iclass 35, count 0 2006.285.09:53:40.45#ibcon#about to read 5, iclass 35, count 0 2006.285.09:53:40.45#ibcon#read 5, iclass 35, count 0 2006.285.09:53:40.45#ibcon#about to read 6, iclass 35, count 0 2006.285.09:53:40.45#ibcon#read 6, iclass 35, count 0 2006.285.09:53:40.45#ibcon#end of sib2, iclass 35, count 0 2006.285.09:53:40.45#ibcon#*after write, iclass 35, count 0 2006.285.09:53:40.45#ibcon#*before return 0, iclass 35, count 0 2006.285.09:53:40.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:53:40.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:53:40.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:53:40.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:53:40.45$vck44/va=4,6 2006.285.09:53:40.45#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.09:53:40.45#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.09:53:40.45#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:40.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:53:40.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:53:40.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:53:40.51#ibcon#enter wrdev, iclass 37, count 2 2006.285.09:53:40.51#ibcon#first serial, iclass 37, count 2 2006.285.09:53:40.51#ibcon#enter sib2, iclass 37, count 2 2006.285.09:53:40.51#ibcon#flushed, iclass 37, count 2 2006.285.09:53:40.51#ibcon#about to write, iclass 37, count 2 2006.285.09:53:40.51#ibcon#wrote, iclass 37, count 2 2006.285.09:53:40.51#ibcon#about to read 3, iclass 37, count 2 2006.285.09:53:40.53#ibcon#read 3, iclass 37, count 2 2006.285.09:53:40.53#ibcon#about to read 4, iclass 37, count 2 2006.285.09:53:40.53#ibcon#read 4, iclass 37, count 2 2006.285.09:53:40.53#ibcon#about to read 5, iclass 37, count 2 2006.285.09:53:40.53#ibcon#read 5, iclass 37, count 2 2006.285.09:53:40.53#ibcon#about to read 6, iclass 37, count 2 2006.285.09:53:40.53#ibcon#read 6, iclass 37, count 2 2006.285.09:53:40.53#ibcon#end of sib2, iclass 37, count 2 2006.285.09:53:40.53#ibcon#*mode == 0, iclass 37, count 2 2006.285.09:53:40.53#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.09:53:40.53#ibcon#[25=AT04-06\r\n] 2006.285.09:53:40.53#ibcon#*before write, iclass 37, count 2 2006.285.09:53:40.53#ibcon#enter sib2, iclass 37, count 2 2006.285.09:53:40.53#ibcon#flushed, iclass 37, count 2 2006.285.09:53:40.53#ibcon#about to write, iclass 37, count 2 2006.285.09:53:40.53#ibcon#wrote, iclass 37, count 2 2006.285.09:53:40.53#ibcon#about to read 3, iclass 37, count 2 2006.285.09:53:40.56#ibcon#read 3, iclass 37, count 2 2006.285.09:53:40.56#ibcon#about to read 4, iclass 37, count 2 2006.285.09:53:40.56#ibcon#read 4, iclass 37, count 2 2006.285.09:53:40.56#ibcon#about to read 5, iclass 37, count 2 2006.285.09:53:40.56#ibcon#read 5, iclass 37, count 2 2006.285.09:53:40.56#ibcon#about to read 6, iclass 37, count 2 2006.285.09:53:40.56#ibcon#read 6, iclass 37, count 2 2006.285.09:53:40.56#ibcon#end of sib2, iclass 37, count 2 2006.285.09:53:40.56#ibcon#*after write, iclass 37, count 2 2006.285.09:53:40.56#ibcon#*before return 0, iclass 37, count 2 2006.285.09:53:40.56#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:53:40.56#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:53:40.56#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.09:53:40.56#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:40.56#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:53:40.68#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:53:40.68#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:53:40.68#ibcon#enter wrdev, iclass 37, count 0 2006.285.09:53:40.68#ibcon#first serial, iclass 37, count 0 2006.285.09:53:40.68#ibcon#enter sib2, iclass 37, count 0 2006.285.09:53:40.68#ibcon#flushed, iclass 37, count 0 2006.285.09:53:40.68#ibcon#about to write, iclass 37, count 0 2006.285.09:53:40.68#ibcon#wrote, iclass 37, count 0 2006.285.09:53:40.68#ibcon#about to read 3, iclass 37, count 0 2006.285.09:53:40.70#ibcon#read 3, iclass 37, count 0 2006.285.09:53:40.70#ibcon#about to read 4, iclass 37, count 0 2006.285.09:53:40.70#ibcon#read 4, iclass 37, count 0 2006.285.09:53:40.70#ibcon#about to read 5, iclass 37, count 0 2006.285.09:53:40.70#ibcon#read 5, iclass 37, count 0 2006.285.09:53:40.70#ibcon#about to read 6, iclass 37, count 0 2006.285.09:53:40.70#ibcon#read 6, iclass 37, count 0 2006.285.09:53:40.70#ibcon#end of sib2, iclass 37, count 0 2006.285.09:53:40.70#ibcon#*mode == 0, iclass 37, count 0 2006.285.09:53:40.70#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.09:53:40.70#ibcon#[25=USB\r\n] 2006.285.09:53:40.70#ibcon#*before write, iclass 37, count 0 2006.285.09:53:40.70#ibcon#enter sib2, iclass 37, count 0 2006.285.09:53:40.70#ibcon#flushed, iclass 37, count 0 2006.285.09:53:40.70#ibcon#about to write, iclass 37, count 0 2006.285.09:53:40.70#ibcon#wrote, iclass 37, count 0 2006.285.09:53:40.70#ibcon#about to read 3, iclass 37, count 0 2006.285.09:53:40.73#ibcon#read 3, iclass 37, count 0 2006.285.09:53:40.73#ibcon#about to read 4, iclass 37, count 0 2006.285.09:53:40.73#ibcon#read 4, iclass 37, count 0 2006.285.09:53:40.73#ibcon#about to read 5, iclass 37, count 0 2006.285.09:53:40.73#ibcon#read 5, iclass 37, count 0 2006.285.09:53:40.73#ibcon#about to read 6, iclass 37, count 0 2006.285.09:53:40.73#ibcon#read 6, iclass 37, count 0 2006.285.09:53:40.73#ibcon#end of sib2, iclass 37, count 0 2006.285.09:53:40.73#ibcon#*after write, iclass 37, count 0 2006.285.09:53:40.73#ibcon#*before return 0, iclass 37, count 0 2006.285.09:53:40.73#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:53:40.73#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:53:40.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.09:53:40.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.09:53:40.73$vck44/valo=5,734.99 2006.285.09:53:40.73#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.09:53:40.73#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.09:53:40.73#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:40.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:53:40.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:53:40.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:53:40.73#ibcon#enter wrdev, iclass 39, count 0 2006.285.09:53:40.73#ibcon#first serial, iclass 39, count 0 2006.285.09:53:40.73#ibcon#enter sib2, iclass 39, count 0 2006.285.09:53:40.73#ibcon#flushed, iclass 39, count 0 2006.285.09:53:40.73#ibcon#about to write, iclass 39, count 0 2006.285.09:53:40.73#ibcon#wrote, iclass 39, count 0 2006.285.09:53:40.73#ibcon#about to read 3, iclass 39, count 0 2006.285.09:53:40.75#ibcon#read 3, iclass 39, count 0 2006.285.09:53:40.75#ibcon#about to read 4, iclass 39, count 0 2006.285.09:53:40.75#ibcon#read 4, iclass 39, count 0 2006.285.09:53:40.75#ibcon#about to read 5, iclass 39, count 0 2006.285.09:53:40.75#ibcon#read 5, iclass 39, count 0 2006.285.09:53:40.75#ibcon#about to read 6, iclass 39, count 0 2006.285.09:53:40.75#ibcon#read 6, iclass 39, count 0 2006.285.09:53:40.75#ibcon#end of sib2, iclass 39, count 0 2006.285.09:53:40.75#ibcon#*mode == 0, iclass 39, count 0 2006.285.09:53:40.75#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.09:53:40.75#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:53:40.75#ibcon#*before write, iclass 39, count 0 2006.285.09:53:40.75#ibcon#enter sib2, iclass 39, count 0 2006.285.09:53:40.75#ibcon#flushed, iclass 39, count 0 2006.285.09:53:40.75#ibcon#about to write, iclass 39, count 0 2006.285.09:53:40.75#ibcon#wrote, iclass 39, count 0 2006.285.09:53:40.75#ibcon#about to read 3, iclass 39, count 0 2006.285.09:53:40.79#ibcon#read 3, iclass 39, count 0 2006.285.09:53:40.79#ibcon#about to read 4, iclass 39, count 0 2006.285.09:53:40.79#ibcon#read 4, iclass 39, count 0 2006.285.09:53:40.79#ibcon#about to read 5, iclass 39, count 0 2006.285.09:53:40.79#ibcon#read 5, iclass 39, count 0 2006.285.09:53:40.79#ibcon#about to read 6, iclass 39, count 0 2006.285.09:53:40.79#ibcon#read 6, iclass 39, count 0 2006.285.09:53:40.79#ibcon#end of sib2, iclass 39, count 0 2006.285.09:53:40.79#ibcon#*after write, iclass 39, count 0 2006.285.09:53:40.79#ibcon#*before return 0, iclass 39, count 0 2006.285.09:53:40.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:53:40.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:53:40.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.09:53:40.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.09:53:40.79$vck44/va=5,3 2006.285.09:53:40.79#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.09:53:40.79#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.09:53:40.79#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:40.79#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:53:40.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:53:40.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:53:40.85#ibcon#enter wrdev, iclass 3, count 2 2006.285.09:53:40.85#ibcon#first serial, iclass 3, count 2 2006.285.09:53:40.85#ibcon#enter sib2, iclass 3, count 2 2006.285.09:53:40.85#ibcon#flushed, iclass 3, count 2 2006.285.09:53:40.85#ibcon#about to write, iclass 3, count 2 2006.285.09:53:40.85#ibcon#wrote, iclass 3, count 2 2006.285.09:53:40.85#ibcon#about to read 3, iclass 3, count 2 2006.285.09:53:40.87#ibcon#read 3, iclass 3, count 2 2006.285.09:53:40.87#ibcon#about to read 4, iclass 3, count 2 2006.285.09:53:40.87#ibcon#read 4, iclass 3, count 2 2006.285.09:53:40.87#ibcon#about to read 5, iclass 3, count 2 2006.285.09:53:40.87#ibcon#read 5, iclass 3, count 2 2006.285.09:53:40.87#ibcon#about to read 6, iclass 3, count 2 2006.285.09:53:40.87#ibcon#read 6, iclass 3, count 2 2006.285.09:53:40.87#ibcon#end of sib2, iclass 3, count 2 2006.285.09:53:40.87#ibcon#*mode == 0, iclass 3, count 2 2006.285.09:53:40.87#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.09:53:40.87#ibcon#[25=AT05-03\r\n] 2006.285.09:53:40.87#ibcon#*before write, iclass 3, count 2 2006.285.09:53:40.87#ibcon#enter sib2, iclass 3, count 2 2006.285.09:53:40.87#ibcon#flushed, iclass 3, count 2 2006.285.09:53:40.87#ibcon#about to write, iclass 3, count 2 2006.285.09:53:40.87#ibcon#wrote, iclass 3, count 2 2006.285.09:53:40.87#ibcon#about to read 3, iclass 3, count 2 2006.285.09:53:40.90#ibcon#read 3, iclass 3, count 2 2006.285.09:53:40.90#ibcon#about to read 4, iclass 3, count 2 2006.285.09:53:40.90#ibcon#read 4, iclass 3, count 2 2006.285.09:53:40.90#ibcon#about to read 5, iclass 3, count 2 2006.285.09:53:40.90#ibcon#read 5, iclass 3, count 2 2006.285.09:53:40.90#ibcon#about to read 6, iclass 3, count 2 2006.285.09:53:40.90#ibcon#read 6, iclass 3, count 2 2006.285.09:53:40.90#ibcon#end of sib2, iclass 3, count 2 2006.285.09:53:40.90#ibcon#*after write, iclass 3, count 2 2006.285.09:53:40.90#ibcon#*before return 0, iclass 3, count 2 2006.285.09:53:40.90#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:53:40.90#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:53:40.90#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.09:53:40.90#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:40.90#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:53:41.02#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:53:41.02#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:53:41.02#ibcon#enter wrdev, iclass 3, count 0 2006.285.09:53:41.02#ibcon#first serial, iclass 3, count 0 2006.285.09:53:41.02#ibcon#enter sib2, iclass 3, count 0 2006.285.09:53:41.02#ibcon#flushed, iclass 3, count 0 2006.285.09:53:41.02#ibcon#about to write, iclass 3, count 0 2006.285.09:53:41.02#ibcon#wrote, iclass 3, count 0 2006.285.09:53:41.02#ibcon#about to read 3, iclass 3, count 0 2006.285.09:53:41.04#ibcon#read 3, iclass 3, count 0 2006.285.09:53:41.04#ibcon#about to read 4, iclass 3, count 0 2006.285.09:53:41.04#ibcon#read 4, iclass 3, count 0 2006.285.09:53:41.04#ibcon#about to read 5, iclass 3, count 0 2006.285.09:53:41.04#ibcon#read 5, iclass 3, count 0 2006.285.09:53:41.04#ibcon#about to read 6, iclass 3, count 0 2006.285.09:53:41.04#ibcon#read 6, iclass 3, count 0 2006.285.09:53:41.04#ibcon#end of sib2, iclass 3, count 0 2006.285.09:53:41.04#ibcon#*mode == 0, iclass 3, count 0 2006.285.09:53:41.04#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.09:53:41.04#ibcon#[25=USB\r\n] 2006.285.09:53:41.04#ibcon#*before write, iclass 3, count 0 2006.285.09:53:41.04#ibcon#enter sib2, iclass 3, count 0 2006.285.09:53:41.04#ibcon#flushed, iclass 3, count 0 2006.285.09:53:41.04#ibcon#about to write, iclass 3, count 0 2006.285.09:53:41.04#ibcon#wrote, iclass 3, count 0 2006.285.09:53:41.04#ibcon#about to read 3, iclass 3, count 0 2006.285.09:53:41.07#ibcon#read 3, iclass 3, count 0 2006.285.09:53:41.07#ibcon#about to read 4, iclass 3, count 0 2006.285.09:53:41.07#ibcon#read 4, iclass 3, count 0 2006.285.09:53:41.07#ibcon#about to read 5, iclass 3, count 0 2006.285.09:53:41.07#ibcon#read 5, iclass 3, count 0 2006.285.09:53:41.07#ibcon#about to read 6, iclass 3, count 0 2006.285.09:53:41.07#ibcon#read 6, iclass 3, count 0 2006.285.09:53:41.07#ibcon#end of sib2, iclass 3, count 0 2006.285.09:53:41.07#ibcon#*after write, iclass 3, count 0 2006.285.09:53:41.07#ibcon#*before return 0, iclass 3, count 0 2006.285.09:53:41.07#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:53:41.07#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:53:41.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.09:53:41.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.09:53:41.07$vck44/valo=6,814.99 2006.285.09:53:41.07#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.09:53:41.07#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.09:53:41.07#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:41.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:53:41.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:53:41.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:53:41.07#ibcon#enter wrdev, iclass 5, count 0 2006.285.09:53:41.07#ibcon#first serial, iclass 5, count 0 2006.285.09:53:41.07#ibcon#enter sib2, iclass 5, count 0 2006.285.09:53:41.07#ibcon#flushed, iclass 5, count 0 2006.285.09:53:41.07#ibcon#about to write, iclass 5, count 0 2006.285.09:53:41.07#ibcon#wrote, iclass 5, count 0 2006.285.09:53:41.07#ibcon#about to read 3, iclass 5, count 0 2006.285.09:53:41.09#ibcon#read 3, iclass 5, count 0 2006.285.09:53:41.09#ibcon#about to read 4, iclass 5, count 0 2006.285.09:53:41.09#ibcon#read 4, iclass 5, count 0 2006.285.09:53:41.09#ibcon#about to read 5, iclass 5, count 0 2006.285.09:53:41.09#ibcon#read 5, iclass 5, count 0 2006.285.09:53:41.09#ibcon#about to read 6, iclass 5, count 0 2006.285.09:53:41.09#ibcon#read 6, iclass 5, count 0 2006.285.09:53:41.09#ibcon#end of sib2, iclass 5, count 0 2006.285.09:53:41.09#ibcon#*mode == 0, iclass 5, count 0 2006.285.09:53:41.09#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.09:53:41.09#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:53:41.09#ibcon#*before write, iclass 5, count 0 2006.285.09:53:41.09#ibcon#enter sib2, iclass 5, count 0 2006.285.09:53:41.09#ibcon#flushed, iclass 5, count 0 2006.285.09:53:41.09#ibcon#about to write, iclass 5, count 0 2006.285.09:53:41.09#ibcon#wrote, iclass 5, count 0 2006.285.09:53:41.09#ibcon#about to read 3, iclass 5, count 0 2006.285.09:53:41.13#ibcon#read 3, iclass 5, count 0 2006.285.09:53:41.13#ibcon#about to read 4, iclass 5, count 0 2006.285.09:53:41.13#ibcon#read 4, iclass 5, count 0 2006.285.09:53:41.13#ibcon#about to read 5, iclass 5, count 0 2006.285.09:53:41.13#ibcon#read 5, iclass 5, count 0 2006.285.09:53:41.13#ibcon#about to read 6, iclass 5, count 0 2006.285.09:53:41.13#ibcon#read 6, iclass 5, count 0 2006.285.09:53:41.13#ibcon#end of sib2, iclass 5, count 0 2006.285.09:53:41.13#ibcon#*after write, iclass 5, count 0 2006.285.09:53:41.13#ibcon#*before return 0, iclass 5, count 0 2006.285.09:53:41.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:53:41.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:53:41.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.09:53:41.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.09:53:41.13$vck44/va=6,4 2006.285.09:53:41.13#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.09:53:41.13#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.09:53:41.13#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:41.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:53:41.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:53:41.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:53:41.19#ibcon#enter wrdev, iclass 7, count 2 2006.285.09:53:41.19#ibcon#first serial, iclass 7, count 2 2006.285.09:53:41.19#ibcon#enter sib2, iclass 7, count 2 2006.285.09:53:41.19#ibcon#flushed, iclass 7, count 2 2006.285.09:53:41.19#ibcon#about to write, iclass 7, count 2 2006.285.09:53:41.19#ibcon#wrote, iclass 7, count 2 2006.285.09:53:41.19#ibcon#about to read 3, iclass 7, count 2 2006.285.09:53:41.21#ibcon#read 3, iclass 7, count 2 2006.285.09:53:41.21#ibcon#about to read 4, iclass 7, count 2 2006.285.09:53:41.21#ibcon#read 4, iclass 7, count 2 2006.285.09:53:41.21#ibcon#about to read 5, iclass 7, count 2 2006.285.09:53:41.21#ibcon#read 5, iclass 7, count 2 2006.285.09:53:41.21#ibcon#about to read 6, iclass 7, count 2 2006.285.09:53:41.21#ibcon#read 6, iclass 7, count 2 2006.285.09:53:41.21#ibcon#end of sib2, iclass 7, count 2 2006.285.09:53:41.21#ibcon#*mode == 0, iclass 7, count 2 2006.285.09:53:41.21#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.09:53:41.21#ibcon#[25=AT06-04\r\n] 2006.285.09:53:41.21#ibcon#*before write, iclass 7, count 2 2006.285.09:53:41.21#ibcon#enter sib2, iclass 7, count 2 2006.285.09:53:41.21#ibcon#flushed, iclass 7, count 2 2006.285.09:53:41.21#ibcon#about to write, iclass 7, count 2 2006.285.09:53:41.21#ibcon#wrote, iclass 7, count 2 2006.285.09:53:41.21#ibcon#about to read 3, iclass 7, count 2 2006.285.09:53:41.24#ibcon#read 3, iclass 7, count 2 2006.285.09:53:41.24#ibcon#about to read 4, iclass 7, count 2 2006.285.09:53:41.24#ibcon#read 4, iclass 7, count 2 2006.285.09:53:41.24#ibcon#about to read 5, iclass 7, count 2 2006.285.09:53:41.24#ibcon#read 5, iclass 7, count 2 2006.285.09:53:41.24#ibcon#about to read 6, iclass 7, count 2 2006.285.09:53:41.24#ibcon#read 6, iclass 7, count 2 2006.285.09:53:41.24#ibcon#end of sib2, iclass 7, count 2 2006.285.09:53:41.24#ibcon#*after write, iclass 7, count 2 2006.285.09:53:41.24#ibcon#*before return 0, iclass 7, count 2 2006.285.09:53:41.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:53:41.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:53:41.24#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.09:53:41.24#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:41.24#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:53:41.36#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:53:41.36#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:53:41.36#ibcon#enter wrdev, iclass 7, count 0 2006.285.09:53:41.36#ibcon#first serial, iclass 7, count 0 2006.285.09:53:41.36#ibcon#enter sib2, iclass 7, count 0 2006.285.09:53:41.36#ibcon#flushed, iclass 7, count 0 2006.285.09:53:41.36#ibcon#about to write, iclass 7, count 0 2006.285.09:53:41.36#ibcon#wrote, iclass 7, count 0 2006.285.09:53:41.36#ibcon#about to read 3, iclass 7, count 0 2006.285.09:53:41.38#ibcon#read 3, iclass 7, count 0 2006.285.09:53:41.38#ibcon#about to read 4, iclass 7, count 0 2006.285.09:53:41.38#ibcon#read 4, iclass 7, count 0 2006.285.09:53:41.38#ibcon#about to read 5, iclass 7, count 0 2006.285.09:53:41.38#ibcon#read 5, iclass 7, count 0 2006.285.09:53:41.38#ibcon#about to read 6, iclass 7, count 0 2006.285.09:53:41.38#ibcon#read 6, iclass 7, count 0 2006.285.09:53:41.38#ibcon#end of sib2, iclass 7, count 0 2006.285.09:53:41.38#ibcon#*mode == 0, iclass 7, count 0 2006.285.09:53:41.38#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.09:53:41.38#ibcon#[25=USB\r\n] 2006.285.09:53:41.38#ibcon#*before write, iclass 7, count 0 2006.285.09:53:41.38#ibcon#enter sib2, iclass 7, count 0 2006.285.09:53:41.38#ibcon#flushed, iclass 7, count 0 2006.285.09:53:41.38#ibcon#about to write, iclass 7, count 0 2006.285.09:53:41.38#ibcon#wrote, iclass 7, count 0 2006.285.09:53:41.38#ibcon#about to read 3, iclass 7, count 0 2006.285.09:53:41.41#ibcon#read 3, iclass 7, count 0 2006.285.09:53:41.41#ibcon#about to read 4, iclass 7, count 0 2006.285.09:53:41.41#ibcon#read 4, iclass 7, count 0 2006.285.09:53:41.41#ibcon#about to read 5, iclass 7, count 0 2006.285.09:53:41.41#ibcon#read 5, iclass 7, count 0 2006.285.09:53:41.41#ibcon#about to read 6, iclass 7, count 0 2006.285.09:53:41.41#ibcon#read 6, iclass 7, count 0 2006.285.09:53:41.41#ibcon#end of sib2, iclass 7, count 0 2006.285.09:53:41.41#ibcon#*after write, iclass 7, count 0 2006.285.09:53:41.41#ibcon#*before return 0, iclass 7, count 0 2006.285.09:53:41.41#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:53:41.41#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:53:41.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.09:53:41.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.09:53:41.41$vck44/valo=7,864.99 2006.285.09:53:41.41#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.09:53:41.41#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.09:53:41.41#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:41.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:53:41.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:53:41.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:53:41.41#ibcon#enter wrdev, iclass 11, count 0 2006.285.09:53:41.41#ibcon#first serial, iclass 11, count 0 2006.285.09:53:41.41#ibcon#enter sib2, iclass 11, count 0 2006.285.09:53:41.41#ibcon#flushed, iclass 11, count 0 2006.285.09:53:41.41#ibcon#about to write, iclass 11, count 0 2006.285.09:53:41.41#ibcon#wrote, iclass 11, count 0 2006.285.09:53:41.41#ibcon#about to read 3, iclass 11, count 0 2006.285.09:53:41.43#ibcon#read 3, iclass 11, count 0 2006.285.09:53:41.43#ibcon#about to read 4, iclass 11, count 0 2006.285.09:53:41.43#ibcon#read 4, iclass 11, count 0 2006.285.09:53:41.43#ibcon#about to read 5, iclass 11, count 0 2006.285.09:53:41.43#ibcon#read 5, iclass 11, count 0 2006.285.09:53:41.43#ibcon#about to read 6, iclass 11, count 0 2006.285.09:53:41.43#ibcon#read 6, iclass 11, count 0 2006.285.09:53:41.43#ibcon#end of sib2, iclass 11, count 0 2006.285.09:53:41.43#ibcon#*mode == 0, iclass 11, count 0 2006.285.09:53:41.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.09:53:41.43#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:53:41.43#ibcon#*before write, iclass 11, count 0 2006.285.09:53:41.43#ibcon#enter sib2, iclass 11, count 0 2006.285.09:53:41.43#ibcon#flushed, iclass 11, count 0 2006.285.09:53:41.43#ibcon#about to write, iclass 11, count 0 2006.285.09:53:41.43#ibcon#wrote, iclass 11, count 0 2006.285.09:53:41.43#ibcon#about to read 3, iclass 11, count 0 2006.285.09:53:41.47#ibcon#read 3, iclass 11, count 0 2006.285.09:53:41.47#ibcon#about to read 4, iclass 11, count 0 2006.285.09:53:41.47#ibcon#read 4, iclass 11, count 0 2006.285.09:53:41.47#ibcon#about to read 5, iclass 11, count 0 2006.285.09:53:41.47#ibcon#read 5, iclass 11, count 0 2006.285.09:53:41.47#ibcon#about to read 6, iclass 11, count 0 2006.285.09:53:41.47#ibcon#read 6, iclass 11, count 0 2006.285.09:53:41.47#ibcon#end of sib2, iclass 11, count 0 2006.285.09:53:41.47#ibcon#*after write, iclass 11, count 0 2006.285.09:53:41.47#ibcon#*before return 0, iclass 11, count 0 2006.285.09:53:41.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:53:41.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:53:41.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.09:53:41.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.09:53:41.47$vck44/va=7,4 2006.285.09:53:41.47#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.09:53:41.47#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.09:53:41.47#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:41.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:53:41.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:53:41.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:53:41.53#ibcon#enter wrdev, iclass 13, count 2 2006.285.09:53:41.53#ibcon#first serial, iclass 13, count 2 2006.285.09:53:41.53#ibcon#enter sib2, iclass 13, count 2 2006.285.09:53:41.53#ibcon#flushed, iclass 13, count 2 2006.285.09:53:41.53#ibcon#about to write, iclass 13, count 2 2006.285.09:53:41.53#ibcon#wrote, iclass 13, count 2 2006.285.09:53:41.53#ibcon#about to read 3, iclass 13, count 2 2006.285.09:53:41.55#ibcon#read 3, iclass 13, count 2 2006.285.09:53:41.55#ibcon#about to read 4, iclass 13, count 2 2006.285.09:53:41.55#ibcon#read 4, iclass 13, count 2 2006.285.09:53:41.55#ibcon#about to read 5, iclass 13, count 2 2006.285.09:53:41.55#ibcon#read 5, iclass 13, count 2 2006.285.09:53:41.55#ibcon#about to read 6, iclass 13, count 2 2006.285.09:53:41.55#ibcon#read 6, iclass 13, count 2 2006.285.09:53:41.55#ibcon#end of sib2, iclass 13, count 2 2006.285.09:53:41.55#ibcon#*mode == 0, iclass 13, count 2 2006.285.09:53:41.55#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.09:53:41.55#ibcon#[25=AT07-04\r\n] 2006.285.09:53:41.55#ibcon#*before write, iclass 13, count 2 2006.285.09:53:41.55#ibcon#enter sib2, iclass 13, count 2 2006.285.09:53:41.55#ibcon#flushed, iclass 13, count 2 2006.285.09:53:41.55#ibcon#about to write, iclass 13, count 2 2006.285.09:53:41.55#ibcon#wrote, iclass 13, count 2 2006.285.09:53:41.55#ibcon#about to read 3, iclass 13, count 2 2006.285.09:53:41.58#ibcon#read 3, iclass 13, count 2 2006.285.09:53:41.58#ibcon#about to read 4, iclass 13, count 2 2006.285.09:53:41.58#ibcon#read 4, iclass 13, count 2 2006.285.09:53:41.58#ibcon#about to read 5, iclass 13, count 2 2006.285.09:53:41.58#ibcon#read 5, iclass 13, count 2 2006.285.09:53:41.58#ibcon#about to read 6, iclass 13, count 2 2006.285.09:53:41.58#ibcon#read 6, iclass 13, count 2 2006.285.09:53:41.58#ibcon#end of sib2, iclass 13, count 2 2006.285.09:53:41.58#ibcon#*after write, iclass 13, count 2 2006.285.09:53:41.58#ibcon#*before return 0, iclass 13, count 2 2006.285.09:53:41.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:53:41.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:53:41.58#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.09:53:41.58#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:41.58#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:53:41.70#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:53:41.70#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:53:41.70#ibcon#enter wrdev, iclass 13, count 0 2006.285.09:53:41.70#ibcon#first serial, iclass 13, count 0 2006.285.09:53:41.70#ibcon#enter sib2, iclass 13, count 0 2006.285.09:53:41.70#ibcon#flushed, iclass 13, count 0 2006.285.09:53:41.70#ibcon#about to write, iclass 13, count 0 2006.285.09:53:41.70#ibcon#wrote, iclass 13, count 0 2006.285.09:53:41.70#ibcon#about to read 3, iclass 13, count 0 2006.285.09:53:41.72#ibcon#read 3, iclass 13, count 0 2006.285.09:53:41.72#ibcon#about to read 4, iclass 13, count 0 2006.285.09:53:41.72#ibcon#read 4, iclass 13, count 0 2006.285.09:53:41.72#ibcon#about to read 5, iclass 13, count 0 2006.285.09:53:41.72#ibcon#read 5, iclass 13, count 0 2006.285.09:53:41.72#ibcon#about to read 6, iclass 13, count 0 2006.285.09:53:41.72#ibcon#read 6, iclass 13, count 0 2006.285.09:53:41.72#ibcon#end of sib2, iclass 13, count 0 2006.285.09:53:41.72#ibcon#*mode == 0, iclass 13, count 0 2006.285.09:53:41.72#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.09:53:41.72#ibcon#[25=USB\r\n] 2006.285.09:53:41.72#ibcon#*before write, iclass 13, count 0 2006.285.09:53:41.72#ibcon#enter sib2, iclass 13, count 0 2006.285.09:53:41.72#ibcon#flushed, iclass 13, count 0 2006.285.09:53:41.72#ibcon#about to write, iclass 13, count 0 2006.285.09:53:41.72#ibcon#wrote, iclass 13, count 0 2006.285.09:53:41.72#ibcon#about to read 3, iclass 13, count 0 2006.285.09:53:41.75#ibcon#read 3, iclass 13, count 0 2006.285.09:53:41.75#ibcon#about to read 4, iclass 13, count 0 2006.285.09:53:41.75#ibcon#read 4, iclass 13, count 0 2006.285.09:53:41.75#ibcon#about to read 5, iclass 13, count 0 2006.285.09:53:41.75#ibcon#read 5, iclass 13, count 0 2006.285.09:53:41.75#ibcon#about to read 6, iclass 13, count 0 2006.285.09:53:41.75#ibcon#read 6, iclass 13, count 0 2006.285.09:53:41.75#ibcon#end of sib2, iclass 13, count 0 2006.285.09:53:41.75#ibcon#*after write, iclass 13, count 0 2006.285.09:53:41.75#ibcon#*before return 0, iclass 13, count 0 2006.285.09:53:41.75#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:53:41.75#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:53:41.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.09:53:41.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.09:53:41.75$vck44/valo=8,884.99 2006.285.09:53:41.75#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.09:53:41.75#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.09:53:41.75#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:41.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:53:41.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:53:41.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:53:41.75#ibcon#enter wrdev, iclass 15, count 0 2006.285.09:53:41.75#ibcon#first serial, iclass 15, count 0 2006.285.09:53:41.75#ibcon#enter sib2, iclass 15, count 0 2006.285.09:53:41.75#ibcon#flushed, iclass 15, count 0 2006.285.09:53:41.75#ibcon#about to write, iclass 15, count 0 2006.285.09:53:41.75#ibcon#wrote, iclass 15, count 0 2006.285.09:53:41.75#ibcon#about to read 3, iclass 15, count 0 2006.285.09:53:41.77#ibcon#read 3, iclass 15, count 0 2006.285.09:53:41.77#ibcon#about to read 4, iclass 15, count 0 2006.285.09:53:41.77#ibcon#read 4, iclass 15, count 0 2006.285.09:53:41.77#ibcon#about to read 5, iclass 15, count 0 2006.285.09:53:41.77#ibcon#read 5, iclass 15, count 0 2006.285.09:53:41.77#ibcon#about to read 6, iclass 15, count 0 2006.285.09:53:41.77#ibcon#read 6, iclass 15, count 0 2006.285.09:53:41.77#ibcon#end of sib2, iclass 15, count 0 2006.285.09:53:41.77#ibcon#*mode == 0, iclass 15, count 0 2006.285.09:53:41.77#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.09:53:41.77#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:53:41.77#ibcon#*before write, iclass 15, count 0 2006.285.09:53:41.77#ibcon#enter sib2, iclass 15, count 0 2006.285.09:53:41.77#ibcon#flushed, iclass 15, count 0 2006.285.09:53:41.77#ibcon#about to write, iclass 15, count 0 2006.285.09:53:41.77#ibcon#wrote, iclass 15, count 0 2006.285.09:53:41.77#ibcon#about to read 3, iclass 15, count 0 2006.285.09:53:41.81#ibcon#read 3, iclass 15, count 0 2006.285.09:53:41.81#ibcon#about to read 4, iclass 15, count 0 2006.285.09:53:41.81#ibcon#read 4, iclass 15, count 0 2006.285.09:53:41.81#ibcon#about to read 5, iclass 15, count 0 2006.285.09:53:41.81#ibcon#read 5, iclass 15, count 0 2006.285.09:53:41.81#ibcon#about to read 6, iclass 15, count 0 2006.285.09:53:41.81#ibcon#read 6, iclass 15, count 0 2006.285.09:53:41.81#ibcon#end of sib2, iclass 15, count 0 2006.285.09:53:41.81#ibcon#*after write, iclass 15, count 0 2006.285.09:53:41.81#ibcon#*before return 0, iclass 15, count 0 2006.285.09:53:41.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:53:41.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:53:41.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.09:53:41.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.09:53:41.81$vck44/va=8,3 2006.285.09:53:41.81#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.09:53:41.81#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.09:53:41.81#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:41.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:53:41.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:53:41.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:53:41.87#ibcon#enter wrdev, iclass 17, count 2 2006.285.09:53:41.87#ibcon#first serial, iclass 17, count 2 2006.285.09:53:41.87#ibcon#enter sib2, iclass 17, count 2 2006.285.09:53:41.87#ibcon#flushed, iclass 17, count 2 2006.285.09:53:41.87#ibcon#about to write, iclass 17, count 2 2006.285.09:53:41.87#ibcon#wrote, iclass 17, count 2 2006.285.09:53:41.87#ibcon#about to read 3, iclass 17, count 2 2006.285.09:53:41.89#ibcon#read 3, iclass 17, count 2 2006.285.09:53:41.89#ibcon#about to read 4, iclass 17, count 2 2006.285.09:53:41.89#ibcon#read 4, iclass 17, count 2 2006.285.09:53:41.89#ibcon#about to read 5, iclass 17, count 2 2006.285.09:53:41.89#ibcon#read 5, iclass 17, count 2 2006.285.09:53:41.89#ibcon#about to read 6, iclass 17, count 2 2006.285.09:53:41.89#ibcon#read 6, iclass 17, count 2 2006.285.09:53:41.89#ibcon#end of sib2, iclass 17, count 2 2006.285.09:53:41.89#ibcon#*mode == 0, iclass 17, count 2 2006.285.09:53:41.89#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.09:53:41.89#ibcon#[25=AT08-03\r\n] 2006.285.09:53:41.89#ibcon#*before write, iclass 17, count 2 2006.285.09:53:41.89#ibcon#enter sib2, iclass 17, count 2 2006.285.09:53:41.89#ibcon#flushed, iclass 17, count 2 2006.285.09:53:41.89#ibcon#about to write, iclass 17, count 2 2006.285.09:53:41.89#ibcon#wrote, iclass 17, count 2 2006.285.09:53:41.89#ibcon#about to read 3, iclass 17, count 2 2006.285.09:53:41.92#ibcon#read 3, iclass 17, count 2 2006.285.09:53:41.92#ibcon#about to read 4, iclass 17, count 2 2006.285.09:53:41.92#ibcon#read 4, iclass 17, count 2 2006.285.09:53:41.92#ibcon#about to read 5, iclass 17, count 2 2006.285.09:53:41.92#ibcon#read 5, iclass 17, count 2 2006.285.09:53:41.92#ibcon#about to read 6, iclass 17, count 2 2006.285.09:53:41.92#ibcon#read 6, iclass 17, count 2 2006.285.09:53:41.92#ibcon#end of sib2, iclass 17, count 2 2006.285.09:53:41.92#ibcon#*after write, iclass 17, count 2 2006.285.09:53:41.92#ibcon#*before return 0, iclass 17, count 2 2006.285.09:53:41.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:53:41.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.09:53:41.92#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.09:53:41.92#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:41.92#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:53:42.04#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:53:42.04#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:53:42.04#ibcon#enter wrdev, iclass 17, count 0 2006.285.09:53:42.04#ibcon#first serial, iclass 17, count 0 2006.285.09:53:42.04#ibcon#enter sib2, iclass 17, count 0 2006.285.09:53:42.04#ibcon#flushed, iclass 17, count 0 2006.285.09:53:42.04#ibcon#about to write, iclass 17, count 0 2006.285.09:53:42.04#ibcon#wrote, iclass 17, count 0 2006.285.09:53:42.04#ibcon#about to read 3, iclass 17, count 0 2006.285.09:53:42.06#ibcon#read 3, iclass 17, count 0 2006.285.09:53:42.06#ibcon#about to read 4, iclass 17, count 0 2006.285.09:53:42.06#ibcon#read 4, iclass 17, count 0 2006.285.09:53:42.06#ibcon#about to read 5, iclass 17, count 0 2006.285.09:53:42.06#ibcon#read 5, iclass 17, count 0 2006.285.09:53:42.06#ibcon#about to read 6, iclass 17, count 0 2006.285.09:53:42.06#ibcon#read 6, iclass 17, count 0 2006.285.09:53:42.06#ibcon#end of sib2, iclass 17, count 0 2006.285.09:53:42.06#ibcon#*mode == 0, iclass 17, count 0 2006.285.09:53:42.06#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.09:53:42.06#ibcon#[25=USB\r\n] 2006.285.09:53:42.06#ibcon#*before write, iclass 17, count 0 2006.285.09:53:42.06#ibcon#enter sib2, iclass 17, count 0 2006.285.09:53:42.06#ibcon#flushed, iclass 17, count 0 2006.285.09:53:42.06#ibcon#about to write, iclass 17, count 0 2006.285.09:53:42.06#ibcon#wrote, iclass 17, count 0 2006.285.09:53:42.06#ibcon#about to read 3, iclass 17, count 0 2006.285.09:53:42.09#ibcon#read 3, iclass 17, count 0 2006.285.09:53:42.09#ibcon#about to read 4, iclass 17, count 0 2006.285.09:53:42.09#ibcon#read 4, iclass 17, count 0 2006.285.09:53:42.09#ibcon#about to read 5, iclass 17, count 0 2006.285.09:53:42.09#ibcon#read 5, iclass 17, count 0 2006.285.09:53:42.09#ibcon#about to read 6, iclass 17, count 0 2006.285.09:53:42.09#ibcon#read 6, iclass 17, count 0 2006.285.09:53:42.09#ibcon#end of sib2, iclass 17, count 0 2006.285.09:53:42.09#ibcon#*after write, iclass 17, count 0 2006.285.09:53:42.09#ibcon#*before return 0, iclass 17, count 0 2006.285.09:53:42.09#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:53:42.09#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.09:53:42.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.09:53:42.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.09:53:42.09$vck44/vblo=1,629.99 2006.285.09:53:42.09#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.09:53:42.09#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.09:53:42.09#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:42.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:53:42.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:53:42.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:53:42.09#ibcon#enter wrdev, iclass 19, count 0 2006.285.09:53:42.09#ibcon#first serial, iclass 19, count 0 2006.285.09:53:42.09#ibcon#enter sib2, iclass 19, count 0 2006.285.09:53:42.09#ibcon#flushed, iclass 19, count 0 2006.285.09:53:42.09#ibcon#about to write, iclass 19, count 0 2006.285.09:53:42.09#ibcon#wrote, iclass 19, count 0 2006.285.09:53:42.09#ibcon#about to read 3, iclass 19, count 0 2006.285.09:53:42.11#ibcon#read 3, iclass 19, count 0 2006.285.09:53:42.11#ibcon#about to read 4, iclass 19, count 0 2006.285.09:53:42.11#ibcon#read 4, iclass 19, count 0 2006.285.09:53:42.11#ibcon#about to read 5, iclass 19, count 0 2006.285.09:53:42.11#ibcon#read 5, iclass 19, count 0 2006.285.09:53:42.11#ibcon#about to read 6, iclass 19, count 0 2006.285.09:53:42.11#ibcon#read 6, iclass 19, count 0 2006.285.09:53:42.11#ibcon#end of sib2, iclass 19, count 0 2006.285.09:53:42.11#ibcon#*mode == 0, iclass 19, count 0 2006.285.09:53:42.11#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.09:53:42.11#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:53:42.11#ibcon#*before write, iclass 19, count 0 2006.285.09:53:42.11#ibcon#enter sib2, iclass 19, count 0 2006.285.09:53:42.11#ibcon#flushed, iclass 19, count 0 2006.285.09:53:42.11#ibcon#about to write, iclass 19, count 0 2006.285.09:53:42.11#ibcon#wrote, iclass 19, count 0 2006.285.09:53:42.11#ibcon#about to read 3, iclass 19, count 0 2006.285.09:53:42.15#ibcon#read 3, iclass 19, count 0 2006.285.09:53:42.15#ibcon#about to read 4, iclass 19, count 0 2006.285.09:53:42.15#ibcon#read 4, iclass 19, count 0 2006.285.09:53:42.15#ibcon#about to read 5, iclass 19, count 0 2006.285.09:53:42.15#ibcon#read 5, iclass 19, count 0 2006.285.09:53:42.15#ibcon#about to read 6, iclass 19, count 0 2006.285.09:53:42.15#ibcon#read 6, iclass 19, count 0 2006.285.09:53:42.15#ibcon#end of sib2, iclass 19, count 0 2006.285.09:53:42.15#ibcon#*after write, iclass 19, count 0 2006.285.09:53:42.15#ibcon#*before return 0, iclass 19, count 0 2006.285.09:53:42.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:53:42.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.09:53:42.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.09:53:42.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.09:53:42.15$vck44/vb=1,4 2006.285.09:53:42.15#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.09:53:42.15#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.09:53:42.15#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:42.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:53:42.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:53:42.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:53:42.15#ibcon#enter wrdev, iclass 21, count 2 2006.285.09:53:42.15#ibcon#first serial, iclass 21, count 2 2006.285.09:53:42.15#ibcon#enter sib2, iclass 21, count 2 2006.285.09:53:42.15#ibcon#flushed, iclass 21, count 2 2006.285.09:53:42.15#ibcon#about to write, iclass 21, count 2 2006.285.09:53:42.15#ibcon#wrote, iclass 21, count 2 2006.285.09:53:42.15#ibcon#about to read 3, iclass 21, count 2 2006.285.09:53:42.17#ibcon#read 3, iclass 21, count 2 2006.285.09:53:42.17#ibcon#about to read 4, iclass 21, count 2 2006.285.09:53:42.17#ibcon#read 4, iclass 21, count 2 2006.285.09:53:42.17#ibcon#about to read 5, iclass 21, count 2 2006.285.09:53:42.17#ibcon#read 5, iclass 21, count 2 2006.285.09:53:42.17#ibcon#about to read 6, iclass 21, count 2 2006.285.09:53:42.17#ibcon#read 6, iclass 21, count 2 2006.285.09:53:42.17#ibcon#end of sib2, iclass 21, count 2 2006.285.09:53:42.17#ibcon#*mode == 0, iclass 21, count 2 2006.285.09:53:42.17#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.09:53:42.17#ibcon#[27=AT01-04\r\n] 2006.285.09:53:42.17#ibcon#*before write, iclass 21, count 2 2006.285.09:53:42.17#ibcon#enter sib2, iclass 21, count 2 2006.285.09:53:42.17#ibcon#flushed, iclass 21, count 2 2006.285.09:53:42.17#ibcon#about to write, iclass 21, count 2 2006.285.09:53:42.17#ibcon#wrote, iclass 21, count 2 2006.285.09:53:42.17#ibcon#about to read 3, iclass 21, count 2 2006.285.09:53:42.20#ibcon#read 3, iclass 21, count 2 2006.285.09:53:42.20#ibcon#about to read 4, iclass 21, count 2 2006.285.09:53:42.20#ibcon#read 4, iclass 21, count 2 2006.285.09:53:42.20#ibcon#about to read 5, iclass 21, count 2 2006.285.09:53:42.20#ibcon#read 5, iclass 21, count 2 2006.285.09:53:42.20#ibcon#about to read 6, iclass 21, count 2 2006.285.09:53:42.20#ibcon#read 6, iclass 21, count 2 2006.285.09:53:42.20#ibcon#end of sib2, iclass 21, count 2 2006.285.09:53:42.20#ibcon#*after write, iclass 21, count 2 2006.285.09:53:42.20#ibcon#*before return 0, iclass 21, count 2 2006.285.09:53:42.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:53:42.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.09:53:42.20#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.09:53:42.20#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:42.20#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:53:42.32#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:53:42.32#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:53:42.32#ibcon#enter wrdev, iclass 21, count 0 2006.285.09:53:42.32#ibcon#first serial, iclass 21, count 0 2006.285.09:53:42.32#ibcon#enter sib2, iclass 21, count 0 2006.285.09:53:42.32#ibcon#flushed, iclass 21, count 0 2006.285.09:53:42.32#ibcon#about to write, iclass 21, count 0 2006.285.09:53:42.32#ibcon#wrote, iclass 21, count 0 2006.285.09:53:42.32#ibcon#about to read 3, iclass 21, count 0 2006.285.09:53:42.34#ibcon#read 3, iclass 21, count 0 2006.285.09:53:42.34#ibcon#about to read 4, iclass 21, count 0 2006.285.09:53:42.34#ibcon#read 4, iclass 21, count 0 2006.285.09:53:42.34#ibcon#about to read 5, iclass 21, count 0 2006.285.09:53:42.34#ibcon#read 5, iclass 21, count 0 2006.285.09:53:42.34#ibcon#about to read 6, iclass 21, count 0 2006.285.09:53:42.34#ibcon#read 6, iclass 21, count 0 2006.285.09:53:42.34#ibcon#end of sib2, iclass 21, count 0 2006.285.09:53:42.34#ibcon#*mode == 0, iclass 21, count 0 2006.285.09:53:42.34#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.09:53:42.34#ibcon#[27=USB\r\n] 2006.285.09:53:42.34#ibcon#*before write, iclass 21, count 0 2006.285.09:53:42.34#ibcon#enter sib2, iclass 21, count 0 2006.285.09:53:42.34#ibcon#flushed, iclass 21, count 0 2006.285.09:53:42.34#ibcon#about to write, iclass 21, count 0 2006.285.09:53:42.34#ibcon#wrote, iclass 21, count 0 2006.285.09:53:42.34#ibcon#about to read 3, iclass 21, count 0 2006.285.09:53:42.37#ibcon#read 3, iclass 21, count 0 2006.285.09:53:42.37#ibcon#about to read 4, iclass 21, count 0 2006.285.09:53:42.37#ibcon#read 4, iclass 21, count 0 2006.285.09:53:42.37#ibcon#about to read 5, iclass 21, count 0 2006.285.09:53:42.37#ibcon#read 5, iclass 21, count 0 2006.285.09:53:42.37#ibcon#about to read 6, iclass 21, count 0 2006.285.09:53:42.37#ibcon#read 6, iclass 21, count 0 2006.285.09:53:42.37#ibcon#end of sib2, iclass 21, count 0 2006.285.09:53:42.37#ibcon#*after write, iclass 21, count 0 2006.285.09:53:42.37#ibcon#*before return 0, iclass 21, count 0 2006.285.09:53:42.37#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:53:42.37#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.09:53:42.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.09:53:42.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.09:53:42.37$vck44/vblo=2,634.99 2006.285.09:53:42.37#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.09:53:42.37#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.09:53:42.37#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:42.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:53:42.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:53:42.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:53:42.37#ibcon#enter wrdev, iclass 23, count 0 2006.285.09:53:42.37#ibcon#first serial, iclass 23, count 0 2006.285.09:53:42.37#ibcon#enter sib2, iclass 23, count 0 2006.285.09:53:42.37#ibcon#flushed, iclass 23, count 0 2006.285.09:53:42.37#ibcon#about to write, iclass 23, count 0 2006.285.09:53:42.37#ibcon#wrote, iclass 23, count 0 2006.285.09:53:42.37#ibcon#about to read 3, iclass 23, count 0 2006.285.09:53:42.39#ibcon#read 3, iclass 23, count 0 2006.285.09:53:42.39#ibcon#about to read 4, iclass 23, count 0 2006.285.09:53:42.39#ibcon#read 4, iclass 23, count 0 2006.285.09:53:42.39#ibcon#about to read 5, iclass 23, count 0 2006.285.09:53:42.39#ibcon#read 5, iclass 23, count 0 2006.285.09:53:42.39#ibcon#about to read 6, iclass 23, count 0 2006.285.09:53:42.39#ibcon#read 6, iclass 23, count 0 2006.285.09:53:42.39#ibcon#end of sib2, iclass 23, count 0 2006.285.09:53:42.39#ibcon#*mode == 0, iclass 23, count 0 2006.285.09:53:42.39#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.09:53:42.39#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:53:42.39#ibcon#*before write, iclass 23, count 0 2006.285.09:53:42.39#ibcon#enter sib2, iclass 23, count 0 2006.285.09:53:42.39#ibcon#flushed, iclass 23, count 0 2006.285.09:53:42.39#ibcon#about to write, iclass 23, count 0 2006.285.09:53:42.39#ibcon#wrote, iclass 23, count 0 2006.285.09:53:42.39#ibcon#about to read 3, iclass 23, count 0 2006.285.09:53:42.43#ibcon#read 3, iclass 23, count 0 2006.285.09:53:42.43#ibcon#about to read 4, iclass 23, count 0 2006.285.09:53:42.43#ibcon#read 4, iclass 23, count 0 2006.285.09:53:42.43#ibcon#about to read 5, iclass 23, count 0 2006.285.09:53:42.43#ibcon#read 5, iclass 23, count 0 2006.285.09:53:42.43#ibcon#about to read 6, iclass 23, count 0 2006.285.09:53:42.43#ibcon#read 6, iclass 23, count 0 2006.285.09:53:42.43#ibcon#end of sib2, iclass 23, count 0 2006.285.09:53:42.43#ibcon#*after write, iclass 23, count 0 2006.285.09:53:42.43#ibcon#*before return 0, iclass 23, count 0 2006.285.09:53:42.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:53:42.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.09:53:42.43#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.09:53:42.43#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.09:53:42.43$vck44/vb=2,5 2006.285.09:53:42.43#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.09:53:42.43#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.09:53:42.43#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:42.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:53:42.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:53:42.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:53:42.49#ibcon#enter wrdev, iclass 25, count 2 2006.285.09:53:42.49#ibcon#first serial, iclass 25, count 2 2006.285.09:53:42.49#ibcon#enter sib2, iclass 25, count 2 2006.285.09:53:42.49#ibcon#flushed, iclass 25, count 2 2006.285.09:53:42.49#ibcon#about to write, iclass 25, count 2 2006.285.09:53:42.49#ibcon#wrote, iclass 25, count 2 2006.285.09:53:42.49#ibcon#about to read 3, iclass 25, count 2 2006.285.09:53:42.51#ibcon#read 3, iclass 25, count 2 2006.285.09:53:42.51#ibcon#about to read 4, iclass 25, count 2 2006.285.09:53:42.51#ibcon#read 4, iclass 25, count 2 2006.285.09:53:42.51#ibcon#about to read 5, iclass 25, count 2 2006.285.09:53:42.51#ibcon#read 5, iclass 25, count 2 2006.285.09:53:42.51#ibcon#about to read 6, iclass 25, count 2 2006.285.09:53:42.51#ibcon#read 6, iclass 25, count 2 2006.285.09:53:42.51#ibcon#end of sib2, iclass 25, count 2 2006.285.09:53:42.51#ibcon#*mode == 0, iclass 25, count 2 2006.285.09:53:42.51#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.09:53:42.51#ibcon#[27=AT02-05\r\n] 2006.285.09:53:42.51#ibcon#*before write, iclass 25, count 2 2006.285.09:53:42.51#ibcon#enter sib2, iclass 25, count 2 2006.285.09:53:42.51#ibcon#flushed, iclass 25, count 2 2006.285.09:53:42.51#ibcon#about to write, iclass 25, count 2 2006.285.09:53:42.51#ibcon#wrote, iclass 25, count 2 2006.285.09:53:42.51#ibcon#about to read 3, iclass 25, count 2 2006.285.09:53:42.54#ibcon#read 3, iclass 25, count 2 2006.285.09:53:42.54#ibcon#about to read 4, iclass 25, count 2 2006.285.09:53:42.54#ibcon#read 4, iclass 25, count 2 2006.285.09:53:42.54#ibcon#about to read 5, iclass 25, count 2 2006.285.09:53:42.54#ibcon#read 5, iclass 25, count 2 2006.285.09:53:42.54#ibcon#about to read 6, iclass 25, count 2 2006.285.09:53:42.54#ibcon#read 6, iclass 25, count 2 2006.285.09:53:42.54#ibcon#end of sib2, iclass 25, count 2 2006.285.09:53:42.54#ibcon#*after write, iclass 25, count 2 2006.285.09:53:42.54#ibcon#*before return 0, iclass 25, count 2 2006.285.09:53:42.54#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:53:42.54#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.09:53:42.54#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.09:53:42.54#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:42.54#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:53:42.66#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:53:42.66#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:53:42.66#ibcon#enter wrdev, iclass 25, count 0 2006.285.09:53:42.66#ibcon#first serial, iclass 25, count 0 2006.285.09:53:42.66#ibcon#enter sib2, iclass 25, count 0 2006.285.09:53:42.66#ibcon#flushed, iclass 25, count 0 2006.285.09:53:42.66#ibcon#about to write, iclass 25, count 0 2006.285.09:53:42.66#ibcon#wrote, iclass 25, count 0 2006.285.09:53:42.66#ibcon#about to read 3, iclass 25, count 0 2006.285.09:53:42.68#ibcon#read 3, iclass 25, count 0 2006.285.09:53:42.68#ibcon#about to read 4, iclass 25, count 0 2006.285.09:53:42.68#ibcon#read 4, iclass 25, count 0 2006.285.09:53:42.68#ibcon#about to read 5, iclass 25, count 0 2006.285.09:53:42.68#ibcon#read 5, iclass 25, count 0 2006.285.09:53:42.68#ibcon#about to read 6, iclass 25, count 0 2006.285.09:53:42.68#ibcon#read 6, iclass 25, count 0 2006.285.09:53:42.68#ibcon#end of sib2, iclass 25, count 0 2006.285.09:53:42.68#ibcon#*mode == 0, iclass 25, count 0 2006.285.09:53:42.68#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.09:53:42.68#ibcon#[27=USB\r\n] 2006.285.09:53:42.68#ibcon#*before write, iclass 25, count 0 2006.285.09:53:42.68#ibcon#enter sib2, iclass 25, count 0 2006.285.09:53:42.68#ibcon#flushed, iclass 25, count 0 2006.285.09:53:42.68#ibcon#about to write, iclass 25, count 0 2006.285.09:53:42.68#ibcon#wrote, iclass 25, count 0 2006.285.09:53:42.68#ibcon#about to read 3, iclass 25, count 0 2006.285.09:53:42.71#ibcon#read 3, iclass 25, count 0 2006.285.09:53:42.71#ibcon#about to read 4, iclass 25, count 0 2006.285.09:53:42.71#ibcon#read 4, iclass 25, count 0 2006.285.09:53:42.71#ibcon#about to read 5, iclass 25, count 0 2006.285.09:53:42.71#ibcon#read 5, iclass 25, count 0 2006.285.09:53:42.71#ibcon#about to read 6, iclass 25, count 0 2006.285.09:53:42.71#ibcon#read 6, iclass 25, count 0 2006.285.09:53:42.71#ibcon#end of sib2, iclass 25, count 0 2006.285.09:53:42.71#ibcon#*after write, iclass 25, count 0 2006.285.09:53:42.71#ibcon#*before return 0, iclass 25, count 0 2006.285.09:53:42.71#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:53:42.71#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.09:53:42.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.09:53:42.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.09:53:42.71$vck44/vblo=3,649.99 2006.285.09:53:42.71#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.09:53:42.71#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.09:53:42.71#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:42.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:53:42.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:53:42.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:53:42.71#ibcon#enter wrdev, iclass 27, count 0 2006.285.09:53:42.71#ibcon#first serial, iclass 27, count 0 2006.285.09:53:42.71#ibcon#enter sib2, iclass 27, count 0 2006.285.09:53:42.71#ibcon#flushed, iclass 27, count 0 2006.285.09:53:42.71#ibcon#about to write, iclass 27, count 0 2006.285.09:53:42.71#ibcon#wrote, iclass 27, count 0 2006.285.09:53:42.71#ibcon#about to read 3, iclass 27, count 0 2006.285.09:53:42.73#ibcon#read 3, iclass 27, count 0 2006.285.09:53:42.73#ibcon#about to read 4, iclass 27, count 0 2006.285.09:53:42.73#ibcon#read 4, iclass 27, count 0 2006.285.09:53:42.73#ibcon#about to read 5, iclass 27, count 0 2006.285.09:53:42.73#ibcon#read 5, iclass 27, count 0 2006.285.09:53:42.73#ibcon#about to read 6, iclass 27, count 0 2006.285.09:53:42.73#ibcon#read 6, iclass 27, count 0 2006.285.09:53:42.73#ibcon#end of sib2, iclass 27, count 0 2006.285.09:53:42.73#ibcon#*mode == 0, iclass 27, count 0 2006.285.09:53:42.73#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.09:53:42.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:53:42.73#ibcon#*before write, iclass 27, count 0 2006.285.09:53:42.73#ibcon#enter sib2, iclass 27, count 0 2006.285.09:53:42.73#ibcon#flushed, iclass 27, count 0 2006.285.09:53:42.73#ibcon#about to write, iclass 27, count 0 2006.285.09:53:42.73#ibcon#wrote, iclass 27, count 0 2006.285.09:53:42.73#ibcon#about to read 3, iclass 27, count 0 2006.285.09:53:42.77#ibcon#read 3, iclass 27, count 0 2006.285.09:53:42.77#ibcon#about to read 4, iclass 27, count 0 2006.285.09:53:42.77#ibcon#read 4, iclass 27, count 0 2006.285.09:53:42.77#ibcon#about to read 5, iclass 27, count 0 2006.285.09:53:42.77#ibcon#read 5, iclass 27, count 0 2006.285.09:53:42.77#ibcon#about to read 6, iclass 27, count 0 2006.285.09:53:42.77#ibcon#read 6, iclass 27, count 0 2006.285.09:53:42.77#ibcon#end of sib2, iclass 27, count 0 2006.285.09:53:42.77#ibcon#*after write, iclass 27, count 0 2006.285.09:53:42.77#ibcon#*before return 0, iclass 27, count 0 2006.285.09:53:42.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:53:42.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.09:53:42.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.09:53:42.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.09:53:42.77$vck44/vb=3,4 2006.285.09:53:42.77#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.09:53:42.77#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.09:53:42.77#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:42.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:53:42.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:53:42.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:53:42.83#ibcon#enter wrdev, iclass 29, count 2 2006.285.09:53:42.83#ibcon#first serial, iclass 29, count 2 2006.285.09:53:42.83#ibcon#enter sib2, iclass 29, count 2 2006.285.09:53:42.83#ibcon#flushed, iclass 29, count 2 2006.285.09:53:42.83#ibcon#about to write, iclass 29, count 2 2006.285.09:53:42.83#ibcon#wrote, iclass 29, count 2 2006.285.09:53:42.83#ibcon#about to read 3, iclass 29, count 2 2006.285.09:53:42.85#ibcon#read 3, iclass 29, count 2 2006.285.09:53:42.85#ibcon#about to read 4, iclass 29, count 2 2006.285.09:53:42.85#ibcon#read 4, iclass 29, count 2 2006.285.09:53:42.85#ibcon#about to read 5, iclass 29, count 2 2006.285.09:53:42.85#ibcon#read 5, iclass 29, count 2 2006.285.09:53:42.85#ibcon#about to read 6, iclass 29, count 2 2006.285.09:53:42.85#ibcon#read 6, iclass 29, count 2 2006.285.09:53:42.85#ibcon#end of sib2, iclass 29, count 2 2006.285.09:53:42.85#ibcon#*mode == 0, iclass 29, count 2 2006.285.09:53:42.85#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.09:53:42.85#ibcon#[27=AT03-04\r\n] 2006.285.09:53:42.85#ibcon#*before write, iclass 29, count 2 2006.285.09:53:42.85#ibcon#enter sib2, iclass 29, count 2 2006.285.09:53:42.85#ibcon#flushed, iclass 29, count 2 2006.285.09:53:42.85#ibcon#about to write, iclass 29, count 2 2006.285.09:53:42.85#ibcon#wrote, iclass 29, count 2 2006.285.09:53:42.85#ibcon#about to read 3, iclass 29, count 2 2006.285.09:53:42.88#ibcon#read 3, iclass 29, count 2 2006.285.09:53:42.88#ibcon#about to read 4, iclass 29, count 2 2006.285.09:53:42.88#ibcon#read 4, iclass 29, count 2 2006.285.09:53:42.88#ibcon#about to read 5, iclass 29, count 2 2006.285.09:53:42.88#ibcon#read 5, iclass 29, count 2 2006.285.09:53:42.88#ibcon#about to read 6, iclass 29, count 2 2006.285.09:53:42.88#ibcon#read 6, iclass 29, count 2 2006.285.09:53:42.88#ibcon#end of sib2, iclass 29, count 2 2006.285.09:53:42.88#ibcon#*after write, iclass 29, count 2 2006.285.09:53:42.88#ibcon#*before return 0, iclass 29, count 2 2006.285.09:53:42.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:53:42.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.09:53:42.88#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.09:53:42.88#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:42.88#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:53:43.00#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:53:43.00#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:53:43.00#ibcon#enter wrdev, iclass 29, count 0 2006.285.09:53:43.00#ibcon#first serial, iclass 29, count 0 2006.285.09:53:43.00#ibcon#enter sib2, iclass 29, count 0 2006.285.09:53:43.00#ibcon#flushed, iclass 29, count 0 2006.285.09:53:43.00#ibcon#about to write, iclass 29, count 0 2006.285.09:53:43.00#ibcon#wrote, iclass 29, count 0 2006.285.09:53:43.00#ibcon#about to read 3, iclass 29, count 0 2006.285.09:53:43.02#ibcon#read 3, iclass 29, count 0 2006.285.09:53:43.02#ibcon#about to read 4, iclass 29, count 0 2006.285.09:53:43.02#ibcon#read 4, iclass 29, count 0 2006.285.09:53:43.02#ibcon#about to read 5, iclass 29, count 0 2006.285.09:53:43.02#ibcon#read 5, iclass 29, count 0 2006.285.09:53:43.02#ibcon#about to read 6, iclass 29, count 0 2006.285.09:53:43.02#ibcon#read 6, iclass 29, count 0 2006.285.09:53:43.02#ibcon#end of sib2, iclass 29, count 0 2006.285.09:53:43.02#ibcon#*mode == 0, iclass 29, count 0 2006.285.09:53:43.02#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.09:53:43.02#ibcon#[27=USB\r\n] 2006.285.09:53:43.02#ibcon#*before write, iclass 29, count 0 2006.285.09:53:43.02#ibcon#enter sib2, iclass 29, count 0 2006.285.09:53:43.02#ibcon#flushed, iclass 29, count 0 2006.285.09:53:43.02#ibcon#about to write, iclass 29, count 0 2006.285.09:53:43.02#ibcon#wrote, iclass 29, count 0 2006.285.09:53:43.02#ibcon#about to read 3, iclass 29, count 0 2006.285.09:53:43.05#ibcon#read 3, iclass 29, count 0 2006.285.09:53:43.05#ibcon#about to read 4, iclass 29, count 0 2006.285.09:53:43.05#ibcon#read 4, iclass 29, count 0 2006.285.09:53:43.05#ibcon#about to read 5, iclass 29, count 0 2006.285.09:53:43.05#ibcon#read 5, iclass 29, count 0 2006.285.09:53:43.05#ibcon#about to read 6, iclass 29, count 0 2006.285.09:53:43.05#ibcon#read 6, iclass 29, count 0 2006.285.09:53:43.05#ibcon#end of sib2, iclass 29, count 0 2006.285.09:53:43.05#ibcon#*after write, iclass 29, count 0 2006.285.09:53:43.05#ibcon#*before return 0, iclass 29, count 0 2006.285.09:53:43.05#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:53:43.05#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.09:53:43.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.09:53:43.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.09:53:43.05$vck44/vblo=4,679.99 2006.285.09:53:43.05#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.09:53:43.05#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.09:53:43.05#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:43.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:53:43.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:53:43.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:53:43.05#ibcon#enter wrdev, iclass 31, count 0 2006.285.09:53:43.05#ibcon#first serial, iclass 31, count 0 2006.285.09:53:43.05#ibcon#enter sib2, iclass 31, count 0 2006.285.09:53:43.05#ibcon#flushed, iclass 31, count 0 2006.285.09:53:43.05#ibcon#about to write, iclass 31, count 0 2006.285.09:53:43.05#ibcon#wrote, iclass 31, count 0 2006.285.09:53:43.05#ibcon#about to read 3, iclass 31, count 0 2006.285.09:53:43.07#ibcon#read 3, iclass 31, count 0 2006.285.09:53:43.07#ibcon#about to read 4, iclass 31, count 0 2006.285.09:53:43.07#ibcon#read 4, iclass 31, count 0 2006.285.09:53:43.07#ibcon#about to read 5, iclass 31, count 0 2006.285.09:53:43.07#ibcon#read 5, iclass 31, count 0 2006.285.09:53:43.07#ibcon#about to read 6, iclass 31, count 0 2006.285.09:53:43.07#ibcon#read 6, iclass 31, count 0 2006.285.09:53:43.07#ibcon#end of sib2, iclass 31, count 0 2006.285.09:53:43.07#ibcon#*mode == 0, iclass 31, count 0 2006.285.09:53:43.07#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.09:53:43.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:53:43.07#ibcon#*before write, iclass 31, count 0 2006.285.09:53:43.07#ibcon#enter sib2, iclass 31, count 0 2006.285.09:53:43.07#ibcon#flushed, iclass 31, count 0 2006.285.09:53:43.07#ibcon#about to write, iclass 31, count 0 2006.285.09:53:43.07#ibcon#wrote, iclass 31, count 0 2006.285.09:53:43.07#ibcon#about to read 3, iclass 31, count 0 2006.285.09:53:43.11#ibcon#read 3, iclass 31, count 0 2006.285.09:53:43.11#ibcon#about to read 4, iclass 31, count 0 2006.285.09:53:43.11#ibcon#read 4, iclass 31, count 0 2006.285.09:53:43.11#ibcon#about to read 5, iclass 31, count 0 2006.285.09:53:43.11#ibcon#read 5, iclass 31, count 0 2006.285.09:53:43.11#ibcon#about to read 6, iclass 31, count 0 2006.285.09:53:43.11#ibcon#read 6, iclass 31, count 0 2006.285.09:53:43.11#ibcon#end of sib2, iclass 31, count 0 2006.285.09:53:43.11#ibcon#*after write, iclass 31, count 0 2006.285.09:53:43.11#ibcon#*before return 0, iclass 31, count 0 2006.285.09:53:43.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:53:43.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.09:53:43.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.09:53:43.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.09:53:43.11$vck44/vb=4,5 2006.285.09:53:43.11#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.09:53:43.11#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.09:53:43.11#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:43.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:53:43.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:53:43.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:53:43.17#ibcon#enter wrdev, iclass 33, count 2 2006.285.09:53:43.17#ibcon#first serial, iclass 33, count 2 2006.285.09:53:43.17#ibcon#enter sib2, iclass 33, count 2 2006.285.09:53:43.17#ibcon#flushed, iclass 33, count 2 2006.285.09:53:43.17#ibcon#about to write, iclass 33, count 2 2006.285.09:53:43.17#ibcon#wrote, iclass 33, count 2 2006.285.09:53:43.17#ibcon#about to read 3, iclass 33, count 2 2006.285.09:53:43.19#ibcon#read 3, iclass 33, count 2 2006.285.09:53:43.19#ibcon#about to read 4, iclass 33, count 2 2006.285.09:53:43.19#ibcon#read 4, iclass 33, count 2 2006.285.09:53:43.19#ibcon#about to read 5, iclass 33, count 2 2006.285.09:53:43.19#ibcon#read 5, iclass 33, count 2 2006.285.09:53:43.19#ibcon#about to read 6, iclass 33, count 2 2006.285.09:53:43.19#ibcon#read 6, iclass 33, count 2 2006.285.09:53:43.19#ibcon#end of sib2, iclass 33, count 2 2006.285.09:53:43.19#ibcon#*mode == 0, iclass 33, count 2 2006.285.09:53:43.19#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.09:53:43.19#ibcon#[27=AT04-05\r\n] 2006.285.09:53:43.19#ibcon#*before write, iclass 33, count 2 2006.285.09:53:43.19#ibcon#enter sib2, iclass 33, count 2 2006.285.09:53:43.19#ibcon#flushed, iclass 33, count 2 2006.285.09:53:43.19#ibcon#about to write, iclass 33, count 2 2006.285.09:53:43.19#ibcon#wrote, iclass 33, count 2 2006.285.09:53:43.19#ibcon#about to read 3, iclass 33, count 2 2006.285.09:53:43.22#ibcon#read 3, iclass 33, count 2 2006.285.09:53:43.22#ibcon#about to read 4, iclass 33, count 2 2006.285.09:53:43.22#ibcon#read 4, iclass 33, count 2 2006.285.09:53:43.22#ibcon#about to read 5, iclass 33, count 2 2006.285.09:53:43.22#ibcon#read 5, iclass 33, count 2 2006.285.09:53:43.22#ibcon#about to read 6, iclass 33, count 2 2006.285.09:53:43.22#ibcon#read 6, iclass 33, count 2 2006.285.09:53:43.22#ibcon#end of sib2, iclass 33, count 2 2006.285.09:53:43.22#ibcon#*after write, iclass 33, count 2 2006.285.09:53:43.22#ibcon#*before return 0, iclass 33, count 2 2006.285.09:53:43.22#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:53:43.22#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.09:53:43.22#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.09:53:43.22#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:43.22#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:53:43.34#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:53:43.34#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:53:43.34#ibcon#enter wrdev, iclass 33, count 0 2006.285.09:53:43.34#ibcon#first serial, iclass 33, count 0 2006.285.09:53:43.34#ibcon#enter sib2, iclass 33, count 0 2006.285.09:53:43.34#ibcon#flushed, iclass 33, count 0 2006.285.09:53:43.34#ibcon#about to write, iclass 33, count 0 2006.285.09:53:43.34#ibcon#wrote, iclass 33, count 0 2006.285.09:53:43.34#ibcon#about to read 3, iclass 33, count 0 2006.285.09:53:43.36#ibcon#read 3, iclass 33, count 0 2006.285.09:53:43.36#ibcon#about to read 4, iclass 33, count 0 2006.285.09:53:43.36#ibcon#read 4, iclass 33, count 0 2006.285.09:53:43.36#ibcon#about to read 5, iclass 33, count 0 2006.285.09:53:43.36#ibcon#read 5, iclass 33, count 0 2006.285.09:53:43.36#ibcon#about to read 6, iclass 33, count 0 2006.285.09:53:43.36#ibcon#read 6, iclass 33, count 0 2006.285.09:53:43.36#ibcon#end of sib2, iclass 33, count 0 2006.285.09:53:43.36#ibcon#*mode == 0, iclass 33, count 0 2006.285.09:53:43.36#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.09:53:43.36#ibcon#[27=USB\r\n] 2006.285.09:53:43.36#ibcon#*before write, iclass 33, count 0 2006.285.09:53:43.36#ibcon#enter sib2, iclass 33, count 0 2006.285.09:53:43.36#ibcon#flushed, iclass 33, count 0 2006.285.09:53:43.36#ibcon#about to write, iclass 33, count 0 2006.285.09:53:43.36#ibcon#wrote, iclass 33, count 0 2006.285.09:53:43.36#ibcon#about to read 3, iclass 33, count 0 2006.285.09:53:43.39#ibcon#read 3, iclass 33, count 0 2006.285.09:53:43.39#ibcon#about to read 4, iclass 33, count 0 2006.285.09:53:43.39#ibcon#read 4, iclass 33, count 0 2006.285.09:53:43.39#ibcon#about to read 5, iclass 33, count 0 2006.285.09:53:43.39#ibcon#read 5, iclass 33, count 0 2006.285.09:53:43.39#ibcon#about to read 6, iclass 33, count 0 2006.285.09:53:43.39#ibcon#read 6, iclass 33, count 0 2006.285.09:53:43.39#ibcon#end of sib2, iclass 33, count 0 2006.285.09:53:43.39#ibcon#*after write, iclass 33, count 0 2006.285.09:53:43.39#ibcon#*before return 0, iclass 33, count 0 2006.285.09:53:43.39#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:53:43.39#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.09:53:43.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.09:53:43.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.09:53:43.39$vck44/vblo=5,709.99 2006.285.09:53:43.39#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.09:53:43.39#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.09:53:43.39#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:43.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:53:43.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:53:43.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:53:43.39#ibcon#enter wrdev, iclass 35, count 0 2006.285.09:53:43.39#ibcon#first serial, iclass 35, count 0 2006.285.09:53:43.39#ibcon#enter sib2, iclass 35, count 0 2006.285.09:53:43.39#ibcon#flushed, iclass 35, count 0 2006.285.09:53:43.39#ibcon#about to write, iclass 35, count 0 2006.285.09:53:43.39#ibcon#wrote, iclass 35, count 0 2006.285.09:53:43.39#ibcon#about to read 3, iclass 35, count 0 2006.285.09:53:43.41#ibcon#read 3, iclass 35, count 0 2006.285.09:53:43.41#ibcon#about to read 4, iclass 35, count 0 2006.285.09:53:43.41#ibcon#read 4, iclass 35, count 0 2006.285.09:53:43.41#ibcon#about to read 5, iclass 35, count 0 2006.285.09:53:43.41#ibcon#read 5, iclass 35, count 0 2006.285.09:53:43.41#ibcon#about to read 6, iclass 35, count 0 2006.285.09:53:43.41#ibcon#read 6, iclass 35, count 0 2006.285.09:53:43.41#ibcon#end of sib2, iclass 35, count 0 2006.285.09:53:43.41#ibcon#*mode == 0, iclass 35, count 0 2006.285.09:53:43.41#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.09:53:43.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:53:43.41#ibcon#*before write, iclass 35, count 0 2006.285.09:53:43.41#ibcon#enter sib2, iclass 35, count 0 2006.285.09:53:43.41#ibcon#flushed, iclass 35, count 0 2006.285.09:53:43.41#ibcon#about to write, iclass 35, count 0 2006.285.09:53:43.41#ibcon#wrote, iclass 35, count 0 2006.285.09:53:43.41#ibcon#about to read 3, iclass 35, count 0 2006.285.09:53:43.45#ibcon#read 3, iclass 35, count 0 2006.285.09:53:43.45#ibcon#about to read 4, iclass 35, count 0 2006.285.09:53:43.45#ibcon#read 4, iclass 35, count 0 2006.285.09:53:43.45#ibcon#about to read 5, iclass 35, count 0 2006.285.09:53:43.45#ibcon#read 5, iclass 35, count 0 2006.285.09:53:43.45#ibcon#about to read 6, iclass 35, count 0 2006.285.09:53:43.45#ibcon#read 6, iclass 35, count 0 2006.285.09:53:43.45#ibcon#end of sib2, iclass 35, count 0 2006.285.09:53:43.45#ibcon#*after write, iclass 35, count 0 2006.285.09:53:43.45#ibcon#*before return 0, iclass 35, count 0 2006.285.09:53:43.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:53:43.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.09:53:43.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.09:53:43.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.09:53:43.45$vck44/vb=5,4 2006.285.09:53:43.45#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.09:53:43.45#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.09:53:43.45#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:43.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:53:43.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:53:43.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:53:43.51#ibcon#enter wrdev, iclass 37, count 2 2006.285.09:53:43.51#ibcon#first serial, iclass 37, count 2 2006.285.09:53:43.51#ibcon#enter sib2, iclass 37, count 2 2006.285.09:53:43.51#ibcon#flushed, iclass 37, count 2 2006.285.09:53:43.51#ibcon#about to write, iclass 37, count 2 2006.285.09:53:43.51#ibcon#wrote, iclass 37, count 2 2006.285.09:53:43.51#ibcon#about to read 3, iclass 37, count 2 2006.285.09:53:43.53#ibcon#read 3, iclass 37, count 2 2006.285.09:53:43.53#ibcon#about to read 4, iclass 37, count 2 2006.285.09:53:43.53#ibcon#read 4, iclass 37, count 2 2006.285.09:53:43.53#ibcon#about to read 5, iclass 37, count 2 2006.285.09:53:43.53#ibcon#read 5, iclass 37, count 2 2006.285.09:53:43.53#ibcon#about to read 6, iclass 37, count 2 2006.285.09:53:43.53#ibcon#read 6, iclass 37, count 2 2006.285.09:53:43.53#ibcon#end of sib2, iclass 37, count 2 2006.285.09:53:43.53#ibcon#*mode == 0, iclass 37, count 2 2006.285.09:53:43.53#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.09:53:43.53#ibcon#[27=AT05-04\r\n] 2006.285.09:53:43.53#ibcon#*before write, iclass 37, count 2 2006.285.09:53:43.53#ibcon#enter sib2, iclass 37, count 2 2006.285.09:53:43.53#ibcon#flushed, iclass 37, count 2 2006.285.09:53:43.53#ibcon#about to write, iclass 37, count 2 2006.285.09:53:43.53#ibcon#wrote, iclass 37, count 2 2006.285.09:53:43.53#ibcon#about to read 3, iclass 37, count 2 2006.285.09:53:43.56#ibcon#read 3, iclass 37, count 2 2006.285.09:53:43.56#ibcon#about to read 4, iclass 37, count 2 2006.285.09:53:43.56#ibcon#read 4, iclass 37, count 2 2006.285.09:53:43.56#ibcon#about to read 5, iclass 37, count 2 2006.285.09:53:43.56#ibcon#read 5, iclass 37, count 2 2006.285.09:53:43.56#ibcon#about to read 6, iclass 37, count 2 2006.285.09:53:43.56#ibcon#read 6, iclass 37, count 2 2006.285.09:53:43.56#ibcon#end of sib2, iclass 37, count 2 2006.285.09:53:43.56#ibcon#*after write, iclass 37, count 2 2006.285.09:53:43.56#ibcon#*before return 0, iclass 37, count 2 2006.285.09:53:43.56#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:53:43.56#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.09:53:43.56#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.09:53:43.56#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:43.56#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:53:43.68#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:53:43.68#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:53:43.68#ibcon#enter wrdev, iclass 37, count 0 2006.285.09:53:43.68#ibcon#first serial, iclass 37, count 0 2006.285.09:53:43.68#ibcon#enter sib2, iclass 37, count 0 2006.285.09:53:43.68#ibcon#flushed, iclass 37, count 0 2006.285.09:53:43.68#ibcon#about to write, iclass 37, count 0 2006.285.09:53:43.68#ibcon#wrote, iclass 37, count 0 2006.285.09:53:43.68#ibcon#about to read 3, iclass 37, count 0 2006.285.09:53:43.70#ibcon#read 3, iclass 37, count 0 2006.285.09:53:43.70#ibcon#about to read 4, iclass 37, count 0 2006.285.09:53:43.70#ibcon#read 4, iclass 37, count 0 2006.285.09:53:43.70#ibcon#about to read 5, iclass 37, count 0 2006.285.09:53:43.70#ibcon#read 5, iclass 37, count 0 2006.285.09:53:43.70#ibcon#about to read 6, iclass 37, count 0 2006.285.09:53:43.70#ibcon#read 6, iclass 37, count 0 2006.285.09:53:43.70#ibcon#end of sib2, iclass 37, count 0 2006.285.09:53:43.70#ibcon#*mode == 0, iclass 37, count 0 2006.285.09:53:43.70#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.09:53:43.70#ibcon#[27=USB\r\n] 2006.285.09:53:43.70#ibcon#*before write, iclass 37, count 0 2006.285.09:53:43.70#ibcon#enter sib2, iclass 37, count 0 2006.285.09:53:43.70#ibcon#flushed, iclass 37, count 0 2006.285.09:53:43.70#ibcon#about to write, iclass 37, count 0 2006.285.09:53:43.70#ibcon#wrote, iclass 37, count 0 2006.285.09:53:43.70#ibcon#about to read 3, iclass 37, count 0 2006.285.09:53:43.73#ibcon#read 3, iclass 37, count 0 2006.285.09:53:43.73#ibcon#about to read 4, iclass 37, count 0 2006.285.09:53:43.73#ibcon#read 4, iclass 37, count 0 2006.285.09:53:43.73#ibcon#about to read 5, iclass 37, count 0 2006.285.09:53:43.73#ibcon#read 5, iclass 37, count 0 2006.285.09:53:43.73#ibcon#about to read 6, iclass 37, count 0 2006.285.09:53:43.73#ibcon#read 6, iclass 37, count 0 2006.285.09:53:43.73#ibcon#end of sib2, iclass 37, count 0 2006.285.09:53:43.73#ibcon#*after write, iclass 37, count 0 2006.285.09:53:43.73#ibcon#*before return 0, iclass 37, count 0 2006.285.09:53:43.73#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:53:43.73#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.09:53:43.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.09:53:43.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.09:53:43.73$vck44/vblo=6,719.99 2006.285.09:53:43.73#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.09:53:43.73#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.09:53:43.73#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:43.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:53:43.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:53:43.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:53:43.73#ibcon#enter wrdev, iclass 39, count 0 2006.285.09:53:43.73#ibcon#first serial, iclass 39, count 0 2006.285.09:53:43.73#ibcon#enter sib2, iclass 39, count 0 2006.285.09:53:43.73#ibcon#flushed, iclass 39, count 0 2006.285.09:53:43.73#ibcon#about to write, iclass 39, count 0 2006.285.09:53:43.73#ibcon#wrote, iclass 39, count 0 2006.285.09:53:43.73#ibcon#about to read 3, iclass 39, count 0 2006.285.09:53:43.75#ibcon#read 3, iclass 39, count 0 2006.285.09:53:43.75#ibcon#about to read 4, iclass 39, count 0 2006.285.09:53:43.75#ibcon#read 4, iclass 39, count 0 2006.285.09:53:43.75#ibcon#about to read 5, iclass 39, count 0 2006.285.09:53:43.75#ibcon#read 5, iclass 39, count 0 2006.285.09:53:43.75#ibcon#about to read 6, iclass 39, count 0 2006.285.09:53:43.75#ibcon#read 6, iclass 39, count 0 2006.285.09:53:43.75#ibcon#end of sib2, iclass 39, count 0 2006.285.09:53:43.75#ibcon#*mode == 0, iclass 39, count 0 2006.285.09:53:43.75#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.09:53:43.75#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:53:43.75#ibcon#*before write, iclass 39, count 0 2006.285.09:53:43.75#ibcon#enter sib2, iclass 39, count 0 2006.285.09:53:43.75#ibcon#flushed, iclass 39, count 0 2006.285.09:53:43.75#ibcon#about to write, iclass 39, count 0 2006.285.09:53:43.75#ibcon#wrote, iclass 39, count 0 2006.285.09:53:43.75#ibcon#about to read 3, iclass 39, count 0 2006.285.09:53:43.79#ibcon#read 3, iclass 39, count 0 2006.285.09:53:43.79#ibcon#about to read 4, iclass 39, count 0 2006.285.09:53:43.79#ibcon#read 4, iclass 39, count 0 2006.285.09:53:43.79#ibcon#about to read 5, iclass 39, count 0 2006.285.09:53:43.79#ibcon#read 5, iclass 39, count 0 2006.285.09:53:43.79#ibcon#about to read 6, iclass 39, count 0 2006.285.09:53:43.79#ibcon#read 6, iclass 39, count 0 2006.285.09:53:43.79#ibcon#end of sib2, iclass 39, count 0 2006.285.09:53:43.79#ibcon#*after write, iclass 39, count 0 2006.285.09:53:43.79#ibcon#*before return 0, iclass 39, count 0 2006.285.09:53:43.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:53:43.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.09:53:43.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.09:53:43.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.09:53:43.79$vck44/vb=6,3 2006.285.09:53:43.79#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.09:53:43.79#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.09:53:43.79#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:43.79#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:53:43.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:53:43.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:53:43.85#ibcon#enter wrdev, iclass 3, count 2 2006.285.09:53:43.85#ibcon#first serial, iclass 3, count 2 2006.285.09:53:43.85#ibcon#enter sib2, iclass 3, count 2 2006.285.09:53:43.85#ibcon#flushed, iclass 3, count 2 2006.285.09:53:43.85#ibcon#about to write, iclass 3, count 2 2006.285.09:53:43.85#ibcon#wrote, iclass 3, count 2 2006.285.09:53:43.85#ibcon#about to read 3, iclass 3, count 2 2006.285.09:53:43.87#ibcon#read 3, iclass 3, count 2 2006.285.09:53:43.87#ibcon#about to read 4, iclass 3, count 2 2006.285.09:53:43.87#ibcon#read 4, iclass 3, count 2 2006.285.09:53:43.87#ibcon#about to read 5, iclass 3, count 2 2006.285.09:53:43.87#ibcon#read 5, iclass 3, count 2 2006.285.09:53:43.87#ibcon#about to read 6, iclass 3, count 2 2006.285.09:53:43.87#ibcon#read 6, iclass 3, count 2 2006.285.09:53:43.87#ibcon#end of sib2, iclass 3, count 2 2006.285.09:53:43.87#ibcon#*mode == 0, iclass 3, count 2 2006.285.09:53:43.87#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.09:53:43.87#ibcon#[27=AT06-03\r\n] 2006.285.09:53:43.87#ibcon#*before write, iclass 3, count 2 2006.285.09:53:43.87#ibcon#enter sib2, iclass 3, count 2 2006.285.09:53:43.87#ibcon#flushed, iclass 3, count 2 2006.285.09:53:43.87#ibcon#about to write, iclass 3, count 2 2006.285.09:53:43.87#ibcon#wrote, iclass 3, count 2 2006.285.09:53:43.87#ibcon#about to read 3, iclass 3, count 2 2006.285.09:53:43.90#ibcon#read 3, iclass 3, count 2 2006.285.09:53:43.90#ibcon#about to read 4, iclass 3, count 2 2006.285.09:53:43.90#ibcon#read 4, iclass 3, count 2 2006.285.09:53:43.90#ibcon#about to read 5, iclass 3, count 2 2006.285.09:53:43.90#ibcon#read 5, iclass 3, count 2 2006.285.09:53:43.90#ibcon#about to read 6, iclass 3, count 2 2006.285.09:53:43.90#ibcon#read 6, iclass 3, count 2 2006.285.09:53:43.90#ibcon#end of sib2, iclass 3, count 2 2006.285.09:53:43.90#ibcon#*after write, iclass 3, count 2 2006.285.09:53:43.90#ibcon#*before return 0, iclass 3, count 2 2006.285.09:53:43.90#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:53:43.90#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.09:53:43.90#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.09:53:43.90#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:43.90#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:53:44.02#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:53:44.02#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:53:44.02#ibcon#enter wrdev, iclass 3, count 0 2006.285.09:53:44.02#ibcon#first serial, iclass 3, count 0 2006.285.09:53:44.02#ibcon#enter sib2, iclass 3, count 0 2006.285.09:53:44.02#ibcon#flushed, iclass 3, count 0 2006.285.09:53:44.02#ibcon#about to write, iclass 3, count 0 2006.285.09:53:44.02#ibcon#wrote, iclass 3, count 0 2006.285.09:53:44.02#ibcon#about to read 3, iclass 3, count 0 2006.285.09:53:44.04#ibcon#read 3, iclass 3, count 0 2006.285.09:53:44.04#ibcon#about to read 4, iclass 3, count 0 2006.285.09:53:44.04#ibcon#read 4, iclass 3, count 0 2006.285.09:53:44.04#ibcon#about to read 5, iclass 3, count 0 2006.285.09:53:44.04#ibcon#read 5, iclass 3, count 0 2006.285.09:53:44.04#ibcon#about to read 6, iclass 3, count 0 2006.285.09:53:44.04#ibcon#read 6, iclass 3, count 0 2006.285.09:53:44.04#ibcon#end of sib2, iclass 3, count 0 2006.285.09:53:44.04#ibcon#*mode == 0, iclass 3, count 0 2006.285.09:53:44.04#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.09:53:44.04#ibcon#[27=USB\r\n] 2006.285.09:53:44.04#ibcon#*before write, iclass 3, count 0 2006.285.09:53:44.04#ibcon#enter sib2, iclass 3, count 0 2006.285.09:53:44.04#ibcon#flushed, iclass 3, count 0 2006.285.09:53:44.04#ibcon#about to write, iclass 3, count 0 2006.285.09:53:44.04#ibcon#wrote, iclass 3, count 0 2006.285.09:53:44.04#ibcon#about to read 3, iclass 3, count 0 2006.285.09:53:44.07#ibcon#read 3, iclass 3, count 0 2006.285.09:53:44.07#ibcon#about to read 4, iclass 3, count 0 2006.285.09:53:44.07#ibcon#read 4, iclass 3, count 0 2006.285.09:53:44.07#ibcon#about to read 5, iclass 3, count 0 2006.285.09:53:44.07#ibcon#read 5, iclass 3, count 0 2006.285.09:53:44.07#ibcon#about to read 6, iclass 3, count 0 2006.285.09:53:44.07#ibcon#read 6, iclass 3, count 0 2006.285.09:53:44.07#ibcon#end of sib2, iclass 3, count 0 2006.285.09:53:44.07#ibcon#*after write, iclass 3, count 0 2006.285.09:53:44.07#ibcon#*before return 0, iclass 3, count 0 2006.285.09:53:44.07#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:53:44.07#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.09:53:44.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.09:53:44.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.09:53:44.07$vck44/vblo=7,734.99 2006.285.09:53:44.07#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.09:53:44.07#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.09:53:44.07#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:44.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:53:44.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:53:44.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:53:44.07#ibcon#enter wrdev, iclass 5, count 0 2006.285.09:53:44.07#ibcon#first serial, iclass 5, count 0 2006.285.09:53:44.07#ibcon#enter sib2, iclass 5, count 0 2006.285.09:53:44.07#ibcon#flushed, iclass 5, count 0 2006.285.09:53:44.07#ibcon#about to write, iclass 5, count 0 2006.285.09:53:44.07#ibcon#wrote, iclass 5, count 0 2006.285.09:53:44.07#ibcon#about to read 3, iclass 5, count 0 2006.285.09:53:44.09#ibcon#read 3, iclass 5, count 0 2006.285.09:53:44.09#ibcon#about to read 4, iclass 5, count 0 2006.285.09:53:44.09#ibcon#read 4, iclass 5, count 0 2006.285.09:53:44.09#ibcon#about to read 5, iclass 5, count 0 2006.285.09:53:44.09#ibcon#read 5, iclass 5, count 0 2006.285.09:53:44.09#ibcon#about to read 6, iclass 5, count 0 2006.285.09:53:44.09#ibcon#read 6, iclass 5, count 0 2006.285.09:53:44.09#ibcon#end of sib2, iclass 5, count 0 2006.285.09:53:44.09#ibcon#*mode == 0, iclass 5, count 0 2006.285.09:53:44.09#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.09:53:44.09#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:53:44.09#ibcon#*before write, iclass 5, count 0 2006.285.09:53:44.09#ibcon#enter sib2, iclass 5, count 0 2006.285.09:53:44.09#ibcon#flushed, iclass 5, count 0 2006.285.09:53:44.09#ibcon#about to write, iclass 5, count 0 2006.285.09:53:44.09#ibcon#wrote, iclass 5, count 0 2006.285.09:53:44.09#ibcon#about to read 3, iclass 5, count 0 2006.285.09:53:44.13#ibcon#read 3, iclass 5, count 0 2006.285.09:53:44.13#ibcon#about to read 4, iclass 5, count 0 2006.285.09:53:44.13#ibcon#read 4, iclass 5, count 0 2006.285.09:53:44.13#ibcon#about to read 5, iclass 5, count 0 2006.285.09:53:44.13#ibcon#read 5, iclass 5, count 0 2006.285.09:53:44.13#ibcon#about to read 6, iclass 5, count 0 2006.285.09:53:44.13#ibcon#read 6, iclass 5, count 0 2006.285.09:53:44.13#ibcon#end of sib2, iclass 5, count 0 2006.285.09:53:44.13#ibcon#*after write, iclass 5, count 0 2006.285.09:53:44.13#ibcon#*before return 0, iclass 5, count 0 2006.285.09:53:44.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:53:44.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.09:53:44.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.09:53:44.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.09:53:44.13$vck44/vb=7,4 2006.285.09:53:44.13#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.09:53:44.13#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.09:53:44.13#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:44.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:53:44.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:53:44.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:53:44.19#ibcon#enter wrdev, iclass 7, count 2 2006.285.09:53:44.19#ibcon#first serial, iclass 7, count 2 2006.285.09:53:44.19#ibcon#enter sib2, iclass 7, count 2 2006.285.09:53:44.19#ibcon#flushed, iclass 7, count 2 2006.285.09:53:44.19#ibcon#about to write, iclass 7, count 2 2006.285.09:53:44.19#ibcon#wrote, iclass 7, count 2 2006.285.09:53:44.19#ibcon#about to read 3, iclass 7, count 2 2006.285.09:53:44.21#ibcon#read 3, iclass 7, count 2 2006.285.09:53:44.21#ibcon#about to read 4, iclass 7, count 2 2006.285.09:53:44.21#ibcon#read 4, iclass 7, count 2 2006.285.09:53:44.21#ibcon#about to read 5, iclass 7, count 2 2006.285.09:53:44.21#ibcon#read 5, iclass 7, count 2 2006.285.09:53:44.21#ibcon#about to read 6, iclass 7, count 2 2006.285.09:53:44.21#ibcon#read 6, iclass 7, count 2 2006.285.09:53:44.21#ibcon#end of sib2, iclass 7, count 2 2006.285.09:53:44.21#ibcon#*mode == 0, iclass 7, count 2 2006.285.09:53:44.21#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.09:53:44.21#ibcon#[27=AT07-04\r\n] 2006.285.09:53:44.21#ibcon#*before write, iclass 7, count 2 2006.285.09:53:44.21#ibcon#enter sib2, iclass 7, count 2 2006.285.09:53:44.21#ibcon#flushed, iclass 7, count 2 2006.285.09:53:44.21#ibcon#about to write, iclass 7, count 2 2006.285.09:53:44.21#ibcon#wrote, iclass 7, count 2 2006.285.09:53:44.21#ibcon#about to read 3, iclass 7, count 2 2006.285.09:53:44.24#ibcon#read 3, iclass 7, count 2 2006.285.09:53:44.24#ibcon#about to read 4, iclass 7, count 2 2006.285.09:53:44.24#ibcon#read 4, iclass 7, count 2 2006.285.09:53:44.24#ibcon#about to read 5, iclass 7, count 2 2006.285.09:53:44.24#ibcon#read 5, iclass 7, count 2 2006.285.09:53:44.24#ibcon#about to read 6, iclass 7, count 2 2006.285.09:53:44.24#ibcon#read 6, iclass 7, count 2 2006.285.09:53:44.24#ibcon#end of sib2, iclass 7, count 2 2006.285.09:53:44.24#ibcon#*after write, iclass 7, count 2 2006.285.09:53:44.24#ibcon#*before return 0, iclass 7, count 2 2006.285.09:53:44.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:53:44.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.09:53:44.24#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.09:53:44.24#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:44.24#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:53:44.36#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:53:44.36#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:53:44.36#ibcon#enter wrdev, iclass 7, count 0 2006.285.09:53:44.36#ibcon#first serial, iclass 7, count 0 2006.285.09:53:44.36#ibcon#enter sib2, iclass 7, count 0 2006.285.09:53:44.36#ibcon#flushed, iclass 7, count 0 2006.285.09:53:44.36#ibcon#about to write, iclass 7, count 0 2006.285.09:53:44.36#ibcon#wrote, iclass 7, count 0 2006.285.09:53:44.36#ibcon#about to read 3, iclass 7, count 0 2006.285.09:53:44.38#ibcon#read 3, iclass 7, count 0 2006.285.09:53:44.38#ibcon#about to read 4, iclass 7, count 0 2006.285.09:53:44.38#ibcon#read 4, iclass 7, count 0 2006.285.09:53:44.38#ibcon#about to read 5, iclass 7, count 0 2006.285.09:53:44.38#ibcon#read 5, iclass 7, count 0 2006.285.09:53:44.38#ibcon#about to read 6, iclass 7, count 0 2006.285.09:53:44.38#ibcon#read 6, iclass 7, count 0 2006.285.09:53:44.38#ibcon#end of sib2, iclass 7, count 0 2006.285.09:53:44.38#ibcon#*mode == 0, iclass 7, count 0 2006.285.09:53:44.38#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.09:53:44.38#ibcon#[27=USB\r\n] 2006.285.09:53:44.38#ibcon#*before write, iclass 7, count 0 2006.285.09:53:44.38#ibcon#enter sib2, iclass 7, count 0 2006.285.09:53:44.38#ibcon#flushed, iclass 7, count 0 2006.285.09:53:44.38#ibcon#about to write, iclass 7, count 0 2006.285.09:53:44.38#ibcon#wrote, iclass 7, count 0 2006.285.09:53:44.38#ibcon#about to read 3, iclass 7, count 0 2006.285.09:53:44.41#ibcon#read 3, iclass 7, count 0 2006.285.09:53:44.41#ibcon#about to read 4, iclass 7, count 0 2006.285.09:53:44.41#ibcon#read 4, iclass 7, count 0 2006.285.09:53:44.41#ibcon#about to read 5, iclass 7, count 0 2006.285.09:53:44.41#ibcon#read 5, iclass 7, count 0 2006.285.09:53:44.41#ibcon#about to read 6, iclass 7, count 0 2006.285.09:53:44.41#ibcon#read 6, iclass 7, count 0 2006.285.09:53:44.41#ibcon#end of sib2, iclass 7, count 0 2006.285.09:53:44.41#ibcon#*after write, iclass 7, count 0 2006.285.09:53:44.41#ibcon#*before return 0, iclass 7, count 0 2006.285.09:53:44.41#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:53:44.41#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.09:53:44.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.09:53:44.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.09:53:44.41$vck44/vblo=8,744.99 2006.285.09:53:44.41#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.09:53:44.41#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.09:53:44.41#ibcon#ireg 17 cls_cnt 0 2006.285.09:53:44.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:53:44.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:53:44.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:53:44.41#ibcon#enter wrdev, iclass 11, count 0 2006.285.09:53:44.41#ibcon#first serial, iclass 11, count 0 2006.285.09:53:44.41#ibcon#enter sib2, iclass 11, count 0 2006.285.09:53:44.41#ibcon#flushed, iclass 11, count 0 2006.285.09:53:44.41#ibcon#about to write, iclass 11, count 0 2006.285.09:53:44.41#ibcon#wrote, iclass 11, count 0 2006.285.09:53:44.41#ibcon#about to read 3, iclass 11, count 0 2006.285.09:53:44.43#ibcon#read 3, iclass 11, count 0 2006.285.09:53:44.43#ibcon#about to read 4, iclass 11, count 0 2006.285.09:53:44.43#ibcon#read 4, iclass 11, count 0 2006.285.09:53:44.43#ibcon#about to read 5, iclass 11, count 0 2006.285.09:53:44.43#ibcon#read 5, iclass 11, count 0 2006.285.09:53:44.43#ibcon#about to read 6, iclass 11, count 0 2006.285.09:53:44.43#ibcon#read 6, iclass 11, count 0 2006.285.09:53:44.43#ibcon#end of sib2, iclass 11, count 0 2006.285.09:53:44.43#ibcon#*mode == 0, iclass 11, count 0 2006.285.09:53:44.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.09:53:44.43#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:53:44.43#ibcon#*before write, iclass 11, count 0 2006.285.09:53:44.43#ibcon#enter sib2, iclass 11, count 0 2006.285.09:53:44.43#ibcon#flushed, iclass 11, count 0 2006.285.09:53:44.43#ibcon#about to write, iclass 11, count 0 2006.285.09:53:44.43#ibcon#wrote, iclass 11, count 0 2006.285.09:53:44.43#ibcon#about to read 3, iclass 11, count 0 2006.285.09:53:44.47#ibcon#read 3, iclass 11, count 0 2006.285.09:53:44.47#ibcon#about to read 4, iclass 11, count 0 2006.285.09:53:44.47#ibcon#read 4, iclass 11, count 0 2006.285.09:53:44.47#ibcon#about to read 5, iclass 11, count 0 2006.285.09:53:44.47#ibcon#read 5, iclass 11, count 0 2006.285.09:53:44.47#ibcon#about to read 6, iclass 11, count 0 2006.285.09:53:44.47#ibcon#read 6, iclass 11, count 0 2006.285.09:53:44.47#ibcon#end of sib2, iclass 11, count 0 2006.285.09:53:44.47#ibcon#*after write, iclass 11, count 0 2006.285.09:53:44.47#ibcon#*before return 0, iclass 11, count 0 2006.285.09:53:44.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:53:44.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.09:53:44.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.09:53:44.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.09:53:44.47$vck44/vb=8,4 2006.285.09:53:44.47#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.09:53:44.47#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.09:53:44.47#ibcon#ireg 11 cls_cnt 2 2006.285.09:53:44.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:53:44.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:53:44.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:53:44.53#ibcon#enter wrdev, iclass 13, count 2 2006.285.09:53:44.53#ibcon#first serial, iclass 13, count 2 2006.285.09:53:44.53#ibcon#enter sib2, iclass 13, count 2 2006.285.09:53:44.53#ibcon#flushed, iclass 13, count 2 2006.285.09:53:44.53#ibcon#about to write, iclass 13, count 2 2006.285.09:53:44.53#ibcon#wrote, iclass 13, count 2 2006.285.09:53:44.53#ibcon#about to read 3, iclass 13, count 2 2006.285.09:53:44.55#ibcon#read 3, iclass 13, count 2 2006.285.09:53:44.55#ibcon#about to read 4, iclass 13, count 2 2006.285.09:53:44.55#ibcon#read 4, iclass 13, count 2 2006.285.09:53:44.55#ibcon#about to read 5, iclass 13, count 2 2006.285.09:53:44.55#ibcon#read 5, iclass 13, count 2 2006.285.09:53:44.55#ibcon#about to read 6, iclass 13, count 2 2006.285.09:53:44.55#ibcon#read 6, iclass 13, count 2 2006.285.09:53:44.55#ibcon#end of sib2, iclass 13, count 2 2006.285.09:53:44.55#ibcon#*mode == 0, iclass 13, count 2 2006.285.09:53:44.55#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.09:53:44.55#ibcon#[27=AT08-04\r\n] 2006.285.09:53:44.55#ibcon#*before write, iclass 13, count 2 2006.285.09:53:44.55#ibcon#enter sib2, iclass 13, count 2 2006.285.09:53:44.55#ibcon#flushed, iclass 13, count 2 2006.285.09:53:44.55#ibcon#about to write, iclass 13, count 2 2006.285.09:53:44.55#ibcon#wrote, iclass 13, count 2 2006.285.09:53:44.55#ibcon#about to read 3, iclass 13, count 2 2006.285.09:53:44.58#ibcon#read 3, iclass 13, count 2 2006.285.09:53:44.58#ibcon#about to read 4, iclass 13, count 2 2006.285.09:53:44.58#ibcon#read 4, iclass 13, count 2 2006.285.09:53:44.58#ibcon#about to read 5, iclass 13, count 2 2006.285.09:53:44.58#ibcon#read 5, iclass 13, count 2 2006.285.09:53:44.58#ibcon#about to read 6, iclass 13, count 2 2006.285.09:53:44.58#ibcon#read 6, iclass 13, count 2 2006.285.09:53:44.58#ibcon#end of sib2, iclass 13, count 2 2006.285.09:53:44.58#ibcon#*after write, iclass 13, count 2 2006.285.09:53:44.58#ibcon#*before return 0, iclass 13, count 2 2006.285.09:53:44.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:53:44.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.09:53:44.58#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.09:53:44.58#ibcon#ireg 7 cls_cnt 0 2006.285.09:53:44.58#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:53:44.70#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:53:44.70#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:53:44.70#ibcon#enter wrdev, iclass 13, count 0 2006.285.09:53:44.70#ibcon#first serial, iclass 13, count 0 2006.285.09:53:44.70#ibcon#enter sib2, iclass 13, count 0 2006.285.09:53:44.70#ibcon#flushed, iclass 13, count 0 2006.285.09:53:44.70#ibcon#about to write, iclass 13, count 0 2006.285.09:53:44.70#ibcon#wrote, iclass 13, count 0 2006.285.09:53:44.70#ibcon#about to read 3, iclass 13, count 0 2006.285.09:53:44.72#ibcon#read 3, iclass 13, count 0 2006.285.09:53:44.72#ibcon#about to read 4, iclass 13, count 0 2006.285.09:53:44.72#ibcon#read 4, iclass 13, count 0 2006.285.09:53:44.72#ibcon#about to read 5, iclass 13, count 0 2006.285.09:53:44.72#ibcon#read 5, iclass 13, count 0 2006.285.09:53:44.72#ibcon#about to read 6, iclass 13, count 0 2006.285.09:53:44.72#ibcon#read 6, iclass 13, count 0 2006.285.09:53:44.72#ibcon#end of sib2, iclass 13, count 0 2006.285.09:53:44.72#ibcon#*mode == 0, iclass 13, count 0 2006.285.09:53:44.72#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.09:53:44.72#ibcon#[27=USB\r\n] 2006.285.09:53:44.72#ibcon#*before write, iclass 13, count 0 2006.285.09:53:44.72#ibcon#enter sib2, iclass 13, count 0 2006.285.09:53:44.72#ibcon#flushed, iclass 13, count 0 2006.285.09:53:44.72#ibcon#about to write, iclass 13, count 0 2006.285.09:53:44.72#ibcon#wrote, iclass 13, count 0 2006.285.09:53:44.72#ibcon#about to read 3, iclass 13, count 0 2006.285.09:53:44.75#ibcon#read 3, iclass 13, count 0 2006.285.09:53:44.75#ibcon#about to read 4, iclass 13, count 0 2006.285.09:53:44.75#ibcon#read 4, iclass 13, count 0 2006.285.09:53:44.75#ibcon#about to read 5, iclass 13, count 0 2006.285.09:53:44.75#ibcon#read 5, iclass 13, count 0 2006.285.09:53:44.75#ibcon#about to read 6, iclass 13, count 0 2006.285.09:53:44.75#ibcon#read 6, iclass 13, count 0 2006.285.09:53:44.75#ibcon#end of sib2, iclass 13, count 0 2006.285.09:53:44.75#ibcon#*after write, iclass 13, count 0 2006.285.09:53:44.75#ibcon#*before return 0, iclass 13, count 0 2006.285.09:53:44.75#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:53:44.75#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.09:53:44.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.09:53:44.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.09:53:44.75$vck44/vabw=wide 2006.285.09:53:44.75#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.09:53:44.75#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.09:53:44.75#ibcon#ireg 8 cls_cnt 0 2006.285.09:53:44.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:53:44.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:53:44.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:53:44.75#ibcon#enter wrdev, iclass 15, count 0 2006.285.09:53:44.75#ibcon#first serial, iclass 15, count 0 2006.285.09:53:44.75#ibcon#enter sib2, iclass 15, count 0 2006.285.09:53:44.75#ibcon#flushed, iclass 15, count 0 2006.285.09:53:44.75#ibcon#about to write, iclass 15, count 0 2006.285.09:53:44.75#ibcon#wrote, iclass 15, count 0 2006.285.09:53:44.75#ibcon#about to read 3, iclass 15, count 0 2006.285.09:53:44.77#ibcon#read 3, iclass 15, count 0 2006.285.09:53:44.77#ibcon#about to read 4, iclass 15, count 0 2006.285.09:53:44.77#ibcon#read 4, iclass 15, count 0 2006.285.09:53:44.77#ibcon#about to read 5, iclass 15, count 0 2006.285.09:53:44.77#ibcon#read 5, iclass 15, count 0 2006.285.09:53:44.77#ibcon#about to read 6, iclass 15, count 0 2006.285.09:53:44.77#ibcon#read 6, iclass 15, count 0 2006.285.09:53:44.77#ibcon#end of sib2, iclass 15, count 0 2006.285.09:53:44.77#ibcon#*mode == 0, iclass 15, count 0 2006.285.09:53:44.77#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.09:53:44.77#ibcon#[25=BW32\r\n] 2006.285.09:53:44.77#ibcon#*before write, iclass 15, count 0 2006.285.09:53:44.77#ibcon#enter sib2, iclass 15, count 0 2006.285.09:53:44.77#ibcon#flushed, iclass 15, count 0 2006.285.09:53:44.77#ibcon#about to write, iclass 15, count 0 2006.285.09:53:44.77#ibcon#wrote, iclass 15, count 0 2006.285.09:53:44.77#ibcon#about to read 3, iclass 15, count 0 2006.285.09:53:44.80#ibcon#read 3, iclass 15, count 0 2006.285.09:53:44.80#ibcon#about to read 4, iclass 15, count 0 2006.285.09:53:44.80#ibcon#read 4, iclass 15, count 0 2006.285.09:53:44.80#ibcon#about to read 5, iclass 15, count 0 2006.285.09:53:44.80#ibcon#read 5, iclass 15, count 0 2006.285.09:53:44.80#ibcon#about to read 6, iclass 15, count 0 2006.285.09:53:44.80#ibcon#read 6, iclass 15, count 0 2006.285.09:53:44.80#ibcon#end of sib2, iclass 15, count 0 2006.285.09:53:44.80#ibcon#*after write, iclass 15, count 0 2006.285.09:53:44.80#ibcon#*before return 0, iclass 15, count 0 2006.285.09:53:44.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:53:44.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.09:53:44.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.09:53:44.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.09:53:44.80$vck44/vbbw=wide 2006.285.09:53:44.80#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.09:53:44.80#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.09:53:44.80#ibcon#ireg 8 cls_cnt 0 2006.285.09:53:44.80#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:53:44.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:53:44.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:53:44.87#ibcon#enter wrdev, iclass 17, count 0 2006.285.09:53:44.87#ibcon#first serial, iclass 17, count 0 2006.285.09:53:44.87#ibcon#enter sib2, iclass 17, count 0 2006.285.09:53:44.87#ibcon#flushed, iclass 17, count 0 2006.285.09:53:44.87#ibcon#about to write, iclass 17, count 0 2006.285.09:53:44.87#ibcon#wrote, iclass 17, count 0 2006.285.09:53:44.87#ibcon#about to read 3, iclass 17, count 0 2006.285.09:53:44.89#ibcon#read 3, iclass 17, count 0 2006.285.09:53:44.89#ibcon#about to read 4, iclass 17, count 0 2006.285.09:53:44.89#ibcon#read 4, iclass 17, count 0 2006.285.09:53:44.89#ibcon#about to read 5, iclass 17, count 0 2006.285.09:53:44.89#ibcon#read 5, iclass 17, count 0 2006.285.09:53:44.89#ibcon#about to read 6, iclass 17, count 0 2006.285.09:53:44.89#ibcon#read 6, iclass 17, count 0 2006.285.09:53:44.89#ibcon#end of sib2, iclass 17, count 0 2006.285.09:53:44.89#ibcon#*mode == 0, iclass 17, count 0 2006.285.09:53:44.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.09:53:44.89#ibcon#[27=BW32\r\n] 2006.285.09:53:44.89#ibcon#*before write, iclass 17, count 0 2006.285.09:53:44.89#ibcon#enter sib2, iclass 17, count 0 2006.285.09:53:44.89#ibcon#flushed, iclass 17, count 0 2006.285.09:53:44.89#ibcon#about to write, iclass 17, count 0 2006.285.09:53:44.89#ibcon#wrote, iclass 17, count 0 2006.285.09:53:44.89#ibcon#about to read 3, iclass 17, count 0 2006.285.09:53:44.92#ibcon#read 3, iclass 17, count 0 2006.285.09:53:44.92#ibcon#about to read 4, iclass 17, count 0 2006.285.09:53:44.92#ibcon#read 4, iclass 17, count 0 2006.285.09:53:44.92#ibcon#about to read 5, iclass 17, count 0 2006.285.09:53:44.92#ibcon#read 5, iclass 17, count 0 2006.285.09:53:44.92#ibcon#about to read 6, iclass 17, count 0 2006.285.09:53:44.92#ibcon#read 6, iclass 17, count 0 2006.285.09:53:44.92#ibcon#end of sib2, iclass 17, count 0 2006.285.09:53:44.92#ibcon#*after write, iclass 17, count 0 2006.285.09:53:44.92#ibcon#*before return 0, iclass 17, count 0 2006.285.09:53:44.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:53:44.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.09:53:44.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.09:53:44.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.09:53:44.92$setupk4/ifdk4 2006.285.09:53:44.92$ifdk4/lo= 2006.285.09:53:44.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:53:44.92$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:53:44.92$ifdk4/patch= 2006.285.09:53:44.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:53:44.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:53:44.92$setupk4/!*+20s 2006.285.09:53:46.25#abcon#<5=/06 1.1 1.4 19.38 951015.1\r\n> 2006.285.09:53:46.27#abcon#{5=INTERFACE CLEAR} 2006.285.09:53:46.33#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:53:56.42#abcon#<5=/06 1.1 1.4 19.37 951015.1\r\n> 2006.285.09:53:56.44#abcon#{5=INTERFACE CLEAR} 2006.285.09:53:56.50#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:53:59.43$setupk4/"tpicd 2006.285.09:53:59.43$setupk4/echo=off 2006.285.09:53:59.43$setupk4/xlog=off 2006.285.09:53:59.43:!2006.285.09:55:42 2006.285.09:54:18.14#trakl#Source acquired 2006.285.09:54:18.14#flagr#flagr/antenna,acquired 2006.285.09:55:42.00:preob 2006.285.09:55:43.13/onsource/TRACKING 2006.285.09:55:43.13:!2006.285.09:55:52 2006.285.09:55:52.00:"tape 2006.285.09:55:52.00:"st=record 2006.285.09:55:52.00:data_valid=on 2006.285.09:55:52.00:midob 2006.285.09:55:52.13/onsource/TRACKING 2006.285.09:55:52.13/wx/19.38,1015.1,94 2006.285.09:55:52.27/cable/+6.4832E-03 2006.285.09:55:53.36/va/01,07,usb,yes,32,34 2006.285.09:55:53.36/va/02,06,usb,yes,32,32 2006.285.09:55:53.36/va/03,07,usb,yes,31,33 2006.285.09:55:53.36/va/04,06,usb,yes,33,34 2006.285.09:55:53.36/va/05,03,usb,yes,32,33 2006.285.09:55:53.36/va/06,04,usb,yes,29,29 2006.285.09:55:53.36/va/07,04,usb,yes,30,30 2006.285.09:55:53.36/va/08,03,usb,yes,30,37 2006.285.09:55:53.59/valo/01,524.99,yes,locked 2006.285.09:55:53.59/valo/02,534.99,yes,locked 2006.285.09:55:53.59/valo/03,564.99,yes,locked 2006.285.09:55:53.59/valo/04,624.99,yes,locked 2006.285.09:55:53.59/valo/05,734.99,yes,locked 2006.285.09:55:53.59/valo/06,814.99,yes,locked 2006.285.09:55:53.59/valo/07,864.99,yes,locked 2006.285.09:55:53.59/valo/08,884.99,yes,locked 2006.285.09:55:54.68/vb/01,04,usb,yes,31,28 2006.285.09:55:54.68/vb/02,05,usb,yes,29,29 2006.285.09:55:54.68/vb/03,04,usb,yes,30,33 2006.285.09:55:54.68/vb/04,05,usb,yes,30,29 2006.285.09:55:54.68/vb/05,04,usb,yes,27,29 2006.285.09:55:54.68/vb/06,03,usb,yes,38,34 2006.285.09:55:54.68/vb/07,04,usb,yes,31,31 2006.285.09:55:54.68/vb/08,04,usb,yes,28,32 2006.285.09:55:54.91/vblo/01,629.99,yes,locked 2006.285.09:55:54.91/vblo/02,634.99,yes,locked 2006.285.09:55:54.91/vblo/03,649.99,yes,locked 2006.285.09:55:54.91/vblo/04,679.99,yes,locked 2006.285.09:55:54.91/vblo/05,709.99,yes,locked 2006.285.09:55:54.91/vblo/06,719.99,yes,locked 2006.285.09:55:54.91/vblo/07,734.99,yes,locked 2006.285.09:55:54.91/vblo/08,744.99,yes,locked 2006.285.09:55:55.06/vabw/8 2006.285.09:55:55.21/vbbw/8 2006.285.09:55:55.30/xfe/off,on,12.2 2006.285.09:55:55.68/ifatt/23,28,28,28 2006.285.09:55:56.08/fmout-gps/S +2.48E-07 2006.285.09:55:56.10:!2006.285.09:57:42 2006.285.09:57:42.01:data_valid=off 2006.285.09:57:42.01:"et 2006.285.09:57:42.01:!+3s 2006.285.09:57:45.02:"tape 2006.285.09:57:45.02:postob 2006.285.09:57:45.15/cable/+6.4843E-03 2006.285.09:57:45.15/wx/19.38,1015.1,94 2006.285.09:57:46.08/fmout-gps/S +2.47E-07 2006.285.09:57:46.08:scan_name=285-1001,jd0610,40 2006.285.09:57:46.08:source=1954-388,195800.00,-384506.4,2000.0,cw 2006.285.09:57:47.14#flagr#flagr/antenna,new-source 2006.285.09:57:47.14:checkk5 2006.285.09:57:47.69/chk_autoobs//k5ts1/ autoobs is running! 2006.285.09:57:48.10/chk_autoobs//k5ts2/ autoobs is running! 2006.285.09:57:48.46/chk_autoobs//k5ts3/ autoobs is running! 2006.285.09:57:48.86/chk_autoobs//k5ts4/ autoobs is running! 2006.285.09:57:49.26/chk_obsdata//k5ts1/T2850955??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.09:57:49.63/chk_obsdata//k5ts2/T2850955??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.09:57:50.05/chk_obsdata//k5ts3/T2850955??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.09:57:50.45/chk_obsdata//k5ts4/T2850955??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.09:57:51.39/k5log//k5ts1_log_newline 2006.285.09:57:52.10/k5log//k5ts2_log_newline 2006.285.09:57:53.23/k5log//k5ts3_log_newline 2006.285.09:57:59.02/k5log//k5ts4_log_newline 2006.285.09:57:59.05/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.09:57:59.05:setupk4=1 2006.285.09:57:59.05$setupk4/echo=on 2006.285.09:57:59.05$setupk4/pcalon 2006.285.09:57:59.05$pcalon/"no phase cal control is implemented here 2006.285.09:57:59.05$setupk4/"tpicd=stop 2006.285.09:57:59.05$setupk4/"rec=synch_on 2006.285.09:57:59.05$setupk4/"rec_mode=128 2006.285.09:57:59.05$setupk4/!* 2006.285.09:57:59.05$setupk4/recpk4 2006.285.09:57:59.05$recpk4/recpatch= 2006.285.09:57:59.05$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.09:57:59.05$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.09:57:59.05$setupk4/vck44 2006.285.09:57:59.05$vck44/valo=1,524.99 2006.285.09:57:59.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.09:57:59.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.09:57:59.05#ibcon#ireg 17 cls_cnt 0 2006.285.09:57:59.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:57:59.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:57:59.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:57:59.05#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:57:59.05#ibcon#first serial, iclass 14, count 0 2006.285.09:57:59.05#ibcon#enter sib2, iclass 14, count 0 2006.285.09:57:59.05#ibcon#flushed, iclass 14, count 0 2006.285.09:57:59.05#ibcon#about to write, iclass 14, count 0 2006.285.09:57:59.05#ibcon#wrote, iclass 14, count 0 2006.285.09:57:59.05#ibcon#about to read 3, iclass 14, count 0 2006.285.09:57:59.07#ibcon#read 3, iclass 14, count 0 2006.285.09:57:59.07#ibcon#about to read 4, iclass 14, count 0 2006.285.09:57:59.07#ibcon#read 4, iclass 14, count 0 2006.285.09:57:59.07#ibcon#about to read 5, iclass 14, count 0 2006.285.09:57:59.07#ibcon#read 5, iclass 14, count 0 2006.285.09:57:59.07#ibcon#about to read 6, iclass 14, count 0 2006.285.09:57:59.07#ibcon#read 6, iclass 14, count 0 2006.285.09:57:59.07#ibcon#end of sib2, iclass 14, count 0 2006.285.09:57:59.07#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:57:59.07#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:57:59.07#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.09:57:59.07#ibcon#*before write, iclass 14, count 0 2006.285.09:57:59.07#ibcon#enter sib2, iclass 14, count 0 2006.285.09:57:59.07#ibcon#flushed, iclass 14, count 0 2006.285.09:57:59.07#ibcon#about to write, iclass 14, count 0 2006.285.09:57:59.07#ibcon#wrote, iclass 14, count 0 2006.285.09:57:59.07#ibcon#about to read 3, iclass 14, count 0 2006.285.09:57:59.12#ibcon#read 3, iclass 14, count 0 2006.285.09:57:59.12#ibcon#about to read 4, iclass 14, count 0 2006.285.09:57:59.12#ibcon#read 4, iclass 14, count 0 2006.285.09:57:59.12#ibcon#about to read 5, iclass 14, count 0 2006.285.09:57:59.12#ibcon#read 5, iclass 14, count 0 2006.285.09:57:59.12#ibcon#about to read 6, iclass 14, count 0 2006.285.09:57:59.12#ibcon#read 6, iclass 14, count 0 2006.285.09:57:59.12#ibcon#end of sib2, iclass 14, count 0 2006.285.09:57:59.12#ibcon#*after write, iclass 14, count 0 2006.285.09:57:59.12#ibcon#*before return 0, iclass 14, count 0 2006.285.09:57:59.12#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:57:59.12#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:57:59.12#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:57:59.12#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:57:59.12$vck44/va=1,7 2006.285.09:57:59.12#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.09:57:59.12#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.09:57:59.12#ibcon#ireg 11 cls_cnt 2 2006.285.09:57:59.12#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:57:59.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:57:59.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:57:59.12#ibcon#enter wrdev, iclass 16, count 2 2006.285.09:57:59.12#ibcon#first serial, iclass 16, count 2 2006.285.09:57:59.12#ibcon#enter sib2, iclass 16, count 2 2006.285.09:57:59.12#ibcon#flushed, iclass 16, count 2 2006.285.09:57:59.12#ibcon#about to write, iclass 16, count 2 2006.285.09:57:59.12#ibcon#wrote, iclass 16, count 2 2006.285.09:57:59.12#ibcon#about to read 3, iclass 16, count 2 2006.285.09:57:59.14#ibcon#read 3, iclass 16, count 2 2006.285.09:57:59.14#ibcon#about to read 4, iclass 16, count 2 2006.285.09:57:59.14#ibcon#read 4, iclass 16, count 2 2006.285.09:57:59.14#ibcon#about to read 5, iclass 16, count 2 2006.285.09:57:59.14#ibcon#read 5, iclass 16, count 2 2006.285.09:57:59.14#ibcon#about to read 6, iclass 16, count 2 2006.285.09:57:59.14#ibcon#read 6, iclass 16, count 2 2006.285.09:57:59.14#ibcon#end of sib2, iclass 16, count 2 2006.285.09:57:59.14#ibcon#*mode == 0, iclass 16, count 2 2006.285.09:57:59.14#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.09:57:59.14#ibcon#[25=AT01-07\r\n] 2006.285.09:57:59.14#ibcon#*before write, iclass 16, count 2 2006.285.09:57:59.14#ibcon#enter sib2, iclass 16, count 2 2006.285.09:57:59.14#ibcon#flushed, iclass 16, count 2 2006.285.09:57:59.14#ibcon#about to write, iclass 16, count 2 2006.285.09:57:59.14#ibcon#wrote, iclass 16, count 2 2006.285.09:57:59.14#ibcon#about to read 3, iclass 16, count 2 2006.285.09:57:59.17#ibcon#read 3, iclass 16, count 2 2006.285.09:57:59.17#ibcon#about to read 4, iclass 16, count 2 2006.285.09:57:59.17#ibcon#read 4, iclass 16, count 2 2006.285.09:57:59.17#ibcon#about to read 5, iclass 16, count 2 2006.285.09:57:59.17#ibcon#read 5, iclass 16, count 2 2006.285.09:57:59.17#ibcon#about to read 6, iclass 16, count 2 2006.285.09:57:59.17#ibcon#read 6, iclass 16, count 2 2006.285.09:57:59.17#ibcon#end of sib2, iclass 16, count 2 2006.285.09:57:59.17#ibcon#*after write, iclass 16, count 2 2006.285.09:57:59.17#ibcon#*before return 0, iclass 16, count 2 2006.285.09:57:59.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:57:59.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:57:59.17#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.09:57:59.17#ibcon#ireg 7 cls_cnt 0 2006.285.09:57:59.17#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:57:59.29#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:57:59.29#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:57:59.29#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:57:59.29#ibcon#first serial, iclass 16, count 0 2006.285.09:57:59.29#ibcon#enter sib2, iclass 16, count 0 2006.285.09:57:59.29#ibcon#flushed, iclass 16, count 0 2006.285.09:57:59.29#ibcon#about to write, iclass 16, count 0 2006.285.09:57:59.29#ibcon#wrote, iclass 16, count 0 2006.285.09:57:59.29#ibcon#about to read 3, iclass 16, count 0 2006.285.09:57:59.31#ibcon#read 3, iclass 16, count 0 2006.285.09:57:59.31#ibcon#about to read 4, iclass 16, count 0 2006.285.09:57:59.31#ibcon#read 4, iclass 16, count 0 2006.285.09:57:59.31#ibcon#about to read 5, iclass 16, count 0 2006.285.09:57:59.31#ibcon#read 5, iclass 16, count 0 2006.285.09:57:59.31#ibcon#about to read 6, iclass 16, count 0 2006.285.09:57:59.31#ibcon#read 6, iclass 16, count 0 2006.285.09:57:59.31#ibcon#end of sib2, iclass 16, count 0 2006.285.09:57:59.31#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:57:59.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:57:59.31#ibcon#[25=USB\r\n] 2006.285.09:57:59.31#ibcon#*before write, iclass 16, count 0 2006.285.09:57:59.31#ibcon#enter sib2, iclass 16, count 0 2006.285.09:57:59.31#ibcon#flushed, iclass 16, count 0 2006.285.09:57:59.31#ibcon#about to write, iclass 16, count 0 2006.285.09:57:59.31#ibcon#wrote, iclass 16, count 0 2006.285.09:57:59.31#ibcon#about to read 3, iclass 16, count 0 2006.285.09:57:59.34#ibcon#read 3, iclass 16, count 0 2006.285.09:57:59.34#ibcon#about to read 4, iclass 16, count 0 2006.285.09:57:59.34#ibcon#read 4, iclass 16, count 0 2006.285.09:57:59.34#ibcon#about to read 5, iclass 16, count 0 2006.285.09:57:59.34#ibcon#read 5, iclass 16, count 0 2006.285.09:57:59.34#ibcon#about to read 6, iclass 16, count 0 2006.285.09:57:59.34#ibcon#read 6, iclass 16, count 0 2006.285.09:57:59.34#ibcon#end of sib2, iclass 16, count 0 2006.285.09:57:59.34#ibcon#*after write, iclass 16, count 0 2006.285.09:57:59.34#ibcon#*before return 0, iclass 16, count 0 2006.285.09:57:59.34#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:57:59.34#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:57:59.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:57:59.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:57:59.34$vck44/valo=2,534.99 2006.285.09:57:59.34#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.09:57:59.34#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.09:57:59.34#ibcon#ireg 17 cls_cnt 0 2006.285.09:57:59.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:57:59.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:57:59.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:57:59.34#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:57:59.34#ibcon#first serial, iclass 18, count 0 2006.285.09:57:59.34#ibcon#enter sib2, iclass 18, count 0 2006.285.09:57:59.34#ibcon#flushed, iclass 18, count 0 2006.285.09:57:59.34#ibcon#about to write, iclass 18, count 0 2006.285.09:57:59.34#ibcon#wrote, iclass 18, count 0 2006.285.09:57:59.34#ibcon#about to read 3, iclass 18, count 0 2006.285.09:57:59.36#ibcon#read 3, iclass 18, count 0 2006.285.09:57:59.36#ibcon#about to read 4, iclass 18, count 0 2006.285.09:57:59.36#ibcon#read 4, iclass 18, count 0 2006.285.09:57:59.36#ibcon#about to read 5, iclass 18, count 0 2006.285.09:57:59.36#ibcon#read 5, iclass 18, count 0 2006.285.09:57:59.36#ibcon#about to read 6, iclass 18, count 0 2006.285.09:57:59.36#ibcon#read 6, iclass 18, count 0 2006.285.09:57:59.36#ibcon#end of sib2, iclass 18, count 0 2006.285.09:57:59.36#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:57:59.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:57:59.36#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.09:57:59.36#ibcon#*before write, iclass 18, count 0 2006.285.09:57:59.36#ibcon#enter sib2, iclass 18, count 0 2006.285.09:57:59.36#ibcon#flushed, iclass 18, count 0 2006.285.09:57:59.36#ibcon#about to write, iclass 18, count 0 2006.285.09:57:59.36#ibcon#wrote, iclass 18, count 0 2006.285.09:57:59.36#ibcon#about to read 3, iclass 18, count 0 2006.285.09:57:59.40#ibcon#read 3, iclass 18, count 0 2006.285.09:57:59.40#ibcon#about to read 4, iclass 18, count 0 2006.285.09:57:59.40#ibcon#read 4, iclass 18, count 0 2006.285.09:57:59.40#ibcon#about to read 5, iclass 18, count 0 2006.285.09:57:59.40#ibcon#read 5, iclass 18, count 0 2006.285.09:57:59.40#ibcon#about to read 6, iclass 18, count 0 2006.285.09:57:59.40#ibcon#read 6, iclass 18, count 0 2006.285.09:57:59.40#ibcon#end of sib2, iclass 18, count 0 2006.285.09:57:59.40#ibcon#*after write, iclass 18, count 0 2006.285.09:57:59.40#ibcon#*before return 0, iclass 18, count 0 2006.285.09:57:59.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:57:59.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:57:59.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:57:59.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:57:59.40$vck44/va=2,6 2006.285.09:57:59.40#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.09:57:59.40#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.09:57:59.40#ibcon#ireg 11 cls_cnt 2 2006.285.09:57:59.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:57:59.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:57:59.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:57:59.46#ibcon#enter wrdev, iclass 20, count 2 2006.285.09:57:59.46#ibcon#first serial, iclass 20, count 2 2006.285.09:57:59.46#ibcon#enter sib2, iclass 20, count 2 2006.285.09:57:59.46#ibcon#flushed, iclass 20, count 2 2006.285.09:57:59.46#ibcon#about to write, iclass 20, count 2 2006.285.09:57:59.46#ibcon#wrote, iclass 20, count 2 2006.285.09:57:59.46#ibcon#about to read 3, iclass 20, count 2 2006.285.09:57:59.48#ibcon#read 3, iclass 20, count 2 2006.285.09:57:59.48#ibcon#about to read 4, iclass 20, count 2 2006.285.09:57:59.48#ibcon#read 4, iclass 20, count 2 2006.285.09:57:59.48#ibcon#about to read 5, iclass 20, count 2 2006.285.09:57:59.48#ibcon#read 5, iclass 20, count 2 2006.285.09:57:59.48#ibcon#about to read 6, iclass 20, count 2 2006.285.09:57:59.48#ibcon#read 6, iclass 20, count 2 2006.285.09:57:59.48#ibcon#end of sib2, iclass 20, count 2 2006.285.09:57:59.48#ibcon#*mode == 0, iclass 20, count 2 2006.285.09:57:59.48#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.09:57:59.48#ibcon#[25=AT02-06\r\n] 2006.285.09:57:59.48#ibcon#*before write, iclass 20, count 2 2006.285.09:57:59.48#ibcon#enter sib2, iclass 20, count 2 2006.285.09:57:59.48#ibcon#flushed, iclass 20, count 2 2006.285.09:57:59.48#ibcon#about to write, iclass 20, count 2 2006.285.09:57:59.48#ibcon#wrote, iclass 20, count 2 2006.285.09:57:59.48#ibcon#about to read 3, iclass 20, count 2 2006.285.09:57:59.51#ibcon#read 3, iclass 20, count 2 2006.285.09:57:59.51#ibcon#about to read 4, iclass 20, count 2 2006.285.09:57:59.51#ibcon#read 4, iclass 20, count 2 2006.285.09:57:59.51#ibcon#about to read 5, iclass 20, count 2 2006.285.09:57:59.51#ibcon#read 5, iclass 20, count 2 2006.285.09:57:59.51#ibcon#about to read 6, iclass 20, count 2 2006.285.09:57:59.51#ibcon#read 6, iclass 20, count 2 2006.285.09:57:59.51#ibcon#end of sib2, iclass 20, count 2 2006.285.09:57:59.51#ibcon#*after write, iclass 20, count 2 2006.285.09:57:59.51#ibcon#*before return 0, iclass 20, count 2 2006.285.09:57:59.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:57:59.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:57:59.51#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.09:57:59.51#ibcon#ireg 7 cls_cnt 0 2006.285.09:57:59.51#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:57:59.63#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:57:59.63#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:57:59.63#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:57:59.63#ibcon#first serial, iclass 20, count 0 2006.285.09:57:59.63#ibcon#enter sib2, iclass 20, count 0 2006.285.09:57:59.63#ibcon#flushed, iclass 20, count 0 2006.285.09:57:59.63#ibcon#about to write, iclass 20, count 0 2006.285.09:57:59.63#ibcon#wrote, iclass 20, count 0 2006.285.09:57:59.63#ibcon#about to read 3, iclass 20, count 0 2006.285.09:57:59.65#ibcon#read 3, iclass 20, count 0 2006.285.09:57:59.65#ibcon#about to read 4, iclass 20, count 0 2006.285.09:57:59.65#ibcon#read 4, iclass 20, count 0 2006.285.09:57:59.65#ibcon#about to read 5, iclass 20, count 0 2006.285.09:57:59.65#ibcon#read 5, iclass 20, count 0 2006.285.09:57:59.65#ibcon#about to read 6, iclass 20, count 0 2006.285.09:57:59.65#ibcon#read 6, iclass 20, count 0 2006.285.09:57:59.65#ibcon#end of sib2, iclass 20, count 0 2006.285.09:57:59.65#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:57:59.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:57:59.65#ibcon#[25=USB\r\n] 2006.285.09:57:59.65#ibcon#*before write, iclass 20, count 0 2006.285.09:57:59.65#ibcon#enter sib2, iclass 20, count 0 2006.285.09:57:59.65#ibcon#flushed, iclass 20, count 0 2006.285.09:57:59.65#ibcon#about to write, iclass 20, count 0 2006.285.09:57:59.65#ibcon#wrote, iclass 20, count 0 2006.285.09:57:59.65#ibcon#about to read 3, iclass 20, count 0 2006.285.09:57:59.68#ibcon#read 3, iclass 20, count 0 2006.285.09:57:59.68#ibcon#about to read 4, iclass 20, count 0 2006.285.09:57:59.68#ibcon#read 4, iclass 20, count 0 2006.285.09:57:59.68#ibcon#about to read 5, iclass 20, count 0 2006.285.09:57:59.68#ibcon#read 5, iclass 20, count 0 2006.285.09:57:59.68#ibcon#about to read 6, iclass 20, count 0 2006.285.09:57:59.68#ibcon#read 6, iclass 20, count 0 2006.285.09:57:59.68#ibcon#end of sib2, iclass 20, count 0 2006.285.09:57:59.68#ibcon#*after write, iclass 20, count 0 2006.285.09:57:59.68#ibcon#*before return 0, iclass 20, count 0 2006.285.09:57:59.68#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:57:59.68#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:57:59.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:57:59.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:57:59.68$vck44/valo=3,564.99 2006.285.09:57:59.68#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.09:57:59.68#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.09:57:59.68#ibcon#ireg 17 cls_cnt 0 2006.285.09:57:59.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:57:59.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:57:59.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:57:59.68#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:57:59.68#ibcon#first serial, iclass 22, count 0 2006.285.09:57:59.68#ibcon#enter sib2, iclass 22, count 0 2006.285.09:57:59.68#ibcon#flushed, iclass 22, count 0 2006.285.09:57:59.68#ibcon#about to write, iclass 22, count 0 2006.285.09:57:59.68#ibcon#wrote, iclass 22, count 0 2006.285.09:57:59.68#ibcon#about to read 3, iclass 22, count 0 2006.285.09:57:59.70#ibcon#read 3, iclass 22, count 0 2006.285.09:57:59.70#ibcon#about to read 4, iclass 22, count 0 2006.285.09:57:59.70#ibcon#read 4, iclass 22, count 0 2006.285.09:57:59.70#ibcon#about to read 5, iclass 22, count 0 2006.285.09:57:59.70#ibcon#read 5, iclass 22, count 0 2006.285.09:57:59.70#ibcon#about to read 6, iclass 22, count 0 2006.285.09:57:59.70#ibcon#read 6, iclass 22, count 0 2006.285.09:57:59.70#ibcon#end of sib2, iclass 22, count 0 2006.285.09:57:59.70#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:57:59.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:57:59.70#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.09:57:59.70#ibcon#*before write, iclass 22, count 0 2006.285.09:57:59.70#ibcon#enter sib2, iclass 22, count 0 2006.285.09:57:59.70#ibcon#flushed, iclass 22, count 0 2006.285.09:57:59.70#ibcon#about to write, iclass 22, count 0 2006.285.09:57:59.70#ibcon#wrote, iclass 22, count 0 2006.285.09:57:59.70#ibcon#about to read 3, iclass 22, count 0 2006.285.09:57:59.74#ibcon#read 3, iclass 22, count 0 2006.285.09:57:59.74#ibcon#about to read 4, iclass 22, count 0 2006.285.09:57:59.74#ibcon#read 4, iclass 22, count 0 2006.285.09:57:59.74#ibcon#about to read 5, iclass 22, count 0 2006.285.09:57:59.74#ibcon#read 5, iclass 22, count 0 2006.285.09:57:59.74#ibcon#about to read 6, iclass 22, count 0 2006.285.09:57:59.74#ibcon#read 6, iclass 22, count 0 2006.285.09:57:59.74#ibcon#end of sib2, iclass 22, count 0 2006.285.09:57:59.74#ibcon#*after write, iclass 22, count 0 2006.285.09:57:59.74#ibcon#*before return 0, iclass 22, count 0 2006.285.09:57:59.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:57:59.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:57:59.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:57:59.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:57:59.74$vck44/va=3,7 2006.285.09:57:59.74#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.09:57:59.74#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.09:57:59.74#ibcon#ireg 11 cls_cnt 2 2006.285.09:57:59.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:57:59.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:57:59.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:57:59.80#ibcon#enter wrdev, iclass 24, count 2 2006.285.09:57:59.80#ibcon#first serial, iclass 24, count 2 2006.285.09:57:59.80#ibcon#enter sib2, iclass 24, count 2 2006.285.09:57:59.80#ibcon#flushed, iclass 24, count 2 2006.285.09:57:59.80#ibcon#about to write, iclass 24, count 2 2006.285.09:57:59.80#ibcon#wrote, iclass 24, count 2 2006.285.09:57:59.80#ibcon#about to read 3, iclass 24, count 2 2006.285.09:57:59.82#ibcon#read 3, iclass 24, count 2 2006.285.09:57:59.82#ibcon#about to read 4, iclass 24, count 2 2006.285.09:57:59.82#ibcon#read 4, iclass 24, count 2 2006.285.09:57:59.82#ibcon#about to read 5, iclass 24, count 2 2006.285.09:57:59.82#ibcon#read 5, iclass 24, count 2 2006.285.09:57:59.82#ibcon#about to read 6, iclass 24, count 2 2006.285.09:57:59.82#ibcon#read 6, iclass 24, count 2 2006.285.09:57:59.82#ibcon#end of sib2, iclass 24, count 2 2006.285.09:57:59.82#ibcon#*mode == 0, iclass 24, count 2 2006.285.09:57:59.82#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.09:57:59.82#ibcon#[25=AT03-07\r\n] 2006.285.09:57:59.82#ibcon#*before write, iclass 24, count 2 2006.285.09:57:59.82#ibcon#enter sib2, iclass 24, count 2 2006.285.09:57:59.82#ibcon#flushed, iclass 24, count 2 2006.285.09:57:59.82#ibcon#about to write, iclass 24, count 2 2006.285.09:57:59.82#ibcon#wrote, iclass 24, count 2 2006.285.09:57:59.82#ibcon#about to read 3, iclass 24, count 2 2006.285.09:57:59.85#ibcon#read 3, iclass 24, count 2 2006.285.09:57:59.85#ibcon#about to read 4, iclass 24, count 2 2006.285.09:57:59.85#ibcon#read 4, iclass 24, count 2 2006.285.09:57:59.85#ibcon#about to read 5, iclass 24, count 2 2006.285.09:57:59.85#ibcon#read 5, iclass 24, count 2 2006.285.09:57:59.85#ibcon#about to read 6, iclass 24, count 2 2006.285.09:57:59.85#ibcon#read 6, iclass 24, count 2 2006.285.09:57:59.85#ibcon#end of sib2, iclass 24, count 2 2006.285.09:57:59.85#ibcon#*after write, iclass 24, count 2 2006.285.09:57:59.85#ibcon#*before return 0, iclass 24, count 2 2006.285.09:57:59.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:57:59.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:57:59.85#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.09:57:59.85#ibcon#ireg 7 cls_cnt 0 2006.285.09:57:59.85#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:57:59.97#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:57:59.97#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:57:59.97#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:57:59.97#ibcon#first serial, iclass 24, count 0 2006.285.09:57:59.97#ibcon#enter sib2, iclass 24, count 0 2006.285.09:57:59.97#ibcon#flushed, iclass 24, count 0 2006.285.09:57:59.97#ibcon#about to write, iclass 24, count 0 2006.285.09:57:59.97#ibcon#wrote, iclass 24, count 0 2006.285.09:57:59.97#ibcon#about to read 3, iclass 24, count 0 2006.285.09:57:59.99#ibcon#read 3, iclass 24, count 0 2006.285.09:57:59.99#ibcon#about to read 4, iclass 24, count 0 2006.285.09:57:59.99#ibcon#read 4, iclass 24, count 0 2006.285.09:57:59.99#ibcon#about to read 5, iclass 24, count 0 2006.285.09:57:59.99#ibcon#read 5, iclass 24, count 0 2006.285.09:57:59.99#ibcon#about to read 6, iclass 24, count 0 2006.285.09:57:59.99#ibcon#read 6, iclass 24, count 0 2006.285.09:57:59.99#ibcon#end of sib2, iclass 24, count 0 2006.285.09:57:59.99#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:57:59.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:57:59.99#ibcon#[25=USB\r\n] 2006.285.09:57:59.99#ibcon#*before write, iclass 24, count 0 2006.285.09:57:59.99#ibcon#enter sib2, iclass 24, count 0 2006.285.09:57:59.99#ibcon#flushed, iclass 24, count 0 2006.285.09:57:59.99#ibcon#about to write, iclass 24, count 0 2006.285.09:57:59.99#ibcon#wrote, iclass 24, count 0 2006.285.09:57:59.99#ibcon#about to read 3, iclass 24, count 0 2006.285.09:58:00.02#ibcon#read 3, iclass 24, count 0 2006.285.09:58:00.02#ibcon#about to read 4, iclass 24, count 0 2006.285.09:58:00.02#ibcon#read 4, iclass 24, count 0 2006.285.09:58:00.02#ibcon#about to read 5, iclass 24, count 0 2006.285.09:58:00.02#ibcon#read 5, iclass 24, count 0 2006.285.09:58:00.02#ibcon#about to read 6, iclass 24, count 0 2006.285.09:58:00.02#ibcon#read 6, iclass 24, count 0 2006.285.09:58:00.02#ibcon#end of sib2, iclass 24, count 0 2006.285.09:58:00.02#ibcon#*after write, iclass 24, count 0 2006.285.09:58:00.02#ibcon#*before return 0, iclass 24, count 0 2006.285.09:58:00.02#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:58:00.02#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:58:00.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:58:00.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:58:00.02$vck44/valo=4,624.99 2006.285.09:58:00.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.09:58:00.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.09:58:00.02#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:00.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:58:00.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:58:00.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:58:00.02#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:58:00.02#ibcon#first serial, iclass 26, count 0 2006.285.09:58:00.02#ibcon#enter sib2, iclass 26, count 0 2006.285.09:58:00.02#ibcon#flushed, iclass 26, count 0 2006.285.09:58:00.02#ibcon#about to write, iclass 26, count 0 2006.285.09:58:00.02#ibcon#wrote, iclass 26, count 0 2006.285.09:58:00.02#ibcon#about to read 3, iclass 26, count 0 2006.285.09:58:00.04#ibcon#read 3, iclass 26, count 0 2006.285.09:58:00.04#ibcon#about to read 4, iclass 26, count 0 2006.285.09:58:00.04#ibcon#read 4, iclass 26, count 0 2006.285.09:58:00.04#ibcon#about to read 5, iclass 26, count 0 2006.285.09:58:00.04#ibcon#read 5, iclass 26, count 0 2006.285.09:58:00.04#ibcon#about to read 6, iclass 26, count 0 2006.285.09:58:00.04#ibcon#read 6, iclass 26, count 0 2006.285.09:58:00.04#ibcon#end of sib2, iclass 26, count 0 2006.285.09:58:00.04#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:58:00.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:58:00.04#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.09:58:00.04#ibcon#*before write, iclass 26, count 0 2006.285.09:58:00.04#ibcon#enter sib2, iclass 26, count 0 2006.285.09:58:00.04#ibcon#flushed, iclass 26, count 0 2006.285.09:58:00.04#ibcon#about to write, iclass 26, count 0 2006.285.09:58:00.04#ibcon#wrote, iclass 26, count 0 2006.285.09:58:00.04#ibcon#about to read 3, iclass 26, count 0 2006.285.09:58:00.08#ibcon#read 3, iclass 26, count 0 2006.285.09:58:00.08#ibcon#about to read 4, iclass 26, count 0 2006.285.09:58:00.08#ibcon#read 4, iclass 26, count 0 2006.285.09:58:00.08#ibcon#about to read 5, iclass 26, count 0 2006.285.09:58:00.08#ibcon#read 5, iclass 26, count 0 2006.285.09:58:00.08#ibcon#about to read 6, iclass 26, count 0 2006.285.09:58:00.08#ibcon#read 6, iclass 26, count 0 2006.285.09:58:00.08#ibcon#end of sib2, iclass 26, count 0 2006.285.09:58:00.08#ibcon#*after write, iclass 26, count 0 2006.285.09:58:00.08#ibcon#*before return 0, iclass 26, count 0 2006.285.09:58:00.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:58:00.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:58:00.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:58:00.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:58:00.08$vck44/va=4,6 2006.285.09:58:00.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.09:58:00.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.09:58:00.08#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:00.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:58:00.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:58:00.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:58:00.14#ibcon#enter wrdev, iclass 28, count 2 2006.285.09:58:00.14#ibcon#first serial, iclass 28, count 2 2006.285.09:58:00.14#ibcon#enter sib2, iclass 28, count 2 2006.285.09:58:00.14#ibcon#flushed, iclass 28, count 2 2006.285.09:58:00.14#ibcon#about to write, iclass 28, count 2 2006.285.09:58:00.14#ibcon#wrote, iclass 28, count 2 2006.285.09:58:00.14#ibcon#about to read 3, iclass 28, count 2 2006.285.09:58:00.16#ibcon#read 3, iclass 28, count 2 2006.285.09:58:00.16#ibcon#about to read 4, iclass 28, count 2 2006.285.09:58:00.16#ibcon#read 4, iclass 28, count 2 2006.285.09:58:00.16#ibcon#about to read 5, iclass 28, count 2 2006.285.09:58:00.16#ibcon#read 5, iclass 28, count 2 2006.285.09:58:00.16#ibcon#about to read 6, iclass 28, count 2 2006.285.09:58:00.16#ibcon#read 6, iclass 28, count 2 2006.285.09:58:00.16#ibcon#end of sib2, iclass 28, count 2 2006.285.09:58:00.16#ibcon#*mode == 0, iclass 28, count 2 2006.285.09:58:00.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.09:58:00.16#ibcon#[25=AT04-06\r\n] 2006.285.09:58:00.16#ibcon#*before write, iclass 28, count 2 2006.285.09:58:00.16#ibcon#enter sib2, iclass 28, count 2 2006.285.09:58:00.16#ibcon#flushed, iclass 28, count 2 2006.285.09:58:00.16#ibcon#about to write, iclass 28, count 2 2006.285.09:58:00.16#ibcon#wrote, iclass 28, count 2 2006.285.09:58:00.16#ibcon#about to read 3, iclass 28, count 2 2006.285.09:58:00.19#ibcon#read 3, iclass 28, count 2 2006.285.09:58:00.19#ibcon#about to read 4, iclass 28, count 2 2006.285.09:58:00.19#ibcon#read 4, iclass 28, count 2 2006.285.09:58:00.19#ibcon#about to read 5, iclass 28, count 2 2006.285.09:58:00.19#ibcon#read 5, iclass 28, count 2 2006.285.09:58:00.19#ibcon#about to read 6, iclass 28, count 2 2006.285.09:58:00.19#ibcon#read 6, iclass 28, count 2 2006.285.09:58:00.19#ibcon#end of sib2, iclass 28, count 2 2006.285.09:58:00.19#ibcon#*after write, iclass 28, count 2 2006.285.09:58:00.19#ibcon#*before return 0, iclass 28, count 2 2006.285.09:58:00.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:58:00.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:58:00.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.09:58:00.19#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:00.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:58:00.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:58:00.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:58:00.31#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:58:00.31#ibcon#first serial, iclass 28, count 0 2006.285.09:58:00.31#ibcon#enter sib2, iclass 28, count 0 2006.285.09:58:00.31#ibcon#flushed, iclass 28, count 0 2006.285.09:58:00.31#ibcon#about to write, iclass 28, count 0 2006.285.09:58:00.31#ibcon#wrote, iclass 28, count 0 2006.285.09:58:00.31#ibcon#about to read 3, iclass 28, count 0 2006.285.09:58:00.33#ibcon#read 3, iclass 28, count 0 2006.285.09:58:00.33#ibcon#about to read 4, iclass 28, count 0 2006.285.09:58:00.33#ibcon#read 4, iclass 28, count 0 2006.285.09:58:00.33#ibcon#about to read 5, iclass 28, count 0 2006.285.09:58:00.33#ibcon#read 5, iclass 28, count 0 2006.285.09:58:00.33#ibcon#about to read 6, iclass 28, count 0 2006.285.09:58:00.33#ibcon#read 6, iclass 28, count 0 2006.285.09:58:00.33#ibcon#end of sib2, iclass 28, count 0 2006.285.09:58:00.33#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:58:00.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:58:00.33#ibcon#[25=USB\r\n] 2006.285.09:58:00.33#ibcon#*before write, iclass 28, count 0 2006.285.09:58:00.33#ibcon#enter sib2, iclass 28, count 0 2006.285.09:58:00.33#ibcon#flushed, iclass 28, count 0 2006.285.09:58:00.33#ibcon#about to write, iclass 28, count 0 2006.285.09:58:00.33#ibcon#wrote, iclass 28, count 0 2006.285.09:58:00.33#ibcon#about to read 3, iclass 28, count 0 2006.285.09:58:00.36#ibcon#read 3, iclass 28, count 0 2006.285.09:58:00.36#ibcon#about to read 4, iclass 28, count 0 2006.285.09:58:00.36#ibcon#read 4, iclass 28, count 0 2006.285.09:58:00.36#ibcon#about to read 5, iclass 28, count 0 2006.285.09:58:00.36#ibcon#read 5, iclass 28, count 0 2006.285.09:58:00.36#ibcon#about to read 6, iclass 28, count 0 2006.285.09:58:00.36#ibcon#read 6, iclass 28, count 0 2006.285.09:58:00.36#ibcon#end of sib2, iclass 28, count 0 2006.285.09:58:00.36#ibcon#*after write, iclass 28, count 0 2006.285.09:58:00.36#ibcon#*before return 0, iclass 28, count 0 2006.285.09:58:00.36#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:58:00.36#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:58:00.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:58:00.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:58:00.36$vck44/valo=5,734.99 2006.285.09:58:00.36#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.09:58:00.36#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.09:58:00.36#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:00.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:58:00.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:58:00.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:58:00.36#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:58:00.36#ibcon#first serial, iclass 30, count 0 2006.285.09:58:00.36#ibcon#enter sib2, iclass 30, count 0 2006.285.09:58:00.36#ibcon#flushed, iclass 30, count 0 2006.285.09:58:00.36#ibcon#about to write, iclass 30, count 0 2006.285.09:58:00.36#ibcon#wrote, iclass 30, count 0 2006.285.09:58:00.36#ibcon#about to read 3, iclass 30, count 0 2006.285.09:58:00.38#ibcon#read 3, iclass 30, count 0 2006.285.09:58:00.38#ibcon#about to read 4, iclass 30, count 0 2006.285.09:58:00.38#ibcon#read 4, iclass 30, count 0 2006.285.09:58:00.38#ibcon#about to read 5, iclass 30, count 0 2006.285.09:58:00.38#ibcon#read 5, iclass 30, count 0 2006.285.09:58:00.38#ibcon#about to read 6, iclass 30, count 0 2006.285.09:58:00.38#ibcon#read 6, iclass 30, count 0 2006.285.09:58:00.38#ibcon#end of sib2, iclass 30, count 0 2006.285.09:58:00.38#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:58:00.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:58:00.38#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.09:58:00.38#ibcon#*before write, iclass 30, count 0 2006.285.09:58:00.38#ibcon#enter sib2, iclass 30, count 0 2006.285.09:58:00.38#ibcon#flushed, iclass 30, count 0 2006.285.09:58:00.38#ibcon#about to write, iclass 30, count 0 2006.285.09:58:00.38#ibcon#wrote, iclass 30, count 0 2006.285.09:58:00.38#ibcon#about to read 3, iclass 30, count 0 2006.285.09:58:00.42#ibcon#read 3, iclass 30, count 0 2006.285.09:58:00.42#ibcon#about to read 4, iclass 30, count 0 2006.285.09:58:00.42#ibcon#read 4, iclass 30, count 0 2006.285.09:58:00.42#ibcon#about to read 5, iclass 30, count 0 2006.285.09:58:00.42#ibcon#read 5, iclass 30, count 0 2006.285.09:58:00.42#ibcon#about to read 6, iclass 30, count 0 2006.285.09:58:00.42#ibcon#read 6, iclass 30, count 0 2006.285.09:58:00.42#ibcon#end of sib2, iclass 30, count 0 2006.285.09:58:00.42#ibcon#*after write, iclass 30, count 0 2006.285.09:58:00.42#ibcon#*before return 0, iclass 30, count 0 2006.285.09:58:00.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:58:00.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:58:00.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:58:00.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:58:00.42$vck44/va=5,3 2006.285.09:58:00.42#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.09:58:00.42#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.09:58:00.42#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:00.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:58:00.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:58:00.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:58:00.48#ibcon#enter wrdev, iclass 32, count 2 2006.285.09:58:00.48#ibcon#first serial, iclass 32, count 2 2006.285.09:58:00.48#ibcon#enter sib2, iclass 32, count 2 2006.285.09:58:00.48#ibcon#flushed, iclass 32, count 2 2006.285.09:58:00.48#ibcon#about to write, iclass 32, count 2 2006.285.09:58:00.48#ibcon#wrote, iclass 32, count 2 2006.285.09:58:00.48#ibcon#about to read 3, iclass 32, count 2 2006.285.09:58:00.50#ibcon#read 3, iclass 32, count 2 2006.285.09:58:00.50#ibcon#about to read 4, iclass 32, count 2 2006.285.09:58:00.50#ibcon#read 4, iclass 32, count 2 2006.285.09:58:00.50#ibcon#about to read 5, iclass 32, count 2 2006.285.09:58:00.50#ibcon#read 5, iclass 32, count 2 2006.285.09:58:00.50#ibcon#about to read 6, iclass 32, count 2 2006.285.09:58:00.50#ibcon#read 6, iclass 32, count 2 2006.285.09:58:00.50#ibcon#end of sib2, iclass 32, count 2 2006.285.09:58:00.50#ibcon#*mode == 0, iclass 32, count 2 2006.285.09:58:00.50#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.09:58:00.50#ibcon#[25=AT05-03\r\n] 2006.285.09:58:00.50#ibcon#*before write, iclass 32, count 2 2006.285.09:58:00.50#ibcon#enter sib2, iclass 32, count 2 2006.285.09:58:00.50#ibcon#flushed, iclass 32, count 2 2006.285.09:58:00.50#ibcon#about to write, iclass 32, count 2 2006.285.09:58:00.50#ibcon#wrote, iclass 32, count 2 2006.285.09:58:00.50#ibcon#about to read 3, iclass 32, count 2 2006.285.09:58:00.50#abcon#<5=/05 1.2 1.7 19.38 941015.1\r\n> 2006.285.09:58:00.52#abcon#{5=INTERFACE CLEAR} 2006.285.09:58:00.53#ibcon#read 3, iclass 32, count 2 2006.285.09:58:00.53#ibcon#about to read 4, iclass 32, count 2 2006.285.09:58:00.53#ibcon#read 4, iclass 32, count 2 2006.285.09:58:00.53#ibcon#about to read 5, iclass 32, count 2 2006.285.09:58:00.53#ibcon#read 5, iclass 32, count 2 2006.285.09:58:00.53#ibcon#about to read 6, iclass 32, count 2 2006.285.09:58:00.53#ibcon#read 6, iclass 32, count 2 2006.285.09:58:00.53#ibcon#end of sib2, iclass 32, count 2 2006.285.09:58:00.53#ibcon#*after write, iclass 32, count 2 2006.285.09:58:00.53#ibcon#*before return 0, iclass 32, count 2 2006.285.09:58:00.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:58:00.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:58:00.53#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.09:58:00.53#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:00.53#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:58:00.58#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:58:00.65#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:58:00.65#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:58:00.65#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:58:00.65#ibcon#first serial, iclass 32, count 0 2006.285.09:58:00.65#ibcon#enter sib2, iclass 32, count 0 2006.285.09:58:00.65#ibcon#flushed, iclass 32, count 0 2006.285.09:58:00.65#ibcon#about to write, iclass 32, count 0 2006.285.09:58:00.65#ibcon#wrote, iclass 32, count 0 2006.285.09:58:00.65#ibcon#about to read 3, iclass 32, count 0 2006.285.09:58:00.67#ibcon#read 3, iclass 32, count 0 2006.285.09:58:00.67#ibcon#about to read 4, iclass 32, count 0 2006.285.09:58:00.67#ibcon#read 4, iclass 32, count 0 2006.285.09:58:00.67#ibcon#about to read 5, iclass 32, count 0 2006.285.09:58:00.67#ibcon#read 5, iclass 32, count 0 2006.285.09:58:00.67#ibcon#about to read 6, iclass 32, count 0 2006.285.09:58:00.67#ibcon#read 6, iclass 32, count 0 2006.285.09:58:00.67#ibcon#end of sib2, iclass 32, count 0 2006.285.09:58:00.67#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:58:00.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:58:00.67#ibcon#[25=USB\r\n] 2006.285.09:58:00.67#ibcon#*before write, iclass 32, count 0 2006.285.09:58:00.67#ibcon#enter sib2, iclass 32, count 0 2006.285.09:58:00.67#ibcon#flushed, iclass 32, count 0 2006.285.09:58:00.67#ibcon#about to write, iclass 32, count 0 2006.285.09:58:00.67#ibcon#wrote, iclass 32, count 0 2006.285.09:58:00.67#ibcon#about to read 3, iclass 32, count 0 2006.285.09:58:00.70#ibcon#read 3, iclass 32, count 0 2006.285.09:58:00.70#ibcon#about to read 4, iclass 32, count 0 2006.285.09:58:00.70#ibcon#read 4, iclass 32, count 0 2006.285.09:58:00.70#ibcon#about to read 5, iclass 32, count 0 2006.285.09:58:00.70#ibcon#read 5, iclass 32, count 0 2006.285.09:58:00.70#ibcon#about to read 6, iclass 32, count 0 2006.285.09:58:00.70#ibcon#read 6, iclass 32, count 0 2006.285.09:58:00.70#ibcon#end of sib2, iclass 32, count 0 2006.285.09:58:00.70#ibcon#*after write, iclass 32, count 0 2006.285.09:58:00.70#ibcon#*before return 0, iclass 32, count 0 2006.285.09:58:00.70#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:58:00.70#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:58:00.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:58:00.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:58:00.70$vck44/valo=6,814.99 2006.285.09:58:00.70#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.09:58:00.70#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.09:58:00.70#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:00.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:58:00.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:58:00.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:58:00.70#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:58:00.70#ibcon#first serial, iclass 38, count 0 2006.285.09:58:00.70#ibcon#enter sib2, iclass 38, count 0 2006.285.09:58:00.70#ibcon#flushed, iclass 38, count 0 2006.285.09:58:00.70#ibcon#about to write, iclass 38, count 0 2006.285.09:58:00.70#ibcon#wrote, iclass 38, count 0 2006.285.09:58:00.70#ibcon#about to read 3, iclass 38, count 0 2006.285.09:58:00.72#ibcon#read 3, iclass 38, count 0 2006.285.09:58:00.72#ibcon#about to read 4, iclass 38, count 0 2006.285.09:58:00.72#ibcon#read 4, iclass 38, count 0 2006.285.09:58:00.72#ibcon#about to read 5, iclass 38, count 0 2006.285.09:58:00.72#ibcon#read 5, iclass 38, count 0 2006.285.09:58:00.72#ibcon#about to read 6, iclass 38, count 0 2006.285.09:58:00.72#ibcon#read 6, iclass 38, count 0 2006.285.09:58:00.72#ibcon#end of sib2, iclass 38, count 0 2006.285.09:58:00.72#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:58:00.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:58:00.72#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.09:58:00.72#ibcon#*before write, iclass 38, count 0 2006.285.09:58:00.72#ibcon#enter sib2, iclass 38, count 0 2006.285.09:58:00.72#ibcon#flushed, iclass 38, count 0 2006.285.09:58:00.72#ibcon#about to write, iclass 38, count 0 2006.285.09:58:00.72#ibcon#wrote, iclass 38, count 0 2006.285.09:58:00.72#ibcon#about to read 3, iclass 38, count 0 2006.285.09:58:00.76#ibcon#read 3, iclass 38, count 0 2006.285.09:58:00.76#ibcon#about to read 4, iclass 38, count 0 2006.285.09:58:00.76#ibcon#read 4, iclass 38, count 0 2006.285.09:58:00.76#ibcon#about to read 5, iclass 38, count 0 2006.285.09:58:00.76#ibcon#read 5, iclass 38, count 0 2006.285.09:58:00.76#ibcon#about to read 6, iclass 38, count 0 2006.285.09:58:00.76#ibcon#read 6, iclass 38, count 0 2006.285.09:58:00.76#ibcon#end of sib2, iclass 38, count 0 2006.285.09:58:00.76#ibcon#*after write, iclass 38, count 0 2006.285.09:58:00.76#ibcon#*before return 0, iclass 38, count 0 2006.285.09:58:00.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:58:00.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:58:00.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:58:00.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:58:00.76$vck44/va=6,4 2006.285.09:58:00.76#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.09:58:00.76#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.09:58:00.76#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:00.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:58:00.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:58:00.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:58:00.82#ibcon#enter wrdev, iclass 40, count 2 2006.285.09:58:00.82#ibcon#first serial, iclass 40, count 2 2006.285.09:58:00.82#ibcon#enter sib2, iclass 40, count 2 2006.285.09:58:00.82#ibcon#flushed, iclass 40, count 2 2006.285.09:58:00.82#ibcon#about to write, iclass 40, count 2 2006.285.09:58:00.82#ibcon#wrote, iclass 40, count 2 2006.285.09:58:00.82#ibcon#about to read 3, iclass 40, count 2 2006.285.09:58:00.84#ibcon#read 3, iclass 40, count 2 2006.285.09:58:00.84#ibcon#about to read 4, iclass 40, count 2 2006.285.09:58:00.84#ibcon#read 4, iclass 40, count 2 2006.285.09:58:00.84#ibcon#about to read 5, iclass 40, count 2 2006.285.09:58:00.84#ibcon#read 5, iclass 40, count 2 2006.285.09:58:00.84#ibcon#about to read 6, iclass 40, count 2 2006.285.09:58:00.84#ibcon#read 6, iclass 40, count 2 2006.285.09:58:00.84#ibcon#end of sib2, iclass 40, count 2 2006.285.09:58:00.84#ibcon#*mode == 0, iclass 40, count 2 2006.285.09:58:00.84#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.09:58:00.84#ibcon#[25=AT06-04\r\n] 2006.285.09:58:00.84#ibcon#*before write, iclass 40, count 2 2006.285.09:58:00.84#ibcon#enter sib2, iclass 40, count 2 2006.285.09:58:00.84#ibcon#flushed, iclass 40, count 2 2006.285.09:58:00.84#ibcon#about to write, iclass 40, count 2 2006.285.09:58:00.84#ibcon#wrote, iclass 40, count 2 2006.285.09:58:00.84#ibcon#about to read 3, iclass 40, count 2 2006.285.09:58:00.87#ibcon#read 3, iclass 40, count 2 2006.285.09:58:00.87#ibcon#about to read 4, iclass 40, count 2 2006.285.09:58:00.87#ibcon#read 4, iclass 40, count 2 2006.285.09:58:00.87#ibcon#about to read 5, iclass 40, count 2 2006.285.09:58:00.87#ibcon#read 5, iclass 40, count 2 2006.285.09:58:00.87#ibcon#about to read 6, iclass 40, count 2 2006.285.09:58:00.87#ibcon#read 6, iclass 40, count 2 2006.285.09:58:00.87#ibcon#end of sib2, iclass 40, count 2 2006.285.09:58:00.87#ibcon#*after write, iclass 40, count 2 2006.285.09:58:00.87#ibcon#*before return 0, iclass 40, count 2 2006.285.09:58:00.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:58:00.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:58:00.87#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.09:58:00.87#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:00.87#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:58:00.99#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:58:00.99#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:58:00.99#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:58:00.99#ibcon#first serial, iclass 40, count 0 2006.285.09:58:00.99#ibcon#enter sib2, iclass 40, count 0 2006.285.09:58:00.99#ibcon#flushed, iclass 40, count 0 2006.285.09:58:00.99#ibcon#about to write, iclass 40, count 0 2006.285.09:58:00.99#ibcon#wrote, iclass 40, count 0 2006.285.09:58:00.99#ibcon#about to read 3, iclass 40, count 0 2006.285.09:58:01.01#ibcon#read 3, iclass 40, count 0 2006.285.09:58:01.01#ibcon#about to read 4, iclass 40, count 0 2006.285.09:58:01.01#ibcon#read 4, iclass 40, count 0 2006.285.09:58:01.01#ibcon#about to read 5, iclass 40, count 0 2006.285.09:58:01.01#ibcon#read 5, iclass 40, count 0 2006.285.09:58:01.01#ibcon#about to read 6, iclass 40, count 0 2006.285.09:58:01.01#ibcon#read 6, iclass 40, count 0 2006.285.09:58:01.01#ibcon#end of sib2, iclass 40, count 0 2006.285.09:58:01.01#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:58:01.01#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:58:01.01#ibcon#[25=USB\r\n] 2006.285.09:58:01.01#ibcon#*before write, iclass 40, count 0 2006.285.09:58:01.01#ibcon#enter sib2, iclass 40, count 0 2006.285.09:58:01.01#ibcon#flushed, iclass 40, count 0 2006.285.09:58:01.01#ibcon#about to write, iclass 40, count 0 2006.285.09:58:01.01#ibcon#wrote, iclass 40, count 0 2006.285.09:58:01.01#ibcon#about to read 3, iclass 40, count 0 2006.285.09:58:01.04#ibcon#read 3, iclass 40, count 0 2006.285.09:58:01.04#ibcon#about to read 4, iclass 40, count 0 2006.285.09:58:01.04#ibcon#read 4, iclass 40, count 0 2006.285.09:58:01.04#ibcon#about to read 5, iclass 40, count 0 2006.285.09:58:01.04#ibcon#read 5, iclass 40, count 0 2006.285.09:58:01.04#ibcon#about to read 6, iclass 40, count 0 2006.285.09:58:01.04#ibcon#read 6, iclass 40, count 0 2006.285.09:58:01.04#ibcon#end of sib2, iclass 40, count 0 2006.285.09:58:01.04#ibcon#*after write, iclass 40, count 0 2006.285.09:58:01.04#ibcon#*before return 0, iclass 40, count 0 2006.285.09:58:01.04#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:58:01.04#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:58:01.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:58:01.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:58:01.04$vck44/valo=7,864.99 2006.285.09:58:01.04#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.09:58:01.04#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.09:58:01.04#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:01.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:58:01.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:58:01.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:58:01.04#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:58:01.04#ibcon#first serial, iclass 4, count 0 2006.285.09:58:01.04#ibcon#enter sib2, iclass 4, count 0 2006.285.09:58:01.04#ibcon#flushed, iclass 4, count 0 2006.285.09:58:01.04#ibcon#about to write, iclass 4, count 0 2006.285.09:58:01.04#ibcon#wrote, iclass 4, count 0 2006.285.09:58:01.04#ibcon#about to read 3, iclass 4, count 0 2006.285.09:58:01.06#ibcon#read 3, iclass 4, count 0 2006.285.09:58:01.06#ibcon#about to read 4, iclass 4, count 0 2006.285.09:58:01.06#ibcon#read 4, iclass 4, count 0 2006.285.09:58:01.06#ibcon#about to read 5, iclass 4, count 0 2006.285.09:58:01.06#ibcon#read 5, iclass 4, count 0 2006.285.09:58:01.06#ibcon#about to read 6, iclass 4, count 0 2006.285.09:58:01.06#ibcon#read 6, iclass 4, count 0 2006.285.09:58:01.06#ibcon#end of sib2, iclass 4, count 0 2006.285.09:58:01.06#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:58:01.06#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:58:01.06#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.09:58:01.06#ibcon#*before write, iclass 4, count 0 2006.285.09:58:01.06#ibcon#enter sib2, iclass 4, count 0 2006.285.09:58:01.06#ibcon#flushed, iclass 4, count 0 2006.285.09:58:01.06#ibcon#about to write, iclass 4, count 0 2006.285.09:58:01.06#ibcon#wrote, iclass 4, count 0 2006.285.09:58:01.06#ibcon#about to read 3, iclass 4, count 0 2006.285.09:58:01.10#ibcon#read 3, iclass 4, count 0 2006.285.09:58:01.10#ibcon#about to read 4, iclass 4, count 0 2006.285.09:58:01.10#ibcon#read 4, iclass 4, count 0 2006.285.09:58:01.10#ibcon#about to read 5, iclass 4, count 0 2006.285.09:58:01.10#ibcon#read 5, iclass 4, count 0 2006.285.09:58:01.10#ibcon#about to read 6, iclass 4, count 0 2006.285.09:58:01.10#ibcon#read 6, iclass 4, count 0 2006.285.09:58:01.10#ibcon#end of sib2, iclass 4, count 0 2006.285.09:58:01.10#ibcon#*after write, iclass 4, count 0 2006.285.09:58:01.10#ibcon#*before return 0, iclass 4, count 0 2006.285.09:58:01.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:58:01.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:58:01.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:58:01.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:58:01.10$vck44/va=7,4 2006.285.09:58:01.10#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.09:58:01.10#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.09:58:01.10#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:01.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:58:01.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:58:01.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:58:01.16#ibcon#enter wrdev, iclass 6, count 2 2006.285.09:58:01.16#ibcon#first serial, iclass 6, count 2 2006.285.09:58:01.16#ibcon#enter sib2, iclass 6, count 2 2006.285.09:58:01.16#ibcon#flushed, iclass 6, count 2 2006.285.09:58:01.16#ibcon#about to write, iclass 6, count 2 2006.285.09:58:01.16#ibcon#wrote, iclass 6, count 2 2006.285.09:58:01.16#ibcon#about to read 3, iclass 6, count 2 2006.285.09:58:01.18#ibcon#read 3, iclass 6, count 2 2006.285.09:58:01.18#ibcon#about to read 4, iclass 6, count 2 2006.285.09:58:01.18#ibcon#read 4, iclass 6, count 2 2006.285.09:58:01.18#ibcon#about to read 5, iclass 6, count 2 2006.285.09:58:01.18#ibcon#read 5, iclass 6, count 2 2006.285.09:58:01.18#ibcon#about to read 6, iclass 6, count 2 2006.285.09:58:01.18#ibcon#read 6, iclass 6, count 2 2006.285.09:58:01.18#ibcon#end of sib2, iclass 6, count 2 2006.285.09:58:01.18#ibcon#*mode == 0, iclass 6, count 2 2006.285.09:58:01.18#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.09:58:01.18#ibcon#[25=AT07-04\r\n] 2006.285.09:58:01.18#ibcon#*before write, iclass 6, count 2 2006.285.09:58:01.18#ibcon#enter sib2, iclass 6, count 2 2006.285.09:58:01.18#ibcon#flushed, iclass 6, count 2 2006.285.09:58:01.18#ibcon#about to write, iclass 6, count 2 2006.285.09:58:01.18#ibcon#wrote, iclass 6, count 2 2006.285.09:58:01.18#ibcon#about to read 3, iclass 6, count 2 2006.285.09:58:01.21#ibcon#read 3, iclass 6, count 2 2006.285.09:58:01.21#ibcon#about to read 4, iclass 6, count 2 2006.285.09:58:01.21#ibcon#read 4, iclass 6, count 2 2006.285.09:58:01.21#ibcon#about to read 5, iclass 6, count 2 2006.285.09:58:01.21#ibcon#read 5, iclass 6, count 2 2006.285.09:58:01.21#ibcon#about to read 6, iclass 6, count 2 2006.285.09:58:01.21#ibcon#read 6, iclass 6, count 2 2006.285.09:58:01.21#ibcon#end of sib2, iclass 6, count 2 2006.285.09:58:01.21#ibcon#*after write, iclass 6, count 2 2006.285.09:58:01.21#ibcon#*before return 0, iclass 6, count 2 2006.285.09:58:01.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:58:01.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:58:01.21#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.09:58:01.21#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:01.21#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:58:01.33#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:58:01.33#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:58:01.33#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:58:01.33#ibcon#first serial, iclass 6, count 0 2006.285.09:58:01.33#ibcon#enter sib2, iclass 6, count 0 2006.285.09:58:01.33#ibcon#flushed, iclass 6, count 0 2006.285.09:58:01.33#ibcon#about to write, iclass 6, count 0 2006.285.09:58:01.33#ibcon#wrote, iclass 6, count 0 2006.285.09:58:01.33#ibcon#about to read 3, iclass 6, count 0 2006.285.09:58:01.35#ibcon#read 3, iclass 6, count 0 2006.285.09:58:01.35#ibcon#about to read 4, iclass 6, count 0 2006.285.09:58:01.35#ibcon#read 4, iclass 6, count 0 2006.285.09:58:01.35#ibcon#about to read 5, iclass 6, count 0 2006.285.09:58:01.35#ibcon#read 5, iclass 6, count 0 2006.285.09:58:01.35#ibcon#about to read 6, iclass 6, count 0 2006.285.09:58:01.35#ibcon#read 6, iclass 6, count 0 2006.285.09:58:01.35#ibcon#end of sib2, iclass 6, count 0 2006.285.09:58:01.35#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:58:01.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:58:01.35#ibcon#[25=USB\r\n] 2006.285.09:58:01.35#ibcon#*before write, iclass 6, count 0 2006.285.09:58:01.35#ibcon#enter sib2, iclass 6, count 0 2006.285.09:58:01.35#ibcon#flushed, iclass 6, count 0 2006.285.09:58:01.35#ibcon#about to write, iclass 6, count 0 2006.285.09:58:01.35#ibcon#wrote, iclass 6, count 0 2006.285.09:58:01.35#ibcon#about to read 3, iclass 6, count 0 2006.285.09:58:01.38#ibcon#read 3, iclass 6, count 0 2006.285.09:58:01.38#ibcon#about to read 4, iclass 6, count 0 2006.285.09:58:01.38#ibcon#read 4, iclass 6, count 0 2006.285.09:58:01.38#ibcon#about to read 5, iclass 6, count 0 2006.285.09:58:01.38#ibcon#read 5, iclass 6, count 0 2006.285.09:58:01.38#ibcon#about to read 6, iclass 6, count 0 2006.285.09:58:01.38#ibcon#read 6, iclass 6, count 0 2006.285.09:58:01.38#ibcon#end of sib2, iclass 6, count 0 2006.285.09:58:01.38#ibcon#*after write, iclass 6, count 0 2006.285.09:58:01.38#ibcon#*before return 0, iclass 6, count 0 2006.285.09:58:01.38#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:58:01.38#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:58:01.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:58:01.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:58:01.38$vck44/valo=8,884.99 2006.285.09:58:01.38#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.09:58:01.38#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.09:58:01.38#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:01.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:58:01.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:58:01.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:58:01.38#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:58:01.38#ibcon#first serial, iclass 10, count 0 2006.285.09:58:01.38#ibcon#enter sib2, iclass 10, count 0 2006.285.09:58:01.38#ibcon#flushed, iclass 10, count 0 2006.285.09:58:01.38#ibcon#about to write, iclass 10, count 0 2006.285.09:58:01.38#ibcon#wrote, iclass 10, count 0 2006.285.09:58:01.38#ibcon#about to read 3, iclass 10, count 0 2006.285.09:58:01.40#ibcon#read 3, iclass 10, count 0 2006.285.09:58:01.40#ibcon#about to read 4, iclass 10, count 0 2006.285.09:58:01.40#ibcon#read 4, iclass 10, count 0 2006.285.09:58:01.40#ibcon#about to read 5, iclass 10, count 0 2006.285.09:58:01.40#ibcon#read 5, iclass 10, count 0 2006.285.09:58:01.40#ibcon#about to read 6, iclass 10, count 0 2006.285.09:58:01.40#ibcon#read 6, iclass 10, count 0 2006.285.09:58:01.40#ibcon#end of sib2, iclass 10, count 0 2006.285.09:58:01.40#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:58:01.40#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:58:01.40#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.09:58:01.40#ibcon#*before write, iclass 10, count 0 2006.285.09:58:01.40#ibcon#enter sib2, iclass 10, count 0 2006.285.09:58:01.40#ibcon#flushed, iclass 10, count 0 2006.285.09:58:01.40#ibcon#about to write, iclass 10, count 0 2006.285.09:58:01.40#ibcon#wrote, iclass 10, count 0 2006.285.09:58:01.40#ibcon#about to read 3, iclass 10, count 0 2006.285.09:58:01.44#ibcon#read 3, iclass 10, count 0 2006.285.09:58:01.44#ibcon#about to read 4, iclass 10, count 0 2006.285.09:58:01.44#ibcon#read 4, iclass 10, count 0 2006.285.09:58:01.44#ibcon#about to read 5, iclass 10, count 0 2006.285.09:58:01.44#ibcon#read 5, iclass 10, count 0 2006.285.09:58:01.44#ibcon#about to read 6, iclass 10, count 0 2006.285.09:58:01.44#ibcon#read 6, iclass 10, count 0 2006.285.09:58:01.44#ibcon#end of sib2, iclass 10, count 0 2006.285.09:58:01.44#ibcon#*after write, iclass 10, count 0 2006.285.09:58:01.44#ibcon#*before return 0, iclass 10, count 0 2006.285.09:58:01.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:58:01.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:58:01.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:58:01.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:58:01.44$vck44/va=8,3 2006.285.09:58:01.44#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.09:58:01.44#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.09:58:01.44#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:01.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:58:01.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:58:01.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:58:01.50#ibcon#enter wrdev, iclass 12, count 2 2006.285.09:58:01.50#ibcon#first serial, iclass 12, count 2 2006.285.09:58:01.50#ibcon#enter sib2, iclass 12, count 2 2006.285.09:58:01.50#ibcon#flushed, iclass 12, count 2 2006.285.09:58:01.50#ibcon#about to write, iclass 12, count 2 2006.285.09:58:01.50#ibcon#wrote, iclass 12, count 2 2006.285.09:58:01.50#ibcon#about to read 3, iclass 12, count 2 2006.285.09:58:01.52#ibcon#read 3, iclass 12, count 2 2006.285.09:58:01.52#ibcon#about to read 4, iclass 12, count 2 2006.285.09:58:01.52#ibcon#read 4, iclass 12, count 2 2006.285.09:58:01.52#ibcon#about to read 5, iclass 12, count 2 2006.285.09:58:01.52#ibcon#read 5, iclass 12, count 2 2006.285.09:58:01.52#ibcon#about to read 6, iclass 12, count 2 2006.285.09:58:01.52#ibcon#read 6, iclass 12, count 2 2006.285.09:58:01.52#ibcon#end of sib2, iclass 12, count 2 2006.285.09:58:01.52#ibcon#*mode == 0, iclass 12, count 2 2006.285.09:58:01.52#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.09:58:01.52#ibcon#[25=AT08-03\r\n] 2006.285.09:58:01.52#ibcon#*before write, iclass 12, count 2 2006.285.09:58:01.52#ibcon#enter sib2, iclass 12, count 2 2006.285.09:58:01.52#ibcon#flushed, iclass 12, count 2 2006.285.09:58:01.52#ibcon#about to write, iclass 12, count 2 2006.285.09:58:01.52#ibcon#wrote, iclass 12, count 2 2006.285.09:58:01.52#ibcon#about to read 3, iclass 12, count 2 2006.285.09:58:01.55#ibcon#read 3, iclass 12, count 2 2006.285.09:58:01.55#ibcon#about to read 4, iclass 12, count 2 2006.285.09:58:01.55#ibcon#read 4, iclass 12, count 2 2006.285.09:58:01.55#ibcon#about to read 5, iclass 12, count 2 2006.285.09:58:01.55#ibcon#read 5, iclass 12, count 2 2006.285.09:58:01.55#ibcon#about to read 6, iclass 12, count 2 2006.285.09:58:01.55#ibcon#read 6, iclass 12, count 2 2006.285.09:58:01.55#ibcon#end of sib2, iclass 12, count 2 2006.285.09:58:01.55#ibcon#*after write, iclass 12, count 2 2006.285.09:58:01.55#ibcon#*before return 0, iclass 12, count 2 2006.285.09:58:01.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:58:01.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.09:58:01.55#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.09:58:01.55#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:01.55#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:58:01.67#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:58:01.67#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:58:01.67#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:58:01.67#ibcon#first serial, iclass 12, count 0 2006.285.09:58:01.67#ibcon#enter sib2, iclass 12, count 0 2006.285.09:58:01.67#ibcon#flushed, iclass 12, count 0 2006.285.09:58:01.67#ibcon#about to write, iclass 12, count 0 2006.285.09:58:01.67#ibcon#wrote, iclass 12, count 0 2006.285.09:58:01.67#ibcon#about to read 3, iclass 12, count 0 2006.285.09:58:01.69#ibcon#read 3, iclass 12, count 0 2006.285.09:58:01.69#ibcon#about to read 4, iclass 12, count 0 2006.285.09:58:01.69#ibcon#read 4, iclass 12, count 0 2006.285.09:58:01.69#ibcon#about to read 5, iclass 12, count 0 2006.285.09:58:01.69#ibcon#read 5, iclass 12, count 0 2006.285.09:58:01.69#ibcon#about to read 6, iclass 12, count 0 2006.285.09:58:01.69#ibcon#read 6, iclass 12, count 0 2006.285.09:58:01.69#ibcon#end of sib2, iclass 12, count 0 2006.285.09:58:01.69#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:58:01.69#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:58:01.69#ibcon#[25=USB\r\n] 2006.285.09:58:01.69#ibcon#*before write, iclass 12, count 0 2006.285.09:58:01.69#ibcon#enter sib2, iclass 12, count 0 2006.285.09:58:01.69#ibcon#flushed, iclass 12, count 0 2006.285.09:58:01.69#ibcon#about to write, iclass 12, count 0 2006.285.09:58:01.69#ibcon#wrote, iclass 12, count 0 2006.285.09:58:01.69#ibcon#about to read 3, iclass 12, count 0 2006.285.09:58:01.72#ibcon#read 3, iclass 12, count 0 2006.285.09:58:01.72#ibcon#about to read 4, iclass 12, count 0 2006.285.09:58:01.72#ibcon#read 4, iclass 12, count 0 2006.285.09:58:01.72#ibcon#about to read 5, iclass 12, count 0 2006.285.09:58:01.72#ibcon#read 5, iclass 12, count 0 2006.285.09:58:01.72#ibcon#about to read 6, iclass 12, count 0 2006.285.09:58:01.72#ibcon#read 6, iclass 12, count 0 2006.285.09:58:01.72#ibcon#end of sib2, iclass 12, count 0 2006.285.09:58:01.72#ibcon#*after write, iclass 12, count 0 2006.285.09:58:01.72#ibcon#*before return 0, iclass 12, count 0 2006.285.09:58:01.72#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:58:01.72#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.09:58:01.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:58:01.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:58:01.72$vck44/vblo=1,629.99 2006.285.09:58:01.72#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.09:58:01.72#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.09:58:01.72#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:01.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:58:01.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:58:01.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:58:01.72#ibcon#enter wrdev, iclass 14, count 0 2006.285.09:58:01.72#ibcon#first serial, iclass 14, count 0 2006.285.09:58:01.72#ibcon#enter sib2, iclass 14, count 0 2006.285.09:58:01.72#ibcon#flushed, iclass 14, count 0 2006.285.09:58:01.72#ibcon#about to write, iclass 14, count 0 2006.285.09:58:01.72#ibcon#wrote, iclass 14, count 0 2006.285.09:58:01.72#ibcon#about to read 3, iclass 14, count 0 2006.285.09:58:01.74#ibcon#read 3, iclass 14, count 0 2006.285.09:58:01.74#ibcon#about to read 4, iclass 14, count 0 2006.285.09:58:01.74#ibcon#read 4, iclass 14, count 0 2006.285.09:58:01.74#ibcon#about to read 5, iclass 14, count 0 2006.285.09:58:01.74#ibcon#read 5, iclass 14, count 0 2006.285.09:58:01.74#ibcon#about to read 6, iclass 14, count 0 2006.285.09:58:01.74#ibcon#read 6, iclass 14, count 0 2006.285.09:58:01.74#ibcon#end of sib2, iclass 14, count 0 2006.285.09:58:01.74#ibcon#*mode == 0, iclass 14, count 0 2006.285.09:58:01.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.09:58:01.74#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.09:58:01.74#ibcon#*before write, iclass 14, count 0 2006.285.09:58:01.74#ibcon#enter sib2, iclass 14, count 0 2006.285.09:58:01.74#ibcon#flushed, iclass 14, count 0 2006.285.09:58:01.74#ibcon#about to write, iclass 14, count 0 2006.285.09:58:01.74#ibcon#wrote, iclass 14, count 0 2006.285.09:58:01.74#ibcon#about to read 3, iclass 14, count 0 2006.285.09:58:01.78#ibcon#read 3, iclass 14, count 0 2006.285.09:58:01.78#ibcon#about to read 4, iclass 14, count 0 2006.285.09:58:01.78#ibcon#read 4, iclass 14, count 0 2006.285.09:58:01.78#ibcon#about to read 5, iclass 14, count 0 2006.285.09:58:01.78#ibcon#read 5, iclass 14, count 0 2006.285.09:58:01.78#ibcon#about to read 6, iclass 14, count 0 2006.285.09:58:01.78#ibcon#read 6, iclass 14, count 0 2006.285.09:58:01.78#ibcon#end of sib2, iclass 14, count 0 2006.285.09:58:01.78#ibcon#*after write, iclass 14, count 0 2006.285.09:58:01.78#ibcon#*before return 0, iclass 14, count 0 2006.285.09:58:01.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:58:01.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.09:58:01.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.09:58:01.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.09:58:01.78$vck44/vb=1,4 2006.285.09:58:01.78#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.09:58:01.78#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.09:58:01.78#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:01.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:58:01.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:58:01.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:58:01.78#ibcon#enter wrdev, iclass 16, count 2 2006.285.09:58:01.78#ibcon#first serial, iclass 16, count 2 2006.285.09:58:01.78#ibcon#enter sib2, iclass 16, count 2 2006.285.09:58:01.78#ibcon#flushed, iclass 16, count 2 2006.285.09:58:01.78#ibcon#about to write, iclass 16, count 2 2006.285.09:58:01.78#ibcon#wrote, iclass 16, count 2 2006.285.09:58:01.78#ibcon#about to read 3, iclass 16, count 2 2006.285.09:58:01.80#ibcon#read 3, iclass 16, count 2 2006.285.09:58:01.80#ibcon#about to read 4, iclass 16, count 2 2006.285.09:58:01.80#ibcon#read 4, iclass 16, count 2 2006.285.09:58:01.80#ibcon#about to read 5, iclass 16, count 2 2006.285.09:58:01.80#ibcon#read 5, iclass 16, count 2 2006.285.09:58:01.80#ibcon#about to read 6, iclass 16, count 2 2006.285.09:58:01.80#ibcon#read 6, iclass 16, count 2 2006.285.09:58:01.80#ibcon#end of sib2, iclass 16, count 2 2006.285.09:58:01.80#ibcon#*mode == 0, iclass 16, count 2 2006.285.09:58:01.80#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.09:58:01.80#ibcon#[27=AT01-04\r\n] 2006.285.09:58:01.80#ibcon#*before write, iclass 16, count 2 2006.285.09:58:01.80#ibcon#enter sib2, iclass 16, count 2 2006.285.09:58:01.80#ibcon#flushed, iclass 16, count 2 2006.285.09:58:01.80#ibcon#about to write, iclass 16, count 2 2006.285.09:58:01.80#ibcon#wrote, iclass 16, count 2 2006.285.09:58:01.80#ibcon#about to read 3, iclass 16, count 2 2006.285.09:58:01.83#ibcon#read 3, iclass 16, count 2 2006.285.09:58:01.83#ibcon#about to read 4, iclass 16, count 2 2006.285.09:58:01.83#ibcon#read 4, iclass 16, count 2 2006.285.09:58:01.83#ibcon#about to read 5, iclass 16, count 2 2006.285.09:58:01.83#ibcon#read 5, iclass 16, count 2 2006.285.09:58:01.83#ibcon#about to read 6, iclass 16, count 2 2006.285.09:58:01.83#ibcon#read 6, iclass 16, count 2 2006.285.09:58:01.83#ibcon#end of sib2, iclass 16, count 2 2006.285.09:58:01.83#ibcon#*after write, iclass 16, count 2 2006.285.09:58:01.83#ibcon#*before return 0, iclass 16, count 2 2006.285.09:58:01.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:58:01.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.09:58:01.83#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.09:58:01.83#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:01.83#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:58:01.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:58:01.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:58:01.95#ibcon#enter wrdev, iclass 16, count 0 2006.285.09:58:01.95#ibcon#first serial, iclass 16, count 0 2006.285.09:58:01.95#ibcon#enter sib2, iclass 16, count 0 2006.285.09:58:01.95#ibcon#flushed, iclass 16, count 0 2006.285.09:58:01.95#ibcon#about to write, iclass 16, count 0 2006.285.09:58:01.95#ibcon#wrote, iclass 16, count 0 2006.285.09:58:01.95#ibcon#about to read 3, iclass 16, count 0 2006.285.09:58:01.97#ibcon#read 3, iclass 16, count 0 2006.285.09:58:01.97#ibcon#about to read 4, iclass 16, count 0 2006.285.09:58:01.97#ibcon#read 4, iclass 16, count 0 2006.285.09:58:01.97#ibcon#about to read 5, iclass 16, count 0 2006.285.09:58:01.97#ibcon#read 5, iclass 16, count 0 2006.285.09:58:01.97#ibcon#about to read 6, iclass 16, count 0 2006.285.09:58:01.97#ibcon#read 6, iclass 16, count 0 2006.285.09:58:01.97#ibcon#end of sib2, iclass 16, count 0 2006.285.09:58:01.97#ibcon#*mode == 0, iclass 16, count 0 2006.285.09:58:01.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.09:58:01.97#ibcon#[27=USB\r\n] 2006.285.09:58:01.97#ibcon#*before write, iclass 16, count 0 2006.285.09:58:01.97#ibcon#enter sib2, iclass 16, count 0 2006.285.09:58:01.97#ibcon#flushed, iclass 16, count 0 2006.285.09:58:01.97#ibcon#about to write, iclass 16, count 0 2006.285.09:58:01.97#ibcon#wrote, iclass 16, count 0 2006.285.09:58:01.97#ibcon#about to read 3, iclass 16, count 0 2006.285.09:58:02.00#ibcon#read 3, iclass 16, count 0 2006.285.09:58:02.00#ibcon#about to read 4, iclass 16, count 0 2006.285.09:58:02.00#ibcon#read 4, iclass 16, count 0 2006.285.09:58:02.00#ibcon#about to read 5, iclass 16, count 0 2006.285.09:58:02.00#ibcon#read 5, iclass 16, count 0 2006.285.09:58:02.00#ibcon#about to read 6, iclass 16, count 0 2006.285.09:58:02.00#ibcon#read 6, iclass 16, count 0 2006.285.09:58:02.00#ibcon#end of sib2, iclass 16, count 0 2006.285.09:58:02.00#ibcon#*after write, iclass 16, count 0 2006.285.09:58:02.00#ibcon#*before return 0, iclass 16, count 0 2006.285.09:58:02.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:58:02.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.09:58:02.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.09:58:02.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.09:58:02.00$vck44/vblo=2,634.99 2006.285.09:58:02.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.09:58:02.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.09:58:02.00#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:02.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:58:02.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:58:02.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:58:02.00#ibcon#enter wrdev, iclass 18, count 0 2006.285.09:58:02.00#ibcon#first serial, iclass 18, count 0 2006.285.09:58:02.00#ibcon#enter sib2, iclass 18, count 0 2006.285.09:58:02.00#ibcon#flushed, iclass 18, count 0 2006.285.09:58:02.00#ibcon#about to write, iclass 18, count 0 2006.285.09:58:02.00#ibcon#wrote, iclass 18, count 0 2006.285.09:58:02.00#ibcon#about to read 3, iclass 18, count 0 2006.285.09:58:02.02#ibcon#read 3, iclass 18, count 0 2006.285.09:58:02.02#ibcon#about to read 4, iclass 18, count 0 2006.285.09:58:02.02#ibcon#read 4, iclass 18, count 0 2006.285.09:58:02.02#ibcon#about to read 5, iclass 18, count 0 2006.285.09:58:02.02#ibcon#read 5, iclass 18, count 0 2006.285.09:58:02.02#ibcon#about to read 6, iclass 18, count 0 2006.285.09:58:02.02#ibcon#read 6, iclass 18, count 0 2006.285.09:58:02.02#ibcon#end of sib2, iclass 18, count 0 2006.285.09:58:02.02#ibcon#*mode == 0, iclass 18, count 0 2006.285.09:58:02.02#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.09:58:02.02#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.09:58:02.02#ibcon#*before write, iclass 18, count 0 2006.285.09:58:02.02#ibcon#enter sib2, iclass 18, count 0 2006.285.09:58:02.02#ibcon#flushed, iclass 18, count 0 2006.285.09:58:02.02#ibcon#about to write, iclass 18, count 0 2006.285.09:58:02.02#ibcon#wrote, iclass 18, count 0 2006.285.09:58:02.02#ibcon#about to read 3, iclass 18, count 0 2006.285.09:58:02.06#ibcon#read 3, iclass 18, count 0 2006.285.09:58:02.06#ibcon#about to read 4, iclass 18, count 0 2006.285.09:58:02.06#ibcon#read 4, iclass 18, count 0 2006.285.09:58:02.06#ibcon#about to read 5, iclass 18, count 0 2006.285.09:58:02.06#ibcon#read 5, iclass 18, count 0 2006.285.09:58:02.06#ibcon#about to read 6, iclass 18, count 0 2006.285.09:58:02.06#ibcon#read 6, iclass 18, count 0 2006.285.09:58:02.06#ibcon#end of sib2, iclass 18, count 0 2006.285.09:58:02.06#ibcon#*after write, iclass 18, count 0 2006.285.09:58:02.06#ibcon#*before return 0, iclass 18, count 0 2006.285.09:58:02.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:58:02.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.09:58:02.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.09:58:02.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.09:58:02.06$vck44/vb=2,5 2006.285.09:58:02.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.09:58:02.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.09:58:02.06#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:02.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:58:02.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:58:02.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:58:02.12#ibcon#enter wrdev, iclass 20, count 2 2006.285.09:58:02.12#ibcon#first serial, iclass 20, count 2 2006.285.09:58:02.12#ibcon#enter sib2, iclass 20, count 2 2006.285.09:58:02.12#ibcon#flushed, iclass 20, count 2 2006.285.09:58:02.12#ibcon#about to write, iclass 20, count 2 2006.285.09:58:02.12#ibcon#wrote, iclass 20, count 2 2006.285.09:58:02.12#ibcon#about to read 3, iclass 20, count 2 2006.285.09:58:02.14#ibcon#read 3, iclass 20, count 2 2006.285.09:58:02.14#ibcon#about to read 4, iclass 20, count 2 2006.285.09:58:02.14#ibcon#read 4, iclass 20, count 2 2006.285.09:58:02.14#ibcon#about to read 5, iclass 20, count 2 2006.285.09:58:02.14#ibcon#read 5, iclass 20, count 2 2006.285.09:58:02.14#ibcon#about to read 6, iclass 20, count 2 2006.285.09:58:02.14#ibcon#read 6, iclass 20, count 2 2006.285.09:58:02.14#ibcon#end of sib2, iclass 20, count 2 2006.285.09:58:02.14#ibcon#*mode == 0, iclass 20, count 2 2006.285.09:58:02.14#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.09:58:02.14#ibcon#[27=AT02-05\r\n] 2006.285.09:58:02.14#ibcon#*before write, iclass 20, count 2 2006.285.09:58:02.14#ibcon#enter sib2, iclass 20, count 2 2006.285.09:58:02.14#ibcon#flushed, iclass 20, count 2 2006.285.09:58:02.14#ibcon#about to write, iclass 20, count 2 2006.285.09:58:02.14#ibcon#wrote, iclass 20, count 2 2006.285.09:58:02.14#ibcon#about to read 3, iclass 20, count 2 2006.285.09:58:02.17#ibcon#read 3, iclass 20, count 2 2006.285.09:58:02.17#ibcon#about to read 4, iclass 20, count 2 2006.285.09:58:02.17#ibcon#read 4, iclass 20, count 2 2006.285.09:58:02.17#ibcon#about to read 5, iclass 20, count 2 2006.285.09:58:02.17#ibcon#read 5, iclass 20, count 2 2006.285.09:58:02.17#ibcon#about to read 6, iclass 20, count 2 2006.285.09:58:02.17#ibcon#read 6, iclass 20, count 2 2006.285.09:58:02.17#ibcon#end of sib2, iclass 20, count 2 2006.285.09:58:02.17#ibcon#*after write, iclass 20, count 2 2006.285.09:58:02.17#ibcon#*before return 0, iclass 20, count 2 2006.285.09:58:02.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:58:02.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.09:58:02.17#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.09:58:02.17#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:02.17#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:58:02.29#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:58:02.29#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:58:02.29#ibcon#enter wrdev, iclass 20, count 0 2006.285.09:58:02.29#ibcon#first serial, iclass 20, count 0 2006.285.09:58:02.29#ibcon#enter sib2, iclass 20, count 0 2006.285.09:58:02.29#ibcon#flushed, iclass 20, count 0 2006.285.09:58:02.29#ibcon#about to write, iclass 20, count 0 2006.285.09:58:02.29#ibcon#wrote, iclass 20, count 0 2006.285.09:58:02.29#ibcon#about to read 3, iclass 20, count 0 2006.285.09:58:02.31#ibcon#read 3, iclass 20, count 0 2006.285.09:58:02.31#ibcon#about to read 4, iclass 20, count 0 2006.285.09:58:02.31#ibcon#read 4, iclass 20, count 0 2006.285.09:58:02.31#ibcon#about to read 5, iclass 20, count 0 2006.285.09:58:02.31#ibcon#read 5, iclass 20, count 0 2006.285.09:58:02.31#ibcon#about to read 6, iclass 20, count 0 2006.285.09:58:02.31#ibcon#read 6, iclass 20, count 0 2006.285.09:58:02.31#ibcon#end of sib2, iclass 20, count 0 2006.285.09:58:02.31#ibcon#*mode == 0, iclass 20, count 0 2006.285.09:58:02.31#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.09:58:02.31#ibcon#[27=USB\r\n] 2006.285.09:58:02.31#ibcon#*before write, iclass 20, count 0 2006.285.09:58:02.31#ibcon#enter sib2, iclass 20, count 0 2006.285.09:58:02.31#ibcon#flushed, iclass 20, count 0 2006.285.09:58:02.31#ibcon#about to write, iclass 20, count 0 2006.285.09:58:02.31#ibcon#wrote, iclass 20, count 0 2006.285.09:58:02.31#ibcon#about to read 3, iclass 20, count 0 2006.285.09:58:02.34#ibcon#read 3, iclass 20, count 0 2006.285.09:58:02.34#ibcon#about to read 4, iclass 20, count 0 2006.285.09:58:02.34#ibcon#read 4, iclass 20, count 0 2006.285.09:58:02.34#ibcon#about to read 5, iclass 20, count 0 2006.285.09:58:02.34#ibcon#read 5, iclass 20, count 0 2006.285.09:58:02.34#ibcon#about to read 6, iclass 20, count 0 2006.285.09:58:02.34#ibcon#read 6, iclass 20, count 0 2006.285.09:58:02.34#ibcon#end of sib2, iclass 20, count 0 2006.285.09:58:02.34#ibcon#*after write, iclass 20, count 0 2006.285.09:58:02.34#ibcon#*before return 0, iclass 20, count 0 2006.285.09:58:02.34#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:58:02.34#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.09:58:02.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.09:58:02.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.09:58:02.34$vck44/vblo=3,649.99 2006.285.09:58:02.34#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.09:58:02.34#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.09:58:02.34#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:02.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:58:02.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:58:02.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:58:02.34#ibcon#enter wrdev, iclass 22, count 0 2006.285.09:58:02.34#ibcon#first serial, iclass 22, count 0 2006.285.09:58:02.34#ibcon#enter sib2, iclass 22, count 0 2006.285.09:58:02.34#ibcon#flushed, iclass 22, count 0 2006.285.09:58:02.34#ibcon#about to write, iclass 22, count 0 2006.285.09:58:02.34#ibcon#wrote, iclass 22, count 0 2006.285.09:58:02.34#ibcon#about to read 3, iclass 22, count 0 2006.285.09:58:02.36#ibcon#read 3, iclass 22, count 0 2006.285.09:58:02.36#ibcon#about to read 4, iclass 22, count 0 2006.285.09:58:02.36#ibcon#read 4, iclass 22, count 0 2006.285.09:58:02.36#ibcon#about to read 5, iclass 22, count 0 2006.285.09:58:02.36#ibcon#read 5, iclass 22, count 0 2006.285.09:58:02.36#ibcon#about to read 6, iclass 22, count 0 2006.285.09:58:02.36#ibcon#read 6, iclass 22, count 0 2006.285.09:58:02.36#ibcon#end of sib2, iclass 22, count 0 2006.285.09:58:02.36#ibcon#*mode == 0, iclass 22, count 0 2006.285.09:58:02.36#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.09:58:02.36#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.09:58:02.36#ibcon#*before write, iclass 22, count 0 2006.285.09:58:02.36#ibcon#enter sib2, iclass 22, count 0 2006.285.09:58:02.36#ibcon#flushed, iclass 22, count 0 2006.285.09:58:02.36#ibcon#about to write, iclass 22, count 0 2006.285.09:58:02.36#ibcon#wrote, iclass 22, count 0 2006.285.09:58:02.36#ibcon#about to read 3, iclass 22, count 0 2006.285.09:58:02.40#ibcon#read 3, iclass 22, count 0 2006.285.09:58:02.40#ibcon#about to read 4, iclass 22, count 0 2006.285.09:58:02.40#ibcon#read 4, iclass 22, count 0 2006.285.09:58:02.40#ibcon#about to read 5, iclass 22, count 0 2006.285.09:58:02.40#ibcon#read 5, iclass 22, count 0 2006.285.09:58:02.40#ibcon#about to read 6, iclass 22, count 0 2006.285.09:58:02.40#ibcon#read 6, iclass 22, count 0 2006.285.09:58:02.40#ibcon#end of sib2, iclass 22, count 0 2006.285.09:58:02.40#ibcon#*after write, iclass 22, count 0 2006.285.09:58:02.40#ibcon#*before return 0, iclass 22, count 0 2006.285.09:58:02.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:58:02.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.09:58:02.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.09:58:02.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.09:58:02.40$vck44/vb=3,4 2006.285.09:58:02.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.09:58:02.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.09:58:02.40#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:02.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:58:02.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:58:02.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:58:02.46#ibcon#enter wrdev, iclass 24, count 2 2006.285.09:58:02.46#ibcon#first serial, iclass 24, count 2 2006.285.09:58:02.46#ibcon#enter sib2, iclass 24, count 2 2006.285.09:58:02.46#ibcon#flushed, iclass 24, count 2 2006.285.09:58:02.46#ibcon#about to write, iclass 24, count 2 2006.285.09:58:02.46#ibcon#wrote, iclass 24, count 2 2006.285.09:58:02.46#ibcon#about to read 3, iclass 24, count 2 2006.285.09:58:02.48#ibcon#read 3, iclass 24, count 2 2006.285.09:58:02.48#ibcon#about to read 4, iclass 24, count 2 2006.285.09:58:02.48#ibcon#read 4, iclass 24, count 2 2006.285.09:58:02.48#ibcon#about to read 5, iclass 24, count 2 2006.285.09:58:02.48#ibcon#read 5, iclass 24, count 2 2006.285.09:58:02.48#ibcon#about to read 6, iclass 24, count 2 2006.285.09:58:02.48#ibcon#read 6, iclass 24, count 2 2006.285.09:58:02.48#ibcon#end of sib2, iclass 24, count 2 2006.285.09:58:02.48#ibcon#*mode == 0, iclass 24, count 2 2006.285.09:58:02.48#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.09:58:02.48#ibcon#[27=AT03-04\r\n] 2006.285.09:58:02.48#ibcon#*before write, iclass 24, count 2 2006.285.09:58:02.48#ibcon#enter sib2, iclass 24, count 2 2006.285.09:58:02.48#ibcon#flushed, iclass 24, count 2 2006.285.09:58:02.48#ibcon#about to write, iclass 24, count 2 2006.285.09:58:02.48#ibcon#wrote, iclass 24, count 2 2006.285.09:58:02.48#ibcon#about to read 3, iclass 24, count 2 2006.285.09:58:02.51#ibcon#read 3, iclass 24, count 2 2006.285.09:58:02.51#ibcon#about to read 4, iclass 24, count 2 2006.285.09:58:02.51#ibcon#read 4, iclass 24, count 2 2006.285.09:58:02.51#ibcon#about to read 5, iclass 24, count 2 2006.285.09:58:02.51#ibcon#read 5, iclass 24, count 2 2006.285.09:58:02.51#ibcon#about to read 6, iclass 24, count 2 2006.285.09:58:02.51#ibcon#read 6, iclass 24, count 2 2006.285.09:58:02.51#ibcon#end of sib2, iclass 24, count 2 2006.285.09:58:02.51#ibcon#*after write, iclass 24, count 2 2006.285.09:58:02.51#ibcon#*before return 0, iclass 24, count 2 2006.285.09:58:02.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:58:02.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.09:58:02.51#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.09:58:02.51#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:02.51#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:58:02.63#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:58:02.63#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:58:02.63#ibcon#enter wrdev, iclass 24, count 0 2006.285.09:58:02.63#ibcon#first serial, iclass 24, count 0 2006.285.09:58:02.63#ibcon#enter sib2, iclass 24, count 0 2006.285.09:58:02.63#ibcon#flushed, iclass 24, count 0 2006.285.09:58:02.63#ibcon#about to write, iclass 24, count 0 2006.285.09:58:02.63#ibcon#wrote, iclass 24, count 0 2006.285.09:58:02.63#ibcon#about to read 3, iclass 24, count 0 2006.285.09:58:02.65#ibcon#read 3, iclass 24, count 0 2006.285.09:58:02.65#ibcon#about to read 4, iclass 24, count 0 2006.285.09:58:02.65#ibcon#read 4, iclass 24, count 0 2006.285.09:58:02.65#ibcon#about to read 5, iclass 24, count 0 2006.285.09:58:02.65#ibcon#read 5, iclass 24, count 0 2006.285.09:58:02.65#ibcon#about to read 6, iclass 24, count 0 2006.285.09:58:02.65#ibcon#read 6, iclass 24, count 0 2006.285.09:58:02.65#ibcon#end of sib2, iclass 24, count 0 2006.285.09:58:02.65#ibcon#*mode == 0, iclass 24, count 0 2006.285.09:58:02.65#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.09:58:02.65#ibcon#[27=USB\r\n] 2006.285.09:58:02.65#ibcon#*before write, iclass 24, count 0 2006.285.09:58:02.65#ibcon#enter sib2, iclass 24, count 0 2006.285.09:58:02.65#ibcon#flushed, iclass 24, count 0 2006.285.09:58:02.65#ibcon#about to write, iclass 24, count 0 2006.285.09:58:02.65#ibcon#wrote, iclass 24, count 0 2006.285.09:58:02.65#ibcon#about to read 3, iclass 24, count 0 2006.285.09:58:02.68#ibcon#read 3, iclass 24, count 0 2006.285.09:58:02.68#ibcon#about to read 4, iclass 24, count 0 2006.285.09:58:02.68#ibcon#read 4, iclass 24, count 0 2006.285.09:58:02.68#ibcon#about to read 5, iclass 24, count 0 2006.285.09:58:02.68#ibcon#read 5, iclass 24, count 0 2006.285.09:58:02.68#ibcon#about to read 6, iclass 24, count 0 2006.285.09:58:02.68#ibcon#read 6, iclass 24, count 0 2006.285.09:58:02.68#ibcon#end of sib2, iclass 24, count 0 2006.285.09:58:02.68#ibcon#*after write, iclass 24, count 0 2006.285.09:58:02.68#ibcon#*before return 0, iclass 24, count 0 2006.285.09:58:02.68#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:58:02.68#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.09:58:02.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.09:58:02.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.09:58:02.68$vck44/vblo=4,679.99 2006.285.09:58:02.68#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.09:58:02.68#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.09:58:02.68#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:02.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:58:02.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:58:02.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:58:02.68#ibcon#enter wrdev, iclass 26, count 0 2006.285.09:58:02.68#ibcon#first serial, iclass 26, count 0 2006.285.09:58:02.68#ibcon#enter sib2, iclass 26, count 0 2006.285.09:58:02.68#ibcon#flushed, iclass 26, count 0 2006.285.09:58:02.68#ibcon#about to write, iclass 26, count 0 2006.285.09:58:02.68#ibcon#wrote, iclass 26, count 0 2006.285.09:58:02.68#ibcon#about to read 3, iclass 26, count 0 2006.285.09:58:02.70#ibcon#read 3, iclass 26, count 0 2006.285.09:58:02.70#ibcon#about to read 4, iclass 26, count 0 2006.285.09:58:02.70#ibcon#read 4, iclass 26, count 0 2006.285.09:58:02.70#ibcon#about to read 5, iclass 26, count 0 2006.285.09:58:02.70#ibcon#read 5, iclass 26, count 0 2006.285.09:58:02.70#ibcon#about to read 6, iclass 26, count 0 2006.285.09:58:02.70#ibcon#read 6, iclass 26, count 0 2006.285.09:58:02.70#ibcon#end of sib2, iclass 26, count 0 2006.285.09:58:02.70#ibcon#*mode == 0, iclass 26, count 0 2006.285.09:58:02.70#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.09:58:02.70#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.09:58:02.70#ibcon#*before write, iclass 26, count 0 2006.285.09:58:02.70#ibcon#enter sib2, iclass 26, count 0 2006.285.09:58:02.70#ibcon#flushed, iclass 26, count 0 2006.285.09:58:02.70#ibcon#about to write, iclass 26, count 0 2006.285.09:58:02.70#ibcon#wrote, iclass 26, count 0 2006.285.09:58:02.70#ibcon#about to read 3, iclass 26, count 0 2006.285.09:58:02.74#ibcon#read 3, iclass 26, count 0 2006.285.09:58:02.74#ibcon#about to read 4, iclass 26, count 0 2006.285.09:58:02.74#ibcon#read 4, iclass 26, count 0 2006.285.09:58:02.74#ibcon#about to read 5, iclass 26, count 0 2006.285.09:58:02.74#ibcon#read 5, iclass 26, count 0 2006.285.09:58:02.74#ibcon#about to read 6, iclass 26, count 0 2006.285.09:58:02.74#ibcon#read 6, iclass 26, count 0 2006.285.09:58:02.74#ibcon#end of sib2, iclass 26, count 0 2006.285.09:58:02.74#ibcon#*after write, iclass 26, count 0 2006.285.09:58:02.74#ibcon#*before return 0, iclass 26, count 0 2006.285.09:58:02.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:58:02.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.09:58:02.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.09:58:02.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.09:58:02.74$vck44/vb=4,5 2006.285.09:58:02.74#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.09:58:02.74#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.09:58:02.74#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:02.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:58:02.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:58:02.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:58:02.80#ibcon#enter wrdev, iclass 28, count 2 2006.285.09:58:02.80#ibcon#first serial, iclass 28, count 2 2006.285.09:58:02.80#ibcon#enter sib2, iclass 28, count 2 2006.285.09:58:02.80#ibcon#flushed, iclass 28, count 2 2006.285.09:58:02.80#ibcon#about to write, iclass 28, count 2 2006.285.09:58:02.80#ibcon#wrote, iclass 28, count 2 2006.285.09:58:02.80#ibcon#about to read 3, iclass 28, count 2 2006.285.09:58:02.82#ibcon#read 3, iclass 28, count 2 2006.285.09:58:02.82#ibcon#about to read 4, iclass 28, count 2 2006.285.09:58:02.82#ibcon#read 4, iclass 28, count 2 2006.285.09:58:02.82#ibcon#about to read 5, iclass 28, count 2 2006.285.09:58:02.82#ibcon#read 5, iclass 28, count 2 2006.285.09:58:02.82#ibcon#about to read 6, iclass 28, count 2 2006.285.09:58:02.82#ibcon#read 6, iclass 28, count 2 2006.285.09:58:02.82#ibcon#end of sib2, iclass 28, count 2 2006.285.09:58:02.82#ibcon#*mode == 0, iclass 28, count 2 2006.285.09:58:02.82#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.09:58:02.82#ibcon#[27=AT04-05\r\n] 2006.285.09:58:02.82#ibcon#*before write, iclass 28, count 2 2006.285.09:58:02.82#ibcon#enter sib2, iclass 28, count 2 2006.285.09:58:02.82#ibcon#flushed, iclass 28, count 2 2006.285.09:58:02.82#ibcon#about to write, iclass 28, count 2 2006.285.09:58:02.82#ibcon#wrote, iclass 28, count 2 2006.285.09:58:02.82#ibcon#about to read 3, iclass 28, count 2 2006.285.09:58:02.85#ibcon#read 3, iclass 28, count 2 2006.285.09:58:02.85#ibcon#about to read 4, iclass 28, count 2 2006.285.09:58:02.85#ibcon#read 4, iclass 28, count 2 2006.285.09:58:02.85#ibcon#about to read 5, iclass 28, count 2 2006.285.09:58:02.85#ibcon#read 5, iclass 28, count 2 2006.285.09:58:02.85#ibcon#about to read 6, iclass 28, count 2 2006.285.09:58:02.85#ibcon#read 6, iclass 28, count 2 2006.285.09:58:02.85#ibcon#end of sib2, iclass 28, count 2 2006.285.09:58:02.85#ibcon#*after write, iclass 28, count 2 2006.285.09:58:02.85#ibcon#*before return 0, iclass 28, count 2 2006.285.09:58:02.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:58:02.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.09:58:02.85#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.09:58:02.85#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:02.85#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:58:02.97#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:58:02.97#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:58:02.97#ibcon#enter wrdev, iclass 28, count 0 2006.285.09:58:02.97#ibcon#first serial, iclass 28, count 0 2006.285.09:58:02.97#ibcon#enter sib2, iclass 28, count 0 2006.285.09:58:02.97#ibcon#flushed, iclass 28, count 0 2006.285.09:58:02.97#ibcon#about to write, iclass 28, count 0 2006.285.09:58:02.97#ibcon#wrote, iclass 28, count 0 2006.285.09:58:02.97#ibcon#about to read 3, iclass 28, count 0 2006.285.09:58:02.99#ibcon#read 3, iclass 28, count 0 2006.285.09:58:02.99#ibcon#about to read 4, iclass 28, count 0 2006.285.09:58:02.99#ibcon#read 4, iclass 28, count 0 2006.285.09:58:02.99#ibcon#about to read 5, iclass 28, count 0 2006.285.09:58:02.99#ibcon#read 5, iclass 28, count 0 2006.285.09:58:02.99#ibcon#about to read 6, iclass 28, count 0 2006.285.09:58:02.99#ibcon#read 6, iclass 28, count 0 2006.285.09:58:02.99#ibcon#end of sib2, iclass 28, count 0 2006.285.09:58:02.99#ibcon#*mode == 0, iclass 28, count 0 2006.285.09:58:02.99#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.09:58:02.99#ibcon#[27=USB\r\n] 2006.285.09:58:02.99#ibcon#*before write, iclass 28, count 0 2006.285.09:58:02.99#ibcon#enter sib2, iclass 28, count 0 2006.285.09:58:02.99#ibcon#flushed, iclass 28, count 0 2006.285.09:58:02.99#ibcon#about to write, iclass 28, count 0 2006.285.09:58:02.99#ibcon#wrote, iclass 28, count 0 2006.285.09:58:02.99#ibcon#about to read 3, iclass 28, count 0 2006.285.09:58:03.02#ibcon#read 3, iclass 28, count 0 2006.285.09:58:03.02#ibcon#about to read 4, iclass 28, count 0 2006.285.09:58:03.02#ibcon#read 4, iclass 28, count 0 2006.285.09:58:03.02#ibcon#about to read 5, iclass 28, count 0 2006.285.09:58:03.02#ibcon#read 5, iclass 28, count 0 2006.285.09:58:03.02#ibcon#about to read 6, iclass 28, count 0 2006.285.09:58:03.02#ibcon#read 6, iclass 28, count 0 2006.285.09:58:03.02#ibcon#end of sib2, iclass 28, count 0 2006.285.09:58:03.02#ibcon#*after write, iclass 28, count 0 2006.285.09:58:03.02#ibcon#*before return 0, iclass 28, count 0 2006.285.09:58:03.02#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:58:03.02#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.09:58:03.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.09:58:03.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.09:58:03.02$vck44/vblo=5,709.99 2006.285.09:58:03.02#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.09:58:03.02#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.09:58:03.02#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:03.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:58:03.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:58:03.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:58:03.02#ibcon#enter wrdev, iclass 30, count 0 2006.285.09:58:03.02#ibcon#first serial, iclass 30, count 0 2006.285.09:58:03.02#ibcon#enter sib2, iclass 30, count 0 2006.285.09:58:03.02#ibcon#flushed, iclass 30, count 0 2006.285.09:58:03.02#ibcon#about to write, iclass 30, count 0 2006.285.09:58:03.02#ibcon#wrote, iclass 30, count 0 2006.285.09:58:03.02#ibcon#about to read 3, iclass 30, count 0 2006.285.09:58:03.04#ibcon#read 3, iclass 30, count 0 2006.285.09:58:03.04#ibcon#about to read 4, iclass 30, count 0 2006.285.09:58:03.04#ibcon#read 4, iclass 30, count 0 2006.285.09:58:03.04#ibcon#about to read 5, iclass 30, count 0 2006.285.09:58:03.04#ibcon#read 5, iclass 30, count 0 2006.285.09:58:03.04#ibcon#about to read 6, iclass 30, count 0 2006.285.09:58:03.04#ibcon#read 6, iclass 30, count 0 2006.285.09:58:03.04#ibcon#end of sib2, iclass 30, count 0 2006.285.09:58:03.04#ibcon#*mode == 0, iclass 30, count 0 2006.285.09:58:03.04#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.09:58:03.04#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.09:58:03.04#ibcon#*before write, iclass 30, count 0 2006.285.09:58:03.04#ibcon#enter sib2, iclass 30, count 0 2006.285.09:58:03.04#ibcon#flushed, iclass 30, count 0 2006.285.09:58:03.04#ibcon#about to write, iclass 30, count 0 2006.285.09:58:03.04#ibcon#wrote, iclass 30, count 0 2006.285.09:58:03.04#ibcon#about to read 3, iclass 30, count 0 2006.285.09:58:03.08#ibcon#read 3, iclass 30, count 0 2006.285.09:58:03.08#ibcon#about to read 4, iclass 30, count 0 2006.285.09:58:03.08#ibcon#read 4, iclass 30, count 0 2006.285.09:58:03.08#ibcon#about to read 5, iclass 30, count 0 2006.285.09:58:03.08#ibcon#read 5, iclass 30, count 0 2006.285.09:58:03.08#ibcon#about to read 6, iclass 30, count 0 2006.285.09:58:03.08#ibcon#read 6, iclass 30, count 0 2006.285.09:58:03.08#ibcon#end of sib2, iclass 30, count 0 2006.285.09:58:03.08#ibcon#*after write, iclass 30, count 0 2006.285.09:58:03.08#ibcon#*before return 0, iclass 30, count 0 2006.285.09:58:03.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:58:03.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.09:58:03.08#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.09:58:03.08#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.09:58:03.08$vck44/vb=5,4 2006.285.09:58:03.08#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.09:58:03.08#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.09:58:03.08#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:03.08#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:58:03.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:58:03.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:58:03.14#ibcon#enter wrdev, iclass 32, count 2 2006.285.09:58:03.14#ibcon#first serial, iclass 32, count 2 2006.285.09:58:03.14#ibcon#enter sib2, iclass 32, count 2 2006.285.09:58:03.14#ibcon#flushed, iclass 32, count 2 2006.285.09:58:03.14#ibcon#about to write, iclass 32, count 2 2006.285.09:58:03.14#ibcon#wrote, iclass 32, count 2 2006.285.09:58:03.14#ibcon#about to read 3, iclass 32, count 2 2006.285.09:58:03.16#ibcon#read 3, iclass 32, count 2 2006.285.09:58:03.16#ibcon#about to read 4, iclass 32, count 2 2006.285.09:58:03.16#ibcon#read 4, iclass 32, count 2 2006.285.09:58:03.16#ibcon#about to read 5, iclass 32, count 2 2006.285.09:58:03.16#ibcon#read 5, iclass 32, count 2 2006.285.09:58:03.16#ibcon#about to read 6, iclass 32, count 2 2006.285.09:58:03.16#ibcon#read 6, iclass 32, count 2 2006.285.09:58:03.16#ibcon#end of sib2, iclass 32, count 2 2006.285.09:58:03.16#ibcon#*mode == 0, iclass 32, count 2 2006.285.09:58:03.16#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.09:58:03.16#ibcon#[27=AT05-04\r\n] 2006.285.09:58:03.16#ibcon#*before write, iclass 32, count 2 2006.285.09:58:03.16#ibcon#enter sib2, iclass 32, count 2 2006.285.09:58:03.16#ibcon#flushed, iclass 32, count 2 2006.285.09:58:03.16#ibcon#about to write, iclass 32, count 2 2006.285.09:58:03.16#ibcon#wrote, iclass 32, count 2 2006.285.09:58:03.16#ibcon#about to read 3, iclass 32, count 2 2006.285.09:58:03.19#ibcon#read 3, iclass 32, count 2 2006.285.09:58:03.19#ibcon#about to read 4, iclass 32, count 2 2006.285.09:58:03.19#ibcon#read 4, iclass 32, count 2 2006.285.09:58:03.19#ibcon#about to read 5, iclass 32, count 2 2006.285.09:58:03.19#ibcon#read 5, iclass 32, count 2 2006.285.09:58:03.19#ibcon#about to read 6, iclass 32, count 2 2006.285.09:58:03.19#ibcon#read 6, iclass 32, count 2 2006.285.09:58:03.19#ibcon#end of sib2, iclass 32, count 2 2006.285.09:58:03.19#ibcon#*after write, iclass 32, count 2 2006.285.09:58:03.19#ibcon#*before return 0, iclass 32, count 2 2006.285.09:58:03.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:58:03.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.09:58:03.19#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.09:58:03.19#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:03.19#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:58:03.31#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:58:03.31#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:58:03.31#ibcon#enter wrdev, iclass 32, count 0 2006.285.09:58:03.31#ibcon#first serial, iclass 32, count 0 2006.285.09:58:03.31#ibcon#enter sib2, iclass 32, count 0 2006.285.09:58:03.31#ibcon#flushed, iclass 32, count 0 2006.285.09:58:03.31#ibcon#about to write, iclass 32, count 0 2006.285.09:58:03.31#ibcon#wrote, iclass 32, count 0 2006.285.09:58:03.31#ibcon#about to read 3, iclass 32, count 0 2006.285.09:58:03.33#ibcon#read 3, iclass 32, count 0 2006.285.09:58:03.33#ibcon#about to read 4, iclass 32, count 0 2006.285.09:58:03.33#ibcon#read 4, iclass 32, count 0 2006.285.09:58:03.33#ibcon#about to read 5, iclass 32, count 0 2006.285.09:58:03.33#ibcon#read 5, iclass 32, count 0 2006.285.09:58:03.33#ibcon#about to read 6, iclass 32, count 0 2006.285.09:58:03.33#ibcon#read 6, iclass 32, count 0 2006.285.09:58:03.33#ibcon#end of sib2, iclass 32, count 0 2006.285.09:58:03.33#ibcon#*mode == 0, iclass 32, count 0 2006.285.09:58:03.33#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.09:58:03.33#ibcon#[27=USB\r\n] 2006.285.09:58:03.33#ibcon#*before write, iclass 32, count 0 2006.285.09:58:03.33#ibcon#enter sib2, iclass 32, count 0 2006.285.09:58:03.33#ibcon#flushed, iclass 32, count 0 2006.285.09:58:03.33#ibcon#about to write, iclass 32, count 0 2006.285.09:58:03.33#ibcon#wrote, iclass 32, count 0 2006.285.09:58:03.33#ibcon#about to read 3, iclass 32, count 0 2006.285.09:58:03.36#ibcon#read 3, iclass 32, count 0 2006.285.09:58:03.36#ibcon#about to read 4, iclass 32, count 0 2006.285.09:58:03.36#ibcon#read 4, iclass 32, count 0 2006.285.09:58:03.36#ibcon#about to read 5, iclass 32, count 0 2006.285.09:58:03.36#ibcon#read 5, iclass 32, count 0 2006.285.09:58:03.36#ibcon#about to read 6, iclass 32, count 0 2006.285.09:58:03.36#ibcon#read 6, iclass 32, count 0 2006.285.09:58:03.36#ibcon#end of sib2, iclass 32, count 0 2006.285.09:58:03.36#ibcon#*after write, iclass 32, count 0 2006.285.09:58:03.36#ibcon#*before return 0, iclass 32, count 0 2006.285.09:58:03.36#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:58:03.36#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.09:58:03.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.09:58:03.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.09:58:03.36$vck44/vblo=6,719.99 2006.285.09:58:03.36#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.09:58:03.36#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.09:58:03.36#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:03.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:58:03.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:58:03.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:58:03.36#ibcon#enter wrdev, iclass 34, count 0 2006.285.09:58:03.36#ibcon#first serial, iclass 34, count 0 2006.285.09:58:03.36#ibcon#enter sib2, iclass 34, count 0 2006.285.09:58:03.36#ibcon#flushed, iclass 34, count 0 2006.285.09:58:03.36#ibcon#about to write, iclass 34, count 0 2006.285.09:58:03.36#ibcon#wrote, iclass 34, count 0 2006.285.09:58:03.36#ibcon#about to read 3, iclass 34, count 0 2006.285.09:58:03.38#ibcon#read 3, iclass 34, count 0 2006.285.09:58:03.38#ibcon#about to read 4, iclass 34, count 0 2006.285.09:58:03.38#ibcon#read 4, iclass 34, count 0 2006.285.09:58:03.38#ibcon#about to read 5, iclass 34, count 0 2006.285.09:58:03.38#ibcon#read 5, iclass 34, count 0 2006.285.09:58:03.38#ibcon#about to read 6, iclass 34, count 0 2006.285.09:58:03.38#ibcon#read 6, iclass 34, count 0 2006.285.09:58:03.38#ibcon#end of sib2, iclass 34, count 0 2006.285.09:58:03.38#ibcon#*mode == 0, iclass 34, count 0 2006.285.09:58:03.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.09:58:03.38#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.09:58:03.38#ibcon#*before write, iclass 34, count 0 2006.285.09:58:03.38#ibcon#enter sib2, iclass 34, count 0 2006.285.09:58:03.38#ibcon#flushed, iclass 34, count 0 2006.285.09:58:03.38#ibcon#about to write, iclass 34, count 0 2006.285.09:58:03.38#ibcon#wrote, iclass 34, count 0 2006.285.09:58:03.38#ibcon#about to read 3, iclass 34, count 0 2006.285.09:58:03.42#ibcon#read 3, iclass 34, count 0 2006.285.09:58:03.42#ibcon#about to read 4, iclass 34, count 0 2006.285.09:58:03.42#ibcon#read 4, iclass 34, count 0 2006.285.09:58:03.42#ibcon#about to read 5, iclass 34, count 0 2006.285.09:58:03.42#ibcon#read 5, iclass 34, count 0 2006.285.09:58:03.42#ibcon#about to read 6, iclass 34, count 0 2006.285.09:58:03.42#ibcon#read 6, iclass 34, count 0 2006.285.09:58:03.42#ibcon#end of sib2, iclass 34, count 0 2006.285.09:58:03.42#ibcon#*after write, iclass 34, count 0 2006.285.09:58:03.42#ibcon#*before return 0, iclass 34, count 0 2006.285.09:58:03.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:58:03.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.09:58:03.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.09:58:03.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.09:58:03.42$vck44/vb=6,3 2006.285.09:58:03.42#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.09:58:03.42#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.09:58:03.42#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:03.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:58:03.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:58:03.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:58:03.48#ibcon#enter wrdev, iclass 36, count 2 2006.285.09:58:03.48#ibcon#first serial, iclass 36, count 2 2006.285.09:58:03.48#ibcon#enter sib2, iclass 36, count 2 2006.285.09:58:03.48#ibcon#flushed, iclass 36, count 2 2006.285.09:58:03.48#ibcon#about to write, iclass 36, count 2 2006.285.09:58:03.48#ibcon#wrote, iclass 36, count 2 2006.285.09:58:03.48#ibcon#about to read 3, iclass 36, count 2 2006.285.09:58:03.50#ibcon#read 3, iclass 36, count 2 2006.285.09:58:03.50#ibcon#about to read 4, iclass 36, count 2 2006.285.09:58:03.50#ibcon#read 4, iclass 36, count 2 2006.285.09:58:03.50#ibcon#about to read 5, iclass 36, count 2 2006.285.09:58:03.50#ibcon#read 5, iclass 36, count 2 2006.285.09:58:03.50#ibcon#about to read 6, iclass 36, count 2 2006.285.09:58:03.50#ibcon#read 6, iclass 36, count 2 2006.285.09:58:03.50#ibcon#end of sib2, iclass 36, count 2 2006.285.09:58:03.50#ibcon#*mode == 0, iclass 36, count 2 2006.285.09:58:03.50#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.09:58:03.50#ibcon#[27=AT06-03\r\n] 2006.285.09:58:03.50#ibcon#*before write, iclass 36, count 2 2006.285.09:58:03.50#ibcon#enter sib2, iclass 36, count 2 2006.285.09:58:03.50#ibcon#flushed, iclass 36, count 2 2006.285.09:58:03.50#ibcon#about to write, iclass 36, count 2 2006.285.09:58:03.50#ibcon#wrote, iclass 36, count 2 2006.285.09:58:03.50#ibcon#about to read 3, iclass 36, count 2 2006.285.09:58:03.53#ibcon#read 3, iclass 36, count 2 2006.285.09:58:03.53#ibcon#about to read 4, iclass 36, count 2 2006.285.09:58:03.53#ibcon#read 4, iclass 36, count 2 2006.285.09:58:03.53#ibcon#about to read 5, iclass 36, count 2 2006.285.09:58:03.53#ibcon#read 5, iclass 36, count 2 2006.285.09:58:03.53#ibcon#about to read 6, iclass 36, count 2 2006.285.09:58:03.53#ibcon#read 6, iclass 36, count 2 2006.285.09:58:03.53#ibcon#end of sib2, iclass 36, count 2 2006.285.09:58:03.53#ibcon#*after write, iclass 36, count 2 2006.285.09:58:03.53#ibcon#*before return 0, iclass 36, count 2 2006.285.09:58:03.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:58:03.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.09:58:03.53#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.09:58:03.53#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:03.53#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:58:03.65#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:58:03.65#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:58:03.65#ibcon#enter wrdev, iclass 36, count 0 2006.285.09:58:03.65#ibcon#first serial, iclass 36, count 0 2006.285.09:58:03.65#ibcon#enter sib2, iclass 36, count 0 2006.285.09:58:03.65#ibcon#flushed, iclass 36, count 0 2006.285.09:58:03.65#ibcon#about to write, iclass 36, count 0 2006.285.09:58:03.65#ibcon#wrote, iclass 36, count 0 2006.285.09:58:03.65#ibcon#about to read 3, iclass 36, count 0 2006.285.09:58:03.67#ibcon#read 3, iclass 36, count 0 2006.285.09:58:03.67#ibcon#about to read 4, iclass 36, count 0 2006.285.09:58:03.67#ibcon#read 4, iclass 36, count 0 2006.285.09:58:03.67#ibcon#about to read 5, iclass 36, count 0 2006.285.09:58:03.67#ibcon#read 5, iclass 36, count 0 2006.285.09:58:03.67#ibcon#about to read 6, iclass 36, count 0 2006.285.09:58:03.67#ibcon#read 6, iclass 36, count 0 2006.285.09:58:03.67#ibcon#end of sib2, iclass 36, count 0 2006.285.09:58:03.67#ibcon#*mode == 0, iclass 36, count 0 2006.285.09:58:03.67#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.09:58:03.67#ibcon#[27=USB\r\n] 2006.285.09:58:03.67#ibcon#*before write, iclass 36, count 0 2006.285.09:58:03.67#ibcon#enter sib2, iclass 36, count 0 2006.285.09:58:03.67#ibcon#flushed, iclass 36, count 0 2006.285.09:58:03.67#ibcon#about to write, iclass 36, count 0 2006.285.09:58:03.67#ibcon#wrote, iclass 36, count 0 2006.285.09:58:03.67#ibcon#about to read 3, iclass 36, count 0 2006.285.09:58:03.70#ibcon#read 3, iclass 36, count 0 2006.285.09:58:03.70#ibcon#about to read 4, iclass 36, count 0 2006.285.09:58:03.70#ibcon#read 4, iclass 36, count 0 2006.285.09:58:03.70#ibcon#about to read 5, iclass 36, count 0 2006.285.09:58:03.70#ibcon#read 5, iclass 36, count 0 2006.285.09:58:03.70#ibcon#about to read 6, iclass 36, count 0 2006.285.09:58:03.70#ibcon#read 6, iclass 36, count 0 2006.285.09:58:03.70#ibcon#end of sib2, iclass 36, count 0 2006.285.09:58:03.70#ibcon#*after write, iclass 36, count 0 2006.285.09:58:03.70#ibcon#*before return 0, iclass 36, count 0 2006.285.09:58:03.70#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:58:03.70#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.09:58:03.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.09:58:03.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.09:58:03.70$vck44/vblo=7,734.99 2006.285.09:58:03.70#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.09:58:03.70#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.09:58:03.70#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:03.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:58:03.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:58:03.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:58:03.70#ibcon#enter wrdev, iclass 38, count 0 2006.285.09:58:03.70#ibcon#first serial, iclass 38, count 0 2006.285.09:58:03.70#ibcon#enter sib2, iclass 38, count 0 2006.285.09:58:03.70#ibcon#flushed, iclass 38, count 0 2006.285.09:58:03.70#ibcon#about to write, iclass 38, count 0 2006.285.09:58:03.70#ibcon#wrote, iclass 38, count 0 2006.285.09:58:03.70#ibcon#about to read 3, iclass 38, count 0 2006.285.09:58:03.72#ibcon#read 3, iclass 38, count 0 2006.285.09:58:03.72#ibcon#about to read 4, iclass 38, count 0 2006.285.09:58:03.72#ibcon#read 4, iclass 38, count 0 2006.285.09:58:03.72#ibcon#about to read 5, iclass 38, count 0 2006.285.09:58:03.72#ibcon#read 5, iclass 38, count 0 2006.285.09:58:03.72#ibcon#about to read 6, iclass 38, count 0 2006.285.09:58:03.72#ibcon#read 6, iclass 38, count 0 2006.285.09:58:03.72#ibcon#end of sib2, iclass 38, count 0 2006.285.09:58:03.72#ibcon#*mode == 0, iclass 38, count 0 2006.285.09:58:03.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.09:58:03.72#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.09:58:03.72#ibcon#*before write, iclass 38, count 0 2006.285.09:58:03.72#ibcon#enter sib2, iclass 38, count 0 2006.285.09:58:03.72#ibcon#flushed, iclass 38, count 0 2006.285.09:58:03.72#ibcon#about to write, iclass 38, count 0 2006.285.09:58:03.72#ibcon#wrote, iclass 38, count 0 2006.285.09:58:03.72#ibcon#about to read 3, iclass 38, count 0 2006.285.09:58:03.76#ibcon#read 3, iclass 38, count 0 2006.285.09:58:03.76#ibcon#about to read 4, iclass 38, count 0 2006.285.09:58:03.76#ibcon#read 4, iclass 38, count 0 2006.285.09:58:03.76#ibcon#about to read 5, iclass 38, count 0 2006.285.09:58:03.76#ibcon#read 5, iclass 38, count 0 2006.285.09:58:03.76#ibcon#about to read 6, iclass 38, count 0 2006.285.09:58:03.76#ibcon#read 6, iclass 38, count 0 2006.285.09:58:03.76#ibcon#end of sib2, iclass 38, count 0 2006.285.09:58:03.76#ibcon#*after write, iclass 38, count 0 2006.285.09:58:03.76#ibcon#*before return 0, iclass 38, count 0 2006.285.09:58:03.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:58:03.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.09:58:03.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.09:58:03.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.09:58:03.76$vck44/vb=7,4 2006.285.09:58:03.76#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.09:58:03.76#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.09:58:03.76#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:03.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:58:03.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:58:03.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:58:03.82#ibcon#enter wrdev, iclass 40, count 2 2006.285.09:58:03.82#ibcon#first serial, iclass 40, count 2 2006.285.09:58:03.82#ibcon#enter sib2, iclass 40, count 2 2006.285.09:58:03.82#ibcon#flushed, iclass 40, count 2 2006.285.09:58:03.82#ibcon#about to write, iclass 40, count 2 2006.285.09:58:03.82#ibcon#wrote, iclass 40, count 2 2006.285.09:58:03.82#ibcon#about to read 3, iclass 40, count 2 2006.285.09:58:03.84#ibcon#read 3, iclass 40, count 2 2006.285.09:58:03.84#ibcon#about to read 4, iclass 40, count 2 2006.285.09:58:03.84#ibcon#read 4, iclass 40, count 2 2006.285.09:58:03.84#ibcon#about to read 5, iclass 40, count 2 2006.285.09:58:03.84#ibcon#read 5, iclass 40, count 2 2006.285.09:58:03.84#ibcon#about to read 6, iclass 40, count 2 2006.285.09:58:03.84#ibcon#read 6, iclass 40, count 2 2006.285.09:58:03.84#ibcon#end of sib2, iclass 40, count 2 2006.285.09:58:03.84#ibcon#*mode == 0, iclass 40, count 2 2006.285.09:58:03.84#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.09:58:03.84#ibcon#[27=AT07-04\r\n] 2006.285.09:58:03.84#ibcon#*before write, iclass 40, count 2 2006.285.09:58:03.84#ibcon#enter sib2, iclass 40, count 2 2006.285.09:58:03.84#ibcon#flushed, iclass 40, count 2 2006.285.09:58:03.84#ibcon#about to write, iclass 40, count 2 2006.285.09:58:03.84#ibcon#wrote, iclass 40, count 2 2006.285.09:58:03.84#ibcon#about to read 3, iclass 40, count 2 2006.285.09:58:03.87#ibcon#read 3, iclass 40, count 2 2006.285.09:58:03.87#ibcon#about to read 4, iclass 40, count 2 2006.285.09:58:03.87#ibcon#read 4, iclass 40, count 2 2006.285.09:58:03.87#ibcon#about to read 5, iclass 40, count 2 2006.285.09:58:03.87#ibcon#read 5, iclass 40, count 2 2006.285.09:58:03.87#ibcon#about to read 6, iclass 40, count 2 2006.285.09:58:03.87#ibcon#read 6, iclass 40, count 2 2006.285.09:58:03.87#ibcon#end of sib2, iclass 40, count 2 2006.285.09:58:03.87#ibcon#*after write, iclass 40, count 2 2006.285.09:58:03.87#ibcon#*before return 0, iclass 40, count 2 2006.285.09:58:03.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:58:03.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.09:58:03.87#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.09:58:03.87#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:03.87#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:58:03.99#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:58:03.99#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:58:03.99#ibcon#enter wrdev, iclass 40, count 0 2006.285.09:58:03.99#ibcon#first serial, iclass 40, count 0 2006.285.09:58:03.99#ibcon#enter sib2, iclass 40, count 0 2006.285.09:58:03.99#ibcon#flushed, iclass 40, count 0 2006.285.09:58:03.99#ibcon#about to write, iclass 40, count 0 2006.285.09:58:03.99#ibcon#wrote, iclass 40, count 0 2006.285.09:58:03.99#ibcon#about to read 3, iclass 40, count 0 2006.285.09:58:04.01#ibcon#read 3, iclass 40, count 0 2006.285.09:58:04.01#ibcon#about to read 4, iclass 40, count 0 2006.285.09:58:04.01#ibcon#read 4, iclass 40, count 0 2006.285.09:58:04.01#ibcon#about to read 5, iclass 40, count 0 2006.285.09:58:04.01#ibcon#read 5, iclass 40, count 0 2006.285.09:58:04.01#ibcon#about to read 6, iclass 40, count 0 2006.285.09:58:04.01#ibcon#read 6, iclass 40, count 0 2006.285.09:58:04.01#ibcon#end of sib2, iclass 40, count 0 2006.285.09:58:04.01#ibcon#*mode == 0, iclass 40, count 0 2006.285.09:58:04.01#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.09:58:04.01#ibcon#[27=USB\r\n] 2006.285.09:58:04.01#ibcon#*before write, iclass 40, count 0 2006.285.09:58:04.01#ibcon#enter sib2, iclass 40, count 0 2006.285.09:58:04.01#ibcon#flushed, iclass 40, count 0 2006.285.09:58:04.01#ibcon#about to write, iclass 40, count 0 2006.285.09:58:04.01#ibcon#wrote, iclass 40, count 0 2006.285.09:58:04.01#ibcon#about to read 3, iclass 40, count 0 2006.285.09:58:04.04#ibcon#read 3, iclass 40, count 0 2006.285.09:58:04.04#ibcon#about to read 4, iclass 40, count 0 2006.285.09:58:04.04#ibcon#read 4, iclass 40, count 0 2006.285.09:58:04.04#ibcon#about to read 5, iclass 40, count 0 2006.285.09:58:04.04#ibcon#read 5, iclass 40, count 0 2006.285.09:58:04.04#ibcon#about to read 6, iclass 40, count 0 2006.285.09:58:04.04#ibcon#read 6, iclass 40, count 0 2006.285.09:58:04.04#ibcon#end of sib2, iclass 40, count 0 2006.285.09:58:04.04#ibcon#*after write, iclass 40, count 0 2006.285.09:58:04.04#ibcon#*before return 0, iclass 40, count 0 2006.285.09:58:04.04#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:58:04.04#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.09:58:04.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.09:58:04.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.09:58:04.04$vck44/vblo=8,744.99 2006.285.09:58:04.04#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.09:58:04.04#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.09:58:04.04#ibcon#ireg 17 cls_cnt 0 2006.285.09:58:04.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:58:04.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:58:04.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:58:04.04#ibcon#enter wrdev, iclass 4, count 0 2006.285.09:58:04.04#ibcon#first serial, iclass 4, count 0 2006.285.09:58:04.04#ibcon#enter sib2, iclass 4, count 0 2006.285.09:58:04.04#ibcon#flushed, iclass 4, count 0 2006.285.09:58:04.04#ibcon#about to write, iclass 4, count 0 2006.285.09:58:04.04#ibcon#wrote, iclass 4, count 0 2006.285.09:58:04.04#ibcon#about to read 3, iclass 4, count 0 2006.285.09:58:04.06#ibcon#read 3, iclass 4, count 0 2006.285.09:58:04.06#ibcon#about to read 4, iclass 4, count 0 2006.285.09:58:04.06#ibcon#read 4, iclass 4, count 0 2006.285.09:58:04.06#ibcon#about to read 5, iclass 4, count 0 2006.285.09:58:04.06#ibcon#read 5, iclass 4, count 0 2006.285.09:58:04.06#ibcon#about to read 6, iclass 4, count 0 2006.285.09:58:04.06#ibcon#read 6, iclass 4, count 0 2006.285.09:58:04.06#ibcon#end of sib2, iclass 4, count 0 2006.285.09:58:04.06#ibcon#*mode == 0, iclass 4, count 0 2006.285.09:58:04.06#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.09:58:04.06#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.09:58:04.06#ibcon#*before write, iclass 4, count 0 2006.285.09:58:04.06#ibcon#enter sib2, iclass 4, count 0 2006.285.09:58:04.06#ibcon#flushed, iclass 4, count 0 2006.285.09:58:04.06#ibcon#about to write, iclass 4, count 0 2006.285.09:58:04.06#ibcon#wrote, iclass 4, count 0 2006.285.09:58:04.06#ibcon#about to read 3, iclass 4, count 0 2006.285.09:58:04.10#ibcon#read 3, iclass 4, count 0 2006.285.09:58:04.10#ibcon#about to read 4, iclass 4, count 0 2006.285.09:58:04.10#ibcon#read 4, iclass 4, count 0 2006.285.09:58:04.10#ibcon#about to read 5, iclass 4, count 0 2006.285.09:58:04.10#ibcon#read 5, iclass 4, count 0 2006.285.09:58:04.10#ibcon#about to read 6, iclass 4, count 0 2006.285.09:58:04.10#ibcon#read 6, iclass 4, count 0 2006.285.09:58:04.10#ibcon#end of sib2, iclass 4, count 0 2006.285.09:58:04.10#ibcon#*after write, iclass 4, count 0 2006.285.09:58:04.10#ibcon#*before return 0, iclass 4, count 0 2006.285.09:58:04.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:58:04.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.09:58:04.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.09:58:04.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.09:58:04.10$vck44/vb=8,4 2006.285.09:58:04.10#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.09:58:04.10#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.09:58:04.10#ibcon#ireg 11 cls_cnt 2 2006.285.09:58:04.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:58:04.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:58:04.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:58:04.16#ibcon#enter wrdev, iclass 6, count 2 2006.285.09:58:04.16#ibcon#first serial, iclass 6, count 2 2006.285.09:58:04.16#ibcon#enter sib2, iclass 6, count 2 2006.285.09:58:04.16#ibcon#flushed, iclass 6, count 2 2006.285.09:58:04.16#ibcon#about to write, iclass 6, count 2 2006.285.09:58:04.16#ibcon#wrote, iclass 6, count 2 2006.285.09:58:04.16#ibcon#about to read 3, iclass 6, count 2 2006.285.09:58:04.18#ibcon#read 3, iclass 6, count 2 2006.285.09:58:04.18#ibcon#about to read 4, iclass 6, count 2 2006.285.09:58:04.18#ibcon#read 4, iclass 6, count 2 2006.285.09:58:04.18#ibcon#about to read 5, iclass 6, count 2 2006.285.09:58:04.18#ibcon#read 5, iclass 6, count 2 2006.285.09:58:04.18#ibcon#about to read 6, iclass 6, count 2 2006.285.09:58:04.18#ibcon#read 6, iclass 6, count 2 2006.285.09:58:04.18#ibcon#end of sib2, iclass 6, count 2 2006.285.09:58:04.18#ibcon#*mode == 0, iclass 6, count 2 2006.285.09:58:04.18#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.09:58:04.18#ibcon#[27=AT08-04\r\n] 2006.285.09:58:04.18#ibcon#*before write, iclass 6, count 2 2006.285.09:58:04.18#ibcon#enter sib2, iclass 6, count 2 2006.285.09:58:04.18#ibcon#flushed, iclass 6, count 2 2006.285.09:58:04.18#ibcon#about to write, iclass 6, count 2 2006.285.09:58:04.18#ibcon#wrote, iclass 6, count 2 2006.285.09:58:04.18#ibcon#about to read 3, iclass 6, count 2 2006.285.09:58:04.21#ibcon#read 3, iclass 6, count 2 2006.285.09:58:04.21#ibcon#about to read 4, iclass 6, count 2 2006.285.09:58:04.21#ibcon#read 4, iclass 6, count 2 2006.285.09:58:04.21#ibcon#about to read 5, iclass 6, count 2 2006.285.09:58:04.21#ibcon#read 5, iclass 6, count 2 2006.285.09:58:04.21#ibcon#about to read 6, iclass 6, count 2 2006.285.09:58:04.21#ibcon#read 6, iclass 6, count 2 2006.285.09:58:04.21#ibcon#end of sib2, iclass 6, count 2 2006.285.09:58:04.21#ibcon#*after write, iclass 6, count 2 2006.285.09:58:04.21#ibcon#*before return 0, iclass 6, count 2 2006.285.09:58:04.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:58:04.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.09:58:04.21#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.09:58:04.21#ibcon#ireg 7 cls_cnt 0 2006.285.09:58:04.21#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:58:04.33#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:58:04.33#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:58:04.33#ibcon#enter wrdev, iclass 6, count 0 2006.285.09:58:04.33#ibcon#first serial, iclass 6, count 0 2006.285.09:58:04.33#ibcon#enter sib2, iclass 6, count 0 2006.285.09:58:04.33#ibcon#flushed, iclass 6, count 0 2006.285.09:58:04.33#ibcon#about to write, iclass 6, count 0 2006.285.09:58:04.33#ibcon#wrote, iclass 6, count 0 2006.285.09:58:04.33#ibcon#about to read 3, iclass 6, count 0 2006.285.09:58:04.35#ibcon#read 3, iclass 6, count 0 2006.285.09:58:04.35#ibcon#about to read 4, iclass 6, count 0 2006.285.09:58:04.35#ibcon#read 4, iclass 6, count 0 2006.285.09:58:04.35#ibcon#about to read 5, iclass 6, count 0 2006.285.09:58:04.35#ibcon#read 5, iclass 6, count 0 2006.285.09:58:04.35#ibcon#about to read 6, iclass 6, count 0 2006.285.09:58:04.35#ibcon#read 6, iclass 6, count 0 2006.285.09:58:04.35#ibcon#end of sib2, iclass 6, count 0 2006.285.09:58:04.35#ibcon#*mode == 0, iclass 6, count 0 2006.285.09:58:04.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.09:58:04.35#ibcon#[27=USB\r\n] 2006.285.09:58:04.35#ibcon#*before write, iclass 6, count 0 2006.285.09:58:04.35#ibcon#enter sib2, iclass 6, count 0 2006.285.09:58:04.35#ibcon#flushed, iclass 6, count 0 2006.285.09:58:04.35#ibcon#about to write, iclass 6, count 0 2006.285.09:58:04.35#ibcon#wrote, iclass 6, count 0 2006.285.09:58:04.35#ibcon#about to read 3, iclass 6, count 0 2006.285.09:58:04.38#ibcon#read 3, iclass 6, count 0 2006.285.09:58:04.38#ibcon#about to read 4, iclass 6, count 0 2006.285.09:58:04.38#ibcon#read 4, iclass 6, count 0 2006.285.09:58:04.38#ibcon#about to read 5, iclass 6, count 0 2006.285.09:58:04.38#ibcon#read 5, iclass 6, count 0 2006.285.09:58:04.38#ibcon#about to read 6, iclass 6, count 0 2006.285.09:58:04.38#ibcon#read 6, iclass 6, count 0 2006.285.09:58:04.38#ibcon#end of sib2, iclass 6, count 0 2006.285.09:58:04.38#ibcon#*after write, iclass 6, count 0 2006.285.09:58:04.38#ibcon#*before return 0, iclass 6, count 0 2006.285.09:58:04.38#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:58:04.38#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.09:58:04.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.09:58:04.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.09:58:04.38$vck44/vabw=wide 2006.285.09:58:04.38#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.09:58:04.38#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.09:58:04.38#ibcon#ireg 8 cls_cnt 0 2006.285.09:58:04.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:58:04.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:58:04.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:58:04.38#ibcon#enter wrdev, iclass 10, count 0 2006.285.09:58:04.38#ibcon#first serial, iclass 10, count 0 2006.285.09:58:04.38#ibcon#enter sib2, iclass 10, count 0 2006.285.09:58:04.38#ibcon#flushed, iclass 10, count 0 2006.285.09:58:04.38#ibcon#about to write, iclass 10, count 0 2006.285.09:58:04.38#ibcon#wrote, iclass 10, count 0 2006.285.09:58:04.38#ibcon#about to read 3, iclass 10, count 0 2006.285.09:58:04.40#ibcon#read 3, iclass 10, count 0 2006.285.09:58:04.40#ibcon#about to read 4, iclass 10, count 0 2006.285.09:58:04.40#ibcon#read 4, iclass 10, count 0 2006.285.09:58:04.40#ibcon#about to read 5, iclass 10, count 0 2006.285.09:58:04.40#ibcon#read 5, iclass 10, count 0 2006.285.09:58:04.40#ibcon#about to read 6, iclass 10, count 0 2006.285.09:58:04.40#ibcon#read 6, iclass 10, count 0 2006.285.09:58:04.40#ibcon#end of sib2, iclass 10, count 0 2006.285.09:58:04.40#ibcon#*mode == 0, iclass 10, count 0 2006.285.09:58:04.40#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.09:58:04.40#ibcon#[25=BW32\r\n] 2006.285.09:58:04.40#ibcon#*before write, iclass 10, count 0 2006.285.09:58:04.40#ibcon#enter sib2, iclass 10, count 0 2006.285.09:58:04.40#ibcon#flushed, iclass 10, count 0 2006.285.09:58:04.40#ibcon#about to write, iclass 10, count 0 2006.285.09:58:04.40#ibcon#wrote, iclass 10, count 0 2006.285.09:58:04.40#ibcon#about to read 3, iclass 10, count 0 2006.285.09:58:04.43#ibcon#read 3, iclass 10, count 0 2006.285.09:58:04.43#ibcon#about to read 4, iclass 10, count 0 2006.285.09:58:04.43#ibcon#read 4, iclass 10, count 0 2006.285.09:58:04.43#ibcon#about to read 5, iclass 10, count 0 2006.285.09:58:04.43#ibcon#read 5, iclass 10, count 0 2006.285.09:58:04.43#ibcon#about to read 6, iclass 10, count 0 2006.285.09:58:04.43#ibcon#read 6, iclass 10, count 0 2006.285.09:58:04.43#ibcon#end of sib2, iclass 10, count 0 2006.285.09:58:04.43#ibcon#*after write, iclass 10, count 0 2006.285.09:58:04.43#ibcon#*before return 0, iclass 10, count 0 2006.285.09:58:04.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:58:04.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.09:58:04.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.09:58:04.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.09:58:04.43$vck44/vbbw=wide 2006.285.09:58:04.43#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.09:58:04.43#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.09:58:04.43#ibcon#ireg 8 cls_cnt 0 2006.285.09:58:04.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:58:04.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:58:04.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:58:04.50#ibcon#enter wrdev, iclass 12, count 0 2006.285.09:58:04.50#ibcon#first serial, iclass 12, count 0 2006.285.09:58:04.50#ibcon#enter sib2, iclass 12, count 0 2006.285.09:58:04.50#ibcon#flushed, iclass 12, count 0 2006.285.09:58:04.50#ibcon#about to write, iclass 12, count 0 2006.285.09:58:04.50#ibcon#wrote, iclass 12, count 0 2006.285.09:58:04.50#ibcon#about to read 3, iclass 12, count 0 2006.285.09:58:04.52#ibcon#read 3, iclass 12, count 0 2006.285.09:58:04.52#ibcon#about to read 4, iclass 12, count 0 2006.285.09:58:04.52#ibcon#read 4, iclass 12, count 0 2006.285.09:58:04.52#ibcon#about to read 5, iclass 12, count 0 2006.285.09:58:04.52#ibcon#read 5, iclass 12, count 0 2006.285.09:58:04.52#ibcon#about to read 6, iclass 12, count 0 2006.285.09:58:04.52#ibcon#read 6, iclass 12, count 0 2006.285.09:58:04.52#ibcon#end of sib2, iclass 12, count 0 2006.285.09:58:04.52#ibcon#*mode == 0, iclass 12, count 0 2006.285.09:58:04.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.09:58:04.52#ibcon#[27=BW32\r\n] 2006.285.09:58:04.52#ibcon#*before write, iclass 12, count 0 2006.285.09:58:04.52#ibcon#enter sib2, iclass 12, count 0 2006.285.09:58:04.52#ibcon#flushed, iclass 12, count 0 2006.285.09:58:04.52#ibcon#about to write, iclass 12, count 0 2006.285.09:58:04.52#ibcon#wrote, iclass 12, count 0 2006.285.09:58:04.52#ibcon#about to read 3, iclass 12, count 0 2006.285.09:58:04.55#ibcon#read 3, iclass 12, count 0 2006.285.09:58:04.55#ibcon#about to read 4, iclass 12, count 0 2006.285.09:58:04.55#ibcon#read 4, iclass 12, count 0 2006.285.09:58:04.55#ibcon#about to read 5, iclass 12, count 0 2006.285.09:58:04.55#ibcon#read 5, iclass 12, count 0 2006.285.09:58:04.55#ibcon#about to read 6, iclass 12, count 0 2006.285.09:58:04.55#ibcon#read 6, iclass 12, count 0 2006.285.09:58:04.55#ibcon#end of sib2, iclass 12, count 0 2006.285.09:58:04.55#ibcon#*after write, iclass 12, count 0 2006.285.09:58:04.55#ibcon#*before return 0, iclass 12, count 0 2006.285.09:58:04.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:58:04.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.09:58:04.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.09:58:04.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.09:58:04.55$setupk4/ifdk4 2006.285.09:58:04.55$ifdk4/lo= 2006.285.09:58:04.55$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.09:58:04.55$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.09:58:04.55$ifdk4/patch= 2006.285.09:58:04.55$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.09:58:04.55$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.09:58:04.55$setupk4/!*+20s 2006.285.09:58:10.67#abcon#<5=/05 1.2 1.7 19.38 941015.1\r\n> 2006.285.09:58:10.69#abcon#{5=INTERFACE CLEAR} 2006.285.09:58:10.75#abcon#[5=S1D000X0/0*\r\n] 2006.285.09:58:19.06$setupk4/"tpicd 2006.285.09:58:19.06$setupk4/echo=off 2006.285.09:58:19.06$setupk4/xlog=off 2006.285.09:58:19.06:!2006.285.10:01:20 2006.285.09:58:42.14#trakl#Source acquired 2006.285.09:58:43.14#flagr#flagr/antenna,acquired 2006.285.10:01:20.02:preob 2006.285.10:01:21.14/onsource/TRACKING 2006.285.10:01:21.14:!2006.285.10:01:30 2006.285.10:01:30.02:"tape 2006.285.10:01:30.02:"st=record 2006.285.10:01:30.02:data_valid=on 2006.285.10:01:30.02:midob 2006.285.10:01:31.14/onsource/TRACKING 2006.285.10:01:31.14/wx/19.41,1015.1,93 2006.285.10:01:31.31/cable/+6.4847E-03 2006.285.10:01:32.40/va/01,07,usb,yes,35,38 2006.285.10:01:32.40/va/02,06,usb,yes,35,36 2006.285.10:01:32.40/va/03,07,usb,yes,35,37 2006.285.10:01:32.40/va/04,06,usb,yes,36,38 2006.285.10:01:32.40/va/05,03,usb,yes,36,36 2006.285.10:01:32.40/va/06,04,usb,yes,32,32 2006.285.10:01:32.40/va/07,04,usb,yes,33,33 2006.285.10:01:32.40/va/08,03,usb,yes,33,41 2006.285.10:01:32.63/valo/01,524.99,yes,locked 2006.285.10:01:32.63/valo/02,534.99,yes,locked 2006.285.10:01:32.63/valo/03,564.99,yes,locked 2006.285.10:01:32.63/valo/04,624.99,yes,locked 2006.285.10:01:32.63/valo/05,734.99,yes,locked 2006.285.10:01:32.63/valo/06,814.99,yes,locked 2006.285.10:01:32.63/valo/07,864.99,yes,locked 2006.285.10:01:32.63/valo/08,884.99,yes,locked 2006.285.10:01:33.72/vb/01,04,usb,yes,32,30 2006.285.10:01:33.72/vb/02,05,usb,yes,31,30 2006.285.10:01:33.72/vb/03,04,usb,yes,32,35 2006.285.10:01:33.72/vb/04,05,usb,yes,32,31 2006.285.10:01:33.72/vb/05,04,usb,yes,28,31 2006.285.10:01:33.72/vb/06,03,usb,yes,40,36 2006.285.10:01:33.72/vb/07,04,usb,yes,33,33 2006.285.10:01:33.72/vb/08,04,usb,yes,30,33 2006.285.10:01:33.95/vblo/01,629.99,yes,locked 2006.285.10:01:33.95/vblo/02,634.99,yes,locked 2006.285.10:01:33.95/vblo/03,649.99,yes,locked 2006.285.10:01:33.95/vblo/04,679.99,yes,locked 2006.285.10:01:33.95/vblo/05,709.99,yes,locked 2006.285.10:01:33.95/vblo/06,719.99,yes,locked 2006.285.10:01:33.95/vblo/07,734.99,yes,locked 2006.285.10:01:33.95/vblo/08,744.99,yes,locked 2006.285.10:01:34.09/vabw/8 2006.285.10:01:34.25/vbbw/8 2006.285.10:01:34.34/xfe/off,on,12.2 2006.285.10:01:34.72/ifatt/23,28,28,28 2006.285.10:01:35.08/fmout-gps/S +2.49E-07 2006.285.10:01:35.09:!2006.285.10:02:10 2006.285.10:02:10.02:data_valid=off 2006.285.10:02:10.02:"et 2006.285.10:02:10.02:!+3s 2006.285.10:02:13.04:"tape 2006.285.10:02:13.05:postob 2006.285.10:02:13.15/cable/+6.4842E-03 2006.285.10:02:13.15/wx/19.42,1015.1,93 2006.285.10:02:13.20/fmout-gps/S +2.52E-07 2006.285.10:02:13.21:scan_name=285-1006,jd0610,70 2006.285.10:02:13.21:source=2136+141,213901.31,142336.0,2000.0,cw 2006.285.10:02:14.15#flagr#flagr/antenna,new-source 2006.285.10:02:14.15:checkk5 2006.285.10:02:14.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:02:14.91/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:02:15.54/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:02:15.89/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:02:16.28/chk_obsdata//k5ts1/T2851001??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.10:02:21.68/chk_obsdata//k5ts2/T2851001??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.10:02:22.27/chk_obsdata//k5ts3/T2851001??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.10:02:22.64/chk_obsdata//k5ts4/T2851001??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.10:02:23.51/k5log//k5ts1_log_newline 2006.285.10:02:24.27/k5log//k5ts2_log_newline 2006.285.10:02:25.06/k5log//k5ts3_log_newline 2006.285.10:02:25.83/k5log//k5ts4_log_newline 2006.285.10:02:25.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:02:25.85:setupk4=1 2006.285.10:02:25.85$setupk4/echo=on 2006.285.10:02:25.85$setupk4/pcalon 2006.285.10:02:25.85$pcalon/"no phase cal control is implemented here 2006.285.10:02:25.85$setupk4/"tpicd=stop 2006.285.10:02:25.85$setupk4/"rec=synch_on 2006.285.10:02:25.85$setupk4/"rec_mode=128 2006.285.10:02:25.85$setupk4/!* 2006.285.10:02:25.85$setupk4/recpk4 2006.285.10:02:25.85$recpk4/recpatch= 2006.285.10:02:25.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:02:25.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:02:25.86$setupk4/vck44 2006.285.10:02:25.86$vck44/valo=1,524.99 2006.285.10:02:25.86#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.10:02:25.86#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.10:02:25.86#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:25.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:02:25.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:02:25.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:02:25.86#ibcon#enter wrdev, iclass 13, count 0 2006.285.10:02:25.86#ibcon#first serial, iclass 13, count 0 2006.285.10:02:25.86#ibcon#enter sib2, iclass 13, count 0 2006.285.10:02:25.86#ibcon#flushed, iclass 13, count 0 2006.285.10:02:25.86#ibcon#about to write, iclass 13, count 0 2006.285.10:02:25.86#ibcon#wrote, iclass 13, count 0 2006.285.10:02:25.86#ibcon#about to read 3, iclass 13, count 0 2006.285.10:02:25.87#ibcon#read 3, iclass 13, count 0 2006.285.10:02:25.87#ibcon#about to read 4, iclass 13, count 0 2006.285.10:02:25.87#ibcon#read 4, iclass 13, count 0 2006.285.10:02:25.87#ibcon#about to read 5, iclass 13, count 0 2006.285.10:02:25.87#ibcon#read 5, iclass 13, count 0 2006.285.10:02:25.87#ibcon#about to read 6, iclass 13, count 0 2006.285.10:02:25.87#ibcon#read 6, iclass 13, count 0 2006.285.10:02:25.87#ibcon#end of sib2, iclass 13, count 0 2006.285.10:02:25.87#ibcon#*mode == 0, iclass 13, count 0 2006.285.10:02:25.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.10:02:25.87#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:02:25.87#ibcon#*before write, iclass 13, count 0 2006.285.10:02:25.87#ibcon#enter sib2, iclass 13, count 0 2006.285.10:02:25.87#ibcon#flushed, iclass 13, count 0 2006.285.10:02:25.87#ibcon#about to write, iclass 13, count 0 2006.285.10:02:25.87#ibcon#wrote, iclass 13, count 0 2006.285.10:02:25.87#ibcon#about to read 3, iclass 13, count 0 2006.285.10:02:25.92#ibcon#read 3, iclass 13, count 0 2006.285.10:02:25.92#ibcon#about to read 4, iclass 13, count 0 2006.285.10:02:25.92#ibcon#read 4, iclass 13, count 0 2006.285.10:02:25.92#ibcon#about to read 5, iclass 13, count 0 2006.285.10:02:25.92#ibcon#read 5, iclass 13, count 0 2006.285.10:02:25.92#ibcon#about to read 6, iclass 13, count 0 2006.285.10:02:25.92#ibcon#read 6, iclass 13, count 0 2006.285.10:02:25.92#ibcon#end of sib2, iclass 13, count 0 2006.285.10:02:25.92#ibcon#*after write, iclass 13, count 0 2006.285.10:02:25.92#ibcon#*before return 0, iclass 13, count 0 2006.285.10:02:25.92#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:02:25.92#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:02:25.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.10:02:25.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.10:02:25.93$vck44/va=1,7 2006.285.10:02:25.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.10:02:25.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.10:02:25.93#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:25.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:02:25.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:02:25.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:02:25.93#ibcon#enter wrdev, iclass 15, count 2 2006.285.10:02:25.93#ibcon#first serial, iclass 15, count 2 2006.285.10:02:25.93#ibcon#enter sib2, iclass 15, count 2 2006.285.10:02:25.93#ibcon#flushed, iclass 15, count 2 2006.285.10:02:25.93#ibcon#about to write, iclass 15, count 2 2006.285.10:02:25.93#ibcon#wrote, iclass 15, count 2 2006.285.10:02:25.93#ibcon#about to read 3, iclass 15, count 2 2006.285.10:02:25.94#ibcon#read 3, iclass 15, count 2 2006.285.10:02:25.94#ibcon#about to read 4, iclass 15, count 2 2006.285.10:02:25.94#ibcon#read 4, iclass 15, count 2 2006.285.10:02:25.94#ibcon#about to read 5, iclass 15, count 2 2006.285.10:02:25.94#ibcon#read 5, iclass 15, count 2 2006.285.10:02:25.94#ibcon#about to read 6, iclass 15, count 2 2006.285.10:02:25.94#ibcon#read 6, iclass 15, count 2 2006.285.10:02:25.94#ibcon#end of sib2, iclass 15, count 2 2006.285.10:02:25.94#ibcon#*mode == 0, iclass 15, count 2 2006.285.10:02:25.94#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.10:02:25.94#ibcon#[25=AT01-07\r\n] 2006.285.10:02:25.94#ibcon#*before write, iclass 15, count 2 2006.285.10:02:25.94#ibcon#enter sib2, iclass 15, count 2 2006.285.10:02:25.94#ibcon#flushed, iclass 15, count 2 2006.285.10:02:25.94#ibcon#about to write, iclass 15, count 2 2006.285.10:02:25.94#ibcon#wrote, iclass 15, count 2 2006.285.10:02:25.94#ibcon#about to read 3, iclass 15, count 2 2006.285.10:02:25.97#ibcon#read 3, iclass 15, count 2 2006.285.10:02:25.97#ibcon#about to read 4, iclass 15, count 2 2006.285.10:02:25.97#ibcon#read 4, iclass 15, count 2 2006.285.10:02:25.97#ibcon#about to read 5, iclass 15, count 2 2006.285.10:02:25.97#ibcon#read 5, iclass 15, count 2 2006.285.10:02:25.97#ibcon#about to read 6, iclass 15, count 2 2006.285.10:02:25.97#ibcon#read 6, iclass 15, count 2 2006.285.10:02:25.97#ibcon#end of sib2, iclass 15, count 2 2006.285.10:02:25.97#ibcon#*after write, iclass 15, count 2 2006.285.10:02:25.97#ibcon#*before return 0, iclass 15, count 2 2006.285.10:02:25.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:02:25.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:02:25.97#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.10:02:25.97#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:25.97#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:02:26.09#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:02:26.09#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:02:26.09#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:02:26.09#ibcon#first serial, iclass 15, count 0 2006.285.10:02:26.09#ibcon#enter sib2, iclass 15, count 0 2006.285.10:02:26.09#ibcon#flushed, iclass 15, count 0 2006.285.10:02:26.09#ibcon#about to write, iclass 15, count 0 2006.285.10:02:26.09#ibcon#wrote, iclass 15, count 0 2006.285.10:02:26.09#ibcon#about to read 3, iclass 15, count 0 2006.285.10:02:26.11#ibcon#read 3, iclass 15, count 0 2006.285.10:02:26.11#ibcon#about to read 4, iclass 15, count 0 2006.285.10:02:26.11#ibcon#read 4, iclass 15, count 0 2006.285.10:02:26.11#ibcon#about to read 5, iclass 15, count 0 2006.285.10:02:26.11#ibcon#read 5, iclass 15, count 0 2006.285.10:02:26.11#ibcon#about to read 6, iclass 15, count 0 2006.285.10:02:26.11#ibcon#read 6, iclass 15, count 0 2006.285.10:02:26.11#ibcon#end of sib2, iclass 15, count 0 2006.285.10:02:26.11#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:02:26.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:02:26.11#ibcon#[25=USB\r\n] 2006.285.10:02:26.11#ibcon#*before write, iclass 15, count 0 2006.285.10:02:26.11#ibcon#enter sib2, iclass 15, count 0 2006.285.10:02:26.11#ibcon#flushed, iclass 15, count 0 2006.285.10:02:26.11#ibcon#about to write, iclass 15, count 0 2006.285.10:02:26.11#ibcon#wrote, iclass 15, count 0 2006.285.10:02:26.11#ibcon#about to read 3, iclass 15, count 0 2006.285.10:02:26.15#ibcon#read 3, iclass 15, count 0 2006.285.10:02:26.15#ibcon#about to read 4, iclass 15, count 0 2006.285.10:02:26.15#ibcon#read 4, iclass 15, count 0 2006.285.10:02:26.15#ibcon#about to read 5, iclass 15, count 0 2006.285.10:02:26.15#ibcon#read 5, iclass 15, count 0 2006.285.10:02:26.15#ibcon#about to read 6, iclass 15, count 0 2006.285.10:02:26.15#ibcon#read 6, iclass 15, count 0 2006.285.10:02:26.15#ibcon#end of sib2, iclass 15, count 0 2006.285.10:02:26.15#ibcon#*after write, iclass 15, count 0 2006.285.10:02:26.15#ibcon#*before return 0, iclass 15, count 0 2006.285.10:02:26.15#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:02:26.15#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:02:26.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:02:26.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:02:26.15$vck44/valo=2,534.99 2006.285.10:02:26.15#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.10:02:26.15#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.10:02:26.15#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:26.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:02:26.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:02:26.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:02:26.15#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:02:26.15#ibcon#first serial, iclass 17, count 0 2006.285.10:02:26.15#ibcon#enter sib2, iclass 17, count 0 2006.285.10:02:26.15#ibcon#flushed, iclass 17, count 0 2006.285.10:02:26.15#ibcon#about to write, iclass 17, count 0 2006.285.10:02:26.15#ibcon#wrote, iclass 17, count 0 2006.285.10:02:26.15#ibcon#about to read 3, iclass 17, count 0 2006.285.10:02:26.16#ibcon#read 3, iclass 17, count 0 2006.285.10:02:26.16#ibcon#about to read 4, iclass 17, count 0 2006.285.10:02:26.16#ibcon#read 4, iclass 17, count 0 2006.285.10:02:26.16#ibcon#about to read 5, iclass 17, count 0 2006.285.10:02:26.16#ibcon#read 5, iclass 17, count 0 2006.285.10:02:26.16#ibcon#about to read 6, iclass 17, count 0 2006.285.10:02:26.16#ibcon#read 6, iclass 17, count 0 2006.285.10:02:26.16#ibcon#end of sib2, iclass 17, count 0 2006.285.10:02:26.16#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:02:26.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:02:26.16#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:02:26.16#ibcon#*before write, iclass 17, count 0 2006.285.10:02:26.16#ibcon#enter sib2, iclass 17, count 0 2006.285.10:02:26.16#ibcon#flushed, iclass 17, count 0 2006.285.10:02:26.16#ibcon#about to write, iclass 17, count 0 2006.285.10:02:26.16#ibcon#wrote, iclass 17, count 0 2006.285.10:02:26.16#ibcon#about to read 3, iclass 17, count 0 2006.285.10:02:26.20#ibcon#read 3, iclass 17, count 0 2006.285.10:02:26.20#ibcon#about to read 4, iclass 17, count 0 2006.285.10:02:26.20#ibcon#read 4, iclass 17, count 0 2006.285.10:02:26.20#ibcon#about to read 5, iclass 17, count 0 2006.285.10:02:26.20#ibcon#read 5, iclass 17, count 0 2006.285.10:02:26.20#ibcon#about to read 6, iclass 17, count 0 2006.285.10:02:26.20#ibcon#read 6, iclass 17, count 0 2006.285.10:02:26.20#ibcon#end of sib2, iclass 17, count 0 2006.285.10:02:26.20#ibcon#*after write, iclass 17, count 0 2006.285.10:02:26.20#ibcon#*before return 0, iclass 17, count 0 2006.285.10:02:26.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:02:26.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:02:26.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:02:26.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:02:26.21$vck44/va=2,6 2006.285.10:02:26.21#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.10:02:26.21#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.10:02:26.21#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:26.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:02:26.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:02:26.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:02:26.26#ibcon#enter wrdev, iclass 19, count 2 2006.285.10:02:26.26#ibcon#first serial, iclass 19, count 2 2006.285.10:02:26.26#ibcon#enter sib2, iclass 19, count 2 2006.285.10:02:26.26#ibcon#flushed, iclass 19, count 2 2006.285.10:02:26.26#ibcon#about to write, iclass 19, count 2 2006.285.10:02:26.26#ibcon#wrote, iclass 19, count 2 2006.285.10:02:26.26#ibcon#about to read 3, iclass 19, count 2 2006.285.10:02:26.28#ibcon#read 3, iclass 19, count 2 2006.285.10:02:26.28#ibcon#about to read 4, iclass 19, count 2 2006.285.10:02:26.28#ibcon#read 4, iclass 19, count 2 2006.285.10:02:26.28#ibcon#about to read 5, iclass 19, count 2 2006.285.10:02:26.28#ibcon#read 5, iclass 19, count 2 2006.285.10:02:26.28#ibcon#about to read 6, iclass 19, count 2 2006.285.10:02:26.28#ibcon#read 6, iclass 19, count 2 2006.285.10:02:26.28#ibcon#end of sib2, iclass 19, count 2 2006.285.10:02:26.28#ibcon#*mode == 0, iclass 19, count 2 2006.285.10:02:26.28#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.10:02:26.28#ibcon#[25=AT02-06\r\n] 2006.285.10:02:26.28#ibcon#*before write, iclass 19, count 2 2006.285.10:02:26.28#ibcon#enter sib2, iclass 19, count 2 2006.285.10:02:26.28#ibcon#flushed, iclass 19, count 2 2006.285.10:02:26.28#ibcon#about to write, iclass 19, count 2 2006.285.10:02:26.29#ibcon#wrote, iclass 19, count 2 2006.285.10:02:26.29#ibcon#about to read 3, iclass 19, count 2 2006.285.10:02:26.31#ibcon#read 3, iclass 19, count 2 2006.285.10:02:26.31#ibcon#about to read 4, iclass 19, count 2 2006.285.10:02:26.31#ibcon#read 4, iclass 19, count 2 2006.285.10:02:26.31#ibcon#about to read 5, iclass 19, count 2 2006.285.10:02:26.31#ibcon#read 5, iclass 19, count 2 2006.285.10:02:26.31#ibcon#about to read 6, iclass 19, count 2 2006.285.10:02:26.31#ibcon#read 6, iclass 19, count 2 2006.285.10:02:26.31#ibcon#end of sib2, iclass 19, count 2 2006.285.10:02:26.31#ibcon#*after write, iclass 19, count 2 2006.285.10:02:26.31#ibcon#*before return 0, iclass 19, count 2 2006.285.10:02:26.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:02:26.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:02:26.31#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.10:02:26.32#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:26.32#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:02:26.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:02:26.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:02:26.42#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:02:26.42#ibcon#first serial, iclass 19, count 0 2006.285.10:02:26.42#ibcon#enter sib2, iclass 19, count 0 2006.285.10:02:26.42#ibcon#flushed, iclass 19, count 0 2006.285.10:02:26.42#ibcon#about to write, iclass 19, count 0 2006.285.10:02:26.42#ibcon#wrote, iclass 19, count 0 2006.285.10:02:26.42#ibcon#about to read 3, iclass 19, count 0 2006.285.10:02:26.44#ibcon#read 3, iclass 19, count 0 2006.285.10:02:26.44#ibcon#about to read 4, iclass 19, count 0 2006.285.10:02:26.44#ibcon#read 4, iclass 19, count 0 2006.285.10:02:26.44#ibcon#about to read 5, iclass 19, count 0 2006.285.10:02:26.44#ibcon#read 5, iclass 19, count 0 2006.285.10:02:26.44#ibcon#about to read 6, iclass 19, count 0 2006.285.10:02:26.44#ibcon#read 6, iclass 19, count 0 2006.285.10:02:26.44#ibcon#end of sib2, iclass 19, count 0 2006.285.10:02:26.44#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:02:26.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:02:26.44#ibcon#[25=USB\r\n] 2006.285.10:02:26.44#ibcon#*before write, iclass 19, count 0 2006.285.10:02:26.44#ibcon#enter sib2, iclass 19, count 0 2006.285.10:02:26.44#ibcon#flushed, iclass 19, count 0 2006.285.10:02:26.44#ibcon#about to write, iclass 19, count 0 2006.285.10:02:26.44#ibcon#wrote, iclass 19, count 0 2006.285.10:02:26.44#ibcon#about to read 3, iclass 19, count 0 2006.285.10:02:26.47#ibcon#read 3, iclass 19, count 0 2006.285.10:02:26.47#ibcon#about to read 4, iclass 19, count 0 2006.285.10:02:26.47#ibcon#read 4, iclass 19, count 0 2006.285.10:02:26.47#ibcon#about to read 5, iclass 19, count 0 2006.285.10:02:26.47#ibcon#read 5, iclass 19, count 0 2006.285.10:02:26.47#ibcon#about to read 6, iclass 19, count 0 2006.285.10:02:26.47#ibcon#read 6, iclass 19, count 0 2006.285.10:02:26.47#ibcon#end of sib2, iclass 19, count 0 2006.285.10:02:26.47#ibcon#*after write, iclass 19, count 0 2006.285.10:02:26.47#ibcon#*before return 0, iclass 19, count 0 2006.285.10:02:26.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:02:26.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:02:26.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:02:26.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:02:26.48$vck44/valo=3,564.99 2006.285.10:02:26.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.10:02:26.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.10:02:26.48#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:26.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:02:26.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:02:26.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:02:26.48#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:02:26.48#ibcon#first serial, iclass 21, count 0 2006.285.10:02:26.48#ibcon#enter sib2, iclass 21, count 0 2006.285.10:02:26.48#ibcon#flushed, iclass 21, count 0 2006.285.10:02:26.48#ibcon#about to write, iclass 21, count 0 2006.285.10:02:26.48#ibcon#wrote, iclass 21, count 0 2006.285.10:02:26.48#ibcon#about to read 3, iclass 21, count 0 2006.285.10:02:26.49#ibcon#read 3, iclass 21, count 0 2006.285.10:02:26.49#ibcon#about to read 4, iclass 21, count 0 2006.285.10:02:26.49#ibcon#read 4, iclass 21, count 0 2006.285.10:02:26.49#ibcon#about to read 5, iclass 21, count 0 2006.285.10:02:26.49#ibcon#read 5, iclass 21, count 0 2006.285.10:02:26.49#ibcon#about to read 6, iclass 21, count 0 2006.285.10:02:26.49#ibcon#read 6, iclass 21, count 0 2006.285.10:02:26.49#ibcon#end of sib2, iclass 21, count 0 2006.285.10:02:26.49#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:02:26.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:02:26.49#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:02:26.49#ibcon#*before write, iclass 21, count 0 2006.285.10:02:26.49#ibcon#enter sib2, iclass 21, count 0 2006.285.10:02:26.49#ibcon#flushed, iclass 21, count 0 2006.285.10:02:26.49#ibcon#about to write, iclass 21, count 0 2006.285.10:02:26.49#ibcon#wrote, iclass 21, count 0 2006.285.10:02:26.50#ibcon#about to read 3, iclass 21, count 0 2006.285.10:02:26.53#ibcon#read 3, iclass 21, count 0 2006.285.10:02:26.53#ibcon#about to read 4, iclass 21, count 0 2006.285.10:02:26.53#ibcon#read 4, iclass 21, count 0 2006.285.10:02:26.53#ibcon#about to read 5, iclass 21, count 0 2006.285.10:02:26.53#ibcon#read 5, iclass 21, count 0 2006.285.10:02:26.53#ibcon#about to read 6, iclass 21, count 0 2006.285.10:02:26.53#ibcon#read 6, iclass 21, count 0 2006.285.10:02:26.53#ibcon#end of sib2, iclass 21, count 0 2006.285.10:02:26.53#ibcon#*after write, iclass 21, count 0 2006.285.10:02:26.53#ibcon#*before return 0, iclass 21, count 0 2006.285.10:02:26.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:02:26.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:02:26.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:02:26.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:02:26.54$vck44/va=3,7 2006.285.10:02:26.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.10:02:26.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.10:02:26.54#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:26.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:02:26.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:02:26.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:02:26.58#ibcon#enter wrdev, iclass 23, count 2 2006.285.10:02:26.58#ibcon#first serial, iclass 23, count 2 2006.285.10:02:26.58#ibcon#enter sib2, iclass 23, count 2 2006.285.10:02:26.58#ibcon#flushed, iclass 23, count 2 2006.285.10:02:26.58#ibcon#about to write, iclass 23, count 2 2006.285.10:02:26.58#ibcon#wrote, iclass 23, count 2 2006.285.10:02:26.58#ibcon#about to read 3, iclass 23, count 2 2006.285.10:02:26.60#ibcon#read 3, iclass 23, count 2 2006.285.10:02:26.60#ibcon#about to read 4, iclass 23, count 2 2006.285.10:02:26.60#ibcon#read 4, iclass 23, count 2 2006.285.10:02:26.60#ibcon#about to read 5, iclass 23, count 2 2006.285.10:02:26.60#ibcon#read 5, iclass 23, count 2 2006.285.10:02:26.60#ibcon#about to read 6, iclass 23, count 2 2006.285.10:02:26.60#ibcon#read 6, iclass 23, count 2 2006.285.10:02:26.60#ibcon#end of sib2, iclass 23, count 2 2006.285.10:02:26.60#ibcon#*mode == 0, iclass 23, count 2 2006.285.10:02:26.60#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.10:02:26.60#ibcon#[25=AT03-07\r\n] 2006.285.10:02:26.60#ibcon#*before write, iclass 23, count 2 2006.285.10:02:26.60#ibcon#enter sib2, iclass 23, count 2 2006.285.10:02:26.60#ibcon#flushed, iclass 23, count 2 2006.285.10:02:26.60#ibcon#about to write, iclass 23, count 2 2006.285.10:02:26.60#ibcon#wrote, iclass 23, count 2 2006.285.10:02:26.60#ibcon#about to read 3, iclass 23, count 2 2006.285.10:02:26.63#ibcon#read 3, iclass 23, count 2 2006.285.10:02:26.63#ibcon#about to read 4, iclass 23, count 2 2006.285.10:02:26.63#ibcon#read 4, iclass 23, count 2 2006.285.10:02:26.63#ibcon#about to read 5, iclass 23, count 2 2006.285.10:02:26.63#ibcon#read 5, iclass 23, count 2 2006.285.10:02:26.63#ibcon#about to read 6, iclass 23, count 2 2006.285.10:02:26.63#ibcon#read 6, iclass 23, count 2 2006.285.10:02:26.63#ibcon#end of sib2, iclass 23, count 2 2006.285.10:02:26.63#ibcon#*after write, iclass 23, count 2 2006.285.10:02:26.63#ibcon#*before return 0, iclass 23, count 2 2006.285.10:02:26.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:02:26.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:02:26.63#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.10:02:26.63#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:26.63#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:02:26.75#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:02:26.75#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:02:26.75#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:02:26.75#ibcon#first serial, iclass 23, count 0 2006.285.10:02:26.75#ibcon#enter sib2, iclass 23, count 0 2006.285.10:02:26.75#ibcon#flushed, iclass 23, count 0 2006.285.10:02:26.75#ibcon#about to write, iclass 23, count 0 2006.285.10:02:26.75#ibcon#wrote, iclass 23, count 0 2006.285.10:02:26.75#ibcon#about to read 3, iclass 23, count 0 2006.285.10:02:26.77#ibcon#read 3, iclass 23, count 0 2006.285.10:02:26.77#ibcon#about to read 4, iclass 23, count 0 2006.285.10:02:26.77#ibcon#read 4, iclass 23, count 0 2006.285.10:02:26.77#ibcon#about to read 5, iclass 23, count 0 2006.285.10:02:26.77#ibcon#read 5, iclass 23, count 0 2006.285.10:02:26.77#ibcon#about to read 6, iclass 23, count 0 2006.285.10:02:26.77#ibcon#read 6, iclass 23, count 0 2006.285.10:02:26.77#ibcon#end of sib2, iclass 23, count 0 2006.285.10:02:26.77#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:02:26.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:02:26.77#ibcon#[25=USB\r\n] 2006.285.10:02:26.77#ibcon#*before write, iclass 23, count 0 2006.285.10:02:26.77#ibcon#enter sib2, iclass 23, count 0 2006.285.10:02:26.77#ibcon#flushed, iclass 23, count 0 2006.285.10:02:26.77#ibcon#about to write, iclass 23, count 0 2006.285.10:02:26.77#ibcon#wrote, iclass 23, count 0 2006.285.10:02:26.77#ibcon#about to read 3, iclass 23, count 0 2006.285.10:02:26.80#ibcon#read 3, iclass 23, count 0 2006.285.10:02:26.80#ibcon#about to read 4, iclass 23, count 0 2006.285.10:02:26.80#ibcon#read 4, iclass 23, count 0 2006.285.10:02:26.80#ibcon#about to read 5, iclass 23, count 0 2006.285.10:02:26.80#ibcon#read 5, iclass 23, count 0 2006.285.10:02:26.80#ibcon#about to read 6, iclass 23, count 0 2006.285.10:02:26.80#ibcon#read 6, iclass 23, count 0 2006.285.10:02:26.80#ibcon#end of sib2, iclass 23, count 0 2006.285.10:02:26.80#ibcon#*after write, iclass 23, count 0 2006.285.10:02:26.80#ibcon#*before return 0, iclass 23, count 0 2006.285.10:02:26.80#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:02:26.80#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:02:26.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:02:26.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:02:26.81$vck44/valo=4,624.99 2006.285.10:02:26.81#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.10:02:26.81#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.10:02:26.81#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:26.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:02:26.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:02:26.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:02:26.81#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:02:26.81#ibcon#first serial, iclass 25, count 0 2006.285.10:02:26.81#ibcon#enter sib2, iclass 25, count 0 2006.285.10:02:26.81#ibcon#flushed, iclass 25, count 0 2006.285.10:02:26.81#ibcon#about to write, iclass 25, count 0 2006.285.10:02:26.81#ibcon#wrote, iclass 25, count 0 2006.285.10:02:26.81#ibcon#about to read 3, iclass 25, count 0 2006.285.10:02:26.82#ibcon#read 3, iclass 25, count 0 2006.285.10:02:26.82#ibcon#about to read 4, iclass 25, count 0 2006.285.10:02:26.82#ibcon#read 4, iclass 25, count 0 2006.285.10:02:26.82#ibcon#about to read 5, iclass 25, count 0 2006.285.10:02:26.82#ibcon#read 5, iclass 25, count 0 2006.285.10:02:26.82#ibcon#about to read 6, iclass 25, count 0 2006.285.10:02:26.82#ibcon#read 6, iclass 25, count 0 2006.285.10:02:26.82#ibcon#end of sib2, iclass 25, count 0 2006.285.10:02:26.82#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:02:26.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:02:26.82#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:02:26.82#ibcon#*before write, iclass 25, count 0 2006.285.10:02:26.82#ibcon#enter sib2, iclass 25, count 0 2006.285.10:02:26.82#ibcon#flushed, iclass 25, count 0 2006.285.10:02:26.82#ibcon#about to write, iclass 25, count 0 2006.285.10:02:26.82#ibcon#wrote, iclass 25, count 0 2006.285.10:02:26.82#ibcon#about to read 3, iclass 25, count 0 2006.285.10:02:26.86#ibcon#read 3, iclass 25, count 0 2006.285.10:02:26.86#ibcon#about to read 4, iclass 25, count 0 2006.285.10:02:26.86#ibcon#read 4, iclass 25, count 0 2006.285.10:02:26.86#ibcon#about to read 5, iclass 25, count 0 2006.285.10:02:26.86#ibcon#read 5, iclass 25, count 0 2006.285.10:02:26.86#ibcon#about to read 6, iclass 25, count 0 2006.285.10:02:26.86#ibcon#read 6, iclass 25, count 0 2006.285.10:02:26.86#ibcon#end of sib2, iclass 25, count 0 2006.285.10:02:26.86#ibcon#*after write, iclass 25, count 0 2006.285.10:02:26.86#ibcon#*before return 0, iclass 25, count 0 2006.285.10:02:26.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:02:26.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:02:26.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:02:26.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:02:26.87$vck44/va=4,6 2006.285.10:02:26.87#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.10:02:26.87#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.10:02:26.87#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:26.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:02:26.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:02:26.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:02:26.91#ibcon#enter wrdev, iclass 27, count 2 2006.285.10:02:26.91#ibcon#first serial, iclass 27, count 2 2006.285.10:02:26.91#ibcon#enter sib2, iclass 27, count 2 2006.285.10:02:26.91#ibcon#flushed, iclass 27, count 2 2006.285.10:02:26.91#ibcon#about to write, iclass 27, count 2 2006.285.10:02:26.91#ibcon#wrote, iclass 27, count 2 2006.285.10:02:26.91#ibcon#about to read 3, iclass 27, count 2 2006.285.10:02:26.93#ibcon#read 3, iclass 27, count 2 2006.285.10:02:26.93#ibcon#about to read 4, iclass 27, count 2 2006.285.10:02:26.93#ibcon#read 4, iclass 27, count 2 2006.285.10:02:26.93#ibcon#about to read 5, iclass 27, count 2 2006.285.10:02:26.93#ibcon#read 5, iclass 27, count 2 2006.285.10:02:26.93#ibcon#about to read 6, iclass 27, count 2 2006.285.10:02:26.93#ibcon#read 6, iclass 27, count 2 2006.285.10:02:26.93#ibcon#end of sib2, iclass 27, count 2 2006.285.10:02:26.93#ibcon#*mode == 0, iclass 27, count 2 2006.285.10:02:26.93#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.10:02:26.93#ibcon#[25=AT04-06\r\n] 2006.285.10:02:26.93#ibcon#*before write, iclass 27, count 2 2006.285.10:02:26.93#ibcon#enter sib2, iclass 27, count 2 2006.285.10:02:26.93#ibcon#flushed, iclass 27, count 2 2006.285.10:02:26.93#ibcon#about to write, iclass 27, count 2 2006.285.10:02:26.93#ibcon#wrote, iclass 27, count 2 2006.285.10:02:26.93#ibcon#about to read 3, iclass 27, count 2 2006.285.10:02:26.96#ibcon#read 3, iclass 27, count 2 2006.285.10:02:26.96#ibcon#about to read 4, iclass 27, count 2 2006.285.10:02:26.96#ibcon#read 4, iclass 27, count 2 2006.285.10:02:26.96#ibcon#about to read 5, iclass 27, count 2 2006.285.10:02:26.96#ibcon#read 5, iclass 27, count 2 2006.285.10:02:26.96#ibcon#about to read 6, iclass 27, count 2 2006.285.10:02:26.96#ibcon#read 6, iclass 27, count 2 2006.285.10:02:26.96#ibcon#end of sib2, iclass 27, count 2 2006.285.10:02:26.96#ibcon#*after write, iclass 27, count 2 2006.285.10:02:26.96#ibcon#*before return 0, iclass 27, count 2 2006.285.10:02:26.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:02:26.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:02:26.96#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.10:02:26.96#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:26.96#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:02:27.08#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:02:27.08#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:02:27.08#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:02:27.08#ibcon#first serial, iclass 27, count 0 2006.285.10:02:27.08#ibcon#enter sib2, iclass 27, count 0 2006.285.10:02:27.08#ibcon#flushed, iclass 27, count 0 2006.285.10:02:27.08#ibcon#about to write, iclass 27, count 0 2006.285.10:02:27.08#ibcon#wrote, iclass 27, count 0 2006.285.10:02:27.08#ibcon#about to read 3, iclass 27, count 0 2006.285.10:02:27.10#ibcon#read 3, iclass 27, count 0 2006.285.10:02:27.10#ibcon#about to read 4, iclass 27, count 0 2006.285.10:02:27.10#ibcon#read 4, iclass 27, count 0 2006.285.10:02:27.10#ibcon#about to read 5, iclass 27, count 0 2006.285.10:02:27.10#ibcon#read 5, iclass 27, count 0 2006.285.10:02:27.10#ibcon#about to read 6, iclass 27, count 0 2006.285.10:02:27.10#ibcon#read 6, iclass 27, count 0 2006.285.10:02:27.10#ibcon#end of sib2, iclass 27, count 0 2006.285.10:02:27.10#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:02:27.10#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:02:27.10#ibcon#[25=USB\r\n] 2006.285.10:02:27.10#ibcon#*before write, iclass 27, count 0 2006.285.10:02:27.10#ibcon#enter sib2, iclass 27, count 0 2006.285.10:02:27.10#ibcon#flushed, iclass 27, count 0 2006.285.10:02:27.10#ibcon#about to write, iclass 27, count 0 2006.285.10:02:27.10#ibcon#wrote, iclass 27, count 0 2006.285.10:02:27.10#ibcon#about to read 3, iclass 27, count 0 2006.285.10:02:27.13#ibcon#read 3, iclass 27, count 0 2006.285.10:02:27.13#ibcon#about to read 4, iclass 27, count 0 2006.285.10:02:27.13#ibcon#read 4, iclass 27, count 0 2006.285.10:02:27.13#ibcon#about to read 5, iclass 27, count 0 2006.285.10:02:27.13#ibcon#read 5, iclass 27, count 0 2006.285.10:02:27.13#ibcon#about to read 6, iclass 27, count 0 2006.285.10:02:27.13#ibcon#read 6, iclass 27, count 0 2006.285.10:02:27.13#ibcon#end of sib2, iclass 27, count 0 2006.285.10:02:27.13#ibcon#*after write, iclass 27, count 0 2006.285.10:02:27.13#ibcon#*before return 0, iclass 27, count 0 2006.285.10:02:27.13#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:02:27.13#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:02:27.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:02:27.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:02:27.14$vck44/valo=5,734.99 2006.285.10:02:27.14#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.10:02:27.14#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.10:02:27.14#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:27.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:02:27.14#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:02:27.14#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:02:27.14#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:02:27.14#ibcon#first serial, iclass 29, count 0 2006.285.10:02:27.14#ibcon#enter sib2, iclass 29, count 0 2006.285.10:02:27.14#ibcon#flushed, iclass 29, count 0 2006.285.10:02:27.14#ibcon#about to write, iclass 29, count 0 2006.285.10:02:27.14#ibcon#wrote, iclass 29, count 0 2006.285.10:02:27.14#ibcon#about to read 3, iclass 29, count 0 2006.285.10:02:27.15#ibcon#read 3, iclass 29, count 0 2006.285.10:02:27.15#ibcon#about to read 4, iclass 29, count 0 2006.285.10:02:27.15#ibcon#read 4, iclass 29, count 0 2006.285.10:02:27.15#ibcon#about to read 5, iclass 29, count 0 2006.285.10:02:27.15#ibcon#read 5, iclass 29, count 0 2006.285.10:02:27.15#ibcon#about to read 6, iclass 29, count 0 2006.285.10:02:27.15#ibcon#read 6, iclass 29, count 0 2006.285.10:02:27.15#ibcon#end of sib2, iclass 29, count 0 2006.285.10:02:27.15#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:02:27.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:02:27.15#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:02:27.15#ibcon#*before write, iclass 29, count 0 2006.285.10:02:27.15#ibcon#enter sib2, iclass 29, count 0 2006.285.10:02:27.15#ibcon#flushed, iclass 29, count 0 2006.285.10:02:27.15#ibcon#about to write, iclass 29, count 0 2006.285.10:02:27.15#ibcon#wrote, iclass 29, count 0 2006.285.10:02:27.15#ibcon#about to read 3, iclass 29, count 0 2006.285.10:02:27.19#ibcon#read 3, iclass 29, count 0 2006.285.10:02:27.19#ibcon#about to read 4, iclass 29, count 0 2006.285.10:02:27.19#ibcon#read 4, iclass 29, count 0 2006.285.10:02:27.19#ibcon#about to read 5, iclass 29, count 0 2006.285.10:02:27.19#ibcon#read 5, iclass 29, count 0 2006.285.10:02:27.19#ibcon#about to read 6, iclass 29, count 0 2006.285.10:02:27.19#ibcon#read 6, iclass 29, count 0 2006.285.10:02:27.19#ibcon#end of sib2, iclass 29, count 0 2006.285.10:02:27.19#ibcon#*after write, iclass 29, count 0 2006.285.10:02:27.19#ibcon#*before return 0, iclass 29, count 0 2006.285.10:02:27.19#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:02:27.19#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:02:27.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:02:27.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:02:27.20$vck44/va=5,3 2006.285.10:02:27.20#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.10:02:27.20#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.10:02:27.20#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:27.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:02:27.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:02:27.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:02:27.24#ibcon#enter wrdev, iclass 31, count 2 2006.285.10:02:27.24#ibcon#first serial, iclass 31, count 2 2006.285.10:02:27.24#ibcon#enter sib2, iclass 31, count 2 2006.285.10:02:27.24#ibcon#flushed, iclass 31, count 2 2006.285.10:02:27.24#ibcon#about to write, iclass 31, count 2 2006.285.10:02:27.24#ibcon#wrote, iclass 31, count 2 2006.285.10:02:27.24#ibcon#about to read 3, iclass 31, count 2 2006.285.10:02:27.26#ibcon#read 3, iclass 31, count 2 2006.285.10:02:27.26#ibcon#about to read 4, iclass 31, count 2 2006.285.10:02:27.26#ibcon#read 4, iclass 31, count 2 2006.285.10:02:27.26#ibcon#about to read 5, iclass 31, count 2 2006.285.10:02:27.26#ibcon#read 5, iclass 31, count 2 2006.285.10:02:27.26#ibcon#about to read 6, iclass 31, count 2 2006.285.10:02:27.26#ibcon#read 6, iclass 31, count 2 2006.285.10:02:27.26#ibcon#end of sib2, iclass 31, count 2 2006.285.10:02:27.26#ibcon#*mode == 0, iclass 31, count 2 2006.285.10:02:27.26#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.10:02:27.26#ibcon#[25=AT05-03\r\n] 2006.285.10:02:27.26#ibcon#*before write, iclass 31, count 2 2006.285.10:02:27.26#ibcon#enter sib2, iclass 31, count 2 2006.285.10:02:27.26#ibcon#flushed, iclass 31, count 2 2006.285.10:02:27.26#ibcon#about to write, iclass 31, count 2 2006.285.10:02:27.27#ibcon#wrote, iclass 31, count 2 2006.285.10:02:27.27#ibcon#about to read 3, iclass 31, count 2 2006.285.10:02:27.29#ibcon#read 3, iclass 31, count 2 2006.285.10:02:27.29#ibcon#about to read 4, iclass 31, count 2 2006.285.10:02:27.29#ibcon#read 4, iclass 31, count 2 2006.285.10:02:27.29#ibcon#about to read 5, iclass 31, count 2 2006.285.10:02:27.29#ibcon#read 5, iclass 31, count 2 2006.285.10:02:27.29#ibcon#about to read 6, iclass 31, count 2 2006.285.10:02:27.29#ibcon#read 6, iclass 31, count 2 2006.285.10:02:27.29#ibcon#end of sib2, iclass 31, count 2 2006.285.10:02:27.29#ibcon#*after write, iclass 31, count 2 2006.285.10:02:27.29#ibcon#*before return 0, iclass 31, count 2 2006.285.10:02:27.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:02:27.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:02:27.29#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.10:02:27.29#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:27.29#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:02:27.41#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:02:27.41#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:02:27.41#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:02:27.41#ibcon#first serial, iclass 31, count 0 2006.285.10:02:27.41#ibcon#enter sib2, iclass 31, count 0 2006.285.10:02:27.41#ibcon#flushed, iclass 31, count 0 2006.285.10:02:27.41#ibcon#about to write, iclass 31, count 0 2006.285.10:02:27.41#ibcon#wrote, iclass 31, count 0 2006.285.10:02:27.41#ibcon#about to read 3, iclass 31, count 0 2006.285.10:02:27.43#ibcon#read 3, iclass 31, count 0 2006.285.10:02:27.43#ibcon#about to read 4, iclass 31, count 0 2006.285.10:02:27.43#ibcon#read 4, iclass 31, count 0 2006.285.10:02:27.43#ibcon#about to read 5, iclass 31, count 0 2006.285.10:02:27.43#ibcon#read 5, iclass 31, count 0 2006.285.10:02:27.43#ibcon#about to read 6, iclass 31, count 0 2006.285.10:02:27.43#ibcon#read 6, iclass 31, count 0 2006.285.10:02:27.43#ibcon#end of sib2, iclass 31, count 0 2006.285.10:02:27.43#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:02:27.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:02:27.43#ibcon#[25=USB\r\n] 2006.285.10:02:27.43#ibcon#*before write, iclass 31, count 0 2006.285.10:02:27.43#ibcon#enter sib2, iclass 31, count 0 2006.285.10:02:27.43#ibcon#flushed, iclass 31, count 0 2006.285.10:02:27.43#ibcon#about to write, iclass 31, count 0 2006.285.10:02:27.43#ibcon#wrote, iclass 31, count 0 2006.285.10:02:27.43#ibcon#about to read 3, iclass 31, count 0 2006.285.10:02:27.46#ibcon#read 3, iclass 31, count 0 2006.285.10:02:27.46#ibcon#about to read 4, iclass 31, count 0 2006.285.10:02:27.46#ibcon#read 4, iclass 31, count 0 2006.285.10:02:27.46#ibcon#about to read 5, iclass 31, count 0 2006.285.10:02:27.46#ibcon#read 5, iclass 31, count 0 2006.285.10:02:27.46#ibcon#about to read 6, iclass 31, count 0 2006.285.10:02:27.46#ibcon#read 6, iclass 31, count 0 2006.285.10:02:27.46#ibcon#end of sib2, iclass 31, count 0 2006.285.10:02:27.46#ibcon#*after write, iclass 31, count 0 2006.285.10:02:27.46#ibcon#*before return 0, iclass 31, count 0 2006.285.10:02:27.46#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:02:27.46#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:02:27.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:02:27.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:02:27.47$vck44/valo=6,814.99 2006.285.10:02:27.47#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.10:02:27.47#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.10:02:27.47#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:27.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:02:27.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:02:27.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:02:27.47#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:02:27.47#ibcon#first serial, iclass 33, count 0 2006.285.10:02:27.47#ibcon#enter sib2, iclass 33, count 0 2006.285.10:02:27.47#ibcon#flushed, iclass 33, count 0 2006.285.10:02:27.47#ibcon#about to write, iclass 33, count 0 2006.285.10:02:27.47#ibcon#wrote, iclass 33, count 0 2006.285.10:02:27.47#ibcon#about to read 3, iclass 33, count 0 2006.285.10:02:27.48#ibcon#read 3, iclass 33, count 0 2006.285.10:02:27.48#ibcon#about to read 4, iclass 33, count 0 2006.285.10:02:27.48#ibcon#read 4, iclass 33, count 0 2006.285.10:02:27.48#ibcon#about to read 5, iclass 33, count 0 2006.285.10:02:27.48#ibcon#read 5, iclass 33, count 0 2006.285.10:02:27.48#ibcon#about to read 6, iclass 33, count 0 2006.285.10:02:27.48#ibcon#read 6, iclass 33, count 0 2006.285.10:02:27.48#ibcon#end of sib2, iclass 33, count 0 2006.285.10:02:27.48#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:02:27.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:02:27.48#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:02:27.48#ibcon#*before write, iclass 33, count 0 2006.285.10:02:27.48#ibcon#enter sib2, iclass 33, count 0 2006.285.10:02:27.48#ibcon#flushed, iclass 33, count 0 2006.285.10:02:27.48#ibcon#about to write, iclass 33, count 0 2006.285.10:02:27.48#ibcon#wrote, iclass 33, count 0 2006.285.10:02:27.48#ibcon#about to read 3, iclass 33, count 0 2006.285.10:02:27.52#ibcon#read 3, iclass 33, count 0 2006.285.10:02:27.52#ibcon#about to read 4, iclass 33, count 0 2006.285.10:02:27.52#ibcon#read 4, iclass 33, count 0 2006.285.10:02:27.52#ibcon#about to read 5, iclass 33, count 0 2006.285.10:02:27.52#ibcon#read 5, iclass 33, count 0 2006.285.10:02:27.52#ibcon#about to read 6, iclass 33, count 0 2006.285.10:02:27.52#ibcon#read 6, iclass 33, count 0 2006.285.10:02:27.52#ibcon#end of sib2, iclass 33, count 0 2006.285.10:02:27.52#ibcon#*after write, iclass 33, count 0 2006.285.10:02:27.52#ibcon#*before return 0, iclass 33, count 0 2006.285.10:02:27.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:02:27.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:02:27.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:02:27.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:02:27.53$vck44/va=6,4 2006.285.10:02:27.53#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.10:02:27.53#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.10:02:27.53#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:27.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:02:27.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:02:27.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:02:27.57#ibcon#enter wrdev, iclass 35, count 2 2006.285.10:02:27.57#ibcon#first serial, iclass 35, count 2 2006.285.10:02:27.57#ibcon#enter sib2, iclass 35, count 2 2006.285.10:02:27.57#ibcon#flushed, iclass 35, count 2 2006.285.10:02:27.57#ibcon#about to write, iclass 35, count 2 2006.285.10:02:27.57#ibcon#wrote, iclass 35, count 2 2006.285.10:02:27.57#ibcon#about to read 3, iclass 35, count 2 2006.285.10:02:27.59#ibcon#read 3, iclass 35, count 2 2006.285.10:02:27.59#ibcon#about to read 4, iclass 35, count 2 2006.285.10:02:27.59#ibcon#read 4, iclass 35, count 2 2006.285.10:02:27.59#ibcon#about to read 5, iclass 35, count 2 2006.285.10:02:27.59#ibcon#read 5, iclass 35, count 2 2006.285.10:02:27.59#ibcon#about to read 6, iclass 35, count 2 2006.285.10:02:27.59#ibcon#read 6, iclass 35, count 2 2006.285.10:02:27.59#ibcon#end of sib2, iclass 35, count 2 2006.285.10:02:27.59#ibcon#*mode == 0, iclass 35, count 2 2006.285.10:02:27.59#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.10:02:27.59#ibcon#[25=AT06-04\r\n] 2006.285.10:02:27.59#ibcon#*before write, iclass 35, count 2 2006.285.10:02:27.59#ibcon#enter sib2, iclass 35, count 2 2006.285.10:02:27.59#ibcon#flushed, iclass 35, count 2 2006.285.10:02:27.59#ibcon#about to write, iclass 35, count 2 2006.285.10:02:27.59#ibcon#wrote, iclass 35, count 2 2006.285.10:02:27.59#ibcon#about to read 3, iclass 35, count 2 2006.285.10:02:27.62#ibcon#read 3, iclass 35, count 2 2006.285.10:02:27.62#ibcon#about to read 4, iclass 35, count 2 2006.285.10:02:27.62#ibcon#read 4, iclass 35, count 2 2006.285.10:02:27.62#ibcon#about to read 5, iclass 35, count 2 2006.285.10:02:27.62#ibcon#read 5, iclass 35, count 2 2006.285.10:02:27.62#ibcon#about to read 6, iclass 35, count 2 2006.285.10:02:27.62#ibcon#read 6, iclass 35, count 2 2006.285.10:02:27.62#ibcon#end of sib2, iclass 35, count 2 2006.285.10:02:27.62#ibcon#*after write, iclass 35, count 2 2006.285.10:02:27.62#ibcon#*before return 0, iclass 35, count 2 2006.285.10:02:27.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:02:27.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:02:27.62#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.10:02:27.62#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:27.62#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:02:27.74#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:02:27.74#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:02:27.74#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:02:27.74#ibcon#first serial, iclass 35, count 0 2006.285.10:02:27.74#ibcon#enter sib2, iclass 35, count 0 2006.285.10:02:27.74#ibcon#flushed, iclass 35, count 0 2006.285.10:02:27.74#ibcon#about to write, iclass 35, count 0 2006.285.10:02:27.74#ibcon#wrote, iclass 35, count 0 2006.285.10:02:27.74#ibcon#about to read 3, iclass 35, count 0 2006.285.10:02:27.76#ibcon#read 3, iclass 35, count 0 2006.285.10:02:27.76#ibcon#about to read 4, iclass 35, count 0 2006.285.10:02:27.76#ibcon#read 4, iclass 35, count 0 2006.285.10:02:27.76#ibcon#about to read 5, iclass 35, count 0 2006.285.10:02:27.76#ibcon#read 5, iclass 35, count 0 2006.285.10:02:27.76#ibcon#about to read 6, iclass 35, count 0 2006.285.10:02:27.76#ibcon#read 6, iclass 35, count 0 2006.285.10:02:27.76#ibcon#end of sib2, iclass 35, count 0 2006.285.10:02:27.76#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:02:27.76#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:02:27.76#ibcon#[25=USB\r\n] 2006.285.10:02:27.76#ibcon#*before write, iclass 35, count 0 2006.285.10:02:27.76#ibcon#enter sib2, iclass 35, count 0 2006.285.10:02:27.76#ibcon#flushed, iclass 35, count 0 2006.285.10:02:27.76#ibcon#about to write, iclass 35, count 0 2006.285.10:02:27.76#ibcon#wrote, iclass 35, count 0 2006.285.10:02:27.76#ibcon#about to read 3, iclass 35, count 0 2006.285.10:02:27.79#ibcon#read 3, iclass 35, count 0 2006.285.10:02:27.79#ibcon#about to read 4, iclass 35, count 0 2006.285.10:02:27.79#ibcon#read 4, iclass 35, count 0 2006.285.10:02:27.79#ibcon#about to read 5, iclass 35, count 0 2006.285.10:02:27.79#ibcon#read 5, iclass 35, count 0 2006.285.10:02:27.79#ibcon#about to read 6, iclass 35, count 0 2006.285.10:02:27.79#ibcon#read 6, iclass 35, count 0 2006.285.10:02:27.79#ibcon#end of sib2, iclass 35, count 0 2006.285.10:02:27.79#ibcon#*after write, iclass 35, count 0 2006.285.10:02:27.79#ibcon#*before return 0, iclass 35, count 0 2006.285.10:02:27.79#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:02:27.79#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:02:27.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:02:27.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:02:27.80$vck44/valo=7,864.99 2006.285.10:02:27.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.10:02:27.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.10:02:27.80#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:27.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:02:27.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:02:27.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:02:27.80#ibcon#enter wrdev, iclass 37, count 0 2006.285.10:02:27.80#ibcon#first serial, iclass 37, count 0 2006.285.10:02:27.80#ibcon#enter sib2, iclass 37, count 0 2006.285.10:02:27.80#ibcon#flushed, iclass 37, count 0 2006.285.10:02:27.80#ibcon#about to write, iclass 37, count 0 2006.285.10:02:27.80#ibcon#wrote, iclass 37, count 0 2006.285.10:02:27.80#ibcon#about to read 3, iclass 37, count 0 2006.285.10:02:27.81#ibcon#read 3, iclass 37, count 0 2006.285.10:02:27.81#ibcon#about to read 4, iclass 37, count 0 2006.285.10:02:27.81#ibcon#read 4, iclass 37, count 0 2006.285.10:02:27.81#ibcon#about to read 5, iclass 37, count 0 2006.285.10:02:27.81#ibcon#read 5, iclass 37, count 0 2006.285.10:02:27.81#ibcon#about to read 6, iclass 37, count 0 2006.285.10:02:27.81#ibcon#read 6, iclass 37, count 0 2006.285.10:02:27.81#ibcon#end of sib2, iclass 37, count 0 2006.285.10:02:27.81#ibcon#*mode == 0, iclass 37, count 0 2006.285.10:02:27.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.10:02:27.81#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:02:27.81#ibcon#*before write, iclass 37, count 0 2006.285.10:02:27.81#ibcon#enter sib2, iclass 37, count 0 2006.285.10:02:27.81#ibcon#flushed, iclass 37, count 0 2006.285.10:02:27.81#ibcon#about to write, iclass 37, count 0 2006.285.10:02:27.81#ibcon#wrote, iclass 37, count 0 2006.285.10:02:27.81#ibcon#about to read 3, iclass 37, count 0 2006.285.10:02:27.85#ibcon#read 3, iclass 37, count 0 2006.285.10:02:27.85#ibcon#about to read 4, iclass 37, count 0 2006.285.10:02:27.85#ibcon#read 4, iclass 37, count 0 2006.285.10:02:27.85#ibcon#about to read 5, iclass 37, count 0 2006.285.10:02:27.85#ibcon#read 5, iclass 37, count 0 2006.285.10:02:27.85#ibcon#about to read 6, iclass 37, count 0 2006.285.10:02:27.85#ibcon#read 6, iclass 37, count 0 2006.285.10:02:27.85#ibcon#end of sib2, iclass 37, count 0 2006.285.10:02:27.85#ibcon#*after write, iclass 37, count 0 2006.285.10:02:27.85#ibcon#*before return 0, iclass 37, count 0 2006.285.10:02:27.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:02:27.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:02:27.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.10:02:27.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.10:02:27.86$vck44/va=7,4 2006.285.10:02:27.86#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.10:02:27.86#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.10:02:27.86#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:27.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:02:27.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:02:27.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:02:27.90#ibcon#enter wrdev, iclass 39, count 2 2006.285.10:02:27.90#ibcon#first serial, iclass 39, count 2 2006.285.10:02:27.90#ibcon#enter sib2, iclass 39, count 2 2006.285.10:02:27.90#ibcon#flushed, iclass 39, count 2 2006.285.10:02:27.90#ibcon#about to write, iclass 39, count 2 2006.285.10:02:27.90#ibcon#wrote, iclass 39, count 2 2006.285.10:02:27.90#ibcon#about to read 3, iclass 39, count 2 2006.285.10:02:27.92#ibcon#read 3, iclass 39, count 2 2006.285.10:02:27.92#ibcon#about to read 4, iclass 39, count 2 2006.285.10:02:27.92#ibcon#read 4, iclass 39, count 2 2006.285.10:02:27.92#ibcon#about to read 5, iclass 39, count 2 2006.285.10:02:27.92#ibcon#read 5, iclass 39, count 2 2006.285.10:02:27.92#ibcon#about to read 6, iclass 39, count 2 2006.285.10:02:27.92#ibcon#read 6, iclass 39, count 2 2006.285.10:02:27.92#ibcon#end of sib2, iclass 39, count 2 2006.285.10:02:27.92#ibcon#*mode == 0, iclass 39, count 2 2006.285.10:02:27.92#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.10:02:27.92#ibcon#[25=AT07-04\r\n] 2006.285.10:02:27.92#ibcon#*before write, iclass 39, count 2 2006.285.10:02:27.92#ibcon#enter sib2, iclass 39, count 2 2006.285.10:02:27.92#ibcon#flushed, iclass 39, count 2 2006.285.10:02:27.92#ibcon#about to write, iclass 39, count 2 2006.285.10:02:27.92#ibcon#wrote, iclass 39, count 2 2006.285.10:02:27.92#ibcon#about to read 3, iclass 39, count 2 2006.285.10:02:27.95#ibcon#read 3, iclass 39, count 2 2006.285.10:02:27.95#ibcon#about to read 4, iclass 39, count 2 2006.285.10:02:27.95#ibcon#read 4, iclass 39, count 2 2006.285.10:02:27.95#ibcon#about to read 5, iclass 39, count 2 2006.285.10:02:27.95#ibcon#read 5, iclass 39, count 2 2006.285.10:02:27.95#ibcon#about to read 6, iclass 39, count 2 2006.285.10:02:27.95#ibcon#read 6, iclass 39, count 2 2006.285.10:02:27.95#ibcon#end of sib2, iclass 39, count 2 2006.285.10:02:27.95#ibcon#*after write, iclass 39, count 2 2006.285.10:02:27.95#ibcon#*before return 0, iclass 39, count 2 2006.285.10:02:27.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:02:27.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:02:27.95#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.10:02:27.95#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:27.95#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:02:28.07#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:02:28.07#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:02:28.07#ibcon#enter wrdev, iclass 39, count 0 2006.285.10:02:28.07#ibcon#first serial, iclass 39, count 0 2006.285.10:02:28.07#ibcon#enter sib2, iclass 39, count 0 2006.285.10:02:28.07#ibcon#flushed, iclass 39, count 0 2006.285.10:02:28.07#ibcon#about to write, iclass 39, count 0 2006.285.10:02:28.07#ibcon#wrote, iclass 39, count 0 2006.285.10:02:28.07#ibcon#about to read 3, iclass 39, count 0 2006.285.10:02:28.09#ibcon#read 3, iclass 39, count 0 2006.285.10:02:28.09#ibcon#about to read 4, iclass 39, count 0 2006.285.10:02:28.09#ibcon#read 4, iclass 39, count 0 2006.285.10:02:28.09#ibcon#about to read 5, iclass 39, count 0 2006.285.10:02:28.09#ibcon#read 5, iclass 39, count 0 2006.285.10:02:28.09#ibcon#about to read 6, iclass 39, count 0 2006.285.10:02:28.09#ibcon#read 6, iclass 39, count 0 2006.285.10:02:28.09#ibcon#end of sib2, iclass 39, count 0 2006.285.10:02:28.09#ibcon#*mode == 0, iclass 39, count 0 2006.285.10:02:28.09#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.10:02:28.09#ibcon#[25=USB\r\n] 2006.285.10:02:28.09#ibcon#*before write, iclass 39, count 0 2006.285.10:02:28.09#ibcon#enter sib2, iclass 39, count 0 2006.285.10:02:28.09#ibcon#flushed, iclass 39, count 0 2006.285.10:02:28.09#ibcon#about to write, iclass 39, count 0 2006.285.10:02:28.09#ibcon#wrote, iclass 39, count 0 2006.285.10:02:28.09#ibcon#about to read 3, iclass 39, count 0 2006.285.10:02:28.12#ibcon#read 3, iclass 39, count 0 2006.285.10:02:28.12#ibcon#about to read 4, iclass 39, count 0 2006.285.10:02:28.12#ibcon#read 4, iclass 39, count 0 2006.285.10:02:28.12#ibcon#about to read 5, iclass 39, count 0 2006.285.10:02:28.12#ibcon#read 5, iclass 39, count 0 2006.285.10:02:28.12#ibcon#about to read 6, iclass 39, count 0 2006.285.10:02:28.12#ibcon#read 6, iclass 39, count 0 2006.285.10:02:28.12#ibcon#end of sib2, iclass 39, count 0 2006.285.10:02:28.12#ibcon#*after write, iclass 39, count 0 2006.285.10:02:28.12#ibcon#*before return 0, iclass 39, count 0 2006.285.10:02:28.12#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:02:28.12#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:02:28.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.10:02:28.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.10:02:28.13$vck44/valo=8,884.99 2006.285.10:02:28.13#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.10:02:28.13#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.10:02:28.13#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:28.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:02:28.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:02:28.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:02:28.13#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:02:28.13#ibcon#first serial, iclass 3, count 0 2006.285.10:02:28.13#ibcon#enter sib2, iclass 3, count 0 2006.285.10:02:28.13#ibcon#flushed, iclass 3, count 0 2006.285.10:02:28.13#ibcon#about to write, iclass 3, count 0 2006.285.10:02:28.13#ibcon#wrote, iclass 3, count 0 2006.285.10:02:28.13#ibcon#about to read 3, iclass 3, count 0 2006.285.10:02:28.15#ibcon#read 3, iclass 3, count 0 2006.285.10:02:28.15#ibcon#about to read 4, iclass 3, count 0 2006.285.10:02:28.15#ibcon#read 4, iclass 3, count 0 2006.285.10:02:28.15#ibcon#about to read 5, iclass 3, count 0 2006.285.10:02:28.15#ibcon#read 5, iclass 3, count 0 2006.285.10:02:28.15#ibcon#about to read 6, iclass 3, count 0 2006.285.10:02:28.15#ibcon#read 6, iclass 3, count 0 2006.285.10:02:28.15#ibcon#end of sib2, iclass 3, count 0 2006.285.10:02:28.15#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:02:28.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:02:28.15#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:02:28.15#ibcon#*before write, iclass 3, count 0 2006.285.10:02:28.15#ibcon#enter sib2, iclass 3, count 0 2006.285.10:02:28.15#ibcon#flushed, iclass 3, count 0 2006.285.10:02:28.15#ibcon#about to write, iclass 3, count 0 2006.285.10:02:28.15#ibcon#wrote, iclass 3, count 0 2006.285.10:02:28.15#ibcon#about to read 3, iclass 3, count 0 2006.285.10:02:28.18#ibcon#read 3, iclass 3, count 0 2006.285.10:02:28.18#ibcon#about to read 4, iclass 3, count 0 2006.285.10:02:28.18#ibcon#read 4, iclass 3, count 0 2006.285.10:02:28.18#ibcon#about to read 5, iclass 3, count 0 2006.285.10:02:28.18#ibcon#read 5, iclass 3, count 0 2006.285.10:02:28.18#ibcon#about to read 6, iclass 3, count 0 2006.285.10:02:28.18#ibcon#read 6, iclass 3, count 0 2006.285.10:02:28.18#ibcon#end of sib2, iclass 3, count 0 2006.285.10:02:28.18#ibcon#*after write, iclass 3, count 0 2006.285.10:02:28.18#ibcon#*before return 0, iclass 3, count 0 2006.285.10:02:28.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:02:28.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:02:28.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:02:28.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:02:28.19$vck44/va=8,3 2006.285.10:02:28.19#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.10:02:28.19#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.10:02:28.19#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:28.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:02:28.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:02:28.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:02:28.23#ibcon#enter wrdev, iclass 5, count 2 2006.285.10:02:28.23#ibcon#first serial, iclass 5, count 2 2006.285.10:02:28.23#ibcon#enter sib2, iclass 5, count 2 2006.285.10:02:28.23#ibcon#flushed, iclass 5, count 2 2006.285.10:02:28.23#ibcon#about to write, iclass 5, count 2 2006.285.10:02:28.23#ibcon#wrote, iclass 5, count 2 2006.285.10:02:28.23#ibcon#about to read 3, iclass 5, count 2 2006.285.10:02:28.25#ibcon#read 3, iclass 5, count 2 2006.285.10:02:28.25#ibcon#about to read 4, iclass 5, count 2 2006.285.10:02:28.25#ibcon#read 4, iclass 5, count 2 2006.285.10:02:28.25#ibcon#about to read 5, iclass 5, count 2 2006.285.10:02:28.25#ibcon#read 5, iclass 5, count 2 2006.285.10:02:28.25#ibcon#about to read 6, iclass 5, count 2 2006.285.10:02:28.25#ibcon#read 6, iclass 5, count 2 2006.285.10:02:28.25#ibcon#end of sib2, iclass 5, count 2 2006.285.10:02:28.25#ibcon#*mode == 0, iclass 5, count 2 2006.285.10:02:28.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.10:02:28.25#ibcon#[25=AT08-03\r\n] 2006.285.10:02:28.25#ibcon#*before write, iclass 5, count 2 2006.285.10:02:28.25#ibcon#enter sib2, iclass 5, count 2 2006.285.10:02:28.25#ibcon#flushed, iclass 5, count 2 2006.285.10:02:28.25#ibcon#about to write, iclass 5, count 2 2006.285.10:02:28.25#ibcon#wrote, iclass 5, count 2 2006.285.10:02:28.25#ibcon#about to read 3, iclass 5, count 2 2006.285.10:02:28.28#ibcon#read 3, iclass 5, count 2 2006.285.10:02:28.28#ibcon#about to read 4, iclass 5, count 2 2006.285.10:02:28.28#ibcon#read 4, iclass 5, count 2 2006.285.10:02:28.28#ibcon#about to read 5, iclass 5, count 2 2006.285.10:02:28.28#ibcon#read 5, iclass 5, count 2 2006.285.10:02:28.28#ibcon#about to read 6, iclass 5, count 2 2006.285.10:02:28.28#ibcon#read 6, iclass 5, count 2 2006.285.10:02:28.28#ibcon#end of sib2, iclass 5, count 2 2006.285.10:02:28.28#ibcon#*after write, iclass 5, count 2 2006.285.10:02:28.28#ibcon#*before return 0, iclass 5, count 2 2006.285.10:02:28.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:02:28.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:02:28.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.10:02:28.28#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:28.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:02:28.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:02:28.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:02:28.40#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:02:28.40#ibcon#first serial, iclass 5, count 0 2006.285.10:02:28.40#ibcon#enter sib2, iclass 5, count 0 2006.285.10:02:28.40#ibcon#flushed, iclass 5, count 0 2006.285.10:02:28.40#ibcon#about to write, iclass 5, count 0 2006.285.10:02:28.40#ibcon#wrote, iclass 5, count 0 2006.285.10:02:28.40#ibcon#about to read 3, iclass 5, count 0 2006.285.10:02:28.42#ibcon#read 3, iclass 5, count 0 2006.285.10:02:28.42#ibcon#about to read 4, iclass 5, count 0 2006.285.10:02:28.42#ibcon#read 4, iclass 5, count 0 2006.285.10:02:28.42#ibcon#about to read 5, iclass 5, count 0 2006.285.10:02:28.42#ibcon#read 5, iclass 5, count 0 2006.285.10:02:28.42#ibcon#about to read 6, iclass 5, count 0 2006.285.10:02:28.42#ibcon#read 6, iclass 5, count 0 2006.285.10:02:28.42#ibcon#end of sib2, iclass 5, count 0 2006.285.10:02:28.42#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:02:28.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:02:28.42#ibcon#[25=USB\r\n] 2006.285.10:02:28.42#ibcon#*before write, iclass 5, count 0 2006.285.10:02:28.42#ibcon#enter sib2, iclass 5, count 0 2006.285.10:02:28.42#ibcon#flushed, iclass 5, count 0 2006.285.10:02:28.42#ibcon#about to write, iclass 5, count 0 2006.285.10:02:28.42#ibcon#wrote, iclass 5, count 0 2006.285.10:02:28.42#ibcon#about to read 3, iclass 5, count 0 2006.285.10:02:28.45#ibcon#read 3, iclass 5, count 0 2006.285.10:02:28.45#ibcon#about to read 4, iclass 5, count 0 2006.285.10:02:28.45#ibcon#read 4, iclass 5, count 0 2006.285.10:02:28.45#ibcon#about to read 5, iclass 5, count 0 2006.285.10:02:28.45#ibcon#read 5, iclass 5, count 0 2006.285.10:02:28.45#ibcon#about to read 6, iclass 5, count 0 2006.285.10:02:28.45#ibcon#read 6, iclass 5, count 0 2006.285.10:02:28.45#ibcon#end of sib2, iclass 5, count 0 2006.285.10:02:28.45#ibcon#*after write, iclass 5, count 0 2006.285.10:02:28.45#ibcon#*before return 0, iclass 5, count 0 2006.285.10:02:28.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:02:28.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:02:28.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:02:28.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:02:28.46$vck44/vblo=1,629.99 2006.285.10:02:28.46#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.10:02:28.46#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.10:02:28.46#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:28.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:02:28.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:02:28.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:02:28.46#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:02:28.46#ibcon#first serial, iclass 7, count 0 2006.285.10:02:28.46#ibcon#enter sib2, iclass 7, count 0 2006.285.10:02:28.46#ibcon#flushed, iclass 7, count 0 2006.285.10:02:28.46#ibcon#about to write, iclass 7, count 0 2006.285.10:02:28.46#ibcon#wrote, iclass 7, count 0 2006.285.10:02:28.46#ibcon#about to read 3, iclass 7, count 0 2006.285.10:02:28.47#ibcon#read 3, iclass 7, count 0 2006.285.10:02:28.47#ibcon#about to read 4, iclass 7, count 0 2006.285.10:02:28.47#ibcon#read 4, iclass 7, count 0 2006.285.10:02:28.47#ibcon#about to read 5, iclass 7, count 0 2006.285.10:02:28.47#ibcon#read 5, iclass 7, count 0 2006.285.10:02:28.47#ibcon#about to read 6, iclass 7, count 0 2006.285.10:02:28.47#ibcon#read 6, iclass 7, count 0 2006.285.10:02:28.47#ibcon#end of sib2, iclass 7, count 0 2006.285.10:02:28.47#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:02:28.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:02:28.47#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:02:28.47#ibcon#*before write, iclass 7, count 0 2006.285.10:02:28.47#ibcon#enter sib2, iclass 7, count 0 2006.285.10:02:28.47#ibcon#flushed, iclass 7, count 0 2006.285.10:02:28.47#ibcon#about to write, iclass 7, count 0 2006.285.10:02:28.47#ibcon#wrote, iclass 7, count 0 2006.285.10:02:28.47#ibcon#about to read 3, iclass 7, count 0 2006.285.10:02:28.51#ibcon#read 3, iclass 7, count 0 2006.285.10:02:28.51#ibcon#about to read 4, iclass 7, count 0 2006.285.10:02:28.51#ibcon#read 4, iclass 7, count 0 2006.285.10:02:28.51#ibcon#about to read 5, iclass 7, count 0 2006.285.10:02:28.51#ibcon#read 5, iclass 7, count 0 2006.285.10:02:28.51#ibcon#about to read 6, iclass 7, count 0 2006.285.10:02:28.51#ibcon#read 6, iclass 7, count 0 2006.285.10:02:28.51#ibcon#end of sib2, iclass 7, count 0 2006.285.10:02:28.51#ibcon#*after write, iclass 7, count 0 2006.285.10:02:28.51#ibcon#*before return 0, iclass 7, count 0 2006.285.10:02:28.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:02:28.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:02:28.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:02:28.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:02:28.52$vck44/vb=1,4 2006.285.10:02:28.52#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.10:02:28.52#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.10:02:28.52#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:28.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:02:28.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:02:28.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:02:28.52#ibcon#enter wrdev, iclass 11, count 2 2006.285.10:02:28.52#ibcon#first serial, iclass 11, count 2 2006.285.10:02:28.52#ibcon#enter sib2, iclass 11, count 2 2006.285.10:02:28.52#ibcon#flushed, iclass 11, count 2 2006.285.10:02:28.52#ibcon#about to write, iclass 11, count 2 2006.285.10:02:28.52#ibcon#wrote, iclass 11, count 2 2006.285.10:02:28.52#ibcon#about to read 3, iclass 11, count 2 2006.285.10:02:28.53#ibcon#read 3, iclass 11, count 2 2006.285.10:02:28.53#ibcon#about to read 4, iclass 11, count 2 2006.285.10:02:28.53#ibcon#read 4, iclass 11, count 2 2006.285.10:02:28.53#ibcon#about to read 5, iclass 11, count 2 2006.285.10:02:28.53#ibcon#read 5, iclass 11, count 2 2006.285.10:02:28.53#ibcon#about to read 6, iclass 11, count 2 2006.285.10:02:28.53#ibcon#read 6, iclass 11, count 2 2006.285.10:02:28.53#ibcon#end of sib2, iclass 11, count 2 2006.285.10:02:28.53#ibcon#*mode == 0, iclass 11, count 2 2006.285.10:02:28.53#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.10:02:28.53#ibcon#[27=AT01-04\r\n] 2006.285.10:02:28.53#ibcon#*before write, iclass 11, count 2 2006.285.10:02:28.53#ibcon#enter sib2, iclass 11, count 2 2006.285.10:02:28.53#ibcon#flushed, iclass 11, count 2 2006.285.10:02:28.53#ibcon#about to write, iclass 11, count 2 2006.285.10:02:28.53#ibcon#wrote, iclass 11, count 2 2006.285.10:02:28.53#ibcon#about to read 3, iclass 11, count 2 2006.285.10:02:28.56#ibcon#read 3, iclass 11, count 2 2006.285.10:02:28.56#ibcon#about to read 4, iclass 11, count 2 2006.285.10:02:28.56#ibcon#read 4, iclass 11, count 2 2006.285.10:02:28.56#ibcon#about to read 5, iclass 11, count 2 2006.285.10:02:28.56#ibcon#read 5, iclass 11, count 2 2006.285.10:02:28.56#ibcon#about to read 6, iclass 11, count 2 2006.285.10:02:28.56#ibcon#read 6, iclass 11, count 2 2006.285.10:02:28.56#ibcon#end of sib2, iclass 11, count 2 2006.285.10:02:28.56#ibcon#*after write, iclass 11, count 2 2006.285.10:02:28.56#ibcon#*before return 0, iclass 11, count 2 2006.285.10:02:28.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:02:28.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:02:28.56#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.10:02:28.56#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:28.56#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:02:28.68#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:02:28.68#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:02:28.68#ibcon#enter wrdev, iclass 11, count 0 2006.285.10:02:28.68#ibcon#first serial, iclass 11, count 0 2006.285.10:02:28.68#ibcon#enter sib2, iclass 11, count 0 2006.285.10:02:28.68#ibcon#flushed, iclass 11, count 0 2006.285.10:02:28.68#ibcon#about to write, iclass 11, count 0 2006.285.10:02:28.68#ibcon#wrote, iclass 11, count 0 2006.285.10:02:28.68#ibcon#about to read 3, iclass 11, count 0 2006.285.10:02:28.70#ibcon#read 3, iclass 11, count 0 2006.285.10:02:28.70#ibcon#about to read 4, iclass 11, count 0 2006.285.10:02:28.70#ibcon#read 4, iclass 11, count 0 2006.285.10:02:28.70#ibcon#about to read 5, iclass 11, count 0 2006.285.10:02:28.70#ibcon#read 5, iclass 11, count 0 2006.285.10:02:28.70#ibcon#about to read 6, iclass 11, count 0 2006.285.10:02:28.70#ibcon#read 6, iclass 11, count 0 2006.285.10:02:28.70#ibcon#end of sib2, iclass 11, count 0 2006.285.10:02:28.70#ibcon#*mode == 0, iclass 11, count 0 2006.285.10:02:28.70#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.10:02:28.70#ibcon#[27=USB\r\n] 2006.285.10:02:28.70#ibcon#*before write, iclass 11, count 0 2006.285.10:02:28.70#ibcon#enter sib2, iclass 11, count 0 2006.285.10:02:28.70#ibcon#flushed, iclass 11, count 0 2006.285.10:02:28.70#ibcon#about to write, iclass 11, count 0 2006.285.10:02:28.70#ibcon#wrote, iclass 11, count 0 2006.285.10:02:28.70#ibcon#about to read 3, iclass 11, count 0 2006.285.10:02:28.73#ibcon#read 3, iclass 11, count 0 2006.285.10:02:28.73#ibcon#about to read 4, iclass 11, count 0 2006.285.10:02:28.73#ibcon#read 4, iclass 11, count 0 2006.285.10:02:28.73#ibcon#about to read 5, iclass 11, count 0 2006.285.10:02:28.73#ibcon#read 5, iclass 11, count 0 2006.285.10:02:28.73#ibcon#about to read 6, iclass 11, count 0 2006.285.10:02:28.73#ibcon#read 6, iclass 11, count 0 2006.285.10:02:28.73#ibcon#end of sib2, iclass 11, count 0 2006.285.10:02:28.73#ibcon#*after write, iclass 11, count 0 2006.285.10:02:28.73#ibcon#*before return 0, iclass 11, count 0 2006.285.10:02:28.73#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:02:28.73#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:02:28.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.10:02:28.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.10:02:28.74$vck44/vblo=2,634.99 2006.285.10:02:28.74#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.10:02:28.74#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.10:02:28.74#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:28.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:02:28.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:02:28.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:02:28.74#ibcon#enter wrdev, iclass 13, count 0 2006.285.10:02:28.74#ibcon#first serial, iclass 13, count 0 2006.285.10:02:28.74#ibcon#enter sib2, iclass 13, count 0 2006.285.10:02:28.74#ibcon#flushed, iclass 13, count 0 2006.285.10:02:28.74#ibcon#about to write, iclass 13, count 0 2006.285.10:02:28.74#ibcon#wrote, iclass 13, count 0 2006.285.10:02:28.74#ibcon#about to read 3, iclass 13, count 0 2006.285.10:02:28.75#ibcon#read 3, iclass 13, count 0 2006.285.10:02:28.75#ibcon#about to read 4, iclass 13, count 0 2006.285.10:02:28.75#ibcon#read 4, iclass 13, count 0 2006.285.10:02:28.75#ibcon#about to read 5, iclass 13, count 0 2006.285.10:02:28.75#ibcon#read 5, iclass 13, count 0 2006.285.10:02:28.75#ibcon#about to read 6, iclass 13, count 0 2006.285.10:02:28.75#ibcon#read 6, iclass 13, count 0 2006.285.10:02:28.75#ibcon#end of sib2, iclass 13, count 0 2006.285.10:02:28.75#ibcon#*mode == 0, iclass 13, count 0 2006.285.10:02:28.75#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.10:02:28.75#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:02:28.75#ibcon#*before write, iclass 13, count 0 2006.285.10:02:28.75#ibcon#enter sib2, iclass 13, count 0 2006.285.10:02:28.75#ibcon#flushed, iclass 13, count 0 2006.285.10:02:28.75#ibcon#about to write, iclass 13, count 0 2006.285.10:02:28.75#ibcon#wrote, iclass 13, count 0 2006.285.10:02:28.75#ibcon#about to read 3, iclass 13, count 0 2006.285.10:02:28.79#ibcon#read 3, iclass 13, count 0 2006.285.10:02:28.79#ibcon#about to read 4, iclass 13, count 0 2006.285.10:02:28.79#ibcon#read 4, iclass 13, count 0 2006.285.10:02:28.79#ibcon#about to read 5, iclass 13, count 0 2006.285.10:02:28.79#ibcon#read 5, iclass 13, count 0 2006.285.10:02:28.79#ibcon#about to read 6, iclass 13, count 0 2006.285.10:02:28.79#ibcon#read 6, iclass 13, count 0 2006.285.10:02:28.79#ibcon#end of sib2, iclass 13, count 0 2006.285.10:02:28.79#ibcon#*after write, iclass 13, count 0 2006.285.10:02:28.79#ibcon#*before return 0, iclass 13, count 0 2006.285.10:02:28.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:02:28.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:02:28.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.10:02:28.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.10:02:28.80$vck44/vb=2,5 2006.285.10:02:28.80#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.10:02:28.80#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.10:02:28.80#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:28.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:02:28.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:02:28.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:02:28.84#ibcon#enter wrdev, iclass 15, count 2 2006.285.10:02:28.84#ibcon#first serial, iclass 15, count 2 2006.285.10:02:28.84#ibcon#enter sib2, iclass 15, count 2 2006.285.10:02:28.84#ibcon#flushed, iclass 15, count 2 2006.285.10:02:28.84#ibcon#about to write, iclass 15, count 2 2006.285.10:02:28.84#ibcon#wrote, iclass 15, count 2 2006.285.10:02:28.84#ibcon#about to read 3, iclass 15, count 2 2006.285.10:02:28.86#ibcon#read 3, iclass 15, count 2 2006.285.10:02:28.86#ibcon#about to read 4, iclass 15, count 2 2006.285.10:02:28.86#ibcon#read 4, iclass 15, count 2 2006.285.10:02:28.86#ibcon#about to read 5, iclass 15, count 2 2006.285.10:02:28.86#ibcon#read 5, iclass 15, count 2 2006.285.10:02:28.86#ibcon#about to read 6, iclass 15, count 2 2006.285.10:02:28.86#ibcon#read 6, iclass 15, count 2 2006.285.10:02:28.86#ibcon#end of sib2, iclass 15, count 2 2006.285.10:02:28.86#ibcon#*mode == 0, iclass 15, count 2 2006.285.10:02:28.86#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.10:02:28.86#ibcon#[27=AT02-05\r\n] 2006.285.10:02:28.86#ibcon#*before write, iclass 15, count 2 2006.285.10:02:28.86#ibcon#enter sib2, iclass 15, count 2 2006.285.10:02:28.86#ibcon#flushed, iclass 15, count 2 2006.285.10:02:28.86#ibcon#about to write, iclass 15, count 2 2006.285.10:02:28.86#ibcon#wrote, iclass 15, count 2 2006.285.10:02:28.86#ibcon#about to read 3, iclass 15, count 2 2006.285.10:02:28.89#ibcon#read 3, iclass 15, count 2 2006.285.10:02:28.89#ibcon#about to read 4, iclass 15, count 2 2006.285.10:02:28.89#ibcon#read 4, iclass 15, count 2 2006.285.10:02:28.89#ibcon#about to read 5, iclass 15, count 2 2006.285.10:02:28.89#ibcon#read 5, iclass 15, count 2 2006.285.10:02:28.89#ibcon#about to read 6, iclass 15, count 2 2006.285.10:02:28.89#ibcon#read 6, iclass 15, count 2 2006.285.10:02:28.89#ibcon#end of sib2, iclass 15, count 2 2006.285.10:02:28.89#ibcon#*after write, iclass 15, count 2 2006.285.10:02:28.89#ibcon#*before return 0, iclass 15, count 2 2006.285.10:02:28.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:02:28.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:02:28.89#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.10:02:28.89#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:28.89#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:02:29.02#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:02:29.02#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:02:29.02#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:02:29.02#ibcon#first serial, iclass 15, count 0 2006.285.10:02:29.02#ibcon#enter sib2, iclass 15, count 0 2006.285.10:02:29.02#ibcon#flushed, iclass 15, count 0 2006.285.10:02:29.02#ibcon#about to write, iclass 15, count 0 2006.285.10:02:29.02#ibcon#wrote, iclass 15, count 0 2006.285.10:02:29.02#ibcon#about to read 3, iclass 15, count 0 2006.285.10:02:29.03#ibcon#read 3, iclass 15, count 0 2006.285.10:02:29.03#ibcon#about to read 4, iclass 15, count 0 2006.285.10:02:29.03#ibcon#read 4, iclass 15, count 0 2006.285.10:02:29.03#ibcon#about to read 5, iclass 15, count 0 2006.285.10:02:29.03#ibcon#read 5, iclass 15, count 0 2006.285.10:02:29.03#ibcon#about to read 6, iclass 15, count 0 2006.285.10:02:29.03#ibcon#read 6, iclass 15, count 0 2006.285.10:02:29.03#ibcon#end of sib2, iclass 15, count 0 2006.285.10:02:29.03#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:02:29.03#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:02:29.03#ibcon#[27=USB\r\n] 2006.285.10:02:29.03#ibcon#*before write, iclass 15, count 0 2006.285.10:02:29.03#ibcon#enter sib2, iclass 15, count 0 2006.285.10:02:29.03#ibcon#flushed, iclass 15, count 0 2006.285.10:02:29.03#ibcon#about to write, iclass 15, count 0 2006.285.10:02:29.03#ibcon#wrote, iclass 15, count 0 2006.285.10:02:29.03#ibcon#about to read 3, iclass 15, count 0 2006.285.10:02:29.06#ibcon#read 3, iclass 15, count 0 2006.285.10:02:29.06#ibcon#about to read 4, iclass 15, count 0 2006.285.10:02:29.06#ibcon#read 4, iclass 15, count 0 2006.285.10:02:29.06#ibcon#about to read 5, iclass 15, count 0 2006.285.10:02:29.06#ibcon#read 5, iclass 15, count 0 2006.285.10:02:29.06#ibcon#about to read 6, iclass 15, count 0 2006.285.10:02:29.06#ibcon#read 6, iclass 15, count 0 2006.285.10:02:29.06#ibcon#end of sib2, iclass 15, count 0 2006.285.10:02:29.06#ibcon#*after write, iclass 15, count 0 2006.285.10:02:29.06#ibcon#*before return 0, iclass 15, count 0 2006.285.10:02:29.06#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:02:29.06#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:02:29.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:02:29.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:02:29.07$vck44/vblo=3,649.99 2006.285.10:02:29.07#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.10:02:29.07#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.10:02:29.07#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:29.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:02:29.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:02:29.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:02:29.07#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:02:29.07#ibcon#first serial, iclass 17, count 0 2006.285.10:02:29.07#ibcon#enter sib2, iclass 17, count 0 2006.285.10:02:29.07#ibcon#flushed, iclass 17, count 0 2006.285.10:02:29.07#ibcon#about to write, iclass 17, count 0 2006.285.10:02:29.07#ibcon#wrote, iclass 17, count 0 2006.285.10:02:29.07#ibcon#about to read 3, iclass 17, count 0 2006.285.10:02:29.08#ibcon#read 3, iclass 17, count 0 2006.285.10:02:29.08#ibcon#about to read 4, iclass 17, count 0 2006.285.10:02:29.08#ibcon#read 4, iclass 17, count 0 2006.285.10:02:29.08#ibcon#about to read 5, iclass 17, count 0 2006.285.10:02:29.08#ibcon#read 5, iclass 17, count 0 2006.285.10:02:29.08#ibcon#about to read 6, iclass 17, count 0 2006.285.10:02:29.08#ibcon#read 6, iclass 17, count 0 2006.285.10:02:29.08#ibcon#end of sib2, iclass 17, count 0 2006.285.10:02:29.08#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:02:29.08#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:02:29.08#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:02:29.08#ibcon#*before write, iclass 17, count 0 2006.285.10:02:29.08#ibcon#enter sib2, iclass 17, count 0 2006.285.10:02:29.08#ibcon#flushed, iclass 17, count 0 2006.285.10:02:29.08#ibcon#about to write, iclass 17, count 0 2006.285.10:02:29.08#ibcon#wrote, iclass 17, count 0 2006.285.10:02:29.08#ibcon#about to read 3, iclass 17, count 0 2006.285.10:02:29.12#ibcon#read 3, iclass 17, count 0 2006.285.10:02:29.12#ibcon#about to read 4, iclass 17, count 0 2006.285.10:02:29.12#ibcon#read 4, iclass 17, count 0 2006.285.10:02:29.12#ibcon#about to read 5, iclass 17, count 0 2006.285.10:02:29.12#ibcon#read 5, iclass 17, count 0 2006.285.10:02:29.12#ibcon#about to read 6, iclass 17, count 0 2006.285.10:02:29.12#ibcon#read 6, iclass 17, count 0 2006.285.10:02:29.12#ibcon#end of sib2, iclass 17, count 0 2006.285.10:02:29.12#ibcon#*after write, iclass 17, count 0 2006.285.10:02:29.12#ibcon#*before return 0, iclass 17, count 0 2006.285.10:02:29.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:02:29.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:02:29.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:02:29.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:02:29.13$vck44/vb=3,4 2006.285.10:02:29.13#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.10:02:29.13#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.10:02:29.13#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:29.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:02:29.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:02:29.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:02:29.17#ibcon#enter wrdev, iclass 19, count 2 2006.285.10:02:29.17#ibcon#first serial, iclass 19, count 2 2006.285.10:02:29.17#ibcon#enter sib2, iclass 19, count 2 2006.285.10:02:29.17#ibcon#flushed, iclass 19, count 2 2006.285.10:02:29.17#ibcon#about to write, iclass 19, count 2 2006.285.10:02:29.17#ibcon#wrote, iclass 19, count 2 2006.285.10:02:29.17#ibcon#about to read 3, iclass 19, count 2 2006.285.10:02:29.19#ibcon#read 3, iclass 19, count 2 2006.285.10:02:29.19#ibcon#about to read 4, iclass 19, count 2 2006.285.10:02:29.19#ibcon#read 4, iclass 19, count 2 2006.285.10:02:29.19#ibcon#about to read 5, iclass 19, count 2 2006.285.10:02:29.19#ibcon#read 5, iclass 19, count 2 2006.285.10:02:29.19#ibcon#about to read 6, iclass 19, count 2 2006.285.10:02:29.19#ibcon#read 6, iclass 19, count 2 2006.285.10:02:29.19#ibcon#end of sib2, iclass 19, count 2 2006.285.10:02:29.19#ibcon#*mode == 0, iclass 19, count 2 2006.285.10:02:29.19#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.10:02:29.19#ibcon#[27=AT03-04\r\n] 2006.285.10:02:29.19#ibcon#*before write, iclass 19, count 2 2006.285.10:02:29.19#ibcon#enter sib2, iclass 19, count 2 2006.285.10:02:29.19#ibcon#flushed, iclass 19, count 2 2006.285.10:02:29.19#ibcon#about to write, iclass 19, count 2 2006.285.10:02:29.19#ibcon#wrote, iclass 19, count 2 2006.285.10:02:29.19#ibcon#about to read 3, iclass 19, count 2 2006.285.10:02:29.22#ibcon#read 3, iclass 19, count 2 2006.285.10:02:29.22#ibcon#about to read 4, iclass 19, count 2 2006.285.10:02:29.22#ibcon#read 4, iclass 19, count 2 2006.285.10:02:29.22#ibcon#about to read 5, iclass 19, count 2 2006.285.10:02:29.22#ibcon#read 5, iclass 19, count 2 2006.285.10:02:29.22#ibcon#about to read 6, iclass 19, count 2 2006.285.10:02:29.22#ibcon#read 6, iclass 19, count 2 2006.285.10:02:29.22#ibcon#end of sib2, iclass 19, count 2 2006.285.10:02:29.22#ibcon#*after write, iclass 19, count 2 2006.285.10:02:29.22#ibcon#*before return 0, iclass 19, count 2 2006.285.10:02:29.22#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:02:29.22#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:02:29.22#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.10:02:29.22#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:29.22#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:02:29.34#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:02:29.34#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:02:29.34#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:02:29.34#ibcon#first serial, iclass 19, count 0 2006.285.10:02:29.34#ibcon#enter sib2, iclass 19, count 0 2006.285.10:02:29.34#ibcon#flushed, iclass 19, count 0 2006.285.10:02:29.34#ibcon#about to write, iclass 19, count 0 2006.285.10:02:29.34#ibcon#wrote, iclass 19, count 0 2006.285.10:02:29.34#ibcon#about to read 3, iclass 19, count 0 2006.285.10:02:29.36#ibcon#read 3, iclass 19, count 0 2006.285.10:02:29.36#ibcon#about to read 4, iclass 19, count 0 2006.285.10:02:29.36#ibcon#read 4, iclass 19, count 0 2006.285.10:02:29.36#ibcon#about to read 5, iclass 19, count 0 2006.285.10:02:29.36#ibcon#read 5, iclass 19, count 0 2006.285.10:02:29.36#ibcon#about to read 6, iclass 19, count 0 2006.285.10:02:29.36#ibcon#read 6, iclass 19, count 0 2006.285.10:02:29.36#ibcon#end of sib2, iclass 19, count 0 2006.285.10:02:29.36#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:02:29.36#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:02:29.36#ibcon#[27=USB\r\n] 2006.285.10:02:29.36#ibcon#*before write, iclass 19, count 0 2006.285.10:02:29.36#ibcon#enter sib2, iclass 19, count 0 2006.285.10:02:29.36#ibcon#flushed, iclass 19, count 0 2006.285.10:02:29.36#ibcon#about to write, iclass 19, count 0 2006.285.10:02:29.36#ibcon#wrote, iclass 19, count 0 2006.285.10:02:29.36#ibcon#about to read 3, iclass 19, count 0 2006.285.10:02:29.39#ibcon#read 3, iclass 19, count 0 2006.285.10:02:29.39#ibcon#about to read 4, iclass 19, count 0 2006.285.10:02:29.39#ibcon#read 4, iclass 19, count 0 2006.285.10:02:29.39#ibcon#about to read 5, iclass 19, count 0 2006.285.10:02:29.39#ibcon#read 5, iclass 19, count 0 2006.285.10:02:29.39#ibcon#about to read 6, iclass 19, count 0 2006.285.10:02:29.39#ibcon#read 6, iclass 19, count 0 2006.285.10:02:29.39#ibcon#end of sib2, iclass 19, count 0 2006.285.10:02:29.39#ibcon#*after write, iclass 19, count 0 2006.285.10:02:29.39#ibcon#*before return 0, iclass 19, count 0 2006.285.10:02:29.39#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:02:29.39#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:02:29.39#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:02:29.39#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:02:29.40$vck44/vblo=4,679.99 2006.285.10:02:29.40#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.10:02:29.40#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.10:02:29.40#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:29.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:02:29.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:02:29.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:02:29.40#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:02:29.40#ibcon#first serial, iclass 21, count 0 2006.285.10:02:29.40#ibcon#enter sib2, iclass 21, count 0 2006.285.10:02:29.40#ibcon#flushed, iclass 21, count 0 2006.285.10:02:29.40#ibcon#about to write, iclass 21, count 0 2006.285.10:02:29.40#ibcon#wrote, iclass 21, count 0 2006.285.10:02:29.40#ibcon#about to read 3, iclass 21, count 0 2006.285.10:02:29.41#ibcon#read 3, iclass 21, count 0 2006.285.10:02:29.41#ibcon#about to read 4, iclass 21, count 0 2006.285.10:02:29.41#ibcon#read 4, iclass 21, count 0 2006.285.10:02:29.41#ibcon#about to read 5, iclass 21, count 0 2006.285.10:02:29.41#ibcon#read 5, iclass 21, count 0 2006.285.10:02:29.41#ibcon#about to read 6, iclass 21, count 0 2006.285.10:02:29.41#ibcon#read 6, iclass 21, count 0 2006.285.10:02:29.41#ibcon#end of sib2, iclass 21, count 0 2006.285.10:02:29.41#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:02:29.41#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:02:29.41#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:02:29.41#ibcon#*before write, iclass 21, count 0 2006.285.10:02:29.41#ibcon#enter sib2, iclass 21, count 0 2006.285.10:02:29.41#ibcon#flushed, iclass 21, count 0 2006.285.10:02:29.41#ibcon#about to write, iclass 21, count 0 2006.285.10:02:29.41#ibcon#wrote, iclass 21, count 0 2006.285.10:02:29.41#ibcon#about to read 3, iclass 21, count 0 2006.285.10:02:29.45#ibcon#read 3, iclass 21, count 0 2006.285.10:02:29.45#ibcon#about to read 4, iclass 21, count 0 2006.285.10:02:29.45#ibcon#read 4, iclass 21, count 0 2006.285.10:02:29.45#ibcon#about to read 5, iclass 21, count 0 2006.285.10:02:29.45#ibcon#read 5, iclass 21, count 0 2006.285.10:02:29.45#ibcon#about to read 6, iclass 21, count 0 2006.285.10:02:29.45#ibcon#read 6, iclass 21, count 0 2006.285.10:02:29.45#ibcon#end of sib2, iclass 21, count 0 2006.285.10:02:29.45#ibcon#*after write, iclass 21, count 0 2006.285.10:02:29.45#ibcon#*before return 0, iclass 21, count 0 2006.285.10:02:29.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:02:29.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:02:29.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:02:29.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:02:29.46$vck44/vb=4,5 2006.285.10:02:29.46#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.10:02:29.46#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.10:02:29.46#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:29.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:02:29.50#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:02:29.50#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:02:29.50#ibcon#enter wrdev, iclass 23, count 2 2006.285.10:02:29.50#ibcon#first serial, iclass 23, count 2 2006.285.10:02:29.50#ibcon#enter sib2, iclass 23, count 2 2006.285.10:02:29.50#ibcon#flushed, iclass 23, count 2 2006.285.10:02:29.50#ibcon#about to write, iclass 23, count 2 2006.285.10:02:29.50#ibcon#wrote, iclass 23, count 2 2006.285.10:02:29.50#ibcon#about to read 3, iclass 23, count 2 2006.285.10:02:29.52#ibcon#read 3, iclass 23, count 2 2006.285.10:02:29.52#ibcon#about to read 4, iclass 23, count 2 2006.285.10:02:29.52#ibcon#read 4, iclass 23, count 2 2006.285.10:02:29.52#ibcon#about to read 5, iclass 23, count 2 2006.285.10:02:29.52#ibcon#read 5, iclass 23, count 2 2006.285.10:02:29.52#ibcon#about to read 6, iclass 23, count 2 2006.285.10:02:29.52#ibcon#read 6, iclass 23, count 2 2006.285.10:02:29.52#ibcon#end of sib2, iclass 23, count 2 2006.285.10:02:29.52#ibcon#*mode == 0, iclass 23, count 2 2006.285.10:02:29.52#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.10:02:29.52#ibcon#[27=AT04-05\r\n] 2006.285.10:02:29.52#ibcon#*before write, iclass 23, count 2 2006.285.10:02:29.52#ibcon#enter sib2, iclass 23, count 2 2006.285.10:02:29.52#ibcon#flushed, iclass 23, count 2 2006.285.10:02:29.52#ibcon#about to write, iclass 23, count 2 2006.285.10:02:29.52#ibcon#wrote, iclass 23, count 2 2006.285.10:02:29.52#ibcon#about to read 3, iclass 23, count 2 2006.285.10:02:29.55#ibcon#read 3, iclass 23, count 2 2006.285.10:02:29.55#ibcon#about to read 4, iclass 23, count 2 2006.285.10:02:29.55#ibcon#read 4, iclass 23, count 2 2006.285.10:02:29.55#ibcon#about to read 5, iclass 23, count 2 2006.285.10:02:29.55#ibcon#read 5, iclass 23, count 2 2006.285.10:02:29.55#ibcon#about to read 6, iclass 23, count 2 2006.285.10:02:29.55#ibcon#read 6, iclass 23, count 2 2006.285.10:02:29.55#ibcon#end of sib2, iclass 23, count 2 2006.285.10:02:29.55#ibcon#*after write, iclass 23, count 2 2006.285.10:02:29.55#ibcon#*before return 0, iclass 23, count 2 2006.285.10:02:29.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:02:29.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:02:29.55#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.10:02:29.55#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:29.55#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:02:29.67#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:02:29.67#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:02:29.67#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:02:29.67#ibcon#first serial, iclass 23, count 0 2006.285.10:02:29.67#ibcon#enter sib2, iclass 23, count 0 2006.285.10:02:29.67#ibcon#flushed, iclass 23, count 0 2006.285.10:02:29.67#ibcon#about to write, iclass 23, count 0 2006.285.10:02:29.67#ibcon#wrote, iclass 23, count 0 2006.285.10:02:29.67#ibcon#about to read 3, iclass 23, count 0 2006.285.10:02:29.69#ibcon#read 3, iclass 23, count 0 2006.285.10:02:29.69#ibcon#about to read 4, iclass 23, count 0 2006.285.10:02:29.69#ibcon#read 4, iclass 23, count 0 2006.285.10:02:29.69#ibcon#about to read 5, iclass 23, count 0 2006.285.10:02:29.69#ibcon#read 5, iclass 23, count 0 2006.285.10:02:29.69#ibcon#about to read 6, iclass 23, count 0 2006.285.10:02:29.69#ibcon#read 6, iclass 23, count 0 2006.285.10:02:29.69#ibcon#end of sib2, iclass 23, count 0 2006.285.10:02:29.69#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:02:29.69#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:02:29.69#ibcon#[27=USB\r\n] 2006.285.10:02:29.69#ibcon#*before write, iclass 23, count 0 2006.285.10:02:29.69#ibcon#enter sib2, iclass 23, count 0 2006.285.10:02:29.69#ibcon#flushed, iclass 23, count 0 2006.285.10:02:29.69#ibcon#about to write, iclass 23, count 0 2006.285.10:02:29.69#ibcon#wrote, iclass 23, count 0 2006.285.10:02:29.69#ibcon#about to read 3, iclass 23, count 0 2006.285.10:02:29.72#ibcon#read 3, iclass 23, count 0 2006.285.10:02:29.72#ibcon#about to read 4, iclass 23, count 0 2006.285.10:02:29.72#ibcon#read 4, iclass 23, count 0 2006.285.10:02:29.72#ibcon#about to read 5, iclass 23, count 0 2006.285.10:02:29.72#ibcon#read 5, iclass 23, count 0 2006.285.10:02:29.72#ibcon#about to read 6, iclass 23, count 0 2006.285.10:02:29.72#ibcon#read 6, iclass 23, count 0 2006.285.10:02:29.72#ibcon#end of sib2, iclass 23, count 0 2006.285.10:02:29.72#ibcon#*after write, iclass 23, count 0 2006.285.10:02:29.72#ibcon#*before return 0, iclass 23, count 0 2006.285.10:02:29.72#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:02:29.72#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:02:29.72#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:02:29.72#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:02:29.73$vck44/vblo=5,709.99 2006.285.10:02:29.73#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.10:02:29.73#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.10:02:29.73#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:29.73#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:02:29.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:02:29.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:02:29.73#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:02:29.73#ibcon#first serial, iclass 25, count 0 2006.285.10:02:29.73#ibcon#enter sib2, iclass 25, count 0 2006.285.10:02:29.73#ibcon#flushed, iclass 25, count 0 2006.285.10:02:29.73#ibcon#about to write, iclass 25, count 0 2006.285.10:02:29.73#ibcon#wrote, iclass 25, count 0 2006.285.10:02:29.73#ibcon#about to read 3, iclass 25, count 0 2006.285.10:02:29.74#ibcon#read 3, iclass 25, count 0 2006.285.10:02:29.74#ibcon#about to read 4, iclass 25, count 0 2006.285.10:02:29.74#ibcon#read 4, iclass 25, count 0 2006.285.10:02:29.74#ibcon#about to read 5, iclass 25, count 0 2006.285.10:02:29.74#ibcon#read 5, iclass 25, count 0 2006.285.10:02:29.74#ibcon#about to read 6, iclass 25, count 0 2006.285.10:02:29.74#ibcon#read 6, iclass 25, count 0 2006.285.10:02:29.74#ibcon#end of sib2, iclass 25, count 0 2006.285.10:02:29.74#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:02:29.74#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:02:29.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:02:29.74#ibcon#*before write, iclass 25, count 0 2006.285.10:02:29.74#ibcon#enter sib2, iclass 25, count 0 2006.285.10:02:29.74#ibcon#flushed, iclass 25, count 0 2006.285.10:02:29.74#ibcon#about to write, iclass 25, count 0 2006.285.10:02:29.74#ibcon#wrote, iclass 25, count 0 2006.285.10:02:29.74#ibcon#about to read 3, iclass 25, count 0 2006.285.10:02:29.78#ibcon#read 3, iclass 25, count 0 2006.285.10:02:29.78#ibcon#about to read 4, iclass 25, count 0 2006.285.10:02:29.78#ibcon#read 4, iclass 25, count 0 2006.285.10:02:29.78#ibcon#about to read 5, iclass 25, count 0 2006.285.10:02:29.78#ibcon#read 5, iclass 25, count 0 2006.285.10:02:29.78#ibcon#about to read 6, iclass 25, count 0 2006.285.10:02:29.78#ibcon#read 6, iclass 25, count 0 2006.285.10:02:29.78#ibcon#end of sib2, iclass 25, count 0 2006.285.10:02:29.78#ibcon#*after write, iclass 25, count 0 2006.285.10:02:29.78#ibcon#*before return 0, iclass 25, count 0 2006.285.10:02:29.78#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:02:29.78#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:02:29.78#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:02:29.78#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:02:29.79$vck44/vb=5,4 2006.285.10:02:29.79#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.10:02:29.79#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.10:02:29.79#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:29.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:02:29.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:02:29.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:02:29.83#ibcon#enter wrdev, iclass 27, count 2 2006.285.10:02:29.83#ibcon#first serial, iclass 27, count 2 2006.285.10:02:29.83#ibcon#enter sib2, iclass 27, count 2 2006.285.10:02:29.83#ibcon#flushed, iclass 27, count 2 2006.285.10:02:29.83#ibcon#about to write, iclass 27, count 2 2006.285.10:02:29.83#ibcon#wrote, iclass 27, count 2 2006.285.10:02:29.83#ibcon#about to read 3, iclass 27, count 2 2006.285.10:02:29.85#ibcon#read 3, iclass 27, count 2 2006.285.10:02:29.85#ibcon#about to read 4, iclass 27, count 2 2006.285.10:02:29.85#ibcon#read 4, iclass 27, count 2 2006.285.10:02:29.85#ibcon#about to read 5, iclass 27, count 2 2006.285.10:02:29.85#ibcon#read 5, iclass 27, count 2 2006.285.10:02:29.85#ibcon#about to read 6, iclass 27, count 2 2006.285.10:02:29.85#ibcon#read 6, iclass 27, count 2 2006.285.10:02:29.85#ibcon#end of sib2, iclass 27, count 2 2006.285.10:02:29.85#ibcon#*mode == 0, iclass 27, count 2 2006.285.10:02:29.85#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.10:02:29.85#ibcon#[27=AT05-04\r\n] 2006.285.10:02:29.85#ibcon#*before write, iclass 27, count 2 2006.285.10:02:29.85#ibcon#enter sib2, iclass 27, count 2 2006.285.10:02:29.85#ibcon#flushed, iclass 27, count 2 2006.285.10:02:29.85#ibcon#about to write, iclass 27, count 2 2006.285.10:02:29.85#ibcon#wrote, iclass 27, count 2 2006.285.10:02:29.85#ibcon#about to read 3, iclass 27, count 2 2006.285.10:02:29.88#ibcon#read 3, iclass 27, count 2 2006.285.10:02:29.88#ibcon#about to read 4, iclass 27, count 2 2006.285.10:02:29.88#ibcon#read 4, iclass 27, count 2 2006.285.10:02:29.88#ibcon#about to read 5, iclass 27, count 2 2006.285.10:02:29.88#ibcon#read 5, iclass 27, count 2 2006.285.10:02:29.88#ibcon#about to read 6, iclass 27, count 2 2006.285.10:02:29.88#ibcon#read 6, iclass 27, count 2 2006.285.10:02:29.88#ibcon#end of sib2, iclass 27, count 2 2006.285.10:02:29.88#ibcon#*after write, iclass 27, count 2 2006.285.10:02:29.88#ibcon#*before return 0, iclass 27, count 2 2006.285.10:02:29.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:02:29.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:02:29.88#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.10:02:29.88#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:29.88#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:02:30.00#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:02:30.00#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:02:30.00#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:02:30.00#ibcon#first serial, iclass 27, count 0 2006.285.10:02:30.00#ibcon#enter sib2, iclass 27, count 0 2006.285.10:02:30.00#ibcon#flushed, iclass 27, count 0 2006.285.10:02:30.00#ibcon#about to write, iclass 27, count 0 2006.285.10:02:30.00#ibcon#wrote, iclass 27, count 0 2006.285.10:02:30.00#ibcon#about to read 3, iclass 27, count 0 2006.285.10:02:30.02#ibcon#read 3, iclass 27, count 0 2006.285.10:02:30.02#ibcon#about to read 4, iclass 27, count 0 2006.285.10:02:30.02#ibcon#read 4, iclass 27, count 0 2006.285.10:02:30.02#ibcon#about to read 5, iclass 27, count 0 2006.285.10:02:30.02#ibcon#read 5, iclass 27, count 0 2006.285.10:02:30.02#ibcon#about to read 6, iclass 27, count 0 2006.285.10:02:30.02#ibcon#read 6, iclass 27, count 0 2006.285.10:02:30.02#ibcon#end of sib2, iclass 27, count 0 2006.285.10:02:30.02#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:02:30.02#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:02:30.02#ibcon#[27=USB\r\n] 2006.285.10:02:30.02#ibcon#*before write, iclass 27, count 0 2006.285.10:02:30.02#ibcon#enter sib2, iclass 27, count 0 2006.285.10:02:30.02#ibcon#flushed, iclass 27, count 0 2006.285.10:02:30.02#ibcon#about to write, iclass 27, count 0 2006.285.10:02:30.02#ibcon#wrote, iclass 27, count 0 2006.285.10:02:30.02#ibcon#about to read 3, iclass 27, count 0 2006.285.10:02:30.05#ibcon#read 3, iclass 27, count 0 2006.285.10:02:30.05#ibcon#about to read 4, iclass 27, count 0 2006.285.10:02:30.05#ibcon#read 4, iclass 27, count 0 2006.285.10:02:30.05#ibcon#about to read 5, iclass 27, count 0 2006.285.10:02:30.05#ibcon#read 5, iclass 27, count 0 2006.285.10:02:30.05#ibcon#about to read 6, iclass 27, count 0 2006.285.10:02:30.05#ibcon#read 6, iclass 27, count 0 2006.285.10:02:30.05#ibcon#end of sib2, iclass 27, count 0 2006.285.10:02:30.05#ibcon#*after write, iclass 27, count 0 2006.285.10:02:30.05#ibcon#*before return 0, iclass 27, count 0 2006.285.10:02:30.05#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:02:30.05#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:02:30.05#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:02:30.05#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:02:30.06$vck44/vblo=6,719.99 2006.285.10:02:30.06#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.10:02:30.06#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.10:02:30.06#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:30.06#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:02:30.06#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:02:30.06#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:02:30.06#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:02:30.06#ibcon#first serial, iclass 29, count 0 2006.285.10:02:30.06#ibcon#enter sib2, iclass 29, count 0 2006.285.10:02:30.06#ibcon#flushed, iclass 29, count 0 2006.285.10:02:30.06#ibcon#about to write, iclass 29, count 0 2006.285.10:02:30.06#ibcon#wrote, iclass 29, count 0 2006.285.10:02:30.06#ibcon#about to read 3, iclass 29, count 0 2006.285.10:02:30.07#ibcon#read 3, iclass 29, count 0 2006.285.10:02:30.07#ibcon#about to read 4, iclass 29, count 0 2006.285.10:02:30.07#ibcon#read 4, iclass 29, count 0 2006.285.10:02:30.07#ibcon#about to read 5, iclass 29, count 0 2006.285.10:02:30.07#ibcon#read 5, iclass 29, count 0 2006.285.10:02:30.07#ibcon#about to read 6, iclass 29, count 0 2006.285.10:02:30.07#ibcon#read 6, iclass 29, count 0 2006.285.10:02:30.07#ibcon#end of sib2, iclass 29, count 0 2006.285.10:02:30.07#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:02:30.07#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:02:30.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:02:30.07#ibcon#*before write, iclass 29, count 0 2006.285.10:02:30.07#ibcon#enter sib2, iclass 29, count 0 2006.285.10:02:30.07#ibcon#flushed, iclass 29, count 0 2006.285.10:02:30.07#ibcon#about to write, iclass 29, count 0 2006.285.10:02:30.07#ibcon#wrote, iclass 29, count 0 2006.285.10:02:30.07#ibcon#about to read 3, iclass 29, count 0 2006.285.10:02:30.11#ibcon#read 3, iclass 29, count 0 2006.285.10:02:30.11#ibcon#about to read 4, iclass 29, count 0 2006.285.10:02:30.11#ibcon#read 4, iclass 29, count 0 2006.285.10:02:30.11#ibcon#about to read 5, iclass 29, count 0 2006.285.10:02:30.11#ibcon#read 5, iclass 29, count 0 2006.285.10:02:30.11#ibcon#about to read 6, iclass 29, count 0 2006.285.10:02:30.11#ibcon#read 6, iclass 29, count 0 2006.285.10:02:30.11#ibcon#end of sib2, iclass 29, count 0 2006.285.10:02:30.11#ibcon#*after write, iclass 29, count 0 2006.285.10:02:30.11#ibcon#*before return 0, iclass 29, count 0 2006.285.10:02:30.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:02:30.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:02:30.11#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:02:30.11#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:02:30.12$vck44/vb=6,3 2006.285.10:02:30.12#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.10:02:30.12#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.10:02:30.12#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:30.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:02:30.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:02:30.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:02:30.16#ibcon#enter wrdev, iclass 31, count 2 2006.285.10:02:30.16#ibcon#first serial, iclass 31, count 2 2006.285.10:02:30.16#ibcon#enter sib2, iclass 31, count 2 2006.285.10:02:30.16#ibcon#flushed, iclass 31, count 2 2006.285.10:02:30.16#ibcon#about to write, iclass 31, count 2 2006.285.10:02:30.16#ibcon#wrote, iclass 31, count 2 2006.285.10:02:30.16#ibcon#about to read 3, iclass 31, count 2 2006.285.10:02:30.18#ibcon#read 3, iclass 31, count 2 2006.285.10:02:30.18#ibcon#about to read 4, iclass 31, count 2 2006.285.10:02:30.18#ibcon#read 4, iclass 31, count 2 2006.285.10:02:30.18#ibcon#about to read 5, iclass 31, count 2 2006.285.10:02:30.18#ibcon#read 5, iclass 31, count 2 2006.285.10:02:30.18#ibcon#about to read 6, iclass 31, count 2 2006.285.10:02:30.18#ibcon#read 6, iclass 31, count 2 2006.285.10:02:30.18#ibcon#end of sib2, iclass 31, count 2 2006.285.10:02:30.18#ibcon#*mode == 0, iclass 31, count 2 2006.285.10:02:30.18#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.10:02:30.18#ibcon#[27=AT06-03\r\n] 2006.285.10:02:30.18#ibcon#*before write, iclass 31, count 2 2006.285.10:02:30.18#ibcon#enter sib2, iclass 31, count 2 2006.285.10:02:30.18#ibcon#flushed, iclass 31, count 2 2006.285.10:02:30.18#ibcon#about to write, iclass 31, count 2 2006.285.10:02:30.18#ibcon#wrote, iclass 31, count 2 2006.285.10:02:30.18#ibcon#about to read 3, iclass 31, count 2 2006.285.10:02:30.21#ibcon#read 3, iclass 31, count 2 2006.285.10:02:30.21#ibcon#about to read 4, iclass 31, count 2 2006.285.10:02:30.21#ibcon#read 4, iclass 31, count 2 2006.285.10:02:30.21#ibcon#about to read 5, iclass 31, count 2 2006.285.10:02:30.21#ibcon#read 5, iclass 31, count 2 2006.285.10:02:30.21#ibcon#about to read 6, iclass 31, count 2 2006.285.10:02:30.21#ibcon#read 6, iclass 31, count 2 2006.285.10:02:30.21#ibcon#end of sib2, iclass 31, count 2 2006.285.10:02:30.21#ibcon#*after write, iclass 31, count 2 2006.285.10:02:30.21#ibcon#*before return 0, iclass 31, count 2 2006.285.10:02:30.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:02:30.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:02:30.21#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.10:02:30.21#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:30.21#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:02:30.33#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:02:30.33#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:02:30.33#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:02:30.33#ibcon#first serial, iclass 31, count 0 2006.285.10:02:30.33#ibcon#enter sib2, iclass 31, count 0 2006.285.10:02:30.33#ibcon#flushed, iclass 31, count 0 2006.285.10:02:30.33#ibcon#about to write, iclass 31, count 0 2006.285.10:02:30.33#ibcon#wrote, iclass 31, count 0 2006.285.10:02:30.33#ibcon#about to read 3, iclass 31, count 0 2006.285.10:02:30.35#ibcon#read 3, iclass 31, count 0 2006.285.10:02:30.35#ibcon#about to read 4, iclass 31, count 0 2006.285.10:02:30.35#ibcon#read 4, iclass 31, count 0 2006.285.10:02:30.35#ibcon#about to read 5, iclass 31, count 0 2006.285.10:02:30.35#ibcon#read 5, iclass 31, count 0 2006.285.10:02:30.35#ibcon#about to read 6, iclass 31, count 0 2006.285.10:02:30.35#ibcon#read 6, iclass 31, count 0 2006.285.10:02:30.35#ibcon#end of sib2, iclass 31, count 0 2006.285.10:02:30.35#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:02:30.35#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:02:30.35#ibcon#[27=USB\r\n] 2006.285.10:02:30.35#ibcon#*before write, iclass 31, count 0 2006.285.10:02:30.35#ibcon#enter sib2, iclass 31, count 0 2006.285.10:02:30.35#ibcon#flushed, iclass 31, count 0 2006.285.10:02:30.35#ibcon#about to write, iclass 31, count 0 2006.285.10:02:30.35#ibcon#wrote, iclass 31, count 0 2006.285.10:02:30.35#ibcon#about to read 3, iclass 31, count 0 2006.285.10:02:30.38#ibcon#read 3, iclass 31, count 0 2006.285.10:02:30.38#ibcon#about to read 4, iclass 31, count 0 2006.285.10:02:30.38#ibcon#read 4, iclass 31, count 0 2006.285.10:02:30.38#ibcon#about to read 5, iclass 31, count 0 2006.285.10:02:30.38#ibcon#read 5, iclass 31, count 0 2006.285.10:02:30.38#ibcon#about to read 6, iclass 31, count 0 2006.285.10:02:30.38#ibcon#read 6, iclass 31, count 0 2006.285.10:02:30.38#ibcon#end of sib2, iclass 31, count 0 2006.285.10:02:30.38#ibcon#*after write, iclass 31, count 0 2006.285.10:02:30.38#ibcon#*before return 0, iclass 31, count 0 2006.285.10:02:30.38#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:02:30.38#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:02:30.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:02:30.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:02:30.39$vck44/vblo=7,734.99 2006.285.10:02:30.39#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.10:02:30.39#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.10:02:30.39#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:30.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:02:30.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:02:30.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:02:30.39#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:02:30.39#ibcon#first serial, iclass 33, count 0 2006.285.10:02:30.39#ibcon#enter sib2, iclass 33, count 0 2006.285.10:02:30.39#ibcon#flushed, iclass 33, count 0 2006.285.10:02:30.39#ibcon#about to write, iclass 33, count 0 2006.285.10:02:30.39#ibcon#wrote, iclass 33, count 0 2006.285.10:02:30.39#ibcon#about to read 3, iclass 33, count 0 2006.285.10:02:30.40#ibcon#read 3, iclass 33, count 0 2006.285.10:02:30.40#ibcon#about to read 4, iclass 33, count 0 2006.285.10:02:30.40#ibcon#read 4, iclass 33, count 0 2006.285.10:02:30.40#ibcon#about to read 5, iclass 33, count 0 2006.285.10:02:30.40#ibcon#read 5, iclass 33, count 0 2006.285.10:02:30.40#ibcon#about to read 6, iclass 33, count 0 2006.285.10:02:30.40#ibcon#read 6, iclass 33, count 0 2006.285.10:02:30.40#ibcon#end of sib2, iclass 33, count 0 2006.285.10:02:30.40#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:02:30.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:02:30.40#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:02:30.40#ibcon#*before write, iclass 33, count 0 2006.285.10:02:30.40#ibcon#enter sib2, iclass 33, count 0 2006.285.10:02:30.40#ibcon#flushed, iclass 33, count 0 2006.285.10:02:30.40#ibcon#about to write, iclass 33, count 0 2006.285.10:02:30.40#ibcon#wrote, iclass 33, count 0 2006.285.10:02:30.40#ibcon#about to read 3, iclass 33, count 0 2006.285.10:02:30.44#ibcon#read 3, iclass 33, count 0 2006.285.10:02:30.44#ibcon#about to read 4, iclass 33, count 0 2006.285.10:02:30.44#ibcon#read 4, iclass 33, count 0 2006.285.10:02:30.44#ibcon#about to read 5, iclass 33, count 0 2006.285.10:02:30.44#ibcon#read 5, iclass 33, count 0 2006.285.10:02:30.44#ibcon#about to read 6, iclass 33, count 0 2006.285.10:02:30.44#ibcon#read 6, iclass 33, count 0 2006.285.10:02:30.44#ibcon#end of sib2, iclass 33, count 0 2006.285.10:02:30.44#ibcon#*after write, iclass 33, count 0 2006.285.10:02:30.44#ibcon#*before return 0, iclass 33, count 0 2006.285.10:02:30.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:02:30.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:02:30.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:02:30.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:02:30.45$vck44/vb=7,4 2006.285.10:02:30.45#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.10:02:30.45#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.10:02:30.45#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:30.45#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:02:30.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:02:30.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:02:30.49#ibcon#enter wrdev, iclass 35, count 2 2006.285.10:02:30.49#ibcon#first serial, iclass 35, count 2 2006.285.10:02:30.49#ibcon#enter sib2, iclass 35, count 2 2006.285.10:02:30.49#ibcon#flushed, iclass 35, count 2 2006.285.10:02:30.49#ibcon#about to write, iclass 35, count 2 2006.285.10:02:30.49#ibcon#wrote, iclass 35, count 2 2006.285.10:02:30.49#ibcon#about to read 3, iclass 35, count 2 2006.285.10:02:30.51#ibcon#read 3, iclass 35, count 2 2006.285.10:02:30.51#ibcon#about to read 4, iclass 35, count 2 2006.285.10:02:30.51#ibcon#read 4, iclass 35, count 2 2006.285.10:02:30.51#ibcon#about to read 5, iclass 35, count 2 2006.285.10:02:30.51#ibcon#read 5, iclass 35, count 2 2006.285.10:02:30.51#ibcon#about to read 6, iclass 35, count 2 2006.285.10:02:30.51#ibcon#read 6, iclass 35, count 2 2006.285.10:02:30.51#ibcon#end of sib2, iclass 35, count 2 2006.285.10:02:30.51#ibcon#*mode == 0, iclass 35, count 2 2006.285.10:02:30.51#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.10:02:30.51#ibcon#[27=AT07-04\r\n] 2006.285.10:02:30.51#ibcon#*before write, iclass 35, count 2 2006.285.10:02:30.51#ibcon#enter sib2, iclass 35, count 2 2006.285.10:02:30.51#ibcon#flushed, iclass 35, count 2 2006.285.10:02:30.51#ibcon#about to write, iclass 35, count 2 2006.285.10:02:30.51#ibcon#wrote, iclass 35, count 2 2006.285.10:02:30.51#ibcon#about to read 3, iclass 35, count 2 2006.285.10:02:30.54#ibcon#read 3, iclass 35, count 2 2006.285.10:02:30.54#ibcon#about to read 4, iclass 35, count 2 2006.285.10:02:30.54#ibcon#read 4, iclass 35, count 2 2006.285.10:02:30.54#ibcon#about to read 5, iclass 35, count 2 2006.285.10:02:30.54#ibcon#read 5, iclass 35, count 2 2006.285.10:02:30.54#ibcon#about to read 6, iclass 35, count 2 2006.285.10:02:30.54#ibcon#read 6, iclass 35, count 2 2006.285.10:02:30.54#ibcon#end of sib2, iclass 35, count 2 2006.285.10:02:30.54#ibcon#*after write, iclass 35, count 2 2006.285.10:02:30.54#ibcon#*before return 0, iclass 35, count 2 2006.285.10:02:30.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:02:30.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:02:30.54#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.10:02:30.54#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:30.54#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:02:30.66#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:02:30.66#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:02:30.66#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:02:30.66#ibcon#first serial, iclass 35, count 0 2006.285.10:02:30.66#ibcon#enter sib2, iclass 35, count 0 2006.285.10:02:30.66#ibcon#flushed, iclass 35, count 0 2006.285.10:02:30.66#ibcon#about to write, iclass 35, count 0 2006.285.10:02:30.66#ibcon#wrote, iclass 35, count 0 2006.285.10:02:30.66#ibcon#about to read 3, iclass 35, count 0 2006.285.10:02:30.68#ibcon#read 3, iclass 35, count 0 2006.285.10:02:30.68#ibcon#about to read 4, iclass 35, count 0 2006.285.10:02:30.68#ibcon#read 4, iclass 35, count 0 2006.285.10:02:30.68#ibcon#about to read 5, iclass 35, count 0 2006.285.10:02:30.68#ibcon#read 5, iclass 35, count 0 2006.285.10:02:30.68#ibcon#about to read 6, iclass 35, count 0 2006.285.10:02:30.68#ibcon#read 6, iclass 35, count 0 2006.285.10:02:30.68#ibcon#end of sib2, iclass 35, count 0 2006.285.10:02:30.68#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:02:30.68#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:02:30.68#ibcon#[27=USB\r\n] 2006.285.10:02:30.68#ibcon#*before write, iclass 35, count 0 2006.285.10:02:30.68#ibcon#enter sib2, iclass 35, count 0 2006.285.10:02:30.68#ibcon#flushed, iclass 35, count 0 2006.285.10:02:30.68#ibcon#about to write, iclass 35, count 0 2006.285.10:02:30.68#ibcon#wrote, iclass 35, count 0 2006.285.10:02:30.68#ibcon#about to read 3, iclass 35, count 0 2006.285.10:02:30.71#ibcon#read 3, iclass 35, count 0 2006.285.10:02:30.71#ibcon#about to read 4, iclass 35, count 0 2006.285.10:02:30.71#ibcon#read 4, iclass 35, count 0 2006.285.10:02:30.71#ibcon#about to read 5, iclass 35, count 0 2006.285.10:02:30.71#ibcon#read 5, iclass 35, count 0 2006.285.10:02:30.71#ibcon#about to read 6, iclass 35, count 0 2006.285.10:02:30.71#ibcon#read 6, iclass 35, count 0 2006.285.10:02:30.71#ibcon#end of sib2, iclass 35, count 0 2006.285.10:02:30.71#ibcon#*after write, iclass 35, count 0 2006.285.10:02:30.71#ibcon#*before return 0, iclass 35, count 0 2006.285.10:02:30.71#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:02:30.71#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:02:30.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:02:30.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:02:30.72$vck44/vblo=8,744.99 2006.285.10:02:30.72#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.10:02:30.72#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.10:02:30.72#ibcon#ireg 17 cls_cnt 0 2006.285.10:02:30.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:02:30.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:02:30.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:02:30.72#ibcon#enter wrdev, iclass 37, count 0 2006.285.10:02:30.72#ibcon#first serial, iclass 37, count 0 2006.285.10:02:30.72#ibcon#enter sib2, iclass 37, count 0 2006.285.10:02:30.72#ibcon#flushed, iclass 37, count 0 2006.285.10:02:30.72#ibcon#about to write, iclass 37, count 0 2006.285.10:02:30.72#ibcon#wrote, iclass 37, count 0 2006.285.10:02:30.72#ibcon#about to read 3, iclass 37, count 0 2006.285.10:02:30.73#ibcon#read 3, iclass 37, count 0 2006.285.10:02:30.73#ibcon#about to read 4, iclass 37, count 0 2006.285.10:02:30.73#ibcon#read 4, iclass 37, count 0 2006.285.10:02:30.73#ibcon#about to read 5, iclass 37, count 0 2006.285.10:02:30.73#ibcon#read 5, iclass 37, count 0 2006.285.10:02:30.73#ibcon#about to read 6, iclass 37, count 0 2006.285.10:02:30.73#ibcon#read 6, iclass 37, count 0 2006.285.10:02:30.73#ibcon#end of sib2, iclass 37, count 0 2006.285.10:02:30.73#ibcon#*mode == 0, iclass 37, count 0 2006.285.10:02:30.73#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.10:02:30.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:02:30.73#ibcon#*before write, iclass 37, count 0 2006.285.10:02:30.73#ibcon#enter sib2, iclass 37, count 0 2006.285.10:02:30.73#ibcon#flushed, iclass 37, count 0 2006.285.10:02:30.73#ibcon#about to write, iclass 37, count 0 2006.285.10:02:30.73#ibcon#wrote, iclass 37, count 0 2006.285.10:02:30.73#ibcon#about to read 3, iclass 37, count 0 2006.285.10:02:30.77#ibcon#read 3, iclass 37, count 0 2006.285.10:02:30.77#ibcon#about to read 4, iclass 37, count 0 2006.285.10:02:30.77#ibcon#read 4, iclass 37, count 0 2006.285.10:02:30.77#ibcon#about to read 5, iclass 37, count 0 2006.285.10:02:30.77#ibcon#read 5, iclass 37, count 0 2006.285.10:02:30.77#ibcon#about to read 6, iclass 37, count 0 2006.285.10:02:30.77#ibcon#read 6, iclass 37, count 0 2006.285.10:02:30.77#ibcon#end of sib2, iclass 37, count 0 2006.285.10:02:30.77#ibcon#*after write, iclass 37, count 0 2006.285.10:02:30.77#ibcon#*before return 0, iclass 37, count 0 2006.285.10:02:30.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:02:30.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:02:30.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.10:02:30.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.10:02:30.78$vck44/vb=8,4 2006.285.10:02:30.78#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.10:02:30.78#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.10:02:30.78#ibcon#ireg 11 cls_cnt 2 2006.285.10:02:30.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:02:30.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:02:30.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:02:30.82#ibcon#enter wrdev, iclass 39, count 2 2006.285.10:02:30.82#ibcon#first serial, iclass 39, count 2 2006.285.10:02:30.82#ibcon#enter sib2, iclass 39, count 2 2006.285.10:02:30.82#ibcon#flushed, iclass 39, count 2 2006.285.10:02:30.82#ibcon#about to write, iclass 39, count 2 2006.285.10:02:30.82#ibcon#wrote, iclass 39, count 2 2006.285.10:02:30.82#ibcon#about to read 3, iclass 39, count 2 2006.285.10:02:30.84#ibcon#read 3, iclass 39, count 2 2006.285.10:02:30.84#ibcon#about to read 4, iclass 39, count 2 2006.285.10:02:30.84#ibcon#read 4, iclass 39, count 2 2006.285.10:02:30.84#ibcon#about to read 5, iclass 39, count 2 2006.285.10:02:30.84#ibcon#read 5, iclass 39, count 2 2006.285.10:02:30.84#ibcon#about to read 6, iclass 39, count 2 2006.285.10:02:30.84#ibcon#read 6, iclass 39, count 2 2006.285.10:02:30.84#ibcon#end of sib2, iclass 39, count 2 2006.285.10:02:30.84#ibcon#*mode == 0, iclass 39, count 2 2006.285.10:02:30.84#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.10:02:30.84#ibcon#[27=AT08-04\r\n] 2006.285.10:02:30.84#ibcon#*before write, iclass 39, count 2 2006.285.10:02:30.84#ibcon#enter sib2, iclass 39, count 2 2006.285.10:02:30.84#ibcon#flushed, iclass 39, count 2 2006.285.10:02:30.84#ibcon#about to write, iclass 39, count 2 2006.285.10:02:30.84#ibcon#wrote, iclass 39, count 2 2006.285.10:02:30.84#ibcon#about to read 3, iclass 39, count 2 2006.285.10:02:30.87#ibcon#read 3, iclass 39, count 2 2006.285.10:02:30.87#ibcon#about to read 4, iclass 39, count 2 2006.285.10:02:30.87#ibcon#read 4, iclass 39, count 2 2006.285.10:02:30.87#ibcon#about to read 5, iclass 39, count 2 2006.285.10:02:30.87#ibcon#read 5, iclass 39, count 2 2006.285.10:02:30.87#ibcon#about to read 6, iclass 39, count 2 2006.285.10:02:30.87#ibcon#read 6, iclass 39, count 2 2006.285.10:02:30.87#ibcon#end of sib2, iclass 39, count 2 2006.285.10:02:30.87#ibcon#*after write, iclass 39, count 2 2006.285.10:02:30.87#ibcon#*before return 0, iclass 39, count 2 2006.285.10:02:30.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:02:30.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:02:30.87#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.10:02:30.87#ibcon#ireg 7 cls_cnt 0 2006.285.10:02:30.87#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:02:30.99#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:02:30.99#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:02:30.99#ibcon#enter wrdev, iclass 39, count 0 2006.285.10:02:30.99#ibcon#first serial, iclass 39, count 0 2006.285.10:02:30.99#ibcon#enter sib2, iclass 39, count 0 2006.285.10:02:30.99#ibcon#flushed, iclass 39, count 0 2006.285.10:02:30.99#ibcon#about to write, iclass 39, count 0 2006.285.10:02:30.99#ibcon#wrote, iclass 39, count 0 2006.285.10:02:30.99#ibcon#about to read 3, iclass 39, count 0 2006.285.10:02:31.01#ibcon#read 3, iclass 39, count 0 2006.285.10:02:31.01#ibcon#about to read 4, iclass 39, count 0 2006.285.10:02:31.01#ibcon#read 4, iclass 39, count 0 2006.285.10:02:31.01#ibcon#about to read 5, iclass 39, count 0 2006.285.10:02:31.01#ibcon#read 5, iclass 39, count 0 2006.285.10:02:31.01#ibcon#about to read 6, iclass 39, count 0 2006.285.10:02:31.01#ibcon#read 6, iclass 39, count 0 2006.285.10:02:31.01#ibcon#end of sib2, iclass 39, count 0 2006.285.10:02:31.01#ibcon#*mode == 0, iclass 39, count 0 2006.285.10:02:31.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.10:02:31.01#ibcon#[27=USB\r\n] 2006.285.10:02:31.01#ibcon#*before write, iclass 39, count 0 2006.285.10:02:31.01#ibcon#enter sib2, iclass 39, count 0 2006.285.10:02:31.01#ibcon#flushed, iclass 39, count 0 2006.285.10:02:31.01#ibcon#about to write, iclass 39, count 0 2006.285.10:02:31.01#ibcon#wrote, iclass 39, count 0 2006.285.10:02:31.01#ibcon#about to read 3, iclass 39, count 0 2006.285.10:02:31.04#ibcon#read 3, iclass 39, count 0 2006.285.10:02:31.04#ibcon#about to read 4, iclass 39, count 0 2006.285.10:02:31.04#ibcon#read 4, iclass 39, count 0 2006.285.10:02:31.04#ibcon#about to read 5, iclass 39, count 0 2006.285.10:02:31.04#ibcon#read 5, iclass 39, count 0 2006.285.10:02:31.04#ibcon#about to read 6, iclass 39, count 0 2006.285.10:02:31.04#ibcon#read 6, iclass 39, count 0 2006.285.10:02:31.04#ibcon#end of sib2, iclass 39, count 0 2006.285.10:02:31.04#ibcon#*after write, iclass 39, count 0 2006.285.10:02:31.04#ibcon#*before return 0, iclass 39, count 0 2006.285.10:02:31.04#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:02:31.04#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:02:31.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.10:02:31.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.10:02:31.05$vck44/vabw=wide 2006.285.10:02:31.05#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.10:02:31.05#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.10:02:31.05#ibcon#ireg 8 cls_cnt 0 2006.285.10:02:31.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:02:31.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:02:31.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:02:31.05#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:02:31.05#ibcon#first serial, iclass 3, count 0 2006.285.10:02:31.05#ibcon#enter sib2, iclass 3, count 0 2006.285.10:02:31.05#ibcon#flushed, iclass 3, count 0 2006.285.10:02:31.05#ibcon#about to write, iclass 3, count 0 2006.285.10:02:31.05#ibcon#wrote, iclass 3, count 0 2006.285.10:02:31.05#ibcon#about to read 3, iclass 3, count 0 2006.285.10:02:31.06#ibcon#read 3, iclass 3, count 0 2006.285.10:02:31.06#ibcon#about to read 4, iclass 3, count 0 2006.285.10:02:31.06#ibcon#read 4, iclass 3, count 0 2006.285.10:02:31.06#ibcon#about to read 5, iclass 3, count 0 2006.285.10:02:31.06#ibcon#read 5, iclass 3, count 0 2006.285.10:02:31.06#ibcon#about to read 6, iclass 3, count 0 2006.285.10:02:31.06#ibcon#read 6, iclass 3, count 0 2006.285.10:02:31.06#ibcon#end of sib2, iclass 3, count 0 2006.285.10:02:31.06#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:02:31.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:02:31.06#ibcon#[25=BW32\r\n] 2006.285.10:02:31.06#ibcon#*before write, iclass 3, count 0 2006.285.10:02:31.06#ibcon#enter sib2, iclass 3, count 0 2006.285.10:02:31.06#ibcon#flushed, iclass 3, count 0 2006.285.10:02:31.06#ibcon#about to write, iclass 3, count 0 2006.285.10:02:31.06#ibcon#wrote, iclass 3, count 0 2006.285.10:02:31.06#ibcon#about to read 3, iclass 3, count 0 2006.285.10:02:31.09#ibcon#read 3, iclass 3, count 0 2006.285.10:02:31.09#ibcon#about to read 4, iclass 3, count 0 2006.285.10:02:31.09#ibcon#read 4, iclass 3, count 0 2006.285.10:02:31.09#ibcon#about to read 5, iclass 3, count 0 2006.285.10:02:31.09#ibcon#read 5, iclass 3, count 0 2006.285.10:02:31.09#ibcon#about to read 6, iclass 3, count 0 2006.285.10:02:31.09#ibcon#read 6, iclass 3, count 0 2006.285.10:02:31.09#ibcon#end of sib2, iclass 3, count 0 2006.285.10:02:31.09#ibcon#*after write, iclass 3, count 0 2006.285.10:02:31.09#ibcon#*before return 0, iclass 3, count 0 2006.285.10:02:31.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:02:31.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:02:31.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:02:31.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:02:31.10$vck44/vbbw=wide 2006.285.10:02:31.10#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.10:02:31.10#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.10:02:31.10#ibcon#ireg 8 cls_cnt 0 2006.285.10:02:31.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:02:31.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:02:31.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:02:31.15#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:02:31.15#ibcon#first serial, iclass 5, count 0 2006.285.10:02:31.15#ibcon#enter sib2, iclass 5, count 0 2006.285.10:02:31.15#ibcon#flushed, iclass 5, count 0 2006.285.10:02:31.15#ibcon#about to write, iclass 5, count 0 2006.285.10:02:31.15#ibcon#wrote, iclass 5, count 0 2006.285.10:02:31.15#ibcon#about to read 3, iclass 5, count 0 2006.285.10:02:31.17#ibcon#read 3, iclass 5, count 0 2006.285.10:02:31.17#ibcon#about to read 4, iclass 5, count 0 2006.285.10:02:31.17#ibcon#read 4, iclass 5, count 0 2006.285.10:02:31.17#ibcon#about to read 5, iclass 5, count 0 2006.285.10:02:31.17#ibcon#read 5, iclass 5, count 0 2006.285.10:02:31.17#ibcon#about to read 6, iclass 5, count 0 2006.285.10:02:31.17#ibcon#read 6, iclass 5, count 0 2006.285.10:02:31.17#ibcon#end of sib2, iclass 5, count 0 2006.285.10:02:31.17#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:02:31.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:02:31.17#ibcon#[27=BW32\r\n] 2006.285.10:02:31.17#ibcon#*before write, iclass 5, count 0 2006.285.10:02:31.17#ibcon#enter sib2, iclass 5, count 0 2006.285.10:02:31.17#ibcon#flushed, iclass 5, count 0 2006.285.10:02:31.17#ibcon#about to write, iclass 5, count 0 2006.285.10:02:31.17#ibcon#wrote, iclass 5, count 0 2006.285.10:02:31.17#ibcon#about to read 3, iclass 5, count 0 2006.285.10:02:31.20#ibcon#read 3, iclass 5, count 0 2006.285.10:02:31.20#ibcon#about to read 4, iclass 5, count 0 2006.285.10:02:31.20#ibcon#read 4, iclass 5, count 0 2006.285.10:02:31.20#ibcon#about to read 5, iclass 5, count 0 2006.285.10:02:31.20#ibcon#read 5, iclass 5, count 0 2006.285.10:02:31.20#ibcon#about to read 6, iclass 5, count 0 2006.285.10:02:31.20#ibcon#read 6, iclass 5, count 0 2006.285.10:02:31.20#ibcon#end of sib2, iclass 5, count 0 2006.285.10:02:31.20#ibcon#*after write, iclass 5, count 0 2006.285.10:02:31.20#ibcon#*before return 0, iclass 5, count 0 2006.285.10:02:31.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:02:31.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:02:31.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:02:31.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:02:31.21$setupk4/ifdk4 2006.285.10:02:31.21$ifdk4/lo= 2006.285.10:02:31.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:02:31.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:02:31.21$ifdk4/patch= 2006.285.10:02:31.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:02:31.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:02:31.21$setupk4/!*+20s 2006.285.10:02:35.09#abcon#<5=/05 1.2 1.7 19.43 931015.1\r\n> 2006.285.10:02:35.11#abcon#{5=INTERFACE CLEAR} 2006.285.10:02:35.17#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:02:41.14#trakl#Source acquired 2006.285.10:02:43.15#flagr#flagr/antenna,acquired 2006.285.10:02:45.47#abcon#<5=/05 1.2 1.7 19.43 931015.1\r\n> 2006.285.10:02:45.49#abcon#{5=INTERFACE CLEAR} 2006.285.10:02:45.55#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:02:45.87$setupk4/"tpicd 2006.285.10:02:45.87$setupk4/echo=off 2006.285.10:02:45.87$setupk4/xlog=off 2006.285.10:02:45.88:!2006.285.10:06:47 2006.285.10:06:47.01:preob 2006.285.10:06:48.14/onsource/TRACKING 2006.285.10:06:48.14:!2006.285.10:06:57 2006.285.10:06:57.00:"tape 2006.285.10:06:57.00:"st=record 2006.285.10:06:57.00:data_valid=on 2006.285.10:06:57.00:midob 2006.285.10:06:57.14/onsource/TRACKING 2006.285.10:06:57.15/wx/19.53,1015.1,92 2006.285.10:06:57.30/cable/+6.4844E-03 2006.285.10:06:58.39/va/01,07,usb,yes,31,34 2006.285.10:06:58.39/va/02,06,usb,yes,31,32 2006.285.10:06:58.39/va/03,07,usb,yes,31,33 2006.285.10:06:58.39/va/04,06,usb,yes,32,34 2006.285.10:06:58.39/va/05,03,usb,yes,32,32 2006.285.10:06:58.39/va/06,04,usb,yes,29,28 2006.285.10:06:58.39/va/07,04,usb,yes,29,30 2006.285.10:06:58.39/va/08,03,usb,yes,30,36 2006.285.10:06:58.62/valo/01,524.99,yes,locked 2006.285.10:06:58.62/valo/02,534.99,yes,locked 2006.285.10:06:58.62/valo/03,564.99,yes,locked 2006.285.10:06:58.62/valo/04,624.99,yes,locked 2006.285.10:06:58.62/valo/05,734.99,yes,locked 2006.285.10:06:58.62/valo/06,814.99,yes,locked 2006.285.10:06:58.62/valo/07,864.99,yes,locked 2006.285.10:06:58.62/valo/08,884.99,yes,locked 2006.285.10:06:59.71/vb/01,04,usb,yes,30,28 2006.285.10:06:59.71/vb/02,05,usb,yes,28,28 2006.285.10:06:59.71/vb/03,04,usb,yes,29,32 2006.285.10:06:59.71/vb/04,05,usb,yes,29,28 2006.285.10:06:59.71/vb/05,04,usb,yes,26,28 2006.285.10:06:59.71/vb/06,03,usb,yes,37,33 2006.285.10:06:59.71/vb/07,04,usb,yes,30,30 2006.285.10:06:59.71/vb/08,04,usb,yes,27,31 2006.285.10:06:59.94/vblo/01,629.99,yes,locked 2006.285.10:06:59.94/vblo/02,634.99,yes,locked 2006.285.10:06:59.94/vblo/03,649.99,yes,locked 2006.285.10:06:59.94/vblo/04,679.99,yes,locked 2006.285.10:06:59.94/vblo/05,709.99,yes,locked 2006.285.10:06:59.94/vblo/06,719.99,yes,locked 2006.285.10:06:59.94/vblo/07,734.99,yes,locked 2006.285.10:06:59.94/vblo/08,744.99,yes,locked 2006.285.10:07:00.09/vabw/8 2006.285.10:07:00.24/vbbw/8 2006.285.10:07:00.33/xfe/off,on,12.2 2006.285.10:07:00.71/ifatt/23,28,28,28 2006.285.10:07:01.07/fmout-gps/S +2.64E-07 2006.285.10:07:01.09:!2006.285.10:08:07 2006.285.10:08:07.00:data_valid=off 2006.285.10:08:07.00:"et 2006.285.10:08:07.00:!+3s 2006.285.10:08:10.01:"tape 2006.285.10:08:10.01:postob 2006.285.10:08:10.12/cable/+6.4853E-03 2006.285.10:08:10.12/wx/19.56,1015.1,91 2006.285.10:08:11.07/fmout-gps/S +2.67E-07 2006.285.10:08:11.07:scan_name=285-1012,jd0610,100 2006.285.10:08:11.07:source=2128-123,213135.26,-120704.8,2000.0,cw 2006.285.10:08:12.14#flagr#flagr/antenna,new-source 2006.285.10:08:12.14:checkk5 2006.285.10:08:12.98/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:08:13.38/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:08:13.88/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:08:14.25/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:08:14.66/chk_obsdata//k5ts1/T2851006??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:08:15.07/chk_obsdata//k5ts2/T2851006??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:08:15.44/chk_obsdata//k5ts3/T2851006??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:08:16.05/chk_obsdata//k5ts4/T2851006??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:08:16.87/k5log//k5ts1_log_newline 2006.285.10:08:17.66/k5log//k5ts2_log_newline 2006.285.10:08:18.51/k5log//k5ts3_log_newline 2006.285.10:08:19.37/k5log//k5ts4_log_newline 2006.285.10:08:19.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:08:19.39:setupk4=1 2006.285.10:08:19.39$setupk4/echo=on 2006.285.10:08:19.39$setupk4/pcalon 2006.285.10:08:19.39$pcalon/"no phase cal control is implemented here 2006.285.10:08:19.39$setupk4/"tpicd=stop 2006.285.10:08:19.39$setupk4/"rec=synch_on 2006.285.10:08:19.39$setupk4/"rec_mode=128 2006.285.10:08:19.39$setupk4/!* 2006.285.10:08:19.39$setupk4/recpk4 2006.285.10:08:19.39$recpk4/recpatch= 2006.285.10:08:19.39$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:08:19.39$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:08:19.39$setupk4/vck44 2006.285.10:08:19.39$vck44/valo=1,524.99 2006.285.10:08:19.39#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.10:08:19.39#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.10:08:19.39#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:19.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:08:19.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:08:19.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:08:19.39#ibcon#enter wrdev, iclass 40, count 0 2006.285.10:08:19.39#ibcon#first serial, iclass 40, count 0 2006.285.10:08:19.39#ibcon#enter sib2, iclass 40, count 0 2006.285.10:08:19.39#ibcon#flushed, iclass 40, count 0 2006.285.10:08:19.39#ibcon#about to write, iclass 40, count 0 2006.285.10:08:19.39#ibcon#wrote, iclass 40, count 0 2006.285.10:08:19.39#ibcon#about to read 3, iclass 40, count 0 2006.285.10:08:19.41#ibcon#read 3, iclass 40, count 0 2006.285.10:08:19.41#ibcon#about to read 4, iclass 40, count 0 2006.285.10:08:19.41#ibcon#read 4, iclass 40, count 0 2006.285.10:08:19.41#ibcon#about to read 5, iclass 40, count 0 2006.285.10:08:19.41#ibcon#read 5, iclass 40, count 0 2006.285.10:08:19.41#ibcon#about to read 6, iclass 40, count 0 2006.285.10:08:19.41#ibcon#read 6, iclass 40, count 0 2006.285.10:08:19.41#ibcon#end of sib2, iclass 40, count 0 2006.285.10:08:19.41#ibcon#*mode == 0, iclass 40, count 0 2006.285.10:08:19.41#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.10:08:19.41#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:08:19.41#ibcon#*before write, iclass 40, count 0 2006.285.10:08:19.41#ibcon#enter sib2, iclass 40, count 0 2006.285.10:08:19.41#ibcon#flushed, iclass 40, count 0 2006.285.10:08:19.41#ibcon#about to write, iclass 40, count 0 2006.285.10:08:19.41#ibcon#wrote, iclass 40, count 0 2006.285.10:08:19.41#ibcon#about to read 3, iclass 40, count 0 2006.285.10:08:19.46#ibcon#read 3, iclass 40, count 0 2006.285.10:08:19.46#ibcon#about to read 4, iclass 40, count 0 2006.285.10:08:19.46#ibcon#read 4, iclass 40, count 0 2006.285.10:08:19.46#ibcon#about to read 5, iclass 40, count 0 2006.285.10:08:19.46#ibcon#read 5, iclass 40, count 0 2006.285.10:08:19.46#ibcon#about to read 6, iclass 40, count 0 2006.285.10:08:19.46#ibcon#read 6, iclass 40, count 0 2006.285.10:08:19.46#ibcon#end of sib2, iclass 40, count 0 2006.285.10:08:19.46#ibcon#*after write, iclass 40, count 0 2006.285.10:08:19.46#ibcon#*before return 0, iclass 40, count 0 2006.285.10:08:19.46#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:08:19.46#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:08:19.46#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.10:08:19.46#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.10:08:19.47$vck44/va=1,7 2006.285.10:08:19.47#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.10:08:19.47#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.10:08:19.47#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:19.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:08:19.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:08:19.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:08:19.47#ibcon#enter wrdev, iclass 4, count 2 2006.285.10:08:19.47#ibcon#first serial, iclass 4, count 2 2006.285.10:08:19.47#ibcon#enter sib2, iclass 4, count 2 2006.285.10:08:19.47#ibcon#flushed, iclass 4, count 2 2006.285.10:08:19.47#ibcon#about to write, iclass 4, count 2 2006.285.10:08:19.47#ibcon#wrote, iclass 4, count 2 2006.285.10:08:19.47#ibcon#about to read 3, iclass 4, count 2 2006.285.10:08:19.48#ibcon#read 3, iclass 4, count 2 2006.285.10:08:19.48#ibcon#about to read 4, iclass 4, count 2 2006.285.10:08:19.48#ibcon#read 4, iclass 4, count 2 2006.285.10:08:19.48#ibcon#about to read 5, iclass 4, count 2 2006.285.10:08:19.48#ibcon#read 5, iclass 4, count 2 2006.285.10:08:19.48#ibcon#about to read 6, iclass 4, count 2 2006.285.10:08:19.48#ibcon#read 6, iclass 4, count 2 2006.285.10:08:19.48#ibcon#end of sib2, iclass 4, count 2 2006.285.10:08:19.48#ibcon#*mode == 0, iclass 4, count 2 2006.285.10:08:19.48#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.10:08:19.48#ibcon#[25=AT01-07\r\n] 2006.285.10:08:19.48#ibcon#*before write, iclass 4, count 2 2006.285.10:08:19.48#ibcon#enter sib2, iclass 4, count 2 2006.285.10:08:19.48#ibcon#flushed, iclass 4, count 2 2006.285.10:08:19.48#ibcon#about to write, iclass 4, count 2 2006.285.10:08:19.48#ibcon#wrote, iclass 4, count 2 2006.285.10:08:19.48#ibcon#about to read 3, iclass 4, count 2 2006.285.10:08:19.51#ibcon#read 3, iclass 4, count 2 2006.285.10:08:19.51#ibcon#about to read 4, iclass 4, count 2 2006.285.10:08:19.51#ibcon#read 4, iclass 4, count 2 2006.285.10:08:19.51#ibcon#about to read 5, iclass 4, count 2 2006.285.10:08:19.51#ibcon#read 5, iclass 4, count 2 2006.285.10:08:19.51#ibcon#about to read 6, iclass 4, count 2 2006.285.10:08:19.51#ibcon#read 6, iclass 4, count 2 2006.285.10:08:19.51#ibcon#end of sib2, iclass 4, count 2 2006.285.10:08:19.51#ibcon#*after write, iclass 4, count 2 2006.285.10:08:19.51#ibcon#*before return 0, iclass 4, count 2 2006.285.10:08:19.51#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:08:19.51#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:08:19.51#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.10:08:19.51#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:19.51#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:08:19.63#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:08:19.63#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:08:19.63#ibcon#enter wrdev, iclass 4, count 0 2006.285.10:08:19.63#ibcon#first serial, iclass 4, count 0 2006.285.10:08:19.63#ibcon#enter sib2, iclass 4, count 0 2006.285.10:08:19.63#ibcon#flushed, iclass 4, count 0 2006.285.10:08:19.63#ibcon#about to write, iclass 4, count 0 2006.285.10:08:19.63#ibcon#wrote, iclass 4, count 0 2006.285.10:08:19.63#ibcon#about to read 3, iclass 4, count 0 2006.285.10:08:19.65#ibcon#read 3, iclass 4, count 0 2006.285.10:08:19.65#ibcon#about to read 4, iclass 4, count 0 2006.285.10:08:19.65#ibcon#read 4, iclass 4, count 0 2006.285.10:08:19.65#ibcon#about to read 5, iclass 4, count 0 2006.285.10:08:19.65#ibcon#read 5, iclass 4, count 0 2006.285.10:08:19.65#ibcon#about to read 6, iclass 4, count 0 2006.285.10:08:19.65#ibcon#read 6, iclass 4, count 0 2006.285.10:08:19.65#ibcon#end of sib2, iclass 4, count 0 2006.285.10:08:19.65#ibcon#*mode == 0, iclass 4, count 0 2006.285.10:08:19.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.10:08:19.65#ibcon#[25=USB\r\n] 2006.285.10:08:19.65#ibcon#*before write, iclass 4, count 0 2006.285.10:08:19.65#ibcon#enter sib2, iclass 4, count 0 2006.285.10:08:19.65#ibcon#flushed, iclass 4, count 0 2006.285.10:08:19.65#ibcon#about to write, iclass 4, count 0 2006.285.10:08:19.65#ibcon#wrote, iclass 4, count 0 2006.285.10:08:19.65#ibcon#about to read 3, iclass 4, count 0 2006.285.10:08:19.68#ibcon#read 3, iclass 4, count 0 2006.285.10:08:19.68#ibcon#about to read 4, iclass 4, count 0 2006.285.10:08:19.68#ibcon#read 4, iclass 4, count 0 2006.285.10:08:19.68#ibcon#about to read 5, iclass 4, count 0 2006.285.10:08:19.68#ibcon#read 5, iclass 4, count 0 2006.285.10:08:19.68#ibcon#about to read 6, iclass 4, count 0 2006.285.10:08:19.68#ibcon#read 6, iclass 4, count 0 2006.285.10:08:19.68#ibcon#end of sib2, iclass 4, count 0 2006.285.10:08:19.68#ibcon#*after write, iclass 4, count 0 2006.285.10:08:19.68#ibcon#*before return 0, iclass 4, count 0 2006.285.10:08:19.68#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:08:19.68#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:08:19.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.10:08:19.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.10:08:19.69$vck44/valo=2,534.99 2006.285.10:08:19.69#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.10:08:19.69#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.10:08:19.69#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:19.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:08:19.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:08:19.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:08:19.69#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:08:19.69#ibcon#first serial, iclass 6, count 0 2006.285.10:08:19.69#ibcon#enter sib2, iclass 6, count 0 2006.285.10:08:19.69#ibcon#flushed, iclass 6, count 0 2006.285.10:08:19.69#ibcon#about to write, iclass 6, count 0 2006.285.10:08:19.69#ibcon#wrote, iclass 6, count 0 2006.285.10:08:19.69#ibcon#about to read 3, iclass 6, count 0 2006.285.10:08:19.70#ibcon#read 3, iclass 6, count 0 2006.285.10:08:19.70#ibcon#about to read 4, iclass 6, count 0 2006.285.10:08:19.70#ibcon#read 4, iclass 6, count 0 2006.285.10:08:19.70#ibcon#about to read 5, iclass 6, count 0 2006.285.10:08:19.70#ibcon#read 5, iclass 6, count 0 2006.285.10:08:19.70#ibcon#about to read 6, iclass 6, count 0 2006.285.10:08:19.70#ibcon#read 6, iclass 6, count 0 2006.285.10:08:19.70#ibcon#end of sib2, iclass 6, count 0 2006.285.10:08:19.70#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:08:19.70#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:08:19.70#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:08:19.70#ibcon#*before write, iclass 6, count 0 2006.285.10:08:19.70#ibcon#enter sib2, iclass 6, count 0 2006.285.10:08:19.70#ibcon#flushed, iclass 6, count 0 2006.285.10:08:19.70#ibcon#about to write, iclass 6, count 0 2006.285.10:08:19.70#ibcon#wrote, iclass 6, count 0 2006.285.10:08:19.70#ibcon#about to read 3, iclass 6, count 0 2006.285.10:08:19.74#ibcon#read 3, iclass 6, count 0 2006.285.10:08:19.74#ibcon#about to read 4, iclass 6, count 0 2006.285.10:08:19.74#ibcon#read 4, iclass 6, count 0 2006.285.10:08:19.74#ibcon#about to read 5, iclass 6, count 0 2006.285.10:08:19.74#ibcon#read 5, iclass 6, count 0 2006.285.10:08:19.74#ibcon#about to read 6, iclass 6, count 0 2006.285.10:08:19.74#ibcon#read 6, iclass 6, count 0 2006.285.10:08:19.74#ibcon#end of sib2, iclass 6, count 0 2006.285.10:08:19.74#ibcon#*after write, iclass 6, count 0 2006.285.10:08:19.74#ibcon#*before return 0, iclass 6, count 0 2006.285.10:08:19.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:08:19.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:08:19.74#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:08:19.74#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:08:19.76$vck44/va=2,6 2006.285.10:08:19.76#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.10:08:19.76#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.10:08:19.76#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:19.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:08:19.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:08:19.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:08:19.80#ibcon#enter wrdev, iclass 10, count 2 2006.285.10:08:19.80#ibcon#first serial, iclass 10, count 2 2006.285.10:08:19.80#ibcon#enter sib2, iclass 10, count 2 2006.285.10:08:19.80#ibcon#flushed, iclass 10, count 2 2006.285.10:08:19.80#ibcon#about to write, iclass 10, count 2 2006.285.10:08:19.80#ibcon#wrote, iclass 10, count 2 2006.285.10:08:19.80#ibcon#about to read 3, iclass 10, count 2 2006.285.10:08:19.82#ibcon#read 3, iclass 10, count 2 2006.285.10:08:19.82#ibcon#about to read 4, iclass 10, count 2 2006.285.10:08:19.82#ibcon#read 4, iclass 10, count 2 2006.285.10:08:19.82#ibcon#about to read 5, iclass 10, count 2 2006.285.10:08:19.82#ibcon#read 5, iclass 10, count 2 2006.285.10:08:19.82#ibcon#about to read 6, iclass 10, count 2 2006.285.10:08:19.82#ibcon#read 6, iclass 10, count 2 2006.285.10:08:19.82#ibcon#end of sib2, iclass 10, count 2 2006.285.10:08:19.82#ibcon#*mode == 0, iclass 10, count 2 2006.285.10:08:19.82#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.10:08:19.82#ibcon#[25=AT02-06\r\n] 2006.285.10:08:19.82#ibcon#*before write, iclass 10, count 2 2006.285.10:08:19.82#ibcon#enter sib2, iclass 10, count 2 2006.285.10:08:19.82#ibcon#flushed, iclass 10, count 2 2006.285.10:08:19.82#ibcon#about to write, iclass 10, count 2 2006.285.10:08:19.82#ibcon#wrote, iclass 10, count 2 2006.285.10:08:19.82#ibcon#about to read 3, iclass 10, count 2 2006.285.10:08:19.85#ibcon#read 3, iclass 10, count 2 2006.285.10:08:19.85#ibcon#about to read 4, iclass 10, count 2 2006.285.10:08:19.85#ibcon#read 4, iclass 10, count 2 2006.285.10:08:19.85#ibcon#about to read 5, iclass 10, count 2 2006.285.10:08:19.85#ibcon#read 5, iclass 10, count 2 2006.285.10:08:19.85#ibcon#about to read 6, iclass 10, count 2 2006.285.10:08:19.85#ibcon#read 6, iclass 10, count 2 2006.285.10:08:19.85#ibcon#end of sib2, iclass 10, count 2 2006.285.10:08:19.85#ibcon#*after write, iclass 10, count 2 2006.285.10:08:19.85#ibcon#*before return 0, iclass 10, count 2 2006.285.10:08:19.85#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:08:19.85#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:08:19.85#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.10:08:19.85#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:19.85#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:08:19.97#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:08:19.97#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:08:19.97#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:08:19.97#ibcon#first serial, iclass 10, count 0 2006.285.10:08:19.97#ibcon#enter sib2, iclass 10, count 0 2006.285.10:08:19.97#ibcon#flushed, iclass 10, count 0 2006.285.10:08:19.97#ibcon#about to write, iclass 10, count 0 2006.285.10:08:19.97#ibcon#wrote, iclass 10, count 0 2006.285.10:08:19.97#ibcon#about to read 3, iclass 10, count 0 2006.285.10:08:19.99#ibcon#read 3, iclass 10, count 0 2006.285.10:08:19.99#ibcon#about to read 4, iclass 10, count 0 2006.285.10:08:19.99#ibcon#read 4, iclass 10, count 0 2006.285.10:08:19.99#ibcon#about to read 5, iclass 10, count 0 2006.285.10:08:19.99#ibcon#read 5, iclass 10, count 0 2006.285.10:08:19.99#ibcon#about to read 6, iclass 10, count 0 2006.285.10:08:19.99#ibcon#read 6, iclass 10, count 0 2006.285.10:08:19.99#ibcon#end of sib2, iclass 10, count 0 2006.285.10:08:19.99#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:08:19.99#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:08:19.99#ibcon#[25=USB\r\n] 2006.285.10:08:19.99#ibcon#*before write, iclass 10, count 0 2006.285.10:08:19.99#ibcon#enter sib2, iclass 10, count 0 2006.285.10:08:19.99#ibcon#flushed, iclass 10, count 0 2006.285.10:08:19.99#ibcon#about to write, iclass 10, count 0 2006.285.10:08:19.99#ibcon#wrote, iclass 10, count 0 2006.285.10:08:19.99#ibcon#about to read 3, iclass 10, count 0 2006.285.10:08:20.02#ibcon#read 3, iclass 10, count 0 2006.285.10:08:20.02#ibcon#about to read 4, iclass 10, count 0 2006.285.10:08:20.02#ibcon#read 4, iclass 10, count 0 2006.285.10:08:20.02#ibcon#about to read 5, iclass 10, count 0 2006.285.10:08:20.02#ibcon#read 5, iclass 10, count 0 2006.285.10:08:20.02#ibcon#about to read 6, iclass 10, count 0 2006.285.10:08:20.02#ibcon#read 6, iclass 10, count 0 2006.285.10:08:20.02#ibcon#end of sib2, iclass 10, count 0 2006.285.10:08:20.02#ibcon#*after write, iclass 10, count 0 2006.285.10:08:20.02#ibcon#*before return 0, iclass 10, count 0 2006.285.10:08:20.02#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:08:20.02#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:08:20.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:08:20.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:08:20.02$vck44/valo=3,564.99 2006.285.10:08:20.02#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.10:08:20.02#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.10:08:20.02#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:20.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:08:20.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:08:20.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:08:20.03#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:08:20.03#ibcon#first serial, iclass 12, count 0 2006.285.10:08:20.03#ibcon#enter sib2, iclass 12, count 0 2006.285.10:08:20.03#ibcon#flushed, iclass 12, count 0 2006.285.10:08:20.03#ibcon#about to write, iclass 12, count 0 2006.285.10:08:20.03#ibcon#wrote, iclass 12, count 0 2006.285.10:08:20.03#ibcon#about to read 3, iclass 12, count 0 2006.285.10:08:20.04#ibcon#read 3, iclass 12, count 0 2006.285.10:08:20.04#ibcon#about to read 4, iclass 12, count 0 2006.285.10:08:20.04#ibcon#read 4, iclass 12, count 0 2006.285.10:08:20.04#ibcon#about to read 5, iclass 12, count 0 2006.285.10:08:20.04#ibcon#read 5, iclass 12, count 0 2006.285.10:08:20.04#ibcon#about to read 6, iclass 12, count 0 2006.285.10:08:20.04#ibcon#read 6, iclass 12, count 0 2006.285.10:08:20.04#ibcon#end of sib2, iclass 12, count 0 2006.285.10:08:20.04#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:08:20.04#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:08:20.04#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:08:20.04#ibcon#*before write, iclass 12, count 0 2006.285.10:08:20.04#ibcon#enter sib2, iclass 12, count 0 2006.285.10:08:20.04#ibcon#flushed, iclass 12, count 0 2006.285.10:08:20.04#ibcon#about to write, iclass 12, count 0 2006.285.10:08:20.04#ibcon#wrote, iclass 12, count 0 2006.285.10:08:20.04#ibcon#about to read 3, iclass 12, count 0 2006.285.10:08:20.08#ibcon#read 3, iclass 12, count 0 2006.285.10:08:20.08#ibcon#about to read 4, iclass 12, count 0 2006.285.10:08:20.08#ibcon#read 4, iclass 12, count 0 2006.285.10:08:20.08#ibcon#about to read 5, iclass 12, count 0 2006.285.10:08:20.08#ibcon#read 5, iclass 12, count 0 2006.285.10:08:20.08#ibcon#about to read 6, iclass 12, count 0 2006.285.10:08:20.08#ibcon#read 6, iclass 12, count 0 2006.285.10:08:20.08#ibcon#end of sib2, iclass 12, count 0 2006.285.10:08:20.08#ibcon#*after write, iclass 12, count 0 2006.285.10:08:20.08#ibcon#*before return 0, iclass 12, count 0 2006.285.10:08:20.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:08:20.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:08:20.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:08:20.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:08:20.08$vck44/va=3,7 2006.285.10:08:20.08#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.10:08:20.08#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.10:08:20.08#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:20.08#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:08:20.14#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:08:20.14#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:08:20.14#ibcon#enter wrdev, iclass 14, count 2 2006.285.10:08:20.14#ibcon#first serial, iclass 14, count 2 2006.285.10:08:20.14#ibcon#enter sib2, iclass 14, count 2 2006.285.10:08:20.14#ibcon#flushed, iclass 14, count 2 2006.285.10:08:20.14#ibcon#about to write, iclass 14, count 2 2006.285.10:08:20.14#ibcon#wrote, iclass 14, count 2 2006.285.10:08:20.14#ibcon#about to read 3, iclass 14, count 2 2006.285.10:08:20.16#ibcon#read 3, iclass 14, count 2 2006.285.10:08:20.16#ibcon#about to read 4, iclass 14, count 2 2006.285.10:08:20.16#ibcon#read 4, iclass 14, count 2 2006.285.10:08:20.16#ibcon#about to read 5, iclass 14, count 2 2006.285.10:08:20.16#ibcon#read 5, iclass 14, count 2 2006.285.10:08:20.16#ibcon#about to read 6, iclass 14, count 2 2006.285.10:08:20.16#ibcon#read 6, iclass 14, count 2 2006.285.10:08:20.16#ibcon#end of sib2, iclass 14, count 2 2006.285.10:08:20.16#ibcon#*mode == 0, iclass 14, count 2 2006.285.10:08:20.16#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.10:08:20.16#ibcon#[25=AT03-07\r\n] 2006.285.10:08:20.16#ibcon#*before write, iclass 14, count 2 2006.285.10:08:20.16#ibcon#enter sib2, iclass 14, count 2 2006.285.10:08:20.16#ibcon#flushed, iclass 14, count 2 2006.285.10:08:20.16#ibcon#about to write, iclass 14, count 2 2006.285.10:08:20.16#ibcon#wrote, iclass 14, count 2 2006.285.10:08:20.16#ibcon#about to read 3, iclass 14, count 2 2006.285.10:08:20.19#ibcon#read 3, iclass 14, count 2 2006.285.10:08:20.19#ibcon#about to read 4, iclass 14, count 2 2006.285.10:08:20.19#ibcon#read 4, iclass 14, count 2 2006.285.10:08:20.19#ibcon#about to read 5, iclass 14, count 2 2006.285.10:08:20.19#ibcon#read 5, iclass 14, count 2 2006.285.10:08:20.19#ibcon#about to read 6, iclass 14, count 2 2006.285.10:08:20.19#ibcon#read 6, iclass 14, count 2 2006.285.10:08:20.19#ibcon#end of sib2, iclass 14, count 2 2006.285.10:08:20.19#ibcon#*after write, iclass 14, count 2 2006.285.10:08:20.19#ibcon#*before return 0, iclass 14, count 2 2006.285.10:08:20.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:08:20.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:08:20.19#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.10:08:20.19#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:20.19#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:08:20.31#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:08:20.31#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:08:20.31#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:08:20.31#ibcon#first serial, iclass 14, count 0 2006.285.10:08:20.31#ibcon#enter sib2, iclass 14, count 0 2006.285.10:08:20.31#ibcon#flushed, iclass 14, count 0 2006.285.10:08:20.31#ibcon#about to write, iclass 14, count 0 2006.285.10:08:20.31#ibcon#wrote, iclass 14, count 0 2006.285.10:08:20.31#ibcon#about to read 3, iclass 14, count 0 2006.285.10:08:20.33#ibcon#read 3, iclass 14, count 0 2006.285.10:08:20.33#ibcon#about to read 4, iclass 14, count 0 2006.285.10:08:20.33#ibcon#read 4, iclass 14, count 0 2006.285.10:08:20.33#ibcon#about to read 5, iclass 14, count 0 2006.285.10:08:20.33#ibcon#read 5, iclass 14, count 0 2006.285.10:08:20.33#ibcon#about to read 6, iclass 14, count 0 2006.285.10:08:20.33#ibcon#read 6, iclass 14, count 0 2006.285.10:08:20.33#ibcon#end of sib2, iclass 14, count 0 2006.285.10:08:20.33#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:08:20.33#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:08:20.33#ibcon#[25=USB\r\n] 2006.285.10:08:20.33#ibcon#*before write, iclass 14, count 0 2006.285.10:08:20.33#ibcon#enter sib2, iclass 14, count 0 2006.285.10:08:20.33#ibcon#flushed, iclass 14, count 0 2006.285.10:08:20.33#ibcon#about to write, iclass 14, count 0 2006.285.10:08:20.33#ibcon#wrote, iclass 14, count 0 2006.285.10:08:20.33#ibcon#about to read 3, iclass 14, count 0 2006.285.10:08:20.36#ibcon#read 3, iclass 14, count 0 2006.285.10:08:20.36#ibcon#about to read 4, iclass 14, count 0 2006.285.10:08:20.36#ibcon#read 4, iclass 14, count 0 2006.285.10:08:20.36#ibcon#about to read 5, iclass 14, count 0 2006.285.10:08:20.36#ibcon#read 5, iclass 14, count 0 2006.285.10:08:20.36#ibcon#about to read 6, iclass 14, count 0 2006.285.10:08:20.36#ibcon#read 6, iclass 14, count 0 2006.285.10:08:20.36#ibcon#end of sib2, iclass 14, count 0 2006.285.10:08:20.36#ibcon#*after write, iclass 14, count 0 2006.285.10:08:20.36#ibcon#*before return 0, iclass 14, count 0 2006.285.10:08:20.36#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:08:20.36#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:08:20.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:08:20.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:08:20.36$vck44/valo=4,624.99 2006.285.10:08:20.36#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.10:08:20.36#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.10:08:20.36#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:20.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:08:20.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:08:20.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:08:20.36#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:08:20.36#ibcon#first serial, iclass 16, count 0 2006.285.10:08:20.36#ibcon#enter sib2, iclass 16, count 0 2006.285.10:08:20.36#ibcon#flushed, iclass 16, count 0 2006.285.10:08:20.36#ibcon#about to write, iclass 16, count 0 2006.285.10:08:20.36#ibcon#wrote, iclass 16, count 0 2006.285.10:08:20.36#ibcon#about to read 3, iclass 16, count 0 2006.285.10:08:20.38#ibcon#read 3, iclass 16, count 0 2006.285.10:08:20.38#ibcon#about to read 4, iclass 16, count 0 2006.285.10:08:20.38#ibcon#read 4, iclass 16, count 0 2006.285.10:08:20.38#ibcon#about to read 5, iclass 16, count 0 2006.285.10:08:20.38#ibcon#read 5, iclass 16, count 0 2006.285.10:08:20.38#ibcon#about to read 6, iclass 16, count 0 2006.285.10:08:20.38#ibcon#read 6, iclass 16, count 0 2006.285.10:08:20.38#ibcon#end of sib2, iclass 16, count 0 2006.285.10:08:20.38#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:08:20.38#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:08:20.38#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:08:20.38#ibcon#*before write, iclass 16, count 0 2006.285.10:08:20.38#ibcon#enter sib2, iclass 16, count 0 2006.285.10:08:20.38#ibcon#flushed, iclass 16, count 0 2006.285.10:08:20.38#ibcon#about to write, iclass 16, count 0 2006.285.10:08:20.38#ibcon#wrote, iclass 16, count 0 2006.285.10:08:20.38#ibcon#about to read 3, iclass 16, count 0 2006.285.10:08:20.42#ibcon#read 3, iclass 16, count 0 2006.285.10:08:20.42#ibcon#about to read 4, iclass 16, count 0 2006.285.10:08:20.42#ibcon#read 4, iclass 16, count 0 2006.285.10:08:20.42#ibcon#about to read 5, iclass 16, count 0 2006.285.10:08:20.42#ibcon#read 5, iclass 16, count 0 2006.285.10:08:20.42#ibcon#about to read 6, iclass 16, count 0 2006.285.10:08:20.42#ibcon#read 6, iclass 16, count 0 2006.285.10:08:20.42#ibcon#end of sib2, iclass 16, count 0 2006.285.10:08:20.42#ibcon#*after write, iclass 16, count 0 2006.285.10:08:20.42#ibcon#*before return 0, iclass 16, count 0 2006.285.10:08:20.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:08:20.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:08:20.42#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:08:20.42#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:08:20.42$vck44/va=4,6 2006.285.10:08:20.42#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.10:08:20.42#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.10:08:20.42#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:20.42#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:08:20.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:08:20.48#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:08:20.48#ibcon#enter wrdev, iclass 18, count 2 2006.285.10:08:20.48#ibcon#first serial, iclass 18, count 2 2006.285.10:08:20.48#ibcon#enter sib2, iclass 18, count 2 2006.285.10:08:20.48#ibcon#flushed, iclass 18, count 2 2006.285.10:08:20.48#ibcon#about to write, iclass 18, count 2 2006.285.10:08:20.48#ibcon#wrote, iclass 18, count 2 2006.285.10:08:20.48#ibcon#about to read 3, iclass 18, count 2 2006.285.10:08:20.50#ibcon#read 3, iclass 18, count 2 2006.285.10:08:20.50#ibcon#about to read 4, iclass 18, count 2 2006.285.10:08:20.50#ibcon#read 4, iclass 18, count 2 2006.285.10:08:20.50#ibcon#about to read 5, iclass 18, count 2 2006.285.10:08:20.50#ibcon#read 5, iclass 18, count 2 2006.285.10:08:20.50#ibcon#about to read 6, iclass 18, count 2 2006.285.10:08:20.50#ibcon#read 6, iclass 18, count 2 2006.285.10:08:20.50#ibcon#end of sib2, iclass 18, count 2 2006.285.10:08:20.50#ibcon#*mode == 0, iclass 18, count 2 2006.285.10:08:20.50#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.10:08:20.50#ibcon#[25=AT04-06\r\n] 2006.285.10:08:20.50#ibcon#*before write, iclass 18, count 2 2006.285.10:08:20.50#ibcon#enter sib2, iclass 18, count 2 2006.285.10:08:20.50#ibcon#flushed, iclass 18, count 2 2006.285.10:08:20.50#ibcon#about to write, iclass 18, count 2 2006.285.10:08:20.50#ibcon#wrote, iclass 18, count 2 2006.285.10:08:20.50#ibcon#about to read 3, iclass 18, count 2 2006.285.10:08:20.53#ibcon#read 3, iclass 18, count 2 2006.285.10:08:20.53#ibcon#about to read 4, iclass 18, count 2 2006.285.10:08:20.53#ibcon#read 4, iclass 18, count 2 2006.285.10:08:20.53#ibcon#about to read 5, iclass 18, count 2 2006.285.10:08:20.53#ibcon#read 5, iclass 18, count 2 2006.285.10:08:20.53#ibcon#about to read 6, iclass 18, count 2 2006.285.10:08:20.53#ibcon#read 6, iclass 18, count 2 2006.285.10:08:20.53#ibcon#end of sib2, iclass 18, count 2 2006.285.10:08:20.53#ibcon#*after write, iclass 18, count 2 2006.285.10:08:20.53#ibcon#*before return 0, iclass 18, count 2 2006.285.10:08:20.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:08:20.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:08:20.53#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.10:08:20.53#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:20.53#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:08:20.65#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:08:20.65#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:08:20.65#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:08:20.65#ibcon#first serial, iclass 18, count 0 2006.285.10:08:20.65#ibcon#enter sib2, iclass 18, count 0 2006.285.10:08:20.65#ibcon#flushed, iclass 18, count 0 2006.285.10:08:20.65#ibcon#about to write, iclass 18, count 0 2006.285.10:08:20.65#ibcon#wrote, iclass 18, count 0 2006.285.10:08:20.65#ibcon#about to read 3, iclass 18, count 0 2006.285.10:08:20.67#ibcon#read 3, iclass 18, count 0 2006.285.10:08:20.67#ibcon#about to read 4, iclass 18, count 0 2006.285.10:08:20.67#ibcon#read 4, iclass 18, count 0 2006.285.10:08:20.67#ibcon#about to read 5, iclass 18, count 0 2006.285.10:08:20.67#ibcon#read 5, iclass 18, count 0 2006.285.10:08:20.67#ibcon#about to read 6, iclass 18, count 0 2006.285.10:08:20.67#ibcon#read 6, iclass 18, count 0 2006.285.10:08:20.67#ibcon#end of sib2, iclass 18, count 0 2006.285.10:08:20.67#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:08:20.67#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:08:20.67#ibcon#[25=USB\r\n] 2006.285.10:08:20.67#ibcon#*before write, iclass 18, count 0 2006.285.10:08:20.67#ibcon#enter sib2, iclass 18, count 0 2006.285.10:08:20.67#ibcon#flushed, iclass 18, count 0 2006.285.10:08:20.67#ibcon#about to write, iclass 18, count 0 2006.285.10:08:20.67#ibcon#wrote, iclass 18, count 0 2006.285.10:08:20.67#ibcon#about to read 3, iclass 18, count 0 2006.285.10:08:20.70#ibcon#read 3, iclass 18, count 0 2006.285.10:08:20.70#ibcon#about to read 4, iclass 18, count 0 2006.285.10:08:20.70#ibcon#read 4, iclass 18, count 0 2006.285.10:08:20.70#ibcon#about to read 5, iclass 18, count 0 2006.285.10:08:20.70#ibcon#read 5, iclass 18, count 0 2006.285.10:08:20.70#ibcon#about to read 6, iclass 18, count 0 2006.285.10:08:20.70#ibcon#read 6, iclass 18, count 0 2006.285.10:08:20.70#ibcon#end of sib2, iclass 18, count 0 2006.285.10:08:20.70#ibcon#*after write, iclass 18, count 0 2006.285.10:08:20.70#ibcon#*before return 0, iclass 18, count 0 2006.285.10:08:20.70#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:08:20.70#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:08:20.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:08:20.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:08:20.70$vck44/valo=5,734.99 2006.285.10:08:20.70#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.10:08:20.70#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.10:08:20.70#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:20.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:08:20.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:08:20.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:08:20.70#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:08:20.70#ibcon#first serial, iclass 20, count 0 2006.285.10:08:20.70#ibcon#enter sib2, iclass 20, count 0 2006.285.10:08:20.70#ibcon#flushed, iclass 20, count 0 2006.285.10:08:20.70#ibcon#about to write, iclass 20, count 0 2006.285.10:08:20.70#ibcon#wrote, iclass 20, count 0 2006.285.10:08:20.70#ibcon#about to read 3, iclass 20, count 0 2006.285.10:08:20.72#ibcon#read 3, iclass 20, count 0 2006.285.10:08:20.72#ibcon#about to read 4, iclass 20, count 0 2006.285.10:08:20.72#ibcon#read 4, iclass 20, count 0 2006.285.10:08:20.72#ibcon#about to read 5, iclass 20, count 0 2006.285.10:08:20.72#ibcon#read 5, iclass 20, count 0 2006.285.10:08:20.72#ibcon#about to read 6, iclass 20, count 0 2006.285.10:08:20.72#ibcon#read 6, iclass 20, count 0 2006.285.10:08:20.72#ibcon#end of sib2, iclass 20, count 0 2006.285.10:08:20.72#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:08:20.72#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:08:20.72#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:08:20.72#ibcon#*before write, iclass 20, count 0 2006.285.10:08:20.72#ibcon#enter sib2, iclass 20, count 0 2006.285.10:08:20.72#ibcon#flushed, iclass 20, count 0 2006.285.10:08:20.72#ibcon#about to write, iclass 20, count 0 2006.285.10:08:20.72#ibcon#wrote, iclass 20, count 0 2006.285.10:08:20.72#ibcon#about to read 3, iclass 20, count 0 2006.285.10:08:20.76#ibcon#read 3, iclass 20, count 0 2006.285.10:08:20.76#ibcon#about to read 4, iclass 20, count 0 2006.285.10:08:20.76#ibcon#read 4, iclass 20, count 0 2006.285.10:08:20.76#ibcon#about to read 5, iclass 20, count 0 2006.285.10:08:20.76#ibcon#read 5, iclass 20, count 0 2006.285.10:08:20.76#ibcon#about to read 6, iclass 20, count 0 2006.285.10:08:20.76#ibcon#read 6, iclass 20, count 0 2006.285.10:08:20.76#ibcon#end of sib2, iclass 20, count 0 2006.285.10:08:20.76#ibcon#*after write, iclass 20, count 0 2006.285.10:08:20.76#ibcon#*before return 0, iclass 20, count 0 2006.285.10:08:20.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:08:20.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:08:20.76#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:08:20.76#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:08:20.76$vck44/va=5,3 2006.285.10:08:20.77#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.10:08:20.77#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.10:08:20.77#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:20.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:08:20.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:08:20.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:08:20.81#ibcon#enter wrdev, iclass 22, count 2 2006.285.10:08:20.81#ibcon#first serial, iclass 22, count 2 2006.285.10:08:20.81#ibcon#enter sib2, iclass 22, count 2 2006.285.10:08:20.81#ibcon#flushed, iclass 22, count 2 2006.285.10:08:20.81#ibcon#about to write, iclass 22, count 2 2006.285.10:08:20.81#ibcon#wrote, iclass 22, count 2 2006.285.10:08:20.81#ibcon#about to read 3, iclass 22, count 2 2006.285.10:08:20.83#ibcon#read 3, iclass 22, count 2 2006.285.10:08:20.83#ibcon#about to read 4, iclass 22, count 2 2006.285.10:08:20.83#ibcon#read 4, iclass 22, count 2 2006.285.10:08:20.83#ibcon#about to read 5, iclass 22, count 2 2006.285.10:08:20.83#ibcon#read 5, iclass 22, count 2 2006.285.10:08:20.83#ibcon#about to read 6, iclass 22, count 2 2006.285.10:08:20.83#ibcon#read 6, iclass 22, count 2 2006.285.10:08:20.83#ibcon#end of sib2, iclass 22, count 2 2006.285.10:08:20.83#ibcon#*mode == 0, iclass 22, count 2 2006.285.10:08:20.83#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.10:08:20.83#ibcon#[25=AT05-03\r\n] 2006.285.10:08:20.83#ibcon#*before write, iclass 22, count 2 2006.285.10:08:20.83#ibcon#enter sib2, iclass 22, count 2 2006.285.10:08:20.83#ibcon#flushed, iclass 22, count 2 2006.285.10:08:20.83#ibcon#about to write, iclass 22, count 2 2006.285.10:08:20.83#ibcon#wrote, iclass 22, count 2 2006.285.10:08:20.83#ibcon#about to read 3, iclass 22, count 2 2006.285.10:08:20.86#ibcon#read 3, iclass 22, count 2 2006.285.10:08:20.86#ibcon#about to read 4, iclass 22, count 2 2006.285.10:08:20.86#ibcon#read 4, iclass 22, count 2 2006.285.10:08:20.86#ibcon#about to read 5, iclass 22, count 2 2006.285.10:08:20.86#ibcon#read 5, iclass 22, count 2 2006.285.10:08:20.86#ibcon#about to read 6, iclass 22, count 2 2006.285.10:08:20.86#ibcon#read 6, iclass 22, count 2 2006.285.10:08:20.86#ibcon#end of sib2, iclass 22, count 2 2006.285.10:08:20.86#ibcon#*after write, iclass 22, count 2 2006.285.10:08:20.86#ibcon#*before return 0, iclass 22, count 2 2006.285.10:08:20.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:08:20.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:08:20.86#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.10:08:20.86#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:20.86#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:08:20.98#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:08:20.98#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:08:20.98#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:08:20.98#ibcon#first serial, iclass 22, count 0 2006.285.10:08:20.98#ibcon#enter sib2, iclass 22, count 0 2006.285.10:08:20.98#ibcon#flushed, iclass 22, count 0 2006.285.10:08:20.98#ibcon#about to write, iclass 22, count 0 2006.285.10:08:20.98#ibcon#wrote, iclass 22, count 0 2006.285.10:08:20.98#ibcon#about to read 3, iclass 22, count 0 2006.285.10:08:21.00#ibcon#read 3, iclass 22, count 0 2006.285.10:08:21.00#ibcon#about to read 4, iclass 22, count 0 2006.285.10:08:21.00#ibcon#read 4, iclass 22, count 0 2006.285.10:08:21.00#ibcon#about to read 5, iclass 22, count 0 2006.285.10:08:21.00#ibcon#read 5, iclass 22, count 0 2006.285.10:08:21.00#ibcon#about to read 6, iclass 22, count 0 2006.285.10:08:21.00#ibcon#read 6, iclass 22, count 0 2006.285.10:08:21.00#ibcon#end of sib2, iclass 22, count 0 2006.285.10:08:21.00#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:08:21.00#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:08:21.00#ibcon#[25=USB\r\n] 2006.285.10:08:21.00#ibcon#*before write, iclass 22, count 0 2006.285.10:08:21.00#ibcon#enter sib2, iclass 22, count 0 2006.285.10:08:21.00#ibcon#flushed, iclass 22, count 0 2006.285.10:08:21.00#ibcon#about to write, iclass 22, count 0 2006.285.10:08:21.00#ibcon#wrote, iclass 22, count 0 2006.285.10:08:21.00#ibcon#about to read 3, iclass 22, count 0 2006.285.10:08:21.03#ibcon#read 3, iclass 22, count 0 2006.285.10:08:21.03#ibcon#about to read 4, iclass 22, count 0 2006.285.10:08:21.03#ibcon#read 4, iclass 22, count 0 2006.285.10:08:21.03#ibcon#about to read 5, iclass 22, count 0 2006.285.10:08:21.03#ibcon#read 5, iclass 22, count 0 2006.285.10:08:21.03#ibcon#about to read 6, iclass 22, count 0 2006.285.10:08:21.03#ibcon#read 6, iclass 22, count 0 2006.285.10:08:21.03#ibcon#end of sib2, iclass 22, count 0 2006.285.10:08:21.03#ibcon#*after write, iclass 22, count 0 2006.285.10:08:21.03#ibcon#*before return 0, iclass 22, count 0 2006.285.10:08:21.03#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:08:21.03#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:08:21.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:08:21.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:08:21.03$vck44/valo=6,814.99 2006.285.10:08:21.03#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.10:08:21.03#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.10:08:21.03#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:21.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:08:21.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:08:21.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:08:21.03#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:08:21.03#ibcon#first serial, iclass 24, count 0 2006.285.10:08:21.04#ibcon#enter sib2, iclass 24, count 0 2006.285.10:08:21.04#ibcon#flushed, iclass 24, count 0 2006.285.10:08:21.04#ibcon#about to write, iclass 24, count 0 2006.285.10:08:21.04#ibcon#wrote, iclass 24, count 0 2006.285.10:08:21.04#ibcon#about to read 3, iclass 24, count 0 2006.285.10:08:21.05#ibcon#read 3, iclass 24, count 0 2006.285.10:08:21.05#ibcon#about to read 4, iclass 24, count 0 2006.285.10:08:21.05#ibcon#read 4, iclass 24, count 0 2006.285.10:08:21.05#ibcon#about to read 5, iclass 24, count 0 2006.285.10:08:21.05#ibcon#read 5, iclass 24, count 0 2006.285.10:08:21.05#ibcon#about to read 6, iclass 24, count 0 2006.285.10:08:21.05#ibcon#read 6, iclass 24, count 0 2006.285.10:08:21.05#ibcon#end of sib2, iclass 24, count 0 2006.285.10:08:21.05#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:08:21.05#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:08:21.05#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:08:21.05#ibcon#*before write, iclass 24, count 0 2006.285.10:08:21.05#ibcon#enter sib2, iclass 24, count 0 2006.285.10:08:21.05#ibcon#flushed, iclass 24, count 0 2006.285.10:08:21.05#ibcon#about to write, iclass 24, count 0 2006.285.10:08:21.05#ibcon#wrote, iclass 24, count 0 2006.285.10:08:21.05#ibcon#about to read 3, iclass 24, count 0 2006.285.10:08:21.09#ibcon#read 3, iclass 24, count 0 2006.285.10:08:21.09#ibcon#about to read 4, iclass 24, count 0 2006.285.10:08:21.09#ibcon#read 4, iclass 24, count 0 2006.285.10:08:21.09#ibcon#about to read 5, iclass 24, count 0 2006.285.10:08:21.09#ibcon#read 5, iclass 24, count 0 2006.285.10:08:21.09#ibcon#about to read 6, iclass 24, count 0 2006.285.10:08:21.09#ibcon#read 6, iclass 24, count 0 2006.285.10:08:21.09#ibcon#end of sib2, iclass 24, count 0 2006.285.10:08:21.09#ibcon#*after write, iclass 24, count 0 2006.285.10:08:21.09#ibcon#*before return 0, iclass 24, count 0 2006.285.10:08:21.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:08:21.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:08:21.09#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:08:21.09#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:08:21.09$vck44/va=6,4 2006.285.10:08:21.09#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.10:08:21.09#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.10:08:21.09#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:21.09#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:08:21.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:08:21.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:08:21.15#ibcon#enter wrdev, iclass 26, count 2 2006.285.10:08:21.15#ibcon#first serial, iclass 26, count 2 2006.285.10:08:21.15#ibcon#enter sib2, iclass 26, count 2 2006.285.10:08:21.15#ibcon#flushed, iclass 26, count 2 2006.285.10:08:21.15#ibcon#about to write, iclass 26, count 2 2006.285.10:08:21.15#ibcon#wrote, iclass 26, count 2 2006.285.10:08:21.15#ibcon#about to read 3, iclass 26, count 2 2006.285.10:08:21.17#ibcon#read 3, iclass 26, count 2 2006.285.10:08:21.17#ibcon#about to read 4, iclass 26, count 2 2006.285.10:08:21.17#ibcon#read 4, iclass 26, count 2 2006.285.10:08:21.17#ibcon#about to read 5, iclass 26, count 2 2006.285.10:08:21.17#ibcon#read 5, iclass 26, count 2 2006.285.10:08:21.17#ibcon#about to read 6, iclass 26, count 2 2006.285.10:08:21.17#ibcon#read 6, iclass 26, count 2 2006.285.10:08:21.17#ibcon#end of sib2, iclass 26, count 2 2006.285.10:08:21.17#ibcon#*mode == 0, iclass 26, count 2 2006.285.10:08:21.17#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.10:08:21.17#ibcon#[25=AT06-04\r\n] 2006.285.10:08:21.17#ibcon#*before write, iclass 26, count 2 2006.285.10:08:21.17#ibcon#enter sib2, iclass 26, count 2 2006.285.10:08:21.17#ibcon#flushed, iclass 26, count 2 2006.285.10:08:21.17#ibcon#about to write, iclass 26, count 2 2006.285.10:08:21.17#ibcon#wrote, iclass 26, count 2 2006.285.10:08:21.17#ibcon#about to read 3, iclass 26, count 2 2006.285.10:08:21.17#abcon#<5=/05 1.2 1.9 19.57 911015.1\r\n> 2006.285.10:08:21.19#abcon#{5=INTERFACE CLEAR} 2006.285.10:08:21.20#ibcon#read 3, iclass 26, count 2 2006.285.10:08:21.20#ibcon#about to read 4, iclass 26, count 2 2006.285.10:08:21.20#ibcon#read 4, iclass 26, count 2 2006.285.10:08:21.20#ibcon#about to read 5, iclass 26, count 2 2006.285.10:08:21.20#ibcon#read 5, iclass 26, count 2 2006.285.10:08:21.20#ibcon#about to read 6, iclass 26, count 2 2006.285.10:08:21.20#ibcon#read 6, iclass 26, count 2 2006.285.10:08:21.20#ibcon#end of sib2, iclass 26, count 2 2006.285.10:08:21.20#ibcon#*after write, iclass 26, count 2 2006.285.10:08:21.20#ibcon#*before return 0, iclass 26, count 2 2006.285.10:08:21.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:08:21.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:08:21.20#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.10:08:21.20#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:21.20#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:08:21.25#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:08:21.32#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:08:21.32#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:08:21.32#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:08:21.32#ibcon#first serial, iclass 26, count 0 2006.285.10:08:21.32#ibcon#enter sib2, iclass 26, count 0 2006.285.10:08:21.32#ibcon#flushed, iclass 26, count 0 2006.285.10:08:21.32#ibcon#about to write, iclass 26, count 0 2006.285.10:08:21.32#ibcon#wrote, iclass 26, count 0 2006.285.10:08:21.32#ibcon#about to read 3, iclass 26, count 0 2006.285.10:08:21.34#ibcon#read 3, iclass 26, count 0 2006.285.10:08:21.34#ibcon#about to read 4, iclass 26, count 0 2006.285.10:08:21.34#ibcon#read 4, iclass 26, count 0 2006.285.10:08:21.34#ibcon#about to read 5, iclass 26, count 0 2006.285.10:08:21.34#ibcon#read 5, iclass 26, count 0 2006.285.10:08:21.34#ibcon#about to read 6, iclass 26, count 0 2006.285.10:08:21.34#ibcon#read 6, iclass 26, count 0 2006.285.10:08:21.34#ibcon#end of sib2, iclass 26, count 0 2006.285.10:08:21.34#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:08:21.34#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:08:21.34#ibcon#[25=USB\r\n] 2006.285.10:08:21.34#ibcon#*before write, iclass 26, count 0 2006.285.10:08:21.34#ibcon#enter sib2, iclass 26, count 0 2006.285.10:08:21.34#ibcon#flushed, iclass 26, count 0 2006.285.10:08:21.34#ibcon#about to write, iclass 26, count 0 2006.285.10:08:21.34#ibcon#wrote, iclass 26, count 0 2006.285.10:08:21.34#ibcon#about to read 3, iclass 26, count 0 2006.285.10:08:21.37#ibcon#read 3, iclass 26, count 0 2006.285.10:08:21.37#ibcon#about to read 4, iclass 26, count 0 2006.285.10:08:21.37#ibcon#read 4, iclass 26, count 0 2006.285.10:08:21.37#ibcon#about to read 5, iclass 26, count 0 2006.285.10:08:21.37#ibcon#read 5, iclass 26, count 0 2006.285.10:08:21.37#ibcon#about to read 6, iclass 26, count 0 2006.285.10:08:21.37#ibcon#read 6, iclass 26, count 0 2006.285.10:08:21.37#ibcon#end of sib2, iclass 26, count 0 2006.285.10:08:21.37#ibcon#*after write, iclass 26, count 0 2006.285.10:08:21.37#ibcon#*before return 0, iclass 26, count 0 2006.285.10:08:21.37#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:08:21.37#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:08:21.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:08:21.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:08:21.37$vck44/valo=7,864.99 2006.285.10:08:21.37#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.10:08:21.37#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.10:08:21.37#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:21.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:08:21.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:08:21.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:08:21.37#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:08:21.37#ibcon#first serial, iclass 32, count 0 2006.285.10:08:21.37#ibcon#enter sib2, iclass 32, count 0 2006.285.10:08:21.37#ibcon#flushed, iclass 32, count 0 2006.285.10:08:21.37#ibcon#about to write, iclass 32, count 0 2006.285.10:08:21.37#ibcon#wrote, iclass 32, count 0 2006.285.10:08:21.37#ibcon#about to read 3, iclass 32, count 0 2006.285.10:08:21.39#ibcon#read 3, iclass 32, count 0 2006.285.10:08:21.39#ibcon#about to read 4, iclass 32, count 0 2006.285.10:08:21.39#ibcon#read 4, iclass 32, count 0 2006.285.10:08:21.39#ibcon#about to read 5, iclass 32, count 0 2006.285.10:08:21.39#ibcon#read 5, iclass 32, count 0 2006.285.10:08:21.39#ibcon#about to read 6, iclass 32, count 0 2006.285.10:08:21.39#ibcon#read 6, iclass 32, count 0 2006.285.10:08:21.39#ibcon#end of sib2, iclass 32, count 0 2006.285.10:08:21.39#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:08:21.39#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:08:21.39#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:08:21.39#ibcon#*before write, iclass 32, count 0 2006.285.10:08:21.39#ibcon#enter sib2, iclass 32, count 0 2006.285.10:08:21.39#ibcon#flushed, iclass 32, count 0 2006.285.10:08:21.39#ibcon#about to write, iclass 32, count 0 2006.285.10:08:21.39#ibcon#wrote, iclass 32, count 0 2006.285.10:08:21.39#ibcon#about to read 3, iclass 32, count 0 2006.285.10:08:21.43#ibcon#read 3, iclass 32, count 0 2006.285.10:08:21.43#ibcon#about to read 4, iclass 32, count 0 2006.285.10:08:21.43#ibcon#read 4, iclass 32, count 0 2006.285.10:08:21.43#ibcon#about to read 5, iclass 32, count 0 2006.285.10:08:21.43#ibcon#read 5, iclass 32, count 0 2006.285.10:08:21.43#ibcon#about to read 6, iclass 32, count 0 2006.285.10:08:21.43#ibcon#read 6, iclass 32, count 0 2006.285.10:08:21.43#ibcon#end of sib2, iclass 32, count 0 2006.285.10:08:21.43#ibcon#*after write, iclass 32, count 0 2006.285.10:08:21.43#ibcon#*before return 0, iclass 32, count 0 2006.285.10:08:21.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:08:21.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:08:21.43#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:08:21.43#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:08:21.43$vck44/va=7,4 2006.285.10:08:21.43#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.10:08:21.43#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.10:08:21.43#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:21.43#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:08:21.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:08:21.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:08:21.49#ibcon#enter wrdev, iclass 34, count 2 2006.285.10:08:21.49#ibcon#first serial, iclass 34, count 2 2006.285.10:08:21.49#ibcon#enter sib2, iclass 34, count 2 2006.285.10:08:21.49#ibcon#flushed, iclass 34, count 2 2006.285.10:08:21.49#ibcon#about to write, iclass 34, count 2 2006.285.10:08:21.49#ibcon#wrote, iclass 34, count 2 2006.285.10:08:21.49#ibcon#about to read 3, iclass 34, count 2 2006.285.10:08:21.51#ibcon#read 3, iclass 34, count 2 2006.285.10:08:21.51#ibcon#about to read 4, iclass 34, count 2 2006.285.10:08:21.51#ibcon#read 4, iclass 34, count 2 2006.285.10:08:21.51#ibcon#about to read 5, iclass 34, count 2 2006.285.10:08:21.51#ibcon#read 5, iclass 34, count 2 2006.285.10:08:21.51#ibcon#about to read 6, iclass 34, count 2 2006.285.10:08:21.51#ibcon#read 6, iclass 34, count 2 2006.285.10:08:21.51#ibcon#end of sib2, iclass 34, count 2 2006.285.10:08:21.51#ibcon#*mode == 0, iclass 34, count 2 2006.285.10:08:21.51#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.10:08:21.51#ibcon#[25=AT07-04\r\n] 2006.285.10:08:21.51#ibcon#*before write, iclass 34, count 2 2006.285.10:08:21.51#ibcon#enter sib2, iclass 34, count 2 2006.285.10:08:21.51#ibcon#flushed, iclass 34, count 2 2006.285.10:08:21.51#ibcon#about to write, iclass 34, count 2 2006.285.10:08:21.51#ibcon#wrote, iclass 34, count 2 2006.285.10:08:21.51#ibcon#about to read 3, iclass 34, count 2 2006.285.10:08:21.54#ibcon#read 3, iclass 34, count 2 2006.285.10:08:21.54#ibcon#about to read 4, iclass 34, count 2 2006.285.10:08:21.54#ibcon#read 4, iclass 34, count 2 2006.285.10:08:21.54#ibcon#about to read 5, iclass 34, count 2 2006.285.10:08:21.54#ibcon#read 5, iclass 34, count 2 2006.285.10:08:21.54#ibcon#about to read 6, iclass 34, count 2 2006.285.10:08:21.54#ibcon#read 6, iclass 34, count 2 2006.285.10:08:21.54#ibcon#end of sib2, iclass 34, count 2 2006.285.10:08:21.54#ibcon#*after write, iclass 34, count 2 2006.285.10:08:21.54#ibcon#*before return 0, iclass 34, count 2 2006.285.10:08:21.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:08:21.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:08:21.54#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.10:08:21.54#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:21.54#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:08:21.66#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:08:21.66#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:08:21.66#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:08:21.66#ibcon#first serial, iclass 34, count 0 2006.285.10:08:21.66#ibcon#enter sib2, iclass 34, count 0 2006.285.10:08:21.66#ibcon#flushed, iclass 34, count 0 2006.285.10:08:21.66#ibcon#about to write, iclass 34, count 0 2006.285.10:08:21.66#ibcon#wrote, iclass 34, count 0 2006.285.10:08:21.66#ibcon#about to read 3, iclass 34, count 0 2006.285.10:08:21.68#ibcon#read 3, iclass 34, count 0 2006.285.10:08:21.68#ibcon#about to read 4, iclass 34, count 0 2006.285.10:08:21.68#ibcon#read 4, iclass 34, count 0 2006.285.10:08:21.68#ibcon#about to read 5, iclass 34, count 0 2006.285.10:08:21.68#ibcon#read 5, iclass 34, count 0 2006.285.10:08:21.68#ibcon#about to read 6, iclass 34, count 0 2006.285.10:08:21.68#ibcon#read 6, iclass 34, count 0 2006.285.10:08:21.68#ibcon#end of sib2, iclass 34, count 0 2006.285.10:08:21.68#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:08:21.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:08:21.68#ibcon#[25=USB\r\n] 2006.285.10:08:21.68#ibcon#*before write, iclass 34, count 0 2006.285.10:08:21.68#ibcon#enter sib2, iclass 34, count 0 2006.285.10:08:21.68#ibcon#flushed, iclass 34, count 0 2006.285.10:08:21.68#ibcon#about to write, iclass 34, count 0 2006.285.10:08:21.68#ibcon#wrote, iclass 34, count 0 2006.285.10:08:21.68#ibcon#about to read 3, iclass 34, count 0 2006.285.10:08:21.71#ibcon#read 3, iclass 34, count 0 2006.285.10:08:21.71#ibcon#about to read 4, iclass 34, count 0 2006.285.10:08:21.71#ibcon#read 4, iclass 34, count 0 2006.285.10:08:21.71#ibcon#about to read 5, iclass 34, count 0 2006.285.10:08:21.71#ibcon#read 5, iclass 34, count 0 2006.285.10:08:21.71#ibcon#about to read 6, iclass 34, count 0 2006.285.10:08:21.71#ibcon#read 6, iclass 34, count 0 2006.285.10:08:21.71#ibcon#end of sib2, iclass 34, count 0 2006.285.10:08:21.71#ibcon#*after write, iclass 34, count 0 2006.285.10:08:21.71#ibcon#*before return 0, iclass 34, count 0 2006.285.10:08:21.71#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:08:21.71#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:08:21.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:08:21.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:08:21.71$vck44/valo=8,884.99 2006.285.10:08:21.71#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.10:08:21.71#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.10:08:21.71#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:21.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:08:21.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:08:21.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:08:21.71#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:08:21.71#ibcon#first serial, iclass 36, count 0 2006.285.10:08:21.71#ibcon#enter sib2, iclass 36, count 0 2006.285.10:08:21.71#ibcon#flushed, iclass 36, count 0 2006.285.10:08:21.71#ibcon#about to write, iclass 36, count 0 2006.285.10:08:21.71#ibcon#wrote, iclass 36, count 0 2006.285.10:08:21.71#ibcon#about to read 3, iclass 36, count 0 2006.285.10:08:21.73#ibcon#read 3, iclass 36, count 0 2006.285.10:08:21.73#ibcon#about to read 4, iclass 36, count 0 2006.285.10:08:21.73#ibcon#read 4, iclass 36, count 0 2006.285.10:08:21.73#ibcon#about to read 5, iclass 36, count 0 2006.285.10:08:21.73#ibcon#read 5, iclass 36, count 0 2006.285.10:08:21.73#ibcon#about to read 6, iclass 36, count 0 2006.285.10:08:21.73#ibcon#read 6, iclass 36, count 0 2006.285.10:08:21.73#ibcon#end of sib2, iclass 36, count 0 2006.285.10:08:21.73#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:08:21.73#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:08:21.73#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:08:21.73#ibcon#*before write, iclass 36, count 0 2006.285.10:08:21.73#ibcon#enter sib2, iclass 36, count 0 2006.285.10:08:21.73#ibcon#flushed, iclass 36, count 0 2006.285.10:08:21.73#ibcon#about to write, iclass 36, count 0 2006.285.10:08:21.73#ibcon#wrote, iclass 36, count 0 2006.285.10:08:21.73#ibcon#about to read 3, iclass 36, count 0 2006.285.10:08:21.77#ibcon#read 3, iclass 36, count 0 2006.285.10:08:21.77#ibcon#about to read 4, iclass 36, count 0 2006.285.10:08:21.77#ibcon#read 4, iclass 36, count 0 2006.285.10:08:21.77#ibcon#about to read 5, iclass 36, count 0 2006.285.10:08:21.77#ibcon#read 5, iclass 36, count 0 2006.285.10:08:21.77#ibcon#about to read 6, iclass 36, count 0 2006.285.10:08:21.77#ibcon#read 6, iclass 36, count 0 2006.285.10:08:21.77#ibcon#end of sib2, iclass 36, count 0 2006.285.10:08:21.77#ibcon#*after write, iclass 36, count 0 2006.285.10:08:21.77#ibcon#*before return 0, iclass 36, count 0 2006.285.10:08:21.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:08:21.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:08:21.77#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:08:21.77#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:08:21.77$vck44/va=8,3 2006.285.10:08:21.78#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.10:08:21.78#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.10:08:21.78#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:21.78#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:08:21.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:08:21.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:08:21.82#ibcon#enter wrdev, iclass 38, count 2 2006.285.10:08:21.82#ibcon#first serial, iclass 38, count 2 2006.285.10:08:21.82#ibcon#enter sib2, iclass 38, count 2 2006.285.10:08:21.82#ibcon#flushed, iclass 38, count 2 2006.285.10:08:21.82#ibcon#about to write, iclass 38, count 2 2006.285.10:08:21.82#ibcon#wrote, iclass 38, count 2 2006.285.10:08:21.82#ibcon#about to read 3, iclass 38, count 2 2006.285.10:08:21.84#ibcon#read 3, iclass 38, count 2 2006.285.10:08:21.84#ibcon#about to read 4, iclass 38, count 2 2006.285.10:08:21.84#ibcon#read 4, iclass 38, count 2 2006.285.10:08:21.84#ibcon#about to read 5, iclass 38, count 2 2006.285.10:08:21.84#ibcon#read 5, iclass 38, count 2 2006.285.10:08:21.84#ibcon#about to read 6, iclass 38, count 2 2006.285.10:08:21.84#ibcon#read 6, iclass 38, count 2 2006.285.10:08:21.84#ibcon#end of sib2, iclass 38, count 2 2006.285.10:08:21.84#ibcon#*mode == 0, iclass 38, count 2 2006.285.10:08:21.84#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.10:08:21.84#ibcon#[25=AT08-03\r\n] 2006.285.10:08:21.84#ibcon#*before write, iclass 38, count 2 2006.285.10:08:21.84#ibcon#enter sib2, iclass 38, count 2 2006.285.10:08:21.84#ibcon#flushed, iclass 38, count 2 2006.285.10:08:21.84#ibcon#about to write, iclass 38, count 2 2006.285.10:08:21.84#ibcon#wrote, iclass 38, count 2 2006.285.10:08:21.84#ibcon#about to read 3, iclass 38, count 2 2006.285.10:08:21.87#ibcon#read 3, iclass 38, count 2 2006.285.10:08:21.87#ibcon#about to read 4, iclass 38, count 2 2006.285.10:08:21.87#ibcon#read 4, iclass 38, count 2 2006.285.10:08:21.87#ibcon#about to read 5, iclass 38, count 2 2006.285.10:08:21.87#ibcon#read 5, iclass 38, count 2 2006.285.10:08:21.87#ibcon#about to read 6, iclass 38, count 2 2006.285.10:08:21.87#ibcon#read 6, iclass 38, count 2 2006.285.10:08:21.87#ibcon#end of sib2, iclass 38, count 2 2006.285.10:08:21.87#ibcon#*after write, iclass 38, count 2 2006.285.10:08:21.87#ibcon#*before return 0, iclass 38, count 2 2006.285.10:08:21.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:08:21.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:08:21.87#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.10:08:21.87#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:21.87#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:08:21.99#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:08:21.99#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:08:21.99#ibcon#enter wrdev, iclass 38, count 0 2006.285.10:08:21.99#ibcon#first serial, iclass 38, count 0 2006.285.10:08:21.99#ibcon#enter sib2, iclass 38, count 0 2006.285.10:08:21.99#ibcon#flushed, iclass 38, count 0 2006.285.10:08:21.99#ibcon#about to write, iclass 38, count 0 2006.285.10:08:21.99#ibcon#wrote, iclass 38, count 0 2006.285.10:08:21.99#ibcon#about to read 3, iclass 38, count 0 2006.285.10:08:22.01#ibcon#read 3, iclass 38, count 0 2006.285.10:08:22.01#ibcon#about to read 4, iclass 38, count 0 2006.285.10:08:22.01#ibcon#read 4, iclass 38, count 0 2006.285.10:08:22.01#ibcon#about to read 5, iclass 38, count 0 2006.285.10:08:22.01#ibcon#read 5, iclass 38, count 0 2006.285.10:08:22.01#ibcon#about to read 6, iclass 38, count 0 2006.285.10:08:22.01#ibcon#read 6, iclass 38, count 0 2006.285.10:08:22.01#ibcon#end of sib2, iclass 38, count 0 2006.285.10:08:22.01#ibcon#*mode == 0, iclass 38, count 0 2006.285.10:08:22.01#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.10:08:22.01#ibcon#[25=USB\r\n] 2006.285.10:08:22.01#ibcon#*before write, iclass 38, count 0 2006.285.10:08:22.01#ibcon#enter sib2, iclass 38, count 0 2006.285.10:08:22.01#ibcon#flushed, iclass 38, count 0 2006.285.10:08:22.01#ibcon#about to write, iclass 38, count 0 2006.285.10:08:22.01#ibcon#wrote, iclass 38, count 0 2006.285.10:08:22.01#ibcon#about to read 3, iclass 38, count 0 2006.285.10:08:22.04#ibcon#read 3, iclass 38, count 0 2006.285.10:08:22.04#ibcon#about to read 4, iclass 38, count 0 2006.285.10:08:22.04#ibcon#read 4, iclass 38, count 0 2006.285.10:08:22.04#ibcon#about to read 5, iclass 38, count 0 2006.285.10:08:22.04#ibcon#read 5, iclass 38, count 0 2006.285.10:08:22.04#ibcon#about to read 6, iclass 38, count 0 2006.285.10:08:22.04#ibcon#read 6, iclass 38, count 0 2006.285.10:08:22.04#ibcon#end of sib2, iclass 38, count 0 2006.285.10:08:22.04#ibcon#*after write, iclass 38, count 0 2006.285.10:08:22.04#ibcon#*before return 0, iclass 38, count 0 2006.285.10:08:22.04#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:08:22.04#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:08:22.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.10:08:22.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.10:08:22.04$vck44/vblo=1,629.99 2006.285.10:08:22.04#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.10:08:22.04#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.10:08:22.04#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:22.04#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:08:22.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:08:22.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:08:22.04#ibcon#enter wrdev, iclass 40, count 0 2006.285.10:08:22.04#ibcon#first serial, iclass 40, count 0 2006.285.10:08:22.04#ibcon#enter sib2, iclass 40, count 0 2006.285.10:08:22.04#ibcon#flushed, iclass 40, count 0 2006.285.10:08:22.04#ibcon#about to write, iclass 40, count 0 2006.285.10:08:22.04#ibcon#wrote, iclass 40, count 0 2006.285.10:08:22.05#ibcon#about to read 3, iclass 40, count 0 2006.285.10:08:22.06#ibcon#read 3, iclass 40, count 0 2006.285.10:08:22.06#ibcon#about to read 4, iclass 40, count 0 2006.285.10:08:22.06#ibcon#read 4, iclass 40, count 0 2006.285.10:08:22.06#ibcon#about to read 5, iclass 40, count 0 2006.285.10:08:22.06#ibcon#read 5, iclass 40, count 0 2006.285.10:08:22.06#ibcon#about to read 6, iclass 40, count 0 2006.285.10:08:22.06#ibcon#read 6, iclass 40, count 0 2006.285.10:08:22.06#ibcon#end of sib2, iclass 40, count 0 2006.285.10:08:22.06#ibcon#*mode == 0, iclass 40, count 0 2006.285.10:08:22.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.10:08:22.06#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:08:22.06#ibcon#*before write, iclass 40, count 0 2006.285.10:08:22.06#ibcon#enter sib2, iclass 40, count 0 2006.285.10:08:22.06#ibcon#flushed, iclass 40, count 0 2006.285.10:08:22.06#ibcon#about to write, iclass 40, count 0 2006.285.10:08:22.06#ibcon#wrote, iclass 40, count 0 2006.285.10:08:22.06#ibcon#about to read 3, iclass 40, count 0 2006.285.10:08:22.10#ibcon#read 3, iclass 40, count 0 2006.285.10:08:22.10#ibcon#about to read 4, iclass 40, count 0 2006.285.10:08:22.10#ibcon#read 4, iclass 40, count 0 2006.285.10:08:22.10#ibcon#about to read 5, iclass 40, count 0 2006.285.10:08:22.10#ibcon#read 5, iclass 40, count 0 2006.285.10:08:22.10#ibcon#about to read 6, iclass 40, count 0 2006.285.10:08:22.10#ibcon#read 6, iclass 40, count 0 2006.285.10:08:22.10#ibcon#end of sib2, iclass 40, count 0 2006.285.10:08:22.10#ibcon#*after write, iclass 40, count 0 2006.285.10:08:22.10#ibcon#*before return 0, iclass 40, count 0 2006.285.10:08:22.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:08:22.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:08:22.10#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.10:08:22.10#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.10:08:22.10$vck44/vb=1,4 2006.285.10:08:22.10#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.10:08:22.10#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.10:08:22.10#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:22.10#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:08:22.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:08:22.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:08:22.10#ibcon#enter wrdev, iclass 4, count 2 2006.285.10:08:22.10#ibcon#first serial, iclass 4, count 2 2006.285.10:08:22.10#ibcon#enter sib2, iclass 4, count 2 2006.285.10:08:22.10#ibcon#flushed, iclass 4, count 2 2006.285.10:08:22.10#ibcon#about to write, iclass 4, count 2 2006.285.10:08:22.11#ibcon#wrote, iclass 4, count 2 2006.285.10:08:22.11#ibcon#about to read 3, iclass 4, count 2 2006.285.10:08:22.12#ibcon#read 3, iclass 4, count 2 2006.285.10:08:22.12#ibcon#about to read 4, iclass 4, count 2 2006.285.10:08:22.12#ibcon#read 4, iclass 4, count 2 2006.285.10:08:22.12#ibcon#about to read 5, iclass 4, count 2 2006.285.10:08:22.12#ibcon#read 5, iclass 4, count 2 2006.285.10:08:22.12#ibcon#about to read 6, iclass 4, count 2 2006.285.10:08:22.12#ibcon#read 6, iclass 4, count 2 2006.285.10:08:22.12#ibcon#end of sib2, iclass 4, count 2 2006.285.10:08:22.12#ibcon#*mode == 0, iclass 4, count 2 2006.285.10:08:22.12#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.10:08:22.12#ibcon#[27=AT01-04\r\n] 2006.285.10:08:22.12#ibcon#*before write, iclass 4, count 2 2006.285.10:08:22.12#ibcon#enter sib2, iclass 4, count 2 2006.285.10:08:22.12#ibcon#flushed, iclass 4, count 2 2006.285.10:08:22.12#ibcon#about to write, iclass 4, count 2 2006.285.10:08:22.12#ibcon#wrote, iclass 4, count 2 2006.285.10:08:22.12#ibcon#about to read 3, iclass 4, count 2 2006.285.10:08:22.15#ibcon#read 3, iclass 4, count 2 2006.285.10:08:22.15#ibcon#about to read 4, iclass 4, count 2 2006.285.10:08:22.15#ibcon#read 4, iclass 4, count 2 2006.285.10:08:22.15#ibcon#about to read 5, iclass 4, count 2 2006.285.10:08:22.15#ibcon#read 5, iclass 4, count 2 2006.285.10:08:22.15#ibcon#about to read 6, iclass 4, count 2 2006.285.10:08:22.15#ibcon#read 6, iclass 4, count 2 2006.285.10:08:22.15#ibcon#end of sib2, iclass 4, count 2 2006.285.10:08:22.15#ibcon#*after write, iclass 4, count 2 2006.285.10:08:22.15#ibcon#*before return 0, iclass 4, count 2 2006.285.10:08:22.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:08:22.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:08:22.15#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.10:08:22.15#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:22.15#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:08:22.27#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:08:22.27#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:08:22.27#ibcon#enter wrdev, iclass 4, count 0 2006.285.10:08:22.27#ibcon#first serial, iclass 4, count 0 2006.285.10:08:22.27#ibcon#enter sib2, iclass 4, count 0 2006.285.10:08:22.27#ibcon#flushed, iclass 4, count 0 2006.285.10:08:22.27#ibcon#about to write, iclass 4, count 0 2006.285.10:08:22.27#ibcon#wrote, iclass 4, count 0 2006.285.10:08:22.27#ibcon#about to read 3, iclass 4, count 0 2006.285.10:08:22.29#ibcon#read 3, iclass 4, count 0 2006.285.10:08:22.29#ibcon#about to read 4, iclass 4, count 0 2006.285.10:08:22.29#ibcon#read 4, iclass 4, count 0 2006.285.10:08:22.29#ibcon#about to read 5, iclass 4, count 0 2006.285.10:08:22.29#ibcon#read 5, iclass 4, count 0 2006.285.10:08:22.29#ibcon#about to read 6, iclass 4, count 0 2006.285.10:08:22.29#ibcon#read 6, iclass 4, count 0 2006.285.10:08:22.29#ibcon#end of sib2, iclass 4, count 0 2006.285.10:08:22.29#ibcon#*mode == 0, iclass 4, count 0 2006.285.10:08:22.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.10:08:22.29#ibcon#[27=USB\r\n] 2006.285.10:08:22.29#ibcon#*before write, iclass 4, count 0 2006.285.10:08:22.29#ibcon#enter sib2, iclass 4, count 0 2006.285.10:08:22.29#ibcon#flushed, iclass 4, count 0 2006.285.10:08:22.29#ibcon#about to write, iclass 4, count 0 2006.285.10:08:22.29#ibcon#wrote, iclass 4, count 0 2006.285.10:08:22.29#ibcon#about to read 3, iclass 4, count 0 2006.285.10:08:22.32#ibcon#read 3, iclass 4, count 0 2006.285.10:08:22.32#ibcon#about to read 4, iclass 4, count 0 2006.285.10:08:22.32#ibcon#read 4, iclass 4, count 0 2006.285.10:08:22.32#ibcon#about to read 5, iclass 4, count 0 2006.285.10:08:22.32#ibcon#read 5, iclass 4, count 0 2006.285.10:08:22.32#ibcon#about to read 6, iclass 4, count 0 2006.285.10:08:22.32#ibcon#read 6, iclass 4, count 0 2006.285.10:08:22.32#ibcon#end of sib2, iclass 4, count 0 2006.285.10:08:22.32#ibcon#*after write, iclass 4, count 0 2006.285.10:08:22.32#ibcon#*before return 0, iclass 4, count 0 2006.285.10:08:22.32#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:08:22.32#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:08:22.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.10:08:22.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.10:08:22.32$vck44/vblo=2,634.99 2006.285.10:08:22.32#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.10:08:22.32#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.10:08:22.32#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:22.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:08:22.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:08:22.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:08:22.32#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:08:22.32#ibcon#first serial, iclass 6, count 0 2006.285.10:08:22.32#ibcon#enter sib2, iclass 6, count 0 2006.285.10:08:22.32#ibcon#flushed, iclass 6, count 0 2006.285.10:08:22.32#ibcon#about to write, iclass 6, count 0 2006.285.10:08:22.32#ibcon#wrote, iclass 6, count 0 2006.285.10:08:22.32#ibcon#about to read 3, iclass 6, count 0 2006.285.10:08:22.34#ibcon#read 3, iclass 6, count 0 2006.285.10:08:22.34#ibcon#about to read 4, iclass 6, count 0 2006.285.10:08:22.34#ibcon#read 4, iclass 6, count 0 2006.285.10:08:22.34#ibcon#about to read 5, iclass 6, count 0 2006.285.10:08:22.34#ibcon#read 5, iclass 6, count 0 2006.285.10:08:22.34#ibcon#about to read 6, iclass 6, count 0 2006.285.10:08:22.34#ibcon#read 6, iclass 6, count 0 2006.285.10:08:22.34#ibcon#end of sib2, iclass 6, count 0 2006.285.10:08:22.34#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:08:22.34#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:08:22.34#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:08:22.34#ibcon#*before write, iclass 6, count 0 2006.285.10:08:22.34#ibcon#enter sib2, iclass 6, count 0 2006.285.10:08:22.34#ibcon#flushed, iclass 6, count 0 2006.285.10:08:22.34#ibcon#about to write, iclass 6, count 0 2006.285.10:08:22.34#ibcon#wrote, iclass 6, count 0 2006.285.10:08:22.34#ibcon#about to read 3, iclass 6, count 0 2006.285.10:08:22.38#ibcon#read 3, iclass 6, count 0 2006.285.10:08:22.38#ibcon#about to read 4, iclass 6, count 0 2006.285.10:08:22.38#ibcon#read 4, iclass 6, count 0 2006.285.10:08:22.38#ibcon#about to read 5, iclass 6, count 0 2006.285.10:08:22.38#ibcon#read 5, iclass 6, count 0 2006.285.10:08:22.38#ibcon#about to read 6, iclass 6, count 0 2006.285.10:08:22.38#ibcon#read 6, iclass 6, count 0 2006.285.10:08:22.38#ibcon#end of sib2, iclass 6, count 0 2006.285.10:08:22.38#ibcon#*after write, iclass 6, count 0 2006.285.10:08:22.38#ibcon#*before return 0, iclass 6, count 0 2006.285.10:08:22.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:08:22.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:08:22.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:08:22.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:08:22.38$vck44/vb=2,5 2006.285.10:08:22.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.10:08:22.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.10:08:22.38#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:22.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:08:22.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:08:22.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:08:22.44#ibcon#enter wrdev, iclass 10, count 2 2006.285.10:08:22.44#ibcon#first serial, iclass 10, count 2 2006.285.10:08:22.44#ibcon#enter sib2, iclass 10, count 2 2006.285.10:08:22.44#ibcon#flushed, iclass 10, count 2 2006.285.10:08:22.44#ibcon#about to write, iclass 10, count 2 2006.285.10:08:22.44#ibcon#wrote, iclass 10, count 2 2006.285.10:08:22.44#ibcon#about to read 3, iclass 10, count 2 2006.285.10:08:22.46#ibcon#read 3, iclass 10, count 2 2006.285.10:08:22.46#ibcon#about to read 4, iclass 10, count 2 2006.285.10:08:22.46#ibcon#read 4, iclass 10, count 2 2006.285.10:08:22.46#ibcon#about to read 5, iclass 10, count 2 2006.285.10:08:22.46#ibcon#read 5, iclass 10, count 2 2006.285.10:08:22.46#ibcon#about to read 6, iclass 10, count 2 2006.285.10:08:22.46#ibcon#read 6, iclass 10, count 2 2006.285.10:08:22.46#ibcon#end of sib2, iclass 10, count 2 2006.285.10:08:22.46#ibcon#*mode == 0, iclass 10, count 2 2006.285.10:08:22.46#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.10:08:22.46#ibcon#[27=AT02-05\r\n] 2006.285.10:08:22.46#ibcon#*before write, iclass 10, count 2 2006.285.10:08:22.46#ibcon#enter sib2, iclass 10, count 2 2006.285.10:08:22.46#ibcon#flushed, iclass 10, count 2 2006.285.10:08:22.46#ibcon#about to write, iclass 10, count 2 2006.285.10:08:22.46#ibcon#wrote, iclass 10, count 2 2006.285.10:08:22.46#ibcon#about to read 3, iclass 10, count 2 2006.285.10:08:22.49#ibcon#read 3, iclass 10, count 2 2006.285.10:08:22.49#ibcon#about to read 4, iclass 10, count 2 2006.285.10:08:22.49#ibcon#read 4, iclass 10, count 2 2006.285.10:08:22.49#ibcon#about to read 5, iclass 10, count 2 2006.285.10:08:22.49#ibcon#read 5, iclass 10, count 2 2006.285.10:08:22.49#ibcon#about to read 6, iclass 10, count 2 2006.285.10:08:22.49#ibcon#read 6, iclass 10, count 2 2006.285.10:08:22.49#ibcon#end of sib2, iclass 10, count 2 2006.285.10:08:22.49#ibcon#*after write, iclass 10, count 2 2006.285.10:08:22.49#ibcon#*before return 0, iclass 10, count 2 2006.285.10:08:22.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:08:22.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:08:22.49#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.10:08:22.49#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:22.49#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:08:22.61#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:08:22.61#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:08:22.61#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:08:22.61#ibcon#first serial, iclass 10, count 0 2006.285.10:08:22.61#ibcon#enter sib2, iclass 10, count 0 2006.285.10:08:22.61#ibcon#flushed, iclass 10, count 0 2006.285.10:08:22.61#ibcon#about to write, iclass 10, count 0 2006.285.10:08:22.61#ibcon#wrote, iclass 10, count 0 2006.285.10:08:22.61#ibcon#about to read 3, iclass 10, count 0 2006.285.10:08:22.63#ibcon#read 3, iclass 10, count 0 2006.285.10:08:22.63#ibcon#about to read 4, iclass 10, count 0 2006.285.10:08:22.63#ibcon#read 4, iclass 10, count 0 2006.285.10:08:22.63#ibcon#about to read 5, iclass 10, count 0 2006.285.10:08:22.63#ibcon#read 5, iclass 10, count 0 2006.285.10:08:22.63#ibcon#about to read 6, iclass 10, count 0 2006.285.10:08:22.63#ibcon#read 6, iclass 10, count 0 2006.285.10:08:22.63#ibcon#end of sib2, iclass 10, count 0 2006.285.10:08:22.63#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:08:22.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:08:22.63#ibcon#[27=USB\r\n] 2006.285.10:08:22.63#ibcon#*before write, iclass 10, count 0 2006.285.10:08:22.63#ibcon#enter sib2, iclass 10, count 0 2006.285.10:08:22.63#ibcon#flushed, iclass 10, count 0 2006.285.10:08:22.63#ibcon#about to write, iclass 10, count 0 2006.285.10:08:22.63#ibcon#wrote, iclass 10, count 0 2006.285.10:08:22.63#ibcon#about to read 3, iclass 10, count 0 2006.285.10:08:22.66#ibcon#read 3, iclass 10, count 0 2006.285.10:08:22.66#ibcon#about to read 4, iclass 10, count 0 2006.285.10:08:22.66#ibcon#read 4, iclass 10, count 0 2006.285.10:08:22.66#ibcon#about to read 5, iclass 10, count 0 2006.285.10:08:22.66#ibcon#read 5, iclass 10, count 0 2006.285.10:08:22.66#ibcon#about to read 6, iclass 10, count 0 2006.285.10:08:22.66#ibcon#read 6, iclass 10, count 0 2006.285.10:08:22.66#ibcon#end of sib2, iclass 10, count 0 2006.285.10:08:22.66#ibcon#*after write, iclass 10, count 0 2006.285.10:08:22.66#ibcon#*before return 0, iclass 10, count 0 2006.285.10:08:22.66#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:08:22.66#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:08:22.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:08:22.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:08:22.66$vck44/vblo=3,649.99 2006.285.10:08:22.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.10:08:22.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.10:08:22.66#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:22.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:08:22.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:08:22.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:08:22.66#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:08:22.66#ibcon#first serial, iclass 12, count 0 2006.285.10:08:22.66#ibcon#enter sib2, iclass 12, count 0 2006.285.10:08:22.66#ibcon#flushed, iclass 12, count 0 2006.285.10:08:22.66#ibcon#about to write, iclass 12, count 0 2006.285.10:08:22.66#ibcon#wrote, iclass 12, count 0 2006.285.10:08:22.66#ibcon#about to read 3, iclass 12, count 0 2006.285.10:08:22.68#ibcon#read 3, iclass 12, count 0 2006.285.10:08:22.68#ibcon#about to read 4, iclass 12, count 0 2006.285.10:08:22.68#ibcon#read 4, iclass 12, count 0 2006.285.10:08:22.68#ibcon#about to read 5, iclass 12, count 0 2006.285.10:08:22.68#ibcon#read 5, iclass 12, count 0 2006.285.10:08:22.68#ibcon#about to read 6, iclass 12, count 0 2006.285.10:08:22.68#ibcon#read 6, iclass 12, count 0 2006.285.10:08:22.68#ibcon#end of sib2, iclass 12, count 0 2006.285.10:08:22.68#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:08:22.68#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:08:22.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:08:22.68#ibcon#*before write, iclass 12, count 0 2006.285.10:08:22.68#ibcon#enter sib2, iclass 12, count 0 2006.285.10:08:22.68#ibcon#flushed, iclass 12, count 0 2006.285.10:08:22.68#ibcon#about to write, iclass 12, count 0 2006.285.10:08:22.68#ibcon#wrote, iclass 12, count 0 2006.285.10:08:22.68#ibcon#about to read 3, iclass 12, count 0 2006.285.10:08:22.72#ibcon#read 3, iclass 12, count 0 2006.285.10:08:22.72#ibcon#about to read 4, iclass 12, count 0 2006.285.10:08:22.72#ibcon#read 4, iclass 12, count 0 2006.285.10:08:22.72#ibcon#about to read 5, iclass 12, count 0 2006.285.10:08:22.72#ibcon#read 5, iclass 12, count 0 2006.285.10:08:22.72#ibcon#about to read 6, iclass 12, count 0 2006.285.10:08:22.72#ibcon#read 6, iclass 12, count 0 2006.285.10:08:22.72#ibcon#end of sib2, iclass 12, count 0 2006.285.10:08:22.72#ibcon#*after write, iclass 12, count 0 2006.285.10:08:22.72#ibcon#*before return 0, iclass 12, count 0 2006.285.10:08:22.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:08:22.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:08:22.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:08:22.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:08:22.72$vck44/vb=3,4 2006.285.10:08:22.72#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.10:08:22.72#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.10:08:22.72#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:22.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:08:22.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:08:22.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:08:22.78#ibcon#enter wrdev, iclass 14, count 2 2006.285.10:08:22.78#ibcon#first serial, iclass 14, count 2 2006.285.10:08:22.78#ibcon#enter sib2, iclass 14, count 2 2006.285.10:08:22.78#ibcon#flushed, iclass 14, count 2 2006.285.10:08:22.78#ibcon#about to write, iclass 14, count 2 2006.285.10:08:22.78#ibcon#wrote, iclass 14, count 2 2006.285.10:08:22.78#ibcon#about to read 3, iclass 14, count 2 2006.285.10:08:22.80#ibcon#read 3, iclass 14, count 2 2006.285.10:08:22.80#ibcon#about to read 4, iclass 14, count 2 2006.285.10:08:22.80#ibcon#read 4, iclass 14, count 2 2006.285.10:08:22.80#ibcon#about to read 5, iclass 14, count 2 2006.285.10:08:22.80#ibcon#read 5, iclass 14, count 2 2006.285.10:08:22.80#ibcon#about to read 6, iclass 14, count 2 2006.285.10:08:22.80#ibcon#read 6, iclass 14, count 2 2006.285.10:08:22.80#ibcon#end of sib2, iclass 14, count 2 2006.285.10:08:22.80#ibcon#*mode == 0, iclass 14, count 2 2006.285.10:08:22.80#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.10:08:22.80#ibcon#[27=AT03-04\r\n] 2006.285.10:08:22.80#ibcon#*before write, iclass 14, count 2 2006.285.10:08:22.80#ibcon#enter sib2, iclass 14, count 2 2006.285.10:08:22.80#ibcon#flushed, iclass 14, count 2 2006.285.10:08:22.80#ibcon#about to write, iclass 14, count 2 2006.285.10:08:22.80#ibcon#wrote, iclass 14, count 2 2006.285.10:08:22.80#ibcon#about to read 3, iclass 14, count 2 2006.285.10:08:22.83#ibcon#read 3, iclass 14, count 2 2006.285.10:08:22.83#ibcon#about to read 4, iclass 14, count 2 2006.285.10:08:22.83#ibcon#read 4, iclass 14, count 2 2006.285.10:08:22.83#ibcon#about to read 5, iclass 14, count 2 2006.285.10:08:22.83#ibcon#read 5, iclass 14, count 2 2006.285.10:08:22.83#ibcon#about to read 6, iclass 14, count 2 2006.285.10:08:22.83#ibcon#read 6, iclass 14, count 2 2006.285.10:08:22.83#ibcon#end of sib2, iclass 14, count 2 2006.285.10:08:22.83#ibcon#*after write, iclass 14, count 2 2006.285.10:08:22.83#ibcon#*before return 0, iclass 14, count 2 2006.285.10:08:22.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:08:22.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:08:22.83#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.10:08:22.83#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:22.83#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:08:22.95#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:08:22.95#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:08:22.95#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:08:22.95#ibcon#first serial, iclass 14, count 0 2006.285.10:08:22.95#ibcon#enter sib2, iclass 14, count 0 2006.285.10:08:22.95#ibcon#flushed, iclass 14, count 0 2006.285.10:08:22.95#ibcon#about to write, iclass 14, count 0 2006.285.10:08:22.95#ibcon#wrote, iclass 14, count 0 2006.285.10:08:22.95#ibcon#about to read 3, iclass 14, count 0 2006.285.10:08:22.97#ibcon#read 3, iclass 14, count 0 2006.285.10:08:22.97#ibcon#about to read 4, iclass 14, count 0 2006.285.10:08:22.97#ibcon#read 4, iclass 14, count 0 2006.285.10:08:22.97#ibcon#about to read 5, iclass 14, count 0 2006.285.10:08:22.97#ibcon#read 5, iclass 14, count 0 2006.285.10:08:22.97#ibcon#about to read 6, iclass 14, count 0 2006.285.10:08:22.97#ibcon#read 6, iclass 14, count 0 2006.285.10:08:22.97#ibcon#end of sib2, iclass 14, count 0 2006.285.10:08:22.97#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:08:22.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:08:22.97#ibcon#[27=USB\r\n] 2006.285.10:08:22.97#ibcon#*before write, iclass 14, count 0 2006.285.10:08:22.97#ibcon#enter sib2, iclass 14, count 0 2006.285.10:08:22.97#ibcon#flushed, iclass 14, count 0 2006.285.10:08:22.97#ibcon#about to write, iclass 14, count 0 2006.285.10:08:22.97#ibcon#wrote, iclass 14, count 0 2006.285.10:08:22.97#ibcon#about to read 3, iclass 14, count 0 2006.285.10:08:23.00#ibcon#read 3, iclass 14, count 0 2006.285.10:08:23.00#ibcon#about to read 4, iclass 14, count 0 2006.285.10:08:23.00#ibcon#read 4, iclass 14, count 0 2006.285.10:08:23.00#ibcon#about to read 5, iclass 14, count 0 2006.285.10:08:23.00#ibcon#read 5, iclass 14, count 0 2006.285.10:08:23.00#ibcon#about to read 6, iclass 14, count 0 2006.285.10:08:23.00#ibcon#read 6, iclass 14, count 0 2006.285.10:08:23.00#ibcon#end of sib2, iclass 14, count 0 2006.285.10:08:23.00#ibcon#*after write, iclass 14, count 0 2006.285.10:08:23.00#ibcon#*before return 0, iclass 14, count 0 2006.285.10:08:23.00#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:08:23.00#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:08:23.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:08:23.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:08:23.00$vck44/vblo=4,679.99 2006.285.10:08:23.00#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.10:08:23.00#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.10:08:23.00#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:23.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:08:23.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:08:23.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:08:23.00#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:08:23.00#ibcon#first serial, iclass 16, count 0 2006.285.10:08:23.01#ibcon#enter sib2, iclass 16, count 0 2006.285.10:08:23.01#ibcon#flushed, iclass 16, count 0 2006.285.10:08:23.01#ibcon#about to write, iclass 16, count 0 2006.285.10:08:23.01#ibcon#wrote, iclass 16, count 0 2006.285.10:08:23.01#ibcon#about to read 3, iclass 16, count 0 2006.285.10:08:23.02#ibcon#read 3, iclass 16, count 0 2006.285.10:08:23.02#ibcon#about to read 4, iclass 16, count 0 2006.285.10:08:23.02#ibcon#read 4, iclass 16, count 0 2006.285.10:08:23.02#ibcon#about to read 5, iclass 16, count 0 2006.285.10:08:23.02#ibcon#read 5, iclass 16, count 0 2006.285.10:08:23.02#ibcon#about to read 6, iclass 16, count 0 2006.285.10:08:23.02#ibcon#read 6, iclass 16, count 0 2006.285.10:08:23.02#ibcon#end of sib2, iclass 16, count 0 2006.285.10:08:23.02#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:08:23.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:08:23.02#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:08:23.02#ibcon#*before write, iclass 16, count 0 2006.285.10:08:23.02#ibcon#enter sib2, iclass 16, count 0 2006.285.10:08:23.02#ibcon#flushed, iclass 16, count 0 2006.285.10:08:23.02#ibcon#about to write, iclass 16, count 0 2006.285.10:08:23.02#ibcon#wrote, iclass 16, count 0 2006.285.10:08:23.02#ibcon#about to read 3, iclass 16, count 0 2006.285.10:08:23.06#ibcon#read 3, iclass 16, count 0 2006.285.10:08:23.06#ibcon#about to read 4, iclass 16, count 0 2006.285.10:08:23.06#ibcon#read 4, iclass 16, count 0 2006.285.10:08:23.06#ibcon#about to read 5, iclass 16, count 0 2006.285.10:08:23.06#ibcon#read 5, iclass 16, count 0 2006.285.10:08:23.06#ibcon#about to read 6, iclass 16, count 0 2006.285.10:08:23.06#ibcon#read 6, iclass 16, count 0 2006.285.10:08:23.06#ibcon#end of sib2, iclass 16, count 0 2006.285.10:08:23.06#ibcon#*after write, iclass 16, count 0 2006.285.10:08:23.06#ibcon#*before return 0, iclass 16, count 0 2006.285.10:08:23.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:08:23.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:08:23.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:08:23.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:08:23.06$vck44/vb=4,5 2006.285.10:08:23.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.10:08:23.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.10:08:23.06#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:23.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:08:23.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:08:23.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:08:23.12#ibcon#enter wrdev, iclass 18, count 2 2006.285.10:08:23.12#ibcon#first serial, iclass 18, count 2 2006.285.10:08:23.12#ibcon#enter sib2, iclass 18, count 2 2006.285.10:08:23.12#ibcon#flushed, iclass 18, count 2 2006.285.10:08:23.12#ibcon#about to write, iclass 18, count 2 2006.285.10:08:23.12#ibcon#wrote, iclass 18, count 2 2006.285.10:08:23.12#ibcon#about to read 3, iclass 18, count 2 2006.285.10:08:23.14#ibcon#read 3, iclass 18, count 2 2006.285.10:08:23.14#ibcon#about to read 4, iclass 18, count 2 2006.285.10:08:23.14#ibcon#read 4, iclass 18, count 2 2006.285.10:08:23.14#ibcon#about to read 5, iclass 18, count 2 2006.285.10:08:23.14#ibcon#read 5, iclass 18, count 2 2006.285.10:08:23.14#ibcon#about to read 6, iclass 18, count 2 2006.285.10:08:23.14#ibcon#read 6, iclass 18, count 2 2006.285.10:08:23.14#ibcon#end of sib2, iclass 18, count 2 2006.285.10:08:23.14#ibcon#*mode == 0, iclass 18, count 2 2006.285.10:08:23.14#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.10:08:23.14#ibcon#[27=AT04-05\r\n] 2006.285.10:08:23.14#ibcon#*before write, iclass 18, count 2 2006.285.10:08:23.14#ibcon#enter sib2, iclass 18, count 2 2006.285.10:08:23.14#ibcon#flushed, iclass 18, count 2 2006.285.10:08:23.14#ibcon#about to write, iclass 18, count 2 2006.285.10:08:23.14#ibcon#wrote, iclass 18, count 2 2006.285.10:08:23.14#ibcon#about to read 3, iclass 18, count 2 2006.285.10:08:23.17#ibcon#read 3, iclass 18, count 2 2006.285.10:08:23.17#ibcon#about to read 4, iclass 18, count 2 2006.285.10:08:23.17#ibcon#read 4, iclass 18, count 2 2006.285.10:08:23.17#ibcon#about to read 5, iclass 18, count 2 2006.285.10:08:23.17#ibcon#read 5, iclass 18, count 2 2006.285.10:08:23.17#ibcon#about to read 6, iclass 18, count 2 2006.285.10:08:23.17#ibcon#read 6, iclass 18, count 2 2006.285.10:08:23.17#ibcon#end of sib2, iclass 18, count 2 2006.285.10:08:23.17#ibcon#*after write, iclass 18, count 2 2006.285.10:08:23.17#ibcon#*before return 0, iclass 18, count 2 2006.285.10:08:23.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:08:23.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:08:23.17#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.10:08:23.17#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:23.17#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:08:23.29#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:08:23.29#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:08:23.29#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:08:23.29#ibcon#first serial, iclass 18, count 0 2006.285.10:08:23.29#ibcon#enter sib2, iclass 18, count 0 2006.285.10:08:23.29#ibcon#flushed, iclass 18, count 0 2006.285.10:08:23.29#ibcon#about to write, iclass 18, count 0 2006.285.10:08:23.29#ibcon#wrote, iclass 18, count 0 2006.285.10:08:23.29#ibcon#about to read 3, iclass 18, count 0 2006.285.10:08:23.31#ibcon#read 3, iclass 18, count 0 2006.285.10:08:23.31#ibcon#about to read 4, iclass 18, count 0 2006.285.10:08:23.31#ibcon#read 4, iclass 18, count 0 2006.285.10:08:23.31#ibcon#about to read 5, iclass 18, count 0 2006.285.10:08:23.31#ibcon#read 5, iclass 18, count 0 2006.285.10:08:23.31#ibcon#about to read 6, iclass 18, count 0 2006.285.10:08:23.31#ibcon#read 6, iclass 18, count 0 2006.285.10:08:23.31#ibcon#end of sib2, iclass 18, count 0 2006.285.10:08:23.31#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:08:23.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:08:23.31#ibcon#[27=USB\r\n] 2006.285.10:08:23.31#ibcon#*before write, iclass 18, count 0 2006.285.10:08:23.31#ibcon#enter sib2, iclass 18, count 0 2006.285.10:08:23.31#ibcon#flushed, iclass 18, count 0 2006.285.10:08:23.31#ibcon#about to write, iclass 18, count 0 2006.285.10:08:23.31#ibcon#wrote, iclass 18, count 0 2006.285.10:08:23.31#ibcon#about to read 3, iclass 18, count 0 2006.285.10:08:23.34#ibcon#read 3, iclass 18, count 0 2006.285.10:08:23.34#ibcon#about to read 4, iclass 18, count 0 2006.285.10:08:23.34#ibcon#read 4, iclass 18, count 0 2006.285.10:08:23.34#ibcon#about to read 5, iclass 18, count 0 2006.285.10:08:23.34#ibcon#read 5, iclass 18, count 0 2006.285.10:08:23.34#ibcon#about to read 6, iclass 18, count 0 2006.285.10:08:23.34#ibcon#read 6, iclass 18, count 0 2006.285.10:08:23.34#ibcon#end of sib2, iclass 18, count 0 2006.285.10:08:23.34#ibcon#*after write, iclass 18, count 0 2006.285.10:08:23.34#ibcon#*before return 0, iclass 18, count 0 2006.285.10:08:23.34#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:08:23.34#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:08:23.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:08:23.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:08:23.34$vck44/vblo=5,709.99 2006.285.10:08:23.34#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.10:08:23.34#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.10:08:23.34#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:23.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:08:23.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:08:23.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:08:23.34#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:08:23.34#ibcon#first serial, iclass 20, count 0 2006.285.10:08:23.34#ibcon#enter sib2, iclass 20, count 0 2006.285.10:08:23.34#ibcon#flushed, iclass 20, count 0 2006.285.10:08:23.34#ibcon#about to write, iclass 20, count 0 2006.285.10:08:23.34#ibcon#wrote, iclass 20, count 0 2006.285.10:08:23.34#ibcon#about to read 3, iclass 20, count 0 2006.285.10:08:23.36#ibcon#read 3, iclass 20, count 0 2006.285.10:08:23.36#ibcon#about to read 4, iclass 20, count 0 2006.285.10:08:23.36#ibcon#read 4, iclass 20, count 0 2006.285.10:08:23.36#ibcon#about to read 5, iclass 20, count 0 2006.285.10:08:23.36#ibcon#read 5, iclass 20, count 0 2006.285.10:08:23.36#ibcon#about to read 6, iclass 20, count 0 2006.285.10:08:23.36#ibcon#read 6, iclass 20, count 0 2006.285.10:08:23.36#ibcon#end of sib2, iclass 20, count 0 2006.285.10:08:23.36#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:08:23.36#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:08:23.36#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:08:23.36#ibcon#*before write, iclass 20, count 0 2006.285.10:08:23.36#ibcon#enter sib2, iclass 20, count 0 2006.285.10:08:23.36#ibcon#flushed, iclass 20, count 0 2006.285.10:08:23.36#ibcon#about to write, iclass 20, count 0 2006.285.10:08:23.36#ibcon#wrote, iclass 20, count 0 2006.285.10:08:23.36#ibcon#about to read 3, iclass 20, count 0 2006.285.10:08:23.40#ibcon#read 3, iclass 20, count 0 2006.285.10:08:23.40#ibcon#about to read 4, iclass 20, count 0 2006.285.10:08:23.40#ibcon#read 4, iclass 20, count 0 2006.285.10:08:23.40#ibcon#about to read 5, iclass 20, count 0 2006.285.10:08:23.40#ibcon#read 5, iclass 20, count 0 2006.285.10:08:23.40#ibcon#about to read 6, iclass 20, count 0 2006.285.10:08:23.40#ibcon#read 6, iclass 20, count 0 2006.285.10:08:23.40#ibcon#end of sib2, iclass 20, count 0 2006.285.10:08:23.40#ibcon#*after write, iclass 20, count 0 2006.285.10:08:23.40#ibcon#*before return 0, iclass 20, count 0 2006.285.10:08:23.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:08:23.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:08:23.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:08:23.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:08:23.40$vck44/vb=5,4 2006.285.10:08:23.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.10:08:23.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.10:08:23.40#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:23.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:08:23.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:08:23.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:08:23.46#ibcon#enter wrdev, iclass 22, count 2 2006.285.10:08:23.46#ibcon#first serial, iclass 22, count 2 2006.285.10:08:23.46#ibcon#enter sib2, iclass 22, count 2 2006.285.10:08:23.46#ibcon#flushed, iclass 22, count 2 2006.285.10:08:23.46#ibcon#about to write, iclass 22, count 2 2006.285.10:08:23.46#ibcon#wrote, iclass 22, count 2 2006.285.10:08:23.46#ibcon#about to read 3, iclass 22, count 2 2006.285.10:08:23.48#ibcon#read 3, iclass 22, count 2 2006.285.10:08:23.48#ibcon#about to read 4, iclass 22, count 2 2006.285.10:08:23.48#ibcon#read 4, iclass 22, count 2 2006.285.10:08:23.48#ibcon#about to read 5, iclass 22, count 2 2006.285.10:08:23.48#ibcon#read 5, iclass 22, count 2 2006.285.10:08:23.48#ibcon#about to read 6, iclass 22, count 2 2006.285.10:08:23.48#ibcon#read 6, iclass 22, count 2 2006.285.10:08:23.48#ibcon#end of sib2, iclass 22, count 2 2006.285.10:08:23.48#ibcon#*mode == 0, iclass 22, count 2 2006.285.10:08:23.48#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.10:08:23.48#ibcon#[27=AT05-04\r\n] 2006.285.10:08:23.48#ibcon#*before write, iclass 22, count 2 2006.285.10:08:23.48#ibcon#enter sib2, iclass 22, count 2 2006.285.10:08:23.48#ibcon#flushed, iclass 22, count 2 2006.285.10:08:23.48#ibcon#about to write, iclass 22, count 2 2006.285.10:08:23.48#ibcon#wrote, iclass 22, count 2 2006.285.10:08:23.48#ibcon#about to read 3, iclass 22, count 2 2006.285.10:08:23.51#ibcon#read 3, iclass 22, count 2 2006.285.10:08:23.51#ibcon#about to read 4, iclass 22, count 2 2006.285.10:08:23.51#ibcon#read 4, iclass 22, count 2 2006.285.10:08:23.51#ibcon#about to read 5, iclass 22, count 2 2006.285.10:08:23.51#ibcon#read 5, iclass 22, count 2 2006.285.10:08:23.51#ibcon#about to read 6, iclass 22, count 2 2006.285.10:08:23.51#ibcon#read 6, iclass 22, count 2 2006.285.10:08:23.51#ibcon#end of sib2, iclass 22, count 2 2006.285.10:08:23.51#ibcon#*after write, iclass 22, count 2 2006.285.10:08:23.51#ibcon#*before return 0, iclass 22, count 2 2006.285.10:08:23.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:08:23.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:08:23.51#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.10:08:23.51#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:23.51#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:08:23.63#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:08:23.63#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:08:23.63#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:08:23.63#ibcon#first serial, iclass 22, count 0 2006.285.10:08:23.63#ibcon#enter sib2, iclass 22, count 0 2006.285.10:08:23.63#ibcon#flushed, iclass 22, count 0 2006.285.10:08:23.63#ibcon#about to write, iclass 22, count 0 2006.285.10:08:23.63#ibcon#wrote, iclass 22, count 0 2006.285.10:08:23.63#ibcon#about to read 3, iclass 22, count 0 2006.285.10:08:23.65#ibcon#read 3, iclass 22, count 0 2006.285.10:08:23.65#ibcon#about to read 4, iclass 22, count 0 2006.285.10:08:23.65#ibcon#read 4, iclass 22, count 0 2006.285.10:08:23.65#ibcon#about to read 5, iclass 22, count 0 2006.285.10:08:23.65#ibcon#read 5, iclass 22, count 0 2006.285.10:08:23.65#ibcon#about to read 6, iclass 22, count 0 2006.285.10:08:23.65#ibcon#read 6, iclass 22, count 0 2006.285.10:08:23.65#ibcon#end of sib2, iclass 22, count 0 2006.285.10:08:23.65#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:08:23.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:08:23.65#ibcon#[27=USB\r\n] 2006.285.10:08:23.65#ibcon#*before write, iclass 22, count 0 2006.285.10:08:23.65#ibcon#enter sib2, iclass 22, count 0 2006.285.10:08:23.65#ibcon#flushed, iclass 22, count 0 2006.285.10:08:23.65#ibcon#about to write, iclass 22, count 0 2006.285.10:08:23.65#ibcon#wrote, iclass 22, count 0 2006.285.10:08:23.65#ibcon#about to read 3, iclass 22, count 0 2006.285.10:08:23.68#ibcon#read 3, iclass 22, count 0 2006.285.10:08:23.68#ibcon#about to read 4, iclass 22, count 0 2006.285.10:08:23.68#ibcon#read 4, iclass 22, count 0 2006.285.10:08:23.68#ibcon#about to read 5, iclass 22, count 0 2006.285.10:08:23.68#ibcon#read 5, iclass 22, count 0 2006.285.10:08:23.68#ibcon#about to read 6, iclass 22, count 0 2006.285.10:08:23.68#ibcon#read 6, iclass 22, count 0 2006.285.10:08:23.68#ibcon#end of sib2, iclass 22, count 0 2006.285.10:08:23.68#ibcon#*after write, iclass 22, count 0 2006.285.10:08:23.68#ibcon#*before return 0, iclass 22, count 0 2006.285.10:08:23.68#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:08:23.68#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:08:23.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:08:23.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:08:23.68$vck44/vblo=6,719.99 2006.285.10:08:23.68#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.10:08:23.68#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.10:08:23.68#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:23.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:08:23.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:08:23.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:08:23.68#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:08:23.68#ibcon#first serial, iclass 24, count 0 2006.285.10:08:23.68#ibcon#enter sib2, iclass 24, count 0 2006.285.10:08:23.68#ibcon#flushed, iclass 24, count 0 2006.285.10:08:23.68#ibcon#about to write, iclass 24, count 0 2006.285.10:08:23.68#ibcon#wrote, iclass 24, count 0 2006.285.10:08:23.68#ibcon#about to read 3, iclass 24, count 0 2006.285.10:08:23.70#ibcon#read 3, iclass 24, count 0 2006.285.10:08:23.70#ibcon#about to read 4, iclass 24, count 0 2006.285.10:08:23.70#ibcon#read 4, iclass 24, count 0 2006.285.10:08:23.70#ibcon#about to read 5, iclass 24, count 0 2006.285.10:08:23.70#ibcon#read 5, iclass 24, count 0 2006.285.10:08:23.70#ibcon#about to read 6, iclass 24, count 0 2006.285.10:08:23.70#ibcon#read 6, iclass 24, count 0 2006.285.10:08:23.70#ibcon#end of sib2, iclass 24, count 0 2006.285.10:08:23.70#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:08:23.70#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:08:23.70#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:08:23.70#ibcon#*before write, iclass 24, count 0 2006.285.10:08:23.70#ibcon#enter sib2, iclass 24, count 0 2006.285.10:08:23.70#ibcon#flushed, iclass 24, count 0 2006.285.10:08:23.70#ibcon#about to write, iclass 24, count 0 2006.285.10:08:23.70#ibcon#wrote, iclass 24, count 0 2006.285.10:08:23.70#ibcon#about to read 3, iclass 24, count 0 2006.285.10:08:23.74#ibcon#read 3, iclass 24, count 0 2006.285.10:08:23.74#ibcon#about to read 4, iclass 24, count 0 2006.285.10:08:23.74#ibcon#read 4, iclass 24, count 0 2006.285.10:08:23.74#ibcon#about to read 5, iclass 24, count 0 2006.285.10:08:23.74#ibcon#read 5, iclass 24, count 0 2006.285.10:08:23.74#ibcon#about to read 6, iclass 24, count 0 2006.285.10:08:23.74#ibcon#read 6, iclass 24, count 0 2006.285.10:08:23.74#ibcon#end of sib2, iclass 24, count 0 2006.285.10:08:23.74#ibcon#*after write, iclass 24, count 0 2006.285.10:08:23.74#ibcon#*before return 0, iclass 24, count 0 2006.285.10:08:23.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:08:23.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:08:23.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:08:23.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:08:23.74$vck44/vb=6,3 2006.285.10:08:23.74#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.10:08:23.74#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.10:08:23.74#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:23.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:08:23.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:08:23.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:08:23.80#ibcon#enter wrdev, iclass 26, count 2 2006.285.10:08:23.80#ibcon#first serial, iclass 26, count 2 2006.285.10:08:23.80#ibcon#enter sib2, iclass 26, count 2 2006.285.10:08:23.80#ibcon#flushed, iclass 26, count 2 2006.285.10:08:23.80#ibcon#about to write, iclass 26, count 2 2006.285.10:08:23.80#ibcon#wrote, iclass 26, count 2 2006.285.10:08:23.80#ibcon#about to read 3, iclass 26, count 2 2006.285.10:08:23.82#ibcon#read 3, iclass 26, count 2 2006.285.10:08:23.82#ibcon#about to read 4, iclass 26, count 2 2006.285.10:08:23.82#ibcon#read 4, iclass 26, count 2 2006.285.10:08:23.82#ibcon#about to read 5, iclass 26, count 2 2006.285.10:08:23.82#ibcon#read 5, iclass 26, count 2 2006.285.10:08:23.82#ibcon#about to read 6, iclass 26, count 2 2006.285.10:08:23.82#ibcon#read 6, iclass 26, count 2 2006.285.10:08:23.82#ibcon#end of sib2, iclass 26, count 2 2006.285.10:08:23.82#ibcon#*mode == 0, iclass 26, count 2 2006.285.10:08:23.82#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.10:08:23.82#ibcon#[27=AT06-03\r\n] 2006.285.10:08:23.82#ibcon#*before write, iclass 26, count 2 2006.285.10:08:23.82#ibcon#enter sib2, iclass 26, count 2 2006.285.10:08:23.82#ibcon#flushed, iclass 26, count 2 2006.285.10:08:23.82#ibcon#about to write, iclass 26, count 2 2006.285.10:08:23.82#ibcon#wrote, iclass 26, count 2 2006.285.10:08:23.82#ibcon#about to read 3, iclass 26, count 2 2006.285.10:08:23.85#ibcon#read 3, iclass 26, count 2 2006.285.10:08:23.85#ibcon#about to read 4, iclass 26, count 2 2006.285.10:08:23.85#ibcon#read 4, iclass 26, count 2 2006.285.10:08:23.85#ibcon#about to read 5, iclass 26, count 2 2006.285.10:08:23.85#ibcon#read 5, iclass 26, count 2 2006.285.10:08:23.85#ibcon#about to read 6, iclass 26, count 2 2006.285.10:08:23.85#ibcon#read 6, iclass 26, count 2 2006.285.10:08:23.85#ibcon#end of sib2, iclass 26, count 2 2006.285.10:08:23.85#ibcon#*after write, iclass 26, count 2 2006.285.10:08:23.85#ibcon#*before return 0, iclass 26, count 2 2006.285.10:08:23.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:08:23.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:08:23.85#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.10:08:23.85#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:23.85#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:08:23.97#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:08:23.97#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:08:23.97#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:08:23.97#ibcon#first serial, iclass 26, count 0 2006.285.10:08:23.97#ibcon#enter sib2, iclass 26, count 0 2006.285.10:08:23.97#ibcon#flushed, iclass 26, count 0 2006.285.10:08:23.97#ibcon#about to write, iclass 26, count 0 2006.285.10:08:23.97#ibcon#wrote, iclass 26, count 0 2006.285.10:08:23.97#ibcon#about to read 3, iclass 26, count 0 2006.285.10:08:23.99#ibcon#read 3, iclass 26, count 0 2006.285.10:08:23.99#ibcon#about to read 4, iclass 26, count 0 2006.285.10:08:23.99#ibcon#read 4, iclass 26, count 0 2006.285.10:08:23.99#ibcon#about to read 5, iclass 26, count 0 2006.285.10:08:23.99#ibcon#read 5, iclass 26, count 0 2006.285.10:08:23.99#ibcon#about to read 6, iclass 26, count 0 2006.285.10:08:23.99#ibcon#read 6, iclass 26, count 0 2006.285.10:08:23.99#ibcon#end of sib2, iclass 26, count 0 2006.285.10:08:23.99#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:08:23.99#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:08:23.99#ibcon#[27=USB\r\n] 2006.285.10:08:23.99#ibcon#*before write, iclass 26, count 0 2006.285.10:08:23.99#ibcon#enter sib2, iclass 26, count 0 2006.285.10:08:23.99#ibcon#flushed, iclass 26, count 0 2006.285.10:08:23.99#ibcon#about to write, iclass 26, count 0 2006.285.10:08:23.99#ibcon#wrote, iclass 26, count 0 2006.285.10:08:23.99#ibcon#about to read 3, iclass 26, count 0 2006.285.10:08:24.02#ibcon#read 3, iclass 26, count 0 2006.285.10:08:24.02#ibcon#about to read 4, iclass 26, count 0 2006.285.10:08:24.02#ibcon#read 4, iclass 26, count 0 2006.285.10:08:24.02#ibcon#about to read 5, iclass 26, count 0 2006.285.10:08:24.02#ibcon#read 5, iclass 26, count 0 2006.285.10:08:24.02#ibcon#about to read 6, iclass 26, count 0 2006.285.10:08:24.02#ibcon#read 6, iclass 26, count 0 2006.285.10:08:24.02#ibcon#end of sib2, iclass 26, count 0 2006.285.10:08:24.02#ibcon#*after write, iclass 26, count 0 2006.285.10:08:24.02#ibcon#*before return 0, iclass 26, count 0 2006.285.10:08:24.02#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:08:24.02#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:08:24.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:08:24.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:08:24.02$vck44/vblo=7,734.99 2006.285.10:08:24.02#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.10:08:24.02#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.10:08:24.02#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:24.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:08:24.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:08:24.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:08:24.02#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:08:24.02#ibcon#first serial, iclass 28, count 0 2006.285.10:08:24.02#ibcon#enter sib2, iclass 28, count 0 2006.285.10:08:24.03#ibcon#flushed, iclass 28, count 0 2006.285.10:08:24.03#ibcon#about to write, iclass 28, count 0 2006.285.10:08:24.03#ibcon#wrote, iclass 28, count 0 2006.285.10:08:24.03#ibcon#about to read 3, iclass 28, count 0 2006.285.10:08:24.04#ibcon#read 3, iclass 28, count 0 2006.285.10:08:24.04#ibcon#about to read 4, iclass 28, count 0 2006.285.10:08:24.04#ibcon#read 4, iclass 28, count 0 2006.285.10:08:24.04#ibcon#about to read 5, iclass 28, count 0 2006.285.10:08:24.04#ibcon#read 5, iclass 28, count 0 2006.285.10:08:24.04#ibcon#about to read 6, iclass 28, count 0 2006.285.10:08:24.04#ibcon#read 6, iclass 28, count 0 2006.285.10:08:24.04#ibcon#end of sib2, iclass 28, count 0 2006.285.10:08:24.04#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:08:24.04#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:08:24.04#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:08:24.04#ibcon#*before write, iclass 28, count 0 2006.285.10:08:24.04#ibcon#enter sib2, iclass 28, count 0 2006.285.10:08:24.04#ibcon#flushed, iclass 28, count 0 2006.285.10:08:24.04#ibcon#about to write, iclass 28, count 0 2006.285.10:08:24.04#ibcon#wrote, iclass 28, count 0 2006.285.10:08:24.04#ibcon#about to read 3, iclass 28, count 0 2006.285.10:08:24.08#ibcon#read 3, iclass 28, count 0 2006.285.10:08:24.08#ibcon#about to read 4, iclass 28, count 0 2006.285.10:08:24.08#ibcon#read 4, iclass 28, count 0 2006.285.10:08:24.08#ibcon#about to read 5, iclass 28, count 0 2006.285.10:08:24.08#ibcon#read 5, iclass 28, count 0 2006.285.10:08:24.08#ibcon#about to read 6, iclass 28, count 0 2006.285.10:08:24.08#ibcon#read 6, iclass 28, count 0 2006.285.10:08:24.08#ibcon#end of sib2, iclass 28, count 0 2006.285.10:08:24.08#ibcon#*after write, iclass 28, count 0 2006.285.10:08:24.08#ibcon#*before return 0, iclass 28, count 0 2006.285.10:08:24.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:08:24.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:08:24.08#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:08:24.08#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:08:24.08$vck44/vb=7,4 2006.285.10:08:24.08#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.10:08:24.08#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.10:08:24.08#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:24.08#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:08:24.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:08:24.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:08:24.14#ibcon#enter wrdev, iclass 30, count 2 2006.285.10:08:24.14#ibcon#first serial, iclass 30, count 2 2006.285.10:08:24.14#ibcon#enter sib2, iclass 30, count 2 2006.285.10:08:24.14#ibcon#flushed, iclass 30, count 2 2006.285.10:08:24.14#ibcon#about to write, iclass 30, count 2 2006.285.10:08:24.14#ibcon#wrote, iclass 30, count 2 2006.285.10:08:24.14#ibcon#about to read 3, iclass 30, count 2 2006.285.10:08:24.16#ibcon#read 3, iclass 30, count 2 2006.285.10:08:24.16#ibcon#about to read 4, iclass 30, count 2 2006.285.10:08:24.16#ibcon#read 4, iclass 30, count 2 2006.285.10:08:24.16#ibcon#about to read 5, iclass 30, count 2 2006.285.10:08:24.16#ibcon#read 5, iclass 30, count 2 2006.285.10:08:24.16#ibcon#about to read 6, iclass 30, count 2 2006.285.10:08:24.16#ibcon#read 6, iclass 30, count 2 2006.285.10:08:24.16#ibcon#end of sib2, iclass 30, count 2 2006.285.10:08:24.16#ibcon#*mode == 0, iclass 30, count 2 2006.285.10:08:24.16#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.10:08:24.16#ibcon#[27=AT07-04\r\n] 2006.285.10:08:24.16#ibcon#*before write, iclass 30, count 2 2006.285.10:08:24.16#ibcon#enter sib2, iclass 30, count 2 2006.285.10:08:24.16#ibcon#flushed, iclass 30, count 2 2006.285.10:08:24.16#ibcon#about to write, iclass 30, count 2 2006.285.10:08:24.16#ibcon#wrote, iclass 30, count 2 2006.285.10:08:24.16#ibcon#about to read 3, iclass 30, count 2 2006.285.10:08:24.19#ibcon#read 3, iclass 30, count 2 2006.285.10:08:24.19#ibcon#about to read 4, iclass 30, count 2 2006.285.10:08:24.19#ibcon#read 4, iclass 30, count 2 2006.285.10:08:24.19#ibcon#about to read 5, iclass 30, count 2 2006.285.10:08:24.19#ibcon#read 5, iclass 30, count 2 2006.285.10:08:24.19#ibcon#about to read 6, iclass 30, count 2 2006.285.10:08:24.19#ibcon#read 6, iclass 30, count 2 2006.285.10:08:24.19#ibcon#end of sib2, iclass 30, count 2 2006.285.10:08:24.19#ibcon#*after write, iclass 30, count 2 2006.285.10:08:24.19#ibcon#*before return 0, iclass 30, count 2 2006.285.10:08:24.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:08:24.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:08:24.19#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.10:08:24.19#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:24.19#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:08:24.31#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:08:24.31#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:08:24.31#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:08:24.31#ibcon#first serial, iclass 30, count 0 2006.285.10:08:24.31#ibcon#enter sib2, iclass 30, count 0 2006.285.10:08:24.31#ibcon#flushed, iclass 30, count 0 2006.285.10:08:24.31#ibcon#about to write, iclass 30, count 0 2006.285.10:08:24.31#ibcon#wrote, iclass 30, count 0 2006.285.10:08:24.31#ibcon#about to read 3, iclass 30, count 0 2006.285.10:08:24.33#ibcon#read 3, iclass 30, count 0 2006.285.10:08:24.33#ibcon#about to read 4, iclass 30, count 0 2006.285.10:08:24.33#ibcon#read 4, iclass 30, count 0 2006.285.10:08:24.33#ibcon#about to read 5, iclass 30, count 0 2006.285.10:08:24.33#ibcon#read 5, iclass 30, count 0 2006.285.10:08:24.33#ibcon#about to read 6, iclass 30, count 0 2006.285.10:08:24.33#ibcon#read 6, iclass 30, count 0 2006.285.10:08:24.33#ibcon#end of sib2, iclass 30, count 0 2006.285.10:08:24.33#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:08:24.33#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:08:24.33#ibcon#[27=USB\r\n] 2006.285.10:08:24.33#ibcon#*before write, iclass 30, count 0 2006.285.10:08:24.33#ibcon#enter sib2, iclass 30, count 0 2006.285.10:08:24.33#ibcon#flushed, iclass 30, count 0 2006.285.10:08:24.33#ibcon#about to write, iclass 30, count 0 2006.285.10:08:24.33#ibcon#wrote, iclass 30, count 0 2006.285.10:08:24.33#ibcon#about to read 3, iclass 30, count 0 2006.285.10:08:24.36#ibcon#read 3, iclass 30, count 0 2006.285.10:08:24.36#ibcon#about to read 4, iclass 30, count 0 2006.285.10:08:24.36#ibcon#read 4, iclass 30, count 0 2006.285.10:08:24.36#ibcon#about to read 5, iclass 30, count 0 2006.285.10:08:24.36#ibcon#read 5, iclass 30, count 0 2006.285.10:08:24.36#ibcon#about to read 6, iclass 30, count 0 2006.285.10:08:24.36#ibcon#read 6, iclass 30, count 0 2006.285.10:08:24.36#ibcon#end of sib2, iclass 30, count 0 2006.285.10:08:24.36#ibcon#*after write, iclass 30, count 0 2006.285.10:08:24.36#ibcon#*before return 0, iclass 30, count 0 2006.285.10:08:24.36#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:08:24.36#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:08:24.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:08:24.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:08:24.36$vck44/vblo=8,744.99 2006.285.10:08:24.36#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.10:08:24.36#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.10:08:24.36#ibcon#ireg 17 cls_cnt 0 2006.285.10:08:24.36#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:08:24.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:08:24.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:08:24.36#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:08:24.36#ibcon#first serial, iclass 32, count 0 2006.285.10:08:24.36#ibcon#enter sib2, iclass 32, count 0 2006.285.10:08:24.36#ibcon#flushed, iclass 32, count 0 2006.285.10:08:24.36#ibcon#about to write, iclass 32, count 0 2006.285.10:08:24.36#ibcon#wrote, iclass 32, count 0 2006.285.10:08:24.36#ibcon#about to read 3, iclass 32, count 0 2006.285.10:08:24.38#ibcon#read 3, iclass 32, count 0 2006.285.10:08:24.38#ibcon#about to read 4, iclass 32, count 0 2006.285.10:08:24.38#ibcon#read 4, iclass 32, count 0 2006.285.10:08:24.38#ibcon#about to read 5, iclass 32, count 0 2006.285.10:08:24.38#ibcon#read 5, iclass 32, count 0 2006.285.10:08:24.38#ibcon#about to read 6, iclass 32, count 0 2006.285.10:08:24.38#ibcon#read 6, iclass 32, count 0 2006.285.10:08:24.38#ibcon#end of sib2, iclass 32, count 0 2006.285.10:08:24.38#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:08:24.38#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:08:24.38#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:08:24.38#ibcon#*before write, iclass 32, count 0 2006.285.10:08:24.38#ibcon#enter sib2, iclass 32, count 0 2006.285.10:08:24.38#ibcon#flushed, iclass 32, count 0 2006.285.10:08:24.38#ibcon#about to write, iclass 32, count 0 2006.285.10:08:24.38#ibcon#wrote, iclass 32, count 0 2006.285.10:08:24.38#ibcon#about to read 3, iclass 32, count 0 2006.285.10:08:24.42#ibcon#read 3, iclass 32, count 0 2006.285.10:08:24.42#ibcon#about to read 4, iclass 32, count 0 2006.285.10:08:24.42#ibcon#read 4, iclass 32, count 0 2006.285.10:08:24.42#ibcon#about to read 5, iclass 32, count 0 2006.285.10:08:24.42#ibcon#read 5, iclass 32, count 0 2006.285.10:08:24.42#ibcon#about to read 6, iclass 32, count 0 2006.285.10:08:24.42#ibcon#read 6, iclass 32, count 0 2006.285.10:08:24.42#ibcon#end of sib2, iclass 32, count 0 2006.285.10:08:24.42#ibcon#*after write, iclass 32, count 0 2006.285.10:08:24.42#ibcon#*before return 0, iclass 32, count 0 2006.285.10:08:24.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:08:24.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:08:24.42#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:08:24.42#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:08:24.42$vck44/vb=8,4 2006.285.10:08:24.42#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.10:08:24.42#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.10:08:24.42#ibcon#ireg 11 cls_cnt 2 2006.285.10:08:24.42#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:08:24.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:08:24.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:08:24.48#ibcon#enter wrdev, iclass 34, count 2 2006.285.10:08:24.48#ibcon#first serial, iclass 34, count 2 2006.285.10:08:24.48#ibcon#enter sib2, iclass 34, count 2 2006.285.10:08:24.48#ibcon#flushed, iclass 34, count 2 2006.285.10:08:24.48#ibcon#about to write, iclass 34, count 2 2006.285.10:08:24.48#ibcon#wrote, iclass 34, count 2 2006.285.10:08:24.48#ibcon#about to read 3, iclass 34, count 2 2006.285.10:08:24.50#ibcon#read 3, iclass 34, count 2 2006.285.10:08:24.50#ibcon#about to read 4, iclass 34, count 2 2006.285.10:08:24.50#ibcon#read 4, iclass 34, count 2 2006.285.10:08:24.50#ibcon#about to read 5, iclass 34, count 2 2006.285.10:08:24.50#ibcon#read 5, iclass 34, count 2 2006.285.10:08:24.50#ibcon#about to read 6, iclass 34, count 2 2006.285.10:08:24.50#ibcon#read 6, iclass 34, count 2 2006.285.10:08:24.50#ibcon#end of sib2, iclass 34, count 2 2006.285.10:08:24.50#ibcon#*mode == 0, iclass 34, count 2 2006.285.10:08:24.50#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.10:08:24.50#ibcon#[27=AT08-04\r\n] 2006.285.10:08:24.50#ibcon#*before write, iclass 34, count 2 2006.285.10:08:24.50#ibcon#enter sib2, iclass 34, count 2 2006.285.10:08:24.50#ibcon#flushed, iclass 34, count 2 2006.285.10:08:24.50#ibcon#about to write, iclass 34, count 2 2006.285.10:08:24.50#ibcon#wrote, iclass 34, count 2 2006.285.10:08:24.50#ibcon#about to read 3, iclass 34, count 2 2006.285.10:08:24.53#ibcon#read 3, iclass 34, count 2 2006.285.10:08:24.53#ibcon#about to read 4, iclass 34, count 2 2006.285.10:08:24.53#ibcon#read 4, iclass 34, count 2 2006.285.10:08:24.53#ibcon#about to read 5, iclass 34, count 2 2006.285.10:08:24.53#ibcon#read 5, iclass 34, count 2 2006.285.10:08:24.53#ibcon#about to read 6, iclass 34, count 2 2006.285.10:08:24.53#ibcon#read 6, iclass 34, count 2 2006.285.10:08:24.53#ibcon#end of sib2, iclass 34, count 2 2006.285.10:08:24.53#ibcon#*after write, iclass 34, count 2 2006.285.10:08:24.53#ibcon#*before return 0, iclass 34, count 2 2006.285.10:08:24.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:08:24.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:08:24.53#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.10:08:24.53#ibcon#ireg 7 cls_cnt 0 2006.285.10:08:24.53#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:08:24.65#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:08:24.65#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:08:24.65#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:08:24.65#ibcon#first serial, iclass 34, count 0 2006.285.10:08:24.65#ibcon#enter sib2, iclass 34, count 0 2006.285.10:08:24.65#ibcon#flushed, iclass 34, count 0 2006.285.10:08:24.65#ibcon#about to write, iclass 34, count 0 2006.285.10:08:24.65#ibcon#wrote, iclass 34, count 0 2006.285.10:08:24.65#ibcon#about to read 3, iclass 34, count 0 2006.285.10:08:24.67#ibcon#read 3, iclass 34, count 0 2006.285.10:08:24.67#ibcon#about to read 4, iclass 34, count 0 2006.285.10:08:24.67#ibcon#read 4, iclass 34, count 0 2006.285.10:08:24.67#ibcon#about to read 5, iclass 34, count 0 2006.285.10:08:24.67#ibcon#read 5, iclass 34, count 0 2006.285.10:08:24.67#ibcon#about to read 6, iclass 34, count 0 2006.285.10:08:24.67#ibcon#read 6, iclass 34, count 0 2006.285.10:08:24.67#ibcon#end of sib2, iclass 34, count 0 2006.285.10:08:24.67#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:08:24.67#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:08:24.67#ibcon#[27=USB\r\n] 2006.285.10:08:24.67#ibcon#*before write, iclass 34, count 0 2006.285.10:08:24.67#ibcon#enter sib2, iclass 34, count 0 2006.285.10:08:24.67#ibcon#flushed, iclass 34, count 0 2006.285.10:08:24.67#ibcon#about to write, iclass 34, count 0 2006.285.10:08:24.67#ibcon#wrote, iclass 34, count 0 2006.285.10:08:24.67#ibcon#about to read 3, iclass 34, count 0 2006.285.10:08:24.70#ibcon#read 3, iclass 34, count 0 2006.285.10:08:24.70#ibcon#about to read 4, iclass 34, count 0 2006.285.10:08:24.70#ibcon#read 4, iclass 34, count 0 2006.285.10:08:24.70#ibcon#about to read 5, iclass 34, count 0 2006.285.10:08:24.70#ibcon#read 5, iclass 34, count 0 2006.285.10:08:24.70#ibcon#about to read 6, iclass 34, count 0 2006.285.10:08:24.70#ibcon#read 6, iclass 34, count 0 2006.285.10:08:24.70#ibcon#end of sib2, iclass 34, count 0 2006.285.10:08:24.70#ibcon#*after write, iclass 34, count 0 2006.285.10:08:24.70#ibcon#*before return 0, iclass 34, count 0 2006.285.10:08:24.70#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:08:24.70#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:08:24.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:08:24.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:08:24.70$vck44/vabw=wide 2006.285.10:08:24.70#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.10:08:24.70#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.10:08:24.70#ibcon#ireg 8 cls_cnt 0 2006.285.10:08:24.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:08:24.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:08:24.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:08:24.70#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:08:24.70#ibcon#first serial, iclass 36, count 0 2006.285.10:08:24.70#ibcon#enter sib2, iclass 36, count 0 2006.285.10:08:24.70#ibcon#flushed, iclass 36, count 0 2006.285.10:08:24.70#ibcon#about to write, iclass 36, count 0 2006.285.10:08:24.70#ibcon#wrote, iclass 36, count 0 2006.285.10:08:24.70#ibcon#about to read 3, iclass 36, count 0 2006.285.10:08:24.72#ibcon#read 3, iclass 36, count 0 2006.285.10:08:24.72#ibcon#about to read 4, iclass 36, count 0 2006.285.10:08:24.72#ibcon#read 4, iclass 36, count 0 2006.285.10:08:24.72#ibcon#about to read 5, iclass 36, count 0 2006.285.10:08:24.72#ibcon#read 5, iclass 36, count 0 2006.285.10:08:24.72#ibcon#about to read 6, iclass 36, count 0 2006.285.10:08:24.72#ibcon#read 6, iclass 36, count 0 2006.285.10:08:24.72#ibcon#end of sib2, iclass 36, count 0 2006.285.10:08:24.72#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:08:24.72#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:08:24.72#ibcon#[25=BW32\r\n] 2006.285.10:08:24.72#ibcon#*before write, iclass 36, count 0 2006.285.10:08:24.72#ibcon#enter sib2, iclass 36, count 0 2006.285.10:08:24.72#ibcon#flushed, iclass 36, count 0 2006.285.10:08:24.72#ibcon#about to write, iclass 36, count 0 2006.285.10:08:24.72#ibcon#wrote, iclass 36, count 0 2006.285.10:08:24.72#ibcon#about to read 3, iclass 36, count 0 2006.285.10:08:24.75#ibcon#read 3, iclass 36, count 0 2006.285.10:08:24.75#ibcon#about to read 4, iclass 36, count 0 2006.285.10:08:24.75#ibcon#read 4, iclass 36, count 0 2006.285.10:08:24.75#ibcon#about to read 5, iclass 36, count 0 2006.285.10:08:24.75#ibcon#read 5, iclass 36, count 0 2006.285.10:08:24.75#ibcon#about to read 6, iclass 36, count 0 2006.285.10:08:24.75#ibcon#read 6, iclass 36, count 0 2006.285.10:08:24.75#ibcon#end of sib2, iclass 36, count 0 2006.285.10:08:24.75#ibcon#*after write, iclass 36, count 0 2006.285.10:08:24.75#ibcon#*before return 0, iclass 36, count 0 2006.285.10:08:24.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:08:24.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:08:24.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:08:24.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:08:24.75$vck44/vbbw=wide 2006.285.10:08:24.75#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.10:08:24.75#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.10:08:24.75#ibcon#ireg 8 cls_cnt 0 2006.285.10:08:24.75#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:08:24.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:08:24.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:08:24.82#ibcon#enter wrdev, iclass 38, count 0 2006.285.10:08:24.82#ibcon#first serial, iclass 38, count 0 2006.285.10:08:24.82#ibcon#enter sib2, iclass 38, count 0 2006.285.10:08:24.82#ibcon#flushed, iclass 38, count 0 2006.285.10:08:24.82#ibcon#about to write, iclass 38, count 0 2006.285.10:08:24.82#ibcon#wrote, iclass 38, count 0 2006.285.10:08:24.82#ibcon#about to read 3, iclass 38, count 0 2006.285.10:08:24.84#ibcon#read 3, iclass 38, count 0 2006.285.10:08:24.84#ibcon#about to read 4, iclass 38, count 0 2006.285.10:08:24.84#ibcon#read 4, iclass 38, count 0 2006.285.10:08:24.84#ibcon#about to read 5, iclass 38, count 0 2006.285.10:08:24.84#ibcon#read 5, iclass 38, count 0 2006.285.10:08:24.84#ibcon#about to read 6, iclass 38, count 0 2006.285.10:08:24.84#ibcon#read 6, iclass 38, count 0 2006.285.10:08:24.84#ibcon#end of sib2, iclass 38, count 0 2006.285.10:08:24.84#ibcon#*mode == 0, iclass 38, count 0 2006.285.10:08:24.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.10:08:24.84#ibcon#[27=BW32\r\n] 2006.285.10:08:24.84#ibcon#*before write, iclass 38, count 0 2006.285.10:08:24.84#ibcon#enter sib2, iclass 38, count 0 2006.285.10:08:24.84#ibcon#flushed, iclass 38, count 0 2006.285.10:08:24.84#ibcon#about to write, iclass 38, count 0 2006.285.10:08:24.84#ibcon#wrote, iclass 38, count 0 2006.285.10:08:24.84#ibcon#about to read 3, iclass 38, count 0 2006.285.10:08:24.87#ibcon#read 3, iclass 38, count 0 2006.285.10:08:24.87#ibcon#about to read 4, iclass 38, count 0 2006.285.10:08:24.87#ibcon#read 4, iclass 38, count 0 2006.285.10:08:24.87#ibcon#about to read 5, iclass 38, count 0 2006.285.10:08:24.87#ibcon#read 5, iclass 38, count 0 2006.285.10:08:24.87#ibcon#about to read 6, iclass 38, count 0 2006.285.10:08:24.87#ibcon#read 6, iclass 38, count 0 2006.285.10:08:24.87#ibcon#end of sib2, iclass 38, count 0 2006.285.10:08:24.87#ibcon#*after write, iclass 38, count 0 2006.285.10:08:24.87#ibcon#*before return 0, iclass 38, count 0 2006.285.10:08:24.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:08:24.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:08:24.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.10:08:24.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.10:08:24.87$setupk4/ifdk4 2006.285.10:08:24.87$ifdk4/lo= 2006.285.10:08:24.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:08:24.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:08:24.88$ifdk4/patch= 2006.285.10:08:24.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:08:24.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:08:24.88$setupk4/!*+20s 2006.285.10:08:31.34#abcon#<5=/05 1.2 1.9 19.57 911015.1\r\n> 2006.285.10:08:31.36#abcon#{5=INTERFACE CLEAR} 2006.285.10:08:31.42#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:08:32.14#trakl#Source acquired 2006.285.10:08:32.14#flagr#flagr/antenna,acquired 2006.285.10:08:39.41$setupk4/"tpicd 2006.285.10:08:39.41$setupk4/echo=off 2006.285.10:08:39.41$setupk4/xlog=off 2006.285.10:08:39.41:!2006.285.10:12:14 2006.285.10:12:14.00:preob 2006.285.10:12:15.13/onsource/TRACKING 2006.285.10:12:15.13:!2006.285.10:12:24 2006.285.10:12:24.00:"tape 2006.285.10:12:24.00:"st=record 2006.285.10:12:24.00:data_valid=on 2006.285.10:12:24.00:midob 2006.285.10:12:24.13/onsource/TRACKING 2006.285.10:12:24.13/wx/19.67,1015.0,90 2006.285.10:12:24.27/cable/+6.4837E-03 2006.285.10:12:25.36/va/01,07,usb,yes,32,34 2006.285.10:12:25.36/va/02,06,usb,yes,32,32 2006.285.10:12:25.36/va/03,07,usb,yes,31,33 2006.285.10:12:25.36/va/04,06,usb,yes,33,34 2006.285.10:12:25.36/va/05,03,usb,yes,32,33 2006.285.10:12:25.36/va/06,04,usb,yes,29,29 2006.285.10:12:25.36/va/07,04,usb,yes,30,30 2006.285.10:12:25.36/va/08,03,usb,yes,30,37 2006.285.10:12:25.59/valo/01,524.99,yes,locked 2006.285.10:12:25.59/valo/02,534.99,yes,locked 2006.285.10:12:25.59/valo/03,564.99,yes,locked 2006.285.10:12:25.59/valo/04,624.99,yes,locked 2006.285.10:12:25.59/valo/05,734.99,yes,locked 2006.285.10:12:25.59/valo/06,814.99,yes,locked 2006.285.10:12:25.59/valo/07,864.99,yes,locked 2006.285.10:12:25.59/valo/08,884.99,yes,locked 2006.285.10:12:26.68/vb/01,04,usb,yes,31,28 2006.285.10:12:26.68/vb/02,05,usb,yes,29,29 2006.285.10:12:26.68/vb/03,04,usb,yes,29,33 2006.285.10:12:26.68/vb/04,05,usb,yes,30,29 2006.285.10:12:26.68/vb/05,04,usb,yes,26,29 2006.285.10:12:26.68/vb/06,03,usb,yes,38,33 2006.285.10:12:26.68/vb/07,04,usb,yes,30,30 2006.285.10:12:26.68/vb/08,04,usb,yes,28,31 2006.285.10:12:26.91/vblo/01,629.99,yes,locked 2006.285.10:12:26.91/vblo/02,634.99,yes,locked 2006.285.10:12:26.91/vblo/03,649.99,yes,locked 2006.285.10:12:26.91/vblo/04,679.99,yes,locked 2006.285.10:12:26.91/vblo/05,709.99,yes,locked 2006.285.10:12:26.91/vblo/06,719.99,yes,locked 2006.285.10:12:26.91/vblo/07,734.99,yes,locked 2006.285.10:12:26.91/vblo/08,744.99,yes,locked 2006.285.10:12:27.06/vabw/8 2006.285.10:12:27.21/vbbw/8 2006.285.10:12:27.34/xfe/off,on,12.2 2006.285.10:12:27.72/ifatt/23,28,28,28 2006.285.10:12:28.07/fmout-gps/S +2.67E-07 2006.285.10:12:28.09:!2006.285.10:14:04 2006.285.10:14:04.00:data_valid=off 2006.285.10:14:04.00:"et 2006.285.10:14:04.00:!+3s 2006.285.10:14:07.01:"tape 2006.285.10:14:07.01:postob 2006.285.10:14:07.20/cable/+6.4855E-03 2006.285.10:14:07.20/wx/19.70,1015.0,90 2006.285.10:14:08.07/fmout-gps/S +2.68E-07 2006.285.10:14:08.07:scan_name=285-1018,jd0610,40 2006.285.10:14:08.07:source=3c345,164258.81,394837.0,2000.0,cw 2006.285.10:14:09.14#flagr#flagr/antenna,new-source 2006.285.10:14:09.14:checkk5 2006.285.10:14:09.50/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:14:10.12/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:14:10.50/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:14:10.91/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:14:11.29/chk_obsdata//k5ts1/T2851012??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.10:14:11.64/chk_obsdata//k5ts2/T2851012??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.10:14:11.98/chk_obsdata//k5ts3/T2851012??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.10:14:12.38/chk_obsdata//k5ts4/T2851012??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.10:14:13.22/k5log//k5ts1_log_newline 2006.285.10:14:14.01/k5log//k5ts2_log_newline 2006.285.10:14:15.14/k5log//k5ts3_log_newline 2006.285.10:14:15.95/k5log//k5ts4_log_newline 2006.285.10:14:15.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:14:15.97:setupk4=1 2006.285.10:14:15.97$setupk4/echo=on 2006.285.10:14:15.97$setupk4/pcalon 2006.285.10:14:15.97$pcalon/"no phase cal control is implemented here 2006.285.10:14:15.97$setupk4/"tpicd=stop 2006.285.10:14:15.97$setupk4/"rec=synch_on 2006.285.10:14:15.97$setupk4/"rec_mode=128 2006.285.10:14:15.97$setupk4/!* 2006.285.10:14:15.97$setupk4/recpk4 2006.285.10:14:15.97$recpk4/recpatch= 2006.285.10:14:15.97$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:14:15.97$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:14:15.97$setupk4/vck44 2006.285.10:14:15.97$vck44/valo=1,524.99 2006.285.10:14:15.97#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.10:14:15.97#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.10:14:15.97#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:15.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:14:15.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:14:15.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:14:15.97#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:14:15.97#ibcon#first serial, iclass 35, count 0 2006.285.10:14:15.97#ibcon#enter sib2, iclass 35, count 0 2006.285.10:14:15.97#ibcon#flushed, iclass 35, count 0 2006.285.10:14:15.97#ibcon#about to write, iclass 35, count 0 2006.285.10:14:15.97#ibcon#wrote, iclass 35, count 0 2006.285.10:14:15.97#ibcon#about to read 3, iclass 35, count 0 2006.285.10:14:15.99#ibcon#read 3, iclass 35, count 0 2006.285.10:14:15.99#ibcon#about to read 4, iclass 35, count 0 2006.285.10:14:15.99#ibcon#read 4, iclass 35, count 0 2006.285.10:14:15.99#ibcon#about to read 5, iclass 35, count 0 2006.285.10:14:15.99#ibcon#read 5, iclass 35, count 0 2006.285.10:14:15.99#ibcon#about to read 6, iclass 35, count 0 2006.285.10:14:15.99#ibcon#read 6, iclass 35, count 0 2006.285.10:14:15.99#ibcon#end of sib2, iclass 35, count 0 2006.285.10:14:15.99#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:14:15.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:14:15.99#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:14:15.99#ibcon#*before write, iclass 35, count 0 2006.285.10:14:15.99#ibcon#enter sib2, iclass 35, count 0 2006.285.10:14:15.99#ibcon#flushed, iclass 35, count 0 2006.285.10:14:15.99#ibcon#about to write, iclass 35, count 0 2006.285.10:14:15.99#ibcon#wrote, iclass 35, count 0 2006.285.10:14:15.99#ibcon#about to read 3, iclass 35, count 0 2006.285.10:14:16.04#ibcon#read 3, iclass 35, count 0 2006.285.10:14:16.04#ibcon#about to read 4, iclass 35, count 0 2006.285.10:14:16.04#ibcon#read 4, iclass 35, count 0 2006.285.10:14:16.04#ibcon#about to read 5, iclass 35, count 0 2006.285.10:14:16.04#ibcon#read 5, iclass 35, count 0 2006.285.10:14:16.04#ibcon#about to read 6, iclass 35, count 0 2006.285.10:14:16.04#ibcon#read 6, iclass 35, count 0 2006.285.10:14:16.04#ibcon#end of sib2, iclass 35, count 0 2006.285.10:14:16.04#ibcon#*after write, iclass 35, count 0 2006.285.10:14:16.04#ibcon#*before return 0, iclass 35, count 0 2006.285.10:14:16.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:14:16.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:14:16.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:14:16.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:14:16.04$vck44/va=1,7 2006.285.10:14:16.04#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.10:14:16.04#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.10:14:16.04#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:16.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:14:16.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:14:16.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:14:16.04#ibcon#enter wrdev, iclass 37, count 2 2006.285.10:14:16.04#ibcon#first serial, iclass 37, count 2 2006.285.10:14:16.04#ibcon#enter sib2, iclass 37, count 2 2006.285.10:14:16.04#ibcon#flushed, iclass 37, count 2 2006.285.10:14:16.04#ibcon#about to write, iclass 37, count 2 2006.285.10:14:16.04#ibcon#wrote, iclass 37, count 2 2006.285.10:14:16.04#ibcon#about to read 3, iclass 37, count 2 2006.285.10:14:16.06#ibcon#read 3, iclass 37, count 2 2006.285.10:14:16.06#ibcon#about to read 4, iclass 37, count 2 2006.285.10:14:16.06#ibcon#read 4, iclass 37, count 2 2006.285.10:14:16.06#ibcon#about to read 5, iclass 37, count 2 2006.285.10:14:16.06#ibcon#read 5, iclass 37, count 2 2006.285.10:14:16.06#ibcon#about to read 6, iclass 37, count 2 2006.285.10:14:16.06#ibcon#read 6, iclass 37, count 2 2006.285.10:14:16.06#ibcon#end of sib2, iclass 37, count 2 2006.285.10:14:16.06#ibcon#*mode == 0, iclass 37, count 2 2006.285.10:14:16.06#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.10:14:16.06#ibcon#[25=AT01-07\r\n] 2006.285.10:14:16.06#ibcon#*before write, iclass 37, count 2 2006.285.10:14:16.06#ibcon#enter sib2, iclass 37, count 2 2006.285.10:14:16.06#ibcon#flushed, iclass 37, count 2 2006.285.10:14:16.06#ibcon#about to write, iclass 37, count 2 2006.285.10:14:16.06#ibcon#wrote, iclass 37, count 2 2006.285.10:14:16.06#ibcon#about to read 3, iclass 37, count 2 2006.285.10:14:16.09#ibcon#read 3, iclass 37, count 2 2006.285.10:14:16.09#ibcon#about to read 4, iclass 37, count 2 2006.285.10:14:16.09#ibcon#read 4, iclass 37, count 2 2006.285.10:14:16.09#ibcon#about to read 5, iclass 37, count 2 2006.285.10:14:16.09#ibcon#read 5, iclass 37, count 2 2006.285.10:14:16.09#ibcon#about to read 6, iclass 37, count 2 2006.285.10:14:16.09#ibcon#read 6, iclass 37, count 2 2006.285.10:14:16.09#ibcon#end of sib2, iclass 37, count 2 2006.285.10:14:16.09#ibcon#*after write, iclass 37, count 2 2006.285.10:14:16.09#ibcon#*before return 0, iclass 37, count 2 2006.285.10:14:16.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:14:16.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:14:16.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.10:14:16.09#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:16.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:14:16.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:14:16.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:14:16.21#ibcon#enter wrdev, iclass 37, count 0 2006.285.10:14:16.21#ibcon#first serial, iclass 37, count 0 2006.285.10:14:16.21#ibcon#enter sib2, iclass 37, count 0 2006.285.10:14:16.21#ibcon#flushed, iclass 37, count 0 2006.285.10:14:16.21#ibcon#about to write, iclass 37, count 0 2006.285.10:14:16.21#ibcon#wrote, iclass 37, count 0 2006.285.10:14:16.21#ibcon#about to read 3, iclass 37, count 0 2006.285.10:14:16.23#ibcon#read 3, iclass 37, count 0 2006.285.10:14:16.23#ibcon#about to read 4, iclass 37, count 0 2006.285.10:14:16.23#ibcon#read 4, iclass 37, count 0 2006.285.10:14:16.23#ibcon#about to read 5, iclass 37, count 0 2006.285.10:14:16.23#ibcon#read 5, iclass 37, count 0 2006.285.10:14:16.23#ibcon#about to read 6, iclass 37, count 0 2006.285.10:14:16.23#ibcon#read 6, iclass 37, count 0 2006.285.10:14:16.23#ibcon#end of sib2, iclass 37, count 0 2006.285.10:14:16.23#ibcon#*mode == 0, iclass 37, count 0 2006.285.10:14:16.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.10:14:16.23#ibcon#[25=USB\r\n] 2006.285.10:14:16.23#ibcon#*before write, iclass 37, count 0 2006.285.10:14:16.23#ibcon#enter sib2, iclass 37, count 0 2006.285.10:14:16.23#ibcon#flushed, iclass 37, count 0 2006.285.10:14:16.23#ibcon#about to write, iclass 37, count 0 2006.285.10:14:16.23#ibcon#wrote, iclass 37, count 0 2006.285.10:14:16.23#ibcon#about to read 3, iclass 37, count 0 2006.285.10:14:16.26#ibcon#read 3, iclass 37, count 0 2006.285.10:14:16.26#ibcon#about to read 4, iclass 37, count 0 2006.285.10:14:16.26#ibcon#read 4, iclass 37, count 0 2006.285.10:14:16.26#ibcon#about to read 5, iclass 37, count 0 2006.285.10:14:16.26#ibcon#read 5, iclass 37, count 0 2006.285.10:14:16.26#ibcon#about to read 6, iclass 37, count 0 2006.285.10:14:16.26#ibcon#read 6, iclass 37, count 0 2006.285.10:14:16.26#ibcon#end of sib2, iclass 37, count 0 2006.285.10:14:16.26#ibcon#*after write, iclass 37, count 0 2006.285.10:14:16.26#ibcon#*before return 0, iclass 37, count 0 2006.285.10:14:16.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:14:16.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:14:16.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.10:14:16.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.10:14:16.26$vck44/valo=2,534.99 2006.285.10:14:16.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.10:14:16.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.10:14:16.26#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:16.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:14:16.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:14:16.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:14:16.26#ibcon#enter wrdev, iclass 39, count 0 2006.285.10:14:16.26#ibcon#first serial, iclass 39, count 0 2006.285.10:14:16.26#ibcon#enter sib2, iclass 39, count 0 2006.285.10:14:16.26#ibcon#flushed, iclass 39, count 0 2006.285.10:14:16.26#ibcon#about to write, iclass 39, count 0 2006.285.10:14:16.26#ibcon#wrote, iclass 39, count 0 2006.285.10:14:16.26#ibcon#about to read 3, iclass 39, count 0 2006.285.10:14:16.28#ibcon#read 3, iclass 39, count 0 2006.285.10:14:16.28#ibcon#about to read 4, iclass 39, count 0 2006.285.10:14:16.28#ibcon#read 4, iclass 39, count 0 2006.285.10:14:16.28#ibcon#about to read 5, iclass 39, count 0 2006.285.10:14:16.28#ibcon#read 5, iclass 39, count 0 2006.285.10:14:16.28#ibcon#about to read 6, iclass 39, count 0 2006.285.10:14:16.28#ibcon#read 6, iclass 39, count 0 2006.285.10:14:16.28#ibcon#end of sib2, iclass 39, count 0 2006.285.10:14:16.28#ibcon#*mode == 0, iclass 39, count 0 2006.285.10:14:16.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.10:14:16.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:14:16.28#ibcon#*before write, iclass 39, count 0 2006.285.10:14:16.28#ibcon#enter sib2, iclass 39, count 0 2006.285.10:14:16.28#ibcon#flushed, iclass 39, count 0 2006.285.10:14:16.28#ibcon#about to write, iclass 39, count 0 2006.285.10:14:16.28#ibcon#wrote, iclass 39, count 0 2006.285.10:14:16.28#ibcon#about to read 3, iclass 39, count 0 2006.285.10:14:16.32#ibcon#read 3, iclass 39, count 0 2006.285.10:14:16.32#ibcon#about to read 4, iclass 39, count 0 2006.285.10:14:16.32#ibcon#read 4, iclass 39, count 0 2006.285.10:14:16.32#ibcon#about to read 5, iclass 39, count 0 2006.285.10:14:16.32#ibcon#read 5, iclass 39, count 0 2006.285.10:14:16.32#ibcon#about to read 6, iclass 39, count 0 2006.285.10:14:16.32#ibcon#read 6, iclass 39, count 0 2006.285.10:14:16.32#ibcon#end of sib2, iclass 39, count 0 2006.285.10:14:16.32#ibcon#*after write, iclass 39, count 0 2006.285.10:14:16.32#ibcon#*before return 0, iclass 39, count 0 2006.285.10:14:16.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:14:16.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:14:16.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.10:14:16.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.10:14:16.32$vck44/va=2,6 2006.285.10:14:16.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.10:14:16.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.10:14:16.32#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:16.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:14:16.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:14:16.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:14:16.38#ibcon#enter wrdev, iclass 3, count 2 2006.285.10:14:16.38#ibcon#first serial, iclass 3, count 2 2006.285.10:14:16.38#ibcon#enter sib2, iclass 3, count 2 2006.285.10:14:16.38#ibcon#flushed, iclass 3, count 2 2006.285.10:14:16.38#ibcon#about to write, iclass 3, count 2 2006.285.10:14:16.38#ibcon#wrote, iclass 3, count 2 2006.285.10:14:16.38#ibcon#about to read 3, iclass 3, count 2 2006.285.10:14:16.40#ibcon#read 3, iclass 3, count 2 2006.285.10:14:16.40#ibcon#about to read 4, iclass 3, count 2 2006.285.10:14:16.40#ibcon#read 4, iclass 3, count 2 2006.285.10:14:16.40#ibcon#about to read 5, iclass 3, count 2 2006.285.10:14:16.40#ibcon#read 5, iclass 3, count 2 2006.285.10:14:16.40#ibcon#about to read 6, iclass 3, count 2 2006.285.10:14:16.40#ibcon#read 6, iclass 3, count 2 2006.285.10:14:16.40#ibcon#end of sib2, iclass 3, count 2 2006.285.10:14:16.40#ibcon#*mode == 0, iclass 3, count 2 2006.285.10:14:16.40#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.10:14:16.40#ibcon#[25=AT02-06\r\n] 2006.285.10:14:16.40#ibcon#*before write, iclass 3, count 2 2006.285.10:14:16.40#ibcon#enter sib2, iclass 3, count 2 2006.285.10:14:16.40#ibcon#flushed, iclass 3, count 2 2006.285.10:14:16.40#ibcon#about to write, iclass 3, count 2 2006.285.10:14:16.40#ibcon#wrote, iclass 3, count 2 2006.285.10:14:16.40#ibcon#about to read 3, iclass 3, count 2 2006.285.10:14:16.43#ibcon#read 3, iclass 3, count 2 2006.285.10:14:16.43#ibcon#about to read 4, iclass 3, count 2 2006.285.10:14:16.43#ibcon#read 4, iclass 3, count 2 2006.285.10:14:16.43#ibcon#about to read 5, iclass 3, count 2 2006.285.10:14:16.43#ibcon#read 5, iclass 3, count 2 2006.285.10:14:16.43#ibcon#about to read 6, iclass 3, count 2 2006.285.10:14:16.43#ibcon#read 6, iclass 3, count 2 2006.285.10:14:16.43#ibcon#end of sib2, iclass 3, count 2 2006.285.10:14:16.43#ibcon#*after write, iclass 3, count 2 2006.285.10:14:16.43#ibcon#*before return 0, iclass 3, count 2 2006.285.10:14:16.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:14:16.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:14:16.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.10:14:16.43#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:16.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:14:16.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:14:16.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:14:16.55#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:14:16.55#ibcon#first serial, iclass 3, count 0 2006.285.10:14:16.55#ibcon#enter sib2, iclass 3, count 0 2006.285.10:14:16.55#ibcon#flushed, iclass 3, count 0 2006.285.10:14:16.55#ibcon#about to write, iclass 3, count 0 2006.285.10:14:16.55#ibcon#wrote, iclass 3, count 0 2006.285.10:14:16.55#ibcon#about to read 3, iclass 3, count 0 2006.285.10:14:16.57#ibcon#read 3, iclass 3, count 0 2006.285.10:14:16.57#ibcon#about to read 4, iclass 3, count 0 2006.285.10:14:16.57#ibcon#read 4, iclass 3, count 0 2006.285.10:14:16.57#ibcon#about to read 5, iclass 3, count 0 2006.285.10:14:16.57#ibcon#read 5, iclass 3, count 0 2006.285.10:14:16.57#ibcon#about to read 6, iclass 3, count 0 2006.285.10:14:16.57#ibcon#read 6, iclass 3, count 0 2006.285.10:14:16.57#ibcon#end of sib2, iclass 3, count 0 2006.285.10:14:16.57#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:14:16.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:14:16.57#ibcon#[25=USB\r\n] 2006.285.10:14:16.57#ibcon#*before write, iclass 3, count 0 2006.285.10:14:16.57#ibcon#enter sib2, iclass 3, count 0 2006.285.10:14:16.57#ibcon#flushed, iclass 3, count 0 2006.285.10:14:16.57#ibcon#about to write, iclass 3, count 0 2006.285.10:14:16.57#ibcon#wrote, iclass 3, count 0 2006.285.10:14:16.57#ibcon#about to read 3, iclass 3, count 0 2006.285.10:14:16.60#ibcon#read 3, iclass 3, count 0 2006.285.10:14:16.60#ibcon#about to read 4, iclass 3, count 0 2006.285.10:14:16.60#ibcon#read 4, iclass 3, count 0 2006.285.10:14:16.60#ibcon#about to read 5, iclass 3, count 0 2006.285.10:14:16.60#ibcon#read 5, iclass 3, count 0 2006.285.10:14:16.60#ibcon#about to read 6, iclass 3, count 0 2006.285.10:14:16.60#ibcon#read 6, iclass 3, count 0 2006.285.10:14:16.60#ibcon#end of sib2, iclass 3, count 0 2006.285.10:14:16.60#ibcon#*after write, iclass 3, count 0 2006.285.10:14:16.60#ibcon#*before return 0, iclass 3, count 0 2006.285.10:14:16.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:14:16.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:14:16.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:14:16.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:14:16.60$vck44/valo=3,564.99 2006.285.10:14:16.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.10:14:16.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.10:14:16.60#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:16.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:14:16.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:14:16.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:14:16.60#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:14:16.60#ibcon#first serial, iclass 5, count 0 2006.285.10:14:16.60#ibcon#enter sib2, iclass 5, count 0 2006.285.10:14:16.60#ibcon#flushed, iclass 5, count 0 2006.285.10:14:16.60#ibcon#about to write, iclass 5, count 0 2006.285.10:14:16.60#ibcon#wrote, iclass 5, count 0 2006.285.10:14:16.60#ibcon#about to read 3, iclass 5, count 0 2006.285.10:14:16.62#ibcon#read 3, iclass 5, count 0 2006.285.10:14:16.62#ibcon#about to read 4, iclass 5, count 0 2006.285.10:14:16.62#ibcon#read 4, iclass 5, count 0 2006.285.10:14:16.62#ibcon#about to read 5, iclass 5, count 0 2006.285.10:14:16.62#ibcon#read 5, iclass 5, count 0 2006.285.10:14:16.62#ibcon#about to read 6, iclass 5, count 0 2006.285.10:14:16.62#ibcon#read 6, iclass 5, count 0 2006.285.10:14:16.62#ibcon#end of sib2, iclass 5, count 0 2006.285.10:14:16.62#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:14:16.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:14:16.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:14:16.62#ibcon#*before write, iclass 5, count 0 2006.285.10:14:16.62#ibcon#enter sib2, iclass 5, count 0 2006.285.10:14:16.62#ibcon#flushed, iclass 5, count 0 2006.285.10:14:16.62#ibcon#about to write, iclass 5, count 0 2006.285.10:14:16.62#ibcon#wrote, iclass 5, count 0 2006.285.10:14:16.62#ibcon#about to read 3, iclass 5, count 0 2006.285.10:14:16.66#ibcon#read 3, iclass 5, count 0 2006.285.10:14:16.66#ibcon#about to read 4, iclass 5, count 0 2006.285.10:14:16.66#ibcon#read 4, iclass 5, count 0 2006.285.10:14:16.66#ibcon#about to read 5, iclass 5, count 0 2006.285.10:14:16.66#ibcon#read 5, iclass 5, count 0 2006.285.10:14:16.66#ibcon#about to read 6, iclass 5, count 0 2006.285.10:14:16.66#ibcon#read 6, iclass 5, count 0 2006.285.10:14:16.66#ibcon#end of sib2, iclass 5, count 0 2006.285.10:14:16.66#ibcon#*after write, iclass 5, count 0 2006.285.10:14:16.66#ibcon#*before return 0, iclass 5, count 0 2006.285.10:14:16.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:14:16.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:14:16.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:14:16.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:14:16.66$vck44/va=3,7 2006.285.10:14:16.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.10:14:16.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.10:14:16.66#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:16.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:14:16.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:14:16.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:14:16.72#ibcon#enter wrdev, iclass 7, count 2 2006.285.10:14:16.72#ibcon#first serial, iclass 7, count 2 2006.285.10:14:16.72#ibcon#enter sib2, iclass 7, count 2 2006.285.10:14:16.72#ibcon#flushed, iclass 7, count 2 2006.285.10:14:16.72#ibcon#about to write, iclass 7, count 2 2006.285.10:14:16.72#ibcon#wrote, iclass 7, count 2 2006.285.10:14:16.72#ibcon#about to read 3, iclass 7, count 2 2006.285.10:14:16.74#ibcon#read 3, iclass 7, count 2 2006.285.10:14:16.74#ibcon#about to read 4, iclass 7, count 2 2006.285.10:14:16.74#ibcon#read 4, iclass 7, count 2 2006.285.10:14:16.74#ibcon#about to read 5, iclass 7, count 2 2006.285.10:14:16.74#ibcon#read 5, iclass 7, count 2 2006.285.10:14:16.74#ibcon#about to read 6, iclass 7, count 2 2006.285.10:14:16.74#ibcon#read 6, iclass 7, count 2 2006.285.10:14:16.74#ibcon#end of sib2, iclass 7, count 2 2006.285.10:14:16.74#ibcon#*mode == 0, iclass 7, count 2 2006.285.10:14:16.74#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.10:14:16.74#ibcon#[25=AT03-07\r\n] 2006.285.10:14:16.74#ibcon#*before write, iclass 7, count 2 2006.285.10:14:16.74#ibcon#enter sib2, iclass 7, count 2 2006.285.10:14:16.74#ibcon#flushed, iclass 7, count 2 2006.285.10:14:16.74#ibcon#about to write, iclass 7, count 2 2006.285.10:14:16.74#ibcon#wrote, iclass 7, count 2 2006.285.10:14:16.74#ibcon#about to read 3, iclass 7, count 2 2006.285.10:14:16.77#ibcon#read 3, iclass 7, count 2 2006.285.10:14:16.77#ibcon#about to read 4, iclass 7, count 2 2006.285.10:14:16.77#ibcon#read 4, iclass 7, count 2 2006.285.10:14:16.77#ibcon#about to read 5, iclass 7, count 2 2006.285.10:14:16.77#ibcon#read 5, iclass 7, count 2 2006.285.10:14:16.77#ibcon#about to read 6, iclass 7, count 2 2006.285.10:14:16.77#ibcon#read 6, iclass 7, count 2 2006.285.10:14:16.77#ibcon#end of sib2, iclass 7, count 2 2006.285.10:14:16.77#ibcon#*after write, iclass 7, count 2 2006.285.10:14:16.77#ibcon#*before return 0, iclass 7, count 2 2006.285.10:14:16.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:14:16.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:14:16.77#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.10:14:16.77#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:16.77#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:14:16.89#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:14:16.89#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:14:16.89#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:14:16.89#ibcon#first serial, iclass 7, count 0 2006.285.10:14:16.89#ibcon#enter sib2, iclass 7, count 0 2006.285.10:14:16.89#ibcon#flushed, iclass 7, count 0 2006.285.10:14:16.89#ibcon#about to write, iclass 7, count 0 2006.285.10:14:16.89#ibcon#wrote, iclass 7, count 0 2006.285.10:14:16.89#ibcon#about to read 3, iclass 7, count 0 2006.285.10:14:16.91#ibcon#read 3, iclass 7, count 0 2006.285.10:14:16.91#ibcon#about to read 4, iclass 7, count 0 2006.285.10:14:16.91#ibcon#read 4, iclass 7, count 0 2006.285.10:14:16.91#ibcon#about to read 5, iclass 7, count 0 2006.285.10:14:16.91#ibcon#read 5, iclass 7, count 0 2006.285.10:14:16.91#ibcon#about to read 6, iclass 7, count 0 2006.285.10:14:16.91#ibcon#read 6, iclass 7, count 0 2006.285.10:14:16.91#ibcon#end of sib2, iclass 7, count 0 2006.285.10:14:16.91#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:14:16.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:14:16.91#ibcon#[25=USB\r\n] 2006.285.10:14:16.91#ibcon#*before write, iclass 7, count 0 2006.285.10:14:16.91#ibcon#enter sib2, iclass 7, count 0 2006.285.10:14:16.91#ibcon#flushed, iclass 7, count 0 2006.285.10:14:16.91#ibcon#about to write, iclass 7, count 0 2006.285.10:14:16.91#ibcon#wrote, iclass 7, count 0 2006.285.10:14:16.91#ibcon#about to read 3, iclass 7, count 0 2006.285.10:14:16.94#ibcon#read 3, iclass 7, count 0 2006.285.10:14:16.94#ibcon#about to read 4, iclass 7, count 0 2006.285.10:14:16.94#ibcon#read 4, iclass 7, count 0 2006.285.10:14:16.94#ibcon#about to read 5, iclass 7, count 0 2006.285.10:14:16.94#ibcon#read 5, iclass 7, count 0 2006.285.10:14:16.94#ibcon#about to read 6, iclass 7, count 0 2006.285.10:14:16.94#ibcon#read 6, iclass 7, count 0 2006.285.10:14:16.94#ibcon#end of sib2, iclass 7, count 0 2006.285.10:14:16.94#ibcon#*after write, iclass 7, count 0 2006.285.10:14:16.94#ibcon#*before return 0, iclass 7, count 0 2006.285.10:14:16.94#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:14:16.94#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:14:16.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:14:16.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:14:16.94$vck44/valo=4,624.99 2006.285.10:14:16.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.10:14:16.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.10:14:16.94#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:16.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:14:16.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:14:16.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:14:16.94#ibcon#enter wrdev, iclass 11, count 0 2006.285.10:14:16.94#ibcon#first serial, iclass 11, count 0 2006.285.10:14:16.94#ibcon#enter sib2, iclass 11, count 0 2006.285.10:14:16.94#ibcon#flushed, iclass 11, count 0 2006.285.10:14:16.94#ibcon#about to write, iclass 11, count 0 2006.285.10:14:16.94#ibcon#wrote, iclass 11, count 0 2006.285.10:14:16.94#ibcon#about to read 3, iclass 11, count 0 2006.285.10:14:16.96#ibcon#read 3, iclass 11, count 0 2006.285.10:14:16.96#ibcon#about to read 4, iclass 11, count 0 2006.285.10:14:16.96#ibcon#read 4, iclass 11, count 0 2006.285.10:14:16.96#ibcon#about to read 5, iclass 11, count 0 2006.285.10:14:16.96#ibcon#read 5, iclass 11, count 0 2006.285.10:14:16.96#ibcon#about to read 6, iclass 11, count 0 2006.285.10:14:16.96#ibcon#read 6, iclass 11, count 0 2006.285.10:14:16.96#ibcon#end of sib2, iclass 11, count 0 2006.285.10:14:16.96#ibcon#*mode == 0, iclass 11, count 0 2006.285.10:14:16.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.10:14:16.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:14:16.96#ibcon#*before write, iclass 11, count 0 2006.285.10:14:16.96#ibcon#enter sib2, iclass 11, count 0 2006.285.10:14:16.96#ibcon#flushed, iclass 11, count 0 2006.285.10:14:16.96#ibcon#about to write, iclass 11, count 0 2006.285.10:14:16.96#ibcon#wrote, iclass 11, count 0 2006.285.10:14:16.96#ibcon#about to read 3, iclass 11, count 0 2006.285.10:14:17.00#ibcon#read 3, iclass 11, count 0 2006.285.10:14:17.00#ibcon#about to read 4, iclass 11, count 0 2006.285.10:14:17.00#ibcon#read 4, iclass 11, count 0 2006.285.10:14:17.00#ibcon#about to read 5, iclass 11, count 0 2006.285.10:14:17.00#ibcon#read 5, iclass 11, count 0 2006.285.10:14:17.00#ibcon#about to read 6, iclass 11, count 0 2006.285.10:14:17.00#ibcon#read 6, iclass 11, count 0 2006.285.10:14:17.00#ibcon#end of sib2, iclass 11, count 0 2006.285.10:14:17.00#ibcon#*after write, iclass 11, count 0 2006.285.10:14:17.00#ibcon#*before return 0, iclass 11, count 0 2006.285.10:14:17.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:14:17.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:14:17.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.10:14:17.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.10:14:17.00$vck44/va=4,6 2006.285.10:14:17.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.10:14:17.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.10:14:17.00#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:17.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:14:17.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:14:17.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:14:17.06#ibcon#enter wrdev, iclass 13, count 2 2006.285.10:14:17.06#ibcon#first serial, iclass 13, count 2 2006.285.10:14:17.06#ibcon#enter sib2, iclass 13, count 2 2006.285.10:14:17.06#ibcon#flushed, iclass 13, count 2 2006.285.10:14:17.06#ibcon#about to write, iclass 13, count 2 2006.285.10:14:17.06#ibcon#wrote, iclass 13, count 2 2006.285.10:14:17.06#ibcon#about to read 3, iclass 13, count 2 2006.285.10:14:17.08#ibcon#read 3, iclass 13, count 2 2006.285.10:14:17.08#ibcon#about to read 4, iclass 13, count 2 2006.285.10:14:17.08#ibcon#read 4, iclass 13, count 2 2006.285.10:14:17.08#ibcon#about to read 5, iclass 13, count 2 2006.285.10:14:17.08#ibcon#read 5, iclass 13, count 2 2006.285.10:14:17.08#ibcon#about to read 6, iclass 13, count 2 2006.285.10:14:17.08#ibcon#read 6, iclass 13, count 2 2006.285.10:14:17.08#ibcon#end of sib2, iclass 13, count 2 2006.285.10:14:17.08#ibcon#*mode == 0, iclass 13, count 2 2006.285.10:14:17.08#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.10:14:17.08#ibcon#[25=AT04-06\r\n] 2006.285.10:14:17.08#ibcon#*before write, iclass 13, count 2 2006.285.10:14:17.08#ibcon#enter sib2, iclass 13, count 2 2006.285.10:14:17.08#ibcon#flushed, iclass 13, count 2 2006.285.10:14:17.08#ibcon#about to write, iclass 13, count 2 2006.285.10:14:17.08#ibcon#wrote, iclass 13, count 2 2006.285.10:14:17.08#ibcon#about to read 3, iclass 13, count 2 2006.285.10:14:17.11#ibcon#read 3, iclass 13, count 2 2006.285.10:14:17.11#ibcon#about to read 4, iclass 13, count 2 2006.285.10:14:17.11#ibcon#read 4, iclass 13, count 2 2006.285.10:14:17.11#ibcon#about to read 5, iclass 13, count 2 2006.285.10:14:17.11#ibcon#read 5, iclass 13, count 2 2006.285.10:14:17.11#ibcon#about to read 6, iclass 13, count 2 2006.285.10:14:17.11#ibcon#read 6, iclass 13, count 2 2006.285.10:14:17.11#ibcon#end of sib2, iclass 13, count 2 2006.285.10:14:17.11#ibcon#*after write, iclass 13, count 2 2006.285.10:14:17.11#ibcon#*before return 0, iclass 13, count 2 2006.285.10:14:17.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:14:17.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:14:17.11#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.10:14:17.11#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:17.11#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:14:17.17#abcon#<5=/04 1.4 2.0 19.70 911015.0\r\n> 2006.285.10:14:17.19#abcon#{5=INTERFACE CLEAR} 2006.285.10:14:17.23#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:14:17.23#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:14:17.23#ibcon#enter wrdev, iclass 13, count 0 2006.285.10:14:17.23#ibcon#first serial, iclass 13, count 0 2006.285.10:14:17.23#ibcon#enter sib2, iclass 13, count 0 2006.285.10:14:17.23#ibcon#flushed, iclass 13, count 0 2006.285.10:14:17.23#ibcon#about to write, iclass 13, count 0 2006.285.10:14:17.23#ibcon#wrote, iclass 13, count 0 2006.285.10:14:17.23#ibcon#about to read 3, iclass 13, count 0 2006.285.10:14:17.25#ibcon#read 3, iclass 13, count 0 2006.285.10:14:17.25#ibcon#about to read 4, iclass 13, count 0 2006.285.10:14:17.25#ibcon#read 4, iclass 13, count 0 2006.285.10:14:17.25#ibcon#about to read 5, iclass 13, count 0 2006.285.10:14:17.25#ibcon#read 5, iclass 13, count 0 2006.285.10:14:17.25#ibcon#about to read 6, iclass 13, count 0 2006.285.10:14:17.25#ibcon#read 6, iclass 13, count 0 2006.285.10:14:17.25#ibcon#end of sib2, iclass 13, count 0 2006.285.10:14:17.25#ibcon#*mode == 0, iclass 13, count 0 2006.285.10:14:17.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.10:14:17.25#ibcon#[25=USB\r\n] 2006.285.10:14:17.25#ibcon#*before write, iclass 13, count 0 2006.285.10:14:17.25#ibcon#enter sib2, iclass 13, count 0 2006.285.10:14:17.25#ibcon#flushed, iclass 13, count 0 2006.285.10:14:17.25#ibcon#about to write, iclass 13, count 0 2006.285.10:14:17.25#ibcon#wrote, iclass 13, count 0 2006.285.10:14:17.25#ibcon#about to read 3, iclass 13, count 0 2006.285.10:14:17.25#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:14:17.28#ibcon#read 3, iclass 13, count 0 2006.285.10:14:17.28#ibcon#about to read 4, iclass 13, count 0 2006.285.10:14:17.28#ibcon#read 4, iclass 13, count 0 2006.285.10:14:17.28#ibcon#about to read 5, iclass 13, count 0 2006.285.10:14:17.28#ibcon#read 5, iclass 13, count 0 2006.285.10:14:17.28#ibcon#about to read 6, iclass 13, count 0 2006.285.10:14:17.28#ibcon#read 6, iclass 13, count 0 2006.285.10:14:17.28#ibcon#end of sib2, iclass 13, count 0 2006.285.10:14:17.28#ibcon#*after write, iclass 13, count 0 2006.285.10:14:17.28#ibcon#*before return 0, iclass 13, count 0 2006.285.10:14:17.28#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:14:17.28#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:14:17.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.10:14:17.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.10:14:17.28$vck44/valo=5,734.99 2006.285.10:14:17.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.10:14:17.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.10:14:17.28#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:17.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:14:17.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:14:17.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:14:17.28#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:14:17.28#ibcon#first serial, iclass 19, count 0 2006.285.10:14:17.28#ibcon#enter sib2, iclass 19, count 0 2006.285.10:14:17.28#ibcon#flushed, iclass 19, count 0 2006.285.10:14:17.28#ibcon#about to write, iclass 19, count 0 2006.285.10:14:17.28#ibcon#wrote, iclass 19, count 0 2006.285.10:14:17.28#ibcon#about to read 3, iclass 19, count 0 2006.285.10:14:17.30#ibcon#read 3, iclass 19, count 0 2006.285.10:14:17.30#ibcon#about to read 4, iclass 19, count 0 2006.285.10:14:17.30#ibcon#read 4, iclass 19, count 0 2006.285.10:14:17.30#ibcon#about to read 5, iclass 19, count 0 2006.285.10:14:17.30#ibcon#read 5, iclass 19, count 0 2006.285.10:14:17.30#ibcon#about to read 6, iclass 19, count 0 2006.285.10:14:17.30#ibcon#read 6, iclass 19, count 0 2006.285.10:14:17.30#ibcon#end of sib2, iclass 19, count 0 2006.285.10:14:17.30#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:14:17.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:14:17.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:14:17.30#ibcon#*before write, iclass 19, count 0 2006.285.10:14:17.30#ibcon#enter sib2, iclass 19, count 0 2006.285.10:14:17.30#ibcon#flushed, iclass 19, count 0 2006.285.10:14:17.30#ibcon#about to write, iclass 19, count 0 2006.285.10:14:17.30#ibcon#wrote, iclass 19, count 0 2006.285.10:14:17.30#ibcon#about to read 3, iclass 19, count 0 2006.285.10:14:17.34#ibcon#read 3, iclass 19, count 0 2006.285.10:14:17.34#ibcon#about to read 4, iclass 19, count 0 2006.285.10:14:17.34#ibcon#read 4, iclass 19, count 0 2006.285.10:14:17.34#ibcon#about to read 5, iclass 19, count 0 2006.285.10:14:17.34#ibcon#read 5, iclass 19, count 0 2006.285.10:14:17.34#ibcon#about to read 6, iclass 19, count 0 2006.285.10:14:17.34#ibcon#read 6, iclass 19, count 0 2006.285.10:14:17.34#ibcon#end of sib2, iclass 19, count 0 2006.285.10:14:17.34#ibcon#*after write, iclass 19, count 0 2006.285.10:14:17.34#ibcon#*before return 0, iclass 19, count 0 2006.285.10:14:17.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:14:17.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:14:17.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:14:17.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:14:17.34$vck44/va=5,3 2006.285.10:14:17.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.10:14:17.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.10:14:17.34#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:17.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:14:17.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:14:17.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:14:17.40#ibcon#enter wrdev, iclass 21, count 2 2006.285.10:14:17.40#ibcon#first serial, iclass 21, count 2 2006.285.10:14:17.40#ibcon#enter sib2, iclass 21, count 2 2006.285.10:14:17.40#ibcon#flushed, iclass 21, count 2 2006.285.10:14:17.40#ibcon#about to write, iclass 21, count 2 2006.285.10:14:17.40#ibcon#wrote, iclass 21, count 2 2006.285.10:14:17.40#ibcon#about to read 3, iclass 21, count 2 2006.285.10:14:17.42#ibcon#read 3, iclass 21, count 2 2006.285.10:14:17.42#ibcon#about to read 4, iclass 21, count 2 2006.285.10:14:17.42#ibcon#read 4, iclass 21, count 2 2006.285.10:14:17.42#ibcon#about to read 5, iclass 21, count 2 2006.285.10:14:17.42#ibcon#read 5, iclass 21, count 2 2006.285.10:14:17.42#ibcon#about to read 6, iclass 21, count 2 2006.285.10:14:17.42#ibcon#read 6, iclass 21, count 2 2006.285.10:14:17.42#ibcon#end of sib2, iclass 21, count 2 2006.285.10:14:17.42#ibcon#*mode == 0, iclass 21, count 2 2006.285.10:14:17.42#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.10:14:17.42#ibcon#[25=AT05-03\r\n] 2006.285.10:14:17.42#ibcon#*before write, iclass 21, count 2 2006.285.10:14:17.42#ibcon#enter sib2, iclass 21, count 2 2006.285.10:14:17.42#ibcon#flushed, iclass 21, count 2 2006.285.10:14:17.42#ibcon#about to write, iclass 21, count 2 2006.285.10:14:17.42#ibcon#wrote, iclass 21, count 2 2006.285.10:14:17.42#ibcon#about to read 3, iclass 21, count 2 2006.285.10:14:17.45#ibcon#read 3, iclass 21, count 2 2006.285.10:14:17.45#ibcon#about to read 4, iclass 21, count 2 2006.285.10:14:17.45#ibcon#read 4, iclass 21, count 2 2006.285.10:14:17.45#ibcon#about to read 5, iclass 21, count 2 2006.285.10:14:17.45#ibcon#read 5, iclass 21, count 2 2006.285.10:14:17.45#ibcon#about to read 6, iclass 21, count 2 2006.285.10:14:17.45#ibcon#read 6, iclass 21, count 2 2006.285.10:14:17.45#ibcon#end of sib2, iclass 21, count 2 2006.285.10:14:17.45#ibcon#*after write, iclass 21, count 2 2006.285.10:14:17.45#ibcon#*before return 0, iclass 21, count 2 2006.285.10:14:17.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:14:17.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:14:17.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.10:14:17.45#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:17.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:14:17.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:14:17.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:14:17.57#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:14:17.57#ibcon#first serial, iclass 21, count 0 2006.285.10:14:17.57#ibcon#enter sib2, iclass 21, count 0 2006.285.10:14:17.57#ibcon#flushed, iclass 21, count 0 2006.285.10:14:17.57#ibcon#about to write, iclass 21, count 0 2006.285.10:14:17.57#ibcon#wrote, iclass 21, count 0 2006.285.10:14:17.57#ibcon#about to read 3, iclass 21, count 0 2006.285.10:14:17.59#ibcon#read 3, iclass 21, count 0 2006.285.10:14:17.59#ibcon#about to read 4, iclass 21, count 0 2006.285.10:14:17.59#ibcon#read 4, iclass 21, count 0 2006.285.10:14:17.59#ibcon#about to read 5, iclass 21, count 0 2006.285.10:14:17.59#ibcon#read 5, iclass 21, count 0 2006.285.10:14:17.59#ibcon#about to read 6, iclass 21, count 0 2006.285.10:14:17.59#ibcon#read 6, iclass 21, count 0 2006.285.10:14:17.59#ibcon#end of sib2, iclass 21, count 0 2006.285.10:14:17.59#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:14:17.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:14:17.59#ibcon#[25=USB\r\n] 2006.285.10:14:17.59#ibcon#*before write, iclass 21, count 0 2006.285.10:14:17.59#ibcon#enter sib2, iclass 21, count 0 2006.285.10:14:17.59#ibcon#flushed, iclass 21, count 0 2006.285.10:14:17.59#ibcon#about to write, iclass 21, count 0 2006.285.10:14:17.59#ibcon#wrote, iclass 21, count 0 2006.285.10:14:17.59#ibcon#about to read 3, iclass 21, count 0 2006.285.10:14:17.62#ibcon#read 3, iclass 21, count 0 2006.285.10:14:17.62#ibcon#about to read 4, iclass 21, count 0 2006.285.10:14:17.62#ibcon#read 4, iclass 21, count 0 2006.285.10:14:17.62#ibcon#about to read 5, iclass 21, count 0 2006.285.10:14:17.62#ibcon#read 5, iclass 21, count 0 2006.285.10:14:17.62#ibcon#about to read 6, iclass 21, count 0 2006.285.10:14:17.62#ibcon#read 6, iclass 21, count 0 2006.285.10:14:17.62#ibcon#end of sib2, iclass 21, count 0 2006.285.10:14:17.62#ibcon#*after write, iclass 21, count 0 2006.285.10:14:17.62#ibcon#*before return 0, iclass 21, count 0 2006.285.10:14:17.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:14:17.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:14:17.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:14:17.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:14:17.62$vck44/valo=6,814.99 2006.285.10:14:17.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.10:14:17.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.10:14:17.62#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:17.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:14:17.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:14:17.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:14:17.62#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:14:17.62#ibcon#first serial, iclass 23, count 0 2006.285.10:14:17.62#ibcon#enter sib2, iclass 23, count 0 2006.285.10:14:17.62#ibcon#flushed, iclass 23, count 0 2006.285.10:14:17.62#ibcon#about to write, iclass 23, count 0 2006.285.10:14:17.62#ibcon#wrote, iclass 23, count 0 2006.285.10:14:17.62#ibcon#about to read 3, iclass 23, count 0 2006.285.10:14:17.64#ibcon#read 3, iclass 23, count 0 2006.285.10:14:17.64#ibcon#about to read 4, iclass 23, count 0 2006.285.10:14:17.64#ibcon#read 4, iclass 23, count 0 2006.285.10:14:17.64#ibcon#about to read 5, iclass 23, count 0 2006.285.10:14:17.64#ibcon#read 5, iclass 23, count 0 2006.285.10:14:17.64#ibcon#about to read 6, iclass 23, count 0 2006.285.10:14:17.64#ibcon#read 6, iclass 23, count 0 2006.285.10:14:17.64#ibcon#end of sib2, iclass 23, count 0 2006.285.10:14:17.64#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:14:17.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:14:17.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:14:17.64#ibcon#*before write, iclass 23, count 0 2006.285.10:14:17.64#ibcon#enter sib2, iclass 23, count 0 2006.285.10:14:17.64#ibcon#flushed, iclass 23, count 0 2006.285.10:14:17.64#ibcon#about to write, iclass 23, count 0 2006.285.10:14:17.64#ibcon#wrote, iclass 23, count 0 2006.285.10:14:17.64#ibcon#about to read 3, iclass 23, count 0 2006.285.10:14:17.68#ibcon#read 3, iclass 23, count 0 2006.285.10:14:17.68#ibcon#about to read 4, iclass 23, count 0 2006.285.10:14:17.68#ibcon#read 4, iclass 23, count 0 2006.285.10:14:17.68#ibcon#about to read 5, iclass 23, count 0 2006.285.10:14:17.68#ibcon#read 5, iclass 23, count 0 2006.285.10:14:17.68#ibcon#about to read 6, iclass 23, count 0 2006.285.10:14:17.68#ibcon#read 6, iclass 23, count 0 2006.285.10:14:17.68#ibcon#end of sib2, iclass 23, count 0 2006.285.10:14:17.68#ibcon#*after write, iclass 23, count 0 2006.285.10:14:17.68#ibcon#*before return 0, iclass 23, count 0 2006.285.10:14:17.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:14:17.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:14:17.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:14:17.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:14:17.68$vck44/va=6,4 2006.285.10:14:17.68#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.10:14:17.68#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.10:14:17.68#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:17.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:14:17.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:14:17.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:14:17.74#ibcon#enter wrdev, iclass 25, count 2 2006.285.10:14:17.74#ibcon#first serial, iclass 25, count 2 2006.285.10:14:17.74#ibcon#enter sib2, iclass 25, count 2 2006.285.10:14:17.74#ibcon#flushed, iclass 25, count 2 2006.285.10:14:17.74#ibcon#about to write, iclass 25, count 2 2006.285.10:14:17.74#ibcon#wrote, iclass 25, count 2 2006.285.10:14:17.74#ibcon#about to read 3, iclass 25, count 2 2006.285.10:14:17.76#ibcon#read 3, iclass 25, count 2 2006.285.10:14:17.76#ibcon#about to read 4, iclass 25, count 2 2006.285.10:14:17.76#ibcon#read 4, iclass 25, count 2 2006.285.10:14:17.76#ibcon#about to read 5, iclass 25, count 2 2006.285.10:14:17.76#ibcon#read 5, iclass 25, count 2 2006.285.10:14:17.76#ibcon#about to read 6, iclass 25, count 2 2006.285.10:14:17.76#ibcon#read 6, iclass 25, count 2 2006.285.10:14:17.76#ibcon#end of sib2, iclass 25, count 2 2006.285.10:14:17.76#ibcon#*mode == 0, iclass 25, count 2 2006.285.10:14:17.76#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.10:14:17.76#ibcon#[25=AT06-04\r\n] 2006.285.10:14:17.76#ibcon#*before write, iclass 25, count 2 2006.285.10:14:17.76#ibcon#enter sib2, iclass 25, count 2 2006.285.10:14:17.76#ibcon#flushed, iclass 25, count 2 2006.285.10:14:17.76#ibcon#about to write, iclass 25, count 2 2006.285.10:14:17.76#ibcon#wrote, iclass 25, count 2 2006.285.10:14:17.76#ibcon#about to read 3, iclass 25, count 2 2006.285.10:14:17.79#ibcon#read 3, iclass 25, count 2 2006.285.10:14:17.79#ibcon#about to read 4, iclass 25, count 2 2006.285.10:14:17.79#ibcon#read 4, iclass 25, count 2 2006.285.10:14:17.79#ibcon#about to read 5, iclass 25, count 2 2006.285.10:14:17.79#ibcon#read 5, iclass 25, count 2 2006.285.10:14:17.79#ibcon#about to read 6, iclass 25, count 2 2006.285.10:14:17.79#ibcon#read 6, iclass 25, count 2 2006.285.10:14:17.79#ibcon#end of sib2, iclass 25, count 2 2006.285.10:14:17.79#ibcon#*after write, iclass 25, count 2 2006.285.10:14:17.79#ibcon#*before return 0, iclass 25, count 2 2006.285.10:14:17.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:14:17.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:14:17.79#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.10:14:17.79#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:17.79#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:14:17.91#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:14:17.91#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:14:17.91#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:14:17.91#ibcon#first serial, iclass 25, count 0 2006.285.10:14:17.91#ibcon#enter sib2, iclass 25, count 0 2006.285.10:14:17.91#ibcon#flushed, iclass 25, count 0 2006.285.10:14:17.91#ibcon#about to write, iclass 25, count 0 2006.285.10:14:17.91#ibcon#wrote, iclass 25, count 0 2006.285.10:14:17.91#ibcon#about to read 3, iclass 25, count 0 2006.285.10:14:17.93#ibcon#read 3, iclass 25, count 0 2006.285.10:14:17.93#ibcon#about to read 4, iclass 25, count 0 2006.285.10:14:17.93#ibcon#read 4, iclass 25, count 0 2006.285.10:14:17.93#ibcon#about to read 5, iclass 25, count 0 2006.285.10:14:17.93#ibcon#read 5, iclass 25, count 0 2006.285.10:14:17.93#ibcon#about to read 6, iclass 25, count 0 2006.285.10:14:17.93#ibcon#read 6, iclass 25, count 0 2006.285.10:14:17.93#ibcon#end of sib2, iclass 25, count 0 2006.285.10:14:17.93#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:14:17.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:14:17.93#ibcon#[25=USB\r\n] 2006.285.10:14:17.93#ibcon#*before write, iclass 25, count 0 2006.285.10:14:17.93#ibcon#enter sib2, iclass 25, count 0 2006.285.10:14:17.93#ibcon#flushed, iclass 25, count 0 2006.285.10:14:17.93#ibcon#about to write, iclass 25, count 0 2006.285.10:14:17.93#ibcon#wrote, iclass 25, count 0 2006.285.10:14:17.93#ibcon#about to read 3, iclass 25, count 0 2006.285.10:14:17.96#ibcon#read 3, iclass 25, count 0 2006.285.10:14:17.96#ibcon#about to read 4, iclass 25, count 0 2006.285.10:14:17.96#ibcon#read 4, iclass 25, count 0 2006.285.10:14:17.96#ibcon#about to read 5, iclass 25, count 0 2006.285.10:14:17.96#ibcon#read 5, iclass 25, count 0 2006.285.10:14:17.96#ibcon#about to read 6, iclass 25, count 0 2006.285.10:14:17.96#ibcon#read 6, iclass 25, count 0 2006.285.10:14:17.96#ibcon#end of sib2, iclass 25, count 0 2006.285.10:14:17.96#ibcon#*after write, iclass 25, count 0 2006.285.10:14:17.96#ibcon#*before return 0, iclass 25, count 0 2006.285.10:14:17.96#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:14:17.96#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:14:17.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:14:17.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:14:17.96$vck44/valo=7,864.99 2006.285.10:14:17.96#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.10:14:17.96#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.10:14:17.96#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:17.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:14:17.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:14:17.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:14:17.96#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:14:17.96#ibcon#first serial, iclass 27, count 0 2006.285.10:14:17.96#ibcon#enter sib2, iclass 27, count 0 2006.285.10:14:17.96#ibcon#flushed, iclass 27, count 0 2006.285.10:14:17.96#ibcon#about to write, iclass 27, count 0 2006.285.10:14:17.96#ibcon#wrote, iclass 27, count 0 2006.285.10:14:17.96#ibcon#about to read 3, iclass 27, count 0 2006.285.10:14:17.98#ibcon#read 3, iclass 27, count 0 2006.285.10:14:17.98#ibcon#about to read 4, iclass 27, count 0 2006.285.10:14:17.98#ibcon#read 4, iclass 27, count 0 2006.285.10:14:17.98#ibcon#about to read 5, iclass 27, count 0 2006.285.10:14:17.98#ibcon#read 5, iclass 27, count 0 2006.285.10:14:17.98#ibcon#about to read 6, iclass 27, count 0 2006.285.10:14:17.98#ibcon#read 6, iclass 27, count 0 2006.285.10:14:17.98#ibcon#end of sib2, iclass 27, count 0 2006.285.10:14:17.98#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:14:17.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:14:17.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:14:17.98#ibcon#*before write, iclass 27, count 0 2006.285.10:14:17.98#ibcon#enter sib2, iclass 27, count 0 2006.285.10:14:17.98#ibcon#flushed, iclass 27, count 0 2006.285.10:14:17.98#ibcon#about to write, iclass 27, count 0 2006.285.10:14:17.98#ibcon#wrote, iclass 27, count 0 2006.285.10:14:17.98#ibcon#about to read 3, iclass 27, count 0 2006.285.10:14:18.02#ibcon#read 3, iclass 27, count 0 2006.285.10:14:18.02#ibcon#about to read 4, iclass 27, count 0 2006.285.10:14:18.02#ibcon#read 4, iclass 27, count 0 2006.285.10:14:18.02#ibcon#about to read 5, iclass 27, count 0 2006.285.10:14:18.02#ibcon#read 5, iclass 27, count 0 2006.285.10:14:18.02#ibcon#about to read 6, iclass 27, count 0 2006.285.10:14:18.02#ibcon#read 6, iclass 27, count 0 2006.285.10:14:18.02#ibcon#end of sib2, iclass 27, count 0 2006.285.10:14:18.02#ibcon#*after write, iclass 27, count 0 2006.285.10:14:18.02#ibcon#*before return 0, iclass 27, count 0 2006.285.10:14:18.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:14:18.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:14:18.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:14:18.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:14:18.02$vck44/va=7,4 2006.285.10:14:18.02#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.10:14:18.02#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.10:14:18.02#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:18.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:14:18.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:14:18.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:14:18.08#ibcon#enter wrdev, iclass 29, count 2 2006.285.10:14:18.08#ibcon#first serial, iclass 29, count 2 2006.285.10:14:18.08#ibcon#enter sib2, iclass 29, count 2 2006.285.10:14:18.08#ibcon#flushed, iclass 29, count 2 2006.285.10:14:18.08#ibcon#about to write, iclass 29, count 2 2006.285.10:14:18.08#ibcon#wrote, iclass 29, count 2 2006.285.10:14:18.08#ibcon#about to read 3, iclass 29, count 2 2006.285.10:14:18.10#ibcon#read 3, iclass 29, count 2 2006.285.10:14:18.10#ibcon#about to read 4, iclass 29, count 2 2006.285.10:14:18.10#ibcon#read 4, iclass 29, count 2 2006.285.10:14:18.10#ibcon#about to read 5, iclass 29, count 2 2006.285.10:14:18.10#ibcon#read 5, iclass 29, count 2 2006.285.10:14:18.10#ibcon#about to read 6, iclass 29, count 2 2006.285.10:14:18.10#ibcon#read 6, iclass 29, count 2 2006.285.10:14:18.10#ibcon#end of sib2, iclass 29, count 2 2006.285.10:14:18.10#ibcon#*mode == 0, iclass 29, count 2 2006.285.10:14:18.10#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.10:14:18.10#ibcon#[25=AT07-04\r\n] 2006.285.10:14:18.10#ibcon#*before write, iclass 29, count 2 2006.285.10:14:18.10#ibcon#enter sib2, iclass 29, count 2 2006.285.10:14:18.10#ibcon#flushed, iclass 29, count 2 2006.285.10:14:18.10#ibcon#about to write, iclass 29, count 2 2006.285.10:14:18.10#ibcon#wrote, iclass 29, count 2 2006.285.10:14:18.10#ibcon#about to read 3, iclass 29, count 2 2006.285.10:14:18.13#ibcon#read 3, iclass 29, count 2 2006.285.10:14:18.13#ibcon#about to read 4, iclass 29, count 2 2006.285.10:14:18.13#ibcon#read 4, iclass 29, count 2 2006.285.10:14:18.13#ibcon#about to read 5, iclass 29, count 2 2006.285.10:14:18.13#ibcon#read 5, iclass 29, count 2 2006.285.10:14:18.13#ibcon#about to read 6, iclass 29, count 2 2006.285.10:14:18.13#ibcon#read 6, iclass 29, count 2 2006.285.10:14:18.13#ibcon#end of sib2, iclass 29, count 2 2006.285.10:14:18.13#ibcon#*after write, iclass 29, count 2 2006.285.10:14:18.13#ibcon#*before return 0, iclass 29, count 2 2006.285.10:14:18.13#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:14:18.13#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:14:18.13#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.10:14:18.13#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:18.13#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:14:18.25#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:14:18.25#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:14:18.25#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:14:18.25#ibcon#first serial, iclass 29, count 0 2006.285.10:14:18.25#ibcon#enter sib2, iclass 29, count 0 2006.285.10:14:18.25#ibcon#flushed, iclass 29, count 0 2006.285.10:14:18.25#ibcon#about to write, iclass 29, count 0 2006.285.10:14:18.25#ibcon#wrote, iclass 29, count 0 2006.285.10:14:18.25#ibcon#about to read 3, iclass 29, count 0 2006.285.10:14:18.27#ibcon#read 3, iclass 29, count 0 2006.285.10:14:18.27#ibcon#about to read 4, iclass 29, count 0 2006.285.10:14:18.27#ibcon#read 4, iclass 29, count 0 2006.285.10:14:18.27#ibcon#about to read 5, iclass 29, count 0 2006.285.10:14:18.27#ibcon#read 5, iclass 29, count 0 2006.285.10:14:18.27#ibcon#about to read 6, iclass 29, count 0 2006.285.10:14:18.27#ibcon#read 6, iclass 29, count 0 2006.285.10:14:18.27#ibcon#end of sib2, iclass 29, count 0 2006.285.10:14:18.27#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:14:18.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:14:18.27#ibcon#[25=USB\r\n] 2006.285.10:14:18.27#ibcon#*before write, iclass 29, count 0 2006.285.10:14:18.27#ibcon#enter sib2, iclass 29, count 0 2006.285.10:14:18.27#ibcon#flushed, iclass 29, count 0 2006.285.10:14:18.27#ibcon#about to write, iclass 29, count 0 2006.285.10:14:18.27#ibcon#wrote, iclass 29, count 0 2006.285.10:14:18.27#ibcon#about to read 3, iclass 29, count 0 2006.285.10:14:18.30#ibcon#read 3, iclass 29, count 0 2006.285.10:14:18.30#ibcon#about to read 4, iclass 29, count 0 2006.285.10:14:18.30#ibcon#read 4, iclass 29, count 0 2006.285.10:14:18.30#ibcon#about to read 5, iclass 29, count 0 2006.285.10:14:18.30#ibcon#read 5, iclass 29, count 0 2006.285.10:14:18.30#ibcon#about to read 6, iclass 29, count 0 2006.285.10:14:18.30#ibcon#read 6, iclass 29, count 0 2006.285.10:14:18.30#ibcon#end of sib2, iclass 29, count 0 2006.285.10:14:18.30#ibcon#*after write, iclass 29, count 0 2006.285.10:14:18.30#ibcon#*before return 0, iclass 29, count 0 2006.285.10:14:18.30#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:14:18.30#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:14:18.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:14:18.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:14:18.30$vck44/valo=8,884.99 2006.285.10:14:18.30#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.10:14:18.30#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.10:14:18.30#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:18.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:14:18.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:14:18.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:14:18.30#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:14:18.30#ibcon#first serial, iclass 31, count 0 2006.285.10:14:18.30#ibcon#enter sib2, iclass 31, count 0 2006.285.10:14:18.30#ibcon#flushed, iclass 31, count 0 2006.285.10:14:18.30#ibcon#about to write, iclass 31, count 0 2006.285.10:14:18.30#ibcon#wrote, iclass 31, count 0 2006.285.10:14:18.30#ibcon#about to read 3, iclass 31, count 0 2006.285.10:14:18.32#ibcon#read 3, iclass 31, count 0 2006.285.10:14:18.32#ibcon#about to read 4, iclass 31, count 0 2006.285.10:14:18.32#ibcon#read 4, iclass 31, count 0 2006.285.10:14:18.32#ibcon#about to read 5, iclass 31, count 0 2006.285.10:14:18.32#ibcon#read 5, iclass 31, count 0 2006.285.10:14:18.32#ibcon#about to read 6, iclass 31, count 0 2006.285.10:14:18.32#ibcon#read 6, iclass 31, count 0 2006.285.10:14:18.32#ibcon#end of sib2, iclass 31, count 0 2006.285.10:14:18.32#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:14:18.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:14:18.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:14:18.32#ibcon#*before write, iclass 31, count 0 2006.285.10:14:18.32#ibcon#enter sib2, iclass 31, count 0 2006.285.10:14:18.32#ibcon#flushed, iclass 31, count 0 2006.285.10:14:18.32#ibcon#about to write, iclass 31, count 0 2006.285.10:14:18.32#ibcon#wrote, iclass 31, count 0 2006.285.10:14:18.32#ibcon#about to read 3, iclass 31, count 0 2006.285.10:14:18.36#ibcon#read 3, iclass 31, count 0 2006.285.10:14:18.36#ibcon#about to read 4, iclass 31, count 0 2006.285.10:14:18.36#ibcon#read 4, iclass 31, count 0 2006.285.10:14:18.36#ibcon#about to read 5, iclass 31, count 0 2006.285.10:14:18.36#ibcon#read 5, iclass 31, count 0 2006.285.10:14:18.36#ibcon#about to read 6, iclass 31, count 0 2006.285.10:14:18.36#ibcon#read 6, iclass 31, count 0 2006.285.10:14:18.36#ibcon#end of sib2, iclass 31, count 0 2006.285.10:14:18.36#ibcon#*after write, iclass 31, count 0 2006.285.10:14:18.36#ibcon#*before return 0, iclass 31, count 0 2006.285.10:14:18.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:14:18.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:14:18.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:14:18.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:14:18.36$vck44/va=8,3 2006.285.10:14:18.36#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.10:14:18.36#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.10:14:18.36#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:18.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:14:18.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:14:18.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:14:18.42#ibcon#enter wrdev, iclass 33, count 2 2006.285.10:14:18.42#ibcon#first serial, iclass 33, count 2 2006.285.10:14:18.42#ibcon#enter sib2, iclass 33, count 2 2006.285.10:14:18.42#ibcon#flushed, iclass 33, count 2 2006.285.10:14:18.42#ibcon#about to write, iclass 33, count 2 2006.285.10:14:18.42#ibcon#wrote, iclass 33, count 2 2006.285.10:14:18.42#ibcon#about to read 3, iclass 33, count 2 2006.285.10:14:18.44#ibcon#read 3, iclass 33, count 2 2006.285.10:14:18.44#ibcon#about to read 4, iclass 33, count 2 2006.285.10:14:18.44#ibcon#read 4, iclass 33, count 2 2006.285.10:14:18.44#ibcon#about to read 5, iclass 33, count 2 2006.285.10:14:18.44#ibcon#read 5, iclass 33, count 2 2006.285.10:14:18.44#ibcon#about to read 6, iclass 33, count 2 2006.285.10:14:18.44#ibcon#read 6, iclass 33, count 2 2006.285.10:14:18.44#ibcon#end of sib2, iclass 33, count 2 2006.285.10:14:18.44#ibcon#*mode == 0, iclass 33, count 2 2006.285.10:14:18.44#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.10:14:18.44#ibcon#[25=AT08-03\r\n] 2006.285.10:14:18.44#ibcon#*before write, iclass 33, count 2 2006.285.10:14:18.44#ibcon#enter sib2, iclass 33, count 2 2006.285.10:14:18.44#ibcon#flushed, iclass 33, count 2 2006.285.10:14:18.44#ibcon#about to write, iclass 33, count 2 2006.285.10:14:18.44#ibcon#wrote, iclass 33, count 2 2006.285.10:14:18.44#ibcon#about to read 3, iclass 33, count 2 2006.285.10:14:18.47#ibcon#read 3, iclass 33, count 2 2006.285.10:14:18.47#ibcon#about to read 4, iclass 33, count 2 2006.285.10:14:18.47#ibcon#read 4, iclass 33, count 2 2006.285.10:14:18.47#ibcon#about to read 5, iclass 33, count 2 2006.285.10:14:18.47#ibcon#read 5, iclass 33, count 2 2006.285.10:14:18.47#ibcon#about to read 6, iclass 33, count 2 2006.285.10:14:18.47#ibcon#read 6, iclass 33, count 2 2006.285.10:14:18.47#ibcon#end of sib2, iclass 33, count 2 2006.285.10:14:18.47#ibcon#*after write, iclass 33, count 2 2006.285.10:14:18.47#ibcon#*before return 0, iclass 33, count 2 2006.285.10:14:18.47#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:14:18.47#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:14:18.47#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.10:14:18.47#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:18.47#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:14:18.59#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:14:18.59#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:14:18.59#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:14:18.59#ibcon#first serial, iclass 33, count 0 2006.285.10:14:18.59#ibcon#enter sib2, iclass 33, count 0 2006.285.10:14:18.59#ibcon#flushed, iclass 33, count 0 2006.285.10:14:18.59#ibcon#about to write, iclass 33, count 0 2006.285.10:14:18.59#ibcon#wrote, iclass 33, count 0 2006.285.10:14:18.59#ibcon#about to read 3, iclass 33, count 0 2006.285.10:14:18.61#ibcon#read 3, iclass 33, count 0 2006.285.10:14:18.61#ibcon#about to read 4, iclass 33, count 0 2006.285.10:14:18.61#ibcon#read 4, iclass 33, count 0 2006.285.10:14:18.61#ibcon#about to read 5, iclass 33, count 0 2006.285.10:14:18.61#ibcon#read 5, iclass 33, count 0 2006.285.10:14:18.61#ibcon#about to read 6, iclass 33, count 0 2006.285.10:14:18.61#ibcon#read 6, iclass 33, count 0 2006.285.10:14:18.61#ibcon#end of sib2, iclass 33, count 0 2006.285.10:14:18.61#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:14:18.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:14:18.61#ibcon#[25=USB\r\n] 2006.285.10:14:18.61#ibcon#*before write, iclass 33, count 0 2006.285.10:14:18.61#ibcon#enter sib2, iclass 33, count 0 2006.285.10:14:18.61#ibcon#flushed, iclass 33, count 0 2006.285.10:14:18.61#ibcon#about to write, iclass 33, count 0 2006.285.10:14:18.61#ibcon#wrote, iclass 33, count 0 2006.285.10:14:18.61#ibcon#about to read 3, iclass 33, count 0 2006.285.10:14:18.64#ibcon#read 3, iclass 33, count 0 2006.285.10:14:18.64#ibcon#about to read 4, iclass 33, count 0 2006.285.10:14:18.64#ibcon#read 4, iclass 33, count 0 2006.285.10:14:18.64#ibcon#about to read 5, iclass 33, count 0 2006.285.10:14:18.64#ibcon#read 5, iclass 33, count 0 2006.285.10:14:18.64#ibcon#about to read 6, iclass 33, count 0 2006.285.10:14:18.64#ibcon#read 6, iclass 33, count 0 2006.285.10:14:18.64#ibcon#end of sib2, iclass 33, count 0 2006.285.10:14:18.64#ibcon#*after write, iclass 33, count 0 2006.285.10:14:18.64#ibcon#*before return 0, iclass 33, count 0 2006.285.10:14:18.64#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:14:18.64#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:14:18.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:14:18.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:14:18.64$vck44/vblo=1,629.99 2006.285.10:14:18.64#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.10:14:18.64#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.10:14:18.64#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:18.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:14:18.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:14:18.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:14:18.64#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:14:18.64#ibcon#first serial, iclass 35, count 0 2006.285.10:14:18.64#ibcon#enter sib2, iclass 35, count 0 2006.285.10:14:18.64#ibcon#flushed, iclass 35, count 0 2006.285.10:14:18.64#ibcon#about to write, iclass 35, count 0 2006.285.10:14:18.64#ibcon#wrote, iclass 35, count 0 2006.285.10:14:18.64#ibcon#about to read 3, iclass 35, count 0 2006.285.10:14:18.66#ibcon#read 3, iclass 35, count 0 2006.285.10:14:18.66#ibcon#about to read 4, iclass 35, count 0 2006.285.10:14:18.66#ibcon#read 4, iclass 35, count 0 2006.285.10:14:18.66#ibcon#about to read 5, iclass 35, count 0 2006.285.10:14:18.66#ibcon#read 5, iclass 35, count 0 2006.285.10:14:18.66#ibcon#about to read 6, iclass 35, count 0 2006.285.10:14:18.66#ibcon#read 6, iclass 35, count 0 2006.285.10:14:18.66#ibcon#end of sib2, iclass 35, count 0 2006.285.10:14:18.66#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:14:18.66#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:14:18.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:14:18.66#ibcon#*before write, iclass 35, count 0 2006.285.10:14:18.66#ibcon#enter sib2, iclass 35, count 0 2006.285.10:14:18.66#ibcon#flushed, iclass 35, count 0 2006.285.10:14:18.66#ibcon#about to write, iclass 35, count 0 2006.285.10:14:18.66#ibcon#wrote, iclass 35, count 0 2006.285.10:14:18.66#ibcon#about to read 3, iclass 35, count 0 2006.285.10:14:18.70#ibcon#read 3, iclass 35, count 0 2006.285.10:14:18.70#ibcon#about to read 4, iclass 35, count 0 2006.285.10:14:18.70#ibcon#read 4, iclass 35, count 0 2006.285.10:14:18.70#ibcon#about to read 5, iclass 35, count 0 2006.285.10:14:18.70#ibcon#read 5, iclass 35, count 0 2006.285.10:14:18.70#ibcon#about to read 6, iclass 35, count 0 2006.285.10:14:18.70#ibcon#read 6, iclass 35, count 0 2006.285.10:14:18.70#ibcon#end of sib2, iclass 35, count 0 2006.285.10:14:18.70#ibcon#*after write, iclass 35, count 0 2006.285.10:14:18.70#ibcon#*before return 0, iclass 35, count 0 2006.285.10:14:18.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:14:18.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:14:18.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:14:18.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:14:18.70$vck44/vb=1,4 2006.285.10:14:18.70#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.10:14:18.70#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.10:14:18.70#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:18.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:14:18.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:14:18.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:14:18.70#ibcon#enter wrdev, iclass 37, count 2 2006.285.10:14:18.70#ibcon#first serial, iclass 37, count 2 2006.285.10:14:18.70#ibcon#enter sib2, iclass 37, count 2 2006.285.10:14:18.70#ibcon#flushed, iclass 37, count 2 2006.285.10:14:18.70#ibcon#about to write, iclass 37, count 2 2006.285.10:14:18.70#ibcon#wrote, iclass 37, count 2 2006.285.10:14:18.70#ibcon#about to read 3, iclass 37, count 2 2006.285.10:14:18.72#ibcon#read 3, iclass 37, count 2 2006.285.10:14:18.72#ibcon#about to read 4, iclass 37, count 2 2006.285.10:14:18.72#ibcon#read 4, iclass 37, count 2 2006.285.10:14:18.72#ibcon#about to read 5, iclass 37, count 2 2006.285.10:14:18.72#ibcon#read 5, iclass 37, count 2 2006.285.10:14:18.72#ibcon#about to read 6, iclass 37, count 2 2006.285.10:14:18.72#ibcon#read 6, iclass 37, count 2 2006.285.10:14:18.72#ibcon#end of sib2, iclass 37, count 2 2006.285.10:14:18.72#ibcon#*mode == 0, iclass 37, count 2 2006.285.10:14:18.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.10:14:18.72#ibcon#[27=AT01-04\r\n] 2006.285.10:14:18.72#ibcon#*before write, iclass 37, count 2 2006.285.10:14:18.72#ibcon#enter sib2, iclass 37, count 2 2006.285.10:14:18.72#ibcon#flushed, iclass 37, count 2 2006.285.10:14:18.72#ibcon#about to write, iclass 37, count 2 2006.285.10:14:18.72#ibcon#wrote, iclass 37, count 2 2006.285.10:14:18.72#ibcon#about to read 3, iclass 37, count 2 2006.285.10:14:18.75#ibcon#read 3, iclass 37, count 2 2006.285.10:14:18.75#ibcon#about to read 4, iclass 37, count 2 2006.285.10:14:18.75#ibcon#read 4, iclass 37, count 2 2006.285.10:14:18.75#ibcon#about to read 5, iclass 37, count 2 2006.285.10:14:18.75#ibcon#read 5, iclass 37, count 2 2006.285.10:14:18.75#ibcon#about to read 6, iclass 37, count 2 2006.285.10:14:18.75#ibcon#read 6, iclass 37, count 2 2006.285.10:14:18.75#ibcon#end of sib2, iclass 37, count 2 2006.285.10:14:18.75#ibcon#*after write, iclass 37, count 2 2006.285.10:14:18.75#ibcon#*before return 0, iclass 37, count 2 2006.285.10:14:18.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:14:18.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:14:18.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.10:14:18.75#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:18.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:14:18.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:14:18.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:14:18.87#ibcon#enter wrdev, iclass 37, count 0 2006.285.10:14:18.87#ibcon#first serial, iclass 37, count 0 2006.285.10:14:18.87#ibcon#enter sib2, iclass 37, count 0 2006.285.10:14:18.87#ibcon#flushed, iclass 37, count 0 2006.285.10:14:18.87#ibcon#about to write, iclass 37, count 0 2006.285.10:14:18.87#ibcon#wrote, iclass 37, count 0 2006.285.10:14:18.87#ibcon#about to read 3, iclass 37, count 0 2006.285.10:14:18.89#ibcon#read 3, iclass 37, count 0 2006.285.10:14:18.89#ibcon#about to read 4, iclass 37, count 0 2006.285.10:14:18.89#ibcon#read 4, iclass 37, count 0 2006.285.10:14:18.89#ibcon#about to read 5, iclass 37, count 0 2006.285.10:14:18.89#ibcon#read 5, iclass 37, count 0 2006.285.10:14:18.89#ibcon#about to read 6, iclass 37, count 0 2006.285.10:14:18.89#ibcon#read 6, iclass 37, count 0 2006.285.10:14:18.89#ibcon#end of sib2, iclass 37, count 0 2006.285.10:14:18.89#ibcon#*mode == 0, iclass 37, count 0 2006.285.10:14:18.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.10:14:18.89#ibcon#[27=USB\r\n] 2006.285.10:14:18.89#ibcon#*before write, iclass 37, count 0 2006.285.10:14:18.89#ibcon#enter sib2, iclass 37, count 0 2006.285.10:14:18.89#ibcon#flushed, iclass 37, count 0 2006.285.10:14:18.89#ibcon#about to write, iclass 37, count 0 2006.285.10:14:18.89#ibcon#wrote, iclass 37, count 0 2006.285.10:14:18.89#ibcon#about to read 3, iclass 37, count 0 2006.285.10:14:18.92#ibcon#read 3, iclass 37, count 0 2006.285.10:14:18.92#ibcon#about to read 4, iclass 37, count 0 2006.285.10:14:18.92#ibcon#read 4, iclass 37, count 0 2006.285.10:14:18.92#ibcon#about to read 5, iclass 37, count 0 2006.285.10:14:18.92#ibcon#read 5, iclass 37, count 0 2006.285.10:14:18.92#ibcon#about to read 6, iclass 37, count 0 2006.285.10:14:18.92#ibcon#read 6, iclass 37, count 0 2006.285.10:14:18.92#ibcon#end of sib2, iclass 37, count 0 2006.285.10:14:18.92#ibcon#*after write, iclass 37, count 0 2006.285.10:14:18.92#ibcon#*before return 0, iclass 37, count 0 2006.285.10:14:18.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:14:18.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:14:18.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.10:14:18.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.10:14:18.92$vck44/vblo=2,634.99 2006.285.10:14:18.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.10:14:18.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.10:14:18.92#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:18.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:14:18.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:14:18.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:14:18.92#ibcon#enter wrdev, iclass 39, count 0 2006.285.10:14:18.92#ibcon#first serial, iclass 39, count 0 2006.285.10:14:18.92#ibcon#enter sib2, iclass 39, count 0 2006.285.10:14:18.92#ibcon#flushed, iclass 39, count 0 2006.285.10:14:18.92#ibcon#about to write, iclass 39, count 0 2006.285.10:14:18.92#ibcon#wrote, iclass 39, count 0 2006.285.10:14:18.92#ibcon#about to read 3, iclass 39, count 0 2006.285.10:14:18.94#ibcon#read 3, iclass 39, count 0 2006.285.10:14:18.94#ibcon#about to read 4, iclass 39, count 0 2006.285.10:14:18.94#ibcon#read 4, iclass 39, count 0 2006.285.10:14:18.94#ibcon#about to read 5, iclass 39, count 0 2006.285.10:14:18.94#ibcon#read 5, iclass 39, count 0 2006.285.10:14:18.94#ibcon#about to read 6, iclass 39, count 0 2006.285.10:14:18.94#ibcon#read 6, iclass 39, count 0 2006.285.10:14:18.94#ibcon#end of sib2, iclass 39, count 0 2006.285.10:14:18.94#ibcon#*mode == 0, iclass 39, count 0 2006.285.10:14:18.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.10:14:18.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:14:18.94#ibcon#*before write, iclass 39, count 0 2006.285.10:14:18.94#ibcon#enter sib2, iclass 39, count 0 2006.285.10:14:18.94#ibcon#flushed, iclass 39, count 0 2006.285.10:14:18.94#ibcon#about to write, iclass 39, count 0 2006.285.10:14:18.94#ibcon#wrote, iclass 39, count 0 2006.285.10:14:18.94#ibcon#about to read 3, iclass 39, count 0 2006.285.10:14:18.98#ibcon#read 3, iclass 39, count 0 2006.285.10:14:18.98#ibcon#about to read 4, iclass 39, count 0 2006.285.10:14:18.98#ibcon#read 4, iclass 39, count 0 2006.285.10:14:18.98#ibcon#about to read 5, iclass 39, count 0 2006.285.10:14:18.98#ibcon#read 5, iclass 39, count 0 2006.285.10:14:18.98#ibcon#about to read 6, iclass 39, count 0 2006.285.10:14:18.98#ibcon#read 6, iclass 39, count 0 2006.285.10:14:18.98#ibcon#end of sib2, iclass 39, count 0 2006.285.10:14:18.98#ibcon#*after write, iclass 39, count 0 2006.285.10:14:18.98#ibcon#*before return 0, iclass 39, count 0 2006.285.10:14:18.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:14:18.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:14:18.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.10:14:18.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.10:14:18.98$vck44/vb=2,5 2006.285.10:14:18.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.10:14:18.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.10:14:18.98#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:18.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:14:19.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:14:19.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:14:19.04#ibcon#enter wrdev, iclass 3, count 2 2006.285.10:14:19.04#ibcon#first serial, iclass 3, count 2 2006.285.10:14:19.04#ibcon#enter sib2, iclass 3, count 2 2006.285.10:14:19.04#ibcon#flushed, iclass 3, count 2 2006.285.10:14:19.04#ibcon#about to write, iclass 3, count 2 2006.285.10:14:19.04#ibcon#wrote, iclass 3, count 2 2006.285.10:14:19.04#ibcon#about to read 3, iclass 3, count 2 2006.285.10:14:19.06#ibcon#read 3, iclass 3, count 2 2006.285.10:14:19.06#ibcon#about to read 4, iclass 3, count 2 2006.285.10:14:19.06#ibcon#read 4, iclass 3, count 2 2006.285.10:14:19.06#ibcon#about to read 5, iclass 3, count 2 2006.285.10:14:19.06#ibcon#read 5, iclass 3, count 2 2006.285.10:14:19.06#ibcon#about to read 6, iclass 3, count 2 2006.285.10:14:19.06#ibcon#read 6, iclass 3, count 2 2006.285.10:14:19.06#ibcon#end of sib2, iclass 3, count 2 2006.285.10:14:19.06#ibcon#*mode == 0, iclass 3, count 2 2006.285.10:14:19.06#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.10:14:19.06#ibcon#[27=AT02-05\r\n] 2006.285.10:14:19.06#ibcon#*before write, iclass 3, count 2 2006.285.10:14:19.06#ibcon#enter sib2, iclass 3, count 2 2006.285.10:14:19.06#ibcon#flushed, iclass 3, count 2 2006.285.10:14:19.06#ibcon#about to write, iclass 3, count 2 2006.285.10:14:19.06#ibcon#wrote, iclass 3, count 2 2006.285.10:14:19.06#ibcon#about to read 3, iclass 3, count 2 2006.285.10:14:19.09#ibcon#read 3, iclass 3, count 2 2006.285.10:14:19.09#ibcon#about to read 4, iclass 3, count 2 2006.285.10:14:19.09#ibcon#read 4, iclass 3, count 2 2006.285.10:14:19.09#ibcon#about to read 5, iclass 3, count 2 2006.285.10:14:19.09#ibcon#read 5, iclass 3, count 2 2006.285.10:14:19.09#ibcon#about to read 6, iclass 3, count 2 2006.285.10:14:19.09#ibcon#read 6, iclass 3, count 2 2006.285.10:14:19.09#ibcon#end of sib2, iclass 3, count 2 2006.285.10:14:19.09#ibcon#*after write, iclass 3, count 2 2006.285.10:14:19.09#ibcon#*before return 0, iclass 3, count 2 2006.285.10:14:19.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:14:19.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:14:19.09#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.10:14:19.09#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:19.09#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:14:19.21#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:14:19.21#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:14:19.21#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:14:19.21#ibcon#first serial, iclass 3, count 0 2006.285.10:14:19.21#ibcon#enter sib2, iclass 3, count 0 2006.285.10:14:19.21#ibcon#flushed, iclass 3, count 0 2006.285.10:14:19.21#ibcon#about to write, iclass 3, count 0 2006.285.10:14:19.21#ibcon#wrote, iclass 3, count 0 2006.285.10:14:19.21#ibcon#about to read 3, iclass 3, count 0 2006.285.10:14:19.23#ibcon#read 3, iclass 3, count 0 2006.285.10:14:19.23#ibcon#about to read 4, iclass 3, count 0 2006.285.10:14:19.23#ibcon#read 4, iclass 3, count 0 2006.285.10:14:19.23#ibcon#about to read 5, iclass 3, count 0 2006.285.10:14:19.23#ibcon#read 5, iclass 3, count 0 2006.285.10:14:19.23#ibcon#about to read 6, iclass 3, count 0 2006.285.10:14:19.23#ibcon#read 6, iclass 3, count 0 2006.285.10:14:19.23#ibcon#end of sib2, iclass 3, count 0 2006.285.10:14:19.23#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:14:19.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:14:19.23#ibcon#[27=USB\r\n] 2006.285.10:14:19.23#ibcon#*before write, iclass 3, count 0 2006.285.10:14:19.23#ibcon#enter sib2, iclass 3, count 0 2006.285.10:14:19.23#ibcon#flushed, iclass 3, count 0 2006.285.10:14:19.23#ibcon#about to write, iclass 3, count 0 2006.285.10:14:19.23#ibcon#wrote, iclass 3, count 0 2006.285.10:14:19.23#ibcon#about to read 3, iclass 3, count 0 2006.285.10:14:19.26#ibcon#read 3, iclass 3, count 0 2006.285.10:14:19.26#ibcon#about to read 4, iclass 3, count 0 2006.285.10:14:19.26#ibcon#read 4, iclass 3, count 0 2006.285.10:14:19.26#ibcon#about to read 5, iclass 3, count 0 2006.285.10:14:19.26#ibcon#read 5, iclass 3, count 0 2006.285.10:14:19.26#ibcon#about to read 6, iclass 3, count 0 2006.285.10:14:19.26#ibcon#read 6, iclass 3, count 0 2006.285.10:14:19.26#ibcon#end of sib2, iclass 3, count 0 2006.285.10:14:19.26#ibcon#*after write, iclass 3, count 0 2006.285.10:14:19.26#ibcon#*before return 0, iclass 3, count 0 2006.285.10:14:19.26#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:14:19.26#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:14:19.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:14:19.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:14:19.26$vck44/vblo=3,649.99 2006.285.10:14:19.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.10:14:19.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.10:14:19.26#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:19.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:14:19.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:14:19.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:14:19.26#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:14:19.26#ibcon#first serial, iclass 5, count 0 2006.285.10:14:19.26#ibcon#enter sib2, iclass 5, count 0 2006.285.10:14:19.26#ibcon#flushed, iclass 5, count 0 2006.285.10:14:19.26#ibcon#about to write, iclass 5, count 0 2006.285.10:14:19.26#ibcon#wrote, iclass 5, count 0 2006.285.10:14:19.26#ibcon#about to read 3, iclass 5, count 0 2006.285.10:14:19.28#ibcon#read 3, iclass 5, count 0 2006.285.10:14:19.28#ibcon#about to read 4, iclass 5, count 0 2006.285.10:14:19.28#ibcon#read 4, iclass 5, count 0 2006.285.10:14:19.28#ibcon#about to read 5, iclass 5, count 0 2006.285.10:14:19.28#ibcon#read 5, iclass 5, count 0 2006.285.10:14:19.28#ibcon#about to read 6, iclass 5, count 0 2006.285.10:14:19.28#ibcon#read 6, iclass 5, count 0 2006.285.10:14:19.28#ibcon#end of sib2, iclass 5, count 0 2006.285.10:14:19.28#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:14:19.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:14:19.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:14:19.28#ibcon#*before write, iclass 5, count 0 2006.285.10:14:19.28#ibcon#enter sib2, iclass 5, count 0 2006.285.10:14:19.28#ibcon#flushed, iclass 5, count 0 2006.285.10:14:19.28#ibcon#about to write, iclass 5, count 0 2006.285.10:14:19.28#ibcon#wrote, iclass 5, count 0 2006.285.10:14:19.28#ibcon#about to read 3, iclass 5, count 0 2006.285.10:14:19.32#ibcon#read 3, iclass 5, count 0 2006.285.10:14:19.32#ibcon#about to read 4, iclass 5, count 0 2006.285.10:14:19.32#ibcon#read 4, iclass 5, count 0 2006.285.10:14:19.32#ibcon#about to read 5, iclass 5, count 0 2006.285.10:14:19.32#ibcon#read 5, iclass 5, count 0 2006.285.10:14:19.32#ibcon#about to read 6, iclass 5, count 0 2006.285.10:14:19.32#ibcon#read 6, iclass 5, count 0 2006.285.10:14:19.32#ibcon#end of sib2, iclass 5, count 0 2006.285.10:14:19.32#ibcon#*after write, iclass 5, count 0 2006.285.10:14:19.32#ibcon#*before return 0, iclass 5, count 0 2006.285.10:14:19.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:14:19.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:14:19.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:14:19.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:14:19.32$vck44/vb=3,4 2006.285.10:14:19.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.10:14:19.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.10:14:19.32#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:19.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:14:19.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:14:19.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:14:19.38#ibcon#enter wrdev, iclass 7, count 2 2006.285.10:14:19.38#ibcon#first serial, iclass 7, count 2 2006.285.10:14:19.38#ibcon#enter sib2, iclass 7, count 2 2006.285.10:14:19.38#ibcon#flushed, iclass 7, count 2 2006.285.10:14:19.38#ibcon#about to write, iclass 7, count 2 2006.285.10:14:19.38#ibcon#wrote, iclass 7, count 2 2006.285.10:14:19.38#ibcon#about to read 3, iclass 7, count 2 2006.285.10:14:19.40#ibcon#read 3, iclass 7, count 2 2006.285.10:14:19.40#ibcon#about to read 4, iclass 7, count 2 2006.285.10:14:19.40#ibcon#read 4, iclass 7, count 2 2006.285.10:14:19.40#ibcon#about to read 5, iclass 7, count 2 2006.285.10:14:19.40#ibcon#read 5, iclass 7, count 2 2006.285.10:14:19.40#ibcon#about to read 6, iclass 7, count 2 2006.285.10:14:19.40#ibcon#read 6, iclass 7, count 2 2006.285.10:14:19.40#ibcon#end of sib2, iclass 7, count 2 2006.285.10:14:19.40#ibcon#*mode == 0, iclass 7, count 2 2006.285.10:14:19.40#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.10:14:19.40#ibcon#[27=AT03-04\r\n] 2006.285.10:14:19.40#ibcon#*before write, iclass 7, count 2 2006.285.10:14:19.40#ibcon#enter sib2, iclass 7, count 2 2006.285.10:14:19.40#ibcon#flushed, iclass 7, count 2 2006.285.10:14:19.40#ibcon#about to write, iclass 7, count 2 2006.285.10:14:19.40#ibcon#wrote, iclass 7, count 2 2006.285.10:14:19.40#ibcon#about to read 3, iclass 7, count 2 2006.285.10:14:19.43#ibcon#read 3, iclass 7, count 2 2006.285.10:14:19.43#ibcon#about to read 4, iclass 7, count 2 2006.285.10:14:19.43#ibcon#read 4, iclass 7, count 2 2006.285.10:14:19.43#ibcon#about to read 5, iclass 7, count 2 2006.285.10:14:19.43#ibcon#read 5, iclass 7, count 2 2006.285.10:14:19.43#ibcon#about to read 6, iclass 7, count 2 2006.285.10:14:19.43#ibcon#read 6, iclass 7, count 2 2006.285.10:14:19.43#ibcon#end of sib2, iclass 7, count 2 2006.285.10:14:19.43#ibcon#*after write, iclass 7, count 2 2006.285.10:14:19.43#ibcon#*before return 0, iclass 7, count 2 2006.285.10:14:19.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:14:19.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:14:19.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.10:14:19.43#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:19.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:14:19.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:14:19.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:14:19.55#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:14:19.55#ibcon#first serial, iclass 7, count 0 2006.285.10:14:19.55#ibcon#enter sib2, iclass 7, count 0 2006.285.10:14:19.55#ibcon#flushed, iclass 7, count 0 2006.285.10:14:19.55#ibcon#about to write, iclass 7, count 0 2006.285.10:14:19.55#ibcon#wrote, iclass 7, count 0 2006.285.10:14:19.55#ibcon#about to read 3, iclass 7, count 0 2006.285.10:14:19.57#ibcon#read 3, iclass 7, count 0 2006.285.10:14:19.57#ibcon#about to read 4, iclass 7, count 0 2006.285.10:14:19.57#ibcon#read 4, iclass 7, count 0 2006.285.10:14:19.57#ibcon#about to read 5, iclass 7, count 0 2006.285.10:14:19.57#ibcon#read 5, iclass 7, count 0 2006.285.10:14:19.57#ibcon#about to read 6, iclass 7, count 0 2006.285.10:14:19.57#ibcon#read 6, iclass 7, count 0 2006.285.10:14:19.57#ibcon#end of sib2, iclass 7, count 0 2006.285.10:14:19.57#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:14:19.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:14:19.57#ibcon#[27=USB\r\n] 2006.285.10:14:19.57#ibcon#*before write, iclass 7, count 0 2006.285.10:14:19.57#ibcon#enter sib2, iclass 7, count 0 2006.285.10:14:19.57#ibcon#flushed, iclass 7, count 0 2006.285.10:14:19.57#ibcon#about to write, iclass 7, count 0 2006.285.10:14:19.57#ibcon#wrote, iclass 7, count 0 2006.285.10:14:19.57#ibcon#about to read 3, iclass 7, count 0 2006.285.10:14:19.60#ibcon#read 3, iclass 7, count 0 2006.285.10:14:19.60#ibcon#about to read 4, iclass 7, count 0 2006.285.10:14:19.60#ibcon#read 4, iclass 7, count 0 2006.285.10:14:19.60#ibcon#about to read 5, iclass 7, count 0 2006.285.10:14:19.60#ibcon#read 5, iclass 7, count 0 2006.285.10:14:19.60#ibcon#about to read 6, iclass 7, count 0 2006.285.10:14:19.60#ibcon#read 6, iclass 7, count 0 2006.285.10:14:19.60#ibcon#end of sib2, iclass 7, count 0 2006.285.10:14:19.60#ibcon#*after write, iclass 7, count 0 2006.285.10:14:19.60#ibcon#*before return 0, iclass 7, count 0 2006.285.10:14:19.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:14:19.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:14:19.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:14:19.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:14:19.60$vck44/vblo=4,679.99 2006.285.10:14:19.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.10:14:19.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.10:14:19.60#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:19.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:14:19.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:14:19.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:14:19.60#ibcon#enter wrdev, iclass 11, count 0 2006.285.10:14:19.60#ibcon#first serial, iclass 11, count 0 2006.285.10:14:19.60#ibcon#enter sib2, iclass 11, count 0 2006.285.10:14:19.60#ibcon#flushed, iclass 11, count 0 2006.285.10:14:19.60#ibcon#about to write, iclass 11, count 0 2006.285.10:14:19.60#ibcon#wrote, iclass 11, count 0 2006.285.10:14:19.60#ibcon#about to read 3, iclass 11, count 0 2006.285.10:14:19.62#ibcon#read 3, iclass 11, count 0 2006.285.10:14:19.62#ibcon#about to read 4, iclass 11, count 0 2006.285.10:14:19.62#ibcon#read 4, iclass 11, count 0 2006.285.10:14:19.62#ibcon#about to read 5, iclass 11, count 0 2006.285.10:14:19.62#ibcon#read 5, iclass 11, count 0 2006.285.10:14:19.62#ibcon#about to read 6, iclass 11, count 0 2006.285.10:14:19.62#ibcon#read 6, iclass 11, count 0 2006.285.10:14:19.62#ibcon#end of sib2, iclass 11, count 0 2006.285.10:14:19.62#ibcon#*mode == 0, iclass 11, count 0 2006.285.10:14:19.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.10:14:19.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:14:19.62#ibcon#*before write, iclass 11, count 0 2006.285.10:14:19.62#ibcon#enter sib2, iclass 11, count 0 2006.285.10:14:19.62#ibcon#flushed, iclass 11, count 0 2006.285.10:14:19.62#ibcon#about to write, iclass 11, count 0 2006.285.10:14:19.62#ibcon#wrote, iclass 11, count 0 2006.285.10:14:19.62#ibcon#about to read 3, iclass 11, count 0 2006.285.10:14:19.66#ibcon#read 3, iclass 11, count 0 2006.285.10:14:19.66#ibcon#about to read 4, iclass 11, count 0 2006.285.10:14:19.66#ibcon#read 4, iclass 11, count 0 2006.285.10:14:19.66#ibcon#about to read 5, iclass 11, count 0 2006.285.10:14:19.66#ibcon#read 5, iclass 11, count 0 2006.285.10:14:19.66#ibcon#about to read 6, iclass 11, count 0 2006.285.10:14:19.66#ibcon#read 6, iclass 11, count 0 2006.285.10:14:19.66#ibcon#end of sib2, iclass 11, count 0 2006.285.10:14:19.66#ibcon#*after write, iclass 11, count 0 2006.285.10:14:19.66#ibcon#*before return 0, iclass 11, count 0 2006.285.10:14:19.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:14:19.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:14:19.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.10:14:19.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.10:14:19.66$vck44/vb=4,5 2006.285.10:14:19.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.10:14:19.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.10:14:19.66#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:19.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:14:19.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:14:19.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:14:19.72#ibcon#enter wrdev, iclass 13, count 2 2006.285.10:14:19.72#ibcon#first serial, iclass 13, count 2 2006.285.10:14:19.72#ibcon#enter sib2, iclass 13, count 2 2006.285.10:14:19.72#ibcon#flushed, iclass 13, count 2 2006.285.10:14:19.72#ibcon#about to write, iclass 13, count 2 2006.285.10:14:19.72#ibcon#wrote, iclass 13, count 2 2006.285.10:14:19.72#ibcon#about to read 3, iclass 13, count 2 2006.285.10:14:19.74#ibcon#read 3, iclass 13, count 2 2006.285.10:14:19.74#ibcon#about to read 4, iclass 13, count 2 2006.285.10:14:19.74#ibcon#read 4, iclass 13, count 2 2006.285.10:14:19.74#ibcon#about to read 5, iclass 13, count 2 2006.285.10:14:19.74#ibcon#read 5, iclass 13, count 2 2006.285.10:14:19.74#ibcon#about to read 6, iclass 13, count 2 2006.285.10:14:19.74#ibcon#read 6, iclass 13, count 2 2006.285.10:14:19.74#ibcon#end of sib2, iclass 13, count 2 2006.285.10:14:19.74#ibcon#*mode == 0, iclass 13, count 2 2006.285.10:14:19.74#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.10:14:19.74#ibcon#[27=AT04-05\r\n] 2006.285.10:14:19.74#ibcon#*before write, iclass 13, count 2 2006.285.10:14:19.74#ibcon#enter sib2, iclass 13, count 2 2006.285.10:14:19.74#ibcon#flushed, iclass 13, count 2 2006.285.10:14:19.74#ibcon#about to write, iclass 13, count 2 2006.285.10:14:19.74#ibcon#wrote, iclass 13, count 2 2006.285.10:14:19.74#ibcon#about to read 3, iclass 13, count 2 2006.285.10:14:19.77#ibcon#read 3, iclass 13, count 2 2006.285.10:14:19.77#ibcon#about to read 4, iclass 13, count 2 2006.285.10:14:19.77#ibcon#read 4, iclass 13, count 2 2006.285.10:14:19.77#ibcon#about to read 5, iclass 13, count 2 2006.285.10:14:19.77#ibcon#read 5, iclass 13, count 2 2006.285.10:14:19.77#ibcon#about to read 6, iclass 13, count 2 2006.285.10:14:19.77#ibcon#read 6, iclass 13, count 2 2006.285.10:14:19.77#ibcon#end of sib2, iclass 13, count 2 2006.285.10:14:19.77#ibcon#*after write, iclass 13, count 2 2006.285.10:14:19.77#ibcon#*before return 0, iclass 13, count 2 2006.285.10:14:19.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:14:19.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:14:19.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.10:14:19.77#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:19.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:14:19.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:14:19.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:14:19.89#ibcon#enter wrdev, iclass 13, count 0 2006.285.10:14:19.89#ibcon#first serial, iclass 13, count 0 2006.285.10:14:19.89#ibcon#enter sib2, iclass 13, count 0 2006.285.10:14:19.89#ibcon#flushed, iclass 13, count 0 2006.285.10:14:19.89#ibcon#about to write, iclass 13, count 0 2006.285.10:14:19.89#ibcon#wrote, iclass 13, count 0 2006.285.10:14:19.89#ibcon#about to read 3, iclass 13, count 0 2006.285.10:14:19.91#ibcon#read 3, iclass 13, count 0 2006.285.10:14:19.91#ibcon#about to read 4, iclass 13, count 0 2006.285.10:14:19.91#ibcon#read 4, iclass 13, count 0 2006.285.10:14:19.91#ibcon#about to read 5, iclass 13, count 0 2006.285.10:14:19.91#ibcon#read 5, iclass 13, count 0 2006.285.10:14:19.91#ibcon#about to read 6, iclass 13, count 0 2006.285.10:14:19.91#ibcon#read 6, iclass 13, count 0 2006.285.10:14:19.91#ibcon#end of sib2, iclass 13, count 0 2006.285.10:14:19.91#ibcon#*mode == 0, iclass 13, count 0 2006.285.10:14:19.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.10:14:19.91#ibcon#[27=USB\r\n] 2006.285.10:14:19.91#ibcon#*before write, iclass 13, count 0 2006.285.10:14:19.91#ibcon#enter sib2, iclass 13, count 0 2006.285.10:14:19.91#ibcon#flushed, iclass 13, count 0 2006.285.10:14:19.91#ibcon#about to write, iclass 13, count 0 2006.285.10:14:19.91#ibcon#wrote, iclass 13, count 0 2006.285.10:14:19.91#ibcon#about to read 3, iclass 13, count 0 2006.285.10:14:19.94#ibcon#read 3, iclass 13, count 0 2006.285.10:14:19.94#ibcon#about to read 4, iclass 13, count 0 2006.285.10:14:19.94#ibcon#read 4, iclass 13, count 0 2006.285.10:14:19.94#ibcon#about to read 5, iclass 13, count 0 2006.285.10:14:19.94#ibcon#read 5, iclass 13, count 0 2006.285.10:14:19.94#ibcon#about to read 6, iclass 13, count 0 2006.285.10:14:19.94#ibcon#read 6, iclass 13, count 0 2006.285.10:14:19.94#ibcon#end of sib2, iclass 13, count 0 2006.285.10:14:19.94#ibcon#*after write, iclass 13, count 0 2006.285.10:14:19.94#ibcon#*before return 0, iclass 13, count 0 2006.285.10:14:19.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:14:19.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:14:19.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.10:14:19.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.10:14:19.94$vck44/vblo=5,709.99 2006.285.10:14:19.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.10:14:19.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.10:14:19.94#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:19.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:14:19.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:14:19.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:14:19.94#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:14:19.94#ibcon#first serial, iclass 15, count 0 2006.285.10:14:19.94#ibcon#enter sib2, iclass 15, count 0 2006.285.10:14:19.94#ibcon#flushed, iclass 15, count 0 2006.285.10:14:19.94#ibcon#about to write, iclass 15, count 0 2006.285.10:14:19.94#ibcon#wrote, iclass 15, count 0 2006.285.10:14:19.94#ibcon#about to read 3, iclass 15, count 0 2006.285.10:14:19.96#ibcon#read 3, iclass 15, count 0 2006.285.10:14:19.96#ibcon#about to read 4, iclass 15, count 0 2006.285.10:14:19.96#ibcon#read 4, iclass 15, count 0 2006.285.10:14:19.96#ibcon#about to read 5, iclass 15, count 0 2006.285.10:14:19.96#ibcon#read 5, iclass 15, count 0 2006.285.10:14:19.96#ibcon#about to read 6, iclass 15, count 0 2006.285.10:14:19.96#ibcon#read 6, iclass 15, count 0 2006.285.10:14:19.96#ibcon#end of sib2, iclass 15, count 0 2006.285.10:14:19.96#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:14:19.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:14:19.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:14:19.96#ibcon#*before write, iclass 15, count 0 2006.285.10:14:19.96#ibcon#enter sib2, iclass 15, count 0 2006.285.10:14:19.96#ibcon#flushed, iclass 15, count 0 2006.285.10:14:19.96#ibcon#about to write, iclass 15, count 0 2006.285.10:14:19.96#ibcon#wrote, iclass 15, count 0 2006.285.10:14:19.96#ibcon#about to read 3, iclass 15, count 0 2006.285.10:14:20.00#ibcon#read 3, iclass 15, count 0 2006.285.10:14:20.00#ibcon#about to read 4, iclass 15, count 0 2006.285.10:14:20.00#ibcon#read 4, iclass 15, count 0 2006.285.10:14:20.00#ibcon#about to read 5, iclass 15, count 0 2006.285.10:14:20.00#ibcon#read 5, iclass 15, count 0 2006.285.10:14:20.00#ibcon#about to read 6, iclass 15, count 0 2006.285.10:14:20.00#ibcon#read 6, iclass 15, count 0 2006.285.10:14:20.00#ibcon#end of sib2, iclass 15, count 0 2006.285.10:14:20.00#ibcon#*after write, iclass 15, count 0 2006.285.10:14:20.00#ibcon#*before return 0, iclass 15, count 0 2006.285.10:14:20.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:14:20.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:14:20.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:14:20.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:14:20.00$vck44/vb=5,4 2006.285.10:14:20.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.10:14:20.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.10:14:20.00#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:20.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:14:20.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:14:20.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:14:20.06#ibcon#enter wrdev, iclass 17, count 2 2006.285.10:14:20.06#ibcon#first serial, iclass 17, count 2 2006.285.10:14:20.06#ibcon#enter sib2, iclass 17, count 2 2006.285.10:14:20.06#ibcon#flushed, iclass 17, count 2 2006.285.10:14:20.06#ibcon#about to write, iclass 17, count 2 2006.285.10:14:20.06#ibcon#wrote, iclass 17, count 2 2006.285.10:14:20.06#ibcon#about to read 3, iclass 17, count 2 2006.285.10:14:20.08#ibcon#read 3, iclass 17, count 2 2006.285.10:14:20.08#ibcon#about to read 4, iclass 17, count 2 2006.285.10:14:20.08#ibcon#read 4, iclass 17, count 2 2006.285.10:14:20.08#ibcon#about to read 5, iclass 17, count 2 2006.285.10:14:20.08#ibcon#read 5, iclass 17, count 2 2006.285.10:14:20.08#ibcon#about to read 6, iclass 17, count 2 2006.285.10:14:20.08#ibcon#read 6, iclass 17, count 2 2006.285.10:14:20.08#ibcon#end of sib2, iclass 17, count 2 2006.285.10:14:20.08#ibcon#*mode == 0, iclass 17, count 2 2006.285.10:14:20.08#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.10:14:20.08#ibcon#[27=AT05-04\r\n] 2006.285.10:14:20.08#ibcon#*before write, iclass 17, count 2 2006.285.10:14:20.08#ibcon#enter sib2, iclass 17, count 2 2006.285.10:14:20.08#ibcon#flushed, iclass 17, count 2 2006.285.10:14:20.08#ibcon#about to write, iclass 17, count 2 2006.285.10:14:20.08#ibcon#wrote, iclass 17, count 2 2006.285.10:14:20.08#ibcon#about to read 3, iclass 17, count 2 2006.285.10:14:20.11#ibcon#read 3, iclass 17, count 2 2006.285.10:14:20.11#ibcon#about to read 4, iclass 17, count 2 2006.285.10:14:20.11#ibcon#read 4, iclass 17, count 2 2006.285.10:14:20.11#ibcon#about to read 5, iclass 17, count 2 2006.285.10:14:20.11#ibcon#read 5, iclass 17, count 2 2006.285.10:14:20.11#ibcon#about to read 6, iclass 17, count 2 2006.285.10:14:20.11#ibcon#read 6, iclass 17, count 2 2006.285.10:14:20.11#ibcon#end of sib2, iclass 17, count 2 2006.285.10:14:20.11#ibcon#*after write, iclass 17, count 2 2006.285.10:14:20.11#ibcon#*before return 0, iclass 17, count 2 2006.285.10:14:20.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:14:20.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:14:20.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.10:14:20.11#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:20.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:14:20.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:14:20.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:14:20.23#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:14:20.23#ibcon#first serial, iclass 17, count 0 2006.285.10:14:20.23#ibcon#enter sib2, iclass 17, count 0 2006.285.10:14:20.23#ibcon#flushed, iclass 17, count 0 2006.285.10:14:20.23#ibcon#about to write, iclass 17, count 0 2006.285.10:14:20.23#ibcon#wrote, iclass 17, count 0 2006.285.10:14:20.23#ibcon#about to read 3, iclass 17, count 0 2006.285.10:14:20.25#ibcon#read 3, iclass 17, count 0 2006.285.10:14:20.25#ibcon#about to read 4, iclass 17, count 0 2006.285.10:14:20.25#ibcon#read 4, iclass 17, count 0 2006.285.10:14:20.25#ibcon#about to read 5, iclass 17, count 0 2006.285.10:14:20.25#ibcon#read 5, iclass 17, count 0 2006.285.10:14:20.25#ibcon#about to read 6, iclass 17, count 0 2006.285.10:14:20.25#ibcon#read 6, iclass 17, count 0 2006.285.10:14:20.25#ibcon#end of sib2, iclass 17, count 0 2006.285.10:14:20.25#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:14:20.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:14:20.25#ibcon#[27=USB\r\n] 2006.285.10:14:20.25#ibcon#*before write, iclass 17, count 0 2006.285.10:14:20.25#ibcon#enter sib2, iclass 17, count 0 2006.285.10:14:20.25#ibcon#flushed, iclass 17, count 0 2006.285.10:14:20.25#ibcon#about to write, iclass 17, count 0 2006.285.10:14:20.25#ibcon#wrote, iclass 17, count 0 2006.285.10:14:20.25#ibcon#about to read 3, iclass 17, count 0 2006.285.10:14:20.28#ibcon#read 3, iclass 17, count 0 2006.285.10:14:20.28#ibcon#about to read 4, iclass 17, count 0 2006.285.10:14:20.28#ibcon#read 4, iclass 17, count 0 2006.285.10:14:20.28#ibcon#about to read 5, iclass 17, count 0 2006.285.10:14:20.28#ibcon#read 5, iclass 17, count 0 2006.285.10:14:20.28#ibcon#about to read 6, iclass 17, count 0 2006.285.10:14:20.28#ibcon#read 6, iclass 17, count 0 2006.285.10:14:20.28#ibcon#end of sib2, iclass 17, count 0 2006.285.10:14:20.28#ibcon#*after write, iclass 17, count 0 2006.285.10:14:20.28#ibcon#*before return 0, iclass 17, count 0 2006.285.10:14:20.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:14:20.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:14:20.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:14:20.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:14:20.28$vck44/vblo=6,719.99 2006.285.10:14:20.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.10:14:20.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.10:14:20.28#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:20.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:14:20.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:14:20.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:14:20.28#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:14:20.28#ibcon#first serial, iclass 19, count 0 2006.285.10:14:20.28#ibcon#enter sib2, iclass 19, count 0 2006.285.10:14:20.28#ibcon#flushed, iclass 19, count 0 2006.285.10:14:20.28#ibcon#about to write, iclass 19, count 0 2006.285.10:14:20.28#ibcon#wrote, iclass 19, count 0 2006.285.10:14:20.28#ibcon#about to read 3, iclass 19, count 0 2006.285.10:14:20.30#ibcon#read 3, iclass 19, count 0 2006.285.10:14:20.30#ibcon#about to read 4, iclass 19, count 0 2006.285.10:14:20.30#ibcon#read 4, iclass 19, count 0 2006.285.10:14:20.30#ibcon#about to read 5, iclass 19, count 0 2006.285.10:14:20.30#ibcon#read 5, iclass 19, count 0 2006.285.10:14:20.30#ibcon#about to read 6, iclass 19, count 0 2006.285.10:14:20.30#ibcon#read 6, iclass 19, count 0 2006.285.10:14:20.30#ibcon#end of sib2, iclass 19, count 0 2006.285.10:14:20.30#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:14:20.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:14:20.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:14:20.30#ibcon#*before write, iclass 19, count 0 2006.285.10:14:20.30#ibcon#enter sib2, iclass 19, count 0 2006.285.10:14:20.30#ibcon#flushed, iclass 19, count 0 2006.285.10:14:20.30#ibcon#about to write, iclass 19, count 0 2006.285.10:14:20.30#ibcon#wrote, iclass 19, count 0 2006.285.10:14:20.30#ibcon#about to read 3, iclass 19, count 0 2006.285.10:14:20.34#ibcon#read 3, iclass 19, count 0 2006.285.10:14:20.34#ibcon#about to read 4, iclass 19, count 0 2006.285.10:14:20.34#ibcon#read 4, iclass 19, count 0 2006.285.10:14:20.34#ibcon#about to read 5, iclass 19, count 0 2006.285.10:14:20.34#ibcon#read 5, iclass 19, count 0 2006.285.10:14:20.34#ibcon#about to read 6, iclass 19, count 0 2006.285.10:14:20.34#ibcon#read 6, iclass 19, count 0 2006.285.10:14:20.34#ibcon#end of sib2, iclass 19, count 0 2006.285.10:14:20.34#ibcon#*after write, iclass 19, count 0 2006.285.10:14:20.34#ibcon#*before return 0, iclass 19, count 0 2006.285.10:14:20.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:14:20.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:14:20.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:14:20.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:14:20.34$vck44/vb=6,3 2006.285.10:14:20.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.10:14:20.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.10:14:20.34#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:20.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:14:20.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:14:20.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:14:20.40#ibcon#enter wrdev, iclass 21, count 2 2006.285.10:14:20.40#ibcon#first serial, iclass 21, count 2 2006.285.10:14:20.40#ibcon#enter sib2, iclass 21, count 2 2006.285.10:14:20.40#ibcon#flushed, iclass 21, count 2 2006.285.10:14:20.40#ibcon#about to write, iclass 21, count 2 2006.285.10:14:20.40#ibcon#wrote, iclass 21, count 2 2006.285.10:14:20.40#ibcon#about to read 3, iclass 21, count 2 2006.285.10:14:20.42#ibcon#read 3, iclass 21, count 2 2006.285.10:14:20.42#ibcon#about to read 4, iclass 21, count 2 2006.285.10:14:20.42#ibcon#read 4, iclass 21, count 2 2006.285.10:14:20.42#ibcon#about to read 5, iclass 21, count 2 2006.285.10:14:20.42#ibcon#read 5, iclass 21, count 2 2006.285.10:14:20.42#ibcon#about to read 6, iclass 21, count 2 2006.285.10:14:20.42#ibcon#read 6, iclass 21, count 2 2006.285.10:14:20.42#ibcon#end of sib2, iclass 21, count 2 2006.285.10:14:20.42#ibcon#*mode == 0, iclass 21, count 2 2006.285.10:14:20.42#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.10:14:20.42#ibcon#[27=AT06-03\r\n] 2006.285.10:14:20.42#ibcon#*before write, iclass 21, count 2 2006.285.10:14:20.42#ibcon#enter sib2, iclass 21, count 2 2006.285.10:14:20.42#ibcon#flushed, iclass 21, count 2 2006.285.10:14:20.42#ibcon#about to write, iclass 21, count 2 2006.285.10:14:20.42#ibcon#wrote, iclass 21, count 2 2006.285.10:14:20.42#ibcon#about to read 3, iclass 21, count 2 2006.285.10:14:20.45#ibcon#read 3, iclass 21, count 2 2006.285.10:14:20.45#ibcon#about to read 4, iclass 21, count 2 2006.285.10:14:20.45#ibcon#read 4, iclass 21, count 2 2006.285.10:14:20.45#ibcon#about to read 5, iclass 21, count 2 2006.285.10:14:20.45#ibcon#read 5, iclass 21, count 2 2006.285.10:14:20.45#ibcon#about to read 6, iclass 21, count 2 2006.285.10:14:20.45#ibcon#read 6, iclass 21, count 2 2006.285.10:14:20.45#ibcon#end of sib2, iclass 21, count 2 2006.285.10:14:20.45#ibcon#*after write, iclass 21, count 2 2006.285.10:14:20.45#ibcon#*before return 0, iclass 21, count 2 2006.285.10:14:20.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:14:20.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:14:20.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.10:14:20.45#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:20.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:14:20.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:14:20.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:14:20.57#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:14:20.57#ibcon#first serial, iclass 21, count 0 2006.285.10:14:20.57#ibcon#enter sib2, iclass 21, count 0 2006.285.10:14:20.57#ibcon#flushed, iclass 21, count 0 2006.285.10:14:20.57#ibcon#about to write, iclass 21, count 0 2006.285.10:14:20.57#ibcon#wrote, iclass 21, count 0 2006.285.10:14:20.57#ibcon#about to read 3, iclass 21, count 0 2006.285.10:14:20.59#ibcon#read 3, iclass 21, count 0 2006.285.10:14:20.59#ibcon#about to read 4, iclass 21, count 0 2006.285.10:14:20.59#ibcon#read 4, iclass 21, count 0 2006.285.10:14:20.59#ibcon#about to read 5, iclass 21, count 0 2006.285.10:14:20.59#ibcon#read 5, iclass 21, count 0 2006.285.10:14:20.59#ibcon#about to read 6, iclass 21, count 0 2006.285.10:14:20.59#ibcon#read 6, iclass 21, count 0 2006.285.10:14:20.59#ibcon#end of sib2, iclass 21, count 0 2006.285.10:14:20.59#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:14:20.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:14:20.59#ibcon#[27=USB\r\n] 2006.285.10:14:20.59#ibcon#*before write, iclass 21, count 0 2006.285.10:14:20.59#ibcon#enter sib2, iclass 21, count 0 2006.285.10:14:20.59#ibcon#flushed, iclass 21, count 0 2006.285.10:14:20.59#ibcon#about to write, iclass 21, count 0 2006.285.10:14:20.59#ibcon#wrote, iclass 21, count 0 2006.285.10:14:20.59#ibcon#about to read 3, iclass 21, count 0 2006.285.10:14:20.62#ibcon#read 3, iclass 21, count 0 2006.285.10:14:20.62#ibcon#about to read 4, iclass 21, count 0 2006.285.10:14:20.62#ibcon#read 4, iclass 21, count 0 2006.285.10:14:20.62#ibcon#about to read 5, iclass 21, count 0 2006.285.10:14:20.62#ibcon#read 5, iclass 21, count 0 2006.285.10:14:20.62#ibcon#about to read 6, iclass 21, count 0 2006.285.10:14:20.62#ibcon#read 6, iclass 21, count 0 2006.285.10:14:20.62#ibcon#end of sib2, iclass 21, count 0 2006.285.10:14:20.62#ibcon#*after write, iclass 21, count 0 2006.285.10:14:20.62#ibcon#*before return 0, iclass 21, count 0 2006.285.10:14:20.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:14:20.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:14:20.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:14:20.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:14:20.62$vck44/vblo=7,734.99 2006.285.10:14:20.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.10:14:20.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.10:14:20.62#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:20.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:14:20.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:14:20.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:14:20.62#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:14:20.62#ibcon#first serial, iclass 23, count 0 2006.285.10:14:20.62#ibcon#enter sib2, iclass 23, count 0 2006.285.10:14:20.62#ibcon#flushed, iclass 23, count 0 2006.285.10:14:20.62#ibcon#about to write, iclass 23, count 0 2006.285.10:14:20.62#ibcon#wrote, iclass 23, count 0 2006.285.10:14:20.62#ibcon#about to read 3, iclass 23, count 0 2006.285.10:14:20.64#ibcon#read 3, iclass 23, count 0 2006.285.10:14:20.64#ibcon#about to read 4, iclass 23, count 0 2006.285.10:14:20.64#ibcon#read 4, iclass 23, count 0 2006.285.10:14:20.64#ibcon#about to read 5, iclass 23, count 0 2006.285.10:14:20.64#ibcon#read 5, iclass 23, count 0 2006.285.10:14:20.64#ibcon#about to read 6, iclass 23, count 0 2006.285.10:14:20.64#ibcon#read 6, iclass 23, count 0 2006.285.10:14:20.64#ibcon#end of sib2, iclass 23, count 0 2006.285.10:14:20.64#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:14:20.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:14:20.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:14:20.64#ibcon#*before write, iclass 23, count 0 2006.285.10:14:20.64#ibcon#enter sib2, iclass 23, count 0 2006.285.10:14:20.64#ibcon#flushed, iclass 23, count 0 2006.285.10:14:20.64#ibcon#about to write, iclass 23, count 0 2006.285.10:14:20.64#ibcon#wrote, iclass 23, count 0 2006.285.10:14:20.64#ibcon#about to read 3, iclass 23, count 0 2006.285.10:14:20.68#ibcon#read 3, iclass 23, count 0 2006.285.10:14:20.68#ibcon#about to read 4, iclass 23, count 0 2006.285.10:14:20.68#ibcon#read 4, iclass 23, count 0 2006.285.10:14:20.68#ibcon#about to read 5, iclass 23, count 0 2006.285.10:14:20.68#ibcon#read 5, iclass 23, count 0 2006.285.10:14:20.68#ibcon#about to read 6, iclass 23, count 0 2006.285.10:14:20.68#ibcon#read 6, iclass 23, count 0 2006.285.10:14:20.68#ibcon#end of sib2, iclass 23, count 0 2006.285.10:14:20.68#ibcon#*after write, iclass 23, count 0 2006.285.10:14:20.68#ibcon#*before return 0, iclass 23, count 0 2006.285.10:14:20.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:14:20.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:14:20.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:14:20.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:14:20.68$vck44/vb=7,4 2006.285.10:14:20.68#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.10:14:20.68#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.10:14:20.68#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:20.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:14:20.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:14:20.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:14:20.74#ibcon#enter wrdev, iclass 25, count 2 2006.285.10:14:20.74#ibcon#first serial, iclass 25, count 2 2006.285.10:14:20.74#ibcon#enter sib2, iclass 25, count 2 2006.285.10:14:20.74#ibcon#flushed, iclass 25, count 2 2006.285.10:14:20.74#ibcon#about to write, iclass 25, count 2 2006.285.10:14:20.74#ibcon#wrote, iclass 25, count 2 2006.285.10:14:20.74#ibcon#about to read 3, iclass 25, count 2 2006.285.10:14:20.76#ibcon#read 3, iclass 25, count 2 2006.285.10:14:20.76#ibcon#about to read 4, iclass 25, count 2 2006.285.10:14:20.76#ibcon#read 4, iclass 25, count 2 2006.285.10:14:20.76#ibcon#about to read 5, iclass 25, count 2 2006.285.10:14:20.76#ibcon#read 5, iclass 25, count 2 2006.285.10:14:20.76#ibcon#about to read 6, iclass 25, count 2 2006.285.10:14:20.76#ibcon#read 6, iclass 25, count 2 2006.285.10:14:20.76#ibcon#end of sib2, iclass 25, count 2 2006.285.10:14:20.76#ibcon#*mode == 0, iclass 25, count 2 2006.285.10:14:20.76#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.10:14:20.76#ibcon#[27=AT07-04\r\n] 2006.285.10:14:20.76#ibcon#*before write, iclass 25, count 2 2006.285.10:14:20.76#ibcon#enter sib2, iclass 25, count 2 2006.285.10:14:20.76#ibcon#flushed, iclass 25, count 2 2006.285.10:14:20.76#ibcon#about to write, iclass 25, count 2 2006.285.10:14:20.76#ibcon#wrote, iclass 25, count 2 2006.285.10:14:20.76#ibcon#about to read 3, iclass 25, count 2 2006.285.10:14:20.79#ibcon#read 3, iclass 25, count 2 2006.285.10:14:20.79#ibcon#about to read 4, iclass 25, count 2 2006.285.10:14:20.79#ibcon#read 4, iclass 25, count 2 2006.285.10:14:20.79#ibcon#about to read 5, iclass 25, count 2 2006.285.10:14:20.79#ibcon#read 5, iclass 25, count 2 2006.285.10:14:20.79#ibcon#about to read 6, iclass 25, count 2 2006.285.10:14:20.79#ibcon#read 6, iclass 25, count 2 2006.285.10:14:20.79#ibcon#end of sib2, iclass 25, count 2 2006.285.10:14:20.79#ibcon#*after write, iclass 25, count 2 2006.285.10:14:20.79#ibcon#*before return 0, iclass 25, count 2 2006.285.10:14:20.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:14:20.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:14:20.79#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.10:14:20.79#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:20.79#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:14:20.91#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:14:20.91#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:14:20.91#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:14:20.91#ibcon#first serial, iclass 25, count 0 2006.285.10:14:20.91#ibcon#enter sib2, iclass 25, count 0 2006.285.10:14:20.91#ibcon#flushed, iclass 25, count 0 2006.285.10:14:20.91#ibcon#about to write, iclass 25, count 0 2006.285.10:14:20.91#ibcon#wrote, iclass 25, count 0 2006.285.10:14:20.91#ibcon#about to read 3, iclass 25, count 0 2006.285.10:14:20.93#ibcon#read 3, iclass 25, count 0 2006.285.10:14:20.93#ibcon#about to read 4, iclass 25, count 0 2006.285.10:14:20.93#ibcon#read 4, iclass 25, count 0 2006.285.10:14:20.93#ibcon#about to read 5, iclass 25, count 0 2006.285.10:14:20.93#ibcon#read 5, iclass 25, count 0 2006.285.10:14:20.93#ibcon#about to read 6, iclass 25, count 0 2006.285.10:14:20.93#ibcon#read 6, iclass 25, count 0 2006.285.10:14:20.93#ibcon#end of sib2, iclass 25, count 0 2006.285.10:14:20.93#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:14:20.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:14:20.93#ibcon#[27=USB\r\n] 2006.285.10:14:20.93#ibcon#*before write, iclass 25, count 0 2006.285.10:14:20.93#ibcon#enter sib2, iclass 25, count 0 2006.285.10:14:20.93#ibcon#flushed, iclass 25, count 0 2006.285.10:14:20.93#ibcon#about to write, iclass 25, count 0 2006.285.10:14:20.93#ibcon#wrote, iclass 25, count 0 2006.285.10:14:20.93#ibcon#about to read 3, iclass 25, count 0 2006.285.10:14:20.96#ibcon#read 3, iclass 25, count 0 2006.285.10:14:20.96#ibcon#about to read 4, iclass 25, count 0 2006.285.10:14:20.96#ibcon#read 4, iclass 25, count 0 2006.285.10:14:20.96#ibcon#about to read 5, iclass 25, count 0 2006.285.10:14:20.96#ibcon#read 5, iclass 25, count 0 2006.285.10:14:20.96#ibcon#about to read 6, iclass 25, count 0 2006.285.10:14:20.96#ibcon#read 6, iclass 25, count 0 2006.285.10:14:20.96#ibcon#end of sib2, iclass 25, count 0 2006.285.10:14:20.96#ibcon#*after write, iclass 25, count 0 2006.285.10:14:20.96#ibcon#*before return 0, iclass 25, count 0 2006.285.10:14:20.96#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:14:20.96#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:14:20.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:14:20.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:14:20.96$vck44/vblo=8,744.99 2006.285.10:14:20.96#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.10:14:20.96#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.10:14:20.96#ibcon#ireg 17 cls_cnt 0 2006.285.10:14:20.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:14:20.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:14:20.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:14:20.96#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:14:20.96#ibcon#first serial, iclass 27, count 0 2006.285.10:14:20.96#ibcon#enter sib2, iclass 27, count 0 2006.285.10:14:20.96#ibcon#flushed, iclass 27, count 0 2006.285.10:14:20.96#ibcon#about to write, iclass 27, count 0 2006.285.10:14:20.96#ibcon#wrote, iclass 27, count 0 2006.285.10:14:20.96#ibcon#about to read 3, iclass 27, count 0 2006.285.10:14:20.98#ibcon#read 3, iclass 27, count 0 2006.285.10:14:20.98#ibcon#about to read 4, iclass 27, count 0 2006.285.10:14:20.98#ibcon#read 4, iclass 27, count 0 2006.285.10:14:20.98#ibcon#about to read 5, iclass 27, count 0 2006.285.10:14:20.98#ibcon#read 5, iclass 27, count 0 2006.285.10:14:20.98#ibcon#about to read 6, iclass 27, count 0 2006.285.10:14:20.98#ibcon#read 6, iclass 27, count 0 2006.285.10:14:20.98#ibcon#end of sib2, iclass 27, count 0 2006.285.10:14:20.98#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:14:20.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:14:20.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:14:20.98#ibcon#*before write, iclass 27, count 0 2006.285.10:14:20.98#ibcon#enter sib2, iclass 27, count 0 2006.285.10:14:20.98#ibcon#flushed, iclass 27, count 0 2006.285.10:14:20.98#ibcon#about to write, iclass 27, count 0 2006.285.10:14:20.98#ibcon#wrote, iclass 27, count 0 2006.285.10:14:20.98#ibcon#about to read 3, iclass 27, count 0 2006.285.10:14:21.02#ibcon#read 3, iclass 27, count 0 2006.285.10:14:21.02#ibcon#about to read 4, iclass 27, count 0 2006.285.10:14:21.02#ibcon#read 4, iclass 27, count 0 2006.285.10:14:21.02#ibcon#about to read 5, iclass 27, count 0 2006.285.10:14:21.02#ibcon#read 5, iclass 27, count 0 2006.285.10:14:21.02#ibcon#about to read 6, iclass 27, count 0 2006.285.10:14:21.02#ibcon#read 6, iclass 27, count 0 2006.285.10:14:21.02#ibcon#end of sib2, iclass 27, count 0 2006.285.10:14:21.02#ibcon#*after write, iclass 27, count 0 2006.285.10:14:21.02#ibcon#*before return 0, iclass 27, count 0 2006.285.10:14:21.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:14:21.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:14:21.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:14:21.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:14:21.02$vck44/vb=8,4 2006.285.10:14:21.02#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.10:14:21.02#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.10:14:21.02#ibcon#ireg 11 cls_cnt 2 2006.285.10:14:21.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:14:21.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:14:21.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:14:21.08#ibcon#enter wrdev, iclass 29, count 2 2006.285.10:14:21.08#ibcon#first serial, iclass 29, count 2 2006.285.10:14:21.08#ibcon#enter sib2, iclass 29, count 2 2006.285.10:14:21.08#ibcon#flushed, iclass 29, count 2 2006.285.10:14:21.08#ibcon#about to write, iclass 29, count 2 2006.285.10:14:21.08#ibcon#wrote, iclass 29, count 2 2006.285.10:14:21.08#ibcon#about to read 3, iclass 29, count 2 2006.285.10:14:21.10#ibcon#read 3, iclass 29, count 2 2006.285.10:14:21.10#ibcon#about to read 4, iclass 29, count 2 2006.285.10:14:21.10#ibcon#read 4, iclass 29, count 2 2006.285.10:14:21.10#ibcon#about to read 5, iclass 29, count 2 2006.285.10:14:21.10#ibcon#read 5, iclass 29, count 2 2006.285.10:14:21.10#ibcon#about to read 6, iclass 29, count 2 2006.285.10:14:21.10#ibcon#read 6, iclass 29, count 2 2006.285.10:14:21.10#ibcon#end of sib2, iclass 29, count 2 2006.285.10:14:21.10#ibcon#*mode == 0, iclass 29, count 2 2006.285.10:14:21.10#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.10:14:21.10#ibcon#[27=AT08-04\r\n] 2006.285.10:14:21.10#ibcon#*before write, iclass 29, count 2 2006.285.10:14:21.10#ibcon#enter sib2, iclass 29, count 2 2006.285.10:14:21.10#ibcon#flushed, iclass 29, count 2 2006.285.10:14:21.10#ibcon#about to write, iclass 29, count 2 2006.285.10:14:21.10#ibcon#wrote, iclass 29, count 2 2006.285.10:14:21.10#ibcon#about to read 3, iclass 29, count 2 2006.285.10:14:21.13#ibcon#read 3, iclass 29, count 2 2006.285.10:14:21.13#ibcon#about to read 4, iclass 29, count 2 2006.285.10:14:21.13#ibcon#read 4, iclass 29, count 2 2006.285.10:14:21.13#ibcon#about to read 5, iclass 29, count 2 2006.285.10:14:21.13#ibcon#read 5, iclass 29, count 2 2006.285.10:14:21.13#ibcon#about to read 6, iclass 29, count 2 2006.285.10:14:21.13#ibcon#read 6, iclass 29, count 2 2006.285.10:14:21.13#ibcon#end of sib2, iclass 29, count 2 2006.285.10:14:21.13#ibcon#*after write, iclass 29, count 2 2006.285.10:14:21.13#ibcon#*before return 0, iclass 29, count 2 2006.285.10:14:21.13#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:14:21.13#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:14:21.13#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.10:14:21.13#ibcon#ireg 7 cls_cnt 0 2006.285.10:14:21.13#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:14:21.25#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:14:21.25#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:14:21.25#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:14:21.25#ibcon#first serial, iclass 29, count 0 2006.285.10:14:21.25#ibcon#enter sib2, iclass 29, count 0 2006.285.10:14:21.25#ibcon#flushed, iclass 29, count 0 2006.285.10:14:21.25#ibcon#about to write, iclass 29, count 0 2006.285.10:14:21.25#ibcon#wrote, iclass 29, count 0 2006.285.10:14:21.25#ibcon#about to read 3, iclass 29, count 0 2006.285.10:14:21.27#ibcon#read 3, iclass 29, count 0 2006.285.10:14:21.27#ibcon#about to read 4, iclass 29, count 0 2006.285.10:14:21.27#ibcon#read 4, iclass 29, count 0 2006.285.10:14:21.27#ibcon#about to read 5, iclass 29, count 0 2006.285.10:14:21.27#ibcon#read 5, iclass 29, count 0 2006.285.10:14:21.27#ibcon#about to read 6, iclass 29, count 0 2006.285.10:14:21.27#ibcon#read 6, iclass 29, count 0 2006.285.10:14:21.27#ibcon#end of sib2, iclass 29, count 0 2006.285.10:14:21.27#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:14:21.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:14:21.27#ibcon#[27=USB\r\n] 2006.285.10:14:21.27#ibcon#*before write, iclass 29, count 0 2006.285.10:14:21.27#ibcon#enter sib2, iclass 29, count 0 2006.285.10:14:21.27#ibcon#flushed, iclass 29, count 0 2006.285.10:14:21.27#ibcon#about to write, iclass 29, count 0 2006.285.10:14:21.27#ibcon#wrote, iclass 29, count 0 2006.285.10:14:21.27#ibcon#about to read 3, iclass 29, count 0 2006.285.10:14:21.30#ibcon#read 3, iclass 29, count 0 2006.285.10:14:21.30#ibcon#about to read 4, iclass 29, count 0 2006.285.10:14:21.30#ibcon#read 4, iclass 29, count 0 2006.285.10:14:21.30#ibcon#about to read 5, iclass 29, count 0 2006.285.10:14:21.30#ibcon#read 5, iclass 29, count 0 2006.285.10:14:21.30#ibcon#about to read 6, iclass 29, count 0 2006.285.10:14:21.30#ibcon#read 6, iclass 29, count 0 2006.285.10:14:21.30#ibcon#end of sib2, iclass 29, count 0 2006.285.10:14:21.30#ibcon#*after write, iclass 29, count 0 2006.285.10:14:21.30#ibcon#*before return 0, iclass 29, count 0 2006.285.10:14:21.30#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:14:21.30#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:14:21.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:14:21.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:14:21.30$vck44/vabw=wide 2006.285.10:14:21.30#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.10:14:21.30#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.10:14:21.30#ibcon#ireg 8 cls_cnt 0 2006.285.10:14:21.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:14:21.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:14:21.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:14:21.30#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:14:21.30#ibcon#first serial, iclass 31, count 0 2006.285.10:14:21.30#ibcon#enter sib2, iclass 31, count 0 2006.285.10:14:21.30#ibcon#flushed, iclass 31, count 0 2006.285.10:14:21.30#ibcon#about to write, iclass 31, count 0 2006.285.10:14:21.30#ibcon#wrote, iclass 31, count 0 2006.285.10:14:21.30#ibcon#about to read 3, iclass 31, count 0 2006.285.10:14:21.32#ibcon#read 3, iclass 31, count 0 2006.285.10:14:21.32#ibcon#about to read 4, iclass 31, count 0 2006.285.10:14:21.32#ibcon#read 4, iclass 31, count 0 2006.285.10:14:21.32#ibcon#about to read 5, iclass 31, count 0 2006.285.10:14:21.32#ibcon#read 5, iclass 31, count 0 2006.285.10:14:21.32#ibcon#about to read 6, iclass 31, count 0 2006.285.10:14:21.32#ibcon#read 6, iclass 31, count 0 2006.285.10:14:21.32#ibcon#end of sib2, iclass 31, count 0 2006.285.10:14:21.32#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:14:21.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:14:21.32#ibcon#[25=BW32\r\n] 2006.285.10:14:21.32#ibcon#*before write, iclass 31, count 0 2006.285.10:14:21.32#ibcon#enter sib2, iclass 31, count 0 2006.285.10:14:21.32#ibcon#flushed, iclass 31, count 0 2006.285.10:14:21.32#ibcon#about to write, iclass 31, count 0 2006.285.10:14:21.32#ibcon#wrote, iclass 31, count 0 2006.285.10:14:21.32#ibcon#about to read 3, iclass 31, count 0 2006.285.10:14:21.35#ibcon#read 3, iclass 31, count 0 2006.285.10:14:21.35#ibcon#about to read 4, iclass 31, count 0 2006.285.10:14:21.35#ibcon#read 4, iclass 31, count 0 2006.285.10:14:21.35#ibcon#about to read 5, iclass 31, count 0 2006.285.10:14:21.35#ibcon#read 5, iclass 31, count 0 2006.285.10:14:21.35#ibcon#about to read 6, iclass 31, count 0 2006.285.10:14:21.35#ibcon#read 6, iclass 31, count 0 2006.285.10:14:21.35#ibcon#end of sib2, iclass 31, count 0 2006.285.10:14:21.35#ibcon#*after write, iclass 31, count 0 2006.285.10:14:21.35#ibcon#*before return 0, iclass 31, count 0 2006.285.10:14:21.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:14:21.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:14:21.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:14:21.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:14:21.35$vck44/vbbw=wide 2006.285.10:14:21.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.10:14:21.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.10:14:21.35#ibcon#ireg 8 cls_cnt 0 2006.285.10:14:21.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:14:21.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:14:21.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:14:21.42#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:14:21.42#ibcon#first serial, iclass 33, count 0 2006.285.10:14:21.42#ibcon#enter sib2, iclass 33, count 0 2006.285.10:14:21.42#ibcon#flushed, iclass 33, count 0 2006.285.10:14:21.42#ibcon#about to write, iclass 33, count 0 2006.285.10:14:21.42#ibcon#wrote, iclass 33, count 0 2006.285.10:14:21.42#ibcon#about to read 3, iclass 33, count 0 2006.285.10:14:21.44#ibcon#read 3, iclass 33, count 0 2006.285.10:14:21.44#ibcon#about to read 4, iclass 33, count 0 2006.285.10:14:21.44#ibcon#read 4, iclass 33, count 0 2006.285.10:14:21.44#ibcon#about to read 5, iclass 33, count 0 2006.285.10:14:21.44#ibcon#read 5, iclass 33, count 0 2006.285.10:14:21.44#ibcon#about to read 6, iclass 33, count 0 2006.285.10:14:21.44#ibcon#read 6, iclass 33, count 0 2006.285.10:14:21.44#ibcon#end of sib2, iclass 33, count 0 2006.285.10:14:21.44#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:14:21.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:14:21.44#ibcon#[27=BW32\r\n] 2006.285.10:14:21.44#ibcon#*before write, iclass 33, count 0 2006.285.10:14:21.44#ibcon#enter sib2, iclass 33, count 0 2006.285.10:14:21.44#ibcon#flushed, iclass 33, count 0 2006.285.10:14:21.44#ibcon#about to write, iclass 33, count 0 2006.285.10:14:21.44#ibcon#wrote, iclass 33, count 0 2006.285.10:14:21.44#ibcon#about to read 3, iclass 33, count 0 2006.285.10:14:21.47#ibcon#read 3, iclass 33, count 0 2006.285.10:14:21.47#ibcon#about to read 4, iclass 33, count 0 2006.285.10:14:21.47#ibcon#read 4, iclass 33, count 0 2006.285.10:14:21.47#ibcon#about to read 5, iclass 33, count 0 2006.285.10:14:21.47#ibcon#read 5, iclass 33, count 0 2006.285.10:14:21.47#ibcon#about to read 6, iclass 33, count 0 2006.285.10:14:21.47#ibcon#read 6, iclass 33, count 0 2006.285.10:14:21.47#ibcon#end of sib2, iclass 33, count 0 2006.285.10:14:21.47#ibcon#*after write, iclass 33, count 0 2006.285.10:14:21.47#ibcon#*before return 0, iclass 33, count 0 2006.285.10:14:21.47#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:14:21.47#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:14:21.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:14:21.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:14:21.47$setupk4/ifdk4 2006.285.10:14:21.47$ifdk4/lo= 2006.285.10:14:21.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:14:21.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:14:21.47$ifdk4/patch= 2006.285.10:14:21.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:14:21.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:14:21.48$setupk4/!*+20s 2006.285.10:14:27.34#abcon#<5=/04 1.4 2.0 19.71 911015.0\r\n> 2006.285.10:14:27.36#abcon#{5=INTERFACE CLEAR} 2006.285.10:14:27.42#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:14:35.99$setupk4/"tpicd 2006.285.10:14:35.99$setupk4/echo=off 2006.285.10:14:35.99$setupk4/xlog=off 2006.285.10:14:35.99:!2006.285.10:18:47 2006.285.10:14:57.14#trakl#Source acquired 2006.285.10:14:58.14#flagr#flagr/antenna,acquired 2006.285.10:18:47.00:preob 2006.285.10:18:47.14/onsource/TRACKING 2006.285.10:18:47.14:!2006.285.10:18:57 2006.285.10:18:57.00:"tape 2006.285.10:18:57.00:"st=record 2006.285.10:18:57.00:data_valid=on 2006.285.10:18:57.00:midob 2006.285.10:18:58.14/onsource/TRACKING 2006.285.10:18:58.14/wx/19.75,1015.1,91 2006.285.10:18:58.30/cable/+6.4863E-03 2006.285.10:18:59.39/va/01,07,usb,yes,32,35 2006.285.10:18:59.39/va/02,06,usb,yes,32,33 2006.285.10:18:59.39/va/03,07,usb,yes,32,34 2006.285.10:18:59.39/va/04,06,usb,yes,33,35 2006.285.10:18:59.39/va/05,03,usb,yes,33,33 2006.285.10:18:59.39/va/06,04,usb,yes,29,29 2006.285.10:18:59.39/va/07,04,usb,yes,30,31 2006.285.10:18:59.39/va/08,03,usb,yes,31,37 2006.285.10:18:59.62/valo/01,524.99,yes,locked 2006.285.10:18:59.62/valo/02,534.99,yes,locked 2006.285.10:18:59.62/valo/03,564.99,yes,locked 2006.285.10:18:59.62/valo/04,624.99,yes,locked 2006.285.10:18:59.62/valo/05,734.99,yes,locked 2006.285.10:18:59.62/valo/06,814.99,yes,locked 2006.285.10:18:59.62/valo/07,864.99,yes,locked 2006.285.10:18:59.62/valo/08,884.99,yes,locked 2006.285.10:19:00.71/vb/01,04,usb,yes,31,29 2006.285.10:19:00.71/vb/02,05,usb,yes,29,29 2006.285.10:19:00.71/vb/03,04,usb,yes,30,33 2006.285.10:19:00.71/vb/04,05,usb,yes,30,29 2006.285.10:19:00.71/vb/05,04,usb,yes,27,29 2006.285.10:19:00.71/vb/06,03,usb,yes,38,34 2006.285.10:19:00.71/vb/07,04,usb,yes,31,31 2006.285.10:19:00.71/vb/08,04,usb,yes,28,32 2006.285.10:19:00.94/vblo/01,629.99,yes,locked 2006.285.10:19:00.94/vblo/02,634.99,yes,locked 2006.285.10:19:00.94/vblo/03,649.99,yes,locked 2006.285.10:19:00.94/vblo/04,679.99,yes,locked 2006.285.10:19:00.94/vblo/05,709.99,yes,locked 2006.285.10:19:00.94/vblo/06,719.99,yes,locked 2006.285.10:19:00.94/vblo/07,734.99,yes,locked 2006.285.10:19:00.94/vblo/08,744.99,yes,locked 2006.285.10:19:01.09/vabw/8 2006.285.10:19:01.24/vbbw/8 2006.285.10:19:01.33/xfe/off,on,12.2 2006.285.10:19:01.71/ifatt/23,28,28,28 2006.285.10:19:02.07/fmout-gps/S +2.69E-07 2006.285.10:19:02.09:!2006.285.10:19:37 2006.285.10:19:37.00:data_valid=off 2006.285.10:19:37.00:"et 2006.285.10:19:37.00:!+3s 2006.285.10:19:40.01:"tape 2006.285.10:19:40.01:postob 2006.285.10:19:40.16/cable/+6.4846E-03 2006.285.10:19:40.16/wx/19.76,1015.0,91 2006.285.10:19:41.08/fmout-gps/S +2.68E-07 2006.285.10:19:41.08:scan_name=285-1020,jd0610,60 2006.285.10:19:41.08:source=1611+343,161341.06,341247.9,2000.0,cw 2006.285.10:19:42.14#flagr#flagr/antenna,new-source 2006.285.10:19:42.14:checkk5 2006.285.10:19:42.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:19:42.98/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:19:43.39/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:19:43.81/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:19:44.20/chk_obsdata//k5ts1/T2851018??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.10:19:44.55/chk_obsdata//k5ts2/T2851018??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.10:19:44.94/chk_obsdata//k5ts3/T2851018??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.10:19:45.33/chk_obsdata//k5ts4/T2851018??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.10:19:46.35/k5log//k5ts1_log_newline 2006.285.10:19:47.10/k5log//k5ts2_log_newline 2006.285.10:19:47.82/k5log//k5ts3_log_newline 2006.285.10:19:48.59/k5log//k5ts4_log_newline 2006.285.10:19:48.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:19:48.62:setupk4=1 2006.285.10:19:48.62$setupk4/echo=on 2006.285.10:19:48.62$setupk4/pcalon 2006.285.10:19:48.62$pcalon/"no phase cal control is implemented here 2006.285.10:19:48.62$setupk4/"tpicd=stop 2006.285.10:19:48.62$setupk4/"rec=synch_on 2006.285.10:19:48.62$setupk4/"rec_mode=128 2006.285.10:19:48.62$setupk4/!* 2006.285.10:19:48.62$setupk4/recpk4 2006.285.10:19:48.62$recpk4/recpatch= 2006.285.10:19:48.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:19:48.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:19:48.62$setupk4/vck44 2006.285.10:19:48.62$vck44/valo=1,524.99 2006.285.10:19:48.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.10:19:48.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.10:19:48.62#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:48.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:19:48.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:19:48.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:19:48.62#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:19:48.62#ibcon#first serial, iclass 22, count 0 2006.285.10:19:48.62#ibcon#enter sib2, iclass 22, count 0 2006.285.10:19:48.62#ibcon#flushed, iclass 22, count 0 2006.285.10:19:48.62#ibcon#about to write, iclass 22, count 0 2006.285.10:19:48.62#ibcon#wrote, iclass 22, count 0 2006.285.10:19:48.62#ibcon#about to read 3, iclass 22, count 0 2006.285.10:19:48.64#ibcon#read 3, iclass 22, count 0 2006.285.10:19:48.64#ibcon#about to read 4, iclass 22, count 0 2006.285.10:19:48.64#ibcon#read 4, iclass 22, count 0 2006.285.10:19:48.64#ibcon#about to read 5, iclass 22, count 0 2006.285.10:19:48.64#ibcon#read 5, iclass 22, count 0 2006.285.10:19:48.64#ibcon#about to read 6, iclass 22, count 0 2006.285.10:19:48.64#ibcon#read 6, iclass 22, count 0 2006.285.10:19:48.64#ibcon#end of sib2, iclass 22, count 0 2006.285.10:19:48.64#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:19:48.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:19:48.64#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:19:48.64#ibcon#*before write, iclass 22, count 0 2006.285.10:19:48.64#ibcon#enter sib2, iclass 22, count 0 2006.285.10:19:48.64#ibcon#flushed, iclass 22, count 0 2006.285.10:19:48.64#ibcon#about to write, iclass 22, count 0 2006.285.10:19:48.64#ibcon#wrote, iclass 22, count 0 2006.285.10:19:48.64#ibcon#about to read 3, iclass 22, count 0 2006.285.10:19:48.69#ibcon#read 3, iclass 22, count 0 2006.285.10:19:48.69#ibcon#about to read 4, iclass 22, count 0 2006.285.10:19:48.69#ibcon#read 4, iclass 22, count 0 2006.285.10:19:48.69#ibcon#about to read 5, iclass 22, count 0 2006.285.10:19:48.69#ibcon#read 5, iclass 22, count 0 2006.285.10:19:48.69#ibcon#about to read 6, iclass 22, count 0 2006.285.10:19:48.69#ibcon#read 6, iclass 22, count 0 2006.285.10:19:48.69#ibcon#end of sib2, iclass 22, count 0 2006.285.10:19:48.69#ibcon#*after write, iclass 22, count 0 2006.285.10:19:48.69#ibcon#*before return 0, iclass 22, count 0 2006.285.10:19:48.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:19:48.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:19:48.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:19:48.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:19:48.69$vck44/va=1,7 2006.285.10:19:48.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.10:19:48.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.10:19:48.69#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:48.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:19:48.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:19:48.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:19:48.69#ibcon#enter wrdev, iclass 24, count 2 2006.285.10:19:48.69#ibcon#first serial, iclass 24, count 2 2006.285.10:19:48.69#ibcon#enter sib2, iclass 24, count 2 2006.285.10:19:48.69#ibcon#flushed, iclass 24, count 2 2006.285.10:19:48.69#ibcon#about to write, iclass 24, count 2 2006.285.10:19:48.69#ibcon#wrote, iclass 24, count 2 2006.285.10:19:48.69#ibcon#about to read 3, iclass 24, count 2 2006.285.10:19:48.71#ibcon#read 3, iclass 24, count 2 2006.285.10:19:48.71#ibcon#about to read 4, iclass 24, count 2 2006.285.10:19:48.71#ibcon#read 4, iclass 24, count 2 2006.285.10:19:48.71#ibcon#about to read 5, iclass 24, count 2 2006.285.10:19:48.71#ibcon#read 5, iclass 24, count 2 2006.285.10:19:48.71#ibcon#about to read 6, iclass 24, count 2 2006.285.10:19:48.71#ibcon#read 6, iclass 24, count 2 2006.285.10:19:48.71#ibcon#end of sib2, iclass 24, count 2 2006.285.10:19:48.71#ibcon#*mode == 0, iclass 24, count 2 2006.285.10:19:48.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.10:19:48.71#ibcon#[25=AT01-07\r\n] 2006.285.10:19:48.71#ibcon#*before write, iclass 24, count 2 2006.285.10:19:48.71#ibcon#enter sib2, iclass 24, count 2 2006.285.10:19:48.71#ibcon#flushed, iclass 24, count 2 2006.285.10:19:48.71#ibcon#about to write, iclass 24, count 2 2006.285.10:19:48.71#ibcon#wrote, iclass 24, count 2 2006.285.10:19:48.71#ibcon#about to read 3, iclass 24, count 2 2006.285.10:19:48.74#ibcon#read 3, iclass 24, count 2 2006.285.10:19:48.74#ibcon#about to read 4, iclass 24, count 2 2006.285.10:19:48.74#ibcon#read 4, iclass 24, count 2 2006.285.10:19:48.74#ibcon#about to read 5, iclass 24, count 2 2006.285.10:19:48.74#ibcon#read 5, iclass 24, count 2 2006.285.10:19:48.74#ibcon#about to read 6, iclass 24, count 2 2006.285.10:19:48.74#ibcon#read 6, iclass 24, count 2 2006.285.10:19:48.74#ibcon#end of sib2, iclass 24, count 2 2006.285.10:19:48.74#ibcon#*after write, iclass 24, count 2 2006.285.10:19:48.74#ibcon#*before return 0, iclass 24, count 2 2006.285.10:19:48.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:19:48.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:19:48.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.10:19:48.74#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:48.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:19:48.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:19:48.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:19:48.86#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:19:48.86#ibcon#first serial, iclass 24, count 0 2006.285.10:19:48.86#ibcon#enter sib2, iclass 24, count 0 2006.285.10:19:48.86#ibcon#flushed, iclass 24, count 0 2006.285.10:19:48.86#ibcon#about to write, iclass 24, count 0 2006.285.10:19:48.86#ibcon#wrote, iclass 24, count 0 2006.285.10:19:48.86#ibcon#about to read 3, iclass 24, count 0 2006.285.10:19:48.88#ibcon#read 3, iclass 24, count 0 2006.285.10:19:48.88#ibcon#about to read 4, iclass 24, count 0 2006.285.10:19:48.88#ibcon#read 4, iclass 24, count 0 2006.285.10:19:48.88#ibcon#about to read 5, iclass 24, count 0 2006.285.10:19:48.88#ibcon#read 5, iclass 24, count 0 2006.285.10:19:48.88#ibcon#about to read 6, iclass 24, count 0 2006.285.10:19:48.88#ibcon#read 6, iclass 24, count 0 2006.285.10:19:48.88#ibcon#end of sib2, iclass 24, count 0 2006.285.10:19:48.88#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:19:48.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:19:48.88#ibcon#[25=USB\r\n] 2006.285.10:19:48.88#ibcon#*before write, iclass 24, count 0 2006.285.10:19:48.88#ibcon#enter sib2, iclass 24, count 0 2006.285.10:19:48.88#ibcon#flushed, iclass 24, count 0 2006.285.10:19:48.88#ibcon#about to write, iclass 24, count 0 2006.285.10:19:48.88#ibcon#wrote, iclass 24, count 0 2006.285.10:19:48.88#ibcon#about to read 3, iclass 24, count 0 2006.285.10:19:48.91#ibcon#read 3, iclass 24, count 0 2006.285.10:19:48.91#ibcon#about to read 4, iclass 24, count 0 2006.285.10:19:48.91#ibcon#read 4, iclass 24, count 0 2006.285.10:19:48.91#ibcon#about to read 5, iclass 24, count 0 2006.285.10:19:48.91#ibcon#read 5, iclass 24, count 0 2006.285.10:19:48.91#ibcon#about to read 6, iclass 24, count 0 2006.285.10:19:48.91#ibcon#read 6, iclass 24, count 0 2006.285.10:19:48.91#ibcon#end of sib2, iclass 24, count 0 2006.285.10:19:48.91#ibcon#*after write, iclass 24, count 0 2006.285.10:19:48.91#ibcon#*before return 0, iclass 24, count 0 2006.285.10:19:48.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:19:48.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:19:48.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:19:48.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:19:48.91$vck44/valo=2,534.99 2006.285.10:19:48.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.10:19:48.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.10:19:48.91#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:48.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:19:48.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:19:48.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:19:48.91#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:19:48.91#ibcon#first serial, iclass 26, count 0 2006.285.10:19:48.91#ibcon#enter sib2, iclass 26, count 0 2006.285.10:19:48.91#ibcon#flushed, iclass 26, count 0 2006.285.10:19:48.91#ibcon#about to write, iclass 26, count 0 2006.285.10:19:48.91#ibcon#wrote, iclass 26, count 0 2006.285.10:19:48.91#ibcon#about to read 3, iclass 26, count 0 2006.285.10:19:48.93#ibcon#read 3, iclass 26, count 0 2006.285.10:19:48.93#ibcon#about to read 4, iclass 26, count 0 2006.285.10:19:48.93#ibcon#read 4, iclass 26, count 0 2006.285.10:19:48.93#ibcon#about to read 5, iclass 26, count 0 2006.285.10:19:48.93#ibcon#read 5, iclass 26, count 0 2006.285.10:19:48.93#ibcon#about to read 6, iclass 26, count 0 2006.285.10:19:48.93#ibcon#read 6, iclass 26, count 0 2006.285.10:19:48.93#ibcon#end of sib2, iclass 26, count 0 2006.285.10:19:48.93#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:19:48.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:19:48.93#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:19:48.93#ibcon#*before write, iclass 26, count 0 2006.285.10:19:48.93#ibcon#enter sib2, iclass 26, count 0 2006.285.10:19:48.93#ibcon#flushed, iclass 26, count 0 2006.285.10:19:48.93#ibcon#about to write, iclass 26, count 0 2006.285.10:19:48.93#ibcon#wrote, iclass 26, count 0 2006.285.10:19:48.93#ibcon#about to read 3, iclass 26, count 0 2006.285.10:19:48.97#ibcon#read 3, iclass 26, count 0 2006.285.10:19:48.97#ibcon#about to read 4, iclass 26, count 0 2006.285.10:19:48.97#ibcon#read 4, iclass 26, count 0 2006.285.10:19:48.97#ibcon#about to read 5, iclass 26, count 0 2006.285.10:19:48.97#ibcon#read 5, iclass 26, count 0 2006.285.10:19:48.97#ibcon#about to read 6, iclass 26, count 0 2006.285.10:19:48.97#ibcon#read 6, iclass 26, count 0 2006.285.10:19:48.97#ibcon#end of sib2, iclass 26, count 0 2006.285.10:19:48.97#ibcon#*after write, iclass 26, count 0 2006.285.10:19:48.97#ibcon#*before return 0, iclass 26, count 0 2006.285.10:19:48.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:19:48.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:19:48.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:19:48.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:19:48.97$vck44/va=2,6 2006.285.10:19:48.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.10:19:48.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.10:19:48.97#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:48.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:19:49.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:19:49.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:19:49.03#ibcon#enter wrdev, iclass 28, count 2 2006.285.10:19:49.03#ibcon#first serial, iclass 28, count 2 2006.285.10:19:49.03#ibcon#enter sib2, iclass 28, count 2 2006.285.10:19:49.03#ibcon#flushed, iclass 28, count 2 2006.285.10:19:49.03#ibcon#about to write, iclass 28, count 2 2006.285.10:19:49.03#ibcon#wrote, iclass 28, count 2 2006.285.10:19:49.03#ibcon#about to read 3, iclass 28, count 2 2006.285.10:19:49.05#ibcon#read 3, iclass 28, count 2 2006.285.10:19:49.05#ibcon#about to read 4, iclass 28, count 2 2006.285.10:19:49.05#ibcon#read 4, iclass 28, count 2 2006.285.10:19:49.05#ibcon#about to read 5, iclass 28, count 2 2006.285.10:19:49.05#ibcon#read 5, iclass 28, count 2 2006.285.10:19:49.05#ibcon#about to read 6, iclass 28, count 2 2006.285.10:19:49.05#ibcon#read 6, iclass 28, count 2 2006.285.10:19:49.05#ibcon#end of sib2, iclass 28, count 2 2006.285.10:19:49.05#ibcon#*mode == 0, iclass 28, count 2 2006.285.10:19:49.05#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.10:19:49.05#ibcon#[25=AT02-06\r\n] 2006.285.10:19:49.05#ibcon#*before write, iclass 28, count 2 2006.285.10:19:49.05#ibcon#enter sib2, iclass 28, count 2 2006.285.10:19:49.05#ibcon#flushed, iclass 28, count 2 2006.285.10:19:49.05#ibcon#about to write, iclass 28, count 2 2006.285.10:19:49.05#ibcon#wrote, iclass 28, count 2 2006.285.10:19:49.05#ibcon#about to read 3, iclass 28, count 2 2006.285.10:19:49.08#ibcon#read 3, iclass 28, count 2 2006.285.10:19:49.08#ibcon#about to read 4, iclass 28, count 2 2006.285.10:19:49.08#ibcon#read 4, iclass 28, count 2 2006.285.10:19:49.08#ibcon#about to read 5, iclass 28, count 2 2006.285.10:19:49.08#ibcon#read 5, iclass 28, count 2 2006.285.10:19:49.08#ibcon#about to read 6, iclass 28, count 2 2006.285.10:19:49.08#ibcon#read 6, iclass 28, count 2 2006.285.10:19:49.08#ibcon#end of sib2, iclass 28, count 2 2006.285.10:19:49.08#ibcon#*after write, iclass 28, count 2 2006.285.10:19:49.08#ibcon#*before return 0, iclass 28, count 2 2006.285.10:19:49.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:19:49.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:19:49.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.10:19:49.08#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:49.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:19:49.20#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:19:49.20#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:19:49.20#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:19:49.20#ibcon#first serial, iclass 28, count 0 2006.285.10:19:49.20#ibcon#enter sib2, iclass 28, count 0 2006.285.10:19:49.20#ibcon#flushed, iclass 28, count 0 2006.285.10:19:49.20#ibcon#about to write, iclass 28, count 0 2006.285.10:19:49.20#ibcon#wrote, iclass 28, count 0 2006.285.10:19:49.20#ibcon#about to read 3, iclass 28, count 0 2006.285.10:19:49.22#ibcon#read 3, iclass 28, count 0 2006.285.10:19:49.22#ibcon#about to read 4, iclass 28, count 0 2006.285.10:19:49.22#ibcon#read 4, iclass 28, count 0 2006.285.10:19:49.22#ibcon#about to read 5, iclass 28, count 0 2006.285.10:19:49.22#ibcon#read 5, iclass 28, count 0 2006.285.10:19:49.22#ibcon#about to read 6, iclass 28, count 0 2006.285.10:19:49.22#ibcon#read 6, iclass 28, count 0 2006.285.10:19:49.22#ibcon#end of sib2, iclass 28, count 0 2006.285.10:19:49.22#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:19:49.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:19:49.22#ibcon#[25=USB\r\n] 2006.285.10:19:49.22#ibcon#*before write, iclass 28, count 0 2006.285.10:19:49.22#ibcon#enter sib2, iclass 28, count 0 2006.285.10:19:49.22#ibcon#flushed, iclass 28, count 0 2006.285.10:19:49.22#ibcon#about to write, iclass 28, count 0 2006.285.10:19:49.22#ibcon#wrote, iclass 28, count 0 2006.285.10:19:49.22#ibcon#about to read 3, iclass 28, count 0 2006.285.10:19:49.25#ibcon#read 3, iclass 28, count 0 2006.285.10:19:49.25#ibcon#about to read 4, iclass 28, count 0 2006.285.10:19:49.25#ibcon#read 4, iclass 28, count 0 2006.285.10:19:49.25#ibcon#about to read 5, iclass 28, count 0 2006.285.10:19:49.25#ibcon#read 5, iclass 28, count 0 2006.285.10:19:49.25#ibcon#about to read 6, iclass 28, count 0 2006.285.10:19:49.25#ibcon#read 6, iclass 28, count 0 2006.285.10:19:49.25#ibcon#end of sib2, iclass 28, count 0 2006.285.10:19:49.25#ibcon#*after write, iclass 28, count 0 2006.285.10:19:49.25#ibcon#*before return 0, iclass 28, count 0 2006.285.10:19:49.25#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:19:49.25#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:19:49.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:19:49.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:19:49.25$vck44/valo=3,564.99 2006.285.10:19:49.25#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.10:19:49.25#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.10:19:49.25#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:49.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:19:49.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:19:49.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:19:49.25#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:19:49.25#ibcon#first serial, iclass 30, count 0 2006.285.10:19:49.25#ibcon#enter sib2, iclass 30, count 0 2006.285.10:19:49.25#ibcon#flushed, iclass 30, count 0 2006.285.10:19:49.25#ibcon#about to write, iclass 30, count 0 2006.285.10:19:49.25#ibcon#wrote, iclass 30, count 0 2006.285.10:19:49.25#ibcon#about to read 3, iclass 30, count 0 2006.285.10:19:49.27#ibcon#read 3, iclass 30, count 0 2006.285.10:19:49.27#ibcon#about to read 4, iclass 30, count 0 2006.285.10:19:49.27#ibcon#read 4, iclass 30, count 0 2006.285.10:19:49.27#ibcon#about to read 5, iclass 30, count 0 2006.285.10:19:49.27#ibcon#read 5, iclass 30, count 0 2006.285.10:19:49.27#ibcon#about to read 6, iclass 30, count 0 2006.285.10:19:49.27#ibcon#read 6, iclass 30, count 0 2006.285.10:19:49.27#ibcon#end of sib2, iclass 30, count 0 2006.285.10:19:49.27#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:19:49.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:19:49.27#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:19:49.27#ibcon#*before write, iclass 30, count 0 2006.285.10:19:49.27#ibcon#enter sib2, iclass 30, count 0 2006.285.10:19:49.27#ibcon#flushed, iclass 30, count 0 2006.285.10:19:49.27#ibcon#about to write, iclass 30, count 0 2006.285.10:19:49.27#ibcon#wrote, iclass 30, count 0 2006.285.10:19:49.27#ibcon#about to read 3, iclass 30, count 0 2006.285.10:19:49.31#ibcon#read 3, iclass 30, count 0 2006.285.10:19:49.31#ibcon#about to read 4, iclass 30, count 0 2006.285.10:19:49.31#ibcon#read 4, iclass 30, count 0 2006.285.10:19:49.31#ibcon#about to read 5, iclass 30, count 0 2006.285.10:19:49.31#ibcon#read 5, iclass 30, count 0 2006.285.10:19:49.31#ibcon#about to read 6, iclass 30, count 0 2006.285.10:19:49.31#ibcon#read 6, iclass 30, count 0 2006.285.10:19:49.31#ibcon#end of sib2, iclass 30, count 0 2006.285.10:19:49.31#ibcon#*after write, iclass 30, count 0 2006.285.10:19:49.31#ibcon#*before return 0, iclass 30, count 0 2006.285.10:19:49.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:19:49.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:19:49.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:19:49.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:19:49.31$vck44/va=3,7 2006.285.10:19:49.31#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.10:19:49.31#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.10:19:49.31#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:49.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:19:49.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:19:49.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:19:49.37#ibcon#enter wrdev, iclass 32, count 2 2006.285.10:19:49.37#ibcon#first serial, iclass 32, count 2 2006.285.10:19:49.37#ibcon#enter sib2, iclass 32, count 2 2006.285.10:19:49.37#ibcon#flushed, iclass 32, count 2 2006.285.10:19:49.37#ibcon#about to write, iclass 32, count 2 2006.285.10:19:49.37#ibcon#wrote, iclass 32, count 2 2006.285.10:19:49.37#ibcon#about to read 3, iclass 32, count 2 2006.285.10:19:49.39#ibcon#read 3, iclass 32, count 2 2006.285.10:19:49.39#ibcon#about to read 4, iclass 32, count 2 2006.285.10:19:49.39#ibcon#read 4, iclass 32, count 2 2006.285.10:19:49.39#ibcon#about to read 5, iclass 32, count 2 2006.285.10:19:49.39#ibcon#read 5, iclass 32, count 2 2006.285.10:19:49.39#ibcon#about to read 6, iclass 32, count 2 2006.285.10:19:49.39#ibcon#read 6, iclass 32, count 2 2006.285.10:19:49.39#ibcon#end of sib2, iclass 32, count 2 2006.285.10:19:49.39#ibcon#*mode == 0, iclass 32, count 2 2006.285.10:19:49.39#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.10:19:49.39#ibcon#[25=AT03-07\r\n] 2006.285.10:19:49.39#ibcon#*before write, iclass 32, count 2 2006.285.10:19:49.39#ibcon#enter sib2, iclass 32, count 2 2006.285.10:19:49.39#ibcon#flushed, iclass 32, count 2 2006.285.10:19:49.39#ibcon#about to write, iclass 32, count 2 2006.285.10:19:49.39#ibcon#wrote, iclass 32, count 2 2006.285.10:19:49.39#ibcon#about to read 3, iclass 32, count 2 2006.285.10:19:49.42#ibcon#read 3, iclass 32, count 2 2006.285.10:19:49.42#ibcon#about to read 4, iclass 32, count 2 2006.285.10:19:49.42#ibcon#read 4, iclass 32, count 2 2006.285.10:19:49.42#ibcon#about to read 5, iclass 32, count 2 2006.285.10:19:49.42#ibcon#read 5, iclass 32, count 2 2006.285.10:19:49.42#ibcon#about to read 6, iclass 32, count 2 2006.285.10:19:49.42#ibcon#read 6, iclass 32, count 2 2006.285.10:19:49.42#ibcon#end of sib2, iclass 32, count 2 2006.285.10:19:49.42#ibcon#*after write, iclass 32, count 2 2006.285.10:19:49.42#ibcon#*before return 0, iclass 32, count 2 2006.285.10:19:49.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:19:49.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:19:49.42#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.10:19:49.42#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:49.42#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:19:49.54#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:19:49.54#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:19:49.54#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:19:49.54#ibcon#first serial, iclass 32, count 0 2006.285.10:19:49.54#ibcon#enter sib2, iclass 32, count 0 2006.285.10:19:49.54#ibcon#flushed, iclass 32, count 0 2006.285.10:19:49.54#ibcon#about to write, iclass 32, count 0 2006.285.10:19:49.54#ibcon#wrote, iclass 32, count 0 2006.285.10:19:49.54#ibcon#about to read 3, iclass 32, count 0 2006.285.10:19:49.56#ibcon#read 3, iclass 32, count 0 2006.285.10:19:49.56#ibcon#about to read 4, iclass 32, count 0 2006.285.10:19:49.56#ibcon#read 4, iclass 32, count 0 2006.285.10:19:49.56#ibcon#about to read 5, iclass 32, count 0 2006.285.10:19:49.56#ibcon#read 5, iclass 32, count 0 2006.285.10:19:49.56#ibcon#about to read 6, iclass 32, count 0 2006.285.10:19:49.56#ibcon#read 6, iclass 32, count 0 2006.285.10:19:49.56#ibcon#end of sib2, iclass 32, count 0 2006.285.10:19:49.56#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:19:49.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:19:49.56#ibcon#[25=USB\r\n] 2006.285.10:19:49.56#ibcon#*before write, iclass 32, count 0 2006.285.10:19:49.56#ibcon#enter sib2, iclass 32, count 0 2006.285.10:19:49.56#ibcon#flushed, iclass 32, count 0 2006.285.10:19:49.56#ibcon#about to write, iclass 32, count 0 2006.285.10:19:49.56#ibcon#wrote, iclass 32, count 0 2006.285.10:19:49.56#ibcon#about to read 3, iclass 32, count 0 2006.285.10:19:49.59#ibcon#read 3, iclass 32, count 0 2006.285.10:19:49.59#ibcon#about to read 4, iclass 32, count 0 2006.285.10:19:49.59#ibcon#read 4, iclass 32, count 0 2006.285.10:19:49.59#ibcon#about to read 5, iclass 32, count 0 2006.285.10:19:49.59#ibcon#read 5, iclass 32, count 0 2006.285.10:19:49.59#ibcon#about to read 6, iclass 32, count 0 2006.285.10:19:49.59#ibcon#read 6, iclass 32, count 0 2006.285.10:19:49.59#ibcon#end of sib2, iclass 32, count 0 2006.285.10:19:49.59#ibcon#*after write, iclass 32, count 0 2006.285.10:19:49.59#ibcon#*before return 0, iclass 32, count 0 2006.285.10:19:49.59#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:19:49.59#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:19:49.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:19:49.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:19:49.59$vck44/valo=4,624.99 2006.285.10:19:49.59#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.10:19:49.59#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.10:19:49.59#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:49.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:19:49.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:19:49.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:19:49.59#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:19:49.59#ibcon#first serial, iclass 34, count 0 2006.285.10:19:49.59#ibcon#enter sib2, iclass 34, count 0 2006.285.10:19:49.59#ibcon#flushed, iclass 34, count 0 2006.285.10:19:49.59#ibcon#about to write, iclass 34, count 0 2006.285.10:19:49.59#ibcon#wrote, iclass 34, count 0 2006.285.10:19:49.59#ibcon#about to read 3, iclass 34, count 0 2006.285.10:19:49.61#ibcon#read 3, iclass 34, count 0 2006.285.10:19:49.61#ibcon#about to read 4, iclass 34, count 0 2006.285.10:19:49.61#ibcon#read 4, iclass 34, count 0 2006.285.10:19:49.61#ibcon#about to read 5, iclass 34, count 0 2006.285.10:19:49.61#ibcon#read 5, iclass 34, count 0 2006.285.10:19:49.61#ibcon#about to read 6, iclass 34, count 0 2006.285.10:19:49.61#ibcon#read 6, iclass 34, count 0 2006.285.10:19:49.61#ibcon#end of sib2, iclass 34, count 0 2006.285.10:19:49.61#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:19:49.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:19:49.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:19:49.61#ibcon#*before write, iclass 34, count 0 2006.285.10:19:49.61#ibcon#enter sib2, iclass 34, count 0 2006.285.10:19:49.61#ibcon#flushed, iclass 34, count 0 2006.285.10:19:49.61#ibcon#about to write, iclass 34, count 0 2006.285.10:19:49.61#ibcon#wrote, iclass 34, count 0 2006.285.10:19:49.61#ibcon#about to read 3, iclass 34, count 0 2006.285.10:19:49.65#ibcon#read 3, iclass 34, count 0 2006.285.10:19:49.65#ibcon#about to read 4, iclass 34, count 0 2006.285.10:19:49.65#ibcon#read 4, iclass 34, count 0 2006.285.10:19:49.65#ibcon#about to read 5, iclass 34, count 0 2006.285.10:19:49.65#ibcon#read 5, iclass 34, count 0 2006.285.10:19:49.65#ibcon#about to read 6, iclass 34, count 0 2006.285.10:19:49.65#ibcon#read 6, iclass 34, count 0 2006.285.10:19:49.65#ibcon#end of sib2, iclass 34, count 0 2006.285.10:19:49.65#ibcon#*after write, iclass 34, count 0 2006.285.10:19:49.65#ibcon#*before return 0, iclass 34, count 0 2006.285.10:19:49.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:19:49.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:19:49.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:19:49.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:19:49.65$vck44/va=4,6 2006.285.10:19:49.65#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.10:19:49.65#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.10:19:49.65#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:49.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:19:49.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:19:49.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:19:49.71#ibcon#enter wrdev, iclass 36, count 2 2006.285.10:19:49.71#ibcon#first serial, iclass 36, count 2 2006.285.10:19:49.71#ibcon#enter sib2, iclass 36, count 2 2006.285.10:19:49.71#ibcon#flushed, iclass 36, count 2 2006.285.10:19:49.71#ibcon#about to write, iclass 36, count 2 2006.285.10:19:49.71#ibcon#wrote, iclass 36, count 2 2006.285.10:19:49.71#ibcon#about to read 3, iclass 36, count 2 2006.285.10:19:49.73#ibcon#read 3, iclass 36, count 2 2006.285.10:19:49.73#ibcon#about to read 4, iclass 36, count 2 2006.285.10:19:49.73#ibcon#read 4, iclass 36, count 2 2006.285.10:19:49.73#ibcon#about to read 5, iclass 36, count 2 2006.285.10:19:49.73#ibcon#read 5, iclass 36, count 2 2006.285.10:19:49.73#ibcon#about to read 6, iclass 36, count 2 2006.285.10:19:49.73#ibcon#read 6, iclass 36, count 2 2006.285.10:19:49.73#ibcon#end of sib2, iclass 36, count 2 2006.285.10:19:49.73#ibcon#*mode == 0, iclass 36, count 2 2006.285.10:19:49.73#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.10:19:49.73#ibcon#[25=AT04-06\r\n] 2006.285.10:19:49.73#ibcon#*before write, iclass 36, count 2 2006.285.10:19:49.73#ibcon#enter sib2, iclass 36, count 2 2006.285.10:19:49.73#ibcon#flushed, iclass 36, count 2 2006.285.10:19:49.73#ibcon#about to write, iclass 36, count 2 2006.285.10:19:49.73#ibcon#wrote, iclass 36, count 2 2006.285.10:19:49.73#ibcon#about to read 3, iclass 36, count 2 2006.285.10:19:49.76#ibcon#read 3, iclass 36, count 2 2006.285.10:19:49.76#ibcon#about to read 4, iclass 36, count 2 2006.285.10:19:49.76#ibcon#read 4, iclass 36, count 2 2006.285.10:19:49.76#ibcon#about to read 5, iclass 36, count 2 2006.285.10:19:49.76#ibcon#read 5, iclass 36, count 2 2006.285.10:19:49.76#ibcon#about to read 6, iclass 36, count 2 2006.285.10:19:49.76#ibcon#read 6, iclass 36, count 2 2006.285.10:19:49.76#ibcon#end of sib2, iclass 36, count 2 2006.285.10:19:49.76#ibcon#*after write, iclass 36, count 2 2006.285.10:19:49.76#ibcon#*before return 0, iclass 36, count 2 2006.285.10:19:49.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:19:49.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:19:49.76#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.10:19:49.76#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:49.76#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:19:49.88#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:19:49.88#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:19:49.88#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:19:49.88#ibcon#first serial, iclass 36, count 0 2006.285.10:19:49.88#ibcon#enter sib2, iclass 36, count 0 2006.285.10:19:49.88#ibcon#flushed, iclass 36, count 0 2006.285.10:19:49.88#ibcon#about to write, iclass 36, count 0 2006.285.10:19:49.88#ibcon#wrote, iclass 36, count 0 2006.285.10:19:49.88#ibcon#about to read 3, iclass 36, count 0 2006.285.10:19:49.90#ibcon#read 3, iclass 36, count 0 2006.285.10:19:49.90#ibcon#about to read 4, iclass 36, count 0 2006.285.10:19:49.90#ibcon#read 4, iclass 36, count 0 2006.285.10:19:49.90#ibcon#about to read 5, iclass 36, count 0 2006.285.10:19:49.90#ibcon#read 5, iclass 36, count 0 2006.285.10:19:49.90#ibcon#about to read 6, iclass 36, count 0 2006.285.10:19:49.90#ibcon#read 6, iclass 36, count 0 2006.285.10:19:49.90#ibcon#end of sib2, iclass 36, count 0 2006.285.10:19:49.90#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:19:49.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:19:49.90#ibcon#[25=USB\r\n] 2006.285.10:19:49.90#ibcon#*before write, iclass 36, count 0 2006.285.10:19:49.90#ibcon#enter sib2, iclass 36, count 0 2006.285.10:19:49.90#ibcon#flushed, iclass 36, count 0 2006.285.10:19:49.90#ibcon#about to write, iclass 36, count 0 2006.285.10:19:49.90#ibcon#wrote, iclass 36, count 0 2006.285.10:19:49.90#ibcon#about to read 3, iclass 36, count 0 2006.285.10:19:49.93#ibcon#read 3, iclass 36, count 0 2006.285.10:19:49.93#ibcon#about to read 4, iclass 36, count 0 2006.285.10:19:49.93#ibcon#read 4, iclass 36, count 0 2006.285.10:19:49.93#ibcon#about to read 5, iclass 36, count 0 2006.285.10:19:49.93#ibcon#read 5, iclass 36, count 0 2006.285.10:19:49.93#ibcon#about to read 6, iclass 36, count 0 2006.285.10:19:49.93#ibcon#read 6, iclass 36, count 0 2006.285.10:19:49.93#ibcon#end of sib2, iclass 36, count 0 2006.285.10:19:49.93#ibcon#*after write, iclass 36, count 0 2006.285.10:19:49.93#ibcon#*before return 0, iclass 36, count 0 2006.285.10:19:49.93#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:19:49.93#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:19:49.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:19:49.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:19:49.93$vck44/valo=5,734.99 2006.285.10:19:49.93#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.10:19:49.93#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.10:19:49.93#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:49.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:19:49.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:19:49.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:19:49.93#ibcon#enter wrdev, iclass 38, count 0 2006.285.10:19:49.93#ibcon#first serial, iclass 38, count 0 2006.285.10:19:49.93#ibcon#enter sib2, iclass 38, count 0 2006.285.10:19:49.93#ibcon#flushed, iclass 38, count 0 2006.285.10:19:49.93#ibcon#about to write, iclass 38, count 0 2006.285.10:19:49.93#ibcon#wrote, iclass 38, count 0 2006.285.10:19:49.93#ibcon#about to read 3, iclass 38, count 0 2006.285.10:19:49.95#ibcon#read 3, iclass 38, count 0 2006.285.10:19:49.95#ibcon#about to read 4, iclass 38, count 0 2006.285.10:19:49.95#ibcon#read 4, iclass 38, count 0 2006.285.10:19:49.95#ibcon#about to read 5, iclass 38, count 0 2006.285.10:19:49.95#ibcon#read 5, iclass 38, count 0 2006.285.10:19:49.95#ibcon#about to read 6, iclass 38, count 0 2006.285.10:19:49.95#ibcon#read 6, iclass 38, count 0 2006.285.10:19:49.95#ibcon#end of sib2, iclass 38, count 0 2006.285.10:19:49.95#ibcon#*mode == 0, iclass 38, count 0 2006.285.10:19:49.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.10:19:49.95#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:19:49.95#ibcon#*before write, iclass 38, count 0 2006.285.10:19:49.95#ibcon#enter sib2, iclass 38, count 0 2006.285.10:19:49.95#ibcon#flushed, iclass 38, count 0 2006.285.10:19:49.95#ibcon#about to write, iclass 38, count 0 2006.285.10:19:49.95#ibcon#wrote, iclass 38, count 0 2006.285.10:19:49.95#ibcon#about to read 3, iclass 38, count 0 2006.285.10:19:49.99#ibcon#read 3, iclass 38, count 0 2006.285.10:19:49.99#ibcon#about to read 4, iclass 38, count 0 2006.285.10:19:49.99#ibcon#read 4, iclass 38, count 0 2006.285.10:19:49.99#ibcon#about to read 5, iclass 38, count 0 2006.285.10:19:49.99#ibcon#read 5, iclass 38, count 0 2006.285.10:19:49.99#ibcon#about to read 6, iclass 38, count 0 2006.285.10:19:49.99#ibcon#read 6, iclass 38, count 0 2006.285.10:19:49.99#ibcon#end of sib2, iclass 38, count 0 2006.285.10:19:49.99#ibcon#*after write, iclass 38, count 0 2006.285.10:19:49.99#ibcon#*before return 0, iclass 38, count 0 2006.285.10:19:49.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:19:49.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:19:49.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.10:19:49.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.10:19:49.99$vck44/va=5,3 2006.285.10:19:49.99#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.10:19:49.99#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.10:19:49.99#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:49.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:19:50.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:19:50.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:19:50.05#ibcon#enter wrdev, iclass 40, count 2 2006.285.10:19:50.05#ibcon#first serial, iclass 40, count 2 2006.285.10:19:50.05#ibcon#enter sib2, iclass 40, count 2 2006.285.10:19:50.05#ibcon#flushed, iclass 40, count 2 2006.285.10:19:50.05#ibcon#about to write, iclass 40, count 2 2006.285.10:19:50.05#ibcon#wrote, iclass 40, count 2 2006.285.10:19:50.05#ibcon#about to read 3, iclass 40, count 2 2006.285.10:19:50.07#ibcon#read 3, iclass 40, count 2 2006.285.10:19:50.07#ibcon#about to read 4, iclass 40, count 2 2006.285.10:19:50.07#ibcon#read 4, iclass 40, count 2 2006.285.10:19:50.07#ibcon#about to read 5, iclass 40, count 2 2006.285.10:19:50.07#ibcon#read 5, iclass 40, count 2 2006.285.10:19:50.07#ibcon#about to read 6, iclass 40, count 2 2006.285.10:19:50.07#ibcon#read 6, iclass 40, count 2 2006.285.10:19:50.07#ibcon#end of sib2, iclass 40, count 2 2006.285.10:19:50.07#ibcon#*mode == 0, iclass 40, count 2 2006.285.10:19:50.07#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.10:19:50.07#ibcon#[25=AT05-03\r\n] 2006.285.10:19:50.07#ibcon#*before write, iclass 40, count 2 2006.285.10:19:50.07#ibcon#enter sib2, iclass 40, count 2 2006.285.10:19:50.07#ibcon#flushed, iclass 40, count 2 2006.285.10:19:50.07#ibcon#about to write, iclass 40, count 2 2006.285.10:19:50.07#ibcon#wrote, iclass 40, count 2 2006.285.10:19:50.07#ibcon#about to read 3, iclass 40, count 2 2006.285.10:19:50.10#ibcon#read 3, iclass 40, count 2 2006.285.10:19:50.10#ibcon#about to read 4, iclass 40, count 2 2006.285.10:19:50.10#ibcon#read 4, iclass 40, count 2 2006.285.10:19:50.10#ibcon#about to read 5, iclass 40, count 2 2006.285.10:19:50.10#ibcon#read 5, iclass 40, count 2 2006.285.10:19:50.10#ibcon#about to read 6, iclass 40, count 2 2006.285.10:19:50.10#ibcon#read 6, iclass 40, count 2 2006.285.10:19:50.10#ibcon#end of sib2, iclass 40, count 2 2006.285.10:19:50.10#ibcon#*after write, iclass 40, count 2 2006.285.10:19:50.10#ibcon#*before return 0, iclass 40, count 2 2006.285.10:19:50.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:19:50.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:19:50.10#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.10:19:50.10#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:50.10#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:19:50.22#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:19:50.22#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:19:50.22#ibcon#enter wrdev, iclass 40, count 0 2006.285.10:19:50.22#ibcon#first serial, iclass 40, count 0 2006.285.10:19:50.22#ibcon#enter sib2, iclass 40, count 0 2006.285.10:19:50.22#ibcon#flushed, iclass 40, count 0 2006.285.10:19:50.22#ibcon#about to write, iclass 40, count 0 2006.285.10:19:50.22#ibcon#wrote, iclass 40, count 0 2006.285.10:19:50.22#ibcon#about to read 3, iclass 40, count 0 2006.285.10:19:50.24#ibcon#read 3, iclass 40, count 0 2006.285.10:19:50.24#ibcon#about to read 4, iclass 40, count 0 2006.285.10:19:50.24#ibcon#read 4, iclass 40, count 0 2006.285.10:19:50.24#ibcon#about to read 5, iclass 40, count 0 2006.285.10:19:50.24#ibcon#read 5, iclass 40, count 0 2006.285.10:19:50.24#ibcon#about to read 6, iclass 40, count 0 2006.285.10:19:50.24#ibcon#read 6, iclass 40, count 0 2006.285.10:19:50.24#ibcon#end of sib2, iclass 40, count 0 2006.285.10:19:50.24#ibcon#*mode == 0, iclass 40, count 0 2006.285.10:19:50.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.10:19:50.24#ibcon#[25=USB\r\n] 2006.285.10:19:50.24#ibcon#*before write, iclass 40, count 0 2006.285.10:19:50.24#ibcon#enter sib2, iclass 40, count 0 2006.285.10:19:50.24#ibcon#flushed, iclass 40, count 0 2006.285.10:19:50.24#ibcon#about to write, iclass 40, count 0 2006.285.10:19:50.24#ibcon#wrote, iclass 40, count 0 2006.285.10:19:50.24#ibcon#about to read 3, iclass 40, count 0 2006.285.10:19:50.27#ibcon#read 3, iclass 40, count 0 2006.285.10:19:50.27#ibcon#about to read 4, iclass 40, count 0 2006.285.10:19:50.27#ibcon#read 4, iclass 40, count 0 2006.285.10:19:50.27#ibcon#about to read 5, iclass 40, count 0 2006.285.10:19:50.27#ibcon#read 5, iclass 40, count 0 2006.285.10:19:50.27#ibcon#about to read 6, iclass 40, count 0 2006.285.10:19:50.27#ibcon#read 6, iclass 40, count 0 2006.285.10:19:50.27#ibcon#end of sib2, iclass 40, count 0 2006.285.10:19:50.27#ibcon#*after write, iclass 40, count 0 2006.285.10:19:50.27#ibcon#*before return 0, iclass 40, count 0 2006.285.10:19:50.27#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:19:50.27#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:19:50.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.10:19:50.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.10:19:50.27$vck44/valo=6,814.99 2006.285.10:19:50.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.10:19:50.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.10:19:50.27#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:50.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:19:50.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:19:50.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:19:50.27#ibcon#enter wrdev, iclass 4, count 0 2006.285.10:19:50.27#ibcon#first serial, iclass 4, count 0 2006.285.10:19:50.27#ibcon#enter sib2, iclass 4, count 0 2006.285.10:19:50.27#ibcon#flushed, iclass 4, count 0 2006.285.10:19:50.27#ibcon#about to write, iclass 4, count 0 2006.285.10:19:50.27#ibcon#wrote, iclass 4, count 0 2006.285.10:19:50.27#ibcon#about to read 3, iclass 4, count 0 2006.285.10:19:50.29#ibcon#read 3, iclass 4, count 0 2006.285.10:19:50.29#ibcon#about to read 4, iclass 4, count 0 2006.285.10:19:50.29#ibcon#read 4, iclass 4, count 0 2006.285.10:19:50.29#ibcon#about to read 5, iclass 4, count 0 2006.285.10:19:50.29#ibcon#read 5, iclass 4, count 0 2006.285.10:19:50.29#ibcon#about to read 6, iclass 4, count 0 2006.285.10:19:50.29#ibcon#read 6, iclass 4, count 0 2006.285.10:19:50.29#ibcon#end of sib2, iclass 4, count 0 2006.285.10:19:50.29#ibcon#*mode == 0, iclass 4, count 0 2006.285.10:19:50.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.10:19:50.29#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:19:50.29#ibcon#*before write, iclass 4, count 0 2006.285.10:19:50.29#ibcon#enter sib2, iclass 4, count 0 2006.285.10:19:50.29#ibcon#flushed, iclass 4, count 0 2006.285.10:19:50.29#ibcon#about to write, iclass 4, count 0 2006.285.10:19:50.29#ibcon#wrote, iclass 4, count 0 2006.285.10:19:50.29#ibcon#about to read 3, iclass 4, count 0 2006.285.10:19:50.33#ibcon#read 3, iclass 4, count 0 2006.285.10:19:50.33#ibcon#about to read 4, iclass 4, count 0 2006.285.10:19:50.33#ibcon#read 4, iclass 4, count 0 2006.285.10:19:50.33#ibcon#about to read 5, iclass 4, count 0 2006.285.10:19:50.33#ibcon#read 5, iclass 4, count 0 2006.285.10:19:50.33#ibcon#about to read 6, iclass 4, count 0 2006.285.10:19:50.33#ibcon#read 6, iclass 4, count 0 2006.285.10:19:50.33#ibcon#end of sib2, iclass 4, count 0 2006.285.10:19:50.33#ibcon#*after write, iclass 4, count 0 2006.285.10:19:50.33#ibcon#*before return 0, iclass 4, count 0 2006.285.10:19:50.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:19:50.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:19:50.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.10:19:50.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.10:19:50.33$vck44/va=6,4 2006.285.10:19:50.33#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.10:19:50.33#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.10:19:50.33#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:50.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:19:50.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:19:50.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:19:50.39#ibcon#enter wrdev, iclass 6, count 2 2006.285.10:19:50.39#ibcon#first serial, iclass 6, count 2 2006.285.10:19:50.39#ibcon#enter sib2, iclass 6, count 2 2006.285.10:19:50.39#ibcon#flushed, iclass 6, count 2 2006.285.10:19:50.39#ibcon#about to write, iclass 6, count 2 2006.285.10:19:50.39#ibcon#wrote, iclass 6, count 2 2006.285.10:19:50.39#ibcon#about to read 3, iclass 6, count 2 2006.285.10:19:50.41#ibcon#read 3, iclass 6, count 2 2006.285.10:19:50.41#ibcon#about to read 4, iclass 6, count 2 2006.285.10:19:50.41#ibcon#read 4, iclass 6, count 2 2006.285.10:19:50.41#ibcon#about to read 5, iclass 6, count 2 2006.285.10:19:50.41#ibcon#read 5, iclass 6, count 2 2006.285.10:19:50.41#ibcon#about to read 6, iclass 6, count 2 2006.285.10:19:50.41#ibcon#read 6, iclass 6, count 2 2006.285.10:19:50.41#ibcon#end of sib2, iclass 6, count 2 2006.285.10:19:50.41#ibcon#*mode == 0, iclass 6, count 2 2006.285.10:19:50.41#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.10:19:50.41#ibcon#[25=AT06-04\r\n] 2006.285.10:19:50.41#ibcon#*before write, iclass 6, count 2 2006.285.10:19:50.41#ibcon#enter sib2, iclass 6, count 2 2006.285.10:19:50.41#ibcon#flushed, iclass 6, count 2 2006.285.10:19:50.41#ibcon#about to write, iclass 6, count 2 2006.285.10:19:50.41#ibcon#wrote, iclass 6, count 2 2006.285.10:19:50.41#ibcon#about to read 3, iclass 6, count 2 2006.285.10:19:50.44#ibcon#read 3, iclass 6, count 2 2006.285.10:19:50.44#ibcon#about to read 4, iclass 6, count 2 2006.285.10:19:50.44#ibcon#read 4, iclass 6, count 2 2006.285.10:19:50.44#ibcon#about to read 5, iclass 6, count 2 2006.285.10:19:50.44#ibcon#read 5, iclass 6, count 2 2006.285.10:19:50.44#ibcon#about to read 6, iclass 6, count 2 2006.285.10:19:50.44#ibcon#read 6, iclass 6, count 2 2006.285.10:19:50.44#ibcon#end of sib2, iclass 6, count 2 2006.285.10:19:50.44#ibcon#*after write, iclass 6, count 2 2006.285.10:19:50.44#ibcon#*before return 0, iclass 6, count 2 2006.285.10:19:50.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:19:50.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:19:50.44#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.10:19:50.44#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:50.44#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:19:50.56#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:19:50.56#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:19:50.56#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:19:50.56#ibcon#first serial, iclass 6, count 0 2006.285.10:19:50.56#ibcon#enter sib2, iclass 6, count 0 2006.285.10:19:50.56#ibcon#flushed, iclass 6, count 0 2006.285.10:19:50.56#ibcon#about to write, iclass 6, count 0 2006.285.10:19:50.56#ibcon#wrote, iclass 6, count 0 2006.285.10:19:50.56#ibcon#about to read 3, iclass 6, count 0 2006.285.10:19:50.58#ibcon#read 3, iclass 6, count 0 2006.285.10:19:50.58#ibcon#about to read 4, iclass 6, count 0 2006.285.10:19:50.58#ibcon#read 4, iclass 6, count 0 2006.285.10:19:50.58#ibcon#about to read 5, iclass 6, count 0 2006.285.10:19:50.58#ibcon#read 5, iclass 6, count 0 2006.285.10:19:50.58#ibcon#about to read 6, iclass 6, count 0 2006.285.10:19:50.58#ibcon#read 6, iclass 6, count 0 2006.285.10:19:50.58#ibcon#end of sib2, iclass 6, count 0 2006.285.10:19:50.58#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:19:50.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:19:50.58#ibcon#[25=USB\r\n] 2006.285.10:19:50.58#ibcon#*before write, iclass 6, count 0 2006.285.10:19:50.58#ibcon#enter sib2, iclass 6, count 0 2006.285.10:19:50.58#ibcon#flushed, iclass 6, count 0 2006.285.10:19:50.58#ibcon#about to write, iclass 6, count 0 2006.285.10:19:50.58#ibcon#wrote, iclass 6, count 0 2006.285.10:19:50.58#ibcon#about to read 3, iclass 6, count 0 2006.285.10:19:50.61#ibcon#read 3, iclass 6, count 0 2006.285.10:19:50.61#ibcon#about to read 4, iclass 6, count 0 2006.285.10:19:50.61#ibcon#read 4, iclass 6, count 0 2006.285.10:19:50.61#ibcon#about to read 5, iclass 6, count 0 2006.285.10:19:50.61#ibcon#read 5, iclass 6, count 0 2006.285.10:19:50.61#ibcon#about to read 6, iclass 6, count 0 2006.285.10:19:50.61#ibcon#read 6, iclass 6, count 0 2006.285.10:19:50.61#ibcon#end of sib2, iclass 6, count 0 2006.285.10:19:50.61#ibcon#*after write, iclass 6, count 0 2006.285.10:19:50.61#ibcon#*before return 0, iclass 6, count 0 2006.285.10:19:50.61#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:19:50.61#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:19:50.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:19:50.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:19:50.61$vck44/valo=7,864.99 2006.285.10:19:50.61#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.10:19:50.61#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.10:19:50.61#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:50.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:19:50.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:19:50.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:19:50.61#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:19:50.61#ibcon#first serial, iclass 10, count 0 2006.285.10:19:50.61#ibcon#enter sib2, iclass 10, count 0 2006.285.10:19:50.61#ibcon#flushed, iclass 10, count 0 2006.285.10:19:50.61#ibcon#about to write, iclass 10, count 0 2006.285.10:19:50.61#ibcon#wrote, iclass 10, count 0 2006.285.10:19:50.61#ibcon#about to read 3, iclass 10, count 0 2006.285.10:19:50.63#ibcon#read 3, iclass 10, count 0 2006.285.10:19:50.63#ibcon#about to read 4, iclass 10, count 0 2006.285.10:19:50.63#ibcon#read 4, iclass 10, count 0 2006.285.10:19:50.63#ibcon#about to read 5, iclass 10, count 0 2006.285.10:19:50.63#ibcon#read 5, iclass 10, count 0 2006.285.10:19:50.63#ibcon#about to read 6, iclass 10, count 0 2006.285.10:19:50.63#ibcon#read 6, iclass 10, count 0 2006.285.10:19:50.63#ibcon#end of sib2, iclass 10, count 0 2006.285.10:19:50.63#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:19:50.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:19:50.63#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:19:50.63#ibcon#*before write, iclass 10, count 0 2006.285.10:19:50.63#ibcon#enter sib2, iclass 10, count 0 2006.285.10:19:50.63#ibcon#flushed, iclass 10, count 0 2006.285.10:19:50.63#ibcon#about to write, iclass 10, count 0 2006.285.10:19:50.63#ibcon#wrote, iclass 10, count 0 2006.285.10:19:50.63#ibcon#about to read 3, iclass 10, count 0 2006.285.10:19:50.67#ibcon#read 3, iclass 10, count 0 2006.285.10:19:50.67#ibcon#about to read 4, iclass 10, count 0 2006.285.10:19:50.67#ibcon#read 4, iclass 10, count 0 2006.285.10:19:50.67#ibcon#about to read 5, iclass 10, count 0 2006.285.10:19:50.67#ibcon#read 5, iclass 10, count 0 2006.285.10:19:50.67#ibcon#about to read 6, iclass 10, count 0 2006.285.10:19:50.67#ibcon#read 6, iclass 10, count 0 2006.285.10:19:50.67#ibcon#end of sib2, iclass 10, count 0 2006.285.10:19:50.67#ibcon#*after write, iclass 10, count 0 2006.285.10:19:50.67#ibcon#*before return 0, iclass 10, count 0 2006.285.10:19:50.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:19:50.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:19:50.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:19:50.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:19:50.67$vck44/va=7,4 2006.285.10:19:50.67#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.10:19:50.67#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.10:19:50.67#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:50.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:19:50.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:19:50.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:19:50.73#ibcon#enter wrdev, iclass 12, count 2 2006.285.10:19:50.73#ibcon#first serial, iclass 12, count 2 2006.285.10:19:50.73#ibcon#enter sib2, iclass 12, count 2 2006.285.10:19:50.73#ibcon#flushed, iclass 12, count 2 2006.285.10:19:50.73#ibcon#about to write, iclass 12, count 2 2006.285.10:19:50.73#ibcon#wrote, iclass 12, count 2 2006.285.10:19:50.73#ibcon#about to read 3, iclass 12, count 2 2006.285.10:19:50.75#ibcon#read 3, iclass 12, count 2 2006.285.10:19:50.75#ibcon#about to read 4, iclass 12, count 2 2006.285.10:19:50.75#ibcon#read 4, iclass 12, count 2 2006.285.10:19:50.75#ibcon#about to read 5, iclass 12, count 2 2006.285.10:19:50.75#ibcon#read 5, iclass 12, count 2 2006.285.10:19:50.75#ibcon#about to read 6, iclass 12, count 2 2006.285.10:19:50.75#ibcon#read 6, iclass 12, count 2 2006.285.10:19:50.75#ibcon#end of sib2, iclass 12, count 2 2006.285.10:19:50.75#ibcon#*mode == 0, iclass 12, count 2 2006.285.10:19:50.75#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.10:19:50.75#ibcon#[25=AT07-04\r\n] 2006.285.10:19:50.75#ibcon#*before write, iclass 12, count 2 2006.285.10:19:50.75#ibcon#enter sib2, iclass 12, count 2 2006.285.10:19:50.75#ibcon#flushed, iclass 12, count 2 2006.285.10:19:50.75#ibcon#about to write, iclass 12, count 2 2006.285.10:19:50.75#ibcon#wrote, iclass 12, count 2 2006.285.10:19:50.75#ibcon#about to read 3, iclass 12, count 2 2006.285.10:19:50.78#ibcon#read 3, iclass 12, count 2 2006.285.10:19:50.78#ibcon#about to read 4, iclass 12, count 2 2006.285.10:19:50.78#ibcon#read 4, iclass 12, count 2 2006.285.10:19:50.78#ibcon#about to read 5, iclass 12, count 2 2006.285.10:19:50.78#ibcon#read 5, iclass 12, count 2 2006.285.10:19:50.78#ibcon#about to read 6, iclass 12, count 2 2006.285.10:19:50.78#ibcon#read 6, iclass 12, count 2 2006.285.10:19:50.78#ibcon#end of sib2, iclass 12, count 2 2006.285.10:19:50.78#ibcon#*after write, iclass 12, count 2 2006.285.10:19:50.78#ibcon#*before return 0, iclass 12, count 2 2006.285.10:19:50.78#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:19:50.78#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:19:50.78#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.10:19:50.78#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:50.78#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:19:50.90#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:19:50.90#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:19:50.90#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:19:50.90#ibcon#first serial, iclass 12, count 0 2006.285.10:19:50.90#ibcon#enter sib2, iclass 12, count 0 2006.285.10:19:50.90#ibcon#flushed, iclass 12, count 0 2006.285.10:19:50.90#ibcon#about to write, iclass 12, count 0 2006.285.10:19:50.90#ibcon#wrote, iclass 12, count 0 2006.285.10:19:50.90#ibcon#about to read 3, iclass 12, count 0 2006.285.10:19:50.92#ibcon#read 3, iclass 12, count 0 2006.285.10:19:50.92#ibcon#about to read 4, iclass 12, count 0 2006.285.10:19:50.92#ibcon#read 4, iclass 12, count 0 2006.285.10:19:50.92#ibcon#about to read 5, iclass 12, count 0 2006.285.10:19:50.92#ibcon#read 5, iclass 12, count 0 2006.285.10:19:50.92#ibcon#about to read 6, iclass 12, count 0 2006.285.10:19:50.92#ibcon#read 6, iclass 12, count 0 2006.285.10:19:50.92#ibcon#end of sib2, iclass 12, count 0 2006.285.10:19:50.92#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:19:50.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:19:50.92#ibcon#[25=USB\r\n] 2006.285.10:19:50.92#ibcon#*before write, iclass 12, count 0 2006.285.10:19:50.92#ibcon#enter sib2, iclass 12, count 0 2006.285.10:19:50.92#ibcon#flushed, iclass 12, count 0 2006.285.10:19:50.92#ibcon#about to write, iclass 12, count 0 2006.285.10:19:50.92#ibcon#wrote, iclass 12, count 0 2006.285.10:19:50.92#ibcon#about to read 3, iclass 12, count 0 2006.285.10:19:50.95#ibcon#read 3, iclass 12, count 0 2006.285.10:19:50.95#ibcon#about to read 4, iclass 12, count 0 2006.285.10:19:50.95#ibcon#read 4, iclass 12, count 0 2006.285.10:19:50.95#ibcon#about to read 5, iclass 12, count 0 2006.285.10:19:50.95#ibcon#read 5, iclass 12, count 0 2006.285.10:19:50.95#ibcon#about to read 6, iclass 12, count 0 2006.285.10:19:50.95#ibcon#read 6, iclass 12, count 0 2006.285.10:19:50.95#ibcon#end of sib2, iclass 12, count 0 2006.285.10:19:50.95#ibcon#*after write, iclass 12, count 0 2006.285.10:19:50.95#ibcon#*before return 0, iclass 12, count 0 2006.285.10:19:50.95#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:19:50.95#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:19:50.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:19:50.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:19:50.95$vck44/valo=8,884.99 2006.285.10:19:50.95#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.10:19:50.95#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.10:19:50.95#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:50.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:19:50.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:19:50.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:19:50.95#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:19:50.95#ibcon#first serial, iclass 14, count 0 2006.285.10:19:50.95#ibcon#enter sib2, iclass 14, count 0 2006.285.10:19:50.95#ibcon#flushed, iclass 14, count 0 2006.285.10:19:50.95#ibcon#about to write, iclass 14, count 0 2006.285.10:19:50.95#ibcon#wrote, iclass 14, count 0 2006.285.10:19:50.95#ibcon#about to read 3, iclass 14, count 0 2006.285.10:19:50.97#ibcon#read 3, iclass 14, count 0 2006.285.10:19:50.97#ibcon#about to read 4, iclass 14, count 0 2006.285.10:19:50.97#ibcon#read 4, iclass 14, count 0 2006.285.10:19:50.97#ibcon#about to read 5, iclass 14, count 0 2006.285.10:19:50.97#ibcon#read 5, iclass 14, count 0 2006.285.10:19:50.97#ibcon#about to read 6, iclass 14, count 0 2006.285.10:19:50.97#ibcon#read 6, iclass 14, count 0 2006.285.10:19:50.97#ibcon#end of sib2, iclass 14, count 0 2006.285.10:19:50.97#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:19:50.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:19:50.97#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:19:50.97#ibcon#*before write, iclass 14, count 0 2006.285.10:19:50.97#ibcon#enter sib2, iclass 14, count 0 2006.285.10:19:50.97#ibcon#flushed, iclass 14, count 0 2006.285.10:19:50.97#ibcon#about to write, iclass 14, count 0 2006.285.10:19:50.97#ibcon#wrote, iclass 14, count 0 2006.285.10:19:50.97#ibcon#about to read 3, iclass 14, count 0 2006.285.10:19:51.01#ibcon#read 3, iclass 14, count 0 2006.285.10:19:51.01#ibcon#about to read 4, iclass 14, count 0 2006.285.10:19:51.01#ibcon#read 4, iclass 14, count 0 2006.285.10:19:51.01#ibcon#about to read 5, iclass 14, count 0 2006.285.10:19:51.01#ibcon#read 5, iclass 14, count 0 2006.285.10:19:51.01#ibcon#about to read 6, iclass 14, count 0 2006.285.10:19:51.01#ibcon#read 6, iclass 14, count 0 2006.285.10:19:51.01#ibcon#end of sib2, iclass 14, count 0 2006.285.10:19:51.01#ibcon#*after write, iclass 14, count 0 2006.285.10:19:51.01#ibcon#*before return 0, iclass 14, count 0 2006.285.10:19:51.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:19:51.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:19:51.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:19:51.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:19:51.01$vck44/va=8,3 2006.285.10:19:51.01#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.10:19:51.01#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.10:19:51.01#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:51.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:19:51.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:19:51.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:19:51.07#ibcon#enter wrdev, iclass 16, count 2 2006.285.10:19:51.07#ibcon#first serial, iclass 16, count 2 2006.285.10:19:51.07#ibcon#enter sib2, iclass 16, count 2 2006.285.10:19:51.07#ibcon#flushed, iclass 16, count 2 2006.285.10:19:51.07#ibcon#about to write, iclass 16, count 2 2006.285.10:19:51.07#ibcon#wrote, iclass 16, count 2 2006.285.10:19:51.07#ibcon#about to read 3, iclass 16, count 2 2006.285.10:19:51.09#ibcon#read 3, iclass 16, count 2 2006.285.10:19:51.09#ibcon#about to read 4, iclass 16, count 2 2006.285.10:19:51.09#ibcon#read 4, iclass 16, count 2 2006.285.10:19:51.09#ibcon#about to read 5, iclass 16, count 2 2006.285.10:19:51.09#ibcon#read 5, iclass 16, count 2 2006.285.10:19:51.09#ibcon#about to read 6, iclass 16, count 2 2006.285.10:19:51.09#ibcon#read 6, iclass 16, count 2 2006.285.10:19:51.09#ibcon#end of sib2, iclass 16, count 2 2006.285.10:19:51.09#ibcon#*mode == 0, iclass 16, count 2 2006.285.10:19:51.09#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.10:19:51.09#ibcon#[25=AT08-03\r\n] 2006.285.10:19:51.09#ibcon#*before write, iclass 16, count 2 2006.285.10:19:51.09#ibcon#enter sib2, iclass 16, count 2 2006.285.10:19:51.09#ibcon#flushed, iclass 16, count 2 2006.285.10:19:51.09#ibcon#about to write, iclass 16, count 2 2006.285.10:19:51.09#ibcon#wrote, iclass 16, count 2 2006.285.10:19:51.09#ibcon#about to read 3, iclass 16, count 2 2006.285.10:19:51.12#ibcon#read 3, iclass 16, count 2 2006.285.10:19:51.12#ibcon#about to read 4, iclass 16, count 2 2006.285.10:19:51.12#ibcon#read 4, iclass 16, count 2 2006.285.10:19:51.12#ibcon#about to read 5, iclass 16, count 2 2006.285.10:19:51.12#ibcon#read 5, iclass 16, count 2 2006.285.10:19:51.12#ibcon#about to read 6, iclass 16, count 2 2006.285.10:19:51.12#ibcon#read 6, iclass 16, count 2 2006.285.10:19:51.12#ibcon#end of sib2, iclass 16, count 2 2006.285.10:19:51.12#ibcon#*after write, iclass 16, count 2 2006.285.10:19:51.12#ibcon#*before return 0, iclass 16, count 2 2006.285.10:19:51.12#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:19:51.12#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:19:51.12#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.10:19:51.12#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:51.12#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:19:51.24#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:19:51.24#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:19:51.24#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:19:51.24#ibcon#first serial, iclass 16, count 0 2006.285.10:19:51.24#ibcon#enter sib2, iclass 16, count 0 2006.285.10:19:51.24#ibcon#flushed, iclass 16, count 0 2006.285.10:19:51.24#ibcon#about to write, iclass 16, count 0 2006.285.10:19:51.24#ibcon#wrote, iclass 16, count 0 2006.285.10:19:51.24#ibcon#about to read 3, iclass 16, count 0 2006.285.10:19:51.26#ibcon#read 3, iclass 16, count 0 2006.285.10:19:51.26#ibcon#about to read 4, iclass 16, count 0 2006.285.10:19:51.26#ibcon#read 4, iclass 16, count 0 2006.285.10:19:51.26#ibcon#about to read 5, iclass 16, count 0 2006.285.10:19:51.26#ibcon#read 5, iclass 16, count 0 2006.285.10:19:51.26#ibcon#about to read 6, iclass 16, count 0 2006.285.10:19:51.26#ibcon#read 6, iclass 16, count 0 2006.285.10:19:51.26#ibcon#end of sib2, iclass 16, count 0 2006.285.10:19:51.26#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:19:51.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:19:51.26#ibcon#[25=USB\r\n] 2006.285.10:19:51.26#ibcon#*before write, iclass 16, count 0 2006.285.10:19:51.26#ibcon#enter sib2, iclass 16, count 0 2006.285.10:19:51.26#ibcon#flushed, iclass 16, count 0 2006.285.10:19:51.26#ibcon#about to write, iclass 16, count 0 2006.285.10:19:51.26#ibcon#wrote, iclass 16, count 0 2006.285.10:19:51.26#ibcon#about to read 3, iclass 16, count 0 2006.285.10:19:51.29#ibcon#read 3, iclass 16, count 0 2006.285.10:19:51.29#ibcon#about to read 4, iclass 16, count 0 2006.285.10:19:51.29#ibcon#read 4, iclass 16, count 0 2006.285.10:19:51.29#ibcon#about to read 5, iclass 16, count 0 2006.285.10:19:51.29#ibcon#read 5, iclass 16, count 0 2006.285.10:19:51.29#ibcon#about to read 6, iclass 16, count 0 2006.285.10:19:51.29#ibcon#read 6, iclass 16, count 0 2006.285.10:19:51.29#ibcon#end of sib2, iclass 16, count 0 2006.285.10:19:51.29#ibcon#*after write, iclass 16, count 0 2006.285.10:19:51.29#ibcon#*before return 0, iclass 16, count 0 2006.285.10:19:51.29#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:19:51.29#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:19:51.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:19:51.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:19:51.29$vck44/vblo=1,629.99 2006.285.10:19:51.29#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.10:19:51.29#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.10:19:51.29#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:51.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:19:51.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:19:51.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:19:51.29#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:19:51.29#ibcon#first serial, iclass 18, count 0 2006.285.10:19:51.29#ibcon#enter sib2, iclass 18, count 0 2006.285.10:19:51.29#ibcon#flushed, iclass 18, count 0 2006.285.10:19:51.29#ibcon#about to write, iclass 18, count 0 2006.285.10:19:51.29#ibcon#wrote, iclass 18, count 0 2006.285.10:19:51.29#ibcon#about to read 3, iclass 18, count 0 2006.285.10:19:51.31#ibcon#read 3, iclass 18, count 0 2006.285.10:19:51.31#ibcon#about to read 4, iclass 18, count 0 2006.285.10:19:51.31#ibcon#read 4, iclass 18, count 0 2006.285.10:19:51.31#ibcon#about to read 5, iclass 18, count 0 2006.285.10:19:51.31#ibcon#read 5, iclass 18, count 0 2006.285.10:19:51.31#ibcon#about to read 6, iclass 18, count 0 2006.285.10:19:51.31#ibcon#read 6, iclass 18, count 0 2006.285.10:19:51.31#ibcon#end of sib2, iclass 18, count 0 2006.285.10:19:51.31#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:19:51.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:19:51.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:19:51.31#ibcon#*before write, iclass 18, count 0 2006.285.10:19:51.31#ibcon#enter sib2, iclass 18, count 0 2006.285.10:19:51.31#ibcon#flushed, iclass 18, count 0 2006.285.10:19:51.31#ibcon#about to write, iclass 18, count 0 2006.285.10:19:51.31#ibcon#wrote, iclass 18, count 0 2006.285.10:19:51.31#ibcon#about to read 3, iclass 18, count 0 2006.285.10:19:51.35#ibcon#read 3, iclass 18, count 0 2006.285.10:19:51.35#ibcon#about to read 4, iclass 18, count 0 2006.285.10:19:51.35#ibcon#read 4, iclass 18, count 0 2006.285.10:19:51.35#ibcon#about to read 5, iclass 18, count 0 2006.285.10:19:51.35#ibcon#read 5, iclass 18, count 0 2006.285.10:19:51.35#ibcon#about to read 6, iclass 18, count 0 2006.285.10:19:51.35#ibcon#read 6, iclass 18, count 0 2006.285.10:19:51.35#ibcon#end of sib2, iclass 18, count 0 2006.285.10:19:51.35#ibcon#*after write, iclass 18, count 0 2006.285.10:19:51.35#ibcon#*before return 0, iclass 18, count 0 2006.285.10:19:51.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:19:51.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:19:51.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:19:51.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:19:51.35$vck44/vb=1,4 2006.285.10:19:51.35#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.10:19:51.35#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.10:19:51.35#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:51.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:19:51.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:19:51.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:19:51.35#ibcon#enter wrdev, iclass 20, count 2 2006.285.10:19:51.35#ibcon#first serial, iclass 20, count 2 2006.285.10:19:51.35#ibcon#enter sib2, iclass 20, count 2 2006.285.10:19:51.35#ibcon#flushed, iclass 20, count 2 2006.285.10:19:51.35#ibcon#about to write, iclass 20, count 2 2006.285.10:19:51.35#ibcon#wrote, iclass 20, count 2 2006.285.10:19:51.35#ibcon#about to read 3, iclass 20, count 2 2006.285.10:19:51.37#ibcon#read 3, iclass 20, count 2 2006.285.10:19:51.37#ibcon#about to read 4, iclass 20, count 2 2006.285.10:19:51.37#ibcon#read 4, iclass 20, count 2 2006.285.10:19:51.37#ibcon#about to read 5, iclass 20, count 2 2006.285.10:19:51.37#ibcon#read 5, iclass 20, count 2 2006.285.10:19:51.37#ibcon#about to read 6, iclass 20, count 2 2006.285.10:19:51.37#ibcon#read 6, iclass 20, count 2 2006.285.10:19:51.37#ibcon#end of sib2, iclass 20, count 2 2006.285.10:19:51.37#ibcon#*mode == 0, iclass 20, count 2 2006.285.10:19:51.37#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.10:19:51.37#ibcon#[27=AT01-04\r\n] 2006.285.10:19:51.37#ibcon#*before write, iclass 20, count 2 2006.285.10:19:51.37#ibcon#enter sib2, iclass 20, count 2 2006.285.10:19:51.37#ibcon#flushed, iclass 20, count 2 2006.285.10:19:51.37#ibcon#about to write, iclass 20, count 2 2006.285.10:19:51.37#ibcon#wrote, iclass 20, count 2 2006.285.10:19:51.37#ibcon#about to read 3, iclass 20, count 2 2006.285.10:19:51.40#ibcon#read 3, iclass 20, count 2 2006.285.10:19:51.40#ibcon#about to read 4, iclass 20, count 2 2006.285.10:19:51.40#ibcon#read 4, iclass 20, count 2 2006.285.10:19:51.40#ibcon#about to read 5, iclass 20, count 2 2006.285.10:19:51.40#ibcon#read 5, iclass 20, count 2 2006.285.10:19:51.40#ibcon#about to read 6, iclass 20, count 2 2006.285.10:19:51.40#ibcon#read 6, iclass 20, count 2 2006.285.10:19:51.40#ibcon#end of sib2, iclass 20, count 2 2006.285.10:19:51.40#ibcon#*after write, iclass 20, count 2 2006.285.10:19:51.40#ibcon#*before return 0, iclass 20, count 2 2006.285.10:19:51.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:19:51.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:19:51.40#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.10:19:51.40#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:51.40#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:19:51.52#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:19:51.52#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:19:51.52#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:19:51.52#ibcon#first serial, iclass 20, count 0 2006.285.10:19:51.52#ibcon#enter sib2, iclass 20, count 0 2006.285.10:19:51.52#ibcon#flushed, iclass 20, count 0 2006.285.10:19:51.52#ibcon#about to write, iclass 20, count 0 2006.285.10:19:51.52#ibcon#wrote, iclass 20, count 0 2006.285.10:19:51.52#ibcon#about to read 3, iclass 20, count 0 2006.285.10:19:51.54#ibcon#read 3, iclass 20, count 0 2006.285.10:19:51.54#ibcon#about to read 4, iclass 20, count 0 2006.285.10:19:51.54#ibcon#read 4, iclass 20, count 0 2006.285.10:19:51.54#ibcon#about to read 5, iclass 20, count 0 2006.285.10:19:51.54#ibcon#read 5, iclass 20, count 0 2006.285.10:19:51.54#ibcon#about to read 6, iclass 20, count 0 2006.285.10:19:51.54#ibcon#read 6, iclass 20, count 0 2006.285.10:19:51.54#ibcon#end of sib2, iclass 20, count 0 2006.285.10:19:51.54#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:19:51.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:19:51.54#ibcon#[27=USB\r\n] 2006.285.10:19:51.54#ibcon#*before write, iclass 20, count 0 2006.285.10:19:51.54#ibcon#enter sib2, iclass 20, count 0 2006.285.10:19:51.54#ibcon#flushed, iclass 20, count 0 2006.285.10:19:51.54#ibcon#about to write, iclass 20, count 0 2006.285.10:19:51.54#ibcon#wrote, iclass 20, count 0 2006.285.10:19:51.54#ibcon#about to read 3, iclass 20, count 0 2006.285.10:19:51.57#ibcon#read 3, iclass 20, count 0 2006.285.10:19:51.57#ibcon#about to read 4, iclass 20, count 0 2006.285.10:19:51.57#ibcon#read 4, iclass 20, count 0 2006.285.10:19:51.57#ibcon#about to read 5, iclass 20, count 0 2006.285.10:19:51.57#ibcon#read 5, iclass 20, count 0 2006.285.10:19:51.57#ibcon#about to read 6, iclass 20, count 0 2006.285.10:19:51.57#ibcon#read 6, iclass 20, count 0 2006.285.10:19:51.57#ibcon#end of sib2, iclass 20, count 0 2006.285.10:19:51.57#ibcon#*after write, iclass 20, count 0 2006.285.10:19:51.57#ibcon#*before return 0, iclass 20, count 0 2006.285.10:19:51.57#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:19:51.57#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:19:51.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:19:51.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:19:51.57$vck44/vblo=2,634.99 2006.285.10:19:51.57#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.10:19:51.57#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.10:19:51.57#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:51.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:19:51.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:19:51.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:19:51.57#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:19:51.57#ibcon#first serial, iclass 22, count 0 2006.285.10:19:51.57#ibcon#enter sib2, iclass 22, count 0 2006.285.10:19:51.57#ibcon#flushed, iclass 22, count 0 2006.285.10:19:51.57#ibcon#about to write, iclass 22, count 0 2006.285.10:19:51.57#ibcon#wrote, iclass 22, count 0 2006.285.10:19:51.57#ibcon#about to read 3, iclass 22, count 0 2006.285.10:19:51.59#ibcon#read 3, iclass 22, count 0 2006.285.10:19:51.59#ibcon#about to read 4, iclass 22, count 0 2006.285.10:19:51.59#ibcon#read 4, iclass 22, count 0 2006.285.10:19:51.59#ibcon#about to read 5, iclass 22, count 0 2006.285.10:19:51.59#ibcon#read 5, iclass 22, count 0 2006.285.10:19:51.59#ibcon#about to read 6, iclass 22, count 0 2006.285.10:19:51.59#ibcon#read 6, iclass 22, count 0 2006.285.10:19:51.59#ibcon#end of sib2, iclass 22, count 0 2006.285.10:19:51.59#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:19:51.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:19:51.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:19:51.59#ibcon#*before write, iclass 22, count 0 2006.285.10:19:51.59#ibcon#enter sib2, iclass 22, count 0 2006.285.10:19:51.59#ibcon#flushed, iclass 22, count 0 2006.285.10:19:51.59#ibcon#about to write, iclass 22, count 0 2006.285.10:19:51.59#ibcon#wrote, iclass 22, count 0 2006.285.10:19:51.59#ibcon#about to read 3, iclass 22, count 0 2006.285.10:19:51.63#ibcon#read 3, iclass 22, count 0 2006.285.10:19:51.63#ibcon#about to read 4, iclass 22, count 0 2006.285.10:19:51.63#ibcon#read 4, iclass 22, count 0 2006.285.10:19:51.63#ibcon#about to read 5, iclass 22, count 0 2006.285.10:19:51.63#ibcon#read 5, iclass 22, count 0 2006.285.10:19:51.63#ibcon#about to read 6, iclass 22, count 0 2006.285.10:19:51.63#ibcon#read 6, iclass 22, count 0 2006.285.10:19:51.63#ibcon#end of sib2, iclass 22, count 0 2006.285.10:19:51.63#ibcon#*after write, iclass 22, count 0 2006.285.10:19:51.63#ibcon#*before return 0, iclass 22, count 0 2006.285.10:19:51.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:19:51.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:19:51.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:19:51.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:19:51.63$vck44/vb=2,5 2006.285.10:19:51.63#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.10:19:51.63#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.10:19:51.63#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:51.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:19:51.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:19:51.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:19:51.69#ibcon#enter wrdev, iclass 24, count 2 2006.285.10:19:51.69#ibcon#first serial, iclass 24, count 2 2006.285.10:19:51.69#ibcon#enter sib2, iclass 24, count 2 2006.285.10:19:51.69#ibcon#flushed, iclass 24, count 2 2006.285.10:19:51.69#ibcon#about to write, iclass 24, count 2 2006.285.10:19:51.69#ibcon#wrote, iclass 24, count 2 2006.285.10:19:51.69#ibcon#about to read 3, iclass 24, count 2 2006.285.10:19:51.71#ibcon#read 3, iclass 24, count 2 2006.285.10:19:51.71#ibcon#about to read 4, iclass 24, count 2 2006.285.10:19:51.71#ibcon#read 4, iclass 24, count 2 2006.285.10:19:51.71#ibcon#about to read 5, iclass 24, count 2 2006.285.10:19:51.71#ibcon#read 5, iclass 24, count 2 2006.285.10:19:51.71#ibcon#about to read 6, iclass 24, count 2 2006.285.10:19:51.71#ibcon#read 6, iclass 24, count 2 2006.285.10:19:51.71#ibcon#end of sib2, iclass 24, count 2 2006.285.10:19:51.71#ibcon#*mode == 0, iclass 24, count 2 2006.285.10:19:51.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.10:19:51.71#ibcon#[27=AT02-05\r\n] 2006.285.10:19:51.71#ibcon#*before write, iclass 24, count 2 2006.285.10:19:51.71#ibcon#enter sib2, iclass 24, count 2 2006.285.10:19:51.71#ibcon#flushed, iclass 24, count 2 2006.285.10:19:51.71#ibcon#about to write, iclass 24, count 2 2006.285.10:19:51.71#ibcon#wrote, iclass 24, count 2 2006.285.10:19:51.71#ibcon#about to read 3, iclass 24, count 2 2006.285.10:19:51.74#ibcon#read 3, iclass 24, count 2 2006.285.10:19:51.74#ibcon#about to read 4, iclass 24, count 2 2006.285.10:19:51.74#ibcon#read 4, iclass 24, count 2 2006.285.10:19:51.74#ibcon#about to read 5, iclass 24, count 2 2006.285.10:19:51.74#ibcon#read 5, iclass 24, count 2 2006.285.10:19:51.74#ibcon#about to read 6, iclass 24, count 2 2006.285.10:19:51.74#ibcon#read 6, iclass 24, count 2 2006.285.10:19:51.74#ibcon#end of sib2, iclass 24, count 2 2006.285.10:19:51.74#ibcon#*after write, iclass 24, count 2 2006.285.10:19:51.74#ibcon#*before return 0, iclass 24, count 2 2006.285.10:19:51.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:19:51.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:19:51.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.10:19:51.74#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:51.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:19:51.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:19:51.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:19:51.86#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:19:51.86#ibcon#first serial, iclass 24, count 0 2006.285.10:19:51.86#ibcon#enter sib2, iclass 24, count 0 2006.285.10:19:51.86#ibcon#flushed, iclass 24, count 0 2006.285.10:19:51.86#ibcon#about to write, iclass 24, count 0 2006.285.10:19:51.86#ibcon#wrote, iclass 24, count 0 2006.285.10:19:51.86#ibcon#about to read 3, iclass 24, count 0 2006.285.10:19:51.88#ibcon#read 3, iclass 24, count 0 2006.285.10:19:51.88#ibcon#about to read 4, iclass 24, count 0 2006.285.10:19:51.88#ibcon#read 4, iclass 24, count 0 2006.285.10:19:51.88#ibcon#about to read 5, iclass 24, count 0 2006.285.10:19:51.88#ibcon#read 5, iclass 24, count 0 2006.285.10:19:51.88#ibcon#about to read 6, iclass 24, count 0 2006.285.10:19:51.88#ibcon#read 6, iclass 24, count 0 2006.285.10:19:51.88#ibcon#end of sib2, iclass 24, count 0 2006.285.10:19:51.88#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:19:51.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:19:51.88#ibcon#[27=USB\r\n] 2006.285.10:19:51.88#ibcon#*before write, iclass 24, count 0 2006.285.10:19:51.88#ibcon#enter sib2, iclass 24, count 0 2006.285.10:19:51.88#ibcon#flushed, iclass 24, count 0 2006.285.10:19:51.88#ibcon#about to write, iclass 24, count 0 2006.285.10:19:51.88#ibcon#wrote, iclass 24, count 0 2006.285.10:19:51.88#ibcon#about to read 3, iclass 24, count 0 2006.285.10:19:51.91#ibcon#read 3, iclass 24, count 0 2006.285.10:19:51.91#ibcon#about to read 4, iclass 24, count 0 2006.285.10:19:51.91#ibcon#read 4, iclass 24, count 0 2006.285.10:19:51.91#ibcon#about to read 5, iclass 24, count 0 2006.285.10:19:51.91#ibcon#read 5, iclass 24, count 0 2006.285.10:19:51.91#ibcon#about to read 6, iclass 24, count 0 2006.285.10:19:51.91#ibcon#read 6, iclass 24, count 0 2006.285.10:19:51.91#ibcon#end of sib2, iclass 24, count 0 2006.285.10:19:51.91#ibcon#*after write, iclass 24, count 0 2006.285.10:19:51.91#ibcon#*before return 0, iclass 24, count 0 2006.285.10:19:51.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:19:51.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:19:51.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:19:51.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:19:51.91$vck44/vblo=3,649.99 2006.285.10:19:51.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.10:19:51.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.10:19:51.91#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:51.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:19:51.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:19:51.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:19:51.91#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:19:51.91#ibcon#first serial, iclass 26, count 0 2006.285.10:19:51.91#ibcon#enter sib2, iclass 26, count 0 2006.285.10:19:51.91#ibcon#flushed, iclass 26, count 0 2006.285.10:19:51.91#ibcon#about to write, iclass 26, count 0 2006.285.10:19:51.91#ibcon#wrote, iclass 26, count 0 2006.285.10:19:51.91#ibcon#about to read 3, iclass 26, count 0 2006.285.10:19:51.93#ibcon#read 3, iclass 26, count 0 2006.285.10:19:51.93#ibcon#about to read 4, iclass 26, count 0 2006.285.10:19:51.93#ibcon#read 4, iclass 26, count 0 2006.285.10:19:51.93#ibcon#about to read 5, iclass 26, count 0 2006.285.10:19:51.93#ibcon#read 5, iclass 26, count 0 2006.285.10:19:51.93#ibcon#about to read 6, iclass 26, count 0 2006.285.10:19:51.93#ibcon#read 6, iclass 26, count 0 2006.285.10:19:51.93#ibcon#end of sib2, iclass 26, count 0 2006.285.10:19:51.93#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:19:51.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:19:51.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:19:51.93#ibcon#*before write, iclass 26, count 0 2006.285.10:19:51.93#ibcon#enter sib2, iclass 26, count 0 2006.285.10:19:51.93#ibcon#flushed, iclass 26, count 0 2006.285.10:19:51.93#ibcon#about to write, iclass 26, count 0 2006.285.10:19:51.93#ibcon#wrote, iclass 26, count 0 2006.285.10:19:51.93#ibcon#about to read 3, iclass 26, count 0 2006.285.10:19:51.97#ibcon#read 3, iclass 26, count 0 2006.285.10:19:51.97#ibcon#about to read 4, iclass 26, count 0 2006.285.10:19:51.97#ibcon#read 4, iclass 26, count 0 2006.285.10:19:51.97#ibcon#about to read 5, iclass 26, count 0 2006.285.10:19:51.97#ibcon#read 5, iclass 26, count 0 2006.285.10:19:51.97#ibcon#about to read 6, iclass 26, count 0 2006.285.10:19:51.97#ibcon#read 6, iclass 26, count 0 2006.285.10:19:51.97#ibcon#end of sib2, iclass 26, count 0 2006.285.10:19:51.97#ibcon#*after write, iclass 26, count 0 2006.285.10:19:51.97#ibcon#*before return 0, iclass 26, count 0 2006.285.10:19:51.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:19:51.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:19:51.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:19:51.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:19:51.97$vck44/vb=3,4 2006.285.10:19:51.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.10:19:51.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.10:19:51.97#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:51.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:19:52.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:19:52.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:19:52.03#ibcon#enter wrdev, iclass 28, count 2 2006.285.10:19:52.03#ibcon#first serial, iclass 28, count 2 2006.285.10:19:52.03#ibcon#enter sib2, iclass 28, count 2 2006.285.10:19:52.03#ibcon#flushed, iclass 28, count 2 2006.285.10:19:52.03#ibcon#about to write, iclass 28, count 2 2006.285.10:19:52.03#ibcon#wrote, iclass 28, count 2 2006.285.10:19:52.03#ibcon#about to read 3, iclass 28, count 2 2006.285.10:19:52.05#ibcon#read 3, iclass 28, count 2 2006.285.10:19:52.05#ibcon#about to read 4, iclass 28, count 2 2006.285.10:19:52.05#ibcon#read 4, iclass 28, count 2 2006.285.10:19:52.05#ibcon#about to read 5, iclass 28, count 2 2006.285.10:19:52.05#ibcon#read 5, iclass 28, count 2 2006.285.10:19:52.05#ibcon#about to read 6, iclass 28, count 2 2006.285.10:19:52.05#ibcon#read 6, iclass 28, count 2 2006.285.10:19:52.05#ibcon#end of sib2, iclass 28, count 2 2006.285.10:19:52.05#ibcon#*mode == 0, iclass 28, count 2 2006.285.10:19:52.05#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.10:19:52.05#ibcon#[27=AT03-04\r\n] 2006.285.10:19:52.05#ibcon#*before write, iclass 28, count 2 2006.285.10:19:52.05#ibcon#enter sib2, iclass 28, count 2 2006.285.10:19:52.05#ibcon#flushed, iclass 28, count 2 2006.285.10:19:52.05#ibcon#about to write, iclass 28, count 2 2006.285.10:19:52.05#ibcon#wrote, iclass 28, count 2 2006.285.10:19:52.05#ibcon#about to read 3, iclass 28, count 2 2006.285.10:19:52.08#ibcon#read 3, iclass 28, count 2 2006.285.10:19:52.08#ibcon#about to read 4, iclass 28, count 2 2006.285.10:19:52.08#ibcon#read 4, iclass 28, count 2 2006.285.10:19:52.08#ibcon#about to read 5, iclass 28, count 2 2006.285.10:19:52.08#ibcon#read 5, iclass 28, count 2 2006.285.10:19:52.08#ibcon#about to read 6, iclass 28, count 2 2006.285.10:19:52.08#ibcon#read 6, iclass 28, count 2 2006.285.10:19:52.08#ibcon#end of sib2, iclass 28, count 2 2006.285.10:19:52.08#ibcon#*after write, iclass 28, count 2 2006.285.10:19:52.08#ibcon#*before return 0, iclass 28, count 2 2006.285.10:19:52.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:19:52.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:19:52.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.10:19:52.08#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:52.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:19:52.20#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:19:52.20#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:19:52.20#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:19:52.20#ibcon#first serial, iclass 28, count 0 2006.285.10:19:52.20#ibcon#enter sib2, iclass 28, count 0 2006.285.10:19:52.20#ibcon#flushed, iclass 28, count 0 2006.285.10:19:52.20#ibcon#about to write, iclass 28, count 0 2006.285.10:19:52.20#ibcon#wrote, iclass 28, count 0 2006.285.10:19:52.20#ibcon#about to read 3, iclass 28, count 0 2006.285.10:19:52.22#ibcon#read 3, iclass 28, count 0 2006.285.10:19:52.22#ibcon#about to read 4, iclass 28, count 0 2006.285.10:19:52.22#ibcon#read 4, iclass 28, count 0 2006.285.10:19:52.22#ibcon#about to read 5, iclass 28, count 0 2006.285.10:19:52.22#ibcon#read 5, iclass 28, count 0 2006.285.10:19:52.22#ibcon#about to read 6, iclass 28, count 0 2006.285.10:19:52.22#ibcon#read 6, iclass 28, count 0 2006.285.10:19:52.22#ibcon#end of sib2, iclass 28, count 0 2006.285.10:19:52.22#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:19:52.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:19:52.22#ibcon#[27=USB\r\n] 2006.285.10:19:52.22#ibcon#*before write, iclass 28, count 0 2006.285.10:19:52.22#ibcon#enter sib2, iclass 28, count 0 2006.285.10:19:52.22#ibcon#flushed, iclass 28, count 0 2006.285.10:19:52.22#ibcon#about to write, iclass 28, count 0 2006.285.10:19:52.22#ibcon#wrote, iclass 28, count 0 2006.285.10:19:52.22#ibcon#about to read 3, iclass 28, count 0 2006.285.10:19:52.25#ibcon#read 3, iclass 28, count 0 2006.285.10:19:52.25#ibcon#about to read 4, iclass 28, count 0 2006.285.10:19:52.25#ibcon#read 4, iclass 28, count 0 2006.285.10:19:52.25#ibcon#about to read 5, iclass 28, count 0 2006.285.10:19:52.25#ibcon#read 5, iclass 28, count 0 2006.285.10:19:52.25#ibcon#about to read 6, iclass 28, count 0 2006.285.10:19:52.25#ibcon#read 6, iclass 28, count 0 2006.285.10:19:52.25#ibcon#end of sib2, iclass 28, count 0 2006.285.10:19:52.25#ibcon#*after write, iclass 28, count 0 2006.285.10:19:52.25#ibcon#*before return 0, iclass 28, count 0 2006.285.10:19:52.25#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:19:52.25#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:19:52.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:19:52.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:19:52.25$vck44/vblo=4,679.99 2006.285.10:19:52.25#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.10:19:52.25#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.10:19:52.25#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:52.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:19:52.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:19:52.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:19:52.25#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:19:52.25#ibcon#first serial, iclass 30, count 0 2006.285.10:19:52.25#ibcon#enter sib2, iclass 30, count 0 2006.285.10:19:52.25#ibcon#flushed, iclass 30, count 0 2006.285.10:19:52.25#ibcon#about to write, iclass 30, count 0 2006.285.10:19:52.25#ibcon#wrote, iclass 30, count 0 2006.285.10:19:52.25#ibcon#about to read 3, iclass 30, count 0 2006.285.10:19:52.27#ibcon#read 3, iclass 30, count 0 2006.285.10:19:52.27#ibcon#about to read 4, iclass 30, count 0 2006.285.10:19:52.27#ibcon#read 4, iclass 30, count 0 2006.285.10:19:52.27#ibcon#about to read 5, iclass 30, count 0 2006.285.10:19:52.27#ibcon#read 5, iclass 30, count 0 2006.285.10:19:52.27#ibcon#about to read 6, iclass 30, count 0 2006.285.10:19:52.27#ibcon#read 6, iclass 30, count 0 2006.285.10:19:52.27#ibcon#end of sib2, iclass 30, count 0 2006.285.10:19:52.27#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:19:52.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:19:52.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:19:52.27#ibcon#*before write, iclass 30, count 0 2006.285.10:19:52.27#ibcon#enter sib2, iclass 30, count 0 2006.285.10:19:52.27#ibcon#flushed, iclass 30, count 0 2006.285.10:19:52.27#ibcon#about to write, iclass 30, count 0 2006.285.10:19:52.27#ibcon#wrote, iclass 30, count 0 2006.285.10:19:52.27#ibcon#about to read 3, iclass 30, count 0 2006.285.10:19:52.31#ibcon#read 3, iclass 30, count 0 2006.285.10:19:52.31#ibcon#about to read 4, iclass 30, count 0 2006.285.10:19:52.31#ibcon#read 4, iclass 30, count 0 2006.285.10:19:52.31#ibcon#about to read 5, iclass 30, count 0 2006.285.10:19:52.31#ibcon#read 5, iclass 30, count 0 2006.285.10:19:52.31#ibcon#about to read 6, iclass 30, count 0 2006.285.10:19:52.31#ibcon#read 6, iclass 30, count 0 2006.285.10:19:52.31#ibcon#end of sib2, iclass 30, count 0 2006.285.10:19:52.31#ibcon#*after write, iclass 30, count 0 2006.285.10:19:52.31#ibcon#*before return 0, iclass 30, count 0 2006.285.10:19:52.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:19:52.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:19:52.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:19:52.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:19:52.31$vck44/vb=4,5 2006.285.10:19:52.31#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.10:19:52.31#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.10:19:52.31#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:52.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:19:52.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:19:52.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:19:52.37#ibcon#enter wrdev, iclass 32, count 2 2006.285.10:19:52.37#ibcon#first serial, iclass 32, count 2 2006.285.10:19:52.37#ibcon#enter sib2, iclass 32, count 2 2006.285.10:19:52.37#ibcon#flushed, iclass 32, count 2 2006.285.10:19:52.37#ibcon#about to write, iclass 32, count 2 2006.285.10:19:52.37#ibcon#wrote, iclass 32, count 2 2006.285.10:19:52.37#ibcon#about to read 3, iclass 32, count 2 2006.285.10:19:52.39#ibcon#read 3, iclass 32, count 2 2006.285.10:19:52.39#ibcon#about to read 4, iclass 32, count 2 2006.285.10:19:52.39#ibcon#read 4, iclass 32, count 2 2006.285.10:19:52.39#ibcon#about to read 5, iclass 32, count 2 2006.285.10:19:52.39#ibcon#read 5, iclass 32, count 2 2006.285.10:19:52.39#ibcon#about to read 6, iclass 32, count 2 2006.285.10:19:52.39#ibcon#read 6, iclass 32, count 2 2006.285.10:19:52.39#ibcon#end of sib2, iclass 32, count 2 2006.285.10:19:52.39#ibcon#*mode == 0, iclass 32, count 2 2006.285.10:19:52.39#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.10:19:52.39#ibcon#[27=AT04-05\r\n] 2006.285.10:19:52.39#ibcon#*before write, iclass 32, count 2 2006.285.10:19:52.39#ibcon#enter sib2, iclass 32, count 2 2006.285.10:19:52.39#ibcon#flushed, iclass 32, count 2 2006.285.10:19:52.39#ibcon#about to write, iclass 32, count 2 2006.285.10:19:52.39#ibcon#wrote, iclass 32, count 2 2006.285.10:19:52.39#ibcon#about to read 3, iclass 32, count 2 2006.285.10:19:52.42#ibcon#read 3, iclass 32, count 2 2006.285.10:19:52.42#ibcon#about to read 4, iclass 32, count 2 2006.285.10:19:52.42#ibcon#read 4, iclass 32, count 2 2006.285.10:19:52.42#ibcon#about to read 5, iclass 32, count 2 2006.285.10:19:52.42#ibcon#read 5, iclass 32, count 2 2006.285.10:19:52.42#ibcon#about to read 6, iclass 32, count 2 2006.285.10:19:52.42#ibcon#read 6, iclass 32, count 2 2006.285.10:19:52.42#ibcon#end of sib2, iclass 32, count 2 2006.285.10:19:52.42#ibcon#*after write, iclass 32, count 2 2006.285.10:19:52.42#ibcon#*before return 0, iclass 32, count 2 2006.285.10:19:52.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:19:52.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:19:52.42#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.10:19:52.42#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:52.42#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:19:52.54#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:19:52.54#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:19:52.54#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:19:52.54#ibcon#first serial, iclass 32, count 0 2006.285.10:19:52.54#ibcon#enter sib2, iclass 32, count 0 2006.285.10:19:52.54#ibcon#flushed, iclass 32, count 0 2006.285.10:19:52.54#ibcon#about to write, iclass 32, count 0 2006.285.10:19:52.54#ibcon#wrote, iclass 32, count 0 2006.285.10:19:52.54#ibcon#about to read 3, iclass 32, count 0 2006.285.10:19:52.56#ibcon#read 3, iclass 32, count 0 2006.285.10:19:52.56#ibcon#about to read 4, iclass 32, count 0 2006.285.10:19:52.56#ibcon#read 4, iclass 32, count 0 2006.285.10:19:52.56#ibcon#about to read 5, iclass 32, count 0 2006.285.10:19:52.56#ibcon#read 5, iclass 32, count 0 2006.285.10:19:52.56#ibcon#about to read 6, iclass 32, count 0 2006.285.10:19:52.56#ibcon#read 6, iclass 32, count 0 2006.285.10:19:52.56#ibcon#end of sib2, iclass 32, count 0 2006.285.10:19:52.56#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:19:52.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:19:52.56#ibcon#[27=USB\r\n] 2006.285.10:19:52.56#ibcon#*before write, iclass 32, count 0 2006.285.10:19:52.56#ibcon#enter sib2, iclass 32, count 0 2006.285.10:19:52.56#ibcon#flushed, iclass 32, count 0 2006.285.10:19:52.56#ibcon#about to write, iclass 32, count 0 2006.285.10:19:52.56#ibcon#wrote, iclass 32, count 0 2006.285.10:19:52.56#ibcon#about to read 3, iclass 32, count 0 2006.285.10:19:52.59#ibcon#read 3, iclass 32, count 0 2006.285.10:19:52.59#ibcon#about to read 4, iclass 32, count 0 2006.285.10:19:52.59#ibcon#read 4, iclass 32, count 0 2006.285.10:19:52.59#ibcon#about to read 5, iclass 32, count 0 2006.285.10:19:52.59#ibcon#read 5, iclass 32, count 0 2006.285.10:19:52.59#ibcon#about to read 6, iclass 32, count 0 2006.285.10:19:52.59#ibcon#read 6, iclass 32, count 0 2006.285.10:19:52.59#ibcon#end of sib2, iclass 32, count 0 2006.285.10:19:52.59#ibcon#*after write, iclass 32, count 0 2006.285.10:19:52.59#ibcon#*before return 0, iclass 32, count 0 2006.285.10:19:52.59#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:19:52.59#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:19:52.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:19:52.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:19:52.59$vck44/vblo=5,709.99 2006.285.10:19:52.59#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.10:19:52.59#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.10:19:52.59#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:52.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:19:52.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:19:52.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:19:52.59#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:19:52.59#ibcon#first serial, iclass 34, count 0 2006.285.10:19:52.59#ibcon#enter sib2, iclass 34, count 0 2006.285.10:19:52.59#ibcon#flushed, iclass 34, count 0 2006.285.10:19:52.59#ibcon#about to write, iclass 34, count 0 2006.285.10:19:52.59#ibcon#wrote, iclass 34, count 0 2006.285.10:19:52.59#ibcon#about to read 3, iclass 34, count 0 2006.285.10:19:52.61#ibcon#read 3, iclass 34, count 0 2006.285.10:19:52.61#ibcon#about to read 4, iclass 34, count 0 2006.285.10:19:52.61#ibcon#read 4, iclass 34, count 0 2006.285.10:19:52.61#ibcon#about to read 5, iclass 34, count 0 2006.285.10:19:52.61#ibcon#read 5, iclass 34, count 0 2006.285.10:19:52.61#ibcon#about to read 6, iclass 34, count 0 2006.285.10:19:52.61#ibcon#read 6, iclass 34, count 0 2006.285.10:19:52.61#ibcon#end of sib2, iclass 34, count 0 2006.285.10:19:52.61#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:19:52.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:19:52.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:19:52.61#ibcon#*before write, iclass 34, count 0 2006.285.10:19:52.61#ibcon#enter sib2, iclass 34, count 0 2006.285.10:19:52.61#ibcon#flushed, iclass 34, count 0 2006.285.10:19:52.61#ibcon#about to write, iclass 34, count 0 2006.285.10:19:52.61#ibcon#wrote, iclass 34, count 0 2006.285.10:19:52.61#ibcon#about to read 3, iclass 34, count 0 2006.285.10:19:52.65#ibcon#read 3, iclass 34, count 0 2006.285.10:19:52.65#ibcon#about to read 4, iclass 34, count 0 2006.285.10:19:52.65#ibcon#read 4, iclass 34, count 0 2006.285.10:19:52.65#ibcon#about to read 5, iclass 34, count 0 2006.285.10:19:52.65#ibcon#read 5, iclass 34, count 0 2006.285.10:19:52.65#ibcon#about to read 6, iclass 34, count 0 2006.285.10:19:52.65#ibcon#read 6, iclass 34, count 0 2006.285.10:19:52.65#ibcon#end of sib2, iclass 34, count 0 2006.285.10:19:52.65#ibcon#*after write, iclass 34, count 0 2006.285.10:19:52.65#ibcon#*before return 0, iclass 34, count 0 2006.285.10:19:52.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:19:52.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:19:52.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:19:52.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:19:52.65$vck44/vb=5,4 2006.285.10:19:52.65#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.10:19:52.65#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.10:19:52.65#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:52.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:19:52.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:19:52.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:19:52.71#ibcon#enter wrdev, iclass 36, count 2 2006.285.10:19:52.71#ibcon#first serial, iclass 36, count 2 2006.285.10:19:52.71#ibcon#enter sib2, iclass 36, count 2 2006.285.10:19:52.71#ibcon#flushed, iclass 36, count 2 2006.285.10:19:52.71#ibcon#about to write, iclass 36, count 2 2006.285.10:19:52.71#ibcon#wrote, iclass 36, count 2 2006.285.10:19:52.71#ibcon#about to read 3, iclass 36, count 2 2006.285.10:19:52.73#ibcon#read 3, iclass 36, count 2 2006.285.10:19:52.73#ibcon#about to read 4, iclass 36, count 2 2006.285.10:19:52.73#ibcon#read 4, iclass 36, count 2 2006.285.10:19:52.73#ibcon#about to read 5, iclass 36, count 2 2006.285.10:19:52.73#ibcon#read 5, iclass 36, count 2 2006.285.10:19:52.73#ibcon#about to read 6, iclass 36, count 2 2006.285.10:19:52.73#ibcon#read 6, iclass 36, count 2 2006.285.10:19:52.73#ibcon#end of sib2, iclass 36, count 2 2006.285.10:19:52.73#ibcon#*mode == 0, iclass 36, count 2 2006.285.10:19:52.73#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.10:19:52.73#ibcon#[27=AT05-04\r\n] 2006.285.10:19:52.73#ibcon#*before write, iclass 36, count 2 2006.285.10:19:52.73#ibcon#enter sib2, iclass 36, count 2 2006.285.10:19:52.73#ibcon#flushed, iclass 36, count 2 2006.285.10:19:52.73#ibcon#about to write, iclass 36, count 2 2006.285.10:19:52.73#ibcon#wrote, iclass 36, count 2 2006.285.10:19:52.73#ibcon#about to read 3, iclass 36, count 2 2006.285.10:19:52.76#ibcon#read 3, iclass 36, count 2 2006.285.10:19:52.76#ibcon#about to read 4, iclass 36, count 2 2006.285.10:19:52.76#ibcon#read 4, iclass 36, count 2 2006.285.10:19:52.76#ibcon#about to read 5, iclass 36, count 2 2006.285.10:19:52.76#ibcon#read 5, iclass 36, count 2 2006.285.10:19:52.76#ibcon#about to read 6, iclass 36, count 2 2006.285.10:19:52.76#ibcon#read 6, iclass 36, count 2 2006.285.10:19:52.76#ibcon#end of sib2, iclass 36, count 2 2006.285.10:19:52.76#ibcon#*after write, iclass 36, count 2 2006.285.10:19:52.76#ibcon#*before return 0, iclass 36, count 2 2006.285.10:19:52.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:19:52.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:19:52.76#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.10:19:52.76#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:52.76#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:19:52.79#abcon#<5=/04 1.4 2.5 19.76 911015.0\r\n> 2006.285.10:19:52.81#abcon#{5=INTERFACE CLEAR} 2006.285.10:19:52.87#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:19:52.88#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:19:52.88#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:19:52.88#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:19:52.88#ibcon#first serial, iclass 36, count 0 2006.285.10:19:52.88#ibcon#enter sib2, iclass 36, count 0 2006.285.10:19:52.88#ibcon#flushed, iclass 36, count 0 2006.285.10:19:52.88#ibcon#about to write, iclass 36, count 0 2006.285.10:19:52.88#ibcon#wrote, iclass 36, count 0 2006.285.10:19:52.88#ibcon#about to read 3, iclass 36, count 0 2006.285.10:19:52.90#ibcon#read 3, iclass 36, count 0 2006.285.10:19:52.90#ibcon#about to read 4, iclass 36, count 0 2006.285.10:19:52.90#ibcon#read 4, iclass 36, count 0 2006.285.10:19:52.90#ibcon#about to read 5, iclass 36, count 0 2006.285.10:19:52.90#ibcon#read 5, iclass 36, count 0 2006.285.10:19:52.90#ibcon#about to read 6, iclass 36, count 0 2006.285.10:19:52.90#ibcon#read 6, iclass 36, count 0 2006.285.10:19:52.90#ibcon#end of sib2, iclass 36, count 0 2006.285.10:19:52.90#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:19:52.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:19:52.90#ibcon#[27=USB\r\n] 2006.285.10:19:52.90#ibcon#*before write, iclass 36, count 0 2006.285.10:19:52.90#ibcon#enter sib2, iclass 36, count 0 2006.285.10:19:52.90#ibcon#flushed, iclass 36, count 0 2006.285.10:19:52.90#ibcon#about to write, iclass 36, count 0 2006.285.10:19:52.90#ibcon#wrote, iclass 36, count 0 2006.285.10:19:52.90#ibcon#about to read 3, iclass 36, count 0 2006.285.10:19:52.93#ibcon#read 3, iclass 36, count 0 2006.285.10:19:52.93#ibcon#about to read 4, iclass 36, count 0 2006.285.10:19:52.93#ibcon#read 4, iclass 36, count 0 2006.285.10:19:52.93#ibcon#about to read 5, iclass 36, count 0 2006.285.10:19:52.93#ibcon#read 5, iclass 36, count 0 2006.285.10:19:52.93#ibcon#about to read 6, iclass 36, count 0 2006.285.10:19:52.93#ibcon#read 6, iclass 36, count 0 2006.285.10:19:52.93#ibcon#end of sib2, iclass 36, count 0 2006.285.10:19:52.93#ibcon#*after write, iclass 36, count 0 2006.285.10:19:52.93#ibcon#*before return 0, iclass 36, count 0 2006.285.10:19:52.93#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:19:52.93#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:19:52.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:19:52.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:19:52.93$vck44/vblo=6,719.99 2006.285.10:19:52.93#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.10:19:52.93#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.10:19:52.93#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:52.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:19:52.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:19:52.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:19:52.93#ibcon#enter wrdev, iclass 4, count 0 2006.285.10:19:52.93#ibcon#first serial, iclass 4, count 0 2006.285.10:19:52.93#ibcon#enter sib2, iclass 4, count 0 2006.285.10:19:52.93#ibcon#flushed, iclass 4, count 0 2006.285.10:19:52.93#ibcon#about to write, iclass 4, count 0 2006.285.10:19:52.93#ibcon#wrote, iclass 4, count 0 2006.285.10:19:52.93#ibcon#about to read 3, iclass 4, count 0 2006.285.10:19:52.95#ibcon#read 3, iclass 4, count 0 2006.285.10:19:52.95#ibcon#about to read 4, iclass 4, count 0 2006.285.10:19:52.95#ibcon#read 4, iclass 4, count 0 2006.285.10:19:52.95#ibcon#about to read 5, iclass 4, count 0 2006.285.10:19:52.95#ibcon#read 5, iclass 4, count 0 2006.285.10:19:52.95#ibcon#about to read 6, iclass 4, count 0 2006.285.10:19:52.95#ibcon#read 6, iclass 4, count 0 2006.285.10:19:52.95#ibcon#end of sib2, iclass 4, count 0 2006.285.10:19:52.95#ibcon#*mode == 0, iclass 4, count 0 2006.285.10:19:52.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.10:19:52.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:19:52.95#ibcon#*before write, iclass 4, count 0 2006.285.10:19:52.95#ibcon#enter sib2, iclass 4, count 0 2006.285.10:19:52.95#ibcon#flushed, iclass 4, count 0 2006.285.10:19:52.95#ibcon#about to write, iclass 4, count 0 2006.285.10:19:52.95#ibcon#wrote, iclass 4, count 0 2006.285.10:19:52.95#ibcon#about to read 3, iclass 4, count 0 2006.285.10:19:52.99#ibcon#read 3, iclass 4, count 0 2006.285.10:19:52.99#ibcon#about to read 4, iclass 4, count 0 2006.285.10:19:52.99#ibcon#read 4, iclass 4, count 0 2006.285.10:19:52.99#ibcon#about to read 5, iclass 4, count 0 2006.285.10:19:52.99#ibcon#read 5, iclass 4, count 0 2006.285.10:19:52.99#ibcon#about to read 6, iclass 4, count 0 2006.285.10:19:52.99#ibcon#read 6, iclass 4, count 0 2006.285.10:19:52.99#ibcon#end of sib2, iclass 4, count 0 2006.285.10:19:52.99#ibcon#*after write, iclass 4, count 0 2006.285.10:19:52.99#ibcon#*before return 0, iclass 4, count 0 2006.285.10:19:52.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:19:52.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:19:52.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.10:19:52.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.10:19:52.99$vck44/vb=6,3 2006.285.10:19:52.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.10:19:52.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.10:19:52.99#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:52.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:19:53.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:19:53.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:19:53.05#ibcon#enter wrdev, iclass 6, count 2 2006.285.10:19:53.05#ibcon#first serial, iclass 6, count 2 2006.285.10:19:53.05#ibcon#enter sib2, iclass 6, count 2 2006.285.10:19:53.05#ibcon#flushed, iclass 6, count 2 2006.285.10:19:53.05#ibcon#about to write, iclass 6, count 2 2006.285.10:19:53.05#ibcon#wrote, iclass 6, count 2 2006.285.10:19:53.05#ibcon#about to read 3, iclass 6, count 2 2006.285.10:19:53.07#ibcon#read 3, iclass 6, count 2 2006.285.10:19:53.07#ibcon#about to read 4, iclass 6, count 2 2006.285.10:19:53.07#ibcon#read 4, iclass 6, count 2 2006.285.10:19:53.07#ibcon#about to read 5, iclass 6, count 2 2006.285.10:19:53.07#ibcon#read 5, iclass 6, count 2 2006.285.10:19:53.07#ibcon#about to read 6, iclass 6, count 2 2006.285.10:19:53.07#ibcon#read 6, iclass 6, count 2 2006.285.10:19:53.07#ibcon#end of sib2, iclass 6, count 2 2006.285.10:19:53.07#ibcon#*mode == 0, iclass 6, count 2 2006.285.10:19:53.07#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.10:19:53.07#ibcon#[27=AT06-03\r\n] 2006.285.10:19:53.07#ibcon#*before write, iclass 6, count 2 2006.285.10:19:53.07#ibcon#enter sib2, iclass 6, count 2 2006.285.10:19:53.07#ibcon#flushed, iclass 6, count 2 2006.285.10:19:53.07#ibcon#about to write, iclass 6, count 2 2006.285.10:19:53.07#ibcon#wrote, iclass 6, count 2 2006.285.10:19:53.07#ibcon#about to read 3, iclass 6, count 2 2006.285.10:19:53.10#ibcon#read 3, iclass 6, count 2 2006.285.10:19:53.10#ibcon#about to read 4, iclass 6, count 2 2006.285.10:19:53.10#ibcon#read 4, iclass 6, count 2 2006.285.10:19:53.10#ibcon#about to read 5, iclass 6, count 2 2006.285.10:19:53.10#ibcon#read 5, iclass 6, count 2 2006.285.10:19:53.10#ibcon#about to read 6, iclass 6, count 2 2006.285.10:19:53.10#ibcon#read 6, iclass 6, count 2 2006.285.10:19:53.10#ibcon#end of sib2, iclass 6, count 2 2006.285.10:19:53.10#ibcon#*after write, iclass 6, count 2 2006.285.10:19:53.10#ibcon#*before return 0, iclass 6, count 2 2006.285.10:19:53.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:19:53.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:19:53.10#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.10:19:53.10#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:53.10#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:19:53.22#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:19:53.22#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:19:53.22#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:19:53.22#ibcon#first serial, iclass 6, count 0 2006.285.10:19:53.22#ibcon#enter sib2, iclass 6, count 0 2006.285.10:19:53.22#ibcon#flushed, iclass 6, count 0 2006.285.10:19:53.22#ibcon#about to write, iclass 6, count 0 2006.285.10:19:53.22#ibcon#wrote, iclass 6, count 0 2006.285.10:19:53.22#ibcon#about to read 3, iclass 6, count 0 2006.285.10:19:53.24#ibcon#read 3, iclass 6, count 0 2006.285.10:19:53.24#ibcon#about to read 4, iclass 6, count 0 2006.285.10:19:53.24#ibcon#read 4, iclass 6, count 0 2006.285.10:19:53.24#ibcon#about to read 5, iclass 6, count 0 2006.285.10:19:53.24#ibcon#read 5, iclass 6, count 0 2006.285.10:19:53.24#ibcon#about to read 6, iclass 6, count 0 2006.285.10:19:53.24#ibcon#read 6, iclass 6, count 0 2006.285.10:19:53.24#ibcon#end of sib2, iclass 6, count 0 2006.285.10:19:53.24#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:19:53.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:19:53.24#ibcon#[27=USB\r\n] 2006.285.10:19:53.24#ibcon#*before write, iclass 6, count 0 2006.285.10:19:53.24#ibcon#enter sib2, iclass 6, count 0 2006.285.10:19:53.24#ibcon#flushed, iclass 6, count 0 2006.285.10:19:53.24#ibcon#about to write, iclass 6, count 0 2006.285.10:19:53.24#ibcon#wrote, iclass 6, count 0 2006.285.10:19:53.24#ibcon#about to read 3, iclass 6, count 0 2006.285.10:19:53.27#ibcon#read 3, iclass 6, count 0 2006.285.10:19:53.27#ibcon#about to read 4, iclass 6, count 0 2006.285.10:19:53.27#ibcon#read 4, iclass 6, count 0 2006.285.10:19:53.27#ibcon#about to read 5, iclass 6, count 0 2006.285.10:19:53.27#ibcon#read 5, iclass 6, count 0 2006.285.10:19:53.27#ibcon#about to read 6, iclass 6, count 0 2006.285.10:19:53.27#ibcon#read 6, iclass 6, count 0 2006.285.10:19:53.27#ibcon#end of sib2, iclass 6, count 0 2006.285.10:19:53.27#ibcon#*after write, iclass 6, count 0 2006.285.10:19:53.27#ibcon#*before return 0, iclass 6, count 0 2006.285.10:19:53.27#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:19:53.27#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:19:53.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:19:53.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:19:53.27$vck44/vblo=7,734.99 2006.285.10:19:53.27#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.10:19:53.27#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.10:19:53.27#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:53.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:19:53.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:19:53.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:19:53.27#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:19:53.27#ibcon#first serial, iclass 10, count 0 2006.285.10:19:53.27#ibcon#enter sib2, iclass 10, count 0 2006.285.10:19:53.27#ibcon#flushed, iclass 10, count 0 2006.285.10:19:53.27#ibcon#about to write, iclass 10, count 0 2006.285.10:19:53.27#ibcon#wrote, iclass 10, count 0 2006.285.10:19:53.27#ibcon#about to read 3, iclass 10, count 0 2006.285.10:19:53.29#ibcon#read 3, iclass 10, count 0 2006.285.10:19:53.29#ibcon#about to read 4, iclass 10, count 0 2006.285.10:19:53.29#ibcon#read 4, iclass 10, count 0 2006.285.10:19:53.29#ibcon#about to read 5, iclass 10, count 0 2006.285.10:19:53.29#ibcon#read 5, iclass 10, count 0 2006.285.10:19:53.29#ibcon#about to read 6, iclass 10, count 0 2006.285.10:19:53.29#ibcon#read 6, iclass 10, count 0 2006.285.10:19:53.29#ibcon#end of sib2, iclass 10, count 0 2006.285.10:19:53.29#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:19:53.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:19:53.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:19:53.29#ibcon#*before write, iclass 10, count 0 2006.285.10:19:53.29#ibcon#enter sib2, iclass 10, count 0 2006.285.10:19:53.29#ibcon#flushed, iclass 10, count 0 2006.285.10:19:53.29#ibcon#about to write, iclass 10, count 0 2006.285.10:19:53.29#ibcon#wrote, iclass 10, count 0 2006.285.10:19:53.29#ibcon#about to read 3, iclass 10, count 0 2006.285.10:19:53.33#ibcon#read 3, iclass 10, count 0 2006.285.10:19:53.33#ibcon#about to read 4, iclass 10, count 0 2006.285.10:19:53.33#ibcon#read 4, iclass 10, count 0 2006.285.10:19:53.33#ibcon#about to read 5, iclass 10, count 0 2006.285.10:19:53.33#ibcon#read 5, iclass 10, count 0 2006.285.10:19:53.33#ibcon#about to read 6, iclass 10, count 0 2006.285.10:19:53.33#ibcon#read 6, iclass 10, count 0 2006.285.10:19:53.33#ibcon#end of sib2, iclass 10, count 0 2006.285.10:19:53.33#ibcon#*after write, iclass 10, count 0 2006.285.10:19:53.33#ibcon#*before return 0, iclass 10, count 0 2006.285.10:19:53.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:19:53.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:19:53.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:19:53.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:19:53.33$vck44/vb=7,4 2006.285.10:19:53.33#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.10:19:53.33#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.10:19:53.33#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:53.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:19:53.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:19:53.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:19:53.39#ibcon#enter wrdev, iclass 12, count 2 2006.285.10:19:53.39#ibcon#first serial, iclass 12, count 2 2006.285.10:19:53.39#ibcon#enter sib2, iclass 12, count 2 2006.285.10:19:53.39#ibcon#flushed, iclass 12, count 2 2006.285.10:19:53.39#ibcon#about to write, iclass 12, count 2 2006.285.10:19:53.39#ibcon#wrote, iclass 12, count 2 2006.285.10:19:53.39#ibcon#about to read 3, iclass 12, count 2 2006.285.10:19:53.41#ibcon#read 3, iclass 12, count 2 2006.285.10:19:53.41#ibcon#about to read 4, iclass 12, count 2 2006.285.10:19:53.41#ibcon#read 4, iclass 12, count 2 2006.285.10:19:53.41#ibcon#about to read 5, iclass 12, count 2 2006.285.10:19:53.41#ibcon#read 5, iclass 12, count 2 2006.285.10:19:53.41#ibcon#about to read 6, iclass 12, count 2 2006.285.10:19:53.41#ibcon#read 6, iclass 12, count 2 2006.285.10:19:53.41#ibcon#end of sib2, iclass 12, count 2 2006.285.10:19:53.41#ibcon#*mode == 0, iclass 12, count 2 2006.285.10:19:53.41#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.10:19:53.41#ibcon#[27=AT07-04\r\n] 2006.285.10:19:53.41#ibcon#*before write, iclass 12, count 2 2006.285.10:19:53.41#ibcon#enter sib2, iclass 12, count 2 2006.285.10:19:53.41#ibcon#flushed, iclass 12, count 2 2006.285.10:19:53.41#ibcon#about to write, iclass 12, count 2 2006.285.10:19:53.41#ibcon#wrote, iclass 12, count 2 2006.285.10:19:53.41#ibcon#about to read 3, iclass 12, count 2 2006.285.10:19:53.44#ibcon#read 3, iclass 12, count 2 2006.285.10:19:53.44#ibcon#about to read 4, iclass 12, count 2 2006.285.10:19:53.44#ibcon#read 4, iclass 12, count 2 2006.285.10:19:53.44#ibcon#about to read 5, iclass 12, count 2 2006.285.10:19:53.44#ibcon#read 5, iclass 12, count 2 2006.285.10:19:53.44#ibcon#about to read 6, iclass 12, count 2 2006.285.10:19:53.44#ibcon#read 6, iclass 12, count 2 2006.285.10:19:53.44#ibcon#end of sib2, iclass 12, count 2 2006.285.10:19:53.44#ibcon#*after write, iclass 12, count 2 2006.285.10:19:53.44#ibcon#*before return 0, iclass 12, count 2 2006.285.10:19:53.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:19:53.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:19:53.44#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.10:19:53.44#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:53.44#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:19:53.56#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:19:53.56#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:19:53.56#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:19:53.56#ibcon#first serial, iclass 12, count 0 2006.285.10:19:53.56#ibcon#enter sib2, iclass 12, count 0 2006.285.10:19:53.56#ibcon#flushed, iclass 12, count 0 2006.285.10:19:53.56#ibcon#about to write, iclass 12, count 0 2006.285.10:19:53.56#ibcon#wrote, iclass 12, count 0 2006.285.10:19:53.56#ibcon#about to read 3, iclass 12, count 0 2006.285.10:19:53.58#ibcon#read 3, iclass 12, count 0 2006.285.10:19:53.58#ibcon#about to read 4, iclass 12, count 0 2006.285.10:19:53.58#ibcon#read 4, iclass 12, count 0 2006.285.10:19:53.58#ibcon#about to read 5, iclass 12, count 0 2006.285.10:19:53.58#ibcon#read 5, iclass 12, count 0 2006.285.10:19:53.58#ibcon#about to read 6, iclass 12, count 0 2006.285.10:19:53.58#ibcon#read 6, iclass 12, count 0 2006.285.10:19:53.58#ibcon#end of sib2, iclass 12, count 0 2006.285.10:19:53.58#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:19:53.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:19:53.58#ibcon#[27=USB\r\n] 2006.285.10:19:53.58#ibcon#*before write, iclass 12, count 0 2006.285.10:19:53.58#ibcon#enter sib2, iclass 12, count 0 2006.285.10:19:53.58#ibcon#flushed, iclass 12, count 0 2006.285.10:19:53.58#ibcon#about to write, iclass 12, count 0 2006.285.10:19:53.58#ibcon#wrote, iclass 12, count 0 2006.285.10:19:53.58#ibcon#about to read 3, iclass 12, count 0 2006.285.10:19:53.61#ibcon#read 3, iclass 12, count 0 2006.285.10:19:53.61#ibcon#about to read 4, iclass 12, count 0 2006.285.10:19:53.61#ibcon#read 4, iclass 12, count 0 2006.285.10:19:53.61#ibcon#about to read 5, iclass 12, count 0 2006.285.10:19:53.61#ibcon#read 5, iclass 12, count 0 2006.285.10:19:53.61#ibcon#about to read 6, iclass 12, count 0 2006.285.10:19:53.61#ibcon#read 6, iclass 12, count 0 2006.285.10:19:53.61#ibcon#end of sib2, iclass 12, count 0 2006.285.10:19:53.61#ibcon#*after write, iclass 12, count 0 2006.285.10:19:53.61#ibcon#*before return 0, iclass 12, count 0 2006.285.10:19:53.61#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:19:53.61#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:19:53.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:19:53.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:19:53.61$vck44/vblo=8,744.99 2006.285.10:19:53.61#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.10:19:53.61#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.10:19:53.61#ibcon#ireg 17 cls_cnt 0 2006.285.10:19:53.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:19:53.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:19:53.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:19:53.61#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:19:53.61#ibcon#first serial, iclass 14, count 0 2006.285.10:19:53.61#ibcon#enter sib2, iclass 14, count 0 2006.285.10:19:53.61#ibcon#flushed, iclass 14, count 0 2006.285.10:19:53.61#ibcon#about to write, iclass 14, count 0 2006.285.10:19:53.61#ibcon#wrote, iclass 14, count 0 2006.285.10:19:53.61#ibcon#about to read 3, iclass 14, count 0 2006.285.10:19:53.63#ibcon#read 3, iclass 14, count 0 2006.285.10:19:53.63#ibcon#about to read 4, iclass 14, count 0 2006.285.10:19:53.63#ibcon#read 4, iclass 14, count 0 2006.285.10:19:53.63#ibcon#about to read 5, iclass 14, count 0 2006.285.10:19:53.63#ibcon#read 5, iclass 14, count 0 2006.285.10:19:53.63#ibcon#about to read 6, iclass 14, count 0 2006.285.10:19:53.63#ibcon#read 6, iclass 14, count 0 2006.285.10:19:53.63#ibcon#end of sib2, iclass 14, count 0 2006.285.10:19:53.63#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:19:53.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:19:53.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:19:53.63#ibcon#*before write, iclass 14, count 0 2006.285.10:19:53.63#ibcon#enter sib2, iclass 14, count 0 2006.285.10:19:53.63#ibcon#flushed, iclass 14, count 0 2006.285.10:19:53.63#ibcon#about to write, iclass 14, count 0 2006.285.10:19:53.63#ibcon#wrote, iclass 14, count 0 2006.285.10:19:53.63#ibcon#about to read 3, iclass 14, count 0 2006.285.10:19:53.67#ibcon#read 3, iclass 14, count 0 2006.285.10:19:53.67#ibcon#about to read 4, iclass 14, count 0 2006.285.10:19:53.67#ibcon#read 4, iclass 14, count 0 2006.285.10:19:53.67#ibcon#about to read 5, iclass 14, count 0 2006.285.10:19:53.67#ibcon#read 5, iclass 14, count 0 2006.285.10:19:53.67#ibcon#about to read 6, iclass 14, count 0 2006.285.10:19:53.67#ibcon#read 6, iclass 14, count 0 2006.285.10:19:53.67#ibcon#end of sib2, iclass 14, count 0 2006.285.10:19:53.67#ibcon#*after write, iclass 14, count 0 2006.285.10:19:53.67#ibcon#*before return 0, iclass 14, count 0 2006.285.10:19:53.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:19:53.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:19:53.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:19:53.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:19:53.67$vck44/vb=8,4 2006.285.10:19:53.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.10:19:53.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.10:19:53.67#ibcon#ireg 11 cls_cnt 2 2006.285.10:19:53.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:19:53.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:19:53.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:19:53.73#ibcon#enter wrdev, iclass 16, count 2 2006.285.10:19:53.73#ibcon#first serial, iclass 16, count 2 2006.285.10:19:53.73#ibcon#enter sib2, iclass 16, count 2 2006.285.10:19:53.73#ibcon#flushed, iclass 16, count 2 2006.285.10:19:53.73#ibcon#about to write, iclass 16, count 2 2006.285.10:19:53.73#ibcon#wrote, iclass 16, count 2 2006.285.10:19:53.73#ibcon#about to read 3, iclass 16, count 2 2006.285.10:19:53.75#ibcon#read 3, iclass 16, count 2 2006.285.10:19:53.75#ibcon#about to read 4, iclass 16, count 2 2006.285.10:19:53.75#ibcon#read 4, iclass 16, count 2 2006.285.10:19:53.75#ibcon#about to read 5, iclass 16, count 2 2006.285.10:19:53.75#ibcon#read 5, iclass 16, count 2 2006.285.10:19:53.75#ibcon#about to read 6, iclass 16, count 2 2006.285.10:19:53.75#ibcon#read 6, iclass 16, count 2 2006.285.10:19:53.75#ibcon#end of sib2, iclass 16, count 2 2006.285.10:19:53.75#ibcon#*mode == 0, iclass 16, count 2 2006.285.10:19:53.75#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.10:19:53.75#ibcon#[27=AT08-04\r\n] 2006.285.10:19:53.75#ibcon#*before write, iclass 16, count 2 2006.285.10:19:53.75#ibcon#enter sib2, iclass 16, count 2 2006.285.10:19:53.75#ibcon#flushed, iclass 16, count 2 2006.285.10:19:53.75#ibcon#about to write, iclass 16, count 2 2006.285.10:19:53.75#ibcon#wrote, iclass 16, count 2 2006.285.10:19:53.75#ibcon#about to read 3, iclass 16, count 2 2006.285.10:19:53.78#ibcon#read 3, iclass 16, count 2 2006.285.10:19:53.78#ibcon#about to read 4, iclass 16, count 2 2006.285.10:19:53.78#ibcon#read 4, iclass 16, count 2 2006.285.10:19:53.78#ibcon#about to read 5, iclass 16, count 2 2006.285.10:19:53.78#ibcon#read 5, iclass 16, count 2 2006.285.10:19:53.78#ibcon#about to read 6, iclass 16, count 2 2006.285.10:19:53.78#ibcon#read 6, iclass 16, count 2 2006.285.10:19:53.78#ibcon#end of sib2, iclass 16, count 2 2006.285.10:19:53.78#ibcon#*after write, iclass 16, count 2 2006.285.10:19:53.78#ibcon#*before return 0, iclass 16, count 2 2006.285.10:19:53.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:19:53.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:19:53.78#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.10:19:53.78#ibcon#ireg 7 cls_cnt 0 2006.285.10:19:53.78#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:19:53.90#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:19:53.90#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:19:53.90#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:19:53.90#ibcon#first serial, iclass 16, count 0 2006.285.10:19:53.90#ibcon#enter sib2, iclass 16, count 0 2006.285.10:19:53.90#ibcon#flushed, iclass 16, count 0 2006.285.10:19:53.90#ibcon#about to write, iclass 16, count 0 2006.285.10:19:53.90#ibcon#wrote, iclass 16, count 0 2006.285.10:19:53.90#ibcon#about to read 3, iclass 16, count 0 2006.285.10:19:53.92#ibcon#read 3, iclass 16, count 0 2006.285.10:19:53.92#ibcon#about to read 4, iclass 16, count 0 2006.285.10:19:53.92#ibcon#read 4, iclass 16, count 0 2006.285.10:19:53.92#ibcon#about to read 5, iclass 16, count 0 2006.285.10:19:53.92#ibcon#read 5, iclass 16, count 0 2006.285.10:19:53.92#ibcon#about to read 6, iclass 16, count 0 2006.285.10:19:53.92#ibcon#read 6, iclass 16, count 0 2006.285.10:19:53.92#ibcon#end of sib2, iclass 16, count 0 2006.285.10:19:53.92#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:19:53.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:19:53.92#ibcon#[27=USB\r\n] 2006.285.10:19:53.92#ibcon#*before write, iclass 16, count 0 2006.285.10:19:53.92#ibcon#enter sib2, iclass 16, count 0 2006.285.10:19:53.92#ibcon#flushed, iclass 16, count 0 2006.285.10:19:53.92#ibcon#about to write, iclass 16, count 0 2006.285.10:19:53.92#ibcon#wrote, iclass 16, count 0 2006.285.10:19:53.92#ibcon#about to read 3, iclass 16, count 0 2006.285.10:19:53.95#ibcon#read 3, iclass 16, count 0 2006.285.10:19:53.95#ibcon#about to read 4, iclass 16, count 0 2006.285.10:19:53.95#ibcon#read 4, iclass 16, count 0 2006.285.10:19:53.95#ibcon#about to read 5, iclass 16, count 0 2006.285.10:19:53.95#ibcon#read 5, iclass 16, count 0 2006.285.10:19:53.95#ibcon#about to read 6, iclass 16, count 0 2006.285.10:19:53.95#ibcon#read 6, iclass 16, count 0 2006.285.10:19:53.95#ibcon#end of sib2, iclass 16, count 0 2006.285.10:19:53.95#ibcon#*after write, iclass 16, count 0 2006.285.10:19:53.95#ibcon#*before return 0, iclass 16, count 0 2006.285.10:19:53.95#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:19:53.95#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:19:53.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:19:53.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:19:53.95$vck44/vabw=wide 2006.285.10:19:53.95#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.10:19:53.95#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.10:19:53.95#ibcon#ireg 8 cls_cnt 0 2006.285.10:19:53.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:19:53.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:19:53.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:19:53.95#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:19:53.95#ibcon#first serial, iclass 18, count 0 2006.285.10:19:53.95#ibcon#enter sib2, iclass 18, count 0 2006.285.10:19:53.95#ibcon#flushed, iclass 18, count 0 2006.285.10:19:53.95#ibcon#about to write, iclass 18, count 0 2006.285.10:19:53.95#ibcon#wrote, iclass 18, count 0 2006.285.10:19:53.95#ibcon#about to read 3, iclass 18, count 0 2006.285.10:19:53.97#ibcon#read 3, iclass 18, count 0 2006.285.10:19:53.97#ibcon#about to read 4, iclass 18, count 0 2006.285.10:19:53.97#ibcon#read 4, iclass 18, count 0 2006.285.10:19:53.97#ibcon#about to read 5, iclass 18, count 0 2006.285.10:19:53.97#ibcon#read 5, iclass 18, count 0 2006.285.10:19:53.97#ibcon#about to read 6, iclass 18, count 0 2006.285.10:19:53.97#ibcon#read 6, iclass 18, count 0 2006.285.10:19:53.97#ibcon#end of sib2, iclass 18, count 0 2006.285.10:19:53.97#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:19:53.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:19:53.97#ibcon#[25=BW32\r\n] 2006.285.10:19:53.97#ibcon#*before write, iclass 18, count 0 2006.285.10:19:53.97#ibcon#enter sib2, iclass 18, count 0 2006.285.10:19:53.97#ibcon#flushed, iclass 18, count 0 2006.285.10:19:53.97#ibcon#about to write, iclass 18, count 0 2006.285.10:19:53.97#ibcon#wrote, iclass 18, count 0 2006.285.10:19:53.97#ibcon#about to read 3, iclass 18, count 0 2006.285.10:19:54.00#ibcon#read 3, iclass 18, count 0 2006.285.10:19:54.00#ibcon#about to read 4, iclass 18, count 0 2006.285.10:19:54.00#ibcon#read 4, iclass 18, count 0 2006.285.10:19:54.00#ibcon#about to read 5, iclass 18, count 0 2006.285.10:19:54.00#ibcon#read 5, iclass 18, count 0 2006.285.10:19:54.00#ibcon#about to read 6, iclass 18, count 0 2006.285.10:19:54.00#ibcon#read 6, iclass 18, count 0 2006.285.10:19:54.00#ibcon#end of sib2, iclass 18, count 0 2006.285.10:19:54.00#ibcon#*after write, iclass 18, count 0 2006.285.10:19:54.00#ibcon#*before return 0, iclass 18, count 0 2006.285.10:19:54.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:19:54.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:19:54.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:19:54.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:19:54.00$vck44/vbbw=wide 2006.285.10:19:54.00#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.10:19:54.00#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.10:19:54.00#ibcon#ireg 8 cls_cnt 0 2006.285.10:19:54.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:19:54.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:19:54.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:19:54.07#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:19:54.07#ibcon#first serial, iclass 20, count 0 2006.285.10:19:54.07#ibcon#enter sib2, iclass 20, count 0 2006.285.10:19:54.07#ibcon#flushed, iclass 20, count 0 2006.285.10:19:54.07#ibcon#about to write, iclass 20, count 0 2006.285.10:19:54.07#ibcon#wrote, iclass 20, count 0 2006.285.10:19:54.07#ibcon#about to read 3, iclass 20, count 0 2006.285.10:19:54.09#ibcon#read 3, iclass 20, count 0 2006.285.10:19:54.09#ibcon#about to read 4, iclass 20, count 0 2006.285.10:19:54.09#ibcon#read 4, iclass 20, count 0 2006.285.10:19:54.09#ibcon#about to read 5, iclass 20, count 0 2006.285.10:19:54.09#ibcon#read 5, iclass 20, count 0 2006.285.10:19:54.09#ibcon#about to read 6, iclass 20, count 0 2006.285.10:19:54.09#ibcon#read 6, iclass 20, count 0 2006.285.10:19:54.09#ibcon#end of sib2, iclass 20, count 0 2006.285.10:19:54.09#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:19:54.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:19:54.09#ibcon#[27=BW32\r\n] 2006.285.10:19:54.09#ibcon#*before write, iclass 20, count 0 2006.285.10:19:54.09#ibcon#enter sib2, iclass 20, count 0 2006.285.10:19:54.09#ibcon#flushed, iclass 20, count 0 2006.285.10:19:54.09#ibcon#about to write, iclass 20, count 0 2006.285.10:19:54.09#ibcon#wrote, iclass 20, count 0 2006.285.10:19:54.09#ibcon#about to read 3, iclass 20, count 0 2006.285.10:19:54.12#ibcon#read 3, iclass 20, count 0 2006.285.10:19:54.12#ibcon#about to read 4, iclass 20, count 0 2006.285.10:19:54.12#ibcon#read 4, iclass 20, count 0 2006.285.10:19:54.12#ibcon#about to read 5, iclass 20, count 0 2006.285.10:19:54.12#ibcon#read 5, iclass 20, count 0 2006.285.10:19:54.12#ibcon#about to read 6, iclass 20, count 0 2006.285.10:19:54.12#ibcon#read 6, iclass 20, count 0 2006.285.10:19:54.12#ibcon#end of sib2, iclass 20, count 0 2006.285.10:19:54.12#ibcon#*after write, iclass 20, count 0 2006.285.10:19:54.12#ibcon#*before return 0, iclass 20, count 0 2006.285.10:19:54.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:19:54.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:19:54.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:19:54.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:19:54.12$setupk4/ifdk4 2006.285.10:19:54.12$ifdk4/lo= 2006.285.10:19:54.12$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:19:54.12$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:19:54.12$ifdk4/patch= 2006.285.10:19:54.12$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:19:54.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:19:54.12$setupk4/!*+20s 2006.285.10:19:57.14#trakl#Source acquired 2006.285.10:19:58.14#flagr#flagr/antenna,acquired 2006.285.10:20:02.96#abcon#<5=/04 1.4 2.5 19.76 911015.0\r\n> 2006.285.10:20:02.98#abcon#{5=INTERFACE CLEAR} 2006.285.10:20:03.04#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:20:08.63$setupk4/"tpicd 2006.285.10:20:08.63$setupk4/echo=off 2006.285.10:20:08.63$setupk4/xlog=off 2006.285.10:20:08.63:!2006.285.10:20:44 2006.285.10:20:44.00:preob 2006.285.10:20:44.13/onsource/TRACKING 2006.285.10:20:44.13:!2006.285.10:20:54 2006.285.10:20:54.00:"tape 2006.285.10:20:54.00:"st=record 2006.285.10:20:54.00:data_valid=on 2006.285.10:20:54.00:midob 2006.285.10:20:55.13/onsource/TRACKING 2006.285.10:20:55.13/wx/19.76,1015.1,91 2006.285.10:20:55.18/cable/+6.4859E-03 2006.285.10:20:56.27/va/01,07,usb,yes,32,35 2006.285.10:20:56.27/va/02,06,usb,yes,33,33 2006.285.10:20:56.27/va/03,07,usb,yes,32,34 2006.285.10:20:56.27/va/04,06,usb,yes,34,35 2006.285.10:20:56.27/va/05,03,usb,yes,33,33 2006.285.10:20:56.27/va/06,04,usb,yes,30,29 2006.285.10:20:56.27/va/07,04,usb,yes,30,31 2006.285.10:20:56.27/va/08,03,usb,yes,31,38 2006.285.10:20:56.50/valo/01,524.99,yes,locked 2006.285.10:20:56.50/valo/02,534.99,yes,locked 2006.285.10:20:56.50/valo/03,564.99,yes,locked 2006.285.10:20:56.50/valo/04,624.99,yes,locked 2006.285.10:20:56.50/valo/05,734.99,yes,locked 2006.285.10:20:56.50/valo/06,814.99,yes,locked 2006.285.10:20:56.50/valo/07,864.99,yes,locked 2006.285.10:20:56.50/valo/08,884.99,yes,locked 2006.285.10:20:57.59/vb/01,04,usb,yes,31,29 2006.285.10:20:57.59/vb/02,05,usb,yes,29,29 2006.285.10:20:57.59/vb/03,04,usb,yes,30,33 2006.285.10:20:57.59/vb/04,05,usb,yes,31,29 2006.285.10:20:57.59/vb/05,04,usb,yes,27,29 2006.285.10:20:57.59/vb/06,03,usb,yes,39,34 2006.285.10:20:57.59/vb/07,04,usb,yes,31,31 2006.285.10:20:57.59/vb/08,04,usb,yes,28,32 2006.285.10:20:57.82/vblo/01,629.99,yes,locked 2006.285.10:20:57.82/vblo/02,634.99,yes,locked 2006.285.10:20:57.82/vblo/03,649.99,yes,locked 2006.285.10:20:57.82/vblo/04,679.99,yes,locked 2006.285.10:20:57.82/vblo/05,709.99,yes,locked 2006.285.10:20:57.82/vblo/06,719.99,yes,locked 2006.285.10:20:57.82/vblo/07,734.99,yes,locked 2006.285.10:20:57.82/vblo/08,744.99,yes,locked 2006.285.10:20:57.97/vabw/8 2006.285.10:20:58.12/vbbw/8 2006.285.10:20:58.21/xfe/off,on,12.0 2006.285.10:20:58.59/ifatt/23,28,28,28 2006.285.10:20:59.08/fmout-gps/S +2.67E-07 2006.285.10:20:59.10:!2006.285.10:21:54 2006.285.10:21:54.01:data_valid=off 2006.285.10:21:54.01:"et 2006.285.10:21:54.01:!+3s 2006.285.10:21:57.02:"tape 2006.285.10:21:57.02:postob 2006.285.10:21:57.27/cable/+6.4849E-03 2006.285.10:21:57.27/wx/19.77,1015.0,91 2006.285.10:21:58.08/fmout-gps/S +2.68E-07 2006.285.10:21:58.08:scan_name=285-1025,jd0610,40 2006.285.10:21:58.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.285.10:21:58.13#flagr#flagr/antenna,new-source 2006.285.10:21:59.13:checkk5 2006.285.10:21:59.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:22:00.00/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:22:00.41/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:22:00.77/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:22:01.19/chk_obsdata//k5ts1/T2851020??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.10:22:01.57/chk_obsdata//k5ts2/T2851020??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.10:22:01.98/chk_obsdata//k5ts3/T2851020??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.10:22:02.38/chk_obsdata//k5ts4/T2851020??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.10:22:03.12/k5log//k5ts1_log_newline 2006.285.10:22:04.05/k5log//k5ts2_log_newline 2006.285.10:22:04.72/k5log//k5ts3_log_newline 2006.285.10:22:05.53/k5log//k5ts4_log_newline 2006.285.10:22:05.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:22:05.55:setupk4=1 2006.285.10:22:05.55$setupk4/echo=on 2006.285.10:22:05.55$setupk4/pcalon 2006.285.10:22:05.55$pcalon/"no phase cal control is implemented here 2006.285.10:22:05.55$setupk4/"tpicd=stop 2006.285.10:22:05.55$setupk4/"rec=synch_on 2006.285.10:22:05.55$setupk4/"rec_mode=128 2006.285.10:22:05.55$setupk4/!* 2006.285.10:22:05.55$setupk4/recpk4 2006.285.10:22:05.55$recpk4/recpatch= 2006.285.10:22:05.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:22:05.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:22:05.55$setupk4/vck44 2006.285.10:22:05.55$vck44/valo=1,524.99 2006.285.10:22:05.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.10:22:05.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.10:22:05.55#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:05.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:22:05.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:22:05.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:22:05.55#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:22:05.55#ibcon#first serial, iclass 3, count 0 2006.285.10:22:05.55#ibcon#enter sib2, iclass 3, count 0 2006.285.10:22:05.55#ibcon#flushed, iclass 3, count 0 2006.285.10:22:05.55#ibcon#about to write, iclass 3, count 0 2006.285.10:22:05.55#ibcon#wrote, iclass 3, count 0 2006.285.10:22:05.55#ibcon#about to read 3, iclass 3, count 0 2006.285.10:22:05.57#ibcon#read 3, iclass 3, count 0 2006.285.10:22:05.57#ibcon#about to read 4, iclass 3, count 0 2006.285.10:22:05.57#ibcon#read 4, iclass 3, count 0 2006.285.10:22:05.57#ibcon#about to read 5, iclass 3, count 0 2006.285.10:22:05.57#ibcon#read 5, iclass 3, count 0 2006.285.10:22:05.57#ibcon#about to read 6, iclass 3, count 0 2006.285.10:22:05.57#ibcon#read 6, iclass 3, count 0 2006.285.10:22:05.57#ibcon#end of sib2, iclass 3, count 0 2006.285.10:22:05.57#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:22:05.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:22:05.57#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:22:05.57#ibcon#*before write, iclass 3, count 0 2006.285.10:22:05.57#ibcon#enter sib2, iclass 3, count 0 2006.285.10:22:05.57#ibcon#flushed, iclass 3, count 0 2006.285.10:22:05.57#ibcon#about to write, iclass 3, count 0 2006.285.10:22:05.57#ibcon#wrote, iclass 3, count 0 2006.285.10:22:05.57#ibcon#about to read 3, iclass 3, count 0 2006.285.10:22:05.62#ibcon#read 3, iclass 3, count 0 2006.285.10:22:05.62#ibcon#about to read 4, iclass 3, count 0 2006.285.10:22:05.62#ibcon#read 4, iclass 3, count 0 2006.285.10:22:05.62#ibcon#about to read 5, iclass 3, count 0 2006.285.10:22:05.62#ibcon#read 5, iclass 3, count 0 2006.285.10:22:05.62#ibcon#about to read 6, iclass 3, count 0 2006.285.10:22:05.62#ibcon#read 6, iclass 3, count 0 2006.285.10:22:05.62#ibcon#end of sib2, iclass 3, count 0 2006.285.10:22:05.62#ibcon#*after write, iclass 3, count 0 2006.285.10:22:05.62#ibcon#*before return 0, iclass 3, count 0 2006.285.10:22:05.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:22:05.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:22:05.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:22:05.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:22:05.62$vck44/va=1,7 2006.285.10:22:05.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.10:22:05.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.10:22:05.62#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:05.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:22:05.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:22:05.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:22:05.62#ibcon#enter wrdev, iclass 5, count 2 2006.285.10:22:05.62#ibcon#first serial, iclass 5, count 2 2006.285.10:22:05.62#ibcon#enter sib2, iclass 5, count 2 2006.285.10:22:05.62#ibcon#flushed, iclass 5, count 2 2006.285.10:22:05.62#ibcon#about to write, iclass 5, count 2 2006.285.10:22:05.62#ibcon#wrote, iclass 5, count 2 2006.285.10:22:05.62#ibcon#about to read 3, iclass 5, count 2 2006.285.10:22:05.64#ibcon#read 3, iclass 5, count 2 2006.285.10:22:05.64#ibcon#about to read 4, iclass 5, count 2 2006.285.10:22:05.64#ibcon#read 4, iclass 5, count 2 2006.285.10:22:05.64#ibcon#about to read 5, iclass 5, count 2 2006.285.10:22:05.64#ibcon#read 5, iclass 5, count 2 2006.285.10:22:05.64#ibcon#about to read 6, iclass 5, count 2 2006.285.10:22:05.64#ibcon#read 6, iclass 5, count 2 2006.285.10:22:05.64#ibcon#end of sib2, iclass 5, count 2 2006.285.10:22:05.64#ibcon#*mode == 0, iclass 5, count 2 2006.285.10:22:05.64#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.10:22:05.64#ibcon#[25=AT01-07\r\n] 2006.285.10:22:05.64#ibcon#*before write, iclass 5, count 2 2006.285.10:22:05.64#ibcon#enter sib2, iclass 5, count 2 2006.285.10:22:05.64#ibcon#flushed, iclass 5, count 2 2006.285.10:22:05.64#ibcon#about to write, iclass 5, count 2 2006.285.10:22:05.64#ibcon#wrote, iclass 5, count 2 2006.285.10:22:05.64#ibcon#about to read 3, iclass 5, count 2 2006.285.10:22:05.67#ibcon#read 3, iclass 5, count 2 2006.285.10:22:05.67#ibcon#about to read 4, iclass 5, count 2 2006.285.10:22:05.67#ibcon#read 4, iclass 5, count 2 2006.285.10:22:05.67#ibcon#about to read 5, iclass 5, count 2 2006.285.10:22:05.67#ibcon#read 5, iclass 5, count 2 2006.285.10:22:05.67#ibcon#about to read 6, iclass 5, count 2 2006.285.10:22:05.67#ibcon#read 6, iclass 5, count 2 2006.285.10:22:05.67#ibcon#end of sib2, iclass 5, count 2 2006.285.10:22:05.67#ibcon#*after write, iclass 5, count 2 2006.285.10:22:05.67#ibcon#*before return 0, iclass 5, count 2 2006.285.10:22:05.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:22:05.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:22:05.67#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.10:22:05.67#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:05.67#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:22:05.79#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:22:05.79#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:22:05.79#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:22:05.79#ibcon#first serial, iclass 5, count 0 2006.285.10:22:05.79#ibcon#enter sib2, iclass 5, count 0 2006.285.10:22:05.79#ibcon#flushed, iclass 5, count 0 2006.285.10:22:05.79#ibcon#about to write, iclass 5, count 0 2006.285.10:22:05.79#ibcon#wrote, iclass 5, count 0 2006.285.10:22:05.79#ibcon#about to read 3, iclass 5, count 0 2006.285.10:22:05.81#ibcon#read 3, iclass 5, count 0 2006.285.10:22:05.81#ibcon#about to read 4, iclass 5, count 0 2006.285.10:22:05.81#ibcon#read 4, iclass 5, count 0 2006.285.10:22:05.81#ibcon#about to read 5, iclass 5, count 0 2006.285.10:22:05.81#ibcon#read 5, iclass 5, count 0 2006.285.10:22:05.81#ibcon#about to read 6, iclass 5, count 0 2006.285.10:22:05.81#ibcon#read 6, iclass 5, count 0 2006.285.10:22:05.81#ibcon#end of sib2, iclass 5, count 0 2006.285.10:22:05.81#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:22:05.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:22:05.81#ibcon#[25=USB\r\n] 2006.285.10:22:05.81#ibcon#*before write, iclass 5, count 0 2006.285.10:22:05.81#ibcon#enter sib2, iclass 5, count 0 2006.285.10:22:05.81#ibcon#flushed, iclass 5, count 0 2006.285.10:22:05.81#ibcon#about to write, iclass 5, count 0 2006.285.10:22:05.81#ibcon#wrote, iclass 5, count 0 2006.285.10:22:05.81#ibcon#about to read 3, iclass 5, count 0 2006.285.10:22:05.84#ibcon#read 3, iclass 5, count 0 2006.285.10:22:05.84#ibcon#about to read 4, iclass 5, count 0 2006.285.10:22:05.84#ibcon#read 4, iclass 5, count 0 2006.285.10:22:05.84#ibcon#about to read 5, iclass 5, count 0 2006.285.10:22:05.84#ibcon#read 5, iclass 5, count 0 2006.285.10:22:05.84#ibcon#about to read 6, iclass 5, count 0 2006.285.10:22:05.84#ibcon#read 6, iclass 5, count 0 2006.285.10:22:05.84#ibcon#end of sib2, iclass 5, count 0 2006.285.10:22:05.84#ibcon#*after write, iclass 5, count 0 2006.285.10:22:05.84#ibcon#*before return 0, iclass 5, count 0 2006.285.10:22:05.84#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:22:05.84#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:22:05.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:22:05.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:22:05.84$vck44/valo=2,534.99 2006.285.10:22:05.84#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.10:22:05.84#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.10:22:05.84#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:05.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:22:05.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:22:05.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:22:05.84#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:22:05.84#ibcon#first serial, iclass 7, count 0 2006.285.10:22:05.84#ibcon#enter sib2, iclass 7, count 0 2006.285.10:22:05.84#ibcon#flushed, iclass 7, count 0 2006.285.10:22:05.84#ibcon#about to write, iclass 7, count 0 2006.285.10:22:05.84#ibcon#wrote, iclass 7, count 0 2006.285.10:22:05.84#ibcon#about to read 3, iclass 7, count 0 2006.285.10:22:05.86#ibcon#read 3, iclass 7, count 0 2006.285.10:22:05.86#ibcon#about to read 4, iclass 7, count 0 2006.285.10:22:05.86#ibcon#read 4, iclass 7, count 0 2006.285.10:22:05.86#ibcon#about to read 5, iclass 7, count 0 2006.285.10:22:05.86#ibcon#read 5, iclass 7, count 0 2006.285.10:22:05.86#ibcon#about to read 6, iclass 7, count 0 2006.285.10:22:05.86#ibcon#read 6, iclass 7, count 0 2006.285.10:22:05.86#ibcon#end of sib2, iclass 7, count 0 2006.285.10:22:05.86#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:22:05.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:22:05.86#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:22:05.86#ibcon#*before write, iclass 7, count 0 2006.285.10:22:05.86#ibcon#enter sib2, iclass 7, count 0 2006.285.10:22:05.86#ibcon#flushed, iclass 7, count 0 2006.285.10:22:05.86#ibcon#about to write, iclass 7, count 0 2006.285.10:22:05.86#ibcon#wrote, iclass 7, count 0 2006.285.10:22:05.86#ibcon#about to read 3, iclass 7, count 0 2006.285.10:22:05.90#ibcon#read 3, iclass 7, count 0 2006.285.10:22:05.90#ibcon#about to read 4, iclass 7, count 0 2006.285.10:22:05.90#ibcon#read 4, iclass 7, count 0 2006.285.10:22:05.90#ibcon#about to read 5, iclass 7, count 0 2006.285.10:22:05.90#ibcon#read 5, iclass 7, count 0 2006.285.10:22:05.90#ibcon#about to read 6, iclass 7, count 0 2006.285.10:22:05.90#ibcon#read 6, iclass 7, count 0 2006.285.10:22:05.90#ibcon#end of sib2, iclass 7, count 0 2006.285.10:22:05.90#ibcon#*after write, iclass 7, count 0 2006.285.10:22:05.90#ibcon#*before return 0, iclass 7, count 0 2006.285.10:22:05.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:22:05.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:22:05.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:22:05.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:22:05.90$vck44/va=2,6 2006.285.10:22:05.90#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.10:22:05.90#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.10:22:05.90#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:05.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:22:05.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:22:05.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:22:05.96#ibcon#enter wrdev, iclass 11, count 2 2006.285.10:22:05.96#ibcon#first serial, iclass 11, count 2 2006.285.10:22:05.96#ibcon#enter sib2, iclass 11, count 2 2006.285.10:22:05.96#ibcon#flushed, iclass 11, count 2 2006.285.10:22:05.96#ibcon#about to write, iclass 11, count 2 2006.285.10:22:05.96#ibcon#wrote, iclass 11, count 2 2006.285.10:22:05.96#ibcon#about to read 3, iclass 11, count 2 2006.285.10:22:05.98#ibcon#read 3, iclass 11, count 2 2006.285.10:22:05.98#ibcon#about to read 4, iclass 11, count 2 2006.285.10:22:05.98#ibcon#read 4, iclass 11, count 2 2006.285.10:22:05.98#ibcon#about to read 5, iclass 11, count 2 2006.285.10:22:05.98#ibcon#read 5, iclass 11, count 2 2006.285.10:22:05.98#ibcon#about to read 6, iclass 11, count 2 2006.285.10:22:05.98#ibcon#read 6, iclass 11, count 2 2006.285.10:22:05.98#ibcon#end of sib2, iclass 11, count 2 2006.285.10:22:05.98#ibcon#*mode == 0, iclass 11, count 2 2006.285.10:22:05.98#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.10:22:05.98#ibcon#[25=AT02-06\r\n] 2006.285.10:22:05.98#ibcon#*before write, iclass 11, count 2 2006.285.10:22:05.98#ibcon#enter sib2, iclass 11, count 2 2006.285.10:22:05.98#ibcon#flushed, iclass 11, count 2 2006.285.10:22:05.98#ibcon#about to write, iclass 11, count 2 2006.285.10:22:05.98#ibcon#wrote, iclass 11, count 2 2006.285.10:22:05.98#ibcon#about to read 3, iclass 11, count 2 2006.285.10:22:06.01#ibcon#read 3, iclass 11, count 2 2006.285.10:22:06.01#ibcon#about to read 4, iclass 11, count 2 2006.285.10:22:06.01#ibcon#read 4, iclass 11, count 2 2006.285.10:22:06.01#ibcon#about to read 5, iclass 11, count 2 2006.285.10:22:06.01#ibcon#read 5, iclass 11, count 2 2006.285.10:22:06.01#ibcon#about to read 6, iclass 11, count 2 2006.285.10:22:06.01#ibcon#read 6, iclass 11, count 2 2006.285.10:22:06.01#ibcon#end of sib2, iclass 11, count 2 2006.285.10:22:06.01#ibcon#*after write, iclass 11, count 2 2006.285.10:22:06.01#ibcon#*before return 0, iclass 11, count 2 2006.285.10:22:06.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:22:06.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:22:06.01#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.10:22:06.01#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:06.01#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:22:06.13#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:22:06.13#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:22:06.13#ibcon#enter wrdev, iclass 11, count 0 2006.285.10:22:06.13#ibcon#first serial, iclass 11, count 0 2006.285.10:22:06.13#ibcon#enter sib2, iclass 11, count 0 2006.285.10:22:06.13#ibcon#flushed, iclass 11, count 0 2006.285.10:22:06.13#ibcon#about to write, iclass 11, count 0 2006.285.10:22:06.13#ibcon#wrote, iclass 11, count 0 2006.285.10:22:06.13#ibcon#about to read 3, iclass 11, count 0 2006.285.10:22:06.15#ibcon#read 3, iclass 11, count 0 2006.285.10:22:06.15#ibcon#about to read 4, iclass 11, count 0 2006.285.10:22:06.15#ibcon#read 4, iclass 11, count 0 2006.285.10:22:06.15#ibcon#about to read 5, iclass 11, count 0 2006.285.10:22:06.15#ibcon#read 5, iclass 11, count 0 2006.285.10:22:06.15#ibcon#about to read 6, iclass 11, count 0 2006.285.10:22:06.15#ibcon#read 6, iclass 11, count 0 2006.285.10:22:06.15#ibcon#end of sib2, iclass 11, count 0 2006.285.10:22:06.15#ibcon#*mode == 0, iclass 11, count 0 2006.285.10:22:06.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.10:22:06.15#ibcon#[25=USB\r\n] 2006.285.10:22:06.15#ibcon#*before write, iclass 11, count 0 2006.285.10:22:06.15#ibcon#enter sib2, iclass 11, count 0 2006.285.10:22:06.15#ibcon#flushed, iclass 11, count 0 2006.285.10:22:06.15#ibcon#about to write, iclass 11, count 0 2006.285.10:22:06.15#ibcon#wrote, iclass 11, count 0 2006.285.10:22:06.15#ibcon#about to read 3, iclass 11, count 0 2006.285.10:22:06.18#ibcon#read 3, iclass 11, count 0 2006.285.10:22:06.18#ibcon#about to read 4, iclass 11, count 0 2006.285.10:22:06.18#ibcon#read 4, iclass 11, count 0 2006.285.10:22:06.18#ibcon#about to read 5, iclass 11, count 0 2006.285.10:22:06.18#ibcon#read 5, iclass 11, count 0 2006.285.10:22:06.18#ibcon#about to read 6, iclass 11, count 0 2006.285.10:22:06.18#ibcon#read 6, iclass 11, count 0 2006.285.10:22:06.18#ibcon#end of sib2, iclass 11, count 0 2006.285.10:22:06.18#ibcon#*after write, iclass 11, count 0 2006.285.10:22:06.18#ibcon#*before return 0, iclass 11, count 0 2006.285.10:22:06.18#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:22:06.18#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:22:06.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.10:22:06.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.10:22:06.18$vck44/valo=3,564.99 2006.285.10:22:06.18#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.10:22:06.18#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.10:22:06.18#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:06.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:22:06.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:22:06.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:22:06.18#ibcon#enter wrdev, iclass 13, count 0 2006.285.10:22:06.18#ibcon#first serial, iclass 13, count 0 2006.285.10:22:06.18#ibcon#enter sib2, iclass 13, count 0 2006.285.10:22:06.18#ibcon#flushed, iclass 13, count 0 2006.285.10:22:06.18#ibcon#about to write, iclass 13, count 0 2006.285.10:22:06.18#ibcon#wrote, iclass 13, count 0 2006.285.10:22:06.18#ibcon#about to read 3, iclass 13, count 0 2006.285.10:22:06.20#ibcon#read 3, iclass 13, count 0 2006.285.10:22:06.20#ibcon#about to read 4, iclass 13, count 0 2006.285.10:22:06.20#ibcon#read 4, iclass 13, count 0 2006.285.10:22:06.20#ibcon#about to read 5, iclass 13, count 0 2006.285.10:22:06.20#ibcon#read 5, iclass 13, count 0 2006.285.10:22:06.20#ibcon#about to read 6, iclass 13, count 0 2006.285.10:22:06.20#ibcon#read 6, iclass 13, count 0 2006.285.10:22:06.20#ibcon#end of sib2, iclass 13, count 0 2006.285.10:22:06.20#ibcon#*mode == 0, iclass 13, count 0 2006.285.10:22:06.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.10:22:06.20#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:22:06.20#ibcon#*before write, iclass 13, count 0 2006.285.10:22:06.20#ibcon#enter sib2, iclass 13, count 0 2006.285.10:22:06.20#ibcon#flushed, iclass 13, count 0 2006.285.10:22:06.20#ibcon#about to write, iclass 13, count 0 2006.285.10:22:06.20#ibcon#wrote, iclass 13, count 0 2006.285.10:22:06.20#ibcon#about to read 3, iclass 13, count 0 2006.285.10:22:06.24#ibcon#read 3, iclass 13, count 0 2006.285.10:22:06.24#ibcon#about to read 4, iclass 13, count 0 2006.285.10:22:06.24#ibcon#read 4, iclass 13, count 0 2006.285.10:22:06.24#ibcon#about to read 5, iclass 13, count 0 2006.285.10:22:06.24#ibcon#read 5, iclass 13, count 0 2006.285.10:22:06.24#ibcon#about to read 6, iclass 13, count 0 2006.285.10:22:06.24#ibcon#read 6, iclass 13, count 0 2006.285.10:22:06.24#ibcon#end of sib2, iclass 13, count 0 2006.285.10:22:06.24#ibcon#*after write, iclass 13, count 0 2006.285.10:22:06.24#ibcon#*before return 0, iclass 13, count 0 2006.285.10:22:06.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:22:06.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:22:06.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.10:22:06.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.10:22:06.24$vck44/va=3,7 2006.285.10:22:06.24#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.10:22:06.24#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.10:22:06.24#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:06.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:22:06.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:22:06.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:22:06.30#ibcon#enter wrdev, iclass 15, count 2 2006.285.10:22:06.30#ibcon#first serial, iclass 15, count 2 2006.285.10:22:06.30#ibcon#enter sib2, iclass 15, count 2 2006.285.10:22:06.30#ibcon#flushed, iclass 15, count 2 2006.285.10:22:06.30#ibcon#about to write, iclass 15, count 2 2006.285.10:22:06.30#ibcon#wrote, iclass 15, count 2 2006.285.10:22:06.30#ibcon#about to read 3, iclass 15, count 2 2006.285.10:22:06.32#ibcon#read 3, iclass 15, count 2 2006.285.10:22:06.32#ibcon#about to read 4, iclass 15, count 2 2006.285.10:22:06.32#ibcon#read 4, iclass 15, count 2 2006.285.10:22:06.32#ibcon#about to read 5, iclass 15, count 2 2006.285.10:22:06.32#ibcon#read 5, iclass 15, count 2 2006.285.10:22:06.32#ibcon#about to read 6, iclass 15, count 2 2006.285.10:22:06.32#ibcon#read 6, iclass 15, count 2 2006.285.10:22:06.32#ibcon#end of sib2, iclass 15, count 2 2006.285.10:22:06.32#ibcon#*mode == 0, iclass 15, count 2 2006.285.10:22:06.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.10:22:06.32#ibcon#[25=AT03-07\r\n] 2006.285.10:22:06.32#ibcon#*before write, iclass 15, count 2 2006.285.10:22:06.32#ibcon#enter sib2, iclass 15, count 2 2006.285.10:22:06.32#ibcon#flushed, iclass 15, count 2 2006.285.10:22:06.32#ibcon#about to write, iclass 15, count 2 2006.285.10:22:06.32#ibcon#wrote, iclass 15, count 2 2006.285.10:22:06.32#ibcon#about to read 3, iclass 15, count 2 2006.285.10:22:06.35#ibcon#read 3, iclass 15, count 2 2006.285.10:22:06.35#ibcon#about to read 4, iclass 15, count 2 2006.285.10:22:06.35#ibcon#read 4, iclass 15, count 2 2006.285.10:22:06.35#ibcon#about to read 5, iclass 15, count 2 2006.285.10:22:06.35#ibcon#read 5, iclass 15, count 2 2006.285.10:22:06.35#ibcon#about to read 6, iclass 15, count 2 2006.285.10:22:06.35#ibcon#read 6, iclass 15, count 2 2006.285.10:22:06.35#ibcon#end of sib2, iclass 15, count 2 2006.285.10:22:06.35#ibcon#*after write, iclass 15, count 2 2006.285.10:22:06.35#ibcon#*before return 0, iclass 15, count 2 2006.285.10:22:06.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:22:06.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:22:06.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.10:22:06.35#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:06.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:22:06.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:22:06.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:22:06.47#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:22:06.47#ibcon#first serial, iclass 15, count 0 2006.285.10:22:06.47#ibcon#enter sib2, iclass 15, count 0 2006.285.10:22:06.47#ibcon#flushed, iclass 15, count 0 2006.285.10:22:06.47#ibcon#about to write, iclass 15, count 0 2006.285.10:22:06.47#ibcon#wrote, iclass 15, count 0 2006.285.10:22:06.47#ibcon#about to read 3, iclass 15, count 0 2006.285.10:22:06.49#ibcon#read 3, iclass 15, count 0 2006.285.10:22:06.49#ibcon#about to read 4, iclass 15, count 0 2006.285.10:22:06.49#ibcon#read 4, iclass 15, count 0 2006.285.10:22:06.49#ibcon#about to read 5, iclass 15, count 0 2006.285.10:22:06.49#ibcon#read 5, iclass 15, count 0 2006.285.10:22:06.49#ibcon#about to read 6, iclass 15, count 0 2006.285.10:22:06.49#ibcon#read 6, iclass 15, count 0 2006.285.10:22:06.49#ibcon#end of sib2, iclass 15, count 0 2006.285.10:22:06.49#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:22:06.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:22:06.49#ibcon#[25=USB\r\n] 2006.285.10:22:06.49#ibcon#*before write, iclass 15, count 0 2006.285.10:22:06.49#ibcon#enter sib2, iclass 15, count 0 2006.285.10:22:06.49#ibcon#flushed, iclass 15, count 0 2006.285.10:22:06.49#ibcon#about to write, iclass 15, count 0 2006.285.10:22:06.49#ibcon#wrote, iclass 15, count 0 2006.285.10:22:06.49#ibcon#about to read 3, iclass 15, count 0 2006.285.10:22:06.52#ibcon#read 3, iclass 15, count 0 2006.285.10:22:06.52#ibcon#about to read 4, iclass 15, count 0 2006.285.10:22:06.52#ibcon#read 4, iclass 15, count 0 2006.285.10:22:06.52#ibcon#about to read 5, iclass 15, count 0 2006.285.10:22:06.52#ibcon#read 5, iclass 15, count 0 2006.285.10:22:06.52#ibcon#about to read 6, iclass 15, count 0 2006.285.10:22:06.52#ibcon#read 6, iclass 15, count 0 2006.285.10:22:06.52#ibcon#end of sib2, iclass 15, count 0 2006.285.10:22:06.52#ibcon#*after write, iclass 15, count 0 2006.285.10:22:06.52#ibcon#*before return 0, iclass 15, count 0 2006.285.10:22:06.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:22:06.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:22:06.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:22:06.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:22:06.52$vck44/valo=4,624.99 2006.285.10:22:06.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.10:22:06.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.10:22:06.52#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:06.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:22:06.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:22:06.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:22:06.52#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:22:06.52#ibcon#first serial, iclass 17, count 0 2006.285.10:22:06.52#ibcon#enter sib2, iclass 17, count 0 2006.285.10:22:06.52#ibcon#flushed, iclass 17, count 0 2006.285.10:22:06.52#ibcon#about to write, iclass 17, count 0 2006.285.10:22:06.52#ibcon#wrote, iclass 17, count 0 2006.285.10:22:06.52#ibcon#about to read 3, iclass 17, count 0 2006.285.10:22:06.54#ibcon#read 3, iclass 17, count 0 2006.285.10:22:06.54#ibcon#about to read 4, iclass 17, count 0 2006.285.10:22:06.54#ibcon#read 4, iclass 17, count 0 2006.285.10:22:06.54#ibcon#about to read 5, iclass 17, count 0 2006.285.10:22:06.54#ibcon#read 5, iclass 17, count 0 2006.285.10:22:06.54#ibcon#about to read 6, iclass 17, count 0 2006.285.10:22:06.54#ibcon#read 6, iclass 17, count 0 2006.285.10:22:06.54#ibcon#end of sib2, iclass 17, count 0 2006.285.10:22:06.54#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:22:06.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:22:06.54#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:22:06.54#ibcon#*before write, iclass 17, count 0 2006.285.10:22:06.54#ibcon#enter sib2, iclass 17, count 0 2006.285.10:22:06.54#ibcon#flushed, iclass 17, count 0 2006.285.10:22:06.54#ibcon#about to write, iclass 17, count 0 2006.285.10:22:06.54#ibcon#wrote, iclass 17, count 0 2006.285.10:22:06.54#ibcon#about to read 3, iclass 17, count 0 2006.285.10:22:06.58#ibcon#read 3, iclass 17, count 0 2006.285.10:22:06.58#ibcon#about to read 4, iclass 17, count 0 2006.285.10:22:06.58#ibcon#read 4, iclass 17, count 0 2006.285.10:22:06.58#ibcon#about to read 5, iclass 17, count 0 2006.285.10:22:06.58#ibcon#read 5, iclass 17, count 0 2006.285.10:22:06.58#ibcon#about to read 6, iclass 17, count 0 2006.285.10:22:06.58#ibcon#read 6, iclass 17, count 0 2006.285.10:22:06.58#ibcon#end of sib2, iclass 17, count 0 2006.285.10:22:06.58#ibcon#*after write, iclass 17, count 0 2006.285.10:22:06.58#ibcon#*before return 0, iclass 17, count 0 2006.285.10:22:06.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:22:06.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:22:06.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:22:06.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:22:06.58$vck44/va=4,6 2006.285.10:22:06.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.10:22:06.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.10:22:06.58#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:06.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:22:06.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:22:06.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:22:06.64#ibcon#enter wrdev, iclass 19, count 2 2006.285.10:22:06.64#ibcon#first serial, iclass 19, count 2 2006.285.10:22:06.64#ibcon#enter sib2, iclass 19, count 2 2006.285.10:22:06.64#ibcon#flushed, iclass 19, count 2 2006.285.10:22:06.64#ibcon#about to write, iclass 19, count 2 2006.285.10:22:06.64#ibcon#wrote, iclass 19, count 2 2006.285.10:22:06.64#ibcon#about to read 3, iclass 19, count 2 2006.285.10:22:06.66#ibcon#read 3, iclass 19, count 2 2006.285.10:22:06.66#ibcon#about to read 4, iclass 19, count 2 2006.285.10:22:06.66#ibcon#read 4, iclass 19, count 2 2006.285.10:22:06.66#ibcon#about to read 5, iclass 19, count 2 2006.285.10:22:06.66#ibcon#read 5, iclass 19, count 2 2006.285.10:22:06.66#ibcon#about to read 6, iclass 19, count 2 2006.285.10:22:06.66#ibcon#read 6, iclass 19, count 2 2006.285.10:22:06.66#ibcon#end of sib2, iclass 19, count 2 2006.285.10:22:06.66#ibcon#*mode == 0, iclass 19, count 2 2006.285.10:22:06.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.10:22:06.66#ibcon#[25=AT04-06\r\n] 2006.285.10:22:06.66#ibcon#*before write, iclass 19, count 2 2006.285.10:22:06.66#ibcon#enter sib2, iclass 19, count 2 2006.285.10:22:06.66#ibcon#flushed, iclass 19, count 2 2006.285.10:22:06.66#ibcon#about to write, iclass 19, count 2 2006.285.10:22:06.66#ibcon#wrote, iclass 19, count 2 2006.285.10:22:06.66#ibcon#about to read 3, iclass 19, count 2 2006.285.10:22:06.69#ibcon#read 3, iclass 19, count 2 2006.285.10:22:06.69#ibcon#about to read 4, iclass 19, count 2 2006.285.10:22:06.69#ibcon#read 4, iclass 19, count 2 2006.285.10:22:06.69#ibcon#about to read 5, iclass 19, count 2 2006.285.10:22:06.69#ibcon#read 5, iclass 19, count 2 2006.285.10:22:06.69#ibcon#about to read 6, iclass 19, count 2 2006.285.10:22:06.69#ibcon#read 6, iclass 19, count 2 2006.285.10:22:06.69#ibcon#end of sib2, iclass 19, count 2 2006.285.10:22:06.69#ibcon#*after write, iclass 19, count 2 2006.285.10:22:06.69#ibcon#*before return 0, iclass 19, count 2 2006.285.10:22:06.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:22:06.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:22:06.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.10:22:06.69#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:06.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:22:06.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:22:06.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:22:06.81#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:22:06.81#ibcon#first serial, iclass 19, count 0 2006.285.10:22:06.81#ibcon#enter sib2, iclass 19, count 0 2006.285.10:22:06.81#ibcon#flushed, iclass 19, count 0 2006.285.10:22:06.81#ibcon#about to write, iclass 19, count 0 2006.285.10:22:06.81#ibcon#wrote, iclass 19, count 0 2006.285.10:22:06.81#ibcon#about to read 3, iclass 19, count 0 2006.285.10:22:06.83#ibcon#read 3, iclass 19, count 0 2006.285.10:22:06.83#ibcon#about to read 4, iclass 19, count 0 2006.285.10:22:06.83#ibcon#read 4, iclass 19, count 0 2006.285.10:22:06.83#ibcon#about to read 5, iclass 19, count 0 2006.285.10:22:06.83#ibcon#read 5, iclass 19, count 0 2006.285.10:22:06.83#ibcon#about to read 6, iclass 19, count 0 2006.285.10:22:06.83#ibcon#read 6, iclass 19, count 0 2006.285.10:22:06.83#ibcon#end of sib2, iclass 19, count 0 2006.285.10:22:06.83#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:22:06.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:22:06.83#ibcon#[25=USB\r\n] 2006.285.10:22:06.83#ibcon#*before write, iclass 19, count 0 2006.285.10:22:06.83#ibcon#enter sib2, iclass 19, count 0 2006.285.10:22:06.83#ibcon#flushed, iclass 19, count 0 2006.285.10:22:06.83#ibcon#about to write, iclass 19, count 0 2006.285.10:22:06.83#ibcon#wrote, iclass 19, count 0 2006.285.10:22:06.83#ibcon#about to read 3, iclass 19, count 0 2006.285.10:22:06.86#ibcon#read 3, iclass 19, count 0 2006.285.10:22:06.86#ibcon#about to read 4, iclass 19, count 0 2006.285.10:22:06.86#ibcon#read 4, iclass 19, count 0 2006.285.10:22:06.86#ibcon#about to read 5, iclass 19, count 0 2006.285.10:22:06.86#ibcon#read 5, iclass 19, count 0 2006.285.10:22:06.86#ibcon#about to read 6, iclass 19, count 0 2006.285.10:22:06.86#ibcon#read 6, iclass 19, count 0 2006.285.10:22:06.86#ibcon#end of sib2, iclass 19, count 0 2006.285.10:22:06.86#ibcon#*after write, iclass 19, count 0 2006.285.10:22:06.86#ibcon#*before return 0, iclass 19, count 0 2006.285.10:22:06.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:22:06.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:22:06.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:22:06.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:22:06.86$vck44/valo=5,734.99 2006.285.10:22:06.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.10:22:06.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.10:22:06.86#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:06.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:22:06.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:22:06.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:22:06.86#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:22:06.86#ibcon#first serial, iclass 21, count 0 2006.285.10:22:06.86#ibcon#enter sib2, iclass 21, count 0 2006.285.10:22:06.86#ibcon#flushed, iclass 21, count 0 2006.285.10:22:06.86#ibcon#about to write, iclass 21, count 0 2006.285.10:22:06.86#ibcon#wrote, iclass 21, count 0 2006.285.10:22:06.86#ibcon#about to read 3, iclass 21, count 0 2006.285.10:22:06.88#ibcon#read 3, iclass 21, count 0 2006.285.10:22:06.88#ibcon#about to read 4, iclass 21, count 0 2006.285.10:22:06.88#ibcon#read 4, iclass 21, count 0 2006.285.10:22:06.88#ibcon#about to read 5, iclass 21, count 0 2006.285.10:22:06.88#ibcon#read 5, iclass 21, count 0 2006.285.10:22:06.88#ibcon#about to read 6, iclass 21, count 0 2006.285.10:22:06.88#ibcon#read 6, iclass 21, count 0 2006.285.10:22:06.88#ibcon#end of sib2, iclass 21, count 0 2006.285.10:22:06.88#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:22:06.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:22:06.88#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:22:06.88#ibcon#*before write, iclass 21, count 0 2006.285.10:22:06.88#ibcon#enter sib2, iclass 21, count 0 2006.285.10:22:06.88#ibcon#flushed, iclass 21, count 0 2006.285.10:22:06.88#ibcon#about to write, iclass 21, count 0 2006.285.10:22:06.88#ibcon#wrote, iclass 21, count 0 2006.285.10:22:06.88#ibcon#about to read 3, iclass 21, count 0 2006.285.10:22:06.92#ibcon#read 3, iclass 21, count 0 2006.285.10:22:06.92#ibcon#about to read 4, iclass 21, count 0 2006.285.10:22:06.92#ibcon#read 4, iclass 21, count 0 2006.285.10:22:06.92#ibcon#about to read 5, iclass 21, count 0 2006.285.10:22:06.92#ibcon#read 5, iclass 21, count 0 2006.285.10:22:06.92#ibcon#about to read 6, iclass 21, count 0 2006.285.10:22:06.92#ibcon#read 6, iclass 21, count 0 2006.285.10:22:06.92#ibcon#end of sib2, iclass 21, count 0 2006.285.10:22:06.92#ibcon#*after write, iclass 21, count 0 2006.285.10:22:06.92#ibcon#*before return 0, iclass 21, count 0 2006.285.10:22:06.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:22:06.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:22:06.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:22:06.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:22:06.92$vck44/va=5,3 2006.285.10:22:06.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.10:22:06.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.10:22:06.92#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:06.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:22:06.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:22:06.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:22:06.98#ibcon#enter wrdev, iclass 23, count 2 2006.285.10:22:06.98#ibcon#first serial, iclass 23, count 2 2006.285.10:22:06.98#ibcon#enter sib2, iclass 23, count 2 2006.285.10:22:06.98#ibcon#flushed, iclass 23, count 2 2006.285.10:22:06.98#ibcon#about to write, iclass 23, count 2 2006.285.10:22:06.98#ibcon#wrote, iclass 23, count 2 2006.285.10:22:06.98#ibcon#about to read 3, iclass 23, count 2 2006.285.10:22:07.00#ibcon#read 3, iclass 23, count 2 2006.285.10:22:07.00#ibcon#about to read 4, iclass 23, count 2 2006.285.10:22:07.00#ibcon#read 4, iclass 23, count 2 2006.285.10:22:07.00#ibcon#about to read 5, iclass 23, count 2 2006.285.10:22:07.00#ibcon#read 5, iclass 23, count 2 2006.285.10:22:07.00#ibcon#about to read 6, iclass 23, count 2 2006.285.10:22:07.00#ibcon#read 6, iclass 23, count 2 2006.285.10:22:07.00#ibcon#end of sib2, iclass 23, count 2 2006.285.10:22:07.00#ibcon#*mode == 0, iclass 23, count 2 2006.285.10:22:07.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.10:22:07.00#ibcon#[25=AT05-03\r\n] 2006.285.10:22:07.00#ibcon#*before write, iclass 23, count 2 2006.285.10:22:07.00#ibcon#enter sib2, iclass 23, count 2 2006.285.10:22:07.00#ibcon#flushed, iclass 23, count 2 2006.285.10:22:07.00#ibcon#about to write, iclass 23, count 2 2006.285.10:22:07.00#ibcon#wrote, iclass 23, count 2 2006.285.10:22:07.00#ibcon#about to read 3, iclass 23, count 2 2006.285.10:22:07.03#ibcon#read 3, iclass 23, count 2 2006.285.10:22:07.03#ibcon#about to read 4, iclass 23, count 2 2006.285.10:22:07.03#ibcon#read 4, iclass 23, count 2 2006.285.10:22:07.03#ibcon#about to read 5, iclass 23, count 2 2006.285.10:22:07.03#ibcon#read 5, iclass 23, count 2 2006.285.10:22:07.03#ibcon#about to read 6, iclass 23, count 2 2006.285.10:22:07.03#ibcon#read 6, iclass 23, count 2 2006.285.10:22:07.03#ibcon#end of sib2, iclass 23, count 2 2006.285.10:22:07.03#ibcon#*after write, iclass 23, count 2 2006.285.10:22:07.03#ibcon#*before return 0, iclass 23, count 2 2006.285.10:22:07.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:22:07.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:22:07.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.10:22:07.03#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:07.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:22:07.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:22:07.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:22:07.15#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:22:07.15#ibcon#first serial, iclass 23, count 0 2006.285.10:22:07.15#ibcon#enter sib2, iclass 23, count 0 2006.285.10:22:07.15#ibcon#flushed, iclass 23, count 0 2006.285.10:22:07.15#ibcon#about to write, iclass 23, count 0 2006.285.10:22:07.15#ibcon#wrote, iclass 23, count 0 2006.285.10:22:07.15#ibcon#about to read 3, iclass 23, count 0 2006.285.10:22:07.17#ibcon#read 3, iclass 23, count 0 2006.285.10:22:07.17#ibcon#about to read 4, iclass 23, count 0 2006.285.10:22:07.17#ibcon#read 4, iclass 23, count 0 2006.285.10:22:07.17#ibcon#about to read 5, iclass 23, count 0 2006.285.10:22:07.17#ibcon#read 5, iclass 23, count 0 2006.285.10:22:07.17#ibcon#about to read 6, iclass 23, count 0 2006.285.10:22:07.17#ibcon#read 6, iclass 23, count 0 2006.285.10:22:07.17#ibcon#end of sib2, iclass 23, count 0 2006.285.10:22:07.17#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:22:07.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:22:07.17#ibcon#[25=USB\r\n] 2006.285.10:22:07.17#ibcon#*before write, iclass 23, count 0 2006.285.10:22:07.17#ibcon#enter sib2, iclass 23, count 0 2006.285.10:22:07.17#ibcon#flushed, iclass 23, count 0 2006.285.10:22:07.17#ibcon#about to write, iclass 23, count 0 2006.285.10:22:07.17#ibcon#wrote, iclass 23, count 0 2006.285.10:22:07.17#ibcon#about to read 3, iclass 23, count 0 2006.285.10:22:07.20#ibcon#read 3, iclass 23, count 0 2006.285.10:22:07.20#ibcon#about to read 4, iclass 23, count 0 2006.285.10:22:07.20#ibcon#read 4, iclass 23, count 0 2006.285.10:22:07.20#ibcon#about to read 5, iclass 23, count 0 2006.285.10:22:07.20#ibcon#read 5, iclass 23, count 0 2006.285.10:22:07.20#ibcon#about to read 6, iclass 23, count 0 2006.285.10:22:07.20#ibcon#read 6, iclass 23, count 0 2006.285.10:22:07.20#ibcon#end of sib2, iclass 23, count 0 2006.285.10:22:07.20#ibcon#*after write, iclass 23, count 0 2006.285.10:22:07.20#ibcon#*before return 0, iclass 23, count 0 2006.285.10:22:07.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:22:07.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:22:07.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:22:07.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:22:07.20$vck44/valo=6,814.99 2006.285.10:22:07.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.10:22:07.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.10:22:07.20#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:07.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:22:07.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:22:07.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:22:07.20#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:22:07.20#ibcon#first serial, iclass 25, count 0 2006.285.10:22:07.20#ibcon#enter sib2, iclass 25, count 0 2006.285.10:22:07.20#ibcon#flushed, iclass 25, count 0 2006.285.10:22:07.20#ibcon#about to write, iclass 25, count 0 2006.285.10:22:07.20#ibcon#wrote, iclass 25, count 0 2006.285.10:22:07.20#ibcon#about to read 3, iclass 25, count 0 2006.285.10:22:07.22#ibcon#read 3, iclass 25, count 0 2006.285.10:22:07.22#ibcon#about to read 4, iclass 25, count 0 2006.285.10:22:07.22#ibcon#read 4, iclass 25, count 0 2006.285.10:22:07.22#ibcon#about to read 5, iclass 25, count 0 2006.285.10:22:07.22#ibcon#read 5, iclass 25, count 0 2006.285.10:22:07.22#ibcon#about to read 6, iclass 25, count 0 2006.285.10:22:07.22#ibcon#read 6, iclass 25, count 0 2006.285.10:22:07.22#ibcon#end of sib2, iclass 25, count 0 2006.285.10:22:07.22#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:22:07.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:22:07.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:22:07.22#ibcon#*before write, iclass 25, count 0 2006.285.10:22:07.22#ibcon#enter sib2, iclass 25, count 0 2006.285.10:22:07.22#ibcon#flushed, iclass 25, count 0 2006.285.10:22:07.22#ibcon#about to write, iclass 25, count 0 2006.285.10:22:07.22#ibcon#wrote, iclass 25, count 0 2006.285.10:22:07.22#ibcon#about to read 3, iclass 25, count 0 2006.285.10:22:07.26#ibcon#read 3, iclass 25, count 0 2006.285.10:22:07.26#ibcon#about to read 4, iclass 25, count 0 2006.285.10:22:07.26#ibcon#read 4, iclass 25, count 0 2006.285.10:22:07.26#ibcon#about to read 5, iclass 25, count 0 2006.285.10:22:07.26#ibcon#read 5, iclass 25, count 0 2006.285.10:22:07.26#ibcon#about to read 6, iclass 25, count 0 2006.285.10:22:07.26#ibcon#read 6, iclass 25, count 0 2006.285.10:22:07.26#ibcon#end of sib2, iclass 25, count 0 2006.285.10:22:07.26#ibcon#*after write, iclass 25, count 0 2006.285.10:22:07.26#ibcon#*before return 0, iclass 25, count 0 2006.285.10:22:07.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:22:07.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:22:07.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:22:07.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:22:07.26$vck44/va=6,4 2006.285.10:22:07.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.10:22:07.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.10:22:07.26#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:07.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:22:07.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:22:07.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:22:07.32#ibcon#enter wrdev, iclass 27, count 2 2006.285.10:22:07.32#ibcon#first serial, iclass 27, count 2 2006.285.10:22:07.32#ibcon#enter sib2, iclass 27, count 2 2006.285.10:22:07.32#ibcon#flushed, iclass 27, count 2 2006.285.10:22:07.32#ibcon#about to write, iclass 27, count 2 2006.285.10:22:07.32#ibcon#wrote, iclass 27, count 2 2006.285.10:22:07.32#ibcon#about to read 3, iclass 27, count 2 2006.285.10:22:07.34#ibcon#read 3, iclass 27, count 2 2006.285.10:22:07.34#ibcon#about to read 4, iclass 27, count 2 2006.285.10:22:07.34#ibcon#read 4, iclass 27, count 2 2006.285.10:22:07.34#ibcon#about to read 5, iclass 27, count 2 2006.285.10:22:07.34#ibcon#read 5, iclass 27, count 2 2006.285.10:22:07.34#ibcon#about to read 6, iclass 27, count 2 2006.285.10:22:07.34#ibcon#read 6, iclass 27, count 2 2006.285.10:22:07.34#ibcon#end of sib2, iclass 27, count 2 2006.285.10:22:07.34#ibcon#*mode == 0, iclass 27, count 2 2006.285.10:22:07.34#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.10:22:07.34#ibcon#[25=AT06-04\r\n] 2006.285.10:22:07.34#ibcon#*before write, iclass 27, count 2 2006.285.10:22:07.34#ibcon#enter sib2, iclass 27, count 2 2006.285.10:22:07.34#ibcon#flushed, iclass 27, count 2 2006.285.10:22:07.34#ibcon#about to write, iclass 27, count 2 2006.285.10:22:07.34#ibcon#wrote, iclass 27, count 2 2006.285.10:22:07.34#ibcon#about to read 3, iclass 27, count 2 2006.285.10:22:07.37#ibcon#read 3, iclass 27, count 2 2006.285.10:22:07.37#ibcon#about to read 4, iclass 27, count 2 2006.285.10:22:07.37#ibcon#read 4, iclass 27, count 2 2006.285.10:22:07.37#ibcon#about to read 5, iclass 27, count 2 2006.285.10:22:07.37#ibcon#read 5, iclass 27, count 2 2006.285.10:22:07.37#ibcon#about to read 6, iclass 27, count 2 2006.285.10:22:07.37#ibcon#read 6, iclass 27, count 2 2006.285.10:22:07.37#ibcon#end of sib2, iclass 27, count 2 2006.285.10:22:07.37#ibcon#*after write, iclass 27, count 2 2006.285.10:22:07.37#ibcon#*before return 0, iclass 27, count 2 2006.285.10:22:07.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:22:07.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:22:07.37#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.10:22:07.37#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:07.37#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:22:07.49#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:22:07.49#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:22:07.49#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:22:07.49#ibcon#first serial, iclass 27, count 0 2006.285.10:22:07.49#ibcon#enter sib2, iclass 27, count 0 2006.285.10:22:07.49#ibcon#flushed, iclass 27, count 0 2006.285.10:22:07.49#ibcon#about to write, iclass 27, count 0 2006.285.10:22:07.49#ibcon#wrote, iclass 27, count 0 2006.285.10:22:07.49#ibcon#about to read 3, iclass 27, count 0 2006.285.10:22:07.51#ibcon#read 3, iclass 27, count 0 2006.285.10:22:07.51#ibcon#about to read 4, iclass 27, count 0 2006.285.10:22:07.51#ibcon#read 4, iclass 27, count 0 2006.285.10:22:07.51#ibcon#about to read 5, iclass 27, count 0 2006.285.10:22:07.51#ibcon#read 5, iclass 27, count 0 2006.285.10:22:07.51#ibcon#about to read 6, iclass 27, count 0 2006.285.10:22:07.51#ibcon#read 6, iclass 27, count 0 2006.285.10:22:07.51#ibcon#end of sib2, iclass 27, count 0 2006.285.10:22:07.51#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:22:07.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:22:07.51#ibcon#[25=USB\r\n] 2006.285.10:22:07.51#ibcon#*before write, iclass 27, count 0 2006.285.10:22:07.51#ibcon#enter sib2, iclass 27, count 0 2006.285.10:22:07.51#ibcon#flushed, iclass 27, count 0 2006.285.10:22:07.51#ibcon#about to write, iclass 27, count 0 2006.285.10:22:07.51#ibcon#wrote, iclass 27, count 0 2006.285.10:22:07.51#ibcon#about to read 3, iclass 27, count 0 2006.285.10:22:07.54#ibcon#read 3, iclass 27, count 0 2006.285.10:22:07.54#ibcon#about to read 4, iclass 27, count 0 2006.285.10:22:07.54#ibcon#read 4, iclass 27, count 0 2006.285.10:22:07.54#ibcon#about to read 5, iclass 27, count 0 2006.285.10:22:07.54#ibcon#read 5, iclass 27, count 0 2006.285.10:22:07.54#ibcon#about to read 6, iclass 27, count 0 2006.285.10:22:07.54#ibcon#read 6, iclass 27, count 0 2006.285.10:22:07.54#ibcon#end of sib2, iclass 27, count 0 2006.285.10:22:07.54#ibcon#*after write, iclass 27, count 0 2006.285.10:22:07.54#ibcon#*before return 0, iclass 27, count 0 2006.285.10:22:07.54#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:22:07.54#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:22:07.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:22:07.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:22:07.54$vck44/valo=7,864.99 2006.285.10:22:07.54#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.10:22:07.54#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.10:22:07.54#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:07.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:22:07.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:22:07.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:22:07.54#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:22:07.54#ibcon#first serial, iclass 29, count 0 2006.285.10:22:07.54#ibcon#enter sib2, iclass 29, count 0 2006.285.10:22:07.54#ibcon#flushed, iclass 29, count 0 2006.285.10:22:07.54#ibcon#about to write, iclass 29, count 0 2006.285.10:22:07.54#ibcon#wrote, iclass 29, count 0 2006.285.10:22:07.54#ibcon#about to read 3, iclass 29, count 0 2006.285.10:22:07.56#ibcon#read 3, iclass 29, count 0 2006.285.10:22:07.56#ibcon#about to read 4, iclass 29, count 0 2006.285.10:22:07.56#ibcon#read 4, iclass 29, count 0 2006.285.10:22:07.56#ibcon#about to read 5, iclass 29, count 0 2006.285.10:22:07.56#ibcon#read 5, iclass 29, count 0 2006.285.10:22:07.56#ibcon#about to read 6, iclass 29, count 0 2006.285.10:22:07.56#ibcon#read 6, iclass 29, count 0 2006.285.10:22:07.56#ibcon#end of sib2, iclass 29, count 0 2006.285.10:22:07.56#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:22:07.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:22:07.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:22:07.56#ibcon#*before write, iclass 29, count 0 2006.285.10:22:07.56#ibcon#enter sib2, iclass 29, count 0 2006.285.10:22:07.56#ibcon#flushed, iclass 29, count 0 2006.285.10:22:07.56#ibcon#about to write, iclass 29, count 0 2006.285.10:22:07.56#ibcon#wrote, iclass 29, count 0 2006.285.10:22:07.56#ibcon#about to read 3, iclass 29, count 0 2006.285.10:22:07.60#ibcon#read 3, iclass 29, count 0 2006.285.10:22:07.60#ibcon#about to read 4, iclass 29, count 0 2006.285.10:22:07.60#ibcon#read 4, iclass 29, count 0 2006.285.10:22:07.60#ibcon#about to read 5, iclass 29, count 0 2006.285.10:22:07.60#ibcon#read 5, iclass 29, count 0 2006.285.10:22:07.60#ibcon#about to read 6, iclass 29, count 0 2006.285.10:22:07.60#ibcon#read 6, iclass 29, count 0 2006.285.10:22:07.60#ibcon#end of sib2, iclass 29, count 0 2006.285.10:22:07.60#ibcon#*after write, iclass 29, count 0 2006.285.10:22:07.60#ibcon#*before return 0, iclass 29, count 0 2006.285.10:22:07.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:22:07.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:22:07.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:22:07.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:22:07.60$vck44/va=7,4 2006.285.10:22:07.60#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.10:22:07.60#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.10:22:07.60#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:07.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:22:07.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:22:07.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:22:07.66#ibcon#enter wrdev, iclass 31, count 2 2006.285.10:22:07.66#ibcon#first serial, iclass 31, count 2 2006.285.10:22:07.66#ibcon#enter sib2, iclass 31, count 2 2006.285.10:22:07.66#ibcon#flushed, iclass 31, count 2 2006.285.10:22:07.66#ibcon#about to write, iclass 31, count 2 2006.285.10:22:07.66#ibcon#wrote, iclass 31, count 2 2006.285.10:22:07.66#ibcon#about to read 3, iclass 31, count 2 2006.285.10:22:07.68#ibcon#read 3, iclass 31, count 2 2006.285.10:22:07.68#ibcon#about to read 4, iclass 31, count 2 2006.285.10:22:07.68#ibcon#read 4, iclass 31, count 2 2006.285.10:22:07.68#ibcon#about to read 5, iclass 31, count 2 2006.285.10:22:07.68#ibcon#read 5, iclass 31, count 2 2006.285.10:22:07.68#ibcon#about to read 6, iclass 31, count 2 2006.285.10:22:07.68#ibcon#read 6, iclass 31, count 2 2006.285.10:22:07.68#ibcon#end of sib2, iclass 31, count 2 2006.285.10:22:07.68#ibcon#*mode == 0, iclass 31, count 2 2006.285.10:22:07.68#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.10:22:07.68#ibcon#[25=AT07-04\r\n] 2006.285.10:22:07.68#ibcon#*before write, iclass 31, count 2 2006.285.10:22:07.68#ibcon#enter sib2, iclass 31, count 2 2006.285.10:22:07.68#ibcon#flushed, iclass 31, count 2 2006.285.10:22:07.68#ibcon#about to write, iclass 31, count 2 2006.285.10:22:07.68#ibcon#wrote, iclass 31, count 2 2006.285.10:22:07.68#ibcon#about to read 3, iclass 31, count 2 2006.285.10:22:07.71#ibcon#read 3, iclass 31, count 2 2006.285.10:22:07.71#ibcon#about to read 4, iclass 31, count 2 2006.285.10:22:07.71#ibcon#read 4, iclass 31, count 2 2006.285.10:22:07.71#ibcon#about to read 5, iclass 31, count 2 2006.285.10:22:07.71#ibcon#read 5, iclass 31, count 2 2006.285.10:22:07.71#ibcon#about to read 6, iclass 31, count 2 2006.285.10:22:07.71#ibcon#read 6, iclass 31, count 2 2006.285.10:22:07.71#ibcon#end of sib2, iclass 31, count 2 2006.285.10:22:07.71#ibcon#*after write, iclass 31, count 2 2006.285.10:22:07.71#ibcon#*before return 0, iclass 31, count 2 2006.285.10:22:07.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:22:07.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:22:07.71#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.10:22:07.71#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:07.71#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:22:07.83#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:22:07.83#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:22:07.83#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:22:07.83#ibcon#first serial, iclass 31, count 0 2006.285.10:22:07.83#ibcon#enter sib2, iclass 31, count 0 2006.285.10:22:07.83#ibcon#flushed, iclass 31, count 0 2006.285.10:22:07.83#ibcon#about to write, iclass 31, count 0 2006.285.10:22:07.83#ibcon#wrote, iclass 31, count 0 2006.285.10:22:07.83#ibcon#about to read 3, iclass 31, count 0 2006.285.10:22:07.85#ibcon#read 3, iclass 31, count 0 2006.285.10:22:07.85#ibcon#about to read 4, iclass 31, count 0 2006.285.10:22:07.85#ibcon#read 4, iclass 31, count 0 2006.285.10:22:07.85#ibcon#about to read 5, iclass 31, count 0 2006.285.10:22:07.85#ibcon#read 5, iclass 31, count 0 2006.285.10:22:07.85#ibcon#about to read 6, iclass 31, count 0 2006.285.10:22:07.85#ibcon#read 6, iclass 31, count 0 2006.285.10:22:07.85#ibcon#end of sib2, iclass 31, count 0 2006.285.10:22:07.85#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:22:07.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:22:07.85#ibcon#[25=USB\r\n] 2006.285.10:22:07.85#ibcon#*before write, iclass 31, count 0 2006.285.10:22:07.85#ibcon#enter sib2, iclass 31, count 0 2006.285.10:22:07.85#ibcon#flushed, iclass 31, count 0 2006.285.10:22:07.85#ibcon#about to write, iclass 31, count 0 2006.285.10:22:07.85#ibcon#wrote, iclass 31, count 0 2006.285.10:22:07.85#ibcon#about to read 3, iclass 31, count 0 2006.285.10:22:07.88#ibcon#read 3, iclass 31, count 0 2006.285.10:22:07.88#ibcon#about to read 4, iclass 31, count 0 2006.285.10:22:07.88#ibcon#read 4, iclass 31, count 0 2006.285.10:22:07.88#ibcon#about to read 5, iclass 31, count 0 2006.285.10:22:07.88#ibcon#read 5, iclass 31, count 0 2006.285.10:22:07.88#ibcon#about to read 6, iclass 31, count 0 2006.285.10:22:07.88#ibcon#read 6, iclass 31, count 0 2006.285.10:22:07.88#ibcon#end of sib2, iclass 31, count 0 2006.285.10:22:07.88#ibcon#*after write, iclass 31, count 0 2006.285.10:22:07.88#ibcon#*before return 0, iclass 31, count 0 2006.285.10:22:07.88#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:22:07.88#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:22:07.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:22:07.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:22:07.88$vck44/valo=8,884.99 2006.285.10:22:07.88#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.10:22:07.88#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.10:22:07.88#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:07.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:22:07.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:22:07.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:22:07.88#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:22:07.88#ibcon#first serial, iclass 33, count 0 2006.285.10:22:07.88#ibcon#enter sib2, iclass 33, count 0 2006.285.10:22:07.88#ibcon#flushed, iclass 33, count 0 2006.285.10:22:07.88#ibcon#about to write, iclass 33, count 0 2006.285.10:22:07.88#ibcon#wrote, iclass 33, count 0 2006.285.10:22:07.88#ibcon#about to read 3, iclass 33, count 0 2006.285.10:22:07.90#ibcon#read 3, iclass 33, count 0 2006.285.10:22:07.90#ibcon#about to read 4, iclass 33, count 0 2006.285.10:22:07.90#ibcon#read 4, iclass 33, count 0 2006.285.10:22:07.90#ibcon#about to read 5, iclass 33, count 0 2006.285.10:22:07.90#ibcon#read 5, iclass 33, count 0 2006.285.10:22:07.90#ibcon#about to read 6, iclass 33, count 0 2006.285.10:22:07.90#ibcon#read 6, iclass 33, count 0 2006.285.10:22:07.90#ibcon#end of sib2, iclass 33, count 0 2006.285.10:22:07.90#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:22:07.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:22:07.90#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:22:07.90#ibcon#*before write, iclass 33, count 0 2006.285.10:22:07.90#ibcon#enter sib2, iclass 33, count 0 2006.285.10:22:07.90#ibcon#flushed, iclass 33, count 0 2006.285.10:22:07.90#ibcon#about to write, iclass 33, count 0 2006.285.10:22:07.90#ibcon#wrote, iclass 33, count 0 2006.285.10:22:07.90#ibcon#about to read 3, iclass 33, count 0 2006.285.10:22:07.94#ibcon#read 3, iclass 33, count 0 2006.285.10:22:07.94#ibcon#about to read 4, iclass 33, count 0 2006.285.10:22:07.94#ibcon#read 4, iclass 33, count 0 2006.285.10:22:07.94#ibcon#about to read 5, iclass 33, count 0 2006.285.10:22:07.94#ibcon#read 5, iclass 33, count 0 2006.285.10:22:07.94#ibcon#about to read 6, iclass 33, count 0 2006.285.10:22:07.94#ibcon#read 6, iclass 33, count 0 2006.285.10:22:07.94#ibcon#end of sib2, iclass 33, count 0 2006.285.10:22:07.94#ibcon#*after write, iclass 33, count 0 2006.285.10:22:07.94#ibcon#*before return 0, iclass 33, count 0 2006.285.10:22:07.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:22:07.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:22:07.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:22:07.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:22:07.94$vck44/va=8,3 2006.285.10:22:07.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.10:22:07.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.10:22:07.94#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:07.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:22:08.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:22:08.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:22:08.00#ibcon#enter wrdev, iclass 35, count 2 2006.285.10:22:08.00#ibcon#first serial, iclass 35, count 2 2006.285.10:22:08.00#ibcon#enter sib2, iclass 35, count 2 2006.285.10:22:08.00#ibcon#flushed, iclass 35, count 2 2006.285.10:22:08.00#ibcon#about to write, iclass 35, count 2 2006.285.10:22:08.00#ibcon#wrote, iclass 35, count 2 2006.285.10:22:08.00#ibcon#about to read 3, iclass 35, count 2 2006.285.10:22:08.02#ibcon#read 3, iclass 35, count 2 2006.285.10:22:08.02#ibcon#about to read 4, iclass 35, count 2 2006.285.10:22:08.02#ibcon#read 4, iclass 35, count 2 2006.285.10:22:08.02#ibcon#about to read 5, iclass 35, count 2 2006.285.10:22:08.02#ibcon#read 5, iclass 35, count 2 2006.285.10:22:08.02#ibcon#about to read 6, iclass 35, count 2 2006.285.10:22:08.02#ibcon#read 6, iclass 35, count 2 2006.285.10:22:08.02#ibcon#end of sib2, iclass 35, count 2 2006.285.10:22:08.02#ibcon#*mode == 0, iclass 35, count 2 2006.285.10:22:08.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.10:22:08.02#ibcon#[25=AT08-03\r\n] 2006.285.10:22:08.02#ibcon#*before write, iclass 35, count 2 2006.285.10:22:08.02#ibcon#enter sib2, iclass 35, count 2 2006.285.10:22:08.02#ibcon#flushed, iclass 35, count 2 2006.285.10:22:08.02#ibcon#about to write, iclass 35, count 2 2006.285.10:22:08.02#ibcon#wrote, iclass 35, count 2 2006.285.10:22:08.02#ibcon#about to read 3, iclass 35, count 2 2006.285.10:22:08.05#ibcon#read 3, iclass 35, count 2 2006.285.10:22:08.05#ibcon#about to read 4, iclass 35, count 2 2006.285.10:22:08.05#ibcon#read 4, iclass 35, count 2 2006.285.10:22:08.05#ibcon#about to read 5, iclass 35, count 2 2006.285.10:22:08.05#ibcon#read 5, iclass 35, count 2 2006.285.10:22:08.05#ibcon#about to read 6, iclass 35, count 2 2006.285.10:22:08.05#ibcon#read 6, iclass 35, count 2 2006.285.10:22:08.05#ibcon#end of sib2, iclass 35, count 2 2006.285.10:22:08.05#ibcon#*after write, iclass 35, count 2 2006.285.10:22:08.05#ibcon#*before return 0, iclass 35, count 2 2006.285.10:22:08.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:22:08.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.10:22:08.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.10:22:08.05#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:08.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:22:08.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:22:08.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:22:08.17#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:22:08.17#ibcon#first serial, iclass 35, count 0 2006.285.10:22:08.17#ibcon#enter sib2, iclass 35, count 0 2006.285.10:22:08.17#ibcon#flushed, iclass 35, count 0 2006.285.10:22:08.17#ibcon#about to write, iclass 35, count 0 2006.285.10:22:08.17#ibcon#wrote, iclass 35, count 0 2006.285.10:22:08.17#ibcon#about to read 3, iclass 35, count 0 2006.285.10:22:08.19#ibcon#read 3, iclass 35, count 0 2006.285.10:22:08.19#ibcon#about to read 4, iclass 35, count 0 2006.285.10:22:08.19#ibcon#read 4, iclass 35, count 0 2006.285.10:22:08.19#ibcon#about to read 5, iclass 35, count 0 2006.285.10:22:08.19#ibcon#read 5, iclass 35, count 0 2006.285.10:22:08.19#ibcon#about to read 6, iclass 35, count 0 2006.285.10:22:08.19#ibcon#read 6, iclass 35, count 0 2006.285.10:22:08.19#ibcon#end of sib2, iclass 35, count 0 2006.285.10:22:08.19#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:22:08.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:22:08.19#ibcon#[25=USB\r\n] 2006.285.10:22:08.19#ibcon#*before write, iclass 35, count 0 2006.285.10:22:08.19#ibcon#enter sib2, iclass 35, count 0 2006.285.10:22:08.19#ibcon#flushed, iclass 35, count 0 2006.285.10:22:08.19#ibcon#about to write, iclass 35, count 0 2006.285.10:22:08.19#ibcon#wrote, iclass 35, count 0 2006.285.10:22:08.19#ibcon#about to read 3, iclass 35, count 0 2006.285.10:22:08.22#ibcon#read 3, iclass 35, count 0 2006.285.10:22:08.22#ibcon#about to read 4, iclass 35, count 0 2006.285.10:22:08.22#ibcon#read 4, iclass 35, count 0 2006.285.10:22:08.22#ibcon#about to read 5, iclass 35, count 0 2006.285.10:22:08.22#ibcon#read 5, iclass 35, count 0 2006.285.10:22:08.22#ibcon#about to read 6, iclass 35, count 0 2006.285.10:22:08.22#ibcon#read 6, iclass 35, count 0 2006.285.10:22:08.22#ibcon#end of sib2, iclass 35, count 0 2006.285.10:22:08.22#ibcon#*after write, iclass 35, count 0 2006.285.10:22:08.22#ibcon#*before return 0, iclass 35, count 0 2006.285.10:22:08.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:22:08.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.10:22:08.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:22:08.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:22:08.22$vck44/vblo=1,629.99 2006.285.10:22:08.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.10:22:08.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.10:22:08.22#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:08.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:22:08.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:22:08.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:22:08.22#ibcon#enter wrdev, iclass 37, count 0 2006.285.10:22:08.22#ibcon#first serial, iclass 37, count 0 2006.285.10:22:08.22#ibcon#enter sib2, iclass 37, count 0 2006.285.10:22:08.22#ibcon#flushed, iclass 37, count 0 2006.285.10:22:08.22#ibcon#about to write, iclass 37, count 0 2006.285.10:22:08.22#ibcon#wrote, iclass 37, count 0 2006.285.10:22:08.22#ibcon#about to read 3, iclass 37, count 0 2006.285.10:22:08.24#ibcon#read 3, iclass 37, count 0 2006.285.10:22:08.24#ibcon#about to read 4, iclass 37, count 0 2006.285.10:22:08.24#ibcon#read 4, iclass 37, count 0 2006.285.10:22:08.24#ibcon#about to read 5, iclass 37, count 0 2006.285.10:22:08.24#ibcon#read 5, iclass 37, count 0 2006.285.10:22:08.24#ibcon#about to read 6, iclass 37, count 0 2006.285.10:22:08.24#ibcon#read 6, iclass 37, count 0 2006.285.10:22:08.24#ibcon#end of sib2, iclass 37, count 0 2006.285.10:22:08.24#ibcon#*mode == 0, iclass 37, count 0 2006.285.10:22:08.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.10:22:08.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:22:08.24#ibcon#*before write, iclass 37, count 0 2006.285.10:22:08.24#ibcon#enter sib2, iclass 37, count 0 2006.285.10:22:08.24#ibcon#flushed, iclass 37, count 0 2006.285.10:22:08.24#ibcon#about to write, iclass 37, count 0 2006.285.10:22:08.24#ibcon#wrote, iclass 37, count 0 2006.285.10:22:08.24#ibcon#about to read 3, iclass 37, count 0 2006.285.10:22:08.28#ibcon#read 3, iclass 37, count 0 2006.285.10:22:08.28#ibcon#about to read 4, iclass 37, count 0 2006.285.10:22:08.28#ibcon#read 4, iclass 37, count 0 2006.285.10:22:08.28#ibcon#about to read 5, iclass 37, count 0 2006.285.10:22:08.28#ibcon#read 5, iclass 37, count 0 2006.285.10:22:08.28#ibcon#about to read 6, iclass 37, count 0 2006.285.10:22:08.28#ibcon#read 6, iclass 37, count 0 2006.285.10:22:08.28#ibcon#end of sib2, iclass 37, count 0 2006.285.10:22:08.28#ibcon#*after write, iclass 37, count 0 2006.285.10:22:08.28#ibcon#*before return 0, iclass 37, count 0 2006.285.10:22:08.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:22:08.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:22:08.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.10:22:08.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.10:22:08.28$vck44/vb=1,4 2006.285.10:22:08.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.10:22:08.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.10:22:08.28#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:08.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:22:08.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:22:08.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:22:08.28#ibcon#enter wrdev, iclass 39, count 2 2006.285.10:22:08.28#ibcon#first serial, iclass 39, count 2 2006.285.10:22:08.28#ibcon#enter sib2, iclass 39, count 2 2006.285.10:22:08.28#ibcon#flushed, iclass 39, count 2 2006.285.10:22:08.28#ibcon#about to write, iclass 39, count 2 2006.285.10:22:08.28#ibcon#wrote, iclass 39, count 2 2006.285.10:22:08.28#ibcon#about to read 3, iclass 39, count 2 2006.285.10:22:08.30#ibcon#read 3, iclass 39, count 2 2006.285.10:22:08.30#ibcon#about to read 4, iclass 39, count 2 2006.285.10:22:08.30#ibcon#read 4, iclass 39, count 2 2006.285.10:22:08.30#ibcon#about to read 5, iclass 39, count 2 2006.285.10:22:08.30#ibcon#read 5, iclass 39, count 2 2006.285.10:22:08.30#ibcon#about to read 6, iclass 39, count 2 2006.285.10:22:08.30#ibcon#read 6, iclass 39, count 2 2006.285.10:22:08.30#ibcon#end of sib2, iclass 39, count 2 2006.285.10:22:08.30#ibcon#*mode == 0, iclass 39, count 2 2006.285.10:22:08.30#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.10:22:08.30#ibcon#[27=AT01-04\r\n] 2006.285.10:22:08.30#ibcon#*before write, iclass 39, count 2 2006.285.10:22:08.30#ibcon#enter sib2, iclass 39, count 2 2006.285.10:22:08.30#ibcon#flushed, iclass 39, count 2 2006.285.10:22:08.30#ibcon#about to write, iclass 39, count 2 2006.285.10:22:08.30#ibcon#wrote, iclass 39, count 2 2006.285.10:22:08.30#ibcon#about to read 3, iclass 39, count 2 2006.285.10:22:08.33#ibcon#read 3, iclass 39, count 2 2006.285.10:22:08.33#ibcon#about to read 4, iclass 39, count 2 2006.285.10:22:08.33#ibcon#read 4, iclass 39, count 2 2006.285.10:22:08.33#ibcon#about to read 5, iclass 39, count 2 2006.285.10:22:08.33#ibcon#read 5, iclass 39, count 2 2006.285.10:22:08.33#ibcon#about to read 6, iclass 39, count 2 2006.285.10:22:08.33#ibcon#read 6, iclass 39, count 2 2006.285.10:22:08.33#ibcon#end of sib2, iclass 39, count 2 2006.285.10:22:08.33#ibcon#*after write, iclass 39, count 2 2006.285.10:22:08.33#ibcon#*before return 0, iclass 39, count 2 2006.285.10:22:08.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:22:08.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:22:08.33#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.10:22:08.33#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:08.33#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:22:08.45#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:22:08.45#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:22:08.45#ibcon#enter wrdev, iclass 39, count 0 2006.285.10:22:08.45#ibcon#first serial, iclass 39, count 0 2006.285.10:22:08.45#ibcon#enter sib2, iclass 39, count 0 2006.285.10:22:08.45#ibcon#flushed, iclass 39, count 0 2006.285.10:22:08.45#ibcon#about to write, iclass 39, count 0 2006.285.10:22:08.45#ibcon#wrote, iclass 39, count 0 2006.285.10:22:08.45#ibcon#about to read 3, iclass 39, count 0 2006.285.10:22:08.47#ibcon#read 3, iclass 39, count 0 2006.285.10:22:08.47#ibcon#about to read 4, iclass 39, count 0 2006.285.10:22:08.47#ibcon#read 4, iclass 39, count 0 2006.285.10:22:08.47#ibcon#about to read 5, iclass 39, count 0 2006.285.10:22:08.47#ibcon#read 5, iclass 39, count 0 2006.285.10:22:08.47#ibcon#about to read 6, iclass 39, count 0 2006.285.10:22:08.47#ibcon#read 6, iclass 39, count 0 2006.285.10:22:08.47#ibcon#end of sib2, iclass 39, count 0 2006.285.10:22:08.47#ibcon#*mode == 0, iclass 39, count 0 2006.285.10:22:08.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.10:22:08.47#ibcon#[27=USB\r\n] 2006.285.10:22:08.47#ibcon#*before write, iclass 39, count 0 2006.285.10:22:08.47#ibcon#enter sib2, iclass 39, count 0 2006.285.10:22:08.47#ibcon#flushed, iclass 39, count 0 2006.285.10:22:08.47#ibcon#about to write, iclass 39, count 0 2006.285.10:22:08.47#ibcon#wrote, iclass 39, count 0 2006.285.10:22:08.47#ibcon#about to read 3, iclass 39, count 0 2006.285.10:22:08.50#ibcon#read 3, iclass 39, count 0 2006.285.10:22:08.50#ibcon#about to read 4, iclass 39, count 0 2006.285.10:22:08.50#ibcon#read 4, iclass 39, count 0 2006.285.10:22:08.50#ibcon#about to read 5, iclass 39, count 0 2006.285.10:22:08.50#ibcon#read 5, iclass 39, count 0 2006.285.10:22:08.50#ibcon#about to read 6, iclass 39, count 0 2006.285.10:22:08.50#ibcon#read 6, iclass 39, count 0 2006.285.10:22:08.50#ibcon#end of sib2, iclass 39, count 0 2006.285.10:22:08.50#ibcon#*after write, iclass 39, count 0 2006.285.10:22:08.50#ibcon#*before return 0, iclass 39, count 0 2006.285.10:22:08.50#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:22:08.50#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:22:08.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.10:22:08.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.10:22:08.50$vck44/vblo=2,634.99 2006.285.10:22:08.50#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.10:22:08.50#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.10:22:08.50#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:08.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:22:08.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:22:08.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:22:08.50#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:22:08.50#ibcon#first serial, iclass 3, count 0 2006.285.10:22:08.50#ibcon#enter sib2, iclass 3, count 0 2006.285.10:22:08.50#ibcon#flushed, iclass 3, count 0 2006.285.10:22:08.50#ibcon#about to write, iclass 3, count 0 2006.285.10:22:08.50#ibcon#wrote, iclass 3, count 0 2006.285.10:22:08.50#ibcon#about to read 3, iclass 3, count 0 2006.285.10:22:08.52#ibcon#read 3, iclass 3, count 0 2006.285.10:22:08.52#ibcon#about to read 4, iclass 3, count 0 2006.285.10:22:08.52#ibcon#read 4, iclass 3, count 0 2006.285.10:22:08.52#ibcon#about to read 5, iclass 3, count 0 2006.285.10:22:08.52#ibcon#read 5, iclass 3, count 0 2006.285.10:22:08.52#ibcon#about to read 6, iclass 3, count 0 2006.285.10:22:08.52#ibcon#read 6, iclass 3, count 0 2006.285.10:22:08.52#ibcon#end of sib2, iclass 3, count 0 2006.285.10:22:08.52#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:22:08.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:22:08.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:22:08.52#ibcon#*before write, iclass 3, count 0 2006.285.10:22:08.52#ibcon#enter sib2, iclass 3, count 0 2006.285.10:22:08.52#ibcon#flushed, iclass 3, count 0 2006.285.10:22:08.52#ibcon#about to write, iclass 3, count 0 2006.285.10:22:08.52#ibcon#wrote, iclass 3, count 0 2006.285.10:22:08.52#ibcon#about to read 3, iclass 3, count 0 2006.285.10:22:08.56#ibcon#read 3, iclass 3, count 0 2006.285.10:22:08.56#ibcon#about to read 4, iclass 3, count 0 2006.285.10:22:08.56#ibcon#read 4, iclass 3, count 0 2006.285.10:22:08.56#ibcon#about to read 5, iclass 3, count 0 2006.285.10:22:08.56#ibcon#read 5, iclass 3, count 0 2006.285.10:22:08.56#ibcon#about to read 6, iclass 3, count 0 2006.285.10:22:08.56#ibcon#read 6, iclass 3, count 0 2006.285.10:22:08.56#ibcon#end of sib2, iclass 3, count 0 2006.285.10:22:08.56#ibcon#*after write, iclass 3, count 0 2006.285.10:22:08.56#ibcon#*before return 0, iclass 3, count 0 2006.285.10:22:08.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:22:08.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:22:08.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:22:08.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:22:08.56$vck44/vb=2,5 2006.285.10:22:08.56#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.10:22:08.56#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.10:22:08.56#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:08.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:22:08.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:22:08.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:22:08.62#ibcon#enter wrdev, iclass 5, count 2 2006.285.10:22:08.62#ibcon#first serial, iclass 5, count 2 2006.285.10:22:08.62#ibcon#enter sib2, iclass 5, count 2 2006.285.10:22:08.62#ibcon#flushed, iclass 5, count 2 2006.285.10:22:08.62#ibcon#about to write, iclass 5, count 2 2006.285.10:22:08.62#ibcon#wrote, iclass 5, count 2 2006.285.10:22:08.62#ibcon#about to read 3, iclass 5, count 2 2006.285.10:22:08.64#ibcon#read 3, iclass 5, count 2 2006.285.10:22:08.64#ibcon#about to read 4, iclass 5, count 2 2006.285.10:22:08.64#ibcon#read 4, iclass 5, count 2 2006.285.10:22:08.64#ibcon#about to read 5, iclass 5, count 2 2006.285.10:22:08.64#ibcon#read 5, iclass 5, count 2 2006.285.10:22:08.64#ibcon#about to read 6, iclass 5, count 2 2006.285.10:22:08.64#ibcon#read 6, iclass 5, count 2 2006.285.10:22:08.64#ibcon#end of sib2, iclass 5, count 2 2006.285.10:22:08.64#ibcon#*mode == 0, iclass 5, count 2 2006.285.10:22:08.64#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.10:22:08.64#ibcon#[27=AT02-05\r\n] 2006.285.10:22:08.64#ibcon#*before write, iclass 5, count 2 2006.285.10:22:08.64#ibcon#enter sib2, iclass 5, count 2 2006.285.10:22:08.64#ibcon#flushed, iclass 5, count 2 2006.285.10:22:08.64#ibcon#about to write, iclass 5, count 2 2006.285.10:22:08.64#ibcon#wrote, iclass 5, count 2 2006.285.10:22:08.64#ibcon#about to read 3, iclass 5, count 2 2006.285.10:22:08.67#ibcon#read 3, iclass 5, count 2 2006.285.10:22:08.67#ibcon#about to read 4, iclass 5, count 2 2006.285.10:22:08.67#ibcon#read 4, iclass 5, count 2 2006.285.10:22:08.67#ibcon#about to read 5, iclass 5, count 2 2006.285.10:22:08.67#ibcon#read 5, iclass 5, count 2 2006.285.10:22:08.67#ibcon#about to read 6, iclass 5, count 2 2006.285.10:22:08.67#ibcon#read 6, iclass 5, count 2 2006.285.10:22:08.67#ibcon#end of sib2, iclass 5, count 2 2006.285.10:22:08.67#ibcon#*after write, iclass 5, count 2 2006.285.10:22:08.67#ibcon#*before return 0, iclass 5, count 2 2006.285.10:22:08.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:22:08.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:22:08.67#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.10:22:08.67#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:08.67#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:22:08.79#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:22:08.79#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:22:08.79#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:22:08.79#ibcon#first serial, iclass 5, count 0 2006.285.10:22:08.79#ibcon#enter sib2, iclass 5, count 0 2006.285.10:22:08.79#ibcon#flushed, iclass 5, count 0 2006.285.10:22:08.79#ibcon#about to write, iclass 5, count 0 2006.285.10:22:08.79#ibcon#wrote, iclass 5, count 0 2006.285.10:22:08.79#ibcon#about to read 3, iclass 5, count 0 2006.285.10:22:08.81#ibcon#read 3, iclass 5, count 0 2006.285.10:22:08.81#ibcon#about to read 4, iclass 5, count 0 2006.285.10:22:08.81#ibcon#read 4, iclass 5, count 0 2006.285.10:22:08.81#ibcon#about to read 5, iclass 5, count 0 2006.285.10:22:08.81#ibcon#read 5, iclass 5, count 0 2006.285.10:22:08.81#ibcon#about to read 6, iclass 5, count 0 2006.285.10:22:08.81#ibcon#read 6, iclass 5, count 0 2006.285.10:22:08.81#ibcon#end of sib2, iclass 5, count 0 2006.285.10:22:08.81#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:22:08.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:22:08.81#ibcon#[27=USB\r\n] 2006.285.10:22:08.81#ibcon#*before write, iclass 5, count 0 2006.285.10:22:08.81#ibcon#enter sib2, iclass 5, count 0 2006.285.10:22:08.81#ibcon#flushed, iclass 5, count 0 2006.285.10:22:08.81#ibcon#about to write, iclass 5, count 0 2006.285.10:22:08.81#ibcon#wrote, iclass 5, count 0 2006.285.10:22:08.81#ibcon#about to read 3, iclass 5, count 0 2006.285.10:22:08.84#ibcon#read 3, iclass 5, count 0 2006.285.10:22:08.84#ibcon#about to read 4, iclass 5, count 0 2006.285.10:22:08.84#ibcon#read 4, iclass 5, count 0 2006.285.10:22:08.84#ibcon#about to read 5, iclass 5, count 0 2006.285.10:22:08.84#ibcon#read 5, iclass 5, count 0 2006.285.10:22:08.84#ibcon#about to read 6, iclass 5, count 0 2006.285.10:22:08.84#ibcon#read 6, iclass 5, count 0 2006.285.10:22:08.84#ibcon#end of sib2, iclass 5, count 0 2006.285.10:22:08.84#ibcon#*after write, iclass 5, count 0 2006.285.10:22:08.84#ibcon#*before return 0, iclass 5, count 0 2006.285.10:22:08.84#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:22:08.84#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:22:08.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:22:08.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:22:08.84$vck44/vblo=3,649.99 2006.285.10:22:08.84#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.10:22:08.84#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.10:22:08.84#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:08.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:22:08.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:22:08.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:22:08.84#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:22:08.84#ibcon#first serial, iclass 7, count 0 2006.285.10:22:08.84#ibcon#enter sib2, iclass 7, count 0 2006.285.10:22:08.84#ibcon#flushed, iclass 7, count 0 2006.285.10:22:08.84#ibcon#about to write, iclass 7, count 0 2006.285.10:22:08.84#ibcon#wrote, iclass 7, count 0 2006.285.10:22:08.84#ibcon#about to read 3, iclass 7, count 0 2006.285.10:22:08.86#ibcon#read 3, iclass 7, count 0 2006.285.10:22:08.86#ibcon#about to read 4, iclass 7, count 0 2006.285.10:22:08.86#ibcon#read 4, iclass 7, count 0 2006.285.10:22:08.86#ibcon#about to read 5, iclass 7, count 0 2006.285.10:22:08.86#ibcon#read 5, iclass 7, count 0 2006.285.10:22:08.86#ibcon#about to read 6, iclass 7, count 0 2006.285.10:22:08.86#ibcon#read 6, iclass 7, count 0 2006.285.10:22:08.86#ibcon#end of sib2, iclass 7, count 0 2006.285.10:22:08.86#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:22:08.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:22:08.86#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:22:08.86#ibcon#*before write, iclass 7, count 0 2006.285.10:22:08.86#ibcon#enter sib2, iclass 7, count 0 2006.285.10:22:08.86#ibcon#flushed, iclass 7, count 0 2006.285.10:22:08.86#ibcon#about to write, iclass 7, count 0 2006.285.10:22:08.86#ibcon#wrote, iclass 7, count 0 2006.285.10:22:08.86#ibcon#about to read 3, iclass 7, count 0 2006.285.10:22:08.90#ibcon#read 3, iclass 7, count 0 2006.285.10:22:08.90#ibcon#about to read 4, iclass 7, count 0 2006.285.10:22:08.90#ibcon#read 4, iclass 7, count 0 2006.285.10:22:08.90#ibcon#about to read 5, iclass 7, count 0 2006.285.10:22:08.90#ibcon#read 5, iclass 7, count 0 2006.285.10:22:08.90#ibcon#about to read 6, iclass 7, count 0 2006.285.10:22:08.90#ibcon#read 6, iclass 7, count 0 2006.285.10:22:08.90#ibcon#end of sib2, iclass 7, count 0 2006.285.10:22:08.90#ibcon#*after write, iclass 7, count 0 2006.285.10:22:08.90#ibcon#*before return 0, iclass 7, count 0 2006.285.10:22:08.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:22:08.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:22:08.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:22:08.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:22:08.90$vck44/vb=3,4 2006.285.10:22:08.90#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.10:22:08.90#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.10:22:08.90#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:08.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:22:08.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:22:08.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:22:08.96#ibcon#enter wrdev, iclass 11, count 2 2006.285.10:22:08.96#ibcon#first serial, iclass 11, count 2 2006.285.10:22:08.96#ibcon#enter sib2, iclass 11, count 2 2006.285.10:22:08.96#ibcon#flushed, iclass 11, count 2 2006.285.10:22:08.96#ibcon#about to write, iclass 11, count 2 2006.285.10:22:08.96#ibcon#wrote, iclass 11, count 2 2006.285.10:22:08.96#ibcon#about to read 3, iclass 11, count 2 2006.285.10:22:08.98#ibcon#read 3, iclass 11, count 2 2006.285.10:22:08.98#ibcon#about to read 4, iclass 11, count 2 2006.285.10:22:08.98#ibcon#read 4, iclass 11, count 2 2006.285.10:22:08.98#ibcon#about to read 5, iclass 11, count 2 2006.285.10:22:08.98#ibcon#read 5, iclass 11, count 2 2006.285.10:22:08.98#ibcon#about to read 6, iclass 11, count 2 2006.285.10:22:08.98#ibcon#read 6, iclass 11, count 2 2006.285.10:22:08.98#ibcon#end of sib2, iclass 11, count 2 2006.285.10:22:08.98#ibcon#*mode == 0, iclass 11, count 2 2006.285.10:22:08.98#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.10:22:08.98#ibcon#[27=AT03-04\r\n] 2006.285.10:22:08.98#ibcon#*before write, iclass 11, count 2 2006.285.10:22:08.98#ibcon#enter sib2, iclass 11, count 2 2006.285.10:22:08.98#ibcon#flushed, iclass 11, count 2 2006.285.10:22:08.98#ibcon#about to write, iclass 11, count 2 2006.285.10:22:08.98#ibcon#wrote, iclass 11, count 2 2006.285.10:22:08.98#ibcon#about to read 3, iclass 11, count 2 2006.285.10:22:09.01#ibcon#read 3, iclass 11, count 2 2006.285.10:22:09.01#ibcon#about to read 4, iclass 11, count 2 2006.285.10:22:09.01#ibcon#read 4, iclass 11, count 2 2006.285.10:22:09.01#ibcon#about to read 5, iclass 11, count 2 2006.285.10:22:09.01#ibcon#read 5, iclass 11, count 2 2006.285.10:22:09.01#ibcon#about to read 6, iclass 11, count 2 2006.285.10:22:09.01#ibcon#read 6, iclass 11, count 2 2006.285.10:22:09.01#ibcon#end of sib2, iclass 11, count 2 2006.285.10:22:09.01#ibcon#*after write, iclass 11, count 2 2006.285.10:22:09.01#ibcon#*before return 0, iclass 11, count 2 2006.285.10:22:09.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:22:09.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:22:09.01#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.10:22:09.01#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:09.01#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:22:09.13#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:22:09.13#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:22:09.13#ibcon#enter wrdev, iclass 11, count 0 2006.285.10:22:09.13#ibcon#first serial, iclass 11, count 0 2006.285.10:22:09.13#ibcon#enter sib2, iclass 11, count 0 2006.285.10:22:09.13#ibcon#flushed, iclass 11, count 0 2006.285.10:22:09.13#ibcon#about to write, iclass 11, count 0 2006.285.10:22:09.13#ibcon#wrote, iclass 11, count 0 2006.285.10:22:09.13#ibcon#about to read 3, iclass 11, count 0 2006.285.10:22:09.15#ibcon#read 3, iclass 11, count 0 2006.285.10:22:09.15#ibcon#about to read 4, iclass 11, count 0 2006.285.10:22:09.15#ibcon#read 4, iclass 11, count 0 2006.285.10:22:09.15#ibcon#about to read 5, iclass 11, count 0 2006.285.10:22:09.15#ibcon#read 5, iclass 11, count 0 2006.285.10:22:09.15#ibcon#about to read 6, iclass 11, count 0 2006.285.10:22:09.15#ibcon#read 6, iclass 11, count 0 2006.285.10:22:09.15#ibcon#end of sib2, iclass 11, count 0 2006.285.10:22:09.15#ibcon#*mode == 0, iclass 11, count 0 2006.285.10:22:09.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.10:22:09.15#ibcon#[27=USB\r\n] 2006.285.10:22:09.15#ibcon#*before write, iclass 11, count 0 2006.285.10:22:09.15#ibcon#enter sib2, iclass 11, count 0 2006.285.10:22:09.15#ibcon#flushed, iclass 11, count 0 2006.285.10:22:09.15#ibcon#about to write, iclass 11, count 0 2006.285.10:22:09.15#ibcon#wrote, iclass 11, count 0 2006.285.10:22:09.15#ibcon#about to read 3, iclass 11, count 0 2006.285.10:22:09.18#ibcon#read 3, iclass 11, count 0 2006.285.10:22:09.18#ibcon#about to read 4, iclass 11, count 0 2006.285.10:22:09.18#ibcon#read 4, iclass 11, count 0 2006.285.10:22:09.18#ibcon#about to read 5, iclass 11, count 0 2006.285.10:22:09.18#ibcon#read 5, iclass 11, count 0 2006.285.10:22:09.18#ibcon#about to read 6, iclass 11, count 0 2006.285.10:22:09.18#ibcon#read 6, iclass 11, count 0 2006.285.10:22:09.18#ibcon#end of sib2, iclass 11, count 0 2006.285.10:22:09.18#ibcon#*after write, iclass 11, count 0 2006.285.10:22:09.18#ibcon#*before return 0, iclass 11, count 0 2006.285.10:22:09.18#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:22:09.18#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:22:09.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.10:22:09.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.10:22:09.18$vck44/vblo=4,679.99 2006.285.10:22:09.18#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.10:22:09.18#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.10:22:09.18#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:09.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:22:09.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:22:09.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:22:09.18#ibcon#enter wrdev, iclass 13, count 0 2006.285.10:22:09.18#ibcon#first serial, iclass 13, count 0 2006.285.10:22:09.18#ibcon#enter sib2, iclass 13, count 0 2006.285.10:22:09.18#ibcon#flushed, iclass 13, count 0 2006.285.10:22:09.18#ibcon#about to write, iclass 13, count 0 2006.285.10:22:09.18#ibcon#wrote, iclass 13, count 0 2006.285.10:22:09.18#ibcon#about to read 3, iclass 13, count 0 2006.285.10:22:09.20#ibcon#read 3, iclass 13, count 0 2006.285.10:22:09.20#ibcon#about to read 4, iclass 13, count 0 2006.285.10:22:09.20#ibcon#read 4, iclass 13, count 0 2006.285.10:22:09.20#ibcon#about to read 5, iclass 13, count 0 2006.285.10:22:09.20#ibcon#read 5, iclass 13, count 0 2006.285.10:22:09.20#ibcon#about to read 6, iclass 13, count 0 2006.285.10:22:09.20#ibcon#read 6, iclass 13, count 0 2006.285.10:22:09.20#ibcon#end of sib2, iclass 13, count 0 2006.285.10:22:09.20#ibcon#*mode == 0, iclass 13, count 0 2006.285.10:22:09.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.10:22:09.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:22:09.20#ibcon#*before write, iclass 13, count 0 2006.285.10:22:09.20#ibcon#enter sib2, iclass 13, count 0 2006.285.10:22:09.20#ibcon#flushed, iclass 13, count 0 2006.285.10:22:09.20#ibcon#about to write, iclass 13, count 0 2006.285.10:22:09.20#ibcon#wrote, iclass 13, count 0 2006.285.10:22:09.20#ibcon#about to read 3, iclass 13, count 0 2006.285.10:22:09.24#ibcon#read 3, iclass 13, count 0 2006.285.10:22:09.24#ibcon#about to read 4, iclass 13, count 0 2006.285.10:22:09.24#ibcon#read 4, iclass 13, count 0 2006.285.10:22:09.24#ibcon#about to read 5, iclass 13, count 0 2006.285.10:22:09.24#ibcon#read 5, iclass 13, count 0 2006.285.10:22:09.24#ibcon#about to read 6, iclass 13, count 0 2006.285.10:22:09.24#ibcon#read 6, iclass 13, count 0 2006.285.10:22:09.24#ibcon#end of sib2, iclass 13, count 0 2006.285.10:22:09.24#ibcon#*after write, iclass 13, count 0 2006.285.10:22:09.24#ibcon#*before return 0, iclass 13, count 0 2006.285.10:22:09.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:22:09.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:22:09.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.10:22:09.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.10:22:09.24$vck44/vb=4,5 2006.285.10:22:09.24#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.10:22:09.24#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.10:22:09.24#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:09.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:22:09.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:22:09.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:22:09.30#ibcon#enter wrdev, iclass 15, count 2 2006.285.10:22:09.30#ibcon#first serial, iclass 15, count 2 2006.285.10:22:09.30#ibcon#enter sib2, iclass 15, count 2 2006.285.10:22:09.30#ibcon#flushed, iclass 15, count 2 2006.285.10:22:09.30#ibcon#about to write, iclass 15, count 2 2006.285.10:22:09.30#ibcon#wrote, iclass 15, count 2 2006.285.10:22:09.30#ibcon#about to read 3, iclass 15, count 2 2006.285.10:22:09.32#ibcon#read 3, iclass 15, count 2 2006.285.10:22:09.32#ibcon#about to read 4, iclass 15, count 2 2006.285.10:22:09.32#ibcon#read 4, iclass 15, count 2 2006.285.10:22:09.32#ibcon#about to read 5, iclass 15, count 2 2006.285.10:22:09.32#ibcon#read 5, iclass 15, count 2 2006.285.10:22:09.32#ibcon#about to read 6, iclass 15, count 2 2006.285.10:22:09.32#ibcon#read 6, iclass 15, count 2 2006.285.10:22:09.32#ibcon#end of sib2, iclass 15, count 2 2006.285.10:22:09.32#ibcon#*mode == 0, iclass 15, count 2 2006.285.10:22:09.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.10:22:09.32#ibcon#[27=AT04-05\r\n] 2006.285.10:22:09.32#ibcon#*before write, iclass 15, count 2 2006.285.10:22:09.32#ibcon#enter sib2, iclass 15, count 2 2006.285.10:22:09.32#ibcon#flushed, iclass 15, count 2 2006.285.10:22:09.32#ibcon#about to write, iclass 15, count 2 2006.285.10:22:09.32#ibcon#wrote, iclass 15, count 2 2006.285.10:22:09.32#ibcon#about to read 3, iclass 15, count 2 2006.285.10:22:09.35#ibcon#read 3, iclass 15, count 2 2006.285.10:22:09.35#ibcon#about to read 4, iclass 15, count 2 2006.285.10:22:09.35#ibcon#read 4, iclass 15, count 2 2006.285.10:22:09.35#ibcon#about to read 5, iclass 15, count 2 2006.285.10:22:09.35#ibcon#read 5, iclass 15, count 2 2006.285.10:22:09.35#ibcon#about to read 6, iclass 15, count 2 2006.285.10:22:09.35#ibcon#read 6, iclass 15, count 2 2006.285.10:22:09.35#ibcon#end of sib2, iclass 15, count 2 2006.285.10:22:09.35#ibcon#*after write, iclass 15, count 2 2006.285.10:22:09.35#ibcon#*before return 0, iclass 15, count 2 2006.285.10:22:09.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:22:09.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:22:09.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.10:22:09.35#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:09.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:22:09.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:22:09.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:22:09.47#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:22:09.47#ibcon#first serial, iclass 15, count 0 2006.285.10:22:09.47#ibcon#enter sib2, iclass 15, count 0 2006.285.10:22:09.47#ibcon#flushed, iclass 15, count 0 2006.285.10:22:09.47#ibcon#about to write, iclass 15, count 0 2006.285.10:22:09.47#ibcon#wrote, iclass 15, count 0 2006.285.10:22:09.47#ibcon#about to read 3, iclass 15, count 0 2006.285.10:22:09.49#ibcon#read 3, iclass 15, count 0 2006.285.10:22:09.49#ibcon#about to read 4, iclass 15, count 0 2006.285.10:22:09.49#ibcon#read 4, iclass 15, count 0 2006.285.10:22:09.49#ibcon#about to read 5, iclass 15, count 0 2006.285.10:22:09.49#ibcon#read 5, iclass 15, count 0 2006.285.10:22:09.49#ibcon#about to read 6, iclass 15, count 0 2006.285.10:22:09.49#ibcon#read 6, iclass 15, count 0 2006.285.10:22:09.49#ibcon#end of sib2, iclass 15, count 0 2006.285.10:22:09.49#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:22:09.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:22:09.49#ibcon#[27=USB\r\n] 2006.285.10:22:09.49#ibcon#*before write, iclass 15, count 0 2006.285.10:22:09.49#ibcon#enter sib2, iclass 15, count 0 2006.285.10:22:09.49#ibcon#flushed, iclass 15, count 0 2006.285.10:22:09.49#ibcon#about to write, iclass 15, count 0 2006.285.10:22:09.49#ibcon#wrote, iclass 15, count 0 2006.285.10:22:09.49#ibcon#about to read 3, iclass 15, count 0 2006.285.10:22:09.52#ibcon#read 3, iclass 15, count 0 2006.285.10:22:09.52#ibcon#about to read 4, iclass 15, count 0 2006.285.10:22:09.52#ibcon#read 4, iclass 15, count 0 2006.285.10:22:09.52#ibcon#about to read 5, iclass 15, count 0 2006.285.10:22:09.52#ibcon#read 5, iclass 15, count 0 2006.285.10:22:09.52#ibcon#about to read 6, iclass 15, count 0 2006.285.10:22:09.52#ibcon#read 6, iclass 15, count 0 2006.285.10:22:09.52#ibcon#end of sib2, iclass 15, count 0 2006.285.10:22:09.52#ibcon#*after write, iclass 15, count 0 2006.285.10:22:09.52#ibcon#*before return 0, iclass 15, count 0 2006.285.10:22:09.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:22:09.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:22:09.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:22:09.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:22:09.52$vck44/vblo=5,709.99 2006.285.10:22:09.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.10:22:09.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.10:22:09.52#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:09.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:22:09.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:22:09.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:22:09.52#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:22:09.52#ibcon#first serial, iclass 17, count 0 2006.285.10:22:09.52#ibcon#enter sib2, iclass 17, count 0 2006.285.10:22:09.52#ibcon#flushed, iclass 17, count 0 2006.285.10:22:09.52#ibcon#about to write, iclass 17, count 0 2006.285.10:22:09.52#ibcon#wrote, iclass 17, count 0 2006.285.10:22:09.52#ibcon#about to read 3, iclass 17, count 0 2006.285.10:22:09.54#ibcon#read 3, iclass 17, count 0 2006.285.10:22:09.54#ibcon#about to read 4, iclass 17, count 0 2006.285.10:22:09.54#ibcon#read 4, iclass 17, count 0 2006.285.10:22:09.54#ibcon#about to read 5, iclass 17, count 0 2006.285.10:22:09.54#ibcon#read 5, iclass 17, count 0 2006.285.10:22:09.54#ibcon#about to read 6, iclass 17, count 0 2006.285.10:22:09.54#ibcon#read 6, iclass 17, count 0 2006.285.10:22:09.54#ibcon#end of sib2, iclass 17, count 0 2006.285.10:22:09.54#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:22:09.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:22:09.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:22:09.54#ibcon#*before write, iclass 17, count 0 2006.285.10:22:09.54#ibcon#enter sib2, iclass 17, count 0 2006.285.10:22:09.54#ibcon#flushed, iclass 17, count 0 2006.285.10:22:09.54#ibcon#about to write, iclass 17, count 0 2006.285.10:22:09.54#ibcon#wrote, iclass 17, count 0 2006.285.10:22:09.54#ibcon#about to read 3, iclass 17, count 0 2006.285.10:22:09.58#ibcon#read 3, iclass 17, count 0 2006.285.10:22:09.58#ibcon#about to read 4, iclass 17, count 0 2006.285.10:22:09.58#ibcon#read 4, iclass 17, count 0 2006.285.10:22:09.58#ibcon#about to read 5, iclass 17, count 0 2006.285.10:22:09.58#ibcon#read 5, iclass 17, count 0 2006.285.10:22:09.58#ibcon#about to read 6, iclass 17, count 0 2006.285.10:22:09.58#ibcon#read 6, iclass 17, count 0 2006.285.10:22:09.58#ibcon#end of sib2, iclass 17, count 0 2006.285.10:22:09.58#ibcon#*after write, iclass 17, count 0 2006.285.10:22:09.58#ibcon#*before return 0, iclass 17, count 0 2006.285.10:22:09.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:22:09.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:22:09.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:22:09.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:22:09.58$vck44/vb=5,4 2006.285.10:22:09.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.10:22:09.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.10:22:09.58#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:09.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:22:09.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:22:09.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:22:09.64#ibcon#enter wrdev, iclass 19, count 2 2006.285.10:22:09.64#ibcon#first serial, iclass 19, count 2 2006.285.10:22:09.64#ibcon#enter sib2, iclass 19, count 2 2006.285.10:22:09.64#ibcon#flushed, iclass 19, count 2 2006.285.10:22:09.64#ibcon#about to write, iclass 19, count 2 2006.285.10:22:09.64#ibcon#wrote, iclass 19, count 2 2006.285.10:22:09.64#ibcon#about to read 3, iclass 19, count 2 2006.285.10:22:09.66#ibcon#read 3, iclass 19, count 2 2006.285.10:22:09.66#ibcon#about to read 4, iclass 19, count 2 2006.285.10:22:09.66#ibcon#read 4, iclass 19, count 2 2006.285.10:22:09.66#ibcon#about to read 5, iclass 19, count 2 2006.285.10:22:09.66#ibcon#read 5, iclass 19, count 2 2006.285.10:22:09.66#ibcon#about to read 6, iclass 19, count 2 2006.285.10:22:09.66#ibcon#read 6, iclass 19, count 2 2006.285.10:22:09.66#ibcon#end of sib2, iclass 19, count 2 2006.285.10:22:09.66#ibcon#*mode == 0, iclass 19, count 2 2006.285.10:22:09.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.10:22:09.66#ibcon#[27=AT05-04\r\n] 2006.285.10:22:09.66#ibcon#*before write, iclass 19, count 2 2006.285.10:22:09.66#ibcon#enter sib2, iclass 19, count 2 2006.285.10:22:09.66#ibcon#flushed, iclass 19, count 2 2006.285.10:22:09.66#ibcon#about to write, iclass 19, count 2 2006.285.10:22:09.66#ibcon#wrote, iclass 19, count 2 2006.285.10:22:09.66#ibcon#about to read 3, iclass 19, count 2 2006.285.10:22:09.69#ibcon#read 3, iclass 19, count 2 2006.285.10:22:09.69#ibcon#about to read 4, iclass 19, count 2 2006.285.10:22:09.69#ibcon#read 4, iclass 19, count 2 2006.285.10:22:09.69#ibcon#about to read 5, iclass 19, count 2 2006.285.10:22:09.69#ibcon#read 5, iclass 19, count 2 2006.285.10:22:09.69#ibcon#about to read 6, iclass 19, count 2 2006.285.10:22:09.69#ibcon#read 6, iclass 19, count 2 2006.285.10:22:09.69#ibcon#end of sib2, iclass 19, count 2 2006.285.10:22:09.69#ibcon#*after write, iclass 19, count 2 2006.285.10:22:09.69#ibcon#*before return 0, iclass 19, count 2 2006.285.10:22:09.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:22:09.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:22:09.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.10:22:09.69#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:09.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:22:09.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:22:09.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:22:09.81#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:22:09.81#ibcon#first serial, iclass 19, count 0 2006.285.10:22:09.81#ibcon#enter sib2, iclass 19, count 0 2006.285.10:22:09.81#ibcon#flushed, iclass 19, count 0 2006.285.10:22:09.81#ibcon#about to write, iclass 19, count 0 2006.285.10:22:09.81#ibcon#wrote, iclass 19, count 0 2006.285.10:22:09.81#ibcon#about to read 3, iclass 19, count 0 2006.285.10:22:09.83#ibcon#read 3, iclass 19, count 0 2006.285.10:22:09.83#ibcon#about to read 4, iclass 19, count 0 2006.285.10:22:09.83#ibcon#read 4, iclass 19, count 0 2006.285.10:22:09.83#ibcon#about to read 5, iclass 19, count 0 2006.285.10:22:09.83#ibcon#read 5, iclass 19, count 0 2006.285.10:22:09.83#ibcon#about to read 6, iclass 19, count 0 2006.285.10:22:09.83#ibcon#read 6, iclass 19, count 0 2006.285.10:22:09.83#ibcon#end of sib2, iclass 19, count 0 2006.285.10:22:09.83#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:22:09.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:22:09.83#ibcon#[27=USB\r\n] 2006.285.10:22:09.83#ibcon#*before write, iclass 19, count 0 2006.285.10:22:09.83#ibcon#enter sib2, iclass 19, count 0 2006.285.10:22:09.83#ibcon#flushed, iclass 19, count 0 2006.285.10:22:09.83#ibcon#about to write, iclass 19, count 0 2006.285.10:22:09.83#ibcon#wrote, iclass 19, count 0 2006.285.10:22:09.83#ibcon#about to read 3, iclass 19, count 0 2006.285.10:22:09.86#ibcon#read 3, iclass 19, count 0 2006.285.10:22:09.86#ibcon#about to read 4, iclass 19, count 0 2006.285.10:22:09.86#ibcon#read 4, iclass 19, count 0 2006.285.10:22:09.86#ibcon#about to read 5, iclass 19, count 0 2006.285.10:22:09.86#ibcon#read 5, iclass 19, count 0 2006.285.10:22:09.86#ibcon#about to read 6, iclass 19, count 0 2006.285.10:22:09.86#ibcon#read 6, iclass 19, count 0 2006.285.10:22:09.86#ibcon#end of sib2, iclass 19, count 0 2006.285.10:22:09.86#ibcon#*after write, iclass 19, count 0 2006.285.10:22:09.86#ibcon#*before return 0, iclass 19, count 0 2006.285.10:22:09.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:22:09.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:22:09.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:22:09.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:22:09.86$vck44/vblo=6,719.99 2006.285.10:22:09.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.10:22:09.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.10:22:09.86#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:09.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:22:09.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:22:09.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:22:09.86#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:22:09.86#ibcon#first serial, iclass 21, count 0 2006.285.10:22:09.86#ibcon#enter sib2, iclass 21, count 0 2006.285.10:22:09.86#ibcon#flushed, iclass 21, count 0 2006.285.10:22:09.86#ibcon#about to write, iclass 21, count 0 2006.285.10:22:09.86#ibcon#wrote, iclass 21, count 0 2006.285.10:22:09.86#ibcon#about to read 3, iclass 21, count 0 2006.285.10:22:09.88#ibcon#read 3, iclass 21, count 0 2006.285.10:22:09.88#ibcon#about to read 4, iclass 21, count 0 2006.285.10:22:09.88#ibcon#read 4, iclass 21, count 0 2006.285.10:22:09.88#ibcon#about to read 5, iclass 21, count 0 2006.285.10:22:09.88#ibcon#read 5, iclass 21, count 0 2006.285.10:22:09.88#ibcon#about to read 6, iclass 21, count 0 2006.285.10:22:09.88#ibcon#read 6, iclass 21, count 0 2006.285.10:22:09.88#ibcon#end of sib2, iclass 21, count 0 2006.285.10:22:09.88#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:22:09.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:22:09.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:22:09.88#ibcon#*before write, iclass 21, count 0 2006.285.10:22:09.88#ibcon#enter sib2, iclass 21, count 0 2006.285.10:22:09.88#ibcon#flushed, iclass 21, count 0 2006.285.10:22:09.88#ibcon#about to write, iclass 21, count 0 2006.285.10:22:09.88#ibcon#wrote, iclass 21, count 0 2006.285.10:22:09.88#ibcon#about to read 3, iclass 21, count 0 2006.285.10:22:09.92#ibcon#read 3, iclass 21, count 0 2006.285.10:22:09.92#ibcon#about to read 4, iclass 21, count 0 2006.285.10:22:09.92#ibcon#read 4, iclass 21, count 0 2006.285.10:22:09.92#ibcon#about to read 5, iclass 21, count 0 2006.285.10:22:09.92#ibcon#read 5, iclass 21, count 0 2006.285.10:22:09.92#ibcon#about to read 6, iclass 21, count 0 2006.285.10:22:09.92#ibcon#read 6, iclass 21, count 0 2006.285.10:22:09.92#ibcon#end of sib2, iclass 21, count 0 2006.285.10:22:09.92#ibcon#*after write, iclass 21, count 0 2006.285.10:22:09.92#ibcon#*before return 0, iclass 21, count 0 2006.285.10:22:09.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:22:09.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:22:09.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:22:09.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:22:09.92$vck44/vb=6,3 2006.285.10:22:09.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.10:22:09.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.10:22:09.92#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:09.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:22:09.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:22:09.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:22:09.98#ibcon#enter wrdev, iclass 23, count 2 2006.285.10:22:09.98#ibcon#first serial, iclass 23, count 2 2006.285.10:22:09.98#ibcon#enter sib2, iclass 23, count 2 2006.285.10:22:09.98#ibcon#flushed, iclass 23, count 2 2006.285.10:22:09.98#ibcon#about to write, iclass 23, count 2 2006.285.10:22:09.98#ibcon#wrote, iclass 23, count 2 2006.285.10:22:09.98#ibcon#about to read 3, iclass 23, count 2 2006.285.10:22:10.00#ibcon#read 3, iclass 23, count 2 2006.285.10:22:10.00#ibcon#about to read 4, iclass 23, count 2 2006.285.10:22:10.00#ibcon#read 4, iclass 23, count 2 2006.285.10:22:10.00#ibcon#about to read 5, iclass 23, count 2 2006.285.10:22:10.00#ibcon#read 5, iclass 23, count 2 2006.285.10:22:10.00#ibcon#about to read 6, iclass 23, count 2 2006.285.10:22:10.00#ibcon#read 6, iclass 23, count 2 2006.285.10:22:10.00#ibcon#end of sib2, iclass 23, count 2 2006.285.10:22:10.00#ibcon#*mode == 0, iclass 23, count 2 2006.285.10:22:10.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.10:22:10.00#ibcon#[27=AT06-03\r\n] 2006.285.10:22:10.00#ibcon#*before write, iclass 23, count 2 2006.285.10:22:10.00#ibcon#enter sib2, iclass 23, count 2 2006.285.10:22:10.00#ibcon#flushed, iclass 23, count 2 2006.285.10:22:10.00#ibcon#about to write, iclass 23, count 2 2006.285.10:22:10.00#ibcon#wrote, iclass 23, count 2 2006.285.10:22:10.00#ibcon#about to read 3, iclass 23, count 2 2006.285.10:22:10.03#ibcon#read 3, iclass 23, count 2 2006.285.10:22:10.03#ibcon#about to read 4, iclass 23, count 2 2006.285.10:22:10.03#ibcon#read 4, iclass 23, count 2 2006.285.10:22:10.03#ibcon#about to read 5, iclass 23, count 2 2006.285.10:22:10.03#ibcon#read 5, iclass 23, count 2 2006.285.10:22:10.03#ibcon#about to read 6, iclass 23, count 2 2006.285.10:22:10.03#ibcon#read 6, iclass 23, count 2 2006.285.10:22:10.03#ibcon#end of sib2, iclass 23, count 2 2006.285.10:22:10.03#ibcon#*after write, iclass 23, count 2 2006.285.10:22:10.03#ibcon#*before return 0, iclass 23, count 2 2006.285.10:22:10.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:22:10.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:22:10.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.10:22:10.03#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:10.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:22:10.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:22:10.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:22:10.15#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:22:10.15#ibcon#first serial, iclass 23, count 0 2006.285.10:22:10.15#ibcon#enter sib2, iclass 23, count 0 2006.285.10:22:10.15#ibcon#flushed, iclass 23, count 0 2006.285.10:22:10.15#ibcon#about to write, iclass 23, count 0 2006.285.10:22:10.15#ibcon#wrote, iclass 23, count 0 2006.285.10:22:10.15#ibcon#about to read 3, iclass 23, count 0 2006.285.10:22:10.17#ibcon#read 3, iclass 23, count 0 2006.285.10:22:10.17#ibcon#about to read 4, iclass 23, count 0 2006.285.10:22:10.17#ibcon#read 4, iclass 23, count 0 2006.285.10:22:10.17#ibcon#about to read 5, iclass 23, count 0 2006.285.10:22:10.17#ibcon#read 5, iclass 23, count 0 2006.285.10:22:10.17#ibcon#about to read 6, iclass 23, count 0 2006.285.10:22:10.17#ibcon#read 6, iclass 23, count 0 2006.285.10:22:10.17#ibcon#end of sib2, iclass 23, count 0 2006.285.10:22:10.17#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:22:10.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:22:10.17#ibcon#[27=USB\r\n] 2006.285.10:22:10.17#ibcon#*before write, iclass 23, count 0 2006.285.10:22:10.17#ibcon#enter sib2, iclass 23, count 0 2006.285.10:22:10.17#ibcon#flushed, iclass 23, count 0 2006.285.10:22:10.17#ibcon#about to write, iclass 23, count 0 2006.285.10:22:10.17#ibcon#wrote, iclass 23, count 0 2006.285.10:22:10.17#ibcon#about to read 3, iclass 23, count 0 2006.285.10:22:10.20#ibcon#read 3, iclass 23, count 0 2006.285.10:22:10.20#ibcon#about to read 4, iclass 23, count 0 2006.285.10:22:10.20#ibcon#read 4, iclass 23, count 0 2006.285.10:22:10.20#ibcon#about to read 5, iclass 23, count 0 2006.285.10:22:10.20#ibcon#read 5, iclass 23, count 0 2006.285.10:22:10.20#ibcon#about to read 6, iclass 23, count 0 2006.285.10:22:10.20#ibcon#read 6, iclass 23, count 0 2006.285.10:22:10.20#ibcon#end of sib2, iclass 23, count 0 2006.285.10:22:10.20#ibcon#*after write, iclass 23, count 0 2006.285.10:22:10.20#ibcon#*before return 0, iclass 23, count 0 2006.285.10:22:10.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:22:10.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:22:10.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:22:10.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:22:10.20$vck44/vblo=7,734.99 2006.285.10:22:10.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.10:22:10.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.10:22:10.20#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:10.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:22:10.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:22:10.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:22:10.20#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:22:10.20#ibcon#first serial, iclass 25, count 0 2006.285.10:22:10.20#ibcon#enter sib2, iclass 25, count 0 2006.285.10:22:10.20#ibcon#flushed, iclass 25, count 0 2006.285.10:22:10.20#ibcon#about to write, iclass 25, count 0 2006.285.10:22:10.20#ibcon#wrote, iclass 25, count 0 2006.285.10:22:10.20#ibcon#about to read 3, iclass 25, count 0 2006.285.10:22:10.22#ibcon#read 3, iclass 25, count 0 2006.285.10:22:10.22#ibcon#about to read 4, iclass 25, count 0 2006.285.10:22:10.22#ibcon#read 4, iclass 25, count 0 2006.285.10:22:10.22#ibcon#about to read 5, iclass 25, count 0 2006.285.10:22:10.22#ibcon#read 5, iclass 25, count 0 2006.285.10:22:10.22#ibcon#about to read 6, iclass 25, count 0 2006.285.10:22:10.22#ibcon#read 6, iclass 25, count 0 2006.285.10:22:10.22#ibcon#end of sib2, iclass 25, count 0 2006.285.10:22:10.22#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:22:10.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:22:10.22#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:22:10.22#ibcon#*before write, iclass 25, count 0 2006.285.10:22:10.22#ibcon#enter sib2, iclass 25, count 0 2006.285.10:22:10.22#ibcon#flushed, iclass 25, count 0 2006.285.10:22:10.22#ibcon#about to write, iclass 25, count 0 2006.285.10:22:10.22#ibcon#wrote, iclass 25, count 0 2006.285.10:22:10.22#ibcon#about to read 3, iclass 25, count 0 2006.285.10:22:10.26#ibcon#read 3, iclass 25, count 0 2006.285.10:22:10.26#ibcon#about to read 4, iclass 25, count 0 2006.285.10:22:10.26#ibcon#read 4, iclass 25, count 0 2006.285.10:22:10.26#ibcon#about to read 5, iclass 25, count 0 2006.285.10:22:10.26#ibcon#read 5, iclass 25, count 0 2006.285.10:22:10.26#ibcon#about to read 6, iclass 25, count 0 2006.285.10:22:10.26#ibcon#read 6, iclass 25, count 0 2006.285.10:22:10.26#ibcon#end of sib2, iclass 25, count 0 2006.285.10:22:10.26#ibcon#*after write, iclass 25, count 0 2006.285.10:22:10.26#ibcon#*before return 0, iclass 25, count 0 2006.285.10:22:10.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:22:10.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:22:10.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:22:10.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:22:10.26$vck44/vb=7,4 2006.285.10:22:10.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.10:22:10.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.10:22:10.26#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:10.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:22:10.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:22:10.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:22:10.32#ibcon#enter wrdev, iclass 27, count 2 2006.285.10:22:10.32#ibcon#first serial, iclass 27, count 2 2006.285.10:22:10.32#ibcon#enter sib2, iclass 27, count 2 2006.285.10:22:10.32#ibcon#flushed, iclass 27, count 2 2006.285.10:22:10.32#ibcon#about to write, iclass 27, count 2 2006.285.10:22:10.32#ibcon#wrote, iclass 27, count 2 2006.285.10:22:10.32#ibcon#about to read 3, iclass 27, count 2 2006.285.10:22:10.34#ibcon#read 3, iclass 27, count 2 2006.285.10:22:10.34#ibcon#about to read 4, iclass 27, count 2 2006.285.10:22:10.34#ibcon#read 4, iclass 27, count 2 2006.285.10:22:10.34#ibcon#about to read 5, iclass 27, count 2 2006.285.10:22:10.34#ibcon#read 5, iclass 27, count 2 2006.285.10:22:10.34#ibcon#about to read 6, iclass 27, count 2 2006.285.10:22:10.34#ibcon#read 6, iclass 27, count 2 2006.285.10:22:10.34#ibcon#end of sib2, iclass 27, count 2 2006.285.10:22:10.34#ibcon#*mode == 0, iclass 27, count 2 2006.285.10:22:10.34#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.10:22:10.34#ibcon#[27=AT07-04\r\n] 2006.285.10:22:10.34#ibcon#*before write, iclass 27, count 2 2006.285.10:22:10.34#ibcon#enter sib2, iclass 27, count 2 2006.285.10:22:10.34#ibcon#flushed, iclass 27, count 2 2006.285.10:22:10.34#ibcon#about to write, iclass 27, count 2 2006.285.10:22:10.34#ibcon#wrote, iclass 27, count 2 2006.285.10:22:10.34#ibcon#about to read 3, iclass 27, count 2 2006.285.10:22:10.37#ibcon#read 3, iclass 27, count 2 2006.285.10:22:10.37#ibcon#about to read 4, iclass 27, count 2 2006.285.10:22:10.37#ibcon#read 4, iclass 27, count 2 2006.285.10:22:10.37#ibcon#about to read 5, iclass 27, count 2 2006.285.10:22:10.37#ibcon#read 5, iclass 27, count 2 2006.285.10:22:10.37#ibcon#about to read 6, iclass 27, count 2 2006.285.10:22:10.37#ibcon#read 6, iclass 27, count 2 2006.285.10:22:10.37#ibcon#end of sib2, iclass 27, count 2 2006.285.10:22:10.37#ibcon#*after write, iclass 27, count 2 2006.285.10:22:10.37#ibcon#*before return 0, iclass 27, count 2 2006.285.10:22:10.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:22:10.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:22:10.37#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.10:22:10.37#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:10.37#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:22:10.49#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:22:10.49#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:22:10.49#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:22:10.49#ibcon#first serial, iclass 27, count 0 2006.285.10:22:10.49#ibcon#enter sib2, iclass 27, count 0 2006.285.10:22:10.49#ibcon#flushed, iclass 27, count 0 2006.285.10:22:10.49#ibcon#about to write, iclass 27, count 0 2006.285.10:22:10.49#ibcon#wrote, iclass 27, count 0 2006.285.10:22:10.49#ibcon#about to read 3, iclass 27, count 0 2006.285.10:22:10.51#ibcon#read 3, iclass 27, count 0 2006.285.10:22:10.51#ibcon#about to read 4, iclass 27, count 0 2006.285.10:22:10.51#ibcon#read 4, iclass 27, count 0 2006.285.10:22:10.51#ibcon#about to read 5, iclass 27, count 0 2006.285.10:22:10.51#ibcon#read 5, iclass 27, count 0 2006.285.10:22:10.51#ibcon#about to read 6, iclass 27, count 0 2006.285.10:22:10.51#ibcon#read 6, iclass 27, count 0 2006.285.10:22:10.51#ibcon#end of sib2, iclass 27, count 0 2006.285.10:22:10.51#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:22:10.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:22:10.51#ibcon#[27=USB\r\n] 2006.285.10:22:10.51#ibcon#*before write, iclass 27, count 0 2006.285.10:22:10.51#ibcon#enter sib2, iclass 27, count 0 2006.285.10:22:10.51#ibcon#flushed, iclass 27, count 0 2006.285.10:22:10.51#ibcon#about to write, iclass 27, count 0 2006.285.10:22:10.51#ibcon#wrote, iclass 27, count 0 2006.285.10:22:10.51#ibcon#about to read 3, iclass 27, count 0 2006.285.10:22:10.54#ibcon#read 3, iclass 27, count 0 2006.285.10:22:10.54#ibcon#about to read 4, iclass 27, count 0 2006.285.10:22:10.54#ibcon#read 4, iclass 27, count 0 2006.285.10:22:10.54#ibcon#about to read 5, iclass 27, count 0 2006.285.10:22:10.54#ibcon#read 5, iclass 27, count 0 2006.285.10:22:10.54#ibcon#about to read 6, iclass 27, count 0 2006.285.10:22:10.54#ibcon#read 6, iclass 27, count 0 2006.285.10:22:10.54#ibcon#end of sib2, iclass 27, count 0 2006.285.10:22:10.54#ibcon#*after write, iclass 27, count 0 2006.285.10:22:10.54#ibcon#*before return 0, iclass 27, count 0 2006.285.10:22:10.54#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:22:10.54#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:22:10.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:22:10.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:22:10.54$vck44/vblo=8,744.99 2006.285.10:22:10.54#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.10:22:10.54#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.10:22:10.54#ibcon#ireg 17 cls_cnt 0 2006.285.10:22:10.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:22:10.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:22:10.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:22:10.54#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:22:10.54#ibcon#first serial, iclass 29, count 0 2006.285.10:22:10.54#ibcon#enter sib2, iclass 29, count 0 2006.285.10:22:10.54#ibcon#flushed, iclass 29, count 0 2006.285.10:22:10.54#ibcon#about to write, iclass 29, count 0 2006.285.10:22:10.54#ibcon#wrote, iclass 29, count 0 2006.285.10:22:10.54#ibcon#about to read 3, iclass 29, count 0 2006.285.10:22:10.56#ibcon#read 3, iclass 29, count 0 2006.285.10:22:10.56#ibcon#about to read 4, iclass 29, count 0 2006.285.10:22:10.56#ibcon#read 4, iclass 29, count 0 2006.285.10:22:10.56#ibcon#about to read 5, iclass 29, count 0 2006.285.10:22:10.56#ibcon#read 5, iclass 29, count 0 2006.285.10:22:10.56#ibcon#about to read 6, iclass 29, count 0 2006.285.10:22:10.56#ibcon#read 6, iclass 29, count 0 2006.285.10:22:10.56#ibcon#end of sib2, iclass 29, count 0 2006.285.10:22:10.56#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:22:10.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:22:10.56#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:22:10.56#ibcon#*before write, iclass 29, count 0 2006.285.10:22:10.56#ibcon#enter sib2, iclass 29, count 0 2006.285.10:22:10.56#ibcon#flushed, iclass 29, count 0 2006.285.10:22:10.56#ibcon#about to write, iclass 29, count 0 2006.285.10:22:10.56#ibcon#wrote, iclass 29, count 0 2006.285.10:22:10.56#ibcon#about to read 3, iclass 29, count 0 2006.285.10:22:10.60#ibcon#read 3, iclass 29, count 0 2006.285.10:22:10.60#ibcon#about to read 4, iclass 29, count 0 2006.285.10:22:10.60#ibcon#read 4, iclass 29, count 0 2006.285.10:22:10.60#ibcon#about to read 5, iclass 29, count 0 2006.285.10:22:10.60#ibcon#read 5, iclass 29, count 0 2006.285.10:22:10.60#ibcon#about to read 6, iclass 29, count 0 2006.285.10:22:10.60#ibcon#read 6, iclass 29, count 0 2006.285.10:22:10.60#ibcon#end of sib2, iclass 29, count 0 2006.285.10:22:10.60#ibcon#*after write, iclass 29, count 0 2006.285.10:22:10.60#ibcon#*before return 0, iclass 29, count 0 2006.285.10:22:10.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:22:10.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:22:10.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:22:10.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:22:10.60$vck44/vb=8,4 2006.285.10:22:10.60#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.10:22:10.60#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.10:22:10.60#ibcon#ireg 11 cls_cnt 2 2006.285.10:22:10.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:22:10.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:22:10.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:22:10.66#ibcon#enter wrdev, iclass 31, count 2 2006.285.10:22:10.66#ibcon#first serial, iclass 31, count 2 2006.285.10:22:10.66#ibcon#enter sib2, iclass 31, count 2 2006.285.10:22:10.66#ibcon#flushed, iclass 31, count 2 2006.285.10:22:10.66#ibcon#about to write, iclass 31, count 2 2006.285.10:22:10.66#ibcon#wrote, iclass 31, count 2 2006.285.10:22:10.66#ibcon#about to read 3, iclass 31, count 2 2006.285.10:22:10.68#ibcon#read 3, iclass 31, count 2 2006.285.10:22:10.68#ibcon#about to read 4, iclass 31, count 2 2006.285.10:22:10.68#ibcon#read 4, iclass 31, count 2 2006.285.10:22:10.68#ibcon#about to read 5, iclass 31, count 2 2006.285.10:22:10.68#ibcon#read 5, iclass 31, count 2 2006.285.10:22:10.68#ibcon#about to read 6, iclass 31, count 2 2006.285.10:22:10.68#ibcon#read 6, iclass 31, count 2 2006.285.10:22:10.68#ibcon#end of sib2, iclass 31, count 2 2006.285.10:22:10.68#ibcon#*mode == 0, iclass 31, count 2 2006.285.10:22:10.68#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.10:22:10.68#ibcon#[27=AT08-04\r\n] 2006.285.10:22:10.68#ibcon#*before write, iclass 31, count 2 2006.285.10:22:10.68#ibcon#enter sib2, iclass 31, count 2 2006.285.10:22:10.68#ibcon#flushed, iclass 31, count 2 2006.285.10:22:10.68#ibcon#about to write, iclass 31, count 2 2006.285.10:22:10.68#ibcon#wrote, iclass 31, count 2 2006.285.10:22:10.68#ibcon#about to read 3, iclass 31, count 2 2006.285.10:22:10.71#ibcon#read 3, iclass 31, count 2 2006.285.10:22:10.71#ibcon#about to read 4, iclass 31, count 2 2006.285.10:22:10.71#ibcon#read 4, iclass 31, count 2 2006.285.10:22:10.71#ibcon#about to read 5, iclass 31, count 2 2006.285.10:22:10.71#ibcon#read 5, iclass 31, count 2 2006.285.10:22:10.71#ibcon#about to read 6, iclass 31, count 2 2006.285.10:22:10.71#ibcon#read 6, iclass 31, count 2 2006.285.10:22:10.71#ibcon#end of sib2, iclass 31, count 2 2006.285.10:22:10.71#ibcon#*after write, iclass 31, count 2 2006.285.10:22:10.71#ibcon#*before return 0, iclass 31, count 2 2006.285.10:22:10.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:22:10.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:22:10.71#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.10:22:10.71#ibcon#ireg 7 cls_cnt 0 2006.285.10:22:10.71#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:22:10.83#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:22:10.83#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:22:10.83#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:22:10.83#ibcon#first serial, iclass 31, count 0 2006.285.10:22:10.83#ibcon#enter sib2, iclass 31, count 0 2006.285.10:22:10.83#ibcon#flushed, iclass 31, count 0 2006.285.10:22:10.83#ibcon#about to write, iclass 31, count 0 2006.285.10:22:10.83#ibcon#wrote, iclass 31, count 0 2006.285.10:22:10.83#ibcon#about to read 3, iclass 31, count 0 2006.285.10:22:10.85#ibcon#read 3, iclass 31, count 0 2006.285.10:22:10.85#ibcon#about to read 4, iclass 31, count 0 2006.285.10:22:10.85#ibcon#read 4, iclass 31, count 0 2006.285.10:22:10.85#ibcon#about to read 5, iclass 31, count 0 2006.285.10:22:10.85#ibcon#read 5, iclass 31, count 0 2006.285.10:22:10.85#ibcon#about to read 6, iclass 31, count 0 2006.285.10:22:10.85#ibcon#read 6, iclass 31, count 0 2006.285.10:22:10.85#ibcon#end of sib2, iclass 31, count 0 2006.285.10:22:10.85#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:22:10.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:22:10.85#ibcon#[27=USB\r\n] 2006.285.10:22:10.85#ibcon#*before write, iclass 31, count 0 2006.285.10:22:10.85#ibcon#enter sib2, iclass 31, count 0 2006.285.10:22:10.85#ibcon#flushed, iclass 31, count 0 2006.285.10:22:10.85#ibcon#about to write, iclass 31, count 0 2006.285.10:22:10.85#ibcon#wrote, iclass 31, count 0 2006.285.10:22:10.85#ibcon#about to read 3, iclass 31, count 0 2006.285.10:22:10.88#ibcon#read 3, iclass 31, count 0 2006.285.10:22:10.88#ibcon#about to read 4, iclass 31, count 0 2006.285.10:22:10.88#ibcon#read 4, iclass 31, count 0 2006.285.10:22:10.88#ibcon#about to read 5, iclass 31, count 0 2006.285.10:22:10.88#ibcon#read 5, iclass 31, count 0 2006.285.10:22:10.88#ibcon#about to read 6, iclass 31, count 0 2006.285.10:22:10.88#ibcon#read 6, iclass 31, count 0 2006.285.10:22:10.88#ibcon#end of sib2, iclass 31, count 0 2006.285.10:22:10.88#ibcon#*after write, iclass 31, count 0 2006.285.10:22:10.88#ibcon#*before return 0, iclass 31, count 0 2006.285.10:22:10.88#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:22:10.88#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:22:10.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:22:10.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:22:10.88$vck44/vabw=wide 2006.285.10:22:10.88#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.10:22:10.88#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.10:22:10.88#ibcon#ireg 8 cls_cnt 0 2006.285.10:22:10.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:22:10.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:22:10.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:22:10.88#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:22:10.88#ibcon#first serial, iclass 33, count 0 2006.285.10:22:10.88#ibcon#enter sib2, iclass 33, count 0 2006.285.10:22:10.88#ibcon#flushed, iclass 33, count 0 2006.285.10:22:10.88#ibcon#about to write, iclass 33, count 0 2006.285.10:22:10.88#ibcon#wrote, iclass 33, count 0 2006.285.10:22:10.88#ibcon#about to read 3, iclass 33, count 0 2006.285.10:22:10.90#ibcon#read 3, iclass 33, count 0 2006.285.10:22:10.90#ibcon#about to read 4, iclass 33, count 0 2006.285.10:22:10.90#ibcon#read 4, iclass 33, count 0 2006.285.10:22:10.90#ibcon#about to read 5, iclass 33, count 0 2006.285.10:22:10.90#ibcon#read 5, iclass 33, count 0 2006.285.10:22:10.90#ibcon#about to read 6, iclass 33, count 0 2006.285.10:22:10.90#ibcon#read 6, iclass 33, count 0 2006.285.10:22:10.90#ibcon#end of sib2, iclass 33, count 0 2006.285.10:22:10.90#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:22:10.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:22:10.90#ibcon#[25=BW32\r\n] 2006.285.10:22:10.90#ibcon#*before write, iclass 33, count 0 2006.285.10:22:10.90#ibcon#enter sib2, iclass 33, count 0 2006.285.10:22:10.90#ibcon#flushed, iclass 33, count 0 2006.285.10:22:10.90#ibcon#about to write, iclass 33, count 0 2006.285.10:22:10.90#ibcon#wrote, iclass 33, count 0 2006.285.10:22:10.90#ibcon#about to read 3, iclass 33, count 0 2006.285.10:22:10.93#ibcon#read 3, iclass 33, count 0 2006.285.10:22:10.93#ibcon#about to read 4, iclass 33, count 0 2006.285.10:22:10.93#ibcon#read 4, iclass 33, count 0 2006.285.10:22:10.93#ibcon#about to read 5, iclass 33, count 0 2006.285.10:22:10.93#ibcon#read 5, iclass 33, count 0 2006.285.10:22:10.93#ibcon#about to read 6, iclass 33, count 0 2006.285.10:22:10.93#ibcon#read 6, iclass 33, count 0 2006.285.10:22:10.93#ibcon#end of sib2, iclass 33, count 0 2006.285.10:22:10.93#ibcon#*after write, iclass 33, count 0 2006.285.10:22:10.93#ibcon#*before return 0, iclass 33, count 0 2006.285.10:22:10.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:22:10.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:22:10.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:22:10.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:22:10.93$vck44/vbbw=wide 2006.285.10:22:10.93#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.10:22:10.93#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.10:22:10.93#ibcon#ireg 8 cls_cnt 0 2006.285.10:22:10.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:22:11.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:22:11.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:22:11.00#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:22:11.00#ibcon#first serial, iclass 35, count 0 2006.285.10:22:11.00#ibcon#enter sib2, iclass 35, count 0 2006.285.10:22:11.00#ibcon#flushed, iclass 35, count 0 2006.285.10:22:11.00#ibcon#about to write, iclass 35, count 0 2006.285.10:22:11.00#ibcon#wrote, iclass 35, count 0 2006.285.10:22:11.00#ibcon#about to read 3, iclass 35, count 0 2006.285.10:22:11.02#ibcon#read 3, iclass 35, count 0 2006.285.10:22:11.02#ibcon#about to read 4, iclass 35, count 0 2006.285.10:22:11.02#ibcon#read 4, iclass 35, count 0 2006.285.10:22:11.02#ibcon#about to read 5, iclass 35, count 0 2006.285.10:22:11.02#ibcon#read 5, iclass 35, count 0 2006.285.10:22:11.02#ibcon#about to read 6, iclass 35, count 0 2006.285.10:22:11.02#ibcon#read 6, iclass 35, count 0 2006.285.10:22:11.02#ibcon#end of sib2, iclass 35, count 0 2006.285.10:22:11.02#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:22:11.02#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:22:11.02#ibcon#[27=BW32\r\n] 2006.285.10:22:11.02#ibcon#*before write, iclass 35, count 0 2006.285.10:22:11.02#ibcon#enter sib2, iclass 35, count 0 2006.285.10:22:11.02#ibcon#flushed, iclass 35, count 0 2006.285.10:22:11.02#ibcon#about to write, iclass 35, count 0 2006.285.10:22:11.02#ibcon#wrote, iclass 35, count 0 2006.285.10:22:11.02#ibcon#about to read 3, iclass 35, count 0 2006.285.10:22:11.05#ibcon#read 3, iclass 35, count 0 2006.285.10:22:11.05#ibcon#about to read 4, iclass 35, count 0 2006.285.10:22:11.05#ibcon#read 4, iclass 35, count 0 2006.285.10:22:11.05#ibcon#about to read 5, iclass 35, count 0 2006.285.10:22:11.05#ibcon#read 5, iclass 35, count 0 2006.285.10:22:11.05#ibcon#about to read 6, iclass 35, count 0 2006.285.10:22:11.05#ibcon#read 6, iclass 35, count 0 2006.285.10:22:11.05#ibcon#end of sib2, iclass 35, count 0 2006.285.10:22:11.05#ibcon#*after write, iclass 35, count 0 2006.285.10:22:11.05#ibcon#*before return 0, iclass 35, count 0 2006.285.10:22:11.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:22:11.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:22:11.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:22:11.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:22:11.05$setupk4/ifdk4 2006.285.10:22:11.05$ifdk4/lo= 2006.285.10:22:11.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:22:11.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:22:11.05$ifdk4/patch= 2006.285.10:22:11.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:22:11.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:22:11.05$setupk4/!*+20s 2006.285.10:22:15.18#abcon#<5=/04 1.4 2.5 19.77 901015.0\r\n> 2006.285.10:22:15.20#abcon#{5=INTERFACE CLEAR} 2006.285.10:22:15.26#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:22:24.13#trakl#Source acquired 2006.285.10:22:25.13#flagr#flagr/antenna,acquired 2006.285.10:22:25.56$setupk4/"tpicd 2006.285.10:22:25.56$setupk4/echo=off 2006.285.10:22:25.56$setupk4/xlog=off 2006.285.10:22:25.56:!2006.285.10:24:51 2006.285.10:24:51.00:preob 2006.285.10:24:51.14/onsource/TRACKING 2006.285.10:24:51.14:!2006.285.10:25:01 2006.285.10:25:01.00:"tape 2006.285.10:25:01.00:"st=record 2006.285.10:25:01.00:data_valid=on 2006.285.10:25:01.00:midob 2006.285.10:25:01.14/onsource/TRACKING 2006.285.10:25:01.14/wx/19.79,1015.0,90 2006.285.10:25:01.28/cable/+6.4871E-03 2006.285.10:25:02.37/va/01,07,usb,yes,33,35 2006.285.10:25:02.37/va/02,06,usb,yes,33,33 2006.285.10:25:02.37/va/03,07,usb,yes,32,34 2006.285.10:25:02.37/va/04,06,usb,yes,34,35 2006.285.10:25:02.37/va/05,03,usb,yes,33,34 2006.285.10:25:02.37/va/06,04,usb,yes,30,30 2006.285.10:25:02.37/va/07,04,usb,yes,31,31 2006.285.10:25:02.37/va/08,03,usb,yes,31,38 2006.285.10:25:02.60/valo/01,524.99,yes,locked 2006.285.10:25:02.60/valo/02,534.99,yes,locked 2006.285.10:25:02.60/valo/03,564.99,yes,locked 2006.285.10:25:02.60/valo/04,624.99,yes,locked 2006.285.10:25:02.60/valo/05,734.99,yes,locked 2006.285.10:25:02.60/valo/06,814.99,yes,locked 2006.285.10:25:02.60/valo/07,864.99,yes,locked 2006.285.10:25:02.60/valo/08,884.99,yes,locked 2006.285.10:25:03.69/vb/01,04,usb,yes,31,29 2006.285.10:25:03.69/vb/02,05,usb,yes,29,29 2006.285.10:25:03.69/vb/03,04,usb,yes,30,33 2006.285.10:25:03.69/vb/04,05,usb,yes,31,30 2006.285.10:25:03.69/vb/05,04,usb,yes,27,30 2006.285.10:25:03.69/vb/06,03,usb,yes,39,34 2006.285.10:25:03.69/vb/07,04,usb,yes,31,31 2006.285.10:25:03.69/vb/08,04,usb,yes,28,32 2006.285.10:25:03.92/vblo/01,629.99,yes,locked 2006.285.10:25:03.92/vblo/02,634.99,yes,locked 2006.285.10:25:03.92/vblo/03,649.99,yes,locked 2006.285.10:25:03.92/vblo/04,679.99,yes,locked 2006.285.10:25:03.92/vblo/05,709.99,yes,locked 2006.285.10:25:03.92/vblo/06,719.99,yes,locked 2006.285.10:25:03.92/vblo/07,734.99,yes,locked 2006.285.10:25:03.92/vblo/08,744.99,yes,locked 2006.285.10:25:04.07/vabw/8 2006.285.10:25:04.22/vbbw/8 2006.285.10:25:04.31/xfe/off,on,12.2 2006.285.10:25:04.68/ifatt/23,28,28,28 2006.285.10:25:05.07/fmout-gps/S +2.63E-07 2006.285.10:25:05.09:!2006.285.10:25:41 2006.285.10:25:41.00:data_valid=off 2006.285.10:25:41.00:"et 2006.285.10:25:41.00:!+3s 2006.285.10:25:44.01:"tape 2006.285.10:25:44.01:postob 2006.285.10:25:44.07/cable/+6.4846E-03 2006.285.10:25:44.07/wx/19.78,1015.0,90 2006.285.10:25:45.07/fmout-gps/S +2.59E-07 2006.285.10:25:45.07:scan_name=285-1027,jd0610,70 2006.285.10:25:45.07:source=2121+053,212344.52,053522.1,2000.0,cw 2006.285.10:25:46.14#flagr#flagr/antenna,new-source 2006.285.10:25:46.14:checkk5 2006.285.10:25:46.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:25:46.93/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:25:47.35/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:25:47.73/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:25:48.11/chk_obsdata//k5ts1/T2851025??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.10:25:48.52/chk_obsdata//k5ts2/T2851025??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.10:25:48.92/chk_obsdata//k5ts3/T2851025??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.10:25:49.35/chk_obsdata//k5ts4/T2851025??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.10:25:50.35/k5log//k5ts1_log_newline 2006.285.10:25:51.11/k5log//k5ts2_log_newline 2006.285.10:25:52.11/k5log//k5ts3_log_newline 2006.285.10:25:52.92/k5log//k5ts4_log_newline 2006.285.10:25:52.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:25:52.94:setupk4=1 2006.285.10:25:52.94$setupk4/echo=on 2006.285.10:25:52.94$setupk4/pcalon 2006.285.10:25:52.94$pcalon/"no phase cal control is implemented here 2006.285.10:25:52.94$setupk4/"tpicd=stop 2006.285.10:25:52.94$setupk4/"rec=synch_on 2006.285.10:25:52.94$setupk4/"rec_mode=128 2006.285.10:25:52.94$setupk4/!* 2006.285.10:25:52.94$setupk4/recpk4 2006.285.10:25:52.94$recpk4/recpatch= 2006.285.10:25:52.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:25:52.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:25:52.94$setupk4/vck44 2006.285.10:25:52.95$vck44/valo=1,524.99 2006.285.10:25:52.95#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.10:25:52.95#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.10:25:52.95#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:52.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:25:52.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:25:52.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:25:52.95#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:25:52.95#ibcon#first serial, iclass 15, count 0 2006.285.10:25:52.95#ibcon#enter sib2, iclass 15, count 0 2006.285.10:25:52.95#ibcon#flushed, iclass 15, count 0 2006.285.10:25:52.95#ibcon#about to write, iclass 15, count 0 2006.285.10:25:52.95#ibcon#wrote, iclass 15, count 0 2006.285.10:25:52.95#ibcon#about to read 3, iclass 15, count 0 2006.285.10:25:52.96#ibcon#read 3, iclass 15, count 0 2006.285.10:25:52.96#ibcon#about to read 4, iclass 15, count 0 2006.285.10:25:52.96#ibcon#read 4, iclass 15, count 0 2006.285.10:25:52.96#ibcon#about to read 5, iclass 15, count 0 2006.285.10:25:52.96#ibcon#read 5, iclass 15, count 0 2006.285.10:25:52.96#ibcon#about to read 6, iclass 15, count 0 2006.285.10:25:52.96#ibcon#read 6, iclass 15, count 0 2006.285.10:25:52.96#ibcon#end of sib2, iclass 15, count 0 2006.285.10:25:52.96#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:25:52.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:25:52.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:25:52.96#ibcon#*before write, iclass 15, count 0 2006.285.10:25:52.96#ibcon#enter sib2, iclass 15, count 0 2006.285.10:25:52.96#ibcon#flushed, iclass 15, count 0 2006.285.10:25:52.96#ibcon#about to write, iclass 15, count 0 2006.285.10:25:52.96#ibcon#wrote, iclass 15, count 0 2006.285.10:25:52.96#ibcon#about to read 3, iclass 15, count 0 2006.285.10:25:53.01#ibcon#read 3, iclass 15, count 0 2006.285.10:25:53.01#ibcon#about to read 4, iclass 15, count 0 2006.285.10:25:53.01#ibcon#read 4, iclass 15, count 0 2006.285.10:25:53.01#ibcon#about to read 5, iclass 15, count 0 2006.285.10:25:53.01#ibcon#read 5, iclass 15, count 0 2006.285.10:25:53.01#ibcon#about to read 6, iclass 15, count 0 2006.285.10:25:53.01#ibcon#read 6, iclass 15, count 0 2006.285.10:25:53.01#ibcon#end of sib2, iclass 15, count 0 2006.285.10:25:53.01#ibcon#*after write, iclass 15, count 0 2006.285.10:25:53.01#ibcon#*before return 0, iclass 15, count 0 2006.285.10:25:53.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:25:53.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:25:53.01#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:25:53.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:25:53.01$vck44/va=1,7 2006.285.10:25:53.01#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.10:25:53.01#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.10:25:53.01#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:53.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:25:53.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:25:53.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:25:53.01#ibcon#enter wrdev, iclass 17, count 2 2006.285.10:25:53.01#ibcon#first serial, iclass 17, count 2 2006.285.10:25:53.01#ibcon#enter sib2, iclass 17, count 2 2006.285.10:25:53.01#ibcon#flushed, iclass 17, count 2 2006.285.10:25:53.01#ibcon#about to write, iclass 17, count 2 2006.285.10:25:53.01#ibcon#wrote, iclass 17, count 2 2006.285.10:25:53.01#ibcon#about to read 3, iclass 17, count 2 2006.285.10:25:53.03#ibcon#read 3, iclass 17, count 2 2006.285.10:25:53.03#ibcon#about to read 4, iclass 17, count 2 2006.285.10:25:53.03#ibcon#read 4, iclass 17, count 2 2006.285.10:25:53.03#ibcon#about to read 5, iclass 17, count 2 2006.285.10:25:53.03#ibcon#read 5, iclass 17, count 2 2006.285.10:25:53.03#ibcon#about to read 6, iclass 17, count 2 2006.285.10:25:53.03#ibcon#read 6, iclass 17, count 2 2006.285.10:25:53.03#ibcon#end of sib2, iclass 17, count 2 2006.285.10:25:53.03#ibcon#*mode == 0, iclass 17, count 2 2006.285.10:25:53.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.10:25:53.03#ibcon#[25=AT01-07\r\n] 2006.285.10:25:53.03#ibcon#*before write, iclass 17, count 2 2006.285.10:25:53.03#ibcon#enter sib2, iclass 17, count 2 2006.285.10:25:53.03#ibcon#flushed, iclass 17, count 2 2006.285.10:25:53.03#ibcon#about to write, iclass 17, count 2 2006.285.10:25:53.03#ibcon#wrote, iclass 17, count 2 2006.285.10:25:53.03#ibcon#about to read 3, iclass 17, count 2 2006.285.10:25:53.06#ibcon#read 3, iclass 17, count 2 2006.285.10:25:53.06#ibcon#about to read 4, iclass 17, count 2 2006.285.10:25:53.06#ibcon#read 4, iclass 17, count 2 2006.285.10:25:53.06#ibcon#about to read 5, iclass 17, count 2 2006.285.10:25:53.06#ibcon#read 5, iclass 17, count 2 2006.285.10:25:53.06#ibcon#about to read 6, iclass 17, count 2 2006.285.10:25:53.06#ibcon#read 6, iclass 17, count 2 2006.285.10:25:53.06#ibcon#end of sib2, iclass 17, count 2 2006.285.10:25:53.06#ibcon#*after write, iclass 17, count 2 2006.285.10:25:53.06#ibcon#*before return 0, iclass 17, count 2 2006.285.10:25:53.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:25:53.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:25:53.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.10:25:53.06#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:53.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:25:53.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:25:53.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:25:53.18#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:25:53.18#ibcon#first serial, iclass 17, count 0 2006.285.10:25:53.18#ibcon#enter sib2, iclass 17, count 0 2006.285.10:25:53.18#ibcon#flushed, iclass 17, count 0 2006.285.10:25:53.18#ibcon#about to write, iclass 17, count 0 2006.285.10:25:53.18#ibcon#wrote, iclass 17, count 0 2006.285.10:25:53.18#ibcon#about to read 3, iclass 17, count 0 2006.285.10:25:53.20#ibcon#read 3, iclass 17, count 0 2006.285.10:25:53.20#ibcon#about to read 4, iclass 17, count 0 2006.285.10:25:53.20#ibcon#read 4, iclass 17, count 0 2006.285.10:25:53.20#ibcon#about to read 5, iclass 17, count 0 2006.285.10:25:53.20#ibcon#read 5, iclass 17, count 0 2006.285.10:25:53.20#ibcon#about to read 6, iclass 17, count 0 2006.285.10:25:53.20#ibcon#read 6, iclass 17, count 0 2006.285.10:25:53.20#ibcon#end of sib2, iclass 17, count 0 2006.285.10:25:53.20#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:25:53.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:25:53.20#ibcon#[25=USB\r\n] 2006.285.10:25:53.20#ibcon#*before write, iclass 17, count 0 2006.285.10:25:53.20#ibcon#enter sib2, iclass 17, count 0 2006.285.10:25:53.20#ibcon#flushed, iclass 17, count 0 2006.285.10:25:53.20#ibcon#about to write, iclass 17, count 0 2006.285.10:25:53.20#ibcon#wrote, iclass 17, count 0 2006.285.10:25:53.20#ibcon#about to read 3, iclass 17, count 0 2006.285.10:25:53.23#ibcon#read 3, iclass 17, count 0 2006.285.10:25:53.23#ibcon#about to read 4, iclass 17, count 0 2006.285.10:25:53.23#ibcon#read 4, iclass 17, count 0 2006.285.10:25:53.23#ibcon#about to read 5, iclass 17, count 0 2006.285.10:25:53.23#ibcon#read 5, iclass 17, count 0 2006.285.10:25:53.23#ibcon#about to read 6, iclass 17, count 0 2006.285.10:25:53.23#ibcon#read 6, iclass 17, count 0 2006.285.10:25:53.23#ibcon#end of sib2, iclass 17, count 0 2006.285.10:25:53.23#ibcon#*after write, iclass 17, count 0 2006.285.10:25:53.23#ibcon#*before return 0, iclass 17, count 0 2006.285.10:25:53.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:25:53.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:25:53.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:25:53.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:25:53.23$vck44/valo=2,534.99 2006.285.10:25:53.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.10:25:53.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.10:25:53.23#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:53.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:25:53.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:25:53.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:25:53.23#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:25:53.23#ibcon#first serial, iclass 19, count 0 2006.285.10:25:53.23#ibcon#enter sib2, iclass 19, count 0 2006.285.10:25:53.23#ibcon#flushed, iclass 19, count 0 2006.285.10:25:53.23#ibcon#about to write, iclass 19, count 0 2006.285.10:25:53.23#ibcon#wrote, iclass 19, count 0 2006.285.10:25:53.23#ibcon#about to read 3, iclass 19, count 0 2006.285.10:25:53.25#ibcon#read 3, iclass 19, count 0 2006.285.10:25:53.25#ibcon#about to read 4, iclass 19, count 0 2006.285.10:25:53.25#ibcon#read 4, iclass 19, count 0 2006.285.10:25:53.25#ibcon#about to read 5, iclass 19, count 0 2006.285.10:25:53.25#ibcon#read 5, iclass 19, count 0 2006.285.10:25:53.25#ibcon#about to read 6, iclass 19, count 0 2006.285.10:25:53.25#ibcon#read 6, iclass 19, count 0 2006.285.10:25:53.25#ibcon#end of sib2, iclass 19, count 0 2006.285.10:25:53.25#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:25:53.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:25:53.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:25:53.25#ibcon#*before write, iclass 19, count 0 2006.285.10:25:53.25#ibcon#enter sib2, iclass 19, count 0 2006.285.10:25:53.25#ibcon#flushed, iclass 19, count 0 2006.285.10:25:53.25#ibcon#about to write, iclass 19, count 0 2006.285.10:25:53.25#ibcon#wrote, iclass 19, count 0 2006.285.10:25:53.25#ibcon#about to read 3, iclass 19, count 0 2006.285.10:25:53.29#ibcon#read 3, iclass 19, count 0 2006.285.10:25:53.29#ibcon#about to read 4, iclass 19, count 0 2006.285.10:25:53.29#ibcon#read 4, iclass 19, count 0 2006.285.10:25:53.29#ibcon#about to read 5, iclass 19, count 0 2006.285.10:25:53.29#ibcon#read 5, iclass 19, count 0 2006.285.10:25:53.29#ibcon#about to read 6, iclass 19, count 0 2006.285.10:25:53.29#ibcon#read 6, iclass 19, count 0 2006.285.10:25:53.29#ibcon#end of sib2, iclass 19, count 0 2006.285.10:25:53.29#ibcon#*after write, iclass 19, count 0 2006.285.10:25:53.29#ibcon#*before return 0, iclass 19, count 0 2006.285.10:25:53.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:25:53.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:25:53.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:25:53.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:25:53.29$vck44/va=2,6 2006.285.10:25:53.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.10:25:53.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.10:25:53.29#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:53.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:25:53.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:25:53.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:25:53.35#ibcon#enter wrdev, iclass 21, count 2 2006.285.10:25:53.35#ibcon#first serial, iclass 21, count 2 2006.285.10:25:53.35#ibcon#enter sib2, iclass 21, count 2 2006.285.10:25:53.35#ibcon#flushed, iclass 21, count 2 2006.285.10:25:53.35#ibcon#about to write, iclass 21, count 2 2006.285.10:25:53.35#ibcon#wrote, iclass 21, count 2 2006.285.10:25:53.35#ibcon#about to read 3, iclass 21, count 2 2006.285.10:25:53.37#ibcon#read 3, iclass 21, count 2 2006.285.10:25:53.37#ibcon#about to read 4, iclass 21, count 2 2006.285.10:25:53.37#ibcon#read 4, iclass 21, count 2 2006.285.10:25:53.37#ibcon#about to read 5, iclass 21, count 2 2006.285.10:25:53.37#ibcon#read 5, iclass 21, count 2 2006.285.10:25:53.37#ibcon#about to read 6, iclass 21, count 2 2006.285.10:25:53.37#ibcon#read 6, iclass 21, count 2 2006.285.10:25:53.37#ibcon#end of sib2, iclass 21, count 2 2006.285.10:25:53.37#ibcon#*mode == 0, iclass 21, count 2 2006.285.10:25:53.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.10:25:53.37#ibcon#[25=AT02-06\r\n] 2006.285.10:25:53.37#ibcon#*before write, iclass 21, count 2 2006.285.10:25:53.37#ibcon#enter sib2, iclass 21, count 2 2006.285.10:25:53.37#ibcon#flushed, iclass 21, count 2 2006.285.10:25:53.37#ibcon#about to write, iclass 21, count 2 2006.285.10:25:53.37#ibcon#wrote, iclass 21, count 2 2006.285.10:25:53.37#ibcon#about to read 3, iclass 21, count 2 2006.285.10:25:53.40#ibcon#read 3, iclass 21, count 2 2006.285.10:25:53.40#ibcon#about to read 4, iclass 21, count 2 2006.285.10:25:53.40#ibcon#read 4, iclass 21, count 2 2006.285.10:25:53.40#ibcon#about to read 5, iclass 21, count 2 2006.285.10:25:53.40#ibcon#read 5, iclass 21, count 2 2006.285.10:25:53.40#ibcon#about to read 6, iclass 21, count 2 2006.285.10:25:53.40#ibcon#read 6, iclass 21, count 2 2006.285.10:25:53.40#ibcon#end of sib2, iclass 21, count 2 2006.285.10:25:53.40#ibcon#*after write, iclass 21, count 2 2006.285.10:25:53.40#ibcon#*before return 0, iclass 21, count 2 2006.285.10:25:53.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:25:53.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:25:53.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.10:25:53.40#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:53.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:25:53.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:25:53.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:25:53.52#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:25:53.52#ibcon#first serial, iclass 21, count 0 2006.285.10:25:53.52#ibcon#enter sib2, iclass 21, count 0 2006.285.10:25:53.52#ibcon#flushed, iclass 21, count 0 2006.285.10:25:53.52#ibcon#about to write, iclass 21, count 0 2006.285.10:25:53.52#ibcon#wrote, iclass 21, count 0 2006.285.10:25:53.52#ibcon#about to read 3, iclass 21, count 0 2006.285.10:25:53.54#ibcon#read 3, iclass 21, count 0 2006.285.10:25:53.54#ibcon#about to read 4, iclass 21, count 0 2006.285.10:25:53.54#ibcon#read 4, iclass 21, count 0 2006.285.10:25:53.54#ibcon#about to read 5, iclass 21, count 0 2006.285.10:25:53.54#ibcon#read 5, iclass 21, count 0 2006.285.10:25:53.54#ibcon#about to read 6, iclass 21, count 0 2006.285.10:25:53.54#ibcon#read 6, iclass 21, count 0 2006.285.10:25:53.54#ibcon#end of sib2, iclass 21, count 0 2006.285.10:25:53.54#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:25:53.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:25:53.54#ibcon#[25=USB\r\n] 2006.285.10:25:53.54#ibcon#*before write, iclass 21, count 0 2006.285.10:25:53.54#ibcon#enter sib2, iclass 21, count 0 2006.285.10:25:53.54#ibcon#flushed, iclass 21, count 0 2006.285.10:25:53.54#ibcon#about to write, iclass 21, count 0 2006.285.10:25:53.54#ibcon#wrote, iclass 21, count 0 2006.285.10:25:53.54#ibcon#about to read 3, iclass 21, count 0 2006.285.10:25:53.57#ibcon#read 3, iclass 21, count 0 2006.285.10:25:53.57#ibcon#about to read 4, iclass 21, count 0 2006.285.10:25:53.57#ibcon#read 4, iclass 21, count 0 2006.285.10:25:53.57#ibcon#about to read 5, iclass 21, count 0 2006.285.10:25:53.57#ibcon#read 5, iclass 21, count 0 2006.285.10:25:53.57#ibcon#about to read 6, iclass 21, count 0 2006.285.10:25:53.57#ibcon#read 6, iclass 21, count 0 2006.285.10:25:53.57#ibcon#end of sib2, iclass 21, count 0 2006.285.10:25:53.57#ibcon#*after write, iclass 21, count 0 2006.285.10:25:53.57#ibcon#*before return 0, iclass 21, count 0 2006.285.10:25:53.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:25:53.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:25:53.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:25:53.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:25:53.57$vck44/valo=3,564.99 2006.285.10:25:53.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.10:25:53.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.10:25:53.57#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:53.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:25:53.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:25:53.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:25:53.57#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:25:53.57#ibcon#first serial, iclass 23, count 0 2006.285.10:25:53.57#ibcon#enter sib2, iclass 23, count 0 2006.285.10:25:53.57#ibcon#flushed, iclass 23, count 0 2006.285.10:25:53.57#ibcon#about to write, iclass 23, count 0 2006.285.10:25:53.57#ibcon#wrote, iclass 23, count 0 2006.285.10:25:53.57#ibcon#about to read 3, iclass 23, count 0 2006.285.10:25:53.59#ibcon#read 3, iclass 23, count 0 2006.285.10:25:53.59#ibcon#about to read 4, iclass 23, count 0 2006.285.10:25:53.59#ibcon#read 4, iclass 23, count 0 2006.285.10:25:53.59#ibcon#about to read 5, iclass 23, count 0 2006.285.10:25:53.59#ibcon#read 5, iclass 23, count 0 2006.285.10:25:53.59#ibcon#about to read 6, iclass 23, count 0 2006.285.10:25:53.59#ibcon#read 6, iclass 23, count 0 2006.285.10:25:53.59#ibcon#end of sib2, iclass 23, count 0 2006.285.10:25:53.59#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:25:53.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:25:53.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:25:53.59#ibcon#*before write, iclass 23, count 0 2006.285.10:25:53.59#ibcon#enter sib2, iclass 23, count 0 2006.285.10:25:53.59#ibcon#flushed, iclass 23, count 0 2006.285.10:25:53.59#ibcon#about to write, iclass 23, count 0 2006.285.10:25:53.59#ibcon#wrote, iclass 23, count 0 2006.285.10:25:53.59#ibcon#about to read 3, iclass 23, count 0 2006.285.10:25:53.63#ibcon#read 3, iclass 23, count 0 2006.285.10:25:53.63#ibcon#about to read 4, iclass 23, count 0 2006.285.10:25:53.63#ibcon#read 4, iclass 23, count 0 2006.285.10:25:53.63#ibcon#about to read 5, iclass 23, count 0 2006.285.10:25:53.63#ibcon#read 5, iclass 23, count 0 2006.285.10:25:53.63#ibcon#about to read 6, iclass 23, count 0 2006.285.10:25:53.63#ibcon#read 6, iclass 23, count 0 2006.285.10:25:53.63#ibcon#end of sib2, iclass 23, count 0 2006.285.10:25:53.63#ibcon#*after write, iclass 23, count 0 2006.285.10:25:53.63#ibcon#*before return 0, iclass 23, count 0 2006.285.10:25:53.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:25:53.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:25:53.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:25:53.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:25:53.63$vck44/va=3,7 2006.285.10:25:53.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.10:25:53.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.10:25:53.63#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:53.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:25:53.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:25:53.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:25:53.69#ibcon#enter wrdev, iclass 25, count 2 2006.285.10:25:53.69#ibcon#first serial, iclass 25, count 2 2006.285.10:25:53.69#ibcon#enter sib2, iclass 25, count 2 2006.285.10:25:53.69#ibcon#flushed, iclass 25, count 2 2006.285.10:25:53.69#ibcon#about to write, iclass 25, count 2 2006.285.10:25:53.69#ibcon#wrote, iclass 25, count 2 2006.285.10:25:53.69#ibcon#about to read 3, iclass 25, count 2 2006.285.10:25:53.71#ibcon#read 3, iclass 25, count 2 2006.285.10:25:53.71#ibcon#about to read 4, iclass 25, count 2 2006.285.10:25:53.71#ibcon#read 4, iclass 25, count 2 2006.285.10:25:53.71#ibcon#about to read 5, iclass 25, count 2 2006.285.10:25:53.71#ibcon#read 5, iclass 25, count 2 2006.285.10:25:53.71#ibcon#about to read 6, iclass 25, count 2 2006.285.10:25:53.71#ibcon#read 6, iclass 25, count 2 2006.285.10:25:53.71#ibcon#end of sib2, iclass 25, count 2 2006.285.10:25:53.71#ibcon#*mode == 0, iclass 25, count 2 2006.285.10:25:53.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.10:25:53.71#ibcon#[25=AT03-07\r\n] 2006.285.10:25:53.71#ibcon#*before write, iclass 25, count 2 2006.285.10:25:53.71#ibcon#enter sib2, iclass 25, count 2 2006.285.10:25:53.71#ibcon#flushed, iclass 25, count 2 2006.285.10:25:53.71#ibcon#about to write, iclass 25, count 2 2006.285.10:25:53.71#ibcon#wrote, iclass 25, count 2 2006.285.10:25:53.71#ibcon#about to read 3, iclass 25, count 2 2006.285.10:25:53.74#ibcon#read 3, iclass 25, count 2 2006.285.10:25:53.74#ibcon#about to read 4, iclass 25, count 2 2006.285.10:25:53.74#ibcon#read 4, iclass 25, count 2 2006.285.10:25:53.74#ibcon#about to read 5, iclass 25, count 2 2006.285.10:25:53.74#ibcon#read 5, iclass 25, count 2 2006.285.10:25:53.74#ibcon#about to read 6, iclass 25, count 2 2006.285.10:25:53.74#ibcon#read 6, iclass 25, count 2 2006.285.10:25:53.74#ibcon#end of sib2, iclass 25, count 2 2006.285.10:25:53.74#ibcon#*after write, iclass 25, count 2 2006.285.10:25:53.74#ibcon#*before return 0, iclass 25, count 2 2006.285.10:25:53.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:25:53.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:25:53.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.10:25:53.74#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:53.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:25:53.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:25:53.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:25:53.86#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:25:53.86#ibcon#first serial, iclass 25, count 0 2006.285.10:25:53.86#ibcon#enter sib2, iclass 25, count 0 2006.285.10:25:53.86#ibcon#flushed, iclass 25, count 0 2006.285.10:25:53.86#ibcon#about to write, iclass 25, count 0 2006.285.10:25:53.86#ibcon#wrote, iclass 25, count 0 2006.285.10:25:53.86#ibcon#about to read 3, iclass 25, count 0 2006.285.10:25:53.88#ibcon#read 3, iclass 25, count 0 2006.285.10:25:53.88#ibcon#about to read 4, iclass 25, count 0 2006.285.10:25:53.88#ibcon#read 4, iclass 25, count 0 2006.285.10:25:53.88#ibcon#about to read 5, iclass 25, count 0 2006.285.10:25:53.88#ibcon#read 5, iclass 25, count 0 2006.285.10:25:53.88#ibcon#about to read 6, iclass 25, count 0 2006.285.10:25:53.88#ibcon#read 6, iclass 25, count 0 2006.285.10:25:53.88#ibcon#end of sib2, iclass 25, count 0 2006.285.10:25:53.88#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:25:53.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:25:53.88#ibcon#[25=USB\r\n] 2006.285.10:25:53.88#ibcon#*before write, iclass 25, count 0 2006.285.10:25:53.88#ibcon#enter sib2, iclass 25, count 0 2006.285.10:25:53.88#ibcon#flushed, iclass 25, count 0 2006.285.10:25:53.88#ibcon#about to write, iclass 25, count 0 2006.285.10:25:53.88#ibcon#wrote, iclass 25, count 0 2006.285.10:25:53.88#ibcon#about to read 3, iclass 25, count 0 2006.285.10:25:53.91#ibcon#read 3, iclass 25, count 0 2006.285.10:25:53.91#ibcon#about to read 4, iclass 25, count 0 2006.285.10:25:53.91#ibcon#read 4, iclass 25, count 0 2006.285.10:25:53.91#ibcon#about to read 5, iclass 25, count 0 2006.285.10:25:53.91#ibcon#read 5, iclass 25, count 0 2006.285.10:25:53.91#ibcon#about to read 6, iclass 25, count 0 2006.285.10:25:53.91#ibcon#read 6, iclass 25, count 0 2006.285.10:25:53.91#ibcon#end of sib2, iclass 25, count 0 2006.285.10:25:53.91#ibcon#*after write, iclass 25, count 0 2006.285.10:25:53.91#ibcon#*before return 0, iclass 25, count 0 2006.285.10:25:53.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:25:53.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:25:53.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:25:53.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:25:53.91$vck44/valo=4,624.99 2006.285.10:25:53.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.10:25:53.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.10:25:53.91#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:53.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:25:53.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:25:53.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:25:53.91#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:25:53.91#ibcon#first serial, iclass 27, count 0 2006.285.10:25:53.91#ibcon#enter sib2, iclass 27, count 0 2006.285.10:25:53.91#ibcon#flushed, iclass 27, count 0 2006.285.10:25:53.91#ibcon#about to write, iclass 27, count 0 2006.285.10:25:53.91#ibcon#wrote, iclass 27, count 0 2006.285.10:25:53.91#ibcon#about to read 3, iclass 27, count 0 2006.285.10:25:53.93#ibcon#read 3, iclass 27, count 0 2006.285.10:25:53.93#ibcon#about to read 4, iclass 27, count 0 2006.285.10:25:53.93#ibcon#read 4, iclass 27, count 0 2006.285.10:25:53.93#ibcon#about to read 5, iclass 27, count 0 2006.285.10:25:53.93#ibcon#read 5, iclass 27, count 0 2006.285.10:25:53.93#ibcon#about to read 6, iclass 27, count 0 2006.285.10:25:53.93#ibcon#read 6, iclass 27, count 0 2006.285.10:25:53.93#ibcon#end of sib2, iclass 27, count 0 2006.285.10:25:53.93#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:25:53.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:25:53.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:25:53.93#ibcon#*before write, iclass 27, count 0 2006.285.10:25:53.93#ibcon#enter sib2, iclass 27, count 0 2006.285.10:25:53.93#ibcon#flushed, iclass 27, count 0 2006.285.10:25:53.93#ibcon#about to write, iclass 27, count 0 2006.285.10:25:53.93#ibcon#wrote, iclass 27, count 0 2006.285.10:25:53.93#ibcon#about to read 3, iclass 27, count 0 2006.285.10:25:53.97#ibcon#read 3, iclass 27, count 0 2006.285.10:25:53.97#ibcon#about to read 4, iclass 27, count 0 2006.285.10:25:53.97#ibcon#read 4, iclass 27, count 0 2006.285.10:25:53.97#ibcon#about to read 5, iclass 27, count 0 2006.285.10:25:53.97#ibcon#read 5, iclass 27, count 0 2006.285.10:25:53.97#ibcon#about to read 6, iclass 27, count 0 2006.285.10:25:53.97#ibcon#read 6, iclass 27, count 0 2006.285.10:25:53.97#ibcon#end of sib2, iclass 27, count 0 2006.285.10:25:53.97#ibcon#*after write, iclass 27, count 0 2006.285.10:25:53.97#ibcon#*before return 0, iclass 27, count 0 2006.285.10:25:53.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:25:53.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:25:53.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:25:53.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:25:53.97$vck44/va=4,6 2006.285.10:25:53.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.10:25:53.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.10:25:53.97#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:53.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:25:54.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:25:54.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:25:54.03#ibcon#enter wrdev, iclass 29, count 2 2006.285.10:25:54.03#ibcon#first serial, iclass 29, count 2 2006.285.10:25:54.03#ibcon#enter sib2, iclass 29, count 2 2006.285.10:25:54.03#ibcon#flushed, iclass 29, count 2 2006.285.10:25:54.03#ibcon#about to write, iclass 29, count 2 2006.285.10:25:54.03#ibcon#wrote, iclass 29, count 2 2006.285.10:25:54.03#ibcon#about to read 3, iclass 29, count 2 2006.285.10:25:54.05#ibcon#read 3, iclass 29, count 2 2006.285.10:25:54.05#ibcon#about to read 4, iclass 29, count 2 2006.285.10:25:54.05#ibcon#read 4, iclass 29, count 2 2006.285.10:25:54.05#ibcon#about to read 5, iclass 29, count 2 2006.285.10:25:54.05#ibcon#read 5, iclass 29, count 2 2006.285.10:25:54.05#ibcon#about to read 6, iclass 29, count 2 2006.285.10:25:54.05#ibcon#read 6, iclass 29, count 2 2006.285.10:25:54.05#ibcon#end of sib2, iclass 29, count 2 2006.285.10:25:54.05#ibcon#*mode == 0, iclass 29, count 2 2006.285.10:25:54.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.10:25:54.05#ibcon#[25=AT04-06\r\n] 2006.285.10:25:54.05#ibcon#*before write, iclass 29, count 2 2006.285.10:25:54.05#ibcon#enter sib2, iclass 29, count 2 2006.285.10:25:54.05#ibcon#flushed, iclass 29, count 2 2006.285.10:25:54.05#ibcon#about to write, iclass 29, count 2 2006.285.10:25:54.05#ibcon#wrote, iclass 29, count 2 2006.285.10:25:54.05#ibcon#about to read 3, iclass 29, count 2 2006.285.10:25:54.08#ibcon#read 3, iclass 29, count 2 2006.285.10:25:54.08#ibcon#about to read 4, iclass 29, count 2 2006.285.10:25:54.08#ibcon#read 4, iclass 29, count 2 2006.285.10:25:54.08#ibcon#about to read 5, iclass 29, count 2 2006.285.10:25:54.08#ibcon#read 5, iclass 29, count 2 2006.285.10:25:54.08#ibcon#about to read 6, iclass 29, count 2 2006.285.10:25:54.08#ibcon#read 6, iclass 29, count 2 2006.285.10:25:54.08#ibcon#end of sib2, iclass 29, count 2 2006.285.10:25:54.08#ibcon#*after write, iclass 29, count 2 2006.285.10:25:54.08#ibcon#*before return 0, iclass 29, count 2 2006.285.10:25:54.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:25:54.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:25:54.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.10:25:54.08#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:54.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:25:54.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:25:54.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:25:54.20#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:25:54.20#ibcon#first serial, iclass 29, count 0 2006.285.10:25:54.20#ibcon#enter sib2, iclass 29, count 0 2006.285.10:25:54.20#ibcon#flushed, iclass 29, count 0 2006.285.10:25:54.20#ibcon#about to write, iclass 29, count 0 2006.285.10:25:54.20#ibcon#wrote, iclass 29, count 0 2006.285.10:25:54.20#ibcon#about to read 3, iclass 29, count 0 2006.285.10:25:54.22#ibcon#read 3, iclass 29, count 0 2006.285.10:25:54.22#ibcon#about to read 4, iclass 29, count 0 2006.285.10:25:54.22#ibcon#read 4, iclass 29, count 0 2006.285.10:25:54.22#ibcon#about to read 5, iclass 29, count 0 2006.285.10:25:54.22#ibcon#read 5, iclass 29, count 0 2006.285.10:25:54.22#ibcon#about to read 6, iclass 29, count 0 2006.285.10:25:54.22#ibcon#read 6, iclass 29, count 0 2006.285.10:25:54.22#ibcon#end of sib2, iclass 29, count 0 2006.285.10:25:54.22#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:25:54.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:25:54.22#ibcon#[25=USB\r\n] 2006.285.10:25:54.22#ibcon#*before write, iclass 29, count 0 2006.285.10:25:54.22#ibcon#enter sib2, iclass 29, count 0 2006.285.10:25:54.22#ibcon#flushed, iclass 29, count 0 2006.285.10:25:54.22#ibcon#about to write, iclass 29, count 0 2006.285.10:25:54.22#ibcon#wrote, iclass 29, count 0 2006.285.10:25:54.22#ibcon#about to read 3, iclass 29, count 0 2006.285.10:25:54.25#ibcon#read 3, iclass 29, count 0 2006.285.10:25:54.25#ibcon#about to read 4, iclass 29, count 0 2006.285.10:25:54.25#ibcon#read 4, iclass 29, count 0 2006.285.10:25:54.25#ibcon#about to read 5, iclass 29, count 0 2006.285.10:25:54.25#ibcon#read 5, iclass 29, count 0 2006.285.10:25:54.25#ibcon#about to read 6, iclass 29, count 0 2006.285.10:25:54.25#ibcon#read 6, iclass 29, count 0 2006.285.10:25:54.25#ibcon#end of sib2, iclass 29, count 0 2006.285.10:25:54.25#ibcon#*after write, iclass 29, count 0 2006.285.10:25:54.25#ibcon#*before return 0, iclass 29, count 0 2006.285.10:25:54.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:25:54.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:25:54.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:25:54.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:25:54.25$vck44/valo=5,734.99 2006.285.10:25:54.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.10:25:54.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.10:25:54.25#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:54.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:25:54.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:25:54.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:25:54.25#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:25:54.25#ibcon#first serial, iclass 31, count 0 2006.285.10:25:54.25#ibcon#enter sib2, iclass 31, count 0 2006.285.10:25:54.25#ibcon#flushed, iclass 31, count 0 2006.285.10:25:54.25#ibcon#about to write, iclass 31, count 0 2006.285.10:25:54.25#ibcon#wrote, iclass 31, count 0 2006.285.10:25:54.25#ibcon#about to read 3, iclass 31, count 0 2006.285.10:25:54.27#ibcon#read 3, iclass 31, count 0 2006.285.10:25:54.27#ibcon#about to read 4, iclass 31, count 0 2006.285.10:25:54.27#ibcon#read 4, iclass 31, count 0 2006.285.10:25:54.27#ibcon#about to read 5, iclass 31, count 0 2006.285.10:25:54.27#ibcon#read 5, iclass 31, count 0 2006.285.10:25:54.27#ibcon#about to read 6, iclass 31, count 0 2006.285.10:25:54.27#ibcon#read 6, iclass 31, count 0 2006.285.10:25:54.27#ibcon#end of sib2, iclass 31, count 0 2006.285.10:25:54.27#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:25:54.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:25:54.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:25:54.27#ibcon#*before write, iclass 31, count 0 2006.285.10:25:54.27#ibcon#enter sib2, iclass 31, count 0 2006.285.10:25:54.27#ibcon#flushed, iclass 31, count 0 2006.285.10:25:54.27#ibcon#about to write, iclass 31, count 0 2006.285.10:25:54.27#ibcon#wrote, iclass 31, count 0 2006.285.10:25:54.27#ibcon#about to read 3, iclass 31, count 0 2006.285.10:25:54.31#ibcon#read 3, iclass 31, count 0 2006.285.10:25:54.31#ibcon#about to read 4, iclass 31, count 0 2006.285.10:25:54.31#ibcon#read 4, iclass 31, count 0 2006.285.10:25:54.31#ibcon#about to read 5, iclass 31, count 0 2006.285.10:25:54.31#ibcon#read 5, iclass 31, count 0 2006.285.10:25:54.31#ibcon#about to read 6, iclass 31, count 0 2006.285.10:25:54.31#ibcon#read 6, iclass 31, count 0 2006.285.10:25:54.31#ibcon#end of sib2, iclass 31, count 0 2006.285.10:25:54.31#ibcon#*after write, iclass 31, count 0 2006.285.10:25:54.31#ibcon#*before return 0, iclass 31, count 0 2006.285.10:25:54.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:25:54.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:25:54.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:25:54.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:25:54.31$vck44/va=5,3 2006.285.10:25:54.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.10:25:54.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.10:25:54.31#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:54.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:25:54.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:25:54.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:25:54.37#ibcon#enter wrdev, iclass 33, count 2 2006.285.10:25:54.37#ibcon#first serial, iclass 33, count 2 2006.285.10:25:54.37#ibcon#enter sib2, iclass 33, count 2 2006.285.10:25:54.37#ibcon#flushed, iclass 33, count 2 2006.285.10:25:54.37#ibcon#about to write, iclass 33, count 2 2006.285.10:25:54.37#ibcon#wrote, iclass 33, count 2 2006.285.10:25:54.37#ibcon#about to read 3, iclass 33, count 2 2006.285.10:25:54.39#ibcon#read 3, iclass 33, count 2 2006.285.10:25:54.39#ibcon#about to read 4, iclass 33, count 2 2006.285.10:25:54.39#ibcon#read 4, iclass 33, count 2 2006.285.10:25:54.39#ibcon#about to read 5, iclass 33, count 2 2006.285.10:25:54.39#ibcon#read 5, iclass 33, count 2 2006.285.10:25:54.39#ibcon#about to read 6, iclass 33, count 2 2006.285.10:25:54.39#ibcon#read 6, iclass 33, count 2 2006.285.10:25:54.39#ibcon#end of sib2, iclass 33, count 2 2006.285.10:25:54.39#ibcon#*mode == 0, iclass 33, count 2 2006.285.10:25:54.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.10:25:54.39#ibcon#[25=AT05-03\r\n] 2006.285.10:25:54.39#ibcon#*before write, iclass 33, count 2 2006.285.10:25:54.39#ibcon#enter sib2, iclass 33, count 2 2006.285.10:25:54.39#ibcon#flushed, iclass 33, count 2 2006.285.10:25:54.39#ibcon#about to write, iclass 33, count 2 2006.285.10:25:54.39#ibcon#wrote, iclass 33, count 2 2006.285.10:25:54.39#ibcon#about to read 3, iclass 33, count 2 2006.285.10:25:54.42#ibcon#read 3, iclass 33, count 2 2006.285.10:25:54.42#ibcon#about to read 4, iclass 33, count 2 2006.285.10:25:54.42#ibcon#read 4, iclass 33, count 2 2006.285.10:25:54.42#ibcon#about to read 5, iclass 33, count 2 2006.285.10:25:54.42#ibcon#read 5, iclass 33, count 2 2006.285.10:25:54.42#ibcon#about to read 6, iclass 33, count 2 2006.285.10:25:54.42#ibcon#read 6, iclass 33, count 2 2006.285.10:25:54.42#ibcon#end of sib2, iclass 33, count 2 2006.285.10:25:54.42#ibcon#*after write, iclass 33, count 2 2006.285.10:25:54.42#ibcon#*before return 0, iclass 33, count 2 2006.285.10:25:54.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:25:54.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:25:54.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.10:25:54.42#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:54.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:25:54.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:25:54.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:25:54.54#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:25:54.54#ibcon#first serial, iclass 33, count 0 2006.285.10:25:54.54#ibcon#enter sib2, iclass 33, count 0 2006.285.10:25:54.54#ibcon#flushed, iclass 33, count 0 2006.285.10:25:54.54#ibcon#about to write, iclass 33, count 0 2006.285.10:25:54.54#ibcon#wrote, iclass 33, count 0 2006.285.10:25:54.54#ibcon#about to read 3, iclass 33, count 0 2006.285.10:25:54.56#ibcon#read 3, iclass 33, count 0 2006.285.10:25:54.56#ibcon#about to read 4, iclass 33, count 0 2006.285.10:25:54.56#ibcon#read 4, iclass 33, count 0 2006.285.10:25:54.56#ibcon#about to read 5, iclass 33, count 0 2006.285.10:25:54.56#ibcon#read 5, iclass 33, count 0 2006.285.10:25:54.56#ibcon#about to read 6, iclass 33, count 0 2006.285.10:25:54.56#ibcon#read 6, iclass 33, count 0 2006.285.10:25:54.56#ibcon#end of sib2, iclass 33, count 0 2006.285.10:25:54.56#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:25:54.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:25:54.56#ibcon#[25=USB\r\n] 2006.285.10:25:54.56#ibcon#*before write, iclass 33, count 0 2006.285.10:25:54.56#ibcon#enter sib2, iclass 33, count 0 2006.285.10:25:54.56#ibcon#flushed, iclass 33, count 0 2006.285.10:25:54.56#ibcon#about to write, iclass 33, count 0 2006.285.10:25:54.56#ibcon#wrote, iclass 33, count 0 2006.285.10:25:54.56#ibcon#about to read 3, iclass 33, count 0 2006.285.10:25:54.59#ibcon#read 3, iclass 33, count 0 2006.285.10:25:54.59#ibcon#about to read 4, iclass 33, count 0 2006.285.10:25:54.59#ibcon#read 4, iclass 33, count 0 2006.285.10:25:54.59#ibcon#about to read 5, iclass 33, count 0 2006.285.10:25:54.59#ibcon#read 5, iclass 33, count 0 2006.285.10:25:54.59#ibcon#about to read 6, iclass 33, count 0 2006.285.10:25:54.59#ibcon#read 6, iclass 33, count 0 2006.285.10:25:54.59#ibcon#end of sib2, iclass 33, count 0 2006.285.10:25:54.59#ibcon#*after write, iclass 33, count 0 2006.285.10:25:54.59#ibcon#*before return 0, iclass 33, count 0 2006.285.10:25:54.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:25:54.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:25:54.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:25:54.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:25:54.59$vck44/valo=6,814.99 2006.285.10:25:54.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.10:25:54.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.10:25:54.59#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:54.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:25:54.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:25:54.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:25:54.59#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:25:54.59#ibcon#first serial, iclass 35, count 0 2006.285.10:25:54.59#ibcon#enter sib2, iclass 35, count 0 2006.285.10:25:54.59#ibcon#flushed, iclass 35, count 0 2006.285.10:25:54.59#ibcon#about to write, iclass 35, count 0 2006.285.10:25:54.59#ibcon#wrote, iclass 35, count 0 2006.285.10:25:54.59#ibcon#about to read 3, iclass 35, count 0 2006.285.10:25:54.61#ibcon#read 3, iclass 35, count 0 2006.285.10:25:54.61#ibcon#about to read 4, iclass 35, count 0 2006.285.10:25:54.61#ibcon#read 4, iclass 35, count 0 2006.285.10:25:54.61#ibcon#about to read 5, iclass 35, count 0 2006.285.10:25:54.61#ibcon#read 5, iclass 35, count 0 2006.285.10:25:54.61#ibcon#about to read 6, iclass 35, count 0 2006.285.10:25:54.61#ibcon#read 6, iclass 35, count 0 2006.285.10:25:54.61#ibcon#end of sib2, iclass 35, count 0 2006.285.10:25:54.61#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:25:54.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:25:54.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:25:54.61#ibcon#*before write, iclass 35, count 0 2006.285.10:25:54.61#ibcon#enter sib2, iclass 35, count 0 2006.285.10:25:54.61#ibcon#flushed, iclass 35, count 0 2006.285.10:25:54.61#ibcon#about to write, iclass 35, count 0 2006.285.10:25:54.61#ibcon#wrote, iclass 35, count 0 2006.285.10:25:54.61#ibcon#about to read 3, iclass 35, count 0 2006.285.10:25:54.65#ibcon#read 3, iclass 35, count 0 2006.285.10:25:54.65#ibcon#about to read 4, iclass 35, count 0 2006.285.10:25:54.65#ibcon#read 4, iclass 35, count 0 2006.285.10:25:54.65#ibcon#about to read 5, iclass 35, count 0 2006.285.10:25:54.65#ibcon#read 5, iclass 35, count 0 2006.285.10:25:54.65#ibcon#about to read 6, iclass 35, count 0 2006.285.10:25:54.65#ibcon#read 6, iclass 35, count 0 2006.285.10:25:54.65#ibcon#end of sib2, iclass 35, count 0 2006.285.10:25:54.65#ibcon#*after write, iclass 35, count 0 2006.285.10:25:54.65#ibcon#*before return 0, iclass 35, count 0 2006.285.10:25:54.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:25:54.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:25:54.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:25:54.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:25:54.65$vck44/va=6,4 2006.285.10:25:54.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.10:25:54.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.10:25:54.65#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:54.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:25:54.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:25:54.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:25:54.71#ibcon#enter wrdev, iclass 37, count 2 2006.285.10:25:54.71#ibcon#first serial, iclass 37, count 2 2006.285.10:25:54.71#ibcon#enter sib2, iclass 37, count 2 2006.285.10:25:54.71#ibcon#flushed, iclass 37, count 2 2006.285.10:25:54.71#ibcon#about to write, iclass 37, count 2 2006.285.10:25:54.71#ibcon#wrote, iclass 37, count 2 2006.285.10:25:54.71#ibcon#about to read 3, iclass 37, count 2 2006.285.10:25:54.73#ibcon#read 3, iclass 37, count 2 2006.285.10:25:54.73#ibcon#about to read 4, iclass 37, count 2 2006.285.10:25:54.73#ibcon#read 4, iclass 37, count 2 2006.285.10:25:54.73#ibcon#about to read 5, iclass 37, count 2 2006.285.10:25:54.73#ibcon#read 5, iclass 37, count 2 2006.285.10:25:54.73#ibcon#about to read 6, iclass 37, count 2 2006.285.10:25:54.73#ibcon#read 6, iclass 37, count 2 2006.285.10:25:54.73#ibcon#end of sib2, iclass 37, count 2 2006.285.10:25:54.73#ibcon#*mode == 0, iclass 37, count 2 2006.285.10:25:54.73#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.10:25:54.73#ibcon#[25=AT06-04\r\n] 2006.285.10:25:54.73#ibcon#*before write, iclass 37, count 2 2006.285.10:25:54.73#ibcon#enter sib2, iclass 37, count 2 2006.285.10:25:54.73#ibcon#flushed, iclass 37, count 2 2006.285.10:25:54.73#ibcon#about to write, iclass 37, count 2 2006.285.10:25:54.73#ibcon#wrote, iclass 37, count 2 2006.285.10:25:54.73#ibcon#about to read 3, iclass 37, count 2 2006.285.10:25:54.76#ibcon#read 3, iclass 37, count 2 2006.285.10:25:54.76#ibcon#about to read 4, iclass 37, count 2 2006.285.10:25:54.76#ibcon#read 4, iclass 37, count 2 2006.285.10:25:54.76#ibcon#about to read 5, iclass 37, count 2 2006.285.10:25:54.76#ibcon#read 5, iclass 37, count 2 2006.285.10:25:54.76#ibcon#about to read 6, iclass 37, count 2 2006.285.10:25:54.76#ibcon#read 6, iclass 37, count 2 2006.285.10:25:54.76#ibcon#end of sib2, iclass 37, count 2 2006.285.10:25:54.76#ibcon#*after write, iclass 37, count 2 2006.285.10:25:54.76#ibcon#*before return 0, iclass 37, count 2 2006.285.10:25:54.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:25:54.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:25:54.76#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.10:25:54.76#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:54.76#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:25:54.88#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:25:54.88#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:25:54.88#ibcon#enter wrdev, iclass 37, count 0 2006.285.10:25:54.88#ibcon#first serial, iclass 37, count 0 2006.285.10:25:54.88#ibcon#enter sib2, iclass 37, count 0 2006.285.10:25:54.88#ibcon#flushed, iclass 37, count 0 2006.285.10:25:54.88#ibcon#about to write, iclass 37, count 0 2006.285.10:25:54.88#ibcon#wrote, iclass 37, count 0 2006.285.10:25:54.88#ibcon#about to read 3, iclass 37, count 0 2006.285.10:25:54.90#ibcon#read 3, iclass 37, count 0 2006.285.10:25:54.90#ibcon#about to read 4, iclass 37, count 0 2006.285.10:25:54.90#ibcon#read 4, iclass 37, count 0 2006.285.10:25:54.90#ibcon#about to read 5, iclass 37, count 0 2006.285.10:25:54.90#ibcon#read 5, iclass 37, count 0 2006.285.10:25:54.90#ibcon#about to read 6, iclass 37, count 0 2006.285.10:25:54.90#ibcon#read 6, iclass 37, count 0 2006.285.10:25:54.90#ibcon#end of sib2, iclass 37, count 0 2006.285.10:25:54.90#ibcon#*mode == 0, iclass 37, count 0 2006.285.10:25:54.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.10:25:54.90#ibcon#[25=USB\r\n] 2006.285.10:25:54.90#ibcon#*before write, iclass 37, count 0 2006.285.10:25:54.90#ibcon#enter sib2, iclass 37, count 0 2006.285.10:25:54.90#ibcon#flushed, iclass 37, count 0 2006.285.10:25:54.90#ibcon#about to write, iclass 37, count 0 2006.285.10:25:54.90#ibcon#wrote, iclass 37, count 0 2006.285.10:25:54.90#ibcon#about to read 3, iclass 37, count 0 2006.285.10:25:54.93#ibcon#read 3, iclass 37, count 0 2006.285.10:25:54.93#ibcon#about to read 4, iclass 37, count 0 2006.285.10:25:54.93#ibcon#read 4, iclass 37, count 0 2006.285.10:25:54.93#ibcon#about to read 5, iclass 37, count 0 2006.285.10:25:54.93#ibcon#read 5, iclass 37, count 0 2006.285.10:25:54.93#ibcon#about to read 6, iclass 37, count 0 2006.285.10:25:54.93#ibcon#read 6, iclass 37, count 0 2006.285.10:25:54.93#ibcon#end of sib2, iclass 37, count 0 2006.285.10:25:54.93#ibcon#*after write, iclass 37, count 0 2006.285.10:25:54.93#ibcon#*before return 0, iclass 37, count 0 2006.285.10:25:54.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:25:54.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:25:54.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.10:25:54.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.10:25:54.93$vck44/valo=7,864.99 2006.285.10:25:54.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.10:25:54.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.10:25:54.93#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:54.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:25:54.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:25:54.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:25:54.93#ibcon#enter wrdev, iclass 39, count 0 2006.285.10:25:54.93#ibcon#first serial, iclass 39, count 0 2006.285.10:25:54.93#ibcon#enter sib2, iclass 39, count 0 2006.285.10:25:54.93#ibcon#flushed, iclass 39, count 0 2006.285.10:25:54.93#ibcon#about to write, iclass 39, count 0 2006.285.10:25:54.93#ibcon#wrote, iclass 39, count 0 2006.285.10:25:54.93#ibcon#about to read 3, iclass 39, count 0 2006.285.10:25:54.95#ibcon#read 3, iclass 39, count 0 2006.285.10:25:54.95#ibcon#about to read 4, iclass 39, count 0 2006.285.10:25:54.95#ibcon#read 4, iclass 39, count 0 2006.285.10:25:54.95#ibcon#about to read 5, iclass 39, count 0 2006.285.10:25:54.95#ibcon#read 5, iclass 39, count 0 2006.285.10:25:54.95#ibcon#about to read 6, iclass 39, count 0 2006.285.10:25:54.95#ibcon#read 6, iclass 39, count 0 2006.285.10:25:54.95#ibcon#end of sib2, iclass 39, count 0 2006.285.10:25:54.95#ibcon#*mode == 0, iclass 39, count 0 2006.285.10:25:54.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.10:25:54.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:25:54.95#ibcon#*before write, iclass 39, count 0 2006.285.10:25:54.95#ibcon#enter sib2, iclass 39, count 0 2006.285.10:25:54.95#ibcon#flushed, iclass 39, count 0 2006.285.10:25:54.95#ibcon#about to write, iclass 39, count 0 2006.285.10:25:54.95#ibcon#wrote, iclass 39, count 0 2006.285.10:25:54.95#ibcon#about to read 3, iclass 39, count 0 2006.285.10:25:54.99#ibcon#read 3, iclass 39, count 0 2006.285.10:25:54.99#ibcon#about to read 4, iclass 39, count 0 2006.285.10:25:54.99#ibcon#read 4, iclass 39, count 0 2006.285.10:25:54.99#ibcon#about to read 5, iclass 39, count 0 2006.285.10:25:54.99#ibcon#read 5, iclass 39, count 0 2006.285.10:25:54.99#ibcon#about to read 6, iclass 39, count 0 2006.285.10:25:54.99#ibcon#read 6, iclass 39, count 0 2006.285.10:25:54.99#ibcon#end of sib2, iclass 39, count 0 2006.285.10:25:54.99#ibcon#*after write, iclass 39, count 0 2006.285.10:25:54.99#ibcon#*before return 0, iclass 39, count 0 2006.285.10:25:54.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:25:54.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:25:54.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.10:25:54.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.10:25:54.99$vck44/va=7,4 2006.285.10:25:54.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.10:25:54.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.10:25:54.99#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:54.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:25:55.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:25:55.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:25:55.05#ibcon#enter wrdev, iclass 3, count 2 2006.285.10:25:55.05#ibcon#first serial, iclass 3, count 2 2006.285.10:25:55.05#ibcon#enter sib2, iclass 3, count 2 2006.285.10:25:55.05#ibcon#flushed, iclass 3, count 2 2006.285.10:25:55.05#ibcon#about to write, iclass 3, count 2 2006.285.10:25:55.05#ibcon#wrote, iclass 3, count 2 2006.285.10:25:55.05#ibcon#about to read 3, iclass 3, count 2 2006.285.10:25:55.07#ibcon#read 3, iclass 3, count 2 2006.285.10:25:55.07#ibcon#about to read 4, iclass 3, count 2 2006.285.10:25:55.07#ibcon#read 4, iclass 3, count 2 2006.285.10:25:55.07#ibcon#about to read 5, iclass 3, count 2 2006.285.10:25:55.07#ibcon#read 5, iclass 3, count 2 2006.285.10:25:55.07#ibcon#about to read 6, iclass 3, count 2 2006.285.10:25:55.07#ibcon#read 6, iclass 3, count 2 2006.285.10:25:55.07#ibcon#end of sib2, iclass 3, count 2 2006.285.10:25:55.07#ibcon#*mode == 0, iclass 3, count 2 2006.285.10:25:55.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.10:25:55.07#ibcon#[25=AT07-04\r\n] 2006.285.10:25:55.07#ibcon#*before write, iclass 3, count 2 2006.285.10:25:55.07#ibcon#enter sib2, iclass 3, count 2 2006.285.10:25:55.07#ibcon#flushed, iclass 3, count 2 2006.285.10:25:55.07#ibcon#about to write, iclass 3, count 2 2006.285.10:25:55.07#ibcon#wrote, iclass 3, count 2 2006.285.10:25:55.07#ibcon#about to read 3, iclass 3, count 2 2006.285.10:25:55.10#ibcon#read 3, iclass 3, count 2 2006.285.10:25:55.10#ibcon#about to read 4, iclass 3, count 2 2006.285.10:25:55.10#ibcon#read 4, iclass 3, count 2 2006.285.10:25:55.10#ibcon#about to read 5, iclass 3, count 2 2006.285.10:25:55.10#ibcon#read 5, iclass 3, count 2 2006.285.10:25:55.10#ibcon#about to read 6, iclass 3, count 2 2006.285.10:25:55.10#ibcon#read 6, iclass 3, count 2 2006.285.10:25:55.10#ibcon#end of sib2, iclass 3, count 2 2006.285.10:25:55.10#ibcon#*after write, iclass 3, count 2 2006.285.10:25:55.10#ibcon#*before return 0, iclass 3, count 2 2006.285.10:25:55.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:25:55.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:25:55.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.10:25:55.10#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:55.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:25:55.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:25:55.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:25:55.22#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:25:55.22#ibcon#first serial, iclass 3, count 0 2006.285.10:25:55.22#ibcon#enter sib2, iclass 3, count 0 2006.285.10:25:55.22#ibcon#flushed, iclass 3, count 0 2006.285.10:25:55.22#ibcon#about to write, iclass 3, count 0 2006.285.10:25:55.22#ibcon#wrote, iclass 3, count 0 2006.285.10:25:55.22#ibcon#about to read 3, iclass 3, count 0 2006.285.10:25:55.24#ibcon#read 3, iclass 3, count 0 2006.285.10:25:55.24#ibcon#about to read 4, iclass 3, count 0 2006.285.10:25:55.24#ibcon#read 4, iclass 3, count 0 2006.285.10:25:55.24#ibcon#about to read 5, iclass 3, count 0 2006.285.10:25:55.24#ibcon#read 5, iclass 3, count 0 2006.285.10:25:55.24#ibcon#about to read 6, iclass 3, count 0 2006.285.10:25:55.24#ibcon#read 6, iclass 3, count 0 2006.285.10:25:55.24#ibcon#end of sib2, iclass 3, count 0 2006.285.10:25:55.24#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:25:55.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:25:55.24#ibcon#[25=USB\r\n] 2006.285.10:25:55.24#ibcon#*before write, iclass 3, count 0 2006.285.10:25:55.24#ibcon#enter sib2, iclass 3, count 0 2006.285.10:25:55.24#ibcon#flushed, iclass 3, count 0 2006.285.10:25:55.24#ibcon#about to write, iclass 3, count 0 2006.285.10:25:55.24#ibcon#wrote, iclass 3, count 0 2006.285.10:25:55.24#ibcon#about to read 3, iclass 3, count 0 2006.285.10:25:55.27#ibcon#read 3, iclass 3, count 0 2006.285.10:25:55.27#ibcon#about to read 4, iclass 3, count 0 2006.285.10:25:55.27#ibcon#read 4, iclass 3, count 0 2006.285.10:25:55.27#ibcon#about to read 5, iclass 3, count 0 2006.285.10:25:55.27#ibcon#read 5, iclass 3, count 0 2006.285.10:25:55.27#ibcon#about to read 6, iclass 3, count 0 2006.285.10:25:55.27#ibcon#read 6, iclass 3, count 0 2006.285.10:25:55.27#ibcon#end of sib2, iclass 3, count 0 2006.285.10:25:55.27#ibcon#*after write, iclass 3, count 0 2006.285.10:25:55.27#ibcon#*before return 0, iclass 3, count 0 2006.285.10:25:55.27#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:25:55.27#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:25:55.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:25:55.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:25:55.27$vck44/valo=8,884.99 2006.285.10:25:55.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.10:25:55.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.10:25:55.27#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:55.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:25:55.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:25:55.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:25:55.27#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:25:55.27#ibcon#first serial, iclass 5, count 0 2006.285.10:25:55.27#ibcon#enter sib2, iclass 5, count 0 2006.285.10:25:55.27#ibcon#flushed, iclass 5, count 0 2006.285.10:25:55.27#ibcon#about to write, iclass 5, count 0 2006.285.10:25:55.27#ibcon#wrote, iclass 5, count 0 2006.285.10:25:55.27#ibcon#about to read 3, iclass 5, count 0 2006.285.10:25:55.29#ibcon#read 3, iclass 5, count 0 2006.285.10:25:55.29#ibcon#about to read 4, iclass 5, count 0 2006.285.10:25:55.29#ibcon#read 4, iclass 5, count 0 2006.285.10:25:55.29#ibcon#about to read 5, iclass 5, count 0 2006.285.10:25:55.29#ibcon#read 5, iclass 5, count 0 2006.285.10:25:55.29#ibcon#about to read 6, iclass 5, count 0 2006.285.10:25:55.29#ibcon#read 6, iclass 5, count 0 2006.285.10:25:55.29#ibcon#end of sib2, iclass 5, count 0 2006.285.10:25:55.29#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:25:55.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:25:55.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:25:55.29#ibcon#*before write, iclass 5, count 0 2006.285.10:25:55.29#ibcon#enter sib2, iclass 5, count 0 2006.285.10:25:55.29#ibcon#flushed, iclass 5, count 0 2006.285.10:25:55.29#ibcon#about to write, iclass 5, count 0 2006.285.10:25:55.29#ibcon#wrote, iclass 5, count 0 2006.285.10:25:55.29#ibcon#about to read 3, iclass 5, count 0 2006.285.10:25:55.33#ibcon#read 3, iclass 5, count 0 2006.285.10:25:55.33#ibcon#about to read 4, iclass 5, count 0 2006.285.10:25:55.33#ibcon#read 4, iclass 5, count 0 2006.285.10:25:55.33#ibcon#about to read 5, iclass 5, count 0 2006.285.10:25:55.33#ibcon#read 5, iclass 5, count 0 2006.285.10:25:55.33#ibcon#about to read 6, iclass 5, count 0 2006.285.10:25:55.33#ibcon#read 6, iclass 5, count 0 2006.285.10:25:55.33#ibcon#end of sib2, iclass 5, count 0 2006.285.10:25:55.33#ibcon#*after write, iclass 5, count 0 2006.285.10:25:55.33#ibcon#*before return 0, iclass 5, count 0 2006.285.10:25:55.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:25:55.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:25:55.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:25:55.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:25:55.33$vck44/va=8,3 2006.285.10:25:55.33#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.10:25:55.33#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.10:25:55.33#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:55.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:25:55.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:25:55.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:25:55.39#ibcon#enter wrdev, iclass 7, count 2 2006.285.10:25:55.39#ibcon#first serial, iclass 7, count 2 2006.285.10:25:55.39#ibcon#enter sib2, iclass 7, count 2 2006.285.10:25:55.39#ibcon#flushed, iclass 7, count 2 2006.285.10:25:55.39#ibcon#about to write, iclass 7, count 2 2006.285.10:25:55.39#ibcon#wrote, iclass 7, count 2 2006.285.10:25:55.39#ibcon#about to read 3, iclass 7, count 2 2006.285.10:25:55.41#ibcon#read 3, iclass 7, count 2 2006.285.10:25:55.41#ibcon#about to read 4, iclass 7, count 2 2006.285.10:25:55.41#ibcon#read 4, iclass 7, count 2 2006.285.10:25:55.41#ibcon#about to read 5, iclass 7, count 2 2006.285.10:25:55.41#ibcon#read 5, iclass 7, count 2 2006.285.10:25:55.41#ibcon#about to read 6, iclass 7, count 2 2006.285.10:25:55.41#ibcon#read 6, iclass 7, count 2 2006.285.10:25:55.41#ibcon#end of sib2, iclass 7, count 2 2006.285.10:25:55.41#ibcon#*mode == 0, iclass 7, count 2 2006.285.10:25:55.41#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.10:25:55.41#ibcon#[25=AT08-03\r\n] 2006.285.10:25:55.41#ibcon#*before write, iclass 7, count 2 2006.285.10:25:55.41#ibcon#enter sib2, iclass 7, count 2 2006.285.10:25:55.41#ibcon#flushed, iclass 7, count 2 2006.285.10:25:55.41#ibcon#about to write, iclass 7, count 2 2006.285.10:25:55.41#ibcon#wrote, iclass 7, count 2 2006.285.10:25:55.41#ibcon#about to read 3, iclass 7, count 2 2006.285.10:25:55.44#ibcon#read 3, iclass 7, count 2 2006.285.10:25:55.44#ibcon#about to read 4, iclass 7, count 2 2006.285.10:25:55.44#ibcon#read 4, iclass 7, count 2 2006.285.10:25:55.44#ibcon#about to read 5, iclass 7, count 2 2006.285.10:25:55.44#ibcon#read 5, iclass 7, count 2 2006.285.10:25:55.44#ibcon#about to read 6, iclass 7, count 2 2006.285.10:25:55.44#ibcon#read 6, iclass 7, count 2 2006.285.10:25:55.44#ibcon#end of sib2, iclass 7, count 2 2006.285.10:25:55.44#ibcon#*after write, iclass 7, count 2 2006.285.10:25:55.44#ibcon#*before return 0, iclass 7, count 2 2006.285.10:25:55.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:25:55.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:25:55.44#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.10:25:55.44#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:55.44#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:25:55.56#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:25:55.56#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:25:55.56#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:25:55.56#ibcon#first serial, iclass 7, count 0 2006.285.10:25:55.56#ibcon#enter sib2, iclass 7, count 0 2006.285.10:25:55.56#ibcon#flushed, iclass 7, count 0 2006.285.10:25:55.56#ibcon#about to write, iclass 7, count 0 2006.285.10:25:55.56#ibcon#wrote, iclass 7, count 0 2006.285.10:25:55.56#ibcon#about to read 3, iclass 7, count 0 2006.285.10:25:55.58#ibcon#read 3, iclass 7, count 0 2006.285.10:25:55.58#ibcon#about to read 4, iclass 7, count 0 2006.285.10:25:55.58#ibcon#read 4, iclass 7, count 0 2006.285.10:25:55.58#ibcon#about to read 5, iclass 7, count 0 2006.285.10:25:55.58#ibcon#read 5, iclass 7, count 0 2006.285.10:25:55.58#ibcon#about to read 6, iclass 7, count 0 2006.285.10:25:55.58#ibcon#read 6, iclass 7, count 0 2006.285.10:25:55.58#ibcon#end of sib2, iclass 7, count 0 2006.285.10:25:55.58#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:25:55.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:25:55.58#ibcon#[25=USB\r\n] 2006.285.10:25:55.58#ibcon#*before write, iclass 7, count 0 2006.285.10:25:55.58#ibcon#enter sib2, iclass 7, count 0 2006.285.10:25:55.58#ibcon#flushed, iclass 7, count 0 2006.285.10:25:55.58#ibcon#about to write, iclass 7, count 0 2006.285.10:25:55.58#ibcon#wrote, iclass 7, count 0 2006.285.10:25:55.58#ibcon#about to read 3, iclass 7, count 0 2006.285.10:25:55.61#ibcon#read 3, iclass 7, count 0 2006.285.10:25:55.61#ibcon#about to read 4, iclass 7, count 0 2006.285.10:25:55.61#ibcon#read 4, iclass 7, count 0 2006.285.10:25:55.61#ibcon#about to read 5, iclass 7, count 0 2006.285.10:25:55.61#ibcon#read 5, iclass 7, count 0 2006.285.10:25:55.61#ibcon#about to read 6, iclass 7, count 0 2006.285.10:25:55.61#ibcon#read 6, iclass 7, count 0 2006.285.10:25:55.61#ibcon#end of sib2, iclass 7, count 0 2006.285.10:25:55.61#ibcon#*after write, iclass 7, count 0 2006.285.10:25:55.61#ibcon#*before return 0, iclass 7, count 0 2006.285.10:25:55.61#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:25:55.61#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:25:55.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:25:55.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:25:55.61$vck44/vblo=1,629.99 2006.285.10:25:55.61#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.10:25:55.61#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.10:25:55.61#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:55.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:25:55.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:25:55.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:25:55.61#ibcon#enter wrdev, iclass 11, count 0 2006.285.10:25:55.61#ibcon#first serial, iclass 11, count 0 2006.285.10:25:55.61#ibcon#enter sib2, iclass 11, count 0 2006.285.10:25:55.61#ibcon#flushed, iclass 11, count 0 2006.285.10:25:55.61#ibcon#about to write, iclass 11, count 0 2006.285.10:25:55.61#ibcon#wrote, iclass 11, count 0 2006.285.10:25:55.61#ibcon#about to read 3, iclass 11, count 0 2006.285.10:25:55.63#ibcon#read 3, iclass 11, count 0 2006.285.10:25:55.63#ibcon#about to read 4, iclass 11, count 0 2006.285.10:25:55.63#ibcon#read 4, iclass 11, count 0 2006.285.10:25:55.63#ibcon#about to read 5, iclass 11, count 0 2006.285.10:25:55.63#ibcon#read 5, iclass 11, count 0 2006.285.10:25:55.63#ibcon#about to read 6, iclass 11, count 0 2006.285.10:25:55.63#ibcon#read 6, iclass 11, count 0 2006.285.10:25:55.63#ibcon#end of sib2, iclass 11, count 0 2006.285.10:25:55.63#ibcon#*mode == 0, iclass 11, count 0 2006.285.10:25:55.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.10:25:55.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:25:55.63#ibcon#*before write, iclass 11, count 0 2006.285.10:25:55.63#ibcon#enter sib2, iclass 11, count 0 2006.285.10:25:55.63#ibcon#flushed, iclass 11, count 0 2006.285.10:25:55.63#ibcon#about to write, iclass 11, count 0 2006.285.10:25:55.63#ibcon#wrote, iclass 11, count 0 2006.285.10:25:55.63#ibcon#about to read 3, iclass 11, count 0 2006.285.10:25:55.67#ibcon#read 3, iclass 11, count 0 2006.285.10:25:55.67#ibcon#about to read 4, iclass 11, count 0 2006.285.10:25:55.67#ibcon#read 4, iclass 11, count 0 2006.285.10:25:55.67#ibcon#about to read 5, iclass 11, count 0 2006.285.10:25:55.67#ibcon#read 5, iclass 11, count 0 2006.285.10:25:55.67#ibcon#about to read 6, iclass 11, count 0 2006.285.10:25:55.67#ibcon#read 6, iclass 11, count 0 2006.285.10:25:55.67#ibcon#end of sib2, iclass 11, count 0 2006.285.10:25:55.67#ibcon#*after write, iclass 11, count 0 2006.285.10:25:55.67#ibcon#*before return 0, iclass 11, count 0 2006.285.10:25:55.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:25:55.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:25:55.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.10:25:55.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.10:25:55.67$vck44/vb=1,4 2006.285.10:25:55.67#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.10:25:55.67#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.10:25:55.67#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:55.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:25:55.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:25:55.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:25:55.67#ibcon#enter wrdev, iclass 13, count 2 2006.285.10:25:55.67#ibcon#first serial, iclass 13, count 2 2006.285.10:25:55.67#ibcon#enter sib2, iclass 13, count 2 2006.285.10:25:55.67#ibcon#flushed, iclass 13, count 2 2006.285.10:25:55.67#ibcon#about to write, iclass 13, count 2 2006.285.10:25:55.67#ibcon#wrote, iclass 13, count 2 2006.285.10:25:55.67#ibcon#about to read 3, iclass 13, count 2 2006.285.10:25:55.69#ibcon#read 3, iclass 13, count 2 2006.285.10:25:55.69#ibcon#about to read 4, iclass 13, count 2 2006.285.10:25:55.69#ibcon#read 4, iclass 13, count 2 2006.285.10:25:55.69#ibcon#about to read 5, iclass 13, count 2 2006.285.10:25:55.69#ibcon#read 5, iclass 13, count 2 2006.285.10:25:55.69#ibcon#about to read 6, iclass 13, count 2 2006.285.10:25:55.69#ibcon#read 6, iclass 13, count 2 2006.285.10:25:55.69#ibcon#end of sib2, iclass 13, count 2 2006.285.10:25:55.69#ibcon#*mode == 0, iclass 13, count 2 2006.285.10:25:55.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.10:25:55.69#ibcon#[27=AT01-04\r\n] 2006.285.10:25:55.69#ibcon#*before write, iclass 13, count 2 2006.285.10:25:55.69#ibcon#enter sib2, iclass 13, count 2 2006.285.10:25:55.69#ibcon#flushed, iclass 13, count 2 2006.285.10:25:55.69#ibcon#about to write, iclass 13, count 2 2006.285.10:25:55.69#ibcon#wrote, iclass 13, count 2 2006.285.10:25:55.69#ibcon#about to read 3, iclass 13, count 2 2006.285.10:25:55.72#ibcon#read 3, iclass 13, count 2 2006.285.10:25:55.72#ibcon#about to read 4, iclass 13, count 2 2006.285.10:25:55.72#ibcon#read 4, iclass 13, count 2 2006.285.10:25:55.72#ibcon#about to read 5, iclass 13, count 2 2006.285.10:25:55.72#ibcon#read 5, iclass 13, count 2 2006.285.10:25:55.72#ibcon#about to read 6, iclass 13, count 2 2006.285.10:25:55.72#ibcon#read 6, iclass 13, count 2 2006.285.10:25:55.72#ibcon#end of sib2, iclass 13, count 2 2006.285.10:25:55.72#ibcon#*after write, iclass 13, count 2 2006.285.10:25:55.72#ibcon#*before return 0, iclass 13, count 2 2006.285.10:25:55.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:25:55.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:25:55.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.10:25:55.72#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:55.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:25:55.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:25:55.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:25:55.84#ibcon#enter wrdev, iclass 13, count 0 2006.285.10:25:55.84#ibcon#first serial, iclass 13, count 0 2006.285.10:25:55.84#ibcon#enter sib2, iclass 13, count 0 2006.285.10:25:55.84#ibcon#flushed, iclass 13, count 0 2006.285.10:25:55.84#ibcon#about to write, iclass 13, count 0 2006.285.10:25:55.84#ibcon#wrote, iclass 13, count 0 2006.285.10:25:55.84#ibcon#about to read 3, iclass 13, count 0 2006.285.10:25:55.86#ibcon#read 3, iclass 13, count 0 2006.285.10:25:55.86#ibcon#about to read 4, iclass 13, count 0 2006.285.10:25:55.86#ibcon#read 4, iclass 13, count 0 2006.285.10:25:55.86#ibcon#about to read 5, iclass 13, count 0 2006.285.10:25:55.86#ibcon#read 5, iclass 13, count 0 2006.285.10:25:55.86#ibcon#about to read 6, iclass 13, count 0 2006.285.10:25:55.86#ibcon#read 6, iclass 13, count 0 2006.285.10:25:55.86#ibcon#end of sib2, iclass 13, count 0 2006.285.10:25:55.86#ibcon#*mode == 0, iclass 13, count 0 2006.285.10:25:55.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.10:25:55.86#ibcon#[27=USB\r\n] 2006.285.10:25:55.86#ibcon#*before write, iclass 13, count 0 2006.285.10:25:55.86#ibcon#enter sib2, iclass 13, count 0 2006.285.10:25:55.86#ibcon#flushed, iclass 13, count 0 2006.285.10:25:55.86#ibcon#about to write, iclass 13, count 0 2006.285.10:25:55.86#ibcon#wrote, iclass 13, count 0 2006.285.10:25:55.86#ibcon#about to read 3, iclass 13, count 0 2006.285.10:25:55.89#ibcon#read 3, iclass 13, count 0 2006.285.10:25:55.89#ibcon#about to read 4, iclass 13, count 0 2006.285.10:25:55.89#ibcon#read 4, iclass 13, count 0 2006.285.10:25:55.89#ibcon#about to read 5, iclass 13, count 0 2006.285.10:25:55.89#ibcon#read 5, iclass 13, count 0 2006.285.10:25:55.89#ibcon#about to read 6, iclass 13, count 0 2006.285.10:25:55.89#ibcon#read 6, iclass 13, count 0 2006.285.10:25:55.89#ibcon#end of sib2, iclass 13, count 0 2006.285.10:25:55.89#ibcon#*after write, iclass 13, count 0 2006.285.10:25:55.89#ibcon#*before return 0, iclass 13, count 0 2006.285.10:25:55.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:25:55.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:25:55.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.10:25:55.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.10:25:55.89$vck44/vblo=2,634.99 2006.285.10:25:55.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.10:25:55.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.10:25:55.89#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:55.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:25:55.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:25:55.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:25:55.89#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:25:55.89#ibcon#first serial, iclass 15, count 0 2006.285.10:25:55.89#ibcon#enter sib2, iclass 15, count 0 2006.285.10:25:55.89#ibcon#flushed, iclass 15, count 0 2006.285.10:25:55.89#ibcon#about to write, iclass 15, count 0 2006.285.10:25:55.89#ibcon#wrote, iclass 15, count 0 2006.285.10:25:55.89#ibcon#about to read 3, iclass 15, count 0 2006.285.10:25:55.91#ibcon#read 3, iclass 15, count 0 2006.285.10:25:55.91#ibcon#about to read 4, iclass 15, count 0 2006.285.10:25:55.91#ibcon#read 4, iclass 15, count 0 2006.285.10:25:55.91#ibcon#about to read 5, iclass 15, count 0 2006.285.10:25:55.91#ibcon#read 5, iclass 15, count 0 2006.285.10:25:55.91#ibcon#about to read 6, iclass 15, count 0 2006.285.10:25:55.91#ibcon#read 6, iclass 15, count 0 2006.285.10:25:55.91#ibcon#end of sib2, iclass 15, count 0 2006.285.10:25:55.91#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:25:55.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:25:55.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:25:55.91#ibcon#*before write, iclass 15, count 0 2006.285.10:25:55.91#ibcon#enter sib2, iclass 15, count 0 2006.285.10:25:55.91#ibcon#flushed, iclass 15, count 0 2006.285.10:25:55.91#ibcon#about to write, iclass 15, count 0 2006.285.10:25:55.91#ibcon#wrote, iclass 15, count 0 2006.285.10:25:55.91#ibcon#about to read 3, iclass 15, count 0 2006.285.10:25:55.95#ibcon#read 3, iclass 15, count 0 2006.285.10:25:55.95#ibcon#about to read 4, iclass 15, count 0 2006.285.10:25:55.95#ibcon#read 4, iclass 15, count 0 2006.285.10:25:55.95#ibcon#about to read 5, iclass 15, count 0 2006.285.10:25:55.95#ibcon#read 5, iclass 15, count 0 2006.285.10:25:55.95#ibcon#about to read 6, iclass 15, count 0 2006.285.10:25:55.95#ibcon#read 6, iclass 15, count 0 2006.285.10:25:55.95#ibcon#end of sib2, iclass 15, count 0 2006.285.10:25:55.95#ibcon#*after write, iclass 15, count 0 2006.285.10:25:55.95#ibcon#*before return 0, iclass 15, count 0 2006.285.10:25:55.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:25:55.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:25:55.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:25:55.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:25:55.95$vck44/vb=2,5 2006.285.10:25:55.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.10:25:55.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.10:25:55.95#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:55.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:25:56.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:25:56.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:25:56.01#ibcon#enter wrdev, iclass 17, count 2 2006.285.10:25:56.01#ibcon#first serial, iclass 17, count 2 2006.285.10:25:56.01#ibcon#enter sib2, iclass 17, count 2 2006.285.10:25:56.01#ibcon#flushed, iclass 17, count 2 2006.285.10:25:56.01#ibcon#about to write, iclass 17, count 2 2006.285.10:25:56.01#ibcon#wrote, iclass 17, count 2 2006.285.10:25:56.01#ibcon#about to read 3, iclass 17, count 2 2006.285.10:25:56.03#ibcon#read 3, iclass 17, count 2 2006.285.10:25:56.03#ibcon#about to read 4, iclass 17, count 2 2006.285.10:25:56.03#ibcon#read 4, iclass 17, count 2 2006.285.10:25:56.03#ibcon#about to read 5, iclass 17, count 2 2006.285.10:25:56.03#ibcon#read 5, iclass 17, count 2 2006.285.10:25:56.03#ibcon#about to read 6, iclass 17, count 2 2006.285.10:25:56.03#ibcon#read 6, iclass 17, count 2 2006.285.10:25:56.03#ibcon#end of sib2, iclass 17, count 2 2006.285.10:25:56.03#ibcon#*mode == 0, iclass 17, count 2 2006.285.10:25:56.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.10:25:56.03#ibcon#[27=AT02-05\r\n] 2006.285.10:25:56.03#ibcon#*before write, iclass 17, count 2 2006.285.10:25:56.03#ibcon#enter sib2, iclass 17, count 2 2006.285.10:25:56.03#ibcon#flushed, iclass 17, count 2 2006.285.10:25:56.03#ibcon#about to write, iclass 17, count 2 2006.285.10:25:56.03#ibcon#wrote, iclass 17, count 2 2006.285.10:25:56.03#ibcon#about to read 3, iclass 17, count 2 2006.285.10:25:56.06#ibcon#read 3, iclass 17, count 2 2006.285.10:25:56.06#ibcon#about to read 4, iclass 17, count 2 2006.285.10:25:56.06#ibcon#read 4, iclass 17, count 2 2006.285.10:25:56.06#ibcon#about to read 5, iclass 17, count 2 2006.285.10:25:56.06#ibcon#read 5, iclass 17, count 2 2006.285.10:25:56.06#ibcon#about to read 6, iclass 17, count 2 2006.285.10:25:56.06#ibcon#read 6, iclass 17, count 2 2006.285.10:25:56.06#ibcon#end of sib2, iclass 17, count 2 2006.285.10:25:56.06#ibcon#*after write, iclass 17, count 2 2006.285.10:25:56.06#ibcon#*before return 0, iclass 17, count 2 2006.285.10:25:56.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:25:56.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:25:56.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.10:25:56.06#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:56.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:25:56.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:25:56.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:25:56.18#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:25:56.18#ibcon#first serial, iclass 17, count 0 2006.285.10:25:56.18#ibcon#enter sib2, iclass 17, count 0 2006.285.10:25:56.18#ibcon#flushed, iclass 17, count 0 2006.285.10:25:56.18#ibcon#about to write, iclass 17, count 0 2006.285.10:25:56.18#ibcon#wrote, iclass 17, count 0 2006.285.10:25:56.18#ibcon#about to read 3, iclass 17, count 0 2006.285.10:25:56.20#ibcon#read 3, iclass 17, count 0 2006.285.10:25:56.20#ibcon#about to read 4, iclass 17, count 0 2006.285.10:25:56.20#ibcon#read 4, iclass 17, count 0 2006.285.10:25:56.20#ibcon#about to read 5, iclass 17, count 0 2006.285.10:25:56.20#ibcon#read 5, iclass 17, count 0 2006.285.10:25:56.20#ibcon#about to read 6, iclass 17, count 0 2006.285.10:25:56.20#ibcon#read 6, iclass 17, count 0 2006.285.10:25:56.20#ibcon#end of sib2, iclass 17, count 0 2006.285.10:25:56.20#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:25:56.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:25:56.20#ibcon#[27=USB\r\n] 2006.285.10:25:56.20#ibcon#*before write, iclass 17, count 0 2006.285.10:25:56.20#ibcon#enter sib2, iclass 17, count 0 2006.285.10:25:56.20#ibcon#flushed, iclass 17, count 0 2006.285.10:25:56.20#ibcon#about to write, iclass 17, count 0 2006.285.10:25:56.20#ibcon#wrote, iclass 17, count 0 2006.285.10:25:56.20#ibcon#about to read 3, iclass 17, count 0 2006.285.10:25:56.23#ibcon#read 3, iclass 17, count 0 2006.285.10:25:56.23#ibcon#about to read 4, iclass 17, count 0 2006.285.10:25:56.23#ibcon#read 4, iclass 17, count 0 2006.285.10:25:56.23#ibcon#about to read 5, iclass 17, count 0 2006.285.10:25:56.23#ibcon#read 5, iclass 17, count 0 2006.285.10:25:56.23#ibcon#about to read 6, iclass 17, count 0 2006.285.10:25:56.23#ibcon#read 6, iclass 17, count 0 2006.285.10:25:56.23#ibcon#end of sib2, iclass 17, count 0 2006.285.10:25:56.23#ibcon#*after write, iclass 17, count 0 2006.285.10:25:56.23#ibcon#*before return 0, iclass 17, count 0 2006.285.10:25:56.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:25:56.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:25:56.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:25:56.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:25:56.23$vck44/vblo=3,649.99 2006.285.10:25:56.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.10:25:56.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.10:25:56.23#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:56.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:25:56.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:25:56.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:25:56.23#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:25:56.23#ibcon#first serial, iclass 19, count 0 2006.285.10:25:56.23#ibcon#enter sib2, iclass 19, count 0 2006.285.10:25:56.23#ibcon#flushed, iclass 19, count 0 2006.285.10:25:56.23#ibcon#about to write, iclass 19, count 0 2006.285.10:25:56.23#ibcon#wrote, iclass 19, count 0 2006.285.10:25:56.23#ibcon#about to read 3, iclass 19, count 0 2006.285.10:25:56.25#ibcon#read 3, iclass 19, count 0 2006.285.10:25:56.25#ibcon#about to read 4, iclass 19, count 0 2006.285.10:25:56.25#ibcon#read 4, iclass 19, count 0 2006.285.10:25:56.25#ibcon#about to read 5, iclass 19, count 0 2006.285.10:25:56.25#ibcon#read 5, iclass 19, count 0 2006.285.10:25:56.25#ibcon#about to read 6, iclass 19, count 0 2006.285.10:25:56.25#ibcon#read 6, iclass 19, count 0 2006.285.10:25:56.25#ibcon#end of sib2, iclass 19, count 0 2006.285.10:25:56.25#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:25:56.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:25:56.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:25:56.25#ibcon#*before write, iclass 19, count 0 2006.285.10:25:56.25#ibcon#enter sib2, iclass 19, count 0 2006.285.10:25:56.25#ibcon#flushed, iclass 19, count 0 2006.285.10:25:56.25#ibcon#about to write, iclass 19, count 0 2006.285.10:25:56.25#ibcon#wrote, iclass 19, count 0 2006.285.10:25:56.25#ibcon#about to read 3, iclass 19, count 0 2006.285.10:25:56.29#ibcon#read 3, iclass 19, count 0 2006.285.10:25:56.29#ibcon#about to read 4, iclass 19, count 0 2006.285.10:25:56.29#ibcon#read 4, iclass 19, count 0 2006.285.10:25:56.29#ibcon#about to read 5, iclass 19, count 0 2006.285.10:25:56.29#ibcon#read 5, iclass 19, count 0 2006.285.10:25:56.29#ibcon#about to read 6, iclass 19, count 0 2006.285.10:25:56.29#ibcon#read 6, iclass 19, count 0 2006.285.10:25:56.29#ibcon#end of sib2, iclass 19, count 0 2006.285.10:25:56.29#ibcon#*after write, iclass 19, count 0 2006.285.10:25:56.29#ibcon#*before return 0, iclass 19, count 0 2006.285.10:25:56.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:25:56.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:25:56.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:25:56.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:25:56.29$vck44/vb=3,4 2006.285.10:25:56.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.10:25:56.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.10:25:56.29#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:56.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:25:56.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:25:56.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:25:56.35#ibcon#enter wrdev, iclass 21, count 2 2006.285.10:25:56.35#ibcon#first serial, iclass 21, count 2 2006.285.10:25:56.35#ibcon#enter sib2, iclass 21, count 2 2006.285.10:25:56.35#ibcon#flushed, iclass 21, count 2 2006.285.10:25:56.35#ibcon#about to write, iclass 21, count 2 2006.285.10:25:56.35#ibcon#wrote, iclass 21, count 2 2006.285.10:25:56.35#ibcon#about to read 3, iclass 21, count 2 2006.285.10:25:56.37#ibcon#read 3, iclass 21, count 2 2006.285.10:25:56.37#ibcon#about to read 4, iclass 21, count 2 2006.285.10:25:56.37#ibcon#read 4, iclass 21, count 2 2006.285.10:25:56.37#ibcon#about to read 5, iclass 21, count 2 2006.285.10:25:56.37#ibcon#read 5, iclass 21, count 2 2006.285.10:25:56.37#ibcon#about to read 6, iclass 21, count 2 2006.285.10:25:56.37#ibcon#read 6, iclass 21, count 2 2006.285.10:25:56.37#ibcon#end of sib2, iclass 21, count 2 2006.285.10:25:56.37#ibcon#*mode == 0, iclass 21, count 2 2006.285.10:25:56.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.10:25:56.37#ibcon#[27=AT03-04\r\n] 2006.285.10:25:56.37#ibcon#*before write, iclass 21, count 2 2006.285.10:25:56.37#ibcon#enter sib2, iclass 21, count 2 2006.285.10:25:56.37#ibcon#flushed, iclass 21, count 2 2006.285.10:25:56.37#ibcon#about to write, iclass 21, count 2 2006.285.10:25:56.37#ibcon#wrote, iclass 21, count 2 2006.285.10:25:56.37#ibcon#about to read 3, iclass 21, count 2 2006.285.10:25:56.40#ibcon#read 3, iclass 21, count 2 2006.285.10:25:56.40#ibcon#about to read 4, iclass 21, count 2 2006.285.10:25:56.40#ibcon#read 4, iclass 21, count 2 2006.285.10:25:56.40#ibcon#about to read 5, iclass 21, count 2 2006.285.10:25:56.40#ibcon#read 5, iclass 21, count 2 2006.285.10:25:56.40#ibcon#about to read 6, iclass 21, count 2 2006.285.10:25:56.40#ibcon#read 6, iclass 21, count 2 2006.285.10:25:56.40#ibcon#end of sib2, iclass 21, count 2 2006.285.10:25:56.40#ibcon#*after write, iclass 21, count 2 2006.285.10:25:56.40#ibcon#*before return 0, iclass 21, count 2 2006.285.10:25:56.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:25:56.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:25:56.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.10:25:56.40#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:56.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:25:56.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:25:56.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:25:56.52#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:25:56.52#ibcon#first serial, iclass 21, count 0 2006.285.10:25:56.52#ibcon#enter sib2, iclass 21, count 0 2006.285.10:25:56.52#ibcon#flushed, iclass 21, count 0 2006.285.10:25:56.52#ibcon#about to write, iclass 21, count 0 2006.285.10:25:56.52#ibcon#wrote, iclass 21, count 0 2006.285.10:25:56.52#ibcon#about to read 3, iclass 21, count 0 2006.285.10:25:56.54#ibcon#read 3, iclass 21, count 0 2006.285.10:25:56.54#ibcon#about to read 4, iclass 21, count 0 2006.285.10:25:56.54#ibcon#read 4, iclass 21, count 0 2006.285.10:25:56.54#ibcon#about to read 5, iclass 21, count 0 2006.285.10:25:56.54#ibcon#read 5, iclass 21, count 0 2006.285.10:25:56.54#ibcon#about to read 6, iclass 21, count 0 2006.285.10:25:56.54#ibcon#read 6, iclass 21, count 0 2006.285.10:25:56.54#ibcon#end of sib2, iclass 21, count 0 2006.285.10:25:56.54#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:25:56.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:25:56.54#ibcon#[27=USB\r\n] 2006.285.10:25:56.54#ibcon#*before write, iclass 21, count 0 2006.285.10:25:56.54#ibcon#enter sib2, iclass 21, count 0 2006.285.10:25:56.54#ibcon#flushed, iclass 21, count 0 2006.285.10:25:56.54#ibcon#about to write, iclass 21, count 0 2006.285.10:25:56.54#ibcon#wrote, iclass 21, count 0 2006.285.10:25:56.54#ibcon#about to read 3, iclass 21, count 0 2006.285.10:25:56.57#ibcon#read 3, iclass 21, count 0 2006.285.10:25:56.57#ibcon#about to read 4, iclass 21, count 0 2006.285.10:25:56.57#ibcon#read 4, iclass 21, count 0 2006.285.10:25:56.57#ibcon#about to read 5, iclass 21, count 0 2006.285.10:25:56.57#ibcon#read 5, iclass 21, count 0 2006.285.10:25:56.57#ibcon#about to read 6, iclass 21, count 0 2006.285.10:25:56.57#ibcon#read 6, iclass 21, count 0 2006.285.10:25:56.57#ibcon#end of sib2, iclass 21, count 0 2006.285.10:25:56.57#ibcon#*after write, iclass 21, count 0 2006.285.10:25:56.57#ibcon#*before return 0, iclass 21, count 0 2006.285.10:25:56.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:25:56.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:25:56.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:25:56.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:25:56.57$vck44/vblo=4,679.99 2006.285.10:25:56.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.10:25:56.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.10:25:56.57#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:56.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:25:56.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:25:56.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:25:56.57#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:25:56.57#ibcon#first serial, iclass 23, count 0 2006.285.10:25:56.57#ibcon#enter sib2, iclass 23, count 0 2006.285.10:25:56.57#ibcon#flushed, iclass 23, count 0 2006.285.10:25:56.57#ibcon#about to write, iclass 23, count 0 2006.285.10:25:56.57#ibcon#wrote, iclass 23, count 0 2006.285.10:25:56.57#ibcon#about to read 3, iclass 23, count 0 2006.285.10:25:56.59#ibcon#read 3, iclass 23, count 0 2006.285.10:25:56.59#ibcon#about to read 4, iclass 23, count 0 2006.285.10:25:56.59#ibcon#read 4, iclass 23, count 0 2006.285.10:25:56.59#ibcon#about to read 5, iclass 23, count 0 2006.285.10:25:56.59#ibcon#read 5, iclass 23, count 0 2006.285.10:25:56.59#ibcon#about to read 6, iclass 23, count 0 2006.285.10:25:56.59#ibcon#read 6, iclass 23, count 0 2006.285.10:25:56.59#ibcon#end of sib2, iclass 23, count 0 2006.285.10:25:56.59#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:25:56.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:25:56.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:25:56.59#ibcon#*before write, iclass 23, count 0 2006.285.10:25:56.59#ibcon#enter sib2, iclass 23, count 0 2006.285.10:25:56.59#ibcon#flushed, iclass 23, count 0 2006.285.10:25:56.59#ibcon#about to write, iclass 23, count 0 2006.285.10:25:56.59#ibcon#wrote, iclass 23, count 0 2006.285.10:25:56.59#ibcon#about to read 3, iclass 23, count 0 2006.285.10:25:56.63#ibcon#read 3, iclass 23, count 0 2006.285.10:25:56.63#ibcon#about to read 4, iclass 23, count 0 2006.285.10:25:56.63#ibcon#read 4, iclass 23, count 0 2006.285.10:25:56.63#ibcon#about to read 5, iclass 23, count 0 2006.285.10:25:56.63#ibcon#read 5, iclass 23, count 0 2006.285.10:25:56.63#ibcon#about to read 6, iclass 23, count 0 2006.285.10:25:56.63#ibcon#read 6, iclass 23, count 0 2006.285.10:25:56.63#ibcon#end of sib2, iclass 23, count 0 2006.285.10:25:56.63#ibcon#*after write, iclass 23, count 0 2006.285.10:25:56.63#ibcon#*before return 0, iclass 23, count 0 2006.285.10:25:56.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:25:56.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:25:56.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:25:56.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:25:56.63$vck44/vb=4,5 2006.285.10:25:56.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.10:25:56.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.10:25:56.63#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:56.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:25:56.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:25:56.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:25:56.69#ibcon#enter wrdev, iclass 25, count 2 2006.285.10:25:56.69#ibcon#first serial, iclass 25, count 2 2006.285.10:25:56.69#ibcon#enter sib2, iclass 25, count 2 2006.285.10:25:56.69#ibcon#flushed, iclass 25, count 2 2006.285.10:25:56.69#ibcon#about to write, iclass 25, count 2 2006.285.10:25:56.69#ibcon#wrote, iclass 25, count 2 2006.285.10:25:56.69#ibcon#about to read 3, iclass 25, count 2 2006.285.10:25:56.71#ibcon#read 3, iclass 25, count 2 2006.285.10:25:56.71#ibcon#about to read 4, iclass 25, count 2 2006.285.10:25:56.71#ibcon#read 4, iclass 25, count 2 2006.285.10:25:56.71#ibcon#about to read 5, iclass 25, count 2 2006.285.10:25:56.71#ibcon#read 5, iclass 25, count 2 2006.285.10:25:56.71#ibcon#about to read 6, iclass 25, count 2 2006.285.10:25:56.71#ibcon#read 6, iclass 25, count 2 2006.285.10:25:56.71#ibcon#end of sib2, iclass 25, count 2 2006.285.10:25:56.71#ibcon#*mode == 0, iclass 25, count 2 2006.285.10:25:56.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.10:25:56.71#ibcon#[27=AT04-05\r\n] 2006.285.10:25:56.71#ibcon#*before write, iclass 25, count 2 2006.285.10:25:56.71#ibcon#enter sib2, iclass 25, count 2 2006.285.10:25:56.71#ibcon#flushed, iclass 25, count 2 2006.285.10:25:56.71#ibcon#about to write, iclass 25, count 2 2006.285.10:25:56.71#ibcon#wrote, iclass 25, count 2 2006.285.10:25:56.71#ibcon#about to read 3, iclass 25, count 2 2006.285.10:25:56.74#ibcon#read 3, iclass 25, count 2 2006.285.10:25:56.74#ibcon#about to read 4, iclass 25, count 2 2006.285.10:25:56.74#ibcon#read 4, iclass 25, count 2 2006.285.10:25:56.74#ibcon#about to read 5, iclass 25, count 2 2006.285.10:25:56.74#ibcon#read 5, iclass 25, count 2 2006.285.10:25:56.74#ibcon#about to read 6, iclass 25, count 2 2006.285.10:25:56.74#ibcon#read 6, iclass 25, count 2 2006.285.10:25:56.74#ibcon#end of sib2, iclass 25, count 2 2006.285.10:25:56.74#ibcon#*after write, iclass 25, count 2 2006.285.10:25:56.74#ibcon#*before return 0, iclass 25, count 2 2006.285.10:25:56.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:25:56.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:25:56.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.10:25:56.74#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:56.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:25:56.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:25:56.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:25:56.86#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:25:56.86#ibcon#first serial, iclass 25, count 0 2006.285.10:25:56.86#ibcon#enter sib2, iclass 25, count 0 2006.285.10:25:56.86#ibcon#flushed, iclass 25, count 0 2006.285.10:25:56.86#ibcon#about to write, iclass 25, count 0 2006.285.10:25:56.86#ibcon#wrote, iclass 25, count 0 2006.285.10:25:56.86#ibcon#about to read 3, iclass 25, count 0 2006.285.10:25:56.88#ibcon#read 3, iclass 25, count 0 2006.285.10:25:56.88#ibcon#about to read 4, iclass 25, count 0 2006.285.10:25:56.88#ibcon#read 4, iclass 25, count 0 2006.285.10:25:56.88#ibcon#about to read 5, iclass 25, count 0 2006.285.10:25:56.88#ibcon#read 5, iclass 25, count 0 2006.285.10:25:56.88#ibcon#about to read 6, iclass 25, count 0 2006.285.10:25:56.88#ibcon#read 6, iclass 25, count 0 2006.285.10:25:56.88#ibcon#end of sib2, iclass 25, count 0 2006.285.10:25:56.88#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:25:56.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:25:56.88#ibcon#[27=USB\r\n] 2006.285.10:25:56.88#ibcon#*before write, iclass 25, count 0 2006.285.10:25:56.88#ibcon#enter sib2, iclass 25, count 0 2006.285.10:25:56.88#ibcon#flushed, iclass 25, count 0 2006.285.10:25:56.88#ibcon#about to write, iclass 25, count 0 2006.285.10:25:56.88#ibcon#wrote, iclass 25, count 0 2006.285.10:25:56.88#ibcon#about to read 3, iclass 25, count 0 2006.285.10:25:56.91#ibcon#read 3, iclass 25, count 0 2006.285.10:25:56.91#ibcon#about to read 4, iclass 25, count 0 2006.285.10:25:56.91#ibcon#read 4, iclass 25, count 0 2006.285.10:25:56.91#ibcon#about to read 5, iclass 25, count 0 2006.285.10:25:56.91#ibcon#read 5, iclass 25, count 0 2006.285.10:25:56.91#ibcon#about to read 6, iclass 25, count 0 2006.285.10:25:56.91#ibcon#read 6, iclass 25, count 0 2006.285.10:25:56.91#ibcon#end of sib2, iclass 25, count 0 2006.285.10:25:56.91#ibcon#*after write, iclass 25, count 0 2006.285.10:25:56.91#ibcon#*before return 0, iclass 25, count 0 2006.285.10:25:56.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:25:56.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:25:56.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:25:56.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:25:56.91$vck44/vblo=5,709.99 2006.285.10:25:56.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.10:25:56.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.10:25:56.91#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:56.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:25:56.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:25:56.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:25:56.91#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:25:56.91#ibcon#first serial, iclass 27, count 0 2006.285.10:25:56.91#ibcon#enter sib2, iclass 27, count 0 2006.285.10:25:56.91#ibcon#flushed, iclass 27, count 0 2006.285.10:25:56.91#ibcon#about to write, iclass 27, count 0 2006.285.10:25:56.91#ibcon#wrote, iclass 27, count 0 2006.285.10:25:56.91#ibcon#about to read 3, iclass 27, count 0 2006.285.10:25:56.93#ibcon#read 3, iclass 27, count 0 2006.285.10:25:56.93#ibcon#about to read 4, iclass 27, count 0 2006.285.10:25:56.93#ibcon#read 4, iclass 27, count 0 2006.285.10:25:56.93#ibcon#about to read 5, iclass 27, count 0 2006.285.10:25:56.93#ibcon#read 5, iclass 27, count 0 2006.285.10:25:56.93#ibcon#about to read 6, iclass 27, count 0 2006.285.10:25:56.93#ibcon#read 6, iclass 27, count 0 2006.285.10:25:56.93#ibcon#end of sib2, iclass 27, count 0 2006.285.10:25:56.93#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:25:56.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:25:56.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:25:56.93#ibcon#*before write, iclass 27, count 0 2006.285.10:25:56.93#ibcon#enter sib2, iclass 27, count 0 2006.285.10:25:56.93#ibcon#flushed, iclass 27, count 0 2006.285.10:25:56.93#ibcon#about to write, iclass 27, count 0 2006.285.10:25:56.93#ibcon#wrote, iclass 27, count 0 2006.285.10:25:56.93#ibcon#about to read 3, iclass 27, count 0 2006.285.10:25:56.97#ibcon#read 3, iclass 27, count 0 2006.285.10:25:56.97#ibcon#about to read 4, iclass 27, count 0 2006.285.10:25:56.97#ibcon#read 4, iclass 27, count 0 2006.285.10:25:56.97#ibcon#about to read 5, iclass 27, count 0 2006.285.10:25:56.97#ibcon#read 5, iclass 27, count 0 2006.285.10:25:56.97#ibcon#about to read 6, iclass 27, count 0 2006.285.10:25:56.97#ibcon#read 6, iclass 27, count 0 2006.285.10:25:56.97#ibcon#end of sib2, iclass 27, count 0 2006.285.10:25:56.97#ibcon#*after write, iclass 27, count 0 2006.285.10:25:56.97#ibcon#*before return 0, iclass 27, count 0 2006.285.10:25:56.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:25:56.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:25:56.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:25:56.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:25:56.97$vck44/vb=5,4 2006.285.10:25:56.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.10:25:56.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.10:25:56.97#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:56.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:25:57.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:25:57.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:25:57.03#ibcon#enter wrdev, iclass 29, count 2 2006.285.10:25:57.03#ibcon#first serial, iclass 29, count 2 2006.285.10:25:57.03#ibcon#enter sib2, iclass 29, count 2 2006.285.10:25:57.03#ibcon#flushed, iclass 29, count 2 2006.285.10:25:57.03#ibcon#about to write, iclass 29, count 2 2006.285.10:25:57.03#ibcon#wrote, iclass 29, count 2 2006.285.10:25:57.03#ibcon#about to read 3, iclass 29, count 2 2006.285.10:25:57.05#ibcon#read 3, iclass 29, count 2 2006.285.10:25:57.05#ibcon#about to read 4, iclass 29, count 2 2006.285.10:25:57.05#ibcon#read 4, iclass 29, count 2 2006.285.10:25:57.05#ibcon#about to read 5, iclass 29, count 2 2006.285.10:25:57.05#ibcon#read 5, iclass 29, count 2 2006.285.10:25:57.05#ibcon#about to read 6, iclass 29, count 2 2006.285.10:25:57.05#ibcon#read 6, iclass 29, count 2 2006.285.10:25:57.05#ibcon#end of sib2, iclass 29, count 2 2006.285.10:25:57.05#ibcon#*mode == 0, iclass 29, count 2 2006.285.10:25:57.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.10:25:57.05#ibcon#[27=AT05-04\r\n] 2006.285.10:25:57.05#ibcon#*before write, iclass 29, count 2 2006.285.10:25:57.05#ibcon#enter sib2, iclass 29, count 2 2006.285.10:25:57.05#ibcon#flushed, iclass 29, count 2 2006.285.10:25:57.05#ibcon#about to write, iclass 29, count 2 2006.285.10:25:57.05#ibcon#wrote, iclass 29, count 2 2006.285.10:25:57.05#ibcon#about to read 3, iclass 29, count 2 2006.285.10:25:57.08#ibcon#read 3, iclass 29, count 2 2006.285.10:25:57.08#ibcon#about to read 4, iclass 29, count 2 2006.285.10:25:57.08#ibcon#read 4, iclass 29, count 2 2006.285.10:25:57.08#ibcon#about to read 5, iclass 29, count 2 2006.285.10:25:57.08#ibcon#read 5, iclass 29, count 2 2006.285.10:25:57.08#ibcon#about to read 6, iclass 29, count 2 2006.285.10:25:57.08#ibcon#read 6, iclass 29, count 2 2006.285.10:25:57.08#ibcon#end of sib2, iclass 29, count 2 2006.285.10:25:57.08#ibcon#*after write, iclass 29, count 2 2006.285.10:25:57.08#ibcon#*before return 0, iclass 29, count 2 2006.285.10:25:57.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:25:57.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:25:57.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.10:25:57.08#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:57.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:25:57.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:25:57.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:25:57.20#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:25:57.20#ibcon#first serial, iclass 29, count 0 2006.285.10:25:57.20#ibcon#enter sib2, iclass 29, count 0 2006.285.10:25:57.20#ibcon#flushed, iclass 29, count 0 2006.285.10:25:57.20#ibcon#about to write, iclass 29, count 0 2006.285.10:25:57.20#ibcon#wrote, iclass 29, count 0 2006.285.10:25:57.20#ibcon#about to read 3, iclass 29, count 0 2006.285.10:25:57.22#ibcon#read 3, iclass 29, count 0 2006.285.10:25:57.22#ibcon#about to read 4, iclass 29, count 0 2006.285.10:25:57.22#ibcon#read 4, iclass 29, count 0 2006.285.10:25:57.22#ibcon#about to read 5, iclass 29, count 0 2006.285.10:25:57.22#ibcon#read 5, iclass 29, count 0 2006.285.10:25:57.22#ibcon#about to read 6, iclass 29, count 0 2006.285.10:25:57.22#ibcon#read 6, iclass 29, count 0 2006.285.10:25:57.22#ibcon#end of sib2, iclass 29, count 0 2006.285.10:25:57.22#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:25:57.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:25:57.22#ibcon#[27=USB\r\n] 2006.285.10:25:57.22#ibcon#*before write, iclass 29, count 0 2006.285.10:25:57.22#ibcon#enter sib2, iclass 29, count 0 2006.285.10:25:57.22#ibcon#flushed, iclass 29, count 0 2006.285.10:25:57.22#ibcon#about to write, iclass 29, count 0 2006.285.10:25:57.22#ibcon#wrote, iclass 29, count 0 2006.285.10:25:57.22#ibcon#about to read 3, iclass 29, count 0 2006.285.10:25:57.25#ibcon#read 3, iclass 29, count 0 2006.285.10:25:57.25#ibcon#about to read 4, iclass 29, count 0 2006.285.10:25:57.25#ibcon#read 4, iclass 29, count 0 2006.285.10:25:57.25#ibcon#about to read 5, iclass 29, count 0 2006.285.10:25:57.25#ibcon#read 5, iclass 29, count 0 2006.285.10:25:57.25#ibcon#about to read 6, iclass 29, count 0 2006.285.10:25:57.25#ibcon#read 6, iclass 29, count 0 2006.285.10:25:57.25#ibcon#end of sib2, iclass 29, count 0 2006.285.10:25:57.25#ibcon#*after write, iclass 29, count 0 2006.285.10:25:57.25#ibcon#*before return 0, iclass 29, count 0 2006.285.10:25:57.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:25:57.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:25:57.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:25:57.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:25:57.25$vck44/vblo=6,719.99 2006.285.10:25:57.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.10:25:57.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.10:25:57.25#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:57.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:25:57.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:25:57.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:25:57.25#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:25:57.25#ibcon#first serial, iclass 31, count 0 2006.285.10:25:57.25#ibcon#enter sib2, iclass 31, count 0 2006.285.10:25:57.25#ibcon#flushed, iclass 31, count 0 2006.285.10:25:57.25#ibcon#about to write, iclass 31, count 0 2006.285.10:25:57.25#ibcon#wrote, iclass 31, count 0 2006.285.10:25:57.25#ibcon#about to read 3, iclass 31, count 0 2006.285.10:25:57.27#ibcon#read 3, iclass 31, count 0 2006.285.10:25:57.27#ibcon#about to read 4, iclass 31, count 0 2006.285.10:25:57.27#ibcon#read 4, iclass 31, count 0 2006.285.10:25:57.27#ibcon#about to read 5, iclass 31, count 0 2006.285.10:25:57.27#ibcon#read 5, iclass 31, count 0 2006.285.10:25:57.27#ibcon#about to read 6, iclass 31, count 0 2006.285.10:25:57.27#ibcon#read 6, iclass 31, count 0 2006.285.10:25:57.27#ibcon#end of sib2, iclass 31, count 0 2006.285.10:25:57.27#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:25:57.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:25:57.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:25:57.27#ibcon#*before write, iclass 31, count 0 2006.285.10:25:57.27#ibcon#enter sib2, iclass 31, count 0 2006.285.10:25:57.27#ibcon#flushed, iclass 31, count 0 2006.285.10:25:57.27#ibcon#about to write, iclass 31, count 0 2006.285.10:25:57.27#ibcon#wrote, iclass 31, count 0 2006.285.10:25:57.27#ibcon#about to read 3, iclass 31, count 0 2006.285.10:25:57.31#ibcon#read 3, iclass 31, count 0 2006.285.10:25:57.31#ibcon#about to read 4, iclass 31, count 0 2006.285.10:25:57.31#ibcon#read 4, iclass 31, count 0 2006.285.10:25:57.31#ibcon#about to read 5, iclass 31, count 0 2006.285.10:25:57.31#ibcon#read 5, iclass 31, count 0 2006.285.10:25:57.31#ibcon#about to read 6, iclass 31, count 0 2006.285.10:25:57.31#ibcon#read 6, iclass 31, count 0 2006.285.10:25:57.31#ibcon#end of sib2, iclass 31, count 0 2006.285.10:25:57.31#ibcon#*after write, iclass 31, count 0 2006.285.10:25:57.31#ibcon#*before return 0, iclass 31, count 0 2006.285.10:25:57.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:25:57.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:25:57.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:25:57.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:25:57.31$vck44/vb=6,3 2006.285.10:25:57.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.10:25:57.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.10:25:57.31#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:57.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:25:57.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:25:57.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:25:57.37#ibcon#enter wrdev, iclass 33, count 2 2006.285.10:25:57.37#ibcon#first serial, iclass 33, count 2 2006.285.10:25:57.37#ibcon#enter sib2, iclass 33, count 2 2006.285.10:25:57.37#ibcon#flushed, iclass 33, count 2 2006.285.10:25:57.37#ibcon#about to write, iclass 33, count 2 2006.285.10:25:57.37#ibcon#wrote, iclass 33, count 2 2006.285.10:25:57.37#ibcon#about to read 3, iclass 33, count 2 2006.285.10:25:57.39#ibcon#read 3, iclass 33, count 2 2006.285.10:25:57.39#ibcon#about to read 4, iclass 33, count 2 2006.285.10:25:57.39#ibcon#read 4, iclass 33, count 2 2006.285.10:25:57.39#ibcon#about to read 5, iclass 33, count 2 2006.285.10:25:57.39#ibcon#read 5, iclass 33, count 2 2006.285.10:25:57.39#ibcon#about to read 6, iclass 33, count 2 2006.285.10:25:57.39#ibcon#read 6, iclass 33, count 2 2006.285.10:25:57.39#ibcon#end of sib2, iclass 33, count 2 2006.285.10:25:57.39#ibcon#*mode == 0, iclass 33, count 2 2006.285.10:25:57.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.10:25:57.39#ibcon#[27=AT06-03\r\n] 2006.285.10:25:57.39#ibcon#*before write, iclass 33, count 2 2006.285.10:25:57.39#ibcon#enter sib2, iclass 33, count 2 2006.285.10:25:57.39#ibcon#flushed, iclass 33, count 2 2006.285.10:25:57.39#ibcon#about to write, iclass 33, count 2 2006.285.10:25:57.39#ibcon#wrote, iclass 33, count 2 2006.285.10:25:57.39#ibcon#about to read 3, iclass 33, count 2 2006.285.10:25:57.42#ibcon#read 3, iclass 33, count 2 2006.285.10:25:57.42#ibcon#about to read 4, iclass 33, count 2 2006.285.10:25:57.42#ibcon#read 4, iclass 33, count 2 2006.285.10:25:57.42#ibcon#about to read 5, iclass 33, count 2 2006.285.10:25:57.42#ibcon#read 5, iclass 33, count 2 2006.285.10:25:57.42#ibcon#about to read 6, iclass 33, count 2 2006.285.10:25:57.42#ibcon#read 6, iclass 33, count 2 2006.285.10:25:57.42#ibcon#end of sib2, iclass 33, count 2 2006.285.10:25:57.42#ibcon#*after write, iclass 33, count 2 2006.285.10:25:57.42#ibcon#*before return 0, iclass 33, count 2 2006.285.10:25:57.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:25:57.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:25:57.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.10:25:57.42#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:57.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:25:57.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:25:57.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:25:57.54#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:25:57.54#ibcon#first serial, iclass 33, count 0 2006.285.10:25:57.54#ibcon#enter sib2, iclass 33, count 0 2006.285.10:25:57.54#ibcon#flushed, iclass 33, count 0 2006.285.10:25:57.54#ibcon#about to write, iclass 33, count 0 2006.285.10:25:57.54#ibcon#wrote, iclass 33, count 0 2006.285.10:25:57.54#ibcon#about to read 3, iclass 33, count 0 2006.285.10:25:57.56#ibcon#read 3, iclass 33, count 0 2006.285.10:25:57.56#ibcon#about to read 4, iclass 33, count 0 2006.285.10:25:57.56#ibcon#read 4, iclass 33, count 0 2006.285.10:25:57.56#ibcon#about to read 5, iclass 33, count 0 2006.285.10:25:57.56#ibcon#read 5, iclass 33, count 0 2006.285.10:25:57.56#ibcon#about to read 6, iclass 33, count 0 2006.285.10:25:57.56#ibcon#read 6, iclass 33, count 0 2006.285.10:25:57.56#ibcon#end of sib2, iclass 33, count 0 2006.285.10:25:57.56#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:25:57.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:25:57.56#ibcon#[27=USB\r\n] 2006.285.10:25:57.56#ibcon#*before write, iclass 33, count 0 2006.285.10:25:57.56#ibcon#enter sib2, iclass 33, count 0 2006.285.10:25:57.56#ibcon#flushed, iclass 33, count 0 2006.285.10:25:57.56#ibcon#about to write, iclass 33, count 0 2006.285.10:25:57.56#ibcon#wrote, iclass 33, count 0 2006.285.10:25:57.56#ibcon#about to read 3, iclass 33, count 0 2006.285.10:25:57.59#ibcon#read 3, iclass 33, count 0 2006.285.10:25:57.59#ibcon#about to read 4, iclass 33, count 0 2006.285.10:25:57.59#ibcon#read 4, iclass 33, count 0 2006.285.10:25:57.59#ibcon#about to read 5, iclass 33, count 0 2006.285.10:25:57.59#ibcon#read 5, iclass 33, count 0 2006.285.10:25:57.59#ibcon#about to read 6, iclass 33, count 0 2006.285.10:25:57.59#ibcon#read 6, iclass 33, count 0 2006.285.10:25:57.59#ibcon#end of sib2, iclass 33, count 0 2006.285.10:25:57.59#ibcon#*after write, iclass 33, count 0 2006.285.10:25:57.59#ibcon#*before return 0, iclass 33, count 0 2006.285.10:25:57.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:25:57.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:25:57.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:25:57.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:25:57.59$vck44/vblo=7,734.99 2006.285.10:25:57.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.10:25:57.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.10:25:57.59#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:57.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:25:57.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:25:57.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:25:57.59#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:25:57.59#ibcon#first serial, iclass 35, count 0 2006.285.10:25:57.59#ibcon#enter sib2, iclass 35, count 0 2006.285.10:25:57.59#ibcon#flushed, iclass 35, count 0 2006.285.10:25:57.59#ibcon#about to write, iclass 35, count 0 2006.285.10:25:57.59#ibcon#wrote, iclass 35, count 0 2006.285.10:25:57.59#ibcon#about to read 3, iclass 35, count 0 2006.285.10:25:57.61#ibcon#read 3, iclass 35, count 0 2006.285.10:25:57.61#ibcon#about to read 4, iclass 35, count 0 2006.285.10:25:57.61#ibcon#read 4, iclass 35, count 0 2006.285.10:25:57.61#ibcon#about to read 5, iclass 35, count 0 2006.285.10:25:57.61#ibcon#read 5, iclass 35, count 0 2006.285.10:25:57.61#ibcon#about to read 6, iclass 35, count 0 2006.285.10:25:57.61#ibcon#read 6, iclass 35, count 0 2006.285.10:25:57.61#ibcon#end of sib2, iclass 35, count 0 2006.285.10:25:57.61#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:25:57.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:25:57.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:25:57.61#ibcon#*before write, iclass 35, count 0 2006.285.10:25:57.61#ibcon#enter sib2, iclass 35, count 0 2006.285.10:25:57.61#ibcon#flushed, iclass 35, count 0 2006.285.10:25:57.61#ibcon#about to write, iclass 35, count 0 2006.285.10:25:57.61#ibcon#wrote, iclass 35, count 0 2006.285.10:25:57.61#ibcon#about to read 3, iclass 35, count 0 2006.285.10:25:57.65#ibcon#read 3, iclass 35, count 0 2006.285.10:25:57.65#ibcon#about to read 4, iclass 35, count 0 2006.285.10:25:57.65#ibcon#read 4, iclass 35, count 0 2006.285.10:25:57.65#ibcon#about to read 5, iclass 35, count 0 2006.285.10:25:57.65#ibcon#read 5, iclass 35, count 0 2006.285.10:25:57.65#ibcon#about to read 6, iclass 35, count 0 2006.285.10:25:57.65#ibcon#read 6, iclass 35, count 0 2006.285.10:25:57.65#ibcon#end of sib2, iclass 35, count 0 2006.285.10:25:57.65#ibcon#*after write, iclass 35, count 0 2006.285.10:25:57.65#ibcon#*before return 0, iclass 35, count 0 2006.285.10:25:57.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:25:57.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:25:57.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:25:57.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:25:57.65$vck44/vb=7,4 2006.285.10:25:57.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.10:25:57.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.10:25:57.65#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:57.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:25:57.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:25:57.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:25:57.71#ibcon#enter wrdev, iclass 37, count 2 2006.285.10:25:57.71#ibcon#first serial, iclass 37, count 2 2006.285.10:25:57.71#ibcon#enter sib2, iclass 37, count 2 2006.285.10:25:57.71#ibcon#flushed, iclass 37, count 2 2006.285.10:25:57.71#ibcon#about to write, iclass 37, count 2 2006.285.10:25:57.71#ibcon#wrote, iclass 37, count 2 2006.285.10:25:57.71#ibcon#about to read 3, iclass 37, count 2 2006.285.10:25:57.73#ibcon#read 3, iclass 37, count 2 2006.285.10:25:57.73#ibcon#about to read 4, iclass 37, count 2 2006.285.10:25:57.73#ibcon#read 4, iclass 37, count 2 2006.285.10:25:57.73#ibcon#about to read 5, iclass 37, count 2 2006.285.10:25:57.73#ibcon#read 5, iclass 37, count 2 2006.285.10:25:57.73#ibcon#about to read 6, iclass 37, count 2 2006.285.10:25:57.73#ibcon#read 6, iclass 37, count 2 2006.285.10:25:57.73#ibcon#end of sib2, iclass 37, count 2 2006.285.10:25:57.73#ibcon#*mode == 0, iclass 37, count 2 2006.285.10:25:57.73#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.10:25:57.73#ibcon#[27=AT07-04\r\n] 2006.285.10:25:57.73#ibcon#*before write, iclass 37, count 2 2006.285.10:25:57.73#ibcon#enter sib2, iclass 37, count 2 2006.285.10:25:57.73#ibcon#flushed, iclass 37, count 2 2006.285.10:25:57.73#ibcon#about to write, iclass 37, count 2 2006.285.10:25:57.73#ibcon#wrote, iclass 37, count 2 2006.285.10:25:57.73#ibcon#about to read 3, iclass 37, count 2 2006.285.10:25:57.76#ibcon#read 3, iclass 37, count 2 2006.285.10:25:57.76#ibcon#about to read 4, iclass 37, count 2 2006.285.10:25:57.76#ibcon#read 4, iclass 37, count 2 2006.285.10:25:57.76#ibcon#about to read 5, iclass 37, count 2 2006.285.10:25:57.76#ibcon#read 5, iclass 37, count 2 2006.285.10:25:57.76#ibcon#about to read 6, iclass 37, count 2 2006.285.10:25:57.76#ibcon#read 6, iclass 37, count 2 2006.285.10:25:57.76#ibcon#end of sib2, iclass 37, count 2 2006.285.10:25:57.76#ibcon#*after write, iclass 37, count 2 2006.285.10:25:57.76#ibcon#*before return 0, iclass 37, count 2 2006.285.10:25:57.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:25:57.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:25:57.76#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.10:25:57.76#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:57.76#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:25:57.88#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:25:57.88#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:25:57.88#ibcon#enter wrdev, iclass 37, count 0 2006.285.10:25:57.88#ibcon#first serial, iclass 37, count 0 2006.285.10:25:57.88#ibcon#enter sib2, iclass 37, count 0 2006.285.10:25:57.88#ibcon#flushed, iclass 37, count 0 2006.285.10:25:57.88#ibcon#about to write, iclass 37, count 0 2006.285.10:25:57.88#ibcon#wrote, iclass 37, count 0 2006.285.10:25:57.88#ibcon#about to read 3, iclass 37, count 0 2006.285.10:25:57.90#ibcon#read 3, iclass 37, count 0 2006.285.10:25:57.90#ibcon#about to read 4, iclass 37, count 0 2006.285.10:25:57.90#ibcon#read 4, iclass 37, count 0 2006.285.10:25:57.90#ibcon#about to read 5, iclass 37, count 0 2006.285.10:25:57.90#ibcon#read 5, iclass 37, count 0 2006.285.10:25:57.90#ibcon#about to read 6, iclass 37, count 0 2006.285.10:25:57.90#ibcon#read 6, iclass 37, count 0 2006.285.10:25:57.90#ibcon#end of sib2, iclass 37, count 0 2006.285.10:25:57.90#ibcon#*mode == 0, iclass 37, count 0 2006.285.10:25:57.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.10:25:57.90#ibcon#[27=USB\r\n] 2006.285.10:25:57.90#ibcon#*before write, iclass 37, count 0 2006.285.10:25:57.90#ibcon#enter sib2, iclass 37, count 0 2006.285.10:25:57.90#ibcon#flushed, iclass 37, count 0 2006.285.10:25:57.90#ibcon#about to write, iclass 37, count 0 2006.285.10:25:57.90#ibcon#wrote, iclass 37, count 0 2006.285.10:25:57.90#ibcon#about to read 3, iclass 37, count 0 2006.285.10:25:57.93#ibcon#read 3, iclass 37, count 0 2006.285.10:25:57.93#ibcon#about to read 4, iclass 37, count 0 2006.285.10:25:57.93#ibcon#read 4, iclass 37, count 0 2006.285.10:25:57.93#ibcon#about to read 5, iclass 37, count 0 2006.285.10:25:57.93#ibcon#read 5, iclass 37, count 0 2006.285.10:25:57.93#ibcon#about to read 6, iclass 37, count 0 2006.285.10:25:57.93#ibcon#read 6, iclass 37, count 0 2006.285.10:25:57.93#ibcon#end of sib2, iclass 37, count 0 2006.285.10:25:57.93#ibcon#*after write, iclass 37, count 0 2006.285.10:25:57.93#ibcon#*before return 0, iclass 37, count 0 2006.285.10:25:57.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:25:57.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:25:57.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.10:25:57.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.10:25:57.93$vck44/vblo=8,744.99 2006.285.10:25:57.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.10:25:57.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.10:25:57.93#ibcon#ireg 17 cls_cnt 0 2006.285.10:25:57.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:25:57.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:25:57.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:25:57.93#ibcon#enter wrdev, iclass 39, count 0 2006.285.10:25:57.93#ibcon#first serial, iclass 39, count 0 2006.285.10:25:57.93#ibcon#enter sib2, iclass 39, count 0 2006.285.10:25:57.93#ibcon#flushed, iclass 39, count 0 2006.285.10:25:57.93#ibcon#about to write, iclass 39, count 0 2006.285.10:25:57.93#ibcon#wrote, iclass 39, count 0 2006.285.10:25:57.93#ibcon#about to read 3, iclass 39, count 0 2006.285.10:25:57.95#ibcon#read 3, iclass 39, count 0 2006.285.10:25:57.95#ibcon#about to read 4, iclass 39, count 0 2006.285.10:25:57.95#ibcon#read 4, iclass 39, count 0 2006.285.10:25:57.95#ibcon#about to read 5, iclass 39, count 0 2006.285.10:25:57.95#ibcon#read 5, iclass 39, count 0 2006.285.10:25:57.95#ibcon#about to read 6, iclass 39, count 0 2006.285.10:25:57.95#ibcon#read 6, iclass 39, count 0 2006.285.10:25:57.95#ibcon#end of sib2, iclass 39, count 0 2006.285.10:25:57.95#ibcon#*mode == 0, iclass 39, count 0 2006.285.10:25:57.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.10:25:57.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:25:57.95#ibcon#*before write, iclass 39, count 0 2006.285.10:25:57.95#ibcon#enter sib2, iclass 39, count 0 2006.285.10:25:57.95#ibcon#flushed, iclass 39, count 0 2006.285.10:25:57.95#ibcon#about to write, iclass 39, count 0 2006.285.10:25:57.95#ibcon#wrote, iclass 39, count 0 2006.285.10:25:57.95#ibcon#about to read 3, iclass 39, count 0 2006.285.10:25:57.99#ibcon#read 3, iclass 39, count 0 2006.285.10:25:57.99#ibcon#about to read 4, iclass 39, count 0 2006.285.10:25:57.99#ibcon#read 4, iclass 39, count 0 2006.285.10:25:57.99#ibcon#about to read 5, iclass 39, count 0 2006.285.10:25:57.99#ibcon#read 5, iclass 39, count 0 2006.285.10:25:57.99#ibcon#about to read 6, iclass 39, count 0 2006.285.10:25:57.99#ibcon#read 6, iclass 39, count 0 2006.285.10:25:57.99#ibcon#end of sib2, iclass 39, count 0 2006.285.10:25:57.99#ibcon#*after write, iclass 39, count 0 2006.285.10:25:57.99#ibcon#*before return 0, iclass 39, count 0 2006.285.10:25:57.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:25:57.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:25:57.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.10:25:57.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.10:25:57.99$vck44/vb=8,4 2006.285.10:25:57.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.10:25:57.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.10:25:57.99#ibcon#ireg 11 cls_cnt 2 2006.285.10:25:57.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:25:58.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:25:58.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:25:58.05#ibcon#enter wrdev, iclass 3, count 2 2006.285.10:25:58.05#ibcon#first serial, iclass 3, count 2 2006.285.10:25:58.05#ibcon#enter sib2, iclass 3, count 2 2006.285.10:25:58.05#ibcon#flushed, iclass 3, count 2 2006.285.10:25:58.05#ibcon#about to write, iclass 3, count 2 2006.285.10:25:58.05#ibcon#wrote, iclass 3, count 2 2006.285.10:25:58.05#ibcon#about to read 3, iclass 3, count 2 2006.285.10:25:58.07#ibcon#read 3, iclass 3, count 2 2006.285.10:25:58.07#ibcon#about to read 4, iclass 3, count 2 2006.285.10:25:58.07#ibcon#read 4, iclass 3, count 2 2006.285.10:25:58.07#ibcon#about to read 5, iclass 3, count 2 2006.285.10:25:58.07#ibcon#read 5, iclass 3, count 2 2006.285.10:25:58.07#ibcon#about to read 6, iclass 3, count 2 2006.285.10:25:58.07#ibcon#read 6, iclass 3, count 2 2006.285.10:25:58.07#ibcon#end of sib2, iclass 3, count 2 2006.285.10:25:58.07#ibcon#*mode == 0, iclass 3, count 2 2006.285.10:25:58.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.10:25:58.07#ibcon#[27=AT08-04\r\n] 2006.285.10:25:58.07#ibcon#*before write, iclass 3, count 2 2006.285.10:25:58.07#ibcon#enter sib2, iclass 3, count 2 2006.285.10:25:58.07#ibcon#flushed, iclass 3, count 2 2006.285.10:25:58.07#ibcon#about to write, iclass 3, count 2 2006.285.10:25:58.07#ibcon#wrote, iclass 3, count 2 2006.285.10:25:58.07#ibcon#about to read 3, iclass 3, count 2 2006.285.10:25:58.10#ibcon#read 3, iclass 3, count 2 2006.285.10:25:58.10#ibcon#about to read 4, iclass 3, count 2 2006.285.10:25:58.10#ibcon#read 4, iclass 3, count 2 2006.285.10:25:58.10#ibcon#about to read 5, iclass 3, count 2 2006.285.10:25:58.10#ibcon#read 5, iclass 3, count 2 2006.285.10:25:58.10#ibcon#about to read 6, iclass 3, count 2 2006.285.10:25:58.10#ibcon#read 6, iclass 3, count 2 2006.285.10:25:58.10#ibcon#end of sib2, iclass 3, count 2 2006.285.10:25:58.10#ibcon#*after write, iclass 3, count 2 2006.285.10:25:58.10#ibcon#*before return 0, iclass 3, count 2 2006.285.10:25:58.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:25:58.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:25:58.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.10:25:58.10#ibcon#ireg 7 cls_cnt 0 2006.285.10:25:58.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:25:58.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:25:58.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:25:58.22#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:25:58.22#ibcon#first serial, iclass 3, count 0 2006.285.10:25:58.22#ibcon#enter sib2, iclass 3, count 0 2006.285.10:25:58.22#ibcon#flushed, iclass 3, count 0 2006.285.10:25:58.22#ibcon#about to write, iclass 3, count 0 2006.285.10:25:58.22#ibcon#wrote, iclass 3, count 0 2006.285.10:25:58.22#ibcon#about to read 3, iclass 3, count 0 2006.285.10:25:58.24#ibcon#read 3, iclass 3, count 0 2006.285.10:25:58.24#ibcon#about to read 4, iclass 3, count 0 2006.285.10:25:58.24#ibcon#read 4, iclass 3, count 0 2006.285.10:25:58.24#ibcon#about to read 5, iclass 3, count 0 2006.285.10:25:58.24#ibcon#read 5, iclass 3, count 0 2006.285.10:25:58.24#ibcon#about to read 6, iclass 3, count 0 2006.285.10:25:58.24#ibcon#read 6, iclass 3, count 0 2006.285.10:25:58.24#ibcon#end of sib2, iclass 3, count 0 2006.285.10:25:58.24#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:25:58.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:25:58.24#ibcon#[27=USB\r\n] 2006.285.10:25:58.24#ibcon#*before write, iclass 3, count 0 2006.285.10:25:58.24#ibcon#enter sib2, iclass 3, count 0 2006.285.10:25:58.24#ibcon#flushed, iclass 3, count 0 2006.285.10:25:58.24#ibcon#about to write, iclass 3, count 0 2006.285.10:25:58.24#ibcon#wrote, iclass 3, count 0 2006.285.10:25:58.24#ibcon#about to read 3, iclass 3, count 0 2006.285.10:25:58.27#ibcon#read 3, iclass 3, count 0 2006.285.10:25:58.27#ibcon#about to read 4, iclass 3, count 0 2006.285.10:25:58.27#ibcon#read 4, iclass 3, count 0 2006.285.10:25:58.27#ibcon#about to read 5, iclass 3, count 0 2006.285.10:25:58.27#ibcon#read 5, iclass 3, count 0 2006.285.10:25:58.27#ibcon#about to read 6, iclass 3, count 0 2006.285.10:25:58.27#ibcon#read 6, iclass 3, count 0 2006.285.10:25:58.27#ibcon#end of sib2, iclass 3, count 0 2006.285.10:25:58.27#ibcon#*after write, iclass 3, count 0 2006.285.10:25:58.27#ibcon#*before return 0, iclass 3, count 0 2006.285.10:25:58.27#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:25:58.27#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:25:58.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:25:58.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:25:58.27$vck44/vabw=wide 2006.285.10:25:58.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.10:25:58.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.10:25:58.27#ibcon#ireg 8 cls_cnt 0 2006.285.10:25:58.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:25:58.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:25:58.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:25:58.27#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:25:58.27#ibcon#first serial, iclass 5, count 0 2006.285.10:25:58.27#ibcon#enter sib2, iclass 5, count 0 2006.285.10:25:58.27#ibcon#flushed, iclass 5, count 0 2006.285.10:25:58.27#ibcon#about to write, iclass 5, count 0 2006.285.10:25:58.27#ibcon#wrote, iclass 5, count 0 2006.285.10:25:58.27#ibcon#about to read 3, iclass 5, count 0 2006.285.10:25:58.29#ibcon#read 3, iclass 5, count 0 2006.285.10:25:58.29#ibcon#about to read 4, iclass 5, count 0 2006.285.10:25:58.29#ibcon#read 4, iclass 5, count 0 2006.285.10:25:58.29#ibcon#about to read 5, iclass 5, count 0 2006.285.10:25:58.29#ibcon#read 5, iclass 5, count 0 2006.285.10:25:58.29#ibcon#about to read 6, iclass 5, count 0 2006.285.10:25:58.29#ibcon#read 6, iclass 5, count 0 2006.285.10:25:58.29#ibcon#end of sib2, iclass 5, count 0 2006.285.10:25:58.29#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:25:58.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:25:58.29#ibcon#[25=BW32\r\n] 2006.285.10:25:58.29#ibcon#*before write, iclass 5, count 0 2006.285.10:25:58.29#ibcon#enter sib2, iclass 5, count 0 2006.285.10:25:58.29#ibcon#flushed, iclass 5, count 0 2006.285.10:25:58.29#ibcon#about to write, iclass 5, count 0 2006.285.10:25:58.29#ibcon#wrote, iclass 5, count 0 2006.285.10:25:58.29#ibcon#about to read 3, iclass 5, count 0 2006.285.10:25:58.32#ibcon#read 3, iclass 5, count 0 2006.285.10:25:58.32#ibcon#about to read 4, iclass 5, count 0 2006.285.10:25:58.32#ibcon#read 4, iclass 5, count 0 2006.285.10:25:58.32#ibcon#about to read 5, iclass 5, count 0 2006.285.10:25:58.32#ibcon#read 5, iclass 5, count 0 2006.285.10:25:58.32#ibcon#about to read 6, iclass 5, count 0 2006.285.10:25:58.32#ibcon#read 6, iclass 5, count 0 2006.285.10:25:58.32#ibcon#end of sib2, iclass 5, count 0 2006.285.10:25:58.32#ibcon#*after write, iclass 5, count 0 2006.285.10:25:58.32#ibcon#*before return 0, iclass 5, count 0 2006.285.10:25:58.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:25:58.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:25:58.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:25:58.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:25:58.32$vck44/vbbw=wide 2006.285.10:25:58.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.10:25:58.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.10:25:58.32#ibcon#ireg 8 cls_cnt 0 2006.285.10:25:58.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:25:58.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:25:58.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:25:58.39#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:25:58.39#ibcon#first serial, iclass 7, count 0 2006.285.10:25:58.39#ibcon#enter sib2, iclass 7, count 0 2006.285.10:25:58.39#ibcon#flushed, iclass 7, count 0 2006.285.10:25:58.39#ibcon#about to write, iclass 7, count 0 2006.285.10:25:58.39#ibcon#wrote, iclass 7, count 0 2006.285.10:25:58.39#ibcon#about to read 3, iclass 7, count 0 2006.285.10:25:58.41#ibcon#read 3, iclass 7, count 0 2006.285.10:25:58.41#ibcon#about to read 4, iclass 7, count 0 2006.285.10:25:58.41#ibcon#read 4, iclass 7, count 0 2006.285.10:25:58.41#ibcon#about to read 5, iclass 7, count 0 2006.285.10:25:58.41#ibcon#read 5, iclass 7, count 0 2006.285.10:25:58.41#ibcon#about to read 6, iclass 7, count 0 2006.285.10:25:58.41#ibcon#read 6, iclass 7, count 0 2006.285.10:25:58.41#ibcon#end of sib2, iclass 7, count 0 2006.285.10:25:58.41#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:25:58.41#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:25:58.41#ibcon#[27=BW32\r\n] 2006.285.10:25:58.41#ibcon#*before write, iclass 7, count 0 2006.285.10:25:58.41#ibcon#enter sib2, iclass 7, count 0 2006.285.10:25:58.41#ibcon#flushed, iclass 7, count 0 2006.285.10:25:58.41#ibcon#about to write, iclass 7, count 0 2006.285.10:25:58.41#ibcon#wrote, iclass 7, count 0 2006.285.10:25:58.41#ibcon#about to read 3, iclass 7, count 0 2006.285.10:25:58.44#ibcon#read 3, iclass 7, count 0 2006.285.10:25:58.44#ibcon#about to read 4, iclass 7, count 0 2006.285.10:25:58.44#ibcon#read 4, iclass 7, count 0 2006.285.10:25:58.44#ibcon#about to read 5, iclass 7, count 0 2006.285.10:25:58.44#ibcon#read 5, iclass 7, count 0 2006.285.10:25:58.44#ibcon#about to read 6, iclass 7, count 0 2006.285.10:25:58.44#ibcon#read 6, iclass 7, count 0 2006.285.10:25:58.44#ibcon#end of sib2, iclass 7, count 0 2006.285.10:25:58.44#ibcon#*after write, iclass 7, count 0 2006.285.10:25:58.44#ibcon#*before return 0, iclass 7, count 0 2006.285.10:25:58.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:25:58.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:25:58.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:25:58.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:25:58.44$setupk4/ifdk4 2006.285.10:25:58.44$ifdk4/lo= 2006.285.10:25:58.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:25:58.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:25:58.44$ifdk4/patch= 2006.285.10:25:58.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:25:58.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:25:58.44$setupk4/!*+20s 2006.285.10:26:01.75#abcon#<5=/04 1.5 2.5 19.78 901015.0\r\n> 2006.285.10:26:01.77#abcon#{5=INTERFACE CLEAR} 2006.285.10:26:01.83#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:26:11.92#abcon#<5=/04 1.5 2.5 19.78 911015.0\r\n> 2006.285.10:26:11.94#abcon#{5=INTERFACE CLEAR} 2006.285.10:26:12.00#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:26:12.95$setupk4/"tpicd 2006.285.10:26:12.95$setupk4/echo=off 2006.285.10:26:12.95$setupk4/xlog=off 2006.285.10:26:12.95:!2006.285.10:27:15 2006.285.10:26:17.14#trakl#Source acquired 2006.285.10:26:17.14#flagr#flagr/antenna,acquired 2006.285.10:27:15.00:preob 2006.285.10:27:15.14/onsource/TRACKING 2006.285.10:27:15.14:!2006.285.10:27:25 2006.285.10:27:25.00:"tape 2006.285.10:27:25.00:"st=record 2006.285.10:27:25.00:data_valid=on 2006.285.10:27:25.00:midob 2006.285.10:27:26.14/onsource/TRACKING 2006.285.10:27:26.14/wx/19.78,1015.0,91 2006.285.10:27:26.20/cable/+6.4859E-03 2006.285.10:27:27.29/va/01,07,usb,yes,31,34 2006.285.10:27:27.29/va/02,06,usb,yes,31,32 2006.285.10:27:27.29/va/03,07,usb,yes,31,33 2006.285.10:27:27.29/va/04,06,usb,yes,32,34 2006.285.10:27:27.29/va/05,03,usb,yes,32,32 2006.285.10:27:27.29/va/06,04,usb,yes,29,28 2006.285.10:27:27.29/va/07,04,usb,yes,29,30 2006.285.10:27:27.29/va/08,03,usb,yes,30,36 2006.285.10:27:27.52/valo/01,524.99,yes,locked 2006.285.10:27:27.52/valo/02,534.99,yes,locked 2006.285.10:27:27.52/valo/03,564.99,yes,locked 2006.285.10:27:27.52/valo/04,624.99,yes,locked 2006.285.10:27:27.52/valo/05,734.99,yes,locked 2006.285.10:27:27.52/valo/06,814.99,yes,locked 2006.285.10:27:27.52/valo/07,864.99,yes,locked 2006.285.10:27:27.52/valo/08,884.99,yes,locked 2006.285.10:27:28.61/vb/01,04,usb,yes,30,28 2006.285.10:27:28.61/vb/02,05,usb,yes,28,28 2006.285.10:27:28.61/vb/03,04,usb,yes,29,32 2006.285.10:27:28.61/vb/04,05,usb,yes,29,28 2006.285.10:27:28.61/vb/05,04,usb,yes,26,28 2006.285.10:27:28.61/vb/06,03,usb,yes,37,33 2006.285.10:27:28.61/vb/07,04,usb,yes,30,30 2006.285.10:27:28.61/vb/08,04,usb,yes,27,31 2006.285.10:27:28.85/vblo/01,629.99,yes,locked 2006.285.10:27:28.85/vblo/02,634.99,yes,locked 2006.285.10:27:28.85/vblo/03,649.99,yes,locked 2006.285.10:27:28.85/vblo/04,679.99,yes,locked 2006.285.10:27:28.85/vblo/05,709.99,yes,locked 2006.285.10:27:28.85/vblo/06,719.99,yes,locked 2006.285.10:27:28.85/vblo/07,734.99,yes,locked 2006.285.10:27:28.85/vblo/08,744.99,yes,locked 2006.285.10:27:29.00/vabw/8 2006.285.10:27:29.15/vbbw/8 2006.285.10:27:29.27/xfe/off,on,12.0 2006.285.10:27:29.65/ifatt/23,28,28,28 2006.285.10:27:30.08/fmout-gps/S +2.60E-07 2006.285.10:27:30.10:!2006.285.10:28:35 2006.285.10:28:35.01:data_valid=off 2006.285.10:28:35.01:"et 2006.285.10:28:35.01:!+3s 2006.285.10:28:38.02:"tape 2006.285.10:28:38.02:postob 2006.285.10:28:38.23/cable/+6.4868E-03 2006.285.10:28:38.23/wx/19.77,1015.0,91 2006.285.10:28:38.29/fmout-gps/S +2.62E-07 2006.285.10:28:38.29:scan_name=285-1030,jd0610,160 2006.285.10:28:38.29:source=2201+315,220314.98,314538.3,2000.0,cw 2006.285.10:28:40.14#flagr#flagr/antenna,new-source 2006.285.10:28:40.14:checkk5 2006.285.10:28:40.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:28:40.87/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:28:41.30/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:28:41.69/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:28:42.30/chk_obsdata//k5ts1/T2851027??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:28:42.71/chk_obsdata//k5ts2/T2851027??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:28:43.32/chk_obsdata//k5ts3/T2851027??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:28:43.71/chk_obsdata//k5ts4/T2851027??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:28:44.47/k5log//k5ts1_log_newline 2006.285.10:28:45.24/k5log//k5ts2_log_newline 2006.285.10:28:46.19/k5log//k5ts3_log_newline 2006.285.10:28:46.89/k5log//k5ts4_log_newline 2006.285.10:28:46.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:28:46.91:setupk4=1 2006.285.10:28:46.91$setupk4/echo=on 2006.285.10:28:46.91$setupk4/pcalon 2006.285.10:28:46.91$pcalon/"no phase cal control is implemented here 2006.285.10:28:46.91$setupk4/"tpicd=stop 2006.285.10:28:46.91$setupk4/"rec=synch_on 2006.285.10:28:46.91$setupk4/"rec_mode=128 2006.285.10:28:46.91$setupk4/!* 2006.285.10:28:46.91$setupk4/recpk4 2006.285.10:28:46.91$recpk4/recpatch= 2006.285.10:28:46.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:28:46.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:28:46.91$setupk4/vck44 2006.285.10:28:46.91$vck44/valo=1,524.99 2006.285.10:28:46.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.10:28:46.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.10:28:46.91#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:46.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:28:46.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:28:46.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:28:46.91#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:28:46.91#ibcon#first serial, iclass 10, count 0 2006.285.10:28:46.91#ibcon#enter sib2, iclass 10, count 0 2006.285.10:28:46.91#ibcon#flushed, iclass 10, count 0 2006.285.10:28:46.91#ibcon#about to write, iclass 10, count 0 2006.285.10:28:46.91#ibcon#wrote, iclass 10, count 0 2006.285.10:28:46.91#ibcon#about to read 3, iclass 10, count 0 2006.285.10:28:46.93#ibcon#read 3, iclass 10, count 0 2006.285.10:28:46.93#ibcon#about to read 4, iclass 10, count 0 2006.285.10:28:46.93#ibcon#read 4, iclass 10, count 0 2006.285.10:28:46.93#ibcon#about to read 5, iclass 10, count 0 2006.285.10:28:46.93#ibcon#read 5, iclass 10, count 0 2006.285.10:28:46.93#ibcon#about to read 6, iclass 10, count 0 2006.285.10:28:46.93#ibcon#read 6, iclass 10, count 0 2006.285.10:28:46.93#ibcon#end of sib2, iclass 10, count 0 2006.285.10:28:46.93#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:28:46.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:28:46.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:28:46.93#ibcon#*before write, iclass 10, count 0 2006.285.10:28:46.93#ibcon#enter sib2, iclass 10, count 0 2006.285.10:28:46.93#ibcon#flushed, iclass 10, count 0 2006.285.10:28:46.93#ibcon#about to write, iclass 10, count 0 2006.285.10:28:46.93#ibcon#wrote, iclass 10, count 0 2006.285.10:28:46.93#ibcon#about to read 3, iclass 10, count 0 2006.285.10:28:46.98#ibcon#read 3, iclass 10, count 0 2006.285.10:28:46.98#ibcon#about to read 4, iclass 10, count 0 2006.285.10:28:46.98#ibcon#read 4, iclass 10, count 0 2006.285.10:28:46.98#ibcon#about to read 5, iclass 10, count 0 2006.285.10:28:46.98#ibcon#read 5, iclass 10, count 0 2006.285.10:28:46.98#ibcon#about to read 6, iclass 10, count 0 2006.285.10:28:46.98#ibcon#read 6, iclass 10, count 0 2006.285.10:28:46.98#ibcon#end of sib2, iclass 10, count 0 2006.285.10:28:46.98#ibcon#*after write, iclass 10, count 0 2006.285.10:28:46.98#ibcon#*before return 0, iclass 10, count 0 2006.285.10:28:46.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:28:46.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:28:46.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:28:46.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:28:46.98$vck44/va=1,7 2006.285.10:28:46.98#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.10:28:46.98#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.10:28:46.98#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:46.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:28:46.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:28:46.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:28:46.98#ibcon#enter wrdev, iclass 12, count 2 2006.285.10:28:46.98#ibcon#first serial, iclass 12, count 2 2006.285.10:28:46.98#ibcon#enter sib2, iclass 12, count 2 2006.285.10:28:46.98#ibcon#flushed, iclass 12, count 2 2006.285.10:28:46.98#ibcon#about to write, iclass 12, count 2 2006.285.10:28:46.98#ibcon#wrote, iclass 12, count 2 2006.285.10:28:46.98#ibcon#about to read 3, iclass 12, count 2 2006.285.10:28:47.00#ibcon#read 3, iclass 12, count 2 2006.285.10:28:47.00#ibcon#about to read 4, iclass 12, count 2 2006.285.10:28:47.00#ibcon#read 4, iclass 12, count 2 2006.285.10:28:47.00#ibcon#about to read 5, iclass 12, count 2 2006.285.10:28:47.00#ibcon#read 5, iclass 12, count 2 2006.285.10:28:47.00#ibcon#about to read 6, iclass 12, count 2 2006.285.10:28:47.00#ibcon#read 6, iclass 12, count 2 2006.285.10:28:47.00#ibcon#end of sib2, iclass 12, count 2 2006.285.10:28:47.00#ibcon#*mode == 0, iclass 12, count 2 2006.285.10:28:47.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.10:28:47.00#ibcon#[25=AT01-07\r\n] 2006.285.10:28:47.00#ibcon#*before write, iclass 12, count 2 2006.285.10:28:47.00#ibcon#enter sib2, iclass 12, count 2 2006.285.10:28:47.00#ibcon#flushed, iclass 12, count 2 2006.285.10:28:47.00#ibcon#about to write, iclass 12, count 2 2006.285.10:28:47.00#ibcon#wrote, iclass 12, count 2 2006.285.10:28:47.00#ibcon#about to read 3, iclass 12, count 2 2006.285.10:28:47.03#ibcon#read 3, iclass 12, count 2 2006.285.10:28:47.03#ibcon#about to read 4, iclass 12, count 2 2006.285.10:28:47.03#ibcon#read 4, iclass 12, count 2 2006.285.10:28:47.03#ibcon#about to read 5, iclass 12, count 2 2006.285.10:28:47.03#ibcon#read 5, iclass 12, count 2 2006.285.10:28:47.03#ibcon#about to read 6, iclass 12, count 2 2006.285.10:28:47.03#ibcon#read 6, iclass 12, count 2 2006.285.10:28:47.03#ibcon#end of sib2, iclass 12, count 2 2006.285.10:28:47.03#ibcon#*after write, iclass 12, count 2 2006.285.10:28:47.03#ibcon#*before return 0, iclass 12, count 2 2006.285.10:28:47.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:28:47.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:28:47.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.10:28:47.03#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:47.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:28:47.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:28:47.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:28:47.15#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:28:47.15#ibcon#first serial, iclass 12, count 0 2006.285.10:28:47.15#ibcon#enter sib2, iclass 12, count 0 2006.285.10:28:47.15#ibcon#flushed, iclass 12, count 0 2006.285.10:28:47.15#ibcon#about to write, iclass 12, count 0 2006.285.10:28:47.15#ibcon#wrote, iclass 12, count 0 2006.285.10:28:47.15#ibcon#about to read 3, iclass 12, count 0 2006.285.10:28:47.17#ibcon#read 3, iclass 12, count 0 2006.285.10:28:47.17#ibcon#about to read 4, iclass 12, count 0 2006.285.10:28:47.17#ibcon#read 4, iclass 12, count 0 2006.285.10:28:47.17#ibcon#about to read 5, iclass 12, count 0 2006.285.10:28:47.17#ibcon#read 5, iclass 12, count 0 2006.285.10:28:47.17#ibcon#about to read 6, iclass 12, count 0 2006.285.10:28:47.17#ibcon#read 6, iclass 12, count 0 2006.285.10:28:47.17#ibcon#end of sib2, iclass 12, count 0 2006.285.10:28:47.17#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:28:47.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:28:47.17#ibcon#[25=USB\r\n] 2006.285.10:28:47.17#ibcon#*before write, iclass 12, count 0 2006.285.10:28:47.17#ibcon#enter sib2, iclass 12, count 0 2006.285.10:28:47.17#ibcon#flushed, iclass 12, count 0 2006.285.10:28:47.17#ibcon#about to write, iclass 12, count 0 2006.285.10:28:47.17#ibcon#wrote, iclass 12, count 0 2006.285.10:28:47.17#ibcon#about to read 3, iclass 12, count 0 2006.285.10:28:47.20#ibcon#read 3, iclass 12, count 0 2006.285.10:28:47.20#ibcon#about to read 4, iclass 12, count 0 2006.285.10:28:47.20#ibcon#read 4, iclass 12, count 0 2006.285.10:28:47.20#ibcon#about to read 5, iclass 12, count 0 2006.285.10:28:47.20#ibcon#read 5, iclass 12, count 0 2006.285.10:28:47.20#ibcon#about to read 6, iclass 12, count 0 2006.285.10:28:47.20#ibcon#read 6, iclass 12, count 0 2006.285.10:28:47.20#ibcon#end of sib2, iclass 12, count 0 2006.285.10:28:47.20#ibcon#*after write, iclass 12, count 0 2006.285.10:28:47.20#ibcon#*before return 0, iclass 12, count 0 2006.285.10:28:47.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:28:47.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:28:47.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:28:47.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:28:47.20$vck44/valo=2,534.99 2006.285.10:28:47.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.10:28:47.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.10:28:47.20#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:47.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:28:47.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:28:47.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:28:47.20#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:28:47.20#ibcon#first serial, iclass 14, count 0 2006.285.10:28:47.20#ibcon#enter sib2, iclass 14, count 0 2006.285.10:28:47.20#ibcon#flushed, iclass 14, count 0 2006.285.10:28:47.20#ibcon#about to write, iclass 14, count 0 2006.285.10:28:47.20#ibcon#wrote, iclass 14, count 0 2006.285.10:28:47.20#ibcon#about to read 3, iclass 14, count 0 2006.285.10:28:47.22#ibcon#read 3, iclass 14, count 0 2006.285.10:28:47.22#ibcon#about to read 4, iclass 14, count 0 2006.285.10:28:47.22#ibcon#read 4, iclass 14, count 0 2006.285.10:28:47.22#ibcon#about to read 5, iclass 14, count 0 2006.285.10:28:47.22#ibcon#read 5, iclass 14, count 0 2006.285.10:28:47.22#ibcon#about to read 6, iclass 14, count 0 2006.285.10:28:47.22#ibcon#read 6, iclass 14, count 0 2006.285.10:28:47.22#ibcon#end of sib2, iclass 14, count 0 2006.285.10:28:47.22#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:28:47.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:28:47.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:28:47.22#ibcon#*before write, iclass 14, count 0 2006.285.10:28:47.22#ibcon#enter sib2, iclass 14, count 0 2006.285.10:28:47.22#ibcon#flushed, iclass 14, count 0 2006.285.10:28:47.22#ibcon#about to write, iclass 14, count 0 2006.285.10:28:47.22#ibcon#wrote, iclass 14, count 0 2006.285.10:28:47.22#ibcon#about to read 3, iclass 14, count 0 2006.285.10:28:47.26#ibcon#read 3, iclass 14, count 0 2006.285.10:28:47.26#ibcon#about to read 4, iclass 14, count 0 2006.285.10:28:47.26#ibcon#read 4, iclass 14, count 0 2006.285.10:28:47.26#ibcon#about to read 5, iclass 14, count 0 2006.285.10:28:47.26#ibcon#read 5, iclass 14, count 0 2006.285.10:28:47.26#ibcon#about to read 6, iclass 14, count 0 2006.285.10:28:47.26#ibcon#read 6, iclass 14, count 0 2006.285.10:28:47.26#ibcon#end of sib2, iclass 14, count 0 2006.285.10:28:47.26#ibcon#*after write, iclass 14, count 0 2006.285.10:28:47.26#ibcon#*before return 0, iclass 14, count 0 2006.285.10:28:47.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:28:47.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:28:47.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:28:47.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:28:47.26$vck44/va=2,6 2006.285.10:28:47.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.10:28:47.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.10:28:47.26#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:47.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:28:47.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:28:47.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:28:47.32#ibcon#enter wrdev, iclass 16, count 2 2006.285.10:28:47.32#ibcon#first serial, iclass 16, count 2 2006.285.10:28:47.32#ibcon#enter sib2, iclass 16, count 2 2006.285.10:28:47.32#ibcon#flushed, iclass 16, count 2 2006.285.10:28:47.32#ibcon#about to write, iclass 16, count 2 2006.285.10:28:47.32#ibcon#wrote, iclass 16, count 2 2006.285.10:28:47.32#ibcon#about to read 3, iclass 16, count 2 2006.285.10:28:47.34#ibcon#read 3, iclass 16, count 2 2006.285.10:28:47.34#ibcon#about to read 4, iclass 16, count 2 2006.285.10:28:47.34#ibcon#read 4, iclass 16, count 2 2006.285.10:28:47.34#ibcon#about to read 5, iclass 16, count 2 2006.285.10:28:47.34#ibcon#read 5, iclass 16, count 2 2006.285.10:28:47.34#ibcon#about to read 6, iclass 16, count 2 2006.285.10:28:47.34#ibcon#read 6, iclass 16, count 2 2006.285.10:28:47.34#ibcon#end of sib2, iclass 16, count 2 2006.285.10:28:47.34#ibcon#*mode == 0, iclass 16, count 2 2006.285.10:28:47.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.10:28:47.34#ibcon#[25=AT02-06\r\n] 2006.285.10:28:47.34#ibcon#*before write, iclass 16, count 2 2006.285.10:28:47.34#ibcon#enter sib2, iclass 16, count 2 2006.285.10:28:47.34#ibcon#flushed, iclass 16, count 2 2006.285.10:28:47.34#ibcon#about to write, iclass 16, count 2 2006.285.10:28:47.34#ibcon#wrote, iclass 16, count 2 2006.285.10:28:47.34#ibcon#about to read 3, iclass 16, count 2 2006.285.10:28:47.37#ibcon#read 3, iclass 16, count 2 2006.285.10:28:47.37#ibcon#about to read 4, iclass 16, count 2 2006.285.10:28:47.37#ibcon#read 4, iclass 16, count 2 2006.285.10:28:47.37#ibcon#about to read 5, iclass 16, count 2 2006.285.10:28:47.37#ibcon#read 5, iclass 16, count 2 2006.285.10:28:47.37#ibcon#about to read 6, iclass 16, count 2 2006.285.10:28:47.37#ibcon#read 6, iclass 16, count 2 2006.285.10:28:47.37#ibcon#end of sib2, iclass 16, count 2 2006.285.10:28:47.37#ibcon#*after write, iclass 16, count 2 2006.285.10:28:47.37#ibcon#*before return 0, iclass 16, count 2 2006.285.10:28:47.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:28:47.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:28:47.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.10:28:47.37#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:47.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:28:47.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:28:47.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:28:47.49#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:28:47.49#ibcon#first serial, iclass 16, count 0 2006.285.10:28:47.49#ibcon#enter sib2, iclass 16, count 0 2006.285.10:28:47.49#ibcon#flushed, iclass 16, count 0 2006.285.10:28:47.49#ibcon#about to write, iclass 16, count 0 2006.285.10:28:47.49#ibcon#wrote, iclass 16, count 0 2006.285.10:28:47.49#ibcon#about to read 3, iclass 16, count 0 2006.285.10:28:47.51#ibcon#read 3, iclass 16, count 0 2006.285.10:28:47.51#ibcon#about to read 4, iclass 16, count 0 2006.285.10:28:47.51#ibcon#read 4, iclass 16, count 0 2006.285.10:28:47.51#ibcon#about to read 5, iclass 16, count 0 2006.285.10:28:47.51#ibcon#read 5, iclass 16, count 0 2006.285.10:28:47.51#ibcon#about to read 6, iclass 16, count 0 2006.285.10:28:47.51#ibcon#read 6, iclass 16, count 0 2006.285.10:28:47.51#ibcon#end of sib2, iclass 16, count 0 2006.285.10:28:47.51#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:28:47.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:28:47.51#ibcon#[25=USB\r\n] 2006.285.10:28:47.51#ibcon#*before write, iclass 16, count 0 2006.285.10:28:47.51#ibcon#enter sib2, iclass 16, count 0 2006.285.10:28:47.51#ibcon#flushed, iclass 16, count 0 2006.285.10:28:47.51#ibcon#about to write, iclass 16, count 0 2006.285.10:28:47.51#ibcon#wrote, iclass 16, count 0 2006.285.10:28:47.51#ibcon#about to read 3, iclass 16, count 0 2006.285.10:28:47.54#ibcon#read 3, iclass 16, count 0 2006.285.10:28:47.54#ibcon#about to read 4, iclass 16, count 0 2006.285.10:28:47.54#ibcon#read 4, iclass 16, count 0 2006.285.10:28:47.54#ibcon#about to read 5, iclass 16, count 0 2006.285.10:28:47.54#ibcon#read 5, iclass 16, count 0 2006.285.10:28:47.54#ibcon#about to read 6, iclass 16, count 0 2006.285.10:28:47.54#ibcon#read 6, iclass 16, count 0 2006.285.10:28:47.54#ibcon#end of sib2, iclass 16, count 0 2006.285.10:28:47.54#ibcon#*after write, iclass 16, count 0 2006.285.10:28:47.54#ibcon#*before return 0, iclass 16, count 0 2006.285.10:28:47.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:28:47.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:28:47.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:28:47.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:28:47.54$vck44/valo=3,564.99 2006.285.10:28:47.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.10:28:47.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.10:28:47.54#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:47.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:28:47.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:28:47.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:28:47.54#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:28:47.54#ibcon#first serial, iclass 18, count 0 2006.285.10:28:47.54#ibcon#enter sib2, iclass 18, count 0 2006.285.10:28:47.54#ibcon#flushed, iclass 18, count 0 2006.285.10:28:47.54#ibcon#about to write, iclass 18, count 0 2006.285.10:28:47.54#ibcon#wrote, iclass 18, count 0 2006.285.10:28:47.54#ibcon#about to read 3, iclass 18, count 0 2006.285.10:28:47.56#ibcon#read 3, iclass 18, count 0 2006.285.10:28:47.56#ibcon#about to read 4, iclass 18, count 0 2006.285.10:28:47.56#ibcon#read 4, iclass 18, count 0 2006.285.10:28:47.56#ibcon#about to read 5, iclass 18, count 0 2006.285.10:28:47.56#ibcon#read 5, iclass 18, count 0 2006.285.10:28:47.56#ibcon#about to read 6, iclass 18, count 0 2006.285.10:28:47.56#ibcon#read 6, iclass 18, count 0 2006.285.10:28:47.56#ibcon#end of sib2, iclass 18, count 0 2006.285.10:28:47.56#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:28:47.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:28:47.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:28:47.56#ibcon#*before write, iclass 18, count 0 2006.285.10:28:47.56#ibcon#enter sib2, iclass 18, count 0 2006.285.10:28:47.56#ibcon#flushed, iclass 18, count 0 2006.285.10:28:47.56#ibcon#about to write, iclass 18, count 0 2006.285.10:28:47.56#ibcon#wrote, iclass 18, count 0 2006.285.10:28:47.56#ibcon#about to read 3, iclass 18, count 0 2006.285.10:28:47.60#ibcon#read 3, iclass 18, count 0 2006.285.10:28:47.60#ibcon#about to read 4, iclass 18, count 0 2006.285.10:28:47.60#ibcon#read 4, iclass 18, count 0 2006.285.10:28:47.60#ibcon#about to read 5, iclass 18, count 0 2006.285.10:28:47.60#ibcon#read 5, iclass 18, count 0 2006.285.10:28:47.60#ibcon#about to read 6, iclass 18, count 0 2006.285.10:28:47.60#ibcon#read 6, iclass 18, count 0 2006.285.10:28:47.60#ibcon#end of sib2, iclass 18, count 0 2006.285.10:28:47.60#ibcon#*after write, iclass 18, count 0 2006.285.10:28:47.60#ibcon#*before return 0, iclass 18, count 0 2006.285.10:28:47.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:28:47.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:28:47.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:28:47.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:28:47.60$vck44/va=3,7 2006.285.10:28:47.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.10:28:47.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.10:28:47.60#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:47.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:28:47.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:28:47.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:28:47.66#ibcon#enter wrdev, iclass 20, count 2 2006.285.10:28:47.66#ibcon#first serial, iclass 20, count 2 2006.285.10:28:47.66#ibcon#enter sib2, iclass 20, count 2 2006.285.10:28:47.66#ibcon#flushed, iclass 20, count 2 2006.285.10:28:47.66#ibcon#about to write, iclass 20, count 2 2006.285.10:28:47.66#ibcon#wrote, iclass 20, count 2 2006.285.10:28:47.66#ibcon#about to read 3, iclass 20, count 2 2006.285.10:28:47.68#ibcon#read 3, iclass 20, count 2 2006.285.10:28:47.68#ibcon#about to read 4, iclass 20, count 2 2006.285.10:28:47.68#ibcon#read 4, iclass 20, count 2 2006.285.10:28:47.68#ibcon#about to read 5, iclass 20, count 2 2006.285.10:28:47.68#ibcon#read 5, iclass 20, count 2 2006.285.10:28:47.68#ibcon#about to read 6, iclass 20, count 2 2006.285.10:28:47.68#ibcon#read 6, iclass 20, count 2 2006.285.10:28:47.68#ibcon#end of sib2, iclass 20, count 2 2006.285.10:28:47.68#ibcon#*mode == 0, iclass 20, count 2 2006.285.10:28:47.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.10:28:47.68#ibcon#[25=AT03-07\r\n] 2006.285.10:28:47.68#ibcon#*before write, iclass 20, count 2 2006.285.10:28:47.68#ibcon#enter sib2, iclass 20, count 2 2006.285.10:28:47.68#ibcon#flushed, iclass 20, count 2 2006.285.10:28:47.68#ibcon#about to write, iclass 20, count 2 2006.285.10:28:47.68#ibcon#wrote, iclass 20, count 2 2006.285.10:28:47.68#ibcon#about to read 3, iclass 20, count 2 2006.285.10:28:47.71#ibcon#read 3, iclass 20, count 2 2006.285.10:28:47.71#ibcon#about to read 4, iclass 20, count 2 2006.285.10:28:47.71#ibcon#read 4, iclass 20, count 2 2006.285.10:28:47.71#ibcon#about to read 5, iclass 20, count 2 2006.285.10:28:47.71#ibcon#read 5, iclass 20, count 2 2006.285.10:28:47.71#ibcon#about to read 6, iclass 20, count 2 2006.285.10:28:47.71#ibcon#read 6, iclass 20, count 2 2006.285.10:28:47.71#ibcon#end of sib2, iclass 20, count 2 2006.285.10:28:47.71#ibcon#*after write, iclass 20, count 2 2006.285.10:28:47.71#ibcon#*before return 0, iclass 20, count 2 2006.285.10:28:47.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:28:47.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:28:47.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.10:28:47.71#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:47.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:28:47.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:28:47.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:28:47.83#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:28:47.83#ibcon#first serial, iclass 20, count 0 2006.285.10:28:47.83#ibcon#enter sib2, iclass 20, count 0 2006.285.10:28:47.83#ibcon#flushed, iclass 20, count 0 2006.285.10:28:47.83#ibcon#about to write, iclass 20, count 0 2006.285.10:28:47.83#ibcon#wrote, iclass 20, count 0 2006.285.10:28:47.83#ibcon#about to read 3, iclass 20, count 0 2006.285.10:28:47.85#ibcon#read 3, iclass 20, count 0 2006.285.10:28:47.85#ibcon#about to read 4, iclass 20, count 0 2006.285.10:28:47.85#ibcon#read 4, iclass 20, count 0 2006.285.10:28:47.85#ibcon#about to read 5, iclass 20, count 0 2006.285.10:28:47.85#ibcon#read 5, iclass 20, count 0 2006.285.10:28:47.85#ibcon#about to read 6, iclass 20, count 0 2006.285.10:28:47.85#ibcon#read 6, iclass 20, count 0 2006.285.10:28:47.85#ibcon#end of sib2, iclass 20, count 0 2006.285.10:28:47.85#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:28:47.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:28:47.85#ibcon#[25=USB\r\n] 2006.285.10:28:47.85#ibcon#*before write, iclass 20, count 0 2006.285.10:28:47.85#ibcon#enter sib2, iclass 20, count 0 2006.285.10:28:47.85#ibcon#flushed, iclass 20, count 0 2006.285.10:28:47.85#ibcon#about to write, iclass 20, count 0 2006.285.10:28:47.85#ibcon#wrote, iclass 20, count 0 2006.285.10:28:47.85#ibcon#about to read 3, iclass 20, count 0 2006.285.10:28:47.88#ibcon#read 3, iclass 20, count 0 2006.285.10:28:47.88#ibcon#about to read 4, iclass 20, count 0 2006.285.10:28:47.88#ibcon#read 4, iclass 20, count 0 2006.285.10:28:47.88#ibcon#about to read 5, iclass 20, count 0 2006.285.10:28:47.88#ibcon#read 5, iclass 20, count 0 2006.285.10:28:47.88#ibcon#about to read 6, iclass 20, count 0 2006.285.10:28:47.88#ibcon#read 6, iclass 20, count 0 2006.285.10:28:47.88#ibcon#end of sib2, iclass 20, count 0 2006.285.10:28:47.88#ibcon#*after write, iclass 20, count 0 2006.285.10:28:47.88#ibcon#*before return 0, iclass 20, count 0 2006.285.10:28:47.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:28:47.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:28:47.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:28:47.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:28:47.88$vck44/valo=4,624.99 2006.285.10:28:47.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.10:28:47.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.10:28:47.88#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:47.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:28:47.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:28:47.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:28:47.88#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:28:47.88#ibcon#first serial, iclass 22, count 0 2006.285.10:28:47.88#ibcon#enter sib2, iclass 22, count 0 2006.285.10:28:47.88#ibcon#flushed, iclass 22, count 0 2006.285.10:28:47.88#ibcon#about to write, iclass 22, count 0 2006.285.10:28:47.88#ibcon#wrote, iclass 22, count 0 2006.285.10:28:47.88#ibcon#about to read 3, iclass 22, count 0 2006.285.10:28:47.90#ibcon#read 3, iclass 22, count 0 2006.285.10:28:47.90#ibcon#about to read 4, iclass 22, count 0 2006.285.10:28:47.90#ibcon#read 4, iclass 22, count 0 2006.285.10:28:47.90#ibcon#about to read 5, iclass 22, count 0 2006.285.10:28:47.90#ibcon#read 5, iclass 22, count 0 2006.285.10:28:47.90#ibcon#about to read 6, iclass 22, count 0 2006.285.10:28:47.90#ibcon#read 6, iclass 22, count 0 2006.285.10:28:47.90#ibcon#end of sib2, iclass 22, count 0 2006.285.10:28:47.90#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:28:47.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:28:47.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:28:47.90#ibcon#*before write, iclass 22, count 0 2006.285.10:28:47.90#ibcon#enter sib2, iclass 22, count 0 2006.285.10:28:47.90#ibcon#flushed, iclass 22, count 0 2006.285.10:28:47.90#ibcon#about to write, iclass 22, count 0 2006.285.10:28:47.90#ibcon#wrote, iclass 22, count 0 2006.285.10:28:47.90#ibcon#about to read 3, iclass 22, count 0 2006.285.10:28:47.94#ibcon#read 3, iclass 22, count 0 2006.285.10:28:47.94#ibcon#about to read 4, iclass 22, count 0 2006.285.10:28:47.94#ibcon#read 4, iclass 22, count 0 2006.285.10:28:47.94#ibcon#about to read 5, iclass 22, count 0 2006.285.10:28:47.94#ibcon#read 5, iclass 22, count 0 2006.285.10:28:47.94#ibcon#about to read 6, iclass 22, count 0 2006.285.10:28:47.94#ibcon#read 6, iclass 22, count 0 2006.285.10:28:47.94#ibcon#end of sib2, iclass 22, count 0 2006.285.10:28:47.94#ibcon#*after write, iclass 22, count 0 2006.285.10:28:47.94#ibcon#*before return 0, iclass 22, count 0 2006.285.10:28:47.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:28:47.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:28:47.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:28:47.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:28:47.94$vck44/va=4,6 2006.285.10:28:47.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.10:28:47.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.10:28:47.94#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:47.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:28:48.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:28:48.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:28:48.00#ibcon#enter wrdev, iclass 24, count 2 2006.285.10:28:48.00#ibcon#first serial, iclass 24, count 2 2006.285.10:28:48.00#ibcon#enter sib2, iclass 24, count 2 2006.285.10:28:48.00#ibcon#flushed, iclass 24, count 2 2006.285.10:28:48.00#ibcon#about to write, iclass 24, count 2 2006.285.10:28:48.00#ibcon#wrote, iclass 24, count 2 2006.285.10:28:48.00#ibcon#about to read 3, iclass 24, count 2 2006.285.10:28:48.02#ibcon#read 3, iclass 24, count 2 2006.285.10:28:48.02#ibcon#about to read 4, iclass 24, count 2 2006.285.10:28:48.02#ibcon#read 4, iclass 24, count 2 2006.285.10:28:48.02#ibcon#about to read 5, iclass 24, count 2 2006.285.10:28:48.02#ibcon#read 5, iclass 24, count 2 2006.285.10:28:48.02#ibcon#about to read 6, iclass 24, count 2 2006.285.10:28:48.02#ibcon#read 6, iclass 24, count 2 2006.285.10:28:48.02#ibcon#end of sib2, iclass 24, count 2 2006.285.10:28:48.02#ibcon#*mode == 0, iclass 24, count 2 2006.285.10:28:48.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.10:28:48.02#ibcon#[25=AT04-06\r\n] 2006.285.10:28:48.02#ibcon#*before write, iclass 24, count 2 2006.285.10:28:48.02#ibcon#enter sib2, iclass 24, count 2 2006.285.10:28:48.02#ibcon#flushed, iclass 24, count 2 2006.285.10:28:48.02#ibcon#about to write, iclass 24, count 2 2006.285.10:28:48.02#ibcon#wrote, iclass 24, count 2 2006.285.10:28:48.02#ibcon#about to read 3, iclass 24, count 2 2006.285.10:28:48.05#ibcon#read 3, iclass 24, count 2 2006.285.10:28:48.05#ibcon#about to read 4, iclass 24, count 2 2006.285.10:28:48.05#ibcon#read 4, iclass 24, count 2 2006.285.10:28:48.05#ibcon#about to read 5, iclass 24, count 2 2006.285.10:28:48.05#ibcon#read 5, iclass 24, count 2 2006.285.10:28:48.05#ibcon#about to read 6, iclass 24, count 2 2006.285.10:28:48.05#ibcon#read 6, iclass 24, count 2 2006.285.10:28:48.05#ibcon#end of sib2, iclass 24, count 2 2006.285.10:28:48.05#ibcon#*after write, iclass 24, count 2 2006.285.10:28:48.05#ibcon#*before return 0, iclass 24, count 2 2006.285.10:28:48.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:28:48.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:28:48.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.10:28:48.05#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:48.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:28:48.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:28:48.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:28:48.17#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:28:48.17#ibcon#first serial, iclass 24, count 0 2006.285.10:28:48.17#ibcon#enter sib2, iclass 24, count 0 2006.285.10:28:48.17#ibcon#flushed, iclass 24, count 0 2006.285.10:28:48.17#ibcon#about to write, iclass 24, count 0 2006.285.10:28:48.17#ibcon#wrote, iclass 24, count 0 2006.285.10:28:48.17#ibcon#about to read 3, iclass 24, count 0 2006.285.10:28:48.19#ibcon#read 3, iclass 24, count 0 2006.285.10:28:48.19#ibcon#about to read 4, iclass 24, count 0 2006.285.10:28:48.19#ibcon#read 4, iclass 24, count 0 2006.285.10:28:48.19#ibcon#about to read 5, iclass 24, count 0 2006.285.10:28:48.19#ibcon#read 5, iclass 24, count 0 2006.285.10:28:48.19#ibcon#about to read 6, iclass 24, count 0 2006.285.10:28:48.19#ibcon#read 6, iclass 24, count 0 2006.285.10:28:48.19#ibcon#end of sib2, iclass 24, count 0 2006.285.10:28:48.19#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:28:48.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:28:48.19#ibcon#[25=USB\r\n] 2006.285.10:28:48.19#ibcon#*before write, iclass 24, count 0 2006.285.10:28:48.19#ibcon#enter sib2, iclass 24, count 0 2006.285.10:28:48.19#ibcon#flushed, iclass 24, count 0 2006.285.10:28:48.19#ibcon#about to write, iclass 24, count 0 2006.285.10:28:48.19#ibcon#wrote, iclass 24, count 0 2006.285.10:28:48.19#ibcon#about to read 3, iclass 24, count 0 2006.285.10:28:48.22#ibcon#read 3, iclass 24, count 0 2006.285.10:28:48.22#ibcon#about to read 4, iclass 24, count 0 2006.285.10:28:48.22#ibcon#read 4, iclass 24, count 0 2006.285.10:28:48.22#ibcon#about to read 5, iclass 24, count 0 2006.285.10:28:48.22#ibcon#read 5, iclass 24, count 0 2006.285.10:28:48.22#ibcon#about to read 6, iclass 24, count 0 2006.285.10:28:48.22#ibcon#read 6, iclass 24, count 0 2006.285.10:28:48.22#ibcon#end of sib2, iclass 24, count 0 2006.285.10:28:48.22#ibcon#*after write, iclass 24, count 0 2006.285.10:28:48.22#ibcon#*before return 0, iclass 24, count 0 2006.285.10:28:48.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:28:48.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:28:48.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:28:48.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:28:48.22$vck44/valo=5,734.99 2006.285.10:28:48.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.10:28:48.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.10:28:48.22#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:48.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:28:48.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:28:48.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:28:48.22#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:28:48.22#ibcon#first serial, iclass 26, count 0 2006.285.10:28:48.22#ibcon#enter sib2, iclass 26, count 0 2006.285.10:28:48.22#ibcon#flushed, iclass 26, count 0 2006.285.10:28:48.22#ibcon#about to write, iclass 26, count 0 2006.285.10:28:48.22#ibcon#wrote, iclass 26, count 0 2006.285.10:28:48.22#ibcon#about to read 3, iclass 26, count 0 2006.285.10:28:48.24#ibcon#read 3, iclass 26, count 0 2006.285.10:28:48.24#ibcon#about to read 4, iclass 26, count 0 2006.285.10:28:48.24#ibcon#read 4, iclass 26, count 0 2006.285.10:28:48.24#ibcon#about to read 5, iclass 26, count 0 2006.285.10:28:48.24#ibcon#read 5, iclass 26, count 0 2006.285.10:28:48.24#ibcon#about to read 6, iclass 26, count 0 2006.285.10:28:48.24#ibcon#read 6, iclass 26, count 0 2006.285.10:28:48.24#ibcon#end of sib2, iclass 26, count 0 2006.285.10:28:48.24#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:28:48.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:28:48.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:28:48.24#ibcon#*before write, iclass 26, count 0 2006.285.10:28:48.24#ibcon#enter sib2, iclass 26, count 0 2006.285.10:28:48.24#ibcon#flushed, iclass 26, count 0 2006.285.10:28:48.24#ibcon#about to write, iclass 26, count 0 2006.285.10:28:48.24#ibcon#wrote, iclass 26, count 0 2006.285.10:28:48.24#ibcon#about to read 3, iclass 26, count 0 2006.285.10:28:48.28#ibcon#read 3, iclass 26, count 0 2006.285.10:28:48.28#ibcon#about to read 4, iclass 26, count 0 2006.285.10:28:48.28#ibcon#read 4, iclass 26, count 0 2006.285.10:28:48.28#ibcon#about to read 5, iclass 26, count 0 2006.285.10:28:48.28#ibcon#read 5, iclass 26, count 0 2006.285.10:28:48.28#ibcon#about to read 6, iclass 26, count 0 2006.285.10:28:48.28#ibcon#read 6, iclass 26, count 0 2006.285.10:28:48.28#ibcon#end of sib2, iclass 26, count 0 2006.285.10:28:48.28#ibcon#*after write, iclass 26, count 0 2006.285.10:28:48.28#ibcon#*before return 0, iclass 26, count 0 2006.285.10:28:48.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:28:48.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:28:48.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:28:48.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:28:48.28$vck44/va=5,3 2006.285.10:28:48.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.10:28:48.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.10:28:48.28#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:48.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:28:48.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:28:48.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:28:48.34#ibcon#enter wrdev, iclass 28, count 2 2006.285.10:28:48.34#ibcon#first serial, iclass 28, count 2 2006.285.10:28:48.34#ibcon#enter sib2, iclass 28, count 2 2006.285.10:28:48.34#ibcon#flushed, iclass 28, count 2 2006.285.10:28:48.34#ibcon#about to write, iclass 28, count 2 2006.285.10:28:48.34#ibcon#wrote, iclass 28, count 2 2006.285.10:28:48.34#ibcon#about to read 3, iclass 28, count 2 2006.285.10:28:48.36#ibcon#read 3, iclass 28, count 2 2006.285.10:28:48.36#ibcon#about to read 4, iclass 28, count 2 2006.285.10:28:48.36#ibcon#read 4, iclass 28, count 2 2006.285.10:28:48.36#ibcon#about to read 5, iclass 28, count 2 2006.285.10:28:48.36#ibcon#read 5, iclass 28, count 2 2006.285.10:28:48.36#ibcon#about to read 6, iclass 28, count 2 2006.285.10:28:48.36#ibcon#read 6, iclass 28, count 2 2006.285.10:28:48.36#ibcon#end of sib2, iclass 28, count 2 2006.285.10:28:48.36#ibcon#*mode == 0, iclass 28, count 2 2006.285.10:28:48.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.10:28:48.36#ibcon#[25=AT05-03\r\n] 2006.285.10:28:48.36#ibcon#*before write, iclass 28, count 2 2006.285.10:28:48.36#ibcon#enter sib2, iclass 28, count 2 2006.285.10:28:48.36#ibcon#flushed, iclass 28, count 2 2006.285.10:28:48.36#ibcon#about to write, iclass 28, count 2 2006.285.10:28:48.36#ibcon#wrote, iclass 28, count 2 2006.285.10:28:48.36#ibcon#about to read 3, iclass 28, count 2 2006.285.10:28:48.39#ibcon#read 3, iclass 28, count 2 2006.285.10:28:48.39#ibcon#about to read 4, iclass 28, count 2 2006.285.10:28:48.39#ibcon#read 4, iclass 28, count 2 2006.285.10:28:48.39#ibcon#about to read 5, iclass 28, count 2 2006.285.10:28:48.39#ibcon#read 5, iclass 28, count 2 2006.285.10:28:48.39#ibcon#about to read 6, iclass 28, count 2 2006.285.10:28:48.39#ibcon#read 6, iclass 28, count 2 2006.285.10:28:48.39#ibcon#end of sib2, iclass 28, count 2 2006.285.10:28:48.39#ibcon#*after write, iclass 28, count 2 2006.285.10:28:48.39#ibcon#*before return 0, iclass 28, count 2 2006.285.10:28:48.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:28:48.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:28:48.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.10:28:48.39#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:48.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:28:48.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:28:48.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:28:48.51#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:28:48.51#ibcon#first serial, iclass 28, count 0 2006.285.10:28:48.51#ibcon#enter sib2, iclass 28, count 0 2006.285.10:28:48.51#ibcon#flushed, iclass 28, count 0 2006.285.10:28:48.51#ibcon#about to write, iclass 28, count 0 2006.285.10:28:48.51#ibcon#wrote, iclass 28, count 0 2006.285.10:28:48.51#ibcon#about to read 3, iclass 28, count 0 2006.285.10:28:48.53#ibcon#read 3, iclass 28, count 0 2006.285.10:28:48.53#ibcon#about to read 4, iclass 28, count 0 2006.285.10:28:48.53#ibcon#read 4, iclass 28, count 0 2006.285.10:28:48.53#ibcon#about to read 5, iclass 28, count 0 2006.285.10:28:48.53#ibcon#read 5, iclass 28, count 0 2006.285.10:28:48.53#ibcon#about to read 6, iclass 28, count 0 2006.285.10:28:48.53#ibcon#read 6, iclass 28, count 0 2006.285.10:28:48.53#ibcon#end of sib2, iclass 28, count 0 2006.285.10:28:48.53#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:28:48.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:28:48.53#ibcon#[25=USB\r\n] 2006.285.10:28:48.53#ibcon#*before write, iclass 28, count 0 2006.285.10:28:48.53#ibcon#enter sib2, iclass 28, count 0 2006.285.10:28:48.53#ibcon#flushed, iclass 28, count 0 2006.285.10:28:48.53#ibcon#about to write, iclass 28, count 0 2006.285.10:28:48.53#ibcon#wrote, iclass 28, count 0 2006.285.10:28:48.53#ibcon#about to read 3, iclass 28, count 0 2006.285.10:28:48.56#ibcon#read 3, iclass 28, count 0 2006.285.10:28:48.56#ibcon#about to read 4, iclass 28, count 0 2006.285.10:28:48.56#ibcon#read 4, iclass 28, count 0 2006.285.10:28:48.56#ibcon#about to read 5, iclass 28, count 0 2006.285.10:28:48.56#ibcon#read 5, iclass 28, count 0 2006.285.10:28:48.56#ibcon#about to read 6, iclass 28, count 0 2006.285.10:28:48.56#ibcon#read 6, iclass 28, count 0 2006.285.10:28:48.56#ibcon#end of sib2, iclass 28, count 0 2006.285.10:28:48.56#ibcon#*after write, iclass 28, count 0 2006.285.10:28:48.56#ibcon#*before return 0, iclass 28, count 0 2006.285.10:28:48.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:28:48.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:28:48.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:28:48.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:28:48.56$vck44/valo=6,814.99 2006.285.10:28:48.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.10:28:48.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.10:28:48.56#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:48.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:28:48.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:28:48.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:28:48.56#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:28:48.56#ibcon#first serial, iclass 30, count 0 2006.285.10:28:48.56#ibcon#enter sib2, iclass 30, count 0 2006.285.10:28:48.56#ibcon#flushed, iclass 30, count 0 2006.285.10:28:48.56#ibcon#about to write, iclass 30, count 0 2006.285.10:28:48.56#ibcon#wrote, iclass 30, count 0 2006.285.10:28:48.56#ibcon#about to read 3, iclass 30, count 0 2006.285.10:28:48.58#ibcon#read 3, iclass 30, count 0 2006.285.10:28:48.58#ibcon#about to read 4, iclass 30, count 0 2006.285.10:28:48.58#ibcon#read 4, iclass 30, count 0 2006.285.10:28:48.58#ibcon#about to read 5, iclass 30, count 0 2006.285.10:28:48.58#ibcon#read 5, iclass 30, count 0 2006.285.10:28:48.58#ibcon#about to read 6, iclass 30, count 0 2006.285.10:28:48.58#ibcon#read 6, iclass 30, count 0 2006.285.10:28:48.58#ibcon#end of sib2, iclass 30, count 0 2006.285.10:28:48.58#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:28:48.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:28:48.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:28:48.58#ibcon#*before write, iclass 30, count 0 2006.285.10:28:48.58#ibcon#enter sib2, iclass 30, count 0 2006.285.10:28:48.58#ibcon#flushed, iclass 30, count 0 2006.285.10:28:48.58#ibcon#about to write, iclass 30, count 0 2006.285.10:28:48.58#ibcon#wrote, iclass 30, count 0 2006.285.10:28:48.58#ibcon#about to read 3, iclass 30, count 0 2006.285.10:28:48.62#ibcon#read 3, iclass 30, count 0 2006.285.10:28:48.62#ibcon#about to read 4, iclass 30, count 0 2006.285.10:28:48.62#ibcon#read 4, iclass 30, count 0 2006.285.10:28:48.62#ibcon#about to read 5, iclass 30, count 0 2006.285.10:28:48.62#ibcon#read 5, iclass 30, count 0 2006.285.10:28:48.62#ibcon#about to read 6, iclass 30, count 0 2006.285.10:28:48.62#ibcon#read 6, iclass 30, count 0 2006.285.10:28:48.62#ibcon#end of sib2, iclass 30, count 0 2006.285.10:28:48.62#ibcon#*after write, iclass 30, count 0 2006.285.10:28:48.62#ibcon#*before return 0, iclass 30, count 0 2006.285.10:28:48.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:28:48.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:28:48.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:28:48.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:28:48.62$vck44/va=6,4 2006.285.10:28:48.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.10:28:48.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.10:28:48.62#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:48.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:28:48.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:28:48.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:28:48.68#ibcon#enter wrdev, iclass 32, count 2 2006.285.10:28:48.68#ibcon#first serial, iclass 32, count 2 2006.285.10:28:48.68#ibcon#enter sib2, iclass 32, count 2 2006.285.10:28:48.68#ibcon#flushed, iclass 32, count 2 2006.285.10:28:48.68#ibcon#about to write, iclass 32, count 2 2006.285.10:28:48.68#ibcon#wrote, iclass 32, count 2 2006.285.10:28:48.68#ibcon#about to read 3, iclass 32, count 2 2006.285.10:28:48.70#ibcon#read 3, iclass 32, count 2 2006.285.10:28:48.70#ibcon#about to read 4, iclass 32, count 2 2006.285.10:28:48.70#ibcon#read 4, iclass 32, count 2 2006.285.10:28:48.70#ibcon#about to read 5, iclass 32, count 2 2006.285.10:28:48.70#ibcon#read 5, iclass 32, count 2 2006.285.10:28:48.70#ibcon#about to read 6, iclass 32, count 2 2006.285.10:28:48.70#ibcon#read 6, iclass 32, count 2 2006.285.10:28:48.70#ibcon#end of sib2, iclass 32, count 2 2006.285.10:28:48.70#ibcon#*mode == 0, iclass 32, count 2 2006.285.10:28:48.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.10:28:48.70#ibcon#[25=AT06-04\r\n] 2006.285.10:28:48.70#ibcon#*before write, iclass 32, count 2 2006.285.10:28:48.70#ibcon#enter sib2, iclass 32, count 2 2006.285.10:28:48.70#ibcon#flushed, iclass 32, count 2 2006.285.10:28:48.70#ibcon#about to write, iclass 32, count 2 2006.285.10:28:48.70#ibcon#wrote, iclass 32, count 2 2006.285.10:28:48.70#ibcon#about to read 3, iclass 32, count 2 2006.285.10:28:48.73#ibcon#read 3, iclass 32, count 2 2006.285.10:28:48.73#ibcon#about to read 4, iclass 32, count 2 2006.285.10:28:48.73#ibcon#read 4, iclass 32, count 2 2006.285.10:28:48.73#ibcon#about to read 5, iclass 32, count 2 2006.285.10:28:48.73#ibcon#read 5, iclass 32, count 2 2006.285.10:28:48.73#ibcon#about to read 6, iclass 32, count 2 2006.285.10:28:48.73#ibcon#read 6, iclass 32, count 2 2006.285.10:28:48.73#ibcon#end of sib2, iclass 32, count 2 2006.285.10:28:48.73#ibcon#*after write, iclass 32, count 2 2006.285.10:28:48.73#ibcon#*before return 0, iclass 32, count 2 2006.285.10:28:48.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:28:48.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:28:48.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.10:28:48.73#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:48.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:28:48.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:28:48.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:28:48.85#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:28:48.85#ibcon#first serial, iclass 32, count 0 2006.285.10:28:48.85#ibcon#enter sib2, iclass 32, count 0 2006.285.10:28:48.85#ibcon#flushed, iclass 32, count 0 2006.285.10:28:48.85#ibcon#about to write, iclass 32, count 0 2006.285.10:28:48.85#ibcon#wrote, iclass 32, count 0 2006.285.10:28:48.85#ibcon#about to read 3, iclass 32, count 0 2006.285.10:28:48.87#ibcon#read 3, iclass 32, count 0 2006.285.10:28:48.87#ibcon#about to read 4, iclass 32, count 0 2006.285.10:28:48.87#ibcon#read 4, iclass 32, count 0 2006.285.10:28:48.87#ibcon#about to read 5, iclass 32, count 0 2006.285.10:28:48.87#ibcon#read 5, iclass 32, count 0 2006.285.10:28:48.87#ibcon#about to read 6, iclass 32, count 0 2006.285.10:28:48.87#ibcon#read 6, iclass 32, count 0 2006.285.10:28:48.87#ibcon#end of sib2, iclass 32, count 0 2006.285.10:28:48.87#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:28:48.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:28:48.87#ibcon#[25=USB\r\n] 2006.285.10:28:48.87#ibcon#*before write, iclass 32, count 0 2006.285.10:28:48.87#ibcon#enter sib2, iclass 32, count 0 2006.285.10:28:48.87#ibcon#flushed, iclass 32, count 0 2006.285.10:28:48.87#ibcon#about to write, iclass 32, count 0 2006.285.10:28:48.87#ibcon#wrote, iclass 32, count 0 2006.285.10:28:48.87#ibcon#about to read 3, iclass 32, count 0 2006.285.10:28:48.90#ibcon#read 3, iclass 32, count 0 2006.285.10:28:48.90#ibcon#about to read 4, iclass 32, count 0 2006.285.10:28:48.90#ibcon#read 4, iclass 32, count 0 2006.285.10:28:48.90#ibcon#about to read 5, iclass 32, count 0 2006.285.10:28:48.90#ibcon#read 5, iclass 32, count 0 2006.285.10:28:48.90#ibcon#about to read 6, iclass 32, count 0 2006.285.10:28:48.90#ibcon#read 6, iclass 32, count 0 2006.285.10:28:48.90#ibcon#end of sib2, iclass 32, count 0 2006.285.10:28:48.90#ibcon#*after write, iclass 32, count 0 2006.285.10:28:48.90#ibcon#*before return 0, iclass 32, count 0 2006.285.10:28:48.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:28:48.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:28:48.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:28:48.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:28:48.90$vck44/valo=7,864.99 2006.285.10:28:48.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.10:28:48.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.10:28:48.90#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:48.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:28:48.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:28:48.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:28:48.90#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:28:48.90#ibcon#first serial, iclass 34, count 0 2006.285.10:28:48.90#ibcon#enter sib2, iclass 34, count 0 2006.285.10:28:48.90#ibcon#flushed, iclass 34, count 0 2006.285.10:28:48.90#ibcon#about to write, iclass 34, count 0 2006.285.10:28:48.90#ibcon#wrote, iclass 34, count 0 2006.285.10:28:48.90#ibcon#about to read 3, iclass 34, count 0 2006.285.10:28:48.92#ibcon#read 3, iclass 34, count 0 2006.285.10:28:48.92#ibcon#about to read 4, iclass 34, count 0 2006.285.10:28:48.92#ibcon#read 4, iclass 34, count 0 2006.285.10:28:48.92#ibcon#about to read 5, iclass 34, count 0 2006.285.10:28:48.92#ibcon#read 5, iclass 34, count 0 2006.285.10:28:48.92#ibcon#about to read 6, iclass 34, count 0 2006.285.10:28:48.92#ibcon#read 6, iclass 34, count 0 2006.285.10:28:48.92#ibcon#end of sib2, iclass 34, count 0 2006.285.10:28:48.92#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:28:48.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:28:48.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:28:48.92#ibcon#*before write, iclass 34, count 0 2006.285.10:28:48.92#ibcon#enter sib2, iclass 34, count 0 2006.285.10:28:48.92#ibcon#flushed, iclass 34, count 0 2006.285.10:28:48.92#ibcon#about to write, iclass 34, count 0 2006.285.10:28:48.92#ibcon#wrote, iclass 34, count 0 2006.285.10:28:48.92#ibcon#about to read 3, iclass 34, count 0 2006.285.10:28:48.96#ibcon#read 3, iclass 34, count 0 2006.285.10:28:48.96#ibcon#about to read 4, iclass 34, count 0 2006.285.10:28:48.96#ibcon#read 4, iclass 34, count 0 2006.285.10:28:48.96#ibcon#about to read 5, iclass 34, count 0 2006.285.10:28:48.96#ibcon#read 5, iclass 34, count 0 2006.285.10:28:48.96#ibcon#about to read 6, iclass 34, count 0 2006.285.10:28:48.96#ibcon#read 6, iclass 34, count 0 2006.285.10:28:48.96#ibcon#end of sib2, iclass 34, count 0 2006.285.10:28:48.96#ibcon#*after write, iclass 34, count 0 2006.285.10:28:48.96#ibcon#*before return 0, iclass 34, count 0 2006.285.10:28:48.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:28:48.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:28:48.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:28:48.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:28:48.96$vck44/va=7,4 2006.285.10:28:48.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.10:28:48.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.10:28:48.96#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:48.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:28:49.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:28:49.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:28:49.02#ibcon#enter wrdev, iclass 36, count 2 2006.285.10:28:49.02#ibcon#first serial, iclass 36, count 2 2006.285.10:28:49.02#ibcon#enter sib2, iclass 36, count 2 2006.285.10:28:49.02#ibcon#flushed, iclass 36, count 2 2006.285.10:28:49.02#ibcon#about to write, iclass 36, count 2 2006.285.10:28:49.02#ibcon#wrote, iclass 36, count 2 2006.285.10:28:49.02#ibcon#about to read 3, iclass 36, count 2 2006.285.10:28:49.04#ibcon#read 3, iclass 36, count 2 2006.285.10:28:49.04#ibcon#about to read 4, iclass 36, count 2 2006.285.10:28:49.04#ibcon#read 4, iclass 36, count 2 2006.285.10:28:49.04#ibcon#about to read 5, iclass 36, count 2 2006.285.10:28:49.04#ibcon#read 5, iclass 36, count 2 2006.285.10:28:49.04#ibcon#about to read 6, iclass 36, count 2 2006.285.10:28:49.04#ibcon#read 6, iclass 36, count 2 2006.285.10:28:49.04#ibcon#end of sib2, iclass 36, count 2 2006.285.10:28:49.04#ibcon#*mode == 0, iclass 36, count 2 2006.285.10:28:49.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.10:28:49.04#ibcon#[25=AT07-04\r\n] 2006.285.10:28:49.04#ibcon#*before write, iclass 36, count 2 2006.285.10:28:49.04#ibcon#enter sib2, iclass 36, count 2 2006.285.10:28:49.04#ibcon#flushed, iclass 36, count 2 2006.285.10:28:49.04#ibcon#about to write, iclass 36, count 2 2006.285.10:28:49.04#ibcon#wrote, iclass 36, count 2 2006.285.10:28:49.04#ibcon#about to read 3, iclass 36, count 2 2006.285.10:28:49.07#ibcon#read 3, iclass 36, count 2 2006.285.10:28:49.07#ibcon#about to read 4, iclass 36, count 2 2006.285.10:28:49.07#ibcon#read 4, iclass 36, count 2 2006.285.10:28:49.07#ibcon#about to read 5, iclass 36, count 2 2006.285.10:28:49.07#ibcon#read 5, iclass 36, count 2 2006.285.10:28:49.07#ibcon#about to read 6, iclass 36, count 2 2006.285.10:28:49.07#ibcon#read 6, iclass 36, count 2 2006.285.10:28:49.07#ibcon#end of sib2, iclass 36, count 2 2006.285.10:28:49.07#ibcon#*after write, iclass 36, count 2 2006.285.10:28:49.07#ibcon#*before return 0, iclass 36, count 2 2006.285.10:28:49.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:28:49.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:28:49.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.10:28:49.07#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:49.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:28:49.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:28:49.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:28:49.19#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:28:49.19#ibcon#first serial, iclass 36, count 0 2006.285.10:28:49.19#ibcon#enter sib2, iclass 36, count 0 2006.285.10:28:49.19#ibcon#flushed, iclass 36, count 0 2006.285.10:28:49.19#ibcon#about to write, iclass 36, count 0 2006.285.10:28:49.19#ibcon#wrote, iclass 36, count 0 2006.285.10:28:49.19#ibcon#about to read 3, iclass 36, count 0 2006.285.10:28:49.21#ibcon#read 3, iclass 36, count 0 2006.285.10:28:49.21#ibcon#about to read 4, iclass 36, count 0 2006.285.10:28:49.21#ibcon#read 4, iclass 36, count 0 2006.285.10:28:49.21#ibcon#about to read 5, iclass 36, count 0 2006.285.10:28:49.21#ibcon#read 5, iclass 36, count 0 2006.285.10:28:49.21#ibcon#about to read 6, iclass 36, count 0 2006.285.10:28:49.21#ibcon#read 6, iclass 36, count 0 2006.285.10:28:49.21#ibcon#end of sib2, iclass 36, count 0 2006.285.10:28:49.21#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:28:49.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:28:49.21#ibcon#[25=USB\r\n] 2006.285.10:28:49.21#ibcon#*before write, iclass 36, count 0 2006.285.10:28:49.21#ibcon#enter sib2, iclass 36, count 0 2006.285.10:28:49.21#ibcon#flushed, iclass 36, count 0 2006.285.10:28:49.21#ibcon#about to write, iclass 36, count 0 2006.285.10:28:49.21#ibcon#wrote, iclass 36, count 0 2006.285.10:28:49.21#ibcon#about to read 3, iclass 36, count 0 2006.285.10:28:49.24#ibcon#read 3, iclass 36, count 0 2006.285.10:28:49.24#ibcon#about to read 4, iclass 36, count 0 2006.285.10:28:49.24#ibcon#read 4, iclass 36, count 0 2006.285.10:28:49.24#ibcon#about to read 5, iclass 36, count 0 2006.285.10:28:49.24#ibcon#read 5, iclass 36, count 0 2006.285.10:28:49.24#ibcon#about to read 6, iclass 36, count 0 2006.285.10:28:49.24#ibcon#read 6, iclass 36, count 0 2006.285.10:28:49.24#ibcon#end of sib2, iclass 36, count 0 2006.285.10:28:49.24#ibcon#*after write, iclass 36, count 0 2006.285.10:28:49.24#ibcon#*before return 0, iclass 36, count 0 2006.285.10:28:49.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:28:49.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:28:49.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:28:49.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:28:49.24$vck44/valo=8,884.99 2006.285.10:28:49.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.10:28:49.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.10:28:49.24#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:49.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:28:49.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:28:49.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:28:49.24#ibcon#enter wrdev, iclass 38, count 0 2006.285.10:28:49.24#ibcon#first serial, iclass 38, count 0 2006.285.10:28:49.24#ibcon#enter sib2, iclass 38, count 0 2006.285.10:28:49.24#ibcon#flushed, iclass 38, count 0 2006.285.10:28:49.24#ibcon#about to write, iclass 38, count 0 2006.285.10:28:49.24#ibcon#wrote, iclass 38, count 0 2006.285.10:28:49.24#ibcon#about to read 3, iclass 38, count 0 2006.285.10:28:49.26#ibcon#read 3, iclass 38, count 0 2006.285.10:28:49.26#ibcon#about to read 4, iclass 38, count 0 2006.285.10:28:49.26#ibcon#read 4, iclass 38, count 0 2006.285.10:28:49.26#ibcon#about to read 5, iclass 38, count 0 2006.285.10:28:49.26#ibcon#read 5, iclass 38, count 0 2006.285.10:28:49.26#ibcon#about to read 6, iclass 38, count 0 2006.285.10:28:49.26#ibcon#read 6, iclass 38, count 0 2006.285.10:28:49.26#ibcon#end of sib2, iclass 38, count 0 2006.285.10:28:49.26#ibcon#*mode == 0, iclass 38, count 0 2006.285.10:28:49.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.10:28:49.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:28:49.26#ibcon#*before write, iclass 38, count 0 2006.285.10:28:49.26#ibcon#enter sib2, iclass 38, count 0 2006.285.10:28:49.26#ibcon#flushed, iclass 38, count 0 2006.285.10:28:49.26#ibcon#about to write, iclass 38, count 0 2006.285.10:28:49.26#ibcon#wrote, iclass 38, count 0 2006.285.10:28:49.26#ibcon#about to read 3, iclass 38, count 0 2006.285.10:28:49.30#ibcon#read 3, iclass 38, count 0 2006.285.10:28:49.30#ibcon#about to read 4, iclass 38, count 0 2006.285.10:28:49.30#ibcon#read 4, iclass 38, count 0 2006.285.10:28:49.30#ibcon#about to read 5, iclass 38, count 0 2006.285.10:28:49.30#ibcon#read 5, iclass 38, count 0 2006.285.10:28:49.30#ibcon#about to read 6, iclass 38, count 0 2006.285.10:28:49.30#ibcon#read 6, iclass 38, count 0 2006.285.10:28:49.30#ibcon#end of sib2, iclass 38, count 0 2006.285.10:28:49.30#ibcon#*after write, iclass 38, count 0 2006.285.10:28:49.30#ibcon#*before return 0, iclass 38, count 0 2006.285.10:28:49.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:28:49.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:28:49.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.10:28:49.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.10:28:49.30$vck44/va=8,3 2006.285.10:28:49.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.10:28:49.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.10:28:49.30#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:49.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:28:49.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:28:49.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:28:49.36#ibcon#enter wrdev, iclass 40, count 2 2006.285.10:28:49.36#ibcon#first serial, iclass 40, count 2 2006.285.10:28:49.36#ibcon#enter sib2, iclass 40, count 2 2006.285.10:28:49.36#ibcon#flushed, iclass 40, count 2 2006.285.10:28:49.36#ibcon#about to write, iclass 40, count 2 2006.285.10:28:49.36#ibcon#wrote, iclass 40, count 2 2006.285.10:28:49.36#ibcon#about to read 3, iclass 40, count 2 2006.285.10:28:49.38#ibcon#read 3, iclass 40, count 2 2006.285.10:28:49.38#ibcon#about to read 4, iclass 40, count 2 2006.285.10:28:49.38#ibcon#read 4, iclass 40, count 2 2006.285.10:28:49.38#ibcon#about to read 5, iclass 40, count 2 2006.285.10:28:49.38#ibcon#read 5, iclass 40, count 2 2006.285.10:28:49.38#ibcon#about to read 6, iclass 40, count 2 2006.285.10:28:49.38#ibcon#read 6, iclass 40, count 2 2006.285.10:28:49.38#ibcon#end of sib2, iclass 40, count 2 2006.285.10:28:49.38#ibcon#*mode == 0, iclass 40, count 2 2006.285.10:28:49.38#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.10:28:49.38#ibcon#[25=AT08-03\r\n] 2006.285.10:28:49.38#ibcon#*before write, iclass 40, count 2 2006.285.10:28:49.38#ibcon#enter sib2, iclass 40, count 2 2006.285.10:28:49.38#ibcon#flushed, iclass 40, count 2 2006.285.10:28:49.38#ibcon#about to write, iclass 40, count 2 2006.285.10:28:49.38#ibcon#wrote, iclass 40, count 2 2006.285.10:28:49.38#ibcon#about to read 3, iclass 40, count 2 2006.285.10:28:49.41#ibcon#read 3, iclass 40, count 2 2006.285.10:28:49.41#ibcon#about to read 4, iclass 40, count 2 2006.285.10:28:49.41#ibcon#read 4, iclass 40, count 2 2006.285.10:28:49.41#ibcon#about to read 5, iclass 40, count 2 2006.285.10:28:49.41#ibcon#read 5, iclass 40, count 2 2006.285.10:28:49.41#ibcon#about to read 6, iclass 40, count 2 2006.285.10:28:49.41#ibcon#read 6, iclass 40, count 2 2006.285.10:28:49.41#ibcon#end of sib2, iclass 40, count 2 2006.285.10:28:49.41#ibcon#*after write, iclass 40, count 2 2006.285.10:28:49.41#ibcon#*before return 0, iclass 40, count 2 2006.285.10:28:49.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:28:49.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:28:49.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.10:28:49.41#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:49.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:28:49.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:28:49.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:28:49.53#ibcon#enter wrdev, iclass 40, count 0 2006.285.10:28:49.53#ibcon#first serial, iclass 40, count 0 2006.285.10:28:49.53#ibcon#enter sib2, iclass 40, count 0 2006.285.10:28:49.53#ibcon#flushed, iclass 40, count 0 2006.285.10:28:49.53#ibcon#about to write, iclass 40, count 0 2006.285.10:28:49.53#ibcon#wrote, iclass 40, count 0 2006.285.10:28:49.53#ibcon#about to read 3, iclass 40, count 0 2006.285.10:28:49.55#ibcon#read 3, iclass 40, count 0 2006.285.10:28:49.55#ibcon#about to read 4, iclass 40, count 0 2006.285.10:28:49.55#ibcon#read 4, iclass 40, count 0 2006.285.10:28:49.55#ibcon#about to read 5, iclass 40, count 0 2006.285.10:28:49.55#ibcon#read 5, iclass 40, count 0 2006.285.10:28:49.55#ibcon#about to read 6, iclass 40, count 0 2006.285.10:28:49.55#ibcon#read 6, iclass 40, count 0 2006.285.10:28:49.55#ibcon#end of sib2, iclass 40, count 0 2006.285.10:28:49.55#ibcon#*mode == 0, iclass 40, count 0 2006.285.10:28:49.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.10:28:49.55#ibcon#[25=USB\r\n] 2006.285.10:28:49.55#ibcon#*before write, iclass 40, count 0 2006.285.10:28:49.55#ibcon#enter sib2, iclass 40, count 0 2006.285.10:28:49.55#ibcon#flushed, iclass 40, count 0 2006.285.10:28:49.55#ibcon#about to write, iclass 40, count 0 2006.285.10:28:49.55#ibcon#wrote, iclass 40, count 0 2006.285.10:28:49.55#ibcon#about to read 3, iclass 40, count 0 2006.285.10:28:49.58#ibcon#read 3, iclass 40, count 0 2006.285.10:28:49.58#ibcon#about to read 4, iclass 40, count 0 2006.285.10:28:49.58#ibcon#read 4, iclass 40, count 0 2006.285.10:28:49.58#ibcon#about to read 5, iclass 40, count 0 2006.285.10:28:49.58#ibcon#read 5, iclass 40, count 0 2006.285.10:28:49.58#ibcon#about to read 6, iclass 40, count 0 2006.285.10:28:49.58#ibcon#read 6, iclass 40, count 0 2006.285.10:28:49.58#ibcon#end of sib2, iclass 40, count 0 2006.285.10:28:49.58#ibcon#*after write, iclass 40, count 0 2006.285.10:28:49.58#ibcon#*before return 0, iclass 40, count 0 2006.285.10:28:49.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:28:49.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:28:49.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.10:28:49.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.10:28:49.58$vck44/vblo=1,629.99 2006.285.10:28:49.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.10:28:49.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.10:28:49.58#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:49.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:28:49.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:28:49.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:28:49.58#ibcon#enter wrdev, iclass 4, count 0 2006.285.10:28:49.58#ibcon#first serial, iclass 4, count 0 2006.285.10:28:49.58#ibcon#enter sib2, iclass 4, count 0 2006.285.10:28:49.58#ibcon#flushed, iclass 4, count 0 2006.285.10:28:49.58#ibcon#about to write, iclass 4, count 0 2006.285.10:28:49.58#ibcon#wrote, iclass 4, count 0 2006.285.10:28:49.58#ibcon#about to read 3, iclass 4, count 0 2006.285.10:28:49.60#ibcon#read 3, iclass 4, count 0 2006.285.10:28:49.60#ibcon#about to read 4, iclass 4, count 0 2006.285.10:28:49.60#ibcon#read 4, iclass 4, count 0 2006.285.10:28:49.60#ibcon#about to read 5, iclass 4, count 0 2006.285.10:28:49.60#ibcon#read 5, iclass 4, count 0 2006.285.10:28:49.60#ibcon#about to read 6, iclass 4, count 0 2006.285.10:28:49.60#ibcon#read 6, iclass 4, count 0 2006.285.10:28:49.60#ibcon#end of sib2, iclass 4, count 0 2006.285.10:28:49.60#ibcon#*mode == 0, iclass 4, count 0 2006.285.10:28:49.60#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.10:28:49.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:28:49.60#ibcon#*before write, iclass 4, count 0 2006.285.10:28:49.60#ibcon#enter sib2, iclass 4, count 0 2006.285.10:28:49.60#ibcon#flushed, iclass 4, count 0 2006.285.10:28:49.60#ibcon#about to write, iclass 4, count 0 2006.285.10:28:49.60#ibcon#wrote, iclass 4, count 0 2006.285.10:28:49.60#ibcon#about to read 3, iclass 4, count 0 2006.285.10:28:49.64#ibcon#read 3, iclass 4, count 0 2006.285.10:28:49.64#ibcon#about to read 4, iclass 4, count 0 2006.285.10:28:49.64#ibcon#read 4, iclass 4, count 0 2006.285.10:28:49.64#ibcon#about to read 5, iclass 4, count 0 2006.285.10:28:49.64#ibcon#read 5, iclass 4, count 0 2006.285.10:28:49.64#ibcon#about to read 6, iclass 4, count 0 2006.285.10:28:49.64#ibcon#read 6, iclass 4, count 0 2006.285.10:28:49.64#ibcon#end of sib2, iclass 4, count 0 2006.285.10:28:49.64#ibcon#*after write, iclass 4, count 0 2006.285.10:28:49.64#ibcon#*before return 0, iclass 4, count 0 2006.285.10:28:49.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:28:49.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:28:49.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.10:28:49.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.10:28:49.64$vck44/vb=1,4 2006.285.10:28:49.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.10:28:49.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.10:28:49.64#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:49.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:28:49.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:28:49.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:28:49.64#ibcon#enter wrdev, iclass 6, count 2 2006.285.10:28:49.64#ibcon#first serial, iclass 6, count 2 2006.285.10:28:49.64#ibcon#enter sib2, iclass 6, count 2 2006.285.10:28:49.64#ibcon#flushed, iclass 6, count 2 2006.285.10:28:49.64#ibcon#about to write, iclass 6, count 2 2006.285.10:28:49.64#ibcon#wrote, iclass 6, count 2 2006.285.10:28:49.64#ibcon#about to read 3, iclass 6, count 2 2006.285.10:28:49.66#ibcon#read 3, iclass 6, count 2 2006.285.10:28:49.66#ibcon#about to read 4, iclass 6, count 2 2006.285.10:28:49.66#ibcon#read 4, iclass 6, count 2 2006.285.10:28:49.66#ibcon#about to read 5, iclass 6, count 2 2006.285.10:28:49.66#ibcon#read 5, iclass 6, count 2 2006.285.10:28:49.66#ibcon#about to read 6, iclass 6, count 2 2006.285.10:28:49.66#ibcon#read 6, iclass 6, count 2 2006.285.10:28:49.66#ibcon#end of sib2, iclass 6, count 2 2006.285.10:28:49.66#ibcon#*mode == 0, iclass 6, count 2 2006.285.10:28:49.66#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.10:28:49.66#ibcon#[27=AT01-04\r\n] 2006.285.10:28:49.66#ibcon#*before write, iclass 6, count 2 2006.285.10:28:49.66#ibcon#enter sib2, iclass 6, count 2 2006.285.10:28:49.66#ibcon#flushed, iclass 6, count 2 2006.285.10:28:49.66#ibcon#about to write, iclass 6, count 2 2006.285.10:28:49.66#ibcon#wrote, iclass 6, count 2 2006.285.10:28:49.66#ibcon#about to read 3, iclass 6, count 2 2006.285.10:28:49.69#ibcon#read 3, iclass 6, count 2 2006.285.10:28:49.69#ibcon#about to read 4, iclass 6, count 2 2006.285.10:28:49.69#ibcon#read 4, iclass 6, count 2 2006.285.10:28:49.69#ibcon#about to read 5, iclass 6, count 2 2006.285.10:28:49.69#ibcon#read 5, iclass 6, count 2 2006.285.10:28:49.69#ibcon#about to read 6, iclass 6, count 2 2006.285.10:28:49.69#ibcon#read 6, iclass 6, count 2 2006.285.10:28:49.69#ibcon#end of sib2, iclass 6, count 2 2006.285.10:28:49.69#ibcon#*after write, iclass 6, count 2 2006.285.10:28:49.69#ibcon#*before return 0, iclass 6, count 2 2006.285.10:28:49.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:28:49.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:28:49.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.10:28:49.69#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:49.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:28:49.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:28:49.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:28:49.81#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:28:49.81#ibcon#first serial, iclass 6, count 0 2006.285.10:28:49.81#ibcon#enter sib2, iclass 6, count 0 2006.285.10:28:49.81#ibcon#flushed, iclass 6, count 0 2006.285.10:28:49.81#ibcon#about to write, iclass 6, count 0 2006.285.10:28:49.81#ibcon#wrote, iclass 6, count 0 2006.285.10:28:49.81#ibcon#about to read 3, iclass 6, count 0 2006.285.10:28:49.83#ibcon#read 3, iclass 6, count 0 2006.285.10:28:49.83#ibcon#about to read 4, iclass 6, count 0 2006.285.10:28:49.83#ibcon#read 4, iclass 6, count 0 2006.285.10:28:49.83#ibcon#about to read 5, iclass 6, count 0 2006.285.10:28:49.83#ibcon#read 5, iclass 6, count 0 2006.285.10:28:49.83#ibcon#about to read 6, iclass 6, count 0 2006.285.10:28:49.83#ibcon#read 6, iclass 6, count 0 2006.285.10:28:49.83#ibcon#end of sib2, iclass 6, count 0 2006.285.10:28:49.83#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:28:49.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:28:49.83#ibcon#[27=USB\r\n] 2006.285.10:28:49.83#ibcon#*before write, iclass 6, count 0 2006.285.10:28:49.83#ibcon#enter sib2, iclass 6, count 0 2006.285.10:28:49.83#ibcon#flushed, iclass 6, count 0 2006.285.10:28:49.83#ibcon#about to write, iclass 6, count 0 2006.285.10:28:49.83#ibcon#wrote, iclass 6, count 0 2006.285.10:28:49.83#ibcon#about to read 3, iclass 6, count 0 2006.285.10:28:49.86#ibcon#read 3, iclass 6, count 0 2006.285.10:28:49.86#ibcon#about to read 4, iclass 6, count 0 2006.285.10:28:49.86#ibcon#read 4, iclass 6, count 0 2006.285.10:28:49.86#ibcon#about to read 5, iclass 6, count 0 2006.285.10:28:49.86#ibcon#read 5, iclass 6, count 0 2006.285.10:28:49.86#ibcon#about to read 6, iclass 6, count 0 2006.285.10:28:49.86#ibcon#read 6, iclass 6, count 0 2006.285.10:28:49.86#ibcon#end of sib2, iclass 6, count 0 2006.285.10:28:49.86#ibcon#*after write, iclass 6, count 0 2006.285.10:28:49.86#ibcon#*before return 0, iclass 6, count 0 2006.285.10:28:49.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:28:49.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:28:49.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:28:49.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:28:49.86$vck44/vblo=2,634.99 2006.285.10:28:49.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.10:28:49.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.10:28:49.86#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:49.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:28:49.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:28:49.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:28:49.86#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:28:49.86#ibcon#first serial, iclass 10, count 0 2006.285.10:28:49.86#ibcon#enter sib2, iclass 10, count 0 2006.285.10:28:49.86#ibcon#flushed, iclass 10, count 0 2006.285.10:28:49.86#ibcon#about to write, iclass 10, count 0 2006.285.10:28:49.86#ibcon#wrote, iclass 10, count 0 2006.285.10:28:49.86#ibcon#about to read 3, iclass 10, count 0 2006.285.10:28:49.88#ibcon#read 3, iclass 10, count 0 2006.285.10:28:49.88#ibcon#about to read 4, iclass 10, count 0 2006.285.10:28:49.88#ibcon#read 4, iclass 10, count 0 2006.285.10:28:49.88#ibcon#about to read 5, iclass 10, count 0 2006.285.10:28:49.88#ibcon#read 5, iclass 10, count 0 2006.285.10:28:49.88#ibcon#about to read 6, iclass 10, count 0 2006.285.10:28:49.88#ibcon#read 6, iclass 10, count 0 2006.285.10:28:49.88#ibcon#end of sib2, iclass 10, count 0 2006.285.10:28:49.88#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:28:49.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:28:49.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:28:49.88#ibcon#*before write, iclass 10, count 0 2006.285.10:28:49.88#ibcon#enter sib2, iclass 10, count 0 2006.285.10:28:49.88#ibcon#flushed, iclass 10, count 0 2006.285.10:28:49.88#ibcon#about to write, iclass 10, count 0 2006.285.10:28:49.88#ibcon#wrote, iclass 10, count 0 2006.285.10:28:49.88#ibcon#about to read 3, iclass 10, count 0 2006.285.10:28:49.92#ibcon#read 3, iclass 10, count 0 2006.285.10:28:49.92#ibcon#about to read 4, iclass 10, count 0 2006.285.10:28:49.92#ibcon#read 4, iclass 10, count 0 2006.285.10:28:49.92#ibcon#about to read 5, iclass 10, count 0 2006.285.10:28:49.92#ibcon#read 5, iclass 10, count 0 2006.285.10:28:49.92#ibcon#about to read 6, iclass 10, count 0 2006.285.10:28:49.92#ibcon#read 6, iclass 10, count 0 2006.285.10:28:49.92#ibcon#end of sib2, iclass 10, count 0 2006.285.10:28:49.92#ibcon#*after write, iclass 10, count 0 2006.285.10:28:49.92#ibcon#*before return 0, iclass 10, count 0 2006.285.10:28:49.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:28:49.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:28:49.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:28:49.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:28:49.92$vck44/vb=2,5 2006.285.10:28:49.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.10:28:49.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.10:28:49.92#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:49.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:28:49.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:28:49.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:28:49.98#ibcon#enter wrdev, iclass 12, count 2 2006.285.10:28:49.98#ibcon#first serial, iclass 12, count 2 2006.285.10:28:49.98#ibcon#enter sib2, iclass 12, count 2 2006.285.10:28:49.98#ibcon#flushed, iclass 12, count 2 2006.285.10:28:49.98#ibcon#about to write, iclass 12, count 2 2006.285.10:28:49.98#ibcon#wrote, iclass 12, count 2 2006.285.10:28:49.98#ibcon#about to read 3, iclass 12, count 2 2006.285.10:28:50.00#ibcon#read 3, iclass 12, count 2 2006.285.10:28:50.00#ibcon#about to read 4, iclass 12, count 2 2006.285.10:28:50.00#ibcon#read 4, iclass 12, count 2 2006.285.10:28:50.00#ibcon#about to read 5, iclass 12, count 2 2006.285.10:28:50.00#ibcon#read 5, iclass 12, count 2 2006.285.10:28:50.00#ibcon#about to read 6, iclass 12, count 2 2006.285.10:28:50.00#ibcon#read 6, iclass 12, count 2 2006.285.10:28:50.00#ibcon#end of sib2, iclass 12, count 2 2006.285.10:28:50.00#ibcon#*mode == 0, iclass 12, count 2 2006.285.10:28:50.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.10:28:50.00#ibcon#[27=AT02-05\r\n] 2006.285.10:28:50.00#ibcon#*before write, iclass 12, count 2 2006.285.10:28:50.00#ibcon#enter sib2, iclass 12, count 2 2006.285.10:28:50.00#ibcon#flushed, iclass 12, count 2 2006.285.10:28:50.00#ibcon#about to write, iclass 12, count 2 2006.285.10:28:50.00#ibcon#wrote, iclass 12, count 2 2006.285.10:28:50.00#ibcon#about to read 3, iclass 12, count 2 2006.285.10:28:50.03#ibcon#read 3, iclass 12, count 2 2006.285.10:28:50.03#ibcon#about to read 4, iclass 12, count 2 2006.285.10:28:50.03#ibcon#read 4, iclass 12, count 2 2006.285.10:28:50.03#ibcon#about to read 5, iclass 12, count 2 2006.285.10:28:50.03#ibcon#read 5, iclass 12, count 2 2006.285.10:28:50.03#ibcon#about to read 6, iclass 12, count 2 2006.285.10:28:50.03#ibcon#read 6, iclass 12, count 2 2006.285.10:28:50.03#ibcon#end of sib2, iclass 12, count 2 2006.285.10:28:50.03#ibcon#*after write, iclass 12, count 2 2006.285.10:28:50.03#ibcon#*before return 0, iclass 12, count 2 2006.285.10:28:50.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:28:50.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:28:50.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.10:28:50.03#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:50.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:28:50.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:28:50.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:28:50.15#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:28:50.15#ibcon#first serial, iclass 12, count 0 2006.285.10:28:50.15#ibcon#enter sib2, iclass 12, count 0 2006.285.10:28:50.15#ibcon#flushed, iclass 12, count 0 2006.285.10:28:50.15#ibcon#about to write, iclass 12, count 0 2006.285.10:28:50.15#ibcon#wrote, iclass 12, count 0 2006.285.10:28:50.15#ibcon#about to read 3, iclass 12, count 0 2006.285.10:28:50.17#ibcon#read 3, iclass 12, count 0 2006.285.10:28:50.17#ibcon#about to read 4, iclass 12, count 0 2006.285.10:28:50.17#ibcon#read 4, iclass 12, count 0 2006.285.10:28:50.17#ibcon#about to read 5, iclass 12, count 0 2006.285.10:28:50.17#ibcon#read 5, iclass 12, count 0 2006.285.10:28:50.17#ibcon#about to read 6, iclass 12, count 0 2006.285.10:28:50.17#ibcon#read 6, iclass 12, count 0 2006.285.10:28:50.17#ibcon#end of sib2, iclass 12, count 0 2006.285.10:28:50.17#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:28:50.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:28:50.17#ibcon#[27=USB\r\n] 2006.285.10:28:50.17#ibcon#*before write, iclass 12, count 0 2006.285.10:28:50.17#ibcon#enter sib2, iclass 12, count 0 2006.285.10:28:50.17#ibcon#flushed, iclass 12, count 0 2006.285.10:28:50.17#ibcon#about to write, iclass 12, count 0 2006.285.10:28:50.17#ibcon#wrote, iclass 12, count 0 2006.285.10:28:50.17#ibcon#about to read 3, iclass 12, count 0 2006.285.10:28:50.20#ibcon#read 3, iclass 12, count 0 2006.285.10:28:50.20#ibcon#about to read 4, iclass 12, count 0 2006.285.10:28:50.20#ibcon#read 4, iclass 12, count 0 2006.285.10:28:50.20#ibcon#about to read 5, iclass 12, count 0 2006.285.10:28:50.20#ibcon#read 5, iclass 12, count 0 2006.285.10:28:50.20#ibcon#about to read 6, iclass 12, count 0 2006.285.10:28:50.20#ibcon#read 6, iclass 12, count 0 2006.285.10:28:50.20#ibcon#end of sib2, iclass 12, count 0 2006.285.10:28:50.20#ibcon#*after write, iclass 12, count 0 2006.285.10:28:50.20#ibcon#*before return 0, iclass 12, count 0 2006.285.10:28:50.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:28:50.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:28:50.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:28:50.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:28:50.20$vck44/vblo=3,649.99 2006.285.10:28:50.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.10:28:50.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.10:28:50.20#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:50.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:28:50.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:28:50.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:28:50.20#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:28:50.20#ibcon#first serial, iclass 14, count 0 2006.285.10:28:50.20#ibcon#enter sib2, iclass 14, count 0 2006.285.10:28:50.20#ibcon#flushed, iclass 14, count 0 2006.285.10:28:50.20#ibcon#about to write, iclass 14, count 0 2006.285.10:28:50.20#ibcon#wrote, iclass 14, count 0 2006.285.10:28:50.20#ibcon#about to read 3, iclass 14, count 0 2006.285.10:28:50.22#ibcon#read 3, iclass 14, count 0 2006.285.10:28:50.22#ibcon#about to read 4, iclass 14, count 0 2006.285.10:28:50.22#ibcon#read 4, iclass 14, count 0 2006.285.10:28:50.22#ibcon#about to read 5, iclass 14, count 0 2006.285.10:28:50.22#ibcon#read 5, iclass 14, count 0 2006.285.10:28:50.22#ibcon#about to read 6, iclass 14, count 0 2006.285.10:28:50.22#ibcon#read 6, iclass 14, count 0 2006.285.10:28:50.22#ibcon#end of sib2, iclass 14, count 0 2006.285.10:28:50.22#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:28:50.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:28:50.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:28:50.22#ibcon#*before write, iclass 14, count 0 2006.285.10:28:50.22#ibcon#enter sib2, iclass 14, count 0 2006.285.10:28:50.22#ibcon#flushed, iclass 14, count 0 2006.285.10:28:50.22#ibcon#about to write, iclass 14, count 0 2006.285.10:28:50.22#ibcon#wrote, iclass 14, count 0 2006.285.10:28:50.22#ibcon#about to read 3, iclass 14, count 0 2006.285.10:28:50.26#ibcon#read 3, iclass 14, count 0 2006.285.10:28:50.26#ibcon#about to read 4, iclass 14, count 0 2006.285.10:28:50.26#ibcon#read 4, iclass 14, count 0 2006.285.10:28:50.26#ibcon#about to read 5, iclass 14, count 0 2006.285.10:28:50.26#ibcon#read 5, iclass 14, count 0 2006.285.10:28:50.26#ibcon#about to read 6, iclass 14, count 0 2006.285.10:28:50.26#ibcon#read 6, iclass 14, count 0 2006.285.10:28:50.26#ibcon#end of sib2, iclass 14, count 0 2006.285.10:28:50.26#ibcon#*after write, iclass 14, count 0 2006.285.10:28:50.26#ibcon#*before return 0, iclass 14, count 0 2006.285.10:28:50.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:28:50.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:28:50.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:28:50.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:28:50.26$vck44/vb=3,4 2006.285.10:28:50.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.10:28:50.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.10:28:50.26#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:50.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:28:50.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:28:50.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:28:50.32#ibcon#enter wrdev, iclass 16, count 2 2006.285.10:28:50.32#ibcon#first serial, iclass 16, count 2 2006.285.10:28:50.32#ibcon#enter sib2, iclass 16, count 2 2006.285.10:28:50.32#ibcon#flushed, iclass 16, count 2 2006.285.10:28:50.32#ibcon#about to write, iclass 16, count 2 2006.285.10:28:50.32#ibcon#wrote, iclass 16, count 2 2006.285.10:28:50.32#ibcon#about to read 3, iclass 16, count 2 2006.285.10:28:50.34#ibcon#read 3, iclass 16, count 2 2006.285.10:28:50.34#ibcon#about to read 4, iclass 16, count 2 2006.285.10:28:50.34#ibcon#read 4, iclass 16, count 2 2006.285.10:28:50.34#ibcon#about to read 5, iclass 16, count 2 2006.285.10:28:50.34#ibcon#read 5, iclass 16, count 2 2006.285.10:28:50.34#ibcon#about to read 6, iclass 16, count 2 2006.285.10:28:50.34#ibcon#read 6, iclass 16, count 2 2006.285.10:28:50.34#ibcon#end of sib2, iclass 16, count 2 2006.285.10:28:50.34#ibcon#*mode == 0, iclass 16, count 2 2006.285.10:28:50.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.10:28:50.34#ibcon#[27=AT03-04\r\n] 2006.285.10:28:50.34#ibcon#*before write, iclass 16, count 2 2006.285.10:28:50.34#ibcon#enter sib2, iclass 16, count 2 2006.285.10:28:50.34#ibcon#flushed, iclass 16, count 2 2006.285.10:28:50.34#ibcon#about to write, iclass 16, count 2 2006.285.10:28:50.34#ibcon#wrote, iclass 16, count 2 2006.285.10:28:50.34#ibcon#about to read 3, iclass 16, count 2 2006.285.10:28:50.37#ibcon#read 3, iclass 16, count 2 2006.285.10:28:50.37#ibcon#about to read 4, iclass 16, count 2 2006.285.10:28:50.37#ibcon#read 4, iclass 16, count 2 2006.285.10:28:50.37#ibcon#about to read 5, iclass 16, count 2 2006.285.10:28:50.37#ibcon#read 5, iclass 16, count 2 2006.285.10:28:50.37#ibcon#about to read 6, iclass 16, count 2 2006.285.10:28:50.37#ibcon#read 6, iclass 16, count 2 2006.285.10:28:50.37#ibcon#end of sib2, iclass 16, count 2 2006.285.10:28:50.37#ibcon#*after write, iclass 16, count 2 2006.285.10:28:50.37#ibcon#*before return 0, iclass 16, count 2 2006.285.10:28:50.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:28:50.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:28:50.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.10:28:50.37#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:50.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:28:50.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:28:50.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:28:50.49#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:28:50.49#ibcon#first serial, iclass 16, count 0 2006.285.10:28:50.49#ibcon#enter sib2, iclass 16, count 0 2006.285.10:28:50.49#ibcon#flushed, iclass 16, count 0 2006.285.10:28:50.49#ibcon#about to write, iclass 16, count 0 2006.285.10:28:50.49#ibcon#wrote, iclass 16, count 0 2006.285.10:28:50.49#ibcon#about to read 3, iclass 16, count 0 2006.285.10:28:50.51#ibcon#read 3, iclass 16, count 0 2006.285.10:28:50.51#ibcon#about to read 4, iclass 16, count 0 2006.285.10:28:50.51#ibcon#read 4, iclass 16, count 0 2006.285.10:28:50.51#ibcon#about to read 5, iclass 16, count 0 2006.285.10:28:50.51#ibcon#read 5, iclass 16, count 0 2006.285.10:28:50.51#ibcon#about to read 6, iclass 16, count 0 2006.285.10:28:50.51#ibcon#read 6, iclass 16, count 0 2006.285.10:28:50.51#ibcon#end of sib2, iclass 16, count 0 2006.285.10:28:50.51#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:28:50.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:28:50.51#ibcon#[27=USB\r\n] 2006.285.10:28:50.51#ibcon#*before write, iclass 16, count 0 2006.285.10:28:50.51#ibcon#enter sib2, iclass 16, count 0 2006.285.10:28:50.51#ibcon#flushed, iclass 16, count 0 2006.285.10:28:50.51#ibcon#about to write, iclass 16, count 0 2006.285.10:28:50.51#ibcon#wrote, iclass 16, count 0 2006.285.10:28:50.51#ibcon#about to read 3, iclass 16, count 0 2006.285.10:28:50.54#ibcon#read 3, iclass 16, count 0 2006.285.10:28:50.54#ibcon#about to read 4, iclass 16, count 0 2006.285.10:28:50.54#ibcon#read 4, iclass 16, count 0 2006.285.10:28:50.54#ibcon#about to read 5, iclass 16, count 0 2006.285.10:28:50.54#ibcon#read 5, iclass 16, count 0 2006.285.10:28:50.54#ibcon#about to read 6, iclass 16, count 0 2006.285.10:28:50.54#ibcon#read 6, iclass 16, count 0 2006.285.10:28:50.54#ibcon#end of sib2, iclass 16, count 0 2006.285.10:28:50.54#ibcon#*after write, iclass 16, count 0 2006.285.10:28:50.54#ibcon#*before return 0, iclass 16, count 0 2006.285.10:28:50.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:28:50.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:28:50.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:28:50.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:28:50.54$vck44/vblo=4,679.99 2006.285.10:28:50.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.10:28:50.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.10:28:50.54#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:50.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:28:50.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:28:50.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:28:50.54#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:28:50.54#ibcon#first serial, iclass 18, count 0 2006.285.10:28:50.54#ibcon#enter sib2, iclass 18, count 0 2006.285.10:28:50.54#ibcon#flushed, iclass 18, count 0 2006.285.10:28:50.54#ibcon#about to write, iclass 18, count 0 2006.285.10:28:50.54#ibcon#wrote, iclass 18, count 0 2006.285.10:28:50.54#ibcon#about to read 3, iclass 18, count 0 2006.285.10:28:50.56#ibcon#read 3, iclass 18, count 0 2006.285.10:28:50.56#ibcon#about to read 4, iclass 18, count 0 2006.285.10:28:50.56#ibcon#read 4, iclass 18, count 0 2006.285.10:28:50.56#ibcon#about to read 5, iclass 18, count 0 2006.285.10:28:50.56#ibcon#read 5, iclass 18, count 0 2006.285.10:28:50.56#ibcon#about to read 6, iclass 18, count 0 2006.285.10:28:50.56#ibcon#read 6, iclass 18, count 0 2006.285.10:28:50.56#ibcon#end of sib2, iclass 18, count 0 2006.285.10:28:50.56#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:28:50.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:28:50.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:28:50.56#ibcon#*before write, iclass 18, count 0 2006.285.10:28:50.56#ibcon#enter sib2, iclass 18, count 0 2006.285.10:28:50.56#ibcon#flushed, iclass 18, count 0 2006.285.10:28:50.56#ibcon#about to write, iclass 18, count 0 2006.285.10:28:50.56#ibcon#wrote, iclass 18, count 0 2006.285.10:28:50.56#ibcon#about to read 3, iclass 18, count 0 2006.285.10:28:50.60#ibcon#read 3, iclass 18, count 0 2006.285.10:28:50.60#ibcon#about to read 4, iclass 18, count 0 2006.285.10:28:50.60#ibcon#read 4, iclass 18, count 0 2006.285.10:28:50.60#ibcon#about to read 5, iclass 18, count 0 2006.285.10:28:50.60#ibcon#read 5, iclass 18, count 0 2006.285.10:28:50.60#ibcon#about to read 6, iclass 18, count 0 2006.285.10:28:50.60#ibcon#read 6, iclass 18, count 0 2006.285.10:28:50.60#ibcon#end of sib2, iclass 18, count 0 2006.285.10:28:50.60#ibcon#*after write, iclass 18, count 0 2006.285.10:28:50.60#ibcon#*before return 0, iclass 18, count 0 2006.285.10:28:50.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:28:50.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:28:50.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:28:50.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:28:50.60$vck44/vb=4,5 2006.285.10:28:50.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.10:28:50.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.10:28:50.60#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:50.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:28:50.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:28:50.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:28:50.66#ibcon#enter wrdev, iclass 20, count 2 2006.285.10:28:50.66#ibcon#first serial, iclass 20, count 2 2006.285.10:28:50.66#ibcon#enter sib2, iclass 20, count 2 2006.285.10:28:50.66#ibcon#flushed, iclass 20, count 2 2006.285.10:28:50.66#ibcon#about to write, iclass 20, count 2 2006.285.10:28:50.66#ibcon#wrote, iclass 20, count 2 2006.285.10:28:50.66#ibcon#about to read 3, iclass 20, count 2 2006.285.10:28:50.68#ibcon#read 3, iclass 20, count 2 2006.285.10:28:50.68#ibcon#about to read 4, iclass 20, count 2 2006.285.10:28:50.68#ibcon#read 4, iclass 20, count 2 2006.285.10:28:50.68#ibcon#about to read 5, iclass 20, count 2 2006.285.10:28:50.68#ibcon#read 5, iclass 20, count 2 2006.285.10:28:50.68#ibcon#about to read 6, iclass 20, count 2 2006.285.10:28:50.68#ibcon#read 6, iclass 20, count 2 2006.285.10:28:50.68#ibcon#end of sib2, iclass 20, count 2 2006.285.10:28:50.68#ibcon#*mode == 0, iclass 20, count 2 2006.285.10:28:50.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.10:28:50.68#ibcon#[27=AT04-05\r\n] 2006.285.10:28:50.68#ibcon#*before write, iclass 20, count 2 2006.285.10:28:50.68#ibcon#enter sib2, iclass 20, count 2 2006.285.10:28:50.68#ibcon#flushed, iclass 20, count 2 2006.285.10:28:50.68#ibcon#about to write, iclass 20, count 2 2006.285.10:28:50.68#ibcon#wrote, iclass 20, count 2 2006.285.10:28:50.68#ibcon#about to read 3, iclass 20, count 2 2006.285.10:28:50.71#ibcon#read 3, iclass 20, count 2 2006.285.10:28:50.71#ibcon#about to read 4, iclass 20, count 2 2006.285.10:28:50.71#ibcon#read 4, iclass 20, count 2 2006.285.10:28:50.71#ibcon#about to read 5, iclass 20, count 2 2006.285.10:28:50.71#ibcon#read 5, iclass 20, count 2 2006.285.10:28:50.71#ibcon#about to read 6, iclass 20, count 2 2006.285.10:28:50.71#ibcon#read 6, iclass 20, count 2 2006.285.10:28:50.71#ibcon#end of sib2, iclass 20, count 2 2006.285.10:28:50.71#ibcon#*after write, iclass 20, count 2 2006.285.10:28:50.71#ibcon#*before return 0, iclass 20, count 2 2006.285.10:28:50.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:28:50.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:28:50.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.10:28:50.71#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:50.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:28:50.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:28:50.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:28:50.83#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:28:50.83#ibcon#first serial, iclass 20, count 0 2006.285.10:28:50.83#ibcon#enter sib2, iclass 20, count 0 2006.285.10:28:50.83#ibcon#flushed, iclass 20, count 0 2006.285.10:28:50.83#ibcon#about to write, iclass 20, count 0 2006.285.10:28:50.83#ibcon#wrote, iclass 20, count 0 2006.285.10:28:50.83#ibcon#about to read 3, iclass 20, count 0 2006.285.10:28:50.85#ibcon#read 3, iclass 20, count 0 2006.285.10:28:50.85#ibcon#about to read 4, iclass 20, count 0 2006.285.10:28:50.85#ibcon#read 4, iclass 20, count 0 2006.285.10:28:50.85#ibcon#about to read 5, iclass 20, count 0 2006.285.10:28:50.85#ibcon#read 5, iclass 20, count 0 2006.285.10:28:50.85#ibcon#about to read 6, iclass 20, count 0 2006.285.10:28:50.85#ibcon#read 6, iclass 20, count 0 2006.285.10:28:50.85#ibcon#end of sib2, iclass 20, count 0 2006.285.10:28:50.85#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:28:50.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:28:50.85#ibcon#[27=USB\r\n] 2006.285.10:28:50.85#ibcon#*before write, iclass 20, count 0 2006.285.10:28:50.85#ibcon#enter sib2, iclass 20, count 0 2006.285.10:28:50.85#ibcon#flushed, iclass 20, count 0 2006.285.10:28:50.85#ibcon#about to write, iclass 20, count 0 2006.285.10:28:50.85#ibcon#wrote, iclass 20, count 0 2006.285.10:28:50.85#ibcon#about to read 3, iclass 20, count 0 2006.285.10:28:50.88#ibcon#read 3, iclass 20, count 0 2006.285.10:28:50.88#ibcon#about to read 4, iclass 20, count 0 2006.285.10:28:50.88#ibcon#read 4, iclass 20, count 0 2006.285.10:28:50.88#ibcon#about to read 5, iclass 20, count 0 2006.285.10:28:50.88#ibcon#read 5, iclass 20, count 0 2006.285.10:28:50.88#ibcon#about to read 6, iclass 20, count 0 2006.285.10:28:50.88#ibcon#read 6, iclass 20, count 0 2006.285.10:28:50.88#ibcon#end of sib2, iclass 20, count 0 2006.285.10:28:50.88#ibcon#*after write, iclass 20, count 0 2006.285.10:28:50.88#ibcon#*before return 0, iclass 20, count 0 2006.285.10:28:50.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:28:50.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:28:50.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:28:50.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:28:50.88$vck44/vblo=5,709.99 2006.285.10:28:50.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.10:28:50.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.10:28:50.88#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:50.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:28:50.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:28:50.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:28:50.88#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:28:50.88#ibcon#first serial, iclass 22, count 0 2006.285.10:28:50.88#ibcon#enter sib2, iclass 22, count 0 2006.285.10:28:50.88#ibcon#flushed, iclass 22, count 0 2006.285.10:28:50.88#ibcon#about to write, iclass 22, count 0 2006.285.10:28:50.88#ibcon#wrote, iclass 22, count 0 2006.285.10:28:50.88#ibcon#about to read 3, iclass 22, count 0 2006.285.10:28:50.90#ibcon#read 3, iclass 22, count 0 2006.285.10:28:50.90#ibcon#about to read 4, iclass 22, count 0 2006.285.10:28:50.90#ibcon#read 4, iclass 22, count 0 2006.285.10:28:50.90#ibcon#about to read 5, iclass 22, count 0 2006.285.10:28:50.90#ibcon#read 5, iclass 22, count 0 2006.285.10:28:50.90#ibcon#about to read 6, iclass 22, count 0 2006.285.10:28:50.90#ibcon#read 6, iclass 22, count 0 2006.285.10:28:50.90#ibcon#end of sib2, iclass 22, count 0 2006.285.10:28:50.90#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:28:50.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:28:50.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:28:50.90#ibcon#*before write, iclass 22, count 0 2006.285.10:28:50.90#ibcon#enter sib2, iclass 22, count 0 2006.285.10:28:50.90#ibcon#flushed, iclass 22, count 0 2006.285.10:28:50.90#ibcon#about to write, iclass 22, count 0 2006.285.10:28:50.90#ibcon#wrote, iclass 22, count 0 2006.285.10:28:50.90#ibcon#about to read 3, iclass 22, count 0 2006.285.10:28:50.94#ibcon#read 3, iclass 22, count 0 2006.285.10:28:50.94#ibcon#about to read 4, iclass 22, count 0 2006.285.10:28:50.94#ibcon#read 4, iclass 22, count 0 2006.285.10:28:50.94#ibcon#about to read 5, iclass 22, count 0 2006.285.10:28:50.94#ibcon#read 5, iclass 22, count 0 2006.285.10:28:50.94#ibcon#about to read 6, iclass 22, count 0 2006.285.10:28:50.94#ibcon#read 6, iclass 22, count 0 2006.285.10:28:50.94#ibcon#end of sib2, iclass 22, count 0 2006.285.10:28:50.94#ibcon#*after write, iclass 22, count 0 2006.285.10:28:50.94#ibcon#*before return 0, iclass 22, count 0 2006.285.10:28:50.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:28:50.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:28:50.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:28:50.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:28:50.94$vck44/vb=5,4 2006.285.10:28:50.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.10:28:50.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.10:28:50.94#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:50.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:28:51.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:28:51.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:28:51.00#ibcon#enter wrdev, iclass 24, count 2 2006.285.10:28:51.00#ibcon#first serial, iclass 24, count 2 2006.285.10:28:51.00#ibcon#enter sib2, iclass 24, count 2 2006.285.10:28:51.00#ibcon#flushed, iclass 24, count 2 2006.285.10:28:51.00#ibcon#about to write, iclass 24, count 2 2006.285.10:28:51.00#ibcon#wrote, iclass 24, count 2 2006.285.10:28:51.00#ibcon#about to read 3, iclass 24, count 2 2006.285.10:28:51.02#ibcon#read 3, iclass 24, count 2 2006.285.10:28:51.02#ibcon#about to read 4, iclass 24, count 2 2006.285.10:28:51.02#ibcon#read 4, iclass 24, count 2 2006.285.10:28:51.02#ibcon#about to read 5, iclass 24, count 2 2006.285.10:28:51.02#ibcon#read 5, iclass 24, count 2 2006.285.10:28:51.02#ibcon#about to read 6, iclass 24, count 2 2006.285.10:28:51.02#ibcon#read 6, iclass 24, count 2 2006.285.10:28:51.02#ibcon#end of sib2, iclass 24, count 2 2006.285.10:28:51.02#ibcon#*mode == 0, iclass 24, count 2 2006.285.10:28:51.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.10:28:51.02#ibcon#[27=AT05-04\r\n] 2006.285.10:28:51.02#ibcon#*before write, iclass 24, count 2 2006.285.10:28:51.02#ibcon#enter sib2, iclass 24, count 2 2006.285.10:28:51.02#ibcon#flushed, iclass 24, count 2 2006.285.10:28:51.02#ibcon#about to write, iclass 24, count 2 2006.285.10:28:51.02#ibcon#wrote, iclass 24, count 2 2006.285.10:28:51.02#ibcon#about to read 3, iclass 24, count 2 2006.285.10:28:51.05#ibcon#read 3, iclass 24, count 2 2006.285.10:28:51.05#ibcon#about to read 4, iclass 24, count 2 2006.285.10:28:51.05#ibcon#read 4, iclass 24, count 2 2006.285.10:28:51.05#ibcon#about to read 5, iclass 24, count 2 2006.285.10:28:51.05#ibcon#read 5, iclass 24, count 2 2006.285.10:28:51.05#ibcon#about to read 6, iclass 24, count 2 2006.285.10:28:51.05#ibcon#read 6, iclass 24, count 2 2006.285.10:28:51.05#ibcon#end of sib2, iclass 24, count 2 2006.285.10:28:51.05#ibcon#*after write, iclass 24, count 2 2006.285.10:28:51.05#ibcon#*before return 0, iclass 24, count 2 2006.285.10:28:51.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:28:51.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:28:51.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.10:28:51.05#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:51.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:28:51.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:28:51.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:28:51.17#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:28:51.17#ibcon#first serial, iclass 24, count 0 2006.285.10:28:51.17#ibcon#enter sib2, iclass 24, count 0 2006.285.10:28:51.17#ibcon#flushed, iclass 24, count 0 2006.285.10:28:51.17#ibcon#about to write, iclass 24, count 0 2006.285.10:28:51.17#ibcon#wrote, iclass 24, count 0 2006.285.10:28:51.17#ibcon#about to read 3, iclass 24, count 0 2006.285.10:28:51.19#ibcon#read 3, iclass 24, count 0 2006.285.10:28:51.19#ibcon#about to read 4, iclass 24, count 0 2006.285.10:28:51.19#ibcon#read 4, iclass 24, count 0 2006.285.10:28:51.19#ibcon#about to read 5, iclass 24, count 0 2006.285.10:28:51.19#ibcon#read 5, iclass 24, count 0 2006.285.10:28:51.19#ibcon#about to read 6, iclass 24, count 0 2006.285.10:28:51.19#ibcon#read 6, iclass 24, count 0 2006.285.10:28:51.19#ibcon#end of sib2, iclass 24, count 0 2006.285.10:28:51.19#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:28:51.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:28:51.19#ibcon#[27=USB\r\n] 2006.285.10:28:51.19#ibcon#*before write, iclass 24, count 0 2006.285.10:28:51.19#ibcon#enter sib2, iclass 24, count 0 2006.285.10:28:51.19#ibcon#flushed, iclass 24, count 0 2006.285.10:28:51.19#ibcon#about to write, iclass 24, count 0 2006.285.10:28:51.19#ibcon#wrote, iclass 24, count 0 2006.285.10:28:51.19#ibcon#about to read 3, iclass 24, count 0 2006.285.10:28:51.22#ibcon#read 3, iclass 24, count 0 2006.285.10:28:51.22#ibcon#about to read 4, iclass 24, count 0 2006.285.10:28:51.22#ibcon#read 4, iclass 24, count 0 2006.285.10:28:51.22#ibcon#about to read 5, iclass 24, count 0 2006.285.10:28:51.22#ibcon#read 5, iclass 24, count 0 2006.285.10:28:51.22#ibcon#about to read 6, iclass 24, count 0 2006.285.10:28:51.22#ibcon#read 6, iclass 24, count 0 2006.285.10:28:51.22#ibcon#end of sib2, iclass 24, count 0 2006.285.10:28:51.22#ibcon#*after write, iclass 24, count 0 2006.285.10:28:51.22#ibcon#*before return 0, iclass 24, count 0 2006.285.10:28:51.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:28:51.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:28:51.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:28:51.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:28:51.22$vck44/vblo=6,719.99 2006.285.10:28:51.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.10:28:51.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.10:28:51.22#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:51.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:28:51.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:28:51.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:28:51.22#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:28:51.22#ibcon#first serial, iclass 26, count 0 2006.285.10:28:51.22#ibcon#enter sib2, iclass 26, count 0 2006.285.10:28:51.22#ibcon#flushed, iclass 26, count 0 2006.285.10:28:51.22#ibcon#about to write, iclass 26, count 0 2006.285.10:28:51.22#ibcon#wrote, iclass 26, count 0 2006.285.10:28:51.22#ibcon#about to read 3, iclass 26, count 0 2006.285.10:28:51.24#ibcon#read 3, iclass 26, count 0 2006.285.10:28:51.24#ibcon#about to read 4, iclass 26, count 0 2006.285.10:28:51.24#ibcon#read 4, iclass 26, count 0 2006.285.10:28:51.24#ibcon#about to read 5, iclass 26, count 0 2006.285.10:28:51.24#ibcon#read 5, iclass 26, count 0 2006.285.10:28:51.24#ibcon#about to read 6, iclass 26, count 0 2006.285.10:28:51.24#ibcon#read 6, iclass 26, count 0 2006.285.10:28:51.24#ibcon#end of sib2, iclass 26, count 0 2006.285.10:28:51.24#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:28:51.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:28:51.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:28:51.24#ibcon#*before write, iclass 26, count 0 2006.285.10:28:51.24#ibcon#enter sib2, iclass 26, count 0 2006.285.10:28:51.24#ibcon#flushed, iclass 26, count 0 2006.285.10:28:51.24#ibcon#about to write, iclass 26, count 0 2006.285.10:28:51.24#ibcon#wrote, iclass 26, count 0 2006.285.10:28:51.24#ibcon#about to read 3, iclass 26, count 0 2006.285.10:28:51.28#ibcon#read 3, iclass 26, count 0 2006.285.10:28:51.28#ibcon#about to read 4, iclass 26, count 0 2006.285.10:28:51.28#ibcon#read 4, iclass 26, count 0 2006.285.10:28:51.28#ibcon#about to read 5, iclass 26, count 0 2006.285.10:28:51.28#ibcon#read 5, iclass 26, count 0 2006.285.10:28:51.28#ibcon#about to read 6, iclass 26, count 0 2006.285.10:28:51.28#ibcon#read 6, iclass 26, count 0 2006.285.10:28:51.28#ibcon#end of sib2, iclass 26, count 0 2006.285.10:28:51.28#ibcon#*after write, iclass 26, count 0 2006.285.10:28:51.28#ibcon#*before return 0, iclass 26, count 0 2006.285.10:28:51.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:28:51.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:28:51.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:28:51.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:28:51.28$vck44/vb=6,3 2006.285.10:28:51.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.10:28:51.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.10:28:51.28#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:51.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:28:51.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:28:51.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:28:51.34#ibcon#enter wrdev, iclass 28, count 2 2006.285.10:28:51.34#ibcon#first serial, iclass 28, count 2 2006.285.10:28:51.34#ibcon#enter sib2, iclass 28, count 2 2006.285.10:28:51.34#ibcon#flushed, iclass 28, count 2 2006.285.10:28:51.34#ibcon#about to write, iclass 28, count 2 2006.285.10:28:51.34#ibcon#wrote, iclass 28, count 2 2006.285.10:28:51.34#ibcon#about to read 3, iclass 28, count 2 2006.285.10:28:51.36#ibcon#read 3, iclass 28, count 2 2006.285.10:28:51.36#ibcon#about to read 4, iclass 28, count 2 2006.285.10:28:51.36#ibcon#read 4, iclass 28, count 2 2006.285.10:28:51.36#ibcon#about to read 5, iclass 28, count 2 2006.285.10:28:51.36#ibcon#read 5, iclass 28, count 2 2006.285.10:28:51.36#ibcon#about to read 6, iclass 28, count 2 2006.285.10:28:51.36#ibcon#read 6, iclass 28, count 2 2006.285.10:28:51.36#ibcon#end of sib2, iclass 28, count 2 2006.285.10:28:51.36#ibcon#*mode == 0, iclass 28, count 2 2006.285.10:28:51.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.10:28:51.36#ibcon#[27=AT06-03\r\n] 2006.285.10:28:51.36#ibcon#*before write, iclass 28, count 2 2006.285.10:28:51.36#ibcon#enter sib2, iclass 28, count 2 2006.285.10:28:51.36#ibcon#flushed, iclass 28, count 2 2006.285.10:28:51.36#ibcon#about to write, iclass 28, count 2 2006.285.10:28:51.36#ibcon#wrote, iclass 28, count 2 2006.285.10:28:51.36#ibcon#about to read 3, iclass 28, count 2 2006.285.10:28:51.39#ibcon#read 3, iclass 28, count 2 2006.285.10:28:51.39#ibcon#about to read 4, iclass 28, count 2 2006.285.10:28:51.39#ibcon#read 4, iclass 28, count 2 2006.285.10:28:51.39#ibcon#about to read 5, iclass 28, count 2 2006.285.10:28:51.39#ibcon#read 5, iclass 28, count 2 2006.285.10:28:51.39#ibcon#about to read 6, iclass 28, count 2 2006.285.10:28:51.39#ibcon#read 6, iclass 28, count 2 2006.285.10:28:51.39#ibcon#end of sib2, iclass 28, count 2 2006.285.10:28:51.39#ibcon#*after write, iclass 28, count 2 2006.285.10:28:51.39#ibcon#*before return 0, iclass 28, count 2 2006.285.10:28:51.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:28:51.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:28:51.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.10:28:51.39#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:51.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:28:51.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:28:51.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:28:51.51#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:28:51.51#ibcon#first serial, iclass 28, count 0 2006.285.10:28:51.51#ibcon#enter sib2, iclass 28, count 0 2006.285.10:28:51.51#ibcon#flushed, iclass 28, count 0 2006.285.10:28:51.51#ibcon#about to write, iclass 28, count 0 2006.285.10:28:51.51#ibcon#wrote, iclass 28, count 0 2006.285.10:28:51.51#ibcon#about to read 3, iclass 28, count 0 2006.285.10:28:51.53#ibcon#read 3, iclass 28, count 0 2006.285.10:28:51.53#ibcon#about to read 4, iclass 28, count 0 2006.285.10:28:51.53#ibcon#read 4, iclass 28, count 0 2006.285.10:28:51.53#ibcon#about to read 5, iclass 28, count 0 2006.285.10:28:51.53#ibcon#read 5, iclass 28, count 0 2006.285.10:28:51.53#ibcon#about to read 6, iclass 28, count 0 2006.285.10:28:51.53#ibcon#read 6, iclass 28, count 0 2006.285.10:28:51.53#ibcon#end of sib2, iclass 28, count 0 2006.285.10:28:51.53#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:28:51.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:28:51.53#ibcon#[27=USB\r\n] 2006.285.10:28:51.53#ibcon#*before write, iclass 28, count 0 2006.285.10:28:51.53#ibcon#enter sib2, iclass 28, count 0 2006.285.10:28:51.53#ibcon#flushed, iclass 28, count 0 2006.285.10:28:51.53#ibcon#about to write, iclass 28, count 0 2006.285.10:28:51.53#ibcon#wrote, iclass 28, count 0 2006.285.10:28:51.53#ibcon#about to read 3, iclass 28, count 0 2006.285.10:28:51.56#ibcon#read 3, iclass 28, count 0 2006.285.10:28:51.56#ibcon#about to read 4, iclass 28, count 0 2006.285.10:28:51.56#ibcon#read 4, iclass 28, count 0 2006.285.10:28:51.56#ibcon#about to read 5, iclass 28, count 0 2006.285.10:28:51.56#ibcon#read 5, iclass 28, count 0 2006.285.10:28:51.56#ibcon#about to read 6, iclass 28, count 0 2006.285.10:28:51.56#ibcon#read 6, iclass 28, count 0 2006.285.10:28:51.56#ibcon#end of sib2, iclass 28, count 0 2006.285.10:28:51.56#ibcon#*after write, iclass 28, count 0 2006.285.10:28:51.56#ibcon#*before return 0, iclass 28, count 0 2006.285.10:28:51.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:28:51.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:28:51.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:28:51.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:28:51.56$vck44/vblo=7,734.99 2006.285.10:28:51.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.10:28:51.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.10:28:51.56#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:51.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:28:51.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:28:51.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:28:51.56#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:28:51.56#ibcon#first serial, iclass 30, count 0 2006.285.10:28:51.56#ibcon#enter sib2, iclass 30, count 0 2006.285.10:28:51.56#ibcon#flushed, iclass 30, count 0 2006.285.10:28:51.56#ibcon#about to write, iclass 30, count 0 2006.285.10:28:51.56#ibcon#wrote, iclass 30, count 0 2006.285.10:28:51.56#ibcon#about to read 3, iclass 30, count 0 2006.285.10:28:51.58#ibcon#read 3, iclass 30, count 0 2006.285.10:28:51.58#ibcon#about to read 4, iclass 30, count 0 2006.285.10:28:51.58#ibcon#read 4, iclass 30, count 0 2006.285.10:28:51.58#ibcon#about to read 5, iclass 30, count 0 2006.285.10:28:51.58#ibcon#read 5, iclass 30, count 0 2006.285.10:28:51.58#ibcon#about to read 6, iclass 30, count 0 2006.285.10:28:51.58#ibcon#read 6, iclass 30, count 0 2006.285.10:28:51.58#ibcon#end of sib2, iclass 30, count 0 2006.285.10:28:51.58#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:28:51.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:28:51.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:28:51.58#ibcon#*before write, iclass 30, count 0 2006.285.10:28:51.58#ibcon#enter sib2, iclass 30, count 0 2006.285.10:28:51.58#ibcon#flushed, iclass 30, count 0 2006.285.10:28:51.58#ibcon#about to write, iclass 30, count 0 2006.285.10:28:51.58#ibcon#wrote, iclass 30, count 0 2006.285.10:28:51.58#ibcon#about to read 3, iclass 30, count 0 2006.285.10:28:51.62#ibcon#read 3, iclass 30, count 0 2006.285.10:28:51.62#ibcon#about to read 4, iclass 30, count 0 2006.285.10:28:51.62#ibcon#read 4, iclass 30, count 0 2006.285.10:28:51.62#ibcon#about to read 5, iclass 30, count 0 2006.285.10:28:51.62#ibcon#read 5, iclass 30, count 0 2006.285.10:28:51.62#ibcon#about to read 6, iclass 30, count 0 2006.285.10:28:51.62#ibcon#read 6, iclass 30, count 0 2006.285.10:28:51.62#ibcon#end of sib2, iclass 30, count 0 2006.285.10:28:51.62#ibcon#*after write, iclass 30, count 0 2006.285.10:28:51.62#ibcon#*before return 0, iclass 30, count 0 2006.285.10:28:51.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:28:51.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:28:51.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:28:51.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:28:51.62$vck44/vb=7,4 2006.285.10:28:51.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.10:28:51.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.10:28:51.62#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:51.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:28:51.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:28:51.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:28:51.68#ibcon#enter wrdev, iclass 32, count 2 2006.285.10:28:51.68#ibcon#first serial, iclass 32, count 2 2006.285.10:28:51.68#ibcon#enter sib2, iclass 32, count 2 2006.285.10:28:51.68#ibcon#flushed, iclass 32, count 2 2006.285.10:28:51.68#ibcon#about to write, iclass 32, count 2 2006.285.10:28:51.68#ibcon#wrote, iclass 32, count 2 2006.285.10:28:51.68#ibcon#about to read 3, iclass 32, count 2 2006.285.10:28:51.70#ibcon#read 3, iclass 32, count 2 2006.285.10:28:51.70#ibcon#about to read 4, iclass 32, count 2 2006.285.10:28:51.70#ibcon#read 4, iclass 32, count 2 2006.285.10:28:51.70#ibcon#about to read 5, iclass 32, count 2 2006.285.10:28:51.70#ibcon#read 5, iclass 32, count 2 2006.285.10:28:51.70#ibcon#about to read 6, iclass 32, count 2 2006.285.10:28:51.70#ibcon#read 6, iclass 32, count 2 2006.285.10:28:51.70#ibcon#end of sib2, iclass 32, count 2 2006.285.10:28:51.70#ibcon#*mode == 0, iclass 32, count 2 2006.285.10:28:51.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.10:28:51.70#ibcon#[27=AT07-04\r\n] 2006.285.10:28:51.70#ibcon#*before write, iclass 32, count 2 2006.285.10:28:51.70#ibcon#enter sib2, iclass 32, count 2 2006.285.10:28:51.70#ibcon#flushed, iclass 32, count 2 2006.285.10:28:51.70#ibcon#about to write, iclass 32, count 2 2006.285.10:28:51.70#ibcon#wrote, iclass 32, count 2 2006.285.10:28:51.70#ibcon#about to read 3, iclass 32, count 2 2006.285.10:28:51.73#ibcon#read 3, iclass 32, count 2 2006.285.10:28:51.73#ibcon#about to read 4, iclass 32, count 2 2006.285.10:28:51.73#ibcon#read 4, iclass 32, count 2 2006.285.10:28:51.73#ibcon#about to read 5, iclass 32, count 2 2006.285.10:28:51.73#ibcon#read 5, iclass 32, count 2 2006.285.10:28:51.73#ibcon#about to read 6, iclass 32, count 2 2006.285.10:28:51.73#ibcon#read 6, iclass 32, count 2 2006.285.10:28:51.73#ibcon#end of sib2, iclass 32, count 2 2006.285.10:28:51.73#ibcon#*after write, iclass 32, count 2 2006.285.10:28:51.73#ibcon#*before return 0, iclass 32, count 2 2006.285.10:28:51.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:28:51.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:28:51.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.10:28:51.73#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:51.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:28:51.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:28:51.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:28:51.85#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:28:51.85#ibcon#first serial, iclass 32, count 0 2006.285.10:28:51.85#ibcon#enter sib2, iclass 32, count 0 2006.285.10:28:51.85#ibcon#flushed, iclass 32, count 0 2006.285.10:28:51.85#ibcon#about to write, iclass 32, count 0 2006.285.10:28:51.85#ibcon#wrote, iclass 32, count 0 2006.285.10:28:51.85#ibcon#about to read 3, iclass 32, count 0 2006.285.10:28:51.87#ibcon#read 3, iclass 32, count 0 2006.285.10:28:51.87#ibcon#about to read 4, iclass 32, count 0 2006.285.10:28:51.87#ibcon#read 4, iclass 32, count 0 2006.285.10:28:51.87#ibcon#about to read 5, iclass 32, count 0 2006.285.10:28:51.87#ibcon#read 5, iclass 32, count 0 2006.285.10:28:51.87#ibcon#about to read 6, iclass 32, count 0 2006.285.10:28:51.87#ibcon#read 6, iclass 32, count 0 2006.285.10:28:51.87#ibcon#end of sib2, iclass 32, count 0 2006.285.10:28:51.87#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:28:51.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:28:51.87#ibcon#[27=USB\r\n] 2006.285.10:28:51.87#ibcon#*before write, iclass 32, count 0 2006.285.10:28:51.87#ibcon#enter sib2, iclass 32, count 0 2006.285.10:28:51.87#ibcon#flushed, iclass 32, count 0 2006.285.10:28:51.87#ibcon#about to write, iclass 32, count 0 2006.285.10:28:51.87#ibcon#wrote, iclass 32, count 0 2006.285.10:28:51.87#ibcon#about to read 3, iclass 32, count 0 2006.285.10:28:51.90#ibcon#read 3, iclass 32, count 0 2006.285.10:28:51.90#ibcon#about to read 4, iclass 32, count 0 2006.285.10:28:51.90#ibcon#read 4, iclass 32, count 0 2006.285.10:28:51.90#ibcon#about to read 5, iclass 32, count 0 2006.285.10:28:51.90#ibcon#read 5, iclass 32, count 0 2006.285.10:28:51.90#ibcon#about to read 6, iclass 32, count 0 2006.285.10:28:51.90#ibcon#read 6, iclass 32, count 0 2006.285.10:28:51.90#ibcon#end of sib2, iclass 32, count 0 2006.285.10:28:51.90#ibcon#*after write, iclass 32, count 0 2006.285.10:28:51.90#ibcon#*before return 0, iclass 32, count 0 2006.285.10:28:51.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:28:51.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:28:51.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:28:51.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:28:51.90$vck44/vblo=8,744.99 2006.285.10:28:51.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.10:28:51.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.10:28:51.90#ibcon#ireg 17 cls_cnt 0 2006.285.10:28:51.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:28:51.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:28:51.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:28:51.90#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:28:51.90#ibcon#first serial, iclass 34, count 0 2006.285.10:28:51.90#ibcon#enter sib2, iclass 34, count 0 2006.285.10:28:51.90#ibcon#flushed, iclass 34, count 0 2006.285.10:28:51.90#ibcon#about to write, iclass 34, count 0 2006.285.10:28:51.90#ibcon#wrote, iclass 34, count 0 2006.285.10:28:51.90#ibcon#about to read 3, iclass 34, count 0 2006.285.10:28:51.92#ibcon#read 3, iclass 34, count 0 2006.285.10:28:51.92#ibcon#about to read 4, iclass 34, count 0 2006.285.10:28:51.92#ibcon#read 4, iclass 34, count 0 2006.285.10:28:51.92#ibcon#about to read 5, iclass 34, count 0 2006.285.10:28:51.92#ibcon#read 5, iclass 34, count 0 2006.285.10:28:51.92#ibcon#about to read 6, iclass 34, count 0 2006.285.10:28:51.92#ibcon#read 6, iclass 34, count 0 2006.285.10:28:51.92#ibcon#end of sib2, iclass 34, count 0 2006.285.10:28:51.92#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:28:51.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:28:51.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:28:51.92#ibcon#*before write, iclass 34, count 0 2006.285.10:28:51.92#ibcon#enter sib2, iclass 34, count 0 2006.285.10:28:51.92#ibcon#flushed, iclass 34, count 0 2006.285.10:28:51.92#ibcon#about to write, iclass 34, count 0 2006.285.10:28:51.92#ibcon#wrote, iclass 34, count 0 2006.285.10:28:51.92#ibcon#about to read 3, iclass 34, count 0 2006.285.10:28:51.96#ibcon#read 3, iclass 34, count 0 2006.285.10:28:51.96#ibcon#about to read 4, iclass 34, count 0 2006.285.10:28:51.96#ibcon#read 4, iclass 34, count 0 2006.285.10:28:51.96#ibcon#about to read 5, iclass 34, count 0 2006.285.10:28:51.96#ibcon#read 5, iclass 34, count 0 2006.285.10:28:51.96#ibcon#about to read 6, iclass 34, count 0 2006.285.10:28:51.96#ibcon#read 6, iclass 34, count 0 2006.285.10:28:51.96#ibcon#end of sib2, iclass 34, count 0 2006.285.10:28:51.96#ibcon#*after write, iclass 34, count 0 2006.285.10:28:51.96#ibcon#*before return 0, iclass 34, count 0 2006.285.10:28:51.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:28:51.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:28:51.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:28:51.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:28:51.96$vck44/vb=8,4 2006.285.10:28:51.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.10:28:51.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.10:28:51.96#ibcon#ireg 11 cls_cnt 2 2006.285.10:28:51.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:28:52.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:28:52.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:28:52.02#ibcon#enter wrdev, iclass 36, count 2 2006.285.10:28:52.02#ibcon#first serial, iclass 36, count 2 2006.285.10:28:52.02#ibcon#enter sib2, iclass 36, count 2 2006.285.10:28:52.02#ibcon#flushed, iclass 36, count 2 2006.285.10:28:52.02#ibcon#about to write, iclass 36, count 2 2006.285.10:28:52.02#ibcon#wrote, iclass 36, count 2 2006.285.10:28:52.02#ibcon#about to read 3, iclass 36, count 2 2006.285.10:28:52.04#ibcon#read 3, iclass 36, count 2 2006.285.10:28:52.04#ibcon#about to read 4, iclass 36, count 2 2006.285.10:28:52.04#ibcon#read 4, iclass 36, count 2 2006.285.10:28:52.04#ibcon#about to read 5, iclass 36, count 2 2006.285.10:28:52.04#ibcon#read 5, iclass 36, count 2 2006.285.10:28:52.04#ibcon#about to read 6, iclass 36, count 2 2006.285.10:28:52.04#ibcon#read 6, iclass 36, count 2 2006.285.10:28:52.04#ibcon#end of sib2, iclass 36, count 2 2006.285.10:28:52.04#ibcon#*mode == 0, iclass 36, count 2 2006.285.10:28:52.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.10:28:52.04#ibcon#[27=AT08-04\r\n] 2006.285.10:28:52.04#ibcon#*before write, iclass 36, count 2 2006.285.10:28:52.04#ibcon#enter sib2, iclass 36, count 2 2006.285.10:28:52.04#ibcon#flushed, iclass 36, count 2 2006.285.10:28:52.04#ibcon#about to write, iclass 36, count 2 2006.285.10:28:52.04#ibcon#wrote, iclass 36, count 2 2006.285.10:28:52.04#ibcon#about to read 3, iclass 36, count 2 2006.285.10:28:52.07#ibcon#read 3, iclass 36, count 2 2006.285.10:28:52.07#ibcon#about to read 4, iclass 36, count 2 2006.285.10:28:52.07#ibcon#read 4, iclass 36, count 2 2006.285.10:28:52.07#ibcon#about to read 5, iclass 36, count 2 2006.285.10:28:52.07#ibcon#read 5, iclass 36, count 2 2006.285.10:28:52.07#ibcon#about to read 6, iclass 36, count 2 2006.285.10:28:52.07#ibcon#read 6, iclass 36, count 2 2006.285.10:28:52.07#ibcon#end of sib2, iclass 36, count 2 2006.285.10:28:52.07#ibcon#*after write, iclass 36, count 2 2006.285.10:28:52.07#ibcon#*before return 0, iclass 36, count 2 2006.285.10:28:52.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:28:52.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:28:52.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.10:28:52.07#ibcon#ireg 7 cls_cnt 0 2006.285.10:28:52.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:28:52.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:28:52.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:28:52.19#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:28:52.19#ibcon#first serial, iclass 36, count 0 2006.285.10:28:52.19#ibcon#enter sib2, iclass 36, count 0 2006.285.10:28:52.19#ibcon#flushed, iclass 36, count 0 2006.285.10:28:52.19#ibcon#about to write, iclass 36, count 0 2006.285.10:28:52.19#ibcon#wrote, iclass 36, count 0 2006.285.10:28:52.19#ibcon#about to read 3, iclass 36, count 0 2006.285.10:28:52.21#ibcon#read 3, iclass 36, count 0 2006.285.10:28:52.21#ibcon#about to read 4, iclass 36, count 0 2006.285.10:28:52.21#ibcon#read 4, iclass 36, count 0 2006.285.10:28:52.21#ibcon#about to read 5, iclass 36, count 0 2006.285.10:28:52.21#ibcon#read 5, iclass 36, count 0 2006.285.10:28:52.21#ibcon#about to read 6, iclass 36, count 0 2006.285.10:28:52.21#ibcon#read 6, iclass 36, count 0 2006.285.10:28:52.21#ibcon#end of sib2, iclass 36, count 0 2006.285.10:28:52.21#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:28:52.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:28:52.21#ibcon#[27=USB\r\n] 2006.285.10:28:52.21#ibcon#*before write, iclass 36, count 0 2006.285.10:28:52.21#ibcon#enter sib2, iclass 36, count 0 2006.285.10:28:52.21#ibcon#flushed, iclass 36, count 0 2006.285.10:28:52.21#ibcon#about to write, iclass 36, count 0 2006.285.10:28:52.21#ibcon#wrote, iclass 36, count 0 2006.285.10:28:52.21#ibcon#about to read 3, iclass 36, count 0 2006.285.10:28:52.24#ibcon#read 3, iclass 36, count 0 2006.285.10:28:52.24#ibcon#about to read 4, iclass 36, count 0 2006.285.10:28:52.24#ibcon#read 4, iclass 36, count 0 2006.285.10:28:52.24#ibcon#about to read 5, iclass 36, count 0 2006.285.10:28:52.24#ibcon#read 5, iclass 36, count 0 2006.285.10:28:52.24#ibcon#about to read 6, iclass 36, count 0 2006.285.10:28:52.24#ibcon#read 6, iclass 36, count 0 2006.285.10:28:52.24#ibcon#end of sib2, iclass 36, count 0 2006.285.10:28:52.24#ibcon#*after write, iclass 36, count 0 2006.285.10:28:52.24#ibcon#*before return 0, iclass 36, count 0 2006.285.10:28:52.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:28:52.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:28:52.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:28:52.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:28:52.24$vck44/vabw=wide 2006.285.10:28:52.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.10:28:52.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.10:28:52.24#ibcon#ireg 8 cls_cnt 0 2006.285.10:28:52.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:28:52.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:28:52.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:28:52.24#ibcon#enter wrdev, iclass 38, count 0 2006.285.10:28:52.24#ibcon#first serial, iclass 38, count 0 2006.285.10:28:52.24#ibcon#enter sib2, iclass 38, count 0 2006.285.10:28:52.24#ibcon#flushed, iclass 38, count 0 2006.285.10:28:52.24#ibcon#about to write, iclass 38, count 0 2006.285.10:28:52.24#ibcon#wrote, iclass 38, count 0 2006.285.10:28:52.24#ibcon#about to read 3, iclass 38, count 0 2006.285.10:28:52.26#ibcon#read 3, iclass 38, count 0 2006.285.10:28:52.26#ibcon#about to read 4, iclass 38, count 0 2006.285.10:28:52.26#ibcon#read 4, iclass 38, count 0 2006.285.10:28:52.26#ibcon#about to read 5, iclass 38, count 0 2006.285.10:28:52.26#ibcon#read 5, iclass 38, count 0 2006.285.10:28:52.26#ibcon#about to read 6, iclass 38, count 0 2006.285.10:28:52.26#ibcon#read 6, iclass 38, count 0 2006.285.10:28:52.26#ibcon#end of sib2, iclass 38, count 0 2006.285.10:28:52.26#ibcon#*mode == 0, iclass 38, count 0 2006.285.10:28:52.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.10:28:52.26#ibcon#[25=BW32\r\n] 2006.285.10:28:52.26#ibcon#*before write, iclass 38, count 0 2006.285.10:28:52.26#ibcon#enter sib2, iclass 38, count 0 2006.285.10:28:52.26#ibcon#flushed, iclass 38, count 0 2006.285.10:28:52.26#ibcon#about to write, iclass 38, count 0 2006.285.10:28:52.26#ibcon#wrote, iclass 38, count 0 2006.285.10:28:52.26#ibcon#about to read 3, iclass 38, count 0 2006.285.10:28:52.29#ibcon#read 3, iclass 38, count 0 2006.285.10:28:52.29#ibcon#about to read 4, iclass 38, count 0 2006.285.10:28:52.29#ibcon#read 4, iclass 38, count 0 2006.285.10:28:52.29#ibcon#about to read 5, iclass 38, count 0 2006.285.10:28:52.29#ibcon#read 5, iclass 38, count 0 2006.285.10:28:52.29#ibcon#about to read 6, iclass 38, count 0 2006.285.10:28:52.29#ibcon#read 6, iclass 38, count 0 2006.285.10:28:52.29#ibcon#end of sib2, iclass 38, count 0 2006.285.10:28:52.29#ibcon#*after write, iclass 38, count 0 2006.285.10:28:52.29#ibcon#*before return 0, iclass 38, count 0 2006.285.10:28:52.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:28:52.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:28:52.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.10:28:52.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.10:28:52.29$vck44/vbbw=wide 2006.285.10:28:52.29#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.10:28:52.29#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.10:28:52.29#ibcon#ireg 8 cls_cnt 0 2006.285.10:28:52.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:28:52.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:28:52.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:28:52.36#ibcon#enter wrdev, iclass 40, count 0 2006.285.10:28:52.36#ibcon#first serial, iclass 40, count 0 2006.285.10:28:52.36#ibcon#enter sib2, iclass 40, count 0 2006.285.10:28:52.36#ibcon#flushed, iclass 40, count 0 2006.285.10:28:52.36#ibcon#about to write, iclass 40, count 0 2006.285.10:28:52.36#ibcon#wrote, iclass 40, count 0 2006.285.10:28:52.36#ibcon#about to read 3, iclass 40, count 0 2006.285.10:28:52.38#ibcon#read 3, iclass 40, count 0 2006.285.10:28:52.38#ibcon#about to read 4, iclass 40, count 0 2006.285.10:28:52.38#ibcon#read 4, iclass 40, count 0 2006.285.10:28:52.38#ibcon#about to read 5, iclass 40, count 0 2006.285.10:28:52.38#ibcon#read 5, iclass 40, count 0 2006.285.10:28:52.38#ibcon#about to read 6, iclass 40, count 0 2006.285.10:28:52.38#ibcon#read 6, iclass 40, count 0 2006.285.10:28:52.38#ibcon#end of sib2, iclass 40, count 0 2006.285.10:28:52.38#ibcon#*mode == 0, iclass 40, count 0 2006.285.10:28:52.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.10:28:52.38#ibcon#[27=BW32\r\n] 2006.285.10:28:52.38#ibcon#*before write, iclass 40, count 0 2006.285.10:28:52.38#ibcon#enter sib2, iclass 40, count 0 2006.285.10:28:52.38#ibcon#flushed, iclass 40, count 0 2006.285.10:28:52.38#ibcon#about to write, iclass 40, count 0 2006.285.10:28:52.38#ibcon#wrote, iclass 40, count 0 2006.285.10:28:52.38#ibcon#about to read 3, iclass 40, count 0 2006.285.10:28:52.41#ibcon#read 3, iclass 40, count 0 2006.285.10:28:52.41#ibcon#about to read 4, iclass 40, count 0 2006.285.10:28:52.41#ibcon#read 4, iclass 40, count 0 2006.285.10:28:52.41#ibcon#about to read 5, iclass 40, count 0 2006.285.10:28:52.41#ibcon#read 5, iclass 40, count 0 2006.285.10:28:52.41#ibcon#about to read 6, iclass 40, count 0 2006.285.10:28:52.41#ibcon#read 6, iclass 40, count 0 2006.285.10:28:52.41#ibcon#end of sib2, iclass 40, count 0 2006.285.10:28:52.41#ibcon#*after write, iclass 40, count 0 2006.285.10:28:52.41#ibcon#*before return 0, iclass 40, count 0 2006.285.10:28:52.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:28:52.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:28:52.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.10:28:52.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.10:28:52.41$setupk4/ifdk4 2006.285.10:28:52.41$ifdk4/lo= 2006.285.10:28:52.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:28:52.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:28:52.41$ifdk4/patch= 2006.285.10:28:52.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:28:52.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:28:52.41$setupk4/!*+20s 2006.285.10:28:54.73#abcon#<5=/04 1.4 2.5 19.77 911015.0\r\n> 2006.285.10:28:54.75#abcon#{5=INTERFACE CLEAR} 2006.285.10:28:54.81#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:29:04.90#abcon#<5=/04 1.4 2.5 19.77 911015.0\r\n> 2006.285.10:29:04.92#abcon#{5=INTERFACE CLEAR} 2006.285.10:29:04.98#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:29:06.92$setupk4/"tpicd 2006.285.10:29:06.92$setupk4/echo=off 2006.285.10:29:06.92$setupk4/xlog=off 2006.285.10:29:06.92:!2006.285.10:30:21 2006.285.10:29:10.13#trakl#Source acquired 2006.285.10:29:11.13#flagr#flagr/antenna,acquired 2006.285.10:30:21.00:preob 2006.285.10:30:21.13/onsource/TRACKING 2006.285.10:30:21.13:!2006.285.10:30:31 2006.285.10:30:31.00:"tape 2006.285.10:30:31.00:"st=record 2006.285.10:30:31.00:data_valid=on 2006.285.10:30:31.00:midob 2006.285.10:30:32.13/onsource/TRACKING 2006.285.10:30:32.13/wx/19.76,1015.0,91 2006.285.10:30:32.31/cable/+6.4871E-03 2006.285.10:30:33.40/va/01,07,usb,yes,31,34 2006.285.10:30:33.40/va/02,06,usb,yes,31,32 2006.285.10:30:33.40/va/03,07,usb,yes,31,33 2006.285.10:30:33.40/va/04,06,usb,yes,32,34 2006.285.10:30:33.40/va/05,03,usb,yes,32,32 2006.285.10:30:33.40/va/06,04,usb,yes,29,28 2006.285.10:30:33.40/va/07,04,usb,yes,29,30 2006.285.10:30:33.40/va/08,03,usb,yes,30,36 2006.285.10:30:33.63/valo/01,524.99,yes,locked 2006.285.10:30:33.63/valo/02,534.99,yes,locked 2006.285.10:30:33.63/valo/03,564.99,yes,locked 2006.285.10:30:33.63/valo/04,624.99,yes,locked 2006.285.10:30:33.63/valo/05,734.99,yes,locked 2006.285.10:30:33.63/valo/06,814.99,yes,locked 2006.285.10:30:33.63/valo/07,864.99,yes,locked 2006.285.10:30:33.63/valo/08,884.99,yes,locked 2006.285.10:30:34.72/vb/01,04,usb,yes,30,28 2006.285.10:30:34.72/vb/02,05,usb,yes,28,28 2006.285.10:30:34.72/vb/03,04,usb,yes,29,32 2006.285.10:30:34.72/vb/04,05,usb,yes,29,28 2006.285.10:30:34.72/vb/05,04,usb,yes,26,28 2006.285.10:30:34.72/vb/06,03,usb,yes,37,33 2006.285.10:30:34.72/vb/07,04,usb,yes,30,30 2006.285.10:30:34.72/vb/08,04,usb,yes,27,31 2006.285.10:30:34.96/vblo/01,629.99,yes,locked 2006.285.10:30:34.96/vblo/02,634.99,yes,locked 2006.285.10:30:34.96/vblo/03,649.99,yes,locked 2006.285.10:30:34.96/vblo/04,679.99,yes,locked 2006.285.10:30:34.96/vblo/05,709.99,yes,locked 2006.285.10:30:34.96/vblo/06,719.99,yes,locked 2006.285.10:30:34.96/vblo/07,734.99,yes,locked 2006.285.10:30:34.96/vblo/08,744.99,yes,locked 2006.285.10:30:35.11/vabw/8 2006.285.10:30:35.26/vbbw/8 2006.285.10:30:35.35/xfe/off,on,12.2 2006.285.10:30:35.72/ifatt/23,28,28,28 2006.285.10:30:36.08/fmout-gps/S +2.65E-07 2006.285.10:30:36.10:!2006.285.10:33:11 2006.285.10:33:11.00:data_valid=off 2006.285.10:33:11.00:"et 2006.285.10:33:11.00:!+3s 2006.285.10:33:14.01:"tape 2006.285.10:33:14.01:postob 2006.285.10:33:14.11/cable/+6.4848E-03 2006.285.10:33:14.11/wx/19.75,1015.0,91 2006.285.10:33:15.08/fmout-gps/S +2.68E-07 2006.285.10:33:15.08:scan_name=285-1038,jd0610,160 2006.285.10:33:15.08:source=3c446,222547.26,-045701.4,2000.0,cw 2006.285.10:33:16.14#flagr#flagr/antenna,new-source 2006.285.10:33:16.14:checkk5 2006.285.10:33:16.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:33:17.84/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:33:18.24/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:33:18.69/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:33:19.50/chk_obsdata//k5ts1/T2851030??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.10:33:19.88/chk_obsdata//k5ts2/T2851030??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.10:33:20.29/chk_obsdata//k5ts3/T2851030??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.10:33:20.76/chk_obsdata//k5ts4/T2851030??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.10:33:21.50/k5log//k5ts1_log_newline 2006.285.10:33:22.25/k5log//k5ts2_log_newline 2006.285.10:33:23.47/k5log//k5ts3_log_newline 2006.285.10:33:24.27/k5log//k5ts4_log_newline 2006.285.10:33:24.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:33:24.29:setupk4=1 2006.285.10:33:24.29$setupk4/echo=on 2006.285.10:33:24.29$setupk4/pcalon 2006.285.10:33:24.29$pcalon/"no phase cal control is implemented here 2006.285.10:33:24.29$setupk4/"tpicd=stop 2006.285.10:33:24.29$setupk4/"rec=synch_on 2006.285.10:33:24.29$setupk4/"rec_mode=128 2006.285.10:33:24.29$setupk4/!* 2006.285.10:33:24.29$setupk4/recpk4 2006.285.10:33:24.30$recpk4/recpatch= 2006.285.10:33:24.30$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:33:24.30$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:33:24.30$setupk4/vck44 2006.285.10:33:24.30$vck44/valo=1,524.99 2006.285.10:33:24.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.10:33:24.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.10:33:24.30#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:24.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:33:24.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:33:24.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:33:24.30#ibcon#enter wrdev, iclass 40, count 0 2006.285.10:33:24.30#ibcon#first serial, iclass 40, count 0 2006.285.10:33:24.30#ibcon#enter sib2, iclass 40, count 0 2006.285.10:33:24.30#ibcon#flushed, iclass 40, count 0 2006.285.10:33:24.30#ibcon#about to write, iclass 40, count 0 2006.285.10:33:24.30#ibcon#wrote, iclass 40, count 0 2006.285.10:33:24.30#ibcon#about to read 3, iclass 40, count 0 2006.285.10:33:24.32#ibcon#read 3, iclass 40, count 0 2006.285.10:33:24.32#ibcon#about to read 4, iclass 40, count 0 2006.285.10:33:24.32#ibcon#read 4, iclass 40, count 0 2006.285.10:33:24.32#ibcon#about to read 5, iclass 40, count 0 2006.285.10:33:24.32#ibcon#read 5, iclass 40, count 0 2006.285.10:33:24.32#ibcon#about to read 6, iclass 40, count 0 2006.285.10:33:24.32#ibcon#read 6, iclass 40, count 0 2006.285.10:33:24.32#ibcon#end of sib2, iclass 40, count 0 2006.285.10:33:24.32#ibcon#*mode == 0, iclass 40, count 0 2006.285.10:33:24.32#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.10:33:24.32#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:33:24.32#ibcon#*before write, iclass 40, count 0 2006.285.10:33:24.32#ibcon#enter sib2, iclass 40, count 0 2006.285.10:33:24.32#ibcon#flushed, iclass 40, count 0 2006.285.10:33:24.32#ibcon#about to write, iclass 40, count 0 2006.285.10:33:24.32#ibcon#wrote, iclass 40, count 0 2006.285.10:33:24.32#ibcon#about to read 3, iclass 40, count 0 2006.285.10:33:24.37#ibcon#read 3, iclass 40, count 0 2006.285.10:33:24.37#ibcon#about to read 4, iclass 40, count 0 2006.285.10:33:24.37#ibcon#read 4, iclass 40, count 0 2006.285.10:33:24.37#ibcon#about to read 5, iclass 40, count 0 2006.285.10:33:24.37#ibcon#read 5, iclass 40, count 0 2006.285.10:33:24.37#ibcon#about to read 6, iclass 40, count 0 2006.285.10:33:24.37#ibcon#read 6, iclass 40, count 0 2006.285.10:33:24.37#ibcon#end of sib2, iclass 40, count 0 2006.285.10:33:24.37#ibcon#*after write, iclass 40, count 0 2006.285.10:33:24.37#ibcon#*before return 0, iclass 40, count 0 2006.285.10:33:24.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:33:24.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:33:24.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.10:33:24.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.10:33:24.37$vck44/va=1,7 2006.285.10:33:24.37#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.10:33:24.37#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.10:33:24.37#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:24.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:33:24.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:33:24.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:33:24.37#ibcon#enter wrdev, iclass 4, count 2 2006.285.10:33:24.37#ibcon#first serial, iclass 4, count 2 2006.285.10:33:24.37#ibcon#enter sib2, iclass 4, count 2 2006.285.10:33:24.37#ibcon#flushed, iclass 4, count 2 2006.285.10:33:24.37#ibcon#about to write, iclass 4, count 2 2006.285.10:33:24.37#ibcon#wrote, iclass 4, count 2 2006.285.10:33:24.37#ibcon#about to read 3, iclass 4, count 2 2006.285.10:33:24.39#ibcon#read 3, iclass 4, count 2 2006.285.10:33:24.39#ibcon#about to read 4, iclass 4, count 2 2006.285.10:33:24.39#ibcon#read 4, iclass 4, count 2 2006.285.10:33:24.39#ibcon#about to read 5, iclass 4, count 2 2006.285.10:33:24.39#ibcon#read 5, iclass 4, count 2 2006.285.10:33:24.39#ibcon#about to read 6, iclass 4, count 2 2006.285.10:33:24.39#ibcon#read 6, iclass 4, count 2 2006.285.10:33:24.39#ibcon#end of sib2, iclass 4, count 2 2006.285.10:33:24.39#ibcon#*mode == 0, iclass 4, count 2 2006.285.10:33:24.39#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.10:33:24.39#ibcon#[25=AT01-07\r\n] 2006.285.10:33:24.39#ibcon#*before write, iclass 4, count 2 2006.285.10:33:24.39#ibcon#enter sib2, iclass 4, count 2 2006.285.10:33:24.39#ibcon#flushed, iclass 4, count 2 2006.285.10:33:24.39#ibcon#about to write, iclass 4, count 2 2006.285.10:33:24.39#ibcon#wrote, iclass 4, count 2 2006.285.10:33:24.39#ibcon#about to read 3, iclass 4, count 2 2006.285.10:33:24.42#ibcon#read 3, iclass 4, count 2 2006.285.10:33:24.42#ibcon#about to read 4, iclass 4, count 2 2006.285.10:33:24.42#ibcon#read 4, iclass 4, count 2 2006.285.10:33:24.42#ibcon#about to read 5, iclass 4, count 2 2006.285.10:33:24.42#ibcon#read 5, iclass 4, count 2 2006.285.10:33:24.42#ibcon#about to read 6, iclass 4, count 2 2006.285.10:33:24.42#ibcon#read 6, iclass 4, count 2 2006.285.10:33:24.42#ibcon#end of sib2, iclass 4, count 2 2006.285.10:33:24.42#ibcon#*after write, iclass 4, count 2 2006.285.10:33:24.42#ibcon#*before return 0, iclass 4, count 2 2006.285.10:33:24.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:33:24.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:33:24.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.10:33:24.42#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:24.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:33:24.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:33:24.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:33:24.54#ibcon#enter wrdev, iclass 4, count 0 2006.285.10:33:24.54#ibcon#first serial, iclass 4, count 0 2006.285.10:33:24.54#ibcon#enter sib2, iclass 4, count 0 2006.285.10:33:24.54#ibcon#flushed, iclass 4, count 0 2006.285.10:33:24.54#ibcon#about to write, iclass 4, count 0 2006.285.10:33:24.54#ibcon#wrote, iclass 4, count 0 2006.285.10:33:24.54#ibcon#about to read 3, iclass 4, count 0 2006.285.10:33:24.56#ibcon#read 3, iclass 4, count 0 2006.285.10:33:24.56#ibcon#about to read 4, iclass 4, count 0 2006.285.10:33:24.56#ibcon#read 4, iclass 4, count 0 2006.285.10:33:24.56#ibcon#about to read 5, iclass 4, count 0 2006.285.10:33:24.56#ibcon#read 5, iclass 4, count 0 2006.285.10:33:24.56#ibcon#about to read 6, iclass 4, count 0 2006.285.10:33:24.56#ibcon#read 6, iclass 4, count 0 2006.285.10:33:24.56#ibcon#end of sib2, iclass 4, count 0 2006.285.10:33:24.56#ibcon#*mode == 0, iclass 4, count 0 2006.285.10:33:24.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.10:33:24.56#ibcon#[25=USB\r\n] 2006.285.10:33:24.56#ibcon#*before write, iclass 4, count 0 2006.285.10:33:24.56#ibcon#enter sib2, iclass 4, count 0 2006.285.10:33:24.56#ibcon#flushed, iclass 4, count 0 2006.285.10:33:24.56#ibcon#about to write, iclass 4, count 0 2006.285.10:33:24.56#ibcon#wrote, iclass 4, count 0 2006.285.10:33:24.56#ibcon#about to read 3, iclass 4, count 0 2006.285.10:33:24.59#ibcon#read 3, iclass 4, count 0 2006.285.10:33:24.59#ibcon#about to read 4, iclass 4, count 0 2006.285.10:33:24.59#ibcon#read 4, iclass 4, count 0 2006.285.10:33:24.59#ibcon#about to read 5, iclass 4, count 0 2006.285.10:33:24.59#ibcon#read 5, iclass 4, count 0 2006.285.10:33:24.59#ibcon#about to read 6, iclass 4, count 0 2006.285.10:33:24.59#ibcon#read 6, iclass 4, count 0 2006.285.10:33:24.59#ibcon#end of sib2, iclass 4, count 0 2006.285.10:33:24.59#ibcon#*after write, iclass 4, count 0 2006.285.10:33:24.59#ibcon#*before return 0, iclass 4, count 0 2006.285.10:33:24.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:33:24.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:33:24.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.10:33:24.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.10:33:24.59$vck44/valo=2,534.99 2006.285.10:33:24.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.10:33:24.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.10:33:24.59#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:24.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:33:24.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:33:24.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:33:24.59#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:33:24.59#ibcon#first serial, iclass 6, count 0 2006.285.10:33:24.59#ibcon#enter sib2, iclass 6, count 0 2006.285.10:33:24.59#ibcon#flushed, iclass 6, count 0 2006.285.10:33:24.59#ibcon#about to write, iclass 6, count 0 2006.285.10:33:24.59#ibcon#wrote, iclass 6, count 0 2006.285.10:33:24.59#ibcon#about to read 3, iclass 6, count 0 2006.285.10:33:24.61#ibcon#read 3, iclass 6, count 0 2006.285.10:33:24.61#ibcon#about to read 4, iclass 6, count 0 2006.285.10:33:24.61#ibcon#read 4, iclass 6, count 0 2006.285.10:33:24.61#ibcon#about to read 5, iclass 6, count 0 2006.285.10:33:24.61#ibcon#read 5, iclass 6, count 0 2006.285.10:33:24.61#ibcon#about to read 6, iclass 6, count 0 2006.285.10:33:24.61#ibcon#read 6, iclass 6, count 0 2006.285.10:33:24.61#ibcon#end of sib2, iclass 6, count 0 2006.285.10:33:24.61#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:33:24.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:33:24.61#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:33:24.61#ibcon#*before write, iclass 6, count 0 2006.285.10:33:24.61#ibcon#enter sib2, iclass 6, count 0 2006.285.10:33:24.61#ibcon#flushed, iclass 6, count 0 2006.285.10:33:24.61#ibcon#about to write, iclass 6, count 0 2006.285.10:33:24.61#ibcon#wrote, iclass 6, count 0 2006.285.10:33:24.61#ibcon#about to read 3, iclass 6, count 0 2006.285.10:33:24.65#ibcon#read 3, iclass 6, count 0 2006.285.10:33:24.65#ibcon#about to read 4, iclass 6, count 0 2006.285.10:33:24.65#ibcon#read 4, iclass 6, count 0 2006.285.10:33:24.65#ibcon#about to read 5, iclass 6, count 0 2006.285.10:33:24.65#ibcon#read 5, iclass 6, count 0 2006.285.10:33:24.65#ibcon#about to read 6, iclass 6, count 0 2006.285.10:33:24.65#ibcon#read 6, iclass 6, count 0 2006.285.10:33:24.65#ibcon#end of sib2, iclass 6, count 0 2006.285.10:33:24.65#ibcon#*after write, iclass 6, count 0 2006.285.10:33:24.65#ibcon#*before return 0, iclass 6, count 0 2006.285.10:33:24.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:33:24.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:33:24.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:33:24.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:33:24.65$vck44/va=2,6 2006.285.10:33:24.65#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.10:33:24.65#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.10:33:24.65#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:24.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:33:24.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:33:24.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:33:24.71#ibcon#enter wrdev, iclass 10, count 2 2006.285.10:33:24.71#ibcon#first serial, iclass 10, count 2 2006.285.10:33:24.71#ibcon#enter sib2, iclass 10, count 2 2006.285.10:33:24.71#ibcon#flushed, iclass 10, count 2 2006.285.10:33:24.71#ibcon#about to write, iclass 10, count 2 2006.285.10:33:24.71#ibcon#wrote, iclass 10, count 2 2006.285.10:33:24.71#ibcon#about to read 3, iclass 10, count 2 2006.285.10:33:24.73#ibcon#read 3, iclass 10, count 2 2006.285.10:33:24.73#ibcon#about to read 4, iclass 10, count 2 2006.285.10:33:24.73#ibcon#read 4, iclass 10, count 2 2006.285.10:33:24.73#ibcon#about to read 5, iclass 10, count 2 2006.285.10:33:24.73#ibcon#read 5, iclass 10, count 2 2006.285.10:33:24.73#ibcon#about to read 6, iclass 10, count 2 2006.285.10:33:24.73#ibcon#read 6, iclass 10, count 2 2006.285.10:33:24.73#ibcon#end of sib2, iclass 10, count 2 2006.285.10:33:24.73#ibcon#*mode == 0, iclass 10, count 2 2006.285.10:33:24.73#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.10:33:24.73#ibcon#[25=AT02-06\r\n] 2006.285.10:33:24.73#ibcon#*before write, iclass 10, count 2 2006.285.10:33:24.73#ibcon#enter sib2, iclass 10, count 2 2006.285.10:33:24.73#ibcon#flushed, iclass 10, count 2 2006.285.10:33:24.73#ibcon#about to write, iclass 10, count 2 2006.285.10:33:24.73#ibcon#wrote, iclass 10, count 2 2006.285.10:33:24.73#ibcon#about to read 3, iclass 10, count 2 2006.285.10:33:24.76#ibcon#read 3, iclass 10, count 2 2006.285.10:33:24.76#ibcon#about to read 4, iclass 10, count 2 2006.285.10:33:24.76#ibcon#read 4, iclass 10, count 2 2006.285.10:33:24.76#ibcon#about to read 5, iclass 10, count 2 2006.285.10:33:24.76#ibcon#read 5, iclass 10, count 2 2006.285.10:33:24.76#ibcon#about to read 6, iclass 10, count 2 2006.285.10:33:24.76#ibcon#read 6, iclass 10, count 2 2006.285.10:33:24.76#ibcon#end of sib2, iclass 10, count 2 2006.285.10:33:24.76#ibcon#*after write, iclass 10, count 2 2006.285.10:33:24.76#ibcon#*before return 0, iclass 10, count 2 2006.285.10:33:24.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:33:24.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:33:24.76#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.10:33:24.76#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:24.76#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:33:24.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:33:24.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:33:24.88#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:33:24.88#ibcon#first serial, iclass 10, count 0 2006.285.10:33:24.88#ibcon#enter sib2, iclass 10, count 0 2006.285.10:33:24.88#ibcon#flushed, iclass 10, count 0 2006.285.10:33:24.88#ibcon#about to write, iclass 10, count 0 2006.285.10:33:24.88#ibcon#wrote, iclass 10, count 0 2006.285.10:33:24.88#ibcon#about to read 3, iclass 10, count 0 2006.285.10:33:24.90#ibcon#read 3, iclass 10, count 0 2006.285.10:33:24.90#ibcon#about to read 4, iclass 10, count 0 2006.285.10:33:24.90#ibcon#read 4, iclass 10, count 0 2006.285.10:33:24.90#ibcon#about to read 5, iclass 10, count 0 2006.285.10:33:24.90#ibcon#read 5, iclass 10, count 0 2006.285.10:33:24.90#ibcon#about to read 6, iclass 10, count 0 2006.285.10:33:24.90#ibcon#read 6, iclass 10, count 0 2006.285.10:33:24.90#ibcon#end of sib2, iclass 10, count 0 2006.285.10:33:24.90#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:33:24.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:33:24.90#ibcon#[25=USB\r\n] 2006.285.10:33:24.90#ibcon#*before write, iclass 10, count 0 2006.285.10:33:24.90#ibcon#enter sib2, iclass 10, count 0 2006.285.10:33:24.90#ibcon#flushed, iclass 10, count 0 2006.285.10:33:24.90#ibcon#about to write, iclass 10, count 0 2006.285.10:33:24.90#ibcon#wrote, iclass 10, count 0 2006.285.10:33:24.90#ibcon#about to read 3, iclass 10, count 0 2006.285.10:33:24.93#ibcon#read 3, iclass 10, count 0 2006.285.10:33:24.93#ibcon#about to read 4, iclass 10, count 0 2006.285.10:33:24.93#ibcon#read 4, iclass 10, count 0 2006.285.10:33:24.93#ibcon#about to read 5, iclass 10, count 0 2006.285.10:33:24.93#ibcon#read 5, iclass 10, count 0 2006.285.10:33:24.93#ibcon#about to read 6, iclass 10, count 0 2006.285.10:33:24.93#ibcon#read 6, iclass 10, count 0 2006.285.10:33:24.93#ibcon#end of sib2, iclass 10, count 0 2006.285.10:33:24.93#ibcon#*after write, iclass 10, count 0 2006.285.10:33:24.93#ibcon#*before return 0, iclass 10, count 0 2006.285.10:33:24.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:33:24.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:33:24.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:33:24.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:33:24.93$vck44/valo=3,564.99 2006.285.10:33:24.93#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.10:33:24.93#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.10:33:24.93#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:24.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:33:24.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:33:24.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:33:24.93#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:33:24.93#ibcon#first serial, iclass 12, count 0 2006.285.10:33:24.93#ibcon#enter sib2, iclass 12, count 0 2006.285.10:33:24.93#ibcon#flushed, iclass 12, count 0 2006.285.10:33:24.93#ibcon#about to write, iclass 12, count 0 2006.285.10:33:24.93#ibcon#wrote, iclass 12, count 0 2006.285.10:33:24.93#ibcon#about to read 3, iclass 12, count 0 2006.285.10:33:24.95#ibcon#read 3, iclass 12, count 0 2006.285.10:33:24.95#ibcon#about to read 4, iclass 12, count 0 2006.285.10:33:24.95#ibcon#read 4, iclass 12, count 0 2006.285.10:33:24.95#ibcon#about to read 5, iclass 12, count 0 2006.285.10:33:24.95#ibcon#read 5, iclass 12, count 0 2006.285.10:33:24.95#ibcon#about to read 6, iclass 12, count 0 2006.285.10:33:24.95#ibcon#read 6, iclass 12, count 0 2006.285.10:33:24.95#ibcon#end of sib2, iclass 12, count 0 2006.285.10:33:24.95#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:33:24.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:33:24.95#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:33:24.95#ibcon#*before write, iclass 12, count 0 2006.285.10:33:24.95#ibcon#enter sib2, iclass 12, count 0 2006.285.10:33:24.95#ibcon#flushed, iclass 12, count 0 2006.285.10:33:24.95#ibcon#about to write, iclass 12, count 0 2006.285.10:33:24.95#ibcon#wrote, iclass 12, count 0 2006.285.10:33:24.95#ibcon#about to read 3, iclass 12, count 0 2006.285.10:33:24.99#ibcon#read 3, iclass 12, count 0 2006.285.10:33:24.99#ibcon#about to read 4, iclass 12, count 0 2006.285.10:33:24.99#ibcon#read 4, iclass 12, count 0 2006.285.10:33:24.99#ibcon#about to read 5, iclass 12, count 0 2006.285.10:33:24.99#ibcon#read 5, iclass 12, count 0 2006.285.10:33:24.99#ibcon#about to read 6, iclass 12, count 0 2006.285.10:33:24.99#ibcon#read 6, iclass 12, count 0 2006.285.10:33:24.99#ibcon#end of sib2, iclass 12, count 0 2006.285.10:33:24.99#ibcon#*after write, iclass 12, count 0 2006.285.10:33:24.99#ibcon#*before return 0, iclass 12, count 0 2006.285.10:33:24.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:33:24.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:33:24.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:33:24.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:33:24.99$vck44/va=3,7 2006.285.10:33:24.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.10:33:24.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.10:33:24.99#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:24.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:33:25.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:33:25.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:33:25.05#ibcon#enter wrdev, iclass 14, count 2 2006.285.10:33:25.05#ibcon#first serial, iclass 14, count 2 2006.285.10:33:25.05#ibcon#enter sib2, iclass 14, count 2 2006.285.10:33:25.05#ibcon#flushed, iclass 14, count 2 2006.285.10:33:25.05#ibcon#about to write, iclass 14, count 2 2006.285.10:33:25.05#ibcon#wrote, iclass 14, count 2 2006.285.10:33:25.05#ibcon#about to read 3, iclass 14, count 2 2006.285.10:33:25.07#ibcon#read 3, iclass 14, count 2 2006.285.10:33:25.07#ibcon#about to read 4, iclass 14, count 2 2006.285.10:33:25.07#ibcon#read 4, iclass 14, count 2 2006.285.10:33:25.07#ibcon#about to read 5, iclass 14, count 2 2006.285.10:33:25.07#ibcon#read 5, iclass 14, count 2 2006.285.10:33:25.07#ibcon#about to read 6, iclass 14, count 2 2006.285.10:33:25.07#ibcon#read 6, iclass 14, count 2 2006.285.10:33:25.07#ibcon#end of sib2, iclass 14, count 2 2006.285.10:33:25.07#ibcon#*mode == 0, iclass 14, count 2 2006.285.10:33:25.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.10:33:25.07#ibcon#[25=AT03-07\r\n] 2006.285.10:33:25.07#ibcon#*before write, iclass 14, count 2 2006.285.10:33:25.07#ibcon#enter sib2, iclass 14, count 2 2006.285.10:33:25.07#ibcon#flushed, iclass 14, count 2 2006.285.10:33:25.07#ibcon#about to write, iclass 14, count 2 2006.285.10:33:25.07#ibcon#wrote, iclass 14, count 2 2006.285.10:33:25.07#ibcon#about to read 3, iclass 14, count 2 2006.285.10:33:25.10#ibcon#read 3, iclass 14, count 2 2006.285.10:33:25.10#ibcon#about to read 4, iclass 14, count 2 2006.285.10:33:25.10#ibcon#read 4, iclass 14, count 2 2006.285.10:33:25.10#ibcon#about to read 5, iclass 14, count 2 2006.285.10:33:25.10#ibcon#read 5, iclass 14, count 2 2006.285.10:33:25.10#ibcon#about to read 6, iclass 14, count 2 2006.285.10:33:25.10#ibcon#read 6, iclass 14, count 2 2006.285.10:33:25.10#ibcon#end of sib2, iclass 14, count 2 2006.285.10:33:25.10#ibcon#*after write, iclass 14, count 2 2006.285.10:33:25.10#ibcon#*before return 0, iclass 14, count 2 2006.285.10:33:25.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:33:25.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:33:25.10#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.10:33:25.10#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:25.10#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:33:25.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:33:25.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:33:25.22#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:33:25.22#ibcon#first serial, iclass 14, count 0 2006.285.10:33:25.22#ibcon#enter sib2, iclass 14, count 0 2006.285.10:33:25.22#ibcon#flushed, iclass 14, count 0 2006.285.10:33:25.22#ibcon#about to write, iclass 14, count 0 2006.285.10:33:25.22#ibcon#wrote, iclass 14, count 0 2006.285.10:33:25.22#ibcon#about to read 3, iclass 14, count 0 2006.285.10:33:25.24#ibcon#read 3, iclass 14, count 0 2006.285.10:33:25.24#ibcon#about to read 4, iclass 14, count 0 2006.285.10:33:25.24#ibcon#read 4, iclass 14, count 0 2006.285.10:33:25.24#ibcon#about to read 5, iclass 14, count 0 2006.285.10:33:25.24#ibcon#read 5, iclass 14, count 0 2006.285.10:33:25.24#ibcon#about to read 6, iclass 14, count 0 2006.285.10:33:25.24#ibcon#read 6, iclass 14, count 0 2006.285.10:33:25.24#ibcon#end of sib2, iclass 14, count 0 2006.285.10:33:25.24#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:33:25.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:33:25.24#ibcon#[25=USB\r\n] 2006.285.10:33:25.24#ibcon#*before write, iclass 14, count 0 2006.285.10:33:25.24#ibcon#enter sib2, iclass 14, count 0 2006.285.10:33:25.24#ibcon#flushed, iclass 14, count 0 2006.285.10:33:25.24#ibcon#about to write, iclass 14, count 0 2006.285.10:33:25.24#ibcon#wrote, iclass 14, count 0 2006.285.10:33:25.24#ibcon#about to read 3, iclass 14, count 0 2006.285.10:33:25.27#ibcon#read 3, iclass 14, count 0 2006.285.10:33:25.27#ibcon#about to read 4, iclass 14, count 0 2006.285.10:33:25.27#ibcon#read 4, iclass 14, count 0 2006.285.10:33:25.27#ibcon#about to read 5, iclass 14, count 0 2006.285.10:33:25.27#ibcon#read 5, iclass 14, count 0 2006.285.10:33:25.27#ibcon#about to read 6, iclass 14, count 0 2006.285.10:33:25.27#ibcon#read 6, iclass 14, count 0 2006.285.10:33:25.27#ibcon#end of sib2, iclass 14, count 0 2006.285.10:33:25.27#ibcon#*after write, iclass 14, count 0 2006.285.10:33:25.27#ibcon#*before return 0, iclass 14, count 0 2006.285.10:33:25.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:33:25.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:33:25.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:33:25.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:33:25.27$vck44/valo=4,624.99 2006.285.10:33:25.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.10:33:25.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.10:33:25.27#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:25.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:33:25.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:33:25.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:33:25.27#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:33:25.27#ibcon#first serial, iclass 16, count 0 2006.285.10:33:25.27#ibcon#enter sib2, iclass 16, count 0 2006.285.10:33:25.27#ibcon#flushed, iclass 16, count 0 2006.285.10:33:25.27#ibcon#about to write, iclass 16, count 0 2006.285.10:33:25.27#ibcon#wrote, iclass 16, count 0 2006.285.10:33:25.27#ibcon#about to read 3, iclass 16, count 0 2006.285.10:33:25.29#ibcon#read 3, iclass 16, count 0 2006.285.10:33:25.29#ibcon#about to read 4, iclass 16, count 0 2006.285.10:33:25.29#ibcon#read 4, iclass 16, count 0 2006.285.10:33:25.29#ibcon#about to read 5, iclass 16, count 0 2006.285.10:33:25.29#ibcon#read 5, iclass 16, count 0 2006.285.10:33:25.29#ibcon#about to read 6, iclass 16, count 0 2006.285.10:33:25.29#ibcon#read 6, iclass 16, count 0 2006.285.10:33:25.29#ibcon#end of sib2, iclass 16, count 0 2006.285.10:33:25.29#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:33:25.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:33:25.29#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:33:25.29#ibcon#*before write, iclass 16, count 0 2006.285.10:33:25.29#ibcon#enter sib2, iclass 16, count 0 2006.285.10:33:25.29#ibcon#flushed, iclass 16, count 0 2006.285.10:33:25.29#ibcon#about to write, iclass 16, count 0 2006.285.10:33:25.29#ibcon#wrote, iclass 16, count 0 2006.285.10:33:25.29#ibcon#about to read 3, iclass 16, count 0 2006.285.10:33:25.33#ibcon#read 3, iclass 16, count 0 2006.285.10:33:25.33#ibcon#about to read 4, iclass 16, count 0 2006.285.10:33:25.33#ibcon#read 4, iclass 16, count 0 2006.285.10:33:25.33#ibcon#about to read 5, iclass 16, count 0 2006.285.10:33:25.33#ibcon#read 5, iclass 16, count 0 2006.285.10:33:25.33#ibcon#about to read 6, iclass 16, count 0 2006.285.10:33:25.33#ibcon#read 6, iclass 16, count 0 2006.285.10:33:25.33#ibcon#end of sib2, iclass 16, count 0 2006.285.10:33:25.33#ibcon#*after write, iclass 16, count 0 2006.285.10:33:25.33#ibcon#*before return 0, iclass 16, count 0 2006.285.10:33:25.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:33:25.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:33:25.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:33:25.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:33:25.33$vck44/va=4,6 2006.285.10:33:25.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.10:33:25.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.10:33:25.33#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:25.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:33:25.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:33:25.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:33:25.39#ibcon#enter wrdev, iclass 18, count 2 2006.285.10:33:25.39#ibcon#first serial, iclass 18, count 2 2006.285.10:33:25.39#ibcon#enter sib2, iclass 18, count 2 2006.285.10:33:25.39#ibcon#flushed, iclass 18, count 2 2006.285.10:33:25.39#ibcon#about to write, iclass 18, count 2 2006.285.10:33:25.39#ibcon#wrote, iclass 18, count 2 2006.285.10:33:25.39#ibcon#about to read 3, iclass 18, count 2 2006.285.10:33:25.41#ibcon#read 3, iclass 18, count 2 2006.285.10:33:25.41#ibcon#about to read 4, iclass 18, count 2 2006.285.10:33:25.41#ibcon#read 4, iclass 18, count 2 2006.285.10:33:25.41#ibcon#about to read 5, iclass 18, count 2 2006.285.10:33:25.41#ibcon#read 5, iclass 18, count 2 2006.285.10:33:25.41#ibcon#about to read 6, iclass 18, count 2 2006.285.10:33:25.41#ibcon#read 6, iclass 18, count 2 2006.285.10:33:25.41#ibcon#end of sib2, iclass 18, count 2 2006.285.10:33:25.41#ibcon#*mode == 0, iclass 18, count 2 2006.285.10:33:25.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.10:33:25.41#ibcon#[25=AT04-06\r\n] 2006.285.10:33:25.41#ibcon#*before write, iclass 18, count 2 2006.285.10:33:25.41#ibcon#enter sib2, iclass 18, count 2 2006.285.10:33:25.41#ibcon#flushed, iclass 18, count 2 2006.285.10:33:25.41#ibcon#about to write, iclass 18, count 2 2006.285.10:33:25.41#ibcon#wrote, iclass 18, count 2 2006.285.10:33:25.41#ibcon#about to read 3, iclass 18, count 2 2006.285.10:33:25.44#ibcon#read 3, iclass 18, count 2 2006.285.10:33:25.44#ibcon#about to read 4, iclass 18, count 2 2006.285.10:33:25.44#ibcon#read 4, iclass 18, count 2 2006.285.10:33:25.44#ibcon#about to read 5, iclass 18, count 2 2006.285.10:33:25.44#ibcon#read 5, iclass 18, count 2 2006.285.10:33:25.44#ibcon#about to read 6, iclass 18, count 2 2006.285.10:33:25.44#ibcon#read 6, iclass 18, count 2 2006.285.10:33:25.44#ibcon#end of sib2, iclass 18, count 2 2006.285.10:33:25.44#ibcon#*after write, iclass 18, count 2 2006.285.10:33:25.44#ibcon#*before return 0, iclass 18, count 2 2006.285.10:33:25.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:33:25.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:33:25.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.10:33:25.44#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:25.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:33:25.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:33:25.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:33:25.56#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:33:25.56#ibcon#first serial, iclass 18, count 0 2006.285.10:33:25.56#ibcon#enter sib2, iclass 18, count 0 2006.285.10:33:25.56#ibcon#flushed, iclass 18, count 0 2006.285.10:33:25.56#ibcon#about to write, iclass 18, count 0 2006.285.10:33:25.56#ibcon#wrote, iclass 18, count 0 2006.285.10:33:25.56#ibcon#about to read 3, iclass 18, count 0 2006.285.10:33:25.58#ibcon#read 3, iclass 18, count 0 2006.285.10:33:25.58#ibcon#about to read 4, iclass 18, count 0 2006.285.10:33:25.58#ibcon#read 4, iclass 18, count 0 2006.285.10:33:25.58#ibcon#about to read 5, iclass 18, count 0 2006.285.10:33:25.58#ibcon#read 5, iclass 18, count 0 2006.285.10:33:25.58#ibcon#about to read 6, iclass 18, count 0 2006.285.10:33:25.58#ibcon#read 6, iclass 18, count 0 2006.285.10:33:25.58#ibcon#end of sib2, iclass 18, count 0 2006.285.10:33:25.58#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:33:25.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:33:25.58#ibcon#[25=USB\r\n] 2006.285.10:33:25.58#ibcon#*before write, iclass 18, count 0 2006.285.10:33:25.58#ibcon#enter sib2, iclass 18, count 0 2006.285.10:33:25.58#ibcon#flushed, iclass 18, count 0 2006.285.10:33:25.58#ibcon#about to write, iclass 18, count 0 2006.285.10:33:25.58#ibcon#wrote, iclass 18, count 0 2006.285.10:33:25.58#ibcon#about to read 3, iclass 18, count 0 2006.285.10:33:25.61#ibcon#read 3, iclass 18, count 0 2006.285.10:33:25.61#ibcon#about to read 4, iclass 18, count 0 2006.285.10:33:25.61#ibcon#read 4, iclass 18, count 0 2006.285.10:33:25.61#ibcon#about to read 5, iclass 18, count 0 2006.285.10:33:25.61#ibcon#read 5, iclass 18, count 0 2006.285.10:33:25.61#ibcon#about to read 6, iclass 18, count 0 2006.285.10:33:25.61#ibcon#read 6, iclass 18, count 0 2006.285.10:33:25.61#ibcon#end of sib2, iclass 18, count 0 2006.285.10:33:25.61#ibcon#*after write, iclass 18, count 0 2006.285.10:33:25.61#ibcon#*before return 0, iclass 18, count 0 2006.285.10:33:25.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:33:25.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:33:25.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:33:25.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:33:25.61$vck44/valo=5,734.99 2006.285.10:33:25.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.10:33:25.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.10:33:25.61#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:25.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:33:25.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:33:25.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:33:25.61#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:33:25.61#ibcon#first serial, iclass 20, count 0 2006.285.10:33:25.61#ibcon#enter sib2, iclass 20, count 0 2006.285.10:33:25.61#ibcon#flushed, iclass 20, count 0 2006.285.10:33:25.61#ibcon#about to write, iclass 20, count 0 2006.285.10:33:25.61#ibcon#wrote, iclass 20, count 0 2006.285.10:33:25.61#ibcon#about to read 3, iclass 20, count 0 2006.285.10:33:25.63#ibcon#read 3, iclass 20, count 0 2006.285.10:33:25.63#ibcon#about to read 4, iclass 20, count 0 2006.285.10:33:25.63#ibcon#read 4, iclass 20, count 0 2006.285.10:33:25.63#ibcon#about to read 5, iclass 20, count 0 2006.285.10:33:25.63#ibcon#read 5, iclass 20, count 0 2006.285.10:33:25.63#ibcon#about to read 6, iclass 20, count 0 2006.285.10:33:25.63#ibcon#read 6, iclass 20, count 0 2006.285.10:33:25.63#ibcon#end of sib2, iclass 20, count 0 2006.285.10:33:25.63#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:33:25.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:33:25.63#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:33:25.63#ibcon#*before write, iclass 20, count 0 2006.285.10:33:25.63#ibcon#enter sib2, iclass 20, count 0 2006.285.10:33:25.63#ibcon#flushed, iclass 20, count 0 2006.285.10:33:25.63#ibcon#about to write, iclass 20, count 0 2006.285.10:33:25.63#ibcon#wrote, iclass 20, count 0 2006.285.10:33:25.63#ibcon#about to read 3, iclass 20, count 0 2006.285.10:33:25.67#ibcon#read 3, iclass 20, count 0 2006.285.10:33:25.67#ibcon#about to read 4, iclass 20, count 0 2006.285.10:33:25.67#ibcon#read 4, iclass 20, count 0 2006.285.10:33:25.67#ibcon#about to read 5, iclass 20, count 0 2006.285.10:33:25.67#ibcon#read 5, iclass 20, count 0 2006.285.10:33:25.67#ibcon#about to read 6, iclass 20, count 0 2006.285.10:33:25.67#ibcon#read 6, iclass 20, count 0 2006.285.10:33:25.67#ibcon#end of sib2, iclass 20, count 0 2006.285.10:33:25.67#ibcon#*after write, iclass 20, count 0 2006.285.10:33:25.67#ibcon#*before return 0, iclass 20, count 0 2006.285.10:33:25.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:33:25.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:33:25.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:33:25.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:33:25.67$vck44/va=5,3 2006.285.10:33:25.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.10:33:25.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.10:33:25.67#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:25.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:33:25.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:33:25.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:33:25.73#ibcon#enter wrdev, iclass 22, count 2 2006.285.10:33:25.73#ibcon#first serial, iclass 22, count 2 2006.285.10:33:25.73#ibcon#enter sib2, iclass 22, count 2 2006.285.10:33:25.73#ibcon#flushed, iclass 22, count 2 2006.285.10:33:25.73#ibcon#about to write, iclass 22, count 2 2006.285.10:33:25.73#ibcon#wrote, iclass 22, count 2 2006.285.10:33:25.73#ibcon#about to read 3, iclass 22, count 2 2006.285.10:33:25.75#ibcon#read 3, iclass 22, count 2 2006.285.10:33:25.75#ibcon#about to read 4, iclass 22, count 2 2006.285.10:33:25.75#ibcon#read 4, iclass 22, count 2 2006.285.10:33:25.75#ibcon#about to read 5, iclass 22, count 2 2006.285.10:33:25.75#ibcon#read 5, iclass 22, count 2 2006.285.10:33:25.75#ibcon#about to read 6, iclass 22, count 2 2006.285.10:33:25.75#ibcon#read 6, iclass 22, count 2 2006.285.10:33:25.75#ibcon#end of sib2, iclass 22, count 2 2006.285.10:33:25.75#ibcon#*mode == 0, iclass 22, count 2 2006.285.10:33:25.75#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.10:33:25.75#ibcon#[25=AT05-03\r\n] 2006.285.10:33:25.75#ibcon#*before write, iclass 22, count 2 2006.285.10:33:25.75#ibcon#enter sib2, iclass 22, count 2 2006.285.10:33:25.75#ibcon#flushed, iclass 22, count 2 2006.285.10:33:25.75#ibcon#about to write, iclass 22, count 2 2006.285.10:33:25.75#ibcon#wrote, iclass 22, count 2 2006.285.10:33:25.75#ibcon#about to read 3, iclass 22, count 2 2006.285.10:33:25.78#ibcon#read 3, iclass 22, count 2 2006.285.10:33:25.78#ibcon#about to read 4, iclass 22, count 2 2006.285.10:33:25.78#ibcon#read 4, iclass 22, count 2 2006.285.10:33:25.78#ibcon#about to read 5, iclass 22, count 2 2006.285.10:33:25.78#ibcon#read 5, iclass 22, count 2 2006.285.10:33:25.78#ibcon#about to read 6, iclass 22, count 2 2006.285.10:33:25.78#ibcon#read 6, iclass 22, count 2 2006.285.10:33:25.78#ibcon#end of sib2, iclass 22, count 2 2006.285.10:33:25.78#ibcon#*after write, iclass 22, count 2 2006.285.10:33:25.78#ibcon#*before return 0, iclass 22, count 2 2006.285.10:33:25.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:33:25.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:33:25.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.10:33:25.78#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:25.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:33:25.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:33:25.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:33:25.90#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:33:25.90#ibcon#first serial, iclass 22, count 0 2006.285.10:33:25.90#ibcon#enter sib2, iclass 22, count 0 2006.285.10:33:25.90#ibcon#flushed, iclass 22, count 0 2006.285.10:33:25.90#ibcon#about to write, iclass 22, count 0 2006.285.10:33:25.90#ibcon#wrote, iclass 22, count 0 2006.285.10:33:25.90#ibcon#about to read 3, iclass 22, count 0 2006.285.10:33:25.92#ibcon#read 3, iclass 22, count 0 2006.285.10:33:25.92#ibcon#about to read 4, iclass 22, count 0 2006.285.10:33:25.92#ibcon#read 4, iclass 22, count 0 2006.285.10:33:25.92#ibcon#about to read 5, iclass 22, count 0 2006.285.10:33:25.92#ibcon#read 5, iclass 22, count 0 2006.285.10:33:25.92#ibcon#about to read 6, iclass 22, count 0 2006.285.10:33:25.92#ibcon#read 6, iclass 22, count 0 2006.285.10:33:25.92#ibcon#end of sib2, iclass 22, count 0 2006.285.10:33:25.92#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:33:25.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:33:25.92#ibcon#[25=USB\r\n] 2006.285.10:33:25.92#ibcon#*before write, iclass 22, count 0 2006.285.10:33:25.92#ibcon#enter sib2, iclass 22, count 0 2006.285.10:33:25.92#ibcon#flushed, iclass 22, count 0 2006.285.10:33:25.92#ibcon#about to write, iclass 22, count 0 2006.285.10:33:25.92#ibcon#wrote, iclass 22, count 0 2006.285.10:33:25.92#ibcon#about to read 3, iclass 22, count 0 2006.285.10:33:25.95#ibcon#read 3, iclass 22, count 0 2006.285.10:33:25.95#ibcon#about to read 4, iclass 22, count 0 2006.285.10:33:25.95#ibcon#read 4, iclass 22, count 0 2006.285.10:33:25.95#ibcon#about to read 5, iclass 22, count 0 2006.285.10:33:25.95#ibcon#read 5, iclass 22, count 0 2006.285.10:33:25.95#ibcon#about to read 6, iclass 22, count 0 2006.285.10:33:25.95#ibcon#read 6, iclass 22, count 0 2006.285.10:33:25.95#ibcon#end of sib2, iclass 22, count 0 2006.285.10:33:25.95#ibcon#*after write, iclass 22, count 0 2006.285.10:33:25.95#ibcon#*before return 0, iclass 22, count 0 2006.285.10:33:25.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:33:25.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:33:25.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:33:25.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:33:25.95$vck44/valo=6,814.99 2006.285.10:33:25.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.10:33:25.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.10:33:25.95#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:25.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:33:25.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:33:25.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:33:25.95#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:33:25.95#ibcon#first serial, iclass 24, count 0 2006.285.10:33:25.95#ibcon#enter sib2, iclass 24, count 0 2006.285.10:33:25.95#ibcon#flushed, iclass 24, count 0 2006.285.10:33:25.95#ibcon#about to write, iclass 24, count 0 2006.285.10:33:25.95#ibcon#wrote, iclass 24, count 0 2006.285.10:33:25.95#ibcon#about to read 3, iclass 24, count 0 2006.285.10:33:25.97#ibcon#read 3, iclass 24, count 0 2006.285.10:33:25.97#ibcon#about to read 4, iclass 24, count 0 2006.285.10:33:25.97#ibcon#read 4, iclass 24, count 0 2006.285.10:33:25.97#ibcon#about to read 5, iclass 24, count 0 2006.285.10:33:25.97#ibcon#read 5, iclass 24, count 0 2006.285.10:33:25.97#ibcon#about to read 6, iclass 24, count 0 2006.285.10:33:25.97#ibcon#read 6, iclass 24, count 0 2006.285.10:33:25.97#ibcon#end of sib2, iclass 24, count 0 2006.285.10:33:25.97#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:33:25.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:33:25.97#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:33:25.97#ibcon#*before write, iclass 24, count 0 2006.285.10:33:25.97#ibcon#enter sib2, iclass 24, count 0 2006.285.10:33:25.97#ibcon#flushed, iclass 24, count 0 2006.285.10:33:25.97#ibcon#about to write, iclass 24, count 0 2006.285.10:33:25.97#ibcon#wrote, iclass 24, count 0 2006.285.10:33:25.97#ibcon#about to read 3, iclass 24, count 0 2006.285.10:33:26.01#ibcon#read 3, iclass 24, count 0 2006.285.10:33:26.01#ibcon#about to read 4, iclass 24, count 0 2006.285.10:33:26.01#ibcon#read 4, iclass 24, count 0 2006.285.10:33:26.01#ibcon#about to read 5, iclass 24, count 0 2006.285.10:33:26.01#ibcon#read 5, iclass 24, count 0 2006.285.10:33:26.01#ibcon#about to read 6, iclass 24, count 0 2006.285.10:33:26.01#ibcon#read 6, iclass 24, count 0 2006.285.10:33:26.01#ibcon#end of sib2, iclass 24, count 0 2006.285.10:33:26.01#ibcon#*after write, iclass 24, count 0 2006.285.10:33:26.01#ibcon#*before return 0, iclass 24, count 0 2006.285.10:33:26.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:33:26.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:33:26.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:33:26.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:33:26.01$vck44/va=6,4 2006.285.10:33:26.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.10:33:26.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.10:33:26.01#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:26.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:33:26.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:33:26.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:33:26.07#ibcon#enter wrdev, iclass 26, count 2 2006.285.10:33:26.07#ibcon#first serial, iclass 26, count 2 2006.285.10:33:26.07#ibcon#enter sib2, iclass 26, count 2 2006.285.10:33:26.07#ibcon#flushed, iclass 26, count 2 2006.285.10:33:26.07#ibcon#about to write, iclass 26, count 2 2006.285.10:33:26.07#ibcon#wrote, iclass 26, count 2 2006.285.10:33:26.07#ibcon#about to read 3, iclass 26, count 2 2006.285.10:33:26.09#ibcon#read 3, iclass 26, count 2 2006.285.10:33:26.09#ibcon#about to read 4, iclass 26, count 2 2006.285.10:33:26.09#ibcon#read 4, iclass 26, count 2 2006.285.10:33:26.09#ibcon#about to read 5, iclass 26, count 2 2006.285.10:33:26.09#ibcon#read 5, iclass 26, count 2 2006.285.10:33:26.09#ibcon#about to read 6, iclass 26, count 2 2006.285.10:33:26.09#ibcon#read 6, iclass 26, count 2 2006.285.10:33:26.09#ibcon#end of sib2, iclass 26, count 2 2006.285.10:33:26.09#ibcon#*mode == 0, iclass 26, count 2 2006.285.10:33:26.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.10:33:26.09#ibcon#[25=AT06-04\r\n] 2006.285.10:33:26.09#ibcon#*before write, iclass 26, count 2 2006.285.10:33:26.09#ibcon#enter sib2, iclass 26, count 2 2006.285.10:33:26.09#ibcon#flushed, iclass 26, count 2 2006.285.10:33:26.09#ibcon#about to write, iclass 26, count 2 2006.285.10:33:26.09#ibcon#wrote, iclass 26, count 2 2006.285.10:33:26.09#ibcon#about to read 3, iclass 26, count 2 2006.285.10:33:26.12#ibcon#read 3, iclass 26, count 2 2006.285.10:33:26.12#ibcon#about to read 4, iclass 26, count 2 2006.285.10:33:26.12#ibcon#read 4, iclass 26, count 2 2006.285.10:33:26.12#ibcon#about to read 5, iclass 26, count 2 2006.285.10:33:26.12#ibcon#read 5, iclass 26, count 2 2006.285.10:33:26.12#ibcon#about to read 6, iclass 26, count 2 2006.285.10:33:26.12#ibcon#read 6, iclass 26, count 2 2006.285.10:33:26.12#ibcon#end of sib2, iclass 26, count 2 2006.285.10:33:26.12#ibcon#*after write, iclass 26, count 2 2006.285.10:33:26.12#ibcon#*before return 0, iclass 26, count 2 2006.285.10:33:26.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:33:26.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:33:26.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.10:33:26.12#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:26.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:33:26.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:33:26.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:33:26.24#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:33:26.24#ibcon#first serial, iclass 26, count 0 2006.285.10:33:26.24#ibcon#enter sib2, iclass 26, count 0 2006.285.10:33:26.24#ibcon#flushed, iclass 26, count 0 2006.285.10:33:26.24#ibcon#about to write, iclass 26, count 0 2006.285.10:33:26.24#ibcon#wrote, iclass 26, count 0 2006.285.10:33:26.24#ibcon#about to read 3, iclass 26, count 0 2006.285.10:33:26.26#ibcon#read 3, iclass 26, count 0 2006.285.10:33:26.26#ibcon#about to read 4, iclass 26, count 0 2006.285.10:33:26.26#ibcon#read 4, iclass 26, count 0 2006.285.10:33:26.26#ibcon#about to read 5, iclass 26, count 0 2006.285.10:33:26.26#ibcon#read 5, iclass 26, count 0 2006.285.10:33:26.26#ibcon#about to read 6, iclass 26, count 0 2006.285.10:33:26.26#ibcon#read 6, iclass 26, count 0 2006.285.10:33:26.26#ibcon#end of sib2, iclass 26, count 0 2006.285.10:33:26.26#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:33:26.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:33:26.26#ibcon#[25=USB\r\n] 2006.285.10:33:26.26#ibcon#*before write, iclass 26, count 0 2006.285.10:33:26.26#ibcon#enter sib2, iclass 26, count 0 2006.285.10:33:26.26#ibcon#flushed, iclass 26, count 0 2006.285.10:33:26.26#ibcon#about to write, iclass 26, count 0 2006.285.10:33:26.26#ibcon#wrote, iclass 26, count 0 2006.285.10:33:26.26#ibcon#about to read 3, iclass 26, count 0 2006.285.10:33:26.29#ibcon#read 3, iclass 26, count 0 2006.285.10:33:26.29#ibcon#about to read 4, iclass 26, count 0 2006.285.10:33:26.29#ibcon#read 4, iclass 26, count 0 2006.285.10:33:26.29#ibcon#about to read 5, iclass 26, count 0 2006.285.10:33:26.29#ibcon#read 5, iclass 26, count 0 2006.285.10:33:26.29#ibcon#about to read 6, iclass 26, count 0 2006.285.10:33:26.29#ibcon#read 6, iclass 26, count 0 2006.285.10:33:26.29#ibcon#end of sib2, iclass 26, count 0 2006.285.10:33:26.29#ibcon#*after write, iclass 26, count 0 2006.285.10:33:26.29#ibcon#*before return 0, iclass 26, count 0 2006.285.10:33:26.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:33:26.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:33:26.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:33:26.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:33:26.29$vck44/valo=7,864.99 2006.285.10:33:26.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.10:33:26.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.10:33:26.29#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:26.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:33:26.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:33:26.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:33:26.29#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:33:26.29#ibcon#first serial, iclass 28, count 0 2006.285.10:33:26.29#ibcon#enter sib2, iclass 28, count 0 2006.285.10:33:26.29#ibcon#flushed, iclass 28, count 0 2006.285.10:33:26.29#ibcon#about to write, iclass 28, count 0 2006.285.10:33:26.29#ibcon#wrote, iclass 28, count 0 2006.285.10:33:26.29#ibcon#about to read 3, iclass 28, count 0 2006.285.10:33:26.31#ibcon#read 3, iclass 28, count 0 2006.285.10:33:26.31#ibcon#about to read 4, iclass 28, count 0 2006.285.10:33:26.31#ibcon#read 4, iclass 28, count 0 2006.285.10:33:26.31#ibcon#about to read 5, iclass 28, count 0 2006.285.10:33:26.31#ibcon#read 5, iclass 28, count 0 2006.285.10:33:26.31#ibcon#about to read 6, iclass 28, count 0 2006.285.10:33:26.31#ibcon#read 6, iclass 28, count 0 2006.285.10:33:26.31#ibcon#end of sib2, iclass 28, count 0 2006.285.10:33:26.31#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:33:26.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:33:26.31#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:33:26.31#ibcon#*before write, iclass 28, count 0 2006.285.10:33:26.31#ibcon#enter sib2, iclass 28, count 0 2006.285.10:33:26.31#ibcon#flushed, iclass 28, count 0 2006.285.10:33:26.31#ibcon#about to write, iclass 28, count 0 2006.285.10:33:26.31#ibcon#wrote, iclass 28, count 0 2006.285.10:33:26.31#ibcon#about to read 3, iclass 28, count 0 2006.285.10:33:26.35#ibcon#read 3, iclass 28, count 0 2006.285.10:33:26.35#ibcon#about to read 4, iclass 28, count 0 2006.285.10:33:26.35#ibcon#read 4, iclass 28, count 0 2006.285.10:33:26.35#ibcon#about to read 5, iclass 28, count 0 2006.285.10:33:26.35#ibcon#read 5, iclass 28, count 0 2006.285.10:33:26.35#ibcon#about to read 6, iclass 28, count 0 2006.285.10:33:26.35#ibcon#read 6, iclass 28, count 0 2006.285.10:33:26.35#ibcon#end of sib2, iclass 28, count 0 2006.285.10:33:26.35#ibcon#*after write, iclass 28, count 0 2006.285.10:33:26.35#ibcon#*before return 0, iclass 28, count 0 2006.285.10:33:26.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:33:26.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:33:26.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:33:26.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:33:26.35$vck44/va=7,4 2006.285.10:33:26.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.10:33:26.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.10:33:26.35#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:26.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:33:26.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:33:26.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:33:26.41#ibcon#enter wrdev, iclass 30, count 2 2006.285.10:33:26.41#ibcon#first serial, iclass 30, count 2 2006.285.10:33:26.41#ibcon#enter sib2, iclass 30, count 2 2006.285.10:33:26.41#ibcon#flushed, iclass 30, count 2 2006.285.10:33:26.41#ibcon#about to write, iclass 30, count 2 2006.285.10:33:26.41#ibcon#wrote, iclass 30, count 2 2006.285.10:33:26.41#ibcon#about to read 3, iclass 30, count 2 2006.285.10:33:26.43#ibcon#read 3, iclass 30, count 2 2006.285.10:33:26.43#ibcon#about to read 4, iclass 30, count 2 2006.285.10:33:26.43#ibcon#read 4, iclass 30, count 2 2006.285.10:33:26.43#ibcon#about to read 5, iclass 30, count 2 2006.285.10:33:26.43#ibcon#read 5, iclass 30, count 2 2006.285.10:33:26.43#ibcon#about to read 6, iclass 30, count 2 2006.285.10:33:26.43#ibcon#read 6, iclass 30, count 2 2006.285.10:33:26.43#ibcon#end of sib2, iclass 30, count 2 2006.285.10:33:26.43#ibcon#*mode == 0, iclass 30, count 2 2006.285.10:33:26.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.10:33:26.43#ibcon#[25=AT07-04\r\n] 2006.285.10:33:26.43#ibcon#*before write, iclass 30, count 2 2006.285.10:33:26.43#ibcon#enter sib2, iclass 30, count 2 2006.285.10:33:26.43#ibcon#flushed, iclass 30, count 2 2006.285.10:33:26.43#ibcon#about to write, iclass 30, count 2 2006.285.10:33:26.43#ibcon#wrote, iclass 30, count 2 2006.285.10:33:26.43#ibcon#about to read 3, iclass 30, count 2 2006.285.10:33:26.46#ibcon#read 3, iclass 30, count 2 2006.285.10:33:26.46#ibcon#about to read 4, iclass 30, count 2 2006.285.10:33:26.46#ibcon#read 4, iclass 30, count 2 2006.285.10:33:26.46#ibcon#about to read 5, iclass 30, count 2 2006.285.10:33:26.46#ibcon#read 5, iclass 30, count 2 2006.285.10:33:26.46#ibcon#about to read 6, iclass 30, count 2 2006.285.10:33:26.46#ibcon#read 6, iclass 30, count 2 2006.285.10:33:26.46#ibcon#end of sib2, iclass 30, count 2 2006.285.10:33:26.46#ibcon#*after write, iclass 30, count 2 2006.285.10:33:26.46#ibcon#*before return 0, iclass 30, count 2 2006.285.10:33:26.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:33:26.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:33:26.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.10:33:26.46#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:26.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:33:26.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:33:26.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:33:26.58#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:33:26.58#ibcon#first serial, iclass 30, count 0 2006.285.10:33:26.58#ibcon#enter sib2, iclass 30, count 0 2006.285.10:33:26.58#ibcon#flushed, iclass 30, count 0 2006.285.10:33:26.58#ibcon#about to write, iclass 30, count 0 2006.285.10:33:26.58#ibcon#wrote, iclass 30, count 0 2006.285.10:33:26.58#ibcon#about to read 3, iclass 30, count 0 2006.285.10:33:26.60#ibcon#read 3, iclass 30, count 0 2006.285.10:33:26.60#ibcon#about to read 4, iclass 30, count 0 2006.285.10:33:26.60#ibcon#read 4, iclass 30, count 0 2006.285.10:33:26.60#ibcon#about to read 5, iclass 30, count 0 2006.285.10:33:26.60#ibcon#read 5, iclass 30, count 0 2006.285.10:33:26.60#ibcon#about to read 6, iclass 30, count 0 2006.285.10:33:26.60#ibcon#read 6, iclass 30, count 0 2006.285.10:33:26.60#ibcon#end of sib2, iclass 30, count 0 2006.285.10:33:26.60#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:33:26.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:33:26.60#ibcon#[25=USB\r\n] 2006.285.10:33:26.60#ibcon#*before write, iclass 30, count 0 2006.285.10:33:26.60#ibcon#enter sib2, iclass 30, count 0 2006.285.10:33:26.60#ibcon#flushed, iclass 30, count 0 2006.285.10:33:26.60#ibcon#about to write, iclass 30, count 0 2006.285.10:33:26.60#ibcon#wrote, iclass 30, count 0 2006.285.10:33:26.60#ibcon#about to read 3, iclass 30, count 0 2006.285.10:33:26.63#ibcon#read 3, iclass 30, count 0 2006.285.10:33:26.63#ibcon#about to read 4, iclass 30, count 0 2006.285.10:33:26.63#ibcon#read 4, iclass 30, count 0 2006.285.10:33:26.63#ibcon#about to read 5, iclass 30, count 0 2006.285.10:33:26.63#ibcon#read 5, iclass 30, count 0 2006.285.10:33:26.63#ibcon#about to read 6, iclass 30, count 0 2006.285.10:33:26.63#ibcon#read 6, iclass 30, count 0 2006.285.10:33:26.63#ibcon#end of sib2, iclass 30, count 0 2006.285.10:33:26.63#ibcon#*after write, iclass 30, count 0 2006.285.10:33:26.63#ibcon#*before return 0, iclass 30, count 0 2006.285.10:33:26.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:33:26.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:33:26.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:33:26.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:33:26.63$vck44/valo=8,884.99 2006.285.10:33:26.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.10:33:26.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.10:33:26.63#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:26.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:33:26.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:33:26.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:33:26.63#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:33:26.63#ibcon#first serial, iclass 32, count 0 2006.285.10:33:26.63#ibcon#enter sib2, iclass 32, count 0 2006.285.10:33:26.63#ibcon#flushed, iclass 32, count 0 2006.285.10:33:26.63#ibcon#about to write, iclass 32, count 0 2006.285.10:33:26.63#ibcon#wrote, iclass 32, count 0 2006.285.10:33:26.63#ibcon#about to read 3, iclass 32, count 0 2006.285.10:33:26.65#ibcon#read 3, iclass 32, count 0 2006.285.10:33:26.65#ibcon#about to read 4, iclass 32, count 0 2006.285.10:33:26.65#ibcon#read 4, iclass 32, count 0 2006.285.10:33:26.65#ibcon#about to read 5, iclass 32, count 0 2006.285.10:33:26.65#ibcon#read 5, iclass 32, count 0 2006.285.10:33:26.65#ibcon#about to read 6, iclass 32, count 0 2006.285.10:33:26.65#ibcon#read 6, iclass 32, count 0 2006.285.10:33:26.65#ibcon#end of sib2, iclass 32, count 0 2006.285.10:33:26.65#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:33:26.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:33:26.65#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:33:26.65#ibcon#*before write, iclass 32, count 0 2006.285.10:33:26.65#ibcon#enter sib2, iclass 32, count 0 2006.285.10:33:26.65#ibcon#flushed, iclass 32, count 0 2006.285.10:33:26.65#ibcon#about to write, iclass 32, count 0 2006.285.10:33:26.65#ibcon#wrote, iclass 32, count 0 2006.285.10:33:26.65#ibcon#about to read 3, iclass 32, count 0 2006.285.10:33:26.69#ibcon#read 3, iclass 32, count 0 2006.285.10:33:26.69#ibcon#about to read 4, iclass 32, count 0 2006.285.10:33:26.69#ibcon#read 4, iclass 32, count 0 2006.285.10:33:26.69#ibcon#about to read 5, iclass 32, count 0 2006.285.10:33:26.69#ibcon#read 5, iclass 32, count 0 2006.285.10:33:26.69#ibcon#about to read 6, iclass 32, count 0 2006.285.10:33:26.69#ibcon#read 6, iclass 32, count 0 2006.285.10:33:26.69#ibcon#end of sib2, iclass 32, count 0 2006.285.10:33:26.69#ibcon#*after write, iclass 32, count 0 2006.285.10:33:26.69#ibcon#*before return 0, iclass 32, count 0 2006.285.10:33:26.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:33:26.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:33:26.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:33:26.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:33:26.69$vck44/va=8,3 2006.285.10:33:26.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.10:33:26.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.10:33:26.69#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:26.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:33:26.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:33:26.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:33:26.75#ibcon#enter wrdev, iclass 34, count 2 2006.285.10:33:26.75#ibcon#first serial, iclass 34, count 2 2006.285.10:33:26.75#ibcon#enter sib2, iclass 34, count 2 2006.285.10:33:26.75#ibcon#flushed, iclass 34, count 2 2006.285.10:33:26.75#ibcon#about to write, iclass 34, count 2 2006.285.10:33:26.75#ibcon#wrote, iclass 34, count 2 2006.285.10:33:26.75#ibcon#about to read 3, iclass 34, count 2 2006.285.10:33:26.77#ibcon#read 3, iclass 34, count 2 2006.285.10:33:26.77#ibcon#about to read 4, iclass 34, count 2 2006.285.10:33:26.77#ibcon#read 4, iclass 34, count 2 2006.285.10:33:26.77#ibcon#about to read 5, iclass 34, count 2 2006.285.10:33:26.77#ibcon#read 5, iclass 34, count 2 2006.285.10:33:26.77#ibcon#about to read 6, iclass 34, count 2 2006.285.10:33:26.77#ibcon#read 6, iclass 34, count 2 2006.285.10:33:26.77#ibcon#end of sib2, iclass 34, count 2 2006.285.10:33:26.77#ibcon#*mode == 0, iclass 34, count 2 2006.285.10:33:26.77#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.10:33:26.77#ibcon#[25=AT08-03\r\n] 2006.285.10:33:26.77#ibcon#*before write, iclass 34, count 2 2006.285.10:33:26.77#ibcon#enter sib2, iclass 34, count 2 2006.285.10:33:26.77#ibcon#flushed, iclass 34, count 2 2006.285.10:33:26.77#ibcon#about to write, iclass 34, count 2 2006.285.10:33:26.77#ibcon#wrote, iclass 34, count 2 2006.285.10:33:26.77#ibcon#about to read 3, iclass 34, count 2 2006.285.10:33:26.80#ibcon#read 3, iclass 34, count 2 2006.285.10:33:26.80#ibcon#about to read 4, iclass 34, count 2 2006.285.10:33:26.80#ibcon#read 4, iclass 34, count 2 2006.285.10:33:26.80#ibcon#about to read 5, iclass 34, count 2 2006.285.10:33:26.80#ibcon#read 5, iclass 34, count 2 2006.285.10:33:26.80#ibcon#about to read 6, iclass 34, count 2 2006.285.10:33:26.80#ibcon#read 6, iclass 34, count 2 2006.285.10:33:26.80#ibcon#end of sib2, iclass 34, count 2 2006.285.10:33:26.80#ibcon#*after write, iclass 34, count 2 2006.285.10:33:26.80#ibcon#*before return 0, iclass 34, count 2 2006.285.10:33:26.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:33:26.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:33:26.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.10:33:26.80#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:26.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:33:26.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:33:26.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:33:26.92#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:33:26.92#ibcon#first serial, iclass 34, count 0 2006.285.10:33:26.92#ibcon#enter sib2, iclass 34, count 0 2006.285.10:33:26.92#ibcon#flushed, iclass 34, count 0 2006.285.10:33:26.92#ibcon#about to write, iclass 34, count 0 2006.285.10:33:26.92#ibcon#wrote, iclass 34, count 0 2006.285.10:33:26.92#ibcon#about to read 3, iclass 34, count 0 2006.285.10:33:26.94#ibcon#read 3, iclass 34, count 0 2006.285.10:33:26.94#ibcon#about to read 4, iclass 34, count 0 2006.285.10:33:26.94#ibcon#read 4, iclass 34, count 0 2006.285.10:33:26.94#ibcon#about to read 5, iclass 34, count 0 2006.285.10:33:26.94#ibcon#read 5, iclass 34, count 0 2006.285.10:33:26.94#ibcon#about to read 6, iclass 34, count 0 2006.285.10:33:26.94#ibcon#read 6, iclass 34, count 0 2006.285.10:33:26.94#ibcon#end of sib2, iclass 34, count 0 2006.285.10:33:26.94#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:33:26.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:33:26.94#ibcon#[25=USB\r\n] 2006.285.10:33:26.94#ibcon#*before write, iclass 34, count 0 2006.285.10:33:26.94#ibcon#enter sib2, iclass 34, count 0 2006.285.10:33:26.94#ibcon#flushed, iclass 34, count 0 2006.285.10:33:26.94#ibcon#about to write, iclass 34, count 0 2006.285.10:33:26.94#ibcon#wrote, iclass 34, count 0 2006.285.10:33:26.94#ibcon#about to read 3, iclass 34, count 0 2006.285.10:33:26.97#ibcon#read 3, iclass 34, count 0 2006.285.10:33:26.97#ibcon#about to read 4, iclass 34, count 0 2006.285.10:33:26.97#ibcon#read 4, iclass 34, count 0 2006.285.10:33:26.97#ibcon#about to read 5, iclass 34, count 0 2006.285.10:33:26.97#ibcon#read 5, iclass 34, count 0 2006.285.10:33:26.97#ibcon#about to read 6, iclass 34, count 0 2006.285.10:33:26.97#ibcon#read 6, iclass 34, count 0 2006.285.10:33:26.97#ibcon#end of sib2, iclass 34, count 0 2006.285.10:33:26.97#ibcon#*after write, iclass 34, count 0 2006.285.10:33:26.97#ibcon#*before return 0, iclass 34, count 0 2006.285.10:33:26.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:33:26.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:33:26.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:33:26.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:33:26.97$vck44/vblo=1,629.99 2006.285.10:33:26.97#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.10:33:26.97#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.10:33:26.97#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:26.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:33:26.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:33:26.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:33:26.97#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:33:26.97#ibcon#first serial, iclass 36, count 0 2006.285.10:33:26.97#ibcon#enter sib2, iclass 36, count 0 2006.285.10:33:26.97#ibcon#flushed, iclass 36, count 0 2006.285.10:33:26.97#ibcon#about to write, iclass 36, count 0 2006.285.10:33:26.97#ibcon#wrote, iclass 36, count 0 2006.285.10:33:26.97#ibcon#about to read 3, iclass 36, count 0 2006.285.10:33:26.99#ibcon#read 3, iclass 36, count 0 2006.285.10:33:26.99#ibcon#about to read 4, iclass 36, count 0 2006.285.10:33:26.99#ibcon#read 4, iclass 36, count 0 2006.285.10:33:26.99#ibcon#about to read 5, iclass 36, count 0 2006.285.10:33:26.99#ibcon#read 5, iclass 36, count 0 2006.285.10:33:26.99#ibcon#about to read 6, iclass 36, count 0 2006.285.10:33:26.99#ibcon#read 6, iclass 36, count 0 2006.285.10:33:26.99#ibcon#end of sib2, iclass 36, count 0 2006.285.10:33:26.99#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:33:26.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:33:26.99#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:33:26.99#ibcon#*before write, iclass 36, count 0 2006.285.10:33:26.99#ibcon#enter sib2, iclass 36, count 0 2006.285.10:33:26.99#ibcon#flushed, iclass 36, count 0 2006.285.10:33:26.99#ibcon#about to write, iclass 36, count 0 2006.285.10:33:26.99#ibcon#wrote, iclass 36, count 0 2006.285.10:33:26.99#ibcon#about to read 3, iclass 36, count 0 2006.285.10:33:27.03#ibcon#read 3, iclass 36, count 0 2006.285.10:33:27.03#ibcon#about to read 4, iclass 36, count 0 2006.285.10:33:27.03#ibcon#read 4, iclass 36, count 0 2006.285.10:33:27.03#ibcon#about to read 5, iclass 36, count 0 2006.285.10:33:27.03#ibcon#read 5, iclass 36, count 0 2006.285.10:33:27.03#ibcon#about to read 6, iclass 36, count 0 2006.285.10:33:27.03#ibcon#read 6, iclass 36, count 0 2006.285.10:33:27.03#ibcon#end of sib2, iclass 36, count 0 2006.285.10:33:27.03#ibcon#*after write, iclass 36, count 0 2006.285.10:33:27.03#ibcon#*before return 0, iclass 36, count 0 2006.285.10:33:27.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:33:27.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:33:27.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:33:27.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:33:27.03$vck44/vb=1,4 2006.285.10:33:27.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.10:33:27.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.10:33:27.03#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:27.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:33:27.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:33:27.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:33:27.03#ibcon#enter wrdev, iclass 38, count 2 2006.285.10:33:27.03#ibcon#first serial, iclass 38, count 2 2006.285.10:33:27.03#ibcon#enter sib2, iclass 38, count 2 2006.285.10:33:27.03#ibcon#flushed, iclass 38, count 2 2006.285.10:33:27.03#ibcon#about to write, iclass 38, count 2 2006.285.10:33:27.03#ibcon#wrote, iclass 38, count 2 2006.285.10:33:27.03#ibcon#about to read 3, iclass 38, count 2 2006.285.10:33:27.05#ibcon#read 3, iclass 38, count 2 2006.285.10:33:27.05#ibcon#about to read 4, iclass 38, count 2 2006.285.10:33:27.05#ibcon#read 4, iclass 38, count 2 2006.285.10:33:27.05#ibcon#about to read 5, iclass 38, count 2 2006.285.10:33:27.05#ibcon#read 5, iclass 38, count 2 2006.285.10:33:27.05#ibcon#about to read 6, iclass 38, count 2 2006.285.10:33:27.05#ibcon#read 6, iclass 38, count 2 2006.285.10:33:27.05#ibcon#end of sib2, iclass 38, count 2 2006.285.10:33:27.05#ibcon#*mode == 0, iclass 38, count 2 2006.285.10:33:27.05#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.10:33:27.05#ibcon#[27=AT01-04\r\n] 2006.285.10:33:27.05#ibcon#*before write, iclass 38, count 2 2006.285.10:33:27.05#ibcon#enter sib2, iclass 38, count 2 2006.285.10:33:27.05#ibcon#flushed, iclass 38, count 2 2006.285.10:33:27.05#ibcon#about to write, iclass 38, count 2 2006.285.10:33:27.05#ibcon#wrote, iclass 38, count 2 2006.285.10:33:27.05#ibcon#about to read 3, iclass 38, count 2 2006.285.10:33:27.08#ibcon#read 3, iclass 38, count 2 2006.285.10:33:27.08#ibcon#about to read 4, iclass 38, count 2 2006.285.10:33:27.08#ibcon#read 4, iclass 38, count 2 2006.285.10:33:27.08#ibcon#about to read 5, iclass 38, count 2 2006.285.10:33:27.08#ibcon#read 5, iclass 38, count 2 2006.285.10:33:27.08#ibcon#about to read 6, iclass 38, count 2 2006.285.10:33:27.08#ibcon#read 6, iclass 38, count 2 2006.285.10:33:27.08#ibcon#end of sib2, iclass 38, count 2 2006.285.10:33:27.08#ibcon#*after write, iclass 38, count 2 2006.285.10:33:27.08#ibcon#*before return 0, iclass 38, count 2 2006.285.10:33:27.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:33:27.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:33:27.08#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.10:33:27.08#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:27.08#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:33:27.20#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:33:27.20#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:33:27.20#ibcon#enter wrdev, iclass 38, count 0 2006.285.10:33:27.20#ibcon#first serial, iclass 38, count 0 2006.285.10:33:27.20#ibcon#enter sib2, iclass 38, count 0 2006.285.10:33:27.20#ibcon#flushed, iclass 38, count 0 2006.285.10:33:27.20#ibcon#about to write, iclass 38, count 0 2006.285.10:33:27.20#ibcon#wrote, iclass 38, count 0 2006.285.10:33:27.20#ibcon#about to read 3, iclass 38, count 0 2006.285.10:33:27.22#ibcon#read 3, iclass 38, count 0 2006.285.10:33:27.22#ibcon#about to read 4, iclass 38, count 0 2006.285.10:33:27.22#ibcon#read 4, iclass 38, count 0 2006.285.10:33:27.22#ibcon#about to read 5, iclass 38, count 0 2006.285.10:33:27.22#ibcon#read 5, iclass 38, count 0 2006.285.10:33:27.22#ibcon#about to read 6, iclass 38, count 0 2006.285.10:33:27.22#ibcon#read 6, iclass 38, count 0 2006.285.10:33:27.22#ibcon#end of sib2, iclass 38, count 0 2006.285.10:33:27.22#ibcon#*mode == 0, iclass 38, count 0 2006.285.10:33:27.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.10:33:27.22#ibcon#[27=USB\r\n] 2006.285.10:33:27.22#ibcon#*before write, iclass 38, count 0 2006.285.10:33:27.22#ibcon#enter sib2, iclass 38, count 0 2006.285.10:33:27.22#ibcon#flushed, iclass 38, count 0 2006.285.10:33:27.22#ibcon#about to write, iclass 38, count 0 2006.285.10:33:27.22#ibcon#wrote, iclass 38, count 0 2006.285.10:33:27.22#ibcon#about to read 3, iclass 38, count 0 2006.285.10:33:27.25#ibcon#read 3, iclass 38, count 0 2006.285.10:33:27.25#ibcon#about to read 4, iclass 38, count 0 2006.285.10:33:27.25#ibcon#read 4, iclass 38, count 0 2006.285.10:33:27.25#ibcon#about to read 5, iclass 38, count 0 2006.285.10:33:27.25#ibcon#read 5, iclass 38, count 0 2006.285.10:33:27.25#ibcon#about to read 6, iclass 38, count 0 2006.285.10:33:27.25#ibcon#read 6, iclass 38, count 0 2006.285.10:33:27.25#ibcon#end of sib2, iclass 38, count 0 2006.285.10:33:27.25#ibcon#*after write, iclass 38, count 0 2006.285.10:33:27.25#ibcon#*before return 0, iclass 38, count 0 2006.285.10:33:27.25#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:33:27.25#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:33:27.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.10:33:27.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.10:33:27.25$vck44/vblo=2,634.99 2006.285.10:33:27.25#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.10:33:27.25#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.10:33:27.25#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:27.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:33:27.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:33:27.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:33:27.25#ibcon#enter wrdev, iclass 40, count 0 2006.285.10:33:27.25#ibcon#first serial, iclass 40, count 0 2006.285.10:33:27.25#ibcon#enter sib2, iclass 40, count 0 2006.285.10:33:27.25#ibcon#flushed, iclass 40, count 0 2006.285.10:33:27.25#ibcon#about to write, iclass 40, count 0 2006.285.10:33:27.25#ibcon#wrote, iclass 40, count 0 2006.285.10:33:27.25#ibcon#about to read 3, iclass 40, count 0 2006.285.10:33:27.27#ibcon#read 3, iclass 40, count 0 2006.285.10:33:27.27#ibcon#about to read 4, iclass 40, count 0 2006.285.10:33:27.27#ibcon#read 4, iclass 40, count 0 2006.285.10:33:27.27#ibcon#about to read 5, iclass 40, count 0 2006.285.10:33:27.27#ibcon#read 5, iclass 40, count 0 2006.285.10:33:27.27#ibcon#about to read 6, iclass 40, count 0 2006.285.10:33:27.27#ibcon#read 6, iclass 40, count 0 2006.285.10:33:27.27#ibcon#end of sib2, iclass 40, count 0 2006.285.10:33:27.27#ibcon#*mode == 0, iclass 40, count 0 2006.285.10:33:27.27#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.10:33:27.27#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:33:27.27#ibcon#*before write, iclass 40, count 0 2006.285.10:33:27.27#ibcon#enter sib2, iclass 40, count 0 2006.285.10:33:27.27#ibcon#flushed, iclass 40, count 0 2006.285.10:33:27.27#ibcon#about to write, iclass 40, count 0 2006.285.10:33:27.27#ibcon#wrote, iclass 40, count 0 2006.285.10:33:27.27#ibcon#about to read 3, iclass 40, count 0 2006.285.10:33:27.31#ibcon#read 3, iclass 40, count 0 2006.285.10:33:27.31#ibcon#about to read 4, iclass 40, count 0 2006.285.10:33:27.31#ibcon#read 4, iclass 40, count 0 2006.285.10:33:27.31#ibcon#about to read 5, iclass 40, count 0 2006.285.10:33:27.31#ibcon#read 5, iclass 40, count 0 2006.285.10:33:27.31#ibcon#about to read 6, iclass 40, count 0 2006.285.10:33:27.31#ibcon#read 6, iclass 40, count 0 2006.285.10:33:27.31#ibcon#end of sib2, iclass 40, count 0 2006.285.10:33:27.31#ibcon#*after write, iclass 40, count 0 2006.285.10:33:27.31#ibcon#*before return 0, iclass 40, count 0 2006.285.10:33:27.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:33:27.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:33:27.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.10:33:27.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.10:33:27.31$vck44/vb=2,5 2006.285.10:33:27.31#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.10:33:27.31#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.10:33:27.31#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:27.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:33:27.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:33:27.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:33:27.37#ibcon#enter wrdev, iclass 4, count 2 2006.285.10:33:27.37#ibcon#first serial, iclass 4, count 2 2006.285.10:33:27.37#ibcon#enter sib2, iclass 4, count 2 2006.285.10:33:27.37#ibcon#flushed, iclass 4, count 2 2006.285.10:33:27.37#ibcon#about to write, iclass 4, count 2 2006.285.10:33:27.37#ibcon#wrote, iclass 4, count 2 2006.285.10:33:27.37#ibcon#about to read 3, iclass 4, count 2 2006.285.10:33:27.39#ibcon#read 3, iclass 4, count 2 2006.285.10:33:27.39#ibcon#about to read 4, iclass 4, count 2 2006.285.10:33:27.39#ibcon#read 4, iclass 4, count 2 2006.285.10:33:27.39#ibcon#about to read 5, iclass 4, count 2 2006.285.10:33:27.39#ibcon#read 5, iclass 4, count 2 2006.285.10:33:27.39#ibcon#about to read 6, iclass 4, count 2 2006.285.10:33:27.39#ibcon#read 6, iclass 4, count 2 2006.285.10:33:27.39#ibcon#end of sib2, iclass 4, count 2 2006.285.10:33:27.39#ibcon#*mode == 0, iclass 4, count 2 2006.285.10:33:27.39#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.10:33:27.39#ibcon#[27=AT02-05\r\n] 2006.285.10:33:27.39#ibcon#*before write, iclass 4, count 2 2006.285.10:33:27.39#ibcon#enter sib2, iclass 4, count 2 2006.285.10:33:27.39#ibcon#flushed, iclass 4, count 2 2006.285.10:33:27.39#ibcon#about to write, iclass 4, count 2 2006.285.10:33:27.39#ibcon#wrote, iclass 4, count 2 2006.285.10:33:27.39#ibcon#about to read 3, iclass 4, count 2 2006.285.10:33:27.42#ibcon#read 3, iclass 4, count 2 2006.285.10:33:27.42#ibcon#about to read 4, iclass 4, count 2 2006.285.10:33:27.42#ibcon#read 4, iclass 4, count 2 2006.285.10:33:27.42#ibcon#about to read 5, iclass 4, count 2 2006.285.10:33:27.42#ibcon#read 5, iclass 4, count 2 2006.285.10:33:27.42#ibcon#about to read 6, iclass 4, count 2 2006.285.10:33:27.42#ibcon#read 6, iclass 4, count 2 2006.285.10:33:27.42#ibcon#end of sib2, iclass 4, count 2 2006.285.10:33:27.42#ibcon#*after write, iclass 4, count 2 2006.285.10:33:27.42#ibcon#*before return 0, iclass 4, count 2 2006.285.10:33:27.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:33:27.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:33:27.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.10:33:27.42#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:27.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:33:27.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:33:27.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:33:27.54#ibcon#enter wrdev, iclass 4, count 0 2006.285.10:33:27.54#ibcon#first serial, iclass 4, count 0 2006.285.10:33:27.54#ibcon#enter sib2, iclass 4, count 0 2006.285.10:33:27.54#ibcon#flushed, iclass 4, count 0 2006.285.10:33:27.54#ibcon#about to write, iclass 4, count 0 2006.285.10:33:27.54#ibcon#wrote, iclass 4, count 0 2006.285.10:33:27.54#ibcon#about to read 3, iclass 4, count 0 2006.285.10:33:27.56#ibcon#read 3, iclass 4, count 0 2006.285.10:33:27.56#ibcon#about to read 4, iclass 4, count 0 2006.285.10:33:27.56#ibcon#read 4, iclass 4, count 0 2006.285.10:33:27.56#ibcon#about to read 5, iclass 4, count 0 2006.285.10:33:27.56#ibcon#read 5, iclass 4, count 0 2006.285.10:33:27.56#ibcon#about to read 6, iclass 4, count 0 2006.285.10:33:27.56#ibcon#read 6, iclass 4, count 0 2006.285.10:33:27.56#ibcon#end of sib2, iclass 4, count 0 2006.285.10:33:27.56#ibcon#*mode == 0, iclass 4, count 0 2006.285.10:33:27.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.10:33:27.56#ibcon#[27=USB\r\n] 2006.285.10:33:27.56#ibcon#*before write, iclass 4, count 0 2006.285.10:33:27.56#ibcon#enter sib2, iclass 4, count 0 2006.285.10:33:27.56#ibcon#flushed, iclass 4, count 0 2006.285.10:33:27.56#ibcon#about to write, iclass 4, count 0 2006.285.10:33:27.56#ibcon#wrote, iclass 4, count 0 2006.285.10:33:27.56#ibcon#about to read 3, iclass 4, count 0 2006.285.10:33:27.59#ibcon#read 3, iclass 4, count 0 2006.285.10:33:27.59#ibcon#about to read 4, iclass 4, count 0 2006.285.10:33:27.59#ibcon#read 4, iclass 4, count 0 2006.285.10:33:27.59#ibcon#about to read 5, iclass 4, count 0 2006.285.10:33:27.59#ibcon#read 5, iclass 4, count 0 2006.285.10:33:27.59#ibcon#about to read 6, iclass 4, count 0 2006.285.10:33:27.59#ibcon#read 6, iclass 4, count 0 2006.285.10:33:27.59#ibcon#end of sib2, iclass 4, count 0 2006.285.10:33:27.59#ibcon#*after write, iclass 4, count 0 2006.285.10:33:27.59#ibcon#*before return 0, iclass 4, count 0 2006.285.10:33:27.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:33:27.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:33:27.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.10:33:27.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.10:33:27.59$vck44/vblo=3,649.99 2006.285.10:33:27.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.10:33:27.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.10:33:27.59#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:27.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:33:27.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:33:27.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:33:27.59#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:33:27.59#ibcon#first serial, iclass 6, count 0 2006.285.10:33:27.59#ibcon#enter sib2, iclass 6, count 0 2006.285.10:33:27.59#ibcon#flushed, iclass 6, count 0 2006.285.10:33:27.59#ibcon#about to write, iclass 6, count 0 2006.285.10:33:27.59#ibcon#wrote, iclass 6, count 0 2006.285.10:33:27.59#ibcon#about to read 3, iclass 6, count 0 2006.285.10:33:27.61#ibcon#read 3, iclass 6, count 0 2006.285.10:33:27.61#ibcon#about to read 4, iclass 6, count 0 2006.285.10:33:27.61#ibcon#read 4, iclass 6, count 0 2006.285.10:33:27.61#ibcon#about to read 5, iclass 6, count 0 2006.285.10:33:27.61#ibcon#read 5, iclass 6, count 0 2006.285.10:33:27.61#ibcon#about to read 6, iclass 6, count 0 2006.285.10:33:27.61#ibcon#read 6, iclass 6, count 0 2006.285.10:33:27.61#ibcon#end of sib2, iclass 6, count 0 2006.285.10:33:27.61#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:33:27.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:33:27.61#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:33:27.61#ibcon#*before write, iclass 6, count 0 2006.285.10:33:27.61#ibcon#enter sib2, iclass 6, count 0 2006.285.10:33:27.61#ibcon#flushed, iclass 6, count 0 2006.285.10:33:27.61#ibcon#about to write, iclass 6, count 0 2006.285.10:33:27.61#ibcon#wrote, iclass 6, count 0 2006.285.10:33:27.61#ibcon#about to read 3, iclass 6, count 0 2006.285.10:33:27.65#ibcon#read 3, iclass 6, count 0 2006.285.10:33:27.65#ibcon#about to read 4, iclass 6, count 0 2006.285.10:33:27.65#ibcon#read 4, iclass 6, count 0 2006.285.10:33:27.65#ibcon#about to read 5, iclass 6, count 0 2006.285.10:33:27.65#ibcon#read 5, iclass 6, count 0 2006.285.10:33:27.65#ibcon#about to read 6, iclass 6, count 0 2006.285.10:33:27.65#ibcon#read 6, iclass 6, count 0 2006.285.10:33:27.65#ibcon#end of sib2, iclass 6, count 0 2006.285.10:33:27.65#ibcon#*after write, iclass 6, count 0 2006.285.10:33:27.65#ibcon#*before return 0, iclass 6, count 0 2006.285.10:33:27.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:33:27.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:33:27.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:33:27.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:33:27.65$vck44/vb=3,4 2006.285.10:33:27.65#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.10:33:27.65#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.10:33:27.65#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:27.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:33:27.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:33:27.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:33:27.71#ibcon#enter wrdev, iclass 10, count 2 2006.285.10:33:27.71#ibcon#first serial, iclass 10, count 2 2006.285.10:33:27.71#ibcon#enter sib2, iclass 10, count 2 2006.285.10:33:27.71#ibcon#flushed, iclass 10, count 2 2006.285.10:33:27.71#ibcon#about to write, iclass 10, count 2 2006.285.10:33:27.71#ibcon#wrote, iclass 10, count 2 2006.285.10:33:27.71#ibcon#about to read 3, iclass 10, count 2 2006.285.10:33:27.73#ibcon#read 3, iclass 10, count 2 2006.285.10:33:27.73#ibcon#about to read 4, iclass 10, count 2 2006.285.10:33:27.73#ibcon#read 4, iclass 10, count 2 2006.285.10:33:27.73#ibcon#about to read 5, iclass 10, count 2 2006.285.10:33:27.73#ibcon#read 5, iclass 10, count 2 2006.285.10:33:27.73#ibcon#about to read 6, iclass 10, count 2 2006.285.10:33:27.73#ibcon#read 6, iclass 10, count 2 2006.285.10:33:27.73#ibcon#end of sib2, iclass 10, count 2 2006.285.10:33:27.73#ibcon#*mode == 0, iclass 10, count 2 2006.285.10:33:27.73#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.10:33:27.73#ibcon#[27=AT03-04\r\n] 2006.285.10:33:27.73#ibcon#*before write, iclass 10, count 2 2006.285.10:33:27.73#ibcon#enter sib2, iclass 10, count 2 2006.285.10:33:27.73#ibcon#flushed, iclass 10, count 2 2006.285.10:33:27.73#ibcon#about to write, iclass 10, count 2 2006.285.10:33:27.73#ibcon#wrote, iclass 10, count 2 2006.285.10:33:27.73#ibcon#about to read 3, iclass 10, count 2 2006.285.10:33:27.76#ibcon#read 3, iclass 10, count 2 2006.285.10:33:27.76#ibcon#about to read 4, iclass 10, count 2 2006.285.10:33:27.76#ibcon#read 4, iclass 10, count 2 2006.285.10:33:27.76#ibcon#about to read 5, iclass 10, count 2 2006.285.10:33:27.76#ibcon#read 5, iclass 10, count 2 2006.285.10:33:27.76#ibcon#about to read 6, iclass 10, count 2 2006.285.10:33:27.76#ibcon#read 6, iclass 10, count 2 2006.285.10:33:27.76#ibcon#end of sib2, iclass 10, count 2 2006.285.10:33:27.76#ibcon#*after write, iclass 10, count 2 2006.285.10:33:27.76#ibcon#*before return 0, iclass 10, count 2 2006.285.10:33:27.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:33:27.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:33:27.76#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.10:33:27.76#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:27.76#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:33:27.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:33:27.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:33:27.88#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:33:27.88#ibcon#first serial, iclass 10, count 0 2006.285.10:33:27.88#ibcon#enter sib2, iclass 10, count 0 2006.285.10:33:27.88#ibcon#flushed, iclass 10, count 0 2006.285.10:33:27.88#ibcon#about to write, iclass 10, count 0 2006.285.10:33:27.88#ibcon#wrote, iclass 10, count 0 2006.285.10:33:27.88#ibcon#about to read 3, iclass 10, count 0 2006.285.10:33:27.90#ibcon#read 3, iclass 10, count 0 2006.285.10:33:27.90#ibcon#about to read 4, iclass 10, count 0 2006.285.10:33:27.90#ibcon#read 4, iclass 10, count 0 2006.285.10:33:27.90#ibcon#about to read 5, iclass 10, count 0 2006.285.10:33:27.90#ibcon#read 5, iclass 10, count 0 2006.285.10:33:27.90#ibcon#about to read 6, iclass 10, count 0 2006.285.10:33:27.90#ibcon#read 6, iclass 10, count 0 2006.285.10:33:27.90#ibcon#end of sib2, iclass 10, count 0 2006.285.10:33:27.90#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:33:27.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:33:27.90#ibcon#[27=USB\r\n] 2006.285.10:33:27.90#ibcon#*before write, iclass 10, count 0 2006.285.10:33:27.90#ibcon#enter sib2, iclass 10, count 0 2006.285.10:33:27.90#ibcon#flushed, iclass 10, count 0 2006.285.10:33:27.90#ibcon#about to write, iclass 10, count 0 2006.285.10:33:27.90#ibcon#wrote, iclass 10, count 0 2006.285.10:33:27.90#ibcon#about to read 3, iclass 10, count 0 2006.285.10:33:27.93#ibcon#read 3, iclass 10, count 0 2006.285.10:33:27.93#ibcon#about to read 4, iclass 10, count 0 2006.285.10:33:27.93#ibcon#read 4, iclass 10, count 0 2006.285.10:33:27.93#ibcon#about to read 5, iclass 10, count 0 2006.285.10:33:27.93#ibcon#read 5, iclass 10, count 0 2006.285.10:33:27.93#ibcon#about to read 6, iclass 10, count 0 2006.285.10:33:27.93#ibcon#read 6, iclass 10, count 0 2006.285.10:33:27.93#ibcon#end of sib2, iclass 10, count 0 2006.285.10:33:27.93#ibcon#*after write, iclass 10, count 0 2006.285.10:33:27.93#ibcon#*before return 0, iclass 10, count 0 2006.285.10:33:27.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:33:27.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:33:27.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:33:27.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:33:27.93$vck44/vblo=4,679.99 2006.285.10:33:27.93#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.10:33:27.93#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.10:33:27.93#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:27.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:33:27.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:33:27.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:33:27.93#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:33:27.93#ibcon#first serial, iclass 12, count 0 2006.285.10:33:27.93#ibcon#enter sib2, iclass 12, count 0 2006.285.10:33:27.93#ibcon#flushed, iclass 12, count 0 2006.285.10:33:27.93#ibcon#about to write, iclass 12, count 0 2006.285.10:33:27.93#ibcon#wrote, iclass 12, count 0 2006.285.10:33:27.93#ibcon#about to read 3, iclass 12, count 0 2006.285.10:33:27.95#ibcon#read 3, iclass 12, count 0 2006.285.10:33:27.95#ibcon#about to read 4, iclass 12, count 0 2006.285.10:33:27.95#ibcon#read 4, iclass 12, count 0 2006.285.10:33:27.95#ibcon#about to read 5, iclass 12, count 0 2006.285.10:33:27.95#ibcon#read 5, iclass 12, count 0 2006.285.10:33:27.95#ibcon#about to read 6, iclass 12, count 0 2006.285.10:33:27.95#ibcon#read 6, iclass 12, count 0 2006.285.10:33:27.95#ibcon#end of sib2, iclass 12, count 0 2006.285.10:33:27.95#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:33:27.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:33:27.95#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:33:27.95#ibcon#*before write, iclass 12, count 0 2006.285.10:33:27.95#ibcon#enter sib2, iclass 12, count 0 2006.285.10:33:27.95#ibcon#flushed, iclass 12, count 0 2006.285.10:33:27.95#ibcon#about to write, iclass 12, count 0 2006.285.10:33:27.95#ibcon#wrote, iclass 12, count 0 2006.285.10:33:27.95#ibcon#about to read 3, iclass 12, count 0 2006.285.10:33:27.99#ibcon#read 3, iclass 12, count 0 2006.285.10:33:27.99#ibcon#about to read 4, iclass 12, count 0 2006.285.10:33:27.99#ibcon#read 4, iclass 12, count 0 2006.285.10:33:27.99#ibcon#about to read 5, iclass 12, count 0 2006.285.10:33:27.99#ibcon#read 5, iclass 12, count 0 2006.285.10:33:27.99#ibcon#about to read 6, iclass 12, count 0 2006.285.10:33:27.99#ibcon#read 6, iclass 12, count 0 2006.285.10:33:27.99#ibcon#end of sib2, iclass 12, count 0 2006.285.10:33:27.99#ibcon#*after write, iclass 12, count 0 2006.285.10:33:27.99#ibcon#*before return 0, iclass 12, count 0 2006.285.10:33:27.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:33:27.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:33:27.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:33:27.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:33:27.99$vck44/vb=4,5 2006.285.10:33:27.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.10:33:27.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.10:33:27.99#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:27.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:33:28.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:33:28.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:33:28.05#ibcon#enter wrdev, iclass 14, count 2 2006.285.10:33:28.05#ibcon#first serial, iclass 14, count 2 2006.285.10:33:28.05#ibcon#enter sib2, iclass 14, count 2 2006.285.10:33:28.05#ibcon#flushed, iclass 14, count 2 2006.285.10:33:28.05#ibcon#about to write, iclass 14, count 2 2006.285.10:33:28.05#ibcon#wrote, iclass 14, count 2 2006.285.10:33:28.05#ibcon#about to read 3, iclass 14, count 2 2006.285.10:33:28.07#ibcon#read 3, iclass 14, count 2 2006.285.10:33:28.07#ibcon#about to read 4, iclass 14, count 2 2006.285.10:33:28.07#ibcon#read 4, iclass 14, count 2 2006.285.10:33:28.07#ibcon#about to read 5, iclass 14, count 2 2006.285.10:33:28.07#ibcon#read 5, iclass 14, count 2 2006.285.10:33:28.07#ibcon#about to read 6, iclass 14, count 2 2006.285.10:33:28.07#ibcon#read 6, iclass 14, count 2 2006.285.10:33:28.07#ibcon#end of sib2, iclass 14, count 2 2006.285.10:33:28.07#ibcon#*mode == 0, iclass 14, count 2 2006.285.10:33:28.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.10:33:28.07#ibcon#[27=AT04-05\r\n] 2006.285.10:33:28.07#ibcon#*before write, iclass 14, count 2 2006.285.10:33:28.07#ibcon#enter sib2, iclass 14, count 2 2006.285.10:33:28.07#ibcon#flushed, iclass 14, count 2 2006.285.10:33:28.07#ibcon#about to write, iclass 14, count 2 2006.285.10:33:28.07#ibcon#wrote, iclass 14, count 2 2006.285.10:33:28.07#ibcon#about to read 3, iclass 14, count 2 2006.285.10:33:28.10#ibcon#read 3, iclass 14, count 2 2006.285.10:33:28.10#ibcon#about to read 4, iclass 14, count 2 2006.285.10:33:28.10#ibcon#read 4, iclass 14, count 2 2006.285.10:33:28.10#ibcon#about to read 5, iclass 14, count 2 2006.285.10:33:28.10#ibcon#read 5, iclass 14, count 2 2006.285.10:33:28.10#ibcon#about to read 6, iclass 14, count 2 2006.285.10:33:28.10#ibcon#read 6, iclass 14, count 2 2006.285.10:33:28.10#ibcon#end of sib2, iclass 14, count 2 2006.285.10:33:28.10#ibcon#*after write, iclass 14, count 2 2006.285.10:33:28.10#ibcon#*before return 0, iclass 14, count 2 2006.285.10:33:28.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:33:28.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:33:28.10#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.10:33:28.10#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:28.10#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:33:28.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:33:28.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:33:28.22#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:33:28.22#ibcon#first serial, iclass 14, count 0 2006.285.10:33:28.22#ibcon#enter sib2, iclass 14, count 0 2006.285.10:33:28.22#ibcon#flushed, iclass 14, count 0 2006.285.10:33:28.22#ibcon#about to write, iclass 14, count 0 2006.285.10:33:28.22#ibcon#wrote, iclass 14, count 0 2006.285.10:33:28.22#ibcon#about to read 3, iclass 14, count 0 2006.285.10:33:28.24#ibcon#read 3, iclass 14, count 0 2006.285.10:33:28.24#ibcon#about to read 4, iclass 14, count 0 2006.285.10:33:28.24#ibcon#read 4, iclass 14, count 0 2006.285.10:33:28.24#ibcon#about to read 5, iclass 14, count 0 2006.285.10:33:28.24#ibcon#read 5, iclass 14, count 0 2006.285.10:33:28.24#ibcon#about to read 6, iclass 14, count 0 2006.285.10:33:28.24#ibcon#read 6, iclass 14, count 0 2006.285.10:33:28.24#ibcon#end of sib2, iclass 14, count 0 2006.285.10:33:28.24#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:33:28.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:33:28.24#ibcon#[27=USB\r\n] 2006.285.10:33:28.24#ibcon#*before write, iclass 14, count 0 2006.285.10:33:28.24#ibcon#enter sib2, iclass 14, count 0 2006.285.10:33:28.24#ibcon#flushed, iclass 14, count 0 2006.285.10:33:28.24#ibcon#about to write, iclass 14, count 0 2006.285.10:33:28.24#ibcon#wrote, iclass 14, count 0 2006.285.10:33:28.24#ibcon#about to read 3, iclass 14, count 0 2006.285.10:33:28.27#ibcon#read 3, iclass 14, count 0 2006.285.10:33:28.27#ibcon#about to read 4, iclass 14, count 0 2006.285.10:33:28.27#ibcon#read 4, iclass 14, count 0 2006.285.10:33:28.27#ibcon#about to read 5, iclass 14, count 0 2006.285.10:33:28.27#ibcon#read 5, iclass 14, count 0 2006.285.10:33:28.27#ibcon#about to read 6, iclass 14, count 0 2006.285.10:33:28.27#ibcon#read 6, iclass 14, count 0 2006.285.10:33:28.27#ibcon#end of sib2, iclass 14, count 0 2006.285.10:33:28.27#ibcon#*after write, iclass 14, count 0 2006.285.10:33:28.27#ibcon#*before return 0, iclass 14, count 0 2006.285.10:33:28.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:33:28.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:33:28.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:33:28.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:33:28.27$vck44/vblo=5,709.99 2006.285.10:33:28.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.10:33:28.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.10:33:28.27#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:28.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:33:28.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:33:28.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:33:28.27#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:33:28.27#ibcon#first serial, iclass 16, count 0 2006.285.10:33:28.27#ibcon#enter sib2, iclass 16, count 0 2006.285.10:33:28.27#ibcon#flushed, iclass 16, count 0 2006.285.10:33:28.27#ibcon#about to write, iclass 16, count 0 2006.285.10:33:28.27#ibcon#wrote, iclass 16, count 0 2006.285.10:33:28.27#ibcon#about to read 3, iclass 16, count 0 2006.285.10:33:28.29#ibcon#read 3, iclass 16, count 0 2006.285.10:33:28.29#ibcon#about to read 4, iclass 16, count 0 2006.285.10:33:28.29#ibcon#read 4, iclass 16, count 0 2006.285.10:33:28.29#ibcon#about to read 5, iclass 16, count 0 2006.285.10:33:28.29#ibcon#read 5, iclass 16, count 0 2006.285.10:33:28.29#ibcon#about to read 6, iclass 16, count 0 2006.285.10:33:28.29#ibcon#read 6, iclass 16, count 0 2006.285.10:33:28.29#ibcon#end of sib2, iclass 16, count 0 2006.285.10:33:28.29#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:33:28.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:33:28.29#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:33:28.29#ibcon#*before write, iclass 16, count 0 2006.285.10:33:28.29#ibcon#enter sib2, iclass 16, count 0 2006.285.10:33:28.29#ibcon#flushed, iclass 16, count 0 2006.285.10:33:28.29#ibcon#about to write, iclass 16, count 0 2006.285.10:33:28.29#ibcon#wrote, iclass 16, count 0 2006.285.10:33:28.29#ibcon#about to read 3, iclass 16, count 0 2006.285.10:33:28.33#ibcon#read 3, iclass 16, count 0 2006.285.10:33:28.33#ibcon#about to read 4, iclass 16, count 0 2006.285.10:33:28.33#ibcon#read 4, iclass 16, count 0 2006.285.10:33:28.33#ibcon#about to read 5, iclass 16, count 0 2006.285.10:33:28.33#ibcon#read 5, iclass 16, count 0 2006.285.10:33:28.33#ibcon#about to read 6, iclass 16, count 0 2006.285.10:33:28.33#ibcon#read 6, iclass 16, count 0 2006.285.10:33:28.33#ibcon#end of sib2, iclass 16, count 0 2006.285.10:33:28.33#ibcon#*after write, iclass 16, count 0 2006.285.10:33:28.33#ibcon#*before return 0, iclass 16, count 0 2006.285.10:33:28.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:33:28.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:33:28.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:33:28.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:33:28.33$vck44/vb=5,4 2006.285.10:33:28.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.10:33:28.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.10:33:28.33#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:28.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:33:28.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:33:28.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:33:28.39#ibcon#enter wrdev, iclass 18, count 2 2006.285.10:33:28.39#ibcon#first serial, iclass 18, count 2 2006.285.10:33:28.39#ibcon#enter sib2, iclass 18, count 2 2006.285.10:33:28.39#ibcon#flushed, iclass 18, count 2 2006.285.10:33:28.39#ibcon#about to write, iclass 18, count 2 2006.285.10:33:28.39#ibcon#wrote, iclass 18, count 2 2006.285.10:33:28.39#ibcon#about to read 3, iclass 18, count 2 2006.285.10:33:28.41#ibcon#read 3, iclass 18, count 2 2006.285.10:33:28.41#ibcon#about to read 4, iclass 18, count 2 2006.285.10:33:28.41#ibcon#read 4, iclass 18, count 2 2006.285.10:33:28.41#ibcon#about to read 5, iclass 18, count 2 2006.285.10:33:28.41#ibcon#read 5, iclass 18, count 2 2006.285.10:33:28.41#ibcon#about to read 6, iclass 18, count 2 2006.285.10:33:28.41#ibcon#read 6, iclass 18, count 2 2006.285.10:33:28.41#ibcon#end of sib2, iclass 18, count 2 2006.285.10:33:28.41#ibcon#*mode == 0, iclass 18, count 2 2006.285.10:33:28.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.10:33:28.41#ibcon#[27=AT05-04\r\n] 2006.285.10:33:28.41#ibcon#*before write, iclass 18, count 2 2006.285.10:33:28.41#ibcon#enter sib2, iclass 18, count 2 2006.285.10:33:28.41#ibcon#flushed, iclass 18, count 2 2006.285.10:33:28.41#ibcon#about to write, iclass 18, count 2 2006.285.10:33:28.41#ibcon#wrote, iclass 18, count 2 2006.285.10:33:28.41#ibcon#about to read 3, iclass 18, count 2 2006.285.10:33:28.44#ibcon#read 3, iclass 18, count 2 2006.285.10:33:28.44#ibcon#about to read 4, iclass 18, count 2 2006.285.10:33:28.44#ibcon#read 4, iclass 18, count 2 2006.285.10:33:28.44#ibcon#about to read 5, iclass 18, count 2 2006.285.10:33:28.44#ibcon#read 5, iclass 18, count 2 2006.285.10:33:28.44#ibcon#about to read 6, iclass 18, count 2 2006.285.10:33:28.44#ibcon#read 6, iclass 18, count 2 2006.285.10:33:28.44#ibcon#end of sib2, iclass 18, count 2 2006.285.10:33:28.44#ibcon#*after write, iclass 18, count 2 2006.285.10:33:28.44#ibcon#*before return 0, iclass 18, count 2 2006.285.10:33:28.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:33:28.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:33:28.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.10:33:28.44#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:28.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:33:28.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:33:28.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:33:28.56#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:33:28.56#ibcon#first serial, iclass 18, count 0 2006.285.10:33:28.56#ibcon#enter sib2, iclass 18, count 0 2006.285.10:33:28.56#ibcon#flushed, iclass 18, count 0 2006.285.10:33:28.56#ibcon#about to write, iclass 18, count 0 2006.285.10:33:28.56#ibcon#wrote, iclass 18, count 0 2006.285.10:33:28.56#ibcon#about to read 3, iclass 18, count 0 2006.285.10:33:28.58#ibcon#read 3, iclass 18, count 0 2006.285.10:33:28.58#ibcon#about to read 4, iclass 18, count 0 2006.285.10:33:28.58#ibcon#read 4, iclass 18, count 0 2006.285.10:33:28.58#ibcon#about to read 5, iclass 18, count 0 2006.285.10:33:28.58#ibcon#read 5, iclass 18, count 0 2006.285.10:33:28.58#ibcon#about to read 6, iclass 18, count 0 2006.285.10:33:28.58#ibcon#read 6, iclass 18, count 0 2006.285.10:33:28.58#ibcon#end of sib2, iclass 18, count 0 2006.285.10:33:28.58#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:33:28.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:33:28.58#ibcon#[27=USB\r\n] 2006.285.10:33:28.58#ibcon#*before write, iclass 18, count 0 2006.285.10:33:28.58#ibcon#enter sib2, iclass 18, count 0 2006.285.10:33:28.58#ibcon#flushed, iclass 18, count 0 2006.285.10:33:28.58#ibcon#about to write, iclass 18, count 0 2006.285.10:33:28.58#ibcon#wrote, iclass 18, count 0 2006.285.10:33:28.58#ibcon#about to read 3, iclass 18, count 0 2006.285.10:33:28.61#ibcon#read 3, iclass 18, count 0 2006.285.10:33:28.61#ibcon#about to read 4, iclass 18, count 0 2006.285.10:33:28.61#ibcon#read 4, iclass 18, count 0 2006.285.10:33:28.61#ibcon#about to read 5, iclass 18, count 0 2006.285.10:33:28.61#ibcon#read 5, iclass 18, count 0 2006.285.10:33:28.61#ibcon#about to read 6, iclass 18, count 0 2006.285.10:33:28.61#ibcon#read 6, iclass 18, count 0 2006.285.10:33:28.61#ibcon#end of sib2, iclass 18, count 0 2006.285.10:33:28.61#ibcon#*after write, iclass 18, count 0 2006.285.10:33:28.61#ibcon#*before return 0, iclass 18, count 0 2006.285.10:33:28.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:33:28.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:33:28.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:33:28.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:33:28.61$vck44/vblo=6,719.99 2006.285.10:33:28.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.10:33:28.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.10:33:28.61#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:28.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:33:28.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:33:28.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:33:28.61#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:33:28.61#ibcon#first serial, iclass 20, count 0 2006.285.10:33:28.61#ibcon#enter sib2, iclass 20, count 0 2006.285.10:33:28.61#ibcon#flushed, iclass 20, count 0 2006.285.10:33:28.61#ibcon#about to write, iclass 20, count 0 2006.285.10:33:28.61#ibcon#wrote, iclass 20, count 0 2006.285.10:33:28.61#ibcon#about to read 3, iclass 20, count 0 2006.285.10:33:28.63#ibcon#read 3, iclass 20, count 0 2006.285.10:33:28.63#ibcon#about to read 4, iclass 20, count 0 2006.285.10:33:28.63#ibcon#read 4, iclass 20, count 0 2006.285.10:33:28.63#ibcon#about to read 5, iclass 20, count 0 2006.285.10:33:28.63#ibcon#read 5, iclass 20, count 0 2006.285.10:33:28.63#ibcon#about to read 6, iclass 20, count 0 2006.285.10:33:28.63#ibcon#read 6, iclass 20, count 0 2006.285.10:33:28.63#ibcon#end of sib2, iclass 20, count 0 2006.285.10:33:28.63#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:33:28.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:33:28.63#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:33:28.63#ibcon#*before write, iclass 20, count 0 2006.285.10:33:28.63#ibcon#enter sib2, iclass 20, count 0 2006.285.10:33:28.63#ibcon#flushed, iclass 20, count 0 2006.285.10:33:28.63#ibcon#about to write, iclass 20, count 0 2006.285.10:33:28.63#ibcon#wrote, iclass 20, count 0 2006.285.10:33:28.63#ibcon#about to read 3, iclass 20, count 0 2006.285.10:33:28.67#ibcon#read 3, iclass 20, count 0 2006.285.10:33:28.67#ibcon#about to read 4, iclass 20, count 0 2006.285.10:33:28.67#ibcon#read 4, iclass 20, count 0 2006.285.10:33:28.67#ibcon#about to read 5, iclass 20, count 0 2006.285.10:33:28.67#ibcon#read 5, iclass 20, count 0 2006.285.10:33:28.67#ibcon#about to read 6, iclass 20, count 0 2006.285.10:33:28.67#ibcon#read 6, iclass 20, count 0 2006.285.10:33:28.67#ibcon#end of sib2, iclass 20, count 0 2006.285.10:33:28.67#ibcon#*after write, iclass 20, count 0 2006.285.10:33:28.67#ibcon#*before return 0, iclass 20, count 0 2006.285.10:33:28.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:33:28.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:33:28.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:33:28.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:33:28.67$vck44/vb=6,3 2006.285.10:33:28.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.10:33:28.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.10:33:28.67#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:28.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:33:28.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:33:28.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:33:28.73#ibcon#enter wrdev, iclass 22, count 2 2006.285.10:33:28.73#ibcon#first serial, iclass 22, count 2 2006.285.10:33:28.73#ibcon#enter sib2, iclass 22, count 2 2006.285.10:33:28.73#ibcon#flushed, iclass 22, count 2 2006.285.10:33:28.73#ibcon#about to write, iclass 22, count 2 2006.285.10:33:28.73#ibcon#wrote, iclass 22, count 2 2006.285.10:33:28.73#ibcon#about to read 3, iclass 22, count 2 2006.285.10:33:28.75#ibcon#read 3, iclass 22, count 2 2006.285.10:33:28.75#ibcon#about to read 4, iclass 22, count 2 2006.285.10:33:28.75#ibcon#read 4, iclass 22, count 2 2006.285.10:33:28.75#ibcon#about to read 5, iclass 22, count 2 2006.285.10:33:28.75#ibcon#read 5, iclass 22, count 2 2006.285.10:33:28.75#ibcon#about to read 6, iclass 22, count 2 2006.285.10:33:28.75#ibcon#read 6, iclass 22, count 2 2006.285.10:33:28.75#ibcon#end of sib2, iclass 22, count 2 2006.285.10:33:28.75#ibcon#*mode == 0, iclass 22, count 2 2006.285.10:33:28.75#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.10:33:28.75#ibcon#[27=AT06-03\r\n] 2006.285.10:33:28.75#ibcon#*before write, iclass 22, count 2 2006.285.10:33:28.75#ibcon#enter sib2, iclass 22, count 2 2006.285.10:33:28.75#ibcon#flushed, iclass 22, count 2 2006.285.10:33:28.75#ibcon#about to write, iclass 22, count 2 2006.285.10:33:28.75#ibcon#wrote, iclass 22, count 2 2006.285.10:33:28.75#ibcon#about to read 3, iclass 22, count 2 2006.285.10:33:28.78#ibcon#read 3, iclass 22, count 2 2006.285.10:33:28.78#ibcon#about to read 4, iclass 22, count 2 2006.285.10:33:28.78#ibcon#read 4, iclass 22, count 2 2006.285.10:33:28.78#ibcon#about to read 5, iclass 22, count 2 2006.285.10:33:28.78#ibcon#read 5, iclass 22, count 2 2006.285.10:33:28.78#ibcon#about to read 6, iclass 22, count 2 2006.285.10:33:28.78#ibcon#read 6, iclass 22, count 2 2006.285.10:33:28.78#ibcon#end of sib2, iclass 22, count 2 2006.285.10:33:28.78#ibcon#*after write, iclass 22, count 2 2006.285.10:33:28.78#ibcon#*before return 0, iclass 22, count 2 2006.285.10:33:28.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:33:28.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:33:28.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.10:33:28.78#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:28.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:33:28.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:33:28.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:33:28.90#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:33:28.90#ibcon#first serial, iclass 22, count 0 2006.285.10:33:28.90#ibcon#enter sib2, iclass 22, count 0 2006.285.10:33:28.90#ibcon#flushed, iclass 22, count 0 2006.285.10:33:28.90#ibcon#about to write, iclass 22, count 0 2006.285.10:33:28.90#ibcon#wrote, iclass 22, count 0 2006.285.10:33:28.90#ibcon#about to read 3, iclass 22, count 0 2006.285.10:33:28.92#ibcon#read 3, iclass 22, count 0 2006.285.10:33:28.92#ibcon#about to read 4, iclass 22, count 0 2006.285.10:33:28.92#ibcon#read 4, iclass 22, count 0 2006.285.10:33:28.92#ibcon#about to read 5, iclass 22, count 0 2006.285.10:33:28.92#ibcon#read 5, iclass 22, count 0 2006.285.10:33:28.92#ibcon#about to read 6, iclass 22, count 0 2006.285.10:33:28.92#ibcon#read 6, iclass 22, count 0 2006.285.10:33:28.92#ibcon#end of sib2, iclass 22, count 0 2006.285.10:33:28.92#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:33:28.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:33:28.92#ibcon#[27=USB\r\n] 2006.285.10:33:28.92#ibcon#*before write, iclass 22, count 0 2006.285.10:33:28.92#ibcon#enter sib2, iclass 22, count 0 2006.285.10:33:28.92#ibcon#flushed, iclass 22, count 0 2006.285.10:33:28.92#ibcon#about to write, iclass 22, count 0 2006.285.10:33:28.92#ibcon#wrote, iclass 22, count 0 2006.285.10:33:28.92#ibcon#about to read 3, iclass 22, count 0 2006.285.10:33:28.95#ibcon#read 3, iclass 22, count 0 2006.285.10:33:28.95#ibcon#about to read 4, iclass 22, count 0 2006.285.10:33:28.95#ibcon#read 4, iclass 22, count 0 2006.285.10:33:28.95#ibcon#about to read 5, iclass 22, count 0 2006.285.10:33:28.95#ibcon#read 5, iclass 22, count 0 2006.285.10:33:28.95#ibcon#about to read 6, iclass 22, count 0 2006.285.10:33:28.95#ibcon#read 6, iclass 22, count 0 2006.285.10:33:28.95#ibcon#end of sib2, iclass 22, count 0 2006.285.10:33:28.95#ibcon#*after write, iclass 22, count 0 2006.285.10:33:28.95#ibcon#*before return 0, iclass 22, count 0 2006.285.10:33:28.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:33:28.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:33:28.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:33:28.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:33:28.95$vck44/vblo=7,734.99 2006.285.10:33:28.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.10:33:28.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.10:33:28.95#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:28.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:33:28.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:33:28.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:33:28.95#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:33:28.95#ibcon#first serial, iclass 24, count 0 2006.285.10:33:28.95#ibcon#enter sib2, iclass 24, count 0 2006.285.10:33:28.95#ibcon#flushed, iclass 24, count 0 2006.285.10:33:28.95#ibcon#about to write, iclass 24, count 0 2006.285.10:33:28.95#ibcon#wrote, iclass 24, count 0 2006.285.10:33:28.95#ibcon#about to read 3, iclass 24, count 0 2006.285.10:33:28.97#ibcon#read 3, iclass 24, count 0 2006.285.10:33:28.97#ibcon#about to read 4, iclass 24, count 0 2006.285.10:33:28.97#ibcon#read 4, iclass 24, count 0 2006.285.10:33:28.97#ibcon#about to read 5, iclass 24, count 0 2006.285.10:33:28.97#ibcon#read 5, iclass 24, count 0 2006.285.10:33:28.97#ibcon#about to read 6, iclass 24, count 0 2006.285.10:33:28.97#ibcon#read 6, iclass 24, count 0 2006.285.10:33:28.97#ibcon#end of sib2, iclass 24, count 0 2006.285.10:33:28.97#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:33:28.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:33:28.97#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:33:28.97#ibcon#*before write, iclass 24, count 0 2006.285.10:33:28.97#ibcon#enter sib2, iclass 24, count 0 2006.285.10:33:28.97#ibcon#flushed, iclass 24, count 0 2006.285.10:33:28.97#ibcon#about to write, iclass 24, count 0 2006.285.10:33:28.97#ibcon#wrote, iclass 24, count 0 2006.285.10:33:28.97#ibcon#about to read 3, iclass 24, count 0 2006.285.10:33:29.01#ibcon#read 3, iclass 24, count 0 2006.285.10:33:29.01#ibcon#about to read 4, iclass 24, count 0 2006.285.10:33:29.01#ibcon#read 4, iclass 24, count 0 2006.285.10:33:29.01#ibcon#about to read 5, iclass 24, count 0 2006.285.10:33:29.01#ibcon#read 5, iclass 24, count 0 2006.285.10:33:29.01#ibcon#about to read 6, iclass 24, count 0 2006.285.10:33:29.01#ibcon#read 6, iclass 24, count 0 2006.285.10:33:29.01#ibcon#end of sib2, iclass 24, count 0 2006.285.10:33:29.01#ibcon#*after write, iclass 24, count 0 2006.285.10:33:29.01#ibcon#*before return 0, iclass 24, count 0 2006.285.10:33:29.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:33:29.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:33:29.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:33:29.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:33:29.01$vck44/vb=7,4 2006.285.10:33:29.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.10:33:29.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.10:33:29.01#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:29.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:33:29.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:33:29.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:33:29.07#ibcon#enter wrdev, iclass 26, count 2 2006.285.10:33:29.07#ibcon#first serial, iclass 26, count 2 2006.285.10:33:29.07#ibcon#enter sib2, iclass 26, count 2 2006.285.10:33:29.07#ibcon#flushed, iclass 26, count 2 2006.285.10:33:29.07#ibcon#about to write, iclass 26, count 2 2006.285.10:33:29.07#ibcon#wrote, iclass 26, count 2 2006.285.10:33:29.07#ibcon#about to read 3, iclass 26, count 2 2006.285.10:33:29.09#ibcon#read 3, iclass 26, count 2 2006.285.10:33:29.09#ibcon#about to read 4, iclass 26, count 2 2006.285.10:33:29.09#ibcon#read 4, iclass 26, count 2 2006.285.10:33:29.09#ibcon#about to read 5, iclass 26, count 2 2006.285.10:33:29.09#ibcon#read 5, iclass 26, count 2 2006.285.10:33:29.09#ibcon#about to read 6, iclass 26, count 2 2006.285.10:33:29.09#ibcon#read 6, iclass 26, count 2 2006.285.10:33:29.09#ibcon#end of sib2, iclass 26, count 2 2006.285.10:33:29.09#ibcon#*mode == 0, iclass 26, count 2 2006.285.10:33:29.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.10:33:29.09#ibcon#[27=AT07-04\r\n] 2006.285.10:33:29.09#ibcon#*before write, iclass 26, count 2 2006.285.10:33:29.09#ibcon#enter sib2, iclass 26, count 2 2006.285.10:33:29.09#ibcon#flushed, iclass 26, count 2 2006.285.10:33:29.09#ibcon#about to write, iclass 26, count 2 2006.285.10:33:29.09#ibcon#wrote, iclass 26, count 2 2006.285.10:33:29.09#ibcon#about to read 3, iclass 26, count 2 2006.285.10:33:29.12#ibcon#read 3, iclass 26, count 2 2006.285.10:33:29.12#ibcon#about to read 4, iclass 26, count 2 2006.285.10:33:29.12#ibcon#read 4, iclass 26, count 2 2006.285.10:33:29.12#ibcon#about to read 5, iclass 26, count 2 2006.285.10:33:29.12#ibcon#read 5, iclass 26, count 2 2006.285.10:33:29.12#ibcon#about to read 6, iclass 26, count 2 2006.285.10:33:29.12#ibcon#read 6, iclass 26, count 2 2006.285.10:33:29.12#ibcon#end of sib2, iclass 26, count 2 2006.285.10:33:29.12#ibcon#*after write, iclass 26, count 2 2006.285.10:33:29.12#ibcon#*before return 0, iclass 26, count 2 2006.285.10:33:29.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:33:29.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:33:29.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.10:33:29.12#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:29.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:33:29.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:33:29.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:33:29.24#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:33:29.24#ibcon#first serial, iclass 26, count 0 2006.285.10:33:29.24#ibcon#enter sib2, iclass 26, count 0 2006.285.10:33:29.24#ibcon#flushed, iclass 26, count 0 2006.285.10:33:29.24#ibcon#about to write, iclass 26, count 0 2006.285.10:33:29.24#ibcon#wrote, iclass 26, count 0 2006.285.10:33:29.24#ibcon#about to read 3, iclass 26, count 0 2006.285.10:33:29.26#ibcon#read 3, iclass 26, count 0 2006.285.10:33:29.26#ibcon#about to read 4, iclass 26, count 0 2006.285.10:33:29.26#ibcon#read 4, iclass 26, count 0 2006.285.10:33:29.26#ibcon#about to read 5, iclass 26, count 0 2006.285.10:33:29.26#ibcon#read 5, iclass 26, count 0 2006.285.10:33:29.26#ibcon#about to read 6, iclass 26, count 0 2006.285.10:33:29.26#ibcon#read 6, iclass 26, count 0 2006.285.10:33:29.26#ibcon#end of sib2, iclass 26, count 0 2006.285.10:33:29.26#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:33:29.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:33:29.26#ibcon#[27=USB\r\n] 2006.285.10:33:29.26#ibcon#*before write, iclass 26, count 0 2006.285.10:33:29.26#ibcon#enter sib2, iclass 26, count 0 2006.285.10:33:29.26#ibcon#flushed, iclass 26, count 0 2006.285.10:33:29.26#ibcon#about to write, iclass 26, count 0 2006.285.10:33:29.26#ibcon#wrote, iclass 26, count 0 2006.285.10:33:29.26#ibcon#about to read 3, iclass 26, count 0 2006.285.10:33:29.29#ibcon#read 3, iclass 26, count 0 2006.285.10:33:29.29#ibcon#about to read 4, iclass 26, count 0 2006.285.10:33:29.29#ibcon#read 4, iclass 26, count 0 2006.285.10:33:29.29#ibcon#about to read 5, iclass 26, count 0 2006.285.10:33:29.29#ibcon#read 5, iclass 26, count 0 2006.285.10:33:29.29#ibcon#about to read 6, iclass 26, count 0 2006.285.10:33:29.29#ibcon#read 6, iclass 26, count 0 2006.285.10:33:29.29#ibcon#end of sib2, iclass 26, count 0 2006.285.10:33:29.29#ibcon#*after write, iclass 26, count 0 2006.285.10:33:29.29#ibcon#*before return 0, iclass 26, count 0 2006.285.10:33:29.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:33:29.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:33:29.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:33:29.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:33:29.29$vck44/vblo=8,744.99 2006.285.10:33:29.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.10:33:29.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.10:33:29.29#ibcon#ireg 17 cls_cnt 0 2006.285.10:33:29.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:33:29.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:33:29.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:33:29.29#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:33:29.29#ibcon#first serial, iclass 28, count 0 2006.285.10:33:29.29#ibcon#enter sib2, iclass 28, count 0 2006.285.10:33:29.29#ibcon#flushed, iclass 28, count 0 2006.285.10:33:29.29#ibcon#about to write, iclass 28, count 0 2006.285.10:33:29.29#ibcon#wrote, iclass 28, count 0 2006.285.10:33:29.29#ibcon#about to read 3, iclass 28, count 0 2006.285.10:33:29.31#ibcon#read 3, iclass 28, count 0 2006.285.10:33:29.31#ibcon#about to read 4, iclass 28, count 0 2006.285.10:33:29.31#ibcon#read 4, iclass 28, count 0 2006.285.10:33:29.31#ibcon#about to read 5, iclass 28, count 0 2006.285.10:33:29.31#ibcon#read 5, iclass 28, count 0 2006.285.10:33:29.31#ibcon#about to read 6, iclass 28, count 0 2006.285.10:33:29.31#ibcon#read 6, iclass 28, count 0 2006.285.10:33:29.31#ibcon#end of sib2, iclass 28, count 0 2006.285.10:33:29.31#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:33:29.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:33:29.31#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:33:29.31#ibcon#*before write, iclass 28, count 0 2006.285.10:33:29.31#ibcon#enter sib2, iclass 28, count 0 2006.285.10:33:29.31#ibcon#flushed, iclass 28, count 0 2006.285.10:33:29.31#ibcon#about to write, iclass 28, count 0 2006.285.10:33:29.31#ibcon#wrote, iclass 28, count 0 2006.285.10:33:29.31#ibcon#about to read 3, iclass 28, count 0 2006.285.10:33:29.35#ibcon#read 3, iclass 28, count 0 2006.285.10:33:29.35#ibcon#about to read 4, iclass 28, count 0 2006.285.10:33:29.35#ibcon#read 4, iclass 28, count 0 2006.285.10:33:29.35#ibcon#about to read 5, iclass 28, count 0 2006.285.10:33:29.35#ibcon#read 5, iclass 28, count 0 2006.285.10:33:29.35#ibcon#about to read 6, iclass 28, count 0 2006.285.10:33:29.35#ibcon#read 6, iclass 28, count 0 2006.285.10:33:29.35#ibcon#end of sib2, iclass 28, count 0 2006.285.10:33:29.35#ibcon#*after write, iclass 28, count 0 2006.285.10:33:29.35#ibcon#*before return 0, iclass 28, count 0 2006.285.10:33:29.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:33:29.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:33:29.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:33:29.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:33:29.35$vck44/vb=8,4 2006.285.10:33:29.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.10:33:29.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.10:33:29.35#ibcon#ireg 11 cls_cnt 2 2006.285.10:33:29.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:33:29.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:33:29.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:33:29.41#ibcon#enter wrdev, iclass 30, count 2 2006.285.10:33:29.41#ibcon#first serial, iclass 30, count 2 2006.285.10:33:29.41#ibcon#enter sib2, iclass 30, count 2 2006.285.10:33:29.41#ibcon#flushed, iclass 30, count 2 2006.285.10:33:29.41#ibcon#about to write, iclass 30, count 2 2006.285.10:33:29.41#ibcon#wrote, iclass 30, count 2 2006.285.10:33:29.41#ibcon#about to read 3, iclass 30, count 2 2006.285.10:33:29.43#ibcon#read 3, iclass 30, count 2 2006.285.10:33:29.43#ibcon#about to read 4, iclass 30, count 2 2006.285.10:33:29.43#ibcon#read 4, iclass 30, count 2 2006.285.10:33:29.43#ibcon#about to read 5, iclass 30, count 2 2006.285.10:33:29.43#ibcon#read 5, iclass 30, count 2 2006.285.10:33:29.43#ibcon#about to read 6, iclass 30, count 2 2006.285.10:33:29.43#ibcon#read 6, iclass 30, count 2 2006.285.10:33:29.43#ibcon#end of sib2, iclass 30, count 2 2006.285.10:33:29.43#ibcon#*mode == 0, iclass 30, count 2 2006.285.10:33:29.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.10:33:29.43#ibcon#[27=AT08-04\r\n] 2006.285.10:33:29.43#ibcon#*before write, iclass 30, count 2 2006.285.10:33:29.43#ibcon#enter sib2, iclass 30, count 2 2006.285.10:33:29.43#ibcon#flushed, iclass 30, count 2 2006.285.10:33:29.43#ibcon#about to write, iclass 30, count 2 2006.285.10:33:29.43#ibcon#wrote, iclass 30, count 2 2006.285.10:33:29.43#ibcon#about to read 3, iclass 30, count 2 2006.285.10:33:29.46#ibcon#read 3, iclass 30, count 2 2006.285.10:33:29.46#ibcon#about to read 4, iclass 30, count 2 2006.285.10:33:29.46#ibcon#read 4, iclass 30, count 2 2006.285.10:33:29.46#ibcon#about to read 5, iclass 30, count 2 2006.285.10:33:29.46#ibcon#read 5, iclass 30, count 2 2006.285.10:33:29.46#ibcon#about to read 6, iclass 30, count 2 2006.285.10:33:29.46#ibcon#read 6, iclass 30, count 2 2006.285.10:33:29.46#ibcon#end of sib2, iclass 30, count 2 2006.285.10:33:29.46#ibcon#*after write, iclass 30, count 2 2006.285.10:33:29.46#ibcon#*before return 0, iclass 30, count 2 2006.285.10:33:29.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:33:29.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:33:29.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.10:33:29.46#ibcon#ireg 7 cls_cnt 0 2006.285.10:33:29.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:33:29.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:33:29.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:33:29.58#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:33:29.58#ibcon#first serial, iclass 30, count 0 2006.285.10:33:29.58#ibcon#enter sib2, iclass 30, count 0 2006.285.10:33:29.58#ibcon#flushed, iclass 30, count 0 2006.285.10:33:29.58#ibcon#about to write, iclass 30, count 0 2006.285.10:33:29.58#ibcon#wrote, iclass 30, count 0 2006.285.10:33:29.58#ibcon#about to read 3, iclass 30, count 0 2006.285.10:33:29.60#ibcon#read 3, iclass 30, count 0 2006.285.10:33:29.60#ibcon#about to read 4, iclass 30, count 0 2006.285.10:33:29.60#ibcon#read 4, iclass 30, count 0 2006.285.10:33:29.60#ibcon#about to read 5, iclass 30, count 0 2006.285.10:33:29.60#ibcon#read 5, iclass 30, count 0 2006.285.10:33:29.60#ibcon#about to read 6, iclass 30, count 0 2006.285.10:33:29.60#ibcon#read 6, iclass 30, count 0 2006.285.10:33:29.60#ibcon#end of sib2, iclass 30, count 0 2006.285.10:33:29.60#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:33:29.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:33:29.60#ibcon#[27=USB\r\n] 2006.285.10:33:29.60#ibcon#*before write, iclass 30, count 0 2006.285.10:33:29.60#ibcon#enter sib2, iclass 30, count 0 2006.285.10:33:29.60#ibcon#flushed, iclass 30, count 0 2006.285.10:33:29.60#ibcon#about to write, iclass 30, count 0 2006.285.10:33:29.60#ibcon#wrote, iclass 30, count 0 2006.285.10:33:29.60#ibcon#about to read 3, iclass 30, count 0 2006.285.10:33:29.63#ibcon#read 3, iclass 30, count 0 2006.285.10:33:29.63#ibcon#about to read 4, iclass 30, count 0 2006.285.10:33:29.63#ibcon#read 4, iclass 30, count 0 2006.285.10:33:29.63#ibcon#about to read 5, iclass 30, count 0 2006.285.10:33:29.63#ibcon#read 5, iclass 30, count 0 2006.285.10:33:29.63#ibcon#about to read 6, iclass 30, count 0 2006.285.10:33:29.63#ibcon#read 6, iclass 30, count 0 2006.285.10:33:29.63#ibcon#end of sib2, iclass 30, count 0 2006.285.10:33:29.63#ibcon#*after write, iclass 30, count 0 2006.285.10:33:29.63#ibcon#*before return 0, iclass 30, count 0 2006.285.10:33:29.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:33:29.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:33:29.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:33:29.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:33:29.63$vck44/vabw=wide 2006.285.10:33:29.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.10:33:29.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.10:33:29.63#ibcon#ireg 8 cls_cnt 0 2006.285.10:33:29.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:33:29.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:33:29.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:33:29.63#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:33:29.63#ibcon#first serial, iclass 32, count 0 2006.285.10:33:29.63#ibcon#enter sib2, iclass 32, count 0 2006.285.10:33:29.63#ibcon#flushed, iclass 32, count 0 2006.285.10:33:29.63#ibcon#about to write, iclass 32, count 0 2006.285.10:33:29.63#ibcon#wrote, iclass 32, count 0 2006.285.10:33:29.63#ibcon#about to read 3, iclass 32, count 0 2006.285.10:33:29.65#ibcon#read 3, iclass 32, count 0 2006.285.10:33:29.65#ibcon#about to read 4, iclass 32, count 0 2006.285.10:33:29.65#ibcon#read 4, iclass 32, count 0 2006.285.10:33:29.65#ibcon#about to read 5, iclass 32, count 0 2006.285.10:33:29.65#ibcon#read 5, iclass 32, count 0 2006.285.10:33:29.65#ibcon#about to read 6, iclass 32, count 0 2006.285.10:33:29.65#ibcon#read 6, iclass 32, count 0 2006.285.10:33:29.65#ibcon#end of sib2, iclass 32, count 0 2006.285.10:33:29.65#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:33:29.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:33:29.65#ibcon#[25=BW32\r\n] 2006.285.10:33:29.65#ibcon#*before write, iclass 32, count 0 2006.285.10:33:29.65#ibcon#enter sib2, iclass 32, count 0 2006.285.10:33:29.65#ibcon#flushed, iclass 32, count 0 2006.285.10:33:29.65#ibcon#about to write, iclass 32, count 0 2006.285.10:33:29.65#ibcon#wrote, iclass 32, count 0 2006.285.10:33:29.65#ibcon#about to read 3, iclass 32, count 0 2006.285.10:33:29.68#ibcon#read 3, iclass 32, count 0 2006.285.10:33:29.68#ibcon#about to read 4, iclass 32, count 0 2006.285.10:33:29.68#ibcon#read 4, iclass 32, count 0 2006.285.10:33:29.68#ibcon#about to read 5, iclass 32, count 0 2006.285.10:33:29.68#ibcon#read 5, iclass 32, count 0 2006.285.10:33:29.68#ibcon#about to read 6, iclass 32, count 0 2006.285.10:33:29.68#ibcon#read 6, iclass 32, count 0 2006.285.10:33:29.68#ibcon#end of sib2, iclass 32, count 0 2006.285.10:33:29.68#ibcon#*after write, iclass 32, count 0 2006.285.10:33:29.68#ibcon#*before return 0, iclass 32, count 0 2006.285.10:33:29.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:33:29.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:33:29.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:33:29.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:33:29.68$vck44/vbbw=wide 2006.285.10:33:29.68#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.10:33:29.68#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.10:33:29.68#ibcon#ireg 8 cls_cnt 0 2006.285.10:33:29.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:33:29.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:33:29.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:33:29.75#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:33:29.75#ibcon#first serial, iclass 34, count 0 2006.285.10:33:29.75#ibcon#enter sib2, iclass 34, count 0 2006.285.10:33:29.75#ibcon#flushed, iclass 34, count 0 2006.285.10:33:29.75#ibcon#about to write, iclass 34, count 0 2006.285.10:33:29.75#ibcon#wrote, iclass 34, count 0 2006.285.10:33:29.75#ibcon#about to read 3, iclass 34, count 0 2006.285.10:33:29.77#ibcon#read 3, iclass 34, count 0 2006.285.10:33:29.77#ibcon#about to read 4, iclass 34, count 0 2006.285.10:33:29.77#ibcon#read 4, iclass 34, count 0 2006.285.10:33:29.77#ibcon#about to read 5, iclass 34, count 0 2006.285.10:33:29.77#ibcon#read 5, iclass 34, count 0 2006.285.10:33:29.77#ibcon#about to read 6, iclass 34, count 0 2006.285.10:33:29.77#ibcon#read 6, iclass 34, count 0 2006.285.10:33:29.77#ibcon#end of sib2, iclass 34, count 0 2006.285.10:33:29.77#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:33:29.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:33:29.77#ibcon#[27=BW32\r\n] 2006.285.10:33:29.77#ibcon#*before write, iclass 34, count 0 2006.285.10:33:29.77#ibcon#enter sib2, iclass 34, count 0 2006.285.10:33:29.77#ibcon#flushed, iclass 34, count 0 2006.285.10:33:29.77#ibcon#about to write, iclass 34, count 0 2006.285.10:33:29.77#ibcon#wrote, iclass 34, count 0 2006.285.10:33:29.77#ibcon#about to read 3, iclass 34, count 0 2006.285.10:33:29.80#ibcon#read 3, iclass 34, count 0 2006.285.10:33:29.80#ibcon#about to read 4, iclass 34, count 0 2006.285.10:33:29.80#ibcon#read 4, iclass 34, count 0 2006.285.10:33:29.80#ibcon#about to read 5, iclass 34, count 0 2006.285.10:33:29.80#ibcon#read 5, iclass 34, count 0 2006.285.10:33:29.80#ibcon#about to read 6, iclass 34, count 0 2006.285.10:33:29.80#ibcon#read 6, iclass 34, count 0 2006.285.10:33:29.80#ibcon#end of sib2, iclass 34, count 0 2006.285.10:33:29.80#ibcon#*after write, iclass 34, count 0 2006.285.10:33:29.80#ibcon#*before return 0, iclass 34, count 0 2006.285.10:33:29.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:33:29.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:33:29.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:33:29.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:33:29.80$setupk4/ifdk4 2006.285.10:33:29.80$ifdk4/lo= 2006.285.10:33:29.80$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:33:29.80$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:33:29.80$ifdk4/patch= 2006.285.10:33:29.80$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:33:29.80$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:33:29.80$setupk4/!*+20s 2006.285.10:33:32.15#abcon#<5=/04 1.3 2.2 19.75 911015.0\r\n> 2006.285.10:33:32.17#abcon#{5=INTERFACE CLEAR} 2006.285.10:33:32.23#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:33:39.14#trakl#Source acquired 2006.285.10:33:41.14#flagr#flagr/antenna,acquired 2006.285.10:33:42.32#abcon#<5=/04 1.3 2.2 19.75 911015.0\r\n> 2006.285.10:33:42.34#abcon#{5=INTERFACE CLEAR} 2006.285.10:33:42.40#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:33:44.30$setupk4/"tpicd 2006.285.10:33:44.30$setupk4/echo=off 2006.285.10:33:44.30$setupk4/xlog=off 2006.285.10:33:44.30:!2006.285.10:38:31 2006.285.10:38:31.01:preob 2006.285.10:38:32.13/onsource/TRACKING 2006.285.10:38:32.13:!2006.285.10:38:41 2006.285.10:38:41.01:"tape 2006.285.10:38:41.01:"st=record 2006.285.10:38:41.01:data_valid=on 2006.285.10:38:41.02:midob 2006.285.10:38:42.13/onsource/TRACKING 2006.285.10:38:42.14/wx/19.73,1015.0,91 2006.285.10:38:42.35/cable/+6.4855E-03 2006.285.10:38:43.44/va/01,07,usb,yes,32,34 2006.285.10:38:43.44/va/02,06,usb,yes,32,32 2006.285.10:38:43.44/va/03,07,usb,yes,31,33 2006.285.10:38:43.44/va/04,06,usb,yes,33,34 2006.285.10:38:43.44/va/05,03,usb,yes,32,33 2006.285.10:38:43.44/va/06,04,usb,yes,29,29 2006.285.10:38:43.44/va/07,04,usb,yes,30,30 2006.285.10:38:43.44/va/08,03,usb,yes,30,37 2006.285.10:38:43.67/valo/01,524.99,yes,locked 2006.285.10:38:43.67/valo/02,534.99,yes,locked 2006.285.10:38:43.67/valo/03,564.99,yes,locked 2006.285.10:38:43.67/valo/04,624.99,yes,locked 2006.285.10:38:43.67/valo/05,734.99,yes,locked 2006.285.10:38:43.67/valo/06,814.99,yes,locked 2006.285.10:38:43.67/valo/07,864.99,yes,locked 2006.285.10:38:43.67/valo/08,884.99,yes,locked 2006.285.10:38:44.76/vb/01,04,usb,yes,30,28 2006.285.10:38:44.76/vb/02,05,usb,yes,29,29 2006.285.10:38:44.76/vb/03,04,usb,yes,30,33 2006.285.10:38:44.76/vb/04,05,usb,yes,30,29 2006.285.10:38:44.76/vb/05,04,usb,yes,26,29 2006.285.10:38:44.76/vb/06,03,usb,yes,38,33 2006.285.10:38:44.76/vb/07,04,usb,yes,30,30 2006.285.10:38:44.76/vb/08,04,usb,yes,28,31 2006.285.10:38:44.99/vblo/01,629.99,yes,locked 2006.285.10:38:44.99/vblo/02,634.99,yes,locked 2006.285.10:38:44.99/vblo/03,649.99,yes,locked 2006.285.10:38:44.99/vblo/04,679.99,yes,locked 2006.285.10:38:44.99/vblo/05,709.99,yes,locked 2006.285.10:38:44.99/vblo/06,719.99,yes,locked 2006.285.10:38:44.99/vblo/07,734.99,yes,locked 2006.285.10:38:44.99/vblo/08,744.99,yes,locked 2006.285.10:38:45.14/vabw/8 2006.285.10:38:45.29/vbbw/8 2006.285.10:38:45.38/xfe/off,on,12.0 2006.285.10:38:45.76/ifatt/23,28,28,28 2006.285.10:38:46.07/fmout-gps/S +2.62E-07 2006.285.10:38:46.09:!2006.285.10:41:21 2006.285.10:41:21.00:data_valid=off 2006.285.10:41:21.00:"et 2006.285.10:41:21.00:!+3s 2006.285.10:41:24.01:"tape 2006.285.10:41:24.01:postob 2006.285.10:41:24.15/cable/+6.4863E-03 2006.285.10:41:24.15/wx/19.70,1015.0,92 2006.285.10:41:25.07/fmout-gps/S +2.68E-07 2006.285.10:41:25.07:scan_name=285-1043,jd0610,70 2006.285.10:41:25.07:source=2136+141,213901.31,142336.0,2000.0,cw 2006.285.10:41:25.14#flagr#flagr/antenna,new-source 2006.285.10:41:26.14:checkk5 2006.285.10:41:27.04/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:41:27.46/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:41:27.91/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:41:28.29/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:41:28.92/chk_obsdata//k5ts1/T2851038??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.10:41:29.29/chk_obsdata//k5ts2/T2851038??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.10:41:29.74/chk_obsdata//k5ts3/T2851038??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.10:41:30.62/chk_obsdata//k5ts4/T2851038??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.10:41:31.34/k5log//k5ts1_log_newline 2006.285.10:41:32.46/k5log//k5ts2_log_newline 2006.285.10:41:33.26/k5log//k5ts3_log_newline 2006.285.10:41:34.07/k5log//k5ts4_log_newline 2006.285.10:41:34.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:41:34.09:setupk4=1 2006.285.10:41:34.09$setupk4/echo=on 2006.285.10:41:34.09$setupk4/pcalon 2006.285.10:41:34.09$pcalon/"no phase cal control is implemented here 2006.285.10:41:34.09$setupk4/"tpicd=stop 2006.285.10:41:34.09$setupk4/"rec=synch_on 2006.285.10:41:34.09$setupk4/"rec_mode=128 2006.285.10:41:34.09$setupk4/!* 2006.285.10:41:34.09$setupk4/recpk4 2006.285.10:41:34.09$recpk4/recpatch= 2006.285.10:41:34.09$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:41:34.09$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:41:34.09$setupk4/vck44 2006.285.10:41:34.09$vck44/valo=1,524.99 2006.285.10:41:34.09#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.10:41:34.10#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.10:41:34.10#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:34.10#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:41:34.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:41:34.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:41:34.10#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:41:34.10#ibcon#first serial, iclass 15, count 0 2006.285.10:41:34.10#ibcon#enter sib2, iclass 15, count 0 2006.285.10:41:34.10#ibcon#flushed, iclass 15, count 0 2006.285.10:41:34.10#ibcon#about to write, iclass 15, count 0 2006.285.10:41:34.10#ibcon#wrote, iclass 15, count 0 2006.285.10:41:34.10#ibcon#about to read 3, iclass 15, count 0 2006.285.10:41:34.11#ibcon#read 3, iclass 15, count 0 2006.285.10:41:34.11#ibcon#about to read 4, iclass 15, count 0 2006.285.10:41:34.11#ibcon#read 4, iclass 15, count 0 2006.285.10:41:34.11#ibcon#about to read 5, iclass 15, count 0 2006.285.10:41:34.11#ibcon#read 5, iclass 15, count 0 2006.285.10:41:34.11#ibcon#about to read 6, iclass 15, count 0 2006.285.10:41:34.11#ibcon#read 6, iclass 15, count 0 2006.285.10:41:34.11#ibcon#end of sib2, iclass 15, count 0 2006.285.10:41:34.11#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:41:34.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:41:34.11#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:41:34.11#ibcon#*before write, iclass 15, count 0 2006.285.10:41:34.11#ibcon#enter sib2, iclass 15, count 0 2006.285.10:41:34.11#ibcon#flushed, iclass 15, count 0 2006.285.10:41:34.11#ibcon#about to write, iclass 15, count 0 2006.285.10:41:34.11#ibcon#wrote, iclass 15, count 0 2006.285.10:41:34.11#ibcon#about to read 3, iclass 15, count 0 2006.285.10:41:34.16#ibcon#read 3, iclass 15, count 0 2006.285.10:41:34.16#ibcon#about to read 4, iclass 15, count 0 2006.285.10:41:34.16#ibcon#read 4, iclass 15, count 0 2006.285.10:41:34.16#ibcon#about to read 5, iclass 15, count 0 2006.285.10:41:34.16#ibcon#read 5, iclass 15, count 0 2006.285.10:41:34.16#ibcon#about to read 6, iclass 15, count 0 2006.285.10:41:34.16#ibcon#read 6, iclass 15, count 0 2006.285.10:41:34.16#ibcon#end of sib2, iclass 15, count 0 2006.285.10:41:34.16#ibcon#*after write, iclass 15, count 0 2006.285.10:41:34.16#ibcon#*before return 0, iclass 15, count 0 2006.285.10:41:34.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:41:34.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:41:34.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:41:34.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:41:34.17$vck44/va=1,7 2006.285.10:41:34.17#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.10:41:34.17#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.10:41:34.17#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:34.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:41:34.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:41:34.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:41:34.17#ibcon#enter wrdev, iclass 17, count 2 2006.285.10:41:34.17#ibcon#first serial, iclass 17, count 2 2006.285.10:41:34.17#ibcon#enter sib2, iclass 17, count 2 2006.285.10:41:34.17#ibcon#flushed, iclass 17, count 2 2006.285.10:41:34.17#ibcon#about to write, iclass 17, count 2 2006.285.10:41:34.17#ibcon#wrote, iclass 17, count 2 2006.285.10:41:34.17#ibcon#about to read 3, iclass 17, count 2 2006.285.10:41:34.18#ibcon#read 3, iclass 17, count 2 2006.285.10:41:34.18#ibcon#about to read 4, iclass 17, count 2 2006.285.10:41:34.18#ibcon#read 4, iclass 17, count 2 2006.285.10:41:34.18#ibcon#about to read 5, iclass 17, count 2 2006.285.10:41:34.18#ibcon#read 5, iclass 17, count 2 2006.285.10:41:34.18#ibcon#about to read 6, iclass 17, count 2 2006.285.10:41:34.18#ibcon#read 6, iclass 17, count 2 2006.285.10:41:34.18#ibcon#end of sib2, iclass 17, count 2 2006.285.10:41:34.18#ibcon#*mode == 0, iclass 17, count 2 2006.285.10:41:34.18#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.10:41:34.18#ibcon#[25=AT01-07\r\n] 2006.285.10:41:34.18#ibcon#*before write, iclass 17, count 2 2006.285.10:41:34.18#ibcon#enter sib2, iclass 17, count 2 2006.285.10:41:34.18#ibcon#flushed, iclass 17, count 2 2006.285.10:41:34.18#ibcon#about to write, iclass 17, count 2 2006.285.10:41:34.18#ibcon#wrote, iclass 17, count 2 2006.285.10:41:34.18#ibcon#about to read 3, iclass 17, count 2 2006.285.10:41:34.21#ibcon#read 3, iclass 17, count 2 2006.285.10:41:34.21#ibcon#about to read 4, iclass 17, count 2 2006.285.10:41:34.21#ibcon#read 4, iclass 17, count 2 2006.285.10:41:34.21#ibcon#about to read 5, iclass 17, count 2 2006.285.10:41:34.21#ibcon#read 5, iclass 17, count 2 2006.285.10:41:34.21#ibcon#about to read 6, iclass 17, count 2 2006.285.10:41:34.21#ibcon#read 6, iclass 17, count 2 2006.285.10:41:34.21#ibcon#end of sib2, iclass 17, count 2 2006.285.10:41:34.21#ibcon#*after write, iclass 17, count 2 2006.285.10:41:34.21#ibcon#*before return 0, iclass 17, count 2 2006.285.10:41:34.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:41:34.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:41:34.21#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.10:41:34.21#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:34.21#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:41:34.33#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:41:34.33#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:41:34.33#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:41:34.33#ibcon#first serial, iclass 17, count 0 2006.285.10:41:34.33#ibcon#enter sib2, iclass 17, count 0 2006.285.10:41:34.33#ibcon#flushed, iclass 17, count 0 2006.285.10:41:34.33#ibcon#about to write, iclass 17, count 0 2006.285.10:41:34.33#ibcon#wrote, iclass 17, count 0 2006.285.10:41:34.33#ibcon#about to read 3, iclass 17, count 0 2006.285.10:41:34.35#ibcon#read 3, iclass 17, count 0 2006.285.10:41:34.35#ibcon#about to read 4, iclass 17, count 0 2006.285.10:41:34.35#ibcon#read 4, iclass 17, count 0 2006.285.10:41:34.35#ibcon#about to read 5, iclass 17, count 0 2006.285.10:41:34.35#ibcon#read 5, iclass 17, count 0 2006.285.10:41:34.35#ibcon#about to read 6, iclass 17, count 0 2006.285.10:41:34.35#ibcon#read 6, iclass 17, count 0 2006.285.10:41:34.35#ibcon#end of sib2, iclass 17, count 0 2006.285.10:41:34.35#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:41:34.35#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:41:34.35#ibcon#[25=USB\r\n] 2006.285.10:41:34.35#ibcon#*before write, iclass 17, count 0 2006.285.10:41:34.35#ibcon#enter sib2, iclass 17, count 0 2006.285.10:41:34.35#ibcon#flushed, iclass 17, count 0 2006.285.10:41:34.35#ibcon#about to write, iclass 17, count 0 2006.285.10:41:34.35#ibcon#wrote, iclass 17, count 0 2006.285.10:41:34.35#ibcon#about to read 3, iclass 17, count 0 2006.285.10:41:34.38#ibcon#read 3, iclass 17, count 0 2006.285.10:41:34.38#ibcon#about to read 4, iclass 17, count 0 2006.285.10:41:34.38#ibcon#read 4, iclass 17, count 0 2006.285.10:41:34.38#ibcon#about to read 5, iclass 17, count 0 2006.285.10:41:34.38#ibcon#read 5, iclass 17, count 0 2006.285.10:41:34.38#ibcon#about to read 6, iclass 17, count 0 2006.285.10:41:34.38#ibcon#read 6, iclass 17, count 0 2006.285.10:41:34.38#ibcon#end of sib2, iclass 17, count 0 2006.285.10:41:34.38#ibcon#*after write, iclass 17, count 0 2006.285.10:41:34.38#ibcon#*before return 0, iclass 17, count 0 2006.285.10:41:34.38#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:41:34.38#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:41:34.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:41:34.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:41:34.39$vck44/valo=2,534.99 2006.285.10:41:34.39#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.10:41:34.39#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.10:41:34.39#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:34.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:41:34.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:41:34.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:41:34.39#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:41:34.39#ibcon#first serial, iclass 19, count 0 2006.285.10:41:34.39#ibcon#enter sib2, iclass 19, count 0 2006.285.10:41:34.39#ibcon#flushed, iclass 19, count 0 2006.285.10:41:34.39#ibcon#about to write, iclass 19, count 0 2006.285.10:41:34.39#ibcon#wrote, iclass 19, count 0 2006.285.10:41:34.39#ibcon#about to read 3, iclass 19, count 0 2006.285.10:41:34.40#ibcon#read 3, iclass 19, count 0 2006.285.10:41:34.40#ibcon#about to read 4, iclass 19, count 0 2006.285.10:41:34.40#ibcon#read 4, iclass 19, count 0 2006.285.10:41:34.40#ibcon#about to read 5, iclass 19, count 0 2006.285.10:41:34.40#ibcon#read 5, iclass 19, count 0 2006.285.10:41:34.40#ibcon#about to read 6, iclass 19, count 0 2006.285.10:41:34.40#ibcon#read 6, iclass 19, count 0 2006.285.10:41:34.40#ibcon#end of sib2, iclass 19, count 0 2006.285.10:41:34.40#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:41:34.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:41:34.40#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:41:34.40#ibcon#*before write, iclass 19, count 0 2006.285.10:41:34.40#ibcon#enter sib2, iclass 19, count 0 2006.285.10:41:34.40#ibcon#flushed, iclass 19, count 0 2006.285.10:41:34.40#ibcon#about to write, iclass 19, count 0 2006.285.10:41:34.40#ibcon#wrote, iclass 19, count 0 2006.285.10:41:34.40#ibcon#about to read 3, iclass 19, count 0 2006.285.10:41:34.44#ibcon#read 3, iclass 19, count 0 2006.285.10:41:34.44#ibcon#about to read 4, iclass 19, count 0 2006.285.10:41:34.44#ibcon#read 4, iclass 19, count 0 2006.285.10:41:34.44#ibcon#about to read 5, iclass 19, count 0 2006.285.10:41:34.44#ibcon#read 5, iclass 19, count 0 2006.285.10:41:34.44#ibcon#about to read 6, iclass 19, count 0 2006.285.10:41:34.44#ibcon#read 6, iclass 19, count 0 2006.285.10:41:34.44#ibcon#end of sib2, iclass 19, count 0 2006.285.10:41:34.44#ibcon#*after write, iclass 19, count 0 2006.285.10:41:34.44#ibcon#*before return 0, iclass 19, count 0 2006.285.10:41:34.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:41:34.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:41:34.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:41:34.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:41:34.45$vck44/va=2,6 2006.285.10:41:34.45#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.10:41:34.45#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.10:41:34.45#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:34.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:41:34.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:41:34.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:41:34.49#ibcon#enter wrdev, iclass 21, count 2 2006.285.10:41:34.49#ibcon#first serial, iclass 21, count 2 2006.285.10:41:34.49#ibcon#enter sib2, iclass 21, count 2 2006.285.10:41:34.49#ibcon#flushed, iclass 21, count 2 2006.285.10:41:34.49#ibcon#about to write, iclass 21, count 2 2006.285.10:41:34.49#ibcon#wrote, iclass 21, count 2 2006.285.10:41:34.49#ibcon#about to read 3, iclass 21, count 2 2006.285.10:41:34.51#ibcon#read 3, iclass 21, count 2 2006.285.10:41:34.51#ibcon#about to read 4, iclass 21, count 2 2006.285.10:41:34.51#ibcon#read 4, iclass 21, count 2 2006.285.10:41:34.51#ibcon#about to read 5, iclass 21, count 2 2006.285.10:41:34.51#ibcon#read 5, iclass 21, count 2 2006.285.10:41:34.51#ibcon#about to read 6, iclass 21, count 2 2006.285.10:41:34.51#ibcon#read 6, iclass 21, count 2 2006.285.10:41:34.51#ibcon#end of sib2, iclass 21, count 2 2006.285.10:41:34.51#ibcon#*mode == 0, iclass 21, count 2 2006.285.10:41:34.51#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.10:41:34.51#ibcon#[25=AT02-06\r\n] 2006.285.10:41:34.51#ibcon#*before write, iclass 21, count 2 2006.285.10:41:34.51#ibcon#enter sib2, iclass 21, count 2 2006.285.10:41:34.51#ibcon#flushed, iclass 21, count 2 2006.285.10:41:34.51#ibcon#about to write, iclass 21, count 2 2006.285.10:41:34.51#ibcon#wrote, iclass 21, count 2 2006.285.10:41:34.51#ibcon#about to read 3, iclass 21, count 2 2006.285.10:41:34.54#ibcon#read 3, iclass 21, count 2 2006.285.10:41:34.54#ibcon#about to read 4, iclass 21, count 2 2006.285.10:41:34.54#ibcon#read 4, iclass 21, count 2 2006.285.10:41:34.54#ibcon#about to read 5, iclass 21, count 2 2006.285.10:41:34.54#ibcon#read 5, iclass 21, count 2 2006.285.10:41:34.54#ibcon#about to read 6, iclass 21, count 2 2006.285.10:41:34.54#ibcon#read 6, iclass 21, count 2 2006.285.10:41:34.54#ibcon#end of sib2, iclass 21, count 2 2006.285.10:41:34.54#ibcon#*after write, iclass 21, count 2 2006.285.10:41:34.54#ibcon#*before return 0, iclass 21, count 2 2006.285.10:41:34.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:41:34.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:41:34.54#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.10:41:34.54#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:34.54#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:41:34.66#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:41:34.66#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:41:34.66#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:41:34.66#ibcon#first serial, iclass 21, count 0 2006.285.10:41:34.66#ibcon#enter sib2, iclass 21, count 0 2006.285.10:41:34.66#ibcon#flushed, iclass 21, count 0 2006.285.10:41:34.66#ibcon#about to write, iclass 21, count 0 2006.285.10:41:34.66#ibcon#wrote, iclass 21, count 0 2006.285.10:41:34.66#ibcon#about to read 3, iclass 21, count 0 2006.285.10:41:34.68#ibcon#read 3, iclass 21, count 0 2006.285.10:41:34.68#ibcon#about to read 4, iclass 21, count 0 2006.285.10:41:34.68#ibcon#read 4, iclass 21, count 0 2006.285.10:41:34.68#ibcon#about to read 5, iclass 21, count 0 2006.285.10:41:34.68#ibcon#read 5, iclass 21, count 0 2006.285.10:41:34.68#ibcon#about to read 6, iclass 21, count 0 2006.285.10:41:34.68#ibcon#read 6, iclass 21, count 0 2006.285.10:41:34.68#ibcon#end of sib2, iclass 21, count 0 2006.285.10:41:34.68#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:41:34.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:41:34.68#ibcon#[25=USB\r\n] 2006.285.10:41:34.68#ibcon#*before write, iclass 21, count 0 2006.285.10:41:34.68#ibcon#enter sib2, iclass 21, count 0 2006.285.10:41:34.68#ibcon#flushed, iclass 21, count 0 2006.285.10:41:34.68#ibcon#about to write, iclass 21, count 0 2006.285.10:41:34.68#ibcon#wrote, iclass 21, count 0 2006.285.10:41:34.68#ibcon#about to read 3, iclass 21, count 0 2006.285.10:41:34.71#ibcon#read 3, iclass 21, count 0 2006.285.10:41:34.71#ibcon#about to read 4, iclass 21, count 0 2006.285.10:41:34.71#ibcon#read 4, iclass 21, count 0 2006.285.10:41:34.71#ibcon#about to read 5, iclass 21, count 0 2006.285.10:41:34.71#ibcon#read 5, iclass 21, count 0 2006.285.10:41:34.71#ibcon#about to read 6, iclass 21, count 0 2006.285.10:41:34.71#ibcon#read 6, iclass 21, count 0 2006.285.10:41:34.71#ibcon#end of sib2, iclass 21, count 0 2006.285.10:41:34.71#ibcon#*after write, iclass 21, count 0 2006.285.10:41:34.71#ibcon#*before return 0, iclass 21, count 0 2006.285.10:41:34.71#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:41:34.71#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:41:34.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:41:34.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:41:34.71$vck44/valo=3,564.99 2006.285.10:41:34.71#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.10:41:34.71#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.10:41:34.71#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:34.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:41:34.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:41:34.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:41:34.72#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:41:34.72#ibcon#first serial, iclass 23, count 0 2006.285.10:41:34.72#ibcon#enter sib2, iclass 23, count 0 2006.285.10:41:34.72#ibcon#flushed, iclass 23, count 0 2006.285.10:41:34.72#ibcon#about to write, iclass 23, count 0 2006.285.10:41:34.72#ibcon#wrote, iclass 23, count 0 2006.285.10:41:34.72#ibcon#about to read 3, iclass 23, count 0 2006.285.10:41:34.73#ibcon#read 3, iclass 23, count 0 2006.285.10:41:34.73#ibcon#about to read 4, iclass 23, count 0 2006.285.10:41:34.73#ibcon#read 4, iclass 23, count 0 2006.285.10:41:34.73#ibcon#about to read 5, iclass 23, count 0 2006.285.10:41:34.73#ibcon#read 5, iclass 23, count 0 2006.285.10:41:34.73#ibcon#about to read 6, iclass 23, count 0 2006.285.10:41:34.73#ibcon#read 6, iclass 23, count 0 2006.285.10:41:34.73#ibcon#end of sib2, iclass 23, count 0 2006.285.10:41:34.73#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:41:34.73#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:41:34.73#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:41:34.73#ibcon#*before write, iclass 23, count 0 2006.285.10:41:34.73#ibcon#enter sib2, iclass 23, count 0 2006.285.10:41:34.73#ibcon#flushed, iclass 23, count 0 2006.285.10:41:34.73#ibcon#about to write, iclass 23, count 0 2006.285.10:41:34.73#ibcon#wrote, iclass 23, count 0 2006.285.10:41:34.73#ibcon#about to read 3, iclass 23, count 0 2006.285.10:41:34.77#ibcon#read 3, iclass 23, count 0 2006.285.10:41:34.77#ibcon#about to read 4, iclass 23, count 0 2006.285.10:41:34.77#ibcon#read 4, iclass 23, count 0 2006.285.10:41:34.77#ibcon#about to read 5, iclass 23, count 0 2006.285.10:41:34.77#ibcon#read 5, iclass 23, count 0 2006.285.10:41:34.77#ibcon#about to read 6, iclass 23, count 0 2006.285.10:41:34.77#ibcon#read 6, iclass 23, count 0 2006.285.10:41:34.77#ibcon#end of sib2, iclass 23, count 0 2006.285.10:41:34.77#ibcon#*after write, iclass 23, count 0 2006.285.10:41:34.77#ibcon#*before return 0, iclass 23, count 0 2006.285.10:41:34.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:41:34.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:41:34.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:41:34.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:41:34.77$vck44/va=3,7 2006.285.10:41:34.77#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.10:41:34.77#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.10:41:34.77#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:34.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:41:34.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:41:34.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:41:34.83#ibcon#enter wrdev, iclass 25, count 2 2006.285.10:41:34.83#ibcon#first serial, iclass 25, count 2 2006.285.10:41:34.83#ibcon#enter sib2, iclass 25, count 2 2006.285.10:41:34.83#ibcon#flushed, iclass 25, count 2 2006.285.10:41:34.83#ibcon#about to write, iclass 25, count 2 2006.285.10:41:34.83#ibcon#wrote, iclass 25, count 2 2006.285.10:41:34.83#ibcon#about to read 3, iclass 25, count 2 2006.285.10:41:34.85#ibcon#read 3, iclass 25, count 2 2006.285.10:41:34.85#ibcon#about to read 4, iclass 25, count 2 2006.285.10:41:34.85#ibcon#read 4, iclass 25, count 2 2006.285.10:41:34.85#ibcon#about to read 5, iclass 25, count 2 2006.285.10:41:34.85#ibcon#read 5, iclass 25, count 2 2006.285.10:41:34.85#ibcon#about to read 6, iclass 25, count 2 2006.285.10:41:34.85#ibcon#read 6, iclass 25, count 2 2006.285.10:41:34.85#ibcon#end of sib2, iclass 25, count 2 2006.285.10:41:34.85#ibcon#*mode == 0, iclass 25, count 2 2006.285.10:41:34.85#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.10:41:34.85#ibcon#[25=AT03-07\r\n] 2006.285.10:41:34.85#ibcon#*before write, iclass 25, count 2 2006.285.10:41:34.85#ibcon#enter sib2, iclass 25, count 2 2006.285.10:41:34.85#ibcon#flushed, iclass 25, count 2 2006.285.10:41:34.85#ibcon#about to write, iclass 25, count 2 2006.285.10:41:34.85#ibcon#wrote, iclass 25, count 2 2006.285.10:41:34.85#ibcon#about to read 3, iclass 25, count 2 2006.285.10:41:34.88#ibcon#read 3, iclass 25, count 2 2006.285.10:41:34.88#ibcon#about to read 4, iclass 25, count 2 2006.285.10:41:34.88#ibcon#read 4, iclass 25, count 2 2006.285.10:41:34.88#ibcon#about to read 5, iclass 25, count 2 2006.285.10:41:34.88#ibcon#read 5, iclass 25, count 2 2006.285.10:41:34.88#ibcon#about to read 6, iclass 25, count 2 2006.285.10:41:34.88#ibcon#read 6, iclass 25, count 2 2006.285.10:41:34.88#ibcon#end of sib2, iclass 25, count 2 2006.285.10:41:34.88#ibcon#*after write, iclass 25, count 2 2006.285.10:41:34.88#ibcon#*before return 0, iclass 25, count 2 2006.285.10:41:34.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:41:34.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:41:34.88#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.10:41:34.88#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:34.88#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:41:35.00#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:41:35.00#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:41:35.00#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:41:35.00#ibcon#first serial, iclass 25, count 0 2006.285.10:41:35.00#ibcon#enter sib2, iclass 25, count 0 2006.285.10:41:35.00#ibcon#flushed, iclass 25, count 0 2006.285.10:41:35.00#ibcon#about to write, iclass 25, count 0 2006.285.10:41:35.00#ibcon#wrote, iclass 25, count 0 2006.285.10:41:35.00#ibcon#about to read 3, iclass 25, count 0 2006.285.10:41:35.02#ibcon#read 3, iclass 25, count 0 2006.285.10:41:35.02#ibcon#about to read 4, iclass 25, count 0 2006.285.10:41:35.02#ibcon#read 4, iclass 25, count 0 2006.285.10:41:35.02#ibcon#about to read 5, iclass 25, count 0 2006.285.10:41:35.02#ibcon#read 5, iclass 25, count 0 2006.285.10:41:35.02#ibcon#about to read 6, iclass 25, count 0 2006.285.10:41:35.02#ibcon#read 6, iclass 25, count 0 2006.285.10:41:35.02#ibcon#end of sib2, iclass 25, count 0 2006.285.10:41:35.02#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:41:35.02#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:41:35.02#ibcon#[25=USB\r\n] 2006.285.10:41:35.02#ibcon#*before write, iclass 25, count 0 2006.285.10:41:35.02#ibcon#enter sib2, iclass 25, count 0 2006.285.10:41:35.02#ibcon#flushed, iclass 25, count 0 2006.285.10:41:35.02#ibcon#about to write, iclass 25, count 0 2006.285.10:41:35.02#ibcon#wrote, iclass 25, count 0 2006.285.10:41:35.02#ibcon#about to read 3, iclass 25, count 0 2006.285.10:41:35.05#ibcon#read 3, iclass 25, count 0 2006.285.10:41:35.05#ibcon#about to read 4, iclass 25, count 0 2006.285.10:41:35.05#ibcon#read 4, iclass 25, count 0 2006.285.10:41:35.05#ibcon#about to read 5, iclass 25, count 0 2006.285.10:41:35.05#ibcon#read 5, iclass 25, count 0 2006.285.10:41:35.05#ibcon#about to read 6, iclass 25, count 0 2006.285.10:41:35.05#ibcon#read 6, iclass 25, count 0 2006.285.10:41:35.05#ibcon#end of sib2, iclass 25, count 0 2006.285.10:41:35.05#ibcon#*after write, iclass 25, count 0 2006.285.10:41:35.05#ibcon#*before return 0, iclass 25, count 0 2006.285.10:41:35.05#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:41:35.05#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:41:35.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:41:35.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:41:35.05$vck44/valo=4,624.99 2006.285.10:41:35.05#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.10:41:35.05#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.10:41:35.05#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:35.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:41:35.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:41:35.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:41:35.05#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:41:35.05#ibcon#first serial, iclass 27, count 0 2006.285.10:41:35.05#ibcon#enter sib2, iclass 27, count 0 2006.285.10:41:35.05#ibcon#flushed, iclass 27, count 0 2006.285.10:41:35.05#ibcon#about to write, iclass 27, count 0 2006.285.10:41:35.05#ibcon#wrote, iclass 27, count 0 2006.285.10:41:35.05#ibcon#about to read 3, iclass 27, count 0 2006.285.10:41:35.07#ibcon#read 3, iclass 27, count 0 2006.285.10:41:35.07#ibcon#about to read 4, iclass 27, count 0 2006.285.10:41:35.07#ibcon#read 4, iclass 27, count 0 2006.285.10:41:35.07#ibcon#about to read 5, iclass 27, count 0 2006.285.10:41:35.07#ibcon#read 5, iclass 27, count 0 2006.285.10:41:35.07#ibcon#about to read 6, iclass 27, count 0 2006.285.10:41:35.07#ibcon#read 6, iclass 27, count 0 2006.285.10:41:35.07#ibcon#end of sib2, iclass 27, count 0 2006.285.10:41:35.07#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:41:35.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:41:35.07#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:41:35.07#ibcon#*before write, iclass 27, count 0 2006.285.10:41:35.07#ibcon#enter sib2, iclass 27, count 0 2006.285.10:41:35.07#ibcon#flushed, iclass 27, count 0 2006.285.10:41:35.07#ibcon#about to write, iclass 27, count 0 2006.285.10:41:35.07#ibcon#wrote, iclass 27, count 0 2006.285.10:41:35.07#ibcon#about to read 3, iclass 27, count 0 2006.285.10:41:35.11#ibcon#read 3, iclass 27, count 0 2006.285.10:41:35.11#ibcon#about to read 4, iclass 27, count 0 2006.285.10:41:35.11#ibcon#read 4, iclass 27, count 0 2006.285.10:41:35.11#ibcon#about to read 5, iclass 27, count 0 2006.285.10:41:35.11#ibcon#read 5, iclass 27, count 0 2006.285.10:41:35.11#ibcon#about to read 6, iclass 27, count 0 2006.285.10:41:35.11#ibcon#read 6, iclass 27, count 0 2006.285.10:41:35.11#ibcon#end of sib2, iclass 27, count 0 2006.285.10:41:35.11#ibcon#*after write, iclass 27, count 0 2006.285.10:41:35.11#ibcon#*before return 0, iclass 27, count 0 2006.285.10:41:35.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:41:35.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:41:35.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:41:35.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:41:35.11$vck44/va=4,6 2006.285.10:41:35.11#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.10:41:35.11#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.10:41:35.11#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:35.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:41:35.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:41:35.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:41:35.17#ibcon#enter wrdev, iclass 29, count 2 2006.285.10:41:35.17#ibcon#first serial, iclass 29, count 2 2006.285.10:41:35.17#ibcon#enter sib2, iclass 29, count 2 2006.285.10:41:35.17#ibcon#flushed, iclass 29, count 2 2006.285.10:41:35.17#ibcon#about to write, iclass 29, count 2 2006.285.10:41:35.17#ibcon#wrote, iclass 29, count 2 2006.285.10:41:35.17#ibcon#about to read 3, iclass 29, count 2 2006.285.10:41:35.19#ibcon#read 3, iclass 29, count 2 2006.285.10:41:35.19#ibcon#about to read 4, iclass 29, count 2 2006.285.10:41:35.19#ibcon#read 4, iclass 29, count 2 2006.285.10:41:35.19#ibcon#about to read 5, iclass 29, count 2 2006.285.10:41:35.19#ibcon#read 5, iclass 29, count 2 2006.285.10:41:35.19#ibcon#about to read 6, iclass 29, count 2 2006.285.10:41:35.19#ibcon#read 6, iclass 29, count 2 2006.285.10:41:35.19#ibcon#end of sib2, iclass 29, count 2 2006.285.10:41:35.19#ibcon#*mode == 0, iclass 29, count 2 2006.285.10:41:35.19#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.10:41:35.19#ibcon#[25=AT04-06\r\n] 2006.285.10:41:35.19#ibcon#*before write, iclass 29, count 2 2006.285.10:41:35.19#ibcon#enter sib2, iclass 29, count 2 2006.285.10:41:35.19#ibcon#flushed, iclass 29, count 2 2006.285.10:41:35.19#ibcon#about to write, iclass 29, count 2 2006.285.10:41:35.19#ibcon#wrote, iclass 29, count 2 2006.285.10:41:35.19#ibcon#about to read 3, iclass 29, count 2 2006.285.10:41:35.22#ibcon#read 3, iclass 29, count 2 2006.285.10:41:35.22#ibcon#about to read 4, iclass 29, count 2 2006.285.10:41:35.22#ibcon#read 4, iclass 29, count 2 2006.285.10:41:35.22#ibcon#about to read 5, iclass 29, count 2 2006.285.10:41:35.22#ibcon#read 5, iclass 29, count 2 2006.285.10:41:35.22#ibcon#about to read 6, iclass 29, count 2 2006.285.10:41:35.22#ibcon#read 6, iclass 29, count 2 2006.285.10:41:35.22#ibcon#end of sib2, iclass 29, count 2 2006.285.10:41:35.22#ibcon#*after write, iclass 29, count 2 2006.285.10:41:35.22#ibcon#*before return 0, iclass 29, count 2 2006.285.10:41:35.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:41:35.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:41:35.22#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.10:41:35.22#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:35.22#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:41:35.34#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:41:35.34#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:41:35.34#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:41:35.34#ibcon#first serial, iclass 29, count 0 2006.285.10:41:35.34#ibcon#enter sib2, iclass 29, count 0 2006.285.10:41:35.34#ibcon#flushed, iclass 29, count 0 2006.285.10:41:35.34#ibcon#about to write, iclass 29, count 0 2006.285.10:41:35.34#ibcon#wrote, iclass 29, count 0 2006.285.10:41:35.34#ibcon#about to read 3, iclass 29, count 0 2006.285.10:41:35.36#ibcon#read 3, iclass 29, count 0 2006.285.10:41:35.36#ibcon#about to read 4, iclass 29, count 0 2006.285.10:41:35.36#ibcon#read 4, iclass 29, count 0 2006.285.10:41:35.36#ibcon#about to read 5, iclass 29, count 0 2006.285.10:41:35.36#ibcon#read 5, iclass 29, count 0 2006.285.10:41:35.36#ibcon#about to read 6, iclass 29, count 0 2006.285.10:41:35.36#ibcon#read 6, iclass 29, count 0 2006.285.10:41:35.36#ibcon#end of sib2, iclass 29, count 0 2006.285.10:41:35.36#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:41:35.36#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:41:35.36#ibcon#[25=USB\r\n] 2006.285.10:41:35.36#ibcon#*before write, iclass 29, count 0 2006.285.10:41:35.36#ibcon#enter sib2, iclass 29, count 0 2006.285.10:41:35.36#ibcon#flushed, iclass 29, count 0 2006.285.10:41:35.36#ibcon#about to write, iclass 29, count 0 2006.285.10:41:35.36#ibcon#wrote, iclass 29, count 0 2006.285.10:41:35.36#ibcon#about to read 3, iclass 29, count 0 2006.285.10:41:35.39#ibcon#read 3, iclass 29, count 0 2006.285.10:41:35.39#ibcon#about to read 4, iclass 29, count 0 2006.285.10:41:35.39#ibcon#read 4, iclass 29, count 0 2006.285.10:41:35.39#ibcon#about to read 5, iclass 29, count 0 2006.285.10:41:35.39#ibcon#read 5, iclass 29, count 0 2006.285.10:41:35.39#ibcon#about to read 6, iclass 29, count 0 2006.285.10:41:35.39#ibcon#read 6, iclass 29, count 0 2006.285.10:41:35.39#ibcon#end of sib2, iclass 29, count 0 2006.285.10:41:35.39#ibcon#*after write, iclass 29, count 0 2006.285.10:41:35.39#ibcon#*before return 0, iclass 29, count 0 2006.285.10:41:35.39#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:41:35.39#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:41:35.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:41:35.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:41:35.39$vck44/valo=5,734.99 2006.285.10:41:35.39#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.10:41:35.39#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.10:41:35.39#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:35.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:41:35.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:41:35.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:41:35.39#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:41:35.39#ibcon#first serial, iclass 31, count 0 2006.285.10:41:35.39#ibcon#enter sib2, iclass 31, count 0 2006.285.10:41:35.39#ibcon#flushed, iclass 31, count 0 2006.285.10:41:35.39#ibcon#about to write, iclass 31, count 0 2006.285.10:41:35.39#ibcon#wrote, iclass 31, count 0 2006.285.10:41:35.39#ibcon#about to read 3, iclass 31, count 0 2006.285.10:41:35.41#ibcon#read 3, iclass 31, count 0 2006.285.10:41:35.41#ibcon#about to read 4, iclass 31, count 0 2006.285.10:41:35.41#ibcon#read 4, iclass 31, count 0 2006.285.10:41:35.41#ibcon#about to read 5, iclass 31, count 0 2006.285.10:41:35.41#ibcon#read 5, iclass 31, count 0 2006.285.10:41:35.41#ibcon#about to read 6, iclass 31, count 0 2006.285.10:41:35.41#ibcon#read 6, iclass 31, count 0 2006.285.10:41:35.41#ibcon#end of sib2, iclass 31, count 0 2006.285.10:41:35.41#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:41:35.41#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:41:35.41#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:41:35.41#ibcon#*before write, iclass 31, count 0 2006.285.10:41:35.41#ibcon#enter sib2, iclass 31, count 0 2006.285.10:41:35.41#ibcon#flushed, iclass 31, count 0 2006.285.10:41:35.41#ibcon#about to write, iclass 31, count 0 2006.285.10:41:35.41#ibcon#wrote, iclass 31, count 0 2006.285.10:41:35.41#ibcon#about to read 3, iclass 31, count 0 2006.285.10:41:35.45#ibcon#read 3, iclass 31, count 0 2006.285.10:41:35.45#ibcon#about to read 4, iclass 31, count 0 2006.285.10:41:35.45#ibcon#read 4, iclass 31, count 0 2006.285.10:41:35.45#ibcon#about to read 5, iclass 31, count 0 2006.285.10:41:35.45#ibcon#read 5, iclass 31, count 0 2006.285.10:41:35.45#ibcon#about to read 6, iclass 31, count 0 2006.285.10:41:35.45#ibcon#read 6, iclass 31, count 0 2006.285.10:41:35.45#ibcon#end of sib2, iclass 31, count 0 2006.285.10:41:35.45#ibcon#*after write, iclass 31, count 0 2006.285.10:41:35.45#ibcon#*before return 0, iclass 31, count 0 2006.285.10:41:35.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:41:35.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:41:35.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:41:35.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:41:35.45$vck44/va=5,3 2006.285.10:41:35.45#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.10:41:35.45#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.10:41:35.45#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:35.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:41:35.51#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:41:35.51#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:41:35.51#ibcon#enter wrdev, iclass 33, count 2 2006.285.10:41:35.51#ibcon#first serial, iclass 33, count 2 2006.285.10:41:35.51#ibcon#enter sib2, iclass 33, count 2 2006.285.10:41:35.51#ibcon#flushed, iclass 33, count 2 2006.285.10:41:35.51#ibcon#about to write, iclass 33, count 2 2006.285.10:41:35.51#ibcon#wrote, iclass 33, count 2 2006.285.10:41:35.51#ibcon#about to read 3, iclass 33, count 2 2006.285.10:41:35.53#ibcon#read 3, iclass 33, count 2 2006.285.10:41:35.53#ibcon#about to read 4, iclass 33, count 2 2006.285.10:41:35.53#ibcon#read 4, iclass 33, count 2 2006.285.10:41:35.53#ibcon#about to read 5, iclass 33, count 2 2006.285.10:41:35.53#ibcon#read 5, iclass 33, count 2 2006.285.10:41:35.53#ibcon#about to read 6, iclass 33, count 2 2006.285.10:41:35.53#ibcon#read 6, iclass 33, count 2 2006.285.10:41:35.53#ibcon#end of sib2, iclass 33, count 2 2006.285.10:41:35.53#ibcon#*mode == 0, iclass 33, count 2 2006.285.10:41:35.53#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.10:41:35.53#ibcon#[25=AT05-03\r\n] 2006.285.10:41:35.53#ibcon#*before write, iclass 33, count 2 2006.285.10:41:35.53#ibcon#enter sib2, iclass 33, count 2 2006.285.10:41:35.53#ibcon#flushed, iclass 33, count 2 2006.285.10:41:35.53#ibcon#about to write, iclass 33, count 2 2006.285.10:41:35.53#ibcon#wrote, iclass 33, count 2 2006.285.10:41:35.53#ibcon#about to read 3, iclass 33, count 2 2006.285.10:41:35.56#ibcon#read 3, iclass 33, count 2 2006.285.10:41:35.56#ibcon#about to read 4, iclass 33, count 2 2006.285.10:41:35.56#ibcon#read 4, iclass 33, count 2 2006.285.10:41:35.56#ibcon#about to read 5, iclass 33, count 2 2006.285.10:41:35.56#ibcon#read 5, iclass 33, count 2 2006.285.10:41:35.56#ibcon#about to read 6, iclass 33, count 2 2006.285.10:41:35.56#ibcon#read 6, iclass 33, count 2 2006.285.10:41:35.56#ibcon#end of sib2, iclass 33, count 2 2006.285.10:41:35.56#ibcon#*after write, iclass 33, count 2 2006.285.10:41:35.56#ibcon#*before return 0, iclass 33, count 2 2006.285.10:41:35.56#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:41:35.56#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:41:35.56#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.10:41:35.56#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:35.56#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:41:35.68#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:41:35.68#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:41:35.68#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:41:35.68#ibcon#first serial, iclass 33, count 0 2006.285.10:41:35.68#ibcon#enter sib2, iclass 33, count 0 2006.285.10:41:35.68#ibcon#flushed, iclass 33, count 0 2006.285.10:41:35.68#ibcon#about to write, iclass 33, count 0 2006.285.10:41:35.68#ibcon#wrote, iclass 33, count 0 2006.285.10:41:35.68#ibcon#about to read 3, iclass 33, count 0 2006.285.10:41:35.70#ibcon#read 3, iclass 33, count 0 2006.285.10:41:35.70#ibcon#about to read 4, iclass 33, count 0 2006.285.10:41:35.70#ibcon#read 4, iclass 33, count 0 2006.285.10:41:35.70#ibcon#about to read 5, iclass 33, count 0 2006.285.10:41:35.70#ibcon#read 5, iclass 33, count 0 2006.285.10:41:35.70#ibcon#about to read 6, iclass 33, count 0 2006.285.10:41:35.70#ibcon#read 6, iclass 33, count 0 2006.285.10:41:35.70#ibcon#end of sib2, iclass 33, count 0 2006.285.10:41:35.70#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:41:35.70#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:41:35.70#ibcon#[25=USB\r\n] 2006.285.10:41:35.70#ibcon#*before write, iclass 33, count 0 2006.285.10:41:35.70#ibcon#enter sib2, iclass 33, count 0 2006.285.10:41:35.70#ibcon#flushed, iclass 33, count 0 2006.285.10:41:35.70#ibcon#about to write, iclass 33, count 0 2006.285.10:41:35.70#ibcon#wrote, iclass 33, count 0 2006.285.10:41:35.70#ibcon#about to read 3, iclass 33, count 0 2006.285.10:41:35.73#ibcon#read 3, iclass 33, count 0 2006.285.10:41:35.73#ibcon#about to read 4, iclass 33, count 0 2006.285.10:41:35.73#ibcon#read 4, iclass 33, count 0 2006.285.10:41:35.73#ibcon#about to read 5, iclass 33, count 0 2006.285.10:41:35.73#ibcon#read 5, iclass 33, count 0 2006.285.10:41:35.73#ibcon#about to read 6, iclass 33, count 0 2006.285.10:41:35.73#ibcon#read 6, iclass 33, count 0 2006.285.10:41:35.73#ibcon#end of sib2, iclass 33, count 0 2006.285.10:41:35.73#ibcon#*after write, iclass 33, count 0 2006.285.10:41:35.73#ibcon#*before return 0, iclass 33, count 0 2006.285.10:41:35.73#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:41:35.73#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:41:35.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:41:35.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:41:35.73$vck44/valo=6,814.99 2006.285.10:41:35.73#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.10:41:35.73#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.10:41:35.73#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:35.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:41:35.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:41:35.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:41:35.73#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:41:35.73#ibcon#first serial, iclass 35, count 0 2006.285.10:41:35.73#ibcon#enter sib2, iclass 35, count 0 2006.285.10:41:35.73#ibcon#flushed, iclass 35, count 0 2006.285.10:41:35.73#ibcon#about to write, iclass 35, count 0 2006.285.10:41:35.73#ibcon#wrote, iclass 35, count 0 2006.285.10:41:35.73#ibcon#about to read 3, iclass 35, count 0 2006.285.10:41:35.75#ibcon#read 3, iclass 35, count 0 2006.285.10:41:35.75#ibcon#about to read 4, iclass 35, count 0 2006.285.10:41:35.75#ibcon#read 4, iclass 35, count 0 2006.285.10:41:35.75#ibcon#about to read 5, iclass 35, count 0 2006.285.10:41:35.75#ibcon#read 5, iclass 35, count 0 2006.285.10:41:35.75#ibcon#about to read 6, iclass 35, count 0 2006.285.10:41:35.75#ibcon#read 6, iclass 35, count 0 2006.285.10:41:35.75#ibcon#end of sib2, iclass 35, count 0 2006.285.10:41:35.75#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:41:35.75#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:41:35.75#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:41:35.75#ibcon#*before write, iclass 35, count 0 2006.285.10:41:35.75#ibcon#enter sib2, iclass 35, count 0 2006.285.10:41:35.75#ibcon#flushed, iclass 35, count 0 2006.285.10:41:35.75#ibcon#about to write, iclass 35, count 0 2006.285.10:41:35.75#ibcon#wrote, iclass 35, count 0 2006.285.10:41:35.75#ibcon#about to read 3, iclass 35, count 0 2006.285.10:41:35.79#ibcon#read 3, iclass 35, count 0 2006.285.10:41:35.79#ibcon#about to read 4, iclass 35, count 0 2006.285.10:41:35.79#ibcon#read 4, iclass 35, count 0 2006.285.10:41:35.79#ibcon#about to read 5, iclass 35, count 0 2006.285.10:41:35.79#ibcon#read 5, iclass 35, count 0 2006.285.10:41:35.79#ibcon#about to read 6, iclass 35, count 0 2006.285.10:41:35.79#ibcon#read 6, iclass 35, count 0 2006.285.10:41:35.79#ibcon#end of sib2, iclass 35, count 0 2006.285.10:41:35.79#ibcon#*after write, iclass 35, count 0 2006.285.10:41:35.79#ibcon#*before return 0, iclass 35, count 0 2006.285.10:41:35.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:41:35.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:41:35.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:41:35.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:41:35.79$vck44/va=6,4 2006.285.10:41:35.79#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.10:41:35.79#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.10:41:35.79#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:35.79#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:41:35.85#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:41:35.85#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:41:35.85#ibcon#enter wrdev, iclass 37, count 2 2006.285.10:41:35.85#ibcon#first serial, iclass 37, count 2 2006.285.10:41:35.85#ibcon#enter sib2, iclass 37, count 2 2006.285.10:41:35.85#ibcon#flushed, iclass 37, count 2 2006.285.10:41:35.85#ibcon#about to write, iclass 37, count 2 2006.285.10:41:35.85#ibcon#wrote, iclass 37, count 2 2006.285.10:41:35.85#ibcon#about to read 3, iclass 37, count 2 2006.285.10:41:35.87#ibcon#read 3, iclass 37, count 2 2006.285.10:41:35.87#ibcon#about to read 4, iclass 37, count 2 2006.285.10:41:35.87#ibcon#read 4, iclass 37, count 2 2006.285.10:41:35.87#ibcon#about to read 5, iclass 37, count 2 2006.285.10:41:35.87#ibcon#read 5, iclass 37, count 2 2006.285.10:41:35.87#ibcon#about to read 6, iclass 37, count 2 2006.285.10:41:35.87#ibcon#read 6, iclass 37, count 2 2006.285.10:41:35.87#ibcon#end of sib2, iclass 37, count 2 2006.285.10:41:35.87#ibcon#*mode == 0, iclass 37, count 2 2006.285.10:41:35.87#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.10:41:35.87#ibcon#[25=AT06-04\r\n] 2006.285.10:41:35.87#ibcon#*before write, iclass 37, count 2 2006.285.10:41:35.87#ibcon#enter sib2, iclass 37, count 2 2006.285.10:41:35.87#ibcon#flushed, iclass 37, count 2 2006.285.10:41:35.87#ibcon#about to write, iclass 37, count 2 2006.285.10:41:35.87#ibcon#wrote, iclass 37, count 2 2006.285.10:41:35.87#ibcon#about to read 3, iclass 37, count 2 2006.285.10:41:35.90#ibcon#read 3, iclass 37, count 2 2006.285.10:41:35.90#ibcon#about to read 4, iclass 37, count 2 2006.285.10:41:35.90#ibcon#read 4, iclass 37, count 2 2006.285.10:41:35.90#ibcon#about to read 5, iclass 37, count 2 2006.285.10:41:35.90#ibcon#read 5, iclass 37, count 2 2006.285.10:41:35.90#ibcon#about to read 6, iclass 37, count 2 2006.285.10:41:35.90#ibcon#read 6, iclass 37, count 2 2006.285.10:41:35.90#ibcon#end of sib2, iclass 37, count 2 2006.285.10:41:35.90#ibcon#*after write, iclass 37, count 2 2006.285.10:41:35.90#ibcon#*before return 0, iclass 37, count 2 2006.285.10:41:35.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:41:35.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:41:35.90#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.10:41:35.90#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:35.90#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:41:36.02#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:41:36.02#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:41:36.02#ibcon#enter wrdev, iclass 37, count 0 2006.285.10:41:36.02#ibcon#first serial, iclass 37, count 0 2006.285.10:41:36.02#ibcon#enter sib2, iclass 37, count 0 2006.285.10:41:36.02#ibcon#flushed, iclass 37, count 0 2006.285.10:41:36.02#ibcon#about to write, iclass 37, count 0 2006.285.10:41:36.02#ibcon#wrote, iclass 37, count 0 2006.285.10:41:36.02#ibcon#about to read 3, iclass 37, count 0 2006.285.10:41:36.04#ibcon#read 3, iclass 37, count 0 2006.285.10:41:36.04#ibcon#about to read 4, iclass 37, count 0 2006.285.10:41:36.04#ibcon#read 4, iclass 37, count 0 2006.285.10:41:36.04#ibcon#about to read 5, iclass 37, count 0 2006.285.10:41:36.04#ibcon#read 5, iclass 37, count 0 2006.285.10:41:36.04#ibcon#about to read 6, iclass 37, count 0 2006.285.10:41:36.04#ibcon#read 6, iclass 37, count 0 2006.285.10:41:36.04#ibcon#end of sib2, iclass 37, count 0 2006.285.10:41:36.04#ibcon#*mode == 0, iclass 37, count 0 2006.285.10:41:36.04#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.10:41:36.04#ibcon#[25=USB\r\n] 2006.285.10:41:36.04#ibcon#*before write, iclass 37, count 0 2006.285.10:41:36.04#ibcon#enter sib2, iclass 37, count 0 2006.285.10:41:36.04#ibcon#flushed, iclass 37, count 0 2006.285.10:41:36.04#ibcon#about to write, iclass 37, count 0 2006.285.10:41:36.04#ibcon#wrote, iclass 37, count 0 2006.285.10:41:36.04#ibcon#about to read 3, iclass 37, count 0 2006.285.10:41:36.07#ibcon#read 3, iclass 37, count 0 2006.285.10:41:36.07#ibcon#about to read 4, iclass 37, count 0 2006.285.10:41:36.07#ibcon#read 4, iclass 37, count 0 2006.285.10:41:36.07#ibcon#about to read 5, iclass 37, count 0 2006.285.10:41:36.07#ibcon#read 5, iclass 37, count 0 2006.285.10:41:36.07#ibcon#about to read 6, iclass 37, count 0 2006.285.10:41:36.07#ibcon#read 6, iclass 37, count 0 2006.285.10:41:36.07#ibcon#end of sib2, iclass 37, count 0 2006.285.10:41:36.07#ibcon#*after write, iclass 37, count 0 2006.285.10:41:36.07#ibcon#*before return 0, iclass 37, count 0 2006.285.10:41:36.07#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:41:36.07#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:41:36.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.10:41:36.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.10:41:36.07$vck44/valo=7,864.99 2006.285.10:41:36.07#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.10:41:36.07#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.10:41:36.07#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:36.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:41:36.07#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:41:36.07#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:41:36.07#ibcon#enter wrdev, iclass 39, count 0 2006.285.10:41:36.07#ibcon#first serial, iclass 39, count 0 2006.285.10:41:36.08#ibcon#enter sib2, iclass 39, count 0 2006.285.10:41:36.08#ibcon#flushed, iclass 39, count 0 2006.285.10:41:36.08#ibcon#about to write, iclass 39, count 0 2006.285.10:41:36.08#ibcon#wrote, iclass 39, count 0 2006.285.10:41:36.08#ibcon#about to read 3, iclass 39, count 0 2006.285.10:41:36.09#ibcon#read 3, iclass 39, count 0 2006.285.10:41:36.09#ibcon#about to read 4, iclass 39, count 0 2006.285.10:41:36.09#ibcon#read 4, iclass 39, count 0 2006.285.10:41:36.09#ibcon#about to read 5, iclass 39, count 0 2006.285.10:41:36.09#ibcon#read 5, iclass 39, count 0 2006.285.10:41:36.09#ibcon#about to read 6, iclass 39, count 0 2006.285.10:41:36.09#ibcon#read 6, iclass 39, count 0 2006.285.10:41:36.09#ibcon#end of sib2, iclass 39, count 0 2006.285.10:41:36.09#ibcon#*mode == 0, iclass 39, count 0 2006.285.10:41:36.09#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.10:41:36.09#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:41:36.09#ibcon#*before write, iclass 39, count 0 2006.285.10:41:36.09#ibcon#enter sib2, iclass 39, count 0 2006.285.10:41:36.09#ibcon#flushed, iclass 39, count 0 2006.285.10:41:36.09#ibcon#about to write, iclass 39, count 0 2006.285.10:41:36.09#ibcon#wrote, iclass 39, count 0 2006.285.10:41:36.09#ibcon#about to read 3, iclass 39, count 0 2006.285.10:41:36.13#ibcon#read 3, iclass 39, count 0 2006.285.10:41:36.13#ibcon#about to read 4, iclass 39, count 0 2006.285.10:41:36.13#ibcon#read 4, iclass 39, count 0 2006.285.10:41:36.13#ibcon#about to read 5, iclass 39, count 0 2006.285.10:41:36.13#ibcon#read 5, iclass 39, count 0 2006.285.10:41:36.13#ibcon#about to read 6, iclass 39, count 0 2006.285.10:41:36.13#ibcon#read 6, iclass 39, count 0 2006.285.10:41:36.13#ibcon#end of sib2, iclass 39, count 0 2006.285.10:41:36.13#ibcon#*after write, iclass 39, count 0 2006.285.10:41:36.13#ibcon#*before return 0, iclass 39, count 0 2006.285.10:41:36.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:41:36.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:41:36.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.10:41:36.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.10:41:36.13$vck44/va=7,4 2006.285.10:41:36.13#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.10:41:36.13#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.10:41:36.13#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:36.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:41:36.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:41:36.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:41:36.19#ibcon#enter wrdev, iclass 3, count 2 2006.285.10:41:36.19#ibcon#first serial, iclass 3, count 2 2006.285.10:41:36.19#ibcon#enter sib2, iclass 3, count 2 2006.285.10:41:36.19#ibcon#flushed, iclass 3, count 2 2006.285.10:41:36.19#ibcon#about to write, iclass 3, count 2 2006.285.10:41:36.19#ibcon#wrote, iclass 3, count 2 2006.285.10:41:36.19#ibcon#about to read 3, iclass 3, count 2 2006.285.10:41:36.21#ibcon#read 3, iclass 3, count 2 2006.285.10:41:36.21#ibcon#about to read 4, iclass 3, count 2 2006.285.10:41:36.21#ibcon#read 4, iclass 3, count 2 2006.285.10:41:36.21#ibcon#about to read 5, iclass 3, count 2 2006.285.10:41:36.21#ibcon#read 5, iclass 3, count 2 2006.285.10:41:36.21#ibcon#about to read 6, iclass 3, count 2 2006.285.10:41:36.21#ibcon#read 6, iclass 3, count 2 2006.285.10:41:36.21#ibcon#end of sib2, iclass 3, count 2 2006.285.10:41:36.21#ibcon#*mode == 0, iclass 3, count 2 2006.285.10:41:36.21#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.10:41:36.21#ibcon#[25=AT07-04\r\n] 2006.285.10:41:36.21#ibcon#*before write, iclass 3, count 2 2006.285.10:41:36.21#ibcon#enter sib2, iclass 3, count 2 2006.285.10:41:36.21#ibcon#flushed, iclass 3, count 2 2006.285.10:41:36.21#ibcon#about to write, iclass 3, count 2 2006.285.10:41:36.21#ibcon#wrote, iclass 3, count 2 2006.285.10:41:36.21#ibcon#about to read 3, iclass 3, count 2 2006.285.10:41:36.24#ibcon#read 3, iclass 3, count 2 2006.285.10:41:36.24#ibcon#about to read 4, iclass 3, count 2 2006.285.10:41:36.24#ibcon#read 4, iclass 3, count 2 2006.285.10:41:36.24#ibcon#about to read 5, iclass 3, count 2 2006.285.10:41:36.24#ibcon#read 5, iclass 3, count 2 2006.285.10:41:36.24#ibcon#about to read 6, iclass 3, count 2 2006.285.10:41:36.24#ibcon#read 6, iclass 3, count 2 2006.285.10:41:36.24#ibcon#end of sib2, iclass 3, count 2 2006.285.10:41:36.24#ibcon#*after write, iclass 3, count 2 2006.285.10:41:36.24#ibcon#*before return 0, iclass 3, count 2 2006.285.10:41:36.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:41:36.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:41:36.24#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.10:41:36.24#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:36.24#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:41:36.36#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:41:36.36#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:41:36.36#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:41:36.36#ibcon#first serial, iclass 3, count 0 2006.285.10:41:36.36#ibcon#enter sib2, iclass 3, count 0 2006.285.10:41:36.36#ibcon#flushed, iclass 3, count 0 2006.285.10:41:36.36#ibcon#about to write, iclass 3, count 0 2006.285.10:41:36.36#ibcon#wrote, iclass 3, count 0 2006.285.10:41:36.36#ibcon#about to read 3, iclass 3, count 0 2006.285.10:41:36.38#ibcon#read 3, iclass 3, count 0 2006.285.10:41:36.38#ibcon#about to read 4, iclass 3, count 0 2006.285.10:41:36.38#ibcon#read 4, iclass 3, count 0 2006.285.10:41:36.38#ibcon#about to read 5, iclass 3, count 0 2006.285.10:41:36.38#ibcon#read 5, iclass 3, count 0 2006.285.10:41:36.38#ibcon#about to read 6, iclass 3, count 0 2006.285.10:41:36.38#ibcon#read 6, iclass 3, count 0 2006.285.10:41:36.38#ibcon#end of sib2, iclass 3, count 0 2006.285.10:41:36.38#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:41:36.38#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:41:36.38#ibcon#[25=USB\r\n] 2006.285.10:41:36.38#ibcon#*before write, iclass 3, count 0 2006.285.10:41:36.38#ibcon#enter sib2, iclass 3, count 0 2006.285.10:41:36.38#ibcon#flushed, iclass 3, count 0 2006.285.10:41:36.38#ibcon#about to write, iclass 3, count 0 2006.285.10:41:36.38#ibcon#wrote, iclass 3, count 0 2006.285.10:41:36.38#ibcon#about to read 3, iclass 3, count 0 2006.285.10:41:36.41#ibcon#read 3, iclass 3, count 0 2006.285.10:41:36.41#ibcon#about to read 4, iclass 3, count 0 2006.285.10:41:36.41#ibcon#read 4, iclass 3, count 0 2006.285.10:41:36.41#ibcon#about to read 5, iclass 3, count 0 2006.285.10:41:36.41#ibcon#read 5, iclass 3, count 0 2006.285.10:41:36.41#ibcon#about to read 6, iclass 3, count 0 2006.285.10:41:36.41#ibcon#read 6, iclass 3, count 0 2006.285.10:41:36.41#ibcon#end of sib2, iclass 3, count 0 2006.285.10:41:36.41#ibcon#*after write, iclass 3, count 0 2006.285.10:41:36.41#ibcon#*before return 0, iclass 3, count 0 2006.285.10:41:36.41#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:41:36.41#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:41:36.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:41:36.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:41:36.41$vck44/valo=8,884.99 2006.285.10:41:36.41#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.10:41:36.41#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.10:41:36.41#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:36.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:41:36.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:41:36.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:41:36.41#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:41:36.41#ibcon#first serial, iclass 5, count 0 2006.285.10:41:36.41#ibcon#enter sib2, iclass 5, count 0 2006.285.10:41:36.41#ibcon#flushed, iclass 5, count 0 2006.285.10:41:36.41#ibcon#about to write, iclass 5, count 0 2006.285.10:41:36.41#ibcon#wrote, iclass 5, count 0 2006.285.10:41:36.41#ibcon#about to read 3, iclass 5, count 0 2006.285.10:41:36.43#ibcon#read 3, iclass 5, count 0 2006.285.10:41:36.43#ibcon#about to read 4, iclass 5, count 0 2006.285.10:41:36.43#ibcon#read 4, iclass 5, count 0 2006.285.10:41:36.43#ibcon#about to read 5, iclass 5, count 0 2006.285.10:41:36.43#ibcon#read 5, iclass 5, count 0 2006.285.10:41:36.43#ibcon#about to read 6, iclass 5, count 0 2006.285.10:41:36.43#ibcon#read 6, iclass 5, count 0 2006.285.10:41:36.43#ibcon#end of sib2, iclass 5, count 0 2006.285.10:41:36.43#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:41:36.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:41:36.43#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:41:36.43#ibcon#*before write, iclass 5, count 0 2006.285.10:41:36.43#ibcon#enter sib2, iclass 5, count 0 2006.285.10:41:36.43#ibcon#flushed, iclass 5, count 0 2006.285.10:41:36.43#ibcon#about to write, iclass 5, count 0 2006.285.10:41:36.43#ibcon#wrote, iclass 5, count 0 2006.285.10:41:36.43#ibcon#about to read 3, iclass 5, count 0 2006.285.10:41:36.47#ibcon#read 3, iclass 5, count 0 2006.285.10:41:36.47#ibcon#about to read 4, iclass 5, count 0 2006.285.10:41:36.47#ibcon#read 4, iclass 5, count 0 2006.285.10:41:36.47#ibcon#about to read 5, iclass 5, count 0 2006.285.10:41:36.47#ibcon#read 5, iclass 5, count 0 2006.285.10:41:36.47#ibcon#about to read 6, iclass 5, count 0 2006.285.10:41:36.47#ibcon#read 6, iclass 5, count 0 2006.285.10:41:36.47#ibcon#end of sib2, iclass 5, count 0 2006.285.10:41:36.47#ibcon#*after write, iclass 5, count 0 2006.285.10:41:36.47#ibcon#*before return 0, iclass 5, count 0 2006.285.10:41:36.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:41:36.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:41:36.47#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:41:36.47#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:41:36.47$vck44/va=8,3 2006.285.10:41:36.47#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.10:41:36.47#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.10:41:36.47#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:36.47#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:41:36.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:41:36.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:41:36.53#ibcon#enter wrdev, iclass 7, count 2 2006.285.10:41:36.53#ibcon#first serial, iclass 7, count 2 2006.285.10:41:36.53#ibcon#enter sib2, iclass 7, count 2 2006.285.10:41:36.53#ibcon#flushed, iclass 7, count 2 2006.285.10:41:36.53#ibcon#about to write, iclass 7, count 2 2006.285.10:41:36.53#ibcon#wrote, iclass 7, count 2 2006.285.10:41:36.53#ibcon#about to read 3, iclass 7, count 2 2006.285.10:41:36.55#ibcon#read 3, iclass 7, count 2 2006.285.10:41:36.55#ibcon#about to read 4, iclass 7, count 2 2006.285.10:41:36.55#ibcon#read 4, iclass 7, count 2 2006.285.10:41:36.55#ibcon#about to read 5, iclass 7, count 2 2006.285.10:41:36.55#ibcon#read 5, iclass 7, count 2 2006.285.10:41:36.55#ibcon#about to read 6, iclass 7, count 2 2006.285.10:41:36.55#ibcon#read 6, iclass 7, count 2 2006.285.10:41:36.55#ibcon#end of sib2, iclass 7, count 2 2006.285.10:41:36.55#ibcon#*mode == 0, iclass 7, count 2 2006.285.10:41:36.55#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.10:41:36.55#ibcon#[25=AT08-03\r\n] 2006.285.10:41:36.55#ibcon#*before write, iclass 7, count 2 2006.285.10:41:36.55#ibcon#enter sib2, iclass 7, count 2 2006.285.10:41:36.55#ibcon#flushed, iclass 7, count 2 2006.285.10:41:36.55#ibcon#about to write, iclass 7, count 2 2006.285.10:41:36.55#ibcon#wrote, iclass 7, count 2 2006.285.10:41:36.55#ibcon#about to read 3, iclass 7, count 2 2006.285.10:41:36.58#ibcon#read 3, iclass 7, count 2 2006.285.10:41:36.58#ibcon#about to read 4, iclass 7, count 2 2006.285.10:41:36.58#ibcon#read 4, iclass 7, count 2 2006.285.10:41:36.58#ibcon#about to read 5, iclass 7, count 2 2006.285.10:41:36.58#ibcon#read 5, iclass 7, count 2 2006.285.10:41:36.58#ibcon#about to read 6, iclass 7, count 2 2006.285.10:41:36.58#ibcon#read 6, iclass 7, count 2 2006.285.10:41:36.58#ibcon#end of sib2, iclass 7, count 2 2006.285.10:41:36.58#ibcon#*after write, iclass 7, count 2 2006.285.10:41:36.58#ibcon#*before return 0, iclass 7, count 2 2006.285.10:41:36.58#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:41:36.58#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.10:41:36.58#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.10:41:36.58#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:36.58#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:41:36.70#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:41:36.70#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:41:36.70#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:41:36.70#ibcon#first serial, iclass 7, count 0 2006.285.10:41:36.70#ibcon#enter sib2, iclass 7, count 0 2006.285.10:41:36.70#ibcon#flushed, iclass 7, count 0 2006.285.10:41:36.70#ibcon#about to write, iclass 7, count 0 2006.285.10:41:36.70#ibcon#wrote, iclass 7, count 0 2006.285.10:41:36.70#ibcon#about to read 3, iclass 7, count 0 2006.285.10:41:36.72#ibcon#read 3, iclass 7, count 0 2006.285.10:41:36.72#ibcon#about to read 4, iclass 7, count 0 2006.285.10:41:36.72#ibcon#read 4, iclass 7, count 0 2006.285.10:41:36.72#ibcon#about to read 5, iclass 7, count 0 2006.285.10:41:36.72#ibcon#read 5, iclass 7, count 0 2006.285.10:41:36.72#ibcon#about to read 6, iclass 7, count 0 2006.285.10:41:36.72#ibcon#read 6, iclass 7, count 0 2006.285.10:41:36.72#ibcon#end of sib2, iclass 7, count 0 2006.285.10:41:36.72#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:41:36.72#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:41:36.72#ibcon#[25=USB\r\n] 2006.285.10:41:36.72#ibcon#*before write, iclass 7, count 0 2006.285.10:41:36.72#ibcon#enter sib2, iclass 7, count 0 2006.285.10:41:36.72#ibcon#flushed, iclass 7, count 0 2006.285.10:41:36.72#ibcon#about to write, iclass 7, count 0 2006.285.10:41:36.72#ibcon#wrote, iclass 7, count 0 2006.285.10:41:36.72#ibcon#about to read 3, iclass 7, count 0 2006.285.10:41:36.75#ibcon#read 3, iclass 7, count 0 2006.285.10:41:36.75#ibcon#about to read 4, iclass 7, count 0 2006.285.10:41:36.75#ibcon#read 4, iclass 7, count 0 2006.285.10:41:36.75#ibcon#about to read 5, iclass 7, count 0 2006.285.10:41:36.75#ibcon#read 5, iclass 7, count 0 2006.285.10:41:36.75#ibcon#about to read 6, iclass 7, count 0 2006.285.10:41:36.75#ibcon#read 6, iclass 7, count 0 2006.285.10:41:36.75#ibcon#end of sib2, iclass 7, count 0 2006.285.10:41:36.75#ibcon#*after write, iclass 7, count 0 2006.285.10:41:36.75#ibcon#*before return 0, iclass 7, count 0 2006.285.10:41:36.75#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:41:36.75#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.10:41:36.75#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:41:36.75#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:41:36.75$vck44/vblo=1,629.99 2006.285.10:41:36.75#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.10:41:36.75#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.10:41:36.75#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:36.75#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:41:36.75#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:41:36.75#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:41:36.75#ibcon#enter wrdev, iclass 11, count 0 2006.285.10:41:36.75#ibcon#first serial, iclass 11, count 0 2006.285.10:41:36.75#ibcon#enter sib2, iclass 11, count 0 2006.285.10:41:36.75#ibcon#flushed, iclass 11, count 0 2006.285.10:41:36.75#ibcon#about to write, iclass 11, count 0 2006.285.10:41:36.75#ibcon#wrote, iclass 11, count 0 2006.285.10:41:36.75#ibcon#about to read 3, iclass 11, count 0 2006.285.10:41:36.77#ibcon#read 3, iclass 11, count 0 2006.285.10:41:36.77#ibcon#about to read 4, iclass 11, count 0 2006.285.10:41:36.77#ibcon#read 4, iclass 11, count 0 2006.285.10:41:36.77#ibcon#about to read 5, iclass 11, count 0 2006.285.10:41:36.77#ibcon#read 5, iclass 11, count 0 2006.285.10:41:36.77#ibcon#about to read 6, iclass 11, count 0 2006.285.10:41:36.77#ibcon#read 6, iclass 11, count 0 2006.285.10:41:36.77#ibcon#end of sib2, iclass 11, count 0 2006.285.10:41:36.77#ibcon#*mode == 0, iclass 11, count 0 2006.285.10:41:36.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.10:41:36.77#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:41:36.77#ibcon#*before write, iclass 11, count 0 2006.285.10:41:36.77#ibcon#enter sib2, iclass 11, count 0 2006.285.10:41:36.77#ibcon#flushed, iclass 11, count 0 2006.285.10:41:36.77#ibcon#about to write, iclass 11, count 0 2006.285.10:41:36.77#ibcon#wrote, iclass 11, count 0 2006.285.10:41:36.77#ibcon#about to read 3, iclass 11, count 0 2006.285.10:41:36.81#ibcon#read 3, iclass 11, count 0 2006.285.10:41:36.81#ibcon#about to read 4, iclass 11, count 0 2006.285.10:41:36.81#ibcon#read 4, iclass 11, count 0 2006.285.10:41:36.81#ibcon#about to read 5, iclass 11, count 0 2006.285.10:41:36.81#ibcon#read 5, iclass 11, count 0 2006.285.10:41:36.81#ibcon#about to read 6, iclass 11, count 0 2006.285.10:41:36.81#ibcon#read 6, iclass 11, count 0 2006.285.10:41:36.81#ibcon#end of sib2, iclass 11, count 0 2006.285.10:41:36.81#ibcon#*after write, iclass 11, count 0 2006.285.10:41:36.81#ibcon#*before return 0, iclass 11, count 0 2006.285.10:41:36.81#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:41:36.81#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.10:41:36.81#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.10:41:36.81#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.10:41:36.81$vck44/vb=1,4 2006.285.10:41:36.81#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.10:41:36.81#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.10:41:36.81#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:36.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:41:36.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:41:36.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:41:36.81#ibcon#enter wrdev, iclass 13, count 2 2006.285.10:41:36.81#ibcon#first serial, iclass 13, count 2 2006.285.10:41:36.81#ibcon#enter sib2, iclass 13, count 2 2006.285.10:41:36.81#ibcon#flushed, iclass 13, count 2 2006.285.10:41:36.81#ibcon#about to write, iclass 13, count 2 2006.285.10:41:36.81#ibcon#wrote, iclass 13, count 2 2006.285.10:41:36.81#ibcon#about to read 3, iclass 13, count 2 2006.285.10:41:36.83#ibcon#read 3, iclass 13, count 2 2006.285.10:41:36.83#ibcon#about to read 4, iclass 13, count 2 2006.285.10:41:36.83#ibcon#read 4, iclass 13, count 2 2006.285.10:41:36.83#ibcon#about to read 5, iclass 13, count 2 2006.285.10:41:36.83#ibcon#read 5, iclass 13, count 2 2006.285.10:41:36.83#ibcon#about to read 6, iclass 13, count 2 2006.285.10:41:36.83#ibcon#read 6, iclass 13, count 2 2006.285.10:41:36.83#ibcon#end of sib2, iclass 13, count 2 2006.285.10:41:36.83#ibcon#*mode == 0, iclass 13, count 2 2006.285.10:41:36.83#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.10:41:36.83#ibcon#[27=AT01-04\r\n] 2006.285.10:41:36.83#ibcon#*before write, iclass 13, count 2 2006.285.10:41:36.83#ibcon#enter sib2, iclass 13, count 2 2006.285.10:41:36.83#ibcon#flushed, iclass 13, count 2 2006.285.10:41:36.83#ibcon#about to write, iclass 13, count 2 2006.285.10:41:36.83#ibcon#wrote, iclass 13, count 2 2006.285.10:41:36.83#ibcon#about to read 3, iclass 13, count 2 2006.285.10:41:36.86#ibcon#read 3, iclass 13, count 2 2006.285.10:41:36.86#ibcon#about to read 4, iclass 13, count 2 2006.285.10:41:36.86#ibcon#read 4, iclass 13, count 2 2006.285.10:41:36.86#ibcon#about to read 5, iclass 13, count 2 2006.285.10:41:36.86#ibcon#read 5, iclass 13, count 2 2006.285.10:41:36.86#ibcon#about to read 6, iclass 13, count 2 2006.285.10:41:36.86#ibcon#read 6, iclass 13, count 2 2006.285.10:41:36.86#ibcon#end of sib2, iclass 13, count 2 2006.285.10:41:36.86#ibcon#*after write, iclass 13, count 2 2006.285.10:41:36.86#ibcon#*before return 0, iclass 13, count 2 2006.285.10:41:36.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:41:36.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.10:41:36.86#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.10:41:36.86#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:36.86#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:41:36.98#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:41:36.98#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:41:36.98#ibcon#enter wrdev, iclass 13, count 0 2006.285.10:41:36.98#ibcon#first serial, iclass 13, count 0 2006.285.10:41:36.98#ibcon#enter sib2, iclass 13, count 0 2006.285.10:41:36.98#ibcon#flushed, iclass 13, count 0 2006.285.10:41:36.98#ibcon#about to write, iclass 13, count 0 2006.285.10:41:36.98#ibcon#wrote, iclass 13, count 0 2006.285.10:41:36.98#ibcon#about to read 3, iclass 13, count 0 2006.285.10:41:37.00#ibcon#read 3, iclass 13, count 0 2006.285.10:41:37.00#ibcon#about to read 4, iclass 13, count 0 2006.285.10:41:37.00#ibcon#read 4, iclass 13, count 0 2006.285.10:41:37.00#ibcon#about to read 5, iclass 13, count 0 2006.285.10:41:37.00#ibcon#read 5, iclass 13, count 0 2006.285.10:41:37.00#ibcon#about to read 6, iclass 13, count 0 2006.285.10:41:37.00#ibcon#read 6, iclass 13, count 0 2006.285.10:41:37.00#ibcon#end of sib2, iclass 13, count 0 2006.285.10:41:37.00#ibcon#*mode == 0, iclass 13, count 0 2006.285.10:41:37.00#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.10:41:37.00#ibcon#[27=USB\r\n] 2006.285.10:41:37.00#ibcon#*before write, iclass 13, count 0 2006.285.10:41:37.00#ibcon#enter sib2, iclass 13, count 0 2006.285.10:41:37.00#ibcon#flushed, iclass 13, count 0 2006.285.10:41:37.00#ibcon#about to write, iclass 13, count 0 2006.285.10:41:37.00#ibcon#wrote, iclass 13, count 0 2006.285.10:41:37.00#ibcon#about to read 3, iclass 13, count 0 2006.285.10:41:37.03#ibcon#read 3, iclass 13, count 0 2006.285.10:41:37.03#ibcon#about to read 4, iclass 13, count 0 2006.285.10:41:37.03#ibcon#read 4, iclass 13, count 0 2006.285.10:41:37.03#ibcon#about to read 5, iclass 13, count 0 2006.285.10:41:37.03#ibcon#read 5, iclass 13, count 0 2006.285.10:41:37.03#ibcon#about to read 6, iclass 13, count 0 2006.285.10:41:37.03#ibcon#read 6, iclass 13, count 0 2006.285.10:41:37.03#ibcon#end of sib2, iclass 13, count 0 2006.285.10:41:37.03#ibcon#*after write, iclass 13, count 0 2006.285.10:41:37.03#ibcon#*before return 0, iclass 13, count 0 2006.285.10:41:37.03#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:41:37.03#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.10:41:37.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.10:41:37.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.10:41:37.03$vck44/vblo=2,634.99 2006.285.10:41:37.03#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.10:41:37.03#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.10:41:37.03#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:37.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:41:37.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:41:37.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:41:37.03#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:41:37.03#ibcon#first serial, iclass 15, count 0 2006.285.10:41:37.03#ibcon#enter sib2, iclass 15, count 0 2006.285.10:41:37.03#ibcon#flushed, iclass 15, count 0 2006.285.10:41:37.04#ibcon#about to write, iclass 15, count 0 2006.285.10:41:37.04#ibcon#wrote, iclass 15, count 0 2006.285.10:41:37.04#ibcon#about to read 3, iclass 15, count 0 2006.285.10:41:37.05#ibcon#read 3, iclass 15, count 0 2006.285.10:41:37.05#ibcon#about to read 4, iclass 15, count 0 2006.285.10:41:37.05#ibcon#read 4, iclass 15, count 0 2006.285.10:41:37.05#ibcon#about to read 5, iclass 15, count 0 2006.285.10:41:37.05#ibcon#read 5, iclass 15, count 0 2006.285.10:41:37.05#ibcon#about to read 6, iclass 15, count 0 2006.285.10:41:37.05#ibcon#read 6, iclass 15, count 0 2006.285.10:41:37.05#ibcon#end of sib2, iclass 15, count 0 2006.285.10:41:37.05#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:41:37.05#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:41:37.05#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:41:37.05#ibcon#*before write, iclass 15, count 0 2006.285.10:41:37.05#ibcon#enter sib2, iclass 15, count 0 2006.285.10:41:37.05#ibcon#flushed, iclass 15, count 0 2006.285.10:41:37.05#ibcon#about to write, iclass 15, count 0 2006.285.10:41:37.05#ibcon#wrote, iclass 15, count 0 2006.285.10:41:37.05#ibcon#about to read 3, iclass 15, count 0 2006.285.10:41:37.09#ibcon#read 3, iclass 15, count 0 2006.285.10:41:37.09#ibcon#about to read 4, iclass 15, count 0 2006.285.10:41:37.09#ibcon#read 4, iclass 15, count 0 2006.285.10:41:37.09#ibcon#about to read 5, iclass 15, count 0 2006.285.10:41:37.09#ibcon#read 5, iclass 15, count 0 2006.285.10:41:37.09#ibcon#about to read 6, iclass 15, count 0 2006.285.10:41:37.09#ibcon#read 6, iclass 15, count 0 2006.285.10:41:37.09#ibcon#end of sib2, iclass 15, count 0 2006.285.10:41:37.09#ibcon#*after write, iclass 15, count 0 2006.285.10:41:37.09#ibcon#*before return 0, iclass 15, count 0 2006.285.10:41:37.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:41:37.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.10:41:37.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:41:37.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:41:37.09$vck44/vb=2,5 2006.285.10:41:37.09#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.10:41:37.09#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.10:41:37.09#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:37.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:41:37.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:41:37.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:41:37.15#ibcon#enter wrdev, iclass 17, count 2 2006.285.10:41:37.15#ibcon#first serial, iclass 17, count 2 2006.285.10:41:37.15#ibcon#enter sib2, iclass 17, count 2 2006.285.10:41:37.15#ibcon#flushed, iclass 17, count 2 2006.285.10:41:37.15#ibcon#about to write, iclass 17, count 2 2006.285.10:41:37.15#ibcon#wrote, iclass 17, count 2 2006.285.10:41:37.15#ibcon#about to read 3, iclass 17, count 2 2006.285.10:41:37.17#ibcon#read 3, iclass 17, count 2 2006.285.10:41:37.17#ibcon#about to read 4, iclass 17, count 2 2006.285.10:41:37.17#ibcon#read 4, iclass 17, count 2 2006.285.10:41:37.17#ibcon#about to read 5, iclass 17, count 2 2006.285.10:41:37.17#ibcon#read 5, iclass 17, count 2 2006.285.10:41:37.17#ibcon#about to read 6, iclass 17, count 2 2006.285.10:41:37.17#ibcon#read 6, iclass 17, count 2 2006.285.10:41:37.17#ibcon#end of sib2, iclass 17, count 2 2006.285.10:41:37.17#ibcon#*mode == 0, iclass 17, count 2 2006.285.10:41:37.17#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.10:41:37.17#ibcon#[27=AT02-05\r\n] 2006.285.10:41:37.17#ibcon#*before write, iclass 17, count 2 2006.285.10:41:37.17#ibcon#enter sib2, iclass 17, count 2 2006.285.10:41:37.17#ibcon#flushed, iclass 17, count 2 2006.285.10:41:37.17#ibcon#about to write, iclass 17, count 2 2006.285.10:41:37.17#ibcon#wrote, iclass 17, count 2 2006.285.10:41:37.17#ibcon#about to read 3, iclass 17, count 2 2006.285.10:41:37.20#ibcon#read 3, iclass 17, count 2 2006.285.10:41:37.20#ibcon#about to read 4, iclass 17, count 2 2006.285.10:41:37.20#ibcon#read 4, iclass 17, count 2 2006.285.10:41:37.20#ibcon#about to read 5, iclass 17, count 2 2006.285.10:41:37.20#ibcon#read 5, iclass 17, count 2 2006.285.10:41:37.20#ibcon#about to read 6, iclass 17, count 2 2006.285.10:41:37.20#ibcon#read 6, iclass 17, count 2 2006.285.10:41:37.20#ibcon#end of sib2, iclass 17, count 2 2006.285.10:41:37.20#ibcon#*after write, iclass 17, count 2 2006.285.10:41:37.20#ibcon#*before return 0, iclass 17, count 2 2006.285.10:41:37.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:41:37.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.10:41:37.20#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.10:41:37.20#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:37.20#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:41:37.32#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:41:37.32#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:41:37.32#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:41:37.32#ibcon#first serial, iclass 17, count 0 2006.285.10:41:37.32#ibcon#enter sib2, iclass 17, count 0 2006.285.10:41:37.32#ibcon#flushed, iclass 17, count 0 2006.285.10:41:37.32#ibcon#about to write, iclass 17, count 0 2006.285.10:41:37.32#ibcon#wrote, iclass 17, count 0 2006.285.10:41:37.32#ibcon#about to read 3, iclass 17, count 0 2006.285.10:41:37.34#ibcon#read 3, iclass 17, count 0 2006.285.10:41:37.34#ibcon#about to read 4, iclass 17, count 0 2006.285.10:41:37.34#ibcon#read 4, iclass 17, count 0 2006.285.10:41:37.34#ibcon#about to read 5, iclass 17, count 0 2006.285.10:41:37.34#ibcon#read 5, iclass 17, count 0 2006.285.10:41:37.34#ibcon#about to read 6, iclass 17, count 0 2006.285.10:41:37.34#ibcon#read 6, iclass 17, count 0 2006.285.10:41:37.34#ibcon#end of sib2, iclass 17, count 0 2006.285.10:41:37.34#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:41:37.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:41:37.34#ibcon#[27=USB\r\n] 2006.285.10:41:37.34#ibcon#*before write, iclass 17, count 0 2006.285.10:41:37.34#ibcon#enter sib2, iclass 17, count 0 2006.285.10:41:37.34#ibcon#flushed, iclass 17, count 0 2006.285.10:41:37.34#ibcon#about to write, iclass 17, count 0 2006.285.10:41:37.34#ibcon#wrote, iclass 17, count 0 2006.285.10:41:37.34#ibcon#about to read 3, iclass 17, count 0 2006.285.10:41:37.37#ibcon#read 3, iclass 17, count 0 2006.285.10:41:37.37#ibcon#about to read 4, iclass 17, count 0 2006.285.10:41:37.37#ibcon#read 4, iclass 17, count 0 2006.285.10:41:37.37#ibcon#about to read 5, iclass 17, count 0 2006.285.10:41:37.37#ibcon#read 5, iclass 17, count 0 2006.285.10:41:37.37#ibcon#about to read 6, iclass 17, count 0 2006.285.10:41:37.37#ibcon#read 6, iclass 17, count 0 2006.285.10:41:37.37#ibcon#end of sib2, iclass 17, count 0 2006.285.10:41:37.37#ibcon#*after write, iclass 17, count 0 2006.285.10:41:37.37#ibcon#*before return 0, iclass 17, count 0 2006.285.10:41:37.37#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:41:37.37#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.10:41:37.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:41:37.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:41:37.37$vck44/vblo=3,649.99 2006.285.10:41:37.37#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.10:41:37.37#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.10:41:37.37#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:37.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:41:37.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:41:37.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:41:37.37#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:41:37.37#ibcon#first serial, iclass 19, count 0 2006.285.10:41:37.37#ibcon#enter sib2, iclass 19, count 0 2006.285.10:41:37.37#ibcon#flushed, iclass 19, count 0 2006.285.10:41:37.37#ibcon#about to write, iclass 19, count 0 2006.285.10:41:37.37#ibcon#wrote, iclass 19, count 0 2006.285.10:41:37.37#ibcon#about to read 3, iclass 19, count 0 2006.285.10:41:37.39#ibcon#read 3, iclass 19, count 0 2006.285.10:41:37.39#ibcon#about to read 4, iclass 19, count 0 2006.285.10:41:37.39#ibcon#read 4, iclass 19, count 0 2006.285.10:41:37.39#ibcon#about to read 5, iclass 19, count 0 2006.285.10:41:37.39#ibcon#read 5, iclass 19, count 0 2006.285.10:41:37.39#ibcon#about to read 6, iclass 19, count 0 2006.285.10:41:37.39#ibcon#read 6, iclass 19, count 0 2006.285.10:41:37.39#ibcon#end of sib2, iclass 19, count 0 2006.285.10:41:37.39#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:41:37.39#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:41:37.39#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:41:37.39#ibcon#*before write, iclass 19, count 0 2006.285.10:41:37.39#ibcon#enter sib2, iclass 19, count 0 2006.285.10:41:37.39#ibcon#flushed, iclass 19, count 0 2006.285.10:41:37.39#ibcon#about to write, iclass 19, count 0 2006.285.10:41:37.39#ibcon#wrote, iclass 19, count 0 2006.285.10:41:37.39#ibcon#about to read 3, iclass 19, count 0 2006.285.10:41:37.43#ibcon#read 3, iclass 19, count 0 2006.285.10:41:37.43#ibcon#about to read 4, iclass 19, count 0 2006.285.10:41:37.43#ibcon#read 4, iclass 19, count 0 2006.285.10:41:37.43#ibcon#about to read 5, iclass 19, count 0 2006.285.10:41:37.43#ibcon#read 5, iclass 19, count 0 2006.285.10:41:37.43#ibcon#about to read 6, iclass 19, count 0 2006.285.10:41:37.43#ibcon#read 6, iclass 19, count 0 2006.285.10:41:37.43#ibcon#end of sib2, iclass 19, count 0 2006.285.10:41:37.43#ibcon#*after write, iclass 19, count 0 2006.285.10:41:37.43#ibcon#*before return 0, iclass 19, count 0 2006.285.10:41:37.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:41:37.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.10:41:37.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:41:37.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:41:37.43$vck44/vb=3,4 2006.285.10:41:37.43#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.10:41:37.43#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.10:41:37.43#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:37.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:41:37.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:41:37.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:41:37.49#ibcon#enter wrdev, iclass 21, count 2 2006.285.10:41:37.49#ibcon#first serial, iclass 21, count 2 2006.285.10:41:37.49#ibcon#enter sib2, iclass 21, count 2 2006.285.10:41:37.49#ibcon#flushed, iclass 21, count 2 2006.285.10:41:37.49#ibcon#about to write, iclass 21, count 2 2006.285.10:41:37.49#ibcon#wrote, iclass 21, count 2 2006.285.10:41:37.49#ibcon#about to read 3, iclass 21, count 2 2006.285.10:41:37.51#ibcon#read 3, iclass 21, count 2 2006.285.10:41:37.51#ibcon#about to read 4, iclass 21, count 2 2006.285.10:41:37.51#ibcon#read 4, iclass 21, count 2 2006.285.10:41:37.51#ibcon#about to read 5, iclass 21, count 2 2006.285.10:41:37.51#ibcon#read 5, iclass 21, count 2 2006.285.10:41:37.51#ibcon#about to read 6, iclass 21, count 2 2006.285.10:41:37.51#ibcon#read 6, iclass 21, count 2 2006.285.10:41:37.51#ibcon#end of sib2, iclass 21, count 2 2006.285.10:41:37.51#ibcon#*mode == 0, iclass 21, count 2 2006.285.10:41:37.51#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.10:41:37.51#ibcon#[27=AT03-04\r\n] 2006.285.10:41:37.51#ibcon#*before write, iclass 21, count 2 2006.285.10:41:37.51#ibcon#enter sib2, iclass 21, count 2 2006.285.10:41:37.51#ibcon#flushed, iclass 21, count 2 2006.285.10:41:37.51#ibcon#about to write, iclass 21, count 2 2006.285.10:41:37.51#ibcon#wrote, iclass 21, count 2 2006.285.10:41:37.51#ibcon#about to read 3, iclass 21, count 2 2006.285.10:41:37.54#ibcon#read 3, iclass 21, count 2 2006.285.10:41:37.54#ibcon#about to read 4, iclass 21, count 2 2006.285.10:41:37.54#ibcon#read 4, iclass 21, count 2 2006.285.10:41:37.54#ibcon#about to read 5, iclass 21, count 2 2006.285.10:41:37.54#ibcon#read 5, iclass 21, count 2 2006.285.10:41:37.54#ibcon#about to read 6, iclass 21, count 2 2006.285.10:41:37.54#ibcon#read 6, iclass 21, count 2 2006.285.10:41:37.54#ibcon#end of sib2, iclass 21, count 2 2006.285.10:41:37.54#ibcon#*after write, iclass 21, count 2 2006.285.10:41:37.54#ibcon#*before return 0, iclass 21, count 2 2006.285.10:41:37.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:41:37.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.10:41:37.54#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.10:41:37.54#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:37.54#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:41:37.66#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:41:37.66#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:41:37.66#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:41:37.66#ibcon#first serial, iclass 21, count 0 2006.285.10:41:37.66#ibcon#enter sib2, iclass 21, count 0 2006.285.10:41:37.66#ibcon#flushed, iclass 21, count 0 2006.285.10:41:37.66#ibcon#about to write, iclass 21, count 0 2006.285.10:41:37.66#ibcon#wrote, iclass 21, count 0 2006.285.10:41:37.66#ibcon#about to read 3, iclass 21, count 0 2006.285.10:41:37.68#ibcon#read 3, iclass 21, count 0 2006.285.10:41:37.68#ibcon#about to read 4, iclass 21, count 0 2006.285.10:41:37.68#ibcon#read 4, iclass 21, count 0 2006.285.10:41:37.68#ibcon#about to read 5, iclass 21, count 0 2006.285.10:41:37.68#ibcon#read 5, iclass 21, count 0 2006.285.10:41:37.68#ibcon#about to read 6, iclass 21, count 0 2006.285.10:41:37.68#ibcon#read 6, iclass 21, count 0 2006.285.10:41:37.68#ibcon#end of sib2, iclass 21, count 0 2006.285.10:41:37.68#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:41:37.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:41:37.68#ibcon#[27=USB\r\n] 2006.285.10:41:37.68#ibcon#*before write, iclass 21, count 0 2006.285.10:41:37.68#ibcon#enter sib2, iclass 21, count 0 2006.285.10:41:37.68#ibcon#flushed, iclass 21, count 0 2006.285.10:41:37.68#ibcon#about to write, iclass 21, count 0 2006.285.10:41:37.68#ibcon#wrote, iclass 21, count 0 2006.285.10:41:37.68#ibcon#about to read 3, iclass 21, count 0 2006.285.10:41:37.71#ibcon#read 3, iclass 21, count 0 2006.285.10:41:37.71#ibcon#about to read 4, iclass 21, count 0 2006.285.10:41:37.71#ibcon#read 4, iclass 21, count 0 2006.285.10:41:37.71#ibcon#about to read 5, iclass 21, count 0 2006.285.10:41:37.71#ibcon#read 5, iclass 21, count 0 2006.285.10:41:37.71#ibcon#about to read 6, iclass 21, count 0 2006.285.10:41:37.71#ibcon#read 6, iclass 21, count 0 2006.285.10:41:37.71#ibcon#end of sib2, iclass 21, count 0 2006.285.10:41:37.71#ibcon#*after write, iclass 21, count 0 2006.285.10:41:37.71#ibcon#*before return 0, iclass 21, count 0 2006.285.10:41:37.71#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:41:37.71#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.10:41:37.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:41:37.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:41:37.71$vck44/vblo=4,679.99 2006.285.10:41:37.71#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.10:41:37.71#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.10:41:37.71#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:37.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:41:37.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:41:37.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:41:37.71#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:41:37.71#ibcon#first serial, iclass 23, count 0 2006.285.10:41:37.71#ibcon#enter sib2, iclass 23, count 0 2006.285.10:41:37.71#ibcon#flushed, iclass 23, count 0 2006.285.10:41:37.71#ibcon#about to write, iclass 23, count 0 2006.285.10:41:37.72#ibcon#wrote, iclass 23, count 0 2006.285.10:41:37.72#ibcon#about to read 3, iclass 23, count 0 2006.285.10:41:37.73#ibcon#read 3, iclass 23, count 0 2006.285.10:41:37.73#ibcon#about to read 4, iclass 23, count 0 2006.285.10:41:37.73#ibcon#read 4, iclass 23, count 0 2006.285.10:41:37.73#ibcon#about to read 5, iclass 23, count 0 2006.285.10:41:37.73#ibcon#read 5, iclass 23, count 0 2006.285.10:41:37.73#ibcon#about to read 6, iclass 23, count 0 2006.285.10:41:37.73#ibcon#read 6, iclass 23, count 0 2006.285.10:41:37.73#ibcon#end of sib2, iclass 23, count 0 2006.285.10:41:37.73#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:41:37.73#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:41:37.73#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:41:37.73#ibcon#*before write, iclass 23, count 0 2006.285.10:41:37.73#ibcon#enter sib2, iclass 23, count 0 2006.285.10:41:37.73#ibcon#flushed, iclass 23, count 0 2006.285.10:41:37.73#ibcon#about to write, iclass 23, count 0 2006.285.10:41:37.73#ibcon#wrote, iclass 23, count 0 2006.285.10:41:37.73#ibcon#about to read 3, iclass 23, count 0 2006.285.10:41:37.77#ibcon#read 3, iclass 23, count 0 2006.285.10:41:37.77#ibcon#about to read 4, iclass 23, count 0 2006.285.10:41:37.77#ibcon#read 4, iclass 23, count 0 2006.285.10:41:37.77#ibcon#about to read 5, iclass 23, count 0 2006.285.10:41:37.77#ibcon#read 5, iclass 23, count 0 2006.285.10:41:37.77#ibcon#about to read 6, iclass 23, count 0 2006.285.10:41:37.77#ibcon#read 6, iclass 23, count 0 2006.285.10:41:37.77#ibcon#end of sib2, iclass 23, count 0 2006.285.10:41:37.77#ibcon#*after write, iclass 23, count 0 2006.285.10:41:37.77#ibcon#*before return 0, iclass 23, count 0 2006.285.10:41:37.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:41:37.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.10:41:37.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:41:37.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:41:37.77$vck44/vb=4,5 2006.285.10:41:37.77#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.10:41:37.77#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.10:41:37.77#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:37.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:41:37.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:41:37.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:41:37.83#ibcon#enter wrdev, iclass 25, count 2 2006.285.10:41:37.83#ibcon#first serial, iclass 25, count 2 2006.285.10:41:37.83#ibcon#enter sib2, iclass 25, count 2 2006.285.10:41:37.83#ibcon#flushed, iclass 25, count 2 2006.285.10:41:37.83#ibcon#about to write, iclass 25, count 2 2006.285.10:41:37.83#ibcon#wrote, iclass 25, count 2 2006.285.10:41:37.83#ibcon#about to read 3, iclass 25, count 2 2006.285.10:41:37.85#ibcon#read 3, iclass 25, count 2 2006.285.10:41:37.85#ibcon#about to read 4, iclass 25, count 2 2006.285.10:41:37.85#ibcon#read 4, iclass 25, count 2 2006.285.10:41:37.85#ibcon#about to read 5, iclass 25, count 2 2006.285.10:41:37.85#ibcon#read 5, iclass 25, count 2 2006.285.10:41:37.85#ibcon#about to read 6, iclass 25, count 2 2006.285.10:41:37.85#ibcon#read 6, iclass 25, count 2 2006.285.10:41:37.85#ibcon#end of sib2, iclass 25, count 2 2006.285.10:41:37.85#ibcon#*mode == 0, iclass 25, count 2 2006.285.10:41:37.85#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.10:41:37.85#ibcon#[27=AT04-05\r\n] 2006.285.10:41:37.85#ibcon#*before write, iclass 25, count 2 2006.285.10:41:37.85#ibcon#enter sib2, iclass 25, count 2 2006.285.10:41:37.85#ibcon#flushed, iclass 25, count 2 2006.285.10:41:37.85#ibcon#about to write, iclass 25, count 2 2006.285.10:41:37.85#ibcon#wrote, iclass 25, count 2 2006.285.10:41:37.85#ibcon#about to read 3, iclass 25, count 2 2006.285.10:41:37.88#ibcon#read 3, iclass 25, count 2 2006.285.10:41:37.88#ibcon#about to read 4, iclass 25, count 2 2006.285.10:41:37.88#ibcon#read 4, iclass 25, count 2 2006.285.10:41:37.88#ibcon#about to read 5, iclass 25, count 2 2006.285.10:41:37.88#ibcon#read 5, iclass 25, count 2 2006.285.10:41:37.88#ibcon#about to read 6, iclass 25, count 2 2006.285.10:41:37.88#ibcon#read 6, iclass 25, count 2 2006.285.10:41:37.88#ibcon#end of sib2, iclass 25, count 2 2006.285.10:41:37.88#ibcon#*after write, iclass 25, count 2 2006.285.10:41:37.88#ibcon#*before return 0, iclass 25, count 2 2006.285.10:41:37.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:41:37.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.10:41:37.88#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.10:41:37.88#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:37.88#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:41:38.00#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:41:38.00#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:41:38.00#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:41:38.00#ibcon#first serial, iclass 25, count 0 2006.285.10:41:38.00#ibcon#enter sib2, iclass 25, count 0 2006.285.10:41:38.00#ibcon#flushed, iclass 25, count 0 2006.285.10:41:38.00#ibcon#about to write, iclass 25, count 0 2006.285.10:41:38.00#ibcon#wrote, iclass 25, count 0 2006.285.10:41:38.00#ibcon#about to read 3, iclass 25, count 0 2006.285.10:41:38.02#ibcon#read 3, iclass 25, count 0 2006.285.10:41:38.02#ibcon#about to read 4, iclass 25, count 0 2006.285.10:41:38.02#ibcon#read 4, iclass 25, count 0 2006.285.10:41:38.02#ibcon#about to read 5, iclass 25, count 0 2006.285.10:41:38.02#ibcon#read 5, iclass 25, count 0 2006.285.10:41:38.02#ibcon#about to read 6, iclass 25, count 0 2006.285.10:41:38.02#ibcon#read 6, iclass 25, count 0 2006.285.10:41:38.02#ibcon#end of sib2, iclass 25, count 0 2006.285.10:41:38.02#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:41:38.02#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:41:38.02#ibcon#[27=USB\r\n] 2006.285.10:41:38.02#ibcon#*before write, iclass 25, count 0 2006.285.10:41:38.02#ibcon#enter sib2, iclass 25, count 0 2006.285.10:41:38.02#ibcon#flushed, iclass 25, count 0 2006.285.10:41:38.02#ibcon#about to write, iclass 25, count 0 2006.285.10:41:38.02#ibcon#wrote, iclass 25, count 0 2006.285.10:41:38.02#ibcon#about to read 3, iclass 25, count 0 2006.285.10:41:38.05#ibcon#read 3, iclass 25, count 0 2006.285.10:41:38.05#ibcon#about to read 4, iclass 25, count 0 2006.285.10:41:38.05#ibcon#read 4, iclass 25, count 0 2006.285.10:41:38.05#ibcon#about to read 5, iclass 25, count 0 2006.285.10:41:38.05#ibcon#read 5, iclass 25, count 0 2006.285.10:41:38.05#ibcon#about to read 6, iclass 25, count 0 2006.285.10:41:38.05#ibcon#read 6, iclass 25, count 0 2006.285.10:41:38.05#ibcon#end of sib2, iclass 25, count 0 2006.285.10:41:38.05#ibcon#*after write, iclass 25, count 0 2006.285.10:41:38.05#ibcon#*before return 0, iclass 25, count 0 2006.285.10:41:38.05#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:41:38.05#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.10:41:38.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:41:38.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:41:38.05$vck44/vblo=5,709.99 2006.285.10:41:38.05#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.10:41:38.05#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.10:41:38.05#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:38.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:41:38.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:41:38.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:41:38.05#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:41:38.05#ibcon#first serial, iclass 27, count 0 2006.285.10:41:38.05#ibcon#enter sib2, iclass 27, count 0 2006.285.10:41:38.05#ibcon#flushed, iclass 27, count 0 2006.285.10:41:38.05#ibcon#about to write, iclass 27, count 0 2006.285.10:41:38.05#ibcon#wrote, iclass 27, count 0 2006.285.10:41:38.05#ibcon#about to read 3, iclass 27, count 0 2006.285.10:41:38.07#ibcon#read 3, iclass 27, count 0 2006.285.10:41:38.07#ibcon#about to read 4, iclass 27, count 0 2006.285.10:41:38.07#ibcon#read 4, iclass 27, count 0 2006.285.10:41:38.07#ibcon#about to read 5, iclass 27, count 0 2006.285.10:41:38.07#ibcon#read 5, iclass 27, count 0 2006.285.10:41:38.07#ibcon#about to read 6, iclass 27, count 0 2006.285.10:41:38.07#ibcon#read 6, iclass 27, count 0 2006.285.10:41:38.07#ibcon#end of sib2, iclass 27, count 0 2006.285.10:41:38.07#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:41:38.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:41:38.07#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:41:38.07#ibcon#*before write, iclass 27, count 0 2006.285.10:41:38.07#ibcon#enter sib2, iclass 27, count 0 2006.285.10:41:38.07#ibcon#flushed, iclass 27, count 0 2006.285.10:41:38.07#ibcon#about to write, iclass 27, count 0 2006.285.10:41:38.07#ibcon#wrote, iclass 27, count 0 2006.285.10:41:38.07#ibcon#about to read 3, iclass 27, count 0 2006.285.10:41:38.11#ibcon#read 3, iclass 27, count 0 2006.285.10:41:38.11#ibcon#about to read 4, iclass 27, count 0 2006.285.10:41:38.11#ibcon#read 4, iclass 27, count 0 2006.285.10:41:38.11#ibcon#about to read 5, iclass 27, count 0 2006.285.10:41:38.11#ibcon#read 5, iclass 27, count 0 2006.285.10:41:38.11#ibcon#about to read 6, iclass 27, count 0 2006.285.10:41:38.11#ibcon#read 6, iclass 27, count 0 2006.285.10:41:38.11#ibcon#end of sib2, iclass 27, count 0 2006.285.10:41:38.11#ibcon#*after write, iclass 27, count 0 2006.285.10:41:38.11#ibcon#*before return 0, iclass 27, count 0 2006.285.10:41:38.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:41:38.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.10:41:38.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:41:38.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:41:38.11$vck44/vb=5,4 2006.285.10:41:38.11#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.10:41:38.11#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.10:41:38.11#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:38.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:41:38.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:41:38.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:41:38.17#ibcon#enter wrdev, iclass 29, count 2 2006.285.10:41:38.17#ibcon#first serial, iclass 29, count 2 2006.285.10:41:38.17#ibcon#enter sib2, iclass 29, count 2 2006.285.10:41:38.17#ibcon#flushed, iclass 29, count 2 2006.285.10:41:38.17#ibcon#about to write, iclass 29, count 2 2006.285.10:41:38.17#ibcon#wrote, iclass 29, count 2 2006.285.10:41:38.17#ibcon#about to read 3, iclass 29, count 2 2006.285.10:41:38.19#ibcon#read 3, iclass 29, count 2 2006.285.10:41:38.19#ibcon#about to read 4, iclass 29, count 2 2006.285.10:41:38.19#ibcon#read 4, iclass 29, count 2 2006.285.10:41:38.19#ibcon#about to read 5, iclass 29, count 2 2006.285.10:41:38.19#ibcon#read 5, iclass 29, count 2 2006.285.10:41:38.19#ibcon#about to read 6, iclass 29, count 2 2006.285.10:41:38.19#ibcon#read 6, iclass 29, count 2 2006.285.10:41:38.19#ibcon#end of sib2, iclass 29, count 2 2006.285.10:41:38.19#ibcon#*mode == 0, iclass 29, count 2 2006.285.10:41:38.19#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.10:41:38.19#ibcon#[27=AT05-04\r\n] 2006.285.10:41:38.19#ibcon#*before write, iclass 29, count 2 2006.285.10:41:38.19#ibcon#enter sib2, iclass 29, count 2 2006.285.10:41:38.19#ibcon#flushed, iclass 29, count 2 2006.285.10:41:38.19#ibcon#about to write, iclass 29, count 2 2006.285.10:41:38.19#ibcon#wrote, iclass 29, count 2 2006.285.10:41:38.19#ibcon#about to read 3, iclass 29, count 2 2006.285.10:41:38.22#ibcon#read 3, iclass 29, count 2 2006.285.10:41:38.22#ibcon#about to read 4, iclass 29, count 2 2006.285.10:41:38.22#ibcon#read 4, iclass 29, count 2 2006.285.10:41:38.22#ibcon#about to read 5, iclass 29, count 2 2006.285.10:41:38.22#ibcon#read 5, iclass 29, count 2 2006.285.10:41:38.22#ibcon#about to read 6, iclass 29, count 2 2006.285.10:41:38.22#ibcon#read 6, iclass 29, count 2 2006.285.10:41:38.22#ibcon#end of sib2, iclass 29, count 2 2006.285.10:41:38.22#ibcon#*after write, iclass 29, count 2 2006.285.10:41:38.22#ibcon#*before return 0, iclass 29, count 2 2006.285.10:41:38.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:41:38.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.10:41:38.22#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.10:41:38.22#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:38.22#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:41:38.34#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:41:38.34#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:41:38.34#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:41:38.34#ibcon#first serial, iclass 29, count 0 2006.285.10:41:38.34#ibcon#enter sib2, iclass 29, count 0 2006.285.10:41:38.34#ibcon#flushed, iclass 29, count 0 2006.285.10:41:38.34#ibcon#about to write, iclass 29, count 0 2006.285.10:41:38.34#ibcon#wrote, iclass 29, count 0 2006.285.10:41:38.34#ibcon#about to read 3, iclass 29, count 0 2006.285.10:41:38.36#ibcon#read 3, iclass 29, count 0 2006.285.10:41:38.36#ibcon#about to read 4, iclass 29, count 0 2006.285.10:41:38.36#ibcon#read 4, iclass 29, count 0 2006.285.10:41:38.36#ibcon#about to read 5, iclass 29, count 0 2006.285.10:41:38.36#ibcon#read 5, iclass 29, count 0 2006.285.10:41:38.36#ibcon#about to read 6, iclass 29, count 0 2006.285.10:41:38.36#ibcon#read 6, iclass 29, count 0 2006.285.10:41:38.36#ibcon#end of sib2, iclass 29, count 0 2006.285.10:41:38.36#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:41:38.36#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:41:38.36#ibcon#[27=USB\r\n] 2006.285.10:41:38.36#ibcon#*before write, iclass 29, count 0 2006.285.10:41:38.36#ibcon#enter sib2, iclass 29, count 0 2006.285.10:41:38.36#ibcon#flushed, iclass 29, count 0 2006.285.10:41:38.36#ibcon#about to write, iclass 29, count 0 2006.285.10:41:38.36#ibcon#wrote, iclass 29, count 0 2006.285.10:41:38.36#ibcon#about to read 3, iclass 29, count 0 2006.285.10:41:38.39#ibcon#read 3, iclass 29, count 0 2006.285.10:41:38.39#ibcon#about to read 4, iclass 29, count 0 2006.285.10:41:38.39#ibcon#read 4, iclass 29, count 0 2006.285.10:41:38.39#ibcon#about to read 5, iclass 29, count 0 2006.285.10:41:38.39#ibcon#read 5, iclass 29, count 0 2006.285.10:41:38.39#ibcon#about to read 6, iclass 29, count 0 2006.285.10:41:38.39#ibcon#read 6, iclass 29, count 0 2006.285.10:41:38.39#ibcon#end of sib2, iclass 29, count 0 2006.285.10:41:38.39#ibcon#*after write, iclass 29, count 0 2006.285.10:41:38.39#ibcon#*before return 0, iclass 29, count 0 2006.285.10:41:38.39#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:41:38.39#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.10:41:38.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:41:38.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:41:38.39$vck44/vblo=6,719.99 2006.285.10:41:38.39#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.10:41:38.39#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.10:41:38.39#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:38.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:41:38.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:41:38.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:41:38.39#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:41:38.39#ibcon#first serial, iclass 31, count 0 2006.285.10:41:38.39#ibcon#enter sib2, iclass 31, count 0 2006.285.10:41:38.39#ibcon#flushed, iclass 31, count 0 2006.285.10:41:38.39#ibcon#about to write, iclass 31, count 0 2006.285.10:41:38.39#ibcon#wrote, iclass 31, count 0 2006.285.10:41:38.39#ibcon#about to read 3, iclass 31, count 0 2006.285.10:41:38.41#ibcon#read 3, iclass 31, count 0 2006.285.10:41:38.41#ibcon#about to read 4, iclass 31, count 0 2006.285.10:41:38.41#ibcon#read 4, iclass 31, count 0 2006.285.10:41:38.41#ibcon#about to read 5, iclass 31, count 0 2006.285.10:41:38.41#ibcon#read 5, iclass 31, count 0 2006.285.10:41:38.41#ibcon#about to read 6, iclass 31, count 0 2006.285.10:41:38.41#ibcon#read 6, iclass 31, count 0 2006.285.10:41:38.41#ibcon#end of sib2, iclass 31, count 0 2006.285.10:41:38.41#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:41:38.41#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:41:38.41#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:41:38.41#ibcon#*before write, iclass 31, count 0 2006.285.10:41:38.41#ibcon#enter sib2, iclass 31, count 0 2006.285.10:41:38.41#ibcon#flushed, iclass 31, count 0 2006.285.10:41:38.41#ibcon#about to write, iclass 31, count 0 2006.285.10:41:38.41#ibcon#wrote, iclass 31, count 0 2006.285.10:41:38.41#ibcon#about to read 3, iclass 31, count 0 2006.285.10:41:38.45#ibcon#read 3, iclass 31, count 0 2006.285.10:41:38.45#ibcon#about to read 4, iclass 31, count 0 2006.285.10:41:38.45#ibcon#read 4, iclass 31, count 0 2006.285.10:41:38.45#ibcon#about to read 5, iclass 31, count 0 2006.285.10:41:38.45#ibcon#read 5, iclass 31, count 0 2006.285.10:41:38.45#ibcon#about to read 6, iclass 31, count 0 2006.285.10:41:38.45#ibcon#read 6, iclass 31, count 0 2006.285.10:41:38.45#ibcon#end of sib2, iclass 31, count 0 2006.285.10:41:38.45#ibcon#*after write, iclass 31, count 0 2006.285.10:41:38.45#ibcon#*before return 0, iclass 31, count 0 2006.285.10:41:38.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:41:38.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.10:41:38.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:41:38.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:41:38.45$vck44/vb=6,3 2006.285.10:41:38.45#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.10:41:38.45#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.10:41:38.45#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:38.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:41:38.51#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:41:38.51#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:41:38.51#ibcon#enter wrdev, iclass 33, count 2 2006.285.10:41:38.51#ibcon#first serial, iclass 33, count 2 2006.285.10:41:38.51#ibcon#enter sib2, iclass 33, count 2 2006.285.10:41:38.51#ibcon#flushed, iclass 33, count 2 2006.285.10:41:38.51#ibcon#about to write, iclass 33, count 2 2006.285.10:41:38.51#ibcon#wrote, iclass 33, count 2 2006.285.10:41:38.51#ibcon#about to read 3, iclass 33, count 2 2006.285.10:41:38.53#ibcon#read 3, iclass 33, count 2 2006.285.10:41:38.53#ibcon#about to read 4, iclass 33, count 2 2006.285.10:41:38.53#ibcon#read 4, iclass 33, count 2 2006.285.10:41:38.53#ibcon#about to read 5, iclass 33, count 2 2006.285.10:41:38.53#ibcon#read 5, iclass 33, count 2 2006.285.10:41:38.53#ibcon#about to read 6, iclass 33, count 2 2006.285.10:41:38.53#ibcon#read 6, iclass 33, count 2 2006.285.10:41:38.53#ibcon#end of sib2, iclass 33, count 2 2006.285.10:41:38.53#ibcon#*mode == 0, iclass 33, count 2 2006.285.10:41:38.53#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.10:41:38.53#ibcon#[27=AT06-03\r\n] 2006.285.10:41:38.53#ibcon#*before write, iclass 33, count 2 2006.285.10:41:38.53#ibcon#enter sib2, iclass 33, count 2 2006.285.10:41:38.53#ibcon#flushed, iclass 33, count 2 2006.285.10:41:38.53#ibcon#about to write, iclass 33, count 2 2006.285.10:41:38.53#ibcon#wrote, iclass 33, count 2 2006.285.10:41:38.53#ibcon#about to read 3, iclass 33, count 2 2006.285.10:41:38.56#ibcon#read 3, iclass 33, count 2 2006.285.10:41:38.56#ibcon#about to read 4, iclass 33, count 2 2006.285.10:41:38.56#ibcon#read 4, iclass 33, count 2 2006.285.10:41:38.56#ibcon#about to read 5, iclass 33, count 2 2006.285.10:41:38.56#ibcon#read 5, iclass 33, count 2 2006.285.10:41:38.56#ibcon#about to read 6, iclass 33, count 2 2006.285.10:41:38.56#ibcon#read 6, iclass 33, count 2 2006.285.10:41:38.56#ibcon#end of sib2, iclass 33, count 2 2006.285.10:41:38.56#ibcon#*after write, iclass 33, count 2 2006.285.10:41:38.56#ibcon#*before return 0, iclass 33, count 2 2006.285.10:41:38.56#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:41:38.56#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.10:41:38.56#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.10:41:38.56#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:38.56#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:41:38.68#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:41:38.68#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:41:38.68#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:41:38.68#ibcon#first serial, iclass 33, count 0 2006.285.10:41:38.68#ibcon#enter sib2, iclass 33, count 0 2006.285.10:41:38.68#ibcon#flushed, iclass 33, count 0 2006.285.10:41:38.68#ibcon#about to write, iclass 33, count 0 2006.285.10:41:38.68#ibcon#wrote, iclass 33, count 0 2006.285.10:41:38.68#ibcon#about to read 3, iclass 33, count 0 2006.285.10:41:38.70#ibcon#read 3, iclass 33, count 0 2006.285.10:41:38.70#ibcon#about to read 4, iclass 33, count 0 2006.285.10:41:38.70#ibcon#read 4, iclass 33, count 0 2006.285.10:41:38.70#ibcon#about to read 5, iclass 33, count 0 2006.285.10:41:38.70#ibcon#read 5, iclass 33, count 0 2006.285.10:41:38.70#ibcon#about to read 6, iclass 33, count 0 2006.285.10:41:38.70#ibcon#read 6, iclass 33, count 0 2006.285.10:41:38.70#ibcon#end of sib2, iclass 33, count 0 2006.285.10:41:38.70#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:41:38.70#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:41:38.70#ibcon#[27=USB\r\n] 2006.285.10:41:38.70#ibcon#*before write, iclass 33, count 0 2006.285.10:41:38.70#ibcon#enter sib2, iclass 33, count 0 2006.285.10:41:38.70#ibcon#flushed, iclass 33, count 0 2006.285.10:41:38.70#ibcon#about to write, iclass 33, count 0 2006.285.10:41:38.70#ibcon#wrote, iclass 33, count 0 2006.285.10:41:38.70#ibcon#about to read 3, iclass 33, count 0 2006.285.10:41:38.73#ibcon#read 3, iclass 33, count 0 2006.285.10:41:38.73#ibcon#about to read 4, iclass 33, count 0 2006.285.10:41:38.73#ibcon#read 4, iclass 33, count 0 2006.285.10:41:38.73#ibcon#about to read 5, iclass 33, count 0 2006.285.10:41:38.73#ibcon#read 5, iclass 33, count 0 2006.285.10:41:38.73#ibcon#about to read 6, iclass 33, count 0 2006.285.10:41:38.73#ibcon#read 6, iclass 33, count 0 2006.285.10:41:38.73#ibcon#end of sib2, iclass 33, count 0 2006.285.10:41:38.73#ibcon#*after write, iclass 33, count 0 2006.285.10:41:38.73#ibcon#*before return 0, iclass 33, count 0 2006.285.10:41:38.73#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:41:38.73#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.10:41:38.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:41:38.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:41:38.73$vck44/vblo=7,734.99 2006.285.10:41:38.73#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.10:41:38.73#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.10:41:38.73#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:38.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:41:38.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:41:38.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:41:38.73#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:41:38.73#ibcon#first serial, iclass 35, count 0 2006.285.10:41:38.73#ibcon#enter sib2, iclass 35, count 0 2006.285.10:41:38.73#ibcon#flushed, iclass 35, count 0 2006.285.10:41:38.73#ibcon#about to write, iclass 35, count 0 2006.285.10:41:38.74#ibcon#wrote, iclass 35, count 0 2006.285.10:41:38.74#ibcon#about to read 3, iclass 35, count 0 2006.285.10:41:38.75#ibcon#read 3, iclass 35, count 0 2006.285.10:41:38.75#ibcon#about to read 4, iclass 35, count 0 2006.285.10:41:38.75#ibcon#read 4, iclass 35, count 0 2006.285.10:41:38.75#ibcon#about to read 5, iclass 35, count 0 2006.285.10:41:38.75#ibcon#read 5, iclass 35, count 0 2006.285.10:41:38.75#ibcon#about to read 6, iclass 35, count 0 2006.285.10:41:38.75#ibcon#read 6, iclass 35, count 0 2006.285.10:41:38.75#ibcon#end of sib2, iclass 35, count 0 2006.285.10:41:38.75#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:41:38.75#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:41:38.75#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:41:38.75#ibcon#*before write, iclass 35, count 0 2006.285.10:41:38.75#ibcon#enter sib2, iclass 35, count 0 2006.285.10:41:38.75#ibcon#flushed, iclass 35, count 0 2006.285.10:41:38.75#ibcon#about to write, iclass 35, count 0 2006.285.10:41:38.75#ibcon#wrote, iclass 35, count 0 2006.285.10:41:38.75#ibcon#about to read 3, iclass 35, count 0 2006.285.10:41:38.79#ibcon#read 3, iclass 35, count 0 2006.285.10:41:38.79#ibcon#about to read 4, iclass 35, count 0 2006.285.10:41:38.79#ibcon#read 4, iclass 35, count 0 2006.285.10:41:38.79#ibcon#about to read 5, iclass 35, count 0 2006.285.10:41:38.79#ibcon#read 5, iclass 35, count 0 2006.285.10:41:38.79#ibcon#about to read 6, iclass 35, count 0 2006.285.10:41:38.79#ibcon#read 6, iclass 35, count 0 2006.285.10:41:38.79#ibcon#end of sib2, iclass 35, count 0 2006.285.10:41:38.79#ibcon#*after write, iclass 35, count 0 2006.285.10:41:38.79#ibcon#*before return 0, iclass 35, count 0 2006.285.10:41:38.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:41:38.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:41:38.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:41:38.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:41:38.79$vck44/vb=7,4 2006.285.10:41:38.79#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.10:41:38.79#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.10:41:38.79#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:38.79#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:41:38.85#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:41:38.85#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:41:38.85#ibcon#enter wrdev, iclass 37, count 2 2006.285.10:41:38.85#ibcon#first serial, iclass 37, count 2 2006.285.10:41:38.85#ibcon#enter sib2, iclass 37, count 2 2006.285.10:41:38.85#ibcon#flushed, iclass 37, count 2 2006.285.10:41:38.85#ibcon#about to write, iclass 37, count 2 2006.285.10:41:38.85#ibcon#wrote, iclass 37, count 2 2006.285.10:41:38.85#ibcon#about to read 3, iclass 37, count 2 2006.285.10:41:38.87#ibcon#read 3, iclass 37, count 2 2006.285.10:41:38.87#ibcon#about to read 4, iclass 37, count 2 2006.285.10:41:38.87#ibcon#read 4, iclass 37, count 2 2006.285.10:41:38.87#ibcon#about to read 5, iclass 37, count 2 2006.285.10:41:38.87#ibcon#read 5, iclass 37, count 2 2006.285.10:41:38.87#ibcon#about to read 6, iclass 37, count 2 2006.285.10:41:38.87#ibcon#read 6, iclass 37, count 2 2006.285.10:41:38.87#ibcon#end of sib2, iclass 37, count 2 2006.285.10:41:38.87#ibcon#*mode == 0, iclass 37, count 2 2006.285.10:41:38.87#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.10:41:38.87#ibcon#[27=AT07-04\r\n] 2006.285.10:41:38.87#ibcon#*before write, iclass 37, count 2 2006.285.10:41:38.87#ibcon#enter sib2, iclass 37, count 2 2006.285.10:41:38.87#ibcon#flushed, iclass 37, count 2 2006.285.10:41:38.87#ibcon#about to write, iclass 37, count 2 2006.285.10:41:38.87#ibcon#wrote, iclass 37, count 2 2006.285.10:41:38.87#ibcon#about to read 3, iclass 37, count 2 2006.285.10:41:38.90#ibcon#read 3, iclass 37, count 2 2006.285.10:41:38.90#ibcon#about to read 4, iclass 37, count 2 2006.285.10:41:38.90#ibcon#read 4, iclass 37, count 2 2006.285.10:41:38.90#ibcon#about to read 5, iclass 37, count 2 2006.285.10:41:38.90#ibcon#read 5, iclass 37, count 2 2006.285.10:41:38.90#ibcon#about to read 6, iclass 37, count 2 2006.285.10:41:38.90#ibcon#read 6, iclass 37, count 2 2006.285.10:41:38.90#ibcon#end of sib2, iclass 37, count 2 2006.285.10:41:38.90#ibcon#*after write, iclass 37, count 2 2006.285.10:41:38.90#ibcon#*before return 0, iclass 37, count 2 2006.285.10:41:38.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:41:38.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.10:41:38.90#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.10:41:38.90#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:38.90#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:41:39.02#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:41:39.02#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:41:39.02#ibcon#enter wrdev, iclass 37, count 0 2006.285.10:41:39.02#ibcon#first serial, iclass 37, count 0 2006.285.10:41:39.02#ibcon#enter sib2, iclass 37, count 0 2006.285.10:41:39.02#ibcon#flushed, iclass 37, count 0 2006.285.10:41:39.02#ibcon#about to write, iclass 37, count 0 2006.285.10:41:39.02#ibcon#wrote, iclass 37, count 0 2006.285.10:41:39.02#ibcon#about to read 3, iclass 37, count 0 2006.285.10:41:39.04#ibcon#read 3, iclass 37, count 0 2006.285.10:41:39.04#ibcon#about to read 4, iclass 37, count 0 2006.285.10:41:39.04#ibcon#read 4, iclass 37, count 0 2006.285.10:41:39.04#ibcon#about to read 5, iclass 37, count 0 2006.285.10:41:39.04#ibcon#read 5, iclass 37, count 0 2006.285.10:41:39.04#ibcon#about to read 6, iclass 37, count 0 2006.285.10:41:39.04#ibcon#read 6, iclass 37, count 0 2006.285.10:41:39.04#ibcon#end of sib2, iclass 37, count 0 2006.285.10:41:39.04#ibcon#*mode == 0, iclass 37, count 0 2006.285.10:41:39.04#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.10:41:39.04#ibcon#[27=USB\r\n] 2006.285.10:41:39.04#ibcon#*before write, iclass 37, count 0 2006.285.10:41:39.04#ibcon#enter sib2, iclass 37, count 0 2006.285.10:41:39.04#ibcon#flushed, iclass 37, count 0 2006.285.10:41:39.04#ibcon#about to write, iclass 37, count 0 2006.285.10:41:39.04#ibcon#wrote, iclass 37, count 0 2006.285.10:41:39.04#ibcon#about to read 3, iclass 37, count 0 2006.285.10:41:39.07#ibcon#read 3, iclass 37, count 0 2006.285.10:41:39.07#ibcon#about to read 4, iclass 37, count 0 2006.285.10:41:39.07#ibcon#read 4, iclass 37, count 0 2006.285.10:41:39.07#ibcon#about to read 5, iclass 37, count 0 2006.285.10:41:39.07#ibcon#read 5, iclass 37, count 0 2006.285.10:41:39.07#ibcon#about to read 6, iclass 37, count 0 2006.285.10:41:39.07#ibcon#read 6, iclass 37, count 0 2006.285.10:41:39.07#ibcon#end of sib2, iclass 37, count 0 2006.285.10:41:39.07#ibcon#*after write, iclass 37, count 0 2006.285.10:41:39.07#ibcon#*before return 0, iclass 37, count 0 2006.285.10:41:39.07#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:41:39.07#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.10:41:39.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.10:41:39.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.10:41:39.07$vck44/vblo=8,744.99 2006.285.10:41:39.07#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.10:41:39.07#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.10:41:39.07#ibcon#ireg 17 cls_cnt 0 2006.285.10:41:39.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:41:39.07#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:41:39.07#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:41:39.07#ibcon#enter wrdev, iclass 39, count 0 2006.285.10:41:39.07#ibcon#first serial, iclass 39, count 0 2006.285.10:41:39.07#ibcon#enter sib2, iclass 39, count 0 2006.285.10:41:39.08#ibcon#flushed, iclass 39, count 0 2006.285.10:41:39.08#ibcon#about to write, iclass 39, count 0 2006.285.10:41:39.08#ibcon#wrote, iclass 39, count 0 2006.285.10:41:39.08#ibcon#about to read 3, iclass 39, count 0 2006.285.10:41:39.09#ibcon#read 3, iclass 39, count 0 2006.285.10:41:39.09#ibcon#about to read 4, iclass 39, count 0 2006.285.10:41:39.09#ibcon#read 4, iclass 39, count 0 2006.285.10:41:39.09#ibcon#about to read 5, iclass 39, count 0 2006.285.10:41:39.09#ibcon#read 5, iclass 39, count 0 2006.285.10:41:39.09#ibcon#about to read 6, iclass 39, count 0 2006.285.10:41:39.09#ibcon#read 6, iclass 39, count 0 2006.285.10:41:39.09#ibcon#end of sib2, iclass 39, count 0 2006.285.10:41:39.09#ibcon#*mode == 0, iclass 39, count 0 2006.285.10:41:39.09#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.10:41:39.09#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:41:39.09#ibcon#*before write, iclass 39, count 0 2006.285.10:41:39.09#ibcon#enter sib2, iclass 39, count 0 2006.285.10:41:39.09#ibcon#flushed, iclass 39, count 0 2006.285.10:41:39.09#ibcon#about to write, iclass 39, count 0 2006.285.10:41:39.09#ibcon#wrote, iclass 39, count 0 2006.285.10:41:39.09#ibcon#about to read 3, iclass 39, count 0 2006.285.10:41:39.13#ibcon#read 3, iclass 39, count 0 2006.285.10:41:39.13#ibcon#about to read 4, iclass 39, count 0 2006.285.10:41:39.13#ibcon#read 4, iclass 39, count 0 2006.285.10:41:39.13#ibcon#about to read 5, iclass 39, count 0 2006.285.10:41:39.13#ibcon#read 5, iclass 39, count 0 2006.285.10:41:39.13#ibcon#about to read 6, iclass 39, count 0 2006.285.10:41:39.13#ibcon#read 6, iclass 39, count 0 2006.285.10:41:39.13#ibcon#end of sib2, iclass 39, count 0 2006.285.10:41:39.13#ibcon#*after write, iclass 39, count 0 2006.285.10:41:39.13#ibcon#*before return 0, iclass 39, count 0 2006.285.10:41:39.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:41:39.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.10:41:39.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.10:41:39.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.10:41:39.13$vck44/vb=8,4 2006.285.10:41:39.13#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.10:41:39.13#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.10:41:39.13#ibcon#ireg 11 cls_cnt 2 2006.285.10:41:39.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:41:39.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:41:39.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:41:39.19#ibcon#enter wrdev, iclass 3, count 2 2006.285.10:41:39.19#ibcon#first serial, iclass 3, count 2 2006.285.10:41:39.19#ibcon#enter sib2, iclass 3, count 2 2006.285.10:41:39.19#ibcon#flushed, iclass 3, count 2 2006.285.10:41:39.19#ibcon#about to write, iclass 3, count 2 2006.285.10:41:39.19#ibcon#wrote, iclass 3, count 2 2006.285.10:41:39.19#ibcon#about to read 3, iclass 3, count 2 2006.285.10:41:39.21#ibcon#read 3, iclass 3, count 2 2006.285.10:41:39.21#ibcon#about to read 4, iclass 3, count 2 2006.285.10:41:39.21#ibcon#read 4, iclass 3, count 2 2006.285.10:41:39.21#ibcon#about to read 5, iclass 3, count 2 2006.285.10:41:39.21#ibcon#read 5, iclass 3, count 2 2006.285.10:41:39.21#ibcon#about to read 6, iclass 3, count 2 2006.285.10:41:39.21#ibcon#read 6, iclass 3, count 2 2006.285.10:41:39.21#ibcon#end of sib2, iclass 3, count 2 2006.285.10:41:39.21#ibcon#*mode == 0, iclass 3, count 2 2006.285.10:41:39.21#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.10:41:39.21#ibcon#[27=AT08-04\r\n] 2006.285.10:41:39.21#ibcon#*before write, iclass 3, count 2 2006.285.10:41:39.21#ibcon#enter sib2, iclass 3, count 2 2006.285.10:41:39.21#ibcon#flushed, iclass 3, count 2 2006.285.10:41:39.21#ibcon#about to write, iclass 3, count 2 2006.285.10:41:39.21#ibcon#wrote, iclass 3, count 2 2006.285.10:41:39.21#ibcon#about to read 3, iclass 3, count 2 2006.285.10:41:39.24#ibcon#read 3, iclass 3, count 2 2006.285.10:41:39.24#ibcon#about to read 4, iclass 3, count 2 2006.285.10:41:39.24#ibcon#read 4, iclass 3, count 2 2006.285.10:41:39.24#ibcon#about to read 5, iclass 3, count 2 2006.285.10:41:39.24#ibcon#read 5, iclass 3, count 2 2006.285.10:41:39.24#ibcon#about to read 6, iclass 3, count 2 2006.285.10:41:39.24#ibcon#read 6, iclass 3, count 2 2006.285.10:41:39.24#ibcon#end of sib2, iclass 3, count 2 2006.285.10:41:39.24#ibcon#*after write, iclass 3, count 2 2006.285.10:41:39.24#ibcon#*before return 0, iclass 3, count 2 2006.285.10:41:39.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:41:39.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.10:41:39.24#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.10:41:39.24#ibcon#ireg 7 cls_cnt 0 2006.285.10:41:39.24#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:41:39.36#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:41:39.36#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:41:39.36#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:41:39.36#ibcon#first serial, iclass 3, count 0 2006.285.10:41:39.36#ibcon#enter sib2, iclass 3, count 0 2006.285.10:41:39.36#ibcon#flushed, iclass 3, count 0 2006.285.10:41:39.36#ibcon#about to write, iclass 3, count 0 2006.285.10:41:39.36#ibcon#wrote, iclass 3, count 0 2006.285.10:41:39.36#ibcon#about to read 3, iclass 3, count 0 2006.285.10:41:39.38#ibcon#read 3, iclass 3, count 0 2006.285.10:41:39.38#ibcon#about to read 4, iclass 3, count 0 2006.285.10:41:39.38#ibcon#read 4, iclass 3, count 0 2006.285.10:41:39.38#ibcon#about to read 5, iclass 3, count 0 2006.285.10:41:39.38#ibcon#read 5, iclass 3, count 0 2006.285.10:41:39.38#ibcon#about to read 6, iclass 3, count 0 2006.285.10:41:39.38#ibcon#read 6, iclass 3, count 0 2006.285.10:41:39.38#ibcon#end of sib2, iclass 3, count 0 2006.285.10:41:39.38#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:41:39.38#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:41:39.38#ibcon#[27=USB\r\n] 2006.285.10:41:39.38#ibcon#*before write, iclass 3, count 0 2006.285.10:41:39.38#ibcon#enter sib2, iclass 3, count 0 2006.285.10:41:39.38#ibcon#flushed, iclass 3, count 0 2006.285.10:41:39.38#ibcon#about to write, iclass 3, count 0 2006.285.10:41:39.38#ibcon#wrote, iclass 3, count 0 2006.285.10:41:39.38#ibcon#about to read 3, iclass 3, count 0 2006.285.10:41:39.41#ibcon#read 3, iclass 3, count 0 2006.285.10:41:39.41#ibcon#about to read 4, iclass 3, count 0 2006.285.10:41:39.41#ibcon#read 4, iclass 3, count 0 2006.285.10:41:39.41#ibcon#about to read 5, iclass 3, count 0 2006.285.10:41:39.41#ibcon#read 5, iclass 3, count 0 2006.285.10:41:39.41#ibcon#about to read 6, iclass 3, count 0 2006.285.10:41:39.41#ibcon#read 6, iclass 3, count 0 2006.285.10:41:39.41#ibcon#end of sib2, iclass 3, count 0 2006.285.10:41:39.41#ibcon#*after write, iclass 3, count 0 2006.285.10:41:39.41#ibcon#*before return 0, iclass 3, count 0 2006.285.10:41:39.41#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:41:39.41#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.10:41:39.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:41:39.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:41:39.41$vck44/vabw=wide 2006.285.10:41:39.41#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.10:41:39.41#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.10:41:39.41#ibcon#ireg 8 cls_cnt 0 2006.285.10:41:39.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:41:39.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:41:39.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:41:39.41#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:41:39.41#ibcon#first serial, iclass 5, count 0 2006.285.10:41:39.41#ibcon#enter sib2, iclass 5, count 0 2006.285.10:41:39.41#ibcon#flushed, iclass 5, count 0 2006.285.10:41:39.41#ibcon#about to write, iclass 5, count 0 2006.285.10:41:39.41#ibcon#wrote, iclass 5, count 0 2006.285.10:41:39.41#ibcon#about to read 3, iclass 5, count 0 2006.285.10:41:39.43#ibcon#read 3, iclass 5, count 0 2006.285.10:41:39.43#ibcon#about to read 4, iclass 5, count 0 2006.285.10:41:39.43#ibcon#read 4, iclass 5, count 0 2006.285.10:41:39.43#ibcon#about to read 5, iclass 5, count 0 2006.285.10:41:39.43#ibcon#read 5, iclass 5, count 0 2006.285.10:41:39.43#ibcon#about to read 6, iclass 5, count 0 2006.285.10:41:39.43#ibcon#read 6, iclass 5, count 0 2006.285.10:41:39.43#ibcon#end of sib2, iclass 5, count 0 2006.285.10:41:39.43#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:41:39.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:41:39.43#ibcon#[25=BW32\r\n] 2006.285.10:41:39.43#ibcon#*before write, iclass 5, count 0 2006.285.10:41:39.43#ibcon#enter sib2, iclass 5, count 0 2006.285.10:41:39.43#ibcon#flushed, iclass 5, count 0 2006.285.10:41:39.43#ibcon#about to write, iclass 5, count 0 2006.285.10:41:39.43#ibcon#wrote, iclass 5, count 0 2006.285.10:41:39.43#ibcon#about to read 3, iclass 5, count 0 2006.285.10:41:39.46#ibcon#read 3, iclass 5, count 0 2006.285.10:41:39.46#ibcon#about to read 4, iclass 5, count 0 2006.285.10:41:39.46#ibcon#read 4, iclass 5, count 0 2006.285.10:41:39.46#ibcon#about to read 5, iclass 5, count 0 2006.285.10:41:39.46#ibcon#read 5, iclass 5, count 0 2006.285.10:41:39.46#ibcon#about to read 6, iclass 5, count 0 2006.285.10:41:39.46#ibcon#read 6, iclass 5, count 0 2006.285.10:41:39.46#ibcon#end of sib2, iclass 5, count 0 2006.285.10:41:39.46#ibcon#*after write, iclass 5, count 0 2006.285.10:41:39.46#ibcon#*before return 0, iclass 5, count 0 2006.285.10:41:39.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:41:39.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.10:41:39.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:41:39.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:41:39.46$vck44/vbbw=wide 2006.285.10:41:39.46#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.10:41:39.46#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.10:41:39.46#ibcon#ireg 8 cls_cnt 0 2006.285.10:41:39.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:41:39.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:41:39.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:41:39.53#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:41:39.53#ibcon#first serial, iclass 7, count 0 2006.285.10:41:39.53#ibcon#enter sib2, iclass 7, count 0 2006.285.10:41:39.53#ibcon#flushed, iclass 7, count 0 2006.285.10:41:39.53#ibcon#about to write, iclass 7, count 0 2006.285.10:41:39.53#ibcon#wrote, iclass 7, count 0 2006.285.10:41:39.53#ibcon#about to read 3, iclass 7, count 0 2006.285.10:41:39.55#ibcon#read 3, iclass 7, count 0 2006.285.10:41:39.55#ibcon#about to read 4, iclass 7, count 0 2006.285.10:41:39.55#ibcon#read 4, iclass 7, count 0 2006.285.10:41:39.55#ibcon#about to read 5, iclass 7, count 0 2006.285.10:41:39.55#ibcon#read 5, iclass 7, count 0 2006.285.10:41:39.55#ibcon#about to read 6, iclass 7, count 0 2006.285.10:41:39.55#ibcon#read 6, iclass 7, count 0 2006.285.10:41:39.55#ibcon#end of sib2, iclass 7, count 0 2006.285.10:41:39.55#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:41:39.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:41:39.55#ibcon#[27=BW32\r\n] 2006.285.10:41:39.55#ibcon#*before write, iclass 7, count 0 2006.285.10:41:39.55#ibcon#enter sib2, iclass 7, count 0 2006.285.10:41:39.55#ibcon#flushed, iclass 7, count 0 2006.285.10:41:39.55#ibcon#about to write, iclass 7, count 0 2006.285.10:41:39.55#ibcon#wrote, iclass 7, count 0 2006.285.10:41:39.55#ibcon#about to read 3, iclass 7, count 0 2006.285.10:41:39.58#ibcon#read 3, iclass 7, count 0 2006.285.10:41:39.58#ibcon#about to read 4, iclass 7, count 0 2006.285.10:41:39.58#ibcon#read 4, iclass 7, count 0 2006.285.10:41:39.58#ibcon#about to read 5, iclass 7, count 0 2006.285.10:41:39.58#ibcon#read 5, iclass 7, count 0 2006.285.10:41:39.58#ibcon#about to read 6, iclass 7, count 0 2006.285.10:41:39.58#ibcon#read 6, iclass 7, count 0 2006.285.10:41:39.58#ibcon#end of sib2, iclass 7, count 0 2006.285.10:41:39.58#ibcon#*after write, iclass 7, count 0 2006.285.10:41:39.58#ibcon#*before return 0, iclass 7, count 0 2006.285.10:41:39.58#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:41:39.58#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:41:39.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:41:39.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:41:39.58$setupk4/ifdk4 2006.285.10:41:39.58$ifdk4/lo= 2006.285.10:41:39.59$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:41:39.59$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:41:39.59$ifdk4/patch= 2006.285.10:41:39.59$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:41:39.59$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:41:39.59$setupk4/!*+20s 2006.285.10:41:40.39#abcon#<5=/05 1.4 2.5 19.69 921015.0\r\n> 2006.285.10:41:40.41#abcon#{5=INTERFACE CLEAR} 2006.285.10:41:40.47#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:41:46.14#trakl#Source acquired 2006.285.10:41:46.14#flagr#flagr/antenna,acquired 2006.285.10:41:50.65#abcon#<5=/05 1.4 2.6 19.69 921015.0\r\n> 2006.285.10:41:50.67#abcon#{5=INTERFACE CLEAR} 2006.285.10:41:50.73#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:41:54.11$setupk4/"tpicd 2006.285.10:41:54.11$setupk4/echo=off 2006.285.10:41:54.11$setupk4/xlog=off 2006.285.10:41:54.11:!2006.285.10:43:48 2006.285.10:43:48.00:preob 2006.285.10:43:48.14/onsource/TRACKING 2006.285.10:43:48.14:!2006.285.10:43:58 2006.285.10:43:58.00:"tape 2006.285.10:43:58.00:"st=record 2006.285.10:43:58.00:data_valid=on 2006.285.10:43:58.00:midob 2006.285.10:43:58.14/onsource/TRACKING 2006.285.10:43:58.14/wx/19.67,1015.0,92 2006.285.10:43:58.35/cable/+6.4869E-03 2006.285.10:43:59.44/va/01,07,usb,yes,31,34 2006.285.10:43:59.44/va/02,06,usb,yes,31,32 2006.285.10:43:59.44/va/03,07,usb,yes,31,33 2006.285.10:43:59.44/va/04,06,usb,yes,32,34 2006.285.10:43:59.44/va/05,03,usb,yes,32,32 2006.285.10:43:59.44/va/06,04,usb,yes,29,28 2006.285.10:43:59.44/va/07,04,usb,yes,29,30 2006.285.10:43:59.44/va/08,03,usb,yes,30,36 2006.285.10:43:59.67/valo/01,524.99,yes,locked 2006.285.10:43:59.67/valo/02,534.99,yes,locked 2006.285.10:43:59.67/valo/03,564.99,yes,locked 2006.285.10:43:59.67/valo/04,624.99,yes,locked 2006.285.10:43:59.67/valo/05,734.99,yes,locked 2006.285.10:43:59.67/valo/06,814.99,yes,locked 2006.285.10:43:59.67/valo/07,864.99,yes,locked 2006.285.10:43:59.67/valo/08,884.99,yes,locked 2006.285.10:44:00.76/vb/01,04,usb,yes,30,28 2006.285.10:44:00.76/vb/02,05,usb,yes,28,28 2006.285.10:44:00.76/vb/03,04,usb,yes,29,32 2006.285.10:44:00.76/vb/04,05,usb,yes,29,28 2006.285.10:44:00.76/vb/05,04,usb,yes,26,28 2006.285.10:44:00.76/vb/06,03,usb,yes,37,33 2006.285.10:44:00.76/vb/07,04,usb,yes,30,30 2006.285.10:44:00.76/vb/08,04,usb,yes,27,31 2006.285.10:44:00.99/vblo/01,629.99,yes,locked 2006.285.10:44:00.99/vblo/02,634.99,yes,locked 2006.285.10:44:00.99/vblo/03,649.99,yes,locked 2006.285.10:44:00.99/vblo/04,679.99,yes,locked 2006.285.10:44:00.99/vblo/05,709.99,yes,locked 2006.285.10:44:00.99/vblo/06,719.99,yes,locked 2006.285.10:44:00.99/vblo/07,734.99,yes,locked 2006.285.10:44:00.99/vblo/08,744.99,yes,locked 2006.285.10:44:01.14/vabw/8 2006.285.10:44:01.29/vbbw/8 2006.285.10:44:01.38/xfe/off,on,12.2 2006.285.10:44:01.75/ifatt/23,28,28,28 2006.285.10:44:02.07/fmout-gps/S +2.77E-07 2006.285.10:44:02.09:!2006.285.10:45:08 2006.285.10:45:08.00:data_valid=off 2006.285.10:45:08.00:"et 2006.285.10:45:08.00:!+3s 2006.285.10:45:11.01:"tape 2006.285.10:45:11.01:postob 2006.285.10:45:11.11/cable/+6.4869E-03 2006.285.10:45:11.11/wx/19.66,1015.0,92 2006.285.10:45:12.07/fmout-gps/S +2.78E-07 2006.285.10:45:12.07:scan_name=285-1049,jd0610,40 2006.285.10:45:12.07:source=1954-388,195800.00,-384506.4,2000.0,cw 2006.285.10:45:13.14#flagr#flagr/antenna,new-source 2006.285.10:45:13.14:checkk5 2006.285.10:45:13.48/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:45:13.84/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:45:14.22/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:45:14.62/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:45:14.99/chk_obsdata//k5ts1/T2851043??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:45:15.40/chk_obsdata//k5ts2/T2851043??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:45:15.77/chk_obsdata//k5ts3/T2851043??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:45:16.16/chk_obsdata//k5ts4/T2851043??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.10:45:16.97/k5log//k5ts1_log_newline 2006.285.10:45:17.75/k5log//k5ts2_log_newline 2006.285.10:45:18.75/k5log//k5ts3_log_newline 2006.285.10:45:19.76/k5log//k5ts4_log_newline 2006.285.10:45:19.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:45:19.79:setupk4=1 2006.285.10:45:19.79$setupk4/echo=on 2006.285.10:45:19.79$setupk4/pcalon 2006.285.10:45:19.79$pcalon/"no phase cal control is implemented here 2006.285.10:45:19.79$setupk4/"tpicd=stop 2006.285.10:45:19.79$setupk4/"rec=synch_on 2006.285.10:45:19.79$setupk4/"rec_mode=128 2006.285.10:45:19.79$setupk4/!* 2006.285.10:45:19.79$setupk4/recpk4 2006.285.10:45:19.79$recpk4/recpatch= 2006.285.10:45:19.79$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:45:19.79$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:45:19.79$setupk4/vck44 2006.285.10:45:19.79$vck44/valo=1,524.99 2006.285.10:45:19.79#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.10:45:19.79#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.10:45:19.79#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:19.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:45:19.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:45:19.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:45:19.79#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:45:19.79#ibcon#first serial, iclass 30, count 0 2006.285.10:45:19.79#ibcon#enter sib2, iclass 30, count 0 2006.285.10:45:19.79#ibcon#flushed, iclass 30, count 0 2006.285.10:45:19.79#ibcon#about to write, iclass 30, count 0 2006.285.10:45:19.79#ibcon#wrote, iclass 30, count 0 2006.285.10:45:19.79#ibcon#about to read 3, iclass 30, count 0 2006.285.10:45:19.81#ibcon#read 3, iclass 30, count 0 2006.285.10:45:19.81#ibcon#about to read 4, iclass 30, count 0 2006.285.10:45:19.81#ibcon#read 4, iclass 30, count 0 2006.285.10:45:19.81#ibcon#about to read 5, iclass 30, count 0 2006.285.10:45:19.81#ibcon#read 5, iclass 30, count 0 2006.285.10:45:19.81#ibcon#about to read 6, iclass 30, count 0 2006.285.10:45:19.81#ibcon#read 6, iclass 30, count 0 2006.285.10:45:19.81#ibcon#end of sib2, iclass 30, count 0 2006.285.10:45:19.81#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:45:19.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:45:19.81#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:45:19.81#ibcon#*before write, iclass 30, count 0 2006.285.10:45:19.81#ibcon#enter sib2, iclass 30, count 0 2006.285.10:45:19.81#ibcon#flushed, iclass 30, count 0 2006.285.10:45:19.81#ibcon#about to write, iclass 30, count 0 2006.285.10:45:19.81#ibcon#wrote, iclass 30, count 0 2006.285.10:45:19.81#ibcon#about to read 3, iclass 30, count 0 2006.285.10:45:19.86#ibcon#read 3, iclass 30, count 0 2006.285.10:45:19.86#ibcon#about to read 4, iclass 30, count 0 2006.285.10:45:19.86#ibcon#read 4, iclass 30, count 0 2006.285.10:45:19.86#ibcon#about to read 5, iclass 30, count 0 2006.285.10:45:19.86#ibcon#read 5, iclass 30, count 0 2006.285.10:45:19.86#ibcon#about to read 6, iclass 30, count 0 2006.285.10:45:19.86#ibcon#read 6, iclass 30, count 0 2006.285.10:45:19.86#ibcon#end of sib2, iclass 30, count 0 2006.285.10:45:19.86#ibcon#*after write, iclass 30, count 0 2006.285.10:45:19.86#ibcon#*before return 0, iclass 30, count 0 2006.285.10:45:19.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:45:19.86#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:45:19.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:45:19.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:45:19.86$vck44/va=1,7 2006.285.10:45:19.86#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.10:45:19.86#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.10:45:19.86#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:19.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:45:19.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:45:19.86#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:45:19.86#ibcon#enter wrdev, iclass 32, count 2 2006.285.10:45:19.86#ibcon#first serial, iclass 32, count 2 2006.285.10:45:19.86#ibcon#enter sib2, iclass 32, count 2 2006.285.10:45:19.86#ibcon#flushed, iclass 32, count 2 2006.285.10:45:19.86#ibcon#about to write, iclass 32, count 2 2006.285.10:45:19.86#ibcon#wrote, iclass 32, count 2 2006.285.10:45:19.86#ibcon#about to read 3, iclass 32, count 2 2006.285.10:45:19.88#ibcon#read 3, iclass 32, count 2 2006.285.10:45:19.88#ibcon#about to read 4, iclass 32, count 2 2006.285.10:45:19.88#ibcon#read 4, iclass 32, count 2 2006.285.10:45:19.88#ibcon#about to read 5, iclass 32, count 2 2006.285.10:45:19.88#ibcon#read 5, iclass 32, count 2 2006.285.10:45:19.88#ibcon#about to read 6, iclass 32, count 2 2006.285.10:45:19.88#ibcon#read 6, iclass 32, count 2 2006.285.10:45:19.88#ibcon#end of sib2, iclass 32, count 2 2006.285.10:45:19.88#ibcon#*mode == 0, iclass 32, count 2 2006.285.10:45:19.88#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.10:45:19.88#ibcon#[25=AT01-07\r\n] 2006.285.10:45:19.88#ibcon#*before write, iclass 32, count 2 2006.285.10:45:19.88#ibcon#enter sib2, iclass 32, count 2 2006.285.10:45:19.88#ibcon#flushed, iclass 32, count 2 2006.285.10:45:19.88#ibcon#about to write, iclass 32, count 2 2006.285.10:45:19.88#ibcon#wrote, iclass 32, count 2 2006.285.10:45:19.88#ibcon#about to read 3, iclass 32, count 2 2006.285.10:45:19.91#ibcon#read 3, iclass 32, count 2 2006.285.10:45:19.91#ibcon#about to read 4, iclass 32, count 2 2006.285.10:45:19.91#ibcon#read 4, iclass 32, count 2 2006.285.10:45:19.91#ibcon#about to read 5, iclass 32, count 2 2006.285.10:45:19.91#ibcon#read 5, iclass 32, count 2 2006.285.10:45:19.91#ibcon#about to read 6, iclass 32, count 2 2006.285.10:45:19.91#ibcon#read 6, iclass 32, count 2 2006.285.10:45:19.91#ibcon#end of sib2, iclass 32, count 2 2006.285.10:45:19.91#ibcon#*after write, iclass 32, count 2 2006.285.10:45:19.91#ibcon#*before return 0, iclass 32, count 2 2006.285.10:45:19.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:45:19.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:45:19.91#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.10:45:19.91#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:19.91#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:45:20.03#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:45:20.03#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:45:20.03#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:45:20.03#ibcon#first serial, iclass 32, count 0 2006.285.10:45:20.03#ibcon#enter sib2, iclass 32, count 0 2006.285.10:45:20.03#ibcon#flushed, iclass 32, count 0 2006.285.10:45:20.03#ibcon#about to write, iclass 32, count 0 2006.285.10:45:20.03#ibcon#wrote, iclass 32, count 0 2006.285.10:45:20.03#ibcon#about to read 3, iclass 32, count 0 2006.285.10:45:20.05#ibcon#read 3, iclass 32, count 0 2006.285.10:45:20.05#ibcon#about to read 4, iclass 32, count 0 2006.285.10:45:20.05#ibcon#read 4, iclass 32, count 0 2006.285.10:45:20.05#ibcon#about to read 5, iclass 32, count 0 2006.285.10:45:20.05#ibcon#read 5, iclass 32, count 0 2006.285.10:45:20.05#ibcon#about to read 6, iclass 32, count 0 2006.285.10:45:20.05#ibcon#read 6, iclass 32, count 0 2006.285.10:45:20.05#ibcon#end of sib2, iclass 32, count 0 2006.285.10:45:20.05#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:45:20.05#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:45:20.05#ibcon#[25=USB\r\n] 2006.285.10:45:20.05#ibcon#*before write, iclass 32, count 0 2006.285.10:45:20.05#ibcon#enter sib2, iclass 32, count 0 2006.285.10:45:20.05#ibcon#flushed, iclass 32, count 0 2006.285.10:45:20.05#ibcon#about to write, iclass 32, count 0 2006.285.10:45:20.05#ibcon#wrote, iclass 32, count 0 2006.285.10:45:20.05#ibcon#about to read 3, iclass 32, count 0 2006.285.10:45:20.08#ibcon#read 3, iclass 32, count 0 2006.285.10:45:20.08#ibcon#about to read 4, iclass 32, count 0 2006.285.10:45:20.08#ibcon#read 4, iclass 32, count 0 2006.285.10:45:20.08#ibcon#about to read 5, iclass 32, count 0 2006.285.10:45:20.08#ibcon#read 5, iclass 32, count 0 2006.285.10:45:20.08#ibcon#about to read 6, iclass 32, count 0 2006.285.10:45:20.08#ibcon#read 6, iclass 32, count 0 2006.285.10:45:20.08#ibcon#end of sib2, iclass 32, count 0 2006.285.10:45:20.08#ibcon#*after write, iclass 32, count 0 2006.285.10:45:20.08#ibcon#*before return 0, iclass 32, count 0 2006.285.10:45:20.08#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:45:20.08#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:45:20.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:45:20.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:45:20.08$vck44/valo=2,534.99 2006.285.10:45:20.08#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.10:45:20.08#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.10:45:20.08#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:20.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:45:20.08#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:45:20.08#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:45:20.08#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:45:20.08#ibcon#first serial, iclass 34, count 0 2006.285.10:45:20.08#ibcon#enter sib2, iclass 34, count 0 2006.285.10:45:20.08#ibcon#flushed, iclass 34, count 0 2006.285.10:45:20.08#ibcon#about to write, iclass 34, count 0 2006.285.10:45:20.08#ibcon#wrote, iclass 34, count 0 2006.285.10:45:20.08#ibcon#about to read 3, iclass 34, count 0 2006.285.10:45:20.10#ibcon#read 3, iclass 34, count 0 2006.285.10:45:20.10#ibcon#about to read 4, iclass 34, count 0 2006.285.10:45:20.10#ibcon#read 4, iclass 34, count 0 2006.285.10:45:20.10#ibcon#about to read 5, iclass 34, count 0 2006.285.10:45:20.10#ibcon#read 5, iclass 34, count 0 2006.285.10:45:20.10#ibcon#about to read 6, iclass 34, count 0 2006.285.10:45:20.10#ibcon#read 6, iclass 34, count 0 2006.285.10:45:20.10#ibcon#end of sib2, iclass 34, count 0 2006.285.10:45:20.10#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:45:20.10#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:45:20.10#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:45:20.10#ibcon#*before write, iclass 34, count 0 2006.285.10:45:20.10#ibcon#enter sib2, iclass 34, count 0 2006.285.10:45:20.10#ibcon#flushed, iclass 34, count 0 2006.285.10:45:20.10#ibcon#about to write, iclass 34, count 0 2006.285.10:45:20.10#ibcon#wrote, iclass 34, count 0 2006.285.10:45:20.10#ibcon#about to read 3, iclass 34, count 0 2006.285.10:45:20.14#ibcon#read 3, iclass 34, count 0 2006.285.10:45:20.14#ibcon#about to read 4, iclass 34, count 0 2006.285.10:45:20.14#ibcon#read 4, iclass 34, count 0 2006.285.10:45:20.14#ibcon#about to read 5, iclass 34, count 0 2006.285.10:45:20.14#ibcon#read 5, iclass 34, count 0 2006.285.10:45:20.14#ibcon#about to read 6, iclass 34, count 0 2006.285.10:45:20.14#ibcon#read 6, iclass 34, count 0 2006.285.10:45:20.14#ibcon#end of sib2, iclass 34, count 0 2006.285.10:45:20.14#ibcon#*after write, iclass 34, count 0 2006.285.10:45:20.14#ibcon#*before return 0, iclass 34, count 0 2006.285.10:45:20.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:45:20.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:45:20.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:45:20.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:45:20.14$vck44/va=2,6 2006.285.10:45:20.14#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.10:45:20.14#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.10:45:20.14#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:20.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:45:20.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:45:20.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:45:20.20#ibcon#enter wrdev, iclass 36, count 2 2006.285.10:45:20.20#ibcon#first serial, iclass 36, count 2 2006.285.10:45:20.20#ibcon#enter sib2, iclass 36, count 2 2006.285.10:45:20.20#ibcon#flushed, iclass 36, count 2 2006.285.10:45:20.20#ibcon#about to write, iclass 36, count 2 2006.285.10:45:20.20#ibcon#wrote, iclass 36, count 2 2006.285.10:45:20.20#ibcon#about to read 3, iclass 36, count 2 2006.285.10:45:20.22#ibcon#read 3, iclass 36, count 2 2006.285.10:45:20.22#ibcon#about to read 4, iclass 36, count 2 2006.285.10:45:20.22#ibcon#read 4, iclass 36, count 2 2006.285.10:45:20.22#ibcon#about to read 5, iclass 36, count 2 2006.285.10:45:20.22#ibcon#read 5, iclass 36, count 2 2006.285.10:45:20.22#ibcon#about to read 6, iclass 36, count 2 2006.285.10:45:20.22#ibcon#read 6, iclass 36, count 2 2006.285.10:45:20.22#ibcon#end of sib2, iclass 36, count 2 2006.285.10:45:20.22#ibcon#*mode == 0, iclass 36, count 2 2006.285.10:45:20.22#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.10:45:20.22#ibcon#[25=AT02-06\r\n] 2006.285.10:45:20.22#ibcon#*before write, iclass 36, count 2 2006.285.10:45:20.22#ibcon#enter sib2, iclass 36, count 2 2006.285.10:45:20.22#ibcon#flushed, iclass 36, count 2 2006.285.10:45:20.22#ibcon#about to write, iclass 36, count 2 2006.285.10:45:20.22#ibcon#wrote, iclass 36, count 2 2006.285.10:45:20.22#ibcon#about to read 3, iclass 36, count 2 2006.285.10:45:20.25#ibcon#read 3, iclass 36, count 2 2006.285.10:45:20.25#ibcon#about to read 4, iclass 36, count 2 2006.285.10:45:20.25#ibcon#read 4, iclass 36, count 2 2006.285.10:45:20.25#ibcon#about to read 5, iclass 36, count 2 2006.285.10:45:20.25#ibcon#read 5, iclass 36, count 2 2006.285.10:45:20.25#ibcon#about to read 6, iclass 36, count 2 2006.285.10:45:20.25#ibcon#read 6, iclass 36, count 2 2006.285.10:45:20.25#ibcon#end of sib2, iclass 36, count 2 2006.285.10:45:20.25#ibcon#*after write, iclass 36, count 2 2006.285.10:45:20.25#ibcon#*before return 0, iclass 36, count 2 2006.285.10:45:20.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:45:20.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:45:20.25#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.10:45:20.25#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:20.25#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:45:20.37#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:45:20.37#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:45:20.37#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:45:20.37#ibcon#first serial, iclass 36, count 0 2006.285.10:45:20.37#ibcon#enter sib2, iclass 36, count 0 2006.285.10:45:20.37#ibcon#flushed, iclass 36, count 0 2006.285.10:45:20.37#ibcon#about to write, iclass 36, count 0 2006.285.10:45:20.37#ibcon#wrote, iclass 36, count 0 2006.285.10:45:20.37#ibcon#about to read 3, iclass 36, count 0 2006.285.10:45:20.39#ibcon#read 3, iclass 36, count 0 2006.285.10:45:20.39#ibcon#about to read 4, iclass 36, count 0 2006.285.10:45:20.39#ibcon#read 4, iclass 36, count 0 2006.285.10:45:20.39#ibcon#about to read 5, iclass 36, count 0 2006.285.10:45:20.39#ibcon#read 5, iclass 36, count 0 2006.285.10:45:20.39#ibcon#about to read 6, iclass 36, count 0 2006.285.10:45:20.39#ibcon#read 6, iclass 36, count 0 2006.285.10:45:20.39#ibcon#end of sib2, iclass 36, count 0 2006.285.10:45:20.39#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:45:20.39#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:45:20.39#ibcon#[25=USB\r\n] 2006.285.10:45:20.39#ibcon#*before write, iclass 36, count 0 2006.285.10:45:20.39#ibcon#enter sib2, iclass 36, count 0 2006.285.10:45:20.39#ibcon#flushed, iclass 36, count 0 2006.285.10:45:20.39#ibcon#about to write, iclass 36, count 0 2006.285.10:45:20.39#ibcon#wrote, iclass 36, count 0 2006.285.10:45:20.39#ibcon#about to read 3, iclass 36, count 0 2006.285.10:45:20.42#ibcon#read 3, iclass 36, count 0 2006.285.10:45:20.42#ibcon#about to read 4, iclass 36, count 0 2006.285.10:45:20.42#ibcon#read 4, iclass 36, count 0 2006.285.10:45:20.42#ibcon#about to read 5, iclass 36, count 0 2006.285.10:45:20.42#ibcon#read 5, iclass 36, count 0 2006.285.10:45:20.42#ibcon#about to read 6, iclass 36, count 0 2006.285.10:45:20.42#ibcon#read 6, iclass 36, count 0 2006.285.10:45:20.42#ibcon#end of sib2, iclass 36, count 0 2006.285.10:45:20.42#ibcon#*after write, iclass 36, count 0 2006.285.10:45:20.42#ibcon#*before return 0, iclass 36, count 0 2006.285.10:45:20.42#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:45:20.42#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:45:20.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:45:20.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:45:20.42$vck44/valo=3,564.99 2006.285.10:45:20.42#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.10:45:20.42#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.10:45:20.42#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:20.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:45:20.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:45:20.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:45:20.42#ibcon#enter wrdev, iclass 38, count 0 2006.285.10:45:20.42#ibcon#first serial, iclass 38, count 0 2006.285.10:45:20.42#ibcon#enter sib2, iclass 38, count 0 2006.285.10:45:20.42#ibcon#flushed, iclass 38, count 0 2006.285.10:45:20.42#ibcon#about to write, iclass 38, count 0 2006.285.10:45:20.42#ibcon#wrote, iclass 38, count 0 2006.285.10:45:20.42#ibcon#about to read 3, iclass 38, count 0 2006.285.10:45:20.44#ibcon#read 3, iclass 38, count 0 2006.285.10:45:20.44#ibcon#about to read 4, iclass 38, count 0 2006.285.10:45:20.44#ibcon#read 4, iclass 38, count 0 2006.285.10:45:20.44#ibcon#about to read 5, iclass 38, count 0 2006.285.10:45:20.44#ibcon#read 5, iclass 38, count 0 2006.285.10:45:20.44#ibcon#about to read 6, iclass 38, count 0 2006.285.10:45:20.44#ibcon#read 6, iclass 38, count 0 2006.285.10:45:20.44#ibcon#end of sib2, iclass 38, count 0 2006.285.10:45:20.44#ibcon#*mode == 0, iclass 38, count 0 2006.285.10:45:20.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.10:45:20.44#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:45:20.44#ibcon#*before write, iclass 38, count 0 2006.285.10:45:20.44#ibcon#enter sib2, iclass 38, count 0 2006.285.10:45:20.44#ibcon#flushed, iclass 38, count 0 2006.285.10:45:20.44#ibcon#about to write, iclass 38, count 0 2006.285.10:45:20.44#ibcon#wrote, iclass 38, count 0 2006.285.10:45:20.44#ibcon#about to read 3, iclass 38, count 0 2006.285.10:45:20.48#ibcon#read 3, iclass 38, count 0 2006.285.10:45:20.48#ibcon#about to read 4, iclass 38, count 0 2006.285.10:45:20.48#ibcon#read 4, iclass 38, count 0 2006.285.10:45:20.48#ibcon#about to read 5, iclass 38, count 0 2006.285.10:45:20.48#ibcon#read 5, iclass 38, count 0 2006.285.10:45:20.48#ibcon#about to read 6, iclass 38, count 0 2006.285.10:45:20.48#ibcon#read 6, iclass 38, count 0 2006.285.10:45:20.48#ibcon#end of sib2, iclass 38, count 0 2006.285.10:45:20.48#ibcon#*after write, iclass 38, count 0 2006.285.10:45:20.48#ibcon#*before return 0, iclass 38, count 0 2006.285.10:45:20.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:45:20.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:45:20.48#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.10:45:20.48#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.10:45:20.48$vck44/va=3,7 2006.285.10:45:20.48#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.10:45:20.48#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.10:45:20.48#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:20.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:45:20.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:45:20.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:45:20.54#ibcon#enter wrdev, iclass 40, count 2 2006.285.10:45:20.54#ibcon#first serial, iclass 40, count 2 2006.285.10:45:20.54#ibcon#enter sib2, iclass 40, count 2 2006.285.10:45:20.54#ibcon#flushed, iclass 40, count 2 2006.285.10:45:20.54#ibcon#about to write, iclass 40, count 2 2006.285.10:45:20.54#ibcon#wrote, iclass 40, count 2 2006.285.10:45:20.54#ibcon#about to read 3, iclass 40, count 2 2006.285.10:45:20.56#ibcon#read 3, iclass 40, count 2 2006.285.10:45:20.56#ibcon#about to read 4, iclass 40, count 2 2006.285.10:45:20.56#ibcon#read 4, iclass 40, count 2 2006.285.10:45:20.56#ibcon#about to read 5, iclass 40, count 2 2006.285.10:45:20.56#ibcon#read 5, iclass 40, count 2 2006.285.10:45:20.56#ibcon#about to read 6, iclass 40, count 2 2006.285.10:45:20.56#ibcon#read 6, iclass 40, count 2 2006.285.10:45:20.56#ibcon#end of sib2, iclass 40, count 2 2006.285.10:45:20.56#ibcon#*mode == 0, iclass 40, count 2 2006.285.10:45:20.56#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.10:45:20.56#ibcon#[25=AT03-07\r\n] 2006.285.10:45:20.56#ibcon#*before write, iclass 40, count 2 2006.285.10:45:20.56#ibcon#enter sib2, iclass 40, count 2 2006.285.10:45:20.56#ibcon#flushed, iclass 40, count 2 2006.285.10:45:20.56#ibcon#about to write, iclass 40, count 2 2006.285.10:45:20.56#ibcon#wrote, iclass 40, count 2 2006.285.10:45:20.56#ibcon#about to read 3, iclass 40, count 2 2006.285.10:45:20.59#ibcon#read 3, iclass 40, count 2 2006.285.10:45:20.59#ibcon#about to read 4, iclass 40, count 2 2006.285.10:45:20.59#ibcon#read 4, iclass 40, count 2 2006.285.10:45:20.59#ibcon#about to read 5, iclass 40, count 2 2006.285.10:45:20.59#ibcon#read 5, iclass 40, count 2 2006.285.10:45:20.59#ibcon#about to read 6, iclass 40, count 2 2006.285.10:45:20.59#ibcon#read 6, iclass 40, count 2 2006.285.10:45:20.59#ibcon#end of sib2, iclass 40, count 2 2006.285.10:45:20.59#ibcon#*after write, iclass 40, count 2 2006.285.10:45:20.59#ibcon#*before return 0, iclass 40, count 2 2006.285.10:45:20.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:45:20.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:45:20.59#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.10:45:20.59#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:20.59#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:45:20.71#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:45:20.71#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:45:20.71#ibcon#enter wrdev, iclass 40, count 0 2006.285.10:45:20.71#ibcon#first serial, iclass 40, count 0 2006.285.10:45:20.71#ibcon#enter sib2, iclass 40, count 0 2006.285.10:45:20.71#ibcon#flushed, iclass 40, count 0 2006.285.10:45:20.71#ibcon#about to write, iclass 40, count 0 2006.285.10:45:20.71#ibcon#wrote, iclass 40, count 0 2006.285.10:45:20.71#ibcon#about to read 3, iclass 40, count 0 2006.285.10:45:20.73#ibcon#read 3, iclass 40, count 0 2006.285.10:45:20.73#ibcon#about to read 4, iclass 40, count 0 2006.285.10:45:20.73#ibcon#read 4, iclass 40, count 0 2006.285.10:45:20.73#ibcon#about to read 5, iclass 40, count 0 2006.285.10:45:20.73#ibcon#read 5, iclass 40, count 0 2006.285.10:45:20.73#ibcon#about to read 6, iclass 40, count 0 2006.285.10:45:20.73#ibcon#read 6, iclass 40, count 0 2006.285.10:45:20.73#ibcon#end of sib2, iclass 40, count 0 2006.285.10:45:20.73#ibcon#*mode == 0, iclass 40, count 0 2006.285.10:45:20.73#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.10:45:20.73#ibcon#[25=USB\r\n] 2006.285.10:45:20.73#ibcon#*before write, iclass 40, count 0 2006.285.10:45:20.73#ibcon#enter sib2, iclass 40, count 0 2006.285.10:45:20.73#ibcon#flushed, iclass 40, count 0 2006.285.10:45:20.73#ibcon#about to write, iclass 40, count 0 2006.285.10:45:20.73#ibcon#wrote, iclass 40, count 0 2006.285.10:45:20.73#ibcon#about to read 3, iclass 40, count 0 2006.285.10:45:20.76#ibcon#read 3, iclass 40, count 0 2006.285.10:45:20.76#ibcon#about to read 4, iclass 40, count 0 2006.285.10:45:20.76#ibcon#read 4, iclass 40, count 0 2006.285.10:45:20.76#ibcon#about to read 5, iclass 40, count 0 2006.285.10:45:20.76#ibcon#read 5, iclass 40, count 0 2006.285.10:45:20.76#ibcon#about to read 6, iclass 40, count 0 2006.285.10:45:20.76#ibcon#read 6, iclass 40, count 0 2006.285.10:45:20.76#ibcon#end of sib2, iclass 40, count 0 2006.285.10:45:20.76#ibcon#*after write, iclass 40, count 0 2006.285.10:45:20.76#ibcon#*before return 0, iclass 40, count 0 2006.285.10:45:20.76#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:45:20.76#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:45:20.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.10:45:20.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.10:45:20.76$vck44/valo=4,624.99 2006.285.10:45:20.76#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.10:45:20.76#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.10:45:20.76#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:20.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:45:20.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:45:20.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:45:20.76#ibcon#enter wrdev, iclass 4, count 0 2006.285.10:45:20.76#ibcon#first serial, iclass 4, count 0 2006.285.10:45:20.76#ibcon#enter sib2, iclass 4, count 0 2006.285.10:45:20.76#ibcon#flushed, iclass 4, count 0 2006.285.10:45:20.76#ibcon#about to write, iclass 4, count 0 2006.285.10:45:20.76#ibcon#wrote, iclass 4, count 0 2006.285.10:45:20.76#ibcon#about to read 3, iclass 4, count 0 2006.285.10:45:20.78#ibcon#read 3, iclass 4, count 0 2006.285.10:45:20.78#ibcon#about to read 4, iclass 4, count 0 2006.285.10:45:20.78#ibcon#read 4, iclass 4, count 0 2006.285.10:45:20.78#ibcon#about to read 5, iclass 4, count 0 2006.285.10:45:20.78#ibcon#read 5, iclass 4, count 0 2006.285.10:45:20.78#ibcon#about to read 6, iclass 4, count 0 2006.285.10:45:20.78#ibcon#read 6, iclass 4, count 0 2006.285.10:45:20.78#ibcon#end of sib2, iclass 4, count 0 2006.285.10:45:20.78#ibcon#*mode == 0, iclass 4, count 0 2006.285.10:45:20.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.10:45:20.78#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:45:20.78#ibcon#*before write, iclass 4, count 0 2006.285.10:45:20.78#ibcon#enter sib2, iclass 4, count 0 2006.285.10:45:20.78#ibcon#flushed, iclass 4, count 0 2006.285.10:45:20.78#ibcon#about to write, iclass 4, count 0 2006.285.10:45:20.78#ibcon#wrote, iclass 4, count 0 2006.285.10:45:20.78#ibcon#about to read 3, iclass 4, count 0 2006.285.10:45:20.82#ibcon#read 3, iclass 4, count 0 2006.285.10:45:20.82#ibcon#about to read 4, iclass 4, count 0 2006.285.10:45:20.82#ibcon#read 4, iclass 4, count 0 2006.285.10:45:20.82#ibcon#about to read 5, iclass 4, count 0 2006.285.10:45:20.82#ibcon#read 5, iclass 4, count 0 2006.285.10:45:20.82#ibcon#about to read 6, iclass 4, count 0 2006.285.10:45:20.82#ibcon#read 6, iclass 4, count 0 2006.285.10:45:20.82#ibcon#end of sib2, iclass 4, count 0 2006.285.10:45:20.82#ibcon#*after write, iclass 4, count 0 2006.285.10:45:20.82#ibcon#*before return 0, iclass 4, count 0 2006.285.10:45:20.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:45:20.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:45:20.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.10:45:20.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.10:45:20.82$vck44/va=4,6 2006.285.10:45:20.82#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.10:45:20.82#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.10:45:20.82#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:20.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:45:20.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:45:20.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:45:20.88#ibcon#enter wrdev, iclass 6, count 2 2006.285.10:45:20.88#ibcon#first serial, iclass 6, count 2 2006.285.10:45:20.88#ibcon#enter sib2, iclass 6, count 2 2006.285.10:45:20.88#ibcon#flushed, iclass 6, count 2 2006.285.10:45:20.88#ibcon#about to write, iclass 6, count 2 2006.285.10:45:20.88#ibcon#wrote, iclass 6, count 2 2006.285.10:45:20.88#ibcon#about to read 3, iclass 6, count 2 2006.285.10:45:20.90#ibcon#read 3, iclass 6, count 2 2006.285.10:45:20.90#ibcon#about to read 4, iclass 6, count 2 2006.285.10:45:20.90#ibcon#read 4, iclass 6, count 2 2006.285.10:45:20.90#ibcon#about to read 5, iclass 6, count 2 2006.285.10:45:20.90#ibcon#read 5, iclass 6, count 2 2006.285.10:45:20.90#ibcon#about to read 6, iclass 6, count 2 2006.285.10:45:20.90#ibcon#read 6, iclass 6, count 2 2006.285.10:45:20.90#ibcon#end of sib2, iclass 6, count 2 2006.285.10:45:20.90#ibcon#*mode == 0, iclass 6, count 2 2006.285.10:45:20.90#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.10:45:20.90#ibcon#[25=AT04-06\r\n] 2006.285.10:45:20.90#ibcon#*before write, iclass 6, count 2 2006.285.10:45:20.90#ibcon#enter sib2, iclass 6, count 2 2006.285.10:45:20.90#ibcon#flushed, iclass 6, count 2 2006.285.10:45:20.90#ibcon#about to write, iclass 6, count 2 2006.285.10:45:20.90#ibcon#wrote, iclass 6, count 2 2006.285.10:45:20.90#ibcon#about to read 3, iclass 6, count 2 2006.285.10:45:20.93#ibcon#read 3, iclass 6, count 2 2006.285.10:45:20.93#ibcon#about to read 4, iclass 6, count 2 2006.285.10:45:20.93#ibcon#read 4, iclass 6, count 2 2006.285.10:45:20.93#ibcon#about to read 5, iclass 6, count 2 2006.285.10:45:20.93#ibcon#read 5, iclass 6, count 2 2006.285.10:45:20.93#ibcon#about to read 6, iclass 6, count 2 2006.285.10:45:20.93#ibcon#read 6, iclass 6, count 2 2006.285.10:45:20.93#ibcon#end of sib2, iclass 6, count 2 2006.285.10:45:20.93#ibcon#*after write, iclass 6, count 2 2006.285.10:45:20.93#ibcon#*before return 0, iclass 6, count 2 2006.285.10:45:20.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:45:20.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:45:20.93#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.10:45:20.93#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:20.93#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:45:21.05#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:45:21.05#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:45:21.05#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:45:21.05#ibcon#first serial, iclass 6, count 0 2006.285.10:45:21.05#ibcon#enter sib2, iclass 6, count 0 2006.285.10:45:21.05#ibcon#flushed, iclass 6, count 0 2006.285.10:45:21.05#ibcon#about to write, iclass 6, count 0 2006.285.10:45:21.05#ibcon#wrote, iclass 6, count 0 2006.285.10:45:21.05#ibcon#about to read 3, iclass 6, count 0 2006.285.10:45:21.07#ibcon#read 3, iclass 6, count 0 2006.285.10:45:21.07#ibcon#about to read 4, iclass 6, count 0 2006.285.10:45:21.07#ibcon#read 4, iclass 6, count 0 2006.285.10:45:21.07#ibcon#about to read 5, iclass 6, count 0 2006.285.10:45:21.07#ibcon#read 5, iclass 6, count 0 2006.285.10:45:21.07#ibcon#about to read 6, iclass 6, count 0 2006.285.10:45:21.07#ibcon#read 6, iclass 6, count 0 2006.285.10:45:21.07#ibcon#end of sib2, iclass 6, count 0 2006.285.10:45:21.07#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:45:21.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:45:21.07#ibcon#[25=USB\r\n] 2006.285.10:45:21.07#ibcon#*before write, iclass 6, count 0 2006.285.10:45:21.07#ibcon#enter sib2, iclass 6, count 0 2006.285.10:45:21.07#ibcon#flushed, iclass 6, count 0 2006.285.10:45:21.07#ibcon#about to write, iclass 6, count 0 2006.285.10:45:21.07#ibcon#wrote, iclass 6, count 0 2006.285.10:45:21.07#ibcon#about to read 3, iclass 6, count 0 2006.285.10:45:21.10#ibcon#read 3, iclass 6, count 0 2006.285.10:45:21.10#ibcon#about to read 4, iclass 6, count 0 2006.285.10:45:21.10#ibcon#read 4, iclass 6, count 0 2006.285.10:45:21.10#ibcon#about to read 5, iclass 6, count 0 2006.285.10:45:21.10#ibcon#read 5, iclass 6, count 0 2006.285.10:45:21.10#ibcon#about to read 6, iclass 6, count 0 2006.285.10:45:21.10#ibcon#read 6, iclass 6, count 0 2006.285.10:45:21.10#ibcon#end of sib2, iclass 6, count 0 2006.285.10:45:21.10#ibcon#*after write, iclass 6, count 0 2006.285.10:45:21.10#ibcon#*before return 0, iclass 6, count 0 2006.285.10:45:21.10#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:45:21.10#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:45:21.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:45:21.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:45:21.10$vck44/valo=5,734.99 2006.285.10:45:21.10#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.10:45:21.10#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.10:45:21.10#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:21.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:45:21.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:45:21.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:45:21.10#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:45:21.10#ibcon#first serial, iclass 10, count 0 2006.285.10:45:21.10#ibcon#enter sib2, iclass 10, count 0 2006.285.10:45:21.10#ibcon#flushed, iclass 10, count 0 2006.285.10:45:21.10#ibcon#about to write, iclass 10, count 0 2006.285.10:45:21.10#ibcon#wrote, iclass 10, count 0 2006.285.10:45:21.10#ibcon#about to read 3, iclass 10, count 0 2006.285.10:45:21.12#ibcon#read 3, iclass 10, count 0 2006.285.10:45:21.12#ibcon#about to read 4, iclass 10, count 0 2006.285.10:45:21.12#ibcon#read 4, iclass 10, count 0 2006.285.10:45:21.12#ibcon#about to read 5, iclass 10, count 0 2006.285.10:45:21.12#ibcon#read 5, iclass 10, count 0 2006.285.10:45:21.12#ibcon#about to read 6, iclass 10, count 0 2006.285.10:45:21.12#ibcon#read 6, iclass 10, count 0 2006.285.10:45:21.12#ibcon#end of sib2, iclass 10, count 0 2006.285.10:45:21.12#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:45:21.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:45:21.12#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:45:21.12#ibcon#*before write, iclass 10, count 0 2006.285.10:45:21.12#ibcon#enter sib2, iclass 10, count 0 2006.285.10:45:21.12#ibcon#flushed, iclass 10, count 0 2006.285.10:45:21.12#ibcon#about to write, iclass 10, count 0 2006.285.10:45:21.12#ibcon#wrote, iclass 10, count 0 2006.285.10:45:21.12#ibcon#about to read 3, iclass 10, count 0 2006.285.10:45:21.16#ibcon#read 3, iclass 10, count 0 2006.285.10:45:21.16#ibcon#about to read 4, iclass 10, count 0 2006.285.10:45:21.16#ibcon#read 4, iclass 10, count 0 2006.285.10:45:21.16#ibcon#about to read 5, iclass 10, count 0 2006.285.10:45:21.16#ibcon#read 5, iclass 10, count 0 2006.285.10:45:21.16#ibcon#about to read 6, iclass 10, count 0 2006.285.10:45:21.16#ibcon#read 6, iclass 10, count 0 2006.285.10:45:21.16#ibcon#end of sib2, iclass 10, count 0 2006.285.10:45:21.16#ibcon#*after write, iclass 10, count 0 2006.285.10:45:21.16#ibcon#*before return 0, iclass 10, count 0 2006.285.10:45:21.16#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:45:21.16#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:45:21.16#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:45:21.16#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:45:21.16$vck44/va=5,3 2006.285.10:45:21.16#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.10:45:21.16#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.10:45:21.16#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:21.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:45:21.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:45:21.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:45:21.22#ibcon#enter wrdev, iclass 12, count 2 2006.285.10:45:21.22#ibcon#first serial, iclass 12, count 2 2006.285.10:45:21.22#ibcon#enter sib2, iclass 12, count 2 2006.285.10:45:21.22#ibcon#flushed, iclass 12, count 2 2006.285.10:45:21.22#ibcon#about to write, iclass 12, count 2 2006.285.10:45:21.22#ibcon#wrote, iclass 12, count 2 2006.285.10:45:21.22#ibcon#about to read 3, iclass 12, count 2 2006.285.10:45:21.24#ibcon#read 3, iclass 12, count 2 2006.285.10:45:21.24#ibcon#about to read 4, iclass 12, count 2 2006.285.10:45:21.24#ibcon#read 4, iclass 12, count 2 2006.285.10:45:21.24#ibcon#about to read 5, iclass 12, count 2 2006.285.10:45:21.24#ibcon#read 5, iclass 12, count 2 2006.285.10:45:21.24#ibcon#about to read 6, iclass 12, count 2 2006.285.10:45:21.24#ibcon#read 6, iclass 12, count 2 2006.285.10:45:21.24#ibcon#end of sib2, iclass 12, count 2 2006.285.10:45:21.24#ibcon#*mode == 0, iclass 12, count 2 2006.285.10:45:21.24#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.10:45:21.24#ibcon#[25=AT05-03\r\n] 2006.285.10:45:21.24#ibcon#*before write, iclass 12, count 2 2006.285.10:45:21.24#ibcon#enter sib2, iclass 12, count 2 2006.285.10:45:21.24#ibcon#flushed, iclass 12, count 2 2006.285.10:45:21.24#ibcon#about to write, iclass 12, count 2 2006.285.10:45:21.24#ibcon#wrote, iclass 12, count 2 2006.285.10:45:21.24#ibcon#about to read 3, iclass 12, count 2 2006.285.10:45:21.27#ibcon#read 3, iclass 12, count 2 2006.285.10:45:21.27#ibcon#about to read 4, iclass 12, count 2 2006.285.10:45:21.27#ibcon#read 4, iclass 12, count 2 2006.285.10:45:21.27#ibcon#about to read 5, iclass 12, count 2 2006.285.10:45:21.27#ibcon#read 5, iclass 12, count 2 2006.285.10:45:21.27#ibcon#about to read 6, iclass 12, count 2 2006.285.10:45:21.27#ibcon#read 6, iclass 12, count 2 2006.285.10:45:21.27#ibcon#end of sib2, iclass 12, count 2 2006.285.10:45:21.27#ibcon#*after write, iclass 12, count 2 2006.285.10:45:21.27#ibcon#*before return 0, iclass 12, count 2 2006.285.10:45:21.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:45:21.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:45:21.27#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.10:45:21.27#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:21.27#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:45:21.39#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:45:21.39#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:45:21.39#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:45:21.39#ibcon#first serial, iclass 12, count 0 2006.285.10:45:21.39#ibcon#enter sib2, iclass 12, count 0 2006.285.10:45:21.39#ibcon#flushed, iclass 12, count 0 2006.285.10:45:21.39#ibcon#about to write, iclass 12, count 0 2006.285.10:45:21.39#ibcon#wrote, iclass 12, count 0 2006.285.10:45:21.39#ibcon#about to read 3, iclass 12, count 0 2006.285.10:45:21.41#ibcon#read 3, iclass 12, count 0 2006.285.10:45:21.41#ibcon#about to read 4, iclass 12, count 0 2006.285.10:45:21.41#ibcon#read 4, iclass 12, count 0 2006.285.10:45:21.41#ibcon#about to read 5, iclass 12, count 0 2006.285.10:45:21.41#ibcon#read 5, iclass 12, count 0 2006.285.10:45:21.41#ibcon#about to read 6, iclass 12, count 0 2006.285.10:45:21.41#ibcon#read 6, iclass 12, count 0 2006.285.10:45:21.41#ibcon#end of sib2, iclass 12, count 0 2006.285.10:45:21.41#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:45:21.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:45:21.41#ibcon#[25=USB\r\n] 2006.285.10:45:21.41#ibcon#*before write, iclass 12, count 0 2006.285.10:45:21.41#ibcon#enter sib2, iclass 12, count 0 2006.285.10:45:21.41#ibcon#flushed, iclass 12, count 0 2006.285.10:45:21.41#ibcon#about to write, iclass 12, count 0 2006.285.10:45:21.41#ibcon#wrote, iclass 12, count 0 2006.285.10:45:21.41#ibcon#about to read 3, iclass 12, count 0 2006.285.10:45:21.44#ibcon#read 3, iclass 12, count 0 2006.285.10:45:21.44#ibcon#about to read 4, iclass 12, count 0 2006.285.10:45:21.44#ibcon#read 4, iclass 12, count 0 2006.285.10:45:21.44#ibcon#about to read 5, iclass 12, count 0 2006.285.10:45:21.44#ibcon#read 5, iclass 12, count 0 2006.285.10:45:21.44#ibcon#about to read 6, iclass 12, count 0 2006.285.10:45:21.44#ibcon#read 6, iclass 12, count 0 2006.285.10:45:21.44#ibcon#end of sib2, iclass 12, count 0 2006.285.10:45:21.44#ibcon#*after write, iclass 12, count 0 2006.285.10:45:21.44#ibcon#*before return 0, iclass 12, count 0 2006.285.10:45:21.44#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:45:21.44#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:45:21.44#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:45:21.44#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:45:21.44$vck44/valo=6,814.99 2006.285.10:45:21.44#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.10:45:21.44#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.10:45:21.44#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:21.44#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:45:21.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:45:21.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:45:21.44#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:45:21.44#ibcon#first serial, iclass 14, count 0 2006.285.10:45:21.44#ibcon#enter sib2, iclass 14, count 0 2006.285.10:45:21.44#ibcon#flushed, iclass 14, count 0 2006.285.10:45:21.44#ibcon#about to write, iclass 14, count 0 2006.285.10:45:21.44#ibcon#wrote, iclass 14, count 0 2006.285.10:45:21.44#ibcon#about to read 3, iclass 14, count 0 2006.285.10:45:21.46#ibcon#read 3, iclass 14, count 0 2006.285.10:45:21.46#ibcon#about to read 4, iclass 14, count 0 2006.285.10:45:21.46#ibcon#read 4, iclass 14, count 0 2006.285.10:45:21.46#ibcon#about to read 5, iclass 14, count 0 2006.285.10:45:21.46#ibcon#read 5, iclass 14, count 0 2006.285.10:45:21.46#ibcon#about to read 6, iclass 14, count 0 2006.285.10:45:21.46#ibcon#read 6, iclass 14, count 0 2006.285.10:45:21.46#ibcon#end of sib2, iclass 14, count 0 2006.285.10:45:21.46#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:45:21.46#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:45:21.46#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:45:21.46#ibcon#*before write, iclass 14, count 0 2006.285.10:45:21.46#ibcon#enter sib2, iclass 14, count 0 2006.285.10:45:21.46#ibcon#flushed, iclass 14, count 0 2006.285.10:45:21.46#ibcon#about to write, iclass 14, count 0 2006.285.10:45:21.46#ibcon#wrote, iclass 14, count 0 2006.285.10:45:21.46#ibcon#about to read 3, iclass 14, count 0 2006.285.10:45:21.50#ibcon#read 3, iclass 14, count 0 2006.285.10:45:21.50#ibcon#about to read 4, iclass 14, count 0 2006.285.10:45:21.50#ibcon#read 4, iclass 14, count 0 2006.285.10:45:21.50#ibcon#about to read 5, iclass 14, count 0 2006.285.10:45:21.50#ibcon#read 5, iclass 14, count 0 2006.285.10:45:21.50#ibcon#about to read 6, iclass 14, count 0 2006.285.10:45:21.50#ibcon#read 6, iclass 14, count 0 2006.285.10:45:21.50#ibcon#end of sib2, iclass 14, count 0 2006.285.10:45:21.50#ibcon#*after write, iclass 14, count 0 2006.285.10:45:21.50#ibcon#*before return 0, iclass 14, count 0 2006.285.10:45:21.50#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:45:21.50#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.10:45:21.50#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:45:21.50#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:45:21.50$vck44/va=6,4 2006.285.10:45:21.50#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.10:45:21.50#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.10:45:21.50#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:21.50#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:45:21.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:45:21.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:45:21.56#ibcon#enter wrdev, iclass 16, count 2 2006.285.10:45:21.56#ibcon#first serial, iclass 16, count 2 2006.285.10:45:21.56#ibcon#enter sib2, iclass 16, count 2 2006.285.10:45:21.56#ibcon#flushed, iclass 16, count 2 2006.285.10:45:21.56#ibcon#about to write, iclass 16, count 2 2006.285.10:45:21.56#ibcon#wrote, iclass 16, count 2 2006.285.10:45:21.56#ibcon#about to read 3, iclass 16, count 2 2006.285.10:45:21.58#ibcon#read 3, iclass 16, count 2 2006.285.10:45:21.58#ibcon#about to read 4, iclass 16, count 2 2006.285.10:45:21.58#ibcon#read 4, iclass 16, count 2 2006.285.10:45:21.58#ibcon#about to read 5, iclass 16, count 2 2006.285.10:45:21.58#ibcon#read 5, iclass 16, count 2 2006.285.10:45:21.58#ibcon#about to read 6, iclass 16, count 2 2006.285.10:45:21.58#ibcon#read 6, iclass 16, count 2 2006.285.10:45:21.58#ibcon#end of sib2, iclass 16, count 2 2006.285.10:45:21.58#ibcon#*mode == 0, iclass 16, count 2 2006.285.10:45:21.58#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.10:45:21.58#ibcon#[25=AT06-04\r\n] 2006.285.10:45:21.58#ibcon#*before write, iclass 16, count 2 2006.285.10:45:21.58#ibcon#enter sib2, iclass 16, count 2 2006.285.10:45:21.58#ibcon#flushed, iclass 16, count 2 2006.285.10:45:21.58#ibcon#about to write, iclass 16, count 2 2006.285.10:45:21.58#ibcon#wrote, iclass 16, count 2 2006.285.10:45:21.58#ibcon#about to read 3, iclass 16, count 2 2006.285.10:45:21.61#ibcon#read 3, iclass 16, count 2 2006.285.10:45:21.61#ibcon#about to read 4, iclass 16, count 2 2006.285.10:45:21.61#ibcon#read 4, iclass 16, count 2 2006.285.10:45:21.61#ibcon#about to read 5, iclass 16, count 2 2006.285.10:45:21.61#ibcon#read 5, iclass 16, count 2 2006.285.10:45:21.61#ibcon#about to read 6, iclass 16, count 2 2006.285.10:45:21.61#ibcon#read 6, iclass 16, count 2 2006.285.10:45:21.61#ibcon#end of sib2, iclass 16, count 2 2006.285.10:45:21.61#ibcon#*after write, iclass 16, count 2 2006.285.10:45:21.61#ibcon#*before return 0, iclass 16, count 2 2006.285.10:45:21.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:45:21.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.10:45:21.61#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.10:45:21.61#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:21.61#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:45:21.73#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:45:21.73#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:45:21.73#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:45:21.73#ibcon#first serial, iclass 16, count 0 2006.285.10:45:21.73#ibcon#enter sib2, iclass 16, count 0 2006.285.10:45:21.73#ibcon#flushed, iclass 16, count 0 2006.285.10:45:21.73#ibcon#about to write, iclass 16, count 0 2006.285.10:45:21.73#ibcon#wrote, iclass 16, count 0 2006.285.10:45:21.73#ibcon#about to read 3, iclass 16, count 0 2006.285.10:45:21.75#ibcon#read 3, iclass 16, count 0 2006.285.10:45:21.75#ibcon#about to read 4, iclass 16, count 0 2006.285.10:45:21.75#ibcon#read 4, iclass 16, count 0 2006.285.10:45:21.75#ibcon#about to read 5, iclass 16, count 0 2006.285.10:45:21.75#ibcon#read 5, iclass 16, count 0 2006.285.10:45:21.75#ibcon#about to read 6, iclass 16, count 0 2006.285.10:45:21.75#ibcon#read 6, iclass 16, count 0 2006.285.10:45:21.75#ibcon#end of sib2, iclass 16, count 0 2006.285.10:45:21.75#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:45:21.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:45:21.75#ibcon#[25=USB\r\n] 2006.285.10:45:21.75#ibcon#*before write, iclass 16, count 0 2006.285.10:45:21.75#ibcon#enter sib2, iclass 16, count 0 2006.285.10:45:21.75#ibcon#flushed, iclass 16, count 0 2006.285.10:45:21.75#ibcon#about to write, iclass 16, count 0 2006.285.10:45:21.75#ibcon#wrote, iclass 16, count 0 2006.285.10:45:21.75#ibcon#about to read 3, iclass 16, count 0 2006.285.10:45:21.78#ibcon#read 3, iclass 16, count 0 2006.285.10:45:21.78#ibcon#about to read 4, iclass 16, count 0 2006.285.10:45:21.78#ibcon#read 4, iclass 16, count 0 2006.285.10:45:21.78#ibcon#about to read 5, iclass 16, count 0 2006.285.10:45:21.78#ibcon#read 5, iclass 16, count 0 2006.285.10:45:21.78#ibcon#about to read 6, iclass 16, count 0 2006.285.10:45:21.78#ibcon#read 6, iclass 16, count 0 2006.285.10:45:21.78#ibcon#end of sib2, iclass 16, count 0 2006.285.10:45:21.78#ibcon#*after write, iclass 16, count 0 2006.285.10:45:21.78#ibcon#*before return 0, iclass 16, count 0 2006.285.10:45:21.78#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:45:21.78#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.10:45:21.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:45:21.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:45:21.78$vck44/valo=7,864.99 2006.285.10:45:21.78#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.10:45:21.78#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.10:45:21.78#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:21.78#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:45:21.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:45:21.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:45:21.78#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:45:21.78#ibcon#first serial, iclass 18, count 0 2006.285.10:45:21.78#ibcon#enter sib2, iclass 18, count 0 2006.285.10:45:21.78#ibcon#flushed, iclass 18, count 0 2006.285.10:45:21.78#ibcon#about to write, iclass 18, count 0 2006.285.10:45:21.78#ibcon#wrote, iclass 18, count 0 2006.285.10:45:21.78#ibcon#about to read 3, iclass 18, count 0 2006.285.10:45:21.80#ibcon#read 3, iclass 18, count 0 2006.285.10:45:21.80#ibcon#about to read 4, iclass 18, count 0 2006.285.10:45:21.80#ibcon#read 4, iclass 18, count 0 2006.285.10:45:21.80#ibcon#about to read 5, iclass 18, count 0 2006.285.10:45:21.80#ibcon#read 5, iclass 18, count 0 2006.285.10:45:21.80#ibcon#about to read 6, iclass 18, count 0 2006.285.10:45:21.80#ibcon#read 6, iclass 18, count 0 2006.285.10:45:21.80#ibcon#end of sib2, iclass 18, count 0 2006.285.10:45:21.80#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:45:21.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:45:21.80#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:45:21.80#ibcon#*before write, iclass 18, count 0 2006.285.10:45:21.80#ibcon#enter sib2, iclass 18, count 0 2006.285.10:45:21.80#ibcon#flushed, iclass 18, count 0 2006.285.10:45:21.80#ibcon#about to write, iclass 18, count 0 2006.285.10:45:21.80#ibcon#wrote, iclass 18, count 0 2006.285.10:45:21.80#ibcon#about to read 3, iclass 18, count 0 2006.285.10:45:21.84#ibcon#read 3, iclass 18, count 0 2006.285.10:45:21.84#ibcon#about to read 4, iclass 18, count 0 2006.285.10:45:21.84#ibcon#read 4, iclass 18, count 0 2006.285.10:45:21.84#ibcon#about to read 5, iclass 18, count 0 2006.285.10:45:21.84#ibcon#read 5, iclass 18, count 0 2006.285.10:45:21.84#ibcon#about to read 6, iclass 18, count 0 2006.285.10:45:21.84#ibcon#read 6, iclass 18, count 0 2006.285.10:45:21.84#ibcon#end of sib2, iclass 18, count 0 2006.285.10:45:21.84#ibcon#*after write, iclass 18, count 0 2006.285.10:45:21.84#ibcon#*before return 0, iclass 18, count 0 2006.285.10:45:21.84#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:45:21.84#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:45:21.84#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:45:21.84#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:45:21.84$vck44/va=7,4 2006.285.10:45:21.84#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.10:45:21.84#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.10:45:21.84#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:21.84#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:45:21.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:45:21.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:45:21.90#ibcon#enter wrdev, iclass 20, count 2 2006.285.10:45:21.90#ibcon#first serial, iclass 20, count 2 2006.285.10:45:21.90#ibcon#enter sib2, iclass 20, count 2 2006.285.10:45:21.90#ibcon#flushed, iclass 20, count 2 2006.285.10:45:21.90#ibcon#about to write, iclass 20, count 2 2006.285.10:45:21.90#ibcon#wrote, iclass 20, count 2 2006.285.10:45:21.90#ibcon#about to read 3, iclass 20, count 2 2006.285.10:45:21.92#ibcon#read 3, iclass 20, count 2 2006.285.10:45:21.92#ibcon#about to read 4, iclass 20, count 2 2006.285.10:45:21.92#ibcon#read 4, iclass 20, count 2 2006.285.10:45:21.92#ibcon#about to read 5, iclass 20, count 2 2006.285.10:45:21.92#ibcon#read 5, iclass 20, count 2 2006.285.10:45:21.92#ibcon#about to read 6, iclass 20, count 2 2006.285.10:45:21.92#ibcon#read 6, iclass 20, count 2 2006.285.10:45:21.92#ibcon#end of sib2, iclass 20, count 2 2006.285.10:45:21.92#ibcon#*mode == 0, iclass 20, count 2 2006.285.10:45:21.92#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.10:45:21.92#ibcon#[25=AT07-04\r\n] 2006.285.10:45:21.92#ibcon#*before write, iclass 20, count 2 2006.285.10:45:21.92#ibcon#enter sib2, iclass 20, count 2 2006.285.10:45:21.92#ibcon#flushed, iclass 20, count 2 2006.285.10:45:21.92#ibcon#about to write, iclass 20, count 2 2006.285.10:45:21.92#ibcon#wrote, iclass 20, count 2 2006.285.10:45:21.92#ibcon#about to read 3, iclass 20, count 2 2006.285.10:45:21.95#ibcon#read 3, iclass 20, count 2 2006.285.10:45:21.95#ibcon#about to read 4, iclass 20, count 2 2006.285.10:45:21.95#ibcon#read 4, iclass 20, count 2 2006.285.10:45:21.95#ibcon#about to read 5, iclass 20, count 2 2006.285.10:45:21.95#ibcon#read 5, iclass 20, count 2 2006.285.10:45:21.95#ibcon#about to read 6, iclass 20, count 2 2006.285.10:45:21.95#ibcon#read 6, iclass 20, count 2 2006.285.10:45:21.95#ibcon#end of sib2, iclass 20, count 2 2006.285.10:45:21.95#ibcon#*after write, iclass 20, count 2 2006.285.10:45:21.95#ibcon#*before return 0, iclass 20, count 2 2006.285.10:45:21.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:45:21.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:45:21.95#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.10:45:21.95#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:21.95#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:45:22.07#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:45:22.07#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:45:22.07#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:45:22.07#ibcon#first serial, iclass 20, count 0 2006.285.10:45:22.07#ibcon#enter sib2, iclass 20, count 0 2006.285.10:45:22.07#ibcon#flushed, iclass 20, count 0 2006.285.10:45:22.07#ibcon#about to write, iclass 20, count 0 2006.285.10:45:22.07#ibcon#wrote, iclass 20, count 0 2006.285.10:45:22.07#ibcon#about to read 3, iclass 20, count 0 2006.285.10:45:22.09#ibcon#read 3, iclass 20, count 0 2006.285.10:45:22.09#ibcon#about to read 4, iclass 20, count 0 2006.285.10:45:22.09#ibcon#read 4, iclass 20, count 0 2006.285.10:45:22.09#ibcon#about to read 5, iclass 20, count 0 2006.285.10:45:22.09#ibcon#read 5, iclass 20, count 0 2006.285.10:45:22.09#ibcon#about to read 6, iclass 20, count 0 2006.285.10:45:22.09#ibcon#read 6, iclass 20, count 0 2006.285.10:45:22.09#ibcon#end of sib2, iclass 20, count 0 2006.285.10:45:22.09#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:45:22.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:45:22.09#ibcon#[25=USB\r\n] 2006.285.10:45:22.09#ibcon#*before write, iclass 20, count 0 2006.285.10:45:22.09#ibcon#enter sib2, iclass 20, count 0 2006.285.10:45:22.09#ibcon#flushed, iclass 20, count 0 2006.285.10:45:22.09#ibcon#about to write, iclass 20, count 0 2006.285.10:45:22.09#ibcon#wrote, iclass 20, count 0 2006.285.10:45:22.09#ibcon#about to read 3, iclass 20, count 0 2006.285.10:45:22.12#ibcon#read 3, iclass 20, count 0 2006.285.10:45:22.12#ibcon#about to read 4, iclass 20, count 0 2006.285.10:45:22.12#ibcon#read 4, iclass 20, count 0 2006.285.10:45:22.12#ibcon#about to read 5, iclass 20, count 0 2006.285.10:45:22.12#ibcon#read 5, iclass 20, count 0 2006.285.10:45:22.12#ibcon#about to read 6, iclass 20, count 0 2006.285.10:45:22.12#ibcon#read 6, iclass 20, count 0 2006.285.10:45:22.12#ibcon#end of sib2, iclass 20, count 0 2006.285.10:45:22.12#ibcon#*after write, iclass 20, count 0 2006.285.10:45:22.12#ibcon#*before return 0, iclass 20, count 0 2006.285.10:45:22.12#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:45:22.12#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:45:22.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:45:22.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:45:22.12$vck44/valo=8,884.99 2006.285.10:45:22.12#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.10:45:22.12#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.10:45:22.12#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:22.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:45:22.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:45:22.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:45:22.12#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:45:22.12#ibcon#first serial, iclass 22, count 0 2006.285.10:45:22.12#ibcon#enter sib2, iclass 22, count 0 2006.285.10:45:22.12#ibcon#flushed, iclass 22, count 0 2006.285.10:45:22.12#ibcon#about to write, iclass 22, count 0 2006.285.10:45:22.12#ibcon#wrote, iclass 22, count 0 2006.285.10:45:22.12#ibcon#about to read 3, iclass 22, count 0 2006.285.10:45:22.14#ibcon#read 3, iclass 22, count 0 2006.285.10:45:22.14#ibcon#about to read 4, iclass 22, count 0 2006.285.10:45:22.14#ibcon#read 4, iclass 22, count 0 2006.285.10:45:22.14#ibcon#about to read 5, iclass 22, count 0 2006.285.10:45:22.14#ibcon#read 5, iclass 22, count 0 2006.285.10:45:22.14#ibcon#about to read 6, iclass 22, count 0 2006.285.10:45:22.14#ibcon#read 6, iclass 22, count 0 2006.285.10:45:22.14#ibcon#end of sib2, iclass 22, count 0 2006.285.10:45:22.14#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:45:22.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:45:22.14#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:45:22.14#ibcon#*before write, iclass 22, count 0 2006.285.10:45:22.14#ibcon#enter sib2, iclass 22, count 0 2006.285.10:45:22.14#ibcon#flushed, iclass 22, count 0 2006.285.10:45:22.14#ibcon#about to write, iclass 22, count 0 2006.285.10:45:22.14#ibcon#wrote, iclass 22, count 0 2006.285.10:45:22.14#ibcon#about to read 3, iclass 22, count 0 2006.285.10:45:22.18#ibcon#read 3, iclass 22, count 0 2006.285.10:45:22.18#ibcon#about to read 4, iclass 22, count 0 2006.285.10:45:22.18#ibcon#read 4, iclass 22, count 0 2006.285.10:45:22.18#ibcon#about to read 5, iclass 22, count 0 2006.285.10:45:22.18#ibcon#read 5, iclass 22, count 0 2006.285.10:45:22.18#ibcon#about to read 6, iclass 22, count 0 2006.285.10:45:22.18#ibcon#read 6, iclass 22, count 0 2006.285.10:45:22.18#ibcon#end of sib2, iclass 22, count 0 2006.285.10:45:22.18#ibcon#*after write, iclass 22, count 0 2006.285.10:45:22.18#ibcon#*before return 0, iclass 22, count 0 2006.285.10:45:22.18#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:45:22.18#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:45:22.18#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:45:22.18#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:45:22.18$vck44/va=8,3 2006.285.10:45:22.18#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.10:45:22.18#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.10:45:22.18#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:22.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:45:22.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:45:22.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:45:22.24#ibcon#enter wrdev, iclass 24, count 2 2006.285.10:45:22.24#ibcon#first serial, iclass 24, count 2 2006.285.10:45:22.24#ibcon#enter sib2, iclass 24, count 2 2006.285.10:45:22.24#ibcon#flushed, iclass 24, count 2 2006.285.10:45:22.24#ibcon#about to write, iclass 24, count 2 2006.285.10:45:22.24#ibcon#wrote, iclass 24, count 2 2006.285.10:45:22.24#ibcon#about to read 3, iclass 24, count 2 2006.285.10:45:22.26#ibcon#read 3, iclass 24, count 2 2006.285.10:45:22.26#ibcon#about to read 4, iclass 24, count 2 2006.285.10:45:22.26#ibcon#read 4, iclass 24, count 2 2006.285.10:45:22.26#ibcon#about to read 5, iclass 24, count 2 2006.285.10:45:22.26#ibcon#read 5, iclass 24, count 2 2006.285.10:45:22.26#ibcon#about to read 6, iclass 24, count 2 2006.285.10:45:22.26#ibcon#read 6, iclass 24, count 2 2006.285.10:45:22.26#ibcon#end of sib2, iclass 24, count 2 2006.285.10:45:22.26#ibcon#*mode == 0, iclass 24, count 2 2006.285.10:45:22.26#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.10:45:22.26#ibcon#[25=AT08-03\r\n] 2006.285.10:45:22.26#ibcon#*before write, iclass 24, count 2 2006.285.10:45:22.26#ibcon#enter sib2, iclass 24, count 2 2006.285.10:45:22.26#ibcon#flushed, iclass 24, count 2 2006.285.10:45:22.26#ibcon#about to write, iclass 24, count 2 2006.285.10:45:22.26#ibcon#wrote, iclass 24, count 2 2006.285.10:45:22.26#ibcon#about to read 3, iclass 24, count 2 2006.285.10:45:22.29#ibcon#read 3, iclass 24, count 2 2006.285.10:45:22.29#ibcon#about to read 4, iclass 24, count 2 2006.285.10:45:22.29#ibcon#read 4, iclass 24, count 2 2006.285.10:45:22.29#ibcon#about to read 5, iclass 24, count 2 2006.285.10:45:22.29#ibcon#read 5, iclass 24, count 2 2006.285.10:45:22.29#ibcon#about to read 6, iclass 24, count 2 2006.285.10:45:22.29#ibcon#read 6, iclass 24, count 2 2006.285.10:45:22.29#ibcon#end of sib2, iclass 24, count 2 2006.285.10:45:22.29#ibcon#*after write, iclass 24, count 2 2006.285.10:45:22.29#ibcon#*before return 0, iclass 24, count 2 2006.285.10:45:22.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:45:22.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:45:22.29#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.10:45:22.29#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:22.29#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:45:22.41#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:45:22.41#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:45:22.41#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:45:22.41#ibcon#first serial, iclass 24, count 0 2006.285.10:45:22.41#ibcon#enter sib2, iclass 24, count 0 2006.285.10:45:22.41#ibcon#flushed, iclass 24, count 0 2006.285.10:45:22.41#ibcon#about to write, iclass 24, count 0 2006.285.10:45:22.41#ibcon#wrote, iclass 24, count 0 2006.285.10:45:22.41#ibcon#about to read 3, iclass 24, count 0 2006.285.10:45:22.43#ibcon#read 3, iclass 24, count 0 2006.285.10:45:22.43#ibcon#about to read 4, iclass 24, count 0 2006.285.10:45:22.43#ibcon#read 4, iclass 24, count 0 2006.285.10:45:22.43#ibcon#about to read 5, iclass 24, count 0 2006.285.10:45:22.43#ibcon#read 5, iclass 24, count 0 2006.285.10:45:22.43#ibcon#about to read 6, iclass 24, count 0 2006.285.10:45:22.43#ibcon#read 6, iclass 24, count 0 2006.285.10:45:22.43#ibcon#end of sib2, iclass 24, count 0 2006.285.10:45:22.43#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:45:22.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:45:22.43#ibcon#[25=USB\r\n] 2006.285.10:45:22.43#ibcon#*before write, iclass 24, count 0 2006.285.10:45:22.43#ibcon#enter sib2, iclass 24, count 0 2006.285.10:45:22.43#ibcon#flushed, iclass 24, count 0 2006.285.10:45:22.43#ibcon#about to write, iclass 24, count 0 2006.285.10:45:22.43#ibcon#wrote, iclass 24, count 0 2006.285.10:45:22.43#ibcon#about to read 3, iclass 24, count 0 2006.285.10:45:22.46#ibcon#read 3, iclass 24, count 0 2006.285.10:45:22.46#ibcon#about to read 4, iclass 24, count 0 2006.285.10:45:22.46#ibcon#read 4, iclass 24, count 0 2006.285.10:45:22.46#ibcon#about to read 5, iclass 24, count 0 2006.285.10:45:22.46#ibcon#read 5, iclass 24, count 0 2006.285.10:45:22.46#ibcon#about to read 6, iclass 24, count 0 2006.285.10:45:22.46#ibcon#read 6, iclass 24, count 0 2006.285.10:45:22.46#ibcon#end of sib2, iclass 24, count 0 2006.285.10:45:22.46#ibcon#*after write, iclass 24, count 0 2006.285.10:45:22.46#ibcon#*before return 0, iclass 24, count 0 2006.285.10:45:22.46#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:45:22.46#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:45:22.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:45:22.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:45:22.46$vck44/vblo=1,629.99 2006.285.10:45:22.46#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.10:45:22.46#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.10:45:22.46#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:22.46#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:45:22.46#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:45:22.46#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:45:22.46#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:45:22.46#ibcon#first serial, iclass 26, count 0 2006.285.10:45:22.46#ibcon#enter sib2, iclass 26, count 0 2006.285.10:45:22.46#ibcon#flushed, iclass 26, count 0 2006.285.10:45:22.46#ibcon#about to write, iclass 26, count 0 2006.285.10:45:22.46#ibcon#wrote, iclass 26, count 0 2006.285.10:45:22.46#ibcon#about to read 3, iclass 26, count 0 2006.285.10:45:22.48#ibcon#read 3, iclass 26, count 0 2006.285.10:45:22.48#ibcon#about to read 4, iclass 26, count 0 2006.285.10:45:22.48#ibcon#read 4, iclass 26, count 0 2006.285.10:45:22.48#ibcon#about to read 5, iclass 26, count 0 2006.285.10:45:22.48#ibcon#read 5, iclass 26, count 0 2006.285.10:45:22.48#ibcon#about to read 6, iclass 26, count 0 2006.285.10:45:22.48#ibcon#read 6, iclass 26, count 0 2006.285.10:45:22.48#ibcon#end of sib2, iclass 26, count 0 2006.285.10:45:22.48#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:45:22.48#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:45:22.48#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:45:22.48#ibcon#*before write, iclass 26, count 0 2006.285.10:45:22.48#ibcon#enter sib2, iclass 26, count 0 2006.285.10:45:22.48#ibcon#flushed, iclass 26, count 0 2006.285.10:45:22.48#ibcon#about to write, iclass 26, count 0 2006.285.10:45:22.48#ibcon#wrote, iclass 26, count 0 2006.285.10:45:22.48#ibcon#about to read 3, iclass 26, count 0 2006.285.10:45:22.52#ibcon#read 3, iclass 26, count 0 2006.285.10:45:22.52#ibcon#about to read 4, iclass 26, count 0 2006.285.10:45:22.52#ibcon#read 4, iclass 26, count 0 2006.285.10:45:22.52#ibcon#about to read 5, iclass 26, count 0 2006.285.10:45:22.52#ibcon#read 5, iclass 26, count 0 2006.285.10:45:22.52#ibcon#about to read 6, iclass 26, count 0 2006.285.10:45:22.52#ibcon#read 6, iclass 26, count 0 2006.285.10:45:22.52#ibcon#end of sib2, iclass 26, count 0 2006.285.10:45:22.52#ibcon#*after write, iclass 26, count 0 2006.285.10:45:22.52#ibcon#*before return 0, iclass 26, count 0 2006.285.10:45:22.52#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:45:22.52#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:45:22.52#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:45:22.52#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:45:22.52$vck44/vb=1,4 2006.285.10:45:22.52#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.10:45:22.52#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.10:45:22.52#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:22.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:45:22.52#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:45:22.52#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:45:22.52#ibcon#enter wrdev, iclass 28, count 2 2006.285.10:45:22.52#ibcon#first serial, iclass 28, count 2 2006.285.10:45:22.52#ibcon#enter sib2, iclass 28, count 2 2006.285.10:45:22.52#ibcon#flushed, iclass 28, count 2 2006.285.10:45:22.52#ibcon#about to write, iclass 28, count 2 2006.285.10:45:22.52#ibcon#wrote, iclass 28, count 2 2006.285.10:45:22.52#ibcon#about to read 3, iclass 28, count 2 2006.285.10:45:22.54#ibcon#read 3, iclass 28, count 2 2006.285.10:45:22.54#ibcon#about to read 4, iclass 28, count 2 2006.285.10:45:22.54#ibcon#read 4, iclass 28, count 2 2006.285.10:45:22.54#ibcon#about to read 5, iclass 28, count 2 2006.285.10:45:22.54#ibcon#read 5, iclass 28, count 2 2006.285.10:45:22.54#ibcon#about to read 6, iclass 28, count 2 2006.285.10:45:22.54#ibcon#read 6, iclass 28, count 2 2006.285.10:45:22.54#ibcon#end of sib2, iclass 28, count 2 2006.285.10:45:22.54#ibcon#*mode == 0, iclass 28, count 2 2006.285.10:45:22.54#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.10:45:22.54#ibcon#[27=AT01-04\r\n] 2006.285.10:45:22.54#ibcon#*before write, iclass 28, count 2 2006.285.10:45:22.54#ibcon#enter sib2, iclass 28, count 2 2006.285.10:45:22.54#ibcon#flushed, iclass 28, count 2 2006.285.10:45:22.54#ibcon#about to write, iclass 28, count 2 2006.285.10:45:22.54#ibcon#wrote, iclass 28, count 2 2006.285.10:45:22.54#ibcon#about to read 3, iclass 28, count 2 2006.285.10:45:22.57#ibcon#read 3, iclass 28, count 2 2006.285.10:45:22.57#ibcon#about to read 4, iclass 28, count 2 2006.285.10:45:22.57#ibcon#read 4, iclass 28, count 2 2006.285.10:45:22.57#ibcon#about to read 5, iclass 28, count 2 2006.285.10:45:22.57#ibcon#read 5, iclass 28, count 2 2006.285.10:45:22.57#ibcon#about to read 6, iclass 28, count 2 2006.285.10:45:22.57#ibcon#read 6, iclass 28, count 2 2006.285.10:45:22.57#ibcon#end of sib2, iclass 28, count 2 2006.285.10:45:22.57#ibcon#*after write, iclass 28, count 2 2006.285.10:45:22.57#ibcon#*before return 0, iclass 28, count 2 2006.285.10:45:22.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:45:22.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.10:45:22.57#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.10:45:22.57#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:22.57#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:45:22.69#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:45:22.69#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:45:22.69#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:45:22.69#ibcon#first serial, iclass 28, count 0 2006.285.10:45:22.69#ibcon#enter sib2, iclass 28, count 0 2006.285.10:45:22.69#ibcon#flushed, iclass 28, count 0 2006.285.10:45:22.69#ibcon#about to write, iclass 28, count 0 2006.285.10:45:22.69#ibcon#wrote, iclass 28, count 0 2006.285.10:45:22.69#ibcon#about to read 3, iclass 28, count 0 2006.285.10:45:22.71#ibcon#read 3, iclass 28, count 0 2006.285.10:45:22.71#ibcon#about to read 4, iclass 28, count 0 2006.285.10:45:22.71#ibcon#read 4, iclass 28, count 0 2006.285.10:45:22.71#ibcon#about to read 5, iclass 28, count 0 2006.285.10:45:22.71#ibcon#read 5, iclass 28, count 0 2006.285.10:45:22.71#ibcon#about to read 6, iclass 28, count 0 2006.285.10:45:22.71#ibcon#read 6, iclass 28, count 0 2006.285.10:45:22.71#ibcon#end of sib2, iclass 28, count 0 2006.285.10:45:22.71#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:45:22.71#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:45:22.71#ibcon#[27=USB\r\n] 2006.285.10:45:22.71#ibcon#*before write, iclass 28, count 0 2006.285.10:45:22.71#ibcon#enter sib2, iclass 28, count 0 2006.285.10:45:22.71#ibcon#flushed, iclass 28, count 0 2006.285.10:45:22.71#ibcon#about to write, iclass 28, count 0 2006.285.10:45:22.71#ibcon#wrote, iclass 28, count 0 2006.285.10:45:22.71#ibcon#about to read 3, iclass 28, count 0 2006.285.10:45:22.74#ibcon#read 3, iclass 28, count 0 2006.285.10:45:22.74#ibcon#about to read 4, iclass 28, count 0 2006.285.10:45:22.74#ibcon#read 4, iclass 28, count 0 2006.285.10:45:22.74#ibcon#about to read 5, iclass 28, count 0 2006.285.10:45:22.74#ibcon#read 5, iclass 28, count 0 2006.285.10:45:22.74#ibcon#about to read 6, iclass 28, count 0 2006.285.10:45:22.74#ibcon#read 6, iclass 28, count 0 2006.285.10:45:22.74#ibcon#end of sib2, iclass 28, count 0 2006.285.10:45:22.74#ibcon#*after write, iclass 28, count 0 2006.285.10:45:22.74#ibcon#*before return 0, iclass 28, count 0 2006.285.10:45:22.74#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:45:22.74#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.10:45:22.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:45:22.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:45:22.74$vck44/vblo=2,634.99 2006.285.10:45:22.74#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.10:45:22.74#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.10:45:22.74#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:22.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:45:22.74#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:45:22.74#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:45:22.74#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:45:22.74#ibcon#first serial, iclass 30, count 0 2006.285.10:45:22.74#ibcon#enter sib2, iclass 30, count 0 2006.285.10:45:22.74#ibcon#flushed, iclass 30, count 0 2006.285.10:45:22.74#ibcon#about to write, iclass 30, count 0 2006.285.10:45:22.74#ibcon#wrote, iclass 30, count 0 2006.285.10:45:22.74#ibcon#about to read 3, iclass 30, count 0 2006.285.10:45:22.76#ibcon#read 3, iclass 30, count 0 2006.285.10:45:22.76#ibcon#about to read 4, iclass 30, count 0 2006.285.10:45:22.76#ibcon#read 4, iclass 30, count 0 2006.285.10:45:22.76#ibcon#about to read 5, iclass 30, count 0 2006.285.10:45:22.76#ibcon#read 5, iclass 30, count 0 2006.285.10:45:22.76#ibcon#about to read 6, iclass 30, count 0 2006.285.10:45:22.76#ibcon#read 6, iclass 30, count 0 2006.285.10:45:22.76#ibcon#end of sib2, iclass 30, count 0 2006.285.10:45:22.76#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:45:22.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:45:22.76#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:45:22.76#ibcon#*before write, iclass 30, count 0 2006.285.10:45:22.76#ibcon#enter sib2, iclass 30, count 0 2006.285.10:45:22.76#ibcon#flushed, iclass 30, count 0 2006.285.10:45:22.76#ibcon#about to write, iclass 30, count 0 2006.285.10:45:22.76#ibcon#wrote, iclass 30, count 0 2006.285.10:45:22.76#ibcon#about to read 3, iclass 30, count 0 2006.285.10:45:22.80#ibcon#read 3, iclass 30, count 0 2006.285.10:45:22.80#ibcon#about to read 4, iclass 30, count 0 2006.285.10:45:22.80#ibcon#read 4, iclass 30, count 0 2006.285.10:45:22.80#ibcon#about to read 5, iclass 30, count 0 2006.285.10:45:22.80#ibcon#read 5, iclass 30, count 0 2006.285.10:45:22.80#ibcon#about to read 6, iclass 30, count 0 2006.285.10:45:22.80#ibcon#read 6, iclass 30, count 0 2006.285.10:45:22.80#ibcon#end of sib2, iclass 30, count 0 2006.285.10:45:22.80#ibcon#*after write, iclass 30, count 0 2006.285.10:45:22.80#ibcon#*before return 0, iclass 30, count 0 2006.285.10:45:22.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:45:22.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.10:45:22.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:45:22.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:45:22.80$vck44/vb=2,5 2006.285.10:45:22.80#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.10:45:22.80#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.10:45:22.80#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:22.80#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:45:22.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:45:22.86#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:45:22.86#ibcon#enter wrdev, iclass 32, count 2 2006.285.10:45:22.86#ibcon#first serial, iclass 32, count 2 2006.285.10:45:22.86#ibcon#enter sib2, iclass 32, count 2 2006.285.10:45:22.86#ibcon#flushed, iclass 32, count 2 2006.285.10:45:22.86#ibcon#about to write, iclass 32, count 2 2006.285.10:45:22.86#ibcon#wrote, iclass 32, count 2 2006.285.10:45:22.86#ibcon#about to read 3, iclass 32, count 2 2006.285.10:45:22.88#ibcon#read 3, iclass 32, count 2 2006.285.10:45:22.88#ibcon#about to read 4, iclass 32, count 2 2006.285.10:45:22.88#ibcon#read 4, iclass 32, count 2 2006.285.10:45:22.88#ibcon#about to read 5, iclass 32, count 2 2006.285.10:45:22.88#ibcon#read 5, iclass 32, count 2 2006.285.10:45:22.88#ibcon#about to read 6, iclass 32, count 2 2006.285.10:45:22.88#ibcon#read 6, iclass 32, count 2 2006.285.10:45:22.88#ibcon#end of sib2, iclass 32, count 2 2006.285.10:45:22.88#ibcon#*mode == 0, iclass 32, count 2 2006.285.10:45:22.88#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.10:45:22.88#ibcon#[27=AT02-05\r\n] 2006.285.10:45:22.88#ibcon#*before write, iclass 32, count 2 2006.285.10:45:22.88#ibcon#enter sib2, iclass 32, count 2 2006.285.10:45:22.88#ibcon#flushed, iclass 32, count 2 2006.285.10:45:22.88#ibcon#about to write, iclass 32, count 2 2006.285.10:45:22.88#ibcon#wrote, iclass 32, count 2 2006.285.10:45:22.88#ibcon#about to read 3, iclass 32, count 2 2006.285.10:45:22.91#ibcon#read 3, iclass 32, count 2 2006.285.10:45:22.91#ibcon#about to read 4, iclass 32, count 2 2006.285.10:45:22.91#ibcon#read 4, iclass 32, count 2 2006.285.10:45:22.91#ibcon#about to read 5, iclass 32, count 2 2006.285.10:45:22.91#ibcon#read 5, iclass 32, count 2 2006.285.10:45:22.91#ibcon#about to read 6, iclass 32, count 2 2006.285.10:45:22.91#ibcon#read 6, iclass 32, count 2 2006.285.10:45:22.91#ibcon#end of sib2, iclass 32, count 2 2006.285.10:45:22.91#ibcon#*after write, iclass 32, count 2 2006.285.10:45:22.91#ibcon#*before return 0, iclass 32, count 2 2006.285.10:45:22.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:45:22.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.10:45:22.91#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.10:45:22.91#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:22.91#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:45:23.03#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:45:23.03#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:45:23.03#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:45:23.03#ibcon#first serial, iclass 32, count 0 2006.285.10:45:23.03#ibcon#enter sib2, iclass 32, count 0 2006.285.10:45:23.03#ibcon#flushed, iclass 32, count 0 2006.285.10:45:23.03#ibcon#about to write, iclass 32, count 0 2006.285.10:45:23.03#ibcon#wrote, iclass 32, count 0 2006.285.10:45:23.03#ibcon#about to read 3, iclass 32, count 0 2006.285.10:45:23.05#ibcon#read 3, iclass 32, count 0 2006.285.10:45:23.05#ibcon#about to read 4, iclass 32, count 0 2006.285.10:45:23.05#ibcon#read 4, iclass 32, count 0 2006.285.10:45:23.05#ibcon#about to read 5, iclass 32, count 0 2006.285.10:45:23.05#ibcon#read 5, iclass 32, count 0 2006.285.10:45:23.05#ibcon#about to read 6, iclass 32, count 0 2006.285.10:45:23.05#ibcon#read 6, iclass 32, count 0 2006.285.10:45:23.05#ibcon#end of sib2, iclass 32, count 0 2006.285.10:45:23.05#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:45:23.05#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:45:23.05#ibcon#[27=USB\r\n] 2006.285.10:45:23.05#ibcon#*before write, iclass 32, count 0 2006.285.10:45:23.05#ibcon#enter sib2, iclass 32, count 0 2006.285.10:45:23.05#ibcon#flushed, iclass 32, count 0 2006.285.10:45:23.05#ibcon#about to write, iclass 32, count 0 2006.285.10:45:23.05#ibcon#wrote, iclass 32, count 0 2006.285.10:45:23.05#ibcon#about to read 3, iclass 32, count 0 2006.285.10:45:23.08#ibcon#read 3, iclass 32, count 0 2006.285.10:45:23.08#ibcon#about to read 4, iclass 32, count 0 2006.285.10:45:23.08#ibcon#read 4, iclass 32, count 0 2006.285.10:45:23.08#ibcon#about to read 5, iclass 32, count 0 2006.285.10:45:23.08#ibcon#read 5, iclass 32, count 0 2006.285.10:45:23.08#ibcon#about to read 6, iclass 32, count 0 2006.285.10:45:23.08#ibcon#read 6, iclass 32, count 0 2006.285.10:45:23.08#ibcon#end of sib2, iclass 32, count 0 2006.285.10:45:23.08#ibcon#*after write, iclass 32, count 0 2006.285.10:45:23.08#ibcon#*before return 0, iclass 32, count 0 2006.285.10:45:23.08#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:45:23.08#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.10:45:23.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:45:23.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:45:23.08$vck44/vblo=3,649.99 2006.285.10:45:23.08#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.10:45:23.08#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.10:45:23.08#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:23.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:45:23.08#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:45:23.08#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:45:23.08#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:45:23.08#ibcon#first serial, iclass 34, count 0 2006.285.10:45:23.08#ibcon#enter sib2, iclass 34, count 0 2006.285.10:45:23.08#ibcon#flushed, iclass 34, count 0 2006.285.10:45:23.08#ibcon#about to write, iclass 34, count 0 2006.285.10:45:23.08#ibcon#wrote, iclass 34, count 0 2006.285.10:45:23.08#ibcon#about to read 3, iclass 34, count 0 2006.285.10:45:23.10#ibcon#read 3, iclass 34, count 0 2006.285.10:45:23.10#ibcon#about to read 4, iclass 34, count 0 2006.285.10:45:23.10#ibcon#read 4, iclass 34, count 0 2006.285.10:45:23.10#ibcon#about to read 5, iclass 34, count 0 2006.285.10:45:23.10#ibcon#read 5, iclass 34, count 0 2006.285.10:45:23.10#ibcon#about to read 6, iclass 34, count 0 2006.285.10:45:23.10#ibcon#read 6, iclass 34, count 0 2006.285.10:45:23.10#ibcon#end of sib2, iclass 34, count 0 2006.285.10:45:23.10#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:45:23.10#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:45:23.10#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:45:23.10#ibcon#*before write, iclass 34, count 0 2006.285.10:45:23.10#ibcon#enter sib2, iclass 34, count 0 2006.285.10:45:23.10#ibcon#flushed, iclass 34, count 0 2006.285.10:45:23.10#ibcon#about to write, iclass 34, count 0 2006.285.10:45:23.10#ibcon#wrote, iclass 34, count 0 2006.285.10:45:23.10#ibcon#about to read 3, iclass 34, count 0 2006.285.10:45:23.14#ibcon#read 3, iclass 34, count 0 2006.285.10:45:23.14#ibcon#about to read 4, iclass 34, count 0 2006.285.10:45:23.14#ibcon#read 4, iclass 34, count 0 2006.285.10:45:23.14#ibcon#about to read 5, iclass 34, count 0 2006.285.10:45:23.14#ibcon#read 5, iclass 34, count 0 2006.285.10:45:23.14#ibcon#about to read 6, iclass 34, count 0 2006.285.10:45:23.14#ibcon#read 6, iclass 34, count 0 2006.285.10:45:23.14#ibcon#end of sib2, iclass 34, count 0 2006.285.10:45:23.14#ibcon#*after write, iclass 34, count 0 2006.285.10:45:23.14#ibcon#*before return 0, iclass 34, count 0 2006.285.10:45:23.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:45:23.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.10:45:23.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:45:23.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:45:23.14$vck44/vb=3,4 2006.285.10:45:23.14#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.10:45:23.14#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.10:45:23.14#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:23.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:45:23.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:45:23.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:45:23.20#ibcon#enter wrdev, iclass 36, count 2 2006.285.10:45:23.20#ibcon#first serial, iclass 36, count 2 2006.285.10:45:23.20#ibcon#enter sib2, iclass 36, count 2 2006.285.10:45:23.20#ibcon#flushed, iclass 36, count 2 2006.285.10:45:23.20#ibcon#about to write, iclass 36, count 2 2006.285.10:45:23.20#ibcon#wrote, iclass 36, count 2 2006.285.10:45:23.20#ibcon#about to read 3, iclass 36, count 2 2006.285.10:45:23.22#ibcon#read 3, iclass 36, count 2 2006.285.10:45:23.22#ibcon#about to read 4, iclass 36, count 2 2006.285.10:45:23.22#ibcon#read 4, iclass 36, count 2 2006.285.10:45:23.22#ibcon#about to read 5, iclass 36, count 2 2006.285.10:45:23.22#ibcon#read 5, iclass 36, count 2 2006.285.10:45:23.22#ibcon#about to read 6, iclass 36, count 2 2006.285.10:45:23.22#ibcon#read 6, iclass 36, count 2 2006.285.10:45:23.22#ibcon#end of sib2, iclass 36, count 2 2006.285.10:45:23.22#ibcon#*mode == 0, iclass 36, count 2 2006.285.10:45:23.22#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.10:45:23.22#ibcon#[27=AT03-04\r\n] 2006.285.10:45:23.22#ibcon#*before write, iclass 36, count 2 2006.285.10:45:23.22#ibcon#enter sib2, iclass 36, count 2 2006.285.10:45:23.22#ibcon#flushed, iclass 36, count 2 2006.285.10:45:23.22#ibcon#about to write, iclass 36, count 2 2006.285.10:45:23.22#ibcon#wrote, iclass 36, count 2 2006.285.10:45:23.22#ibcon#about to read 3, iclass 36, count 2 2006.285.10:45:23.25#ibcon#read 3, iclass 36, count 2 2006.285.10:45:23.25#ibcon#about to read 4, iclass 36, count 2 2006.285.10:45:23.25#ibcon#read 4, iclass 36, count 2 2006.285.10:45:23.25#ibcon#about to read 5, iclass 36, count 2 2006.285.10:45:23.25#ibcon#read 5, iclass 36, count 2 2006.285.10:45:23.25#ibcon#about to read 6, iclass 36, count 2 2006.285.10:45:23.25#ibcon#read 6, iclass 36, count 2 2006.285.10:45:23.25#ibcon#end of sib2, iclass 36, count 2 2006.285.10:45:23.25#ibcon#*after write, iclass 36, count 2 2006.285.10:45:23.25#ibcon#*before return 0, iclass 36, count 2 2006.285.10:45:23.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:45:23.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:45:23.25#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.10:45:23.25#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:23.25#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:45:23.37#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:45:23.37#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:45:23.37#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:45:23.37#ibcon#first serial, iclass 36, count 0 2006.285.10:45:23.37#ibcon#enter sib2, iclass 36, count 0 2006.285.10:45:23.37#ibcon#flushed, iclass 36, count 0 2006.285.10:45:23.37#ibcon#about to write, iclass 36, count 0 2006.285.10:45:23.37#ibcon#wrote, iclass 36, count 0 2006.285.10:45:23.37#ibcon#about to read 3, iclass 36, count 0 2006.285.10:45:23.39#ibcon#read 3, iclass 36, count 0 2006.285.10:45:23.39#ibcon#about to read 4, iclass 36, count 0 2006.285.10:45:23.39#ibcon#read 4, iclass 36, count 0 2006.285.10:45:23.39#ibcon#about to read 5, iclass 36, count 0 2006.285.10:45:23.39#ibcon#read 5, iclass 36, count 0 2006.285.10:45:23.39#ibcon#about to read 6, iclass 36, count 0 2006.285.10:45:23.39#ibcon#read 6, iclass 36, count 0 2006.285.10:45:23.39#ibcon#end of sib2, iclass 36, count 0 2006.285.10:45:23.39#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:45:23.39#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:45:23.39#ibcon#[27=USB\r\n] 2006.285.10:45:23.39#ibcon#*before write, iclass 36, count 0 2006.285.10:45:23.39#ibcon#enter sib2, iclass 36, count 0 2006.285.10:45:23.39#ibcon#flushed, iclass 36, count 0 2006.285.10:45:23.39#ibcon#about to write, iclass 36, count 0 2006.285.10:45:23.39#ibcon#wrote, iclass 36, count 0 2006.285.10:45:23.39#ibcon#about to read 3, iclass 36, count 0 2006.285.10:45:23.42#ibcon#read 3, iclass 36, count 0 2006.285.10:45:23.42#ibcon#about to read 4, iclass 36, count 0 2006.285.10:45:23.42#ibcon#read 4, iclass 36, count 0 2006.285.10:45:23.42#ibcon#about to read 5, iclass 36, count 0 2006.285.10:45:23.42#ibcon#read 5, iclass 36, count 0 2006.285.10:45:23.42#ibcon#about to read 6, iclass 36, count 0 2006.285.10:45:23.42#ibcon#read 6, iclass 36, count 0 2006.285.10:45:23.42#ibcon#end of sib2, iclass 36, count 0 2006.285.10:45:23.42#ibcon#*after write, iclass 36, count 0 2006.285.10:45:23.42#ibcon#*before return 0, iclass 36, count 0 2006.285.10:45:23.42#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:45:23.42#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:45:23.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:45:23.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:45:23.42$vck44/vblo=4,679.99 2006.285.10:45:23.42#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.10:45:23.42#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.10:45:23.42#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:23.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:45:23.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:45:23.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:45:23.42#ibcon#enter wrdev, iclass 38, count 0 2006.285.10:45:23.42#ibcon#first serial, iclass 38, count 0 2006.285.10:45:23.42#ibcon#enter sib2, iclass 38, count 0 2006.285.10:45:23.42#ibcon#flushed, iclass 38, count 0 2006.285.10:45:23.42#ibcon#about to write, iclass 38, count 0 2006.285.10:45:23.42#ibcon#wrote, iclass 38, count 0 2006.285.10:45:23.42#ibcon#about to read 3, iclass 38, count 0 2006.285.10:45:23.44#ibcon#read 3, iclass 38, count 0 2006.285.10:45:23.44#ibcon#about to read 4, iclass 38, count 0 2006.285.10:45:23.44#ibcon#read 4, iclass 38, count 0 2006.285.10:45:23.44#ibcon#about to read 5, iclass 38, count 0 2006.285.10:45:23.44#ibcon#read 5, iclass 38, count 0 2006.285.10:45:23.44#ibcon#about to read 6, iclass 38, count 0 2006.285.10:45:23.44#ibcon#read 6, iclass 38, count 0 2006.285.10:45:23.44#ibcon#end of sib2, iclass 38, count 0 2006.285.10:45:23.44#ibcon#*mode == 0, iclass 38, count 0 2006.285.10:45:23.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.10:45:23.44#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:45:23.44#ibcon#*before write, iclass 38, count 0 2006.285.10:45:23.44#ibcon#enter sib2, iclass 38, count 0 2006.285.10:45:23.44#ibcon#flushed, iclass 38, count 0 2006.285.10:45:23.44#ibcon#about to write, iclass 38, count 0 2006.285.10:45:23.44#ibcon#wrote, iclass 38, count 0 2006.285.10:45:23.44#ibcon#about to read 3, iclass 38, count 0 2006.285.10:45:23.48#ibcon#read 3, iclass 38, count 0 2006.285.10:45:23.48#ibcon#about to read 4, iclass 38, count 0 2006.285.10:45:23.48#ibcon#read 4, iclass 38, count 0 2006.285.10:45:23.48#ibcon#about to read 5, iclass 38, count 0 2006.285.10:45:23.48#ibcon#read 5, iclass 38, count 0 2006.285.10:45:23.48#ibcon#about to read 6, iclass 38, count 0 2006.285.10:45:23.48#ibcon#read 6, iclass 38, count 0 2006.285.10:45:23.48#ibcon#end of sib2, iclass 38, count 0 2006.285.10:45:23.48#ibcon#*after write, iclass 38, count 0 2006.285.10:45:23.48#ibcon#*before return 0, iclass 38, count 0 2006.285.10:45:23.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:45:23.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.10:45:23.48#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.10:45:23.48#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.10:45:23.48$vck44/vb=4,5 2006.285.10:45:23.48#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.10:45:23.48#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.10:45:23.48#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:23.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:45:23.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:45:23.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:45:23.54#ibcon#enter wrdev, iclass 40, count 2 2006.285.10:45:23.54#ibcon#first serial, iclass 40, count 2 2006.285.10:45:23.54#ibcon#enter sib2, iclass 40, count 2 2006.285.10:45:23.54#ibcon#flushed, iclass 40, count 2 2006.285.10:45:23.54#ibcon#about to write, iclass 40, count 2 2006.285.10:45:23.54#ibcon#wrote, iclass 40, count 2 2006.285.10:45:23.54#ibcon#about to read 3, iclass 40, count 2 2006.285.10:45:23.56#ibcon#read 3, iclass 40, count 2 2006.285.10:45:23.56#ibcon#about to read 4, iclass 40, count 2 2006.285.10:45:23.56#ibcon#read 4, iclass 40, count 2 2006.285.10:45:23.56#ibcon#about to read 5, iclass 40, count 2 2006.285.10:45:23.56#ibcon#read 5, iclass 40, count 2 2006.285.10:45:23.56#ibcon#about to read 6, iclass 40, count 2 2006.285.10:45:23.56#ibcon#read 6, iclass 40, count 2 2006.285.10:45:23.56#ibcon#end of sib2, iclass 40, count 2 2006.285.10:45:23.56#ibcon#*mode == 0, iclass 40, count 2 2006.285.10:45:23.56#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.10:45:23.56#ibcon#[27=AT04-05\r\n] 2006.285.10:45:23.56#ibcon#*before write, iclass 40, count 2 2006.285.10:45:23.56#ibcon#enter sib2, iclass 40, count 2 2006.285.10:45:23.56#ibcon#flushed, iclass 40, count 2 2006.285.10:45:23.56#ibcon#about to write, iclass 40, count 2 2006.285.10:45:23.56#ibcon#wrote, iclass 40, count 2 2006.285.10:45:23.56#ibcon#about to read 3, iclass 40, count 2 2006.285.10:45:23.59#ibcon#read 3, iclass 40, count 2 2006.285.10:45:23.59#ibcon#about to read 4, iclass 40, count 2 2006.285.10:45:23.59#ibcon#read 4, iclass 40, count 2 2006.285.10:45:23.59#ibcon#about to read 5, iclass 40, count 2 2006.285.10:45:23.59#ibcon#read 5, iclass 40, count 2 2006.285.10:45:23.59#ibcon#about to read 6, iclass 40, count 2 2006.285.10:45:23.59#ibcon#read 6, iclass 40, count 2 2006.285.10:45:23.59#ibcon#end of sib2, iclass 40, count 2 2006.285.10:45:23.59#ibcon#*after write, iclass 40, count 2 2006.285.10:45:23.59#ibcon#*before return 0, iclass 40, count 2 2006.285.10:45:23.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:45:23.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.10:45:23.59#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.10:45:23.59#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:23.59#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:45:23.71#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:45:23.71#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:45:23.71#ibcon#enter wrdev, iclass 40, count 0 2006.285.10:45:23.71#ibcon#first serial, iclass 40, count 0 2006.285.10:45:23.71#ibcon#enter sib2, iclass 40, count 0 2006.285.10:45:23.71#ibcon#flushed, iclass 40, count 0 2006.285.10:45:23.71#ibcon#about to write, iclass 40, count 0 2006.285.10:45:23.71#ibcon#wrote, iclass 40, count 0 2006.285.10:45:23.71#ibcon#about to read 3, iclass 40, count 0 2006.285.10:45:23.73#ibcon#read 3, iclass 40, count 0 2006.285.10:45:23.73#ibcon#about to read 4, iclass 40, count 0 2006.285.10:45:23.73#ibcon#read 4, iclass 40, count 0 2006.285.10:45:23.73#ibcon#about to read 5, iclass 40, count 0 2006.285.10:45:23.73#ibcon#read 5, iclass 40, count 0 2006.285.10:45:23.73#ibcon#about to read 6, iclass 40, count 0 2006.285.10:45:23.73#ibcon#read 6, iclass 40, count 0 2006.285.10:45:23.73#ibcon#end of sib2, iclass 40, count 0 2006.285.10:45:23.73#ibcon#*mode == 0, iclass 40, count 0 2006.285.10:45:23.73#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.10:45:23.73#ibcon#[27=USB\r\n] 2006.285.10:45:23.73#ibcon#*before write, iclass 40, count 0 2006.285.10:45:23.73#ibcon#enter sib2, iclass 40, count 0 2006.285.10:45:23.73#ibcon#flushed, iclass 40, count 0 2006.285.10:45:23.73#ibcon#about to write, iclass 40, count 0 2006.285.10:45:23.73#ibcon#wrote, iclass 40, count 0 2006.285.10:45:23.73#ibcon#about to read 3, iclass 40, count 0 2006.285.10:45:23.76#ibcon#read 3, iclass 40, count 0 2006.285.10:45:23.76#ibcon#about to read 4, iclass 40, count 0 2006.285.10:45:23.76#ibcon#read 4, iclass 40, count 0 2006.285.10:45:23.76#ibcon#about to read 5, iclass 40, count 0 2006.285.10:45:23.76#ibcon#read 5, iclass 40, count 0 2006.285.10:45:23.76#ibcon#about to read 6, iclass 40, count 0 2006.285.10:45:23.76#ibcon#read 6, iclass 40, count 0 2006.285.10:45:23.76#ibcon#end of sib2, iclass 40, count 0 2006.285.10:45:23.76#ibcon#*after write, iclass 40, count 0 2006.285.10:45:23.76#ibcon#*before return 0, iclass 40, count 0 2006.285.10:45:23.76#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:45:23.76#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.10:45:23.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.10:45:23.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.10:45:23.76$vck44/vblo=5,709.99 2006.285.10:45:23.76#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.10:45:23.76#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.10:45:23.76#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:23.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:45:23.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:45:23.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:45:23.76#ibcon#enter wrdev, iclass 4, count 0 2006.285.10:45:23.76#ibcon#first serial, iclass 4, count 0 2006.285.10:45:23.76#ibcon#enter sib2, iclass 4, count 0 2006.285.10:45:23.76#ibcon#flushed, iclass 4, count 0 2006.285.10:45:23.76#ibcon#about to write, iclass 4, count 0 2006.285.10:45:23.76#ibcon#wrote, iclass 4, count 0 2006.285.10:45:23.76#ibcon#about to read 3, iclass 4, count 0 2006.285.10:45:23.78#ibcon#read 3, iclass 4, count 0 2006.285.10:45:23.78#ibcon#about to read 4, iclass 4, count 0 2006.285.10:45:23.78#ibcon#read 4, iclass 4, count 0 2006.285.10:45:23.78#ibcon#about to read 5, iclass 4, count 0 2006.285.10:45:23.78#ibcon#read 5, iclass 4, count 0 2006.285.10:45:23.78#ibcon#about to read 6, iclass 4, count 0 2006.285.10:45:23.78#ibcon#read 6, iclass 4, count 0 2006.285.10:45:23.78#ibcon#end of sib2, iclass 4, count 0 2006.285.10:45:23.78#ibcon#*mode == 0, iclass 4, count 0 2006.285.10:45:23.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.10:45:23.78#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:45:23.78#ibcon#*before write, iclass 4, count 0 2006.285.10:45:23.78#ibcon#enter sib2, iclass 4, count 0 2006.285.10:45:23.78#ibcon#flushed, iclass 4, count 0 2006.285.10:45:23.78#ibcon#about to write, iclass 4, count 0 2006.285.10:45:23.78#ibcon#wrote, iclass 4, count 0 2006.285.10:45:23.78#ibcon#about to read 3, iclass 4, count 0 2006.285.10:45:23.82#ibcon#read 3, iclass 4, count 0 2006.285.10:45:23.82#ibcon#about to read 4, iclass 4, count 0 2006.285.10:45:23.82#ibcon#read 4, iclass 4, count 0 2006.285.10:45:23.82#ibcon#about to read 5, iclass 4, count 0 2006.285.10:45:23.82#ibcon#read 5, iclass 4, count 0 2006.285.10:45:23.82#ibcon#about to read 6, iclass 4, count 0 2006.285.10:45:23.82#ibcon#read 6, iclass 4, count 0 2006.285.10:45:23.82#ibcon#end of sib2, iclass 4, count 0 2006.285.10:45:23.82#ibcon#*after write, iclass 4, count 0 2006.285.10:45:23.82#ibcon#*before return 0, iclass 4, count 0 2006.285.10:45:23.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:45:23.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.10:45:23.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.10:45:23.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.10:45:23.82$vck44/vb=5,4 2006.285.10:45:23.82#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.10:45:23.82#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.10:45:23.82#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:23.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:45:23.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:45:23.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:45:23.88#ibcon#enter wrdev, iclass 6, count 2 2006.285.10:45:23.88#ibcon#first serial, iclass 6, count 2 2006.285.10:45:23.88#ibcon#enter sib2, iclass 6, count 2 2006.285.10:45:23.88#ibcon#flushed, iclass 6, count 2 2006.285.10:45:23.88#ibcon#about to write, iclass 6, count 2 2006.285.10:45:23.88#ibcon#wrote, iclass 6, count 2 2006.285.10:45:23.88#ibcon#about to read 3, iclass 6, count 2 2006.285.10:45:23.90#ibcon#read 3, iclass 6, count 2 2006.285.10:45:23.90#ibcon#about to read 4, iclass 6, count 2 2006.285.10:45:23.90#ibcon#read 4, iclass 6, count 2 2006.285.10:45:23.90#ibcon#about to read 5, iclass 6, count 2 2006.285.10:45:23.90#ibcon#read 5, iclass 6, count 2 2006.285.10:45:23.90#ibcon#about to read 6, iclass 6, count 2 2006.285.10:45:23.90#ibcon#read 6, iclass 6, count 2 2006.285.10:45:23.90#ibcon#end of sib2, iclass 6, count 2 2006.285.10:45:23.90#ibcon#*mode == 0, iclass 6, count 2 2006.285.10:45:23.90#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.10:45:23.90#ibcon#[27=AT05-04\r\n] 2006.285.10:45:23.90#ibcon#*before write, iclass 6, count 2 2006.285.10:45:23.90#ibcon#enter sib2, iclass 6, count 2 2006.285.10:45:23.90#ibcon#flushed, iclass 6, count 2 2006.285.10:45:23.90#ibcon#about to write, iclass 6, count 2 2006.285.10:45:23.90#ibcon#wrote, iclass 6, count 2 2006.285.10:45:23.90#ibcon#about to read 3, iclass 6, count 2 2006.285.10:45:23.93#ibcon#read 3, iclass 6, count 2 2006.285.10:45:23.93#ibcon#about to read 4, iclass 6, count 2 2006.285.10:45:23.93#ibcon#read 4, iclass 6, count 2 2006.285.10:45:23.93#ibcon#about to read 5, iclass 6, count 2 2006.285.10:45:23.93#ibcon#read 5, iclass 6, count 2 2006.285.10:45:23.93#ibcon#about to read 6, iclass 6, count 2 2006.285.10:45:23.93#ibcon#read 6, iclass 6, count 2 2006.285.10:45:23.93#ibcon#end of sib2, iclass 6, count 2 2006.285.10:45:23.93#ibcon#*after write, iclass 6, count 2 2006.285.10:45:23.93#ibcon#*before return 0, iclass 6, count 2 2006.285.10:45:23.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:45:23.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.10:45:23.93#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.10:45:23.93#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:23.93#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:45:24.05#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:45:24.05#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:45:24.05#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:45:24.05#ibcon#first serial, iclass 6, count 0 2006.285.10:45:24.05#ibcon#enter sib2, iclass 6, count 0 2006.285.10:45:24.05#ibcon#flushed, iclass 6, count 0 2006.285.10:45:24.05#ibcon#about to write, iclass 6, count 0 2006.285.10:45:24.05#ibcon#wrote, iclass 6, count 0 2006.285.10:45:24.05#ibcon#about to read 3, iclass 6, count 0 2006.285.10:45:24.07#ibcon#read 3, iclass 6, count 0 2006.285.10:45:24.07#ibcon#about to read 4, iclass 6, count 0 2006.285.10:45:24.07#ibcon#read 4, iclass 6, count 0 2006.285.10:45:24.07#ibcon#about to read 5, iclass 6, count 0 2006.285.10:45:24.07#ibcon#read 5, iclass 6, count 0 2006.285.10:45:24.07#ibcon#about to read 6, iclass 6, count 0 2006.285.10:45:24.07#ibcon#read 6, iclass 6, count 0 2006.285.10:45:24.07#ibcon#end of sib2, iclass 6, count 0 2006.285.10:45:24.07#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:45:24.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:45:24.07#ibcon#[27=USB\r\n] 2006.285.10:45:24.07#ibcon#*before write, iclass 6, count 0 2006.285.10:45:24.07#ibcon#enter sib2, iclass 6, count 0 2006.285.10:45:24.07#ibcon#flushed, iclass 6, count 0 2006.285.10:45:24.07#ibcon#about to write, iclass 6, count 0 2006.285.10:45:24.07#ibcon#wrote, iclass 6, count 0 2006.285.10:45:24.07#ibcon#about to read 3, iclass 6, count 0 2006.285.10:45:24.10#ibcon#read 3, iclass 6, count 0 2006.285.10:45:24.10#ibcon#about to read 4, iclass 6, count 0 2006.285.10:45:24.10#ibcon#read 4, iclass 6, count 0 2006.285.10:45:24.10#ibcon#about to read 5, iclass 6, count 0 2006.285.10:45:24.10#ibcon#read 5, iclass 6, count 0 2006.285.10:45:24.10#ibcon#about to read 6, iclass 6, count 0 2006.285.10:45:24.10#ibcon#read 6, iclass 6, count 0 2006.285.10:45:24.10#ibcon#end of sib2, iclass 6, count 0 2006.285.10:45:24.10#ibcon#*after write, iclass 6, count 0 2006.285.10:45:24.10#ibcon#*before return 0, iclass 6, count 0 2006.285.10:45:24.10#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:45:24.10#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.10:45:24.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:45:24.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:45:24.10$vck44/vblo=6,719.99 2006.285.10:45:24.10#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.10:45:24.10#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.10:45:24.10#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:24.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:45:24.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:45:24.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:45:24.10#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:45:24.10#ibcon#first serial, iclass 10, count 0 2006.285.10:45:24.10#ibcon#enter sib2, iclass 10, count 0 2006.285.10:45:24.10#ibcon#flushed, iclass 10, count 0 2006.285.10:45:24.10#ibcon#about to write, iclass 10, count 0 2006.285.10:45:24.10#ibcon#wrote, iclass 10, count 0 2006.285.10:45:24.10#ibcon#about to read 3, iclass 10, count 0 2006.285.10:45:24.12#ibcon#read 3, iclass 10, count 0 2006.285.10:45:24.12#ibcon#about to read 4, iclass 10, count 0 2006.285.10:45:24.12#ibcon#read 4, iclass 10, count 0 2006.285.10:45:24.12#ibcon#about to read 5, iclass 10, count 0 2006.285.10:45:24.12#ibcon#read 5, iclass 10, count 0 2006.285.10:45:24.12#ibcon#about to read 6, iclass 10, count 0 2006.285.10:45:24.12#ibcon#read 6, iclass 10, count 0 2006.285.10:45:24.12#ibcon#end of sib2, iclass 10, count 0 2006.285.10:45:24.12#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:45:24.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:45:24.12#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:45:24.12#ibcon#*before write, iclass 10, count 0 2006.285.10:45:24.12#ibcon#enter sib2, iclass 10, count 0 2006.285.10:45:24.12#ibcon#flushed, iclass 10, count 0 2006.285.10:45:24.12#ibcon#about to write, iclass 10, count 0 2006.285.10:45:24.12#ibcon#wrote, iclass 10, count 0 2006.285.10:45:24.12#ibcon#about to read 3, iclass 10, count 0 2006.285.10:45:24.16#ibcon#read 3, iclass 10, count 0 2006.285.10:45:24.16#ibcon#about to read 4, iclass 10, count 0 2006.285.10:45:24.16#ibcon#read 4, iclass 10, count 0 2006.285.10:45:24.16#ibcon#about to read 5, iclass 10, count 0 2006.285.10:45:24.16#ibcon#read 5, iclass 10, count 0 2006.285.10:45:24.16#ibcon#about to read 6, iclass 10, count 0 2006.285.10:45:24.16#ibcon#read 6, iclass 10, count 0 2006.285.10:45:24.16#ibcon#end of sib2, iclass 10, count 0 2006.285.10:45:24.16#ibcon#*after write, iclass 10, count 0 2006.285.10:45:24.16#ibcon#*before return 0, iclass 10, count 0 2006.285.10:45:24.16#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:45:24.16#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:45:24.16#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:45:24.16#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:45:24.16$vck44/vb=6,3 2006.285.10:45:24.16#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.10:45:24.16#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.10:45:24.16#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:24.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:45:24.22#abcon#<5=/05 1.3 2.0 19.66 921015.0\r\n> 2006.285.10:45:24.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:45:24.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:45:24.22#ibcon#enter wrdev, iclass 12, count 2 2006.285.10:45:24.22#ibcon#first serial, iclass 12, count 2 2006.285.10:45:24.22#ibcon#enter sib2, iclass 12, count 2 2006.285.10:45:24.22#ibcon#flushed, iclass 12, count 2 2006.285.10:45:24.22#ibcon#about to write, iclass 12, count 2 2006.285.10:45:24.22#ibcon#wrote, iclass 12, count 2 2006.285.10:45:24.22#ibcon#about to read 3, iclass 12, count 2 2006.285.10:45:24.24#ibcon#read 3, iclass 12, count 2 2006.285.10:45:24.24#ibcon#about to read 4, iclass 12, count 2 2006.285.10:45:24.24#ibcon#read 4, iclass 12, count 2 2006.285.10:45:24.24#ibcon#about to read 5, iclass 12, count 2 2006.285.10:45:24.24#ibcon#read 5, iclass 12, count 2 2006.285.10:45:24.24#ibcon#about to read 6, iclass 12, count 2 2006.285.10:45:24.24#ibcon#read 6, iclass 12, count 2 2006.285.10:45:24.24#ibcon#end of sib2, iclass 12, count 2 2006.285.10:45:24.24#ibcon#*mode == 0, iclass 12, count 2 2006.285.10:45:24.24#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.10:45:24.24#ibcon#[27=AT06-03\r\n] 2006.285.10:45:24.24#ibcon#*before write, iclass 12, count 2 2006.285.10:45:24.24#ibcon#enter sib2, iclass 12, count 2 2006.285.10:45:24.24#ibcon#flushed, iclass 12, count 2 2006.285.10:45:24.24#ibcon#about to write, iclass 12, count 2 2006.285.10:45:24.24#ibcon#wrote, iclass 12, count 2 2006.285.10:45:24.24#ibcon#about to read 3, iclass 12, count 2 2006.285.10:45:24.24#abcon#{5=INTERFACE CLEAR} 2006.285.10:45:24.27#ibcon#read 3, iclass 12, count 2 2006.285.10:45:24.27#ibcon#about to read 4, iclass 12, count 2 2006.285.10:45:24.27#ibcon#read 4, iclass 12, count 2 2006.285.10:45:24.27#ibcon#about to read 5, iclass 12, count 2 2006.285.10:45:24.27#ibcon#read 5, iclass 12, count 2 2006.285.10:45:24.27#ibcon#about to read 6, iclass 12, count 2 2006.285.10:45:24.27#ibcon#read 6, iclass 12, count 2 2006.285.10:45:24.27#ibcon#end of sib2, iclass 12, count 2 2006.285.10:45:24.27#ibcon#*after write, iclass 12, count 2 2006.285.10:45:24.27#ibcon#*before return 0, iclass 12, count 2 2006.285.10:45:24.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:45:24.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.10:45:24.27#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.10:45:24.27#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:24.27#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:45:24.30#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:45:24.39#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:45:24.39#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:45:24.39#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:45:24.39#ibcon#first serial, iclass 12, count 0 2006.285.10:45:24.39#ibcon#enter sib2, iclass 12, count 0 2006.285.10:45:24.39#ibcon#flushed, iclass 12, count 0 2006.285.10:45:24.39#ibcon#about to write, iclass 12, count 0 2006.285.10:45:24.39#ibcon#wrote, iclass 12, count 0 2006.285.10:45:24.39#ibcon#about to read 3, iclass 12, count 0 2006.285.10:45:24.41#ibcon#read 3, iclass 12, count 0 2006.285.10:45:24.41#ibcon#about to read 4, iclass 12, count 0 2006.285.10:45:24.41#ibcon#read 4, iclass 12, count 0 2006.285.10:45:24.41#ibcon#about to read 5, iclass 12, count 0 2006.285.10:45:24.41#ibcon#read 5, iclass 12, count 0 2006.285.10:45:24.41#ibcon#about to read 6, iclass 12, count 0 2006.285.10:45:24.41#ibcon#read 6, iclass 12, count 0 2006.285.10:45:24.41#ibcon#end of sib2, iclass 12, count 0 2006.285.10:45:24.41#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:45:24.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:45:24.41#ibcon#[27=USB\r\n] 2006.285.10:45:24.41#ibcon#*before write, iclass 12, count 0 2006.285.10:45:24.41#ibcon#enter sib2, iclass 12, count 0 2006.285.10:45:24.41#ibcon#flushed, iclass 12, count 0 2006.285.10:45:24.41#ibcon#about to write, iclass 12, count 0 2006.285.10:45:24.41#ibcon#wrote, iclass 12, count 0 2006.285.10:45:24.41#ibcon#about to read 3, iclass 12, count 0 2006.285.10:45:24.44#ibcon#read 3, iclass 12, count 0 2006.285.10:45:24.44#ibcon#about to read 4, iclass 12, count 0 2006.285.10:45:24.44#ibcon#read 4, iclass 12, count 0 2006.285.10:45:24.44#ibcon#about to read 5, iclass 12, count 0 2006.285.10:45:24.44#ibcon#read 5, iclass 12, count 0 2006.285.10:45:24.44#ibcon#about to read 6, iclass 12, count 0 2006.285.10:45:24.44#ibcon#read 6, iclass 12, count 0 2006.285.10:45:24.44#ibcon#end of sib2, iclass 12, count 0 2006.285.10:45:24.44#ibcon#*after write, iclass 12, count 0 2006.285.10:45:24.44#ibcon#*before return 0, iclass 12, count 0 2006.285.10:45:24.44#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:45:24.44#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.10:45:24.44#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:45:24.44#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:45:24.44$vck44/vblo=7,734.99 2006.285.10:45:24.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.10:45:24.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.10:45:24.44#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:24.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:45:24.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:45:24.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:45:24.44#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:45:24.44#ibcon#first serial, iclass 18, count 0 2006.285.10:45:24.44#ibcon#enter sib2, iclass 18, count 0 2006.285.10:45:24.44#ibcon#flushed, iclass 18, count 0 2006.285.10:45:24.44#ibcon#about to write, iclass 18, count 0 2006.285.10:45:24.44#ibcon#wrote, iclass 18, count 0 2006.285.10:45:24.44#ibcon#about to read 3, iclass 18, count 0 2006.285.10:45:24.46#ibcon#read 3, iclass 18, count 0 2006.285.10:45:24.46#ibcon#about to read 4, iclass 18, count 0 2006.285.10:45:24.46#ibcon#read 4, iclass 18, count 0 2006.285.10:45:24.46#ibcon#about to read 5, iclass 18, count 0 2006.285.10:45:24.46#ibcon#read 5, iclass 18, count 0 2006.285.10:45:24.46#ibcon#about to read 6, iclass 18, count 0 2006.285.10:45:24.46#ibcon#read 6, iclass 18, count 0 2006.285.10:45:24.46#ibcon#end of sib2, iclass 18, count 0 2006.285.10:45:24.46#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:45:24.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:45:24.46#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:45:24.46#ibcon#*before write, iclass 18, count 0 2006.285.10:45:24.46#ibcon#enter sib2, iclass 18, count 0 2006.285.10:45:24.46#ibcon#flushed, iclass 18, count 0 2006.285.10:45:24.46#ibcon#about to write, iclass 18, count 0 2006.285.10:45:24.46#ibcon#wrote, iclass 18, count 0 2006.285.10:45:24.46#ibcon#about to read 3, iclass 18, count 0 2006.285.10:45:24.50#ibcon#read 3, iclass 18, count 0 2006.285.10:45:24.50#ibcon#about to read 4, iclass 18, count 0 2006.285.10:45:24.50#ibcon#read 4, iclass 18, count 0 2006.285.10:45:24.50#ibcon#about to read 5, iclass 18, count 0 2006.285.10:45:24.50#ibcon#read 5, iclass 18, count 0 2006.285.10:45:24.50#ibcon#about to read 6, iclass 18, count 0 2006.285.10:45:24.50#ibcon#read 6, iclass 18, count 0 2006.285.10:45:24.50#ibcon#end of sib2, iclass 18, count 0 2006.285.10:45:24.50#ibcon#*after write, iclass 18, count 0 2006.285.10:45:24.50#ibcon#*before return 0, iclass 18, count 0 2006.285.10:45:24.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:45:24.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.10:45:24.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:45:24.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:45:24.50$vck44/vb=7,4 2006.285.10:45:24.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.10:45:24.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.10:45:24.50#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:24.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:45:24.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:45:24.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:45:24.56#ibcon#enter wrdev, iclass 20, count 2 2006.285.10:45:24.56#ibcon#first serial, iclass 20, count 2 2006.285.10:45:24.56#ibcon#enter sib2, iclass 20, count 2 2006.285.10:45:24.56#ibcon#flushed, iclass 20, count 2 2006.285.10:45:24.56#ibcon#about to write, iclass 20, count 2 2006.285.10:45:24.56#ibcon#wrote, iclass 20, count 2 2006.285.10:45:24.56#ibcon#about to read 3, iclass 20, count 2 2006.285.10:45:24.58#ibcon#read 3, iclass 20, count 2 2006.285.10:45:24.58#ibcon#about to read 4, iclass 20, count 2 2006.285.10:45:24.58#ibcon#read 4, iclass 20, count 2 2006.285.10:45:24.58#ibcon#about to read 5, iclass 20, count 2 2006.285.10:45:24.58#ibcon#read 5, iclass 20, count 2 2006.285.10:45:24.58#ibcon#about to read 6, iclass 20, count 2 2006.285.10:45:24.58#ibcon#read 6, iclass 20, count 2 2006.285.10:45:24.58#ibcon#end of sib2, iclass 20, count 2 2006.285.10:45:24.58#ibcon#*mode == 0, iclass 20, count 2 2006.285.10:45:24.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.10:45:24.58#ibcon#[27=AT07-04\r\n] 2006.285.10:45:24.58#ibcon#*before write, iclass 20, count 2 2006.285.10:45:24.58#ibcon#enter sib2, iclass 20, count 2 2006.285.10:45:24.58#ibcon#flushed, iclass 20, count 2 2006.285.10:45:24.58#ibcon#about to write, iclass 20, count 2 2006.285.10:45:24.58#ibcon#wrote, iclass 20, count 2 2006.285.10:45:24.58#ibcon#about to read 3, iclass 20, count 2 2006.285.10:45:24.61#ibcon#read 3, iclass 20, count 2 2006.285.10:45:24.61#ibcon#about to read 4, iclass 20, count 2 2006.285.10:45:24.61#ibcon#read 4, iclass 20, count 2 2006.285.10:45:24.61#ibcon#about to read 5, iclass 20, count 2 2006.285.10:45:24.61#ibcon#read 5, iclass 20, count 2 2006.285.10:45:24.61#ibcon#about to read 6, iclass 20, count 2 2006.285.10:45:24.61#ibcon#read 6, iclass 20, count 2 2006.285.10:45:24.61#ibcon#end of sib2, iclass 20, count 2 2006.285.10:45:24.61#ibcon#*after write, iclass 20, count 2 2006.285.10:45:24.61#ibcon#*before return 0, iclass 20, count 2 2006.285.10:45:24.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:45:24.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.10:45:24.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.10:45:24.61#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:24.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:45:24.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:45:24.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:45:24.73#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:45:24.73#ibcon#first serial, iclass 20, count 0 2006.285.10:45:24.73#ibcon#enter sib2, iclass 20, count 0 2006.285.10:45:24.73#ibcon#flushed, iclass 20, count 0 2006.285.10:45:24.73#ibcon#about to write, iclass 20, count 0 2006.285.10:45:24.73#ibcon#wrote, iclass 20, count 0 2006.285.10:45:24.73#ibcon#about to read 3, iclass 20, count 0 2006.285.10:45:24.75#ibcon#read 3, iclass 20, count 0 2006.285.10:45:24.75#ibcon#about to read 4, iclass 20, count 0 2006.285.10:45:24.75#ibcon#read 4, iclass 20, count 0 2006.285.10:45:24.75#ibcon#about to read 5, iclass 20, count 0 2006.285.10:45:24.75#ibcon#read 5, iclass 20, count 0 2006.285.10:45:24.75#ibcon#about to read 6, iclass 20, count 0 2006.285.10:45:24.75#ibcon#read 6, iclass 20, count 0 2006.285.10:45:24.75#ibcon#end of sib2, iclass 20, count 0 2006.285.10:45:24.75#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:45:24.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:45:24.75#ibcon#[27=USB\r\n] 2006.285.10:45:24.75#ibcon#*before write, iclass 20, count 0 2006.285.10:45:24.75#ibcon#enter sib2, iclass 20, count 0 2006.285.10:45:24.75#ibcon#flushed, iclass 20, count 0 2006.285.10:45:24.75#ibcon#about to write, iclass 20, count 0 2006.285.10:45:24.75#ibcon#wrote, iclass 20, count 0 2006.285.10:45:24.75#ibcon#about to read 3, iclass 20, count 0 2006.285.10:45:24.78#ibcon#read 3, iclass 20, count 0 2006.285.10:45:24.78#ibcon#about to read 4, iclass 20, count 0 2006.285.10:45:24.78#ibcon#read 4, iclass 20, count 0 2006.285.10:45:24.78#ibcon#about to read 5, iclass 20, count 0 2006.285.10:45:24.78#ibcon#read 5, iclass 20, count 0 2006.285.10:45:24.78#ibcon#about to read 6, iclass 20, count 0 2006.285.10:45:24.78#ibcon#read 6, iclass 20, count 0 2006.285.10:45:24.78#ibcon#end of sib2, iclass 20, count 0 2006.285.10:45:24.78#ibcon#*after write, iclass 20, count 0 2006.285.10:45:24.78#ibcon#*before return 0, iclass 20, count 0 2006.285.10:45:24.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:45:24.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.10:45:24.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:45:24.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:45:24.78$vck44/vblo=8,744.99 2006.285.10:45:24.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.10:45:24.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.10:45:24.78#ibcon#ireg 17 cls_cnt 0 2006.285.10:45:24.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:45:24.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:45:24.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:45:24.78#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:45:24.78#ibcon#first serial, iclass 22, count 0 2006.285.10:45:24.78#ibcon#enter sib2, iclass 22, count 0 2006.285.10:45:24.78#ibcon#flushed, iclass 22, count 0 2006.285.10:45:24.78#ibcon#about to write, iclass 22, count 0 2006.285.10:45:24.78#ibcon#wrote, iclass 22, count 0 2006.285.10:45:24.78#ibcon#about to read 3, iclass 22, count 0 2006.285.10:45:24.80#ibcon#read 3, iclass 22, count 0 2006.285.10:45:24.80#ibcon#about to read 4, iclass 22, count 0 2006.285.10:45:24.80#ibcon#read 4, iclass 22, count 0 2006.285.10:45:24.80#ibcon#about to read 5, iclass 22, count 0 2006.285.10:45:24.80#ibcon#read 5, iclass 22, count 0 2006.285.10:45:24.80#ibcon#about to read 6, iclass 22, count 0 2006.285.10:45:24.80#ibcon#read 6, iclass 22, count 0 2006.285.10:45:24.80#ibcon#end of sib2, iclass 22, count 0 2006.285.10:45:24.80#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:45:24.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:45:24.80#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:45:24.80#ibcon#*before write, iclass 22, count 0 2006.285.10:45:24.80#ibcon#enter sib2, iclass 22, count 0 2006.285.10:45:24.80#ibcon#flushed, iclass 22, count 0 2006.285.10:45:24.80#ibcon#about to write, iclass 22, count 0 2006.285.10:45:24.80#ibcon#wrote, iclass 22, count 0 2006.285.10:45:24.80#ibcon#about to read 3, iclass 22, count 0 2006.285.10:45:24.84#ibcon#read 3, iclass 22, count 0 2006.285.10:45:24.84#ibcon#about to read 4, iclass 22, count 0 2006.285.10:45:24.84#ibcon#read 4, iclass 22, count 0 2006.285.10:45:24.84#ibcon#about to read 5, iclass 22, count 0 2006.285.10:45:24.84#ibcon#read 5, iclass 22, count 0 2006.285.10:45:24.84#ibcon#about to read 6, iclass 22, count 0 2006.285.10:45:24.84#ibcon#read 6, iclass 22, count 0 2006.285.10:45:24.84#ibcon#end of sib2, iclass 22, count 0 2006.285.10:45:24.84#ibcon#*after write, iclass 22, count 0 2006.285.10:45:24.84#ibcon#*before return 0, iclass 22, count 0 2006.285.10:45:24.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:45:24.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.10:45:24.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:45:24.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:45:24.84$vck44/vb=8,4 2006.285.10:45:24.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.10:45:24.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.10:45:24.84#ibcon#ireg 11 cls_cnt 2 2006.285.10:45:24.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:45:24.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:45:24.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:45:24.90#ibcon#enter wrdev, iclass 24, count 2 2006.285.10:45:24.90#ibcon#first serial, iclass 24, count 2 2006.285.10:45:24.90#ibcon#enter sib2, iclass 24, count 2 2006.285.10:45:24.90#ibcon#flushed, iclass 24, count 2 2006.285.10:45:24.90#ibcon#about to write, iclass 24, count 2 2006.285.10:45:24.90#ibcon#wrote, iclass 24, count 2 2006.285.10:45:24.90#ibcon#about to read 3, iclass 24, count 2 2006.285.10:45:24.92#ibcon#read 3, iclass 24, count 2 2006.285.10:45:24.92#ibcon#about to read 4, iclass 24, count 2 2006.285.10:45:24.92#ibcon#read 4, iclass 24, count 2 2006.285.10:45:24.92#ibcon#about to read 5, iclass 24, count 2 2006.285.10:45:24.92#ibcon#read 5, iclass 24, count 2 2006.285.10:45:24.92#ibcon#about to read 6, iclass 24, count 2 2006.285.10:45:24.92#ibcon#read 6, iclass 24, count 2 2006.285.10:45:24.92#ibcon#end of sib2, iclass 24, count 2 2006.285.10:45:24.92#ibcon#*mode == 0, iclass 24, count 2 2006.285.10:45:24.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.10:45:24.92#ibcon#[27=AT08-04\r\n] 2006.285.10:45:24.92#ibcon#*before write, iclass 24, count 2 2006.285.10:45:24.92#ibcon#enter sib2, iclass 24, count 2 2006.285.10:45:24.92#ibcon#flushed, iclass 24, count 2 2006.285.10:45:24.92#ibcon#about to write, iclass 24, count 2 2006.285.10:45:24.92#ibcon#wrote, iclass 24, count 2 2006.285.10:45:24.92#ibcon#about to read 3, iclass 24, count 2 2006.285.10:45:24.95#ibcon#read 3, iclass 24, count 2 2006.285.10:45:24.95#ibcon#about to read 4, iclass 24, count 2 2006.285.10:45:24.95#ibcon#read 4, iclass 24, count 2 2006.285.10:45:24.95#ibcon#about to read 5, iclass 24, count 2 2006.285.10:45:24.95#ibcon#read 5, iclass 24, count 2 2006.285.10:45:24.95#ibcon#about to read 6, iclass 24, count 2 2006.285.10:45:24.95#ibcon#read 6, iclass 24, count 2 2006.285.10:45:24.95#ibcon#end of sib2, iclass 24, count 2 2006.285.10:45:24.95#ibcon#*after write, iclass 24, count 2 2006.285.10:45:24.95#ibcon#*before return 0, iclass 24, count 2 2006.285.10:45:24.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:45:24.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.10:45:24.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.10:45:24.95#ibcon#ireg 7 cls_cnt 0 2006.285.10:45:24.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:45:25.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:45:25.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:45:25.07#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:45:25.07#ibcon#first serial, iclass 24, count 0 2006.285.10:45:25.07#ibcon#enter sib2, iclass 24, count 0 2006.285.10:45:25.07#ibcon#flushed, iclass 24, count 0 2006.285.10:45:25.07#ibcon#about to write, iclass 24, count 0 2006.285.10:45:25.07#ibcon#wrote, iclass 24, count 0 2006.285.10:45:25.07#ibcon#about to read 3, iclass 24, count 0 2006.285.10:45:25.09#ibcon#read 3, iclass 24, count 0 2006.285.10:45:25.09#ibcon#about to read 4, iclass 24, count 0 2006.285.10:45:25.09#ibcon#read 4, iclass 24, count 0 2006.285.10:45:25.09#ibcon#about to read 5, iclass 24, count 0 2006.285.10:45:25.09#ibcon#read 5, iclass 24, count 0 2006.285.10:45:25.09#ibcon#about to read 6, iclass 24, count 0 2006.285.10:45:25.09#ibcon#read 6, iclass 24, count 0 2006.285.10:45:25.09#ibcon#end of sib2, iclass 24, count 0 2006.285.10:45:25.09#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:45:25.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:45:25.09#ibcon#[27=USB\r\n] 2006.285.10:45:25.09#ibcon#*before write, iclass 24, count 0 2006.285.10:45:25.09#ibcon#enter sib2, iclass 24, count 0 2006.285.10:45:25.09#ibcon#flushed, iclass 24, count 0 2006.285.10:45:25.09#ibcon#about to write, iclass 24, count 0 2006.285.10:45:25.09#ibcon#wrote, iclass 24, count 0 2006.285.10:45:25.09#ibcon#about to read 3, iclass 24, count 0 2006.285.10:45:25.12#ibcon#read 3, iclass 24, count 0 2006.285.10:45:25.12#ibcon#about to read 4, iclass 24, count 0 2006.285.10:45:25.12#ibcon#read 4, iclass 24, count 0 2006.285.10:45:25.12#ibcon#about to read 5, iclass 24, count 0 2006.285.10:45:25.12#ibcon#read 5, iclass 24, count 0 2006.285.10:45:25.12#ibcon#about to read 6, iclass 24, count 0 2006.285.10:45:25.12#ibcon#read 6, iclass 24, count 0 2006.285.10:45:25.12#ibcon#end of sib2, iclass 24, count 0 2006.285.10:45:25.12#ibcon#*after write, iclass 24, count 0 2006.285.10:45:25.12#ibcon#*before return 0, iclass 24, count 0 2006.285.10:45:25.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:45:25.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.10:45:25.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:45:25.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:45:25.12$vck44/vabw=wide 2006.285.10:45:25.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.10:45:25.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.10:45:25.12#ibcon#ireg 8 cls_cnt 0 2006.285.10:45:25.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:45:25.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:45:25.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:45:25.12#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:45:25.12#ibcon#first serial, iclass 26, count 0 2006.285.10:45:25.12#ibcon#enter sib2, iclass 26, count 0 2006.285.10:45:25.12#ibcon#flushed, iclass 26, count 0 2006.285.10:45:25.12#ibcon#about to write, iclass 26, count 0 2006.285.10:45:25.12#ibcon#wrote, iclass 26, count 0 2006.285.10:45:25.12#ibcon#about to read 3, iclass 26, count 0 2006.285.10:45:25.14#ibcon#read 3, iclass 26, count 0 2006.285.10:45:25.14#ibcon#about to read 4, iclass 26, count 0 2006.285.10:45:25.14#ibcon#read 4, iclass 26, count 0 2006.285.10:45:25.14#ibcon#about to read 5, iclass 26, count 0 2006.285.10:45:25.14#ibcon#read 5, iclass 26, count 0 2006.285.10:45:25.14#ibcon#about to read 6, iclass 26, count 0 2006.285.10:45:25.14#ibcon#read 6, iclass 26, count 0 2006.285.10:45:25.14#ibcon#end of sib2, iclass 26, count 0 2006.285.10:45:25.14#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:45:25.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:45:25.14#ibcon#[25=BW32\r\n] 2006.285.10:45:25.14#ibcon#*before write, iclass 26, count 0 2006.285.10:45:25.14#ibcon#enter sib2, iclass 26, count 0 2006.285.10:45:25.14#ibcon#flushed, iclass 26, count 0 2006.285.10:45:25.14#ibcon#about to write, iclass 26, count 0 2006.285.10:45:25.14#ibcon#wrote, iclass 26, count 0 2006.285.10:45:25.14#ibcon#about to read 3, iclass 26, count 0 2006.285.10:45:25.17#ibcon#read 3, iclass 26, count 0 2006.285.10:45:25.17#ibcon#about to read 4, iclass 26, count 0 2006.285.10:45:25.17#ibcon#read 4, iclass 26, count 0 2006.285.10:45:25.17#ibcon#about to read 5, iclass 26, count 0 2006.285.10:45:25.17#ibcon#read 5, iclass 26, count 0 2006.285.10:45:25.17#ibcon#about to read 6, iclass 26, count 0 2006.285.10:45:25.17#ibcon#read 6, iclass 26, count 0 2006.285.10:45:25.17#ibcon#end of sib2, iclass 26, count 0 2006.285.10:45:25.17#ibcon#*after write, iclass 26, count 0 2006.285.10:45:25.17#ibcon#*before return 0, iclass 26, count 0 2006.285.10:45:25.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:45:25.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.10:45:25.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:45:25.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:45:25.17$vck44/vbbw=wide 2006.285.10:45:25.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.10:45:25.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.10:45:25.17#ibcon#ireg 8 cls_cnt 0 2006.285.10:45:25.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:45:25.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:45:25.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:45:25.24#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:45:25.24#ibcon#first serial, iclass 28, count 0 2006.285.10:45:25.24#ibcon#enter sib2, iclass 28, count 0 2006.285.10:45:25.24#ibcon#flushed, iclass 28, count 0 2006.285.10:45:25.24#ibcon#about to write, iclass 28, count 0 2006.285.10:45:25.24#ibcon#wrote, iclass 28, count 0 2006.285.10:45:25.24#ibcon#about to read 3, iclass 28, count 0 2006.285.10:45:25.26#ibcon#read 3, iclass 28, count 0 2006.285.10:45:25.26#ibcon#about to read 4, iclass 28, count 0 2006.285.10:45:25.26#ibcon#read 4, iclass 28, count 0 2006.285.10:45:25.26#ibcon#about to read 5, iclass 28, count 0 2006.285.10:45:25.26#ibcon#read 5, iclass 28, count 0 2006.285.10:45:25.26#ibcon#about to read 6, iclass 28, count 0 2006.285.10:45:25.26#ibcon#read 6, iclass 28, count 0 2006.285.10:45:25.26#ibcon#end of sib2, iclass 28, count 0 2006.285.10:45:25.26#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:45:25.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:45:25.26#ibcon#[27=BW32\r\n] 2006.285.10:45:25.26#ibcon#*before write, iclass 28, count 0 2006.285.10:45:25.26#ibcon#enter sib2, iclass 28, count 0 2006.285.10:45:25.26#ibcon#flushed, iclass 28, count 0 2006.285.10:45:25.26#ibcon#about to write, iclass 28, count 0 2006.285.10:45:25.26#ibcon#wrote, iclass 28, count 0 2006.285.10:45:25.26#ibcon#about to read 3, iclass 28, count 0 2006.285.10:45:25.29#ibcon#read 3, iclass 28, count 0 2006.285.10:45:25.29#ibcon#about to read 4, iclass 28, count 0 2006.285.10:45:25.29#ibcon#read 4, iclass 28, count 0 2006.285.10:45:25.29#ibcon#about to read 5, iclass 28, count 0 2006.285.10:45:25.29#ibcon#read 5, iclass 28, count 0 2006.285.10:45:25.29#ibcon#about to read 6, iclass 28, count 0 2006.285.10:45:25.29#ibcon#read 6, iclass 28, count 0 2006.285.10:45:25.29#ibcon#end of sib2, iclass 28, count 0 2006.285.10:45:25.29#ibcon#*after write, iclass 28, count 0 2006.285.10:45:25.29#ibcon#*before return 0, iclass 28, count 0 2006.285.10:45:25.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:45:25.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:45:25.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:45:25.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:45:25.29$setupk4/ifdk4 2006.285.10:45:25.29$ifdk4/lo= 2006.285.10:45:25.29$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:45:25.29$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:45:25.29$ifdk4/patch= 2006.285.10:45:25.29$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:45:25.29$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:45:25.29$setupk4/!*+20s 2006.285.10:45:34.39#abcon#<5=/05 1.3 2.0 19.66 921015.0\r\n> 2006.285.10:45:34.41#abcon#{5=INTERFACE CLEAR} 2006.285.10:45:34.47#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:45:39.80$setupk4/"tpicd 2006.285.10:45:39.80$setupk4/echo=off 2006.285.10:45:39.80$setupk4/xlog=off 2006.285.10:45:39.80:!2006.285.10:49:15 2006.285.10:45:43.14#trakl#Source acquired 2006.285.10:45:44.14#flagr#flagr/antenna,acquired 2006.285.10:49:15.00:preob 2006.285.10:49:15.14/onsource/TRACKING 2006.285.10:49:15.14:!2006.285.10:49:25 2006.285.10:49:25.00:"tape 2006.285.10:49:25.00:"st=record 2006.285.10:49:25.00:data_valid=on 2006.285.10:49:25.00:midob 2006.285.10:49:26.14/onsource/TRACKING 2006.285.10:49:26.14/wx/19.64,1014.9,91 2006.285.10:49:26.31/cable/+6.4872E-03 2006.285.10:49:27.40/va/01,07,usb,yes,36,39 2006.285.10:49:27.40/va/02,06,usb,yes,36,37 2006.285.10:49:27.40/va/03,07,usb,yes,36,38 2006.285.10:49:27.40/va/04,06,usb,yes,37,39 2006.285.10:49:27.40/va/05,03,usb,yes,37,37 2006.285.10:49:27.40/va/06,04,usb,yes,33,33 2006.285.10:49:27.40/va/07,04,usb,yes,34,34 2006.285.10:49:27.40/va/08,03,usb,yes,35,42 2006.285.10:49:27.63/valo/01,524.99,yes,locked 2006.285.10:49:27.63/valo/02,534.99,yes,locked 2006.285.10:49:27.63/valo/03,564.99,yes,locked 2006.285.10:49:27.63/valo/04,624.99,yes,locked 2006.285.10:49:27.63/valo/05,734.99,yes,locked 2006.285.10:49:27.63/valo/06,814.99,yes,locked 2006.285.10:49:27.63/valo/07,864.99,yes,locked 2006.285.10:49:27.63/valo/08,884.99,yes,locked 2006.285.10:49:28.72/vb/01,04,usb,yes,33,31 2006.285.10:49:28.72/vb/02,05,usb,yes,31,31 2006.285.10:49:28.72/vb/03,04,usb,yes,32,35 2006.285.10:49:28.72/vb/04,05,usb,yes,32,31 2006.285.10:49:28.72/vb/05,04,usb,yes,29,31 2006.285.10:49:28.72/vb/06,03,usb,yes,41,36 2006.285.10:49:28.72/vb/07,04,usb,yes,33,33 2006.285.10:49:28.72/vb/08,04,usb,yes,30,34 2006.285.10:49:28.95/vblo/01,629.99,yes,locked 2006.285.10:49:28.95/vblo/02,634.99,yes,locked 2006.285.10:49:28.95/vblo/03,649.99,yes,locked 2006.285.10:49:28.95/vblo/04,679.99,yes,locked 2006.285.10:49:28.95/vblo/05,709.99,yes,locked 2006.285.10:49:28.95/vblo/06,719.99,yes,locked 2006.285.10:49:28.95/vblo/07,734.99,yes,locked 2006.285.10:49:28.95/vblo/08,744.99,yes,locked 2006.285.10:49:29.10/vabw/8 2006.285.10:49:29.25/vbbw/8 2006.285.10:49:29.34/xfe/off,on,12.0 2006.285.10:49:29.72/ifatt/23,28,28,28 2006.285.10:49:30.07/fmout-gps/S +2.72E-07 2006.285.10:49:30.09:!2006.285.10:50:05 2006.285.10:50:05.01:data_valid=off 2006.285.10:50:05.01:"et 2006.285.10:50:05.01:!+3s 2006.285.10:50:08.02:"tape 2006.285.10:50:08.02:postob 2006.285.10:50:08.27/cable/+6.4867E-03 2006.285.10:50:08.27/wx/19.63,1014.9,92 2006.285.10:50:08.33/fmout-gps/S +2.71E-07 2006.285.10:50:08.33:scan_name=285-1055,jd0610,100 2006.285.10:50:08.33:source=2128-123,213135.26,-120704.8,2000.0,cw 2006.285.10:50:10.14#flagr#flagr/antenna,new-source 2006.285.10:50:10.14:checkk5 2006.285.10:50:10.48/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:50:10.93/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:50:11.27/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:50:11.60/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:50:12.02/chk_obsdata//k5ts1/T2851049??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.10:50:12.38/chk_obsdata//k5ts2/T2851049??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.10:50:12.80/chk_obsdata//k5ts3/T2851049??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.10:50:13.14/chk_obsdata//k5ts4/T2851049??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.10:50:13.90/k5log//k5ts1_log_newline 2006.285.10:50:14.67/k5log//k5ts2_log_newline 2006.285.10:50:15.47/k5log//k5ts3_log_newline 2006.285.10:50:16.44/k5log//k5ts4_log_newline 2006.285.10:50:16.46/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:50:16.46:setupk4=1 2006.285.10:50:16.46$setupk4/echo=on 2006.285.10:50:16.46$setupk4/pcalon 2006.285.10:50:16.46$pcalon/"no phase cal control is implemented here 2006.285.10:50:16.46$setupk4/"tpicd=stop 2006.285.10:50:16.46$setupk4/"rec=synch_on 2006.285.10:50:16.46$setupk4/"rec_mode=128 2006.285.10:50:16.46$setupk4/!* 2006.285.10:50:16.46$setupk4/recpk4 2006.285.10:50:16.47$recpk4/recpatch= 2006.285.10:50:16.47$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:50:16.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:50:16.47$setupk4/vck44 2006.285.10:50:16.47$vck44/valo=1,524.99 2006.285.10:50:16.47#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.10:50:16.47#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.10:50:16.47#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:16.47#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:50:16.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:50:16.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:50:16.47#ibcon#enter wrdev, iclass 37, count 0 2006.285.10:50:16.47#ibcon#first serial, iclass 37, count 0 2006.285.10:50:16.47#ibcon#enter sib2, iclass 37, count 0 2006.285.10:50:16.47#ibcon#flushed, iclass 37, count 0 2006.285.10:50:16.47#ibcon#about to write, iclass 37, count 0 2006.285.10:50:16.47#ibcon#wrote, iclass 37, count 0 2006.285.10:50:16.47#ibcon#about to read 3, iclass 37, count 0 2006.285.10:50:16.48#ibcon#read 3, iclass 37, count 0 2006.285.10:50:16.48#ibcon#about to read 4, iclass 37, count 0 2006.285.10:50:16.48#ibcon#read 4, iclass 37, count 0 2006.285.10:50:16.48#ibcon#about to read 5, iclass 37, count 0 2006.285.10:50:16.48#ibcon#read 5, iclass 37, count 0 2006.285.10:50:16.48#ibcon#about to read 6, iclass 37, count 0 2006.285.10:50:16.48#ibcon#read 6, iclass 37, count 0 2006.285.10:50:16.48#ibcon#end of sib2, iclass 37, count 0 2006.285.10:50:16.48#ibcon#*mode == 0, iclass 37, count 0 2006.285.10:50:16.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.10:50:16.48#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:50:16.48#ibcon#*before write, iclass 37, count 0 2006.285.10:50:16.48#ibcon#enter sib2, iclass 37, count 0 2006.285.10:50:16.48#ibcon#flushed, iclass 37, count 0 2006.285.10:50:16.48#ibcon#about to write, iclass 37, count 0 2006.285.10:50:16.48#ibcon#wrote, iclass 37, count 0 2006.285.10:50:16.48#ibcon#about to read 3, iclass 37, count 0 2006.285.10:50:16.53#ibcon#read 3, iclass 37, count 0 2006.285.10:50:16.53#ibcon#about to read 4, iclass 37, count 0 2006.285.10:50:16.53#ibcon#read 4, iclass 37, count 0 2006.285.10:50:16.53#ibcon#about to read 5, iclass 37, count 0 2006.285.10:50:16.53#ibcon#read 5, iclass 37, count 0 2006.285.10:50:16.53#ibcon#about to read 6, iclass 37, count 0 2006.285.10:50:16.53#ibcon#read 6, iclass 37, count 0 2006.285.10:50:16.53#ibcon#end of sib2, iclass 37, count 0 2006.285.10:50:16.53#ibcon#*after write, iclass 37, count 0 2006.285.10:50:16.53#ibcon#*before return 0, iclass 37, count 0 2006.285.10:50:16.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:50:16.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.10:50:16.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.10:50:16.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.10:50:16.53$vck44/va=1,7 2006.285.10:50:16.53#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.10:50:16.53#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.10:50:16.53#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:16.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:50:16.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:50:16.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:50:16.53#ibcon#enter wrdev, iclass 39, count 2 2006.285.10:50:16.53#ibcon#first serial, iclass 39, count 2 2006.285.10:50:16.53#ibcon#enter sib2, iclass 39, count 2 2006.285.10:50:16.53#ibcon#flushed, iclass 39, count 2 2006.285.10:50:16.53#ibcon#about to write, iclass 39, count 2 2006.285.10:50:16.53#ibcon#wrote, iclass 39, count 2 2006.285.10:50:16.53#ibcon#about to read 3, iclass 39, count 2 2006.285.10:50:16.55#ibcon#read 3, iclass 39, count 2 2006.285.10:50:16.55#ibcon#about to read 4, iclass 39, count 2 2006.285.10:50:16.55#ibcon#read 4, iclass 39, count 2 2006.285.10:50:16.55#ibcon#about to read 5, iclass 39, count 2 2006.285.10:50:16.55#ibcon#read 5, iclass 39, count 2 2006.285.10:50:16.55#ibcon#about to read 6, iclass 39, count 2 2006.285.10:50:16.55#ibcon#read 6, iclass 39, count 2 2006.285.10:50:16.55#ibcon#end of sib2, iclass 39, count 2 2006.285.10:50:16.55#ibcon#*mode == 0, iclass 39, count 2 2006.285.10:50:16.55#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.10:50:16.55#ibcon#[25=AT01-07\r\n] 2006.285.10:50:16.55#ibcon#*before write, iclass 39, count 2 2006.285.10:50:16.55#ibcon#enter sib2, iclass 39, count 2 2006.285.10:50:16.55#ibcon#flushed, iclass 39, count 2 2006.285.10:50:16.55#ibcon#about to write, iclass 39, count 2 2006.285.10:50:16.55#ibcon#wrote, iclass 39, count 2 2006.285.10:50:16.55#ibcon#about to read 3, iclass 39, count 2 2006.285.10:50:16.58#ibcon#read 3, iclass 39, count 2 2006.285.10:50:16.58#ibcon#about to read 4, iclass 39, count 2 2006.285.10:50:16.58#ibcon#read 4, iclass 39, count 2 2006.285.10:50:16.58#ibcon#about to read 5, iclass 39, count 2 2006.285.10:50:16.58#ibcon#read 5, iclass 39, count 2 2006.285.10:50:16.58#ibcon#about to read 6, iclass 39, count 2 2006.285.10:50:16.58#ibcon#read 6, iclass 39, count 2 2006.285.10:50:16.58#ibcon#end of sib2, iclass 39, count 2 2006.285.10:50:16.58#ibcon#*after write, iclass 39, count 2 2006.285.10:50:16.58#ibcon#*before return 0, iclass 39, count 2 2006.285.10:50:16.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:50:16.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.10:50:16.58#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.10:50:16.58#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:16.58#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:50:16.70#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:50:16.70#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:50:16.70#ibcon#enter wrdev, iclass 39, count 0 2006.285.10:50:16.70#ibcon#first serial, iclass 39, count 0 2006.285.10:50:16.70#ibcon#enter sib2, iclass 39, count 0 2006.285.10:50:16.70#ibcon#flushed, iclass 39, count 0 2006.285.10:50:16.70#ibcon#about to write, iclass 39, count 0 2006.285.10:50:16.70#ibcon#wrote, iclass 39, count 0 2006.285.10:50:16.70#ibcon#about to read 3, iclass 39, count 0 2006.285.10:50:16.72#ibcon#read 3, iclass 39, count 0 2006.285.10:50:16.72#ibcon#about to read 4, iclass 39, count 0 2006.285.10:50:16.72#ibcon#read 4, iclass 39, count 0 2006.285.10:50:16.72#ibcon#about to read 5, iclass 39, count 0 2006.285.10:50:16.72#ibcon#read 5, iclass 39, count 0 2006.285.10:50:16.72#ibcon#about to read 6, iclass 39, count 0 2006.285.10:50:16.72#ibcon#read 6, iclass 39, count 0 2006.285.10:50:16.72#ibcon#end of sib2, iclass 39, count 0 2006.285.10:50:16.72#ibcon#*mode == 0, iclass 39, count 0 2006.285.10:50:16.72#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.10:50:16.72#ibcon#[25=USB\r\n] 2006.285.10:50:16.72#ibcon#*before write, iclass 39, count 0 2006.285.10:50:16.72#ibcon#enter sib2, iclass 39, count 0 2006.285.10:50:16.72#ibcon#flushed, iclass 39, count 0 2006.285.10:50:16.72#ibcon#about to write, iclass 39, count 0 2006.285.10:50:16.72#ibcon#wrote, iclass 39, count 0 2006.285.10:50:16.72#ibcon#about to read 3, iclass 39, count 0 2006.285.10:50:16.75#ibcon#read 3, iclass 39, count 0 2006.285.10:50:16.75#ibcon#about to read 4, iclass 39, count 0 2006.285.10:50:16.75#ibcon#read 4, iclass 39, count 0 2006.285.10:50:16.75#ibcon#about to read 5, iclass 39, count 0 2006.285.10:50:16.75#ibcon#read 5, iclass 39, count 0 2006.285.10:50:16.75#ibcon#about to read 6, iclass 39, count 0 2006.285.10:50:16.75#ibcon#read 6, iclass 39, count 0 2006.285.10:50:16.75#ibcon#end of sib2, iclass 39, count 0 2006.285.10:50:16.75#ibcon#*after write, iclass 39, count 0 2006.285.10:50:16.75#ibcon#*before return 0, iclass 39, count 0 2006.285.10:50:16.75#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:50:16.75#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.10:50:16.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.10:50:16.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.10:50:16.75$vck44/valo=2,534.99 2006.285.10:50:16.75#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.10:50:16.75#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.10:50:16.75#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:16.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:50:16.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:50:16.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:50:16.75#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:50:16.75#ibcon#first serial, iclass 3, count 0 2006.285.10:50:16.75#ibcon#enter sib2, iclass 3, count 0 2006.285.10:50:16.75#ibcon#flushed, iclass 3, count 0 2006.285.10:50:16.75#ibcon#about to write, iclass 3, count 0 2006.285.10:50:16.75#ibcon#wrote, iclass 3, count 0 2006.285.10:50:16.75#ibcon#about to read 3, iclass 3, count 0 2006.285.10:50:16.77#ibcon#read 3, iclass 3, count 0 2006.285.10:50:16.77#ibcon#about to read 4, iclass 3, count 0 2006.285.10:50:16.77#ibcon#read 4, iclass 3, count 0 2006.285.10:50:16.77#ibcon#about to read 5, iclass 3, count 0 2006.285.10:50:16.77#ibcon#read 5, iclass 3, count 0 2006.285.10:50:16.77#ibcon#about to read 6, iclass 3, count 0 2006.285.10:50:16.77#ibcon#read 6, iclass 3, count 0 2006.285.10:50:16.77#ibcon#end of sib2, iclass 3, count 0 2006.285.10:50:16.77#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:50:16.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:50:16.77#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:50:16.77#ibcon#*before write, iclass 3, count 0 2006.285.10:50:16.77#ibcon#enter sib2, iclass 3, count 0 2006.285.10:50:16.77#ibcon#flushed, iclass 3, count 0 2006.285.10:50:16.77#ibcon#about to write, iclass 3, count 0 2006.285.10:50:16.77#ibcon#wrote, iclass 3, count 0 2006.285.10:50:16.77#ibcon#about to read 3, iclass 3, count 0 2006.285.10:50:16.81#ibcon#read 3, iclass 3, count 0 2006.285.10:50:16.81#ibcon#about to read 4, iclass 3, count 0 2006.285.10:50:16.81#ibcon#read 4, iclass 3, count 0 2006.285.10:50:16.81#ibcon#about to read 5, iclass 3, count 0 2006.285.10:50:16.81#ibcon#read 5, iclass 3, count 0 2006.285.10:50:16.81#ibcon#about to read 6, iclass 3, count 0 2006.285.10:50:16.81#ibcon#read 6, iclass 3, count 0 2006.285.10:50:16.81#ibcon#end of sib2, iclass 3, count 0 2006.285.10:50:16.81#ibcon#*after write, iclass 3, count 0 2006.285.10:50:16.81#ibcon#*before return 0, iclass 3, count 0 2006.285.10:50:16.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:50:16.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:50:16.81#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:50:16.81#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:50:16.81$vck44/va=2,6 2006.285.10:50:16.81#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.10:50:16.81#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.10:50:16.81#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:16.81#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:50:16.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:50:16.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:50:16.87#ibcon#enter wrdev, iclass 5, count 2 2006.285.10:50:16.87#ibcon#first serial, iclass 5, count 2 2006.285.10:50:16.87#ibcon#enter sib2, iclass 5, count 2 2006.285.10:50:16.87#ibcon#flushed, iclass 5, count 2 2006.285.10:50:16.87#ibcon#about to write, iclass 5, count 2 2006.285.10:50:16.87#ibcon#wrote, iclass 5, count 2 2006.285.10:50:16.87#ibcon#about to read 3, iclass 5, count 2 2006.285.10:50:16.89#ibcon#read 3, iclass 5, count 2 2006.285.10:50:16.89#ibcon#about to read 4, iclass 5, count 2 2006.285.10:50:16.89#ibcon#read 4, iclass 5, count 2 2006.285.10:50:16.89#ibcon#about to read 5, iclass 5, count 2 2006.285.10:50:16.89#ibcon#read 5, iclass 5, count 2 2006.285.10:50:16.89#ibcon#about to read 6, iclass 5, count 2 2006.285.10:50:16.89#ibcon#read 6, iclass 5, count 2 2006.285.10:50:16.89#ibcon#end of sib2, iclass 5, count 2 2006.285.10:50:16.89#ibcon#*mode == 0, iclass 5, count 2 2006.285.10:50:16.89#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.10:50:16.89#ibcon#[25=AT02-06\r\n] 2006.285.10:50:16.89#ibcon#*before write, iclass 5, count 2 2006.285.10:50:16.89#ibcon#enter sib2, iclass 5, count 2 2006.285.10:50:16.89#ibcon#flushed, iclass 5, count 2 2006.285.10:50:16.89#ibcon#about to write, iclass 5, count 2 2006.285.10:50:16.89#ibcon#wrote, iclass 5, count 2 2006.285.10:50:16.89#ibcon#about to read 3, iclass 5, count 2 2006.285.10:50:16.92#ibcon#read 3, iclass 5, count 2 2006.285.10:50:16.92#ibcon#about to read 4, iclass 5, count 2 2006.285.10:50:16.92#ibcon#read 4, iclass 5, count 2 2006.285.10:50:16.92#ibcon#about to read 5, iclass 5, count 2 2006.285.10:50:16.92#ibcon#read 5, iclass 5, count 2 2006.285.10:50:16.92#ibcon#about to read 6, iclass 5, count 2 2006.285.10:50:16.92#ibcon#read 6, iclass 5, count 2 2006.285.10:50:16.92#ibcon#end of sib2, iclass 5, count 2 2006.285.10:50:16.92#ibcon#*after write, iclass 5, count 2 2006.285.10:50:16.92#ibcon#*before return 0, iclass 5, count 2 2006.285.10:50:16.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:50:16.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:50:16.92#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.10:50:16.92#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:16.92#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:50:17.04#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:50:17.04#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:50:17.04#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:50:17.04#ibcon#first serial, iclass 5, count 0 2006.285.10:50:17.04#ibcon#enter sib2, iclass 5, count 0 2006.285.10:50:17.04#ibcon#flushed, iclass 5, count 0 2006.285.10:50:17.04#ibcon#about to write, iclass 5, count 0 2006.285.10:50:17.04#ibcon#wrote, iclass 5, count 0 2006.285.10:50:17.04#ibcon#about to read 3, iclass 5, count 0 2006.285.10:50:17.06#ibcon#read 3, iclass 5, count 0 2006.285.10:50:17.06#ibcon#about to read 4, iclass 5, count 0 2006.285.10:50:17.06#ibcon#read 4, iclass 5, count 0 2006.285.10:50:17.06#ibcon#about to read 5, iclass 5, count 0 2006.285.10:50:17.06#ibcon#read 5, iclass 5, count 0 2006.285.10:50:17.06#ibcon#about to read 6, iclass 5, count 0 2006.285.10:50:17.06#ibcon#read 6, iclass 5, count 0 2006.285.10:50:17.06#ibcon#end of sib2, iclass 5, count 0 2006.285.10:50:17.06#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:50:17.06#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:50:17.06#ibcon#[25=USB\r\n] 2006.285.10:50:17.06#ibcon#*before write, iclass 5, count 0 2006.285.10:50:17.06#ibcon#enter sib2, iclass 5, count 0 2006.285.10:50:17.06#ibcon#flushed, iclass 5, count 0 2006.285.10:50:17.06#ibcon#about to write, iclass 5, count 0 2006.285.10:50:17.06#ibcon#wrote, iclass 5, count 0 2006.285.10:50:17.06#ibcon#about to read 3, iclass 5, count 0 2006.285.10:50:17.09#ibcon#read 3, iclass 5, count 0 2006.285.10:50:17.09#ibcon#about to read 4, iclass 5, count 0 2006.285.10:50:17.09#ibcon#read 4, iclass 5, count 0 2006.285.10:50:17.09#ibcon#about to read 5, iclass 5, count 0 2006.285.10:50:17.09#ibcon#read 5, iclass 5, count 0 2006.285.10:50:17.09#ibcon#about to read 6, iclass 5, count 0 2006.285.10:50:17.09#ibcon#read 6, iclass 5, count 0 2006.285.10:50:17.09#ibcon#end of sib2, iclass 5, count 0 2006.285.10:50:17.09#ibcon#*after write, iclass 5, count 0 2006.285.10:50:17.09#ibcon#*before return 0, iclass 5, count 0 2006.285.10:50:17.09#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:50:17.09#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:50:17.09#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:50:17.09#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:50:17.09$vck44/valo=3,564.99 2006.285.10:50:17.09#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.10:50:17.09#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.10:50:17.09#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:17.09#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:50:17.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:50:17.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:50:17.09#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:50:17.09#ibcon#first serial, iclass 7, count 0 2006.285.10:50:17.09#ibcon#enter sib2, iclass 7, count 0 2006.285.10:50:17.09#ibcon#flushed, iclass 7, count 0 2006.285.10:50:17.09#ibcon#about to write, iclass 7, count 0 2006.285.10:50:17.09#ibcon#wrote, iclass 7, count 0 2006.285.10:50:17.09#ibcon#about to read 3, iclass 7, count 0 2006.285.10:50:17.11#ibcon#read 3, iclass 7, count 0 2006.285.10:50:17.11#ibcon#about to read 4, iclass 7, count 0 2006.285.10:50:17.11#ibcon#read 4, iclass 7, count 0 2006.285.10:50:17.11#ibcon#about to read 5, iclass 7, count 0 2006.285.10:50:17.11#ibcon#read 5, iclass 7, count 0 2006.285.10:50:17.11#ibcon#about to read 6, iclass 7, count 0 2006.285.10:50:17.11#ibcon#read 6, iclass 7, count 0 2006.285.10:50:17.11#ibcon#end of sib2, iclass 7, count 0 2006.285.10:50:17.11#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:50:17.11#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:50:17.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:50:17.11#ibcon#*before write, iclass 7, count 0 2006.285.10:50:17.11#ibcon#enter sib2, iclass 7, count 0 2006.285.10:50:17.11#ibcon#flushed, iclass 7, count 0 2006.285.10:50:17.11#ibcon#about to write, iclass 7, count 0 2006.285.10:50:17.11#ibcon#wrote, iclass 7, count 0 2006.285.10:50:17.11#ibcon#about to read 3, iclass 7, count 0 2006.285.10:50:17.15#ibcon#read 3, iclass 7, count 0 2006.285.10:50:17.15#ibcon#about to read 4, iclass 7, count 0 2006.285.10:50:17.15#ibcon#read 4, iclass 7, count 0 2006.285.10:50:17.15#ibcon#about to read 5, iclass 7, count 0 2006.285.10:50:17.15#ibcon#read 5, iclass 7, count 0 2006.285.10:50:17.15#ibcon#about to read 6, iclass 7, count 0 2006.285.10:50:17.15#ibcon#read 6, iclass 7, count 0 2006.285.10:50:17.15#ibcon#end of sib2, iclass 7, count 0 2006.285.10:50:17.15#ibcon#*after write, iclass 7, count 0 2006.285.10:50:17.15#ibcon#*before return 0, iclass 7, count 0 2006.285.10:50:17.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:50:17.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:50:17.15#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:50:17.15#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:50:17.15$vck44/va=3,7 2006.285.10:50:17.15#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.10:50:17.15#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.10:50:17.15#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:17.15#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:50:17.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:50:17.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:50:17.21#ibcon#enter wrdev, iclass 11, count 2 2006.285.10:50:17.21#ibcon#first serial, iclass 11, count 2 2006.285.10:50:17.21#ibcon#enter sib2, iclass 11, count 2 2006.285.10:50:17.21#ibcon#flushed, iclass 11, count 2 2006.285.10:50:17.21#ibcon#about to write, iclass 11, count 2 2006.285.10:50:17.21#ibcon#wrote, iclass 11, count 2 2006.285.10:50:17.21#ibcon#about to read 3, iclass 11, count 2 2006.285.10:50:17.23#ibcon#read 3, iclass 11, count 2 2006.285.10:50:17.23#ibcon#about to read 4, iclass 11, count 2 2006.285.10:50:17.23#ibcon#read 4, iclass 11, count 2 2006.285.10:50:17.23#ibcon#about to read 5, iclass 11, count 2 2006.285.10:50:17.23#ibcon#read 5, iclass 11, count 2 2006.285.10:50:17.23#ibcon#about to read 6, iclass 11, count 2 2006.285.10:50:17.23#ibcon#read 6, iclass 11, count 2 2006.285.10:50:17.23#ibcon#end of sib2, iclass 11, count 2 2006.285.10:50:17.23#ibcon#*mode == 0, iclass 11, count 2 2006.285.10:50:17.23#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.10:50:17.23#ibcon#[25=AT03-07\r\n] 2006.285.10:50:17.23#ibcon#*before write, iclass 11, count 2 2006.285.10:50:17.23#ibcon#enter sib2, iclass 11, count 2 2006.285.10:50:17.23#ibcon#flushed, iclass 11, count 2 2006.285.10:50:17.23#ibcon#about to write, iclass 11, count 2 2006.285.10:50:17.23#ibcon#wrote, iclass 11, count 2 2006.285.10:50:17.23#ibcon#about to read 3, iclass 11, count 2 2006.285.10:50:17.26#ibcon#read 3, iclass 11, count 2 2006.285.10:50:17.26#ibcon#about to read 4, iclass 11, count 2 2006.285.10:50:17.26#ibcon#read 4, iclass 11, count 2 2006.285.10:50:17.26#ibcon#about to read 5, iclass 11, count 2 2006.285.10:50:17.26#ibcon#read 5, iclass 11, count 2 2006.285.10:50:17.26#ibcon#about to read 6, iclass 11, count 2 2006.285.10:50:17.26#ibcon#read 6, iclass 11, count 2 2006.285.10:50:17.26#ibcon#end of sib2, iclass 11, count 2 2006.285.10:50:17.26#ibcon#*after write, iclass 11, count 2 2006.285.10:50:17.26#ibcon#*before return 0, iclass 11, count 2 2006.285.10:50:17.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:50:17.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:50:17.26#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.10:50:17.26#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:17.26#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:50:17.38#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:50:17.38#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:50:17.38#ibcon#enter wrdev, iclass 11, count 0 2006.285.10:50:17.38#ibcon#first serial, iclass 11, count 0 2006.285.10:50:17.38#ibcon#enter sib2, iclass 11, count 0 2006.285.10:50:17.38#ibcon#flushed, iclass 11, count 0 2006.285.10:50:17.38#ibcon#about to write, iclass 11, count 0 2006.285.10:50:17.38#ibcon#wrote, iclass 11, count 0 2006.285.10:50:17.38#ibcon#about to read 3, iclass 11, count 0 2006.285.10:50:17.40#ibcon#read 3, iclass 11, count 0 2006.285.10:50:17.40#ibcon#about to read 4, iclass 11, count 0 2006.285.10:50:17.40#ibcon#read 4, iclass 11, count 0 2006.285.10:50:17.40#ibcon#about to read 5, iclass 11, count 0 2006.285.10:50:17.40#ibcon#read 5, iclass 11, count 0 2006.285.10:50:17.40#ibcon#about to read 6, iclass 11, count 0 2006.285.10:50:17.40#ibcon#read 6, iclass 11, count 0 2006.285.10:50:17.40#ibcon#end of sib2, iclass 11, count 0 2006.285.10:50:17.40#ibcon#*mode == 0, iclass 11, count 0 2006.285.10:50:17.40#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.10:50:17.40#ibcon#[25=USB\r\n] 2006.285.10:50:17.40#ibcon#*before write, iclass 11, count 0 2006.285.10:50:17.40#ibcon#enter sib2, iclass 11, count 0 2006.285.10:50:17.40#ibcon#flushed, iclass 11, count 0 2006.285.10:50:17.40#ibcon#about to write, iclass 11, count 0 2006.285.10:50:17.40#ibcon#wrote, iclass 11, count 0 2006.285.10:50:17.40#ibcon#about to read 3, iclass 11, count 0 2006.285.10:50:17.43#ibcon#read 3, iclass 11, count 0 2006.285.10:50:17.43#ibcon#about to read 4, iclass 11, count 0 2006.285.10:50:17.43#ibcon#read 4, iclass 11, count 0 2006.285.10:50:17.43#ibcon#about to read 5, iclass 11, count 0 2006.285.10:50:17.43#ibcon#read 5, iclass 11, count 0 2006.285.10:50:17.43#ibcon#about to read 6, iclass 11, count 0 2006.285.10:50:17.43#ibcon#read 6, iclass 11, count 0 2006.285.10:50:17.43#ibcon#end of sib2, iclass 11, count 0 2006.285.10:50:17.43#ibcon#*after write, iclass 11, count 0 2006.285.10:50:17.43#ibcon#*before return 0, iclass 11, count 0 2006.285.10:50:17.43#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:50:17.43#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:50:17.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.10:50:17.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.10:50:17.43$vck44/valo=4,624.99 2006.285.10:50:17.43#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.10:50:17.43#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.10:50:17.43#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:17.43#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:50:17.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:50:17.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:50:17.43#ibcon#enter wrdev, iclass 13, count 0 2006.285.10:50:17.43#ibcon#first serial, iclass 13, count 0 2006.285.10:50:17.43#ibcon#enter sib2, iclass 13, count 0 2006.285.10:50:17.43#ibcon#flushed, iclass 13, count 0 2006.285.10:50:17.43#ibcon#about to write, iclass 13, count 0 2006.285.10:50:17.43#ibcon#wrote, iclass 13, count 0 2006.285.10:50:17.43#ibcon#about to read 3, iclass 13, count 0 2006.285.10:50:17.45#ibcon#read 3, iclass 13, count 0 2006.285.10:50:17.45#ibcon#about to read 4, iclass 13, count 0 2006.285.10:50:17.45#ibcon#read 4, iclass 13, count 0 2006.285.10:50:17.45#ibcon#about to read 5, iclass 13, count 0 2006.285.10:50:17.45#ibcon#read 5, iclass 13, count 0 2006.285.10:50:17.45#ibcon#about to read 6, iclass 13, count 0 2006.285.10:50:17.45#ibcon#read 6, iclass 13, count 0 2006.285.10:50:17.45#ibcon#end of sib2, iclass 13, count 0 2006.285.10:50:17.45#ibcon#*mode == 0, iclass 13, count 0 2006.285.10:50:17.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.10:50:17.45#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:50:17.45#ibcon#*before write, iclass 13, count 0 2006.285.10:50:17.45#ibcon#enter sib2, iclass 13, count 0 2006.285.10:50:17.45#ibcon#flushed, iclass 13, count 0 2006.285.10:50:17.45#ibcon#about to write, iclass 13, count 0 2006.285.10:50:17.45#ibcon#wrote, iclass 13, count 0 2006.285.10:50:17.45#ibcon#about to read 3, iclass 13, count 0 2006.285.10:50:17.49#ibcon#read 3, iclass 13, count 0 2006.285.10:50:17.49#ibcon#about to read 4, iclass 13, count 0 2006.285.10:50:17.49#ibcon#read 4, iclass 13, count 0 2006.285.10:50:17.49#ibcon#about to read 5, iclass 13, count 0 2006.285.10:50:17.49#ibcon#read 5, iclass 13, count 0 2006.285.10:50:17.49#ibcon#about to read 6, iclass 13, count 0 2006.285.10:50:17.49#ibcon#read 6, iclass 13, count 0 2006.285.10:50:17.49#ibcon#end of sib2, iclass 13, count 0 2006.285.10:50:17.49#ibcon#*after write, iclass 13, count 0 2006.285.10:50:17.49#ibcon#*before return 0, iclass 13, count 0 2006.285.10:50:17.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:50:17.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:50:17.49#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.10:50:17.49#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.10:50:17.49$vck44/va=4,6 2006.285.10:50:17.49#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.10:50:17.49#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.10:50:17.49#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:17.49#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:50:17.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:50:17.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:50:17.55#ibcon#enter wrdev, iclass 15, count 2 2006.285.10:50:17.55#ibcon#first serial, iclass 15, count 2 2006.285.10:50:17.55#ibcon#enter sib2, iclass 15, count 2 2006.285.10:50:17.55#ibcon#flushed, iclass 15, count 2 2006.285.10:50:17.55#ibcon#about to write, iclass 15, count 2 2006.285.10:50:17.55#ibcon#wrote, iclass 15, count 2 2006.285.10:50:17.55#ibcon#about to read 3, iclass 15, count 2 2006.285.10:50:17.57#ibcon#read 3, iclass 15, count 2 2006.285.10:50:17.57#ibcon#about to read 4, iclass 15, count 2 2006.285.10:50:17.57#ibcon#read 4, iclass 15, count 2 2006.285.10:50:17.57#ibcon#about to read 5, iclass 15, count 2 2006.285.10:50:17.57#ibcon#read 5, iclass 15, count 2 2006.285.10:50:17.57#ibcon#about to read 6, iclass 15, count 2 2006.285.10:50:17.57#ibcon#read 6, iclass 15, count 2 2006.285.10:50:17.57#ibcon#end of sib2, iclass 15, count 2 2006.285.10:50:17.57#ibcon#*mode == 0, iclass 15, count 2 2006.285.10:50:17.57#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.10:50:17.57#ibcon#[25=AT04-06\r\n] 2006.285.10:50:17.57#ibcon#*before write, iclass 15, count 2 2006.285.10:50:17.57#ibcon#enter sib2, iclass 15, count 2 2006.285.10:50:17.57#ibcon#flushed, iclass 15, count 2 2006.285.10:50:17.57#ibcon#about to write, iclass 15, count 2 2006.285.10:50:17.57#ibcon#wrote, iclass 15, count 2 2006.285.10:50:17.57#ibcon#about to read 3, iclass 15, count 2 2006.285.10:50:17.60#ibcon#read 3, iclass 15, count 2 2006.285.10:50:17.60#ibcon#about to read 4, iclass 15, count 2 2006.285.10:50:17.60#ibcon#read 4, iclass 15, count 2 2006.285.10:50:17.60#ibcon#about to read 5, iclass 15, count 2 2006.285.10:50:17.60#ibcon#read 5, iclass 15, count 2 2006.285.10:50:17.60#ibcon#about to read 6, iclass 15, count 2 2006.285.10:50:17.60#ibcon#read 6, iclass 15, count 2 2006.285.10:50:17.60#ibcon#end of sib2, iclass 15, count 2 2006.285.10:50:17.60#ibcon#*after write, iclass 15, count 2 2006.285.10:50:17.60#ibcon#*before return 0, iclass 15, count 2 2006.285.10:50:17.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:50:17.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:50:17.60#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.10:50:17.60#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:17.60#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:50:17.72#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:50:17.72#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:50:17.72#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:50:17.72#ibcon#first serial, iclass 15, count 0 2006.285.10:50:17.72#ibcon#enter sib2, iclass 15, count 0 2006.285.10:50:17.72#ibcon#flushed, iclass 15, count 0 2006.285.10:50:17.72#ibcon#about to write, iclass 15, count 0 2006.285.10:50:17.72#ibcon#wrote, iclass 15, count 0 2006.285.10:50:17.72#ibcon#about to read 3, iclass 15, count 0 2006.285.10:50:17.74#ibcon#read 3, iclass 15, count 0 2006.285.10:50:17.74#ibcon#about to read 4, iclass 15, count 0 2006.285.10:50:17.74#ibcon#read 4, iclass 15, count 0 2006.285.10:50:17.74#ibcon#about to read 5, iclass 15, count 0 2006.285.10:50:17.74#ibcon#read 5, iclass 15, count 0 2006.285.10:50:17.74#ibcon#about to read 6, iclass 15, count 0 2006.285.10:50:17.74#ibcon#read 6, iclass 15, count 0 2006.285.10:50:17.74#ibcon#end of sib2, iclass 15, count 0 2006.285.10:50:17.74#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:50:17.74#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:50:17.74#ibcon#[25=USB\r\n] 2006.285.10:50:17.74#ibcon#*before write, iclass 15, count 0 2006.285.10:50:17.74#ibcon#enter sib2, iclass 15, count 0 2006.285.10:50:17.74#ibcon#flushed, iclass 15, count 0 2006.285.10:50:17.74#ibcon#about to write, iclass 15, count 0 2006.285.10:50:17.74#ibcon#wrote, iclass 15, count 0 2006.285.10:50:17.74#ibcon#about to read 3, iclass 15, count 0 2006.285.10:50:17.77#ibcon#read 3, iclass 15, count 0 2006.285.10:50:17.77#ibcon#about to read 4, iclass 15, count 0 2006.285.10:50:17.77#ibcon#read 4, iclass 15, count 0 2006.285.10:50:17.77#ibcon#about to read 5, iclass 15, count 0 2006.285.10:50:17.77#ibcon#read 5, iclass 15, count 0 2006.285.10:50:17.77#ibcon#about to read 6, iclass 15, count 0 2006.285.10:50:17.77#ibcon#read 6, iclass 15, count 0 2006.285.10:50:17.77#ibcon#end of sib2, iclass 15, count 0 2006.285.10:50:17.77#ibcon#*after write, iclass 15, count 0 2006.285.10:50:17.77#ibcon#*before return 0, iclass 15, count 0 2006.285.10:50:17.77#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:50:17.77#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:50:17.77#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:50:17.77#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:50:17.77$vck44/valo=5,734.99 2006.285.10:50:17.77#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.10:50:17.77#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.10:50:17.77#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:17.77#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:50:17.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:50:17.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:50:17.77#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:50:17.77#ibcon#first serial, iclass 17, count 0 2006.285.10:50:17.77#ibcon#enter sib2, iclass 17, count 0 2006.285.10:50:17.77#ibcon#flushed, iclass 17, count 0 2006.285.10:50:17.77#ibcon#about to write, iclass 17, count 0 2006.285.10:50:17.77#ibcon#wrote, iclass 17, count 0 2006.285.10:50:17.77#ibcon#about to read 3, iclass 17, count 0 2006.285.10:50:17.79#ibcon#read 3, iclass 17, count 0 2006.285.10:50:17.79#ibcon#about to read 4, iclass 17, count 0 2006.285.10:50:17.79#ibcon#read 4, iclass 17, count 0 2006.285.10:50:17.79#ibcon#about to read 5, iclass 17, count 0 2006.285.10:50:17.79#ibcon#read 5, iclass 17, count 0 2006.285.10:50:17.79#ibcon#about to read 6, iclass 17, count 0 2006.285.10:50:17.79#ibcon#read 6, iclass 17, count 0 2006.285.10:50:17.79#ibcon#end of sib2, iclass 17, count 0 2006.285.10:50:17.79#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:50:17.79#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:50:17.79#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:50:17.79#ibcon#*before write, iclass 17, count 0 2006.285.10:50:17.79#ibcon#enter sib2, iclass 17, count 0 2006.285.10:50:17.79#ibcon#flushed, iclass 17, count 0 2006.285.10:50:17.79#ibcon#about to write, iclass 17, count 0 2006.285.10:50:17.79#ibcon#wrote, iclass 17, count 0 2006.285.10:50:17.79#ibcon#about to read 3, iclass 17, count 0 2006.285.10:50:17.83#ibcon#read 3, iclass 17, count 0 2006.285.10:50:17.83#ibcon#about to read 4, iclass 17, count 0 2006.285.10:50:17.83#ibcon#read 4, iclass 17, count 0 2006.285.10:50:17.83#ibcon#about to read 5, iclass 17, count 0 2006.285.10:50:17.83#ibcon#read 5, iclass 17, count 0 2006.285.10:50:17.83#ibcon#about to read 6, iclass 17, count 0 2006.285.10:50:17.83#ibcon#read 6, iclass 17, count 0 2006.285.10:50:17.83#ibcon#end of sib2, iclass 17, count 0 2006.285.10:50:17.83#ibcon#*after write, iclass 17, count 0 2006.285.10:50:17.83#ibcon#*before return 0, iclass 17, count 0 2006.285.10:50:17.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:50:17.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:50:17.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:50:17.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:50:17.83$vck44/va=5,3 2006.285.10:50:17.83#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.10:50:17.83#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.10:50:17.83#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:17.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:50:17.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:50:17.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:50:17.89#ibcon#enter wrdev, iclass 19, count 2 2006.285.10:50:17.89#ibcon#first serial, iclass 19, count 2 2006.285.10:50:17.89#ibcon#enter sib2, iclass 19, count 2 2006.285.10:50:17.89#ibcon#flushed, iclass 19, count 2 2006.285.10:50:17.89#ibcon#about to write, iclass 19, count 2 2006.285.10:50:17.89#ibcon#wrote, iclass 19, count 2 2006.285.10:50:17.89#ibcon#about to read 3, iclass 19, count 2 2006.285.10:50:17.91#ibcon#read 3, iclass 19, count 2 2006.285.10:50:17.91#ibcon#about to read 4, iclass 19, count 2 2006.285.10:50:17.91#ibcon#read 4, iclass 19, count 2 2006.285.10:50:17.91#ibcon#about to read 5, iclass 19, count 2 2006.285.10:50:17.91#ibcon#read 5, iclass 19, count 2 2006.285.10:50:17.91#ibcon#about to read 6, iclass 19, count 2 2006.285.10:50:17.91#ibcon#read 6, iclass 19, count 2 2006.285.10:50:17.91#ibcon#end of sib2, iclass 19, count 2 2006.285.10:50:17.91#ibcon#*mode == 0, iclass 19, count 2 2006.285.10:50:17.91#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.10:50:17.91#ibcon#[25=AT05-03\r\n] 2006.285.10:50:17.91#ibcon#*before write, iclass 19, count 2 2006.285.10:50:17.91#ibcon#enter sib2, iclass 19, count 2 2006.285.10:50:17.91#ibcon#flushed, iclass 19, count 2 2006.285.10:50:17.91#ibcon#about to write, iclass 19, count 2 2006.285.10:50:17.91#ibcon#wrote, iclass 19, count 2 2006.285.10:50:17.91#ibcon#about to read 3, iclass 19, count 2 2006.285.10:50:17.94#ibcon#read 3, iclass 19, count 2 2006.285.10:50:17.94#ibcon#about to read 4, iclass 19, count 2 2006.285.10:50:17.94#ibcon#read 4, iclass 19, count 2 2006.285.10:50:17.94#ibcon#about to read 5, iclass 19, count 2 2006.285.10:50:17.94#ibcon#read 5, iclass 19, count 2 2006.285.10:50:17.94#ibcon#about to read 6, iclass 19, count 2 2006.285.10:50:17.94#ibcon#read 6, iclass 19, count 2 2006.285.10:50:17.94#ibcon#end of sib2, iclass 19, count 2 2006.285.10:50:17.94#ibcon#*after write, iclass 19, count 2 2006.285.10:50:17.94#ibcon#*before return 0, iclass 19, count 2 2006.285.10:50:17.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:50:17.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:50:17.94#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.10:50:17.94#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:17.94#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:50:18.06#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:50:18.06#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:50:18.06#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:50:18.06#ibcon#first serial, iclass 19, count 0 2006.285.10:50:18.06#ibcon#enter sib2, iclass 19, count 0 2006.285.10:50:18.06#ibcon#flushed, iclass 19, count 0 2006.285.10:50:18.06#ibcon#about to write, iclass 19, count 0 2006.285.10:50:18.06#ibcon#wrote, iclass 19, count 0 2006.285.10:50:18.06#ibcon#about to read 3, iclass 19, count 0 2006.285.10:50:18.08#ibcon#read 3, iclass 19, count 0 2006.285.10:50:18.08#ibcon#about to read 4, iclass 19, count 0 2006.285.10:50:18.08#ibcon#read 4, iclass 19, count 0 2006.285.10:50:18.08#ibcon#about to read 5, iclass 19, count 0 2006.285.10:50:18.08#ibcon#read 5, iclass 19, count 0 2006.285.10:50:18.08#ibcon#about to read 6, iclass 19, count 0 2006.285.10:50:18.08#ibcon#read 6, iclass 19, count 0 2006.285.10:50:18.08#ibcon#end of sib2, iclass 19, count 0 2006.285.10:50:18.08#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:50:18.08#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:50:18.08#ibcon#[25=USB\r\n] 2006.285.10:50:18.08#ibcon#*before write, iclass 19, count 0 2006.285.10:50:18.08#ibcon#enter sib2, iclass 19, count 0 2006.285.10:50:18.08#ibcon#flushed, iclass 19, count 0 2006.285.10:50:18.08#ibcon#about to write, iclass 19, count 0 2006.285.10:50:18.08#ibcon#wrote, iclass 19, count 0 2006.285.10:50:18.08#ibcon#about to read 3, iclass 19, count 0 2006.285.10:50:18.11#ibcon#read 3, iclass 19, count 0 2006.285.10:50:18.11#ibcon#about to read 4, iclass 19, count 0 2006.285.10:50:18.11#ibcon#read 4, iclass 19, count 0 2006.285.10:50:18.11#ibcon#about to read 5, iclass 19, count 0 2006.285.10:50:18.11#ibcon#read 5, iclass 19, count 0 2006.285.10:50:18.11#ibcon#about to read 6, iclass 19, count 0 2006.285.10:50:18.11#ibcon#read 6, iclass 19, count 0 2006.285.10:50:18.11#ibcon#end of sib2, iclass 19, count 0 2006.285.10:50:18.11#ibcon#*after write, iclass 19, count 0 2006.285.10:50:18.11#ibcon#*before return 0, iclass 19, count 0 2006.285.10:50:18.11#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:50:18.11#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:50:18.11#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:50:18.11#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:50:18.11$vck44/valo=6,814.99 2006.285.10:50:18.11#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.10:50:18.11#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.10:50:18.11#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:18.11#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:50:18.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:50:18.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:50:18.11#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:50:18.11#ibcon#first serial, iclass 21, count 0 2006.285.10:50:18.11#ibcon#enter sib2, iclass 21, count 0 2006.285.10:50:18.11#ibcon#flushed, iclass 21, count 0 2006.285.10:50:18.11#ibcon#about to write, iclass 21, count 0 2006.285.10:50:18.11#ibcon#wrote, iclass 21, count 0 2006.285.10:50:18.11#ibcon#about to read 3, iclass 21, count 0 2006.285.10:50:18.13#ibcon#read 3, iclass 21, count 0 2006.285.10:50:18.13#ibcon#about to read 4, iclass 21, count 0 2006.285.10:50:18.13#ibcon#read 4, iclass 21, count 0 2006.285.10:50:18.13#ibcon#about to read 5, iclass 21, count 0 2006.285.10:50:18.13#ibcon#read 5, iclass 21, count 0 2006.285.10:50:18.13#ibcon#about to read 6, iclass 21, count 0 2006.285.10:50:18.13#ibcon#read 6, iclass 21, count 0 2006.285.10:50:18.13#ibcon#end of sib2, iclass 21, count 0 2006.285.10:50:18.13#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:50:18.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:50:18.13#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:50:18.13#ibcon#*before write, iclass 21, count 0 2006.285.10:50:18.13#ibcon#enter sib2, iclass 21, count 0 2006.285.10:50:18.13#ibcon#flushed, iclass 21, count 0 2006.285.10:50:18.13#ibcon#about to write, iclass 21, count 0 2006.285.10:50:18.13#ibcon#wrote, iclass 21, count 0 2006.285.10:50:18.13#ibcon#about to read 3, iclass 21, count 0 2006.285.10:50:18.17#ibcon#read 3, iclass 21, count 0 2006.285.10:50:18.17#ibcon#about to read 4, iclass 21, count 0 2006.285.10:50:18.17#ibcon#read 4, iclass 21, count 0 2006.285.10:50:18.17#ibcon#about to read 5, iclass 21, count 0 2006.285.10:50:18.17#ibcon#read 5, iclass 21, count 0 2006.285.10:50:18.17#ibcon#about to read 6, iclass 21, count 0 2006.285.10:50:18.17#ibcon#read 6, iclass 21, count 0 2006.285.10:50:18.17#ibcon#end of sib2, iclass 21, count 0 2006.285.10:50:18.17#ibcon#*after write, iclass 21, count 0 2006.285.10:50:18.17#ibcon#*before return 0, iclass 21, count 0 2006.285.10:50:18.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:50:18.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:50:18.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:50:18.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:50:18.17$vck44/va=6,4 2006.285.10:50:18.17#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.10:50:18.17#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.10:50:18.17#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:18.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:50:18.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:50:18.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:50:18.23#ibcon#enter wrdev, iclass 23, count 2 2006.285.10:50:18.23#ibcon#first serial, iclass 23, count 2 2006.285.10:50:18.23#ibcon#enter sib2, iclass 23, count 2 2006.285.10:50:18.23#ibcon#flushed, iclass 23, count 2 2006.285.10:50:18.23#ibcon#about to write, iclass 23, count 2 2006.285.10:50:18.23#ibcon#wrote, iclass 23, count 2 2006.285.10:50:18.23#ibcon#about to read 3, iclass 23, count 2 2006.285.10:50:18.25#ibcon#read 3, iclass 23, count 2 2006.285.10:50:18.25#ibcon#about to read 4, iclass 23, count 2 2006.285.10:50:18.25#ibcon#read 4, iclass 23, count 2 2006.285.10:50:18.25#ibcon#about to read 5, iclass 23, count 2 2006.285.10:50:18.25#ibcon#read 5, iclass 23, count 2 2006.285.10:50:18.25#ibcon#about to read 6, iclass 23, count 2 2006.285.10:50:18.25#ibcon#read 6, iclass 23, count 2 2006.285.10:50:18.25#ibcon#end of sib2, iclass 23, count 2 2006.285.10:50:18.25#ibcon#*mode == 0, iclass 23, count 2 2006.285.10:50:18.25#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.10:50:18.25#ibcon#[25=AT06-04\r\n] 2006.285.10:50:18.25#ibcon#*before write, iclass 23, count 2 2006.285.10:50:18.25#ibcon#enter sib2, iclass 23, count 2 2006.285.10:50:18.25#ibcon#flushed, iclass 23, count 2 2006.285.10:50:18.25#ibcon#about to write, iclass 23, count 2 2006.285.10:50:18.25#ibcon#wrote, iclass 23, count 2 2006.285.10:50:18.25#ibcon#about to read 3, iclass 23, count 2 2006.285.10:50:18.28#ibcon#read 3, iclass 23, count 2 2006.285.10:50:18.28#ibcon#about to read 4, iclass 23, count 2 2006.285.10:50:18.28#ibcon#read 4, iclass 23, count 2 2006.285.10:50:18.28#ibcon#about to read 5, iclass 23, count 2 2006.285.10:50:18.28#ibcon#read 5, iclass 23, count 2 2006.285.10:50:18.28#ibcon#about to read 6, iclass 23, count 2 2006.285.10:50:18.28#ibcon#read 6, iclass 23, count 2 2006.285.10:50:18.28#ibcon#end of sib2, iclass 23, count 2 2006.285.10:50:18.28#ibcon#*after write, iclass 23, count 2 2006.285.10:50:18.28#ibcon#*before return 0, iclass 23, count 2 2006.285.10:50:18.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:50:18.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:50:18.28#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.10:50:18.28#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:18.28#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:50:18.40#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:50:18.40#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:50:18.40#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:50:18.40#ibcon#first serial, iclass 23, count 0 2006.285.10:50:18.40#ibcon#enter sib2, iclass 23, count 0 2006.285.10:50:18.40#ibcon#flushed, iclass 23, count 0 2006.285.10:50:18.40#ibcon#about to write, iclass 23, count 0 2006.285.10:50:18.40#ibcon#wrote, iclass 23, count 0 2006.285.10:50:18.40#ibcon#about to read 3, iclass 23, count 0 2006.285.10:50:18.42#ibcon#read 3, iclass 23, count 0 2006.285.10:50:18.42#ibcon#about to read 4, iclass 23, count 0 2006.285.10:50:18.42#ibcon#read 4, iclass 23, count 0 2006.285.10:50:18.42#ibcon#about to read 5, iclass 23, count 0 2006.285.10:50:18.42#ibcon#read 5, iclass 23, count 0 2006.285.10:50:18.42#ibcon#about to read 6, iclass 23, count 0 2006.285.10:50:18.42#ibcon#read 6, iclass 23, count 0 2006.285.10:50:18.42#ibcon#end of sib2, iclass 23, count 0 2006.285.10:50:18.42#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:50:18.42#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:50:18.42#ibcon#[25=USB\r\n] 2006.285.10:50:18.42#ibcon#*before write, iclass 23, count 0 2006.285.10:50:18.42#ibcon#enter sib2, iclass 23, count 0 2006.285.10:50:18.42#ibcon#flushed, iclass 23, count 0 2006.285.10:50:18.42#ibcon#about to write, iclass 23, count 0 2006.285.10:50:18.42#ibcon#wrote, iclass 23, count 0 2006.285.10:50:18.42#ibcon#about to read 3, iclass 23, count 0 2006.285.10:50:18.45#ibcon#read 3, iclass 23, count 0 2006.285.10:50:18.45#ibcon#about to read 4, iclass 23, count 0 2006.285.10:50:18.45#ibcon#read 4, iclass 23, count 0 2006.285.10:50:18.45#ibcon#about to read 5, iclass 23, count 0 2006.285.10:50:18.45#ibcon#read 5, iclass 23, count 0 2006.285.10:50:18.45#ibcon#about to read 6, iclass 23, count 0 2006.285.10:50:18.45#ibcon#read 6, iclass 23, count 0 2006.285.10:50:18.45#ibcon#end of sib2, iclass 23, count 0 2006.285.10:50:18.45#ibcon#*after write, iclass 23, count 0 2006.285.10:50:18.45#ibcon#*before return 0, iclass 23, count 0 2006.285.10:50:18.45#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:50:18.45#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:50:18.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:50:18.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:50:18.45$vck44/valo=7,864.99 2006.285.10:50:18.45#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.10:50:18.45#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.10:50:18.45#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:18.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:50:18.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:50:18.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:50:18.45#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:50:18.45#ibcon#first serial, iclass 25, count 0 2006.285.10:50:18.45#ibcon#enter sib2, iclass 25, count 0 2006.285.10:50:18.45#ibcon#flushed, iclass 25, count 0 2006.285.10:50:18.45#ibcon#about to write, iclass 25, count 0 2006.285.10:50:18.45#ibcon#wrote, iclass 25, count 0 2006.285.10:50:18.45#ibcon#about to read 3, iclass 25, count 0 2006.285.10:50:18.47#ibcon#read 3, iclass 25, count 0 2006.285.10:50:18.47#ibcon#about to read 4, iclass 25, count 0 2006.285.10:50:18.47#ibcon#read 4, iclass 25, count 0 2006.285.10:50:18.47#ibcon#about to read 5, iclass 25, count 0 2006.285.10:50:18.47#ibcon#read 5, iclass 25, count 0 2006.285.10:50:18.47#ibcon#about to read 6, iclass 25, count 0 2006.285.10:50:18.47#ibcon#read 6, iclass 25, count 0 2006.285.10:50:18.47#ibcon#end of sib2, iclass 25, count 0 2006.285.10:50:18.47#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:50:18.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:50:18.47#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:50:18.47#ibcon#*before write, iclass 25, count 0 2006.285.10:50:18.47#ibcon#enter sib2, iclass 25, count 0 2006.285.10:50:18.47#ibcon#flushed, iclass 25, count 0 2006.285.10:50:18.47#ibcon#about to write, iclass 25, count 0 2006.285.10:50:18.47#ibcon#wrote, iclass 25, count 0 2006.285.10:50:18.47#ibcon#about to read 3, iclass 25, count 0 2006.285.10:50:18.51#ibcon#read 3, iclass 25, count 0 2006.285.10:50:18.51#ibcon#about to read 4, iclass 25, count 0 2006.285.10:50:18.51#ibcon#read 4, iclass 25, count 0 2006.285.10:50:18.51#ibcon#about to read 5, iclass 25, count 0 2006.285.10:50:18.51#ibcon#read 5, iclass 25, count 0 2006.285.10:50:18.51#ibcon#about to read 6, iclass 25, count 0 2006.285.10:50:18.51#ibcon#read 6, iclass 25, count 0 2006.285.10:50:18.51#ibcon#end of sib2, iclass 25, count 0 2006.285.10:50:18.51#ibcon#*after write, iclass 25, count 0 2006.285.10:50:18.51#ibcon#*before return 0, iclass 25, count 0 2006.285.10:50:18.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:50:18.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:50:18.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:50:18.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:50:18.51$vck44/va=7,4 2006.285.10:50:18.51#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.10:50:18.51#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.10:50:18.51#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:18.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:50:18.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:50:18.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:50:18.57#ibcon#enter wrdev, iclass 27, count 2 2006.285.10:50:18.57#ibcon#first serial, iclass 27, count 2 2006.285.10:50:18.57#ibcon#enter sib2, iclass 27, count 2 2006.285.10:50:18.57#ibcon#flushed, iclass 27, count 2 2006.285.10:50:18.57#ibcon#about to write, iclass 27, count 2 2006.285.10:50:18.57#ibcon#wrote, iclass 27, count 2 2006.285.10:50:18.57#ibcon#about to read 3, iclass 27, count 2 2006.285.10:50:18.59#ibcon#read 3, iclass 27, count 2 2006.285.10:50:18.59#ibcon#about to read 4, iclass 27, count 2 2006.285.10:50:18.59#ibcon#read 4, iclass 27, count 2 2006.285.10:50:18.59#ibcon#about to read 5, iclass 27, count 2 2006.285.10:50:18.59#ibcon#read 5, iclass 27, count 2 2006.285.10:50:18.59#ibcon#about to read 6, iclass 27, count 2 2006.285.10:50:18.59#ibcon#read 6, iclass 27, count 2 2006.285.10:50:18.59#ibcon#end of sib2, iclass 27, count 2 2006.285.10:50:18.59#ibcon#*mode == 0, iclass 27, count 2 2006.285.10:50:18.59#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.10:50:18.59#ibcon#[25=AT07-04\r\n] 2006.285.10:50:18.59#ibcon#*before write, iclass 27, count 2 2006.285.10:50:18.59#ibcon#enter sib2, iclass 27, count 2 2006.285.10:50:18.59#ibcon#flushed, iclass 27, count 2 2006.285.10:50:18.59#ibcon#about to write, iclass 27, count 2 2006.285.10:50:18.59#ibcon#wrote, iclass 27, count 2 2006.285.10:50:18.59#ibcon#about to read 3, iclass 27, count 2 2006.285.10:50:18.62#ibcon#read 3, iclass 27, count 2 2006.285.10:50:18.62#ibcon#about to read 4, iclass 27, count 2 2006.285.10:50:18.62#ibcon#read 4, iclass 27, count 2 2006.285.10:50:18.62#ibcon#about to read 5, iclass 27, count 2 2006.285.10:50:18.62#ibcon#read 5, iclass 27, count 2 2006.285.10:50:18.62#ibcon#about to read 6, iclass 27, count 2 2006.285.10:50:18.62#ibcon#read 6, iclass 27, count 2 2006.285.10:50:18.62#ibcon#end of sib2, iclass 27, count 2 2006.285.10:50:18.62#ibcon#*after write, iclass 27, count 2 2006.285.10:50:18.62#ibcon#*before return 0, iclass 27, count 2 2006.285.10:50:18.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:50:18.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:50:18.62#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.10:50:18.62#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:18.62#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:50:18.74#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:50:18.74#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:50:18.74#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:50:18.74#ibcon#first serial, iclass 27, count 0 2006.285.10:50:18.74#ibcon#enter sib2, iclass 27, count 0 2006.285.10:50:18.74#ibcon#flushed, iclass 27, count 0 2006.285.10:50:18.74#ibcon#about to write, iclass 27, count 0 2006.285.10:50:18.74#ibcon#wrote, iclass 27, count 0 2006.285.10:50:18.74#ibcon#about to read 3, iclass 27, count 0 2006.285.10:50:18.76#ibcon#read 3, iclass 27, count 0 2006.285.10:50:18.76#ibcon#about to read 4, iclass 27, count 0 2006.285.10:50:18.76#ibcon#read 4, iclass 27, count 0 2006.285.10:50:18.76#ibcon#about to read 5, iclass 27, count 0 2006.285.10:50:18.76#ibcon#read 5, iclass 27, count 0 2006.285.10:50:18.76#ibcon#about to read 6, iclass 27, count 0 2006.285.10:50:18.76#ibcon#read 6, iclass 27, count 0 2006.285.10:50:18.76#ibcon#end of sib2, iclass 27, count 0 2006.285.10:50:18.76#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:50:18.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:50:18.76#ibcon#[25=USB\r\n] 2006.285.10:50:18.76#ibcon#*before write, iclass 27, count 0 2006.285.10:50:18.76#ibcon#enter sib2, iclass 27, count 0 2006.285.10:50:18.76#ibcon#flushed, iclass 27, count 0 2006.285.10:50:18.76#ibcon#about to write, iclass 27, count 0 2006.285.10:50:18.76#ibcon#wrote, iclass 27, count 0 2006.285.10:50:18.76#ibcon#about to read 3, iclass 27, count 0 2006.285.10:50:18.79#ibcon#read 3, iclass 27, count 0 2006.285.10:50:18.79#ibcon#about to read 4, iclass 27, count 0 2006.285.10:50:18.79#ibcon#read 4, iclass 27, count 0 2006.285.10:50:18.79#ibcon#about to read 5, iclass 27, count 0 2006.285.10:50:18.79#ibcon#read 5, iclass 27, count 0 2006.285.10:50:18.79#ibcon#about to read 6, iclass 27, count 0 2006.285.10:50:18.79#ibcon#read 6, iclass 27, count 0 2006.285.10:50:18.79#ibcon#end of sib2, iclass 27, count 0 2006.285.10:50:18.79#ibcon#*after write, iclass 27, count 0 2006.285.10:50:18.79#ibcon#*before return 0, iclass 27, count 0 2006.285.10:50:18.79#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:50:18.79#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:50:18.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:50:18.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:50:18.79$vck44/valo=8,884.99 2006.285.10:50:18.79#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.10:50:18.79#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.10:50:18.79#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:18.79#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:50:18.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:50:18.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:50:18.79#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:50:18.79#ibcon#first serial, iclass 29, count 0 2006.285.10:50:18.79#ibcon#enter sib2, iclass 29, count 0 2006.285.10:50:18.79#ibcon#flushed, iclass 29, count 0 2006.285.10:50:18.79#ibcon#about to write, iclass 29, count 0 2006.285.10:50:18.79#ibcon#wrote, iclass 29, count 0 2006.285.10:50:18.79#ibcon#about to read 3, iclass 29, count 0 2006.285.10:50:18.81#ibcon#read 3, iclass 29, count 0 2006.285.10:50:18.81#ibcon#about to read 4, iclass 29, count 0 2006.285.10:50:18.81#ibcon#read 4, iclass 29, count 0 2006.285.10:50:18.81#ibcon#about to read 5, iclass 29, count 0 2006.285.10:50:18.81#ibcon#read 5, iclass 29, count 0 2006.285.10:50:18.81#ibcon#about to read 6, iclass 29, count 0 2006.285.10:50:18.81#ibcon#read 6, iclass 29, count 0 2006.285.10:50:18.81#ibcon#end of sib2, iclass 29, count 0 2006.285.10:50:18.81#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:50:18.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:50:18.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:50:18.81#ibcon#*before write, iclass 29, count 0 2006.285.10:50:18.81#ibcon#enter sib2, iclass 29, count 0 2006.285.10:50:18.81#ibcon#flushed, iclass 29, count 0 2006.285.10:50:18.81#ibcon#about to write, iclass 29, count 0 2006.285.10:50:18.81#ibcon#wrote, iclass 29, count 0 2006.285.10:50:18.81#ibcon#about to read 3, iclass 29, count 0 2006.285.10:50:18.85#ibcon#read 3, iclass 29, count 0 2006.285.10:50:18.85#ibcon#about to read 4, iclass 29, count 0 2006.285.10:50:18.85#ibcon#read 4, iclass 29, count 0 2006.285.10:50:18.85#ibcon#about to read 5, iclass 29, count 0 2006.285.10:50:18.85#ibcon#read 5, iclass 29, count 0 2006.285.10:50:18.85#ibcon#about to read 6, iclass 29, count 0 2006.285.10:50:18.85#ibcon#read 6, iclass 29, count 0 2006.285.10:50:18.85#ibcon#end of sib2, iclass 29, count 0 2006.285.10:50:18.85#ibcon#*after write, iclass 29, count 0 2006.285.10:50:18.85#ibcon#*before return 0, iclass 29, count 0 2006.285.10:50:18.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:50:18.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:50:18.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:50:18.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:50:18.85$vck44/va=8,3 2006.285.10:50:18.85#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.10:50:18.85#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.10:50:18.85#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:18.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:50:18.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:50:18.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:50:18.91#ibcon#enter wrdev, iclass 31, count 2 2006.285.10:50:18.91#ibcon#first serial, iclass 31, count 2 2006.285.10:50:18.91#ibcon#enter sib2, iclass 31, count 2 2006.285.10:50:18.91#ibcon#flushed, iclass 31, count 2 2006.285.10:50:18.91#ibcon#about to write, iclass 31, count 2 2006.285.10:50:18.91#ibcon#wrote, iclass 31, count 2 2006.285.10:50:18.91#ibcon#about to read 3, iclass 31, count 2 2006.285.10:50:18.93#ibcon#read 3, iclass 31, count 2 2006.285.10:50:18.93#ibcon#about to read 4, iclass 31, count 2 2006.285.10:50:18.93#ibcon#read 4, iclass 31, count 2 2006.285.10:50:18.93#ibcon#about to read 5, iclass 31, count 2 2006.285.10:50:18.93#ibcon#read 5, iclass 31, count 2 2006.285.10:50:18.93#ibcon#about to read 6, iclass 31, count 2 2006.285.10:50:18.93#ibcon#read 6, iclass 31, count 2 2006.285.10:50:18.93#ibcon#end of sib2, iclass 31, count 2 2006.285.10:50:18.93#ibcon#*mode == 0, iclass 31, count 2 2006.285.10:50:18.93#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.10:50:18.93#ibcon#[25=AT08-03\r\n] 2006.285.10:50:18.93#ibcon#*before write, iclass 31, count 2 2006.285.10:50:18.93#ibcon#enter sib2, iclass 31, count 2 2006.285.10:50:18.93#ibcon#flushed, iclass 31, count 2 2006.285.10:50:18.93#ibcon#about to write, iclass 31, count 2 2006.285.10:50:18.93#ibcon#wrote, iclass 31, count 2 2006.285.10:50:18.93#ibcon#about to read 3, iclass 31, count 2 2006.285.10:50:18.96#ibcon#read 3, iclass 31, count 2 2006.285.10:50:18.96#ibcon#about to read 4, iclass 31, count 2 2006.285.10:50:18.96#ibcon#read 4, iclass 31, count 2 2006.285.10:50:18.96#ibcon#about to read 5, iclass 31, count 2 2006.285.10:50:18.96#ibcon#read 5, iclass 31, count 2 2006.285.10:50:18.96#ibcon#about to read 6, iclass 31, count 2 2006.285.10:50:18.96#ibcon#read 6, iclass 31, count 2 2006.285.10:50:18.96#ibcon#end of sib2, iclass 31, count 2 2006.285.10:50:18.96#ibcon#*after write, iclass 31, count 2 2006.285.10:50:18.96#ibcon#*before return 0, iclass 31, count 2 2006.285.10:50:18.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:50:18.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:50:18.96#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.10:50:18.96#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:18.96#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:50:19.08#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:50:19.08#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:50:19.08#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:50:19.08#ibcon#first serial, iclass 31, count 0 2006.285.10:50:19.08#ibcon#enter sib2, iclass 31, count 0 2006.285.10:50:19.08#ibcon#flushed, iclass 31, count 0 2006.285.10:50:19.08#ibcon#about to write, iclass 31, count 0 2006.285.10:50:19.08#ibcon#wrote, iclass 31, count 0 2006.285.10:50:19.08#ibcon#about to read 3, iclass 31, count 0 2006.285.10:50:19.10#ibcon#read 3, iclass 31, count 0 2006.285.10:50:19.10#ibcon#about to read 4, iclass 31, count 0 2006.285.10:50:19.10#ibcon#read 4, iclass 31, count 0 2006.285.10:50:19.10#ibcon#about to read 5, iclass 31, count 0 2006.285.10:50:19.10#ibcon#read 5, iclass 31, count 0 2006.285.10:50:19.10#ibcon#about to read 6, iclass 31, count 0 2006.285.10:50:19.10#ibcon#read 6, iclass 31, count 0 2006.285.10:50:19.10#ibcon#end of sib2, iclass 31, count 0 2006.285.10:50:19.10#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:50:19.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:50:19.10#ibcon#[25=USB\r\n] 2006.285.10:50:19.10#ibcon#*before write, iclass 31, count 0 2006.285.10:50:19.10#ibcon#enter sib2, iclass 31, count 0 2006.285.10:50:19.10#ibcon#flushed, iclass 31, count 0 2006.285.10:50:19.10#ibcon#about to write, iclass 31, count 0 2006.285.10:50:19.10#ibcon#wrote, iclass 31, count 0 2006.285.10:50:19.10#ibcon#about to read 3, iclass 31, count 0 2006.285.10:50:19.13#ibcon#read 3, iclass 31, count 0 2006.285.10:50:19.13#ibcon#about to read 4, iclass 31, count 0 2006.285.10:50:19.13#ibcon#read 4, iclass 31, count 0 2006.285.10:50:19.13#ibcon#about to read 5, iclass 31, count 0 2006.285.10:50:19.13#ibcon#read 5, iclass 31, count 0 2006.285.10:50:19.13#ibcon#about to read 6, iclass 31, count 0 2006.285.10:50:19.13#ibcon#read 6, iclass 31, count 0 2006.285.10:50:19.13#ibcon#end of sib2, iclass 31, count 0 2006.285.10:50:19.13#ibcon#*after write, iclass 31, count 0 2006.285.10:50:19.13#ibcon#*before return 0, iclass 31, count 0 2006.285.10:50:19.13#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:50:19.13#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:50:19.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:50:19.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:50:19.13$vck44/vblo=1,629.99 2006.285.10:50:19.13#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.10:50:19.13#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.10:50:19.13#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:19.13#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:50:19.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:50:19.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:50:19.13#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:50:19.13#ibcon#first serial, iclass 33, count 0 2006.285.10:50:19.13#ibcon#enter sib2, iclass 33, count 0 2006.285.10:50:19.13#ibcon#flushed, iclass 33, count 0 2006.285.10:50:19.13#ibcon#about to write, iclass 33, count 0 2006.285.10:50:19.13#ibcon#wrote, iclass 33, count 0 2006.285.10:50:19.13#ibcon#about to read 3, iclass 33, count 0 2006.285.10:50:19.15#ibcon#read 3, iclass 33, count 0 2006.285.10:50:19.15#ibcon#about to read 4, iclass 33, count 0 2006.285.10:50:19.15#ibcon#read 4, iclass 33, count 0 2006.285.10:50:19.15#ibcon#about to read 5, iclass 33, count 0 2006.285.10:50:19.15#ibcon#read 5, iclass 33, count 0 2006.285.10:50:19.15#ibcon#about to read 6, iclass 33, count 0 2006.285.10:50:19.15#ibcon#read 6, iclass 33, count 0 2006.285.10:50:19.15#ibcon#end of sib2, iclass 33, count 0 2006.285.10:50:19.15#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:50:19.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:50:19.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:50:19.15#ibcon#*before write, iclass 33, count 0 2006.285.10:50:19.15#ibcon#enter sib2, iclass 33, count 0 2006.285.10:50:19.15#ibcon#flushed, iclass 33, count 0 2006.285.10:50:19.15#ibcon#about to write, iclass 33, count 0 2006.285.10:50:19.15#ibcon#wrote, iclass 33, count 0 2006.285.10:50:19.15#ibcon#about to read 3, iclass 33, count 0 2006.285.10:50:19.19#ibcon#read 3, iclass 33, count 0 2006.285.10:50:19.19#ibcon#about to read 4, iclass 33, count 0 2006.285.10:50:19.19#ibcon#read 4, iclass 33, count 0 2006.285.10:50:19.19#ibcon#about to read 5, iclass 33, count 0 2006.285.10:50:19.19#ibcon#read 5, iclass 33, count 0 2006.285.10:50:19.19#ibcon#about to read 6, iclass 33, count 0 2006.285.10:50:19.19#ibcon#read 6, iclass 33, count 0 2006.285.10:50:19.19#ibcon#end of sib2, iclass 33, count 0 2006.285.10:50:19.19#ibcon#*after write, iclass 33, count 0 2006.285.10:50:19.19#ibcon#*before return 0, iclass 33, count 0 2006.285.10:50:19.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:50:19.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:50:19.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:50:19.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:50:19.19$vck44/vb=1,4 2006.285.10:50:19.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.10:50:19.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.10:50:19.19#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:19.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:50:19.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:50:19.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:50:19.19#ibcon#enter wrdev, iclass 36, count 2 2006.285.10:50:19.19#ibcon#first serial, iclass 36, count 2 2006.285.10:50:19.19#ibcon#enter sib2, iclass 36, count 2 2006.285.10:50:19.19#ibcon#flushed, iclass 36, count 2 2006.285.10:50:19.19#ibcon#about to write, iclass 36, count 2 2006.285.10:50:19.19#ibcon#wrote, iclass 36, count 2 2006.285.10:50:19.19#ibcon#about to read 3, iclass 36, count 2 2006.285.10:50:19.20#abcon#<5=/05 1.3 2.1 19.63 921014.9\r\n> 2006.285.10:50:19.21#ibcon#read 3, iclass 36, count 2 2006.285.10:50:19.21#ibcon#about to read 4, iclass 36, count 2 2006.285.10:50:19.21#ibcon#read 4, iclass 36, count 2 2006.285.10:50:19.21#ibcon#about to read 5, iclass 36, count 2 2006.285.10:50:19.21#ibcon#read 5, iclass 36, count 2 2006.285.10:50:19.21#ibcon#about to read 6, iclass 36, count 2 2006.285.10:50:19.21#ibcon#read 6, iclass 36, count 2 2006.285.10:50:19.21#ibcon#end of sib2, iclass 36, count 2 2006.285.10:50:19.21#ibcon#*mode == 0, iclass 36, count 2 2006.285.10:50:19.21#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.10:50:19.21#ibcon#[27=AT01-04\r\n] 2006.285.10:50:19.21#ibcon#*before write, iclass 36, count 2 2006.285.10:50:19.21#ibcon#enter sib2, iclass 36, count 2 2006.285.10:50:19.21#ibcon#flushed, iclass 36, count 2 2006.285.10:50:19.21#ibcon#about to write, iclass 36, count 2 2006.285.10:50:19.21#ibcon#wrote, iclass 36, count 2 2006.285.10:50:19.21#ibcon#about to read 3, iclass 36, count 2 2006.285.10:50:19.22#abcon#{5=INTERFACE CLEAR} 2006.285.10:50:19.24#ibcon#read 3, iclass 36, count 2 2006.285.10:50:19.24#ibcon#about to read 4, iclass 36, count 2 2006.285.10:50:19.24#ibcon#read 4, iclass 36, count 2 2006.285.10:50:19.24#ibcon#about to read 5, iclass 36, count 2 2006.285.10:50:19.24#ibcon#read 5, iclass 36, count 2 2006.285.10:50:19.24#ibcon#about to read 6, iclass 36, count 2 2006.285.10:50:19.24#ibcon#read 6, iclass 36, count 2 2006.285.10:50:19.24#ibcon#end of sib2, iclass 36, count 2 2006.285.10:50:19.24#ibcon#*after write, iclass 36, count 2 2006.285.10:50:19.24#ibcon#*before return 0, iclass 36, count 2 2006.285.10:50:19.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:50:19.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.10:50:19.24#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.10:50:19.24#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:19.24#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:50:19.28#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:50:19.36#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:50:19.36#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:50:19.36#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:50:19.36#ibcon#first serial, iclass 36, count 0 2006.285.10:50:19.36#ibcon#enter sib2, iclass 36, count 0 2006.285.10:50:19.36#ibcon#flushed, iclass 36, count 0 2006.285.10:50:19.36#ibcon#about to write, iclass 36, count 0 2006.285.10:50:19.36#ibcon#wrote, iclass 36, count 0 2006.285.10:50:19.36#ibcon#about to read 3, iclass 36, count 0 2006.285.10:50:19.38#ibcon#read 3, iclass 36, count 0 2006.285.10:50:19.38#ibcon#about to read 4, iclass 36, count 0 2006.285.10:50:19.38#ibcon#read 4, iclass 36, count 0 2006.285.10:50:19.38#ibcon#about to read 5, iclass 36, count 0 2006.285.10:50:19.38#ibcon#read 5, iclass 36, count 0 2006.285.10:50:19.38#ibcon#about to read 6, iclass 36, count 0 2006.285.10:50:19.38#ibcon#read 6, iclass 36, count 0 2006.285.10:50:19.38#ibcon#end of sib2, iclass 36, count 0 2006.285.10:50:19.38#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:50:19.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:50:19.38#ibcon#[27=USB\r\n] 2006.285.10:50:19.38#ibcon#*before write, iclass 36, count 0 2006.285.10:50:19.38#ibcon#enter sib2, iclass 36, count 0 2006.285.10:50:19.38#ibcon#flushed, iclass 36, count 0 2006.285.10:50:19.38#ibcon#about to write, iclass 36, count 0 2006.285.10:50:19.38#ibcon#wrote, iclass 36, count 0 2006.285.10:50:19.38#ibcon#about to read 3, iclass 36, count 0 2006.285.10:50:19.41#ibcon#read 3, iclass 36, count 0 2006.285.10:50:19.41#ibcon#about to read 4, iclass 36, count 0 2006.285.10:50:19.41#ibcon#read 4, iclass 36, count 0 2006.285.10:50:19.41#ibcon#about to read 5, iclass 36, count 0 2006.285.10:50:19.41#ibcon#read 5, iclass 36, count 0 2006.285.10:50:19.41#ibcon#about to read 6, iclass 36, count 0 2006.285.10:50:19.41#ibcon#read 6, iclass 36, count 0 2006.285.10:50:19.41#ibcon#end of sib2, iclass 36, count 0 2006.285.10:50:19.41#ibcon#*after write, iclass 36, count 0 2006.285.10:50:19.41#ibcon#*before return 0, iclass 36, count 0 2006.285.10:50:19.41#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:50:19.41#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.10:50:19.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:50:19.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:50:19.41$vck44/vblo=2,634.99 2006.285.10:50:19.41#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.10:50:19.41#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.10:50:19.41#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:19.41#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:50:19.41#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:50:19.41#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:50:19.41#ibcon#enter wrdev, iclass 3, count 0 2006.285.10:50:19.41#ibcon#first serial, iclass 3, count 0 2006.285.10:50:19.41#ibcon#enter sib2, iclass 3, count 0 2006.285.10:50:19.41#ibcon#flushed, iclass 3, count 0 2006.285.10:50:19.41#ibcon#about to write, iclass 3, count 0 2006.285.10:50:19.41#ibcon#wrote, iclass 3, count 0 2006.285.10:50:19.41#ibcon#about to read 3, iclass 3, count 0 2006.285.10:50:19.43#ibcon#read 3, iclass 3, count 0 2006.285.10:50:19.43#ibcon#about to read 4, iclass 3, count 0 2006.285.10:50:19.43#ibcon#read 4, iclass 3, count 0 2006.285.10:50:19.43#ibcon#about to read 5, iclass 3, count 0 2006.285.10:50:19.43#ibcon#read 5, iclass 3, count 0 2006.285.10:50:19.43#ibcon#about to read 6, iclass 3, count 0 2006.285.10:50:19.43#ibcon#read 6, iclass 3, count 0 2006.285.10:50:19.43#ibcon#end of sib2, iclass 3, count 0 2006.285.10:50:19.43#ibcon#*mode == 0, iclass 3, count 0 2006.285.10:50:19.43#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.10:50:19.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:50:19.43#ibcon#*before write, iclass 3, count 0 2006.285.10:50:19.43#ibcon#enter sib2, iclass 3, count 0 2006.285.10:50:19.43#ibcon#flushed, iclass 3, count 0 2006.285.10:50:19.43#ibcon#about to write, iclass 3, count 0 2006.285.10:50:19.43#ibcon#wrote, iclass 3, count 0 2006.285.10:50:19.43#ibcon#about to read 3, iclass 3, count 0 2006.285.10:50:19.47#ibcon#read 3, iclass 3, count 0 2006.285.10:50:19.47#ibcon#about to read 4, iclass 3, count 0 2006.285.10:50:19.47#ibcon#read 4, iclass 3, count 0 2006.285.10:50:19.47#ibcon#about to read 5, iclass 3, count 0 2006.285.10:50:19.47#ibcon#read 5, iclass 3, count 0 2006.285.10:50:19.47#ibcon#about to read 6, iclass 3, count 0 2006.285.10:50:19.47#ibcon#read 6, iclass 3, count 0 2006.285.10:50:19.47#ibcon#end of sib2, iclass 3, count 0 2006.285.10:50:19.47#ibcon#*after write, iclass 3, count 0 2006.285.10:50:19.47#ibcon#*before return 0, iclass 3, count 0 2006.285.10:50:19.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:50:19.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.10:50:19.47#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.10:50:19.47#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.10:50:19.47$vck44/vb=2,5 2006.285.10:50:19.47#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.10:50:19.47#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.10:50:19.47#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:19.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:50:19.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:50:19.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:50:19.53#ibcon#enter wrdev, iclass 5, count 2 2006.285.10:50:19.53#ibcon#first serial, iclass 5, count 2 2006.285.10:50:19.53#ibcon#enter sib2, iclass 5, count 2 2006.285.10:50:19.53#ibcon#flushed, iclass 5, count 2 2006.285.10:50:19.53#ibcon#about to write, iclass 5, count 2 2006.285.10:50:19.53#ibcon#wrote, iclass 5, count 2 2006.285.10:50:19.53#ibcon#about to read 3, iclass 5, count 2 2006.285.10:50:19.55#ibcon#read 3, iclass 5, count 2 2006.285.10:50:19.55#ibcon#about to read 4, iclass 5, count 2 2006.285.10:50:19.55#ibcon#read 4, iclass 5, count 2 2006.285.10:50:19.55#ibcon#about to read 5, iclass 5, count 2 2006.285.10:50:19.55#ibcon#read 5, iclass 5, count 2 2006.285.10:50:19.55#ibcon#about to read 6, iclass 5, count 2 2006.285.10:50:19.55#ibcon#read 6, iclass 5, count 2 2006.285.10:50:19.55#ibcon#end of sib2, iclass 5, count 2 2006.285.10:50:19.55#ibcon#*mode == 0, iclass 5, count 2 2006.285.10:50:19.55#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.10:50:19.55#ibcon#[27=AT02-05\r\n] 2006.285.10:50:19.55#ibcon#*before write, iclass 5, count 2 2006.285.10:50:19.55#ibcon#enter sib2, iclass 5, count 2 2006.285.10:50:19.55#ibcon#flushed, iclass 5, count 2 2006.285.10:50:19.55#ibcon#about to write, iclass 5, count 2 2006.285.10:50:19.55#ibcon#wrote, iclass 5, count 2 2006.285.10:50:19.55#ibcon#about to read 3, iclass 5, count 2 2006.285.10:50:19.58#ibcon#read 3, iclass 5, count 2 2006.285.10:50:19.58#ibcon#about to read 4, iclass 5, count 2 2006.285.10:50:19.58#ibcon#read 4, iclass 5, count 2 2006.285.10:50:19.58#ibcon#about to read 5, iclass 5, count 2 2006.285.10:50:19.58#ibcon#read 5, iclass 5, count 2 2006.285.10:50:19.58#ibcon#about to read 6, iclass 5, count 2 2006.285.10:50:19.58#ibcon#read 6, iclass 5, count 2 2006.285.10:50:19.58#ibcon#end of sib2, iclass 5, count 2 2006.285.10:50:19.58#ibcon#*after write, iclass 5, count 2 2006.285.10:50:19.58#ibcon#*before return 0, iclass 5, count 2 2006.285.10:50:19.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:50:19.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.10:50:19.58#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.10:50:19.58#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:19.58#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:50:19.70#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:50:19.70#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:50:19.70#ibcon#enter wrdev, iclass 5, count 0 2006.285.10:50:19.70#ibcon#first serial, iclass 5, count 0 2006.285.10:50:19.70#ibcon#enter sib2, iclass 5, count 0 2006.285.10:50:19.70#ibcon#flushed, iclass 5, count 0 2006.285.10:50:19.70#ibcon#about to write, iclass 5, count 0 2006.285.10:50:19.70#ibcon#wrote, iclass 5, count 0 2006.285.10:50:19.70#ibcon#about to read 3, iclass 5, count 0 2006.285.10:50:19.72#ibcon#read 3, iclass 5, count 0 2006.285.10:50:19.72#ibcon#about to read 4, iclass 5, count 0 2006.285.10:50:19.72#ibcon#read 4, iclass 5, count 0 2006.285.10:50:19.72#ibcon#about to read 5, iclass 5, count 0 2006.285.10:50:19.72#ibcon#read 5, iclass 5, count 0 2006.285.10:50:19.72#ibcon#about to read 6, iclass 5, count 0 2006.285.10:50:19.72#ibcon#read 6, iclass 5, count 0 2006.285.10:50:19.72#ibcon#end of sib2, iclass 5, count 0 2006.285.10:50:19.72#ibcon#*mode == 0, iclass 5, count 0 2006.285.10:50:19.72#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.10:50:19.72#ibcon#[27=USB\r\n] 2006.285.10:50:19.72#ibcon#*before write, iclass 5, count 0 2006.285.10:50:19.72#ibcon#enter sib2, iclass 5, count 0 2006.285.10:50:19.72#ibcon#flushed, iclass 5, count 0 2006.285.10:50:19.72#ibcon#about to write, iclass 5, count 0 2006.285.10:50:19.72#ibcon#wrote, iclass 5, count 0 2006.285.10:50:19.72#ibcon#about to read 3, iclass 5, count 0 2006.285.10:50:19.75#ibcon#read 3, iclass 5, count 0 2006.285.10:50:19.75#ibcon#about to read 4, iclass 5, count 0 2006.285.10:50:19.75#ibcon#read 4, iclass 5, count 0 2006.285.10:50:19.75#ibcon#about to read 5, iclass 5, count 0 2006.285.10:50:19.75#ibcon#read 5, iclass 5, count 0 2006.285.10:50:19.75#ibcon#about to read 6, iclass 5, count 0 2006.285.10:50:19.75#ibcon#read 6, iclass 5, count 0 2006.285.10:50:19.75#ibcon#end of sib2, iclass 5, count 0 2006.285.10:50:19.75#ibcon#*after write, iclass 5, count 0 2006.285.10:50:19.75#ibcon#*before return 0, iclass 5, count 0 2006.285.10:50:19.75#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:50:19.75#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.10:50:19.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.10:50:19.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.10:50:19.75$vck44/vblo=3,649.99 2006.285.10:50:19.75#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.10:50:19.75#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.10:50:19.75#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:19.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:50:19.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:50:19.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:50:19.75#ibcon#enter wrdev, iclass 7, count 0 2006.285.10:50:19.75#ibcon#first serial, iclass 7, count 0 2006.285.10:50:19.75#ibcon#enter sib2, iclass 7, count 0 2006.285.10:50:19.75#ibcon#flushed, iclass 7, count 0 2006.285.10:50:19.75#ibcon#about to write, iclass 7, count 0 2006.285.10:50:19.75#ibcon#wrote, iclass 7, count 0 2006.285.10:50:19.75#ibcon#about to read 3, iclass 7, count 0 2006.285.10:50:19.77#ibcon#read 3, iclass 7, count 0 2006.285.10:50:19.77#ibcon#about to read 4, iclass 7, count 0 2006.285.10:50:19.77#ibcon#read 4, iclass 7, count 0 2006.285.10:50:19.77#ibcon#about to read 5, iclass 7, count 0 2006.285.10:50:19.77#ibcon#read 5, iclass 7, count 0 2006.285.10:50:19.77#ibcon#about to read 6, iclass 7, count 0 2006.285.10:50:19.77#ibcon#read 6, iclass 7, count 0 2006.285.10:50:19.77#ibcon#end of sib2, iclass 7, count 0 2006.285.10:50:19.77#ibcon#*mode == 0, iclass 7, count 0 2006.285.10:50:19.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.10:50:19.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:50:19.77#ibcon#*before write, iclass 7, count 0 2006.285.10:50:19.77#ibcon#enter sib2, iclass 7, count 0 2006.285.10:50:19.77#ibcon#flushed, iclass 7, count 0 2006.285.10:50:19.77#ibcon#about to write, iclass 7, count 0 2006.285.10:50:19.77#ibcon#wrote, iclass 7, count 0 2006.285.10:50:19.77#ibcon#about to read 3, iclass 7, count 0 2006.285.10:50:19.81#ibcon#read 3, iclass 7, count 0 2006.285.10:50:19.81#ibcon#about to read 4, iclass 7, count 0 2006.285.10:50:19.81#ibcon#read 4, iclass 7, count 0 2006.285.10:50:19.81#ibcon#about to read 5, iclass 7, count 0 2006.285.10:50:19.81#ibcon#read 5, iclass 7, count 0 2006.285.10:50:19.81#ibcon#about to read 6, iclass 7, count 0 2006.285.10:50:19.81#ibcon#read 6, iclass 7, count 0 2006.285.10:50:19.81#ibcon#end of sib2, iclass 7, count 0 2006.285.10:50:19.81#ibcon#*after write, iclass 7, count 0 2006.285.10:50:19.81#ibcon#*before return 0, iclass 7, count 0 2006.285.10:50:19.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:50:19.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.10:50:19.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.10:50:19.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.10:50:19.81$vck44/vb=3,4 2006.285.10:50:19.81#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.10:50:19.81#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.10:50:19.81#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:19.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:50:19.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:50:19.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:50:19.87#ibcon#enter wrdev, iclass 11, count 2 2006.285.10:50:19.87#ibcon#first serial, iclass 11, count 2 2006.285.10:50:19.87#ibcon#enter sib2, iclass 11, count 2 2006.285.10:50:19.87#ibcon#flushed, iclass 11, count 2 2006.285.10:50:19.87#ibcon#about to write, iclass 11, count 2 2006.285.10:50:19.87#ibcon#wrote, iclass 11, count 2 2006.285.10:50:19.87#ibcon#about to read 3, iclass 11, count 2 2006.285.10:50:19.89#ibcon#read 3, iclass 11, count 2 2006.285.10:50:19.89#ibcon#about to read 4, iclass 11, count 2 2006.285.10:50:19.89#ibcon#read 4, iclass 11, count 2 2006.285.10:50:19.89#ibcon#about to read 5, iclass 11, count 2 2006.285.10:50:19.89#ibcon#read 5, iclass 11, count 2 2006.285.10:50:19.89#ibcon#about to read 6, iclass 11, count 2 2006.285.10:50:19.89#ibcon#read 6, iclass 11, count 2 2006.285.10:50:19.89#ibcon#end of sib2, iclass 11, count 2 2006.285.10:50:19.89#ibcon#*mode == 0, iclass 11, count 2 2006.285.10:50:19.89#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.10:50:19.89#ibcon#[27=AT03-04\r\n] 2006.285.10:50:19.89#ibcon#*before write, iclass 11, count 2 2006.285.10:50:19.89#ibcon#enter sib2, iclass 11, count 2 2006.285.10:50:19.89#ibcon#flushed, iclass 11, count 2 2006.285.10:50:19.89#ibcon#about to write, iclass 11, count 2 2006.285.10:50:19.89#ibcon#wrote, iclass 11, count 2 2006.285.10:50:19.89#ibcon#about to read 3, iclass 11, count 2 2006.285.10:50:19.92#ibcon#read 3, iclass 11, count 2 2006.285.10:50:19.92#ibcon#about to read 4, iclass 11, count 2 2006.285.10:50:19.92#ibcon#read 4, iclass 11, count 2 2006.285.10:50:19.92#ibcon#about to read 5, iclass 11, count 2 2006.285.10:50:19.92#ibcon#read 5, iclass 11, count 2 2006.285.10:50:19.92#ibcon#about to read 6, iclass 11, count 2 2006.285.10:50:19.92#ibcon#read 6, iclass 11, count 2 2006.285.10:50:19.92#ibcon#end of sib2, iclass 11, count 2 2006.285.10:50:19.92#ibcon#*after write, iclass 11, count 2 2006.285.10:50:19.92#ibcon#*before return 0, iclass 11, count 2 2006.285.10:50:19.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:50:19.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.10:50:19.92#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.10:50:19.92#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:19.92#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:50:20.04#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:50:20.04#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:50:20.04#ibcon#enter wrdev, iclass 11, count 0 2006.285.10:50:20.04#ibcon#first serial, iclass 11, count 0 2006.285.10:50:20.04#ibcon#enter sib2, iclass 11, count 0 2006.285.10:50:20.04#ibcon#flushed, iclass 11, count 0 2006.285.10:50:20.04#ibcon#about to write, iclass 11, count 0 2006.285.10:50:20.04#ibcon#wrote, iclass 11, count 0 2006.285.10:50:20.04#ibcon#about to read 3, iclass 11, count 0 2006.285.10:50:20.06#ibcon#read 3, iclass 11, count 0 2006.285.10:50:20.06#ibcon#about to read 4, iclass 11, count 0 2006.285.10:50:20.06#ibcon#read 4, iclass 11, count 0 2006.285.10:50:20.06#ibcon#about to read 5, iclass 11, count 0 2006.285.10:50:20.06#ibcon#read 5, iclass 11, count 0 2006.285.10:50:20.06#ibcon#about to read 6, iclass 11, count 0 2006.285.10:50:20.06#ibcon#read 6, iclass 11, count 0 2006.285.10:50:20.06#ibcon#end of sib2, iclass 11, count 0 2006.285.10:50:20.06#ibcon#*mode == 0, iclass 11, count 0 2006.285.10:50:20.06#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.10:50:20.06#ibcon#[27=USB\r\n] 2006.285.10:50:20.06#ibcon#*before write, iclass 11, count 0 2006.285.10:50:20.06#ibcon#enter sib2, iclass 11, count 0 2006.285.10:50:20.06#ibcon#flushed, iclass 11, count 0 2006.285.10:50:20.06#ibcon#about to write, iclass 11, count 0 2006.285.10:50:20.06#ibcon#wrote, iclass 11, count 0 2006.285.10:50:20.06#ibcon#about to read 3, iclass 11, count 0 2006.285.10:50:20.09#ibcon#read 3, iclass 11, count 0 2006.285.10:50:20.09#ibcon#about to read 4, iclass 11, count 0 2006.285.10:50:20.09#ibcon#read 4, iclass 11, count 0 2006.285.10:50:20.09#ibcon#about to read 5, iclass 11, count 0 2006.285.10:50:20.09#ibcon#read 5, iclass 11, count 0 2006.285.10:50:20.09#ibcon#about to read 6, iclass 11, count 0 2006.285.10:50:20.09#ibcon#read 6, iclass 11, count 0 2006.285.10:50:20.09#ibcon#end of sib2, iclass 11, count 0 2006.285.10:50:20.09#ibcon#*after write, iclass 11, count 0 2006.285.10:50:20.09#ibcon#*before return 0, iclass 11, count 0 2006.285.10:50:20.09#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:50:20.09#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.10:50:20.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.10:50:20.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.10:50:20.09$vck44/vblo=4,679.99 2006.285.10:50:20.09#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.10:50:20.09#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.10:50:20.09#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:20.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:50:20.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:50:20.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:50:20.09#ibcon#enter wrdev, iclass 13, count 0 2006.285.10:50:20.09#ibcon#first serial, iclass 13, count 0 2006.285.10:50:20.09#ibcon#enter sib2, iclass 13, count 0 2006.285.10:50:20.09#ibcon#flushed, iclass 13, count 0 2006.285.10:50:20.09#ibcon#about to write, iclass 13, count 0 2006.285.10:50:20.09#ibcon#wrote, iclass 13, count 0 2006.285.10:50:20.09#ibcon#about to read 3, iclass 13, count 0 2006.285.10:50:20.11#ibcon#read 3, iclass 13, count 0 2006.285.10:50:20.11#ibcon#about to read 4, iclass 13, count 0 2006.285.10:50:20.11#ibcon#read 4, iclass 13, count 0 2006.285.10:50:20.11#ibcon#about to read 5, iclass 13, count 0 2006.285.10:50:20.11#ibcon#read 5, iclass 13, count 0 2006.285.10:50:20.11#ibcon#about to read 6, iclass 13, count 0 2006.285.10:50:20.11#ibcon#read 6, iclass 13, count 0 2006.285.10:50:20.11#ibcon#end of sib2, iclass 13, count 0 2006.285.10:50:20.11#ibcon#*mode == 0, iclass 13, count 0 2006.285.10:50:20.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.10:50:20.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:50:20.11#ibcon#*before write, iclass 13, count 0 2006.285.10:50:20.11#ibcon#enter sib2, iclass 13, count 0 2006.285.10:50:20.11#ibcon#flushed, iclass 13, count 0 2006.285.10:50:20.11#ibcon#about to write, iclass 13, count 0 2006.285.10:50:20.11#ibcon#wrote, iclass 13, count 0 2006.285.10:50:20.11#ibcon#about to read 3, iclass 13, count 0 2006.285.10:50:20.15#ibcon#read 3, iclass 13, count 0 2006.285.10:50:20.15#ibcon#about to read 4, iclass 13, count 0 2006.285.10:50:20.15#ibcon#read 4, iclass 13, count 0 2006.285.10:50:20.15#ibcon#about to read 5, iclass 13, count 0 2006.285.10:50:20.15#ibcon#read 5, iclass 13, count 0 2006.285.10:50:20.15#ibcon#about to read 6, iclass 13, count 0 2006.285.10:50:20.15#ibcon#read 6, iclass 13, count 0 2006.285.10:50:20.15#ibcon#end of sib2, iclass 13, count 0 2006.285.10:50:20.15#ibcon#*after write, iclass 13, count 0 2006.285.10:50:20.15#ibcon#*before return 0, iclass 13, count 0 2006.285.10:50:20.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:50:20.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.10:50:20.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.10:50:20.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.10:50:20.15$vck44/vb=4,5 2006.285.10:50:20.15#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.10:50:20.15#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.10:50:20.15#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:20.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:50:20.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:50:20.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:50:20.21#ibcon#enter wrdev, iclass 15, count 2 2006.285.10:50:20.21#ibcon#first serial, iclass 15, count 2 2006.285.10:50:20.21#ibcon#enter sib2, iclass 15, count 2 2006.285.10:50:20.21#ibcon#flushed, iclass 15, count 2 2006.285.10:50:20.21#ibcon#about to write, iclass 15, count 2 2006.285.10:50:20.21#ibcon#wrote, iclass 15, count 2 2006.285.10:50:20.21#ibcon#about to read 3, iclass 15, count 2 2006.285.10:50:20.23#ibcon#read 3, iclass 15, count 2 2006.285.10:50:20.23#ibcon#about to read 4, iclass 15, count 2 2006.285.10:50:20.23#ibcon#read 4, iclass 15, count 2 2006.285.10:50:20.23#ibcon#about to read 5, iclass 15, count 2 2006.285.10:50:20.23#ibcon#read 5, iclass 15, count 2 2006.285.10:50:20.23#ibcon#about to read 6, iclass 15, count 2 2006.285.10:50:20.23#ibcon#read 6, iclass 15, count 2 2006.285.10:50:20.23#ibcon#end of sib2, iclass 15, count 2 2006.285.10:50:20.23#ibcon#*mode == 0, iclass 15, count 2 2006.285.10:50:20.23#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.10:50:20.23#ibcon#[27=AT04-05\r\n] 2006.285.10:50:20.23#ibcon#*before write, iclass 15, count 2 2006.285.10:50:20.23#ibcon#enter sib2, iclass 15, count 2 2006.285.10:50:20.23#ibcon#flushed, iclass 15, count 2 2006.285.10:50:20.23#ibcon#about to write, iclass 15, count 2 2006.285.10:50:20.23#ibcon#wrote, iclass 15, count 2 2006.285.10:50:20.23#ibcon#about to read 3, iclass 15, count 2 2006.285.10:50:20.26#ibcon#read 3, iclass 15, count 2 2006.285.10:50:20.26#ibcon#about to read 4, iclass 15, count 2 2006.285.10:50:20.26#ibcon#read 4, iclass 15, count 2 2006.285.10:50:20.26#ibcon#about to read 5, iclass 15, count 2 2006.285.10:50:20.26#ibcon#read 5, iclass 15, count 2 2006.285.10:50:20.26#ibcon#about to read 6, iclass 15, count 2 2006.285.10:50:20.26#ibcon#read 6, iclass 15, count 2 2006.285.10:50:20.26#ibcon#end of sib2, iclass 15, count 2 2006.285.10:50:20.26#ibcon#*after write, iclass 15, count 2 2006.285.10:50:20.26#ibcon#*before return 0, iclass 15, count 2 2006.285.10:50:20.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:50:20.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.10:50:20.26#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.10:50:20.26#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:20.26#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:50:20.38#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:50:20.38#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:50:20.38#ibcon#enter wrdev, iclass 15, count 0 2006.285.10:50:20.38#ibcon#first serial, iclass 15, count 0 2006.285.10:50:20.38#ibcon#enter sib2, iclass 15, count 0 2006.285.10:50:20.38#ibcon#flushed, iclass 15, count 0 2006.285.10:50:20.38#ibcon#about to write, iclass 15, count 0 2006.285.10:50:20.38#ibcon#wrote, iclass 15, count 0 2006.285.10:50:20.38#ibcon#about to read 3, iclass 15, count 0 2006.285.10:50:20.40#ibcon#read 3, iclass 15, count 0 2006.285.10:50:20.40#ibcon#about to read 4, iclass 15, count 0 2006.285.10:50:20.40#ibcon#read 4, iclass 15, count 0 2006.285.10:50:20.40#ibcon#about to read 5, iclass 15, count 0 2006.285.10:50:20.40#ibcon#read 5, iclass 15, count 0 2006.285.10:50:20.40#ibcon#about to read 6, iclass 15, count 0 2006.285.10:50:20.40#ibcon#read 6, iclass 15, count 0 2006.285.10:50:20.40#ibcon#end of sib2, iclass 15, count 0 2006.285.10:50:20.40#ibcon#*mode == 0, iclass 15, count 0 2006.285.10:50:20.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.10:50:20.40#ibcon#[27=USB\r\n] 2006.285.10:50:20.40#ibcon#*before write, iclass 15, count 0 2006.285.10:50:20.40#ibcon#enter sib2, iclass 15, count 0 2006.285.10:50:20.40#ibcon#flushed, iclass 15, count 0 2006.285.10:50:20.40#ibcon#about to write, iclass 15, count 0 2006.285.10:50:20.40#ibcon#wrote, iclass 15, count 0 2006.285.10:50:20.40#ibcon#about to read 3, iclass 15, count 0 2006.285.10:50:20.43#ibcon#read 3, iclass 15, count 0 2006.285.10:50:20.43#ibcon#about to read 4, iclass 15, count 0 2006.285.10:50:20.43#ibcon#read 4, iclass 15, count 0 2006.285.10:50:20.43#ibcon#about to read 5, iclass 15, count 0 2006.285.10:50:20.43#ibcon#read 5, iclass 15, count 0 2006.285.10:50:20.43#ibcon#about to read 6, iclass 15, count 0 2006.285.10:50:20.43#ibcon#read 6, iclass 15, count 0 2006.285.10:50:20.43#ibcon#end of sib2, iclass 15, count 0 2006.285.10:50:20.43#ibcon#*after write, iclass 15, count 0 2006.285.10:50:20.43#ibcon#*before return 0, iclass 15, count 0 2006.285.10:50:20.43#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:50:20.43#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.10:50:20.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.10:50:20.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.10:50:20.43$vck44/vblo=5,709.99 2006.285.10:50:20.43#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.10:50:20.43#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.10:50:20.43#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:20.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:50:20.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:50:20.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:50:20.43#ibcon#enter wrdev, iclass 17, count 0 2006.285.10:50:20.43#ibcon#first serial, iclass 17, count 0 2006.285.10:50:20.43#ibcon#enter sib2, iclass 17, count 0 2006.285.10:50:20.43#ibcon#flushed, iclass 17, count 0 2006.285.10:50:20.43#ibcon#about to write, iclass 17, count 0 2006.285.10:50:20.43#ibcon#wrote, iclass 17, count 0 2006.285.10:50:20.43#ibcon#about to read 3, iclass 17, count 0 2006.285.10:50:20.45#ibcon#read 3, iclass 17, count 0 2006.285.10:50:20.45#ibcon#about to read 4, iclass 17, count 0 2006.285.10:50:20.45#ibcon#read 4, iclass 17, count 0 2006.285.10:50:20.45#ibcon#about to read 5, iclass 17, count 0 2006.285.10:50:20.45#ibcon#read 5, iclass 17, count 0 2006.285.10:50:20.45#ibcon#about to read 6, iclass 17, count 0 2006.285.10:50:20.45#ibcon#read 6, iclass 17, count 0 2006.285.10:50:20.45#ibcon#end of sib2, iclass 17, count 0 2006.285.10:50:20.45#ibcon#*mode == 0, iclass 17, count 0 2006.285.10:50:20.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.10:50:20.45#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:50:20.45#ibcon#*before write, iclass 17, count 0 2006.285.10:50:20.45#ibcon#enter sib2, iclass 17, count 0 2006.285.10:50:20.45#ibcon#flushed, iclass 17, count 0 2006.285.10:50:20.45#ibcon#about to write, iclass 17, count 0 2006.285.10:50:20.45#ibcon#wrote, iclass 17, count 0 2006.285.10:50:20.45#ibcon#about to read 3, iclass 17, count 0 2006.285.10:50:20.49#ibcon#read 3, iclass 17, count 0 2006.285.10:50:20.49#ibcon#about to read 4, iclass 17, count 0 2006.285.10:50:20.49#ibcon#read 4, iclass 17, count 0 2006.285.10:50:20.49#ibcon#about to read 5, iclass 17, count 0 2006.285.10:50:20.49#ibcon#read 5, iclass 17, count 0 2006.285.10:50:20.49#ibcon#about to read 6, iclass 17, count 0 2006.285.10:50:20.49#ibcon#read 6, iclass 17, count 0 2006.285.10:50:20.49#ibcon#end of sib2, iclass 17, count 0 2006.285.10:50:20.49#ibcon#*after write, iclass 17, count 0 2006.285.10:50:20.49#ibcon#*before return 0, iclass 17, count 0 2006.285.10:50:20.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:50:20.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.10:50:20.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.10:50:20.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.10:50:20.49$vck44/vb=5,4 2006.285.10:50:20.49#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.10:50:20.49#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.10:50:20.49#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:20.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:50:20.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:50:20.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:50:20.55#ibcon#enter wrdev, iclass 19, count 2 2006.285.10:50:20.55#ibcon#first serial, iclass 19, count 2 2006.285.10:50:20.55#ibcon#enter sib2, iclass 19, count 2 2006.285.10:50:20.55#ibcon#flushed, iclass 19, count 2 2006.285.10:50:20.55#ibcon#about to write, iclass 19, count 2 2006.285.10:50:20.55#ibcon#wrote, iclass 19, count 2 2006.285.10:50:20.55#ibcon#about to read 3, iclass 19, count 2 2006.285.10:50:20.57#ibcon#read 3, iclass 19, count 2 2006.285.10:50:20.57#ibcon#about to read 4, iclass 19, count 2 2006.285.10:50:20.57#ibcon#read 4, iclass 19, count 2 2006.285.10:50:20.57#ibcon#about to read 5, iclass 19, count 2 2006.285.10:50:20.57#ibcon#read 5, iclass 19, count 2 2006.285.10:50:20.57#ibcon#about to read 6, iclass 19, count 2 2006.285.10:50:20.57#ibcon#read 6, iclass 19, count 2 2006.285.10:50:20.57#ibcon#end of sib2, iclass 19, count 2 2006.285.10:50:20.57#ibcon#*mode == 0, iclass 19, count 2 2006.285.10:50:20.57#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.10:50:20.57#ibcon#[27=AT05-04\r\n] 2006.285.10:50:20.57#ibcon#*before write, iclass 19, count 2 2006.285.10:50:20.57#ibcon#enter sib2, iclass 19, count 2 2006.285.10:50:20.57#ibcon#flushed, iclass 19, count 2 2006.285.10:50:20.57#ibcon#about to write, iclass 19, count 2 2006.285.10:50:20.57#ibcon#wrote, iclass 19, count 2 2006.285.10:50:20.57#ibcon#about to read 3, iclass 19, count 2 2006.285.10:50:20.60#ibcon#read 3, iclass 19, count 2 2006.285.10:50:20.60#ibcon#about to read 4, iclass 19, count 2 2006.285.10:50:20.60#ibcon#read 4, iclass 19, count 2 2006.285.10:50:20.60#ibcon#about to read 5, iclass 19, count 2 2006.285.10:50:20.60#ibcon#read 5, iclass 19, count 2 2006.285.10:50:20.60#ibcon#about to read 6, iclass 19, count 2 2006.285.10:50:20.60#ibcon#read 6, iclass 19, count 2 2006.285.10:50:20.60#ibcon#end of sib2, iclass 19, count 2 2006.285.10:50:20.60#ibcon#*after write, iclass 19, count 2 2006.285.10:50:20.60#ibcon#*before return 0, iclass 19, count 2 2006.285.10:50:20.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:50:20.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.10:50:20.60#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.10:50:20.60#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:20.60#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:50:20.72#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:50:20.72#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:50:20.72#ibcon#enter wrdev, iclass 19, count 0 2006.285.10:50:20.72#ibcon#first serial, iclass 19, count 0 2006.285.10:50:20.72#ibcon#enter sib2, iclass 19, count 0 2006.285.10:50:20.72#ibcon#flushed, iclass 19, count 0 2006.285.10:50:20.72#ibcon#about to write, iclass 19, count 0 2006.285.10:50:20.72#ibcon#wrote, iclass 19, count 0 2006.285.10:50:20.72#ibcon#about to read 3, iclass 19, count 0 2006.285.10:50:20.74#ibcon#read 3, iclass 19, count 0 2006.285.10:50:20.74#ibcon#about to read 4, iclass 19, count 0 2006.285.10:50:20.74#ibcon#read 4, iclass 19, count 0 2006.285.10:50:20.74#ibcon#about to read 5, iclass 19, count 0 2006.285.10:50:20.74#ibcon#read 5, iclass 19, count 0 2006.285.10:50:20.74#ibcon#about to read 6, iclass 19, count 0 2006.285.10:50:20.74#ibcon#read 6, iclass 19, count 0 2006.285.10:50:20.74#ibcon#end of sib2, iclass 19, count 0 2006.285.10:50:20.74#ibcon#*mode == 0, iclass 19, count 0 2006.285.10:50:20.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.10:50:20.74#ibcon#[27=USB\r\n] 2006.285.10:50:20.74#ibcon#*before write, iclass 19, count 0 2006.285.10:50:20.74#ibcon#enter sib2, iclass 19, count 0 2006.285.10:50:20.74#ibcon#flushed, iclass 19, count 0 2006.285.10:50:20.74#ibcon#about to write, iclass 19, count 0 2006.285.10:50:20.74#ibcon#wrote, iclass 19, count 0 2006.285.10:50:20.74#ibcon#about to read 3, iclass 19, count 0 2006.285.10:50:20.77#ibcon#read 3, iclass 19, count 0 2006.285.10:50:20.77#ibcon#about to read 4, iclass 19, count 0 2006.285.10:50:20.77#ibcon#read 4, iclass 19, count 0 2006.285.10:50:20.77#ibcon#about to read 5, iclass 19, count 0 2006.285.10:50:20.77#ibcon#read 5, iclass 19, count 0 2006.285.10:50:20.77#ibcon#about to read 6, iclass 19, count 0 2006.285.10:50:20.77#ibcon#read 6, iclass 19, count 0 2006.285.10:50:20.77#ibcon#end of sib2, iclass 19, count 0 2006.285.10:50:20.77#ibcon#*after write, iclass 19, count 0 2006.285.10:50:20.77#ibcon#*before return 0, iclass 19, count 0 2006.285.10:50:20.77#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:50:20.77#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.10:50:20.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.10:50:20.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.10:50:20.77$vck44/vblo=6,719.99 2006.285.10:50:20.77#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.10:50:20.77#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.10:50:20.77#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:20.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:50:20.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:50:20.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:50:20.77#ibcon#enter wrdev, iclass 21, count 0 2006.285.10:50:20.77#ibcon#first serial, iclass 21, count 0 2006.285.10:50:20.77#ibcon#enter sib2, iclass 21, count 0 2006.285.10:50:20.77#ibcon#flushed, iclass 21, count 0 2006.285.10:50:20.77#ibcon#about to write, iclass 21, count 0 2006.285.10:50:20.77#ibcon#wrote, iclass 21, count 0 2006.285.10:50:20.77#ibcon#about to read 3, iclass 21, count 0 2006.285.10:50:20.79#ibcon#read 3, iclass 21, count 0 2006.285.10:50:20.79#ibcon#about to read 4, iclass 21, count 0 2006.285.10:50:20.79#ibcon#read 4, iclass 21, count 0 2006.285.10:50:20.79#ibcon#about to read 5, iclass 21, count 0 2006.285.10:50:20.79#ibcon#read 5, iclass 21, count 0 2006.285.10:50:20.79#ibcon#about to read 6, iclass 21, count 0 2006.285.10:50:20.79#ibcon#read 6, iclass 21, count 0 2006.285.10:50:20.79#ibcon#end of sib2, iclass 21, count 0 2006.285.10:50:20.79#ibcon#*mode == 0, iclass 21, count 0 2006.285.10:50:20.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.10:50:20.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:50:20.79#ibcon#*before write, iclass 21, count 0 2006.285.10:50:20.79#ibcon#enter sib2, iclass 21, count 0 2006.285.10:50:20.79#ibcon#flushed, iclass 21, count 0 2006.285.10:50:20.79#ibcon#about to write, iclass 21, count 0 2006.285.10:50:20.79#ibcon#wrote, iclass 21, count 0 2006.285.10:50:20.79#ibcon#about to read 3, iclass 21, count 0 2006.285.10:50:20.83#ibcon#read 3, iclass 21, count 0 2006.285.10:50:20.83#ibcon#about to read 4, iclass 21, count 0 2006.285.10:50:20.83#ibcon#read 4, iclass 21, count 0 2006.285.10:50:20.83#ibcon#about to read 5, iclass 21, count 0 2006.285.10:50:20.83#ibcon#read 5, iclass 21, count 0 2006.285.10:50:20.83#ibcon#about to read 6, iclass 21, count 0 2006.285.10:50:20.83#ibcon#read 6, iclass 21, count 0 2006.285.10:50:20.83#ibcon#end of sib2, iclass 21, count 0 2006.285.10:50:20.83#ibcon#*after write, iclass 21, count 0 2006.285.10:50:20.83#ibcon#*before return 0, iclass 21, count 0 2006.285.10:50:20.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:50:20.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.10:50:20.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.10:50:20.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.10:50:20.83$vck44/vb=6,3 2006.285.10:50:20.83#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.10:50:20.83#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.10:50:20.83#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:20.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:50:20.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:50:20.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:50:20.89#ibcon#enter wrdev, iclass 23, count 2 2006.285.10:50:20.89#ibcon#first serial, iclass 23, count 2 2006.285.10:50:20.89#ibcon#enter sib2, iclass 23, count 2 2006.285.10:50:20.89#ibcon#flushed, iclass 23, count 2 2006.285.10:50:20.89#ibcon#about to write, iclass 23, count 2 2006.285.10:50:20.89#ibcon#wrote, iclass 23, count 2 2006.285.10:50:20.89#ibcon#about to read 3, iclass 23, count 2 2006.285.10:50:20.91#ibcon#read 3, iclass 23, count 2 2006.285.10:50:20.91#ibcon#about to read 4, iclass 23, count 2 2006.285.10:50:20.91#ibcon#read 4, iclass 23, count 2 2006.285.10:50:20.91#ibcon#about to read 5, iclass 23, count 2 2006.285.10:50:20.91#ibcon#read 5, iclass 23, count 2 2006.285.10:50:20.91#ibcon#about to read 6, iclass 23, count 2 2006.285.10:50:20.91#ibcon#read 6, iclass 23, count 2 2006.285.10:50:20.91#ibcon#end of sib2, iclass 23, count 2 2006.285.10:50:20.91#ibcon#*mode == 0, iclass 23, count 2 2006.285.10:50:20.91#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.10:50:20.91#ibcon#[27=AT06-03\r\n] 2006.285.10:50:20.91#ibcon#*before write, iclass 23, count 2 2006.285.10:50:20.91#ibcon#enter sib2, iclass 23, count 2 2006.285.10:50:20.91#ibcon#flushed, iclass 23, count 2 2006.285.10:50:20.91#ibcon#about to write, iclass 23, count 2 2006.285.10:50:20.91#ibcon#wrote, iclass 23, count 2 2006.285.10:50:20.91#ibcon#about to read 3, iclass 23, count 2 2006.285.10:50:20.94#ibcon#read 3, iclass 23, count 2 2006.285.10:50:20.94#ibcon#about to read 4, iclass 23, count 2 2006.285.10:50:20.94#ibcon#read 4, iclass 23, count 2 2006.285.10:50:20.94#ibcon#about to read 5, iclass 23, count 2 2006.285.10:50:20.94#ibcon#read 5, iclass 23, count 2 2006.285.10:50:20.94#ibcon#about to read 6, iclass 23, count 2 2006.285.10:50:20.94#ibcon#read 6, iclass 23, count 2 2006.285.10:50:20.94#ibcon#end of sib2, iclass 23, count 2 2006.285.10:50:20.94#ibcon#*after write, iclass 23, count 2 2006.285.10:50:20.94#ibcon#*before return 0, iclass 23, count 2 2006.285.10:50:20.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:50:20.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.10:50:20.94#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.10:50:20.94#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:20.94#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:50:21.06#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:50:21.06#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:50:21.06#ibcon#enter wrdev, iclass 23, count 0 2006.285.10:50:21.06#ibcon#first serial, iclass 23, count 0 2006.285.10:50:21.06#ibcon#enter sib2, iclass 23, count 0 2006.285.10:50:21.06#ibcon#flushed, iclass 23, count 0 2006.285.10:50:21.06#ibcon#about to write, iclass 23, count 0 2006.285.10:50:21.06#ibcon#wrote, iclass 23, count 0 2006.285.10:50:21.06#ibcon#about to read 3, iclass 23, count 0 2006.285.10:50:21.08#ibcon#read 3, iclass 23, count 0 2006.285.10:50:21.08#ibcon#about to read 4, iclass 23, count 0 2006.285.10:50:21.08#ibcon#read 4, iclass 23, count 0 2006.285.10:50:21.08#ibcon#about to read 5, iclass 23, count 0 2006.285.10:50:21.08#ibcon#read 5, iclass 23, count 0 2006.285.10:50:21.08#ibcon#about to read 6, iclass 23, count 0 2006.285.10:50:21.08#ibcon#read 6, iclass 23, count 0 2006.285.10:50:21.08#ibcon#end of sib2, iclass 23, count 0 2006.285.10:50:21.08#ibcon#*mode == 0, iclass 23, count 0 2006.285.10:50:21.08#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.10:50:21.08#ibcon#[27=USB\r\n] 2006.285.10:50:21.08#ibcon#*before write, iclass 23, count 0 2006.285.10:50:21.08#ibcon#enter sib2, iclass 23, count 0 2006.285.10:50:21.08#ibcon#flushed, iclass 23, count 0 2006.285.10:50:21.08#ibcon#about to write, iclass 23, count 0 2006.285.10:50:21.08#ibcon#wrote, iclass 23, count 0 2006.285.10:50:21.08#ibcon#about to read 3, iclass 23, count 0 2006.285.10:50:21.11#ibcon#read 3, iclass 23, count 0 2006.285.10:50:21.11#ibcon#about to read 4, iclass 23, count 0 2006.285.10:50:21.11#ibcon#read 4, iclass 23, count 0 2006.285.10:50:21.11#ibcon#about to read 5, iclass 23, count 0 2006.285.10:50:21.11#ibcon#read 5, iclass 23, count 0 2006.285.10:50:21.11#ibcon#about to read 6, iclass 23, count 0 2006.285.10:50:21.11#ibcon#read 6, iclass 23, count 0 2006.285.10:50:21.11#ibcon#end of sib2, iclass 23, count 0 2006.285.10:50:21.11#ibcon#*after write, iclass 23, count 0 2006.285.10:50:21.11#ibcon#*before return 0, iclass 23, count 0 2006.285.10:50:21.11#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:50:21.11#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.10:50:21.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.10:50:21.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.10:50:21.11$vck44/vblo=7,734.99 2006.285.10:50:21.11#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.10:50:21.11#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.10:50:21.11#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:21.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:50:21.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:50:21.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:50:21.11#ibcon#enter wrdev, iclass 25, count 0 2006.285.10:50:21.11#ibcon#first serial, iclass 25, count 0 2006.285.10:50:21.11#ibcon#enter sib2, iclass 25, count 0 2006.285.10:50:21.11#ibcon#flushed, iclass 25, count 0 2006.285.10:50:21.11#ibcon#about to write, iclass 25, count 0 2006.285.10:50:21.11#ibcon#wrote, iclass 25, count 0 2006.285.10:50:21.11#ibcon#about to read 3, iclass 25, count 0 2006.285.10:50:21.13#ibcon#read 3, iclass 25, count 0 2006.285.10:50:21.13#ibcon#about to read 4, iclass 25, count 0 2006.285.10:50:21.13#ibcon#read 4, iclass 25, count 0 2006.285.10:50:21.13#ibcon#about to read 5, iclass 25, count 0 2006.285.10:50:21.13#ibcon#read 5, iclass 25, count 0 2006.285.10:50:21.13#ibcon#about to read 6, iclass 25, count 0 2006.285.10:50:21.13#ibcon#read 6, iclass 25, count 0 2006.285.10:50:21.13#ibcon#end of sib2, iclass 25, count 0 2006.285.10:50:21.13#ibcon#*mode == 0, iclass 25, count 0 2006.285.10:50:21.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.10:50:21.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:50:21.13#ibcon#*before write, iclass 25, count 0 2006.285.10:50:21.13#ibcon#enter sib2, iclass 25, count 0 2006.285.10:50:21.13#ibcon#flushed, iclass 25, count 0 2006.285.10:50:21.13#ibcon#about to write, iclass 25, count 0 2006.285.10:50:21.13#ibcon#wrote, iclass 25, count 0 2006.285.10:50:21.13#ibcon#about to read 3, iclass 25, count 0 2006.285.10:50:21.17#ibcon#read 3, iclass 25, count 0 2006.285.10:50:21.17#ibcon#about to read 4, iclass 25, count 0 2006.285.10:50:21.17#ibcon#read 4, iclass 25, count 0 2006.285.10:50:21.17#ibcon#about to read 5, iclass 25, count 0 2006.285.10:50:21.17#ibcon#read 5, iclass 25, count 0 2006.285.10:50:21.17#ibcon#about to read 6, iclass 25, count 0 2006.285.10:50:21.17#ibcon#read 6, iclass 25, count 0 2006.285.10:50:21.17#ibcon#end of sib2, iclass 25, count 0 2006.285.10:50:21.17#ibcon#*after write, iclass 25, count 0 2006.285.10:50:21.17#ibcon#*before return 0, iclass 25, count 0 2006.285.10:50:21.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:50:21.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.10:50:21.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.10:50:21.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.10:50:21.17$vck44/vb=7,4 2006.285.10:50:21.17#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.10:50:21.17#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.10:50:21.17#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:21.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:50:21.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:50:21.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:50:21.23#ibcon#enter wrdev, iclass 27, count 2 2006.285.10:50:21.23#ibcon#first serial, iclass 27, count 2 2006.285.10:50:21.23#ibcon#enter sib2, iclass 27, count 2 2006.285.10:50:21.23#ibcon#flushed, iclass 27, count 2 2006.285.10:50:21.23#ibcon#about to write, iclass 27, count 2 2006.285.10:50:21.23#ibcon#wrote, iclass 27, count 2 2006.285.10:50:21.23#ibcon#about to read 3, iclass 27, count 2 2006.285.10:50:21.25#ibcon#read 3, iclass 27, count 2 2006.285.10:50:21.25#ibcon#about to read 4, iclass 27, count 2 2006.285.10:50:21.25#ibcon#read 4, iclass 27, count 2 2006.285.10:50:21.25#ibcon#about to read 5, iclass 27, count 2 2006.285.10:50:21.25#ibcon#read 5, iclass 27, count 2 2006.285.10:50:21.25#ibcon#about to read 6, iclass 27, count 2 2006.285.10:50:21.25#ibcon#read 6, iclass 27, count 2 2006.285.10:50:21.25#ibcon#end of sib2, iclass 27, count 2 2006.285.10:50:21.25#ibcon#*mode == 0, iclass 27, count 2 2006.285.10:50:21.25#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.10:50:21.25#ibcon#[27=AT07-04\r\n] 2006.285.10:50:21.25#ibcon#*before write, iclass 27, count 2 2006.285.10:50:21.25#ibcon#enter sib2, iclass 27, count 2 2006.285.10:50:21.25#ibcon#flushed, iclass 27, count 2 2006.285.10:50:21.25#ibcon#about to write, iclass 27, count 2 2006.285.10:50:21.25#ibcon#wrote, iclass 27, count 2 2006.285.10:50:21.25#ibcon#about to read 3, iclass 27, count 2 2006.285.10:50:21.28#ibcon#read 3, iclass 27, count 2 2006.285.10:50:21.28#ibcon#about to read 4, iclass 27, count 2 2006.285.10:50:21.28#ibcon#read 4, iclass 27, count 2 2006.285.10:50:21.28#ibcon#about to read 5, iclass 27, count 2 2006.285.10:50:21.28#ibcon#read 5, iclass 27, count 2 2006.285.10:50:21.28#ibcon#about to read 6, iclass 27, count 2 2006.285.10:50:21.28#ibcon#read 6, iclass 27, count 2 2006.285.10:50:21.28#ibcon#end of sib2, iclass 27, count 2 2006.285.10:50:21.28#ibcon#*after write, iclass 27, count 2 2006.285.10:50:21.28#ibcon#*before return 0, iclass 27, count 2 2006.285.10:50:21.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:50:21.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.10:50:21.28#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.10:50:21.28#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:21.28#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:50:21.40#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:50:21.40#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:50:21.40#ibcon#enter wrdev, iclass 27, count 0 2006.285.10:50:21.40#ibcon#first serial, iclass 27, count 0 2006.285.10:50:21.40#ibcon#enter sib2, iclass 27, count 0 2006.285.10:50:21.40#ibcon#flushed, iclass 27, count 0 2006.285.10:50:21.40#ibcon#about to write, iclass 27, count 0 2006.285.10:50:21.40#ibcon#wrote, iclass 27, count 0 2006.285.10:50:21.40#ibcon#about to read 3, iclass 27, count 0 2006.285.10:50:21.42#ibcon#read 3, iclass 27, count 0 2006.285.10:50:21.42#ibcon#about to read 4, iclass 27, count 0 2006.285.10:50:21.42#ibcon#read 4, iclass 27, count 0 2006.285.10:50:21.42#ibcon#about to read 5, iclass 27, count 0 2006.285.10:50:21.42#ibcon#read 5, iclass 27, count 0 2006.285.10:50:21.42#ibcon#about to read 6, iclass 27, count 0 2006.285.10:50:21.42#ibcon#read 6, iclass 27, count 0 2006.285.10:50:21.42#ibcon#end of sib2, iclass 27, count 0 2006.285.10:50:21.42#ibcon#*mode == 0, iclass 27, count 0 2006.285.10:50:21.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.10:50:21.42#ibcon#[27=USB\r\n] 2006.285.10:50:21.42#ibcon#*before write, iclass 27, count 0 2006.285.10:50:21.42#ibcon#enter sib2, iclass 27, count 0 2006.285.10:50:21.42#ibcon#flushed, iclass 27, count 0 2006.285.10:50:21.42#ibcon#about to write, iclass 27, count 0 2006.285.10:50:21.42#ibcon#wrote, iclass 27, count 0 2006.285.10:50:21.42#ibcon#about to read 3, iclass 27, count 0 2006.285.10:50:21.45#ibcon#read 3, iclass 27, count 0 2006.285.10:50:21.45#ibcon#about to read 4, iclass 27, count 0 2006.285.10:50:21.45#ibcon#read 4, iclass 27, count 0 2006.285.10:50:21.45#ibcon#about to read 5, iclass 27, count 0 2006.285.10:50:21.45#ibcon#read 5, iclass 27, count 0 2006.285.10:50:21.45#ibcon#about to read 6, iclass 27, count 0 2006.285.10:50:21.45#ibcon#read 6, iclass 27, count 0 2006.285.10:50:21.45#ibcon#end of sib2, iclass 27, count 0 2006.285.10:50:21.45#ibcon#*after write, iclass 27, count 0 2006.285.10:50:21.45#ibcon#*before return 0, iclass 27, count 0 2006.285.10:50:21.45#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:50:21.45#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.10:50:21.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.10:50:21.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.10:50:21.45$vck44/vblo=8,744.99 2006.285.10:50:21.45#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.10:50:21.45#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.10:50:21.45#ibcon#ireg 17 cls_cnt 0 2006.285.10:50:21.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:50:21.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:50:21.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:50:21.45#ibcon#enter wrdev, iclass 29, count 0 2006.285.10:50:21.45#ibcon#first serial, iclass 29, count 0 2006.285.10:50:21.45#ibcon#enter sib2, iclass 29, count 0 2006.285.10:50:21.45#ibcon#flushed, iclass 29, count 0 2006.285.10:50:21.45#ibcon#about to write, iclass 29, count 0 2006.285.10:50:21.45#ibcon#wrote, iclass 29, count 0 2006.285.10:50:21.45#ibcon#about to read 3, iclass 29, count 0 2006.285.10:50:21.47#ibcon#read 3, iclass 29, count 0 2006.285.10:50:21.47#ibcon#about to read 4, iclass 29, count 0 2006.285.10:50:21.47#ibcon#read 4, iclass 29, count 0 2006.285.10:50:21.47#ibcon#about to read 5, iclass 29, count 0 2006.285.10:50:21.47#ibcon#read 5, iclass 29, count 0 2006.285.10:50:21.47#ibcon#about to read 6, iclass 29, count 0 2006.285.10:50:21.47#ibcon#read 6, iclass 29, count 0 2006.285.10:50:21.47#ibcon#end of sib2, iclass 29, count 0 2006.285.10:50:21.47#ibcon#*mode == 0, iclass 29, count 0 2006.285.10:50:21.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.10:50:21.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:50:21.47#ibcon#*before write, iclass 29, count 0 2006.285.10:50:21.47#ibcon#enter sib2, iclass 29, count 0 2006.285.10:50:21.47#ibcon#flushed, iclass 29, count 0 2006.285.10:50:21.47#ibcon#about to write, iclass 29, count 0 2006.285.10:50:21.47#ibcon#wrote, iclass 29, count 0 2006.285.10:50:21.47#ibcon#about to read 3, iclass 29, count 0 2006.285.10:50:21.51#ibcon#read 3, iclass 29, count 0 2006.285.10:50:21.51#ibcon#about to read 4, iclass 29, count 0 2006.285.10:50:21.51#ibcon#read 4, iclass 29, count 0 2006.285.10:50:21.51#ibcon#about to read 5, iclass 29, count 0 2006.285.10:50:21.51#ibcon#read 5, iclass 29, count 0 2006.285.10:50:21.51#ibcon#about to read 6, iclass 29, count 0 2006.285.10:50:21.51#ibcon#read 6, iclass 29, count 0 2006.285.10:50:21.51#ibcon#end of sib2, iclass 29, count 0 2006.285.10:50:21.51#ibcon#*after write, iclass 29, count 0 2006.285.10:50:21.51#ibcon#*before return 0, iclass 29, count 0 2006.285.10:50:21.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:50:21.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.10:50:21.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.10:50:21.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.10:50:21.51$vck44/vb=8,4 2006.285.10:50:21.51#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.10:50:21.51#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.10:50:21.51#ibcon#ireg 11 cls_cnt 2 2006.285.10:50:21.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:50:21.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:50:21.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:50:21.57#ibcon#enter wrdev, iclass 31, count 2 2006.285.10:50:21.57#ibcon#first serial, iclass 31, count 2 2006.285.10:50:21.57#ibcon#enter sib2, iclass 31, count 2 2006.285.10:50:21.57#ibcon#flushed, iclass 31, count 2 2006.285.10:50:21.57#ibcon#about to write, iclass 31, count 2 2006.285.10:50:21.57#ibcon#wrote, iclass 31, count 2 2006.285.10:50:21.57#ibcon#about to read 3, iclass 31, count 2 2006.285.10:50:21.59#ibcon#read 3, iclass 31, count 2 2006.285.10:50:21.59#ibcon#about to read 4, iclass 31, count 2 2006.285.10:50:21.59#ibcon#read 4, iclass 31, count 2 2006.285.10:50:21.59#ibcon#about to read 5, iclass 31, count 2 2006.285.10:50:21.59#ibcon#read 5, iclass 31, count 2 2006.285.10:50:21.59#ibcon#about to read 6, iclass 31, count 2 2006.285.10:50:21.59#ibcon#read 6, iclass 31, count 2 2006.285.10:50:21.59#ibcon#end of sib2, iclass 31, count 2 2006.285.10:50:21.59#ibcon#*mode == 0, iclass 31, count 2 2006.285.10:50:21.59#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.10:50:21.59#ibcon#[27=AT08-04\r\n] 2006.285.10:50:21.59#ibcon#*before write, iclass 31, count 2 2006.285.10:50:21.59#ibcon#enter sib2, iclass 31, count 2 2006.285.10:50:21.59#ibcon#flushed, iclass 31, count 2 2006.285.10:50:21.59#ibcon#about to write, iclass 31, count 2 2006.285.10:50:21.59#ibcon#wrote, iclass 31, count 2 2006.285.10:50:21.59#ibcon#about to read 3, iclass 31, count 2 2006.285.10:50:21.62#ibcon#read 3, iclass 31, count 2 2006.285.10:50:21.62#ibcon#about to read 4, iclass 31, count 2 2006.285.10:50:21.62#ibcon#read 4, iclass 31, count 2 2006.285.10:50:21.62#ibcon#about to read 5, iclass 31, count 2 2006.285.10:50:21.62#ibcon#read 5, iclass 31, count 2 2006.285.10:50:21.62#ibcon#about to read 6, iclass 31, count 2 2006.285.10:50:21.62#ibcon#read 6, iclass 31, count 2 2006.285.10:50:21.62#ibcon#end of sib2, iclass 31, count 2 2006.285.10:50:21.62#ibcon#*after write, iclass 31, count 2 2006.285.10:50:21.62#ibcon#*before return 0, iclass 31, count 2 2006.285.10:50:21.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:50:21.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.10:50:21.62#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.10:50:21.62#ibcon#ireg 7 cls_cnt 0 2006.285.10:50:21.62#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:50:21.74#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:50:21.74#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:50:21.74#ibcon#enter wrdev, iclass 31, count 0 2006.285.10:50:21.74#ibcon#first serial, iclass 31, count 0 2006.285.10:50:21.74#ibcon#enter sib2, iclass 31, count 0 2006.285.10:50:21.74#ibcon#flushed, iclass 31, count 0 2006.285.10:50:21.74#ibcon#about to write, iclass 31, count 0 2006.285.10:50:21.74#ibcon#wrote, iclass 31, count 0 2006.285.10:50:21.74#ibcon#about to read 3, iclass 31, count 0 2006.285.10:50:21.76#ibcon#read 3, iclass 31, count 0 2006.285.10:50:21.76#ibcon#about to read 4, iclass 31, count 0 2006.285.10:50:21.76#ibcon#read 4, iclass 31, count 0 2006.285.10:50:21.76#ibcon#about to read 5, iclass 31, count 0 2006.285.10:50:21.76#ibcon#read 5, iclass 31, count 0 2006.285.10:50:21.76#ibcon#about to read 6, iclass 31, count 0 2006.285.10:50:21.76#ibcon#read 6, iclass 31, count 0 2006.285.10:50:21.76#ibcon#end of sib2, iclass 31, count 0 2006.285.10:50:21.76#ibcon#*mode == 0, iclass 31, count 0 2006.285.10:50:21.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.10:50:21.76#ibcon#[27=USB\r\n] 2006.285.10:50:21.76#ibcon#*before write, iclass 31, count 0 2006.285.10:50:21.76#ibcon#enter sib2, iclass 31, count 0 2006.285.10:50:21.76#ibcon#flushed, iclass 31, count 0 2006.285.10:50:21.76#ibcon#about to write, iclass 31, count 0 2006.285.10:50:21.76#ibcon#wrote, iclass 31, count 0 2006.285.10:50:21.76#ibcon#about to read 3, iclass 31, count 0 2006.285.10:50:21.79#ibcon#read 3, iclass 31, count 0 2006.285.10:50:21.79#ibcon#about to read 4, iclass 31, count 0 2006.285.10:50:21.79#ibcon#read 4, iclass 31, count 0 2006.285.10:50:21.79#ibcon#about to read 5, iclass 31, count 0 2006.285.10:50:21.79#ibcon#read 5, iclass 31, count 0 2006.285.10:50:21.79#ibcon#about to read 6, iclass 31, count 0 2006.285.10:50:21.79#ibcon#read 6, iclass 31, count 0 2006.285.10:50:21.79#ibcon#end of sib2, iclass 31, count 0 2006.285.10:50:21.79#ibcon#*after write, iclass 31, count 0 2006.285.10:50:21.79#ibcon#*before return 0, iclass 31, count 0 2006.285.10:50:21.79#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:50:21.79#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.10:50:21.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.10:50:21.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.10:50:21.79$vck44/vabw=wide 2006.285.10:50:21.79#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.10:50:21.79#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.10:50:21.79#ibcon#ireg 8 cls_cnt 0 2006.285.10:50:21.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:50:21.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:50:21.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:50:21.79#ibcon#enter wrdev, iclass 33, count 0 2006.285.10:50:21.79#ibcon#first serial, iclass 33, count 0 2006.285.10:50:21.79#ibcon#enter sib2, iclass 33, count 0 2006.285.10:50:21.79#ibcon#flushed, iclass 33, count 0 2006.285.10:50:21.79#ibcon#about to write, iclass 33, count 0 2006.285.10:50:21.79#ibcon#wrote, iclass 33, count 0 2006.285.10:50:21.79#ibcon#about to read 3, iclass 33, count 0 2006.285.10:50:21.81#ibcon#read 3, iclass 33, count 0 2006.285.10:50:21.81#ibcon#about to read 4, iclass 33, count 0 2006.285.10:50:21.81#ibcon#read 4, iclass 33, count 0 2006.285.10:50:21.81#ibcon#about to read 5, iclass 33, count 0 2006.285.10:50:21.81#ibcon#read 5, iclass 33, count 0 2006.285.10:50:21.81#ibcon#about to read 6, iclass 33, count 0 2006.285.10:50:21.81#ibcon#read 6, iclass 33, count 0 2006.285.10:50:21.81#ibcon#end of sib2, iclass 33, count 0 2006.285.10:50:21.81#ibcon#*mode == 0, iclass 33, count 0 2006.285.10:50:21.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.10:50:21.81#ibcon#[25=BW32\r\n] 2006.285.10:50:21.81#ibcon#*before write, iclass 33, count 0 2006.285.10:50:21.81#ibcon#enter sib2, iclass 33, count 0 2006.285.10:50:21.81#ibcon#flushed, iclass 33, count 0 2006.285.10:50:21.81#ibcon#about to write, iclass 33, count 0 2006.285.10:50:21.81#ibcon#wrote, iclass 33, count 0 2006.285.10:50:21.81#ibcon#about to read 3, iclass 33, count 0 2006.285.10:50:21.84#ibcon#read 3, iclass 33, count 0 2006.285.10:50:21.84#ibcon#about to read 4, iclass 33, count 0 2006.285.10:50:21.84#ibcon#read 4, iclass 33, count 0 2006.285.10:50:21.84#ibcon#about to read 5, iclass 33, count 0 2006.285.10:50:21.84#ibcon#read 5, iclass 33, count 0 2006.285.10:50:21.84#ibcon#about to read 6, iclass 33, count 0 2006.285.10:50:21.84#ibcon#read 6, iclass 33, count 0 2006.285.10:50:21.84#ibcon#end of sib2, iclass 33, count 0 2006.285.10:50:21.84#ibcon#*after write, iclass 33, count 0 2006.285.10:50:21.84#ibcon#*before return 0, iclass 33, count 0 2006.285.10:50:21.84#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:50:21.84#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.10:50:21.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.10:50:21.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.10:50:21.84$vck44/vbbw=wide 2006.285.10:50:21.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.10:50:21.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.10:50:21.84#ibcon#ireg 8 cls_cnt 0 2006.285.10:50:21.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:50:21.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:50:21.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:50:21.91#ibcon#enter wrdev, iclass 35, count 0 2006.285.10:50:21.91#ibcon#first serial, iclass 35, count 0 2006.285.10:50:21.91#ibcon#enter sib2, iclass 35, count 0 2006.285.10:50:21.91#ibcon#flushed, iclass 35, count 0 2006.285.10:50:21.91#ibcon#about to write, iclass 35, count 0 2006.285.10:50:21.91#ibcon#wrote, iclass 35, count 0 2006.285.10:50:21.91#ibcon#about to read 3, iclass 35, count 0 2006.285.10:50:21.93#ibcon#read 3, iclass 35, count 0 2006.285.10:50:21.93#ibcon#about to read 4, iclass 35, count 0 2006.285.10:50:21.93#ibcon#read 4, iclass 35, count 0 2006.285.10:50:21.93#ibcon#about to read 5, iclass 35, count 0 2006.285.10:50:21.93#ibcon#read 5, iclass 35, count 0 2006.285.10:50:21.93#ibcon#about to read 6, iclass 35, count 0 2006.285.10:50:21.93#ibcon#read 6, iclass 35, count 0 2006.285.10:50:21.93#ibcon#end of sib2, iclass 35, count 0 2006.285.10:50:21.93#ibcon#*mode == 0, iclass 35, count 0 2006.285.10:50:21.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.10:50:21.93#ibcon#[27=BW32\r\n] 2006.285.10:50:21.93#ibcon#*before write, iclass 35, count 0 2006.285.10:50:21.93#ibcon#enter sib2, iclass 35, count 0 2006.285.10:50:21.93#ibcon#flushed, iclass 35, count 0 2006.285.10:50:21.93#ibcon#about to write, iclass 35, count 0 2006.285.10:50:21.93#ibcon#wrote, iclass 35, count 0 2006.285.10:50:21.93#ibcon#about to read 3, iclass 35, count 0 2006.285.10:50:21.96#ibcon#read 3, iclass 35, count 0 2006.285.10:50:21.96#ibcon#about to read 4, iclass 35, count 0 2006.285.10:50:21.96#ibcon#read 4, iclass 35, count 0 2006.285.10:50:21.96#ibcon#about to read 5, iclass 35, count 0 2006.285.10:50:21.96#ibcon#read 5, iclass 35, count 0 2006.285.10:50:21.96#ibcon#about to read 6, iclass 35, count 0 2006.285.10:50:21.96#ibcon#read 6, iclass 35, count 0 2006.285.10:50:21.96#ibcon#end of sib2, iclass 35, count 0 2006.285.10:50:21.96#ibcon#*after write, iclass 35, count 0 2006.285.10:50:21.96#ibcon#*before return 0, iclass 35, count 0 2006.285.10:50:21.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:50:21.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.10:50:21.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.10:50:21.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.10:50:21.96$setupk4/ifdk4 2006.285.10:50:21.96$ifdk4/lo= 2006.285.10:50:21.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:50:21.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:50:21.96$ifdk4/patch= 2006.285.10:50:21.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:50:21.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:50:21.96$setupk4/!*+20s 2006.285.10:50:29.37#abcon#<5=/05 1.3 2.0 19.63 921014.9\r\n> 2006.285.10:50:29.39#abcon#{5=INTERFACE CLEAR} 2006.285.10:50:29.45#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:50:30.14#trakl#Source acquired 2006.285.10:50:32.14#flagr#flagr/antenna,acquired 2006.285.10:50:36.47$setupk4/"tpicd 2006.285.10:50:36.47$setupk4/echo=off 2006.285.10:50:36.47$setupk4/xlog=off 2006.285.10:50:36.47:!2006.285.10:54:52 2006.285.10:54:52.00:preob 2006.285.10:54:52.13/onsource/TRACKING 2006.285.10:54:52.13:!2006.285.10:55:02 2006.285.10:55:02.00:"tape 2006.285.10:55:02.00:"st=record 2006.285.10:55:02.00:data_valid=on 2006.285.10:55:02.00:midob 2006.285.10:55:02.13/onsource/TRACKING 2006.285.10:55:02.13/wx/19.57,1014.9,92 2006.285.10:55:02.30/cable/+6.4872E-03 2006.285.10:55:03.39/va/01,07,usb,yes,32,35 2006.285.10:55:03.39/va/02,06,usb,yes,32,33 2006.285.10:55:03.39/va/03,07,usb,yes,31,33 2006.285.10:55:03.39/va/04,06,usb,yes,33,34 2006.285.10:55:03.39/va/05,03,usb,yes,32,33 2006.285.10:55:03.39/va/06,04,usb,yes,29,29 2006.285.10:55:03.39/va/07,04,usb,yes,30,30 2006.285.10:55:03.39/va/08,03,usb,yes,31,37 2006.285.10:55:03.62/valo/01,524.99,yes,locked 2006.285.10:55:03.62/valo/02,534.99,yes,locked 2006.285.10:55:03.62/valo/03,564.99,yes,locked 2006.285.10:55:03.62/valo/04,624.99,yes,locked 2006.285.10:55:03.62/valo/05,734.99,yes,locked 2006.285.10:55:03.62/valo/06,814.99,yes,locked 2006.285.10:55:03.62/valo/07,864.99,yes,locked 2006.285.10:55:03.62/valo/08,884.99,yes,locked 2006.285.10:55:04.71/vb/01,04,usb,yes,31,28 2006.285.10:55:04.71/vb/02,05,usb,yes,29,29 2006.285.10:55:04.71/vb/03,04,usb,yes,29,33 2006.285.10:55:04.71/vb/04,05,usb,yes,30,29 2006.285.10:55:04.71/vb/05,04,usb,yes,26,29 2006.285.10:55:04.71/vb/06,03,usb,yes,38,33 2006.285.10:55:04.71/vb/07,04,usb,yes,30,30 2006.285.10:55:04.71/vb/08,04,usb,yes,28,31 2006.285.10:55:04.94/vblo/01,629.99,yes,locked 2006.285.10:55:04.94/vblo/02,634.99,yes,locked 2006.285.10:55:04.94/vblo/03,649.99,yes,locked 2006.285.10:55:04.94/vblo/04,679.99,yes,locked 2006.285.10:55:04.94/vblo/05,709.99,yes,locked 2006.285.10:55:04.94/vblo/06,719.99,yes,locked 2006.285.10:55:04.94/vblo/07,734.99,yes,locked 2006.285.10:55:04.94/vblo/08,744.99,yes,locked 2006.285.10:55:05.09/vabw/8 2006.285.10:55:05.24/vbbw/8 2006.285.10:55:05.33/xfe/off,on,12.2 2006.285.10:55:05.70/ifatt/23,28,28,28 2006.285.10:55:06.07/fmout-gps/S +2.67E-07 2006.285.10:55:06.09:!2006.285.10:56:42 2006.285.10:56:42.00:data_valid=off 2006.285.10:56:42.00:"et 2006.285.10:56:42.00:!+3s 2006.285.10:56:45.01:"tape 2006.285.10:56:45.01:postob 2006.285.10:56:45.12/cable/+6.4878E-03 2006.285.10:56:45.12/wx/19.54,1014.9,92 2006.285.10:56:46.08/fmout-gps/S +2.68E-07 2006.285.10:56:46.08:scan_name=285-1101,jd0610,40 2006.285.10:56:46.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.285.10:56:47.14#flagr#flagr/antenna,new-source 2006.285.10:56:47.14:checkk5 2006.285.10:56:47.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.10:56:47.98/chk_autoobs//k5ts2/ autoobs is running! 2006.285.10:56:48.41/chk_autoobs//k5ts3/ autoobs is running! 2006.285.10:56:48.82/chk_autoobs//k5ts4/ autoobs is running! 2006.285.10:56:49.20/chk_obsdata//k5ts1/T2851055??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.10:56:49.60/chk_obsdata//k5ts2/T2851055??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.10:56:50.04/chk_obsdata//k5ts3/T2851055??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.10:56:50.44/chk_obsdata//k5ts4/T2851055??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.10:56:51.37/k5log//k5ts1_log_newline 2006.285.10:56:52.26/k5log//k5ts2_log_newline 2006.285.10:56:53.09/k5log//k5ts3_log_newline 2006.285.10:56:53.82/k5log//k5ts4_log_newline 2006.285.10:56:53.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.10:56:53.84:setupk4=1 2006.285.10:56:53.84$setupk4/echo=on 2006.285.10:56:53.84$setupk4/pcalon 2006.285.10:56:53.84$pcalon/"no phase cal control is implemented here 2006.285.10:56:53.84$setupk4/"tpicd=stop 2006.285.10:56:53.84$setupk4/"rec=synch_on 2006.285.10:56:53.84$setupk4/"rec_mode=128 2006.285.10:56:53.84$setupk4/!* 2006.285.10:56:53.84$setupk4/recpk4 2006.285.10:56:53.84$recpk4/recpatch= 2006.285.10:56:53.85$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.10:56:53.85$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.10:56:53.85$setupk4/vck44 2006.285.10:56:53.85$vck44/valo=1,524.99 2006.285.10:56:53.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.10:56:53.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.10:56:53.85#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:53.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:56:53.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:56:53.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:56:53.85#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:56:53.85#ibcon#first serial, iclass 12, count 0 2006.285.10:56:53.85#ibcon#enter sib2, iclass 12, count 0 2006.285.10:56:53.85#ibcon#flushed, iclass 12, count 0 2006.285.10:56:53.85#ibcon#about to write, iclass 12, count 0 2006.285.10:56:53.85#ibcon#wrote, iclass 12, count 0 2006.285.10:56:53.85#ibcon#about to read 3, iclass 12, count 0 2006.285.10:56:53.87#ibcon#read 3, iclass 12, count 0 2006.285.10:56:53.87#ibcon#about to read 4, iclass 12, count 0 2006.285.10:56:53.87#ibcon#read 4, iclass 12, count 0 2006.285.10:56:53.87#ibcon#about to read 5, iclass 12, count 0 2006.285.10:56:53.87#ibcon#read 5, iclass 12, count 0 2006.285.10:56:53.87#ibcon#about to read 6, iclass 12, count 0 2006.285.10:56:53.87#ibcon#read 6, iclass 12, count 0 2006.285.10:56:53.87#ibcon#end of sib2, iclass 12, count 0 2006.285.10:56:53.87#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:56:53.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:56:53.87#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.10:56:53.87#ibcon#*before write, iclass 12, count 0 2006.285.10:56:53.87#ibcon#enter sib2, iclass 12, count 0 2006.285.10:56:53.87#ibcon#flushed, iclass 12, count 0 2006.285.10:56:53.87#ibcon#about to write, iclass 12, count 0 2006.285.10:56:53.87#ibcon#wrote, iclass 12, count 0 2006.285.10:56:53.87#ibcon#about to read 3, iclass 12, count 0 2006.285.10:56:53.92#ibcon#read 3, iclass 12, count 0 2006.285.10:56:53.92#ibcon#about to read 4, iclass 12, count 0 2006.285.10:56:53.92#ibcon#read 4, iclass 12, count 0 2006.285.10:56:53.92#ibcon#about to read 5, iclass 12, count 0 2006.285.10:56:53.92#ibcon#read 5, iclass 12, count 0 2006.285.10:56:53.92#ibcon#about to read 6, iclass 12, count 0 2006.285.10:56:53.92#ibcon#read 6, iclass 12, count 0 2006.285.10:56:53.92#ibcon#end of sib2, iclass 12, count 0 2006.285.10:56:53.92#ibcon#*after write, iclass 12, count 0 2006.285.10:56:53.92#ibcon#*before return 0, iclass 12, count 0 2006.285.10:56:53.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:56:53.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:56:53.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:56:53.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:56:53.92$vck44/va=1,7 2006.285.10:56:53.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.10:56:53.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.10:56:53.92#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:53.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:56:53.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:56:53.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:56:53.92#ibcon#enter wrdev, iclass 14, count 2 2006.285.10:56:53.92#ibcon#first serial, iclass 14, count 2 2006.285.10:56:53.92#ibcon#enter sib2, iclass 14, count 2 2006.285.10:56:53.92#ibcon#flushed, iclass 14, count 2 2006.285.10:56:53.92#ibcon#about to write, iclass 14, count 2 2006.285.10:56:53.92#ibcon#wrote, iclass 14, count 2 2006.285.10:56:53.92#ibcon#about to read 3, iclass 14, count 2 2006.285.10:56:53.94#ibcon#read 3, iclass 14, count 2 2006.285.10:56:53.94#ibcon#about to read 4, iclass 14, count 2 2006.285.10:56:53.94#ibcon#read 4, iclass 14, count 2 2006.285.10:56:53.94#ibcon#about to read 5, iclass 14, count 2 2006.285.10:56:53.94#ibcon#read 5, iclass 14, count 2 2006.285.10:56:53.94#ibcon#about to read 6, iclass 14, count 2 2006.285.10:56:53.94#ibcon#read 6, iclass 14, count 2 2006.285.10:56:53.94#ibcon#end of sib2, iclass 14, count 2 2006.285.10:56:53.94#ibcon#*mode == 0, iclass 14, count 2 2006.285.10:56:53.94#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.10:56:53.94#ibcon#[25=AT01-07\r\n] 2006.285.10:56:53.94#ibcon#*before write, iclass 14, count 2 2006.285.10:56:53.94#ibcon#enter sib2, iclass 14, count 2 2006.285.10:56:53.94#ibcon#flushed, iclass 14, count 2 2006.285.10:56:53.94#ibcon#about to write, iclass 14, count 2 2006.285.10:56:53.94#ibcon#wrote, iclass 14, count 2 2006.285.10:56:53.94#ibcon#about to read 3, iclass 14, count 2 2006.285.10:56:53.97#ibcon#read 3, iclass 14, count 2 2006.285.10:56:53.97#ibcon#about to read 4, iclass 14, count 2 2006.285.10:56:53.97#ibcon#read 4, iclass 14, count 2 2006.285.10:56:53.97#ibcon#about to read 5, iclass 14, count 2 2006.285.10:56:53.97#ibcon#read 5, iclass 14, count 2 2006.285.10:56:53.97#ibcon#about to read 6, iclass 14, count 2 2006.285.10:56:53.97#ibcon#read 6, iclass 14, count 2 2006.285.10:56:53.97#ibcon#end of sib2, iclass 14, count 2 2006.285.10:56:53.97#ibcon#*after write, iclass 14, count 2 2006.285.10:56:53.97#ibcon#*before return 0, iclass 14, count 2 2006.285.10:56:53.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:56:53.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:56:53.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.10:56:53.97#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:53.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:56:54.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:56:54.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:56:54.09#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:56:54.09#ibcon#first serial, iclass 14, count 0 2006.285.10:56:54.09#ibcon#enter sib2, iclass 14, count 0 2006.285.10:56:54.09#ibcon#flushed, iclass 14, count 0 2006.285.10:56:54.09#ibcon#about to write, iclass 14, count 0 2006.285.10:56:54.09#ibcon#wrote, iclass 14, count 0 2006.285.10:56:54.09#ibcon#about to read 3, iclass 14, count 0 2006.285.10:56:54.11#ibcon#read 3, iclass 14, count 0 2006.285.10:56:54.11#ibcon#about to read 4, iclass 14, count 0 2006.285.10:56:54.11#ibcon#read 4, iclass 14, count 0 2006.285.10:56:54.11#ibcon#about to read 5, iclass 14, count 0 2006.285.10:56:54.11#ibcon#read 5, iclass 14, count 0 2006.285.10:56:54.11#ibcon#about to read 6, iclass 14, count 0 2006.285.10:56:54.11#ibcon#read 6, iclass 14, count 0 2006.285.10:56:54.11#ibcon#end of sib2, iclass 14, count 0 2006.285.10:56:54.11#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:56:54.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:56:54.11#ibcon#[25=USB\r\n] 2006.285.10:56:54.11#ibcon#*before write, iclass 14, count 0 2006.285.10:56:54.11#ibcon#enter sib2, iclass 14, count 0 2006.285.10:56:54.11#ibcon#flushed, iclass 14, count 0 2006.285.10:56:54.11#ibcon#about to write, iclass 14, count 0 2006.285.10:56:54.11#ibcon#wrote, iclass 14, count 0 2006.285.10:56:54.11#ibcon#about to read 3, iclass 14, count 0 2006.285.10:56:54.14#ibcon#read 3, iclass 14, count 0 2006.285.10:56:54.14#ibcon#about to read 4, iclass 14, count 0 2006.285.10:56:54.14#ibcon#read 4, iclass 14, count 0 2006.285.10:56:54.14#ibcon#about to read 5, iclass 14, count 0 2006.285.10:56:54.14#ibcon#read 5, iclass 14, count 0 2006.285.10:56:54.14#ibcon#about to read 6, iclass 14, count 0 2006.285.10:56:54.14#ibcon#read 6, iclass 14, count 0 2006.285.10:56:54.14#ibcon#end of sib2, iclass 14, count 0 2006.285.10:56:54.14#ibcon#*after write, iclass 14, count 0 2006.285.10:56:54.14#ibcon#*before return 0, iclass 14, count 0 2006.285.10:56:54.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:56:54.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:56:54.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:56:54.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:56:54.14$vck44/valo=2,534.99 2006.285.10:56:54.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.10:56:54.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.10:56:54.14#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:54.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:56:54.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:56:54.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:56:54.14#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:56:54.14#ibcon#first serial, iclass 16, count 0 2006.285.10:56:54.14#ibcon#enter sib2, iclass 16, count 0 2006.285.10:56:54.14#ibcon#flushed, iclass 16, count 0 2006.285.10:56:54.14#ibcon#about to write, iclass 16, count 0 2006.285.10:56:54.14#ibcon#wrote, iclass 16, count 0 2006.285.10:56:54.14#ibcon#about to read 3, iclass 16, count 0 2006.285.10:56:54.16#ibcon#read 3, iclass 16, count 0 2006.285.10:56:54.16#ibcon#about to read 4, iclass 16, count 0 2006.285.10:56:54.16#ibcon#read 4, iclass 16, count 0 2006.285.10:56:54.16#ibcon#about to read 5, iclass 16, count 0 2006.285.10:56:54.16#ibcon#read 5, iclass 16, count 0 2006.285.10:56:54.16#ibcon#about to read 6, iclass 16, count 0 2006.285.10:56:54.16#ibcon#read 6, iclass 16, count 0 2006.285.10:56:54.16#ibcon#end of sib2, iclass 16, count 0 2006.285.10:56:54.16#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:56:54.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:56:54.16#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.10:56:54.16#ibcon#*before write, iclass 16, count 0 2006.285.10:56:54.16#ibcon#enter sib2, iclass 16, count 0 2006.285.10:56:54.16#ibcon#flushed, iclass 16, count 0 2006.285.10:56:54.16#ibcon#about to write, iclass 16, count 0 2006.285.10:56:54.16#ibcon#wrote, iclass 16, count 0 2006.285.10:56:54.16#ibcon#about to read 3, iclass 16, count 0 2006.285.10:56:54.20#ibcon#read 3, iclass 16, count 0 2006.285.10:56:54.20#ibcon#about to read 4, iclass 16, count 0 2006.285.10:56:54.20#ibcon#read 4, iclass 16, count 0 2006.285.10:56:54.20#ibcon#about to read 5, iclass 16, count 0 2006.285.10:56:54.20#ibcon#read 5, iclass 16, count 0 2006.285.10:56:54.20#ibcon#about to read 6, iclass 16, count 0 2006.285.10:56:54.20#ibcon#read 6, iclass 16, count 0 2006.285.10:56:54.20#ibcon#end of sib2, iclass 16, count 0 2006.285.10:56:54.20#ibcon#*after write, iclass 16, count 0 2006.285.10:56:54.20#ibcon#*before return 0, iclass 16, count 0 2006.285.10:56:54.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:56:54.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:56:54.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:56:54.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:56:54.20$vck44/va=2,6 2006.285.10:56:54.20#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.10:56:54.20#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.10:56:54.20#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:54.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:56:54.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:56:54.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:56:54.26#ibcon#enter wrdev, iclass 18, count 2 2006.285.10:56:54.26#ibcon#first serial, iclass 18, count 2 2006.285.10:56:54.26#ibcon#enter sib2, iclass 18, count 2 2006.285.10:56:54.26#ibcon#flushed, iclass 18, count 2 2006.285.10:56:54.26#ibcon#about to write, iclass 18, count 2 2006.285.10:56:54.26#ibcon#wrote, iclass 18, count 2 2006.285.10:56:54.26#ibcon#about to read 3, iclass 18, count 2 2006.285.10:56:54.28#ibcon#read 3, iclass 18, count 2 2006.285.10:56:54.28#ibcon#about to read 4, iclass 18, count 2 2006.285.10:56:54.28#ibcon#read 4, iclass 18, count 2 2006.285.10:56:54.28#ibcon#about to read 5, iclass 18, count 2 2006.285.10:56:54.28#ibcon#read 5, iclass 18, count 2 2006.285.10:56:54.28#ibcon#about to read 6, iclass 18, count 2 2006.285.10:56:54.28#ibcon#read 6, iclass 18, count 2 2006.285.10:56:54.28#ibcon#end of sib2, iclass 18, count 2 2006.285.10:56:54.28#ibcon#*mode == 0, iclass 18, count 2 2006.285.10:56:54.28#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.10:56:54.28#ibcon#[25=AT02-06\r\n] 2006.285.10:56:54.28#ibcon#*before write, iclass 18, count 2 2006.285.10:56:54.28#ibcon#enter sib2, iclass 18, count 2 2006.285.10:56:54.28#ibcon#flushed, iclass 18, count 2 2006.285.10:56:54.28#ibcon#about to write, iclass 18, count 2 2006.285.10:56:54.28#ibcon#wrote, iclass 18, count 2 2006.285.10:56:54.28#ibcon#about to read 3, iclass 18, count 2 2006.285.10:56:54.31#ibcon#read 3, iclass 18, count 2 2006.285.10:56:54.31#ibcon#about to read 4, iclass 18, count 2 2006.285.10:56:54.31#ibcon#read 4, iclass 18, count 2 2006.285.10:56:54.31#ibcon#about to read 5, iclass 18, count 2 2006.285.10:56:54.31#ibcon#read 5, iclass 18, count 2 2006.285.10:56:54.31#ibcon#about to read 6, iclass 18, count 2 2006.285.10:56:54.31#ibcon#read 6, iclass 18, count 2 2006.285.10:56:54.31#ibcon#end of sib2, iclass 18, count 2 2006.285.10:56:54.31#ibcon#*after write, iclass 18, count 2 2006.285.10:56:54.31#ibcon#*before return 0, iclass 18, count 2 2006.285.10:56:54.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:56:54.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:56:54.31#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.10:56:54.31#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:54.31#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:56:54.43#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:56:54.43#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:56:54.43#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:56:54.43#ibcon#first serial, iclass 18, count 0 2006.285.10:56:54.43#ibcon#enter sib2, iclass 18, count 0 2006.285.10:56:54.43#ibcon#flushed, iclass 18, count 0 2006.285.10:56:54.43#ibcon#about to write, iclass 18, count 0 2006.285.10:56:54.43#ibcon#wrote, iclass 18, count 0 2006.285.10:56:54.43#ibcon#about to read 3, iclass 18, count 0 2006.285.10:56:54.45#ibcon#read 3, iclass 18, count 0 2006.285.10:56:54.45#ibcon#about to read 4, iclass 18, count 0 2006.285.10:56:54.45#ibcon#read 4, iclass 18, count 0 2006.285.10:56:54.45#ibcon#about to read 5, iclass 18, count 0 2006.285.10:56:54.45#ibcon#read 5, iclass 18, count 0 2006.285.10:56:54.45#ibcon#about to read 6, iclass 18, count 0 2006.285.10:56:54.45#ibcon#read 6, iclass 18, count 0 2006.285.10:56:54.45#ibcon#end of sib2, iclass 18, count 0 2006.285.10:56:54.45#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:56:54.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:56:54.45#ibcon#[25=USB\r\n] 2006.285.10:56:54.45#ibcon#*before write, iclass 18, count 0 2006.285.10:56:54.45#ibcon#enter sib2, iclass 18, count 0 2006.285.10:56:54.45#ibcon#flushed, iclass 18, count 0 2006.285.10:56:54.45#ibcon#about to write, iclass 18, count 0 2006.285.10:56:54.45#ibcon#wrote, iclass 18, count 0 2006.285.10:56:54.45#ibcon#about to read 3, iclass 18, count 0 2006.285.10:56:54.48#ibcon#read 3, iclass 18, count 0 2006.285.10:56:54.48#ibcon#about to read 4, iclass 18, count 0 2006.285.10:56:54.48#ibcon#read 4, iclass 18, count 0 2006.285.10:56:54.48#ibcon#about to read 5, iclass 18, count 0 2006.285.10:56:54.48#ibcon#read 5, iclass 18, count 0 2006.285.10:56:54.48#ibcon#about to read 6, iclass 18, count 0 2006.285.10:56:54.48#ibcon#read 6, iclass 18, count 0 2006.285.10:56:54.48#ibcon#end of sib2, iclass 18, count 0 2006.285.10:56:54.48#ibcon#*after write, iclass 18, count 0 2006.285.10:56:54.48#ibcon#*before return 0, iclass 18, count 0 2006.285.10:56:54.48#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:56:54.48#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:56:54.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:56:54.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:56:54.48$vck44/valo=3,564.99 2006.285.10:56:54.48#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.10:56:54.48#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.10:56:54.48#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:54.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:56:54.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:56:54.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:56:54.48#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:56:54.48#ibcon#first serial, iclass 20, count 0 2006.285.10:56:54.48#ibcon#enter sib2, iclass 20, count 0 2006.285.10:56:54.48#ibcon#flushed, iclass 20, count 0 2006.285.10:56:54.48#ibcon#about to write, iclass 20, count 0 2006.285.10:56:54.48#ibcon#wrote, iclass 20, count 0 2006.285.10:56:54.48#ibcon#about to read 3, iclass 20, count 0 2006.285.10:56:54.50#ibcon#read 3, iclass 20, count 0 2006.285.10:56:54.50#ibcon#about to read 4, iclass 20, count 0 2006.285.10:56:54.50#ibcon#read 4, iclass 20, count 0 2006.285.10:56:54.50#ibcon#about to read 5, iclass 20, count 0 2006.285.10:56:54.50#ibcon#read 5, iclass 20, count 0 2006.285.10:56:54.50#ibcon#about to read 6, iclass 20, count 0 2006.285.10:56:54.50#ibcon#read 6, iclass 20, count 0 2006.285.10:56:54.50#ibcon#end of sib2, iclass 20, count 0 2006.285.10:56:54.50#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:56:54.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:56:54.50#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.10:56:54.50#ibcon#*before write, iclass 20, count 0 2006.285.10:56:54.50#ibcon#enter sib2, iclass 20, count 0 2006.285.10:56:54.50#ibcon#flushed, iclass 20, count 0 2006.285.10:56:54.50#ibcon#about to write, iclass 20, count 0 2006.285.10:56:54.50#ibcon#wrote, iclass 20, count 0 2006.285.10:56:54.50#ibcon#about to read 3, iclass 20, count 0 2006.285.10:56:54.54#ibcon#read 3, iclass 20, count 0 2006.285.10:56:54.54#ibcon#about to read 4, iclass 20, count 0 2006.285.10:56:54.54#ibcon#read 4, iclass 20, count 0 2006.285.10:56:54.54#ibcon#about to read 5, iclass 20, count 0 2006.285.10:56:54.54#ibcon#read 5, iclass 20, count 0 2006.285.10:56:54.54#ibcon#about to read 6, iclass 20, count 0 2006.285.10:56:54.54#ibcon#read 6, iclass 20, count 0 2006.285.10:56:54.54#ibcon#end of sib2, iclass 20, count 0 2006.285.10:56:54.54#ibcon#*after write, iclass 20, count 0 2006.285.10:56:54.54#ibcon#*before return 0, iclass 20, count 0 2006.285.10:56:54.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:56:54.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:56:54.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:56:54.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:56:54.54$vck44/va=3,7 2006.285.10:56:54.54#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.10:56:54.54#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.10:56:54.54#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:54.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:56:54.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:56:54.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:56:54.60#ibcon#enter wrdev, iclass 22, count 2 2006.285.10:56:54.60#ibcon#first serial, iclass 22, count 2 2006.285.10:56:54.60#ibcon#enter sib2, iclass 22, count 2 2006.285.10:56:54.60#ibcon#flushed, iclass 22, count 2 2006.285.10:56:54.60#ibcon#about to write, iclass 22, count 2 2006.285.10:56:54.60#ibcon#wrote, iclass 22, count 2 2006.285.10:56:54.60#ibcon#about to read 3, iclass 22, count 2 2006.285.10:56:54.62#ibcon#read 3, iclass 22, count 2 2006.285.10:56:54.62#ibcon#about to read 4, iclass 22, count 2 2006.285.10:56:54.62#ibcon#read 4, iclass 22, count 2 2006.285.10:56:54.62#ibcon#about to read 5, iclass 22, count 2 2006.285.10:56:54.62#ibcon#read 5, iclass 22, count 2 2006.285.10:56:54.62#ibcon#about to read 6, iclass 22, count 2 2006.285.10:56:54.62#ibcon#read 6, iclass 22, count 2 2006.285.10:56:54.62#ibcon#end of sib2, iclass 22, count 2 2006.285.10:56:54.62#ibcon#*mode == 0, iclass 22, count 2 2006.285.10:56:54.62#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.10:56:54.62#ibcon#[25=AT03-07\r\n] 2006.285.10:56:54.62#ibcon#*before write, iclass 22, count 2 2006.285.10:56:54.62#ibcon#enter sib2, iclass 22, count 2 2006.285.10:56:54.62#ibcon#flushed, iclass 22, count 2 2006.285.10:56:54.62#ibcon#about to write, iclass 22, count 2 2006.285.10:56:54.62#ibcon#wrote, iclass 22, count 2 2006.285.10:56:54.62#ibcon#about to read 3, iclass 22, count 2 2006.285.10:56:54.65#ibcon#read 3, iclass 22, count 2 2006.285.10:56:54.65#ibcon#about to read 4, iclass 22, count 2 2006.285.10:56:54.65#ibcon#read 4, iclass 22, count 2 2006.285.10:56:54.65#ibcon#about to read 5, iclass 22, count 2 2006.285.10:56:54.65#ibcon#read 5, iclass 22, count 2 2006.285.10:56:54.65#ibcon#about to read 6, iclass 22, count 2 2006.285.10:56:54.65#ibcon#read 6, iclass 22, count 2 2006.285.10:56:54.65#ibcon#end of sib2, iclass 22, count 2 2006.285.10:56:54.65#ibcon#*after write, iclass 22, count 2 2006.285.10:56:54.65#ibcon#*before return 0, iclass 22, count 2 2006.285.10:56:54.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:56:54.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:56:54.65#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.10:56:54.65#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:54.65#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:56:54.77#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:56:54.77#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:56:54.77#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:56:54.77#ibcon#first serial, iclass 22, count 0 2006.285.10:56:54.77#ibcon#enter sib2, iclass 22, count 0 2006.285.10:56:54.77#ibcon#flushed, iclass 22, count 0 2006.285.10:56:54.77#ibcon#about to write, iclass 22, count 0 2006.285.10:56:54.77#ibcon#wrote, iclass 22, count 0 2006.285.10:56:54.77#ibcon#about to read 3, iclass 22, count 0 2006.285.10:56:54.79#ibcon#read 3, iclass 22, count 0 2006.285.10:56:54.79#ibcon#about to read 4, iclass 22, count 0 2006.285.10:56:54.79#ibcon#read 4, iclass 22, count 0 2006.285.10:56:54.79#ibcon#about to read 5, iclass 22, count 0 2006.285.10:56:54.79#ibcon#read 5, iclass 22, count 0 2006.285.10:56:54.79#ibcon#about to read 6, iclass 22, count 0 2006.285.10:56:54.79#ibcon#read 6, iclass 22, count 0 2006.285.10:56:54.79#ibcon#end of sib2, iclass 22, count 0 2006.285.10:56:54.79#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:56:54.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:56:54.79#ibcon#[25=USB\r\n] 2006.285.10:56:54.79#ibcon#*before write, iclass 22, count 0 2006.285.10:56:54.79#ibcon#enter sib2, iclass 22, count 0 2006.285.10:56:54.79#ibcon#flushed, iclass 22, count 0 2006.285.10:56:54.79#ibcon#about to write, iclass 22, count 0 2006.285.10:56:54.79#ibcon#wrote, iclass 22, count 0 2006.285.10:56:54.79#ibcon#about to read 3, iclass 22, count 0 2006.285.10:56:54.82#ibcon#read 3, iclass 22, count 0 2006.285.10:56:54.82#ibcon#about to read 4, iclass 22, count 0 2006.285.10:56:54.82#ibcon#read 4, iclass 22, count 0 2006.285.10:56:54.82#ibcon#about to read 5, iclass 22, count 0 2006.285.10:56:54.82#ibcon#read 5, iclass 22, count 0 2006.285.10:56:54.82#ibcon#about to read 6, iclass 22, count 0 2006.285.10:56:54.82#ibcon#read 6, iclass 22, count 0 2006.285.10:56:54.82#ibcon#end of sib2, iclass 22, count 0 2006.285.10:56:54.82#ibcon#*after write, iclass 22, count 0 2006.285.10:56:54.82#ibcon#*before return 0, iclass 22, count 0 2006.285.10:56:54.82#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:56:54.82#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:56:54.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:56:54.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:56:54.82$vck44/valo=4,624.99 2006.285.10:56:54.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.10:56:54.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.10:56:54.82#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:54.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:56:54.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:56:54.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:56:54.82#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:56:54.82#ibcon#first serial, iclass 24, count 0 2006.285.10:56:54.82#ibcon#enter sib2, iclass 24, count 0 2006.285.10:56:54.82#ibcon#flushed, iclass 24, count 0 2006.285.10:56:54.82#ibcon#about to write, iclass 24, count 0 2006.285.10:56:54.82#ibcon#wrote, iclass 24, count 0 2006.285.10:56:54.82#ibcon#about to read 3, iclass 24, count 0 2006.285.10:56:54.84#ibcon#read 3, iclass 24, count 0 2006.285.10:56:54.84#ibcon#about to read 4, iclass 24, count 0 2006.285.10:56:54.84#ibcon#read 4, iclass 24, count 0 2006.285.10:56:54.84#ibcon#about to read 5, iclass 24, count 0 2006.285.10:56:54.84#ibcon#read 5, iclass 24, count 0 2006.285.10:56:54.84#ibcon#about to read 6, iclass 24, count 0 2006.285.10:56:54.84#ibcon#read 6, iclass 24, count 0 2006.285.10:56:54.84#ibcon#end of sib2, iclass 24, count 0 2006.285.10:56:54.84#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:56:54.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:56:54.84#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.10:56:54.84#ibcon#*before write, iclass 24, count 0 2006.285.10:56:54.84#ibcon#enter sib2, iclass 24, count 0 2006.285.10:56:54.84#ibcon#flushed, iclass 24, count 0 2006.285.10:56:54.84#ibcon#about to write, iclass 24, count 0 2006.285.10:56:54.84#ibcon#wrote, iclass 24, count 0 2006.285.10:56:54.84#ibcon#about to read 3, iclass 24, count 0 2006.285.10:56:54.88#ibcon#read 3, iclass 24, count 0 2006.285.10:56:54.88#ibcon#about to read 4, iclass 24, count 0 2006.285.10:56:54.88#ibcon#read 4, iclass 24, count 0 2006.285.10:56:54.88#ibcon#about to read 5, iclass 24, count 0 2006.285.10:56:54.88#ibcon#read 5, iclass 24, count 0 2006.285.10:56:54.88#ibcon#about to read 6, iclass 24, count 0 2006.285.10:56:54.88#ibcon#read 6, iclass 24, count 0 2006.285.10:56:54.88#ibcon#end of sib2, iclass 24, count 0 2006.285.10:56:54.88#ibcon#*after write, iclass 24, count 0 2006.285.10:56:54.88#ibcon#*before return 0, iclass 24, count 0 2006.285.10:56:54.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:56:54.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:56:54.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:56:54.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:56:54.88$vck44/va=4,6 2006.285.10:56:54.88#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.10:56:54.88#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.10:56:54.88#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:54.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:56:54.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:56:54.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:56:54.94#ibcon#enter wrdev, iclass 26, count 2 2006.285.10:56:54.94#ibcon#first serial, iclass 26, count 2 2006.285.10:56:54.94#ibcon#enter sib2, iclass 26, count 2 2006.285.10:56:54.94#ibcon#flushed, iclass 26, count 2 2006.285.10:56:54.94#ibcon#about to write, iclass 26, count 2 2006.285.10:56:54.94#ibcon#wrote, iclass 26, count 2 2006.285.10:56:54.94#ibcon#about to read 3, iclass 26, count 2 2006.285.10:56:54.96#ibcon#read 3, iclass 26, count 2 2006.285.10:56:54.96#ibcon#about to read 4, iclass 26, count 2 2006.285.10:56:54.96#ibcon#read 4, iclass 26, count 2 2006.285.10:56:54.96#ibcon#about to read 5, iclass 26, count 2 2006.285.10:56:54.96#ibcon#read 5, iclass 26, count 2 2006.285.10:56:54.96#ibcon#about to read 6, iclass 26, count 2 2006.285.10:56:54.96#ibcon#read 6, iclass 26, count 2 2006.285.10:56:54.96#ibcon#end of sib2, iclass 26, count 2 2006.285.10:56:54.96#ibcon#*mode == 0, iclass 26, count 2 2006.285.10:56:54.96#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.10:56:54.96#ibcon#[25=AT04-06\r\n] 2006.285.10:56:54.96#ibcon#*before write, iclass 26, count 2 2006.285.10:56:54.96#ibcon#enter sib2, iclass 26, count 2 2006.285.10:56:54.96#ibcon#flushed, iclass 26, count 2 2006.285.10:56:54.96#ibcon#about to write, iclass 26, count 2 2006.285.10:56:54.96#ibcon#wrote, iclass 26, count 2 2006.285.10:56:54.96#ibcon#about to read 3, iclass 26, count 2 2006.285.10:56:54.99#ibcon#read 3, iclass 26, count 2 2006.285.10:56:54.99#ibcon#about to read 4, iclass 26, count 2 2006.285.10:56:54.99#ibcon#read 4, iclass 26, count 2 2006.285.10:56:54.99#ibcon#about to read 5, iclass 26, count 2 2006.285.10:56:54.99#ibcon#read 5, iclass 26, count 2 2006.285.10:56:54.99#ibcon#about to read 6, iclass 26, count 2 2006.285.10:56:54.99#ibcon#read 6, iclass 26, count 2 2006.285.10:56:54.99#ibcon#end of sib2, iclass 26, count 2 2006.285.10:56:54.99#ibcon#*after write, iclass 26, count 2 2006.285.10:56:54.99#ibcon#*before return 0, iclass 26, count 2 2006.285.10:56:54.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:56:54.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:56:54.99#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.10:56:54.99#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:54.99#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:56:55.11#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:56:55.11#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:56:55.11#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:56:55.11#ibcon#first serial, iclass 26, count 0 2006.285.10:56:55.11#ibcon#enter sib2, iclass 26, count 0 2006.285.10:56:55.11#ibcon#flushed, iclass 26, count 0 2006.285.10:56:55.11#ibcon#about to write, iclass 26, count 0 2006.285.10:56:55.11#ibcon#wrote, iclass 26, count 0 2006.285.10:56:55.11#ibcon#about to read 3, iclass 26, count 0 2006.285.10:56:55.13#ibcon#read 3, iclass 26, count 0 2006.285.10:56:55.13#ibcon#about to read 4, iclass 26, count 0 2006.285.10:56:55.13#ibcon#read 4, iclass 26, count 0 2006.285.10:56:55.13#ibcon#about to read 5, iclass 26, count 0 2006.285.10:56:55.13#ibcon#read 5, iclass 26, count 0 2006.285.10:56:55.13#ibcon#about to read 6, iclass 26, count 0 2006.285.10:56:55.13#ibcon#read 6, iclass 26, count 0 2006.285.10:56:55.13#ibcon#end of sib2, iclass 26, count 0 2006.285.10:56:55.13#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:56:55.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:56:55.13#ibcon#[25=USB\r\n] 2006.285.10:56:55.13#ibcon#*before write, iclass 26, count 0 2006.285.10:56:55.13#ibcon#enter sib2, iclass 26, count 0 2006.285.10:56:55.13#ibcon#flushed, iclass 26, count 0 2006.285.10:56:55.13#ibcon#about to write, iclass 26, count 0 2006.285.10:56:55.13#ibcon#wrote, iclass 26, count 0 2006.285.10:56:55.13#ibcon#about to read 3, iclass 26, count 0 2006.285.10:56:55.16#ibcon#read 3, iclass 26, count 0 2006.285.10:56:55.16#ibcon#about to read 4, iclass 26, count 0 2006.285.10:56:55.16#ibcon#read 4, iclass 26, count 0 2006.285.10:56:55.16#ibcon#about to read 5, iclass 26, count 0 2006.285.10:56:55.16#ibcon#read 5, iclass 26, count 0 2006.285.10:56:55.16#ibcon#about to read 6, iclass 26, count 0 2006.285.10:56:55.16#ibcon#read 6, iclass 26, count 0 2006.285.10:56:55.16#ibcon#end of sib2, iclass 26, count 0 2006.285.10:56:55.16#ibcon#*after write, iclass 26, count 0 2006.285.10:56:55.16#ibcon#*before return 0, iclass 26, count 0 2006.285.10:56:55.16#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:56:55.16#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:56:55.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:56:55.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:56:55.16$vck44/valo=5,734.99 2006.285.10:56:55.16#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.10:56:55.16#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.10:56:55.16#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:55.16#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:56:55.16#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:56:55.16#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:56:55.16#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:56:55.16#ibcon#first serial, iclass 28, count 0 2006.285.10:56:55.16#ibcon#enter sib2, iclass 28, count 0 2006.285.10:56:55.16#ibcon#flushed, iclass 28, count 0 2006.285.10:56:55.16#ibcon#about to write, iclass 28, count 0 2006.285.10:56:55.16#ibcon#wrote, iclass 28, count 0 2006.285.10:56:55.16#ibcon#about to read 3, iclass 28, count 0 2006.285.10:56:55.18#ibcon#read 3, iclass 28, count 0 2006.285.10:56:55.18#ibcon#about to read 4, iclass 28, count 0 2006.285.10:56:55.18#ibcon#read 4, iclass 28, count 0 2006.285.10:56:55.18#ibcon#about to read 5, iclass 28, count 0 2006.285.10:56:55.18#ibcon#read 5, iclass 28, count 0 2006.285.10:56:55.18#ibcon#about to read 6, iclass 28, count 0 2006.285.10:56:55.18#ibcon#read 6, iclass 28, count 0 2006.285.10:56:55.18#ibcon#end of sib2, iclass 28, count 0 2006.285.10:56:55.18#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:56:55.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:56:55.18#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.10:56:55.18#ibcon#*before write, iclass 28, count 0 2006.285.10:56:55.18#ibcon#enter sib2, iclass 28, count 0 2006.285.10:56:55.18#ibcon#flushed, iclass 28, count 0 2006.285.10:56:55.18#ibcon#about to write, iclass 28, count 0 2006.285.10:56:55.18#ibcon#wrote, iclass 28, count 0 2006.285.10:56:55.18#ibcon#about to read 3, iclass 28, count 0 2006.285.10:56:55.22#ibcon#read 3, iclass 28, count 0 2006.285.10:56:55.22#ibcon#about to read 4, iclass 28, count 0 2006.285.10:56:55.22#ibcon#read 4, iclass 28, count 0 2006.285.10:56:55.22#ibcon#about to read 5, iclass 28, count 0 2006.285.10:56:55.22#ibcon#read 5, iclass 28, count 0 2006.285.10:56:55.22#ibcon#about to read 6, iclass 28, count 0 2006.285.10:56:55.22#ibcon#read 6, iclass 28, count 0 2006.285.10:56:55.22#ibcon#end of sib2, iclass 28, count 0 2006.285.10:56:55.22#ibcon#*after write, iclass 28, count 0 2006.285.10:56:55.22#ibcon#*before return 0, iclass 28, count 0 2006.285.10:56:55.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:56:55.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:56:55.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:56:55.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:56:55.22$vck44/va=5,3 2006.285.10:56:55.22#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.10:56:55.22#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.10:56:55.22#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:55.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:56:55.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:56:55.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:56:55.28#ibcon#enter wrdev, iclass 30, count 2 2006.285.10:56:55.28#ibcon#first serial, iclass 30, count 2 2006.285.10:56:55.28#ibcon#enter sib2, iclass 30, count 2 2006.285.10:56:55.28#ibcon#flushed, iclass 30, count 2 2006.285.10:56:55.28#ibcon#about to write, iclass 30, count 2 2006.285.10:56:55.28#ibcon#wrote, iclass 30, count 2 2006.285.10:56:55.28#ibcon#about to read 3, iclass 30, count 2 2006.285.10:56:55.30#ibcon#read 3, iclass 30, count 2 2006.285.10:56:55.30#ibcon#about to read 4, iclass 30, count 2 2006.285.10:56:55.30#ibcon#read 4, iclass 30, count 2 2006.285.10:56:55.30#ibcon#about to read 5, iclass 30, count 2 2006.285.10:56:55.30#ibcon#read 5, iclass 30, count 2 2006.285.10:56:55.30#ibcon#about to read 6, iclass 30, count 2 2006.285.10:56:55.30#ibcon#read 6, iclass 30, count 2 2006.285.10:56:55.30#ibcon#end of sib2, iclass 30, count 2 2006.285.10:56:55.30#ibcon#*mode == 0, iclass 30, count 2 2006.285.10:56:55.30#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.10:56:55.30#ibcon#[25=AT05-03\r\n] 2006.285.10:56:55.30#ibcon#*before write, iclass 30, count 2 2006.285.10:56:55.30#ibcon#enter sib2, iclass 30, count 2 2006.285.10:56:55.30#ibcon#flushed, iclass 30, count 2 2006.285.10:56:55.30#ibcon#about to write, iclass 30, count 2 2006.285.10:56:55.30#ibcon#wrote, iclass 30, count 2 2006.285.10:56:55.30#ibcon#about to read 3, iclass 30, count 2 2006.285.10:56:55.33#ibcon#read 3, iclass 30, count 2 2006.285.10:56:55.33#ibcon#about to read 4, iclass 30, count 2 2006.285.10:56:55.33#ibcon#read 4, iclass 30, count 2 2006.285.10:56:55.33#ibcon#about to read 5, iclass 30, count 2 2006.285.10:56:55.33#ibcon#read 5, iclass 30, count 2 2006.285.10:56:55.33#ibcon#about to read 6, iclass 30, count 2 2006.285.10:56:55.33#ibcon#read 6, iclass 30, count 2 2006.285.10:56:55.33#ibcon#end of sib2, iclass 30, count 2 2006.285.10:56:55.33#ibcon#*after write, iclass 30, count 2 2006.285.10:56:55.33#ibcon#*before return 0, iclass 30, count 2 2006.285.10:56:55.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:56:55.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:56:55.33#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.10:56:55.33#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:55.33#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:56:55.45#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:56:55.45#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:56:55.45#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:56:55.45#ibcon#first serial, iclass 30, count 0 2006.285.10:56:55.45#ibcon#enter sib2, iclass 30, count 0 2006.285.10:56:55.45#ibcon#flushed, iclass 30, count 0 2006.285.10:56:55.45#ibcon#about to write, iclass 30, count 0 2006.285.10:56:55.45#ibcon#wrote, iclass 30, count 0 2006.285.10:56:55.45#ibcon#about to read 3, iclass 30, count 0 2006.285.10:56:55.47#ibcon#read 3, iclass 30, count 0 2006.285.10:56:55.47#ibcon#about to read 4, iclass 30, count 0 2006.285.10:56:55.47#ibcon#read 4, iclass 30, count 0 2006.285.10:56:55.47#ibcon#about to read 5, iclass 30, count 0 2006.285.10:56:55.47#ibcon#read 5, iclass 30, count 0 2006.285.10:56:55.47#ibcon#about to read 6, iclass 30, count 0 2006.285.10:56:55.47#ibcon#read 6, iclass 30, count 0 2006.285.10:56:55.47#ibcon#end of sib2, iclass 30, count 0 2006.285.10:56:55.47#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:56:55.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:56:55.47#ibcon#[25=USB\r\n] 2006.285.10:56:55.47#ibcon#*before write, iclass 30, count 0 2006.285.10:56:55.47#ibcon#enter sib2, iclass 30, count 0 2006.285.10:56:55.47#ibcon#flushed, iclass 30, count 0 2006.285.10:56:55.47#ibcon#about to write, iclass 30, count 0 2006.285.10:56:55.47#ibcon#wrote, iclass 30, count 0 2006.285.10:56:55.47#ibcon#about to read 3, iclass 30, count 0 2006.285.10:56:55.50#ibcon#read 3, iclass 30, count 0 2006.285.10:56:55.50#ibcon#about to read 4, iclass 30, count 0 2006.285.10:56:55.50#ibcon#read 4, iclass 30, count 0 2006.285.10:56:55.50#ibcon#about to read 5, iclass 30, count 0 2006.285.10:56:55.50#ibcon#read 5, iclass 30, count 0 2006.285.10:56:55.50#ibcon#about to read 6, iclass 30, count 0 2006.285.10:56:55.50#ibcon#read 6, iclass 30, count 0 2006.285.10:56:55.50#ibcon#end of sib2, iclass 30, count 0 2006.285.10:56:55.50#ibcon#*after write, iclass 30, count 0 2006.285.10:56:55.50#ibcon#*before return 0, iclass 30, count 0 2006.285.10:56:55.50#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:56:55.50#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:56:55.50#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:56:55.50#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:56:55.50$vck44/valo=6,814.99 2006.285.10:56:55.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.10:56:55.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.10:56:55.50#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:55.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:56:55.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:56:55.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:56:55.50#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:56:55.50#ibcon#first serial, iclass 32, count 0 2006.285.10:56:55.50#ibcon#enter sib2, iclass 32, count 0 2006.285.10:56:55.50#ibcon#flushed, iclass 32, count 0 2006.285.10:56:55.50#ibcon#about to write, iclass 32, count 0 2006.285.10:56:55.50#ibcon#wrote, iclass 32, count 0 2006.285.10:56:55.50#ibcon#about to read 3, iclass 32, count 0 2006.285.10:56:55.52#ibcon#read 3, iclass 32, count 0 2006.285.10:56:55.52#ibcon#about to read 4, iclass 32, count 0 2006.285.10:56:55.52#ibcon#read 4, iclass 32, count 0 2006.285.10:56:55.52#ibcon#about to read 5, iclass 32, count 0 2006.285.10:56:55.52#ibcon#read 5, iclass 32, count 0 2006.285.10:56:55.52#ibcon#about to read 6, iclass 32, count 0 2006.285.10:56:55.52#ibcon#read 6, iclass 32, count 0 2006.285.10:56:55.52#ibcon#end of sib2, iclass 32, count 0 2006.285.10:56:55.52#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:56:55.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:56:55.52#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.10:56:55.52#ibcon#*before write, iclass 32, count 0 2006.285.10:56:55.52#ibcon#enter sib2, iclass 32, count 0 2006.285.10:56:55.52#ibcon#flushed, iclass 32, count 0 2006.285.10:56:55.52#ibcon#about to write, iclass 32, count 0 2006.285.10:56:55.52#ibcon#wrote, iclass 32, count 0 2006.285.10:56:55.52#ibcon#about to read 3, iclass 32, count 0 2006.285.10:56:55.56#ibcon#read 3, iclass 32, count 0 2006.285.10:56:55.56#ibcon#about to read 4, iclass 32, count 0 2006.285.10:56:55.56#ibcon#read 4, iclass 32, count 0 2006.285.10:56:55.56#ibcon#about to read 5, iclass 32, count 0 2006.285.10:56:55.56#ibcon#read 5, iclass 32, count 0 2006.285.10:56:55.56#ibcon#about to read 6, iclass 32, count 0 2006.285.10:56:55.56#ibcon#read 6, iclass 32, count 0 2006.285.10:56:55.56#ibcon#end of sib2, iclass 32, count 0 2006.285.10:56:55.56#ibcon#*after write, iclass 32, count 0 2006.285.10:56:55.56#ibcon#*before return 0, iclass 32, count 0 2006.285.10:56:55.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:56:55.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:56:55.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:56:55.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:56:55.56$vck44/va=6,4 2006.285.10:56:55.56#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.10:56:55.56#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.10:56:55.56#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:55.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:56:55.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:56:55.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:56:55.62#ibcon#enter wrdev, iclass 34, count 2 2006.285.10:56:55.62#ibcon#first serial, iclass 34, count 2 2006.285.10:56:55.62#ibcon#enter sib2, iclass 34, count 2 2006.285.10:56:55.62#ibcon#flushed, iclass 34, count 2 2006.285.10:56:55.62#ibcon#about to write, iclass 34, count 2 2006.285.10:56:55.62#ibcon#wrote, iclass 34, count 2 2006.285.10:56:55.62#ibcon#about to read 3, iclass 34, count 2 2006.285.10:56:55.64#ibcon#read 3, iclass 34, count 2 2006.285.10:56:55.64#ibcon#about to read 4, iclass 34, count 2 2006.285.10:56:55.64#ibcon#read 4, iclass 34, count 2 2006.285.10:56:55.64#ibcon#about to read 5, iclass 34, count 2 2006.285.10:56:55.64#ibcon#read 5, iclass 34, count 2 2006.285.10:56:55.64#ibcon#about to read 6, iclass 34, count 2 2006.285.10:56:55.64#ibcon#read 6, iclass 34, count 2 2006.285.10:56:55.64#ibcon#end of sib2, iclass 34, count 2 2006.285.10:56:55.64#ibcon#*mode == 0, iclass 34, count 2 2006.285.10:56:55.64#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.10:56:55.64#ibcon#[25=AT06-04\r\n] 2006.285.10:56:55.64#ibcon#*before write, iclass 34, count 2 2006.285.10:56:55.64#ibcon#enter sib2, iclass 34, count 2 2006.285.10:56:55.64#ibcon#flushed, iclass 34, count 2 2006.285.10:56:55.64#ibcon#about to write, iclass 34, count 2 2006.285.10:56:55.64#ibcon#wrote, iclass 34, count 2 2006.285.10:56:55.64#ibcon#about to read 3, iclass 34, count 2 2006.285.10:56:55.67#ibcon#read 3, iclass 34, count 2 2006.285.10:56:55.67#ibcon#about to read 4, iclass 34, count 2 2006.285.10:56:55.67#ibcon#read 4, iclass 34, count 2 2006.285.10:56:55.67#ibcon#about to read 5, iclass 34, count 2 2006.285.10:56:55.67#ibcon#read 5, iclass 34, count 2 2006.285.10:56:55.67#ibcon#about to read 6, iclass 34, count 2 2006.285.10:56:55.67#ibcon#read 6, iclass 34, count 2 2006.285.10:56:55.67#ibcon#end of sib2, iclass 34, count 2 2006.285.10:56:55.67#ibcon#*after write, iclass 34, count 2 2006.285.10:56:55.67#ibcon#*before return 0, iclass 34, count 2 2006.285.10:56:55.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:56:55.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:56:55.67#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.10:56:55.67#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:55.67#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:56:55.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:56:55.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:56:55.79#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:56:55.79#ibcon#first serial, iclass 34, count 0 2006.285.10:56:55.79#ibcon#enter sib2, iclass 34, count 0 2006.285.10:56:55.79#ibcon#flushed, iclass 34, count 0 2006.285.10:56:55.79#ibcon#about to write, iclass 34, count 0 2006.285.10:56:55.79#ibcon#wrote, iclass 34, count 0 2006.285.10:56:55.79#ibcon#about to read 3, iclass 34, count 0 2006.285.10:56:55.81#ibcon#read 3, iclass 34, count 0 2006.285.10:56:55.81#ibcon#about to read 4, iclass 34, count 0 2006.285.10:56:55.81#ibcon#read 4, iclass 34, count 0 2006.285.10:56:55.81#ibcon#about to read 5, iclass 34, count 0 2006.285.10:56:55.81#ibcon#read 5, iclass 34, count 0 2006.285.10:56:55.81#ibcon#about to read 6, iclass 34, count 0 2006.285.10:56:55.81#ibcon#read 6, iclass 34, count 0 2006.285.10:56:55.81#ibcon#end of sib2, iclass 34, count 0 2006.285.10:56:55.81#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:56:55.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:56:55.81#ibcon#[25=USB\r\n] 2006.285.10:56:55.81#ibcon#*before write, iclass 34, count 0 2006.285.10:56:55.81#ibcon#enter sib2, iclass 34, count 0 2006.285.10:56:55.81#ibcon#flushed, iclass 34, count 0 2006.285.10:56:55.81#ibcon#about to write, iclass 34, count 0 2006.285.10:56:55.81#ibcon#wrote, iclass 34, count 0 2006.285.10:56:55.81#ibcon#about to read 3, iclass 34, count 0 2006.285.10:56:55.84#ibcon#read 3, iclass 34, count 0 2006.285.10:56:55.84#ibcon#about to read 4, iclass 34, count 0 2006.285.10:56:55.84#ibcon#read 4, iclass 34, count 0 2006.285.10:56:55.84#ibcon#about to read 5, iclass 34, count 0 2006.285.10:56:55.84#ibcon#read 5, iclass 34, count 0 2006.285.10:56:55.84#ibcon#about to read 6, iclass 34, count 0 2006.285.10:56:55.84#ibcon#read 6, iclass 34, count 0 2006.285.10:56:55.84#ibcon#end of sib2, iclass 34, count 0 2006.285.10:56:55.84#ibcon#*after write, iclass 34, count 0 2006.285.10:56:55.84#ibcon#*before return 0, iclass 34, count 0 2006.285.10:56:55.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:56:55.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:56:55.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:56:55.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:56:55.84$vck44/valo=7,864.99 2006.285.10:56:55.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.10:56:55.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.10:56:55.84#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:55.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:56:55.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:56:55.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:56:55.84#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:56:55.84#ibcon#first serial, iclass 36, count 0 2006.285.10:56:55.84#ibcon#enter sib2, iclass 36, count 0 2006.285.10:56:55.84#ibcon#flushed, iclass 36, count 0 2006.285.10:56:55.84#ibcon#about to write, iclass 36, count 0 2006.285.10:56:55.84#ibcon#wrote, iclass 36, count 0 2006.285.10:56:55.84#ibcon#about to read 3, iclass 36, count 0 2006.285.10:56:55.86#ibcon#read 3, iclass 36, count 0 2006.285.10:56:55.86#ibcon#about to read 4, iclass 36, count 0 2006.285.10:56:55.86#ibcon#read 4, iclass 36, count 0 2006.285.10:56:55.86#ibcon#about to read 5, iclass 36, count 0 2006.285.10:56:55.86#ibcon#read 5, iclass 36, count 0 2006.285.10:56:55.86#ibcon#about to read 6, iclass 36, count 0 2006.285.10:56:55.86#ibcon#read 6, iclass 36, count 0 2006.285.10:56:55.86#ibcon#end of sib2, iclass 36, count 0 2006.285.10:56:55.86#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:56:55.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:56:55.86#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.10:56:55.86#ibcon#*before write, iclass 36, count 0 2006.285.10:56:55.86#ibcon#enter sib2, iclass 36, count 0 2006.285.10:56:55.86#ibcon#flushed, iclass 36, count 0 2006.285.10:56:55.86#ibcon#about to write, iclass 36, count 0 2006.285.10:56:55.86#ibcon#wrote, iclass 36, count 0 2006.285.10:56:55.86#ibcon#about to read 3, iclass 36, count 0 2006.285.10:56:55.90#ibcon#read 3, iclass 36, count 0 2006.285.10:56:55.90#ibcon#about to read 4, iclass 36, count 0 2006.285.10:56:55.90#ibcon#read 4, iclass 36, count 0 2006.285.10:56:55.90#ibcon#about to read 5, iclass 36, count 0 2006.285.10:56:55.90#ibcon#read 5, iclass 36, count 0 2006.285.10:56:55.90#ibcon#about to read 6, iclass 36, count 0 2006.285.10:56:55.90#ibcon#read 6, iclass 36, count 0 2006.285.10:56:55.90#ibcon#end of sib2, iclass 36, count 0 2006.285.10:56:55.90#ibcon#*after write, iclass 36, count 0 2006.285.10:56:55.90#ibcon#*before return 0, iclass 36, count 0 2006.285.10:56:55.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:56:55.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:56:55.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:56:55.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:56:55.90$vck44/va=7,4 2006.285.10:56:55.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.10:56:55.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.10:56:55.90#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:55.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:56:55.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:56:55.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:56:55.96#ibcon#enter wrdev, iclass 38, count 2 2006.285.10:56:55.96#ibcon#first serial, iclass 38, count 2 2006.285.10:56:55.96#ibcon#enter sib2, iclass 38, count 2 2006.285.10:56:55.96#ibcon#flushed, iclass 38, count 2 2006.285.10:56:55.96#ibcon#about to write, iclass 38, count 2 2006.285.10:56:55.96#ibcon#wrote, iclass 38, count 2 2006.285.10:56:55.96#ibcon#about to read 3, iclass 38, count 2 2006.285.10:56:55.98#abcon#<5=/05 1.3 2.1 19.54 921014.9\r\n> 2006.285.10:56:55.98#ibcon#read 3, iclass 38, count 2 2006.285.10:56:55.98#ibcon#about to read 4, iclass 38, count 2 2006.285.10:56:55.98#ibcon#read 4, iclass 38, count 2 2006.285.10:56:55.98#ibcon#about to read 5, iclass 38, count 2 2006.285.10:56:55.98#ibcon#read 5, iclass 38, count 2 2006.285.10:56:55.98#ibcon#about to read 6, iclass 38, count 2 2006.285.10:56:55.98#ibcon#read 6, iclass 38, count 2 2006.285.10:56:55.98#ibcon#end of sib2, iclass 38, count 2 2006.285.10:56:55.98#ibcon#*mode == 0, iclass 38, count 2 2006.285.10:56:55.98#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.10:56:55.98#ibcon#[25=AT07-04\r\n] 2006.285.10:56:55.98#ibcon#*before write, iclass 38, count 2 2006.285.10:56:55.98#ibcon#enter sib2, iclass 38, count 2 2006.285.10:56:55.98#ibcon#flushed, iclass 38, count 2 2006.285.10:56:55.98#ibcon#about to write, iclass 38, count 2 2006.285.10:56:55.98#ibcon#wrote, iclass 38, count 2 2006.285.10:56:55.98#ibcon#about to read 3, iclass 38, count 2 2006.285.10:56:56.00#abcon#{5=INTERFACE CLEAR} 2006.285.10:56:56.01#ibcon#read 3, iclass 38, count 2 2006.285.10:56:56.01#ibcon#about to read 4, iclass 38, count 2 2006.285.10:56:56.01#ibcon#read 4, iclass 38, count 2 2006.285.10:56:56.01#ibcon#about to read 5, iclass 38, count 2 2006.285.10:56:56.01#ibcon#read 5, iclass 38, count 2 2006.285.10:56:56.01#ibcon#about to read 6, iclass 38, count 2 2006.285.10:56:56.01#ibcon#read 6, iclass 38, count 2 2006.285.10:56:56.01#ibcon#end of sib2, iclass 38, count 2 2006.285.10:56:56.01#ibcon#*after write, iclass 38, count 2 2006.285.10:56:56.01#ibcon#*before return 0, iclass 38, count 2 2006.285.10:56:56.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:56:56.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:56:56.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.10:56:56.01#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:56.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:56:56.06#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:56:56.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:56:56.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:56:56.13#ibcon#enter wrdev, iclass 38, count 0 2006.285.10:56:56.13#ibcon#first serial, iclass 38, count 0 2006.285.10:56:56.13#ibcon#enter sib2, iclass 38, count 0 2006.285.10:56:56.13#ibcon#flushed, iclass 38, count 0 2006.285.10:56:56.13#ibcon#about to write, iclass 38, count 0 2006.285.10:56:56.13#ibcon#wrote, iclass 38, count 0 2006.285.10:56:56.13#ibcon#about to read 3, iclass 38, count 0 2006.285.10:56:56.15#ibcon#read 3, iclass 38, count 0 2006.285.10:56:56.15#ibcon#about to read 4, iclass 38, count 0 2006.285.10:56:56.15#ibcon#read 4, iclass 38, count 0 2006.285.10:56:56.15#ibcon#about to read 5, iclass 38, count 0 2006.285.10:56:56.15#ibcon#read 5, iclass 38, count 0 2006.285.10:56:56.15#ibcon#about to read 6, iclass 38, count 0 2006.285.10:56:56.15#ibcon#read 6, iclass 38, count 0 2006.285.10:56:56.15#ibcon#end of sib2, iclass 38, count 0 2006.285.10:56:56.15#ibcon#*mode == 0, iclass 38, count 0 2006.285.10:56:56.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.10:56:56.15#ibcon#[25=USB\r\n] 2006.285.10:56:56.15#ibcon#*before write, iclass 38, count 0 2006.285.10:56:56.15#ibcon#enter sib2, iclass 38, count 0 2006.285.10:56:56.15#ibcon#flushed, iclass 38, count 0 2006.285.10:56:56.15#ibcon#about to write, iclass 38, count 0 2006.285.10:56:56.15#ibcon#wrote, iclass 38, count 0 2006.285.10:56:56.15#ibcon#about to read 3, iclass 38, count 0 2006.285.10:56:56.18#ibcon#read 3, iclass 38, count 0 2006.285.10:56:56.18#ibcon#about to read 4, iclass 38, count 0 2006.285.10:56:56.18#ibcon#read 4, iclass 38, count 0 2006.285.10:56:56.18#ibcon#about to read 5, iclass 38, count 0 2006.285.10:56:56.18#ibcon#read 5, iclass 38, count 0 2006.285.10:56:56.18#ibcon#about to read 6, iclass 38, count 0 2006.285.10:56:56.18#ibcon#read 6, iclass 38, count 0 2006.285.10:56:56.18#ibcon#end of sib2, iclass 38, count 0 2006.285.10:56:56.18#ibcon#*after write, iclass 38, count 0 2006.285.10:56:56.18#ibcon#*before return 0, iclass 38, count 0 2006.285.10:56:56.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:56:56.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:56:56.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.10:56:56.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.10:56:56.18$vck44/valo=8,884.99 2006.285.10:56:56.18#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.10:56:56.18#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.10:56:56.18#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:56.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:56:56.18#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:56:56.18#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:56:56.18#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:56:56.18#ibcon#first serial, iclass 6, count 0 2006.285.10:56:56.18#ibcon#enter sib2, iclass 6, count 0 2006.285.10:56:56.18#ibcon#flushed, iclass 6, count 0 2006.285.10:56:56.18#ibcon#about to write, iclass 6, count 0 2006.285.10:56:56.18#ibcon#wrote, iclass 6, count 0 2006.285.10:56:56.18#ibcon#about to read 3, iclass 6, count 0 2006.285.10:56:56.20#ibcon#read 3, iclass 6, count 0 2006.285.10:56:56.20#ibcon#about to read 4, iclass 6, count 0 2006.285.10:56:56.20#ibcon#read 4, iclass 6, count 0 2006.285.10:56:56.20#ibcon#about to read 5, iclass 6, count 0 2006.285.10:56:56.20#ibcon#read 5, iclass 6, count 0 2006.285.10:56:56.20#ibcon#about to read 6, iclass 6, count 0 2006.285.10:56:56.20#ibcon#read 6, iclass 6, count 0 2006.285.10:56:56.20#ibcon#end of sib2, iclass 6, count 0 2006.285.10:56:56.20#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:56:56.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:56:56.20#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.10:56:56.20#ibcon#*before write, iclass 6, count 0 2006.285.10:56:56.20#ibcon#enter sib2, iclass 6, count 0 2006.285.10:56:56.20#ibcon#flushed, iclass 6, count 0 2006.285.10:56:56.20#ibcon#about to write, iclass 6, count 0 2006.285.10:56:56.20#ibcon#wrote, iclass 6, count 0 2006.285.10:56:56.20#ibcon#about to read 3, iclass 6, count 0 2006.285.10:56:56.24#ibcon#read 3, iclass 6, count 0 2006.285.10:56:56.24#ibcon#about to read 4, iclass 6, count 0 2006.285.10:56:56.24#ibcon#read 4, iclass 6, count 0 2006.285.10:56:56.24#ibcon#about to read 5, iclass 6, count 0 2006.285.10:56:56.24#ibcon#read 5, iclass 6, count 0 2006.285.10:56:56.24#ibcon#about to read 6, iclass 6, count 0 2006.285.10:56:56.24#ibcon#read 6, iclass 6, count 0 2006.285.10:56:56.24#ibcon#end of sib2, iclass 6, count 0 2006.285.10:56:56.24#ibcon#*after write, iclass 6, count 0 2006.285.10:56:56.24#ibcon#*before return 0, iclass 6, count 0 2006.285.10:56:56.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:56:56.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:56:56.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:56:56.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:56:56.24$vck44/va=8,3 2006.285.10:56:56.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.10:56:56.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.10:56:56.24#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:56.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:56:56.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:56:56.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:56:56.30#ibcon#enter wrdev, iclass 10, count 2 2006.285.10:56:56.30#ibcon#first serial, iclass 10, count 2 2006.285.10:56:56.30#ibcon#enter sib2, iclass 10, count 2 2006.285.10:56:56.30#ibcon#flushed, iclass 10, count 2 2006.285.10:56:56.30#ibcon#about to write, iclass 10, count 2 2006.285.10:56:56.30#ibcon#wrote, iclass 10, count 2 2006.285.10:56:56.30#ibcon#about to read 3, iclass 10, count 2 2006.285.10:56:56.32#ibcon#read 3, iclass 10, count 2 2006.285.10:56:56.32#ibcon#about to read 4, iclass 10, count 2 2006.285.10:56:56.32#ibcon#read 4, iclass 10, count 2 2006.285.10:56:56.32#ibcon#about to read 5, iclass 10, count 2 2006.285.10:56:56.32#ibcon#read 5, iclass 10, count 2 2006.285.10:56:56.32#ibcon#about to read 6, iclass 10, count 2 2006.285.10:56:56.32#ibcon#read 6, iclass 10, count 2 2006.285.10:56:56.32#ibcon#end of sib2, iclass 10, count 2 2006.285.10:56:56.32#ibcon#*mode == 0, iclass 10, count 2 2006.285.10:56:56.32#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.10:56:56.32#ibcon#[25=AT08-03\r\n] 2006.285.10:56:56.32#ibcon#*before write, iclass 10, count 2 2006.285.10:56:56.32#ibcon#enter sib2, iclass 10, count 2 2006.285.10:56:56.32#ibcon#flushed, iclass 10, count 2 2006.285.10:56:56.32#ibcon#about to write, iclass 10, count 2 2006.285.10:56:56.32#ibcon#wrote, iclass 10, count 2 2006.285.10:56:56.32#ibcon#about to read 3, iclass 10, count 2 2006.285.10:56:56.35#ibcon#read 3, iclass 10, count 2 2006.285.10:56:56.35#ibcon#about to read 4, iclass 10, count 2 2006.285.10:56:56.35#ibcon#read 4, iclass 10, count 2 2006.285.10:56:56.35#ibcon#about to read 5, iclass 10, count 2 2006.285.10:56:56.35#ibcon#read 5, iclass 10, count 2 2006.285.10:56:56.35#ibcon#about to read 6, iclass 10, count 2 2006.285.10:56:56.35#ibcon#read 6, iclass 10, count 2 2006.285.10:56:56.35#ibcon#end of sib2, iclass 10, count 2 2006.285.10:56:56.35#ibcon#*after write, iclass 10, count 2 2006.285.10:56:56.35#ibcon#*before return 0, iclass 10, count 2 2006.285.10:56:56.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:56:56.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.10:56:56.35#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.10:56:56.35#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:56.35#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:56:56.47#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:56:56.47#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:56:56.47#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:56:56.47#ibcon#first serial, iclass 10, count 0 2006.285.10:56:56.47#ibcon#enter sib2, iclass 10, count 0 2006.285.10:56:56.47#ibcon#flushed, iclass 10, count 0 2006.285.10:56:56.47#ibcon#about to write, iclass 10, count 0 2006.285.10:56:56.47#ibcon#wrote, iclass 10, count 0 2006.285.10:56:56.47#ibcon#about to read 3, iclass 10, count 0 2006.285.10:56:56.49#ibcon#read 3, iclass 10, count 0 2006.285.10:56:56.49#ibcon#about to read 4, iclass 10, count 0 2006.285.10:56:56.49#ibcon#read 4, iclass 10, count 0 2006.285.10:56:56.49#ibcon#about to read 5, iclass 10, count 0 2006.285.10:56:56.49#ibcon#read 5, iclass 10, count 0 2006.285.10:56:56.49#ibcon#about to read 6, iclass 10, count 0 2006.285.10:56:56.49#ibcon#read 6, iclass 10, count 0 2006.285.10:56:56.49#ibcon#end of sib2, iclass 10, count 0 2006.285.10:56:56.49#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:56:56.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:56:56.49#ibcon#[25=USB\r\n] 2006.285.10:56:56.49#ibcon#*before write, iclass 10, count 0 2006.285.10:56:56.49#ibcon#enter sib2, iclass 10, count 0 2006.285.10:56:56.49#ibcon#flushed, iclass 10, count 0 2006.285.10:56:56.49#ibcon#about to write, iclass 10, count 0 2006.285.10:56:56.49#ibcon#wrote, iclass 10, count 0 2006.285.10:56:56.49#ibcon#about to read 3, iclass 10, count 0 2006.285.10:56:56.52#ibcon#read 3, iclass 10, count 0 2006.285.10:56:56.52#ibcon#about to read 4, iclass 10, count 0 2006.285.10:56:56.52#ibcon#read 4, iclass 10, count 0 2006.285.10:56:56.52#ibcon#about to read 5, iclass 10, count 0 2006.285.10:56:56.52#ibcon#read 5, iclass 10, count 0 2006.285.10:56:56.52#ibcon#about to read 6, iclass 10, count 0 2006.285.10:56:56.52#ibcon#read 6, iclass 10, count 0 2006.285.10:56:56.52#ibcon#end of sib2, iclass 10, count 0 2006.285.10:56:56.52#ibcon#*after write, iclass 10, count 0 2006.285.10:56:56.52#ibcon#*before return 0, iclass 10, count 0 2006.285.10:56:56.52#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:56:56.52#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.10:56:56.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:56:56.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:56:56.52$vck44/vblo=1,629.99 2006.285.10:56:56.52#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.10:56:56.52#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.10:56:56.52#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:56.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:56:56.52#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:56:56.52#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:56:56.52#ibcon#enter wrdev, iclass 12, count 0 2006.285.10:56:56.52#ibcon#first serial, iclass 12, count 0 2006.285.10:56:56.52#ibcon#enter sib2, iclass 12, count 0 2006.285.10:56:56.52#ibcon#flushed, iclass 12, count 0 2006.285.10:56:56.52#ibcon#about to write, iclass 12, count 0 2006.285.10:56:56.52#ibcon#wrote, iclass 12, count 0 2006.285.10:56:56.52#ibcon#about to read 3, iclass 12, count 0 2006.285.10:56:56.54#ibcon#read 3, iclass 12, count 0 2006.285.10:56:56.54#ibcon#about to read 4, iclass 12, count 0 2006.285.10:56:56.54#ibcon#read 4, iclass 12, count 0 2006.285.10:56:56.54#ibcon#about to read 5, iclass 12, count 0 2006.285.10:56:56.54#ibcon#read 5, iclass 12, count 0 2006.285.10:56:56.54#ibcon#about to read 6, iclass 12, count 0 2006.285.10:56:56.54#ibcon#read 6, iclass 12, count 0 2006.285.10:56:56.54#ibcon#end of sib2, iclass 12, count 0 2006.285.10:56:56.54#ibcon#*mode == 0, iclass 12, count 0 2006.285.10:56:56.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.10:56:56.54#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.10:56:56.54#ibcon#*before write, iclass 12, count 0 2006.285.10:56:56.54#ibcon#enter sib2, iclass 12, count 0 2006.285.10:56:56.54#ibcon#flushed, iclass 12, count 0 2006.285.10:56:56.54#ibcon#about to write, iclass 12, count 0 2006.285.10:56:56.54#ibcon#wrote, iclass 12, count 0 2006.285.10:56:56.54#ibcon#about to read 3, iclass 12, count 0 2006.285.10:56:56.58#ibcon#read 3, iclass 12, count 0 2006.285.10:56:56.58#ibcon#about to read 4, iclass 12, count 0 2006.285.10:56:56.58#ibcon#read 4, iclass 12, count 0 2006.285.10:56:56.58#ibcon#about to read 5, iclass 12, count 0 2006.285.10:56:56.58#ibcon#read 5, iclass 12, count 0 2006.285.10:56:56.58#ibcon#about to read 6, iclass 12, count 0 2006.285.10:56:56.58#ibcon#read 6, iclass 12, count 0 2006.285.10:56:56.58#ibcon#end of sib2, iclass 12, count 0 2006.285.10:56:56.58#ibcon#*after write, iclass 12, count 0 2006.285.10:56:56.58#ibcon#*before return 0, iclass 12, count 0 2006.285.10:56:56.58#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:56:56.58#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.10:56:56.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.10:56:56.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.10:56:56.58$vck44/vb=1,4 2006.285.10:56:56.58#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.10:56:56.58#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.10:56:56.58#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:56.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:56:56.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:56:56.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:56:56.58#ibcon#enter wrdev, iclass 14, count 2 2006.285.10:56:56.58#ibcon#first serial, iclass 14, count 2 2006.285.10:56:56.58#ibcon#enter sib2, iclass 14, count 2 2006.285.10:56:56.58#ibcon#flushed, iclass 14, count 2 2006.285.10:56:56.58#ibcon#about to write, iclass 14, count 2 2006.285.10:56:56.58#ibcon#wrote, iclass 14, count 2 2006.285.10:56:56.58#ibcon#about to read 3, iclass 14, count 2 2006.285.10:56:56.60#ibcon#read 3, iclass 14, count 2 2006.285.10:56:56.60#ibcon#about to read 4, iclass 14, count 2 2006.285.10:56:56.60#ibcon#read 4, iclass 14, count 2 2006.285.10:56:56.60#ibcon#about to read 5, iclass 14, count 2 2006.285.10:56:56.60#ibcon#read 5, iclass 14, count 2 2006.285.10:56:56.60#ibcon#about to read 6, iclass 14, count 2 2006.285.10:56:56.60#ibcon#read 6, iclass 14, count 2 2006.285.10:56:56.60#ibcon#end of sib2, iclass 14, count 2 2006.285.10:56:56.60#ibcon#*mode == 0, iclass 14, count 2 2006.285.10:56:56.60#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.10:56:56.60#ibcon#[27=AT01-04\r\n] 2006.285.10:56:56.60#ibcon#*before write, iclass 14, count 2 2006.285.10:56:56.60#ibcon#enter sib2, iclass 14, count 2 2006.285.10:56:56.60#ibcon#flushed, iclass 14, count 2 2006.285.10:56:56.60#ibcon#about to write, iclass 14, count 2 2006.285.10:56:56.60#ibcon#wrote, iclass 14, count 2 2006.285.10:56:56.60#ibcon#about to read 3, iclass 14, count 2 2006.285.10:56:56.63#ibcon#read 3, iclass 14, count 2 2006.285.10:56:56.63#ibcon#about to read 4, iclass 14, count 2 2006.285.10:56:56.63#ibcon#read 4, iclass 14, count 2 2006.285.10:56:56.63#ibcon#about to read 5, iclass 14, count 2 2006.285.10:56:56.63#ibcon#read 5, iclass 14, count 2 2006.285.10:56:56.63#ibcon#about to read 6, iclass 14, count 2 2006.285.10:56:56.63#ibcon#read 6, iclass 14, count 2 2006.285.10:56:56.63#ibcon#end of sib2, iclass 14, count 2 2006.285.10:56:56.63#ibcon#*after write, iclass 14, count 2 2006.285.10:56:56.63#ibcon#*before return 0, iclass 14, count 2 2006.285.10:56:56.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:56:56.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.10:56:56.63#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.10:56:56.63#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:56.63#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:56:56.75#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:56:56.75#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:56:56.75#ibcon#enter wrdev, iclass 14, count 0 2006.285.10:56:56.75#ibcon#first serial, iclass 14, count 0 2006.285.10:56:56.75#ibcon#enter sib2, iclass 14, count 0 2006.285.10:56:56.75#ibcon#flushed, iclass 14, count 0 2006.285.10:56:56.75#ibcon#about to write, iclass 14, count 0 2006.285.10:56:56.75#ibcon#wrote, iclass 14, count 0 2006.285.10:56:56.75#ibcon#about to read 3, iclass 14, count 0 2006.285.10:56:56.77#ibcon#read 3, iclass 14, count 0 2006.285.10:56:56.77#ibcon#about to read 4, iclass 14, count 0 2006.285.10:56:56.77#ibcon#read 4, iclass 14, count 0 2006.285.10:56:56.77#ibcon#about to read 5, iclass 14, count 0 2006.285.10:56:56.77#ibcon#read 5, iclass 14, count 0 2006.285.10:56:56.77#ibcon#about to read 6, iclass 14, count 0 2006.285.10:56:56.77#ibcon#read 6, iclass 14, count 0 2006.285.10:56:56.77#ibcon#end of sib2, iclass 14, count 0 2006.285.10:56:56.77#ibcon#*mode == 0, iclass 14, count 0 2006.285.10:56:56.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.10:56:56.77#ibcon#[27=USB\r\n] 2006.285.10:56:56.77#ibcon#*before write, iclass 14, count 0 2006.285.10:56:56.77#ibcon#enter sib2, iclass 14, count 0 2006.285.10:56:56.77#ibcon#flushed, iclass 14, count 0 2006.285.10:56:56.77#ibcon#about to write, iclass 14, count 0 2006.285.10:56:56.77#ibcon#wrote, iclass 14, count 0 2006.285.10:56:56.77#ibcon#about to read 3, iclass 14, count 0 2006.285.10:56:56.80#ibcon#read 3, iclass 14, count 0 2006.285.10:56:56.80#ibcon#about to read 4, iclass 14, count 0 2006.285.10:56:56.80#ibcon#read 4, iclass 14, count 0 2006.285.10:56:56.80#ibcon#about to read 5, iclass 14, count 0 2006.285.10:56:56.80#ibcon#read 5, iclass 14, count 0 2006.285.10:56:56.80#ibcon#about to read 6, iclass 14, count 0 2006.285.10:56:56.80#ibcon#read 6, iclass 14, count 0 2006.285.10:56:56.80#ibcon#end of sib2, iclass 14, count 0 2006.285.10:56:56.80#ibcon#*after write, iclass 14, count 0 2006.285.10:56:56.80#ibcon#*before return 0, iclass 14, count 0 2006.285.10:56:56.80#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:56:56.80#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.10:56:56.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.10:56:56.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.10:56:56.80$vck44/vblo=2,634.99 2006.285.10:56:56.80#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.10:56:56.80#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.10:56:56.80#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:56.80#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:56:56.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:56:56.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:56:56.80#ibcon#enter wrdev, iclass 16, count 0 2006.285.10:56:56.80#ibcon#first serial, iclass 16, count 0 2006.285.10:56:56.80#ibcon#enter sib2, iclass 16, count 0 2006.285.10:56:56.80#ibcon#flushed, iclass 16, count 0 2006.285.10:56:56.80#ibcon#about to write, iclass 16, count 0 2006.285.10:56:56.80#ibcon#wrote, iclass 16, count 0 2006.285.10:56:56.80#ibcon#about to read 3, iclass 16, count 0 2006.285.10:56:56.82#ibcon#read 3, iclass 16, count 0 2006.285.10:56:56.82#ibcon#about to read 4, iclass 16, count 0 2006.285.10:56:56.82#ibcon#read 4, iclass 16, count 0 2006.285.10:56:56.82#ibcon#about to read 5, iclass 16, count 0 2006.285.10:56:56.82#ibcon#read 5, iclass 16, count 0 2006.285.10:56:56.82#ibcon#about to read 6, iclass 16, count 0 2006.285.10:56:56.82#ibcon#read 6, iclass 16, count 0 2006.285.10:56:56.82#ibcon#end of sib2, iclass 16, count 0 2006.285.10:56:56.82#ibcon#*mode == 0, iclass 16, count 0 2006.285.10:56:56.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.10:56:56.82#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.10:56:56.82#ibcon#*before write, iclass 16, count 0 2006.285.10:56:56.82#ibcon#enter sib2, iclass 16, count 0 2006.285.10:56:56.82#ibcon#flushed, iclass 16, count 0 2006.285.10:56:56.82#ibcon#about to write, iclass 16, count 0 2006.285.10:56:56.82#ibcon#wrote, iclass 16, count 0 2006.285.10:56:56.82#ibcon#about to read 3, iclass 16, count 0 2006.285.10:56:56.86#ibcon#read 3, iclass 16, count 0 2006.285.10:56:56.86#ibcon#about to read 4, iclass 16, count 0 2006.285.10:56:56.86#ibcon#read 4, iclass 16, count 0 2006.285.10:56:56.86#ibcon#about to read 5, iclass 16, count 0 2006.285.10:56:56.86#ibcon#read 5, iclass 16, count 0 2006.285.10:56:56.86#ibcon#about to read 6, iclass 16, count 0 2006.285.10:56:56.86#ibcon#read 6, iclass 16, count 0 2006.285.10:56:56.86#ibcon#end of sib2, iclass 16, count 0 2006.285.10:56:56.86#ibcon#*after write, iclass 16, count 0 2006.285.10:56:56.86#ibcon#*before return 0, iclass 16, count 0 2006.285.10:56:56.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:56:56.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.10:56:56.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.10:56:56.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.10:56:56.86$vck44/vb=2,5 2006.285.10:56:56.86#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.10:56:56.86#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.10:56:56.86#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:56.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:56:56.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:56:56.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:56:56.92#ibcon#enter wrdev, iclass 18, count 2 2006.285.10:56:56.92#ibcon#first serial, iclass 18, count 2 2006.285.10:56:56.92#ibcon#enter sib2, iclass 18, count 2 2006.285.10:56:56.92#ibcon#flushed, iclass 18, count 2 2006.285.10:56:56.92#ibcon#about to write, iclass 18, count 2 2006.285.10:56:56.92#ibcon#wrote, iclass 18, count 2 2006.285.10:56:56.92#ibcon#about to read 3, iclass 18, count 2 2006.285.10:56:56.94#ibcon#read 3, iclass 18, count 2 2006.285.10:56:56.94#ibcon#about to read 4, iclass 18, count 2 2006.285.10:56:56.94#ibcon#read 4, iclass 18, count 2 2006.285.10:56:56.94#ibcon#about to read 5, iclass 18, count 2 2006.285.10:56:56.94#ibcon#read 5, iclass 18, count 2 2006.285.10:56:56.94#ibcon#about to read 6, iclass 18, count 2 2006.285.10:56:56.94#ibcon#read 6, iclass 18, count 2 2006.285.10:56:56.94#ibcon#end of sib2, iclass 18, count 2 2006.285.10:56:56.94#ibcon#*mode == 0, iclass 18, count 2 2006.285.10:56:56.94#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.10:56:56.94#ibcon#[27=AT02-05\r\n] 2006.285.10:56:56.94#ibcon#*before write, iclass 18, count 2 2006.285.10:56:56.94#ibcon#enter sib2, iclass 18, count 2 2006.285.10:56:56.94#ibcon#flushed, iclass 18, count 2 2006.285.10:56:56.94#ibcon#about to write, iclass 18, count 2 2006.285.10:56:56.94#ibcon#wrote, iclass 18, count 2 2006.285.10:56:56.94#ibcon#about to read 3, iclass 18, count 2 2006.285.10:56:56.97#ibcon#read 3, iclass 18, count 2 2006.285.10:56:56.97#ibcon#about to read 4, iclass 18, count 2 2006.285.10:56:56.97#ibcon#read 4, iclass 18, count 2 2006.285.10:56:56.97#ibcon#about to read 5, iclass 18, count 2 2006.285.10:56:56.97#ibcon#read 5, iclass 18, count 2 2006.285.10:56:56.97#ibcon#about to read 6, iclass 18, count 2 2006.285.10:56:56.97#ibcon#read 6, iclass 18, count 2 2006.285.10:56:56.97#ibcon#end of sib2, iclass 18, count 2 2006.285.10:56:56.97#ibcon#*after write, iclass 18, count 2 2006.285.10:56:56.97#ibcon#*before return 0, iclass 18, count 2 2006.285.10:56:56.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:56:56.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.10:56:56.97#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.10:56:56.97#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:56.97#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:56:57.09#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:56:57.09#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:56:57.09#ibcon#enter wrdev, iclass 18, count 0 2006.285.10:56:57.09#ibcon#first serial, iclass 18, count 0 2006.285.10:56:57.09#ibcon#enter sib2, iclass 18, count 0 2006.285.10:56:57.09#ibcon#flushed, iclass 18, count 0 2006.285.10:56:57.09#ibcon#about to write, iclass 18, count 0 2006.285.10:56:57.09#ibcon#wrote, iclass 18, count 0 2006.285.10:56:57.09#ibcon#about to read 3, iclass 18, count 0 2006.285.10:56:57.11#ibcon#read 3, iclass 18, count 0 2006.285.10:56:57.11#ibcon#about to read 4, iclass 18, count 0 2006.285.10:56:57.11#ibcon#read 4, iclass 18, count 0 2006.285.10:56:57.11#ibcon#about to read 5, iclass 18, count 0 2006.285.10:56:57.11#ibcon#read 5, iclass 18, count 0 2006.285.10:56:57.11#ibcon#about to read 6, iclass 18, count 0 2006.285.10:56:57.11#ibcon#read 6, iclass 18, count 0 2006.285.10:56:57.11#ibcon#end of sib2, iclass 18, count 0 2006.285.10:56:57.11#ibcon#*mode == 0, iclass 18, count 0 2006.285.10:56:57.11#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.10:56:57.11#ibcon#[27=USB\r\n] 2006.285.10:56:57.11#ibcon#*before write, iclass 18, count 0 2006.285.10:56:57.11#ibcon#enter sib2, iclass 18, count 0 2006.285.10:56:57.11#ibcon#flushed, iclass 18, count 0 2006.285.10:56:57.11#ibcon#about to write, iclass 18, count 0 2006.285.10:56:57.11#ibcon#wrote, iclass 18, count 0 2006.285.10:56:57.11#ibcon#about to read 3, iclass 18, count 0 2006.285.10:56:57.14#ibcon#read 3, iclass 18, count 0 2006.285.10:56:57.14#ibcon#about to read 4, iclass 18, count 0 2006.285.10:56:57.14#ibcon#read 4, iclass 18, count 0 2006.285.10:56:57.14#ibcon#about to read 5, iclass 18, count 0 2006.285.10:56:57.14#ibcon#read 5, iclass 18, count 0 2006.285.10:56:57.14#ibcon#about to read 6, iclass 18, count 0 2006.285.10:56:57.14#ibcon#read 6, iclass 18, count 0 2006.285.10:56:57.14#ibcon#end of sib2, iclass 18, count 0 2006.285.10:56:57.14#ibcon#*after write, iclass 18, count 0 2006.285.10:56:57.14#ibcon#*before return 0, iclass 18, count 0 2006.285.10:56:57.14#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:56:57.14#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.10:56:57.14#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.10:56:57.14#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.10:56:57.14$vck44/vblo=3,649.99 2006.285.10:56:57.14#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.10:56:57.14#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.10:56:57.14#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:57.14#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:56:57.14#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:56:57.14#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:56:57.14#ibcon#enter wrdev, iclass 20, count 0 2006.285.10:56:57.14#ibcon#first serial, iclass 20, count 0 2006.285.10:56:57.14#ibcon#enter sib2, iclass 20, count 0 2006.285.10:56:57.14#ibcon#flushed, iclass 20, count 0 2006.285.10:56:57.14#ibcon#about to write, iclass 20, count 0 2006.285.10:56:57.14#ibcon#wrote, iclass 20, count 0 2006.285.10:56:57.14#ibcon#about to read 3, iclass 20, count 0 2006.285.10:56:57.16#ibcon#read 3, iclass 20, count 0 2006.285.10:56:57.16#ibcon#about to read 4, iclass 20, count 0 2006.285.10:56:57.16#ibcon#read 4, iclass 20, count 0 2006.285.10:56:57.16#ibcon#about to read 5, iclass 20, count 0 2006.285.10:56:57.16#ibcon#read 5, iclass 20, count 0 2006.285.10:56:57.16#ibcon#about to read 6, iclass 20, count 0 2006.285.10:56:57.16#ibcon#read 6, iclass 20, count 0 2006.285.10:56:57.16#ibcon#end of sib2, iclass 20, count 0 2006.285.10:56:57.16#ibcon#*mode == 0, iclass 20, count 0 2006.285.10:56:57.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.10:56:57.16#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.10:56:57.16#ibcon#*before write, iclass 20, count 0 2006.285.10:56:57.16#ibcon#enter sib2, iclass 20, count 0 2006.285.10:56:57.16#ibcon#flushed, iclass 20, count 0 2006.285.10:56:57.16#ibcon#about to write, iclass 20, count 0 2006.285.10:56:57.16#ibcon#wrote, iclass 20, count 0 2006.285.10:56:57.16#ibcon#about to read 3, iclass 20, count 0 2006.285.10:56:57.20#ibcon#read 3, iclass 20, count 0 2006.285.10:56:57.20#ibcon#about to read 4, iclass 20, count 0 2006.285.10:56:57.20#ibcon#read 4, iclass 20, count 0 2006.285.10:56:57.20#ibcon#about to read 5, iclass 20, count 0 2006.285.10:56:57.20#ibcon#read 5, iclass 20, count 0 2006.285.10:56:57.20#ibcon#about to read 6, iclass 20, count 0 2006.285.10:56:57.20#ibcon#read 6, iclass 20, count 0 2006.285.10:56:57.20#ibcon#end of sib2, iclass 20, count 0 2006.285.10:56:57.20#ibcon#*after write, iclass 20, count 0 2006.285.10:56:57.20#ibcon#*before return 0, iclass 20, count 0 2006.285.10:56:57.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:56:57.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.10:56:57.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.10:56:57.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.10:56:57.20$vck44/vb=3,4 2006.285.10:56:57.20#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.10:56:57.20#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.10:56:57.20#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:57.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:56:57.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:56:57.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:56:57.26#ibcon#enter wrdev, iclass 22, count 2 2006.285.10:56:57.26#ibcon#first serial, iclass 22, count 2 2006.285.10:56:57.26#ibcon#enter sib2, iclass 22, count 2 2006.285.10:56:57.26#ibcon#flushed, iclass 22, count 2 2006.285.10:56:57.26#ibcon#about to write, iclass 22, count 2 2006.285.10:56:57.26#ibcon#wrote, iclass 22, count 2 2006.285.10:56:57.26#ibcon#about to read 3, iclass 22, count 2 2006.285.10:56:57.28#ibcon#read 3, iclass 22, count 2 2006.285.10:56:57.28#ibcon#about to read 4, iclass 22, count 2 2006.285.10:56:57.28#ibcon#read 4, iclass 22, count 2 2006.285.10:56:57.28#ibcon#about to read 5, iclass 22, count 2 2006.285.10:56:57.28#ibcon#read 5, iclass 22, count 2 2006.285.10:56:57.28#ibcon#about to read 6, iclass 22, count 2 2006.285.10:56:57.28#ibcon#read 6, iclass 22, count 2 2006.285.10:56:57.28#ibcon#end of sib2, iclass 22, count 2 2006.285.10:56:57.28#ibcon#*mode == 0, iclass 22, count 2 2006.285.10:56:57.28#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.10:56:57.28#ibcon#[27=AT03-04\r\n] 2006.285.10:56:57.28#ibcon#*before write, iclass 22, count 2 2006.285.10:56:57.28#ibcon#enter sib2, iclass 22, count 2 2006.285.10:56:57.28#ibcon#flushed, iclass 22, count 2 2006.285.10:56:57.28#ibcon#about to write, iclass 22, count 2 2006.285.10:56:57.28#ibcon#wrote, iclass 22, count 2 2006.285.10:56:57.28#ibcon#about to read 3, iclass 22, count 2 2006.285.10:56:57.31#ibcon#read 3, iclass 22, count 2 2006.285.10:56:57.31#ibcon#about to read 4, iclass 22, count 2 2006.285.10:56:57.31#ibcon#read 4, iclass 22, count 2 2006.285.10:56:57.31#ibcon#about to read 5, iclass 22, count 2 2006.285.10:56:57.31#ibcon#read 5, iclass 22, count 2 2006.285.10:56:57.31#ibcon#about to read 6, iclass 22, count 2 2006.285.10:56:57.31#ibcon#read 6, iclass 22, count 2 2006.285.10:56:57.31#ibcon#end of sib2, iclass 22, count 2 2006.285.10:56:57.31#ibcon#*after write, iclass 22, count 2 2006.285.10:56:57.31#ibcon#*before return 0, iclass 22, count 2 2006.285.10:56:57.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:56:57.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.10:56:57.31#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.10:56:57.31#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:57.31#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:56:57.43#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:56:57.43#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:56:57.43#ibcon#enter wrdev, iclass 22, count 0 2006.285.10:56:57.43#ibcon#first serial, iclass 22, count 0 2006.285.10:56:57.43#ibcon#enter sib2, iclass 22, count 0 2006.285.10:56:57.43#ibcon#flushed, iclass 22, count 0 2006.285.10:56:57.43#ibcon#about to write, iclass 22, count 0 2006.285.10:56:57.43#ibcon#wrote, iclass 22, count 0 2006.285.10:56:57.43#ibcon#about to read 3, iclass 22, count 0 2006.285.10:56:57.45#ibcon#read 3, iclass 22, count 0 2006.285.10:56:57.45#ibcon#about to read 4, iclass 22, count 0 2006.285.10:56:57.45#ibcon#read 4, iclass 22, count 0 2006.285.10:56:57.45#ibcon#about to read 5, iclass 22, count 0 2006.285.10:56:57.45#ibcon#read 5, iclass 22, count 0 2006.285.10:56:57.45#ibcon#about to read 6, iclass 22, count 0 2006.285.10:56:57.45#ibcon#read 6, iclass 22, count 0 2006.285.10:56:57.45#ibcon#end of sib2, iclass 22, count 0 2006.285.10:56:57.45#ibcon#*mode == 0, iclass 22, count 0 2006.285.10:56:57.45#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.10:56:57.45#ibcon#[27=USB\r\n] 2006.285.10:56:57.45#ibcon#*before write, iclass 22, count 0 2006.285.10:56:57.45#ibcon#enter sib2, iclass 22, count 0 2006.285.10:56:57.45#ibcon#flushed, iclass 22, count 0 2006.285.10:56:57.45#ibcon#about to write, iclass 22, count 0 2006.285.10:56:57.45#ibcon#wrote, iclass 22, count 0 2006.285.10:56:57.45#ibcon#about to read 3, iclass 22, count 0 2006.285.10:56:57.48#ibcon#read 3, iclass 22, count 0 2006.285.10:56:57.48#ibcon#about to read 4, iclass 22, count 0 2006.285.10:56:57.48#ibcon#read 4, iclass 22, count 0 2006.285.10:56:57.48#ibcon#about to read 5, iclass 22, count 0 2006.285.10:56:57.48#ibcon#read 5, iclass 22, count 0 2006.285.10:56:57.48#ibcon#about to read 6, iclass 22, count 0 2006.285.10:56:57.48#ibcon#read 6, iclass 22, count 0 2006.285.10:56:57.48#ibcon#end of sib2, iclass 22, count 0 2006.285.10:56:57.48#ibcon#*after write, iclass 22, count 0 2006.285.10:56:57.48#ibcon#*before return 0, iclass 22, count 0 2006.285.10:56:57.48#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:56:57.48#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.10:56:57.48#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.10:56:57.48#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.10:56:57.48$vck44/vblo=4,679.99 2006.285.10:56:57.48#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.10:56:57.48#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.10:56:57.48#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:57.48#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:56:57.48#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:56:57.48#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:56:57.48#ibcon#enter wrdev, iclass 24, count 0 2006.285.10:56:57.48#ibcon#first serial, iclass 24, count 0 2006.285.10:56:57.48#ibcon#enter sib2, iclass 24, count 0 2006.285.10:56:57.48#ibcon#flushed, iclass 24, count 0 2006.285.10:56:57.48#ibcon#about to write, iclass 24, count 0 2006.285.10:56:57.48#ibcon#wrote, iclass 24, count 0 2006.285.10:56:57.48#ibcon#about to read 3, iclass 24, count 0 2006.285.10:56:57.50#ibcon#read 3, iclass 24, count 0 2006.285.10:56:57.50#ibcon#about to read 4, iclass 24, count 0 2006.285.10:56:57.50#ibcon#read 4, iclass 24, count 0 2006.285.10:56:57.50#ibcon#about to read 5, iclass 24, count 0 2006.285.10:56:57.50#ibcon#read 5, iclass 24, count 0 2006.285.10:56:57.50#ibcon#about to read 6, iclass 24, count 0 2006.285.10:56:57.50#ibcon#read 6, iclass 24, count 0 2006.285.10:56:57.50#ibcon#end of sib2, iclass 24, count 0 2006.285.10:56:57.50#ibcon#*mode == 0, iclass 24, count 0 2006.285.10:56:57.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.10:56:57.50#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.10:56:57.50#ibcon#*before write, iclass 24, count 0 2006.285.10:56:57.50#ibcon#enter sib2, iclass 24, count 0 2006.285.10:56:57.50#ibcon#flushed, iclass 24, count 0 2006.285.10:56:57.50#ibcon#about to write, iclass 24, count 0 2006.285.10:56:57.50#ibcon#wrote, iclass 24, count 0 2006.285.10:56:57.50#ibcon#about to read 3, iclass 24, count 0 2006.285.10:56:57.54#ibcon#read 3, iclass 24, count 0 2006.285.10:56:57.54#ibcon#about to read 4, iclass 24, count 0 2006.285.10:56:57.54#ibcon#read 4, iclass 24, count 0 2006.285.10:56:57.54#ibcon#about to read 5, iclass 24, count 0 2006.285.10:56:57.54#ibcon#read 5, iclass 24, count 0 2006.285.10:56:57.54#ibcon#about to read 6, iclass 24, count 0 2006.285.10:56:57.54#ibcon#read 6, iclass 24, count 0 2006.285.10:56:57.54#ibcon#end of sib2, iclass 24, count 0 2006.285.10:56:57.54#ibcon#*after write, iclass 24, count 0 2006.285.10:56:57.54#ibcon#*before return 0, iclass 24, count 0 2006.285.10:56:57.54#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:56:57.54#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.10:56:57.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.10:56:57.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.10:56:57.54$vck44/vb=4,5 2006.285.10:56:57.54#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.10:56:57.54#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.10:56:57.54#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:57.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:56:57.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:56:57.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:56:57.60#ibcon#enter wrdev, iclass 26, count 2 2006.285.10:56:57.60#ibcon#first serial, iclass 26, count 2 2006.285.10:56:57.60#ibcon#enter sib2, iclass 26, count 2 2006.285.10:56:57.60#ibcon#flushed, iclass 26, count 2 2006.285.10:56:57.60#ibcon#about to write, iclass 26, count 2 2006.285.10:56:57.60#ibcon#wrote, iclass 26, count 2 2006.285.10:56:57.60#ibcon#about to read 3, iclass 26, count 2 2006.285.10:56:57.62#ibcon#read 3, iclass 26, count 2 2006.285.10:56:57.62#ibcon#about to read 4, iclass 26, count 2 2006.285.10:56:57.62#ibcon#read 4, iclass 26, count 2 2006.285.10:56:57.62#ibcon#about to read 5, iclass 26, count 2 2006.285.10:56:57.62#ibcon#read 5, iclass 26, count 2 2006.285.10:56:57.62#ibcon#about to read 6, iclass 26, count 2 2006.285.10:56:57.62#ibcon#read 6, iclass 26, count 2 2006.285.10:56:57.62#ibcon#end of sib2, iclass 26, count 2 2006.285.10:56:57.62#ibcon#*mode == 0, iclass 26, count 2 2006.285.10:56:57.62#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.10:56:57.62#ibcon#[27=AT04-05\r\n] 2006.285.10:56:57.62#ibcon#*before write, iclass 26, count 2 2006.285.10:56:57.62#ibcon#enter sib2, iclass 26, count 2 2006.285.10:56:57.62#ibcon#flushed, iclass 26, count 2 2006.285.10:56:57.62#ibcon#about to write, iclass 26, count 2 2006.285.10:56:57.62#ibcon#wrote, iclass 26, count 2 2006.285.10:56:57.62#ibcon#about to read 3, iclass 26, count 2 2006.285.10:56:57.65#ibcon#read 3, iclass 26, count 2 2006.285.10:56:57.65#ibcon#about to read 4, iclass 26, count 2 2006.285.10:56:57.65#ibcon#read 4, iclass 26, count 2 2006.285.10:56:57.65#ibcon#about to read 5, iclass 26, count 2 2006.285.10:56:57.65#ibcon#read 5, iclass 26, count 2 2006.285.10:56:57.65#ibcon#about to read 6, iclass 26, count 2 2006.285.10:56:57.65#ibcon#read 6, iclass 26, count 2 2006.285.10:56:57.65#ibcon#end of sib2, iclass 26, count 2 2006.285.10:56:57.65#ibcon#*after write, iclass 26, count 2 2006.285.10:56:57.65#ibcon#*before return 0, iclass 26, count 2 2006.285.10:56:57.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:56:57.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.10:56:57.65#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.10:56:57.65#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:57.65#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:56:57.77#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:56:57.77#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:56:57.77#ibcon#enter wrdev, iclass 26, count 0 2006.285.10:56:57.77#ibcon#first serial, iclass 26, count 0 2006.285.10:56:57.77#ibcon#enter sib2, iclass 26, count 0 2006.285.10:56:57.77#ibcon#flushed, iclass 26, count 0 2006.285.10:56:57.77#ibcon#about to write, iclass 26, count 0 2006.285.10:56:57.77#ibcon#wrote, iclass 26, count 0 2006.285.10:56:57.77#ibcon#about to read 3, iclass 26, count 0 2006.285.10:56:57.79#ibcon#read 3, iclass 26, count 0 2006.285.10:56:57.79#ibcon#about to read 4, iclass 26, count 0 2006.285.10:56:57.79#ibcon#read 4, iclass 26, count 0 2006.285.10:56:57.79#ibcon#about to read 5, iclass 26, count 0 2006.285.10:56:57.79#ibcon#read 5, iclass 26, count 0 2006.285.10:56:57.79#ibcon#about to read 6, iclass 26, count 0 2006.285.10:56:57.79#ibcon#read 6, iclass 26, count 0 2006.285.10:56:57.79#ibcon#end of sib2, iclass 26, count 0 2006.285.10:56:57.79#ibcon#*mode == 0, iclass 26, count 0 2006.285.10:56:57.79#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.10:56:57.79#ibcon#[27=USB\r\n] 2006.285.10:56:57.79#ibcon#*before write, iclass 26, count 0 2006.285.10:56:57.79#ibcon#enter sib2, iclass 26, count 0 2006.285.10:56:57.79#ibcon#flushed, iclass 26, count 0 2006.285.10:56:57.79#ibcon#about to write, iclass 26, count 0 2006.285.10:56:57.79#ibcon#wrote, iclass 26, count 0 2006.285.10:56:57.79#ibcon#about to read 3, iclass 26, count 0 2006.285.10:56:57.82#ibcon#read 3, iclass 26, count 0 2006.285.10:56:57.82#ibcon#about to read 4, iclass 26, count 0 2006.285.10:56:57.82#ibcon#read 4, iclass 26, count 0 2006.285.10:56:57.82#ibcon#about to read 5, iclass 26, count 0 2006.285.10:56:57.82#ibcon#read 5, iclass 26, count 0 2006.285.10:56:57.82#ibcon#about to read 6, iclass 26, count 0 2006.285.10:56:57.82#ibcon#read 6, iclass 26, count 0 2006.285.10:56:57.82#ibcon#end of sib2, iclass 26, count 0 2006.285.10:56:57.82#ibcon#*after write, iclass 26, count 0 2006.285.10:56:57.82#ibcon#*before return 0, iclass 26, count 0 2006.285.10:56:57.82#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:56:57.82#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.10:56:57.82#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.10:56:57.82#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.10:56:57.82$vck44/vblo=5,709.99 2006.285.10:56:57.82#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.10:56:57.82#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.10:56:57.82#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:57.82#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:56:57.82#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:56:57.82#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:56:57.82#ibcon#enter wrdev, iclass 28, count 0 2006.285.10:56:57.82#ibcon#first serial, iclass 28, count 0 2006.285.10:56:57.82#ibcon#enter sib2, iclass 28, count 0 2006.285.10:56:57.82#ibcon#flushed, iclass 28, count 0 2006.285.10:56:57.82#ibcon#about to write, iclass 28, count 0 2006.285.10:56:57.82#ibcon#wrote, iclass 28, count 0 2006.285.10:56:57.82#ibcon#about to read 3, iclass 28, count 0 2006.285.10:56:57.84#ibcon#read 3, iclass 28, count 0 2006.285.10:56:57.84#ibcon#about to read 4, iclass 28, count 0 2006.285.10:56:57.84#ibcon#read 4, iclass 28, count 0 2006.285.10:56:57.84#ibcon#about to read 5, iclass 28, count 0 2006.285.10:56:57.84#ibcon#read 5, iclass 28, count 0 2006.285.10:56:57.84#ibcon#about to read 6, iclass 28, count 0 2006.285.10:56:57.84#ibcon#read 6, iclass 28, count 0 2006.285.10:56:57.84#ibcon#end of sib2, iclass 28, count 0 2006.285.10:56:57.84#ibcon#*mode == 0, iclass 28, count 0 2006.285.10:56:57.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.10:56:57.84#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.10:56:57.84#ibcon#*before write, iclass 28, count 0 2006.285.10:56:57.84#ibcon#enter sib2, iclass 28, count 0 2006.285.10:56:57.84#ibcon#flushed, iclass 28, count 0 2006.285.10:56:57.84#ibcon#about to write, iclass 28, count 0 2006.285.10:56:57.84#ibcon#wrote, iclass 28, count 0 2006.285.10:56:57.84#ibcon#about to read 3, iclass 28, count 0 2006.285.10:56:57.88#ibcon#read 3, iclass 28, count 0 2006.285.10:56:57.88#ibcon#about to read 4, iclass 28, count 0 2006.285.10:56:57.88#ibcon#read 4, iclass 28, count 0 2006.285.10:56:57.88#ibcon#about to read 5, iclass 28, count 0 2006.285.10:56:57.88#ibcon#read 5, iclass 28, count 0 2006.285.10:56:57.88#ibcon#about to read 6, iclass 28, count 0 2006.285.10:56:57.88#ibcon#read 6, iclass 28, count 0 2006.285.10:56:57.88#ibcon#end of sib2, iclass 28, count 0 2006.285.10:56:57.88#ibcon#*after write, iclass 28, count 0 2006.285.10:56:57.88#ibcon#*before return 0, iclass 28, count 0 2006.285.10:56:57.88#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:56:57.88#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.10:56:57.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.10:56:57.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.10:56:57.88$vck44/vb=5,4 2006.285.10:56:57.88#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.10:56:57.88#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.10:56:57.88#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:57.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:56:57.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:56:57.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:56:57.94#ibcon#enter wrdev, iclass 30, count 2 2006.285.10:56:57.94#ibcon#first serial, iclass 30, count 2 2006.285.10:56:57.94#ibcon#enter sib2, iclass 30, count 2 2006.285.10:56:57.94#ibcon#flushed, iclass 30, count 2 2006.285.10:56:57.94#ibcon#about to write, iclass 30, count 2 2006.285.10:56:57.94#ibcon#wrote, iclass 30, count 2 2006.285.10:56:57.94#ibcon#about to read 3, iclass 30, count 2 2006.285.10:56:57.96#ibcon#read 3, iclass 30, count 2 2006.285.10:56:57.96#ibcon#about to read 4, iclass 30, count 2 2006.285.10:56:57.96#ibcon#read 4, iclass 30, count 2 2006.285.10:56:57.96#ibcon#about to read 5, iclass 30, count 2 2006.285.10:56:57.96#ibcon#read 5, iclass 30, count 2 2006.285.10:56:57.96#ibcon#about to read 6, iclass 30, count 2 2006.285.10:56:57.96#ibcon#read 6, iclass 30, count 2 2006.285.10:56:57.96#ibcon#end of sib2, iclass 30, count 2 2006.285.10:56:57.96#ibcon#*mode == 0, iclass 30, count 2 2006.285.10:56:57.96#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.10:56:57.96#ibcon#[27=AT05-04\r\n] 2006.285.10:56:57.96#ibcon#*before write, iclass 30, count 2 2006.285.10:56:57.96#ibcon#enter sib2, iclass 30, count 2 2006.285.10:56:57.96#ibcon#flushed, iclass 30, count 2 2006.285.10:56:57.96#ibcon#about to write, iclass 30, count 2 2006.285.10:56:57.96#ibcon#wrote, iclass 30, count 2 2006.285.10:56:57.96#ibcon#about to read 3, iclass 30, count 2 2006.285.10:56:57.99#ibcon#read 3, iclass 30, count 2 2006.285.10:56:57.99#ibcon#about to read 4, iclass 30, count 2 2006.285.10:56:57.99#ibcon#read 4, iclass 30, count 2 2006.285.10:56:57.99#ibcon#about to read 5, iclass 30, count 2 2006.285.10:56:57.99#ibcon#read 5, iclass 30, count 2 2006.285.10:56:57.99#ibcon#about to read 6, iclass 30, count 2 2006.285.10:56:57.99#ibcon#read 6, iclass 30, count 2 2006.285.10:56:57.99#ibcon#end of sib2, iclass 30, count 2 2006.285.10:56:57.99#ibcon#*after write, iclass 30, count 2 2006.285.10:56:57.99#ibcon#*before return 0, iclass 30, count 2 2006.285.10:56:57.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:56:57.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.10:56:57.99#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.10:56:57.99#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:57.99#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:56:58.11#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:56:58.11#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:56:58.11#ibcon#enter wrdev, iclass 30, count 0 2006.285.10:56:58.11#ibcon#first serial, iclass 30, count 0 2006.285.10:56:58.11#ibcon#enter sib2, iclass 30, count 0 2006.285.10:56:58.11#ibcon#flushed, iclass 30, count 0 2006.285.10:56:58.11#ibcon#about to write, iclass 30, count 0 2006.285.10:56:58.11#ibcon#wrote, iclass 30, count 0 2006.285.10:56:58.11#ibcon#about to read 3, iclass 30, count 0 2006.285.10:56:58.13#ibcon#read 3, iclass 30, count 0 2006.285.10:56:58.13#ibcon#about to read 4, iclass 30, count 0 2006.285.10:56:58.13#ibcon#read 4, iclass 30, count 0 2006.285.10:56:58.13#ibcon#about to read 5, iclass 30, count 0 2006.285.10:56:58.13#ibcon#read 5, iclass 30, count 0 2006.285.10:56:58.13#ibcon#about to read 6, iclass 30, count 0 2006.285.10:56:58.13#ibcon#read 6, iclass 30, count 0 2006.285.10:56:58.13#ibcon#end of sib2, iclass 30, count 0 2006.285.10:56:58.13#ibcon#*mode == 0, iclass 30, count 0 2006.285.10:56:58.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.10:56:58.13#ibcon#[27=USB\r\n] 2006.285.10:56:58.13#ibcon#*before write, iclass 30, count 0 2006.285.10:56:58.13#ibcon#enter sib2, iclass 30, count 0 2006.285.10:56:58.13#ibcon#flushed, iclass 30, count 0 2006.285.10:56:58.13#ibcon#about to write, iclass 30, count 0 2006.285.10:56:58.13#ibcon#wrote, iclass 30, count 0 2006.285.10:56:58.13#ibcon#about to read 3, iclass 30, count 0 2006.285.10:56:58.16#ibcon#read 3, iclass 30, count 0 2006.285.10:56:58.16#ibcon#about to read 4, iclass 30, count 0 2006.285.10:56:58.16#ibcon#read 4, iclass 30, count 0 2006.285.10:56:58.16#ibcon#about to read 5, iclass 30, count 0 2006.285.10:56:58.16#ibcon#read 5, iclass 30, count 0 2006.285.10:56:58.16#ibcon#about to read 6, iclass 30, count 0 2006.285.10:56:58.16#ibcon#read 6, iclass 30, count 0 2006.285.10:56:58.16#ibcon#end of sib2, iclass 30, count 0 2006.285.10:56:58.16#ibcon#*after write, iclass 30, count 0 2006.285.10:56:58.16#ibcon#*before return 0, iclass 30, count 0 2006.285.10:56:58.16#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:56:58.16#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.10:56:58.16#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.10:56:58.16#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.10:56:58.16$vck44/vblo=6,719.99 2006.285.10:56:58.16#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.10:56:58.16#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.10:56:58.16#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:58.16#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:56:58.16#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:56:58.16#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:56:58.16#ibcon#enter wrdev, iclass 32, count 0 2006.285.10:56:58.16#ibcon#first serial, iclass 32, count 0 2006.285.10:56:58.16#ibcon#enter sib2, iclass 32, count 0 2006.285.10:56:58.16#ibcon#flushed, iclass 32, count 0 2006.285.10:56:58.16#ibcon#about to write, iclass 32, count 0 2006.285.10:56:58.16#ibcon#wrote, iclass 32, count 0 2006.285.10:56:58.16#ibcon#about to read 3, iclass 32, count 0 2006.285.10:56:58.18#ibcon#read 3, iclass 32, count 0 2006.285.10:56:58.18#ibcon#about to read 4, iclass 32, count 0 2006.285.10:56:58.18#ibcon#read 4, iclass 32, count 0 2006.285.10:56:58.18#ibcon#about to read 5, iclass 32, count 0 2006.285.10:56:58.18#ibcon#read 5, iclass 32, count 0 2006.285.10:56:58.18#ibcon#about to read 6, iclass 32, count 0 2006.285.10:56:58.18#ibcon#read 6, iclass 32, count 0 2006.285.10:56:58.18#ibcon#end of sib2, iclass 32, count 0 2006.285.10:56:58.18#ibcon#*mode == 0, iclass 32, count 0 2006.285.10:56:58.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.10:56:58.18#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.10:56:58.18#ibcon#*before write, iclass 32, count 0 2006.285.10:56:58.18#ibcon#enter sib2, iclass 32, count 0 2006.285.10:56:58.18#ibcon#flushed, iclass 32, count 0 2006.285.10:56:58.18#ibcon#about to write, iclass 32, count 0 2006.285.10:56:58.18#ibcon#wrote, iclass 32, count 0 2006.285.10:56:58.18#ibcon#about to read 3, iclass 32, count 0 2006.285.10:56:58.22#ibcon#read 3, iclass 32, count 0 2006.285.10:56:58.22#ibcon#about to read 4, iclass 32, count 0 2006.285.10:56:58.22#ibcon#read 4, iclass 32, count 0 2006.285.10:56:58.22#ibcon#about to read 5, iclass 32, count 0 2006.285.10:56:58.22#ibcon#read 5, iclass 32, count 0 2006.285.10:56:58.22#ibcon#about to read 6, iclass 32, count 0 2006.285.10:56:58.22#ibcon#read 6, iclass 32, count 0 2006.285.10:56:58.22#ibcon#end of sib2, iclass 32, count 0 2006.285.10:56:58.22#ibcon#*after write, iclass 32, count 0 2006.285.10:56:58.22#ibcon#*before return 0, iclass 32, count 0 2006.285.10:56:58.22#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:56:58.22#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.10:56:58.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.10:56:58.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.10:56:58.22$vck44/vb=6,3 2006.285.10:56:58.22#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.10:56:58.22#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.10:56:58.22#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:58.22#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:56:58.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:56:58.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:56:58.28#ibcon#enter wrdev, iclass 34, count 2 2006.285.10:56:58.28#ibcon#first serial, iclass 34, count 2 2006.285.10:56:58.28#ibcon#enter sib2, iclass 34, count 2 2006.285.10:56:58.28#ibcon#flushed, iclass 34, count 2 2006.285.10:56:58.28#ibcon#about to write, iclass 34, count 2 2006.285.10:56:58.28#ibcon#wrote, iclass 34, count 2 2006.285.10:56:58.28#ibcon#about to read 3, iclass 34, count 2 2006.285.10:56:58.30#ibcon#read 3, iclass 34, count 2 2006.285.10:56:58.30#ibcon#about to read 4, iclass 34, count 2 2006.285.10:56:58.30#ibcon#read 4, iclass 34, count 2 2006.285.10:56:58.30#ibcon#about to read 5, iclass 34, count 2 2006.285.10:56:58.30#ibcon#read 5, iclass 34, count 2 2006.285.10:56:58.30#ibcon#about to read 6, iclass 34, count 2 2006.285.10:56:58.30#ibcon#read 6, iclass 34, count 2 2006.285.10:56:58.30#ibcon#end of sib2, iclass 34, count 2 2006.285.10:56:58.30#ibcon#*mode == 0, iclass 34, count 2 2006.285.10:56:58.30#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.10:56:58.30#ibcon#[27=AT06-03\r\n] 2006.285.10:56:58.30#ibcon#*before write, iclass 34, count 2 2006.285.10:56:58.30#ibcon#enter sib2, iclass 34, count 2 2006.285.10:56:58.30#ibcon#flushed, iclass 34, count 2 2006.285.10:56:58.30#ibcon#about to write, iclass 34, count 2 2006.285.10:56:58.30#ibcon#wrote, iclass 34, count 2 2006.285.10:56:58.30#ibcon#about to read 3, iclass 34, count 2 2006.285.10:56:58.33#ibcon#read 3, iclass 34, count 2 2006.285.10:56:58.33#ibcon#about to read 4, iclass 34, count 2 2006.285.10:56:58.33#ibcon#read 4, iclass 34, count 2 2006.285.10:56:58.33#ibcon#about to read 5, iclass 34, count 2 2006.285.10:56:58.33#ibcon#read 5, iclass 34, count 2 2006.285.10:56:58.33#ibcon#about to read 6, iclass 34, count 2 2006.285.10:56:58.33#ibcon#read 6, iclass 34, count 2 2006.285.10:56:58.33#ibcon#end of sib2, iclass 34, count 2 2006.285.10:56:58.33#ibcon#*after write, iclass 34, count 2 2006.285.10:56:58.33#ibcon#*before return 0, iclass 34, count 2 2006.285.10:56:58.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:56:58.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.10:56:58.33#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.10:56:58.33#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:58.33#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:56:58.45#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:56:58.45#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:56:58.45#ibcon#enter wrdev, iclass 34, count 0 2006.285.10:56:58.45#ibcon#first serial, iclass 34, count 0 2006.285.10:56:58.45#ibcon#enter sib2, iclass 34, count 0 2006.285.10:56:58.45#ibcon#flushed, iclass 34, count 0 2006.285.10:56:58.45#ibcon#about to write, iclass 34, count 0 2006.285.10:56:58.45#ibcon#wrote, iclass 34, count 0 2006.285.10:56:58.45#ibcon#about to read 3, iclass 34, count 0 2006.285.10:56:58.47#ibcon#read 3, iclass 34, count 0 2006.285.10:56:58.47#ibcon#about to read 4, iclass 34, count 0 2006.285.10:56:58.47#ibcon#read 4, iclass 34, count 0 2006.285.10:56:58.47#ibcon#about to read 5, iclass 34, count 0 2006.285.10:56:58.47#ibcon#read 5, iclass 34, count 0 2006.285.10:56:58.47#ibcon#about to read 6, iclass 34, count 0 2006.285.10:56:58.47#ibcon#read 6, iclass 34, count 0 2006.285.10:56:58.47#ibcon#end of sib2, iclass 34, count 0 2006.285.10:56:58.47#ibcon#*mode == 0, iclass 34, count 0 2006.285.10:56:58.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.10:56:58.47#ibcon#[27=USB\r\n] 2006.285.10:56:58.47#ibcon#*before write, iclass 34, count 0 2006.285.10:56:58.47#ibcon#enter sib2, iclass 34, count 0 2006.285.10:56:58.47#ibcon#flushed, iclass 34, count 0 2006.285.10:56:58.47#ibcon#about to write, iclass 34, count 0 2006.285.10:56:58.47#ibcon#wrote, iclass 34, count 0 2006.285.10:56:58.47#ibcon#about to read 3, iclass 34, count 0 2006.285.10:56:58.50#ibcon#read 3, iclass 34, count 0 2006.285.10:56:58.50#ibcon#about to read 4, iclass 34, count 0 2006.285.10:56:58.50#ibcon#read 4, iclass 34, count 0 2006.285.10:56:58.50#ibcon#about to read 5, iclass 34, count 0 2006.285.10:56:58.50#ibcon#read 5, iclass 34, count 0 2006.285.10:56:58.50#ibcon#about to read 6, iclass 34, count 0 2006.285.10:56:58.50#ibcon#read 6, iclass 34, count 0 2006.285.10:56:58.50#ibcon#end of sib2, iclass 34, count 0 2006.285.10:56:58.50#ibcon#*after write, iclass 34, count 0 2006.285.10:56:58.50#ibcon#*before return 0, iclass 34, count 0 2006.285.10:56:58.50#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:56:58.50#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.10:56:58.50#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.10:56:58.50#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.10:56:58.50$vck44/vblo=7,734.99 2006.285.10:56:58.50#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.10:56:58.50#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.10:56:58.50#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:58.50#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:56:58.50#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:56:58.50#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:56:58.50#ibcon#enter wrdev, iclass 36, count 0 2006.285.10:56:58.50#ibcon#first serial, iclass 36, count 0 2006.285.10:56:58.50#ibcon#enter sib2, iclass 36, count 0 2006.285.10:56:58.50#ibcon#flushed, iclass 36, count 0 2006.285.10:56:58.50#ibcon#about to write, iclass 36, count 0 2006.285.10:56:58.50#ibcon#wrote, iclass 36, count 0 2006.285.10:56:58.50#ibcon#about to read 3, iclass 36, count 0 2006.285.10:56:58.52#ibcon#read 3, iclass 36, count 0 2006.285.10:56:58.52#ibcon#about to read 4, iclass 36, count 0 2006.285.10:56:58.52#ibcon#read 4, iclass 36, count 0 2006.285.10:56:58.52#ibcon#about to read 5, iclass 36, count 0 2006.285.10:56:58.52#ibcon#read 5, iclass 36, count 0 2006.285.10:56:58.52#ibcon#about to read 6, iclass 36, count 0 2006.285.10:56:58.52#ibcon#read 6, iclass 36, count 0 2006.285.10:56:58.52#ibcon#end of sib2, iclass 36, count 0 2006.285.10:56:58.52#ibcon#*mode == 0, iclass 36, count 0 2006.285.10:56:58.52#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.10:56:58.52#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.10:56:58.52#ibcon#*before write, iclass 36, count 0 2006.285.10:56:58.52#ibcon#enter sib2, iclass 36, count 0 2006.285.10:56:58.52#ibcon#flushed, iclass 36, count 0 2006.285.10:56:58.52#ibcon#about to write, iclass 36, count 0 2006.285.10:56:58.52#ibcon#wrote, iclass 36, count 0 2006.285.10:56:58.52#ibcon#about to read 3, iclass 36, count 0 2006.285.10:56:58.56#ibcon#read 3, iclass 36, count 0 2006.285.10:56:58.56#ibcon#about to read 4, iclass 36, count 0 2006.285.10:56:58.56#ibcon#read 4, iclass 36, count 0 2006.285.10:56:58.56#ibcon#about to read 5, iclass 36, count 0 2006.285.10:56:58.56#ibcon#read 5, iclass 36, count 0 2006.285.10:56:58.56#ibcon#about to read 6, iclass 36, count 0 2006.285.10:56:58.56#ibcon#read 6, iclass 36, count 0 2006.285.10:56:58.56#ibcon#end of sib2, iclass 36, count 0 2006.285.10:56:58.56#ibcon#*after write, iclass 36, count 0 2006.285.10:56:58.56#ibcon#*before return 0, iclass 36, count 0 2006.285.10:56:58.56#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:56:58.56#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.10:56:58.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.10:56:58.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.10:56:58.56$vck44/vb=7,4 2006.285.10:56:58.56#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.10:56:58.56#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.10:56:58.56#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:58.56#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:56:58.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:56:58.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:56:58.62#ibcon#enter wrdev, iclass 38, count 2 2006.285.10:56:58.62#ibcon#first serial, iclass 38, count 2 2006.285.10:56:58.62#ibcon#enter sib2, iclass 38, count 2 2006.285.10:56:58.62#ibcon#flushed, iclass 38, count 2 2006.285.10:56:58.62#ibcon#about to write, iclass 38, count 2 2006.285.10:56:58.62#ibcon#wrote, iclass 38, count 2 2006.285.10:56:58.62#ibcon#about to read 3, iclass 38, count 2 2006.285.10:56:58.64#ibcon#read 3, iclass 38, count 2 2006.285.10:56:58.64#ibcon#about to read 4, iclass 38, count 2 2006.285.10:56:58.64#ibcon#read 4, iclass 38, count 2 2006.285.10:56:58.64#ibcon#about to read 5, iclass 38, count 2 2006.285.10:56:58.64#ibcon#read 5, iclass 38, count 2 2006.285.10:56:58.64#ibcon#about to read 6, iclass 38, count 2 2006.285.10:56:58.64#ibcon#read 6, iclass 38, count 2 2006.285.10:56:58.64#ibcon#end of sib2, iclass 38, count 2 2006.285.10:56:58.64#ibcon#*mode == 0, iclass 38, count 2 2006.285.10:56:58.64#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.10:56:58.64#ibcon#[27=AT07-04\r\n] 2006.285.10:56:58.64#ibcon#*before write, iclass 38, count 2 2006.285.10:56:58.64#ibcon#enter sib2, iclass 38, count 2 2006.285.10:56:58.64#ibcon#flushed, iclass 38, count 2 2006.285.10:56:58.64#ibcon#about to write, iclass 38, count 2 2006.285.10:56:58.64#ibcon#wrote, iclass 38, count 2 2006.285.10:56:58.64#ibcon#about to read 3, iclass 38, count 2 2006.285.10:56:58.67#ibcon#read 3, iclass 38, count 2 2006.285.10:56:58.67#ibcon#about to read 4, iclass 38, count 2 2006.285.10:56:58.67#ibcon#read 4, iclass 38, count 2 2006.285.10:56:58.67#ibcon#about to read 5, iclass 38, count 2 2006.285.10:56:58.67#ibcon#read 5, iclass 38, count 2 2006.285.10:56:58.67#ibcon#about to read 6, iclass 38, count 2 2006.285.10:56:58.67#ibcon#read 6, iclass 38, count 2 2006.285.10:56:58.67#ibcon#end of sib2, iclass 38, count 2 2006.285.10:56:58.67#ibcon#*after write, iclass 38, count 2 2006.285.10:56:58.67#ibcon#*before return 0, iclass 38, count 2 2006.285.10:56:58.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:56:58.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.10:56:58.67#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.10:56:58.67#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:58.67#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:56:58.79#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:56:58.79#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:56:58.79#ibcon#enter wrdev, iclass 38, count 0 2006.285.10:56:58.79#ibcon#first serial, iclass 38, count 0 2006.285.10:56:58.79#ibcon#enter sib2, iclass 38, count 0 2006.285.10:56:58.79#ibcon#flushed, iclass 38, count 0 2006.285.10:56:58.79#ibcon#about to write, iclass 38, count 0 2006.285.10:56:58.79#ibcon#wrote, iclass 38, count 0 2006.285.10:56:58.79#ibcon#about to read 3, iclass 38, count 0 2006.285.10:56:58.81#ibcon#read 3, iclass 38, count 0 2006.285.10:56:58.81#ibcon#about to read 4, iclass 38, count 0 2006.285.10:56:58.81#ibcon#read 4, iclass 38, count 0 2006.285.10:56:58.81#ibcon#about to read 5, iclass 38, count 0 2006.285.10:56:58.81#ibcon#read 5, iclass 38, count 0 2006.285.10:56:58.81#ibcon#about to read 6, iclass 38, count 0 2006.285.10:56:58.81#ibcon#read 6, iclass 38, count 0 2006.285.10:56:58.81#ibcon#end of sib2, iclass 38, count 0 2006.285.10:56:58.81#ibcon#*mode == 0, iclass 38, count 0 2006.285.10:56:58.81#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.10:56:58.81#ibcon#[27=USB\r\n] 2006.285.10:56:58.81#ibcon#*before write, iclass 38, count 0 2006.285.10:56:58.81#ibcon#enter sib2, iclass 38, count 0 2006.285.10:56:58.81#ibcon#flushed, iclass 38, count 0 2006.285.10:56:58.81#ibcon#about to write, iclass 38, count 0 2006.285.10:56:58.81#ibcon#wrote, iclass 38, count 0 2006.285.10:56:58.81#ibcon#about to read 3, iclass 38, count 0 2006.285.10:56:58.84#ibcon#read 3, iclass 38, count 0 2006.285.10:56:58.84#ibcon#about to read 4, iclass 38, count 0 2006.285.10:56:58.84#ibcon#read 4, iclass 38, count 0 2006.285.10:56:58.84#ibcon#about to read 5, iclass 38, count 0 2006.285.10:56:58.84#ibcon#read 5, iclass 38, count 0 2006.285.10:56:58.84#ibcon#about to read 6, iclass 38, count 0 2006.285.10:56:58.84#ibcon#read 6, iclass 38, count 0 2006.285.10:56:58.84#ibcon#end of sib2, iclass 38, count 0 2006.285.10:56:58.84#ibcon#*after write, iclass 38, count 0 2006.285.10:56:58.84#ibcon#*before return 0, iclass 38, count 0 2006.285.10:56:58.84#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:56:58.84#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.10:56:58.84#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.10:56:58.84#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.10:56:58.84$vck44/vblo=8,744.99 2006.285.10:56:58.84#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.10:56:58.84#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.10:56:58.84#ibcon#ireg 17 cls_cnt 0 2006.285.10:56:58.84#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:56:58.84#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:56:58.84#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:56:58.84#ibcon#enter wrdev, iclass 40, count 0 2006.285.10:56:58.84#ibcon#first serial, iclass 40, count 0 2006.285.10:56:58.84#ibcon#enter sib2, iclass 40, count 0 2006.285.10:56:58.84#ibcon#flushed, iclass 40, count 0 2006.285.10:56:58.84#ibcon#about to write, iclass 40, count 0 2006.285.10:56:58.84#ibcon#wrote, iclass 40, count 0 2006.285.10:56:58.84#ibcon#about to read 3, iclass 40, count 0 2006.285.10:56:58.86#ibcon#read 3, iclass 40, count 0 2006.285.10:56:58.86#ibcon#about to read 4, iclass 40, count 0 2006.285.10:56:58.86#ibcon#read 4, iclass 40, count 0 2006.285.10:56:58.86#ibcon#about to read 5, iclass 40, count 0 2006.285.10:56:58.86#ibcon#read 5, iclass 40, count 0 2006.285.10:56:58.86#ibcon#about to read 6, iclass 40, count 0 2006.285.10:56:58.86#ibcon#read 6, iclass 40, count 0 2006.285.10:56:58.86#ibcon#end of sib2, iclass 40, count 0 2006.285.10:56:58.86#ibcon#*mode == 0, iclass 40, count 0 2006.285.10:56:58.86#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.10:56:58.86#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.10:56:58.86#ibcon#*before write, iclass 40, count 0 2006.285.10:56:58.86#ibcon#enter sib2, iclass 40, count 0 2006.285.10:56:58.86#ibcon#flushed, iclass 40, count 0 2006.285.10:56:58.86#ibcon#about to write, iclass 40, count 0 2006.285.10:56:58.86#ibcon#wrote, iclass 40, count 0 2006.285.10:56:58.86#ibcon#about to read 3, iclass 40, count 0 2006.285.10:56:58.90#ibcon#read 3, iclass 40, count 0 2006.285.10:56:58.90#ibcon#about to read 4, iclass 40, count 0 2006.285.10:56:58.90#ibcon#read 4, iclass 40, count 0 2006.285.10:56:58.90#ibcon#about to read 5, iclass 40, count 0 2006.285.10:56:58.90#ibcon#read 5, iclass 40, count 0 2006.285.10:56:58.90#ibcon#about to read 6, iclass 40, count 0 2006.285.10:56:58.90#ibcon#read 6, iclass 40, count 0 2006.285.10:56:58.90#ibcon#end of sib2, iclass 40, count 0 2006.285.10:56:58.90#ibcon#*after write, iclass 40, count 0 2006.285.10:56:58.90#ibcon#*before return 0, iclass 40, count 0 2006.285.10:56:58.90#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:56:58.90#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.10:56:58.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.10:56:58.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.10:56:58.90$vck44/vb=8,4 2006.285.10:56:58.90#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.10:56:58.90#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.10:56:58.90#ibcon#ireg 11 cls_cnt 2 2006.285.10:56:58.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:56:58.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:56:58.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:56:58.96#ibcon#enter wrdev, iclass 4, count 2 2006.285.10:56:58.96#ibcon#first serial, iclass 4, count 2 2006.285.10:56:58.96#ibcon#enter sib2, iclass 4, count 2 2006.285.10:56:58.96#ibcon#flushed, iclass 4, count 2 2006.285.10:56:58.96#ibcon#about to write, iclass 4, count 2 2006.285.10:56:58.96#ibcon#wrote, iclass 4, count 2 2006.285.10:56:58.96#ibcon#about to read 3, iclass 4, count 2 2006.285.10:56:58.98#ibcon#read 3, iclass 4, count 2 2006.285.10:56:58.98#ibcon#about to read 4, iclass 4, count 2 2006.285.10:56:58.98#ibcon#read 4, iclass 4, count 2 2006.285.10:56:58.98#ibcon#about to read 5, iclass 4, count 2 2006.285.10:56:58.98#ibcon#read 5, iclass 4, count 2 2006.285.10:56:58.98#ibcon#about to read 6, iclass 4, count 2 2006.285.10:56:58.98#ibcon#read 6, iclass 4, count 2 2006.285.10:56:58.98#ibcon#end of sib2, iclass 4, count 2 2006.285.10:56:58.98#ibcon#*mode == 0, iclass 4, count 2 2006.285.10:56:58.98#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.10:56:58.98#ibcon#[27=AT08-04\r\n] 2006.285.10:56:58.98#ibcon#*before write, iclass 4, count 2 2006.285.10:56:58.98#ibcon#enter sib2, iclass 4, count 2 2006.285.10:56:58.98#ibcon#flushed, iclass 4, count 2 2006.285.10:56:58.98#ibcon#about to write, iclass 4, count 2 2006.285.10:56:58.98#ibcon#wrote, iclass 4, count 2 2006.285.10:56:58.98#ibcon#about to read 3, iclass 4, count 2 2006.285.10:56:59.01#ibcon#read 3, iclass 4, count 2 2006.285.10:56:59.01#ibcon#about to read 4, iclass 4, count 2 2006.285.10:56:59.01#ibcon#read 4, iclass 4, count 2 2006.285.10:56:59.01#ibcon#about to read 5, iclass 4, count 2 2006.285.10:56:59.01#ibcon#read 5, iclass 4, count 2 2006.285.10:56:59.01#ibcon#about to read 6, iclass 4, count 2 2006.285.10:56:59.01#ibcon#read 6, iclass 4, count 2 2006.285.10:56:59.01#ibcon#end of sib2, iclass 4, count 2 2006.285.10:56:59.01#ibcon#*after write, iclass 4, count 2 2006.285.10:56:59.01#ibcon#*before return 0, iclass 4, count 2 2006.285.10:56:59.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:56:59.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.10:56:59.01#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.10:56:59.01#ibcon#ireg 7 cls_cnt 0 2006.285.10:56:59.01#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:56:59.13#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:56:59.13#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:56:59.13#ibcon#enter wrdev, iclass 4, count 0 2006.285.10:56:59.13#ibcon#first serial, iclass 4, count 0 2006.285.10:56:59.13#ibcon#enter sib2, iclass 4, count 0 2006.285.10:56:59.13#ibcon#flushed, iclass 4, count 0 2006.285.10:56:59.13#ibcon#about to write, iclass 4, count 0 2006.285.10:56:59.13#ibcon#wrote, iclass 4, count 0 2006.285.10:56:59.13#ibcon#about to read 3, iclass 4, count 0 2006.285.10:56:59.15#ibcon#read 3, iclass 4, count 0 2006.285.10:56:59.15#ibcon#about to read 4, iclass 4, count 0 2006.285.10:56:59.15#ibcon#read 4, iclass 4, count 0 2006.285.10:56:59.15#ibcon#about to read 5, iclass 4, count 0 2006.285.10:56:59.15#ibcon#read 5, iclass 4, count 0 2006.285.10:56:59.15#ibcon#about to read 6, iclass 4, count 0 2006.285.10:56:59.15#ibcon#read 6, iclass 4, count 0 2006.285.10:56:59.15#ibcon#end of sib2, iclass 4, count 0 2006.285.10:56:59.15#ibcon#*mode == 0, iclass 4, count 0 2006.285.10:56:59.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.10:56:59.15#ibcon#[27=USB\r\n] 2006.285.10:56:59.15#ibcon#*before write, iclass 4, count 0 2006.285.10:56:59.15#ibcon#enter sib2, iclass 4, count 0 2006.285.10:56:59.15#ibcon#flushed, iclass 4, count 0 2006.285.10:56:59.15#ibcon#about to write, iclass 4, count 0 2006.285.10:56:59.15#ibcon#wrote, iclass 4, count 0 2006.285.10:56:59.15#ibcon#about to read 3, iclass 4, count 0 2006.285.10:56:59.18#ibcon#read 3, iclass 4, count 0 2006.285.10:56:59.18#ibcon#about to read 4, iclass 4, count 0 2006.285.10:56:59.18#ibcon#read 4, iclass 4, count 0 2006.285.10:56:59.18#ibcon#about to read 5, iclass 4, count 0 2006.285.10:56:59.18#ibcon#read 5, iclass 4, count 0 2006.285.10:56:59.18#ibcon#about to read 6, iclass 4, count 0 2006.285.10:56:59.18#ibcon#read 6, iclass 4, count 0 2006.285.10:56:59.18#ibcon#end of sib2, iclass 4, count 0 2006.285.10:56:59.18#ibcon#*after write, iclass 4, count 0 2006.285.10:56:59.18#ibcon#*before return 0, iclass 4, count 0 2006.285.10:56:59.18#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:56:59.18#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.10:56:59.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.10:56:59.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.10:56:59.18$vck44/vabw=wide 2006.285.10:56:59.18#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.10:56:59.18#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.10:56:59.18#ibcon#ireg 8 cls_cnt 0 2006.285.10:56:59.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:56:59.18#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:56:59.18#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:56:59.18#ibcon#enter wrdev, iclass 6, count 0 2006.285.10:56:59.18#ibcon#first serial, iclass 6, count 0 2006.285.10:56:59.18#ibcon#enter sib2, iclass 6, count 0 2006.285.10:56:59.18#ibcon#flushed, iclass 6, count 0 2006.285.10:56:59.18#ibcon#about to write, iclass 6, count 0 2006.285.10:56:59.18#ibcon#wrote, iclass 6, count 0 2006.285.10:56:59.18#ibcon#about to read 3, iclass 6, count 0 2006.285.10:56:59.20#ibcon#read 3, iclass 6, count 0 2006.285.10:56:59.20#ibcon#about to read 4, iclass 6, count 0 2006.285.10:56:59.20#ibcon#read 4, iclass 6, count 0 2006.285.10:56:59.20#ibcon#about to read 5, iclass 6, count 0 2006.285.10:56:59.20#ibcon#read 5, iclass 6, count 0 2006.285.10:56:59.20#ibcon#about to read 6, iclass 6, count 0 2006.285.10:56:59.20#ibcon#read 6, iclass 6, count 0 2006.285.10:56:59.20#ibcon#end of sib2, iclass 6, count 0 2006.285.10:56:59.20#ibcon#*mode == 0, iclass 6, count 0 2006.285.10:56:59.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.10:56:59.20#ibcon#[25=BW32\r\n] 2006.285.10:56:59.20#ibcon#*before write, iclass 6, count 0 2006.285.10:56:59.20#ibcon#enter sib2, iclass 6, count 0 2006.285.10:56:59.20#ibcon#flushed, iclass 6, count 0 2006.285.10:56:59.20#ibcon#about to write, iclass 6, count 0 2006.285.10:56:59.20#ibcon#wrote, iclass 6, count 0 2006.285.10:56:59.20#ibcon#about to read 3, iclass 6, count 0 2006.285.10:56:59.23#ibcon#read 3, iclass 6, count 0 2006.285.10:56:59.23#ibcon#about to read 4, iclass 6, count 0 2006.285.10:56:59.23#ibcon#read 4, iclass 6, count 0 2006.285.10:56:59.23#ibcon#about to read 5, iclass 6, count 0 2006.285.10:56:59.23#ibcon#read 5, iclass 6, count 0 2006.285.10:56:59.23#ibcon#about to read 6, iclass 6, count 0 2006.285.10:56:59.23#ibcon#read 6, iclass 6, count 0 2006.285.10:56:59.23#ibcon#end of sib2, iclass 6, count 0 2006.285.10:56:59.23#ibcon#*after write, iclass 6, count 0 2006.285.10:56:59.23#ibcon#*before return 0, iclass 6, count 0 2006.285.10:56:59.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:56:59.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.10:56:59.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.10:56:59.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.10:56:59.23$vck44/vbbw=wide 2006.285.10:56:59.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.10:56:59.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.10:56:59.23#ibcon#ireg 8 cls_cnt 0 2006.285.10:56:59.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:56:59.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:56:59.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:56:59.30#ibcon#enter wrdev, iclass 10, count 0 2006.285.10:56:59.30#ibcon#first serial, iclass 10, count 0 2006.285.10:56:59.30#ibcon#enter sib2, iclass 10, count 0 2006.285.10:56:59.30#ibcon#flushed, iclass 10, count 0 2006.285.10:56:59.30#ibcon#about to write, iclass 10, count 0 2006.285.10:56:59.30#ibcon#wrote, iclass 10, count 0 2006.285.10:56:59.30#ibcon#about to read 3, iclass 10, count 0 2006.285.10:56:59.32#ibcon#read 3, iclass 10, count 0 2006.285.10:56:59.32#ibcon#about to read 4, iclass 10, count 0 2006.285.10:56:59.32#ibcon#read 4, iclass 10, count 0 2006.285.10:56:59.32#ibcon#about to read 5, iclass 10, count 0 2006.285.10:56:59.32#ibcon#read 5, iclass 10, count 0 2006.285.10:56:59.32#ibcon#about to read 6, iclass 10, count 0 2006.285.10:56:59.32#ibcon#read 6, iclass 10, count 0 2006.285.10:56:59.32#ibcon#end of sib2, iclass 10, count 0 2006.285.10:56:59.32#ibcon#*mode == 0, iclass 10, count 0 2006.285.10:56:59.32#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.10:56:59.32#ibcon#[27=BW32\r\n] 2006.285.10:56:59.32#ibcon#*before write, iclass 10, count 0 2006.285.10:56:59.32#ibcon#enter sib2, iclass 10, count 0 2006.285.10:56:59.32#ibcon#flushed, iclass 10, count 0 2006.285.10:56:59.32#ibcon#about to write, iclass 10, count 0 2006.285.10:56:59.32#ibcon#wrote, iclass 10, count 0 2006.285.10:56:59.32#ibcon#about to read 3, iclass 10, count 0 2006.285.10:56:59.35#ibcon#read 3, iclass 10, count 0 2006.285.10:56:59.35#ibcon#about to read 4, iclass 10, count 0 2006.285.10:56:59.35#ibcon#read 4, iclass 10, count 0 2006.285.10:56:59.35#ibcon#about to read 5, iclass 10, count 0 2006.285.10:56:59.35#ibcon#read 5, iclass 10, count 0 2006.285.10:56:59.35#ibcon#about to read 6, iclass 10, count 0 2006.285.10:56:59.35#ibcon#read 6, iclass 10, count 0 2006.285.10:56:59.35#ibcon#end of sib2, iclass 10, count 0 2006.285.10:56:59.35#ibcon#*after write, iclass 10, count 0 2006.285.10:56:59.35#ibcon#*before return 0, iclass 10, count 0 2006.285.10:56:59.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:56:59.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.10:56:59.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.10:56:59.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.10:56:59.35$setupk4/ifdk4 2006.285.10:56:59.35$ifdk4/lo= 2006.285.10:56:59.35$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.10:56:59.35$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.10:56:59.35$ifdk4/patch= 2006.285.10:56:59.35$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.10:56:59.35$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.10:56:59.35$setupk4/!*+20s 2006.285.10:57:06.15#abcon#<5=/05 1.2 2.0 19.53 921014.9\r\n> 2006.285.10:57:06.17#abcon#{5=INTERFACE CLEAR} 2006.285.10:57:06.23#abcon#[5=S1D000X0/0*\r\n] 2006.285.10:57:13.85$setupk4/"tpicd 2006.285.10:57:13.85$setupk4/echo=off 2006.285.10:57:13.85$setupk4/xlog=off 2006.285.10:57:13.85:!2006.285.11:01:03 2006.285.10:57:17.14#trakl#Source acquired 2006.285.10:57:18.14#flagr#flagr/antenna,acquired 2006.285.11:01:03.00:preob 2006.285.11:01:04.14/onsource/TRACKING 2006.285.11:01:04.14:!2006.285.11:01:13 2006.285.11:01:13.00:"tape 2006.285.11:01:13.00:"st=record 2006.285.11:01:13.00:data_valid=on 2006.285.11:01:13.00:midob 2006.285.11:01:13.14/onsource/TRACKING 2006.285.11:01:13.14/wx/19.49,1015.0,92 2006.285.11:01:13.20/cable/+6.4884E-03 2006.285.11:01:14.29/va/01,07,usb,yes,34,36 2006.285.11:01:14.29/va/02,06,usb,yes,34,34 2006.285.11:01:14.29/va/03,07,usb,yes,33,35 2006.285.11:01:14.29/va/04,06,usb,yes,35,36 2006.285.11:01:14.29/va/05,03,usb,yes,34,35 2006.285.11:01:14.29/va/06,04,usb,yes,31,30 2006.285.11:01:14.29/va/07,04,usb,yes,31,32 2006.285.11:01:14.29/va/08,03,usb,yes,32,39 2006.285.11:01:14.52/valo/01,524.99,yes,locked 2006.285.11:01:14.52/valo/02,534.99,yes,locked 2006.285.11:01:14.52/valo/03,564.99,yes,locked 2006.285.11:01:14.52/valo/04,624.99,yes,locked 2006.285.11:01:14.52/valo/05,734.99,yes,locked 2006.285.11:01:14.52/valo/06,814.99,yes,locked 2006.285.11:01:14.52/valo/07,864.99,yes,locked 2006.285.11:01:14.52/valo/08,884.99,yes,locked 2006.285.11:01:15.61/vb/01,04,usb,yes,32,30 2006.285.11:01:15.61/vb/02,05,usb,yes,30,30 2006.285.11:01:15.61/vb/03,04,usb,yes,31,34 2006.285.11:01:15.61/vb/04,05,usb,yes,31,30 2006.285.11:01:15.61/vb/05,04,usb,yes,28,30 2006.285.11:01:15.61/vb/06,03,usb,yes,40,35 2006.285.11:01:15.61/vb/07,04,usb,yes,32,32 2006.285.11:01:15.61/vb/08,04,usb,yes,29,33 2006.285.11:01:15.84/vblo/01,629.99,yes,locked 2006.285.11:01:15.84/vblo/02,634.99,yes,locked 2006.285.11:01:15.84/vblo/03,649.99,yes,locked 2006.285.11:01:15.84/vblo/04,679.99,yes,locked 2006.285.11:01:15.84/vblo/05,709.99,yes,locked 2006.285.11:01:15.84/vblo/06,719.99,yes,locked 2006.285.11:01:15.84/vblo/07,734.99,yes,locked 2006.285.11:01:15.84/vblo/08,744.99,yes,locked 2006.285.11:01:15.99/vabw/8 2006.285.11:01:16.14/vbbw/8 2006.285.11:01:16.34/xfe/off,on,12.2 2006.285.11:01:16.71/ifatt/23,28,28,28 2006.285.11:01:17.08/fmout-gps/S +2.73E-07 2006.285.11:01:17.10:!2006.285.11:01:53 2006.285.11:01:53.00:data_valid=off 2006.285.11:01:53.00:"et 2006.285.11:01:53.00:!+3s 2006.285.11:01:56.01:"tape 2006.285.11:01:56.01:postob 2006.285.11:01:56.11/cable/+6.4881E-03 2006.285.11:01:56.11/wx/19.49,1015.0,92 2006.285.11:01:57.07/fmout-gps/S +2.73E-07 2006.285.11:01:57.07:scan_name=285-1103,jd0610,70 2006.285.11:01:57.07:source=2121+053,212344.52,053522.1,2000.0,cw 2006.285.11:01:58.14#flagr#flagr/antenna,new-source 2006.285.11:01:58.14:checkk5 2006.285.11:01:58.51/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:01:58.93/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:01:59.40/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:01:59.80/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:02:00.19/chk_obsdata//k5ts1/T2851101??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.11:02:00.54/chk_obsdata//k5ts2/T2851101??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.11:02:00.93/chk_obsdata//k5ts3/T2851101??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.11:02:01.47/chk_obsdata//k5ts4/T2851101??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.11:02:02.33/k5log//k5ts1_log_newline 2006.285.11:02:03.38/k5log//k5ts2_log_newline 2006.285.11:02:04.18/k5log//k5ts3_log_newline 2006.285.11:02:05.20/k5log//k5ts4_log_newline 2006.285.11:02:05.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:02:05.22:setupk4=1 2006.285.11:02:05.22$setupk4/echo=on 2006.285.11:02:05.22$setupk4/pcalon 2006.285.11:02:05.22$pcalon/"no phase cal control is implemented here 2006.285.11:02:05.22$setupk4/"tpicd=stop 2006.285.11:02:05.22$setupk4/"rec=synch_on 2006.285.11:02:05.22$setupk4/"rec_mode=128 2006.285.11:02:05.22$setupk4/!* 2006.285.11:02:05.22$setupk4/recpk4 2006.285.11:02:05.22$recpk4/recpatch= 2006.285.11:02:05.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:02:05.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:02:05.22$setupk4/vck44 2006.285.11:02:05.23$vck44/valo=1,524.99 2006.285.11:02:05.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.11:02:05.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.11:02:05.23#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:05.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:02:05.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:02:05.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:02:05.23#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:02:05.23#ibcon#first serial, iclass 27, count 0 2006.285.11:02:05.23#ibcon#enter sib2, iclass 27, count 0 2006.285.11:02:05.23#ibcon#flushed, iclass 27, count 0 2006.285.11:02:05.23#ibcon#about to write, iclass 27, count 0 2006.285.11:02:05.23#ibcon#wrote, iclass 27, count 0 2006.285.11:02:05.23#ibcon#about to read 3, iclass 27, count 0 2006.285.11:02:05.25#ibcon#read 3, iclass 27, count 0 2006.285.11:02:05.25#ibcon#about to read 4, iclass 27, count 0 2006.285.11:02:05.25#ibcon#read 4, iclass 27, count 0 2006.285.11:02:05.25#ibcon#about to read 5, iclass 27, count 0 2006.285.11:02:05.25#ibcon#read 5, iclass 27, count 0 2006.285.11:02:05.25#ibcon#about to read 6, iclass 27, count 0 2006.285.11:02:05.25#ibcon#read 6, iclass 27, count 0 2006.285.11:02:05.25#ibcon#end of sib2, iclass 27, count 0 2006.285.11:02:05.25#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:02:05.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:02:05.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:02:05.25#ibcon#*before write, iclass 27, count 0 2006.285.11:02:05.25#ibcon#enter sib2, iclass 27, count 0 2006.285.11:02:05.25#ibcon#flushed, iclass 27, count 0 2006.285.11:02:05.25#ibcon#about to write, iclass 27, count 0 2006.285.11:02:05.25#ibcon#wrote, iclass 27, count 0 2006.285.11:02:05.25#ibcon#about to read 3, iclass 27, count 0 2006.285.11:02:05.30#ibcon#read 3, iclass 27, count 0 2006.285.11:02:05.30#ibcon#about to read 4, iclass 27, count 0 2006.285.11:02:05.30#ibcon#read 4, iclass 27, count 0 2006.285.11:02:05.30#ibcon#about to read 5, iclass 27, count 0 2006.285.11:02:05.30#ibcon#read 5, iclass 27, count 0 2006.285.11:02:05.30#ibcon#about to read 6, iclass 27, count 0 2006.285.11:02:05.30#ibcon#read 6, iclass 27, count 0 2006.285.11:02:05.30#ibcon#end of sib2, iclass 27, count 0 2006.285.11:02:05.30#ibcon#*after write, iclass 27, count 0 2006.285.11:02:05.30#ibcon#*before return 0, iclass 27, count 0 2006.285.11:02:05.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:02:05.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:02:05.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:02:05.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:02:05.30$vck44/va=1,7 2006.285.11:02:05.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.11:02:05.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.11:02:05.30#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:05.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:02:05.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:02:05.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:02:05.30#ibcon#enter wrdev, iclass 29, count 2 2006.285.11:02:05.30#ibcon#first serial, iclass 29, count 2 2006.285.11:02:05.30#ibcon#enter sib2, iclass 29, count 2 2006.285.11:02:05.30#ibcon#flushed, iclass 29, count 2 2006.285.11:02:05.30#ibcon#about to write, iclass 29, count 2 2006.285.11:02:05.30#ibcon#wrote, iclass 29, count 2 2006.285.11:02:05.30#ibcon#about to read 3, iclass 29, count 2 2006.285.11:02:05.32#ibcon#read 3, iclass 29, count 2 2006.285.11:02:05.32#ibcon#about to read 4, iclass 29, count 2 2006.285.11:02:05.32#ibcon#read 4, iclass 29, count 2 2006.285.11:02:05.32#ibcon#about to read 5, iclass 29, count 2 2006.285.11:02:05.32#ibcon#read 5, iclass 29, count 2 2006.285.11:02:05.32#ibcon#about to read 6, iclass 29, count 2 2006.285.11:02:05.32#ibcon#read 6, iclass 29, count 2 2006.285.11:02:05.32#ibcon#end of sib2, iclass 29, count 2 2006.285.11:02:05.32#ibcon#*mode == 0, iclass 29, count 2 2006.285.11:02:05.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.11:02:05.32#ibcon#[25=AT01-07\r\n] 2006.285.11:02:05.32#ibcon#*before write, iclass 29, count 2 2006.285.11:02:05.32#ibcon#enter sib2, iclass 29, count 2 2006.285.11:02:05.32#ibcon#flushed, iclass 29, count 2 2006.285.11:02:05.32#ibcon#about to write, iclass 29, count 2 2006.285.11:02:05.32#ibcon#wrote, iclass 29, count 2 2006.285.11:02:05.32#ibcon#about to read 3, iclass 29, count 2 2006.285.11:02:05.35#ibcon#read 3, iclass 29, count 2 2006.285.11:02:05.35#ibcon#about to read 4, iclass 29, count 2 2006.285.11:02:05.35#ibcon#read 4, iclass 29, count 2 2006.285.11:02:05.35#ibcon#about to read 5, iclass 29, count 2 2006.285.11:02:05.35#ibcon#read 5, iclass 29, count 2 2006.285.11:02:05.35#ibcon#about to read 6, iclass 29, count 2 2006.285.11:02:05.35#ibcon#read 6, iclass 29, count 2 2006.285.11:02:05.35#ibcon#end of sib2, iclass 29, count 2 2006.285.11:02:05.35#ibcon#*after write, iclass 29, count 2 2006.285.11:02:05.35#ibcon#*before return 0, iclass 29, count 2 2006.285.11:02:05.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:02:05.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:02:05.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.11:02:05.35#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:05.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:02:05.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:02:05.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:02:05.47#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:02:05.47#ibcon#first serial, iclass 29, count 0 2006.285.11:02:05.47#ibcon#enter sib2, iclass 29, count 0 2006.285.11:02:05.47#ibcon#flushed, iclass 29, count 0 2006.285.11:02:05.47#ibcon#about to write, iclass 29, count 0 2006.285.11:02:05.47#ibcon#wrote, iclass 29, count 0 2006.285.11:02:05.47#ibcon#about to read 3, iclass 29, count 0 2006.285.11:02:05.49#ibcon#read 3, iclass 29, count 0 2006.285.11:02:05.49#ibcon#about to read 4, iclass 29, count 0 2006.285.11:02:05.49#ibcon#read 4, iclass 29, count 0 2006.285.11:02:05.49#ibcon#about to read 5, iclass 29, count 0 2006.285.11:02:05.49#ibcon#read 5, iclass 29, count 0 2006.285.11:02:05.49#ibcon#about to read 6, iclass 29, count 0 2006.285.11:02:05.49#ibcon#read 6, iclass 29, count 0 2006.285.11:02:05.49#ibcon#end of sib2, iclass 29, count 0 2006.285.11:02:05.49#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:02:05.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:02:05.49#ibcon#[25=USB\r\n] 2006.285.11:02:05.49#ibcon#*before write, iclass 29, count 0 2006.285.11:02:05.49#ibcon#enter sib2, iclass 29, count 0 2006.285.11:02:05.49#ibcon#flushed, iclass 29, count 0 2006.285.11:02:05.49#ibcon#about to write, iclass 29, count 0 2006.285.11:02:05.49#ibcon#wrote, iclass 29, count 0 2006.285.11:02:05.49#ibcon#about to read 3, iclass 29, count 0 2006.285.11:02:05.52#ibcon#read 3, iclass 29, count 0 2006.285.11:02:05.52#ibcon#about to read 4, iclass 29, count 0 2006.285.11:02:05.52#ibcon#read 4, iclass 29, count 0 2006.285.11:02:05.52#ibcon#about to read 5, iclass 29, count 0 2006.285.11:02:05.52#ibcon#read 5, iclass 29, count 0 2006.285.11:02:05.52#ibcon#about to read 6, iclass 29, count 0 2006.285.11:02:05.52#ibcon#read 6, iclass 29, count 0 2006.285.11:02:05.52#ibcon#end of sib2, iclass 29, count 0 2006.285.11:02:05.52#ibcon#*after write, iclass 29, count 0 2006.285.11:02:05.52#ibcon#*before return 0, iclass 29, count 0 2006.285.11:02:05.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:02:05.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:02:05.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:02:05.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:02:05.52$vck44/valo=2,534.99 2006.285.11:02:05.52#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.11:02:05.52#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.11:02:05.52#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:05.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:02:05.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:02:05.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:02:05.52#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:02:05.52#ibcon#first serial, iclass 31, count 0 2006.285.11:02:05.52#ibcon#enter sib2, iclass 31, count 0 2006.285.11:02:05.52#ibcon#flushed, iclass 31, count 0 2006.285.11:02:05.52#ibcon#about to write, iclass 31, count 0 2006.285.11:02:05.52#ibcon#wrote, iclass 31, count 0 2006.285.11:02:05.52#ibcon#about to read 3, iclass 31, count 0 2006.285.11:02:05.54#ibcon#read 3, iclass 31, count 0 2006.285.11:02:05.54#ibcon#about to read 4, iclass 31, count 0 2006.285.11:02:05.54#ibcon#read 4, iclass 31, count 0 2006.285.11:02:05.54#ibcon#about to read 5, iclass 31, count 0 2006.285.11:02:05.54#ibcon#read 5, iclass 31, count 0 2006.285.11:02:05.54#ibcon#about to read 6, iclass 31, count 0 2006.285.11:02:05.54#ibcon#read 6, iclass 31, count 0 2006.285.11:02:05.54#ibcon#end of sib2, iclass 31, count 0 2006.285.11:02:05.54#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:02:05.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:02:05.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:02:05.54#ibcon#*before write, iclass 31, count 0 2006.285.11:02:05.54#ibcon#enter sib2, iclass 31, count 0 2006.285.11:02:05.54#ibcon#flushed, iclass 31, count 0 2006.285.11:02:05.54#ibcon#about to write, iclass 31, count 0 2006.285.11:02:05.54#ibcon#wrote, iclass 31, count 0 2006.285.11:02:05.54#ibcon#about to read 3, iclass 31, count 0 2006.285.11:02:05.58#ibcon#read 3, iclass 31, count 0 2006.285.11:02:05.58#ibcon#about to read 4, iclass 31, count 0 2006.285.11:02:05.58#ibcon#read 4, iclass 31, count 0 2006.285.11:02:05.58#ibcon#about to read 5, iclass 31, count 0 2006.285.11:02:05.58#ibcon#read 5, iclass 31, count 0 2006.285.11:02:05.58#ibcon#about to read 6, iclass 31, count 0 2006.285.11:02:05.58#ibcon#read 6, iclass 31, count 0 2006.285.11:02:05.58#ibcon#end of sib2, iclass 31, count 0 2006.285.11:02:05.58#ibcon#*after write, iclass 31, count 0 2006.285.11:02:05.58#ibcon#*before return 0, iclass 31, count 0 2006.285.11:02:05.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:02:05.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:02:05.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:02:05.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:02:05.58$vck44/va=2,6 2006.285.11:02:05.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.11:02:05.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.11:02:05.58#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:05.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:02:05.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:02:05.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:02:05.64#ibcon#enter wrdev, iclass 33, count 2 2006.285.11:02:05.64#ibcon#first serial, iclass 33, count 2 2006.285.11:02:05.64#ibcon#enter sib2, iclass 33, count 2 2006.285.11:02:05.64#ibcon#flushed, iclass 33, count 2 2006.285.11:02:05.64#ibcon#about to write, iclass 33, count 2 2006.285.11:02:05.64#ibcon#wrote, iclass 33, count 2 2006.285.11:02:05.64#ibcon#about to read 3, iclass 33, count 2 2006.285.11:02:05.66#ibcon#read 3, iclass 33, count 2 2006.285.11:02:05.66#ibcon#about to read 4, iclass 33, count 2 2006.285.11:02:05.66#ibcon#read 4, iclass 33, count 2 2006.285.11:02:05.66#ibcon#about to read 5, iclass 33, count 2 2006.285.11:02:05.66#ibcon#read 5, iclass 33, count 2 2006.285.11:02:05.66#ibcon#about to read 6, iclass 33, count 2 2006.285.11:02:05.66#ibcon#read 6, iclass 33, count 2 2006.285.11:02:05.66#ibcon#end of sib2, iclass 33, count 2 2006.285.11:02:05.66#ibcon#*mode == 0, iclass 33, count 2 2006.285.11:02:05.66#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.11:02:05.66#ibcon#[25=AT02-06\r\n] 2006.285.11:02:05.66#ibcon#*before write, iclass 33, count 2 2006.285.11:02:05.66#ibcon#enter sib2, iclass 33, count 2 2006.285.11:02:05.66#ibcon#flushed, iclass 33, count 2 2006.285.11:02:05.66#ibcon#about to write, iclass 33, count 2 2006.285.11:02:05.66#ibcon#wrote, iclass 33, count 2 2006.285.11:02:05.66#ibcon#about to read 3, iclass 33, count 2 2006.285.11:02:05.69#ibcon#read 3, iclass 33, count 2 2006.285.11:02:05.69#ibcon#about to read 4, iclass 33, count 2 2006.285.11:02:05.69#ibcon#read 4, iclass 33, count 2 2006.285.11:02:05.69#ibcon#about to read 5, iclass 33, count 2 2006.285.11:02:05.69#ibcon#read 5, iclass 33, count 2 2006.285.11:02:05.69#ibcon#about to read 6, iclass 33, count 2 2006.285.11:02:05.69#ibcon#read 6, iclass 33, count 2 2006.285.11:02:05.69#ibcon#end of sib2, iclass 33, count 2 2006.285.11:02:05.69#ibcon#*after write, iclass 33, count 2 2006.285.11:02:05.69#ibcon#*before return 0, iclass 33, count 2 2006.285.11:02:05.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:02:05.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:02:05.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.11:02:05.69#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:05.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:02:05.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:02:05.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:02:05.81#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:02:05.81#ibcon#first serial, iclass 33, count 0 2006.285.11:02:05.81#ibcon#enter sib2, iclass 33, count 0 2006.285.11:02:05.81#ibcon#flushed, iclass 33, count 0 2006.285.11:02:05.81#ibcon#about to write, iclass 33, count 0 2006.285.11:02:05.81#ibcon#wrote, iclass 33, count 0 2006.285.11:02:05.81#ibcon#about to read 3, iclass 33, count 0 2006.285.11:02:05.83#ibcon#read 3, iclass 33, count 0 2006.285.11:02:05.83#ibcon#about to read 4, iclass 33, count 0 2006.285.11:02:05.83#ibcon#read 4, iclass 33, count 0 2006.285.11:02:05.83#ibcon#about to read 5, iclass 33, count 0 2006.285.11:02:05.83#ibcon#read 5, iclass 33, count 0 2006.285.11:02:05.83#ibcon#about to read 6, iclass 33, count 0 2006.285.11:02:05.83#ibcon#read 6, iclass 33, count 0 2006.285.11:02:05.83#ibcon#end of sib2, iclass 33, count 0 2006.285.11:02:05.83#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:02:05.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:02:05.83#ibcon#[25=USB\r\n] 2006.285.11:02:05.83#ibcon#*before write, iclass 33, count 0 2006.285.11:02:05.83#ibcon#enter sib2, iclass 33, count 0 2006.285.11:02:05.83#ibcon#flushed, iclass 33, count 0 2006.285.11:02:05.83#ibcon#about to write, iclass 33, count 0 2006.285.11:02:05.83#ibcon#wrote, iclass 33, count 0 2006.285.11:02:05.83#ibcon#about to read 3, iclass 33, count 0 2006.285.11:02:05.86#ibcon#read 3, iclass 33, count 0 2006.285.11:02:05.86#ibcon#about to read 4, iclass 33, count 0 2006.285.11:02:05.86#ibcon#read 4, iclass 33, count 0 2006.285.11:02:05.86#ibcon#about to read 5, iclass 33, count 0 2006.285.11:02:05.86#ibcon#read 5, iclass 33, count 0 2006.285.11:02:05.86#ibcon#about to read 6, iclass 33, count 0 2006.285.11:02:05.86#ibcon#read 6, iclass 33, count 0 2006.285.11:02:05.86#ibcon#end of sib2, iclass 33, count 0 2006.285.11:02:05.86#ibcon#*after write, iclass 33, count 0 2006.285.11:02:05.86#ibcon#*before return 0, iclass 33, count 0 2006.285.11:02:05.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:02:05.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:02:05.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:02:05.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:02:05.86$vck44/valo=3,564.99 2006.285.11:02:05.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.11:02:05.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.11:02:05.86#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:05.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:02:05.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:02:05.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:02:05.86#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:02:05.86#ibcon#first serial, iclass 35, count 0 2006.285.11:02:05.86#ibcon#enter sib2, iclass 35, count 0 2006.285.11:02:05.86#ibcon#flushed, iclass 35, count 0 2006.285.11:02:05.86#ibcon#about to write, iclass 35, count 0 2006.285.11:02:05.86#ibcon#wrote, iclass 35, count 0 2006.285.11:02:05.86#ibcon#about to read 3, iclass 35, count 0 2006.285.11:02:05.88#ibcon#read 3, iclass 35, count 0 2006.285.11:02:05.88#ibcon#about to read 4, iclass 35, count 0 2006.285.11:02:05.88#ibcon#read 4, iclass 35, count 0 2006.285.11:02:05.88#ibcon#about to read 5, iclass 35, count 0 2006.285.11:02:05.88#ibcon#read 5, iclass 35, count 0 2006.285.11:02:05.88#ibcon#about to read 6, iclass 35, count 0 2006.285.11:02:05.88#ibcon#read 6, iclass 35, count 0 2006.285.11:02:05.88#ibcon#end of sib2, iclass 35, count 0 2006.285.11:02:05.88#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:02:05.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:02:05.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:02:05.88#ibcon#*before write, iclass 35, count 0 2006.285.11:02:05.88#ibcon#enter sib2, iclass 35, count 0 2006.285.11:02:05.88#ibcon#flushed, iclass 35, count 0 2006.285.11:02:05.88#ibcon#about to write, iclass 35, count 0 2006.285.11:02:05.88#ibcon#wrote, iclass 35, count 0 2006.285.11:02:05.88#ibcon#about to read 3, iclass 35, count 0 2006.285.11:02:05.92#ibcon#read 3, iclass 35, count 0 2006.285.11:02:05.92#ibcon#about to read 4, iclass 35, count 0 2006.285.11:02:05.92#ibcon#read 4, iclass 35, count 0 2006.285.11:02:05.92#ibcon#about to read 5, iclass 35, count 0 2006.285.11:02:05.92#ibcon#read 5, iclass 35, count 0 2006.285.11:02:05.92#ibcon#about to read 6, iclass 35, count 0 2006.285.11:02:05.92#ibcon#read 6, iclass 35, count 0 2006.285.11:02:05.92#ibcon#end of sib2, iclass 35, count 0 2006.285.11:02:05.92#ibcon#*after write, iclass 35, count 0 2006.285.11:02:05.92#ibcon#*before return 0, iclass 35, count 0 2006.285.11:02:05.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:02:05.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:02:05.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:02:05.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:02:05.92$vck44/va=3,7 2006.285.11:02:05.92#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.11:02:05.92#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.11:02:05.92#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:05.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:02:05.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:02:05.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:02:05.98#ibcon#enter wrdev, iclass 37, count 2 2006.285.11:02:05.98#ibcon#first serial, iclass 37, count 2 2006.285.11:02:05.98#ibcon#enter sib2, iclass 37, count 2 2006.285.11:02:05.98#ibcon#flushed, iclass 37, count 2 2006.285.11:02:05.98#ibcon#about to write, iclass 37, count 2 2006.285.11:02:05.98#ibcon#wrote, iclass 37, count 2 2006.285.11:02:05.98#ibcon#about to read 3, iclass 37, count 2 2006.285.11:02:06.00#ibcon#read 3, iclass 37, count 2 2006.285.11:02:06.00#ibcon#about to read 4, iclass 37, count 2 2006.285.11:02:06.00#ibcon#read 4, iclass 37, count 2 2006.285.11:02:06.00#ibcon#about to read 5, iclass 37, count 2 2006.285.11:02:06.00#ibcon#read 5, iclass 37, count 2 2006.285.11:02:06.00#ibcon#about to read 6, iclass 37, count 2 2006.285.11:02:06.00#ibcon#read 6, iclass 37, count 2 2006.285.11:02:06.00#ibcon#end of sib2, iclass 37, count 2 2006.285.11:02:06.00#ibcon#*mode == 0, iclass 37, count 2 2006.285.11:02:06.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.11:02:06.00#ibcon#[25=AT03-07\r\n] 2006.285.11:02:06.00#ibcon#*before write, iclass 37, count 2 2006.285.11:02:06.00#ibcon#enter sib2, iclass 37, count 2 2006.285.11:02:06.00#ibcon#flushed, iclass 37, count 2 2006.285.11:02:06.00#ibcon#about to write, iclass 37, count 2 2006.285.11:02:06.00#ibcon#wrote, iclass 37, count 2 2006.285.11:02:06.00#ibcon#about to read 3, iclass 37, count 2 2006.285.11:02:06.03#ibcon#read 3, iclass 37, count 2 2006.285.11:02:06.03#ibcon#about to read 4, iclass 37, count 2 2006.285.11:02:06.03#ibcon#read 4, iclass 37, count 2 2006.285.11:02:06.03#ibcon#about to read 5, iclass 37, count 2 2006.285.11:02:06.03#ibcon#read 5, iclass 37, count 2 2006.285.11:02:06.03#ibcon#about to read 6, iclass 37, count 2 2006.285.11:02:06.03#ibcon#read 6, iclass 37, count 2 2006.285.11:02:06.03#ibcon#end of sib2, iclass 37, count 2 2006.285.11:02:06.03#ibcon#*after write, iclass 37, count 2 2006.285.11:02:06.03#ibcon#*before return 0, iclass 37, count 2 2006.285.11:02:06.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:02:06.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:02:06.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.11:02:06.03#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:06.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:02:06.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:02:06.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:02:06.15#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:02:06.15#ibcon#first serial, iclass 37, count 0 2006.285.11:02:06.15#ibcon#enter sib2, iclass 37, count 0 2006.285.11:02:06.15#ibcon#flushed, iclass 37, count 0 2006.285.11:02:06.15#ibcon#about to write, iclass 37, count 0 2006.285.11:02:06.15#ibcon#wrote, iclass 37, count 0 2006.285.11:02:06.15#ibcon#about to read 3, iclass 37, count 0 2006.285.11:02:06.17#ibcon#read 3, iclass 37, count 0 2006.285.11:02:06.17#ibcon#about to read 4, iclass 37, count 0 2006.285.11:02:06.17#ibcon#read 4, iclass 37, count 0 2006.285.11:02:06.17#ibcon#about to read 5, iclass 37, count 0 2006.285.11:02:06.17#ibcon#read 5, iclass 37, count 0 2006.285.11:02:06.17#ibcon#about to read 6, iclass 37, count 0 2006.285.11:02:06.17#ibcon#read 6, iclass 37, count 0 2006.285.11:02:06.17#ibcon#end of sib2, iclass 37, count 0 2006.285.11:02:06.17#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:02:06.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:02:06.17#ibcon#[25=USB\r\n] 2006.285.11:02:06.17#ibcon#*before write, iclass 37, count 0 2006.285.11:02:06.17#ibcon#enter sib2, iclass 37, count 0 2006.285.11:02:06.17#ibcon#flushed, iclass 37, count 0 2006.285.11:02:06.17#ibcon#about to write, iclass 37, count 0 2006.285.11:02:06.17#ibcon#wrote, iclass 37, count 0 2006.285.11:02:06.17#ibcon#about to read 3, iclass 37, count 0 2006.285.11:02:06.20#ibcon#read 3, iclass 37, count 0 2006.285.11:02:06.20#ibcon#about to read 4, iclass 37, count 0 2006.285.11:02:06.20#ibcon#read 4, iclass 37, count 0 2006.285.11:02:06.20#ibcon#about to read 5, iclass 37, count 0 2006.285.11:02:06.20#ibcon#read 5, iclass 37, count 0 2006.285.11:02:06.20#ibcon#about to read 6, iclass 37, count 0 2006.285.11:02:06.20#ibcon#read 6, iclass 37, count 0 2006.285.11:02:06.20#ibcon#end of sib2, iclass 37, count 0 2006.285.11:02:06.20#ibcon#*after write, iclass 37, count 0 2006.285.11:02:06.20#ibcon#*before return 0, iclass 37, count 0 2006.285.11:02:06.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:02:06.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:02:06.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:02:06.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:02:06.20$vck44/valo=4,624.99 2006.285.11:02:06.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.11:02:06.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.11:02:06.20#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:06.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:02:06.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:02:06.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:02:06.20#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:02:06.20#ibcon#first serial, iclass 39, count 0 2006.285.11:02:06.20#ibcon#enter sib2, iclass 39, count 0 2006.285.11:02:06.20#ibcon#flushed, iclass 39, count 0 2006.285.11:02:06.20#ibcon#about to write, iclass 39, count 0 2006.285.11:02:06.20#ibcon#wrote, iclass 39, count 0 2006.285.11:02:06.20#ibcon#about to read 3, iclass 39, count 0 2006.285.11:02:06.22#ibcon#read 3, iclass 39, count 0 2006.285.11:02:06.22#ibcon#about to read 4, iclass 39, count 0 2006.285.11:02:06.22#ibcon#read 4, iclass 39, count 0 2006.285.11:02:06.22#ibcon#about to read 5, iclass 39, count 0 2006.285.11:02:06.22#ibcon#read 5, iclass 39, count 0 2006.285.11:02:06.22#ibcon#about to read 6, iclass 39, count 0 2006.285.11:02:06.22#ibcon#read 6, iclass 39, count 0 2006.285.11:02:06.22#ibcon#end of sib2, iclass 39, count 0 2006.285.11:02:06.22#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:02:06.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:02:06.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:02:06.22#ibcon#*before write, iclass 39, count 0 2006.285.11:02:06.22#ibcon#enter sib2, iclass 39, count 0 2006.285.11:02:06.22#ibcon#flushed, iclass 39, count 0 2006.285.11:02:06.22#ibcon#about to write, iclass 39, count 0 2006.285.11:02:06.22#ibcon#wrote, iclass 39, count 0 2006.285.11:02:06.22#ibcon#about to read 3, iclass 39, count 0 2006.285.11:02:06.26#ibcon#read 3, iclass 39, count 0 2006.285.11:02:06.26#ibcon#about to read 4, iclass 39, count 0 2006.285.11:02:06.26#ibcon#read 4, iclass 39, count 0 2006.285.11:02:06.26#ibcon#about to read 5, iclass 39, count 0 2006.285.11:02:06.26#ibcon#read 5, iclass 39, count 0 2006.285.11:02:06.26#ibcon#about to read 6, iclass 39, count 0 2006.285.11:02:06.26#ibcon#read 6, iclass 39, count 0 2006.285.11:02:06.26#ibcon#end of sib2, iclass 39, count 0 2006.285.11:02:06.26#ibcon#*after write, iclass 39, count 0 2006.285.11:02:06.26#ibcon#*before return 0, iclass 39, count 0 2006.285.11:02:06.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:02:06.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:02:06.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:02:06.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:02:06.26$vck44/va=4,6 2006.285.11:02:06.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.11:02:06.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.11:02:06.26#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:06.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:02:06.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:02:06.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:02:06.32#ibcon#enter wrdev, iclass 3, count 2 2006.285.11:02:06.32#ibcon#first serial, iclass 3, count 2 2006.285.11:02:06.32#ibcon#enter sib2, iclass 3, count 2 2006.285.11:02:06.32#ibcon#flushed, iclass 3, count 2 2006.285.11:02:06.32#ibcon#about to write, iclass 3, count 2 2006.285.11:02:06.32#ibcon#wrote, iclass 3, count 2 2006.285.11:02:06.32#ibcon#about to read 3, iclass 3, count 2 2006.285.11:02:06.34#ibcon#read 3, iclass 3, count 2 2006.285.11:02:06.34#ibcon#about to read 4, iclass 3, count 2 2006.285.11:02:06.34#ibcon#read 4, iclass 3, count 2 2006.285.11:02:06.34#ibcon#about to read 5, iclass 3, count 2 2006.285.11:02:06.34#ibcon#read 5, iclass 3, count 2 2006.285.11:02:06.34#ibcon#about to read 6, iclass 3, count 2 2006.285.11:02:06.34#ibcon#read 6, iclass 3, count 2 2006.285.11:02:06.34#ibcon#end of sib2, iclass 3, count 2 2006.285.11:02:06.34#ibcon#*mode == 0, iclass 3, count 2 2006.285.11:02:06.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.11:02:06.34#ibcon#[25=AT04-06\r\n] 2006.285.11:02:06.34#ibcon#*before write, iclass 3, count 2 2006.285.11:02:06.34#ibcon#enter sib2, iclass 3, count 2 2006.285.11:02:06.34#ibcon#flushed, iclass 3, count 2 2006.285.11:02:06.34#ibcon#about to write, iclass 3, count 2 2006.285.11:02:06.34#ibcon#wrote, iclass 3, count 2 2006.285.11:02:06.34#ibcon#about to read 3, iclass 3, count 2 2006.285.11:02:06.37#ibcon#read 3, iclass 3, count 2 2006.285.11:02:06.37#ibcon#about to read 4, iclass 3, count 2 2006.285.11:02:06.37#ibcon#read 4, iclass 3, count 2 2006.285.11:02:06.37#ibcon#about to read 5, iclass 3, count 2 2006.285.11:02:06.37#ibcon#read 5, iclass 3, count 2 2006.285.11:02:06.37#ibcon#about to read 6, iclass 3, count 2 2006.285.11:02:06.37#ibcon#read 6, iclass 3, count 2 2006.285.11:02:06.37#ibcon#end of sib2, iclass 3, count 2 2006.285.11:02:06.37#ibcon#*after write, iclass 3, count 2 2006.285.11:02:06.37#ibcon#*before return 0, iclass 3, count 2 2006.285.11:02:06.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:02:06.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:02:06.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.11:02:06.37#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:06.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:02:06.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:02:06.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:02:06.49#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:02:06.49#ibcon#first serial, iclass 3, count 0 2006.285.11:02:06.49#ibcon#enter sib2, iclass 3, count 0 2006.285.11:02:06.49#ibcon#flushed, iclass 3, count 0 2006.285.11:02:06.49#ibcon#about to write, iclass 3, count 0 2006.285.11:02:06.49#ibcon#wrote, iclass 3, count 0 2006.285.11:02:06.49#ibcon#about to read 3, iclass 3, count 0 2006.285.11:02:06.51#ibcon#read 3, iclass 3, count 0 2006.285.11:02:06.51#ibcon#about to read 4, iclass 3, count 0 2006.285.11:02:06.51#ibcon#read 4, iclass 3, count 0 2006.285.11:02:06.51#ibcon#about to read 5, iclass 3, count 0 2006.285.11:02:06.51#ibcon#read 5, iclass 3, count 0 2006.285.11:02:06.51#ibcon#about to read 6, iclass 3, count 0 2006.285.11:02:06.51#ibcon#read 6, iclass 3, count 0 2006.285.11:02:06.51#ibcon#end of sib2, iclass 3, count 0 2006.285.11:02:06.51#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:02:06.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:02:06.51#ibcon#[25=USB\r\n] 2006.285.11:02:06.51#ibcon#*before write, iclass 3, count 0 2006.285.11:02:06.51#ibcon#enter sib2, iclass 3, count 0 2006.285.11:02:06.51#ibcon#flushed, iclass 3, count 0 2006.285.11:02:06.51#ibcon#about to write, iclass 3, count 0 2006.285.11:02:06.51#ibcon#wrote, iclass 3, count 0 2006.285.11:02:06.51#ibcon#about to read 3, iclass 3, count 0 2006.285.11:02:06.54#ibcon#read 3, iclass 3, count 0 2006.285.11:02:06.54#ibcon#about to read 4, iclass 3, count 0 2006.285.11:02:06.54#ibcon#read 4, iclass 3, count 0 2006.285.11:02:06.54#ibcon#about to read 5, iclass 3, count 0 2006.285.11:02:06.54#ibcon#read 5, iclass 3, count 0 2006.285.11:02:06.54#ibcon#about to read 6, iclass 3, count 0 2006.285.11:02:06.54#ibcon#read 6, iclass 3, count 0 2006.285.11:02:06.54#ibcon#end of sib2, iclass 3, count 0 2006.285.11:02:06.54#ibcon#*after write, iclass 3, count 0 2006.285.11:02:06.54#ibcon#*before return 0, iclass 3, count 0 2006.285.11:02:06.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:02:06.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:02:06.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:02:06.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:02:06.54$vck44/valo=5,734.99 2006.285.11:02:06.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.11:02:06.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.11:02:06.54#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:06.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:02:06.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:02:06.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:02:06.54#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:02:06.54#ibcon#first serial, iclass 5, count 0 2006.285.11:02:06.54#ibcon#enter sib2, iclass 5, count 0 2006.285.11:02:06.54#ibcon#flushed, iclass 5, count 0 2006.285.11:02:06.54#ibcon#about to write, iclass 5, count 0 2006.285.11:02:06.54#ibcon#wrote, iclass 5, count 0 2006.285.11:02:06.54#ibcon#about to read 3, iclass 5, count 0 2006.285.11:02:06.56#ibcon#read 3, iclass 5, count 0 2006.285.11:02:06.56#ibcon#about to read 4, iclass 5, count 0 2006.285.11:02:06.56#ibcon#read 4, iclass 5, count 0 2006.285.11:02:06.56#ibcon#about to read 5, iclass 5, count 0 2006.285.11:02:06.56#ibcon#read 5, iclass 5, count 0 2006.285.11:02:06.56#ibcon#about to read 6, iclass 5, count 0 2006.285.11:02:06.56#ibcon#read 6, iclass 5, count 0 2006.285.11:02:06.56#ibcon#end of sib2, iclass 5, count 0 2006.285.11:02:06.56#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:02:06.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:02:06.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:02:06.56#ibcon#*before write, iclass 5, count 0 2006.285.11:02:06.56#ibcon#enter sib2, iclass 5, count 0 2006.285.11:02:06.56#ibcon#flushed, iclass 5, count 0 2006.285.11:02:06.56#ibcon#about to write, iclass 5, count 0 2006.285.11:02:06.56#ibcon#wrote, iclass 5, count 0 2006.285.11:02:06.56#ibcon#about to read 3, iclass 5, count 0 2006.285.11:02:06.60#ibcon#read 3, iclass 5, count 0 2006.285.11:02:06.60#ibcon#about to read 4, iclass 5, count 0 2006.285.11:02:06.60#ibcon#read 4, iclass 5, count 0 2006.285.11:02:06.60#ibcon#about to read 5, iclass 5, count 0 2006.285.11:02:06.60#ibcon#read 5, iclass 5, count 0 2006.285.11:02:06.60#ibcon#about to read 6, iclass 5, count 0 2006.285.11:02:06.60#ibcon#read 6, iclass 5, count 0 2006.285.11:02:06.60#ibcon#end of sib2, iclass 5, count 0 2006.285.11:02:06.60#ibcon#*after write, iclass 5, count 0 2006.285.11:02:06.60#ibcon#*before return 0, iclass 5, count 0 2006.285.11:02:06.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:02:06.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:02:06.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:02:06.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:02:06.60$vck44/va=5,3 2006.285.11:02:06.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.11:02:06.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.11:02:06.60#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:06.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:02:06.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:02:06.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:02:06.66#ibcon#enter wrdev, iclass 7, count 2 2006.285.11:02:06.66#ibcon#first serial, iclass 7, count 2 2006.285.11:02:06.66#ibcon#enter sib2, iclass 7, count 2 2006.285.11:02:06.66#ibcon#flushed, iclass 7, count 2 2006.285.11:02:06.66#ibcon#about to write, iclass 7, count 2 2006.285.11:02:06.66#ibcon#wrote, iclass 7, count 2 2006.285.11:02:06.66#ibcon#about to read 3, iclass 7, count 2 2006.285.11:02:06.68#ibcon#read 3, iclass 7, count 2 2006.285.11:02:06.68#ibcon#about to read 4, iclass 7, count 2 2006.285.11:02:06.68#ibcon#read 4, iclass 7, count 2 2006.285.11:02:06.68#ibcon#about to read 5, iclass 7, count 2 2006.285.11:02:06.68#ibcon#read 5, iclass 7, count 2 2006.285.11:02:06.68#ibcon#about to read 6, iclass 7, count 2 2006.285.11:02:06.68#ibcon#read 6, iclass 7, count 2 2006.285.11:02:06.68#ibcon#end of sib2, iclass 7, count 2 2006.285.11:02:06.68#ibcon#*mode == 0, iclass 7, count 2 2006.285.11:02:06.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.11:02:06.68#ibcon#[25=AT05-03\r\n] 2006.285.11:02:06.68#ibcon#*before write, iclass 7, count 2 2006.285.11:02:06.68#ibcon#enter sib2, iclass 7, count 2 2006.285.11:02:06.68#ibcon#flushed, iclass 7, count 2 2006.285.11:02:06.68#ibcon#about to write, iclass 7, count 2 2006.285.11:02:06.68#ibcon#wrote, iclass 7, count 2 2006.285.11:02:06.68#ibcon#about to read 3, iclass 7, count 2 2006.285.11:02:06.71#ibcon#read 3, iclass 7, count 2 2006.285.11:02:06.71#ibcon#about to read 4, iclass 7, count 2 2006.285.11:02:06.71#ibcon#read 4, iclass 7, count 2 2006.285.11:02:06.71#ibcon#about to read 5, iclass 7, count 2 2006.285.11:02:06.71#ibcon#read 5, iclass 7, count 2 2006.285.11:02:06.71#ibcon#about to read 6, iclass 7, count 2 2006.285.11:02:06.71#ibcon#read 6, iclass 7, count 2 2006.285.11:02:06.71#ibcon#end of sib2, iclass 7, count 2 2006.285.11:02:06.71#ibcon#*after write, iclass 7, count 2 2006.285.11:02:06.71#ibcon#*before return 0, iclass 7, count 2 2006.285.11:02:06.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:02:06.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:02:06.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.11:02:06.71#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:06.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:02:06.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:02:06.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:02:06.83#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:02:06.83#ibcon#first serial, iclass 7, count 0 2006.285.11:02:06.83#ibcon#enter sib2, iclass 7, count 0 2006.285.11:02:06.83#ibcon#flushed, iclass 7, count 0 2006.285.11:02:06.83#ibcon#about to write, iclass 7, count 0 2006.285.11:02:06.83#ibcon#wrote, iclass 7, count 0 2006.285.11:02:06.83#ibcon#about to read 3, iclass 7, count 0 2006.285.11:02:06.85#ibcon#read 3, iclass 7, count 0 2006.285.11:02:06.85#ibcon#about to read 4, iclass 7, count 0 2006.285.11:02:06.85#ibcon#read 4, iclass 7, count 0 2006.285.11:02:06.85#ibcon#about to read 5, iclass 7, count 0 2006.285.11:02:06.85#ibcon#read 5, iclass 7, count 0 2006.285.11:02:06.85#ibcon#about to read 6, iclass 7, count 0 2006.285.11:02:06.85#ibcon#read 6, iclass 7, count 0 2006.285.11:02:06.85#ibcon#end of sib2, iclass 7, count 0 2006.285.11:02:06.85#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:02:06.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:02:06.85#ibcon#[25=USB\r\n] 2006.285.11:02:06.85#ibcon#*before write, iclass 7, count 0 2006.285.11:02:06.85#ibcon#enter sib2, iclass 7, count 0 2006.285.11:02:06.85#ibcon#flushed, iclass 7, count 0 2006.285.11:02:06.85#ibcon#about to write, iclass 7, count 0 2006.285.11:02:06.85#ibcon#wrote, iclass 7, count 0 2006.285.11:02:06.85#ibcon#about to read 3, iclass 7, count 0 2006.285.11:02:06.88#ibcon#read 3, iclass 7, count 0 2006.285.11:02:06.88#ibcon#about to read 4, iclass 7, count 0 2006.285.11:02:06.88#ibcon#read 4, iclass 7, count 0 2006.285.11:02:06.88#ibcon#about to read 5, iclass 7, count 0 2006.285.11:02:06.88#ibcon#read 5, iclass 7, count 0 2006.285.11:02:06.88#ibcon#about to read 6, iclass 7, count 0 2006.285.11:02:06.88#ibcon#read 6, iclass 7, count 0 2006.285.11:02:06.88#ibcon#end of sib2, iclass 7, count 0 2006.285.11:02:06.88#ibcon#*after write, iclass 7, count 0 2006.285.11:02:06.88#ibcon#*before return 0, iclass 7, count 0 2006.285.11:02:06.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:02:06.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:02:06.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:02:06.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:02:06.88$vck44/valo=6,814.99 2006.285.11:02:06.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.11:02:06.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.11:02:06.88#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:06.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:02:06.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:02:06.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:02:06.88#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:02:06.88#ibcon#first serial, iclass 11, count 0 2006.285.11:02:06.88#ibcon#enter sib2, iclass 11, count 0 2006.285.11:02:06.88#ibcon#flushed, iclass 11, count 0 2006.285.11:02:06.88#ibcon#about to write, iclass 11, count 0 2006.285.11:02:06.88#ibcon#wrote, iclass 11, count 0 2006.285.11:02:06.88#ibcon#about to read 3, iclass 11, count 0 2006.285.11:02:06.90#ibcon#read 3, iclass 11, count 0 2006.285.11:02:06.90#ibcon#about to read 4, iclass 11, count 0 2006.285.11:02:06.90#ibcon#read 4, iclass 11, count 0 2006.285.11:02:06.90#ibcon#about to read 5, iclass 11, count 0 2006.285.11:02:06.90#ibcon#read 5, iclass 11, count 0 2006.285.11:02:06.90#ibcon#about to read 6, iclass 11, count 0 2006.285.11:02:06.90#ibcon#read 6, iclass 11, count 0 2006.285.11:02:06.90#ibcon#end of sib2, iclass 11, count 0 2006.285.11:02:06.90#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:02:06.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:02:06.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:02:06.90#ibcon#*before write, iclass 11, count 0 2006.285.11:02:06.90#ibcon#enter sib2, iclass 11, count 0 2006.285.11:02:06.90#ibcon#flushed, iclass 11, count 0 2006.285.11:02:06.90#ibcon#about to write, iclass 11, count 0 2006.285.11:02:06.90#ibcon#wrote, iclass 11, count 0 2006.285.11:02:06.90#ibcon#about to read 3, iclass 11, count 0 2006.285.11:02:06.94#ibcon#read 3, iclass 11, count 0 2006.285.11:02:06.94#ibcon#about to read 4, iclass 11, count 0 2006.285.11:02:06.94#ibcon#read 4, iclass 11, count 0 2006.285.11:02:06.94#ibcon#about to read 5, iclass 11, count 0 2006.285.11:02:06.94#ibcon#read 5, iclass 11, count 0 2006.285.11:02:06.94#ibcon#about to read 6, iclass 11, count 0 2006.285.11:02:06.94#ibcon#read 6, iclass 11, count 0 2006.285.11:02:06.94#ibcon#end of sib2, iclass 11, count 0 2006.285.11:02:06.94#ibcon#*after write, iclass 11, count 0 2006.285.11:02:06.94#ibcon#*before return 0, iclass 11, count 0 2006.285.11:02:06.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:02:06.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:02:06.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:02:06.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:02:06.94$vck44/va=6,4 2006.285.11:02:06.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.11:02:06.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.11:02:06.94#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:06.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:02:07.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:02:07.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:02:07.00#ibcon#enter wrdev, iclass 13, count 2 2006.285.11:02:07.00#ibcon#first serial, iclass 13, count 2 2006.285.11:02:07.00#ibcon#enter sib2, iclass 13, count 2 2006.285.11:02:07.00#ibcon#flushed, iclass 13, count 2 2006.285.11:02:07.00#ibcon#about to write, iclass 13, count 2 2006.285.11:02:07.00#ibcon#wrote, iclass 13, count 2 2006.285.11:02:07.00#ibcon#about to read 3, iclass 13, count 2 2006.285.11:02:07.02#ibcon#read 3, iclass 13, count 2 2006.285.11:02:07.02#ibcon#about to read 4, iclass 13, count 2 2006.285.11:02:07.02#ibcon#read 4, iclass 13, count 2 2006.285.11:02:07.02#ibcon#about to read 5, iclass 13, count 2 2006.285.11:02:07.02#ibcon#read 5, iclass 13, count 2 2006.285.11:02:07.02#ibcon#about to read 6, iclass 13, count 2 2006.285.11:02:07.02#ibcon#read 6, iclass 13, count 2 2006.285.11:02:07.02#ibcon#end of sib2, iclass 13, count 2 2006.285.11:02:07.02#ibcon#*mode == 0, iclass 13, count 2 2006.285.11:02:07.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.11:02:07.02#ibcon#[25=AT06-04\r\n] 2006.285.11:02:07.02#ibcon#*before write, iclass 13, count 2 2006.285.11:02:07.02#ibcon#enter sib2, iclass 13, count 2 2006.285.11:02:07.02#ibcon#flushed, iclass 13, count 2 2006.285.11:02:07.02#ibcon#about to write, iclass 13, count 2 2006.285.11:02:07.02#ibcon#wrote, iclass 13, count 2 2006.285.11:02:07.02#ibcon#about to read 3, iclass 13, count 2 2006.285.11:02:07.05#ibcon#read 3, iclass 13, count 2 2006.285.11:02:07.05#ibcon#about to read 4, iclass 13, count 2 2006.285.11:02:07.05#ibcon#read 4, iclass 13, count 2 2006.285.11:02:07.05#ibcon#about to read 5, iclass 13, count 2 2006.285.11:02:07.05#ibcon#read 5, iclass 13, count 2 2006.285.11:02:07.05#ibcon#about to read 6, iclass 13, count 2 2006.285.11:02:07.05#ibcon#read 6, iclass 13, count 2 2006.285.11:02:07.05#ibcon#end of sib2, iclass 13, count 2 2006.285.11:02:07.05#ibcon#*after write, iclass 13, count 2 2006.285.11:02:07.05#ibcon#*before return 0, iclass 13, count 2 2006.285.11:02:07.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:02:07.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:02:07.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.11:02:07.05#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:07.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:02:07.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:02:07.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:02:07.17#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:02:07.17#ibcon#first serial, iclass 13, count 0 2006.285.11:02:07.17#ibcon#enter sib2, iclass 13, count 0 2006.285.11:02:07.17#ibcon#flushed, iclass 13, count 0 2006.285.11:02:07.17#ibcon#about to write, iclass 13, count 0 2006.285.11:02:07.17#ibcon#wrote, iclass 13, count 0 2006.285.11:02:07.17#ibcon#about to read 3, iclass 13, count 0 2006.285.11:02:07.19#ibcon#read 3, iclass 13, count 0 2006.285.11:02:07.19#ibcon#about to read 4, iclass 13, count 0 2006.285.11:02:07.19#ibcon#read 4, iclass 13, count 0 2006.285.11:02:07.19#ibcon#about to read 5, iclass 13, count 0 2006.285.11:02:07.19#ibcon#read 5, iclass 13, count 0 2006.285.11:02:07.19#ibcon#about to read 6, iclass 13, count 0 2006.285.11:02:07.19#ibcon#read 6, iclass 13, count 0 2006.285.11:02:07.19#ibcon#end of sib2, iclass 13, count 0 2006.285.11:02:07.19#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:02:07.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:02:07.19#ibcon#[25=USB\r\n] 2006.285.11:02:07.19#ibcon#*before write, iclass 13, count 0 2006.285.11:02:07.19#ibcon#enter sib2, iclass 13, count 0 2006.285.11:02:07.19#ibcon#flushed, iclass 13, count 0 2006.285.11:02:07.19#ibcon#about to write, iclass 13, count 0 2006.285.11:02:07.19#ibcon#wrote, iclass 13, count 0 2006.285.11:02:07.19#ibcon#about to read 3, iclass 13, count 0 2006.285.11:02:07.22#ibcon#read 3, iclass 13, count 0 2006.285.11:02:07.22#ibcon#about to read 4, iclass 13, count 0 2006.285.11:02:07.22#ibcon#read 4, iclass 13, count 0 2006.285.11:02:07.22#ibcon#about to read 5, iclass 13, count 0 2006.285.11:02:07.22#ibcon#read 5, iclass 13, count 0 2006.285.11:02:07.22#ibcon#about to read 6, iclass 13, count 0 2006.285.11:02:07.22#ibcon#read 6, iclass 13, count 0 2006.285.11:02:07.22#ibcon#end of sib2, iclass 13, count 0 2006.285.11:02:07.22#ibcon#*after write, iclass 13, count 0 2006.285.11:02:07.22#ibcon#*before return 0, iclass 13, count 0 2006.285.11:02:07.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:02:07.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:02:07.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:02:07.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:02:07.22$vck44/valo=7,864.99 2006.285.11:02:07.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.11:02:07.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.11:02:07.22#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:07.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:02:07.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:02:07.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:02:07.22#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:02:07.22#ibcon#first serial, iclass 15, count 0 2006.285.11:02:07.22#ibcon#enter sib2, iclass 15, count 0 2006.285.11:02:07.22#ibcon#flushed, iclass 15, count 0 2006.285.11:02:07.22#ibcon#about to write, iclass 15, count 0 2006.285.11:02:07.22#ibcon#wrote, iclass 15, count 0 2006.285.11:02:07.22#ibcon#about to read 3, iclass 15, count 0 2006.285.11:02:07.24#ibcon#read 3, iclass 15, count 0 2006.285.11:02:07.24#ibcon#about to read 4, iclass 15, count 0 2006.285.11:02:07.24#ibcon#read 4, iclass 15, count 0 2006.285.11:02:07.24#ibcon#about to read 5, iclass 15, count 0 2006.285.11:02:07.24#ibcon#read 5, iclass 15, count 0 2006.285.11:02:07.24#ibcon#about to read 6, iclass 15, count 0 2006.285.11:02:07.24#ibcon#read 6, iclass 15, count 0 2006.285.11:02:07.24#ibcon#end of sib2, iclass 15, count 0 2006.285.11:02:07.24#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:02:07.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:02:07.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:02:07.24#ibcon#*before write, iclass 15, count 0 2006.285.11:02:07.24#ibcon#enter sib2, iclass 15, count 0 2006.285.11:02:07.24#ibcon#flushed, iclass 15, count 0 2006.285.11:02:07.24#ibcon#about to write, iclass 15, count 0 2006.285.11:02:07.24#ibcon#wrote, iclass 15, count 0 2006.285.11:02:07.24#ibcon#about to read 3, iclass 15, count 0 2006.285.11:02:07.28#ibcon#read 3, iclass 15, count 0 2006.285.11:02:07.28#ibcon#about to read 4, iclass 15, count 0 2006.285.11:02:07.28#ibcon#read 4, iclass 15, count 0 2006.285.11:02:07.28#ibcon#about to read 5, iclass 15, count 0 2006.285.11:02:07.28#ibcon#read 5, iclass 15, count 0 2006.285.11:02:07.28#ibcon#about to read 6, iclass 15, count 0 2006.285.11:02:07.28#ibcon#read 6, iclass 15, count 0 2006.285.11:02:07.28#ibcon#end of sib2, iclass 15, count 0 2006.285.11:02:07.28#ibcon#*after write, iclass 15, count 0 2006.285.11:02:07.28#ibcon#*before return 0, iclass 15, count 0 2006.285.11:02:07.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:02:07.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:02:07.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:02:07.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:02:07.28$vck44/va=7,4 2006.285.11:02:07.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.11:02:07.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.11:02:07.28#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:07.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:02:07.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:02:07.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:02:07.34#ibcon#enter wrdev, iclass 17, count 2 2006.285.11:02:07.34#ibcon#first serial, iclass 17, count 2 2006.285.11:02:07.34#ibcon#enter sib2, iclass 17, count 2 2006.285.11:02:07.34#ibcon#flushed, iclass 17, count 2 2006.285.11:02:07.34#ibcon#about to write, iclass 17, count 2 2006.285.11:02:07.34#ibcon#wrote, iclass 17, count 2 2006.285.11:02:07.34#ibcon#about to read 3, iclass 17, count 2 2006.285.11:02:07.36#ibcon#read 3, iclass 17, count 2 2006.285.11:02:07.36#ibcon#about to read 4, iclass 17, count 2 2006.285.11:02:07.36#ibcon#read 4, iclass 17, count 2 2006.285.11:02:07.36#ibcon#about to read 5, iclass 17, count 2 2006.285.11:02:07.36#ibcon#read 5, iclass 17, count 2 2006.285.11:02:07.36#ibcon#about to read 6, iclass 17, count 2 2006.285.11:02:07.36#ibcon#read 6, iclass 17, count 2 2006.285.11:02:07.36#ibcon#end of sib2, iclass 17, count 2 2006.285.11:02:07.36#ibcon#*mode == 0, iclass 17, count 2 2006.285.11:02:07.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.11:02:07.36#ibcon#[25=AT07-04\r\n] 2006.285.11:02:07.36#ibcon#*before write, iclass 17, count 2 2006.285.11:02:07.36#ibcon#enter sib2, iclass 17, count 2 2006.285.11:02:07.36#ibcon#flushed, iclass 17, count 2 2006.285.11:02:07.36#ibcon#about to write, iclass 17, count 2 2006.285.11:02:07.36#ibcon#wrote, iclass 17, count 2 2006.285.11:02:07.36#ibcon#about to read 3, iclass 17, count 2 2006.285.11:02:07.39#ibcon#read 3, iclass 17, count 2 2006.285.11:02:07.39#ibcon#about to read 4, iclass 17, count 2 2006.285.11:02:07.39#ibcon#read 4, iclass 17, count 2 2006.285.11:02:07.39#ibcon#about to read 5, iclass 17, count 2 2006.285.11:02:07.39#ibcon#read 5, iclass 17, count 2 2006.285.11:02:07.39#ibcon#about to read 6, iclass 17, count 2 2006.285.11:02:07.39#ibcon#read 6, iclass 17, count 2 2006.285.11:02:07.39#ibcon#end of sib2, iclass 17, count 2 2006.285.11:02:07.39#ibcon#*after write, iclass 17, count 2 2006.285.11:02:07.39#ibcon#*before return 0, iclass 17, count 2 2006.285.11:02:07.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:02:07.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:02:07.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.11:02:07.39#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:07.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:02:07.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:02:07.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:02:07.51#ibcon#enter wrdev, iclass 17, count 0 2006.285.11:02:07.51#ibcon#first serial, iclass 17, count 0 2006.285.11:02:07.51#ibcon#enter sib2, iclass 17, count 0 2006.285.11:02:07.51#ibcon#flushed, iclass 17, count 0 2006.285.11:02:07.51#ibcon#about to write, iclass 17, count 0 2006.285.11:02:07.51#ibcon#wrote, iclass 17, count 0 2006.285.11:02:07.51#ibcon#about to read 3, iclass 17, count 0 2006.285.11:02:07.53#ibcon#read 3, iclass 17, count 0 2006.285.11:02:07.53#ibcon#about to read 4, iclass 17, count 0 2006.285.11:02:07.53#ibcon#read 4, iclass 17, count 0 2006.285.11:02:07.53#ibcon#about to read 5, iclass 17, count 0 2006.285.11:02:07.53#ibcon#read 5, iclass 17, count 0 2006.285.11:02:07.53#ibcon#about to read 6, iclass 17, count 0 2006.285.11:02:07.53#ibcon#read 6, iclass 17, count 0 2006.285.11:02:07.53#ibcon#end of sib2, iclass 17, count 0 2006.285.11:02:07.53#ibcon#*mode == 0, iclass 17, count 0 2006.285.11:02:07.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.11:02:07.53#ibcon#[25=USB\r\n] 2006.285.11:02:07.53#ibcon#*before write, iclass 17, count 0 2006.285.11:02:07.53#ibcon#enter sib2, iclass 17, count 0 2006.285.11:02:07.53#ibcon#flushed, iclass 17, count 0 2006.285.11:02:07.53#ibcon#about to write, iclass 17, count 0 2006.285.11:02:07.53#ibcon#wrote, iclass 17, count 0 2006.285.11:02:07.53#ibcon#about to read 3, iclass 17, count 0 2006.285.11:02:07.56#ibcon#read 3, iclass 17, count 0 2006.285.11:02:07.56#ibcon#about to read 4, iclass 17, count 0 2006.285.11:02:07.56#ibcon#read 4, iclass 17, count 0 2006.285.11:02:07.56#ibcon#about to read 5, iclass 17, count 0 2006.285.11:02:07.56#ibcon#read 5, iclass 17, count 0 2006.285.11:02:07.56#ibcon#about to read 6, iclass 17, count 0 2006.285.11:02:07.56#ibcon#read 6, iclass 17, count 0 2006.285.11:02:07.56#ibcon#end of sib2, iclass 17, count 0 2006.285.11:02:07.56#ibcon#*after write, iclass 17, count 0 2006.285.11:02:07.56#ibcon#*before return 0, iclass 17, count 0 2006.285.11:02:07.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:02:07.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:02:07.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.11:02:07.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.11:02:07.56$vck44/valo=8,884.99 2006.285.11:02:07.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.11:02:07.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.11:02:07.56#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:07.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:02:07.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:02:07.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:02:07.56#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:02:07.56#ibcon#first serial, iclass 19, count 0 2006.285.11:02:07.56#ibcon#enter sib2, iclass 19, count 0 2006.285.11:02:07.56#ibcon#flushed, iclass 19, count 0 2006.285.11:02:07.56#ibcon#about to write, iclass 19, count 0 2006.285.11:02:07.56#ibcon#wrote, iclass 19, count 0 2006.285.11:02:07.56#ibcon#about to read 3, iclass 19, count 0 2006.285.11:02:07.58#ibcon#read 3, iclass 19, count 0 2006.285.11:02:07.58#ibcon#about to read 4, iclass 19, count 0 2006.285.11:02:07.58#ibcon#read 4, iclass 19, count 0 2006.285.11:02:07.58#ibcon#about to read 5, iclass 19, count 0 2006.285.11:02:07.58#ibcon#read 5, iclass 19, count 0 2006.285.11:02:07.58#ibcon#about to read 6, iclass 19, count 0 2006.285.11:02:07.58#ibcon#read 6, iclass 19, count 0 2006.285.11:02:07.58#ibcon#end of sib2, iclass 19, count 0 2006.285.11:02:07.58#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:02:07.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:02:07.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:02:07.58#ibcon#*before write, iclass 19, count 0 2006.285.11:02:07.58#ibcon#enter sib2, iclass 19, count 0 2006.285.11:02:07.58#ibcon#flushed, iclass 19, count 0 2006.285.11:02:07.58#ibcon#about to write, iclass 19, count 0 2006.285.11:02:07.58#ibcon#wrote, iclass 19, count 0 2006.285.11:02:07.58#ibcon#about to read 3, iclass 19, count 0 2006.285.11:02:07.62#ibcon#read 3, iclass 19, count 0 2006.285.11:02:07.62#ibcon#about to read 4, iclass 19, count 0 2006.285.11:02:07.62#ibcon#read 4, iclass 19, count 0 2006.285.11:02:07.62#ibcon#about to read 5, iclass 19, count 0 2006.285.11:02:07.62#ibcon#read 5, iclass 19, count 0 2006.285.11:02:07.62#ibcon#about to read 6, iclass 19, count 0 2006.285.11:02:07.62#ibcon#read 6, iclass 19, count 0 2006.285.11:02:07.62#ibcon#end of sib2, iclass 19, count 0 2006.285.11:02:07.62#ibcon#*after write, iclass 19, count 0 2006.285.11:02:07.62#ibcon#*before return 0, iclass 19, count 0 2006.285.11:02:07.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:02:07.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:02:07.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:02:07.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:02:07.62$vck44/va=8,3 2006.285.11:02:07.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.11:02:07.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.11:02:07.62#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:07.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:02:07.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:02:07.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:02:07.68#ibcon#enter wrdev, iclass 21, count 2 2006.285.11:02:07.68#ibcon#first serial, iclass 21, count 2 2006.285.11:02:07.68#ibcon#enter sib2, iclass 21, count 2 2006.285.11:02:07.68#ibcon#flushed, iclass 21, count 2 2006.285.11:02:07.68#ibcon#about to write, iclass 21, count 2 2006.285.11:02:07.68#ibcon#wrote, iclass 21, count 2 2006.285.11:02:07.68#ibcon#about to read 3, iclass 21, count 2 2006.285.11:02:07.70#ibcon#read 3, iclass 21, count 2 2006.285.11:02:07.70#ibcon#about to read 4, iclass 21, count 2 2006.285.11:02:07.70#ibcon#read 4, iclass 21, count 2 2006.285.11:02:07.70#ibcon#about to read 5, iclass 21, count 2 2006.285.11:02:07.70#ibcon#read 5, iclass 21, count 2 2006.285.11:02:07.70#ibcon#about to read 6, iclass 21, count 2 2006.285.11:02:07.70#ibcon#read 6, iclass 21, count 2 2006.285.11:02:07.70#ibcon#end of sib2, iclass 21, count 2 2006.285.11:02:07.70#ibcon#*mode == 0, iclass 21, count 2 2006.285.11:02:07.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.11:02:07.70#ibcon#[25=AT08-03\r\n] 2006.285.11:02:07.70#ibcon#*before write, iclass 21, count 2 2006.285.11:02:07.70#ibcon#enter sib2, iclass 21, count 2 2006.285.11:02:07.70#ibcon#flushed, iclass 21, count 2 2006.285.11:02:07.70#ibcon#about to write, iclass 21, count 2 2006.285.11:02:07.70#ibcon#wrote, iclass 21, count 2 2006.285.11:02:07.70#ibcon#about to read 3, iclass 21, count 2 2006.285.11:02:07.73#ibcon#read 3, iclass 21, count 2 2006.285.11:02:07.73#ibcon#about to read 4, iclass 21, count 2 2006.285.11:02:07.73#ibcon#read 4, iclass 21, count 2 2006.285.11:02:07.73#ibcon#about to read 5, iclass 21, count 2 2006.285.11:02:07.73#ibcon#read 5, iclass 21, count 2 2006.285.11:02:07.73#ibcon#about to read 6, iclass 21, count 2 2006.285.11:02:07.73#ibcon#read 6, iclass 21, count 2 2006.285.11:02:07.73#ibcon#end of sib2, iclass 21, count 2 2006.285.11:02:07.73#ibcon#*after write, iclass 21, count 2 2006.285.11:02:07.73#ibcon#*before return 0, iclass 21, count 2 2006.285.11:02:07.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:02:07.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:02:07.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.11:02:07.73#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:07.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:02:07.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:02:07.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:02:07.85#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:02:07.85#ibcon#first serial, iclass 21, count 0 2006.285.11:02:07.85#ibcon#enter sib2, iclass 21, count 0 2006.285.11:02:07.85#ibcon#flushed, iclass 21, count 0 2006.285.11:02:07.85#ibcon#about to write, iclass 21, count 0 2006.285.11:02:07.85#ibcon#wrote, iclass 21, count 0 2006.285.11:02:07.85#ibcon#about to read 3, iclass 21, count 0 2006.285.11:02:07.87#ibcon#read 3, iclass 21, count 0 2006.285.11:02:07.87#ibcon#about to read 4, iclass 21, count 0 2006.285.11:02:07.87#ibcon#read 4, iclass 21, count 0 2006.285.11:02:07.87#ibcon#about to read 5, iclass 21, count 0 2006.285.11:02:07.87#ibcon#read 5, iclass 21, count 0 2006.285.11:02:07.87#ibcon#about to read 6, iclass 21, count 0 2006.285.11:02:07.87#ibcon#read 6, iclass 21, count 0 2006.285.11:02:07.87#ibcon#end of sib2, iclass 21, count 0 2006.285.11:02:07.87#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:02:07.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:02:07.87#ibcon#[25=USB\r\n] 2006.285.11:02:07.87#ibcon#*before write, iclass 21, count 0 2006.285.11:02:07.87#ibcon#enter sib2, iclass 21, count 0 2006.285.11:02:07.87#ibcon#flushed, iclass 21, count 0 2006.285.11:02:07.87#ibcon#about to write, iclass 21, count 0 2006.285.11:02:07.87#ibcon#wrote, iclass 21, count 0 2006.285.11:02:07.87#ibcon#about to read 3, iclass 21, count 0 2006.285.11:02:07.90#ibcon#read 3, iclass 21, count 0 2006.285.11:02:07.90#ibcon#about to read 4, iclass 21, count 0 2006.285.11:02:07.90#ibcon#read 4, iclass 21, count 0 2006.285.11:02:07.90#ibcon#about to read 5, iclass 21, count 0 2006.285.11:02:07.90#ibcon#read 5, iclass 21, count 0 2006.285.11:02:07.90#ibcon#about to read 6, iclass 21, count 0 2006.285.11:02:07.90#ibcon#read 6, iclass 21, count 0 2006.285.11:02:07.90#ibcon#end of sib2, iclass 21, count 0 2006.285.11:02:07.90#ibcon#*after write, iclass 21, count 0 2006.285.11:02:07.90#ibcon#*before return 0, iclass 21, count 0 2006.285.11:02:07.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:02:07.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:02:07.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:02:07.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:02:07.90$vck44/vblo=1,629.99 2006.285.11:02:07.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.11:02:07.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.11:02:07.90#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:07.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:02:07.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:02:07.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:02:07.90#ibcon#enter wrdev, iclass 23, count 0 2006.285.11:02:07.90#ibcon#first serial, iclass 23, count 0 2006.285.11:02:07.90#ibcon#enter sib2, iclass 23, count 0 2006.285.11:02:07.90#ibcon#flushed, iclass 23, count 0 2006.285.11:02:07.90#ibcon#about to write, iclass 23, count 0 2006.285.11:02:07.90#ibcon#wrote, iclass 23, count 0 2006.285.11:02:07.90#ibcon#about to read 3, iclass 23, count 0 2006.285.11:02:07.92#ibcon#read 3, iclass 23, count 0 2006.285.11:02:07.92#ibcon#about to read 4, iclass 23, count 0 2006.285.11:02:07.92#ibcon#read 4, iclass 23, count 0 2006.285.11:02:07.92#ibcon#about to read 5, iclass 23, count 0 2006.285.11:02:07.92#ibcon#read 5, iclass 23, count 0 2006.285.11:02:07.92#ibcon#about to read 6, iclass 23, count 0 2006.285.11:02:07.92#ibcon#read 6, iclass 23, count 0 2006.285.11:02:07.92#ibcon#end of sib2, iclass 23, count 0 2006.285.11:02:07.92#ibcon#*mode == 0, iclass 23, count 0 2006.285.11:02:07.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.11:02:07.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:02:07.92#ibcon#*before write, iclass 23, count 0 2006.285.11:02:07.92#ibcon#enter sib2, iclass 23, count 0 2006.285.11:02:07.92#ibcon#flushed, iclass 23, count 0 2006.285.11:02:07.92#ibcon#about to write, iclass 23, count 0 2006.285.11:02:07.92#ibcon#wrote, iclass 23, count 0 2006.285.11:02:07.92#ibcon#about to read 3, iclass 23, count 0 2006.285.11:02:07.96#ibcon#read 3, iclass 23, count 0 2006.285.11:02:07.96#ibcon#about to read 4, iclass 23, count 0 2006.285.11:02:07.96#ibcon#read 4, iclass 23, count 0 2006.285.11:02:07.96#ibcon#about to read 5, iclass 23, count 0 2006.285.11:02:07.96#ibcon#read 5, iclass 23, count 0 2006.285.11:02:07.96#ibcon#about to read 6, iclass 23, count 0 2006.285.11:02:07.96#ibcon#read 6, iclass 23, count 0 2006.285.11:02:07.96#ibcon#end of sib2, iclass 23, count 0 2006.285.11:02:07.96#ibcon#*after write, iclass 23, count 0 2006.285.11:02:07.96#ibcon#*before return 0, iclass 23, count 0 2006.285.11:02:07.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:02:07.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:02:07.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.11:02:07.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.11:02:07.96$vck44/vb=1,4 2006.285.11:02:07.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.11:02:07.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.11:02:07.96#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:07.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:02:07.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:02:07.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:02:07.96#ibcon#enter wrdev, iclass 25, count 2 2006.285.11:02:07.96#ibcon#first serial, iclass 25, count 2 2006.285.11:02:07.96#ibcon#enter sib2, iclass 25, count 2 2006.285.11:02:07.96#ibcon#flushed, iclass 25, count 2 2006.285.11:02:07.96#ibcon#about to write, iclass 25, count 2 2006.285.11:02:07.96#ibcon#wrote, iclass 25, count 2 2006.285.11:02:07.96#ibcon#about to read 3, iclass 25, count 2 2006.285.11:02:07.98#ibcon#read 3, iclass 25, count 2 2006.285.11:02:07.98#ibcon#about to read 4, iclass 25, count 2 2006.285.11:02:07.98#ibcon#read 4, iclass 25, count 2 2006.285.11:02:07.98#ibcon#about to read 5, iclass 25, count 2 2006.285.11:02:07.98#ibcon#read 5, iclass 25, count 2 2006.285.11:02:07.98#ibcon#about to read 6, iclass 25, count 2 2006.285.11:02:07.98#ibcon#read 6, iclass 25, count 2 2006.285.11:02:07.98#ibcon#end of sib2, iclass 25, count 2 2006.285.11:02:07.98#ibcon#*mode == 0, iclass 25, count 2 2006.285.11:02:07.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.11:02:07.98#ibcon#[27=AT01-04\r\n] 2006.285.11:02:07.98#ibcon#*before write, iclass 25, count 2 2006.285.11:02:07.98#ibcon#enter sib2, iclass 25, count 2 2006.285.11:02:07.98#ibcon#flushed, iclass 25, count 2 2006.285.11:02:07.98#ibcon#about to write, iclass 25, count 2 2006.285.11:02:07.98#ibcon#wrote, iclass 25, count 2 2006.285.11:02:07.98#ibcon#about to read 3, iclass 25, count 2 2006.285.11:02:08.01#ibcon#read 3, iclass 25, count 2 2006.285.11:02:08.01#ibcon#about to read 4, iclass 25, count 2 2006.285.11:02:08.01#ibcon#read 4, iclass 25, count 2 2006.285.11:02:08.01#ibcon#about to read 5, iclass 25, count 2 2006.285.11:02:08.01#ibcon#read 5, iclass 25, count 2 2006.285.11:02:08.01#ibcon#about to read 6, iclass 25, count 2 2006.285.11:02:08.01#ibcon#read 6, iclass 25, count 2 2006.285.11:02:08.01#ibcon#end of sib2, iclass 25, count 2 2006.285.11:02:08.01#ibcon#*after write, iclass 25, count 2 2006.285.11:02:08.01#ibcon#*before return 0, iclass 25, count 2 2006.285.11:02:08.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:02:08.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:02:08.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.11:02:08.01#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:08.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:02:08.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:02:08.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:02:08.13#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:02:08.13#ibcon#first serial, iclass 25, count 0 2006.285.11:02:08.13#ibcon#enter sib2, iclass 25, count 0 2006.285.11:02:08.13#ibcon#flushed, iclass 25, count 0 2006.285.11:02:08.13#ibcon#about to write, iclass 25, count 0 2006.285.11:02:08.13#ibcon#wrote, iclass 25, count 0 2006.285.11:02:08.13#ibcon#about to read 3, iclass 25, count 0 2006.285.11:02:08.15#ibcon#read 3, iclass 25, count 0 2006.285.11:02:08.15#ibcon#about to read 4, iclass 25, count 0 2006.285.11:02:08.15#ibcon#read 4, iclass 25, count 0 2006.285.11:02:08.15#ibcon#about to read 5, iclass 25, count 0 2006.285.11:02:08.15#ibcon#read 5, iclass 25, count 0 2006.285.11:02:08.15#ibcon#about to read 6, iclass 25, count 0 2006.285.11:02:08.15#ibcon#read 6, iclass 25, count 0 2006.285.11:02:08.15#ibcon#end of sib2, iclass 25, count 0 2006.285.11:02:08.15#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:02:08.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:02:08.15#ibcon#[27=USB\r\n] 2006.285.11:02:08.15#ibcon#*before write, iclass 25, count 0 2006.285.11:02:08.15#ibcon#enter sib2, iclass 25, count 0 2006.285.11:02:08.15#ibcon#flushed, iclass 25, count 0 2006.285.11:02:08.15#ibcon#about to write, iclass 25, count 0 2006.285.11:02:08.15#ibcon#wrote, iclass 25, count 0 2006.285.11:02:08.15#ibcon#about to read 3, iclass 25, count 0 2006.285.11:02:08.18#ibcon#read 3, iclass 25, count 0 2006.285.11:02:08.18#ibcon#about to read 4, iclass 25, count 0 2006.285.11:02:08.18#ibcon#read 4, iclass 25, count 0 2006.285.11:02:08.18#ibcon#about to read 5, iclass 25, count 0 2006.285.11:02:08.18#ibcon#read 5, iclass 25, count 0 2006.285.11:02:08.18#ibcon#about to read 6, iclass 25, count 0 2006.285.11:02:08.18#ibcon#read 6, iclass 25, count 0 2006.285.11:02:08.18#ibcon#end of sib2, iclass 25, count 0 2006.285.11:02:08.18#ibcon#*after write, iclass 25, count 0 2006.285.11:02:08.18#ibcon#*before return 0, iclass 25, count 0 2006.285.11:02:08.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:02:08.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:02:08.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:02:08.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:02:08.18$vck44/vblo=2,634.99 2006.285.11:02:08.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.11:02:08.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.11:02:08.18#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:08.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:02:08.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:02:08.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:02:08.18#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:02:08.18#ibcon#first serial, iclass 27, count 0 2006.285.11:02:08.18#ibcon#enter sib2, iclass 27, count 0 2006.285.11:02:08.18#ibcon#flushed, iclass 27, count 0 2006.285.11:02:08.18#ibcon#about to write, iclass 27, count 0 2006.285.11:02:08.18#ibcon#wrote, iclass 27, count 0 2006.285.11:02:08.18#ibcon#about to read 3, iclass 27, count 0 2006.285.11:02:08.20#ibcon#read 3, iclass 27, count 0 2006.285.11:02:08.20#ibcon#about to read 4, iclass 27, count 0 2006.285.11:02:08.20#ibcon#read 4, iclass 27, count 0 2006.285.11:02:08.20#ibcon#about to read 5, iclass 27, count 0 2006.285.11:02:08.20#ibcon#read 5, iclass 27, count 0 2006.285.11:02:08.20#ibcon#about to read 6, iclass 27, count 0 2006.285.11:02:08.20#ibcon#read 6, iclass 27, count 0 2006.285.11:02:08.20#ibcon#end of sib2, iclass 27, count 0 2006.285.11:02:08.20#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:02:08.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:02:08.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:02:08.20#ibcon#*before write, iclass 27, count 0 2006.285.11:02:08.20#ibcon#enter sib2, iclass 27, count 0 2006.285.11:02:08.20#ibcon#flushed, iclass 27, count 0 2006.285.11:02:08.20#ibcon#about to write, iclass 27, count 0 2006.285.11:02:08.20#ibcon#wrote, iclass 27, count 0 2006.285.11:02:08.20#ibcon#about to read 3, iclass 27, count 0 2006.285.11:02:08.24#ibcon#read 3, iclass 27, count 0 2006.285.11:02:08.24#ibcon#about to read 4, iclass 27, count 0 2006.285.11:02:08.24#ibcon#read 4, iclass 27, count 0 2006.285.11:02:08.24#ibcon#about to read 5, iclass 27, count 0 2006.285.11:02:08.24#ibcon#read 5, iclass 27, count 0 2006.285.11:02:08.24#ibcon#about to read 6, iclass 27, count 0 2006.285.11:02:08.24#ibcon#read 6, iclass 27, count 0 2006.285.11:02:08.24#ibcon#end of sib2, iclass 27, count 0 2006.285.11:02:08.24#ibcon#*after write, iclass 27, count 0 2006.285.11:02:08.24#ibcon#*before return 0, iclass 27, count 0 2006.285.11:02:08.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:02:08.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:02:08.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:02:08.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:02:08.24$vck44/vb=2,5 2006.285.11:02:08.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.11:02:08.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.11:02:08.24#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:08.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:02:08.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:02:08.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:02:08.30#ibcon#enter wrdev, iclass 29, count 2 2006.285.11:02:08.30#ibcon#first serial, iclass 29, count 2 2006.285.11:02:08.30#ibcon#enter sib2, iclass 29, count 2 2006.285.11:02:08.30#ibcon#flushed, iclass 29, count 2 2006.285.11:02:08.30#ibcon#about to write, iclass 29, count 2 2006.285.11:02:08.30#ibcon#wrote, iclass 29, count 2 2006.285.11:02:08.30#ibcon#about to read 3, iclass 29, count 2 2006.285.11:02:08.32#ibcon#read 3, iclass 29, count 2 2006.285.11:02:08.32#ibcon#about to read 4, iclass 29, count 2 2006.285.11:02:08.32#ibcon#read 4, iclass 29, count 2 2006.285.11:02:08.32#ibcon#about to read 5, iclass 29, count 2 2006.285.11:02:08.32#ibcon#read 5, iclass 29, count 2 2006.285.11:02:08.32#ibcon#about to read 6, iclass 29, count 2 2006.285.11:02:08.32#ibcon#read 6, iclass 29, count 2 2006.285.11:02:08.32#ibcon#end of sib2, iclass 29, count 2 2006.285.11:02:08.32#ibcon#*mode == 0, iclass 29, count 2 2006.285.11:02:08.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.11:02:08.32#ibcon#[27=AT02-05\r\n] 2006.285.11:02:08.32#ibcon#*before write, iclass 29, count 2 2006.285.11:02:08.32#ibcon#enter sib2, iclass 29, count 2 2006.285.11:02:08.32#ibcon#flushed, iclass 29, count 2 2006.285.11:02:08.32#ibcon#about to write, iclass 29, count 2 2006.285.11:02:08.32#ibcon#wrote, iclass 29, count 2 2006.285.11:02:08.32#ibcon#about to read 3, iclass 29, count 2 2006.285.11:02:08.35#ibcon#read 3, iclass 29, count 2 2006.285.11:02:08.35#ibcon#about to read 4, iclass 29, count 2 2006.285.11:02:08.35#ibcon#read 4, iclass 29, count 2 2006.285.11:02:08.35#ibcon#about to read 5, iclass 29, count 2 2006.285.11:02:08.35#ibcon#read 5, iclass 29, count 2 2006.285.11:02:08.35#ibcon#about to read 6, iclass 29, count 2 2006.285.11:02:08.35#ibcon#read 6, iclass 29, count 2 2006.285.11:02:08.35#ibcon#end of sib2, iclass 29, count 2 2006.285.11:02:08.35#ibcon#*after write, iclass 29, count 2 2006.285.11:02:08.35#ibcon#*before return 0, iclass 29, count 2 2006.285.11:02:08.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:02:08.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:02:08.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.11:02:08.35#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:08.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:02:08.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:02:08.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:02:08.47#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:02:08.47#ibcon#first serial, iclass 29, count 0 2006.285.11:02:08.47#ibcon#enter sib2, iclass 29, count 0 2006.285.11:02:08.47#ibcon#flushed, iclass 29, count 0 2006.285.11:02:08.47#ibcon#about to write, iclass 29, count 0 2006.285.11:02:08.47#ibcon#wrote, iclass 29, count 0 2006.285.11:02:08.47#ibcon#about to read 3, iclass 29, count 0 2006.285.11:02:08.49#ibcon#read 3, iclass 29, count 0 2006.285.11:02:08.49#ibcon#about to read 4, iclass 29, count 0 2006.285.11:02:08.49#ibcon#read 4, iclass 29, count 0 2006.285.11:02:08.49#ibcon#about to read 5, iclass 29, count 0 2006.285.11:02:08.49#ibcon#read 5, iclass 29, count 0 2006.285.11:02:08.49#ibcon#about to read 6, iclass 29, count 0 2006.285.11:02:08.49#ibcon#read 6, iclass 29, count 0 2006.285.11:02:08.49#ibcon#end of sib2, iclass 29, count 0 2006.285.11:02:08.49#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:02:08.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:02:08.49#ibcon#[27=USB\r\n] 2006.285.11:02:08.49#ibcon#*before write, iclass 29, count 0 2006.285.11:02:08.49#ibcon#enter sib2, iclass 29, count 0 2006.285.11:02:08.49#ibcon#flushed, iclass 29, count 0 2006.285.11:02:08.49#ibcon#about to write, iclass 29, count 0 2006.285.11:02:08.49#ibcon#wrote, iclass 29, count 0 2006.285.11:02:08.49#ibcon#about to read 3, iclass 29, count 0 2006.285.11:02:08.52#ibcon#read 3, iclass 29, count 0 2006.285.11:02:08.52#ibcon#about to read 4, iclass 29, count 0 2006.285.11:02:08.52#ibcon#read 4, iclass 29, count 0 2006.285.11:02:08.52#ibcon#about to read 5, iclass 29, count 0 2006.285.11:02:08.52#ibcon#read 5, iclass 29, count 0 2006.285.11:02:08.52#ibcon#about to read 6, iclass 29, count 0 2006.285.11:02:08.52#ibcon#read 6, iclass 29, count 0 2006.285.11:02:08.52#ibcon#end of sib2, iclass 29, count 0 2006.285.11:02:08.52#ibcon#*after write, iclass 29, count 0 2006.285.11:02:08.52#ibcon#*before return 0, iclass 29, count 0 2006.285.11:02:08.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:02:08.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:02:08.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:02:08.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:02:08.52$vck44/vblo=3,649.99 2006.285.11:02:08.52#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.11:02:08.52#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.11:02:08.52#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:08.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:02:08.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:02:08.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:02:08.52#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:02:08.52#ibcon#first serial, iclass 31, count 0 2006.285.11:02:08.52#ibcon#enter sib2, iclass 31, count 0 2006.285.11:02:08.52#ibcon#flushed, iclass 31, count 0 2006.285.11:02:08.52#ibcon#about to write, iclass 31, count 0 2006.285.11:02:08.52#ibcon#wrote, iclass 31, count 0 2006.285.11:02:08.52#ibcon#about to read 3, iclass 31, count 0 2006.285.11:02:08.54#ibcon#read 3, iclass 31, count 0 2006.285.11:02:08.54#ibcon#about to read 4, iclass 31, count 0 2006.285.11:02:08.54#ibcon#read 4, iclass 31, count 0 2006.285.11:02:08.54#ibcon#about to read 5, iclass 31, count 0 2006.285.11:02:08.54#ibcon#read 5, iclass 31, count 0 2006.285.11:02:08.54#ibcon#about to read 6, iclass 31, count 0 2006.285.11:02:08.54#ibcon#read 6, iclass 31, count 0 2006.285.11:02:08.54#ibcon#end of sib2, iclass 31, count 0 2006.285.11:02:08.54#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:02:08.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:02:08.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:02:08.54#ibcon#*before write, iclass 31, count 0 2006.285.11:02:08.54#ibcon#enter sib2, iclass 31, count 0 2006.285.11:02:08.54#ibcon#flushed, iclass 31, count 0 2006.285.11:02:08.54#ibcon#about to write, iclass 31, count 0 2006.285.11:02:08.54#ibcon#wrote, iclass 31, count 0 2006.285.11:02:08.54#ibcon#about to read 3, iclass 31, count 0 2006.285.11:02:08.58#ibcon#read 3, iclass 31, count 0 2006.285.11:02:08.58#ibcon#about to read 4, iclass 31, count 0 2006.285.11:02:08.58#ibcon#read 4, iclass 31, count 0 2006.285.11:02:08.58#ibcon#about to read 5, iclass 31, count 0 2006.285.11:02:08.58#ibcon#read 5, iclass 31, count 0 2006.285.11:02:08.58#ibcon#about to read 6, iclass 31, count 0 2006.285.11:02:08.58#ibcon#read 6, iclass 31, count 0 2006.285.11:02:08.58#ibcon#end of sib2, iclass 31, count 0 2006.285.11:02:08.58#ibcon#*after write, iclass 31, count 0 2006.285.11:02:08.58#ibcon#*before return 0, iclass 31, count 0 2006.285.11:02:08.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:02:08.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:02:08.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:02:08.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:02:08.58$vck44/vb=3,4 2006.285.11:02:08.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.11:02:08.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.11:02:08.58#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:08.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:02:08.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:02:08.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:02:08.64#ibcon#enter wrdev, iclass 33, count 2 2006.285.11:02:08.64#ibcon#first serial, iclass 33, count 2 2006.285.11:02:08.64#ibcon#enter sib2, iclass 33, count 2 2006.285.11:02:08.64#ibcon#flushed, iclass 33, count 2 2006.285.11:02:08.64#ibcon#about to write, iclass 33, count 2 2006.285.11:02:08.64#ibcon#wrote, iclass 33, count 2 2006.285.11:02:08.64#ibcon#about to read 3, iclass 33, count 2 2006.285.11:02:08.66#ibcon#read 3, iclass 33, count 2 2006.285.11:02:08.66#ibcon#about to read 4, iclass 33, count 2 2006.285.11:02:08.66#ibcon#read 4, iclass 33, count 2 2006.285.11:02:08.66#ibcon#about to read 5, iclass 33, count 2 2006.285.11:02:08.66#ibcon#read 5, iclass 33, count 2 2006.285.11:02:08.66#ibcon#about to read 6, iclass 33, count 2 2006.285.11:02:08.66#ibcon#read 6, iclass 33, count 2 2006.285.11:02:08.66#ibcon#end of sib2, iclass 33, count 2 2006.285.11:02:08.66#ibcon#*mode == 0, iclass 33, count 2 2006.285.11:02:08.66#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.11:02:08.66#ibcon#[27=AT03-04\r\n] 2006.285.11:02:08.66#ibcon#*before write, iclass 33, count 2 2006.285.11:02:08.66#ibcon#enter sib2, iclass 33, count 2 2006.285.11:02:08.66#ibcon#flushed, iclass 33, count 2 2006.285.11:02:08.66#ibcon#about to write, iclass 33, count 2 2006.285.11:02:08.66#ibcon#wrote, iclass 33, count 2 2006.285.11:02:08.66#ibcon#about to read 3, iclass 33, count 2 2006.285.11:02:08.69#ibcon#read 3, iclass 33, count 2 2006.285.11:02:08.69#ibcon#about to read 4, iclass 33, count 2 2006.285.11:02:08.69#ibcon#read 4, iclass 33, count 2 2006.285.11:02:08.69#ibcon#about to read 5, iclass 33, count 2 2006.285.11:02:08.69#ibcon#read 5, iclass 33, count 2 2006.285.11:02:08.69#ibcon#about to read 6, iclass 33, count 2 2006.285.11:02:08.69#ibcon#read 6, iclass 33, count 2 2006.285.11:02:08.69#ibcon#end of sib2, iclass 33, count 2 2006.285.11:02:08.69#ibcon#*after write, iclass 33, count 2 2006.285.11:02:08.69#ibcon#*before return 0, iclass 33, count 2 2006.285.11:02:08.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:02:08.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:02:08.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.11:02:08.69#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:08.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:02:08.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:02:08.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:02:08.81#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:02:08.81#ibcon#first serial, iclass 33, count 0 2006.285.11:02:08.81#ibcon#enter sib2, iclass 33, count 0 2006.285.11:02:08.81#ibcon#flushed, iclass 33, count 0 2006.285.11:02:08.81#ibcon#about to write, iclass 33, count 0 2006.285.11:02:08.81#ibcon#wrote, iclass 33, count 0 2006.285.11:02:08.81#ibcon#about to read 3, iclass 33, count 0 2006.285.11:02:08.83#ibcon#read 3, iclass 33, count 0 2006.285.11:02:08.83#ibcon#about to read 4, iclass 33, count 0 2006.285.11:02:08.83#ibcon#read 4, iclass 33, count 0 2006.285.11:02:08.83#ibcon#about to read 5, iclass 33, count 0 2006.285.11:02:08.83#ibcon#read 5, iclass 33, count 0 2006.285.11:02:08.83#ibcon#about to read 6, iclass 33, count 0 2006.285.11:02:08.83#ibcon#read 6, iclass 33, count 0 2006.285.11:02:08.83#ibcon#end of sib2, iclass 33, count 0 2006.285.11:02:08.83#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:02:08.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:02:08.83#ibcon#[27=USB\r\n] 2006.285.11:02:08.83#ibcon#*before write, iclass 33, count 0 2006.285.11:02:08.83#ibcon#enter sib2, iclass 33, count 0 2006.285.11:02:08.83#ibcon#flushed, iclass 33, count 0 2006.285.11:02:08.83#ibcon#about to write, iclass 33, count 0 2006.285.11:02:08.83#ibcon#wrote, iclass 33, count 0 2006.285.11:02:08.83#ibcon#about to read 3, iclass 33, count 0 2006.285.11:02:08.86#ibcon#read 3, iclass 33, count 0 2006.285.11:02:08.86#ibcon#about to read 4, iclass 33, count 0 2006.285.11:02:08.86#ibcon#read 4, iclass 33, count 0 2006.285.11:02:08.86#ibcon#about to read 5, iclass 33, count 0 2006.285.11:02:08.86#ibcon#read 5, iclass 33, count 0 2006.285.11:02:08.86#ibcon#about to read 6, iclass 33, count 0 2006.285.11:02:08.86#ibcon#read 6, iclass 33, count 0 2006.285.11:02:08.86#ibcon#end of sib2, iclass 33, count 0 2006.285.11:02:08.86#ibcon#*after write, iclass 33, count 0 2006.285.11:02:08.86#ibcon#*before return 0, iclass 33, count 0 2006.285.11:02:08.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:02:08.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:02:08.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:02:08.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:02:08.86$vck44/vblo=4,679.99 2006.285.11:02:08.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.11:02:08.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.11:02:08.86#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:08.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:02:08.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:02:08.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:02:08.86#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:02:08.86#ibcon#first serial, iclass 35, count 0 2006.285.11:02:08.86#ibcon#enter sib2, iclass 35, count 0 2006.285.11:02:08.86#ibcon#flushed, iclass 35, count 0 2006.285.11:02:08.86#ibcon#about to write, iclass 35, count 0 2006.285.11:02:08.86#ibcon#wrote, iclass 35, count 0 2006.285.11:02:08.86#ibcon#about to read 3, iclass 35, count 0 2006.285.11:02:08.88#ibcon#read 3, iclass 35, count 0 2006.285.11:02:08.88#ibcon#about to read 4, iclass 35, count 0 2006.285.11:02:08.88#ibcon#read 4, iclass 35, count 0 2006.285.11:02:08.88#ibcon#about to read 5, iclass 35, count 0 2006.285.11:02:08.88#ibcon#read 5, iclass 35, count 0 2006.285.11:02:08.88#ibcon#about to read 6, iclass 35, count 0 2006.285.11:02:08.88#ibcon#read 6, iclass 35, count 0 2006.285.11:02:08.88#ibcon#end of sib2, iclass 35, count 0 2006.285.11:02:08.88#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:02:08.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:02:08.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:02:08.88#ibcon#*before write, iclass 35, count 0 2006.285.11:02:08.88#ibcon#enter sib2, iclass 35, count 0 2006.285.11:02:08.88#ibcon#flushed, iclass 35, count 0 2006.285.11:02:08.88#ibcon#about to write, iclass 35, count 0 2006.285.11:02:08.88#ibcon#wrote, iclass 35, count 0 2006.285.11:02:08.88#ibcon#about to read 3, iclass 35, count 0 2006.285.11:02:08.92#ibcon#read 3, iclass 35, count 0 2006.285.11:02:08.92#ibcon#about to read 4, iclass 35, count 0 2006.285.11:02:08.92#ibcon#read 4, iclass 35, count 0 2006.285.11:02:08.92#ibcon#about to read 5, iclass 35, count 0 2006.285.11:02:08.92#ibcon#read 5, iclass 35, count 0 2006.285.11:02:08.92#ibcon#about to read 6, iclass 35, count 0 2006.285.11:02:08.92#ibcon#read 6, iclass 35, count 0 2006.285.11:02:08.92#ibcon#end of sib2, iclass 35, count 0 2006.285.11:02:08.92#ibcon#*after write, iclass 35, count 0 2006.285.11:02:08.92#ibcon#*before return 0, iclass 35, count 0 2006.285.11:02:08.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:02:08.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:02:08.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:02:08.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:02:08.92$vck44/vb=4,5 2006.285.11:02:08.92#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.11:02:08.92#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.11:02:08.92#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:08.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:02:08.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:02:08.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:02:08.98#ibcon#enter wrdev, iclass 37, count 2 2006.285.11:02:08.98#ibcon#first serial, iclass 37, count 2 2006.285.11:02:08.98#ibcon#enter sib2, iclass 37, count 2 2006.285.11:02:08.98#ibcon#flushed, iclass 37, count 2 2006.285.11:02:08.98#ibcon#about to write, iclass 37, count 2 2006.285.11:02:08.98#ibcon#wrote, iclass 37, count 2 2006.285.11:02:08.98#ibcon#about to read 3, iclass 37, count 2 2006.285.11:02:09.00#ibcon#read 3, iclass 37, count 2 2006.285.11:02:09.00#ibcon#about to read 4, iclass 37, count 2 2006.285.11:02:09.00#ibcon#read 4, iclass 37, count 2 2006.285.11:02:09.00#ibcon#about to read 5, iclass 37, count 2 2006.285.11:02:09.00#ibcon#read 5, iclass 37, count 2 2006.285.11:02:09.00#ibcon#about to read 6, iclass 37, count 2 2006.285.11:02:09.00#ibcon#read 6, iclass 37, count 2 2006.285.11:02:09.00#ibcon#end of sib2, iclass 37, count 2 2006.285.11:02:09.00#ibcon#*mode == 0, iclass 37, count 2 2006.285.11:02:09.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.11:02:09.00#ibcon#[27=AT04-05\r\n] 2006.285.11:02:09.00#ibcon#*before write, iclass 37, count 2 2006.285.11:02:09.00#ibcon#enter sib2, iclass 37, count 2 2006.285.11:02:09.00#ibcon#flushed, iclass 37, count 2 2006.285.11:02:09.00#ibcon#about to write, iclass 37, count 2 2006.285.11:02:09.00#ibcon#wrote, iclass 37, count 2 2006.285.11:02:09.00#ibcon#about to read 3, iclass 37, count 2 2006.285.11:02:09.03#ibcon#read 3, iclass 37, count 2 2006.285.11:02:09.03#ibcon#about to read 4, iclass 37, count 2 2006.285.11:02:09.03#ibcon#read 4, iclass 37, count 2 2006.285.11:02:09.03#ibcon#about to read 5, iclass 37, count 2 2006.285.11:02:09.03#ibcon#read 5, iclass 37, count 2 2006.285.11:02:09.03#ibcon#about to read 6, iclass 37, count 2 2006.285.11:02:09.03#ibcon#read 6, iclass 37, count 2 2006.285.11:02:09.03#ibcon#end of sib2, iclass 37, count 2 2006.285.11:02:09.03#ibcon#*after write, iclass 37, count 2 2006.285.11:02:09.03#ibcon#*before return 0, iclass 37, count 2 2006.285.11:02:09.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:02:09.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:02:09.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.11:02:09.03#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:09.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:02:09.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:02:09.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:02:09.15#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:02:09.15#ibcon#first serial, iclass 37, count 0 2006.285.11:02:09.15#ibcon#enter sib2, iclass 37, count 0 2006.285.11:02:09.15#ibcon#flushed, iclass 37, count 0 2006.285.11:02:09.15#ibcon#about to write, iclass 37, count 0 2006.285.11:02:09.15#ibcon#wrote, iclass 37, count 0 2006.285.11:02:09.15#ibcon#about to read 3, iclass 37, count 0 2006.285.11:02:09.17#ibcon#read 3, iclass 37, count 0 2006.285.11:02:09.17#ibcon#about to read 4, iclass 37, count 0 2006.285.11:02:09.17#ibcon#read 4, iclass 37, count 0 2006.285.11:02:09.17#ibcon#about to read 5, iclass 37, count 0 2006.285.11:02:09.17#ibcon#read 5, iclass 37, count 0 2006.285.11:02:09.17#ibcon#about to read 6, iclass 37, count 0 2006.285.11:02:09.17#ibcon#read 6, iclass 37, count 0 2006.285.11:02:09.17#ibcon#end of sib2, iclass 37, count 0 2006.285.11:02:09.17#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:02:09.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:02:09.17#ibcon#[27=USB\r\n] 2006.285.11:02:09.17#ibcon#*before write, iclass 37, count 0 2006.285.11:02:09.17#ibcon#enter sib2, iclass 37, count 0 2006.285.11:02:09.17#ibcon#flushed, iclass 37, count 0 2006.285.11:02:09.17#ibcon#about to write, iclass 37, count 0 2006.285.11:02:09.17#ibcon#wrote, iclass 37, count 0 2006.285.11:02:09.17#ibcon#about to read 3, iclass 37, count 0 2006.285.11:02:09.20#ibcon#read 3, iclass 37, count 0 2006.285.11:02:09.20#ibcon#about to read 4, iclass 37, count 0 2006.285.11:02:09.20#ibcon#read 4, iclass 37, count 0 2006.285.11:02:09.20#ibcon#about to read 5, iclass 37, count 0 2006.285.11:02:09.20#ibcon#read 5, iclass 37, count 0 2006.285.11:02:09.20#ibcon#about to read 6, iclass 37, count 0 2006.285.11:02:09.20#ibcon#read 6, iclass 37, count 0 2006.285.11:02:09.20#ibcon#end of sib2, iclass 37, count 0 2006.285.11:02:09.20#ibcon#*after write, iclass 37, count 0 2006.285.11:02:09.20#ibcon#*before return 0, iclass 37, count 0 2006.285.11:02:09.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:02:09.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:02:09.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:02:09.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:02:09.20$vck44/vblo=5,709.99 2006.285.11:02:09.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.11:02:09.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.11:02:09.20#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:09.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:02:09.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:02:09.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:02:09.20#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:02:09.20#ibcon#first serial, iclass 39, count 0 2006.285.11:02:09.20#ibcon#enter sib2, iclass 39, count 0 2006.285.11:02:09.20#ibcon#flushed, iclass 39, count 0 2006.285.11:02:09.20#ibcon#about to write, iclass 39, count 0 2006.285.11:02:09.20#ibcon#wrote, iclass 39, count 0 2006.285.11:02:09.20#ibcon#about to read 3, iclass 39, count 0 2006.285.11:02:09.22#ibcon#read 3, iclass 39, count 0 2006.285.11:02:09.22#ibcon#about to read 4, iclass 39, count 0 2006.285.11:02:09.22#ibcon#read 4, iclass 39, count 0 2006.285.11:02:09.22#ibcon#about to read 5, iclass 39, count 0 2006.285.11:02:09.22#ibcon#read 5, iclass 39, count 0 2006.285.11:02:09.22#ibcon#about to read 6, iclass 39, count 0 2006.285.11:02:09.22#ibcon#read 6, iclass 39, count 0 2006.285.11:02:09.22#ibcon#end of sib2, iclass 39, count 0 2006.285.11:02:09.22#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:02:09.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:02:09.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:02:09.22#ibcon#*before write, iclass 39, count 0 2006.285.11:02:09.22#ibcon#enter sib2, iclass 39, count 0 2006.285.11:02:09.22#ibcon#flushed, iclass 39, count 0 2006.285.11:02:09.22#ibcon#about to write, iclass 39, count 0 2006.285.11:02:09.22#ibcon#wrote, iclass 39, count 0 2006.285.11:02:09.22#ibcon#about to read 3, iclass 39, count 0 2006.285.11:02:09.26#ibcon#read 3, iclass 39, count 0 2006.285.11:02:09.26#ibcon#about to read 4, iclass 39, count 0 2006.285.11:02:09.26#ibcon#read 4, iclass 39, count 0 2006.285.11:02:09.26#ibcon#about to read 5, iclass 39, count 0 2006.285.11:02:09.26#ibcon#read 5, iclass 39, count 0 2006.285.11:02:09.26#ibcon#about to read 6, iclass 39, count 0 2006.285.11:02:09.26#ibcon#read 6, iclass 39, count 0 2006.285.11:02:09.26#ibcon#end of sib2, iclass 39, count 0 2006.285.11:02:09.26#ibcon#*after write, iclass 39, count 0 2006.285.11:02:09.26#ibcon#*before return 0, iclass 39, count 0 2006.285.11:02:09.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:02:09.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:02:09.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:02:09.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:02:09.26$vck44/vb=5,4 2006.285.11:02:09.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.11:02:09.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.11:02:09.26#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:09.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:02:09.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:02:09.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:02:09.32#ibcon#enter wrdev, iclass 3, count 2 2006.285.11:02:09.32#ibcon#first serial, iclass 3, count 2 2006.285.11:02:09.32#ibcon#enter sib2, iclass 3, count 2 2006.285.11:02:09.32#ibcon#flushed, iclass 3, count 2 2006.285.11:02:09.32#ibcon#about to write, iclass 3, count 2 2006.285.11:02:09.32#ibcon#wrote, iclass 3, count 2 2006.285.11:02:09.32#ibcon#about to read 3, iclass 3, count 2 2006.285.11:02:09.34#ibcon#read 3, iclass 3, count 2 2006.285.11:02:09.34#ibcon#about to read 4, iclass 3, count 2 2006.285.11:02:09.34#ibcon#read 4, iclass 3, count 2 2006.285.11:02:09.34#ibcon#about to read 5, iclass 3, count 2 2006.285.11:02:09.34#ibcon#read 5, iclass 3, count 2 2006.285.11:02:09.34#ibcon#about to read 6, iclass 3, count 2 2006.285.11:02:09.34#ibcon#read 6, iclass 3, count 2 2006.285.11:02:09.34#ibcon#end of sib2, iclass 3, count 2 2006.285.11:02:09.34#ibcon#*mode == 0, iclass 3, count 2 2006.285.11:02:09.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.11:02:09.34#ibcon#[27=AT05-04\r\n] 2006.285.11:02:09.34#ibcon#*before write, iclass 3, count 2 2006.285.11:02:09.34#ibcon#enter sib2, iclass 3, count 2 2006.285.11:02:09.34#ibcon#flushed, iclass 3, count 2 2006.285.11:02:09.34#ibcon#about to write, iclass 3, count 2 2006.285.11:02:09.34#ibcon#wrote, iclass 3, count 2 2006.285.11:02:09.34#ibcon#about to read 3, iclass 3, count 2 2006.285.11:02:09.37#ibcon#read 3, iclass 3, count 2 2006.285.11:02:09.37#ibcon#about to read 4, iclass 3, count 2 2006.285.11:02:09.37#ibcon#read 4, iclass 3, count 2 2006.285.11:02:09.37#ibcon#about to read 5, iclass 3, count 2 2006.285.11:02:09.37#ibcon#read 5, iclass 3, count 2 2006.285.11:02:09.37#ibcon#about to read 6, iclass 3, count 2 2006.285.11:02:09.37#ibcon#read 6, iclass 3, count 2 2006.285.11:02:09.37#ibcon#end of sib2, iclass 3, count 2 2006.285.11:02:09.37#ibcon#*after write, iclass 3, count 2 2006.285.11:02:09.37#ibcon#*before return 0, iclass 3, count 2 2006.285.11:02:09.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:02:09.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:02:09.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.11:02:09.37#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:09.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:02:09.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:02:09.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:02:09.49#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:02:09.49#ibcon#first serial, iclass 3, count 0 2006.285.11:02:09.49#ibcon#enter sib2, iclass 3, count 0 2006.285.11:02:09.49#ibcon#flushed, iclass 3, count 0 2006.285.11:02:09.49#ibcon#about to write, iclass 3, count 0 2006.285.11:02:09.49#ibcon#wrote, iclass 3, count 0 2006.285.11:02:09.49#ibcon#about to read 3, iclass 3, count 0 2006.285.11:02:09.51#ibcon#read 3, iclass 3, count 0 2006.285.11:02:09.51#ibcon#about to read 4, iclass 3, count 0 2006.285.11:02:09.51#ibcon#read 4, iclass 3, count 0 2006.285.11:02:09.51#ibcon#about to read 5, iclass 3, count 0 2006.285.11:02:09.51#ibcon#read 5, iclass 3, count 0 2006.285.11:02:09.51#ibcon#about to read 6, iclass 3, count 0 2006.285.11:02:09.51#ibcon#read 6, iclass 3, count 0 2006.285.11:02:09.51#ibcon#end of sib2, iclass 3, count 0 2006.285.11:02:09.51#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:02:09.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:02:09.51#ibcon#[27=USB\r\n] 2006.285.11:02:09.51#ibcon#*before write, iclass 3, count 0 2006.285.11:02:09.51#ibcon#enter sib2, iclass 3, count 0 2006.285.11:02:09.51#ibcon#flushed, iclass 3, count 0 2006.285.11:02:09.51#ibcon#about to write, iclass 3, count 0 2006.285.11:02:09.51#ibcon#wrote, iclass 3, count 0 2006.285.11:02:09.51#ibcon#about to read 3, iclass 3, count 0 2006.285.11:02:09.54#ibcon#read 3, iclass 3, count 0 2006.285.11:02:09.54#ibcon#about to read 4, iclass 3, count 0 2006.285.11:02:09.54#ibcon#read 4, iclass 3, count 0 2006.285.11:02:09.54#ibcon#about to read 5, iclass 3, count 0 2006.285.11:02:09.54#ibcon#read 5, iclass 3, count 0 2006.285.11:02:09.54#ibcon#about to read 6, iclass 3, count 0 2006.285.11:02:09.54#ibcon#read 6, iclass 3, count 0 2006.285.11:02:09.54#ibcon#end of sib2, iclass 3, count 0 2006.285.11:02:09.54#ibcon#*after write, iclass 3, count 0 2006.285.11:02:09.54#ibcon#*before return 0, iclass 3, count 0 2006.285.11:02:09.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:02:09.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:02:09.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:02:09.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:02:09.54$vck44/vblo=6,719.99 2006.285.11:02:09.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.11:02:09.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.11:02:09.54#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:09.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:02:09.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:02:09.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:02:09.54#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:02:09.54#ibcon#first serial, iclass 5, count 0 2006.285.11:02:09.54#ibcon#enter sib2, iclass 5, count 0 2006.285.11:02:09.54#ibcon#flushed, iclass 5, count 0 2006.285.11:02:09.54#ibcon#about to write, iclass 5, count 0 2006.285.11:02:09.54#ibcon#wrote, iclass 5, count 0 2006.285.11:02:09.54#ibcon#about to read 3, iclass 5, count 0 2006.285.11:02:09.56#ibcon#read 3, iclass 5, count 0 2006.285.11:02:09.56#ibcon#about to read 4, iclass 5, count 0 2006.285.11:02:09.56#ibcon#read 4, iclass 5, count 0 2006.285.11:02:09.56#ibcon#about to read 5, iclass 5, count 0 2006.285.11:02:09.56#ibcon#read 5, iclass 5, count 0 2006.285.11:02:09.56#ibcon#about to read 6, iclass 5, count 0 2006.285.11:02:09.56#ibcon#read 6, iclass 5, count 0 2006.285.11:02:09.56#ibcon#end of sib2, iclass 5, count 0 2006.285.11:02:09.56#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:02:09.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:02:09.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:02:09.56#ibcon#*before write, iclass 5, count 0 2006.285.11:02:09.56#ibcon#enter sib2, iclass 5, count 0 2006.285.11:02:09.56#ibcon#flushed, iclass 5, count 0 2006.285.11:02:09.56#ibcon#about to write, iclass 5, count 0 2006.285.11:02:09.56#ibcon#wrote, iclass 5, count 0 2006.285.11:02:09.56#ibcon#about to read 3, iclass 5, count 0 2006.285.11:02:09.60#ibcon#read 3, iclass 5, count 0 2006.285.11:02:09.60#ibcon#about to read 4, iclass 5, count 0 2006.285.11:02:09.60#ibcon#read 4, iclass 5, count 0 2006.285.11:02:09.60#ibcon#about to read 5, iclass 5, count 0 2006.285.11:02:09.60#ibcon#read 5, iclass 5, count 0 2006.285.11:02:09.60#ibcon#about to read 6, iclass 5, count 0 2006.285.11:02:09.60#ibcon#read 6, iclass 5, count 0 2006.285.11:02:09.60#ibcon#end of sib2, iclass 5, count 0 2006.285.11:02:09.60#ibcon#*after write, iclass 5, count 0 2006.285.11:02:09.60#ibcon#*before return 0, iclass 5, count 0 2006.285.11:02:09.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:02:09.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:02:09.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:02:09.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:02:09.60$vck44/vb=6,3 2006.285.11:02:09.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.11:02:09.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.11:02:09.60#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:09.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:02:09.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:02:09.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:02:09.66#ibcon#enter wrdev, iclass 7, count 2 2006.285.11:02:09.66#ibcon#first serial, iclass 7, count 2 2006.285.11:02:09.66#ibcon#enter sib2, iclass 7, count 2 2006.285.11:02:09.66#ibcon#flushed, iclass 7, count 2 2006.285.11:02:09.66#ibcon#about to write, iclass 7, count 2 2006.285.11:02:09.66#ibcon#wrote, iclass 7, count 2 2006.285.11:02:09.66#ibcon#about to read 3, iclass 7, count 2 2006.285.11:02:09.68#ibcon#read 3, iclass 7, count 2 2006.285.11:02:09.68#ibcon#about to read 4, iclass 7, count 2 2006.285.11:02:09.68#ibcon#read 4, iclass 7, count 2 2006.285.11:02:09.68#ibcon#about to read 5, iclass 7, count 2 2006.285.11:02:09.68#ibcon#read 5, iclass 7, count 2 2006.285.11:02:09.68#ibcon#about to read 6, iclass 7, count 2 2006.285.11:02:09.68#ibcon#read 6, iclass 7, count 2 2006.285.11:02:09.68#ibcon#end of sib2, iclass 7, count 2 2006.285.11:02:09.68#ibcon#*mode == 0, iclass 7, count 2 2006.285.11:02:09.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.11:02:09.68#ibcon#[27=AT06-03\r\n] 2006.285.11:02:09.68#ibcon#*before write, iclass 7, count 2 2006.285.11:02:09.68#ibcon#enter sib2, iclass 7, count 2 2006.285.11:02:09.68#ibcon#flushed, iclass 7, count 2 2006.285.11:02:09.68#ibcon#about to write, iclass 7, count 2 2006.285.11:02:09.68#ibcon#wrote, iclass 7, count 2 2006.285.11:02:09.68#ibcon#about to read 3, iclass 7, count 2 2006.285.11:02:09.71#ibcon#read 3, iclass 7, count 2 2006.285.11:02:09.71#ibcon#about to read 4, iclass 7, count 2 2006.285.11:02:09.71#ibcon#read 4, iclass 7, count 2 2006.285.11:02:09.71#ibcon#about to read 5, iclass 7, count 2 2006.285.11:02:09.71#ibcon#read 5, iclass 7, count 2 2006.285.11:02:09.71#ibcon#about to read 6, iclass 7, count 2 2006.285.11:02:09.71#ibcon#read 6, iclass 7, count 2 2006.285.11:02:09.71#ibcon#end of sib2, iclass 7, count 2 2006.285.11:02:09.71#ibcon#*after write, iclass 7, count 2 2006.285.11:02:09.71#ibcon#*before return 0, iclass 7, count 2 2006.285.11:02:09.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:02:09.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:02:09.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.11:02:09.71#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:09.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:02:09.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:02:09.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:02:09.83#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:02:09.83#ibcon#first serial, iclass 7, count 0 2006.285.11:02:09.83#ibcon#enter sib2, iclass 7, count 0 2006.285.11:02:09.83#ibcon#flushed, iclass 7, count 0 2006.285.11:02:09.83#ibcon#about to write, iclass 7, count 0 2006.285.11:02:09.83#ibcon#wrote, iclass 7, count 0 2006.285.11:02:09.83#ibcon#about to read 3, iclass 7, count 0 2006.285.11:02:09.85#ibcon#read 3, iclass 7, count 0 2006.285.11:02:09.85#ibcon#about to read 4, iclass 7, count 0 2006.285.11:02:09.85#ibcon#read 4, iclass 7, count 0 2006.285.11:02:09.85#ibcon#about to read 5, iclass 7, count 0 2006.285.11:02:09.85#ibcon#read 5, iclass 7, count 0 2006.285.11:02:09.85#ibcon#about to read 6, iclass 7, count 0 2006.285.11:02:09.85#ibcon#read 6, iclass 7, count 0 2006.285.11:02:09.85#ibcon#end of sib2, iclass 7, count 0 2006.285.11:02:09.85#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:02:09.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:02:09.85#ibcon#[27=USB\r\n] 2006.285.11:02:09.85#ibcon#*before write, iclass 7, count 0 2006.285.11:02:09.85#ibcon#enter sib2, iclass 7, count 0 2006.285.11:02:09.85#ibcon#flushed, iclass 7, count 0 2006.285.11:02:09.85#ibcon#about to write, iclass 7, count 0 2006.285.11:02:09.85#ibcon#wrote, iclass 7, count 0 2006.285.11:02:09.85#ibcon#about to read 3, iclass 7, count 0 2006.285.11:02:09.88#ibcon#read 3, iclass 7, count 0 2006.285.11:02:09.88#ibcon#about to read 4, iclass 7, count 0 2006.285.11:02:09.88#ibcon#read 4, iclass 7, count 0 2006.285.11:02:09.88#ibcon#about to read 5, iclass 7, count 0 2006.285.11:02:09.88#ibcon#read 5, iclass 7, count 0 2006.285.11:02:09.88#ibcon#about to read 6, iclass 7, count 0 2006.285.11:02:09.88#ibcon#read 6, iclass 7, count 0 2006.285.11:02:09.88#ibcon#end of sib2, iclass 7, count 0 2006.285.11:02:09.88#ibcon#*after write, iclass 7, count 0 2006.285.11:02:09.88#ibcon#*before return 0, iclass 7, count 0 2006.285.11:02:09.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:02:09.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:02:09.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:02:09.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:02:09.88$vck44/vblo=7,734.99 2006.285.11:02:09.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.11:02:09.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.11:02:09.88#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:09.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:02:09.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:02:09.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:02:09.88#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:02:09.88#ibcon#first serial, iclass 11, count 0 2006.285.11:02:09.88#ibcon#enter sib2, iclass 11, count 0 2006.285.11:02:09.88#ibcon#flushed, iclass 11, count 0 2006.285.11:02:09.88#ibcon#about to write, iclass 11, count 0 2006.285.11:02:09.88#ibcon#wrote, iclass 11, count 0 2006.285.11:02:09.88#ibcon#about to read 3, iclass 11, count 0 2006.285.11:02:09.90#ibcon#read 3, iclass 11, count 0 2006.285.11:02:09.90#ibcon#about to read 4, iclass 11, count 0 2006.285.11:02:09.90#ibcon#read 4, iclass 11, count 0 2006.285.11:02:09.90#ibcon#about to read 5, iclass 11, count 0 2006.285.11:02:09.90#ibcon#read 5, iclass 11, count 0 2006.285.11:02:09.90#ibcon#about to read 6, iclass 11, count 0 2006.285.11:02:09.90#ibcon#read 6, iclass 11, count 0 2006.285.11:02:09.90#ibcon#end of sib2, iclass 11, count 0 2006.285.11:02:09.90#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:02:09.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:02:09.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:02:09.90#ibcon#*before write, iclass 11, count 0 2006.285.11:02:09.90#ibcon#enter sib2, iclass 11, count 0 2006.285.11:02:09.90#ibcon#flushed, iclass 11, count 0 2006.285.11:02:09.90#ibcon#about to write, iclass 11, count 0 2006.285.11:02:09.90#ibcon#wrote, iclass 11, count 0 2006.285.11:02:09.90#ibcon#about to read 3, iclass 11, count 0 2006.285.11:02:09.94#ibcon#read 3, iclass 11, count 0 2006.285.11:02:09.94#ibcon#about to read 4, iclass 11, count 0 2006.285.11:02:09.94#ibcon#read 4, iclass 11, count 0 2006.285.11:02:09.94#ibcon#about to read 5, iclass 11, count 0 2006.285.11:02:09.94#ibcon#read 5, iclass 11, count 0 2006.285.11:02:09.94#ibcon#about to read 6, iclass 11, count 0 2006.285.11:02:09.94#ibcon#read 6, iclass 11, count 0 2006.285.11:02:09.94#ibcon#end of sib2, iclass 11, count 0 2006.285.11:02:09.94#ibcon#*after write, iclass 11, count 0 2006.285.11:02:09.94#ibcon#*before return 0, iclass 11, count 0 2006.285.11:02:09.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:02:09.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:02:09.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:02:09.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:02:09.94$vck44/vb=7,4 2006.285.11:02:09.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.11:02:09.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.11:02:09.94#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:09.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:02:10.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:02:10.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:02:10.00#ibcon#enter wrdev, iclass 13, count 2 2006.285.11:02:10.00#ibcon#first serial, iclass 13, count 2 2006.285.11:02:10.00#ibcon#enter sib2, iclass 13, count 2 2006.285.11:02:10.00#ibcon#flushed, iclass 13, count 2 2006.285.11:02:10.00#ibcon#about to write, iclass 13, count 2 2006.285.11:02:10.00#ibcon#wrote, iclass 13, count 2 2006.285.11:02:10.00#ibcon#about to read 3, iclass 13, count 2 2006.285.11:02:10.02#ibcon#read 3, iclass 13, count 2 2006.285.11:02:10.02#ibcon#about to read 4, iclass 13, count 2 2006.285.11:02:10.02#ibcon#read 4, iclass 13, count 2 2006.285.11:02:10.02#ibcon#about to read 5, iclass 13, count 2 2006.285.11:02:10.02#ibcon#read 5, iclass 13, count 2 2006.285.11:02:10.02#ibcon#about to read 6, iclass 13, count 2 2006.285.11:02:10.02#ibcon#read 6, iclass 13, count 2 2006.285.11:02:10.02#ibcon#end of sib2, iclass 13, count 2 2006.285.11:02:10.02#ibcon#*mode == 0, iclass 13, count 2 2006.285.11:02:10.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.11:02:10.02#ibcon#[27=AT07-04\r\n] 2006.285.11:02:10.02#ibcon#*before write, iclass 13, count 2 2006.285.11:02:10.02#ibcon#enter sib2, iclass 13, count 2 2006.285.11:02:10.02#ibcon#flushed, iclass 13, count 2 2006.285.11:02:10.02#ibcon#about to write, iclass 13, count 2 2006.285.11:02:10.02#ibcon#wrote, iclass 13, count 2 2006.285.11:02:10.02#ibcon#about to read 3, iclass 13, count 2 2006.285.11:02:10.05#ibcon#read 3, iclass 13, count 2 2006.285.11:02:10.05#ibcon#about to read 4, iclass 13, count 2 2006.285.11:02:10.05#ibcon#read 4, iclass 13, count 2 2006.285.11:02:10.05#ibcon#about to read 5, iclass 13, count 2 2006.285.11:02:10.05#ibcon#read 5, iclass 13, count 2 2006.285.11:02:10.05#ibcon#about to read 6, iclass 13, count 2 2006.285.11:02:10.05#ibcon#read 6, iclass 13, count 2 2006.285.11:02:10.05#ibcon#end of sib2, iclass 13, count 2 2006.285.11:02:10.05#ibcon#*after write, iclass 13, count 2 2006.285.11:02:10.05#ibcon#*before return 0, iclass 13, count 2 2006.285.11:02:10.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:02:10.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:02:10.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.11:02:10.05#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:10.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:02:10.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:02:10.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:02:10.17#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:02:10.17#ibcon#first serial, iclass 13, count 0 2006.285.11:02:10.17#ibcon#enter sib2, iclass 13, count 0 2006.285.11:02:10.17#ibcon#flushed, iclass 13, count 0 2006.285.11:02:10.17#ibcon#about to write, iclass 13, count 0 2006.285.11:02:10.17#ibcon#wrote, iclass 13, count 0 2006.285.11:02:10.17#ibcon#about to read 3, iclass 13, count 0 2006.285.11:02:10.19#ibcon#read 3, iclass 13, count 0 2006.285.11:02:10.19#ibcon#about to read 4, iclass 13, count 0 2006.285.11:02:10.19#ibcon#read 4, iclass 13, count 0 2006.285.11:02:10.19#ibcon#about to read 5, iclass 13, count 0 2006.285.11:02:10.19#ibcon#read 5, iclass 13, count 0 2006.285.11:02:10.19#ibcon#about to read 6, iclass 13, count 0 2006.285.11:02:10.19#ibcon#read 6, iclass 13, count 0 2006.285.11:02:10.19#ibcon#end of sib2, iclass 13, count 0 2006.285.11:02:10.19#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:02:10.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:02:10.19#ibcon#[27=USB\r\n] 2006.285.11:02:10.19#ibcon#*before write, iclass 13, count 0 2006.285.11:02:10.19#ibcon#enter sib2, iclass 13, count 0 2006.285.11:02:10.19#ibcon#flushed, iclass 13, count 0 2006.285.11:02:10.19#ibcon#about to write, iclass 13, count 0 2006.285.11:02:10.19#ibcon#wrote, iclass 13, count 0 2006.285.11:02:10.19#ibcon#about to read 3, iclass 13, count 0 2006.285.11:02:10.22#ibcon#read 3, iclass 13, count 0 2006.285.11:02:10.22#ibcon#about to read 4, iclass 13, count 0 2006.285.11:02:10.22#ibcon#read 4, iclass 13, count 0 2006.285.11:02:10.22#ibcon#about to read 5, iclass 13, count 0 2006.285.11:02:10.22#ibcon#read 5, iclass 13, count 0 2006.285.11:02:10.22#ibcon#about to read 6, iclass 13, count 0 2006.285.11:02:10.22#ibcon#read 6, iclass 13, count 0 2006.285.11:02:10.22#ibcon#end of sib2, iclass 13, count 0 2006.285.11:02:10.22#ibcon#*after write, iclass 13, count 0 2006.285.11:02:10.22#ibcon#*before return 0, iclass 13, count 0 2006.285.11:02:10.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:02:10.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:02:10.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:02:10.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:02:10.22$vck44/vblo=8,744.99 2006.285.11:02:10.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.11:02:10.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.11:02:10.22#ibcon#ireg 17 cls_cnt 0 2006.285.11:02:10.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:02:10.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:02:10.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:02:10.22#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:02:10.22#ibcon#first serial, iclass 15, count 0 2006.285.11:02:10.22#ibcon#enter sib2, iclass 15, count 0 2006.285.11:02:10.22#ibcon#flushed, iclass 15, count 0 2006.285.11:02:10.22#ibcon#about to write, iclass 15, count 0 2006.285.11:02:10.22#ibcon#wrote, iclass 15, count 0 2006.285.11:02:10.22#ibcon#about to read 3, iclass 15, count 0 2006.285.11:02:10.24#ibcon#read 3, iclass 15, count 0 2006.285.11:02:10.24#ibcon#about to read 4, iclass 15, count 0 2006.285.11:02:10.24#ibcon#read 4, iclass 15, count 0 2006.285.11:02:10.24#ibcon#about to read 5, iclass 15, count 0 2006.285.11:02:10.24#ibcon#read 5, iclass 15, count 0 2006.285.11:02:10.24#ibcon#about to read 6, iclass 15, count 0 2006.285.11:02:10.24#ibcon#read 6, iclass 15, count 0 2006.285.11:02:10.24#ibcon#end of sib2, iclass 15, count 0 2006.285.11:02:10.24#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:02:10.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:02:10.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:02:10.24#ibcon#*before write, iclass 15, count 0 2006.285.11:02:10.24#ibcon#enter sib2, iclass 15, count 0 2006.285.11:02:10.24#ibcon#flushed, iclass 15, count 0 2006.285.11:02:10.24#ibcon#about to write, iclass 15, count 0 2006.285.11:02:10.24#ibcon#wrote, iclass 15, count 0 2006.285.11:02:10.24#ibcon#about to read 3, iclass 15, count 0 2006.285.11:02:10.28#ibcon#read 3, iclass 15, count 0 2006.285.11:02:10.28#ibcon#about to read 4, iclass 15, count 0 2006.285.11:02:10.28#ibcon#read 4, iclass 15, count 0 2006.285.11:02:10.28#ibcon#about to read 5, iclass 15, count 0 2006.285.11:02:10.28#ibcon#read 5, iclass 15, count 0 2006.285.11:02:10.28#ibcon#about to read 6, iclass 15, count 0 2006.285.11:02:10.28#ibcon#read 6, iclass 15, count 0 2006.285.11:02:10.28#ibcon#end of sib2, iclass 15, count 0 2006.285.11:02:10.28#ibcon#*after write, iclass 15, count 0 2006.285.11:02:10.28#ibcon#*before return 0, iclass 15, count 0 2006.285.11:02:10.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:02:10.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:02:10.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:02:10.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:02:10.28$vck44/vb=8,4 2006.285.11:02:10.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.11:02:10.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.11:02:10.28#ibcon#ireg 11 cls_cnt 2 2006.285.11:02:10.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:02:10.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:02:10.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:02:10.34#ibcon#enter wrdev, iclass 17, count 2 2006.285.11:02:10.34#ibcon#first serial, iclass 17, count 2 2006.285.11:02:10.34#ibcon#enter sib2, iclass 17, count 2 2006.285.11:02:10.34#ibcon#flushed, iclass 17, count 2 2006.285.11:02:10.34#ibcon#about to write, iclass 17, count 2 2006.285.11:02:10.34#ibcon#wrote, iclass 17, count 2 2006.285.11:02:10.34#ibcon#about to read 3, iclass 17, count 2 2006.285.11:02:10.36#ibcon#read 3, iclass 17, count 2 2006.285.11:02:10.36#ibcon#about to read 4, iclass 17, count 2 2006.285.11:02:10.36#ibcon#read 4, iclass 17, count 2 2006.285.11:02:10.36#ibcon#about to read 5, iclass 17, count 2 2006.285.11:02:10.36#ibcon#read 5, iclass 17, count 2 2006.285.11:02:10.36#ibcon#about to read 6, iclass 17, count 2 2006.285.11:02:10.36#ibcon#read 6, iclass 17, count 2 2006.285.11:02:10.36#ibcon#end of sib2, iclass 17, count 2 2006.285.11:02:10.36#ibcon#*mode == 0, iclass 17, count 2 2006.285.11:02:10.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.11:02:10.36#ibcon#[27=AT08-04\r\n] 2006.285.11:02:10.36#ibcon#*before write, iclass 17, count 2 2006.285.11:02:10.36#ibcon#enter sib2, iclass 17, count 2 2006.285.11:02:10.36#ibcon#flushed, iclass 17, count 2 2006.285.11:02:10.36#ibcon#about to write, iclass 17, count 2 2006.285.11:02:10.36#ibcon#wrote, iclass 17, count 2 2006.285.11:02:10.36#ibcon#about to read 3, iclass 17, count 2 2006.285.11:02:10.39#ibcon#read 3, iclass 17, count 2 2006.285.11:02:10.39#ibcon#about to read 4, iclass 17, count 2 2006.285.11:02:10.39#ibcon#read 4, iclass 17, count 2 2006.285.11:02:10.39#ibcon#about to read 5, iclass 17, count 2 2006.285.11:02:10.39#ibcon#read 5, iclass 17, count 2 2006.285.11:02:10.39#ibcon#about to read 6, iclass 17, count 2 2006.285.11:02:10.39#ibcon#read 6, iclass 17, count 2 2006.285.11:02:10.39#ibcon#end of sib2, iclass 17, count 2 2006.285.11:02:10.39#ibcon#*after write, iclass 17, count 2 2006.285.11:02:10.39#ibcon#*before return 0, iclass 17, count 2 2006.285.11:02:10.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:02:10.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:02:10.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.11:02:10.39#ibcon#ireg 7 cls_cnt 0 2006.285.11:02:10.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:02:10.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:02:10.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:02:10.51#ibcon#enter wrdev, iclass 17, count 0 2006.285.11:02:10.51#ibcon#first serial, iclass 17, count 0 2006.285.11:02:10.51#ibcon#enter sib2, iclass 17, count 0 2006.285.11:02:10.51#ibcon#flushed, iclass 17, count 0 2006.285.11:02:10.51#ibcon#about to write, iclass 17, count 0 2006.285.11:02:10.51#ibcon#wrote, iclass 17, count 0 2006.285.11:02:10.51#ibcon#about to read 3, iclass 17, count 0 2006.285.11:02:10.53#ibcon#read 3, iclass 17, count 0 2006.285.11:02:10.53#ibcon#about to read 4, iclass 17, count 0 2006.285.11:02:10.53#ibcon#read 4, iclass 17, count 0 2006.285.11:02:10.53#ibcon#about to read 5, iclass 17, count 0 2006.285.11:02:10.53#ibcon#read 5, iclass 17, count 0 2006.285.11:02:10.53#ibcon#about to read 6, iclass 17, count 0 2006.285.11:02:10.53#ibcon#read 6, iclass 17, count 0 2006.285.11:02:10.53#ibcon#end of sib2, iclass 17, count 0 2006.285.11:02:10.53#ibcon#*mode == 0, iclass 17, count 0 2006.285.11:02:10.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.11:02:10.53#ibcon#[27=USB\r\n] 2006.285.11:02:10.53#ibcon#*before write, iclass 17, count 0 2006.285.11:02:10.53#ibcon#enter sib2, iclass 17, count 0 2006.285.11:02:10.53#ibcon#flushed, iclass 17, count 0 2006.285.11:02:10.53#ibcon#about to write, iclass 17, count 0 2006.285.11:02:10.53#ibcon#wrote, iclass 17, count 0 2006.285.11:02:10.53#ibcon#about to read 3, iclass 17, count 0 2006.285.11:02:10.56#ibcon#read 3, iclass 17, count 0 2006.285.11:02:10.56#ibcon#about to read 4, iclass 17, count 0 2006.285.11:02:10.56#ibcon#read 4, iclass 17, count 0 2006.285.11:02:10.56#ibcon#about to read 5, iclass 17, count 0 2006.285.11:02:10.56#ibcon#read 5, iclass 17, count 0 2006.285.11:02:10.56#ibcon#about to read 6, iclass 17, count 0 2006.285.11:02:10.56#ibcon#read 6, iclass 17, count 0 2006.285.11:02:10.56#ibcon#end of sib2, iclass 17, count 0 2006.285.11:02:10.56#ibcon#*after write, iclass 17, count 0 2006.285.11:02:10.56#ibcon#*before return 0, iclass 17, count 0 2006.285.11:02:10.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:02:10.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:02:10.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.11:02:10.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.11:02:10.56$vck44/vabw=wide 2006.285.11:02:10.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.11:02:10.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.11:02:10.56#ibcon#ireg 8 cls_cnt 0 2006.285.11:02:10.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:02:10.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:02:10.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:02:10.56#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:02:10.56#ibcon#first serial, iclass 19, count 0 2006.285.11:02:10.56#ibcon#enter sib2, iclass 19, count 0 2006.285.11:02:10.56#ibcon#flushed, iclass 19, count 0 2006.285.11:02:10.56#ibcon#about to write, iclass 19, count 0 2006.285.11:02:10.56#ibcon#wrote, iclass 19, count 0 2006.285.11:02:10.56#ibcon#about to read 3, iclass 19, count 0 2006.285.11:02:10.58#ibcon#read 3, iclass 19, count 0 2006.285.11:02:10.58#ibcon#about to read 4, iclass 19, count 0 2006.285.11:02:10.58#ibcon#read 4, iclass 19, count 0 2006.285.11:02:10.58#ibcon#about to read 5, iclass 19, count 0 2006.285.11:02:10.58#ibcon#read 5, iclass 19, count 0 2006.285.11:02:10.58#ibcon#about to read 6, iclass 19, count 0 2006.285.11:02:10.58#ibcon#read 6, iclass 19, count 0 2006.285.11:02:10.58#ibcon#end of sib2, iclass 19, count 0 2006.285.11:02:10.58#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:02:10.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:02:10.58#ibcon#[25=BW32\r\n] 2006.285.11:02:10.58#ibcon#*before write, iclass 19, count 0 2006.285.11:02:10.58#ibcon#enter sib2, iclass 19, count 0 2006.285.11:02:10.58#ibcon#flushed, iclass 19, count 0 2006.285.11:02:10.58#ibcon#about to write, iclass 19, count 0 2006.285.11:02:10.58#ibcon#wrote, iclass 19, count 0 2006.285.11:02:10.58#ibcon#about to read 3, iclass 19, count 0 2006.285.11:02:10.61#ibcon#read 3, iclass 19, count 0 2006.285.11:02:10.61#ibcon#about to read 4, iclass 19, count 0 2006.285.11:02:10.61#ibcon#read 4, iclass 19, count 0 2006.285.11:02:10.61#ibcon#about to read 5, iclass 19, count 0 2006.285.11:02:10.61#ibcon#read 5, iclass 19, count 0 2006.285.11:02:10.61#ibcon#about to read 6, iclass 19, count 0 2006.285.11:02:10.61#ibcon#read 6, iclass 19, count 0 2006.285.11:02:10.61#ibcon#end of sib2, iclass 19, count 0 2006.285.11:02:10.61#ibcon#*after write, iclass 19, count 0 2006.285.11:02:10.61#ibcon#*before return 0, iclass 19, count 0 2006.285.11:02:10.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:02:10.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:02:10.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:02:10.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:02:10.61$vck44/vbbw=wide 2006.285.11:02:10.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.11:02:10.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.11:02:10.61#ibcon#ireg 8 cls_cnt 0 2006.285.11:02:10.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:02:10.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:02:10.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:02:10.68#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:02:10.68#ibcon#first serial, iclass 21, count 0 2006.285.11:02:10.68#ibcon#enter sib2, iclass 21, count 0 2006.285.11:02:10.68#ibcon#flushed, iclass 21, count 0 2006.285.11:02:10.68#ibcon#about to write, iclass 21, count 0 2006.285.11:02:10.68#ibcon#wrote, iclass 21, count 0 2006.285.11:02:10.68#ibcon#about to read 3, iclass 21, count 0 2006.285.11:02:10.70#ibcon#read 3, iclass 21, count 0 2006.285.11:02:10.70#ibcon#about to read 4, iclass 21, count 0 2006.285.11:02:10.70#ibcon#read 4, iclass 21, count 0 2006.285.11:02:10.70#ibcon#about to read 5, iclass 21, count 0 2006.285.11:02:10.70#ibcon#read 5, iclass 21, count 0 2006.285.11:02:10.70#ibcon#about to read 6, iclass 21, count 0 2006.285.11:02:10.70#ibcon#read 6, iclass 21, count 0 2006.285.11:02:10.70#ibcon#end of sib2, iclass 21, count 0 2006.285.11:02:10.70#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:02:10.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:02:10.70#ibcon#[27=BW32\r\n] 2006.285.11:02:10.70#ibcon#*before write, iclass 21, count 0 2006.285.11:02:10.70#ibcon#enter sib2, iclass 21, count 0 2006.285.11:02:10.70#ibcon#flushed, iclass 21, count 0 2006.285.11:02:10.70#ibcon#about to write, iclass 21, count 0 2006.285.11:02:10.70#ibcon#wrote, iclass 21, count 0 2006.285.11:02:10.70#ibcon#about to read 3, iclass 21, count 0 2006.285.11:02:10.73#ibcon#read 3, iclass 21, count 0 2006.285.11:02:10.73#ibcon#about to read 4, iclass 21, count 0 2006.285.11:02:10.73#ibcon#read 4, iclass 21, count 0 2006.285.11:02:10.73#ibcon#about to read 5, iclass 21, count 0 2006.285.11:02:10.73#ibcon#read 5, iclass 21, count 0 2006.285.11:02:10.73#ibcon#about to read 6, iclass 21, count 0 2006.285.11:02:10.73#ibcon#read 6, iclass 21, count 0 2006.285.11:02:10.73#ibcon#end of sib2, iclass 21, count 0 2006.285.11:02:10.73#ibcon#*after write, iclass 21, count 0 2006.285.11:02:10.73#ibcon#*before return 0, iclass 21, count 0 2006.285.11:02:10.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:02:10.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:02:10.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:02:10.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:02:10.73$setupk4/ifdk4 2006.285.11:02:10.73$ifdk4/lo= 2006.285.11:02:10.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:02:10.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:02:10.73$ifdk4/patch= 2006.285.11:02:10.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:02:10.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:02:10.73$setupk4/!*+20s 2006.285.11:02:11.25#abcon#<5=/05 1.1 1.8 19.48 921015.0\r\n> 2006.285.11:02:11.27#abcon#{5=INTERFACE CLEAR} 2006.285.11:02:11.33#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:02:21.42#abcon#<5=/05 1.1 1.8 19.48 931015.0\r\n> 2006.285.11:02:21.44#abcon#{5=INTERFACE CLEAR} 2006.285.11:02:21.50#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:02:25.14#trakl#Source acquired 2006.285.11:02:25.23$setupk4/"tpicd 2006.285.11:02:25.23$setupk4/echo=off 2006.285.11:02:25.23$setupk4/xlog=off 2006.285.11:02:25.23:!2006.285.11:03:23 2006.285.11:02:26.14#flagr#flagr/antenna,acquired 2006.285.11:03:23.00:preob 2006.285.11:03:24.13/onsource/TRACKING 2006.285.11:03:24.13:!2006.285.11:03:33 2006.285.11:03:33.00:"tape 2006.285.11:03:33.00:"st=record 2006.285.11:03:33.00:data_valid=on 2006.285.11:03:33.00:midob 2006.285.11:03:33.13/onsource/TRACKING 2006.285.11:03:33.13/wx/19.48,1015.0,92 2006.285.11:03:33.19/cable/+6.4877E-03 2006.285.11:03:34.28/va/01,07,usb,yes,31,34 2006.285.11:03:34.28/va/02,06,usb,yes,31,32 2006.285.11:03:34.28/va/03,07,usb,yes,31,33 2006.285.11:03:34.28/va/04,06,usb,yes,32,34 2006.285.11:03:34.28/va/05,03,usb,yes,32,32 2006.285.11:03:34.28/va/06,04,usb,yes,29,28 2006.285.11:03:34.28/va/07,04,usb,yes,29,30 2006.285.11:03:34.28/va/08,03,usb,yes,30,36 2006.285.11:03:34.51/valo/01,524.99,yes,locked 2006.285.11:03:34.51/valo/02,534.99,yes,locked 2006.285.11:03:34.51/valo/03,564.99,yes,locked 2006.285.11:03:34.51/valo/04,624.99,yes,locked 2006.285.11:03:34.51/valo/05,734.99,yes,locked 2006.285.11:03:34.51/valo/06,814.99,yes,locked 2006.285.11:03:34.51/valo/07,864.99,yes,locked 2006.285.11:03:34.51/valo/08,884.99,yes,locked 2006.285.11:03:35.60/vb/01,04,usb,yes,30,28 2006.285.11:03:35.60/vb/02,05,usb,yes,28,28 2006.285.11:03:35.60/vb/03,04,usb,yes,29,32 2006.285.11:03:35.60/vb/04,05,usb,yes,29,28 2006.285.11:03:35.60/vb/05,04,usb,yes,26,28 2006.285.11:03:35.60/vb/06,03,usb,yes,37,33 2006.285.11:03:35.60/vb/07,04,usb,yes,30,30 2006.285.11:03:35.60/vb/08,04,usb,yes,27,31 2006.285.11:03:35.83/vblo/01,629.99,yes,locked 2006.285.11:03:35.83/vblo/02,634.99,yes,locked 2006.285.11:03:35.83/vblo/03,649.99,yes,locked 2006.285.11:03:35.83/vblo/04,679.99,yes,locked 2006.285.11:03:35.83/vblo/05,709.99,yes,locked 2006.285.11:03:35.83/vblo/06,719.99,yes,locked 2006.285.11:03:35.83/vblo/07,734.99,yes,locked 2006.285.11:03:35.83/vblo/08,744.99,yes,locked 2006.285.11:03:35.98/vabw/8 2006.285.11:03:36.13/vbbw/8 2006.285.11:03:36.22/xfe/off,on,12.0 2006.285.11:03:36.59/ifatt/23,28,28,28 2006.285.11:03:37.07/fmout-gps/S +2.76E-07 2006.285.11:03:37.09:!2006.285.11:04:43 2006.285.11:04:43.00:data_valid=off 2006.285.11:04:43.00:"et 2006.285.11:04:43.00:!+3s 2006.285.11:04:46.01:"tape 2006.285.11:04:46.01:postob 2006.285.11:04:46.12/cable/+6.4896E-03 2006.285.11:04:46.12/wx/19.47,1015.0,93 2006.285.11:04:47.08/fmout-gps/S +2.74E-07 2006.285.11:04:47.08:scan_name=285-1106,jd0610,60 2006.285.11:04:47.08:source=1611+343,161341.06,341247.9,2000.0,cw 2006.285.11:04:48.13#flagr#flagr/antenna,new-source 2006.285.11:04:48.13:checkk5 2006.285.11:04:48.47/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:04:48.84/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:04:49.19/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:04:49.55/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:04:49.96/chk_obsdata//k5ts1/T2851103??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.11:04:50.59/chk_obsdata//k5ts2/T2851103??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.11:04:51.02/chk_obsdata//k5ts3/T2851103??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.11:04:51.39/chk_obsdata//k5ts4/T2851103??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.11:04:52.43/k5log//k5ts1_log_newline 2006.285.11:04:53.40/k5log//k5ts2_log_newline 2006.285.11:04:54.77/k5log//k5ts3_log_newline 2006.285.11:04:55.47/k5log//k5ts4_log_newline 2006.285.11:04:55.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:04:55.49:setupk4=1 2006.285.11:04:55.49$setupk4/echo=on 2006.285.11:04:55.49$setupk4/pcalon 2006.285.11:04:55.49$pcalon/"no phase cal control is implemented here 2006.285.11:04:55.49$setupk4/"tpicd=stop 2006.285.11:04:55.49$setupk4/"rec=synch_on 2006.285.11:04:55.49$setupk4/"rec_mode=128 2006.285.11:04:55.49$setupk4/!* 2006.285.11:04:55.49$setupk4/recpk4 2006.285.11:04:55.49$recpk4/recpatch= 2006.285.11:04:55.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:04:55.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:04:55.49$setupk4/vck44 2006.285.11:04:55.49$vck44/valo=1,524.99 2006.285.11:04:55.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.11:04:55.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.11:04:55.49#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:55.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:04:55.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:04:55.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:04:55.49#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:04:55.49#ibcon#first serial, iclass 22, count 0 2006.285.11:04:55.49#ibcon#enter sib2, iclass 22, count 0 2006.285.11:04:55.49#ibcon#flushed, iclass 22, count 0 2006.285.11:04:55.49#ibcon#about to write, iclass 22, count 0 2006.285.11:04:55.49#ibcon#wrote, iclass 22, count 0 2006.285.11:04:55.49#ibcon#about to read 3, iclass 22, count 0 2006.285.11:04:55.51#ibcon#read 3, iclass 22, count 0 2006.285.11:04:55.51#ibcon#about to read 4, iclass 22, count 0 2006.285.11:04:55.51#ibcon#read 4, iclass 22, count 0 2006.285.11:04:55.51#ibcon#about to read 5, iclass 22, count 0 2006.285.11:04:55.51#ibcon#read 5, iclass 22, count 0 2006.285.11:04:55.51#ibcon#about to read 6, iclass 22, count 0 2006.285.11:04:55.51#ibcon#read 6, iclass 22, count 0 2006.285.11:04:55.51#ibcon#end of sib2, iclass 22, count 0 2006.285.11:04:55.51#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:04:55.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:04:55.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:04:55.51#ibcon#*before write, iclass 22, count 0 2006.285.11:04:55.51#ibcon#enter sib2, iclass 22, count 0 2006.285.11:04:55.51#ibcon#flushed, iclass 22, count 0 2006.285.11:04:55.51#ibcon#about to write, iclass 22, count 0 2006.285.11:04:55.51#ibcon#wrote, iclass 22, count 0 2006.285.11:04:55.51#ibcon#about to read 3, iclass 22, count 0 2006.285.11:04:55.56#ibcon#read 3, iclass 22, count 0 2006.285.11:04:55.56#ibcon#about to read 4, iclass 22, count 0 2006.285.11:04:55.56#ibcon#read 4, iclass 22, count 0 2006.285.11:04:55.56#ibcon#about to read 5, iclass 22, count 0 2006.285.11:04:55.56#ibcon#read 5, iclass 22, count 0 2006.285.11:04:55.56#ibcon#about to read 6, iclass 22, count 0 2006.285.11:04:55.56#ibcon#read 6, iclass 22, count 0 2006.285.11:04:55.56#ibcon#end of sib2, iclass 22, count 0 2006.285.11:04:55.56#ibcon#*after write, iclass 22, count 0 2006.285.11:04:55.56#ibcon#*before return 0, iclass 22, count 0 2006.285.11:04:55.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:04:55.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:04:55.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:04:55.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:04:55.56$vck44/va=1,7 2006.285.11:04:55.56#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.11:04:55.56#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.11:04:55.56#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:55.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:04:55.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:04:55.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:04:55.56#ibcon#enter wrdev, iclass 24, count 2 2006.285.11:04:55.56#ibcon#first serial, iclass 24, count 2 2006.285.11:04:55.56#ibcon#enter sib2, iclass 24, count 2 2006.285.11:04:55.56#ibcon#flushed, iclass 24, count 2 2006.285.11:04:55.56#ibcon#about to write, iclass 24, count 2 2006.285.11:04:55.56#ibcon#wrote, iclass 24, count 2 2006.285.11:04:55.56#ibcon#about to read 3, iclass 24, count 2 2006.285.11:04:55.58#ibcon#read 3, iclass 24, count 2 2006.285.11:04:55.58#ibcon#about to read 4, iclass 24, count 2 2006.285.11:04:55.58#ibcon#read 4, iclass 24, count 2 2006.285.11:04:55.58#ibcon#about to read 5, iclass 24, count 2 2006.285.11:04:55.58#ibcon#read 5, iclass 24, count 2 2006.285.11:04:55.58#ibcon#about to read 6, iclass 24, count 2 2006.285.11:04:55.58#ibcon#read 6, iclass 24, count 2 2006.285.11:04:55.58#ibcon#end of sib2, iclass 24, count 2 2006.285.11:04:55.58#ibcon#*mode == 0, iclass 24, count 2 2006.285.11:04:55.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.11:04:55.58#ibcon#[25=AT01-07\r\n] 2006.285.11:04:55.58#ibcon#*before write, iclass 24, count 2 2006.285.11:04:55.58#ibcon#enter sib2, iclass 24, count 2 2006.285.11:04:55.58#ibcon#flushed, iclass 24, count 2 2006.285.11:04:55.58#ibcon#about to write, iclass 24, count 2 2006.285.11:04:55.58#ibcon#wrote, iclass 24, count 2 2006.285.11:04:55.58#ibcon#about to read 3, iclass 24, count 2 2006.285.11:04:55.61#ibcon#read 3, iclass 24, count 2 2006.285.11:04:55.61#ibcon#about to read 4, iclass 24, count 2 2006.285.11:04:55.61#ibcon#read 4, iclass 24, count 2 2006.285.11:04:55.61#ibcon#about to read 5, iclass 24, count 2 2006.285.11:04:55.61#ibcon#read 5, iclass 24, count 2 2006.285.11:04:55.61#ibcon#about to read 6, iclass 24, count 2 2006.285.11:04:55.61#ibcon#read 6, iclass 24, count 2 2006.285.11:04:55.61#ibcon#end of sib2, iclass 24, count 2 2006.285.11:04:55.61#ibcon#*after write, iclass 24, count 2 2006.285.11:04:55.61#ibcon#*before return 0, iclass 24, count 2 2006.285.11:04:55.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:04:55.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:04:55.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.11:04:55.61#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:55.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:04:55.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:04:55.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:04:55.73#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:04:55.73#ibcon#first serial, iclass 24, count 0 2006.285.11:04:55.73#ibcon#enter sib2, iclass 24, count 0 2006.285.11:04:55.73#ibcon#flushed, iclass 24, count 0 2006.285.11:04:55.73#ibcon#about to write, iclass 24, count 0 2006.285.11:04:55.73#ibcon#wrote, iclass 24, count 0 2006.285.11:04:55.73#ibcon#about to read 3, iclass 24, count 0 2006.285.11:04:55.75#ibcon#read 3, iclass 24, count 0 2006.285.11:04:55.75#ibcon#about to read 4, iclass 24, count 0 2006.285.11:04:55.75#ibcon#read 4, iclass 24, count 0 2006.285.11:04:55.75#ibcon#about to read 5, iclass 24, count 0 2006.285.11:04:55.75#ibcon#read 5, iclass 24, count 0 2006.285.11:04:55.75#ibcon#about to read 6, iclass 24, count 0 2006.285.11:04:55.75#ibcon#read 6, iclass 24, count 0 2006.285.11:04:55.75#ibcon#end of sib2, iclass 24, count 0 2006.285.11:04:55.75#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:04:55.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:04:55.75#ibcon#[25=USB\r\n] 2006.285.11:04:55.75#ibcon#*before write, iclass 24, count 0 2006.285.11:04:55.75#ibcon#enter sib2, iclass 24, count 0 2006.285.11:04:55.75#ibcon#flushed, iclass 24, count 0 2006.285.11:04:55.75#ibcon#about to write, iclass 24, count 0 2006.285.11:04:55.75#ibcon#wrote, iclass 24, count 0 2006.285.11:04:55.75#ibcon#about to read 3, iclass 24, count 0 2006.285.11:04:55.78#ibcon#read 3, iclass 24, count 0 2006.285.11:04:55.78#ibcon#about to read 4, iclass 24, count 0 2006.285.11:04:55.78#ibcon#read 4, iclass 24, count 0 2006.285.11:04:55.78#ibcon#about to read 5, iclass 24, count 0 2006.285.11:04:55.78#ibcon#read 5, iclass 24, count 0 2006.285.11:04:55.78#ibcon#about to read 6, iclass 24, count 0 2006.285.11:04:55.78#ibcon#read 6, iclass 24, count 0 2006.285.11:04:55.78#ibcon#end of sib2, iclass 24, count 0 2006.285.11:04:55.78#ibcon#*after write, iclass 24, count 0 2006.285.11:04:55.78#ibcon#*before return 0, iclass 24, count 0 2006.285.11:04:55.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:04:55.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:04:55.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:04:55.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:04:55.78$vck44/valo=2,534.99 2006.285.11:04:55.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.11:04:55.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.11:04:55.78#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:55.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:04:55.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:04:55.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:04:55.78#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:04:55.78#ibcon#first serial, iclass 26, count 0 2006.285.11:04:55.78#ibcon#enter sib2, iclass 26, count 0 2006.285.11:04:55.78#ibcon#flushed, iclass 26, count 0 2006.285.11:04:55.78#ibcon#about to write, iclass 26, count 0 2006.285.11:04:55.78#ibcon#wrote, iclass 26, count 0 2006.285.11:04:55.78#ibcon#about to read 3, iclass 26, count 0 2006.285.11:04:55.80#ibcon#read 3, iclass 26, count 0 2006.285.11:04:55.80#ibcon#about to read 4, iclass 26, count 0 2006.285.11:04:55.80#ibcon#read 4, iclass 26, count 0 2006.285.11:04:55.80#ibcon#about to read 5, iclass 26, count 0 2006.285.11:04:55.80#ibcon#read 5, iclass 26, count 0 2006.285.11:04:55.80#ibcon#about to read 6, iclass 26, count 0 2006.285.11:04:55.80#ibcon#read 6, iclass 26, count 0 2006.285.11:04:55.80#ibcon#end of sib2, iclass 26, count 0 2006.285.11:04:55.80#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:04:55.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:04:55.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:04:55.80#ibcon#*before write, iclass 26, count 0 2006.285.11:04:55.80#ibcon#enter sib2, iclass 26, count 0 2006.285.11:04:55.80#ibcon#flushed, iclass 26, count 0 2006.285.11:04:55.80#ibcon#about to write, iclass 26, count 0 2006.285.11:04:55.80#ibcon#wrote, iclass 26, count 0 2006.285.11:04:55.80#ibcon#about to read 3, iclass 26, count 0 2006.285.11:04:55.84#ibcon#read 3, iclass 26, count 0 2006.285.11:04:55.84#ibcon#about to read 4, iclass 26, count 0 2006.285.11:04:55.84#ibcon#read 4, iclass 26, count 0 2006.285.11:04:55.84#ibcon#about to read 5, iclass 26, count 0 2006.285.11:04:55.84#ibcon#read 5, iclass 26, count 0 2006.285.11:04:55.84#ibcon#about to read 6, iclass 26, count 0 2006.285.11:04:55.84#ibcon#read 6, iclass 26, count 0 2006.285.11:04:55.84#ibcon#end of sib2, iclass 26, count 0 2006.285.11:04:55.84#ibcon#*after write, iclass 26, count 0 2006.285.11:04:55.84#ibcon#*before return 0, iclass 26, count 0 2006.285.11:04:55.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:04:55.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:04:55.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:04:55.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:04:55.84$vck44/va=2,6 2006.285.11:04:55.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.11:04:55.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.11:04:55.84#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:55.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:04:55.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:04:55.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:04:55.90#ibcon#enter wrdev, iclass 28, count 2 2006.285.11:04:55.90#ibcon#first serial, iclass 28, count 2 2006.285.11:04:55.90#ibcon#enter sib2, iclass 28, count 2 2006.285.11:04:55.90#ibcon#flushed, iclass 28, count 2 2006.285.11:04:55.90#ibcon#about to write, iclass 28, count 2 2006.285.11:04:55.90#ibcon#wrote, iclass 28, count 2 2006.285.11:04:55.90#ibcon#about to read 3, iclass 28, count 2 2006.285.11:04:55.92#ibcon#read 3, iclass 28, count 2 2006.285.11:04:55.92#ibcon#about to read 4, iclass 28, count 2 2006.285.11:04:55.92#ibcon#read 4, iclass 28, count 2 2006.285.11:04:55.92#ibcon#about to read 5, iclass 28, count 2 2006.285.11:04:55.92#ibcon#read 5, iclass 28, count 2 2006.285.11:04:55.92#ibcon#about to read 6, iclass 28, count 2 2006.285.11:04:55.92#ibcon#read 6, iclass 28, count 2 2006.285.11:04:55.92#ibcon#end of sib2, iclass 28, count 2 2006.285.11:04:55.92#ibcon#*mode == 0, iclass 28, count 2 2006.285.11:04:55.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.11:04:55.92#ibcon#[25=AT02-06\r\n] 2006.285.11:04:55.92#ibcon#*before write, iclass 28, count 2 2006.285.11:04:55.92#ibcon#enter sib2, iclass 28, count 2 2006.285.11:04:55.92#ibcon#flushed, iclass 28, count 2 2006.285.11:04:55.92#ibcon#about to write, iclass 28, count 2 2006.285.11:04:55.92#ibcon#wrote, iclass 28, count 2 2006.285.11:04:55.92#ibcon#about to read 3, iclass 28, count 2 2006.285.11:04:55.95#ibcon#read 3, iclass 28, count 2 2006.285.11:04:55.95#ibcon#about to read 4, iclass 28, count 2 2006.285.11:04:55.95#ibcon#read 4, iclass 28, count 2 2006.285.11:04:55.95#ibcon#about to read 5, iclass 28, count 2 2006.285.11:04:55.95#ibcon#read 5, iclass 28, count 2 2006.285.11:04:55.95#ibcon#about to read 6, iclass 28, count 2 2006.285.11:04:55.95#ibcon#read 6, iclass 28, count 2 2006.285.11:04:55.95#ibcon#end of sib2, iclass 28, count 2 2006.285.11:04:55.95#ibcon#*after write, iclass 28, count 2 2006.285.11:04:55.95#ibcon#*before return 0, iclass 28, count 2 2006.285.11:04:55.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:04:55.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:04:55.95#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.11:04:55.95#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:55.95#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:04:56.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:04:56.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:04:56.07#ibcon#enter wrdev, iclass 28, count 0 2006.285.11:04:56.07#ibcon#first serial, iclass 28, count 0 2006.285.11:04:56.07#ibcon#enter sib2, iclass 28, count 0 2006.285.11:04:56.07#ibcon#flushed, iclass 28, count 0 2006.285.11:04:56.07#ibcon#about to write, iclass 28, count 0 2006.285.11:04:56.07#ibcon#wrote, iclass 28, count 0 2006.285.11:04:56.07#ibcon#about to read 3, iclass 28, count 0 2006.285.11:04:56.09#ibcon#read 3, iclass 28, count 0 2006.285.11:04:56.09#ibcon#about to read 4, iclass 28, count 0 2006.285.11:04:56.09#ibcon#read 4, iclass 28, count 0 2006.285.11:04:56.09#ibcon#about to read 5, iclass 28, count 0 2006.285.11:04:56.09#ibcon#read 5, iclass 28, count 0 2006.285.11:04:56.09#ibcon#about to read 6, iclass 28, count 0 2006.285.11:04:56.09#ibcon#read 6, iclass 28, count 0 2006.285.11:04:56.09#ibcon#end of sib2, iclass 28, count 0 2006.285.11:04:56.09#ibcon#*mode == 0, iclass 28, count 0 2006.285.11:04:56.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.11:04:56.09#ibcon#[25=USB\r\n] 2006.285.11:04:56.09#ibcon#*before write, iclass 28, count 0 2006.285.11:04:56.09#ibcon#enter sib2, iclass 28, count 0 2006.285.11:04:56.09#ibcon#flushed, iclass 28, count 0 2006.285.11:04:56.09#ibcon#about to write, iclass 28, count 0 2006.285.11:04:56.09#ibcon#wrote, iclass 28, count 0 2006.285.11:04:56.09#ibcon#about to read 3, iclass 28, count 0 2006.285.11:04:56.12#ibcon#read 3, iclass 28, count 0 2006.285.11:04:56.12#ibcon#about to read 4, iclass 28, count 0 2006.285.11:04:56.12#ibcon#read 4, iclass 28, count 0 2006.285.11:04:56.12#ibcon#about to read 5, iclass 28, count 0 2006.285.11:04:56.12#ibcon#read 5, iclass 28, count 0 2006.285.11:04:56.12#ibcon#about to read 6, iclass 28, count 0 2006.285.11:04:56.12#ibcon#read 6, iclass 28, count 0 2006.285.11:04:56.12#ibcon#end of sib2, iclass 28, count 0 2006.285.11:04:56.12#ibcon#*after write, iclass 28, count 0 2006.285.11:04:56.12#ibcon#*before return 0, iclass 28, count 0 2006.285.11:04:56.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:04:56.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:04:56.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.11:04:56.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.11:04:56.12$vck44/valo=3,564.99 2006.285.11:04:56.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.11:04:56.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.11:04:56.12#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:56.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:04:56.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:04:56.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:04:56.12#ibcon#enter wrdev, iclass 30, count 0 2006.285.11:04:56.12#ibcon#first serial, iclass 30, count 0 2006.285.11:04:56.12#ibcon#enter sib2, iclass 30, count 0 2006.285.11:04:56.12#ibcon#flushed, iclass 30, count 0 2006.285.11:04:56.12#ibcon#about to write, iclass 30, count 0 2006.285.11:04:56.12#ibcon#wrote, iclass 30, count 0 2006.285.11:04:56.12#ibcon#about to read 3, iclass 30, count 0 2006.285.11:04:56.14#ibcon#read 3, iclass 30, count 0 2006.285.11:04:56.14#ibcon#about to read 4, iclass 30, count 0 2006.285.11:04:56.14#ibcon#read 4, iclass 30, count 0 2006.285.11:04:56.14#ibcon#about to read 5, iclass 30, count 0 2006.285.11:04:56.14#ibcon#read 5, iclass 30, count 0 2006.285.11:04:56.14#ibcon#about to read 6, iclass 30, count 0 2006.285.11:04:56.14#ibcon#read 6, iclass 30, count 0 2006.285.11:04:56.14#ibcon#end of sib2, iclass 30, count 0 2006.285.11:04:56.14#ibcon#*mode == 0, iclass 30, count 0 2006.285.11:04:56.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.11:04:56.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:04:56.14#ibcon#*before write, iclass 30, count 0 2006.285.11:04:56.14#ibcon#enter sib2, iclass 30, count 0 2006.285.11:04:56.14#ibcon#flushed, iclass 30, count 0 2006.285.11:04:56.14#ibcon#about to write, iclass 30, count 0 2006.285.11:04:56.14#ibcon#wrote, iclass 30, count 0 2006.285.11:04:56.14#ibcon#about to read 3, iclass 30, count 0 2006.285.11:04:56.18#ibcon#read 3, iclass 30, count 0 2006.285.11:04:56.18#ibcon#about to read 4, iclass 30, count 0 2006.285.11:04:56.18#ibcon#read 4, iclass 30, count 0 2006.285.11:04:56.18#ibcon#about to read 5, iclass 30, count 0 2006.285.11:04:56.18#ibcon#read 5, iclass 30, count 0 2006.285.11:04:56.18#ibcon#about to read 6, iclass 30, count 0 2006.285.11:04:56.18#ibcon#read 6, iclass 30, count 0 2006.285.11:04:56.18#ibcon#end of sib2, iclass 30, count 0 2006.285.11:04:56.18#ibcon#*after write, iclass 30, count 0 2006.285.11:04:56.18#ibcon#*before return 0, iclass 30, count 0 2006.285.11:04:56.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:04:56.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:04:56.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.11:04:56.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.11:04:56.18$vck44/va=3,7 2006.285.11:04:56.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.11:04:56.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.11:04:56.18#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:56.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:04:56.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:04:56.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:04:56.24#ibcon#enter wrdev, iclass 32, count 2 2006.285.11:04:56.24#ibcon#first serial, iclass 32, count 2 2006.285.11:04:56.24#ibcon#enter sib2, iclass 32, count 2 2006.285.11:04:56.24#ibcon#flushed, iclass 32, count 2 2006.285.11:04:56.24#ibcon#about to write, iclass 32, count 2 2006.285.11:04:56.24#ibcon#wrote, iclass 32, count 2 2006.285.11:04:56.24#ibcon#about to read 3, iclass 32, count 2 2006.285.11:04:56.26#ibcon#read 3, iclass 32, count 2 2006.285.11:04:56.26#ibcon#about to read 4, iclass 32, count 2 2006.285.11:04:56.26#ibcon#read 4, iclass 32, count 2 2006.285.11:04:56.26#ibcon#about to read 5, iclass 32, count 2 2006.285.11:04:56.26#ibcon#read 5, iclass 32, count 2 2006.285.11:04:56.26#ibcon#about to read 6, iclass 32, count 2 2006.285.11:04:56.26#ibcon#read 6, iclass 32, count 2 2006.285.11:04:56.26#ibcon#end of sib2, iclass 32, count 2 2006.285.11:04:56.26#ibcon#*mode == 0, iclass 32, count 2 2006.285.11:04:56.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.11:04:56.26#ibcon#[25=AT03-07\r\n] 2006.285.11:04:56.26#ibcon#*before write, iclass 32, count 2 2006.285.11:04:56.26#ibcon#enter sib2, iclass 32, count 2 2006.285.11:04:56.26#ibcon#flushed, iclass 32, count 2 2006.285.11:04:56.26#ibcon#about to write, iclass 32, count 2 2006.285.11:04:56.26#ibcon#wrote, iclass 32, count 2 2006.285.11:04:56.26#ibcon#about to read 3, iclass 32, count 2 2006.285.11:04:56.29#ibcon#read 3, iclass 32, count 2 2006.285.11:04:56.29#ibcon#about to read 4, iclass 32, count 2 2006.285.11:04:56.29#ibcon#read 4, iclass 32, count 2 2006.285.11:04:56.29#ibcon#about to read 5, iclass 32, count 2 2006.285.11:04:56.29#ibcon#read 5, iclass 32, count 2 2006.285.11:04:56.29#ibcon#about to read 6, iclass 32, count 2 2006.285.11:04:56.29#ibcon#read 6, iclass 32, count 2 2006.285.11:04:56.29#ibcon#end of sib2, iclass 32, count 2 2006.285.11:04:56.29#ibcon#*after write, iclass 32, count 2 2006.285.11:04:56.29#ibcon#*before return 0, iclass 32, count 2 2006.285.11:04:56.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:04:56.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:04:56.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.11:04:56.29#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:56.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:04:56.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:04:56.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:04:56.41#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:04:56.41#ibcon#first serial, iclass 32, count 0 2006.285.11:04:56.41#ibcon#enter sib2, iclass 32, count 0 2006.285.11:04:56.41#ibcon#flushed, iclass 32, count 0 2006.285.11:04:56.41#ibcon#about to write, iclass 32, count 0 2006.285.11:04:56.41#ibcon#wrote, iclass 32, count 0 2006.285.11:04:56.41#ibcon#about to read 3, iclass 32, count 0 2006.285.11:04:56.43#ibcon#read 3, iclass 32, count 0 2006.285.11:04:56.43#ibcon#about to read 4, iclass 32, count 0 2006.285.11:04:56.43#ibcon#read 4, iclass 32, count 0 2006.285.11:04:56.43#ibcon#about to read 5, iclass 32, count 0 2006.285.11:04:56.43#ibcon#read 5, iclass 32, count 0 2006.285.11:04:56.43#ibcon#about to read 6, iclass 32, count 0 2006.285.11:04:56.43#ibcon#read 6, iclass 32, count 0 2006.285.11:04:56.43#ibcon#end of sib2, iclass 32, count 0 2006.285.11:04:56.43#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:04:56.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:04:56.43#ibcon#[25=USB\r\n] 2006.285.11:04:56.43#ibcon#*before write, iclass 32, count 0 2006.285.11:04:56.43#ibcon#enter sib2, iclass 32, count 0 2006.285.11:04:56.43#ibcon#flushed, iclass 32, count 0 2006.285.11:04:56.43#ibcon#about to write, iclass 32, count 0 2006.285.11:04:56.43#ibcon#wrote, iclass 32, count 0 2006.285.11:04:56.43#ibcon#about to read 3, iclass 32, count 0 2006.285.11:04:56.46#ibcon#read 3, iclass 32, count 0 2006.285.11:04:56.46#ibcon#about to read 4, iclass 32, count 0 2006.285.11:04:56.46#ibcon#read 4, iclass 32, count 0 2006.285.11:04:56.46#ibcon#about to read 5, iclass 32, count 0 2006.285.11:04:56.46#ibcon#read 5, iclass 32, count 0 2006.285.11:04:56.46#ibcon#about to read 6, iclass 32, count 0 2006.285.11:04:56.46#ibcon#read 6, iclass 32, count 0 2006.285.11:04:56.46#ibcon#end of sib2, iclass 32, count 0 2006.285.11:04:56.46#ibcon#*after write, iclass 32, count 0 2006.285.11:04:56.46#ibcon#*before return 0, iclass 32, count 0 2006.285.11:04:56.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:04:56.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:04:56.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:04:56.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:04:56.46$vck44/valo=4,624.99 2006.285.11:04:56.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.11:04:56.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.11:04:56.46#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:56.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:04:56.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:04:56.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:04:56.46#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:04:56.46#ibcon#first serial, iclass 34, count 0 2006.285.11:04:56.46#ibcon#enter sib2, iclass 34, count 0 2006.285.11:04:56.46#ibcon#flushed, iclass 34, count 0 2006.285.11:04:56.46#ibcon#about to write, iclass 34, count 0 2006.285.11:04:56.46#ibcon#wrote, iclass 34, count 0 2006.285.11:04:56.46#ibcon#about to read 3, iclass 34, count 0 2006.285.11:04:56.48#ibcon#read 3, iclass 34, count 0 2006.285.11:04:56.48#ibcon#about to read 4, iclass 34, count 0 2006.285.11:04:56.48#ibcon#read 4, iclass 34, count 0 2006.285.11:04:56.48#ibcon#about to read 5, iclass 34, count 0 2006.285.11:04:56.48#ibcon#read 5, iclass 34, count 0 2006.285.11:04:56.48#ibcon#about to read 6, iclass 34, count 0 2006.285.11:04:56.48#ibcon#read 6, iclass 34, count 0 2006.285.11:04:56.48#ibcon#end of sib2, iclass 34, count 0 2006.285.11:04:56.48#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:04:56.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:04:56.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:04:56.48#ibcon#*before write, iclass 34, count 0 2006.285.11:04:56.48#ibcon#enter sib2, iclass 34, count 0 2006.285.11:04:56.48#ibcon#flushed, iclass 34, count 0 2006.285.11:04:56.48#ibcon#about to write, iclass 34, count 0 2006.285.11:04:56.48#ibcon#wrote, iclass 34, count 0 2006.285.11:04:56.48#ibcon#about to read 3, iclass 34, count 0 2006.285.11:04:56.52#ibcon#read 3, iclass 34, count 0 2006.285.11:04:56.52#ibcon#about to read 4, iclass 34, count 0 2006.285.11:04:56.52#ibcon#read 4, iclass 34, count 0 2006.285.11:04:56.52#ibcon#about to read 5, iclass 34, count 0 2006.285.11:04:56.52#ibcon#read 5, iclass 34, count 0 2006.285.11:04:56.52#ibcon#about to read 6, iclass 34, count 0 2006.285.11:04:56.52#ibcon#read 6, iclass 34, count 0 2006.285.11:04:56.52#ibcon#end of sib2, iclass 34, count 0 2006.285.11:04:56.52#ibcon#*after write, iclass 34, count 0 2006.285.11:04:56.52#ibcon#*before return 0, iclass 34, count 0 2006.285.11:04:56.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:04:56.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:04:56.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:04:56.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:04:56.52$vck44/va=4,6 2006.285.11:04:56.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.11:04:56.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.11:04:56.52#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:56.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:04:56.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:04:56.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:04:56.58#ibcon#enter wrdev, iclass 36, count 2 2006.285.11:04:56.58#ibcon#first serial, iclass 36, count 2 2006.285.11:04:56.58#ibcon#enter sib2, iclass 36, count 2 2006.285.11:04:56.58#ibcon#flushed, iclass 36, count 2 2006.285.11:04:56.58#ibcon#about to write, iclass 36, count 2 2006.285.11:04:56.58#ibcon#wrote, iclass 36, count 2 2006.285.11:04:56.58#ibcon#about to read 3, iclass 36, count 2 2006.285.11:04:56.60#ibcon#read 3, iclass 36, count 2 2006.285.11:04:56.60#ibcon#about to read 4, iclass 36, count 2 2006.285.11:04:56.60#ibcon#read 4, iclass 36, count 2 2006.285.11:04:56.60#ibcon#about to read 5, iclass 36, count 2 2006.285.11:04:56.60#ibcon#read 5, iclass 36, count 2 2006.285.11:04:56.60#ibcon#about to read 6, iclass 36, count 2 2006.285.11:04:56.60#ibcon#read 6, iclass 36, count 2 2006.285.11:04:56.60#ibcon#end of sib2, iclass 36, count 2 2006.285.11:04:56.60#ibcon#*mode == 0, iclass 36, count 2 2006.285.11:04:56.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.11:04:56.60#ibcon#[25=AT04-06\r\n] 2006.285.11:04:56.60#ibcon#*before write, iclass 36, count 2 2006.285.11:04:56.60#ibcon#enter sib2, iclass 36, count 2 2006.285.11:04:56.60#ibcon#flushed, iclass 36, count 2 2006.285.11:04:56.60#ibcon#about to write, iclass 36, count 2 2006.285.11:04:56.60#ibcon#wrote, iclass 36, count 2 2006.285.11:04:56.60#ibcon#about to read 3, iclass 36, count 2 2006.285.11:04:56.63#ibcon#read 3, iclass 36, count 2 2006.285.11:04:56.63#ibcon#about to read 4, iclass 36, count 2 2006.285.11:04:56.63#ibcon#read 4, iclass 36, count 2 2006.285.11:04:56.63#ibcon#about to read 5, iclass 36, count 2 2006.285.11:04:56.63#ibcon#read 5, iclass 36, count 2 2006.285.11:04:56.63#ibcon#about to read 6, iclass 36, count 2 2006.285.11:04:56.63#ibcon#read 6, iclass 36, count 2 2006.285.11:04:56.63#ibcon#end of sib2, iclass 36, count 2 2006.285.11:04:56.63#ibcon#*after write, iclass 36, count 2 2006.285.11:04:56.63#ibcon#*before return 0, iclass 36, count 2 2006.285.11:04:56.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:04:56.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:04:56.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.11:04:56.63#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:56.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:04:56.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:04:56.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:04:56.75#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:04:56.75#ibcon#first serial, iclass 36, count 0 2006.285.11:04:56.75#ibcon#enter sib2, iclass 36, count 0 2006.285.11:04:56.75#ibcon#flushed, iclass 36, count 0 2006.285.11:04:56.75#ibcon#about to write, iclass 36, count 0 2006.285.11:04:56.75#ibcon#wrote, iclass 36, count 0 2006.285.11:04:56.75#ibcon#about to read 3, iclass 36, count 0 2006.285.11:04:56.77#ibcon#read 3, iclass 36, count 0 2006.285.11:04:56.77#ibcon#about to read 4, iclass 36, count 0 2006.285.11:04:56.77#ibcon#read 4, iclass 36, count 0 2006.285.11:04:56.77#ibcon#about to read 5, iclass 36, count 0 2006.285.11:04:56.77#ibcon#read 5, iclass 36, count 0 2006.285.11:04:56.77#ibcon#about to read 6, iclass 36, count 0 2006.285.11:04:56.77#ibcon#read 6, iclass 36, count 0 2006.285.11:04:56.77#ibcon#end of sib2, iclass 36, count 0 2006.285.11:04:56.77#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:04:56.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:04:56.77#ibcon#[25=USB\r\n] 2006.285.11:04:56.77#ibcon#*before write, iclass 36, count 0 2006.285.11:04:56.77#ibcon#enter sib2, iclass 36, count 0 2006.285.11:04:56.77#ibcon#flushed, iclass 36, count 0 2006.285.11:04:56.77#ibcon#about to write, iclass 36, count 0 2006.285.11:04:56.77#ibcon#wrote, iclass 36, count 0 2006.285.11:04:56.77#ibcon#about to read 3, iclass 36, count 0 2006.285.11:04:56.80#ibcon#read 3, iclass 36, count 0 2006.285.11:04:56.80#ibcon#about to read 4, iclass 36, count 0 2006.285.11:04:56.80#ibcon#read 4, iclass 36, count 0 2006.285.11:04:56.80#ibcon#about to read 5, iclass 36, count 0 2006.285.11:04:56.80#ibcon#read 5, iclass 36, count 0 2006.285.11:04:56.80#ibcon#about to read 6, iclass 36, count 0 2006.285.11:04:56.80#ibcon#read 6, iclass 36, count 0 2006.285.11:04:56.80#ibcon#end of sib2, iclass 36, count 0 2006.285.11:04:56.80#ibcon#*after write, iclass 36, count 0 2006.285.11:04:56.80#ibcon#*before return 0, iclass 36, count 0 2006.285.11:04:56.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:04:56.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:04:56.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:04:56.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:04:56.80$vck44/valo=5,734.99 2006.285.11:04:56.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.11:04:56.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.11:04:56.80#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:56.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:04:56.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:04:56.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:04:56.80#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:04:56.80#ibcon#first serial, iclass 38, count 0 2006.285.11:04:56.80#ibcon#enter sib2, iclass 38, count 0 2006.285.11:04:56.80#ibcon#flushed, iclass 38, count 0 2006.285.11:04:56.80#ibcon#about to write, iclass 38, count 0 2006.285.11:04:56.80#ibcon#wrote, iclass 38, count 0 2006.285.11:04:56.80#ibcon#about to read 3, iclass 38, count 0 2006.285.11:04:56.82#ibcon#read 3, iclass 38, count 0 2006.285.11:04:56.82#ibcon#about to read 4, iclass 38, count 0 2006.285.11:04:56.82#ibcon#read 4, iclass 38, count 0 2006.285.11:04:56.82#ibcon#about to read 5, iclass 38, count 0 2006.285.11:04:56.82#ibcon#read 5, iclass 38, count 0 2006.285.11:04:56.82#ibcon#about to read 6, iclass 38, count 0 2006.285.11:04:56.82#ibcon#read 6, iclass 38, count 0 2006.285.11:04:56.82#ibcon#end of sib2, iclass 38, count 0 2006.285.11:04:56.82#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:04:56.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:04:56.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:04:56.82#ibcon#*before write, iclass 38, count 0 2006.285.11:04:56.82#ibcon#enter sib2, iclass 38, count 0 2006.285.11:04:56.82#ibcon#flushed, iclass 38, count 0 2006.285.11:04:56.82#ibcon#about to write, iclass 38, count 0 2006.285.11:04:56.82#ibcon#wrote, iclass 38, count 0 2006.285.11:04:56.82#ibcon#about to read 3, iclass 38, count 0 2006.285.11:04:56.86#ibcon#read 3, iclass 38, count 0 2006.285.11:04:56.86#ibcon#about to read 4, iclass 38, count 0 2006.285.11:04:56.86#ibcon#read 4, iclass 38, count 0 2006.285.11:04:56.86#ibcon#about to read 5, iclass 38, count 0 2006.285.11:04:56.86#ibcon#read 5, iclass 38, count 0 2006.285.11:04:56.86#ibcon#about to read 6, iclass 38, count 0 2006.285.11:04:56.86#ibcon#read 6, iclass 38, count 0 2006.285.11:04:56.86#ibcon#end of sib2, iclass 38, count 0 2006.285.11:04:56.86#ibcon#*after write, iclass 38, count 0 2006.285.11:04:56.86#ibcon#*before return 0, iclass 38, count 0 2006.285.11:04:56.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:04:56.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:04:56.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:04:56.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:04:56.86$vck44/va=5,3 2006.285.11:04:56.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.11:04:56.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.11:04:56.86#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:56.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:04:56.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:04:56.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:04:56.92#ibcon#enter wrdev, iclass 40, count 2 2006.285.11:04:56.92#ibcon#first serial, iclass 40, count 2 2006.285.11:04:56.92#ibcon#enter sib2, iclass 40, count 2 2006.285.11:04:56.92#ibcon#flushed, iclass 40, count 2 2006.285.11:04:56.92#ibcon#about to write, iclass 40, count 2 2006.285.11:04:56.92#ibcon#wrote, iclass 40, count 2 2006.285.11:04:56.92#ibcon#about to read 3, iclass 40, count 2 2006.285.11:04:56.94#ibcon#read 3, iclass 40, count 2 2006.285.11:04:56.94#ibcon#about to read 4, iclass 40, count 2 2006.285.11:04:56.94#ibcon#read 4, iclass 40, count 2 2006.285.11:04:56.94#ibcon#about to read 5, iclass 40, count 2 2006.285.11:04:56.94#ibcon#read 5, iclass 40, count 2 2006.285.11:04:56.94#ibcon#about to read 6, iclass 40, count 2 2006.285.11:04:56.94#ibcon#read 6, iclass 40, count 2 2006.285.11:04:56.94#ibcon#end of sib2, iclass 40, count 2 2006.285.11:04:56.94#ibcon#*mode == 0, iclass 40, count 2 2006.285.11:04:56.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.11:04:56.94#ibcon#[25=AT05-03\r\n] 2006.285.11:04:56.94#ibcon#*before write, iclass 40, count 2 2006.285.11:04:56.94#ibcon#enter sib2, iclass 40, count 2 2006.285.11:04:56.94#ibcon#flushed, iclass 40, count 2 2006.285.11:04:56.94#ibcon#about to write, iclass 40, count 2 2006.285.11:04:56.94#ibcon#wrote, iclass 40, count 2 2006.285.11:04:56.94#ibcon#about to read 3, iclass 40, count 2 2006.285.11:04:56.97#ibcon#read 3, iclass 40, count 2 2006.285.11:04:56.97#ibcon#about to read 4, iclass 40, count 2 2006.285.11:04:56.97#ibcon#read 4, iclass 40, count 2 2006.285.11:04:56.97#ibcon#about to read 5, iclass 40, count 2 2006.285.11:04:56.97#ibcon#read 5, iclass 40, count 2 2006.285.11:04:56.97#ibcon#about to read 6, iclass 40, count 2 2006.285.11:04:56.97#ibcon#read 6, iclass 40, count 2 2006.285.11:04:56.97#ibcon#end of sib2, iclass 40, count 2 2006.285.11:04:56.97#ibcon#*after write, iclass 40, count 2 2006.285.11:04:56.97#ibcon#*before return 0, iclass 40, count 2 2006.285.11:04:56.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:04:56.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:04:56.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.11:04:56.97#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:56.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:04:57.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:04:57.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:04:57.09#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:04:57.09#ibcon#first serial, iclass 40, count 0 2006.285.11:04:57.09#ibcon#enter sib2, iclass 40, count 0 2006.285.11:04:57.09#ibcon#flushed, iclass 40, count 0 2006.285.11:04:57.09#ibcon#about to write, iclass 40, count 0 2006.285.11:04:57.09#ibcon#wrote, iclass 40, count 0 2006.285.11:04:57.09#ibcon#about to read 3, iclass 40, count 0 2006.285.11:04:57.11#ibcon#read 3, iclass 40, count 0 2006.285.11:04:57.11#ibcon#about to read 4, iclass 40, count 0 2006.285.11:04:57.11#ibcon#read 4, iclass 40, count 0 2006.285.11:04:57.11#ibcon#about to read 5, iclass 40, count 0 2006.285.11:04:57.11#ibcon#read 5, iclass 40, count 0 2006.285.11:04:57.11#ibcon#about to read 6, iclass 40, count 0 2006.285.11:04:57.11#ibcon#read 6, iclass 40, count 0 2006.285.11:04:57.11#ibcon#end of sib2, iclass 40, count 0 2006.285.11:04:57.11#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:04:57.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:04:57.11#ibcon#[25=USB\r\n] 2006.285.11:04:57.11#ibcon#*before write, iclass 40, count 0 2006.285.11:04:57.11#ibcon#enter sib2, iclass 40, count 0 2006.285.11:04:57.11#ibcon#flushed, iclass 40, count 0 2006.285.11:04:57.11#ibcon#about to write, iclass 40, count 0 2006.285.11:04:57.11#ibcon#wrote, iclass 40, count 0 2006.285.11:04:57.11#ibcon#about to read 3, iclass 40, count 0 2006.285.11:04:57.14#ibcon#read 3, iclass 40, count 0 2006.285.11:04:57.14#ibcon#about to read 4, iclass 40, count 0 2006.285.11:04:57.14#ibcon#read 4, iclass 40, count 0 2006.285.11:04:57.14#ibcon#about to read 5, iclass 40, count 0 2006.285.11:04:57.14#ibcon#read 5, iclass 40, count 0 2006.285.11:04:57.14#ibcon#about to read 6, iclass 40, count 0 2006.285.11:04:57.14#ibcon#read 6, iclass 40, count 0 2006.285.11:04:57.14#ibcon#end of sib2, iclass 40, count 0 2006.285.11:04:57.14#ibcon#*after write, iclass 40, count 0 2006.285.11:04:57.14#ibcon#*before return 0, iclass 40, count 0 2006.285.11:04:57.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:04:57.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:04:57.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:04:57.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:04:57.14$vck44/valo=6,814.99 2006.285.11:04:57.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.11:04:57.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.11:04:57.14#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:57.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:04:57.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:04:57.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:04:57.14#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:04:57.14#ibcon#first serial, iclass 4, count 0 2006.285.11:04:57.14#ibcon#enter sib2, iclass 4, count 0 2006.285.11:04:57.14#ibcon#flushed, iclass 4, count 0 2006.285.11:04:57.14#ibcon#about to write, iclass 4, count 0 2006.285.11:04:57.14#ibcon#wrote, iclass 4, count 0 2006.285.11:04:57.14#ibcon#about to read 3, iclass 4, count 0 2006.285.11:04:57.16#ibcon#read 3, iclass 4, count 0 2006.285.11:04:57.16#ibcon#about to read 4, iclass 4, count 0 2006.285.11:04:57.16#ibcon#read 4, iclass 4, count 0 2006.285.11:04:57.16#ibcon#about to read 5, iclass 4, count 0 2006.285.11:04:57.16#ibcon#read 5, iclass 4, count 0 2006.285.11:04:57.16#ibcon#about to read 6, iclass 4, count 0 2006.285.11:04:57.16#ibcon#read 6, iclass 4, count 0 2006.285.11:04:57.16#ibcon#end of sib2, iclass 4, count 0 2006.285.11:04:57.16#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:04:57.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:04:57.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:04:57.16#ibcon#*before write, iclass 4, count 0 2006.285.11:04:57.16#ibcon#enter sib2, iclass 4, count 0 2006.285.11:04:57.16#ibcon#flushed, iclass 4, count 0 2006.285.11:04:57.16#ibcon#about to write, iclass 4, count 0 2006.285.11:04:57.16#ibcon#wrote, iclass 4, count 0 2006.285.11:04:57.16#ibcon#about to read 3, iclass 4, count 0 2006.285.11:04:57.20#ibcon#read 3, iclass 4, count 0 2006.285.11:04:57.20#ibcon#about to read 4, iclass 4, count 0 2006.285.11:04:57.20#ibcon#read 4, iclass 4, count 0 2006.285.11:04:57.20#ibcon#about to read 5, iclass 4, count 0 2006.285.11:04:57.20#ibcon#read 5, iclass 4, count 0 2006.285.11:04:57.20#ibcon#about to read 6, iclass 4, count 0 2006.285.11:04:57.20#ibcon#read 6, iclass 4, count 0 2006.285.11:04:57.20#ibcon#end of sib2, iclass 4, count 0 2006.285.11:04:57.20#ibcon#*after write, iclass 4, count 0 2006.285.11:04:57.20#ibcon#*before return 0, iclass 4, count 0 2006.285.11:04:57.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:04:57.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:04:57.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:04:57.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:04:57.20$vck44/va=6,4 2006.285.11:04:57.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.11:04:57.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.11:04:57.20#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:57.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:04:57.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:04:57.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:04:57.26#ibcon#enter wrdev, iclass 6, count 2 2006.285.11:04:57.26#ibcon#first serial, iclass 6, count 2 2006.285.11:04:57.26#ibcon#enter sib2, iclass 6, count 2 2006.285.11:04:57.26#ibcon#flushed, iclass 6, count 2 2006.285.11:04:57.26#ibcon#about to write, iclass 6, count 2 2006.285.11:04:57.26#ibcon#wrote, iclass 6, count 2 2006.285.11:04:57.26#ibcon#about to read 3, iclass 6, count 2 2006.285.11:04:57.28#ibcon#read 3, iclass 6, count 2 2006.285.11:04:57.28#ibcon#about to read 4, iclass 6, count 2 2006.285.11:04:57.28#ibcon#read 4, iclass 6, count 2 2006.285.11:04:57.28#ibcon#about to read 5, iclass 6, count 2 2006.285.11:04:57.28#ibcon#read 5, iclass 6, count 2 2006.285.11:04:57.28#ibcon#about to read 6, iclass 6, count 2 2006.285.11:04:57.28#ibcon#read 6, iclass 6, count 2 2006.285.11:04:57.28#ibcon#end of sib2, iclass 6, count 2 2006.285.11:04:57.28#ibcon#*mode == 0, iclass 6, count 2 2006.285.11:04:57.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.11:04:57.28#ibcon#[25=AT06-04\r\n] 2006.285.11:04:57.28#ibcon#*before write, iclass 6, count 2 2006.285.11:04:57.28#ibcon#enter sib2, iclass 6, count 2 2006.285.11:04:57.28#ibcon#flushed, iclass 6, count 2 2006.285.11:04:57.28#ibcon#about to write, iclass 6, count 2 2006.285.11:04:57.28#ibcon#wrote, iclass 6, count 2 2006.285.11:04:57.28#ibcon#about to read 3, iclass 6, count 2 2006.285.11:04:57.31#ibcon#read 3, iclass 6, count 2 2006.285.11:04:57.31#ibcon#about to read 4, iclass 6, count 2 2006.285.11:04:57.31#ibcon#read 4, iclass 6, count 2 2006.285.11:04:57.31#ibcon#about to read 5, iclass 6, count 2 2006.285.11:04:57.31#ibcon#read 5, iclass 6, count 2 2006.285.11:04:57.31#ibcon#about to read 6, iclass 6, count 2 2006.285.11:04:57.31#ibcon#read 6, iclass 6, count 2 2006.285.11:04:57.31#ibcon#end of sib2, iclass 6, count 2 2006.285.11:04:57.31#ibcon#*after write, iclass 6, count 2 2006.285.11:04:57.31#ibcon#*before return 0, iclass 6, count 2 2006.285.11:04:57.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:04:57.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:04:57.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.11:04:57.31#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:57.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:04:57.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:04:57.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:04:57.43#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:04:57.43#ibcon#first serial, iclass 6, count 0 2006.285.11:04:57.43#ibcon#enter sib2, iclass 6, count 0 2006.285.11:04:57.43#ibcon#flushed, iclass 6, count 0 2006.285.11:04:57.43#ibcon#about to write, iclass 6, count 0 2006.285.11:04:57.43#ibcon#wrote, iclass 6, count 0 2006.285.11:04:57.43#ibcon#about to read 3, iclass 6, count 0 2006.285.11:04:57.45#ibcon#read 3, iclass 6, count 0 2006.285.11:04:57.45#ibcon#about to read 4, iclass 6, count 0 2006.285.11:04:57.45#ibcon#read 4, iclass 6, count 0 2006.285.11:04:57.45#ibcon#about to read 5, iclass 6, count 0 2006.285.11:04:57.45#ibcon#read 5, iclass 6, count 0 2006.285.11:04:57.45#ibcon#about to read 6, iclass 6, count 0 2006.285.11:04:57.45#ibcon#read 6, iclass 6, count 0 2006.285.11:04:57.45#ibcon#end of sib2, iclass 6, count 0 2006.285.11:04:57.45#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:04:57.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:04:57.45#ibcon#[25=USB\r\n] 2006.285.11:04:57.45#ibcon#*before write, iclass 6, count 0 2006.285.11:04:57.45#ibcon#enter sib2, iclass 6, count 0 2006.285.11:04:57.45#ibcon#flushed, iclass 6, count 0 2006.285.11:04:57.45#ibcon#about to write, iclass 6, count 0 2006.285.11:04:57.45#ibcon#wrote, iclass 6, count 0 2006.285.11:04:57.45#ibcon#about to read 3, iclass 6, count 0 2006.285.11:04:57.48#ibcon#read 3, iclass 6, count 0 2006.285.11:04:57.48#ibcon#about to read 4, iclass 6, count 0 2006.285.11:04:57.48#ibcon#read 4, iclass 6, count 0 2006.285.11:04:57.48#ibcon#about to read 5, iclass 6, count 0 2006.285.11:04:57.48#ibcon#read 5, iclass 6, count 0 2006.285.11:04:57.48#ibcon#about to read 6, iclass 6, count 0 2006.285.11:04:57.48#ibcon#read 6, iclass 6, count 0 2006.285.11:04:57.48#ibcon#end of sib2, iclass 6, count 0 2006.285.11:04:57.48#ibcon#*after write, iclass 6, count 0 2006.285.11:04:57.48#ibcon#*before return 0, iclass 6, count 0 2006.285.11:04:57.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:04:57.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:04:57.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:04:57.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:04:57.48$vck44/valo=7,864.99 2006.285.11:04:57.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.11:04:57.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.11:04:57.48#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:57.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:04:57.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:04:57.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:04:57.48#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:04:57.48#ibcon#first serial, iclass 10, count 0 2006.285.11:04:57.48#ibcon#enter sib2, iclass 10, count 0 2006.285.11:04:57.48#ibcon#flushed, iclass 10, count 0 2006.285.11:04:57.48#ibcon#about to write, iclass 10, count 0 2006.285.11:04:57.48#ibcon#wrote, iclass 10, count 0 2006.285.11:04:57.48#ibcon#about to read 3, iclass 10, count 0 2006.285.11:04:57.50#ibcon#read 3, iclass 10, count 0 2006.285.11:04:57.50#ibcon#about to read 4, iclass 10, count 0 2006.285.11:04:57.50#ibcon#read 4, iclass 10, count 0 2006.285.11:04:57.50#ibcon#about to read 5, iclass 10, count 0 2006.285.11:04:57.50#ibcon#read 5, iclass 10, count 0 2006.285.11:04:57.50#ibcon#about to read 6, iclass 10, count 0 2006.285.11:04:57.50#ibcon#read 6, iclass 10, count 0 2006.285.11:04:57.50#ibcon#end of sib2, iclass 10, count 0 2006.285.11:04:57.50#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:04:57.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:04:57.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:04:57.50#ibcon#*before write, iclass 10, count 0 2006.285.11:04:57.50#ibcon#enter sib2, iclass 10, count 0 2006.285.11:04:57.50#ibcon#flushed, iclass 10, count 0 2006.285.11:04:57.50#ibcon#about to write, iclass 10, count 0 2006.285.11:04:57.50#ibcon#wrote, iclass 10, count 0 2006.285.11:04:57.50#ibcon#about to read 3, iclass 10, count 0 2006.285.11:04:57.54#ibcon#read 3, iclass 10, count 0 2006.285.11:04:57.54#ibcon#about to read 4, iclass 10, count 0 2006.285.11:04:57.54#ibcon#read 4, iclass 10, count 0 2006.285.11:04:57.54#ibcon#about to read 5, iclass 10, count 0 2006.285.11:04:57.54#ibcon#read 5, iclass 10, count 0 2006.285.11:04:57.54#ibcon#about to read 6, iclass 10, count 0 2006.285.11:04:57.54#ibcon#read 6, iclass 10, count 0 2006.285.11:04:57.54#ibcon#end of sib2, iclass 10, count 0 2006.285.11:04:57.54#ibcon#*after write, iclass 10, count 0 2006.285.11:04:57.54#ibcon#*before return 0, iclass 10, count 0 2006.285.11:04:57.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:04:57.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:04:57.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:04:57.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:04:57.54$vck44/va=7,4 2006.285.11:04:57.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.11:04:57.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.11:04:57.54#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:57.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:04:57.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:04:57.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:04:57.60#ibcon#enter wrdev, iclass 12, count 2 2006.285.11:04:57.60#ibcon#first serial, iclass 12, count 2 2006.285.11:04:57.60#ibcon#enter sib2, iclass 12, count 2 2006.285.11:04:57.60#ibcon#flushed, iclass 12, count 2 2006.285.11:04:57.60#ibcon#about to write, iclass 12, count 2 2006.285.11:04:57.60#ibcon#wrote, iclass 12, count 2 2006.285.11:04:57.60#ibcon#about to read 3, iclass 12, count 2 2006.285.11:04:57.62#ibcon#read 3, iclass 12, count 2 2006.285.11:04:57.62#ibcon#about to read 4, iclass 12, count 2 2006.285.11:04:57.62#ibcon#read 4, iclass 12, count 2 2006.285.11:04:57.62#ibcon#about to read 5, iclass 12, count 2 2006.285.11:04:57.62#ibcon#read 5, iclass 12, count 2 2006.285.11:04:57.62#ibcon#about to read 6, iclass 12, count 2 2006.285.11:04:57.62#ibcon#read 6, iclass 12, count 2 2006.285.11:04:57.62#ibcon#end of sib2, iclass 12, count 2 2006.285.11:04:57.62#ibcon#*mode == 0, iclass 12, count 2 2006.285.11:04:57.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.11:04:57.62#ibcon#[25=AT07-04\r\n] 2006.285.11:04:57.62#ibcon#*before write, iclass 12, count 2 2006.285.11:04:57.62#ibcon#enter sib2, iclass 12, count 2 2006.285.11:04:57.62#ibcon#flushed, iclass 12, count 2 2006.285.11:04:57.62#ibcon#about to write, iclass 12, count 2 2006.285.11:04:57.62#ibcon#wrote, iclass 12, count 2 2006.285.11:04:57.62#ibcon#about to read 3, iclass 12, count 2 2006.285.11:04:57.65#ibcon#read 3, iclass 12, count 2 2006.285.11:04:57.65#ibcon#about to read 4, iclass 12, count 2 2006.285.11:04:57.65#ibcon#read 4, iclass 12, count 2 2006.285.11:04:57.65#ibcon#about to read 5, iclass 12, count 2 2006.285.11:04:57.65#ibcon#read 5, iclass 12, count 2 2006.285.11:04:57.65#ibcon#about to read 6, iclass 12, count 2 2006.285.11:04:57.65#ibcon#read 6, iclass 12, count 2 2006.285.11:04:57.65#ibcon#end of sib2, iclass 12, count 2 2006.285.11:04:57.65#ibcon#*after write, iclass 12, count 2 2006.285.11:04:57.65#ibcon#*before return 0, iclass 12, count 2 2006.285.11:04:57.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:04:57.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:04:57.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.11:04:57.65#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:57.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:04:57.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:04:57.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:04:57.77#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:04:57.77#ibcon#first serial, iclass 12, count 0 2006.285.11:04:57.77#ibcon#enter sib2, iclass 12, count 0 2006.285.11:04:57.77#ibcon#flushed, iclass 12, count 0 2006.285.11:04:57.77#ibcon#about to write, iclass 12, count 0 2006.285.11:04:57.77#ibcon#wrote, iclass 12, count 0 2006.285.11:04:57.77#ibcon#about to read 3, iclass 12, count 0 2006.285.11:04:57.79#ibcon#read 3, iclass 12, count 0 2006.285.11:04:57.79#ibcon#about to read 4, iclass 12, count 0 2006.285.11:04:57.79#ibcon#read 4, iclass 12, count 0 2006.285.11:04:57.79#ibcon#about to read 5, iclass 12, count 0 2006.285.11:04:57.79#ibcon#read 5, iclass 12, count 0 2006.285.11:04:57.79#ibcon#about to read 6, iclass 12, count 0 2006.285.11:04:57.79#ibcon#read 6, iclass 12, count 0 2006.285.11:04:57.79#ibcon#end of sib2, iclass 12, count 0 2006.285.11:04:57.79#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:04:57.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:04:57.79#ibcon#[25=USB\r\n] 2006.285.11:04:57.79#ibcon#*before write, iclass 12, count 0 2006.285.11:04:57.79#ibcon#enter sib2, iclass 12, count 0 2006.285.11:04:57.79#ibcon#flushed, iclass 12, count 0 2006.285.11:04:57.79#ibcon#about to write, iclass 12, count 0 2006.285.11:04:57.79#ibcon#wrote, iclass 12, count 0 2006.285.11:04:57.79#ibcon#about to read 3, iclass 12, count 0 2006.285.11:04:57.82#ibcon#read 3, iclass 12, count 0 2006.285.11:04:57.82#ibcon#about to read 4, iclass 12, count 0 2006.285.11:04:57.82#ibcon#read 4, iclass 12, count 0 2006.285.11:04:57.82#ibcon#about to read 5, iclass 12, count 0 2006.285.11:04:57.82#ibcon#read 5, iclass 12, count 0 2006.285.11:04:57.82#ibcon#about to read 6, iclass 12, count 0 2006.285.11:04:57.82#ibcon#read 6, iclass 12, count 0 2006.285.11:04:57.82#ibcon#end of sib2, iclass 12, count 0 2006.285.11:04:57.82#ibcon#*after write, iclass 12, count 0 2006.285.11:04:57.82#ibcon#*before return 0, iclass 12, count 0 2006.285.11:04:57.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:04:57.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:04:57.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:04:57.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:04:57.82$vck44/valo=8,884.99 2006.285.11:04:57.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.11:04:57.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.11:04:57.82#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:57.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:04:57.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:04:57.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:04:57.82#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:04:57.82#ibcon#first serial, iclass 14, count 0 2006.285.11:04:57.82#ibcon#enter sib2, iclass 14, count 0 2006.285.11:04:57.82#ibcon#flushed, iclass 14, count 0 2006.285.11:04:57.82#ibcon#about to write, iclass 14, count 0 2006.285.11:04:57.82#ibcon#wrote, iclass 14, count 0 2006.285.11:04:57.82#ibcon#about to read 3, iclass 14, count 0 2006.285.11:04:57.84#ibcon#read 3, iclass 14, count 0 2006.285.11:04:57.84#ibcon#about to read 4, iclass 14, count 0 2006.285.11:04:57.84#ibcon#read 4, iclass 14, count 0 2006.285.11:04:57.84#ibcon#about to read 5, iclass 14, count 0 2006.285.11:04:57.84#ibcon#read 5, iclass 14, count 0 2006.285.11:04:57.84#ibcon#about to read 6, iclass 14, count 0 2006.285.11:04:57.84#ibcon#read 6, iclass 14, count 0 2006.285.11:04:57.84#ibcon#end of sib2, iclass 14, count 0 2006.285.11:04:57.84#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:04:57.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:04:57.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:04:57.84#ibcon#*before write, iclass 14, count 0 2006.285.11:04:57.84#ibcon#enter sib2, iclass 14, count 0 2006.285.11:04:57.84#ibcon#flushed, iclass 14, count 0 2006.285.11:04:57.84#ibcon#about to write, iclass 14, count 0 2006.285.11:04:57.84#ibcon#wrote, iclass 14, count 0 2006.285.11:04:57.84#ibcon#about to read 3, iclass 14, count 0 2006.285.11:04:57.88#ibcon#read 3, iclass 14, count 0 2006.285.11:04:57.88#ibcon#about to read 4, iclass 14, count 0 2006.285.11:04:57.88#ibcon#read 4, iclass 14, count 0 2006.285.11:04:57.88#ibcon#about to read 5, iclass 14, count 0 2006.285.11:04:57.88#ibcon#read 5, iclass 14, count 0 2006.285.11:04:57.88#ibcon#about to read 6, iclass 14, count 0 2006.285.11:04:57.88#ibcon#read 6, iclass 14, count 0 2006.285.11:04:57.88#ibcon#end of sib2, iclass 14, count 0 2006.285.11:04:57.88#ibcon#*after write, iclass 14, count 0 2006.285.11:04:57.88#ibcon#*before return 0, iclass 14, count 0 2006.285.11:04:57.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:04:57.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:04:57.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:04:57.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:04:57.88$vck44/va=8,3 2006.285.11:04:57.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.11:04:57.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.11:04:57.88#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:57.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:04:57.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:04:57.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:04:57.94#ibcon#enter wrdev, iclass 16, count 2 2006.285.11:04:57.94#ibcon#first serial, iclass 16, count 2 2006.285.11:04:57.94#ibcon#enter sib2, iclass 16, count 2 2006.285.11:04:57.94#ibcon#flushed, iclass 16, count 2 2006.285.11:04:57.94#ibcon#about to write, iclass 16, count 2 2006.285.11:04:57.94#ibcon#wrote, iclass 16, count 2 2006.285.11:04:57.94#ibcon#about to read 3, iclass 16, count 2 2006.285.11:04:57.96#ibcon#read 3, iclass 16, count 2 2006.285.11:04:57.96#ibcon#about to read 4, iclass 16, count 2 2006.285.11:04:57.96#ibcon#read 4, iclass 16, count 2 2006.285.11:04:57.96#ibcon#about to read 5, iclass 16, count 2 2006.285.11:04:57.96#ibcon#read 5, iclass 16, count 2 2006.285.11:04:57.96#ibcon#about to read 6, iclass 16, count 2 2006.285.11:04:57.96#ibcon#read 6, iclass 16, count 2 2006.285.11:04:57.96#ibcon#end of sib2, iclass 16, count 2 2006.285.11:04:57.96#ibcon#*mode == 0, iclass 16, count 2 2006.285.11:04:57.96#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.11:04:57.96#ibcon#[25=AT08-03\r\n] 2006.285.11:04:57.96#ibcon#*before write, iclass 16, count 2 2006.285.11:04:57.96#ibcon#enter sib2, iclass 16, count 2 2006.285.11:04:57.96#ibcon#flushed, iclass 16, count 2 2006.285.11:04:57.96#ibcon#about to write, iclass 16, count 2 2006.285.11:04:57.96#ibcon#wrote, iclass 16, count 2 2006.285.11:04:57.96#ibcon#about to read 3, iclass 16, count 2 2006.285.11:04:57.99#ibcon#read 3, iclass 16, count 2 2006.285.11:04:57.99#ibcon#about to read 4, iclass 16, count 2 2006.285.11:04:57.99#ibcon#read 4, iclass 16, count 2 2006.285.11:04:57.99#ibcon#about to read 5, iclass 16, count 2 2006.285.11:04:57.99#ibcon#read 5, iclass 16, count 2 2006.285.11:04:57.99#ibcon#about to read 6, iclass 16, count 2 2006.285.11:04:57.99#ibcon#read 6, iclass 16, count 2 2006.285.11:04:57.99#ibcon#end of sib2, iclass 16, count 2 2006.285.11:04:57.99#ibcon#*after write, iclass 16, count 2 2006.285.11:04:57.99#ibcon#*before return 0, iclass 16, count 2 2006.285.11:04:57.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:04:57.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:04:57.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.11:04:57.99#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:57.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:04:58.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:04:58.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:04:58.11#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:04:58.11#ibcon#first serial, iclass 16, count 0 2006.285.11:04:58.11#ibcon#enter sib2, iclass 16, count 0 2006.285.11:04:58.11#ibcon#flushed, iclass 16, count 0 2006.285.11:04:58.11#ibcon#about to write, iclass 16, count 0 2006.285.11:04:58.11#ibcon#wrote, iclass 16, count 0 2006.285.11:04:58.11#ibcon#about to read 3, iclass 16, count 0 2006.285.11:04:58.13#ibcon#read 3, iclass 16, count 0 2006.285.11:04:58.13#ibcon#about to read 4, iclass 16, count 0 2006.285.11:04:58.13#ibcon#read 4, iclass 16, count 0 2006.285.11:04:58.13#ibcon#about to read 5, iclass 16, count 0 2006.285.11:04:58.13#ibcon#read 5, iclass 16, count 0 2006.285.11:04:58.13#ibcon#about to read 6, iclass 16, count 0 2006.285.11:04:58.13#ibcon#read 6, iclass 16, count 0 2006.285.11:04:58.13#ibcon#end of sib2, iclass 16, count 0 2006.285.11:04:58.13#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:04:58.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:04:58.13#ibcon#[25=USB\r\n] 2006.285.11:04:58.13#ibcon#*before write, iclass 16, count 0 2006.285.11:04:58.13#ibcon#enter sib2, iclass 16, count 0 2006.285.11:04:58.13#ibcon#flushed, iclass 16, count 0 2006.285.11:04:58.13#ibcon#about to write, iclass 16, count 0 2006.285.11:04:58.13#ibcon#wrote, iclass 16, count 0 2006.285.11:04:58.13#ibcon#about to read 3, iclass 16, count 0 2006.285.11:04:58.16#ibcon#read 3, iclass 16, count 0 2006.285.11:04:58.16#ibcon#about to read 4, iclass 16, count 0 2006.285.11:04:58.16#ibcon#read 4, iclass 16, count 0 2006.285.11:04:58.16#ibcon#about to read 5, iclass 16, count 0 2006.285.11:04:58.16#ibcon#read 5, iclass 16, count 0 2006.285.11:04:58.16#ibcon#about to read 6, iclass 16, count 0 2006.285.11:04:58.16#ibcon#read 6, iclass 16, count 0 2006.285.11:04:58.16#ibcon#end of sib2, iclass 16, count 0 2006.285.11:04:58.16#ibcon#*after write, iclass 16, count 0 2006.285.11:04:58.16#ibcon#*before return 0, iclass 16, count 0 2006.285.11:04:58.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:04:58.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:04:58.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:04:58.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:04:58.16$vck44/vblo=1,629.99 2006.285.11:04:58.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.11:04:58.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.11:04:58.16#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:58.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:04:58.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:04:58.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:04:58.16#ibcon#enter wrdev, iclass 18, count 0 2006.285.11:04:58.16#ibcon#first serial, iclass 18, count 0 2006.285.11:04:58.16#ibcon#enter sib2, iclass 18, count 0 2006.285.11:04:58.16#ibcon#flushed, iclass 18, count 0 2006.285.11:04:58.16#ibcon#about to write, iclass 18, count 0 2006.285.11:04:58.16#ibcon#wrote, iclass 18, count 0 2006.285.11:04:58.16#ibcon#about to read 3, iclass 18, count 0 2006.285.11:04:58.18#ibcon#read 3, iclass 18, count 0 2006.285.11:04:58.18#ibcon#about to read 4, iclass 18, count 0 2006.285.11:04:58.18#ibcon#read 4, iclass 18, count 0 2006.285.11:04:58.18#ibcon#about to read 5, iclass 18, count 0 2006.285.11:04:58.18#ibcon#read 5, iclass 18, count 0 2006.285.11:04:58.18#ibcon#about to read 6, iclass 18, count 0 2006.285.11:04:58.18#ibcon#read 6, iclass 18, count 0 2006.285.11:04:58.18#ibcon#end of sib2, iclass 18, count 0 2006.285.11:04:58.18#ibcon#*mode == 0, iclass 18, count 0 2006.285.11:04:58.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.11:04:58.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:04:58.18#ibcon#*before write, iclass 18, count 0 2006.285.11:04:58.18#ibcon#enter sib2, iclass 18, count 0 2006.285.11:04:58.18#ibcon#flushed, iclass 18, count 0 2006.285.11:04:58.18#ibcon#about to write, iclass 18, count 0 2006.285.11:04:58.18#ibcon#wrote, iclass 18, count 0 2006.285.11:04:58.18#ibcon#about to read 3, iclass 18, count 0 2006.285.11:04:58.22#ibcon#read 3, iclass 18, count 0 2006.285.11:04:58.22#ibcon#about to read 4, iclass 18, count 0 2006.285.11:04:58.22#ibcon#read 4, iclass 18, count 0 2006.285.11:04:58.22#ibcon#about to read 5, iclass 18, count 0 2006.285.11:04:58.22#ibcon#read 5, iclass 18, count 0 2006.285.11:04:58.22#ibcon#about to read 6, iclass 18, count 0 2006.285.11:04:58.22#ibcon#read 6, iclass 18, count 0 2006.285.11:04:58.22#ibcon#end of sib2, iclass 18, count 0 2006.285.11:04:58.22#ibcon#*after write, iclass 18, count 0 2006.285.11:04:58.22#ibcon#*before return 0, iclass 18, count 0 2006.285.11:04:58.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:04:58.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:04:58.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.11:04:58.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.11:04:58.22$vck44/vb=1,4 2006.285.11:04:58.22#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.11:04:58.22#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.11:04:58.22#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:58.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:04:58.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:04:58.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:04:58.22#ibcon#enter wrdev, iclass 20, count 2 2006.285.11:04:58.22#ibcon#first serial, iclass 20, count 2 2006.285.11:04:58.22#ibcon#enter sib2, iclass 20, count 2 2006.285.11:04:58.22#ibcon#flushed, iclass 20, count 2 2006.285.11:04:58.22#ibcon#about to write, iclass 20, count 2 2006.285.11:04:58.22#ibcon#wrote, iclass 20, count 2 2006.285.11:04:58.22#ibcon#about to read 3, iclass 20, count 2 2006.285.11:04:58.24#ibcon#read 3, iclass 20, count 2 2006.285.11:04:58.24#ibcon#about to read 4, iclass 20, count 2 2006.285.11:04:58.24#ibcon#read 4, iclass 20, count 2 2006.285.11:04:58.24#ibcon#about to read 5, iclass 20, count 2 2006.285.11:04:58.24#ibcon#read 5, iclass 20, count 2 2006.285.11:04:58.24#ibcon#about to read 6, iclass 20, count 2 2006.285.11:04:58.24#ibcon#read 6, iclass 20, count 2 2006.285.11:04:58.24#ibcon#end of sib2, iclass 20, count 2 2006.285.11:04:58.24#ibcon#*mode == 0, iclass 20, count 2 2006.285.11:04:58.24#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.11:04:58.24#ibcon#[27=AT01-04\r\n] 2006.285.11:04:58.24#ibcon#*before write, iclass 20, count 2 2006.285.11:04:58.24#ibcon#enter sib2, iclass 20, count 2 2006.285.11:04:58.24#ibcon#flushed, iclass 20, count 2 2006.285.11:04:58.24#ibcon#about to write, iclass 20, count 2 2006.285.11:04:58.24#ibcon#wrote, iclass 20, count 2 2006.285.11:04:58.24#ibcon#about to read 3, iclass 20, count 2 2006.285.11:04:58.27#ibcon#read 3, iclass 20, count 2 2006.285.11:04:58.27#ibcon#about to read 4, iclass 20, count 2 2006.285.11:04:58.27#ibcon#read 4, iclass 20, count 2 2006.285.11:04:58.27#ibcon#about to read 5, iclass 20, count 2 2006.285.11:04:58.27#ibcon#read 5, iclass 20, count 2 2006.285.11:04:58.27#ibcon#about to read 6, iclass 20, count 2 2006.285.11:04:58.27#ibcon#read 6, iclass 20, count 2 2006.285.11:04:58.27#ibcon#end of sib2, iclass 20, count 2 2006.285.11:04:58.27#ibcon#*after write, iclass 20, count 2 2006.285.11:04:58.27#ibcon#*before return 0, iclass 20, count 2 2006.285.11:04:58.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:04:58.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:04:58.27#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.11:04:58.27#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:58.27#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:04:58.39#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:04:58.39#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:04:58.39#ibcon#enter wrdev, iclass 20, count 0 2006.285.11:04:58.39#ibcon#first serial, iclass 20, count 0 2006.285.11:04:58.39#ibcon#enter sib2, iclass 20, count 0 2006.285.11:04:58.39#ibcon#flushed, iclass 20, count 0 2006.285.11:04:58.39#ibcon#about to write, iclass 20, count 0 2006.285.11:04:58.39#ibcon#wrote, iclass 20, count 0 2006.285.11:04:58.39#ibcon#about to read 3, iclass 20, count 0 2006.285.11:04:58.41#ibcon#read 3, iclass 20, count 0 2006.285.11:04:58.41#ibcon#about to read 4, iclass 20, count 0 2006.285.11:04:58.41#ibcon#read 4, iclass 20, count 0 2006.285.11:04:58.41#ibcon#about to read 5, iclass 20, count 0 2006.285.11:04:58.41#ibcon#read 5, iclass 20, count 0 2006.285.11:04:58.41#ibcon#about to read 6, iclass 20, count 0 2006.285.11:04:58.41#ibcon#read 6, iclass 20, count 0 2006.285.11:04:58.41#ibcon#end of sib2, iclass 20, count 0 2006.285.11:04:58.41#ibcon#*mode == 0, iclass 20, count 0 2006.285.11:04:58.41#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.11:04:58.41#ibcon#[27=USB\r\n] 2006.285.11:04:58.41#ibcon#*before write, iclass 20, count 0 2006.285.11:04:58.41#ibcon#enter sib2, iclass 20, count 0 2006.285.11:04:58.41#ibcon#flushed, iclass 20, count 0 2006.285.11:04:58.41#ibcon#about to write, iclass 20, count 0 2006.285.11:04:58.41#ibcon#wrote, iclass 20, count 0 2006.285.11:04:58.41#ibcon#about to read 3, iclass 20, count 0 2006.285.11:04:58.44#ibcon#read 3, iclass 20, count 0 2006.285.11:04:58.44#ibcon#about to read 4, iclass 20, count 0 2006.285.11:04:58.44#ibcon#read 4, iclass 20, count 0 2006.285.11:04:58.44#ibcon#about to read 5, iclass 20, count 0 2006.285.11:04:58.44#ibcon#read 5, iclass 20, count 0 2006.285.11:04:58.44#ibcon#about to read 6, iclass 20, count 0 2006.285.11:04:58.44#ibcon#read 6, iclass 20, count 0 2006.285.11:04:58.44#ibcon#end of sib2, iclass 20, count 0 2006.285.11:04:58.44#ibcon#*after write, iclass 20, count 0 2006.285.11:04:58.44#ibcon#*before return 0, iclass 20, count 0 2006.285.11:04:58.44#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:04:58.44#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:04:58.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.11:04:58.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.11:04:58.44$vck44/vblo=2,634.99 2006.285.11:04:58.44#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.11:04:58.44#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.11:04:58.44#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:58.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:04:58.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:04:58.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:04:58.44#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:04:58.44#ibcon#first serial, iclass 22, count 0 2006.285.11:04:58.44#ibcon#enter sib2, iclass 22, count 0 2006.285.11:04:58.44#ibcon#flushed, iclass 22, count 0 2006.285.11:04:58.44#ibcon#about to write, iclass 22, count 0 2006.285.11:04:58.44#ibcon#wrote, iclass 22, count 0 2006.285.11:04:58.44#ibcon#about to read 3, iclass 22, count 0 2006.285.11:04:58.46#ibcon#read 3, iclass 22, count 0 2006.285.11:04:58.46#ibcon#about to read 4, iclass 22, count 0 2006.285.11:04:58.46#ibcon#read 4, iclass 22, count 0 2006.285.11:04:58.46#ibcon#about to read 5, iclass 22, count 0 2006.285.11:04:58.46#ibcon#read 5, iclass 22, count 0 2006.285.11:04:58.46#ibcon#about to read 6, iclass 22, count 0 2006.285.11:04:58.46#ibcon#read 6, iclass 22, count 0 2006.285.11:04:58.46#ibcon#end of sib2, iclass 22, count 0 2006.285.11:04:58.46#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:04:58.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:04:58.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:04:58.46#ibcon#*before write, iclass 22, count 0 2006.285.11:04:58.46#ibcon#enter sib2, iclass 22, count 0 2006.285.11:04:58.46#ibcon#flushed, iclass 22, count 0 2006.285.11:04:58.46#ibcon#about to write, iclass 22, count 0 2006.285.11:04:58.46#ibcon#wrote, iclass 22, count 0 2006.285.11:04:58.46#ibcon#about to read 3, iclass 22, count 0 2006.285.11:04:58.50#ibcon#read 3, iclass 22, count 0 2006.285.11:04:58.50#ibcon#about to read 4, iclass 22, count 0 2006.285.11:04:58.50#ibcon#read 4, iclass 22, count 0 2006.285.11:04:58.50#ibcon#about to read 5, iclass 22, count 0 2006.285.11:04:58.50#ibcon#read 5, iclass 22, count 0 2006.285.11:04:58.50#ibcon#about to read 6, iclass 22, count 0 2006.285.11:04:58.50#ibcon#read 6, iclass 22, count 0 2006.285.11:04:58.50#ibcon#end of sib2, iclass 22, count 0 2006.285.11:04:58.50#ibcon#*after write, iclass 22, count 0 2006.285.11:04:58.50#ibcon#*before return 0, iclass 22, count 0 2006.285.11:04:58.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:04:58.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:04:58.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:04:58.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:04:58.50$vck44/vb=2,5 2006.285.11:04:58.50#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.11:04:58.50#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.11:04:58.50#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:58.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:04:58.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:04:58.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:04:58.56#ibcon#enter wrdev, iclass 24, count 2 2006.285.11:04:58.56#ibcon#first serial, iclass 24, count 2 2006.285.11:04:58.56#ibcon#enter sib2, iclass 24, count 2 2006.285.11:04:58.56#ibcon#flushed, iclass 24, count 2 2006.285.11:04:58.56#ibcon#about to write, iclass 24, count 2 2006.285.11:04:58.56#ibcon#wrote, iclass 24, count 2 2006.285.11:04:58.56#ibcon#about to read 3, iclass 24, count 2 2006.285.11:04:58.58#ibcon#read 3, iclass 24, count 2 2006.285.11:04:58.58#ibcon#about to read 4, iclass 24, count 2 2006.285.11:04:58.58#ibcon#read 4, iclass 24, count 2 2006.285.11:04:58.58#ibcon#about to read 5, iclass 24, count 2 2006.285.11:04:58.58#ibcon#read 5, iclass 24, count 2 2006.285.11:04:58.58#ibcon#about to read 6, iclass 24, count 2 2006.285.11:04:58.58#ibcon#read 6, iclass 24, count 2 2006.285.11:04:58.58#ibcon#end of sib2, iclass 24, count 2 2006.285.11:04:58.58#ibcon#*mode == 0, iclass 24, count 2 2006.285.11:04:58.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.11:04:58.58#ibcon#[27=AT02-05\r\n] 2006.285.11:04:58.58#ibcon#*before write, iclass 24, count 2 2006.285.11:04:58.58#ibcon#enter sib2, iclass 24, count 2 2006.285.11:04:58.58#ibcon#flushed, iclass 24, count 2 2006.285.11:04:58.58#ibcon#about to write, iclass 24, count 2 2006.285.11:04:58.58#ibcon#wrote, iclass 24, count 2 2006.285.11:04:58.58#ibcon#about to read 3, iclass 24, count 2 2006.285.11:04:58.61#ibcon#read 3, iclass 24, count 2 2006.285.11:04:58.61#ibcon#about to read 4, iclass 24, count 2 2006.285.11:04:58.61#ibcon#read 4, iclass 24, count 2 2006.285.11:04:58.61#ibcon#about to read 5, iclass 24, count 2 2006.285.11:04:58.61#ibcon#read 5, iclass 24, count 2 2006.285.11:04:58.61#ibcon#about to read 6, iclass 24, count 2 2006.285.11:04:58.61#ibcon#read 6, iclass 24, count 2 2006.285.11:04:58.61#ibcon#end of sib2, iclass 24, count 2 2006.285.11:04:58.61#ibcon#*after write, iclass 24, count 2 2006.285.11:04:58.61#ibcon#*before return 0, iclass 24, count 2 2006.285.11:04:58.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:04:58.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:04:58.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.11:04:58.61#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:58.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:04:58.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:04:58.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:04:58.73#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:04:58.73#ibcon#first serial, iclass 24, count 0 2006.285.11:04:58.73#ibcon#enter sib2, iclass 24, count 0 2006.285.11:04:58.73#ibcon#flushed, iclass 24, count 0 2006.285.11:04:58.73#ibcon#about to write, iclass 24, count 0 2006.285.11:04:58.73#ibcon#wrote, iclass 24, count 0 2006.285.11:04:58.73#ibcon#about to read 3, iclass 24, count 0 2006.285.11:04:58.75#ibcon#read 3, iclass 24, count 0 2006.285.11:04:58.75#ibcon#about to read 4, iclass 24, count 0 2006.285.11:04:58.75#ibcon#read 4, iclass 24, count 0 2006.285.11:04:58.75#ibcon#about to read 5, iclass 24, count 0 2006.285.11:04:58.75#ibcon#read 5, iclass 24, count 0 2006.285.11:04:58.75#ibcon#about to read 6, iclass 24, count 0 2006.285.11:04:58.75#ibcon#read 6, iclass 24, count 0 2006.285.11:04:58.75#ibcon#end of sib2, iclass 24, count 0 2006.285.11:04:58.75#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:04:58.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:04:58.75#ibcon#[27=USB\r\n] 2006.285.11:04:58.75#ibcon#*before write, iclass 24, count 0 2006.285.11:04:58.75#ibcon#enter sib2, iclass 24, count 0 2006.285.11:04:58.75#ibcon#flushed, iclass 24, count 0 2006.285.11:04:58.75#ibcon#about to write, iclass 24, count 0 2006.285.11:04:58.75#ibcon#wrote, iclass 24, count 0 2006.285.11:04:58.75#ibcon#about to read 3, iclass 24, count 0 2006.285.11:04:58.78#ibcon#read 3, iclass 24, count 0 2006.285.11:04:58.78#ibcon#about to read 4, iclass 24, count 0 2006.285.11:04:58.78#ibcon#read 4, iclass 24, count 0 2006.285.11:04:58.78#ibcon#about to read 5, iclass 24, count 0 2006.285.11:04:58.78#ibcon#read 5, iclass 24, count 0 2006.285.11:04:58.78#ibcon#about to read 6, iclass 24, count 0 2006.285.11:04:58.78#ibcon#read 6, iclass 24, count 0 2006.285.11:04:58.78#ibcon#end of sib2, iclass 24, count 0 2006.285.11:04:58.78#ibcon#*after write, iclass 24, count 0 2006.285.11:04:58.78#ibcon#*before return 0, iclass 24, count 0 2006.285.11:04:58.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:04:58.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:04:58.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:04:58.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:04:58.78$vck44/vblo=3,649.99 2006.285.11:04:58.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.11:04:58.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.11:04:58.78#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:58.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:04:58.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:04:58.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:04:58.78#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:04:58.78#ibcon#first serial, iclass 26, count 0 2006.285.11:04:58.78#ibcon#enter sib2, iclass 26, count 0 2006.285.11:04:58.78#ibcon#flushed, iclass 26, count 0 2006.285.11:04:58.78#ibcon#about to write, iclass 26, count 0 2006.285.11:04:58.78#ibcon#wrote, iclass 26, count 0 2006.285.11:04:58.78#ibcon#about to read 3, iclass 26, count 0 2006.285.11:04:58.80#ibcon#read 3, iclass 26, count 0 2006.285.11:04:58.80#ibcon#about to read 4, iclass 26, count 0 2006.285.11:04:58.80#ibcon#read 4, iclass 26, count 0 2006.285.11:04:58.80#ibcon#about to read 5, iclass 26, count 0 2006.285.11:04:58.80#ibcon#read 5, iclass 26, count 0 2006.285.11:04:58.80#ibcon#about to read 6, iclass 26, count 0 2006.285.11:04:58.80#ibcon#read 6, iclass 26, count 0 2006.285.11:04:58.80#ibcon#end of sib2, iclass 26, count 0 2006.285.11:04:58.80#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:04:58.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:04:58.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:04:58.80#ibcon#*before write, iclass 26, count 0 2006.285.11:04:58.80#ibcon#enter sib2, iclass 26, count 0 2006.285.11:04:58.80#ibcon#flushed, iclass 26, count 0 2006.285.11:04:58.80#ibcon#about to write, iclass 26, count 0 2006.285.11:04:58.80#ibcon#wrote, iclass 26, count 0 2006.285.11:04:58.80#ibcon#about to read 3, iclass 26, count 0 2006.285.11:04:58.84#ibcon#read 3, iclass 26, count 0 2006.285.11:04:58.84#ibcon#about to read 4, iclass 26, count 0 2006.285.11:04:58.84#ibcon#read 4, iclass 26, count 0 2006.285.11:04:58.84#ibcon#about to read 5, iclass 26, count 0 2006.285.11:04:58.84#ibcon#read 5, iclass 26, count 0 2006.285.11:04:58.84#ibcon#about to read 6, iclass 26, count 0 2006.285.11:04:58.84#ibcon#read 6, iclass 26, count 0 2006.285.11:04:58.84#ibcon#end of sib2, iclass 26, count 0 2006.285.11:04:58.84#ibcon#*after write, iclass 26, count 0 2006.285.11:04:58.84#ibcon#*before return 0, iclass 26, count 0 2006.285.11:04:58.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:04:58.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:04:58.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:04:58.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:04:58.84$vck44/vb=3,4 2006.285.11:04:58.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.11:04:58.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.11:04:58.84#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:58.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:04:58.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:04:58.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:04:58.90#ibcon#enter wrdev, iclass 28, count 2 2006.285.11:04:58.90#ibcon#first serial, iclass 28, count 2 2006.285.11:04:58.90#ibcon#enter sib2, iclass 28, count 2 2006.285.11:04:58.90#ibcon#flushed, iclass 28, count 2 2006.285.11:04:58.90#ibcon#about to write, iclass 28, count 2 2006.285.11:04:58.90#ibcon#wrote, iclass 28, count 2 2006.285.11:04:58.90#ibcon#about to read 3, iclass 28, count 2 2006.285.11:04:58.92#ibcon#read 3, iclass 28, count 2 2006.285.11:04:58.92#ibcon#about to read 4, iclass 28, count 2 2006.285.11:04:58.92#ibcon#read 4, iclass 28, count 2 2006.285.11:04:58.92#ibcon#about to read 5, iclass 28, count 2 2006.285.11:04:58.92#ibcon#read 5, iclass 28, count 2 2006.285.11:04:58.92#ibcon#about to read 6, iclass 28, count 2 2006.285.11:04:58.92#ibcon#read 6, iclass 28, count 2 2006.285.11:04:58.92#ibcon#end of sib2, iclass 28, count 2 2006.285.11:04:58.92#ibcon#*mode == 0, iclass 28, count 2 2006.285.11:04:58.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.11:04:58.92#ibcon#[27=AT03-04\r\n] 2006.285.11:04:58.92#ibcon#*before write, iclass 28, count 2 2006.285.11:04:58.92#ibcon#enter sib2, iclass 28, count 2 2006.285.11:04:58.92#ibcon#flushed, iclass 28, count 2 2006.285.11:04:58.92#ibcon#about to write, iclass 28, count 2 2006.285.11:04:58.92#ibcon#wrote, iclass 28, count 2 2006.285.11:04:58.92#ibcon#about to read 3, iclass 28, count 2 2006.285.11:04:58.95#ibcon#read 3, iclass 28, count 2 2006.285.11:04:58.95#ibcon#about to read 4, iclass 28, count 2 2006.285.11:04:58.95#ibcon#read 4, iclass 28, count 2 2006.285.11:04:58.95#ibcon#about to read 5, iclass 28, count 2 2006.285.11:04:58.95#ibcon#read 5, iclass 28, count 2 2006.285.11:04:58.95#ibcon#about to read 6, iclass 28, count 2 2006.285.11:04:58.95#ibcon#read 6, iclass 28, count 2 2006.285.11:04:58.95#ibcon#end of sib2, iclass 28, count 2 2006.285.11:04:58.95#ibcon#*after write, iclass 28, count 2 2006.285.11:04:58.95#ibcon#*before return 0, iclass 28, count 2 2006.285.11:04:58.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:04:58.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:04:58.95#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.11:04:58.95#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:58.95#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:04:59.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:04:59.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:04:59.07#ibcon#enter wrdev, iclass 28, count 0 2006.285.11:04:59.07#ibcon#first serial, iclass 28, count 0 2006.285.11:04:59.07#ibcon#enter sib2, iclass 28, count 0 2006.285.11:04:59.07#ibcon#flushed, iclass 28, count 0 2006.285.11:04:59.07#ibcon#about to write, iclass 28, count 0 2006.285.11:04:59.07#ibcon#wrote, iclass 28, count 0 2006.285.11:04:59.07#ibcon#about to read 3, iclass 28, count 0 2006.285.11:04:59.09#ibcon#read 3, iclass 28, count 0 2006.285.11:04:59.09#ibcon#about to read 4, iclass 28, count 0 2006.285.11:04:59.09#ibcon#read 4, iclass 28, count 0 2006.285.11:04:59.09#ibcon#about to read 5, iclass 28, count 0 2006.285.11:04:59.09#ibcon#read 5, iclass 28, count 0 2006.285.11:04:59.09#ibcon#about to read 6, iclass 28, count 0 2006.285.11:04:59.09#ibcon#read 6, iclass 28, count 0 2006.285.11:04:59.09#ibcon#end of sib2, iclass 28, count 0 2006.285.11:04:59.09#ibcon#*mode == 0, iclass 28, count 0 2006.285.11:04:59.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.11:04:59.09#ibcon#[27=USB\r\n] 2006.285.11:04:59.09#ibcon#*before write, iclass 28, count 0 2006.285.11:04:59.09#ibcon#enter sib2, iclass 28, count 0 2006.285.11:04:59.09#ibcon#flushed, iclass 28, count 0 2006.285.11:04:59.09#ibcon#about to write, iclass 28, count 0 2006.285.11:04:59.09#ibcon#wrote, iclass 28, count 0 2006.285.11:04:59.09#ibcon#about to read 3, iclass 28, count 0 2006.285.11:04:59.12#ibcon#read 3, iclass 28, count 0 2006.285.11:04:59.12#ibcon#about to read 4, iclass 28, count 0 2006.285.11:04:59.12#ibcon#read 4, iclass 28, count 0 2006.285.11:04:59.12#ibcon#about to read 5, iclass 28, count 0 2006.285.11:04:59.12#ibcon#read 5, iclass 28, count 0 2006.285.11:04:59.12#ibcon#about to read 6, iclass 28, count 0 2006.285.11:04:59.12#ibcon#read 6, iclass 28, count 0 2006.285.11:04:59.12#ibcon#end of sib2, iclass 28, count 0 2006.285.11:04:59.12#ibcon#*after write, iclass 28, count 0 2006.285.11:04:59.12#ibcon#*before return 0, iclass 28, count 0 2006.285.11:04:59.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:04:59.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:04:59.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.11:04:59.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.11:04:59.12$vck44/vblo=4,679.99 2006.285.11:04:59.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.11:04:59.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.11:04:59.12#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:59.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:04:59.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:04:59.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:04:59.12#ibcon#enter wrdev, iclass 30, count 0 2006.285.11:04:59.12#ibcon#first serial, iclass 30, count 0 2006.285.11:04:59.12#ibcon#enter sib2, iclass 30, count 0 2006.285.11:04:59.12#ibcon#flushed, iclass 30, count 0 2006.285.11:04:59.12#ibcon#about to write, iclass 30, count 0 2006.285.11:04:59.12#ibcon#wrote, iclass 30, count 0 2006.285.11:04:59.12#ibcon#about to read 3, iclass 30, count 0 2006.285.11:04:59.14#ibcon#read 3, iclass 30, count 0 2006.285.11:04:59.14#ibcon#about to read 4, iclass 30, count 0 2006.285.11:04:59.14#ibcon#read 4, iclass 30, count 0 2006.285.11:04:59.14#ibcon#about to read 5, iclass 30, count 0 2006.285.11:04:59.14#ibcon#read 5, iclass 30, count 0 2006.285.11:04:59.14#ibcon#about to read 6, iclass 30, count 0 2006.285.11:04:59.14#ibcon#read 6, iclass 30, count 0 2006.285.11:04:59.14#ibcon#end of sib2, iclass 30, count 0 2006.285.11:04:59.14#ibcon#*mode == 0, iclass 30, count 0 2006.285.11:04:59.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.11:04:59.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:04:59.14#ibcon#*before write, iclass 30, count 0 2006.285.11:04:59.14#ibcon#enter sib2, iclass 30, count 0 2006.285.11:04:59.14#ibcon#flushed, iclass 30, count 0 2006.285.11:04:59.14#ibcon#about to write, iclass 30, count 0 2006.285.11:04:59.14#ibcon#wrote, iclass 30, count 0 2006.285.11:04:59.14#ibcon#about to read 3, iclass 30, count 0 2006.285.11:04:59.18#ibcon#read 3, iclass 30, count 0 2006.285.11:04:59.18#ibcon#about to read 4, iclass 30, count 0 2006.285.11:04:59.18#ibcon#read 4, iclass 30, count 0 2006.285.11:04:59.18#ibcon#about to read 5, iclass 30, count 0 2006.285.11:04:59.18#ibcon#read 5, iclass 30, count 0 2006.285.11:04:59.18#ibcon#about to read 6, iclass 30, count 0 2006.285.11:04:59.18#ibcon#read 6, iclass 30, count 0 2006.285.11:04:59.18#ibcon#end of sib2, iclass 30, count 0 2006.285.11:04:59.18#ibcon#*after write, iclass 30, count 0 2006.285.11:04:59.18#ibcon#*before return 0, iclass 30, count 0 2006.285.11:04:59.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:04:59.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:04:59.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.11:04:59.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.11:04:59.18$vck44/vb=4,5 2006.285.11:04:59.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.11:04:59.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.11:04:59.18#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:59.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:04:59.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:04:59.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:04:59.24#ibcon#enter wrdev, iclass 32, count 2 2006.285.11:04:59.24#ibcon#first serial, iclass 32, count 2 2006.285.11:04:59.24#ibcon#enter sib2, iclass 32, count 2 2006.285.11:04:59.24#ibcon#flushed, iclass 32, count 2 2006.285.11:04:59.24#ibcon#about to write, iclass 32, count 2 2006.285.11:04:59.24#ibcon#wrote, iclass 32, count 2 2006.285.11:04:59.24#ibcon#about to read 3, iclass 32, count 2 2006.285.11:04:59.26#ibcon#read 3, iclass 32, count 2 2006.285.11:04:59.26#ibcon#about to read 4, iclass 32, count 2 2006.285.11:04:59.26#ibcon#read 4, iclass 32, count 2 2006.285.11:04:59.26#ibcon#about to read 5, iclass 32, count 2 2006.285.11:04:59.26#ibcon#read 5, iclass 32, count 2 2006.285.11:04:59.26#ibcon#about to read 6, iclass 32, count 2 2006.285.11:04:59.26#ibcon#read 6, iclass 32, count 2 2006.285.11:04:59.26#ibcon#end of sib2, iclass 32, count 2 2006.285.11:04:59.26#ibcon#*mode == 0, iclass 32, count 2 2006.285.11:04:59.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.11:04:59.26#ibcon#[27=AT04-05\r\n] 2006.285.11:04:59.26#ibcon#*before write, iclass 32, count 2 2006.285.11:04:59.26#ibcon#enter sib2, iclass 32, count 2 2006.285.11:04:59.26#ibcon#flushed, iclass 32, count 2 2006.285.11:04:59.26#ibcon#about to write, iclass 32, count 2 2006.285.11:04:59.26#ibcon#wrote, iclass 32, count 2 2006.285.11:04:59.26#ibcon#about to read 3, iclass 32, count 2 2006.285.11:04:59.29#ibcon#read 3, iclass 32, count 2 2006.285.11:04:59.29#ibcon#about to read 4, iclass 32, count 2 2006.285.11:04:59.29#ibcon#read 4, iclass 32, count 2 2006.285.11:04:59.29#ibcon#about to read 5, iclass 32, count 2 2006.285.11:04:59.29#ibcon#read 5, iclass 32, count 2 2006.285.11:04:59.29#ibcon#about to read 6, iclass 32, count 2 2006.285.11:04:59.29#ibcon#read 6, iclass 32, count 2 2006.285.11:04:59.29#ibcon#end of sib2, iclass 32, count 2 2006.285.11:04:59.29#ibcon#*after write, iclass 32, count 2 2006.285.11:04:59.29#ibcon#*before return 0, iclass 32, count 2 2006.285.11:04:59.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:04:59.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:04:59.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.11:04:59.29#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:59.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:04:59.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:04:59.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:04:59.41#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:04:59.41#ibcon#first serial, iclass 32, count 0 2006.285.11:04:59.41#ibcon#enter sib2, iclass 32, count 0 2006.285.11:04:59.41#ibcon#flushed, iclass 32, count 0 2006.285.11:04:59.41#ibcon#about to write, iclass 32, count 0 2006.285.11:04:59.41#ibcon#wrote, iclass 32, count 0 2006.285.11:04:59.41#ibcon#about to read 3, iclass 32, count 0 2006.285.11:04:59.43#ibcon#read 3, iclass 32, count 0 2006.285.11:04:59.43#ibcon#about to read 4, iclass 32, count 0 2006.285.11:04:59.43#ibcon#read 4, iclass 32, count 0 2006.285.11:04:59.43#ibcon#about to read 5, iclass 32, count 0 2006.285.11:04:59.43#ibcon#read 5, iclass 32, count 0 2006.285.11:04:59.43#ibcon#about to read 6, iclass 32, count 0 2006.285.11:04:59.43#ibcon#read 6, iclass 32, count 0 2006.285.11:04:59.43#ibcon#end of sib2, iclass 32, count 0 2006.285.11:04:59.43#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:04:59.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:04:59.43#ibcon#[27=USB\r\n] 2006.285.11:04:59.43#ibcon#*before write, iclass 32, count 0 2006.285.11:04:59.43#ibcon#enter sib2, iclass 32, count 0 2006.285.11:04:59.43#ibcon#flushed, iclass 32, count 0 2006.285.11:04:59.43#ibcon#about to write, iclass 32, count 0 2006.285.11:04:59.43#ibcon#wrote, iclass 32, count 0 2006.285.11:04:59.43#ibcon#about to read 3, iclass 32, count 0 2006.285.11:04:59.46#ibcon#read 3, iclass 32, count 0 2006.285.11:04:59.46#ibcon#about to read 4, iclass 32, count 0 2006.285.11:04:59.46#ibcon#read 4, iclass 32, count 0 2006.285.11:04:59.46#ibcon#about to read 5, iclass 32, count 0 2006.285.11:04:59.46#ibcon#read 5, iclass 32, count 0 2006.285.11:04:59.46#ibcon#about to read 6, iclass 32, count 0 2006.285.11:04:59.46#ibcon#read 6, iclass 32, count 0 2006.285.11:04:59.46#ibcon#end of sib2, iclass 32, count 0 2006.285.11:04:59.46#ibcon#*after write, iclass 32, count 0 2006.285.11:04:59.46#ibcon#*before return 0, iclass 32, count 0 2006.285.11:04:59.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:04:59.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:04:59.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:04:59.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:04:59.46$vck44/vblo=5,709.99 2006.285.11:04:59.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.11:04:59.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.11:04:59.46#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:59.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:04:59.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:04:59.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:04:59.46#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:04:59.46#ibcon#first serial, iclass 34, count 0 2006.285.11:04:59.46#ibcon#enter sib2, iclass 34, count 0 2006.285.11:04:59.46#ibcon#flushed, iclass 34, count 0 2006.285.11:04:59.46#ibcon#about to write, iclass 34, count 0 2006.285.11:04:59.46#ibcon#wrote, iclass 34, count 0 2006.285.11:04:59.46#ibcon#about to read 3, iclass 34, count 0 2006.285.11:04:59.48#ibcon#read 3, iclass 34, count 0 2006.285.11:04:59.48#ibcon#about to read 4, iclass 34, count 0 2006.285.11:04:59.48#ibcon#read 4, iclass 34, count 0 2006.285.11:04:59.48#ibcon#about to read 5, iclass 34, count 0 2006.285.11:04:59.48#ibcon#read 5, iclass 34, count 0 2006.285.11:04:59.48#ibcon#about to read 6, iclass 34, count 0 2006.285.11:04:59.48#ibcon#read 6, iclass 34, count 0 2006.285.11:04:59.48#ibcon#end of sib2, iclass 34, count 0 2006.285.11:04:59.48#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:04:59.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:04:59.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:04:59.48#ibcon#*before write, iclass 34, count 0 2006.285.11:04:59.48#ibcon#enter sib2, iclass 34, count 0 2006.285.11:04:59.48#ibcon#flushed, iclass 34, count 0 2006.285.11:04:59.48#ibcon#about to write, iclass 34, count 0 2006.285.11:04:59.48#ibcon#wrote, iclass 34, count 0 2006.285.11:04:59.48#ibcon#about to read 3, iclass 34, count 0 2006.285.11:04:59.52#ibcon#read 3, iclass 34, count 0 2006.285.11:04:59.52#ibcon#about to read 4, iclass 34, count 0 2006.285.11:04:59.52#ibcon#read 4, iclass 34, count 0 2006.285.11:04:59.52#ibcon#about to read 5, iclass 34, count 0 2006.285.11:04:59.52#ibcon#read 5, iclass 34, count 0 2006.285.11:04:59.52#ibcon#about to read 6, iclass 34, count 0 2006.285.11:04:59.52#ibcon#read 6, iclass 34, count 0 2006.285.11:04:59.52#ibcon#end of sib2, iclass 34, count 0 2006.285.11:04:59.52#ibcon#*after write, iclass 34, count 0 2006.285.11:04:59.52#ibcon#*before return 0, iclass 34, count 0 2006.285.11:04:59.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:04:59.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:04:59.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:04:59.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:04:59.52$vck44/vb=5,4 2006.285.11:04:59.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.11:04:59.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.11:04:59.52#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:59.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:04:59.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:04:59.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:04:59.58#ibcon#enter wrdev, iclass 36, count 2 2006.285.11:04:59.58#ibcon#first serial, iclass 36, count 2 2006.285.11:04:59.58#ibcon#enter sib2, iclass 36, count 2 2006.285.11:04:59.58#ibcon#flushed, iclass 36, count 2 2006.285.11:04:59.58#ibcon#about to write, iclass 36, count 2 2006.285.11:04:59.58#ibcon#wrote, iclass 36, count 2 2006.285.11:04:59.58#ibcon#about to read 3, iclass 36, count 2 2006.285.11:04:59.60#ibcon#read 3, iclass 36, count 2 2006.285.11:04:59.60#ibcon#about to read 4, iclass 36, count 2 2006.285.11:04:59.60#ibcon#read 4, iclass 36, count 2 2006.285.11:04:59.60#ibcon#about to read 5, iclass 36, count 2 2006.285.11:04:59.60#ibcon#read 5, iclass 36, count 2 2006.285.11:04:59.60#ibcon#about to read 6, iclass 36, count 2 2006.285.11:04:59.60#ibcon#read 6, iclass 36, count 2 2006.285.11:04:59.60#ibcon#end of sib2, iclass 36, count 2 2006.285.11:04:59.60#ibcon#*mode == 0, iclass 36, count 2 2006.285.11:04:59.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.11:04:59.60#ibcon#[27=AT05-04\r\n] 2006.285.11:04:59.60#ibcon#*before write, iclass 36, count 2 2006.285.11:04:59.60#ibcon#enter sib2, iclass 36, count 2 2006.285.11:04:59.60#ibcon#flushed, iclass 36, count 2 2006.285.11:04:59.60#ibcon#about to write, iclass 36, count 2 2006.285.11:04:59.60#ibcon#wrote, iclass 36, count 2 2006.285.11:04:59.60#ibcon#about to read 3, iclass 36, count 2 2006.285.11:04:59.63#ibcon#read 3, iclass 36, count 2 2006.285.11:04:59.63#ibcon#about to read 4, iclass 36, count 2 2006.285.11:04:59.63#ibcon#read 4, iclass 36, count 2 2006.285.11:04:59.63#ibcon#about to read 5, iclass 36, count 2 2006.285.11:04:59.63#ibcon#read 5, iclass 36, count 2 2006.285.11:04:59.63#ibcon#about to read 6, iclass 36, count 2 2006.285.11:04:59.63#ibcon#read 6, iclass 36, count 2 2006.285.11:04:59.63#ibcon#end of sib2, iclass 36, count 2 2006.285.11:04:59.63#ibcon#*after write, iclass 36, count 2 2006.285.11:04:59.63#ibcon#*before return 0, iclass 36, count 2 2006.285.11:04:59.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:04:59.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:04:59.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.11:04:59.63#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:59.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:04:59.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:04:59.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:04:59.75#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:04:59.75#ibcon#first serial, iclass 36, count 0 2006.285.11:04:59.75#ibcon#enter sib2, iclass 36, count 0 2006.285.11:04:59.75#ibcon#flushed, iclass 36, count 0 2006.285.11:04:59.75#ibcon#about to write, iclass 36, count 0 2006.285.11:04:59.75#ibcon#wrote, iclass 36, count 0 2006.285.11:04:59.75#ibcon#about to read 3, iclass 36, count 0 2006.285.11:04:59.77#ibcon#read 3, iclass 36, count 0 2006.285.11:04:59.77#ibcon#about to read 4, iclass 36, count 0 2006.285.11:04:59.77#ibcon#read 4, iclass 36, count 0 2006.285.11:04:59.77#ibcon#about to read 5, iclass 36, count 0 2006.285.11:04:59.77#ibcon#read 5, iclass 36, count 0 2006.285.11:04:59.77#ibcon#about to read 6, iclass 36, count 0 2006.285.11:04:59.77#ibcon#read 6, iclass 36, count 0 2006.285.11:04:59.77#ibcon#end of sib2, iclass 36, count 0 2006.285.11:04:59.77#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:04:59.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:04:59.77#ibcon#[27=USB\r\n] 2006.285.11:04:59.77#ibcon#*before write, iclass 36, count 0 2006.285.11:04:59.77#ibcon#enter sib2, iclass 36, count 0 2006.285.11:04:59.77#ibcon#flushed, iclass 36, count 0 2006.285.11:04:59.77#ibcon#about to write, iclass 36, count 0 2006.285.11:04:59.77#ibcon#wrote, iclass 36, count 0 2006.285.11:04:59.77#ibcon#about to read 3, iclass 36, count 0 2006.285.11:04:59.80#ibcon#read 3, iclass 36, count 0 2006.285.11:04:59.80#ibcon#about to read 4, iclass 36, count 0 2006.285.11:04:59.80#ibcon#read 4, iclass 36, count 0 2006.285.11:04:59.80#ibcon#about to read 5, iclass 36, count 0 2006.285.11:04:59.80#ibcon#read 5, iclass 36, count 0 2006.285.11:04:59.80#ibcon#about to read 6, iclass 36, count 0 2006.285.11:04:59.80#ibcon#read 6, iclass 36, count 0 2006.285.11:04:59.80#ibcon#end of sib2, iclass 36, count 0 2006.285.11:04:59.80#ibcon#*after write, iclass 36, count 0 2006.285.11:04:59.80#ibcon#*before return 0, iclass 36, count 0 2006.285.11:04:59.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:04:59.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:04:59.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:04:59.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:04:59.80$vck44/vblo=6,719.99 2006.285.11:04:59.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.11:04:59.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.11:04:59.80#ibcon#ireg 17 cls_cnt 0 2006.285.11:04:59.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:04:59.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:04:59.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:04:59.80#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:04:59.80#ibcon#first serial, iclass 38, count 0 2006.285.11:04:59.80#ibcon#enter sib2, iclass 38, count 0 2006.285.11:04:59.80#ibcon#flushed, iclass 38, count 0 2006.285.11:04:59.80#ibcon#about to write, iclass 38, count 0 2006.285.11:04:59.80#ibcon#wrote, iclass 38, count 0 2006.285.11:04:59.80#ibcon#about to read 3, iclass 38, count 0 2006.285.11:04:59.82#ibcon#read 3, iclass 38, count 0 2006.285.11:04:59.82#ibcon#about to read 4, iclass 38, count 0 2006.285.11:04:59.82#ibcon#read 4, iclass 38, count 0 2006.285.11:04:59.82#ibcon#about to read 5, iclass 38, count 0 2006.285.11:04:59.82#ibcon#read 5, iclass 38, count 0 2006.285.11:04:59.82#ibcon#about to read 6, iclass 38, count 0 2006.285.11:04:59.82#ibcon#read 6, iclass 38, count 0 2006.285.11:04:59.82#ibcon#end of sib2, iclass 38, count 0 2006.285.11:04:59.82#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:04:59.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:04:59.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:04:59.82#ibcon#*before write, iclass 38, count 0 2006.285.11:04:59.82#ibcon#enter sib2, iclass 38, count 0 2006.285.11:04:59.82#ibcon#flushed, iclass 38, count 0 2006.285.11:04:59.82#ibcon#about to write, iclass 38, count 0 2006.285.11:04:59.82#ibcon#wrote, iclass 38, count 0 2006.285.11:04:59.82#ibcon#about to read 3, iclass 38, count 0 2006.285.11:04:59.86#ibcon#read 3, iclass 38, count 0 2006.285.11:04:59.86#ibcon#about to read 4, iclass 38, count 0 2006.285.11:04:59.86#ibcon#read 4, iclass 38, count 0 2006.285.11:04:59.86#ibcon#about to read 5, iclass 38, count 0 2006.285.11:04:59.86#ibcon#read 5, iclass 38, count 0 2006.285.11:04:59.86#ibcon#about to read 6, iclass 38, count 0 2006.285.11:04:59.86#ibcon#read 6, iclass 38, count 0 2006.285.11:04:59.86#ibcon#end of sib2, iclass 38, count 0 2006.285.11:04:59.86#ibcon#*after write, iclass 38, count 0 2006.285.11:04:59.86#ibcon#*before return 0, iclass 38, count 0 2006.285.11:04:59.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:04:59.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:04:59.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:04:59.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:04:59.86$vck44/vb=6,3 2006.285.11:04:59.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.11:04:59.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.11:04:59.86#ibcon#ireg 11 cls_cnt 2 2006.285.11:04:59.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:04:59.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:04:59.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:04:59.92#ibcon#enter wrdev, iclass 40, count 2 2006.285.11:04:59.92#ibcon#first serial, iclass 40, count 2 2006.285.11:04:59.92#ibcon#enter sib2, iclass 40, count 2 2006.285.11:04:59.92#ibcon#flushed, iclass 40, count 2 2006.285.11:04:59.92#ibcon#about to write, iclass 40, count 2 2006.285.11:04:59.92#ibcon#wrote, iclass 40, count 2 2006.285.11:04:59.92#ibcon#about to read 3, iclass 40, count 2 2006.285.11:04:59.94#ibcon#read 3, iclass 40, count 2 2006.285.11:04:59.94#ibcon#about to read 4, iclass 40, count 2 2006.285.11:04:59.94#ibcon#read 4, iclass 40, count 2 2006.285.11:04:59.94#ibcon#about to read 5, iclass 40, count 2 2006.285.11:04:59.94#ibcon#read 5, iclass 40, count 2 2006.285.11:04:59.94#ibcon#about to read 6, iclass 40, count 2 2006.285.11:04:59.94#ibcon#read 6, iclass 40, count 2 2006.285.11:04:59.94#ibcon#end of sib2, iclass 40, count 2 2006.285.11:04:59.94#ibcon#*mode == 0, iclass 40, count 2 2006.285.11:04:59.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.11:04:59.94#ibcon#[27=AT06-03\r\n] 2006.285.11:04:59.94#ibcon#*before write, iclass 40, count 2 2006.285.11:04:59.94#ibcon#enter sib2, iclass 40, count 2 2006.285.11:04:59.94#ibcon#flushed, iclass 40, count 2 2006.285.11:04:59.94#ibcon#about to write, iclass 40, count 2 2006.285.11:04:59.94#ibcon#wrote, iclass 40, count 2 2006.285.11:04:59.94#ibcon#about to read 3, iclass 40, count 2 2006.285.11:04:59.97#ibcon#read 3, iclass 40, count 2 2006.285.11:04:59.97#ibcon#about to read 4, iclass 40, count 2 2006.285.11:04:59.97#ibcon#read 4, iclass 40, count 2 2006.285.11:04:59.97#ibcon#about to read 5, iclass 40, count 2 2006.285.11:04:59.97#ibcon#read 5, iclass 40, count 2 2006.285.11:04:59.97#ibcon#about to read 6, iclass 40, count 2 2006.285.11:04:59.97#ibcon#read 6, iclass 40, count 2 2006.285.11:04:59.97#ibcon#end of sib2, iclass 40, count 2 2006.285.11:04:59.97#ibcon#*after write, iclass 40, count 2 2006.285.11:04:59.97#ibcon#*before return 0, iclass 40, count 2 2006.285.11:04:59.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:04:59.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:04:59.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.11:04:59.97#ibcon#ireg 7 cls_cnt 0 2006.285.11:04:59.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:05:00.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:05:00.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:05:00.09#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:05:00.09#ibcon#first serial, iclass 40, count 0 2006.285.11:05:00.09#ibcon#enter sib2, iclass 40, count 0 2006.285.11:05:00.09#ibcon#flushed, iclass 40, count 0 2006.285.11:05:00.09#ibcon#about to write, iclass 40, count 0 2006.285.11:05:00.09#ibcon#wrote, iclass 40, count 0 2006.285.11:05:00.09#ibcon#about to read 3, iclass 40, count 0 2006.285.11:05:00.11#ibcon#read 3, iclass 40, count 0 2006.285.11:05:00.11#ibcon#about to read 4, iclass 40, count 0 2006.285.11:05:00.11#ibcon#read 4, iclass 40, count 0 2006.285.11:05:00.11#ibcon#about to read 5, iclass 40, count 0 2006.285.11:05:00.11#ibcon#read 5, iclass 40, count 0 2006.285.11:05:00.11#ibcon#about to read 6, iclass 40, count 0 2006.285.11:05:00.11#ibcon#read 6, iclass 40, count 0 2006.285.11:05:00.11#ibcon#end of sib2, iclass 40, count 0 2006.285.11:05:00.11#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:05:00.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:05:00.11#ibcon#[27=USB\r\n] 2006.285.11:05:00.11#ibcon#*before write, iclass 40, count 0 2006.285.11:05:00.11#ibcon#enter sib2, iclass 40, count 0 2006.285.11:05:00.11#ibcon#flushed, iclass 40, count 0 2006.285.11:05:00.11#ibcon#about to write, iclass 40, count 0 2006.285.11:05:00.11#ibcon#wrote, iclass 40, count 0 2006.285.11:05:00.11#ibcon#about to read 3, iclass 40, count 0 2006.285.11:05:00.14#ibcon#read 3, iclass 40, count 0 2006.285.11:05:00.14#ibcon#about to read 4, iclass 40, count 0 2006.285.11:05:00.14#ibcon#read 4, iclass 40, count 0 2006.285.11:05:00.14#ibcon#about to read 5, iclass 40, count 0 2006.285.11:05:00.14#ibcon#read 5, iclass 40, count 0 2006.285.11:05:00.14#ibcon#about to read 6, iclass 40, count 0 2006.285.11:05:00.14#ibcon#read 6, iclass 40, count 0 2006.285.11:05:00.14#ibcon#end of sib2, iclass 40, count 0 2006.285.11:05:00.14#ibcon#*after write, iclass 40, count 0 2006.285.11:05:00.14#ibcon#*before return 0, iclass 40, count 0 2006.285.11:05:00.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:05:00.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:05:00.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:05:00.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:05:00.14$vck44/vblo=7,734.99 2006.285.11:05:00.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.11:05:00.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.11:05:00.14#ibcon#ireg 17 cls_cnt 0 2006.285.11:05:00.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:05:00.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:05:00.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:05:00.14#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:05:00.14#ibcon#first serial, iclass 4, count 0 2006.285.11:05:00.14#ibcon#enter sib2, iclass 4, count 0 2006.285.11:05:00.14#ibcon#flushed, iclass 4, count 0 2006.285.11:05:00.14#ibcon#about to write, iclass 4, count 0 2006.285.11:05:00.14#ibcon#wrote, iclass 4, count 0 2006.285.11:05:00.14#ibcon#about to read 3, iclass 4, count 0 2006.285.11:05:00.16#ibcon#read 3, iclass 4, count 0 2006.285.11:05:00.16#ibcon#about to read 4, iclass 4, count 0 2006.285.11:05:00.16#ibcon#read 4, iclass 4, count 0 2006.285.11:05:00.16#ibcon#about to read 5, iclass 4, count 0 2006.285.11:05:00.16#ibcon#read 5, iclass 4, count 0 2006.285.11:05:00.16#ibcon#about to read 6, iclass 4, count 0 2006.285.11:05:00.16#ibcon#read 6, iclass 4, count 0 2006.285.11:05:00.16#ibcon#end of sib2, iclass 4, count 0 2006.285.11:05:00.16#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:05:00.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:05:00.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:05:00.16#ibcon#*before write, iclass 4, count 0 2006.285.11:05:00.16#ibcon#enter sib2, iclass 4, count 0 2006.285.11:05:00.16#ibcon#flushed, iclass 4, count 0 2006.285.11:05:00.16#ibcon#about to write, iclass 4, count 0 2006.285.11:05:00.16#ibcon#wrote, iclass 4, count 0 2006.285.11:05:00.16#ibcon#about to read 3, iclass 4, count 0 2006.285.11:05:00.20#ibcon#read 3, iclass 4, count 0 2006.285.11:05:00.20#ibcon#about to read 4, iclass 4, count 0 2006.285.11:05:00.20#ibcon#read 4, iclass 4, count 0 2006.285.11:05:00.20#ibcon#about to read 5, iclass 4, count 0 2006.285.11:05:00.20#ibcon#read 5, iclass 4, count 0 2006.285.11:05:00.20#ibcon#about to read 6, iclass 4, count 0 2006.285.11:05:00.20#ibcon#read 6, iclass 4, count 0 2006.285.11:05:00.20#ibcon#end of sib2, iclass 4, count 0 2006.285.11:05:00.20#ibcon#*after write, iclass 4, count 0 2006.285.11:05:00.20#ibcon#*before return 0, iclass 4, count 0 2006.285.11:05:00.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:05:00.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:05:00.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:05:00.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:05:00.20$vck44/vb=7,4 2006.285.11:05:00.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.11:05:00.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.11:05:00.20#ibcon#ireg 11 cls_cnt 2 2006.285.11:05:00.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:05:00.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:05:00.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:05:00.26#ibcon#enter wrdev, iclass 6, count 2 2006.285.11:05:00.26#ibcon#first serial, iclass 6, count 2 2006.285.11:05:00.26#ibcon#enter sib2, iclass 6, count 2 2006.285.11:05:00.26#ibcon#flushed, iclass 6, count 2 2006.285.11:05:00.26#ibcon#about to write, iclass 6, count 2 2006.285.11:05:00.26#ibcon#wrote, iclass 6, count 2 2006.285.11:05:00.26#ibcon#about to read 3, iclass 6, count 2 2006.285.11:05:00.28#ibcon#read 3, iclass 6, count 2 2006.285.11:05:00.28#ibcon#about to read 4, iclass 6, count 2 2006.285.11:05:00.28#ibcon#read 4, iclass 6, count 2 2006.285.11:05:00.28#ibcon#about to read 5, iclass 6, count 2 2006.285.11:05:00.28#ibcon#read 5, iclass 6, count 2 2006.285.11:05:00.28#ibcon#about to read 6, iclass 6, count 2 2006.285.11:05:00.28#ibcon#read 6, iclass 6, count 2 2006.285.11:05:00.28#ibcon#end of sib2, iclass 6, count 2 2006.285.11:05:00.28#ibcon#*mode == 0, iclass 6, count 2 2006.285.11:05:00.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.11:05:00.28#ibcon#[27=AT07-04\r\n] 2006.285.11:05:00.28#ibcon#*before write, iclass 6, count 2 2006.285.11:05:00.28#ibcon#enter sib2, iclass 6, count 2 2006.285.11:05:00.28#ibcon#flushed, iclass 6, count 2 2006.285.11:05:00.28#ibcon#about to write, iclass 6, count 2 2006.285.11:05:00.28#ibcon#wrote, iclass 6, count 2 2006.285.11:05:00.28#ibcon#about to read 3, iclass 6, count 2 2006.285.11:05:00.31#ibcon#read 3, iclass 6, count 2 2006.285.11:05:00.31#ibcon#about to read 4, iclass 6, count 2 2006.285.11:05:00.31#ibcon#read 4, iclass 6, count 2 2006.285.11:05:00.31#ibcon#about to read 5, iclass 6, count 2 2006.285.11:05:00.31#ibcon#read 5, iclass 6, count 2 2006.285.11:05:00.31#ibcon#about to read 6, iclass 6, count 2 2006.285.11:05:00.31#ibcon#read 6, iclass 6, count 2 2006.285.11:05:00.31#ibcon#end of sib2, iclass 6, count 2 2006.285.11:05:00.31#ibcon#*after write, iclass 6, count 2 2006.285.11:05:00.31#ibcon#*before return 0, iclass 6, count 2 2006.285.11:05:00.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:05:00.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:05:00.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.11:05:00.31#ibcon#ireg 7 cls_cnt 0 2006.285.11:05:00.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:05:00.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:05:00.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:05:00.43#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:05:00.43#ibcon#first serial, iclass 6, count 0 2006.285.11:05:00.43#ibcon#enter sib2, iclass 6, count 0 2006.285.11:05:00.43#ibcon#flushed, iclass 6, count 0 2006.285.11:05:00.43#ibcon#about to write, iclass 6, count 0 2006.285.11:05:00.43#ibcon#wrote, iclass 6, count 0 2006.285.11:05:00.43#ibcon#about to read 3, iclass 6, count 0 2006.285.11:05:00.45#ibcon#read 3, iclass 6, count 0 2006.285.11:05:00.45#ibcon#about to read 4, iclass 6, count 0 2006.285.11:05:00.45#ibcon#read 4, iclass 6, count 0 2006.285.11:05:00.45#ibcon#about to read 5, iclass 6, count 0 2006.285.11:05:00.45#ibcon#read 5, iclass 6, count 0 2006.285.11:05:00.45#ibcon#about to read 6, iclass 6, count 0 2006.285.11:05:00.45#ibcon#read 6, iclass 6, count 0 2006.285.11:05:00.45#ibcon#end of sib2, iclass 6, count 0 2006.285.11:05:00.45#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:05:00.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:05:00.45#ibcon#[27=USB\r\n] 2006.285.11:05:00.45#ibcon#*before write, iclass 6, count 0 2006.285.11:05:00.45#ibcon#enter sib2, iclass 6, count 0 2006.285.11:05:00.45#ibcon#flushed, iclass 6, count 0 2006.285.11:05:00.45#ibcon#about to write, iclass 6, count 0 2006.285.11:05:00.45#ibcon#wrote, iclass 6, count 0 2006.285.11:05:00.45#ibcon#about to read 3, iclass 6, count 0 2006.285.11:05:00.48#ibcon#read 3, iclass 6, count 0 2006.285.11:05:00.48#ibcon#about to read 4, iclass 6, count 0 2006.285.11:05:00.48#ibcon#read 4, iclass 6, count 0 2006.285.11:05:00.48#ibcon#about to read 5, iclass 6, count 0 2006.285.11:05:00.48#ibcon#read 5, iclass 6, count 0 2006.285.11:05:00.48#ibcon#about to read 6, iclass 6, count 0 2006.285.11:05:00.48#ibcon#read 6, iclass 6, count 0 2006.285.11:05:00.48#ibcon#end of sib2, iclass 6, count 0 2006.285.11:05:00.48#ibcon#*after write, iclass 6, count 0 2006.285.11:05:00.48#ibcon#*before return 0, iclass 6, count 0 2006.285.11:05:00.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:05:00.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:05:00.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:05:00.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:05:00.48$vck44/vblo=8,744.99 2006.285.11:05:00.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.11:05:00.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.11:05:00.48#ibcon#ireg 17 cls_cnt 0 2006.285.11:05:00.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:05:00.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:05:00.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:05:00.48#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:05:00.48#ibcon#first serial, iclass 10, count 0 2006.285.11:05:00.48#ibcon#enter sib2, iclass 10, count 0 2006.285.11:05:00.48#ibcon#flushed, iclass 10, count 0 2006.285.11:05:00.48#ibcon#about to write, iclass 10, count 0 2006.285.11:05:00.48#ibcon#wrote, iclass 10, count 0 2006.285.11:05:00.48#ibcon#about to read 3, iclass 10, count 0 2006.285.11:05:00.50#ibcon#read 3, iclass 10, count 0 2006.285.11:05:00.50#ibcon#about to read 4, iclass 10, count 0 2006.285.11:05:00.50#ibcon#read 4, iclass 10, count 0 2006.285.11:05:00.50#ibcon#about to read 5, iclass 10, count 0 2006.285.11:05:00.50#ibcon#read 5, iclass 10, count 0 2006.285.11:05:00.50#ibcon#about to read 6, iclass 10, count 0 2006.285.11:05:00.50#ibcon#read 6, iclass 10, count 0 2006.285.11:05:00.50#ibcon#end of sib2, iclass 10, count 0 2006.285.11:05:00.50#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:05:00.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:05:00.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:05:00.50#ibcon#*before write, iclass 10, count 0 2006.285.11:05:00.50#ibcon#enter sib2, iclass 10, count 0 2006.285.11:05:00.50#ibcon#flushed, iclass 10, count 0 2006.285.11:05:00.50#ibcon#about to write, iclass 10, count 0 2006.285.11:05:00.50#ibcon#wrote, iclass 10, count 0 2006.285.11:05:00.50#ibcon#about to read 3, iclass 10, count 0 2006.285.11:05:00.54#ibcon#read 3, iclass 10, count 0 2006.285.11:05:00.54#ibcon#about to read 4, iclass 10, count 0 2006.285.11:05:00.54#ibcon#read 4, iclass 10, count 0 2006.285.11:05:00.54#ibcon#about to read 5, iclass 10, count 0 2006.285.11:05:00.54#ibcon#read 5, iclass 10, count 0 2006.285.11:05:00.54#ibcon#about to read 6, iclass 10, count 0 2006.285.11:05:00.54#ibcon#read 6, iclass 10, count 0 2006.285.11:05:00.54#ibcon#end of sib2, iclass 10, count 0 2006.285.11:05:00.54#ibcon#*after write, iclass 10, count 0 2006.285.11:05:00.54#ibcon#*before return 0, iclass 10, count 0 2006.285.11:05:00.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:05:00.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:05:00.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:05:00.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:05:00.54$vck44/vb=8,4 2006.285.11:05:00.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.11:05:00.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.11:05:00.54#ibcon#ireg 11 cls_cnt 2 2006.285.11:05:00.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:05:00.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:05:00.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:05:00.60#ibcon#enter wrdev, iclass 12, count 2 2006.285.11:05:00.60#ibcon#first serial, iclass 12, count 2 2006.285.11:05:00.60#ibcon#enter sib2, iclass 12, count 2 2006.285.11:05:00.60#ibcon#flushed, iclass 12, count 2 2006.285.11:05:00.60#ibcon#about to write, iclass 12, count 2 2006.285.11:05:00.60#ibcon#wrote, iclass 12, count 2 2006.285.11:05:00.60#ibcon#about to read 3, iclass 12, count 2 2006.285.11:05:00.62#ibcon#read 3, iclass 12, count 2 2006.285.11:05:00.62#ibcon#about to read 4, iclass 12, count 2 2006.285.11:05:00.62#ibcon#read 4, iclass 12, count 2 2006.285.11:05:00.62#ibcon#about to read 5, iclass 12, count 2 2006.285.11:05:00.62#ibcon#read 5, iclass 12, count 2 2006.285.11:05:00.62#ibcon#about to read 6, iclass 12, count 2 2006.285.11:05:00.62#ibcon#read 6, iclass 12, count 2 2006.285.11:05:00.62#ibcon#end of sib2, iclass 12, count 2 2006.285.11:05:00.62#ibcon#*mode == 0, iclass 12, count 2 2006.285.11:05:00.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.11:05:00.62#ibcon#[27=AT08-04\r\n] 2006.285.11:05:00.62#ibcon#*before write, iclass 12, count 2 2006.285.11:05:00.62#ibcon#enter sib2, iclass 12, count 2 2006.285.11:05:00.62#ibcon#flushed, iclass 12, count 2 2006.285.11:05:00.62#ibcon#about to write, iclass 12, count 2 2006.285.11:05:00.62#ibcon#wrote, iclass 12, count 2 2006.285.11:05:00.62#ibcon#about to read 3, iclass 12, count 2 2006.285.11:05:00.65#ibcon#read 3, iclass 12, count 2 2006.285.11:05:00.65#ibcon#about to read 4, iclass 12, count 2 2006.285.11:05:00.65#ibcon#read 4, iclass 12, count 2 2006.285.11:05:00.65#ibcon#about to read 5, iclass 12, count 2 2006.285.11:05:00.65#ibcon#read 5, iclass 12, count 2 2006.285.11:05:00.65#ibcon#about to read 6, iclass 12, count 2 2006.285.11:05:00.65#ibcon#read 6, iclass 12, count 2 2006.285.11:05:00.65#ibcon#end of sib2, iclass 12, count 2 2006.285.11:05:00.65#ibcon#*after write, iclass 12, count 2 2006.285.11:05:00.65#ibcon#*before return 0, iclass 12, count 2 2006.285.11:05:00.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:05:00.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:05:00.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.11:05:00.65#ibcon#ireg 7 cls_cnt 0 2006.285.11:05:00.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:05:00.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:05:00.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:05:00.77#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:05:00.77#ibcon#first serial, iclass 12, count 0 2006.285.11:05:00.77#ibcon#enter sib2, iclass 12, count 0 2006.285.11:05:00.77#ibcon#flushed, iclass 12, count 0 2006.285.11:05:00.77#ibcon#about to write, iclass 12, count 0 2006.285.11:05:00.77#ibcon#wrote, iclass 12, count 0 2006.285.11:05:00.77#ibcon#about to read 3, iclass 12, count 0 2006.285.11:05:00.79#ibcon#read 3, iclass 12, count 0 2006.285.11:05:00.79#ibcon#about to read 4, iclass 12, count 0 2006.285.11:05:00.79#ibcon#read 4, iclass 12, count 0 2006.285.11:05:00.79#ibcon#about to read 5, iclass 12, count 0 2006.285.11:05:00.79#ibcon#read 5, iclass 12, count 0 2006.285.11:05:00.79#ibcon#about to read 6, iclass 12, count 0 2006.285.11:05:00.79#ibcon#read 6, iclass 12, count 0 2006.285.11:05:00.79#ibcon#end of sib2, iclass 12, count 0 2006.285.11:05:00.79#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:05:00.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:05:00.79#ibcon#[27=USB\r\n] 2006.285.11:05:00.79#ibcon#*before write, iclass 12, count 0 2006.285.11:05:00.79#ibcon#enter sib2, iclass 12, count 0 2006.285.11:05:00.79#ibcon#flushed, iclass 12, count 0 2006.285.11:05:00.79#ibcon#about to write, iclass 12, count 0 2006.285.11:05:00.79#ibcon#wrote, iclass 12, count 0 2006.285.11:05:00.79#ibcon#about to read 3, iclass 12, count 0 2006.285.11:05:00.82#ibcon#read 3, iclass 12, count 0 2006.285.11:05:00.82#ibcon#about to read 4, iclass 12, count 0 2006.285.11:05:00.82#ibcon#read 4, iclass 12, count 0 2006.285.11:05:00.82#ibcon#about to read 5, iclass 12, count 0 2006.285.11:05:00.82#ibcon#read 5, iclass 12, count 0 2006.285.11:05:00.82#ibcon#about to read 6, iclass 12, count 0 2006.285.11:05:00.82#ibcon#read 6, iclass 12, count 0 2006.285.11:05:00.82#ibcon#end of sib2, iclass 12, count 0 2006.285.11:05:00.82#ibcon#*after write, iclass 12, count 0 2006.285.11:05:00.82#ibcon#*before return 0, iclass 12, count 0 2006.285.11:05:00.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:05:00.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:05:00.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:05:00.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:05:00.82$vck44/vabw=wide 2006.285.11:05:00.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.11:05:00.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.11:05:00.82#ibcon#ireg 8 cls_cnt 0 2006.285.11:05:00.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:05:00.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:05:00.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:05:00.82#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:05:00.82#ibcon#first serial, iclass 14, count 0 2006.285.11:05:00.82#ibcon#enter sib2, iclass 14, count 0 2006.285.11:05:00.82#ibcon#flushed, iclass 14, count 0 2006.285.11:05:00.82#ibcon#about to write, iclass 14, count 0 2006.285.11:05:00.82#ibcon#wrote, iclass 14, count 0 2006.285.11:05:00.82#ibcon#about to read 3, iclass 14, count 0 2006.285.11:05:00.84#ibcon#read 3, iclass 14, count 0 2006.285.11:05:00.84#ibcon#about to read 4, iclass 14, count 0 2006.285.11:05:00.84#ibcon#read 4, iclass 14, count 0 2006.285.11:05:00.84#ibcon#about to read 5, iclass 14, count 0 2006.285.11:05:00.84#ibcon#read 5, iclass 14, count 0 2006.285.11:05:00.84#ibcon#about to read 6, iclass 14, count 0 2006.285.11:05:00.84#ibcon#read 6, iclass 14, count 0 2006.285.11:05:00.84#ibcon#end of sib2, iclass 14, count 0 2006.285.11:05:00.84#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:05:00.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:05:00.84#ibcon#[25=BW32\r\n] 2006.285.11:05:00.84#ibcon#*before write, iclass 14, count 0 2006.285.11:05:00.84#ibcon#enter sib2, iclass 14, count 0 2006.285.11:05:00.84#ibcon#flushed, iclass 14, count 0 2006.285.11:05:00.84#ibcon#about to write, iclass 14, count 0 2006.285.11:05:00.84#ibcon#wrote, iclass 14, count 0 2006.285.11:05:00.84#ibcon#about to read 3, iclass 14, count 0 2006.285.11:05:00.87#ibcon#read 3, iclass 14, count 0 2006.285.11:05:00.87#ibcon#about to read 4, iclass 14, count 0 2006.285.11:05:00.87#ibcon#read 4, iclass 14, count 0 2006.285.11:05:00.87#ibcon#about to read 5, iclass 14, count 0 2006.285.11:05:00.87#ibcon#read 5, iclass 14, count 0 2006.285.11:05:00.87#ibcon#about to read 6, iclass 14, count 0 2006.285.11:05:00.87#ibcon#read 6, iclass 14, count 0 2006.285.11:05:00.87#ibcon#end of sib2, iclass 14, count 0 2006.285.11:05:00.87#ibcon#*after write, iclass 14, count 0 2006.285.11:05:00.87#ibcon#*before return 0, iclass 14, count 0 2006.285.11:05:00.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:05:00.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:05:00.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:05:00.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:05:00.87$vck44/vbbw=wide 2006.285.11:05:00.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.11:05:00.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.11:05:00.87#ibcon#ireg 8 cls_cnt 0 2006.285.11:05:00.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:05:00.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:05:00.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:05:00.94#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:05:00.94#ibcon#first serial, iclass 16, count 0 2006.285.11:05:00.94#ibcon#enter sib2, iclass 16, count 0 2006.285.11:05:00.94#ibcon#flushed, iclass 16, count 0 2006.285.11:05:00.94#ibcon#about to write, iclass 16, count 0 2006.285.11:05:00.94#ibcon#wrote, iclass 16, count 0 2006.285.11:05:00.94#ibcon#about to read 3, iclass 16, count 0 2006.285.11:05:00.96#ibcon#read 3, iclass 16, count 0 2006.285.11:05:00.96#ibcon#about to read 4, iclass 16, count 0 2006.285.11:05:00.96#ibcon#read 4, iclass 16, count 0 2006.285.11:05:00.96#ibcon#about to read 5, iclass 16, count 0 2006.285.11:05:00.96#ibcon#read 5, iclass 16, count 0 2006.285.11:05:00.96#ibcon#about to read 6, iclass 16, count 0 2006.285.11:05:00.96#ibcon#read 6, iclass 16, count 0 2006.285.11:05:00.96#ibcon#end of sib2, iclass 16, count 0 2006.285.11:05:00.96#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:05:00.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:05:00.96#ibcon#[27=BW32\r\n] 2006.285.11:05:00.96#ibcon#*before write, iclass 16, count 0 2006.285.11:05:00.96#ibcon#enter sib2, iclass 16, count 0 2006.285.11:05:00.96#ibcon#flushed, iclass 16, count 0 2006.285.11:05:00.96#ibcon#about to write, iclass 16, count 0 2006.285.11:05:00.96#ibcon#wrote, iclass 16, count 0 2006.285.11:05:00.96#ibcon#about to read 3, iclass 16, count 0 2006.285.11:05:00.99#ibcon#read 3, iclass 16, count 0 2006.285.11:05:00.99#ibcon#about to read 4, iclass 16, count 0 2006.285.11:05:00.99#ibcon#read 4, iclass 16, count 0 2006.285.11:05:00.99#ibcon#about to read 5, iclass 16, count 0 2006.285.11:05:00.99#ibcon#read 5, iclass 16, count 0 2006.285.11:05:00.99#ibcon#about to read 6, iclass 16, count 0 2006.285.11:05:00.99#ibcon#read 6, iclass 16, count 0 2006.285.11:05:00.99#ibcon#end of sib2, iclass 16, count 0 2006.285.11:05:00.99#ibcon#*after write, iclass 16, count 0 2006.285.11:05:00.99#ibcon#*before return 0, iclass 16, count 0 2006.285.11:05:00.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:05:00.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:05:00.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:05:00.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:05:00.99$setupk4/ifdk4 2006.285.11:05:00.99$ifdk4/lo= 2006.285.11:05:00.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:05:00.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:05:00.99$ifdk4/patch= 2006.285.11:05:00.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:05:00.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:05:00.99$setupk4/!*+20s 2006.285.11:05:04.14#abcon#<5=/05 1.0 1.8 19.46 931015.0\r\n> 2006.285.11:05:04.16#abcon#{5=INTERFACE CLEAR} 2006.285.11:05:04.22#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:05:14.31#abcon#<5=/05 1.0 1.8 19.46 931015.0\r\n> 2006.285.11:05:14.33#abcon#{5=INTERFACE CLEAR} 2006.285.11:05:14.39#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:05:15.50$setupk4/"tpicd 2006.285.11:05:15.50$setupk4/echo=off 2006.285.11:05:15.50$setupk4/xlog=off 2006.285.11:05:15.50:!2006.285.11:06:41 2006.285.11:05:30.14#trakl#Source acquired 2006.285.11:05:31.14#flagr#flagr/antenna,acquired 2006.285.11:06:41.00:preob 2006.285.11:06:41.14/onsource/TRACKING 2006.285.11:06:41.14:!2006.285.11:06:51 2006.285.11:06:51.00:"tape 2006.285.11:06:51.00:"st=record 2006.285.11:06:51.00:data_valid=on 2006.285.11:06:51.00:midob 2006.285.11:06:52.14/onsource/TRACKING 2006.285.11:06:52.14/wx/19.45,1015.1,93 2006.285.11:06:52.35/cable/+6.4877E-03 2006.285.11:06:53.44/va/01,07,usb,yes,33,36 2006.285.11:06:53.44/va/02,06,usb,yes,33,34 2006.285.11:06:53.44/va/03,07,usb,yes,33,35 2006.285.11:06:53.44/va/04,06,usb,yes,34,36 2006.285.11:06:53.44/va/05,03,usb,yes,34,34 2006.285.11:06:53.44/va/06,04,usb,yes,31,30 2006.285.11:06:53.44/va/07,04,usb,yes,31,32 2006.285.11:06:53.44/va/08,03,usb,yes,32,39 2006.285.11:06:53.67/valo/01,524.99,yes,locked 2006.285.11:06:53.67/valo/02,534.99,yes,locked 2006.285.11:06:53.67/valo/03,564.99,yes,locked 2006.285.11:06:53.67/valo/04,624.99,yes,locked 2006.285.11:06:53.67/valo/05,734.99,yes,locked 2006.285.11:06:53.67/valo/06,814.99,yes,locked 2006.285.11:06:53.67/valo/07,864.99,yes,locked 2006.285.11:06:53.67/valo/08,884.99,yes,locked 2006.285.11:06:54.76/vb/01,04,usb,yes,31,29 2006.285.11:06:54.76/vb/02,05,usb,yes,30,29 2006.285.11:06:54.76/vb/03,04,usb,yes,31,34 2006.285.11:06:54.76/vb/04,05,usb,yes,31,30 2006.285.11:06:54.76/vb/05,04,usb,yes,27,30 2006.285.11:06:54.76/vb/06,03,usb,yes,39,35 2006.285.11:06:54.76/vb/07,04,usb,yes,32,32 2006.285.11:06:54.76/vb/08,04,usb,yes,29,32 2006.285.11:06:54.99/vblo/01,629.99,yes,locked 2006.285.11:06:54.99/vblo/02,634.99,yes,locked 2006.285.11:06:54.99/vblo/03,649.99,yes,locked 2006.285.11:06:54.99/vblo/04,679.99,yes,locked 2006.285.11:06:54.99/vblo/05,709.99,yes,locked 2006.285.11:06:54.99/vblo/06,719.99,yes,locked 2006.285.11:06:54.99/vblo/07,734.99,yes,locked 2006.285.11:06:54.99/vblo/08,744.99,yes,locked 2006.285.11:06:55.14/vabw/8 2006.285.11:06:55.29/vbbw/8 2006.285.11:06:55.38/xfe/off,on,12.2 2006.285.11:06:55.76/ifatt/23,28,28,28 2006.285.11:06:56.08/fmout-gps/S +2.76E-07 2006.285.11:06:56.10:!2006.285.11:07:51 2006.285.11:07:51.00:data_valid=off 2006.285.11:07:51.00:"et 2006.285.11:07:51.00:!+3s 2006.285.11:07:54.01:"tape 2006.285.11:07:54.01:postob 2006.285.11:07:54.20/cable/+6.4885E-03 2006.285.11:07:54.20/wx/19.45,1015.1,93 2006.285.11:07:55.07/fmout-gps/S +2.75E-07 2006.285.11:07:55.07:scan_name=285-1112,jd0610,110 2006.285.11:07:55.07:source=0059+581,010245.76,582411.1,2000.0,cw 2006.285.11:07:55.14#flagr#flagr/antenna,new-source 2006.285.11:07:56.14:checkk5 2006.285.11:07:56.61/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:07:56.98/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:07:57.67/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:07:58.04/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:07:58.37/chk_obsdata//k5ts1/T2851106??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.11:07:58.72/chk_obsdata//k5ts2/T2851106??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.11:07:59.06/chk_obsdata//k5ts3/T2851106??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.11:07:59.53/chk_obsdata//k5ts4/T2851106??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.11:08:00.26/k5log//k5ts1_log_newline 2006.285.11:08:01.07/k5log//k5ts2_log_newline 2006.285.11:08:01.85/k5log//k5ts3_log_newline 2006.285.11:08:02.62/k5log//k5ts4_log_newline 2006.285.11:08:02.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:08:02.64:setupk4=1 2006.285.11:08:02.64$setupk4/echo=on 2006.285.11:08:02.64$setupk4/pcalon 2006.285.11:08:02.64$pcalon/"no phase cal control is implemented here 2006.285.11:08:02.64$setupk4/"tpicd=stop 2006.285.11:08:02.64$setupk4/"rec=synch_on 2006.285.11:08:02.64$setupk4/"rec_mode=128 2006.285.11:08:02.64$setupk4/!* 2006.285.11:08:02.64$setupk4/recpk4 2006.285.11:08:02.64$recpk4/recpatch= 2006.285.11:08:02.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:08:02.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:08:02.65$setupk4/vck44 2006.285.11:08:02.65$vck44/valo=1,524.99 2006.285.11:08:02.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.11:08:02.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.11:08:02.65#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:02.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:08:02.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:08:02.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:08:02.65#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:08:02.65#ibcon#first serial, iclass 21, count 0 2006.285.11:08:02.65#ibcon#enter sib2, iclass 21, count 0 2006.285.11:08:02.65#ibcon#flushed, iclass 21, count 0 2006.285.11:08:02.65#ibcon#about to write, iclass 21, count 0 2006.285.11:08:02.65#ibcon#wrote, iclass 21, count 0 2006.285.11:08:02.65#ibcon#about to read 3, iclass 21, count 0 2006.285.11:08:02.67#ibcon#read 3, iclass 21, count 0 2006.285.11:08:02.67#ibcon#about to read 4, iclass 21, count 0 2006.285.11:08:02.67#ibcon#read 4, iclass 21, count 0 2006.285.11:08:02.67#ibcon#about to read 5, iclass 21, count 0 2006.285.11:08:02.67#ibcon#read 5, iclass 21, count 0 2006.285.11:08:02.67#ibcon#about to read 6, iclass 21, count 0 2006.285.11:08:02.67#ibcon#read 6, iclass 21, count 0 2006.285.11:08:02.67#ibcon#end of sib2, iclass 21, count 0 2006.285.11:08:02.67#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:08:02.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:08:02.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:08:02.67#ibcon#*before write, iclass 21, count 0 2006.285.11:08:02.67#ibcon#enter sib2, iclass 21, count 0 2006.285.11:08:02.67#ibcon#flushed, iclass 21, count 0 2006.285.11:08:02.67#ibcon#about to write, iclass 21, count 0 2006.285.11:08:02.67#ibcon#wrote, iclass 21, count 0 2006.285.11:08:02.67#ibcon#about to read 3, iclass 21, count 0 2006.285.11:08:02.72#ibcon#read 3, iclass 21, count 0 2006.285.11:08:02.72#ibcon#about to read 4, iclass 21, count 0 2006.285.11:08:02.72#ibcon#read 4, iclass 21, count 0 2006.285.11:08:02.72#ibcon#about to read 5, iclass 21, count 0 2006.285.11:08:02.72#ibcon#read 5, iclass 21, count 0 2006.285.11:08:02.72#ibcon#about to read 6, iclass 21, count 0 2006.285.11:08:02.72#ibcon#read 6, iclass 21, count 0 2006.285.11:08:02.72#ibcon#end of sib2, iclass 21, count 0 2006.285.11:08:02.72#ibcon#*after write, iclass 21, count 0 2006.285.11:08:02.72#ibcon#*before return 0, iclass 21, count 0 2006.285.11:08:02.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:08:02.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:08:02.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:08:02.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:08:02.72$vck44/va=1,7 2006.285.11:08:02.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.11:08:02.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.11:08:02.72#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:02.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:08:02.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:08:02.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:08:02.72#ibcon#enter wrdev, iclass 23, count 2 2006.285.11:08:02.72#ibcon#first serial, iclass 23, count 2 2006.285.11:08:02.72#ibcon#enter sib2, iclass 23, count 2 2006.285.11:08:02.72#ibcon#flushed, iclass 23, count 2 2006.285.11:08:02.72#ibcon#about to write, iclass 23, count 2 2006.285.11:08:02.72#ibcon#wrote, iclass 23, count 2 2006.285.11:08:02.72#ibcon#about to read 3, iclass 23, count 2 2006.285.11:08:02.74#ibcon#read 3, iclass 23, count 2 2006.285.11:08:02.74#ibcon#about to read 4, iclass 23, count 2 2006.285.11:08:02.74#ibcon#read 4, iclass 23, count 2 2006.285.11:08:02.74#ibcon#about to read 5, iclass 23, count 2 2006.285.11:08:02.74#ibcon#read 5, iclass 23, count 2 2006.285.11:08:02.74#ibcon#about to read 6, iclass 23, count 2 2006.285.11:08:02.74#ibcon#read 6, iclass 23, count 2 2006.285.11:08:02.74#ibcon#end of sib2, iclass 23, count 2 2006.285.11:08:02.74#ibcon#*mode == 0, iclass 23, count 2 2006.285.11:08:02.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.11:08:02.74#ibcon#[25=AT01-07\r\n] 2006.285.11:08:02.74#ibcon#*before write, iclass 23, count 2 2006.285.11:08:02.74#ibcon#enter sib2, iclass 23, count 2 2006.285.11:08:02.74#ibcon#flushed, iclass 23, count 2 2006.285.11:08:02.74#ibcon#about to write, iclass 23, count 2 2006.285.11:08:02.74#ibcon#wrote, iclass 23, count 2 2006.285.11:08:02.74#ibcon#about to read 3, iclass 23, count 2 2006.285.11:08:02.77#ibcon#read 3, iclass 23, count 2 2006.285.11:08:02.77#ibcon#about to read 4, iclass 23, count 2 2006.285.11:08:02.77#ibcon#read 4, iclass 23, count 2 2006.285.11:08:02.77#ibcon#about to read 5, iclass 23, count 2 2006.285.11:08:02.77#ibcon#read 5, iclass 23, count 2 2006.285.11:08:02.77#ibcon#about to read 6, iclass 23, count 2 2006.285.11:08:02.77#ibcon#read 6, iclass 23, count 2 2006.285.11:08:02.77#ibcon#end of sib2, iclass 23, count 2 2006.285.11:08:02.77#ibcon#*after write, iclass 23, count 2 2006.285.11:08:02.77#ibcon#*before return 0, iclass 23, count 2 2006.285.11:08:02.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:08:02.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:08:02.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.11:08:02.77#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:02.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:08:02.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:08:02.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:08:02.89#ibcon#enter wrdev, iclass 23, count 0 2006.285.11:08:02.89#ibcon#first serial, iclass 23, count 0 2006.285.11:08:02.89#ibcon#enter sib2, iclass 23, count 0 2006.285.11:08:02.89#ibcon#flushed, iclass 23, count 0 2006.285.11:08:02.89#ibcon#about to write, iclass 23, count 0 2006.285.11:08:02.89#ibcon#wrote, iclass 23, count 0 2006.285.11:08:02.89#ibcon#about to read 3, iclass 23, count 0 2006.285.11:08:02.91#ibcon#read 3, iclass 23, count 0 2006.285.11:08:02.91#ibcon#about to read 4, iclass 23, count 0 2006.285.11:08:02.91#ibcon#read 4, iclass 23, count 0 2006.285.11:08:02.91#ibcon#about to read 5, iclass 23, count 0 2006.285.11:08:02.91#ibcon#read 5, iclass 23, count 0 2006.285.11:08:02.91#ibcon#about to read 6, iclass 23, count 0 2006.285.11:08:02.91#ibcon#read 6, iclass 23, count 0 2006.285.11:08:02.91#ibcon#end of sib2, iclass 23, count 0 2006.285.11:08:02.91#ibcon#*mode == 0, iclass 23, count 0 2006.285.11:08:02.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.11:08:02.91#ibcon#[25=USB\r\n] 2006.285.11:08:02.91#ibcon#*before write, iclass 23, count 0 2006.285.11:08:02.91#ibcon#enter sib2, iclass 23, count 0 2006.285.11:08:02.91#ibcon#flushed, iclass 23, count 0 2006.285.11:08:02.91#ibcon#about to write, iclass 23, count 0 2006.285.11:08:02.91#ibcon#wrote, iclass 23, count 0 2006.285.11:08:02.91#ibcon#about to read 3, iclass 23, count 0 2006.285.11:08:02.94#ibcon#read 3, iclass 23, count 0 2006.285.11:08:02.94#ibcon#about to read 4, iclass 23, count 0 2006.285.11:08:02.94#ibcon#read 4, iclass 23, count 0 2006.285.11:08:02.94#ibcon#about to read 5, iclass 23, count 0 2006.285.11:08:02.94#ibcon#read 5, iclass 23, count 0 2006.285.11:08:02.94#ibcon#about to read 6, iclass 23, count 0 2006.285.11:08:02.94#ibcon#read 6, iclass 23, count 0 2006.285.11:08:02.94#ibcon#end of sib2, iclass 23, count 0 2006.285.11:08:02.94#ibcon#*after write, iclass 23, count 0 2006.285.11:08:02.94#ibcon#*before return 0, iclass 23, count 0 2006.285.11:08:02.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:08:02.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:08:02.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.11:08:02.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.11:08:02.94$vck44/valo=2,534.99 2006.285.11:08:02.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.11:08:02.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.11:08:02.94#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:02.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:08:02.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:08:02.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:08:02.94#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:08:02.94#ibcon#first serial, iclass 25, count 0 2006.285.11:08:02.94#ibcon#enter sib2, iclass 25, count 0 2006.285.11:08:02.94#ibcon#flushed, iclass 25, count 0 2006.285.11:08:02.94#ibcon#about to write, iclass 25, count 0 2006.285.11:08:02.94#ibcon#wrote, iclass 25, count 0 2006.285.11:08:02.94#ibcon#about to read 3, iclass 25, count 0 2006.285.11:08:02.96#ibcon#read 3, iclass 25, count 0 2006.285.11:08:02.96#ibcon#about to read 4, iclass 25, count 0 2006.285.11:08:02.96#ibcon#read 4, iclass 25, count 0 2006.285.11:08:02.96#ibcon#about to read 5, iclass 25, count 0 2006.285.11:08:02.96#ibcon#read 5, iclass 25, count 0 2006.285.11:08:02.96#ibcon#about to read 6, iclass 25, count 0 2006.285.11:08:02.96#ibcon#read 6, iclass 25, count 0 2006.285.11:08:02.96#ibcon#end of sib2, iclass 25, count 0 2006.285.11:08:02.96#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:08:02.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:08:02.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:08:02.96#ibcon#*before write, iclass 25, count 0 2006.285.11:08:02.96#ibcon#enter sib2, iclass 25, count 0 2006.285.11:08:02.96#ibcon#flushed, iclass 25, count 0 2006.285.11:08:02.96#ibcon#about to write, iclass 25, count 0 2006.285.11:08:02.96#ibcon#wrote, iclass 25, count 0 2006.285.11:08:02.96#ibcon#about to read 3, iclass 25, count 0 2006.285.11:08:03.00#ibcon#read 3, iclass 25, count 0 2006.285.11:08:03.00#ibcon#about to read 4, iclass 25, count 0 2006.285.11:08:03.00#ibcon#read 4, iclass 25, count 0 2006.285.11:08:03.00#ibcon#about to read 5, iclass 25, count 0 2006.285.11:08:03.00#ibcon#read 5, iclass 25, count 0 2006.285.11:08:03.00#ibcon#about to read 6, iclass 25, count 0 2006.285.11:08:03.00#ibcon#read 6, iclass 25, count 0 2006.285.11:08:03.00#ibcon#end of sib2, iclass 25, count 0 2006.285.11:08:03.00#ibcon#*after write, iclass 25, count 0 2006.285.11:08:03.00#ibcon#*before return 0, iclass 25, count 0 2006.285.11:08:03.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:08:03.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:08:03.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:08:03.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:08:03.00$vck44/va=2,6 2006.285.11:08:03.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.11:08:03.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.11:08:03.00#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:03.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:08:03.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:08:03.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:08:03.06#ibcon#enter wrdev, iclass 27, count 2 2006.285.11:08:03.06#ibcon#first serial, iclass 27, count 2 2006.285.11:08:03.06#ibcon#enter sib2, iclass 27, count 2 2006.285.11:08:03.06#ibcon#flushed, iclass 27, count 2 2006.285.11:08:03.06#ibcon#about to write, iclass 27, count 2 2006.285.11:08:03.06#ibcon#wrote, iclass 27, count 2 2006.285.11:08:03.06#ibcon#about to read 3, iclass 27, count 2 2006.285.11:08:03.08#ibcon#read 3, iclass 27, count 2 2006.285.11:08:03.08#ibcon#about to read 4, iclass 27, count 2 2006.285.11:08:03.08#ibcon#read 4, iclass 27, count 2 2006.285.11:08:03.08#ibcon#about to read 5, iclass 27, count 2 2006.285.11:08:03.08#ibcon#read 5, iclass 27, count 2 2006.285.11:08:03.08#ibcon#about to read 6, iclass 27, count 2 2006.285.11:08:03.08#ibcon#read 6, iclass 27, count 2 2006.285.11:08:03.08#ibcon#end of sib2, iclass 27, count 2 2006.285.11:08:03.08#ibcon#*mode == 0, iclass 27, count 2 2006.285.11:08:03.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.11:08:03.08#ibcon#[25=AT02-06\r\n] 2006.285.11:08:03.08#ibcon#*before write, iclass 27, count 2 2006.285.11:08:03.08#ibcon#enter sib2, iclass 27, count 2 2006.285.11:08:03.08#ibcon#flushed, iclass 27, count 2 2006.285.11:08:03.08#ibcon#about to write, iclass 27, count 2 2006.285.11:08:03.08#ibcon#wrote, iclass 27, count 2 2006.285.11:08:03.08#ibcon#about to read 3, iclass 27, count 2 2006.285.11:08:03.11#ibcon#read 3, iclass 27, count 2 2006.285.11:08:03.11#ibcon#about to read 4, iclass 27, count 2 2006.285.11:08:03.11#ibcon#read 4, iclass 27, count 2 2006.285.11:08:03.11#ibcon#about to read 5, iclass 27, count 2 2006.285.11:08:03.11#ibcon#read 5, iclass 27, count 2 2006.285.11:08:03.11#ibcon#about to read 6, iclass 27, count 2 2006.285.11:08:03.11#ibcon#read 6, iclass 27, count 2 2006.285.11:08:03.11#ibcon#end of sib2, iclass 27, count 2 2006.285.11:08:03.11#ibcon#*after write, iclass 27, count 2 2006.285.11:08:03.11#ibcon#*before return 0, iclass 27, count 2 2006.285.11:08:03.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:08:03.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:08:03.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.11:08:03.11#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:03.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:08:03.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:08:03.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:08:03.23#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:08:03.23#ibcon#first serial, iclass 27, count 0 2006.285.11:08:03.23#ibcon#enter sib2, iclass 27, count 0 2006.285.11:08:03.23#ibcon#flushed, iclass 27, count 0 2006.285.11:08:03.23#ibcon#about to write, iclass 27, count 0 2006.285.11:08:03.23#ibcon#wrote, iclass 27, count 0 2006.285.11:08:03.23#ibcon#about to read 3, iclass 27, count 0 2006.285.11:08:03.25#ibcon#read 3, iclass 27, count 0 2006.285.11:08:03.25#ibcon#about to read 4, iclass 27, count 0 2006.285.11:08:03.25#ibcon#read 4, iclass 27, count 0 2006.285.11:08:03.25#ibcon#about to read 5, iclass 27, count 0 2006.285.11:08:03.25#ibcon#read 5, iclass 27, count 0 2006.285.11:08:03.25#ibcon#about to read 6, iclass 27, count 0 2006.285.11:08:03.25#ibcon#read 6, iclass 27, count 0 2006.285.11:08:03.25#ibcon#end of sib2, iclass 27, count 0 2006.285.11:08:03.25#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:08:03.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:08:03.25#ibcon#[25=USB\r\n] 2006.285.11:08:03.25#ibcon#*before write, iclass 27, count 0 2006.285.11:08:03.25#ibcon#enter sib2, iclass 27, count 0 2006.285.11:08:03.25#ibcon#flushed, iclass 27, count 0 2006.285.11:08:03.25#ibcon#about to write, iclass 27, count 0 2006.285.11:08:03.25#ibcon#wrote, iclass 27, count 0 2006.285.11:08:03.25#ibcon#about to read 3, iclass 27, count 0 2006.285.11:08:03.28#ibcon#read 3, iclass 27, count 0 2006.285.11:08:03.28#ibcon#about to read 4, iclass 27, count 0 2006.285.11:08:03.28#ibcon#read 4, iclass 27, count 0 2006.285.11:08:03.28#ibcon#about to read 5, iclass 27, count 0 2006.285.11:08:03.28#ibcon#read 5, iclass 27, count 0 2006.285.11:08:03.28#ibcon#about to read 6, iclass 27, count 0 2006.285.11:08:03.28#ibcon#read 6, iclass 27, count 0 2006.285.11:08:03.28#ibcon#end of sib2, iclass 27, count 0 2006.285.11:08:03.28#ibcon#*after write, iclass 27, count 0 2006.285.11:08:03.28#ibcon#*before return 0, iclass 27, count 0 2006.285.11:08:03.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:08:03.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:08:03.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:08:03.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:08:03.28$vck44/valo=3,564.99 2006.285.11:08:03.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.11:08:03.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.11:08:03.28#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:03.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:08:03.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:08:03.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:08:03.28#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:08:03.28#ibcon#first serial, iclass 29, count 0 2006.285.11:08:03.28#ibcon#enter sib2, iclass 29, count 0 2006.285.11:08:03.28#ibcon#flushed, iclass 29, count 0 2006.285.11:08:03.28#ibcon#about to write, iclass 29, count 0 2006.285.11:08:03.28#ibcon#wrote, iclass 29, count 0 2006.285.11:08:03.28#ibcon#about to read 3, iclass 29, count 0 2006.285.11:08:03.30#ibcon#read 3, iclass 29, count 0 2006.285.11:08:03.30#ibcon#about to read 4, iclass 29, count 0 2006.285.11:08:03.30#ibcon#read 4, iclass 29, count 0 2006.285.11:08:03.30#ibcon#about to read 5, iclass 29, count 0 2006.285.11:08:03.30#ibcon#read 5, iclass 29, count 0 2006.285.11:08:03.30#ibcon#about to read 6, iclass 29, count 0 2006.285.11:08:03.30#ibcon#read 6, iclass 29, count 0 2006.285.11:08:03.30#ibcon#end of sib2, iclass 29, count 0 2006.285.11:08:03.30#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:08:03.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:08:03.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:08:03.30#ibcon#*before write, iclass 29, count 0 2006.285.11:08:03.30#ibcon#enter sib2, iclass 29, count 0 2006.285.11:08:03.30#ibcon#flushed, iclass 29, count 0 2006.285.11:08:03.30#ibcon#about to write, iclass 29, count 0 2006.285.11:08:03.30#ibcon#wrote, iclass 29, count 0 2006.285.11:08:03.30#ibcon#about to read 3, iclass 29, count 0 2006.285.11:08:03.34#ibcon#read 3, iclass 29, count 0 2006.285.11:08:03.34#ibcon#about to read 4, iclass 29, count 0 2006.285.11:08:03.34#ibcon#read 4, iclass 29, count 0 2006.285.11:08:03.34#ibcon#about to read 5, iclass 29, count 0 2006.285.11:08:03.34#ibcon#read 5, iclass 29, count 0 2006.285.11:08:03.34#ibcon#about to read 6, iclass 29, count 0 2006.285.11:08:03.34#ibcon#read 6, iclass 29, count 0 2006.285.11:08:03.34#ibcon#end of sib2, iclass 29, count 0 2006.285.11:08:03.34#ibcon#*after write, iclass 29, count 0 2006.285.11:08:03.34#ibcon#*before return 0, iclass 29, count 0 2006.285.11:08:03.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:08:03.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:08:03.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:08:03.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:08:03.34$vck44/va=3,7 2006.285.11:08:03.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.11:08:03.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.11:08:03.34#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:03.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:08:03.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:08:03.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:08:03.40#ibcon#enter wrdev, iclass 31, count 2 2006.285.11:08:03.40#ibcon#first serial, iclass 31, count 2 2006.285.11:08:03.40#ibcon#enter sib2, iclass 31, count 2 2006.285.11:08:03.40#ibcon#flushed, iclass 31, count 2 2006.285.11:08:03.40#ibcon#about to write, iclass 31, count 2 2006.285.11:08:03.40#ibcon#wrote, iclass 31, count 2 2006.285.11:08:03.40#ibcon#about to read 3, iclass 31, count 2 2006.285.11:08:03.42#ibcon#read 3, iclass 31, count 2 2006.285.11:08:03.42#ibcon#about to read 4, iclass 31, count 2 2006.285.11:08:03.42#ibcon#read 4, iclass 31, count 2 2006.285.11:08:03.42#ibcon#about to read 5, iclass 31, count 2 2006.285.11:08:03.42#ibcon#read 5, iclass 31, count 2 2006.285.11:08:03.42#ibcon#about to read 6, iclass 31, count 2 2006.285.11:08:03.42#ibcon#read 6, iclass 31, count 2 2006.285.11:08:03.42#ibcon#end of sib2, iclass 31, count 2 2006.285.11:08:03.42#ibcon#*mode == 0, iclass 31, count 2 2006.285.11:08:03.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.11:08:03.42#ibcon#[25=AT03-07\r\n] 2006.285.11:08:03.42#ibcon#*before write, iclass 31, count 2 2006.285.11:08:03.42#ibcon#enter sib2, iclass 31, count 2 2006.285.11:08:03.42#ibcon#flushed, iclass 31, count 2 2006.285.11:08:03.42#ibcon#about to write, iclass 31, count 2 2006.285.11:08:03.42#ibcon#wrote, iclass 31, count 2 2006.285.11:08:03.42#ibcon#about to read 3, iclass 31, count 2 2006.285.11:08:03.45#ibcon#read 3, iclass 31, count 2 2006.285.11:08:03.45#ibcon#about to read 4, iclass 31, count 2 2006.285.11:08:03.45#ibcon#read 4, iclass 31, count 2 2006.285.11:08:03.45#ibcon#about to read 5, iclass 31, count 2 2006.285.11:08:03.45#ibcon#read 5, iclass 31, count 2 2006.285.11:08:03.45#ibcon#about to read 6, iclass 31, count 2 2006.285.11:08:03.45#ibcon#read 6, iclass 31, count 2 2006.285.11:08:03.45#ibcon#end of sib2, iclass 31, count 2 2006.285.11:08:03.45#ibcon#*after write, iclass 31, count 2 2006.285.11:08:03.45#ibcon#*before return 0, iclass 31, count 2 2006.285.11:08:03.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:08:03.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:08:03.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.11:08:03.45#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:03.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:08:03.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:08:03.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:08:03.57#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:08:03.57#ibcon#first serial, iclass 31, count 0 2006.285.11:08:03.57#ibcon#enter sib2, iclass 31, count 0 2006.285.11:08:03.57#ibcon#flushed, iclass 31, count 0 2006.285.11:08:03.57#ibcon#about to write, iclass 31, count 0 2006.285.11:08:03.57#ibcon#wrote, iclass 31, count 0 2006.285.11:08:03.57#ibcon#about to read 3, iclass 31, count 0 2006.285.11:08:03.59#ibcon#read 3, iclass 31, count 0 2006.285.11:08:03.59#ibcon#about to read 4, iclass 31, count 0 2006.285.11:08:03.59#ibcon#read 4, iclass 31, count 0 2006.285.11:08:03.59#ibcon#about to read 5, iclass 31, count 0 2006.285.11:08:03.59#ibcon#read 5, iclass 31, count 0 2006.285.11:08:03.59#ibcon#about to read 6, iclass 31, count 0 2006.285.11:08:03.59#ibcon#read 6, iclass 31, count 0 2006.285.11:08:03.59#ibcon#end of sib2, iclass 31, count 0 2006.285.11:08:03.59#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:08:03.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:08:03.59#ibcon#[25=USB\r\n] 2006.285.11:08:03.59#ibcon#*before write, iclass 31, count 0 2006.285.11:08:03.59#ibcon#enter sib2, iclass 31, count 0 2006.285.11:08:03.59#ibcon#flushed, iclass 31, count 0 2006.285.11:08:03.59#ibcon#about to write, iclass 31, count 0 2006.285.11:08:03.59#ibcon#wrote, iclass 31, count 0 2006.285.11:08:03.59#ibcon#about to read 3, iclass 31, count 0 2006.285.11:08:03.62#ibcon#read 3, iclass 31, count 0 2006.285.11:08:03.62#ibcon#about to read 4, iclass 31, count 0 2006.285.11:08:03.62#ibcon#read 4, iclass 31, count 0 2006.285.11:08:03.62#ibcon#about to read 5, iclass 31, count 0 2006.285.11:08:03.62#ibcon#read 5, iclass 31, count 0 2006.285.11:08:03.62#ibcon#about to read 6, iclass 31, count 0 2006.285.11:08:03.62#ibcon#read 6, iclass 31, count 0 2006.285.11:08:03.62#ibcon#end of sib2, iclass 31, count 0 2006.285.11:08:03.62#ibcon#*after write, iclass 31, count 0 2006.285.11:08:03.62#ibcon#*before return 0, iclass 31, count 0 2006.285.11:08:03.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:08:03.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:08:03.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:08:03.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:08:03.62$vck44/valo=4,624.99 2006.285.11:08:03.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.11:08:03.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.11:08:03.62#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:03.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:08:03.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:08:03.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:08:03.62#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:08:03.62#ibcon#first serial, iclass 33, count 0 2006.285.11:08:03.62#ibcon#enter sib2, iclass 33, count 0 2006.285.11:08:03.62#ibcon#flushed, iclass 33, count 0 2006.285.11:08:03.62#ibcon#about to write, iclass 33, count 0 2006.285.11:08:03.62#ibcon#wrote, iclass 33, count 0 2006.285.11:08:03.62#ibcon#about to read 3, iclass 33, count 0 2006.285.11:08:03.64#ibcon#read 3, iclass 33, count 0 2006.285.11:08:03.64#ibcon#about to read 4, iclass 33, count 0 2006.285.11:08:03.64#ibcon#read 4, iclass 33, count 0 2006.285.11:08:03.64#ibcon#about to read 5, iclass 33, count 0 2006.285.11:08:03.64#ibcon#read 5, iclass 33, count 0 2006.285.11:08:03.64#ibcon#about to read 6, iclass 33, count 0 2006.285.11:08:03.64#ibcon#read 6, iclass 33, count 0 2006.285.11:08:03.64#ibcon#end of sib2, iclass 33, count 0 2006.285.11:08:03.64#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:08:03.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:08:03.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:08:03.64#ibcon#*before write, iclass 33, count 0 2006.285.11:08:03.64#ibcon#enter sib2, iclass 33, count 0 2006.285.11:08:03.64#ibcon#flushed, iclass 33, count 0 2006.285.11:08:03.64#ibcon#about to write, iclass 33, count 0 2006.285.11:08:03.64#ibcon#wrote, iclass 33, count 0 2006.285.11:08:03.64#ibcon#about to read 3, iclass 33, count 0 2006.285.11:08:03.68#ibcon#read 3, iclass 33, count 0 2006.285.11:08:03.68#ibcon#about to read 4, iclass 33, count 0 2006.285.11:08:03.68#ibcon#read 4, iclass 33, count 0 2006.285.11:08:03.68#ibcon#about to read 5, iclass 33, count 0 2006.285.11:08:03.68#ibcon#read 5, iclass 33, count 0 2006.285.11:08:03.68#ibcon#about to read 6, iclass 33, count 0 2006.285.11:08:03.68#ibcon#read 6, iclass 33, count 0 2006.285.11:08:03.68#ibcon#end of sib2, iclass 33, count 0 2006.285.11:08:03.68#ibcon#*after write, iclass 33, count 0 2006.285.11:08:03.68#ibcon#*before return 0, iclass 33, count 0 2006.285.11:08:03.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:08:03.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:08:03.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:08:03.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:08:03.68$vck44/va=4,6 2006.285.11:08:03.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.11:08:03.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.11:08:03.68#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:03.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:08:03.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:08:03.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:08:03.74#ibcon#enter wrdev, iclass 35, count 2 2006.285.11:08:03.74#ibcon#first serial, iclass 35, count 2 2006.285.11:08:03.74#ibcon#enter sib2, iclass 35, count 2 2006.285.11:08:03.74#ibcon#flushed, iclass 35, count 2 2006.285.11:08:03.74#ibcon#about to write, iclass 35, count 2 2006.285.11:08:03.74#ibcon#wrote, iclass 35, count 2 2006.285.11:08:03.74#ibcon#about to read 3, iclass 35, count 2 2006.285.11:08:03.76#ibcon#read 3, iclass 35, count 2 2006.285.11:08:03.76#ibcon#about to read 4, iclass 35, count 2 2006.285.11:08:03.76#ibcon#read 4, iclass 35, count 2 2006.285.11:08:03.76#ibcon#about to read 5, iclass 35, count 2 2006.285.11:08:03.76#ibcon#read 5, iclass 35, count 2 2006.285.11:08:03.76#ibcon#about to read 6, iclass 35, count 2 2006.285.11:08:03.76#ibcon#read 6, iclass 35, count 2 2006.285.11:08:03.76#ibcon#end of sib2, iclass 35, count 2 2006.285.11:08:03.76#ibcon#*mode == 0, iclass 35, count 2 2006.285.11:08:03.76#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.11:08:03.76#ibcon#[25=AT04-06\r\n] 2006.285.11:08:03.76#ibcon#*before write, iclass 35, count 2 2006.285.11:08:03.76#ibcon#enter sib2, iclass 35, count 2 2006.285.11:08:03.76#ibcon#flushed, iclass 35, count 2 2006.285.11:08:03.76#ibcon#about to write, iclass 35, count 2 2006.285.11:08:03.76#ibcon#wrote, iclass 35, count 2 2006.285.11:08:03.76#ibcon#about to read 3, iclass 35, count 2 2006.285.11:08:03.79#ibcon#read 3, iclass 35, count 2 2006.285.11:08:03.79#ibcon#about to read 4, iclass 35, count 2 2006.285.11:08:03.79#ibcon#read 4, iclass 35, count 2 2006.285.11:08:03.79#ibcon#about to read 5, iclass 35, count 2 2006.285.11:08:03.79#ibcon#read 5, iclass 35, count 2 2006.285.11:08:03.79#ibcon#about to read 6, iclass 35, count 2 2006.285.11:08:03.79#ibcon#read 6, iclass 35, count 2 2006.285.11:08:03.79#ibcon#end of sib2, iclass 35, count 2 2006.285.11:08:03.79#ibcon#*after write, iclass 35, count 2 2006.285.11:08:03.79#ibcon#*before return 0, iclass 35, count 2 2006.285.11:08:03.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:08:03.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:08:03.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.11:08:03.79#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:03.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:08:03.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:08:03.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:08:03.91#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:08:03.91#ibcon#first serial, iclass 35, count 0 2006.285.11:08:03.91#ibcon#enter sib2, iclass 35, count 0 2006.285.11:08:03.91#ibcon#flushed, iclass 35, count 0 2006.285.11:08:03.91#ibcon#about to write, iclass 35, count 0 2006.285.11:08:03.91#ibcon#wrote, iclass 35, count 0 2006.285.11:08:03.91#ibcon#about to read 3, iclass 35, count 0 2006.285.11:08:03.93#ibcon#read 3, iclass 35, count 0 2006.285.11:08:03.93#ibcon#about to read 4, iclass 35, count 0 2006.285.11:08:03.93#ibcon#read 4, iclass 35, count 0 2006.285.11:08:03.93#ibcon#about to read 5, iclass 35, count 0 2006.285.11:08:03.93#ibcon#read 5, iclass 35, count 0 2006.285.11:08:03.93#ibcon#about to read 6, iclass 35, count 0 2006.285.11:08:03.93#ibcon#read 6, iclass 35, count 0 2006.285.11:08:03.93#ibcon#end of sib2, iclass 35, count 0 2006.285.11:08:03.93#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:08:03.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:08:03.93#ibcon#[25=USB\r\n] 2006.285.11:08:03.93#ibcon#*before write, iclass 35, count 0 2006.285.11:08:03.93#ibcon#enter sib2, iclass 35, count 0 2006.285.11:08:03.93#ibcon#flushed, iclass 35, count 0 2006.285.11:08:03.93#ibcon#about to write, iclass 35, count 0 2006.285.11:08:03.93#ibcon#wrote, iclass 35, count 0 2006.285.11:08:03.93#ibcon#about to read 3, iclass 35, count 0 2006.285.11:08:03.96#ibcon#read 3, iclass 35, count 0 2006.285.11:08:03.96#ibcon#about to read 4, iclass 35, count 0 2006.285.11:08:03.96#ibcon#read 4, iclass 35, count 0 2006.285.11:08:03.96#ibcon#about to read 5, iclass 35, count 0 2006.285.11:08:03.96#ibcon#read 5, iclass 35, count 0 2006.285.11:08:03.96#ibcon#about to read 6, iclass 35, count 0 2006.285.11:08:03.96#ibcon#read 6, iclass 35, count 0 2006.285.11:08:03.96#ibcon#end of sib2, iclass 35, count 0 2006.285.11:08:03.96#ibcon#*after write, iclass 35, count 0 2006.285.11:08:03.96#ibcon#*before return 0, iclass 35, count 0 2006.285.11:08:03.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:08:03.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:08:03.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:08:03.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:08:03.96$vck44/valo=5,734.99 2006.285.11:08:03.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.11:08:03.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.11:08:03.96#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:03.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:08:03.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:08:03.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:08:03.96#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:08:03.96#ibcon#first serial, iclass 37, count 0 2006.285.11:08:03.96#ibcon#enter sib2, iclass 37, count 0 2006.285.11:08:03.96#ibcon#flushed, iclass 37, count 0 2006.285.11:08:03.96#ibcon#about to write, iclass 37, count 0 2006.285.11:08:03.96#ibcon#wrote, iclass 37, count 0 2006.285.11:08:03.96#ibcon#about to read 3, iclass 37, count 0 2006.285.11:08:03.98#ibcon#read 3, iclass 37, count 0 2006.285.11:08:03.98#ibcon#about to read 4, iclass 37, count 0 2006.285.11:08:03.98#ibcon#read 4, iclass 37, count 0 2006.285.11:08:03.98#ibcon#about to read 5, iclass 37, count 0 2006.285.11:08:03.98#ibcon#read 5, iclass 37, count 0 2006.285.11:08:03.98#ibcon#about to read 6, iclass 37, count 0 2006.285.11:08:03.98#ibcon#read 6, iclass 37, count 0 2006.285.11:08:03.98#ibcon#end of sib2, iclass 37, count 0 2006.285.11:08:03.98#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:08:03.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:08:03.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:08:03.98#ibcon#*before write, iclass 37, count 0 2006.285.11:08:03.98#ibcon#enter sib2, iclass 37, count 0 2006.285.11:08:03.98#ibcon#flushed, iclass 37, count 0 2006.285.11:08:03.98#ibcon#about to write, iclass 37, count 0 2006.285.11:08:03.98#ibcon#wrote, iclass 37, count 0 2006.285.11:08:03.98#ibcon#about to read 3, iclass 37, count 0 2006.285.11:08:04.02#ibcon#read 3, iclass 37, count 0 2006.285.11:08:04.02#ibcon#about to read 4, iclass 37, count 0 2006.285.11:08:04.02#ibcon#read 4, iclass 37, count 0 2006.285.11:08:04.02#ibcon#about to read 5, iclass 37, count 0 2006.285.11:08:04.02#ibcon#read 5, iclass 37, count 0 2006.285.11:08:04.02#ibcon#about to read 6, iclass 37, count 0 2006.285.11:08:04.02#ibcon#read 6, iclass 37, count 0 2006.285.11:08:04.02#ibcon#end of sib2, iclass 37, count 0 2006.285.11:08:04.02#ibcon#*after write, iclass 37, count 0 2006.285.11:08:04.02#ibcon#*before return 0, iclass 37, count 0 2006.285.11:08:04.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:08:04.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:08:04.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:08:04.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:08:04.02$vck44/va=5,3 2006.285.11:08:04.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.11:08:04.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.11:08:04.02#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:04.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:08:04.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:08:04.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:08:04.08#ibcon#enter wrdev, iclass 39, count 2 2006.285.11:08:04.08#ibcon#first serial, iclass 39, count 2 2006.285.11:08:04.08#ibcon#enter sib2, iclass 39, count 2 2006.285.11:08:04.08#ibcon#flushed, iclass 39, count 2 2006.285.11:08:04.08#ibcon#about to write, iclass 39, count 2 2006.285.11:08:04.08#ibcon#wrote, iclass 39, count 2 2006.285.11:08:04.08#ibcon#about to read 3, iclass 39, count 2 2006.285.11:08:04.10#ibcon#read 3, iclass 39, count 2 2006.285.11:08:04.10#ibcon#about to read 4, iclass 39, count 2 2006.285.11:08:04.10#ibcon#read 4, iclass 39, count 2 2006.285.11:08:04.10#ibcon#about to read 5, iclass 39, count 2 2006.285.11:08:04.10#ibcon#read 5, iclass 39, count 2 2006.285.11:08:04.10#ibcon#about to read 6, iclass 39, count 2 2006.285.11:08:04.10#ibcon#read 6, iclass 39, count 2 2006.285.11:08:04.10#ibcon#end of sib2, iclass 39, count 2 2006.285.11:08:04.10#ibcon#*mode == 0, iclass 39, count 2 2006.285.11:08:04.10#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.11:08:04.10#ibcon#[25=AT05-03\r\n] 2006.285.11:08:04.10#ibcon#*before write, iclass 39, count 2 2006.285.11:08:04.10#ibcon#enter sib2, iclass 39, count 2 2006.285.11:08:04.10#ibcon#flushed, iclass 39, count 2 2006.285.11:08:04.10#ibcon#about to write, iclass 39, count 2 2006.285.11:08:04.10#ibcon#wrote, iclass 39, count 2 2006.285.11:08:04.10#ibcon#about to read 3, iclass 39, count 2 2006.285.11:08:04.13#ibcon#read 3, iclass 39, count 2 2006.285.11:08:04.13#ibcon#about to read 4, iclass 39, count 2 2006.285.11:08:04.13#ibcon#read 4, iclass 39, count 2 2006.285.11:08:04.13#ibcon#about to read 5, iclass 39, count 2 2006.285.11:08:04.13#ibcon#read 5, iclass 39, count 2 2006.285.11:08:04.13#ibcon#about to read 6, iclass 39, count 2 2006.285.11:08:04.13#ibcon#read 6, iclass 39, count 2 2006.285.11:08:04.13#ibcon#end of sib2, iclass 39, count 2 2006.285.11:08:04.13#ibcon#*after write, iclass 39, count 2 2006.285.11:08:04.13#ibcon#*before return 0, iclass 39, count 2 2006.285.11:08:04.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:08:04.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:08:04.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.11:08:04.13#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:04.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:08:04.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:08:04.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:08:04.25#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:08:04.25#ibcon#first serial, iclass 39, count 0 2006.285.11:08:04.25#ibcon#enter sib2, iclass 39, count 0 2006.285.11:08:04.25#ibcon#flushed, iclass 39, count 0 2006.285.11:08:04.25#ibcon#about to write, iclass 39, count 0 2006.285.11:08:04.25#ibcon#wrote, iclass 39, count 0 2006.285.11:08:04.25#ibcon#about to read 3, iclass 39, count 0 2006.285.11:08:04.27#ibcon#read 3, iclass 39, count 0 2006.285.11:08:04.27#ibcon#about to read 4, iclass 39, count 0 2006.285.11:08:04.27#ibcon#read 4, iclass 39, count 0 2006.285.11:08:04.27#ibcon#about to read 5, iclass 39, count 0 2006.285.11:08:04.27#ibcon#read 5, iclass 39, count 0 2006.285.11:08:04.27#ibcon#about to read 6, iclass 39, count 0 2006.285.11:08:04.27#ibcon#read 6, iclass 39, count 0 2006.285.11:08:04.27#ibcon#end of sib2, iclass 39, count 0 2006.285.11:08:04.27#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:08:04.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:08:04.27#ibcon#[25=USB\r\n] 2006.285.11:08:04.27#ibcon#*before write, iclass 39, count 0 2006.285.11:08:04.27#ibcon#enter sib2, iclass 39, count 0 2006.285.11:08:04.27#ibcon#flushed, iclass 39, count 0 2006.285.11:08:04.27#ibcon#about to write, iclass 39, count 0 2006.285.11:08:04.27#ibcon#wrote, iclass 39, count 0 2006.285.11:08:04.27#ibcon#about to read 3, iclass 39, count 0 2006.285.11:08:04.30#ibcon#read 3, iclass 39, count 0 2006.285.11:08:04.30#ibcon#about to read 4, iclass 39, count 0 2006.285.11:08:04.30#ibcon#read 4, iclass 39, count 0 2006.285.11:08:04.30#ibcon#about to read 5, iclass 39, count 0 2006.285.11:08:04.30#ibcon#read 5, iclass 39, count 0 2006.285.11:08:04.30#ibcon#about to read 6, iclass 39, count 0 2006.285.11:08:04.30#ibcon#read 6, iclass 39, count 0 2006.285.11:08:04.30#ibcon#end of sib2, iclass 39, count 0 2006.285.11:08:04.30#ibcon#*after write, iclass 39, count 0 2006.285.11:08:04.30#ibcon#*before return 0, iclass 39, count 0 2006.285.11:08:04.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:08:04.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:08:04.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:08:04.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:08:04.30$vck44/valo=6,814.99 2006.285.11:08:04.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.11:08:04.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.11:08:04.30#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:04.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:08:04.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:08:04.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:08:04.30#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:08:04.30#ibcon#first serial, iclass 3, count 0 2006.285.11:08:04.30#ibcon#enter sib2, iclass 3, count 0 2006.285.11:08:04.30#ibcon#flushed, iclass 3, count 0 2006.285.11:08:04.30#ibcon#about to write, iclass 3, count 0 2006.285.11:08:04.30#ibcon#wrote, iclass 3, count 0 2006.285.11:08:04.30#ibcon#about to read 3, iclass 3, count 0 2006.285.11:08:04.32#ibcon#read 3, iclass 3, count 0 2006.285.11:08:04.32#ibcon#about to read 4, iclass 3, count 0 2006.285.11:08:04.32#ibcon#read 4, iclass 3, count 0 2006.285.11:08:04.32#ibcon#about to read 5, iclass 3, count 0 2006.285.11:08:04.32#ibcon#read 5, iclass 3, count 0 2006.285.11:08:04.32#ibcon#about to read 6, iclass 3, count 0 2006.285.11:08:04.32#ibcon#read 6, iclass 3, count 0 2006.285.11:08:04.32#ibcon#end of sib2, iclass 3, count 0 2006.285.11:08:04.32#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:08:04.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:08:04.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:08:04.32#ibcon#*before write, iclass 3, count 0 2006.285.11:08:04.32#ibcon#enter sib2, iclass 3, count 0 2006.285.11:08:04.32#ibcon#flushed, iclass 3, count 0 2006.285.11:08:04.32#ibcon#about to write, iclass 3, count 0 2006.285.11:08:04.32#ibcon#wrote, iclass 3, count 0 2006.285.11:08:04.32#ibcon#about to read 3, iclass 3, count 0 2006.285.11:08:04.36#ibcon#read 3, iclass 3, count 0 2006.285.11:08:04.36#ibcon#about to read 4, iclass 3, count 0 2006.285.11:08:04.36#ibcon#read 4, iclass 3, count 0 2006.285.11:08:04.36#ibcon#about to read 5, iclass 3, count 0 2006.285.11:08:04.36#ibcon#read 5, iclass 3, count 0 2006.285.11:08:04.36#ibcon#about to read 6, iclass 3, count 0 2006.285.11:08:04.36#ibcon#read 6, iclass 3, count 0 2006.285.11:08:04.36#ibcon#end of sib2, iclass 3, count 0 2006.285.11:08:04.36#ibcon#*after write, iclass 3, count 0 2006.285.11:08:04.36#ibcon#*before return 0, iclass 3, count 0 2006.285.11:08:04.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:08:04.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:08:04.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:08:04.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:08:04.36$vck44/va=6,4 2006.285.11:08:04.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.11:08:04.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.11:08:04.36#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:04.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:08:04.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:08:04.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:08:04.42#ibcon#enter wrdev, iclass 5, count 2 2006.285.11:08:04.42#ibcon#first serial, iclass 5, count 2 2006.285.11:08:04.42#ibcon#enter sib2, iclass 5, count 2 2006.285.11:08:04.42#ibcon#flushed, iclass 5, count 2 2006.285.11:08:04.42#ibcon#about to write, iclass 5, count 2 2006.285.11:08:04.42#ibcon#wrote, iclass 5, count 2 2006.285.11:08:04.42#ibcon#about to read 3, iclass 5, count 2 2006.285.11:08:04.44#ibcon#read 3, iclass 5, count 2 2006.285.11:08:04.44#ibcon#about to read 4, iclass 5, count 2 2006.285.11:08:04.44#ibcon#read 4, iclass 5, count 2 2006.285.11:08:04.44#ibcon#about to read 5, iclass 5, count 2 2006.285.11:08:04.44#ibcon#read 5, iclass 5, count 2 2006.285.11:08:04.44#ibcon#about to read 6, iclass 5, count 2 2006.285.11:08:04.44#ibcon#read 6, iclass 5, count 2 2006.285.11:08:04.44#ibcon#end of sib2, iclass 5, count 2 2006.285.11:08:04.44#ibcon#*mode == 0, iclass 5, count 2 2006.285.11:08:04.44#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.11:08:04.44#ibcon#[25=AT06-04\r\n] 2006.285.11:08:04.44#ibcon#*before write, iclass 5, count 2 2006.285.11:08:04.44#ibcon#enter sib2, iclass 5, count 2 2006.285.11:08:04.44#ibcon#flushed, iclass 5, count 2 2006.285.11:08:04.44#ibcon#about to write, iclass 5, count 2 2006.285.11:08:04.44#ibcon#wrote, iclass 5, count 2 2006.285.11:08:04.44#ibcon#about to read 3, iclass 5, count 2 2006.285.11:08:04.47#ibcon#read 3, iclass 5, count 2 2006.285.11:08:04.47#ibcon#about to read 4, iclass 5, count 2 2006.285.11:08:04.47#ibcon#read 4, iclass 5, count 2 2006.285.11:08:04.47#ibcon#about to read 5, iclass 5, count 2 2006.285.11:08:04.47#ibcon#read 5, iclass 5, count 2 2006.285.11:08:04.47#ibcon#about to read 6, iclass 5, count 2 2006.285.11:08:04.47#ibcon#read 6, iclass 5, count 2 2006.285.11:08:04.47#ibcon#end of sib2, iclass 5, count 2 2006.285.11:08:04.47#ibcon#*after write, iclass 5, count 2 2006.285.11:08:04.47#ibcon#*before return 0, iclass 5, count 2 2006.285.11:08:04.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:08:04.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:08:04.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.11:08:04.47#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:04.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:08:04.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:08:04.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:08:04.59#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:08:04.59#ibcon#first serial, iclass 5, count 0 2006.285.11:08:04.59#ibcon#enter sib2, iclass 5, count 0 2006.285.11:08:04.59#ibcon#flushed, iclass 5, count 0 2006.285.11:08:04.59#ibcon#about to write, iclass 5, count 0 2006.285.11:08:04.59#ibcon#wrote, iclass 5, count 0 2006.285.11:08:04.59#ibcon#about to read 3, iclass 5, count 0 2006.285.11:08:04.61#ibcon#read 3, iclass 5, count 0 2006.285.11:08:04.61#ibcon#about to read 4, iclass 5, count 0 2006.285.11:08:04.61#ibcon#read 4, iclass 5, count 0 2006.285.11:08:04.61#ibcon#about to read 5, iclass 5, count 0 2006.285.11:08:04.61#ibcon#read 5, iclass 5, count 0 2006.285.11:08:04.61#ibcon#about to read 6, iclass 5, count 0 2006.285.11:08:04.61#ibcon#read 6, iclass 5, count 0 2006.285.11:08:04.61#ibcon#end of sib2, iclass 5, count 0 2006.285.11:08:04.61#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:08:04.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:08:04.61#ibcon#[25=USB\r\n] 2006.285.11:08:04.61#ibcon#*before write, iclass 5, count 0 2006.285.11:08:04.61#ibcon#enter sib2, iclass 5, count 0 2006.285.11:08:04.61#ibcon#flushed, iclass 5, count 0 2006.285.11:08:04.61#ibcon#about to write, iclass 5, count 0 2006.285.11:08:04.61#ibcon#wrote, iclass 5, count 0 2006.285.11:08:04.61#ibcon#about to read 3, iclass 5, count 0 2006.285.11:08:04.64#ibcon#read 3, iclass 5, count 0 2006.285.11:08:04.64#ibcon#about to read 4, iclass 5, count 0 2006.285.11:08:04.64#ibcon#read 4, iclass 5, count 0 2006.285.11:08:04.64#ibcon#about to read 5, iclass 5, count 0 2006.285.11:08:04.64#ibcon#read 5, iclass 5, count 0 2006.285.11:08:04.64#ibcon#about to read 6, iclass 5, count 0 2006.285.11:08:04.64#ibcon#read 6, iclass 5, count 0 2006.285.11:08:04.64#ibcon#end of sib2, iclass 5, count 0 2006.285.11:08:04.64#ibcon#*after write, iclass 5, count 0 2006.285.11:08:04.64#ibcon#*before return 0, iclass 5, count 0 2006.285.11:08:04.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:08:04.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:08:04.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:08:04.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:08:04.64$vck44/valo=7,864.99 2006.285.11:08:04.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.11:08:04.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.11:08:04.64#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:04.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:08:04.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:08:04.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:08:04.64#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:08:04.64#ibcon#first serial, iclass 7, count 0 2006.285.11:08:04.64#ibcon#enter sib2, iclass 7, count 0 2006.285.11:08:04.64#ibcon#flushed, iclass 7, count 0 2006.285.11:08:04.64#ibcon#about to write, iclass 7, count 0 2006.285.11:08:04.64#ibcon#wrote, iclass 7, count 0 2006.285.11:08:04.64#ibcon#about to read 3, iclass 7, count 0 2006.285.11:08:04.66#ibcon#read 3, iclass 7, count 0 2006.285.11:08:04.66#ibcon#about to read 4, iclass 7, count 0 2006.285.11:08:04.66#ibcon#read 4, iclass 7, count 0 2006.285.11:08:04.66#ibcon#about to read 5, iclass 7, count 0 2006.285.11:08:04.66#ibcon#read 5, iclass 7, count 0 2006.285.11:08:04.66#ibcon#about to read 6, iclass 7, count 0 2006.285.11:08:04.66#ibcon#read 6, iclass 7, count 0 2006.285.11:08:04.66#ibcon#end of sib2, iclass 7, count 0 2006.285.11:08:04.66#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:08:04.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:08:04.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:08:04.66#ibcon#*before write, iclass 7, count 0 2006.285.11:08:04.66#ibcon#enter sib2, iclass 7, count 0 2006.285.11:08:04.66#ibcon#flushed, iclass 7, count 0 2006.285.11:08:04.66#ibcon#about to write, iclass 7, count 0 2006.285.11:08:04.66#ibcon#wrote, iclass 7, count 0 2006.285.11:08:04.66#ibcon#about to read 3, iclass 7, count 0 2006.285.11:08:04.70#ibcon#read 3, iclass 7, count 0 2006.285.11:08:04.70#ibcon#about to read 4, iclass 7, count 0 2006.285.11:08:04.70#ibcon#read 4, iclass 7, count 0 2006.285.11:08:04.70#ibcon#about to read 5, iclass 7, count 0 2006.285.11:08:04.70#ibcon#read 5, iclass 7, count 0 2006.285.11:08:04.70#ibcon#about to read 6, iclass 7, count 0 2006.285.11:08:04.70#ibcon#read 6, iclass 7, count 0 2006.285.11:08:04.70#ibcon#end of sib2, iclass 7, count 0 2006.285.11:08:04.70#ibcon#*after write, iclass 7, count 0 2006.285.11:08:04.70#ibcon#*before return 0, iclass 7, count 0 2006.285.11:08:04.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:08:04.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:08:04.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:08:04.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:08:04.70$vck44/va=7,4 2006.285.11:08:04.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.11:08:04.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.11:08:04.70#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:04.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:08:04.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:08:04.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:08:04.76#ibcon#enter wrdev, iclass 11, count 2 2006.285.11:08:04.76#ibcon#first serial, iclass 11, count 2 2006.285.11:08:04.76#ibcon#enter sib2, iclass 11, count 2 2006.285.11:08:04.76#ibcon#flushed, iclass 11, count 2 2006.285.11:08:04.76#ibcon#about to write, iclass 11, count 2 2006.285.11:08:04.76#ibcon#wrote, iclass 11, count 2 2006.285.11:08:04.76#ibcon#about to read 3, iclass 11, count 2 2006.285.11:08:04.78#ibcon#read 3, iclass 11, count 2 2006.285.11:08:04.78#ibcon#about to read 4, iclass 11, count 2 2006.285.11:08:04.78#ibcon#read 4, iclass 11, count 2 2006.285.11:08:04.78#ibcon#about to read 5, iclass 11, count 2 2006.285.11:08:04.78#ibcon#read 5, iclass 11, count 2 2006.285.11:08:04.78#ibcon#about to read 6, iclass 11, count 2 2006.285.11:08:04.78#ibcon#read 6, iclass 11, count 2 2006.285.11:08:04.78#ibcon#end of sib2, iclass 11, count 2 2006.285.11:08:04.78#ibcon#*mode == 0, iclass 11, count 2 2006.285.11:08:04.78#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.11:08:04.78#ibcon#[25=AT07-04\r\n] 2006.285.11:08:04.78#ibcon#*before write, iclass 11, count 2 2006.285.11:08:04.78#ibcon#enter sib2, iclass 11, count 2 2006.285.11:08:04.78#ibcon#flushed, iclass 11, count 2 2006.285.11:08:04.78#ibcon#about to write, iclass 11, count 2 2006.285.11:08:04.78#ibcon#wrote, iclass 11, count 2 2006.285.11:08:04.78#ibcon#about to read 3, iclass 11, count 2 2006.285.11:08:04.81#ibcon#read 3, iclass 11, count 2 2006.285.11:08:04.81#ibcon#about to read 4, iclass 11, count 2 2006.285.11:08:04.81#ibcon#read 4, iclass 11, count 2 2006.285.11:08:04.81#ibcon#about to read 5, iclass 11, count 2 2006.285.11:08:04.81#ibcon#read 5, iclass 11, count 2 2006.285.11:08:04.81#ibcon#about to read 6, iclass 11, count 2 2006.285.11:08:04.81#ibcon#read 6, iclass 11, count 2 2006.285.11:08:04.81#ibcon#end of sib2, iclass 11, count 2 2006.285.11:08:04.81#ibcon#*after write, iclass 11, count 2 2006.285.11:08:04.81#ibcon#*before return 0, iclass 11, count 2 2006.285.11:08:04.81#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:08:04.81#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:08:04.81#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.11:08:04.81#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:04.81#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:08:04.93#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:08:04.93#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:08:04.93#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:08:04.93#ibcon#first serial, iclass 11, count 0 2006.285.11:08:04.93#ibcon#enter sib2, iclass 11, count 0 2006.285.11:08:04.93#ibcon#flushed, iclass 11, count 0 2006.285.11:08:04.93#ibcon#about to write, iclass 11, count 0 2006.285.11:08:04.93#ibcon#wrote, iclass 11, count 0 2006.285.11:08:04.93#ibcon#about to read 3, iclass 11, count 0 2006.285.11:08:04.95#ibcon#read 3, iclass 11, count 0 2006.285.11:08:04.95#ibcon#about to read 4, iclass 11, count 0 2006.285.11:08:04.95#ibcon#read 4, iclass 11, count 0 2006.285.11:08:04.95#ibcon#about to read 5, iclass 11, count 0 2006.285.11:08:04.95#ibcon#read 5, iclass 11, count 0 2006.285.11:08:04.95#ibcon#about to read 6, iclass 11, count 0 2006.285.11:08:04.95#ibcon#read 6, iclass 11, count 0 2006.285.11:08:04.95#ibcon#end of sib2, iclass 11, count 0 2006.285.11:08:04.95#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:08:04.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:08:04.95#ibcon#[25=USB\r\n] 2006.285.11:08:04.95#ibcon#*before write, iclass 11, count 0 2006.285.11:08:04.95#ibcon#enter sib2, iclass 11, count 0 2006.285.11:08:04.95#ibcon#flushed, iclass 11, count 0 2006.285.11:08:04.95#ibcon#about to write, iclass 11, count 0 2006.285.11:08:04.95#ibcon#wrote, iclass 11, count 0 2006.285.11:08:04.95#ibcon#about to read 3, iclass 11, count 0 2006.285.11:08:04.98#ibcon#read 3, iclass 11, count 0 2006.285.11:08:04.98#ibcon#about to read 4, iclass 11, count 0 2006.285.11:08:04.98#ibcon#read 4, iclass 11, count 0 2006.285.11:08:04.98#ibcon#about to read 5, iclass 11, count 0 2006.285.11:08:04.98#ibcon#read 5, iclass 11, count 0 2006.285.11:08:04.98#ibcon#about to read 6, iclass 11, count 0 2006.285.11:08:04.98#ibcon#read 6, iclass 11, count 0 2006.285.11:08:04.98#ibcon#end of sib2, iclass 11, count 0 2006.285.11:08:04.98#ibcon#*after write, iclass 11, count 0 2006.285.11:08:04.98#ibcon#*before return 0, iclass 11, count 0 2006.285.11:08:04.98#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:08:04.98#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:08:04.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:08:04.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:08:04.98$vck44/valo=8,884.99 2006.285.11:08:04.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.11:08:04.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.11:08:04.98#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:04.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:08:04.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:08:04.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:08:04.98#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:08:04.98#ibcon#first serial, iclass 13, count 0 2006.285.11:08:04.98#ibcon#enter sib2, iclass 13, count 0 2006.285.11:08:04.98#ibcon#flushed, iclass 13, count 0 2006.285.11:08:04.98#ibcon#about to write, iclass 13, count 0 2006.285.11:08:04.98#ibcon#wrote, iclass 13, count 0 2006.285.11:08:04.98#ibcon#about to read 3, iclass 13, count 0 2006.285.11:08:05.00#ibcon#read 3, iclass 13, count 0 2006.285.11:08:05.00#ibcon#about to read 4, iclass 13, count 0 2006.285.11:08:05.00#ibcon#read 4, iclass 13, count 0 2006.285.11:08:05.00#ibcon#about to read 5, iclass 13, count 0 2006.285.11:08:05.00#ibcon#read 5, iclass 13, count 0 2006.285.11:08:05.00#ibcon#about to read 6, iclass 13, count 0 2006.285.11:08:05.00#ibcon#read 6, iclass 13, count 0 2006.285.11:08:05.00#ibcon#end of sib2, iclass 13, count 0 2006.285.11:08:05.00#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:08:05.00#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:08:05.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:08:05.00#ibcon#*before write, iclass 13, count 0 2006.285.11:08:05.00#ibcon#enter sib2, iclass 13, count 0 2006.285.11:08:05.00#ibcon#flushed, iclass 13, count 0 2006.285.11:08:05.00#ibcon#about to write, iclass 13, count 0 2006.285.11:08:05.00#ibcon#wrote, iclass 13, count 0 2006.285.11:08:05.00#ibcon#about to read 3, iclass 13, count 0 2006.285.11:08:05.04#ibcon#read 3, iclass 13, count 0 2006.285.11:08:05.04#ibcon#about to read 4, iclass 13, count 0 2006.285.11:08:05.04#ibcon#read 4, iclass 13, count 0 2006.285.11:08:05.04#ibcon#about to read 5, iclass 13, count 0 2006.285.11:08:05.04#ibcon#read 5, iclass 13, count 0 2006.285.11:08:05.04#ibcon#about to read 6, iclass 13, count 0 2006.285.11:08:05.04#ibcon#read 6, iclass 13, count 0 2006.285.11:08:05.04#ibcon#end of sib2, iclass 13, count 0 2006.285.11:08:05.04#ibcon#*after write, iclass 13, count 0 2006.285.11:08:05.04#ibcon#*before return 0, iclass 13, count 0 2006.285.11:08:05.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:08:05.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:08:05.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:08:05.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:08:05.04$vck44/va=8,3 2006.285.11:08:05.04#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.11:08:05.04#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.11:08:05.04#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:05.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:08:05.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:08:05.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:08:05.10#ibcon#enter wrdev, iclass 15, count 2 2006.285.11:08:05.10#ibcon#first serial, iclass 15, count 2 2006.285.11:08:05.10#ibcon#enter sib2, iclass 15, count 2 2006.285.11:08:05.10#ibcon#flushed, iclass 15, count 2 2006.285.11:08:05.10#ibcon#about to write, iclass 15, count 2 2006.285.11:08:05.10#ibcon#wrote, iclass 15, count 2 2006.285.11:08:05.10#ibcon#about to read 3, iclass 15, count 2 2006.285.11:08:05.12#ibcon#read 3, iclass 15, count 2 2006.285.11:08:05.12#ibcon#about to read 4, iclass 15, count 2 2006.285.11:08:05.12#ibcon#read 4, iclass 15, count 2 2006.285.11:08:05.12#ibcon#about to read 5, iclass 15, count 2 2006.285.11:08:05.12#ibcon#read 5, iclass 15, count 2 2006.285.11:08:05.12#ibcon#about to read 6, iclass 15, count 2 2006.285.11:08:05.12#ibcon#read 6, iclass 15, count 2 2006.285.11:08:05.12#ibcon#end of sib2, iclass 15, count 2 2006.285.11:08:05.12#ibcon#*mode == 0, iclass 15, count 2 2006.285.11:08:05.12#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.11:08:05.12#ibcon#[25=AT08-03\r\n] 2006.285.11:08:05.12#ibcon#*before write, iclass 15, count 2 2006.285.11:08:05.12#ibcon#enter sib2, iclass 15, count 2 2006.285.11:08:05.12#ibcon#flushed, iclass 15, count 2 2006.285.11:08:05.12#ibcon#about to write, iclass 15, count 2 2006.285.11:08:05.12#ibcon#wrote, iclass 15, count 2 2006.285.11:08:05.12#ibcon#about to read 3, iclass 15, count 2 2006.285.11:08:05.15#ibcon#read 3, iclass 15, count 2 2006.285.11:08:05.15#ibcon#about to read 4, iclass 15, count 2 2006.285.11:08:05.15#ibcon#read 4, iclass 15, count 2 2006.285.11:08:05.15#ibcon#about to read 5, iclass 15, count 2 2006.285.11:08:05.15#ibcon#read 5, iclass 15, count 2 2006.285.11:08:05.15#ibcon#about to read 6, iclass 15, count 2 2006.285.11:08:05.15#ibcon#read 6, iclass 15, count 2 2006.285.11:08:05.15#ibcon#end of sib2, iclass 15, count 2 2006.285.11:08:05.15#ibcon#*after write, iclass 15, count 2 2006.285.11:08:05.15#ibcon#*before return 0, iclass 15, count 2 2006.285.11:08:05.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:08:05.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:08:05.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.11:08:05.15#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:05.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:08:05.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:08:05.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:08:05.27#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:08:05.27#ibcon#first serial, iclass 15, count 0 2006.285.11:08:05.27#ibcon#enter sib2, iclass 15, count 0 2006.285.11:08:05.27#ibcon#flushed, iclass 15, count 0 2006.285.11:08:05.27#ibcon#about to write, iclass 15, count 0 2006.285.11:08:05.27#ibcon#wrote, iclass 15, count 0 2006.285.11:08:05.27#ibcon#about to read 3, iclass 15, count 0 2006.285.11:08:05.29#ibcon#read 3, iclass 15, count 0 2006.285.11:08:05.29#ibcon#about to read 4, iclass 15, count 0 2006.285.11:08:05.29#ibcon#read 4, iclass 15, count 0 2006.285.11:08:05.29#ibcon#about to read 5, iclass 15, count 0 2006.285.11:08:05.29#ibcon#read 5, iclass 15, count 0 2006.285.11:08:05.29#ibcon#about to read 6, iclass 15, count 0 2006.285.11:08:05.29#ibcon#read 6, iclass 15, count 0 2006.285.11:08:05.29#ibcon#end of sib2, iclass 15, count 0 2006.285.11:08:05.29#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:08:05.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:08:05.29#ibcon#[25=USB\r\n] 2006.285.11:08:05.29#ibcon#*before write, iclass 15, count 0 2006.285.11:08:05.29#ibcon#enter sib2, iclass 15, count 0 2006.285.11:08:05.29#ibcon#flushed, iclass 15, count 0 2006.285.11:08:05.29#ibcon#about to write, iclass 15, count 0 2006.285.11:08:05.29#ibcon#wrote, iclass 15, count 0 2006.285.11:08:05.29#ibcon#about to read 3, iclass 15, count 0 2006.285.11:08:05.32#ibcon#read 3, iclass 15, count 0 2006.285.11:08:05.32#ibcon#about to read 4, iclass 15, count 0 2006.285.11:08:05.32#ibcon#read 4, iclass 15, count 0 2006.285.11:08:05.32#ibcon#about to read 5, iclass 15, count 0 2006.285.11:08:05.32#ibcon#read 5, iclass 15, count 0 2006.285.11:08:05.32#ibcon#about to read 6, iclass 15, count 0 2006.285.11:08:05.32#ibcon#read 6, iclass 15, count 0 2006.285.11:08:05.32#ibcon#end of sib2, iclass 15, count 0 2006.285.11:08:05.32#ibcon#*after write, iclass 15, count 0 2006.285.11:08:05.32#ibcon#*before return 0, iclass 15, count 0 2006.285.11:08:05.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:08:05.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:08:05.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:08:05.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:08:05.32$vck44/vblo=1,629.99 2006.285.11:08:05.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.11:08:05.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.11:08:05.32#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:05.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:08:05.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:08:05.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:08:05.32#ibcon#enter wrdev, iclass 17, count 0 2006.285.11:08:05.32#ibcon#first serial, iclass 17, count 0 2006.285.11:08:05.32#ibcon#enter sib2, iclass 17, count 0 2006.285.11:08:05.32#ibcon#flushed, iclass 17, count 0 2006.285.11:08:05.32#ibcon#about to write, iclass 17, count 0 2006.285.11:08:05.32#ibcon#wrote, iclass 17, count 0 2006.285.11:08:05.32#ibcon#about to read 3, iclass 17, count 0 2006.285.11:08:05.34#ibcon#read 3, iclass 17, count 0 2006.285.11:08:05.34#ibcon#about to read 4, iclass 17, count 0 2006.285.11:08:05.34#ibcon#read 4, iclass 17, count 0 2006.285.11:08:05.34#ibcon#about to read 5, iclass 17, count 0 2006.285.11:08:05.34#ibcon#read 5, iclass 17, count 0 2006.285.11:08:05.34#ibcon#about to read 6, iclass 17, count 0 2006.285.11:08:05.34#ibcon#read 6, iclass 17, count 0 2006.285.11:08:05.34#ibcon#end of sib2, iclass 17, count 0 2006.285.11:08:05.34#ibcon#*mode == 0, iclass 17, count 0 2006.285.11:08:05.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.11:08:05.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:08:05.34#ibcon#*before write, iclass 17, count 0 2006.285.11:08:05.34#ibcon#enter sib2, iclass 17, count 0 2006.285.11:08:05.34#ibcon#flushed, iclass 17, count 0 2006.285.11:08:05.34#ibcon#about to write, iclass 17, count 0 2006.285.11:08:05.34#ibcon#wrote, iclass 17, count 0 2006.285.11:08:05.34#ibcon#about to read 3, iclass 17, count 0 2006.285.11:08:05.38#ibcon#read 3, iclass 17, count 0 2006.285.11:08:05.38#ibcon#about to read 4, iclass 17, count 0 2006.285.11:08:05.38#ibcon#read 4, iclass 17, count 0 2006.285.11:08:05.38#ibcon#about to read 5, iclass 17, count 0 2006.285.11:08:05.38#ibcon#read 5, iclass 17, count 0 2006.285.11:08:05.38#ibcon#about to read 6, iclass 17, count 0 2006.285.11:08:05.38#ibcon#read 6, iclass 17, count 0 2006.285.11:08:05.38#ibcon#end of sib2, iclass 17, count 0 2006.285.11:08:05.38#ibcon#*after write, iclass 17, count 0 2006.285.11:08:05.38#ibcon#*before return 0, iclass 17, count 0 2006.285.11:08:05.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:08:05.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:08:05.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.11:08:05.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.11:08:05.38$vck44/vb=1,4 2006.285.11:08:05.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.11:08:05.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.11:08:05.38#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:05.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:08:05.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:08:05.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:08:05.38#ibcon#enter wrdev, iclass 19, count 2 2006.285.11:08:05.38#ibcon#first serial, iclass 19, count 2 2006.285.11:08:05.38#ibcon#enter sib2, iclass 19, count 2 2006.285.11:08:05.38#ibcon#flushed, iclass 19, count 2 2006.285.11:08:05.38#ibcon#about to write, iclass 19, count 2 2006.285.11:08:05.38#ibcon#wrote, iclass 19, count 2 2006.285.11:08:05.38#ibcon#about to read 3, iclass 19, count 2 2006.285.11:08:05.40#ibcon#read 3, iclass 19, count 2 2006.285.11:08:05.40#ibcon#about to read 4, iclass 19, count 2 2006.285.11:08:05.40#ibcon#read 4, iclass 19, count 2 2006.285.11:08:05.40#ibcon#about to read 5, iclass 19, count 2 2006.285.11:08:05.40#ibcon#read 5, iclass 19, count 2 2006.285.11:08:05.40#ibcon#about to read 6, iclass 19, count 2 2006.285.11:08:05.40#ibcon#read 6, iclass 19, count 2 2006.285.11:08:05.40#ibcon#end of sib2, iclass 19, count 2 2006.285.11:08:05.40#ibcon#*mode == 0, iclass 19, count 2 2006.285.11:08:05.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.11:08:05.40#ibcon#[27=AT01-04\r\n] 2006.285.11:08:05.40#ibcon#*before write, iclass 19, count 2 2006.285.11:08:05.40#ibcon#enter sib2, iclass 19, count 2 2006.285.11:08:05.40#ibcon#flushed, iclass 19, count 2 2006.285.11:08:05.40#ibcon#about to write, iclass 19, count 2 2006.285.11:08:05.40#ibcon#wrote, iclass 19, count 2 2006.285.11:08:05.40#ibcon#about to read 3, iclass 19, count 2 2006.285.11:08:05.43#ibcon#read 3, iclass 19, count 2 2006.285.11:08:05.43#ibcon#about to read 4, iclass 19, count 2 2006.285.11:08:05.43#ibcon#read 4, iclass 19, count 2 2006.285.11:08:05.43#ibcon#about to read 5, iclass 19, count 2 2006.285.11:08:05.43#ibcon#read 5, iclass 19, count 2 2006.285.11:08:05.43#ibcon#about to read 6, iclass 19, count 2 2006.285.11:08:05.43#ibcon#read 6, iclass 19, count 2 2006.285.11:08:05.43#ibcon#end of sib2, iclass 19, count 2 2006.285.11:08:05.43#ibcon#*after write, iclass 19, count 2 2006.285.11:08:05.43#ibcon#*before return 0, iclass 19, count 2 2006.285.11:08:05.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:08:05.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:08:05.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.11:08:05.43#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:05.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:08:05.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:08:05.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:08:05.55#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:08:05.55#ibcon#first serial, iclass 19, count 0 2006.285.11:08:05.55#ibcon#enter sib2, iclass 19, count 0 2006.285.11:08:05.55#ibcon#flushed, iclass 19, count 0 2006.285.11:08:05.55#ibcon#about to write, iclass 19, count 0 2006.285.11:08:05.55#ibcon#wrote, iclass 19, count 0 2006.285.11:08:05.55#ibcon#about to read 3, iclass 19, count 0 2006.285.11:08:05.57#ibcon#read 3, iclass 19, count 0 2006.285.11:08:05.57#ibcon#about to read 4, iclass 19, count 0 2006.285.11:08:05.57#ibcon#read 4, iclass 19, count 0 2006.285.11:08:05.57#ibcon#about to read 5, iclass 19, count 0 2006.285.11:08:05.57#ibcon#read 5, iclass 19, count 0 2006.285.11:08:05.57#ibcon#about to read 6, iclass 19, count 0 2006.285.11:08:05.57#ibcon#read 6, iclass 19, count 0 2006.285.11:08:05.57#ibcon#end of sib2, iclass 19, count 0 2006.285.11:08:05.57#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:08:05.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:08:05.57#ibcon#[27=USB\r\n] 2006.285.11:08:05.57#ibcon#*before write, iclass 19, count 0 2006.285.11:08:05.57#ibcon#enter sib2, iclass 19, count 0 2006.285.11:08:05.57#ibcon#flushed, iclass 19, count 0 2006.285.11:08:05.57#ibcon#about to write, iclass 19, count 0 2006.285.11:08:05.57#ibcon#wrote, iclass 19, count 0 2006.285.11:08:05.57#ibcon#about to read 3, iclass 19, count 0 2006.285.11:08:05.60#ibcon#read 3, iclass 19, count 0 2006.285.11:08:05.60#ibcon#about to read 4, iclass 19, count 0 2006.285.11:08:05.60#ibcon#read 4, iclass 19, count 0 2006.285.11:08:05.60#ibcon#about to read 5, iclass 19, count 0 2006.285.11:08:05.60#ibcon#read 5, iclass 19, count 0 2006.285.11:08:05.60#ibcon#about to read 6, iclass 19, count 0 2006.285.11:08:05.60#ibcon#read 6, iclass 19, count 0 2006.285.11:08:05.60#ibcon#end of sib2, iclass 19, count 0 2006.285.11:08:05.60#ibcon#*after write, iclass 19, count 0 2006.285.11:08:05.60#ibcon#*before return 0, iclass 19, count 0 2006.285.11:08:05.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:08:05.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:08:05.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:08:05.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:08:05.60$vck44/vblo=2,634.99 2006.285.11:08:05.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.11:08:05.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.11:08:05.60#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:05.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:08:05.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:08:05.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:08:05.60#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:08:05.60#ibcon#first serial, iclass 21, count 0 2006.285.11:08:05.60#ibcon#enter sib2, iclass 21, count 0 2006.285.11:08:05.60#ibcon#flushed, iclass 21, count 0 2006.285.11:08:05.60#ibcon#about to write, iclass 21, count 0 2006.285.11:08:05.60#ibcon#wrote, iclass 21, count 0 2006.285.11:08:05.60#ibcon#about to read 3, iclass 21, count 0 2006.285.11:08:05.62#ibcon#read 3, iclass 21, count 0 2006.285.11:08:05.62#ibcon#about to read 4, iclass 21, count 0 2006.285.11:08:05.62#ibcon#read 4, iclass 21, count 0 2006.285.11:08:05.62#ibcon#about to read 5, iclass 21, count 0 2006.285.11:08:05.62#ibcon#read 5, iclass 21, count 0 2006.285.11:08:05.62#ibcon#about to read 6, iclass 21, count 0 2006.285.11:08:05.62#ibcon#read 6, iclass 21, count 0 2006.285.11:08:05.62#ibcon#end of sib2, iclass 21, count 0 2006.285.11:08:05.62#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:08:05.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:08:05.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:08:05.62#ibcon#*before write, iclass 21, count 0 2006.285.11:08:05.62#ibcon#enter sib2, iclass 21, count 0 2006.285.11:08:05.62#ibcon#flushed, iclass 21, count 0 2006.285.11:08:05.62#ibcon#about to write, iclass 21, count 0 2006.285.11:08:05.62#ibcon#wrote, iclass 21, count 0 2006.285.11:08:05.62#ibcon#about to read 3, iclass 21, count 0 2006.285.11:08:05.66#ibcon#read 3, iclass 21, count 0 2006.285.11:08:05.66#ibcon#about to read 4, iclass 21, count 0 2006.285.11:08:05.66#ibcon#read 4, iclass 21, count 0 2006.285.11:08:05.66#ibcon#about to read 5, iclass 21, count 0 2006.285.11:08:05.66#ibcon#read 5, iclass 21, count 0 2006.285.11:08:05.66#ibcon#about to read 6, iclass 21, count 0 2006.285.11:08:05.66#ibcon#read 6, iclass 21, count 0 2006.285.11:08:05.66#ibcon#end of sib2, iclass 21, count 0 2006.285.11:08:05.66#ibcon#*after write, iclass 21, count 0 2006.285.11:08:05.66#ibcon#*before return 0, iclass 21, count 0 2006.285.11:08:05.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:08:05.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:08:05.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:08:05.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:08:05.66$vck44/vb=2,5 2006.285.11:08:05.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.11:08:05.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.11:08:05.66#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:05.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:08:05.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:08:05.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:08:05.72#ibcon#enter wrdev, iclass 23, count 2 2006.285.11:08:05.72#ibcon#first serial, iclass 23, count 2 2006.285.11:08:05.72#ibcon#enter sib2, iclass 23, count 2 2006.285.11:08:05.72#ibcon#flushed, iclass 23, count 2 2006.285.11:08:05.72#ibcon#about to write, iclass 23, count 2 2006.285.11:08:05.72#ibcon#wrote, iclass 23, count 2 2006.285.11:08:05.72#ibcon#about to read 3, iclass 23, count 2 2006.285.11:08:05.74#ibcon#read 3, iclass 23, count 2 2006.285.11:08:05.74#ibcon#about to read 4, iclass 23, count 2 2006.285.11:08:05.74#ibcon#read 4, iclass 23, count 2 2006.285.11:08:05.74#ibcon#about to read 5, iclass 23, count 2 2006.285.11:08:05.74#ibcon#read 5, iclass 23, count 2 2006.285.11:08:05.74#ibcon#about to read 6, iclass 23, count 2 2006.285.11:08:05.74#ibcon#read 6, iclass 23, count 2 2006.285.11:08:05.74#ibcon#end of sib2, iclass 23, count 2 2006.285.11:08:05.74#ibcon#*mode == 0, iclass 23, count 2 2006.285.11:08:05.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.11:08:05.74#ibcon#[27=AT02-05\r\n] 2006.285.11:08:05.74#ibcon#*before write, iclass 23, count 2 2006.285.11:08:05.74#ibcon#enter sib2, iclass 23, count 2 2006.285.11:08:05.74#ibcon#flushed, iclass 23, count 2 2006.285.11:08:05.74#ibcon#about to write, iclass 23, count 2 2006.285.11:08:05.74#ibcon#wrote, iclass 23, count 2 2006.285.11:08:05.74#ibcon#about to read 3, iclass 23, count 2 2006.285.11:08:05.77#ibcon#read 3, iclass 23, count 2 2006.285.11:08:05.77#ibcon#about to read 4, iclass 23, count 2 2006.285.11:08:05.77#ibcon#read 4, iclass 23, count 2 2006.285.11:08:05.77#ibcon#about to read 5, iclass 23, count 2 2006.285.11:08:05.77#ibcon#read 5, iclass 23, count 2 2006.285.11:08:05.77#ibcon#about to read 6, iclass 23, count 2 2006.285.11:08:05.77#ibcon#read 6, iclass 23, count 2 2006.285.11:08:05.77#ibcon#end of sib2, iclass 23, count 2 2006.285.11:08:05.77#ibcon#*after write, iclass 23, count 2 2006.285.11:08:05.77#ibcon#*before return 0, iclass 23, count 2 2006.285.11:08:05.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:08:05.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:08:05.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.11:08:05.77#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:05.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:08:05.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:08:05.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:08:05.89#ibcon#enter wrdev, iclass 23, count 0 2006.285.11:08:05.89#ibcon#first serial, iclass 23, count 0 2006.285.11:08:05.89#ibcon#enter sib2, iclass 23, count 0 2006.285.11:08:05.89#ibcon#flushed, iclass 23, count 0 2006.285.11:08:05.89#ibcon#about to write, iclass 23, count 0 2006.285.11:08:05.89#ibcon#wrote, iclass 23, count 0 2006.285.11:08:05.89#ibcon#about to read 3, iclass 23, count 0 2006.285.11:08:05.91#ibcon#read 3, iclass 23, count 0 2006.285.11:08:05.91#ibcon#about to read 4, iclass 23, count 0 2006.285.11:08:05.91#ibcon#read 4, iclass 23, count 0 2006.285.11:08:05.91#ibcon#about to read 5, iclass 23, count 0 2006.285.11:08:05.91#ibcon#read 5, iclass 23, count 0 2006.285.11:08:05.91#ibcon#about to read 6, iclass 23, count 0 2006.285.11:08:05.91#ibcon#read 6, iclass 23, count 0 2006.285.11:08:05.91#ibcon#end of sib2, iclass 23, count 0 2006.285.11:08:05.91#ibcon#*mode == 0, iclass 23, count 0 2006.285.11:08:05.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.11:08:05.91#ibcon#[27=USB\r\n] 2006.285.11:08:05.91#ibcon#*before write, iclass 23, count 0 2006.285.11:08:05.91#ibcon#enter sib2, iclass 23, count 0 2006.285.11:08:05.91#ibcon#flushed, iclass 23, count 0 2006.285.11:08:05.91#ibcon#about to write, iclass 23, count 0 2006.285.11:08:05.91#ibcon#wrote, iclass 23, count 0 2006.285.11:08:05.91#ibcon#about to read 3, iclass 23, count 0 2006.285.11:08:05.94#ibcon#read 3, iclass 23, count 0 2006.285.11:08:05.94#ibcon#about to read 4, iclass 23, count 0 2006.285.11:08:05.94#ibcon#read 4, iclass 23, count 0 2006.285.11:08:05.94#ibcon#about to read 5, iclass 23, count 0 2006.285.11:08:05.94#ibcon#read 5, iclass 23, count 0 2006.285.11:08:05.94#ibcon#about to read 6, iclass 23, count 0 2006.285.11:08:05.94#ibcon#read 6, iclass 23, count 0 2006.285.11:08:05.94#ibcon#end of sib2, iclass 23, count 0 2006.285.11:08:05.94#ibcon#*after write, iclass 23, count 0 2006.285.11:08:05.94#ibcon#*before return 0, iclass 23, count 0 2006.285.11:08:05.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:08:05.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:08:05.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.11:08:05.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.11:08:05.94$vck44/vblo=3,649.99 2006.285.11:08:05.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.11:08:05.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.11:08:05.94#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:05.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:08:05.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:08:05.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:08:05.94#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:08:05.94#ibcon#first serial, iclass 25, count 0 2006.285.11:08:05.94#ibcon#enter sib2, iclass 25, count 0 2006.285.11:08:05.94#ibcon#flushed, iclass 25, count 0 2006.285.11:08:05.94#ibcon#about to write, iclass 25, count 0 2006.285.11:08:05.94#ibcon#wrote, iclass 25, count 0 2006.285.11:08:05.94#ibcon#about to read 3, iclass 25, count 0 2006.285.11:08:05.96#ibcon#read 3, iclass 25, count 0 2006.285.11:08:05.96#ibcon#about to read 4, iclass 25, count 0 2006.285.11:08:05.96#ibcon#read 4, iclass 25, count 0 2006.285.11:08:05.96#ibcon#about to read 5, iclass 25, count 0 2006.285.11:08:05.96#ibcon#read 5, iclass 25, count 0 2006.285.11:08:05.96#ibcon#about to read 6, iclass 25, count 0 2006.285.11:08:05.96#ibcon#read 6, iclass 25, count 0 2006.285.11:08:05.96#ibcon#end of sib2, iclass 25, count 0 2006.285.11:08:05.96#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:08:05.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:08:05.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:08:05.96#ibcon#*before write, iclass 25, count 0 2006.285.11:08:05.96#ibcon#enter sib2, iclass 25, count 0 2006.285.11:08:05.96#ibcon#flushed, iclass 25, count 0 2006.285.11:08:05.96#ibcon#about to write, iclass 25, count 0 2006.285.11:08:05.96#ibcon#wrote, iclass 25, count 0 2006.285.11:08:05.96#ibcon#about to read 3, iclass 25, count 0 2006.285.11:08:06.00#ibcon#read 3, iclass 25, count 0 2006.285.11:08:06.00#ibcon#about to read 4, iclass 25, count 0 2006.285.11:08:06.00#ibcon#read 4, iclass 25, count 0 2006.285.11:08:06.00#ibcon#about to read 5, iclass 25, count 0 2006.285.11:08:06.00#ibcon#read 5, iclass 25, count 0 2006.285.11:08:06.00#ibcon#about to read 6, iclass 25, count 0 2006.285.11:08:06.00#ibcon#read 6, iclass 25, count 0 2006.285.11:08:06.00#ibcon#end of sib2, iclass 25, count 0 2006.285.11:08:06.00#ibcon#*after write, iclass 25, count 0 2006.285.11:08:06.00#ibcon#*before return 0, iclass 25, count 0 2006.285.11:08:06.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:08:06.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:08:06.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:08:06.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:08:06.00$vck44/vb=3,4 2006.285.11:08:06.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.11:08:06.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.11:08:06.00#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:06.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:08:06.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:08:06.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:08:06.06#ibcon#enter wrdev, iclass 27, count 2 2006.285.11:08:06.06#ibcon#first serial, iclass 27, count 2 2006.285.11:08:06.06#ibcon#enter sib2, iclass 27, count 2 2006.285.11:08:06.06#ibcon#flushed, iclass 27, count 2 2006.285.11:08:06.06#ibcon#about to write, iclass 27, count 2 2006.285.11:08:06.06#ibcon#wrote, iclass 27, count 2 2006.285.11:08:06.06#ibcon#about to read 3, iclass 27, count 2 2006.285.11:08:06.08#ibcon#read 3, iclass 27, count 2 2006.285.11:08:06.08#ibcon#about to read 4, iclass 27, count 2 2006.285.11:08:06.08#ibcon#read 4, iclass 27, count 2 2006.285.11:08:06.08#ibcon#about to read 5, iclass 27, count 2 2006.285.11:08:06.08#ibcon#read 5, iclass 27, count 2 2006.285.11:08:06.08#ibcon#about to read 6, iclass 27, count 2 2006.285.11:08:06.08#ibcon#read 6, iclass 27, count 2 2006.285.11:08:06.08#ibcon#end of sib2, iclass 27, count 2 2006.285.11:08:06.08#ibcon#*mode == 0, iclass 27, count 2 2006.285.11:08:06.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.11:08:06.08#ibcon#[27=AT03-04\r\n] 2006.285.11:08:06.08#ibcon#*before write, iclass 27, count 2 2006.285.11:08:06.08#ibcon#enter sib2, iclass 27, count 2 2006.285.11:08:06.08#ibcon#flushed, iclass 27, count 2 2006.285.11:08:06.08#ibcon#about to write, iclass 27, count 2 2006.285.11:08:06.08#ibcon#wrote, iclass 27, count 2 2006.285.11:08:06.08#ibcon#about to read 3, iclass 27, count 2 2006.285.11:08:06.11#ibcon#read 3, iclass 27, count 2 2006.285.11:08:06.11#ibcon#about to read 4, iclass 27, count 2 2006.285.11:08:06.11#ibcon#read 4, iclass 27, count 2 2006.285.11:08:06.11#ibcon#about to read 5, iclass 27, count 2 2006.285.11:08:06.11#ibcon#read 5, iclass 27, count 2 2006.285.11:08:06.11#ibcon#about to read 6, iclass 27, count 2 2006.285.11:08:06.11#ibcon#read 6, iclass 27, count 2 2006.285.11:08:06.11#ibcon#end of sib2, iclass 27, count 2 2006.285.11:08:06.11#ibcon#*after write, iclass 27, count 2 2006.285.11:08:06.11#ibcon#*before return 0, iclass 27, count 2 2006.285.11:08:06.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:08:06.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:08:06.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.11:08:06.11#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:06.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:08:06.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:08:06.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:08:06.23#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:08:06.23#ibcon#first serial, iclass 27, count 0 2006.285.11:08:06.23#ibcon#enter sib2, iclass 27, count 0 2006.285.11:08:06.23#ibcon#flushed, iclass 27, count 0 2006.285.11:08:06.23#ibcon#about to write, iclass 27, count 0 2006.285.11:08:06.23#ibcon#wrote, iclass 27, count 0 2006.285.11:08:06.23#ibcon#about to read 3, iclass 27, count 0 2006.285.11:08:06.25#ibcon#read 3, iclass 27, count 0 2006.285.11:08:06.25#ibcon#about to read 4, iclass 27, count 0 2006.285.11:08:06.25#ibcon#read 4, iclass 27, count 0 2006.285.11:08:06.25#ibcon#about to read 5, iclass 27, count 0 2006.285.11:08:06.25#ibcon#read 5, iclass 27, count 0 2006.285.11:08:06.25#ibcon#about to read 6, iclass 27, count 0 2006.285.11:08:06.25#ibcon#read 6, iclass 27, count 0 2006.285.11:08:06.25#ibcon#end of sib2, iclass 27, count 0 2006.285.11:08:06.25#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:08:06.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:08:06.25#ibcon#[27=USB\r\n] 2006.285.11:08:06.25#ibcon#*before write, iclass 27, count 0 2006.285.11:08:06.25#ibcon#enter sib2, iclass 27, count 0 2006.285.11:08:06.25#ibcon#flushed, iclass 27, count 0 2006.285.11:08:06.25#ibcon#about to write, iclass 27, count 0 2006.285.11:08:06.25#ibcon#wrote, iclass 27, count 0 2006.285.11:08:06.25#ibcon#about to read 3, iclass 27, count 0 2006.285.11:08:06.28#ibcon#read 3, iclass 27, count 0 2006.285.11:08:06.28#ibcon#about to read 4, iclass 27, count 0 2006.285.11:08:06.28#ibcon#read 4, iclass 27, count 0 2006.285.11:08:06.28#ibcon#about to read 5, iclass 27, count 0 2006.285.11:08:06.28#ibcon#read 5, iclass 27, count 0 2006.285.11:08:06.28#ibcon#about to read 6, iclass 27, count 0 2006.285.11:08:06.28#ibcon#read 6, iclass 27, count 0 2006.285.11:08:06.28#ibcon#end of sib2, iclass 27, count 0 2006.285.11:08:06.28#ibcon#*after write, iclass 27, count 0 2006.285.11:08:06.28#ibcon#*before return 0, iclass 27, count 0 2006.285.11:08:06.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:08:06.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:08:06.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:08:06.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:08:06.28$vck44/vblo=4,679.99 2006.285.11:08:06.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.11:08:06.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.11:08:06.28#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:06.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:08:06.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:08:06.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:08:06.28#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:08:06.28#ibcon#first serial, iclass 29, count 0 2006.285.11:08:06.28#ibcon#enter sib2, iclass 29, count 0 2006.285.11:08:06.28#ibcon#flushed, iclass 29, count 0 2006.285.11:08:06.28#ibcon#about to write, iclass 29, count 0 2006.285.11:08:06.28#ibcon#wrote, iclass 29, count 0 2006.285.11:08:06.28#ibcon#about to read 3, iclass 29, count 0 2006.285.11:08:06.30#ibcon#read 3, iclass 29, count 0 2006.285.11:08:06.30#ibcon#about to read 4, iclass 29, count 0 2006.285.11:08:06.30#ibcon#read 4, iclass 29, count 0 2006.285.11:08:06.30#ibcon#about to read 5, iclass 29, count 0 2006.285.11:08:06.30#ibcon#read 5, iclass 29, count 0 2006.285.11:08:06.30#ibcon#about to read 6, iclass 29, count 0 2006.285.11:08:06.30#ibcon#read 6, iclass 29, count 0 2006.285.11:08:06.30#ibcon#end of sib2, iclass 29, count 0 2006.285.11:08:06.30#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:08:06.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:08:06.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:08:06.30#ibcon#*before write, iclass 29, count 0 2006.285.11:08:06.30#ibcon#enter sib2, iclass 29, count 0 2006.285.11:08:06.30#ibcon#flushed, iclass 29, count 0 2006.285.11:08:06.30#ibcon#about to write, iclass 29, count 0 2006.285.11:08:06.30#ibcon#wrote, iclass 29, count 0 2006.285.11:08:06.30#ibcon#about to read 3, iclass 29, count 0 2006.285.11:08:06.34#ibcon#read 3, iclass 29, count 0 2006.285.11:08:06.34#ibcon#about to read 4, iclass 29, count 0 2006.285.11:08:06.34#ibcon#read 4, iclass 29, count 0 2006.285.11:08:06.34#ibcon#about to read 5, iclass 29, count 0 2006.285.11:08:06.34#ibcon#read 5, iclass 29, count 0 2006.285.11:08:06.34#ibcon#about to read 6, iclass 29, count 0 2006.285.11:08:06.34#ibcon#read 6, iclass 29, count 0 2006.285.11:08:06.34#ibcon#end of sib2, iclass 29, count 0 2006.285.11:08:06.34#ibcon#*after write, iclass 29, count 0 2006.285.11:08:06.34#ibcon#*before return 0, iclass 29, count 0 2006.285.11:08:06.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:08:06.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:08:06.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:08:06.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:08:06.34$vck44/vb=4,5 2006.285.11:08:06.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.11:08:06.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.11:08:06.34#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:06.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:08:06.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:08:06.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:08:06.40#ibcon#enter wrdev, iclass 31, count 2 2006.285.11:08:06.40#ibcon#first serial, iclass 31, count 2 2006.285.11:08:06.40#ibcon#enter sib2, iclass 31, count 2 2006.285.11:08:06.40#ibcon#flushed, iclass 31, count 2 2006.285.11:08:06.40#ibcon#about to write, iclass 31, count 2 2006.285.11:08:06.40#ibcon#wrote, iclass 31, count 2 2006.285.11:08:06.40#ibcon#about to read 3, iclass 31, count 2 2006.285.11:08:06.42#ibcon#read 3, iclass 31, count 2 2006.285.11:08:06.42#ibcon#about to read 4, iclass 31, count 2 2006.285.11:08:06.42#ibcon#read 4, iclass 31, count 2 2006.285.11:08:06.42#ibcon#about to read 5, iclass 31, count 2 2006.285.11:08:06.42#ibcon#read 5, iclass 31, count 2 2006.285.11:08:06.42#ibcon#about to read 6, iclass 31, count 2 2006.285.11:08:06.42#ibcon#read 6, iclass 31, count 2 2006.285.11:08:06.42#ibcon#end of sib2, iclass 31, count 2 2006.285.11:08:06.42#ibcon#*mode == 0, iclass 31, count 2 2006.285.11:08:06.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.11:08:06.42#ibcon#[27=AT04-05\r\n] 2006.285.11:08:06.42#ibcon#*before write, iclass 31, count 2 2006.285.11:08:06.42#ibcon#enter sib2, iclass 31, count 2 2006.285.11:08:06.42#ibcon#flushed, iclass 31, count 2 2006.285.11:08:06.42#ibcon#about to write, iclass 31, count 2 2006.285.11:08:06.42#ibcon#wrote, iclass 31, count 2 2006.285.11:08:06.42#ibcon#about to read 3, iclass 31, count 2 2006.285.11:08:06.45#ibcon#read 3, iclass 31, count 2 2006.285.11:08:06.45#ibcon#about to read 4, iclass 31, count 2 2006.285.11:08:06.45#ibcon#read 4, iclass 31, count 2 2006.285.11:08:06.45#ibcon#about to read 5, iclass 31, count 2 2006.285.11:08:06.45#ibcon#read 5, iclass 31, count 2 2006.285.11:08:06.45#ibcon#about to read 6, iclass 31, count 2 2006.285.11:08:06.45#ibcon#read 6, iclass 31, count 2 2006.285.11:08:06.45#ibcon#end of sib2, iclass 31, count 2 2006.285.11:08:06.45#ibcon#*after write, iclass 31, count 2 2006.285.11:08:06.45#ibcon#*before return 0, iclass 31, count 2 2006.285.11:08:06.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:08:06.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:08:06.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.11:08:06.45#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:06.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:08:06.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:08:06.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:08:06.57#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:08:06.57#ibcon#first serial, iclass 31, count 0 2006.285.11:08:06.57#ibcon#enter sib2, iclass 31, count 0 2006.285.11:08:06.57#ibcon#flushed, iclass 31, count 0 2006.285.11:08:06.57#ibcon#about to write, iclass 31, count 0 2006.285.11:08:06.57#ibcon#wrote, iclass 31, count 0 2006.285.11:08:06.57#ibcon#about to read 3, iclass 31, count 0 2006.285.11:08:06.59#ibcon#read 3, iclass 31, count 0 2006.285.11:08:06.59#ibcon#about to read 4, iclass 31, count 0 2006.285.11:08:06.59#ibcon#read 4, iclass 31, count 0 2006.285.11:08:06.59#ibcon#about to read 5, iclass 31, count 0 2006.285.11:08:06.59#ibcon#read 5, iclass 31, count 0 2006.285.11:08:06.59#ibcon#about to read 6, iclass 31, count 0 2006.285.11:08:06.59#ibcon#read 6, iclass 31, count 0 2006.285.11:08:06.59#ibcon#end of sib2, iclass 31, count 0 2006.285.11:08:06.59#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:08:06.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:08:06.59#ibcon#[27=USB\r\n] 2006.285.11:08:06.59#ibcon#*before write, iclass 31, count 0 2006.285.11:08:06.59#ibcon#enter sib2, iclass 31, count 0 2006.285.11:08:06.59#ibcon#flushed, iclass 31, count 0 2006.285.11:08:06.59#ibcon#about to write, iclass 31, count 0 2006.285.11:08:06.59#ibcon#wrote, iclass 31, count 0 2006.285.11:08:06.59#ibcon#about to read 3, iclass 31, count 0 2006.285.11:08:06.62#ibcon#read 3, iclass 31, count 0 2006.285.11:08:06.62#ibcon#about to read 4, iclass 31, count 0 2006.285.11:08:06.62#ibcon#read 4, iclass 31, count 0 2006.285.11:08:06.62#ibcon#about to read 5, iclass 31, count 0 2006.285.11:08:06.62#ibcon#read 5, iclass 31, count 0 2006.285.11:08:06.62#ibcon#about to read 6, iclass 31, count 0 2006.285.11:08:06.62#ibcon#read 6, iclass 31, count 0 2006.285.11:08:06.62#ibcon#end of sib2, iclass 31, count 0 2006.285.11:08:06.62#ibcon#*after write, iclass 31, count 0 2006.285.11:08:06.62#ibcon#*before return 0, iclass 31, count 0 2006.285.11:08:06.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:08:06.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:08:06.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:08:06.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:08:06.62$vck44/vblo=5,709.99 2006.285.11:08:06.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.11:08:06.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.11:08:06.62#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:06.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:08:06.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:08:06.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:08:06.62#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:08:06.62#ibcon#first serial, iclass 33, count 0 2006.285.11:08:06.62#ibcon#enter sib2, iclass 33, count 0 2006.285.11:08:06.62#ibcon#flushed, iclass 33, count 0 2006.285.11:08:06.62#ibcon#about to write, iclass 33, count 0 2006.285.11:08:06.62#ibcon#wrote, iclass 33, count 0 2006.285.11:08:06.62#ibcon#about to read 3, iclass 33, count 0 2006.285.11:08:06.64#ibcon#read 3, iclass 33, count 0 2006.285.11:08:06.64#ibcon#about to read 4, iclass 33, count 0 2006.285.11:08:06.64#ibcon#read 4, iclass 33, count 0 2006.285.11:08:06.64#ibcon#about to read 5, iclass 33, count 0 2006.285.11:08:06.64#ibcon#read 5, iclass 33, count 0 2006.285.11:08:06.64#ibcon#about to read 6, iclass 33, count 0 2006.285.11:08:06.64#ibcon#read 6, iclass 33, count 0 2006.285.11:08:06.64#ibcon#end of sib2, iclass 33, count 0 2006.285.11:08:06.64#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:08:06.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:08:06.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:08:06.64#ibcon#*before write, iclass 33, count 0 2006.285.11:08:06.64#ibcon#enter sib2, iclass 33, count 0 2006.285.11:08:06.64#ibcon#flushed, iclass 33, count 0 2006.285.11:08:06.64#ibcon#about to write, iclass 33, count 0 2006.285.11:08:06.64#ibcon#wrote, iclass 33, count 0 2006.285.11:08:06.64#ibcon#about to read 3, iclass 33, count 0 2006.285.11:08:06.68#ibcon#read 3, iclass 33, count 0 2006.285.11:08:06.68#ibcon#about to read 4, iclass 33, count 0 2006.285.11:08:06.68#ibcon#read 4, iclass 33, count 0 2006.285.11:08:06.68#ibcon#about to read 5, iclass 33, count 0 2006.285.11:08:06.68#ibcon#read 5, iclass 33, count 0 2006.285.11:08:06.68#ibcon#about to read 6, iclass 33, count 0 2006.285.11:08:06.68#ibcon#read 6, iclass 33, count 0 2006.285.11:08:06.68#ibcon#end of sib2, iclass 33, count 0 2006.285.11:08:06.68#ibcon#*after write, iclass 33, count 0 2006.285.11:08:06.68#ibcon#*before return 0, iclass 33, count 0 2006.285.11:08:06.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:08:06.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:08:06.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:08:06.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:08:06.68$vck44/vb=5,4 2006.285.11:08:06.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.11:08:06.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.11:08:06.68#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:06.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:08:06.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:08:06.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:08:06.74#ibcon#enter wrdev, iclass 35, count 2 2006.285.11:08:06.74#ibcon#first serial, iclass 35, count 2 2006.285.11:08:06.74#ibcon#enter sib2, iclass 35, count 2 2006.285.11:08:06.74#ibcon#flushed, iclass 35, count 2 2006.285.11:08:06.74#ibcon#about to write, iclass 35, count 2 2006.285.11:08:06.74#ibcon#wrote, iclass 35, count 2 2006.285.11:08:06.74#ibcon#about to read 3, iclass 35, count 2 2006.285.11:08:06.76#ibcon#read 3, iclass 35, count 2 2006.285.11:08:06.76#ibcon#about to read 4, iclass 35, count 2 2006.285.11:08:06.76#ibcon#read 4, iclass 35, count 2 2006.285.11:08:06.76#ibcon#about to read 5, iclass 35, count 2 2006.285.11:08:06.76#ibcon#read 5, iclass 35, count 2 2006.285.11:08:06.76#ibcon#about to read 6, iclass 35, count 2 2006.285.11:08:06.76#ibcon#read 6, iclass 35, count 2 2006.285.11:08:06.76#ibcon#end of sib2, iclass 35, count 2 2006.285.11:08:06.76#ibcon#*mode == 0, iclass 35, count 2 2006.285.11:08:06.76#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.11:08:06.76#ibcon#[27=AT05-04\r\n] 2006.285.11:08:06.76#ibcon#*before write, iclass 35, count 2 2006.285.11:08:06.76#ibcon#enter sib2, iclass 35, count 2 2006.285.11:08:06.76#ibcon#flushed, iclass 35, count 2 2006.285.11:08:06.76#ibcon#about to write, iclass 35, count 2 2006.285.11:08:06.76#ibcon#wrote, iclass 35, count 2 2006.285.11:08:06.76#ibcon#about to read 3, iclass 35, count 2 2006.285.11:08:06.79#ibcon#read 3, iclass 35, count 2 2006.285.11:08:06.79#ibcon#about to read 4, iclass 35, count 2 2006.285.11:08:06.79#ibcon#read 4, iclass 35, count 2 2006.285.11:08:06.79#ibcon#about to read 5, iclass 35, count 2 2006.285.11:08:06.79#ibcon#read 5, iclass 35, count 2 2006.285.11:08:06.79#ibcon#about to read 6, iclass 35, count 2 2006.285.11:08:06.79#ibcon#read 6, iclass 35, count 2 2006.285.11:08:06.79#ibcon#end of sib2, iclass 35, count 2 2006.285.11:08:06.79#ibcon#*after write, iclass 35, count 2 2006.285.11:08:06.79#ibcon#*before return 0, iclass 35, count 2 2006.285.11:08:06.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:08:06.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:08:06.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.11:08:06.79#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:06.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:08:06.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:08:06.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:08:06.91#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:08:06.91#ibcon#first serial, iclass 35, count 0 2006.285.11:08:06.91#ibcon#enter sib2, iclass 35, count 0 2006.285.11:08:06.91#ibcon#flushed, iclass 35, count 0 2006.285.11:08:06.91#ibcon#about to write, iclass 35, count 0 2006.285.11:08:06.91#ibcon#wrote, iclass 35, count 0 2006.285.11:08:06.91#ibcon#about to read 3, iclass 35, count 0 2006.285.11:08:06.93#ibcon#read 3, iclass 35, count 0 2006.285.11:08:06.93#ibcon#about to read 4, iclass 35, count 0 2006.285.11:08:06.93#ibcon#read 4, iclass 35, count 0 2006.285.11:08:06.93#ibcon#about to read 5, iclass 35, count 0 2006.285.11:08:06.93#ibcon#read 5, iclass 35, count 0 2006.285.11:08:06.93#ibcon#about to read 6, iclass 35, count 0 2006.285.11:08:06.93#ibcon#read 6, iclass 35, count 0 2006.285.11:08:06.93#ibcon#end of sib2, iclass 35, count 0 2006.285.11:08:06.93#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:08:06.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:08:06.93#ibcon#[27=USB\r\n] 2006.285.11:08:06.93#ibcon#*before write, iclass 35, count 0 2006.285.11:08:06.93#ibcon#enter sib2, iclass 35, count 0 2006.285.11:08:06.93#ibcon#flushed, iclass 35, count 0 2006.285.11:08:06.93#ibcon#about to write, iclass 35, count 0 2006.285.11:08:06.93#ibcon#wrote, iclass 35, count 0 2006.285.11:08:06.93#ibcon#about to read 3, iclass 35, count 0 2006.285.11:08:06.96#ibcon#read 3, iclass 35, count 0 2006.285.11:08:06.96#ibcon#about to read 4, iclass 35, count 0 2006.285.11:08:06.96#ibcon#read 4, iclass 35, count 0 2006.285.11:08:06.96#ibcon#about to read 5, iclass 35, count 0 2006.285.11:08:06.96#ibcon#read 5, iclass 35, count 0 2006.285.11:08:06.96#ibcon#about to read 6, iclass 35, count 0 2006.285.11:08:06.96#ibcon#read 6, iclass 35, count 0 2006.285.11:08:06.96#ibcon#end of sib2, iclass 35, count 0 2006.285.11:08:06.96#ibcon#*after write, iclass 35, count 0 2006.285.11:08:06.96#ibcon#*before return 0, iclass 35, count 0 2006.285.11:08:06.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:08:06.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:08:06.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:08:06.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:08:06.96$vck44/vblo=6,719.99 2006.285.11:08:06.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.11:08:06.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.11:08:06.96#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:06.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:08:06.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:08:06.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:08:06.96#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:08:06.96#ibcon#first serial, iclass 37, count 0 2006.285.11:08:06.96#ibcon#enter sib2, iclass 37, count 0 2006.285.11:08:06.96#ibcon#flushed, iclass 37, count 0 2006.285.11:08:06.96#ibcon#about to write, iclass 37, count 0 2006.285.11:08:06.96#ibcon#wrote, iclass 37, count 0 2006.285.11:08:06.96#ibcon#about to read 3, iclass 37, count 0 2006.285.11:08:06.98#ibcon#read 3, iclass 37, count 0 2006.285.11:08:06.98#ibcon#about to read 4, iclass 37, count 0 2006.285.11:08:06.98#ibcon#read 4, iclass 37, count 0 2006.285.11:08:06.98#ibcon#about to read 5, iclass 37, count 0 2006.285.11:08:06.98#ibcon#read 5, iclass 37, count 0 2006.285.11:08:06.98#ibcon#about to read 6, iclass 37, count 0 2006.285.11:08:06.98#ibcon#read 6, iclass 37, count 0 2006.285.11:08:06.98#ibcon#end of sib2, iclass 37, count 0 2006.285.11:08:06.98#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:08:06.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:08:06.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:08:06.98#ibcon#*before write, iclass 37, count 0 2006.285.11:08:06.98#ibcon#enter sib2, iclass 37, count 0 2006.285.11:08:06.98#ibcon#flushed, iclass 37, count 0 2006.285.11:08:06.98#ibcon#about to write, iclass 37, count 0 2006.285.11:08:06.98#ibcon#wrote, iclass 37, count 0 2006.285.11:08:06.98#ibcon#about to read 3, iclass 37, count 0 2006.285.11:08:07.02#ibcon#read 3, iclass 37, count 0 2006.285.11:08:07.02#ibcon#about to read 4, iclass 37, count 0 2006.285.11:08:07.02#ibcon#read 4, iclass 37, count 0 2006.285.11:08:07.02#ibcon#about to read 5, iclass 37, count 0 2006.285.11:08:07.02#ibcon#read 5, iclass 37, count 0 2006.285.11:08:07.02#ibcon#about to read 6, iclass 37, count 0 2006.285.11:08:07.02#ibcon#read 6, iclass 37, count 0 2006.285.11:08:07.02#ibcon#end of sib2, iclass 37, count 0 2006.285.11:08:07.02#ibcon#*after write, iclass 37, count 0 2006.285.11:08:07.02#ibcon#*before return 0, iclass 37, count 0 2006.285.11:08:07.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:08:07.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:08:07.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:08:07.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:08:07.02$vck44/vb=6,3 2006.285.11:08:07.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.11:08:07.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.11:08:07.02#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:07.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:08:07.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:08:07.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:08:07.08#ibcon#enter wrdev, iclass 39, count 2 2006.285.11:08:07.08#ibcon#first serial, iclass 39, count 2 2006.285.11:08:07.08#ibcon#enter sib2, iclass 39, count 2 2006.285.11:08:07.08#ibcon#flushed, iclass 39, count 2 2006.285.11:08:07.08#ibcon#about to write, iclass 39, count 2 2006.285.11:08:07.08#ibcon#wrote, iclass 39, count 2 2006.285.11:08:07.08#ibcon#about to read 3, iclass 39, count 2 2006.285.11:08:07.10#ibcon#read 3, iclass 39, count 2 2006.285.11:08:07.10#ibcon#about to read 4, iclass 39, count 2 2006.285.11:08:07.10#ibcon#read 4, iclass 39, count 2 2006.285.11:08:07.10#ibcon#about to read 5, iclass 39, count 2 2006.285.11:08:07.10#ibcon#read 5, iclass 39, count 2 2006.285.11:08:07.10#ibcon#about to read 6, iclass 39, count 2 2006.285.11:08:07.10#ibcon#read 6, iclass 39, count 2 2006.285.11:08:07.10#ibcon#end of sib2, iclass 39, count 2 2006.285.11:08:07.10#ibcon#*mode == 0, iclass 39, count 2 2006.285.11:08:07.10#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.11:08:07.10#ibcon#[27=AT06-03\r\n] 2006.285.11:08:07.10#ibcon#*before write, iclass 39, count 2 2006.285.11:08:07.10#ibcon#enter sib2, iclass 39, count 2 2006.285.11:08:07.10#ibcon#flushed, iclass 39, count 2 2006.285.11:08:07.10#ibcon#about to write, iclass 39, count 2 2006.285.11:08:07.10#ibcon#wrote, iclass 39, count 2 2006.285.11:08:07.10#ibcon#about to read 3, iclass 39, count 2 2006.285.11:08:07.13#ibcon#read 3, iclass 39, count 2 2006.285.11:08:07.13#ibcon#about to read 4, iclass 39, count 2 2006.285.11:08:07.13#ibcon#read 4, iclass 39, count 2 2006.285.11:08:07.13#ibcon#about to read 5, iclass 39, count 2 2006.285.11:08:07.13#ibcon#read 5, iclass 39, count 2 2006.285.11:08:07.13#ibcon#about to read 6, iclass 39, count 2 2006.285.11:08:07.13#ibcon#read 6, iclass 39, count 2 2006.285.11:08:07.13#ibcon#end of sib2, iclass 39, count 2 2006.285.11:08:07.13#ibcon#*after write, iclass 39, count 2 2006.285.11:08:07.13#ibcon#*before return 0, iclass 39, count 2 2006.285.11:08:07.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:08:07.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:08:07.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.11:08:07.13#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:07.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:08:07.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:08:07.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:08:07.25#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:08:07.25#ibcon#first serial, iclass 39, count 0 2006.285.11:08:07.25#ibcon#enter sib2, iclass 39, count 0 2006.285.11:08:07.25#ibcon#flushed, iclass 39, count 0 2006.285.11:08:07.25#ibcon#about to write, iclass 39, count 0 2006.285.11:08:07.25#ibcon#wrote, iclass 39, count 0 2006.285.11:08:07.25#ibcon#about to read 3, iclass 39, count 0 2006.285.11:08:07.27#ibcon#read 3, iclass 39, count 0 2006.285.11:08:07.27#ibcon#about to read 4, iclass 39, count 0 2006.285.11:08:07.27#ibcon#read 4, iclass 39, count 0 2006.285.11:08:07.27#ibcon#about to read 5, iclass 39, count 0 2006.285.11:08:07.27#ibcon#read 5, iclass 39, count 0 2006.285.11:08:07.27#ibcon#about to read 6, iclass 39, count 0 2006.285.11:08:07.27#ibcon#read 6, iclass 39, count 0 2006.285.11:08:07.27#ibcon#end of sib2, iclass 39, count 0 2006.285.11:08:07.27#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:08:07.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:08:07.27#ibcon#[27=USB\r\n] 2006.285.11:08:07.27#ibcon#*before write, iclass 39, count 0 2006.285.11:08:07.27#ibcon#enter sib2, iclass 39, count 0 2006.285.11:08:07.27#ibcon#flushed, iclass 39, count 0 2006.285.11:08:07.27#ibcon#about to write, iclass 39, count 0 2006.285.11:08:07.27#ibcon#wrote, iclass 39, count 0 2006.285.11:08:07.27#ibcon#about to read 3, iclass 39, count 0 2006.285.11:08:07.30#ibcon#read 3, iclass 39, count 0 2006.285.11:08:07.30#ibcon#about to read 4, iclass 39, count 0 2006.285.11:08:07.30#ibcon#read 4, iclass 39, count 0 2006.285.11:08:07.30#ibcon#about to read 5, iclass 39, count 0 2006.285.11:08:07.30#ibcon#read 5, iclass 39, count 0 2006.285.11:08:07.30#ibcon#about to read 6, iclass 39, count 0 2006.285.11:08:07.30#ibcon#read 6, iclass 39, count 0 2006.285.11:08:07.30#ibcon#end of sib2, iclass 39, count 0 2006.285.11:08:07.30#ibcon#*after write, iclass 39, count 0 2006.285.11:08:07.30#ibcon#*before return 0, iclass 39, count 0 2006.285.11:08:07.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:08:07.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:08:07.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:08:07.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:08:07.30$vck44/vblo=7,734.99 2006.285.11:08:07.30#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.11:08:07.30#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.11:08:07.30#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:07.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:08:07.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:08:07.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:08:07.30#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:08:07.30#ibcon#first serial, iclass 4, count 0 2006.285.11:08:07.30#ibcon#enter sib2, iclass 4, count 0 2006.285.11:08:07.30#ibcon#flushed, iclass 4, count 0 2006.285.11:08:07.30#ibcon#about to write, iclass 4, count 0 2006.285.11:08:07.30#ibcon#wrote, iclass 4, count 0 2006.285.11:08:07.30#ibcon#about to read 3, iclass 4, count 0 2006.285.11:08:07.32#ibcon#read 3, iclass 4, count 0 2006.285.11:08:07.32#ibcon#about to read 4, iclass 4, count 0 2006.285.11:08:07.32#ibcon#read 4, iclass 4, count 0 2006.285.11:08:07.32#ibcon#about to read 5, iclass 4, count 0 2006.285.11:08:07.32#ibcon#read 5, iclass 4, count 0 2006.285.11:08:07.32#ibcon#about to read 6, iclass 4, count 0 2006.285.11:08:07.32#ibcon#read 6, iclass 4, count 0 2006.285.11:08:07.32#ibcon#end of sib2, iclass 4, count 0 2006.285.11:08:07.32#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:08:07.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:08:07.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:08:07.32#ibcon#*before write, iclass 4, count 0 2006.285.11:08:07.32#ibcon#enter sib2, iclass 4, count 0 2006.285.11:08:07.32#ibcon#flushed, iclass 4, count 0 2006.285.11:08:07.32#ibcon#about to write, iclass 4, count 0 2006.285.11:08:07.32#ibcon#wrote, iclass 4, count 0 2006.285.11:08:07.32#ibcon#about to read 3, iclass 4, count 0 2006.285.11:08:07.34#abcon#<5=/04 0.9 1.6 19.44 931015.1\r\n> 2006.285.11:08:07.36#abcon#{5=INTERFACE CLEAR} 2006.285.11:08:07.36#ibcon#read 3, iclass 4, count 0 2006.285.11:08:07.36#ibcon#about to read 4, iclass 4, count 0 2006.285.11:08:07.36#ibcon#read 4, iclass 4, count 0 2006.285.11:08:07.36#ibcon#about to read 5, iclass 4, count 0 2006.285.11:08:07.36#ibcon#read 5, iclass 4, count 0 2006.285.11:08:07.36#ibcon#about to read 6, iclass 4, count 0 2006.285.11:08:07.36#ibcon#read 6, iclass 4, count 0 2006.285.11:08:07.36#ibcon#end of sib2, iclass 4, count 0 2006.285.11:08:07.36#ibcon#*after write, iclass 4, count 0 2006.285.11:08:07.36#ibcon#*before return 0, iclass 4, count 0 2006.285.11:08:07.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:08:07.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:08:07.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:08:07.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:08:07.36$vck44/vb=7,4 2006.285.11:08:07.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.11:08:07.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.11:08:07.36#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:07.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:08:07.42#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:08:07.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:08:07.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:08:07.42#ibcon#enter wrdev, iclass 10, count 2 2006.285.11:08:07.42#ibcon#first serial, iclass 10, count 2 2006.285.11:08:07.42#ibcon#enter sib2, iclass 10, count 2 2006.285.11:08:07.42#ibcon#flushed, iclass 10, count 2 2006.285.11:08:07.42#ibcon#about to write, iclass 10, count 2 2006.285.11:08:07.42#ibcon#wrote, iclass 10, count 2 2006.285.11:08:07.42#ibcon#about to read 3, iclass 10, count 2 2006.285.11:08:07.44#ibcon#read 3, iclass 10, count 2 2006.285.11:08:07.44#ibcon#about to read 4, iclass 10, count 2 2006.285.11:08:07.44#ibcon#read 4, iclass 10, count 2 2006.285.11:08:07.44#ibcon#about to read 5, iclass 10, count 2 2006.285.11:08:07.44#ibcon#read 5, iclass 10, count 2 2006.285.11:08:07.44#ibcon#about to read 6, iclass 10, count 2 2006.285.11:08:07.44#ibcon#read 6, iclass 10, count 2 2006.285.11:08:07.44#ibcon#end of sib2, iclass 10, count 2 2006.285.11:08:07.44#ibcon#*mode == 0, iclass 10, count 2 2006.285.11:08:07.44#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.11:08:07.44#ibcon#[27=AT07-04\r\n] 2006.285.11:08:07.44#ibcon#*before write, iclass 10, count 2 2006.285.11:08:07.44#ibcon#enter sib2, iclass 10, count 2 2006.285.11:08:07.44#ibcon#flushed, iclass 10, count 2 2006.285.11:08:07.44#ibcon#about to write, iclass 10, count 2 2006.285.11:08:07.44#ibcon#wrote, iclass 10, count 2 2006.285.11:08:07.44#ibcon#about to read 3, iclass 10, count 2 2006.285.11:08:07.47#ibcon#read 3, iclass 10, count 2 2006.285.11:08:07.47#ibcon#about to read 4, iclass 10, count 2 2006.285.11:08:07.47#ibcon#read 4, iclass 10, count 2 2006.285.11:08:07.47#ibcon#about to read 5, iclass 10, count 2 2006.285.11:08:07.47#ibcon#read 5, iclass 10, count 2 2006.285.11:08:07.47#ibcon#about to read 6, iclass 10, count 2 2006.285.11:08:07.47#ibcon#read 6, iclass 10, count 2 2006.285.11:08:07.47#ibcon#end of sib2, iclass 10, count 2 2006.285.11:08:07.47#ibcon#*after write, iclass 10, count 2 2006.285.11:08:07.47#ibcon#*before return 0, iclass 10, count 2 2006.285.11:08:07.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:08:07.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:08:07.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.11:08:07.47#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:07.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:08:07.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:08:07.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:08:07.59#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:08:07.59#ibcon#first serial, iclass 10, count 0 2006.285.11:08:07.59#ibcon#enter sib2, iclass 10, count 0 2006.285.11:08:07.59#ibcon#flushed, iclass 10, count 0 2006.285.11:08:07.59#ibcon#about to write, iclass 10, count 0 2006.285.11:08:07.59#ibcon#wrote, iclass 10, count 0 2006.285.11:08:07.59#ibcon#about to read 3, iclass 10, count 0 2006.285.11:08:07.61#ibcon#read 3, iclass 10, count 0 2006.285.11:08:07.61#ibcon#about to read 4, iclass 10, count 0 2006.285.11:08:07.61#ibcon#read 4, iclass 10, count 0 2006.285.11:08:07.61#ibcon#about to read 5, iclass 10, count 0 2006.285.11:08:07.61#ibcon#read 5, iclass 10, count 0 2006.285.11:08:07.61#ibcon#about to read 6, iclass 10, count 0 2006.285.11:08:07.61#ibcon#read 6, iclass 10, count 0 2006.285.11:08:07.61#ibcon#end of sib2, iclass 10, count 0 2006.285.11:08:07.61#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:08:07.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:08:07.61#ibcon#[27=USB\r\n] 2006.285.11:08:07.61#ibcon#*before write, iclass 10, count 0 2006.285.11:08:07.61#ibcon#enter sib2, iclass 10, count 0 2006.285.11:08:07.61#ibcon#flushed, iclass 10, count 0 2006.285.11:08:07.61#ibcon#about to write, iclass 10, count 0 2006.285.11:08:07.61#ibcon#wrote, iclass 10, count 0 2006.285.11:08:07.61#ibcon#about to read 3, iclass 10, count 0 2006.285.11:08:07.64#ibcon#read 3, iclass 10, count 0 2006.285.11:08:07.64#ibcon#about to read 4, iclass 10, count 0 2006.285.11:08:07.64#ibcon#read 4, iclass 10, count 0 2006.285.11:08:07.64#ibcon#about to read 5, iclass 10, count 0 2006.285.11:08:07.64#ibcon#read 5, iclass 10, count 0 2006.285.11:08:07.64#ibcon#about to read 6, iclass 10, count 0 2006.285.11:08:07.64#ibcon#read 6, iclass 10, count 0 2006.285.11:08:07.64#ibcon#end of sib2, iclass 10, count 0 2006.285.11:08:07.64#ibcon#*after write, iclass 10, count 0 2006.285.11:08:07.64#ibcon#*before return 0, iclass 10, count 0 2006.285.11:08:07.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:08:07.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:08:07.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:08:07.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:08:07.64$vck44/vblo=8,744.99 2006.285.11:08:07.64#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.11:08:07.64#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.11:08:07.64#ibcon#ireg 17 cls_cnt 0 2006.285.11:08:07.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:08:07.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:08:07.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:08:07.64#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:08:07.64#ibcon#first serial, iclass 13, count 0 2006.285.11:08:07.64#ibcon#enter sib2, iclass 13, count 0 2006.285.11:08:07.64#ibcon#flushed, iclass 13, count 0 2006.285.11:08:07.64#ibcon#about to write, iclass 13, count 0 2006.285.11:08:07.64#ibcon#wrote, iclass 13, count 0 2006.285.11:08:07.64#ibcon#about to read 3, iclass 13, count 0 2006.285.11:08:07.66#ibcon#read 3, iclass 13, count 0 2006.285.11:08:07.66#ibcon#about to read 4, iclass 13, count 0 2006.285.11:08:07.66#ibcon#read 4, iclass 13, count 0 2006.285.11:08:07.66#ibcon#about to read 5, iclass 13, count 0 2006.285.11:08:07.66#ibcon#read 5, iclass 13, count 0 2006.285.11:08:07.66#ibcon#about to read 6, iclass 13, count 0 2006.285.11:08:07.66#ibcon#read 6, iclass 13, count 0 2006.285.11:08:07.66#ibcon#end of sib2, iclass 13, count 0 2006.285.11:08:07.66#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:08:07.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:08:07.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:08:07.66#ibcon#*before write, iclass 13, count 0 2006.285.11:08:07.66#ibcon#enter sib2, iclass 13, count 0 2006.285.11:08:07.66#ibcon#flushed, iclass 13, count 0 2006.285.11:08:07.66#ibcon#about to write, iclass 13, count 0 2006.285.11:08:07.66#ibcon#wrote, iclass 13, count 0 2006.285.11:08:07.66#ibcon#about to read 3, iclass 13, count 0 2006.285.11:08:07.70#ibcon#read 3, iclass 13, count 0 2006.285.11:08:07.70#ibcon#about to read 4, iclass 13, count 0 2006.285.11:08:07.70#ibcon#read 4, iclass 13, count 0 2006.285.11:08:07.70#ibcon#about to read 5, iclass 13, count 0 2006.285.11:08:07.70#ibcon#read 5, iclass 13, count 0 2006.285.11:08:07.70#ibcon#about to read 6, iclass 13, count 0 2006.285.11:08:07.70#ibcon#read 6, iclass 13, count 0 2006.285.11:08:07.70#ibcon#end of sib2, iclass 13, count 0 2006.285.11:08:07.70#ibcon#*after write, iclass 13, count 0 2006.285.11:08:07.70#ibcon#*before return 0, iclass 13, count 0 2006.285.11:08:07.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:08:07.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:08:07.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:08:07.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:08:07.70$vck44/vb=8,4 2006.285.11:08:07.70#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.11:08:07.70#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.11:08:07.70#ibcon#ireg 11 cls_cnt 2 2006.285.11:08:07.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:08:07.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:08:07.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:08:07.76#ibcon#enter wrdev, iclass 15, count 2 2006.285.11:08:07.76#ibcon#first serial, iclass 15, count 2 2006.285.11:08:07.76#ibcon#enter sib2, iclass 15, count 2 2006.285.11:08:07.76#ibcon#flushed, iclass 15, count 2 2006.285.11:08:07.76#ibcon#about to write, iclass 15, count 2 2006.285.11:08:07.76#ibcon#wrote, iclass 15, count 2 2006.285.11:08:07.76#ibcon#about to read 3, iclass 15, count 2 2006.285.11:08:07.78#ibcon#read 3, iclass 15, count 2 2006.285.11:08:07.78#ibcon#about to read 4, iclass 15, count 2 2006.285.11:08:07.78#ibcon#read 4, iclass 15, count 2 2006.285.11:08:07.78#ibcon#about to read 5, iclass 15, count 2 2006.285.11:08:07.78#ibcon#read 5, iclass 15, count 2 2006.285.11:08:07.78#ibcon#about to read 6, iclass 15, count 2 2006.285.11:08:07.78#ibcon#read 6, iclass 15, count 2 2006.285.11:08:07.78#ibcon#end of sib2, iclass 15, count 2 2006.285.11:08:07.78#ibcon#*mode == 0, iclass 15, count 2 2006.285.11:08:07.78#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.11:08:07.78#ibcon#[27=AT08-04\r\n] 2006.285.11:08:07.78#ibcon#*before write, iclass 15, count 2 2006.285.11:08:07.78#ibcon#enter sib2, iclass 15, count 2 2006.285.11:08:07.78#ibcon#flushed, iclass 15, count 2 2006.285.11:08:07.78#ibcon#about to write, iclass 15, count 2 2006.285.11:08:07.78#ibcon#wrote, iclass 15, count 2 2006.285.11:08:07.78#ibcon#about to read 3, iclass 15, count 2 2006.285.11:08:07.81#ibcon#read 3, iclass 15, count 2 2006.285.11:08:07.81#ibcon#about to read 4, iclass 15, count 2 2006.285.11:08:07.81#ibcon#read 4, iclass 15, count 2 2006.285.11:08:07.81#ibcon#about to read 5, iclass 15, count 2 2006.285.11:08:07.81#ibcon#read 5, iclass 15, count 2 2006.285.11:08:07.81#ibcon#about to read 6, iclass 15, count 2 2006.285.11:08:07.81#ibcon#read 6, iclass 15, count 2 2006.285.11:08:07.81#ibcon#end of sib2, iclass 15, count 2 2006.285.11:08:07.81#ibcon#*after write, iclass 15, count 2 2006.285.11:08:07.81#ibcon#*before return 0, iclass 15, count 2 2006.285.11:08:07.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:08:07.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:08:07.81#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.11:08:07.81#ibcon#ireg 7 cls_cnt 0 2006.285.11:08:07.81#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:08:07.93#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:08:07.93#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:08:07.93#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:08:07.93#ibcon#first serial, iclass 15, count 0 2006.285.11:08:07.93#ibcon#enter sib2, iclass 15, count 0 2006.285.11:08:07.93#ibcon#flushed, iclass 15, count 0 2006.285.11:08:07.93#ibcon#about to write, iclass 15, count 0 2006.285.11:08:07.93#ibcon#wrote, iclass 15, count 0 2006.285.11:08:07.93#ibcon#about to read 3, iclass 15, count 0 2006.285.11:08:07.95#ibcon#read 3, iclass 15, count 0 2006.285.11:08:07.95#ibcon#about to read 4, iclass 15, count 0 2006.285.11:08:07.95#ibcon#read 4, iclass 15, count 0 2006.285.11:08:07.95#ibcon#about to read 5, iclass 15, count 0 2006.285.11:08:07.95#ibcon#read 5, iclass 15, count 0 2006.285.11:08:07.95#ibcon#about to read 6, iclass 15, count 0 2006.285.11:08:07.95#ibcon#read 6, iclass 15, count 0 2006.285.11:08:07.95#ibcon#end of sib2, iclass 15, count 0 2006.285.11:08:07.95#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:08:07.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:08:07.95#ibcon#[27=USB\r\n] 2006.285.11:08:07.95#ibcon#*before write, iclass 15, count 0 2006.285.11:08:07.95#ibcon#enter sib2, iclass 15, count 0 2006.285.11:08:07.95#ibcon#flushed, iclass 15, count 0 2006.285.11:08:07.95#ibcon#about to write, iclass 15, count 0 2006.285.11:08:07.95#ibcon#wrote, iclass 15, count 0 2006.285.11:08:07.95#ibcon#about to read 3, iclass 15, count 0 2006.285.11:08:07.98#ibcon#read 3, iclass 15, count 0 2006.285.11:08:07.98#ibcon#about to read 4, iclass 15, count 0 2006.285.11:08:07.98#ibcon#read 4, iclass 15, count 0 2006.285.11:08:07.98#ibcon#about to read 5, iclass 15, count 0 2006.285.11:08:07.98#ibcon#read 5, iclass 15, count 0 2006.285.11:08:07.98#ibcon#about to read 6, iclass 15, count 0 2006.285.11:08:07.98#ibcon#read 6, iclass 15, count 0 2006.285.11:08:07.98#ibcon#end of sib2, iclass 15, count 0 2006.285.11:08:07.98#ibcon#*after write, iclass 15, count 0 2006.285.11:08:07.98#ibcon#*before return 0, iclass 15, count 0 2006.285.11:08:07.98#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:08:07.98#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:08:07.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:08:07.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:08:07.98$vck44/vabw=wide 2006.285.11:08:07.98#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.11:08:07.98#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.11:08:07.98#ibcon#ireg 8 cls_cnt 0 2006.285.11:08:07.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:08:07.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:08:07.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:08:07.98#ibcon#enter wrdev, iclass 17, count 0 2006.285.11:08:07.98#ibcon#first serial, iclass 17, count 0 2006.285.11:08:07.98#ibcon#enter sib2, iclass 17, count 0 2006.285.11:08:07.98#ibcon#flushed, iclass 17, count 0 2006.285.11:08:07.98#ibcon#about to write, iclass 17, count 0 2006.285.11:08:07.98#ibcon#wrote, iclass 17, count 0 2006.285.11:08:07.98#ibcon#about to read 3, iclass 17, count 0 2006.285.11:08:08.00#ibcon#read 3, iclass 17, count 0 2006.285.11:08:08.00#ibcon#about to read 4, iclass 17, count 0 2006.285.11:08:08.00#ibcon#read 4, iclass 17, count 0 2006.285.11:08:08.00#ibcon#about to read 5, iclass 17, count 0 2006.285.11:08:08.00#ibcon#read 5, iclass 17, count 0 2006.285.11:08:08.00#ibcon#about to read 6, iclass 17, count 0 2006.285.11:08:08.00#ibcon#read 6, iclass 17, count 0 2006.285.11:08:08.00#ibcon#end of sib2, iclass 17, count 0 2006.285.11:08:08.00#ibcon#*mode == 0, iclass 17, count 0 2006.285.11:08:08.00#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.11:08:08.00#ibcon#[25=BW32\r\n] 2006.285.11:08:08.00#ibcon#*before write, iclass 17, count 0 2006.285.11:08:08.00#ibcon#enter sib2, iclass 17, count 0 2006.285.11:08:08.00#ibcon#flushed, iclass 17, count 0 2006.285.11:08:08.00#ibcon#about to write, iclass 17, count 0 2006.285.11:08:08.00#ibcon#wrote, iclass 17, count 0 2006.285.11:08:08.00#ibcon#about to read 3, iclass 17, count 0 2006.285.11:08:08.03#ibcon#read 3, iclass 17, count 0 2006.285.11:08:08.03#ibcon#about to read 4, iclass 17, count 0 2006.285.11:08:08.03#ibcon#read 4, iclass 17, count 0 2006.285.11:08:08.03#ibcon#about to read 5, iclass 17, count 0 2006.285.11:08:08.03#ibcon#read 5, iclass 17, count 0 2006.285.11:08:08.03#ibcon#about to read 6, iclass 17, count 0 2006.285.11:08:08.03#ibcon#read 6, iclass 17, count 0 2006.285.11:08:08.03#ibcon#end of sib2, iclass 17, count 0 2006.285.11:08:08.03#ibcon#*after write, iclass 17, count 0 2006.285.11:08:08.03#ibcon#*before return 0, iclass 17, count 0 2006.285.11:08:08.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:08:08.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:08:08.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.11:08:08.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.11:08:08.03$vck44/vbbw=wide 2006.285.11:08:08.03#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.11:08:08.03#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.11:08:08.03#ibcon#ireg 8 cls_cnt 0 2006.285.11:08:08.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:08:08.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:08:08.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:08:08.10#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:08:08.10#ibcon#first serial, iclass 19, count 0 2006.285.11:08:08.10#ibcon#enter sib2, iclass 19, count 0 2006.285.11:08:08.10#ibcon#flushed, iclass 19, count 0 2006.285.11:08:08.10#ibcon#about to write, iclass 19, count 0 2006.285.11:08:08.10#ibcon#wrote, iclass 19, count 0 2006.285.11:08:08.10#ibcon#about to read 3, iclass 19, count 0 2006.285.11:08:08.12#ibcon#read 3, iclass 19, count 0 2006.285.11:08:08.12#ibcon#about to read 4, iclass 19, count 0 2006.285.11:08:08.12#ibcon#read 4, iclass 19, count 0 2006.285.11:08:08.12#ibcon#about to read 5, iclass 19, count 0 2006.285.11:08:08.12#ibcon#read 5, iclass 19, count 0 2006.285.11:08:08.12#ibcon#about to read 6, iclass 19, count 0 2006.285.11:08:08.12#ibcon#read 6, iclass 19, count 0 2006.285.11:08:08.12#ibcon#end of sib2, iclass 19, count 0 2006.285.11:08:08.12#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:08:08.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:08:08.12#ibcon#[27=BW32\r\n] 2006.285.11:08:08.12#ibcon#*before write, iclass 19, count 0 2006.285.11:08:08.12#ibcon#enter sib2, iclass 19, count 0 2006.285.11:08:08.12#ibcon#flushed, iclass 19, count 0 2006.285.11:08:08.12#ibcon#about to write, iclass 19, count 0 2006.285.11:08:08.12#ibcon#wrote, iclass 19, count 0 2006.285.11:08:08.12#ibcon#about to read 3, iclass 19, count 0 2006.285.11:08:08.15#ibcon#read 3, iclass 19, count 0 2006.285.11:08:08.15#ibcon#about to read 4, iclass 19, count 0 2006.285.11:08:08.15#ibcon#read 4, iclass 19, count 0 2006.285.11:08:08.15#ibcon#about to read 5, iclass 19, count 0 2006.285.11:08:08.15#ibcon#read 5, iclass 19, count 0 2006.285.11:08:08.15#ibcon#about to read 6, iclass 19, count 0 2006.285.11:08:08.15#ibcon#read 6, iclass 19, count 0 2006.285.11:08:08.15#ibcon#end of sib2, iclass 19, count 0 2006.285.11:08:08.15#ibcon#*after write, iclass 19, count 0 2006.285.11:08:08.15#ibcon#*before return 0, iclass 19, count 0 2006.285.11:08:08.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:08:08.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:08:08.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:08:08.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:08:08.15$setupk4/ifdk4 2006.285.11:08:08.15$ifdk4/lo= 2006.285.11:08:08.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:08:08.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:08:08.15$ifdk4/patch= 2006.285.11:08:08.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:08:08.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:08:08.15$setupk4/!*+20s 2006.285.11:08:17.51#abcon#<5=/04 0.9 1.6 19.44 931015.1\r\n> 2006.285.11:08:17.53#abcon#{5=INTERFACE CLEAR} 2006.285.11:08:17.59#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:08:22.65$setupk4/"tpicd 2006.285.11:08:22.65$setupk4/echo=off 2006.285.11:08:22.65$setupk4/xlog=off 2006.285.11:08:22.65:!2006.285.11:12:23 2006.285.11:09:25.14#trakl#Source acquired 2006.285.11:09:25.14#flagr#flagr/antenna,acquired 2006.285.11:12:23.02:preob 2006.285.11:12:24.14/onsource/TRACKING 2006.285.11:12:24.14:!2006.285.11:12:33 2006.285.11:12:33.02:"tape 2006.285.11:12:33.02:"st=record 2006.285.11:12:33.02:data_valid=on 2006.285.11:12:33.02:midob 2006.285.11:12:34.14/onsource/TRACKING 2006.285.11:12:34.14/wx/19.42,1015.1,93 2006.285.11:12:34.23/cable/+6.4880E-03 2006.285.11:12:35.32/va/01,07,usb,yes,31,34 2006.285.11:12:35.32/va/02,06,usb,yes,31,32 2006.285.11:12:35.32/va/03,07,usb,yes,31,33 2006.285.11:12:35.32/va/04,06,usb,yes,32,34 2006.285.11:12:35.32/va/05,03,usb,yes,32,32 2006.285.11:12:35.32/va/06,04,usb,yes,29,28 2006.285.11:12:35.32/va/07,04,usb,yes,29,30 2006.285.11:12:35.32/va/08,03,usb,yes,30,36 2006.285.11:12:35.55/valo/01,524.99,yes,locked 2006.285.11:12:35.55/valo/02,534.99,yes,locked 2006.285.11:12:35.55/valo/03,564.99,yes,locked 2006.285.11:12:35.55/valo/04,624.99,yes,locked 2006.285.11:12:35.55/valo/05,734.99,yes,locked 2006.285.11:12:35.55/valo/06,814.99,yes,locked 2006.285.11:12:35.55/valo/07,864.99,yes,locked 2006.285.11:12:35.55/valo/08,884.99,yes,locked 2006.285.11:12:36.64/vb/01,04,usb,yes,30,28 2006.285.11:12:36.64/vb/02,05,usb,yes,29,29 2006.285.11:12:36.64/vb/03,04,usb,yes,30,33 2006.285.11:12:36.64/vb/04,05,usb,yes,30,29 2006.285.11:12:36.64/vb/05,04,usb,yes,26,29 2006.285.11:12:36.64/vb/06,03,usb,yes,38,34 2006.285.11:12:36.64/vb/07,04,usb,yes,31,31 2006.285.11:12:36.64/vb/08,04,usb,yes,28,31 2006.285.11:12:36.87/vblo/01,629.99,yes,locked 2006.285.11:12:36.87/vblo/02,634.99,yes,locked 2006.285.11:12:36.87/vblo/03,649.99,yes,locked 2006.285.11:12:36.87/vblo/04,679.99,yes,locked 2006.285.11:12:36.87/vblo/05,709.99,yes,locked 2006.285.11:12:36.87/vblo/06,719.99,yes,locked 2006.285.11:12:36.87/vblo/07,734.99,yes,locked 2006.285.11:12:36.87/vblo/08,744.99,yes,locked 2006.285.11:12:37.02/vabw/8 2006.285.11:12:37.17/vbbw/8 2006.285.11:12:37.26/xfe/off,on,12.2 2006.285.11:12:37.65/ifatt/23,28,28,28 2006.285.11:12:38.07/fmout-gps/S +2.82E-07 2006.285.11:12:38.09:!2006.285.11:14:23 2006.285.11:14:23.01:data_valid=off 2006.285.11:14:23.02:"et 2006.285.11:14:23.02:!+3s 2006.285.11:14:26.04:"tape 2006.285.11:14:26.04:postob 2006.285.11:14:26.15/cable/+6.4886E-03 2006.285.11:14:26.15/wx/19.40,1015.2,93 2006.285.11:14:26.21/fmout-gps/S +2.81E-07 2006.285.11:14:26.21:scan_name=285-1117,jd0610,160 2006.285.11:14:26.22:source=2201+315,220314.98,314538.3,2000.0,cw 2006.285.11:14:28.14#flagr#flagr/antenna,new-source 2006.285.11:14:28.15:checkk5 2006.285.11:14:28.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:14:28.95/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:14:29.35/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:14:29.74/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:14:30.14/chk_obsdata//k5ts1/T2851112??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.11:14:30.58/chk_obsdata//k5ts2/T2851112??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.11:14:30.99/chk_obsdata//k5ts3/T2851112??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.11:14:31.37/chk_obsdata//k5ts4/T2851112??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.11:14:32.17/k5log//k5ts1_log_newline 2006.285.11:14:33.19/k5log//k5ts2_log_newline 2006.285.11:14:33.95/k5log//k5ts3_log_newline 2006.285.11:14:34.96/k5log//k5ts4_log_newline 2006.285.11:14:34.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:14:34.99:setupk4=1 2006.285.11:14:34.99$setupk4/echo=on 2006.285.11:14:34.99$setupk4/pcalon 2006.285.11:14:34.99$pcalon/"no phase cal control is implemented here 2006.285.11:14:34.99$setupk4/"tpicd=stop 2006.285.11:14:34.99$setupk4/"rec=synch_on 2006.285.11:14:34.99$setupk4/"rec_mode=128 2006.285.11:14:34.99$setupk4/!* 2006.285.11:14:34.99$setupk4/recpk4 2006.285.11:14:34.99$recpk4/recpatch= 2006.285.11:14:34.99$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:14:34.99$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:14:34.99$setupk4/vck44 2006.285.11:14:34.99$vck44/valo=1,524.99 2006.285.11:14:34.99#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.11:14:34.99#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.11:14:34.99#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:34.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:14:34.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:14:34.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:14:34.99#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:14:34.99#ibcon#first serial, iclass 32, count 0 2006.285.11:14:34.99#ibcon#enter sib2, iclass 32, count 0 2006.285.11:14:34.99#ibcon#flushed, iclass 32, count 0 2006.285.11:14:34.99#ibcon#about to write, iclass 32, count 0 2006.285.11:14:34.99#ibcon#wrote, iclass 32, count 0 2006.285.11:14:34.99#ibcon#about to read 3, iclass 32, count 0 2006.285.11:14:35.00#ibcon#read 3, iclass 32, count 0 2006.285.11:14:35.00#ibcon#about to read 4, iclass 32, count 0 2006.285.11:14:35.00#ibcon#read 4, iclass 32, count 0 2006.285.11:14:35.00#ibcon#about to read 5, iclass 32, count 0 2006.285.11:14:35.00#ibcon#read 5, iclass 32, count 0 2006.285.11:14:35.00#ibcon#about to read 6, iclass 32, count 0 2006.285.11:14:35.00#ibcon#read 6, iclass 32, count 0 2006.285.11:14:35.00#ibcon#end of sib2, iclass 32, count 0 2006.285.11:14:35.00#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:14:35.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:14:35.00#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:14:35.00#ibcon#*before write, iclass 32, count 0 2006.285.11:14:35.00#ibcon#enter sib2, iclass 32, count 0 2006.285.11:14:35.00#ibcon#flushed, iclass 32, count 0 2006.285.11:14:35.00#ibcon#about to write, iclass 32, count 0 2006.285.11:14:35.00#ibcon#wrote, iclass 32, count 0 2006.285.11:14:35.00#ibcon#about to read 3, iclass 32, count 0 2006.285.11:14:35.05#ibcon#read 3, iclass 32, count 0 2006.285.11:14:35.05#ibcon#about to read 4, iclass 32, count 0 2006.285.11:14:35.05#ibcon#read 4, iclass 32, count 0 2006.285.11:14:35.05#ibcon#about to read 5, iclass 32, count 0 2006.285.11:14:35.05#ibcon#read 5, iclass 32, count 0 2006.285.11:14:35.05#ibcon#about to read 6, iclass 32, count 0 2006.285.11:14:35.05#ibcon#read 6, iclass 32, count 0 2006.285.11:14:35.05#ibcon#end of sib2, iclass 32, count 0 2006.285.11:14:35.05#ibcon#*after write, iclass 32, count 0 2006.285.11:14:35.05#ibcon#*before return 0, iclass 32, count 0 2006.285.11:14:35.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:14:35.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:14:35.05#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:14:35.05#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:14:35.05$vck44/va=1,7 2006.285.11:14:35.05#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.11:14:35.05#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.11:14:35.05#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:35.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:14:35.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:14:35.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:14:35.05#ibcon#enter wrdev, iclass 34, count 2 2006.285.11:14:35.05#ibcon#first serial, iclass 34, count 2 2006.285.11:14:35.05#ibcon#enter sib2, iclass 34, count 2 2006.285.11:14:35.05#ibcon#flushed, iclass 34, count 2 2006.285.11:14:35.05#ibcon#about to write, iclass 34, count 2 2006.285.11:14:35.05#ibcon#wrote, iclass 34, count 2 2006.285.11:14:35.05#ibcon#about to read 3, iclass 34, count 2 2006.285.11:14:35.07#ibcon#read 3, iclass 34, count 2 2006.285.11:14:35.07#ibcon#about to read 4, iclass 34, count 2 2006.285.11:14:35.07#ibcon#read 4, iclass 34, count 2 2006.285.11:14:35.07#ibcon#about to read 5, iclass 34, count 2 2006.285.11:14:35.07#ibcon#read 5, iclass 34, count 2 2006.285.11:14:35.07#ibcon#about to read 6, iclass 34, count 2 2006.285.11:14:35.07#ibcon#read 6, iclass 34, count 2 2006.285.11:14:35.07#ibcon#end of sib2, iclass 34, count 2 2006.285.11:14:35.07#ibcon#*mode == 0, iclass 34, count 2 2006.285.11:14:35.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.11:14:35.07#ibcon#[25=AT01-07\r\n] 2006.285.11:14:35.07#ibcon#*before write, iclass 34, count 2 2006.285.11:14:35.07#ibcon#enter sib2, iclass 34, count 2 2006.285.11:14:35.07#ibcon#flushed, iclass 34, count 2 2006.285.11:14:35.07#ibcon#about to write, iclass 34, count 2 2006.285.11:14:35.07#ibcon#wrote, iclass 34, count 2 2006.285.11:14:35.07#ibcon#about to read 3, iclass 34, count 2 2006.285.11:14:35.10#ibcon#read 3, iclass 34, count 2 2006.285.11:14:35.10#ibcon#about to read 4, iclass 34, count 2 2006.285.11:14:35.10#ibcon#read 4, iclass 34, count 2 2006.285.11:14:35.10#ibcon#about to read 5, iclass 34, count 2 2006.285.11:14:35.10#ibcon#read 5, iclass 34, count 2 2006.285.11:14:35.10#ibcon#about to read 6, iclass 34, count 2 2006.285.11:14:35.10#ibcon#read 6, iclass 34, count 2 2006.285.11:14:35.10#ibcon#end of sib2, iclass 34, count 2 2006.285.11:14:35.10#ibcon#*after write, iclass 34, count 2 2006.285.11:14:35.10#ibcon#*before return 0, iclass 34, count 2 2006.285.11:14:35.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:14:35.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:14:35.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.11:14:35.10#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:35.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:14:35.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:14:35.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:14:35.22#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:14:35.22#ibcon#first serial, iclass 34, count 0 2006.285.11:14:35.22#ibcon#enter sib2, iclass 34, count 0 2006.285.11:14:35.22#ibcon#flushed, iclass 34, count 0 2006.285.11:14:35.22#ibcon#about to write, iclass 34, count 0 2006.285.11:14:35.22#ibcon#wrote, iclass 34, count 0 2006.285.11:14:35.22#ibcon#about to read 3, iclass 34, count 0 2006.285.11:14:35.24#ibcon#read 3, iclass 34, count 0 2006.285.11:14:35.24#ibcon#about to read 4, iclass 34, count 0 2006.285.11:14:35.24#ibcon#read 4, iclass 34, count 0 2006.285.11:14:35.24#ibcon#about to read 5, iclass 34, count 0 2006.285.11:14:35.24#ibcon#read 5, iclass 34, count 0 2006.285.11:14:35.24#ibcon#about to read 6, iclass 34, count 0 2006.285.11:14:35.24#ibcon#read 6, iclass 34, count 0 2006.285.11:14:35.24#ibcon#end of sib2, iclass 34, count 0 2006.285.11:14:35.24#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:14:35.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:14:35.24#ibcon#[25=USB\r\n] 2006.285.11:14:35.24#ibcon#*before write, iclass 34, count 0 2006.285.11:14:35.24#ibcon#enter sib2, iclass 34, count 0 2006.285.11:14:35.24#ibcon#flushed, iclass 34, count 0 2006.285.11:14:35.24#ibcon#about to write, iclass 34, count 0 2006.285.11:14:35.24#ibcon#wrote, iclass 34, count 0 2006.285.11:14:35.24#ibcon#about to read 3, iclass 34, count 0 2006.285.11:14:35.27#ibcon#read 3, iclass 34, count 0 2006.285.11:14:35.27#ibcon#about to read 4, iclass 34, count 0 2006.285.11:14:35.27#ibcon#read 4, iclass 34, count 0 2006.285.11:14:35.27#ibcon#about to read 5, iclass 34, count 0 2006.285.11:14:35.27#ibcon#read 5, iclass 34, count 0 2006.285.11:14:35.27#ibcon#about to read 6, iclass 34, count 0 2006.285.11:14:35.27#ibcon#read 6, iclass 34, count 0 2006.285.11:14:35.27#ibcon#end of sib2, iclass 34, count 0 2006.285.11:14:35.27#ibcon#*after write, iclass 34, count 0 2006.285.11:14:35.27#ibcon#*before return 0, iclass 34, count 0 2006.285.11:14:35.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:14:35.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:14:35.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:14:35.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:14:35.27$vck44/valo=2,534.99 2006.285.11:14:35.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.11:14:35.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.11:14:35.27#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:35.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:14:35.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:14:35.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:14:35.27#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:14:35.27#ibcon#first serial, iclass 36, count 0 2006.285.11:14:35.27#ibcon#enter sib2, iclass 36, count 0 2006.285.11:14:35.27#ibcon#flushed, iclass 36, count 0 2006.285.11:14:35.27#ibcon#about to write, iclass 36, count 0 2006.285.11:14:35.27#ibcon#wrote, iclass 36, count 0 2006.285.11:14:35.27#ibcon#about to read 3, iclass 36, count 0 2006.285.11:14:35.29#ibcon#read 3, iclass 36, count 0 2006.285.11:14:35.29#ibcon#about to read 4, iclass 36, count 0 2006.285.11:14:35.29#ibcon#read 4, iclass 36, count 0 2006.285.11:14:35.29#ibcon#about to read 5, iclass 36, count 0 2006.285.11:14:35.29#ibcon#read 5, iclass 36, count 0 2006.285.11:14:35.29#ibcon#about to read 6, iclass 36, count 0 2006.285.11:14:35.29#ibcon#read 6, iclass 36, count 0 2006.285.11:14:35.29#ibcon#end of sib2, iclass 36, count 0 2006.285.11:14:35.29#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:14:35.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:14:35.29#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:14:35.29#ibcon#*before write, iclass 36, count 0 2006.285.11:14:35.29#ibcon#enter sib2, iclass 36, count 0 2006.285.11:14:35.29#ibcon#flushed, iclass 36, count 0 2006.285.11:14:35.29#ibcon#about to write, iclass 36, count 0 2006.285.11:14:35.29#ibcon#wrote, iclass 36, count 0 2006.285.11:14:35.29#ibcon#about to read 3, iclass 36, count 0 2006.285.11:14:35.33#ibcon#read 3, iclass 36, count 0 2006.285.11:14:35.33#ibcon#about to read 4, iclass 36, count 0 2006.285.11:14:35.33#ibcon#read 4, iclass 36, count 0 2006.285.11:14:35.33#ibcon#about to read 5, iclass 36, count 0 2006.285.11:14:35.33#ibcon#read 5, iclass 36, count 0 2006.285.11:14:35.33#ibcon#about to read 6, iclass 36, count 0 2006.285.11:14:35.33#ibcon#read 6, iclass 36, count 0 2006.285.11:14:35.33#ibcon#end of sib2, iclass 36, count 0 2006.285.11:14:35.33#ibcon#*after write, iclass 36, count 0 2006.285.11:14:35.33#ibcon#*before return 0, iclass 36, count 0 2006.285.11:14:35.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:14:35.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:14:35.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:14:35.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:14:35.33$vck44/va=2,6 2006.285.11:14:35.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.11:14:35.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.11:14:35.33#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:35.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:14:35.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:14:35.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:14:35.39#ibcon#enter wrdev, iclass 38, count 2 2006.285.11:14:35.39#ibcon#first serial, iclass 38, count 2 2006.285.11:14:35.39#ibcon#enter sib2, iclass 38, count 2 2006.285.11:14:35.39#ibcon#flushed, iclass 38, count 2 2006.285.11:14:35.39#ibcon#about to write, iclass 38, count 2 2006.285.11:14:35.39#ibcon#wrote, iclass 38, count 2 2006.285.11:14:35.39#ibcon#about to read 3, iclass 38, count 2 2006.285.11:14:35.41#ibcon#read 3, iclass 38, count 2 2006.285.11:14:35.41#ibcon#about to read 4, iclass 38, count 2 2006.285.11:14:35.41#ibcon#read 4, iclass 38, count 2 2006.285.11:14:35.41#ibcon#about to read 5, iclass 38, count 2 2006.285.11:14:35.41#ibcon#read 5, iclass 38, count 2 2006.285.11:14:35.41#ibcon#about to read 6, iclass 38, count 2 2006.285.11:14:35.41#ibcon#read 6, iclass 38, count 2 2006.285.11:14:35.41#ibcon#end of sib2, iclass 38, count 2 2006.285.11:14:35.41#ibcon#*mode == 0, iclass 38, count 2 2006.285.11:14:35.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.11:14:35.41#ibcon#[25=AT02-06\r\n] 2006.285.11:14:35.41#ibcon#*before write, iclass 38, count 2 2006.285.11:14:35.41#ibcon#enter sib2, iclass 38, count 2 2006.285.11:14:35.41#ibcon#flushed, iclass 38, count 2 2006.285.11:14:35.41#ibcon#about to write, iclass 38, count 2 2006.285.11:14:35.41#ibcon#wrote, iclass 38, count 2 2006.285.11:14:35.41#ibcon#about to read 3, iclass 38, count 2 2006.285.11:14:35.44#ibcon#read 3, iclass 38, count 2 2006.285.11:14:35.44#ibcon#about to read 4, iclass 38, count 2 2006.285.11:14:35.44#ibcon#read 4, iclass 38, count 2 2006.285.11:14:35.44#ibcon#about to read 5, iclass 38, count 2 2006.285.11:14:35.44#ibcon#read 5, iclass 38, count 2 2006.285.11:14:35.44#ibcon#about to read 6, iclass 38, count 2 2006.285.11:14:35.44#ibcon#read 6, iclass 38, count 2 2006.285.11:14:35.44#ibcon#end of sib2, iclass 38, count 2 2006.285.11:14:35.44#ibcon#*after write, iclass 38, count 2 2006.285.11:14:35.44#ibcon#*before return 0, iclass 38, count 2 2006.285.11:14:35.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:14:35.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:14:35.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.11:14:35.44#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:35.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:14:35.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:14:35.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:14:35.56#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:14:35.56#ibcon#first serial, iclass 38, count 0 2006.285.11:14:35.56#ibcon#enter sib2, iclass 38, count 0 2006.285.11:14:35.56#ibcon#flushed, iclass 38, count 0 2006.285.11:14:35.56#ibcon#about to write, iclass 38, count 0 2006.285.11:14:35.56#ibcon#wrote, iclass 38, count 0 2006.285.11:14:35.56#ibcon#about to read 3, iclass 38, count 0 2006.285.11:14:35.58#ibcon#read 3, iclass 38, count 0 2006.285.11:14:35.58#ibcon#about to read 4, iclass 38, count 0 2006.285.11:14:35.58#ibcon#read 4, iclass 38, count 0 2006.285.11:14:35.58#ibcon#about to read 5, iclass 38, count 0 2006.285.11:14:35.58#ibcon#read 5, iclass 38, count 0 2006.285.11:14:35.58#ibcon#about to read 6, iclass 38, count 0 2006.285.11:14:35.58#ibcon#read 6, iclass 38, count 0 2006.285.11:14:35.58#ibcon#end of sib2, iclass 38, count 0 2006.285.11:14:35.58#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:14:35.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:14:35.58#ibcon#[25=USB\r\n] 2006.285.11:14:35.58#ibcon#*before write, iclass 38, count 0 2006.285.11:14:35.58#ibcon#enter sib2, iclass 38, count 0 2006.285.11:14:35.58#ibcon#flushed, iclass 38, count 0 2006.285.11:14:35.58#ibcon#about to write, iclass 38, count 0 2006.285.11:14:35.58#ibcon#wrote, iclass 38, count 0 2006.285.11:14:35.58#ibcon#about to read 3, iclass 38, count 0 2006.285.11:14:35.61#ibcon#read 3, iclass 38, count 0 2006.285.11:14:35.61#ibcon#about to read 4, iclass 38, count 0 2006.285.11:14:35.61#ibcon#read 4, iclass 38, count 0 2006.285.11:14:35.61#ibcon#about to read 5, iclass 38, count 0 2006.285.11:14:35.61#ibcon#read 5, iclass 38, count 0 2006.285.11:14:35.61#ibcon#about to read 6, iclass 38, count 0 2006.285.11:14:35.61#ibcon#read 6, iclass 38, count 0 2006.285.11:14:35.61#ibcon#end of sib2, iclass 38, count 0 2006.285.11:14:35.61#ibcon#*after write, iclass 38, count 0 2006.285.11:14:35.61#ibcon#*before return 0, iclass 38, count 0 2006.285.11:14:35.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:14:35.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:14:35.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:14:35.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:14:35.61$vck44/valo=3,564.99 2006.285.11:14:35.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.11:14:35.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.11:14:35.61#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:35.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:14:35.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:14:35.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:14:35.61#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:14:35.61#ibcon#first serial, iclass 40, count 0 2006.285.11:14:35.61#ibcon#enter sib2, iclass 40, count 0 2006.285.11:14:35.61#ibcon#flushed, iclass 40, count 0 2006.285.11:14:35.61#ibcon#about to write, iclass 40, count 0 2006.285.11:14:35.61#ibcon#wrote, iclass 40, count 0 2006.285.11:14:35.61#ibcon#about to read 3, iclass 40, count 0 2006.285.11:14:35.63#ibcon#read 3, iclass 40, count 0 2006.285.11:14:35.63#ibcon#about to read 4, iclass 40, count 0 2006.285.11:14:35.63#ibcon#read 4, iclass 40, count 0 2006.285.11:14:35.63#ibcon#about to read 5, iclass 40, count 0 2006.285.11:14:35.63#ibcon#read 5, iclass 40, count 0 2006.285.11:14:35.63#ibcon#about to read 6, iclass 40, count 0 2006.285.11:14:35.63#ibcon#read 6, iclass 40, count 0 2006.285.11:14:35.63#ibcon#end of sib2, iclass 40, count 0 2006.285.11:14:35.63#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:14:35.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:14:35.63#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:14:35.63#ibcon#*before write, iclass 40, count 0 2006.285.11:14:35.63#ibcon#enter sib2, iclass 40, count 0 2006.285.11:14:35.63#ibcon#flushed, iclass 40, count 0 2006.285.11:14:35.63#ibcon#about to write, iclass 40, count 0 2006.285.11:14:35.63#ibcon#wrote, iclass 40, count 0 2006.285.11:14:35.63#ibcon#about to read 3, iclass 40, count 0 2006.285.11:14:35.67#ibcon#read 3, iclass 40, count 0 2006.285.11:14:35.67#ibcon#about to read 4, iclass 40, count 0 2006.285.11:14:35.67#ibcon#read 4, iclass 40, count 0 2006.285.11:14:35.67#ibcon#about to read 5, iclass 40, count 0 2006.285.11:14:35.67#ibcon#read 5, iclass 40, count 0 2006.285.11:14:35.67#ibcon#about to read 6, iclass 40, count 0 2006.285.11:14:35.67#ibcon#read 6, iclass 40, count 0 2006.285.11:14:35.67#ibcon#end of sib2, iclass 40, count 0 2006.285.11:14:35.67#ibcon#*after write, iclass 40, count 0 2006.285.11:14:35.67#ibcon#*before return 0, iclass 40, count 0 2006.285.11:14:35.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:14:35.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:14:35.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:14:35.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:14:35.67$vck44/va=3,7 2006.285.11:14:35.67#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.11:14:35.67#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.11:14:35.67#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:35.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:14:35.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:14:35.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:14:35.73#ibcon#enter wrdev, iclass 4, count 2 2006.285.11:14:35.73#ibcon#first serial, iclass 4, count 2 2006.285.11:14:35.73#ibcon#enter sib2, iclass 4, count 2 2006.285.11:14:35.73#ibcon#flushed, iclass 4, count 2 2006.285.11:14:35.73#ibcon#about to write, iclass 4, count 2 2006.285.11:14:35.73#ibcon#wrote, iclass 4, count 2 2006.285.11:14:35.73#ibcon#about to read 3, iclass 4, count 2 2006.285.11:14:35.75#ibcon#read 3, iclass 4, count 2 2006.285.11:14:35.75#ibcon#about to read 4, iclass 4, count 2 2006.285.11:14:35.75#ibcon#read 4, iclass 4, count 2 2006.285.11:14:35.75#ibcon#about to read 5, iclass 4, count 2 2006.285.11:14:35.75#ibcon#read 5, iclass 4, count 2 2006.285.11:14:35.75#ibcon#about to read 6, iclass 4, count 2 2006.285.11:14:35.75#ibcon#read 6, iclass 4, count 2 2006.285.11:14:35.75#ibcon#end of sib2, iclass 4, count 2 2006.285.11:14:35.75#ibcon#*mode == 0, iclass 4, count 2 2006.285.11:14:35.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.11:14:35.75#ibcon#[25=AT03-07\r\n] 2006.285.11:14:35.75#ibcon#*before write, iclass 4, count 2 2006.285.11:14:35.75#ibcon#enter sib2, iclass 4, count 2 2006.285.11:14:35.75#ibcon#flushed, iclass 4, count 2 2006.285.11:14:35.75#ibcon#about to write, iclass 4, count 2 2006.285.11:14:35.75#ibcon#wrote, iclass 4, count 2 2006.285.11:14:35.75#ibcon#about to read 3, iclass 4, count 2 2006.285.11:14:35.78#ibcon#read 3, iclass 4, count 2 2006.285.11:14:35.78#ibcon#about to read 4, iclass 4, count 2 2006.285.11:14:35.78#ibcon#read 4, iclass 4, count 2 2006.285.11:14:35.78#ibcon#about to read 5, iclass 4, count 2 2006.285.11:14:35.78#ibcon#read 5, iclass 4, count 2 2006.285.11:14:35.78#ibcon#about to read 6, iclass 4, count 2 2006.285.11:14:35.78#ibcon#read 6, iclass 4, count 2 2006.285.11:14:35.78#ibcon#end of sib2, iclass 4, count 2 2006.285.11:14:35.78#ibcon#*after write, iclass 4, count 2 2006.285.11:14:35.78#ibcon#*before return 0, iclass 4, count 2 2006.285.11:14:35.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:14:35.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:14:35.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.11:14:35.78#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:35.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:14:35.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:14:35.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:14:35.90#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:14:35.90#ibcon#first serial, iclass 4, count 0 2006.285.11:14:35.90#ibcon#enter sib2, iclass 4, count 0 2006.285.11:14:35.90#ibcon#flushed, iclass 4, count 0 2006.285.11:14:35.90#ibcon#about to write, iclass 4, count 0 2006.285.11:14:35.90#ibcon#wrote, iclass 4, count 0 2006.285.11:14:35.90#ibcon#about to read 3, iclass 4, count 0 2006.285.11:14:35.92#ibcon#read 3, iclass 4, count 0 2006.285.11:14:35.92#ibcon#about to read 4, iclass 4, count 0 2006.285.11:14:35.92#ibcon#read 4, iclass 4, count 0 2006.285.11:14:35.92#ibcon#about to read 5, iclass 4, count 0 2006.285.11:14:35.92#ibcon#read 5, iclass 4, count 0 2006.285.11:14:35.92#ibcon#about to read 6, iclass 4, count 0 2006.285.11:14:35.92#ibcon#read 6, iclass 4, count 0 2006.285.11:14:35.92#ibcon#end of sib2, iclass 4, count 0 2006.285.11:14:35.92#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:14:35.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:14:35.92#ibcon#[25=USB\r\n] 2006.285.11:14:35.92#ibcon#*before write, iclass 4, count 0 2006.285.11:14:35.92#ibcon#enter sib2, iclass 4, count 0 2006.285.11:14:35.92#ibcon#flushed, iclass 4, count 0 2006.285.11:14:35.92#ibcon#about to write, iclass 4, count 0 2006.285.11:14:35.92#ibcon#wrote, iclass 4, count 0 2006.285.11:14:35.92#ibcon#about to read 3, iclass 4, count 0 2006.285.11:14:35.95#ibcon#read 3, iclass 4, count 0 2006.285.11:14:35.95#ibcon#about to read 4, iclass 4, count 0 2006.285.11:14:35.95#ibcon#read 4, iclass 4, count 0 2006.285.11:14:35.95#ibcon#about to read 5, iclass 4, count 0 2006.285.11:14:35.95#ibcon#read 5, iclass 4, count 0 2006.285.11:14:35.95#ibcon#about to read 6, iclass 4, count 0 2006.285.11:14:35.95#ibcon#read 6, iclass 4, count 0 2006.285.11:14:35.95#ibcon#end of sib2, iclass 4, count 0 2006.285.11:14:35.95#ibcon#*after write, iclass 4, count 0 2006.285.11:14:35.95#ibcon#*before return 0, iclass 4, count 0 2006.285.11:14:35.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:14:35.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:14:35.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:14:35.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:14:35.95$vck44/valo=4,624.99 2006.285.11:14:35.95#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.11:14:35.95#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.11:14:35.95#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:35.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:14:35.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:14:35.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:14:35.95#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:14:35.95#ibcon#first serial, iclass 6, count 0 2006.285.11:14:35.95#ibcon#enter sib2, iclass 6, count 0 2006.285.11:14:35.95#ibcon#flushed, iclass 6, count 0 2006.285.11:14:35.95#ibcon#about to write, iclass 6, count 0 2006.285.11:14:35.95#ibcon#wrote, iclass 6, count 0 2006.285.11:14:35.95#ibcon#about to read 3, iclass 6, count 0 2006.285.11:14:35.97#ibcon#read 3, iclass 6, count 0 2006.285.11:14:35.97#ibcon#about to read 4, iclass 6, count 0 2006.285.11:14:35.97#ibcon#read 4, iclass 6, count 0 2006.285.11:14:35.97#ibcon#about to read 5, iclass 6, count 0 2006.285.11:14:35.97#ibcon#read 5, iclass 6, count 0 2006.285.11:14:35.97#ibcon#about to read 6, iclass 6, count 0 2006.285.11:14:35.97#ibcon#read 6, iclass 6, count 0 2006.285.11:14:35.97#ibcon#end of sib2, iclass 6, count 0 2006.285.11:14:35.97#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:14:35.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:14:35.97#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:14:35.97#ibcon#*before write, iclass 6, count 0 2006.285.11:14:35.97#ibcon#enter sib2, iclass 6, count 0 2006.285.11:14:35.97#ibcon#flushed, iclass 6, count 0 2006.285.11:14:35.97#ibcon#about to write, iclass 6, count 0 2006.285.11:14:35.97#ibcon#wrote, iclass 6, count 0 2006.285.11:14:35.97#ibcon#about to read 3, iclass 6, count 0 2006.285.11:14:36.01#ibcon#read 3, iclass 6, count 0 2006.285.11:14:36.01#ibcon#about to read 4, iclass 6, count 0 2006.285.11:14:36.01#ibcon#read 4, iclass 6, count 0 2006.285.11:14:36.01#ibcon#about to read 5, iclass 6, count 0 2006.285.11:14:36.01#ibcon#read 5, iclass 6, count 0 2006.285.11:14:36.01#ibcon#about to read 6, iclass 6, count 0 2006.285.11:14:36.01#ibcon#read 6, iclass 6, count 0 2006.285.11:14:36.01#ibcon#end of sib2, iclass 6, count 0 2006.285.11:14:36.01#ibcon#*after write, iclass 6, count 0 2006.285.11:14:36.01#ibcon#*before return 0, iclass 6, count 0 2006.285.11:14:36.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:14:36.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:14:36.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:14:36.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:14:36.01$vck44/va=4,6 2006.285.11:14:36.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.11:14:36.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.11:14:36.01#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:36.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:14:36.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:14:36.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:14:36.07#ibcon#enter wrdev, iclass 10, count 2 2006.285.11:14:36.07#ibcon#first serial, iclass 10, count 2 2006.285.11:14:36.07#ibcon#enter sib2, iclass 10, count 2 2006.285.11:14:36.07#ibcon#flushed, iclass 10, count 2 2006.285.11:14:36.07#ibcon#about to write, iclass 10, count 2 2006.285.11:14:36.07#ibcon#wrote, iclass 10, count 2 2006.285.11:14:36.07#ibcon#about to read 3, iclass 10, count 2 2006.285.11:14:36.09#ibcon#read 3, iclass 10, count 2 2006.285.11:14:36.09#ibcon#about to read 4, iclass 10, count 2 2006.285.11:14:36.09#ibcon#read 4, iclass 10, count 2 2006.285.11:14:36.09#ibcon#about to read 5, iclass 10, count 2 2006.285.11:14:36.09#ibcon#read 5, iclass 10, count 2 2006.285.11:14:36.09#ibcon#about to read 6, iclass 10, count 2 2006.285.11:14:36.09#ibcon#read 6, iclass 10, count 2 2006.285.11:14:36.09#ibcon#end of sib2, iclass 10, count 2 2006.285.11:14:36.09#ibcon#*mode == 0, iclass 10, count 2 2006.285.11:14:36.09#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.11:14:36.09#ibcon#[25=AT04-06\r\n] 2006.285.11:14:36.09#ibcon#*before write, iclass 10, count 2 2006.285.11:14:36.09#ibcon#enter sib2, iclass 10, count 2 2006.285.11:14:36.09#ibcon#flushed, iclass 10, count 2 2006.285.11:14:36.09#ibcon#about to write, iclass 10, count 2 2006.285.11:14:36.09#ibcon#wrote, iclass 10, count 2 2006.285.11:14:36.09#ibcon#about to read 3, iclass 10, count 2 2006.285.11:14:36.12#ibcon#read 3, iclass 10, count 2 2006.285.11:14:36.12#ibcon#about to read 4, iclass 10, count 2 2006.285.11:14:36.12#ibcon#read 4, iclass 10, count 2 2006.285.11:14:36.12#ibcon#about to read 5, iclass 10, count 2 2006.285.11:14:36.12#ibcon#read 5, iclass 10, count 2 2006.285.11:14:36.12#ibcon#about to read 6, iclass 10, count 2 2006.285.11:14:36.12#ibcon#read 6, iclass 10, count 2 2006.285.11:14:36.12#ibcon#end of sib2, iclass 10, count 2 2006.285.11:14:36.12#ibcon#*after write, iclass 10, count 2 2006.285.11:14:36.12#ibcon#*before return 0, iclass 10, count 2 2006.285.11:14:36.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:14:36.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:14:36.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.11:14:36.12#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:36.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:14:36.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:14:36.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:14:36.24#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:14:36.24#ibcon#first serial, iclass 10, count 0 2006.285.11:14:36.24#ibcon#enter sib2, iclass 10, count 0 2006.285.11:14:36.24#ibcon#flushed, iclass 10, count 0 2006.285.11:14:36.24#ibcon#about to write, iclass 10, count 0 2006.285.11:14:36.24#ibcon#wrote, iclass 10, count 0 2006.285.11:14:36.24#ibcon#about to read 3, iclass 10, count 0 2006.285.11:14:36.26#ibcon#read 3, iclass 10, count 0 2006.285.11:14:36.26#ibcon#about to read 4, iclass 10, count 0 2006.285.11:14:36.26#ibcon#read 4, iclass 10, count 0 2006.285.11:14:36.26#ibcon#about to read 5, iclass 10, count 0 2006.285.11:14:36.26#ibcon#read 5, iclass 10, count 0 2006.285.11:14:36.26#ibcon#about to read 6, iclass 10, count 0 2006.285.11:14:36.26#ibcon#read 6, iclass 10, count 0 2006.285.11:14:36.26#ibcon#end of sib2, iclass 10, count 0 2006.285.11:14:36.26#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:14:36.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:14:36.26#ibcon#[25=USB\r\n] 2006.285.11:14:36.26#ibcon#*before write, iclass 10, count 0 2006.285.11:14:36.26#ibcon#enter sib2, iclass 10, count 0 2006.285.11:14:36.26#ibcon#flushed, iclass 10, count 0 2006.285.11:14:36.26#ibcon#about to write, iclass 10, count 0 2006.285.11:14:36.26#ibcon#wrote, iclass 10, count 0 2006.285.11:14:36.26#ibcon#about to read 3, iclass 10, count 0 2006.285.11:14:36.29#ibcon#read 3, iclass 10, count 0 2006.285.11:14:36.29#ibcon#about to read 4, iclass 10, count 0 2006.285.11:14:36.29#ibcon#read 4, iclass 10, count 0 2006.285.11:14:36.29#ibcon#about to read 5, iclass 10, count 0 2006.285.11:14:36.29#ibcon#read 5, iclass 10, count 0 2006.285.11:14:36.29#ibcon#about to read 6, iclass 10, count 0 2006.285.11:14:36.29#ibcon#read 6, iclass 10, count 0 2006.285.11:14:36.29#ibcon#end of sib2, iclass 10, count 0 2006.285.11:14:36.29#ibcon#*after write, iclass 10, count 0 2006.285.11:14:36.29#ibcon#*before return 0, iclass 10, count 0 2006.285.11:14:36.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:14:36.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:14:36.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:14:36.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:14:36.29$vck44/valo=5,734.99 2006.285.11:14:36.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.11:14:36.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.11:14:36.29#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:36.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:14:36.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:14:36.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:14:36.29#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:14:36.29#ibcon#first serial, iclass 12, count 0 2006.285.11:14:36.29#ibcon#enter sib2, iclass 12, count 0 2006.285.11:14:36.29#ibcon#flushed, iclass 12, count 0 2006.285.11:14:36.29#ibcon#about to write, iclass 12, count 0 2006.285.11:14:36.29#ibcon#wrote, iclass 12, count 0 2006.285.11:14:36.29#ibcon#about to read 3, iclass 12, count 0 2006.285.11:14:36.31#ibcon#read 3, iclass 12, count 0 2006.285.11:14:36.31#ibcon#about to read 4, iclass 12, count 0 2006.285.11:14:36.31#ibcon#read 4, iclass 12, count 0 2006.285.11:14:36.31#ibcon#about to read 5, iclass 12, count 0 2006.285.11:14:36.31#ibcon#read 5, iclass 12, count 0 2006.285.11:14:36.31#ibcon#about to read 6, iclass 12, count 0 2006.285.11:14:36.31#ibcon#read 6, iclass 12, count 0 2006.285.11:14:36.31#ibcon#end of sib2, iclass 12, count 0 2006.285.11:14:36.31#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:14:36.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:14:36.31#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:14:36.31#ibcon#*before write, iclass 12, count 0 2006.285.11:14:36.31#ibcon#enter sib2, iclass 12, count 0 2006.285.11:14:36.31#ibcon#flushed, iclass 12, count 0 2006.285.11:14:36.31#ibcon#about to write, iclass 12, count 0 2006.285.11:14:36.31#ibcon#wrote, iclass 12, count 0 2006.285.11:14:36.31#ibcon#about to read 3, iclass 12, count 0 2006.285.11:14:36.35#ibcon#read 3, iclass 12, count 0 2006.285.11:14:36.35#ibcon#about to read 4, iclass 12, count 0 2006.285.11:14:36.35#ibcon#read 4, iclass 12, count 0 2006.285.11:14:36.35#ibcon#about to read 5, iclass 12, count 0 2006.285.11:14:36.35#ibcon#read 5, iclass 12, count 0 2006.285.11:14:36.35#ibcon#about to read 6, iclass 12, count 0 2006.285.11:14:36.35#ibcon#read 6, iclass 12, count 0 2006.285.11:14:36.35#ibcon#end of sib2, iclass 12, count 0 2006.285.11:14:36.35#ibcon#*after write, iclass 12, count 0 2006.285.11:14:36.35#ibcon#*before return 0, iclass 12, count 0 2006.285.11:14:36.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:14:36.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:14:36.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:14:36.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:14:36.35$vck44/va=5,3 2006.285.11:14:36.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.11:14:36.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.11:14:36.35#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:36.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:14:36.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:14:36.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:14:36.41#ibcon#enter wrdev, iclass 14, count 2 2006.285.11:14:36.41#ibcon#first serial, iclass 14, count 2 2006.285.11:14:36.41#ibcon#enter sib2, iclass 14, count 2 2006.285.11:14:36.41#ibcon#flushed, iclass 14, count 2 2006.285.11:14:36.41#ibcon#about to write, iclass 14, count 2 2006.285.11:14:36.41#ibcon#wrote, iclass 14, count 2 2006.285.11:14:36.41#ibcon#about to read 3, iclass 14, count 2 2006.285.11:14:36.43#ibcon#read 3, iclass 14, count 2 2006.285.11:14:36.43#ibcon#about to read 4, iclass 14, count 2 2006.285.11:14:36.43#ibcon#read 4, iclass 14, count 2 2006.285.11:14:36.43#ibcon#about to read 5, iclass 14, count 2 2006.285.11:14:36.43#ibcon#read 5, iclass 14, count 2 2006.285.11:14:36.43#ibcon#about to read 6, iclass 14, count 2 2006.285.11:14:36.43#ibcon#read 6, iclass 14, count 2 2006.285.11:14:36.43#ibcon#end of sib2, iclass 14, count 2 2006.285.11:14:36.43#ibcon#*mode == 0, iclass 14, count 2 2006.285.11:14:36.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.11:14:36.43#ibcon#[25=AT05-03\r\n] 2006.285.11:14:36.43#ibcon#*before write, iclass 14, count 2 2006.285.11:14:36.43#ibcon#enter sib2, iclass 14, count 2 2006.285.11:14:36.43#ibcon#flushed, iclass 14, count 2 2006.285.11:14:36.43#ibcon#about to write, iclass 14, count 2 2006.285.11:14:36.43#ibcon#wrote, iclass 14, count 2 2006.285.11:14:36.43#ibcon#about to read 3, iclass 14, count 2 2006.285.11:14:36.46#ibcon#read 3, iclass 14, count 2 2006.285.11:14:36.46#ibcon#about to read 4, iclass 14, count 2 2006.285.11:14:36.46#ibcon#read 4, iclass 14, count 2 2006.285.11:14:36.46#ibcon#about to read 5, iclass 14, count 2 2006.285.11:14:36.46#ibcon#read 5, iclass 14, count 2 2006.285.11:14:36.46#ibcon#about to read 6, iclass 14, count 2 2006.285.11:14:36.46#ibcon#read 6, iclass 14, count 2 2006.285.11:14:36.46#ibcon#end of sib2, iclass 14, count 2 2006.285.11:14:36.46#ibcon#*after write, iclass 14, count 2 2006.285.11:14:36.46#ibcon#*before return 0, iclass 14, count 2 2006.285.11:14:36.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:14:36.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:14:36.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.11:14:36.46#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:36.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:14:36.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:14:36.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:14:36.58#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:14:36.58#ibcon#first serial, iclass 14, count 0 2006.285.11:14:36.58#ibcon#enter sib2, iclass 14, count 0 2006.285.11:14:36.58#ibcon#flushed, iclass 14, count 0 2006.285.11:14:36.58#ibcon#about to write, iclass 14, count 0 2006.285.11:14:36.58#ibcon#wrote, iclass 14, count 0 2006.285.11:14:36.58#ibcon#about to read 3, iclass 14, count 0 2006.285.11:14:36.60#ibcon#read 3, iclass 14, count 0 2006.285.11:14:36.60#ibcon#about to read 4, iclass 14, count 0 2006.285.11:14:36.60#ibcon#read 4, iclass 14, count 0 2006.285.11:14:36.60#ibcon#about to read 5, iclass 14, count 0 2006.285.11:14:36.60#ibcon#read 5, iclass 14, count 0 2006.285.11:14:36.60#ibcon#about to read 6, iclass 14, count 0 2006.285.11:14:36.60#ibcon#read 6, iclass 14, count 0 2006.285.11:14:36.60#ibcon#end of sib2, iclass 14, count 0 2006.285.11:14:36.60#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:14:36.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:14:36.60#ibcon#[25=USB\r\n] 2006.285.11:14:36.60#ibcon#*before write, iclass 14, count 0 2006.285.11:14:36.60#ibcon#enter sib2, iclass 14, count 0 2006.285.11:14:36.60#ibcon#flushed, iclass 14, count 0 2006.285.11:14:36.60#ibcon#about to write, iclass 14, count 0 2006.285.11:14:36.60#ibcon#wrote, iclass 14, count 0 2006.285.11:14:36.60#ibcon#about to read 3, iclass 14, count 0 2006.285.11:14:36.63#ibcon#read 3, iclass 14, count 0 2006.285.11:14:36.63#ibcon#about to read 4, iclass 14, count 0 2006.285.11:14:36.63#ibcon#read 4, iclass 14, count 0 2006.285.11:14:36.63#ibcon#about to read 5, iclass 14, count 0 2006.285.11:14:36.63#ibcon#read 5, iclass 14, count 0 2006.285.11:14:36.63#ibcon#about to read 6, iclass 14, count 0 2006.285.11:14:36.63#ibcon#read 6, iclass 14, count 0 2006.285.11:14:36.63#ibcon#end of sib2, iclass 14, count 0 2006.285.11:14:36.63#ibcon#*after write, iclass 14, count 0 2006.285.11:14:36.63#ibcon#*before return 0, iclass 14, count 0 2006.285.11:14:36.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:14:36.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:14:36.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:14:36.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:14:36.63$vck44/valo=6,814.99 2006.285.11:14:36.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.11:14:36.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.11:14:36.63#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:36.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:14:36.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:14:36.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:14:36.63#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:14:36.63#ibcon#first serial, iclass 16, count 0 2006.285.11:14:36.63#ibcon#enter sib2, iclass 16, count 0 2006.285.11:14:36.63#ibcon#flushed, iclass 16, count 0 2006.285.11:14:36.63#ibcon#about to write, iclass 16, count 0 2006.285.11:14:36.63#ibcon#wrote, iclass 16, count 0 2006.285.11:14:36.63#ibcon#about to read 3, iclass 16, count 0 2006.285.11:14:36.65#ibcon#read 3, iclass 16, count 0 2006.285.11:14:36.65#ibcon#about to read 4, iclass 16, count 0 2006.285.11:14:36.65#ibcon#read 4, iclass 16, count 0 2006.285.11:14:36.65#ibcon#about to read 5, iclass 16, count 0 2006.285.11:14:36.65#ibcon#read 5, iclass 16, count 0 2006.285.11:14:36.65#ibcon#about to read 6, iclass 16, count 0 2006.285.11:14:36.65#ibcon#read 6, iclass 16, count 0 2006.285.11:14:36.65#ibcon#end of sib2, iclass 16, count 0 2006.285.11:14:36.65#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:14:36.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:14:36.65#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:14:36.65#ibcon#*before write, iclass 16, count 0 2006.285.11:14:36.65#ibcon#enter sib2, iclass 16, count 0 2006.285.11:14:36.65#ibcon#flushed, iclass 16, count 0 2006.285.11:14:36.65#ibcon#about to write, iclass 16, count 0 2006.285.11:14:36.65#ibcon#wrote, iclass 16, count 0 2006.285.11:14:36.65#ibcon#about to read 3, iclass 16, count 0 2006.285.11:14:36.69#ibcon#read 3, iclass 16, count 0 2006.285.11:14:36.69#ibcon#about to read 4, iclass 16, count 0 2006.285.11:14:36.69#ibcon#read 4, iclass 16, count 0 2006.285.11:14:36.69#ibcon#about to read 5, iclass 16, count 0 2006.285.11:14:36.69#ibcon#read 5, iclass 16, count 0 2006.285.11:14:36.69#ibcon#about to read 6, iclass 16, count 0 2006.285.11:14:36.69#ibcon#read 6, iclass 16, count 0 2006.285.11:14:36.69#ibcon#end of sib2, iclass 16, count 0 2006.285.11:14:36.69#ibcon#*after write, iclass 16, count 0 2006.285.11:14:36.69#ibcon#*before return 0, iclass 16, count 0 2006.285.11:14:36.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:14:36.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:14:36.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:14:36.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:14:36.69$vck44/va=6,4 2006.285.11:14:36.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.11:14:36.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.11:14:36.69#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:36.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:14:36.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:14:36.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:14:36.75#ibcon#enter wrdev, iclass 18, count 2 2006.285.11:14:36.75#ibcon#first serial, iclass 18, count 2 2006.285.11:14:36.75#ibcon#enter sib2, iclass 18, count 2 2006.285.11:14:36.75#ibcon#flushed, iclass 18, count 2 2006.285.11:14:36.75#ibcon#about to write, iclass 18, count 2 2006.285.11:14:36.75#ibcon#wrote, iclass 18, count 2 2006.285.11:14:36.75#ibcon#about to read 3, iclass 18, count 2 2006.285.11:14:36.77#ibcon#read 3, iclass 18, count 2 2006.285.11:14:36.77#ibcon#about to read 4, iclass 18, count 2 2006.285.11:14:36.77#ibcon#read 4, iclass 18, count 2 2006.285.11:14:36.77#ibcon#about to read 5, iclass 18, count 2 2006.285.11:14:36.77#ibcon#read 5, iclass 18, count 2 2006.285.11:14:36.77#ibcon#about to read 6, iclass 18, count 2 2006.285.11:14:36.77#ibcon#read 6, iclass 18, count 2 2006.285.11:14:36.77#ibcon#end of sib2, iclass 18, count 2 2006.285.11:14:36.77#ibcon#*mode == 0, iclass 18, count 2 2006.285.11:14:36.77#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.11:14:36.77#ibcon#[25=AT06-04\r\n] 2006.285.11:14:36.77#ibcon#*before write, iclass 18, count 2 2006.285.11:14:36.77#ibcon#enter sib2, iclass 18, count 2 2006.285.11:14:36.77#ibcon#flushed, iclass 18, count 2 2006.285.11:14:36.77#ibcon#about to write, iclass 18, count 2 2006.285.11:14:36.77#ibcon#wrote, iclass 18, count 2 2006.285.11:14:36.77#ibcon#about to read 3, iclass 18, count 2 2006.285.11:14:36.80#ibcon#read 3, iclass 18, count 2 2006.285.11:14:36.80#ibcon#about to read 4, iclass 18, count 2 2006.285.11:14:36.80#ibcon#read 4, iclass 18, count 2 2006.285.11:14:36.80#ibcon#about to read 5, iclass 18, count 2 2006.285.11:14:36.80#ibcon#read 5, iclass 18, count 2 2006.285.11:14:36.80#ibcon#about to read 6, iclass 18, count 2 2006.285.11:14:36.80#ibcon#read 6, iclass 18, count 2 2006.285.11:14:36.80#ibcon#end of sib2, iclass 18, count 2 2006.285.11:14:36.80#ibcon#*after write, iclass 18, count 2 2006.285.11:14:36.80#ibcon#*before return 0, iclass 18, count 2 2006.285.11:14:36.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:14:36.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:14:36.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.11:14:36.80#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:36.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:14:36.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:14:36.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:14:36.92#ibcon#enter wrdev, iclass 18, count 0 2006.285.11:14:36.92#ibcon#first serial, iclass 18, count 0 2006.285.11:14:36.92#ibcon#enter sib2, iclass 18, count 0 2006.285.11:14:36.92#ibcon#flushed, iclass 18, count 0 2006.285.11:14:36.92#ibcon#about to write, iclass 18, count 0 2006.285.11:14:36.92#ibcon#wrote, iclass 18, count 0 2006.285.11:14:36.92#ibcon#about to read 3, iclass 18, count 0 2006.285.11:14:36.94#ibcon#read 3, iclass 18, count 0 2006.285.11:14:36.94#ibcon#about to read 4, iclass 18, count 0 2006.285.11:14:36.94#ibcon#read 4, iclass 18, count 0 2006.285.11:14:36.94#ibcon#about to read 5, iclass 18, count 0 2006.285.11:14:36.94#ibcon#read 5, iclass 18, count 0 2006.285.11:14:36.94#ibcon#about to read 6, iclass 18, count 0 2006.285.11:14:36.94#ibcon#read 6, iclass 18, count 0 2006.285.11:14:36.94#ibcon#end of sib2, iclass 18, count 0 2006.285.11:14:36.94#ibcon#*mode == 0, iclass 18, count 0 2006.285.11:14:36.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.11:14:36.94#ibcon#[25=USB\r\n] 2006.285.11:14:36.94#ibcon#*before write, iclass 18, count 0 2006.285.11:14:36.94#ibcon#enter sib2, iclass 18, count 0 2006.285.11:14:36.94#ibcon#flushed, iclass 18, count 0 2006.285.11:14:36.94#ibcon#about to write, iclass 18, count 0 2006.285.11:14:36.94#ibcon#wrote, iclass 18, count 0 2006.285.11:14:36.94#ibcon#about to read 3, iclass 18, count 0 2006.285.11:14:36.97#ibcon#read 3, iclass 18, count 0 2006.285.11:14:36.97#ibcon#about to read 4, iclass 18, count 0 2006.285.11:14:36.97#ibcon#read 4, iclass 18, count 0 2006.285.11:14:36.97#ibcon#about to read 5, iclass 18, count 0 2006.285.11:14:36.97#ibcon#read 5, iclass 18, count 0 2006.285.11:14:36.97#ibcon#about to read 6, iclass 18, count 0 2006.285.11:14:36.97#ibcon#read 6, iclass 18, count 0 2006.285.11:14:36.97#ibcon#end of sib2, iclass 18, count 0 2006.285.11:14:36.97#ibcon#*after write, iclass 18, count 0 2006.285.11:14:36.97#ibcon#*before return 0, iclass 18, count 0 2006.285.11:14:36.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:14:36.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:14:36.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.11:14:36.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.11:14:36.97$vck44/valo=7,864.99 2006.285.11:14:36.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.11:14:36.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.11:14:36.97#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:36.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:14:36.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:14:36.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:14:36.97#ibcon#enter wrdev, iclass 20, count 0 2006.285.11:14:36.97#ibcon#first serial, iclass 20, count 0 2006.285.11:14:36.97#ibcon#enter sib2, iclass 20, count 0 2006.285.11:14:36.97#ibcon#flushed, iclass 20, count 0 2006.285.11:14:36.97#ibcon#about to write, iclass 20, count 0 2006.285.11:14:36.97#ibcon#wrote, iclass 20, count 0 2006.285.11:14:36.97#ibcon#about to read 3, iclass 20, count 0 2006.285.11:14:36.99#ibcon#read 3, iclass 20, count 0 2006.285.11:14:36.99#ibcon#about to read 4, iclass 20, count 0 2006.285.11:14:36.99#ibcon#read 4, iclass 20, count 0 2006.285.11:14:36.99#ibcon#about to read 5, iclass 20, count 0 2006.285.11:14:36.99#ibcon#read 5, iclass 20, count 0 2006.285.11:14:36.99#ibcon#about to read 6, iclass 20, count 0 2006.285.11:14:36.99#ibcon#read 6, iclass 20, count 0 2006.285.11:14:36.99#ibcon#end of sib2, iclass 20, count 0 2006.285.11:14:36.99#ibcon#*mode == 0, iclass 20, count 0 2006.285.11:14:36.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.11:14:36.99#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:14:36.99#ibcon#*before write, iclass 20, count 0 2006.285.11:14:36.99#ibcon#enter sib2, iclass 20, count 0 2006.285.11:14:36.99#ibcon#flushed, iclass 20, count 0 2006.285.11:14:36.99#ibcon#about to write, iclass 20, count 0 2006.285.11:14:36.99#ibcon#wrote, iclass 20, count 0 2006.285.11:14:36.99#ibcon#about to read 3, iclass 20, count 0 2006.285.11:14:37.03#ibcon#read 3, iclass 20, count 0 2006.285.11:14:37.03#ibcon#about to read 4, iclass 20, count 0 2006.285.11:14:37.03#ibcon#read 4, iclass 20, count 0 2006.285.11:14:37.03#ibcon#about to read 5, iclass 20, count 0 2006.285.11:14:37.03#ibcon#read 5, iclass 20, count 0 2006.285.11:14:37.03#ibcon#about to read 6, iclass 20, count 0 2006.285.11:14:37.03#ibcon#read 6, iclass 20, count 0 2006.285.11:14:37.03#ibcon#end of sib2, iclass 20, count 0 2006.285.11:14:37.03#ibcon#*after write, iclass 20, count 0 2006.285.11:14:37.03#ibcon#*before return 0, iclass 20, count 0 2006.285.11:14:37.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:14:37.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:14:37.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.11:14:37.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.11:14:37.03$vck44/va=7,4 2006.285.11:14:37.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.11:14:37.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.11:14:37.03#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:37.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:14:37.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:14:37.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:14:37.09#ibcon#enter wrdev, iclass 22, count 2 2006.285.11:14:37.09#ibcon#first serial, iclass 22, count 2 2006.285.11:14:37.09#ibcon#enter sib2, iclass 22, count 2 2006.285.11:14:37.09#ibcon#flushed, iclass 22, count 2 2006.285.11:14:37.09#ibcon#about to write, iclass 22, count 2 2006.285.11:14:37.09#ibcon#wrote, iclass 22, count 2 2006.285.11:14:37.09#ibcon#about to read 3, iclass 22, count 2 2006.285.11:14:37.11#ibcon#read 3, iclass 22, count 2 2006.285.11:14:37.11#ibcon#about to read 4, iclass 22, count 2 2006.285.11:14:37.11#ibcon#read 4, iclass 22, count 2 2006.285.11:14:37.11#ibcon#about to read 5, iclass 22, count 2 2006.285.11:14:37.11#ibcon#read 5, iclass 22, count 2 2006.285.11:14:37.11#ibcon#about to read 6, iclass 22, count 2 2006.285.11:14:37.11#ibcon#read 6, iclass 22, count 2 2006.285.11:14:37.11#ibcon#end of sib2, iclass 22, count 2 2006.285.11:14:37.11#ibcon#*mode == 0, iclass 22, count 2 2006.285.11:14:37.11#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.11:14:37.11#ibcon#[25=AT07-04\r\n] 2006.285.11:14:37.11#ibcon#*before write, iclass 22, count 2 2006.285.11:14:37.11#ibcon#enter sib2, iclass 22, count 2 2006.285.11:14:37.11#ibcon#flushed, iclass 22, count 2 2006.285.11:14:37.11#ibcon#about to write, iclass 22, count 2 2006.285.11:14:37.11#ibcon#wrote, iclass 22, count 2 2006.285.11:14:37.11#ibcon#about to read 3, iclass 22, count 2 2006.285.11:14:37.14#ibcon#read 3, iclass 22, count 2 2006.285.11:14:37.14#ibcon#about to read 4, iclass 22, count 2 2006.285.11:14:37.14#ibcon#read 4, iclass 22, count 2 2006.285.11:14:37.14#ibcon#about to read 5, iclass 22, count 2 2006.285.11:14:37.14#ibcon#read 5, iclass 22, count 2 2006.285.11:14:37.14#ibcon#about to read 6, iclass 22, count 2 2006.285.11:14:37.14#ibcon#read 6, iclass 22, count 2 2006.285.11:14:37.14#ibcon#end of sib2, iclass 22, count 2 2006.285.11:14:37.14#ibcon#*after write, iclass 22, count 2 2006.285.11:14:37.14#ibcon#*before return 0, iclass 22, count 2 2006.285.11:14:37.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:14:37.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:14:37.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.11:14:37.14#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:37.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:14:37.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:14:37.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:14:37.26#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:14:37.26#ibcon#first serial, iclass 22, count 0 2006.285.11:14:37.26#ibcon#enter sib2, iclass 22, count 0 2006.285.11:14:37.26#ibcon#flushed, iclass 22, count 0 2006.285.11:14:37.26#ibcon#about to write, iclass 22, count 0 2006.285.11:14:37.26#ibcon#wrote, iclass 22, count 0 2006.285.11:14:37.26#ibcon#about to read 3, iclass 22, count 0 2006.285.11:14:37.28#ibcon#read 3, iclass 22, count 0 2006.285.11:14:37.28#ibcon#about to read 4, iclass 22, count 0 2006.285.11:14:37.28#ibcon#read 4, iclass 22, count 0 2006.285.11:14:37.28#ibcon#about to read 5, iclass 22, count 0 2006.285.11:14:37.28#ibcon#read 5, iclass 22, count 0 2006.285.11:14:37.28#ibcon#about to read 6, iclass 22, count 0 2006.285.11:14:37.28#ibcon#read 6, iclass 22, count 0 2006.285.11:14:37.28#ibcon#end of sib2, iclass 22, count 0 2006.285.11:14:37.28#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:14:37.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:14:37.28#ibcon#[25=USB\r\n] 2006.285.11:14:37.28#ibcon#*before write, iclass 22, count 0 2006.285.11:14:37.28#ibcon#enter sib2, iclass 22, count 0 2006.285.11:14:37.28#ibcon#flushed, iclass 22, count 0 2006.285.11:14:37.28#ibcon#about to write, iclass 22, count 0 2006.285.11:14:37.28#ibcon#wrote, iclass 22, count 0 2006.285.11:14:37.28#ibcon#about to read 3, iclass 22, count 0 2006.285.11:14:37.31#ibcon#read 3, iclass 22, count 0 2006.285.11:14:37.31#ibcon#about to read 4, iclass 22, count 0 2006.285.11:14:37.31#ibcon#read 4, iclass 22, count 0 2006.285.11:14:37.31#ibcon#about to read 5, iclass 22, count 0 2006.285.11:14:37.31#ibcon#read 5, iclass 22, count 0 2006.285.11:14:37.31#ibcon#about to read 6, iclass 22, count 0 2006.285.11:14:37.31#ibcon#read 6, iclass 22, count 0 2006.285.11:14:37.31#ibcon#end of sib2, iclass 22, count 0 2006.285.11:14:37.31#ibcon#*after write, iclass 22, count 0 2006.285.11:14:37.31#ibcon#*before return 0, iclass 22, count 0 2006.285.11:14:37.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:14:37.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:14:37.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:14:37.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:14:37.31$vck44/valo=8,884.99 2006.285.11:14:37.31#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.11:14:37.31#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.11:14:37.31#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:37.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:14:37.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:14:37.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:14:37.31#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:14:37.31#ibcon#first serial, iclass 24, count 0 2006.285.11:14:37.31#ibcon#enter sib2, iclass 24, count 0 2006.285.11:14:37.31#ibcon#flushed, iclass 24, count 0 2006.285.11:14:37.31#ibcon#about to write, iclass 24, count 0 2006.285.11:14:37.31#ibcon#wrote, iclass 24, count 0 2006.285.11:14:37.31#ibcon#about to read 3, iclass 24, count 0 2006.285.11:14:37.33#ibcon#read 3, iclass 24, count 0 2006.285.11:14:37.33#ibcon#about to read 4, iclass 24, count 0 2006.285.11:14:37.33#ibcon#read 4, iclass 24, count 0 2006.285.11:14:37.33#ibcon#about to read 5, iclass 24, count 0 2006.285.11:14:37.33#ibcon#read 5, iclass 24, count 0 2006.285.11:14:37.33#ibcon#about to read 6, iclass 24, count 0 2006.285.11:14:37.33#ibcon#read 6, iclass 24, count 0 2006.285.11:14:37.33#ibcon#end of sib2, iclass 24, count 0 2006.285.11:14:37.33#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:14:37.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:14:37.33#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:14:37.33#ibcon#*before write, iclass 24, count 0 2006.285.11:14:37.33#ibcon#enter sib2, iclass 24, count 0 2006.285.11:14:37.33#ibcon#flushed, iclass 24, count 0 2006.285.11:14:37.33#ibcon#about to write, iclass 24, count 0 2006.285.11:14:37.33#ibcon#wrote, iclass 24, count 0 2006.285.11:14:37.33#ibcon#about to read 3, iclass 24, count 0 2006.285.11:14:37.37#ibcon#read 3, iclass 24, count 0 2006.285.11:14:37.37#ibcon#about to read 4, iclass 24, count 0 2006.285.11:14:37.37#ibcon#read 4, iclass 24, count 0 2006.285.11:14:37.37#ibcon#about to read 5, iclass 24, count 0 2006.285.11:14:37.37#ibcon#read 5, iclass 24, count 0 2006.285.11:14:37.37#ibcon#about to read 6, iclass 24, count 0 2006.285.11:14:37.37#ibcon#read 6, iclass 24, count 0 2006.285.11:14:37.37#ibcon#end of sib2, iclass 24, count 0 2006.285.11:14:37.37#ibcon#*after write, iclass 24, count 0 2006.285.11:14:37.37#ibcon#*before return 0, iclass 24, count 0 2006.285.11:14:37.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:14:37.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:14:37.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:14:37.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:14:37.37$vck44/va=8,3 2006.285.11:14:37.37#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.11:14:37.37#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.11:14:37.37#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:37.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:14:37.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:14:37.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:14:37.43#ibcon#enter wrdev, iclass 26, count 2 2006.285.11:14:37.43#ibcon#first serial, iclass 26, count 2 2006.285.11:14:37.43#ibcon#enter sib2, iclass 26, count 2 2006.285.11:14:37.43#ibcon#flushed, iclass 26, count 2 2006.285.11:14:37.43#ibcon#about to write, iclass 26, count 2 2006.285.11:14:37.43#ibcon#wrote, iclass 26, count 2 2006.285.11:14:37.43#ibcon#about to read 3, iclass 26, count 2 2006.285.11:14:37.45#ibcon#read 3, iclass 26, count 2 2006.285.11:14:37.45#ibcon#about to read 4, iclass 26, count 2 2006.285.11:14:37.45#ibcon#read 4, iclass 26, count 2 2006.285.11:14:37.45#ibcon#about to read 5, iclass 26, count 2 2006.285.11:14:37.45#ibcon#read 5, iclass 26, count 2 2006.285.11:14:37.45#ibcon#about to read 6, iclass 26, count 2 2006.285.11:14:37.45#ibcon#read 6, iclass 26, count 2 2006.285.11:14:37.45#ibcon#end of sib2, iclass 26, count 2 2006.285.11:14:37.45#ibcon#*mode == 0, iclass 26, count 2 2006.285.11:14:37.45#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.11:14:37.45#ibcon#[25=AT08-03\r\n] 2006.285.11:14:37.45#ibcon#*before write, iclass 26, count 2 2006.285.11:14:37.45#ibcon#enter sib2, iclass 26, count 2 2006.285.11:14:37.45#ibcon#flushed, iclass 26, count 2 2006.285.11:14:37.45#ibcon#about to write, iclass 26, count 2 2006.285.11:14:37.45#ibcon#wrote, iclass 26, count 2 2006.285.11:14:37.45#ibcon#about to read 3, iclass 26, count 2 2006.285.11:14:37.48#ibcon#read 3, iclass 26, count 2 2006.285.11:14:37.48#ibcon#about to read 4, iclass 26, count 2 2006.285.11:14:37.48#ibcon#read 4, iclass 26, count 2 2006.285.11:14:37.48#ibcon#about to read 5, iclass 26, count 2 2006.285.11:14:37.48#ibcon#read 5, iclass 26, count 2 2006.285.11:14:37.48#ibcon#about to read 6, iclass 26, count 2 2006.285.11:14:37.48#ibcon#read 6, iclass 26, count 2 2006.285.11:14:37.48#ibcon#end of sib2, iclass 26, count 2 2006.285.11:14:37.48#ibcon#*after write, iclass 26, count 2 2006.285.11:14:37.48#ibcon#*before return 0, iclass 26, count 2 2006.285.11:14:37.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:14:37.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:14:37.48#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.11:14:37.48#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:37.48#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:14:37.60#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:14:37.60#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:14:37.60#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:14:37.60#ibcon#first serial, iclass 26, count 0 2006.285.11:14:37.60#ibcon#enter sib2, iclass 26, count 0 2006.285.11:14:37.60#ibcon#flushed, iclass 26, count 0 2006.285.11:14:37.60#ibcon#about to write, iclass 26, count 0 2006.285.11:14:37.60#ibcon#wrote, iclass 26, count 0 2006.285.11:14:37.60#ibcon#about to read 3, iclass 26, count 0 2006.285.11:14:37.62#ibcon#read 3, iclass 26, count 0 2006.285.11:14:37.62#ibcon#about to read 4, iclass 26, count 0 2006.285.11:14:37.62#ibcon#read 4, iclass 26, count 0 2006.285.11:14:37.62#ibcon#about to read 5, iclass 26, count 0 2006.285.11:14:37.62#ibcon#read 5, iclass 26, count 0 2006.285.11:14:37.62#ibcon#about to read 6, iclass 26, count 0 2006.285.11:14:37.62#ibcon#read 6, iclass 26, count 0 2006.285.11:14:37.62#ibcon#end of sib2, iclass 26, count 0 2006.285.11:14:37.62#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:14:37.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:14:37.62#ibcon#[25=USB\r\n] 2006.285.11:14:37.62#ibcon#*before write, iclass 26, count 0 2006.285.11:14:37.62#ibcon#enter sib2, iclass 26, count 0 2006.285.11:14:37.62#ibcon#flushed, iclass 26, count 0 2006.285.11:14:37.62#ibcon#about to write, iclass 26, count 0 2006.285.11:14:37.62#ibcon#wrote, iclass 26, count 0 2006.285.11:14:37.62#ibcon#about to read 3, iclass 26, count 0 2006.285.11:14:37.65#ibcon#read 3, iclass 26, count 0 2006.285.11:14:37.65#ibcon#about to read 4, iclass 26, count 0 2006.285.11:14:37.65#ibcon#read 4, iclass 26, count 0 2006.285.11:14:37.65#ibcon#about to read 5, iclass 26, count 0 2006.285.11:14:37.65#ibcon#read 5, iclass 26, count 0 2006.285.11:14:37.65#ibcon#about to read 6, iclass 26, count 0 2006.285.11:14:37.65#ibcon#read 6, iclass 26, count 0 2006.285.11:14:37.65#ibcon#end of sib2, iclass 26, count 0 2006.285.11:14:37.65#ibcon#*after write, iclass 26, count 0 2006.285.11:14:37.65#ibcon#*before return 0, iclass 26, count 0 2006.285.11:14:37.65#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:14:37.65#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:14:37.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:14:37.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:14:37.65$vck44/vblo=1,629.99 2006.285.11:14:37.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.11:14:37.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.11:14:37.65#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:37.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:14:37.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:14:37.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:14:37.65#ibcon#enter wrdev, iclass 28, count 0 2006.285.11:14:37.65#ibcon#first serial, iclass 28, count 0 2006.285.11:14:37.65#ibcon#enter sib2, iclass 28, count 0 2006.285.11:14:37.65#ibcon#flushed, iclass 28, count 0 2006.285.11:14:37.65#ibcon#about to write, iclass 28, count 0 2006.285.11:14:37.65#ibcon#wrote, iclass 28, count 0 2006.285.11:14:37.65#ibcon#about to read 3, iclass 28, count 0 2006.285.11:14:37.67#ibcon#read 3, iclass 28, count 0 2006.285.11:14:37.67#ibcon#about to read 4, iclass 28, count 0 2006.285.11:14:37.67#ibcon#read 4, iclass 28, count 0 2006.285.11:14:37.67#ibcon#about to read 5, iclass 28, count 0 2006.285.11:14:37.67#ibcon#read 5, iclass 28, count 0 2006.285.11:14:37.67#ibcon#about to read 6, iclass 28, count 0 2006.285.11:14:37.67#ibcon#read 6, iclass 28, count 0 2006.285.11:14:37.67#ibcon#end of sib2, iclass 28, count 0 2006.285.11:14:37.67#ibcon#*mode == 0, iclass 28, count 0 2006.285.11:14:37.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.11:14:37.67#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:14:37.67#ibcon#*before write, iclass 28, count 0 2006.285.11:14:37.67#ibcon#enter sib2, iclass 28, count 0 2006.285.11:14:37.67#ibcon#flushed, iclass 28, count 0 2006.285.11:14:37.67#ibcon#about to write, iclass 28, count 0 2006.285.11:14:37.67#ibcon#wrote, iclass 28, count 0 2006.285.11:14:37.67#ibcon#about to read 3, iclass 28, count 0 2006.285.11:14:37.71#ibcon#read 3, iclass 28, count 0 2006.285.11:14:37.71#ibcon#about to read 4, iclass 28, count 0 2006.285.11:14:37.71#ibcon#read 4, iclass 28, count 0 2006.285.11:14:37.71#ibcon#about to read 5, iclass 28, count 0 2006.285.11:14:37.71#ibcon#read 5, iclass 28, count 0 2006.285.11:14:37.71#ibcon#about to read 6, iclass 28, count 0 2006.285.11:14:37.71#ibcon#read 6, iclass 28, count 0 2006.285.11:14:37.71#ibcon#end of sib2, iclass 28, count 0 2006.285.11:14:37.71#ibcon#*after write, iclass 28, count 0 2006.285.11:14:37.71#ibcon#*before return 0, iclass 28, count 0 2006.285.11:14:37.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:14:37.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:14:37.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.11:14:37.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.11:14:37.71$vck44/vb=1,4 2006.285.11:14:37.71#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.11:14:37.71#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.11:14:37.71#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:37.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:14:37.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:14:37.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:14:37.71#ibcon#enter wrdev, iclass 30, count 2 2006.285.11:14:37.71#ibcon#first serial, iclass 30, count 2 2006.285.11:14:37.71#ibcon#enter sib2, iclass 30, count 2 2006.285.11:14:37.71#ibcon#flushed, iclass 30, count 2 2006.285.11:14:37.71#ibcon#about to write, iclass 30, count 2 2006.285.11:14:37.71#ibcon#wrote, iclass 30, count 2 2006.285.11:14:37.71#ibcon#about to read 3, iclass 30, count 2 2006.285.11:14:37.73#ibcon#read 3, iclass 30, count 2 2006.285.11:14:37.73#ibcon#about to read 4, iclass 30, count 2 2006.285.11:14:37.73#ibcon#read 4, iclass 30, count 2 2006.285.11:14:37.73#ibcon#about to read 5, iclass 30, count 2 2006.285.11:14:37.73#ibcon#read 5, iclass 30, count 2 2006.285.11:14:37.73#ibcon#about to read 6, iclass 30, count 2 2006.285.11:14:37.73#ibcon#read 6, iclass 30, count 2 2006.285.11:14:37.73#ibcon#end of sib2, iclass 30, count 2 2006.285.11:14:37.73#ibcon#*mode == 0, iclass 30, count 2 2006.285.11:14:37.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.11:14:37.73#ibcon#[27=AT01-04\r\n] 2006.285.11:14:37.73#ibcon#*before write, iclass 30, count 2 2006.285.11:14:37.73#ibcon#enter sib2, iclass 30, count 2 2006.285.11:14:37.73#ibcon#flushed, iclass 30, count 2 2006.285.11:14:37.73#ibcon#about to write, iclass 30, count 2 2006.285.11:14:37.73#ibcon#wrote, iclass 30, count 2 2006.285.11:14:37.73#ibcon#about to read 3, iclass 30, count 2 2006.285.11:14:37.76#ibcon#read 3, iclass 30, count 2 2006.285.11:14:37.76#ibcon#about to read 4, iclass 30, count 2 2006.285.11:14:37.76#ibcon#read 4, iclass 30, count 2 2006.285.11:14:37.76#ibcon#about to read 5, iclass 30, count 2 2006.285.11:14:37.76#ibcon#read 5, iclass 30, count 2 2006.285.11:14:37.76#ibcon#about to read 6, iclass 30, count 2 2006.285.11:14:37.76#ibcon#read 6, iclass 30, count 2 2006.285.11:14:37.76#ibcon#end of sib2, iclass 30, count 2 2006.285.11:14:37.76#ibcon#*after write, iclass 30, count 2 2006.285.11:14:37.76#ibcon#*before return 0, iclass 30, count 2 2006.285.11:14:37.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:14:37.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:14:37.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.11:14:37.76#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:37.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:14:37.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:14:37.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:14:37.88#ibcon#enter wrdev, iclass 30, count 0 2006.285.11:14:37.88#ibcon#first serial, iclass 30, count 0 2006.285.11:14:37.88#ibcon#enter sib2, iclass 30, count 0 2006.285.11:14:37.88#ibcon#flushed, iclass 30, count 0 2006.285.11:14:37.88#ibcon#about to write, iclass 30, count 0 2006.285.11:14:37.88#ibcon#wrote, iclass 30, count 0 2006.285.11:14:37.88#ibcon#about to read 3, iclass 30, count 0 2006.285.11:14:37.90#ibcon#read 3, iclass 30, count 0 2006.285.11:14:37.90#ibcon#about to read 4, iclass 30, count 0 2006.285.11:14:37.90#ibcon#read 4, iclass 30, count 0 2006.285.11:14:37.90#ibcon#about to read 5, iclass 30, count 0 2006.285.11:14:37.90#ibcon#read 5, iclass 30, count 0 2006.285.11:14:37.90#ibcon#about to read 6, iclass 30, count 0 2006.285.11:14:37.90#ibcon#read 6, iclass 30, count 0 2006.285.11:14:37.90#ibcon#end of sib2, iclass 30, count 0 2006.285.11:14:37.90#ibcon#*mode == 0, iclass 30, count 0 2006.285.11:14:37.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.11:14:37.90#ibcon#[27=USB\r\n] 2006.285.11:14:37.90#ibcon#*before write, iclass 30, count 0 2006.285.11:14:37.90#ibcon#enter sib2, iclass 30, count 0 2006.285.11:14:37.90#ibcon#flushed, iclass 30, count 0 2006.285.11:14:37.90#ibcon#about to write, iclass 30, count 0 2006.285.11:14:37.90#ibcon#wrote, iclass 30, count 0 2006.285.11:14:37.90#ibcon#about to read 3, iclass 30, count 0 2006.285.11:14:37.93#ibcon#read 3, iclass 30, count 0 2006.285.11:14:37.93#ibcon#about to read 4, iclass 30, count 0 2006.285.11:14:37.93#ibcon#read 4, iclass 30, count 0 2006.285.11:14:37.93#ibcon#about to read 5, iclass 30, count 0 2006.285.11:14:37.93#ibcon#read 5, iclass 30, count 0 2006.285.11:14:37.93#ibcon#about to read 6, iclass 30, count 0 2006.285.11:14:37.93#ibcon#read 6, iclass 30, count 0 2006.285.11:14:37.93#ibcon#end of sib2, iclass 30, count 0 2006.285.11:14:37.93#ibcon#*after write, iclass 30, count 0 2006.285.11:14:37.93#ibcon#*before return 0, iclass 30, count 0 2006.285.11:14:37.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:14:37.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:14:37.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.11:14:37.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.11:14:37.93$vck44/vblo=2,634.99 2006.285.11:14:37.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.11:14:37.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.11:14:37.93#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:37.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:14:37.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:14:37.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:14:37.93#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:14:37.93#ibcon#first serial, iclass 32, count 0 2006.285.11:14:37.93#ibcon#enter sib2, iclass 32, count 0 2006.285.11:14:37.93#ibcon#flushed, iclass 32, count 0 2006.285.11:14:37.93#ibcon#about to write, iclass 32, count 0 2006.285.11:14:37.93#ibcon#wrote, iclass 32, count 0 2006.285.11:14:37.93#ibcon#about to read 3, iclass 32, count 0 2006.285.11:14:37.95#ibcon#read 3, iclass 32, count 0 2006.285.11:14:37.95#ibcon#about to read 4, iclass 32, count 0 2006.285.11:14:37.95#ibcon#read 4, iclass 32, count 0 2006.285.11:14:37.95#ibcon#about to read 5, iclass 32, count 0 2006.285.11:14:37.95#ibcon#read 5, iclass 32, count 0 2006.285.11:14:37.95#ibcon#about to read 6, iclass 32, count 0 2006.285.11:14:37.95#ibcon#read 6, iclass 32, count 0 2006.285.11:14:37.95#ibcon#end of sib2, iclass 32, count 0 2006.285.11:14:37.95#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:14:37.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:14:37.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:14:37.95#ibcon#*before write, iclass 32, count 0 2006.285.11:14:37.95#ibcon#enter sib2, iclass 32, count 0 2006.285.11:14:37.95#ibcon#flushed, iclass 32, count 0 2006.285.11:14:37.95#ibcon#about to write, iclass 32, count 0 2006.285.11:14:37.95#ibcon#wrote, iclass 32, count 0 2006.285.11:14:37.95#ibcon#about to read 3, iclass 32, count 0 2006.285.11:14:37.99#ibcon#read 3, iclass 32, count 0 2006.285.11:14:37.99#ibcon#about to read 4, iclass 32, count 0 2006.285.11:14:37.99#ibcon#read 4, iclass 32, count 0 2006.285.11:14:37.99#ibcon#about to read 5, iclass 32, count 0 2006.285.11:14:37.99#ibcon#read 5, iclass 32, count 0 2006.285.11:14:37.99#ibcon#about to read 6, iclass 32, count 0 2006.285.11:14:37.99#ibcon#read 6, iclass 32, count 0 2006.285.11:14:37.99#ibcon#end of sib2, iclass 32, count 0 2006.285.11:14:37.99#ibcon#*after write, iclass 32, count 0 2006.285.11:14:37.99#ibcon#*before return 0, iclass 32, count 0 2006.285.11:14:37.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:14:37.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:14:37.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:14:37.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:14:37.99$vck44/vb=2,5 2006.285.11:14:37.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.11:14:37.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.11:14:37.99#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:37.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:14:38.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:14:38.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:14:38.05#ibcon#enter wrdev, iclass 34, count 2 2006.285.11:14:38.05#ibcon#first serial, iclass 34, count 2 2006.285.11:14:38.05#ibcon#enter sib2, iclass 34, count 2 2006.285.11:14:38.05#ibcon#flushed, iclass 34, count 2 2006.285.11:14:38.05#ibcon#about to write, iclass 34, count 2 2006.285.11:14:38.05#ibcon#wrote, iclass 34, count 2 2006.285.11:14:38.05#ibcon#about to read 3, iclass 34, count 2 2006.285.11:14:38.07#ibcon#read 3, iclass 34, count 2 2006.285.11:14:38.07#ibcon#about to read 4, iclass 34, count 2 2006.285.11:14:38.07#ibcon#read 4, iclass 34, count 2 2006.285.11:14:38.07#ibcon#about to read 5, iclass 34, count 2 2006.285.11:14:38.07#ibcon#read 5, iclass 34, count 2 2006.285.11:14:38.07#ibcon#about to read 6, iclass 34, count 2 2006.285.11:14:38.07#ibcon#read 6, iclass 34, count 2 2006.285.11:14:38.07#ibcon#end of sib2, iclass 34, count 2 2006.285.11:14:38.07#ibcon#*mode == 0, iclass 34, count 2 2006.285.11:14:38.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.11:14:38.07#ibcon#[27=AT02-05\r\n] 2006.285.11:14:38.07#ibcon#*before write, iclass 34, count 2 2006.285.11:14:38.07#ibcon#enter sib2, iclass 34, count 2 2006.285.11:14:38.07#ibcon#flushed, iclass 34, count 2 2006.285.11:14:38.07#ibcon#about to write, iclass 34, count 2 2006.285.11:14:38.07#ibcon#wrote, iclass 34, count 2 2006.285.11:14:38.07#ibcon#about to read 3, iclass 34, count 2 2006.285.11:14:38.10#ibcon#read 3, iclass 34, count 2 2006.285.11:14:38.10#ibcon#about to read 4, iclass 34, count 2 2006.285.11:14:38.10#ibcon#read 4, iclass 34, count 2 2006.285.11:14:38.10#ibcon#about to read 5, iclass 34, count 2 2006.285.11:14:38.10#ibcon#read 5, iclass 34, count 2 2006.285.11:14:38.10#ibcon#about to read 6, iclass 34, count 2 2006.285.11:14:38.10#ibcon#read 6, iclass 34, count 2 2006.285.11:14:38.10#ibcon#end of sib2, iclass 34, count 2 2006.285.11:14:38.10#ibcon#*after write, iclass 34, count 2 2006.285.11:14:38.10#ibcon#*before return 0, iclass 34, count 2 2006.285.11:14:38.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:14:38.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:14:38.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.11:14:38.10#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:38.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:14:38.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:14:38.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:14:38.22#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:14:38.22#ibcon#first serial, iclass 34, count 0 2006.285.11:14:38.22#ibcon#enter sib2, iclass 34, count 0 2006.285.11:14:38.22#ibcon#flushed, iclass 34, count 0 2006.285.11:14:38.22#ibcon#about to write, iclass 34, count 0 2006.285.11:14:38.22#ibcon#wrote, iclass 34, count 0 2006.285.11:14:38.22#ibcon#about to read 3, iclass 34, count 0 2006.285.11:14:38.24#ibcon#read 3, iclass 34, count 0 2006.285.11:14:38.24#ibcon#about to read 4, iclass 34, count 0 2006.285.11:14:38.24#ibcon#read 4, iclass 34, count 0 2006.285.11:14:38.24#ibcon#about to read 5, iclass 34, count 0 2006.285.11:14:38.24#ibcon#read 5, iclass 34, count 0 2006.285.11:14:38.24#ibcon#about to read 6, iclass 34, count 0 2006.285.11:14:38.24#ibcon#read 6, iclass 34, count 0 2006.285.11:14:38.24#ibcon#end of sib2, iclass 34, count 0 2006.285.11:14:38.24#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:14:38.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:14:38.24#ibcon#[27=USB\r\n] 2006.285.11:14:38.24#ibcon#*before write, iclass 34, count 0 2006.285.11:14:38.24#ibcon#enter sib2, iclass 34, count 0 2006.285.11:14:38.24#ibcon#flushed, iclass 34, count 0 2006.285.11:14:38.24#ibcon#about to write, iclass 34, count 0 2006.285.11:14:38.24#ibcon#wrote, iclass 34, count 0 2006.285.11:14:38.24#ibcon#about to read 3, iclass 34, count 0 2006.285.11:14:38.27#ibcon#read 3, iclass 34, count 0 2006.285.11:14:38.27#ibcon#about to read 4, iclass 34, count 0 2006.285.11:14:38.27#ibcon#read 4, iclass 34, count 0 2006.285.11:14:38.27#ibcon#about to read 5, iclass 34, count 0 2006.285.11:14:38.27#ibcon#read 5, iclass 34, count 0 2006.285.11:14:38.27#ibcon#about to read 6, iclass 34, count 0 2006.285.11:14:38.27#ibcon#read 6, iclass 34, count 0 2006.285.11:14:38.27#ibcon#end of sib2, iclass 34, count 0 2006.285.11:14:38.27#ibcon#*after write, iclass 34, count 0 2006.285.11:14:38.27#ibcon#*before return 0, iclass 34, count 0 2006.285.11:14:38.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:14:38.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:14:38.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:14:38.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:14:38.27$vck44/vblo=3,649.99 2006.285.11:14:38.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.11:14:38.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.11:14:38.27#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:38.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:14:38.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:14:38.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:14:38.27#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:14:38.27#ibcon#first serial, iclass 36, count 0 2006.285.11:14:38.27#ibcon#enter sib2, iclass 36, count 0 2006.285.11:14:38.27#ibcon#flushed, iclass 36, count 0 2006.285.11:14:38.27#ibcon#about to write, iclass 36, count 0 2006.285.11:14:38.27#ibcon#wrote, iclass 36, count 0 2006.285.11:14:38.27#ibcon#about to read 3, iclass 36, count 0 2006.285.11:14:38.29#ibcon#read 3, iclass 36, count 0 2006.285.11:14:38.29#ibcon#about to read 4, iclass 36, count 0 2006.285.11:14:38.29#ibcon#read 4, iclass 36, count 0 2006.285.11:14:38.29#ibcon#about to read 5, iclass 36, count 0 2006.285.11:14:38.29#ibcon#read 5, iclass 36, count 0 2006.285.11:14:38.29#ibcon#about to read 6, iclass 36, count 0 2006.285.11:14:38.29#ibcon#read 6, iclass 36, count 0 2006.285.11:14:38.29#ibcon#end of sib2, iclass 36, count 0 2006.285.11:14:38.29#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:14:38.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:14:38.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:14:38.29#ibcon#*before write, iclass 36, count 0 2006.285.11:14:38.29#ibcon#enter sib2, iclass 36, count 0 2006.285.11:14:38.29#ibcon#flushed, iclass 36, count 0 2006.285.11:14:38.29#ibcon#about to write, iclass 36, count 0 2006.285.11:14:38.29#ibcon#wrote, iclass 36, count 0 2006.285.11:14:38.29#ibcon#about to read 3, iclass 36, count 0 2006.285.11:14:38.33#ibcon#read 3, iclass 36, count 0 2006.285.11:14:38.33#ibcon#about to read 4, iclass 36, count 0 2006.285.11:14:38.33#ibcon#read 4, iclass 36, count 0 2006.285.11:14:38.33#ibcon#about to read 5, iclass 36, count 0 2006.285.11:14:38.33#ibcon#read 5, iclass 36, count 0 2006.285.11:14:38.33#ibcon#about to read 6, iclass 36, count 0 2006.285.11:14:38.33#ibcon#read 6, iclass 36, count 0 2006.285.11:14:38.33#ibcon#end of sib2, iclass 36, count 0 2006.285.11:14:38.33#ibcon#*after write, iclass 36, count 0 2006.285.11:14:38.33#ibcon#*before return 0, iclass 36, count 0 2006.285.11:14:38.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:14:38.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:14:38.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:14:38.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:14:38.33$vck44/vb=3,4 2006.285.11:14:38.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.11:14:38.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.11:14:38.33#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:38.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:14:38.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:14:38.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:14:38.39#ibcon#enter wrdev, iclass 38, count 2 2006.285.11:14:38.39#ibcon#first serial, iclass 38, count 2 2006.285.11:14:38.39#ibcon#enter sib2, iclass 38, count 2 2006.285.11:14:38.39#ibcon#flushed, iclass 38, count 2 2006.285.11:14:38.39#ibcon#about to write, iclass 38, count 2 2006.285.11:14:38.39#ibcon#wrote, iclass 38, count 2 2006.285.11:14:38.39#ibcon#about to read 3, iclass 38, count 2 2006.285.11:14:38.41#ibcon#read 3, iclass 38, count 2 2006.285.11:14:38.41#ibcon#about to read 4, iclass 38, count 2 2006.285.11:14:38.41#ibcon#read 4, iclass 38, count 2 2006.285.11:14:38.41#ibcon#about to read 5, iclass 38, count 2 2006.285.11:14:38.41#ibcon#read 5, iclass 38, count 2 2006.285.11:14:38.41#ibcon#about to read 6, iclass 38, count 2 2006.285.11:14:38.41#ibcon#read 6, iclass 38, count 2 2006.285.11:14:38.41#ibcon#end of sib2, iclass 38, count 2 2006.285.11:14:38.41#ibcon#*mode == 0, iclass 38, count 2 2006.285.11:14:38.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.11:14:38.41#ibcon#[27=AT03-04\r\n] 2006.285.11:14:38.41#ibcon#*before write, iclass 38, count 2 2006.285.11:14:38.41#ibcon#enter sib2, iclass 38, count 2 2006.285.11:14:38.41#ibcon#flushed, iclass 38, count 2 2006.285.11:14:38.41#ibcon#about to write, iclass 38, count 2 2006.285.11:14:38.41#ibcon#wrote, iclass 38, count 2 2006.285.11:14:38.41#ibcon#about to read 3, iclass 38, count 2 2006.285.11:14:38.44#ibcon#read 3, iclass 38, count 2 2006.285.11:14:38.44#ibcon#about to read 4, iclass 38, count 2 2006.285.11:14:38.44#ibcon#read 4, iclass 38, count 2 2006.285.11:14:38.44#ibcon#about to read 5, iclass 38, count 2 2006.285.11:14:38.44#ibcon#read 5, iclass 38, count 2 2006.285.11:14:38.44#ibcon#about to read 6, iclass 38, count 2 2006.285.11:14:38.44#ibcon#read 6, iclass 38, count 2 2006.285.11:14:38.44#ibcon#end of sib2, iclass 38, count 2 2006.285.11:14:38.44#ibcon#*after write, iclass 38, count 2 2006.285.11:14:38.44#ibcon#*before return 0, iclass 38, count 2 2006.285.11:14:38.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:14:38.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:14:38.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.11:14:38.44#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:38.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:14:38.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:14:38.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:14:38.56#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:14:38.56#ibcon#first serial, iclass 38, count 0 2006.285.11:14:38.56#ibcon#enter sib2, iclass 38, count 0 2006.285.11:14:38.56#ibcon#flushed, iclass 38, count 0 2006.285.11:14:38.56#ibcon#about to write, iclass 38, count 0 2006.285.11:14:38.56#ibcon#wrote, iclass 38, count 0 2006.285.11:14:38.56#ibcon#about to read 3, iclass 38, count 0 2006.285.11:14:38.58#ibcon#read 3, iclass 38, count 0 2006.285.11:14:38.58#ibcon#about to read 4, iclass 38, count 0 2006.285.11:14:38.58#ibcon#read 4, iclass 38, count 0 2006.285.11:14:38.58#ibcon#about to read 5, iclass 38, count 0 2006.285.11:14:38.58#ibcon#read 5, iclass 38, count 0 2006.285.11:14:38.58#ibcon#about to read 6, iclass 38, count 0 2006.285.11:14:38.58#ibcon#read 6, iclass 38, count 0 2006.285.11:14:38.58#ibcon#end of sib2, iclass 38, count 0 2006.285.11:14:38.58#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:14:38.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:14:38.58#ibcon#[27=USB\r\n] 2006.285.11:14:38.58#ibcon#*before write, iclass 38, count 0 2006.285.11:14:38.58#ibcon#enter sib2, iclass 38, count 0 2006.285.11:14:38.58#ibcon#flushed, iclass 38, count 0 2006.285.11:14:38.58#ibcon#about to write, iclass 38, count 0 2006.285.11:14:38.58#ibcon#wrote, iclass 38, count 0 2006.285.11:14:38.58#ibcon#about to read 3, iclass 38, count 0 2006.285.11:14:38.61#ibcon#read 3, iclass 38, count 0 2006.285.11:14:38.61#ibcon#about to read 4, iclass 38, count 0 2006.285.11:14:38.61#ibcon#read 4, iclass 38, count 0 2006.285.11:14:38.61#ibcon#about to read 5, iclass 38, count 0 2006.285.11:14:38.61#ibcon#read 5, iclass 38, count 0 2006.285.11:14:38.61#ibcon#about to read 6, iclass 38, count 0 2006.285.11:14:38.61#ibcon#read 6, iclass 38, count 0 2006.285.11:14:38.61#ibcon#end of sib2, iclass 38, count 0 2006.285.11:14:38.61#ibcon#*after write, iclass 38, count 0 2006.285.11:14:38.61#ibcon#*before return 0, iclass 38, count 0 2006.285.11:14:38.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:14:38.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:14:38.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:14:38.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:14:38.61$vck44/vblo=4,679.99 2006.285.11:14:38.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.11:14:38.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.11:14:38.61#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:38.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:14:38.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:14:38.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:14:38.61#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:14:38.61#ibcon#first serial, iclass 40, count 0 2006.285.11:14:38.61#ibcon#enter sib2, iclass 40, count 0 2006.285.11:14:38.61#ibcon#flushed, iclass 40, count 0 2006.285.11:14:38.61#ibcon#about to write, iclass 40, count 0 2006.285.11:14:38.61#ibcon#wrote, iclass 40, count 0 2006.285.11:14:38.61#ibcon#about to read 3, iclass 40, count 0 2006.285.11:14:38.63#ibcon#read 3, iclass 40, count 0 2006.285.11:14:38.63#ibcon#about to read 4, iclass 40, count 0 2006.285.11:14:38.63#ibcon#read 4, iclass 40, count 0 2006.285.11:14:38.63#ibcon#about to read 5, iclass 40, count 0 2006.285.11:14:38.63#ibcon#read 5, iclass 40, count 0 2006.285.11:14:38.63#ibcon#about to read 6, iclass 40, count 0 2006.285.11:14:38.63#ibcon#read 6, iclass 40, count 0 2006.285.11:14:38.63#ibcon#end of sib2, iclass 40, count 0 2006.285.11:14:38.63#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:14:38.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:14:38.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:14:38.63#ibcon#*before write, iclass 40, count 0 2006.285.11:14:38.63#ibcon#enter sib2, iclass 40, count 0 2006.285.11:14:38.63#ibcon#flushed, iclass 40, count 0 2006.285.11:14:38.63#ibcon#about to write, iclass 40, count 0 2006.285.11:14:38.63#ibcon#wrote, iclass 40, count 0 2006.285.11:14:38.63#ibcon#about to read 3, iclass 40, count 0 2006.285.11:14:38.67#ibcon#read 3, iclass 40, count 0 2006.285.11:14:38.67#ibcon#about to read 4, iclass 40, count 0 2006.285.11:14:38.67#ibcon#read 4, iclass 40, count 0 2006.285.11:14:38.67#ibcon#about to read 5, iclass 40, count 0 2006.285.11:14:38.67#ibcon#read 5, iclass 40, count 0 2006.285.11:14:38.67#ibcon#about to read 6, iclass 40, count 0 2006.285.11:14:38.67#ibcon#read 6, iclass 40, count 0 2006.285.11:14:38.67#ibcon#end of sib2, iclass 40, count 0 2006.285.11:14:38.67#ibcon#*after write, iclass 40, count 0 2006.285.11:14:38.67#ibcon#*before return 0, iclass 40, count 0 2006.285.11:14:38.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:14:38.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:14:38.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:14:38.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:14:38.67$vck44/vb=4,5 2006.285.11:14:38.67#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.11:14:38.67#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.11:14:38.67#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:38.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:14:38.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:14:38.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:14:38.73#ibcon#enter wrdev, iclass 4, count 2 2006.285.11:14:38.73#ibcon#first serial, iclass 4, count 2 2006.285.11:14:38.73#ibcon#enter sib2, iclass 4, count 2 2006.285.11:14:38.73#ibcon#flushed, iclass 4, count 2 2006.285.11:14:38.73#ibcon#about to write, iclass 4, count 2 2006.285.11:14:38.73#ibcon#wrote, iclass 4, count 2 2006.285.11:14:38.73#ibcon#about to read 3, iclass 4, count 2 2006.285.11:14:38.75#ibcon#read 3, iclass 4, count 2 2006.285.11:14:38.75#ibcon#about to read 4, iclass 4, count 2 2006.285.11:14:38.75#ibcon#read 4, iclass 4, count 2 2006.285.11:14:38.75#ibcon#about to read 5, iclass 4, count 2 2006.285.11:14:38.75#ibcon#read 5, iclass 4, count 2 2006.285.11:14:38.75#ibcon#about to read 6, iclass 4, count 2 2006.285.11:14:38.75#ibcon#read 6, iclass 4, count 2 2006.285.11:14:38.75#ibcon#end of sib2, iclass 4, count 2 2006.285.11:14:38.75#ibcon#*mode == 0, iclass 4, count 2 2006.285.11:14:38.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.11:14:38.75#ibcon#[27=AT04-05\r\n] 2006.285.11:14:38.75#ibcon#*before write, iclass 4, count 2 2006.285.11:14:38.75#ibcon#enter sib2, iclass 4, count 2 2006.285.11:14:38.75#ibcon#flushed, iclass 4, count 2 2006.285.11:14:38.75#ibcon#about to write, iclass 4, count 2 2006.285.11:14:38.75#ibcon#wrote, iclass 4, count 2 2006.285.11:14:38.75#ibcon#about to read 3, iclass 4, count 2 2006.285.11:14:38.78#ibcon#read 3, iclass 4, count 2 2006.285.11:14:38.78#ibcon#about to read 4, iclass 4, count 2 2006.285.11:14:38.78#ibcon#read 4, iclass 4, count 2 2006.285.11:14:38.78#ibcon#about to read 5, iclass 4, count 2 2006.285.11:14:38.78#ibcon#read 5, iclass 4, count 2 2006.285.11:14:38.78#ibcon#about to read 6, iclass 4, count 2 2006.285.11:14:38.78#ibcon#read 6, iclass 4, count 2 2006.285.11:14:38.78#ibcon#end of sib2, iclass 4, count 2 2006.285.11:14:38.78#ibcon#*after write, iclass 4, count 2 2006.285.11:14:38.78#ibcon#*before return 0, iclass 4, count 2 2006.285.11:14:38.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:14:38.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:14:38.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.11:14:38.78#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:38.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:14:38.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:14:38.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:14:38.90#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:14:38.90#ibcon#first serial, iclass 4, count 0 2006.285.11:14:38.90#ibcon#enter sib2, iclass 4, count 0 2006.285.11:14:38.90#ibcon#flushed, iclass 4, count 0 2006.285.11:14:38.90#ibcon#about to write, iclass 4, count 0 2006.285.11:14:38.90#ibcon#wrote, iclass 4, count 0 2006.285.11:14:38.90#ibcon#about to read 3, iclass 4, count 0 2006.285.11:14:38.92#ibcon#read 3, iclass 4, count 0 2006.285.11:14:38.92#ibcon#about to read 4, iclass 4, count 0 2006.285.11:14:38.92#ibcon#read 4, iclass 4, count 0 2006.285.11:14:38.92#ibcon#about to read 5, iclass 4, count 0 2006.285.11:14:38.92#ibcon#read 5, iclass 4, count 0 2006.285.11:14:38.92#ibcon#about to read 6, iclass 4, count 0 2006.285.11:14:38.92#ibcon#read 6, iclass 4, count 0 2006.285.11:14:38.92#ibcon#end of sib2, iclass 4, count 0 2006.285.11:14:38.92#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:14:38.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:14:38.92#ibcon#[27=USB\r\n] 2006.285.11:14:38.92#ibcon#*before write, iclass 4, count 0 2006.285.11:14:38.92#ibcon#enter sib2, iclass 4, count 0 2006.285.11:14:38.92#ibcon#flushed, iclass 4, count 0 2006.285.11:14:38.92#ibcon#about to write, iclass 4, count 0 2006.285.11:14:38.92#ibcon#wrote, iclass 4, count 0 2006.285.11:14:38.92#ibcon#about to read 3, iclass 4, count 0 2006.285.11:14:38.95#ibcon#read 3, iclass 4, count 0 2006.285.11:14:38.95#ibcon#about to read 4, iclass 4, count 0 2006.285.11:14:38.95#ibcon#read 4, iclass 4, count 0 2006.285.11:14:38.95#ibcon#about to read 5, iclass 4, count 0 2006.285.11:14:38.95#ibcon#read 5, iclass 4, count 0 2006.285.11:14:38.95#ibcon#about to read 6, iclass 4, count 0 2006.285.11:14:38.95#ibcon#read 6, iclass 4, count 0 2006.285.11:14:38.95#ibcon#end of sib2, iclass 4, count 0 2006.285.11:14:38.95#ibcon#*after write, iclass 4, count 0 2006.285.11:14:38.95#ibcon#*before return 0, iclass 4, count 0 2006.285.11:14:38.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:14:38.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:14:38.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:14:38.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:14:38.95$vck44/vblo=5,709.99 2006.285.11:14:38.95#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.11:14:38.95#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.11:14:38.95#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:38.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:14:38.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:14:38.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:14:38.95#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:14:38.95#ibcon#first serial, iclass 6, count 0 2006.285.11:14:38.95#ibcon#enter sib2, iclass 6, count 0 2006.285.11:14:38.95#ibcon#flushed, iclass 6, count 0 2006.285.11:14:38.95#ibcon#about to write, iclass 6, count 0 2006.285.11:14:38.95#ibcon#wrote, iclass 6, count 0 2006.285.11:14:38.95#ibcon#about to read 3, iclass 6, count 0 2006.285.11:14:38.97#ibcon#read 3, iclass 6, count 0 2006.285.11:14:38.97#ibcon#about to read 4, iclass 6, count 0 2006.285.11:14:38.97#ibcon#read 4, iclass 6, count 0 2006.285.11:14:38.97#ibcon#about to read 5, iclass 6, count 0 2006.285.11:14:38.97#ibcon#read 5, iclass 6, count 0 2006.285.11:14:38.97#ibcon#about to read 6, iclass 6, count 0 2006.285.11:14:38.97#ibcon#read 6, iclass 6, count 0 2006.285.11:14:38.97#ibcon#end of sib2, iclass 6, count 0 2006.285.11:14:38.97#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:14:38.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:14:38.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:14:38.97#ibcon#*before write, iclass 6, count 0 2006.285.11:14:38.97#ibcon#enter sib2, iclass 6, count 0 2006.285.11:14:38.97#ibcon#flushed, iclass 6, count 0 2006.285.11:14:38.97#ibcon#about to write, iclass 6, count 0 2006.285.11:14:38.97#ibcon#wrote, iclass 6, count 0 2006.285.11:14:38.97#ibcon#about to read 3, iclass 6, count 0 2006.285.11:14:39.01#ibcon#read 3, iclass 6, count 0 2006.285.11:14:39.01#ibcon#about to read 4, iclass 6, count 0 2006.285.11:14:39.01#ibcon#read 4, iclass 6, count 0 2006.285.11:14:39.01#ibcon#about to read 5, iclass 6, count 0 2006.285.11:14:39.01#ibcon#read 5, iclass 6, count 0 2006.285.11:14:39.01#ibcon#about to read 6, iclass 6, count 0 2006.285.11:14:39.01#ibcon#read 6, iclass 6, count 0 2006.285.11:14:39.01#ibcon#end of sib2, iclass 6, count 0 2006.285.11:14:39.01#ibcon#*after write, iclass 6, count 0 2006.285.11:14:39.01#ibcon#*before return 0, iclass 6, count 0 2006.285.11:14:39.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:14:39.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:14:39.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:14:39.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:14:39.01$vck44/vb=5,4 2006.285.11:14:39.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.11:14:39.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.11:14:39.01#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:39.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:14:39.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:14:39.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:14:39.07#ibcon#enter wrdev, iclass 10, count 2 2006.285.11:14:39.07#ibcon#first serial, iclass 10, count 2 2006.285.11:14:39.07#ibcon#enter sib2, iclass 10, count 2 2006.285.11:14:39.07#ibcon#flushed, iclass 10, count 2 2006.285.11:14:39.07#ibcon#about to write, iclass 10, count 2 2006.285.11:14:39.07#ibcon#wrote, iclass 10, count 2 2006.285.11:14:39.07#ibcon#about to read 3, iclass 10, count 2 2006.285.11:14:39.09#ibcon#read 3, iclass 10, count 2 2006.285.11:14:39.09#ibcon#about to read 4, iclass 10, count 2 2006.285.11:14:39.09#ibcon#read 4, iclass 10, count 2 2006.285.11:14:39.09#ibcon#about to read 5, iclass 10, count 2 2006.285.11:14:39.09#ibcon#read 5, iclass 10, count 2 2006.285.11:14:39.09#ibcon#about to read 6, iclass 10, count 2 2006.285.11:14:39.09#ibcon#read 6, iclass 10, count 2 2006.285.11:14:39.09#ibcon#end of sib2, iclass 10, count 2 2006.285.11:14:39.09#ibcon#*mode == 0, iclass 10, count 2 2006.285.11:14:39.09#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.11:14:39.09#ibcon#[27=AT05-04\r\n] 2006.285.11:14:39.09#ibcon#*before write, iclass 10, count 2 2006.285.11:14:39.09#ibcon#enter sib2, iclass 10, count 2 2006.285.11:14:39.09#ibcon#flushed, iclass 10, count 2 2006.285.11:14:39.09#ibcon#about to write, iclass 10, count 2 2006.285.11:14:39.09#ibcon#wrote, iclass 10, count 2 2006.285.11:14:39.09#ibcon#about to read 3, iclass 10, count 2 2006.285.11:14:39.12#ibcon#read 3, iclass 10, count 2 2006.285.11:14:39.12#ibcon#about to read 4, iclass 10, count 2 2006.285.11:14:39.12#ibcon#read 4, iclass 10, count 2 2006.285.11:14:39.12#ibcon#about to read 5, iclass 10, count 2 2006.285.11:14:39.12#ibcon#read 5, iclass 10, count 2 2006.285.11:14:39.12#ibcon#about to read 6, iclass 10, count 2 2006.285.11:14:39.12#ibcon#read 6, iclass 10, count 2 2006.285.11:14:39.12#ibcon#end of sib2, iclass 10, count 2 2006.285.11:14:39.12#ibcon#*after write, iclass 10, count 2 2006.285.11:14:39.12#ibcon#*before return 0, iclass 10, count 2 2006.285.11:14:39.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:14:39.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:14:39.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.11:14:39.12#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:39.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:14:39.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:14:39.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:14:39.24#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:14:39.24#ibcon#first serial, iclass 10, count 0 2006.285.11:14:39.24#ibcon#enter sib2, iclass 10, count 0 2006.285.11:14:39.24#ibcon#flushed, iclass 10, count 0 2006.285.11:14:39.24#ibcon#about to write, iclass 10, count 0 2006.285.11:14:39.24#ibcon#wrote, iclass 10, count 0 2006.285.11:14:39.24#ibcon#about to read 3, iclass 10, count 0 2006.285.11:14:39.26#ibcon#read 3, iclass 10, count 0 2006.285.11:14:39.26#ibcon#about to read 4, iclass 10, count 0 2006.285.11:14:39.26#ibcon#read 4, iclass 10, count 0 2006.285.11:14:39.26#ibcon#about to read 5, iclass 10, count 0 2006.285.11:14:39.26#ibcon#read 5, iclass 10, count 0 2006.285.11:14:39.26#ibcon#about to read 6, iclass 10, count 0 2006.285.11:14:39.26#ibcon#read 6, iclass 10, count 0 2006.285.11:14:39.26#ibcon#end of sib2, iclass 10, count 0 2006.285.11:14:39.26#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:14:39.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:14:39.26#ibcon#[27=USB\r\n] 2006.285.11:14:39.26#ibcon#*before write, iclass 10, count 0 2006.285.11:14:39.26#ibcon#enter sib2, iclass 10, count 0 2006.285.11:14:39.26#ibcon#flushed, iclass 10, count 0 2006.285.11:14:39.26#ibcon#about to write, iclass 10, count 0 2006.285.11:14:39.26#ibcon#wrote, iclass 10, count 0 2006.285.11:14:39.26#ibcon#about to read 3, iclass 10, count 0 2006.285.11:14:39.29#ibcon#read 3, iclass 10, count 0 2006.285.11:14:39.29#ibcon#about to read 4, iclass 10, count 0 2006.285.11:14:39.29#ibcon#read 4, iclass 10, count 0 2006.285.11:14:39.29#ibcon#about to read 5, iclass 10, count 0 2006.285.11:14:39.29#ibcon#read 5, iclass 10, count 0 2006.285.11:14:39.29#ibcon#about to read 6, iclass 10, count 0 2006.285.11:14:39.29#ibcon#read 6, iclass 10, count 0 2006.285.11:14:39.29#ibcon#end of sib2, iclass 10, count 0 2006.285.11:14:39.29#ibcon#*after write, iclass 10, count 0 2006.285.11:14:39.29#ibcon#*before return 0, iclass 10, count 0 2006.285.11:14:39.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:14:39.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:14:39.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:14:39.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:14:39.29$vck44/vblo=6,719.99 2006.285.11:14:39.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.11:14:39.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.11:14:39.29#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:39.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:14:39.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:14:39.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:14:39.29#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:14:39.29#ibcon#first serial, iclass 12, count 0 2006.285.11:14:39.29#ibcon#enter sib2, iclass 12, count 0 2006.285.11:14:39.29#ibcon#flushed, iclass 12, count 0 2006.285.11:14:39.29#ibcon#about to write, iclass 12, count 0 2006.285.11:14:39.29#ibcon#wrote, iclass 12, count 0 2006.285.11:14:39.29#ibcon#about to read 3, iclass 12, count 0 2006.285.11:14:39.31#ibcon#read 3, iclass 12, count 0 2006.285.11:14:39.31#ibcon#about to read 4, iclass 12, count 0 2006.285.11:14:39.31#ibcon#read 4, iclass 12, count 0 2006.285.11:14:39.31#ibcon#about to read 5, iclass 12, count 0 2006.285.11:14:39.31#ibcon#read 5, iclass 12, count 0 2006.285.11:14:39.31#ibcon#about to read 6, iclass 12, count 0 2006.285.11:14:39.31#ibcon#read 6, iclass 12, count 0 2006.285.11:14:39.31#ibcon#end of sib2, iclass 12, count 0 2006.285.11:14:39.31#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:14:39.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:14:39.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:14:39.31#ibcon#*before write, iclass 12, count 0 2006.285.11:14:39.31#ibcon#enter sib2, iclass 12, count 0 2006.285.11:14:39.31#ibcon#flushed, iclass 12, count 0 2006.285.11:14:39.31#ibcon#about to write, iclass 12, count 0 2006.285.11:14:39.31#ibcon#wrote, iclass 12, count 0 2006.285.11:14:39.31#ibcon#about to read 3, iclass 12, count 0 2006.285.11:14:39.35#ibcon#read 3, iclass 12, count 0 2006.285.11:14:39.35#ibcon#about to read 4, iclass 12, count 0 2006.285.11:14:39.35#ibcon#read 4, iclass 12, count 0 2006.285.11:14:39.35#ibcon#about to read 5, iclass 12, count 0 2006.285.11:14:39.35#ibcon#read 5, iclass 12, count 0 2006.285.11:14:39.35#ibcon#about to read 6, iclass 12, count 0 2006.285.11:14:39.35#ibcon#read 6, iclass 12, count 0 2006.285.11:14:39.35#ibcon#end of sib2, iclass 12, count 0 2006.285.11:14:39.35#ibcon#*after write, iclass 12, count 0 2006.285.11:14:39.35#ibcon#*before return 0, iclass 12, count 0 2006.285.11:14:39.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:14:39.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:14:39.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:14:39.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:14:39.35$vck44/vb=6,3 2006.285.11:14:39.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.11:14:39.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.11:14:39.35#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:39.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:14:39.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:14:39.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:14:39.41#ibcon#enter wrdev, iclass 14, count 2 2006.285.11:14:39.41#ibcon#first serial, iclass 14, count 2 2006.285.11:14:39.41#ibcon#enter sib2, iclass 14, count 2 2006.285.11:14:39.41#ibcon#flushed, iclass 14, count 2 2006.285.11:14:39.41#ibcon#about to write, iclass 14, count 2 2006.285.11:14:39.41#ibcon#wrote, iclass 14, count 2 2006.285.11:14:39.41#ibcon#about to read 3, iclass 14, count 2 2006.285.11:14:39.43#ibcon#read 3, iclass 14, count 2 2006.285.11:14:39.43#ibcon#about to read 4, iclass 14, count 2 2006.285.11:14:39.43#ibcon#read 4, iclass 14, count 2 2006.285.11:14:39.43#ibcon#about to read 5, iclass 14, count 2 2006.285.11:14:39.43#ibcon#read 5, iclass 14, count 2 2006.285.11:14:39.43#ibcon#about to read 6, iclass 14, count 2 2006.285.11:14:39.43#ibcon#read 6, iclass 14, count 2 2006.285.11:14:39.43#ibcon#end of sib2, iclass 14, count 2 2006.285.11:14:39.43#ibcon#*mode == 0, iclass 14, count 2 2006.285.11:14:39.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.11:14:39.43#ibcon#[27=AT06-03\r\n] 2006.285.11:14:39.43#ibcon#*before write, iclass 14, count 2 2006.285.11:14:39.43#ibcon#enter sib2, iclass 14, count 2 2006.285.11:14:39.43#ibcon#flushed, iclass 14, count 2 2006.285.11:14:39.43#ibcon#about to write, iclass 14, count 2 2006.285.11:14:39.43#ibcon#wrote, iclass 14, count 2 2006.285.11:14:39.43#ibcon#about to read 3, iclass 14, count 2 2006.285.11:14:39.46#ibcon#read 3, iclass 14, count 2 2006.285.11:14:39.46#ibcon#about to read 4, iclass 14, count 2 2006.285.11:14:39.46#ibcon#read 4, iclass 14, count 2 2006.285.11:14:39.46#ibcon#about to read 5, iclass 14, count 2 2006.285.11:14:39.46#ibcon#read 5, iclass 14, count 2 2006.285.11:14:39.46#ibcon#about to read 6, iclass 14, count 2 2006.285.11:14:39.46#ibcon#read 6, iclass 14, count 2 2006.285.11:14:39.46#ibcon#end of sib2, iclass 14, count 2 2006.285.11:14:39.46#ibcon#*after write, iclass 14, count 2 2006.285.11:14:39.46#ibcon#*before return 0, iclass 14, count 2 2006.285.11:14:39.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:14:39.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:14:39.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.11:14:39.46#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:39.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:14:39.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:14:39.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:14:39.58#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:14:39.58#ibcon#first serial, iclass 14, count 0 2006.285.11:14:39.58#ibcon#enter sib2, iclass 14, count 0 2006.285.11:14:39.58#ibcon#flushed, iclass 14, count 0 2006.285.11:14:39.58#ibcon#about to write, iclass 14, count 0 2006.285.11:14:39.58#ibcon#wrote, iclass 14, count 0 2006.285.11:14:39.58#ibcon#about to read 3, iclass 14, count 0 2006.285.11:14:39.60#ibcon#read 3, iclass 14, count 0 2006.285.11:14:39.60#ibcon#about to read 4, iclass 14, count 0 2006.285.11:14:39.60#ibcon#read 4, iclass 14, count 0 2006.285.11:14:39.60#ibcon#about to read 5, iclass 14, count 0 2006.285.11:14:39.60#ibcon#read 5, iclass 14, count 0 2006.285.11:14:39.60#ibcon#about to read 6, iclass 14, count 0 2006.285.11:14:39.60#ibcon#read 6, iclass 14, count 0 2006.285.11:14:39.60#ibcon#end of sib2, iclass 14, count 0 2006.285.11:14:39.60#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:14:39.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:14:39.60#ibcon#[27=USB\r\n] 2006.285.11:14:39.60#ibcon#*before write, iclass 14, count 0 2006.285.11:14:39.60#ibcon#enter sib2, iclass 14, count 0 2006.285.11:14:39.60#ibcon#flushed, iclass 14, count 0 2006.285.11:14:39.60#ibcon#about to write, iclass 14, count 0 2006.285.11:14:39.60#ibcon#wrote, iclass 14, count 0 2006.285.11:14:39.60#ibcon#about to read 3, iclass 14, count 0 2006.285.11:14:39.63#ibcon#read 3, iclass 14, count 0 2006.285.11:14:39.63#ibcon#about to read 4, iclass 14, count 0 2006.285.11:14:39.63#ibcon#read 4, iclass 14, count 0 2006.285.11:14:39.63#ibcon#about to read 5, iclass 14, count 0 2006.285.11:14:39.63#ibcon#read 5, iclass 14, count 0 2006.285.11:14:39.63#ibcon#about to read 6, iclass 14, count 0 2006.285.11:14:39.63#ibcon#read 6, iclass 14, count 0 2006.285.11:14:39.63#ibcon#end of sib2, iclass 14, count 0 2006.285.11:14:39.63#ibcon#*after write, iclass 14, count 0 2006.285.11:14:39.63#ibcon#*before return 0, iclass 14, count 0 2006.285.11:14:39.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:14:39.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:14:39.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:14:39.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:14:39.63$vck44/vblo=7,734.99 2006.285.11:14:39.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.11:14:39.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.11:14:39.63#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:39.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:14:39.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:14:39.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:14:39.63#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:14:39.63#ibcon#first serial, iclass 16, count 0 2006.285.11:14:39.63#ibcon#enter sib2, iclass 16, count 0 2006.285.11:14:39.63#ibcon#flushed, iclass 16, count 0 2006.285.11:14:39.63#ibcon#about to write, iclass 16, count 0 2006.285.11:14:39.63#ibcon#wrote, iclass 16, count 0 2006.285.11:14:39.63#ibcon#about to read 3, iclass 16, count 0 2006.285.11:14:39.65#ibcon#read 3, iclass 16, count 0 2006.285.11:14:39.65#ibcon#about to read 4, iclass 16, count 0 2006.285.11:14:39.65#ibcon#read 4, iclass 16, count 0 2006.285.11:14:39.65#ibcon#about to read 5, iclass 16, count 0 2006.285.11:14:39.65#ibcon#read 5, iclass 16, count 0 2006.285.11:14:39.65#ibcon#about to read 6, iclass 16, count 0 2006.285.11:14:39.65#ibcon#read 6, iclass 16, count 0 2006.285.11:14:39.65#ibcon#end of sib2, iclass 16, count 0 2006.285.11:14:39.65#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:14:39.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:14:39.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:14:39.65#ibcon#*before write, iclass 16, count 0 2006.285.11:14:39.65#ibcon#enter sib2, iclass 16, count 0 2006.285.11:14:39.65#ibcon#flushed, iclass 16, count 0 2006.285.11:14:39.65#ibcon#about to write, iclass 16, count 0 2006.285.11:14:39.65#ibcon#wrote, iclass 16, count 0 2006.285.11:14:39.65#ibcon#about to read 3, iclass 16, count 0 2006.285.11:14:39.69#ibcon#read 3, iclass 16, count 0 2006.285.11:14:39.69#ibcon#about to read 4, iclass 16, count 0 2006.285.11:14:39.69#ibcon#read 4, iclass 16, count 0 2006.285.11:14:39.69#ibcon#about to read 5, iclass 16, count 0 2006.285.11:14:39.69#ibcon#read 5, iclass 16, count 0 2006.285.11:14:39.69#ibcon#about to read 6, iclass 16, count 0 2006.285.11:14:39.69#ibcon#read 6, iclass 16, count 0 2006.285.11:14:39.69#ibcon#end of sib2, iclass 16, count 0 2006.285.11:14:39.69#ibcon#*after write, iclass 16, count 0 2006.285.11:14:39.69#ibcon#*before return 0, iclass 16, count 0 2006.285.11:14:39.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:14:39.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:14:39.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:14:39.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:14:39.69$vck44/vb=7,4 2006.285.11:14:39.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.11:14:39.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.11:14:39.69#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:39.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:14:39.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:14:39.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:14:39.75#ibcon#enter wrdev, iclass 18, count 2 2006.285.11:14:39.75#ibcon#first serial, iclass 18, count 2 2006.285.11:14:39.75#ibcon#enter sib2, iclass 18, count 2 2006.285.11:14:39.75#ibcon#flushed, iclass 18, count 2 2006.285.11:14:39.75#ibcon#about to write, iclass 18, count 2 2006.285.11:14:39.75#ibcon#wrote, iclass 18, count 2 2006.285.11:14:39.75#ibcon#about to read 3, iclass 18, count 2 2006.285.11:14:39.77#ibcon#read 3, iclass 18, count 2 2006.285.11:14:39.77#ibcon#about to read 4, iclass 18, count 2 2006.285.11:14:39.77#ibcon#read 4, iclass 18, count 2 2006.285.11:14:39.77#ibcon#about to read 5, iclass 18, count 2 2006.285.11:14:39.77#ibcon#read 5, iclass 18, count 2 2006.285.11:14:39.77#ibcon#about to read 6, iclass 18, count 2 2006.285.11:14:39.77#ibcon#read 6, iclass 18, count 2 2006.285.11:14:39.77#ibcon#end of sib2, iclass 18, count 2 2006.285.11:14:39.77#ibcon#*mode == 0, iclass 18, count 2 2006.285.11:14:39.77#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.11:14:39.77#ibcon#[27=AT07-04\r\n] 2006.285.11:14:39.77#ibcon#*before write, iclass 18, count 2 2006.285.11:14:39.77#ibcon#enter sib2, iclass 18, count 2 2006.285.11:14:39.77#ibcon#flushed, iclass 18, count 2 2006.285.11:14:39.77#ibcon#about to write, iclass 18, count 2 2006.285.11:14:39.77#ibcon#wrote, iclass 18, count 2 2006.285.11:14:39.77#ibcon#about to read 3, iclass 18, count 2 2006.285.11:14:39.80#ibcon#read 3, iclass 18, count 2 2006.285.11:14:39.80#ibcon#about to read 4, iclass 18, count 2 2006.285.11:14:39.80#ibcon#read 4, iclass 18, count 2 2006.285.11:14:39.80#ibcon#about to read 5, iclass 18, count 2 2006.285.11:14:39.80#ibcon#read 5, iclass 18, count 2 2006.285.11:14:39.80#ibcon#about to read 6, iclass 18, count 2 2006.285.11:14:39.80#ibcon#read 6, iclass 18, count 2 2006.285.11:14:39.80#ibcon#end of sib2, iclass 18, count 2 2006.285.11:14:39.80#ibcon#*after write, iclass 18, count 2 2006.285.11:14:39.80#ibcon#*before return 0, iclass 18, count 2 2006.285.11:14:39.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:14:39.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:14:39.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.11:14:39.80#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:39.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:14:39.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:14:39.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:14:39.92#ibcon#enter wrdev, iclass 18, count 0 2006.285.11:14:39.92#ibcon#first serial, iclass 18, count 0 2006.285.11:14:39.92#ibcon#enter sib2, iclass 18, count 0 2006.285.11:14:39.92#ibcon#flushed, iclass 18, count 0 2006.285.11:14:39.92#ibcon#about to write, iclass 18, count 0 2006.285.11:14:39.92#ibcon#wrote, iclass 18, count 0 2006.285.11:14:39.92#ibcon#about to read 3, iclass 18, count 0 2006.285.11:14:39.94#ibcon#read 3, iclass 18, count 0 2006.285.11:14:39.94#ibcon#about to read 4, iclass 18, count 0 2006.285.11:14:39.94#ibcon#read 4, iclass 18, count 0 2006.285.11:14:39.94#ibcon#about to read 5, iclass 18, count 0 2006.285.11:14:39.94#ibcon#read 5, iclass 18, count 0 2006.285.11:14:39.94#ibcon#about to read 6, iclass 18, count 0 2006.285.11:14:39.94#ibcon#read 6, iclass 18, count 0 2006.285.11:14:39.94#ibcon#end of sib2, iclass 18, count 0 2006.285.11:14:39.94#ibcon#*mode == 0, iclass 18, count 0 2006.285.11:14:39.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.11:14:39.94#ibcon#[27=USB\r\n] 2006.285.11:14:39.94#ibcon#*before write, iclass 18, count 0 2006.285.11:14:39.94#ibcon#enter sib2, iclass 18, count 0 2006.285.11:14:39.94#ibcon#flushed, iclass 18, count 0 2006.285.11:14:39.94#ibcon#about to write, iclass 18, count 0 2006.285.11:14:39.94#ibcon#wrote, iclass 18, count 0 2006.285.11:14:39.94#ibcon#about to read 3, iclass 18, count 0 2006.285.11:14:39.97#ibcon#read 3, iclass 18, count 0 2006.285.11:14:39.97#ibcon#about to read 4, iclass 18, count 0 2006.285.11:14:39.97#ibcon#read 4, iclass 18, count 0 2006.285.11:14:39.97#ibcon#about to read 5, iclass 18, count 0 2006.285.11:14:39.97#ibcon#read 5, iclass 18, count 0 2006.285.11:14:39.97#ibcon#about to read 6, iclass 18, count 0 2006.285.11:14:39.97#ibcon#read 6, iclass 18, count 0 2006.285.11:14:39.97#ibcon#end of sib2, iclass 18, count 0 2006.285.11:14:39.97#ibcon#*after write, iclass 18, count 0 2006.285.11:14:39.97#ibcon#*before return 0, iclass 18, count 0 2006.285.11:14:39.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:14:39.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:14:39.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.11:14:39.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.11:14:39.97$vck44/vblo=8,744.99 2006.285.11:14:39.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.11:14:39.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.11:14:39.97#ibcon#ireg 17 cls_cnt 0 2006.285.11:14:39.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:14:39.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:14:39.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:14:39.97#ibcon#enter wrdev, iclass 20, count 0 2006.285.11:14:39.97#ibcon#first serial, iclass 20, count 0 2006.285.11:14:39.97#ibcon#enter sib2, iclass 20, count 0 2006.285.11:14:39.97#ibcon#flushed, iclass 20, count 0 2006.285.11:14:39.97#ibcon#about to write, iclass 20, count 0 2006.285.11:14:39.97#ibcon#wrote, iclass 20, count 0 2006.285.11:14:39.97#ibcon#about to read 3, iclass 20, count 0 2006.285.11:14:39.99#ibcon#read 3, iclass 20, count 0 2006.285.11:14:39.99#ibcon#about to read 4, iclass 20, count 0 2006.285.11:14:39.99#ibcon#read 4, iclass 20, count 0 2006.285.11:14:39.99#ibcon#about to read 5, iclass 20, count 0 2006.285.11:14:39.99#ibcon#read 5, iclass 20, count 0 2006.285.11:14:39.99#ibcon#about to read 6, iclass 20, count 0 2006.285.11:14:39.99#ibcon#read 6, iclass 20, count 0 2006.285.11:14:39.99#ibcon#end of sib2, iclass 20, count 0 2006.285.11:14:39.99#ibcon#*mode == 0, iclass 20, count 0 2006.285.11:14:39.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.11:14:39.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:14:39.99#ibcon#*before write, iclass 20, count 0 2006.285.11:14:39.99#ibcon#enter sib2, iclass 20, count 0 2006.285.11:14:39.99#ibcon#flushed, iclass 20, count 0 2006.285.11:14:39.99#ibcon#about to write, iclass 20, count 0 2006.285.11:14:39.99#ibcon#wrote, iclass 20, count 0 2006.285.11:14:39.99#ibcon#about to read 3, iclass 20, count 0 2006.285.11:14:40.03#ibcon#read 3, iclass 20, count 0 2006.285.11:14:40.03#ibcon#about to read 4, iclass 20, count 0 2006.285.11:14:40.03#ibcon#read 4, iclass 20, count 0 2006.285.11:14:40.03#ibcon#about to read 5, iclass 20, count 0 2006.285.11:14:40.03#ibcon#read 5, iclass 20, count 0 2006.285.11:14:40.03#ibcon#about to read 6, iclass 20, count 0 2006.285.11:14:40.03#ibcon#read 6, iclass 20, count 0 2006.285.11:14:40.03#ibcon#end of sib2, iclass 20, count 0 2006.285.11:14:40.03#ibcon#*after write, iclass 20, count 0 2006.285.11:14:40.03#ibcon#*before return 0, iclass 20, count 0 2006.285.11:14:40.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:14:40.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:14:40.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.11:14:40.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.11:14:40.03$vck44/vb=8,4 2006.285.11:14:40.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.11:14:40.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.11:14:40.03#ibcon#ireg 11 cls_cnt 2 2006.285.11:14:40.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:14:40.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:14:40.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:14:40.09#ibcon#enter wrdev, iclass 22, count 2 2006.285.11:14:40.09#ibcon#first serial, iclass 22, count 2 2006.285.11:14:40.09#ibcon#enter sib2, iclass 22, count 2 2006.285.11:14:40.09#ibcon#flushed, iclass 22, count 2 2006.285.11:14:40.09#ibcon#about to write, iclass 22, count 2 2006.285.11:14:40.09#ibcon#wrote, iclass 22, count 2 2006.285.11:14:40.09#ibcon#about to read 3, iclass 22, count 2 2006.285.11:14:40.11#ibcon#read 3, iclass 22, count 2 2006.285.11:14:40.11#ibcon#about to read 4, iclass 22, count 2 2006.285.11:14:40.11#ibcon#read 4, iclass 22, count 2 2006.285.11:14:40.11#ibcon#about to read 5, iclass 22, count 2 2006.285.11:14:40.11#ibcon#read 5, iclass 22, count 2 2006.285.11:14:40.11#ibcon#about to read 6, iclass 22, count 2 2006.285.11:14:40.11#ibcon#read 6, iclass 22, count 2 2006.285.11:14:40.11#ibcon#end of sib2, iclass 22, count 2 2006.285.11:14:40.11#ibcon#*mode == 0, iclass 22, count 2 2006.285.11:14:40.11#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.11:14:40.11#ibcon#[27=AT08-04\r\n] 2006.285.11:14:40.11#ibcon#*before write, iclass 22, count 2 2006.285.11:14:40.11#ibcon#enter sib2, iclass 22, count 2 2006.285.11:14:40.11#ibcon#flushed, iclass 22, count 2 2006.285.11:14:40.11#ibcon#about to write, iclass 22, count 2 2006.285.11:14:40.11#ibcon#wrote, iclass 22, count 2 2006.285.11:14:40.11#ibcon#about to read 3, iclass 22, count 2 2006.285.11:14:40.14#ibcon#read 3, iclass 22, count 2 2006.285.11:14:40.14#ibcon#about to read 4, iclass 22, count 2 2006.285.11:14:40.14#ibcon#read 4, iclass 22, count 2 2006.285.11:14:40.14#ibcon#about to read 5, iclass 22, count 2 2006.285.11:14:40.14#ibcon#read 5, iclass 22, count 2 2006.285.11:14:40.14#ibcon#about to read 6, iclass 22, count 2 2006.285.11:14:40.14#ibcon#read 6, iclass 22, count 2 2006.285.11:14:40.14#ibcon#end of sib2, iclass 22, count 2 2006.285.11:14:40.14#ibcon#*after write, iclass 22, count 2 2006.285.11:14:40.14#ibcon#*before return 0, iclass 22, count 2 2006.285.11:14:40.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:14:40.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:14:40.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.11:14:40.14#ibcon#ireg 7 cls_cnt 0 2006.285.11:14:40.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:14:40.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:14:40.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:14:40.26#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:14:40.26#ibcon#first serial, iclass 22, count 0 2006.285.11:14:40.26#ibcon#enter sib2, iclass 22, count 0 2006.285.11:14:40.26#ibcon#flushed, iclass 22, count 0 2006.285.11:14:40.26#ibcon#about to write, iclass 22, count 0 2006.285.11:14:40.26#ibcon#wrote, iclass 22, count 0 2006.285.11:14:40.26#ibcon#about to read 3, iclass 22, count 0 2006.285.11:14:40.28#ibcon#read 3, iclass 22, count 0 2006.285.11:14:40.28#ibcon#about to read 4, iclass 22, count 0 2006.285.11:14:40.28#ibcon#read 4, iclass 22, count 0 2006.285.11:14:40.28#ibcon#about to read 5, iclass 22, count 0 2006.285.11:14:40.28#ibcon#read 5, iclass 22, count 0 2006.285.11:14:40.28#ibcon#about to read 6, iclass 22, count 0 2006.285.11:14:40.28#ibcon#read 6, iclass 22, count 0 2006.285.11:14:40.28#ibcon#end of sib2, iclass 22, count 0 2006.285.11:14:40.28#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:14:40.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:14:40.28#ibcon#[27=USB\r\n] 2006.285.11:14:40.28#ibcon#*before write, iclass 22, count 0 2006.285.11:14:40.28#ibcon#enter sib2, iclass 22, count 0 2006.285.11:14:40.28#ibcon#flushed, iclass 22, count 0 2006.285.11:14:40.28#ibcon#about to write, iclass 22, count 0 2006.285.11:14:40.28#ibcon#wrote, iclass 22, count 0 2006.285.11:14:40.28#ibcon#about to read 3, iclass 22, count 0 2006.285.11:14:40.31#ibcon#read 3, iclass 22, count 0 2006.285.11:14:40.31#ibcon#about to read 4, iclass 22, count 0 2006.285.11:14:40.31#ibcon#read 4, iclass 22, count 0 2006.285.11:14:40.31#ibcon#about to read 5, iclass 22, count 0 2006.285.11:14:40.31#ibcon#read 5, iclass 22, count 0 2006.285.11:14:40.31#ibcon#about to read 6, iclass 22, count 0 2006.285.11:14:40.31#ibcon#read 6, iclass 22, count 0 2006.285.11:14:40.31#ibcon#end of sib2, iclass 22, count 0 2006.285.11:14:40.31#ibcon#*after write, iclass 22, count 0 2006.285.11:14:40.31#ibcon#*before return 0, iclass 22, count 0 2006.285.11:14:40.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:14:40.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:14:40.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:14:40.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:14:40.31$vck44/vabw=wide 2006.285.11:14:40.31#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.11:14:40.31#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.11:14:40.31#ibcon#ireg 8 cls_cnt 0 2006.285.11:14:40.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:14:40.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:14:40.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:14:40.31#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:14:40.31#ibcon#first serial, iclass 24, count 0 2006.285.11:14:40.31#ibcon#enter sib2, iclass 24, count 0 2006.285.11:14:40.31#ibcon#flushed, iclass 24, count 0 2006.285.11:14:40.31#ibcon#about to write, iclass 24, count 0 2006.285.11:14:40.31#ibcon#wrote, iclass 24, count 0 2006.285.11:14:40.31#ibcon#about to read 3, iclass 24, count 0 2006.285.11:14:40.33#ibcon#read 3, iclass 24, count 0 2006.285.11:14:40.33#ibcon#about to read 4, iclass 24, count 0 2006.285.11:14:40.33#ibcon#read 4, iclass 24, count 0 2006.285.11:14:40.33#ibcon#about to read 5, iclass 24, count 0 2006.285.11:14:40.33#ibcon#read 5, iclass 24, count 0 2006.285.11:14:40.33#ibcon#about to read 6, iclass 24, count 0 2006.285.11:14:40.33#ibcon#read 6, iclass 24, count 0 2006.285.11:14:40.33#ibcon#end of sib2, iclass 24, count 0 2006.285.11:14:40.33#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:14:40.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:14:40.33#ibcon#[25=BW32\r\n] 2006.285.11:14:40.33#ibcon#*before write, iclass 24, count 0 2006.285.11:14:40.33#ibcon#enter sib2, iclass 24, count 0 2006.285.11:14:40.33#ibcon#flushed, iclass 24, count 0 2006.285.11:14:40.33#ibcon#about to write, iclass 24, count 0 2006.285.11:14:40.33#ibcon#wrote, iclass 24, count 0 2006.285.11:14:40.33#ibcon#about to read 3, iclass 24, count 0 2006.285.11:14:40.36#ibcon#read 3, iclass 24, count 0 2006.285.11:14:40.36#ibcon#about to read 4, iclass 24, count 0 2006.285.11:14:40.36#ibcon#read 4, iclass 24, count 0 2006.285.11:14:40.36#ibcon#about to read 5, iclass 24, count 0 2006.285.11:14:40.36#ibcon#read 5, iclass 24, count 0 2006.285.11:14:40.36#ibcon#about to read 6, iclass 24, count 0 2006.285.11:14:40.36#ibcon#read 6, iclass 24, count 0 2006.285.11:14:40.36#ibcon#end of sib2, iclass 24, count 0 2006.285.11:14:40.36#ibcon#*after write, iclass 24, count 0 2006.285.11:14:40.36#ibcon#*before return 0, iclass 24, count 0 2006.285.11:14:40.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:14:40.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:14:40.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:14:40.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:14:40.36$vck44/vbbw=wide 2006.285.11:14:40.36#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.11:14:40.36#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.11:14:40.36#ibcon#ireg 8 cls_cnt 0 2006.285.11:14:40.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:14:40.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:14:40.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:14:40.43#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:14:40.43#ibcon#first serial, iclass 26, count 0 2006.285.11:14:40.43#ibcon#enter sib2, iclass 26, count 0 2006.285.11:14:40.43#ibcon#flushed, iclass 26, count 0 2006.285.11:14:40.43#ibcon#about to write, iclass 26, count 0 2006.285.11:14:40.43#ibcon#wrote, iclass 26, count 0 2006.285.11:14:40.43#ibcon#about to read 3, iclass 26, count 0 2006.285.11:14:40.45#ibcon#read 3, iclass 26, count 0 2006.285.11:14:40.45#ibcon#about to read 4, iclass 26, count 0 2006.285.11:14:40.45#ibcon#read 4, iclass 26, count 0 2006.285.11:14:40.45#ibcon#about to read 5, iclass 26, count 0 2006.285.11:14:40.45#ibcon#read 5, iclass 26, count 0 2006.285.11:14:40.45#ibcon#about to read 6, iclass 26, count 0 2006.285.11:14:40.45#ibcon#read 6, iclass 26, count 0 2006.285.11:14:40.45#ibcon#end of sib2, iclass 26, count 0 2006.285.11:14:40.45#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:14:40.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:14:40.45#ibcon#[27=BW32\r\n] 2006.285.11:14:40.45#ibcon#*before write, iclass 26, count 0 2006.285.11:14:40.45#ibcon#enter sib2, iclass 26, count 0 2006.285.11:14:40.45#ibcon#flushed, iclass 26, count 0 2006.285.11:14:40.45#ibcon#about to write, iclass 26, count 0 2006.285.11:14:40.45#ibcon#wrote, iclass 26, count 0 2006.285.11:14:40.45#ibcon#about to read 3, iclass 26, count 0 2006.285.11:14:40.48#ibcon#read 3, iclass 26, count 0 2006.285.11:14:40.48#ibcon#about to read 4, iclass 26, count 0 2006.285.11:14:40.48#ibcon#read 4, iclass 26, count 0 2006.285.11:14:40.48#ibcon#about to read 5, iclass 26, count 0 2006.285.11:14:40.48#ibcon#read 5, iclass 26, count 0 2006.285.11:14:40.48#ibcon#about to read 6, iclass 26, count 0 2006.285.11:14:40.48#ibcon#read 6, iclass 26, count 0 2006.285.11:14:40.48#ibcon#end of sib2, iclass 26, count 0 2006.285.11:14:40.48#ibcon#*after write, iclass 26, count 0 2006.285.11:14:40.48#ibcon#*before return 0, iclass 26, count 0 2006.285.11:14:40.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:14:40.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:14:40.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:14:40.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:14:40.48$setupk4/ifdk4 2006.285.11:14:40.48$ifdk4/lo= 2006.285.11:14:40.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:14:40.49$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:14:40.49$ifdk4/patch= 2006.285.11:14:40.49$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:14:40.49$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:14:40.49$setupk4/!*+20s 2006.285.11:14:44.23#abcon#<5=/04 0.9 1.6 19.40 931015.2\r\n> 2006.285.11:14:44.25#abcon#{5=INTERFACE CLEAR} 2006.285.11:14:44.31#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:14:54.40#abcon#<5=/04 0.9 1.6 19.40 931015.2\r\n> 2006.285.11:14:54.42#abcon#{5=INTERFACE CLEAR} 2006.285.11:14:54.48#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:14:55.01$setupk4/"tpicd 2006.285.11:14:55.01$setupk4/echo=off 2006.285.11:14:55.01$setupk4/xlog=off 2006.285.11:14:55.01:!2006.285.11:17:10 2006.285.11:15:17.14#trakl#Source acquired 2006.285.11:15:17.14#flagr#flagr/antenna,acquired 2006.285.11:17:10.00:preob 2006.285.11:17:10.14/onsource/TRACKING 2006.285.11:17:10.14:!2006.285.11:17:20 2006.285.11:17:20.00:"tape 2006.285.11:17:20.00:"st=record 2006.285.11:17:20.00:data_valid=on 2006.285.11:17:20.00:midob 2006.285.11:17:20.14/onsource/TRACKING 2006.285.11:17:20.14/wx/19.37,1015.2,93 2006.285.11:17:20.35/cable/+6.4900E-03 2006.285.11:17:21.44/va/01,07,usb,yes,31,34 2006.285.11:17:21.44/va/02,06,usb,yes,31,32 2006.285.11:17:21.44/va/03,07,usb,yes,31,33 2006.285.11:17:21.44/va/04,06,usb,yes,32,34 2006.285.11:17:21.44/va/05,03,usb,yes,32,32 2006.285.11:17:21.44/va/06,04,usb,yes,29,28 2006.285.11:17:21.44/va/07,04,usb,yes,29,30 2006.285.11:17:21.44/va/08,03,usb,yes,30,36 2006.285.11:17:21.67/valo/01,524.99,yes,locked 2006.285.11:17:21.67/valo/02,534.99,yes,locked 2006.285.11:17:21.67/valo/03,564.99,yes,locked 2006.285.11:17:21.67/valo/04,624.99,yes,locked 2006.285.11:17:21.67/valo/05,734.99,yes,locked 2006.285.11:17:21.67/valo/06,814.99,yes,locked 2006.285.11:17:21.67/valo/07,864.99,yes,locked 2006.285.11:17:21.67/valo/08,884.99,yes,locked 2006.285.11:17:22.76/vb/01,04,usb,yes,30,28 2006.285.11:17:22.76/vb/02,05,usb,yes,28,28 2006.285.11:17:22.76/vb/03,04,usb,yes,29,32 2006.285.11:17:22.76/vb/04,05,usb,yes,30,29 2006.285.11:17:22.76/vb/05,04,usb,yes,26,28 2006.285.11:17:22.76/vb/06,03,usb,yes,37,33 2006.285.11:17:22.76/vb/07,04,usb,yes,30,30 2006.285.11:17:22.76/vb/08,04,usb,yes,27,31 2006.285.11:17:22.99/vblo/01,629.99,yes,locked 2006.285.11:17:22.99/vblo/02,634.99,yes,locked 2006.285.11:17:22.99/vblo/03,649.99,yes,locked 2006.285.11:17:22.99/vblo/04,679.99,yes,locked 2006.285.11:17:22.99/vblo/05,709.99,yes,locked 2006.285.11:17:22.99/vblo/06,719.99,yes,locked 2006.285.11:17:22.99/vblo/07,734.99,yes,locked 2006.285.11:17:22.99/vblo/08,744.99,yes,locked 2006.285.11:17:23.14/vabw/8 2006.285.11:17:23.29/vbbw/8 2006.285.11:17:23.39/xfe/off,on,12.2 2006.285.11:17:23.76/ifatt/23,28,28,28 2006.285.11:17:24.07/fmout-gps/S +2.78E-07 2006.285.11:17:24.09:!2006.285.11:20:00 2006.285.11:20:00.00:data_valid=off 2006.285.11:20:00.00:"et 2006.285.11:20:00.00:!+3s 2006.285.11:20:03.01:"tape 2006.285.11:20:03.01:postob 2006.285.11:20:03.15/cable/+6.4909E-03 2006.285.11:20:03.15/wx/19.35,1015.2,93 2006.285.11:20:04.07/fmout-gps/S +2.77E-07 2006.285.11:20:04.07:scan_name=285-1125,jd0610,240 2006.285.11:20:04.07:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.285.11:20:05.13#flagr#flagr/antenna,new-source 2006.285.11:20:05.13:checkk5 2006.285.11:20:05.50/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:20:05.89/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:20:06.31/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:20:07.05/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:20:07.43/chk_obsdata//k5ts1/T2851117??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.11:20:07.80/chk_obsdata//k5ts2/T2851117??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.11:20:08.27/chk_obsdata//k5ts3/T2851117??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.11:20:08.69/chk_obsdata//k5ts4/T2851117??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.11:20:09.49/k5log//k5ts1_log_newline 2006.285.11:20:10.25/k5log//k5ts2_log_newline 2006.285.11:20:10.99/k5log//k5ts3_log_newline 2006.285.11:20:12.00/k5log//k5ts4_log_newline 2006.285.11:20:12.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:20:12.02:setupk4=1 2006.285.11:20:12.02$setupk4/echo=on 2006.285.11:20:12.02$setupk4/pcalon 2006.285.11:20:12.02$pcalon/"no phase cal control is implemented here 2006.285.11:20:12.02$setupk4/"tpicd=stop 2006.285.11:20:12.02$setupk4/"rec=synch_on 2006.285.11:20:12.02$setupk4/"rec_mode=128 2006.285.11:20:12.02$setupk4/!* 2006.285.11:20:12.02$setupk4/recpk4 2006.285.11:20:12.02$recpk4/recpatch= 2006.285.11:20:12.02$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:20:12.02$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:20:12.02$setupk4/vck44 2006.285.11:20:12.02$vck44/valo=1,524.99 2006.285.11:20:12.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.11:20:12.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.11:20:12.02#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:12.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:20:12.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:20:12.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:20:12.03#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:20:12.03#ibcon#first serial, iclass 19, count 0 2006.285.11:20:12.03#ibcon#enter sib2, iclass 19, count 0 2006.285.11:20:12.03#ibcon#flushed, iclass 19, count 0 2006.285.11:20:12.03#ibcon#about to write, iclass 19, count 0 2006.285.11:20:12.03#ibcon#wrote, iclass 19, count 0 2006.285.11:20:12.03#ibcon#about to read 3, iclass 19, count 0 2006.285.11:20:12.04#ibcon#read 3, iclass 19, count 0 2006.285.11:20:12.04#ibcon#about to read 4, iclass 19, count 0 2006.285.11:20:12.04#ibcon#read 4, iclass 19, count 0 2006.285.11:20:12.04#ibcon#about to read 5, iclass 19, count 0 2006.285.11:20:12.04#ibcon#read 5, iclass 19, count 0 2006.285.11:20:12.04#ibcon#about to read 6, iclass 19, count 0 2006.285.11:20:12.04#ibcon#read 6, iclass 19, count 0 2006.285.11:20:12.04#ibcon#end of sib2, iclass 19, count 0 2006.285.11:20:12.04#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:20:12.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:20:12.04#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:20:12.04#ibcon#*before write, iclass 19, count 0 2006.285.11:20:12.04#ibcon#enter sib2, iclass 19, count 0 2006.285.11:20:12.04#ibcon#flushed, iclass 19, count 0 2006.285.11:20:12.04#ibcon#about to write, iclass 19, count 0 2006.285.11:20:12.04#ibcon#wrote, iclass 19, count 0 2006.285.11:20:12.04#ibcon#about to read 3, iclass 19, count 0 2006.285.11:20:12.09#ibcon#read 3, iclass 19, count 0 2006.285.11:20:12.09#ibcon#about to read 4, iclass 19, count 0 2006.285.11:20:12.09#ibcon#read 4, iclass 19, count 0 2006.285.11:20:12.09#ibcon#about to read 5, iclass 19, count 0 2006.285.11:20:12.09#ibcon#read 5, iclass 19, count 0 2006.285.11:20:12.09#ibcon#about to read 6, iclass 19, count 0 2006.285.11:20:12.09#ibcon#read 6, iclass 19, count 0 2006.285.11:20:12.09#ibcon#end of sib2, iclass 19, count 0 2006.285.11:20:12.09#ibcon#*after write, iclass 19, count 0 2006.285.11:20:12.09#ibcon#*before return 0, iclass 19, count 0 2006.285.11:20:12.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:20:12.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:20:12.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:20:12.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:20:12.09$vck44/va=1,7 2006.285.11:20:12.09#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.11:20:12.09#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.11:20:12.09#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:12.09#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:20:12.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:20:12.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:20:12.09#ibcon#enter wrdev, iclass 21, count 2 2006.285.11:20:12.09#ibcon#first serial, iclass 21, count 2 2006.285.11:20:12.09#ibcon#enter sib2, iclass 21, count 2 2006.285.11:20:12.09#ibcon#flushed, iclass 21, count 2 2006.285.11:20:12.09#ibcon#about to write, iclass 21, count 2 2006.285.11:20:12.09#ibcon#wrote, iclass 21, count 2 2006.285.11:20:12.09#ibcon#about to read 3, iclass 21, count 2 2006.285.11:20:12.11#ibcon#read 3, iclass 21, count 2 2006.285.11:20:12.11#ibcon#about to read 4, iclass 21, count 2 2006.285.11:20:12.11#ibcon#read 4, iclass 21, count 2 2006.285.11:20:12.11#ibcon#about to read 5, iclass 21, count 2 2006.285.11:20:12.11#ibcon#read 5, iclass 21, count 2 2006.285.11:20:12.11#ibcon#about to read 6, iclass 21, count 2 2006.285.11:20:12.11#ibcon#read 6, iclass 21, count 2 2006.285.11:20:12.11#ibcon#end of sib2, iclass 21, count 2 2006.285.11:20:12.11#ibcon#*mode == 0, iclass 21, count 2 2006.285.11:20:12.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.11:20:12.11#ibcon#[25=AT01-07\r\n] 2006.285.11:20:12.11#ibcon#*before write, iclass 21, count 2 2006.285.11:20:12.11#ibcon#enter sib2, iclass 21, count 2 2006.285.11:20:12.11#ibcon#flushed, iclass 21, count 2 2006.285.11:20:12.11#ibcon#about to write, iclass 21, count 2 2006.285.11:20:12.11#ibcon#wrote, iclass 21, count 2 2006.285.11:20:12.11#ibcon#about to read 3, iclass 21, count 2 2006.285.11:20:12.14#ibcon#read 3, iclass 21, count 2 2006.285.11:20:12.14#ibcon#about to read 4, iclass 21, count 2 2006.285.11:20:12.14#ibcon#read 4, iclass 21, count 2 2006.285.11:20:12.14#ibcon#about to read 5, iclass 21, count 2 2006.285.11:20:12.14#ibcon#read 5, iclass 21, count 2 2006.285.11:20:12.14#ibcon#about to read 6, iclass 21, count 2 2006.285.11:20:12.14#ibcon#read 6, iclass 21, count 2 2006.285.11:20:12.14#ibcon#end of sib2, iclass 21, count 2 2006.285.11:20:12.14#ibcon#*after write, iclass 21, count 2 2006.285.11:20:12.14#ibcon#*before return 0, iclass 21, count 2 2006.285.11:20:12.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:20:12.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:20:12.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.11:20:12.14#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:12.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:20:12.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:20:12.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:20:12.26#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:20:12.26#ibcon#first serial, iclass 21, count 0 2006.285.11:20:12.26#ibcon#enter sib2, iclass 21, count 0 2006.285.11:20:12.26#ibcon#flushed, iclass 21, count 0 2006.285.11:20:12.26#ibcon#about to write, iclass 21, count 0 2006.285.11:20:12.26#ibcon#wrote, iclass 21, count 0 2006.285.11:20:12.26#ibcon#about to read 3, iclass 21, count 0 2006.285.11:20:12.28#ibcon#read 3, iclass 21, count 0 2006.285.11:20:12.28#ibcon#about to read 4, iclass 21, count 0 2006.285.11:20:12.28#ibcon#read 4, iclass 21, count 0 2006.285.11:20:12.28#ibcon#about to read 5, iclass 21, count 0 2006.285.11:20:12.28#ibcon#read 5, iclass 21, count 0 2006.285.11:20:12.28#ibcon#about to read 6, iclass 21, count 0 2006.285.11:20:12.28#ibcon#read 6, iclass 21, count 0 2006.285.11:20:12.28#ibcon#end of sib2, iclass 21, count 0 2006.285.11:20:12.28#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:20:12.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:20:12.28#ibcon#[25=USB\r\n] 2006.285.11:20:12.28#ibcon#*before write, iclass 21, count 0 2006.285.11:20:12.28#ibcon#enter sib2, iclass 21, count 0 2006.285.11:20:12.28#ibcon#flushed, iclass 21, count 0 2006.285.11:20:12.28#ibcon#about to write, iclass 21, count 0 2006.285.11:20:12.28#ibcon#wrote, iclass 21, count 0 2006.285.11:20:12.28#ibcon#about to read 3, iclass 21, count 0 2006.285.11:20:12.31#ibcon#read 3, iclass 21, count 0 2006.285.11:20:12.31#ibcon#about to read 4, iclass 21, count 0 2006.285.11:20:12.31#ibcon#read 4, iclass 21, count 0 2006.285.11:20:12.31#ibcon#about to read 5, iclass 21, count 0 2006.285.11:20:12.31#ibcon#read 5, iclass 21, count 0 2006.285.11:20:12.31#ibcon#about to read 6, iclass 21, count 0 2006.285.11:20:12.31#ibcon#read 6, iclass 21, count 0 2006.285.11:20:12.31#ibcon#end of sib2, iclass 21, count 0 2006.285.11:20:12.31#ibcon#*after write, iclass 21, count 0 2006.285.11:20:12.31#ibcon#*before return 0, iclass 21, count 0 2006.285.11:20:12.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:20:12.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:20:12.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:20:12.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:20:12.31$vck44/valo=2,534.99 2006.285.11:20:12.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.11:20:12.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.11:20:12.31#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:12.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:20:12.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:20:12.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:20:12.31#ibcon#enter wrdev, iclass 23, count 0 2006.285.11:20:12.31#ibcon#first serial, iclass 23, count 0 2006.285.11:20:12.31#ibcon#enter sib2, iclass 23, count 0 2006.285.11:20:12.31#ibcon#flushed, iclass 23, count 0 2006.285.11:20:12.31#ibcon#about to write, iclass 23, count 0 2006.285.11:20:12.31#ibcon#wrote, iclass 23, count 0 2006.285.11:20:12.31#ibcon#about to read 3, iclass 23, count 0 2006.285.11:20:12.33#ibcon#read 3, iclass 23, count 0 2006.285.11:20:12.33#ibcon#about to read 4, iclass 23, count 0 2006.285.11:20:12.33#ibcon#read 4, iclass 23, count 0 2006.285.11:20:12.33#ibcon#about to read 5, iclass 23, count 0 2006.285.11:20:12.33#ibcon#read 5, iclass 23, count 0 2006.285.11:20:12.33#ibcon#about to read 6, iclass 23, count 0 2006.285.11:20:12.33#ibcon#read 6, iclass 23, count 0 2006.285.11:20:12.33#ibcon#end of sib2, iclass 23, count 0 2006.285.11:20:12.33#ibcon#*mode == 0, iclass 23, count 0 2006.285.11:20:12.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.11:20:12.33#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:20:12.33#ibcon#*before write, iclass 23, count 0 2006.285.11:20:12.33#ibcon#enter sib2, iclass 23, count 0 2006.285.11:20:12.33#ibcon#flushed, iclass 23, count 0 2006.285.11:20:12.33#ibcon#about to write, iclass 23, count 0 2006.285.11:20:12.33#ibcon#wrote, iclass 23, count 0 2006.285.11:20:12.33#ibcon#about to read 3, iclass 23, count 0 2006.285.11:20:12.37#ibcon#read 3, iclass 23, count 0 2006.285.11:20:12.37#ibcon#about to read 4, iclass 23, count 0 2006.285.11:20:12.37#ibcon#read 4, iclass 23, count 0 2006.285.11:20:12.37#ibcon#about to read 5, iclass 23, count 0 2006.285.11:20:12.37#ibcon#read 5, iclass 23, count 0 2006.285.11:20:12.37#ibcon#about to read 6, iclass 23, count 0 2006.285.11:20:12.37#ibcon#read 6, iclass 23, count 0 2006.285.11:20:12.37#ibcon#end of sib2, iclass 23, count 0 2006.285.11:20:12.37#ibcon#*after write, iclass 23, count 0 2006.285.11:20:12.37#ibcon#*before return 0, iclass 23, count 0 2006.285.11:20:12.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:20:12.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:20:12.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.11:20:12.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.11:20:12.37$vck44/va=2,6 2006.285.11:20:12.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.11:20:12.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.11:20:12.37#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:12.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:20:12.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:20:12.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:20:12.43#ibcon#enter wrdev, iclass 25, count 2 2006.285.11:20:12.43#ibcon#first serial, iclass 25, count 2 2006.285.11:20:12.43#ibcon#enter sib2, iclass 25, count 2 2006.285.11:20:12.43#ibcon#flushed, iclass 25, count 2 2006.285.11:20:12.43#ibcon#about to write, iclass 25, count 2 2006.285.11:20:12.43#ibcon#wrote, iclass 25, count 2 2006.285.11:20:12.43#ibcon#about to read 3, iclass 25, count 2 2006.285.11:20:12.45#ibcon#read 3, iclass 25, count 2 2006.285.11:20:12.45#ibcon#about to read 4, iclass 25, count 2 2006.285.11:20:12.45#ibcon#read 4, iclass 25, count 2 2006.285.11:20:12.45#ibcon#about to read 5, iclass 25, count 2 2006.285.11:20:12.45#ibcon#read 5, iclass 25, count 2 2006.285.11:20:12.45#ibcon#about to read 6, iclass 25, count 2 2006.285.11:20:12.45#ibcon#read 6, iclass 25, count 2 2006.285.11:20:12.45#ibcon#end of sib2, iclass 25, count 2 2006.285.11:20:12.45#ibcon#*mode == 0, iclass 25, count 2 2006.285.11:20:12.45#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.11:20:12.45#ibcon#[25=AT02-06\r\n] 2006.285.11:20:12.45#ibcon#*before write, iclass 25, count 2 2006.285.11:20:12.45#ibcon#enter sib2, iclass 25, count 2 2006.285.11:20:12.45#ibcon#flushed, iclass 25, count 2 2006.285.11:20:12.45#ibcon#about to write, iclass 25, count 2 2006.285.11:20:12.45#ibcon#wrote, iclass 25, count 2 2006.285.11:20:12.45#ibcon#about to read 3, iclass 25, count 2 2006.285.11:20:12.48#ibcon#read 3, iclass 25, count 2 2006.285.11:20:12.48#ibcon#about to read 4, iclass 25, count 2 2006.285.11:20:12.48#ibcon#read 4, iclass 25, count 2 2006.285.11:20:12.48#ibcon#about to read 5, iclass 25, count 2 2006.285.11:20:12.48#ibcon#read 5, iclass 25, count 2 2006.285.11:20:12.48#ibcon#about to read 6, iclass 25, count 2 2006.285.11:20:12.48#ibcon#read 6, iclass 25, count 2 2006.285.11:20:12.48#ibcon#end of sib2, iclass 25, count 2 2006.285.11:20:12.48#ibcon#*after write, iclass 25, count 2 2006.285.11:20:12.48#ibcon#*before return 0, iclass 25, count 2 2006.285.11:20:12.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:20:12.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:20:12.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.11:20:12.48#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:12.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:20:12.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:20:12.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:20:12.60#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:20:12.60#ibcon#first serial, iclass 25, count 0 2006.285.11:20:12.60#ibcon#enter sib2, iclass 25, count 0 2006.285.11:20:12.60#ibcon#flushed, iclass 25, count 0 2006.285.11:20:12.60#ibcon#about to write, iclass 25, count 0 2006.285.11:20:12.60#ibcon#wrote, iclass 25, count 0 2006.285.11:20:12.60#ibcon#about to read 3, iclass 25, count 0 2006.285.11:20:12.62#ibcon#read 3, iclass 25, count 0 2006.285.11:20:12.62#ibcon#about to read 4, iclass 25, count 0 2006.285.11:20:12.62#ibcon#read 4, iclass 25, count 0 2006.285.11:20:12.62#ibcon#about to read 5, iclass 25, count 0 2006.285.11:20:12.62#ibcon#read 5, iclass 25, count 0 2006.285.11:20:12.62#ibcon#about to read 6, iclass 25, count 0 2006.285.11:20:12.62#ibcon#read 6, iclass 25, count 0 2006.285.11:20:12.62#ibcon#end of sib2, iclass 25, count 0 2006.285.11:20:12.62#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:20:12.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:20:12.62#ibcon#[25=USB\r\n] 2006.285.11:20:12.62#ibcon#*before write, iclass 25, count 0 2006.285.11:20:12.62#ibcon#enter sib2, iclass 25, count 0 2006.285.11:20:12.62#ibcon#flushed, iclass 25, count 0 2006.285.11:20:12.62#ibcon#about to write, iclass 25, count 0 2006.285.11:20:12.62#ibcon#wrote, iclass 25, count 0 2006.285.11:20:12.62#ibcon#about to read 3, iclass 25, count 0 2006.285.11:20:12.65#ibcon#read 3, iclass 25, count 0 2006.285.11:20:12.65#ibcon#about to read 4, iclass 25, count 0 2006.285.11:20:12.65#ibcon#read 4, iclass 25, count 0 2006.285.11:20:12.65#ibcon#about to read 5, iclass 25, count 0 2006.285.11:20:12.65#ibcon#read 5, iclass 25, count 0 2006.285.11:20:12.65#ibcon#about to read 6, iclass 25, count 0 2006.285.11:20:12.65#ibcon#read 6, iclass 25, count 0 2006.285.11:20:12.65#ibcon#end of sib2, iclass 25, count 0 2006.285.11:20:12.65#ibcon#*after write, iclass 25, count 0 2006.285.11:20:12.65#ibcon#*before return 0, iclass 25, count 0 2006.285.11:20:12.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:20:12.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:20:12.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:20:12.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:20:12.65$vck44/valo=3,564.99 2006.285.11:20:12.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.11:20:12.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.11:20:12.65#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:12.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:20:12.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:20:12.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:20:12.65#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:20:12.65#ibcon#first serial, iclass 27, count 0 2006.285.11:20:12.65#ibcon#enter sib2, iclass 27, count 0 2006.285.11:20:12.65#ibcon#flushed, iclass 27, count 0 2006.285.11:20:12.65#ibcon#about to write, iclass 27, count 0 2006.285.11:20:12.65#ibcon#wrote, iclass 27, count 0 2006.285.11:20:12.65#ibcon#about to read 3, iclass 27, count 0 2006.285.11:20:12.67#ibcon#read 3, iclass 27, count 0 2006.285.11:20:12.67#ibcon#about to read 4, iclass 27, count 0 2006.285.11:20:12.67#ibcon#read 4, iclass 27, count 0 2006.285.11:20:12.67#ibcon#about to read 5, iclass 27, count 0 2006.285.11:20:12.67#ibcon#read 5, iclass 27, count 0 2006.285.11:20:12.67#ibcon#about to read 6, iclass 27, count 0 2006.285.11:20:12.67#ibcon#read 6, iclass 27, count 0 2006.285.11:20:12.67#ibcon#end of sib2, iclass 27, count 0 2006.285.11:20:12.67#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:20:12.67#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:20:12.67#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:20:12.67#ibcon#*before write, iclass 27, count 0 2006.285.11:20:12.67#ibcon#enter sib2, iclass 27, count 0 2006.285.11:20:12.67#ibcon#flushed, iclass 27, count 0 2006.285.11:20:12.67#ibcon#about to write, iclass 27, count 0 2006.285.11:20:12.67#ibcon#wrote, iclass 27, count 0 2006.285.11:20:12.67#ibcon#about to read 3, iclass 27, count 0 2006.285.11:20:12.71#ibcon#read 3, iclass 27, count 0 2006.285.11:20:12.71#ibcon#about to read 4, iclass 27, count 0 2006.285.11:20:12.71#ibcon#read 4, iclass 27, count 0 2006.285.11:20:12.71#ibcon#about to read 5, iclass 27, count 0 2006.285.11:20:12.71#ibcon#read 5, iclass 27, count 0 2006.285.11:20:12.71#ibcon#about to read 6, iclass 27, count 0 2006.285.11:20:12.71#ibcon#read 6, iclass 27, count 0 2006.285.11:20:12.71#ibcon#end of sib2, iclass 27, count 0 2006.285.11:20:12.71#ibcon#*after write, iclass 27, count 0 2006.285.11:20:12.71#ibcon#*before return 0, iclass 27, count 0 2006.285.11:20:12.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:20:12.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:20:12.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:20:12.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:20:12.71$vck44/va=3,7 2006.285.11:20:12.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.11:20:12.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.11:20:12.71#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:12.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:20:12.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:20:12.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:20:12.77#ibcon#enter wrdev, iclass 29, count 2 2006.285.11:20:12.77#ibcon#first serial, iclass 29, count 2 2006.285.11:20:12.77#ibcon#enter sib2, iclass 29, count 2 2006.285.11:20:12.77#ibcon#flushed, iclass 29, count 2 2006.285.11:20:12.77#ibcon#about to write, iclass 29, count 2 2006.285.11:20:12.77#ibcon#wrote, iclass 29, count 2 2006.285.11:20:12.77#ibcon#about to read 3, iclass 29, count 2 2006.285.11:20:12.79#ibcon#read 3, iclass 29, count 2 2006.285.11:20:12.79#ibcon#about to read 4, iclass 29, count 2 2006.285.11:20:12.79#ibcon#read 4, iclass 29, count 2 2006.285.11:20:12.79#ibcon#about to read 5, iclass 29, count 2 2006.285.11:20:12.79#ibcon#read 5, iclass 29, count 2 2006.285.11:20:12.79#ibcon#about to read 6, iclass 29, count 2 2006.285.11:20:12.79#ibcon#read 6, iclass 29, count 2 2006.285.11:20:12.79#ibcon#end of sib2, iclass 29, count 2 2006.285.11:20:12.79#ibcon#*mode == 0, iclass 29, count 2 2006.285.11:20:12.79#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.11:20:12.79#ibcon#[25=AT03-07\r\n] 2006.285.11:20:12.79#ibcon#*before write, iclass 29, count 2 2006.285.11:20:12.79#ibcon#enter sib2, iclass 29, count 2 2006.285.11:20:12.79#ibcon#flushed, iclass 29, count 2 2006.285.11:20:12.79#ibcon#about to write, iclass 29, count 2 2006.285.11:20:12.79#ibcon#wrote, iclass 29, count 2 2006.285.11:20:12.79#ibcon#about to read 3, iclass 29, count 2 2006.285.11:20:12.82#ibcon#read 3, iclass 29, count 2 2006.285.11:20:12.82#ibcon#about to read 4, iclass 29, count 2 2006.285.11:20:12.82#ibcon#read 4, iclass 29, count 2 2006.285.11:20:12.82#ibcon#about to read 5, iclass 29, count 2 2006.285.11:20:12.82#ibcon#read 5, iclass 29, count 2 2006.285.11:20:12.82#ibcon#about to read 6, iclass 29, count 2 2006.285.11:20:12.82#ibcon#read 6, iclass 29, count 2 2006.285.11:20:12.82#ibcon#end of sib2, iclass 29, count 2 2006.285.11:20:12.82#ibcon#*after write, iclass 29, count 2 2006.285.11:20:12.82#ibcon#*before return 0, iclass 29, count 2 2006.285.11:20:12.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:20:12.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:20:12.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.11:20:12.82#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:12.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:20:12.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:20:12.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:20:12.94#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:20:12.94#ibcon#first serial, iclass 29, count 0 2006.285.11:20:12.94#ibcon#enter sib2, iclass 29, count 0 2006.285.11:20:12.94#ibcon#flushed, iclass 29, count 0 2006.285.11:20:12.94#ibcon#about to write, iclass 29, count 0 2006.285.11:20:12.94#ibcon#wrote, iclass 29, count 0 2006.285.11:20:12.94#ibcon#about to read 3, iclass 29, count 0 2006.285.11:20:12.96#ibcon#read 3, iclass 29, count 0 2006.285.11:20:12.96#ibcon#about to read 4, iclass 29, count 0 2006.285.11:20:12.96#ibcon#read 4, iclass 29, count 0 2006.285.11:20:12.96#ibcon#about to read 5, iclass 29, count 0 2006.285.11:20:12.96#ibcon#read 5, iclass 29, count 0 2006.285.11:20:12.96#ibcon#about to read 6, iclass 29, count 0 2006.285.11:20:12.96#ibcon#read 6, iclass 29, count 0 2006.285.11:20:12.96#ibcon#end of sib2, iclass 29, count 0 2006.285.11:20:12.96#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:20:12.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:20:12.96#ibcon#[25=USB\r\n] 2006.285.11:20:12.96#ibcon#*before write, iclass 29, count 0 2006.285.11:20:12.96#ibcon#enter sib2, iclass 29, count 0 2006.285.11:20:12.96#ibcon#flushed, iclass 29, count 0 2006.285.11:20:12.96#ibcon#about to write, iclass 29, count 0 2006.285.11:20:12.96#ibcon#wrote, iclass 29, count 0 2006.285.11:20:12.96#ibcon#about to read 3, iclass 29, count 0 2006.285.11:20:12.99#ibcon#read 3, iclass 29, count 0 2006.285.11:20:12.99#ibcon#about to read 4, iclass 29, count 0 2006.285.11:20:12.99#ibcon#read 4, iclass 29, count 0 2006.285.11:20:12.99#ibcon#about to read 5, iclass 29, count 0 2006.285.11:20:12.99#ibcon#read 5, iclass 29, count 0 2006.285.11:20:12.99#ibcon#about to read 6, iclass 29, count 0 2006.285.11:20:12.99#ibcon#read 6, iclass 29, count 0 2006.285.11:20:12.99#ibcon#end of sib2, iclass 29, count 0 2006.285.11:20:12.99#ibcon#*after write, iclass 29, count 0 2006.285.11:20:12.99#ibcon#*before return 0, iclass 29, count 0 2006.285.11:20:12.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:20:12.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:20:12.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:20:12.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:20:12.99$vck44/valo=4,624.99 2006.285.11:20:12.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.11:20:12.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.11:20:12.99#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:12.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:20:12.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:20:12.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:20:12.99#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:20:12.99#ibcon#first serial, iclass 31, count 0 2006.285.11:20:12.99#ibcon#enter sib2, iclass 31, count 0 2006.285.11:20:12.99#ibcon#flushed, iclass 31, count 0 2006.285.11:20:12.99#ibcon#about to write, iclass 31, count 0 2006.285.11:20:12.99#ibcon#wrote, iclass 31, count 0 2006.285.11:20:12.99#ibcon#about to read 3, iclass 31, count 0 2006.285.11:20:13.01#ibcon#read 3, iclass 31, count 0 2006.285.11:20:13.01#ibcon#about to read 4, iclass 31, count 0 2006.285.11:20:13.01#ibcon#read 4, iclass 31, count 0 2006.285.11:20:13.01#ibcon#about to read 5, iclass 31, count 0 2006.285.11:20:13.01#ibcon#read 5, iclass 31, count 0 2006.285.11:20:13.01#ibcon#about to read 6, iclass 31, count 0 2006.285.11:20:13.01#ibcon#read 6, iclass 31, count 0 2006.285.11:20:13.01#ibcon#end of sib2, iclass 31, count 0 2006.285.11:20:13.01#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:20:13.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:20:13.01#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:20:13.01#ibcon#*before write, iclass 31, count 0 2006.285.11:20:13.01#ibcon#enter sib2, iclass 31, count 0 2006.285.11:20:13.01#ibcon#flushed, iclass 31, count 0 2006.285.11:20:13.01#ibcon#about to write, iclass 31, count 0 2006.285.11:20:13.01#ibcon#wrote, iclass 31, count 0 2006.285.11:20:13.01#ibcon#about to read 3, iclass 31, count 0 2006.285.11:20:13.05#ibcon#read 3, iclass 31, count 0 2006.285.11:20:13.05#ibcon#about to read 4, iclass 31, count 0 2006.285.11:20:13.05#ibcon#read 4, iclass 31, count 0 2006.285.11:20:13.05#ibcon#about to read 5, iclass 31, count 0 2006.285.11:20:13.05#ibcon#read 5, iclass 31, count 0 2006.285.11:20:13.05#ibcon#about to read 6, iclass 31, count 0 2006.285.11:20:13.05#ibcon#read 6, iclass 31, count 0 2006.285.11:20:13.05#ibcon#end of sib2, iclass 31, count 0 2006.285.11:20:13.05#ibcon#*after write, iclass 31, count 0 2006.285.11:20:13.05#ibcon#*before return 0, iclass 31, count 0 2006.285.11:20:13.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:20:13.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:20:13.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:20:13.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:20:13.05$vck44/va=4,6 2006.285.11:20:13.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.11:20:13.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.11:20:13.05#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:13.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:20:13.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:20:13.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:20:13.11#ibcon#enter wrdev, iclass 33, count 2 2006.285.11:20:13.11#ibcon#first serial, iclass 33, count 2 2006.285.11:20:13.11#ibcon#enter sib2, iclass 33, count 2 2006.285.11:20:13.11#ibcon#flushed, iclass 33, count 2 2006.285.11:20:13.11#ibcon#about to write, iclass 33, count 2 2006.285.11:20:13.11#ibcon#wrote, iclass 33, count 2 2006.285.11:20:13.11#ibcon#about to read 3, iclass 33, count 2 2006.285.11:20:13.13#ibcon#read 3, iclass 33, count 2 2006.285.11:20:13.13#ibcon#about to read 4, iclass 33, count 2 2006.285.11:20:13.13#ibcon#read 4, iclass 33, count 2 2006.285.11:20:13.13#ibcon#about to read 5, iclass 33, count 2 2006.285.11:20:13.13#ibcon#read 5, iclass 33, count 2 2006.285.11:20:13.13#ibcon#about to read 6, iclass 33, count 2 2006.285.11:20:13.13#ibcon#read 6, iclass 33, count 2 2006.285.11:20:13.13#ibcon#end of sib2, iclass 33, count 2 2006.285.11:20:13.13#ibcon#*mode == 0, iclass 33, count 2 2006.285.11:20:13.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.11:20:13.13#ibcon#[25=AT04-06\r\n] 2006.285.11:20:13.13#ibcon#*before write, iclass 33, count 2 2006.285.11:20:13.13#ibcon#enter sib2, iclass 33, count 2 2006.285.11:20:13.13#ibcon#flushed, iclass 33, count 2 2006.285.11:20:13.13#ibcon#about to write, iclass 33, count 2 2006.285.11:20:13.13#ibcon#wrote, iclass 33, count 2 2006.285.11:20:13.13#ibcon#about to read 3, iclass 33, count 2 2006.285.11:20:13.16#ibcon#read 3, iclass 33, count 2 2006.285.11:20:13.16#ibcon#about to read 4, iclass 33, count 2 2006.285.11:20:13.16#ibcon#read 4, iclass 33, count 2 2006.285.11:20:13.16#ibcon#about to read 5, iclass 33, count 2 2006.285.11:20:13.16#ibcon#read 5, iclass 33, count 2 2006.285.11:20:13.16#ibcon#about to read 6, iclass 33, count 2 2006.285.11:20:13.16#ibcon#read 6, iclass 33, count 2 2006.285.11:20:13.16#ibcon#end of sib2, iclass 33, count 2 2006.285.11:20:13.16#ibcon#*after write, iclass 33, count 2 2006.285.11:20:13.16#ibcon#*before return 0, iclass 33, count 2 2006.285.11:20:13.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:20:13.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:20:13.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.11:20:13.16#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:13.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:20:13.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:20:13.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:20:13.28#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:20:13.28#ibcon#first serial, iclass 33, count 0 2006.285.11:20:13.28#ibcon#enter sib2, iclass 33, count 0 2006.285.11:20:13.28#ibcon#flushed, iclass 33, count 0 2006.285.11:20:13.28#ibcon#about to write, iclass 33, count 0 2006.285.11:20:13.28#ibcon#wrote, iclass 33, count 0 2006.285.11:20:13.28#ibcon#about to read 3, iclass 33, count 0 2006.285.11:20:13.30#ibcon#read 3, iclass 33, count 0 2006.285.11:20:13.30#ibcon#about to read 4, iclass 33, count 0 2006.285.11:20:13.30#ibcon#read 4, iclass 33, count 0 2006.285.11:20:13.30#ibcon#about to read 5, iclass 33, count 0 2006.285.11:20:13.30#ibcon#read 5, iclass 33, count 0 2006.285.11:20:13.30#ibcon#about to read 6, iclass 33, count 0 2006.285.11:20:13.30#ibcon#read 6, iclass 33, count 0 2006.285.11:20:13.30#ibcon#end of sib2, iclass 33, count 0 2006.285.11:20:13.30#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:20:13.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:20:13.30#ibcon#[25=USB\r\n] 2006.285.11:20:13.30#ibcon#*before write, iclass 33, count 0 2006.285.11:20:13.30#ibcon#enter sib2, iclass 33, count 0 2006.285.11:20:13.30#ibcon#flushed, iclass 33, count 0 2006.285.11:20:13.30#ibcon#about to write, iclass 33, count 0 2006.285.11:20:13.30#ibcon#wrote, iclass 33, count 0 2006.285.11:20:13.30#ibcon#about to read 3, iclass 33, count 0 2006.285.11:20:13.33#ibcon#read 3, iclass 33, count 0 2006.285.11:20:13.33#ibcon#about to read 4, iclass 33, count 0 2006.285.11:20:13.33#ibcon#read 4, iclass 33, count 0 2006.285.11:20:13.33#ibcon#about to read 5, iclass 33, count 0 2006.285.11:20:13.33#ibcon#read 5, iclass 33, count 0 2006.285.11:20:13.33#ibcon#about to read 6, iclass 33, count 0 2006.285.11:20:13.33#ibcon#read 6, iclass 33, count 0 2006.285.11:20:13.33#ibcon#end of sib2, iclass 33, count 0 2006.285.11:20:13.33#ibcon#*after write, iclass 33, count 0 2006.285.11:20:13.33#ibcon#*before return 0, iclass 33, count 0 2006.285.11:20:13.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:20:13.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:20:13.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:20:13.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:20:13.33$vck44/valo=5,734.99 2006.285.11:20:13.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.11:20:13.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.11:20:13.33#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:13.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:20:13.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:20:13.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:20:13.33#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:20:13.33#ibcon#first serial, iclass 35, count 0 2006.285.11:20:13.33#ibcon#enter sib2, iclass 35, count 0 2006.285.11:20:13.33#ibcon#flushed, iclass 35, count 0 2006.285.11:20:13.33#ibcon#about to write, iclass 35, count 0 2006.285.11:20:13.33#ibcon#wrote, iclass 35, count 0 2006.285.11:20:13.33#ibcon#about to read 3, iclass 35, count 0 2006.285.11:20:13.35#ibcon#read 3, iclass 35, count 0 2006.285.11:20:13.35#ibcon#about to read 4, iclass 35, count 0 2006.285.11:20:13.35#ibcon#read 4, iclass 35, count 0 2006.285.11:20:13.35#ibcon#about to read 5, iclass 35, count 0 2006.285.11:20:13.35#ibcon#read 5, iclass 35, count 0 2006.285.11:20:13.35#ibcon#about to read 6, iclass 35, count 0 2006.285.11:20:13.35#ibcon#read 6, iclass 35, count 0 2006.285.11:20:13.35#ibcon#end of sib2, iclass 35, count 0 2006.285.11:20:13.35#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:20:13.35#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:20:13.35#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:20:13.35#ibcon#*before write, iclass 35, count 0 2006.285.11:20:13.35#ibcon#enter sib2, iclass 35, count 0 2006.285.11:20:13.35#ibcon#flushed, iclass 35, count 0 2006.285.11:20:13.35#ibcon#about to write, iclass 35, count 0 2006.285.11:20:13.35#ibcon#wrote, iclass 35, count 0 2006.285.11:20:13.35#ibcon#about to read 3, iclass 35, count 0 2006.285.11:20:13.39#ibcon#read 3, iclass 35, count 0 2006.285.11:20:13.39#ibcon#about to read 4, iclass 35, count 0 2006.285.11:20:13.39#ibcon#read 4, iclass 35, count 0 2006.285.11:20:13.39#ibcon#about to read 5, iclass 35, count 0 2006.285.11:20:13.39#ibcon#read 5, iclass 35, count 0 2006.285.11:20:13.39#ibcon#about to read 6, iclass 35, count 0 2006.285.11:20:13.39#ibcon#read 6, iclass 35, count 0 2006.285.11:20:13.39#ibcon#end of sib2, iclass 35, count 0 2006.285.11:20:13.39#ibcon#*after write, iclass 35, count 0 2006.285.11:20:13.39#ibcon#*before return 0, iclass 35, count 0 2006.285.11:20:13.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:20:13.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:20:13.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:20:13.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:20:13.39$vck44/va=5,3 2006.285.11:20:13.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.11:20:13.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.11:20:13.39#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:13.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:20:13.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:20:13.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:20:13.45#ibcon#enter wrdev, iclass 37, count 2 2006.285.11:20:13.45#ibcon#first serial, iclass 37, count 2 2006.285.11:20:13.45#ibcon#enter sib2, iclass 37, count 2 2006.285.11:20:13.45#ibcon#flushed, iclass 37, count 2 2006.285.11:20:13.45#ibcon#about to write, iclass 37, count 2 2006.285.11:20:13.45#ibcon#wrote, iclass 37, count 2 2006.285.11:20:13.45#ibcon#about to read 3, iclass 37, count 2 2006.285.11:20:13.47#ibcon#read 3, iclass 37, count 2 2006.285.11:20:13.47#ibcon#about to read 4, iclass 37, count 2 2006.285.11:20:13.47#ibcon#read 4, iclass 37, count 2 2006.285.11:20:13.47#ibcon#about to read 5, iclass 37, count 2 2006.285.11:20:13.47#ibcon#read 5, iclass 37, count 2 2006.285.11:20:13.47#ibcon#about to read 6, iclass 37, count 2 2006.285.11:20:13.47#ibcon#read 6, iclass 37, count 2 2006.285.11:20:13.47#ibcon#end of sib2, iclass 37, count 2 2006.285.11:20:13.47#ibcon#*mode == 0, iclass 37, count 2 2006.285.11:20:13.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.11:20:13.47#ibcon#[25=AT05-03\r\n] 2006.285.11:20:13.47#ibcon#*before write, iclass 37, count 2 2006.285.11:20:13.47#ibcon#enter sib2, iclass 37, count 2 2006.285.11:20:13.47#ibcon#flushed, iclass 37, count 2 2006.285.11:20:13.47#ibcon#about to write, iclass 37, count 2 2006.285.11:20:13.47#ibcon#wrote, iclass 37, count 2 2006.285.11:20:13.47#ibcon#about to read 3, iclass 37, count 2 2006.285.11:20:13.50#ibcon#read 3, iclass 37, count 2 2006.285.11:20:13.50#ibcon#about to read 4, iclass 37, count 2 2006.285.11:20:13.50#ibcon#read 4, iclass 37, count 2 2006.285.11:20:13.50#ibcon#about to read 5, iclass 37, count 2 2006.285.11:20:13.50#ibcon#read 5, iclass 37, count 2 2006.285.11:20:13.50#ibcon#about to read 6, iclass 37, count 2 2006.285.11:20:13.50#ibcon#read 6, iclass 37, count 2 2006.285.11:20:13.50#ibcon#end of sib2, iclass 37, count 2 2006.285.11:20:13.50#ibcon#*after write, iclass 37, count 2 2006.285.11:20:13.50#ibcon#*before return 0, iclass 37, count 2 2006.285.11:20:13.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:20:13.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:20:13.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.11:20:13.50#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:13.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:20:13.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:20:13.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:20:13.62#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:20:13.62#ibcon#first serial, iclass 37, count 0 2006.285.11:20:13.62#ibcon#enter sib2, iclass 37, count 0 2006.285.11:20:13.62#ibcon#flushed, iclass 37, count 0 2006.285.11:20:13.62#ibcon#about to write, iclass 37, count 0 2006.285.11:20:13.62#ibcon#wrote, iclass 37, count 0 2006.285.11:20:13.62#ibcon#about to read 3, iclass 37, count 0 2006.285.11:20:13.64#ibcon#read 3, iclass 37, count 0 2006.285.11:20:13.64#ibcon#about to read 4, iclass 37, count 0 2006.285.11:20:13.64#ibcon#read 4, iclass 37, count 0 2006.285.11:20:13.64#ibcon#about to read 5, iclass 37, count 0 2006.285.11:20:13.64#ibcon#read 5, iclass 37, count 0 2006.285.11:20:13.64#ibcon#about to read 6, iclass 37, count 0 2006.285.11:20:13.64#ibcon#read 6, iclass 37, count 0 2006.285.11:20:13.64#ibcon#end of sib2, iclass 37, count 0 2006.285.11:20:13.64#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:20:13.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:20:13.64#ibcon#[25=USB\r\n] 2006.285.11:20:13.64#ibcon#*before write, iclass 37, count 0 2006.285.11:20:13.64#ibcon#enter sib2, iclass 37, count 0 2006.285.11:20:13.64#ibcon#flushed, iclass 37, count 0 2006.285.11:20:13.64#ibcon#about to write, iclass 37, count 0 2006.285.11:20:13.64#ibcon#wrote, iclass 37, count 0 2006.285.11:20:13.64#ibcon#about to read 3, iclass 37, count 0 2006.285.11:20:13.67#ibcon#read 3, iclass 37, count 0 2006.285.11:20:13.67#ibcon#about to read 4, iclass 37, count 0 2006.285.11:20:13.67#ibcon#read 4, iclass 37, count 0 2006.285.11:20:13.67#ibcon#about to read 5, iclass 37, count 0 2006.285.11:20:13.67#ibcon#read 5, iclass 37, count 0 2006.285.11:20:13.67#ibcon#about to read 6, iclass 37, count 0 2006.285.11:20:13.67#ibcon#read 6, iclass 37, count 0 2006.285.11:20:13.67#ibcon#end of sib2, iclass 37, count 0 2006.285.11:20:13.67#ibcon#*after write, iclass 37, count 0 2006.285.11:20:13.67#ibcon#*before return 0, iclass 37, count 0 2006.285.11:20:13.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:20:13.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:20:13.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:20:13.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:20:13.67$vck44/valo=6,814.99 2006.285.11:20:13.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.11:20:13.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.11:20:13.67#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:13.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:20:13.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:20:13.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:20:13.67#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:20:13.67#ibcon#first serial, iclass 39, count 0 2006.285.11:20:13.67#ibcon#enter sib2, iclass 39, count 0 2006.285.11:20:13.67#ibcon#flushed, iclass 39, count 0 2006.285.11:20:13.67#ibcon#about to write, iclass 39, count 0 2006.285.11:20:13.67#ibcon#wrote, iclass 39, count 0 2006.285.11:20:13.67#ibcon#about to read 3, iclass 39, count 0 2006.285.11:20:13.69#ibcon#read 3, iclass 39, count 0 2006.285.11:20:13.69#ibcon#about to read 4, iclass 39, count 0 2006.285.11:20:13.69#ibcon#read 4, iclass 39, count 0 2006.285.11:20:13.69#ibcon#about to read 5, iclass 39, count 0 2006.285.11:20:13.69#ibcon#read 5, iclass 39, count 0 2006.285.11:20:13.69#ibcon#about to read 6, iclass 39, count 0 2006.285.11:20:13.69#ibcon#read 6, iclass 39, count 0 2006.285.11:20:13.69#ibcon#end of sib2, iclass 39, count 0 2006.285.11:20:13.69#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:20:13.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:20:13.69#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:20:13.69#ibcon#*before write, iclass 39, count 0 2006.285.11:20:13.69#ibcon#enter sib2, iclass 39, count 0 2006.285.11:20:13.69#ibcon#flushed, iclass 39, count 0 2006.285.11:20:13.69#ibcon#about to write, iclass 39, count 0 2006.285.11:20:13.69#ibcon#wrote, iclass 39, count 0 2006.285.11:20:13.69#ibcon#about to read 3, iclass 39, count 0 2006.285.11:20:13.73#ibcon#read 3, iclass 39, count 0 2006.285.11:20:13.73#ibcon#about to read 4, iclass 39, count 0 2006.285.11:20:13.73#ibcon#read 4, iclass 39, count 0 2006.285.11:20:13.73#ibcon#about to read 5, iclass 39, count 0 2006.285.11:20:13.73#ibcon#read 5, iclass 39, count 0 2006.285.11:20:13.73#ibcon#about to read 6, iclass 39, count 0 2006.285.11:20:13.73#ibcon#read 6, iclass 39, count 0 2006.285.11:20:13.73#ibcon#end of sib2, iclass 39, count 0 2006.285.11:20:13.73#ibcon#*after write, iclass 39, count 0 2006.285.11:20:13.73#ibcon#*before return 0, iclass 39, count 0 2006.285.11:20:13.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:20:13.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:20:13.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:20:13.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:20:13.73$vck44/va=6,4 2006.285.11:20:13.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.11:20:13.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.11:20:13.73#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:13.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:20:13.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:20:13.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:20:13.79#ibcon#enter wrdev, iclass 3, count 2 2006.285.11:20:13.79#ibcon#first serial, iclass 3, count 2 2006.285.11:20:13.79#ibcon#enter sib2, iclass 3, count 2 2006.285.11:20:13.79#ibcon#flushed, iclass 3, count 2 2006.285.11:20:13.79#ibcon#about to write, iclass 3, count 2 2006.285.11:20:13.79#ibcon#wrote, iclass 3, count 2 2006.285.11:20:13.79#ibcon#about to read 3, iclass 3, count 2 2006.285.11:20:13.81#ibcon#read 3, iclass 3, count 2 2006.285.11:20:13.81#ibcon#about to read 4, iclass 3, count 2 2006.285.11:20:13.81#ibcon#read 4, iclass 3, count 2 2006.285.11:20:13.81#ibcon#about to read 5, iclass 3, count 2 2006.285.11:20:13.81#ibcon#read 5, iclass 3, count 2 2006.285.11:20:13.81#ibcon#about to read 6, iclass 3, count 2 2006.285.11:20:13.81#ibcon#read 6, iclass 3, count 2 2006.285.11:20:13.81#ibcon#end of sib2, iclass 3, count 2 2006.285.11:20:13.81#ibcon#*mode == 0, iclass 3, count 2 2006.285.11:20:13.81#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.11:20:13.81#ibcon#[25=AT06-04\r\n] 2006.285.11:20:13.81#ibcon#*before write, iclass 3, count 2 2006.285.11:20:13.81#ibcon#enter sib2, iclass 3, count 2 2006.285.11:20:13.81#ibcon#flushed, iclass 3, count 2 2006.285.11:20:13.81#ibcon#about to write, iclass 3, count 2 2006.285.11:20:13.81#ibcon#wrote, iclass 3, count 2 2006.285.11:20:13.81#ibcon#about to read 3, iclass 3, count 2 2006.285.11:20:13.84#ibcon#read 3, iclass 3, count 2 2006.285.11:20:13.84#ibcon#about to read 4, iclass 3, count 2 2006.285.11:20:13.84#ibcon#read 4, iclass 3, count 2 2006.285.11:20:13.84#ibcon#about to read 5, iclass 3, count 2 2006.285.11:20:13.84#ibcon#read 5, iclass 3, count 2 2006.285.11:20:13.84#ibcon#about to read 6, iclass 3, count 2 2006.285.11:20:13.84#ibcon#read 6, iclass 3, count 2 2006.285.11:20:13.84#ibcon#end of sib2, iclass 3, count 2 2006.285.11:20:13.84#ibcon#*after write, iclass 3, count 2 2006.285.11:20:13.84#ibcon#*before return 0, iclass 3, count 2 2006.285.11:20:13.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:20:13.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:20:13.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.11:20:13.84#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:13.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:20:13.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:20:13.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:20:13.96#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:20:13.96#ibcon#first serial, iclass 3, count 0 2006.285.11:20:13.96#ibcon#enter sib2, iclass 3, count 0 2006.285.11:20:13.96#ibcon#flushed, iclass 3, count 0 2006.285.11:20:13.96#ibcon#about to write, iclass 3, count 0 2006.285.11:20:13.96#ibcon#wrote, iclass 3, count 0 2006.285.11:20:13.96#ibcon#about to read 3, iclass 3, count 0 2006.285.11:20:13.98#ibcon#read 3, iclass 3, count 0 2006.285.11:20:13.98#ibcon#about to read 4, iclass 3, count 0 2006.285.11:20:13.98#ibcon#read 4, iclass 3, count 0 2006.285.11:20:13.98#ibcon#about to read 5, iclass 3, count 0 2006.285.11:20:13.98#ibcon#read 5, iclass 3, count 0 2006.285.11:20:13.98#ibcon#about to read 6, iclass 3, count 0 2006.285.11:20:13.98#ibcon#read 6, iclass 3, count 0 2006.285.11:20:13.98#ibcon#end of sib2, iclass 3, count 0 2006.285.11:20:13.98#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:20:13.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:20:13.98#ibcon#[25=USB\r\n] 2006.285.11:20:13.98#ibcon#*before write, iclass 3, count 0 2006.285.11:20:13.98#ibcon#enter sib2, iclass 3, count 0 2006.285.11:20:13.98#ibcon#flushed, iclass 3, count 0 2006.285.11:20:13.98#ibcon#about to write, iclass 3, count 0 2006.285.11:20:13.98#ibcon#wrote, iclass 3, count 0 2006.285.11:20:13.98#ibcon#about to read 3, iclass 3, count 0 2006.285.11:20:14.01#ibcon#read 3, iclass 3, count 0 2006.285.11:20:14.01#ibcon#about to read 4, iclass 3, count 0 2006.285.11:20:14.01#ibcon#read 4, iclass 3, count 0 2006.285.11:20:14.01#ibcon#about to read 5, iclass 3, count 0 2006.285.11:20:14.01#ibcon#read 5, iclass 3, count 0 2006.285.11:20:14.01#ibcon#about to read 6, iclass 3, count 0 2006.285.11:20:14.01#ibcon#read 6, iclass 3, count 0 2006.285.11:20:14.01#ibcon#end of sib2, iclass 3, count 0 2006.285.11:20:14.01#ibcon#*after write, iclass 3, count 0 2006.285.11:20:14.01#ibcon#*before return 0, iclass 3, count 0 2006.285.11:20:14.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:20:14.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:20:14.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:20:14.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:20:14.01$vck44/valo=7,864.99 2006.285.11:20:14.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.11:20:14.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.11:20:14.01#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:14.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:20:14.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:20:14.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:20:14.01#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:20:14.01#ibcon#first serial, iclass 5, count 0 2006.285.11:20:14.01#ibcon#enter sib2, iclass 5, count 0 2006.285.11:20:14.01#ibcon#flushed, iclass 5, count 0 2006.285.11:20:14.01#ibcon#about to write, iclass 5, count 0 2006.285.11:20:14.01#ibcon#wrote, iclass 5, count 0 2006.285.11:20:14.01#ibcon#about to read 3, iclass 5, count 0 2006.285.11:20:14.03#ibcon#read 3, iclass 5, count 0 2006.285.11:20:14.03#ibcon#about to read 4, iclass 5, count 0 2006.285.11:20:14.03#ibcon#read 4, iclass 5, count 0 2006.285.11:20:14.03#ibcon#about to read 5, iclass 5, count 0 2006.285.11:20:14.03#ibcon#read 5, iclass 5, count 0 2006.285.11:20:14.03#ibcon#about to read 6, iclass 5, count 0 2006.285.11:20:14.03#ibcon#read 6, iclass 5, count 0 2006.285.11:20:14.03#ibcon#end of sib2, iclass 5, count 0 2006.285.11:20:14.03#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:20:14.03#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:20:14.03#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:20:14.03#ibcon#*before write, iclass 5, count 0 2006.285.11:20:14.03#ibcon#enter sib2, iclass 5, count 0 2006.285.11:20:14.03#ibcon#flushed, iclass 5, count 0 2006.285.11:20:14.03#ibcon#about to write, iclass 5, count 0 2006.285.11:20:14.03#ibcon#wrote, iclass 5, count 0 2006.285.11:20:14.03#ibcon#about to read 3, iclass 5, count 0 2006.285.11:20:14.07#ibcon#read 3, iclass 5, count 0 2006.285.11:20:14.07#ibcon#about to read 4, iclass 5, count 0 2006.285.11:20:14.07#ibcon#read 4, iclass 5, count 0 2006.285.11:20:14.07#ibcon#about to read 5, iclass 5, count 0 2006.285.11:20:14.07#ibcon#read 5, iclass 5, count 0 2006.285.11:20:14.07#ibcon#about to read 6, iclass 5, count 0 2006.285.11:20:14.07#ibcon#read 6, iclass 5, count 0 2006.285.11:20:14.07#ibcon#end of sib2, iclass 5, count 0 2006.285.11:20:14.07#ibcon#*after write, iclass 5, count 0 2006.285.11:20:14.07#ibcon#*before return 0, iclass 5, count 0 2006.285.11:20:14.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:20:14.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:20:14.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:20:14.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:20:14.07$vck44/va=7,4 2006.285.11:20:14.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.11:20:14.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.11:20:14.07#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:14.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:20:14.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:20:14.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:20:14.13#ibcon#enter wrdev, iclass 7, count 2 2006.285.11:20:14.13#ibcon#first serial, iclass 7, count 2 2006.285.11:20:14.13#ibcon#enter sib2, iclass 7, count 2 2006.285.11:20:14.13#ibcon#flushed, iclass 7, count 2 2006.285.11:20:14.13#ibcon#about to write, iclass 7, count 2 2006.285.11:20:14.13#ibcon#wrote, iclass 7, count 2 2006.285.11:20:14.13#ibcon#about to read 3, iclass 7, count 2 2006.285.11:20:14.15#ibcon#read 3, iclass 7, count 2 2006.285.11:20:14.15#ibcon#about to read 4, iclass 7, count 2 2006.285.11:20:14.15#ibcon#read 4, iclass 7, count 2 2006.285.11:20:14.15#ibcon#about to read 5, iclass 7, count 2 2006.285.11:20:14.15#ibcon#read 5, iclass 7, count 2 2006.285.11:20:14.15#ibcon#about to read 6, iclass 7, count 2 2006.285.11:20:14.15#ibcon#read 6, iclass 7, count 2 2006.285.11:20:14.15#ibcon#end of sib2, iclass 7, count 2 2006.285.11:20:14.15#ibcon#*mode == 0, iclass 7, count 2 2006.285.11:20:14.15#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.11:20:14.15#ibcon#[25=AT07-04\r\n] 2006.285.11:20:14.15#ibcon#*before write, iclass 7, count 2 2006.285.11:20:14.15#ibcon#enter sib2, iclass 7, count 2 2006.285.11:20:14.15#ibcon#flushed, iclass 7, count 2 2006.285.11:20:14.15#ibcon#about to write, iclass 7, count 2 2006.285.11:20:14.15#ibcon#wrote, iclass 7, count 2 2006.285.11:20:14.15#ibcon#about to read 3, iclass 7, count 2 2006.285.11:20:14.18#ibcon#read 3, iclass 7, count 2 2006.285.11:20:14.18#ibcon#about to read 4, iclass 7, count 2 2006.285.11:20:14.18#ibcon#read 4, iclass 7, count 2 2006.285.11:20:14.18#ibcon#about to read 5, iclass 7, count 2 2006.285.11:20:14.18#ibcon#read 5, iclass 7, count 2 2006.285.11:20:14.18#ibcon#about to read 6, iclass 7, count 2 2006.285.11:20:14.18#ibcon#read 6, iclass 7, count 2 2006.285.11:20:14.18#ibcon#end of sib2, iclass 7, count 2 2006.285.11:20:14.18#ibcon#*after write, iclass 7, count 2 2006.285.11:20:14.18#ibcon#*before return 0, iclass 7, count 2 2006.285.11:20:14.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:20:14.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:20:14.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.11:20:14.18#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:14.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:20:14.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:20:14.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:20:14.30#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:20:14.30#ibcon#first serial, iclass 7, count 0 2006.285.11:20:14.30#ibcon#enter sib2, iclass 7, count 0 2006.285.11:20:14.30#ibcon#flushed, iclass 7, count 0 2006.285.11:20:14.30#ibcon#about to write, iclass 7, count 0 2006.285.11:20:14.30#ibcon#wrote, iclass 7, count 0 2006.285.11:20:14.30#ibcon#about to read 3, iclass 7, count 0 2006.285.11:20:14.32#ibcon#read 3, iclass 7, count 0 2006.285.11:20:14.32#ibcon#about to read 4, iclass 7, count 0 2006.285.11:20:14.32#ibcon#read 4, iclass 7, count 0 2006.285.11:20:14.32#ibcon#about to read 5, iclass 7, count 0 2006.285.11:20:14.32#ibcon#read 5, iclass 7, count 0 2006.285.11:20:14.32#ibcon#about to read 6, iclass 7, count 0 2006.285.11:20:14.32#ibcon#read 6, iclass 7, count 0 2006.285.11:20:14.32#ibcon#end of sib2, iclass 7, count 0 2006.285.11:20:14.32#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:20:14.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:20:14.32#ibcon#[25=USB\r\n] 2006.285.11:20:14.32#ibcon#*before write, iclass 7, count 0 2006.285.11:20:14.32#ibcon#enter sib2, iclass 7, count 0 2006.285.11:20:14.32#ibcon#flushed, iclass 7, count 0 2006.285.11:20:14.32#ibcon#about to write, iclass 7, count 0 2006.285.11:20:14.32#ibcon#wrote, iclass 7, count 0 2006.285.11:20:14.32#ibcon#about to read 3, iclass 7, count 0 2006.285.11:20:14.35#ibcon#read 3, iclass 7, count 0 2006.285.11:20:14.35#ibcon#about to read 4, iclass 7, count 0 2006.285.11:20:14.35#ibcon#read 4, iclass 7, count 0 2006.285.11:20:14.35#ibcon#about to read 5, iclass 7, count 0 2006.285.11:20:14.35#ibcon#read 5, iclass 7, count 0 2006.285.11:20:14.35#ibcon#about to read 6, iclass 7, count 0 2006.285.11:20:14.35#ibcon#read 6, iclass 7, count 0 2006.285.11:20:14.35#ibcon#end of sib2, iclass 7, count 0 2006.285.11:20:14.35#ibcon#*after write, iclass 7, count 0 2006.285.11:20:14.35#ibcon#*before return 0, iclass 7, count 0 2006.285.11:20:14.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:20:14.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:20:14.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:20:14.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:20:14.35$vck44/valo=8,884.99 2006.285.11:20:14.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.11:20:14.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.11:20:14.35#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:14.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:20:14.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:20:14.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:20:14.35#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:20:14.35#ibcon#first serial, iclass 11, count 0 2006.285.11:20:14.35#ibcon#enter sib2, iclass 11, count 0 2006.285.11:20:14.35#ibcon#flushed, iclass 11, count 0 2006.285.11:20:14.35#ibcon#about to write, iclass 11, count 0 2006.285.11:20:14.35#ibcon#wrote, iclass 11, count 0 2006.285.11:20:14.35#ibcon#about to read 3, iclass 11, count 0 2006.285.11:20:14.37#ibcon#read 3, iclass 11, count 0 2006.285.11:20:14.37#ibcon#about to read 4, iclass 11, count 0 2006.285.11:20:14.37#ibcon#read 4, iclass 11, count 0 2006.285.11:20:14.37#ibcon#about to read 5, iclass 11, count 0 2006.285.11:20:14.37#ibcon#read 5, iclass 11, count 0 2006.285.11:20:14.37#ibcon#about to read 6, iclass 11, count 0 2006.285.11:20:14.37#ibcon#read 6, iclass 11, count 0 2006.285.11:20:14.37#ibcon#end of sib2, iclass 11, count 0 2006.285.11:20:14.37#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:20:14.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:20:14.37#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:20:14.37#ibcon#*before write, iclass 11, count 0 2006.285.11:20:14.37#ibcon#enter sib2, iclass 11, count 0 2006.285.11:20:14.37#ibcon#flushed, iclass 11, count 0 2006.285.11:20:14.37#ibcon#about to write, iclass 11, count 0 2006.285.11:20:14.37#ibcon#wrote, iclass 11, count 0 2006.285.11:20:14.37#ibcon#about to read 3, iclass 11, count 0 2006.285.11:20:14.41#ibcon#read 3, iclass 11, count 0 2006.285.11:20:14.41#ibcon#about to read 4, iclass 11, count 0 2006.285.11:20:14.41#ibcon#read 4, iclass 11, count 0 2006.285.11:20:14.41#ibcon#about to read 5, iclass 11, count 0 2006.285.11:20:14.41#ibcon#read 5, iclass 11, count 0 2006.285.11:20:14.41#ibcon#about to read 6, iclass 11, count 0 2006.285.11:20:14.41#ibcon#read 6, iclass 11, count 0 2006.285.11:20:14.41#ibcon#end of sib2, iclass 11, count 0 2006.285.11:20:14.41#ibcon#*after write, iclass 11, count 0 2006.285.11:20:14.41#ibcon#*before return 0, iclass 11, count 0 2006.285.11:20:14.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:20:14.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:20:14.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:20:14.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:20:14.41$vck44/va=8,3 2006.285.11:20:14.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.11:20:14.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.11:20:14.41#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:14.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:20:14.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:20:14.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:20:14.47#ibcon#enter wrdev, iclass 13, count 2 2006.285.11:20:14.47#ibcon#first serial, iclass 13, count 2 2006.285.11:20:14.47#ibcon#enter sib2, iclass 13, count 2 2006.285.11:20:14.47#ibcon#flushed, iclass 13, count 2 2006.285.11:20:14.47#ibcon#about to write, iclass 13, count 2 2006.285.11:20:14.47#ibcon#wrote, iclass 13, count 2 2006.285.11:20:14.47#ibcon#about to read 3, iclass 13, count 2 2006.285.11:20:14.49#ibcon#read 3, iclass 13, count 2 2006.285.11:20:14.49#ibcon#about to read 4, iclass 13, count 2 2006.285.11:20:14.49#ibcon#read 4, iclass 13, count 2 2006.285.11:20:14.49#ibcon#about to read 5, iclass 13, count 2 2006.285.11:20:14.49#ibcon#read 5, iclass 13, count 2 2006.285.11:20:14.49#ibcon#about to read 6, iclass 13, count 2 2006.285.11:20:14.49#ibcon#read 6, iclass 13, count 2 2006.285.11:20:14.49#ibcon#end of sib2, iclass 13, count 2 2006.285.11:20:14.49#ibcon#*mode == 0, iclass 13, count 2 2006.285.11:20:14.49#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.11:20:14.49#ibcon#[25=AT08-03\r\n] 2006.285.11:20:14.49#ibcon#*before write, iclass 13, count 2 2006.285.11:20:14.49#ibcon#enter sib2, iclass 13, count 2 2006.285.11:20:14.49#ibcon#flushed, iclass 13, count 2 2006.285.11:20:14.49#ibcon#about to write, iclass 13, count 2 2006.285.11:20:14.49#ibcon#wrote, iclass 13, count 2 2006.285.11:20:14.49#ibcon#about to read 3, iclass 13, count 2 2006.285.11:20:14.52#ibcon#read 3, iclass 13, count 2 2006.285.11:20:14.52#ibcon#about to read 4, iclass 13, count 2 2006.285.11:20:14.52#ibcon#read 4, iclass 13, count 2 2006.285.11:20:14.52#ibcon#about to read 5, iclass 13, count 2 2006.285.11:20:14.52#ibcon#read 5, iclass 13, count 2 2006.285.11:20:14.52#ibcon#about to read 6, iclass 13, count 2 2006.285.11:20:14.52#ibcon#read 6, iclass 13, count 2 2006.285.11:20:14.52#ibcon#end of sib2, iclass 13, count 2 2006.285.11:20:14.52#ibcon#*after write, iclass 13, count 2 2006.285.11:20:14.52#ibcon#*before return 0, iclass 13, count 2 2006.285.11:20:14.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:20:14.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:20:14.52#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.11:20:14.52#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:14.52#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:20:14.64#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:20:14.64#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:20:14.64#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:20:14.64#ibcon#first serial, iclass 13, count 0 2006.285.11:20:14.64#ibcon#enter sib2, iclass 13, count 0 2006.285.11:20:14.64#ibcon#flushed, iclass 13, count 0 2006.285.11:20:14.64#ibcon#about to write, iclass 13, count 0 2006.285.11:20:14.64#ibcon#wrote, iclass 13, count 0 2006.285.11:20:14.64#ibcon#about to read 3, iclass 13, count 0 2006.285.11:20:14.66#ibcon#read 3, iclass 13, count 0 2006.285.11:20:14.66#ibcon#about to read 4, iclass 13, count 0 2006.285.11:20:14.66#ibcon#read 4, iclass 13, count 0 2006.285.11:20:14.66#ibcon#about to read 5, iclass 13, count 0 2006.285.11:20:14.66#ibcon#read 5, iclass 13, count 0 2006.285.11:20:14.66#ibcon#about to read 6, iclass 13, count 0 2006.285.11:20:14.66#ibcon#read 6, iclass 13, count 0 2006.285.11:20:14.66#ibcon#end of sib2, iclass 13, count 0 2006.285.11:20:14.66#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:20:14.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:20:14.66#ibcon#[25=USB\r\n] 2006.285.11:20:14.66#ibcon#*before write, iclass 13, count 0 2006.285.11:20:14.66#ibcon#enter sib2, iclass 13, count 0 2006.285.11:20:14.66#ibcon#flushed, iclass 13, count 0 2006.285.11:20:14.66#ibcon#about to write, iclass 13, count 0 2006.285.11:20:14.66#ibcon#wrote, iclass 13, count 0 2006.285.11:20:14.66#ibcon#about to read 3, iclass 13, count 0 2006.285.11:20:14.69#ibcon#read 3, iclass 13, count 0 2006.285.11:20:14.69#ibcon#about to read 4, iclass 13, count 0 2006.285.11:20:14.69#ibcon#read 4, iclass 13, count 0 2006.285.11:20:14.69#ibcon#about to read 5, iclass 13, count 0 2006.285.11:20:14.69#ibcon#read 5, iclass 13, count 0 2006.285.11:20:14.69#ibcon#about to read 6, iclass 13, count 0 2006.285.11:20:14.69#ibcon#read 6, iclass 13, count 0 2006.285.11:20:14.69#ibcon#end of sib2, iclass 13, count 0 2006.285.11:20:14.69#ibcon#*after write, iclass 13, count 0 2006.285.11:20:14.69#ibcon#*before return 0, iclass 13, count 0 2006.285.11:20:14.69#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:20:14.69#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:20:14.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:20:14.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:20:14.69$vck44/vblo=1,629.99 2006.285.11:20:14.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.11:20:14.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.11:20:14.69#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:14.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:20:14.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:20:14.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:20:14.69#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:20:14.69#ibcon#first serial, iclass 15, count 0 2006.285.11:20:14.69#ibcon#enter sib2, iclass 15, count 0 2006.285.11:20:14.69#ibcon#flushed, iclass 15, count 0 2006.285.11:20:14.69#ibcon#about to write, iclass 15, count 0 2006.285.11:20:14.69#ibcon#wrote, iclass 15, count 0 2006.285.11:20:14.69#ibcon#about to read 3, iclass 15, count 0 2006.285.11:20:14.71#ibcon#read 3, iclass 15, count 0 2006.285.11:20:14.71#ibcon#about to read 4, iclass 15, count 0 2006.285.11:20:14.71#ibcon#read 4, iclass 15, count 0 2006.285.11:20:14.71#ibcon#about to read 5, iclass 15, count 0 2006.285.11:20:14.71#ibcon#read 5, iclass 15, count 0 2006.285.11:20:14.71#ibcon#about to read 6, iclass 15, count 0 2006.285.11:20:14.71#ibcon#read 6, iclass 15, count 0 2006.285.11:20:14.71#ibcon#end of sib2, iclass 15, count 0 2006.285.11:20:14.71#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:20:14.71#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:20:14.71#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:20:14.71#ibcon#*before write, iclass 15, count 0 2006.285.11:20:14.71#ibcon#enter sib2, iclass 15, count 0 2006.285.11:20:14.71#ibcon#flushed, iclass 15, count 0 2006.285.11:20:14.71#ibcon#about to write, iclass 15, count 0 2006.285.11:20:14.71#ibcon#wrote, iclass 15, count 0 2006.285.11:20:14.71#ibcon#about to read 3, iclass 15, count 0 2006.285.11:20:14.75#ibcon#read 3, iclass 15, count 0 2006.285.11:20:14.75#ibcon#about to read 4, iclass 15, count 0 2006.285.11:20:14.75#ibcon#read 4, iclass 15, count 0 2006.285.11:20:14.75#ibcon#about to read 5, iclass 15, count 0 2006.285.11:20:14.75#ibcon#read 5, iclass 15, count 0 2006.285.11:20:14.75#ibcon#about to read 6, iclass 15, count 0 2006.285.11:20:14.75#ibcon#read 6, iclass 15, count 0 2006.285.11:20:14.75#ibcon#end of sib2, iclass 15, count 0 2006.285.11:20:14.75#ibcon#*after write, iclass 15, count 0 2006.285.11:20:14.75#ibcon#*before return 0, iclass 15, count 0 2006.285.11:20:14.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:20:14.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:20:14.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:20:14.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:20:14.75$vck44/vb=1,4 2006.285.11:20:14.75#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.11:20:14.75#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.11:20:14.75#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:14.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:20:14.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:20:14.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:20:14.75#ibcon#enter wrdev, iclass 17, count 2 2006.285.11:20:14.75#ibcon#first serial, iclass 17, count 2 2006.285.11:20:14.75#ibcon#enter sib2, iclass 17, count 2 2006.285.11:20:14.75#ibcon#flushed, iclass 17, count 2 2006.285.11:20:14.75#ibcon#about to write, iclass 17, count 2 2006.285.11:20:14.75#ibcon#wrote, iclass 17, count 2 2006.285.11:20:14.75#ibcon#about to read 3, iclass 17, count 2 2006.285.11:20:14.77#ibcon#read 3, iclass 17, count 2 2006.285.11:20:14.77#ibcon#about to read 4, iclass 17, count 2 2006.285.11:20:14.77#ibcon#read 4, iclass 17, count 2 2006.285.11:20:14.77#ibcon#about to read 5, iclass 17, count 2 2006.285.11:20:14.77#ibcon#read 5, iclass 17, count 2 2006.285.11:20:14.77#ibcon#about to read 6, iclass 17, count 2 2006.285.11:20:14.77#ibcon#read 6, iclass 17, count 2 2006.285.11:20:14.77#ibcon#end of sib2, iclass 17, count 2 2006.285.11:20:14.77#ibcon#*mode == 0, iclass 17, count 2 2006.285.11:20:14.77#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.11:20:14.77#ibcon#[27=AT01-04\r\n] 2006.285.11:20:14.77#ibcon#*before write, iclass 17, count 2 2006.285.11:20:14.77#ibcon#enter sib2, iclass 17, count 2 2006.285.11:20:14.77#ibcon#flushed, iclass 17, count 2 2006.285.11:20:14.77#ibcon#about to write, iclass 17, count 2 2006.285.11:20:14.77#ibcon#wrote, iclass 17, count 2 2006.285.11:20:14.77#ibcon#about to read 3, iclass 17, count 2 2006.285.11:20:14.80#ibcon#read 3, iclass 17, count 2 2006.285.11:20:14.80#ibcon#about to read 4, iclass 17, count 2 2006.285.11:20:14.80#ibcon#read 4, iclass 17, count 2 2006.285.11:20:14.80#ibcon#about to read 5, iclass 17, count 2 2006.285.11:20:14.80#ibcon#read 5, iclass 17, count 2 2006.285.11:20:14.80#ibcon#about to read 6, iclass 17, count 2 2006.285.11:20:14.80#ibcon#read 6, iclass 17, count 2 2006.285.11:20:14.80#ibcon#end of sib2, iclass 17, count 2 2006.285.11:20:14.80#ibcon#*after write, iclass 17, count 2 2006.285.11:20:14.80#ibcon#*before return 0, iclass 17, count 2 2006.285.11:20:14.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:20:14.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:20:14.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.11:20:14.80#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:14.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:20:14.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:20:14.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:20:14.92#ibcon#enter wrdev, iclass 17, count 0 2006.285.11:20:14.92#ibcon#first serial, iclass 17, count 0 2006.285.11:20:14.92#ibcon#enter sib2, iclass 17, count 0 2006.285.11:20:14.92#ibcon#flushed, iclass 17, count 0 2006.285.11:20:14.92#ibcon#about to write, iclass 17, count 0 2006.285.11:20:14.92#ibcon#wrote, iclass 17, count 0 2006.285.11:20:14.92#ibcon#about to read 3, iclass 17, count 0 2006.285.11:20:14.94#ibcon#read 3, iclass 17, count 0 2006.285.11:20:14.94#ibcon#about to read 4, iclass 17, count 0 2006.285.11:20:14.94#ibcon#read 4, iclass 17, count 0 2006.285.11:20:14.94#ibcon#about to read 5, iclass 17, count 0 2006.285.11:20:14.94#ibcon#read 5, iclass 17, count 0 2006.285.11:20:14.94#ibcon#about to read 6, iclass 17, count 0 2006.285.11:20:14.94#ibcon#read 6, iclass 17, count 0 2006.285.11:20:14.94#ibcon#end of sib2, iclass 17, count 0 2006.285.11:20:14.94#ibcon#*mode == 0, iclass 17, count 0 2006.285.11:20:14.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.11:20:14.94#ibcon#[27=USB\r\n] 2006.285.11:20:14.94#ibcon#*before write, iclass 17, count 0 2006.285.11:20:14.94#ibcon#enter sib2, iclass 17, count 0 2006.285.11:20:14.94#ibcon#flushed, iclass 17, count 0 2006.285.11:20:14.94#ibcon#about to write, iclass 17, count 0 2006.285.11:20:14.94#ibcon#wrote, iclass 17, count 0 2006.285.11:20:14.94#ibcon#about to read 3, iclass 17, count 0 2006.285.11:20:14.97#ibcon#read 3, iclass 17, count 0 2006.285.11:20:14.97#ibcon#about to read 4, iclass 17, count 0 2006.285.11:20:14.97#ibcon#read 4, iclass 17, count 0 2006.285.11:20:14.97#ibcon#about to read 5, iclass 17, count 0 2006.285.11:20:14.97#ibcon#read 5, iclass 17, count 0 2006.285.11:20:14.97#ibcon#about to read 6, iclass 17, count 0 2006.285.11:20:14.97#ibcon#read 6, iclass 17, count 0 2006.285.11:20:14.97#ibcon#end of sib2, iclass 17, count 0 2006.285.11:20:14.97#ibcon#*after write, iclass 17, count 0 2006.285.11:20:14.97#ibcon#*before return 0, iclass 17, count 0 2006.285.11:20:14.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:20:14.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:20:14.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.11:20:14.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.11:20:14.97$vck44/vblo=2,634.99 2006.285.11:20:14.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.11:20:14.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.11:20:14.97#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:14.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:20:14.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:20:14.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:20:14.97#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:20:14.97#ibcon#first serial, iclass 19, count 0 2006.285.11:20:14.97#ibcon#enter sib2, iclass 19, count 0 2006.285.11:20:14.97#ibcon#flushed, iclass 19, count 0 2006.285.11:20:14.97#ibcon#about to write, iclass 19, count 0 2006.285.11:20:14.97#ibcon#wrote, iclass 19, count 0 2006.285.11:20:14.97#ibcon#about to read 3, iclass 19, count 0 2006.285.11:20:14.99#ibcon#read 3, iclass 19, count 0 2006.285.11:20:14.99#ibcon#about to read 4, iclass 19, count 0 2006.285.11:20:14.99#ibcon#read 4, iclass 19, count 0 2006.285.11:20:14.99#ibcon#about to read 5, iclass 19, count 0 2006.285.11:20:14.99#ibcon#read 5, iclass 19, count 0 2006.285.11:20:14.99#ibcon#about to read 6, iclass 19, count 0 2006.285.11:20:14.99#ibcon#read 6, iclass 19, count 0 2006.285.11:20:14.99#ibcon#end of sib2, iclass 19, count 0 2006.285.11:20:14.99#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:20:14.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:20:14.99#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:20:14.99#ibcon#*before write, iclass 19, count 0 2006.285.11:20:14.99#ibcon#enter sib2, iclass 19, count 0 2006.285.11:20:14.99#ibcon#flushed, iclass 19, count 0 2006.285.11:20:14.99#ibcon#about to write, iclass 19, count 0 2006.285.11:20:14.99#ibcon#wrote, iclass 19, count 0 2006.285.11:20:14.99#ibcon#about to read 3, iclass 19, count 0 2006.285.11:20:15.03#ibcon#read 3, iclass 19, count 0 2006.285.11:20:15.03#ibcon#about to read 4, iclass 19, count 0 2006.285.11:20:15.03#ibcon#read 4, iclass 19, count 0 2006.285.11:20:15.03#ibcon#about to read 5, iclass 19, count 0 2006.285.11:20:15.03#ibcon#read 5, iclass 19, count 0 2006.285.11:20:15.03#ibcon#about to read 6, iclass 19, count 0 2006.285.11:20:15.03#ibcon#read 6, iclass 19, count 0 2006.285.11:20:15.03#ibcon#end of sib2, iclass 19, count 0 2006.285.11:20:15.03#ibcon#*after write, iclass 19, count 0 2006.285.11:20:15.03#ibcon#*before return 0, iclass 19, count 0 2006.285.11:20:15.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:20:15.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:20:15.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:20:15.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:20:15.03$vck44/vb=2,5 2006.285.11:20:15.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.11:20:15.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.11:20:15.03#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:15.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:20:15.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:20:15.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:20:15.09#ibcon#enter wrdev, iclass 21, count 2 2006.285.11:20:15.09#ibcon#first serial, iclass 21, count 2 2006.285.11:20:15.09#ibcon#enter sib2, iclass 21, count 2 2006.285.11:20:15.09#ibcon#flushed, iclass 21, count 2 2006.285.11:20:15.09#ibcon#about to write, iclass 21, count 2 2006.285.11:20:15.09#ibcon#wrote, iclass 21, count 2 2006.285.11:20:15.09#ibcon#about to read 3, iclass 21, count 2 2006.285.11:20:15.11#ibcon#read 3, iclass 21, count 2 2006.285.11:20:15.11#ibcon#about to read 4, iclass 21, count 2 2006.285.11:20:15.11#ibcon#read 4, iclass 21, count 2 2006.285.11:20:15.11#ibcon#about to read 5, iclass 21, count 2 2006.285.11:20:15.11#ibcon#read 5, iclass 21, count 2 2006.285.11:20:15.11#ibcon#about to read 6, iclass 21, count 2 2006.285.11:20:15.11#ibcon#read 6, iclass 21, count 2 2006.285.11:20:15.11#ibcon#end of sib2, iclass 21, count 2 2006.285.11:20:15.11#ibcon#*mode == 0, iclass 21, count 2 2006.285.11:20:15.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.11:20:15.11#ibcon#[27=AT02-05\r\n] 2006.285.11:20:15.11#ibcon#*before write, iclass 21, count 2 2006.285.11:20:15.11#ibcon#enter sib2, iclass 21, count 2 2006.285.11:20:15.11#ibcon#flushed, iclass 21, count 2 2006.285.11:20:15.11#ibcon#about to write, iclass 21, count 2 2006.285.11:20:15.11#ibcon#wrote, iclass 21, count 2 2006.285.11:20:15.11#ibcon#about to read 3, iclass 21, count 2 2006.285.11:20:15.14#ibcon#read 3, iclass 21, count 2 2006.285.11:20:15.14#ibcon#about to read 4, iclass 21, count 2 2006.285.11:20:15.14#ibcon#read 4, iclass 21, count 2 2006.285.11:20:15.14#ibcon#about to read 5, iclass 21, count 2 2006.285.11:20:15.14#ibcon#read 5, iclass 21, count 2 2006.285.11:20:15.14#ibcon#about to read 6, iclass 21, count 2 2006.285.11:20:15.14#ibcon#read 6, iclass 21, count 2 2006.285.11:20:15.14#ibcon#end of sib2, iclass 21, count 2 2006.285.11:20:15.14#ibcon#*after write, iclass 21, count 2 2006.285.11:20:15.14#ibcon#*before return 0, iclass 21, count 2 2006.285.11:20:15.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:20:15.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:20:15.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.11:20:15.14#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:15.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:20:15.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:20:15.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:20:15.26#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:20:15.26#ibcon#first serial, iclass 21, count 0 2006.285.11:20:15.26#ibcon#enter sib2, iclass 21, count 0 2006.285.11:20:15.26#ibcon#flushed, iclass 21, count 0 2006.285.11:20:15.26#ibcon#about to write, iclass 21, count 0 2006.285.11:20:15.26#ibcon#wrote, iclass 21, count 0 2006.285.11:20:15.26#ibcon#about to read 3, iclass 21, count 0 2006.285.11:20:15.28#ibcon#read 3, iclass 21, count 0 2006.285.11:20:15.28#ibcon#about to read 4, iclass 21, count 0 2006.285.11:20:15.28#ibcon#read 4, iclass 21, count 0 2006.285.11:20:15.28#ibcon#about to read 5, iclass 21, count 0 2006.285.11:20:15.28#ibcon#read 5, iclass 21, count 0 2006.285.11:20:15.28#ibcon#about to read 6, iclass 21, count 0 2006.285.11:20:15.28#ibcon#read 6, iclass 21, count 0 2006.285.11:20:15.28#ibcon#end of sib2, iclass 21, count 0 2006.285.11:20:15.28#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:20:15.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:20:15.28#ibcon#[27=USB\r\n] 2006.285.11:20:15.28#ibcon#*before write, iclass 21, count 0 2006.285.11:20:15.28#ibcon#enter sib2, iclass 21, count 0 2006.285.11:20:15.28#ibcon#flushed, iclass 21, count 0 2006.285.11:20:15.28#ibcon#about to write, iclass 21, count 0 2006.285.11:20:15.28#ibcon#wrote, iclass 21, count 0 2006.285.11:20:15.28#ibcon#about to read 3, iclass 21, count 0 2006.285.11:20:15.31#ibcon#read 3, iclass 21, count 0 2006.285.11:20:15.31#ibcon#about to read 4, iclass 21, count 0 2006.285.11:20:15.31#ibcon#read 4, iclass 21, count 0 2006.285.11:20:15.31#ibcon#about to read 5, iclass 21, count 0 2006.285.11:20:15.31#ibcon#read 5, iclass 21, count 0 2006.285.11:20:15.31#ibcon#about to read 6, iclass 21, count 0 2006.285.11:20:15.31#ibcon#read 6, iclass 21, count 0 2006.285.11:20:15.31#ibcon#end of sib2, iclass 21, count 0 2006.285.11:20:15.31#ibcon#*after write, iclass 21, count 0 2006.285.11:20:15.31#ibcon#*before return 0, iclass 21, count 0 2006.285.11:20:15.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:20:15.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:20:15.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:20:15.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:20:15.31$vck44/vblo=3,649.99 2006.285.11:20:15.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.11:20:15.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.11:20:15.31#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:15.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:20:15.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:20:15.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:20:15.31#ibcon#enter wrdev, iclass 23, count 0 2006.285.11:20:15.31#ibcon#first serial, iclass 23, count 0 2006.285.11:20:15.31#ibcon#enter sib2, iclass 23, count 0 2006.285.11:20:15.31#ibcon#flushed, iclass 23, count 0 2006.285.11:20:15.31#ibcon#about to write, iclass 23, count 0 2006.285.11:20:15.31#ibcon#wrote, iclass 23, count 0 2006.285.11:20:15.31#ibcon#about to read 3, iclass 23, count 0 2006.285.11:20:15.33#ibcon#read 3, iclass 23, count 0 2006.285.11:20:15.33#ibcon#about to read 4, iclass 23, count 0 2006.285.11:20:15.33#ibcon#read 4, iclass 23, count 0 2006.285.11:20:15.33#ibcon#about to read 5, iclass 23, count 0 2006.285.11:20:15.33#ibcon#read 5, iclass 23, count 0 2006.285.11:20:15.33#ibcon#about to read 6, iclass 23, count 0 2006.285.11:20:15.33#ibcon#read 6, iclass 23, count 0 2006.285.11:20:15.33#ibcon#end of sib2, iclass 23, count 0 2006.285.11:20:15.33#ibcon#*mode == 0, iclass 23, count 0 2006.285.11:20:15.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.11:20:15.33#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:20:15.33#ibcon#*before write, iclass 23, count 0 2006.285.11:20:15.33#ibcon#enter sib2, iclass 23, count 0 2006.285.11:20:15.33#ibcon#flushed, iclass 23, count 0 2006.285.11:20:15.33#ibcon#about to write, iclass 23, count 0 2006.285.11:20:15.33#ibcon#wrote, iclass 23, count 0 2006.285.11:20:15.33#ibcon#about to read 3, iclass 23, count 0 2006.285.11:20:15.37#ibcon#read 3, iclass 23, count 0 2006.285.11:20:15.37#ibcon#about to read 4, iclass 23, count 0 2006.285.11:20:15.37#ibcon#read 4, iclass 23, count 0 2006.285.11:20:15.37#ibcon#about to read 5, iclass 23, count 0 2006.285.11:20:15.37#ibcon#read 5, iclass 23, count 0 2006.285.11:20:15.37#ibcon#about to read 6, iclass 23, count 0 2006.285.11:20:15.37#ibcon#read 6, iclass 23, count 0 2006.285.11:20:15.37#ibcon#end of sib2, iclass 23, count 0 2006.285.11:20:15.37#ibcon#*after write, iclass 23, count 0 2006.285.11:20:15.37#ibcon#*before return 0, iclass 23, count 0 2006.285.11:20:15.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:20:15.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:20:15.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.11:20:15.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.11:20:15.37$vck44/vb=3,4 2006.285.11:20:15.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.11:20:15.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.11:20:15.37#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:15.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:20:15.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:20:15.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:20:15.43#ibcon#enter wrdev, iclass 25, count 2 2006.285.11:20:15.43#ibcon#first serial, iclass 25, count 2 2006.285.11:20:15.43#ibcon#enter sib2, iclass 25, count 2 2006.285.11:20:15.43#ibcon#flushed, iclass 25, count 2 2006.285.11:20:15.43#ibcon#about to write, iclass 25, count 2 2006.285.11:20:15.43#ibcon#wrote, iclass 25, count 2 2006.285.11:20:15.43#ibcon#about to read 3, iclass 25, count 2 2006.285.11:20:15.45#ibcon#read 3, iclass 25, count 2 2006.285.11:20:15.45#ibcon#about to read 4, iclass 25, count 2 2006.285.11:20:15.45#ibcon#read 4, iclass 25, count 2 2006.285.11:20:15.45#ibcon#about to read 5, iclass 25, count 2 2006.285.11:20:15.45#ibcon#read 5, iclass 25, count 2 2006.285.11:20:15.45#ibcon#about to read 6, iclass 25, count 2 2006.285.11:20:15.45#ibcon#read 6, iclass 25, count 2 2006.285.11:20:15.45#ibcon#end of sib2, iclass 25, count 2 2006.285.11:20:15.45#ibcon#*mode == 0, iclass 25, count 2 2006.285.11:20:15.45#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.11:20:15.45#ibcon#[27=AT03-04\r\n] 2006.285.11:20:15.45#ibcon#*before write, iclass 25, count 2 2006.285.11:20:15.45#ibcon#enter sib2, iclass 25, count 2 2006.285.11:20:15.45#ibcon#flushed, iclass 25, count 2 2006.285.11:20:15.45#ibcon#about to write, iclass 25, count 2 2006.285.11:20:15.45#ibcon#wrote, iclass 25, count 2 2006.285.11:20:15.45#ibcon#about to read 3, iclass 25, count 2 2006.285.11:20:15.48#ibcon#read 3, iclass 25, count 2 2006.285.11:20:15.48#ibcon#about to read 4, iclass 25, count 2 2006.285.11:20:15.48#ibcon#read 4, iclass 25, count 2 2006.285.11:20:15.48#ibcon#about to read 5, iclass 25, count 2 2006.285.11:20:15.48#ibcon#read 5, iclass 25, count 2 2006.285.11:20:15.48#ibcon#about to read 6, iclass 25, count 2 2006.285.11:20:15.48#ibcon#read 6, iclass 25, count 2 2006.285.11:20:15.48#ibcon#end of sib2, iclass 25, count 2 2006.285.11:20:15.48#ibcon#*after write, iclass 25, count 2 2006.285.11:20:15.48#ibcon#*before return 0, iclass 25, count 2 2006.285.11:20:15.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:20:15.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:20:15.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.11:20:15.48#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:15.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:20:15.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:20:15.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:20:15.60#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:20:15.60#ibcon#first serial, iclass 25, count 0 2006.285.11:20:15.60#ibcon#enter sib2, iclass 25, count 0 2006.285.11:20:15.60#ibcon#flushed, iclass 25, count 0 2006.285.11:20:15.60#ibcon#about to write, iclass 25, count 0 2006.285.11:20:15.60#ibcon#wrote, iclass 25, count 0 2006.285.11:20:15.60#ibcon#about to read 3, iclass 25, count 0 2006.285.11:20:15.62#ibcon#read 3, iclass 25, count 0 2006.285.11:20:15.62#ibcon#about to read 4, iclass 25, count 0 2006.285.11:20:15.62#ibcon#read 4, iclass 25, count 0 2006.285.11:20:15.62#ibcon#about to read 5, iclass 25, count 0 2006.285.11:20:15.62#ibcon#read 5, iclass 25, count 0 2006.285.11:20:15.62#ibcon#about to read 6, iclass 25, count 0 2006.285.11:20:15.62#ibcon#read 6, iclass 25, count 0 2006.285.11:20:15.62#ibcon#end of sib2, iclass 25, count 0 2006.285.11:20:15.62#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:20:15.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:20:15.62#ibcon#[27=USB\r\n] 2006.285.11:20:15.62#ibcon#*before write, iclass 25, count 0 2006.285.11:20:15.62#ibcon#enter sib2, iclass 25, count 0 2006.285.11:20:15.62#ibcon#flushed, iclass 25, count 0 2006.285.11:20:15.62#ibcon#about to write, iclass 25, count 0 2006.285.11:20:15.62#ibcon#wrote, iclass 25, count 0 2006.285.11:20:15.62#ibcon#about to read 3, iclass 25, count 0 2006.285.11:20:15.65#ibcon#read 3, iclass 25, count 0 2006.285.11:20:15.65#ibcon#about to read 4, iclass 25, count 0 2006.285.11:20:15.65#ibcon#read 4, iclass 25, count 0 2006.285.11:20:15.65#ibcon#about to read 5, iclass 25, count 0 2006.285.11:20:15.65#ibcon#read 5, iclass 25, count 0 2006.285.11:20:15.65#ibcon#about to read 6, iclass 25, count 0 2006.285.11:20:15.65#ibcon#read 6, iclass 25, count 0 2006.285.11:20:15.65#ibcon#end of sib2, iclass 25, count 0 2006.285.11:20:15.65#ibcon#*after write, iclass 25, count 0 2006.285.11:20:15.65#ibcon#*before return 0, iclass 25, count 0 2006.285.11:20:15.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:20:15.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:20:15.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:20:15.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:20:15.65$vck44/vblo=4,679.99 2006.285.11:20:15.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.11:20:15.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.11:20:15.65#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:15.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:20:15.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:20:15.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:20:15.65#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:20:15.65#ibcon#first serial, iclass 27, count 0 2006.285.11:20:15.65#ibcon#enter sib2, iclass 27, count 0 2006.285.11:20:15.65#ibcon#flushed, iclass 27, count 0 2006.285.11:20:15.65#ibcon#about to write, iclass 27, count 0 2006.285.11:20:15.65#ibcon#wrote, iclass 27, count 0 2006.285.11:20:15.65#ibcon#about to read 3, iclass 27, count 0 2006.285.11:20:15.67#ibcon#read 3, iclass 27, count 0 2006.285.11:20:15.67#ibcon#about to read 4, iclass 27, count 0 2006.285.11:20:15.67#ibcon#read 4, iclass 27, count 0 2006.285.11:20:15.67#ibcon#about to read 5, iclass 27, count 0 2006.285.11:20:15.67#ibcon#read 5, iclass 27, count 0 2006.285.11:20:15.67#ibcon#about to read 6, iclass 27, count 0 2006.285.11:20:15.67#ibcon#read 6, iclass 27, count 0 2006.285.11:20:15.67#ibcon#end of sib2, iclass 27, count 0 2006.285.11:20:15.67#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:20:15.67#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:20:15.67#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:20:15.67#ibcon#*before write, iclass 27, count 0 2006.285.11:20:15.67#ibcon#enter sib2, iclass 27, count 0 2006.285.11:20:15.67#ibcon#flushed, iclass 27, count 0 2006.285.11:20:15.67#ibcon#about to write, iclass 27, count 0 2006.285.11:20:15.67#ibcon#wrote, iclass 27, count 0 2006.285.11:20:15.67#ibcon#about to read 3, iclass 27, count 0 2006.285.11:20:15.71#ibcon#read 3, iclass 27, count 0 2006.285.11:20:15.71#ibcon#about to read 4, iclass 27, count 0 2006.285.11:20:15.71#ibcon#read 4, iclass 27, count 0 2006.285.11:20:15.71#ibcon#about to read 5, iclass 27, count 0 2006.285.11:20:15.71#ibcon#read 5, iclass 27, count 0 2006.285.11:20:15.71#ibcon#about to read 6, iclass 27, count 0 2006.285.11:20:15.71#ibcon#read 6, iclass 27, count 0 2006.285.11:20:15.71#ibcon#end of sib2, iclass 27, count 0 2006.285.11:20:15.71#ibcon#*after write, iclass 27, count 0 2006.285.11:20:15.71#ibcon#*before return 0, iclass 27, count 0 2006.285.11:20:15.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:20:15.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:20:15.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:20:15.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:20:15.71$vck44/vb=4,5 2006.285.11:20:15.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.11:20:15.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.11:20:15.71#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:15.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:20:15.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:20:15.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:20:15.77#ibcon#enter wrdev, iclass 29, count 2 2006.285.11:20:15.77#ibcon#first serial, iclass 29, count 2 2006.285.11:20:15.77#ibcon#enter sib2, iclass 29, count 2 2006.285.11:20:15.77#ibcon#flushed, iclass 29, count 2 2006.285.11:20:15.77#ibcon#about to write, iclass 29, count 2 2006.285.11:20:15.77#ibcon#wrote, iclass 29, count 2 2006.285.11:20:15.77#ibcon#about to read 3, iclass 29, count 2 2006.285.11:20:15.79#ibcon#read 3, iclass 29, count 2 2006.285.11:20:15.79#ibcon#about to read 4, iclass 29, count 2 2006.285.11:20:15.79#ibcon#read 4, iclass 29, count 2 2006.285.11:20:15.79#ibcon#about to read 5, iclass 29, count 2 2006.285.11:20:15.79#ibcon#read 5, iclass 29, count 2 2006.285.11:20:15.79#ibcon#about to read 6, iclass 29, count 2 2006.285.11:20:15.79#ibcon#read 6, iclass 29, count 2 2006.285.11:20:15.79#ibcon#end of sib2, iclass 29, count 2 2006.285.11:20:15.79#ibcon#*mode == 0, iclass 29, count 2 2006.285.11:20:15.79#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.11:20:15.79#ibcon#[27=AT04-05\r\n] 2006.285.11:20:15.79#ibcon#*before write, iclass 29, count 2 2006.285.11:20:15.79#ibcon#enter sib2, iclass 29, count 2 2006.285.11:20:15.79#ibcon#flushed, iclass 29, count 2 2006.285.11:20:15.79#ibcon#about to write, iclass 29, count 2 2006.285.11:20:15.79#ibcon#wrote, iclass 29, count 2 2006.285.11:20:15.79#ibcon#about to read 3, iclass 29, count 2 2006.285.11:20:15.82#ibcon#read 3, iclass 29, count 2 2006.285.11:20:15.82#ibcon#about to read 4, iclass 29, count 2 2006.285.11:20:15.82#ibcon#read 4, iclass 29, count 2 2006.285.11:20:15.82#ibcon#about to read 5, iclass 29, count 2 2006.285.11:20:15.82#ibcon#read 5, iclass 29, count 2 2006.285.11:20:15.82#ibcon#about to read 6, iclass 29, count 2 2006.285.11:20:15.82#ibcon#read 6, iclass 29, count 2 2006.285.11:20:15.82#ibcon#end of sib2, iclass 29, count 2 2006.285.11:20:15.82#ibcon#*after write, iclass 29, count 2 2006.285.11:20:15.82#ibcon#*before return 0, iclass 29, count 2 2006.285.11:20:15.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:20:15.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:20:15.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.11:20:15.82#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:15.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:20:15.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:20:15.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:20:15.94#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:20:15.94#ibcon#first serial, iclass 29, count 0 2006.285.11:20:15.94#ibcon#enter sib2, iclass 29, count 0 2006.285.11:20:15.94#ibcon#flushed, iclass 29, count 0 2006.285.11:20:15.94#ibcon#about to write, iclass 29, count 0 2006.285.11:20:15.94#ibcon#wrote, iclass 29, count 0 2006.285.11:20:15.94#ibcon#about to read 3, iclass 29, count 0 2006.285.11:20:15.96#ibcon#read 3, iclass 29, count 0 2006.285.11:20:15.96#ibcon#about to read 4, iclass 29, count 0 2006.285.11:20:15.96#ibcon#read 4, iclass 29, count 0 2006.285.11:20:15.96#ibcon#about to read 5, iclass 29, count 0 2006.285.11:20:15.96#ibcon#read 5, iclass 29, count 0 2006.285.11:20:15.96#ibcon#about to read 6, iclass 29, count 0 2006.285.11:20:15.96#ibcon#read 6, iclass 29, count 0 2006.285.11:20:15.96#ibcon#end of sib2, iclass 29, count 0 2006.285.11:20:15.96#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:20:15.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:20:15.96#ibcon#[27=USB\r\n] 2006.285.11:20:15.96#ibcon#*before write, iclass 29, count 0 2006.285.11:20:15.96#ibcon#enter sib2, iclass 29, count 0 2006.285.11:20:15.96#ibcon#flushed, iclass 29, count 0 2006.285.11:20:15.96#ibcon#about to write, iclass 29, count 0 2006.285.11:20:15.96#ibcon#wrote, iclass 29, count 0 2006.285.11:20:15.96#ibcon#about to read 3, iclass 29, count 0 2006.285.11:20:15.99#ibcon#read 3, iclass 29, count 0 2006.285.11:20:15.99#ibcon#about to read 4, iclass 29, count 0 2006.285.11:20:15.99#ibcon#read 4, iclass 29, count 0 2006.285.11:20:15.99#ibcon#about to read 5, iclass 29, count 0 2006.285.11:20:15.99#ibcon#read 5, iclass 29, count 0 2006.285.11:20:15.99#ibcon#about to read 6, iclass 29, count 0 2006.285.11:20:15.99#ibcon#read 6, iclass 29, count 0 2006.285.11:20:15.99#ibcon#end of sib2, iclass 29, count 0 2006.285.11:20:15.99#ibcon#*after write, iclass 29, count 0 2006.285.11:20:15.99#ibcon#*before return 0, iclass 29, count 0 2006.285.11:20:15.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:20:15.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:20:15.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:20:15.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:20:15.99$vck44/vblo=5,709.99 2006.285.11:20:15.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.11:20:15.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.11:20:15.99#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:15.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:20:15.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:20:15.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:20:15.99#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:20:15.99#ibcon#first serial, iclass 31, count 0 2006.285.11:20:15.99#ibcon#enter sib2, iclass 31, count 0 2006.285.11:20:15.99#ibcon#flushed, iclass 31, count 0 2006.285.11:20:15.99#ibcon#about to write, iclass 31, count 0 2006.285.11:20:15.99#ibcon#wrote, iclass 31, count 0 2006.285.11:20:15.99#ibcon#about to read 3, iclass 31, count 0 2006.285.11:20:16.01#ibcon#read 3, iclass 31, count 0 2006.285.11:20:16.01#ibcon#about to read 4, iclass 31, count 0 2006.285.11:20:16.01#ibcon#read 4, iclass 31, count 0 2006.285.11:20:16.01#ibcon#about to read 5, iclass 31, count 0 2006.285.11:20:16.01#ibcon#read 5, iclass 31, count 0 2006.285.11:20:16.01#ibcon#about to read 6, iclass 31, count 0 2006.285.11:20:16.01#ibcon#read 6, iclass 31, count 0 2006.285.11:20:16.01#ibcon#end of sib2, iclass 31, count 0 2006.285.11:20:16.01#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:20:16.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:20:16.01#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:20:16.01#ibcon#*before write, iclass 31, count 0 2006.285.11:20:16.01#ibcon#enter sib2, iclass 31, count 0 2006.285.11:20:16.01#ibcon#flushed, iclass 31, count 0 2006.285.11:20:16.01#ibcon#about to write, iclass 31, count 0 2006.285.11:20:16.01#ibcon#wrote, iclass 31, count 0 2006.285.11:20:16.01#ibcon#about to read 3, iclass 31, count 0 2006.285.11:20:16.05#ibcon#read 3, iclass 31, count 0 2006.285.11:20:16.05#ibcon#about to read 4, iclass 31, count 0 2006.285.11:20:16.05#ibcon#read 4, iclass 31, count 0 2006.285.11:20:16.05#ibcon#about to read 5, iclass 31, count 0 2006.285.11:20:16.05#ibcon#read 5, iclass 31, count 0 2006.285.11:20:16.05#ibcon#about to read 6, iclass 31, count 0 2006.285.11:20:16.05#ibcon#read 6, iclass 31, count 0 2006.285.11:20:16.05#ibcon#end of sib2, iclass 31, count 0 2006.285.11:20:16.05#ibcon#*after write, iclass 31, count 0 2006.285.11:20:16.05#ibcon#*before return 0, iclass 31, count 0 2006.285.11:20:16.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:20:16.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:20:16.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:20:16.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:20:16.05$vck44/vb=5,4 2006.285.11:20:16.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.11:20:16.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.11:20:16.05#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:16.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:20:16.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:20:16.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:20:16.11#ibcon#enter wrdev, iclass 33, count 2 2006.285.11:20:16.11#ibcon#first serial, iclass 33, count 2 2006.285.11:20:16.11#ibcon#enter sib2, iclass 33, count 2 2006.285.11:20:16.11#ibcon#flushed, iclass 33, count 2 2006.285.11:20:16.11#ibcon#about to write, iclass 33, count 2 2006.285.11:20:16.11#ibcon#wrote, iclass 33, count 2 2006.285.11:20:16.11#ibcon#about to read 3, iclass 33, count 2 2006.285.11:20:16.13#ibcon#read 3, iclass 33, count 2 2006.285.11:20:16.13#ibcon#about to read 4, iclass 33, count 2 2006.285.11:20:16.13#ibcon#read 4, iclass 33, count 2 2006.285.11:20:16.13#ibcon#about to read 5, iclass 33, count 2 2006.285.11:20:16.13#ibcon#read 5, iclass 33, count 2 2006.285.11:20:16.13#ibcon#about to read 6, iclass 33, count 2 2006.285.11:20:16.13#ibcon#read 6, iclass 33, count 2 2006.285.11:20:16.13#ibcon#end of sib2, iclass 33, count 2 2006.285.11:20:16.13#ibcon#*mode == 0, iclass 33, count 2 2006.285.11:20:16.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.11:20:16.13#ibcon#[27=AT05-04\r\n] 2006.285.11:20:16.13#ibcon#*before write, iclass 33, count 2 2006.285.11:20:16.13#ibcon#enter sib2, iclass 33, count 2 2006.285.11:20:16.13#ibcon#flushed, iclass 33, count 2 2006.285.11:20:16.13#ibcon#about to write, iclass 33, count 2 2006.285.11:20:16.13#ibcon#wrote, iclass 33, count 2 2006.285.11:20:16.13#ibcon#about to read 3, iclass 33, count 2 2006.285.11:20:16.16#ibcon#read 3, iclass 33, count 2 2006.285.11:20:16.16#ibcon#about to read 4, iclass 33, count 2 2006.285.11:20:16.16#ibcon#read 4, iclass 33, count 2 2006.285.11:20:16.16#ibcon#about to read 5, iclass 33, count 2 2006.285.11:20:16.16#ibcon#read 5, iclass 33, count 2 2006.285.11:20:16.16#ibcon#about to read 6, iclass 33, count 2 2006.285.11:20:16.16#ibcon#read 6, iclass 33, count 2 2006.285.11:20:16.16#ibcon#end of sib2, iclass 33, count 2 2006.285.11:20:16.16#ibcon#*after write, iclass 33, count 2 2006.285.11:20:16.16#ibcon#*before return 0, iclass 33, count 2 2006.285.11:20:16.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:20:16.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:20:16.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.11:20:16.16#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:16.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:20:16.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:20:16.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:20:16.28#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:20:16.28#ibcon#first serial, iclass 33, count 0 2006.285.11:20:16.28#ibcon#enter sib2, iclass 33, count 0 2006.285.11:20:16.28#ibcon#flushed, iclass 33, count 0 2006.285.11:20:16.28#ibcon#about to write, iclass 33, count 0 2006.285.11:20:16.28#ibcon#wrote, iclass 33, count 0 2006.285.11:20:16.28#ibcon#about to read 3, iclass 33, count 0 2006.285.11:20:16.30#ibcon#read 3, iclass 33, count 0 2006.285.11:20:16.30#ibcon#about to read 4, iclass 33, count 0 2006.285.11:20:16.30#ibcon#read 4, iclass 33, count 0 2006.285.11:20:16.30#ibcon#about to read 5, iclass 33, count 0 2006.285.11:20:16.30#ibcon#read 5, iclass 33, count 0 2006.285.11:20:16.30#ibcon#about to read 6, iclass 33, count 0 2006.285.11:20:16.30#ibcon#read 6, iclass 33, count 0 2006.285.11:20:16.30#ibcon#end of sib2, iclass 33, count 0 2006.285.11:20:16.30#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:20:16.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:20:16.30#ibcon#[27=USB\r\n] 2006.285.11:20:16.30#ibcon#*before write, iclass 33, count 0 2006.285.11:20:16.30#ibcon#enter sib2, iclass 33, count 0 2006.285.11:20:16.30#ibcon#flushed, iclass 33, count 0 2006.285.11:20:16.30#ibcon#about to write, iclass 33, count 0 2006.285.11:20:16.30#ibcon#wrote, iclass 33, count 0 2006.285.11:20:16.30#ibcon#about to read 3, iclass 33, count 0 2006.285.11:20:16.33#ibcon#read 3, iclass 33, count 0 2006.285.11:20:16.33#ibcon#about to read 4, iclass 33, count 0 2006.285.11:20:16.33#ibcon#read 4, iclass 33, count 0 2006.285.11:20:16.33#ibcon#about to read 5, iclass 33, count 0 2006.285.11:20:16.33#ibcon#read 5, iclass 33, count 0 2006.285.11:20:16.33#ibcon#about to read 6, iclass 33, count 0 2006.285.11:20:16.33#ibcon#read 6, iclass 33, count 0 2006.285.11:20:16.33#ibcon#end of sib2, iclass 33, count 0 2006.285.11:20:16.33#ibcon#*after write, iclass 33, count 0 2006.285.11:20:16.33#ibcon#*before return 0, iclass 33, count 0 2006.285.11:20:16.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:20:16.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:20:16.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:20:16.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:20:16.33$vck44/vblo=6,719.99 2006.285.11:20:16.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.11:20:16.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.11:20:16.33#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:16.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:20:16.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:20:16.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:20:16.33#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:20:16.33#ibcon#first serial, iclass 35, count 0 2006.285.11:20:16.33#ibcon#enter sib2, iclass 35, count 0 2006.285.11:20:16.33#ibcon#flushed, iclass 35, count 0 2006.285.11:20:16.33#ibcon#about to write, iclass 35, count 0 2006.285.11:20:16.33#ibcon#wrote, iclass 35, count 0 2006.285.11:20:16.33#ibcon#about to read 3, iclass 35, count 0 2006.285.11:20:16.35#ibcon#read 3, iclass 35, count 0 2006.285.11:20:16.35#ibcon#about to read 4, iclass 35, count 0 2006.285.11:20:16.35#ibcon#read 4, iclass 35, count 0 2006.285.11:20:16.35#ibcon#about to read 5, iclass 35, count 0 2006.285.11:20:16.35#ibcon#read 5, iclass 35, count 0 2006.285.11:20:16.35#ibcon#about to read 6, iclass 35, count 0 2006.285.11:20:16.35#ibcon#read 6, iclass 35, count 0 2006.285.11:20:16.35#ibcon#end of sib2, iclass 35, count 0 2006.285.11:20:16.35#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:20:16.35#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:20:16.35#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:20:16.35#ibcon#*before write, iclass 35, count 0 2006.285.11:20:16.35#ibcon#enter sib2, iclass 35, count 0 2006.285.11:20:16.35#ibcon#flushed, iclass 35, count 0 2006.285.11:20:16.35#ibcon#about to write, iclass 35, count 0 2006.285.11:20:16.35#ibcon#wrote, iclass 35, count 0 2006.285.11:20:16.35#ibcon#about to read 3, iclass 35, count 0 2006.285.11:20:16.39#ibcon#read 3, iclass 35, count 0 2006.285.11:20:16.39#ibcon#about to read 4, iclass 35, count 0 2006.285.11:20:16.39#ibcon#read 4, iclass 35, count 0 2006.285.11:20:16.39#ibcon#about to read 5, iclass 35, count 0 2006.285.11:20:16.39#ibcon#read 5, iclass 35, count 0 2006.285.11:20:16.39#ibcon#about to read 6, iclass 35, count 0 2006.285.11:20:16.39#ibcon#read 6, iclass 35, count 0 2006.285.11:20:16.39#ibcon#end of sib2, iclass 35, count 0 2006.285.11:20:16.39#ibcon#*after write, iclass 35, count 0 2006.285.11:20:16.39#ibcon#*before return 0, iclass 35, count 0 2006.285.11:20:16.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:20:16.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:20:16.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:20:16.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:20:16.39$vck44/vb=6,3 2006.285.11:20:16.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.11:20:16.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.11:20:16.39#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:16.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:20:16.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:20:16.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:20:16.45#ibcon#enter wrdev, iclass 37, count 2 2006.285.11:20:16.45#ibcon#first serial, iclass 37, count 2 2006.285.11:20:16.45#ibcon#enter sib2, iclass 37, count 2 2006.285.11:20:16.45#ibcon#flushed, iclass 37, count 2 2006.285.11:20:16.45#ibcon#about to write, iclass 37, count 2 2006.285.11:20:16.45#ibcon#wrote, iclass 37, count 2 2006.285.11:20:16.45#ibcon#about to read 3, iclass 37, count 2 2006.285.11:20:16.47#ibcon#read 3, iclass 37, count 2 2006.285.11:20:16.47#ibcon#about to read 4, iclass 37, count 2 2006.285.11:20:16.47#ibcon#read 4, iclass 37, count 2 2006.285.11:20:16.47#ibcon#about to read 5, iclass 37, count 2 2006.285.11:20:16.47#ibcon#read 5, iclass 37, count 2 2006.285.11:20:16.47#ibcon#about to read 6, iclass 37, count 2 2006.285.11:20:16.47#ibcon#read 6, iclass 37, count 2 2006.285.11:20:16.47#ibcon#end of sib2, iclass 37, count 2 2006.285.11:20:16.47#ibcon#*mode == 0, iclass 37, count 2 2006.285.11:20:16.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.11:20:16.47#ibcon#[27=AT06-03\r\n] 2006.285.11:20:16.47#ibcon#*before write, iclass 37, count 2 2006.285.11:20:16.47#ibcon#enter sib2, iclass 37, count 2 2006.285.11:20:16.47#ibcon#flushed, iclass 37, count 2 2006.285.11:20:16.47#ibcon#about to write, iclass 37, count 2 2006.285.11:20:16.47#ibcon#wrote, iclass 37, count 2 2006.285.11:20:16.47#ibcon#about to read 3, iclass 37, count 2 2006.285.11:20:16.50#ibcon#read 3, iclass 37, count 2 2006.285.11:20:16.50#ibcon#about to read 4, iclass 37, count 2 2006.285.11:20:16.50#ibcon#read 4, iclass 37, count 2 2006.285.11:20:16.50#ibcon#about to read 5, iclass 37, count 2 2006.285.11:20:16.50#ibcon#read 5, iclass 37, count 2 2006.285.11:20:16.50#ibcon#about to read 6, iclass 37, count 2 2006.285.11:20:16.50#ibcon#read 6, iclass 37, count 2 2006.285.11:20:16.50#ibcon#end of sib2, iclass 37, count 2 2006.285.11:20:16.50#ibcon#*after write, iclass 37, count 2 2006.285.11:20:16.50#ibcon#*before return 0, iclass 37, count 2 2006.285.11:20:16.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:20:16.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:20:16.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.11:20:16.50#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:16.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:20:16.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:20:16.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:20:16.62#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:20:16.62#ibcon#first serial, iclass 37, count 0 2006.285.11:20:16.62#ibcon#enter sib2, iclass 37, count 0 2006.285.11:20:16.62#ibcon#flushed, iclass 37, count 0 2006.285.11:20:16.62#ibcon#about to write, iclass 37, count 0 2006.285.11:20:16.62#ibcon#wrote, iclass 37, count 0 2006.285.11:20:16.62#ibcon#about to read 3, iclass 37, count 0 2006.285.11:20:16.64#ibcon#read 3, iclass 37, count 0 2006.285.11:20:16.64#ibcon#about to read 4, iclass 37, count 0 2006.285.11:20:16.64#ibcon#read 4, iclass 37, count 0 2006.285.11:20:16.64#ibcon#about to read 5, iclass 37, count 0 2006.285.11:20:16.64#ibcon#read 5, iclass 37, count 0 2006.285.11:20:16.64#ibcon#about to read 6, iclass 37, count 0 2006.285.11:20:16.64#ibcon#read 6, iclass 37, count 0 2006.285.11:20:16.64#ibcon#end of sib2, iclass 37, count 0 2006.285.11:20:16.64#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:20:16.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:20:16.64#ibcon#[27=USB\r\n] 2006.285.11:20:16.64#ibcon#*before write, iclass 37, count 0 2006.285.11:20:16.64#ibcon#enter sib2, iclass 37, count 0 2006.285.11:20:16.64#ibcon#flushed, iclass 37, count 0 2006.285.11:20:16.64#ibcon#about to write, iclass 37, count 0 2006.285.11:20:16.64#ibcon#wrote, iclass 37, count 0 2006.285.11:20:16.64#ibcon#about to read 3, iclass 37, count 0 2006.285.11:20:16.67#ibcon#read 3, iclass 37, count 0 2006.285.11:20:16.67#ibcon#about to read 4, iclass 37, count 0 2006.285.11:20:16.67#ibcon#read 4, iclass 37, count 0 2006.285.11:20:16.67#ibcon#about to read 5, iclass 37, count 0 2006.285.11:20:16.67#ibcon#read 5, iclass 37, count 0 2006.285.11:20:16.67#ibcon#about to read 6, iclass 37, count 0 2006.285.11:20:16.67#ibcon#read 6, iclass 37, count 0 2006.285.11:20:16.67#ibcon#end of sib2, iclass 37, count 0 2006.285.11:20:16.67#ibcon#*after write, iclass 37, count 0 2006.285.11:20:16.67#ibcon#*before return 0, iclass 37, count 0 2006.285.11:20:16.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:20:16.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:20:16.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:20:16.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:20:16.67$vck44/vblo=7,734.99 2006.285.11:20:16.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.11:20:16.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.11:20:16.67#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:16.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:20:16.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:20:16.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:20:16.67#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:20:16.67#ibcon#first serial, iclass 39, count 0 2006.285.11:20:16.67#ibcon#enter sib2, iclass 39, count 0 2006.285.11:20:16.67#ibcon#flushed, iclass 39, count 0 2006.285.11:20:16.67#ibcon#about to write, iclass 39, count 0 2006.285.11:20:16.67#ibcon#wrote, iclass 39, count 0 2006.285.11:20:16.67#ibcon#about to read 3, iclass 39, count 0 2006.285.11:20:16.69#ibcon#read 3, iclass 39, count 0 2006.285.11:20:16.69#ibcon#about to read 4, iclass 39, count 0 2006.285.11:20:16.69#ibcon#read 4, iclass 39, count 0 2006.285.11:20:16.69#ibcon#about to read 5, iclass 39, count 0 2006.285.11:20:16.69#ibcon#read 5, iclass 39, count 0 2006.285.11:20:16.69#ibcon#about to read 6, iclass 39, count 0 2006.285.11:20:16.69#ibcon#read 6, iclass 39, count 0 2006.285.11:20:16.69#ibcon#end of sib2, iclass 39, count 0 2006.285.11:20:16.69#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:20:16.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:20:16.69#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:20:16.69#ibcon#*before write, iclass 39, count 0 2006.285.11:20:16.69#ibcon#enter sib2, iclass 39, count 0 2006.285.11:20:16.69#ibcon#flushed, iclass 39, count 0 2006.285.11:20:16.69#ibcon#about to write, iclass 39, count 0 2006.285.11:20:16.69#ibcon#wrote, iclass 39, count 0 2006.285.11:20:16.69#ibcon#about to read 3, iclass 39, count 0 2006.285.11:20:16.73#ibcon#read 3, iclass 39, count 0 2006.285.11:20:16.73#ibcon#about to read 4, iclass 39, count 0 2006.285.11:20:16.73#ibcon#read 4, iclass 39, count 0 2006.285.11:20:16.73#ibcon#about to read 5, iclass 39, count 0 2006.285.11:20:16.73#ibcon#read 5, iclass 39, count 0 2006.285.11:20:16.73#ibcon#about to read 6, iclass 39, count 0 2006.285.11:20:16.73#ibcon#read 6, iclass 39, count 0 2006.285.11:20:16.73#ibcon#end of sib2, iclass 39, count 0 2006.285.11:20:16.73#ibcon#*after write, iclass 39, count 0 2006.285.11:20:16.73#ibcon#*before return 0, iclass 39, count 0 2006.285.11:20:16.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:20:16.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:20:16.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:20:16.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:20:16.73$vck44/vb=7,4 2006.285.11:20:16.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.11:20:16.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.11:20:16.73#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:16.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:20:16.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:20:16.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:20:16.79#ibcon#enter wrdev, iclass 3, count 2 2006.285.11:20:16.79#ibcon#first serial, iclass 3, count 2 2006.285.11:20:16.79#ibcon#enter sib2, iclass 3, count 2 2006.285.11:20:16.79#ibcon#flushed, iclass 3, count 2 2006.285.11:20:16.79#ibcon#about to write, iclass 3, count 2 2006.285.11:20:16.79#ibcon#wrote, iclass 3, count 2 2006.285.11:20:16.79#ibcon#about to read 3, iclass 3, count 2 2006.285.11:20:16.81#ibcon#read 3, iclass 3, count 2 2006.285.11:20:16.81#ibcon#about to read 4, iclass 3, count 2 2006.285.11:20:16.81#ibcon#read 4, iclass 3, count 2 2006.285.11:20:16.81#ibcon#about to read 5, iclass 3, count 2 2006.285.11:20:16.81#ibcon#read 5, iclass 3, count 2 2006.285.11:20:16.81#ibcon#about to read 6, iclass 3, count 2 2006.285.11:20:16.81#ibcon#read 6, iclass 3, count 2 2006.285.11:20:16.81#ibcon#end of sib2, iclass 3, count 2 2006.285.11:20:16.81#ibcon#*mode == 0, iclass 3, count 2 2006.285.11:20:16.81#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.11:20:16.81#ibcon#[27=AT07-04\r\n] 2006.285.11:20:16.81#ibcon#*before write, iclass 3, count 2 2006.285.11:20:16.81#ibcon#enter sib2, iclass 3, count 2 2006.285.11:20:16.81#ibcon#flushed, iclass 3, count 2 2006.285.11:20:16.81#ibcon#about to write, iclass 3, count 2 2006.285.11:20:16.81#ibcon#wrote, iclass 3, count 2 2006.285.11:20:16.81#ibcon#about to read 3, iclass 3, count 2 2006.285.11:20:16.84#ibcon#read 3, iclass 3, count 2 2006.285.11:20:16.84#ibcon#about to read 4, iclass 3, count 2 2006.285.11:20:16.84#ibcon#read 4, iclass 3, count 2 2006.285.11:20:16.84#ibcon#about to read 5, iclass 3, count 2 2006.285.11:20:16.84#ibcon#read 5, iclass 3, count 2 2006.285.11:20:16.84#ibcon#about to read 6, iclass 3, count 2 2006.285.11:20:16.84#ibcon#read 6, iclass 3, count 2 2006.285.11:20:16.84#ibcon#end of sib2, iclass 3, count 2 2006.285.11:20:16.84#ibcon#*after write, iclass 3, count 2 2006.285.11:20:16.84#ibcon#*before return 0, iclass 3, count 2 2006.285.11:20:16.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:20:16.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:20:16.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.11:20:16.84#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:16.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:20:16.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:20:16.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:20:16.96#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:20:16.96#ibcon#first serial, iclass 3, count 0 2006.285.11:20:16.96#ibcon#enter sib2, iclass 3, count 0 2006.285.11:20:16.96#ibcon#flushed, iclass 3, count 0 2006.285.11:20:16.96#ibcon#about to write, iclass 3, count 0 2006.285.11:20:16.96#ibcon#wrote, iclass 3, count 0 2006.285.11:20:16.96#ibcon#about to read 3, iclass 3, count 0 2006.285.11:20:16.98#ibcon#read 3, iclass 3, count 0 2006.285.11:20:16.98#ibcon#about to read 4, iclass 3, count 0 2006.285.11:20:16.98#ibcon#read 4, iclass 3, count 0 2006.285.11:20:16.98#ibcon#about to read 5, iclass 3, count 0 2006.285.11:20:16.98#ibcon#read 5, iclass 3, count 0 2006.285.11:20:16.98#ibcon#about to read 6, iclass 3, count 0 2006.285.11:20:16.98#ibcon#read 6, iclass 3, count 0 2006.285.11:20:16.98#ibcon#end of sib2, iclass 3, count 0 2006.285.11:20:16.98#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:20:16.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:20:16.98#ibcon#[27=USB\r\n] 2006.285.11:20:16.98#ibcon#*before write, iclass 3, count 0 2006.285.11:20:16.98#ibcon#enter sib2, iclass 3, count 0 2006.285.11:20:16.98#ibcon#flushed, iclass 3, count 0 2006.285.11:20:16.98#ibcon#about to write, iclass 3, count 0 2006.285.11:20:16.98#ibcon#wrote, iclass 3, count 0 2006.285.11:20:16.98#ibcon#about to read 3, iclass 3, count 0 2006.285.11:20:17.01#ibcon#read 3, iclass 3, count 0 2006.285.11:20:17.01#ibcon#about to read 4, iclass 3, count 0 2006.285.11:20:17.01#ibcon#read 4, iclass 3, count 0 2006.285.11:20:17.01#ibcon#about to read 5, iclass 3, count 0 2006.285.11:20:17.01#ibcon#read 5, iclass 3, count 0 2006.285.11:20:17.01#ibcon#about to read 6, iclass 3, count 0 2006.285.11:20:17.01#ibcon#read 6, iclass 3, count 0 2006.285.11:20:17.01#ibcon#end of sib2, iclass 3, count 0 2006.285.11:20:17.01#ibcon#*after write, iclass 3, count 0 2006.285.11:20:17.01#ibcon#*before return 0, iclass 3, count 0 2006.285.11:20:17.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:20:17.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:20:17.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:20:17.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:20:17.01$vck44/vblo=8,744.99 2006.285.11:20:17.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.11:20:17.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.11:20:17.01#ibcon#ireg 17 cls_cnt 0 2006.285.11:20:17.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:20:17.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:20:17.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:20:17.01#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:20:17.01#ibcon#first serial, iclass 5, count 0 2006.285.11:20:17.01#ibcon#enter sib2, iclass 5, count 0 2006.285.11:20:17.01#ibcon#flushed, iclass 5, count 0 2006.285.11:20:17.01#ibcon#about to write, iclass 5, count 0 2006.285.11:20:17.01#ibcon#wrote, iclass 5, count 0 2006.285.11:20:17.01#ibcon#about to read 3, iclass 5, count 0 2006.285.11:20:17.03#ibcon#read 3, iclass 5, count 0 2006.285.11:20:17.03#ibcon#about to read 4, iclass 5, count 0 2006.285.11:20:17.03#ibcon#read 4, iclass 5, count 0 2006.285.11:20:17.03#ibcon#about to read 5, iclass 5, count 0 2006.285.11:20:17.03#ibcon#read 5, iclass 5, count 0 2006.285.11:20:17.03#ibcon#about to read 6, iclass 5, count 0 2006.285.11:20:17.03#ibcon#read 6, iclass 5, count 0 2006.285.11:20:17.03#ibcon#end of sib2, iclass 5, count 0 2006.285.11:20:17.03#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:20:17.03#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:20:17.03#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:20:17.03#ibcon#*before write, iclass 5, count 0 2006.285.11:20:17.03#ibcon#enter sib2, iclass 5, count 0 2006.285.11:20:17.03#ibcon#flushed, iclass 5, count 0 2006.285.11:20:17.03#ibcon#about to write, iclass 5, count 0 2006.285.11:20:17.03#ibcon#wrote, iclass 5, count 0 2006.285.11:20:17.03#ibcon#about to read 3, iclass 5, count 0 2006.285.11:20:17.07#ibcon#read 3, iclass 5, count 0 2006.285.11:20:17.07#ibcon#about to read 4, iclass 5, count 0 2006.285.11:20:17.07#ibcon#read 4, iclass 5, count 0 2006.285.11:20:17.07#ibcon#about to read 5, iclass 5, count 0 2006.285.11:20:17.07#ibcon#read 5, iclass 5, count 0 2006.285.11:20:17.07#ibcon#about to read 6, iclass 5, count 0 2006.285.11:20:17.07#ibcon#read 6, iclass 5, count 0 2006.285.11:20:17.07#ibcon#end of sib2, iclass 5, count 0 2006.285.11:20:17.07#ibcon#*after write, iclass 5, count 0 2006.285.11:20:17.07#ibcon#*before return 0, iclass 5, count 0 2006.285.11:20:17.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:20:17.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:20:17.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:20:17.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:20:17.07$vck44/vb=8,4 2006.285.11:20:17.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.11:20:17.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.11:20:17.07#ibcon#ireg 11 cls_cnt 2 2006.285.11:20:17.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:20:17.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:20:17.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:20:17.13#ibcon#enter wrdev, iclass 7, count 2 2006.285.11:20:17.13#ibcon#first serial, iclass 7, count 2 2006.285.11:20:17.13#ibcon#enter sib2, iclass 7, count 2 2006.285.11:20:17.13#ibcon#flushed, iclass 7, count 2 2006.285.11:20:17.13#ibcon#about to write, iclass 7, count 2 2006.285.11:20:17.13#ibcon#wrote, iclass 7, count 2 2006.285.11:20:17.13#ibcon#about to read 3, iclass 7, count 2 2006.285.11:20:17.15#ibcon#read 3, iclass 7, count 2 2006.285.11:20:17.15#ibcon#about to read 4, iclass 7, count 2 2006.285.11:20:17.15#ibcon#read 4, iclass 7, count 2 2006.285.11:20:17.15#ibcon#about to read 5, iclass 7, count 2 2006.285.11:20:17.15#ibcon#read 5, iclass 7, count 2 2006.285.11:20:17.15#ibcon#about to read 6, iclass 7, count 2 2006.285.11:20:17.15#ibcon#read 6, iclass 7, count 2 2006.285.11:20:17.15#ibcon#end of sib2, iclass 7, count 2 2006.285.11:20:17.15#ibcon#*mode == 0, iclass 7, count 2 2006.285.11:20:17.15#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.11:20:17.15#ibcon#[27=AT08-04\r\n] 2006.285.11:20:17.15#ibcon#*before write, iclass 7, count 2 2006.285.11:20:17.15#ibcon#enter sib2, iclass 7, count 2 2006.285.11:20:17.15#ibcon#flushed, iclass 7, count 2 2006.285.11:20:17.15#ibcon#about to write, iclass 7, count 2 2006.285.11:20:17.15#ibcon#wrote, iclass 7, count 2 2006.285.11:20:17.15#ibcon#about to read 3, iclass 7, count 2 2006.285.11:20:17.18#ibcon#read 3, iclass 7, count 2 2006.285.11:20:17.18#ibcon#about to read 4, iclass 7, count 2 2006.285.11:20:17.18#ibcon#read 4, iclass 7, count 2 2006.285.11:20:17.18#ibcon#about to read 5, iclass 7, count 2 2006.285.11:20:17.18#ibcon#read 5, iclass 7, count 2 2006.285.11:20:17.18#ibcon#about to read 6, iclass 7, count 2 2006.285.11:20:17.18#ibcon#read 6, iclass 7, count 2 2006.285.11:20:17.18#ibcon#end of sib2, iclass 7, count 2 2006.285.11:20:17.18#ibcon#*after write, iclass 7, count 2 2006.285.11:20:17.18#ibcon#*before return 0, iclass 7, count 2 2006.285.11:20:17.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:20:17.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:20:17.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.11:20:17.18#ibcon#ireg 7 cls_cnt 0 2006.285.11:20:17.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:20:17.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:20:17.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:20:17.30#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:20:17.30#ibcon#first serial, iclass 7, count 0 2006.285.11:20:17.30#ibcon#enter sib2, iclass 7, count 0 2006.285.11:20:17.30#ibcon#flushed, iclass 7, count 0 2006.285.11:20:17.30#ibcon#about to write, iclass 7, count 0 2006.285.11:20:17.30#ibcon#wrote, iclass 7, count 0 2006.285.11:20:17.30#ibcon#about to read 3, iclass 7, count 0 2006.285.11:20:17.32#ibcon#read 3, iclass 7, count 0 2006.285.11:20:17.32#ibcon#about to read 4, iclass 7, count 0 2006.285.11:20:17.32#ibcon#read 4, iclass 7, count 0 2006.285.11:20:17.32#ibcon#about to read 5, iclass 7, count 0 2006.285.11:20:17.32#ibcon#read 5, iclass 7, count 0 2006.285.11:20:17.32#ibcon#about to read 6, iclass 7, count 0 2006.285.11:20:17.32#ibcon#read 6, iclass 7, count 0 2006.285.11:20:17.32#ibcon#end of sib2, iclass 7, count 0 2006.285.11:20:17.32#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:20:17.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:20:17.32#ibcon#[27=USB\r\n] 2006.285.11:20:17.32#ibcon#*before write, iclass 7, count 0 2006.285.11:20:17.32#ibcon#enter sib2, iclass 7, count 0 2006.285.11:20:17.32#ibcon#flushed, iclass 7, count 0 2006.285.11:20:17.32#ibcon#about to write, iclass 7, count 0 2006.285.11:20:17.32#ibcon#wrote, iclass 7, count 0 2006.285.11:20:17.32#ibcon#about to read 3, iclass 7, count 0 2006.285.11:20:17.35#ibcon#read 3, iclass 7, count 0 2006.285.11:20:17.35#ibcon#about to read 4, iclass 7, count 0 2006.285.11:20:17.35#ibcon#read 4, iclass 7, count 0 2006.285.11:20:17.35#ibcon#about to read 5, iclass 7, count 0 2006.285.11:20:17.35#ibcon#read 5, iclass 7, count 0 2006.285.11:20:17.35#ibcon#about to read 6, iclass 7, count 0 2006.285.11:20:17.35#ibcon#read 6, iclass 7, count 0 2006.285.11:20:17.35#ibcon#end of sib2, iclass 7, count 0 2006.285.11:20:17.35#ibcon#*after write, iclass 7, count 0 2006.285.11:20:17.35#ibcon#*before return 0, iclass 7, count 0 2006.285.11:20:17.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:20:17.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:20:17.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:20:17.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:20:17.35$vck44/vabw=wide 2006.285.11:20:17.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.11:20:17.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.11:20:17.35#ibcon#ireg 8 cls_cnt 0 2006.285.11:20:17.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:20:17.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:20:17.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:20:17.35#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:20:17.35#ibcon#first serial, iclass 11, count 0 2006.285.11:20:17.35#ibcon#enter sib2, iclass 11, count 0 2006.285.11:20:17.35#ibcon#flushed, iclass 11, count 0 2006.285.11:20:17.35#ibcon#about to write, iclass 11, count 0 2006.285.11:20:17.35#ibcon#wrote, iclass 11, count 0 2006.285.11:20:17.35#ibcon#about to read 3, iclass 11, count 0 2006.285.11:20:17.37#ibcon#read 3, iclass 11, count 0 2006.285.11:20:17.37#ibcon#about to read 4, iclass 11, count 0 2006.285.11:20:17.37#ibcon#read 4, iclass 11, count 0 2006.285.11:20:17.37#ibcon#about to read 5, iclass 11, count 0 2006.285.11:20:17.37#ibcon#read 5, iclass 11, count 0 2006.285.11:20:17.37#ibcon#about to read 6, iclass 11, count 0 2006.285.11:20:17.37#ibcon#read 6, iclass 11, count 0 2006.285.11:20:17.37#ibcon#end of sib2, iclass 11, count 0 2006.285.11:20:17.37#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:20:17.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:20:17.37#ibcon#[25=BW32\r\n] 2006.285.11:20:17.37#ibcon#*before write, iclass 11, count 0 2006.285.11:20:17.37#ibcon#enter sib2, iclass 11, count 0 2006.285.11:20:17.37#ibcon#flushed, iclass 11, count 0 2006.285.11:20:17.37#ibcon#about to write, iclass 11, count 0 2006.285.11:20:17.37#ibcon#wrote, iclass 11, count 0 2006.285.11:20:17.37#ibcon#about to read 3, iclass 11, count 0 2006.285.11:20:17.40#ibcon#read 3, iclass 11, count 0 2006.285.11:20:17.40#ibcon#about to read 4, iclass 11, count 0 2006.285.11:20:17.40#ibcon#read 4, iclass 11, count 0 2006.285.11:20:17.40#ibcon#about to read 5, iclass 11, count 0 2006.285.11:20:17.40#ibcon#read 5, iclass 11, count 0 2006.285.11:20:17.40#ibcon#about to read 6, iclass 11, count 0 2006.285.11:20:17.40#ibcon#read 6, iclass 11, count 0 2006.285.11:20:17.40#ibcon#end of sib2, iclass 11, count 0 2006.285.11:20:17.40#ibcon#*after write, iclass 11, count 0 2006.285.11:20:17.40#ibcon#*before return 0, iclass 11, count 0 2006.285.11:20:17.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:20:17.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:20:17.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:20:17.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:20:17.40$vck44/vbbw=wide 2006.285.11:20:17.40#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.11:20:17.40#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.11:20:17.40#ibcon#ireg 8 cls_cnt 0 2006.285.11:20:17.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:20:17.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:20:17.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:20:17.47#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:20:17.47#ibcon#first serial, iclass 13, count 0 2006.285.11:20:17.47#ibcon#enter sib2, iclass 13, count 0 2006.285.11:20:17.47#ibcon#flushed, iclass 13, count 0 2006.285.11:20:17.47#ibcon#about to write, iclass 13, count 0 2006.285.11:20:17.47#ibcon#wrote, iclass 13, count 0 2006.285.11:20:17.47#ibcon#about to read 3, iclass 13, count 0 2006.285.11:20:17.49#ibcon#read 3, iclass 13, count 0 2006.285.11:20:17.49#ibcon#about to read 4, iclass 13, count 0 2006.285.11:20:17.49#ibcon#read 4, iclass 13, count 0 2006.285.11:20:17.49#ibcon#about to read 5, iclass 13, count 0 2006.285.11:20:17.49#ibcon#read 5, iclass 13, count 0 2006.285.11:20:17.49#ibcon#about to read 6, iclass 13, count 0 2006.285.11:20:17.49#ibcon#read 6, iclass 13, count 0 2006.285.11:20:17.49#ibcon#end of sib2, iclass 13, count 0 2006.285.11:20:17.49#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:20:17.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:20:17.49#ibcon#[27=BW32\r\n] 2006.285.11:20:17.49#ibcon#*before write, iclass 13, count 0 2006.285.11:20:17.49#ibcon#enter sib2, iclass 13, count 0 2006.285.11:20:17.49#ibcon#flushed, iclass 13, count 0 2006.285.11:20:17.49#ibcon#about to write, iclass 13, count 0 2006.285.11:20:17.49#ibcon#wrote, iclass 13, count 0 2006.285.11:20:17.49#ibcon#about to read 3, iclass 13, count 0 2006.285.11:20:17.52#ibcon#read 3, iclass 13, count 0 2006.285.11:20:17.52#ibcon#about to read 4, iclass 13, count 0 2006.285.11:20:17.52#ibcon#read 4, iclass 13, count 0 2006.285.11:20:17.52#ibcon#about to read 5, iclass 13, count 0 2006.285.11:20:17.52#ibcon#read 5, iclass 13, count 0 2006.285.11:20:17.52#ibcon#about to read 6, iclass 13, count 0 2006.285.11:20:17.52#ibcon#read 6, iclass 13, count 0 2006.285.11:20:17.52#ibcon#end of sib2, iclass 13, count 0 2006.285.11:20:17.52#ibcon#*after write, iclass 13, count 0 2006.285.11:20:17.52#ibcon#*before return 0, iclass 13, count 0 2006.285.11:20:17.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:20:17.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:20:17.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:20:17.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:20:17.52$setupk4/ifdk4 2006.285.11:20:17.52$ifdk4/lo= 2006.285.11:20:17.52$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:20:17.52$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:20:17.52$ifdk4/patch= 2006.285.11:20:17.52$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:20:17.52$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:20:17.52$setupk4/!*+20s 2006.285.11:20:20.05#abcon#<5=/04 0.9 1.4 19.35 931015.2\r\n> 2006.285.11:20:20.07#abcon#{5=INTERFACE CLEAR} 2006.285.11:20:20.13#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:20:30.22#abcon#<5=/04 0.9 1.4 19.35 931015.2\r\n> 2006.285.11:20:30.24#abcon#{5=INTERFACE CLEAR} 2006.285.11:20:30.30#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:20:32.03$setupk4/"tpicd 2006.285.11:20:32.03$setupk4/echo=off 2006.285.11:20:32.03$setupk4/xlog=off 2006.285.11:20:32.03:!2006.285.11:25:08 2006.285.11:21:12.13#trakl#Source acquired 2006.285.11:21:12.13#flagr#flagr/antenna,acquired 2006.285.11:25:08.00:preob 2006.285.11:25:08.14/onsource/TRACKING 2006.285.11:25:08.14:!2006.285.11:25:18 2006.285.11:25:18.00:"tape 2006.285.11:25:18.00:"st=record 2006.285.11:25:18.00:data_valid=on 2006.285.11:25:18.00:midob 2006.285.11:25:18.14/onsource/TRACKING 2006.285.11:25:18.14/wx/19.31,1015.3,93 2006.285.11:25:18.35/cable/+6.4906E-03 2006.285.11:25:19.44/va/01,07,usb,yes,34,37 2006.285.11:25:19.44/va/02,06,usb,yes,34,35 2006.285.11:25:19.44/va/03,07,usb,yes,34,35 2006.285.11:25:19.44/va/04,06,usb,yes,35,37 2006.285.11:25:19.44/va/05,03,usb,yes,35,35 2006.285.11:25:19.44/va/06,04,usb,yes,31,31 2006.285.11:25:19.44/va/07,04,usb,yes,32,32 2006.285.11:25:19.44/va/08,03,usb,yes,33,39 2006.285.11:25:19.67/valo/01,524.99,yes,locked 2006.285.11:25:19.67/valo/02,534.99,yes,locked 2006.285.11:25:19.67/valo/03,564.99,yes,locked 2006.285.11:25:19.67/valo/04,624.99,yes,locked 2006.285.11:25:19.67/valo/05,734.99,yes,locked 2006.285.11:25:19.67/valo/06,814.99,yes,locked 2006.285.11:25:19.67/valo/07,864.99,yes,locked 2006.285.11:25:19.67/valo/08,884.99,yes,locked 2006.285.11:25:20.76/vb/01,04,usb,yes,33,35 2006.285.11:25:20.76/vb/02,05,usb,yes,29,37 2006.285.11:25:20.76/vb/03,04,usb,yes,30,33 2006.285.11:25:20.76/vb/04,05,usb,yes,31,30 2006.285.11:25:20.76/vb/05,04,usb,yes,28,31 2006.285.11:25:20.76/vb/06,03,usb,yes,41,37 2006.285.11:25:20.76/vb/07,04,usb,yes,32,32 2006.285.11:25:20.76/vb/08,04,usb,yes,29,33 2006.285.11:25:21.00/vblo/01,629.99,yes,locked 2006.285.11:25:21.00/vblo/02,634.99,yes,locked 2006.285.11:25:21.00/vblo/03,649.99,yes,locked 2006.285.11:25:21.00/vblo/04,679.99,yes,locked 2006.285.11:25:21.00/vblo/05,709.99,yes,locked 2006.285.11:25:21.00/vblo/06,719.99,yes,locked 2006.285.11:25:21.00/vblo/07,734.99,yes,locked 2006.285.11:25:21.00/vblo/08,744.99,yes,locked 2006.285.11:25:21.15/vabw/8 2006.285.11:25:21.30/vbbw/8 2006.285.11:25:21.39/xfe/off,on,12.2 2006.285.11:25:21.76/ifatt/23,28,28,28 2006.285.11:25:22.08/fmout-gps/S +2.73E-07 2006.285.11:25:22.10:!2006.285.11:29:18 2006.285.11:29:18.00:data_valid=off 2006.285.11:29:18.00:"et 2006.285.11:29:18.00:!+3s 2006.285.11:29:21.01:"tape 2006.285.11:29:21.01:postob 2006.285.11:29:21.16/cable/+6.4909E-03 2006.285.11:29:21.16/wx/19.29,1015.3,94 2006.285.11:29:22.07/fmout-gps/S +2.71E-07 2006.285.11:29:22.07:scan_name=285-1130,jd0610,240 2006.285.11:29:22.07:source=1803+784,180045.68,782804.0,2000.0,ccw 2006.285.11:29:22.13#flagr#flagr/antenna,new-source 2006.285.11:29:23.13:checkk5 2006.285.11:29:23.76/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:29:24.21/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:29:24.66/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:29:25.05/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:29:25.38/chk_obsdata//k5ts1/T2851125??a.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.11:29:25.81/chk_obsdata//k5ts2/T2851125??b.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.11:29:26.28/chk_obsdata//k5ts3/T2851125??c.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.11:29:26.61/chk_obsdata//k5ts4/T2851125??d.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.11:29:27.34/k5log//k5ts1_log_newline 2006.285.11:29:28.07/k5log//k5ts2_log_newline 2006.285.11:29:28.81/k5log//k5ts3_log_newline 2006.285.11:29:29.74/k5log//k5ts4_log_newline 2006.285.11:29:29.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:29:29.77:setupk4=1 2006.285.11:29:29.77$setupk4/echo=on 2006.285.11:29:29.77$setupk4/pcalon 2006.285.11:29:29.77$pcalon/"no phase cal control is implemented here 2006.285.11:29:29.77$setupk4/"tpicd=stop 2006.285.11:29:29.77$setupk4/"rec=synch_on 2006.285.11:29:29.77$setupk4/"rec_mode=128 2006.285.11:29:29.77$setupk4/!* 2006.285.11:29:29.77$setupk4/recpk4 2006.285.11:29:29.77$recpk4/recpatch= 2006.285.11:29:29.77$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:29:29.77$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:29:29.77$setupk4/vck44 2006.285.11:29:29.77$vck44/valo=1,524.99 2006.285.11:29:29.77#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.11:29:29.77#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.11:29:29.77#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:29.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:29:29.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:29:29.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:29:29.77#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:29:29.77#ibcon#first serial, iclass 22, count 0 2006.285.11:29:29.77#ibcon#enter sib2, iclass 22, count 0 2006.285.11:29:29.77#ibcon#flushed, iclass 22, count 0 2006.285.11:29:29.77#ibcon#about to write, iclass 22, count 0 2006.285.11:29:29.77#ibcon#wrote, iclass 22, count 0 2006.285.11:29:29.77#ibcon#about to read 3, iclass 22, count 0 2006.285.11:29:29.79#ibcon#read 3, iclass 22, count 0 2006.285.11:29:29.79#ibcon#about to read 4, iclass 22, count 0 2006.285.11:29:29.79#ibcon#read 4, iclass 22, count 0 2006.285.11:29:29.79#ibcon#about to read 5, iclass 22, count 0 2006.285.11:29:29.79#ibcon#read 5, iclass 22, count 0 2006.285.11:29:29.79#ibcon#about to read 6, iclass 22, count 0 2006.285.11:29:29.79#ibcon#read 6, iclass 22, count 0 2006.285.11:29:29.79#ibcon#end of sib2, iclass 22, count 0 2006.285.11:29:29.79#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:29:29.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:29:29.79#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:29:29.79#ibcon#*before write, iclass 22, count 0 2006.285.11:29:29.79#ibcon#enter sib2, iclass 22, count 0 2006.285.11:29:29.79#ibcon#flushed, iclass 22, count 0 2006.285.11:29:29.79#ibcon#about to write, iclass 22, count 0 2006.285.11:29:29.79#ibcon#wrote, iclass 22, count 0 2006.285.11:29:29.79#ibcon#about to read 3, iclass 22, count 0 2006.285.11:29:29.84#ibcon#read 3, iclass 22, count 0 2006.285.11:29:29.84#ibcon#about to read 4, iclass 22, count 0 2006.285.11:29:29.84#ibcon#read 4, iclass 22, count 0 2006.285.11:29:29.84#ibcon#about to read 5, iclass 22, count 0 2006.285.11:29:29.84#ibcon#read 5, iclass 22, count 0 2006.285.11:29:29.84#ibcon#about to read 6, iclass 22, count 0 2006.285.11:29:29.84#ibcon#read 6, iclass 22, count 0 2006.285.11:29:29.84#ibcon#end of sib2, iclass 22, count 0 2006.285.11:29:29.84#ibcon#*after write, iclass 22, count 0 2006.285.11:29:29.84#ibcon#*before return 0, iclass 22, count 0 2006.285.11:29:29.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:29:29.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:29:29.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:29:29.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:29:29.84$vck44/va=1,7 2006.285.11:29:29.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.11:29:29.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.11:29:29.84#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:29.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:29:29.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:29:29.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:29:29.84#ibcon#enter wrdev, iclass 24, count 2 2006.285.11:29:29.84#ibcon#first serial, iclass 24, count 2 2006.285.11:29:29.84#ibcon#enter sib2, iclass 24, count 2 2006.285.11:29:29.84#ibcon#flushed, iclass 24, count 2 2006.285.11:29:29.84#ibcon#about to write, iclass 24, count 2 2006.285.11:29:29.84#ibcon#wrote, iclass 24, count 2 2006.285.11:29:29.84#ibcon#about to read 3, iclass 24, count 2 2006.285.11:29:29.86#ibcon#read 3, iclass 24, count 2 2006.285.11:29:29.86#ibcon#about to read 4, iclass 24, count 2 2006.285.11:29:29.86#ibcon#read 4, iclass 24, count 2 2006.285.11:29:29.86#ibcon#about to read 5, iclass 24, count 2 2006.285.11:29:29.86#ibcon#read 5, iclass 24, count 2 2006.285.11:29:29.86#ibcon#about to read 6, iclass 24, count 2 2006.285.11:29:29.86#ibcon#read 6, iclass 24, count 2 2006.285.11:29:29.86#ibcon#end of sib2, iclass 24, count 2 2006.285.11:29:29.86#ibcon#*mode == 0, iclass 24, count 2 2006.285.11:29:29.86#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.11:29:29.86#ibcon#[25=AT01-07\r\n] 2006.285.11:29:29.86#ibcon#*before write, iclass 24, count 2 2006.285.11:29:29.86#ibcon#enter sib2, iclass 24, count 2 2006.285.11:29:29.86#ibcon#flushed, iclass 24, count 2 2006.285.11:29:29.86#ibcon#about to write, iclass 24, count 2 2006.285.11:29:29.86#ibcon#wrote, iclass 24, count 2 2006.285.11:29:29.86#ibcon#about to read 3, iclass 24, count 2 2006.285.11:29:29.89#ibcon#read 3, iclass 24, count 2 2006.285.11:29:29.89#ibcon#about to read 4, iclass 24, count 2 2006.285.11:29:29.89#ibcon#read 4, iclass 24, count 2 2006.285.11:29:29.89#ibcon#about to read 5, iclass 24, count 2 2006.285.11:29:29.89#ibcon#read 5, iclass 24, count 2 2006.285.11:29:29.89#ibcon#about to read 6, iclass 24, count 2 2006.285.11:29:29.89#ibcon#read 6, iclass 24, count 2 2006.285.11:29:29.89#ibcon#end of sib2, iclass 24, count 2 2006.285.11:29:29.89#ibcon#*after write, iclass 24, count 2 2006.285.11:29:29.89#ibcon#*before return 0, iclass 24, count 2 2006.285.11:29:29.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:29:29.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:29:29.89#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.11:29:29.89#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:29.89#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:29:30.01#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:29:30.01#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:29:30.01#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:29:30.01#ibcon#first serial, iclass 24, count 0 2006.285.11:29:30.01#ibcon#enter sib2, iclass 24, count 0 2006.285.11:29:30.01#ibcon#flushed, iclass 24, count 0 2006.285.11:29:30.01#ibcon#about to write, iclass 24, count 0 2006.285.11:29:30.01#ibcon#wrote, iclass 24, count 0 2006.285.11:29:30.01#ibcon#about to read 3, iclass 24, count 0 2006.285.11:29:30.03#ibcon#read 3, iclass 24, count 0 2006.285.11:29:30.03#ibcon#about to read 4, iclass 24, count 0 2006.285.11:29:30.03#ibcon#read 4, iclass 24, count 0 2006.285.11:29:30.03#ibcon#about to read 5, iclass 24, count 0 2006.285.11:29:30.03#ibcon#read 5, iclass 24, count 0 2006.285.11:29:30.03#ibcon#about to read 6, iclass 24, count 0 2006.285.11:29:30.03#ibcon#read 6, iclass 24, count 0 2006.285.11:29:30.03#ibcon#end of sib2, iclass 24, count 0 2006.285.11:29:30.03#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:29:30.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:29:30.03#ibcon#[25=USB\r\n] 2006.285.11:29:30.03#ibcon#*before write, iclass 24, count 0 2006.285.11:29:30.03#ibcon#enter sib2, iclass 24, count 0 2006.285.11:29:30.03#ibcon#flushed, iclass 24, count 0 2006.285.11:29:30.03#ibcon#about to write, iclass 24, count 0 2006.285.11:29:30.03#ibcon#wrote, iclass 24, count 0 2006.285.11:29:30.03#ibcon#about to read 3, iclass 24, count 0 2006.285.11:29:30.06#ibcon#read 3, iclass 24, count 0 2006.285.11:29:30.06#ibcon#about to read 4, iclass 24, count 0 2006.285.11:29:30.06#ibcon#read 4, iclass 24, count 0 2006.285.11:29:30.06#ibcon#about to read 5, iclass 24, count 0 2006.285.11:29:30.06#ibcon#read 5, iclass 24, count 0 2006.285.11:29:30.06#ibcon#about to read 6, iclass 24, count 0 2006.285.11:29:30.06#ibcon#read 6, iclass 24, count 0 2006.285.11:29:30.06#ibcon#end of sib2, iclass 24, count 0 2006.285.11:29:30.06#ibcon#*after write, iclass 24, count 0 2006.285.11:29:30.06#ibcon#*before return 0, iclass 24, count 0 2006.285.11:29:30.06#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:29:30.06#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:29:30.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:29:30.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:29:30.06$vck44/valo=2,534.99 2006.285.11:29:30.06#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.11:29:30.06#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.11:29:30.06#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:30.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:29:30.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:29:30.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:29:30.06#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:29:30.06#ibcon#first serial, iclass 26, count 0 2006.285.11:29:30.06#ibcon#enter sib2, iclass 26, count 0 2006.285.11:29:30.06#ibcon#flushed, iclass 26, count 0 2006.285.11:29:30.06#ibcon#about to write, iclass 26, count 0 2006.285.11:29:30.06#ibcon#wrote, iclass 26, count 0 2006.285.11:29:30.06#ibcon#about to read 3, iclass 26, count 0 2006.285.11:29:30.08#ibcon#read 3, iclass 26, count 0 2006.285.11:29:30.08#ibcon#about to read 4, iclass 26, count 0 2006.285.11:29:30.08#ibcon#read 4, iclass 26, count 0 2006.285.11:29:30.08#ibcon#about to read 5, iclass 26, count 0 2006.285.11:29:30.08#ibcon#read 5, iclass 26, count 0 2006.285.11:29:30.08#ibcon#about to read 6, iclass 26, count 0 2006.285.11:29:30.08#ibcon#read 6, iclass 26, count 0 2006.285.11:29:30.08#ibcon#end of sib2, iclass 26, count 0 2006.285.11:29:30.08#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:29:30.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:29:30.08#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:29:30.08#ibcon#*before write, iclass 26, count 0 2006.285.11:29:30.08#ibcon#enter sib2, iclass 26, count 0 2006.285.11:29:30.08#ibcon#flushed, iclass 26, count 0 2006.285.11:29:30.08#ibcon#about to write, iclass 26, count 0 2006.285.11:29:30.08#ibcon#wrote, iclass 26, count 0 2006.285.11:29:30.08#ibcon#about to read 3, iclass 26, count 0 2006.285.11:29:30.12#ibcon#read 3, iclass 26, count 0 2006.285.11:29:30.12#ibcon#about to read 4, iclass 26, count 0 2006.285.11:29:30.12#ibcon#read 4, iclass 26, count 0 2006.285.11:29:30.12#ibcon#about to read 5, iclass 26, count 0 2006.285.11:29:30.12#ibcon#read 5, iclass 26, count 0 2006.285.11:29:30.12#ibcon#about to read 6, iclass 26, count 0 2006.285.11:29:30.12#ibcon#read 6, iclass 26, count 0 2006.285.11:29:30.12#ibcon#end of sib2, iclass 26, count 0 2006.285.11:29:30.12#ibcon#*after write, iclass 26, count 0 2006.285.11:29:30.12#ibcon#*before return 0, iclass 26, count 0 2006.285.11:29:30.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:29:30.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:29:30.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:29:30.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:29:30.12$vck44/va=2,6 2006.285.11:29:30.12#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.11:29:30.12#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.11:29:30.12#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:30.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:29:30.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:29:30.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:29:30.18#ibcon#enter wrdev, iclass 28, count 2 2006.285.11:29:30.18#ibcon#first serial, iclass 28, count 2 2006.285.11:29:30.18#ibcon#enter sib2, iclass 28, count 2 2006.285.11:29:30.18#ibcon#flushed, iclass 28, count 2 2006.285.11:29:30.18#ibcon#about to write, iclass 28, count 2 2006.285.11:29:30.18#ibcon#wrote, iclass 28, count 2 2006.285.11:29:30.18#ibcon#about to read 3, iclass 28, count 2 2006.285.11:29:30.20#ibcon#read 3, iclass 28, count 2 2006.285.11:29:30.20#ibcon#about to read 4, iclass 28, count 2 2006.285.11:29:30.20#ibcon#read 4, iclass 28, count 2 2006.285.11:29:30.20#ibcon#about to read 5, iclass 28, count 2 2006.285.11:29:30.20#ibcon#read 5, iclass 28, count 2 2006.285.11:29:30.20#ibcon#about to read 6, iclass 28, count 2 2006.285.11:29:30.20#ibcon#read 6, iclass 28, count 2 2006.285.11:29:30.20#ibcon#end of sib2, iclass 28, count 2 2006.285.11:29:30.20#ibcon#*mode == 0, iclass 28, count 2 2006.285.11:29:30.20#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.11:29:30.20#ibcon#[25=AT02-06\r\n] 2006.285.11:29:30.20#ibcon#*before write, iclass 28, count 2 2006.285.11:29:30.20#ibcon#enter sib2, iclass 28, count 2 2006.285.11:29:30.20#ibcon#flushed, iclass 28, count 2 2006.285.11:29:30.20#ibcon#about to write, iclass 28, count 2 2006.285.11:29:30.20#ibcon#wrote, iclass 28, count 2 2006.285.11:29:30.20#ibcon#about to read 3, iclass 28, count 2 2006.285.11:29:30.23#ibcon#read 3, iclass 28, count 2 2006.285.11:29:30.23#ibcon#about to read 4, iclass 28, count 2 2006.285.11:29:30.23#ibcon#read 4, iclass 28, count 2 2006.285.11:29:30.23#ibcon#about to read 5, iclass 28, count 2 2006.285.11:29:30.23#ibcon#read 5, iclass 28, count 2 2006.285.11:29:30.23#ibcon#about to read 6, iclass 28, count 2 2006.285.11:29:30.23#ibcon#read 6, iclass 28, count 2 2006.285.11:29:30.23#ibcon#end of sib2, iclass 28, count 2 2006.285.11:29:30.23#ibcon#*after write, iclass 28, count 2 2006.285.11:29:30.23#ibcon#*before return 0, iclass 28, count 2 2006.285.11:29:30.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:29:30.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:29:30.23#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.11:29:30.23#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:30.23#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:29:30.35#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:29:30.35#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:29:30.35#ibcon#enter wrdev, iclass 28, count 0 2006.285.11:29:30.35#ibcon#first serial, iclass 28, count 0 2006.285.11:29:30.35#ibcon#enter sib2, iclass 28, count 0 2006.285.11:29:30.35#ibcon#flushed, iclass 28, count 0 2006.285.11:29:30.35#ibcon#about to write, iclass 28, count 0 2006.285.11:29:30.35#ibcon#wrote, iclass 28, count 0 2006.285.11:29:30.35#ibcon#about to read 3, iclass 28, count 0 2006.285.11:29:30.37#ibcon#read 3, iclass 28, count 0 2006.285.11:29:30.37#ibcon#about to read 4, iclass 28, count 0 2006.285.11:29:30.37#ibcon#read 4, iclass 28, count 0 2006.285.11:29:30.37#ibcon#about to read 5, iclass 28, count 0 2006.285.11:29:30.37#ibcon#read 5, iclass 28, count 0 2006.285.11:29:30.37#ibcon#about to read 6, iclass 28, count 0 2006.285.11:29:30.37#ibcon#read 6, iclass 28, count 0 2006.285.11:29:30.37#ibcon#end of sib2, iclass 28, count 0 2006.285.11:29:30.37#ibcon#*mode == 0, iclass 28, count 0 2006.285.11:29:30.37#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.11:29:30.37#ibcon#[25=USB\r\n] 2006.285.11:29:30.37#ibcon#*before write, iclass 28, count 0 2006.285.11:29:30.37#ibcon#enter sib2, iclass 28, count 0 2006.285.11:29:30.37#ibcon#flushed, iclass 28, count 0 2006.285.11:29:30.37#ibcon#about to write, iclass 28, count 0 2006.285.11:29:30.37#ibcon#wrote, iclass 28, count 0 2006.285.11:29:30.37#ibcon#about to read 3, iclass 28, count 0 2006.285.11:29:30.40#ibcon#read 3, iclass 28, count 0 2006.285.11:29:30.40#ibcon#about to read 4, iclass 28, count 0 2006.285.11:29:30.40#ibcon#read 4, iclass 28, count 0 2006.285.11:29:30.40#ibcon#about to read 5, iclass 28, count 0 2006.285.11:29:30.40#ibcon#read 5, iclass 28, count 0 2006.285.11:29:30.40#ibcon#about to read 6, iclass 28, count 0 2006.285.11:29:30.40#ibcon#read 6, iclass 28, count 0 2006.285.11:29:30.40#ibcon#end of sib2, iclass 28, count 0 2006.285.11:29:30.40#ibcon#*after write, iclass 28, count 0 2006.285.11:29:30.40#ibcon#*before return 0, iclass 28, count 0 2006.285.11:29:30.40#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:29:30.40#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:29:30.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.11:29:30.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.11:29:30.40$vck44/valo=3,564.99 2006.285.11:29:30.40#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.11:29:30.40#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.11:29:30.40#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:30.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:29:30.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:29:30.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:29:30.40#ibcon#enter wrdev, iclass 30, count 0 2006.285.11:29:30.40#ibcon#first serial, iclass 30, count 0 2006.285.11:29:30.40#ibcon#enter sib2, iclass 30, count 0 2006.285.11:29:30.40#ibcon#flushed, iclass 30, count 0 2006.285.11:29:30.40#ibcon#about to write, iclass 30, count 0 2006.285.11:29:30.40#ibcon#wrote, iclass 30, count 0 2006.285.11:29:30.40#ibcon#about to read 3, iclass 30, count 0 2006.285.11:29:30.42#ibcon#read 3, iclass 30, count 0 2006.285.11:29:30.42#ibcon#about to read 4, iclass 30, count 0 2006.285.11:29:30.42#ibcon#read 4, iclass 30, count 0 2006.285.11:29:30.42#ibcon#about to read 5, iclass 30, count 0 2006.285.11:29:30.42#ibcon#read 5, iclass 30, count 0 2006.285.11:29:30.42#ibcon#about to read 6, iclass 30, count 0 2006.285.11:29:30.42#ibcon#read 6, iclass 30, count 0 2006.285.11:29:30.42#ibcon#end of sib2, iclass 30, count 0 2006.285.11:29:30.42#ibcon#*mode == 0, iclass 30, count 0 2006.285.11:29:30.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.11:29:30.42#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:29:30.42#ibcon#*before write, iclass 30, count 0 2006.285.11:29:30.42#ibcon#enter sib2, iclass 30, count 0 2006.285.11:29:30.42#ibcon#flushed, iclass 30, count 0 2006.285.11:29:30.42#ibcon#about to write, iclass 30, count 0 2006.285.11:29:30.42#ibcon#wrote, iclass 30, count 0 2006.285.11:29:30.42#ibcon#about to read 3, iclass 30, count 0 2006.285.11:29:30.46#ibcon#read 3, iclass 30, count 0 2006.285.11:29:30.46#ibcon#about to read 4, iclass 30, count 0 2006.285.11:29:30.46#ibcon#read 4, iclass 30, count 0 2006.285.11:29:30.46#ibcon#about to read 5, iclass 30, count 0 2006.285.11:29:30.46#ibcon#read 5, iclass 30, count 0 2006.285.11:29:30.46#ibcon#about to read 6, iclass 30, count 0 2006.285.11:29:30.46#ibcon#read 6, iclass 30, count 0 2006.285.11:29:30.46#ibcon#end of sib2, iclass 30, count 0 2006.285.11:29:30.46#ibcon#*after write, iclass 30, count 0 2006.285.11:29:30.46#ibcon#*before return 0, iclass 30, count 0 2006.285.11:29:30.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:29:30.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:29:30.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.11:29:30.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.11:29:30.46$vck44/va=3,7 2006.285.11:29:30.46#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.11:29:30.46#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.11:29:30.46#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:30.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:29:30.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:29:30.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:29:30.52#ibcon#enter wrdev, iclass 32, count 2 2006.285.11:29:30.52#ibcon#first serial, iclass 32, count 2 2006.285.11:29:30.52#ibcon#enter sib2, iclass 32, count 2 2006.285.11:29:30.52#ibcon#flushed, iclass 32, count 2 2006.285.11:29:30.52#ibcon#about to write, iclass 32, count 2 2006.285.11:29:30.52#ibcon#wrote, iclass 32, count 2 2006.285.11:29:30.52#ibcon#about to read 3, iclass 32, count 2 2006.285.11:29:30.54#ibcon#read 3, iclass 32, count 2 2006.285.11:29:30.54#ibcon#about to read 4, iclass 32, count 2 2006.285.11:29:30.54#ibcon#read 4, iclass 32, count 2 2006.285.11:29:30.54#ibcon#about to read 5, iclass 32, count 2 2006.285.11:29:30.54#ibcon#read 5, iclass 32, count 2 2006.285.11:29:30.54#ibcon#about to read 6, iclass 32, count 2 2006.285.11:29:30.54#ibcon#read 6, iclass 32, count 2 2006.285.11:29:30.54#ibcon#end of sib2, iclass 32, count 2 2006.285.11:29:30.54#ibcon#*mode == 0, iclass 32, count 2 2006.285.11:29:30.54#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.11:29:30.54#ibcon#[25=AT03-07\r\n] 2006.285.11:29:30.54#ibcon#*before write, iclass 32, count 2 2006.285.11:29:30.54#ibcon#enter sib2, iclass 32, count 2 2006.285.11:29:30.54#ibcon#flushed, iclass 32, count 2 2006.285.11:29:30.54#ibcon#about to write, iclass 32, count 2 2006.285.11:29:30.54#ibcon#wrote, iclass 32, count 2 2006.285.11:29:30.54#ibcon#about to read 3, iclass 32, count 2 2006.285.11:29:30.57#ibcon#read 3, iclass 32, count 2 2006.285.11:29:30.57#ibcon#about to read 4, iclass 32, count 2 2006.285.11:29:30.57#ibcon#read 4, iclass 32, count 2 2006.285.11:29:30.57#ibcon#about to read 5, iclass 32, count 2 2006.285.11:29:30.57#ibcon#read 5, iclass 32, count 2 2006.285.11:29:30.57#ibcon#about to read 6, iclass 32, count 2 2006.285.11:29:30.57#ibcon#read 6, iclass 32, count 2 2006.285.11:29:30.57#ibcon#end of sib2, iclass 32, count 2 2006.285.11:29:30.57#ibcon#*after write, iclass 32, count 2 2006.285.11:29:30.57#ibcon#*before return 0, iclass 32, count 2 2006.285.11:29:30.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:29:30.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:29:30.57#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.11:29:30.57#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:30.57#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:29:30.69#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:29:30.69#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:29:30.69#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:29:30.69#ibcon#first serial, iclass 32, count 0 2006.285.11:29:30.69#ibcon#enter sib2, iclass 32, count 0 2006.285.11:29:30.69#ibcon#flushed, iclass 32, count 0 2006.285.11:29:30.69#ibcon#about to write, iclass 32, count 0 2006.285.11:29:30.69#ibcon#wrote, iclass 32, count 0 2006.285.11:29:30.69#ibcon#about to read 3, iclass 32, count 0 2006.285.11:29:30.71#ibcon#read 3, iclass 32, count 0 2006.285.11:29:30.71#ibcon#about to read 4, iclass 32, count 0 2006.285.11:29:30.71#ibcon#read 4, iclass 32, count 0 2006.285.11:29:30.71#ibcon#about to read 5, iclass 32, count 0 2006.285.11:29:30.71#ibcon#read 5, iclass 32, count 0 2006.285.11:29:30.71#ibcon#about to read 6, iclass 32, count 0 2006.285.11:29:30.71#ibcon#read 6, iclass 32, count 0 2006.285.11:29:30.71#ibcon#end of sib2, iclass 32, count 0 2006.285.11:29:30.71#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:29:30.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:29:30.71#ibcon#[25=USB\r\n] 2006.285.11:29:30.71#ibcon#*before write, iclass 32, count 0 2006.285.11:29:30.71#ibcon#enter sib2, iclass 32, count 0 2006.285.11:29:30.71#ibcon#flushed, iclass 32, count 0 2006.285.11:29:30.71#ibcon#about to write, iclass 32, count 0 2006.285.11:29:30.71#ibcon#wrote, iclass 32, count 0 2006.285.11:29:30.71#ibcon#about to read 3, iclass 32, count 0 2006.285.11:29:30.74#ibcon#read 3, iclass 32, count 0 2006.285.11:29:30.74#ibcon#about to read 4, iclass 32, count 0 2006.285.11:29:30.74#ibcon#read 4, iclass 32, count 0 2006.285.11:29:30.74#ibcon#about to read 5, iclass 32, count 0 2006.285.11:29:30.74#ibcon#read 5, iclass 32, count 0 2006.285.11:29:30.74#ibcon#about to read 6, iclass 32, count 0 2006.285.11:29:30.74#ibcon#read 6, iclass 32, count 0 2006.285.11:29:30.74#ibcon#end of sib2, iclass 32, count 0 2006.285.11:29:30.74#ibcon#*after write, iclass 32, count 0 2006.285.11:29:30.74#ibcon#*before return 0, iclass 32, count 0 2006.285.11:29:30.74#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:29:30.74#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:29:30.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:29:30.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:29:30.74$vck44/valo=4,624.99 2006.285.11:29:30.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.11:29:30.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.11:29:30.74#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:30.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:29:30.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:29:30.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:29:30.74#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:29:30.74#ibcon#first serial, iclass 34, count 0 2006.285.11:29:30.74#ibcon#enter sib2, iclass 34, count 0 2006.285.11:29:30.74#ibcon#flushed, iclass 34, count 0 2006.285.11:29:30.74#ibcon#about to write, iclass 34, count 0 2006.285.11:29:30.74#ibcon#wrote, iclass 34, count 0 2006.285.11:29:30.74#ibcon#about to read 3, iclass 34, count 0 2006.285.11:29:30.76#ibcon#read 3, iclass 34, count 0 2006.285.11:29:30.76#ibcon#about to read 4, iclass 34, count 0 2006.285.11:29:30.76#ibcon#read 4, iclass 34, count 0 2006.285.11:29:30.76#ibcon#about to read 5, iclass 34, count 0 2006.285.11:29:30.76#ibcon#read 5, iclass 34, count 0 2006.285.11:29:30.76#ibcon#about to read 6, iclass 34, count 0 2006.285.11:29:30.76#ibcon#read 6, iclass 34, count 0 2006.285.11:29:30.76#ibcon#end of sib2, iclass 34, count 0 2006.285.11:29:30.76#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:29:30.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:29:30.76#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:29:30.76#ibcon#*before write, iclass 34, count 0 2006.285.11:29:30.76#ibcon#enter sib2, iclass 34, count 0 2006.285.11:29:30.76#ibcon#flushed, iclass 34, count 0 2006.285.11:29:30.76#ibcon#about to write, iclass 34, count 0 2006.285.11:29:30.76#ibcon#wrote, iclass 34, count 0 2006.285.11:29:30.76#ibcon#about to read 3, iclass 34, count 0 2006.285.11:29:30.80#ibcon#read 3, iclass 34, count 0 2006.285.11:29:30.80#ibcon#about to read 4, iclass 34, count 0 2006.285.11:29:30.80#ibcon#read 4, iclass 34, count 0 2006.285.11:29:30.80#ibcon#about to read 5, iclass 34, count 0 2006.285.11:29:30.80#ibcon#read 5, iclass 34, count 0 2006.285.11:29:30.80#ibcon#about to read 6, iclass 34, count 0 2006.285.11:29:30.80#ibcon#read 6, iclass 34, count 0 2006.285.11:29:30.80#ibcon#end of sib2, iclass 34, count 0 2006.285.11:29:30.80#ibcon#*after write, iclass 34, count 0 2006.285.11:29:30.80#ibcon#*before return 0, iclass 34, count 0 2006.285.11:29:30.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:29:30.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:29:30.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:29:30.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:29:30.80$vck44/va=4,6 2006.285.11:29:30.80#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.11:29:30.80#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.11:29:30.80#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:30.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:29:30.86#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:29:30.86#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:29:30.86#ibcon#enter wrdev, iclass 36, count 2 2006.285.11:29:30.86#ibcon#first serial, iclass 36, count 2 2006.285.11:29:30.86#ibcon#enter sib2, iclass 36, count 2 2006.285.11:29:30.86#ibcon#flushed, iclass 36, count 2 2006.285.11:29:30.86#ibcon#about to write, iclass 36, count 2 2006.285.11:29:30.86#ibcon#wrote, iclass 36, count 2 2006.285.11:29:30.86#ibcon#about to read 3, iclass 36, count 2 2006.285.11:29:30.88#ibcon#read 3, iclass 36, count 2 2006.285.11:29:30.88#ibcon#about to read 4, iclass 36, count 2 2006.285.11:29:30.88#ibcon#read 4, iclass 36, count 2 2006.285.11:29:30.88#ibcon#about to read 5, iclass 36, count 2 2006.285.11:29:30.88#ibcon#read 5, iclass 36, count 2 2006.285.11:29:30.88#ibcon#about to read 6, iclass 36, count 2 2006.285.11:29:30.88#ibcon#read 6, iclass 36, count 2 2006.285.11:29:30.88#ibcon#end of sib2, iclass 36, count 2 2006.285.11:29:30.88#ibcon#*mode == 0, iclass 36, count 2 2006.285.11:29:30.88#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.11:29:30.88#ibcon#[25=AT04-06\r\n] 2006.285.11:29:30.88#ibcon#*before write, iclass 36, count 2 2006.285.11:29:30.88#ibcon#enter sib2, iclass 36, count 2 2006.285.11:29:30.88#ibcon#flushed, iclass 36, count 2 2006.285.11:29:30.88#ibcon#about to write, iclass 36, count 2 2006.285.11:29:30.88#ibcon#wrote, iclass 36, count 2 2006.285.11:29:30.88#ibcon#about to read 3, iclass 36, count 2 2006.285.11:29:30.91#ibcon#read 3, iclass 36, count 2 2006.285.11:29:30.91#ibcon#about to read 4, iclass 36, count 2 2006.285.11:29:30.91#ibcon#read 4, iclass 36, count 2 2006.285.11:29:30.91#ibcon#about to read 5, iclass 36, count 2 2006.285.11:29:30.91#ibcon#read 5, iclass 36, count 2 2006.285.11:29:30.91#ibcon#about to read 6, iclass 36, count 2 2006.285.11:29:30.91#ibcon#read 6, iclass 36, count 2 2006.285.11:29:30.91#ibcon#end of sib2, iclass 36, count 2 2006.285.11:29:30.91#ibcon#*after write, iclass 36, count 2 2006.285.11:29:30.91#ibcon#*before return 0, iclass 36, count 2 2006.285.11:29:30.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:29:30.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:29:30.91#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.11:29:30.91#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:30.91#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:29:31.03#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:29:31.03#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:29:31.03#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:29:31.03#ibcon#first serial, iclass 36, count 0 2006.285.11:29:31.03#ibcon#enter sib2, iclass 36, count 0 2006.285.11:29:31.03#ibcon#flushed, iclass 36, count 0 2006.285.11:29:31.03#ibcon#about to write, iclass 36, count 0 2006.285.11:29:31.03#ibcon#wrote, iclass 36, count 0 2006.285.11:29:31.03#ibcon#about to read 3, iclass 36, count 0 2006.285.11:29:31.05#ibcon#read 3, iclass 36, count 0 2006.285.11:29:31.05#ibcon#about to read 4, iclass 36, count 0 2006.285.11:29:31.05#ibcon#read 4, iclass 36, count 0 2006.285.11:29:31.05#ibcon#about to read 5, iclass 36, count 0 2006.285.11:29:31.05#ibcon#read 5, iclass 36, count 0 2006.285.11:29:31.05#ibcon#about to read 6, iclass 36, count 0 2006.285.11:29:31.05#ibcon#read 6, iclass 36, count 0 2006.285.11:29:31.05#ibcon#end of sib2, iclass 36, count 0 2006.285.11:29:31.05#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:29:31.05#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:29:31.05#ibcon#[25=USB\r\n] 2006.285.11:29:31.05#ibcon#*before write, iclass 36, count 0 2006.285.11:29:31.05#ibcon#enter sib2, iclass 36, count 0 2006.285.11:29:31.05#ibcon#flushed, iclass 36, count 0 2006.285.11:29:31.05#ibcon#about to write, iclass 36, count 0 2006.285.11:29:31.05#ibcon#wrote, iclass 36, count 0 2006.285.11:29:31.05#ibcon#about to read 3, iclass 36, count 0 2006.285.11:29:31.08#ibcon#read 3, iclass 36, count 0 2006.285.11:29:31.08#ibcon#about to read 4, iclass 36, count 0 2006.285.11:29:31.08#ibcon#read 4, iclass 36, count 0 2006.285.11:29:31.08#ibcon#about to read 5, iclass 36, count 0 2006.285.11:29:31.08#ibcon#read 5, iclass 36, count 0 2006.285.11:29:31.08#ibcon#about to read 6, iclass 36, count 0 2006.285.11:29:31.08#ibcon#read 6, iclass 36, count 0 2006.285.11:29:31.08#ibcon#end of sib2, iclass 36, count 0 2006.285.11:29:31.08#ibcon#*after write, iclass 36, count 0 2006.285.11:29:31.08#ibcon#*before return 0, iclass 36, count 0 2006.285.11:29:31.08#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:29:31.08#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:29:31.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:29:31.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:29:31.08$vck44/valo=5,734.99 2006.285.11:29:31.08#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.11:29:31.08#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.11:29:31.08#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:31.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:29:31.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:29:31.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:29:31.08#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:29:31.08#ibcon#first serial, iclass 38, count 0 2006.285.11:29:31.08#ibcon#enter sib2, iclass 38, count 0 2006.285.11:29:31.08#ibcon#flushed, iclass 38, count 0 2006.285.11:29:31.08#ibcon#about to write, iclass 38, count 0 2006.285.11:29:31.08#ibcon#wrote, iclass 38, count 0 2006.285.11:29:31.08#ibcon#about to read 3, iclass 38, count 0 2006.285.11:29:31.10#ibcon#read 3, iclass 38, count 0 2006.285.11:29:31.10#ibcon#about to read 4, iclass 38, count 0 2006.285.11:29:31.10#ibcon#read 4, iclass 38, count 0 2006.285.11:29:31.10#ibcon#about to read 5, iclass 38, count 0 2006.285.11:29:31.10#ibcon#read 5, iclass 38, count 0 2006.285.11:29:31.10#ibcon#about to read 6, iclass 38, count 0 2006.285.11:29:31.10#ibcon#read 6, iclass 38, count 0 2006.285.11:29:31.10#ibcon#end of sib2, iclass 38, count 0 2006.285.11:29:31.10#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:29:31.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:29:31.10#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:29:31.10#ibcon#*before write, iclass 38, count 0 2006.285.11:29:31.10#ibcon#enter sib2, iclass 38, count 0 2006.285.11:29:31.10#ibcon#flushed, iclass 38, count 0 2006.285.11:29:31.10#ibcon#about to write, iclass 38, count 0 2006.285.11:29:31.10#ibcon#wrote, iclass 38, count 0 2006.285.11:29:31.10#ibcon#about to read 3, iclass 38, count 0 2006.285.11:29:31.14#ibcon#read 3, iclass 38, count 0 2006.285.11:29:31.14#ibcon#about to read 4, iclass 38, count 0 2006.285.11:29:31.14#ibcon#read 4, iclass 38, count 0 2006.285.11:29:31.14#ibcon#about to read 5, iclass 38, count 0 2006.285.11:29:31.14#ibcon#read 5, iclass 38, count 0 2006.285.11:29:31.14#ibcon#about to read 6, iclass 38, count 0 2006.285.11:29:31.14#ibcon#read 6, iclass 38, count 0 2006.285.11:29:31.14#ibcon#end of sib2, iclass 38, count 0 2006.285.11:29:31.14#ibcon#*after write, iclass 38, count 0 2006.285.11:29:31.14#ibcon#*before return 0, iclass 38, count 0 2006.285.11:29:31.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:29:31.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:29:31.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:29:31.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:29:31.14$vck44/va=5,3 2006.285.11:29:31.14#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.11:29:31.14#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.11:29:31.14#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:31.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:29:31.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:29:31.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:29:31.20#ibcon#enter wrdev, iclass 40, count 2 2006.285.11:29:31.20#ibcon#first serial, iclass 40, count 2 2006.285.11:29:31.20#ibcon#enter sib2, iclass 40, count 2 2006.285.11:29:31.20#ibcon#flushed, iclass 40, count 2 2006.285.11:29:31.20#ibcon#about to write, iclass 40, count 2 2006.285.11:29:31.20#ibcon#wrote, iclass 40, count 2 2006.285.11:29:31.20#ibcon#about to read 3, iclass 40, count 2 2006.285.11:29:31.22#ibcon#read 3, iclass 40, count 2 2006.285.11:29:31.22#ibcon#about to read 4, iclass 40, count 2 2006.285.11:29:31.22#ibcon#read 4, iclass 40, count 2 2006.285.11:29:31.22#ibcon#about to read 5, iclass 40, count 2 2006.285.11:29:31.22#ibcon#read 5, iclass 40, count 2 2006.285.11:29:31.22#ibcon#about to read 6, iclass 40, count 2 2006.285.11:29:31.22#ibcon#read 6, iclass 40, count 2 2006.285.11:29:31.22#ibcon#end of sib2, iclass 40, count 2 2006.285.11:29:31.22#ibcon#*mode == 0, iclass 40, count 2 2006.285.11:29:31.22#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.11:29:31.22#ibcon#[25=AT05-03\r\n] 2006.285.11:29:31.22#ibcon#*before write, iclass 40, count 2 2006.285.11:29:31.22#ibcon#enter sib2, iclass 40, count 2 2006.285.11:29:31.22#ibcon#flushed, iclass 40, count 2 2006.285.11:29:31.22#ibcon#about to write, iclass 40, count 2 2006.285.11:29:31.22#ibcon#wrote, iclass 40, count 2 2006.285.11:29:31.22#ibcon#about to read 3, iclass 40, count 2 2006.285.11:29:31.25#ibcon#read 3, iclass 40, count 2 2006.285.11:29:31.25#ibcon#about to read 4, iclass 40, count 2 2006.285.11:29:31.25#ibcon#read 4, iclass 40, count 2 2006.285.11:29:31.25#ibcon#about to read 5, iclass 40, count 2 2006.285.11:29:31.25#ibcon#read 5, iclass 40, count 2 2006.285.11:29:31.25#ibcon#about to read 6, iclass 40, count 2 2006.285.11:29:31.25#ibcon#read 6, iclass 40, count 2 2006.285.11:29:31.25#ibcon#end of sib2, iclass 40, count 2 2006.285.11:29:31.25#ibcon#*after write, iclass 40, count 2 2006.285.11:29:31.25#ibcon#*before return 0, iclass 40, count 2 2006.285.11:29:31.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:29:31.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:29:31.25#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.11:29:31.25#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:31.25#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:29:31.37#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:29:31.37#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:29:31.37#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:29:31.37#ibcon#first serial, iclass 40, count 0 2006.285.11:29:31.37#ibcon#enter sib2, iclass 40, count 0 2006.285.11:29:31.37#ibcon#flushed, iclass 40, count 0 2006.285.11:29:31.37#ibcon#about to write, iclass 40, count 0 2006.285.11:29:31.37#ibcon#wrote, iclass 40, count 0 2006.285.11:29:31.37#ibcon#about to read 3, iclass 40, count 0 2006.285.11:29:31.39#ibcon#read 3, iclass 40, count 0 2006.285.11:29:31.39#ibcon#about to read 4, iclass 40, count 0 2006.285.11:29:31.39#ibcon#read 4, iclass 40, count 0 2006.285.11:29:31.39#ibcon#about to read 5, iclass 40, count 0 2006.285.11:29:31.39#ibcon#read 5, iclass 40, count 0 2006.285.11:29:31.39#ibcon#about to read 6, iclass 40, count 0 2006.285.11:29:31.39#ibcon#read 6, iclass 40, count 0 2006.285.11:29:31.39#ibcon#end of sib2, iclass 40, count 0 2006.285.11:29:31.39#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:29:31.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:29:31.39#ibcon#[25=USB\r\n] 2006.285.11:29:31.39#ibcon#*before write, iclass 40, count 0 2006.285.11:29:31.39#ibcon#enter sib2, iclass 40, count 0 2006.285.11:29:31.39#ibcon#flushed, iclass 40, count 0 2006.285.11:29:31.39#ibcon#about to write, iclass 40, count 0 2006.285.11:29:31.39#ibcon#wrote, iclass 40, count 0 2006.285.11:29:31.39#ibcon#about to read 3, iclass 40, count 0 2006.285.11:29:31.42#ibcon#read 3, iclass 40, count 0 2006.285.11:29:31.42#ibcon#about to read 4, iclass 40, count 0 2006.285.11:29:31.42#ibcon#read 4, iclass 40, count 0 2006.285.11:29:31.42#ibcon#about to read 5, iclass 40, count 0 2006.285.11:29:31.42#ibcon#read 5, iclass 40, count 0 2006.285.11:29:31.42#ibcon#about to read 6, iclass 40, count 0 2006.285.11:29:31.42#ibcon#read 6, iclass 40, count 0 2006.285.11:29:31.42#ibcon#end of sib2, iclass 40, count 0 2006.285.11:29:31.42#ibcon#*after write, iclass 40, count 0 2006.285.11:29:31.42#ibcon#*before return 0, iclass 40, count 0 2006.285.11:29:31.42#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:29:31.42#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:29:31.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:29:31.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:29:31.42$vck44/valo=6,814.99 2006.285.11:29:31.42#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.11:29:31.42#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.11:29:31.42#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:31.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:29:31.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:29:31.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:29:31.42#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:29:31.42#ibcon#first serial, iclass 4, count 0 2006.285.11:29:31.42#ibcon#enter sib2, iclass 4, count 0 2006.285.11:29:31.42#ibcon#flushed, iclass 4, count 0 2006.285.11:29:31.42#ibcon#about to write, iclass 4, count 0 2006.285.11:29:31.42#ibcon#wrote, iclass 4, count 0 2006.285.11:29:31.42#ibcon#about to read 3, iclass 4, count 0 2006.285.11:29:31.44#ibcon#read 3, iclass 4, count 0 2006.285.11:29:31.44#ibcon#about to read 4, iclass 4, count 0 2006.285.11:29:31.44#ibcon#read 4, iclass 4, count 0 2006.285.11:29:31.44#ibcon#about to read 5, iclass 4, count 0 2006.285.11:29:31.44#ibcon#read 5, iclass 4, count 0 2006.285.11:29:31.44#ibcon#about to read 6, iclass 4, count 0 2006.285.11:29:31.44#ibcon#read 6, iclass 4, count 0 2006.285.11:29:31.44#ibcon#end of sib2, iclass 4, count 0 2006.285.11:29:31.44#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:29:31.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:29:31.44#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:29:31.44#ibcon#*before write, iclass 4, count 0 2006.285.11:29:31.44#ibcon#enter sib2, iclass 4, count 0 2006.285.11:29:31.44#ibcon#flushed, iclass 4, count 0 2006.285.11:29:31.44#ibcon#about to write, iclass 4, count 0 2006.285.11:29:31.44#ibcon#wrote, iclass 4, count 0 2006.285.11:29:31.44#ibcon#about to read 3, iclass 4, count 0 2006.285.11:29:31.48#ibcon#read 3, iclass 4, count 0 2006.285.11:29:31.48#ibcon#about to read 4, iclass 4, count 0 2006.285.11:29:31.48#ibcon#read 4, iclass 4, count 0 2006.285.11:29:31.48#ibcon#about to read 5, iclass 4, count 0 2006.285.11:29:31.48#ibcon#read 5, iclass 4, count 0 2006.285.11:29:31.48#ibcon#about to read 6, iclass 4, count 0 2006.285.11:29:31.48#ibcon#read 6, iclass 4, count 0 2006.285.11:29:31.48#ibcon#end of sib2, iclass 4, count 0 2006.285.11:29:31.48#ibcon#*after write, iclass 4, count 0 2006.285.11:29:31.48#ibcon#*before return 0, iclass 4, count 0 2006.285.11:29:31.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:29:31.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:29:31.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:29:31.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:29:31.48$vck44/va=6,4 2006.285.11:29:31.48#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.11:29:31.48#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.11:29:31.48#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:31.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:29:31.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:29:31.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:29:31.54#ibcon#enter wrdev, iclass 6, count 2 2006.285.11:29:31.54#ibcon#first serial, iclass 6, count 2 2006.285.11:29:31.54#ibcon#enter sib2, iclass 6, count 2 2006.285.11:29:31.54#ibcon#flushed, iclass 6, count 2 2006.285.11:29:31.54#ibcon#about to write, iclass 6, count 2 2006.285.11:29:31.54#ibcon#wrote, iclass 6, count 2 2006.285.11:29:31.54#ibcon#about to read 3, iclass 6, count 2 2006.285.11:29:31.56#ibcon#read 3, iclass 6, count 2 2006.285.11:29:31.56#ibcon#about to read 4, iclass 6, count 2 2006.285.11:29:31.56#ibcon#read 4, iclass 6, count 2 2006.285.11:29:31.56#ibcon#about to read 5, iclass 6, count 2 2006.285.11:29:31.56#ibcon#read 5, iclass 6, count 2 2006.285.11:29:31.56#ibcon#about to read 6, iclass 6, count 2 2006.285.11:29:31.56#ibcon#read 6, iclass 6, count 2 2006.285.11:29:31.56#ibcon#end of sib2, iclass 6, count 2 2006.285.11:29:31.56#ibcon#*mode == 0, iclass 6, count 2 2006.285.11:29:31.56#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.11:29:31.56#ibcon#[25=AT06-04\r\n] 2006.285.11:29:31.56#ibcon#*before write, iclass 6, count 2 2006.285.11:29:31.56#ibcon#enter sib2, iclass 6, count 2 2006.285.11:29:31.56#ibcon#flushed, iclass 6, count 2 2006.285.11:29:31.56#ibcon#about to write, iclass 6, count 2 2006.285.11:29:31.56#ibcon#wrote, iclass 6, count 2 2006.285.11:29:31.56#ibcon#about to read 3, iclass 6, count 2 2006.285.11:29:31.59#ibcon#read 3, iclass 6, count 2 2006.285.11:29:31.59#ibcon#about to read 4, iclass 6, count 2 2006.285.11:29:31.59#ibcon#read 4, iclass 6, count 2 2006.285.11:29:31.59#ibcon#about to read 5, iclass 6, count 2 2006.285.11:29:31.59#ibcon#read 5, iclass 6, count 2 2006.285.11:29:31.59#ibcon#about to read 6, iclass 6, count 2 2006.285.11:29:31.59#ibcon#read 6, iclass 6, count 2 2006.285.11:29:31.59#ibcon#end of sib2, iclass 6, count 2 2006.285.11:29:31.59#ibcon#*after write, iclass 6, count 2 2006.285.11:29:31.59#ibcon#*before return 0, iclass 6, count 2 2006.285.11:29:31.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:29:31.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:29:31.59#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.11:29:31.59#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:31.59#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:29:31.71#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:29:31.71#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:29:31.71#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:29:31.71#ibcon#first serial, iclass 6, count 0 2006.285.11:29:31.71#ibcon#enter sib2, iclass 6, count 0 2006.285.11:29:31.71#ibcon#flushed, iclass 6, count 0 2006.285.11:29:31.71#ibcon#about to write, iclass 6, count 0 2006.285.11:29:31.71#ibcon#wrote, iclass 6, count 0 2006.285.11:29:31.71#ibcon#about to read 3, iclass 6, count 0 2006.285.11:29:31.73#ibcon#read 3, iclass 6, count 0 2006.285.11:29:31.73#ibcon#about to read 4, iclass 6, count 0 2006.285.11:29:31.73#ibcon#read 4, iclass 6, count 0 2006.285.11:29:31.73#ibcon#about to read 5, iclass 6, count 0 2006.285.11:29:31.73#ibcon#read 5, iclass 6, count 0 2006.285.11:29:31.73#ibcon#about to read 6, iclass 6, count 0 2006.285.11:29:31.73#ibcon#read 6, iclass 6, count 0 2006.285.11:29:31.73#ibcon#end of sib2, iclass 6, count 0 2006.285.11:29:31.73#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:29:31.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:29:31.73#ibcon#[25=USB\r\n] 2006.285.11:29:31.73#ibcon#*before write, iclass 6, count 0 2006.285.11:29:31.73#ibcon#enter sib2, iclass 6, count 0 2006.285.11:29:31.73#ibcon#flushed, iclass 6, count 0 2006.285.11:29:31.73#ibcon#about to write, iclass 6, count 0 2006.285.11:29:31.73#ibcon#wrote, iclass 6, count 0 2006.285.11:29:31.73#ibcon#about to read 3, iclass 6, count 0 2006.285.11:29:31.76#ibcon#read 3, iclass 6, count 0 2006.285.11:29:31.76#ibcon#about to read 4, iclass 6, count 0 2006.285.11:29:31.76#ibcon#read 4, iclass 6, count 0 2006.285.11:29:31.76#ibcon#about to read 5, iclass 6, count 0 2006.285.11:29:31.76#ibcon#read 5, iclass 6, count 0 2006.285.11:29:31.76#ibcon#about to read 6, iclass 6, count 0 2006.285.11:29:31.76#ibcon#read 6, iclass 6, count 0 2006.285.11:29:31.76#ibcon#end of sib2, iclass 6, count 0 2006.285.11:29:31.76#ibcon#*after write, iclass 6, count 0 2006.285.11:29:31.76#ibcon#*before return 0, iclass 6, count 0 2006.285.11:29:31.76#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:29:31.76#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:29:31.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:29:31.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:29:31.76$vck44/valo=7,864.99 2006.285.11:29:31.76#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.11:29:31.76#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.11:29:31.76#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:31.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:29:31.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:29:31.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:29:31.76#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:29:31.76#ibcon#first serial, iclass 10, count 0 2006.285.11:29:31.76#ibcon#enter sib2, iclass 10, count 0 2006.285.11:29:31.76#ibcon#flushed, iclass 10, count 0 2006.285.11:29:31.76#ibcon#about to write, iclass 10, count 0 2006.285.11:29:31.76#ibcon#wrote, iclass 10, count 0 2006.285.11:29:31.76#ibcon#about to read 3, iclass 10, count 0 2006.285.11:29:31.78#ibcon#read 3, iclass 10, count 0 2006.285.11:29:31.78#ibcon#about to read 4, iclass 10, count 0 2006.285.11:29:31.78#ibcon#read 4, iclass 10, count 0 2006.285.11:29:31.78#ibcon#about to read 5, iclass 10, count 0 2006.285.11:29:31.78#ibcon#read 5, iclass 10, count 0 2006.285.11:29:31.78#ibcon#about to read 6, iclass 10, count 0 2006.285.11:29:31.78#ibcon#read 6, iclass 10, count 0 2006.285.11:29:31.78#ibcon#end of sib2, iclass 10, count 0 2006.285.11:29:31.78#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:29:31.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:29:31.78#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:29:31.78#ibcon#*before write, iclass 10, count 0 2006.285.11:29:31.78#ibcon#enter sib2, iclass 10, count 0 2006.285.11:29:31.78#ibcon#flushed, iclass 10, count 0 2006.285.11:29:31.78#ibcon#about to write, iclass 10, count 0 2006.285.11:29:31.78#ibcon#wrote, iclass 10, count 0 2006.285.11:29:31.78#ibcon#about to read 3, iclass 10, count 0 2006.285.11:29:31.82#ibcon#read 3, iclass 10, count 0 2006.285.11:29:31.82#ibcon#about to read 4, iclass 10, count 0 2006.285.11:29:31.82#ibcon#read 4, iclass 10, count 0 2006.285.11:29:31.82#ibcon#about to read 5, iclass 10, count 0 2006.285.11:29:31.82#ibcon#read 5, iclass 10, count 0 2006.285.11:29:31.82#ibcon#about to read 6, iclass 10, count 0 2006.285.11:29:31.82#ibcon#read 6, iclass 10, count 0 2006.285.11:29:31.82#ibcon#end of sib2, iclass 10, count 0 2006.285.11:29:31.82#ibcon#*after write, iclass 10, count 0 2006.285.11:29:31.82#ibcon#*before return 0, iclass 10, count 0 2006.285.11:29:31.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:29:31.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:29:31.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:29:31.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:29:31.82$vck44/va=7,4 2006.285.11:29:31.82#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.11:29:31.82#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.11:29:31.82#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:31.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:29:31.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:29:31.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:29:31.88#ibcon#enter wrdev, iclass 12, count 2 2006.285.11:29:31.88#ibcon#first serial, iclass 12, count 2 2006.285.11:29:31.88#ibcon#enter sib2, iclass 12, count 2 2006.285.11:29:31.88#ibcon#flushed, iclass 12, count 2 2006.285.11:29:31.88#ibcon#about to write, iclass 12, count 2 2006.285.11:29:31.88#ibcon#wrote, iclass 12, count 2 2006.285.11:29:31.88#ibcon#about to read 3, iclass 12, count 2 2006.285.11:29:31.90#ibcon#read 3, iclass 12, count 2 2006.285.11:29:31.90#ibcon#about to read 4, iclass 12, count 2 2006.285.11:29:31.90#ibcon#read 4, iclass 12, count 2 2006.285.11:29:31.90#ibcon#about to read 5, iclass 12, count 2 2006.285.11:29:31.90#ibcon#read 5, iclass 12, count 2 2006.285.11:29:31.90#ibcon#about to read 6, iclass 12, count 2 2006.285.11:29:31.90#ibcon#read 6, iclass 12, count 2 2006.285.11:29:31.90#ibcon#end of sib2, iclass 12, count 2 2006.285.11:29:31.90#ibcon#*mode == 0, iclass 12, count 2 2006.285.11:29:31.90#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.11:29:31.90#ibcon#[25=AT07-04\r\n] 2006.285.11:29:31.90#ibcon#*before write, iclass 12, count 2 2006.285.11:29:31.90#ibcon#enter sib2, iclass 12, count 2 2006.285.11:29:31.90#ibcon#flushed, iclass 12, count 2 2006.285.11:29:31.90#ibcon#about to write, iclass 12, count 2 2006.285.11:29:31.90#ibcon#wrote, iclass 12, count 2 2006.285.11:29:31.90#ibcon#about to read 3, iclass 12, count 2 2006.285.11:29:31.93#ibcon#read 3, iclass 12, count 2 2006.285.11:29:31.93#ibcon#about to read 4, iclass 12, count 2 2006.285.11:29:31.93#ibcon#read 4, iclass 12, count 2 2006.285.11:29:31.93#ibcon#about to read 5, iclass 12, count 2 2006.285.11:29:31.93#ibcon#read 5, iclass 12, count 2 2006.285.11:29:31.93#ibcon#about to read 6, iclass 12, count 2 2006.285.11:29:31.93#ibcon#read 6, iclass 12, count 2 2006.285.11:29:31.93#ibcon#end of sib2, iclass 12, count 2 2006.285.11:29:31.93#ibcon#*after write, iclass 12, count 2 2006.285.11:29:31.93#ibcon#*before return 0, iclass 12, count 2 2006.285.11:29:31.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:29:31.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:29:31.93#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.11:29:31.93#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:31.93#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:29:32.05#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:29:32.05#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:29:32.05#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:29:32.05#ibcon#first serial, iclass 12, count 0 2006.285.11:29:32.05#ibcon#enter sib2, iclass 12, count 0 2006.285.11:29:32.05#ibcon#flushed, iclass 12, count 0 2006.285.11:29:32.05#ibcon#about to write, iclass 12, count 0 2006.285.11:29:32.05#ibcon#wrote, iclass 12, count 0 2006.285.11:29:32.05#ibcon#about to read 3, iclass 12, count 0 2006.285.11:29:32.07#ibcon#read 3, iclass 12, count 0 2006.285.11:29:32.07#ibcon#about to read 4, iclass 12, count 0 2006.285.11:29:32.07#ibcon#read 4, iclass 12, count 0 2006.285.11:29:32.07#ibcon#about to read 5, iclass 12, count 0 2006.285.11:29:32.07#ibcon#read 5, iclass 12, count 0 2006.285.11:29:32.07#ibcon#about to read 6, iclass 12, count 0 2006.285.11:29:32.07#ibcon#read 6, iclass 12, count 0 2006.285.11:29:32.07#ibcon#end of sib2, iclass 12, count 0 2006.285.11:29:32.07#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:29:32.07#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:29:32.07#ibcon#[25=USB\r\n] 2006.285.11:29:32.07#ibcon#*before write, iclass 12, count 0 2006.285.11:29:32.07#ibcon#enter sib2, iclass 12, count 0 2006.285.11:29:32.07#ibcon#flushed, iclass 12, count 0 2006.285.11:29:32.07#ibcon#about to write, iclass 12, count 0 2006.285.11:29:32.07#ibcon#wrote, iclass 12, count 0 2006.285.11:29:32.07#ibcon#about to read 3, iclass 12, count 0 2006.285.11:29:32.10#ibcon#read 3, iclass 12, count 0 2006.285.11:29:32.10#ibcon#about to read 4, iclass 12, count 0 2006.285.11:29:32.10#ibcon#read 4, iclass 12, count 0 2006.285.11:29:32.10#ibcon#about to read 5, iclass 12, count 0 2006.285.11:29:32.10#ibcon#read 5, iclass 12, count 0 2006.285.11:29:32.10#ibcon#about to read 6, iclass 12, count 0 2006.285.11:29:32.10#ibcon#read 6, iclass 12, count 0 2006.285.11:29:32.10#ibcon#end of sib2, iclass 12, count 0 2006.285.11:29:32.10#ibcon#*after write, iclass 12, count 0 2006.285.11:29:32.10#ibcon#*before return 0, iclass 12, count 0 2006.285.11:29:32.10#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:29:32.10#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:29:32.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:29:32.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:29:32.10$vck44/valo=8,884.99 2006.285.11:29:32.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.11:29:32.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.11:29:32.10#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:32.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:29:32.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:29:32.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:29:32.10#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:29:32.10#ibcon#first serial, iclass 14, count 0 2006.285.11:29:32.10#ibcon#enter sib2, iclass 14, count 0 2006.285.11:29:32.10#ibcon#flushed, iclass 14, count 0 2006.285.11:29:32.10#ibcon#about to write, iclass 14, count 0 2006.285.11:29:32.10#ibcon#wrote, iclass 14, count 0 2006.285.11:29:32.10#ibcon#about to read 3, iclass 14, count 0 2006.285.11:29:32.12#ibcon#read 3, iclass 14, count 0 2006.285.11:29:32.12#ibcon#about to read 4, iclass 14, count 0 2006.285.11:29:32.12#ibcon#read 4, iclass 14, count 0 2006.285.11:29:32.12#ibcon#about to read 5, iclass 14, count 0 2006.285.11:29:32.12#ibcon#read 5, iclass 14, count 0 2006.285.11:29:32.12#ibcon#about to read 6, iclass 14, count 0 2006.285.11:29:32.12#ibcon#read 6, iclass 14, count 0 2006.285.11:29:32.12#ibcon#end of sib2, iclass 14, count 0 2006.285.11:29:32.12#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:29:32.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:29:32.12#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:29:32.12#ibcon#*before write, iclass 14, count 0 2006.285.11:29:32.12#ibcon#enter sib2, iclass 14, count 0 2006.285.11:29:32.12#ibcon#flushed, iclass 14, count 0 2006.285.11:29:32.12#ibcon#about to write, iclass 14, count 0 2006.285.11:29:32.12#ibcon#wrote, iclass 14, count 0 2006.285.11:29:32.12#ibcon#about to read 3, iclass 14, count 0 2006.285.11:29:32.16#ibcon#read 3, iclass 14, count 0 2006.285.11:29:32.16#ibcon#about to read 4, iclass 14, count 0 2006.285.11:29:32.16#ibcon#read 4, iclass 14, count 0 2006.285.11:29:32.16#ibcon#about to read 5, iclass 14, count 0 2006.285.11:29:32.16#ibcon#read 5, iclass 14, count 0 2006.285.11:29:32.16#ibcon#about to read 6, iclass 14, count 0 2006.285.11:29:32.16#ibcon#read 6, iclass 14, count 0 2006.285.11:29:32.16#ibcon#end of sib2, iclass 14, count 0 2006.285.11:29:32.16#ibcon#*after write, iclass 14, count 0 2006.285.11:29:32.16#ibcon#*before return 0, iclass 14, count 0 2006.285.11:29:32.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:29:32.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:29:32.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:29:32.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:29:32.16$vck44/va=8,3 2006.285.11:29:32.16#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.11:29:32.16#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.11:29:32.16#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:32.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:29:32.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:29:32.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:29:32.22#ibcon#enter wrdev, iclass 16, count 2 2006.285.11:29:32.22#ibcon#first serial, iclass 16, count 2 2006.285.11:29:32.22#ibcon#enter sib2, iclass 16, count 2 2006.285.11:29:32.22#ibcon#flushed, iclass 16, count 2 2006.285.11:29:32.22#ibcon#about to write, iclass 16, count 2 2006.285.11:29:32.22#ibcon#wrote, iclass 16, count 2 2006.285.11:29:32.22#ibcon#about to read 3, iclass 16, count 2 2006.285.11:29:32.24#ibcon#read 3, iclass 16, count 2 2006.285.11:29:32.24#ibcon#about to read 4, iclass 16, count 2 2006.285.11:29:32.24#ibcon#read 4, iclass 16, count 2 2006.285.11:29:32.24#ibcon#about to read 5, iclass 16, count 2 2006.285.11:29:32.24#ibcon#read 5, iclass 16, count 2 2006.285.11:29:32.24#ibcon#about to read 6, iclass 16, count 2 2006.285.11:29:32.24#ibcon#read 6, iclass 16, count 2 2006.285.11:29:32.24#ibcon#end of sib2, iclass 16, count 2 2006.285.11:29:32.24#ibcon#*mode == 0, iclass 16, count 2 2006.285.11:29:32.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.11:29:32.24#ibcon#[25=AT08-03\r\n] 2006.285.11:29:32.24#ibcon#*before write, iclass 16, count 2 2006.285.11:29:32.24#ibcon#enter sib2, iclass 16, count 2 2006.285.11:29:32.24#ibcon#flushed, iclass 16, count 2 2006.285.11:29:32.24#ibcon#about to write, iclass 16, count 2 2006.285.11:29:32.24#ibcon#wrote, iclass 16, count 2 2006.285.11:29:32.24#ibcon#about to read 3, iclass 16, count 2 2006.285.11:29:32.27#ibcon#read 3, iclass 16, count 2 2006.285.11:29:32.27#ibcon#about to read 4, iclass 16, count 2 2006.285.11:29:32.27#ibcon#read 4, iclass 16, count 2 2006.285.11:29:32.27#ibcon#about to read 5, iclass 16, count 2 2006.285.11:29:32.27#ibcon#read 5, iclass 16, count 2 2006.285.11:29:32.27#ibcon#about to read 6, iclass 16, count 2 2006.285.11:29:32.27#ibcon#read 6, iclass 16, count 2 2006.285.11:29:32.27#ibcon#end of sib2, iclass 16, count 2 2006.285.11:29:32.27#ibcon#*after write, iclass 16, count 2 2006.285.11:29:32.27#ibcon#*before return 0, iclass 16, count 2 2006.285.11:29:32.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:29:32.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:29:32.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.11:29:32.27#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:32.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:29:32.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:29:32.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:29:32.39#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:29:32.39#ibcon#first serial, iclass 16, count 0 2006.285.11:29:32.39#ibcon#enter sib2, iclass 16, count 0 2006.285.11:29:32.39#ibcon#flushed, iclass 16, count 0 2006.285.11:29:32.39#ibcon#about to write, iclass 16, count 0 2006.285.11:29:32.39#ibcon#wrote, iclass 16, count 0 2006.285.11:29:32.39#ibcon#about to read 3, iclass 16, count 0 2006.285.11:29:32.41#ibcon#read 3, iclass 16, count 0 2006.285.11:29:32.41#ibcon#about to read 4, iclass 16, count 0 2006.285.11:29:32.41#ibcon#read 4, iclass 16, count 0 2006.285.11:29:32.41#ibcon#about to read 5, iclass 16, count 0 2006.285.11:29:32.41#ibcon#read 5, iclass 16, count 0 2006.285.11:29:32.41#ibcon#about to read 6, iclass 16, count 0 2006.285.11:29:32.41#ibcon#read 6, iclass 16, count 0 2006.285.11:29:32.41#ibcon#end of sib2, iclass 16, count 0 2006.285.11:29:32.41#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:29:32.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:29:32.41#ibcon#[25=USB\r\n] 2006.285.11:29:32.41#ibcon#*before write, iclass 16, count 0 2006.285.11:29:32.41#ibcon#enter sib2, iclass 16, count 0 2006.285.11:29:32.41#ibcon#flushed, iclass 16, count 0 2006.285.11:29:32.41#ibcon#about to write, iclass 16, count 0 2006.285.11:29:32.41#ibcon#wrote, iclass 16, count 0 2006.285.11:29:32.41#ibcon#about to read 3, iclass 16, count 0 2006.285.11:29:32.44#ibcon#read 3, iclass 16, count 0 2006.285.11:29:32.44#ibcon#about to read 4, iclass 16, count 0 2006.285.11:29:32.44#ibcon#read 4, iclass 16, count 0 2006.285.11:29:32.44#ibcon#about to read 5, iclass 16, count 0 2006.285.11:29:32.44#ibcon#read 5, iclass 16, count 0 2006.285.11:29:32.44#ibcon#about to read 6, iclass 16, count 0 2006.285.11:29:32.44#ibcon#read 6, iclass 16, count 0 2006.285.11:29:32.44#ibcon#end of sib2, iclass 16, count 0 2006.285.11:29:32.44#ibcon#*after write, iclass 16, count 0 2006.285.11:29:32.44#ibcon#*before return 0, iclass 16, count 0 2006.285.11:29:32.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:29:32.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:29:32.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:29:32.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:29:32.44$vck44/vblo=1,629.99 2006.285.11:29:32.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.11:29:32.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.11:29:32.44#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:32.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:29:32.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:29:32.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:29:32.44#ibcon#enter wrdev, iclass 18, count 0 2006.285.11:29:32.44#ibcon#first serial, iclass 18, count 0 2006.285.11:29:32.44#ibcon#enter sib2, iclass 18, count 0 2006.285.11:29:32.44#ibcon#flushed, iclass 18, count 0 2006.285.11:29:32.44#ibcon#about to write, iclass 18, count 0 2006.285.11:29:32.44#ibcon#wrote, iclass 18, count 0 2006.285.11:29:32.44#ibcon#about to read 3, iclass 18, count 0 2006.285.11:29:32.46#ibcon#read 3, iclass 18, count 0 2006.285.11:29:32.46#ibcon#about to read 4, iclass 18, count 0 2006.285.11:29:32.46#ibcon#read 4, iclass 18, count 0 2006.285.11:29:32.46#ibcon#about to read 5, iclass 18, count 0 2006.285.11:29:32.46#ibcon#read 5, iclass 18, count 0 2006.285.11:29:32.46#ibcon#about to read 6, iclass 18, count 0 2006.285.11:29:32.46#ibcon#read 6, iclass 18, count 0 2006.285.11:29:32.46#ibcon#end of sib2, iclass 18, count 0 2006.285.11:29:32.46#ibcon#*mode == 0, iclass 18, count 0 2006.285.11:29:32.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.11:29:32.46#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:29:32.46#ibcon#*before write, iclass 18, count 0 2006.285.11:29:32.46#ibcon#enter sib2, iclass 18, count 0 2006.285.11:29:32.46#ibcon#flushed, iclass 18, count 0 2006.285.11:29:32.46#ibcon#about to write, iclass 18, count 0 2006.285.11:29:32.46#ibcon#wrote, iclass 18, count 0 2006.285.11:29:32.46#ibcon#about to read 3, iclass 18, count 0 2006.285.11:29:32.50#ibcon#read 3, iclass 18, count 0 2006.285.11:29:32.50#ibcon#about to read 4, iclass 18, count 0 2006.285.11:29:32.50#ibcon#read 4, iclass 18, count 0 2006.285.11:29:32.50#ibcon#about to read 5, iclass 18, count 0 2006.285.11:29:32.50#ibcon#read 5, iclass 18, count 0 2006.285.11:29:32.50#ibcon#about to read 6, iclass 18, count 0 2006.285.11:29:32.50#ibcon#read 6, iclass 18, count 0 2006.285.11:29:32.50#ibcon#end of sib2, iclass 18, count 0 2006.285.11:29:32.50#ibcon#*after write, iclass 18, count 0 2006.285.11:29:32.50#ibcon#*before return 0, iclass 18, count 0 2006.285.11:29:32.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:29:32.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:29:32.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.11:29:32.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.11:29:32.50$vck44/vb=1,4 2006.285.11:29:32.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.11:29:32.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.11:29:32.50#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:32.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:29:32.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:29:32.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:29:32.50#ibcon#enter wrdev, iclass 20, count 2 2006.285.11:29:32.50#ibcon#first serial, iclass 20, count 2 2006.285.11:29:32.50#ibcon#enter sib2, iclass 20, count 2 2006.285.11:29:32.50#ibcon#flushed, iclass 20, count 2 2006.285.11:29:32.50#ibcon#about to write, iclass 20, count 2 2006.285.11:29:32.50#ibcon#wrote, iclass 20, count 2 2006.285.11:29:32.50#ibcon#about to read 3, iclass 20, count 2 2006.285.11:29:32.52#ibcon#read 3, iclass 20, count 2 2006.285.11:29:32.52#ibcon#about to read 4, iclass 20, count 2 2006.285.11:29:32.52#ibcon#read 4, iclass 20, count 2 2006.285.11:29:32.52#ibcon#about to read 5, iclass 20, count 2 2006.285.11:29:32.52#ibcon#read 5, iclass 20, count 2 2006.285.11:29:32.52#ibcon#about to read 6, iclass 20, count 2 2006.285.11:29:32.52#ibcon#read 6, iclass 20, count 2 2006.285.11:29:32.52#ibcon#end of sib2, iclass 20, count 2 2006.285.11:29:32.52#ibcon#*mode == 0, iclass 20, count 2 2006.285.11:29:32.52#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.11:29:32.52#ibcon#[27=AT01-04\r\n] 2006.285.11:29:32.52#ibcon#*before write, iclass 20, count 2 2006.285.11:29:32.52#ibcon#enter sib2, iclass 20, count 2 2006.285.11:29:32.52#ibcon#flushed, iclass 20, count 2 2006.285.11:29:32.52#ibcon#about to write, iclass 20, count 2 2006.285.11:29:32.52#ibcon#wrote, iclass 20, count 2 2006.285.11:29:32.52#ibcon#about to read 3, iclass 20, count 2 2006.285.11:29:32.55#ibcon#read 3, iclass 20, count 2 2006.285.11:29:32.55#ibcon#about to read 4, iclass 20, count 2 2006.285.11:29:32.55#ibcon#read 4, iclass 20, count 2 2006.285.11:29:32.55#ibcon#about to read 5, iclass 20, count 2 2006.285.11:29:32.55#ibcon#read 5, iclass 20, count 2 2006.285.11:29:32.55#ibcon#about to read 6, iclass 20, count 2 2006.285.11:29:32.55#ibcon#read 6, iclass 20, count 2 2006.285.11:29:32.55#ibcon#end of sib2, iclass 20, count 2 2006.285.11:29:32.55#ibcon#*after write, iclass 20, count 2 2006.285.11:29:32.55#ibcon#*before return 0, iclass 20, count 2 2006.285.11:29:32.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:29:32.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:29:32.55#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.11:29:32.55#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:32.55#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:29:32.67#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:29:32.67#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:29:32.67#ibcon#enter wrdev, iclass 20, count 0 2006.285.11:29:32.67#ibcon#first serial, iclass 20, count 0 2006.285.11:29:32.67#ibcon#enter sib2, iclass 20, count 0 2006.285.11:29:32.67#ibcon#flushed, iclass 20, count 0 2006.285.11:29:32.67#ibcon#about to write, iclass 20, count 0 2006.285.11:29:32.67#ibcon#wrote, iclass 20, count 0 2006.285.11:29:32.67#ibcon#about to read 3, iclass 20, count 0 2006.285.11:29:32.69#ibcon#read 3, iclass 20, count 0 2006.285.11:29:32.69#ibcon#about to read 4, iclass 20, count 0 2006.285.11:29:32.69#ibcon#read 4, iclass 20, count 0 2006.285.11:29:32.69#ibcon#about to read 5, iclass 20, count 0 2006.285.11:29:32.69#ibcon#read 5, iclass 20, count 0 2006.285.11:29:32.69#ibcon#about to read 6, iclass 20, count 0 2006.285.11:29:32.69#ibcon#read 6, iclass 20, count 0 2006.285.11:29:32.69#ibcon#end of sib2, iclass 20, count 0 2006.285.11:29:32.69#ibcon#*mode == 0, iclass 20, count 0 2006.285.11:29:32.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.11:29:32.69#ibcon#[27=USB\r\n] 2006.285.11:29:32.69#ibcon#*before write, iclass 20, count 0 2006.285.11:29:32.69#ibcon#enter sib2, iclass 20, count 0 2006.285.11:29:32.69#ibcon#flushed, iclass 20, count 0 2006.285.11:29:32.69#ibcon#about to write, iclass 20, count 0 2006.285.11:29:32.69#ibcon#wrote, iclass 20, count 0 2006.285.11:29:32.69#ibcon#about to read 3, iclass 20, count 0 2006.285.11:29:32.72#ibcon#read 3, iclass 20, count 0 2006.285.11:29:32.72#ibcon#about to read 4, iclass 20, count 0 2006.285.11:29:32.72#ibcon#read 4, iclass 20, count 0 2006.285.11:29:32.72#ibcon#about to read 5, iclass 20, count 0 2006.285.11:29:32.72#ibcon#read 5, iclass 20, count 0 2006.285.11:29:32.72#ibcon#about to read 6, iclass 20, count 0 2006.285.11:29:32.72#ibcon#read 6, iclass 20, count 0 2006.285.11:29:32.72#ibcon#end of sib2, iclass 20, count 0 2006.285.11:29:32.72#ibcon#*after write, iclass 20, count 0 2006.285.11:29:32.72#ibcon#*before return 0, iclass 20, count 0 2006.285.11:29:32.72#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:29:32.72#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:29:32.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.11:29:32.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.11:29:32.72$vck44/vblo=2,634.99 2006.285.11:29:32.72#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.11:29:32.72#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.11:29:32.72#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:32.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:29:32.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:29:32.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:29:32.72#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:29:32.72#ibcon#first serial, iclass 22, count 0 2006.285.11:29:32.72#ibcon#enter sib2, iclass 22, count 0 2006.285.11:29:32.72#ibcon#flushed, iclass 22, count 0 2006.285.11:29:32.72#ibcon#about to write, iclass 22, count 0 2006.285.11:29:32.72#ibcon#wrote, iclass 22, count 0 2006.285.11:29:32.72#ibcon#about to read 3, iclass 22, count 0 2006.285.11:29:32.74#ibcon#read 3, iclass 22, count 0 2006.285.11:29:32.74#ibcon#about to read 4, iclass 22, count 0 2006.285.11:29:32.74#ibcon#read 4, iclass 22, count 0 2006.285.11:29:32.74#ibcon#about to read 5, iclass 22, count 0 2006.285.11:29:32.74#ibcon#read 5, iclass 22, count 0 2006.285.11:29:32.74#ibcon#about to read 6, iclass 22, count 0 2006.285.11:29:32.74#ibcon#read 6, iclass 22, count 0 2006.285.11:29:32.74#ibcon#end of sib2, iclass 22, count 0 2006.285.11:29:32.74#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:29:32.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:29:32.74#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:29:32.74#ibcon#*before write, iclass 22, count 0 2006.285.11:29:32.74#ibcon#enter sib2, iclass 22, count 0 2006.285.11:29:32.74#ibcon#flushed, iclass 22, count 0 2006.285.11:29:32.74#ibcon#about to write, iclass 22, count 0 2006.285.11:29:32.74#ibcon#wrote, iclass 22, count 0 2006.285.11:29:32.74#ibcon#about to read 3, iclass 22, count 0 2006.285.11:29:32.78#ibcon#read 3, iclass 22, count 0 2006.285.11:29:32.78#ibcon#about to read 4, iclass 22, count 0 2006.285.11:29:32.78#ibcon#read 4, iclass 22, count 0 2006.285.11:29:32.78#ibcon#about to read 5, iclass 22, count 0 2006.285.11:29:32.78#ibcon#read 5, iclass 22, count 0 2006.285.11:29:32.78#ibcon#about to read 6, iclass 22, count 0 2006.285.11:29:32.78#ibcon#read 6, iclass 22, count 0 2006.285.11:29:32.78#ibcon#end of sib2, iclass 22, count 0 2006.285.11:29:32.78#ibcon#*after write, iclass 22, count 0 2006.285.11:29:32.78#ibcon#*before return 0, iclass 22, count 0 2006.285.11:29:32.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:29:32.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:29:32.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:29:32.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:29:32.78$vck44/vb=2,5 2006.285.11:29:32.78#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.11:29:32.78#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.11:29:32.78#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:32.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:29:32.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:29:32.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:29:32.84#ibcon#enter wrdev, iclass 24, count 2 2006.285.11:29:32.84#ibcon#first serial, iclass 24, count 2 2006.285.11:29:32.84#ibcon#enter sib2, iclass 24, count 2 2006.285.11:29:32.84#ibcon#flushed, iclass 24, count 2 2006.285.11:29:32.84#ibcon#about to write, iclass 24, count 2 2006.285.11:29:32.84#ibcon#wrote, iclass 24, count 2 2006.285.11:29:32.84#ibcon#about to read 3, iclass 24, count 2 2006.285.11:29:32.86#ibcon#read 3, iclass 24, count 2 2006.285.11:29:32.86#ibcon#about to read 4, iclass 24, count 2 2006.285.11:29:32.86#ibcon#read 4, iclass 24, count 2 2006.285.11:29:32.86#ibcon#about to read 5, iclass 24, count 2 2006.285.11:29:32.86#ibcon#read 5, iclass 24, count 2 2006.285.11:29:32.86#ibcon#about to read 6, iclass 24, count 2 2006.285.11:29:32.86#ibcon#read 6, iclass 24, count 2 2006.285.11:29:32.86#ibcon#end of sib2, iclass 24, count 2 2006.285.11:29:32.86#ibcon#*mode == 0, iclass 24, count 2 2006.285.11:29:32.86#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.11:29:32.86#ibcon#[27=AT02-05\r\n] 2006.285.11:29:32.86#ibcon#*before write, iclass 24, count 2 2006.285.11:29:32.86#ibcon#enter sib2, iclass 24, count 2 2006.285.11:29:32.86#ibcon#flushed, iclass 24, count 2 2006.285.11:29:32.86#ibcon#about to write, iclass 24, count 2 2006.285.11:29:32.86#ibcon#wrote, iclass 24, count 2 2006.285.11:29:32.86#ibcon#about to read 3, iclass 24, count 2 2006.285.11:29:32.89#ibcon#read 3, iclass 24, count 2 2006.285.11:29:32.89#ibcon#about to read 4, iclass 24, count 2 2006.285.11:29:32.89#ibcon#read 4, iclass 24, count 2 2006.285.11:29:32.89#ibcon#about to read 5, iclass 24, count 2 2006.285.11:29:32.89#ibcon#read 5, iclass 24, count 2 2006.285.11:29:32.89#ibcon#about to read 6, iclass 24, count 2 2006.285.11:29:32.89#ibcon#read 6, iclass 24, count 2 2006.285.11:29:32.89#ibcon#end of sib2, iclass 24, count 2 2006.285.11:29:32.89#ibcon#*after write, iclass 24, count 2 2006.285.11:29:32.89#ibcon#*before return 0, iclass 24, count 2 2006.285.11:29:32.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:29:32.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:29:32.89#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.11:29:32.89#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:32.89#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:29:33.01#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:29:33.01#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:29:33.01#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:29:33.01#ibcon#first serial, iclass 24, count 0 2006.285.11:29:33.01#ibcon#enter sib2, iclass 24, count 0 2006.285.11:29:33.01#ibcon#flushed, iclass 24, count 0 2006.285.11:29:33.01#ibcon#about to write, iclass 24, count 0 2006.285.11:29:33.01#ibcon#wrote, iclass 24, count 0 2006.285.11:29:33.01#ibcon#about to read 3, iclass 24, count 0 2006.285.11:29:33.03#ibcon#read 3, iclass 24, count 0 2006.285.11:29:33.03#ibcon#about to read 4, iclass 24, count 0 2006.285.11:29:33.03#ibcon#read 4, iclass 24, count 0 2006.285.11:29:33.03#ibcon#about to read 5, iclass 24, count 0 2006.285.11:29:33.03#ibcon#read 5, iclass 24, count 0 2006.285.11:29:33.03#ibcon#about to read 6, iclass 24, count 0 2006.285.11:29:33.03#ibcon#read 6, iclass 24, count 0 2006.285.11:29:33.03#ibcon#end of sib2, iclass 24, count 0 2006.285.11:29:33.03#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:29:33.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:29:33.03#ibcon#[27=USB\r\n] 2006.285.11:29:33.03#ibcon#*before write, iclass 24, count 0 2006.285.11:29:33.03#ibcon#enter sib2, iclass 24, count 0 2006.285.11:29:33.03#ibcon#flushed, iclass 24, count 0 2006.285.11:29:33.03#ibcon#about to write, iclass 24, count 0 2006.285.11:29:33.03#ibcon#wrote, iclass 24, count 0 2006.285.11:29:33.03#ibcon#about to read 3, iclass 24, count 0 2006.285.11:29:33.06#ibcon#read 3, iclass 24, count 0 2006.285.11:29:33.06#ibcon#about to read 4, iclass 24, count 0 2006.285.11:29:33.06#ibcon#read 4, iclass 24, count 0 2006.285.11:29:33.06#ibcon#about to read 5, iclass 24, count 0 2006.285.11:29:33.06#ibcon#read 5, iclass 24, count 0 2006.285.11:29:33.06#ibcon#about to read 6, iclass 24, count 0 2006.285.11:29:33.06#ibcon#read 6, iclass 24, count 0 2006.285.11:29:33.06#ibcon#end of sib2, iclass 24, count 0 2006.285.11:29:33.06#ibcon#*after write, iclass 24, count 0 2006.285.11:29:33.06#ibcon#*before return 0, iclass 24, count 0 2006.285.11:29:33.06#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:29:33.06#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:29:33.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:29:33.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:29:33.06$vck44/vblo=3,649.99 2006.285.11:29:33.06#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.11:29:33.06#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.11:29:33.06#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:33.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:29:33.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:29:33.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:29:33.06#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:29:33.06#ibcon#first serial, iclass 26, count 0 2006.285.11:29:33.06#ibcon#enter sib2, iclass 26, count 0 2006.285.11:29:33.06#ibcon#flushed, iclass 26, count 0 2006.285.11:29:33.06#ibcon#about to write, iclass 26, count 0 2006.285.11:29:33.06#ibcon#wrote, iclass 26, count 0 2006.285.11:29:33.06#ibcon#about to read 3, iclass 26, count 0 2006.285.11:29:33.08#ibcon#read 3, iclass 26, count 0 2006.285.11:29:33.08#ibcon#about to read 4, iclass 26, count 0 2006.285.11:29:33.08#ibcon#read 4, iclass 26, count 0 2006.285.11:29:33.08#ibcon#about to read 5, iclass 26, count 0 2006.285.11:29:33.08#ibcon#read 5, iclass 26, count 0 2006.285.11:29:33.08#ibcon#about to read 6, iclass 26, count 0 2006.285.11:29:33.08#ibcon#read 6, iclass 26, count 0 2006.285.11:29:33.08#ibcon#end of sib2, iclass 26, count 0 2006.285.11:29:33.08#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:29:33.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:29:33.08#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:29:33.08#ibcon#*before write, iclass 26, count 0 2006.285.11:29:33.08#ibcon#enter sib2, iclass 26, count 0 2006.285.11:29:33.08#ibcon#flushed, iclass 26, count 0 2006.285.11:29:33.08#ibcon#about to write, iclass 26, count 0 2006.285.11:29:33.08#ibcon#wrote, iclass 26, count 0 2006.285.11:29:33.08#ibcon#about to read 3, iclass 26, count 0 2006.285.11:29:33.12#ibcon#read 3, iclass 26, count 0 2006.285.11:29:33.12#ibcon#about to read 4, iclass 26, count 0 2006.285.11:29:33.12#ibcon#read 4, iclass 26, count 0 2006.285.11:29:33.12#ibcon#about to read 5, iclass 26, count 0 2006.285.11:29:33.12#ibcon#read 5, iclass 26, count 0 2006.285.11:29:33.12#ibcon#about to read 6, iclass 26, count 0 2006.285.11:29:33.12#ibcon#read 6, iclass 26, count 0 2006.285.11:29:33.12#ibcon#end of sib2, iclass 26, count 0 2006.285.11:29:33.12#ibcon#*after write, iclass 26, count 0 2006.285.11:29:33.12#ibcon#*before return 0, iclass 26, count 0 2006.285.11:29:33.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:29:33.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:29:33.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:29:33.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:29:33.12$vck44/vb=3,4 2006.285.11:29:33.12#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.11:29:33.12#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.11:29:33.12#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:33.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:29:33.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:29:33.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:29:33.18#ibcon#enter wrdev, iclass 28, count 2 2006.285.11:29:33.18#ibcon#first serial, iclass 28, count 2 2006.285.11:29:33.18#ibcon#enter sib2, iclass 28, count 2 2006.285.11:29:33.18#ibcon#flushed, iclass 28, count 2 2006.285.11:29:33.18#ibcon#about to write, iclass 28, count 2 2006.285.11:29:33.18#ibcon#wrote, iclass 28, count 2 2006.285.11:29:33.18#ibcon#about to read 3, iclass 28, count 2 2006.285.11:29:33.20#ibcon#read 3, iclass 28, count 2 2006.285.11:29:33.20#ibcon#about to read 4, iclass 28, count 2 2006.285.11:29:33.20#ibcon#read 4, iclass 28, count 2 2006.285.11:29:33.20#ibcon#about to read 5, iclass 28, count 2 2006.285.11:29:33.20#ibcon#read 5, iclass 28, count 2 2006.285.11:29:33.20#ibcon#about to read 6, iclass 28, count 2 2006.285.11:29:33.20#ibcon#read 6, iclass 28, count 2 2006.285.11:29:33.20#ibcon#end of sib2, iclass 28, count 2 2006.285.11:29:33.20#ibcon#*mode == 0, iclass 28, count 2 2006.285.11:29:33.20#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.11:29:33.20#ibcon#[27=AT03-04\r\n] 2006.285.11:29:33.20#ibcon#*before write, iclass 28, count 2 2006.285.11:29:33.20#ibcon#enter sib2, iclass 28, count 2 2006.285.11:29:33.20#ibcon#flushed, iclass 28, count 2 2006.285.11:29:33.20#ibcon#about to write, iclass 28, count 2 2006.285.11:29:33.20#ibcon#wrote, iclass 28, count 2 2006.285.11:29:33.20#ibcon#about to read 3, iclass 28, count 2 2006.285.11:29:33.23#ibcon#read 3, iclass 28, count 2 2006.285.11:29:33.23#ibcon#about to read 4, iclass 28, count 2 2006.285.11:29:33.23#ibcon#read 4, iclass 28, count 2 2006.285.11:29:33.23#ibcon#about to read 5, iclass 28, count 2 2006.285.11:29:33.23#ibcon#read 5, iclass 28, count 2 2006.285.11:29:33.23#ibcon#about to read 6, iclass 28, count 2 2006.285.11:29:33.23#ibcon#read 6, iclass 28, count 2 2006.285.11:29:33.23#ibcon#end of sib2, iclass 28, count 2 2006.285.11:29:33.23#ibcon#*after write, iclass 28, count 2 2006.285.11:29:33.23#ibcon#*before return 0, iclass 28, count 2 2006.285.11:29:33.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:29:33.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:29:33.23#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.11:29:33.23#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:33.23#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:29:33.35#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:29:33.35#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:29:33.35#ibcon#enter wrdev, iclass 28, count 0 2006.285.11:29:33.35#ibcon#first serial, iclass 28, count 0 2006.285.11:29:33.35#ibcon#enter sib2, iclass 28, count 0 2006.285.11:29:33.35#ibcon#flushed, iclass 28, count 0 2006.285.11:29:33.35#ibcon#about to write, iclass 28, count 0 2006.285.11:29:33.35#ibcon#wrote, iclass 28, count 0 2006.285.11:29:33.35#ibcon#about to read 3, iclass 28, count 0 2006.285.11:29:33.37#ibcon#read 3, iclass 28, count 0 2006.285.11:29:33.37#ibcon#about to read 4, iclass 28, count 0 2006.285.11:29:33.37#ibcon#read 4, iclass 28, count 0 2006.285.11:29:33.37#ibcon#about to read 5, iclass 28, count 0 2006.285.11:29:33.37#ibcon#read 5, iclass 28, count 0 2006.285.11:29:33.37#ibcon#about to read 6, iclass 28, count 0 2006.285.11:29:33.37#ibcon#read 6, iclass 28, count 0 2006.285.11:29:33.37#ibcon#end of sib2, iclass 28, count 0 2006.285.11:29:33.37#ibcon#*mode == 0, iclass 28, count 0 2006.285.11:29:33.37#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.11:29:33.37#ibcon#[27=USB\r\n] 2006.285.11:29:33.37#ibcon#*before write, iclass 28, count 0 2006.285.11:29:33.37#ibcon#enter sib2, iclass 28, count 0 2006.285.11:29:33.37#ibcon#flushed, iclass 28, count 0 2006.285.11:29:33.37#ibcon#about to write, iclass 28, count 0 2006.285.11:29:33.37#ibcon#wrote, iclass 28, count 0 2006.285.11:29:33.37#ibcon#about to read 3, iclass 28, count 0 2006.285.11:29:33.40#ibcon#read 3, iclass 28, count 0 2006.285.11:29:33.40#ibcon#about to read 4, iclass 28, count 0 2006.285.11:29:33.40#ibcon#read 4, iclass 28, count 0 2006.285.11:29:33.40#ibcon#about to read 5, iclass 28, count 0 2006.285.11:29:33.40#ibcon#read 5, iclass 28, count 0 2006.285.11:29:33.40#ibcon#about to read 6, iclass 28, count 0 2006.285.11:29:33.40#ibcon#read 6, iclass 28, count 0 2006.285.11:29:33.40#ibcon#end of sib2, iclass 28, count 0 2006.285.11:29:33.40#ibcon#*after write, iclass 28, count 0 2006.285.11:29:33.40#ibcon#*before return 0, iclass 28, count 0 2006.285.11:29:33.40#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:29:33.40#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:29:33.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.11:29:33.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.11:29:33.40$vck44/vblo=4,679.99 2006.285.11:29:33.40#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.11:29:33.40#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.11:29:33.40#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:33.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:29:33.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:29:33.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:29:33.40#ibcon#enter wrdev, iclass 30, count 0 2006.285.11:29:33.40#ibcon#first serial, iclass 30, count 0 2006.285.11:29:33.40#ibcon#enter sib2, iclass 30, count 0 2006.285.11:29:33.40#ibcon#flushed, iclass 30, count 0 2006.285.11:29:33.40#ibcon#about to write, iclass 30, count 0 2006.285.11:29:33.40#ibcon#wrote, iclass 30, count 0 2006.285.11:29:33.40#ibcon#about to read 3, iclass 30, count 0 2006.285.11:29:33.42#ibcon#read 3, iclass 30, count 0 2006.285.11:29:33.42#ibcon#about to read 4, iclass 30, count 0 2006.285.11:29:33.42#ibcon#read 4, iclass 30, count 0 2006.285.11:29:33.42#ibcon#about to read 5, iclass 30, count 0 2006.285.11:29:33.42#ibcon#read 5, iclass 30, count 0 2006.285.11:29:33.42#ibcon#about to read 6, iclass 30, count 0 2006.285.11:29:33.42#ibcon#read 6, iclass 30, count 0 2006.285.11:29:33.42#ibcon#end of sib2, iclass 30, count 0 2006.285.11:29:33.42#ibcon#*mode == 0, iclass 30, count 0 2006.285.11:29:33.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.11:29:33.42#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:29:33.42#ibcon#*before write, iclass 30, count 0 2006.285.11:29:33.42#ibcon#enter sib2, iclass 30, count 0 2006.285.11:29:33.42#ibcon#flushed, iclass 30, count 0 2006.285.11:29:33.42#ibcon#about to write, iclass 30, count 0 2006.285.11:29:33.42#ibcon#wrote, iclass 30, count 0 2006.285.11:29:33.42#ibcon#about to read 3, iclass 30, count 0 2006.285.11:29:33.46#ibcon#read 3, iclass 30, count 0 2006.285.11:29:33.46#ibcon#about to read 4, iclass 30, count 0 2006.285.11:29:33.46#ibcon#read 4, iclass 30, count 0 2006.285.11:29:33.46#ibcon#about to read 5, iclass 30, count 0 2006.285.11:29:33.46#ibcon#read 5, iclass 30, count 0 2006.285.11:29:33.46#ibcon#about to read 6, iclass 30, count 0 2006.285.11:29:33.46#ibcon#read 6, iclass 30, count 0 2006.285.11:29:33.46#ibcon#end of sib2, iclass 30, count 0 2006.285.11:29:33.46#ibcon#*after write, iclass 30, count 0 2006.285.11:29:33.46#ibcon#*before return 0, iclass 30, count 0 2006.285.11:29:33.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:29:33.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:29:33.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.11:29:33.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.11:29:33.46$vck44/vb=4,5 2006.285.11:29:33.46#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.11:29:33.46#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.11:29:33.46#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:33.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:29:33.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:29:33.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:29:33.52#ibcon#enter wrdev, iclass 32, count 2 2006.285.11:29:33.52#ibcon#first serial, iclass 32, count 2 2006.285.11:29:33.52#ibcon#enter sib2, iclass 32, count 2 2006.285.11:29:33.52#ibcon#flushed, iclass 32, count 2 2006.285.11:29:33.52#ibcon#about to write, iclass 32, count 2 2006.285.11:29:33.52#ibcon#wrote, iclass 32, count 2 2006.285.11:29:33.52#ibcon#about to read 3, iclass 32, count 2 2006.285.11:29:33.54#ibcon#read 3, iclass 32, count 2 2006.285.11:29:33.54#ibcon#about to read 4, iclass 32, count 2 2006.285.11:29:33.54#ibcon#read 4, iclass 32, count 2 2006.285.11:29:33.54#ibcon#about to read 5, iclass 32, count 2 2006.285.11:29:33.54#ibcon#read 5, iclass 32, count 2 2006.285.11:29:33.54#ibcon#about to read 6, iclass 32, count 2 2006.285.11:29:33.54#ibcon#read 6, iclass 32, count 2 2006.285.11:29:33.54#ibcon#end of sib2, iclass 32, count 2 2006.285.11:29:33.54#ibcon#*mode == 0, iclass 32, count 2 2006.285.11:29:33.54#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.11:29:33.54#ibcon#[27=AT04-05\r\n] 2006.285.11:29:33.54#ibcon#*before write, iclass 32, count 2 2006.285.11:29:33.54#ibcon#enter sib2, iclass 32, count 2 2006.285.11:29:33.54#ibcon#flushed, iclass 32, count 2 2006.285.11:29:33.54#ibcon#about to write, iclass 32, count 2 2006.285.11:29:33.54#ibcon#wrote, iclass 32, count 2 2006.285.11:29:33.54#ibcon#about to read 3, iclass 32, count 2 2006.285.11:29:33.57#ibcon#read 3, iclass 32, count 2 2006.285.11:29:33.57#ibcon#about to read 4, iclass 32, count 2 2006.285.11:29:33.57#ibcon#read 4, iclass 32, count 2 2006.285.11:29:33.57#ibcon#about to read 5, iclass 32, count 2 2006.285.11:29:33.57#ibcon#read 5, iclass 32, count 2 2006.285.11:29:33.57#ibcon#about to read 6, iclass 32, count 2 2006.285.11:29:33.57#ibcon#read 6, iclass 32, count 2 2006.285.11:29:33.57#ibcon#end of sib2, iclass 32, count 2 2006.285.11:29:33.57#ibcon#*after write, iclass 32, count 2 2006.285.11:29:33.57#ibcon#*before return 0, iclass 32, count 2 2006.285.11:29:33.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:29:33.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:29:33.57#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.11:29:33.57#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:33.57#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:29:33.69#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:29:33.69#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:29:33.69#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:29:33.69#ibcon#first serial, iclass 32, count 0 2006.285.11:29:33.69#ibcon#enter sib2, iclass 32, count 0 2006.285.11:29:33.69#ibcon#flushed, iclass 32, count 0 2006.285.11:29:33.69#ibcon#about to write, iclass 32, count 0 2006.285.11:29:33.69#ibcon#wrote, iclass 32, count 0 2006.285.11:29:33.69#ibcon#about to read 3, iclass 32, count 0 2006.285.11:29:33.71#ibcon#read 3, iclass 32, count 0 2006.285.11:29:33.71#ibcon#about to read 4, iclass 32, count 0 2006.285.11:29:33.71#ibcon#read 4, iclass 32, count 0 2006.285.11:29:33.71#ibcon#about to read 5, iclass 32, count 0 2006.285.11:29:33.71#ibcon#read 5, iclass 32, count 0 2006.285.11:29:33.71#ibcon#about to read 6, iclass 32, count 0 2006.285.11:29:33.71#ibcon#read 6, iclass 32, count 0 2006.285.11:29:33.71#ibcon#end of sib2, iclass 32, count 0 2006.285.11:29:33.71#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:29:33.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:29:33.71#ibcon#[27=USB\r\n] 2006.285.11:29:33.71#ibcon#*before write, iclass 32, count 0 2006.285.11:29:33.71#ibcon#enter sib2, iclass 32, count 0 2006.285.11:29:33.71#ibcon#flushed, iclass 32, count 0 2006.285.11:29:33.71#ibcon#about to write, iclass 32, count 0 2006.285.11:29:33.71#ibcon#wrote, iclass 32, count 0 2006.285.11:29:33.71#ibcon#about to read 3, iclass 32, count 0 2006.285.11:29:33.74#ibcon#read 3, iclass 32, count 0 2006.285.11:29:33.74#ibcon#about to read 4, iclass 32, count 0 2006.285.11:29:33.74#ibcon#read 4, iclass 32, count 0 2006.285.11:29:33.74#ibcon#about to read 5, iclass 32, count 0 2006.285.11:29:33.74#ibcon#read 5, iclass 32, count 0 2006.285.11:29:33.74#ibcon#about to read 6, iclass 32, count 0 2006.285.11:29:33.74#ibcon#read 6, iclass 32, count 0 2006.285.11:29:33.74#ibcon#end of sib2, iclass 32, count 0 2006.285.11:29:33.74#ibcon#*after write, iclass 32, count 0 2006.285.11:29:33.74#ibcon#*before return 0, iclass 32, count 0 2006.285.11:29:33.74#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:29:33.74#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:29:33.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:29:33.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:29:33.74$vck44/vblo=5,709.99 2006.285.11:29:33.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.11:29:33.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.11:29:33.74#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:33.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:29:33.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:29:33.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:29:33.74#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:29:33.74#ibcon#first serial, iclass 34, count 0 2006.285.11:29:33.74#ibcon#enter sib2, iclass 34, count 0 2006.285.11:29:33.74#ibcon#flushed, iclass 34, count 0 2006.285.11:29:33.74#ibcon#about to write, iclass 34, count 0 2006.285.11:29:33.74#ibcon#wrote, iclass 34, count 0 2006.285.11:29:33.74#ibcon#about to read 3, iclass 34, count 0 2006.285.11:29:33.76#ibcon#read 3, iclass 34, count 0 2006.285.11:29:33.76#ibcon#about to read 4, iclass 34, count 0 2006.285.11:29:33.76#ibcon#read 4, iclass 34, count 0 2006.285.11:29:33.76#ibcon#about to read 5, iclass 34, count 0 2006.285.11:29:33.76#ibcon#read 5, iclass 34, count 0 2006.285.11:29:33.76#ibcon#about to read 6, iclass 34, count 0 2006.285.11:29:33.76#ibcon#read 6, iclass 34, count 0 2006.285.11:29:33.76#ibcon#end of sib2, iclass 34, count 0 2006.285.11:29:33.76#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:29:33.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:29:33.76#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:29:33.76#ibcon#*before write, iclass 34, count 0 2006.285.11:29:33.76#ibcon#enter sib2, iclass 34, count 0 2006.285.11:29:33.76#ibcon#flushed, iclass 34, count 0 2006.285.11:29:33.76#ibcon#about to write, iclass 34, count 0 2006.285.11:29:33.76#ibcon#wrote, iclass 34, count 0 2006.285.11:29:33.76#ibcon#about to read 3, iclass 34, count 0 2006.285.11:29:33.80#ibcon#read 3, iclass 34, count 0 2006.285.11:29:33.80#ibcon#about to read 4, iclass 34, count 0 2006.285.11:29:33.80#ibcon#read 4, iclass 34, count 0 2006.285.11:29:33.80#ibcon#about to read 5, iclass 34, count 0 2006.285.11:29:33.80#ibcon#read 5, iclass 34, count 0 2006.285.11:29:33.80#ibcon#about to read 6, iclass 34, count 0 2006.285.11:29:33.80#ibcon#read 6, iclass 34, count 0 2006.285.11:29:33.80#ibcon#end of sib2, iclass 34, count 0 2006.285.11:29:33.80#ibcon#*after write, iclass 34, count 0 2006.285.11:29:33.80#ibcon#*before return 0, iclass 34, count 0 2006.285.11:29:33.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:29:33.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:29:33.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:29:33.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:29:33.80$vck44/vb=5,4 2006.285.11:29:33.80#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.11:29:33.80#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.11:29:33.80#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:33.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:29:33.86#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:29:33.86#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:29:33.86#ibcon#enter wrdev, iclass 36, count 2 2006.285.11:29:33.86#ibcon#first serial, iclass 36, count 2 2006.285.11:29:33.86#ibcon#enter sib2, iclass 36, count 2 2006.285.11:29:33.86#ibcon#flushed, iclass 36, count 2 2006.285.11:29:33.86#ibcon#about to write, iclass 36, count 2 2006.285.11:29:33.86#ibcon#wrote, iclass 36, count 2 2006.285.11:29:33.86#ibcon#about to read 3, iclass 36, count 2 2006.285.11:29:33.88#ibcon#read 3, iclass 36, count 2 2006.285.11:29:33.88#ibcon#about to read 4, iclass 36, count 2 2006.285.11:29:33.88#ibcon#read 4, iclass 36, count 2 2006.285.11:29:33.88#ibcon#about to read 5, iclass 36, count 2 2006.285.11:29:33.88#ibcon#read 5, iclass 36, count 2 2006.285.11:29:33.88#ibcon#about to read 6, iclass 36, count 2 2006.285.11:29:33.88#ibcon#read 6, iclass 36, count 2 2006.285.11:29:33.88#ibcon#end of sib2, iclass 36, count 2 2006.285.11:29:33.88#ibcon#*mode == 0, iclass 36, count 2 2006.285.11:29:33.88#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.11:29:33.88#ibcon#[27=AT05-04\r\n] 2006.285.11:29:33.88#ibcon#*before write, iclass 36, count 2 2006.285.11:29:33.88#ibcon#enter sib2, iclass 36, count 2 2006.285.11:29:33.88#ibcon#flushed, iclass 36, count 2 2006.285.11:29:33.88#ibcon#about to write, iclass 36, count 2 2006.285.11:29:33.88#ibcon#wrote, iclass 36, count 2 2006.285.11:29:33.88#ibcon#about to read 3, iclass 36, count 2 2006.285.11:29:33.91#ibcon#read 3, iclass 36, count 2 2006.285.11:29:33.91#ibcon#about to read 4, iclass 36, count 2 2006.285.11:29:33.91#ibcon#read 4, iclass 36, count 2 2006.285.11:29:33.91#ibcon#about to read 5, iclass 36, count 2 2006.285.11:29:33.91#ibcon#read 5, iclass 36, count 2 2006.285.11:29:33.91#ibcon#about to read 6, iclass 36, count 2 2006.285.11:29:33.91#ibcon#read 6, iclass 36, count 2 2006.285.11:29:33.91#ibcon#end of sib2, iclass 36, count 2 2006.285.11:29:33.91#ibcon#*after write, iclass 36, count 2 2006.285.11:29:33.91#ibcon#*before return 0, iclass 36, count 2 2006.285.11:29:33.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:29:33.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:29:33.91#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.11:29:33.91#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:33.91#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:29:34.03#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:29:34.03#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:29:34.03#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:29:34.03#ibcon#first serial, iclass 36, count 0 2006.285.11:29:34.03#ibcon#enter sib2, iclass 36, count 0 2006.285.11:29:34.03#ibcon#flushed, iclass 36, count 0 2006.285.11:29:34.03#ibcon#about to write, iclass 36, count 0 2006.285.11:29:34.03#ibcon#wrote, iclass 36, count 0 2006.285.11:29:34.03#ibcon#about to read 3, iclass 36, count 0 2006.285.11:29:34.05#ibcon#read 3, iclass 36, count 0 2006.285.11:29:34.05#ibcon#about to read 4, iclass 36, count 0 2006.285.11:29:34.05#ibcon#read 4, iclass 36, count 0 2006.285.11:29:34.05#ibcon#about to read 5, iclass 36, count 0 2006.285.11:29:34.05#ibcon#read 5, iclass 36, count 0 2006.285.11:29:34.05#ibcon#about to read 6, iclass 36, count 0 2006.285.11:29:34.05#ibcon#read 6, iclass 36, count 0 2006.285.11:29:34.05#ibcon#end of sib2, iclass 36, count 0 2006.285.11:29:34.05#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:29:34.05#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:29:34.05#ibcon#[27=USB\r\n] 2006.285.11:29:34.05#ibcon#*before write, iclass 36, count 0 2006.285.11:29:34.05#ibcon#enter sib2, iclass 36, count 0 2006.285.11:29:34.05#ibcon#flushed, iclass 36, count 0 2006.285.11:29:34.05#ibcon#about to write, iclass 36, count 0 2006.285.11:29:34.05#ibcon#wrote, iclass 36, count 0 2006.285.11:29:34.05#ibcon#about to read 3, iclass 36, count 0 2006.285.11:29:34.08#ibcon#read 3, iclass 36, count 0 2006.285.11:29:34.08#ibcon#about to read 4, iclass 36, count 0 2006.285.11:29:34.08#ibcon#read 4, iclass 36, count 0 2006.285.11:29:34.08#ibcon#about to read 5, iclass 36, count 0 2006.285.11:29:34.08#ibcon#read 5, iclass 36, count 0 2006.285.11:29:34.08#ibcon#about to read 6, iclass 36, count 0 2006.285.11:29:34.08#ibcon#read 6, iclass 36, count 0 2006.285.11:29:34.08#ibcon#end of sib2, iclass 36, count 0 2006.285.11:29:34.08#ibcon#*after write, iclass 36, count 0 2006.285.11:29:34.08#ibcon#*before return 0, iclass 36, count 0 2006.285.11:29:34.08#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:29:34.08#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:29:34.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:29:34.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:29:34.08$vck44/vblo=6,719.99 2006.285.11:29:34.08#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.11:29:34.08#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.11:29:34.08#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:34.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:29:34.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:29:34.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:29:34.08#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:29:34.08#ibcon#first serial, iclass 38, count 0 2006.285.11:29:34.08#ibcon#enter sib2, iclass 38, count 0 2006.285.11:29:34.08#ibcon#flushed, iclass 38, count 0 2006.285.11:29:34.08#ibcon#about to write, iclass 38, count 0 2006.285.11:29:34.08#ibcon#wrote, iclass 38, count 0 2006.285.11:29:34.08#ibcon#about to read 3, iclass 38, count 0 2006.285.11:29:34.10#ibcon#read 3, iclass 38, count 0 2006.285.11:29:34.10#ibcon#about to read 4, iclass 38, count 0 2006.285.11:29:34.10#ibcon#read 4, iclass 38, count 0 2006.285.11:29:34.10#ibcon#about to read 5, iclass 38, count 0 2006.285.11:29:34.10#ibcon#read 5, iclass 38, count 0 2006.285.11:29:34.10#ibcon#about to read 6, iclass 38, count 0 2006.285.11:29:34.10#ibcon#read 6, iclass 38, count 0 2006.285.11:29:34.10#ibcon#end of sib2, iclass 38, count 0 2006.285.11:29:34.10#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:29:34.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:29:34.10#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:29:34.10#ibcon#*before write, iclass 38, count 0 2006.285.11:29:34.10#ibcon#enter sib2, iclass 38, count 0 2006.285.11:29:34.10#ibcon#flushed, iclass 38, count 0 2006.285.11:29:34.10#ibcon#about to write, iclass 38, count 0 2006.285.11:29:34.10#ibcon#wrote, iclass 38, count 0 2006.285.11:29:34.10#ibcon#about to read 3, iclass 38, count 0 2006.285.11:29:34.14#ibcon#read 3, iclass 38, count 0 2006.285.11:29:34.14#ibcon#about to read 4, iclass 38, count 0 2006.285.11:29:34.14#ibcon#read 4, iclass 38, count 0 2006.285.11:29:34.14#ibcon#about to read 5, iclass 38, count 0 2006.285.11:29:34.14#ibcon#read 5, iclass 38, count 0 2006.285.11:29:34.14#ibcon#about to read 6, iclass 38, count 0 2006.285.11:29:34.14#ibcon#read 6, iclass 38, count 0 2006.285.11:29:34.14#ibcon#end of sib2, iclass 38, count 0 2006.285.11:29:34.14#ibcon#*after write, iclass 38, count 0 2006.285.11:29:34.14#ibcon#*before return 0, iclass 38, count 0 2006.285.11:29:34.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:29:34.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:29:34.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:29:34.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:29:34.14$vck44/vb=6,3 2006.285.11:29:34.14#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.11:29:34.14#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.11:29:34.14#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:34.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:29:34.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:29:34.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:29:34.20#ibcon#enter wrdev, iclass 40, count 2 2006.285.11:29:34.20#ibcon#first serial, iclass 40, count 2 2006.285.11:29:34.20#ibcon#enter sib2, iclass 40, count 2 2006.285.11:29:34.20#ibcon#flushed, iclass 40, count 2 2006.285.11:29:34.20#ibcon#about to write, iclass 40, count 2 2006.285.11:29:34.20#ibcon#wrote, iclass 40, count 2 2006.285.11:29:34.20#ibcon#about to read 3, iclass 40, count 2 2006.285.11:29:34.22#ibcon#read 3, iclass 40, count 2 2006.285.11:29:34.22#ibcon#about to read 4, iclass 40, count 2 2006.285.11:29:34.22#ibcon#read 4, iclass 40, count 2 2006.285.11:29:34.22#ibcon#about to read 5, iclass 40, count 2 2006.285.11:29:34.22#ibcon#read 5, iclass 40, count 2 2006.285.11:29:34.22#ibcon#about to read 6, iclass 40, count 2 2006.285.11:29:34.22#ibcon#read 6, iclass 40, count 2 2006.285.11:29:34.22#ibcon#end of sib2, iclass 40, count 2 2006.285.11:29:34.22#ibcon#*mode == 0, iclass 40, count 2 2006.285.11:29:34.22#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.11:29:34.22#ibcon#[27=AT06-03\r\n] 2006.285.11:29:34.22#ibcon#*before write, iclass 40, count 2 2006.285.11:29:34.22#ibcon#enter sib2, iclass 40, count 2 2006.285.11:29:34.22#ibcon#flushed, iclass 40, count 2 2006.285.11:29:34.22#ibcon#about to write, iclass 40, count 2 2006.285.11:29:34.22#ibcon#wrote, iclass 40, count 2 2006.285.11:29:34.22#ibcon#about to read 3, iclass 40, count 2 2006.285.11:29:34.25#ibcon#read 3, iclass 40, count 2 2006.285.11:29:34.25#ibcon#about to read 4, iclass 40, count 2 2006.285.11:29:34.25#ibcon#read 4, iclass 40, count 2 2006.285.11:29:34.25#ibcon#about to read 5, iclass 40, count 2 2006.285.11:29:34.25#ibcon#read 5, iclass 40, count 2 2006.285.11:29:34.25#ibcon#about to read 6, iclass 40, count 2 2006.285.11:29:34.25#ibcon#read 6, iclass 40, count 2 2006.285.11:29:34.25#ibcon#end of sib2, iclass 40, count 2 2006.285.11:29:34.25#ibcon#*after write, iclass 40, count 2 2006.285.11:29:34.25#ibcon#*before return 0, iclass 40, count 2 2006.285.11:29:34.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:29:34.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:29:34.25#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.11:29:34.25#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:34.25#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:29:34.37#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:29:34.37#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:29:34.37#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:29:34.37#ibcon#first serial, iclass 40, count 0 2006.285.11:29:34.37#ibcon#enter sib2, iclass 40, count 0 2006.285.11:29:34.37#ibcon#flushed, iclass 40, count 0 2006.285.11:29:34.37#ibcon#about to write, iclass 40, count 0 2006.285.11:29:34.37#ibcon#wrote, iclass 40, count 0 2006.285.11:29:34.37#ibcon#about to read 3, iclass 40, count 0 2006.285.11:29:34.39#ibcon#read 3, iclass 40, count 0 2006.285.11:29:34.39#ibcon#about to read 4, iclass 40, count 0 2006.285.11:29:34.39#ibcon#read 4, iclass 40, count 0 2006.285.11:29:34.39#ibcon#about to read 5, iclass 40, count 0 2006.285.11:29:34.39#ibcon#read 5, iclass 40, count 0 2006.285.11:29:34.39#ibcon#about to read 6, iclass 40, count 0 2006.285.11:29:34.39#ibcon#read 6, iclass 40, count 0 2006.285.11:29:34.39#ibcon#end of sib2, iclass 40, count 0 2006.285.11:29:34.39#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:29:34.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:29:34.39#ibcon#[27=USB\r\n] 2006.285.11:29:34.39#ibcon#*before write, iclass 40, count 0 2006.285.11:29:34.39#ibcon#enter sib2, iclass 40, count 0 2006.285.11:29:34.39#ibcon#flushed, iclass 40, count 0 2006.285.11:29:34.39#ibcon#about to write, iclass 40, count 0 2006.285.11:29:34.39#ibcon#wrote, iclass 40, count 0 2006.285.11:29:34.39#ibcon#about to read 3, iclass 40, count 0 2006.285.11:29:34.42#ibcon#read 3, iclass 40, count 0 2006.285.11:29:34.42#ibcon#about to read 4, iclass 40, count 0 2006.285.11:29:34.42#ibcon#read 4, iclass 40, count 0 2006.285.11:29:34.42#ibcon#about to read 5, iclass 40, count 0 2006.285.11:29:34.42#ibcon#read 5, iclass 40, count 0 2006.285.11:29:34.42#ibcon#about to read 6, iclass 40, count 0 2006.285.11:29:34.42#ibcon#read 6, iclass 40, count 0 2006.285.11:29:34.42#ibcon#end of sib2, iclass 40, count 0 2006.285.11:29:34.42#ibcon#*after write, iclass 40, count 0 2006.285.11:29:34.42#ibcon#*before return 0, iclass 40, count 0 2006.285.11:29:34.42#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:29:34.42#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:29:34.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:29:34.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:29:34.42$vck44/vblo=7,734.99 2006.285.11:29:34.42#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.11:29:34.42#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.11:29:34.42#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:34.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:29:34.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:29:34.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:29:34.42#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:29:34.42#ibcon#first serial, iclass 4, count 0 2006.285.11:29:34.42#ibcon#enter sib2, iclass 4, count 0 2006.285.11:29:34.42#ibcon#flushed, iclass 4, count 0 2006.285.11:29:34.42#ibcon#about to write, iclass 4, count 0 2006.285.11:29:34.42#ibcon#wrote, iclass 4, count 0 2006.285.11:29:34.42#ibcon#about to read 3, iclass 4, count 0 2006.285.11:29:34.44#ibcon#read 3, iclass 4, count 0 2006.285.11:29:34.44#ibcon#about to read 4, iclass 4, count 0 2006.285.11:29:34.44#ibcon#read 4, iclass 4, count 0 2006.285.11:29:34.44#ibcon#about to read 5, iclass 4, count 0 2006.285.11:29:34.44#ibcon#read 5, iclass 4, count 0 2006.285.11:29:34.44#ibcon#about to read 6, iclass 4, count 0 2006.285.11:29:34.44#ibcon#read 6, iclass 4, count 0 2006.285.11:29:34.44#ibcon#end of sib2, iclass 4, count 0 2006.285.11:29:34.44#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:29:34.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:29:34.44#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:29:34.44#ibcon#*before write, iclass 4, count 0 2006.285.11:29:34.44#ibcon#enter sib2, iclass 4, count 0 2006.285.11:29:34.44#ibcon#flushed, iclass 4, count 0 2006.285.11:29:34.44#ibcon#about to write, iclass 4, count 0 2006.285.11:29:34.44#ibcon#wrote, iclass 4, count 0 2006.285.11:29:34.44#ibcon#about to read 3, iclass 4, count 0 2006.285.11:29:34.48#ibcon#read 3, iclass 4, count 0 2006.285.11:29:34.48#ibcon#about to read 4, iclass 4, count 0 2006.285.11:29:34.48#ibcon#read 4, iclass 4, count 0 2006.285.11:29:34.48#ibcon#about to read 5, iclass 4, count 0 2006.285.11:29:34.48#ibcon#read 5, iclass 4, count 0 2006.285.11:29:34.48#ibcon#about to read 6, iclass 4, count 0 2006.285.11:29:34.48#ibcon#read 6, iclass 4, count 0 2006.285.11:29:34.48#ibcon#end of sib2, iclass 4, count 0 2006.285.11:29:34.48#ibcon#*after write, iclass 4, count 0 2006.285.11:29:34.48#ibcon#*before return 0, iclass 4, count 0 2006.285.11:29:34.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:29:34.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:29:34.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:29:34.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:29:34.48$vck44/vb=7,4 2006.285.11:29:34.48#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.11:29:34.48#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.11:29:34.48#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:34.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:29:34.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:29:34.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:29:34.54#ibcon#enter wrdev, iclass 6, count 2 2006.285.11:29:34.54#ibcon#first serial, iclass 6, count 2 2006.285.11:29:34.54#ibcon#enter sib2, iclass 6, count 2 2006.285.11:29:34.54#ibcon#flushed, iclass 6, count 2 2006.285.11:29:34.54#ibcon#about to write, iclass 6, count 2 2006.285.11:29:34.54#ibcon#wrote, iclass 6, count 2 2006.285.11:29:34.54#ibcon#about to read 3, iclass 6, count 2 2006.285.11:29:34.56#ibcon#read 3, iclass 6, count 2 2006.285.11:29:34.56#ibcon#about to read 4, iclass 6, count 2 2006.285.11:29:34.56#ibcon#read 4, iclass 6, count 2 2006.285.11:29:34.56#ibcon#about to read 5, iclass 6, count 2 2006.285.11:29:34.56#ibcon#read 5, iclass 6, count 2 2006.285.11:29:34.56#ibcon#about to read 6, iclass 6, count 2 2006.285.11:29:34.56#ibcon#read 6, iclass 6, count 2 2006.285.11:29:34.56#ibcon#end of sib2, iclass 6, count 2 2006.285.11:29:34.56#ibcon#*mode == 0, iclass 6, count 2 2006.285.11:29:34.56#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.11:29:34.56#ibcon#[27=AT07-04\r\n] 2006.285.11:29:34.56#ibcon#*before write, iclass 6, count 2 2006.285.11:29:34.56#ibcon#enter sib2, iclass 6, count 2 2006.285.11:29:34.56#ibcon#flushed, iclass 6, count 2 2006.285.11:29:34.56#ibcon#about to write, iclass 6, count 2 2006.285.11:29:34.56#ibcon#wrote, iclass 6, count 2 2006.285.11:29:34.56#ibcon#about to read 3, iclass 6, count 2 2006.285.11:29:34.59#ibcon#read 3, iclass 6, count 2 2006.285.11:29:34.59#ibcon#about to read 4, iclass 6, count 2 2006.285.11:29:34.59#ibcon#read 4, iclass 6, count 2 2006.285.11:29:34.59#ibcon#about to read 5, iclass 6, count 2 2006.285.11:29:34.59#ibcon#read 5, iclass 6, count 2 2006.285.11:29:34.59#ibcon#about to read 6, iclass 6, count 2 2006.285.11:29:34.59#ibcon#read 6, iclass 6, count 2 2006.285.11:29:34.59#ibcon#end of sib2, iclass 6, count 2 2006.285.11:29:34.59#ibcon#*after write, iclass 6, count 2 2006.285.11:29:34.59#ibcon#*before return 0, iclass 6, count 2 2006.285.11:29:34.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:29:34.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:29:34.59#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.11:29:34.59#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:34.59#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:29:34.71#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:29:34.71#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:29:34.71#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:29:34.71#ibcon#first serial, iclass 6, count 0 2006.285.11:29:34.71#ibcon#enter sib2, iclass 6, count 0 2006.285.11:29:34.71#ibcon#flushed, iclass 6, count 0 2006.285.11:29:34.71#ibcon#about to write, iclass 6, count 0 2006.285.11:29:34.71#ibcon#wrote, iclass 6, count 0 2006.285.11:29:34.71#ibcon#about to read 3, iclass 6, count 0 2006.285.11:29:34.73#ibcon#read 3, iclass 6, count 0 2006.285.11:29:34.73#ibcon#about to read 4, iclass 6, count 0 2006.285.11:29:34.73#ibcon#read 4, iclass 6, count 0 2006.285.11:29:34.73#ibcon#about to read 5, iclass 6, count 0 2006.285.11:29:34.73#ibcon#read 5, iclass 6, count 0 2006.285.11:29:34.73#ibcon#about to read 6, iclass 6, count 0 2006.285.11:29:34.73#ibcon#read 6, iclass 6, count 0 2006.285.11:29:34.73#ibcon#end of sib2, iclass 6, count 0 2006.285.11:29:34.73#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:29:34.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:29:34.73#ibcon#[27=USB\r\n] 2006.285.11:29:34.73#ibcon#*before write, iclass 6, count 0 2006.285.11:29:34.73#ibcon#enter sib2, iclass 6, count 0 2006.285.11:29:34.73#ibcon#flushed, iclass 6, count 0 2006.285.11:29:34.73#ibcon#about to write, iclass 6, count 0 2006.285.11:29:34.73#ibcon#wrote, iclass 6, count 0 2006.285.11:29:34.73#ibcon#about to read 3, iclass 6, count 0 2006.285.11:29:34.76#ibcon#read 3, iclass 6, count 0 2006.285.11:29:34.76#ibcon#about to read 4, iclass 6, count 0 2006.285.11:29:34.76#ibcon#read 4, iclass 6, count 0 2006.285.11:29:34.76#ibcon#about to read 5, iclass 6, count 0 2006.285.11:29:34.76#ibcon#read 5, iclass 6, count 0 2006.285.11:29:34.76#ibcon#about to read 6, iclass 6, count 0 2006.285.11:29:34.76#ibcon#read 6, iclass 6, count 0 2006.285.11:29:34.76#ibcon#end of sib2, iclass 6, count 0 2006.285.11:29:34.76#ibcon#*after write, iclass 6, count 0 2006.285.11:29:34.76#ibcon#*before return 0, iclass 6, count 0 2006.285.11:29:34.76#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:29:34.76#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:29:34.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:29:34.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:29:34.76$vck44/vblo=8,744.99 2006.285.11:29:34.76#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.11:29:34.76#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.11:29:34.76#ibcon#ireg 17 cls_cnt 0 2006.285.11:29:34.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:29:34.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:29:34.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:29:34.76#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:29:34.76#ibcon#first serial, iclass 10, count 0 2006.285.11:29:34.76#ibcon#enter sib2, iclass 10, count 0 2006.285.11:29:34.76#ibcon#flushed, iclass 10, count 0 2006.285.11:29:34.76#ibcon#about to write, iclass 10, count 0 2006.285.11:29:34.76#ibcon#wrote, iclass 10, count 0 2006.285.11:29:34.76#ibcon#about to read 3, iclass 10, count 0 2006.285.11:29:34.78#ibcon#read 3, iclass 10, count 0 2006.285.11:29:34.78#ibcon#about to read 4, iclass 10, count 0 2006.285.11:29:34.78#ibcon#read 4, iclass 10, count 0 2006.285.11:29:34.78#ibcon#about to read 5, iclass 10, count 0 2006.285.11:29:34.78#ibcon#read 5, iclass 10, count 0 2006.285.11:29:34.78#ibcon#about to read 6, iclass 10, count 0 2006.285.11:29:34.78#ibcon#read 6, iclass 10, count 0 2006.285.11:29:34.78#ibcon#end of sib2, iclass 10, count 0 2006.285.11:29:34.78#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:29:34.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:29:34.78#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:29:34.78#ibcon#*before write, iclass 10, count 0 2006.285.11:29:34.78#ibcon#enter sib2, iclass 10, count 0 2006.285.11:29:34.78#ibcon#flushed, iclass 10, count 0 2006.285.11:29:34.78#ibcon#about to write, iclass 10, count 0 2006.285.11:29:34.78#ibcon#wrote, iclass 10, count 0 2006.285.11:29:34.78#ibcon#about to read 3, iclass 10, count 0 2006.285.11:29:34.82#ibcon#read 3, iclass 10, count 0 2006.285.11:29:34.82#ibcon#about to read 4, iclass 10, count 0 2006.285.11:29:34.82#ibcon#read 4, iclass 10, count 0 2006.285.11:29:34.82#ibcon#about to read 5, iclass 10, count 0 2006.285.11:29:34.82#ibcon#read 5, iclass 10, count 0 2006.285.11:29:34.82#ibcon#about to read 6, iclass 10, count 0 2006.285.11:29:34.82#ibcon#read 6, iclass 10, count 0 2006.285.11:29:34.82#ibcon#end of sib2, iclass 10, count 0 2006.285.11:29:34.82#ibcon#*after write, iclass 10, count 0 2006.285.11:29:34.82#ibcon#*before return 0, iclass 10, count 0 2006.285.11:29:34.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:29:34.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:29:34.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:29:34.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:29:34.82$vck44/vb=8,4 2006.285.11:29:34.82#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.11:29:34.82#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.11:29:34.82#ibcon#ireg 11 cls_cnt 2 2006.285.11:29:34.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:29:34.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:29:34.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:29:34.88#ibcon#enter wrdev, iclass 12, count 2 2006.285.11:29:34.88#ibcon#first serial, iclass 12, count 2 2006.285.11:29:34.88#ibcon#enter sib2, iclass 12, count 2 2006.285.11:29:34.88#ibcon#flushed, iclass 12, count 2 2006.285.11:29:34.88#ibcon#about to write, iclass 12, count 2 2006.285.11:29:34.88#ibcon#wrote, iclass 12, count 2 2006.285.11:29:34.88#ibcon#about to read 3, iclass 12, count 2 2006.285.11:29:34.90#ibcon#read 3, iclass 12, count 2 2006.285.11:29:34.90#ibcon#about to read 4, iclass 12, count 2 2006.285.11:29:34.90#ibcon#read 4, iclass 12, count 2 2006.285.11:29:34.90#ibcon#about to read 5, iclass 12, count 2 2006.285.11:29:34.90#ibcon#read 5, iclass 12, count 2 2006.285.11:29:34.90#ibcon#about to read 6, iclass 12, count 2 2006.285.11:29:34.90#ibcon#read 6, iclass 12, count 2 2006.285.11:29:34.90#ibcon#end of sib2, iclass 12, count 2 2006.285.11:29:34.90#ibcon#*mode == 0, iclass 12, count 2 2006.285.11:29:34.90#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.11:29:34.90#ibcon#[27=AT08-04\r\n] 2006.285.11:29:34.90#ibcon#*before write, iclass 12, count 2 2006.285.11:29:34.90#ibcon#enter sib2, iclass 12, count 2 2006.285.11:29:34.90#ibcon#flushed, iclass 12, count 2 2006.285.11:29:34.90#ibcon#about to write, iclass 12, count 2 2006.285.11:29:34.90#ibcon#wrote, iclass 12, count 2 2006.285.11:29:34.90#ibcon#about to read 3, iclass 12, count 2 2006.285.11:29:34.93#ibcon#read 3, iclass 12, count 2 2006.285.11:29:34.93#ibcon#about to read 4, iclass 12, count 2 2006.285.11:29:34.93#ibcon#read 4, iclass 12, count 2 2006.285.11:29:34.93#ibcon#about to read 5, iclass 12, count 2 2006.285.11:29:34.93#ibcon#read 5, iclass 12, count 2 2006.285.11:29:34.93#ibcon#about to read 6, iclass 12, count 2 2006.285.11:29:34.93#ibcon#read 6, iclass 12, count 2 2006.285.11:29:34.93#ibcon#end of sib2, iclass 12, count 2 2006.285.11:29:34.93#ibcon#*after write, iclass 12, count 2 2006.285.11:29:34.93#ibcon#*before return 0, iclass 12, count 2 2006.285.11:29:34.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:29:34.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:29:34.93#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.11:29:34.93#ibcon#ireg 7 cls_cnt 0 2006.285.11:29:34.93#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:29:35.05#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:29:35.05#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:29:35.05#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:29:35.05#ibcon#first serial, iclass 12, count 0 2006.285.11:29:35.05#ibcon#enter sib2, iclass 12, count 0 2006.285.11:29:35.05#ibcon#flushed, iclass 12, count 0 2006.285.11:29:35.05#ibcon#about to write, iclass 12, count 0 2006.285.11:29:35.05#ibcon#wrote, iclass 12, count 0 2006.285.11:29:35.05#ibcon#about to read 3, iclass 12, count 0 2006.285.11:29:35.07#ibcon#read 3, iclass 12, count 0 2006.285.11:29:35.07#ibcon#about to read 4, iclass 12, count 0 2006.285.11:29:35.07#ibcon#read 4, iclass 12, count 0 2006.285.11:29:35.07#ibcon#about to read 5, iclass 12, count 0 2006.285.11:29:35.07#ibcon#read 5, iclass 12, count 0 2006.285.11:29:35.07#ibcon#about to read 6, iclass 12, count 0 2006.285.11:29:35.07#ibcon#read 6, iclass 12, count 0 2006.285.11:29:35.07#ibcon#end of sib2, iclass 12, count 0 2006.285.11:29:35.07#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:29:35.07#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:29:35.07#ibcon#[27=USB\r\n] 2006.285.11:29:35.07#ibcon#*before write, iclass 12, count 0 2006.285.11:29:35.07#ibcon#enter sib2, iclass 12, count 0 2006.285.11:29:35.07#ibcon#flushed, iclass 12, count 0 2006.285.11:29:35.07#ibcon#about to write, iclass 12, count 0 2006.285.11:29:35.07#ibcon#wrote, iclass 12, count 0 2006.285.11:29:35.07#ibcon#about to read 3, iclass 12, count 0 2006.285.11:29:35.10#ibcon#read 3, iclass 12, count 0 2006.285.11:29:35.10#ibcon#about to read 4, iclass 12, count 0 2006.285.11:29:35.10#ibcon#read 4, iclass 12, count 0 2006.285.11:29:35.10#ibcon#about to read 5, iclass 12, count 0 2006.285.11:29:35.10#ibcon#read 5, iclass 12, count 0 2006.285.11:29:35.10#ibcon#about to read 6, iclass 12, count 0 2006.285.11:29:35.10#ibcon#read 6, iclass 12, count 0 2006.285.11:29:35.10#ibcon#end of sib2, iclass 12, count 0 2006.285.11:29:35.10#ibcon#*after write, iclass 12, count 0 2006.285.11:29:35.10#ibcon#*before return 0, iclass 12, count 0 2006.285.11:29:35.10#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:29:35.10#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:29:35.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:29:35.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:29:35.10$vck44/vabw=wide 2006.285.11:29:35.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.11:29:35.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.11:29:35.10#ibcon#ireg 8 cls_cnt 0 2006.285.11:29:35.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:29:35.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:29:35.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:29:35.10#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:29:35.10#ibcon#first serial, iclass 14, count 0 2006.285.11:29:35.10#ibcon#enter sib2, iclass 14, count 0 2006.285.11:29:35.10#ibcon#flushed, iclass 14, count 0 2006.285.11:29:35.10#ibcon#about to write, iclass 14, count 0 2006.285.11:29:35.10#ibcon#wrote, iclass 14, count 0 2006.285.11:29:35.10#ibcon#about to read 3, iclass 14, count 0 2006.285.11:29:35.12#ibcon#read 3, iclass 14, count 0 2006.285.11:29:35.12#ibcon#about to read 4, iclass 14, count 0 2006.285.11:29:35.12#ibcon#read 4, iclass 14, count 0 2006.285.11:29:35.12#ibcon#about to read 5, iclass 14, count 0 2006.285.11:29:35.12#ibcon#read 5, iclass 14, count 0 2006.285.11:29:35.12#ibcon#about to read 6, iclass 14, count 0 2006.285.11:29:35.12#ibcon#read 6, iclass 14, count 0 2006.285.11:29:35.12#ibcon#end of sib2, iclass 14, count 0 2006.285.11:29:35.12#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:29:35.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:29:35.12#ibcon#[25=BW32\r\n] 2006.285.11:29:35.12#ibcon#*before write, iclass 14, count 0 2006.285.11:29:35.12#ibcon#enter sib2, iclass 14, count 0 2006.285.11:29:35.12#ibcon#flushed, iclass 14, count 0 2006.285.11:29:35.12#ibcon#about to write, iclass 14, count 0 2006.285.11:29:35.12#ibcon#wrote, iclass 14, count 0 2006.285.11:29:35.12#ibcon#about to read 3, iclass 14, count 0 2006.285.11:29:35.15#ibcon#read 3, iclass 14, count 0 2006.285.11:29:35.15#ibcon#about to read 4, iclass 14, count 0 2006.285.11:29:35.15#ibcon#read 4, iclass 14, count 0 2006.285.11:29:35.15#ibcon#about to read 5, iclass 14, count 0 2006.285.11:29:35.15#ibcon#read 5, iclass 14, count 0 2006.285.11:29:35.15#ibcon#about to read 6, iclass 14, count 0 2006.285.11:29:35.15#ibcon#read 6, iclass 14, count 0 2006.285.11:29:35.15#ibcon#end of sib2, iclass 14, count 0 2006.285.11:29:35.15#ibcon#*after write, iclass 14, count 0 2006.285.11:29:35.15#ibcon#*before return 0, iclass 14, count 0 2006.285.11:29:35.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:29:35.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:29:35.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:29:35.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:29:35.15$vck44/vbbw=wide 2006.285.11:29:35.15#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.11:29:35.15#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.11:29:35.15#ibcon#ireg 8 cls_cnt 0 2006.285.11:29:35.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:29:35.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:29:35.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:29:35.22#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:29:35.22#ibcon#first serial, iclass 16, count 0 2006.285.11:29:35.22#ibcon#enter sib2, iclass 16, count 0 2006.285.11:29:35.22#ibcon#flushed, iclass 16, count 0 2006.285.11:29:35.22#ibcon#about to write, iclass 16, count 0 2006.285.11:29:35.22#ibcon#wrote, iclass 16, count 0 2006.285.11:29:35.22#ibcon#about to read 3, iclass 16, count 0 2006.285.11:29:35.24#ibcon#read 3, iclass 16, count 0 2006.285.11:29:35.24#ibcon#about to read 4, iclass 16, count 0 2006.285.11:29:35.24#ibcon#read 4, iclass 16, count 0 2006.285.11:29:35.24#ibcon#about to read 5, iclass 16, count 0 2006.285.11:29:35.24#ibcon#read 5, iclass 16, count 0 2006.285.11:29:35.24#ibcon#about to read 6, iclass 16, count 0 2006.285.11:29:35.24#ibcon#read 6, iclass 16, count 0 2006.285.11:29:35.24#ibcon#end of sib2, iclass 16, count 0 2006.285.11:29:35.24#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:29:35.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:29:35.24#ibcon#[27=BW32\r\n] 2006.285.11:29:35.24#ibcon#*before write, iclass 16, count 0 2006.285.11:29:35.24#ibcon#enter sib2, iclass 16, count 0 2006.285.11:29:35.24#ibcon#flushed, iclass 16, count 0 2006.285.11:29:35.24#ibcon#about to write, iclass 16, count 0 2006.285.11:29:35.24#ibcon#wrote, iclass 16, count 0 2006.285.11:29:35.24#ibcon#about to read 3, iclass 16, count 0 2006.285.11:29:35.27#ibcon#read 3, iclass 16, count 0 2006.285.11:29:35.27#ibcon#about to read 4, iclass 16, count 0 2006.285.11:29:35.27#ibcon#read 4, iclass 16, count 0 2006.285.11:29:35.27#ibcon#about to read 5, iclass 16, count 0 2006.285.11:29:35.27#ibcon#read 5, iclass 16, count 0 2006.285.11:29:35.27#ibcon#about to read 6, iclass 16, count 0 2006.285.11:29:35.27#ibcon#read 6, iclass 16, count 0 2006.285.11:29:35.27#ibcon#end of sib2, iclass 16, count 0 2006.285.11:29:35.27#ibcon#*after write, iclass 16, count 0 2006.285.11:29:35.27#ibcon#*before return 0, iclass 16, count 0 2006.285.11:29:35.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:29:35.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:29:35.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:29:35.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:29:35.27$setupk4/ifdk4 2006.285.11:29:35.27$ifdk4/lo= 2006.285.11:29:35.27$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:29:35.27$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:29:35.27$ifdk4/patch= 2006.285.11:29:35.27$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:29:35.27$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:29:35.27$setupk4/!*+20s 2006.285.11:29:39.54#abcon#<5=/06 0.9 1.6 19.29 941015.3\r\n> 2006.285.11:29:39.56#abcon#{5=INTERFACE CLEAR} 2006.285.11:29:39.62#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:29:41.13#trakl#Source acquired 2006.285.11:29:43.13#flagr#flagr/antenna,acquired 2006.285.11:29:49.71#abcon#<5=/06 0.9 1.6 19.28 941015.2\r\n> 2006.285.11:29:49.73#abcon#{5=INTERFACE CLEAR} 2006.285.11:29:49.78$setupk4/"tpicd 2006.285.11:29:49.78$setupk4/echo=off 2006.285.11:29:49.78$setupk4/xlog=off 2006.285.11:29:49.78:!2006.285.11:29:57 2006.285.11:29:49.79#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:29:57.00:preob 2006.285.11:29:57.13/onsource/TRACKING 2006.285.11:29:57.13:!2006.285.11:30:07 2006.285.11:30:07.00:"tape 2006.285.11:30:07.00:"st=record 2006.285.11:30:07.00:data_valid=on 2006.285.11:30:07.00:midob 2006.285.11:30:07.13/onsource/TRACKING 2006.285.11:30:07.13/wx/19.28,1015.3,94 2006.285.11:30:07.23/cable/+6.4913E-03 2006.285.11:30:08.32/va/01,07,usb,yes,32,35 2006.285.11:30:08.32/va/02,06,usb,yes,32,33 2006.285.11:30:08.32/va/03,07,usb,yes,32,33 2006.285.11:30:08.32/va/04,06,usb,yes,33,34 2006.285.11:30:08.32/va/05,03,usb,yes,33,33 2006.285.11:30:08.32/va/06,04,usb,yes,29,29 2006.285.11:30:08.32/va/07,04,usb,yes,30,30 2006.285.11:30:08.32/va/08,03,usb,yes,31,37 2006.285.11:30:08.55/valo/01,524.99,yes,locked 2006.285.11:30:08.55/valo/02,534.99,yes,locked 2006.285.11:30:08.55/valo/03,564.99,yes,locked 2006.285.11:30:08.55/valo/04,624.99,yes,locked 2006.285.11:30:08.55/valo/05,734.99,yes,locked 2006.285.11:30:08.55/valo/06,814.99,yes,locked 2006.285.11:30:08.55/valo/07,864.99,yes,locked 2006.285.11:30:08.55/valo/08,884.99,yes,locked 2006.285.11:30:09.64/vb/01,04,usb,yes,30,28 2006.285.11:30:09.64/vb/02,05,usb,yes,28,28 2006.285.11:30:09.64/vb/03,04,usb,yes,29,32 2006.285.11:30:09.64/vb/04,05,usb,yes,30,29 2006.285.11:30:09.64/vb/05,04,usb,yes,26,29 2006.285.11:30:09.64/vb/06,03,usb,yes,38,34 2006.285.11:30:09.64/vb/07,04,usb,yes,30,30 2006.285.11:30:09.64/vb/08,04,usb,yes,28,31 2006.285.11:30:09.87/vblo/01,629.99,yes,locked 2006.285.11:30:09.87/vblo/02,634.99,yes,locked 2006.285.11:30:09.87/vblo/03,649.99,yes,locked 2006.285.11:30:09.87/vblo/04,679.99,yes,locked 2006.285.11:30:09.87/vblo/05,709.99,yes,locked 2006.285.11:30:09.87/vblo/06,719.99,yes,locked 2006.285.11:30:09.87/vblo/07,734.99,yes,locked 2006.285.11:30:09.87/vblo/08,744.99,yes,locked 2006.285.11:30:10.02/vabw/8 2006.285.11:30:10.17/vbbw/8 2006.285.11:30:10.32/xfe/off,on,12.2 2006.285.11:30:10.71/ifatt/23,28,28,28 2006.285.11:30:11.07/fmout-gps/S +2.70E-07 2006.285.11:30:11.09:!2006.285.11:34:07 2006.285.11:34:07.01:data_valid=off 2006.285.11:34:07.01:"et 2006.285.11:34:07.01:!+3s 2006.285.11:34:10.02:"tape 2006.285.11:34:10.02:postob 2006.285.11:34:10.18/cable/+6.4925E-03 2006.285.11:34:10.18/wx/19.21,1015.3,94 2006.285.11:34:11.08/fmout-gps/S +2.67E-07 2006.285.11:34:11.08:scan_name=285-1135,jd0610,110 2006.285.11:34:11.08:source=0552+398,055530.81,394849.2,2000.0,cw 2006.285.11:34:11.14#flagr#flagr/antenna,new-source 2006.285.11:34:12.14:checkk5 2006.285.11:34:12.73/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:34:13.17/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:34:13.56/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:34:13.96/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:34:14.33/chk_obsdata//k5ts1/T2851130??a.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.11:34:14.73/chk_obsdata//k5ts2/T2851130??b.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.11:34:15.14/chk_obsdata//k5ts3/T2851130??c.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.11:34:15.58/chk_obsdata//k5ts4/T2851130??d.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.11:34:16.42/k5log//k5ts1_log_newline 2006.285.11:34:17.18/k5log//k5ts2_log_newline 2006.285.11:34:17.87/k5log//k5ts3_log_newline 2006.285.11:34:18.70/k5log//k5ts4_log_newline 2006.285.11:34:18.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:34:18.72:setupk4=1 2006.285.11:34:18.72$setupk4/echo=on 2006.285.11:34:18.72$setupk4/pcalon 2006.285.11:34:18.72$pcalon/"no phase cal control is implemented here 2006.285.11:34:18.72$setupk4/"tpicd=stop 2006.285.11:34:18.72$setupk4/"rec=synch_on 2006.285.11:34:18.72$setupk4/"rec_mode=128 2006.285.11:34:18.72$setupk4/!* 2006.285.11:34:18.72$setupk4/recpk4 2006.285.11:34:18.72$recpk4/recpatch= 2006.285.11:34:18.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:34:18.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:34:18.73$setupk4/vck44 2006.285.11:34:18.73$vck44/valo=1,524.99 2006.285.11:34:18.73#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.11:34:18.73#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.11:34:18.73#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:18.73#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:34:18.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:34:18.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:34:18.73#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:34:18.73#ibcon#first serial, iclass 25, count 0 2006.285.11:34:18.73#ibcon#enter sib2, iclass 25, count 0 2006.285.11:34:18.73#ibcon#flushed, iclass 25, count 0 2006.285.11:34:18.73#ibcon#about to write, iclass 25, count 0 2006.285.11:34:18.73#ibcon#wrote, iclass 25, count 0 2006.285.11:34:18.73#ibcon#about to read 3, iclass 25, count 0 2006.285.11:34:18.75#ibcon#read 3, iclass 25, count 0 2006.285.11:34:18.75#ibcon#about to read 4, iclass 25, count 0 2006.285.11:34:18.75#ibcon#read 4, iclass 25, count 0 2006.285.11:34:18.75#ibcon#about to read 5, iclass 25, count 0 2006.285.11:34:18.75#ibcon#read 5, iclass 25, count 0 2006.285.11:34:18.75#ibcon#about to read 6, iclass 25, count 0 2006.285.11:34:18.75#ibcon#read 6, iclass 25, count 0 2006.285.11:34:18.75#ibcon#end of sib2, iclass 25, count 0 2006.285.11:34:18.75#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:34:18.75#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:34:18.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:34:18.75#ibcon#*before write, iclass 25, count 0 2006.285.11:34:18.75#ibcon#enter sib2, iclass 25, count 0 2006.285.11:34:18.75#ibcon#flushed, iclass 25, count 0 2006.285.11:34:18.75#ibcon#about to write, iclass 25, count 0 2006.285.11:34:18.75#ibcon#wrote, iclass 25, count 0 2006.285.11:34:18.75#ibcon#about to read 3, iclass 25, count 0 2006.285.11:34:18.80#ibcon#read 3, iclass 25, count 0 2006.285.11:34:18.80#ibcon#about to read 4, iclass 25, count 0 2006.285.11:34:18.80#ibcon#read 4, iclass 25, count 0 2006.285.11:34:18.80#ibcon#about to read 5, iclass 25, count 0 2006.285.11:34:18.80#ibcon#read 5, iclass 25, count 0 2006.285.11:34:18.80#ibcon#about to read 6, iclass 25, count 0 2006.285.11:34:18.80#ibcon#read 6, iclass 25, count 0 2006.285.11:34:18.80#ibcon#end of sib2, iclass 25, count 0 2006.285.11:34:18.80#ibcon#*after write, iclass 25, count 0 2006.285.11:34:18.80#ibcon#*before return 0, iclass 25, count 0 2006.285.11:34:18.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:34:18.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:34:18.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:34:18.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:34:18.80$vck44/va=1,7 2006.285.11:34:18.80#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.11:34:18.80#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.11:34:18.80#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:18.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:34:18.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:34:18.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:34:18.80#ibcon#enter wrdev, iclass 27, count 2 2006.285.11:34:18.80#ibcon#first serial, iclass 27, count 2 2006.285.11:34:18.80#ibcon#enter sib2, iclass 27, count 2 2006.285.11:34:18.80#ibcon#flushed, iclass 27, count 2 2006.285.11:34:18.80#ibcon#about to write, iclass 27, count 2 2006.285.11:34:18.80#ibcon#wrote, iclass 27, count 2 2006.285.11:34:18.80#ibcon#about to read 3, iclass 27, count 2 2006.285.11:34:18.82#ibcon#read 3, iclass 27, count 2 2006.285.11:34:18.82#ibcon#about to read 4, iclass 27, count 2 2006.285.11:34:18.82#ibcon#read 4, iclass 27, count 2 2006.285.11:34:18.82#ibcon#about to read 5, iclass 27, count 2 2006.285.11:34:18.82#ibcon#read 5, iclass 27, count 2 2006.285.11:34:18.82#ibcon#about to read 6, iclass 27, count 2 2006.285.11:34:18.82#ibcon#read 6, iclass 27, count 2 2006.285.11:34:18.82#ibcon#end of sib2, iclass 27, count 2 2006.285.11:34:18.82#ibcon#*mode == 0, iclass 27, count 2 2006.285.11:34:18.82#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.11:34:18.82#ibcon#[25=AT01-07\r\n] 2006.285.11:34:18.82#ibcon#*before write, iclass 27, count 2 2006.285.11:34:18.82#ibcon#enter sib2, iclass 27, count 2 2006.285.11:34:18.82#ibcon#flushed, iclass 27, count 2 2006.285.11:34:18.82#ibcon#about to write, iclass 27, count 2 2006.285.11:34:18.82#ibcon#wrote, iclass 27, count 2 2006.285.11:34:18.82#ibcon#about to read 3, iclass 27, count 2 2006.285.11:34:18.85#ibcon#read 3, iclass 27, count 2 2006.285.11:34:18.85#ibcon#about to read 4, iclass 27, count 2 2006.285.11:34:18.85#ibcon#read 4, iclass 27, count 2 2006.285.11:34:18.85#ibcon#about to read 5, iclass 27, count 2 2006.285.11:34:18.85#ibcon#read 5, iclass 27, count 2 2006.285.11:34:18.85#ibcon#about to read 6, iclass 27, count 2 2006.285.11:34:18.85#ibcon#read 6, iclass 27, count 2 2006.285.11:34:18.85#ibcon#end of sib2, iclass 27, count 2 2006.285.11:34:18.85#ibcon#*after write, iclass 27, count 2 2006.285.11:34:18.85#ibcon#*before return 0, iclass 27, count 2 2006.285.11:34:18.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:34:18.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:34:18.85#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.11:34:18.85#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:18.85#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:34:18.99#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:34:18.99#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:34:18.99#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:34:18.99#ibcon#first serial, iclass 27, count 0 2006.285.11:34:18.99#ibcon#enter sib2, iclass 27, count 0 2006.285.11:34:18.99#ibcon#flushed, iclass 27, count 0 2006.285.11:34:18.99#ibcon#about to write, iclass 27, count 0 2006.285.11:34:18.99#ibcon#wrote, iclass 27, count 0 2006.285.11:34:18.99#ibcon#about to read 3, iclass 27, count 0 2006.285.11:34:19.01#ibcon#read 3, iclass 27, count 0 2006.285.11:34:19.01#ibcon#about to read 4, iclass 27, count 0 2006.285.11:34:19.01#ibcon#read 4, iclass 27, count 0 2006.285.11:34:19.01#ibcon#about to read 5, iclass 27, count 0 2006.285.11:34:19.01#ibcon#read 5, iclass 27, count 0 2006.285.11:34:19.01#ibcon#about to read 6, iclass 27, count 0 2006.285.11:34:19.01#ibcon#read 6, iclass 27, count 0 2006.285.11:34:19.01#ibcon#end of sib2, iclass 27, count 0 2006.285.11:34:19.01#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:34:19.01#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:34:19.01#ibcon#[25=USB\r\n] 2006.285.11:34:19.01#ibcon#*before write, iclass 27, count 0 2006.285.11:34:19.01#ibcon#enter sib2, iclass 27, count 0 2006.285.11:34:19.01#ibcon#flushed, iclass 27, count 0 2006.285.11:34:19.01#ibcon#about to write, iclass 27, count 0 2006.285.11:34:19.01#ibcon#wrote, iclass 27, count 0 2006.285.11:34:19.01#ibcon#about to read 3, iclass 27, count 0 2006.285.11:34:19.04#ibcon#read 3, iclass 27, count 0 2006.285.11:34:19.04#ibcon#about to read 4, iclass 27, count 0 2006.285.11:34:19.04#ibcon#read 4, iclass 27, count 0 2006.285.11:34:19.04#ibcon#about to read 5, iclass 27, count 0 2006.285.11:34:19.04#ibcon#read 5, iclass 27, count 0 2006.285.11:34:19.04#ibcon#about to read 6, iclass 27, count 0 2006.285.11:34:19.04#ibcon#read 6, iclass 27, count 0 2006.285.11:34:19.04#ibcon#end of sib2, iclass 27, count 0 2006.285.11:34:19.04#ibcon#*after write, iclass 27, count 0 2006.285.11:34:19.04#ibcon#*before return 0, iclass 27, count 0 2006.285.11:34:19.04#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:34:19.04#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:34:19.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:34:19.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:34:19.04$vck44/valo=2,534.99 2006.285.11:34:19.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.11:34:19.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.11:34:19.04#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:19.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:34:19.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:34:19.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:34:19.04#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:34:19.04#ibcon#first serial, iclass 29, count 0 2006.285.11:34:19.04#ibcon#enter sib2, iclass 29, count 0 2006.285.11:34:19.04#ibcon#flushed, iclass 29, count 0 2006.285.11:34:19.04#ibcon#about to write, iclass 29, count 0 2006.285.11:34:19.04#ibcon#wrote, iclass 29, count 0 2006.285.11:34:19.04#ibcon#about to read 3, iclass 29, count 0 2006.285.11:34:19.06#ibcon#read 3, iclass 29, count 0 2006.285.11:34:19.06#ibcon#about to read 4, iclass 29, count 0 2006.285.11:34:19.06#ibcon#read 4, iclass 29, count 0 2006.285.11:34:19.06#ibcon#about to read 5, iclass 29, count 0 2006.285.11:34:19.06#ibcon#read 5, iclass 29, count 0 2006.285.11:34:19.06#ibcon#about to read 6, iclass 29, count 0 2006.285.11:34:19.06#ibcon#read 6, iclass 29, count 0 2006.285.11:34:19.06#ibcon#end of sib2, iclass 29, count 0 2006.285.11:34:19.06#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:34:19.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:34:19.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:34:19.06#ibcon#*before write, iclass 29, count 0 2006.285.11:34:19.06#ibcon#enter sib2, iclass 29, count 0 2006.285.11:34:19.06#ibcon#flushed, iclass 29, count 0 2006.285.11:34:19.06#ibcon#about to write, iclass 29, count 0 2006.285.11:34:19.06#ibcon#wrote, iclass 29, count 0 2006.285.11:34:19.06#ibcon#about to read 3, iclass 29, count 0 2006.285.11:34:19.10#ibcon#read 3, iclass 29, count 0 2006.285.11:34:19.10#ibcon#about to read 4, iclass 29, count 0 2006.285.11:34:19.10#ibcon#read 4, iclass 29, count 0 2006.285.11:34:19.10#ibcon#about to read 5, iclass 29, count 0 2006.285.11:34:19.10#ibcon#read 5, iclass 29, count 0 2006.285.11:34:19.10#ibcon#about to read 6, iclass 29, count 0 2006.285.11:34:19.10#ibcon#read 6, iclass 29, count 0 2006.285.11:34:19.10#ibcon#end of sib2, iclass 29, count 0 2006.285.11:34:19.10#ibcon#*after write, iclass 29, count 0 2006.285.11:34:19.10#ibcon#*before return 0, iclass 29, count 0 2006.285.11:34:19.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:34:19.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:34:19.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:34:19.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:34:19.10$vck44/va=2,6 2006.285.11:34:19.10#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.11:34:19.10#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.11:34:19.10#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:19.10#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:34:19.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:34:19.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:34:19.16#ibcon#enter wrdev, iclass 31, count 2 2006.285.11:34:19.16#ibcon#first serial, iclass 31, count 2 2006.285.11:34:19.16#ibcon#enter sib2, iclass 31, count 2 2006.285.11:34:19.16#ibcon#flushed, iclass 31, count 2 2006.285.11:34:19.16#ibcon#about to write, iclass 31, count 2 2006.285.11:34:19.16#ibcon#wrote, iclass 31, count 2 2006.285.11:34:19.16#ibcon#about to read 3, iclass 31, count 2 2006.285.11:34:19.18#ibcon#read 3, iclass 31, count 2 2006.285.11:34:19.18#ibcon#about to read 4, iclass 31, count 2 2006.285.11:34:19.18#ibcon#read 4, iclass 31, count 2 2006.285.11:34:19.18#ibcon#about to read 5, iclass 31, count 2 2006.285.11:34:19.18#ibcon#read 5, iclass 31, count 2 2006.285.11:34:19.18#ibcon#about to read 6, iclass 31, count 2 2006.285.11:34:19.18#ibcon#read 6, iclass 31, count 2 2006.285.11:34:19.18#ibcon#end of sib2, iclass 31, count 2 2006.285.11:34:19.18#ibcon#*mode == 0, iclass 31, count 2 2006.285.11:34:19.18#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.11:34:19.18#ibcon#[25=AT02-06\r\n] 2006.285.11:34:19.18#ibcon#*before write, iclass 31, count 2 2006.285.11:34:19.18#ibcon#enter sib2, iclass 31, count 2 2006.285.11:34:19.18#ibcon#flushed, iclass 31, count 2 2006.285.11:34:19.18#ibcon#about to write, iclass 31, count 2 2006.285.11:34:19.18#ibcon#wrote, iclass 31, count 2 2006.285.11:34:19.18#ibcon#about to read 3, iclass 31, count 2 2006.285.11:34:19.21#ibcon#read 3, iclass 31, count 2 2006.285.11:34:19.21#ibcon#about to read 4, iclass 31, count 2 2006.285.11:34:19.21#ibcon#read 4, iclass 31, count 2 2006.285.11:34:19.21#ibcon#about to read 5, iclass 31, count 2 2006.285.11:34:19.21#ibcon#read 5, iclass 31, count 2 2006.285.11:34:19.21#ibcon#about to read 6, iclass 31, count 2 2006.285.11:34:19.21#ibcon#read 6, iclass 31, count 2 2006.285.11:34:19.21#ibcon#end of sib2, iclass 31, count 2 2006.285.11:34:19.21#ibcon#*after write, iclass 31, count 2 2006.285.11:34:19.21#ibcon#*before return 0, iclass 31, count 2 2006.285.11:34:19.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:34:19.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:34:19.21#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.11:34:19.21#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:19.21#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:34:19.33#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:34:19.33#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:34:19.33#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:34:19.33#ibcon#first serial, iclass 31, count 0 2006.285.11:34:19.33#ibcon#enter sib2, iclass 31, count 0 2006.285.11:34:19.33#ibcon#flushed, iclass 31, count 0 2006.285.11:34:19.33#ibcon#about to write, iclass 31, count 0 2006.285.11:34:19.33#ibcon#wrote, iclass 31, count 0 2006.285.11:34:19.33#ibcon#about to read 3, iclass 31, count 0 2006.285.11:34:19.35#ibcon#read 3, iclass 31, count 0 2006.285.11:34:19.35#ibcon#about to read 4, iclass 31, count 0 2006.285.11:34:19.35#ibcon#read 4, iclass 31, count 0 2006.285.11:34:19.35#ibcon#about to read 5, iclass 31, count 0 2006.285.11:34:19.35#ibcon#read 5, iclass 31, count 0 2006.285.11:34:19.35#ibcon#about to read 6, iclass 31, count 0 2006.285.11:34:19.35#ibcon#read 6, iclass 31, count 0 2006.285.11:34:19.35#ibcon#end of sib2, iclass 31, count 0 2006.285.11:34:19.35#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:34:19.35#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:34:19.35#ibcon#[25=USB\r\n] 2006.285.11:34:19.35#ibcon#*before write, iclass 31, count 0 2006.285.11:34:19.35#ibcon#enter sib2, iclass 31, count 0 2006.285.11:34:19.35#ibcon#flushed, iclass 31, count 0 2006.285.11:34:19.35#ibcon#about to write, iclass 31, count 0 2006.285.11:34:19.35#ibcon#wrote, iclass 31, count 0 2006.285.11:34:19.35#ibcon#about to read 3, iclass 31, count 0 2006.285.11:34:19.38#ibcon#read 3, iclass 31, count 0 2006.285.11:34:19.38#ibcon#about to read 4, iclass 31, count 0 2006.285.11:34:19.38#ibcon#read 4, iclass 31, count 0 2006.285.11:34:19.38#ibcon#about to read 5, iclass 31, count 0 2006.285.11:34:19.38#ibcon#read 5, iclass 31, count 0 2006.285.11:34:19.38#ibcon#about to read 6, iclass 31, count 0 2006.285.11:34:19.38#ibcon#read 6, iclass 31, count 0 2006.285.11:34:19.38#ibcon#end of sib2, iclass 31, count 0 2006.285.11:34:19.38#ibcon#*after write, iclass 31, count 0 2006.285.11:34:19.38#ibcon#*before return 0, iclass 31, count 0 2006.285.11:34:19.38#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:34:19.38#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:34:19.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:34:19.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:34:19.38$vck44/valo=3,564.99 2006.285.11:34:19.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.11:34:19.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.11:34:19.38#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:19.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:34:19.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:34:19.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:34:19.38#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:34:19.38#ibcon#first serial, iclass 33, count 0 2006.285.11:34:19.38#ibcon#enter sib2, iclass 33, count 0 2006.285.11:34:19.38#ibcon#flushed, iclass 33, count 0 2006.285.11:34:19.38#ibcon#about to write, iclass 33, count 0 2006.285.11:34:19.38#ibcon#wrote, iclass 33, count 0 2006.285.11:34:19.38#ibcon#about to read 3, iclass 33, count 0 2006.285.11:34:19.40#ibcon#read 3, iclass 33, count 0 2006.285.11:34:19.40#ibcon#about to read 4, iclass 33, count 0 2006.285.11:34:19.40#ibcon#read 4, iclass 33, count 0 2006.285.11:34:19.40#ibcon#about to read 5, iclass 33, count 0 2006.285.11:34:19.40#ibcon#read 5, iclass 33, count 0 2006.285.11:34:19.40#ibcon#about to read 6, iclass 33, count 0 2006.285.11:34:19.40#ibcon#read 6, iclass 33, count 0 2006.285.11:34:19.40#ibcon#end of sib2, iclass 33, count 0 2006.285.11:34:19.40#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:34:19.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:34:19.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:34:19.40#ibcon#*before write, iclass 33, count 0 2006.285.11:34:19.40#ibcon#enter sib2, iclass 33, count 0 2006.285.11:34:19.40#ibcon#flushed, iclass 33, count 0 2006.285.11:34:19.40#ibcon#about to write, iclass 33, count 0 2006.285.11:34:19.40#ibcon#wrote, iclass 33, count 0 2006.285.11:34:19.40#ibcon#about to read 3, iclass 33, count 0 2006.285.11:34:19.44#ibcon#read 3, iclass 33, count 0 2006.285.11:34:19.44#ibcon#about to read 4, iclass 33, count 0 2006.285.11:34:19.44#ibcon#read 4, iclass 33, count 0 2006.285.11:34:19.44#ibcon#about to read 5, iclass 33, count 0 2006.285.11:34:19.44#ibcon#read 5, iclass 33, count 0 2006.285.11:34:19.44#ibcon#about to read 6, iclass 33, count 0 2006.285.11:34:19.44#ibcon#read 6, iclass 33, count 0 2006.285.11:34:19.44#ibcon#end of sib2, iclass 33, count 0 2006.285.11:34:19.44#ibcon#*after write, iclass 33, count 0 2006.285.11:34:19.44#ibcon#*before return 0, iclass 33, count 0 2006.285.11:34:19.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:34:19.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:34:19.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:34:19.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:34:19.44$vck44/va=3,7 2006.285.11:34:19.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.11:34:19.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.11:34:19.44#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:19.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:34:19.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:34:19.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:34:19.50#ibcon#enter wrdev, iclass 35, count 2 2006.285.11:34:19.50#ibcon#first serial, iclass 35, count 2 2006.285.11:34:19.50#ibcon#enter sib2, iclass 35, count 2 2006.285.11:34:19.50#ibcon#flushed, iclass 35, count 2 2006.285.11:34:19.50#ibcon#about to write, iclass 35, count 2 2006.285.11:34:19.50#ibcon#wrote, iclass 35, count 2 2006.285.11:34:19.50#ibcon#about to read 3, iclass 35, count 2 2006.285.11:34:19.52#ibcon#read 3, iclass 35, count 2 2006.285.11:34:19.52#ibcon#about to read 4, iclass 35, count 2 2006.285.11:34:19.52#ibcon#read 4, iclass 35, count 2 2006.285.11:34:19.52#ibcon#about to read 5, iclass 35, count 2 2006.285.11:34:19.52#ibcon#read 5, iclass 35, count 2 2006.285.11:34:19.52#ibcon#about to read 6, iclass 35, count 2 2006.285.11:34:19.52#ibcon#read 6, iclass 35, count 2 2006.285.11:34:19.52#ibcon#end of sib2, iclass 35, count 2 2006.285.11:34:19.52#ibcon#*mode == 0, iclass 35, count 2 2006.285.11:34:19.52#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.11:34:19.52#ibcon#[25=AT03-07\r\n] 2006.285.11:34:19.52#ibcon#*before write, iclass 35, count 2 2006.285.11:34:19.52#ibcon#enter sib2, iclass 35, count 2 2006.285.11:34:19.52#ibcon#flushed, iclass 35, count 2 2006.285.11:34:19.52#ibcon#about to write, iclass 35, count 2 2006.285.11:34:19.52#ibcon#wrote, iclass 35, count 2 2006.285.11:34:19.52#ibcon#about to read 3, iclass 35, count 2 2006.285.11:34:19.55#ibcon#read 3, iclass 35, count 2 2006.285.11:34:19.55#ibcon#about to read 4, iclass 35, count 2 2006.285.11:34:19.55#ibcon#read 4, iclass 35, count 2 2006.285.11:34:19.55#ibcon#about to read 5, iclass 35, count 2 2006.285.11:34:19.55#ibcon#read 5, iclass 35, count 2 2006.285.11:34:19.55#ibcon#about to read 6, iclass 35, count 2 2006.285.11:34:19.55#ibcon#read 6, iclass 35, count 2 2006.285.11:34:19.55#ibcon#end of sib2, iclass 35, count 2 2006.285.11:34:19.55#ibcon#*after write, iclass 35, count 2 2006.285.11:34:19.55#ibcon#*before return 0, iclass 35, count 2 2006.285.11:34:19.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:34:19.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:34:19.55#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.11:34:19.55#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:19.55#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:34:19.67#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:34:19.67#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:34:19.67#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:34:19.67#ibcon#first serial, iclass 35, count 0 2006.285.11:34:19.67#ibcon#enter sib2, iclass 35, count 0 2006.285.11:34:19.67#ibcon#flushed, iclass 35, count 0 2006.285.11:34:19.67#ibcon#about to write, iclass 35, count 0 2006.285.11:34:19.67#ibcon#wrote, iclass 35, count 0 2006.285.11:34:19.67#ibcon#about to read 3, iclass 35, count 0 2006.285.11:34:19.69#ibcon#read 3, iclass 35, count 0 2006.285.11:34:19.69#ibcon#about to read 4, iclass 35, count 0 2006.285.11:34:19.69#ibcon#read 4, iclass 35, count 0 2006.285.11:34:19.69#ibcon#about to read 5, iclass 35, count 0 2006.285.11:34:19.69#ibcon#read 5, iclass 35, count 0 2006.285.11:34:19.69#ibcon#about to read 6, iclass 35, count 0 2006.285.11:34:19.69#ibcon#read 6, iclass 35, count 0 2006.285.11:34:19.69#ibcon#end of sib2, iclass 35, count 0 2006.285.11:34:19.69#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:34:19.69#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:34:19.69#ibcon#[25=USB\r\n] 2006.285.11:34:19.69#ibcon#*before write, iclass 35, count 0 2006.285.11:34:19.69#ibcon#enter sib2, iclass 35, count 0 2006.285.11:34:19.69#ibcon#flushed, iclass 35, count 0 2006.285.11:34:19.69#ibcon#about to write, iclass 35, count 0 2006.285.11:34:19.69#ibcon#wrote, iclass 35, count 0 2006.285.11:34:19.69#ibcon#about to read 3, iclass 35, count 0 2006.285.11:34:19.72#ibcon#read 3, iclass 35, count 0 2006.285.11:34:19.72#ibcon#about to read 4, iclass 35, count 0 2006.285.11:34:19.72#ibcon#read 4, iclass 35, count 0 2006.285.11:34:19.72#ibcon#about to read 5, iclass 35, count 0 2006.285.11:34:19.72#ibcon#read 5, iclass 35, count 0 2006.285.11:34:19.72#ibcon#about to read 6, iclass 35, count 0 2006.285.11:34:19.72#ibcon#read 6, iclass 35, count 0 2006.285.11:34:19.72#ibcon#end of sib2, iclass 35, count 0 2006.285.11:34:19.72#ibcon#*after write, iclass 35, count 0 2006.285.11:34:19.72#ibcon#*before return 0, iclass 35, count 0 2006.285.11:34:19.72#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:34:19.72#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:34:19.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:34:19.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:34:19.72$vck44/valo=4,624.99 2006.285.11:34:19.72#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.11:34:19.72#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.11:34:19.72#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:19.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:34:19.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:34:19.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:34:19.72#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:34:19.72#ibcon#first serial, iclass 37, count 0 2006.285.11:34:19.72#ibcon#enter sib2, iclass 37, count 0 2006.285.11:34:19.72#ibcon#flushed, iclass 37, count 0 2006.285.11:34:19.72#ibcon#about to write, iclass 37, count 0 2006.285.11:34:19.72#ibcon#wrote, iclass 37, count 0 2006.285.11:34:19.72#ibcon#about to read 3, iclass 37, count 0 2006.285.11:34:19.74#ibcon#read 3, iclass 37, count 0 2006.285.11:34:19.74#ibcon#about to read 4, iclass 37, count 0 2006.285.11:34:19.74#ibcon#read 4, iclass 37, count 0 2006.285.11:34:19.74#ibcon#about to read 5, iclass 37, count 0 2006.285.11:34:19.74#ibcon#read 5, iclass 37, count 0 2006.285.11:34:19.74#ibcon#about to read 6, iclass 37, count 0 2006.285.11:34:19.74#ibcon#read 6, iclass 37, count 0 2006.285.11:34:19.74#ibcon#end of sib2, iclass 37, count 0 2006.285.11:34:19.74#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:34:19.74#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:34:19.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:34:19.74#ibcon#*before write, iclass 37, count 0 2006.285.11:34:19.74#ibcon#enter sib2, iclass 37, count 0 2006.285.11:34:19.74#ibcon#flushed, iclass 37, count 0 2006.285.11:34:19.74#ibcon#about to write, iclass 37, count 0 2006.285.11:34:19.74#ibcon#wrote, iclass 37, count 0 2006.285.11:34:19.74#ibcon#about to read 3, iclass 37, count 0 2006.285.11:34:19.78#ibcon#read 3, iclass 37, count 0 2006.285.11:34:19.78#ibcon#about to read 4, iclass 37, count 0 2006.285.11:34:19.78#ibcon#read 4, iclass 37, count 0 2006.285.11:34:19.78#ibcon#about to read 5, iclass 37, count 0 2006.285.11:34:19.78#ibcon#read 5, iclass 37, count 0 2006.285.11:34:19.78#ibcon#about to read 6, iclass 37, count 0 2006.285.11:34:19.78#ibcon#read 6, iclass 37, count 0 2006.285.11:34:19.78#ibcon#end of sib2, iclass 37, count 0 2006.285.11:34:19.78#ibcon#*after write, iclass 37, count 0 2006.285.11:34:19.78#ibcon#*before return 0, iclass 37, count 0 2006.285.11:34:19.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:34:19.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:34:19.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:34:19.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:34:19.78$vck44/va=4,6 2006.285.11:34:19.78#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.11:34:19.78#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.11:34:19.78#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:19.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:34:19.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:34:19.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:34:19.84#ibcon#enter wrdev, iclass 39, count 2 2006.285.11:34:19.84#ibcon#first serial, iclass 39, count 2 2006.285.11:34:19.84#ibcon#enter sib2, iclass 39, count 2 2006.285.11:34:19.84#ibcon#flushed, iclass 39, count 2 2006.285.11:34:19.84#ibcon#about to write, iclass 39, count 2 2006.285.11:34:19.84#ibcon#wrote, iclass 39, count 2 2006.285.11:34:19.84#ibcon#about to read 3, iclass 39, count 2 2006.285.11:34:19.86#ibcon#read 3, iclass 39, count 2 2006.285.11:34:19.86#ibcon#about to read 4, iclass 39, count 2 2006.285.11:34:19.86#ibcon#read 4, iclass 39, count 2 2006.285.11:34:19.86#ibcon#about to read 5, iclass 39, count 2 2006.285.11:34:19.86#ibcon#read 5, iclass 39, count 2 2006.285.11:34:19.86#ibcon#about to read 6, iclass 39, count 2 2006.285.11:34:19.86#ibcon#read 6, iclass 39, count 2 2006.285.11:34:19.86#ibcon#end of sib2, iclass 39, count 2 2006.285.11:34:19.86#ibcon#*mode == 0, iclass 39, count 2 2006.285.11:34:19.86#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.11:34:19.86#ibcon#[25=AT04-06\r\n] 2006.285.11:34:19.86#ibcon#*before write, iclass 39, count 2 2006.285.11:34:19.86#ibcon#enter sib2, iclass 39, count 2 2006.285.11:34:19.86#ibcon#flushed, iclass 39, count 2 2006.285.11:34:19.86#ibcon#about to write, iclass 39, count 2 2006.285.11:34:19.86#ibcon#wrote, iclass 39, count 2 2006.285.11:34:19.86#ibcon#about to read 3, iclass 39, count 2 2006.285.11:34:19.89#ibcon#read 3, iclass 39, count 2 2006.285.11:34:19.89#ibcon#about to read 4, iclass 39, count 2 2006.285.11:34:19.89#ibcon#read 4, iclass 39, count 2 2006.285.11:34:19.89#ibcon#about to read 5, iclass 39, count 2 2006.285.11:34:19.89#ibcon#read 5, iclass 39, count 2 2006.285.11:34:19.89#ibcon#about to read 6, iclass 39, count 2 2006.285.11:34:19.89#ibcon#read 6, iclass 39, count 2 2006.285.11:34:19.89#ibcon#end of sib2, iclass 39, count 2 2006.285.11:34:19.89#ibcon#*after write, iclass 39, count 2 2006.285.11:34:19.89#ibcon#*before return 0, iclass 39, count 2 2006.285.11:34:19.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:34:19.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:34:19.89#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.11:34:19.89#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:19.89#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:34:20.01#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:34:20.01#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:34:20.01#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:34:20.01#ibcon#first serial, iclass 39, count 0 2006.285.11:34:20.01#ibcon#enter sib2, iclass 39, count 0 2006.285.11:34:20.01#ibcon#flushed, iclass 39, count 0 2006.285.11:34:20.01#ibcon#about to write, iclass 39, count 0 2006.285.11:34:20.01#ibcon#wrote, iclass 39, count 0 2006.285.11:34:20.01#ibcon#about to read 3, iclass 39, count 0 2006.285.11:34:20.03#ibcon#read 3, iclass 39, count 0 2006.285.11:34:20.03#ibcon#about to read 4, iclass 39, count 0 2006.285.11:34:20.03#ibcon#read 4, iclass 39, count 0 2006.285.11:34:20.03#ibcon#about to read 5, iclass 39, count 0 2006.285.11:34:20.03#ibcon#read 5, iclass 39, count 0 2006.285.11:34:20.03#ibcon#about to read 6, iclass 39, count 0 2006.285.11:34:20.03#ibcon#read 6, iclass 39, count 0 2006.285.11:34:20.03#ibcon#end of sib2, iclass 39, count 0 2006.285.11:34:20.03#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:34:20.03#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:34:20.03#ibcon#[25=USB\r\n] 2006.285.11:34:20.03#ibcon#*before write, iclass 39, count 0 2006.285.11:34:20.03#ibcon#enter sib2, iclass 39, count 0 2006.285.11:34:20.03#ibcon#flushed, iclass 39, count 0 2006.285.11:34:20.03#ibcon#about to write, iclass 39, count 0 2006.285.11:34:20.03#ibcon#wrote, iclass 39, count 0 2006.285.11:34:20.03#ibcon#about to read 3, iclass 39, count 0 2006.285.11:34:20.06#ibcon#read 3, iclass 39, count 0 2006.285.11:34:20.06#ibcon#about to read 4, iclass 39, count 0 2006.285.11:34:20.06#ibcon#read 4, iclass 39, count 0 2006.285.11:34:20.06#ibcon#about to read 5, iclass 39, count 0 2006.285.11:34:20.06#ibcon#read 5, iclass 39, count 0 2006.285.11:34:20.06#ibcon#about to read 6, iclass 39, count 0 2006.285.11:34:20.06#ibcon#read 6, iclass 39, count 0 2006.285.11:34:20.06#ibcon#end of sib2, iclass 39, count 0 2006.285.11:34:20.06#ibcon#*after write, iclass 39, count 0 2006.285.11:34:20.06#ibcon#*before return 0, iclass 39, count 0 2006.285.11:34:20.06#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:34:20.06#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:34:20.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:34:20.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:34:20.06$vck44/valo=5,734.99 2006.285.11:34:20.06#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.11:34:20.06#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.11:34:20.06#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:20.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:34:20.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:34:20.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:34:20.06#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:34:20.06#ibcon#first serial, iclass 3, count 0 2006.285.11:34:20.06#ibcon#enter sib2, iclass 3, count 0 2006.285.11:34:20.06#ibcon#flushed, iclass 3, count 0 2006.285.11:34:20.06#ibcon#about to write, iclass 3, count 0 2006.285.11:34:20.06#ibcon#wrote, iclass 3, count 0 2006.285.11:34:20.06#ibcon#about to read 3, iclass 3, count 0 2006.285.11:34:20.08#ibcon#read 3, iclass 3, count 0 2006.285.11:34:20.08#ibcon#about to read 4, iclass 3, count 0 2006.285.11:34:20.08#ibcon#read 4, iclass 3, count 0 2006.285.11:34:20.08#ibcon#about to read 5, iclass 3, count 0 2006.285.11:34:20.08#ibcon#read 5, iclass 3, count 0 2006.285.11:34:20.08#ibcon#about to read 6, iclass 3, count 0 2006.285.11:34:20.08#ibcon#read 6, iclass 3, count 0 2006.285.11:34:20.08#ibcon#end of sib2, iclass 3, count 0 2006.285.11:34:20.08#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:34:20.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:34:20.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:34:20.08#ibcon#*before write, iclass 3, count 0 2006.285.11:34:20.08#ibcon#enter sib2, iclass 3, count 0 2006.285.11:34:20.08#ibcon#flushed, iclass 3, count 0 2006.285.11:34:20.08#ibcon#about to write, iclass 3, count 0 2006.285.11:34:20.08#ibcon#wrote, iclass 3, count 0 2006.285.11:34:20.08#ibcon#about to read 3, iclass 3, count 0 2006.285.11:34:20.12#ibcon#read 3, iclass 3, count 0 2006.285.11:34:20.12#ibcon#about to read 4, iclass 3, count 0 2006.285.11:34:20.12#ibcon#read 4, iclass 3, count 0 2006.285.11:34:20.12#ibcon#about to read 5, iclass 3, count 0 2006.285.11:34:20.12#ibcon#read 5, iclass 3, count 0 2006.285.11:34:20.12#ibcon#about to read 6, iclass 3, count 0 2006.285.11:34:20.12#ibcon#read 6, iclass 3, count 0 2006.285.11:34:20.12#ibcon#end of sib2, iclass 3, count 0 2006.285.11:34:20.12#ibcon#*after write, iclass 3, count 0 2006.285.11:34:20.12#ibcon#*before return 0, iclass 3, count 0 2006.285.11:34:20.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:34:20.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:34:20.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:34:20.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:34:20.12$vck44/va=5,3 2006.285.11:34:20.12#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.11:34:20.12#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.11:34:20.12#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:20.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:34:20.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:34:20.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:34:20.18#ibcon#enter wrdev, iclass 5, count 2 2006.285.11:34:20.18#ibcon#first serial, iclass 5, count 2 2006.285.11:34:20.18#ibcon#enter sib2, iclass 5, count 2 2006.285.11:34:20.18#ibcon#flushed, iclass 5, count 2 2006.285.11:34:20.18#ibcon#about to write, iclass 5, count 2 2006.285.11:34:20.18#ibcon#wrote, iclass 5, count 2 2006.285.11:34:20.18#ibcon#about to read 3, iclass 5, count 2 2006.285.11:34:20.20#ibcon#read 3, iclass 5, count 2 2006.285.11:34:20.20#ibcon#about to read 4, iclass 5, count 2 2006.285.11:34:20.20#ibcon#read 4, iclass 5, count 2 2006.285.11:34:20.20#ibcon#about to read 5, iclass 5, count 2 2006.285.11:34:20.20#ibcon#read 5, iclass 5, count 2 2006.285.11:34:20.20#ibcon#about to read 6, iclass 5, count 2 2006.285.11:34:20.20#ibcon#read 6, iclass 5, count 2 2006.285.11:34:20.20#ibcon#end of sib2, iclass 5, count 2 2006.285.11:34:20.20#ibcon#*mode == 0, iclass 5, count 2 2006.285.11:34:20.20#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.11:34:20.20#ibcon#[25=AT05-03\r\n] 2006.285.11:34:20.20#ibcon#*before write, iclass 5, count 2 2006.285.11:34:20.20#ibcon#enter sib2, iclass 5, count 2 2006.285.11:34:20.20#ibcon#flushed, iclass 5, count 2 2006.285.11:34:20.20#ibcon#about to write, iclass 5, count 2 2006.285.11:34:20.20#ibcon#wrote, iclass 5, count 2 2006.285.11:34:20.20#ibcon#about to read 3, iclass 5, count 2 2006.285.11:34:20.23#ibcon#read 3, iclass 5, count 2 2006.285.11:34:20.23#ibcon#about to read 4, iclass 5, count 2 2006.285.11:34:20.23#ibcon#read 4, iclass 5, count 2 2006.285.11:34:20.23#ibcon#about to read 5, iclass 5, count 2 2006.285.11:34:20.23#ibcon#read 5, iclass 5, count 2 2006.285.11:34:20.23#ibcon#about to read 6, iclass 5, count 2 2006.285.11:34:20.23#ibcon#read 6, iclass 5, count 2 2006.285.11:34:20.23#ibcon#end of sib2, iclass 5, count 2 2006.285.11:34:20.23#ibcon#*after write, iclass 5, count 2 2006.285.11:34:20.23#ibcon#*before return 0, iclass 5, count 2 2006.285.11:34:20.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:34:20.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:34:20.23#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.11:34:20.23#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:20.23#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:34:20.35#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:34:20.35#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:34:20.35#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:34:20.35#ibcon#first serial, iclass 5, count 0 2006.285.11:34:20.35#ibcon#enter sib2, iclass 5, count 0 2006.285.11:34:20.35#ibcon#flushed, iclass 5, count 0 2006.285.11:34:20.35#ibcon#about to write, iclass 5, count 0 2006.285.11:34:20.35#ibcon#wrote, iclass 5, count 0 2006.285.11:34:20.35#ibcon#about to read 3, iclass 5, count 0 2006.285.11:34:20.37#ibcon#read 3, iclass 5, count 0 2006.285.11:34:20.37#ibcon#about to read 4, iclass 5, count 0 2006.285.11:34:20.37#ibcon#read 4, iclass 5, count 0 2006.285.11:34:20.37#ibcon#about to read 5, iclass 5, count 0 2006.285.11:34:20.37#ibcon#read 5, iclass 5, count 0 2006.285.11:34:20.37#ibcon#about to read 6, iclass 5, count 0 2006.285.11:34:20.37#ibcon#read 6, iclass 5, count 0 2006.285.11:34:20.37#ibcon#end of sib2, iclass 5, count 0 2006.285.11:34:20.37#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:34:20.37#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:34:20.37#ibcon#[25=USB\r\n] 2006.285.11:34:20.37#ibcon#*before write, iclass 5, count 0 2006.285.11:34:20.37#ibcon#enter sib2, iclass 5, count 0 2006.285.11:34:20.37#ibcon#flushed, iclass 5, count 0 2006.285.11:34:20.37#ibcon#about to write, iclass 5, count 0 2006.285.11:34:20.37#ibcon#wrote, iclass 5, count 0 2006.285.11:34:20.37#ibcon#about to read 3, iclass 5, count 0 2006.285.11:34:20.40#ibcon#read 3, iclass 5, count 0 2006.285.11:34:20.40#ibcon#about to read 4, iclass 5, count 0 2006.285.11:34:20.40#ibcon#read 4, iclass 5, count 0 2006.285.11:34:20.40#ibcon#about to read 5, iclass 5, count 0 2006.285.11:34:20.40#ibcon#read 5, iclass 5, count 0 2006.285.11:34:20.40#ibcon#about to read 6, iclass 5, count 0 2006.285.11:34:20.40#ibcon#read 6, iclass 5, count 0 2006.285.11:34:20.40#ibcon#end of sib2, iclass 5, count 0 2006.285.11:34:20.40#ibcon#*after write, iclass 5, count 0 2006.285.11:34:20.40#ibcon#*before return 0, iclass 5, count 0 2006.285.11:34:20.40#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:34:20.40#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:34:20.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:34:20.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:34:20.40$vck44/valo=6,814.99 2006.285.11:34:20.40#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.11:34:20.40#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.11:34:20.40#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:20.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:34:20.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:34:20.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:34:20.40#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:34:20.40#ibcon#first serial, iclass 7, count 0 2006.285.11:34:20.40#ibcon#enter sib2, iclass 7, count 0 2006.285.11:34:20.40#ibcon#flushed, iclass 7, count 0 2006.285.11:34:20.40#ibcon#about to write, iclass 7, count 0 2006.285.11:34:20.40#ibcon#wrote, iclass 7, count 0 2006.285.11:34:20.40#ibcon#about to read 3, iclass 7, count 0 2006.285.11:34:20.42#ibcon#read 3, iclass 7, count 0 2006.285.11:34:20.42#ibcon#about to read 4, iclass 7, count 0 2006.285.11:34:20.42#ibcon#read 4, iclass 7, count 0 2006.285.11:34:20.42#ibcon#about to read 5, iclass 7, count 0 2006.285.11:34:20.42#ibcon#read 5, iclass 7, count 0 2006.285.11:34:20.42#ibcon#about to read 6, iclass 7, count 0 2006.285.11:34:20.42#ibcon#read 6, iclass 7, count 0 2006.285.11:34:20.42#ibcon#end of sib2, iclass 7, count 0 2006.285.11:34:20.42#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:34:20.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:34:20.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:34:20.42#ibcon#*before write, iclass 7, count 0 2006.285.11:34:20.42#ibcon#enter sib2, iclass 7, count 0 2006.285.11:34:20.42#ibcon#flushed, iclass 7, count 0 2006.285.11:34:20.42#ibcon#about to write, iclass 7, count 0 2006.285.11:34:20.42#ibcon#wrote, iclass 7, count 0 2006.285.11:34:20.42#ibcon#about to read 3, iclass 7, count 0 2006.285.11:34:20.46#ibcon#read 3, iclass 7, count 0 2006.285.11:34:20.46#ibcon#about to read 4, iclass 7, count 0 2006.285.11:34:20.46#ibcon#read 4, iclass 7, count 0 2006.285.11:34:20.46#ibcon#about to read 5, iclass 7, count 0 2006.285.11:34:20.46#ibcon#read 5, iclass 7, count 0 2006.285.11:34:20.46#ibcon#about to read 6, iclass 7, count 0 2006.285.11:34:20.46#ibcon#read 6, iclass 7, count 0 2006.285.11:34:20.46#ibcon#end of sib2, iclass 7, count 0 2006.285.11:34:20.46#ibcon#*after write, iclass 7, count 0 2006.285.11:34:20.46#ibcon#*before return 0, iclass 7, count 0 2006.285.11:34:20.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:34:20.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:34:20.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:34:20.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:34:20.46$vck44/va=6,4 2006.285.11:34:20.46#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.11:34:20.46#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.11:34:20.46#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:20.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:34:20.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:34:20.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:34:20.52#ibcon#enter wrdev, iclass 11, count 2 2006.285.11:34:20.52#ibcon#first serial, iclass 11, count 2 2006.285.11:34:20.52#ibcon#enter sib2, iclass 11, count 2 2006.285.11:34:20.52#ibcon#flushed, iclass 11, count 2 2006.285.11:34:20.52#ibcon#about to write, iclass 11, count 2 2006.285.11:34:20.52#ibcon#wrote, iclass 11, count 2 2006.285.11:34:20.52#ibcon#about to read 3, iclass 11, count 2 2006.285.11:34:20.54#ibcon#read 3, iclass 11, count 2 2006.285.11:34:20.54#ibcon#about to read 4, iclass 11, count 2 2006.285.11:34:20.54#ibcon#read 4, iclass 11, count 2 2006.285.11:34:20.54#ibcon#about to read 5, iclass 11, count 2 2006.285.11:34:20.54#ibcon#read 5, iclass 11, count 2 2006.285.11:34:20.54#ibcon#about to read 6, iclass 11, count 2 2006.285.11:34:20.54#ibcon#read 6, iclass 11, count 2 2006.285.11:34:20.54#ibcon#end of sib2, iclass 11, count 2 2006.285.11:34:20.54#ibcon#*mode == 0, iclass 11, count 2 2006.285.11:34:20.54#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.11:34:20.54#ibcon#[25=AT06-04\r\n] 2006.285.11:34:20.54#ibcon#*before write, iclass 11, count 2 2006.285.11:34:20.54#ibcon#enter sib2, iclass 11, count 2 2006.285.11:34:20.54#ibcon#flushed, iclass 11, count 2 2006.285.11:34:20.54#ibcon#about to write, iclass 11, count 2 2006.285.11:34:20.54#ibcon#wrote, iclass 11, count 2 2006.285.11:34:20.54#ibcon#about to read 3, iclass 11, count 2 2006.285.11:34:20.57#ibcon#read 3, iclass 11, count 2 2006.285.11:34:20.57#ibcon#about to read 4, iclass 11, count 2 2006.285.11:34:20.57#ibcon#read 4, iclass 11, count 2 2006.285.11:34:20.57#ibcon#about to read 5, iclass 11, count 2 2006.285.11:34:20.57#ibcon#read 5, iclass 11, count 2 2006.285.11:34:20.57#ibcon#about to read 6, iclass 11, count 2 2006.285.11:34:20.57#ibcon#read 6, iclass 11, count 2 2006.285.11:34:20.57#ibcon#end of sib2, iclass 11, count 2 2006.285.11:34:20.57#ibcon#*after write, iclass 11, count 2 2006.285.11:34:20.57#ibcon#*before return 0, iclass 11, count 2 2006.285.11:34:20.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:34:20.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:34:20.57#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.11:34:20.57#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:20.57#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:34:20.69#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:34:20.69#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:34:20.69#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:34:20.69#ibcon#first serial, iclass 11, count 0 2006.285.11:34:20.69#ibcon#enter sib2, iclass 11, count 0 2006.285.11:34:20.69#ibcon#flushed, iclass 11, count 0 2006.285.11:34:20.69#ibcon#about to write, iclass 11, count 0 2006.285.11:34:20.69#ibcon#wrote, iclass 11, count 0 2006.285.11:34:20.69#ibcon#about to read 3, iclass 11, count 0 2006.285.11:34:20.71#ibcon#read 3, iclass 11, count 0 2006.285.11:34:20.71#ibcon#about to read 4, iclass 11, count 0 2006.285.11:34:20.71#ibcon#read 4, iclass 11, count 0 2006.285.11:34:20.71#ibcon#about to read 5, iclass 11, count 0 2006.285.11:34:20.71#ibcon#read 5, iclass 11, count 0 2006.285.11:34:20.71#ibcon#about to read 6, iclass 11, count 0 2006.285.11:34:20.71#ibcon#read 6, iclass 11, count 0 2006.285.11:34:20.71#ibcon#end of sib2, iclass 11, count 0 2006.285.11:34:20.71#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:34:20.71#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:34:20.71#ibcon#[25=USB\r\n] 2006.285.11:34:20.71#ibcon#*before write, iclass 11, count 0 2006.285.11:34:20.71#ibcon#enter sib2, iclass 11, count 0 2006.285.11:34:20.71#ibcon#flushed, iclass 11, count 0 2006.285.11:34:20.71#ibcon#about to write, iclass 11, count 0 2006.285.11:34:20.71#ibcon#wrote, iclass 11, count 0 2006.285.11:34:20.71#ibcon#about to read 3, iclass 11, count 0 2006.285.11:34:20.74#ibcon#read 3, iclass 11, count 0 2006.285.11:34:20.74#ibcon#about to read 4, iclass 11, count 0 2006.285.11:34:20.74#ibcon#read 4, iclass 11, count 0 2006.285.11:34:20.74#ibcon#about to read 5, iclass 11, count 0 2006.285.11:34:20.74#ibcon#read 5, iclass 11, count 0 2006.285.11:34:20.74#ibcon#about to read 6, iclass 11, count 0 2006.285.11:34:20.74#ibcon#read 6, iclass 11, count 0 2006.285.11:34:20.74#ibcon#end of sib2, iclass 11, count 0 2006.285.11:34:20.74#ibcon#*after write, iclass 11, count 0 2006.285.11:34:20.74#ibcon#*before return 0, iclass 11, count 0 2006.285.11:34:20.74#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:34:20.74#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:34:20.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:34:20.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:34:20.74$vck44/valo=7,864.99 2006.285.11:34:20.74#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.11:34:20.74#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.11:34:20.74#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:20.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:34:20.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:34:20.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:34:20.74#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:34:20.74#ibcon#first serial, iclass 13, count 0 2006.285.11:34:20.74#ibcon#enter sib2, iclass 13, count 0 2006.285.11:34:20.74#ibcon#flushed, iclass 13, count 0 2006.285.11:34:20.74#ibcon#about to write, iclass 13, count 0 2006.285.11:34:20.74#ibcon#wrote, iclass 13, count 0 2006.285.11:34:20.74#ibcon#about to read 3, iclass 13, count 0 2006.285.11:34:20.76#ibcon#read 3, iclass 13, count 0 2006.285.11:34:20.76#ibcon#about to read 4, iclass 13, count 0 2006.285.11:34:20.76#ibcon#read 4, iclass 13, count 0 2006.285.11:34:20.76#ibcon#about to read 5, iclass 13, count 0 2006.285.11:34:20.76#ibcon#read 5, iclass 13, count 0 2006.285.11:34:20.76#ibcon#about to read 6, iclass 13, count 0 2006.285.11:34:20.76#ibcon#read 6, iclass 13, count 0 2006.285.11:34:20.76#ibcon#end of sib2, iclass 13, count 0 2006.285.11:34:20.76#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:34:20.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:34:20.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:34:20.76#ibcon#*before write, iclass 13, count 0 2006.285.11:34:20.76#ibcon#enter sib2, iclass 13, count 0 2006.285.11:34:20.76#ibcon#flushed, iclass 13, count 0 2006.285.11:34:20.76#ibcon#about to write, iclass 13, count 0 2006.285.11:34:20.76#ibcon#wrote, iclass 13, count 0 2006.285.11:34:20.76#ibcon#about to read 3, iclass 13, count 0 2006.285.11:34:20.80#ibcon#read 3, iclass 13, count 0 2006.285.11:34:20.80#ibcon#about to read 4, iclass 13, count 0 2006.285.11:34:20.80#ibcon#read 4, iclass 13, count 0 2006.285.11:34:20.80#ibcon#about to read 5, iclass 13, count 0 2006.285.11:34:20.80#ibcon#read 5, iclass 13, count 0 2006.285.11:34:20.80#ibcon#about to read 6, iclass 13, count 0 2006.285.11:34:20.80#ibcon#read 6, iclass 13, count 0 2006.285.11:34:20.80#ibcon#end of sib2, iclass 13, count 0 2006.285.11:34:20.80#ibcon#*after write, iclass 13, count 0 2006.285.11:34:20.80#ibcon#*before return 0, iclass 13, count 0 2006.285.11:34:20.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:34:20.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:34:20.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:34:20.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:34:20.80$vck44/va=7,4 2006.285.11:34:20.80#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.11:34:20.80#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.11:34:20.80#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:20.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:34:20.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:34:20.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:34:20.86#ibcon#enter wrdev, iclass 15, count 2 2006.285.11:34:20.86#ibcon#first serial, iclass 15, count 2 2006.285.11:34:20.86#ibcon#enter sib2, iclass 15, count 2 2006.285.11:34:20.86#ibcon#flushed, iclass 15, count 2 2006.285.11:34:20.86#ibcon#about to write, iclass 15, count 2 2006.285.11:34:20.86#ibcon#wrote, iclass 15, count 2 2006.285.11:34:20.86#ibcon#about to read 3, iclass 15, count 2 2006.285.11:34:20.88#ibcon#read 3, iclass 15, count 2 2006.285.11:34:20.88#ibcon#about to read 4, iclass 15, count 2 2006.285.11:34:20.88#ibcon#read 4, iclass 15, count 2 2006.285.11:34:20.88#ibcon#about to read 5, iclass 15, count 2 2006.285.11:34:20.88#ibcon#read 5, iclass 15, count 2 2006.285.11:34:20.88#ibcon#about to read 6, iclass 15, count 2 2006.285.11:34:20.88#ibcon#read 6, iclass 15, count 2 2006.285.11:34:20.88#ibcon#end of sib2, iclass 15, count 2 2006.285.11:34:20.88#ibcon#*mode == 0, iclass 15, count 2 2006.285.11:34:20.88#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.11:34:20.88#ibcon#[25=AT07-04\r\n] 2006.285.11:34:20.88#ibcon#*before write, iclass 15, count 2 2006.285.11:34:20.88#ibcon#enter sib2, iclass 15, count 2 2006.285.11:34:20.88#ibcon#flushed, iclass 15, count 2 2006.285.11:34:20.88#ibcon#about to write, iclass 15, count 2 2006.285.11:34:20.88#ibcon#wrote, iclass 15, count 2 2006.285.11:34:20.88#ibcon#about to read 3, iclass 15, count 2 2006.285.11:34:20.91#ibcon#read 3, iclass 15, count 2 2006.285.11:34:20.91#ibcon#about to read 4, iclass 15, count 2 2006.285.11:34:20.91#ibcon#read 4, iclass 15, count 2 2006.285.11:34:20.91#ibcon#about to read 5, iclass 15, count 2 2006.285.11:34:20.91#ibcon#read 5, iclass 15, count 2 2006.285.11:34:20.91#ibcon#about to read 6, iclass 15, count 2 2006.285.11:34:20.91#ibcon#read 6, iclass 15, count 2 2006.285.11:34:20.91#ibcon#end of sib2, iclass 15, count 2 2006.285.11:34:20.91#ibcon#*after write, iclass 15, count 2 2006.285.11:34:20.91#ibcon#*before return 0, iclass 15, count 2 2006.285.11:34:20.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:34:20.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:34:20.91#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.11:34:20.91#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:20.91#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:34:21.03#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:34:21.03#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:34:21.03#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:34:21.03#ibcon#first serial, iclass 15, count 0 2006.285.11:34:21.03#ibcon#enter sib2, iclass 15, count 0 2006.285.11:34:21.03#ibcon#flushed, iclass 15, count 0 2006.285.11:34:21.03#ibcon#about to write, iclass 15, count 0 2006.285.11:34:21.03#ibcon#wrote, iclass 15, count 0 2006.285.11:34:21.03#ibcon#about to read 3, iclass 15, count 0 2006.285.11:34:21.05#ibcon#read 3, iclass 15, count 0 2006.285.11:34:21.05#ibcon#about to read 4, iclass 15, count 0 2006.285.11:34:21.05#ibcon#read 4, iclass 15, count 0 2006.285.11:34:21.05#ibcon#about to read 5, iclass 15, count 0 2006.285.11:34:21.05#ibcon#read 5, iclass 15, count 0 2006.285.11:34:21.05#ibcon#about to read 6, iclass 15, count 0 2006.285.11:34:21.05#ibcon#read 6, iclass 15, count 0 2006.285.11:34:21.05#ibcon#end of sib2, iclass 15, count 0 2006.285.11:34:21.05#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:34:21.05#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:34:21.05#ibcon#[25=USB\r\n] 2006.285.11:34:21.05#ibcon#*before write, iclass 15, count 0 2006.285.11:34:21.05#ibcon#enter sib2, iclass 15, count 0 2006.285.11:34:21.05#ibcon#flushed, iclass 15, count 0 2006.285.11:34:21.05#ibcon#about to write, iclass 15, count 0 2006.285.11:34:21.05#ibcon#wrote, iclass 15, count 0 2006.285.11:34:21.05#ibcon#about to read 3, iclass 15, count 0 2006.285.11:34:21.08#ibcon#read 3, iclass 15, count 0 2006.285.11:34:21.08#ibcon#about to read 4, iclass 15, count 0 2006.285.11:34:21.08#ibcon#read 4, iclass 15, count 0 2006.285.11:34:21.08#ibcon#about to read 5, iclass 15, count 0 2006.285.11:34:21.08#ibcon#read 5, iclass 15, count 0 2006.285.11:34:21.08#ibcon#about to read 6, iclass 15, count 0 2006.285.11:34:21.08#ibcon#read 6, iclass 15, count 0 2006.285.11:34:21.08#ibcon#end of sib2, iclass 15, count 0 2006.285.11:34:21.08#ibcon#*after write, iclass 15, count 0 2006.285.11:34:21.08#ibcon#*before return 0, iclass 15, count 0 2006.285.11:34:21.08#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:34:21.08#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:34:21.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:34:21.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:34:21.08$vck44/valo=8,884.99 2006.285.11:34:21.08#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.11:34:21.08#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.11:34:21.08#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:21.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:34:21.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:34:21.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:34:21.08#ibcon#enter wrdev, iclass 17, count 0 2006.285.11:34:21.08#ibcon#first serial, iclass 17, count 0 2006.285.11:34:21.08#ibcon#enter sib2, iclass 17, count 0 2006.285.11:34:21.08#ibcon#flushed, iclass 17, count 0 2006.285.11:34:21.08#ibcon#about to write, iclass 17, count 0 2006.285.11:34:21.08#ibcon#wrote, iclass 17, count 0 2006.285.11:34:21.08#ibcon#about to read 3, iclass 17, count 0 2006.285.11:34:21.10#ibcon#read 3, iclass 17, count 0 2006.285.11:34:21.10#ibcon#about to read 4, iclass 17, count 0 2006.285.11:34:21.10#ibcon#read 4, iclass 17, count 0 2006.285.11:34:21.10#ibcon#about to read 5, iclass 17, count 0 2006.285.11:34:21.10#ibcon#read 5, iclass 17, count 0 2006.285.11:34:21.10#ibcon#about to read 6, iclass 17, count 0 2006.285.11:34:21.10#ibcon#read 6, iclass 17, count 0 2006.285.11:34:21.10#ibcon#end of sib2, iclass 17, count 0 2006.285.11:34:21.10#ibcon#*mode == 0, iclass 17, count 0 2006.285.11:34:21.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.11:34:21.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:34:21.10#ibcon#*before write, iclass 17, count 0 2006.285.11:34:21.10#ibcon#enter sib2, iclass 17, count 0 2006.285.11:34:21.10#ibcon#flushed, iclass 17, count 0 2006.285.11:34:21.10#ibcon#about to write, iclass 17, count 0 2006.285.11:34:21.10#ibcon#wrote, iclass 17, count 0 2006.285.11:34:21.10#ibcon#about to read 3, iclass 17, count 0 2006.285.11:34:21.14#ibcon#read 3, iclass 17, count 0 2006.285.11:34:21.14#ibcon#about to read 4, iclass 17, count 0 2006.285.11:34:21.14#ibcon#read 4, iclass 17, count 0 2006.285.11:34:21.14#ibcon#about to read 5, iclass 17, count 0 2006.285.11:34:21.14#ibcon#read 5, iclass 17, count 0 2006.285.11:34:21.14#ibcon#about to read 6, iclass 17, count 0 2006.285.11:34:21.14#ibcon#read 6, iclass 17, count 0 2006.285.11:34:21.14#ibcon#end of sib2, iclass 17, count 0 2006.285.11:34:21.14#ibcon#*after write, iclass 17, count 0 2006.285.11:34:21.14#ibcon#*before return 0, iclass 17, count 0 2006.285.11:34:21.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:34:21.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:34:21.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.11:34:21.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.11:34:21.14$vck44/va=8,3 2006.285.11:34:21.14#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.11:34:21.14#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.11:34:21.14#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:21.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:34:21.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:34:21.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:34:21.20#ibcon#enter wrdev, iclass 19, count 2 2006.285.11:34:21.20#ibcon#first serial, iclass 19, count 2 2006.285.11:34:21.20#ibcon#enter sib2, iclass 19, count 2 2006.285.11:34:21.20#ibcon#flushed, iclass 19, count 2 2006.285.11:34:21.20#ibcon#about to write, iclass 19, count 2 2006.285.11:34:21.20#ibcon#wrote, iclass 19, count 2 2006.285.11:34:21.20#ibcon#about to read 3, iclass 19, count 2 2006.285.11:34:21.22#ibcon#read 3, iclass 19, count 2 2006.285.11:34:21.22#ibcon#about to read 4, iclass 19, count 2 2006.285.11:34:21.22#ibcon#read 4, iclass 19, count 2 2006.285.11:34:21.22#ibcon#about to read 5, iclass 19, count 2 2006.285.11:34:21.22#ibcon#read 5, iclass 19, count 2 2006.285.11:34:21.22#ibcon#about to read 6, iclass 19, count 2 2006.285.11:34:21.22#ibcon#read 6, iclass 19, count 2 2006.285.11:34:21.22#ibcon#end of sib2, iclass 19, count 2 2006.285.11:34:21.22#ibcon#*mode == 0, iclass 19, count 2 2006.285.11:34:21.22#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.11:34:21.22#ibcon#[25=AT08-03\r\n] 2006.285.11:34:21.22#ibcon#*before write, iclass 19, count 2 2006.285.11:34:21.22#ibcon#enter sib2, iclass 19, count 2 2006.285.11:34:21.22#ibcon#flushed, iclass 19, count 2 2006.285.11:34:21.22#ibcon#about to write, iclass 19, count 2 2006.285.11:34:21.22#ibcon#wrote, iclass 19, count 2 2006.285.11:34:21.22#ibcon#about to read 3, iclass 19, count 2 2006.285.11:34:21.25#ibcon#read 3, iclass 19, count 2 2006.285.11:34:21.25#ibcon#about to read 4, iclass 19, count 2 2006.285.11:34:21.25#ibcon#read 4, iclass 19, count 2 2006.285.11:34:21.25#ibcon#about to read 5, iclass 19, count 2 2006.285.11:34:21.25#ibcon#read 5, iclass 19, count 2 2006.285.11:34:21.25#ibcon#about to read 6, iclass 19, count 2 2006.285.11:34:21.25#ibcon#read 6, iclass 19, count 2 2006.285.11:34:21.25#ibcon#end of sib2, iclass 19, count 2 2006.285.11:34:21.25#ibcon#*after write, iclass 19, count 2 2006.285.11:34:21.25#ibcon#*before return 0, iclass 19, count 2 2006.285.11:34:21.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:34:21.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:34:21.25#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.11:34:21.25#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:21.25#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:34:21.37#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:34:21.37#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:34:21.37#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:34:21.37#ibcon#first serial, iclass 19, count 0 2006.285.11:34:21.37#ibcon#enter sib2, iclass 19, count 0 2006.285.11:34:21.37#ibcon#flushed, iclass 19, count 0 2006.285.11:34:21.37#ibcon#about to write, iclass 19, count 0 2006.285.11:34:21.37#ibcon#wrote, iclass 19, count 0 2006.285.11:34:21.37#ibcon#about to read 3, iclass 19, count 0 2006.285.11:34:21.39#ibcon#read 3, iclass 19, count 0 2006.285.11:34:21.39#ibcon#about to read 4, iclass 19, count 0 2006.285.11:34:21.39#ibcon#read 4, iclass 19, count 0 2006.285.11:34:21.39#ibcon#about to read 5, iclass 19, count 0 2006.285.11:34:21.39#ibcon#read 5, iclass 19, count 0 2006.285.11:34:21.39#ibcon#about to read 6, iclass 19, count 0 2006.285.11:34:21.39#ibcon#read 6, iclass 19, count 0 2006.285.11:34:21.39#ibcon#end of sib2, iclass 19, count 0 2006.285.11:34:21.39#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:34:21.39#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:34:21.39#ibcon#[25=USB\r\n] 2006.285.11:34:21.39#ibcon#*before write, iclass 19, count 0 2006.285.11:34:21.39#ibcon#enter sib2, iclass 19, count 0 2006.285.11:34:21.39#ibcon#flushed, iclass 19, count 0 2006.285.11:34:21.39#ibcon#about to write, iclass 19, count 0 2006.285.11:34:21.39#ibcon#wrote, iclass 19, count 0 2006.285.11:34:21.39#ibcon#about to read 3, iclass 19, count 0 2006.285.11:34:21.42#ibcon#read 3, iclass 19, count 0 2006.285.11:34:21.42#ibcon#about to read 4, iclass 19, count 0 2006.285.11:34:21.42#ibcon#read 4, iclass 19, count 0 2006.285.11:34:21.42#ibcon#about to read 5, iclass 19, count 0 2006.285.11:34:21.42#ibcon#read 5, iclass 19, count 0 2006.285.11:34:21.42#ibcon#about to read 6, iclass 19, count 0 2006.285.11:34:21.42#ibcon#read 6, iclass 19, count 0 2006.285.11:34:21.42#ibcon#end of sib2, iclass 19, count 0 2006.285.11:34:21.42#ibcon#*after write, iclass 19, count 0 2006.285.11:34:21.42#ibcon#*before return 0, iclass 19, count 0 2006.285.11:34:21.42#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:34:21.42#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:34:21.42#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:34:21.42#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:34:21.42$vck44/vblo=1,629.99 2006.285.11:34:21.42#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.11:34:21.42#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.11:34:21.42#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:21.42#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:34:21.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:34:21.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:34:21.42#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:34:21.42#ibcon#first serial, iclass 21, count 0 2006.285.11:34:21.42#ibcon#enter sib2, iclass 21, count 0 2006.285.11:34:21.42#ibcon#flushed, iclass 21, count 0 2006.285.11:34:21.42#ibcon#about to write, iclass 21, count 0 2006.285.11:34:21.42#ibcon#wrote, iclass 21, count 0 2006.285.11:34:21.42#ibcon#about to read 3, iclass 21, count 0 2006.285.11:34:21.44#ibcon#read 3, iclass 21, count 0 2006.285.11:34:21.44#ibcon#about to read 4, iclass 21, count 0 2006.285.11:34:21.44#ibcon#read 4, iclass 21, count 0 2006.285.11:34:21.44#ibcon#about to read 5, iclass 21, count 0 2006.285.11:34:21.44#ibcon#read 5, iclass 21, count 0 2006.285.11:34:21.44#ibcon#about to read 6, iclass 21, count 0 2006.285.11:34:21.44#ibcon#read 6, iclass 21, count 0 2006.285.11:34:21.44#ibcon#end of sib2, iclass 21, count 0 2006.285.11:34:21.44#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:34:21.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:34:21.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:34:21.44#ibcon#*before write, iclass 21, count 0 2006.285.11:34:21.44#ibcon#enter sib2, iclass 21, count 0 2006.285.11:34:21.44#ibcon#flushed, iclass 21, count 0 2006.285.11:34:21.44#ibcon#about to write, iclass 21, count 0 2006.285.11:34:21.44#ibcon#wrote, iclass 21, count 0 2006.285.11:34:21.44#ibcon#about to read 3, iclass 21, count 0 2006.285.11:34:21.48#ibcon#read 3, iclass 21, count 0 2006.285.11:34:21.48#ibcon#about to read 4, iclass 21, count 0 2006.285.11:34:21.48#ibcon#read 4, iclass 21, count 0 2006.285.11:34:21.48#ibcon#about to read 5, iclass 21, count 0 2006.285.11:34:21.48#ibcon#read 5, iclass 21, count 0 2006.285.11:34:21.48#ibcon#about to read 6, iclass 21, count 0 2006.285.11:34:21.48#ibcon#read 6, iclass 21, count 0 2006.285.11:34:21.48#ibcon#end of sib2, iclass 21, count 0 2006.285.11:34:21.48#ibcon#*after write, iclass 21, count 0 2006.285.11:34:21.48#ibcon#*before return 0, iclass 21, count 0 2006.285.11:34:21.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:34:21.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:34:21.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:34:21.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:34:21.48$vck44/vb=1,4 2006.285.11:34:21.48#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.11:34:21.48#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.11:34:21.48#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:21.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:34:21.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:34:21.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:34:21.48#ibcon#enter wrdev, iclass 23, count 2 2006.285.11:34:21.48#ibcon#first serial, iclass 23, count 2 2006.285.11:34:21.48#ibcon#enter sib2, iclass 23, count 2 2006.285.11:34:21.48#ibcon#flushed, iclass 23, count 2 2006.285.11:34:21.48#ibcon#about to write, iclass 23, count 2 2006.285.11:34:21.48#ibcon#wrote, iclass 23, count 2 2006.285.11:34:21.48#ibcon#about to read 3, iclass 23, count 2 2006.285.11:34:21.50#ibcon#read 3, iclass 23, count 2 2006.285.11:34:21.50#ibcon#about to read 4, iclass 23, count 2 2006.285.11:34:21.50#ibcon#read 4, iclass 23, count 2 2006.285.11:34:21.50#ibcon#about to read 5, iclass 23, count 2 2006.285.11:34:21.50#ibcon#read 5, iclass 23, count 2 2006.285.11:34:21.50#ibcon#about to read 6, iclass 23, count 2 2006.285.11:34:21.50#ibcon#read 6, iclass 23, count 2 2006.285.11:34:21.50#ibcon#end of sib2, iclass 23, count 2 2006.285.11:34:21.50#ibcon#*mode == 0, iclass 23, count 2 2006.285.11:34:21.50#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.11:34:21.50#ibcon#[27=AT01-04\r\n] 2006.285.11:34:21.50#ibcon#*before write, iclass 23, count 2 2006.285.11:34:21.50#ibcon#enter sib2, iclass 23, count 2 2006.285.11:34:21.50#ibcon#flushed, iclass 23, count 2 2006.285.11:34:21.50#ibcon#about to write, iclass 23, count 2 2006.285.11:34:21.50#ibcon#wrote, iclass 23, count 2 2006.285.11:34:21.50#ibcon#about to read 3, iclass 23, count 2 2006.285.11:34:21.53#ibcon#read 3, iclass 23, count 2 2006.285.11:34:21.53#ibcon#about to read 4, iclass 23, count 2 2006.285.11:34:21.53#ibcon#read 4, iclass 23, count 2 2006.285.11:34:21.53#ibcon#about to read 5, iclass 23, count 2 2006.285.11:34:21.53#ibcon#read 5, iclass 23, count 2 2006.285.11:34:21.53#ibcon#about to read 6, iclass 23, count 2 2006.285.11:34:21.53#ibcon#read 6, iclass 23, count 2 2006.285.11:34:21.53#ibcon#end of sib2, iclass 23, count 2 2006.285.11:34:21.53#ibcon#*after write, iclass 23, count 2 2006.285.11:34:21.53#ibcon#*before return 0, iclass 23, count 2 2006.285.11:34:21.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:34:21.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:34:21.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.11:34:21.53#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:21.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:34:21.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:34:21.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:34:21.65#ibcon#enter wrdev, iclass 23, count 0 2006.285.11:34:21.65#ibcon#first serial, iclass 23, count 0 2006.285.11:34:21.65#ibcon#enter sib2, iclass 23, count 0 2006.285.11:34:21.65#ibcon#flushed, iclass 23, count 0 2006.285.11:34:21.65#ibcon#about to write, iclass 23, count 0 2006.285.11:34:21.65#ibcon#wrote, iclass 23, count 0 2006.285.11:34:21.65#ibcon#about to read 3, iclass 23, count 0 2006.285.11:34:21.67#ibcon#read 3, iclass 23, count 0 2006.285.11:34:21.67#ibcon#about to read 4, iclass 23, count 0 2006.285.11:34:21.67#ibcon#read 4, iclass 23, count 0 2006.285.11:34:21.67#ibcon#about to read 5, iclass 23, count 0 2006.285.11:34:21.67#ibcon#read 5, iclass 23, count 0 2006.285.11:34:21.67#ibcon#about to read 6, iclass 23, count 0 2006.285.11:34:21.67#ibcon#read 6, iclass 23, count 0 2006.285.11:34:21.67#ibcon#end of sib2, iclass 23, count 0 2006.285.11:34:21.67#ibcon#*mode == 0, iclass 23, count 0 2006.285.11:34:21.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.11:34:21.67#ibcon#[27=USB\r\n] 2006.285.11:34:21.67#ibcon#*before write, iclass 23, count 0 2006.285.11:34:21.67#ibcon#enter sib2, iclass 23, count 0 2006.285.11:34:21.67#ibcon#flushed, iclass 23, count 0 2006.285.11:34:21.67#ibcon#about to write, iclass 23, count 0 2006.285.11:34:21.67#ibcon#wrote, iclass 23, count 0 2006.285.11:34:21.67#ibcon#about to read 3, iclass 23, count 0 2006.285.11:34:21.70#ibcon#read 3, iclass 23, count 0 2006.285.11:34:21.70#ibcon#about to read 4, iclass 23, count 0 2006.285.11:34:21.70#ibcon#read 4, iclass 23, count 0 2006.285.11:34:21.70#ibcon#about to read 5, iclass 23, count 0 2006.285.11:34:21.70#ibcon#read 5, iclass 23, count 0 2006.285.11:34:21.70#ibcon#about to read 6, iclass 23, count 0 2006.285.11:34:21.70#ibcon#read 6, iclass 23, count 0 2006.285.11:34:21.70#ibcon#end of sib2, iclass 23, count 0 2006.285.11:34:21.70#ibcon#*after write, iclass 23, count 0 2006.285.11:34:21.70#ibcon#*before return 0, iclass 23, count 0 2006.285.11:34:21.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:34:21.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:34:21.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.11:34:21.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.11:34:21.70$vck44/vblo=2,634.99 2006.285.11:34:21.70#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.11:34:21.70#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.11:34:21.70#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:21.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:34:21.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:34:21.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:34:21.70#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:34:21.70#ibcon#first serial, iclass 25, count 0 2006.285.11:34:21.70#ibcon#enter sib2, iclass 25, count 0 2006.285.11:34:21.70#ibcon#flushed, iclass 25, count 0 2006.285.11:34:21.70#ibcon#about to write, iclass 25, count 0 2006.285.11:34:21.70#ibcon#wrote, iclass 25, count 0 2006.285.11:34:21.70#ibcon#about to read 3, iclass 25, count 0 2006.285.11:34:21.72#ibcon#read 3, iclass 25, count 0 2006.285.11:34:21.72#ibcon#about to read 4, iclass 25, count 0 2006.285.11:34:21.72#ibcon#read 4, iclass 25, count 0 2006.285.11:34:21.72#ibcon#about to read 5, iclass 25, count 0 2006.285.11:34:21.72#ibcon#read 5, iclass 25, count 0 2006.285.11:34:21.72#ibcon#about to read 6, iclass 25, count 0 2006.285.11:34:21.72#ibcon#read 6, iclass 25, count 0 2006.285.11:34:21.72#ibcon#end of sib2, iclass 25, count 0 2006.285.11:34:21.72#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:34:21.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:34:21.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:34:21.72#ibcon#*before write, iclass 25, count 0 2006.285.11:34:21.72#ibcon#enter sib2, iclass 25, count 0 2006.285.11:34:21.72#ibcon#flushed, iclass 25, count 0 2006.285.11:34:21.72#ibcon#about to write, iclass 25, count 0 2006.285.11:34:21.72#ibcon#wrote, iclass 25, count 0 2006.285.11:34:21.72#ibcon#about to read 3, iclass 25, count 0 2006.285.11:34:21.76#ibcon#read 3, iclass 25, count 0 2006.285.11:34:21.76#ibcon#about to read 4, iclass 25, count 0 2006.285.11:34:21.76#ibcon#read 4, iclass 25, count 0 2006.285.11:34:21.76#ibcon#about to read 5, iclass 25, count 0 2006.285.11:34:21.76#ibcon#read 5, iclass 25, count 0 2006.285.11:34:21.76#ibcon#about to read 6, iclass 25, count 0 2006.285.11:34:21.76#ibcon#read 6, iclass 25, count 0 2006.285.11:34:21.76#ibcon#end of sib2, iclass 25, count 0 2006.285.11:34:21.76#ibcon#*after write, iclass 25, count 0 2006.285.11:34:21.76#ibcon#*before return 0, iclass 25, count 0 2006.285.11:34:21.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:34:21.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:34:21.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:34:21.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:34:21.76$vck44/vb=2,5 2006.285.11:34:21.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.11:34:21.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.11:34:21.76#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:21.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:34:21.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:34:21.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:34:21.82#ibcon#enter wrdev, iclass 27, count 2 2006.285.11:34:21.82#ibcon#first serial, iclass 27, count 2 2006.285.11:34:21.82#ibcon#enter sib2, iclass 27, count 2 2006.285.11:34:21.82#ibcon#flushed, iclass 27, count 2 2006.285.11:34:21.82#ibcon#about to write, iclass 27, count 2 2006.285.11:34:21.82#ibcon#wrote, iclass 27, count 2 2006.285.11:34:21.82#ibcon#about to read 3, iclass 27, count 2 2006.285.11:34:21.84#ibcon#read 3, iclass 27, count 2 2006.285.11:34:21.84#ibcon#about to read 4, iclass 27, count 2 2006.285.11:34:21.84#ibcon#read 4, iclass 27, count 2 2006.285.11:34:21.84#ibcon#about to read 5, iclass 27, count 2 2006.285.11:34:21.84#ibcon#read 5, iclass 27, count 2 2006.285.11:34:21.84#ibcon#about to read 6, iclass 27, count 2 2006.285.11:34:21.84#ibcon#read 6, iclass 27, count 2 2006.285.11:34:21.84#ibcon#end of sib2, iclass 27, count 2 2006.285.11:34:21.84#ibcon#*mode == 0, iclass 27, count 2 2006.285.11:34:21.84#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.11:34:21.84#ibcon#[27=AT02-05\r\n] 2006.285.11:34:21.84#ibcon#*before write, iclass 27, count 2 2006.285.11:34:21.84#ibcon#enter sib2, iclass 27, count 2 2006.285.11:34:21.84#ibcon#flushed, iclass 27, count 2 2006.285.11:34:21.84#ibcon#about to write, iclass 27, count 2 2006.285.11:34:21.84#ibcon#wrote, iclass 27, count 2 2006.285.11:34:21.84#ibcon#about to read 3, iclass 27, count 2 2006.285.11:34:21.87#ibcon#read 3, iclass 27, count 2 2006.285.11:34:21.87#ibcon#about to read 4, iclass 27, count 2 2006.285.11:34:21.87#ibcon#read 4, iclass 27, count 2 2006.285.11:34:21.87#ibcon#about to read 5, iclass 27, count 2 2006.285.11:34:21.87#ibcon#read 5, iclass 27, count 2 2006.285.11:34:21.87#ibcon#about to read 6, iclass 27, count 2 2006.285.11:34:21.87#ibcon#read 6, iclass 27, count 2 2006.285.11:34:21.87#ibcon#end of sib2, iclass 27, count 2 2006.285.11:34:21.87#ibcon#*after write, iclass 27, count 2 2006.285.11:34:21.87#ibcon#*before return 0, iclass 27, count 2 2006.285.11:34:21.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:34:21.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:34:21.87#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.11:34:21.87#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:21.87#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:34:21.99#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:34:21.99#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:34:21.99#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:34:21.99#ibcon#first serial, iclass 27, count 0 2006.285.11:34:21.99#ibcon#enter sib2, iclass 27, count 0 2006.285.11:34:21.99#ibcon#flushed, iclass 27, count 0 2006.285.11:34:21.99#ibcon#about to write, iclass 27, count 0 2006.285.11:34:21.99#ibcon#wrote, iclass 27, count 0 2006.285.11:34:21.99#ibcon#about to read 3, iclass 27, count 0 2006.285.11:34:22.01#ibcon#read 3, iclass 27, count 0 2006.285.11:34:22.01#ibcon#about to read 4, iclass 27, count 0 2006.285.11:34:22.01#ibcon#read 4, iclass 27, count 0 2006.285.11:34:22.01#ibcon#about to read 5, iclass 27, count 0 2006.285.11:34:22.01#ibcon#read 5, iclass 27, count 0 2006.285.11:34:22.01#ibcon#about to read 6, iclass 27, count 0 2006.285.11:34:22.01#ibcon#read 6, iclass 27, count 0 2006.285.11:34:22.01#ibcon#end of sib2, iclass 27, count 0 2006.285.11:34:22.01#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:34:22.01#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:34:22.01#ibcon#[27=USB\r\n] 2006.285.11:34:22.01#ibcon#*before write, iclass 27, count 0 2006.285.11:34:22.01#ibcon#enter sib2, iclass 27, count 0 2006.285.11:34:22.01#ibcon#flushed, iclass 27, count 0 2006.285.11:34:22.01#ibcon#about to write, iclass 27, count 0 2006.285.11:34:22.01#ibcon#wrote, iclass 27, count 0 2006.285.11:34:22.01#ibcon#about to read 3, iclass 27, count 0 2006.285.11:34:22.04#ibcon#read 3, iclass 27, count 0 2006.285.11:34:22.04#ibcon#about to read 4, iclass 27, count 0 2006.285.11:34:22.04#ibcon#read 4, iclass 27, count 0 2006.285.11:34:22.04#ibcon#about to read 5, iclass 27, count 0 2006.285.11:34:22.04#ibcon#read 5, iclass 27, count 0 2006.285.11:34:22.04#ibcon#about to read 6, iclass 27, count 0 2006.285.11:34:22.04#ibcon#read 6, iclass 27, count 0 2006.285.11:34:22.04#ibcon#end of sib2, iclass 27, count 0 2006.285.11:34:22.04#ibcon#*after write, iclass 27, count 0 2006.285.11:34:22.04#ibcon#*before return 0, iclass 27, count 0 2006.285.11:34:22.04#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:34:22.04#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:34:22.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:34:22.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:34:22.04$vck44/vblo=3,649.99 2006.285.11:34:22.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.11:34:22.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.11:34:22.04#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:22.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:34:22.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:34:22.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:34:22.04#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:34:22.04#ibcon#first serial, iclass 29, count 0 2006.285.11:34:22.04#ibcon#enter sib2, iclass 29, count 0 2006.285.11:34:22.04#ibcon#flushed, iclass 29, count 0 2006.285.11:34:22.04#ibcon#about to write, iclass 29, count 0 2006.285.11:34:22.04#ibcon#wrote, iclass 29, count 0 2006.285.11:34:22.04#ibcon#about to read 3, iclass 29, count 0 2006.285.11:34:22.06#ibcon#read 3, iclass 29, count 0 2006.285.11:34:22.06#ibcon#about to read 4, iclass 29, count 0 2006.285.11:34:22.06#ibcon#read 4, iclass 29, count 0 2006.285.11:34:22.06#ibcon#about to read 5, iclass 29, count 0 2006.285.11:34:22.06#ibcon#read 5, iclass 29, count 0 2006.285.11:34:22.06#ibcon#about to read 6, iclass 29, count 0 2006.285.11:34:22.06#ibcon#read 6, iclass 29, count 0 2006.285.11:34:22.06#ibcon#end of sib2, iclass 29, count 0 2006.285.11:34:22.06#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:34:22.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:34:22.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:34:22.06#ibcon#*before write, iclass 29, count 0 2006.285.11:34:22.06#ibcon#enter sib2, iclass 29, count 0 2006.285.11:34:22.06#ibcon#flushed, iclass 29, count 0 2006.285.11:34:22.06#ibcon#about to write, iclass 29, count 0 2006.285.11:34:22.06#ibcon#wrote, iclass 29, count 0 2006.285.11:34:22.06#ibcon#about to read 3, iclass 29, count 0 2006.285.11:34:22.10#ibcon#read 3, iclass 29, count 0 2006.285.11:34:22.10#ibcon#about to read 4, iclass 29, count 0 2006.285.11:34:22.10#ibcon#read 4, iclass 29, count 0 2006.285.11:34:22.10#ibcon#about to read 5, iclass 29, count 0 2006.285.11:34:22.10#ibcon#read 5, iclass 29, count 0 2006.285.11:34:22.10#ibcon#about to read 6, iclass 29, count 0 2006.285.11:34:22.10#ibcon#read 6, iclass 29, count 0 2006.285.11:34:22.10#ibcon#end of sib2, iclass 29, count 0 2006.285.11:34:22.10#ibcon#*after write, iclass 29, count 0 2006.285.11:34:22.10#ibcon#*before return 0, iclass 29, count 0 2006.285.11:34:22.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:34:22.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:34:22.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:34:22.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:34:22.10$vck44/vb=3,4 2006.285.11:34:22.10#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.11:34:22.10#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.11:34:22.10#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:22.10#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:34:22.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:34:22.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:34:22.16#ibcon#enter wrdev, iclass 31, count 2 2006.285.11:34:22.16#ibcon#first serial, iclass 31, count 2 2006.285.11:34:22.16#ibcon#enter sib2, iclass 31, count 2 2006.285.11:34:22.16#ibcon#flushed, iclass 31, count 2 2006.285.11:34:22.16#ibcon#about to write, iclass 31, count 2 2006.285.11:34:22.16#ibcon#wrote, iclass 31, count 2 2006.285.11:34:22.16#ibcon#about to read 3, iclass 31, count 2 2006.285.11:34:22.18#ibcon#read 3, iclass 31, count 2 2006.285.11:34:22.18#ibcon#about to read 4, iclass 31, count 2 2006.285.11:34:22.18#ibcon#read 4, iclass 31, count 2 2006.285.11:34:22.18#ibcon#about to read 5, iclass 31, count 2 2006.285.11:34:22.18#ibcon#read 5, iclass 31, count 2 2006.285.11:34:22.18#ibcon#about to read 6, iclass 31, count 2 2006.285.11:34:22.18#ibcon#read 6, iclass 31, count 2 2006.285.11:34:22.18#ibcon#end of sib2, iclass 31, count 2 2006.285.11:34:22.18#ibcon#*mode == 0, iclass 31, count 2 2006.285.11:34:22.18#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.11:34:22.18#ibcon#[27=AT03-04\r\n] 2006.285.11:34:22.18#ibcon#*before write, iclass 31, count 2 2006.285.11:34:22.18#ibcon#enter sib2, iclass 31, count 2 2006.285.11:34:22.18#ibcon#flushed, iclass 31, count 2 2006.285.11:34:22.18#ibcon#about to write, iclass 31, count 2 2006.285.11:34:22.18#ibcon#wrote, iclass 31, count 2 2006.285.11:34:22.18#ibcon#about to read 3, iclass 31, count 2 2006.285.11:34:22.21#ibcon#read 3, iclass 31, count 2 2006.285.11:34:22.21#ibcon#about to read 4, iclass 31, count 2 2006.285.11:34:22.21#ibcon#read 4, iclass 31, count 2 2006.285.11:34:22.21#ibcon#about to read 5, iclass 31, count 2 2006.285.11:34:22.21#ibcon#read 5, iclass 31, count 2 2006.285.11:34:22.21#ibcon#about to read 6, iclass 31, count 2 2006.285.11:34:22.21#ibcon#read 6, iclass 31, count 2 2006.285.11:34:22.21#ibcon#end of sib2, iclass 31, count 2 2006.285.11:34:22.21#ibcon#*after write, iclass 31, count 2 2006.285.11:34:22.21#ibcon#*before return 0, iclass 31, count 2 2006.285.11:34:22.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:34:22.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:34:22.21#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.11:34:22.21#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:22.21#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:34:22.33#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:34:22.33#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:34:22.33#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:34:22.33#ibcon#first serial, iclass 31, count 0 2006.285.11:34:22.33#ibcon#enter sib2, iclass 31, count 0 2006.285.11:34:22.33#ibcon#flushed, iclass 31, count 0 2006.285.11:34:22.33#ibcon#about to write, iclass 31, count 0 2006.285.11:34:22.33#ibcon#wrote, iclass 31, count 0 2006.285.11:34:22.33#ibcon#about to read 3, iclass 31, count 0 2006.285.11:34:22.35#ibcon#read 3, iclass 31, count 0 2006.285.11:34:22.35#ibcon#about to read 4, iclass 31, count 0 2006.285.11:34:22.35#ibcon#read 4, iclass 31, count 0 2006.285.11:34:22.35#ibcon#about to read 5, iclass 31, count 0 2006.285.11:34:22.35#ibcon#read 5, iclass 31, count 0 2006.285.11:34:22.35#ibcon#about to read 6, iclass 31, count 0 2006.285.11:34:22.35#ibcon#read 6, iclass 31, count 0 2006.285.11:34:22.35#ibcon#end of sib2, iclass 31, count 0 2006.285.11:34:22.35#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:34:22.35#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:34:22.35#ibcon#[27=USB\r\n] 2006.285.11:34:22.35#ibcon#*before write, iclass 31, count 0 2006.285.11:34:22.35#ibcon#enter sib2, iclass 31, count 0 2006.285.11:34:22.35#ibcon#flushed, iclass 31, count 0 2006.285.11:34:22.35#ibcon#about to write, iclass 31, count 0 2006.285.11:34:22.35#ibcon#wrote, iclass 31, count 0 2006.285.11:34:22.35#ibcon#about to read 3, iclass 31, count 0 2006.285.11:34:22.38#ibcon#read 3, iclass 31, count 0 2006.285.11:34:22.38#ibcon#about to read 4, iclass 31, count 0 2006.285.11:34:22.38#ibcon#read 4, iclass 31, count 0 2006.285.11:34:22.38#ibcon#about to read 5, iclass 31, count 0 2006.285.11:34:22.38#ibcon#read 5, iclass 31, count 0 2006.285.11:34:22.38#ibcon#about to read 6, iclass 31, count 0 2006.285.11:34:22.38#ibcon#read 6, iclass 31, count 0 2006.285.11:34:22.38#ibcon#end of sib2, iclass 31, count 0 2006.285.11:34:22.38#ibcon#*after write, iclass 31, count 0 2006.285.11:34:22.38#ibcon#*before return 0, iclass 31, count 0 2006.285.11:34:22.38#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:34:22.38#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:34:22.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:34:22.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:34:22.38$vck44/vblo=4,679.99 2006.285.11:34:22.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.11:34:22.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.11:34:22.38#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:22.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:34:22.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:34:22.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:34:22.38#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:34:22.38#ibcon#first serial, iclass 33, count 0 2006.285.11:34:22.38#ibcon#enter sib2, iclass 33, count 0 2006.285.11:34:22.38#ibcon#flushed, iclass 33, count 0 2006.285.11:34:22.38#ibcon#about to write, iclass 33, count 0 2006.285.11:34:22.38#ibcon#wrote, iclass 33, count 0 2006.285.11:34:22.38#ibcon#about to read 3, iclass 33, count 0 2006.285.11:34:22.40#ibcon#read 3, iclass 33, count 0 2006.285.11:34:22.40#ibcon#about to read 4, iclass 33, count 0 2006.285.11:34:22.40#ibcon#read 4, iclass 33, count 0 2006.285.11:34:22.40#ibcon#about to read 5, iclass 33, count 0 2006.285.11:34:22.40#ibcon#read 5, iclass 33, count 0 2006.285.11:34:22.40#ibcon#about to read 6, iclass 33, count 0 2006.285.11:34:22.40#ibcon#read 6, iclass 33, count 0 2006.285.11:34:22.40#ibcon#end of sib2, iclass 33, count 0 2006.285.11:34:22.40#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:34:22.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:34:22.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:34:22.40#ibcon#*before write, iclass 33, count 0 2006.285.11:34:22.40#ibcon#enter sib2, iclass 33, count 0 2006.285.11:34:22.40#ibcon#flushed, iclass 33, count 0 2006.285.11:34:22.40#ibcon#about to write, iclass 33, count 0 2006.285.11:34:22.40#ibcon#wrote, iclass 33, count 0 2006.285.11:34:22.40#ibcon#about to read 3, iclass 33, count 0 2006.285.11:34:22.44#ibcon#read 3, iclass 33, count 0 2006.285.11:34:22.44#ibcon#about to read 4, iclass 33, count 0 2006.285.11:34:22.44#ibcon#read 4, iclass 33, count 0 2006.285.11:34:22.44#ibcon#about to read 5, iclass 33, count 0 2006.285.11:34:22.44#ibcon#read 5, iclass 33, count 0 2006.285.11:34:22.44#ibcon#about to read 6, iclass 33, count 0 2006.285.11:34:22.44#ibcon#read 6, iclass 33, count 0 2006.285.11:34:22.44#ibcon#end of sib2, iclass 33, count 0 2006.285.11:34:22.44#ibcon#*after write, iclass 33, count 0 2006.285.11:34:22.44#ibcon#*before return 0, iclass 33, count 0 2006.285.11:34:22.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:34:22.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:34:22.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:34:22.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:34:22.44$vck44/vb=4,5 2006.285.11:34:22.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.11:34:22.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.11:34:22.44#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:22.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:34:22.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:34:22.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:34:22.50#ibcon#enter wrdev, iclass 35, count 2 2006.285.11:34:22.50#ibcon#first serial, iclass 35, count 2 2006.285.11:34:22.50#ibcon#enter sib2, iclass 35, count 2 2006.285.11:34:22.50#ibcon#flushed, iclass 35, count 2 2006.285.11:34:22.50#ibcon#about to write, iclass 35, count 2 2006.285.11:34:22.50#ibcon#wrote, iclass 35, count 2 2006.285.11:34:22.50#ibcon#about to read 3, iclass 35, count 2 2006.285.11:34:22.52#ibcon#read 3, iclass 35, count 2 2006.285.11:34:22.52#ibcon#about to read 4, iclass 35, count 2 2006.285.11:34:22.52#ibcon#read 4, iclass 35, count 2 2006.285.11:34:22.52#ibcon#about to read 5, iclass 35, count 2 2006.285.11:34:22.52#ibcon#read 5, iclass 35, count 2 2006.285.11:34:22.52#ibcon#about to read 6, iclass 35, count 2 2006.285.11:34:22.52#ibcon#read 6, iclass 35, count 2 2006.285.11:34:22.52#ibcon#end of sib2, iclass 35, count 2 2006.285.11:34:22.52#ibcon#*mode == 0, iclass 35, count 2 2006.285.11:34:22.52#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.11:34:22.52#ibcon#[27=AT04-05\r\n] 2006.285.11:34:22.52#ibcon#*before write, iclass 35, count 2 2006.285.11:34:22.52#ibcon#enter sib2, iclass 35, count 2 2006.285.11:34:22.52#ibcon#flushed, iclass 35, count 2 2006.285.11:34:22.52#ibcon#about to write, iclass 35, count 2 2006.285.11:34:22.52#ibcon#wrote, iclass 35, count 2 2006.285.11:34:22.52#ibcon#about to read 3, iclass 35, count 2 2006.285.11:34:22.55#ibcon#read 3, iclass 35, count 2 2006.285.11:34:22.55#ibcon#about to read 4, iclass 35, count 2 2006.285.11:34:22.55#ibcon#read 4, iclass 35, count 2 2006.285.11:34:22.55#ibcon#about to read 5, iclass 35, count 2 2006.285.11:34:22.55#ibcon#read 5, iclass 35, count 2 2006.285.11:34:22.55#ibcon#about to read 6, iclass 35, count 2 2006.285.11:34:22.55#ibcon#read 6, iclass 35, count 2 2006.285.11:34:22.55#ibcon#end of sib2, iclass 35, count 2 2006.285.11:34:22.55#ibcon#*after write, iclass 35, count 2 2006.285.11:34:22.55#ibcon#*before return 0, iclass 35, count 2 2006.285.11:34:22.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:34:22.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:34:22.55#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.11:34:22.55#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:22.55#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:34:22.67#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:34:22.67#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:34:22.67#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:34:22.67#ibcon#first serial, iclass 35, count 0 2006.285.11:34:22.67#ibcon#enter sib2, iclass 35, count 0 2006.285.11:34:22.67#ibcon#flushed, iclass 35, count 0 2006.285.11:34:22.67#ibcon#about to write, iclass 35, count 0 2006.285.11:34:22.67#ibcon#wrote, iclass 35, count 0 2006.285.11:34:22.67#ibcon#about to read 3, iclass 35, count 0 2006.285.11:34:22.69#ibcon#read 3, iclass 35, count 0 2006.285.11:34:22.69#ibcon#about to read 4, iclass 35, count 0 2006.285.11:34:22.69#ibcon#read 4, iclass 35, count 0 2006.285.11:34:22.69#ibcon#about to read 5, iclass 35, count 0 2006.285.11:34:22.69#ibcon#read 5, iclass 35, count 0 2006.285.11:34:22.69#ibcon#about to read 6, iclass 35, count 0 2006.285.11:34:22.69#ibcon#read 6, iclass 35, count 0 2006.285.11:34:22.69#ibcon#end of sib2, iclass 35, count 0 2006.285.11:34:22.69#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:34:22.69#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:34:22.69#ibcon#[27=USB\r\n] 2006.285.11:34:22.69#ibcon#*before write, iclass 35, count 0 2006.285.11:34:22.69#ibcon#enter sib2, iclass 35, count 0 2006.285.11:34:22.69#ibcon#flushed, iclass 35, count 0 2006.285.11:34:22.69#ibcon#about to write, iclass 35, count 0 2006.285.11:34:22.69#ibcon#wrote, iclass 35, count 0 2006.285.11:34:22.69#ibcon#about to read 3, iclass 35, count 0 2006.285.11:34:22.72#ibcon#read 3, iclass 35, count 0 2006.285.11:34:22.72#ibcon#about to read 4, iclass 35, count 0 2006.285.11:34:22.72#ibcon#read 4, iclass 35, count 0 2006.285.11:34:22.72#ibcon#about to read 5, iclass 35, count 0 2006.285.11:34:22.72#ibcon#read 5, iclass 35, count 0 2006.285.11:34:22.72#ibcon#about to read 6, iclass 35, count 0 2006.285.11:34:22.72#ibcon#read 6, iclass 35, count 0 2006.285.11:34:22.72#ibcon#end of sib2, iclass 35, count 0 2006.285.11:34:22.72#ibcon#*after write, iclass 35, count 0 2006.285.11:34:22.72#ibcon#*before return 0, iclass 35, count 0 2006.285.11:34:22.72#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:34:22.72#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:34:22.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:34:22.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:34:22.72$vck44/vblo=5,709.99 2006.285.11:34:22.72#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.11:34:22.72#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.11:34:22.72#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:22.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:34:22.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:34:22.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:34:22.72#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:34:22.72#ibcon#first serial, iclass 37, count 0 2006.285.11:34:22.72#ibcon#enter sib2, iclass 37, count 0 2006.285.11:34:22.72#ibcon#flushed, iclass 37, count 0 2006.285.11:34:22.72#ibcon#about to write, iclass 37, count 0 2006.285.11:34:22.72#ibcon#wrote, iclass 37, count 0 2006.285.11:34:22.72#ibcon#about to read 3, iclass 37, count 0 2006.285.11:34:22.74#ibcon#read 3, iclass 37, count 0 2006.285.11:34:22.74#ibcon#about to read 4, iclass 37, count 0 2006.285.11:34:22.74#ibcon#read 4, iclass 37, count 0 2006.285.11:34:22.74#ibcon#about to read 5, iclass 37, count 0 2006.285.11:34:22.74#ibcon#read 5, iclass 37, count 0 2006.285.11:34:22.74#ibcon#about to read 6, iclass 37, count 0 2006.285.11:34:22.74#ibcon#read 6, iclass 37, count 0 2006.285.11:34:22.74#ibcon#end of sib2, iclass 37, count 0 2006.285.11:34:22.74#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:34:22.74#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:34:22.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:34:22.74#ibcon#*before write, iclass 37, count 0 2006.285.11:34:22.74#ibcon#enter sib2, iclass 37, count 0 2006.285.11:34:22.74#ibcon#flushed, iclass 37, count 0 2006.285.11:34:22.74#ibcon#about to write, iclass 37, count 0 2006.285.11:34:22.74#ibcon#wrote, iclass 37, count 0 2006.285.11:34:22.74#ibcon#about to read 3, iclass 37, count 0 2006.285.11:34:22.78#ibcon#read 3, iclass 37, count 0 2006.285.11:34:22.78#ibcon#about to read 4, iclass 37, count 0 2006.285.11:34:22.78#ibcon#read 4, iclass 37, count 0 2006.285.11:34:22.78#ibcon#about to read 5, iclass 37, count 0 2006.285.11:34:22.78#ibcon#read 5, iclass 37, count 0 2006.285.11:34:22.78#ibcon#about to read 6, iclass 37, count 0 2006.285.11:34:22.78#ibcon#read 6, iclass 37, count 0 2006.285.11:34:22.78#ibcon#end of sib2, iclass 37, count 0 2006.285.11:34:22.78#ibcon#*after write, iclass 37, count 0 2006.285.11:34:22.78#ibcon#*before return 0, iclass 37, count 0 2006.285.11:34:22.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:34:22.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:34:22.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:34:22.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:34:22.78$vck44/vb=5,4 2006.285.11:34:22.78#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.11:34:22.78#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.11:34:22.78#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:22.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:34:22.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:34:22.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:34:22.84#ibcon#enter wrdev, iclass 39, count 2 2006.285.11:34:22.84#ibcon#first serial, iclass 39, count 2 2006.285.11:34:22.84#ibcon#enter sib2, iclass 39, count 2 2006.285.11:34:22.84#ibcon#flushed, iclass 39, count 2 2006.285.11:34:22.84#ibcon#about to write, iclass 39, count 2 2006.285.11:34:22.84#ibcon#wrote, iclass 39, count 2 2006.285.11:34:22.84#ibcon#about to read 3, iclass 39, count 2 2006.285.11:34:22.86#ibcon#read 3, iclass 39, count 2 2006.285.11:34:22.86#ibcon#about to read 4, iclass 39, count 2 2006.285.11:34:22.86#ibcon#read 4, iclass 39, count 2 2006.285.11:34:22.86#ibcon#about to read 5, iclass 39, count 2 2006.285.11:34:22.86#ibcon#read 5, iclass 39, count 2 2006.285.11:34:22.86#ibcon#about to read 6, iclass 39, count 2 2006.285.11:34:22.86#ibcon#read 6, iclass 39, count 2 2006.285.11:34:22.86#ibcon#end of sib2, iclass 39, count 2 2006.285.11:34:22.86#ibcon#*mode == 0, iclass 39, count 2 2006.285.11:34:22.86#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.11:34:22.86#ibcon#[27=AT05-04\r\n] 2006.285.11:34:22.86#ibcon#*before write, iclass 39, count 2 2006.285.11:34:22.86#ibcon#enter sib2, iclass 39, count 2 2006.285.11:34:22.86#ibcon#flushed, iclass 39, count 2 2006.285.11:34:22.86#ibcon#about to write, iclass 39, count 2 2006.285.11:34:22.86#ibcon#wrote, iclass 39, count 2 2006.285.11:34:22.86#ibcon#about to read 3, iclass 39, count 2 2006.285.11:34:22.89#ibcon#read 3, iclass 39, count 2 2006.285.11:34:22.89#ibcon#about to read 4, iclass 39, count 2 2006.285.11:34:22.89#ibcon#read 4, iclass 39, count 2 2006.285.11:34:22.89#ibcon#about to read 5, iclass 39, count 2 2006.285.11:34:22.89#ibcon#read 5, iclass 39, count 2 2006.285.11:34:22.89#ibcon#about to read 6, iclass 39, count 2 2006.285.11:34:22.89#ibcon#read 6, iclass 39, count 2 2006.285.11:34:22.89#ibcon#end of sib2, iclass 39, count 2 2006.285.11:34:22.89#ibcon#*after write, iclass 39, count 2 2006.285.11:34:22.89#ibcon#*before return 0, iclass 39, count 2 2006.285.11:34:22.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:34:22.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:34:22.89#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.11:34:22.89#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:22.89#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:34:23.01#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:34:23.01#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:34:23.01#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:34:23.01#ibcon#first serial, iclass 39, count 0 2006.285.11:34:23.01#ibcon#enter sib2, iclass 39, count 0 2006.285.11:34:23.01#ibcon#flushed, iclass 39, count 0 2006.285.11:34:23.01#ibcon#about to write, iclass 39, count 0 2006.285.11:34:23.01#ibcon#wrote, iclass 39, count 0 2006.285.11:34:23.01#ibcon#about to read 3, iclass 39, count 0 2006.285.11:34:23.03#ibcon#read 3, iclass 39, count 0 2006.285.11:34:23.03#ibcon#about to read 4, iclass 39, count 0 2006.285.11:34:23.03#ibcon#read 4, iclass 39, count 0 2006.285.11:34:23.03#ibcon#about to read 5, iclass 39, count 0 2006.285.11:34:23.03#ibcon#read 5, iclass 39, count 0 2006.285.11:34:23.03#ibcon#about to read 6, iclass 39, count 0 2006.285.11:34:23.03#ibcon#read 6, iclass 39, count 0 2006.285.11:34:23.03#ibcon#end of sib2, iclass 39, count 0 2006.285.11:34:23.03#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:34:23.03#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:34:23.03#ibcon#[27=USB\r\n] 2006.285.11:34:23.03#ibcon#*before write, iclass 39, count 0 2006.285.11:34:23.03#ibcon#enter sib2, iclass 39, count 0 2006.285.11:34:23.03#ibcon#flushed, iclass 39, count 0 2006.285.11:34:23.03#ibcon#about to write, iclass 39, count 0 2006.285.11:34:23.03#ibcon#wrote, iclass 39, count 0 2006.285.11:34:23.03#ibcon#about to read 3, iclass 39, count 0 2006.285.11:34:23.06#ibcon#read 3, iclass 39, count 0 2006.285.11:34:23.06#ibcon#about to read 4, iclass 39, count 0 2006.285.11:34:23.06#ibcon#read 4, iclass 39, count 0 2006.285.11:34:23.06#ibcon#about to read 5, iclass 39, count 0 2006.285.11:34:23.06#ibcon#read 5, iclass 39, count 0 2006.285.11:34:23.06#ibcon#about to read 6, iclass 39, count 0 2006.285.11:34:23.06#ibcon#read 6, iclass 39, count 0 2006.285.11:34:23.06#ibcon#end of sib2, iclass 39, count 0 2006.285.11:34:23.06#ibcon#*after write, iclass 39, count 0 2006.285.11:34:23.06#ibcon#*before return 0, iclass 39, count 0 2006.285.11:34:23.06#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:34:23.06#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:34:23.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:34:23.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:34:23.06$vck44/vblo=6,719.99 2006.285.11:34:23.06#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.11:34:23.06#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.11:34:23.06#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:23.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:34:23.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:34:23.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:34:23.06#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:34:23.06#ibcon#first serial, iclass 3, count 0 2006.285.11:34:23.06#ibcon#enter sib2, iclass 3, count 0 2006.285.11:34:23.06#ibcon#flushed, iclass 3, count 0 2006.285.11:34:23.06#ibcon#about to write, iclass 3, count 0 2006.285.11:34:23.06#ibcon#wrote, iclass 3, count 0 2006.285.11:34:23.06#ibcon#about to read 3, iclass 3, count 0 2006.285.11:34:23.08#ibcon#read 3, iclass 3, count 0 2006.285.11:34:23.08#ibcon#about to read 4, iclass 3, count 0 2006.285.11:34:23.08#ibcon#read 4, iclass 3, count 0 2006.285.11:34:23.08#ibcon#about to read 5, iclass 3, count 0 2006.285.11:34:23.08#ibcon#read 5, iclass 3, count 0 2006.285.11:34:23.08#ibcon#about to read 6, iclass 3, count 0 2006.285.11:34:23.08#ibcon#read 6, iclass 3, count 0 2006.285.11:34:23.08#ibcon#end of sib2, iclass 3, count 0 2006.285.11:34:23.08#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:34:23.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:34:23.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:34:23.08#ibcon#*before write, iclass 3, count 0 2006.285.11:34:23.08#ibcon#enter sib2, iclass 3, count 0 2006.285.11:34:23.08#ibcon#flushed, iclass 3, count 0 2006.285.11:34:23.08#ibcon#about to write, iclass 3, count 0 2006.285.11:34:23.08#ibcon#wrote, iclass 3, count 0 2006.285.11:34:23.08#ibcon#about to read 3, iclass 3, count 0 2006.285.11:34:23.12#ibcon#read 3, iclass 3, count 0 2006.285.11:34:23.12#ibcon#about to read 4, iclass 3, count 0 2006.285.11:34:23.12#ibcon#read 4, iclass 3, count 0 2006.285.11:34:23.12#ibcon#about to read 5, iclass 3, count 0 2006.285.11:34:23.12#ibcon#read 5, iclass 3, count 0 2006.285.11:34:23.12#ibcon#about to read 6, iclass 3, count 0 2006.285.11:34:23.12#ibcon#read 6, iclass 3, count 0 2006.285.11:34:23.12#ibcon#end of sib2, iclass 3, count 0 2006.285.11:34:23.12#ibcon#*after write, iclass 3, count 0 2006.285.11:34:23.12#ibcon#*before return 0, iclass 3, count 0 2006.285.11:34:23.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:34:23.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:34:23.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:34:23.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:34:23.12$vck44/vb=6,3 2006.285.11:34:23.12#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.11:34:23.12#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.11:34:23.12#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:23.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:34:23.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:34:23.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:34:23.18#ibcon#enter wrdev, iclass 5, count 2 2006.285.11:34:23.18#ibcon#first serial, iclass 5, count 2 2006.285.11:34:23.18#ibcon#enter sib2, iclass 5, count 2 2006.285.11:34:23.18#ibcon#flushed, iclass 5, count 2 2006.285.11:34:23.18#ibcon#about to write, iclass 5, count 2 2006.285.11:34:23.18#ibcon#wrote, iclass 5, count 2 2006.285.11:34:23.18#ibcon#about to read 3, iclass 5, count 2 2006.285.11:34:23.20#ibcon#read 3, iclass 5, count 2 2006.285.11:34:23.20#ibcon#about to read 4, iclass 5, count 2 2006.285.11:34:23.20#ibcon#read 4, iclass 5, count 2 2006.285.11:34:23.20#ibcon#about to read 5, iclass 5, count 2 2006.285.11:34:23.20#ibcon#read 5, iclass 5, count 2 2006.285.11:34:23.20#ibcon#about to read 6, iclass 5, count 2 2006.285.11:34:23.20#ibcon#read 6, iclass 5, count 2 2006.285.11:34:23.20#ibcon#end of sib2, iclass 5, count 2 2006.285.11:34:23.20#ibcon#*mode == 0, iclass 5, count 2 2006.285.11:34:23.20#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.11:34:23.20#ibcon#[27=AT06-03\r\n] 2006.285.11:34:23.20#ibcon#*before write, iclass 5, count 2 2006.285.11:34:23.20#ibcon#enter sib2, iclass 5, count 2 2006.285.11:34:23.20#ibcon#flushed, iclass 5, count 2 2006.285.11:34:23.20#ibcon#about to write, iclass 5, count 2 2006.285.11:34:23.20#ibcon#wrote, iclass 5, count 2 2006.285.11:34:23.20#ibcon#about to read 3, iclass 5, count 2 2006.285.11:34:23.23#ibcon#read 3, iclass 5, count 2 2006.285.11:34:23.23#ibcon#about to read 4, iclass 5, count 2 2006.285.11:34:23.23#ibcon#read 4, iclass 5, count 2 2006.285.11:34:23.23#ibcon#about to read 5, iclass 5, count 2 2006.285.11:34:23.23#ibcon#read 5, iclass 5, count 2 2006.285.11:34:23.23#ibcon#about to read 6, iclass 5, count 2 2006.285.11:34:23.23#ibcon#read 6, iclass 5, count 2 2006.285.11:34:23.23#ibcon#end of sib2, iclass 5, count 2 2006.285.11:34:23.23#ibcon#*after write, iclass 5, count 2 2006.285.11:34:23.23#ibcon#*before return 0, iclass 5, count 2 2006.285.11:34:23.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:34:23.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:34:23.23#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.11:34:23.23#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:23.23#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:34:23.35#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:34:23.35#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:34:23.35#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:34:23.35#ibcon#first serial, iclass 5, count 0 2006.285.11:34:23.35#ibcon#enter sib2, iclass 5, count 0 2006.285.11:34:23.35#ibcon#flushed, iclass 5, count 0 2006.285.11:34:23.35#ibcon#about to write, iclass 5, count 0 2006.285.11:34:23.35#ibcon#wrote, iclass 5, count 0 2006.285.11:34:23.35#ibcon#about to read 3, iclass 5, count 0 2006.285.11:34:23.37#ibcon#read 3, iclass 5, count 0 2006.285.11:34:23.37#ibcon#about to read 4, iclass 5, count 0 2006.285.11:34:23.37#ibcon#read 4, iclass 5, count 0 2006.285.11:34:23.37#ibcon#about to read 5, iclass 5, count 0 2006.285.11:34:23.37#ibcon#read 5, iclass 5, count 0 2006.285.11:34:23.37#ibcon#about to read 6, iclass 5, count 0 2006.285.11:34:23.37#ibcon#read 6, iclass 5, count 0 2006.285.11:34:23.37#ibcon#end of sib2, iclass 5, count 0 2006.285.11:34:23.37#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:34:23.37#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:34:23.37#ibcon#[27=USB\r\n] 2006.285.11:34:23.37#ibcon#*before write, iclass 5, count 0 2006.285.11:34:23.37#ibcon#enter sib2, iclass 5, count 0 2006.285.11:34:23.37#ibcon#flushed, iclass 5, count 0 2006.285.11:34:23.37#ibcon#about to write, iclass 5, count 0 2006.285.11:34:23.37#ibcon#wrote, iclass 5, count 0 2006.285.11:34:23.37#ibcon#about to read 3, iclass 5, count 0 2006.285.11:34:23.40#ibcon#read 3, iclass 5, count 0 2006.285.11:34:23.40#ibcon#about to read 4, iclass 5, count 0 2006.285.11:34:23.40#ibcon#read 4, iclass 5, count 0 2006.285.11:34:23.40#ibcon#about to read 5, iclass 5, count 0 2006.285.11:34:23.40#ibcon#read 5, iclass 5, count 0 2006.285.11:34:23.40#ibcon#about to read 6, iclass 5, count 0 2006.285.11:34:23.40#ibcon#read 6, iclass 5, count 0 2006.285.11:34:23.40#ibcon#end of sib2, iclass 5, count 0 2006.285.11:34:23.40#ibcon#*after write, iclass 5, count 0 2006.285.11:34:23.40#ibcon#*before return 0, iclass 5, count 0 2006.285.11:34:23.40#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:34:23.40#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:34:23.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:34:23.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:34:23.40$vck44/vblo=7,734.99 2006.285.11:34:23.40#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.11:34:23.40#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.11:34:23.40#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:23.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:34:23.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:34:23.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:34:23.40#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:34:23.40#ibcon#first serial, iclass 7, count 0 2006.285.11:34:23.40#ibcon#enter sib2, iclass 7, count 0 2006.285.11:34:23.40#ibcon#flushed, iclass 7, count 0 2006.285.11:34:23.40#ibcon#about to write, iclass 7, count 0 2006.285.11:34:23.40#ibcon#wrote, iclass 7, count 0 2006.285.11:34:23.40#ibcon#about to read 3, iclass 7, count 0 2006.285.11:34:23.42#ibcon#read 3, iclass 7, count 0 2006.285.11:34:23.42#ibcon#about to read 4, iclass 7, count 0 2006.285.11:34:23.42#ibcon#read 4, iclass 7, count 0 2006.285.11:34:23.42#ibcon#about to read 5, iclass 7, count 0 2006.285.11:34:23.42#ibcon#read 5, iclass 7, count 0 2006.285.11:34:23.42#ibcon#about to read 6, iclass 7, count 0 2006.285.11:34:23.42#ibcon#read 6, iclass 7, count 0 2006.285.11:34:23.42#ibcon#end of sib2, iclass 7, count 0 2006.285.11:34:23.42#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:34:23.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:34:23.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:34:23.42#ibcon#*before write, iclass 7, count 0 2006.285.11:34:23.42#ibcon#enter sib2, iclass 7, count 0 2006.285.11:34:23.42#ibcon#flushed, iclass 7, count 0 2006.285.11:34:23.42#ibcon#about to write, iclass 7, count 0 2006.285.11:34:23.42#ibcon#wrote, iclass 7, count 0 2006.285.11:34:23.42#ibcon#about to read 3, iclass 7, count 0 2006.285.11:34:23.46#ibcon#read 3, iclass 7, count 0 2006.285.11:34:23.46#ibcon#about to read 4, iclass 7, count 0 2006.285.11:34:23.46#ibcon#read 4, iclass 7, count 0 2006.285.11:34:23.46#ibcon#about to read 5, iclass 7, count 0 2006.285.11:34:23.46#ibcon#read 5, iclass 7, count 0 2006.285.11:34:23.46#ibcon#about to read 6, iclass 7, count 0 2006.285.11:34:23.46#ibcon#read 6, iclass 7, count 0 2006.285.11:34:23.46#ibcon#end of sib2, iclass 7, count 0 2006.285.11:34:23.46#ibcon#*after write, iclass 7, count 0 2006.285.11:34:23.46#ibcon#*before return 0, iclass 7, count 0 2006.285.11:34:23.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:34:23.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:34:23.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:34:23.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:34:23.46$vck44/vb=7,4 2006.285.11:34:23.46#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.11:34:23.46#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.11:34:23.46#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:23.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:34:23.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:34:23.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:34:23.52#ibcon#enter wrdev, iclass 11, count 2 2006.285.11:34:23.52#ibcon#first serial, iclass 11, count 2 2006.285.11:34:23.52#ibcon#enter sib2, iclass 11, count 2 2006.285.11:34:23.52#ibcon#flushed, iclass 11, count 2 2006.285.11:34:23.52#ibcon#about to write, iclass 11, count 2 2006.285.11:34:23.52#ibcon#wrote, iclass 11, count 2 2006.285.11:34:23.52#ibcon#about to read 3, iclass 11, count 2 2006.285.11:34:23.54#ibcon#read 3, iclass 11, count 2 2006.285.11:34:23.54#ibcon#about to read 4, iclass 11, count 2 2006.285.11:34:23.54#ibcon#read 4, iclass 11, count 2 2006.285.11:34:23.54#ibcon#about to read 5, iclass 11, count 2 2006.285.11:34:23.54#ibcon#read 5, iclass 11, count 2 2006.285.11:34:23.54#ibcon#about to read 6, iclass 11, count 2 2006.285.11:34:23.54#ibcon#read 6, iclass 11, count 2 2006.285.11:34:23.54#ibcon#end of sib2, iclass 11, count 2 2006.285.11:34:23.54#ibcon#*mode == 0, iclass 11, count 2 2006.285.11:34:23.54#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.11:34:23.54#ibcon#[27=AT07-04\r\n] 2006.285.11:34:23.54#ibcon#*before write, iclass 11, count 2 2006.285.11:34:23.54#ibcon#enter sib2, iclass 11, count 2 2006.285.11:34:23.54#ibcon#flushed, iclass 11, count 2 2006.285.11:34:23.54#ibcon#about to write, iclass 11, count 2 2006.285.11:34:23.54#ibcon#wrote, iclass 11, count 2 2006.285.11:34:23.54#ibcon#about to read 3, iclass 11, count 2 2006.285.11:34:23.57#ibcon#read 3, iclass 11, count 2 2006.285.11:34:23.57#ibcon#about to read 4, iclass 11, count 2 2006.285.11:34:23.57#ibcon#read 4, iclass 11, count 2 2006.285.11:34:23.57#ibcon#about to read 5, iclass 11, count 2 2006.285.11:34:23.57#ibcon#read 5, iclass 11, count 2 2006.285.11:34:23.57#ibcon#about to read 6, iclass 11, count 2 2006.285.11:34:23.57#ibcon#read 6, iclass 11, count 2 2006.285.11:34:23.57#ibcon#end of sib2, iclass 11, count 2 2006.285.11:34:23.57#ibcon#*after write, iclass 11, count 2 2006.285.11:34:23.57#ibcon#*before return 0, iclass 11, count 2 2006.285.11:34:23.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:34:23.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:34:23.57#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.11:34:23.57#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:23.57#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:34:23.69#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:34:23.69#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:34:23.69#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:34:23.69#ibcon#first serial, iclass 11, count 0 2006.285.11:34:23.69#ibcon#enter sib2, iclass 11, count 0 2006.285.11:34:23.69#ibcon#flushed, iclass 11, count 0 2006.285.11:34:23.69#ibcon#about to write, iclass 11, count 0 2006.285.11:34:23.69#ibcon#wrote, iclass 11, count 0 2006.285.11:34:23.69#ibcon#about to read 3, iclass 11, count 0 2006.285.11:34:23.71#ibcon#read 3, iclass 11, count 0 2006.285.11:34:23.71#ibcon#about to read 4, iclass 11, count 0 2006.285.11:34:23.71#ibcon#read 4, iclass 11, count 0 2006.285.11:34:23.71#ibcon#about to read 5, iclass 11, count 0 2006.285.11:34:23.71#ibcon#read 5, iclass 11, count 0 2006.285.11:34:23.71#ibcon#about to read 6, iclass 11, count 0 2006.285.11:34:23.71#ibcon#read 6, iclass 11, count 0 2006.285.11:34:23.71#ibcon#end of sib2, iclass 11, count 0 2006.285.11:34:23.71#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:34:23.71#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:34:23.71#ibcon#[27=USB\r\n] 2006.285.11:34:23.71#ibcon#*before write, iclass 11, count 0 2006.285.11:34:23.71#ibcon#enter sib2, iclass 11, count 0 2006.285.11:34:23.71#ibcon#flushed, iclass 11, count 0 2006.285.11:34:23.71#ibcon#about to write, iclass 11, count 0 2006.285.11:34:23.71#ibcon#wrote, iclass 11, count 0 2006.285.11:34:23.71#ibcon#about to read 3, iclass 11, count 0 2006.285.11:34:23.74#ibcon#read 3, iclass 11, count 0 2006.285.11:34:23.74#ibcon#about to read 4, iclass 11, count 0 2006.285.11:34:23.74#ibcon#read 4, iclass 11, count 0 2006.285.11:34:23.74#ibcon#about to read 5, iclass 11, count 0 2006.285.11:34:23.74#ibcon#read 5, iclass 11, count 0 2006.285.11:34:23.74#ibcon#about to read 6, iclass 11, count 0 2006.285.11:34:23.74#ibcon#read 6, iclass 11, count 0 2006.285.11:34:23.74#ibcon#end of sib2, iclass 11, count 0 2006.285.11:34:23.74#ibcon#*after write, iclass 11, count 0 2006.285.11:34:23.74#ibcon#*before return 0, iclass 11, count 0 2006.285.11:34:23.74#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:34:23.74#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:34:23.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:34:23.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:34:23.74$vck44/vblo=8,744.99 2006.285.11:34:23.74#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.11:34:23.74#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.11:34:23.74#ibcon#ireg 17 cls_cnt 0 2006.285.11:34:23.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:34:23.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:34:23.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:34:23.74#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:34:23.74#ibcon#first serial, iclass 13, count 0 2006.285.11:34:23.74#ibcon#enter sib2, iclass 13, count 0 2006.285.11:34:23.74#ibcon#flushed, iclass 13, count 0 2006.285.11:34:23.74#ibcon#about to write, iclass 13, count 0 2006.285.11:34:23.74#ibcon#wrote, iclass 13, count 0 2006.285.11:34:23.74#ibcon#about to read 3, iclass 13, count 0 2006.285.11:34:23.76#ibcon#read 3, iclass 13, count 0 2006.285.11:34:23.76#ibcon#about to read 4, iclass 13, count 0 2006.285.11:34:23.76#ibcon#read 4, iclass 13, count 0 2006.285.11:34:23.76#ibcon#about to read 5, iclass 13, count 0 2006.285.11:34:23.76#ibcon#read 5, iclass 13, count 0 2006.285.11:34:23.76#ibcon#about to read 6, iclass 13, count 0 2006.285.11:34:23.76#ibcon#read 6, iclass 13, count 0 2006.285.11:34:23.76#ibcon#end of sib2, iclass 13, count 0 2006.285.11:34:23.76#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:34:23.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:34:23.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:34:23.76#ibcon#*before write, iclass 13, count 0 2006.285.11:34:23.76#ibcon#enter sib2, iclass 13, count 0 2006.285.11:34:23.76#ibcon#flushed, iclass 13, count 0 2006.285.11:34:23.76#ibcon#about to write, iclass 13, count 0 2006.285.11:34:23.76#ibcon#wrote, iclass 13, count 0 2006.285.11:34:23.76#ibcon#about to read 3, iclass 13, count 0 2006.285.11:34:23.80#ibcon#read 3, iclass 13, count 0 2006.285.11:34:23.80#ibcon#about to read 4, iclass 13, count 0 2006.285.11:34:23.80#ibcon#read 4, iclass 13, count 0 2006.285.11:34:23.80#ibcon#about to read 5, iclass 13, count 0 2006.285.11:34:23.80#ibcon#read 5, iclass 13, count 0 2006.285.11:34:23.80#ibcon#about to read 6, iclass 13, count 0 2006.285.11:34:23.80#ibcon#read 6, iclass 13, count 0 2006.285.11:34:23.80#ibcon#end of sib2, iclass 13, count 0 2006.285.11:34:23.80#ibcon#*after write, iclass 13, count 0 2006.285.11:34:23.80#ibcon#*before return 0, iclass 13, count 0 2006.285.11:34:23.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:34:23.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:34:23.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:34:23.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:34:23.80$vck44/vb=8,4 2006.285.11:34:23.80#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.11:34:23.80#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.11:34:23.80#ibcon#ireg 11 cls_cnt 2 2006.285.11:34:23.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:34:23.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:34:23.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:34:23.86#ibcon#enter wrdev, iclass 15, count 2 2006.285.11:34:23.86#ibcon#first serial, iclass 15, count 2 2006.285.11:34:23.86#ibcon#enter sib2, iclass 15, count 2 2006.285.11:34:23.86#ibcon#flushed, iclass 15, count 2 2006.285.11:34:23.86#ibcon#about to write, iclass 15, count 2 2006.285.11:34:23.86#ibcon#wrote, iclass 15, count 2 2006.285.11:34:23.86#ibcon#about to read 3, iclass 15, count 2 2006.285.11:34:23.88#ibcon#read 3, iclass 15, count 2 2006.285.11:34:23.88#ibcon#about to read 4, iclass 15, count 2 2006.285.11:34:23.88#ibcon#read 4, iclass 15, count 2 2006.285.11:34:23.88#ibcon#about to read 5, iclass 15, count 2 2006.285.11:34:23.88#ibcon#read 5, iclass 15, count 2 2006.285.11:34:23.88#ibcon#about to read 6, iclass 15, count 2 2006.285.11:34:23.88#ibcon#read 6, iclass 15, count 2 2006.285.11:34:23.88#ibcon#end of sib2, iclass 15, count 2 2006.285.11:34:23.88#ibcon#*mode == 0, iclass 15, count 2 2006.285.11:34:23.88#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.11:34:23.88#ibcon#[27=AT08-04\r\n] 2006.285.11:34:23.88#ibcon#*before write, iclass 15, count 2 2006.285.11:34:23.88#ibcon#enter sib2, iclass 15, count 2 2006.285.11:34:23.88#ibcon#flushed, iclass 15, count 2 2006.285.11:34:23.88#ibcon#about to write, iclass 15, count 2 2006.285.11:34:23.88#ibcon#wrote, iclass 15, count 2 2006.285.11:34:23.88#ibcon#about to read 3, iclass 15, count 2 2006.285.11:34:23.91#ibcon#read 3, iclass 15, count 2 2006.285.11:34:23.91#ibcon#about to read 4, iclass 15, count 2 2006.285.11:34:23.91#ibcon#read 4, iclass 15, count 2 2006.285.11:34:23.91#ibcon#about to read 5, iclass 15, count 2 2006.285.11:34:23.91#ibcon#read 5, iclass 15, count 2 2006.285.11:34:23.91#ibcon#about to read 6, iclass 15, count 2 2006.285.11:34:23.91#ibcon#read 6, iclass 15, count 2 2006.285.11:34:23.91#ibcon#end of sib2, iclass 15, count 2 2006.285.11:34:23.91#ibcon#*after write, iclass 15, count 2 2006.285.11:34:23.91#ibcon#*before return 0, iclass 15, count 2 2006.285.11:34:23.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:34:23.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:34:23.91#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.11:34:23.91#ibcon#ireg 7 cls_cnt 0 2006.285.11:34:23.91#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:34:24.03#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:34:24.03#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:34:24.03#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:34:24.03#ibcon#first serial, iclass 15, count 0 2006.285.11:34:24.03#ibcon#enter sib2, iclass 15, count 0 2006.285.11:34:24.03#ibcon#flushed, iclass 15, count 0 2006.285.11:34:24.03#ibcon#about to write, iclass 15, count 0 2006.285.11:34:24.03#ibcon#wrote, iclass 15, count 0 2006.285.11:34:24.03#ibcon#about to read 3, iclass 15, count 0 2006.285.11:34:24.05#ibcon#read 3, iclass 15, count 0 2006.285.11:34:24.05#ibcon#about to read 4, iclass 15, count 0 2006.285.11:34:24.05#ibcon#read 4, iclass 15, count 0 2006.285.11:34:24.05#ibcon#about to read 5, iclass 15, count 0 2006.285.11:34:24.05#ibcon#read 5, iclass 15, count 0 2006.285.11:34:24.05#ibcon#about to read 6, iclass 15, count 0 2006.285.11:34:24.05#ibcon#read 6, iclass 15, count 0 2006.285.11:34:24.05#ibcon#end of sib2, iclass 15, count 0 2006.285.11:34:24.05#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:34:24.05#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:34:24.05#ibcon#[27=USB\r\n] 2006.285.11:34:24.05#ibcon#*before write, iclass 15, count 0 2006.285.11:34:24.05#ibcon#enter sib2, iclass 15, count 0 2006.285.11:34:24.05#ibcon#flushed, iclass 15, count 0 2006.285.11:34:24.05#ibcon#about to write, iclass 15, count 0 2006.285.11:34:24.05#ibcon#wrote, iclass 15, count 0 2006.285.11:34:24.05#ibcon#about to read 3, iclass 15, count 0 2006.285.11:34:24.08#ibcon#read 3, iclass 15, count 0 2006.285.11:34:24.08#ibcon#about to read 4, iclass 15, count 0 2006.285.11:34:24.08#ibcon#read 4, iclass 15, count 0 2006.285.11:34:24.08#ibcon#about to read 5, iclass 15, count 0 2006.285.11:34:24.08#ibcon#read 5, iclass 15, count 0 2006.285.11:34:24.08#ibcon#about to read 6, iclass 15, count 0 2006.285.11:34:24.08#ibcon#read 6, iclass 15, count 0 2006.285.11:34:24.08#ibcon#end of sib2, iclass 15, count 0 2006.285.11:34:24.08#ibcon#*after write, iclass 15, count 0 2006.285.11:34:24.08#ibcon#*before return 0, iclass 15, count 0 2006.285.11:34:24.08#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:34:24.08#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:34:24.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:34:24.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:34:24.08$vck44/vabw=wide 2006.285.11:34:24.08#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.11:34:24.08#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.11:34:24.08#ibcon#ireg 8 cls_cnt 0 2006.285.11:34:24.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:34:24.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:34:24.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:34:24.08#ibcon#enter wrdev, iclass 17, count 0 2006.285.11:34:24.08#ibcon#first serial, iclass 17, count 0 2006.285.11:34:24.08#ibcon#enter sib2, iclass 17, count 0 2006.285.11:34:24.08#ibcon#flushed, iclass 17, count 0 2006.285.11:34:24.08#ibcon#about to write, iclass 17, count 0 2006.285.11:34:24.08#ibcon#wrote, iclass 17, count 0 2006.285.11:34:24.08#ibcon#about to read 3, iclass 17, count 0 2006.285.11:34:24.10#ibcon#read 3, iclass 17, count 0 2006.285.11:34:24.10#ibcon#about to read 4, iclass 17, count 0 2006.285.11:34:24.10#ibcon#read 4, iclass 17, count 0 2006.285.11:34:24.10#ibcon#about to read 5, iclass 17, count 0 2006.285.11:34:24.10#ibcon#read 5, iclass 17, count 0 2006.285.11:34:24.10#ibcon#about to read 6, iclass 17, count 0 2006.285.11:34:24.10#ibcon#read 6, iclass 17, count 0 2006.285.11:34:24.10#ibcon#end of sib2, iclass 17, count 0 2006.285.11:34:24.10#ibcon#*mode == 0, iclass 17, count 0 2006.285.11:34:24.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.11:34:24.10#ibcon#[25=BW32\r\n] 2006.285.11:34:24.10#ibcon#*before write, iclass 17, count 0 2006.285.11:34:24.10#ibcon#enter sib2, iclass 17, count 0 2006.285.11:34:24.10#ibcon#flushed, iclass 17, count 0 2006.285.11:34:24.10#ibcon#about to write, iclass 17, count 0 2006.285.11:34:24.10#ibcon#wrote, iclass 17, count 0 2006.285.11:34:24.10#ibcon#about to read 3, iclass 17, count 0 2006.285.11:34:24.13#ibcon#read 3, iclass 17, count 0 2006.285.11:34:24.13#ibcon#about to read 4, iclass 17, count 0 2006.285.11:34:24.13#ibcon#read 4, iclass 17, count 0 2006.285.11:34:24.13#ibcon#about to read 5, iclass 17, count 0 2006.285.11:34:24.13#ibcon#read 5, iclass 17, count 0 2006.285.11:34:24.13#ibcon#about to read 6, iclass 17, count 0 2006.285.11:34:24.13#ibcon#read 6, iclass 17, count 0 2006.285.11:34:24.13#ibcon#end of sib2, iclass 17, count 0 2006.285.11:34:24.13#ibcon#*after write, iclass 17, count 0 2006.285.11:34:24.13#ibcon#*before return 0, iclass 17, count 0 2006.285.11:34:24.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:34:24.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:34:24.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.11:34:24.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.11:34:24.13$vck44/vbbw=wide 2006.285.11:34:24.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.11:34:24.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.11:34:24.13#ibcon#ireg 8 cls_cnt 0 2006.285.11:34:24.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:34:24.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:34:24.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:34:24.20#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:34:24.20#ibcon#first serial, iclass 19, count 0 2006.285.11:34:24.20#ibcon#enter sib2, iclass 19, count 0 2006.285.11:34:24.20#ibcon#flushed, iclass 19, count 0 2006.285.11:34:24.20#ibcon#about to write, iclass 19, count 0 2006.285.11:34:24.20#ibcon#wrote, iclass 19, count 0 2006.285.11:34:24.20#ibcon#about to read 3, iclass 19, count 0 2006.285.11:34:24.22#ibcon#read 3, iclass 19, count 0 2006.285.11:34:24.22#ibcon#about to read 4, iclass 19, count 0 2006.285.11:34:24.22#ibcon#read 4, iclass 19, count 0 2006.285.11:34:24.22#ibcon#about to read 5, iclass 19, count 0 2006.285.11:34:24.22#ibcon#read 5, iclass 19, count 0 2006.285.11:34:24.22#ibcon#about to read 6, iclass 19, count 0 2006.285.11:34:24.22#ibcon#read 6, iclass 19, count 0 2006.285.11:34:24.22#ibcon#end of sib2, iclass 19, count 0 2006.285.11:34:24.22#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:34:24.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:34:24.22#ibcon#[27=BW32\r\n] 2006.285.11:34:24.22#ibcon#*before write, iclass 19, count 0 2006.285.11:34:24.22#ibcon#enter sib2, iclass 19, count 0 2006.285.11:34:24.22#ibcon#flushed, iclass 19, count 0 2006.285.11:34:24.22#ibcon#about to write, iclass 19, count 0 2006.285.11:34:24.22#ibcon#wrote, iclass 19, count 0 2006.285.11:34:24.22#ibcon#about to read 3, iclass 19, count 0 2006.285.11:34:24.25#ibcon#read 3, iclass 19, count 0 2006.285.11:34:24.25#ibcon#about to read 4, iclass 19, count 0 2006.285.11:34:24.25#ibcon#read 4, iclass 19, count 0 2006.285.11:34:24.25#ibcon#about to read 5, iclass 19, count 0 2006.285.11:34:24.25#ibcon#read 5, iclass 19, count 0 2006.285.11:34:24.25#ibcon#about to read 6, iclass 19, count 0 2006.285.11:34:24.25#ibcon#read 6, iclass 19, count 0 2006.285.11:34:24.25#ibcon#end of sib2, iclass 19, count 0 2006.285.11:34:24.25#ibcon#*after write, iclass 19, count 0 2006.285.11:34:24.25#ibcon#*before return 0, iclass 19, count 0 2006.285.11:34:24.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:34:24.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:34:24.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:34:24.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:34:24.25$setupk4/ifdk4 2006.285.11:34:24.25$ifdk4/lo= 2006.285.11:34:24.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:34:24.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:34:24.25$ifdk4/patch= 2006.285.11:34:24.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:34:24.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:34:24.25$setupk4/!*+20s 2006.285.11:34:24.30#abcon#<5=/06 1.1 1.6 19.20 941015.3\r\n> 2006.285.11:34:24.32#abcon#{5=INTERFACE CLEAR} 2006.285.11:34:24.38#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:34:34.47#abcon#<5=/06 1.1 1.6 19.20 941015.3\r\n> 2006.285.11:34:34.49#abcon#{5=INTERFACE CLEAR} 2006.285.11:34:34.55#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:34:38.73$setupk4/"tpicd 2006.285.11:34:38.73$setupk4/echo=off 2006.285.11:34:38.73$setupk4/xlog=off 2006.285.11:34:38.73:!2006.285.11:35:26 2006.285.11:34:40.14#trakl#Source acquired 2006.285.11:34:41.14#flagr#flagr/antenna,acquired 2006.285.11:35:26.00:preob 2006.285.11:35:27.14/onsource/TRACKING 2006.285.11:35:27.14:!2006.285.11:35:36 2006.285.11:35:36.00:"tape 2006.285.11:35:36.00:"st=record 2006.285.11:35:36.00:data_valid=on 2006.285.11:35:36.00:midob 2006.285.11:35:36.14/onsource/TRACKING 2006.285.11:35:36.14/wx/19.18,1015.3,94 2006.285.11:35:36.20/cable/+6.4907E-03 2006.285.11:35:37.29/va/01,07,usb,yes,40,43 2006.285.11:35:37.29/va/02,06,usb,yes,40,40 2006.285.11:35:37.29/va/03,07,usb,yes,39,41 2006.285.11:35:37.29/va/04,06,usb,yes,41,43 2006.285.11:35:37.29/va/05,03,usb,yes,40,41 2006.285.11:35:37.29/va/06,04,usb,yes,37,36 2006.285.11:35:37.29/va/07,04,usb,yes,37,38 2006.285.11:35:37.29/va/08,03,usb,yes,38,46 2006.285.11:35:37.52/valo/01,524.99,yes,locked 2006.285.11:35:37.52/valo/02,534.99,yes,locked 2006.285.11:35:37.52/valo/03,564.99,yes,locked 2006.285.11:35:37.52/valo/04,624.99,yes,locked 2006.285.11:35:37.52/valo/05,734.99,yes,locked 2006.285.11:35:37.52/valo/06,814.99,yes,locked 2006.285.11:35:37.52/valo/07,864.99,yes,locked 2006.285.11:35:37.52/valo/08,884.99,yes,locked 2006.285.11:35:38.61/vb/01,04,usb,yes,34,32 2006.285.11:35:38.61/vb/02,05,usb,yes,33,32 2006.285.11:35:38.61/vb/03,04,usb,yes,34,37 2006.285.11:35:38.61/vb/04,05,usb,yes,34,33 2006.285.11:35:38.61/vb/05,04,usb,yes,30,33 2006.285.11:35:38.61/vb/06,03,usb,yes,44,39 2006.285.11:35:38.61/vb/07,04,usb,yes,35,35 2006.285.11:35:38.61/vb/08,04,usb,yes,32,36 2006.285.11:35:38.84/vblo/01,629.99,yes,locked 2006.285.11:35:38.84/vblo/02,634.99,yes,locked 2006.285.11:35:38.84/vblo/03,649.99,yes,locked 2006.285.11:35:38.84/vblo/04,679.99,yes,locked 2006.285.11:35:38.84/vblo/05,709.99,yes,locked 2006.285.11:35:38.84/vblo/06,719.99,yes,locked 2006.285.11:35:38.84/vblo/07,734.99,yes,locked 2006.285.11:35:38.84/vblo/08,744.99,yes,locked 2006.285.11:35:38.99/vabw/8 2006.285.11:35:39.14/vbbw/8 2006.285.11:35:39.23/xfe/off,on,12.0 2006.285.11:35:39.60/ifatt/23,28,28,28 2006.285.11:35:40.07/fmout-gps/S +2.68E-07 2006.285.11:35:40.09:!2006.285.11:37:26 2006.285.11:37:26.00:data_valid=off 2006.285.11:37:26.00:"et 2006.285.11:37:26.00:!+3s 2006.285.11:37:29.01:"tape 2006.285.11:37:29.01:postob 2006.285.11:37:29.16/cable/+6.4910E-03 2006.285.11:37:29.16/wx/19.14,1015.3,95 2006.285.11:37:30.08/fmout-gps/S +2.68E-07 2006.285.11:37:30.08:scan_name=285-1144,jd0610,40 2006.285.11:37:30.08:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.285.11:37:31.13#flagr#flagr/antenna,new-source 2006.285.11:37:31.13:checkk5 2006.285.11:37:31.51/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:37:32.17/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:37:32.57/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:37:32.92/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:37:33.30/chk_obsdata//k5ts1/T2851135??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.11:37:33.66/chk_obsdata//k5ts2/T2851135??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.11:37:34.13/chk_obsdata//k5ts3/T2851135??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.11:37:34.48/chk_obsdata//k5ts4/T2851135??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.11:37:35.22/k5log//k5ts1_log_newline 2006.285.11:37:36.89/k5log//k5ts2_log_newline 2006.285.11:37:37.85/k5log//k5ts3_log_newline 2006.285.11:37:38.91/k5log//k5ts4_log_newline 2006.285.11:37:38.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:37:38.93:setupk4=1 2006.285.11:37:38.94$setupk4/echo=on 2006.285.11:37:38.94$setupk4/pcalon 2006.285.11:37:38.94$pcalon/"no phase cal control is implemented here 2006.285.11:37:38.94$setupk4/"tpicd=stop 2006.285.11:37:38.94$setupk4/"rec=synch_on 2006.285.11:37:38.94$setupk4/"rec_mode=128 2006.285.11:37:38.94$setupk4/!* 2006.285.11:37:38.94$setupk4/recpk4 2006.285.11:37:38.94$recpk4/recpatch= 2006.285.11:37:38.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:37:38.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:37:38.94$setupk4/vck44 2006.285.11:37:38.94$vck44/valo=1,524.99 2006.285.11:37:38.94#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.11:37:38.94#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.11:37:38.94#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:38.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:37:38.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:37:38.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:37:38.94#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:37:38.94#ibcon#first serial, iclass 32, count 0 2006.285.11:37:38.94#ibcon#enter sib2, iclass 32, count 0 2006.285.11:37:38.94#ibcon#flushed, iclass 32, count 0 2006.285.11:37:38.94#ibcon#about to write, iclass 32, count 0 2006.285.11:37:38.94#ibcon#wrote, iclass 32, count 0 2006.285.11:37:38.94#ibcon#about to read 3, iclass 32, count 0 2006.285.11:37:38.96#ibcon#read 3, iclass 32, count 0 2006.285.11:37:38.96#ibcon#about to read 4, iclass 32, count 0 2006.285.11:37:38.96#ibcon#read 4, iclass 32, count 0 2006.285.11:37:38.96#ibcon#about to read 5, iclass 32, count 0 2006.285.11:37:38.96#ibcon#read 5, iclass 32, count 0 2006.285.11:37:38.96#ibcon#about to read 6, iclass 32, count 0 2006.285.11:37:38.96#ibcon#read 6, iclass 32, count 0 2006.285.11:37:38.96#ibcon#end of sib2, iclass 32, count 0 2006.285.11:37:38.96#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:37:38.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:37:38.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:37:38.96#ibcon#*before write, iclass 32, count 0 2006.285.11:37:38.96#ibcon#enter sib2, iclass 32, count 0 2006.285.11:37:38.96#ibcon#flushed, iclass 32, count 0 2006.285.11:37:38.96#ibcon#about to write, iclass 32, count 0 2006.285.11:37:38.96#ibcon#wrote, iclass 32, count 0 2006.285.11:37:38.96#ibcon#about to read 3, iclass 32, count 0 2006.285.11:37:39.01#ibcon#read 3, iclass 32, count 0 2006.285.11:37:39.01#ibcon#about to read 4, iclass 32, count 0 2006.285.11:37:39.01#ibcon#read 4, iclass 32, count 0 2006.285.11:37:39.01#ibcon#about to read 5, iclass 32, count 0 2006.285.11:37:39.01#ibcon#read 5, iclass 32, count 0 2006.285.11:37:39.01#ibcon#about to read 6, iclass 32, count 0 2006.285.11:37:39.01#ibcon#read 6, iclass 32, count 0 2006.285.11:37:39.01#ibcon#end of sib2, iclass 32, count 0 2006.285.11:37:39.01#ibcon#*after write, iclass 32, count 0 2006.285.11:37:39.01#ibcon#*before return 0, iclass 32, count 0 2006.285.11:37:39.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:37:39.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:37:39.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:37:39.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:37:39.01$vck44/va=1,7 2006.285.11:37:39.01#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.11:37:39.01#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.11:37:39.01#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:39.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:37:39.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:37:39.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:37:39.01#ibcon#enter wrdev, iclass 34, count 2 2006.285.11:37:39.01#ibcon#first serial, iclass 34, count 2 2006.285.11:37:39.01#ibcon#enter sib2, iclass 34, count 2 2006.285.11:37:39.01#ibcon#flushed, iclass 34, count 2 2006.285.11:37:39.01#ibcon#about to write, iclass 34, count 2 2006.285.11:37:39.01#ibcon#wrote, iclass 34, count 2 2006.285.11:37:39.01#ibcon#about to read 3, iclass 34, count 2 2006.285.11:37:39.03#ibcon#read 3, iclass 34, count 2 2006.285.11:37:39.03#ibcon#about to read 4, iclass 34, count 2 2006.285.11:37:39.03#ibcon#read 4, iclass 34, count 2 2006.285.11:37:39.03#ibcon#about to read 5, iclass 34, count 2 2006.285.11:37:39.03#ibcon#read 5, iclass 34, count 2 2006.285.11:37:39.03#ibcon#about to read 6, iclass 34, count 2 2006.285.11:37:39.03#ibcon#read 6, iclass 34, count 2 2006.285.11:37:39.03#ibcon#end of sib2, iclass 34, count 2 2006.285.11:37:39.03#ibcon#*mode == 0, iclass 34, count 2 2006.285.11:37:39.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.11:37:39.03#ibcon#[25=AT01-07\r\n] 2006.285.11:37:39.03#ibcon#*before write, iclass 34, count 2 2006.285.11:37:39.03#ibcon#enter sib2, iclass 34, count 2 2006.285.11:37:39.03#ibcon#flushed, iclass 34, count 2 2006.285.11:37:39.03#ibcon#about to write, iclass 34, count 2 2006.285.11:37:39.03#ibcon#wrote, iclass 34, count 2 2006.285.11:37:39.03#ibcon#about to read 3, iclass 34, count 2 2006.285.11:37:39.06#ibcon#read 3, iclass 34, count 2 2006.285.11:37:39.06#ibcon#about to read 4, iclass 34, count 2 2006.285.11:37:39.06#ibcon#read 4, iclass 34, count 2 2006.285.11:37:39.06#ibcon#about to read 5, iclass 34, count 2 2006.285.11:37:39.06#ibcon#read 5, iclass 34, count 2 2006.285.11:37:39.06#ibcon#about to read 6, iclass 34, count 2 2006.285.11:37:39.06#ibcon#read 6, iclass 34, count 2 2006.285.11:37:39.06#ibcon#end of sib2, iclass 34, count 2 2006.285.11:37:39.06#ibcon#*after write, iclass 34, count 2 2006.285.11:37:39.06#ibcon#*before return 0, iclass 34, count 2 2006.285.11:37:39.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:37:39.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:37:39.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.11:37:39.06#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:39.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:37:39.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:37:39.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:37:39.18#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:37:39.18#ibcon#first serial, iclass 34, count 0 2006.285.11:37:39.18#ibcon#enter sib2, iclass 34, count 0 2006.285.11:37:39.18#ibcon#flushed, iclass 34, count 0 2006.285.11:37:39.18#ibcon#about to write, iclass 34, count 0 2006.285.11:37:39.18#ibcon#wrote, iclass 34, count 0 2006.285.11:37:39.18#ibcon#about to read 3, iclass 34, count 0 2006.285.11:37:39.20#ibcon#read 3, iclass 34, count 0 2006.285.11:37:39.20#ibcon#about to read 4, iclass 34, count 0 2006.285.11:37:39.20#ibcon#read 4, iclass 34, count 0 2006.285.11:37:39.20#ibcon#about to read 5, iclass 34, count 0 2006.285.11:37:39.20#ibcon#read 5, iclass 34, count 0 2006.285.11:37:39.20#ibcon#about to read 6, iclass 34, count 0 2006.285.11:37:39.20#ibcon#read 6, iclass 34, count 0 2006.285.11:37:39.20#ibcon#end of sib2, iclass 34, count 0 2006.285.11:37:39.20#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:37:39.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:37:39.20#ibcon#[25=USB\r\n] 2006.285.11:37:39.20#ibcon#*before write, iclass 34, count 0 2006.285.11:37:39.20#ibcon#enter sib2, iclass 34, count 0 2006.285.11:37:39.20#ibcon#flushed, iclass 34, count 0 2006.285.11:37:39.20#ibcon#about to write, iclass 34, count 0 2006.285.11:37:39.20#ibcon#wrote, iclass 34, count 0 2006.285.11:37:39.20#ibcon#about to read 3, iclass 34, count 0 2006.285.11:37:39.23#ibcon#read 3, iclass 34, count 0 2006.285.11:37:39.23#ibcon#about to read 4, iclass 34, count 0 2006.285.11:37:39.23#ibcon#read 4, iclass 34, count 0 2006.285.11:37:39.23#ibcon#about to read 5, iclass 34, count 0 2006.285.11:37:39.23#ibcon#read 5, iclass 34, count 0 2006.285.11:37:39.23#ibcon#about to read 6, iclass 34, count 0 2006.285.11:37:39.23#ibcon#read 6, iclass 34, count 0 2006.285.11:37:39.23#ibcon#end of sib2, iclass 34, count 0 2006.285.11:37:39.23#ibcon#*after write, iclass 34, count 0 2006.285.11:37:39.23#ibcon#*before return 0, iclass 34, count 0 2006.285.11:37:39.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:37:39.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:37:39.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:37:39.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:37:39.23$vck44/valo=2,534.99 2006.285.11:37:39.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.11:37:39.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.11:37:39.23#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:39.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:37:39.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:37:39.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:37:39.23#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:37:39.23#ibcon#first serial, iclass 36, count 0 2006.285.11:37:39.23#ibcon#enter sib2, iclass 36, count 0 2006.285.11:37:39.23#ibcon#flushed, iclass 36, count 0 2006.285.11:37:39.23#ibcon#about to write, iclass 36, count 0 2006.285.11:37:39.23#ibcon#wrote, iclass 36, count 0 2006.285.11:37:39.23#ibcon#about to read 3, iclass 36, count 0 2006.285.11:37:39.25#ibcon#read 3, iclass 36, count 0 2006.285.11:37:39.25#ibcon#about to read 4, iclass 36, count 0 2006.285.11:37:39.25#ibcon#read 4, iclass 36, count 0 2006.285.11:37:39.25#ibcon#about to read 5, iclass 36, count 0 2006.285.11:37:39.25#ibcon#read 5, iclass 36, count 0 2006.285.11:37:39.25#ibcon#about to read 6, iclass 36, count 0 2006.285.11:37:39.25#ibcon#read 6, iclass 36, count 0 2006.285.11:37:39.25#ibcon#end of sib2, iclass 36, count 0 2006.285.11:37:39.25#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:37:39.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:37:39.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:37:39.25#ibcon#*before write, iclass 36, count 0 2006.285.11:37:39.25#ibcon#enter sib2, iclass 36, count 0 2006.285.11:37:39.25#ibcon#flushed, iclass 36, count 0 2006.285.11:37:39.25#ibcon#about to write, iclass 36, count 0 2006.285.11:37:39.25#ibcon#wrote, iclass 36, count 0 2006.285.11:37:39.25#ibcon#about to read 3, iclass 36, count 0 2006.285.11:37:39.29#ibcon#read 3, iclass 36, count 0 2006.285.11:37:39.29#ibcon#about to read 4, iclass 36, count 0 2006.285.11:37:39.29#ibcon#read 4, iclass 36, count 0 2006.285.11:37:39.29#ibcon#about to read 5, iclass 36, count 0 2006.285.11:37:39.29#ibcon#read 5, iclass 36, count 0 2006.285.11:37:39.29#ibcon#about to read 6, iclass 36, count 0 2006.285.11:37:39.29#ibcon#read 6, iclass 36, count 0 2006.285.11:37:39.29#ibcon#end of sib2, iclass 36, count 0 2006.285.11:37:39.29#ibcon#*after write, iclass 36, count 0 2006.285.11:37:39.29#ibcon#*before return 0, iclass 36, count 0 2006.285.11:37:39.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:37:39.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:37:39.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:37:39.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:37:39.29$vck44/va=2,6 2006.285.11:37:39.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.11:37:39.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.11:37:39.29#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:39.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:37:39.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:37:39.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:37:39.35#ibcon#enter wrdev, iclass 38, count 2 2006.285.11:37:39.35#ibcon#first serial, iclass 38, count 2 2006.285.11:37:39.35#ibcon#enter sib2, iclass 38, count 2 2006.285.11:37:39.35#ibcon#flushed, iclass 38, count 2 2006.285.11:37:39.35#ibcon#about to write, iclass 38, count 2 2006.285.11:37:39.35#ibcon#wrote, iclass 38, count 2 2006.285.11:37:39.35#ibcon#about to read 3, iclass 38, count 2 2006.285.11:37:39.37#ibcon#read 3, iclass 38, count 2 2006.285.11:37:39.37#ibcon#about to read 4, iclass 38, count 2 2006.285.11:37:39.37#ibcon#read 4, iclass 38, count 2 2006.285.11:37:39.37#ibcon#about to read 5, iclass 38, count 2 2006.285.11:37:39.37#ibcon#read 5, iclass 38, count 2 2006.285.11:37:39.37#ibcon#about to read 6, iclass 38, count 2 2006.285.11:37:39.37#ibcon#read 6, iclass 38, count 2 2006.285.11:37:39.37#ibcon#end of sib2, iclass 38, count 2 2006.285.11:37:39.37#ibcon#*mode == 0, iclass 38, count 2 2006.285.11:37:39.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.11:37:39.37#ibcon#[25=AT02-06\r\n] 2006.285.11:37:39.37#ibcon#*before write, iclass 38, count 2 2006.285.11:37:39.37#ibcon#enter sib2, iclass 38, count 2 2006.285.11:37:39.37#ibcon#flushed, iclass 38, count 2 2006.285.11:37:39.37#ibcon#about to write, iclass 38, count 2 2006.285.11:37:39.37#ibcon#wrote, iclass 38, count 2 2006.285.11:37:39.37#ibcon#about to read 3, iclass 38, count 2 2006.285.11:37:39.40#ibcon#read 3, iclass 38, count 2 2006.285.11:37:39.40#ibcon#about to read 4, iclass 38, count 2 2006.285.11:37:39.40#ibcon#read 4, iclass 38, count 2 2006.285.11:37:39.40#ibcon#about to read 5, iclass 38, count 2 2006.285.11:37:39.40#ibcon#read 5, iclass 38, count 2 2006.285.11:37:39.40#ibcon#about to read 6, iclass 38, count 2 2006.285.11:37:39.40#ibcon#read 6, iclass 38, count 2 2006.285.11:37:39.40#ibcon#end of sib2, iclass 38, count 2 2006.285.11:37:39.40#ibcon#*after write, iclass 38, count 2 2006.285.11:37:39.40#ibcon#*before return 0, iclass 38, count 2 2006.285.11:37:39.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:37:39.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:37:39.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.11:37:39.40#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:39.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:37:39.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:37:39.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:37:39.52#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:37:39.52#ibcon#first serial, iclass 38, count 0 2006.285.11:37:39.52#ibcon#enter sib2, iclass 38, count 0 2006.285.11:37:39.52#ibcon#flushed, iclass 38, count 0 2006.285.11:37:39.52#ibcon#about to write, iclass 38, count 0 2006.285.11:37:39.52#ibcon#wrote, iclass 38, count 0 2006.285.11:37:39.52#ibcon#about to read 3, iclass 38, count 0 2006.285.11:37:39.54#ibcon#read 3, iclass 38, count 0 2006.285.11:37:39.54#ibcon#about to read 4, iclass 38, count 0 2006.285.11:37:39.54#ibcon#read 4, iclass 38, count 0 2006.285.11:37:39.54#ibcon#about to read 5, iclass 38, count 0 2006.285.11:37:39.54#ibcon#read 5, iclass 38, count 0 2006.285.11:37:39.54#ibcon#about to read 6, iclass 38, count 0 2006.285.11:37:39.54#ibcon#read 6, iclass 38, count 0 2006.285.11:37:39.54#ibcon#end of sib2, iclass 38, count 0 2006.285.11:37:39.54#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:37:39.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:37:39.54#ibcon#[25=USB\r\n] 2006.285.11:37:39.54#ibcon#*before write, iclass 38, count 0 2006.285.11:37:39.54#ibcon#enter sib2, iclass 38, count 0 2006.285.11:37:39.54#ibcon#flushed, iclass 38, count 0 2006.285.11:37:39.54#ibcon#about to write, iclass 38, count 0 2006.285.11:37:39.54#ibcon#wrote, iclass 38, count 0 2006.285.11:37:39.54#ibcon#about to read 3, iclass 38, count 0 2006.285.11:37:39.57#ibcon#read 3, iclass 38, count 0 2006.285.11:37:39.57#ibcon#about to read 4, iclass 38, count 0 2006.285.11:37:39.57#ibcon#read 4, iclass 38, count 0 2006.285.11:37:39.57#ibcon#about to read 5, iclass 38, count 0 2006.285.11:37:39.57#ibcon#read 5, iclass 38, count 0 2006.285.11:37:39.57#ibcon#about to read 6, iclass 38, count 0 2006.285.11:37:39.57#ibcon#read 6, iclass 38, count 0 2006.285.11:37:39.57#ibcon#end of sib2, iclass 38, count 0 2006.285.11:37:39.57#ibcon#*after write, iclass 38, count 0 2006.285.11:37:39.57#ibcon#*before return 0, iclass 38, count 0 2006.285.11:37:39.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:37:39.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:37:39.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:37:39.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:37:39.57$vck44/valo=3,564.99 2006.285.11:37:39.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.11:37:39.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.11:37:39.57#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:39.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:37:39.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:37:39.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:37:39.57#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:37:39.57#ibcon#first serial, iclass 40, count 0 2006.285.11:37:39.57#ibcon#enter sib2, iclass 40, count 0 2006.285.11:37:39.57#ibcon#flushed, iclass 40, count 0 2006.285.11:37:39.57#ibcon#about to write, iclass 40, count 0 2006.285.11:37:39.57#ibcon#wrote, iclass 40, count 0 2006.285.11:37:39.57#ibcon#about to read 3, iclass 40, count 0 2006.285.11:37:39.59#ibcon#read 3, iclass 40, count 0 2006.285.11:37:39.59#ibcon#about to read 4, iclass 40, count 0 2006.285.11:37:39.59#ibcon#read 4, iclass 40, count 0 2006.285.11:37:39.59#ibcon#about to read 5, iclass 40, count 0 2006.285.11:37:39.59#ibcon#read 5, iclass 40, count 0 2006.285.11:37:39.59#ibcon#about to read 6, iclass 40, count 0 2006.285.11:37:39.59#ibcon#read 6, iclass 40, count 0 2006.285.11:37:39.59#ibcon#end of sib2, iclass 40, count 0 2006.285.11:37:39.59#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:37:39.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:37:39.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:37:39.59#ibcon#*before write, iclass 40, count 0 2006.285.11:37:39.59#ibcon#enter sib2, iclass 40, count 0 2006.285.11:37:39.59#ibcon#flushed, iclass 40, count 0 2006.285.11:37:39.59#ibcon#about to write, iclass 40, count 0 2006.285.11:37:39.59#ibcon#wrote, iclass 40, count 0 2006.285.11:37:39.59#ibcon#about to read 3, iclass 40, count 0 2006.285.11:37:39.63#ibcon#read 3, iclass 40, count 0 2006.285.11:37:39.63#ibcon#about to read 4, iclass 40, count 0 2006.285.11:37:39.63#ibcon#read 4, iclass 40, count 0 2006.285.11:37:39.63#ibcon#about to read 5, iclass 40, count 0 2006.285.11:37:39.63#ibcon#read 5, iclass 40, count 0 2006.285.11:37:39.63#ibcon#about to read 6, iclass 40, count 0 2006.285.11:37:39.63#ibcon#read 6, iclass 40, count 0 2006.285.11:37:39.63#ibcon#end of sib2, iclass 40, count 0 2006.285.11:37:39.63#ibcon#*after write, iclass 40, count 0 2006.285.11:37:39.63#ibcon#*before return 0, iclass 40, count 0 2006.285.11:37:39.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:37:39.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:37:39.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:37:39.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:37:39.63$vck44/va=3,7 2006.285.11:37:39.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.11:37:39.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.11:37:39.63#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:39.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:37:39.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:37:39.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:37:39.69#ibcon#enter wrdev, iclass 4, count 2 2006.285.11:37:39.69#ibcon#first serial, iclass 4, count 2 2006.285.11:37:39.69#ibcon#enter sib2, iclass 4, count 2 2006.285.11:37:39.69#ibcon#flushed, iclass 4, count 2 2006.285.11:37:39.69#ibcon#about to write, iclass 4, count 2 2006.285.11:37:39.69#ibcon#wrote, iclass 4, count 2 2006.285.11:37:39.69#ibcon#about to read 3, iclass 4, count 2 2006.285.11:37:39.71#ibcon#read 3, iclass 4, count 2 2006.285.11:37:39.71#ibcon#about to read 4, iclass 4, count 2 2006.285.11:37:39.71#ibcon#read 4, iclass 4, count 2 2006.285.11:37:39.71#ibcon#about to read 5, iclass 4, count 2 2006.285.11:37:39.71#ibcon#read 5, iclass 4, count 2 2006.285.11:37:39.71#ibcon#about to read 6, iclass 4, count 2 2006.285.11:37:39.71#ibcon#read 6, iclass 4, count 2 2006.285.11:37:39.71#ibcon#end of sib2, iclass 4, count 2 2006.285.11:37:39.71#ibcon#*mode == 0, iclass 4, count 2 2006.285.11:37:39.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.11:37:39.71#ibcon#[25=AT03-07\r\n] 2006.285.11:37:39.71#ibcon#*before write, iclass 4, count 2 2006.285.11:37:39.71#ibcon#enter sib2, iclass 4, count 2 2006.285.11:37:39.71#ibcon#flushed, iclass 4, count 2 2006.285.11:37:39.71#ibcon#about to write, iclass 4, count 2 2006.285.11:37:39.71#ibcon#wrote, iclass 4, count 2 2006.285.11:37:39.71#ibcon#about to read 3, iclass 4, count 2 2006.285.11:37:39.74#ibcon#read 3, iclass 4, count 2 2006.285.11:37:39.74#ibcon#about to read 4, iclass 4, count 2 2006.285.11:37:39.74#ibcon#read 4, iclass 4, count 2 2006.285.11:37:39.74#ibcon#about to read 5, iclass 4, count 2 2006.285.11:37:39.74#ibcon#read 5, iclass 4, count 2 2006.285.11:37:39.74#ibcon#about to read 6, iclass 4, count 2 2006.285.11:37:39.74#ibcon#read 6, iclass 4, count 2 2006.285.11:37:39.74#ibcon#end of sib2, iclass 4, count 2 2006.285.11:37:39.74#ibcon#*after write, iclass 4, count 2 2006.285.11:37:39.74#ibcon#*before return 0, iclass 4, count 2 2006.285.11:37:39.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:37:39.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:37:39.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.11:37:39.74#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:39.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:37:39.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:37:39.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:37:39.86#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:37:39.86#ibcon#first serial, iclass 4, count 0 2006.285.11:37:39.86#ibcon#enter sib2, iclass 4, count 0 2006.285.11:37:39.86#ibcon#flushed, iclass 4, count 0 2006.285.11:37:39.86#ibcon#about to write, iclass 4, count 0 2006.285.11:37:39.86#ibcon#wrote, iclass 4, count 0 2006.285.11:37:39.86#ibcon#about to read 3, iclass 4, count 0 2006.285.11:37:39.88#ibcon#read 3, iclass 4, count 0 2006.285.11:37:39.88#ibcon#about to read 4, iclass 4, count 0 2006.285.11:37:39.88#ibcon#read 4, iclass 4, count 0 2006.285.11:37:39.88#ibcon#about to read 5, iclass 4, count 0 2006.285.11:37:39.88#ibcon#read 5, iclass 4, count 0 2006.285.11:37:39.88#ibcon#about to read 6, iclass 4, count 0 2006.285.11:37:39.88#ibcon#read 6, iclass 4, count 0 2006.285.11:37:39.88#ibcon#end of sib2, iclass 4, count 0 2006.285.11:37:39.88#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:37:39.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:37:39.88#ibcon#[25=USB\r\n] 2006.285.11:37:39.88#ibcon#*before write, iclass 4, count 0 2006.285.11:37:39.88#ibcon#enter sib2, iclass 4, count 0 2006.285.11:37:39.88#ibcon#flushed, iclass 4, count 0 2006.285.11:37:39.88#ibcon#about to write, iclass 4, count 0 2006.285.11:37:39.88#ibcon#wrote, iclass 4, count 0 2006.285.11:37:39.88#ibcon#about to read 3, iclass 4, count 0 2006.285.11:37:39.91#ibcon#read 3, iclass 4, count 0 2006.285.11:37:39.91#ibcon#about to read 4, iclass 4, count 0 2006.285.11:37:39.91#ibcon#read 4, iclass 4, count 0 2006.285.11:37:39.91#ibcon#about to read 5, iclass 4, count 0 2006.285.11:37:39.91#ibcon#read 5, iclass 4, count 0 2006.285.11:37:39.91#ibcon#about to read 6, iclass 4, count 0 2006.285.11:37:39.91#ibcon#read 6, iclass 4, count 0 2006.285.11:37:39.91#ibcon#end of sib2, iclass 4, count 0 2006.285.11:37:39.91#ibcon#*after write, iclass 4, count 0 2006.285.11:37:39.91#ibcon#*before return 0, iclass 4, count 0 2006.285.11:37:39.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:37:39.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:37:39.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:37:39.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:37:39.91$vck44/valo=4,624.99 2006.285.11:37:39.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.11:37:39.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.11:37:39.91#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:39.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:37:39.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:37:39.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:37:39.91#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:37:39.91#ibcon#first serial, iclass 6, count 0 2006.285.11:37:39.91#ibcon#enter sib2, iclass 6, count 0 2006.285.11:37:39.91#ibcon#flushed, iclass 6, count 0 2006.285.11:37:39.91#ibcon#about to write, iclass 6, count 0 2006.285.11:37:39.91#ibcon#wrote, iclass 6, count 0 2006.285.11:37:39.91#ibcon#about to read 3, iclass 6, count 0 2006.285.11:37:39.93#ibcon#read 3, iclass 6, count 0 2006.285.11:37:39.93#ibcon#about to read 4, iclass 6, count 0 2006.285.11:37:39.93#ibcon#read 4, iclass 6, count 0 2006.285.11:37:39.93#ibcon#about to read 5, iclass 6, count 0 2006.285.11:37:39.93#ibcon#read 5, iclass 6, count 0 2006.285.11:37:39.93#ibcon#about to read 6, iclass 6, count 0 2006.285.11:37:39.93#ibcon#read 6, iclass 6, count 0 2006.285.11:37:39.93#ibcon#end of sib2, iclass 6, count 0 2006.285.11:37:39.93#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:37:39.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:37:39.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:37:39.93#ibcon#*before write, iclass 6, count 0 2006.285.11:37:39.93#ibcon#enter sib2, iclass 6, count 0 2006.285.11:37:39.93#ibcon#flushed, iclass 6, count 0 2006.285.11:37:39.93#ibcon#about to write, iclass 6, count 0 2006.285.11:37:39.93#ibcon#wrote, iclass 6, count 0 2006.285.11:37:39.93#ibcon#about to read 3, iclass 6, count 0 2006.285.11:37:39.97#ibcon#read 3, iclass 6, count 0 2006.285.11:37:39.97#ibcon#about to read 4, iclass 6, count 0 2006.285.11:37:39.97#ibcon#read 4, iclass 6, count 0 2006.285.11:37:39.97#ibcon#about to read 5, iclass 6, count 0 2006.285.11:37:39.97#ibcon#read 5, iclass 6, count 0 2006.285.11:37:39.97#ibcon#about to read 6, iclass 6, count 0 2006.285.11:37:39.97#ibcon#read 6, iclass 6, count 0 2006.285.11:37:39.97#ibcon#end of sib2, iclass 6, count 0 2006.285.11:37:39.97#ibcon#*after write, iclass 6, count 0 2006.285.11:37:39.97#ibcon#*before return 0, iclass 6, count 0 2006.285.11:37:39.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:37:39.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:37:39.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:37:39.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:37:39.97$vck44/va=4,6 2006.285.11:37:39.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.11:37:39.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.11:37:39.97#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:39.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:37:40.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:37:40.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:37:40.03#ibcon#enter wrdev, iclass 10, count 2 2006.285.11:37:40.03#ibcon#first serial, iclass 10, count 2 2006.285.11:37:40.03#ibcon#enter sib2, iclass 10, count 2 2006.285.11:37:40.03#ibcon#flushed, iclass 10, count 2 2006.285.11:37:40.03#ibcon#about to write, iclass 10, count 2 2006.285.11:37:40.03#ibcon#wrote, iclass 10, count 2 2006.285.11:37:40.03#ibcon#about to read 3, iclass 10, count 2 2006.285.11:37:40.05#ibcon#read 3, iclass 10, count 2 2006.285.11:37:40.05#ibcon#about to read 4, iclass 10, count 2 2006.285.11:37:40.05#ibcon#read 4, iclass 10, count 2 2006.285.11:37:40.05#ibcon#about to read 5, iclass 10, count 2 2006.285.11:37:40.05#ibcon#read 5, iclass 10, count 2 2006.285.11:37:40.05#ibcon#about to read 6, iclass 10, count 2 2006.285.11:37:40.05#ibcon#read 6, iclass 10, count 2 2006.285.11:37:40.05#ibcon#end of sib2, iclass 10, count 2 2006.285.11:37:40.05#ibcon#*mode == 0, iclass 10, count 2 2006.285.11:37:40.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.11:37:40.05#ibcon#[25=AT04-06\r\n] 2006.285.11:37:40.05#ibcon#*before write, iclass 10, count 2 2006.285.11:37:40.05#ibcon#enter sib2, iclass 10, count 2 2006.285.11:37:40.05#ibcon#flushed, iclass 10, count 2 2006.285.11:37:40.05#ibcon#about to write, iclass 10, count 2 2006.285.11:37:40.05#ibcon#wrote, iclass 10, count 2 2006.285.11:37:40.05#ibcon#about to read 3, iclass 10, count 2 2006.285.11:37:40.08#ibcon#read 3, iclass 10, count 2 2006.285.11:37:40.08#ibcon#about to read 4, iclass 10, count 2 2006.285.11:37:40.08#ibcon#read 4, iclass 10, count 2 2006.285.11:37:40.08#ibcon#about to read 5, iclass 10, count 2 2006.285.11:37:40.08#ibcon#read 5, iclass 10, count 2 2006.285.11:37:40.08#ibcon#about to read 6, iclass 10, count 2 2006.285.11:37:40.08#ibcon#read 6, iclass 10, count 2 2006.285.11:37:40.08#ibcon#end of sib2, iclass 10, count 2 2006.285.11:37:40.08#ibcon#*after write, iclass 10, count 2 2006.285.11:37:40.08#ibcon#*before return 0, iclass 10, count 2 2006.285.11:37:40.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:37:40.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:37:40.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.11:37:40.08#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:40.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:37:40.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:37:40.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:37:40.20#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:37:40.20#ibcon#first serial, iclass 10, count 0 2006.285.11:37:40.20#ibcon#enter sib2, iclass 10, count 0 2006.285.11:37:40.20#ibcon#flushed, iclass 10, count 0 2006.285.11:37:40.20#ibcon#about to write, iclass 10, count 0 2006.285.11:37:40.20#ibcon#wrote, iclass 10, count 0 2006.285.11:37:40.20#ibcon#about to read 3, iclass 10, count 0 2006.285.11:37:40.22#ibcon#read 3, iclass 10, count 0 2006.285.11:37:40.22#ibcon#about to read 4, iclass 10, count 0 2006.285.11:37:40.22#ibcon#read 4, iclass 10, count 0 2006.285.11:37:40.22#ibcon#about to read 5, iclass 10, count 0 2006.285.11:37:40.22#ibcon#read 5, iclass 10, count 0 2006.285.11:37:40.22#ibcon#about to read 6, iclass 10, count 0 2006.285.11:37:40.22#ibcon#read 6, iclass 10, count 0 2006.285.11:37:40.22#ibcon#end of sib2, iclass 10, count 0 2006.285.11:37:40.22#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:37:40.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:37:40.22#ibcon#[25=USB\r\n] 2006.285.11:37:40.22#ibcon#*before write, iclass 10, count 0 2006.285.11:37:40.22#ibcon#enter sib2, iclass 10, count 0 2006.285.11:37:40.22#ibcon#flushed, iclass 10, count 0 2006.285.11:37:40.22#ibcon#about to write, iclass 10, count 0 2006.285.11:37:40.22#ibcon#wrote, iclass 10, count 0 2006.285.11:37:40.22#ibcon#about to read 3, iclass 10, count 0 2006.285.11:37:40.25#ibcon#read 3, iclass 10, count 0 2006.285.11:37:40.25#ibcon#about to read 4, iclass 10, count 0 2006.285.11:37:40.25#ibcon#read 4, iclass 10, count 0 2006.285.11:37:40.25#ibcon#about to read 5, iclass 10, count 0 2006.285.11:37:40.25#ibcon#read 5, iclass 10, count 0 2006.285.11:37:40.25#ibcon#about to read 6, iclass 10, count 0 2006.285.11:37:40.25#ibcon#read 6, iclass 10, count 0 2006.285.11:37:40.25#ibcon#end of sib2, iclass 10, count 0 2006.285.11:37:40.25#ibcon#*after write, iclass 10, count 0 2006.285.11:37:40.25#ibcon#*before return 0, iclass 10, count 0 2006.285.11:37:40.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:37:40.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:37:40.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:37:40.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:37:40.25$vck44/valo=5,734.99 2006.285.11:37:40.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.11:37:40.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.11:37:40.25#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:40.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:37:40.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:37:40.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:37:40.25#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:37:40.25#ibcon#first serial, iclass 12, count 0 2006.285.11:37:40.25#ibcon#enter sib2, iclass 12, count 0 2006.285.11:37:40.25#ibcon#flushed, iclass 12, count 0 2006.285.11:37:40.25#ibcon#about to write, iclass 12, count 0 2006.285.11:37:40.25#ibcon#wrote, iclass 12, count 0 2006.285.11:37:40.25#ibcon#about to read 3, iclass 12, count 0 2006.285.11:37:40.27#ibcon#read 3, iclass 12, count 0 2006.285.11:37:40.27#ibcon#about to read 4, iclass 12, count 0 2006.285.11:37:40.27#ibcon#read 4, iclass 12, count 0 2006.285.11:37:40.27#ibcon#about to read 5, iclass 12, count 0 2006.285.11:37:40.27#ibcon#read 5, iclass 12, count 0 2006.285.11:37:40.27#ibcon#about to read 6, iclass 12, count 0 2006.285.11:37:40.27#ibcon#read 6, iclass 12, count 0 2006.285.11:37:40.27#ibcon#end of sib2, iclass 12, count 0 2006.285.11:37:40.27#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:37:40.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:37:40.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:37:40.27#ibcon#*before write, iclass 12, count 0 2006.285.11:37:40.27#ibcon#enter sib2, iclass 12, count 0 2006.285.11:37:40.27#ibcon#flushed, iclass 12, count 0 2006.285.11:37:40.27#ibcon#about to write, iclass 12, count 0 2006.285.11:37:40.27#ibcon#wrote, iclass 12, count 0 2006.285.11:37:40.27#ibcon#about to read 3, iclass 12, count 0 2006.285.11:37:40.31#ibcon#read 3, iclass 12, count 0 2006.285.11:37:40.31#ibcon#about to read 4, iclass 12, count 0 2006.285.11:37:40.31#ibcon#read 4, iclass 12, count 0 2006.285.11:37:40.31#ibcon#about to read 5, iclass 12, count 0 2006.285.11:37:40.31#ibcon#read 5, iclass 12, count 0 2006.285.11:37:40.31#ibcon#about to read 6, iclass 12, count 0 2006.285.11:37:40.31#ibcon#read 6, iclass 12, count 0 2006.285.11:37:40.31#ibcon#end of sib2, iclass 12, count 0 2006.285.11:37:40.31#ibcon#*after write, iclass 12, count 0 2006.285.11:37:40.31#ibcon#*before return 0, iclass 12, count 0 2006.285.11:37:40.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:37:40.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:37:40.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:37:40.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:37:40.31$vck44/va=5,3 2006.285.11:37:40.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.11:37:40.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.11:37:40.31#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:40.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:37:40.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:37:40.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:37:40.37#ibcon#enter wrdev, iclass 14, count 2 2006.285.11:37:40.37#ibcon#first serial, iclass 14, count 2 2006.285.11:37:40.37#ibcon#enter sib2, iclass 14, count 2 2006.285.11:37:40.37#ibcon#flushed, iclass 14, count 2 2006.285.11:37:40.37#ibcon#about to write, iclass 14, count 2 2006.285.11:37:40.37#ibcon#wrote, iclass 14, count 2 2006.285.11:37:40.37#ibcon#about to read 3, iclass 14, count 2 2006.285.11:37:40.39#ibcon#read 3, iclass 14, count 2 2006.285.11:37:40.39#ibcon#about to read 4, iclass 14, count 2 2006.285.11:37:40.39#ibcon#read 4, iclass 14, count 2 2006.285.11:37:40.39#ibcon#about to read 5, iclass 14, count 2 2006.285.11:37:40.39#ibcon#read 5, iclass 14, count 2 2006.285.11:37:40.39#ibcon#about to read 6, iclass 14, count 2 2006.285.11:37:40.39#ibcon#read 6, iclass 14, count 2 2006.285.11:37:40.39#ibcon#end of sib2, iclass 14, count 2 2006.285.11:37:40.39#ibcon#*mode == 0, iclass 14, count 2 2006.285.11:37:40.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.11:37:40.39#ibcon#[25=AT05-03\r\n] 2006.285.11:37:40.39#ibcon#*before write, iclass 14, count 2 2006.285.11:37:40.39#ibcon#enter sib2, iclass 14, count 2 2006.285.11:37:40.39#ibcon#flushed, iclass 14, count 2 2006.285.11:37:40.39#ibcon#about to write, iclass 14, count 2 2006.285.11:37:40.39#ibcon#wrote, iclass 14, count 2 2006.285.11:37:40.39#ibcon#about to read 3, iclass 14, count 2 2006.285.11:37:40.42#ibcon#read 3, iclass 14, count 2 2006.285.11:37:40.42#ibcon#about to read 4, iclass 14, count 2 2006.285.11:37:40.42#ibcon#read 4, iclass 14, count 2 2006.285.11:37:40.42#ibcon#about to read 5, iclass 14, count 2 2006.285.11:37:40.42#ibcon#read 5, iclass 14, count 2 2006.285.11:37:40.42#ibcon#about to read 6, iclass 14, count 2 2006.285.11:37:40.42#ibcon#read 6, iclass 14, count 2 2006.285.11:37:40.42#ibcon#end of sib2, iclass 14, count 2 2006.285.11:37:40.42#ibcon#*after write, iclass 14, count 2 2006.285.11:37:40.42#ibcon#*before return 0, iclass 14, count 2 2006.285.11:37:40.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:37:40.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:37:40.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.11:37:40.42#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:40.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:37:40.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:37:40.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:37:40.54#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:37:40.54#ibcon#first serial, iclass 14, count 0 2006.285.11:37:40.54#ibcon#enter sib2, iclass 14, count 0 2006.285.11:37:40.54#ibcon#flushed, iclass 14, count 0 2006.285.11:37:40.54#ibcon#about to write, iclass 14, count 0 2006.285.11:37:40.54#ibcon#wrote, iclass 14, count 0 2006.285.11:37:40.54#ibcon#about to read 3, iclass 14, count 0 2006.285.11:37:40.56#ibcon#read 3, iclass 14, count 0 2006.285.11:37:40.56#ibcon#about to read 4, iclass 14, count 0 2006.285.11:37:40.56#ibcon#read 4, iclass 14, count 0 2006.285.11:37:40.56#ibcon#about to read 5, iclass 14, count 0 2006.285.11:37:40.56#ibcon#read 5, iclass 14, count 0 2006.285.11:37:40.56#ibcon#about to read 6, iclass 14, count 0 2006.285.11:37:40.56#ibcon#read 6, iclass 14, count 0 2006.285.11:37:40.56#ibcon#end of sib2, iclass 14, count 0 2006.285.11:37:40.56#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:37:40.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:37:40.56#ibcon#[25=USB\r\n] 2006.285.11:37:40.56#ibcon#*before write, iclass 14, count 0 2006.285.11:37:40.56#ibcon#enter sib2, iclass 14, count 0 2006.285.11:37:40.56#ibcon#flushed, iclass 14, count 0 2006.285.11:37:40.56#ibcon#about to write, iclass 14, count 0 2006.285.11:37:40.56#ibcon#wrote, iclass 14, count 0 2006.285.11:37:40.56#ibcon#about to read 3, iclass 14, count 0 2006.285.11:37:40.59#ibcon#read 3, iclass 14, count 0 2006.285.11:37:40.59#ibcon#about to read 4, iclass 14, count 0 2006.285.11:37:40.59#ibcon#read 4, iclass 14, count 0 2006.285.11:37:40.59#ibcon#about to read 5, iclass 14, count 0 2006.285.11:37:40.59#ibcon#read 5, iclass 14, count 0 2006.285.11:37:40.59#ibcon#about to read 6, iclass 14, count 0 2006.285.11:37:40.59#ibcon#read 6, iclass 14, count 0 2006.285.11:37:40.59#ibcon#end of sib2, iclass 14, count 0 2006.285.11:37:40.59#ibcon#*after write, iclass 14, count 0 2006.285.11:37:40.59#ibcon#*before return 0, iclass 14, count 0 2006.285.11:37:40.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:37:40.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:37:40.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:37:40.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:37:40.59$vck44/valo=6,814.99 2006.285.11:37:40.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.11:37:40.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.11:37:40.59#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:40.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:37:40.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:37:40.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:37:40.59#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:37:40.59#ibcon#first serial, iclass 16, count 0 2006.285.11:37:40.59#ibcon#enter sib2, iclass 16, count 0 2006.285.11:37:40.59#ibcon#flushed, iclass 16, count 0 2006.285.11:37:40.59#ibcon#about to write, iclass 16, count 0 2006.285.11:37:40.59#ibcon#wrote, iclass 16, count 0 2006.285.11:37:40.59#ibcon#about to read 3, iclass 16, count 0 2006.285.11:37:40.61#ibcon#read 3, iclass 16, count 0 2006.285.11:37:40.61#ibcon#about to read 4, iclass 16, count 0 2006.285.11:37:40.61#ibcon#read 4, iclass 16, count 0 2006.285.11:37:40.61#ibcon#about to read 5, iclass 16, count 0 2006.285.11:37:40.61#ibcon#read 5, iclass 16, count 0 2006.285.11:37:40.61#ibcon#about to read 6, iclass 16, count 0 2006.285.11:37:40.61#ibcon#read 6, iclass 16, count 0 2006.285.11:37:40.61#ibcon#end of sib2, iclass 16, count 0 2006.285.11:37:40.61#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:37:40.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:37:40.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:37:40.61#ibcon#*before write, iclass 16, count 0 2006.285.11:37:40.61#ibcon#enter sib2, iclass 16, count 0 2006.285.11:37:40.61#ibcon#flushed, iclass 16, count 0 2006.285.11:37:40.61#ibcon#about to write, iclass 16, count 0 2006.285.11:37:40.61#ibcon#wrote, iclass 16, count 0 2006.285.11:37:40.61#ibcon#about to read 3, iclass 16, count 0 2006.285.11:37:40.65#ibcon#read 3, iclass 16, count 0 2006.285.11:37:40.65#ibcon#about to read 4, iclass 16, count 0 2006.285.11:37:40.65#ibcon#read 4, iclass 16, count 0 2006.285.11:37:40.65#ibcon#about to read 5, iclass 16, count 0 2006.285.11:37:40.65#ibcon#read 5, iclass 16, count 0 2006.285.11:37:40.65#ibcon#about to read 6, iclass 16, count 0 2006.285.11:37:40.65#ibcon#read 6, iclass 16, count 0 2006.285.11:37:40.65#ibcon#end of sib2, iclass 16, count 0 2006.285.11:37:40.65#ibcon#*after write, iclass 16, count 0 2006.285.11:37:40.65#ibcon#*before return 0, iclass 16, count 0 2006.285.11:37:40.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:37:40.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:37:40.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:37:40.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:37:40.65$vck44/va=6,4 2006.285.11:37:40.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.11:37:40.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.11:37:40.65#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:40.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:37:40.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:37:40.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:37:40.71#ibcon#enter wrdev, iclass 18, count 2 2006.285.11:37:40.71#ibcon#first serial, iclass 18, count 2 2006.285.11:37:40.71#ibcon#enter sib2, iclass 18, count 2 2006.285.11:37:40.71#ibcon#flushed, iclass 18, count 2 2006.285.11:37:40.71#ibcon#about to write, iclass 18, count 2 2006.285.11:37:40.71#ibcon#wrote, iclass 18, count 2 2006.285.11:37:40.71#ibcon#about to read 3, iclass 18, count 2 2006.285.11:37:40.73#ibcon#read 3, iclass 18, count 2 2006.285.11:37:40.73#ibcon#about to read 4, iclass 18, count 2 2006.285.11:37:40.73#ibcon#read 4, iclass 18, count 2 2006.285.11:37:40.73#ibcon#about to read 5, iclass 18, count 2 2006.285.11:37:40.73#ibcon#read 5, iclass 18, count 2 2006.285.11:37:40.73#ibcon#about to read 6, iclass 18, count 2 2006.285.11:37:40.73#ibcon#read 6, iclass 18, count 2 2006.285.11:37:40.73#ibcon#end of sib2, iclass 18, count 2 2006.285.11:37:40.73#ibcon#*mode == 0, iclass 18, count 2 2006.285.11:37:40.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.11:37:40.73#ibcon#[25=AT06-04\r\n] 2006.285.11:37:40.73#ibcon#*before write, iclass 18, count 2 2006.285.11:37:40.73#ibcon#enter sib2, iclass 18, count 2 2006.285.11:37:40.73#ibcon#flushed, iclass 18, count 2 2006.285.11:37:40.73#ibcon#about to write, iclass 18, count 2 2006.285.11:37:40.73#ibcon#wrote, iclass 18, count 2 2006.285.11:37:40.73#ibcon#about to read 3, iclass 18, count 2 2006.285.11:37:40.76#ibcon#read 3, iclass 18, count 2 2006.285.11:37:40.76#ibcon#about to read 4, iclass 18, count 2 2006.285.11:37:40.76#ibcon#read 4, iclass 18, count 2 2006.285.11:37:40.76#ibcon#about to read 5, iclass 18, count 2 2006.285.11:37:40.76#ibcon#read 5, iclass 18, count 2 2006.285.11:37:40.76#ibcon#about to read 6, iclass 18, count 2 2006.285.11:37:40.76#ibcon#read 6, iclass 18, count 2 2006.285.11:37:40.76#ibcon#end of sib2, iclass 18, count 2 2006.285.11:37:40.76#ibcon#*after write, iclass 18, count 2 2006.285.11:37:40.76#ibcon#*before return 0, iclass 18, count 2 2006.285.11:37:40.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:37:40.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:37:40.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.11:37:40.76#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:40.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:37:40.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:37:40.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:37:40.88#ibcon#enter wrdev, iclass 18, count 0 2006.285.11:37:40.88#ibcon#first serial, iclass 18, count 0 2006.285.11:37:40.88#ibcon#enter sib2, iclass 18, count 0 2006.285.11:37:40.88#ibcon#flushed, iclass 18, count 0 2006.285.11:37:40.88#ibcon#about to write, iclass 18, count 0 2006.285.11:37:40.88#ibcon#wrote, iclass 18, count 0 2006.285.11:37:40.88#ibcon#about to read 3, iclass 18, count 0 2006.285.11:37:40.90#ibcon#read 3, iclass 18, count 0 2006.285.11:37:40.90#ibcon#about to read 4, iclass 18, count 0 2006.285.11:37:40.90#ibcon#read 4, iclass 18, count 0 2006.285.11:37:40.90#ibcon#about to read 5, iclass 18, count 0 2006.285.11:37:40.90#ibcon#read 5, iclass 18, count 0 2006.285.11:37:40.90#ibcon#about to read 6, iclass 18, count 0 2006.285.11:37:40.90#ibcon#read 6, iclass 18, count 0 2006.285.11:37:40.90#ibcon#end of sib2, iclass 18, count 0 2006.285.11:37:40.90#ibcon#*mode == 0, iclass 18, count 0 2006.285.11:37:40.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.11:37:40.90#ibcon#[25=USB\r\n] 2006.285.11:37:40.90#ibcon#*before write, iclass 18, count 0 2006.285.11:37:40.90#ibcon#enter sib2, iclass 18, count 0 2006.285.11:37:40.90#ibcon#flushed, iclass 18, count 0 2006.285.11:37:40.90#ibcon#about to write, iclass 18, count 0 2006.285.11:37:40.90#ibcon#wrote, iclass 18, count 0 2006.285.11:37:40.90#ibcon#about to read 3, iclass 18, count 0 2006.285.11:37:40.93#ibcon#read 3, iclass 18, count 0 2006.285.11:37:40.93#ibcon#about to read 4, iclass 18, count 0 2006.285.11:37:40.93#ibcon#read 4, iclass 18, count 0 2006.285.11:37:40.93#ibcon#about to read 5, iclass 18, count 0 2006.285.11:37:40.93#ibcon#read 5, iclass 18, count 0 2006.285.11:37:40.93#ibcon#about to read 6, iclass 18, count 0 2006.285.11:37:40.93#ibcon#read 6, iclass 18, count 0 2006.285.11:37:40.93#ibcon#end of sib2, iclass 18, count 0 2006.285.11:37:40.93#ibcon#*after write, iclass 18, count 0 2006.285.11:37:40.93#ibcon#*before return 0, iclass 18, count 0 2006.285.11:37:40.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:37:40.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:37:40.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.11:37:40.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.11:37:40.93$vck44/valo=7,864.99 2006.285.11:37:40.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.11:37:40.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.11:37:40.93#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:40.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:37:40.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:37:40.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:37:40.93#ibcon#enter wrdev, iclass 20, count 0 2006.285.11:37:40.93#ibcon#first serial, iclass 20, count 0 2006.285.11:37:40.93#ibcon#enter sib2, iclass 20, count 0 2006.285.11:37:40.93#ibcon#flushed, iclass 20, count 0 2006.285.11:37:40.93#ibcon#about to write, iclass 20, count 0 2006.285.11:37:40.93#ibcon#wrote, iclass 20, count 0 2006.285.11:37:40.93#ibcon#about to read 3, iclass 20, count 0 2006.285.11:37:40.95#ibcon#read 3, iclass 20, count 0 2006.285.11:37:40.95#ibcon#about to read 4, iclass 20, count 0 2006.285.11:37:40.95#ibcon#read 4, iclass 20, count 0 2006.285.11:37:40.95#ibcon#about to read 5, iclass 20, count 0 2006.285.11:37:40.95#ibcon#read 5, iclass 20, count 0 2006.285.11:37:40.95#ibcon#about to read 6, iclass 20, count 0 2006.285.11:37:40.95#ibcon#read 6, iclass 20, count 0 2006.285.11:37:40.95#ibcon#end of sib2, iclass 20, count 0 2006.285.11:37:40.95#ibcon#*mode == 0, iclass 20, count 0 2006.285.11:37:40.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.11:37:40.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:37:40.95#ibcon#*before write, iclass 20, count 0 2006.285.11:37:40.95#ibcon#enter sib2, iclass 20, count 0 2006.285.11:37:40.95#ibcon#flushed, iclass 20, count 0 2006.285.11:37:40.95#ibcon#about to write, iclass 20, count 0 2006.285.11:37:40.95#ibcon#wrote, iclass 20, count 0 2006.285.11:37:40.95#ibcon#about to read 3, iclass 20, count 0 2006.285.11:37:40.99#ibcon#read 3, iclass 20, count 0 2006.285.11:37:40.99#ibcon#about to read 4, iclass 20, count 0 2006.285.11:37:40.99#ibcon#read 4, iclass 20, count 0 2006.285.11:37:40.99#ibcon#about to read 5, iclass 20, count 0 2006.285.11:37:40.99#ibcon#read 5, iclass 20, count 0 2006.285.11:37:40.99#ibcon#about to read 6, iclass 20, count 0 2006.285.11:37:40.99#ibcon#read 6, iclass 20, count 0 2006.285.11:37:40.99#ibcon#end of sib2, iclass 20, count 0 2006.285.11:37:40.99#ibcon#*after write, iclass 20, count 0 2006.285.11:37:40.99#ibcon#*before return 0, iclass 20, count 0 2006.285.11:37:40.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:37:40.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:37:40.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.11:37:40.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.11:37:40.99$vck44/va=7,4 2006.285.11:37:40.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.11:37:40.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.11:37:40.99#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:40.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:37:41.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:37:41.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:37:41.05#ibcon#enter wrdev, iclass 22, count 2 2006.285.11:37:41.05#ibcon#first serial, iclass 22, count 2 2006.285.11:37:41.05#ibcon#enter sib2, iclass 22, count 2 2006.285.11:37:41.05#ibcon#flushed, iclass 22, count 2 2006.285.11:37:41.05#ibcon#about to write, iclass 22, count 2 2006.285.11:37:41.05#ibcon#wrote, iclass 22, count 2 2006.285.11:37:41.05#ibcon#about to read 3, iclass 22, count 2 2006.285.11:37:41.07#ibcon#read 3, iclass 22, count 2 2006.285.11:37:41.07#ibcon#about to read 4, iclass 22, count 2 2006.285.11:37:41.07#ibcon#read 4, iclass 22, count 2 2006.285.11:37:41.07#ibcon#about to read 5, iclass 22, count 2 2006.285.11:37:41.07#ibcon#read 5, iclass 22, count 2 2006.285.11:37:41.07#ibcon#about to read 6, iclass 22, count 2 2006.285.11:37:41.07#ibcon#read 6, iclass 22, count 2 2006.285.11:37:41.07#ibcon#end of sib2, iclass 22, count 2 2006.285.11:37:41.07#ibcon#*mode == 0, iclass 22, count 2 2006.285.11:37:41.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.11:37:41.07#ibcon#[25=AT07-04\r\n] 2006.285.11:37:41.07#ibcon#*before write, iclass 22, count 2 2006.285.11:37:41.07#ibcon#enter sib2, iclass 22, count 2 2006.285.11:37:41.07#ibcon#flushed, iclass 22, count 2 2006.285.11:37:41.07#ibcon#about to write, iclass 22, count 2 2006.285.11:37:41.07#ibcon#wrote, iclass 22, count 2 2006.285.11:37:41.07#ibcon#about to read 3, iclass 22, count 2 2006.285.11:37:41.10#ibcon#read 3, iclass 22, count 2 2006.285.11:37:41.10#ibcon#about to read 4, iclass 22, count 2 2006.285.11:37:41.10#ibcon#read 4, iclass 22, count 2 2006.285.11:37:41.10#ibcon#about to read 5, iclass 22, count 2 2006.285.11:37:41.10#ibcon#read 5, iclass 22, count 2 2006.285.11:37:41.10#ibcon#about to read 6, iclass 22, count 2 2006.285.11:37:41.10#ibcon#read 6, iclass 22, count 2 2006.285.11:37:41.10#ibcon#end of sib2, iclass 22, count 2 2006.285.11:37:41.10#ibcon#*after write, iclass 22, count 2 2006.285.11:37:41.10#ibcon#*before return 0, iclass 22, count 2 2006.285.11:37:41.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:37:41.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:37:41.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.11:37:41.10#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:41.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:37:41.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:37:41.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:37:41.22#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:37:41.22#ibcon#first serial, iclass 22, count 0 2006.285.11:37:41.22#ibcon#enter sib2, iclass 22, count 0 2006.285.11:37:41.22#ibcon#flushed, iclass 22, count 0 2006.285.11:37:41.22#ibcon#about to write, iclass 22, count 0 2006.285.11:37:41.22#ibcon#wrote, iclass 22, count 0 2006.285.11:37:41.22#ibcon#about to read 3, iclass 22, count 0 2006.285.11:37:41.24#ibcon#read 3, iclass 22, count 0 2006.285.11:37:41.24#ibcon#about to read 4, iclass 22, count 0 2006.285.11:37:41.24#ibcon#read 4, iclass 22, count 0 2006.285.11:37:41.24#ibcon#about to read 5, iclass 22, count 0 2006.285.11:37:41.24#ibcon#read 5, iclass 22, count 0 2006.285.11:37:41.24#ibcon#about to read 6, iclass 22, count 0 2006.285.11:37:41.24#ibcon#read 6, iclass 22, count 0 2006.285.11:37:41.24#ibcon#end of sib2, iclass 22, count 0 2006.285.11:37:41.24#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:37:41.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:37:41.24#ibcon#[25=USB\r\n] 2006.285.11:37:41.24#ibcon#*before write, iclass 22, count 0 2006.285.11:37:41.24#ibcon#enter sib2, iclass 22, count 0 2006.285.11:37:41.24#ibcon#flushed, iclass 22, count 0 2006.285.11:37:41.24#ibcon#about to write, iclass 22, count 0 2006.285.11:37:41.24#ibcon#wrote, iclass 22, count 0 2006.285.11:37:41.24#ibcon#about to read 3, iclass 22, count 0 2006.285.11:37:41.27#ibcon#read 3, iclass 22, count 0 2006.285.11:37:41.27#ibcon#about to read 4, iclass 22, count 0 2006.285.11:37:41.27#ibcon#read 4, iclass 22, count 0 2006.285.11:37:41.27#ibcon#about to read 5, iclass 22, count 0 2006.285.11:37:41.27#ibcon#read 5, iclass 22, count 0 2006.285.11:37:41.27#ibcon#about to read 6, iclass 22, count 0 2006.285.11:37:41.27#ibcon#read 6, iclass 22, count 0 2006.285.11:37:41.27#ibcon#end of sib2, iclass 22, count 0 2006.285.11:37:41.27#ibcon#*after write, iclass 22, count 0 2006.285.11:37:41.27#ibcon#*before return 0, iclass 22, count 0 2006.285.11:37:41.27#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:37:41.27#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:37:41.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:37:41.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:37:41.27$vck44/valo=8,884.99 2006.285.11:37:41.27#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.11:37:41.27#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.11:37:41.27#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:41.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:37:41.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:37:41.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:37:41.27#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:37:41.27#ibcon#first serial, iclass 24, count 0 2006.285.11:37:41.27#ibcon#enter sib2, iclass 24, count 0 2006.285.11:37:41.27#ibcon#flushed, iclass 24, count 0 2006.285.11:37:41.27#ibcon#about to write, iclass 24, count 0 2006.285.11:37:41.27#ibcon#wrote, iclass 24, count 0 2006.285.11:37:41.27#ibcon#about to read 3, iclass 24, count 0 2006.285.11:37:41.29#ibcon#read 3, iclass 24, count 0 2006.285.11:37:41.29#ibcon#about to read 4, iclass 24, count 0 2006.285.11:37:41.29#ibcon#read 4, iclass 24, count 0 2006.285.11:37:41.29#ibcon#about to read 5, iclass 24, count 0 2006.285.11:37:41.29#ibcon#read 5, iclass 24, count 0 2006.285.11:37:41.29#ibcon#about to read 6, iclass 24, count 0 2006.285.11:37:41.29#ibcon#read 6, iclass 24, count 0 2006.285.11:37:41.29#ibcon#end of sib2, iclass 24, count 0 2006.285.11:37:41.29#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:37:41.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:37:41.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:37:41.29#ibcon#*before write, iclass 24, count 0 2006.285.11:37:41.29#ibcon#enter sib2, iclass 24, count 0 2006.285.11:37:41.29#ibcon#flushed, iclass 24, count 0 2006.285.11:37:41.29#ibcon#about to write, iclass 24, count 0 2006.285.11:37:41.29#ibcon#wrote, iclass 24, count 0 2006.285.11:37:41.29#ibcon#about to read 3, iclass 24, count 0 2006.285.11:37:41.33#ibcon#read 3, iclass 24, count 0 2006.285.11:37:41.33#ibcon#about to read 4, iclass 24, count 0 2006.285.11:37:41.33#ibcon#read 4, iclass 24, count 0 2006.285.11:37:41.33#ibcon#about to read 5, iclass 24, count 0 2006.285.11:37:41.33#ibcon#read 5, iclass 24, count 0 2006.285.11:37:41.33#ibcon#about to read 6, iclass 24, count 0 2006.285.11:37:41.33#ibcon#read 6, iclass 24, count 0 2006.285.11:37:41.33#ibcon#end of sib2, iclass 24, count 0 2006.285.11:37:41.33#ibcon#*after write, iclass 24, count 0 2006.285.11:37:41.33#ibcon#*before return 0, iclass 24, count 0 2006.285.11:37:41.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:37:41.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:37:41.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:37:41.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:37:41.33$vck44/va=8,3 2006.285.11:37:41.33#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.11:37:41.33#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.11:37:41.33#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:41.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:37:41.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:37:41.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:37:41.39#ibcon#enter wrdev, iclass 26, count 2 2006.285.11:37:41.39#ibcon#first serial, iclass 26, count 2 2006.285.11:37:41.39#ibcon#enter sib2, iclass 26, count 2 2006.285.11:37:41.39#ibcon#flushed, iclass 26, count 2 2006.285.11:37:41.39#ibcon#about to write, iclass 26, count 2 2006.285.11:37:41.39#ibcon#wrote, iclass 26, count 2 2006.285.11:37:41.39#ibcon#about to read 3, iclass 26, count 2 2006.285.11:37:41.41#ibcon#read 3, iclass 26, count 2 2006.285.11:37:41.41#ibcon#about to read 4, iclass 26, count 2 2006.285.11:37:41.41#ibcon#read 4, iclass 26, count 2 2006.285.11:37:41.41#ibcon#about to read 5, iclass 26, count 2 2006.285.11:37:41.41#ibcon#read 5, iclass 26, count 2 2006.285.11:37:41.41#ibcon#about to read 6, iclass 26, count 2 2006.285.11:37:41.41#ibcon#read 6, iclass 26, count 2 2006.285.11:37:41.41#ibcon#end of sib2, iclass 26, count 2 2006.285.11:37:41.41#ibcon#*mode == 0, iclass 26, count 2 2006.285.11:37:41.41#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.11:37:41.41#ibcon#[25=AT08-03\r\n] 2006.285.11:37:41.41#ibcon#*before write, iclass 26, count 2 2006.285.11:37:41.41#ibcon#enter sib2, iclass 26, count 2 2006.285.11:37:41.41#ibcon#flushed, iclass 26, count 2 2006.285.11:37:41.41#ibcon#about to write, iclass 26, count 2 2006.285.11:37:41.41#ibcon#wrote, iclass 26, count 2 2006.285.11:37:41.41#ibcon#about to read 3, iclass 26, count 2 2006.285.11:37:41.44#ibcon#read 3, iclass 26, count 2 2006.285.11:37:41.44#ibcon#about to read 4, iclass 26, count 2 2006.285.11:37:41.44#ibcon#read 4, iclass 26, count 2 2006.285.11:37:41.44#ibcon#about to read 5, iclass 26, count 2 2006.285.11:37:41.44#ibcon#read 5, iclass 26, count 2 2006.285.11:37:41.44#ibcon#about to read 6, iclass 26, count 2 2006.285.11:37:41.44#ibcon#read 6, iclass 26, count 2 2006.285.11:37:41.44#ibcon#end of sib2, iclass 26, count 2 2006.285.11:37:41.44#ibcon#*after write, iclass 26, count 2 2006.285.11:37:41.44#ibcon#*before return 0, iclass 26, count 2 2006.285.11:37:41.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:37:41.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:37:41.44#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.11:37:41.44#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:41.44#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:37:41.56#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:37:41.56#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:37:41.56#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:37:41.56#ibcon#first serial, iclass 26, count 0 2006.285.11:37:41.56#ibcon#enter sib2, iclass 26, count 0 2006.285.11:37:41.56#ibcon#flushed, iclass 26, count 0 2006.285.11:37:41.56#ibcon#about to write, iclass 26, count 0 2006.285.11:37:41.56#ibcon#wrote, iclass 26, count 0 2006.285.11:37:41.56#ibcon#about to read 3, iclass 26, count 0 2006.285.11:37:41.58#ibcon#read 3, iclass 26, count 0 2006.285.11:37:41.58#ibcon#about to read 4, iclass 26, count 0 2006.285.11:37:41.58#ibcon#read 4, iclass 26, count 0 2006.285.11:37:41.58#ibcon#about to read 5, iclass 26, count 0 2006.285.11:37:41.58#ibcon#read 5, iclass 26, count 0 2006.285.11:37:41.58#ibcon#about to read 6, iclass 26, count 0 2006.285.11:37:41.58#ibcon#read 6, iclass 26, count 0 2006.285.11:37:41.58#ibcon#end of sib2, iclass 26, count 0 2006.285.11:37:41.58#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:37:41.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:37:41.58#ibcon#[25=USB\r\n] 2006.285.11:37:41.58#ibcon#*before write, iclass 26, count 0 2006.285.11:37:41.58#ibcon#enter sib2, iclass 26, count 0 2006.285.11:37:41.58#ibcon#flushed, iclass 26, count 0 2006.285.11:37:41.58#ibcon#about to write, iclass 26, count 0 2006.285.11:37:41.58#ibcon#wrote, iclass 26, count 0 2006.285.11:37:41.58#ibcon#about to read 3, iclass 26, count 0 2006.285.11:37:41.61#ibcon#read 3, iclass 26, count 0 2006.285.11:37:41.61#ibcon#about to read 4, iclass 26, count 0 2006.285.11:37:41.61#ibcon#read 4, iclass 26, count 0 2006.285.11:37:41.61#ibcon#about to read 5, iclass 26, count 0 2006.285.11:37:41.61#ibcon#read 5, iclass 26, count 0 2006.285.11:37:41.61#ibcon#about to read 6, iclass 26, count 0 2006.285.11:37:41.61#ibcon#read 6, iclass 26, count 0 2006.285.11:37:41.61#ibcon#end of sib2, iclass 26, count 0 2006.285.11:37:41.61#ibcon#*after write, iclass 26, count 0 2006.285.11:37:41.61#ibcon#*before return 0, iclass 26, count 0 2006.285.11:37:41.61#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:37:41.61#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:37:41.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:37:41.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:37:41.61$vck44/vblo=1,629.99 2006.285.11:37:41.61#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.11:37:41.61#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.11:37:41.61#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:41.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:37:41.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:37:41.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:37:41.61#ibcon#enter wrdev, iclass 28, count 0 2006.285.11:37:41.61#ibcon#first serial, iclass 28, count 0 2006.285.11:37:41.61#ibcon#enter sib2, iclass 28, count 0 2006.285.11:37:41.61#ibcon#flushed, iclass 28, count 0 2006.285.11:37:41.61#ibcon#about to write, iclass 28, count 0 2006.285.11:37:41.61#ibcon#wrote, iclass 28, count 0 2006.285.11:37:41.61#ibcon#about to read 3, iclass 28, count 0 2006.285.11:37:41.63#ibcon#read 3, iclass 28, count 0 2006.285.11:37:41.63#ibcon#about to read 4, iclass 28, count 0 2006.285.11:37:41.63#ibcon#read 4, iclass 28, count 0 2006.285.11:37:41.63#ibcon#about to read 5, iclass 28, count 0 2006.285.11:37:41.63#ibcon#read 5, iclass 28, count 0 2006.285.11:37:41.63#ibcon#about to read 6, iclass 28, count 0 2006.285.11:37:41.63#ibcon#read 6, iclass 28, count 0 2006.285.11:37:41.63#ibcon#end of sib2, iclass 28, count 0 2006.285.11:37:41.63#ibcon#*mode == 0, iclass 28, count 0 2006.285.11:37:41.63#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.11:37:41.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:37:41.63#ibcon#*before write, iclass 28, count 0 2006.285.11:37:41.63#ibcon#enter sib2, iclass 28, count 0 2006.285.11:37:41.63#ibcon#flushed, iclass 28, count 0 2006.285.11:37:41.63#ibcon#about to write, iclass 28, count 0 2006.285.11:37:41.63#ibcon#wrote, iclass 28, count 0 2006.285.11:37:41.63#ibcon#about to read 3, iclass 28, count 0 2006.285.11:37:41.67#ibcon#read 3, iclass 28, count 0 2006.285.11:37:41.67#ibcon#about to read 4, iclass 28, count 0 2006.285.11:37:41.67#ibcon#read 4, iclass 28, count 0 2006.285.11:37:41.67#ibcon#about to read 5, iclass 28, count 0 2006.285.11:37:41.67#ibcon#read 5, iclass 28, count 0 2006.285.11:37:41.67#ibcon#about to read 6, iclass 28, count 0 2006.285.11:37:41.67#ibcon#read 6, iclass 28, count 0 2006.285.11:37:41.67#ibcon#end of sib2, iclass 28, count 0 2006.285.11:37:41.67#ibcon#*after write, iclass 28, count 0 2006.285.11:37:41.67#ibcon#*before return 0, iclass 28, count 0 2006.285.11:37:41.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:37:41.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:37:41.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.11:37:41.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.11:37:41.67$vck44/vb=1,4 2006.285.11:37:41.67#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.11:37:41.67#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.11:37:41.67#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:41.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:37:41.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:37:41.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:37:41.67#ibcon#enter wrdev, iclass 30, count 2 2006.285.11:37:41.67#ibcon#first serial, iclass 30, count 2 2006.285.11:37:41.67#ibcon#enter sib2, iclass 30, count 2 2006.285.11:37:41.67#ibcon#flushed, iclass 30, count 2 2006.285.11:37:41.67#ibcon#about to write, iclass 30, count 2 2006.285.11:37:41.67#ibcon#wrote, iclass 30, count 2 2006.285.11:37:41.67#ibcon#about to read 3, iclass 30, count 2 2006.285.11:37:41.69#ibcon#read 3, iclass 30, count 2 2006.285.11:37:41.69#ibcon#about to read 4, iclass 30, count 2 2006.285.11:37:41.69#ibcon#read 4, iclass 30, count 2 2006.285.11:37:41.69#ibcon#about to read 5, iclass 30, count 2 2006.285.11:37:41.69#ibcon#read 5, iclass 30, count 2 2006.285.11:37:41.69#ibcon#about to read 6, iclass 30, count 2 2006.285.11:37:41.69#ibcon#read 6, iclass 30, count 2 2006.285.11:37:41.69#ibcon#end of sib2, iclass 30, count 2 2006.285.11:37:41.69#ibcon#*mode == 0, iclass 30, count 2 2006.285.11:37:41.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.11:37:41.69#ibcon#[27=AT01-04\r\n] 2006.285.11:37:41.69#ibcon#*before write, iclass 30, count 2 2006.285.11:37:41.69#ibcon#enter sib2, iclass 30, count 2 2006.285.11:37:41.69#ibcon#flushed, iclass 30, count 2 2006.285.11:37:41.69#ibcon#about to write, iclass 30, count 2 2006.285.11:37:41.69#ibcon#wrote, iclass 30, count 2 2006.285.11:37:41.69#ibcon#about to read 3, iclass 30, count 2 2006.285.11:37:41.72#ibcon#read 3, iclass 30, count 2 2006.285.11:37:41.72#ibcon#about to read 4, iclass 30, count 2 2006.285.11:37:41.72#ibcon#read 4, iclass 30, count 2 2006.285.11:37:41.72#ibcon#about to read 5, iclass 30, count 2 2006.285.11:37:41.72#ibcon#read 5, iclass 30, count 2 2006.285.11:37:41.72#ibcon#about to read 6, iclass 30, count 2 2006.285.11:37:41.72#ibcon#read 6, iclass 30, count 2 2006.285.11:37:41.72#ibcon#end of sib2, iclass 30, count 2 2006.285.11:37:41.72#ibcon#*after write, iclass 30, count 2 2006.285.11:37:41.72#ibcon#*before return 0, iclass 30, count 2 2006.285.11:37:41.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:37:41.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:37:41.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.11:37:41.72#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:41.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:37:41.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:37:41.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:37:41.84#ibcon#enter wrdev, iclass 30, count 0 2006.285.11:37:41.84#ibcon#first serial, iclass 30, count 0 2006.285.11:37:41.84#ibcon#enter sib2, iclass 30, count 0 2006.285.11:37:41.84#ibcon#flushed, iclass 30, count 0 2006.285.11:37:41.84#ibcon#about to write, iclass 30, count 0 2006.285.11:37:41.84#ibcon#wrote, iclass 30, count 0 2006.285.11:37:41.84#ibcon#about to read 3, iclass 30, count 0 2006.285.11:37:41.86#ibcon#read 3, iclass 30, count 0 2006.285.11:37:41.86#ibcon#about to read 4, iclass 30, count 0 2006.285.11:37:41.86#ibcon#read 4, iclass 30, count 0 2006.285.11:37:41.86#ibcon#about to read 5, iclass 30, count 0 2006.285.11:37:41.86#ibcon#read 5, iclass 30, count 0 2006.285.11:37:41.86#ibcon#about to read 6, iclass 30, count 0 2006.285.11:37:41.86#ibcon#read 6, iclass 30, count 0 2006.285.11:37:41.86#ibcon#end of sib2, iclass 30, count 0 2006.285.11:37:41.86#ibcon#*mode == 0, iclass 30, count 0 2006.285.11:37:41.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.11:37:41.86#ibcon#[27=USB\r\n] 2006.285.11:37:41.86#ibcon#*before write, iclass 30, count 0 2006.285.11:37:41.86#ibcon#enter sib2, iclass 30, count 0 2006.285.11:37:41.86#ibcon#flushed, iclass 30, count 0 2006.285.11:37:41.86#ibcon#about to write, iclass 30, count 0 2006.285.11:37:41.86#ibcon#wrote, iclass 30, count 0 2006.285.11:37:41.86#ibcon#about to read 3, iclass 30, count 0 2006.285.11:37:41.89#ibcon#read 3, iclass 30, count 0 2006.285.11:37:41.89#ibcon#about to read 4, iclass 30, count 0 2006.285.11:37:41.89#ibcon#read 4, iclass 30, count 0 2006.285.11:37:41.89#ibcon#about to read 5, iclass 30, count 0 2006.285.11:37:41.89#ibcon#read 5, iclass 30, count 0 2006.285.11:37:41.89#ibcon#about to read 6, iclass 30, count 0 2006.285.11:37:41.89#ibcon#read 6, iclass 30, count 0 2006.285.11:37:41.89#ibcon#end of sib2, iclass 30, count 0 2006.285.11:37:41.89#ibcon#*after write, iclass 30, count 0 2006.285.11:37:41.89#ibcon#*before return 0, iclass 30, count 0 2006.285.11:37:41.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:37:41.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:37:41.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.11:37:41.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.11:37:41.89$vck44/vblo=2,634.99 2006.285.11:37:41.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.11:37:41.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.11:37:41.89#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:41.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:37:41.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:37:41.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:37:41.89#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:37:41.89#ibcon#first serial, iclass 32, count 0 2006.285.11:37:41.89#ibcon#enter sib2, iclass 32, count 0 2006.285.11:37:41.89#ibcon#flushed, iclass 32, count 0 2006.285.11:37:41.89#ibcon#about to write, iclass 32, count 0 2006.285.11:37:41.89#ibcon#wrote, iclass 32, count 0 2006.285.11:37:41.89#ibcon#about to read 3, iclass 32, count 0 2006.285.11:37:41.91#ibcon#read 3, iclass 32, count 0 2006.285.11:37:41.91#ibcon#about to read 4, iclass 32, count 0 2006.285.11:37:41.91#ibcon#read 4, iclass 32, count 0 2006.285.11:37:41.91#ibcon#about to read 5, iclass 32, count 0 2006.285.11:37:41.91#ibcon#read 5, iclass 32, count 0 2006.285.11:37:41.91#ibcon#about to read 6, iclass 32, count 0 2006.285.11:37:41.91#ibcon#read 6, iclass 32, count 0 2006.285.11:37:41.91#ibcon#end of sib2, iclass 32, count 0 2006.285.11:37:41.91#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:37:41.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:37:41.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:37:41.91#ibcon#*before write, iclass 32, count 0 2006.285.11:37:41.91#ibcon#enter sib2, iclass 32, count 0 2006.285.11:37:41.91#ibcon#flushed, iclass 32, count 0 2006.285.11:37:41.91#ibcon#about to write, iclass 32, count 0 2006.285.11:37:41.91#ibcon#wrote, iclass 32, count 0 2006.285.11:37:41.91#ibcon#about to read 3, iclass 32, count 0 2006.285.11:37:41.95#ibcon#read 3, iclass 32, count 0 2006.285.11:37:41.95#ibcon#about to read 4, iclass 32, count 0 2006.285.11:37:41.95#ibcon#read 4, iclass 32, count 0 2006.285.11:37:41.95#ibcon#about to read 5, iclass 32, count 0 2006.285.11:37:41.95#ibcon#read 5, iclass 32, count 0 2006.285.11:37:41.95#ibcon#about to read 6, iclass 32, count 0 2006.285.11:37:41.95#ibcon#read 6, iclass 32, count 0 2006.285.11:37:41.95#ibcon#end of sib2, iclass 32, count 0 2006.285.11:37:41.95#ibcon#*after write, iclass 32, count 0 2006.285.11:37:41.95#ibcon#*before return 0, iclass 32, count 0 2006.285.11:37:41.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:37:41.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:37:41.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:37:41.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:37:41.95$vck44/vb=2,5 2006.285.11:37:41.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.11:37:41.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.11:37:41.95#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:41.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:37:42.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:37:42.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:37:42.01#ibcon#enter wrdev, iclass 34, count 2 2006.285.11:37:42.01#ibcon#first serial, iclass 34, count 2 2006.285.11:37:42.01#ibcon#enter sib2, iclass 34, count 2 2006.285.11:37:42.01#ibcon#flushed, iclass 34, count 2 2006.285.11:37:42.01#ibcon#about to write, iclass 34, count 2 2006.285.11:37:42.01#ibcon#wrote, iclass 34, count 2 2006.285.11:37:42.01#ibcon#about to read 3, iclass 34, count 2 2006.285.11:37:42.03#ibcon#read 3, iclass 34, count 2 2006.285.11:37:42.03#ibcon#about to read 4, iclass 34, count 2 2006.285.11:37:42.03#ibcon#read 4, iclass 34, count 2 2006.285.11:37:42.03#ibcon#about to read 5, iclass 34, count 2 2006.285.11:37:42.03#ibcon#read 5, iclass 34, count 2 2006.285.11:37:42.03#ibcon#about to read 6, iclass 34, count 2 2006.285.11:37:42.03#ibcon#read 6, iclass 34, count 2 2006.285.11:37:42.03#ibcon#end of sib2, iclass 34, count 2 2006.285.11:37:42.03#ibcon#*mode == 0, iclass 34, count 2 2006.285.11:37:42.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.11:37:42.03#ibcon#[27=AT02-05\r\n] 2006.285.11:37:42.03#ibcon#*before write, iclass 34, count 2 2006.285.11:37:42.03#ibcon#enter sib2, iclass 34, count 2 2006.285.11:37:42.03#ibcon#flushed, iclass 34, count 2 2006.285.11:37:42.03#ibcon#about to write, iclass 34, count 2 2006.285.11:37:42.03#ibcon#wrote, iclass 34, count 2 2006.285.11:37:42.03#ibcon#about to read 3, iclass 34, count 2 2006.285.11:37:42.06#ibcon#read 3, iclass 34, count 2 2006.285.11:37:42.06#ibcon#about to read 4, iclass 34, count 2 2006.285.11:37:42.06#ibcon#read 4, iclass 34, count 2 2006.285.11:37:42.06#ibcon#about to read 5, iclass 34, count 2 2006.285.11:37:42.06#ibcon#read 5, iclass 34, count 2 2006.285.11:37:42.06#ibcon#about to read 6, iclass 34, count 2 2006.285.11:37:42.06#ibcon#read 6, iclass 34, count 2 2006.285.11:37:42.06#ibcon#end of sib2, iclass 34, count 2 2006.285.11:37:42.06#ibcon#*after write, iclass 34, count 2 2006.285.11:37:42.06#ibcon#*before return 0, iclass 34, count 2 2006.285.11:37:42.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:37:42.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:37:42.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.11:37:42.06#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:42.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:37:42.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:37:42.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:37:42.18#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:37:42.18#ibcon#first serial, iclass 34, count 0 2006.285.11:37:42.18#ibcon#enter sib2, iclass 34, count 0 2006.285.11:37:42.18#ibcon#flushed, iclass 34, count 0 2006.285.11:37:42.18#ibcon#about to write, iclass 34, count 0 2006.285.11:37:42.18#ibcon#wrote, iclass 34, count 0 2006.285.11:37:42.18#ibcon#about to read 3, iclass 34, count 0 2006.285.11:37:42.20#ibcon#read 3, iclass 34, count 0 2006.285.11:37:42.20#ibcon#about to read 4, iclass 34, count 0 2006.285.11:37:42.20#ibcon#read 4, iclass 34, count 0 2006.285.11:37:42.20#ibcon#about to read 5, iclass 34, count 0 2006.285.11:37:42.20#ibcon#read 5, iclass 34, count 0 2006.285.11:37:42.20#ibcon#about to read 6, iclass 34, count 0 2006.285.11:37:42.20#ibcon#read 6, iclass 34, count 0 2006.285.11:37:42.20#ibcon#end of sib2, iclass 34, count 0 2006.285.11:37:42.20#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:37:42.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:37:42.20#ibcon#[27=USB\r\n] 2006.285.11:37:42.20#ibcon#*before write, iclass 34, count 0 2006.285.11:37:42.20#ibcon#enter sib2, iclass 34, count 0 2006.285.11:37:42.20#ibcon#flushed, iclass 34, count 0 2006.285.11:37:42.20#ibcon#about to write, iclass 34, count 0 2006.285.11:37:42.20#ibcon#wrote, iclass 34, count 0 2006.285.11:37:42.20#ibcon#about to read 3, iclass 34, count 0 2006.285.11:37:42.23#ibcon#read 3, iclass 34, count 0 2006.285.11:37:42.23#ibcon#about to read 4, iclass 34, count 0 2006.285.11:37:42.23#ibcon#read 4, iclass 34, count 0 2006.285.11:37:42.23#ibcon#about to read 5, iclass 34, count 0 2006.285.11:37:42.23#ibcon#read 5, iclass 34, count 0 2006.285.11:37:42.23#ibcon#about to read 6, iclass 34, count 0 2006.285.11:37:42.23#ibcon#read 6, iclass 34, count 0 2006.285.11:37:42.23#ibcon#end of sib2, iclass 34, count 0 2006.285.11:37:42.23#ibcon#*after write, iclass 34, count 0 2006.285.11:37:42.23#ibcon#*before return 0, iclass 34, count 0 2006.285.11:37:42.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:37:42.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:37:42.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:37:42.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:37:42.23$vck44/vblo=3,649.99 2006.285.11:37:42.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.11:37:42.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.11:37:42.23#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:42.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:37:42.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:37:42.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:37:42.23#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:37:42.23#ibcon#first serial, iclass 36, count 0 2006.285.11:37:42.23#ibcon#enter sib2, iclass 36, count 0 2006.285.11:37:42.23#ibcon#flushed, iclass 36, count 0 2006.285.11:37:42.23#ibcon#about to write, iclass 36, count 0 2006.285.11:37:42.23#ibcon#wrote, iclass 36, count 0 2006.285.11:37:42.23#ibcon#about to read 3, iclass 36, count 0 2006.285.11:37:42.25#ibcon#read 3, iclass 36, count 0 2006.285.11:37:42.25#ibcon#about to read 4, iclass 36, count 0 2006.285.11:37:42.25#ibcon#read 4, iclass 36, count 0 2006.285.11:37:42.25#ibcon#about to read 5, iclass 36, count 0 2006.285.11:37:42.25#ibcon#read 5, iclass 36, count 0 2006.285.11:37:42.25#ibcon#about to read 6, iclass 36, count 0 2006.285.11:37:42.25#ibcon#read 6, iclass 36, count 0 2006.285.11:37:42.25#ibcon#end of sib2, iclass 36, count 0 2006.285.11:37:42.25#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:37:42.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:37:42.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:37:42.25#ibcon#*before write, iclass 36, count 0 2006.285.11:37:42.25#ibcon#enter sib2, iclass 36, count 0 2006.285.11:37:42.25#ibcon#flushed, iclass 36, count 0 2006.285.11:37:42.25#ibcon#about to write, iclass 36, count 0 2006.285.11:37:42.25#ibcon#wrote, iclass 36, count 0 2006.285.11:37:42.25#ibcon#about to read 3, iclass 36, count 0 2006.285.11:37:42.29#ibcon#read 3, iclass 36, count 0 2006.285.11:37:42.29#ibcon#about to read 4, iclass 36, count 0 2006.285.11:37:42.29#ibcon#read 4, iclass 36, count 0 2006.285.11:37:42.29#ibcon#about to read 5, iclass 36, count 0 2006.285.11:37:42.29#ibcon#read 5, iclass 36, count 0 2006.285.11:37:42.29#ibcon#about to read 6, iclass 36, count 0 2006.285.11:37:42.29#ibcon#read 6, iclass 36, count 0 2006.285.11:37:42.29#ibcon#end of sib2, iclass 36, count 0 2006.285.11:37:42.29#ibcon#*after write, iclass 36, count 0 2006.285.11:37:42.29#ibcon#*before return 0, iclass 36, count 0 2006.285.11:37:42.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:37:42.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:37:42.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:37:42.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:37:42.29$vck44/vb=3,4 2006.285.11:37:42.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.11:37:42.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.11:37:42.29#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:42.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:37:42.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:37:42.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:37:42.35#ibcon#enter wrdev, iclass 38, count 2 2006.285.11:37:42.35#ibcon#first serial, iclass 38, count 2 2006.285.11:37:42.35#ibcon#enter sib2, iclass 38, count 2 2006.285.11:37:42.35#ibcon#flushed, iclass 38, count 2 2006.285.11:37:42.35#ibcon#about to write, iclass 38, count 2 2006.285.11:37:42.35#ibcon#wrote, iclass 38, count 2 2006.285.11:37:42.35#ibcon#about to read 3, iclass 38, count 2 2006.285.11:37:42.37#ibcon#read 3, iclass 38, count 2 2006.285.11:37:42.37#ibcon#about to read 4, iclass 38, count 2 2006.285.11:37:42.37#ibcon#read 4, iclass 38, count 2 2006.285.11:37:42.37#ibcon#about to read 5, iclass 38, count 2 2006.285.11:37:42.37#ibcon#read 5, iclass 38, count 2 2006.285.11:37:42.37#ibcon#about to read 6, iclass 38, count 2 2006.285.11:37:42.37#ibcon#read 6, iclass 38, count 2 2006.285.11:37:42.37#ibcon#end of sib2, iclass 38, count 2 2006.285.11:37:42.37#ibcon#*mode == 0, iclass 38, count 2 2006.285.11:37:42.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.11:37:42.37#ibcon#[27=AT03-04\r\n] 2006.285.11:37:42.37#ibcon#*before write, iclass 38, count 2 2006.285.11:37:42.37#ibcon#enter sib2, iclass 38, count 2 2006.285.11:37:42.37#ibcon#flushed, iclass 38, count 2 2006.285.11:37:42.37#ibcon#about to write, iclass 38, count 2 2006.285.11:37:42.37#ibcon#wrote, iclass 38, count 2 2006.285.11:37:42.37#ibcon#about to read 3, iclass 38, count 2 2006.285.11:37:42.40#ibcon#read 3, iclass 38, count 2 2006.285.11:37:42.40#ibcon#about to read 4, iclass 38, count 2 2006.285.11:37:42.40#ibcon#read 4, iclass 38, count 2 2006.285.11:37:42.40#ibcon#about to read 5, iclass 38, count 2 2006.285.11:37:42.40#ibcon#read 5, iclass 38, count 2 2006.285.11:37:42.40#ibcon#about to read 6, iclass 38, count 2 2006.285.11:37:42.40#ibcon#read 6, iclass 38, count 2 2006.285.11:37:42.40#ibcon#end of sib2, iclass 38, count 2 2006.285.11:37:42.40#ibcon#*after write, iclass 38, count 2 2006.285.11:37:42.40#ibcon#*before return 0, iclass 38, count 2 2006.285.11:37:42.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:37:42.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:37:42.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.11:37:42.40#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:42.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:37:42.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:37:42.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:37:42.52#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:37:42.52#ibcon#first serial, iclass 38, count 0 2006.285.11:37:42.52#ibcon#enter sib2, iclass 38, count 0 2006.285.11:37:42.52#ibcon#flushed, iclass 38, count 0 2006.285.11:37:42.52#ibcon#about to write, iclass 38, count 0 2006.285.11:37:42.52#ibcon#wrote, iclass 38, count 0 2006.285.11:37:42.52#ibcon#about to read 3, iclass 38, count 0 2006.285.11:37:42.54#ibcon#read 3, iclass 38, count 0 2006.285.11:37:42.54#ibcon#about to read 4, iclass 38, count 0 2006.285.11:37:42.54#ibcon#read 4, iclass 38, count 0 2006.285.11:37:42.54#ibcon#about to read 5, iclass 38, count 0 2006.285.11:37:42.54#ibcon#read 5, iclass 38, count 0 2006.285.11:37:42.54#ibcon#about to read 6, iclass 38, count 0 2006.285.11:37:42.54#ibcon#read 6, iclass 38, count 0 2006.285.11:37:42.54#ibcon#end of sib2, iclass 38, count 0 2006.285.11:37:42.54#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:37:42.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:37:42.54#ibcon#[27=USB\r\n] 2006.285.11:37:42.54#ibcon#*before write, iclass 38, count 0 2006.285.11:37:42.54#ibcon#enter sib2, iclass 38, count 0 2006.285.11:37:42.54#ibcon#flushed, iclass 38, count 0 2006.285.11:37:42.54#ibcon#about to write, iclass 38, count 0 2006.285.11:37:42.54#ibcon#wrote, iclass 38, count 0 2006.285.11:37:42.54#ibcon#about to read 3, iclass 38, count 0 2006.285.11:37:42.57#ibcon#read 3, iclass 38, count 0 2006.285.11:37:42.57#ibcon#about to read 4, iclass 38, count 0 2006.285.11:37:42.57#ibcon#read 4, iclass 38, count 0 2006.285.11:37:42.57#ibcon#about to read 5, iclass 38, count 0 2006.285.11:37:42.57#ibcon#read 5, iclass 38, count 0 2006.285.11:37:42.57#ibcon#about to read 6, iclass 38, count 0 2006.285.11:37:42.57#ibcon#read 6, iclass 38, count 0 2006.285.11:37:42.57#ibcon#end of sib2, iclass 38, count 0 2006.285.11:37:42.57#ibcon#*after write, iclass 38, count 0 2006.285.11:37:42.57#ibcon#*before return 0, iclass 38, count 0 2006.285.11:37:42.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:37:42.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:37:42.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:37:42.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:37:42.57$vck44/vblo=4,679.99 2006.285.11:37:42.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.11:37:42.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.11:37:42.57#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:42.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:37:42.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:37:42.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:37:42.57#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:37:42.57#ibcon#first serial, iclass 40, count 0 2006.285.11:37:42.57#ibcon#enter sib2, iclass 40, count 0 2006.285.11:37:42.57#ibcon#flushed, iclass 40, count 0 2006.285.11:37:42.57#ibcon#about to write, iclass 40, count 0 2006.285.11:37:42.57#ibcon#wrote, iclass 40, count 0 2006.285.11:37:42.57#ibcon#about to read 3, iclass 40, count 0 2006.285.11:37:42.59#ibcon#read 3, iclass 40, count 0 2006.285.11:37:42.59#ibcon#about to read 4, iclass 40, count 0 2006.285.11:37:42.59#ibcon#read 4, iclass 40, count 0 2006.285.11:37:42.59#ibcon#about to read 5, iclass 40, count 0 2006.285.11:37:42.59#ibcon#read 5, iclass 40, count 0 2006.285.11:37:42.59#ibcon#about to read 6, iclass 40, count 0 2006.285.11:37:42.59#ibcon#read 6, iclass 40, count 0 2006.285.11:37:42.59#ibcon#end of sib2, iclass 40, count 0 2006.285.11:37:42.59#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:37:42.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:37:42.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:37:42.59#ibcon#*before write, iclass 40, count 0 2006.285.11:37:42.59#ibcon#enter sib2, iclass 40, count 0 2006.285.11:37:42.59#ibcon#flushed, iclass 40, count 0 2006.285.11:37:42.59#ibcon#about to write, iclass 40, count 0 2006.285.11:37:42.59#ibcon#wrote, iclass 40, count 0 2006.285.11:37:42.59#ibcon#about to read 3, iclass 40, count 0 2006.285.11:37:42.63#ibcon#read 3, iclass 40, count 0 2006.285.11:37:42.63#ibcon#about to read 4, iclass 40, count 0 2006.285.11:37:42.63#ibcon#read 4, iclass 40, count 0 2006.285.11:37:42.63#ibcon#about to read 5, iclass 40, count 0 2006.285.11:37:42.63#ibcon#read 5, iclass 40, count 0 2006.285.11:37:42.63#ibcon#about to read 6, iclass 40, count 0 2006.285.11:37:42.63#ibcon#read 6, iclass 40, count 0 2006.285.11:37:42.63#ibcon#end of sib2, iclass 40, count 0 2006.285.11:37:42.63#ibcon#*after write, iclass 40, count 0 2006.285.11:37:42.63#ibcon#*before return 0, iclass 40, count 0 2006.285.11:37:42.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:37:42.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:37:42.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:37:42.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:37:42.63$vck44/vb=4,5 2006.285.11:37:42.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.11:37:42.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.11:37:42.63#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:42.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:37:42.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:37:42.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:37:42.69#ibcon#enter wrdev, iclass 4, count 2 2006.285.11:37:42.69#ibcon#first serial, iclass 4, count 2 2006.285.11:37:42.69#ibcon#enter sib2, iclass 4, count 2 2006.285.11:37:42.69#ibcon#flushed, iclass 4, count 2 2006.285.11:37:42.69#ibcon#about to write, iclass 4, count 2 2006.285.11:37:42.69#ibcon#wrote, iclass 4, count 2 2006.285.11:37:42.69#ibcon#about to read 3, iclass 4, count 2 2006.285.11:37:42.71#ibcon#read 3, iclass 4, count 2 2006.285.11:37:42.71#ibcon#about to read 4, iclass 4, count 2 2006.285.11:37:42.71#ibcon#read 4, iclass 4, count 2 2006.285.11:37:42.71#ibcon#about to read 5, iclass 4, count 2 2006.285.11:37:42.71#ibcon#read 5, iclass 4, count 2 2006.285.11:37:42.71#ibcon#about to read 6, iclass 4, count 2 2006.285.11:37:42.71#ibcon#read 6, iclass 4, count 2 2006.285.11:37:42.71#ibcon#end of sib2, iclass 4, count 2 2006.285.11:37:42.71#ibcon#*mode == 0, iclass 4, count 2 2006.285.11:37:42.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.11:37:42.71#ibcon#[27=AT04-05\r\n] 2006.285.11:37:42.71#ibcon#*before write, iclass 4, count 2 2006.285.11:37:42.71#ibcon#enter sib2, iclass 4, count 2 2006.285.11:37:42.71#ibcon#flushed, iclass 4, count 2 2006.285.11:37:42.71#ibcon#about to write, iclass 4, count 2 2006.285.11:37:42.71#ibcon#wrote, iclass 4, count 2 2006.285.11:37:42.71#ibcon#about to read 3, iclass 4, count 2 2006.285.11:37:42.74#ibcon#read 3, iclass 4, count 2 2006.285.11:37:42.74#ibcon#about to read 4, iclass 4, count 2 2006.285.11:37:42.74#ibcon#read 4, iclass 4, count 2 2006.285.11:37:42.74#ibcon#about to read 5, iclass 4, count 2 2006.285.11:37:42.74#ibcon#read 5, iclass 4, count 2 2006.285.11:37:42.74#ibcon#about to read 6, iclass 4, count 2 2006.285.11:37:42.74#ibcon#read 6, iclass 4, count 2 2006.285.11:37:42.74#ibcon#end of sib2, iclass 4, count 2 2006.285.11:37:42.74#ibcon#*after write, iclass 4, count 2 2006.285.11:37:42.74#ibcon#*before return 0, iclass 4, count 2 2006.285.11:37:42.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:37:42.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:37:42.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.11:37:42.74#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:42.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:37:42.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:37:42.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:37:42.86#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:37:42.86#ibcon#first serial, iclass 4, count 0 2006.285.11:37:42.86#ibcon#enter sib2, iclass 4, count 0 2006.285.11:37:42.86#ibcon#flushed, iclass 4, count 0 2006.285.11:37:42.86#ibcon#about to write, iclass 4, count 0 2006.285.11:37:42.86#ibcon#wrote, iclass 4, count 0 2006.285.11:37:42.86#ibcon#about to read 3, iclass 4, count 0 2006.285.11:37:42.88#ibcon#read 3, iclass 4, count 0 2006.285.11:37:42.88#ibcon#about to read 4, iclass 4, count 0 2006.285.11:37:42.88#ibcon#read 4, iclass 4, count 0 2006.285.11:37:42.88#ibcon#about to read 5, iclass 4, count 0 2006.285.11:37:42.88#ibcon#read 5, iclass 4, count 0 2006.285.11:37:42.88#ibcon#about to read 6, iclass 4, count 0 2006.285.11:37:42.88#ibcon#read 6, iclass 4, count 0 2006.285.11:37:42.88#ibcon#end of sib2, iclass 4, count 0 2006.285.11:37:42.88#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:37:42.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:37:42.88#ibcon#[27=USB\r\n] 2006.285.11:37:42.88#ibcon#*before write, iclass 4, count 0 2006.285.11:37:42.88#ibcon#enter sib2, iclass 4, count 0 2006.285.11:37:42.88#ibcon#flushed, iclass 4, count 0 2006.285.11:37:42.88#ibcon#about to write, iclass 4, count 0 2006.285.11:37:42.88#ibcon#wrote, iclass 4, count 0 2006.285.11:37:42.88#ibcon#about to read 3, iclass 4, count 0 2006.285.11:37:42.91#ibcon#read 3, iclass 4, count 0 2006.285.11:37:42.91#ibcon#about to read 4, iclass 4, count 0 2006.285.11:37:42.91#ibcon#read 4, iclass 4, count 0 2006.285.11:37:42.91#ibcon#about to read 5, iclass 4, count 0 2006.285.11:37:42.91#ibcon#read 5, iclass 4, count 0 2006.285.11:37:42.91#ibcon#about to read 6, iclass 4, count 0 2006.285.11:37:42.91#ibcon#read 6, iclass 4, count 0 2006.285.11:37:42.91#ibcon#end of sib2, iclass 4, count 0 2006.285.11:37:42.91#ibcon#*after write, iclass 4, count 0 2006.285.11:37:42.91#ibcon#*before return 0, iclass 4, count 0 2006.285.11:37:42.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:37:42.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:37:42.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:37:42.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:37:42.91$vck44/vblo=5,709.99 2006.285.11:37:42.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.11:37:42.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.11:37:42.91#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:42.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:37:42.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:37:42.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:37:42.91#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:37:42.91#ibcon#first serial, iclass 6, count 0 2006.285.11:37:42.91#ibcon#enter sib2, iclass 6, count 0 2006.285.11:37:42.91#ibcon#flushed, iclass 6, count 0 2006.285.11:37:42.91#ibcon#about to write, iclass 6, count 0 2006.285.11:37:42.91#ibcon#wrote, iclass 6, count 0 2006.285.11:37:42.91#ibcon#about to read 3, iclass 6, count 0 2006.285.11:37:42.93#ibcon#read 3, iclass 6, count 0 2006.285.11:37:42.93#ibcon#about to read 4, iclass 6, count 0 2006.285.11:37:42.93#ibcon#read 4, iclass 6, count 0 2006.285.11:37:42.93#ibcon#about to read 5, iclass 6, count 0 2006.285.11:37:42.93#ibcon#read 5, iclass 6, count 0 2006.285.11:37:42.93#ibcon#about to read 6, iclass 6, count 0 2006.285.11:37:42.93#ibcon#read 6, iclass 6, count 0 2006.285.11:37:42.93#ibcon#end of sib2, iclass 6, count 0 2006.285.11:37:42.93#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:37:42.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:37:42.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:37:42.93#ibcon#*before write, iclass 6, count 0 2006.285.11:37:42.93#ibcon#enter sib2, iclass 6, count 0 2006.285.11:37:42.93#ibcon#flushed, iclass 6, count 0 2006.285.11:37:42.93#ibcon#about to write, iclass 6, count 0 2006.285.11:37:42.93#ibcon#wrote, iclass 6, count 0 2006.285.11:37:42.93#ibcon#about to read 3, iclass 6, count 0 2006.285.11:37:42.97#ibcon#read 3, iclass 6, count 0 2006.285.11:37:42.97#ibcon#about to read 4, iclass 6, count 0 2006.285.11:37:42.97#ibcon#read 4, iclass 6, count 0 2006.285.11:37:42.97#ibcon#about to read 5, iclass 6, count 0 2006.285.11:37:42.97#ibcon#read 5, iclass 6, count 0 2006.285.11:37:42.97#ibcon#about to read 6, iclass 6, count 0 2006.285.11:37:42.97#ibcon#read 6, iclass 6, count 0 2006.285.11:37:42.97#ibcon#end of sib2, iclass 6, count 0 2006.285.11:37:42.97#ibcon#*after write, iclass 6, count 0 2006.285.11:37:42.97#ibcon#*before return 0, iclass 6, count 0 2006.285.11:37:42.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:37:42.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:37:42.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:37:42.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:37:42.97$vck44/vb=5,4 2006.285.11:37:42.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.11:37:42.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.11:37:42.97#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:42.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:37:43.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:37:43.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:37:43.03#ibcon#enter wrdev, iclass 10, count 2 2006.285.11:37:43.03#ibcon#first serial, iclass 10, count 2 2006.285.11:37:43.03#ibcon#enter sib2, iclass 10, count 2 2006.285.11:37:43.03#ibcon#flushed, iclass 10, count 2 2006.285.11:37:43.03#ibcon#about to write, iclass 10, count 2 2006.285.11:37:43.03#ibcon#wrote, iclass 10, count 2 2006.285.11:37:43.03#ibcon#about to read 3, iclass 10, count 2 2006.285.11:37:43.05#ibcon#read 3, iclass 10, count 2 2006.285.11:37:43.05#ibcon#about to read 4, iclass 10, count 2 2006.285.11:37:43.05#ibcon#read 4, iclass 10, count 2 2006.285.11:37:43.05#ibcon#about to read 5, iclass 10, count 2 2006.285.11:37:43.05#ibcon#read 5, iclass 10, count 2 2006.285.11:37:43.05#ibcon#about to read 6, iclass 10, count 2 2006.285.11:37:43.05#ibcon#read 6, iclass 10, count 2 2006.285.11:37:43.05#ibcon#end of sib2, iclass 10, count 2 2006.285.11:37:43.05#ibcon#*mode == 0, iclass 10, count 2 2006.285.11:37:43.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.11:37:43.05#ibcon#[27=AT05-04\r\n] 2006.285.11:37:43.05#ibcon#*before write, iclass 10, count 2 2006.285.11:37:43.05#ibcon#enter sib2, iclass 10, count 2 2006.285.11:37:43.05#ibcon#flushed, iclass 10, count 2 2006.285.11:37:43.05#ibcon#about to write, iclass 10, count 2 2006.285.11:37:43.05#ibcon#wrote, iclass 10, count 2 2006.285.11:37:43.05#ibcon#about to read 3, iclass 10, count 2 2006.285.11:37:43.08#ibcon#read 3, iclass 10, count 2 2006.285.11:37:43.08#ibcon#about to read 4, iclass 10, count 2 2006.285.11:37:43.08#ibcon#read 4, iclass 10, count 2 2006.285.11:37:43.08#ibcon#about to read 5, iclass 10, count 2 2006.285.11:37:43.08#ibcon#read 5, iclass 10, count 2 2006.285.11:37:43.08#ibcon#about to read 6, iclass 10, count 2 2006.285.11:37:43.08#ibcon#read 6, iclass 10, count 2 2006.285.11:37:43.08#ibcon#end of sib2, iclass 10, count 2 2006.285.11:37:43.08#ibcon#*after write, iclass 10, count 2 2006.285.11:37:43.08#ibcon#*before return 0, iclass 10, count 2 2006.285.11:37:43.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:37:43.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:37:43.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.11:37:43.08#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:43.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:37:43.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:37:43.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:37:43.20#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:37:43.20#ibcon#first serial, iclass 10, count 0 2006.285.11:37:43.20#ibcon#enter sib2, iclass 10, count 0 2006.285.11:37:43.20#ibcon#flushed, iclass 10, count 0 2006.285.11:37:43.20#ibcon#about to write, iclass 10, count 0 2006.285.11:37:43.20#ibcon#wrote, iclass 10, count 0 2006.285.11:37:43.20#ibcon#about to read 3, iclass 10, count 0 2006.285.11:37:43.22#ibcon#read 3, iclass 10, count 0 2006.285.11:37:43.22#ibcon#about to read 4, iclass 10, count 0 2006.285.11:37:43.22#ibcon#read 4, iclass 10, count 0 2006.285.11:37:43.22#ibcon#about to read 5, iclass 10, count 0 2006.285.11:37:43.22#ibcon#read 5, iclass 10, count 0 2006.285.11:37:43.22#ibcon#about to read 6, iclass 10, count 0 2006.285.11:37:43.22#ibcon#read 6, iclass 10, count 0 2006.285.11:37:43.22#ibcon#end of sib2, iclass 10, count 0 2006.285.11:37:43.22#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:37:43.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:37:43.22#ibcon#[27=USB\r\n] 2006.285.11:37:43.22#ibcon#*before write, iclass 10, count 0 2006.285.11:37:43.22#ibcon#enter sib2, iclass 10, count 0 2006.285.11:37:43.22#ibcon#flushed, iclass 10, count 0 2006.285.11:37:43.22#ibcon#about to write, iclass 10, count 0 2006.285.11:37:43.22#ibcon#wrote, iclass 10, count 0 2006.285.11:37:43.22#ibcon#about to read 3, iclass 10, count 0 2006.285.11:37:43.25#ibcon#read 3, iclass 10, count 0 2006.285.11:37:43.25#ibcon#about to read 4, iclass 10, count 0 2006.285.11:37:43.25#ibcon#read 4, iclass 10, count 0 2006.285.11:37:43.25#ibcon#about to read 5, iclass 10, count 0 2006.285.11:37:43.25#ibcon#read 5, iclass 10, count 0 2006.285.11:37:43.25#ibcon#about to read 6, iclass 10, count 0 2006.285.11:37:43.25#ibcon#read 6, iclass 10, count 0 2006.285.11:37:43.25#ibcon#end of sib2, iclass 10, count 0 2006.285.11:37:43.25#ibcon#*after write, iclass 10, count 0 2006.285.11:37:43.25#ibcon#*before return 0, iclass 10, count 0 2006.285.11:37:43.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:37:43.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:37:43.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:37:43.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:37:43.25$vck44/vblo=6,719.99 2006.285.11:37:43.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.11:37:43.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.11:37:43.25#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:43.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:37:43.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:37:43.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:37:43.25#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:37:43.25#ibcon#first serial, iclass 12, count 0 2006.285.11:37:43.25#ibcon#enter sib2, iclass 12, count 0 2006.285.11:37:43.25#ibcon#flushed, iclass 12, count 0 2006.285.11:37:43.25#ibcon#about to write, iclass 12, count 0 2006.285.11:37:43.25#ibcon#wrote, iclass 12, count 0 2006.285.11:37:43.25#ibcon#about to read 3, iclass 12, count 0 2006.285.11:37:43.27#ibcon#read 3, iclass 12, count 0 2006.285.11:37:43.27#ibcon#about to read 4, iclass 12, count 0 2006.285.11:37:43.27#ibcon#read 4, iclass 12, count 0 2006.285.11:37:43.27#ibcon#about to read 5, iclass 12, count 0 2006.285.11:37:43.27#ibcon#read 5, iclass 12, count 0 2006.285.11:37:43.27#ibcon#about to read 6, iclass 12, count 0 2006.285.11:37:43.27#ibcon#read 6, iclass 12, count 0 2006.285.11:37:43.27#ibcon#end of sib2, iclass 12, count 0 2006.285.11:37:43.27#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:37:43.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:37:43.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:37:43.27#ibcon#*before write, iclass 12, count 0 2006.285.11:37:43.27#ibcon#enter sib2, iclass 12, count 0 2006.285.11:37:43.27#ibcon#flushed, iclass 12, count 0 2006.285.11:37:43.27#ibcon#about to write, iclass 12, count 0 2006.285.11:37:43.27#ibcon#wrote, iclass 12, count 0 2006.285.11:37:43.27#ibcon#about to read 3, iclass 12, count 0 2006.285.11:37:43.31#ibcon#read 3, iclass 12, count 0 2006.285.11:37:43.31#ibcon#about to read 4, iclass 12, count 0 2006.285.11:37:43.31#ibcon#read 4, iclass 12, count 0 2006.285.11:37:43.31#ibcon#about to read 5, iclass 12, count 0 2006.285.11:37:43.31#ibcon#read 5, iclass 12, count 0 2006.285.11:37:43.31#ibcon#about to read 6, iclass 12, count 0 2006.285.11:37:43.31#ibcon#read 6, iclass 12, count 0 2006.285.11:37:43.31#ibcon#end of sib2, iclass 12, count 0 2006.285.11:37:43.31#ibcon#*after write, iclass 12, count 0 2006.285.11:37:43.31#ibcon#*before return 0, iclass 12, count 0 2006.285.11:37:43.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:37:43.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:37:43.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:37:43.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:37:43.31$vck44/vb=6,3 2006.285.11:37:43.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.11:37:43.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.11:37:43.31#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:43.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:37:43.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:37:43.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:37:43.37#ibcon#enter wrdev, iclass 14, count 2 2006.285.11:37:43.37#ibcon#first serial, iclass 14, count 2 2006.285.11:37:43.37#ibcon#enter sib2, iclass 14, count 2 2006.285.11:37:43.37#ibcon#flushed, iclass 14, count 2 2006.285.11:37:43.37#ibcon#about to write, iclass 14, count 2 2006.285.11:37:43.37#ibcon#wrote, iclass 14, count 2 2006.285.11:37:43.37#ibcon#about to read 3, iclass 14, count 2 2006.285.11:37:43.39#ibcon#read 3, iclass 14, count 2 2006.285.11:37:43.39#ibcon#about to read 4, iclass 14, count 2 2006.285.11:37:43.39#ibcon#read 4, iclass 14, count 2 2006.285.11:37:43.39#ibcon#about to read 5, iclass 14, count 2 2006.285.11:37:43.39#ibcon#read 5, iclass 14, count 2 2006.285.11:37:43.39#ibcon#about to read 6, iclass 14, count 2 2006.285.11:37:43.39#ibcon#read 6, iclass 14, count 2 2006.285.11:37:43.39#ibcon#end of sib2, iclass 14, count 2 2006.285.11:37:43.39#ibcon#*mode == 0, iclass 14, count 2 2006.285.11:37:43.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.11:37:43.39#ibcon#[27=AT06-03\r\n] 2006.285.11:37:43.39#ibcon#*before write, iclass 14, count 2 2006.285.11:37:43.39#ibcon#enter sib2, iclass 14, count 2 2006.285.11:37:43.39#ibcon#flushed, iclass 14, count 2 2006.285.11:37:43.39#ibcon#about to write, iclass 14, count 2 2006.285.11:37:43.39#ibcon#wrote, iclass 14, count 2 2006.285.11:37:43.39#ibcon#about to read 3, iclass 14, count 2 2006.285.11:37:43.42#ibcon#read 3, iclass 14, count 2 2006.285.11:37:43.42#ibcon#about to read 4, iclass 14, count 2 2006.285.11:37:43.42#ibcon#read 4, iclass 14, count 2 2006.285.11:37:43.42#ibcon#about to read 5, iclass 14, count 2 2006.285.11:37:43.42#ibcon#read 5, iclass 14, count 2 2006.285.11:37:43.42#ibcon#about to read 6, iclass 14, count 2 2006.285.11:37:43.42#ibcon#read 6, iclass 14, count 2 2006.285.11:37:43.42#ibcon#end of sib2, iclass 14, count 2 2006.285.11:37:43.42#ibcon#*after write, iclass 14, count 2 2006.285.11:37:43.42#ibcon#*before return 0, iclass 14, count 2 2006.285.11:37:43.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:37:43.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:37:43.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.11:37:43.42#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:43.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:37:43.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:37:43.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:37:43.54#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:37:43.54#ibcon#first serial, iclass 14, count 0 2006.285.11:37:43.54#ibcon#enter sib2, iclass 14, count 0 2006.285.11:37:43.54#ibcon#flushed, iclass 14, count 0 2006.285.11:37:43.54#ibcon#about to write, iclass 14, count 0 2006.285.11:37:43.54#ibcon#wrote, iclass 14, count 0 2006.285.11:37:43.54#ibcon#about to read 3, iclass 14, count 0 2006.285.11:37:43.56#ibcon#read 3, iclass 14, count 0 2006.285.11:37:43.56#ibcon#about to read 4, iclass 14, count 0 2006.285.11:37:43.56#ibcon#read 4, iclass 14, count 0 2006.285.11:37:43.56#ibcon#about to read 5, iclass 14, count 0 2006.285.11:37:43.56#ibcon#read 5, iclass 14, count 0 2006.285.11:37:43.56#ibcon#about to read 6, iclass 14, count 0 2006.285.11:37:43.56#ibcon#read 6, iclass 14, count 0 2006.285.11:37:43.56#ibcon#end of sib2, iclass 14, count 0 2006.285.11:37:43.56#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:37:43.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:37:43.56#ibcon#[27=USB\r\n] 2006.285.11:37:43.56#ibcon#*before write, iclass 14, count 0 2006.285.11:37:43.56#ibcon#enter sib2, iclass 14, count 0 2006.285.11:37:43.56#ibcon#flushed, iclass 14, count 0 2006.285.11:37:43.56#ibcon#about to write, iclass 14, count 0 2006.285.11:37:43.56#ibcon#wrote, iclass 14, count 0 2006.285.11:37:43.56#ibcon#about to read 3, iclass 14, count 0 2006.285.11:37:43.59#ibcon#read 3, iclass 14, count 0 2006.285.11:37:43.59#ibcon#about to read 4, iclass 14, count 0 2006.285.11:37:43.59#ibcon#read 4, iclass 14, count 0 2006.285.11:37:43.59#ibcon#about to read 5, iclass 14, count 0 2006.285.11:37:43.59#ibcon#read 5, iclass 14, count 0 2006.285.11:37:43.59#ibcon#about to read 6, iclass 14, count 0 2006.285.11:37:43.59#ibcon#read 6, iclass 14, count 0 2006.285.11:37:43.59#ibcon#end of sib2, iclass 14, count 0 2006.285.11:37:43.59#ibcon#*after write, iclass 14, count 0 2006.285.11:37:43.59#ibcon#*before return 0, iclass 14, count 0 2006.285.11:37:43.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:37:43.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:37:43.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:37:43.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:37:43.59$vck44/vblo=7,734.99 2006.285.11:37:43.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.11:37:43.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.11:37:43.59#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:43.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:37:43.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:37:43.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:37:43.59#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:37:43.59#ibcon#first serial, iclass 16, count 0 2006.285.11:37:43.59#ibcon#enter sib2, iclass 16, count 0 2006.285.11:37:43.59#ibcon#flushed, iclass 16, count 0 2006.285.11:37:43.59#ibcon#about to write, iclass 16, count 0 2006.285.11:37:43.59#ibcon#wrote, iclass 16, count 0 2006.285.11:37:43.59#ibcon#about to read 3, iclass 16, count 0 2006.285.11:37:43.61#ibcon#read 3, iclass 16, count 0 2006.285.11:37:43.61#ibcon#about to read 4, iclass 16, count 0 2006.285.11:37:43.61#ibcon#read 4, iclass 16, count 0 2006.285.11:37:43.61#ibcon#about to read 5, iclass 16, count 0 2006.285.11:37:43.61#ibcon#read 5, iclass 16, count 0 2006.285.11:37:43.61#ibcon#about to read 6, iclass 16, count 0 2006.285.11:37:43.61#ibcon#read 6, iclass 16, count 0 2006.285.11:37:43.61#ibcon#end of sib2, iclass 16, count 0 2006.285.11:37:43.61#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:37:43.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:37:43.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:37:43.61#ibcon#*before write, iclass 16, count 0 2006.285.11:37:43.61#ibcon#enter sib2, iclass 16, count 0 2006.285.11:37:43.61#ibcon#flushed, iclass 16, count 0 2006.285.11:37:43.61#ibcon#about to write, iclass 16, count 0 2006.285.11:37:43.61#ibcon#wrote, iclass 16, count 0 2006.285.11:37:43.61#ibcon#about to read 3, iclass 16, count 0 2006.285.11:37:43.65#ibcon#read 3, iclass 16, count 0 2006.285.11:37:43.65#ibcon#about to read 4, iclass 16, count 0 2006.285.11:37:43.65#ibcon#read 4, iclass 16, count 0 2006.285.11:37:43.65#ibcon#about to read 5, iclass 16, count 0 2006.285.11:37:43.65#ibcon#read 5, iclass 16, count 0 2006.285.11:37:43.65#ibcon#about to read 6, iclass 16, count 0 2006.285.11:37:43.65#ibcon#read 6, iclass 16, count 0 2006.285.11:37:43.65#ibcon#end of sib2, iclass 16, count 0 2006.285.11:37:43.65#ibcon#*after write, iclass 16, count 0 2006.285.11:37:43.65#ibcon#*before return 0, iclass 16, count 0 2006.285.11:37:43.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:37:43.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:37:43.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:37:43.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:37:43.65$vck44/vb=7,4 2006.285.11:37:43.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.11:37:43.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.11:37:43.65#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:43.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:37:43.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:37:43.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:37:43.71#ibcon#enter wrdev, iclass 18, count 2 2006.285.11:37:43.71#ibcon#first serial, iclass 18, count 2 2006.285.11:37:43.71#ibcon#enter sib2, iclass 18, count 2 2006.285.11:37:43.71#ibcon#flushed, iclass 18, count 2 2006.285.11:37:43.71#ibcon#about to write, iclass 18, count 2 2006.285.11:37:43.71#ibcon#wrote, iclass 18, count 2 2006.285.11:37:43.71#ibcon#about to read 3, iclass 18, count 2 2006.285.11:37:43.73#ibcon#read 3, iclass 18, count 2 2006.285.11:37:43.73#ibcon#about to read 4, iclass 18, count 2 2006.285.11:37:43.73#ibcon#read 4, iclass 18, count 2 2006.285.11:37:43.73#ibcon#about to read 5, iclass 18, count 2 2006.285.11:37:43.73#ibcon#read 5, iclass 18, count 2 2006.285.11:37:43.73#ibcon#about to read 6, iclass 18, count 2 2006.285.11:37:43.73#ibcon#read 6, iclass 18, count 2 2006.285.11:37:43.73#ibcon#end of sib2, iclass 18, count 2 2006.285.11:37:43.73#ibcon#*mode == 0, iclass 18, count 2 2006.285.11:37:43.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.11:37:43.73#ibcon#[27=AT07-04\r\n] 2006.285.11:37:43.73#ibcon#*before write, iclass 18, count 2 2006.285.11:37:43.73#ibcon#enter sib2, iclass 18, count 2 2006.285.11:37:43.73#ibcon#flushed, iclass 18, count 2 2006.285.11:37:43.73#ibcon#about to write, iclass 18, count 2 2006.285.11:37:43.73#ibcon#wrote, iclass 18, count 2 2006.285.11:37:43.73#ibcon#about to read 3, iclass 18, count 2 2006.285.11:37:43.76#ibcon#read 3, iclass 18, count 2 2006.285.11:37:43.76#ibcon#about to read 4, iclass 18, count 2 2006.285.11:37:43.76#ibcon#read 4, iclass 18, count 2 2006.285.11:37:43.76#ibcon#about to read 5, iclass 18, count 2 2006.285.11:37:43.76#ibcon#read 5, iclass 18, count 2 2006.285.11:37:43.76#ibcon#about to read 6, iclass 18, count 2 2006.285.11:37:43.76#ibcon#read 6, iclass 18, count 2 2006.285.11:37:43.76#ibcon#end of sib2, iclass 18, count 2 2006.285.11:37:43.76#ibcon#*after write, iclass 18, count 2 2006.285.11:37:43.76#ibcon#*before return 0, iclass 18, count 2 2006.285.11:37:43.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:37:43.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:37:43.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.11:37:43.76#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:43.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:37:43.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:37:43.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:37:43.88#ibcon#enter wrdev, iclass 18, count 0 2006.285.11:37:43.88#ibcon#first serial, iclass 18, count 0 2006.285.11:37:43.88#ibcon#enter sib2, iclass 18, count 0 2006.285.11:37:43.88#ibcon#flushed, iclass 18, count 0 2006.285.11:37:43.88#ibcon#about to write, iclass 18, count 0 2006.285.11:37:43.88#ibcon#wrote, iclass 18, count 0 2006.285.11:37:43.88#ibcon#about to read 3, iclass 18, count 0 2006.285.11:37:43.90#ibcon#read 3, iclass 18, count 0 2006.285.11:37:43.90#ibcon#about to read 4, iclass 18, count 0 2006.285.11:37:43.90#ibcon#read 4, iclass 18, count 0 2006.285.11:37:43.90#ibcon#about to read 5, iclass 18, count 0 2006.285.11:37:43.90#ibcon#read 5, iclass 18, count 0 2006.285.11:37:43.90#ibcon#about to read 6, iclass 18, count 0 2006.285.11:37:43.90#ibcon#read 6, iclass 18, count 0 2006.285.11:37:43.90#ibcon#end of sib2, iclass 18, count 0 2006.285.11:37:43.90#ibcon#*mode == 0, iclass 18, count 0 2006.285.11:37:43.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.11:37:43.90#ibcon#[27=USB\r\n] 2006.285.11:37:43.90#ibcon#*before write, iclass 18, count 0 2006.285.11:37:43.90#ibcon#enter sib2, iclass 18, count 0 2006.285.11:37:43.90#ibcon#flushed, iclass 18, count 0 2006.285.11:37:43.90#ibcon#about to write, iclass 18, count 0 2006.285.11:37:43.90#ibcon#wrote, iclass 18, count 0 2006.285.11:37:43.90#ibcon#about to read 3, iclass 18, count 0 2006.285.11:37:43.93#ibcon#read 3, iclass 18, count 0 2006.285.11:37:43.93#ibcon#about to read 4, iclass 18, count 0 2006.285.11:37:43.93#ibcon#read 4, iclass 18, count 0 2006.285.11:37:43.93#ibcon#about to read 5, iclass 18, count 0 2006.285.11:37:43.93#ibcon#read 5, iclass 18, count 0 2006.285.11:37:43.93#ibcon#about to read 6, iclass 18, count 0 2006.285.11:37:43.93#ibcon#read 6, iclass 18, count 0 2006.285.11:37:43.93#ibcon#end of sib2, iclass 18, count 0 2006.285.11:37:43.93#ibcon#*after write, iclass 18, count 0 2006.285.11:37:43.93#ibcon#*before return 0, iclass 18, count 0 2006.285.11:37:43.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:37:43.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:37:43.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.11:37:43.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.11:37:43.93$vck44/vblo=8,744.99 2006.285.11:37:43.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.11:37:43.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.11:37:43.93#ibcon#ireg 17 cls_cnt 0 2006.285.11:37:43.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:37:43.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:37:43.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:37:43.93#ibcon#enter wrdev, iclass 20, count 0 2006.285.11:37:43.93#ibcon#first serial, iclass 20, count 0 2006.285.11:37:43.93#ibcon#enter sib2, iclass 20, count 0 2006.285.11:37:43.93#ibcon#flushed, iclass 20, count 0 2006.285.11:37:43.93#ibcon#about to write, iclass 20, count 0 2006.285.11:37:43.93#ibcon#wrote, iclass 20, count 0 2006.285.11:37:43.93#ibcon#about to read 3, iclass 20, count 0 2006.285.11:37:43.95#ibcon#read 3, iclass 20, count 0 2006.285.11:37:43.95#ibcon#about to read 4, iclass 20, count 0 2006.285.11:37:43.95#ibcon#read 4, iclass 20, count 0 2006.285.11:37:43.95#ibcon#about to read 5, iclass 20, count 0 2006.285.11:37:43.95#ibcon#read 5, iclass 20, count 0 2006.285.11:37:43.95#ibcon#about to read 6, iclass 20, count 0 2006.285.11:37:43.95#ibcon#read 6, iclass 20, count 0 2006.285.11:37:43.95#ibcon#end of sib2, iclass 20, count 0 2006.285.11:37:43.95#ibcon#*mode == 0, iclass 20, count 0 2006.285.11:37:43.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.11:37:43.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:37:43.95#ibcon#*before write, iclass 20, count 0 2006.285.11:37:43.95#ibcon#enter sib2, iclass 20, count 0 2006.285.11:37:43.95#ibcon#flushed, iclass 20, count 0 2006.285.11:37:43.95#ibcon#about to write, iclass 20, count 0 2006.285.11:37:43.95#ibcon#wrote, iclass 20, count 0 2006.285.11:37:43.95#ibcon#about to read 3, iclass 20, count 0 2006.285.11:37:43.99#ibcon#read 3, iclass 20, count 0 2006.285.11:37:43.99#ibcon#about to read 4, iclass 20, count 0 2006.285.11:37:43.99#ibcon#read 4, iclass 20, count 0 2006.285.11:37:43.99#ibcon#about to read 5, iclass 20, count 0 2006.285.11:37:43.99#ibcon#read 5, iclass 20, count 0 2006.285.11:37:43.99#ibcon#about to read 6, iclass 20, count 0 2006.285.11:37:43.99#ibcon#read 6, iclass 20, count 0 2006.285.11:37:43.99#ibcon#end of sib2, iclass 20, count 0 2006.285.11:37:43.99#ibcon#*after write, iclass 20, count 0 2006.285.11:37:43.99#ibcon#*before return 0, iclass 20, count 0 2006.285.11:37:43.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:37:43.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:37:43.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.11:37:43.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.11:37:43.99$vck44/vb=8,4 2006.285.11:37:43.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.11:37:43.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.11:37:43.99#ibcon#ireg 11 cls_cnt 2 2006.285.11:37:43.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:37:44.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:37:44.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:37:44.05#ibcon#enter wrdev, iclass 22, count 2 2006.285.11:37:44.05#ibcon#first serial, iclass 22, count 2 2006.285.11:37:44.05#ibcon#enter sib2, iclass 22, count 2 2006.285.11:37:44.05#ibcon#flushed, iclass 22, count 2 2006.285.11:37:44.05#ibcon#about to write, iclass 22, count 2 2006.285.11:37:44.05#ibcon#wrote, iclass 22, count 2 2006.285.11:37:44.05#ibcon#about to read 3, iclass 22, count 2 2006.285.11:37:44.07#ibcon#read 3, iclass 22, count 2 2006.285.11:37:44.07#ibcon#about to read 4, iclass 22, count 2 2006.285.11:37:44.07#ibcon#read 4, iclass 22, count 2 2006.285.11:37:44.07#ibcon#about to read 5, iclass 22, count 2 2006.285.11:37:44.07#ibcon#read 5, iclass 22, count 2 2006.285.11:37:44.07#ibcon#about to read 6, iclass 22, count 2 2006.285.11:37:44.07#ibcon#read 6, iclass 22, count 2 2006.285.11:37:44.07#ibcon#end of sib2, iclass 22, count 2 2006.285.11:37:44.07#ibcon#*mode == 0, iclass 22, count 2 2006.285.11:37:44.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.11:37:44.07#ibcon#[27=AT08-04\r\n] 2006.285.11:37:44.07#ibcon#*before write, iclass 22, count 2 2006.285.11:37:44.07#ibcon#enter sib2, iclass 22, count 2 2006.285.11:37:44.07#ibcon#flushed, iclass 22, count 2 2006.285.11:37:44.07#ibcon#about to write, iclass 22, count 2 2006.285.11:37:44.07#ibcon#wrote, iclass 22, count 2 2006.285.11:37:44.07#ibcon#about to read 3, iclass 22, count 2 2006.285.11:37:44.10#ibcon#read 3, iclass 22, count 2 2006.285.11:37:44.10#ibcon#about to read 4, iclass 22, count 2 2006.285.11:37:44.10#ibcon#read 4, iclass 22, count 2 2006.285.11:37:44.10#ibcon#about to read 5, iclass 22, count 2 2006.285.11:37:44.10#ibcon#read 5, iclass 22, count 2 2006.285.11:37:44.10#ibcon#about to read 6, iclass 22, count 2 2006.285.11:37:44.10#ibcon#read 6, iclass 22, count 2 2006.285.11:37:44.10#ibcon#end of sib2, iclass 22, count 2 2006.285.11:37:44.10#ibcon#*after write, iclass 22, count 2 2006.285.11:37:44.10#ibcon#*before return 0, iclass 22, count 2 2006.285.11:37:44.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:37:44.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:37:44.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.11:37:44.10#ibcon#ireg 7 cls_cnt 0 2006.285.11:37:44.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:37:44.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:37:44.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:37:44.22#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:37:44.22#ibcon#first serial, iclass 22, count 0 2006.285.11:37:44.22#ibcon#enter sib2, iclass 22, count 0 2006.285.11:37:44.22#ibcon#flushed, iclass 22, count 0 2006.285.11:37:44.22#ibcon#about to write, iclass 22, count 0 2006.285.11:37:44.22#ibcon#wrote, iclass 22, count 0 2006.285.11:37:44.22#ibcon#about to read 3, iclass 22, count 0 2006.285.11:37:44.24#ibcon#read 3, iclass 22, count 0 2006.285.11:37:44.24#ibcon#about to read 4, iclass 22, count 0 2006.285.11:37:44.24#ibcon#read 4, iclass 22, count 0 2006.285.11:37:44.24#ibcon#about to read 5, iclass 22, count 0 2006.285.11:37:44.24#ibcon#read 5, iclass 22, count 0 2006.285.11:37:44.24#ibcon#about to read 6, iclass 22, count 0 2006.285.11:37:44.24#ibcon#read 6, iclass 22, count 0 2006.285.11:37:44.24#ibcon#end of sib2, iclass 22, count 0 2006.285.11:37:44.24#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:37:44.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:37:44.24#ibcon#[27=USB\r\n] 2006.285.11:37:44.24#ibcon#*before write, iclass 22, count 0 2006.285.11:37:44.24#ibcon#enter sib2, iclass 22, count 0 2006.285.11:37:44.24#ibcon#flushed, iclass 22, count 0 2006.285.11:37:44.24#ibcon#about to write, iclass 22, count 0 2006.285.11:37:44.24#ibcon#wrote, iclass 22, count 0 2006.285.11:37:44.24#ibcon#about to read 3, iclass 22, count 0 2006.285.11:37:44.27#ibcon#read 3, iclass 22, count 0 2006.285.11:37:44.27#ibcon#about to read 4, iclass 22, count 0 2006.285.11:37:44.27#ibcon#read 4, iclass 22, count 0 2006.285.11:37:44.27#ibcon#about to read 5, iclass 22, count 0 2006.285.11:37:44.27#ibcon#read 5, iclass 22, count 0 2006.285.11:37:44.27#ibcon#about to read 6, iclass 22, count 0 2006.285.11:37:44.27#ibcon#read 6, iclass 22, count 0 2006.285.11:37:44.27#ibcon#end of sib2, iclass 22, count 0 2006.285.11:37:44.27#ibcon#*after write, iclass 22, count 0 2006.285.11:37:44.27#ibcon#*before return 0, iclass 22, count 0 2006.285.11:37:44.27#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:37:44.27#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:37:44.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:37:44.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:37:44.27$vck44/vabw=wide 2006.285.11:37:44.27#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.11:37:44.27#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.11:37:44.27#ibcon#ireg 8 cls_cnt 0 2006.285.11:37:44.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:37:44.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:37:44.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:37:44.27#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:37:44.27#ibcon#first serial, iclass 24, count 0 2006.285.11:37:44.27#ibcon#enter sib2, iclass 24, count 0 2006.285.11:37:44.27#ibcon#flushed, iclass 24, count 0 2006.285.11:37:44.27#ibcon#about to write, iclass 24, count 0 2006.285.11:37:44.27#ibcon#wrote, iclass 24, count 0 2006.285.11:37:44.27#ibcon#about to read 3, iclass 24, count 0 2006.285.11:37:44.29#ibcon#read 3, iclass 24, count 0 2006.285.11:37:44.29#ibcon#about to read 4, iclass 24, count 0 2006.285.11:37:44.29#ibcon#read 4, iclass 24, count 0 2006.285.11:37:44.29#ibcon#about to read 5, iclass 24, count 0 2006.285.11:37:44.29#ibcon#read 5, iclass 24, count 0 2006.285.11:37:44.29#ibcon#about to read 6, iclass 24, count 0 2006.285.11:37:44.29#ibcon#read 6, iclass 24, count 0 2006.285.11:37:44.29#ibcon#end of sib2, iclass 24, count 0 2006.285.11:37:44.29#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:37:44.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:37:44.29#ibcon#[25=BW32\r\n] 2006.285.11:37:44.29#ibcon#*before write, iclass 24, count 0 2006.285.11:37:44.29#ibcon#enter sib2, iclass 24, count 0 2006.285.11:37:44.29#ibcon#flushed, iclass 24, count 0 2006.285.11:37:44.29#ibcon#about to write, iclass 24, count 0 2006.285.11:37:44.29#ibcon#wrote, iclass 24, count 0 2006.285.11:37:44.29#ibcon#about to read 3, iclass 24, count 0 2006.285.11:37:44.32#ibcon#read 3, iclass 24, count 0 2006.285.11:37:44.32#ibcon#about to read 4, iclass 24, count 0 2006.285.11:37:44.32#ibcon#read 4, iclass 24, count 0 2006.285.11:37:44.32#ibcon#about to read 5, iclass 24, count 0 2006.285.11:37:44.32#ibcon#read 5, iclass 24, count 0 2006.285.11:37:44.32#ibcon#about to read 6, iclass 24, count 0 2006.285.11:37:44.32#ibcon#read 6, iclass 24, count 0 2006.285.11:37:44.32#ibcon#end of sib2, iclass 24, count 0 2006.285.11:37:44.32#ibcon#*after write, iclass 24, count 0 2006.285.11:37:44.32#ibcon#*before return 0, iclass 24, count 0 2006.285.11:37:44.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:37:44.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:37:44.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:37:44.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:37:44.32$vck44/vbbw=wide 2006.285.11:37:44.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.11:37:44.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.11:37:44.32#ibcon#ireg 8 cls_cnt 0 2006.285.11:37:44.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:37:44.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:37:44.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:37:44.39#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:37:44.39#ibcon#first serial, iclass 26, count 0 2006.285.11:37:44.39#ibcon#enter sib2, iclass 26, count 0 2006.285.11:37:44.39#ibcon#flushed, iclass 26, count 0 2006.285.11:37:44.39#ibcon#about to write, iclass 26, count 0 2006.285.11:37:44.39#ibcon#wrote, iclass 26, count 0 2006.285.11:37:44.39#ibcon#about to read 3, iclass 26, count 0 2006.285.11:37:44.41#ibcon#read 3, iclass 26, count 0 2006.285.11:37:44.41#ibcon#about to read 4, iclass 26, count 0 2006.285.11:37:44.41#ibcon#read 4, iclass 26, count 0 2006.285.11:37:44.41#ibcon#about to read 5, iclass 26, count 0 2006.285.11:37:44.41#ibcon#read 5, iclass 26, count 0 2006.285.11:37:44.41#ibcon#about to read 6, iclass 26, count 0 2006.285.11:37:44.41#ibcon#read 6, iclass 26, count 0 2006.285.11:37:44.41#ibcon#end of sib2, iclass 26, count 0 2006.285.11:37:44.41#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:37:44.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:37:44.41#ibcon#[27=BW32\r\n] 2006.285.11:37:44.41#ibcon#*before write, iclass 26, count 0 2006.285.11:37:44.41#ibcon#enter sib2, iclass 26, count 0 2006.285.11:37:44.41#ibcon#flushed, iclass 26, count 0 2006.285.11:37:44.41#ibcon#about to write, iclass 26, count 0 2006.285.11:37:44.41#ibcon#wrote, iclass 26, count 0 2006.285.11:37:44.41#ibcon#about to read 3, iclass 26, count 0 2006.285.11:37:44.44#ibcon#read 3, iclass 26, count 0 2006.285.11:37:44.44#ibcon#about to read 4, iclass 26, count 0 2006.285.11:37:44.44#ibcon#read 4, iclass 26, count 0 2006.285.11:37:44.44#ibcon#about to read 5, iclass 26, count 0 2006.285.11:37:44.44#ibcon#read 5, iclass 26, count 0 2006.285.11:37:44.44#ibcon#about to read 6, iclass 26, count 0 2006.285.11:37:44.44#ibcon#read 6, iclass 26, count 0 2006.285.11:37:44.44#ibcon#end of sib2, iclass 26, count 0 2006.285.11:37:44.44#ibcon#*after write, iclass 26, count 0 2006.285.11:37:44.44#ibcon#*before return 0, iclass 26, count 0 2006.285.11:37:44.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:37:44.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:37:44.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:37:44.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:37:44.44$setupk4/ifdk4 2006.285.11:37:44.44$ifdk4/lo= 2006.285.11:37:44.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:37:44.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:37:44.44$ifdk4/patch= 2006.285.11:37:44.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:37:44.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:37:44.44$setupk4/!*+20s 2006.285.11:37:47.85#abcon#<5=/06 1.1 1.8 19.13 951015.3\r\n> 2006.285.11:37:47.87#abcon#{5=INTERFACE CLEAR} 2006.285.11:37:47.93#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:37:58.02#abcon#<5=/06 1.1 1.8 19.13 951015.3\r\n> 2006.285.11:37:58.04#abcon#{5=INTERFACE CLEAR} 2006.285.11:37:58.10#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:37:58.95$setupk4/"tpicd 2006.285.11:37:58.95$setupk4/echo=off 2006.285.11:37:58.95$setupk4/xlog=off 2006.285.11:37:58.95:!2006.285.11:44:00 2006.285.11:38:29.13#trakl#Source acquired 2006.285.11:38:30.13#flagr#flagr/antenna,acquired 2006.285.11:44:00.00:preob 2006.285.11:44:01.14/onsource/TRACKING 2006.285.11:44:01.14:!2006.285.11:44:10 2006.285.11:44:10.00:"tape 2006.285.11:44:10.00:"st=record 2006.285.11:44:10.00:data_valid=on 2006.285.11:44:10.00:midob 2006.285.11:44:10.14/onsource/TRACKING 2006.285.11:44:10.14/wx/19.04,1015.3,95 2006.285.11:44:10.19/cable/+6.4937E-03 2006.285.11:44:11.28/va/01,07,usb,yes,36,39 2006.285.11:44:11.28/va/02,06,usb,yes,36,36 2006.285.11:44:11.28/va/03,07,usb,yes,35,37 2006.285.11:44:11.28/va/04,06,usb,yes,37,39 2006.285.11:44:11.28/va/05,03,usb,yes,36,37 2006.285.11:44:11.28/va/06,04,usb,yes,33,32 2006.285.11:44:11.28/va/07,04,usb,yes,34,34 2006.285.11:44:11.28/va/08,03,usb,yes,34,41 2006.285.11:44:11.51/valo/01,524.99,yes,locked 2006.285.11:44:11.51/valo/02,534.99,yes,locked 2006.285.11:44:11.51/valo/03,564.99,yes,locked 2006.285.11:44:11.51/valo/04,624.99,yes,locked 2006.285.11:44:11.51/valo/05,734.99,yes,locked 2006.285.11:44:11.51/valo/06,814.99,yes,locked 2006.285.11:44:11.51/valo/07,864.99,yes,locked 2006.285.11:44:11.51/valo/08,884.99,yes,locked 2006.285.11:44:12.60/vb/01,04,usb,yes,32,30 2006.285.11:44:12.60/vb/02,05,usb,yes,30,30 2006.285.11:44:12.60/vb/03,04,usb,yes,31,35 2006.285.11:44:12.60/vb/04,05,usb,yes,32,30 2006.285.11:44:12.60/vb/05,04,usb,yes,28,31 2006.285.11:44:12.60/vb/06,03,usb,yes,40,36 2006.285.11:44:12.60/vb/07,04,usb,yes,32,32 2006.285.11:44:12.60/vb/08,04,usb,yes,29,33 2006.285.11:44:12.83/vblo/01,629.99,yes,locked 2006.285.11:44:12.83/vblo/02,634.99,yes,locked 2006.285.11:44:12.83/vblo/03,649.99,yes,locked 2006.285.11:44:12.83/vblo/04,679.99,yes,locked 2006.285.11:44:12.83/vblo/05,709.99,yes,locked 2006.285.11:44:12.83/vblo/06,719.99,yes,locked 2006.285.11:44:12.83/vblo/07,734.99,yes,locked 2006.285.11:44:12.83/vblo/08,744.99,yes,locked 2006.285.11:44:12.98/vabw/8 2006.285.11:44:13.13/vbbw/8 2006.285.11:44:13.22/xfe/off,on,12.2 2006.285.11:44:13.61/ifatt/23,28,28,28 2006.285.11:44:14.08/fmout-gps/S +2.68E-07 2006.285.11:44:14.10:!2006.285.11:44:50 2006.285.11:44:50.00:data_valid=off 2006.285.11:44:50.00:"et 2006.285.11:44:50.00:!+3s 2006.285.11:44:53.01:"tape 2006.285.11:44:53.01:postob 2006.285.11:44:53.07/cable/+6.4924E-03 2006.285.11:44:53.07/wx/19.04,1015.3,95 2006.285.11:44:54.08/fmout-gps/S +2.70E-07 2006.285.11:44:54.08:scan_name=285-1146,jd0610,70 2006.285.11:44:54.08:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.285.11:44:55.14#flagr#flagr/antenna,new-source 2006.285.11:44:55.14:checkk5 2006.285.11:44:55.73/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:44:56.12/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:44:56.65/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:44:57.02/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:44:57.38/chk_obsdata//k5ts1/T2851144??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.11:44:57.78/chk_obsdata//k5ts2/T2851144??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.11:44:58.14/chk_obsdata//k5ts3/T2851144??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.11:44:58.57/chk_obsdata//k5ts4/T2851144??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.11:44:59.28/k5log//k5ts1_log_newline 2006.285.11:45:00.11/k5log//k5ts2_log_newline 2006.285.11:45:00.90/k5log//k5ts3_log_newline 2006.285.11:45:01.73/k5log//k5ts4_log_newline 2006.285.11:45:01.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:45:01.75:setupk4=1 2006.285.11:45:01.75$setupk4/echo=on 2006.285.11:45:01.75$setupk4/pcalon 2006.285.11:45:01.75$pcalon/"no phase cal control is implemented here 2006.285.11:45:01.75$setupk4/"tpicd=stop 2006.285.11:45:01.75$setupk4/"rec=synch_on 2006.285.11:45:01.75$setupk4/"rec_mode=128 2006.285.11:45:01.75$setupk4/!* 2006.285.11:45:01.75$setupk4/recpk4 2006.285.11:45:01.75$recpk4/recpatch= 2006.285.11:45:01.75$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:45:01.75$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:45:01.75$setupk4/vck44 2006.285.11:45:01.75$vck44/valo=1,524.99 2006.285.11:45:01.75#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.11:45:01.75#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.11:45:01.75#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:01.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:45:01.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:45:01.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:45:01.75#ibcon#enter wrdev, iclass 23, count 0 2006.285.11:45:01.75#ibcon#first serial, iclass 23, count 0 2006.285.11:45:01.75#ibcon#enter sib2, iclass 23, count 0 2006.285.11:45:01.75#ibcon#flushed, iclass 23, count 0 2006.285.11:45:01.75#ibcon#about to write, iclass 23, count 0 2006.285.11:45:01.75#ibcon#wrote, iclass 23, count 0 2006.285.11:45:01.75#ibcon#about to read 3, iclass 23, count 0 2006.285.11:45:01.77#ibcon#read 3, iclass 23, count 0 2006.285.11:45:01.77#ibcon#about to read 4, iclass 23, count 0 2006.285.11:45:01.77#ibcon#read 4, iclass 23, count 0 2006.285.11:45:01.77#ibcon#about to read 5, iclass 23, count 0 2006.285.11:45:01.77#ibcon#read 5, iclass 23, count 0 2006.285.11:45:01.77#ibcon#about to read 6, iclass 23, count 0 2006.285.11:45:01.77#ibcon#read 6, iclass 23, count 0 2006.285.11:45:01.77#ibcon#end of sib2, iclass 23, count 0 2006.285.11:45:01.77#ibcon#*mode == 0, iclass 23, count 0 2006.285.11:45:01.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.11:45:01.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:45:01.77#ibcon#*before write, iclass 23, count 0 2006.285.11:45:01.77#ibcon#enter sib2, iclass 23, count 0 2006.285.11:45:01.77#ibcon#flushed, iclass 23, count 0 2006.285.11:45:01.77#ibcon#about to write, iclass 23, count 0 2006.285.11:45:01.77#ibcon#wrote, iclass 23, count 0 2006.285.11:45:01.77#ibcon#about to read 3, iclass 23, count 0 2006.285.11:45:01.82#ibcon#read 3, iclass 23, count 0 2006.285.11:45:01.82#ibcon#about to read 4, iclass 23, count 0 2006.285.11:45:01.82#ibcon#read 4, iclass 23, count 0 2006.285.11:45:01.82#ibcon#about to read 5, iclass 23, count 0 2006.285.11:45:01.82#ibcon#read 5, iclass 23, count 0 2006.285.11:45:01.82#ibcon#about to read 6, iclass 23, count 0 2006.285.11:45:01.82#ibcon#read 6, iclass 23, count 0 2006.285.11:45:01.82#ibcon#end of sib2, iclass 23, count 0 2006.285.11:45:01.82#ibcon#*after write, iclass 23, count 0 2006.285.11:45:01.82#ibcon#*before return 0, iclass 23, count 0 2006.285.11:45:01.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:45:01.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:45:01.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.11:45:01.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.11:45:01.82$vck44/va=1,7 2006.285.11:45:01.82#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.11:45:01.82#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.11:45:01.82#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:01.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:45:01.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:45:01.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:45:01.82#ibcon#enter wrdev, iclass 25, count 2 2006.285.11:45:01.82#ibcon#first serial, iclass 25, count 2 2006.285.11:45:01.82#ibcon#enter sib2, iclass 25, count 2 2006.285.11:45:01.82#ibcon#flushed, iclass 25, count 2 2006.285.11:45:01.82#ibcon#about to write, iclass 25, count 2 2006.285.11:45:01.82#ibcon#wrote, iclass 25, count 2 2006.285.11:45:01.82#ibcon#about to read 3, iclass 25, count 2 2006.285.11:45:01.84#ibcon#read 3, iclass 25, count 2 2006.285.11:45:01.84#ibcon#about to read 4, iclass 25, count 2 2006.285.11:45:01.84#ibcon#read 4, iclass 25, count 2 2006.285.11:45:01.84#ibcon#about to read 5, iclass 25, count 2 2006.285.11:45:01.84#ibcon#read 5, iclass 25, count 2 2006.285.11:45:01.84#ibcon#about to read 6, iclass 25, count 2 2006.285.11:45:01.84#ibcon#read 6, iclass 25, count 2 2006.285.11:45:01.84#ibcon#end of sib2, iclass 25, count 2 2006.285.11:45:01.84#ibcon#*mode == 0, iclass 25, count 2 2006.285.11:45:01.84#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.11:45:01.84#ibcon#[25=AT01-07\r\n] 2006.285.11:45:01.84#ibcon#*before write, iclass 25, count 2 2006.285.11:45:01.84#ibcon#enter sib2, iclass 25, count 2 2006.285.11:45:01.84#ibcon#flushed, iclass 25, count 2 2006.285.11:45:01.84#ibcon#about to write, iclass 25, count 2 2006.285.11:45:01.84#ibcon#wrote, iclass 25, count 2 2006.285.11:45:01.84#ibcon#about to read 3, iclass 25, count 2 2006.285.11:45:01.87#ibcon#read 3, iclass 25, count 2 2006.285.11:45:01.87#ibcon#about to read 4, iclass 25, count 2 2006.285.11:45:01.87#ibcon#read 4, iclass 25, count 2 2006.285.11:45:01.87#ibcon#about to read 5, iclass 25, count 2 2006.285.11:45:01.87#ibcon#read 5, iclass 25, count 2 2006.285.11:45:01.87#ibcon#about to read 6, iclass 25, count 2 2006.285.11:45:01.87#ibcon#read 6, iclass 25, count 2 2006.285.11:45:01.87#ibcon#end of sib2, iclass 25, count 2 2006.285.11:45:01.87#ibcon#*after write, iclass 25, count 2 2006.285.11:45:01.87#ibcon#*before return 0, iclass 25, count 2 2006.285.11:45:01.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:45:01.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:45:01.87#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.11:45:01.87#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:01.87#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:45:01.99#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:45:01.99#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:45:01.99#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:45:01.99#ibcon#first serial, iclass 25, count 0 2006.285.11:45:01.99#ibcon#enter sib2, iclass 25, count 0 2006.285.11:45:01.99#ibcon#flushed, iclass 25, count 0 2006.285.11:45:01.99#ibcon#about to write, iclass 25, count 0 2006.285.11:45:01.99#ibcon#wrote, iclass 25, count 0 2006.285.11:45:01.99#ibcon#about to read 3, iclass 25, count 0 2006.285.11:45:02.01#ibcon#read 3, iclass 25, count 0 2006.285.11:45:02.01#ibcon#about to read 4, iclass 25, count 0 2006.285.11:45:02.01#ibcon#read 4, iclass 25, count 0 2006.285.11:45:02.01#ibcon#about to read 5, iclass 25, count 0 2006.285.11:45:02.01#ibcon#read 5, iclass 25, count 0 2006.285.11:45:02.01#ibcon#about to read 6, iclass 25, count 0 2006.285.11:45:02.01#ibcon#read 6, iclass 25, count 0 2006.285.11:45:02.01#ibcon#end of sib2, iclass 25, count 0 2006.285.11:45:02.01#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:45:02.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:45:02.01#ibcon#[25=USB\r\n] 2006.285.11:45:02.01#ibcon#*before write, iclass 25, count 0 2006.285.11:45:02.01#ibcon#enter sib2, iclass 25, count 0 2006.285.11:45:02.01#ibcon#flushed, iclass 25, count 0 2006.285.11:45:02.01#ibcon#about to write, iclass 25, count 0 2006.285.11:45:02.01#ibcon#wrote, iclass 25, count 0 2006.285.11:45:02.01#ibcon#about to read 3, iclass 25, count 0 2006.285.11:45:02.04#ibcon#read 3, iclass 25, count 0 2006.285.11:45:02.04#ibcon#about to read 4, iclass 25, count 0 2006.285.11:45:02.04#ibcon#read 4, iclass 25, count 0 2006.285.11:45:02.04#ibcon#about to read 5, iclass 25, count 0 2006.285.11:45:02.04#ibcon#read 5, iclass 25, count 0 2006.285.11:45:02.04#ibcon#about to read 6, iclass 25, count 0 2006.285.11:45:02.04#ibcon#read 6, iclass 25, count 0 2006.285.11:45:02.04#ibcon#end of sib2, iclass 25, count 0 2006.285.11:45:02.04#ibcon#*after write, iclass 25, count 0 2006.285.11:45:02.04#ibcon#*before return 0, iclass 25, count 0 2006.285.11:45:02.04#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:45:02.04#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:45:02.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:45:02.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:45:02.04$vck44/valo=2,534.99 2006.285.11:45:02.04#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.11:45:02.04#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.11:45:02.04#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:02.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:45:02.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:45:02.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:45:02.04#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:45:02.04#ibcon#first serial, iclass 27, count 0 2006.285.11:45:02.04#ibcon#enter sib2, iclass 27, count 0 2006.285.11:45:02.04#ibcon#flushed, iclass 27, count 0 2006.285.11:45:02.04#ibcon#about to write, iclass 27, count 0 2006.285.11:45:02.04#ibcon#wrote, iclass 27, count 0 2006.285.11:45:02.04#ibcon#about to read 3, iclass 27, count 0 2006.285.11:45:02.06#ibcon#read 3, iclass 27, count 0 2006.285.11:45:02.06#ibcon#about to read 4, iclass 27, count 0 2006.285.11:45:02.06#ibcon#read 4, iclass 27, count 0 2006.285.11:45:02.06#ibcon#about to read 5, iclass 27, count 0 2006.285.11:45:02.06#ibcon#read 5, iclass 27, count 0 2006.285.11:45:02.06#ibcon#about to read 6, iclass 27, count 0 2006.285.11:45:02.06#ibcon#read 6, iclass 27, count 0 2006.285.11:45:02.06#ibcon#end of sib2, iclass 27, count 0 2006.285.11:45:02.06#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:45:02.06#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:45:02.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:45:02.06#ibcon#*before write, iclass 27, count 0 2006.285.11:45:02.06#ibcon#enter sib2, iclass 27, count 0 2006.285.11:45:02.06#ibcon#flushed, iclass 27, count 0 2006.285.11:45:02.06#ibcon#about to write, iclass 27, count 0 2006.285.11:45:02.06#ibcon#wrote, iclass 27, count 0 2006.285.11:45:02.06#ibcon#about to read 3, iclass 27, count 0 2006.285.11:45:02.10#ibcon#read 3, iclass 27, count 0 2006.285.11:45:02.10#ibcon#about to read 4, iclass 27, count 0 2006.285.11:45:02.10#ibcon#read 4, iclass 27, count 0 2006.285.11:45:02.10#ibcon#about to read 5, iclass 27, count 0 2006.285.11:45:02.10#ibcon#read 5, iclass 27, count 0 2006.285.11:45:02.10#ibcon#about to read 6, iclass 27, count 0 2006.285.11:45:02.10#ibcon#read 6, iclass 27, count 0 2006.285.11:45:02.10#ibcon#end of sib2, iclass 27, count 0 2006.285.11:45:02.10#ibcon#*after write, iclass 27, count 0 2006.285.11:45:02.10#ibcon#*before return 0, iclass 27, count 0 2006.285.11:45:02.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:45:02.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:45:02.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:45:02.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:45:02.10$vck44/va=2,6 2006.285.11:45:02.10#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.11:45:02.10#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.11:45:02.10#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:02.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:45:02.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:45:02.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:45:02.16#ibcon#enter wrdev, iclass 29, count 2 2006.285.11:45:02.16#ibcon#first serial, iclass 29, count 2 2006.285.11:45:02.16#ibcon#enter sib2, iclass 29, count 2 2006.285.11:45:02.16#ibcon#flushed, iclass 29, count 2 2006.285.11:45:02.16#ibcon#about to write, iclass 29, count 2 2006.285.11:45:02.16#ibcon#wrote, iclass 29, count 2 2006.285.11:45:02.16#ibcon#about to read 3, iclass 29, count 2 2006.285.11:45:02.18#ibcon#read 3, iclass 29, count 2 2006.285.11:45:02.18#ibcon#about to read 4, iclass 29, count 2 2006.285.11:45:02.18#ibcon#read 4, iclass 29, count 2 2006.285.11:45:02.18#ibcon#about to read 5, iclass 29, count 2 2006.285.11:45:02.18#ibcon#read 5, iclass 29, count 2 2006.285.11:45:02.18#ibcon#about to read 6, iclass 29, count 2 2006.285.11:45:02.18#ibcon#read 6, iclass 29, count 2 2006.285.11:45:02.18#ibcon#end of sib2, iclass 29, count 2 2006.285.11:45:02.18#ibcon#*mode == 0, iclass 29, count 2 2006.285.11:45:02.18#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.11:45:02.18#ibcon#[25=AT02-06\r\n] 2006.285.11:45:02.18#ibcon#*before write, iclass 29, count 2 2006.285.11:45:02.18#ibcon#enter sib2, iclass 29, count 2 2006.285.11:45:02.18#ibcon#flushed, iclass 29, count 2 2006.285.11:45:02.18#ibcon#about to write, iclass 29, count 2 2006.285.11:45:02.18#ibcon#wrote, iclass 29, count 2 2006.285.11:45:02.18#ibcon#about to read 3, iclass 29, count 2 2006.285.11:45:02.21#ibcon#read 3, iclass 29, count 2 2006.285.11:45:02.21#ibcon#about to read 4, iclass 29, count 2 2006.285.11:45:02.21#ibcon#read 4, iclass 29, count 2 2006.285.11:45:02.21#ibcon#about to read 5, iclass 29, count 2 2006.285.11:45:02.21#ibcon#read 5, iclass 29, count 2 2006.285.11:45:02.21#ibcon#about to read 6, iclass 29, count 2 2006.285.11:45:02.21#ibcon#read 6, iclass 29, count 2 2006.285.11:45:02.21#ibcon#end of sib2, iclass 29, count 2 2006.285.11:45:02.21#ibcon#*after write, iclass 29, count 2 2006.285.11:45:02.21#ibcon#*before return 0, iclass 29, count 2 2006.285.11:45:02.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:45:02.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:45:02.21#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.11:45:02.21#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:02.21#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:45:02.33#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:45:02.33#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:45:02.33#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:45:02.33#ibcon#first serial, iclass 29, count 0 2006.285.11:45:02.33#ibcon#enter sib2, iclass 29, count 0 2006.285.11:45:02.33#ibcon#flushed, iclass 29, count 0 2006.285.11:45:02.33#ibcon#about to write, iclass 29, count 0 2006.285.11:45:02.33#ibcon#wrote, iclass 29, count 0 2006.285.11:45:02.33#ibcon#about to read 3, iclass 29, count 0 2006.285.11:45:02.35#ibcon#read 3, iclass 29, count 0 2006.285.11:45:02.35#ibcon#about to read 4, iclass 29, count 0 2006.285.11:45:02.35#ibcon#read 4, iclass 29, count 0 2006.285.11:45:02.35#ibcon#about to read 5, iclass 29, count 0 2006.285.11:45:02.35#ibcon#read 5, iclass 29, count 0 2006.285.11:45:02.35#ibcon#about to read 6, iclass 29, count 0 2006.285.11:45:02.35#ibcon#read 6, iclass 29, count 0 2006.285.11:45:02.35#ibcon#end of sib2, iclass 29, count 0 2006.285.11:45:02.35#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:45:02.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:45:02.35#ibcon#[25=USB\r\n] 2006.285.11:45:02.35#ibcon#*before write, iclass 29, count 0 2006.285.11:45:02.35#ibcon#enter sib2, iclass 29, count 0 2006.285.11:45:02.35#ibcon#flushed, iclass 29, count 0 2006.285.11:45:02.35#ibcon#about to write, iclass 29, count 0 2006.285.11:45:02.35#ibcon#wrote, iclass 29, count 0 2006.285.11:45:02.35#ibcon#about to read 3, iclass 29, count 0 2006.285.11:45:02.38#ibcon#read 3, iclass 29, count 0 2006.285.11:45:02.38#ibcon#about to read 4, iclass 29, count 0 2006.285.11:45:02.38#ibcon#read 4, iclass 29, count 0 2006.285.11:45:02.38#ibcon#about to read 5, iclass 29, count 0 2006.285.11:45:02.38#ibcon#read 5, iclass 29, count 0 2006.285.11:45:02.38#ibcon#about to read 6, iclass 29, count 0 2006.285.11:45:02.38#ibcon#read 6, iclass 29, count 0 2006.285.11:45:02.38#ibcon#end of sib2, iclass 29, count 0 2006.285.11:45:02.38#ibcon#*after write, iclass 29, count 0 2006.285.11:45:02.38#ibcon#*before return 0, iclass 29, count 0 2006.285.11:45:02.38#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:45:02.38#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:45:02.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:45:02.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:45:02.38$vck44/valo=3,564.99 2006.285.11:45:02.38#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.11:45:02.38#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.11:45:02.38#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:02.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:45:02.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:45:02.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:45:02.38#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:45:02.38#ibcon#first serial, iclass 31, count 0 2006.285.11:45:02.38#ibcon#enter sib2, iclass 31, count 0 2006.285.11:45:02.38#ibcon#flushed, iclass 31, count 0 2006.285.11:45:02.38#ibcon#about to write, iclass 31, count 0 2006.285.11:45:02.38#ibcon#wrote, iclass 31, count 0 2006.285.11:45:02.38#ibcon#about to read 3, iclass 31, count 0 2006.285.11:45:02.40#ibcon#read 3, iclass 31, count 0 2006.285.11:45:02.40#ibcon#about to read 4, iclass 31, count 0 2006.285.11:45:02.40#ibcon#read 4, iclass 31, count 0 2006.285.11:45:02.40#ibcon#about to read 5, iclass 31, count 0 2006.285.11:45:02.40#ibcon#read 5, iclass 31, count 0 2006.285.11:45:02.40#ibcon#about to read 6, iclass 31, count 0 2006.285.11:45:02.40#ibcon#read 6, iclass 31, count 0 2006.285.11:45:02.40#ibcon#end of sib2, iclass 31, count 0 2006.285.11:45:02.40#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:45:02.40#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:45:02.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:45:02.40#ibcon#*before write, iclass 31, count 0 2006.285.11:45:02.40#ibcon#enter sib2, iclass 31, count 0 2006.285.11:45:02.40#ibcon#flushed, iclass 31, count 0 2006.285.11:45:02.40#ibcon#about to write, iclass 31, count 0 2006.285.11:45:02.40#ibcon#wrote, iclass 31, count 0 2006.285.11:45:02.40#ibcon#about to read 3, iclass 31, count 0 2006.285.11:45:02.44#ibcon#read 3, iclass 31, count 0 2006.285.11:45:02.44#ibcon#about to read 4, iclass 31, count 0 2006.285.11:45:02.44#ibcon#read 4, iclass 31, count 0 2006.285.11:45:02.44#ibcon#about to read 5, iclass 31, count 0 2006.285.11:45:02.44#ibcon#read 5, iclass 31, count 0 2006.285.11:45:02.44#ibcon#about to read 6, iclass 31, count 0 2006.285.11:45:02.44#ibcon#read 6, iclass 31, count 0 2006.285.11:45:02.44#ibcon#end of sib2, iclass 31, count 0 2006.285.11:45:02.44#ibcon#*after write, iclass 31, count 0 2006.285.11:45:02.44#ibcon#*before return 0, iclass 31, count 0 2006.285.11:45:02.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:45:02.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.11:45:02.44#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:45:02.44#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:45:02.44$vck44/va=3,7 2006.285.11:45:02.44#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.11:45:02.44#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.11:45:02.44#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:02.44#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:45:02.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:45:02.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:45:02.50#ibcon#enter wrdev, iclass 33, count 2 2006.285.11:45:02.50#ibcon#first serial, iclass 33, count 2 2006.285.11:45:02.50#ibcon#enter sib2, iclass 33, count 2 2006.285.11:45:02.50#ibcon#flushed, iclass 33, count 2 2006.285.11:45:02.50#ibcon#about to write, iclass 33, count 2 2006.285.11:45:02.50#ibcon#wrote, iclass 33, count 2 2006.285.11:45:02.50#ibcon#about to read 3, iclass 33, count 2 2006.285.11:45:02.52#ibcon#read 3, iclass 33, count 2 2006.285.11:45:02.52#ibcon#about to read 4, iclass 33, count 2 2006.285.11:45:02.52#ibcon#read 4, iclass 33, count 2 2006.285.11:45:02.52#ibcon#about to read 5, iclass 33, count 2 2006.285.11:45:02.52#ibcon#read 5, iclass 33, count 2 2006.285.11:45:02.52#ibcon#about to read 6, iclass 33, count 2 2006.285.11:45:02.52#ibcon#read 6, iclass 33, count 2 2006.285.11:45:02.52#ibcon#end of sib2, iclass 33, count 2 2006.285.11:45:02.52#ibcon#*mode == 0, iclass 33, count 2 2006.285.11:45:02.52#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.11:45:02.52#ibcon#[25=AT03-07\r\n] 2006.285.11:45:02.52#ibcon#*before write, iclass 33, count 2 2006.285.11:45:02.52#ibcon#enter sib2, iclass 33, count 2 2006.285.11:45:02.52#ibcon#flushed, iclass 33, count 2 2006.285.11:45:02.52#ibcon#about to write, iclass 33, count 2 2006.285.11:45:02.52#ibcon#wrote, iclass 33, count 2 2006.285.11:45:02.52#ibcon#about to read 3, iclass 33, count 2 2006.285.11:45:02.55#ibcon#read 3, iclass 33, count 2 2006.285.11:45:02.55#ibcon#about to read 4, iclass 33, count 2 2006.285.11:45:02.55#ibcon#read 4, iclass 33, count 2 2006.285.11:45:02.55#ibcon#about to read 5, iclass 33, count 2 2006.285.11:45:02.55#ibcon#read 5, iclass 33, count 2 2006.285.11:45:02.55#ibcon#about to read 6, iclass 33, count 2 2006.285.11:45:02.55#ibcon#read 6, iclass 33, count 2 2006.285.11:45:02.55#ibcon#end of sib2, iclass 33, count 2 2006.285.11:45:02.55#ibcon#*after write, iclass 33, count 2 2006.285.11:45:02.55#ibcon#*before return 0, iclass 33, count 2 2006.285.11:45:02.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:45:02.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.11:45:02.55#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.11:45:02.55#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:02.55#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:45:02.67#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:45:02.67#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:45:02.67#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:45:02.67#ibcon#first serial, iclass 33, count 0 2006.285.11:45:02.67#ibcon#enter sib2, iclass 33, count 0 2006.285.11:45:02.67#ibcon#flushed, iclass 33, count 0 2006.285.11:45:02.67#ibcon#about to write, iclass 33, count 0 2006.285.11:45:02.67#ibcon#wrote, iclass 33, count 0 2006.285.11:45:02.67#ibcon#about to read 3, iclass 33, count 0 2006.285.11:45:02.69#ibcon#read 3, iclass 33, count 0 2006.285.11:45:02.69#ibcon#about to read 4, iclass 33, count 0 2006.285.11:45:02.69#ibcon#read 4, iclass 33, count 0 2006.285.11:45:02.69#ibcon#about to read 5, iclass 33, count 0 2006.285.11:45:02.69#ibcon#read 5, iclass 33, count 0 2006.285.11:45:02.69#ibcon#about to read 6, iclass 33, count 0 2006.285.11:45:02.69#ibcon#read 6, iclass 33, count 0 2006.285.11:45:02.69#ibcon#end of sib2, iclass 33, count 0 2006.285.11:45:02.69#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:45:02.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:45:02.69#ibcon#[25=USB\r\n] 2006.285.11:45:02.69#ibcon#*before write, iclass 33, count 0 2006.285.11:45:02.69#ibcon#enter sib2, iclass 33, count 0 2006.285.11:45:02.69#ibcon#flushed, iclass 33, count 0 2006.285.11:45:02.69#ibcon#about to write, iclass 33, count 0 2006.285.11:45:02.69#ibcon#wrote, iclass 33, count 0 2006.285.11:45:02.69#ibcon#about to read 3, iclass 33, count 0 2006.285.11:45:02.72#ibcon#read 3, iclass 33, count 0 2006.285.11:45:02.72#ibcon#about to read 4, iclass 33, count 0 2006.285.11:45:02.72#ibcon#read 4, iclass 33, count 0 2006.285.11:45:02.72#ibcon#about to read 5, iclass 33, count 0 2006.285.11:45:02.72#ibcon#read 5, iclass 33, count 0 2006.285.11:45:02.72#ibcon#about to read 6, iclass 33, count 0 2006.285.11:45:02.72#ibcon#read 6, iclass 33, count 0 2006.285.11:45:02.72#ibcon#end of sib2, iclass 33, count 0 2006.285.11:45:02.72#ibcon#*after write, iclass 33, count 0 2006.285.11:45:02.72#ibcon#*before return 0, iclass 33, count 0 2006.285.11:45:02.72#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:45:02.72#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.11:45:02.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:45:02.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:45:02.72$vck44/valo=4,624.99 2006.285.11:45:02.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.11:45:02.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.11:45:02.72#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:02.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:45:02.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:45:02.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:45:02.72#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:45:02.72#ibcon#first serial, iclass 35, count 0 2006.285.11:45:02.72#ibcon#enter sib2, iclass 35, count 0 2006.285.11:45:02.72#ibcon#flushed, iclass 35, count 0 2006.285.11:45:02.72#ibcon#about to write, iclass 35, count 0 2006.285.11:45:02.72#ibcon#wrote, iclass 35, count 0 2006.285.11:45:02.72#ibcon#about to read 3, iclass 35, count 0 2006.285.11:45:02.74#ibcon#read 3, iclass 35, count 0 2006.285.11:45:02.74#ibcon#about to read 4, iclass 35, count 0 2006.285.11:45:02.74#ibcon#read 4, iclass 35, count 0 2006.285.11:45:02.74#ibcon#about to read 5, iclass 35, count 0 2006.285.11:45:02.74#ibcon#read 5, iclass 35, count 0 2006.285.11:45:02.74#ibcon#about to read 6, iclass 35, count 0 2006.285.11:45:02.74#ibcon#read 6, iclass 35, count 0 2006.285.11:45:02.74#ibcon#end of sib2, iclass 35, count 0 2006.285.11:45:02.74#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:45:02.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:45:02.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:45:02.74#ibcon#*before write, iclass 35, count 0 2006.285.11:45:02.74#ibcon#enter sib2, iclass 35, count 0 2006.285.11:45:02.74#ibcon#flushed, iclass 35, count 0 2006.285.11:45:02.74#ibcon#about to write, iclass 35, count 0 2006.285.11:45:02.74#ibcon#wrote, iclass 35, count 0 2006.285.11:45:02.74#ibcon#about to read 3, iclass 35, count 0 2006.285.11:45:02.78#ibcon#read 3, iclass 35, count 0 2006.285.11:45:02.78#ibcon#about to read 4, iclass 35, count 0 2006.285.11:45:02.78#ibcon#read 4, iclass 35, count 0 2006.285.11:45:02.78#ibcon#about to read 5, iclass 35, count 0 2006.285.11:45:02.78#ibcon#read 5, iclass 35, count 0 2006.285.11:45:02.78#ibcon#about to read 6, iclass 35, count 0 2006.285.11:45:02.78#ibcon#read 6, iclass 35, count 0 2006.285.11:45:02.78#ibcon#end of sib2, iclass 35, count 0 2006.285.11:45:02.78#ibcon#*after write, iclass 35, count 0 2006.285.11:45:02.78#ibcon#*before return 0, iclass 35, count 0 2006.285.11:45:02.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:45:02.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:45:02.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:45:02.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:45:02.78$vck44/va=4,6 2006.285.11:45:02.78#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.11:45:02.78#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.11:45:02.78#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:02.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:45:02.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:45:02.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:45:02.84#ibcon#enter wrdev, iclass 37, count 2 2006.285.11:45:02.84#ibcon#first serial, iclass 37, count 2 2006.285.11:45:02.84#ibcon#enter sib2, iclass 37, count 2 2006.285.11:45:02.84#ibcon#flushed, iclass 37, count 2 2006.285.11:45:02.84#ibcon#about to write, iclass 37, count 2 2006.285.11:45:02.84#ibcon#wrote, iclass 37, count 2 2006.285.11:45:02.84#ibcon#about to read 3, iclass 37, count 2 2006.285.11:45:02.86#ibcon#read 3, iclass 37, count 2 2006.285.11:45:02.86#ibcon#about to read 4, iclass 37, count 2 2006.285.11:45:02.86#ibcon#read 4, iclass 37, count 2 2006.285.11:45:02.86#ibcon#about to read 5, iclass 37, count 2 2006.285.11:45:02.86#ibcon#read 5, iclass 37, count 2 2006.285.11:45:02.86#ibcon#about to read 6, iclass 37, count 2 2006.285.11:45:02.86#ibcon#read 6, iclass 37, count 2 2006.285.11:45:02.86#ibcon#end of sib2, iclass 37, count 2 2006.285.11:45:02.86#ibcon#*mode == 0, iclass 37, count 2 2006.285.11:45:02.86#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.11:45:02.86#ibcon#[25=AT04-06\r\n] 2006.285.11:45:02.86#ibcon#*before write, iclass 37, count 2 2006.285.11:45:02.86#ibcon#enter sib2, iclass 37, count 2 2006.285.11:45:02.86#ibcon#flushed, iclass 37, count 2 2006.285.11:45:02.86#ibcon#about to write, iclass 37, count 2 2006.285.11:45:02.86#ibcon#wrote, iclass 37, count 2 2006.285.11:45:02.86#ibcon#about to read 3, iclass 37, count 2 2006.285.11:45:02.89#ibcon#read 3, iclass 37, count 2 2006.285.11:45:02.89#ibcon#about to read 4, iclass 37, count 2 2006.285.11:45:02.89#ibcon#read 4, iclass 37, count 2 2006.285.11:45:02.89#ibcon#about to read 5, iclass 37, count 2 2006.285.11:45:02.89#ibcon#read 5, iclass 37, count 2 2006.285.11:45:02.89#ibcon#about to read 6, iclass 37, count 2 2006.285.11:45:02.89#ibcon#read 6, iclass 37, count 2 2006.285.11:45:02.89#ibcon#end of sib2, iclass 37, count 2 2006.285.11:45:02.89#ibcon#*after write, iclass 37, count 2 2006.285.11:45:02.89#ibcon#*before return 0, iclass 37, count 2 2006.285.11:45:02.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:45:02.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:45:02.89#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.11:45:02.89#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:02.89#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:45:03.01#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:45:03.01#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:45:03.01#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:45:03.01#ibcon#first serial, iclass 37, count 0 2006.285.11:45:03.01#ibcon#enter sib2, iclass 37, count 0 2006.285.11:45:03.01#ibcon#flushed, iclass 37, count 0 2006.285.11:45:03.01#ibcon#about to write, iclass 37, count 0 2006.285.11:45:03.01#ibcon#wrote, iclass 37, count 0 2006.285.11:45:03.01#ibcon#about to read 3, iclass 37, count 0 2006.285.11:45:03.03#ibcon#read 3, iclass 37, count 0 2006.285.11:45:03.03#ibcon#about to read 4, iclass 37, count 0 2006.285.11:45:03.03#ibcon#read 4, iclass 37, count 0 2006.285.11:45:03.03#ibcon#about to read 5, iclass 37, count 0 2006.285.11:45:03.03#ibcon#read 5, iclass 37, count 0 2006.285.11:45:03.03#ibcon#about to read 6, iclass 37, count 0 2006.285.11:45:03.03#ibcon#read 6, iclass 37, count 0 2006.285.11:45:03.03#ibcon#end of sib2, iclass 37, count 0 2006.285.11:45:03.03#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:45:03.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:45:03.03#ibcon#[25=USB\r\n] 2006.285.11:45:03.03#ibcon#*before write, iclass 37, count 0 2006.285.11:45:03.03#ibcon#enter sib2, iclass 37, count 0 2006.285.11:45:03.03#ibcon#flushed, iclass 37, count 0 2006.285.11:45:03.03#ibcon#about to write, iclass 37, count 0 2006.285.11:45:03.03#ibcon#wrote, iclass 37, count 0 2006.285.11:45:03.03#ibcon#about to read 3, iclass 37, count 0 2006.285.11:45:03.06#ibcon#read 3, iclass 37, count 0 2006.285.11:45:03.06#ibcon#about to read 4, iclass 37, count 0 2006.285.11:45:03.06#ibcon#read 4, iclass 37, count 0 2006.285.11:45:03.06#ibcon#about to read 5, iclass 37, count 0 2006.285.11:45:03.06#ibcon#read 5, iclass 37, count 0 2006.285.11:45:03.06#ibcon#about to read 6, iclass 37, count 0 2006.285.11:45:03.06#ibcon#read 6, iclass 37, count 0 2006.285.11:45:03.06#ibcon#end of sib2, iclass 37, count 0 2006.285.11:45:03.06#ibcon#*after write, iclass 37, count 0 2006.285.11:45:03.06#ibcon#*before return 0, iclass 37, count 0 2006.285.11:45:03.06#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:45:03.06#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:45:03.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:45:03.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:45:03.06$vck44/valo=5,734.99 2006.285.11:45:03.06#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.11:45:03.06#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.11:45:03.06#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:03.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:45:03.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:45:03.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:45:03.06#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:45:03.06#ibcon#first serial, iclass 39, count 0 2006.285.11:45:03.06#ibcon#enter sib2, iclass 39, count 0 2006.285.11:45:03.06#ibcon#flushed, iclass 39, count 0 2006.285.11:45:03.06#ibcon#about to write, iclass 39, count 0 2006.285.11:45:03.06#ibcon#wrote, iclass 39, count 0 2006.285.11:45:03.06#ibcon#about to read 3, iclass 39, count 0 2006.285.11:45:03.08#ibcon#read 3, iclass 39, count 0 2006.285.11:45:03.08#ibcon#about to read 4, iclass 39, count 0 2006.285.11:45:03.08#ibcon#read 4, iclass 39, count 0 2006.285.11:45:03.08#ibcon#about to read 5, iclass 39, count 0 2006.285.11:45:03.08#ibcon#read 5, iclass 39, count 0 2006.285.11:45:03.08#ibcon#about to read 6, iclass 39, count 0 2006.285.11:45:03.08#ibcon#read 6, iclass 39, count 0 2006.285.11:45:03.08#ibcon#end of sib2, iclass 39, count 0 2006.285.11:45:03.08#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:45:03.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:45:03.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:45:03.08#ibcon#*before write, iclass 39, count 0 2006.285.11:45:03.08#ibcon#enter sib2, iclass 39, count 0 2006.285.11:45:03.08#ibcon#flushed, iclass 39, count 0 2006.285.11:45:03.08#ibcon#about to write, iclass 39, count 0 2006.285.11:45:03.08#ibcon#wrote, iclass 39, count 0 2006.285.11:45:03.08#ibcon#about to read 3, iclass 39, count 0 2006.285.11:45:03.12#ibcon#read 3, iclass 39, count 0 2006.285.11:45:03.12#ibcon#about to read 4, iclass 39, count 0 2006.285.11:45:03.12#ibcon#read 4, iclass 39, count 0 2006.285.11:45:03.12#ibcon#about to read 5, iclass 39, count 0 2006.285.11:45:03.12#ibcon#read 5, iclass 39, count 0 2006.285.11:45:03.12#ibcon#about to read 6, iclass 39, count 0 2006.285.11:45:03.12#ibcon#read 6, iclass 39, count 0 2006.285.11:45:03.12#ibcon#end of sib2, iclass 39, count 0 2006.285.11:45:03.12#ibcon#*after write, iclass 39, count 0 2006.285.11:45:03.12#ibcon#*before return 0, iclass 39, count 0 2006.285.11:45:03.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:45:03.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:45:03.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:45:03.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:45:03.12$vck44/va=5,3 2006.285.11:45:03.12#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.11:45:03.12#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.11:45:03.12#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:03.12#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:45:03.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:45:03.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:45:03.18#ibcon#enter wrdev, iclass 3, count 2 2006.285.11:45:03.18#ibcon#first serial, iclass 3, count 2 2006.285.11:45:03.18#ibcon#enter sib2, iclass 3, count 2 2006.285.11:45:03.18#ibcon#flushed, iclass 3, count 2 2006.285.11:45:03.18#ibcon#about to write, iclass 3, count 2 2006.285.11:45:03.18#ibcon#wrote, iclass 3, count 2 2006.285.11:45:03.18#ibcon#about to read 3, iclass 3, count 2 2006.285.11:45:03.20#ibcon#read 3, iclass 3, count 2 2006.285.11:45:03.20#ibcon#about to read 4, iclass 3, count 2 2006.285.11:45:03.20#ibcon#read 4, iclass 3, count 2 2006.285.11:45:03.20#ibcon#about to read 5, iclass 3, count 2 2006.285.11:45:03.20#ibcon#read 5, iclass 3, count 2 2006.285.11:45:03.20#ibcon#about to read 6, iclass 3, count 2 2006.285.11:45:03.20#ibcon#read 6, iclass 3, count 2 2006.285.11:45:03.20#ibcon#end of sib2, iclass 3, count 2 2006.285.11:45:03.20#ibcon#*mode == 0, iclass 3, count 2 2006.285.11:45:03.20#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.11:45:03.20#ibcon#[25=AT05-03\r\n] 2006.285.11:45:03.20#ibcon#*before write, iclass 3, count 2 2006.285.11:45:03.20#ibcon#enter sib2, iclass 3, count 2 2006.285.11:45:03.20#ibcon#flushed, iclass 3, count 2 2006.285.11:45:03.20#ibcon#about to write, iclass 3, count 2 2006.285.11:45:03.20#ibcon#wrote, iclass 3, count 2 2006.285.11:45:03.20#ibcon#about to read 3, iclass 3, count 2 2006.285.11:45:03.23#ibcon#read 3, iclass 3, count 2 2006.285.11:45:03.23#ibcon#about to read 4, iclass 3, count 2 2006.285.11:45:03.23#ibcon#read 4, iclass 3, count 2 2006.285.11:45:03.23#ibcon#about to read 5, iclass 3, count 2 2006.285.11:45:03.23#ibcon#read 5, iclass 3, count 2 2006.285.11:45:03.23#ibcon#about to read 6, iclass 3, count 2 2006.285.11:45:03.23#ibcon#read 6, iclass 3, count 2 2006.285.11:45:03.23#ibcon#end of sib2, iclass 3, count 2 2006.285.11:45:03.23#ibcon#*after write, iclass 3, count 2 2006.285.11:45:03.23#ibcon#*before return 0, iclass 3, count 2 2006.285.11:45:03.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:45:03.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:45:03.23#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.11:45:03.23#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:03.23#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:45:03.35#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:45:03.35#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:45:03.35#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:45:03.35#ibcon#first serial, iclass 3, count 0 2006.285.11:45:03.35#ibcon#enter sib2, iclass 3, count 0 2006.285.11:45:03.35#ibcon#flushed, iclass 3, count 0 2006.285.11:45:03.35#ibcon#about to write, iclass 3, count 0 2006.285.11:45:03.35#ibcon#wrote, iclass 3, count 0 2006.285.11:45:03.35#ibcon#about to read 3, iclass 3, count 0 2006.285.11:45:03.37#ibcon#read 3, iclass 3, count 0 2006.285.11:45:03.37#ibcon#about to read 4, iclass 3, count 0 2006.285.11:45:03.37#ibcon#read 4, iclass 3, count 0 2006.285.11:45:03.37#ibcon#about to read 5, iclass 3, count 0 2006.285.11:45:03.37#ibcon#read 5, iclass 3, count 0 2006.285.11:45:03.37#ibcon#about to read 6, iclass 3, count 0 2006.285.11:45:03.37#ibcon#read 6, iclass 3, count 0 2006.285.11:45:03.37#ibcon#end of sib2, iclass 3, count 0 2006.285.11:45:03.37#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:45:03.37#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:45:03.37#ibcon#[25=USB\r\n] 2006.285.11:45:03.37#ibcon#*before write, iclass 3, count 0 2006.285.11:45:03.37#ibcon#enter sib2, iclass 3, count 0 2006.285.11:45:03.37#ibcon#flushed, iclass 3, count 0 2006.285.11:45:03.37#ibcon#about to write, iclass 3, count 0 2006.285.11:45:03.37#ibcon#wrote, iclass 3, count 0 2006.285.11:45:03.37#ibcon#about to read 3, iclass 3, count 0 2006.285.11:45:03.40#ibcon#read 3, iclass 3, count 0 2006.285.11:45:03.40#ibcon#about to read 4, iclass 3, count 0 2006.285.11:45:03.40#ibcon#read 4, iclass 3, count 0 2006.285.11:45:03.40#ibcon#about to read 5, iclass 3, count 0 2006.285.11:45:03.40#ibcon#read 5, iclass 3, count 0 2006.285.11:45:03.40#ibcon#about to read 6, iclass 3, count 0 2006.285.11:45:03.40#ibcon#read 6, iclass 3, count 0 2006.285.11:45:03.40#ibcon#end of sib2, iclass 3, count 0 2006.285.11:45:03.40#ibcon#*after write, iclass 3, count 0 2006.285.11:45:03.40#ibcon#*before return 0, iclass 3, count 0 2006.285.11:45:03.40#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:45:03.40#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:45:03.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:45:03.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:45:03.40$vck44/valo=6,814.99 2006.285.11:45:03.40#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.11:45:03.40#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.11:45:03.40#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:03.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:45:03.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:45:03.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:45:03.40#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:45:03.40#ibcon#first serial, iclass 5, count 0 2006.285.11:45:03.40#ibcon#enter sib2, iclass 5, count 0 2006.285.11:45:03.40#ibcon#flushed, iclass 5, count 0 2006.285.11:45:03.40#ibcon#about to write, iclass 5, count 0 2006.285.11:45:03.40#ibcon#wrote, iclass 5, count 0 2006.285.11:45:03.40#ibcon#about to read 3, iclass 5, count 0 2006.285.11:45:03.42#ibcon#read 3, iclass 5, count 0 2006.285.11:45:03.42#ibcon#about to read 4, iclass 5, count 0 2006.285.11:45:03.42#ibcon#read 4, iclass 5, count 0 2006.285.11:45:03.42#ibcon#about to read 5, iclass 5, count 0 2006.285.11:45:03.42#ibcon#read 5, iclass 5, count 0 2006.285.11:45:03.42#ibcon#about to read 6, iclass 5, count 0 2006.285.11:45:03.42#ibcon#read 6, iclass 5, count 0 2006.285.11:45:03.42#ibcon#end of sib2, iclass 5, count 0 2006.285.11:45:03.42#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:45:03.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:45:03.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:45:03.42#ibcon#*before write, iclass 5, count 0 2006.285.11:45:03.42#ibcon#enter sib2, iclass 5, count 0 2006.285.11:45:03.42#ibcon#flushed, iclass 5, count 0 2006.285.11:45:03.42#ibcon#about to write, iclass 5, count 0 2006.285.11:45:03.42#ibcon#wrote, iclass 5, count 0 2006.285.11:45:03.42#ibcon#about to read 3, iclass 5, count 0 2006.285.11:45:03.46#ibcon#read 3, iclass 5, count 0 2006.285.11:45:03.46#ibcon#about to read 4, iclass 5, count 0 2006.285.11:45:03.46#ibcon#read 4, iclass 5, count 0 2006.285.11:45:03.46#ibcon#about to read 5, iclass 5, count 0 2006.285.11:45:03.46#ibcon#read 5, iclass 5, count 0 2006.285.11:45:03.46#ibcon#about to read 6, iclass 5, count 0 2006.285.11:45:03.46#ibcon#read 6, iclass 5, count 0 2006.285.11:45:03.46#ibcon#end of sib2, iclass 5, count 0 2006.285.11:45:03.46#ibcon#*after write, iclass 5, count 0 2006.285.11:45:03.46#ibcon#*before return 0, iclass 5, count 0 2006.285.11:45:03.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:45:03.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:45:03.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:45:03.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:45:03.46$vck44/va=6,4 2006.285.11:45:03.46#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.11:45:03.46#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.11:45:03.46#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:03.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:45:03.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:45:03.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:45:03.52#ibcon#enter wrdev, iclass 7, count 2 2006.285.11:45:03.52#ibcon#first serial, iclass 7, count 2 2006.285.11:45:03.52#ibcon#enter sib2, iclass 7, count 2 2006.285.11:45:03.52#ibcon#flushed, iclass 7, count 2 2006.285.11:45:03.52#ibcon#about to write, iclass 7, count 2 2006.285.11:45:03.52#ibcon#wrote, iclass 7, count 2 2006.285.11:45:03.52#ibcon#about to read 3, iclass 7, count 2 2006.285.11:45:03.54#ibcon#read 3, iclass 7, count 2 2006.285.11:45:03.54#ibcon#about to read 4, iclass 7, count 2 2006.285.11:45:03.54#ibcon#read 4, iclass 7, count 2 2006.285.11:45:03.54#ibcon#about to read 5, iclass 7, count 2 2006.285.11:45:03.54#ibcon#read 5, iclass 7, count 2 2006.285.11:45:03.54#ibcon#about to read 6, iclass 7, count 2 2006.285.11:45:03.54#ibcon#read 6, iclass 7, count 2 2006.285.11:45:03.54#ibcon#end of sib2, iclass 7, count 2 2006.285.11:45:03.54#ibcon#*mode == 0, iclass 7, count 2 2006.285.11:45:03.54#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.11:45:03.54#ibcon#[25=AT06-04\r\n] 2006.285.11:45:03.54#ibcon#*before write, iclass 7, count 2 2006.285.11:45:03.54#ibcon#enter sib2, iclass 7, count 2 2006.285.11:45:03.54#ibcon#flushed, iclass 7, count 2 2006.285.11:45:03.54#ibcon#about to write, iclass 7, count 2 2006.285.11:45:03.54#ibcon#wrote, iclass 7, count 2 2006.285.11:45:03.54#ibcon#about to read 3, iclass 7, count 2 2006.285.11:45:03.57#ibcon#read 3, iclass 7, count 2 2006.285.11:45:03.57#ibcon#about to read 4, iclass 7, count 2 2006.285.11:45:03.57#ibcon#read 4, iclass 7, count 2 2006.285.11:45:03.57#ibcon#about to read 5, iclass 7, count 2 2006.285.11:45:03.57#ibcon#read 5, iclass 7, count 2 2006.285.11:45:03.57#ibcon#about to read 6, iclass 7, count 2 2006.285.11:45:03.57#ibcon#read 6, iclass 7, count 2 2006.285.11:45:03.57#ibcon#end of sib2, iclass 7, count 2 2006.285.11:45:03.57#ibcon#*after write, iclass 7, count 2 2006.285.11:45:03.57#ibcon#*before return 0, iclass 7, count 2 2006.285.11:45:03.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:45:03.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:45:03.57#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.11:45:03.57#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:03.57#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:45:03.69#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:45:03.69#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:45:03.69#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:45:03.69#ibcon#first serial, iclass 7, count 0 2006.285.11:45:03.69#ibcon#enter sib2, iclass 7, count 0 2006.285.11:45:03.69#ibcon#flushed, iclass 7, count 0 2006.285.11:45:03.69#ibcon#about to write, iclass 7, count 0 2006.285.11:45:03.69#ibcon#wrote, iclass 7, count 0 2006.285.11:45:03.69#ibcon#about to read 3, iclass 7, count 0 2006.285.11:45:03.71#ibcon#read 3, iclass 7, count 0 2006.285.11:45:03.71#ibcon#about to read 4, iclass 7, count 0 2006.285.11:45:03.71#ibcon#read 4, iclass 7, count 0 2006.285.11:45:03.71#ibcon#about to read 5, iclass 7, count 0 2006.285.11:45:03.71#ibcon#read 5, iclass 7, count 0 2006.285.11:45:03.71#ibcon#about to read 6, iclass 7, count 0 2006.285.11:45:03.71#ibcon#read 6, iclass 7, count 0 2006.285.11:45:03.71#ibcon#end of sib2, iclass 7, count 0 2006.285.11:45:03.71#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:45:03.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:45:03.71#ibcon#[25=USB\r\n] 2006.285.11:45:03.71#ibcon#*before write, iclass 7, count 0 2006.285.11:45:03.71#ibcon#enter sib2, iclass 7, count 0 2006.285.11:45:03.71#ibcon#flushed, iclass 7, count 0 2006.285.11:45:03.71#ibcon#about to write, iclass 7, count 0 2006.285.11:45:03.71#ibcon#wrote, iclass 7, count 0 2006.285.11:45:03.71#ibcon#about to read 3, iclass 7, count 0 2006.285.11:45:03.74#ibcon#read 3, iclass 7, count 0 2006.285.11:45:03.74#ibcon#about to read 4, iclass 7, count 0 2006.285.11:45:03.74#ibcon#read 4, iclass 7, count 0 2006.285.11:45:03.74#ibcon#about to read 5, iclass 7, count 0 2006.285.11:45:03.74#ibcon#read 5, iclass 7, count 0 2006.285.11:45:03.74#ibcon#about to read 6, iclass 7, count 0 2006.285.11:45:03.74#ibcon#read 6, iclass 7, count 0 2006.285.11:45:03.74#ibcon#end of sib2, iclass 7, count 0 2006.285.11:45:03.74#ibcon#*after write, iclass 7, count 0 2006.285.11:45:03.74#ibcon#*before return 0, iclass 7, count 0 2006.285.11:45:03.74#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:45:03.74#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:45:03.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:45:03.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:45:03.74$vck44/valo=7,864.99 2006.285.11:45:03.74#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.11:45:03.74#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.11:45:03.74#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:03.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:45:03.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:45:03.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:45:03.74#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:45:03.74#ibcon#first serial, iclass 11, count 0 2006.285.11:45:03.74#ibcon#enter sib2, iclass 11, count 0 2006.285.11:45:03.74#ibcon#flushed, iclass 11, count 0 2006.285.11:45:03.74#ibcon#about to write, iclass 11, count 0 2006.285.11:45:03.74#ibcon#wrote, iclass 11, count 0 2006.285.11:45:03.74#ibcon#about to read 3, iclass 11, count 0 2006.285.11:45:03.76#ibcon#read 3, iclass 11, count 0 2006.285.11:45:03.76#ibcon#about to read 4, iclass 11, count 0 2006.285.11:45:03.76#ibcon#read 4, iclass 11, count 0 2006.285.11:45:03.76#ibcon#about to read 5, iclass 11, count 0 2006.285.11:45:03.76#ibcon#read 5, iclass 11, count 0 2006.285.11:45:03.76#ibcon#about to read 6, iclass 11, count 0 2006.285.11:45:03.76#ibcon#read 6, iclass 11, count 0 2006.285.11:45:03.76#ibcon#end of sib2, iclass 11, count 0 2006.285.11:45:03.76#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:45:03.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:45:03.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:45:03.76#ibcon#*before write, iclass 11, count 0 2006.285.11:45:03.76#ibcon#enter sib2, iclass 11, count 0 2006.285.11:45:03.76#ibcon#flushed, iclass 11, count 0 2006.285.11:45:03.76#ibcon#about to write, iclass 11, count 0 2006.285.11:45:03.76#ibcon#wrote, iclass 11, count 0 2006.285.11:45:03.76#ibcon#about to read 3, iclass 11, count 0 2006.285.11:45:03.80#ibcon#read 3, iclass 11, count 0 2006.285.11:45:03.80#ibcon#about to read 4, iclass 11, count 0 2006.285.11:45:03.80#ibcon#read 4, iclass 11, count 0 2006.285.11:45:03.80#ibcon#about to read 5, iclass 11, count 0 2006.285.11:45:03.80#ibcon#read 5, iclass 11, count 0 2006.285.11:45:03.80#ibcon#about to read 6, iclass 11, count 0 2006.285.11:45:03.80#ibcon#read 6, iclass 11, count 0 2006.285.11:45:03.80#ibcon#end of sib2, iclass 11, count 0 2006.285.11:45:03.80#ibcon#*after write, iclass 11, count 0 2006.285.11:45:03.80#ibcon#*before return 0, iclass 11, count 0 2006.285.11:45:03.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:45:03.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:45:03.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:45:03.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:45:03.80$vck44/va=7,4 2006.285.11:45:03.80#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.11:45:03.80#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.11:45:03.80#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:03.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:45:03.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:45:03.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:45:03.86#ibcon#enter wrdev, iclass 13, count 2 2006.285.11:45:03.86#ibcon#first serial, iclass 13, count 2 2006.285.11:45:03.86#ibcon#enter sib2, iclass 13, count 2 2006.285.11:45:03.86#ibcon#flushed, iclass 13, count 2 2006.285.11:45:03.86#ibcon#about to write, iclass 13, count 2 2006.285.11:45:03.86#ibcon#wrote, iclass 13, count 2 2006.285.11:45:03.86#ibcon#about to read 3, iclass 13, count 2 2006.285.11:45:03.88#ibcon#read 3, iclass 13, count 2 2006.285.11:45:03.88#ibcon#about to read 4, iclass 13, count 2 2006.285.11:45:03.88#ibcon#read 4, iclass 13, count 2 2006.285.11:45:03.88#ibcon#about to read 5, iclass 13, count 2 2006.285.11:45:03.88#ibcon#read 5, iclass 13, count 2 2006.285.11:45:03.88#ibcon#about to read 6, iclass 13, count 2 2006.285.11:45:03.88#ibcon#read 6, iclass 13, count 2 2006.285.11:45:03.88#ibcon#end of sib2, iclass 13, count 2 2006.285.11:45:03.88#ibcon#*mode == 0, iclass 13, count 2 2006.285.11:45:03.88#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.11:45:03.88#ibcon#[25=AT07-04\r\n] 2006.285.11:45:03.88#ibcon#*before write, iclass 13, count 2 2006.285.11:45:03.88#ibcon#enter sib2, iclass 13, count 2 2006.285.11:45:03.88#ibcon#flushed, iclass 13, count 2 2006.285.11:45:03.88#ibcon#about to write, iclass 13, count 2 2006.285.11:45:03.88#ibcon#wrote, iclass 13, count 2 2006.285.11:45:03.88#ibcon#about to read 3, iclass 13, count 2 2006.285.11:45:03.91#ibcon#read 3, iclass 13, count 2 2006.285.11:45:03.91#ibcon#about to read 4, iclass 13, count 2 2006.285.11:45:03.91#ibcon#read 4, iclass 13, count 2 2006.285.11:45:03.91#ibcon#about to read 5, iclass 13, count 2 2006.285.11:45:03.91#ibcon#read 5, iclass 13, count 2 2006.285.11:45:03.91#ibcon#about to read 6, iclass 13, count 2 2006.285.11:45:03.91#ibcon#read 6, iclass 13, count 2 2006.285.11:45:03.91#ibcon#end of sib2, iclass 13, count 2 2006.285.11:45:03.91#ibcon#*after write, iclass 13, count 2 2006.285.11:45:03.91#ibcon#*before return 0, iclass 13, count 2 2006.285.11:45:03.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:45:03.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:45:03.91#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.11:45:03.91#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:03.91#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:45:04.03#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:45:04.03#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:45:04.03#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:45:04.03#ibcon#first serial, iclass 13, count 0 2006.285.11:45:04.03#ibcon#enter sib2, iclass 13, count 0 2006.285.11:45:04.03#ibcon#flushed, iclass 13, count 0 2006.285.11:45:04.03#ibcon#about to write, iclass 13, count 0 2006.285.11:45:04.03#ibcon#wrote, iclass 13, count 0 2006.285.11:45:04.03#ibcon#about to read 3, iclass 13, count 0 2006.285.11:45:04.05#ibcon#read 3, iclass 13, count 0 2006.285.11:45:04.05#ibcon#about to read 4, iclass 13, count 0 2006.285.11:45:04.05#ibcon#read 4, iclass 13, count 0 2006.285.11:45:04.05#ibcon#about to read 5, iclass 13, count 0 2006.285.11:45:04.05#ibcon#read 5, iclass 13, count 0 2006.285.11:45:04.05#ibcon#about to read 6, iclass 13, count 0 2006.285.11:45:04.05#ibcon#read 6, iclass 13, count 0 2006.285.11:45:04.05#ibcon#end of sib2, iclass 13, count 0 2006.285.11:45:04.05#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:45:04.05#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:45:04.05#ibcon#[25=USB\r\n] 2006.285.11:45:04.05#ibcon#*before write, iclass 13, count 0 2006.285.11:45:04.05#ibcon#enter sib2, iclass 13, count 0 2006.285.11:45:04.05#ibcon#flushed, iclass 13, count 0 2006.285.11:45:04.05#ibcon#about to write, iclass 13, count 0 2006.285.11:45:04.05#ibcon#wrote, iclass 13, count 0 2006.285.11:45:04.05#ibcon#about to read 3, iclass 13, count 0 2006.285.11:45:04.08#ibcon#read 3, iclass 13, count 0 2006.285.11:45:04.08#ibcon#about to read 4, iclass 13, count 0 2006.285.11:45:04.08#ibcon#read 4, iclass 13, count 0 2006.285.11:45:04.08#ibcon#about to read 5, iclass 13, count 0 2006.285.11:45:04.08#ibcon#read 5, iclass 13, count 0 2006.285.11:45:04.08#ibcon#about to read 6, iclass 13, count 0 2006.285.11:45:04.08#ibcon#read 6, iclass 13, count 0 2006.285.11:45:04.08#ibcon#end of sib2, iclass 13, count 0 2006.285.11:45:04.08#ibcon#*after write, iclass 13, count 0 2006.285.11:45:04.08#ibcon#*before return 0, iclass 13, count 0 2006.285.11:45:04.08#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:45:04.08#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:45:04.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:45:04.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:45:04.08$vck44/valo=8,884.99 2006.285.11:45:04.08#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.11:45:04.08#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.11:45:04.08#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:04.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:45:04.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:45:04.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:45:04.08#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:45:04.08#ibcon#first serial, iclass 15, count 0 2006.285.11:45:04.08#ibcon#enter sib2, iclass 15, count 0 2006.285.11:45:04.08#ibcon#flushed, iclass 15, count 0 2006.285.11:45:04.08#ibcon#about to write, iclass 15, count 0 2006.285.11:45:04.08#ibcon#wrote, iclass 15, count 0 2006.285.11:45:04.08#ibcon#about to read 3, iclass 15, count 0 2006.285.11:45:04.10#ibcon#read 3, iclass 15, count 0 2006.285.11:45:04.10#ibcon#about to read 4, iclass 15, count 0 2006.285.11:45:04.10#ibcon#read 4, iclass 15, count 0 2006.285.11:45:04.10#ibcon#about to read 5, iclass 15, count 0 2006.285.11:45:04.10#ibcon#read 5, iclass 15, count 0 2006.285.11:45:04.10#ibcon#about to read 6, iclass 15, count 0 2006.285.11:45:04.10#ibcon#read 6, iclass 15, count 0 2006.285.11:45:04.10#ibcon#end of sib2, iclass 15, count 0 2006.285.11:45:04.10#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:45:04.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:45:04.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:45:04.10#ibcon#*before write, iclass 15, count 0 2006.285.11:45:04.10#ibcon#enter sib2, iclass 15, count 0 2006.285.11:45:04.10#ibcon#flushed, iclass 15, count 0 2006.285.11:45:04.10#ibcon#about to write, iclass 15, count 0 2006.285.11:45:04.10#ibcon#wrote, iclass 15, count 0 2006.285.11:45:04.10#ibcon#about to read 3, iclass 15, count 0 2006.285.11:45:04.14#ibcon#read 3, iclass 15, count 0 2006.285.11:45:04.14#ibcon#about to read 4, iclass 15, count 0 2006.285.11:45:04.14#ibcon#read 4, iclass 15, count 0 2006.285.11:45:04.14#ibcon#about to read 5, iclass 15, count 0 2006.285.11:45:04.14#ibcon#read 5, iclass 15, count 0 2006.285.11:45:04.14#ibcon#about to read 6, iclass 15, count 0 2006.285.11:45:04.14#ibcon#read 6, iclass 15, count 0 2006.285.11:45:04.14#ibcon#end of sib2, iclass 15, count 0 2006.285.11:45:04.14#ibcon#*after write, iclass 15, count 0 2006.285.11:45:04.14#ibcon#*before return 0, iclass 15, count 0 2006.285.11:45:04.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:45:04.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:45:04.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:45:04.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:45:04.14$vck44/va=8,3 2006.285.11:45:04.14#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.11:45:04.14#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.11:45:04.14#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:04.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:45:04.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:45:04.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:45:04.20#ibcon#enter wrdev, iclass 17, count 2 2006.285.11:45:04.20#ibcon#first serial, iclass 17, count 2 2006.285.11:45:04.20#ibcon#enter sib2, iclass 17, count 2 2006.285.11:45:04.20#ibcon#flushed, iclass 17, count 2 2006.285.11:45:04.20#ibcon#about to write, iclass 17, count 2 2006.285.11:45:04.20#ibcon#wrote, iclass 17, count 2 2006.285.11:45:04.20#ibcon#about to read 3, iclass 17, count 2 2006.285.11:45:04.22#ibcon#read 3, iclass 17, count 2 2006.285.11:45:04.22#ibcon#about to read 4, iclass 17, count 2 2006.285.11:45:04.22#ibcon#read 4, iclass 17, count 2 2006.285.11:45:04.22#ibcon#about to read 5, iclass 17, count 2 2006.285.11:45:04.22#ibcon#read 5, iclass 17, count 2 2006.285.11:45:04.22#ibcon#about to read 6, iclass 17, count 2 2006.285.11:45:04.22#ibcon#read 6, iclass 17, count 2 2006.285.11:45:04.22#ibcon#end of sib2, iclass 17, count 2 2006.285.11:45:04.22#ibcon#*mode == 0, iclass 17, count 2 2006.285.11:45:04.22#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.11:45:04.22#ibcon#[25=AT08-03\r\n] 2006.285.11:45:04.22#ibcon#*before write, iclass 17, count 2 2006.285.11:45:04.22#ibcon#enter sib2, iclass 17, count 2 2006.285.11:45:04.22#ibcon#flushed, iclass 17, count 2 2006.285.11:45:04.22#ibcon#about to write, iclass 17, count 2 2006.285.11:45:04.22#ibcon#wrote, iclass 17, count 2 2006.285.11:45:04.22#ibcon#about to read 3, iclass 17, count 2 2006.285.11:45:04.25#ibcon#read 3, iclass 17, count 2 2006.285.11:45:04.25#ibcon#about to read 4, iclass 17, count 2 2006.285.11:45:04.25#ibcon#read 4, iclass 17, count 2 2006.285.11:45:04.25#ibcon#about to read 5, iclass 17, count 2 2006.285.11:45:04.25#ibcon#read 5, iclass 17, count 2 2006.285.11:45:04.25#ibcon#about to read 6, iclass 17, count 2 2006.285.11:45:04.25#ibcon#read 6, iclass 17, count 2 2006.285.11:45:04.25#ibcon#end of sib2, iclass 17, count 2 2006.285.11:45:04.25#ibcon#*after write, iclass 17, count 2 2006.285.11:45:04.25#ibcon#*before return 0, iclass 17, count 2 2006.285.11:45:04.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:45:04.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:45:04.25#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.11:45:04.25#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:04.25#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:45:04.37#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:45:04.37#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:45:04.37#ibcon#enter wrdev, iclass 17, count 0 2006.285.11:45:04.37#ibcon#first serial, iclass 17, count 0 2006.285.11:45:04.37#ibcon#enter sib2, iclass 17, count 0 2006.285.11:45:04.37#ibcon#flushed, iclass 17, count 0 2006.285.11:45:04.37#ibcon#about to write, iclass 17, count 0 2006.285.11:45:04.37#ibcon#wrote, iclass 17, count 0 2006.285.11:45:04.37#ibcon#about to read 3, iclass 17, count 0 2006.285.11:45:04.39#ibcon#read 3, iclass 17, count 0 2006.285.11:45:04.39#ibcon#about to read 4, iclass 17, count 0 2006.285.11:45:04.39#ibcon#read 4, iclass 17, count 0 2006.285.11:45:04.39#ibcon#about to read 5, iclass 17, count 0 2006.285.11:45:04.39#ibcon#read 5, iclass 17, count 0 2006.285.11:45:04.39#ibcon#about to read 6, iclass 17, count 0 2006.285.11:45:04.39#ibcon#read 6, iclass 17, count 0 2006.285.11:45:04.39#ibcon#end of sib2, iclass 17, count 0 2006.285.11:45:04.39#ibcon#*mode == 0, iclass 17, count 0 2006.285.11:45:04.39#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.11:45:04.39#ibcon#[25=USB\r\n] 2006.285.11:45:04.39#ibcon#*before write, iclass 17, count 0 2006.285.11:45:04.39#ibcon#enter sib2, iclass 17, count 0 2006.285.11:45:04.39#ibcon#flushed, iclass 17, count 0 2006.285.11:45:04.39#ibcon#about to write, iclass 17, count 0 2006.285.11:45:04.39#ibcon#wrote, iclass 17, count 0 2006.285.11:45:04.39#ibcon#about to read 3, iclass 17, count 0 2006.285.11:45:04.42#ibcon#read 3, iclass 17, count 0 2006.285.11:45:04.42#ibcon#about to read 4, iclass 17, count 0 2006.285.11:45:04.42#ibcon#read 4, iclass 17, count 0 2006.285.11:45:04.42#ibcon#about to read 5, iclass 17, count 0 2006.285.11:45:04.42#ibcon#read 5, iclass 17, count 0 2006.285.11:45:04.42#ibcon#about to read 6, iclass 17, count 0 2006.285.11:45:04.42#ibcon#read 6, iclass 17, count 0 2006.285.11:45:04.42#ibcon#end of sib2, iclass 17, count 0 2006.285.11:45:04.42#ibcon#*after write, iclass 17, count 0 2006.285.11:45:04.42#ibcon#*before return 0, iclass 17, count 0 2006.285.11:45:04.42#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:45:04.42#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:45:04.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.11:45:04.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.11:45:04.42$vck44/vblo=1,629.99 2006.285.11:45:04.42#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.11:45:04.42#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.11:45:04.42#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:04.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:45:04.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:45:04.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:45:04.42#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:45:04.42#ibcon#first serial, iclass 19, count 0 2006.285.11:45:04.42#ibcon#enter sib2, iclass 19, count 0 2006.285.11:45:04.42#ibcon#flushed, iclass 19, count 0 2006.285.11:45:04.42#ibcon#about to write, iclass 19, count 0 2006.285.11:45:04.42#ibcon#wrote, iclass 19, count 0 2006.285.11:45:04.42#ibcon#about to read 3, iclass 19, count 0 2006.285.11:45:04.44#ibcon#read 3, iclass 19, count 0 2006.285.11:45:04.44#ibcon#about to read 4, iclass 19, count 0 2006.285.11:45:04.44#ibcon#read 4, iclass 19, count 0 2006.285.11:45:04.44#ibcon#about to read 5, iclass 19, count 0 2006.285.11:45:04.44#ibcon#read 5, iclass 19, count 0 2006.285.11:45:04.44#ibcon#about to read 6, iclass 19, count 0 2006.285.11:45:04.44#ibcon#read 6, iclass 19, count 0 2006.285.11:45:04.44#ibcon#end of sib2, iclass 19, count 0 2006.285.11:45:04.44#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:45:04.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:45:04.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:45:04.44#ibcon#*before write, iclass 19, count 0 2006.285.11:45:04.44#ibcon#enter sib2, iclass 19, count 0 2006.285.11:45:04.44#ibcon#flushed, iclass 19, count 0 2006.285.11:45:04.44#ibcon#about to write, iclass 19, count 0 2006.285.11:45:04.44#ibcon#wrote, iclass 19, count 0 2006.285.11:45:04.44#ibcon#about to read 3, iclass 19, count 0 2006.285.11:45:04.48#ibcon#read 3, iclass 19, count 0 2006.285.11:45:04.48#ibcon#about to read 4, iclass 19, count 0 2006.285.11:45:04.48#ibcon#read 4, iclass 19, count 0 2006.285.11:45:04.48#ibcon#about to read 5, iclass 19, count 0 2006.285.11:45:04.48#ibcon#read 5, iclass 19, count 0 2006.285.11:45:04.48#ibcon#about to read 6, iclass 19, count 0 2006.285.11:45:04.48#ibcon#read 6, iclass 19, count 0 2006.285.11:45:04.48#ibcon#end of sib2, iclass 19, count 0 2006.285.11:45:04.48#ibcon#*after write, iclass 19, count 0 2006.285.11:45:04.48#ibcon#*before return 0, iclass 19, count 0 2006.285.11:45:04.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:45:04.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:45:04.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:45:04.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:45:04.48$vck44/vb=1,4 2006.285.11:45:04.48#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.11:45:04.48#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.11:45:04.48#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:04.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:45:04.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:45:04.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:45:04.48#ibcon#enter wrdev, iclass 21, count 2 2006.285.11:45:04.48#ibcon#first serial, iclass 21, count 2 2006.285.11:45:04.48#ibcon#enter sib2, iclass 21, count 2 2006.285.11:45:04.48#ibcon#flushed, iclass 21, count 2 2006.285.11:45:04.48#ibcon#about to write, iclass 21, count 2 2006.285.11:45:04.48#ibcon#wrote, iclass 21, count 2 2006.285.11:45:04.48#ibcon#about to read 3, iclass 21, count 2 2006.285.11:45:04.50#ibcon#read 3, iclass 21, count 2 2006.285.11:45:04.50#ibcon#about to read 4, iclass 21, count 2 2006.285.11:45:04.50#ibcon#read 4, iclass 21, count 2 2006.285.11:45:04.50#ibcon#about to read 5, iclass 21, count 2 2006.285.11:45:04.50#ibcon#read 5, iclass 21, count 2 2006.285.11:45:04.50#ibcon#about to read 6, iclass 21, count 2 2006.285.11:45:04.50#ibcon#read 6, iclass 21, count 2 2006.285.11:45:04.50#ibcon#end of sib2, iclass 21, count 2 2006.285.11:45:04.50#ibcon#*mode == 0, iclass 21, count 2 2006.285.11:45:04.50#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.11:45:04.50#ibcon#[27=AT01-04\r\n] 2006.285.11:45:04.50#ibcon#*before write, iclass 21, count 2 2006.285.11:45:04.50#ibcon#enter sib2, iclass 21, count 2 2006.285.11:45:04.50#ibcon#flushed, iclass 21, count 2 2006.285.11:45:04.50#ibcon#about to write, iclass 21, count 2 2006.285.11:45:04.50#ibcon#wrote, iclass 21, count 2 2006.285.11:45:04.50#ibcon#about to read 3, iclass 21, count 2 2006.285.11:45:04.53#ibcon#read 3, iclass 21, count 2 2006.285.11:45:04.53#ibcon#about to read 4, iclass 21, count 2 2006.285.11:45:04.53#ibcon#read 4, iclass 21, count 2 2006.285.11:45:04.53#ibcon#about to read 5, iclass 21, count 2 2006.285.11:45:04.53#ibcon#read 5, iclass 21, count 2 2006.285.11:45:04.53#ibcon#about to read 6, iclass 21, count 2 2006.285.11:45:04.53#ibcon#read 6, iclass 21, count 2 2006.285.11:45:04.53#ibcon#end of sib2, iclass 21, count 2 2006.285.11:45:04.53#ibcon#*after write, iclass 21, count 2 2006.285.11:45:04.53#ibcon#*before return 0, iclass 21, count 2 2006.285.11:45:04.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:45:04.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.11:45:04.53#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.11:45:04.53#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:04.53#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:45:04.65#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:45:04.65#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:45:04.65#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:45:04.65#ibcon#first serial, iclass 21, count 0 2006.285.11:45:04.65#ibcon#enter sib2, iclass 21, count 0 2006.285.11:45:04.65#ibcon#flushed, iclass 21, count 0 2006.285.11:45:04.65#ibcon#about to write, iclass 21, count 0 2006.285.11:45:04.65#ibcon#wrote, iclass 21, count 0 2006.285.11:45:04.65#ibcon#about to read 3, iclass 21, count 0 2006.285.11:45:04.67#ibcon#read 3, iclass 21, count 0 2006.285.11:45:04.67#ibcon#about to read 4, iclass 21, count 0 2006.285.11:45:04.67#ibcon#read 4, iclass 21, count 0 2006.285.11:45:04.67#ibcon#about to read 5, iclass 21, count 0 2006.285.11:45:04.67#ibcon#read 5, iclass 21, count 0 2006.285.11:45:04.67#ibcon#about to read 6, iclass 21, count 0 2006.285.11:45:04.67#ibcon#read 6, iclass 21, count 0 2006.285.11:45:04.67#ibcon#end of sib2, iclass 21, count 0 2006.285.11:45:04.67#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:45:04.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:45:04.67#ibcon#[27=USB\r\n] 2006.285.11:45:04.67#ibcon#*before write, iclass 21, count 0 2006.285.11:45:04.67#ibcon#enter sib2, iclass 21, count 0 2006.285.11:45:04.67#ibcon#flushed, iclass 21, count 0 2006.285.11:45:04.67#ibcon#about to write, iclass 21, count 0 2006.285.11:45:04.67#ibcon#wrote, iclass 21, count 0 2006.285.11:45:04.67#ibcon#about to read 3, iclass 21, count 0 2006.285.11:45:04.70#ibcon#read 3, iclass 21, count 0 2006.285.11:45:04.70#ibcon#about to read 4, iclass 21, count 0 2006.285.11:45:04.70#ibcon#read 4, iclass 21, count 0 2006.285.11:45:04.70#ibcon#about to read 5, iclass 21, count 0 2006.285.11:45:04.70#ibcon#read 5, iclass 21, count 0 2006.285.11:45:04.70#ibcon#about to read 6, iclass 21, count 0 2006.285.11:45:04.70#ibcon#read 6, iclass 21, count 0 2006.285.11:45:04.70#ibcon#end of sib2, iclass 21, count 0 2006.285.11:45:04.70#ibcon#*after write, iclass 21, count 0 2006.285.11:45:04.70#ibcon#*before return 0, iclass 21, count 0 2006.285.11:45:04.70#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:45:04.70#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.11:45:04.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:45:04.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:45:04.70$vck44/vblo=2,634.99 2006.285.11:45:04.70#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.11:45:04.70#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.11:45:04.70#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:04.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:45:04.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:45:04.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:45:04.70#ibcon#enter wrdev, iclass 23, count 0 2006.285.11:45:04.70#ibcon#first serial, iclass 23, count 0 2006.285.11:45:04.70#ibcon#enter sib2, iclass 23, count 0 2006.285.11:45:04.70#ibcon#flushed, iclass 23, count 0 2006.285.11:45:04.70#ibcon#about to write, iclass 23, count 0 2006.285.11:45:04.70#ibcon#wrote, iclass 23, count 0 2006.285.11:45:04.70#ibcon#about to read 3, iclass 23, count 0 2006.285.11:45:04.72#ibcon#read 3, iclass 23, count 0 2006.285.11:45:04.72#ibcon#about to read 4, iclass 23, count 0 2006.285.11:45:04.72#ibcon#read 4, iclass 23, count 0 2006.285.11:45:04.72#ibcon#about to read 5, iclass 23, count 0 2006.285.11:45:04.72#ibcon#read 5, iclass 23, count 0 2006.285.11:45:04.72#ibcon#about to read 6, iclass 23, count 0 2006.285.11:45:04.72#ibcon#read 6, iclass 23, count 0 2006.285.11:45:04.72#ibcon#end of sib2, iclass 23, count 0 2006.285.11:45:04.72#ibcon#*mode == 0, iclass 23, count 0 2006.285.11:45:04.72#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.11:45:04.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:45:04.72#ibcon#*before write, iclass 23, count 0 2006.285.11:45:04.72#ibcon#enter sib2, iclass 23, count 0 2006.285.11:45:04.72#ibcon#flushed, iclass 23, count 0 2006.285.11:45:04.72#ibcon#about to write, iclass 23, count 0 2006.285.11:45:04.72#ibcon#wrote, iclass 23, count 0 2006.285.11:45:04.72#ibcon#about to read 3, iclass 23, count 0 2006.285.11:45:04.76#ibcon#read 3, iclass 23, count 0 2006.285.11:45:04.76#ibcon#about to read 4, iclass 23, count 0 2006.285.11:45:04.76#ibcon#read 4, iclass 23, count 0 2006.285.11:45:04.76#ibcon#about to read 5, iclass 23, count 0 2006.285.11:45:04.76#ibcon#read 5, iclass 23, count 0 2006.285.11:45:04.76#ibcon#about to read 6, iclass 23, count 0 2006.285.11:45:04.76#ibcon#read 6, iclass 23, count 0 2006.285.11:45:04.76#ibcon#end of sib2, iclass 23, count 0 2006.285.11:45:04.76#ibcon#*after write, iclass 23, count 0 2006.285.11:45:04.76#ibcon#*before return 0, iclass 23, count 0 2006.285.11:45:04.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:45:04.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.11:45:04.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.11:45:04.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.11:45:04.76$vck44/vb=2,5 2006.285.11:45:04.76#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.11:45:04.76#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.11:45:04.76#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:04.76#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:45:04.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:45:04.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:45:04.82#ibcon#enter wrdev, iclass 25, count 2 2006.285.11:45:04.82#ibcon#first serial, iclass 25, count 2 2006.285.11:45:04.82#ibcon#enter sib2, iclass 25, count 2 2006.285.11:45:04.82#ibcon#flushed, iclass 25, count 2 2006.285.11:45:04.82#ibcon#about to write, iclass 25, count 2 2006.285.11:45:04.82#ibcon#wrote, iclass 25, count 2 2006.285.11:45:04.82#ibcon#about to read 3, iclass 25, count 2 2006.285.11:45:04.84#ibcon#read 3, iclass 25, count 2 2006.285.11:45:04.84#ibcon#about to read 4, iclass 25, count 2 2006.285.11:45:04.84#ibcon#read 4, iclass 25, count 2 2006.285.11:45:04.84#ibcon#about to read 5, iclass 25, count 2 2006.285.11:45:04.84#ibcon#read 5, iclass 25, count 2 2006.285.11:45:04.84#ibcon#about to read 6, iclass 25, count 2 2006.285.11:45:04.84#ibcon#read 6, iclass 25, count 2 2006.285.11:45:04.84#ibcon#end of sib2, iclass 25, count 2 2006.285.11:45:04.84#ibcon#*mode == 0, iclass 25, count 2 2006.285.11:45:04.84#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.11:45:04.84#ibcon#[27=AT02-05\r\n] 2006.285.11:45:04.84#ibcon#*before write, iclass 25, count 2 2006.285.11:45:04.84#ibcon#enter sib2, iclass 25, count 2 2006.285.11:45:04.84#ibcon#flushed, iclass 25, count 2 2006.285.11:45:04.84#ibcon#about to write, iclass 25, count 2 2006.285.11:45:04.84#ibcon#wrote, iclass 25, count 2 2006.285.11:45:04.84#ibcon#about to read 3, iclass 25, count 2 2006.285.11:45:04.87#ibcon#read 3, iclass 25, count 2 2006.285.11:45:04.87#ibcon#about to read 4, iclass 25, count 2 2006.285.11:45:04.87#ibcon#read 4, iclass 25, count 2 2006.285.11:45:04.87#ibcon#about to read 5, iclass 25, count 2 2006.285.11:45:04.87#ibcon#read 5, iclass 25, count 2 2006.285.11:45:04.87#ibcon#about to read 6, iclass 25, count 2 2006.285.11:45:04.87#ibcon#read 6, iclass 25, count 2 2006.285.11:45:04.87#ibcon#end of sib2, iclass 25, count 2 2006.285.11:45:04.87#ibcon#*after write, iclass 25, count 2 2006.285.11:45:04.87#ibcon#*before return 0, iclass 25, count 2 2006.285.11:45:04.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:45:04.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.11:45:04.87#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.11:45:04.87#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:04.87#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:45:04.99#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:45:04.99#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:45:04.99#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:45:04.99#ibcon#first serial, iclass 25, count 0 2006.285.11:45:04.99#ibcon#enter sib2, iclass 25, count 0 2006.285.11:45:04.99#ibcon#flushed, iclass 25, count 0 2006.285.11:45:04.99#ibcon#about to write, iclass 25, count 0 2006.285.11:45:04.99#ibcon#wrote, iclass 25, count 0 2006.285.11:45:04.99#ibcon#about to read 3, iclass 25, count 0 2006.285.11:45:05.01#ibcon#read 3, iclass 25, count 0 2006.285.11:45:05.01#ibcon#about to read 4, iclass 25, count 0 2006.285.11:45:05.01#ibcon#read 4, iclass 25, count 0 2006.285.11:45:05.01#ibcon#about to read 5, iclass 25, count 0 2006.285.11:45:05.01#ibcon#read 5, iclass 25, count 0 2006.285.11:45:05.01#ibcon#about to read 6, iclass 25, count 0 2006.285.11:45:05.01#ibcon#read 6, iclass 25, count 0 2006.285.11:45:05.01#ibcon#end of sib2, iclass 25, count 0 2006.285.11:45:05.01#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:45:05.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:45:05.01#ibcon#[27=USB\r\n] 2006.285.11:45:05.01#ibcon#*before write, iclass 25, count 0 2006.285.11:45:05.01#ibcon#enter sib2, iclass 25, count 0 2006.285.11:45:05.01#ibcon#flushed, iclass 25, count 0 2006.285.11:45:05.01#ibcon#about to write, iclass 25, count 0 2006.285.11:45:05.01#ibcon#wrote, iclass 25, count 0 2006.285.11:45:05.01#ibcon#about to read 3, iclass 25, count 0 2006.285.11:45:05.04#ibcon#read 3, iclass 25, count 0 2006.285.11:45:05.04#ibcon#about to read 4, iclass 25, count 0 2006.285.11:45:05.04#ibcon#read 4, iclass 25, count 0 2006.285.11:45:05.04#ibcon#about to read 5, iclass 25, count 0 2006.285.11:45:05.04#ibcon#read 5, iclass 25, count 0 2006.285.11:45:05.04#ibcon#about to read 6, iclass 25, count 0 2006.285.11:45:05.04#ibcon#read 6, iclass 25, count 0 2006.285.11:45:05.04#ibcon#end of sib2, iclass 25, count 0 2006.285.11:45:05.04#ibcon#*after write, iclass 25, count 0 2006.285.11:45:05.04#ibcon#*before return 0, iclass 25, count 0 2006.285.11:45:05.04#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:45:05.04#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.11:45:05.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:45:05.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:45:05.04$vck44/vblo=3,649.99 2006.285.11:45:05.04#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.11:45:05.04#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.11:45:05.04#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:05.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:45:05.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:45:05.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:45:05.04#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:45:05.04#ibcon#first serial, iclass 27, count 0 2006.285.11:45:05.04#ibcon#enter sib2, iclass 27, count 0 2006.285.11:45:05.04#ibcon#flushed, iclass 27, count 0 2006.285.11:45:05.04#ibcon#about to write, iclass 27, count 0 2006.285.11:45:05.04#ibcon#wrote, iclass 27, count 0 2006.285.11:45:05.04#ibcon#about to read 3, iclass 27, count 0 2006.285.11:45:05.06#ibcon#read 3, iclass 27, count 0 2006.285.11:45:05.06#ibcon#about to read 4, iclass 27, count 0 2006.285.11:45:05.06#ibcon#read 4, iclass 27, count 0 2006.285.11:45:05.06#ibcon#about to read 5, iclass 27, count 0 2006.285.11:45:05.06#ibcon#read 5, iclass 27, count 0 2006.285.11:45:05.06#ibcon#about to read 6, iclass 27, count 0 2006.285.11:45:05.06#ibcon#read 6, iclass 27, count 0 2006.285.11:45:05.06#ibcon#end of sib2, iclass 27, count 0 2006.285.11:45:05.06#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:45:05.06#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:45:05.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:45:05.06#ibcon#*before write, iclass 27, count 0 2006.285.11:45:05.06#ibcon#enter sib2, iclass 27, count 0 2006.285.11:45:05.06#ibcon#flushed, iclass 27, count 0 2006.285.11:45:05.06#ibcon#about to write, iclass 27, count 0 2006.285.11:45:05.06#ibcon#wrote, iclass 27, count 0 2006.285.11:45:05.06#ibcon#about to read 3, iclass 27, count 0 2006.285.11:45:05.10#ibcon#read 3, iclass 27, count 0 2006.285.11:45:05.10#ibcon#about to read 4, iclass 27, count 0 2006.285.11:45:05.10#ibcon#read 4, iclass 27, count 0 2006.285.11:45:05.10#ibcon#about to read 5, iclass 27, count 0 2006.285.11:45:05.10#ibcon#read 5, iclass 27, count 0 2006.285.11:45:05.10#ibcon#about to read 6, iclass 27, count 0 2006.285.11:45:05.10#ibcon#read 6, iclass 27, count 0 2006.285.11:45:05.10#ibcon#end of sib2, iclass 27, count 0 2006.285.11:45:05.10#ibcon#*after write, iclass 27, count 0 2006.285.11:45:05.10#ibcon#*before return 0, iclass 27, count 0 2006.285.11:45:05.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:45:05.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.11:45:05.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:45:05.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:45:05.10$vck44/vb=3,4 2006.285.11:45:05.10#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.11:45:05.10#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.11:45:05.10#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:05.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:45:05.16#abcon#<5=/05 1.0 1.8 19.03 951015.3\r\n> 2006.285.11:45:05.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:45:05.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:45:05.16#ibcon#enter wrdev, iclass 29, count 2 2006.285.11:45:05.16#ibcon#first serial, iclass 29, count 2 2006.285.11:45:05.16#ibcon#enter sib2, iclass 29, count 2 2006.285.11:45:05.16#ibcon#flushed, iclass 29, count 2 2006.285.11:45:05.16#ibcon#about to write, iclass 29, count 2 2006.285.11:45:05.16#ibcon#wrote, iclass 29, count 2 2006.285.11:45:05.16#ibcon#about to read 3, iclass 29, count 2 2006.285.11:45:05.18#ibcon#read 3, iclass 29, count 2 2006.285.11:45:05.18#ibcon#about to read 4, iclass 29, count 2 2006.285.11:45:05.18#ibcon#read 4, iclass 29, count 2 2006.285.11:45:05.18#ibcon#about to read 5, iclass 29, count 2 2006.285.11:45:05.18#ibcon#read 5, iclass 29, count 2 2006.285.11:45:05.18#ibcon#about to read 6, iclass 29, count 2 2006.285.11:45:05.18#ibcon#read 6, iclass 29, count 2 2006.285.11:45:05.18#ibcon#end of sib2, iclass 29, count 2 2006.285.11:45:05.18#ibcon#*mode == 0, iclass 29, count 2 2006.285.11:45:05.18#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.11:45:05.18#ibcon#[27=AT03-04\r\n] 2006.285.11:45:05.18#ibcon#*before write, iclass 29, count 2 2006.285.11:45:05.18#ibcon#enter sib2, iclass 29, count 2 2006.285.11:45:05.18#ibcon#flushed, iclass 29, count 2 2006.285.11:45:05.18#ibcon#about to write, iclass 29, count 2 2006.285.11:45:05.18#ibcon#wrote, iclass 29, count 2 2006.285.11:45:05.18#ibcon#about to read 3, iclass 29, count 2 2006.285.11:45:05.18#abcon#{5=INTERFACE CLEAR} 2006.285.11:45:05.21#ibcon#read 3, iclass 29, count 2 2006.285.11:45:05.21#ibcon#about to read 4, iclass 29, count 2 2006.285.11:45:05.21#ibcon#read 4, iclass 29, count 2 2006.285.11:45:05.21#ibcon#about to read 5, iclass 29, count 2 2006.285.11:45:05.21#ibcon#read 5, iclass 29, count 2 2006.285.11:45:05.21#ibcon#about to read 6, iclass 29, count 2 2006.285.11:45:05.21#ibcon#read 6, iclass 29, count 2 2006.285.11:45:05.21#ibcon#end of sib2, iclass 29, count 2 2006.285.11:45:05.21#ibcon#*after write, iclass 29, count 2 2006.285.11:45:05.21#ibcon#*before return 0, iclass 29, count 2 2006.285.11:45:05.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:45:05.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.11:45:05.21#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.11:45:05.21#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:05.21#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:45:05.24#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:45:05.33#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:45:05.33#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:45:05.33#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:45:05.33#ibcon#first serial, iclass 29, count 0 2006.285.11:45:05.33#ibcon#enter sib2, iclass 29, count 0 2006.285.11:45:05.33#ibcon#flushed, iclass 29, count 0 2006.285.11:45:05.33#ibcon#about to write, iclass 29, count 0 2006.285.11:45:05.33#ibcon#wrote, iclass 29, count 0 2006.285.11:45:05.33#ibcon#about to read 3, iclass 29, count 0 2006.285.11:45:05.35#ibcon#read 3, iclass 29, count 0 2006.285.11:45:05.35#ibcon#about to read 4, iclass 29, count 0 2006.285.11:45:05.35#ibcon#read 4, iclass 29, count 0 2006.285.11:45:05.35#ibcon#about to read 5, iclass 29, count 0 2006.285.11:45:05.35#ibcon#read 5, iclass 29, count 0 2006.285.11:45:05.35#ibcon#about to read 6, iclass 29, count 0 2006.285.11:45:05.35#ibcon#read 6, iclass 29, count 0 2006.285.11:45:05.35#ibcon#end of sib2, iclass 29, count 0 2006.285.11:45:05.35#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:45:05.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:45:05.35#ibcon#[27=USB\r\n] 2006.285.11:45:05.35#ibcon#*before write, iclass 29, count 0 2006.285.11:45:05.35#ibcon#enter sib2, iclass 29, count 0 2006.285.11:45:05.35#ibcon#flushed, iclass 29, count 0 2006.285.11:45:05.35#ibcon#about to write, iclass 29, count 0 2006.285.11:45:05.35#ibcon#wrote, iclass 29, count 0 2006.285.11:45:05.35#ibcon#about to read 3, iclass 29, count 0 2006.285.11:45:05.38#ibcon#read 3, iclass 29, count 0 2006.285.11:45:05.38#ibcon#about to read 4, iclass 29, count 0 2006.285.11:45:05.38#ibcon#read 4, iclass 29, count 0 2006.285.11:45:05.38#ibcon#about to read 5, iclass 29, count 0 2006.285.11:45:05.38#ibcon#read 5, iclass 29, count 0 2006.285.11:45:05.38#ibcon#about to read 6, iclass 29, count 0 2006.285.11:45:05.38#ibcon#read 6, iclass 29, count 0 2006.285.11:45:05.38#ibcon#end of sib2, iclass 29, count 0 2006.285.11:45:05.38#ibcon#*after write, iclass 29, count 0 2006.285.11:45:05.38#ibcon#*before return 0, iclass 29, count 0 2006.285.11:45:05.38#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:45:05.38#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.11:45:05.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:45:05.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:45:05.38$vck44/vblo=4,679.99 2006.285.11:45:05.38#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.11:45:05.38#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.11:45:05.38#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:05.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:45:05.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:45:05.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:45:05.38#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:45:05.38#ibcon#first serial, iclass 35, count 0 2006.285.11:45:05.38#ibcon#enter sib2, iclass 35, count 0 2006.285.11:45:05.38#ibcon#flushed, iclass 35, count 0 2006.285.11:45:05.38#ibcon#about to write, iclass 35, count 0 2006.285.11:45:05.38#ibcon#wrote, iclass 35, count 0 2006.285.11:45:05.38#ibcon#about to read 3, iclass 35, count 0 2006.285.11:45:05.40#ibcon#read 3, iclass 35, count 0 2006.285.11:45:05.40#ibcon#about to read 4, iclass 35, count 0 2006.285.11:45:05.40#ibcon#read 4, iclass 35, count 0 2006.285.11:45:05.40#ibcon#about to read 5, iclass 35, count 0 2006.285.11:45:05.40#ibcon#read 5, iclass 35, count 0 2006.285.11:45:05.40#ibcon#about to read 6, iclass 35, count 0 2006.285.11:45:05.40#ibcon#read 6, iclass 35, count 0 2006.285.11:45:05.40#ibcon#end of sib2, iclass 35, count 0 2006.285.11:45:05.40#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:45:05.40#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:45:05.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:45:05.40#ibcon#*before write, iclass 35, count 0 2006.285.11:45:05.40#ibcon#enter sib2, iclass 35, count 0 2006.285.11:45:05.40#ibcon#flushed, iclass 35, count 0 2006.285.11:45:05.40#ibcon#about to write, iclass 35, count 0 2006.285.11:45:05.40#ibcon#wrote, iclass 35, count 0 2006.285.11:45:05.40#ibcon#about to read 3, iclass 35, count 0 2006.285.11:45:05.44#ibcon#read 3, iclass 35, count 0 2006.285.11:45:05.44#ibcon#about to read 4, iclass 35, count 0 2006.285.11:45:05.44#ibcon#read 4, iclass 35, count 0 2006.285.11:45:05.44#ibcon#about to read 5, iclass 35, count 0 2006.285.11:45:05.44#ibcon#read 5, iclass 35, count 0 2006.285.11:45:05.44#ibcon#about to read 6, iclass 35, count 0 2006.285.11:45:05.44#ibcon#read 6, iclass 35, count 0 2006.285.11:45:05.44#ibcon#end of sib2, iclass 35, count 0 2006.285.11:45:05.44#ibcon#*after write, iclass 35, count 0 2006.285.11:45:05.44#ibcon#*before return 0, iclass 35, count 0 2006.285.11:45:05.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:45:05.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.11:45:05.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:45:05.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:45:05.44$vck44/vb=4,5 2006.285.11:45:05.44#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.11:45:05.44#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.11:45:05.44#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:05.44#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:45:05.50#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:45:05.50#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:45:05.50#ibcon#enter wrdev, iclass 37, count 2 2006.285.11:45:05.50#ibcon#first serial, iclass 37, count 2 2006.285.11:45:05.50#ibcon#enter sib2, iclass 37, count 2 2006.285.11:45:05.50#ibcon#flushed, iclass 37, count 2 2006.285.11:45:05.50#ibcon#about to write, iclass 37, count 2 2006.285.11:45:05.50#ibcon#wrote, iclass 37, count 2 2006.285.11:45:05.50#ibcon#about to read 3, iclass 37, count 2 2006.285.11:45:05.52#ibcon#read 3, iclass 37, count 2 2006.285.11:45:05.52#ibcon#about to read 4, iclass 37, count 2 2006.285.11:45:05.52#ibcon#read 4, iclass 37, count 2 2006.285.11:45:05.52#ibcon#about to read 5, iclass 37, count 2 2006.285.11:45:05.52#ibcon#read 5, iclass 37, count 2 2006.285.11:45:05.52#ibcon#about to read 6, iclass 37, count 2 2006.285.11:45:05.52#ibcon#read 6, iclass 37, count 2 2006.285.11:45:05.52#ibcon#end of sib2, iclass 37, count 2 2006.285.11:45:05.52#ibcon#*mode == 0, iclass 37, count 2 2006.285.11:45:05.52#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.11:45:05.52#ibcon#[27=AT04-05\r\n] 2006.285.11:45:05.52#ibcon#*before write, iclass 37, count 2 2006.285.11:45:05.52#ibcon#enter sib2, iclass 37, count 2 2006.285.11:45:05.52#ibcon#flushed, iclass 37, count 2 2006.285.11:45:05.52#ibcon#about to write, iclass 37, count 2 2006.285.11:45:05.52#ibcon#wrote, iclass 37, count 2 2006.285.11:45:05.52#ibcon#about to read 3, iclass 37, count 2 2006.285.11:45:05.55#ibcon#read 3, iclass 37, count 2 2006.285.11:45:05.55#ibcon#about to read 4, iclass 37, count 2 2006.285.11:45:05.55#ibcon#read 4, iclass 37, count 2 2006.285.11:45:05.55#ibcon#about to read 5, iclass 37, count 2 2006.285.11:45:05.55#ibcon#read 5, iclass 37, count 2 2006.285.11:45:05.55#ibcon#about to read 6, iclass 37, count 2 2006.285.11:45:05.55#ibcon#read 6, iclass 37, count 2 2006.285.11:45:05.55#ibcon#end of sib2, iclass 37, count 2 2006.285.11:45:05.55#ibcon#*after write, iclass 37, count 2 2006.285.11:45:05.55#ibcon#*before return 0, iclass 37, count 2 2006.285.11:45:05.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:45:05.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.11:45:05.55#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.11:45:05.55#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:05.55#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:45:05.67#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:45:05.67#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:45:05.67#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:45:05.67#ibcon#first serial, iclass 37, count 0 2006.285.11:45:05.67#ibcon#enter sib2, iclass 37, count 0 2006.285.11:45:05.67#ibcon#flushed, iclass 37, count 0 2006.285.11:45:05.67#ibcon#about to write, iclass 37, count 0 2006.285.11:45:05.67#ibcon#wrote, iclass 37, count 0 2006.285.11:45:05.67#ibcon#about to read 3, iclass 37, count 0 2006.285.11:45:05.69#ibcon#read 3, iclass 37, count 0 2006.285.11:45:05.69#ibcon#about to read 4, iclass 37, count 0 2006.285.11:45:05.69#ibcon#read 4, iclass 37, count 0 2006.285.11:45:05.69#ibcon#about to read 5, iclass 37, count 0 2006.285.11:45:05.69#ibcon#read 5, iclass 37, count 0 2006.285.11:45:05.69#ibcon#about to read 6, iclass 37, count 0 2006.285.11:45:05.69#ibcon#read 6, iclass 37, count 0 2006.285.11:45:05.69#ibcon#end of sib2, iclass 37, count 0 2006.285.11:45:05.69#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:45:05.69#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:45:05.69#ibcon#[27=USB\r\n] 2006.285.11:45:05.69#ibcon#*before write, iclass 37, count 0 2006.285.11:45:05.69#ibcon#enter sib2, iclass 37, count 0 2006.285.11:45:05.69#ibcon#flushed, iclass 37, count 0 2006.285.11:45:05.69#ibcon#about to write, iclass 37, count 0 2006.285.11:45:05.69#ibcon#wrote, iclass 37, count 0 2006.285.11:45:05.69#ibcon#about to read 3, iclass 37, count 0 2006.285.11:45:05.72#ibcon#read 3, iclass 37, count 0 2006.285.11:45:05.72#ibcon#about to read 4, iclass 37, count 0 2006.285.11:45:05.72#ibcon#read 4, iclass 37, count 0 2006.285.11:45:05.72#ibcon#about to read 5, iclass 37, count 0 2006.285.11:45:05.72#ibcon#read 5, iclass 37, count 0 2006.285.11:45:05.72#ibcon#about to read 6, iclass 37, count 0 2006.285.11:45:05.72#ibcon#read 6, iclass 37, count 0 2006.285.11:45:05.72#ibcon#end of sib2, iclass 37, count 0 2006.285.11:45:05.72#ibcon#*after write, iclass 37, count 0 2006.285.11:45:05.72#ibcon#*before return 0, iclass 37, count 0 2006.285.11:45:05.72#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:45:05.72#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.11:45:05.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:45:05.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:45:05.72$vck44/vblo=5,709.99 2006.285.11:45:05.72#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.11:45:05.72#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.11:45:05.72#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:05.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:45:05.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:45:05.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:45:05.72#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:45:05.72#ibcon#first serial, iclass 39, count 0 2006.285.11:45:05.72#ibcon#enter sib2, iclass 39, count 0 2006.285.11:45:05.72#ibcon#flushed, iclass 39, count 0 2006.285.11:45:05.72#ibcon#about to write, iclass 39, count 0 2006.285.11:45:05.72#ibcon#wrote, iclass 39, count 0 2006.285.11:45:05.72#ibcon#about to read 3, iclass 39, count 0 2006.285.11:45:05.74#ibcon#read 3, iclass 39, count 0 2006.285.11:45:05.74#ibcon#about to read 4, iclass 39, count 0 2006.285.11:45:05.74#ibcon#read 4, iclass 39, count 0 2006.285.11:45:05.74#ibcon#about to read 5, iclass 39, count 0 2006.285.11:45:05.74#ibcon#read 5, iclass 39, count 0 2006.285.11:45:05.74#ibcon#about to read 6, iclass 39, count 0 2006.285.11:45:05.74#ibcon#read 6, iclass 39, count 0 2006.285.11:45:05.74#ibcon#end of sib2, iclass 39, count 0 2006.285.11:45:05.74#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:45:05.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:45:05.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:45:05.74#ibcon#*before write, iclass 39, count 0 2006.285.11:45:05.74#ibcon#enter sib2, iclass 39, count 0 2006.285.11:45:05.74#ibcon#flushed, iclass 39, count 0 2006.285.11:45:05.74#ibcon#about to write, iclass 39, count 0 2006.285.11:45:05.74#ibcon#wrote, iclass 39, count 0 2006.285.11:45:05.74#ibcon#about to read 3, iclass 39, count 0 2006.285.11:45:05.78#ibcon#read 3, iclass 39, count 0 2006.285.11:45:05.78#ibcon#about to read 4, iclass 39, count 0 2006.285.11:45:05.78#ibcon#read 4, iclass 39, count 0 2006.285.11:45:05.78#ibcon#about to read 5, iclass 39, count 0 2006.285.11:45:05.78#ibcon#read 5, iclass 39, count 0 2006.285.11:45:05.78#ibcon#about to read 6, iclass 39, count 0 2006.285.11:45:05.78#ibcon#read 6, iclass 39, count 0 2006.285.11:45:05.78#ibcon#end of sib2, iclass 39, count 0 2006.285.11:45:05.78#ibcon#*after write, iclass 39, count 0 2006.285.11:45:05.78#ibcon#*before return 0, iclass 39, count 0 2006.285.11:45:05.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:45:05.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.11:45:05.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:45:05.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:45:05.78$vck44/vb=5,4 2006.285.11:45:05.78#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.11:45:05.78#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.11:45:05.78#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:05.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:45:05.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:45:05.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:45:05.84#ibcon#enter wrdev, iclass 3, count 2 2006.285.11:45:05.84#ibcon#first serial, iclass 3, count 2 2006.285.11:45:05.84#ibcon#enter sib2, iclass 3, count 2 2006.285.11:45:05.84#ibcon#flushed, iclass 3, count 2 2006.285.11:45:05.84#ibcon#about to write, iclass 3, count 2 2006.285.11:45:05.84#ibcon#wrote, iclass 3, count 2 2006.285.11:45:05.84#ibcon#about to read 3, iclass 3, count 2 2006.285.11:45:05.86#ibcon#read 3, iclass 3, count 2 2006.285.11:45:05.86#ibcon#about to read 4, iclass 3, count 2 2006.285.11:45:05.86#ibcon#read 4, iclass 3, count 2 2006.285.11:45:05.86#ibcon#about to read 5, iclass 3, count 2 2006.285.11:45:05.86#ibcon#read 5, iclass 3, count 2 2006.285.11:45:05.86#ibcon#about to read 6, iclass 3, count 2 2006.285.11:45:05.86#ibcon#read 6, iclass 3, count 2 2006.285.11:45:05.86#ibcon#end of sib2, iclass 3, count 2 2006.285.11:45:05.86#ibcon#*mode == 0, iclass 3, count 2 2006.285.11:45:05.86#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.11:45:05.86#ibcon#[27=AT05-04\r\n] 2006.285.11:45:05.86#ibcon#*before write, iclass 3, count 2 2006.285.11:45:05.86#ibcon#enter sib2, iclass 3, count 2 2006.285.11:45:05.86#ibcon#flushed, iclass 3, count 2 2006.285.11:45:05.86#ibcon#about to write, iclass 3, count 2 2006.285.11:45:05.86#ibcon#wrote, iclass 3, count 2 2006.285.11:45:05.86#ibcon#about to read 3, iclass 3, count 2 2006.285.11:45:05.89#ibcon#read 3, iclass 3, count 2 2006.285.11:45:05.89#ibcon#about to read 4, iclass 3, count 2 2006.285.11:45:05.89#ibcon#read 4, iclass 3, count 2 2006.285.11:45:05.89#ibcon#about to read 5, iclass 3, count 2 2006.285.11:45:05.89#ibcon#read 5, iclass 3, count 2 2006.285.11:45:05.89#ibcon#about to read 6, iclass 3, count 2 2006.285.11:45:05.89#ibcon#read 6, iclass 3, count 2 2006.285.11:45:05.89#ibcon#end of sib2, iclass 3, count 2 2006.285.11:45:05.89#ibcon#*after write, iclass 3, count 2 2006.285.11:45:05.89#ibcon#*before return 0, iclass 3, count 2 2006.285.11:45:05.89#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:45:05.89#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.11:45:05.89#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.11:45:05.89#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:05.89#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:45:06.01#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:45:06.01#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:45:06.01#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:45:06.01#ibcon#first serial, iclass 3, count 0 2006.285.11:45:06.01#ibcon#enter sib2, iclass 3, count 0 2006.285.11:45:06.01#ibcon#flushed, iclass 3, count 0 2006.285.11:45:06.01#ibcon#about to write, iclass 3, count 0 2006.285.11:45:06.01#ibcon#wrote, iclass 3, count 0 2006.285.11:45:06.01#ibcon#about to read 3, iclass 3, count 0 2006.285.11:45:06.03#ibcon#read 3, iclass 3, count 0 2006.285.11:45:06.03#ibcon#about to read 4, iclass 3, count 0 2006.285.11:45:06.03#ibcon#read 4, iclass 3, count 0 2006.285.11:45:06.03#ibcon#about to read 5, iclass 3, count 0 2006.285.11:45:06.03#ibcon#read 5, iclass 3, count 0 2006.285.11:45:06.03#ibcon#about to read 6, iclass 3, count 0 2006.285.11:45:06.03#ibcon#read 6, iclass 3, count 0 2006.285.11:45:06.03#ibcon#end of sib2, iclass 3, count 0 2006.285.11:45:06.03#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:45:06.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:45:06.03#ibcon#[27=USB\r\n] 2006.285.11:45:06.03#ibcon#*before write, iclass 3, count 0 2006.285.11:45:06.03#ibcon#enter sib2, iclass 3, count 0 2006.285.11:45:06.03#ibcon#flushed, iclass 3, count 0 2006.285.11:45:06.03#ibcon#about to write, iclass 3, count 0 2006.285.11:45:06.03#ibcon#wrote, iclass 3, count 0 2006.285.11:45:06.03#ibcon#about to read 3, iclass 3, count 0 2006.285.11:45:06.06#ibcon#read 3, iclass 3, count 0 2006.285.11:45:06.06#ibcon#about to read 4, iclass 3, count 0 2006.285.11:45:06.06#ibcon#read 4, iclass 3, count 0 2006.285.11:45:06.06#ibcon#about to read 5, iclass 3, count 0 2006.285.11:45:06.06#ibcon#read 5, iclass 3, count 0 2006.285.11:45:06.06#ibcon#about to read 6, iclass 3, count 0 2006.285.11:45:06.06#ibcon#read 6, iclass 3, count 0 2006.285.11:45:06.06#ibcon#end of sib2, iclass 3, count 0 2006.285.11:45:06.06#ibcon#*after write, iclass 3, count 0 2006.285.11:45:06.06#ibcon#*before return 0, iclass 3, count 0 2006.285.11:45:06.06#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:45:06.06#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.11:45:06.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:45:06.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:45:06.06$vck44/vblo=6,719.99 2006.285.11:45:06.06#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.11:45:06.06#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.11:45:06.06#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:06.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:45:06.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:45:06.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:45:06.06#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:45:06.06#ibcon#first serial, iclass 5, count 0 2006.285.11:45:06.06#ibcon#enter sib2, iclass 5, count 0 2006.285.11:45:06.06#ibcon#flushed, iclass 5, count 0 2006.285.11:45:06.06#ibcon#about to write, iclass 5, count 0 2006.285.11:45:06.06#ibcon#wrote, iclass 5, count 0 2006.285.11:45:06.06#ibcon#about to read 3, iclass 5, count 0 2006.285.11:45:06.08#ibcon#read 3, iclass 5, count 0 2006.285.11:45:06.08#ibcon#about to read 4, iclass 5, count 0 2006.285.11:45:06.08#ibcon#read 4, iclass 5, count 0 2006.285.11:45:06.08#ibcon#about to read 5, iclass 5, count 0 2006.285.11:45:06.08#ibcon#read 5, iclass 5, count 0 2006.285.11:45:06.08#ibcon#about to read 6, iclass 5, count 0 2006.285.11:45:06.08#ibcon#read 6, iclass 5, count 0 2006.285.11:45:06.08#ibcon#end of sib2, iclass 5, count 0 2006.285.11:45:06.08#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:45:06.08#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:45:06.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:45:06.08#ibcon#*before write, iclass 5, count 0 2006.285.11:45:06.08#ibcon#enter sib2, iclass 5, count 0 2006.285.11:45:06.08#ibcon#flushed, iclass 5, count 0 2006.285.11:45:06.08#ibcon#about to write, iclass 5, count 0 2006.285.11:45:06.08#ibcon#wrote, iclass 5, count 0 2006.285.11:45:06.08#ibcon#about to read 3, iclass 5, count 0 2006.285.11:45:06.12#ibcon#read 3, iclass 5, count 0 2006.285.11:45:06.12#ibcon#about to read 4, iclass 5, count 0 2006.285.11:45:06.12#ibcon#read 4, iclass 5, count 0 2006.285.11:45:06.12#ibcon#about to read 5, iclass 5, count 0 2006.285.11:45:06.12#ibcon#read 5, iclass 5, count 0 2006.285.11:45:06.12#ibcon#about to read 6, iclass 5, count 0 2006.285.11:45:06.12#ibcon#read 6, iclass 5, count 0 2006.285.11:45:06.12#ibcon#end of sib2, iclass 5, count 0 2006.285.11:45:06.12#ibcon#*after write, iclass 5, count 0 2006.285.11:45:06.12#ibcon#*before return 0, iclass 5, count 0 2006.285.11:45:06.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:45:06.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.11:45:06.12#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:45:06.12#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:45:06.12$vck44/vb=6,3 2006.285.11:45:06.12#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.11:45:06.12#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.11:45:06.12#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:06.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:45:06.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:45:06.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:45:06.18#ibcon#enter wrdev, iclass 7, count 2 2006.285.11:45:06.18#ibcon#first serial, iclass 7, count 2 2006.285.11:45:06.18#ibcon#enter sib2, iclass 7, count 2 2006.285.11:45:06.18#ibcon#flushed, iclass 7, count 2 2006.285.11:45:06.18#ibcon#about to write, iclass 7, count 2 2006.285.11:45:06.18#ibcon#wrote, iclass 7, count 2 2006.285.11:45:06.18#ibcon#about to read 3, iclass 7, count 2 2006.285.11:45:06.20#ibcon#read 3, iclass 7, count 2 2006.285.11:45:06.20#ibcon#about to read 4, iclass 7, count 2 2006.285.11:45:06.20#ibcon#read 4, iclass 7, count 2 2006.285.11:45:06.20#ibcon#about to read 5, iclass 7, count 2 2006.285.11:45:06.20#ibcon#read 5, iclass 7, count 2 2006.285.11:45:06.20#ibcon#about to read 6, iclass 7, count 2 2006.285.11:45:06.20#ibcon#read 6, iclass 7, count 2 2006.285.11:45:06.20#ibcon#end of sib2, iclass 7, count 2 2006.285.11:45:06.20#ibcon#*mode == 0, iclass 7, count 2 2006.285.11:45:06.20#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.11:45:06.20#ibcon#[27=AT06-03\r\n] 2006.285.11:45:06.20#ibcon#*before write, iclass 7, count 2 2006.285.11:45:06.20#ibcon#enter sib2, iclass 7, count 2 2006.285.11:45:06.20#ibcon#flushed, iclass 7, count 2 2006.285.11:45:06.20#ibcon#about to write, iclass 7, count 2 2006.285.11:45:06.20#ibcon#wrote, iclass 7, count 2 2006.285.11:45:06.20#ibcon#about to read 3, iclass 7, count 2 2006.285.11:45:06.23#ibcon#read 3, iclass 7, count 2 2006.285.11:45:06.23#ibcon#about to read 4, iclass 7, count 2 2006.285.11:45:06.23#ibcon#read 4, iclass 7, count 2 2006.285.11:45:06.23#ibcon#about to read 5, iclass 7, count 2 2006.285.11:45:06.23#ibcon#read 5, iclass 7, count 2 2006.285.11:45:06.23#ibcon#about to read 6, iclass 7, count 2 2006.285.11:45:06.23#ibcon#read 6, iclass 7, count 2 2006.285.11:45:06.23#ibcon#end of sib2, iclass 7, count 2 2006.285.11:45:06.23#ibcon#*after write, iclass 7, count 2 2006.285.11:45:06.23#ibcon#*before return 0, iclass 7, count 2 2006.285.11:45:06.23#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:45:06.23#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.11:45:06.23#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.11:45:06.23#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:06.23#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:45:06.35#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:45:06.35#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:45:06.35#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:45:06.35#ibcon#first serial, iclass 7, count 0 2006.285.11:45:06.35#ibcon#enter sib2, iclass 7, count 0 2006.285.11:45:06.35#ibcon#flushed, iclass 7, count 0 2006.285.11:45:06.35#ibcon#about to write, iclass 7, count 0 2006.285.11:45:06.35#ibcon#wrote, iclass 7, count 0 2006.285.11:45:06.35#ibcon#about to read 3, iclass 7, count 0 2006.285.11:45:06.37#ibcon#read 3, iclass 7, count 0 2006.285.11:45:06.37#ibcon#about to read 4, iclass 7, count 0 2006.285.11:45:06.37#ibcon#read 4, iclass 7, count 0 2006.285.11:45:06.37#ibcon#about to read 5, iclass 7, count 0 2006.285.11:45:06.37#ibcon#read 5, iclass 7, count 0 2006.285.11:45:06.37#ibcon#about to read 6, iclass 7, count 0 2006.285.11:45:06.37#ibcon#read 6, iclass 7, count 0 2006.285.11:45:06.37#ibcon#end of sib2, iclass 7, count 0 2006.285.11:45:06.37#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:45:06.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:45:06.37#ibcon#[27=USB\r\n] 2006.285.11:45:06.37#ibcon#*before write, iclass 7, count 0 2006.285.11:45:06.37#ibcon#enter sib2, iclass 7, count 0 2006.285.11:45:06.37#ibcon#flushed, iclass 7, count 0 2006.285.11:45:06.37#ibcon#about to write, iclass 7, count 0 2006.285.11:45:06.37#ibcon#wrote, iclass 7, count 0 2006.285.11:45:06.37#ibcon#about to read 3, iclass 7, count 0 2006.285.11:45:06.40#ibcon#read 3, iclass 7, count 0 2006.285.11:45:06.40#ibcon#about to read 4, iclass 7, count 0 2006.285.11:45:06.40#ibcon#read 4, iclass 7, count 0 2006.285.11:45:06.40#ibcon#about to read 5, iclass 7, count 0 2006.285.11:45:06.40#ibcon#read 5, iclass 7, count 0 2006.285.11:45:06.40#ibcon#about to read 6, iclass 7, count 0 2006.285.11:45:06.40#ibcon#read 6, iclass 7, count 0 2006.285.11:45:06.40#ibcon#end of sib2, iclass 7, count 0 2006.285.11:45:06.40#ibcon#*after write, iclass 7, count 0 2006.285.11:45:06.40#ibcon#*before return 0, iclass 7, count 0 2006.285.11:45:06.40#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:45:06.40#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.11:45:06.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:45:06.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:45:06.40$vck44/vblo=7,734.99 2006.285.11:45:06.40#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.11:45:06.40#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.11:45:06.40#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:06.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:45:06.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:45:06.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:45:06.40#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:45:06.40#ibcon#first serial, iclass 11, count 0 2006.285.11:45:06.40#ibcon#enter sib2, iclass 11, count 0 2006.285.11:45:06.40#ibcon#flushed, iclass 11, count 0 2006.285.11:45:06.40#ibcon#about to write, iclass 11, count 0 2006.285.11:45:06.40#ibcon#wrote, iclass 11, count 0 2006.285.11:45:06.40#ibcon#about to read 3, iclass 11, count 0 2006.285.11:45:06.42#ibcon#read 3, iclass 11, count 0 2006.285.11:45:06.42#ibcon#about to read 4, iclass 11, count 0 2006.285.11:45:06.42#ibcon#read 4, iclass 11, count 0 2006.285.11:45:06.42#ibcon#about to read 5, iclass 11, count 0 2006.285.11:45:06.42#ibcon#read 5, iclass 11, count 0 2006.285.11:45:06.42#ibcon#about to read 6, iclass 11, count 0 2006.285.11:45:06.42#ibcon#read 6, iclass 11, count 0 2006.285.11:45:06.42#ibcon#end of sib2, iclass 11, count 0 2006.285.11:45:06.42#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:45:06.42#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:45:06.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:45:06.42#ibcon#*before write, iclass 11, count 0 2006.285.11:45:06.42#ibcon#enter sib2, iclass 11, count 0 2006.285.11:45:06.42#ibcon#flushed, iclass 11, count 0 2006.285.11:45:06.42#ibcon#about to write, iclass 11, count 0 2006.285.11:45:06.42#ibcon#wrote, iclass 11, count 0 2006.285.11:45:06.42#ibcon#about to read 3, iclass 11, count 0 2006.285.11:45:06.46#ibcon#read 3, iclass 11, count 0 2006.285.11:45:06.46#ibcon#about to read 4, iclass 11, count 0 2006.285.11:45:06.46#ibcon#read 4, iclass 11, count 0 2006.285.11:45:06.46#ibcon#about to read 5, iclass 11, count 0 2006.285.11:45:06.46#ibcon#read 5, iclass 11, count 0 2006.285.11:45:06.46#ibcon#about to read 6, iclass 11, count 0 2006.285.11:45:06.46#ibcon#read 6, iclass 11, count 0 2006.285.11:45:06.46#ibcon#end of sib2, iclass 11, count 0 2006.285.11:45:06.46#ibcon#*after write, iclass 11, count 0 2006.285.11:45:06.46#ibcon#*before return 0, iclass 11, count 0 2006.285.11:45:06.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:45:06.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.11:45:06.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:45:06.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:45:06.46$vck44/vb=7,4 2006.285.11:45:06.46#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.11:45:06.46#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.11:45:06.46#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:06.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:45:06.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:45:06.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:45:06.52#ibcon#enter wrdev, iclass 13, count 2 2006.285.11:45:06.52#ibcon#first serial, iclass 13, count 2 2006.285.11:45:06.52#ibcon#enter sib2, iclass 13, count 2 2006.285.11:45:06.52#ibcon#flushed, iclass 13, count 2 2006.285.11:45:06.52#ibcon#about to write, iclass 13, count 2 2006.285.11:45:06.52#ibcon#wrote, iclass 13, count 2 2006.285.11:45:06.52#ibcon#about to read 3, iclass 13, count 2 2006.285.11:45:06.54#ibcon#read 3, iclass 13, count 2 2006.285.11:45:06.54#ibcon#about to read 4, iclass 13, count 2 2006.285.11:45:06.54#ibcon#read 4, iclass 13, count 2 2006.285.11:45:06.54#ibcon#about to read 5, iclass 13, count 2 2006.285.11:45:06.54#ibcon#read 5, iclass 13, count 2 2006.285.11:45:06.54#ibcon#about to read 6, iclass 13, count 2 2006.285.11:45:06.54#ibcon#read 6, iclass 13, count 2 2006.285.11:45:06.54#ibcon#end of sib2, iclass 13, count 2 2006.285.11:45:06.54#ibcon#*mode == 0, iclass 13, count 2 2006.285.11:45:06.54#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.11:45:06.54#ibcon#[27=AT07-04\r\n] 2006.285.11:45:06.54#ibcon#*before write, iclass 13, count 2 2006.285.11:45:06.54#ibcon#enter sib2, iclass 13, count 2 2006.285.11:45:06.54#ibcon#flushed, iclass 13, count 2 2006.285.11:45:06.54#ibcon#about to write, iclass 13, count 2 2006.285.11:45:06.54#ibcon#wrote, iclass 13, count 2 2006.285.11:45:06.54#ibcon#about to read 3, iclass 13, count 2 2006.285.11:45:06.57#ibcon#read 3, iclass 13, count 2 2006.285.11:45:06.57#ibcon#about to read 4, iclass 13, count 2 2006.285.11:45:06.57#ibcon#read 4, iclass 13, count 2 2006.285.11:45:06.57#ibcon#about to read 5, iclass 13, count 2 2006.285.11:45:06.57#ibcon#read 5, iclass 13, count 2 2006.285.11:45:06.57#ibcon#about to read 6, iclass 13, count 2 2006.285.11:45:06.57#ibcon#read 6, iclass 13, count 2 2006.285.11:45:06.57#ibcon#end of sib2, iclass 13, count 2 2006.285.11:45:06.57#ibcon#*after write, iclass 13, count 2 2006.285.11:45:06.57#ibcon#*before return 0, iclass 13, count 2 2006.285.11:45:06.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:45:06.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.11:45:06.57#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.11:45:06.57#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:06.57#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:45:06.69#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:45:06.69#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:45:06.69#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:45:06.69#ibcon#first serial, iclass 13, count 0 2006.285.11:45:06.69#ibcon#enter sib2, iclass 13, count 0 2006.285.11:45:06.69#ibcon#flushed, iclass 13, count 0 2006.285.11:45:06.69#ibcon#about to write, iclass 13, count 0 2006.285.11:45:06.69#ibcon#wrote, iclass 13, count 0 2006.285.11:45:06.69#ibcon#about to read 3, iclass 13, count 0 2006.285.11:45:06.71#ibcon#read 3, iclass 13, count 0 2006.285.11:45:06.71#ibcon#about to read 4, iclass 13, count 0 2006.285.11:45:06.71#ibcon#read 4, iclass 13, count 0 2006.285.11:45:06.71#ibcon#about to read 5, iclass 13, count 0 2006.285.11:45:06.71#ibcon#read 5, iclass 13, count 0 2006.285.11:45:06.71#ibcon#about to read 6, iclass 13, count 0 2006.285.11:45:06.71#ibcon#read 6, iclass 13, count 0 2006.285.11:45:06.71#ibcon#end of sib2, iclass 13, count 0 2006.285.11:45:06.71#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:45:06.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:45:06.71#ibcon#[27=USB\r\n] 2006.285.11:45:06.71#ibcon#*before write, iclass 13, count 0 2006.285.11:45:06.71#ibcon#enter sib2, iclass 13, count 0 2006.285.11:45:06.71#ibcon#flushed, iclass 13, count 0 2006.285.11:45:06.71#ibcon#about to write, iclass 13, count 0 2006.285.11:45:06.71#ibcon#wrote, iclass 13, count 0 2006.285.11:45:06.71#ibcon#about to read 3, iclass 13, count 0 2006.285.11:45:06.74#ibcon#read 3, iclass 13, count 0 2006.285.11:45:06.74#ibcon#about to read 4, iclass 13, count 0 2006.285.11:45:06.74#ibcon#read 4, iclass 13, count 0 2006.285.11:45:06.74#ibcon#about to read 5, iclass 13, count 0 2006.285.11:45:06.74#ibcon#read 5, iclass 13, count 0 2006.285.11:45:06.74#ibcon#about to read 6, iclass 13, count 0 2006.285.11:45:06.74#ibcon#read 6, iclass 13, count 0 2006.285.11:45:06.74#ibcon#end of sib2, iclass 13, count 0 2006.285.11:45:06.74#ibcon#*after write, iclass 13, count 0 2006.285.11:45:06.74#ibcon#*before return 0, iclass 13, count 0 2006.285.11:45:06.74#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:45:06.74#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.11:45:06.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:45:06.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:45:06.74$vck44/vblo=8,744.99 2006.285.11:45:06.74#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.11:45:06.74#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.11:45:06.74#ibcon#ireg 17 cls_cnt 0 2006.285.11:45:06.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:45:06.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:45:06.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:45:06.74#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:45:06.74#ibcon#first serial, iclass 15, count 0 2006.285.11:45:06.74#ibcon#enter sib2, iclass 15, count 0 2006.285.11:45:06.74#ibcon#flushed, iclass 15, count 0 2006.285.11:45:06.74#ibcon#about to write, iclass 15, count 0 2006.285.11:45:06.74#ibcon#wrote, iclass 15, count 0 2006.285.11:45:06.74#ibcon#about to read 3, iclass 15, count 0 2006.285.11:45:06.76#ibcon#read 3, iclass 15, count 0 2006.285.11:45:06.76#ibcon#about to read 4, iclass 15, count 0 2006.285.11:45:06.76#ibcon#read 4, iclass 15, count 0 2006.285.11:45:06.76#ibcon#about to read 5, iclass 15, count 0 2006.285.11:45:06.76#ibcon#read 5, iclass 15, count 0 2006.285.11:45:06.76#ibcon#about to read 6, iclass 15, count 0 2006.285.11:45:06.76#ibcon#read 6, iclass 15, count 0 2006.285.11:45:06.76#ibcon#end of sib2, iclass 15, count 0 2006.285.11:45:06.76#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:45:06.76#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:45:06.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:45:06.76#ibcon#*before write, iclass 15, count 0 2006.285.11:45:06.76#ibcon#enter sib2, iclass 15, count 0 2006.285.11:45:06.76#ibcon#flushed, iclass 15, count 0 2006.285.11:45:06.76#ibcon#about to write, iclass 15, count 0 2006.285.11:45:06.76#ibcon#wrote, iclass 15, count 0 2006.285.11:45:06.76#ibcon#about to read 3, iclass 15, count 0 2006.285.11:45:06.80#ibcon#read 3, iclass 15, count 0 2006.285.11:45:06.80#ibcon#about to read 4, iclass 15, count 0 2006.285.11:45:06.80#ibcon#read 4, iclass 15, count 0 2006.285.11:45:06.80#ibcon#about to read 5, iclass 15, count 0 2006.285.11:45:06.80#ibcon#read 5, iclass 15, count 0 2006.285.11:45:06.80#ibcon#about to read 6, iclass 15, count 0 2006.285.11:45:06.80#ibcon#read 6, iclass 15, count 0 2006.285.11:45:06.80#ibcon#end of sib2, iclass 15, count 0 2006.285.11:45:06.80#ibcon#*after write, iclass 15, count 0 2006.285.11:45:06.80#ibcon#*before return 0, iclass 15, count 0 2006.285.11:45:06.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:45:06.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:45:06.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:45:06.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:45:06.80$vck44/vb=8,4 2006.285.11:45:06.80#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.11:45:06.80#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.11:45:06.80#ibcon#ireg 11 cls_cnt 2 2006.285.11:45:06.80#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:45:06.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:45:06.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:45:06.86#ibcon#enter wrdev, iclass 17, count 2 2006.285.11:45:06.86#ibcon#first serial, iclass 17, count 2 2006.285.11:45:06.86#ibcon#enter sib2, iclass 17, count 2 2006.285.11:45:06.86#ibcon#flushed, iclass 17, count 2 2006.285.11:45:06.86#ibcon#about to write, iclass 17, count 2 2006.285.11:45:06.86#ibcon#wrote, iclass 17, count 2 2006.285.11:45:06.86#ibcon#about to read 3, iclass 17, count 2 2006.285.11:45:06.88#ibcon#read 3, iclass 17, count 2 2006.285.11:45:06.88#ibcon#about to read 4, iclass 17, count 2 2006.285.11:45:06.88#ibcon#read 4, iclass 17, count 2 2006.285.11:45:06.88#ibcon#about to read 5, iclass 17, count 2 2006.285.11:45:06.88#ibcon#read 5, iclass 17, count 2 2006.285.11:45:06.88#ibcon#about to read 6, iclass 17, count 2 2006.285.11:45:06.88#ibcon#read 6, iclass 17, count 2 2006.285.11:45:06.88#ibcon#end of sib2, iclass 17, count 2 2006.285.11:45:06.88#ibcon#*mode == 0, iclass 17, count 2 2006.285.11:45:06.88#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.11:45:06.88#ibcon#[27=AT08-04\r\n] 2006.285.11:45:06.88#ibcon#*before write, iclass 17, count 2 2006.285.11:45:06.88#ibcon#enter sib2, iclass 17, count 2 2006.285.11:45:06.88#ibcon#flushed, iclass 17, count 2 2006.285.11:45:06.88#ibcon#about to write, iclass 17, count 2 2006.285.11:45:06.88#ibcon#wrote, iclass 17, count 2 2006.285.11:45:06.88#ibcon#about to read 3, iclass 17, count 2 2006.285.11:45:06.91#ibcon#read 3, iclass 17, count 2 2006.285.11:45:06.91#ibcon#about to read 4, iclass 17, count 2 2006.285.11:45:06.91#ibcon#read 4, iclass 17, count 2 2006.285.11:45:06.91#ibcon#about to read 5, iclass 17, count 2 2006.285.11:45:06.91#ibcon#read 5, iclass 17, count 2 2006.285.11:45:06.91#ibcon#about to read 6, iclass 17, count 2 2006.285.11:45:06.91#ibcon#read 6, iclass 17, count 2 2006.285.11:45:06.91#ibcon#end of sib2, iclass 17, count 2 2006.285.11:45:06.91#ibcon#*after write, iclass 17, count 2 2006.285.11:45:06.91#ibcon#*before return 0, iclass 17, count 2 2006.285.11:45:06.91#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:45:06.91#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.11:45:06.91#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.11:45:06.91#ibcon#ireg 7 cls_cnt 0 2006.285.11:45:06.91#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:45:07.03#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:45:07.03#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:45:07.03#ibcon#enter wrdev, iclass 17, count 0 2006.285.11:45:07.03#ibcon#first serial, iclass 17, count 0 2006.285.11:45:07.03#ibcon#enter sib2, iclass 17, count 0 2006.285.11:45:07.03#ibcon#flushed, iclass 17, count 0 2006.285.11:45:07.03#ibcon#about to write, iclass 17, count 0 2006.285.11:45:07.03#ibcon#wrote, iclass 17, count 0 2006.285.11:45:07.03#ibcon#about to read 3, iclass 17, count 0 2006.285.11:45:07.05#ibcon#read 3, iclass 17, count 0 2006.285.11:45:07.05#ibcon#about to read 4, iclass 17, count 0 2006.285.11:45:07.05#ibcon#read 4, iclass 17, count 0 2006.285.11:45:07.05#ibcon#about to read 5, iclass 17, count 0 2006.285.11:45:07.05#ibcon#read 5, iclass 17, count 0 2006.285.11:45:07.05#ibcon#about to read 6, iclass 17, count 0 2006.285.11:45:07.05#ibcon#read 6, iclass 17, count 0 2006.285.11:45:07.05#ibcon#end of sib2, iclass 17, count 0 2006.285.11:45:07.05#ibcon#*mode == 0, iclass 17, count 0 2006.285.11:45:07.05#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.11:45:07.05#ibcon#[27=USB\r\n] 2006.285.11:45:07.05#ibcon#*before write, iclass 17, count 0 2006.285.11:45:07.05#ibcon#enter sib2, iclass 17, count 0 2006.285.11:45:07.05#ibcon#flushed, iclass 17, count 0 2006.285.11:45:07.05#ibcon#about to write, iclass 17, count 0 2006.285.11:45:07.05#ibcon#wrote, iclass 17, count 0 2006.285.11:45:07.05#ibcon#about to read 3, iclass 17, count 0 2006.285.11:45:07.08#ibcon#read 3, iclass 17, count 0 2006.285.11:45:07.08#ibcon#about to read 4, iclass 17, count 0 2006.285.11:45:07.08#ibcon#read 4, iclass 17, count 0 2006.285.11:45:07.08#ibcon#about to read 5, iclass 17, count 0 2006.285.11:45:07.08#ibcon#read 5, iclass 17, count 0 2006.285.11:45:07.08#ibcon#about to read 6, iclass 17, count 0 2006.285.11:45:07.08#ibcon#read 6, iclass 17, count 0 2006.285.11:45:07.08#ibcon#end of sib2, iclass 17, count 0 2006.285.11:45:07.08#ibcon#*after write, iclass 17, count 0 2006.285.11:45:07.08#ibcon#*before return 0, iclass 17, count 0 2006.285.11:45:07.08#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:45:07.08#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.11:45:07.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.11:45:07.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.11:45:07.08$vck44/vabw=wide 2006.285.11:45:07.08#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.11:45:07.08#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.11:45:07.08#ibcon#ireg 8 cls_cnt 0 2006.285.11:45:07.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:45:07.08#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:45:07.08#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:45:07.08#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:45:07.08#ibcon#first serial, iclass 19, count 0 2006.285.11:45:07.08#ibcon#enter sib2, iclass 19, count 0 2006.285.11:45:07.08#ibcon#flushed, iclass 19, count 0 2006.285.11:45:07.08#ibcon#about to write, iclass 19, count 0 2006.285.11:45:07.08#ibcon#wrote, iclass 19, count 0 2006.285.11:45:07.08#ibcon#about to read 3, iclass 19, count 0 2006.285.11:45:07.10#ibcon#read 3, iclass 19, count 0 2006.285.11:45:07.10#ibcon#about to read 4, iclass 19, count 0 2006.285.11:45:07.10#ibcon#read 4, iclass 19, count 0 2006.285.11:45:07.10#ibcon#about to read 5, iclass 19, count 0 2006.285.11:45:07.10#ibcon#read 5, iclass 19, count 0 2006.285.11:45:07.10#ibcon#about to read 6, iclass 19, count 0 2006.285.11:45:07.10#ibcon#read 6, iclass 19, count 0 2006.285.11:45:07.10#ibcon#end of sib2, iclass 19, count 0 2006.285.11:45:07.10#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:45:07.10#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:45:07.10#ibcon#[25=BW32\r\n] 2006.285.11:45:07.10#ibcon#*before write, iclass 19, count 0 2006.285.11:45:07.10#ibcon#enter sib2, iclass 19, count 0 2006.285.11:45:07.10#ibcon#flushed, iclass 19, count 0 2006.285.11:45:07.10#ibcon#about to write, iclass 19, count 0 2006.285.11:45:07.10#ibcon#wrote, iclass 19, count 0 2006.285.11:45:07.10#ibcon#about to read 3, iclass 19, count 0 2006.285.11:45:07.13#ibcon#read 3, iclass 19, count 0 2006.285.11:45:07.13#ibcon#about to read 4, iclass 19, count 0 2006.285.11:45:07.13#ibcon#read 4, iclass 19, count 0 2006.285.11:45:07.13#ibcon#about to read 5, iclass 19, count 0 2006.285.11:45:07.13#ibcon#read 5, iclass 19, count 0 2006.285.11:45:07.13#ibcon#about to read 6, iclass 19, count 0 2006.285.11:45:07.13#ibcon#read 6, iclass 19, count 0 2006.285.11:45:07.13#ibcon#end of sib2, iclass 19, count 0 2006.285.11:45:07.13#ibcon#*after write, iclass 19, count 0 2006.285.11:45:07.13#ibcon#*before return 0, iclass 19, count 0 2006.285.11:45:07.13#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:45:07.13#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.11:45:07.13#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:45:07.13#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:45:07.13$vck44/vbbw=wide 2006.285.11:45:07.13#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.11:45:07.13#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.11:45:07.13#ibcon#ireg 8 cls_cnt 0 2006.285.11:45:07.13#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:45:07.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:45:07.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:45:07.20#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:45:07.20#ibcon#first serial, iclass 21, count 0 2006.285.11:45:07.20#ibcon#enter sib2, iclass 21, count 0 2006.285.11:45:07.20#ibcon#flushed, iclass 21, count 0 2006.285.11:45:07.20#ibcon#about to write, iclass 21, count 0 2006.285.11:45:07.20#ibcon#wrote, iclass 21, count 0 2006.285.11:45:07.20#ibcon#about to read 3, iclass 21, count 0 2006.285.11:45:07.22#ibcon#read 3, iclass 21, count 0 2006.285.11:45:07.22#ibcon#about to read 4, iclass 21, count 0 2006.285.11:45:07.22#ibcon#read 4, iclass 21, count 0 2006.285.11:45:07.22#ibcon#about to read 5, iclass 21, count 0 2006.285.11:45:07.22#ibcon#read 5, iclass 21, count 0 2006.285.11:45:07.22#ibcon#about to read 6, iclass 21, count 0 2006.285.11:45:07.22#ibcon#read 6, iclass 21, count 0 2006.285.11:45:07.22#ibcon#end of sib2, iclass 21, count 0 2006.285.11:45:07.22#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:45:07.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:45:07.22#ibcon#[27=BW32\r\n] 2006.285.11:45:07.22#ibcon#*before write, iclass 21, count 0 2006.285.11:45:07.22#ibcon#enter sib2, iclass 21, count 0 2006.285.11:45:07.22#ibcon#flushed, iclass 21, count 0 2006.285.11:45:07.22#ibcon#about to write, iclass 21, count 0 2006.285.11:45:07.22#ibcon#wrote, iclass 21, count 0 2006.285.11:45:07.22#ibcon#about to read 3, iclass 21, count 0 2006.285.11:45:07.25#ibcon#read 3, iclass 21, count 0 2006.285.11:45:07.25#ibcon#about to read 4, iclass 21, count 0 2006.285.11:45:07.25#ibcon#read 4, iclass 21, count 0 2006.285.11:45:07.25#ibcon#about to read 5, iclass 21, count 0 2006.285.11:45:07.25#ibcon#read 5, iclass 21, count 0 2006.285.11:45:07.25#ibcon#about to read 6, iclass 21, count 0 2006.285.11:45:07.25#ibcon#read 6, iclass 21, count 0 2006.285.11:45:07.25#ibcon#end of sib2, iclass 21, count 0 2006.285.11:45:07.25#ibcon#*after write, iclass 21, count 0 2006.285.11:45:07.25#ibcon#*before return 0, iclass 21, count 0 2006.285.11:45:07.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:45:07.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:45:07.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:45:07.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:45:07.25$setupk4/ifdk4 2006.285.11:45:07.25$ifdk4/lo= 2006.285.11:45:07.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:45:07.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:45:07.25$ifdk4/patch= 2006.285.11:45:07.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:45:07.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:45:07.25$setupk4/!*+20s 2006.285.11:45:15.46#abcon#<5=/05 1.0 1.8 19.03 951015.3\r\n> 2006.285.11:45:15.48#abcon#{5=INTERFACE CLEAR} 2006.285.11:45:15.54#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:45:19.14#trakl#Source acquired 2006.285.11:45:20.14#flagr#flagr/antenna,acquired 2006.285.11:45:21.76$setupk4/"tpicd 2006.285.11:45:21.76$setupk4/echo=off 2006.285.11:45:21.76$setupk4/xlog=off 2006.285.11:45:21.76:!2006.285.11:46:47 2006.285.11:46:47.02:preob 2006.285.11:46:48.14/onsource/TRACKING 2006.285.11:46:48.14:!2006.285.11:46:57 2006.285.11:46:57.02:"tape 2006.285.11:46:57.02:"st=record 2006.285.11:46:57.02:data_valid=on 2006.285.11:46:57.02:midob 2006.285.11:46:58.14/onsource/TRACKING 2006.285.11:46:58.14/wx/19.02,1015.4,95 2006.285.11:46:58.19/cable/+6.4909E-03 2006.285.11:46:59.29/va/01,07,usb,yes,31,34 2006.285.11:46:59.29/va/02,06,usb,yes,31,32 2006.285.11:46:59.29/va/03,07,usb,yes,31,33 2006.285.11:46:59.29/va/04,06,usb,yes,32,34 2006.285.11:46:59.29/va/05,03,usb,yes,32,32 2006.285.11:46:59.29/va/06,04,usb,yes,29,28 2006.285.11:46:59.29/va/07,04,usb,yes,29,30 2006.285.11:46:59.29/va/08,03,usb,yes,30,36 2006.285.11:46:59.52/valo/01,524.99,yes,locked 2006.285.11:46:59.52/valo/02,534.99,yes,locked 2006.285.11:46:59.52/valo/03,564.99,yes,locked 2006.285.11:46:59.52/valo/04,624.99,yes,locked 2006.285.11:46:59.52/valo/05,734.99,yes,locked 2006.285.11:46:59.52/valo/06,814.99,yes,locked 2006.285.11:46:59.52/valo/07,864.99,yes,locked 2006.285.11:46:59.52/valo/08,884.99,yes,locked 2006.285.11:47:00.61/vb/01,04,usb,yes,30,27 2006.285.11:47:00.61/vb/02,05,usb,yes,28,28 2006.285.11:47:00.61/vb/03,04,usb,yes,29,32 2006.285.11:47:00.61/vb/04,05,usb,yes,29,28 2006.285.11:47:00.61/vb/05,04,usb,yes,26,28 2006.285.11:47:00.61/vb/06,03,usb,yes,37,33 2006.285.11:47:00.61/vb/07,04,usb,yes,30,30 2006.285.11:47:00.61/vb/08,04,usb,yes,27,31 2006.285.11:47:00.83/vblo/01,629.99,yes,locked 2006.285.11:47:00.84/vblo/02,634.99,yes,locked 2006.285.11:47:00.84/vblo/03,649.99,yes,locked 2006.285.11:47:00.84/vblo/04,679.99,yes,locked 2006.285.11:47:00.84/vblo/05,709.99,yes,locked 2006.285.11:47:00.84/vblo/06,719.99,yes,locked 2006.285.11:47:00.84/vblo/07,734.99,yes,locked 2006.285.11:47:00.84/vblo/08,744.99,yes,locked 2006.285.11:47:00.98/vabw/8 2006.285.11:47:01.14/vbbw/8 2006.285.11:47:01.23/xfe/off,on,12.2 2006.285.11:47:01.60/ifatt/23,28,28,28 2006.285.11:47:02.08/fmout-gps/S +2.70E-07 2006.285.11:47:02.09:!2006.285.11:48:07 2006.285.11:48:07.02:data_valid=off 2006.285.11:48:07.02:"et 2006.285.11:48:07.02:!+3s 2006.285.11:48:10.04:"tape 2006.285.11:48:10.04:postob 2006.285.11:48:10.23/cable/+6.4926E-03 2006.285.11:48:10.24/wx/19.02,1015.4,95 2006.285.11:48:10.29/fmout-gps/S +2.68E-07 2006.285.11:48:10.30:scan_name=285-1149,jd0610,70 2006.285.11:48:10.30:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.285.11:48:11.15#flagr#flagr/antenna,new-source 2006.285.11:48:11.15:checkk5 2006.285.11:48:11.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:48:11.93/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:48:12.37/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:48:12.74/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:48:13.16/chk_obsdata//k5ts1/T2851146??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.11:48:13.54/chk_obsdata//k5ts2/T2851146??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.11:48:14.11/chk_obsdata//k5ts3/T2851146??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.11:48:14.49/chk_obsdata//k5ts4/T2851146??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.11:48:15.51/k5log//k5ts1_log_newline 2006.285.11:48:16.27/k5log//k5ts2_log_newline 2006.285.11:48:17.04/k5log//k5ts3_log_newline 2006.285.11:48:18.07/k5log//k5ts4_log_newline 2006.285.11:48:18.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:48:18.09:setupk4=1 2006.285.11:48:18.09$setupk4/echo=on 2006.285.11:48:18.09$setupk4/pcalon 2006.285.11:48:18.09$pcalon/"no phase cal control is implemented here 2006.285.11:48:18.09$setupk4/"tpicd=stop 2006.285.11:48:18.09$setupk4/"rec=synch_on 2006.285.11:48:18.09$setupk4/"rec_mode=128 2006.285.11:48:18.09$setupk4/!* 2006.285.11:48:18.09$setupk4/recpk4 2006.285.11:48:18.09$recpk4/recpatch= 2006.285.11:48:18.10$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:48:18.10$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:48:18.10$setupk4/vck44 2006.285.11:48:18.10$vck44/valo=1,524.99 2006.285.11:48:18.10#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.11:48:18.10#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.11:48:18.10#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:18.10#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:48:18.10#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:48:18.10#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:48:18.10#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:48:18.10#ibcon#first serial, iclass 26, count 0 2006.285.11:48:18.10#ibcon#enter sib2, iclass 26, count 0 2006.285.11:48:18.10#ibcon#flushed, iclass 26, count 0 2006.285.11:48:18.10#ibcon#about to write, iclass 26, count 0 2006.285.11:48:18.10#ibcon#wrote, iclass 26, count 0 2006.285.11:48:18.10#ibcon#about to read 3, iclass 26, count 0 2006.285.11:48:18.11#ibcon#read 3, iclass 26, count 0 2006.285.11:48:18.11#ibcon#about to read 4, iclass 26, count 0 2006.285.11:48:18.11#ibcon#read 4, iclass 26, count 0 2006.285.11:48:18.11#ibcon#about to read 5, iclass 26, count 0 2006.285.11:48:18.11#ibcon#read 5, iclass 26, count 0 2006.285.11:48:18.11#ibcon#about to read 6, iclass 26, count 0 2006.285.11:48:18.11#ibcon#read 6, iclass 26, count 0 2006.285.11:48:18.11#ibcon#end of sib2, iclass 26, count 0 2006.285.11:48:18.11#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:48:18.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:48:18.11#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:48:18.11#ibcon#*before write, iclass 26, count 0 2006.285.11:48:18.11#ibcon#enter sib2, iclass 26, count 0 2006.285.11:48:18.11#ibcon#flushed, iclass 26, count 0 2006.285.11:48:18.11#ibcon#about to write, iclass 26, count 0 2006.285.11:48:18.11#ibcon#wrote, iclass 26, count 0 2006.285.11:48:18.11#ibcon#about to read 3, iclass 26, count 0 2006.285.11:48:18.16#ibcon#read 3, iclass 26, count 0 2006.285.11:48:18.16#ibcon#about to read 4, iclass 26, count 0 2006.285.11:48:18.16#ibcon#read 4, iclass 26, count 0 2006.285.11:48:18.16#ibcon#about to read 5, iclass 26, count 0 2006.285.11:48:18.16#ibcon#read 5, iclass 26, count 0 2006.285.11:48:18.16#ibcon#about to read 6, iclass 26, count 0 2006.285.11:48:18.16#ibcon#read 6, iclass 26, count 0 2006.285.11:48:18.16#ibcon#end of sib2, iclass 26, count 0 2006.285.11:48:18.16#ibcon#*after write, iclass 26, count 0 2006.285.11:48:18.16#ibcon#*before return 0, iclass 26, count 0 2006.285.11:48:18.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:48:18.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:48:18.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:48:18.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:48:18.16$vck44/va=1,7 2006.285.11:48:18.17#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.11:48:18.17#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.11:48:18.17#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:18.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:48:18.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:48:18.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:48:18.17#ibcon#enter wrdev, iclass 28, count 2 2006.285.11:48:18.17#ibcon#first serial, iclass 28, count 2 2006.285.11:48:18.17#ibcon#enter sib2, iclass 28, count 2 2006.285.11:48:18.17#ibcon#flushed, iclass 28, count 2 2006.285.11:48:18.17#ibcon#about to write, iclass 28, count 2 2006.285.11:48:18.17#ibcon#wrote, iclass 28, count 2 2006.285.11:48:18.17#ibcon#about to read 3, iclass 28, count 2 2006.285.11:48:18.18#ibcon#read 3, iclass 28, count 2 2006.285.11:48:18.18#ibcon#about to read 4, iclass 28, count 2 2006.285.11:48:18.18#ibcon#read 4, iclass 28, count 2 2006.285.11:48:18.18#ibcon#about to read 5, iclass 28, count 2 2006.285.11:48:18.18#ibcon#read 5, iclass 28, count 2 2006.285.11:48:18.18#ibcon#about to read 6, iclass 28, count 2 2006.285.11:48:18.18#ibcon#read 6, iclass 28, count 2 2006.285.11:48:18.18#ibcon#end of sib2, iclass 28, count 2 2006.285.11:48:18.18#ibcon#*mode == 0, iclass 28, count 2 2006.285.11:48:18.18#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.11:48:18.18#ibcon#[25=AT01-07\r\n] 2006.285.11:48:18.18#ibcon#*before write, iclass 28, count 2 2006.285.11:48:18.18#ibcon#enter sib2, iclass 28, count 2 2006.285.11:48:18.18#ibcon#flushed, iclass 28, count 2 2006.285.11:48:18.18#ibcon#about to write, iclass 28, count 2 2006.285.11:48:18.18#ibcon#wrote, iclass 28, count 2 2006.285.11:48:18.18#ibcon#about to read 3, iclass 28, count 2 2006.285.11:48:18.21#ibcon#read 3, iclass 28, count 2 2006.285.11:48:18.21#ibcon#about to read 4, iclass 28, count 2 2006.285.11:48:18.21#ibcon#read 4, iclass 28, count 2 2006.285.11:48:18.21#ibcon#about to read 5, iclass 28, count 2 2006.285.11:48:18.21#ibcon#read 5, iclass 28, count 2 2006.285.11:48:18.21#ibcon#about to read 6, iclass 28, count 2 2006.285.11:48:18.21#ibcon#read 6, iclass 28, count 2 2006.285.11:48:18.21#ibcon#end of sib2, iclass 28, count 2 2006.285.11:48:18.21#ibcon#*after write, iclass 28, count 2 2006.285.11:48:18.21#ibcon#*before return 0, iclass 28, count 2 2006.285.11:48:18.21#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:48:18.21#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:48:18.21#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.11:48:18.21#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:18.21#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:48:18.33#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:48:18.33#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:48:18.33#ibcon#enter wrdev, iclass 28, count 0 2006.285.11:48:18.33#ibcon#first serial, iclass 28, count 0 2006.285.11:48:18.33#ibcon#enter sib2, iclass 28, count 0 2006.285.11:48:18.33#ibcon#flushed, iclass 28, count 0 2006.285.11:48:18.33#ibcon#about to write, iclass 28, count 0 2006.285.11:48:18.33#ibcon#wrote, iclass 28, count 0 2006.285.11:48:18.33#ibcon#about to read 3, iclass 28, count 0 2006.285.11:48:18.35#ibcon#read 3, iclass 28, count 0 2006.285.11:48:18.35#ibcon#about to read 4, iclass 28, count 0 2006.285.11:48:18.35#ibcon#read 4, iclass 28, count 0 2006.285.11:48:18.35#ibcon#about to read 5, iclass 28, count 0 2006.285.11:48:18.35#ibcon#read 5, iclass 28, count 0 2006.285.11:48:18.35#ibcon#about to read 6, iclass 28, count 0 2006.285.11:48:18.35#ibcon#read 6, iclass 28, count 0 2006.285.11:48:18.35#ibcon#end of sib2, iclass 28, count 0 2006.285.11:48:18.35#ibcon#*mode == 0, iclass 28, count 0 2006.285.11:48:18.35#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.11:48:18.35#ibcon#[25=USB\r\n] 2006.285.11:48:18.35#ibcon#*before write, iclass 28, count 0 2006.285.11:48:18.35#ibcon#enter sib2, iclass 28, count 0 2006.285.11:48:18.35#ibcon#flushed, iclass 28, count 0 2006.285.11:48:18.35#ibcon#about to write, iclass 28, count 0 2006.285.11:48:18.35#ibcon#wrote, iclass 28, count 0 2006.285.11:48:18.35#ibcon#about to read 3, iclass 28, count 0 2006.285.11:48:18.38#ibcon#read 3, iclass 28, count 0 2006.285.11:48:18.38#ibcon#about to read 4, iclass 28, count 0 2006.285.11:48:18.38#ibcon#read 4, iclass 28, count 0 2006.285.11:48:18.38#ibcon#about to read 5, iclass 28, count 0 2006.285.11:48:18.38#ibcon#read 5, iclass 28, count 0 2006.285.11:48:18.38#ibcon#about to read 6, iclass 28, count 0 2006.285.11:48:18.38#ibcon#read 6, iclass 28, count 0 2006.285.11:48:18.38#ibcon#end of sib2, iclass 28, count 0 2006.285.11:48:18.38#ibcon#*after write, iclass 28, count 0 2006.285.11:48:18.38#ibcon#*before return 0, iclass 28, count 0 2006.285.11:48:18.38#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:48:18.38#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:48:18.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.11:48:18.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.11:48:18.39$vck44/valo=2,534.99 2006.285.11:48:18.39#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.11:48:18.39#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.11:48:18.39#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:18.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:48:18.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:48:18.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:48:18.39#ibcon#enter wrdev, iclass 30, count 0 2006.285.11:48:18.39#ibcon#first serial, iclass 30, count 0 2006.285.11:48:18.39#ibcon#enter sib2, iclass 30, count 0 2006.285.11:48:18.39#ibcon#flushed, iclass 30, count 0 2006.285.11:48:18.39#ibcon#about to write, iclass 30, count 0 2006.285.11:48:18.39#ibcon#wrote, iclass 30, count 0 2006.285.11:48:18.39#ibcon#about to read 3, iclass 30, count 0 2006.285.11:48:18.40#ibcon#read 3, iclass 30, count 0 2006.285.11:48:18.40#ibcon#about to read 4, iclass 30, count 0 2006.285.11:48:18.40#ibcon#read 4, iclass 30, count 0 2006.285.11:48:18.40#ibcon#about to read 5, iclass 30, count 0 2006.285.11:48:18.40#ibcon#read 5, iclass 30, count 0 2006.285.11:48:18.40#ibcon#about to read 6, iclass 30, count 0 2006.285.11:48:18.40#ibcon#read 6, iclass 30, count 0 2006.285.11:48:18.40#ibcon#end of sib2, iclass 30, count 0 2006.285.11:48:18.40#ibcon#*mode == 0, iclass 30, count 0 2006.285.11:48:18.40#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.11:48:18.40#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:48:18.40#ibcon#*before write, iclass 30, count 0 2006.285.11:48:18.40#ibcon#enter sib2, iclass 30, count 0 2006.285.11:48:18.40#ibcon#flushed, iclass 30, count 0 2006.285.11:48:18.40#ibcon#about to write, iclass 30, count 0 2006.285.11:48:18.40#ibcon#wrote, iclass 30, count 0 2006.285.11:48:18.40#ibcon#about to read 3, iclass 30, count 0 2006.285.11:48:18.44#ibcon#read 3, iclass 30, count 0 2006.285.11:48:18.44#ibcon#about to read 4, iclass 30, count 0 2006.285.11:48:18.44#ibcon#read 4, iclass 30, count 0 2006.285.11:48:18.44#ibcon#about to read 5, iclass 30, count 0 2006.285.11:48:18.44#ibcon#read 5, iclass 30, count 0 2006.285.11:48:18.44#ibcon#about to read 6, iclass 30, count 0 2006.285.11:48:18.44#ibcon#read 6, iclass 30, count 0 2006.285.11:48:18.44#ibcon#end of sib2, iclass 30, count 0 2006.285.11:48:18.44#ibcon#*after write, iclass 30, count 0 2006.285.11:48:18.44#ibcon#*before return 0, iclass 30, count 0 2006.285.11:48:18.44#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:48:18.44#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:48:18.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.11:48:18.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.11:48:18.45$vck44/va=2,6 2006.285.11:48:18.45#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.11:48:18.45#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.11:48:18.45#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:18.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:48:18.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:48:18.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:48:18.49#ibcon#enter wrdev, iclass 32, count 2 2006.285.11:48:18.49#ibcon#first serial, iclass 32, count 2 2006.285.11:48:18.49#ibcon#enter sib2, iclass 32, count 2 2006.285.11:48:18.49#ibcon#flushed, iclass 32, count 2 2006.285.11:48:18.49#ibcon#about to write, iclass 32, count 2 2006.285.11:48:18.49#ibcon#wrote, iclass 32, count 2 2006.285.11:48:18.49#ibcon#about to read 3, iclass 32, count 2 2006.285.11:48:18.51#ibcon#read 3, iclass 32, count 2 2006.285.11:48:18.51#ibcon#about to read 4, iclass 32, count 2 2006.285.11:48:18.51#ibcon#read 4, iclass 32, count 2 2006.285.11:48:18.51#ibcon#about to read 5, iclass 32, count 2 2006.285.11:48:18.51#ibcon#read 5, iclass 32, count 2 2006.285.11:48:18.51#ibcon#about to read 6, iclass 32, count 2 2006.285.11:48:18.51#ibcon#read 6, iclass 32, count 2 2006.285.11:48:18.51#ibcon#end of sib2, iclass 32, count 2 2006.285.11:48:18.51#ibcon#*mode == 0, iclass 32, count 2 2006.285.11:48:18.51#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.11:48:18.51#ibcon#[25=AT02-06\r\n] 2006.285.11:48:18.51#ibcon#*before write, iclass 32, count 2 2006.285.11:48:18.51#ibcon#enter sib2, iclass 32, count 2 2006.285.11:48:18.51#ibcon#flushed, iclass 32, count 2 2006.285.11:48:18.51#ibcon#about to write, iclass 32, count 2 2006.285.11:48:18.51#ibcon#wrote, iclass 32, count 2 2006.285.11:48:18.51#ibcon#about to read 3, iclass 32, count 2 2006.285.11:48:18.51#abcon#<5=/05 1.0 1.4 19.02 951015.4\r\n> 2006.285.11:48:18.53#abcon#{5=INTERFACE CLEAR} 2006.285.11:48:18.54#ibcon#read 3, iclass 32, count 2 2006.285.11:48:18.54#ibcon#about to read 4, iclass 32, count 2 2006.285.11:48:18.54#ibcon#read 4, iclass 32, count 2 2006.285.11:48:18.54#ibcon#about to read 5, iclass 32, count 2 2006.285.11:48:18.54#ibcon#read 5, iclass 32, count 2 2006.285.11:48:18.54#ibcon#about to read 6, iclass 32, count 2 2006.285.11:48:18.54#ibcon#read 6, iclass 32, count 2 2006.285.11:48:18.54#ibcon#end of sib2, iclass 32, count 2 2006.285.11:48:18.54#ibcon#*after write, iclass 32, count 2 2006.285.11:48:18.54#ibcon#*before return 0, iclass 32, count 2 2006.285.11:48:18.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:48:18.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:48:18.54#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.11:48:18.54#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:18.54#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:48:18.59#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:48:18.66#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:48:18.66#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:48:18.66#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:48:18.66#ibcon#first serial, iclass 32, count 0 2006.285.11:48:18.66#ibcon#enter sib2, iclass 32, count 0 2006.285.11:48:18.66#ibcon#flushed, iclass 32, count 0 2006.285.11:48:18.66#ibcon#about to write, iclass 32, count 0 2006.285.11:48:18.66#ibcon#wrote, iclass 32, count 0 2006.285.11:48:18.66#ibcon#about to read 3, iclass 32, count 0 2006.285.11:48:18.68#ibcon#read 3, iclass 32, count 0 2006.285.11:48:18.68#ibcon#about to read 4, iclass 32, count 0 2006.285.11:48:18.68#ibcon#read 4, iclass 32, count 0 2006.285.11:48:18.68#ibcon#about to read 5, iclass 32, count 0 2006.285.11:48:18.68#ibcon#read 5, iclass 32, count 0 2006.285.11:48:18.68#ibcon#about to read 6, iclass 32, count 0 2006.285.11:48:18.68#ibcon#read 6, iclass 32, count 0 2006.285.11:48:18.68#ibcon#end of sib2, iclass 32, count 0 2006.285.11:48:18.68#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:48:18.68#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:48:18.68#ibcon#[25=USB\r\n] 2006.285.11:48:18.68#ibcon#*before write, iclass 32, count 0 2006.285.11:48:18.68#ibcon#enter sib2, iclass 32, count 0 2006.285.11:48:18.68#ibcon#flushed, iclass 32, count 0 2006.285.11:48:18.68#ibcon#about to write, iclass 32, count 0 2006.285.11:48:18.68#ibcon#wrote, iclass 32, count 0 2006.285.11:48:18.68#ibcon#about to read 3, iclass 32, count 0 2006.285.11:48:18.71#ibcon#read 3, iclass 32, count 0 2006.285.11:48:18.71#ibcon#about to read 4, iclass 32, count 0 2006.285.11:48:18.71#ibcon#read 4, iclass 32, count 0 2006.285.11:48:18.71#ibcon#about to read 5, iclass 32, count 0 2006.285.11:48:18.71#ibcon#read 5, iclass 32, count 0 2006.285.11:48:18.71#ibcon#about to read 6, iclass 32, count 0 2006.285.11:48:18.71#ibcon#read 6, iclass 32, count 0 2006.285.11:48:18.71#ibcon#end of sib2, iclass 32, count 0 2006.285.11:48:18.71#ibcon#*after write, iclass 32, count 0 2006.285.11:48:18.71#ibcon#*before return 0, iclass 32, count 0 2006.285.11:48:18.71#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:48:18.71#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:48:18.71#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:48:18.71#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:48:18.71$vck44/valo=3,564.99 2006.285.11:48:18.72#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.11:48:18.72#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.11:48:18.72#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:18.72#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:48:18.72#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:48:18.72#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:48:18.72#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:48:18.72#ibcon#first serial, iclass 38, count 0 2006.285.11:48:18.72#ibcon#enter sib2, iclass 38, count 0 2006.285.11:48:18.72#ibcon#flushed, iclass 38, count 0 2006.285.11:48:18.72#ibcon#about to write, iclass 38, count 0 2006.285.11:48:18.72#ibcon#wrote, iclass 38, count 0 2006.285.11:48:18.72#ibcon#about to read 3, iclass 38, count 0 2006.285.11:48:18.73#ibcon#read 3, iclass 38, count 0 2006.285.11:48:18.73#ibcon#about to read 4, iclass 38, count 0 2006.285.11:48:18.73#ibcon#read 4, iclass 38, count 0 2006.285.11:48:18.73#ibcon#about to read 5, iclass 38, count 0 2006.285.11:48:18.73#ibcon#read 5, iclass 38, count 0 2006.285.11:48:18.73#ibcon#about to read 6, iclass 38, count 0 2006.285.11:48:18.73#ibcon#read 6, iclass 38, count 0 2006.285.11:48:18.73#ibcon#end of sib2, iclass 38, count 0 2006.285.11:48:18.73#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:48:18.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:48:18.73#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:48:18.73#ibcon#*before write, iclass 38, count 0 2006.285.11:48:18.73#ibcon#enter sib2, iclass 38, count 0 2006.285.11:48:18.73#ibcon#flushed, iclass 38, count 0 2006.285.11:48:18.73#ibcon#about to write, iclass 38, count 0 2006.285.11:48:18.73#ibcon#wrote, iclass 38, count 0 2006.285.11:48:18.73#ibcon#about to read 3, iclass 38, count 0 2006.285.11:48:18.77#ibcon#read 3, iclass 38, count 0 2006.285.11:48:18.77#ibcon#about to read 4, iclass 38, count 0 2006.285.11:48:18.77#ibcon#read 4, iclass 38, count 0 2006.285.11:48:18.77#ibcon#about to read 5, iclass 38, count 0 2006.285.11:48:18.77#ibcon#read 5, iclass 38, count 0 2006.285.11:48:18.77#ibcon#about to read 6, iclass 38, count 0 2006.285.11:48:18.77#ibcon#read 6, iclass 38, count 0 2006.285.11:48:18.77#ibcon#end of sib2, iclass 38, count 0 2006.285.11:48:18.77#ibcon#*after write, iclass 38, count 0 2006.285.11:48:18.77#ibcon#*before return 0, iclass 38, count 0 2006.285.11:48:18.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:48:18.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:48:18.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:48:18.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:48:18.77$vck44/va=3,7 2006.285.11:48:18.78#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.11:48:18.78#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.11:48:18.78#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:18.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:48:18.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:48:18.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:48:18.82#ibcon#enter wrdev, iclass 40, count 2 2006.285.11:48:18.82#ibcon#first serial, iclass 40, count 2 2006.285.11:48:18.82#ibcon#enter sib2, iclass 40, count 2 2006.285.11:48:18.82#ibcon#flushed, iclass 40, count 2 2006.285.11:48:18.82#ibcon#about to write, iclass 40, count 2 2006.285.11:48:18.82#ibcon#wrote, iclass 40, count 2 2006.285.11:48:18.82#ibcon#about to read 3, iclass 40, count 2 2006.285.11:48:18.84#ibcon#read 3, iclass 40, count 2 2006.285.11:48:18.84#ibcon#about to read 4, iclass 40, count 2 2006.285.11:48:18.84#ibcon#read 4, iclass 40, count 2 2006.285.11:48:18.84#ibcon#about to read 5, iclass 40, count 2 2006.285.11:48:18.84#ibcon#read 5, iclass 40, count 2 2006.285.11:48:18.84#ibcon#about to read 6, iclass 40, count 2 2006.285.11:48:18.84#ibcon#read 6, iclass 40, count 2 2006.285.11:48:18.84#ibcon#end of sib2, iclass 40, count 2 2006.285.11:48:18.84#ibcon#*mode == 0, iclass 40, count 2 2006.285.11:48:18.84#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.11:48:18.84#ibcon#[25=AT03-07\r\n] 2006.285.11:48:18.84#ibcon#*before write, iclass 40, count 2 2006.285.11:48:18.84#ibcon#enter sib2, iclass 40, count 2 2006.285.11:48:18.84#ibcon#flushed, iclass 40, count 2 2006.285.11:48:18.84#ibcon#about to write, iclass 40, count 2 2006.285.11:48:18.84#ibcon#wrote, iclass 40, count 2 2006.285.11:48:18.84#ibcon#about to read 3, iclass 40, count 2 2006.285.11:48:18.87#ibcon#read 3, iclass 40, count 2 2006.285.11:48:18.87#ibcon#about to read 4, iclass 40, count 2 2006.285.11:48:18.87#ibcon#read 4, iclass 40, count 2 2006.285.11:48:18.87#ibcon#about to read 5, iclass 40, count 2 2006.285.11:48:18.87#ibcon#read 5, iclass 40, count 2 2006.285.11:48:18.87#ibcon#about to read 6, iclass 40, count 2 2006.285.11:48:18.87#ibcon#read 6, iclass 40, count 2 2006.285.11:48:18.87#ibcon#end of sib2, iclass 40, count 2 2006.285.11:48:18.87#ibcon#*after write, iclass 40, count 2 2006.285.11:48:18.87#ibcon#*before return 0, iclass 40, count 2 2006.285.11:48:18.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:48:18.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:48:18.87#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.11:48:18.87#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:18.87#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:48:18.99#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:48:18.99#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:48:18.99#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:48:18.99#ibcon#first serial, iclass 40, count 0 2006.285.11:48:18.99#ibcon#enter sib2, iclass 40, count 0 2006.285.11:48:18.99#ibcon#flushed, iclass 40, count 0 2006.285.11:48:18.99#ibcon#about to write, iclass 40, count 0 2006.285.11:48:18.99#ibcon#wrote, iclass 40, count 0 2006.285.11:48:18.99#ibcon#about to read 3, iclass 40, count 0 2006.285.11:48:19.01#ibcon#read 3, iclass 40, count 0 2006.285.11:48:19.01#ibcon#about to read 4, iclass 40, count 0 2006.285.11:48:19.01#ibcon#read 4, iclass 40, count 0 2006.285.11:48:19.01#ibcon#about to read 5, iclass 40, count 0 2006.285.11:48:19.01#ibcon#read 5, iclass 40, count 0 2006.285.11:48:19.01#ibcon#about to read 6, iclass 40, count 0 2006.285.11:48:19.01#ibcon#read 6, iclass 40, count 0 2006.285.11:48:19.01#ibcon#end of sib2, iclass 40, count 0 2006.285.11:48:19.01#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:48:19.01#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:48:19.01#ibcon#[25=USB\r\n] 2006.285.11:48:19.01#ibcon#*before write, iclass 40, count 0 2006.285.11:48:19.01#ibcon#enter sib2, iclass 40, count 0 2006.285.11:48:19.01#ibcon#flushed, iclass 40, count 0 2006.285.11:48:19.01#ibcon#about to write, iclass 40, count 0 2006.285.11:48:19.01#ibcon#wrote, iclass 40, count 0 2006.285.11:48:19.01#ibcon#about to read 3, iclass 40, count 0 2006.285.11:48:19.04#ibcon#read 3, iclass 40, count 0 2006.285.11:48:19.04#ibcon#about to read 4, iclass 40, count 0 2006.285.11:48:19.04#ibcon#read 4, iclass 40, count 0 2006.285.11:48:19.04#ibcon#about to read 5, iclass 40, count 0 2006.285.11:48:19.04#ibcon#read 5, iclass 40, count 0 2006.285.11:48:19.04#ibcon#about to read 6, iclass 40, count 0 2006.285.11:48:19.04#ibcon#read 6, iclass 40, count 0 2006.285.11:48:19.04#ibcon#end of sib2, iclass 40, count 0 2006.285.11:48:19.04#ibcon#*after write, iclass 40, count 0 2006.285.11:48:19.04#ibcon#*before return 0, iclass 40, count 0 2006.285.11:48:19.04#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:48:19.04#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:48:19.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:48:19.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:48:19.04$vck44/valo=4,624.99 2006.285.11:48:19.05#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.11:48:19.05#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.11:48:19.05#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:19.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:48:19.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:48:19.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:48:19.05#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:48:19.05#ibcon#first serial, iclass 4, count 0 2006.285.11:48:19.05#ibcon#enter sib2, iclass 4, count 0 2006.285.11:48:19.05#ibcon#flushed, iclass 4, count 0 2006.285.11:48:19.05#ibcon#about to write, iclass 4, count 0 2006.285.11:48:19.05#ibcon#wrote, iclass 4, count 0 2006.285.11:48:19.05#ibcon#about to read 3, iclass 4, count 0 2006.285.11:48:19.06#ibcon#read 3, iclass 4, count 0 2006.285.11:48:19.06#ibcon#about to read 4, iclass 4, count 0 2006.285.11:48:19.06#ibcon#read 4, iclass 4, count 0 2006.285.11:48:19.06#ibcon#about to read 5, iclass 4, count 0 2006.285.11:48:19.06#ibcon#read 5, iclass 4, count 0 2006.285.11:48:19.06#ibcon#about to read 6, iclass 4, count 0 2006.285.11:48:19.06#ibcon#read 6, iclass 4, count 0 2006.285.11:48:19.06#ibcon#end of sib2, iclass 4, count 0 2006.285.11:48:19.06#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:48:19.06#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:48:19.06#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:48:19.06#ibcon#*before write, iclass 4, count 0 2006.285.11:48:19.06#ibcon#enter sib2, iclass 4, count 0 2006.285.11:48:19.06#ibcon#flushed, iclass 4, count 0 2006.285.11:48:19.06#ibcon#about to write, iclass 4, count 0 2006.285.11:48:19.06#ibcon#wrote, iclass 4, count 0 2006.285.11:48:19.06#ibcon#about to read 3, iclass 4, count 0 2006.285.11:48:19.10#ibcon#read 3, iclass 4, count 0 2006.285.11:48:19.10#ibcon#about to read 4, iclass 4, count 0 2006.285.11:48:19.10#ibcon#read 4, iclass 4, count 0 2006.285.11:48:19.10#ibcon#about to read 5, iclass 4, count 0 2006.285.11:48:19.10#ibcon#read 5, iclass 4, count 0 2006.285.11:48:19.10#ibcon#about to read 6, iclass 4, count 0 2006.285.11:48:19.10#ibcon#read 6, iclass 4, count 0 2006.285.11:48:19.10#ibcon#end of sib2, iclass 4, count 0 2006.285.11:48:19.10#ibcon#*after write, iclass 4, count 0 2006.285.11:48:19.10#ibcon#*before return 0, iclass 4, count 0 2006.285.11:48:19.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:48:19.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:48:19.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:48:19.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:48:19.10$vck44/va=4,6 2006.285.11:48:19.11#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.11:48:19.11#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.11:48:19.11#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:19.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:48:19.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:48:19.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:48:19.15#ibcon#enter wrdev, iclass 6, count 2 2006.285.11:48:19.15#ibcon#first serial, iclass 6, count 2 2006.285.11:48:19.15#ibcon#enter sib2, iclass 6, count 2 2006.285.11:48:19.15#ibcon#flushed, iclass 6, count 2 2006.285.11:48:19.15#ibcon#about to write, iclass 6, count 2 2006.285.11:48:19.15#ibcon#wrote, iclass 6, count 2 2006.285.11:48:19.15#ibcon#about to read 3, iclass 6, count 2 2006.285.11:48:19.17#ibcon#read 3, iclass 6, count 2 2006.285.11:48:19.17#ibcon#about to read 4, iclass 6, count 2 2006.285.11:48:19.17#ibcon#read 4, iclass 6, count 2 2006.285.11:48:19.17#ibcon#about to read 5, iclass 6, count 2 2006.285.11:48:19.17#ibcon#read 5, iclass 6, count 2 2006.285.11:48:19.17#ibcon#about to read 6, iclass 6, count 2 2006.285.11:48:19.17#ibcon#read 6, iclass 6, count 2 2006.285.11:48:19.17#ibcon#end of sib2, iclass 6, count 2 2006.285.11:48:19.17#ibcon#*mode == 0, iclass 6, count 2 2006.285.11:48:19.17#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.11:48:19.17#ibcon#[25=AT04-06\r\n] 2006.285.11:48:19.17#ibcon#*before write, iclass 6, count 2 2006.285.11:48:19.17#ibcon#enter sib2, iclass 6, count 2 2006.285.11:48:19.17#ibcon#flushed, iclass 6, count 2 2006.285.11:48:19.17#ibcon#about to write, iclass 6, count 2 2006.285.11:48:19.17#ibcon#wrote, iclass 6, count 2 2006.285.11:48:19.17#ibcon#about to read 3, iclass 6, count 2 2006.285.11:48:19.20#ibcon#read 3, iclass 6, count 2 2006.285.11:48:19.20#ibcon#about to read 4, iclass 6, count 2 2006.285.11:48:19.20#ibcon#read 4, iclass 6, count 2 2006.285.11:48:19.20#ibcon#about to read 5, iclass 6, count 2 2006.285.11:48:19.20#ibcon#read 5, iclass 6, count 2 2006.285.11:48:19.20#ibcon#about to read 6, iclass 6, count 2 2006.285.11:48:19.20#ibcon#read 6, iclass 6, count 2 2006.285.11:48:19.20#ibcon#end of sib2, iclass 6, count 2 2006.285.11:48:19.20#ibcon#*after write, iclass 6, count 2 2006.285.11:48:19.20#ibcon#*before return 0, iclass 6, count 2 2006.285.11:48:19.20#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:48:19.20#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:48:19.20#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.11:48:19.20#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:19.20#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:48:19.32#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:48:19.32#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:48:19.32#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:48:19.32#ibcon#first serial, iclass 6, count 0 2006.285.11:48:19.32#ibcon#enter sib2, iclass 6, count 0 2006.285.11:48:19.32#ibcon#flushed, iclass 6, count 0 2006.285.11:48:19.32#ibcon#about to write, iclass 6, count 0 2006.285.11:48:19.33#ibcon#wrote, iclass 6, count 0 2006.285.11:48:19.33#ibcon#about to read 3, iclass 6, count 0 2006.285.11:48:19.34#ibcon#read 3, iclass 6, count 0 2006.285.11:48:19.34#ibcon#about to read 4, iclass 6, count 0 2006.285.11:48:19.34#ibcon#read 4, iclass 6, count 0 2006.285.11:48:19.34#ibcon#about to read 5, iclass 6, count 0 2006.285.11:48:19.34#ibcon#read 5, iclass 6, count 0 2006.285.11:48:19.34#ibcon#about to read 6, iclass 6, count 0 2006.285.11:48:19.34#ibcon#read 6, iclass 6, count 0 2006.285.11:48:19.34#ibcon#end of sib2, iclass 6, count 0 2006.285.11:48:19.34#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:48:19.34#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:48:19.34#ibcon#[25=USB\r\n] 2006.285.11:48:19.34#ibcon#*before write, iclass 6, count 0 2006.285.11:48:19.34#ibcon#enter sib2, iclass 6, count 0 2006.285.11:48:19.34#ibcon#flushed, iclass 6, count 0 2006.285.11:48:19.34#ibcon#about to write, iclass 6, count 0 2006.285.11:48:19.34#ibcon#wrote, iclass 6, count 0 2006.285.11:48:19.34#ibcon#about to read 3, iclass 6, count 0 2006.285.11:48:19.37#ibcon#read 3, iclass 6, count 0 2006.285.11:48:19.37#ibcon#about to read 4, iclass 6, count 0 2006.285.11:48:19.37#ibcon#read 4, iclass 6, count 0 2006.285.11:48:19.37#ibcon#about to read 5, iclass 6, count 0 2006.285.11:48:19.37#ibcon#read 5, iclass 6, count 0 2006.285.11:48:19.37#ibcon#about to read 6, iclass 6, count 0 2006.285.11:48:19.37#ibcon#read 6, iclass 6, count 0 2006.285.11:48:19.37#ibcon#end of sib2, iclass 6, count 0 2006.285.11:48:19.37#ibcon#*after write, iclass 6, count 0 2006.285.11:48:19.37#ibcon#*before return 0, iclass 6, count 0 2006.285.11:48:19.37#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:48:19.37#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:48:19.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:48:19.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:48:19.38$vck44/valo=5,734.99 2006.285.11:48:19.38#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.11:48:19.38#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.11:48:19.38#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:19.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:48:19.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:48:19.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:48:19.38#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:48:19.38#ibcon#first serial, iclass 10, count 0 2006.285.11:48:19.38#ibcon#enter sib2, iclass 10, count 0 2006.285.11:48:19.38#ibcon#flushed, iclass 10, count 0 2006.285.11:48:19.38#ibcon#about to write, iclass 10, count 0 2006.285.11:48:19.38#ibcon#wrote, iclass 10, count 0 2006.285.11:48:19.38#ibcon#about to read 3, iclass 10, count 0 2006.285.11:48:19.39#ibcon#read 3, iclass 10, count 0 2006.285.11:48:19.39#ibcon#about to read 4, iclass 10, count 0 2006.285.11:48:19.39#ibcon#read 4, iclass 10, count 0 2006.285.11:48:19.39#ibcon#about to read 5, iclass 10, count 0 2006.285.11:48:19.39#ibcon#read 5, iclass 10, count 0 2006.285.11:48:19.39#ibcon#about to read 6, iclass 10, count 0 2006.285.11:48:19.39#ibcon#read 6, iclass 10, count 0 2006.285.11:48:19.39#ibcon#end of sib2, iclass 10, count 0 2006.285.11:48:19.39#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:48:19.39#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:48:19.39#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:48:19.39#ibcon#*before write, iclass 10, count 0 2006.285.11:48:19.39#ibcon#enter sib2, iclass 10, count 0 2006.285.11:48:19.39#ibcon#flushed, iclass 10, count 0 2006.285.11:48:19.39#ibcon#about to write, iclass 10, count 0 2006.285.11:48:19.39#ibcon#wrote, iclass 10, count 0 2006.285.11:48:19.39#ibcon#about to read 3, iclass 10, count 0 2006.285.11:48:19.43#ibcon#read 3, iclass 10, count 0 2006.285.11:48:19.43#ibcon#about to read 4, iclass 10, count 0 2006.285.11:48:19.43#ibcon#read 4, iclass 10, count 0 2006.285.11:48:19.43#ibcon#about to read 5, iclass 10, count 0 2006.285.11:48:19.43#ibcon#read 5, iclass 10, count 0 2006.285.11:48:19.43#ibcon#about to read 6, iclass 10, count 0 2006.285.11:48:19.43#ibcon#read 6, iclass 10, count 0 2006.285.11:48:19.43#ibcon#end of sib2, iclass 10, count 0 2006.285.11:48:19.43#ibcon#*after write, iclass 10, count 0 2006.285.11:48:19.43#ibcon#*before return 0, iclass 10, count 0 2006.285.11:48:19.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:48:19.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:48:19.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:48:19.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:48:19.44$vck44/va=5,3 2006.285.11:48:19.44#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.11:48:19.44#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.11:48:19.44#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:19.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:48:19.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:48:19.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:48:19.48#ibcon#enter wrdev, iclass 12, count 2 2006.285.11:48:19.48#ibcon#first serial, iclass 12, count 2 2006.285.11:48:19.48#ibcon#enter sib2, iclass 12, count 2 2006.285.11:48:19.48#ibcon#flushed, iclass 12, count 2 2006.285.11:48:19.48#ibcon#about to write, iclass 12, count 2 2006.285.11:48:19.48#ibcon#wrote, iclass 12, count 2 2006.285.11:48:19.48#ibcon#about to read 3, iclass 12, count 2 2006.285.11:48:19.50#ibcon#read 3, iclass 12, count 2 2006.285.11:48:19.50#ibcon#about to read 4, iclass 12, count 2 2006.285.11:48:19.50#ibcon#read 4, iclass 12, count 2 2006.285.11:48:19.50#ibcon#about to read 5, iclass 12, count 2 2006.285.11:48:19.50#ibcon#read 5, iclass 12, count 2 2006.285.11:48:19.50#ibcon#about to read 6, iclass 12, count 2 2006.285.11:48:19.50#ibcon#read 6, iclass 12, count 2 2006.285.11:48:19.50#ibcon#end of sib2, iclass 12, count 2 2006.285.11:48:19.50#ibcon#*mode == 0, iclass 12, count 2 2006.285.11:48:19.50#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.11:48:19.50#ibcon#[25=AT05-03\r\n] 2006.285.11:48:19.50#ibcon#*before write, iclass 12, count 2 2006.285.11:48:19.50#ibcon#enter sib2, iclass 12, count 2 2006.285.11:48:19.50#ibcon#flushed, iclass 12, count 2 2006.285.11:48:19.50#ibcon#about to write, iclass 12, count 2 2006.285.11:48:19.50#ibcon#wrote, iclass 12, count 2 2006.285.11:48:19.50#ibcon#about to read 3, iclass 12, count 2 2006.285.11:48:19.53#ibcon#read 3, iclass 12, count 2 2006.285.11:48:19.53#ibcon#about to read 4, iclass 12, count 2 2006.285.11:48:19.53#ibcon#read 4, iclass 12, count 2 2006.285.11:48:19.53#ibcon#about to read 5, iclass 12, count 2 2006.285.11:48:19.53#ibcon#read 5, iclass 12, count 2 2006.285.11:48:19.53#ibcon#about to read 6, iclass 12, count 2 2006.285.11:48:19.53#ibcon#read 6, iclass 12, count 2 2006.285.11:48:19.53#ibcon#end of sib2, iclass 12, count 2 2006.285.11:48:19.53#ibcon#*after write, iclass 12, count 2 2006.285.11:48:19.53#ibcon#*before return 0, iclass 12, count 2 2006.285.11:48:19.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:48:19.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:48:19.53#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.11:48:19.53#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:19.53#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:48:19.65#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:48:19.65#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:48:19.65#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:48:19.65#ibcon#first serial, iclass 12, count 0 2006.285.11:48:19.65#ibcon#enter sib2, iclass 12, count 0 2006.285.11:48:19.65#ibcon#flushed, iclass 12, count 0 2006.285.11:48:19.65#ibcon#about to write, iclass 12, count 0 2006.285.11:48:19.65#ibcon#wrote, iclass 12, count 0 2006.285.11:48:19.65#ibcon#about to read 3, iclass 12, count 0 2006.285.11:48:19.67#ibcon#read 3, iclass 12, count 0 2006.285.11:48:19.67#ibcon#about to read 4, iclass 12, count 0 2006.285.11:48:19.67#ibcon#read 4, iclass 12, count 0 2006.285.11:48:19.67#ibcon#about to read 5, iclass 12, count 0 2006.285.11:48:19.67#ibcon#read 5, iclass 12, count 0 2006.285.11:48:19.67#ibcon#about to read 6, iclass 12, count 0 2006.285.11:48:19.67#ibcon#read 6, iclass 12, count 0 2006.285.11:48:19.67#ibcon#end of sib2, iclass 12, count 0 2006.285.11:48:19.67#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:48:19.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:48:19.67#ibcon#[25=USB\r\n] 2006.285.11:48:19.67#ibcon#*before write, iclass 12, count 0 2006.285.11:48:19.67#ibcon#enter sib2, iclass 12, count 0 2006.285.11:48:19.67#ibcon#flushed, iclass 12, count 0 2006.285.11:48:19.67#ibcon#about to write, iclass 12, count 0 2006.285.11:48:19.67#ibcon#wrote, iclass 12, count 0 2006.285.11:48:19.67#ibcon#about to read 3, iclass 12, count 0 2006.285.11:48:19.70#ibcon#read 3, iclass 12, count 0 2006.285.11:48:19.70#ibcon#about to read 4, iclass 12, count 0 2006.285.11:48:19.70#ibcon#read 4, iclass 12, count 0 2006.285.11:48:19.70#ibcon#about to read 5, iclass 12, count 0 2006.285.11:48:19.70#ibcon#read 5, iclass 12, count 0 2006.285.11:48:19.70#ibcon#about to read 6, iclass 12, count 0 2006.285.11:48:19.70#ibcon#read 6, iclass 12, count 0 2006.285.11:48:19.70#ibcon#end of sib2, iclass 12, count 0 2006.285.11:48:19.70#ibcon#*after write, iclass 12, count 0 2006.285.11:48:19.70#ibcon#*before return 0, iclass 12, count 0 2006.285.11:48:19.70#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:48:19.70#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:48:19.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:48:19.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:48:19.70$vck44/valo=6,814.99 2006.285.11:48:19.71#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.11:48:19.71#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.11:48:19.71#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:19.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:48:19.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:48:19.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:48:19.71#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:48:19.71#ibcon#first serial, iclass 14, count 0 2006.285.11:48:19.71#ibcon#enter sib2, iclass 14, count 0 2006.285.11:48:19.71#ibcon#flushed, iclass 14, count 0 2006.285.11:48:19.71#ibcon#about to write, iclass 14, count 0 2006.285.11:48:19.71#ibcon#wrote, iclass 14, count 0 2006.285.11:48:19.71#ibcon#about to read 3, iclass 14, count 0 2006.285.11:48:19.72#ibcon#read 3, iclass 14, count 0 2006.285.11:48:19.72#ibcon#about to read 4, iclass 14, count 0 2006.285.11:48:19.72#ibcon#read 4, iclass 14, count 0 2006.285.11:48:19.72#ibcon#about to read 5, iclass 14, count 0 2006.285.11:48:19.72#ibcon#read 5, iclass 14, count 0 2006.285.11:48:19.72#ibcon#about to read 6, iclass 14, count 0 2006.285.11:48:19.72#ibcon#read 6, iclass 14, count 0 2006.285.11:48:19.72#ibcon#end of sib2, iclass 14, count 0 2006.285.11:48:19.72#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:48:19.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:48:19.72#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:48:19.72#ibcon#*before write, iclass 14, count 0 2006.285.11:48:19.72#ibcon#enter sib2, iclass 14, count 0 2006.285.11:48:19.72#ibcon#flushed, iclass 14, count 0 2006.285.11:48:19.72#ibcon#about to write, iclass 14, count 0 2006.285.11:48:19.72#ibcon#wrote, iclass 14, count 0 2006.285.11:48:19.72#ibcon#about to read 3, iclass 14, count 0 2006.285.11:48:19.76#ibcon#read 3, iclass 14, count 0 2006.285.11:48:19.76#ibcon#about to read 4, iclass 14, count 0 2006.285.11:48:19.76#ibcon#read 4, iclass 14, count 0 2006.285.11:48:19.76#ibcon#about to read 5, iclass 14, count 0 2006.285.11:48:19.76#ibcon#read 5, iclass 14, count 0 2006.285.11:48:19.76#ibcon#about to read 6, iclass 14, count 0 2006.285.11:48:19.76#ibcon#read 6, iclass 14, count 0 2006.285.11:48:19.76#ibcon#end of sib2, iclass 14, count 0 2006.285.11:48:19.76#ibcon#*after write, iclass 14, count 0 2006.285.11:48:19.76#ibcon#*before return 0, iclass 14, count 0 2006.285.11:48:19.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:48:19.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:48:19.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:48:19.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:48:19.76$vck44/va=6,4 2006.285.11:48:19.77#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.11:48:19.77#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.11:48:19.77#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:19.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:48:19.81#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:48:19.81#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:48:19.81#ibcon#enter wrdev, iclass 16, count 2 2006.285.11:48:19.81#ibcon#first serial, iclass 16, count 2 2006.285.11:48:19.81#ibcon#enter sib2, iclass 16, count 2 2006.285.11:48:19.81#ibcon#flushed, iclass 16, count 2 2006.285.11:48:19.81#ibcon#about to write, iclass 16, count 2 2006.285.11:48:19.81#ibcon#wrote, iclass 16, count 2 2006.285.11:48:19.81#ibcon#about to read 3, iclass 16, count 2 2006.285.11:48:19.83#ibcon#read 3, iclass 16, count 2 2006.285.11:48:19.83#ibcon#about to read 4, iclass 16, count 2 2006.285.11:48:19.83#ibcon#read 4, iclass 16, count 2 2006.285.11:48:19.83#ibcon#about to read 5, iclass 16, count 2 2006.285.11:48:19.83#ibcon#read 5, iclass 16, count 2 2006.285.11:48:19.83#ibcon#about to read 6, iclass 16, count 2 2006.285.11:48:19.83#ibcon#read 6, iclass 16, count 2 2006.285.11:48:19.83#ibcon#end of sib2, iclass 16, count 2 2006.285.11:48:19.83#ibcon#*mode == 0, iclass 16, count 2 2006.285.11:48:19.83#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.11:48:19.83#ibcon#[25=AT06-04\r\n] 2006.285.11:48:19.83#ibcon#*before write, iclass 16, count 2 2006.285.11:48:19.83#ibcon#enter sib2, iclass 16, count 2 2006.285.11:48:19.83#ibcon#flushed, iclass 16, count 2 2006.285.11:48:19.83#ibcon#about to write, iclass 16, count 2 2006.285.11:48:19.83#ibcon#wrote, iclass 16, count 2 2006.285.11:48:19.83#ibcon#about to read 3, iclass 16, count 2 2006.285.11:48:19.86#ibcon#read 3, iclass 16, count 2 2006.285.11:48:19.86#ibcon#about to read 4, iclass 16, count 2 2006.285.11:48:19.86#ibcon#read 4, iclass 16, count 2 2006.285.11:48:19.86#ibcon#about to read 5, iclass 16, count 2 2006.285.11:48:19.86#ibcon#read 5, iclass 16, count 2 2006.285.11:48:19.86#ibcon#about to read 6, iclass 16, count 2 2006.285.11:48:19.86#ibcon#read 6, iclass 16, count 2 2006.285.11:48:19.86#ibcon#end of sib2, iclass 16, count 2 2006.285.11:48:19.86#ibcon#*after write, iclass 16, count 2 2006.285.11:48:19.86#ibcon#*before return 0, iclass 16, count 2 2006.285.11:48:19.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:48:19.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:48:19.86#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.11:48:19.86#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:19.86#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:48:19.98#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:48:19.98#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:48:19.98#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:48:19.98#ibcon#first serial, iclass 16, count 0 2006.285.11:48:19.98#ibcon#enter sib2, iclass 16, count 0 2006.285.11:48:19.98#ibcon#flushed, iclass 16, count 0 2006.285.11:48:19.98#ibcon#about to write, iclass 16, count 0 2006.285.11:48:19.98#ibcon#wrote, iclass 16, count 0 2006.285.11:48:19.98#ibcon#about to read 3, iclass 16, count 0 2006.285.11:48:20.00#ibcon#read 3, iclass 16, count 0 2006.285.11:48:20.00#ibcon#about to read 4, iclass 16, count 0 2006.285.11:48:20.00#ibcon#read 4, iclass 16, count 0 2006.285.11:48:20.00#ibcon#about to read 5, iclass 16, count 0 2006.285.11:48:20.00#ibcon#read 5, iclass 16, count 0 2006.285.11:48:20.00#ibcon#about to read 6, iclass 16, count 0 2006.285.11:48:20.00#ibcon#read 6, iclass 16, count 0 2006.285.11:48:20.00#ibcon#end of sib2, iclass 16, count 0 2006.285.11:48:20.00#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:48:20.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:48:20.00#ibcon#[25=USB\r\n] 2006.285.11:48:20.00#ibcon#*before write, iclass 16, count 0 2006.285.11:48:20.00#ibcon#enter sib2, iclass 16, count 0 2006.285.11:48:20.00#ibcon#flushed, iclass 16, count 0 2006.285.11:48:20.00#ibcon#about to write, iclass 16, count 0 2006.285.11:48:20.00#ibcon#wrote, iclass 16, count 0 2006.285.11:48:20.00#ibcon#about to read 3, iclass 16, count 0 2006.285.11:48:20.03#ibcon#read 3, iclass 16, count 0 2006.285.11:48:20.03#ibcon#about to read 4, iclass 16, count 0 2006.285.11:48:20.03#ibcon#read 4, iclass 16, count 0 2006.285.11:48:20.03#ibcon#about to read 5, iclass 16, count 0 2006.285.11:48:20.03#ibcon#read 5, iclass 16, count 0 2006.285.11:48:20.03#ibcon#about to read 6, iclass 16, count 0 2006.285.11:48:20.03#ibcon#read 6, iclass 16, count 0 2006.285.11:48:20.03#ibcon#end of sib2, iclass 16, count 0 2006.285.11:48:20.03#ibcon#*after write, iclass 16, count 0 2006.285.11:48:20.03#ibcon#*before return 0, iclass 16, count 0 2006.285.11:48:20.03#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:48:20.03#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:48:20.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:48:20.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:48:20.03$vck44/valo=7,864.99 2006.285.11:48:20.04#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.11:48:20.04#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.11:48:20.04#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:20.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:48:20.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:48:20.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:48:20.04#ibcon#enter wrdev, iclass 18, count 0 2006.285.11:48:20.04#ibcon#first serial, iclass 18, count 0 2006.285.11:48:20.04#ibcon#enter sib2, iclass 18, count 0 2006.285.11:48:20.04#ibcon#flushed, iclass 18, count 0 2006.285.11:48:20.04#ibcon#about to write, iclass 18, count 0 2006.285.11:48:20.04#ibcon#wrote, iclass 18, count 0 2006.285.11:48:20.04#ibcon#about to read 3, iclass 18, count 0 2006.285.11:48:20.05#ibcon#read 3, iclass 18, count 0 2006.285.11:48:20.05#ibcon#about to read 4, iclass 18, count 0 2006.285.11:48:20.05#ibcon#read 4, iclass 18, count 0 2006.285.11:48:20.05#ibcon#about to read 5, iclass 18, count 0 2006.285.11:48:20.05#ibcon#read 5, iclass 18, count 0 2006.285.11:48:20.05#ibcon#about to read 6, iclass 18, count 0 2006.285.11:48:20.05#ibcon#read 6, iclass 18, count 0 2006.285.11:48:20.05#ibcon#end of sib2, iclass 18, count 0 2006.285.11:48:20.05#ibcon#*mode == 0, iclass 18, count 0 2006.285.11:48:20.05#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.11:48:20.05#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:48:20.05#ibcon#*before write, iclass 18, count 0 2006.285.11:48:20.05#ibcon#enter sib2, iclass 18, count 0 2006.285.11:48:20.05#ibcon#flushed, iclass 18, count 0 2006.285.11:48:20.05#ibcon#about to write, iclass 18, count 0 2006.285.11:48:20.05#ibcon#wrote, iclass 18, count 0 2006.285.11:48:20.05#ibcon#about to read 3, iclass 18, count 0 2006.285.11:48:20.09#ibcon#read 3, iclass 18, count 0 2006.285.11:48:20.09#ibcon#about to read 4, iclass 18, count 0 2006.285.11:48:20.09#ibcon#read 4, iclass 18, count 0 2006.285.11:48:20.09#ibcon#about to read 5, iclass 18, count 0 2006.285.11:48:20.09#ibcon#read 5, iclass 18, count 0 2006.285.11:48:20.09#ibcon#about to read 6, iclass 18, count 0 2006.285.11:48:20.09#ibcon#read 6, iclass 18, count 0 2006.285.11:48:20.09#ibcon#end of sib2, iclass 18, count 0 2006.285.11:48:20.09#ibcon#*after write, iclass 18, count 0 2006.285.11:48:20.09#ibcon#*before return 0, iclass 18, count 0 2006.285.11:48:20.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:48:20.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:48:20.09#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.11:48:20.09#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.11:48:20.09$vck44/va=7,4 2006.285.11:48:20.10#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.11:48:20.10#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.11:48:20.10#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:20.10#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:48:20.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:48:20.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:48:20.15#ibcon#enter wrdev, iclass 20, count 2 2006.285.11:48:20.15#ibcon#first serial, iclass 20, count 2 2006.285.11:48:20.15#ibcon#enter sib2, iclass 20, count 2 2006.285.11:48:20.15#ibcon#flushed, iclass 20, count 2 2006.285.11:48:20.15#ibcon#about to write, iclass 20, count 2 2006.285.11:48:20.15#ibcon#wrote, iclass 20, count 2 2006.285.11:48:20.15#ibcon#about to read 3, iclass 20, count 2 2006.285.11:48:20.16#ibcon#read 3, iclass 20, count 2 2006.285.11:48:20.16#ibcon#about to read 4, iclass 20, count 2 2006.285.11:48:20.16#ibcon#read 4, iclass 20, count 2 2006.285.11:48:20.16#ibcon#about to read 5, iclass 20, count 2 2006.285.11:48:20.16#ibcon#read 5, iclass 20, count 2 2006.285.11:48:20.16#ibcon#about to read 6, iclass 20, count 2 2006.285.11:48:20.16#ibcon#read 6, iclass 20, count 2 2006.285.11:48:20.16#ibcon#end of sib2, iclass 20, count 2 2006.285.11:48:20.16#ibcon#*mode == 0, iclass 20, count 2 2006.285.11:48:20.16#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.11:48:20.16#ibcon#[25=AT07-04\r\n] 2006.285.11:48:20.16#ibcon#*before write, iclass 20, count 2 2006.285.11:48:20.16#ibcon#enter sib2, iclass 20, count 2 2006.285.11:48:20.16#ibcon#flushed, iclass 20, count 2 2006.285.11:48:20.16#ibcon#about to write, iclass 20, count 2 2006.285.11:48:20.16#ibcon#wrote, iclass 20, count 2 2006.285.11:48:20.16#ibcon#about to read 3, iclass 20, count 2 2006.285.11:48:20.19#ibcon#read 3, iclass 20, count 2 2006.285.11:48:20.19#ibcon#about to read 4, iclass 20, count 2 2006.285.11:48:20.19#ibcon#read 4, iclass 20, count 2 2006.285.11:48:20.19#ibcon#about to read 5, iclass 20, count 2 2006.285.11:48:20.19#ibcon#read 5, iclass 20, count 2 2006.285.11:48:20.19#ibcon#about to read 6, iclass 20, count 2 2006.285.11:48:20.19#ibcon#read 6, iclass 20, count 2 2006.285.11:48:20.19#ibcon#end of sib2, iclass 20, count 2 2006.285.11:48:20.19#ibcon#*after write, iclass 20, count 2 2006.285.11:48:20.19#ibcon#*before return 0, iclass 20, count 2 2006.285.11:48:20.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:48:20.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:48:20.19#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.11:48:20.19#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:20.19#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:48:20.31#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:48:20.31#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:48:20.31#ibcon#enter wrdev, iclass 20, count 0 2006.285.11:48:20.31#ibcon#first serial, iclass 20, count 0 2006.285.11:48:20.31#ibcon#enter sib2, iclass 20, count 0 2006.285.11:48:20.31#ibcon#flushed, iclass 20, count 0 2006.285.11:48:20.31#ibcon#about to write, iclass 20, count 0 2006.285.11:48:20.31#ibcon#wrote, iclass 20, count 0 2006.285.11:48:20.31#ibcon#about to read 3, iclass 20, count 0 2006.285.11:48:20.33#ibcon#read 3, iclass 20, count 0 2006.285.11:48:20.33#ibcon#about to read 4, iclass 20, count 0 2006.285.11:48:20.33#ibcon#read 4, iclass 20, count 0 2006.285.11:48:20.33#ibcon#about to read 5, iclass 20, count 0 2006.285.11:48:20.33#ibcon#read 5, iclass 20, count 0 2006.285.11:48:20.33#ibcon#about to read 6, iclass 20, count 0 2006.285.11:48:20.33#ibcon#read 6, iclass 20, count 0 2006.285.11:48:20.33#ibcon#end of sib2, iclass 20, count 0 2006.285.11:48:20.33#ibcon#*mode == 0, iclass 20, count 0 2006.285.11:48:20.33#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.11:48:20.33#ibcon#[25=USB\r\n] 2006.285.11:48:20.33#ibcon#*before write, iclass 20, count 0 2006.285.11:48:20.33#ibcon#enter sib2, iclass 20, count 0 2006.285.11:48:20.33#ibcon#flushed, iclass 20, count 0 2006.285.11:48:20.33#ibcon#about to write, iclass 20, count 0 2006.285.11:48:20.33#ibcon#wrote, iclass 20, count 0 2006.285.11:48:20.33#ibcon#about to read 3, iclass 20, count 0 2006.285.11:48:20.36#ibcon#read 3, iclass 20, count 0 2006.285.11:48:20.36#ibcon#about to read 4, iclass 20, count 0 2006.285.11:48:20.36#ibcon#read 4, iclass 20, count 0 2006.285.11:48:20.36#ibcon#about to read 5, iclass 20, count 0 2006.285.11:48:20.36#ibcon#read 5, iclass 20, count 0 2006.285.11:48:20.36#ibcon#about to read 6, iclass 20, count 0 2006.285.11:48:20.36#ibcon#read 6, iclass 20, count 0 2006.285.11:48:20.36#ibcon#end of sib2, iclass 20, count 0 2006.285.11:48:20.36#ibcon#*after write, iclass 20, count 0 2006.285.11:48:20.36#ibcon#*before return 0, iclass 20, count 0 2006.285.11:48:20.36#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:48:20.36#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:48:20.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.11:48:20.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.11:48:20.37$vck44/valo=8,884.99 2006.285.11:48:20.37#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.11:48:20.37#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.11:48:20.37#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:20.37#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:48:20.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:48:20.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:48:20.37#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:48:20.37#ibcon#first serial, iclass 22, count 0 2006.285.11:48:20.37#ibcon#enter sib2, iclass 22, count 0 2006.285.11:48:20.37#ibcon#flushed, iclass 22, count 0 2006.285.11:48:20.37#ibcon#about to write, iclass 22, count 0 2006.285.11:48:20.37#ibcon#wrote, iclass 22, count 0 2006.285.11:48:20.37#ibcon#about to read 3, iclass 22, count 0 2006.285.11:48:20.38#ibcon#read 3, iclass 22, count 0 2006.285.11:48:20.38#ibcon#about to read 4, iclass 22, count 0 2006.285.11:48:20.38#ibcon#read 4, iclass 22, count 0 2006.285.11:48:20.38#ibcon#about to read 5, iclass 22, count 0 2006.285.11:48:20.38#ibcon#read 5, iclass 22, count 0 2006.285.11:48:20.38#ibcon#about to read 6, iclass 22, count 0 2006.285.11:48:20.38#ibcon#read 6, iclass 22, count 0 2006.285.11:48:20.38#ibcon#end of sib2, iclass 22, count 0 2006.285.11:48:20.38#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:48:20.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:48:20.38#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:48:20.38#ibcon#*before write, iclass 22, count 0 2006.285.11:48:20.38#ibcon#enter sib2, iclass 22, count 0 2006.285.11:48:20.38#ibcon#flushed, iclass 22, count 0 2006.285.11:48:20.38#ibcon#about to write, iclass 22, count 0 2006.285.11:48:20.38#ibcon#wrote, iclass 22, count 0 2006.285.11:48:20.38#ibcon#about to read 3, iclass 22, count 0 2006.285.11:48:20.42#ibcon#read 3, iclass 22, count 0 2006.285.11:48:20.42#ibcon#about to read 4, iclass 22, count 0 2006.285.11:48:20.42#ibcon#read 4, iclass 22, count 0 2006.285.11:48:20.42#ibcon#about to read 5, iclass 22, count 0 2006.285.11:48:20.42#ibcon#read 5, iclass 22, count 0 2006.285.11:48:20.42#ibcon#about to read 6, iclass 22, count 0 2006.285.11:48:20.42#ibcon#read 6, iclass 22, count 0 2006.285.11:48:20.42#ibcon#end of sib2, iclass 22, count 0 2006.285.11:48:20.42#ibcon#*after write, iclass 22, count 0 2006.285.11:48:20.42#ibcon#*before return 0, iclass 22, count 0 2006.285.11:48:20.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:48:20.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:48:20.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:48:20.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:48:20.43$vck44/va=8,3 2006.285.11:48:20.43#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.11:48:20.43#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.11:48:20.43#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:20.43#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:48:20.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:48:20.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:48:20.47#ibcon#enter wrdev, iclass 24, count 2 2006.285.11:48:20.47#ibcon#first serial, iclass 24, count 2 2006.285.11:48:20.47#ibcon#enter sib2, iclass 24, count 2 2006.285.11:48:20.47#ibcon#flushed, iclass 24, count 2 2006.285.11:48:20.47#ibcon#about to write, iclass 24, count 2 2006.285.11:48:20.47#ibcon#wrote, iclass 24, count 2 2006.285.11:48:20.47#ibcon#about to read 3, iclass 24, count 2 2006.285.11:48:20.49#ibcon#read 3, iclass 24, count 2 2006.285.11:48:20.49#ibcon#about to read 4, iclass 24, count 2 2006.285.11:48:20.49#ibcon#read 4, iclass 24, count 2 2006.285.11:48:20.49#ibcon#about to read 5, iclass 24, count 2 2006.285.11:48:20.49#ibcon#read 5, iclass 24, count 2 2006.285.11:48:20.49#ibcon#about to read 6, iclass 24, count 2 2006.285.11:48:20.49#ibcon#read 6, iclass 24, count 2 2006.285.11:48:20.49#ibcon#end of sib2, iclass 24, count 2 2006.285.11:48:20.49#ibcon#*mode == 0, iclass 24, count 2 2006.285.11:48:20.49#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.11:48:20.49#ibcon#[25=AT08-03\r\n] 2006.285.11:48:20.49#ibcon#*before write, iclass 24, count 2 2006.285.11:48:20.49#ibcon#enter sib2, iclass 24, count 2 2006.285.11:48:20.49#ibcon#flushed, iclass 24, count 2 2006.285.11:48:20.49#ibcon#about to write, iclass 24, count 2 2006.285.11:48:20.49#ibcon#wrote, iclass 24, count 2 2006.285.11:48:20.49#ibcon#about to read 3, iclass 24, count 2 2006.285.11:48:20.52#ibcon#read 3, iclass 24, count 2 2006.285.11:48:20.52#ibcon#about to read 4, iclass 24, count 2 2006.285.11:48:20.52#ibcon#read 4, iclass 24, count 2 2006.285.11:48:20.52#ibcon#about to read 5, iclass 24, count 2 2006.285.11:48:20.52#ibcon#read 5, iclass 24, count 2 2006.285.11:48:20.52#ibcon#about to read 6, iclass 24, count 2 2006.285.11:48:20.52#ibcon#read 6, iclass 24, count 2 2006.285.11:48:20.52#ibcon#end of sib2, iclass 24, count 2 2006.285.11:48:20.52#ibcon#*after write, iclass 24, count 2 2006.285.11:48:20.52#ibcon#*before return 0, iclass 24, count 2 2006.285.11:48:20.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:48:20.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.11:48:20.52#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.11:48:20.52#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:20.52#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:48:20.64#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:48:20.64#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:48:20.64#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:48:20.64#ibcon#first serial, iclass 24, count 0 2006.285.11:48:20.64#ibcon#enter sib2, iclass 24, count 0 2006.285.11:48:20.64#ibcon#flushed, iclass 24, count 0 2006.285.11:48:20.64#ibcon#about to write, iclass 24, count 0 2006.285.11:48:20.64#ibcon#wrote, iclass 24, count 0 2006.285.11:48:20.64#ibcon#about to read 3, iclass 24, count 0 2006.285.11:48:20.66#ibcon#read 3, iclass 24, count 0 2006.285.11:48:20.66#ibcon#about to read 4, iclass 24, count 0 2006.285.11:48:20.66#ibcon#read 4, iclass 24, count 0 2006.285.11:48:20.66#ibcon#about to read 5, iclass 24, count 0 2006.285.11:48:20.66#ibcon#read 5, iclass 24, count 0 2006.285.11:48:20.66#ibcon#about to read 6, iclass 24, count 0 2006.285.11:48:20.66#ibcon#read 6, iclass 24, count 0 2006.285.11:48:20.66#ibcon#end of sib2, iclass 24, count 0 2006.285.11:48:20.66#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:48:20.66#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:48:20.66#ibcon#[25=USB\r\n] 2006.285.11:48:20.66#ibcon#*before write, iclass 24, count 0 2006.285.11:48:20.66#ibcon#enter sib2, iclass 24, count 0 2006.285.11:48:20.66#ibcon#flushed, iclass 24, count 0 2006.285.11:48:20.66#ibcon#about to write, iclass 24, count 0 2006.285.11:48:20.66#ibcon#wrote, iclass 24, count 0 2006.285.11:48:20.66#ibcon#about to read 3, iclass 24, count 0 2006.285.11:48:20.69#ibcon#read 3, iclass 24, count 0 2006.285.11:48:20.69#ibcon#about to read 4, iclass 24, count 0 2006.285.11:48:20.69#ibcon#read 4, iclass 24, count 0 2006.285.11:48:20.69#ibcon#about to read 5, iclass 24, count 0 2006.285.11:48:20.69#ibcon#read 5, iclass 24, count 0 2006.285.11:48:20.69#ibcon#about to read 6, iclass 24, count 0 2006.285.11:48:20.69#ibcon#read 6, iclass 24, count 0 2006.285.11:48:20.69#ibcon#end of sib2, iclass 24, count 0 2006.285.11:48:20.69#ibcon#*after write, iclass 24, count 0 2006.285.11:48:20.69#ibcon#*before return 0, iclass 24, count 0 2006.285.11:48:20.69#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:48:20.69#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.11:48:20.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:48:20.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:48:20.69$vck44/vblo=1,629.99 2006.285.11:48:20.70#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.11:48:20.70#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.11:48:20.70#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:20.70#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:48:20.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:48:20.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:48:20.70#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:48:20.70#ibcon#first serial, iclass 26, count 0 2006.285.11:48:20.70#ibcon#enter sib2, iclass 26, count 0 2006.285.11:48:20.70#ibcon#flushed, iclass 26, count 0 2006.285.11:48:20.70#ibcon#about to write, iclass 26, count 0 2006.285.11:48:20.70#ibcon#wrote, iclass 26, count 0 2006.285.11:48:20.70#ibcon#about to read 3, iclass 26, count 0 2006.285.11:48:20.71#ibcon#read 3, iclass 26, count 0 2006.285.11:48:20.71#ibcon#about to read 4, iclass 26, count 0 2006.285.11:48:20.71#ibcon#read 4, iclass 26, count 0 2006.285.11:48:20.71#ibcon#about to read 5, iclass 26, count 0 2006.285.11:48:20.71#ibcon#read 5, iclass 26, count 0 2006.285.11:48:20.71#ibcon#about to read 6, iclass 26, count 0 2006.285.11:48:20.71#ibcon#read 6, iclass 26, count 0 2006.285.11:48:20.71#ibcon#end of sib2, iclass 26, count 0 2006.285.11:48:20.71#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:48:20.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:48:20.71#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:48:20.71#ibcon#*before write, iclass 26, count 0 2006.285.11:48:20.71#ibcon#enter sib2, iclass 26, count 0 2006.285.11:48:20.71#ibcon#flushed, iclass 26, count 0 2006.285.11:48:20.71#ibcon#about to write, iclass 26, count 0 2006.285.11:48:20.71#ibcon#wrote, iclass 26, count 0 2006.285.11:48:20.71#ibcon#about to read 3, iclass 26, count 0 2006.285.11:48:20.75#ibcon#read 3, iclass 26, count 0 2006.285.11:48:20.75#ibcon#about to read 4, iclass 26, count 0 2006.285.11:48:20.75#ibcon#read 4, iclass 26, count 0 2006.285.11:48:20.75#ibcon#about to read 5, iclass 26, count 0 2006.285.11:48:20.75#ibcon#read 5, iclass 26, count 0 2006.285.11:48:20.75#ibcon#about to read 6, iclass 26, count 0 2006.285.11:48:20.75#ibcon#read 6, iclass 26, count 0 2006.285.11:48:20.75#ibcon#end of sib2, iclass 26, count 0 2006.285.11:48:20.75#ibcon#*after write, iclass 26, count 0 2006.285.11:48:20.75#ibcon#*before return 0, iclass 26, count 0 2006.285.11:48:20.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:48:20.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.11:48:20.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:48:20.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:48:20.75$vck44/vb=1,4 2006.285.11:48:20.76#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.11:48:20.76#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.11:48:20.76#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:20.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:48:20.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:48:20.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:48:20.76#ibcon#enter wrdev, iclass 28, count 2 2006.285.11:48:20.76#ibcon#first serial, iclass 28, count 2 2006.285.11:48:20.76#ibcon#enter sib2, iclass 28, count 2 2006.285.11:48:20.76#ibcon#flushed, iclass 28, count 2 2006.285.11:48:20.76#ibcon#about to write, iclass 28, count 2 2006.285.11:48:20.76#ibcon#wrote, iclass 28, count 2 2006.285.11:48:20.76#ibcon#about to read 3, iclass 28, count 2 2006.285.11:48:20.77#ibcon#read 3, iclass 28, count 2 2006.285.11:48:20.77#ibcon#about to read 4, iclass 28, count 2 2006.285.11:48:20.77#ibcon#read 4, iclass 28, count 2 2006.285.11:48:20.77#ibcon#about to read 5, iclass 28, count 2 2006.285.11:48:20.77#ibcon#read 5, iclass 28, count 2 2006.285.11:48:20.77#ibcon#about to read 6, iclass 28, count 2 2006.285.11:48:20.77#ibcon#read 6, iclass 28, count 2 2006.285.11:48:20.77#ibcon#end of sib2, iclass 28, count 2 2006.285.11:48:20.77#ibcon#*mode == 0, iclass 28, count 2 2006.285.11:48:20.77#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.11:48:20.77#ibcon#[27=AT01-04\r\n] 2006.285.11:48:20.77#ibcon#*before write, iclass 28, count 2 2006.285.11:48:20.77#ibcon#enter sib2, iclass 28, count 2 2006.285.11:48:20.77#ibcon#flushed, iclass 28, count 2 2006.285.11:48:20.77#ibcon#about to write, iclass 28, count 2 2006.285.11:48:20.77#ibcon#wrote, iclass 28, count 2 2006.285.11:48:20.77#ibcon#about to read 3, iclass 28, count 2 2006.285.11:48:20.80#ibcon#read 3, iclass 28, count 2 2006.285.11:48:20.80#ibcon#about to read 4, iclass 28, count 2 2006.285.11:48:20.80#ibcon#read 4, iclass 28, count 2 2006.285.11:48:20.80#ibcon#about to read 5, iclass 28, count 2 2006.285.11:48:20.80#ibcon#read 5, iclass 28, count 2 2006.285.11:48:20.80#ibcon#about to read 6, iclass 28, count 2 2006.285.11:48:20.80#ibcon#read 6, iclass 28, count 2 2006.285.11:48:20.80#ibcon#end of sib2, iclass 28, count 2 2006.285.11:48:20.80#ibcon#*after write, iclass 28, count 2 2006.285.11:48:20.80#ibcon#*before return 0, iclass 28, count 2 2006.285.11:48:20.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:48:20.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.11:48:20.80#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.11:48:20.80#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:20.80#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:48:20.92#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:48:20.92#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:48:20.92#ibcon#enter wrdev, iclass 28, count 0 2006.285.11:48:20.92#ibcon#first serial, iclass 28, count 0 2006.285.11:48:20.92#ibcon#enter sib2, iclass 28, count 0 2006.285.11:48:20.92#ibcon#flushed, iclass 28, count 0 2006.285.11:48:20.92#ibcon#about to write, iclass 28, count 0 2006.285.11:48:20.92#ibcon#wrote, iclass 28, count 0 2006.285.11:48:20.92#ibcon#about to read 3, iclass 28, count 0 2006.285.11:48:20.94#ibcon#read 3, iclass 28, count 0 2006.285.11:48:20.94#ibcon#about to read 4, iclass 28, count 0 2006.285.11:48:20.94#ibcon#read 4, iclass 28, count 0 2006.285.11:48:20.94#ibcon#about to read 5, iclass 28, count 0 2006.285.11:48:20.94#ibcon#read 5, iclass 28, count 0 2006.285.11:48:20.94#ibcon#about to read 6, iclass 28, count 0 2006.285.11:48:20.94#ibcon#read 6, iclass 28, count 0 2006.285.11:48:20.94#ibcon#end of sib2, iclass 28, count 0 2006.285.11:48:20.94#ibcon#*mode == 0, iclass 28, count 0 2006.285.11:48:20.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.11:48:20.94#ibcon#[27=USB\r\n] 2006.285.11:48:20.94#ibcon#*before write, iclass 28, count 0 2006.285.11:48:20.94#ibcon#enter sib2, iclass 28, count 0 2006.285.11:48:20.94#ibcon#flushed, iclass 28, count 0 2006.285.11:48:20.94#ibcon#about to write, iclass 28, count 0 2006.285.11:48:20.94#ibcon#wrote, iclass 28, count 0 2006.285.11:48:20.94#ibcon#about to read 3, iclass 28, count 0 2006.285.11:48:20.97#ibcon#read 3, iclass 28, count 0 2006.285.11:48:20.97#ibcon#about to read 4, iclass 28, count 0 2006.285.11:48:20.97#ibcon#read 4, iclass 28, count 0 2006.285.11:48:20.97#ibcon#about to read 5, iclass 28, count 0 2006.285.11:48:20.97#ibcon#read 5, iclass 28, count 0 2006.285.11:48:20.97#ibcon#about to read 6, iclass 28, count 0 2006.285.11:48:20.97#ibcon#read 6, iclass 28, count 0 2006.285.11:48:20.97#ibcon#end of sib2, iclass 28, count 0 2006.285.11:48:20.97#ibcon#*after write, iclass 28, count 0 2006.285.11:48:20.97#ibcon#*before return 0, iclass 28, count 0 2006.285.11:48:20.97#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:48:20.97#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.11:48:20.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.11:48:20.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.11:48:20.97$vck44/vblo=2,634.99 2006.285.11:48:20.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.11:48:20.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.11:48:20.98#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:20.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:48:20.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:48:20.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:48:20.98#ibcon#enter wrdev, iclass 30, count 0 2006.285.11:48:20.98#ibcon#first serial, iclass 30, count 0 2006.285.11:48:20.98#ibcon#enter sib2, iclass 30, count 0 2006.285.11:48:20.98#ibcon#flushed, iclass 30, count 0 2006.285.11:48:20.98#ibcon#about to write, iclass 30, count 0 2006.285.11:48:20.98#ibcon#wrote, iclass 30, count 0 2006.285.11:48:20.98#ibcon#about to read 3, iclass 30, count 0 2006.285.11:48:20.99#ibcon#read 3, iclass 30, count 0 2006.285.11:48:20.99#ibcon#about to read 4, iclass 30, count 0 2006.285.11:48:20.99#ibcon#read 4, iclass 30, count 0 2006.285.11:48:20.99#ibcon#about to read 5, iclass 30, count 0 2006.285.11:48:20.99#ibcon#read 5, iclass 30, count 0 2006.285.11:48:20.99#ibcon#about to read 6, iclass 30, count 0 2006.285.11:48:20.99#ibcon#read 6, iclass 30, count 0 2006.285.11:48:20.99#ibcon#end of sib2, iclass 30, count 0 2006.285.11:48:20.99#ibcon#*mode == 0, iclass 30, count 0 2006.285.11:48:20.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.11:48:20.99#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:48:20.99#ibcon#*before write, iclass 30, count 0 2006.285.11:48:20.99#ibcon#enter sib2, iclass 30, count 0 2006.285.11:48:20.99#ibcon#flushed, iclass 30, count 0 2006.285.11:48:20.99#ibcon#about to write, iclass 30, count 0 2006.285.11:48:20.99#ibcon#wrote, iclass 30, count 0 2006.285.11:48:20.99#ibcon#about to read 3, iclass 30, count 0 2006.285.11:48:21.03#ibcon#read 3, iclass 30, count 0 2006.285.11:48:21.03#ibcon#about to read 4, iclass 30, count 0 2006.285.11:48:21.03#ibcon#read 4, iclass 30, count 0 2006.285.11:48:21.03#ibcon#about to read 5, iclass 30, count 0 2006.285.11:48:21.03#ibcon#read 5, iclass 30, count 0 2006.285.11:48:21.03#ibcon#about to read 6, iclass 30, count 0 2006.285.11:48:21.03#ibcon#read 6, iclass 30, count 0 2006.285.11:48:21.03#ibcon#end of sib2, iclass 30, count 0 2006.285.11:48:21.03#ibcon#*after write, iclass 30, count 0 2006.285.11:48:21.03#ibcon#*before return 0, iclass 30, count 0 2006.285.11:48:21.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:48:21.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.11:48:21.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.11:48:21.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.11:48:21.03$vck44/vb=2,5 2006.285.11:48:21.04#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.11:48:21.04#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.11:48:21.04#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:21.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:48:21.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:48:21.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:48:21.08#ibcon#enter wrdev, iclass 32, count 2 2006.285.11:48:21.08#ibcon#first serial, iclass 32, count 2 2006.285.11:48:21.08#ibcon#enter sib2, iclass 32, count 2 2006.285.11:48:21.08#ibcon#flushed, iclass 32, count 2 2006.285.11:48:21.08#ibcon#about to write, iclass 32, count 2 2006.285.11:48:21.08#ibcon#wrote, iclass 32, count 2 2006.285.11:48:21.08#ibcon#about to read 3, iclass 32, count 2 2006.285.11:48:21.10#ibcon#read 3, iclass 32, count 2 2006.285.11:48:21.10#ibcon#about to read 4, iclass 32, count 2 2006.285.11:48:21.10#ibcon#read 4, iclass 32, count 2 2006.285.11:48:21.10#ibcon#about to read 5, iclass 32, count 2 2006.285.11:48:21.10#ibcon#read 5, iclass 32, count 2 2006.285.11:48:21.10#ibcon#about to read 6, iclass 32, count 2 2006.285.11:48:21.10#ibcon#read 6, iclass 32, count 2 2006.285.11:48:21.10#ibcon#end of sib2, iclass 32, count 2 2006.285.11:48:21.10#ibcon#*mode == 0, iclass 32, count 2 2006.285.11:48:21.10#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.11:48:21.10#ibcon#[27=AT02-05\r\n] 2006.285.11:48:21.10#ibcon#*before write, iclass 32, count 2 2006.285.11:48:21.10#ibcon#enter sib2, iclass 32, count 2 2006.285.11:48:21.10#ibcon#flushed, iclass 32, count 2 2006.285.11:48:21.10#ibcon#about to write, iclass 32, count 2 2006.285.11:48:21.10#ibcon#wrote, iclass 32, count 2 2006.285.11:48:21.10#ibcon#about to read 3, iclass 32, count 2 2006.285.11:48:21.13#ibcon#read 3, iclass 32, count 2 2006.285.11:48:21.13#ibcon#about to read 4, iclass 32, count 2 2006.285.11:48:21.13#ibcon#read 4, iclass 32, count 2 2006.285.11:48:21.13#ibcon#about to read 5, iclass 32, count 2 2006.285.11:48:21.13#ibcon#read 5, iclass 32, count 2 2006.285.11:48:21.13#ibcon#about to read 6, iclass 32, count 2 2006.285.11:48:21.13#ibcon#read 6, iclass 32, count 2 2006.285.11:48:21.13#ibcon#end of sib2, iclass 32, count 2 2006.285.11:48:21.13#ibcon#*after write, iclass 32, count 2 2006.285.11:48:21.13#ibcon#*before return 0, iclass 32, count 2 2006.285.11:48:21.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:48:21.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.11:48:21.13#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.11:48:21.13#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:21.13#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:48:21.25#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:48:21.25#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:48:21.25#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:48:21.25#ibcon#first serial, iclass 32, count 0 2006.285.11:48:21.25#ibcon#enter sib2, iclass 32, count 0 2006.285.11:48:21.25#ibcon#flushed, iclass 32, count 0 2006.285.11:48:21.25#ibcon#about to write, iclass 32, count 0 2006.285.11:48:21.25#ibcon#wrote, iclass 32, count 0 2006.285.11:48:21.25#ibcon#about to read 3, iclass 32, count 0 2006.285.11:48:21.27#ibcon#read 3, iclass 32, count 0 2006.285.11:48:21.27#ibcon#about to read 4, iclass 32, count 0 2006.285.11:48:21.27#ibcon#read 4, iclass 32, count 0 2006.285.11:48:21.27#ibcon#about to read 5, iclass 32, count 0 2006.285.11:48:21.27#ibcon#read 5, iclass 32, count 0 2006.285.11:48:21.27#ibcon#about to read 6, iclass 32, count 0 2006.285.11:48:21.27#ibcon#read 6, iclass 32, count 0 2006.285.11:48:21.27#ibcon#end of sib2, iclass 32, count 0 2006.285.11:48:21.27#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:48:21.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:48:21.27#ibcon#[27=USB\r\n] 2006.285.11:48:21.27#ibcon#*before write, iclass 32, count 0 2006.285.11:48:21.27#ibcon#enter sib2, iclass 32, count 0 2006.285.11:48:21.27#ibcon#flushed, iclass 32, count 0 2006.285.11:48:21.27#ibcon#about to write, iclass 32, count 0 2006.285.11:48:21.27#ibcon#wrote, iclass 32, count 0 2006.285.11:48:21.27#ibcon#about to read 3, iclass 32, count 0 2006.285.11:48:21.30#ibcon#read 3, iclass 32, count 0 2006.285.11:48:21.30#ibcon#about to read 4, iclass 32, count 0 2006.285.11:48:21.30#ibcon#read 4, iclass 32, count 0 2006.285.11:48:21.30#ibcon#about to read 5, iclass 32, count 0 2006.285.11:48:21.30#ibcon#read 5, iclass 32, count 0 2006.285.11:48:21.30#ibcon#about to read 6, iclass 32, count 0 2006.285.11:48:21.30#ibcon#read 6, iclass 32, count 0 2006.285.11:48:21.30#ibcon#end of sib2, iclass 32, count 0 2006.285.11:48:21.30#ibcon#*after write, iclass 32, count 0 2006.285.11:48:21.30#ibcon#*before return 0, iclass 32, count 0 2006.285.11:48:21.30#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:48:21.30#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.11:48:21.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:48:21.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:48:21.30$vck44/vblo=3,649.99 2006.285.11:48:21.31#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.11:48:21.31#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.11:48:21.31#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:21.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:48:21.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:48:21.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:48:21.31#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:48:21.31#ibcon#first serial, iclass 34, count 0 2006.285.11:48:21.31#ibcon#enter sib2, iclass 34, count 0 2006.285.11:48:21.31#ibcon#flushed, iclass 34, count 0 2006.285.11:48:21.31#ibcon#about to write, iclass 34, count 0 2006.285.11:48:21.31#ibcon#wrote, iclass 34, count 0 2006.285.11:48:21.31#ibcon#about to read 3, iclass 34, count 0 2006.285.11:48:21.32#ibcon#read 3, iclass 34, count 0 2006.285.11:48:21.32#ibcon#about to read 4, iclass 34, count 0 2006.285.11:48:21.32#ibcon#read 4, iclass 34, count 0 2006.285.11:48:21.32#ibcon#about to read 5, iclass 34, count 0 2006.285.11:48:21.32#ibcon#read 5, iclass 34, count 0 2006.285.11:48:21.32#ibcon#about to read 6, iclass 34, count 0 2006.285.11:48:21.32#ibcon#read 6, iclass 34, count 0 2006.285.11:48:21.32#ibcon#end of sib2, iclass 34, count 0 2006.285.11:48:21.32#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:48:21.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:48:21.32#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:48:21.32#ibcon#*before write, iclass 34, count 0 2006.285.11:48:21.32#ibcon#enter sib2, iclass 34, count 0 2006.285.11:48:21.32#ibcon#flushed, iclass 34, count 0 2006.285.11:48:21.32#ibcon#about to write, iclass 34, count 0 2006.285.11:48:21.32#ibcon#wrote, iclass 34, count 0 2006.285.11:48:21.32#ibcon#about to read 3, iclass 34, count 0 2006.285.11:48:21.36#ibcon#read 3, iclass 34, count 0 2006.285.11:48:21.36#ibcon#about to read 4, iclass 34, count 0 2006.285.11:48:21.36#ibcon#read 4, iclass 34, count 0 2006.285.11:48:21.36#ibcon#about to read 5, iclass 34, count 0 2006.285.11:48:21.36#ibcon#read 5, iclass 34, count 0 2006.285.11:48:21.36#ibcon#about to read 6, iclass 34, count 0 2006.285.11:48:21.36#ibcon#read 6, iclass 34, count 0 2006.285.11:48:21.36#ibcon#end of sib2, iclass 34, count 0 2006.285.11:48:21.36#ibcon#*after write, iclass 34, count 0 2006.285.11:48:21.36#ibcon#*before return 0, iclass 34, count 0 2006.285.11:48:21.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:48:21.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.11:48:21.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:48:21.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:48:21.37$vck44/vb=3,4 2006.285.11:48:21.37#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.11:48:21.37#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.11:48:21.37#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:21.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:48:21.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:48:21.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:48:21.41#ibcon#enter wrdev, iclass 36, count 2 2006.285.11:48:21.41#ibcon#first serial, iclass 36, count 2 2006.285.11:48:21.41#ibcon#enter sib2, iclass 36, count 2 2006.285.11:48:21.41#ibcon#flushed, iclass 36, count 2 2006.285.11:48:21.41#ibcon#about to write, iclass 36, count 2 2006.285.11:48:21.41#ibcon#wrote, iclass 36, count 2 2006.285.11:48:21.41#ibcon#about to read 3, iclass 36, count 2 2006.285.11:48:21.43#ibcon#read 3, iclass 36, count 2 2006.285.11:48:21.43#ibcon#about to read 4, iclass 36, count 2 2006.285.11:48:21.43#ibcon#read 4, iclass 36, count 2 2006.285.11:48:21.43#ibcon#about to read 5, iclass 36, count 2 2006.285.11:48:21.43#ibcon#read 5, iclass 36, count 2 2006.285.11:48:21.43#ibcon#about to read 6, iclass 36, count 2 2006.285.11:48:21.43#ibcon#read 6, iclass 36, count 2 2006.285.11:48:21.43#ibcon#end of sib2, iclass 36, count 2 2006.285.11:48:21.43#ibcon#*mode == 0, iclass 36, count 2 2006.285.11:48:21.43#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.11:48:21.43#ibcon#[27=AT03-04\r\n] 2006.285.11:48:21.43#ibcon#*before write, iclass 36, count 2 2006.285.11:48:21.43#ibcon#enter sib2, iclass 36, count 2 2006.285.11:48:21.43#ibcon#flushed, iclass 36, count 2 2006.285.11:48:21.43#ibcon#about to write, iclass 36, count 2 2006.285.11:48:21.43#ibcon#wrote, iclass 36, count 2 2006.285.11:48:21.43#ibcon#about to read 3, iclass 36, count 2 2006.285.11:48:21.46#ibcon#read 3, iclass 36, count 2 2006.285.11:48:21.46#ibcon#about to read 4, iclass 36, count 2 2006.285.11:48:21.46#ibcon#read 4, iclass 36, count 2 2006.285.11:48:21.46#ibcon#about to read 5, iclass 36, count 2 2006.285.11:48:21.46#ibcon#read 5, iclass 36, count 2 2006.285.11:48:21.46#ibcon#about to read 6, iclass 36, count 2 2006.285.11:48:21.46#ibcon#read 6, iclass 36, count 2 2006.285.11:48:21.46#ibcon#end of sib2, iclass 36, count 2 2006.285.11:48:21.46#ibcon#*after write, iclass 36, count 2 2006.285.11:48:21.46#ibcon#*before return 0, iclass 36, count 2 2006.285.11:48:21.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:48:21.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.11:48:21.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.11:48:21.46#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:21.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:48:21.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:48:21.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:48:21.58#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:48:21.58#ibcon#first serial, iclass 36, count 0 2006.285.11:48:21.58#ibcon#enter sib2, iclass 36, count 0 2006.285.11:48:21.58#ibcon#flushed, iclass 36, count 0 2006.285.11:48:21.58#ibcon#about to write, iclass 36, count 0 2006.285.11:48:21.58#ibcon#wrote, iclass 36, count 0 2006.285.11:48:21.58#ibcon#about to read 3, iclass 36, count 0 2006.285.11:48:21.60#ibcon#read 3, iclass 36, count 0 2006.285.11:48:21.60#ibcon#about to read 4, iclass 36, count 0 2006.285.11:48:21.60#ibcon#read 4, iclass 36, count 0 2006.285.11:48:21.60#ibcon#about to read 5, iclass 36, count 0 2006.285.11:48:21.60#ibcon#read 5, iclass 36, count 0 2006.285.11:48:21.60#ibcon#about to read 6, iclass 36, count 0 2006.285.11:48:21.60#ibcon#read 6, iclass 36, count 0 2006.285.11:48:21.60#ibcon#end of sib2, iclass 36, count 0 2006.285.11:48:21.60#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:48:21.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:48:21.60#ibcon#[27=USB\r\n] 2006.285.11:48:21.60#ibcon#*before write, iclass 36, count 0 2006.285.11:48:21.60#ibcon#enter sib2, iclass 36, count 0 2006.285.11:48:21.60#ibcon#flushed, iclass 36, count 0 2006.285.11:48:21.60#ibcon#about to write, iclass 36, count 0 2006.285.11:48:21.60#ibcon#wrote, iclass 36, count 0 2006.285.11:48:21.60#ibcon#about to read 3, iclass 36, count 0 2006.285.11:48:21.63#ibcon#read 3, iclass 36, count 0 2006.285.11:48:21.63#ibcon#about to read 4, iclass 36, count 0 2006.285.11:48:21.63#ibcon#read 4, iclass 36, count 0 2006.285.11:48:21.63#ibcon#about to read 5, iclass 36, count 0 2006.285.11:48:21.63#ibcon#read 5, iclass 36, count 0 2006.285.11:48:21.63#ibcon#about to read 6, iclass 36, count 0 2006.285.11:48:21.63#ibcon#read 6, iclass 36, count 0 2006.285.11:48:21.63#ibcon#end of sib2, iclass 36, count 0 2006.285.11:48:21.63#ibcon#*after write, iclass 36, count 0 2006.285.11:48:21.63#ibcon#*before return 0, iclass 36, count 0 2006.285.11:48:21.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:48:21.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.11:48:21.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:48:21.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:48:21.63$vck44/vblo=4,679.99 2006.285.11:48:21.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.11:48:21.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.11:48:21.64#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:21.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:48:21.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:48:21.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:48:21.64#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:48:21.64#ibcon#first serial, iclass 38, count 0 2006.285.11:48:21.64#ibcon#enter sib2, iclass 38, count 0 2006.285.11:48:21.64#ibcon#flushed, iclass 38, count 0 2006.285.11:48:21.64#ibcon#about to write, iclass 38, count 0 2006.285.11:48:21.64#ibcon#wrote, iclass 38, count 0 2006.285.11:48:21.64#ibcon#about to read 3, iclass 38, count 0 2006.285.11:48:21.65#ibcon#read 3, iclass 38, count 0 2006.285.11:48:21.65#ibcon#about to read 4, iclass 38, count 0 2006.285.11:48:21.65#ibcon#read 4, iclass 38, count 0 2006.285.11:48:21.65#ibcon#about to read 5, iclass 38, count 0 2006.285.11:48:21.65#ibcon#read 5, iclass 38, count 0 2006.285.11:48:21.65#ibcon#about to read 6, iclass 38, count 0 2006.285.11:48:21.65#ibcon#read 6, iclass 38, count 0 2006.285.11:48:21.65#ibcon#end of sib2, iclass 38, count 0 2006.285.11:48:21.65#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:48:21.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:48:21.65#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:48:21.65#ibcon#*before write, iclass 38, count 0 2006.285.11:48:21.65#ibcon#enter sib2, iclass 38, count 0 2006.285.11:48:21.65#ibcon#flushed, iclass 38, count 0 2006.285.11:48:21.65#ibcon#about to write, iclass 38, count 0 2006.285.11:48:21.65#ibcon#wrote, iclass 38, count 0 2006.285.11:48:21.65#ibcon#about to read 3, iclass 38, count 0 2006.285.11:48:21.69#ibcon#read 3, iclass 38, count 0 2006.285.11:48:21.69#ibcon#about to read 4, iclass 38, count 0 2006.285.11:48:21.69#ibcon#read 4, iclass 38, count 0 2006.285.11:48:21.69#ibcon#about to read 5, iclass 38, count 0 2006.285.11:48:21.69#ibcon#read 5, iclass 38, count 0 2006.285.11:48:21.69#ibcon#about to read 6, iclass 38, count 0 2006.285.11:48:21.69#ibcon#read 6, iclass 38, count 0 2006.285.11:48:21.69#ibcon#end of sib2, iclass 38, count 0 2006.285.11:48:21.69#ibcon#*after write, iclass 38, count 0 2006.285.11:48:21.69#ibcon#*before return 0, iclass 38, count 0 2006.285.11:48:21.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:48:21.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.11:48:21.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:48:21.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:48:21.69$vck44/vb=4,5 2006.285.11:48:21.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.11:48:21.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.11:48:21.70#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:21.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:48:21.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:48:21.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:48:21.74#ibcon#enter wrdev, iclass 40, count 2 2006.285.11:48:21.74#ibcon#first serial, iclass 40, count 2 2006.285.11:48:21.74#ibcon#enter sib2, iclass 40, count 2 2006.285.11:48:21.74#ibcon#flushed, iclass 40, count 2 2006.285.11:48:21.74#ibcon#about to write, iclass 40, count 2 2006.285.11:48:21.74#ibcon#wrote, iclass 40, count 2 2006.285.11:48:21.74#ibcon#about to read 3, iclass 40, count 2 2006.285.11:48:21.76#ibcon#read 3, iclass 40, count 2 2006.285.11:48:21.76#ibcon#about to read 4, iclass 40, count 2 2006.285.11:48:21.76#ibcon#read 4, iclass 40, count 2 2006.285.11:48:21.76#ibcon#about to read 5, iclass 40, count 2 2006.285.11:48:21.76#ibcon#read 5, iclass 40, count 2 2006.285.11:48:21.76#ibcon#about to read 6, iclass 40, count 2 2006.285.11:48:21.76#ibcon#read 6, iclass 40, count 2 2006.285.11:48:21.76#ibcon#end of sib2, iclass 40, count 2 2006.285.11:48:21.76#ibcon#*mode == 0, iclass 40, count 2 2006.285.11:48:21.76#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.11:48:21.76#ibcon#[27=AT04-05\r\n] 2006.285.11:48:21.76#ibcon#*before write, iclass 40, count 2 2006.285.11:48:21.76#ibcon#enter sib2, iclass 40, count 2 2006.285.11:48:21.76#ibcon#flushed, iclass 40, count 2 2006.285.11:48:21.76#ibcon#about to write, iclass 40, count 2 2006.285.11:48:21.76#ibcon#wrote, iclass 40, count 2 2006.285.11:48:21.76#ibcon#about to read 3, iclass 40, count 2 2006.285.11:48:21.79#ibcon#read 3, iclass 40, count 2 2006.285.11:48:21.79#ibcon#about to read 4, iclass 40, count 2 2006.285.11:48:21.79#ibcon#read 4, iclass 40, count 2 2006.285.11:48:21.79#ibcon#about to read 5, iclass 40, count 2 2006.285.11:48:21.79#ibcon#read 5, iclass 40, count 2 2006.285.11:48:21.79#ibcon#about to read 6, iclass 40, count 2 2006.285.11:48:21.79#ibcon#read 6, iclass 40, count 2 2006.285.11:48:21.79#ibcon#end of sib2, iclass 40, count 2 2006.285.11:48:21.79#ibcon#*after write, iclass 40, count 2 2006.285.11:48:21.79#ibcon#*before return 0, iclass 40, count 2 2006.285.11:48:21.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:48:21.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.11:48:21.79#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.11:48:21.79#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:21.79#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:48:21.91#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:48:21.91#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:48:21.91#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:48:21.91#ibcon#first serial, iclass 40, count 0 2006.285.11:48:21.91#ibcon#enter sib2, iclass 40, count 0 2006.285.11:48:21.91#ibcon#flushed, iclass 40, count 0 2006.285.11:48:21.91#ibcon#about to write, iclass 40, count 0 2006.285.11:48:21.91#ibcon#wrote, iclass 40, count 0 2006.285.11:48:21.91#ibcon#about to read 3, iclass 40, count 0 2006.285.11:48:21.93#ibcon#read 3, iclass 40, count 0 2006.285.11:48:21.93#ibcon#about to read 4, iclass 40, count 0 2006.285.11:48:21.93#ibcon#read 4, iclass 40, count 0 2006.285.11:48:21.93#ibcon#about to read 5, iclass 40, count 0 2006.285.11:48:21.93#ibcon#read 5, iclass 40, count 0 2006.285.11:48:21.93#ibcon#about to read 6, iclass 40, count 0 2006.285.11:48:21.93#ibcon#read 6, iclass 40, count 0 2006.285.11:48:21.93#ibcon#end of sib2, iclass 40, count 0 2006.285.11:48:21.93#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:48:21.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:48:21.93#ibcon#[27=USB\r\n] 2006.285.11:48:21.93#ibcon#*before write, iclass 40, count 0 2006.285.11:48:21.93#ibcon#enter sib2, iclass 40, count 0 2006.285.11:48:21.93#ibcon#flushed, iclass 40, count 0 2006.285.11:48:21.93#ibcon#about to write, iclass 40, count 0 2006.285.11:48:21.93#ibcon#wrote, iclass 40, count 0 2006.285.11:48:21.93#ibcon#about to read 3, iclass 40, count 0 2006.285.11:48:21.96#ibcon#read 3, iclass 40, count 0 2006.285.11:48:21.96#ibcon#about to read 4, iclass 40, count 0 2006.285.11:48:21.96#ibcon#read 4, iclass 40, count 0 2006.285.11:48:21.96#ibcon#about to read 5, iclass 40, count 0 2006.285.11:48:21.96#ibcon#read 5, iclass 40, count 0 2006.285.11:48:21.96#ibcon#about to read 6, iclass 40, count 0 2006.285.11:48:21.96#ibcon#read 6, iclass 40, count 0 2006.285.11:48:21.96#ibcon#end of sib2, iclass 40, count 0 2006.285.11:48:21.96#ibcon#*after write, iclass 40, count 0 2006.285.11:48:21.96#ibcon#*before return 0, iclass 40, count 0 2006.285.11:48:21.96#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:48:21.96#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.11:48:21.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:48:21.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:48:21.96$vck44/vblo=5,709.99 2006.285.11:48:21.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.11:48:21.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.11:48:21.97#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:21.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:48:21.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:48:21.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:48:21.97#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:48:21.97#ibcon#first serial, iclass 4, count 0 2006.285.11:48:21.97#ibcon#enter sib2, iclass 4, count 0 2006.285.11:48:21.97#ibcon#flushed, iclass 4, count 0 2006.285.11:48:21.97#ibcon#about to write, iclass 4, count 0 2006.285.11:48:21.97#ibcon#wrote, iclass 4, count 0 2006.285.11:48:21.97#ibcon#about to read 3, iclass 4, count 0 2006.285.11:48:21.98#ibcon#read 3, iclass 4, count 0 2006.285.11:48:21.98#ibcon#about to read 4, iclass 4, count 0 2006.285.11:48:21.98#ibcon#read 4, iclass 4, count 0 2006.285.11:48:21.98#ibcon#about to read 5, iclass 4, count 0 2006.285.11:48:21.98#ibcon#read 5, iclass 4, count 0 2006.285.11:48:21.98#ibcon#about to read 6, iclass 4, count 0 2006.285.11:48:21.98#ibcon#read 6, iclass 4, count 0 2006.285.11:48:21.98#ibcon#end of sib2, iclass 4, count 0 2006.285.11:48:21.98#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:48:21.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:48:21.98#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:48:21.98#ibcon#*before write, iclass 4, count 0 2006.285.11:48:21.98#ibcon#enter sib2, iclass 4, count 0 2006.285.11:48:21.98#ibcon#flushed, iclass 4, count 0 2006.285.11:48:21.98#ibcon#about to write, iclass 4, count 0 2006.285.11:48:21.98#ibcon#wrote, iclass 4, count 0 2006.285.11:48:21.98#ibcon#about to read 3, iclass 4, count 0 2006.285.11:48:22.02#ibcon#read 3, iclass 4, count 0 2006.285.11:48:22.02#ibcon#about to read 4, iclass 4, count 0 2006.285.11:48:22.02#ibcon#read 4, iclass 4, count 0 2006.285.11:48:22.02#ibcon#about to read 5, iclass 4, count 0 2006.285.11:48:22.02#ibcon#read 5, iclass 4, count 0 2006.285.11:48:22.02#ibcon#about to read 6, iclass 4, count 0 2006.285.11:48:22.02#ibcon#read 6, iclass 4, count 0 2006.285.11:48:22.02#ibcon#end of sib2, iclass 4, count 0 2006.285.11:48:22.02#ibcon#*after write, iclass 4, count 0 2006.285.11:48:22.02#ibcon#*before return 0, iclass 4, count 0 2006.285.11:48:22.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:48:22.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.11:48:22.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:48:22.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:48:22.02$vck44/vb=5,4 2006.285.11:48:22.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.11:48:22.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.11:48:22.03#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:22.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:48:22.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:48:22.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:48:22.07#ibcon#enter wrdev, iclass 6, count 2 2006.285.11:48:22.07#ibcon#first serial, iclass 6, count 2 2006.285.11:48:22.07#ibcon#enter sib2, iclass 6, count 2 2006.285.11:48:22.07#ibcon#flushed, iclass 6, count 2 2006.285.11:48:22.07#ibcon#about to write, iclass 6, count 2 2006.285.11:48:22.07#ibcon#wrote, iclass 6, count 2 2006.285.11:48:22.07#ibcon#about to read 3, iclass 6, count 2 2006.285.11:48:22.09#ibcon#read 3, iclass 6, count 2 2006.285.11:48:22.09#ibcon#about to read 4, iclass 6, count 2 2006.285.11:48:22.09#ibcon#read 4, iclass 6, count 2 2006.285.11:48:22.09#ibcon#about to read 5, iclass 6, count 2 2006.285.11:48:22.09#ibcon#read 5, iclass 6, count 2 2006.285.11:48:22.09#ibcon#about to read 6, iclass 6, count 2 2006.285.11:48:22.09#ibcon#read 6, iclass 6, count 2 2006.285.11:48:22.09#ibcon#end of sib2, iclass 6, count 2 2006.285.11:48:22.09#ibcon#*mode == 0, iclass 6, count 2 2006.285.11:48:22.09#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.11:48:22.09#ibcon#[27=AT05-04\r\n] 2006.285.11:48:22.09#ibcon#*before write, iclass 6, count 2 2006.285.11:48:22.09#ibcon#enter sib2, iclass 6, count 2 2006.285.11:48:22.09#ibcon#flushed, iclass 6, count 2 2006.285.11:48:22.09#ibcon#about to write, iclass 6, count 2 2006.285.11:48:22.09#ibcon#wrote, iclass 6, count 2 2006.285.11:48:22.09#ibcon#about to read 3, iclass 6, count 2 2006.285.11:48:22.12#ibcon#read 3, iclass 6, count 2 2006.285.11:48:22.12#ibcon#about to read 4, iclass 6, count 2 2006.285.11:48:22.12#ibcon#read 4, iclass 6, count 2 2006.285.11:48:22.12#ibcon#about to read 5, iclass 6, count 2 2006.285.11:48:22.12#ibcon#read 5, iclass 6, count 2 2006.285.11:48:22.12#ibcon#about to read 6, iclass 6, count 2 2006.285.11:48:22.12#ibcon#read 6, iclass 6, count 2 2006.285.11:48:22.12#ibcon#end of sib2, iclass 6, count 2 2006.285.11:48:22.12#ibcon#*after write, iclass 6, count 2 2006.285.11:48:22.12#ibcon#*before return 0, iclass 6, count 2 2006.285.11:48:22.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:48:22.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.11:48:22.12#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.11:48:22.12#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:22.12#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:48:22.24#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:48:22.24#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:48:22.24#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:48:22.24#ibcon#first serial, iclass 6, count 0 2006.285.11:48:22.24#ibcon#enter sib2, iclass 6, count 0 2006.285.11:48:22.24#ibcon#flushed, iclass 6, count 0 2006.285.11:48:22.24#ibcon#about to write, iclass 6, count 0 2006.285.11:48:22.24#ibcon#wrote, iclass 6, count 0 2006.285.11:48:22.24#ibcon#about to read 3, iclass 6, count 0 2006.285.11:48:22.26#ibcon#read 3, iclass 6, count 0 2006.285.11:48:22.26#ibcon#about to read 4, iclass 6, count 0 2006.285.11:48:22.26#ibcon#read 4, iclass 6, count 0 2006.285.11:48:22.26#ibcon#about to read 5, iclass 6, count 0 2006.285.11:48:22.26#ibcon#read 5, iclass 6, count 0 2006.285.11:48:22.26#ibcon#about to read 6, iclass 6, count 0 2006.285.11:48:22.26#ibcon#read 6, iclass 6, count 0 2006.285.11:48:22.26#ibcon#end of sib2, iclass 6, count 0 2006.285.11:48:22.26#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:48:22.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:48:22.26#ibcon#[27=USB\r\n] 2006.285.11:48:22.26#ibcon#*before write, iclass 6, count 0 2006.285.11:48:22.26#ibcon#enter sib2, iclass 6, count 0 2006.285.11:48:22.26#ibcon#flushed, iclass 6, count 0 2006.285.11:48:22.26#ibcon#about to write, iclass 6, count 0 2006.285.11:48:22.26#ibcon#wrote, iclass 6, count 0 2006.285.11:48:22.26#ibcon#about to read 3, iclass 6, count 0 2006.285.11:48:22.29#ibcon#read 3, iclass 6, count 0 2006.285.11:48:22.29#ibcon#about to read 4, iclass 6, count 0 2006.285.11:48:22.29#ibcon#read 4, iclass 6, count 0 2006.285.11:48:22.29#ibcon#about to read 5, iclass 6, count 0 2006.285.11:48:22.29#ibcon#read 5, iclass 6, count 0 2006.285.11:48:22.29#ibcon#about to read 6, iclass 6, count 0 2006.285.11:48:22.29#ibcon#read 6, iclass 6, count 0 2006.285.11:48:22.29#ibcon#end of sib2, iclass 6, count 0 2006.285.11:48:22.29#ibcon#*after write, iclass 6, count 0 2006.285.11:48:22.29#ibcon#*before return 0, iclass 6, count 0 2006.285.11:48:22.29#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:48:22.29#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.11:48:22.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:48:22.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:48:22.29$vck44/vblo=6,719.99 2006.285.11:48:22.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.11:48:22.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.11:48:22.30#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:22.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:48:22.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:48:22.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:48:22.30#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:48:22.30#ibcon#first serial, iclass 10, count 0 2006.285.11:48:22.30#ibcon#enter sib2, iclass 10, count 0 2006.285.11:48:22.30#ibcon#flushed, iclass 10, count 0 2006.285.11:48:22.30#ibcon#about to write, iclass 10, count 0 2006.285.11:48:22.30#ibcon#wrote, iclass 10, count 0 2006.285.11:48:22.30#ibcon#about to read 3, iclass 10, count 0 2006.285.11:48:22.31#ibcon#read 3, iclass 10, count 0 2006.285.11:48:22.31#ibcon#about to read 4, iclass 10, count 0 2006.285.11:48:22.31#ibcon#read 4, iclass 10, count 0 2006.285.11:48:22.31#ibcon#about to read 5, iclass 10, count 0 2006.285.11:48:22.31#ibcon#read 5, iclass 10, count 0 2006.285.11:48:22.31#ibcon#about to read 6, iclass 10, count 0 2006.285.11:48:22.31#ibcon#read 6, iclass 10, count 0 2006.285.11:48:22.31#ibcon#end of sib2, iclass 10, count 0 2006.285.11:48:22.31#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:48:22.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:48:22.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:48:22.31#ibcon#*before write, iclass 10, count 0 2006.285.11:48:22.31#ibcon#enter sib2, iclass 10, count 0 2006.285.11:48:22.31#ibcon#flushed, iclass 10, count 0 2006.285.11:48:22.31#ibcon#about to write, iclass 10, count 0 2006.285.11:48:22.31#ibcon#wrote, iclass 10, count 0 2006.285.11:48:22.31#ibcon#about to read 3, iclass 10, count 0 2006.285.11:48:22.35#ibcon#read 3, iclass 10, count 0 2006.285.11:48:22.35#ibcon#about to read 4, iclass 10, count 0 2006.285.11:48:22.35#ibcon#read 4, iclass 10, count 0 2006.285.11:48:22.35#ibcon#about to read 5, iclass 10, count 0 2006.285.11:48:22.35#ibcon#read 5, iclass 10, count 0 2006.285.11:48:22.35#ibcon#about to read 6, iclass 10, count 0 2006.285.11:48:22.35#ibcon#read 6, iclass 10, count 0 2006.285.11:48:22.35#ibcon#end of sib2, iclass 10, count 0 2006.285.11:48:22.35#ibcon#*after write, iclass 10, count 0 2006.285.11:48:22.35#ibcon#*before return 0, iclass 10, count 0 2006.285.11:48:22.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:48:22.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.11:48:22.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:48:22.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:48:22.35$vck44/vb=6,3 2006.285.11:48:22.36#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.11:48:22.36#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.11:48:22.36#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:22.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:48:22.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:48:22.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:48:22.40#ibcon#enter wrdev, iclass 12, count 2 2006.285.11:48:22.40#ibcon#first serial, iclass 12, count 2 2006.285.11:48:22.40#ibcon#enter sib2, iclass 12, count 2 2006.285.11:48:22.40#ibcon#flushed, iclass 12, count 2 2006.285.11:48:22.40#ibcon#about to write, iclass 12, count 2 2006.285.11:48:22.40#ibcon#wrote, iclass 12, count 2 2006.285.11:48:22.40#ibcon#about to read 3, iclass 12, count 2 2006.285.11:48:22.42#ibcon#read 3, iclass 12, count 2 2006.285.11:48:22.42#ibcon#about to read 4, iclass 12, count 2 2006.285.11:48:22.42#ibcon#read 4, iclass 12, count 2 2006.285.11:48:22.42#ibcon#about to read 5, iclass 12, count 2 2006.285.11:48:22.42#ibcon#read 5, iclass 12, count 2 2006.285.11:48:22.42#ibcon#about to read 6, iclass 12, count 2 2006.285.11:48:22.42#ibcon#read 6, iclass 12, count 2 2006.285.11:48:22.42#ibcon#end of sib2, iclass 12, count 2 2006.285.11:48:22.42#ibcon#*mode == 0, iclass 12, count 2 2006.285.11:48:22.42#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.11:48:22.42#ibcon#[27=AT06-03\r\n] 2006.285.11:48:22.42#ibcon#*before write, iclass 12, count 2 2006.285.11:48:22.42#ibcon#enter sib2, iclass 12, count 2 2006.285.11:48:22.42#ibcon#flushed, iclass 12, count 2 2006.285.11:48:22.42#ibcon#about to write, iclass 12, count 2 2006.285.11:48:22.42#ibcon#wrote, iclass 12, count 2 2006.285.11:48:22.42#ibcon#about to read 3, iclass 12, count 2 2006.285.11:48:22.45#ibcon#read 3, iclass 12, count 2 2006.285.11:48:22.45#ibcon#about to read 4, iclass 12, count 2 2006.285.11:48:22.45#ibcon#read 4, iclass 12, count 2 2006.285.11:48:22.45#ibcon#about to read 5, iclass 12, count 2 2006.285.11:48:22.45#ibcon#read 5, iclass 12, count 2 2006.285.11:48:22.45#ibcon#about to read 6, iclass 12, count 2 2006.285.11:48:22.45#ibcon#read 6, iclass 12, count 2 2006.285.11:48:22.45#ibcon#end of sib2, iclass 12, count 2 2006.285.11:48:22.45#ibcon#*after write, iclass 12, count 2 2006.285.11:48:22.45#ibcon#*before return 0, iclass 12, count 2 2006.285.11:48:22.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:48:22.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.11:48:22.45#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.11:48:22.45#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:22.45#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:48:22.57#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:48:22.57#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:48:22.57#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:48:22.57#ibcon#first serial, iclass 12, count 0 2006.285.11:48:22.57#ibcon#enter sib2, iclass 12, count 0 2006.285.11:48:22.57#ibcon#flushed, iclass 12, count 0 2006.285.11:48:22.57#ibcon#about to write, iclass 12, count 0 2006.285.11:48:22.57#ibcon#wrote, iclass 12, count 0 2006.285.11:48:22.57#ibcon#about to read 3, iclass 12, count 0 2006.285.11:48:22.59#ibcon#read 3, iclass 12, count 0 2006.285.11:48:22.59#ibcon#about to read 4, iclass 12, count 0 2006.285.11:48:22.59#ibcon#read 4, iclass 12, count 0 2006.285.11:48:22.59#ibcon#about to read 5, iclass 12, count 0 2006.285.11:48:22.59#ibcon#read 5, iclass 12, count 0 2006.285.11:48:22.59#ibcon#about to read 6, iclass 12, count 0 2006.285.11:48:22.59#ibcon#read 6, iclass 12, count 0 2006.285.11:48:22.59#ibcon#end of sib2, iclass 12, count 0 2006.285.11:48:22.59#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:48:22.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:48:22.59#ibcon#[27=USB\r\n] 2006.285.11:48:22.59#ibcon#*before write, iclass 12, count 0 2006.285.11:48:22.59#ibcon#enter sib2, iclass 12, count 0 2006.285.11:48:22.59#ibcon#flushed, iclass 12, count 0 2006.285.11:48:22.59#ibcon#about to write, iclass 12, count 0 2006.285.11:48:22.59#ibcon#wrote, iclass 12, count 0 2006.285.11:48:22.59#ibcon#about to read 3, iclass 12, count 0 2006.285.11:48:22.62#ibcon#read 3, iclass 12, count 0 2006.285.11:48:22.62#ibcon#about to read 4, iclass 12, count 0 2006.285.11:48:22.62#ibcon#read 4, iclass 12, count 0 2006.285.11:48:22.62#ibcon#about to read 5, iclass 12, count 0 2006.285.11:48:22.62#ibcon#read 5, iclass 12, count 0 2006.285.11:48:22.62#ibcon#about to read 6, iclass 12, count 0 2006.285.11:48:22.62#ibcon#read 6, iclass 12, count 0 2006.285.11:48:22.62#ibcon#end of sib2, iclass 12, count 0 2006.285.11:48:22.62#ibcon#*after write, iclass 12, count 0 2006.285.11:48:22.62#ibcon#*before return 0, iclass 12, count 0 2006.285.11:48:22.62#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:48:22.62#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.11:48:22.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:48:22.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:48:22.62$vck44/vblo=7,734.99 2006.285.11:48:22.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.11:48:22.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.11:48:22.63#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:22.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:48:22.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:48:22.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:48:22.63#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:48:22.63#ibcon#first serial, iclass 14, count 0 2006.285.11:48:22.63#ibcon#enter sib2, iclass 14, count 0 2006.285.11:48:22.63#ibcon#flushed, iclass 14, count 0 2006.285.11:48:22.63#ibcon#about to write, iclass 14, count 0 2006.285.11:48:22.63#ibcon#wrote, iclass 14, count 0 2006.285.11:48:22.63#ibcon#about to read 3, iclass 14, count 0 2006.285.11:48:22.64#ibcon#read 3, iclass 14, count 0 2006.285.11:48:22.64#ibcon#about to read 4, iclass 14, count 0 2006.285.11:48:22.64#ibcon#read 4, iclass 14, count 0 2006.285.11:48:22.64#ibcon#about to read 5, iclass 14, count 0 2006.285.11:48:22.64#ibcon#read 5, iclass 14, count 0 2006.285.11:48:22.64#ibcon#about to read 6, iclass 14, count 0 2006.285.11:48:22.64#ibcon#read 6, iclass 14, count 0 2006.285.11:48:22.64#ibcon#end of sib2, iclass 14, count 0 2006.285.11:48:22.64#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:48:22.64#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:48:22.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:48:22.64#ibcon#*before write, iclass 14, count 0 2006.285.11:48:22.64#ibcon#enter sib2, iclass 14, count 0 2006.285.11:48:22.64#ibcon#flushed, iclass 14, count 0 2006.285.11:48:22.64#ibcon#about to write, iclass 14, count 0 2006.285.11:48:22.64#ibcon#wrote, iclass 14, count 0 2006.285.11:48:22.64#ibcon#about to read 3, iclass 14, count 0 2006.285.11:48:22.68#ibcon#read 3, iclass 14, count 0 2006.285.11:48:22.68#ibcon#about to read 4, iclass 14, count 0 2006.285.11:48:22.68#ibcon#read 4, iclass 14, count 0 2006.285.11:48:22.68#ibcon#about to read 5, iclass 14, count 0 2006.285.11:48:22.68#ibcon#read 5, iclass 14, count 0 2006.285.11:48:22.68#ibcon#about to read 6, iclass 14, count 0 2006.285.11:48:22.68#ibcon#read 6, iclass 14, count 0 2006.285.11:48:22.68#ibcon#end of sib2, iclass 14, count 0 2006.285.11:48:22.68#ibcon#*after write, iclass 14, count 0 2006.285.11:48:22.68#ibcon#*before return 0, iclass 14, count 0 2006.285.11:48:22.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:48:22.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:48:22.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:48:22.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:48:22.68$vck44/vb=7,4 2006.285.11:48:22.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.11:48:22.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.11:48:22.69#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:22.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:48:22.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:48:22.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:48:22.73#ibcon#enter wrdev, iclass 16, count 2 2006.285.11:48:22.73#ibcon#first serial, iclass 16, count 2 2006.285.11:48:22.73#ibcon#enter sib2, iclass 16, count 2 2006.285.11:48:22.73#ibcon#flushed, iclass 16, count 2 2006.285.11:48:22.73#ibcon#about to write, iclass 16, count 2 2006.285.11:48:22.73#ibcon#wrote, iclass 16, count 2 2006.285.11:48:22.73#ibcon#about to read 3, iclass 16, count 2 2006.285.11:48:22.75#ibcon#read 3, iclass 16, count 2 2006.285.11:48:22.75#ibcon#about to read 4, iclass 16, count 2 2006.285.11:48:22.75#ibcon#read 4, iclass 16, count 2 2006.285.11:48:22.75#ibcon#about to read 5, iclass 16, count 2 2006.285.11:48:22.75#ibcon#read 5, iclass 16, count 2 2006.285.11:48:22.75#ibcon#about to read 6, iclass 16, count 2 2006.285.11:48:22.75#ibcon#read 6, iclass 16, count 2 2006.285.11:48:22.75#ibcon#end of sib2, iclass 16, count 2 2006.285.11:48:22.75#ibcon#*mode == 0, iclass 16, count 2 2006.285.11:48:22.75#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.11:48:22.75#ibcon#[27=AT07-04\r\n] 2006.285.11:48:22.75#ibcon#*before write, iclass 16, count 2 2006.285.11:48:22.75#ibcon#enter sib2, iclass 16, count 2 2006.285.11:48:22.75#ibcon#flushed, iclass 16, count 2 2006.285.11:48:22.75#ibcon#about to write, iclass 16, count 2 2006.285.11:48:22.75#ibcon#wrote, iclass 16, count 2 2006.285.11:48:22.75#ibcon#about to read 3, iclass 16, count 2 2006.285.11:48:22.78#ibcon#read 3, iclass 16, count 2 2006.285.11:48:22.78#ibcon#about to read 4, iclass 16, count 2 2006.285.11:48:22.78#ibcon#read 4, iclass 16, count 2 2006.285.11:48:22.78#ibcon#about to read 5, iclass 16, count 2 2006.285.11:48:22.78#ibcon#read 5, iclass 16, count 2 2006.285.11:48:22.78#ibcon#about to read 6, iclass 16, count 2 2006.285.11:48:22.78#ibcon#read 6, iclass 16, count 2 2006.285.11:48:22.78#ibcon#end of sib2, iclass 16, count 2 2006.285.11:48:22.78#ibcon#*after write, iclass 16, count 2 2006.285.11:48:22.78#ibcon#*before return 0, iclass 16, count 2 2006.285.11:48:22.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:48:22.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.11:48:22.78#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.11:48:22.78#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:22.78#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:48:22.90#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:48:22.90#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:48:22.90#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:48:22.90#ibcon#first serial, iclass 16, count 0 2006.285.11:48:22.90#ibcon#enter sib2, iclass 16, count 0 2006.285.11:48:22.90#ibcon#flushed, iclass 16, count 0 2006.285.11:48:22.90#ibcon#about to write, iclass 16, count 0 2006.285.11:48:22.90#ibcon#wrote, iclass 16, count 0 2006.285.11:48:22.90#ibcon#about to read 3, iclass 16, count 0 2006.285.11:48:22.92#ibcon#read 3, iclass 16, count 0 2006.285.11:48:22.92#ibcon#about to read 4, iclass 16, count 0 2006.285.11:48:22.92#ibcon#read 4, iclass 16, count 0 2006.285.11:48:22.92#ibcon#about to read 5, iclass 16, count 0 2006.285.11:48:22.92#ibcon#read 5, iclass 16, count 0 2006.285.11:48:22.92#ibcon#about to read 6, iclass 16, count 0 2006.285.11:48:22.92#ibcon#read 6, iclass 16, count 0 2006.285.11:48:22.92#ibcon#end of sib2, iclass 16, count 0 2006.285.11:48:22.92#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:48:22.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:48:22.92#ibcon#[27=USB\r\n] 2006.285.11:48:22.92#ibcon#*before write, iclass 16, count 0 2006.285.11:48:22.92#ibcon#enter sib2, iclass 16, count 0 2006.285.11:48:22.92#ibcon#flushed, iclass 16, count 0 2006.285.11:48:22.92#ibcon#about to write, iclass 16, count 0 2006.285.11:48:22.92#ibcon#wrote, iclass 16, count 0 2006.285.11:48:22.92#ibcon#about to read 3, iclass 16, count 0 2006.285.11:48:22.95#ibcon#read 3, iclass 16, count 0 2006.285.11:48:22.95#ibcon#about to read 4, iclass 16, count 0 2006.285.11:48:22.95#ibcon#read 4, iclass 16, count 0 2006.285.11:48:22.95#ibcon#about to read 5, iclass 16, count 0 2006.285.11:48:22.95#ibcon#read 5, iclass 16, count 0 2006.285.11:48:22.95#ibcon#about to read 6, iclass 16, count 0 2006.285.11:48:22.95#ibcon#read 6, iclass 16, count 0 2006.285.11:48:22.95#ibcon#end of sib2, iclass 16, count 0 2006.285.11:48:22.95#ibcon#*after write, iclass 16, count 0 2006.285.11:48:22.95#ibcon#*before return 0, iclass 16, count 0 2006.285.11:48:22.95#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:48:22.95#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.11:48:22.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:48:22.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:48:22.95$vck44/vblo=8,744.99 2006.285.11:48:22.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.11:48:22.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.11:48:22.96#ibcon#ireg 17 cls_cnt 0 2006.285.11:48:22.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:48:22.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:48:22.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:48:22.96#ibcon#enter wrdev, iclass 18, count 0 2006.285.11:48:22.96#ibcon#first serial, iclass 18, count 0 2006.285.11:48:22.96#ibcon#enter sib2, iclass 18, count 0 2006.285.11:48:22.96#ibcon#flushed, iclass 18, count 0 2006.285.11:48:22.96#ibcon#about to write, iclass 18, count 0 2006.285.11:48:22.96#ibcon#wrote, iclass 18, count 0 2006.285.11:48:22.96#ibcon#about to read 3, iclass 18, count 0 2006.285.11:48:22.97#ibcon#read 3, iclass 18, count 0 2006.285.11:48:22.97#ibcon#about to read 4, iclass 18, count 0 2006.285.11:48:22.97#ibcon#read 4, iclass 18, count 0 2006.285.11:48:22.97#ibcon#about to read 5, iclass 18, count 0 2006.285.11:48:22.97#ibcon#read 5, iclass 18, count 0 2006.285.11:48:22.97#ibcon#about to read 6, iclass 18, count 0 2006.285.11:48:22.97#ibcon#read 6, iclass 18, count 0 2006.285.11:48:22.97#ibcon#end of sib2, iclass 18, count 0 2006.285.11:48:22.97#ibcon#*mode == 0, iclass 18, count 0 2006.285.11:48:22.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.11:48:22.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:48:22.97#ibcon#*before write, iclass 18, count 0 2006.285.11:48:22.97#ibcon#enter sib2, iclass 18, count 0 2006.285.11:48:22.97#ibcon#flushed, iclass 18, count 0 2006.285.11:48:22.97#ibcon#about to write, iclass 18, count 0 2006.285.11:48:22.97#ibcon#wrote, iclass 18, count 0 2006.285.11:48:22.97#ibcon#about to read 3, iclass 18, count 0 2006.285.11:48:23.01#ibcon#read 3, iclass 18, count 0 2006.285.11:48:23.01#ibcon#about to read 4, iclass 18, count 0 2006.285.11:48:23.01#ibcon#read 4, iclass 18, count 0 2006.285.11:48:23.01#ibcon#about to read 5, iclass 18, count 0 2006.285.11:48:23.01#ibcon#read 5, iclass 18, count 0 2006.285.11:48:23.01#ibcon#about to read 6, iclass 18, count 0 2006.285.11:48:23.01#ibcon#read 6, iclass 18, count 0 2006.285.11:48:23.01#ibcon#end of sib2, iclass 18, count 0 2006.285.11:48:23.01#ibcon#*after write, iclass 18, count 0 2006.285.11:48:23.01#ibcon#*before return 0, iclass 18, count 0 2006.285.11:48:23.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:48:23.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.11:48:23.01#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.11:48:23.01#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.11:48:23.01$vck44/vb=8,4 2006.285.11:48:23.02#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.11:48:23.02#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.11:48:23.02#ibcon#ireg 11 cls_cnt 2 2006.285.11:48:23.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:48:23.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:48:23.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:48:23.06#ibcon#enter wrdev, iclass 20, count 2 2006.285.11:48:23.06#ibcon#first serial, iclass 20, count 2 2006.285.11:48:23.06#ibcon#enter sib2, iclass 20, count 2 2006.285.11:48:23.06#ibcon#flushed, iclass 20, count 2 2006.285.11:48:23.06#ibcon#about to write, iclass 20, count 2 2006.285.11:48:23.06#ibcon#wrote, iclass 20, count 2 2006.285.11:48:23.06#ibcon#about to read 3, iclass 20, count 2 2006.285.11:48:23.08#ibcon#read 3, iclass 20, count 2 2006.285.11:48:23.08#ibcon#about to read 4, iclass 20, count 2 2006.285.11:48:23.08#ibcon#read 4, iclass 20, count 2 2006.285.11:48:23.08#ibcon#about to read 5, iclass 20, count 2 2006.285.11:48:23.08#ibcon#read 5, iclass 20, count 2 2006.285.11:48:23.08#ibcon#about to read 6, iclass 20, count 2 2006.285.11:48:23.08#ibcon#read 6, iclass 20, count 2 2006.285.11:48:23.08#ibcon#end of sib2, iclass 20, count 2 2006.285.11:48:23.08#ibcon#*mode == 0, iclass 20, count 2 2006.285.11:48:23.08#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.11:48:23.08#ibcon#[27=AT08-04\r\n] 2006.285.11:48:23.08#ibcon#*before write, iclass 20, count 2 2006.285.11:48:23.08#ibcon#enter sib2, iclass 20, count 2 2006.285.11:48:23.08#ibcon#flushed, iclass 20, count 2 2006.285.11:48:23.08#ibcon#about to write, iclass 20, count 2 2006.285.11:48:23.08#ibcon#wrote, iclass 20, count 2 2006.285.11:48:23.08#ibcon#about to read 3, iclass 20, count 2 2006.285.11:48:23.11#ibcon#read 3, iclass 20, count 2 2006.285.11:48:23.11#ibcon#about to read 4, iclass 20, count 2 2006.285.11:48:23.11#ibcon#read 4, iclass 20, count 2 2006.285.11:48:23.11#ibcon#about to read 5, iclass 20, count 2 2006.285.11:48:23.11#ibcon#read 5, iclass 20, count 2 2006.285.11:48:23.11#ibcon#about to read 6, iclass 20, count 2 2006.285.11:48:23.11#ibcon#read 6, iclass 20, count 2 2006.285.11:48:23.11#ibcon#end of sib2, iclass 20, count 2 2006.285.11:48:23.11#ibcon#*after write, iclass 20, count 2 2006.285.11:48:23.11#ibcon#*before return 0, iclass 20, count 2 2006.285.11:48:23.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:48:23.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.11:48:23.11#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.11:48:23.11#ibcon#ireg 7 cls_cnt 0 2006.285.11:48:23.11#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:48:23.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:48:23.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:48:23.23#ibcon#enter wrdev, iclass 20, count 0 2006.285.11:48:23.23#ibcon#first serial, iclass 20, count 0 2006.285.11:48:23.23#ibcon#enter sib2, iclass 20, count 0 2006.285.11:48:23.23#ibcon#flushed, iclass 20, count 0 2006.285.11:48:23.23#ibcon#about to write, iclass 20, count 0 2006.285.11:48:23.23#ibcon#wrote, iclass 20, count 0 2006.285.11:48:23.23#ibcon#about to read 3, iclass 20, count 0 2006.285.11:48:23.25#ibcon#read 3, iclass 20, count 0 2006.285.11:48:23.25#ibcon#about to read 4, iclass 20, count 0 2006.285.11:48:23.25#ibcon#read 4, iclass 20, count 0 2006.285.11:48:23.25#ibcon#about to read 5, iclass 20, count 0 2006.285.11:48:23.25#ibcon#read 5, iclass 20, count 0 2006.285.11:48:23.25#ibcon#about to read 6, iclass 20, count 0 2006.285.11:48:23.25#ibcon#read 6, iclass 20, count 0 2006.285.11:48:23.25#ibcon#end of sib2, iclass 20, count 0 2006.285.11:48:23.25#ibcon#*mode == 0, iclass 20, count 0 2006.285.11:48:23.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.11:48:23.25#ibcon#[27=USB\r\n] 2006.285.11:48:23.25#ibcon#*before write, iclass 20, count 0 2006.285.11:48:23.25#ibcon#enter sib2, iclass 20, count 0 2006.285.11:48:23.25#ibcon#flushed, iclass 20, count 0 2006.285.11:48:23.25#ibcon#about to write, iclass 20, count 0 2006.285.11:48:23.25#ibcon#wrote, iclass 20, count 0 2006.285.11:48:23.25#ibcon#about to read 3, iclass 20, count 0 2006.285.11:48:23.28#ibcon#read 3, iclass 20, count 0 2006.285.11:48:23.28#ibcon#about to read 4, iclass 20, count 0 2006.285.11:48:23.28#ibcon#read 4, iclass 20, count 0 2006.285.11:48:23.28#ibcon#about to read 5, iclass 20, count 0 2006.285.11:48:23.28#ibcon#read 5, iclass 20, count 0 2006.285.11:48:23.28#ibcon#about to read 6, iclass 20, count 0 2006.285.11:48:23.28#ibcon#read 6, iclass 20, count 0 2006.285.11:48:23.28#ibcon#end of sib2, iclass 20, count 0 2006.285.11:48:23.28#ibcon#*after write, iclass 20, count 0 2006.285.11:48:23.28#ibcon#*before return 0, iclass 20, count 0 2006.285.11:48:23.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:48:23.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.11:48:23.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.11:48:23.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.11:48:23.28$vck44/vabw=wide 2006.285.11:48:23.29#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.11:48:23.29#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.11:48:23.29#ibcon#ireg 8 cls_cnt 0 2006.285.11:48:23.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:48:23.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:48:23.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:48:23.29#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:48:23.29#ibcon#first serial, iclass 22, count 0 2006.285.11:48:23.29#ibcon#enter sib2, iclass 22, count 0 2006.285.11:48:23.29#ibcon#flushed, iclass 22, count 0 2006.285.11:48:23.29#ibcon#about to write, iclass 22, count 0 2006.285.11:48:23.29#ibcon#wrote, iclass 22, count 0 2006.285.11:48:23.29#ibcon#about to read 3, iclass 22, count 0 2006.285.11:48:23.30#ibcon#read 3, iclass 22, count 0 2006.285.11:48:23.30#ibcon#about to read 4, iclass 22, count 0 2006.285.11:48:23.30#ibcon#read 4, iclass 22, count 0 2006.285.11:48:23.30#ibcon#about to read 5, iclass 22, count 0 2006.285.11:48:23.30#ibcon#read 5, iclass 22, count 0 2006.285.11:48:23.30#ibcon#about to read 6, iclass 22, count 0 2006.285.11:48:23.30#ibcon#read 6, iclass 22, count 0 2006.285.11:48:23.30#ibcon#end of sib2, iclass 22, count 0 2006.285.11:48:23.30#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:48:23.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:48:23.30#ibcon#[25=BW32\r\n] 2006.285.11:48:23.30#ibcon#*before write, iclass 22, count 0 2006.285.11:48:23.30#ibcon#enter sib2, iclass 22, count 0 2006.285.11:48:23.30#ibcon#flushed, iclass 22, count 0 2006.285.11:48:23.30#ibcon#about to write, iclass 22, count 0 2006.285.11:48:23.30#ibcon#wrote, iclass 22, count 0 2006.285.11:48:23.30#ibcon#about to read 3, iclass 22, count 0 2006.285.11:48:23.33#ibcon#read 3, iclass 22, count 0 2006.285.11:48:23.33#ibcon#about to read 4, iclass 22, count 0 2006.285.11:48:23.33#ibcon#read 4, iclass 22, count 0 2006.285.11:48:23.33#ibcon#about to read 5, iclass 22, count 0 2006.285.11:48:23.33#ibcon#read 5, iclass 22, count 0 2006.285.11:48:23.33#ibcon#about to read 6, iclass 22, count 0 2006.285.11:48:23.33#ibcon#read 6, iclass 22, count 0 2006.285.11:48:23.33#ibcon#end of sib2, iclass 22, count 0 2006.285.11:48:23.33#ibcon#*after write, iclass 22, count 0 2006.285.11:48:23.33#ibcon#*before return 0, iclass 22, count 0 2006.285.11:48:23.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:48:23.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.11:48:23.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:48:23.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:48:23.33$vck44/vbbw=wide 2006.285.11:48:23.34#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.11:48:23.34#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.11:48:23.34#ibcon#ireg 8 cls_cnt 0 2006.285.11:48:23.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:48:23.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:48:23.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:48:23.39#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:48:23.39#ibcon#first serial, iclass 24, count 0 2006.285.11:48:23.39#ibcon#enter sib2, iclass 24, count 0 2006.285.11:48:23.39#ibcon#flushed, iclass 24, count 0 2006.285.11:48:23.39#ibcon#about to write, iclass 24, count 0 2006.285.11:48:23.39#ibcon#wrote, iclass 24, count 0 2006.285.11:48:23.39#ibcon#about to read 3, iclass 24, count 0 2006.285.11:48:23.41#ibcon#read 3, iclass 24, count 0 2006.285.11:48:23.41#ibcon#about to read 4, iclass 24, count 0 2006.285.11:48:23.41#ibcon#read 4, iclass 24, count 0 2006.285.11:48:23.41#ibcon#about to read 5, iclass 24, count 0 2006.285.11:48:23.41#ibcon#read 5, iclass 24, count 0 2006.285.11:48:23.41#ibcon#about to read 6, iclass 24, count 0 2006.285.11:48:23.41#ibcon#read 6, iclass 24, count 0 2006.285.11:48:23.41#ibcon#end of sib2, iclass 24, count 0 2006.285.11:48:23.41#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:48:23.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:48:23.41#ibcon#[27=BW32\r\n] 2006.285.11:48:23.41#ibcon#*before write, iclass 24, count 0 2006.285.11:48:23.41#ibcon#enter sib2, iclass 24, count 0 2006.285.11:48:23.41#ibcon#flushed, iclass 24, count 0 2006.285.11:48:23.41#ibcon#about to write, iclass 24, count 0 2006.285.11:48:23.41#ibcon#wrote, iclass 24, count 0 2006.285.11:48:23.41#ibcon#about to read 3, iclass 24, count 0 2006.285.11:48:23.44#ibcon#read 3, iclass 24, count 0 2006.285.11:48:23.44#ibcon#about to read 4, iclass 24, count 0 2006.285.11:48:23.44#ibcon#read 4, iclass 24, count 0 2006.285.11:48:23.44#ibcon#about to read 5, iclass 24, count 0 2006.285.11:48:23.44#ibcon#read 5, iclass 24, count 0 2006.285.11:48:23.44#ibcon#about to read 6, iclass 24, count 0 2006.285.11:48:23.44#ibcon#read 6, iclass 24, count 0 2006.285.11:48:23.44#ibcon#end of sib2, iclass 24, count 0 2006.285.11:48:23.44#ibcon#*after write, iclass 24, count 0 2006.285.11:48:23.44#ibcon#*before return 0, iclass 24, count 0 2006.285.11:48:23.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:48:23.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:48:23.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:48:23.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:48:23.45$setupk4/ifdk4 2006.285.11:48:23.45$ifdk4/lo= 2006.285.11:48:23.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:48:23.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:48:23.45$ifdk4/patch= 2006.285.11:48:23.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:48:23.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:48:23.45$setupk4/!*+20s 2006.285.11:48:25.14#trakl#Source acquired 2006.285.11:48:25.15#flagr#flagr/antenna,acquired 2006.285.11:48:28.68#abcon#<5=/05 1.0 1.3 19.02 951015.4\r\n> 2006.285.11:48:28.70#abcon#{5=INTERFACE CLEAR} 2006.285.11:48:28.76#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:48:38.11$setupk4/"tpicd 2006.285.11:48:38.11$setupk4/echo=off 2006.285.11:48:38.11$setupk4/xlog=off 2006.285.11:48:38.11:!2006.285.11:49:34 2006.285.11:49:34.00:preob 2006.285.11:49:35.14/onsource/TRACKING 2006.285.11:49:35.14:!2006.285.11:49:44 2006.285.11:49:44.00:"tape 2006.285.11:49:44.00:"st=record 2006.285.11:49:44.00:data_valid=on 2006.285.11:49:44.00:midob 2006.285.11:49:44.14/onsource/TRACKING 2006.285.11:49:44.15/wx/19.02,1015.4,95 2006.285.11:49:44.22/cable/+6.4932E-03 2006.285.11:49:45.31/va/01,07,usb,yes,31,34 2006.285.11:49:45.31/va/02,06,usb,yes,31,32 2006.285.11:49:45.31/va/03,07,usb,yes,31,33 2006.285.11:49:45.31/va/04,06,usb,yes,32,34 2006.285.11:49:45.31/va/05,03,usb,yes,32,32 2006.285.11:49:45.31/va/06,04,usb,yes,29,28 2006.285.11:49:45.31/va/07,04,usb,yes,29,30 2006.285.11:49:45.31/va/08,03,usb,yes,30,36 2006.285.11:49:45.54/valo/01,524.99,yes,locked 2006.285.11:49:45.54/valo/02,534.99,yes,locked 2006.285.11:49:45.54/valo/03,564.99,yes,locked 2006.285.11:49:45.54/valo/04,624.99,yes,locked 2006.285.11:49:45.54/valo/05,734.99,yes,locked 2006.285.11:49:45.54/valo/06,814.99,yes,locked 2006.285.11:49:45.54/valo/07,864.99,yes,locked 2006.285.11:49:45.54/valo/08,884.99,yes,locked 2006.285.11:49:46.63/vb/01,04,usb,yes,30,28 2006.285.11:49:46.63/vb/02,05,usb,yes,28,28 2006.285.11:49:46.63/vb/03,04,usb,yes,29,32 2006.285.11:49:46.63/vb/04,05,usb,yes,29,28 2006.285.11:49:46.63/vb/05,04,usb,yes,26,28 2006.285.11:49:46.63/vb/06,03,usb,yes,37,33 2006.285.11:49:46.63/vb/07,04,usb,yes,30,30 2006.285.11:49:46.63/vb/08,04,usb,yes,27,31 2006.285.11:49:46.87/vblo/01,629.99,yes,locked 2006.285.11:49:46.87/vblo/02,634.99,yes,locked 2006.285.11:49:46.87/vblo/03,649.99,yes,locked 2006.285.11:49:46.87/vblo/04,679.99,yes,locked 2006.285.11:49:46.87/vblo/05,709.99,yes,locked 2006.285.11:49:46.87/vblo/06,719.99,yes,locked 2006.285.11:49:46.87/vblo/07,734.99,yes,locked 2006.285.11:49:46.87/vblo/08,744.99,yes,locked 2006.285.11:49:47.02/vabw/8 2006.285.11:49:47.17/vbbw/8 2006.285.11:49:47.26/xfe/off,on,12.2 2006.285.11:49:47.63/ifatt/23,28,28,28 2006.285.11:49:48.07/fmout-gps/S +2.66E-07 2006.285.11:49:48.09:!2006.285.11:50:54 2006.285.11:50:54.01:data_valid=off 2006.285.11:50:54.01:"et 2006.285.11:50:54.02:!+3s 2006.285.11:50:57.04:"tape 2006.285.11:50:57.04:postob 2006.285.11:50:57.22/cable/+6.4928E-03 2006.285.11:50:57.22/wx/19.02,1015.4,95 2006.285.11:50:57.28/fmout-gps/S +2.65E-07 2006.285.11:50:57.28:scan_name=285-1155,jd0610,100 2006.285.11:50:57.28:source=2128-123,213135.26,-120704.8,2000.0,ccw 2006.285.11:50:59.14#flagr#flagr/antenna,new-source 2006.285.11:50:59.15:checkk5 2006.285.11:50:59.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:51:00.02/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:51:00.42/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:51:01.05/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:51:01.44/chk_obsdata//k5ts1/T2851149??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.11:51:02.02/chk_obsdata//k5ts2/T2851149??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.11:51:02.37/chk_obsdata//k5ts3/T2851149??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.11:51:02.88/chk_obsdata//k5ts4/T2851149??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.285.11:51:03.61/k5log//k5ts1_log_newline 2006.285.11:51:04.36/k5log//k5ts2_log_newline 2006.285.11:51:05.15/k5log//k5ts3_log_newline 2006.285.11:51:05.87/k5log//k5ts4_log_newline 2006.285.11:51:05.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:51:05.89:setupk4=1 2006.285.11:51:05.89$setupk4/echo=on 2006.285.11:51:05.89$setupk4/pcalon 2006.285.11:51:05.89$pcalon/"no phase cal control is implemented here 2006.285.11:51:05.89$setupk4/"tpicd=stop 2006.285.11:51:05.89$setupk4/"rec=synch_on 2006.285.11:51:05.89$setupk4/"rec_mode=128 2006.285.11:51:05.89$setupk4/!* 2006.285.11:51:05.89$setupk4/recpk4 2006.285.11:51:05.89$recpk4/recpatch= 2006.285.11:51:05.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:51:05.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:51:05.90$setupk4/vck44 2006.285.11:51:05.90$vck44/valo=1,524.99 2006.285.11:51:05.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.11:51:05.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.11:51:05.90#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:05.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:51:05.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:51:05.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:51:05.90#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:51:05.90#ibcon#first serial, iclass 21, count 0 2006.285.11:51:05.90#ibcon#enter sib2, iclass 21, count 0 2006.285.11:51:05.90#ibcon#flushed, iclass 21, count 0 2006.285.11:51:05.90#ibcon#about to write, iclass 21, count 0 2006.285.11:51:05.90#ibcon#wrote, iclass 21, count 0 2006.285.11:51:05.90#ibcon#about to read 3, iclass 21, count 0 2006.285.11:51:05.91#ibcon#read 3, iclass 21, count 0 2006.285.11:51:05.91#ibcon#about to read 4, iclass 21, count 0 2006.285.11:51:05.91#ibcon#read 4, iclass 21, count 0 2006.285.11:51:05.91#ibcon#about to read 5, iclass 21, count 0 2006.285.11:51:05.91#ibcon#read 5, iclass 21, count 0 2006.285.11:51:05.91#ibcon#about to read 6, iclass 21, count 0 2006.285.11:51:05.91#ibcon#read 6, iclass 21, count 0 2006.285.11:51:05.91#ibcon#end of sib2, iclass 21, count 0 2006.285.11:51:05.91#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:51:05.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:51:05.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:51:05.91#ibcon#*before write, iclass 21, count 0 2006.285.11:51:05.91#ibcon#enter sib2, iclass 21, count 0 2006.285.11:51:05.91#ibcon#flushed, iclass 21, count 0 2006.285.11:51:05.91#ibcon#about to write, iclass 21, count 0 2006.285.11:51:05.91#ibcon#wrote, iclass 21, count 0 2006.285.11:51:05.91#ibcon#about to read 3, iclass 21, count 0 2006.285.11:51:05.96#ibcon#read 3, iclass 21, count 0 2006.285.11:51:05.96#ibcon#about to read 4, iclass 21, count 0 2006.285.11:51:05.96#ibcon#read 4, iclass 21, count 0 2006.285.11:51:05.96#ibcon#about to read 5, iclass 21, count 0 2006.285.11:51:05.96#ibcon#read 5, iclass 21, count 0 2006.285.11:51:05.96#ibcon#about to read 6, iclass 21, count 0 2006.285.11:51:05.96#ibcon#read 6, iclass 21, count 0 2006.285.11:51:05.96#ibcon#end of sib2, iclass 21, count 0 2006.285.11:51:05.96#ibcon#*after write, iclass 21, count 0 2006.285.11:51:05.96#ibcon#*before return 0, iclass 21, count 0 2006.285.11:51:05.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:51:05.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:51:05.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:51:05.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:51:05.97$vck44/va=1,7 2006.285.11:51:05.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.11:51:05.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.11:51:05.97#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:05.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:51:05.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:51:05.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:51:05.97#ibcon#enter wrdev, iclass 23, count 2 2006.285.11:51:05.97#ibcon#first serial, iclass 23, count 2 2006.285.11:51:05.97#ibcon#enter sib2, iclass 23, count 2 2006.285.11:51:05.97#ibcon#flushed, iclass 23, count 2 2006.285.11:51:05.97#ibcon#about to write, iclass 23, count 2 2006.285.11:51:05.97#ibcon#wrote, iclass 23, count 2 2006.285.11:51:05.97#ibcon#about to read 3, iclass 23, count 2 2006.285.11:51:05.98#ibcon#read 3, iclass 23, count 2 2006.285.11:51:05.98#ibcon#about to read 4, iclass 23, count 2 2006.285.11:51:05.98#ibcon#read 4, iclass 23, count 2 2006.285.11:51:05.98#ibcon#about to read 5, iclass 23, count 2 2006.285.11:51:05.98#ibcon#read 5, iclass 23, count 2 2006.285.11:51:05.98#ibcon#about to read 6, iclass 23, count 2 2006.285.11:51:05.98#ibcon#read 6, iclass 23, count 2 2006.285.11:51:05.98#ibcon#end of sib2, iclass 23, count 2 2006.285.11:51:05.98#ibcon#*mode == 0, iclass 23, count 2 2006.285.11:51:05.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.11:51:05.98#ibcon#[25=AT01-07\r\n] 2006.285.11:51:05.98#ibcon#*before write, iclass 23, count 2 2006.285.11:51:05.98#ibcon#enter sib2, iclass 23, count 2 2006.285.11:51:05.98#ibcon#flushed, iclass 23, count 2 2006.285.11:51:05.98#ibcon#about to write, iclass 23, count 2 2006.285.11:51:05.98#ibcon#wrote, iclass 23, count 2 2006.285.11:51:05.98#ibcon#about to read 3, iclass 23, count 2 2006.285.11:51:06.01#ibcon#read 3, iclass 23, count 2 2006.285.11:51:06.01#ibcon#about to read 4, iclass 23, count 2 2006.285.11:51:06.01#ibcon#read 4, iclass 23, count 2 2006.285.11:51:06.01#ibcon#about to read 5, iclass 23, count 2 2006.285.11:51:06.01#ibcon#read 5, iclass 23, count 2 2006.285.11:51:06.01#ibcon#about to read 6, iclass 23, count 2 2006.285.11:51:06.01#ibcon#read 6, iclass 23, count 2 2006.285.11:51:06.01#ibcon#end of sib2, iclass 23, count 2 2006.285.11:51:06.01#ibcon#*after write, iclass 23, count 2 2006.285.11:51:06.01#ibcon#*before return 0, iclass 23, count 2 2006.285.11:51:06.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:51:06.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:51:06.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.11:51:06.01#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:06.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:51:06.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:51:06.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:51:06.13#ibcon#enter wrdev, iclass 23, count 0 2006.285.11:51:06.13#ibcon#first serial, iclass 23, count 0 2006.285.11:51:06.13#ibcon#enter sib2, iclass 23, count 0 2006.285.11:51:06.13#ibcon#flushed, iclass 23, count 0 2006.285.11:51:06.13#ibcon#about to write, iclass 23, count 0 2006.285.11:51:06.13#ibcon#wrote, iclass 23, count 0 2006.285.11:51:06.13#ibcon#about to read 3, iclass 23, count 0 2006.285.11:51:06.15#ibcon#read 3, iclass 23, count 0 2006.285.11:51:06.15#ibcon#about to read 4, iclass 23, count 0 2006.285.11:51:06.15#ibcon#read 4, iclass 23, count 0 2006.285.11:51:06.15#ibcon#about to read 5, iclass 23, count 0 2006.285.11:51:06.15#ibcon#read 5, iclass 23, count 0 2006.285.11:51:06.15#ibcon#about to read 6, iclass 23, count 0 2006.285.11:51:06.15#ibcon#read 6, iclass 23, count 0 2006.285.11:51:06.15#ibcon#end of sib2, iclass 23, count 0 2006.285.11:51:06.15#ibcon#*mode == 0, iclass 23, count 0 2006.285.11:51:06.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.11:51:06.15#ibcon#[25=USB\r\n] 2006.285.11:51:06.15#ibcon#*before write, iclass 23, count 0 2006.285.11:51:06.15#ibcon#enter sib2, iclass 23, count 0 2006.285.11:51:06.15#ibcon#flushed, iclass 23, count 0 2006.285.11:51:06.15#ibcon#about to write, iclass 23, count 0 2006.285.11:51:06.15#ibcon#wrote, iclass 23, count 0 2006.285.11:51:06.15#ibcon#about to read 3, iclass 23, count 0 2006.285.11:51:06.18#ibcon#read 3, iclass 23, count 0 2006.285.11:51:06.18#ibcon#about to read 4, iclass 23, count 0 2006.285.11:51:06.18#ibcon#read 4, iclass 23, count 0 2006.285.11:51:06.18#ibcon#about to read 5, iclass 23, count 0 2006.285.11:51:06.18#ibcon#read 5, iclass 23, count 0 2006.285.11:51:06.18#ibcon#about to read 6, iclass 23, count 0 2006.285.11:51:06.18#ibcon#read 6, iclass 23, count 0 2006.285.11:51:06.18#ibcon#end of sib2, iclass 23, count 0 2006.285.11:51:06.18#ibcon#*after write, iclass 23, count 0 2006.285.11:51:06.18#ibcon#*before return 0, iclass 23, count 0 2006.285.11:51:06.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:51:06.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:51:06.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.11:51:06.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.11:51:06.19$vck44/valo=2,534.99 2006.285.11:51:06.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.11:51:06.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.11:51:06.19#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:06.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:51:06.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:51:06.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:51:06.19#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:51:06.19#ibcon#first serial, iclass 25, count 0 2006.285.11:51:06.19#ibcon#enter sib2, iclass 25, count 0 2006.285.11:51:06.19#ibcon#flushed, iclass 25, count 0 2006.285.11:51:06.19#ibcon#about to write, iclass 25, count 0 2006.285.11:51:06.19#ibcon#wrote, iclass 25, count 0 2006.285.11:51:06.19#ibcon#about to read 3, iclass 25, count 0 2006.285.11:51:06.20#ibcon#read 3, iclass 25, count 0 2006.285.11:51:06.20#ibcon#about to read 4, iclass 25, count 0 2006.285.11:51:06.20#ibcon#read 4, iclass 25, count 0 2006.285.11:51:06.20#ibcon#about to read 5, iclass 25, count 0 2006.285.11:51:06.20#ibcon#read 5, iclass 25, count 0 2006.285.11:51:06.20#ibcon#about to read 6, iclass 25, count 0 2006.285.11:51:06.20#ibcon#read 6, iclass 25, count 0 2006.285.11:51:06.20#ibcon#end of sib2, iclass 25, count 0 2006.285.11:51:06.20#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:51:06.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:51:06.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:51:06.20#ibcon#*before write, iclass 25, count 0 2006.285.11:51:06.20#ibcon#enter sib2, iclass 25, count 0 2006.285.11:51:06.20#ibcon#flushed, iclass 25, count 0 2006.285.11:51:06.20#ibcon#about to write, iclass 25, count 0 2006.285.11:51:06.20#ibcon#wrote, iclass 25, count 0 2006.285.11:51:06.20#ibcon#about to read 3, iclass 25, count 0 2006.285.11:51:06.24#ibcon#read 3, iclass 25, count 0 2006.285.11:51:06.24#ibcon#about to read 4, iclass 25, count 0 2006.285.11:51:06.24#ibcon#read 4, iclass 25, count 0 2006.285.11:51:06.24#ibcon#about to read 5, iclass 25, count 0 2006.285.11:51:06.24#ibcon#read 5, iclass 25, count 0 2006.285.11:51:06.24#ibcon#about to read 6, iclass 25, count 0 2006.285.11:51:06.24#ibcon#read 6, iclass 25, count 0 2006.285.11:51:06.24#ibcon#end of sib2, iclass 25, count 0 2006.285.11:51:06.24#ibcon#*after write, iclass 25, count 0 2006.285.11:51:06.24#ibcon#*before return 0, iclass 25, count 0 2006.285.11:51:06.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:51:06.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:51:06.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:51:06.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:51:06.24$vck44/va=2,6 2006.285.11:51:06.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.11:51:06.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.11:51:06.25#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:06.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:51:06.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:51:06.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:51:06.29#ibcon#enter wrdev, iclass 27, count 2 2006.285.11:51:06.29#ibcon#first serial, iclass 27, count 2 2006.285.11:51:06.29#ibcon#enter sib2, iclass 27, count 2 2006.285.11:51:06.29#ibcon#flushed, iclass 27, count 2 2006.285.11:51:06.29#ibcon#about to write, iclass 27, count 2 2006.285.11:51:06.29#ibcon#wrote, iclass 27, count 2 2006.285.11:51:06.29#ibcon#about to read 3, iclass 27, count 2 2006.285.11:51:06.31#ibcon#read 3, iclass 27, count 2 2006.285.11:51:06.31#ibcon#about to read 4, iclass 27, count 2 2006.285.11:51:06.31#ibcon#read 4, iclass 27, count 2 2006.285.11:51:06.31#ibcon#about to read 5, iclass 27, count 2 2006.285.11:51:06.31#ibcon#read 5, iclass 27, count 2 2006.285.11:51:06.31#ibcon#about to read 6, iclass 27, count 2 2006.285.11:51:06.31#ibcon#read 6, iclass 27, count 2 2006.285.11:51:06.31#ibcon#end of sib2, iclass 27, count 2 2006.285.11:51:06.31#ibcon#*mode == 0, iclass 27, count 2 2006.285.11:51:06.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.11:51:06.31#ibcon#[25=AT02-06\r\n] 2006.285.11:51:06.31#ibcon#*before write, iclass 27, count 2 2006.285.11:51:06.31#ibcon#enter sib2, iclass 27, count 2 2006.285.11:51:06.31#ibcon#flushed, iclass 27, count 2 2006.285.11:51:06.31#ibcon#about to write, iclass 27, count 2 2006.285.11:51:06.31#ibcon#wrote, iclass 27, count 2 2006.285.11:51:06.31#ibcon#about to read 3, iclass 27, count 2 2006.285.11:51:06.34#ibcon#read 3, iclass 27, count 2 2006.285.11:51:06.34#ibcon#about to read 4, iclass 27, count 2 2006.285.11:51:06.34#ibcon#read 4, iclass 27, count 2 2006.285.11:51:06.34#ibcon#about to read 5, iclass 27, count 2 2006.285.11:51:06.34#ibcon#read 5, iclass 27, count 2 2006.285.11:51:06.34#ibcon#about to read 6, iclass 27, count 2 2006.285.11:51:06.34#ibcon#read 6, iclass 27, count 2 2006.285.11:51:06.34#ibcon#end of sib2, iclass 27, count 2 2006.285.11:51:06.34#ibcon#*after write, iclass 27, count 2 2006.285.11:51:06.34#ibcon#*before return 0, iclass 27, count 2 2006.285.11:51:06.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:51:06.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:51:06.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.11:51:06.34#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:06.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:51:06.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:51:06.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:51:06.46#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:51:06.46#ibcon#first serial, iclass 27, count 0 2006.285.11:51:06.46#ibcon#enter sib2, iclass 27, count 0 2006.285.11:51:06.46#ibcon#flushed, iclass 27, count 0 2006.285.11:51:06.46#ibcon#about to write, iclass 27, count 0 2006.285.11:51:06.46#ibcon#wrote, iclass 27, count 0 2006.285.11:51:06.46#ibcon#about to read 3, iclass 27, count 0 2006.285.11:51:06.48#ibcon#read 3, iclass 27, count 0 2006.285.11:51:06.48#ibcon#about to read 4, iclass 27, count 0 2006.285.11:51:06.48#ibcon#read 4, iclass 27, count 0 2006.285.11:51:06.48#ibcon#about to read 5, iclass 27, count 0 2006.285.11:51:06.48#ibcon#read 5, iclass 27, count 0 2006.285.11:51:06.48#ibcon#about to read 6, iclass 27, count 0 2006.285.11:51:06.48#ibcon#read 6, iclass 27, count 0 2006.285.11:51:06.48#ibcon#end of sib2, iclass 27, count 0 2006.285.11:51:06.48#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:51:06.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:51:06.48#ibcon#[25=USB\r\n] 2006.285.11:51:06.48#ibcon#*before write, iclass 27, count 0 2006.285.11:51:06.48#ibcon#enter sib2, iclass 27, count 0 2006.285.11:51:06.48#ibcon#flushed, iclass 27, count 0 2006.285.11:51:06.48#ibcon#about to write, iclass 27, count 0 2006.285.11:51:06.48#ibcon#wrote, iclass 27, count 0 2006.285.11:51:06.48#ibcon#about to read 3, iclass 27, count 0 2006.285.11:51:06.51#ibcon#read 3, iclass 27, count 0 2006.285.11:51:06.51#ibcon#about to read 4, iclass 27, count 0 2006.285.11:51:06.51#ibcon#read 4, iclass 27, count 0 2006.285.11:51:06.51#ibcon#about to read 5, iclass 27, count 0 2006.285.11:51:06.51#ibcon#read 5, iclass 27, count 0 2006.285.11:51:06.51#ibcon#about to read 6, iclass 27, count 0 2006.285.11:51:06.51#ibcon#read 6, iclass 27, count 0 2006.285.11:51:06.51#ibcon#end of sib2, iclass 27, count 0 2006.285.11:51:06.51#ibcon#*after write, iclass 27, count 0 2006.285.11:51:06.51#ibcon#*before return 0, iclass 27, count 0 2006.285.11:51:06.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:51:06.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:51:06.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:51:06.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:51:06.52$vck44/valo=3,564.99 2006.285.11:51:06.52#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.11:51:06.52#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.11:51:06.52#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:06.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:51:06.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:51:06.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:51:06.52#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:51:06.52#ibcon#first serial, iclass 29, count 0 2006.285.11:51:06.52#ibcon#enter sib2, iclass 29, count 0 2006.285.11:51:06.52#ibcon#flushed, iclass 29, count 0 2006.285.11:51:06.52#ibcon#about to write, iclass 29, count 0 2006.285.11:51:06.52#ibcon#wrote, iclass 29, count 0 2006.285.11:51:06.52#ibcon#about to read 3, iclass 29, count 0 2006.285.11:51:06.53#ibcon#read 3, iclass 29, count 0 2006.285.11:51:06.53#ibcon#about to read 4, iclass 29, count 0 2006.285.11:51:06.53#ibcon#read 4, iclass 29, count 0 2006.285.11:51:06.53#ibcon#about to read 5, iclass 29, count 0 2006.285.11:51:06.53#ibcon#read 5, iclass 29, count 0 2006.285.11:51:06.53#ibcon#about to read 6, iclass 29, count 0 2006.285.11:51:06.53#ibcon#read 6, iclass 29, count 0 2006.285.11:51:06.53#ibcon#end of sib2, iclass 29, count 0 2006.285.11:51:06.53#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:51:06.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:51:06.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:51:06.53#ibcon#*before write, iclass 29, count 0 2006.285.11:51:06.53#ibcon#enter sib2, iclass 29, count 0 2006.285.11:51:06.53#ibcon#flushed, iclass 29, count 0 2006.285.11:51:06.53#ibcon#about to write, iclass 29, count 0 2006.285.11:51:06.53#ibcon#wrote, iclass 29, count 0 2006.285.11:51:06.53#ibcon#about to read 3, iclass 29, count 0 2006.285.11:51:06.57#ibcon#read 3, iclass 29, count 0 2006.285.11:51:06.57#ibcon#about to read 4, iclass 29, count 0 2006.285.11:51:06.57#ibcon#read 4, iclass 29, count 0 2006.285.11:51:06.57#ibcon#about to read 5, iclass 29, count 0 2006.285.11:51:06.57#ibcon#read 5, iclass 29, count 0 2006.285.11:51:06.57#ibcon#about to read 6, iclass 29, count 0 2006.285.11:51:06.57#ibcon#read 6, iclass 29, count 0 2006.285.11:51:06.57#ibcon#end of sib2, iclass 29, count 0 2006.285.11:51:06.57#ibcon#*after write, iclass 29, count 0 2006.285.11:51:06.57#ibcon#*before return 0, iclass 29, count 0 2006.285.11:51:06.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:51:06.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:51:06.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:51:06.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:51:06.57$vck44/va=3,7 2006.285.11:51:06.58#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.11:51:06.58#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.11:51:06.58#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:06.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:51:06.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:51:06.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:51:06.62#ibcon#enter wrdev, iclass 31, count 2 2006.285.11:51:06.62#ibcon#first serial, iclass 31, count 2 2006.285.11:51:06.62#ibcon#enter sib2, iclass 31, count 2 2006.285.11:51:06.62#ibcon#flushed, iclass 31, count 2 2006.285.11:51:06.62#ibcon#about to write, iclass 31, count 2 2006.285.11:51:06.62#ibcon#wrote, iclass 31, count 2 2006.285.11:51:06.62#ibcon#about to read 3, iclass 31, count 2 2006.285.11:51:06.64#ibcon#read 3, iclass 31, count 2 2006.285.11:51:06.64#ibcon#about to read 4, iclass 31, count 2 2006.285.11:51:06.64#ibcon#read 4, iclass 31, count 2 2006.285.11:51:06.64#ibcon#about to read 5, iclass 31, count 2 2006.285.11:51:06.64#ibcon#read 5, iclass 31, count 2 2006.285.11:51:06.64#ibcon#about to read 6, iclass 31, count 2 2006.285.11:51:06.64#ibcon#read 6, iclass 31, count 2 2006.285.11:51:06.64#ibcon#end of sib2, iclass 31, count 2 2006.285.11:51:06.64#ibcon#*mode == 0, iclass 31, count 2 2006.285.11:51:06.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.11:51:06.64#ibcon#[25=AT03-07\r\n] 2006.285.11:51:06.64#ibcon#*before write, iclass 31, count 2 2006.285.11:51:06.64#ibcon#enter sib2, iclass 31, count 2 2006.285.11:51:06.64#ibcon#flushed, iclass 31, count 2 2006.285.11:51:06.64#ibcon#about to write, iclass 31, count 2 2006.285.11:51:06.64#ibcon#wrote, iclass 31, count 2 2006.285.11:51:06.64#ibcon#about to read 3, iclass 31, count 2 2006.285.11:51:06.67#ibcon#read 3, iclass 31, count 2 2006.285.11:51:06.67#ibcon#about to read 4, iclass 31, count 2 2006.285.11:51:06.67#ibcon#read 4, iclass 31, count 2 2006.285.11:51:06.67#ibcon#about to read 5, iclass 31, count 2 2006.285.11:51:06.67#ibcon#read 5, iclass 31, count 2 2006.285.11:51:06.67#ibcon#about to read 6, iclass 31, count 2 2006.285.11:51:06.67#ibcon#read 6, iclass 31, count 2 2006.285.11:51:06.67#ibcon#end of sib2, iclass 31, count 2 2006.285.11:51:06.67#ibcon#*after write, iclass 31, count 2 2006.285.11:51:06.67#ibcon#*before return 0, iclass 31, count 2 2006.285.11:51:06.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:51:06.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:51:06.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.11:51:06.67#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:06.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:51:06.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:51:06.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:51:06.79#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:51:06.79#ibcon#first serial, iclass 31, count 0 2006.285.11:51:06.79#ibcon#enter sib2, iclass 31, count 0 2006.285.11:51:06.79#ibcon#flushed, iclass 31, count 0 2006.285.11:51:06.79#ibcon#about to write, iclass 31, count 0 2006.285.11:51:06.79#ibcon#wrote, iclass 31, count 0 2006.285.11:51:06.79#ibcon#about to read 3, iclass 31, count 0 2006.285.11:51:06.81#ibcon#read 3, iclass 31, count 0 2006.285.11:51:06.81#ibcon#about to read 4, iclass 31, count 0 2006.285.11:51:06.81#ibcon#read 4, iclass 31, count 0 2006.285.11:51:06.81#ibcon#about to read 5, iclass 31, count 0 2006.285.11:51:06.81#ibcon#read 5, iclass 31, count 0 2006.285.11:51:06.81#ibcon#about to read 6, iclass 31, count 0 2006.285.11:51:06.81#ibcon#read 6, iclass 31, count 0 2006.285.11:51:06.81#ibcon#end of sib2, iclass 31, count 0 2006.285.11:51:06.81#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:51:06.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:51:06.81#ibcon#[25=USB\r\n] 2006.285.11:51:06.81#ibcon#*before write, iclass 31, count 0 2006.285.11:51:06.81#ibcon#enter sib2, iclass 31, count 0 2006.285.11:51:06.81#ibcon#flushed, iclass 31, count 0 2006.285.11:51:06.81#ibcon#about to write, iclass 31, count 0 2006.285.11:51:06.81#ibcon#wrote, iclass 31, count 0 2006.285.11:51:06.81#ibcon#about to read 3, iclass 31, count 0 2006.285.11:51:06.84#ibcon#read 3, iclass 31, count 0 2006.285.11:51:06.84#ibcon#about to read 4, iclass 31, count 0 2006.285.11:51:06.84#ibcon#read 4, iclass 31, count 0 2006.285.11:51:06.84#ibcon#about to read 5, iclass 31, count 0 2006.285.11:51:06.84#ibcon#read 5, iclass 31, count 0 2006.285.11:51:06.84#ibcon#about to read 6, iclass 31, count 0 2006.285.11:51:06.84#ibcon#read 6, iclass 31, count 0 2006.285.11:51:06.84#ibcon#end of sib2, iclass 31, count 0 2006.285.11:51:06.84#ibcon#*after write, iclass 31, count 0 2006.285.11:51:06.84#ibcon#*before return 0, iclass 31, count 0 2006.285.11:51:06.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:51:06.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:51:06.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:51:06.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:51:06.84$vck44/valo=4,624.99 2006.285.11:51:06.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.11:51:06.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.11:51:06.85#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:06.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:51:06.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:51:06.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:51:06.85#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:51:06.85#ibcon#first serial, iclass 33, count 0 2006.285.11:51:06.85#ibcon#enter sib2, iclass 33, count 0 2006.285.11:51:06.85#ibcon#flushed, iclass 33, count 0 2006.285.11:51:06.85#ibcon#about to write, iclass 33, count 0 2006.285.11:51:06.85#ibcon#wrote, iclass 33, count 0 2006.285.11:51:06.85#ibcon#about to read 3, iclass 33, count 0 2006.285.11:51:06.86#ibcon#read 3, iclass 33, count 0 2006.285.11:51:06.86#ibcon#about to read 4, iclass 33, count 0 2006.285.11:51:06.86#ibcon#read 4, iclass 33, count 0 2006.285.11:51:06.86#ibcon#about to read 5, iclass 33, count 0 2006.285.11:51:06.86#ibcon#read 5, iclass 33, count 0 2006.285.11:51:06.86#ibcon#about to read 6, iclass 33, count 0 2006.285.11:51:06.86#ibcon#read 6, iclass 33, count 0 2006.285.11:51:06.86#ibcon#end of sib2, iclass 33, count 0 2006.285.11:51:06.86#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:51:06.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:51:06.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:51:06.86#ibcon#*before write, iclass 33, count 0 2006.285.11:51:06.86#ibcon#enter sib2, iclass 33, count 0 2006.285.11:51:06.86#ibcon#flushed, iclass 33, count 0 2006.285.11:51:06.86#ibcon#about to write, iclass 33, count 0 2006.285.11:51:06.86#ibcon#wrote, iclass 33, count 0 2006.285.11:51:06.86#ibcon#about to read 3, iclass 33, count 0 2006.285.11:51:06.90#ibcon#read 3, iclass 33, count 0 2006.285.11:51:06.90#ibcon#about to read 4, iclass 33, count 0 2006.285.11:51:06.90#ibcon#read 4, iclass 33, count 0 2006.285.11:51:06.90#ibcon#about to read 5, iclass 33, count 0 2006.285.11:51:06.90#ibcon#read 5, iclass 33, count 0 2006.285.11:51:06.90#ibcon#about to read 6, iclass 33, count 0 2006.285.11:51:06.90#ibcon#read 6, iclass 33, count 0 2006.285.11:51:06.90#ibcon#end of sib2, iclass 33, count 0 2006.285.11:51:06.90#ibcon#*after write, iclass 33, count 0 2006.285.11:51:06.90#ibcon#*before return 0, iclass 33, count 0 2006.285.11:51:06.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:51:06.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:51:06.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:51:06.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:51:06.91$vck44/va=4,6 2006.285.11:51:06.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.11:51:06.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.11:51:06.91#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:06.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:51:06.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:51:06.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:51:06.95#ibcon#enter wrdev, iclass 35, count 2 2006.285.11:51:06.95#ibcon#first serial, iclass 35, count 2 2006.285.11:51:06.95#ibcon#enter sib2, iclass 35, count 2 2006.285.11:51:06.95#ibcon#flushed, iclass 35, count 2 2006.285.11:51:06.95#ibcon#about to write, iclass 35, count 2 2006.285.11:51:06.95#ibcon#wrote, iclass 35, count 2 2006.285.11:51:06.95#ibcon#about to read 3, iclass 35, count 2 2006.285.11:51:06.97#ibcon#read 3, iclass 35, count 2 2006.285.11:51:06.97#ibcon#about to read 4, iclass 35, count 2 2006.285.11:51:06.97#ibcon#read 4, iclass 35, count 2 2006.285.11:51:06.97#ibcon#about to read 5, iclass 35, count 2 2006.285.11:51:06.97#ibcon#read 5, iclass 35, count 2 2006.285.11:51:06.97#ibcon#about to read 6, iclass 35, count 2 2006.285.11:51:06.97#ibcon#read 6, iclass 35, count 2 2006.285.11:51:06.97#ibcon#end of sib2, iclass 35, count 2 2006.285.11:51:06.97#ibcon#*mode == 0, iclass 35, count 2 2006.285.11:51:06.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.11:51:06.97#ibcon#[25=AT04-06\r\n] 2006.285.11:51:06.97#ibcon#*before write, iclass 35, count 2 2006.285.11:51:06.97#ibcon#enter sib2, iclass 35, count 2 2006.285.11:51:06.97#ibcon#flushed, iclass 35, count 2 2006.285.11:51:06.97#ibcon#about to write, iclass 35, count 2 2006.285.11:51:06.97#ibcon#wrote, iclass 35, count 2 2006.285.11:51:06.97#ibcon#about to read 3, iclass 35, count 2 2006.285.11:51:07.00#ibcon#read 3, iclass 35, count 2 2006.285.11:51:07.00#ibcon#about to read 4, iclass 35, count 2 2006.285.11:51:07.00#ibcon#read 4, iclass 35, count 2 2006.285.11:51:07.00#ibcon#about to read 5, iclass 35, count 2 2006.285.11:51:07.00#ibcon#read 5, iclass 35, count 2 2006.285.11:51:07.00#ibcon#about to read 6, iclass 35, count 2 2006.285.11:51:07.00#ibcon#read 6, iclass 35, count 2 2006.285.11:51:07.00#ibcon#end of sib2, iclass 35, count 2 2006.285.11:51:07.00#ibcon#*after write, iclass 35, count 2 2006.285.11:51:07.00#ibcon#*before return 0, iclass 35, count 2 2006.285.11:51:07.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:51:07.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:51:07.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.11:51:07.00#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:07.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:51:07.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:51:07.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:51:07.12#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:51:07.12#ibcon#first serial, iclass 35, count 0 2006.285.11:51:07.12#ibcon#enter sib2, iclass 35, count 0 2006.285.11:51:07.12#ibcon#flushed, iclass 35, count 0 2006.285.11:51:07.12#ibcon#about to write, iclass 35, count 0 2006.285.11:51:07.12#ibcon#wrote, iclass 35, count 0 2006.285.11:51:07.12#ibcon#about to read 3, iclass 35, count 0 2006.285.11:51:07.14#ibcon#read 3, iclass 35, count 0 2006.285.11:51:07.14#ibcon#about to read 4, iclass 35, count 0 2006.285.11:51:07.14#ibcon#read 4, iclass 35, count 0 2006.285.11:51:07.14#ibcon#about to read 5, iclass 35, count 0 2006.285.11:51:07.14#ibcon#read 5, iclass 35, count 0 2006.285.11:51:07.14#ibcon#about to read 6, iclass 35, count 0 2006.285.11:51:07.14#ibcon#read 6, iclass 35, count 0 2006.285.11:51:07.14#ibcon#end of sib2, iclass 35, count 0 2006.285.11:51:07.14#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:51:07.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:51:07.14#ibcon#[25=USB\r\n] 2006.285.11:51:07.14#ibcon#*before write, iclass 35, count 0 2006.285.11:51:07.14#ibcon#enter sib2, iclass 35, count 0 2006.285.11:51:07.14#ibcon#flushed, iclass 35, count 0 2006.285.11:51:07.14#ibcon#about to write, iclass 35, count 0 2006.285.11:51:07.14#ibcon#wrote, iclass 35, count 0 2006.285.11:51:07.14#ibcon#about to read 3, iclass 35, count 0 2006.285.11:51:07.17#ibcon#read 3, iclass 35, count 0 2006.285.11:51:07.17#ibcon#about to read 4, iclass 35, count 0 2006.285.11:51:07.17#ibcon#read 4, iclass 35, count 0 2006.285.11:51:07.17#ibcon#about to read 5, iclass 35, count 0 2006.285.11:51:07.17#ibcon#read 5, iclass 35, count 0 2006.285.11:51:07.17#ibcon#about to read 6, iclass 35, count 0 2006.285.11:51:07.17#ibcon#read 6, iclass 35, count 0 2006.285.11:51:07.17#ibcon#end of sib2, iclass 35, count 0 2006.285.11:51:07.17#ibcon#*after write, iclass 35, count 0 2006.285.11:51:07.17#ibcon#*before return 0, iclass 35, count 0 2006.285.11:51:07.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:51:07.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:51:07.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:51:07.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:51:07.18$vck44/valo=5,734.99 2006.285.11:51:07.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.11:51:07.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.11:51:07.18#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:07.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:51:07.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:51:07.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:51:07.18#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:51:07.18#ibcon#first serial, iclass 37, count 0 2006.285.11:51:07.18#ibcon#enter sib2, iclass 37, count 0 2006.285.11:51:07.18#ibcon#flushed, iclass 37, count 0 2006.285.11:51:07.18#ibcon#about to write, iclass 37, count 0 2006.285.11:51:07.18#ibcon#wrote, iclass 37, count 0 2006.285.11:51:07.18#ibcon#about to read 3, iclass 37, count 0 2006.285.11:51:07.19#ibcon#read 3, iclass 37, count 0 2006.285.11:51:07.19#ibcon#about to read 4, iclass 37, count 0 2006.285.11:51:07.19#ibcon#read 4, iclass 37, count 0 2006.285.11:51:07.19#ibcon#about to read 5, iclass 37, count 0 2006.285.11:51:07.19#ibcon#read 5, iclass 37, count 0 2006.285.11:51:07.19#ibcon#about to read 6, iclass 37, count 0 2006.285.11:51:07.19#ibcon#read 6, iclass 37, count 0 2006.285.11:51:07.19#ibcon#end of sib2, iclass 37, count 0 2006.285.11:51:07.19#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:51:07.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:51:07.19#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:51:07.19#ibcon#*before write, iclass 37, count 0 2006.285.11:51:07.19#ibcon#enter sib2, iclass 37, count 0 2006.285.11:51:07.19#ibcon#flushed, iclass 37, count 0 2006.285.11:51:07.19#ibcon#about to write, iclass 37, count 0 2006.285.11:51:07.19#ibcon#wrote, iclass 37, count 0 2006.285.11:51:07.19#ibcon#about to read 3, iclass 37, count 0 2006.285.11:51:07.23#ibcon#read 3, iclass 37, count 0 2006.285.11:51:07.23#ibcon#about to read 4, iclass 37, count 0 2006.285.11:51:07.23#ibcon#read 4, iclass 37, count 0 2006.285.11:51:07.23#ibcon#about to read 5, iclass 37, count 0 2006.285.11:51:07.23#ibcon#read 5, iclass 37, count 0 2006.285.11:51:07.23#ibcon#about to read 6, iclass 37, count 0 2006.285.11:51:07.23#ibcon#read 6, iclass 37, count 0 2006.285.11:51:07.23#ibcon#end of sib2, iclass 37, count 0 2006.285.11:51:07.23#ibcon#*after write, iclass 37, count 0 2006.285.11:51:07.23#ibcon#*before return 0, iclass 37, count 0 2006.285.11:51:07.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:51:07.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:51:07.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:51:07.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:51:07.23$vck44/va=5,3 2006.285.11:51:07.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.11:51:07.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.11:51:07.24#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:07.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:51:07.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:51:07.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:51:07.28#ibcon#enter wrdev, iclass 39, count 2 2006.285.11:51:07.28#ibcon#first serial, iclass 39, count 2 2006.285.11:51:07.28#ibcon#enter sib2, iclass 39, count 2 2006.285.11:51:07.28#ibcon#flushed, iclass 39, count 2 2006.285.11:51:07.28#ibcon#about to write, iclass 39, count 2 2006.285.11:51:07.28#ibcon#wrote, iclass 39, count 2 2006.285.11:51:07.28#ibcon#about to read 3, iclass 39, count 2 2006.285.11:51:07.30#ibcon#read 3, iclass 39, count 2 2006.285.11:51:07.30#ibcon#about to read 4, iclass 39, count 2 2006.285.11:51:07.30#ibcon#read 4, iclass 39, count 2 2006.285.11:51:07.30#ibcon#about to read 5, iclass 39, count 2 2006.285.11:51:07.30#ibcon#read 5, iclass 39, count 2 2006.285.11:51:07.30#ibcon#about to read 6, iclass 39, count 2 2006.285.11:51:07.30#ibcon#read 6, iclass 39, count 2 2006.285.11:51:07.30#ibcon#end of sib2, iclass 39, count 2 2006.285.11:51:07.30#ibcon#*mode == 0, iclass 39, count 2 2006.285.11:51:07.30#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.11:51:07.30#ibcon#[25=AT05-03\r\n] 2006.285.11:51:07.30#ibcon#*before write, iclass 39, count 2 2006.285.11:51:07.30#ibcon#enter sib2, iclass 39, count 2 2006.285.11:51:07.30#ibcon#flushed, iclass 39, count 2 2006.285.11:51:07.30#ibcon#about to write, iclass 39, count 2 2006.285.11:51:07.30#ibcon#wrote, iclass 39, count 2 2006.285.11:51:07.30#ibcon#about to read 3, iclass 39, count 2 2006.285.11:51:07.33#ibcon#read 3, iclass 39, count 2 2006.285.11:51:07.33#ibcon#about to read 4, iclass 39, count 2 2006.285.11:51:07.33#ibcon#read 4, iclass 39, count 2 2006.285.11:51:07.33#ibcon#about to read 5, iclass 39, count 2 2006.285.11:51:07.33#ibcon#read 5, iclass 39, count 2 2006.285.11:51:07.33#ibcon#about to read 6, iclass 39, count 2 2006.285.11:51:07.33#ibcon#read 6, iclass 39, count 2 2006.285.11:51:07.33#ibcon#end of sib2, iclass 39, count 2 2006.285.11:51:07.33#ibcon#*after write, iclass 39, count 2 2006.285.11:51:07.33#ibcon#*before return 0, iclass 39, count 2 2006.285.11:51:07.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:51:07.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:51:07.33#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.11:51:07.33#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:07.33#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:51:07.45#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:51:07.45#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:51:07.45#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:51:07.45#ibcon#first serial, iclass 39, count 0 2006.285.11:51:07.45#ibcon#enter sib2, iclass 39, count 0 2006.285.11:51:07.45#ibcon#flushed, iclass 39, count 0 2006.285.11:51:07.45#ibcon#about to write, iclass 39, count 0 2006.285.11:51:07.45#ibcon#wrote, iclass 39, count 0 2006.285.11:51:07.45#ibcon#about to read 3, iclass 39, count 0 2006.285.11:51:07.47#ibcon#read 3, iclass 39, count 0 2006.285.11:51:07.47#ibcon#about to read 4, iclass 39, count 0 2006.285.11:51:07.47#ibcon#read 4, iclass 39, count 0 2006.285.11:51:07.47#ibcon#about to read 5, iclass 39, count 0 2006.285.11:51:07.47#ibcon#read 5, iclass 39, count 0 2006.285.11:51:07.47#ibcon#about to read 6, iclass 39, count 0 2006.285.11:51:07.47#ibcon#read 6, iclass 39, count 0 2006.285.11:51:07.47#ibcon#end of sib2, iclass 39, count 0 2006.285.11:51:07.47#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:51:07.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:51:07.47#ibcon#[25=USB\r\n] 2006.285.11:51:07.47#ibcon#*before write, iclass 39, count 0 2006.285.11:51:07.47#ibcon#enter sib2, iclass 39, count 0 2006.285.11:51:07.47#ibcon#flushed, iclass 39, count 0 2006.285.11:51:07.47#ibcon#about to write, iclass 39, count 0 2006.285.11:51:07.47#ibcon#wrote, iclass 39, count 0 2006.285.11:51:07.47#ibcon#about to read 3, iclass 39, count 0 2006.285.11:51:07.50#ibcon#read 3, iclass 39, count 0 2006.285.11:51:07.50#ibcon#about to read 4, iclass 39, count 0 2006.285.11:51:07.50#ibcon#read 4, iclass 39, count 0 2006.285.11:51:07.50#ibcon#about to read 5, iclass 39, count 0 2006.285.11:51:07.50#ibcon#read 5, iclass 39, count 0 2006.285.11:51:07.50#ibcon#about to read 6, iclass 39, count 0 2006.285.11:51:07.50#ibcon#read 6, iclass 39, count 0 2006.285.11:51:07.50#ibcon#end of sib2, iclass 39, count 0 2006.285.11:51:07.50#ibcon#*after write, iclass 39, count 0 2006.285.11:51:07.50#ibcon#*before return 0, iclass 39, count 0 2006.285.11:51:07.50#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:51:07.50#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:51:07.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:51:07.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:51:07.51$vck44/valo=6,814.99 2006.285.11:51:07.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.11:51:07.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.11:51:07.51#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:07.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:51:07.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:51:07.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:51:07.51#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:51:07.51#ibcon#first serial, iclass 3, count 0 2006.285.11:51:07.51#ibcon#enter sib2, iclass 3, count 0 2006.285.11:51:07.51#ibcon#flushed, iclass 3, count 0 2006.285.11:51:07.51#ibcon#about to write, iclass 3, count 0 2006.285.11:51:07.51#ibcon#wrote, iclass 3, count 0 2006.285.11:51:07.51#ibcon#about to read 3, iclass 3, count 0 2006.285.11:51:07.52#ibcon#read 3, iclass 3, count 0 2006.285.11:51:07.52#ibcon#about to read 4, iclass 3, count 0 2006.285.11:51:07.52#ibcon#read 4, iclass 3, count 0 2006.285.11:51:07.52#ibcon#about to read 5, iclass 3, count 0 2006.285.11:51:07.52#ibcon#read 5, iclass 3, count 0 2006.285.11:51:07.52#ibcon#about to read 6, iclass 3, count 0 2006.285.11:51:07.52#ibcon#read 6, iclass 3, count 0 2006.285.11:51:07.52#ibcon#end of sib2, iclass 3, count 0 2006.285.11:51:07.52#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:51:07.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:51:07.52#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:51:07.52#ibcon#*before write, iclass 3, count 0 2006.285.11:51:07.52#ibcon#enter sib2, iclass 3, count 0 2006.285.11:51:07.52#ibcon#flushed, iclass 3, count 0 2006.285.11:51:07.52#ibcon#about to write, iclass 3, count 0 2006.285.11:51:07.52#ibcon#wrote, iclass 3, count 0 2006.285.11:51:07.52#ibcon#about to read 3, iclass 3, count 0 2006.285.11:51:07.56#ibcon#read 3, iclass 3, count 0 2006.285.11:51:07.56#ibcon#about to read 4, iclass 3, count 0 2006.285.11:51:07.56#ibcon#read 4, iclass 3, count 0 2006.285.11:51:07.56#ibcon#about to read 5, iclass 3, count 0 2006.285.11:51:07.56#ibcon#read 5, iclass 3, count 0 2006.285.11:51:07.56#ibcon#about to read 6, iclass 3, count 0 2006.285.11:51:07.56#ibcon#read 6, iclass 3, count 0 2006.285.11:51:07.56#ibcon#end of sib2, iclass 3, count 0 2006.285.11:51:07.56#ibcon#*after write, iclass 3, count 0 2006.285.11:51:07.56#ibcon#*before return 0, iclass 3, count 0 2006.285.11:51:07.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:51:07.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:51:07.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:51:07.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:51:07.56$vck44/va=6,4 2006.285.11:51:07.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.11:51:07.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.11:51:07.57#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:07.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:51:07.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:51:07.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:51:07.61#ibcon#enter wrdev, iclass 5, count 2 2006.285.11:51:07.61#ibcon#first serial, iclass 5, count 2 2006.285.11:51:07.61#ibcon#enter sib2, iclass 5, count 2 2006.285.11:51:07.61#ibcon#flushed, iclass 5, count 2 2006.285.11:51:07.61#ibcon#about to write, iclass 5, count 2 2006.285.11:51:07.61#ibcon#wrote, iclass 5, count 2 2006.285.11:51:07.61#ibcon#about to read 3, iclass 5, count 2 2006.285.11:51:07.63#ibcon#read 3, iclass 5, count 2 2006.285.11:51:07.63#ibcon#about to read 4, iclass 5, count 2 2006.285.11:51:07.63#ibcon#read 4, iclass 5, count 2 2006.285.11:51:07.63#ibcon#about to read 5, iclass 5, count 2 2006.285.11:51:07.63#ibcon#read 5, iclass 5, count 2 2006.285.11:51:07.63#ibcon#about to read 6, iclass 5, count 2 2006.285.11:51:07.63#ibcon#read 6, iclass 5, count 2 2006.285.11:51:07.63#ibcon#end of sib2, iclass 5, count 2 2006.285.11:51:07.63#ibcon#*mode == 0, iclass 5, count 2 2006.285.11:51:07.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.11:51:07.63#ibcon#[25=AT06-04\r\n] 2006.285.11:51:07.63#ibcon#*before write, iclass 5, count 2 2006.285.11:51:07.63#ibcon#enter sib2, iclass 5, count 2 2006.285.11:51:07.63#ibcon#flushed, iclass 5, count 2 2006.285.11:51:07.63#ibcon#about to write, iclass 5, count 2 2006.285.11:51:07.63#ibcon#wrote, iclass 5, count 2 2006.285.11:51:07.63#ibcon#about to read 3, iclass 5, count 2 2006.285.11:51:07.66#ibcon#read 3, iclass 5, count 2 2006.285.11:51:07.66#ibcon#about to read 4, iclass 5, count 2 2006.285.11:51:07.66#ibcon#read 4, iclass 5, count 2 2006.285.11:51:07.66#ibcon#about to read 5, iclass 5, count 2 2006.285.11:51:07.66#ibcon#read 5, iclass 5, count 2 2006.285.11:51:07.66#ibcon#about to read 6, iclass 5, count 2 2006.285.11:51:07.66#ibcon#read 6, iclass 5, count 2 2006.285.11:51:07.66#ibcon#end of sib2, iclass 5, count 2 2006.285.11:51:07.66#ibcon#*after write, iclass 5, count 2 2006.285.11:51:07.66#ibcon#*before return 0, iclass 5, count 2 2006.285.11:51:07.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:51:07.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:51:07.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.11:51:07.66#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:07.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:51:07.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:51:07.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:51:07.78#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:51:07.78#ibcon#first serial, iclass 5, count 0 2006.285.11:51:07.78#ibcon#enter sib2, iclass 5, count 0 2006.285.11:51:07.78#ibcon#flushed, iclass 5, count 0 2006.285.11:51:07.78#ibcon#about to write, iclass 5, count 0 2006.285.11:51:07.78#ibcon#wrote, iclass 5, count 0 2006.285.11:51:07.78#ibcon#about to read 3, iclass 5, count 0 2006.285.11:51:07.80#ibcon#read 3, iclass 5, count 0 2006.285.11:51:07.80#ibcon#about to read 4, iclass 5, count 0 2006.285.11:51:07.80#ibcon#read 4, iclass 5, count 0 2006.285.11:51:07.80#ibcon#about to read 5, iclass 5, count 0 2006.285.11:51:07.80#ibcon#read 5, iclass 5, count 0 2006.285.11:51:07.80#ibcon#about to read 6, iclass 5, count 0 2006.285.11:51:07.80#ibcon#read 6, iclass 5, count 0 2006.285.11:51:07.80#ibcon#end of sib2, iclass 5, count 0 2006.285.11:51:07.80#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:51:07.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:51:07.80#ibcon#[25=USB\r\n] 2006.285.11:51:07.80#ibcon#*before write, iclass 5, count 0 2006.285.11:51:07.80#ibcon#enter sib2, iclass 5, count 0 2006.285.11:51:07.80#ibcon#flushed, iclass 5, count 0 2006.285.11:51:07.80#ibcon#about to write, iclass 5, count 0 2006.285.11:51:07.80#ibcon#wrote, iclass 5, count 0 2006.285.11:51:07.80#ibcon#about to read 3, iclass 5, count 0 2006.285.11:51:07.83#ibcon#read 3, iclass 5, count 0 2006.285.11:51:07.83#ibcon#about to read 4, iclass 5, count 0 2006.285.11:51:07.83#ibcon#read 4, iclass 5, count 0 2006.285.11:51:07.83#ibcon#about to read 5, iclass 5, count 0 2006.285.11:51:07.83#ibcon#read 5, iclass 5, count 0 2006.285.11:51:07.83#ibcon#about to read 6, iclass 5, count 0 2006.285.11:51:07.83#ibcon#read 6, iclass 5, count 0 2006.285.11:51:07.83#ibcon#end of sib2, iclass 5, count 0 2006.285.11:51:07.83#ibcon#*after write, iclass 5, count 0 2006.285.11:51:07.83#ibcon#*before return 0, iclass 5, count 0 2006.285.11:51:07.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:51:07.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:51:07.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:51:07.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:51:07.83$vck44/valo=7,864.99 2006.285.11:51:07.84#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.11:51:07.84#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.11:51:07.84#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:07.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:51:07.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:51:07.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:51:07.84#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:51:07.84#ibcon#first serial, iclass 7, count 0 2006.285.11:51:07.84#ibcon#enter sib2, iclass 7, count 0 2006.285.11:51:07.84#ibcon#flushed, iclass 7, count 0 2006.285.11:51:07.84#ibcon#about to write, iclass 7, count 0 2006.285.11:51:07.84#ibcon#wrote, iclass 7, count 0 2006.285.11:51:07.84#ibcon#about to read 3, iclass 7, count 0 2006.285.11:51:07.85#ibcon#read 3, iclass 7, count 0 2006.285.11:51:07.85#ibcon#about to read 4, iclass 7, count 0 2006.285.11:51:07.85#ibcon#read 4, iclass 7, count 0 2006.285.11:51:07.85#ibcon#about to read 5, iclass 7, count 0 2006.285.11:51:07.85#ibcon#read 5, iclass 7, count 0 2006.285.11:51:07.85#ibcon#about to read 6, iclass 7, count 0 2006.285.11:51:07.85#ibcon#read 6, iclass 7, count 0 2006.285.11:51:07.85#ibcon#end of sib2, iclass 7, count 0 2006.285.11:51:07.85#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:51:07.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:51:07.85#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:51:07.85#ibcon#*before write, iclass 7, count 0 2006.285.11:51:07.85#ibcon#enter sib2, iclass 7, count 0 2006.285.11:51:07.85#ibcon#flushed, iclass 7, count 0 2006.285.11:51:07.85#ibcon#about to write, iclass 7, count 0 2006.285.11:51:07.85#ibcon#wrote, iclass 7, count 0 2006.285.11:51:07.85#ibcon#about to read 3, iclass 7, count 0 2006.285.11:51:07.89#ibcon#read 3, iclass 7, count 0 2006.285.11:51:07.89#ibcon#about to read 4, iclass 7, count 0 2006.285.11:51:07.89#ibcon#read 4, iclass 7, count 0 2006.285.11:51:07.89#ibcon#about to read 5, iclass 7, count 0 2006.285.11:51:07.89#ibcon#read 5, iclass 7, count 0 2006.285.11:51:07.89#ibcon#about to read 6, iclass 7, count 0 2006.285.11:51:07.89#ibcon#read 6, iclass 7, count 0 2006.285.11:51:07.89#ibcon#end of sib2, iclass 7, count 0 2006.285.11:51:07.89#ibcon#*after write, iclass 7, count 0 2006.285.11:51:07.89#ibcon#*before return 0, iclass 7, count 0 2006.285.11:51:07.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:51:07.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:51:07.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:51:07.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:51:07.90$vck44/va=7,4 2006.285.11:51:07.90#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.11:51:07.90#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.11:51:07.90#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:07.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:51:07.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:51:07.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:51:07.94#ibcon#enter wrdev, iclass 11, count 2 2006.285.11:51:07.94#ibcon#first serial, iclass 11, count 2 2006.285.11:51:07.94#ibcon#enter sib2, iclass 11, count 2 2006.285.11:51:07.94#ibcon#flushed, iclass 11, count 2 2006.285.11:51:07.94#ibcon#about to write, iclass 11, count 2 2006.285.11:51:07.94#ibcon#wrote, iclass 11, count 2 2006.285.11:51:07.94#ibcon#about to read 3, iclass 11, count 2 2006.285.11:51:07.96#ibcon#read 3, iclass 11, count 2 2006.285.11:51:07.96#ibcon#about to read 4, iclass 11, count 2 2006.285.11:51:07.96#ibcon#read 4, iclass 11, count 2 2006.285.11:51:07.96#ibcon#about to read 5, iclass 11, count 2 2006.285.11:51:07.96#ibcon#read 5, iclass 11, count 2 2006.285.11:51:07.96#ibcon#about to read 6, iclass 11, count 2 2006.285.11:51:07.96#ibcon#read 6, iclass 11, count 2 2006.285.11:51:07.96#ibcon#end of sib2, iclass 11, count 2 2006.285.11:51:07.96#ibcon#*mode == 0, iclass 11, count 2 2006.285.11:51:07.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.11:51:07.96#ibcon#[25=AT07-04\r\n] 2006.285.11:51:07.96#ibcon#*before write, iclass 11, count 2 2006.285.11:51:07.96#ibcon#enter sib2, iclass 11, count 2 2006.285.11:51:07.96#ibcon#flushed, iclass 11, count 2 2006.285.11:51:07.96#ibcon#about to write, iclass 11, count 2 2006.285.11:51:07.96#ibcon#wrote, iclass 11, count 2 2006.285.11:51:07.96#ibcon#about to read 3, iclass 11, count 2 2006.285.11:51:07.99#ibcon#read 3, iclass 11, count 2 2006.285.11:51:07.99#ibcon#about to read 4, iclass 11, count 2 2006.285.11:51:07.99#ibcon#read 4, iclass 11, count 2 2006.285.11:51:07.99#ibcon#about to read 5, iclass 11, count 2 2006.285.11:51:07.99#ibcon#read 5, iclass 11, count 2 2006.285.11:51:07.99#ibcon#about to read 6, iclass 11, count 2 2006.285.11:51:07.99#ibcon#read 6, iclass 11, count 2 2006.285.11:51:07.99#ibcon#end of sib2, iclass 11, count 2 2006.285.11:51:07.99#ibcon#*after write, iclass 11, count 2 2006.285.11:51:07.99#ibcon#*before return 0, iclass 11, count 2 2006.285.11:51:07.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:51:07.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:51:07.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.11:51:07.99#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:07.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:51:08.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:51:08.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:51:08.11#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:51:08.11#ibcon#first serial, iclass 11, count 0 2006.285.11:51:08.11#ibcon#enter sib2, iclass 11, count 0 2006.285.11:51:08.11#ibcon#flushed, iclass 11, count 0 2006.285.11:51:08.11#ibcon#about to write, iclass 11, count 0 2006.285.11:51:08.11#ibcon#wrote, iclass 11, count 0 2006.285.11:51:08.11#ibcon#about to read 3, iclass 11, count 0 2006.285.11:51:08.13#ibcon#read 3, iclass 11, count 0 2006.285.11:51:08.13#ibcon#about to read 4, iclass 11, count 0 2006.285.11:51:08.13#ibcon#read 4, iclass 11, count 0 2006.285.11:51:08.13#ibcon#about to read 5, iclass 11, count 0 2006.285.11:51:08.13#ibcon#read 5, iclass 11, count 0 2006.285.11:51:08.13#ibcon#about to read 6, iclass 11, count 0 2006.285.11:51:08.13#ibcon#read 6, iclass 11, count 0 2006.285.11:51:08.13#ibcon#end of sib2, iclass 11, count 0 2006.285.11:51:08.13#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:51:08.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:51:08.13#ibcon#[25=USB\r\n] 2006.285.11:51:08.13#ibcon#*before write, iclass 11, count 0 2006.285.11:51:08.13#ibcon#enter sib2, iclass 11, count 0 2006.285.11:51:08.13#ibcon#flushed, iclass 11, count 0 2006.285.11:51:08.13#ibcon#about to write, iclass 11, count 0 2006.285.11:51:08.13#ibcon#wrote, iclass 11, count 0 2006.285.11:51:08.13#ibcon#about to read 3, iclass 11, count 0 2006.285.11:51:08.16#ibcon#read 3, iclass 11, count 0 2006.285.11:51:08.16#ibcon#about to read 4, iclass 11, count 0 2006.285.11:51:08.16#ibcon#read 4, iclass 11, count 0 2006.285.11:51:08.16#ibcon#about to read 5, iclass 11, count 0 2006.285.11:51:08.16#ibcon#read 5, iclass 11, count 0 2006.285.11:51:08.16#ibcon#about to read 6, iclass 11, count 0 2006.285.11:51:08.16#ibcon#read 6, iclass 11, count 0 2006.285.11:51:08.16#ibcon#end of sib2, iclass 11, count 0 2006.285.11:51:08.16#ibcon#*after write, iclass 11, count 0 2006.285.11:51:08.16#ibcon#*before return 0, iclass 11, count 0 2006.285.11:51:08.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:51:08.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:51:08.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:51:08.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:51:08.17$vck44/valo=8,884.99 2006.285.11:51:08.17#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.11:51:08.17#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.11:51:08.17#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:08.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:51:08.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:51:08.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:51:08.17#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:51:08.17#ibcon#first serial, iclass 13, count 0 2006.285.11:51:08.17#ibcon#enter sib2, iclass 13, count 0 2006.285.11:51:08.17#ibcon#flushed, iclass 13, count 0 2006.285.11:51:08.17#ibcon#about to write, iclass 13, count 0 2006.285.11:51:08.17#ibcon#wrote, iclass 13, count 0 2006.285.11:51:08.17#ibcon#about to read 3, iclass 13, count 0 2006.285.11:51:08.18#ibcon#read 3, iclass 13, count 0 2006.285.11:51:08.18#ibcon#about to read 4, iclass 13, count 0 2006.285.11:51:08.18#ibcon#read 4, iclass 13, count 0 2006.285.11:51:08.18#ibcon#about to read 5, iclass 13, count 0 2006.285.11:51:08.18#ibcon#read 5, iclass 13, count 0 2006.285.11:51:08.18#ibcon#about to read 6, iclass 13, count 0 2006.285.11:51:08.18#ibcon#read 6, iclass 13, count 0 2006.285.11:51:08.18#ibcon#end of sib2, iclass 13, count 0 2006.285.11:51:08.18#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:51:08.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:51:08.18#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:51:08.18#ibcon#*before write, iclass 13, count 0 2006.285.11:51:08.18#ibcon#enter sib2, iclass 13, count 0 2006.285.11:51:08.18#ibcon#flushed, iclass 13, count 0 2006.285.11:51:08.18#ibcon#about to write, iclass 13, count 0 2006.285.11:51:08.18#ibcon#wrote, iclass 13, count 0 2006.285.11:51:08.18#ibcon#about to read 3, iclass 13, count 0 2006.285.11:51:08.22#ibcon#read 3, iclass 13, count 0 2006.285.11:51:08.22#ibcon#about to read 4, iclass 13, count 0 2006.285.11:51:08.22#ibcon#read 4, iclass 13, count 0 2006.285.11:51:08.22#ibcon#about to read 5, iclass 13, count 0 2006.285.11:51:08.22#ibcon#read 5, iclass 13, count 0 2006.285.11:51:08.22#ibcon#about to read 6, iclass 13, count 0 2006.285.11:51:08.22#ibcon#read 6, iclass 13, count 0 2006.285.11:51:08.22#ibcon#end of sib2, iclass 13, count 0 2006.285.11:51:08.22#ibcon#*after write, iclass 13, count 0 2006.285.11:51:08.22#ibcon#*before return 0, iclass 13, count 0 2006.285.11:51:08.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:51:08.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:51:08.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:51:08.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:51:08.23$vck44/va=8,3 2006.285.11:51:08.23#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.11:51:08.23#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.11:51:08.23#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:08.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:51:08.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:51:08.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:51:08.27#ibcon#enter wrdev, iclass 15, count 2 2006.285.11:51:08.27#ibcon#first serial, iclass 15, count 2 2006.285.11:51:08.27#ibcon#enter sib2, iclass 15, count 2 2006.285.11:51:08.27#ibcon#flushed, iclass 15, count 2 2006.285.11:51:08.27#ibcon#about to write, iclass 15, count 2 2006.285.11:51:08.27#ibcon#wrote, iclass 15, count 2 2006.285.11:51:08.27#ibcon#about to read 3, iclass 15, count 2 2006.285.11:51:08.29#ibcon#read 3, iclass 15, count 2 2006.285.11:51:08.29#ibcon#about to read 4, iclass 15, count 2 2006.285.11:51:08.29#ibcon#read 4, iclass 15, count 2 2006.285.11:51:08.29#ibcon#about to read 5, iclass 15, count 2 2006.285.11:51:08.29#ibcon#read 5, iclass 15, count 2 2006.285.11:51:08.29#ibcon#about to read 6, iclass 15, count 2 2006.285.11:51:08.29#ibcon#read 6, iclass 15, count 2 2006.285.11:51:08.29#ibcon#end of sib2, iclass 15, count 2 2006.285.11:51:08.29#ibcon#*mode == 0, iclass 15, count 2 2006.285.11:51:08.29#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.11:51:08.29#ibcon#[25=AT08-03\r\n] 2006.285.11:51:08.29#ibcon#*before write, iclass 15, count 2 2006.285.11:51:08.29#ibcon#enter sib2, iclass 15, count 2 2006.285.11:51:08.29#ibcon#flushed, iclass 15, count 2 2006.285.11:51:08.29#ibcon#about to write, iclass 15, count 2 2006.285.11:51:08.29#ibcon#wrote, iclass 15, count 2 2006.285.11:51:08.29#ibcon#about to read 3, iclass 15, count 2 2006.285.11:51:08.32#ibcon#read 3, iclass 15, count 2 2006.285.11:51:08.32#ibcon#about to read 4, iclass 15, count 2 2006.285.11:51:08.32#ibcon#read 4, iclass 15, count 2 2006.285.11:51:08.32#ibcon#about to read 5, iclass 15, count 2 2006.285.11:51:08.32#ibcon#read 5, iclass 15, count 2 2006.285.11:51:08.32#ibcon#about to read 6, iclass 15, count 2 2006.285.11:51:08.32#ibcon#read 6, iclass 15, count 2 2006.285.11:51:08.32#ibcon#end of sib2, iclass 15, count 2 2006.285.11:51:08.32#ibcon#*after write, iclass 15, count 2 2006.285.11:51:08.32#ibcon#*before return 0, iclass 15, count 2 2006.285.11:51:08.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:51:08.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.11:51:08.32#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.11:51:08.32#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:08.32#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:51:08.44#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:51:08.44#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:51:08.44#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:51:08.44#ibcon#first serial, iclass 15, count 0 2006.285.11:51:08.44#ibcon#enter sib2, iclass 15, count 0 2006.285.11:51:08.44#ibcon#flushed, iclass 15, count 0 2006.285.11:51:08.44#ibcon#about to write, iclass 15, count 0 2006.285.11:51:08.44#ibcon#wrote, iclass 15, count 0 2006.285.11:51:08.44#ibcon#about to read 3, iclass 15, count 0 2006.285.11:51:08.46#ibcon#read 3, iclass 15, count 0 2006.285.11:51:08.46#ibcon#about to read 4, iclass 15, count 0 2006.285.11:51:08.46#ibcon#read 4, iclass 15, count 0 2006.285.11:51:08.46#ibcon#about to read 5, iclass 15, count 0 2006.285.11:51:08.46#ibcon#read 5, iclass 15, count 0 2006.285.11:51:08.46#ibcon#about to read 6, iclass 15, count 0 2006.285.11:51:08.46#ibcon#read 6, iclass 15, count 0 2006.285.11:51:08.46#ibcon#end of sib2, iclass 15, count 0 2006.285.11:51:08.46#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:51:08.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:51:08.46#ibcon#[25=USB\r\n] 2006.285.11:51:08.46#ibcon#*before write, iclass 15, count 0 2006.285.11:51:08.46#ibcon#enter sib2, iclass 15, count 0 2006.285.11:51:08.46#ibcon#flushed, iclass 15, count 0 2006.285.11:51:08.46#ibcon#about to write, iclass 15, count 0 2006.285.11:51:08.46#ibcon#wrote, iclass 15, count 0 2006.285.11:51:08.46#ibcon#about to read 3, iclass 15, count 0 2006.285.11:51:08.49#ibcon#read 3, iclass 15, count 0 2006.285.11:51:08.49#ibcon#about to read 4, iclass 15, count 0 2006.285.11:51:08.49#ibcon#read 4, iclass 15, count 0 2006.285.11:51:08.49#ibcon#about to read 5, iclass 15, count 0 2006.285.11:51:08.49#ibcon#read 5, iclass 15, count 0 2006.285.11:51:08.49#ibcon#about to read 6, iclass 15, count 0 2006.285.11:51:08.49#ibcon#read 6, iclass 15, count 0 2006.285.11:51:08.49#ibcon#end of sib2, iclass 15, count 0 2006.285.11:51:08.49#ibcon#*after write, iclass 15, count 0 2006.285.11:51:08.49#ibcon#*before return 0, iclass 15, count 0 2006.285.11:51:08.49#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:51:08.49#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.11:51:08.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:51:08.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:51:08.50$vck44/vblo=1,629.99 2006.285.11:51:08.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.11:51:08.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.11:51:08.50#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:08.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:51:08.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:51:08.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:51:08.50#ibcon#enter wrdev, iclass 17, count 0 2006.285.11:51:08.50#ibcon#first serial, iclass 17, count 0 2006.285.11:51:08.50#ibcon#enter sib2, iclass 17, count 0 2006.285.11:51:08.50#ibcon#flushed, iclass 17, count 0 2006.285.11:51:08.50#ibcon#about to write, iclass 17, count 0 2006.285.11:51:08.50#ibcon#wrote, iclass 17, count 0 2006.285.11:51:08.50#ibcon#about to read 3, iclass 17, count 0 2006.285.11:51:08.51#ibcon#read 3, iclass 17, count 0 2006.285.11:51:08.51#ibcon#about to read 4, iclass 17, count 0 2006.285.11:51:08.51#ibcon#read 4, iclass 17, count 0 2006.285.11:51:08.51#ibcon#about to read 5, iclass 17, count 0 2006.285.11:51:08.51#ibcon#read 5, iclass 17, count 0 2006.285.11:51:08.51#ibcon#about to read 6, iclass 17, count 0 2006.285.11:51:08.51#ibcon#read 6, iclass 17, count 0 2006.285.11:51:08.51#ibcon#end of sib2, iclass 17, count 0 2006.285.11:51:08.51#ibcon#*mode == 0, iclass 17, count 0 2006.285.11:51:08.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.11:51:08.51#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:51:08.51#ibcon#*before write, iclass 17, count 0 2006.285.11:51:08.51#ibcon#enter sib2, iclass 17, count 0 2006.285.11:51:08.51#ibcon#flushed, iclass 17, count 0 2006.285.11:51:08.51#ibcon#about to write, iclass 17, count 0 2006.285.11:51:08.51#ibcon#wrote, iclass 17, count 0 2006.285.11:51:08.51#ibcon#about to read 3, iclass 17, count 0 2006.285.11:51:08.55#ibcon#read 3, iclass 17, count 0 2006.285.11:51:08.55#ibcon#about to read 4, iclass 17, count 0 2006.285.11:51:08.55#ibcon#read 4, iclass 17, count 0 2006.285.11:51:08.55#ibcon#about to read 5, iclass 17, count 0 2006.285.11:51:08.55#ibcon#read 5, iclass 17, count 0 2006.285.11:51:08.55#ibcon#about to read 6, iclass 17, count 0 2006.285.11:51:08.55#ibcon#read 6, iclass 17, count 0 2006.285.11:51:08.55#ibcon#end of sib2, iclass 17, count 0 2006.285.11:51:08.55#ibcon#*after write, iclass 17, count 0 2006.285.11:51:08.55#ibcon#*before return 0, iclass 17, count 0 2006.285.11:51:08.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:51:08.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.11:51:08.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.11:51:08.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.11:51:08.55$vck44/vb=1,4 2006.285.11:51:08.56#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.11:51:08.56#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.11:51:08.56#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:08.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:51:08.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:51:08.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:51:08.56#ibcon#enter wrdev, iclass 19, count 2 2006.285.11:51:08.56#ibcon#first serial, iclass 19, count 2 2006.285.11:51:08.56#ibcon#enter sib2, iclass 19, count 2 2006.285.11:51:08.56#ibcon#flushed, iclass 19, count 2 2006.285.11:51:08.56#ibcon#about to write, iclass 19, count 2 2006.285.11:51:08.56#ibcon#wrote, iclass 19, count 2 2006.285.11:51:08.56#ibcon#about to read 3, iclass 19, count 2 2006.285.11:51:08.57#ibcon#read 3, iclass 19, count 2 2006.285.11:51:08.57#ibcon#about to read 4, iclass 19, count 2 2006.285.11:51:08.57#ibcon#read 4, iclass 19, count 2 2006.285.11:51:08.57#ibcon#about to read 5, iclass 19, count 2 2006.285.11:51:08.57#ibcon#read 5, iclass 19, count 2 2006.285.11:51:08.57#ibcon#about to read 6, iclass 19, count 2 2006.285.11:51:08.57#ibcon#read 6, iclass 19, count 2 2006.285.11:51:08.57#ibcon#end of sib2, iclass 19, count 2 2006.285.11:51:08.57#ibcon#*mode == 0, iclass 19, count 2 2006.285.11:51:08.57#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.11:51:08.57#ibcon#[27=AT01-04\r\n] 2006.285.11:51:08.57#ibcon#*before write, iclass 19, count 2 2006.285.11:51:08.57#ibcon#enter sib2, iclass 19, count 2 2006.285.11:51:08.57#ibcon#flushed, iclass 19, count 2 2006.285.11:51:08.57#ibcon#about to write, iclass 19, count 2 2006.285.11:51:08.57#ibcon#wrote, iclass 19, count 2 2006.285.11:51:08.57#ibcon#about to read 3, iclass 19, count 2 2006.285.11:51:08.60#ibcon#read 3, iclass 19, count 2 2006.285.11:51:08.60#ibcon#about to read 4, iclass 19, count 2 2006.285.11:51:08.60#ibcon#read 4, iclass 19, count 2 2006.285.11:51:08.60#ibcon#about to read 5, iclass 19, count 2 2006.285.11:51:08.60#ibcon#read 5, iclass 19, count 2 2006.285.11:51:08.60#ibcon#about to read 6, iclass 19, count 2 2006.285.11:51:08.60#ibcon#read 6, iclass 19, count 2 2006.285.11:51:08.60#ibcon#end of sib2, iclass 19, count 2 2006.285.11:51:08.60#ibcon#*after write, iclass 19, count 2 2006.285.11:51:08.60#ibcon#*before return 0, iclass 19, count 2 2006.285.11:51:08.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:51:08.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.11:51:08.60#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.11:51:08.60#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:08.60#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:51:08.72#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:51:08.72#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:51:08.72#ibcon#enter wrdev, iclass 19, count 0 2006.285.11:51:08.72#ibcon#first serial, iclass 19, count 0 2006.285.11:51:08.72#ibcon#enter sib2, iclass 19, count 0 2006.285.11:51:08.72#ibcon#flushed, iclass 19, count 0 2006.285.11:51:08.72#ibcon#about to write, iclass 19, count 0 2006.285.11:51:08.72#ibcon#wrote, iclass 19, count 0 2006.285.11:51:08.72#ibcon#about to read 3, iclass 19, count 0 2006.285.11:51:08.74#ibcon#read 3, iclass 19, count 0 2006.285.11:51:08.74#ibcon#about to read 4, iclass 19, count 0 2006.285.11:51:08.74#ibcon#read 4, iclass 19, count 0 2006.285.11:51:08.74#ibcon#about to read 5, iclass 19, count 0 2006.285.11:51:08.74#ibcon#read 5, iclass 19, count 0 2006.285.11:51:08.74#ibcon#about to read 6, iclass 19, count 0 2006.285.11:51:08.74#ibcon#read 6, iclass 19, count 0 2006.285.11:51:08.74#ibcon#end of sib2, iclass 19, count 0 2006.285.11:51:08.74#ibcon#*mode == 0, iclass 19, count 0 2006.285.11:51:08.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.11:51:08.74#ibcon#[27=USB\r\n] 2006.285.11:51:08.74#ibcon#*before write, iclass 19, count 0 2006.285.11:51:08.74#ibcon#enter sib2, iclass 19, count 0 2006.285.11:51:08.74#ibcon#flushed, iclass 19, count 0 2006.285.11:51:08.74#ibcon#about to write, iclass 19, count 0 2006.285.11:51:08.74#ibcon#wrote, iclass 19, count 0 2006.285.11:51:08.74#ibcon#about to read 3, iclass 19, count 0 2006.285.11:51:08.77#ibcon#read 3, iclass 19, count 0 2006.285.11:51:08.77#ibcon#about to read 4, iclass 19, count 0 2006.285.11:51:08.77#ibcon#read 4, iclass 19, count 0 2006.285.11:51:08.77#ibcon#about to read 5, iclass 19, count 0 2006.285.11:51:08.77#ibcon#read 5, iclass 19, count 0 2006.285.11:51:08.77#ibcon#about to read 6, iclass 19, count 0 2006.285.11:51:08.77#ibcon#read 6, iclass 19, count 0 2006.285.11:51:08.77#ibcon#end of sib2, iclass 19, count 0 2006.285.11:51:08.77#ibcon#*after write, iclass 19, count 0 2006.285.11:51:08.77#ibcon#*before return 0, iclass 19, count 0 2006.285.11:51:08.77#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:51:08.77#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.11:51:08.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.11:51:08.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.11:51:08.78$vck44/vblo=2,634.99 2006.285.11:51:08.78#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.11:51:08.78#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.11:51:08.78#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:08.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:51:08.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:51:08.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:51:08.78#ibcon#enter wrdev, iclass 21, count 0 2006.285.11:51:08.78#ibcon#first serial, iclass 21, count 0 2006.285.11:51:08.78#ibcon#enter sib2, iclass 21, count 0 2006.285.11:51:08.78#ibcon#flushed, iclass 21, count 0 2006.285.11:51:08.78#ibcon#about to write, iclass 21, count 0 2006.285.11:51:08.78#ibcon#wrote, iclass 21, count 0 2006.285.11:51:08.78#ibcon#about to read 3, iclass 21, count 0 2006.285.11:51:08.79#ibcon#read 3, iclass 21, count 0 2006.285.11:51:08.79#ibcon#about to read 4, iclass 21, count 0 2006.285.11:51:08.79#ibcon#read 4, iclass 21, count 0 2006.285.11:51:08.79#ibcon#about to read 5, iclass 21, count 0 2006.285.11:51:08.79#ibcon#read 5, iclass 21, count 0 2006.285.11:51:08.79#ibcon#about to read 6, iclass 21, count 0 2006.285.11:51:08.79#ibcon#read 6, iclass 21, count 0 2006.285.11:51:08.79#ibcon#end of sib2, iclass 21, count 0 2006.285.11:51:08.79#ibcon#*mode == 0, iclass 21, count 0 2006.285.11:51:08.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.11:51:08.79#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:51:08.79#ibcon#*before write, iclass 21, count 0 2006.285.11:51:08.79#ibcon#enter sib2, iclass 21, count 0 2006.285.11:51:08.79#ibcon#flushed, iclass 21, count 0 2006.285.11:51:08.79#ibcon#about to write, iclass 21, count 0 2006.285.11:51:08.79#ibcon#wrote, iclass 21, count 0 2006.285.11:51:08.79#ibcon#about to read 3, iclass 21, count 0 2006.285.11:51:08.83#ibcon#read 3, iclass 21, count 0 2006.285.11:51:08.83#ibcon#about to read 4, iclass 21, count 0 2006.285.11:51:08.83#ibcon#read 4, iclass 21, count 0 2006.285.11:51:08.83#ibcon#about to read 5, iclass 21, count 0 2006.285.11:51:08.83#ibcon#read 5, iclass 21, count 0 2006.285.11:51:08.83#ibcon#about to read 6, iclass 21, count 0 2006.285.11:51:08.83#ibcon#read 6, iclass 21, count 0 2006.285.11:51:08.83#ibcon#end of sib2, iclass 21, count 0 2006.285.11:51:08.83#ibcon#*after write, iclass 21, count 0 2006.285.11:51:08.83#ibcon#*before return 0, iclass 21, count 0 2006.285.11:51:08.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:51:08.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.11:51:08.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.11:51:08.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.11:51:08.83$vck44/vb=2,5 2006.285.11:51:08.84#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.11:51:08.84#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.11:51:08.84#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:08.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:51:08.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:51:08.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:51:08.88#ibcon#enter wrdev, iclass 23, count 2 2006.285.11:51:08.88#ibcon#first serial, iclass 23, count 2 2006.285.11:51:08.88#ibcon#enter sib2, iclass 23, count 2 2006.285.11:51:08.88#ibcon#flushed, iclass 23, count 2 2006.285.11:51:08.88#ibcon#about to write, iclass 23, count 2 2006.285.11:51:08.88#ibcon#wrote, iclass 23, count 2 2006.285.11:51:08.88#ibcon#about to read 3, iclass 23, count 2 2006.285.11:51:08.90#ibcon#read 3, iclass 23, count 2 2006.285.11:51:08.90#ibcon#about to read 4, iclass 23, count 2 2006.285.11:51:08.90#ibcon#read 4, iclass 23, count 2 2006.285.11:51:08.90#ibcon#about to read 5, iclass 23, count 2 2006.285.11:51:08.90#ibcon#read 5, iclass 23, count 2 2006.285.11:51:08.90#ibcon#about to read 6, iclass 23, count 2 2006.285.11:51:08.90#ibcon#read 6, iclass 23, count 2 2006.285.11:51:08.90#ibcon#end of sib2, iclass 23, count 2 2006.285.11:51:08.90#ibcon#*mode == 0, iclass 23, count 2 2006.285.11:51:08.90#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.11:51:08.90#ibcon#[27=AT02-05\r\n] 2006.285.11:51:08.90#ibcon#*before write, iclass 23, count 2 2006.285.11:51:08.90#ibcon#enter sib2, iclass 23, count 2 2006.285.11:51:08.90#ibcon#flushed, iclass 23, count 2 2006.285.11:51:08.90#ibcon#about to write, iclass 23, count 2 2006.285.11:51:08.90#ibcon#wrote, iclass 23, count 2 2006.285.11:51:08.90#ibcon#about to read 3, iclass 23, count 2 2006.285.11:51:08.93#ibcon#read 3, iclass 23, count 2 2006.285.11:51:08.93#ibcon#about to read 4, iclass 23, count 2 2006.285.11:51:08.93#ibcon#read 4, iclass 23, count 2 2006.285.11:51:08.93#ibcon#about to read 5, iclass 23, count 2 2006.285.11:51:08.93#ibcon#read 5, iclass 23, count 2 2006.285.11:51:08.93#ibcon#about to read 6, iclass 23, count 2 2006.285.11:51:08.93#ibcon#read 6, iclass 23, count 2 2006.285.11:51:08.93#ibcon#end of sib2, iclass 23, count 2 2006.285.11:51:08.93#ibcon#*after write, iclass 23, count 2 2006.285.11:51:08.93#ibcon#*before return 0, iclass 23, count 2 2006.285.11:51:08.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:51:08.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.11:51:08.93#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.11:51:08.93#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:08.93#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:51:09.05#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:51:09.05#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:51:09.05#ibcon#enter wrdev, iclass 23, count 0 2006.285.11:51:09.05#ibcon#first serial, iclass 23, count 0 2006.285.11:51:09.05#ibcon#enter sib2, iclass 23, count 0 2006.285.11:51:09.05#ibcon#flushed, iclass 23, count 0 2006.285.11:51:09.05#ibcon#about to write, iclass 23, count 0 2006.285.11:51:09.05#ibcon#wrote, iclass 23, count 0 2006.285.11:51:09.05#ibcon#about to read 3, iclass 23, count 0 2006.285.11:51:09.07#ibcon#read 3, iclass 23, count 0 2006.285.11:51:09.07#ibcon#about to read 4, iclass 23, count 0 2006.285.11:51:09.07#ibcon#read 4, iclass 23, count 0 2006.285.11:51:09.07#ibcon#about to read 5, iclass 23, count 0 2006.285.11:51:09.07#ibcon#read 5, iclass 23, count 0 2006.285.11:51:09.07#ibcon#about to read 6, iclass 23, count 0 2006.285.11:51:09.07#ibcon#read 6, iclass 23, count 0 2006.285.11:51:09.07#ibcon#end of sib2, iclass 23, count 0 2006.285.11:51:09.07#ibcon#*mode == 0, iclass 23, count 0 2006.285.11:51:09.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.11:51:09.07#ibcon#[27=USB\r\n] 2006.285.11:51:09.07#ibcon#*before write, iclass 23, count 0 2006.285.11:51:09.07#ibcon#enter sib2, iclass 23, count 0 2006.285.11:51:09.07#ibcon#flushed, iclass 23, count 0 2006.285.11:51:09.07#ibcon#about to write, iclass 23, count 0 2006.285.11:51:09.07#ibcon#wrote, iclass 23, count 0 2006.285.11:51:09.07#ibcon#about to read 3, iclass 23, count 0 2006.285.11:51:09.10#ibcon#read 3, iclass 23, count 0 2006.285.11:51:09.10#ibcon#about to read 4, iclass 23, count 0 2006.285.11:51:09.10#ibcon#read 4, iclass 23, count 0 2006.285.11:51:09.10#ibcon#about to read 5, iclass 23, count 0 2006.285.11:51:09.10#ibcon#read 5, iclass 23, count 0 2006.285.11:51:09.10#ibcon#about to read 6, iclass 23, count 0 2006.285.11:51:09.10#ibcon#read 6, iclass 23, count 0 2006.285.11:51:09.10#ibcon#end of sib2, iclass 23, count 0 2006.285.11:51:09.10#ibcon#*after write, iclass 23, count 0 2006.285.11:51:09.10#ibcon#*before return 0, iclass 23, count 0 2006.285.11:51:09.10#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:51:09.10#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.11:51:09.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.11:51:09.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.11:51:09.11$vck44/vblo=3,649.99 2006.285.11:51:09.11#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.11:51:09.11#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.11:51:09.11#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:09.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:51:09.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:51:09.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:51:09.11#ibcon#enter wrdev, iclass 25, count 0 2006.285.11:51:09.11#ibcon#first serial, iclass 25, count 0 2006.285.11:51:09.11#ibcon#enter sib2, iclass 25, count 0 2006.285.11:51:09.11#ibcon#flushed, iclass 25, count 0 2006.285.11:51:09.11#ibcon#about to write, iclass 25, count 0 2006.285.11:51:09.11#ibcon#wrote, iclass 25, count 0 2006.285.11:51:09.11#ibcon#about to read 3, iclass 25, count 0 2006.285.11:51:09.12#ibcon#read 3, iclass 25, count 0 2006.285.11:51:09.12#ibcon#about to read 4, iclass 25, count 0 2006.285.11:51:09.12#ibcon#read 4, iclass 25, count 0 2006.285.11:51:09.12#ibcon#about to read 5, iclass 25, count 0 2006.285.11:51:09.12#ibcon#read 5, iclass 25, count 0 2006.285.11:51:09.12#ibcon#about to read 6, iclass 25, count 0 2006.285.11:51:09.12#ibcon#read 6, iclass 25, count 0 2006.285.11:51:09.12#ibcon#end of sib2, iclass 25, count 0 2006.285.11:51:09.12#ibcon#*mode == 0, iclass 25, count 0 2006.285.11:51:09.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.11:51:09.12#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:51:09.12#ibcon#*before write, iclass 25, count 0 2006.285.11:51:09.12#ibcon#enter sib2, iclass 25, count 0 2006.285.11:51:09.12#ibcon#flushed, iclass 25, count 0 2006.285.11:51:09.12#ibcon#about to write, iclass 25, count 0 2006.285.11:51:09.12#ibcon#wrote, iclass 25, count 0 2006.285.11:51:09.12#ibcon#about to read 3, iclass 25, count 0 2006.285.11:51:09.16#ibcon#read 3, iclass 25, count 0 2006.285.11:51:09.16#ibcon#about to read 4, iclass 25, count 0 2006.285.11:51:09.16#ibcon#read 4, iclass 25, count 0 2006.285.11:51:09.16#ibcon#about to read 5, iclass 25, count 0 2006.285.11:51:09.16#ibcon#read 5, iclass 25, count 0 2006.285.11:51:09.16#ibcon#about to read 6, iclass 25, count 0 2006.285.11:51:09.16#ibcon#read 6, iclass 25, count 0 2006.285.11:51:09.16#ibcon#end of sib2, iclass 25, count 0 2006.285.11:51:09.16#ibcon#*after write, iclass 25, count 0 2006.285.11:51:09.16#ibcon#*before return 0, iclass 25, count 0 2006.285.11:51:09.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:51:09.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.11:51:09.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.11:51:09.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.11:51:09.17$vck44/vb=3,4 2006.285.11:51:09.17#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.11:51:09.17#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.11:51:09.17#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:09.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:51:09.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:51:09.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:51:09.21#ibcon#enter wrdev, iclass 27, count 2 2006.285.11:51:09.21#ibcon#first serial, iclass 27, count 2 2006.285.11:51:09.21#ibcon#enter sib2, iclass 27, count 2 2006.285.11:51:09.21#ibcon#flushed, iclass 27, count 2 2006.285.11:51:09.21#ibcon#about to write, iclass 27, count 2 2006.285.11:51:09.21#ibcon#wrote, iclass 27, count 2 2006.285.11:51:09.21#ibcon#about to read 3, iclass 27, count 2 2006.285.11:51:09.23#ibcon#read 3, iclass 27, count 2 2006.285.11:51:09.23#ibcon#about to read 4, iclass 27, count 2 2006.285.11:51:09.23#ibcon#read 4, iclass 27, count 2 2006.285.11:51:09.23#ibcon#about to read 5, iclass 27, count 2 2006.285.11:51:09.23#ibcon#read 5, iclass 27, count 2 2006.285.11:51:09.23#ibcon#about to read 6, iclass 27, count 2 2006.285.11:51:09.23#ibcon#read 6, iclass 27, count 2 2006.285.11:51:09.23#ibcon#end of sib2, iclass 27, count 2 2006.285.11:51:09.23#ibcon#*mode == 0, iclass 27, count 2 2006.285.11:51:09.23#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.11:51:09.23#ibcon#[27=AT03-04\r\n] 2006.285.11:51:09.23#ibcon#*before write, iclass 27, count 2 2006.285.11:51:09.23#ibcon#enter sib2, iclass 27, count 2 2006.285.11:51:09.23#ibcon#flushed, iclass 27, count 2 2006.285.11:51:09.23#ibcon#about to write, iclass 27, count 2 2006.285.11:51:09.23#ibcon#wrote, iclass 27, count 2 2006.285.11:51:09.23#ibcon#about to read 3, iclass 27, count 2 2006.285.11:51:09.26#ibcon#read 3, iclass 27, count 2 2006.285.11:51:09.26#ibcon#about to read 4, iclass 27, count 2 2006.285.11:51:09.26#ibcon#read 4, iclass 27, count 2 2006.285.11:51:09.26#ibcon#about to read 5, iclass 27, count 2 2006.285.11:51:09.26#ibcon#read 5, iclass 27, count 2 2006.285.11:51:09.26#ibcon#about to read 6, iclass 27, count 2 2006.285.11:51:09.26#ibcon#read 6, iclass 27, count 2 2006.285.11:51:09.26#ibcon#end of sib2, iclass 27, count 2 2006.285.11:51:09.26#ibcon#*after write, iclass 27, count 2 2006.285.11:51:09.26#ibcon#*before return 0, iclass 27, count 2 2006.285.11:51:09.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:51:09.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.11:51:09.26#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.11:51:09.26#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:09.26#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:51:09.38#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:51:09.38#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:51:09.38#ibcon#enter wrdev, iclass 27, count 0 2006.285.11:51:09.38#ibcon#first serial, iclass 27, count 0 2006.285.11:51:09.38#ibcon#enter sib2, iclass 27, count 0 2006.285.11:51:09.38#ibcon#flushed, iclass 27, count 0 2006.285.11:51:09.38#ibcon#about to write, iclass 27, count 0 2006.285.11:51:09.38#ibcon#wrote, iclass 27, count 0 2006.285.11:51:09.38#ibcon#about to read 3, iclass 27, count 0 2006.285.11:51:09.40#ibcon#read 3, iclass 27, count 0 2006.285.11:51:09.40#ibcon#about to read 4, iclass 27, count 0 2006.285.11:51:09.40#ibcon#read 4, iclass 27, count 0 2006.285.11:51:09.40#ibcon#about to read 5, iclass 27, count 0 2006.285.11:51:09.40#ibcon#read 5, iclass 27, count 0 2006.285.11:51:09.40#ibcon#about to read 6, iclass 27, count 0 2006.285.11:51:09.40#ibcon#read 6, iclass 27, count 0 2006.285.11:51:09.40#ibcon#end of sib2, iclass 27, count 0 2006.285.11:51:09.40#ibcon#*mode == 0, iclass 27, count 0 2006.285.11:51:09.40#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.11:51:09.40#ibcon#[27=USB\r\n] 2006.285.11:51:09.40#ibcon#*before write, iclass 27, count 0 2006.285.11:51:09.40#ibcon#enter sib2, iclass 27, count 0 2006.285.11:51:09.40#ibcon#flushed, iclass 27, count 0 2006.285.11:51:09.40#ibcon#about to write, iclass 27, count 0 2006.285.11:51:09.40#ibcon#wrote, iclass 27, count 0 2006.285.11:51:09.40#ibcon#about to read 3, iclass 27, count 0 2006.285.11:51:09.43#ibcon#read 3, iclass 27, count 0 2006.285.11:51:09.43#ibcon#about to read 4, iclass 27, count 0 2006.285.11:51:09.43#ibcon#read 4, iclass 27, count 0 2006.285.11:51:09.43#ibcon#about to read 5, iclass 27, count 0 2006.285.11:51:09.43#ibcon#read 5, iclass 27, count 0 2006.285.11:51:09.43#ibcon#about to read 6, iclass 27, count 0 2006.285.11:51:09.43#ibcon#read 6, iclass 27, count 0 2006.285.11:51:09.43#ibcon#end of sib2, iclass 27, count 0 2006.285.11:51:09.43#ibcon#*after write, iclass 27, count 0 2006.285.11:51:09.43#ibcon#*before return 0, iclass 27, count 0 2006.285.11:51:09.43#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:51:09.43#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.11:51:09.43#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.11:51:09.43#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.11:51:09.43$vck44/vblo=4,679.99 2006.285.11:51:09.44#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.11:51:09.44#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.11:51:09.44#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:09.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:51:09.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:51:09.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:51:09.44#ibcon#enter wrdev, iclass 29, count 0 2006.285.11:51:09.44#ibcon#first serial, iclass 29, count 0 2006.285.11:51:09.44#ibcon#enter sib2, iclass 29, count 0 2006.285.11:51:09.44#ibcon#flushed, iclass 29, count 0 2006.285.11:51:09.44#ibcon#about to write, iclass 29, count 0 2006.285.11:51:09.44#ibcon#wrote, iclass 29, count 0 2006.285.11:51:09.44#ibcon#about to read 3, iclass 29, count 0 2006.285.11:51:09.45#ibcon#read 3, iclass 29, count 0 2006.285.11:51:09.45#ibcon#about to read 4, iclass 29, count 0 2006.285.11:51:09.45#ibcon#read 4, iclass 29, count 0 2006.285.11:51:09.45#ibcon#about to read 5, iclass 29, count 0 2006.285.11:51:09.45#ibcon#read 5, iclass 29, count 0 2006.285.11:51:09.45#ibcon#about to read 6, iclass 29, count 0 2006.285.11:51:09.45#ibcon#read 6, iclass 29, count 0 2006.285.11:51:09.45#ibcon#end of sib2, iclass 29, count 0 2006.285.11:51:09.45#ibcon#*mode == 0, iclass 29, count 0 2006.285.11:51:09.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.11:51:09.45#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:51:09.45#ibcon#*before write, iclass 29, count 0 2006.285.11:51:09.45#ibcon#enter sib2, iclass 29, count 0 2006.285.11:51:09.45#ibcon#flushed, iclass 29, count 0 2006.285.11:51:09.45#ibcon#about to write, iclass 29, count 0 2006.285.11:51:09.45#ibcon#wrote, iclass 29, count 0 2006.285.11:51:09.45#ibcon#about to read 3, iclass 29, count 0 2006.285.11:51:09.49#ibcon#read 3, iclass 29, count 0 2006.285.11:51:09.49#ibcon#about to read 4, iclass 29, count 0 2006.285.11:51:09.49#ibcon#read 4, iclass 29, count 0 2006.285.11:51:09.49#ibcon#about to read 5, iclass 29, count 0 2006.285.11:51:09.49#ibcon#read 5, iclass 29, count 0 2006.285.11:51:09.49#ibcon#about to read 6, iclass 29, count 0 2006.285.11:51:09.49#ibcon#read 6, iclass 29, count 0 2006.285.11:51:09.49#ibcon#end of sib2, iclass 29, count 0 2006.285.11:51:09.49#ibcon#*after write, iclass 29, count 0 2006.285.11:51:09.49#ibcon#*before return 0, iclass 29, count 0 2006.285.11:51:09.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:51:09.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.11:51:09.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.11:51:09.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.11:51:09.50$vck44/vb=4,5 2006.285.11:51:09.50#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.11:51:09.50#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.11:51:09.50#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:09.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:51:09.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:51:09.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:51:09.54#ibcon#enter wrdev, iclass 31, count 2 2006.285.11:51:09.54#ibcon#first serial, iclass 31, count 2 2006.285.11:51:09.54#ibcon#enter sib2, iclass 31, count 2 2006.285.11:51:09.54#ibcon#flushed, iclass 31, count 2 2006.285.11:51:09.54#ibcon#about to write, iclass 31, count 2 2006.285.11:51:09.54#ibcon#wrote, iclass 31, count 2 2006.285.11:51:09.54#ibcon#about to read 3, iclass 31, count 2 2006.285.11:51:09.56#ibcon#read 3, iclass 31, count 2 2006.285.11:51:09.56#ibcon#about to read 4, iclass 31, count 2 2006.285.11:51:09.56#ibcon#read 4, iclass 31, count 2 2006.285.11:51:09.56#ibcon#about to read 5, iclass 31, count 2 2006.285.11:51:09.56#ibcon#read 5, iclass 31, count 2 2006.285.11:51:09.56#ibcon#about to read 6, iclass 31, count 2 2006.285.11:51:09.56#ibcon#read 6, iclass 31, count 2 2006.285.11:51:09.56#ibcon#end of sib2, iclass 31, count 2 2006.285.11:51:09.56#ibcon#*mode == 0, iclass 31, count 2 2006.285.11:51:09.56#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.11:51:09.56#ibcon#[27=AT04-05\r\n] 2006.285.11:51:09.56#ibcon#*before write, iclass 31, count 2 2006.285.11:51:09.56#ibcon#enter sib2, iclass 31, count 2 2006.285.11:51:09.56#ibcon#flushed, iclass 31, count 2 2006.285.11:51:09.56#ibcon#about to write, iclass 31, count 2 2006.285.11:51:09.56#ibcon#wrote, iclass 31, count 2 2006.285.11:51:09.56#ibcon#about to read 3, iclass 31, count 2 2006.285.11:51:09.59#ibcon#read 3, iclass 31, count 2 2006.285.11:51:09.59#ibcon#about to read 4, iclass 31, count 2 2006.285.11:51:09.59#ibcon#read 4, iclass 31, count 2 2006.285.11:51:09.59#ibcon#about to read 5, iclass 31, count 2 2006.285.11:51:09.59#ibcon#read 5, iclass 31, count 2 2006.285.11:51:09.59#ibcon#about to read 6, iclass 31, count 2 2006.285.11:51:09.59#ibcon#read 6, iclass 31, count 2 2006.285.11:51:09.59#ibcon#end of sib2, iclass 31, count 2 2006.285.11:51:09.59#ibcon#*after write, iclass 31, count 2 2006.285.11:51:09.59#ibcon#*before return 0, iclass 31, count 2 2006.285.11:51:09.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:51:09.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.11:51:09.59#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.11:51:09.59#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:09.59#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:51:09.71#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:51:09.71#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:51:09.71#ibcon#enter wrdev, iclass 31, count 0 2006.285.11:51:09.71#ibcon#first serial, iclass 31, count 0 2006.285.11:51:09.71#ibcon#enter sib2, iclass 31, count 0 2006.285.11:51:09.71#ibcon#flushed, iclass 31, count 0 2006.285.11:51:09.71#ibcon#about to write, iclass 31, count 0 2006.285.11:51:09.71#ibcon#wrote, iclass 31, count 0 2006.285.11:51:09.71#ibcon#about to read 3, iclass 31, count 0 2006.285.11:51:09.73#ibcon#read 3, iclass 31, count 0 2006.285.11:51:09.73#ibcon#about to read 4, iclass 31, count 0 2006.285.11:51:09.73#ibcon#read 4, iclass 31, count 0 2006.285.11:51:09.73#ibcon#about to read 5, iclass 31, count 0 2006.285.11:51:09.73#ibcon#read 5, iclass 31, count 0 2006.285.11:51:09.73#ibcon#about to read 6, iclass 31, count 0 2006.285.11:51:09.73#ibcon#read 6, iclass 31, count 0 2006.285.11:51:09.73#ibcon#end of sib2, iclass 31, count 0 2006.285.11:51:09.73#ibcon#*mode == 0, iclass 31, count 0 2006.285.11:51:09.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.11:51:09.73#ibcon#[27=USB\r\n] 2006.285.11:51:09.73#ibcon#*before write, iclass 31, count 0 2006.285.11:51:09.73#ibcon#enter sib2, iclass 31, count 0 2006.285.11:51:09.73#ibcon#flushed, iclass 31, count 0 2006.285.11:51:09.73#ibcon#about to write, iclass 31, count 0 2006.285.11:51:09.73#ibcon#wrote, iclass 31, count 0 2006.285.11:51:09.73#ibcon#about to read 3, iclass 31, count 0 2006.285.11:51:09.76#ibcon#read 3, iclass 31, count 0 2006.285.11:51:09.76#ibcon#about to read 4, iclass 31, count 0 2006.285.11:51:09.76#ibcon#read 4, iclass 31, count 0 2006.285.11:51:09.76#ibcon#about to read 5, iclass 31, count 0 2006.285.11:51:09.76#ibcon#read 5, iclass 31, count 0 2006.285.11:51:09.76#ibcon#about to read 6, iclass 31, count 0 2006.285.11:51:09.76#ibcon#read 6, iclass 31, count 0 2006.285.11:51:09.76#ibcon#end of sib2, iclass 31, count 0 2006.285.11:51:09.76#ibcon#*after write, iclass 31, count 0 2006.285.11:51:09.76#ibcon#*before return 0, iclass 31, count 0 2006.285.11:51:09.76#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:51:09.76#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.11:51:09.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.11:51:09.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.11:51:09.76$vck44/vblo=5,709.99 2006.285.11:51:09.77#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.11:51:09.77#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.11:51:09.77#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:09.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:51:09.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:51:09.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:51:09.77#ibcon#enter wrdev, iclass 33, count 0 2006.285.11:51:09.77#ibcon#first serial, iclass 33, count 0 2006.285.11:51:09.77#ibcon#enter sib2, iclass 33, count 0 2006.285.11:51:09.77#ibcon#flushed, iclass 33, count 0 2006.285.11:51:09.77#ibcon#about to write, iclass 33, count 0 2006.285.11:51:09.77#ibcon#wrote, iclass 33, count 0 2006.285.11:51:09.77#ibcon#about to read 3, iclass 33, count 0 2006.285.11:51:09.78#ibcon#read 3, iclass 33, count 0 2006.285.11:51:09.78#ibcon#about to read 4, iclass 33, count 0 2006.285.11:51:09.78#ibcon#read 4, iclass 33, count 0 2006.285.11:51:09.78#ibcon#about to read 5, iclass 33, count 0 2006.285.11:51:09.78#ibcon#read 5, iclass 33, count 0 2006.285.11:51:09.78#ibcon#about to read 6, iclass 33, count 0 2006.285.11:51:09.78#ibcon#read 6, iclass 33, count 0 2006.285.11:51:09.78#ibcon#end of sib2, iclass 33, count 0 2006.285.11:51:09.78#ibcon#*mode == 0, iclass 33, count 0 2006.285.11:51:09.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.11:51:09.78#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:51:09.78#ibcon#*before write, iclass 33, count 0 2006.285.11:51:09.78#ibcon#enter sib2, iclass 33, count 0 2006.285.11:51:09.78#ibcon#flushed, iclass 33, count 0 2006.285.11:51:09.78#ibcon#about to write, iclass 33, count 0 2006.285.11:51:09.78#ibcon#wrote, iclass 33, count 0 2006.285.11:51:09.78#ibcon#about to read 3, iclass 33, count 0 2006.285.11:51:09.82#ibcon#read 3, iclass 33, count 0 2006.285.11:51:09.82#ibcon#about to read 4, iclass 33, count 0 2006.285.11:51:09.82#ibcon#read 4, iclass 33, count 0 2006.285.11:51:09.82#ibcon#about to read 5, iclass 33, count 0 2006.285.11:51:09.82#ibcon#read 5, iclass 33, count 0 2006.285.11:51:09.82#ibcon#about to read 6, iclass 33, count 0 2006.285.11:51:09.82#ibcon#read 6, iclass 33, count 0 2006.285.11:51:09.82#ibcon#end of sib2, iclass 33, count 0 2006.285.11:51:09.82#ibcon#*after write, iclass 33, count 0 2006.285.11:51:09.82#ibcon#*before return 0, iclass 33, count 0 2006.285.11:51:09.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:51:09.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.11:51:09.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.11:51:09.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.11:51:09.83$vck44/vb=5,4 2006.285.11:51:09.83#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.11:51:09.83#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.11:51:09.83#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:09.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:51:09.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:51:09.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:51:09.87#ibcon#enter wrdev, iclass 35, count 2 2006.285.11:51:09.87#ibcon#first serial, iclass 35, count 2 2006.285.11:51:09.87#ibcon#enter sib2, iclass 35, count 2 2006.285.11:51:09.87#ibcon#flushed, iclass 35, count 2 2006.285.11:51:09.87#ibcon#about to write, iclass 35, count 2 2006.285.11:51:09.87#ibcon#wrote, iclass 35, count 2 2006.285.11:51:09.87#ibcon#about to read 3, iclass 35, count 2 2006.285.11:51:09.89#ibcon#read 3, iclass 35, count 2 2006.285.11:51:09.89#ibcon#about to read 4, iclass 35, count 2 2006.285.11:51:09.89#ibcon#read 4, iclass 35, count 2 2006.285.11:51:09.89#ibcon#about to read 5, iclass 35, count 2 2006.285.11:51:09.89#ibcon#read 5, iclass 35, count 2 2006.285.11:51:09.89#ibcon#about to read 6, iclass 35, count 2 2006.285.11:51:09.89#ibcon#read 6, iclass 35, count 2 2006.285.11:51:09.89#ibcon#end of sib2, iclass 35, count 2 2006.285.11:51:09.89#ibcon#*mode == 0, iclass 35, count 2 2006.285.11:51:09.89#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.11:51:09.89#ibcon#[27=AT05-04\r\n] 2006.285.11:51:09.89#ibcon#*before write, iclass 35, count 2 2006.285.11:51:09.89#ibcon#enter sib2, iclass 35, count 2 2006.285.11:51:09.89#ibcon#flushed, iclass 35, count 2 2006.285.11:51:09.89#ibcon#about to write, iclass 35, count 2 2006.285.11:51:09.89#ibcon#wrote, iclass 35, count 2 2006.285.11:51:09.89#ibcon#about to read 3, iclass 35, count 2 2006.285.11:51:09.92#ibcon#read 3, iclass 35, count 2 2006.285.11:51:09.92#ibcon#about to read 4, iclass 35, count 2 2006.285.11:51:09.92#ibcon#read 4, iclass 35, count 2 2006.285.11:51:09.92#ibcon#about to read 5, iclass 35, count 2 2006.285.11:51:09.92#ibcon#read 5, iclass 35, count 2 2006.285.11:51:09.92#ibcon#about to read 6, iclass 35, count 2 2006.285.11:51:09.92#ibcon#read 6, iclass 35, count 2 2006.285.11:51:09.92#ibcon#end of sib2, iclass 35, count 2 2006.285.11:51:09.92#ibcon#*after write, iclass 35, count 2 2006.285.11:51:09.92#ibcon#*before return 0, iclass 35, count 2 2006.285.11:51:09.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:51:09.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.11:51:09.92#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.11:51:09.92#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:09.92#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:51:10.04#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:51:10.04#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:51:10.04#ibcon#enter wrdev, iclass 35, count 0 2006.285.11:51:10.04#ibcon#first serial, iclass 35, count 0 2006.285.11:51:10.04#ibcon#enter sib2, iclass 35, count 0 2006.285.11:51:10.04#ibcon#flushed, iclass 35, count 0 2006.285.11:51:10.04#ibcon#about to write, iclass 35, count 0 2006.285.11:51:10.04#ibcon#wrote, iclass 35, count 0 2006.285.11:51:10.04#ibcon#about to read 3, iclass 35, count 0 2006.285.11:51:10.06#ibcon#read 3, iclass 35, count 0 2006.285.11:51:10.06#ibcon#about to read 4, iclass 35, count 0 2006.285.11:51:10.06#ibcon#read 4, iclass 35, count 0 2006.285.11:51:10.06#ibcon#about to read 5, iclass 35, count 0 2006.285.11:51:10.06#ibcon#read 5, iclass 35, count 0 2006.285.11:51:10.06#ibcon#about to read 6, iclass 35, count 0 2006.285.11:51:10.06#ibcon#read 6, iclass 35, count 0 2006.285.11:51:10.06#ibcon#end of sib2, iclass 35, count 0 2006.285.11:51:10.06#ibcon#*mode == 0, iclass 35, count 0 2006.285.11:51:10.06#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.11:51:10.06#ibcon#[27=USB\r\n] 2006.285.11:51:10.06#ibcon#*before write, iclass 35, count 0 2006.285.11:51:10.06#ibcon#enter sib2, iclass 35, count 0 2006.285.11:51:10.06#ibcon#flushed, iclass 35, count 0 2006.285.11:51:10.06#ibcon#about to write, iclass 35, count 0 2006.285.11:51:10.06#ibcon#wrote, iclass 35, count 0 2006.285.11:51:10.06#ibcon#about to read 3, iclass 35, count 0 2006.285.11:51:10.09#ibcon#read 3, iclass 35, count 0 2006.285.11:51:10.09#ibcon#about to read 4, iclass 35, count 0 2006.285.11:51:10.09#ibcon#read 4, iclass 35, count 0 2006.285.11:51:10.09#ibcon#about to read 5, iclass 35, count 0 2006.285.11:51:10.09#ibcon#read 5, iclass 35, count 0 2006.285.11:51:10.09#ibcon#about to read 6, iclass 35, count 0 2006.285.11:51:10.09#ibcon#read 6, iclass 35, count 0 2006.285.11:51:10.09#ibcon#end of sib2, iclass 35, count 0 2006.285.11:51:10.09#ibcon#*after write, iclass 35, count 0 2006.285.11:51:10.09#ibcon#*before return 0, iclass 35, count 0 2006.285.11:51:10.09#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:51:10.09#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.11:51:10.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.11:51:10.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.11:51:10.10$vck44/vblo=6,719.99 2006.285.11:51:10.10#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.11:51:10.10#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.11:51:10.10#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:10.10#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:51:10.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:51:10.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:51:10.10#ibcon#enter wrdev, iclass 37, count 0 2006.285.11:51:10.10#ibcon#first serial, iclass 37, count 0 2006.285.11:51:10.10#ibcon#enter sib2, iclass 37, count 0 2006.285.11:51:10.10#ibcon#flushed, iclass 37, count 0 2006.285.11:51:10.10#ibcon#about to write, iclass 37, count 0 2006.285.11:51:10.10#ibcon#wrote, iclass 37, count 0 2006.285.11:51:10.10#ibcon#about to read 3, iclass 37, count 0 2006.285.11:51:10.11#ibcon#read 3, iclass 37, count 0 2006.285.11:51:10.11#ibcon#about to read 4, iclass 37, count 0 2006.285.11:51:10.11#ibcon#read 4, iclass 37, count 0 2006.285.11:51:10.11#ibcon#about to read 5, iclass 37, count 0 2006.285.11:51:10.11#ibcon#read 5, iclass 37, count 0 2006.285.11:51:10.11#ibcon#about to read 6, iclass 37, count 0 2006.285.11:51:10.11#ibcon#read 6, iclass 37, count 0 2006.285.11:51:10.11#ibcon#end of sib2, iclass 37, count 0 2006.285.11:51:10.11#ibcon#*mode == 0, iclass 37, count 0 2006.285.11:51:10.11#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.11:51:10.11#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:51:10.11#ibcon#*before write, iclass 37, count 0 2006.285.11:51:10.11#ibcon#enter sib2, iclass 37, count 0 2006.285.11:51:10.11#ibcon#flushed, iclass 37, count 0 2006.285.11:51:10.11#ibcon#about to write, iclass 37, count 0 2006.285.11:51:10.11#ibcon#wrote, iclass 37, count 0 2006.285.11:51:10.11#ibcon#about to read 3, iclass 37, count 0 2006.285.11:51:10.15#ibcon#read 3, iclass 37, count 0 2006.285.11:51:10.15#ibcon#about to read 4, iclass 37, count 0 2006.285.11:51:10.15#ibcon#read 4, iclass 37, count 0 2006.285.11:51:10.15#ibcon#about to read 5, iclass 37, count 0 2006.285.11:51:10.15#ibcon#read 5, iclass 37, count 0 2006.285.11:51:10.15#ibcon#about to read 6, iclass 37, count 0 2006.285.11:51:10.15#ibcon#read 6, iclass 37, count 0 2006.285.11:51:10.15#ibcon#end of sib2, iclass 37, count 0 2006.285.11:51:10.15#ibcon#*after write, iclass 37, count 0 2006.285.11:51:10.15#ibcon#*before return 0, iclass 37, count 0 2006.285.11:51:10.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:51:10.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.11:51:10.15#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.11:51:10.15#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.11:51:10.16$vck44/vb=6,3 2006.285.11:51:10.16#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.11:51:10.16#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.11:51:10.16#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:10.16#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:51:10.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:51:10.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:51:10.20#ibcon#enter wrdev, iclass 39, count 2 2006.285.11:51:10.20#ibcon#first serial, iclass 39, count 2 2006.285.11:51:10.20#ibcon#enter sib2, iclass 39, count 2 2006.285.11:51:10.20#ibcon#flushed, iclass 39, count 2 2006.285.11:51:10.20#ibcon#about to write, iclass 39, count 2 2006.285.11:51:10.20#ibcon#wrote, iclass 39, count 2 2006.285.11:51:10.20#ibcon#about to read 3, iclass 39, count 2 2006.285.11:51:10.22#ibcon#read 3, iclass 39, count 2 2006.285.11:51:10.22#ibcon#about to read 4, iclass 39, count 2 2006.285.11:51:10.22#ibcon#read 4, iclass 39, count 2 2006.285.11:51:10.22#ibcon#about to read 5, iclass 39, count 2 2006.285.11:51:10.22#ibcon#read 5, iclass 39, count 2 2006.285.11:51:10.22#ibcon#about to read 6, iclass 39, count 2 2006.285.11:51:10.22#ibcon#read 6, iclass 39, count 2 2006.285.11:51:10.22#ibcon#end of sib2, iclass 39, count 2 2006.285.11:51:10.22#ibcon#*mode == 0, iclass 39, count 2 2006.285.11:51:10.22#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.11:51:10.22#ibcon#[27=AT06-03\r\n] 2006.285.11:51:10.22#ibcon#*before write, iclass 39, count 2 2006.285.11:51:10.22#ibcon#enter sib2, iclass 39, count 2 2006.285.11:51:10.22#ibcon#flushed, iclass 39, count 2 2006.285.11:51:10.22#ibcon#about to write, iclass 39, count 2 2006.285.11:51:10.22#ibcon#wrote, iclass 39, count 2 2006.285.11:51:10.22#ibcon#about to read 3, iclass 39, count 2 2006.285.11:51:10.25#ibcon#read 3, iclass 39, count 2 2006.285.11:51:10.25#ibcon#about to read 4, iclass 39, count 2 2006.285.11:51:10.25#ibcon#read 4, iclass 39, count 2 2006.285.11:51:10.25#ibcon#about to read 5, iclass 39, count 2 2006.285.11:51:10.25#ibcon#read 5, iclass 39, count 2 2006.285.11:51:10.25#ibcon#about to read 6, iclass 39, count 2 2006.285.11:51:10.25#ibcon#read 6, iclass 39, count 2 2006.285.11:51:10.25#ibcon#end of sib2, iclass 39, count 2 2006.285.11:51:10.25#ibcon#*after write, iclass 39, count 2 2006.285.11:51:10.25#ibcon#*before return 0, iclass 39, count 2 2006.285.11:51:10.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:51:10.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:51:10.25#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.11:51:10.25#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:10.25#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:51:10.37#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:51:10.37#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:51:10.37#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:51:10.37#ibcon#first serial, iclass 39, count 0 2006.285.11:51:10.37#ibcon#enter sib2, iclass 39, count 0 2006.285.11:51:10.37#ibcon#flushed, iclass 39, count 0 2006.285.11:51:10.37#ibcon#about to write, iclass 39, count 0 2006.285.11:51:10.37#ibcon#wrote, iclass 39, count 0 2006.285.11:51:10.37#ibcon#about to read 3, iclass 39, count 0 2006.285.11:51:10.39#ibcon#read 3, iclass 39, count 0 2006.285.11:51:10.39#ibcon#about to read 4, iclass 39, count 0 2006.285.11:51:10.39#ibcon#read 4, iclass 39, count 0 2006.285.11:51:10.39#ibcon#about to read 5, iclass 39, count 0 2006.285.11:51:10.39#ibcon#read 5, iclass 39, count 0 2006.285.11:51:10.39#ibcon#about to read 6, iclass 39, count 0 2006.285.11:51:10.39#ibcon#read 6, iclass 39, count 0 2006.285.11:51:10.39#ibcon#end of sib2, iclass 39, count 0 2006.285.11:51:10.39#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:51:10.39#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:51:10.39#ibcon#[27=USB\r\n] 2006.285.11:51:10.39#ibcon#*before write, iclass 39, count 0 2006.285.11:51:10.39#ibcon#enter sib2, iclass 39, count 0 2006.285.11:51:10.39#ibcon#flushed, iclass 39, count 0 2006.285.11:51:10.39#ibcon#about to write, iclass 39, count 0 2006.285.11:51:10.39#ibcon#wrote, iclass 39, count 0 2006.285.11:51:10.39#ibcon#about to read 3, iclass 39, count 0 2006.285.11:51:10.42#ibcon#read 3, iclass 39, count 0 2006.285.11:51:10.42#ibcon#about to read 4, iclass 39, count 0 2006.285.11:51:10.42#ibcon#read 4, iclass 39, count 0 2006.285.11:51:10.42#ibcon#about to read 5, iclass 39, count 0 2006.285.11:51:10.42#ibcon#read 5, iclass 39, count 0 2006.285.11:51:10.42#ibcon#about to read 6, iclass 39, count 0 2006.285.11:51:10.42#ibcon#read 6, iclass 39, count 0 2006.285.11:51:10.42#ibcon#end of sib2, iclass 39, count 0 2006.285.11:51:10.42#ibcon#*after write, iclass 39, count 0 2006.285.11:51:10.42#ibcon#*before return 0, iclass 39, count 0 2006.285.11:51:10.42#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:51:10.42#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:51:10.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:51:10.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:51:10.42$vck44/vblo=7,734.99 2006.285.11:51:10.43#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.11:51:10.43#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.11:51:10.43#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:10.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:51:10.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:51:10.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:51:10.43#ibcon#enter wrdev, iclass 3, count 0 2006.285.11:51:10.43#ibcon#first serial, iclass 3, count 0 2006.285.11:51:10.43#ibcon#enter sib2, iclass 3, count 0 2006.285.11:51:10.43#ibcon#flushed, iclass 3, count 0 2006.285.11:51:10.43#ibcon#about to write, iclass 3, count 0 2006.285.11:51:10.43#ibcon#wrote, iclass 3, count 0 2006.285.11:51:10.43#ibcon#about to read 3, iclass 3, count 0 2006.285.11:51:10.44#ibcon#read 3, iclass 3, count 0 2006.285.11:51:10.44#ibcon#about to read 4, iclass 3, count 0 2006.285.11:51:10.44#ibcon#read 4, iclass 3, count 0 2006.285.11:51:10.44#ibcon#about to read 5, iclass 3, count 0 2006.285.11:51:10.44#ibcon#read 5, iclass 3, count 0 2006.285.11:51:10.44#ibcon#about to read 6, iclass 3, count 0 2006.285.11:51:10.44#ibcon#read 6, iclass 3, count 0 2006.285.11:51:10.44#ibcon#end of sib2, iclass 3, count 0 2006.285.11:51:10.44#ibcon#*mode == 0, iclass 3, count 0 2006.285.11:51:10.44#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.11:51:10.44#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:51:10.44#ibcon#*before write, iclass 3, count 0 2006.285.11:51:10.44#ibcon#enter sib2, iclass 3, count 0 2006.285.11:51:10.44#ibcon#flushed, iclass 3, count 0 2006.285.11:51:10.44#ibcon#about to write, iclass 3, count 0 2006.285.11:51:10.44#ibcon#wrote, iclass 3, count 0 2006.285.11:51:10.44#ibcon#about to read 3, iclass 3, count 0 2006.285.11:51:10.48#ibcon#read 3, iclass 3, count 0 2006.285.11:51:10.48#ibcon#about to read 4, iclass 3, count 0 2006.285.11:51:10.48#ibcon#read 4, iclass 3, count 0 2006.285.11:51:10.48#ibcon#about to read 5, iclass 3, count 0 2006.285.11:51:10.48#ibcon#read 5, iclass 3, count 0 2006.285.11:51:10.48#ibcon#about to read 6, iclass 3, count 0 2006.285.11:51:10.48#ibcon#read 6, iclass 3, count 0 2006.285.11:51:10.48#ibcon#end of sib2, iclass 3, count 0 2006.285.11:51:10.48#ibcon#*after write, iclass 3, count 0 2006.285.11:51:10.48#ibcon#*before return 0, iclass 3, count 0 2006.285.11:51:10.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:51:10.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.11:51:10.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.11:51:10.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.11:51:10.49$vck44/vb=7,4 2006.285.11:51:10.49#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.11:51:10.49#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.11:51:10.49#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:10.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:51:10.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:51:10.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:51:10.53#ibcon#enter wrdev, iclass 5, count 2 2006.285.11:51:10.53#ibcon#first serial, iclass 5, count 2 2006.285.11:51:10.53#ibcon#enter sib2, iclass 5, count 2 2006.285.11:51:10.53#ibcon#flushed, iclass 5, count 2 2006.285.11:51:10.53#ibcon#about to write, iclass 5, count 2 2006.285.11:51:10.53#ibcon#wrote, iclass 5, count 2 2006.285.11:51:10.53#ibcon#about to read 3, iclass 5, count 2 2006.285.11:51:10.55#ibcon#read 3, iclass 5, count 2 2006.285.11:51:10.55#ibcon#about to read 4, iclass 5, count 2 2006.285.11:51:10.55#ibcon#read 4, iclass 5, count 2 2006.285.11:51:10.55#ibcon#about to read 5, iclass 5, count 2 2006.285.11:51:10.55#ibcon#read 5, iclass 5, count 2 2006.285.11:51:10.55#ibcon#about to read 6, iclass 5, count 2 2006.285.11:51:10.55#ibcon#read 6, iclass 5, count 2 2006.285.11:51:10.55#ibcon#end of sib2, iclass 5, count 2 2006.285.11:51:10.55#ibcon#*mode == 0, iclass 5, count 2 2006.285.11:51:10.55#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.11:51:10.55#ibcon#[27=AT07-04\r\n] 2006.285.11:51:10.55#ibcon#*before write, iclass 5, count 2 2006.285.11:51:10.55#ibcon#enter sib2, iclass 5, count 2 2006.285.11:51:10.55#ibcon#flushed, iclass 5, count 2 2006.285.11:51:10.55#ibcon#about to write, iclass 5, count 2 2006.285.11:51:10.55#ibcon#wrote, iclass 5, count 2 2006.285.11:51:10.55#ibcon#about to read 3, iclass 5, count 2 2006.285.11:51:10.58#ibcon#read 3, iclass 5, count 2 2006.285.11:51:10.58#ibcon#about to read 4, iclass 5, count 2 2006.285.11:51:10.58#ibcon#read 4, iclass 5, count 2 2006.285.11:51:10.58#ibcon#about to read 5, iclass 5, count 2 2006.285.11:51:10.58#ibcon#read 5, iclass 5, count 2 2006.285.11:51:10.58#ibcon#about to read 6, iclass 5, count 2 2006.285.11:51:10.58#ibcon#read 6, iclass 5, count 2 2006.285.11:51:10.58#ibcon#end of sib2, iclass 5, count 2 2006.285.11:51:10.58#ibcon#*after write, iclass 5, count 2 2006.285.11:51:10.58#ibcon#*before return 0, iclass 5, count 2 2006.285.11:51:10.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:51:10.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.11:51:10.58#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.11:51:10.58#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:10.58#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:51:10.70#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:51:10.70#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:51:10.70#ibcon#enter wrdev, iclass 5, count 0 2006.285.11:51:10.70#ibcon#first serial, iclass 5, count 0 2006.285.11:51:10.70#ibcon#enter sib2, iclass 5, count 0 2006.285.11:51:10.70#ibcon#flushed, iclass 5, count 0 2006.285.11:51:10.70#ibcon#about to write, iclass 5, count 0 2006.285.11:51:10.70#ibcon#wrote, iclass 5, count 0 2006.285.11:51:10.70#ibcon#about to read 3, iclass 5, count 0 2006.285.11:51:10.72#ibcon#read 3, iclass 5, count 0 2006.285.11:51:10.72#ibcon#about to read 4, iclass 5, count 0 2006.285.11:51:10.72#ibcon#read 4, iclass 5, count 0 2006.285.11:51:10.72#ibcon#about to read 5, iclass 5, count 0 2006.285.11:51:10.72#ibcon#read 5, iclass 5, count 0 2006.285.11:51:10.72#ibcon#about to read 6, iclass 5, count 0 2006.285.11:51:10.72#ibcon#read 6, iclass 5, count 0 2006.285.11:51:10.72#ibcon#end of sib2, iclass 5, count 0 2006.285.11:51:10.72#ibcon#*mode == 0, iclass 5, count 0 2006.285.11:51:10.72#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.11:51:10.72#ibcon#[27=USB\r\n] 2006.285.11:51:10.72#ibcon#*before write, iclass 5, count 0 2006.285.11:51:10.72#ibcon#enter sib2, iclass 5, count 0 2006.285.11:51:10.72#ibcon#flushed, iclass 5, count 0 2006.285.11:51:10.72#ibcon#about to write, iclass 5, count 0 2006.285.11:51:10.72#ibcon#wrote, iclass 5, count 0 2006.285.11:51:10.72#ibcon#about to read 3, iclass 5, count 0 2006.285.11:51:10.75#ibcon#read 3, iclass 5, count 0 2006.285.11:51:10.75#ibcon#about to read 4, iclass 5, count 0 2006.285.11:51:10.75#ibcon#read 4, iclass 5, count 0 2006.285.11:51:10.75#ibcon#about to read 5, iclass 5, count 0 2006.285.11:51:10.75#ibcon#read 5, iclass 5, count 0 2006.285.11:51:10.75#ibcon#about to read 6, iclass 5, count 0 2006.285.11:51:10.75#ibcon#read 6, iclass 5, count 0 2006.285.11:51:10.75#ibcon#end of sib2, iclass 5, count 0 2006.285.11:51:10.75#ibcon#*after write, iclass 5, count 0 2006.285.11:51:10.75#ibcon#*before return 0, iclass 5, count 0 2006.285.11:51:10.75#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:51:10.75#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.11:51:10.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.11:51:10.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.11:51:10.75$vck44/vblo=8,744.99 2006.285.11:51:10.76#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.11:51:10.76#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.11:51:10.76#ibcon#ireg 17 cls_cnt 0 2006.285.11:51:10.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:51:10.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:51:10.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:51:10.76#ibcon#enter wrdev, iclass 7, count 0 2006.285.11:51:10.76#ibcon#first serial, iclass 7, count 0 2006.285.11:51:10.76#ibcon#enter sib2, iclass 7, count 0 2006.285.11:51:10.76#ibcon#flushed, iclass 7, count 0 2006.285.11:51:10.76#ibcon#about to write, iclass 7, count 0 2006.285.11:51:10.76#ibcon#wrote, iclass 7, count 0 2006.285.11:51:10.76#ibcon#about to read 3, iclass 7, count 0 2006.285.11:51:10.77#ibcon#read 3, iclass 7, count 0 2006.285.11:51:10.77#ibcon#about to read 4, iclass 7, count 0 2006.285.11:51:10.77#ibcon#read 4, iclass 7, count 0 2006.285.11:51:10.77#ibcon#about to read 5, iclass 7, count 0 2006.285.11:51:10.77#ibcon#read 5, iclass 7, count 0 2006.285.11:51:10.77#ibcon#about to read 6, iclass 7, count 0 2006.285.11:51:10.77#ibcon#read 6, iclass 7, count 0 2006.285.11:51:10.77#ibcon#end of sib2, iclass 7, count 0 2006.285.11:51:10.77#ibcon#*mode == 0, iclass 7, count 0 2006.285.11:51:10.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.11:51:10.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:51:10.77#ibcon#*before write, iclass 7, count 0 2006.285.11:51:10.77#ibcon#enter sib2, iclass 7, count 0 2006.285.11:51:10.77#ibcon#flushed, iclass 7, count 0 2006.285.11:51:10.77#ibcon#about to write, iclass 7, count 0 2006.285.11:51:10.77#ibcon#wrote, iclass 7, count 0 2006.285.11:51:10.77#ibcon#about to read 3, iclass 7, count 0 2006.285.11:51:10.81#ibcon#read 3, iclass 7, count 0 2006.285.11:51:10.81#ibcon#about to read 4, iclass 7, count 0 2006.285.11:51:10.81#ibcon#read 4, iclass 7, count 0 2006.285.11:51:10.81#ibcon#about to read 5, iclass 7, count 0 2006.285.11:51:10.81#ibcon#read 5, iclass 7, count 0 2006.285.11:51:10.81#ibcon#about to read 6, iclass 7, count 0 2006.285.11:51:10.81#ibcon#read 6, iclass 7, count 0 2006.285.11:51:10.81#ibcon#end of sib2, iclass 7, count 0 2006.285.11:51:10.81#ibcon#*after write, iclass 7, count 0 2006.285.11:51:10.81#ibcon#*before return 0, iclass 7, count 0 2006.285.11:51:10.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:51:10.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.11:51:10.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.11:51:10.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.11:51:10.81$vck44/vb=8,4 2006.285.11:51:10.82#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.11:51:10.82#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.11:51:10.82#ibcon#ireg 11 cls_cnt 2 2006.285.11:51:10.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:51:10.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:51:10.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:51:10.86#ibcon#enter wrdev, iclass 11, count 2 2006.285.11:51:10.86#ibcon#first serial, iclass 11, count 2 2006.285.11:51:10.86#ibcon#enter sib2, iclass 11, count 2 2006.285.11:51:10.86#ibcon#flushed, iclass 11, count 2 2006.285.11:51:10.86#ibcon#about to write, iclass 11, count 2 2006.285.11:51:10.86#ibcon#wrote, iclass 11, count 2 2006.285.11:51:10.86#ibcon#about to read 3, iclass 11, count 2 2006.285.11:51:10.88#ibcon#read 3, iclass 11, count 2 2006.285.11:51:10.88#ibcon#about to read 4, iclass 11, count 2 2006.285.11:51:10.88#ibcon#read 4, iclass 11, count 2 2006.285.11:51:10.88#ibcon#about to read 5, iclass 11, count 2 2006.285.11:51:10.88#ibcon#read 5, iclass 11, count 2 2006.285.11:51:10.88#ibcon#about to read 6, iclass 11, count 2 2006.285.11:51:10.88#ibcon#read 6, iclass 11, count 2 2006.285.11:51:10.88#ibcon#end of sib2, iclass 11, count 2 2006.285.11:51:10.88#ibcon#*mode == 0, iclass 11, count 2 2006.285.11:51:10.88#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.11:51:10.88#ibcon#[27=AT08-04\r\n] 2006.285.11:51:10.88#ibcon#*before write, iclass 11, count 2 2006.285.11:51:10.88#ibcon#enter sib2, iclass 11, count 2 2006.285.11:51:10.88#ibcon#flushed, iclass 11, count 2 2006.285.11:51:10.88#ibcon#about to write, iclass 11, count 2 2006.285.11:51:10.88#ibcon#wrote, iclass 11, count 2 2006.285.11:51:10.88#ibcon#about to read 3, iclass 11, count 2 2006.285.11:51:10.91#ibcon#read 3, iclass 11, count 2 2006.285.11:51:10.91#ibcon#about to read 4, iclass 11, count 2 2006.285.11:51:10.91#ibcon#read 4, iclass 11, count 2 2006.285.11:51:10.91#ibcon#about to read 5, iclass 11, count 2 2006.285.11:51:10.91#ibcon#read 5, iclass 11, count 2 2006.285.11:51:10.91#ibcon#about to read 6, iclass 11, count 2 2006.285.11:51:10.91#ibcon#read 6, iclass 11, count 2 2006.285.11:51:10.91#ibcon#end of sib2, iclass 11, count 2 2006.285.11:51:10.91#ibcon#*after write, iclass 11, count 2 2006.285.11:51:10.91#ibcon#*before return 0, iclass 11, count 2 2006.285.11:51:10.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:51:10.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.11:51:10.91#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.11:51:10.91#ibcon#ireg 7 cls_cnt 0 2006.285.11:51:10.91#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:51:11.03#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:51:11.03#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:51:11.03#ibcon#enter wrdev, iclass 11, count 0 2006.285.11:51:11.03#ibcon#first serial, iclass 11, count 0 2006.285.11:51:11.03#ibcon#enter sib2, iclass 11, count 0 2006.285.11:51:11.03#ibcon#flushed, iclass 11, count 0 2006.285.11:51:11.03#ibcon#about to write, iclass 11, count 0 2006.285.11:51:11.03#ibcon#wrote, iclass 11, count 0 2006.285.11:51:11.03#ibcon#about to read 3, iclass 11, count 0 2006.285.11:51:11.05#ibcon#read 3, iclass 11, count 0 2006.285.11:51:11.05#ibcon#about to read 4, iclass 11, count 0 2006.285.11:51:11.05#ibcon#read 4, iclass 11, count 0 2006.285.11:51:11.05#ibcon#about to read 5, iclass 11, count 0 2006.285.11:51:11.05#ibcon#read 5, iclass 11, count 0 2006.285.11:51:11.05#ibcon#about to read 6, iclass 11, count 0 2006.285.11:51:11.05#ibcon#read 6, iclass 11, count 0 2006.285.11:51:11.05#ibcon#end of sib2, iclass 11, count 0 2006.285.11:51:11.05#ibcon#*mode == 0, iclass 11, count 0 2006.285.11:51:11.05#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.11:51:11.05#ibcon#[27=USB\r\n] 2006.285.11:51:11.05#ibcon#*before write, iclass 11, count 0 2006.285.11:51:11.05#ibcon#enter sib2, iclass 11, count 0 2006.285.11:51:11.05#ibcon#flushed, iclass 11, count 0 2006.285.11:51:11.05#ibcon#about to write, iclass 11, count 0 2006.285.11:51:11.05#ibcon#wrote, iclass 11, count 0 2006.285.11:51:11.05#ibcon#about to read 3, iclass 11, count 0 2006.285.11:51:11.08#ibcon#read 3, iclass 11, count 0 2006.285.11:51:11.08#ibcon#about to read 4, iclass 11, count 0 2006.285.11:51:11.08#ibcon#read 4, iclass 11, count 0 2006.285.11:51:11.08#ibcon#about to read 5, iclass 11, count 0 2006.285.11:51:11.08#ibcon#read 5, iclass 11, count 0 2006.285.11:51:11.08#ibcon#about to read 6, iclass 11, count 0 2006.285.11:51:11.08#ibcon#read 6, iclass 11, count 0 2006.285.11:51:11.08#ibcon#end of sib2, iclass 11, count 0 2006.285.11:51:11.08#ibcon#*after write, iclass 11, count 0 2006.285.11:51:11.08#ibcon#*before return 0, iclass 11, count 0 2006.285.11:51:11.08#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:51:11.08#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.11:51:11.08#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.11:51:11.08#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.11:51:11.09$vck44/vabw=wide 2006.285.11:51:11.09#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.11:51:11.09#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.11:51:11.09#ibcon#ireg 8 cls_cnt 0 2006.285.11:51:11.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:51:11.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:51:11.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:51:11.09#ibcon#enter wrdev, iclass 13, count 0 2006.285.11:51:11.09#ibcon#first serial, iclass 13, count 0 2006.285.11:51:11.09#ibcon#enter sib2, iclass 13, count 0 2006.285.11:51:11.09#ibcon#flushed, iclass 13, count 0 2006.285.11:51:11.09#ibcon#about to write, iclass 13, count 0 2006.285.11:51:11.09#ibcon#wrote, iclass 13, count 0 2006.285.11:51:11.09#ibcon#about to read 3, iclass 13, count 0 2006.285.11:51:11.10#ibcon#read 3, iclass 13, count 0 2006.285.11:51:11.10#ibcon#about to read 4, iclass 13, count 0 2006.285.11:51:11.10#ibcon#read 4, iclass 13, count 0 2006.285.11:51:11.10#ibcon#about to read 5, iclass 13, count 0 2006.285.11:51:11.10#ibcon#read 5, iclass 13, count 0 2006.285.11:51:11.10#ibcon#about to read 6, iclass 13, count 0 2006.285.11:51:11.10#ibcon#read 6, iclass 13, count 0 2006.285.11:51:11.10#ibcon#end of sib2, iclass 13, count 0 2006.285.11:51:11.10#ibcon#*mode == 0, iclass 13, count 0 2006.285.11:51:11.10#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.11:51:11.10#ibcon#[25=BW32\r\n] 2006.285.11:51:11.10#ibcon#*before write, iclass 13, count 0 2006.285.11:51:11.10#ibcon#enter sib2, iclass 13, count 0 2006.285.11:51:11.10#ibcon#flushed, iclass 13, count 0 2006.285.11:51:11.10#ibcon#about to write, iclass 13, count 0 2006.285.11:51:11.10#ibcon#wrote, iclass 13, count 0 2006.285.11:51:11.10#ibcon#about to read 3, iclass 13, count 0 2006.285.11:51:11.13#ibcon#read 3, iclass 13, count 0 2006.285.11:51:11.13#ibcon#about to read 4, iclass 13, count 0 2006.285.11:51:11.13#ibcon#read 4, iclass 13, count 0 2006.285.11:51:11.13#ibcon#about to read 5, iclass 13, count 0 2006.285.11:51:11.13#ibcon#read 5, iclass 13, count 0 2006.285.11:51:11.13#ibcon#about to read 6, iclass 13, count 0 2006.285.11:51:11.13#ibcon#read 6, iclass 13, count 0 2006.285.11:51:11.13#ibcon#end of sib2, iclass 13, count 0 2006.285.11:51:11.13#ibcon#*after write, iclass 13, count 0 2006.285.11:51:11.13#ibcon#*before return 0, iclass 13, count 0 2006.285.11:51:11.13#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:51:11.13#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.11:51:11.13#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.11:51:11.13#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.11:51:11.14$vck44/vbbw=wide 2006.285.11:51:11.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.11:51:11.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.11:51:11.14#ibcon#ireg 8 cls_cnt 0 2006.285.11:51:11.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:51:11.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:51:11.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:51:11.19#ibcon#enter wrdev, iclass 15, count 0 2006.285.11:51:11.19#ibcon#first serial, iclass 15, count 0 2006.285.11:51:11.19#ibcon#enter sib2, iclass 15, count 0 2006.285.11:51:11.19#ibcon#flushed, iclass 15, count 0 2006.285.11:51:11.19#ibcon#about to write, iclass 15, count 0 2006.285.11:51:11.19#ibcon#wrote, iclass 15, count 0 2006.285.11:51:11.19#ibcon#about to read 3, iclass 15, count 0 2006.285.11:51:11.21#ibcon#read 3, iclass 15, count 0 2006.285.11:51:11.21#ibcon#about to read 4, iclass 15, count 0 2006.285.11:51:11.21#ibcon#read 4, iclass 15, count 0 2006.285.11:51:11.21#ibcon#about to read 5, iclass 15, count 0 2006.285.11:51:11.21#ibcon#read 5, iclass 15, count 0 2006.285.11:51:11.21#ibcon#about to read 6, iclass 15, count 0 2006.285.11:51:11.21#ibcon#read 6, iclass 15, count 0 2006.285.11:51:11.21#ibcon#end of sib2, iclass 15, count 0 2006.285.11:51:11.21#ibcon#*mode == 0, iclass 15, count 0 2006.285.11:51:11.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.11:51:11.21#ibcon#[27=BW32\r\n] 2006.285.11:51:11.21#ibcon#*before write, iclass 15, count 0 2006.285.11:51:11.21#ibcon#enter sib2, iclass 15, count 0 2006.285.11:51:11.21#ibcon#flushed, iclass 15, count 0 2006.285.11:51:11.21#ibcon#about to write, iclass 15, count 0 2006.285.11:51:11.21#ibcon#wrote, iclass 15, count 0 2006.285.11:51:11.21#ibcon#about to read 3, iclass 15, count 0 2006.285.11:51:11.24#ibcon#read 3, iclass 15, count 0 2006.285.11:51:11.24#ibcon#about to read 4, iclass 15, count 0 2006.285.11:51:11.24#ibcon#read 4, iclass 15, count 0 2006.285.11:51:11.24#ibcon#about to read 5, iclass 15, count 0 2006.285.11:51:11.24#ibcon#read 5, iclass 15, count 0 2006.285.11:51:11.24#ibcon#about to read 6, iclass 15, count 0 2006.285.11:51:11.24#ibcon#read 6, iclass 15, count 0 2006.285.11:51:11.24#ibcon#end of sib2, iclass 15, count 0 2006.285.11:51:11.24#ibcon#*after write, iclass 15, count 0 2006.285.11:51:11.24#ibcon#*before return 0, iclass 15, count 0 2006.285.11:51:11.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:51:11.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.11:51:11.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.11:51:11.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.11:51:11.25$setupk4/ifdk4 2006.285.11:51:11.25$ifdk4/lo= 2006.285.11:51:11.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:51:11.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:51:11.25$ifdk4/patch= 2006.285.11:51:11.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:51:11.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:51:11.25$setupk4/!*+20s 2006.285.11:51:11.49#abcon#<5=/05 1.0 1.4 19.03 951015.4\r\n> 2006.285.11:51:11.51#abcon#{5=INTERFACE CLEAR} 2006.285.11:51:11.57#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:51:19.14#trakl#Source acquired 2006.285.11:51:21.14#flagr#flagr/antenna,acquired 2006.285.11:51:21.66#abcon#<5=/05 1.0 1.4 19.03 951015.4\r\n> 2006.285.11:51:21.68#abcon#{5=INTERFACE CLEAR} 2006.285.11:51:21.74#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:51:25.91$setupk4/"tpicd 2006.285.11:51:25.91$setupk4/echo=off 2006.285.11:51:25.91$setupk4/xlog=off 2006.285.11:51:25.91:!2006.285.11:55:01 2006.285.11:55:01.00:preob 2006.285.11:55:01.13/onsource/TRACKING 2006.285.11:55:01.13:!2006.285.11:55:11 2006.285.11:55:11.00:"tape 2006.285.11:55:11.00:"st=record 2006.285.11:55:11.00:data_valid=on 2006.285.11:55:11.00:midob 2006.285.11:55:12.13/onsource/TRACKING 2006.285.11:55:12.13/wx/19.03,1015.4,95 2006.285.11:55:12.27/cable/+6.4935E-03 2006.285.11:55:13.36/va/01,07,usb,yes,32,35 2006.285.11:55:13.36/va/02,06,usb,yes,32,33 2006.285.11:55:13.36/va/03,07,usb,yes,32,33 2006.285.11:55:13.36/va/04,06,usb,yes,33,34 2006.285.11:55:13.36/va/05,03,usb,yes,33,33 2006.285.11:55:13.36/va/06,04,usb,yes,29,29 2006.285.11:55:13.36/va/07,04,usb,yes,30,30 2006.285.11:55:13.36/va/08,03,usb,yes,31,37 2006.285.11:55:13.59/valo/01,524.99,yes,locked 2006.285.11:55:13.59/valo/02,534.99,yes,locked 2006.285.11:55:13.59/valo/03,564.99,yes,locked 2006.285.11:55:13.59/valo/04,624.99,yes,locked 2006.285.11:55:13.59/valo/05,734.99,yes,locked 2006.285.11:55:13.59/valo/06,814.99,yes,locked 2006.285.11:55:13.59/valo/07,864.99,yes,locked 2006.285.11:55:13.59/valo/08,884.99,yes,locked 2006.285.11:55:14.68/vb/01,04,usb,yes,32,28 2006.285.11:55:14.68/vb/02,05,usb,yes,29,30 2006.285.11:55:14.68/vb/03,04,usb,yes,30,33 2006.285.11:55:14.68/vb/04,05,usb,yes,30,29 2006.285.11:55:14.68/vb/05,04,usb,yes,26,29 2006.285.11:55:14.68/vb/06,03,usb,yes,38,33 2006.285.11:55:14.68/vb/07,04,usb,yes,30,30 2006.285.11:55:14.68/vb/08,04,usb,yes,28,31 2006.285.11:55:14.91/vblo/01,629.99,yes,locked 2006.285.11:55:14.91/vblo/02,634.99,yes,locked 2006.285.11:55:14.91/vblo/03,649.99,yes,locked 2006.285.11:55:14.91/vblo/04,679.99,yes,locked 2006.285.11:55:14.91/vblo/05,709.99,yes,locked 2006.285.11:55:14.91/vblo/06,719.99,yes,locked 2006.285.11:55:14.91/vblo/07,734.99,yes,locked 2006.285.11:55:14.91/vblo/08,744.99,yes,locked 2006.285.11:55:15.06/vabw/8 2006.285.11:55:15.21/vbbw/8 2006.285.11:55:15.30/xfe/off,on,12.2 2006.285.11:55:15.67/ifatt/23,28,28,28 2006.285.11:55:16.07/fmout-gps/S +2.70E-07 2006.285.11:55:16.09:!2006.285.11:56:51 2006.285.11:56:51.00:data_valid=off 2006.285.11:56:51.00:"et 2006.285.11:56:51.00:!+3s 2006.285.11:56:54.01:"tape 2006.285.11:56:54.01:postob 2006.285.11:56:54.07/cable/+6.4940E-03 2006.285.11:56:54.07/wx/19.03,1015.4,95 2006.285.11:56:55.07/fmout-gps/S +2.69E-07 2006.285.11:56:55.07:scan_name=285-1201,jd0610,80 2006.285.11:56:55.07:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.285.11:56:56.14#flagr#flagr/antenna,new-source 2006.285.11:56:56.14:checkk5 2006.285.11:56:56.49/chk_autoobs//k5ts1/ autoobs is running! 2006.285.11:56:56.83/chk_autoobs//k5ts2/ autoobs is running! 2006.285.11:56:57.17/chk_autoobs//k5ts3/ autoobs is running! 2006.285.11:56:57.55/chk_autoobs//k5ts4/ autoobs is running! 2006.285.11:56:57.93/chk_obsdata//k5ts1/T2851155??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.11:56:58.33/chk_obsdata//k5ts2/T2851155??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.11:56:58.74/chk_obsdata//k5ts3/T2851155??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.11:56:59.08/chk_obsdata//k5ts4/T2851155??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.11:56:59.83/k5log//k5ts1_log_newline 2006.285.11:57:00.78/k5log//k5ts2_log_newline 2006.285.11:57:01.57/k5log//k5ts3_log_newline 2006.285.11:57:02.82/k5log//k5ts4_log_newline 2006.285.11:57:02.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.11:57:02.85:setupk4=1 2006.285.11:57:02.85$setupk4/echo=on 2006.285.11:57:02.85$setupk4/pcalon 2006.285.11:57:02.85$pcalon/"no phase cal control is implemented here 2006.285.11:57:02.85$setupk4/"tpicd=stop 2006.285.11:57:02.85$setupk4/"rec=synch_on 2006.285.11:57:02.85$setupk4/"rec_mode=128 2006.285.11:57:02.85$setupk4/!* 2006.285.11:57:02.85$setupk4/recpk4 2006.285.11:57:02.85$recpk4/recpatch= 2006.285.11:57:02.85$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.11:57:02.85$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.11:57:02.85$setupk4/vck44 2006.285.11:57:02.85$vck44/valo=1,524.99 2006.285.11:57:02.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.11:57:02.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.11:57:02.85#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:02.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:57:02.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:57:02.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:57:02.85#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:57:02.85#ibcon#first serial, iclass 16, count 0 2006.285.11:57:02.85#ibcon#enter sib2, iclass 16, count 0 2006.285.11:57:02.85#ibcon#flushed, iclass 16, count 0 2006.285.11:57:02.85#ibcon#about to write, iclass 16, count 0 2006.285.11:57:02.85#ibcon#wrote, iclass 16, count 0 2006.285.11:57:02.85#ibcon#about to read 3, iclass 16, count 0 2006.285.11:57:02.87#ibcon#read 3, iclass 16, count 0 2006.285.11:57:02.87#ibcon#about to read 4, iclass 16, count 0 2006.285.11:57:02.87#ibcon#read 4, iclass 16, count 0 2006.285.11:57:02.87#ibcon#about to read 5, iclass 16, count 0 2006.285.11:57:02.87#ibcon#read 5, iclass 16, count 0 2006.285.11:57:02.87#ibcon#about to read 6, iclass 16, count 0 2006.285.11:57:02.87#ibcon#read 6, iclass 16, count 0 2006.285.11:57:02.87#ibcon#end of sib2, iclass 16, count 0 2006.285.11:57:02.87#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:57:02.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:57:02.87#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.11:57:02.87#ibcon#*before write, iclass 16, count 0 2006.285.11:57:02.87#ibcon#enter sib2, iclass 16, count 0 2006.285.11:57:02.87#ibcon#flushed, iclass 16, count 0 2006.285.11:57:02.87#ibcon#about to write, iclass 16, count 0 2006.285.11:57:02.87#ibcon#wrote, iclass 16, count 0 2006.285.11:57:02.87#ibcon#about to read 3, iclass 16, count 0 2006.285.11:57:02.92#ibcon#read 3, iclass 16, count 0 2006.285.11:57:02.92#ibcon#about to read 4, iclass 16, count 0 2006.285.11:57:02.92#ibcon#read 4, iclass 16, count 0 2006.285.11:57:02.92#ibcon#about to read 5, iclass 16, count 0 2006.285.11:57:02.92#ibcon#read 5, iclass 16, count 0 2006.285.11:57:02.92#ibcon#about to read 6, iclass 16, count 0 2006.285.11:57:02.92#ibcon#read 6, iclass 16, count 0 2006.285.11:57:02.92#ibcon#end of sib2, iclass 16, count 0 2006.285.11:57:02.92#ibcon#*after write, iclass 16, count 0 2006.285.11:57:02.92#ibcon#*before return 0, iclass 16, count 0 2006.285.11:57:02.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:57:02.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:57:02.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:57:02.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:57:02.92$vck44/va=1,7 2006.285.11:57:02.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.11:57:02.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.11:57:02.92#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:02.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:57:02.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:57:02.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:57:02.92#ibcon#enter wrdev, iclass 18, count 2 2006.285.11:57:02.92#ibcon#first serial, iclass 18, count 2 2006.285.11:57:02.92#ibcon#enter sib2, iclass 18, count 2 2006.285.11:57:02.92#ibcon#flushed, iclass 18, count 2 2006.285.11:57:02.92#ibcon#about to write, iclass 18, count 2 2006.285.11:57:02.92#ibcon#wrote, iclass 18, count 2 2006.285.11:57:02.92#ibcon#about to read 3, iclass 18, count 2 2006.285.11:57:02.94#ibcon#read 3, iclass 18, count 2 2006.285.11:57:02.94#ibcon#about to read 4, iclass 18, count 2 2006.285.11:57:02.94#ibcon#read 4, iclass 18, count 2 2006.285.11:57:02.94#ibcon#about to read 5, iclass 18, count 2 2006.285.11:57:02.94#ibcon#read 5, iclass 18, count 2 2006.285.11:57:02.94#ibcon#about to read 6, iclass 18, count 2 2006.285.11:57:02.94#ibcon#read 6, iclass 18, count 2 2006.285.11:57:02.94#ibcon#end of sib2, iclass 18, count 2 2006.285.11:57:02.94#ibcon#*mode == 0, iclass 18, count 2 2006.285.11:57:02.94#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.11:57:02.94#ibcon#[25=AT01-07\r\n] 2006.285.11:57:02.94#ibcon#*before write, iclass 18, count 2 2006.285.11:57:02.94#ibcon#enter sib2, iclass 18, count 2 2006.285.11:57:02.94#ibcon#flushed, iclass 18, count 2 2006.285.11:57:02.94#ibcon#about to write, iclass 18, count 2 2006.285.11:57:02.94#ibcon#wrote, iclass 18, count 2 2006.285.11:57:02.94#ibcon#about to read 3, iclass 18, count 2 2006.285.11:57:02.97#ibcon#read 3, iclass 18, count 2 2006.285.11:57:02.97#ibcon#about to read 4, iclass 18, count 2 2006.285.11:57:02.97#ibcon#read 4, iclass 18, count 2 2006.285.11:57:02.97#ibcon#about to read 5, iclass 18, count 2 2006.285.11:57:02.97#ibcon#read 5, iclass 18, count 2 2006.285.11:57:02.97#ibcon#about to read 6, iclass 18, count 2 2006.285.11:57:02.97#ibcon#read 6, iclass 18, count 2 2006.285.11:57:02.97#ibcon#end of sib2, iclass 18, count 2 2006.285.11:57:02.97#ibcon#*after write, iclass 18, count 2 2006.285.11:57:02.97#ibcon#*before return 0, iclass 18, count 2 2006.285.11:57:02.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:57:02.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:57:02.97#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.11:57:02.97#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:02.97#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:57:03.09#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:57:03.09#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:57:03.09#ibcon#enter wrdev, iclass 18, count 0 2006.285.11:57:03.09#ibcon#first serial, iclass 18, count 0 2006.285.11:57:03.09#ibcon#enter sib2, iclass 18, count 0 2006.285.11:57:03.09#ibcon#flushed, iclass 18, count 0 2006.285.11:57:03.09#ibcon#about to write, iclass 18, count 0 2006.285.11:57:03.09#ibcon#wrote, iclass 18, count 0 2006.285.11:57:03.09#ibcon#about to read 3, iclass 18, count 0 2006.285.11:57:03.11#ibcon#read 3, iclass 18, count 0 2006.285.11:57:03.11#ibcon#about to read 4, iclass 18, count 0 2006.285.11:57:03.11#ibcon#read 4, iclass 18, count 0 2006.285.11:57:03.11#ibcon#about to read 5, iclass 18, count 0 2006.285.11:57:03.11#ibcon#read 5, iclass 18, count 0 2006.285.11:57:03.11#ibcon#about to read 6, iclass 18, count 0 2006.285.11:57:03.11#ibcon#read 6, iclass 18, count 0 2006.285.11:57:03.11#ibcon#end of sib2, iclass 18, count 0 2006.285.11:57:03.11#ibcon#*mode == 0, iclass 18, count 0 2006.285.11:57:03.11#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.11:57:03.11#ibcon#[25=USB\r\n] 2006.285.11:57:03.11#ibcon#*before write, iclass 18, count 0 2006.285.11:57:03.11#ibcon#enter sib2, iclass 18, count 0 2006.285.11:57:03.11#ibcon#flushed, iclass 18, count 0 2006.285.11:57:03.11#ibcon#about to write, iclass 18, count 0 2006.285.11:57:03.11#ibcon#wrote, iclass 18, count 0 2006.285.11:57:03.11#ibcon#about to read 3, iclass 18, count 0 2006.285.11:57:03.14#ibcon#read 3, iclass 18, count 0 2006.285.11:57:03.14#ibcon#about to read 4, iclass 18, count 0 2006.285.11:57:03.14#ibcon#read 4, iclass 18, count 0 2006.285.11:57:03.14#ibcon#about to read 5, iclass 18, count 0 2006.285.11:57:03.14#ibcon#read 5, iclass 18, count 0 2006.285.11:57:03.14#ibcon#about to read 6, iclass 18, count 0 2006.285.11:57:03.14#ibcon#read 6, iclass 18, count 0 2006.285.11:57:03.14#ibcon#end of sib2, iclass 18, count 0 2006.285.11:57:03.14#ibcon#*after write, iclass 18, count 0 2006.285.11:57:03.14#ibcon#*before return 0, iclass 18, count 0 2006.285.11:57:03.14#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:57:03.14#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:57:03.14#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.11:57:03.14#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.11:57:03.14$vck44/valo=2,534.99 2006.285.11:57:03.15#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.11:57:03.15#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.11:57:03.15#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:03.15#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:57:03.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:57:03.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:57:03.15#ibcon#enter wrdev, iclass 20, count 0 2006.285.11:57:03.15#ibcon#first serial, iclass 20, count 0 2006.285.11:57:03.15#ibcon#enter sib2, iclass 20, count 0 2006.285.11:57:03.15#ibcon#flushed, iclass 20, count 0 2006.285.11:57:03.15#ibcon#about to write, iclass 20, count 0 2006.285.11:57:03.15#ibcon#wrote, iclass 20, count 0 2006.285.11:57:03.15#ibcon#about to read 3, iclass 20, count 0 2006.285.11:57:03.16#ibcon#read 3, iclass 20, count 0 2006.285.11:57:03.16#ibcon#about to read 4, iclass 20, count 0 2006.285.11:57:03.16#ibcon#read 4, iclass 20, count 0 2006.285.11:57:03.16#ibcon#about to read 5, iclass 20, count 0 2006.285.11:57:03.16#ibcon#read 5, iclass 20, count 0 2006.285.11:57:03.16#ibcon#about to read 6, iclass 20, count 0 2006.285.11:57:03.16#ibcon#read 6, iclass 20, count 0 2006.285.11:57:03.16#ibcon#end of sib2, iclass 20, count 0 2006.285.11:57:03.16#ibcon#*mode == 0, iclass 20, count 0 2006.285.11:57:03.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.11:57:03.16#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.11:57:03.16#ibcon#*before write, iclass 20, count 0 2006.285.11:57:03.16#ibcon#enter sib2, iclass 20, count 0 2006.285.11:57:03.16#ibcon#flushed, iclass 20, count 0 2006.285.11:57:03.16#ibcon#about to write, iclass 20, count 0 2006.285.11:57:03.16#ibcon#wrote, iclass 20, count 0 2006.285.11:57:03.16#ibcon#about to read 3, iclass 20, count 0 2006.285.11:57:03.20#ibcon#read 3, iclass 20, count 0 2006.285.11:57:03.20#ibcon#about to read 4, iclass 20, count 0 2006.285.11:57:03.20#ibcon#read 4, iclass 20, count 0 2006.285.11:57:03.20#ibcon#about to read 5, iclass 20, count 0 2006.285.11:57:03.20#ibcon#read 5, iclass 20, count 0 2006.285.11:57:03.20#ibcon#about to read 6, iclass 20, count 0 2006.285.11:57:03.20#ibcon#read 6, iclass 20, count 0 2006.285.11:57:03.20#ibcon#end of sib2, iclass 20, count 0 2006.285.11:57:03.20#ibcon#*after write, iclass 20, count 0 2006.285.11:57:03.20#ibcon#*before return 0, iclass 20, count 0 2006.285.11:57:03.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:57:03.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:57:03.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.11:57:03.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.11:57:03.20$vck44/va=2,6 2006.285.11:57:03.20#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.11:57:03.20#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.11:57:03.20#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:03.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:57:03.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:57:03.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:57:03.26#ibcon#enter wrdev, iclass 22, count 2 2006.285.11:57:03.26#ibcon#first serial, iclass 22, count 2 2006.285.11:57:03.26#ibcon#enter sib2, iclass 22, count 2 2006.285.11:57:03.26#ibcon#flushed, iclass 22, count 2 2006.285.11:57:03.26#ibcon#about to write, iclass 22, count 2 2006.285.11:57:03.26#ibcon#wrote, iclass 22, count 2 2006.285.11:57:03.26#ibcon#about to read 3, iclass 22, count 2 2006.285.11:57:03.28#ibcon#read 3, iclass 22, count 2 2006.285.11:57:03.28#ibcon#about to read 4, iclass 22, count 2 2006.285.11:57:03.28#ibcon#read 4, iclass 22, count 2 2006.285.11:57:03.28#ibcon#about to read 5, iclass 22, count 2 2006.285.11:57:03.28#ibcon#read 5, iclass 22, count 2 2006.285.11:57:03.28#ibcon#about to read 6, iclass 22, count 2 2006.285.11:57:03.28#ibcon#read 6, iclass 22, count 2 2006.285.11:57:03.28#ibcon#end of sib2, iclass 22, count 2 2006.285.11:57:03.28#ibcon#*mode == 0, iclass 22, count 2 2006.285.11:57:03.28#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.11:57:03.28#ibcon#[25=AT02-06\r\n] 2006.285.11:57:03.28#ibcon#*before write, iclass 22, count 2 2006.285.11:57:03.28#ibcon#enter sib2, iclass 22, count 2 2006.285.11:57:03.28#ibcon#flushed, iclass 22, count 2 2006.285.11:57:03.28#ibcon#about to write, iclass 22, count 2 2006.285.11:57:03.28#ibcon#wrote, iclass 22, count 2 2006.285.11:57:03.28#ibcon#about to read 3, iclass 22, count 2 2006.285.11:57:03.31#ibcon#read 3, iclass 22, count 2 2006.285.11:57:03.31#ibcon#about to read 4, iclass 22, count 2 2006.285.11:57:03.31#ibcon#read 4, iclass 22, count 2 2006.285.11:57:03.31#ibcon#about to read 5, iclass 22, count 2 2006.285.11:57:03.31#ibcon#read 5, iclass 22, count 2 2006.285.11:57:03.31#ibcon#about to read 6, iclass 22, count 2 2006.285.11:57:03.31#ibcon#read 6, iclass 22, count 2 2006.285.11:57:03.31#ibcon#end of sib2, iclass 22, count 2 2006.285.11:57:03.31#ibcon#*after write, iclass 22, count 2 2006.285.11:57:03.31#ibcon#*before return 0, iclass 22, count 2 2006.285.11:57:03.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:57:03.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:57:03.31#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.11:57:03.31#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:03.31#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:57:03.43#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:57:03.43#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:57:03.43#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:57:03.43#ibcon#first serial, iclass 22, count 0 2006.285.11:57:03.43#ibcon#enter sib2, iclass 22, count 0 2006.285.11:57:03.43#ibcon#flushed, iclass 22, count 0 2006.285.11:57:03.43#ibcon#about to write, iclass 22, count 0 2006.285.11:57:03.43#ibcon#wrote, iclass 22, count 0 2006.285.11:57:03.43#ibcon#about to read 3, iclass 22, count 0 2006.285.11:57:03.45#ibcon#read 3, iclass 22, count 0 2006.285.11:57:03.45#ibcon#about to read 4, iclass 22, count 0 2006.285.11:57:03.45#ibcon#read 4, iclass 22, count 0 2006.285.11:57:03.45#ibcon#about to read 5, iclass 22, count 0 2006.285.11:57:03.45#ibcon#read 5, iclass 22, count 0 2006.285.11:57:03.45#ibcon#about to read 6, iclass 22, count 0 2006.285.11:57:03.45#ibcon#read 6, iclass 22, count 0 2006.285.11:57:03.45#ibcon#end of sib2, iclass 22, count 0 2006.285.11:57:03.45#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:57:03.45#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:57:03.45#ibcon#[25=USB\r\n] 2006.285.11:57:03.45#ibcon#*before write, iclass 22, count 0 2006.285.11:57:03.45#ibcon#enter sib2, iclass 22, count 0 2006.285.11:57:03.45#ibcon#flushed, iclass 22, count 0 2006.285.11:57:03.45#ibcon#about to write, iclass 22, count 0 2006.285.11:57:03.45#ibcon#wrote, iclass 22, count 0 2006.285.11:57:03.45#ibcon#about to read 3, iclass 22, count 0 2006.285.11:57:03.48#ibcon#read 3, iclass 22, count 0 2006.285.11:57:03.48#ibcon#about to read 4, iclass 22, count 0 2006.285.11:57:03.48#ibcon#read 4, iclass 22, count 0 2006.285.11:57:03.48#ibcon#about to read 5, iclass 22, count 0 2006.285.11:57:03.48#ibcon#read 5, iclass 22, count 0 2006.285.11:57:03.48#ibcon#about to read 6, iclass 22, count 0 2006.285.11:57:03.48#ibcon#read 6, iclass 22, count 0 2006.285.11:57:03.48#ibcon#end of sib2, iclass 22, count 0 2006.285.11:57:03.48#ibcon#*after write, iclass 22, count 0 2006.285.11:57:03.48#ibcon#*before return 0, iclass 22, count 0 2006.285.11:57:03.48#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:57:03.48#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:57:03.48#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:57:03.48#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:57:03.48$vck44/valo=3,564.99 2006.285.11:57:03.48#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.11:57:03.48#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.11:57:03.48#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:03.48#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:57:03.48#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:57:03.48#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:57:03.48#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:57:03.48#ibcon#first serial, iclass 24, count 0 2006.285.11:57:03.48#ibcon#enter sib2, iclass 24, count 0 2006.285.11:57:03.48#ibcon#flushed, iclass 24, count 0 2006.285.11:57:03.48#ibcon#about to write, iclass 24, count 0 2006.285.11:57:03.48#ibcon#wrote, iclass 24, count 0 2006.285.11:57:03.48#ibcon#about to read 3, iclass 24, count 0 2006.285.11:57:03.50#ibcon#read 3, iclass 24, count 0 2006.285.11:57:03.50#ibcon#about to read 4, iclass 24, count 0 2006.285.11:57:03.50#ibcon#read 4, iclass 24, count 0 2006.285.11:57:03.50#ibcon#about to read 5, iclass 24, count 0 2006.285.11:57:03.50#ibcon#read 5, iclass 24, count 0 2006.285.11:57:03.50#ibcon#about to read 6, iclass 24, count 0 2006.285.11:57:03.50#ibcon#read 6, iclass 24, count 0 2006.285.11:57:03.50#ibcon#end of sib2, iclass 24, count 0 2006.285.11:57:03.50#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:57:03.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:57:03.50#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.11:57:03.50#ibcon#*before write, iclass 24, count 0 2006.285.11:57:03.50#ibcon#enter sib2, iclass 24, count 0 2006.285.11:57:03.50#ibcon#flushed, iclass 24, count 0 2006.285.11:57:03.50#ibcon#about to write, iclass 24, count 0 2006.285.11:57:03.50#ibcon#wrote, iclass 24, count 0 2006.285.11:57:03.50#ibcon#about to read 3, iclass 24, count 0 2006.285.11:57:03.54#ibcon#read 3, iclass 24, count 0 2006.285.11:57:03.54#ibcon#about to read 4, iclass 24, count 0 2006.285.11:57:03.54#ibcon#read 4, iclass 24, count 0 2006.285.11:57:03.54#ibcon#about to read 5, iclass 24, count 0 2006.285.11:57:03.54#ibcon#read 5, iclass 24, count 0 2006.285.11:57:03.54#ibcon#about to read 6, iclass 24, count 0 2006.285.11:57:03.54#ibcon#read 6, iclass 24, count 0 2006.285.11:57:03.54#ibcon#end of sib2, iclass 24, count 0 2006.285.11:57:03.54#ibcon#*after write, iclass 24, count 0 2006.285.11:57:03.54#ibcon#*before return 0, iclass 24, count 0 2006.285.11:57:03.54#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:57:03.54#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:57:03.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:57:03.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:57:03.54$vck44/va=3,7 2006.285.11:57:03.54#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.11:57:03.54#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.11:57:03.54#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:03.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:57:03.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:57:03.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:57:03.60#ibcon#enter wrdev, iclass 26, count 2 2006.285.11:57:03.60#ibcon#first serial, iclass 26, count 2 2006.285.11:57:03.60#ibcon#enter sib2, iclass 26, count 2 2006.285.11:57:03.60#ibcon#flushed, iclass 26, count 2 2006.285.11:57:03.60#ibcon#about to write, iclass 26, count 2 2006.285.11:57:03.60#ibcon#wrote, iclass 26, count 2 2006.285.11:57:03.60#ibcon#about to read 3, iclass 26, count 2 2006.285.11:57:03.62#ibcon#read 3, iclass 26, count 2 2006.285.11:57:03.62#ibcon#about to read 4, iclass 26, count 2 2006.285.11:57:03.62#ibcon#read 4, iclass 26, count 2 2006.285.11:57:03.62#ibcon#about to read 5, iclass 26, count 2 2006.285.11:57:03.62#ibcon#read 5, iclass 26, count 2 2006.285.11:57:03.62#ibcon#about to read 6, iclass 26, count 2 2006.285.11:57:03.62#ibcon#read 6, iclass 26, count 2 2006.285.11:57:03.62#ibcon#end of sib2, iclass 26, count 2 2006.285.11:57:03.62#ibcon#*mode == 0, iclass 26, count 2 2006.285.11:57:03.62#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.11:57:03.62#ibcon#[25=AT03-07\r\n] 2006.285.11:57:03.62#ibcon#*before write, iclass 26, count 2 2006.285.11:57:03.62#ibcon#enter sib2, iclass 26, count 2 2006.285.11:57:03.62#ibcon#flushed, iclass 26, count 2 2006.285.11:57:03.62#ibcon#about to write, iclass 26, count 2 2006.285.11:57:03.62#ibcon#wrote, iclass 26, count 2 2006.285.11:57:03.62#ibcon#about to read 3, iclass 26, count 2 2006.285.11:57:03.65#ibcon#read 3, iclass 26, count 2 2006.285.11:57:03.65#ibcon#about to read 4, iclass 26, count 2 2006.285.11:57:03.65#ibcon#read 4, iclass 26, count 2 2006.285.11:57:03.65#ibcon#about to read 5, iclass 26, count 2 2006.285.11:57:03.65#ibcon#read 5, iclass 26, count 2 2006.285.11:57:03.65#ibcon#about to read 6, iclass 26, count 2 2006.285.11:57:03.65#ibcon#read 6, iclass 26, count 2 2006.285.11:57:03.65#ibcon#end of sib2, iclass 26, count 2 2006.285.11:57:03.65#ibcon#*after write, iclass 26, count 2 2006.285.11:57:03.65#ibcon#*before return 0, iclass 26, count 2 2006.285.11:57:03.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:57:03.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:57:03.65#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.11:57:03.65#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:03.65#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:57:03.77#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:57:03.77#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:57:03.77#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:57:03.77#ibcon#first serial, iclass 26, count 0 2006.285.11:57:03.77#ibcon#enter sib2, iclass 26, count 0 2006.285.11:57:03.77#ibcon#flushed, iclass 26, count 0 2006.285.11:57:03.77#ibcon#about to write, iclass 26, count 0 2006.285.11:57:03.77#ibcon#wrote, iclass 26, count 0 2006.285.11:57:03.77#ibcon#about to read 3, iclass 26, count 0 2006.285.11:57:03.79#ibcon#read 3, iclass 26, count 0 2006.285.11:57:03.79#ibcon#about to read 4, iclass 26, count 0 2006.285.11:57:03.79#ibcon#read 4, iclass 26, count 0 2006.285.11:57:03.79#ibcon#about to read 5, iclass 26, count 0 2006.285.11:57:03.79#ibcon#read 5, iclass 26, count 0 2006.285.11:57:03.79#ibcon#about to read 6, iclass 26, count 0 2006.285.11:57:03.79#ibcon#read 6, iclass 26, count 0 2006.285.11:57:03.79#ibcon#end of sib2, iclass 26, count 0 2006.285.11:57:03.79#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:57:03.79#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:57:03.79#ibcon#[25=USB\r\n] 2006.285.11:57:03.79#ibcon#*before write, iclass 26, count 0 2006.285.11:57:03.79#ibcon#enter sib2, iclass 26, count 0 2006.285.11:57:03.79#ibcon#flushed, iclass 26, count 0 2006.285.11:57:03.79#ibcon#about to write, iclass 26, count 0 2006.285.11:57:03.79#ibcon#wrote, iclass 26, count 0 2006.285.11:57:03.79#ibcon#about to read 3, iclass 26, count 0 2006.285.11:57:03.82#ibcon#read 3, iclass 26, count 0 2006.285.11:57:03.82#ibcon#about to read 4, iclass 26, count 0 2006.285.11:57:03.82#ibcon#read 4, iclass 26, count 0 2006.285.11:57:03.82#ibcon#about to read 5, iclass 26, count 0 2006.285.11:57:03.82#ibcon#read 5, iclass 26, count 0 2006.285.11:57:03.82#ibcon#about to read 6, iclass 26, count 0 2006.285.11:57:03.82#ibcon#read 6, iclass 26, count 0 2006.285.11:57:03.82#ibcon#end of sib2, iclass 26, count 0 2006.285.11:57:03.82#ibcon#*after write, iclass 26, count 0 2006.285.11:57:03.82#ibcon#*before return 0, iclass 26, count 0 2006.285.11:57:03.82#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:57:03.82#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:57:03.82#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:57:03.82#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:57:03.82$vck44/valo=4,624.99 2006.285.11:57:03.82#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.11:57:03.82#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.11:57:03.82#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:03.82#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:57:03.82#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:57:03.82#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:57:03.82#ibcon#enter wrdev, iclass 28, count 0 2006.285.11:57:03.82#ibcon#first serial, iclass 28, count 0 2006.285.11:57:03.82#ibcon#enter sib2, iclass 28, count 0 2006.285.11:57:03.82#ibcon#flushed, iclass 28, count 0 2006.285.11:57:03.82#ibcon#about to write, iclass 28, count 0 2006.285.11:57:03.82#ibcon#wrote, iclass 28, count 0 2006.285.11:57:03.82#ibcon#about to read 3, iclass 28, count 0 2006.285.11:57:03.84#ibcon#read 3, iclass 28, count 0 2006.285.11:57:03.84#ibcon#about to read 4, iclass 28, count 0 2006.285.11:57:03.84#ibcon#read 4, iclass 28, count 0 2006.285.11:57:03.84#ibcon#about to read 5, iclass 28, count 0 2006.285.11:57:03.84#ibcon#read 5, iclass 28, count 0 2006.285.11:57:03.84#ibcon#about to read 6, iclass 28, count 0 2006.285.11:57:03.84#ibcon#read 6, iclass 28, count 0 2006.285.11:57:03.84#ibcon#end of sib2, iclass 28, count 0 2006.285.11:57:03.84#ibcon#*mode == 0, iclass 28, count 0 2006.285.11:57:03.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.11:57:03.84#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.11:57:03.84#ibcon#*before write, iclass 28, count 0 2006.285.11:57:03.84#ibcon#enter sib2, iclass 28, count 0 2006.285.11:57:03.84#ibcon#flushed, iclass 28, count 0 2006.285.11:57:03.84#ibcon#about to write, iclass 28, count 0 2006.285.11:57:03.84#ibcon#wrote, iclass 28, count 0 2006.285.11:57:03.84#ibcon#about to read 3, iclass 28, count 0 2006.285.11:57:03.88#ibcon#read 3, iclass 28, count 0 2006.285.11:57:03.88#ibcon#about to read 4, iclass 28, count 0 2006.285.11:57:03.88#ibcon#read 4, iclass 28, count 0 2006.285.11:57:03.88#ibcon#about to read 5, iclass 28, count 0 2006.285.11:57:03.88#ibcon#read 5, iclass 28, count 0 2006.285.11:57:03.88#ibcon#about to read 6, iclass 28, count 0 2006.285.11:57:03.88#ibcon#read 6, iclass 28, count 0 2006.285.11:57:03.88#ibcon#end of sib2, iclass 28, count 0 2006.285.11:57:03.88#ibcon#*after write, iclass 28, count 0 2006.285.11:57:03.88#ibcon#*before return 0, iclass 28, count 0 2006.285.11:57:03.88#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:57:03.88#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:57:03.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.11:57:03.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.11:57:03.88$vck44/va=4,6 2006.285.11:57:03.88#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.11:57:03.88#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.11:57:03.88#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:03.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:57:03.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:57:03.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:57:03.94#ibcon#enter wrdev, iclass 30, count 2 2006.285.11:57:03.94#ibcon#first serial, iclass 30, count 2 2006.285.11:57:03.94#ibcon#enter sib2, iclass 30, count 2 2006.285.11:57:03.94#ibcon#flushed, iclass 30, count 2 2006.285.11:57:03.94#ibcon#about to write, iclass 30, count 2 2006.285.11:57:03.94#ibcon#wrote, iclass 30, count 2 2006.285.11:57:03.94#ibcon#about to read 3, iclass 30, count 2 2006.285.11:57:03.96#ibcon#read 3, iclass 30, count 2 2006.285.11:57:03.96#ibcon#about to read 4, iclass 30, count 2 2006.285.11:57:03.96#ibcon#read 4, iclass 30, count 2 2006.285.11:57:03.96#ibcon#about to read 5, iclass 30, count 2 2006.285.11:57:03.96#ibcon#read 5, iclass 30, count 2 2006.285.11:57:03.96#ibcon#about to read 6, iclass 30, count 2 2006.285.11:57:03.96#ibcon#read 6, iclass 30, count 2 2006.285.11:57:03.96#ibcon#end of sib2, iclass 30, count 2 2006.285.11:57:03.96#ibcon#*mode == 0, iclass 30, count 2 2006.285.11:57:03.96#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.11:57:03.96#ibcon#[25=AT04-06\r\n] 2006.285.11:57:03.96#ibcon#*before write, iclass 30, count 2 2006.285.11:57:03.96#ibcon#enter sib2, iclass 30, count 2 2006.285.11:57:03.96#ibcon#flushed, iclass 30, count 2 2006.285.11:57:03.96#ibcon#about to write, iclass 30, count 2 2006.285.11:57:03.96#ibcon#wrote, iclass 30, count 2 2006.285.11:57:03.96#ibcon#about to read 3, iclass 30, count 2 2006.285.11:57:03.99#ibcon#read 3, iclass 30, count 2 2006.285.11:57:03.99#ibcon#about to read 4, iclass 30, count 2 2006.285.11:57:03.99#ibcon#read 4, iclass 30, count 2 2006.285.11:57:03.99#ibcon#about to read 5, iclass 30, count 2 2006.285.11:57:03.99#ibcon#read 5, iclass 30, count 2 2006.285.11:57:03.99#ibcon#about to read 6, iclass 30, count 2 2006.285.11:57:03.99#ibcon#read 6, iclass 30, count 2 2006.285.11:57:03.99#ibcon#end of sib2, iclass 30, count 2 2006.285.11:57:03.99#ibcon#*after write, iclass 30, count 2 2006.285.11:57:03.99#ibcon#*before return 0, iclass 30, count 2 2006.285.11:57:03.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:57:03.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:57:03.99#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.11:57:03.99#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:03.99#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:57:04.11#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:57:04.11#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:57:04.11#ibcon#enter wrdev, iclass 30, count 0 2006.285.11:57:04.11#ibcon#first serial, iclass 30, count 0 2006.285.11:57:04.11#ibcon#enter sib2, iclass 30, count 0 2006.285.11:57:04.11#ibcon#flushed, iclass 30, count 0 2006.285.11:57:04.11#ibcon#about to write, iclass 30, count 0 2006.285.11:57:04.11#ibcon#wrote, iclass 30, count 0 2006.285.11:57:04.11#ibcon#about to read 3, iclass 30, count 0 2006.285.11:57:04.13#ibcon#read 3, iclass 30, count 0 2006.285.11:57:04.13#ibcon#about to read 4, iclass 30, count 0 2006.285.11:57:04.13#ibcon#read 4, iclass 30, count 0 2006.285.11:57:04.13#ibcon#about to read 5, iclass 30, count 0 2006.285.11:57:04.13#ibcon#read 5, iclass 30, count 0 2006.285.11:57:04.13#ibcon#about to read 6, iclass 30, count 0 2006.285.11:57:04.13#ibcon#read 6, iclass 30, count 0 2006.285.11:57:04.13#ibcon#end of sib2, iclass 30, count 0 2006.285.11:57:04.13#ibcon#*mode == 0, iclass 30, count 0 2006.285.11:57:04.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.11:57:04.13#ibcon#[25=USB\r\n] 2006.285.11:57:04.13#ibcon#*before write, iclass 30, count 0 2006.285.11:57:04.13#ibcon#enter sib2, iclass 30, count 0 2006.285.11:57:04.13#ibcon#flushed, iclass 30, count 0 2006.285.11:57:04.13#ibcon#about to write, iclass 30, count 0 2006.285.11:57:04.13#ibcon#wrote, iclass 30, count 0 2006.285.11:57:04.13#ibcon#about to read 3, iclass 30, count 0 2006.285.11:57:04.16#ibcon#read 3, iclass 30, count 0 2006.285.11:57:04.16#ibcon#about to read 4, iclass 30, count 0 2006.285.11:57:04.16#ibcon#read 4, iclass 30, count 0 2006.285.11:57:04.16#ibcon#about to read 5, iclass 30, count 0 2006.285.11:57:04.16#ibcon#read 5, iclass 30, count 0 2006.285.11:57:04.16#ibcon#about to read 6, iclass 30, count 0 2006.285.11:57:04.16#ibcon#read 6, iclass 30, count 0 2006.285.11:57:04.16#ibcon#end of sib2, iclass 30, count 0 2006.285.11:57:04.16#ibcon#*after write, iclass 30, count 0 2006.285.11:57:04.16#ibcon#*before return 0, iclass 30, count 0 2006.285.11:57:04.16#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:57:04.16#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:57:04.16#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.11:57:04.16#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.11:57:04.16$vck44/valo=5,734.99 2006.285.11:57:04.16#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.11:57:04.16#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.11:57:04.16#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:04.16#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:57:04.16#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:57:04.16#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:57:04.16#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:57:04.16#ibcon#first serial, iclass 32, count 0 2006.285.11:57:04.16#ibcon#enter sib2, iclass 32, count 0 2006.285.11:57:04.16#ibcon#flushed, iclass 32, count 0 2006.285.11:57:04.16#ibcon#about to write, iclass 32, count 0 2006.285.11:57:04.16#ibcon#wrote, iclass 32, count 0 2006.285.11:57:04.16#ibcon#about to read 3, iclass 32, count 0 2006.285.11:57:04.18#ibcon#read 3, iclass 32, count 0 2006.285.11:57:04.18#ibcon#about to read 4, iclass 32, count 0 2006.285.11:57:04.18#ibcon#read 4, iclass 32, count 0 2006.285.11:57:04.18#ibcon#about to read 5, iclass 32, count 0 2006.285.11:57:04.18#ibcon#read 5, iclass 32, count 0 2006.285.11:57:04.18#ibcon#about to read 6, iclass 32, count 0 2006.285.11:57:04.18#ibcon#read 6, iclass 32, count 0 2006.285.11:57:04.18#ibcon#end of sib2, iclass 32, count 0 2006.285.11:57:04.18#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:57:04.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:57:04.18#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.11:57:04.18#ibcon#*before write, iclass 32, count 0 2006.285.11:57:04.18#ibcon#enter sib2, iclass 32, count 0 2006.285.11:57:04.18#ibcon#flushed, iclass 32, count 0 2006.285.11:57:04.18#ibcon#about to write, iclass 32, count 0 2006.285.11:57:04.18#ibcon#wrote, iclass 32, count 0 2006.285.11:57:04.18#ibcon#about to read 3, iclass 32, count 0 2006.285.11:57:04.22#ibcon#read 3, iclass 32, count 0 2006.285.11:57:04.22#ibcon#about to read 4, iclass 32, count 0 2006.285.11:57:04.22#ibcon#read 4, iclass 32, count 0 2006.285.11:57:04.22#ibcon#about to read 5, iclass 32, count 0 2006.285.11:57:04.22#ibcon#read 5, iclass 32, count 0 2006.285.11:57:04.22#ibcon#about to read 6, iclass 32, count 0 2006.285.11:57:04.22#ibcon#read 6, iclass 32, count 0 2006.285.11:57:04.22#ibcon#end of sib2, iclass 32, count 0 2006.285.11:57:04.22#ibcon#*after write, iclass 32, count 0 2006.285.11:57:04.22#ibcon#*before return 0, iclass 32, count 0 2006.285.11:57:04.22#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:57:04.22#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:57:04.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:57:04.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:57:04.22$vck44/va=5,3 2006.285.11:57:04.22#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.11:57:04.22#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.11:57:04.22#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:04.22#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:57:04.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:57:04.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:57:04.28#ibcon#enter wrdev, iclass 34, count 2 2006.285.11:57:04.28#ibcon#first serial, iclass 34, count 2 2006.285.11:57:04.28#ibcon#enter sib2, iclass 34, count 2 2006.285.11:57:04.28#ibcon#flushed, iclass 34, count 2 2006.285.11:57:04.28#ibcon#about to write, iclass 34, count 2 2006.285.11:57:04.28#ibcon#wrote, iclass 34, count 2 2006.285.11:57:04.28#ibcon#about to read 3, iclass 34, count 2 2006.285.11:57:04.30#ibcon#read 3, iclass 34, count 2 2006.285.11:57:04.30#ibcon#about to read 4, iclass 34, count 2 2006.285.11:57:04.30#ibcon#read 4, iclass 34, count 2 2006.285.11:57:04.30#ibcon#about to read 5, iclass 34, count 2 2006.285.11:57:04.30#ibcon#read 5, iclass 34, count 2 2006.285.11:57:04.30#ibcon#about to read 6, iclass 34, count 2 2006.285.11:57:04.30#ibcon#read 6, iclass 34, count 2 2006.285.11:57:04.30#ibcon#end of sib2, iclass 34, count 2 2006.285.11:57:04.30#ibcon#*mode == 0, iclass 34, count 2 2006.285.11:57:04.30#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.11:57:04.30#ibcon#[25=AT05-03\r\n] 2006.285.11:57:04.30#ibcon#*before write, iclass 34, count 2 2006.285.11:57:04.30#ibcon#enter sib2, iclass 34, count 2 2006.285.11:57:04.30#ibcon#flushed, iclass 34, count 2 2006.285.11:57:04.30#ibcon#about to write, iclass 34, count 2 2006.285.11:57:04.30#ibcon#wrote, iclass 34, count 2 2006.285.11:57:04.30#ibcon#about to read 3, iclass 34, count 2 2006.285.11:57:04.33#ibcon#read 3, iclass 34, count 2 2006.285.11:57:04.33#ibcon#about to read 4, iclass 34, count 2 2006.285.11:57:04.33#ibcon#read 4, iclass 34, count 2 2006.285.11:57:04.33#ibcon#about to read 5, iclass 34, count 2 2006.285.11:57:04.33#ibcon#read 5, iclass 34, count 2 2006.285.11:57:04.33#ibcon#about to read 6, iclass 34, count 2 2006.285.11:57:04.33#ibcon#read 6, iclass 34, count 2 2006.285.11:57:04.33#ibcon#end of sib2, iclass 34, count 2 2006.285.11:57:04.33#ibcon#*after write, iclass 34, count 2 2006.285.11:57:04.33#ibcon#*before return 0, iclass 34, count 2 2006.285.11:57:04.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:57:04.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:57:04.33#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.11:57:04.33#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:04.33#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:57:04.45#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:57:04.45#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:57:04.45#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:57:04.45#ibcon#first serial, iclass 34, count 0 2006.285.11:57:04.45#ibcon#enter sib2, iclass 34, count 0 2006.285.11:57:04.45#ibcon#flushed, iclass 34, count 0 2006.285.11:57:04.45#ibcon#about to write, iclass 34, count 0 2006.285.11:57:04.45#ibcon#wrote, iclass 34, count 0 2006.285.11:57:04.45#ibcon#about to read 3, iclass 34, count 0 2006.285.11:57:04.47#ibcon#read 3, iclass 34, count 0 2006.285.11:57:04.47#ibcon#about to read 4, iclass 34, count 0 2006.285.11:57:04.47#ibcon#read 4, iclass 34, count 0 2006.285.11:57:04.47#ibcon#about to read 5, iclass 34, count 0 2006.285.11:57:04.47#ibcon#read 5, iclass 34, count 0 2006.285.11:57:04.47#ibcon#about to read 6, iclass 34, count 0 2006.285.11:57:04.47#ibcon#read 6, iclass 34, count 0 2006.285.11:57:04.47#ibcon#end of sib2, iclass 34, count 0 2006.285.11:57:04.47#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:57:04.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:57:04.47#ibcon#[25=USB\r\n] 2006.285.11:57:04.47#ibcon#*before write, iclass 34, count 0 2006.285.11:57:04.47#ibcon#enter sib2, iclass 34, count 0 2006.285.11:57:04.47#ibcon#flushed, iclass 34, count 0 2006.285.11:57:04.47#ibcon#about to write, iclass 34, count 0 2006.285.11:57:04.47#ibcon#wrote, iclass 34, count 0 2006.285.11:57:04.47#ibcon#about to read 3, iclass 34, count 0 2006.285.11:57:04.50#ibcon#read 3, iclass 34, count 0 2006.285.11:57:04.50#ibcon#about to read 4, iclass 34, count 0 2006.285.11:57:04.50#ibcon#read 4, iclass 34, count 0 2006.285.11:57:04.50#ibcon#about to read 5, iclass 34, count 0 2006.285.11:57:04.50#ibcon#read 5, iclass 34, count 0 2006.285.11:57:04.50#ibcon#about to read 6, iclass 34, count 0 2006.285.11:57:04.50#ibcon#read 6, iclass 34, count 0 2006.285.11:57:04.50#ibcon#end of sib2, iclass 34, count 0 2006.285.11:57:04.50#ibcon#*after write, iclass 34, count 0 2006.285.11:57:04.50#ibcon#*before return 0, iclass 34, count 0 2006.285.11:57:04.50#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:57:04.50#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:57:04.50#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:57:04.50#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:57:04.50$vck44/valo=6,814.99 2006.285.11:57:04.50#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.11:57:04.50#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.11:57:04.50#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:04.50#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:57:04.50#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:57:04.50#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:57:04.50#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:57:04.50#ibcon#first serial, iclass 36, count 0 2006.285.11:57:04.50#ibcon#enter sib2, iclass 36, count 0 2006.285.11:57:04.50#ibcon#flushed, iclass 36, count 0 2006.285.11:57:04.50#ibcon#about to write, iclass 36, count 0 2006.285.11:57:04.50#ibcon#wrote, iclass 36, count 0 2006.285.11:57:04.50#ibcon#about to read 3, iclass 36, count 0 2006.285.11:57:04.52#ibcon#read 3, iclass 36, count 0 2006.285.11:57:04.52#ibcon#about to read 4, iclass 36, count 0 2006.285.11:57:04.52#ibcon#read 4, iclass 36, count 0 2006.285.11:57:04.52#ibcon#about to read 5, iclass 36, count 0 2006.285.11:57:04.52#ibcon#read 5, iclass 36, count 0 2006.285.11:57:04.52#ibcon#about to read 6, iclass 36, count 0 2006.285.11:57:04.52#ibcon#read 6, iclass 36, count 0 2006.285.11:57:04.52#ibcon#end of sib2, iclass 36, count 0 2006.285.11:57:04.52#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:57:04.52#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:57:04.52#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.11:57:04.52#ibcon#*before write, iclass 36, count 0 2006.285.11:57:04.52#ibcon#enter sib2, iclass 36, count 0 2006.285.11:57:04.52#ibcon#flushed, iclass 36, count 0 2006.285.11:57:04.52#ibcon#about to write, iclass 36, count 0 2006.285.11:57:04.52#ibcon#wrote, iclass 36, count 0 2006.285.11:57:04.52#ibcon#about to read 3, iclass 36, count 0 2006.285.11:57:04.56#ibcon#read 3, iclass 36, count 0 2006.285.11:57:04.56#ibcon#about to read 4, iclass 36, count 0 2006.285.11:57:04.56#ibcon#read 4, iclass 36, count 0 2006.285.11:57:04.56#ibcon#about to read 5, iclass 36, count 0 2006.285.11:57:04.56#ibcon#read 5, iclass 36, count 0 2006.285.11:57:04.56#ibcon#about to read 6, iclass 36, count 0 2006.285.11:57:04.56#ibcon#read 6, iclass 36, count 0 2006.285.11:57:04.56#ibcon#end of sib2, iclass 36, count 0 2006.285.11:57:04.56#ibcon#*after write, iclass 36, count 0 2006.285.11:57:04.56#ibcon#*before return 0, iclass 36, count 0 2006.285.11:57:04.56#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:57:04.56#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:57:04.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:57:04.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:57:04.56$vck44/va=6,4 2006.285.11:57:04.56#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.11:57:04.56#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.11:57:04.56#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:04.56#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:57:04.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:57:04.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:57:04.62#ibcon#enter wrdev, iclass 38, count 2 2006.285.11:57:04.62#ibcon#first serial, iclass 38, count 2 2006.285.11:57:04.62#ibcon#enter sib2, iclass 38, count 2 2006.285.11:57:04.62#ibcon#flushed, iclass 38, count 2 2006.285.11:57:04.62#ibcon#about to write, iclass 38, count 2 2006.285.11:57:04.62#ibcon#wrote, iclass 38, count 2 2006.285.11:57:04.62#ibcon#about to read 3, iclass 38, count 2 2006.285.11:57:04.64#ibcon#read 3, iclass 38, count 2 2006.285.11:57:04.64#ibcon#about to read 4, iclass 38, count 2 2006.285.11:57:04.64#ibcon#read 4, iclass 38, count 2 2006.285.11:57:04.64#ibcon#about to read 5, iclass 38, count 2 2006.285.11:57:04.64#ibcon#read 5, iclass 38, count 2 2006.285.11:57:04.64#ibcon#about to read 6, iclass 38, count 2 2006.285.11:57:04.64#ibcon#read 6, iclass 38, count 2 2006.285.11:57:04.64#ibcon#end of sib2, iclass 38, count 2 2006.285.11:57:04.64#ibcon#*mode == 0, iclass 38, count 2 2006.285.11:57:04.64#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.11:57:04.64#ibcon#[25=AT06-04\r\n] 2006.285.11:57:04.64#ibcon#*before write, iclass 38, count 2 2006.285.11:57:04.64#ibcon#enter sib2, iclass 38, count 2 2006.285.11:57:04.64#ibcon#flushed, iclass 38, count 2 2006.285.11:57:04.64#ibcon#about to write, iclass 38, count 2 2006.285.11:57:04.64#ibcon#wrote, iclass 38, count 2 2006.285.11:57:04.64#ibcon#about to read 3, iclass 38, count 2 2006.285.11:57:04.67#ibcon#read 3, iclass 38, count 2 2006.285.11:57:04.67#ibcon#about to read 4, iclass 38, count 2 2006.285.11:57:04.67#ibcon#read 4, iclass 38, count 2 2006.285.11:57:04.67#ibcon#about to read 5, iclass 38, count 2 2006.285.11:57:04.67#ibcon#read 5, iclass 38, count 2 2006.285.11:57:04.67#ibcon#about to read 6, iclass 38, count 2 2006.285.11:57:04.67#ibcon#read 6, iclass 38, count 2 2006.285.11:57:04.67#ibcon#end of sib2, iclass 38, count 2 2006.285.11:57:04.67#ibcon#*after write, iclass 38, count 2 2006.285.11:57:04.67#ibcon#*before return 0, iclass 38, count 2 2006.285.11:57:04.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:57:04.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.11:57:04.67#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.11:57:04.67#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:04.67#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:57:04.79#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:57:04.79#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:57:04.79#ibcon#enter wrdev, iclass 38, count 0 2006.285.11:57:04.79#ibcon#first serial, iclass 38, count 0 2006.285.11:57:04.79#ibcon#enter sib2, iclass 38, count 0 2006.285.11:57:04.79#ibcon#flushed, iclass 38, count 0 2006.285.11:57:04.79#ibcon#about to write, iclass 38, count 0 2006.285.11:57:04.79#ibcon#wrote, iclass 38, count 0 2006.285.11:57:04.79#ibcon#about to read 3, iclass 38, count 0 2006.285.11:57:04.81#ibcon#read 3, iclass 38, count 0 2006.285.11:57:04.81#ibcon#about to read 4, iclass 38, count 0 2006.285.11:57:04.81#ibcon#read 4, iclass 38, count 0 2006.285.11:57:04.81#ibcon#about to read 5, iclass 38, count 0 2006.285.11:57:04.81#ibcon#read 5, iclass 38, count 0 2006.285.11:57:04.81#ibcon#about to read 6, iclass 38, count 0 2006.285.11:57:04.81#ibcon#read 6, iclass 38, count 0 2006.285.11:57:04.81#ibcon#end of sib2, iclass 38, count 0 2006.285.11:57:04.81#ibcon#*mode == 0, iclass 38, count 0 2006.285.11:57:04.81#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.11:57:04.81#ibcon#[25=USB\r\n] 2006.285.11:57:04.81#ibcon#*before write, iclass 38, count 0 2006.285.11:57:04.81#ibcon#enter sib2, iclass 38, count 0 2006.285.11:57:04.81#ibcon#flushed, iclass 38, count 0 2006.285.11:57:04.81#ibcon#about to write, iclass 38, count 0 2006.285.11:57:04.81#ibcon#wrote, iclass 38, count 0 2006.285.11:57:04.81#ibcon#about to read 3, iclass 38, count 0 2006.285.11:57:04.84#ibcon#read 3, iclass 38, count 0 2006.285.11:57:04.84#ibcon#about to read 4, iclass 38, count 0 2006.285.11:57:04.84#ibcon#read 4, iclass 38, count 0 2006.285.11:57:04.84#ibcon#about to read 5, iclass 38, count 0 2006.285.11:57:04.84#ibcon#read 5, iclass 38, count 0 2006.285.11:57:04.84#ibcon#about to read 6, iclass 38, count 0 2006.285.11:57:04.84#ibcon#read 6, iclass 38, count 0 2006.285.11:57:04.84#ibcon#end of sib2, iclass 38, count 0 2006.285.11:57:04.84#ibcon#*after write, iclass 38, count 0 2006.285.11:57:04.84#ibcon#*before return 0, iclass 38, count 0 2006.285.11:57:04.84#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:57:04.84#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.11:57:04.84#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.11:57:04.84#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.11:57:04.84$vck44/valo=7,864.99 2006.285.11:57:04.84#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.11:57:04.84#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.11:57:04.84#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:04.84#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:57:04.84#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:57:04.84#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:57:04.84#ibcon#enter wrdev, iclass 40, count 0 2006.285.11:57:04.84#ibcon#first serial, iclass 40, count 0 2006.285.11:57:04.84#ibcon#enter sib2, iclass 40, count 0 2006.285.11:57:04.84#ibcon#flushed, iclass 40, count 0 2006.285.11:57:04.84#ibcon#about to write, iclass 40, count 0 2006.285.11:57:04.84#ibcon#wrote, iclass 40, count 0 2006.285.11:57:04.84#ibcon#about to read 3, iclass 40, count 0 2006.285.11:57:04.86#ibcon#read 3, iclass 40, count 0 2006.285.11:57:04.86#ibcon#about to read 4, iclass 40, count 0 2006.285.11:57:04.86#ibcon#read 4, iclass 40, count 0 2006.285.11:57:04.86#ibcon#about to read 5, iclass 40, count 0 2006.285.11:57:04.86#ibcon#read 5, iclass 40, count 0 2006.285.11:57:04.86#ibcon#about to read 6, iclass 40, count 0 2006.285.11:57:04.86#ibcon#read 6, iclass 40, count 0 2006.285.11:57:04.86#ibcon#end of sib2, iclass 40, count 0 2006.285.11:57:04.86#ibcon#*mode == 0, iclass 40, count 0 2006.285.11:57:04.86#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.11:57:04.86#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.11:57:04.86#ibcon#*before write, iclass 40, count 0 2006.285.11:57:04.86#ibcon#enter sib2, iclass 40, count 0 2006.285.11:57:04.86#ibcon#flushed, iclass 40, count 0 2006.285.11:57:04.86#ibcon#about to write, iclass 40, count 0 2006.285.11:57:04.86#ibcon#wrote, iclass 40, count 0 2006.285.11:57:04.86#ibcon#about to read 3, iclass 40, count 0 2006.285.11:57:04.90#ibcon#read 3, iclass 40, count 0 2006.285.11:57:04.90#ibcon#about to read 4, iclass 40, count 0 2006.285.11:57:04.90#ibcon#read 4, iclass 40, count 0 2006.285.11:57:04.90#ibcon#about to read 5, iclass 40, count 0 2006.285.11:57:04.90#ibcon#read 5, iclass 40, count 0 2006.285.11:57:04.90#ibcon#about to read 6, iclass 40, count 0 2006.285.11:57:04.90#ibcon#read 6, iclass 40, count 0 2006.285.11:57:04.90#ibcon#end of sib2, iclass 40, count 0 2006.285.11:57:04.90#ibcon#*after write, iclass 40, count 0 2006.285.11:57:04.90#ibcon#*before return 0, iclass 40, count 0 2006.285.11:57:04.90#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:57:04.90#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.11:57:04.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.11:57:04.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.11:57:04.90$vck44/va=7,4 2006.285.11:57:04.90#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.11:57:04.90#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.11:57:04.90#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:04.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:57:04.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:57:04.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:57:04.96#ibcon#enter wrdev, iclass 4, count 2 2006.285.11:57:04.96#ibcon#first serial, iclass 4, count 2 2006.285.11:57:04.96#ibcon#enter sib2, iclass 4, count 2 2006.285.11:57:04.96#ibcon#flushed, iclass 4, count 2 2006.285.11:57:04.96#ibcon#about to write, iclass 4, count 2 2006.285.11:57:04.96#ibcon#wrote, iclass 4, count 2 2006.285.11:57:04.96#ibcon#about to read 3, iclass 4, count 2 2006.285.11:57:04.98#ibcon#read 3, iclass 4, count 2 2006.285.11:57:04.98#ibcon#about to read 4, iclass 4, count 2 2006.285.11:57:04.98#ibcon#read 4, iclass 4, count 2 2006.285.11:57:04.98#ibcon#about to read 5, iclass 4, count 2 2006.285.11:57:04.98#ibcon#read 5, iclass 4, count 2 2006.285.11:57:04.98#ibcon#about to read 6, iclass 4, count 2 2006.285.11:57:04.98#ibcon#read 6, iclass 4, count 2 2006.285.11:57:04.98#ibcon#end of sib2, iclass 4, count 2 2006.285.11:57:04.98#ibcon#*mode == 0, iclass 4, count 2 2006.285.11:57:04.98#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.11:57:04.98#ibcon#[25=AT07-04\r\n] 2006.285.11:57:04.98#ibcon#*before write, iclass 4, count 2 2006.285.11:57:04.98#ibcon#enter sib2, iclass 4, count 2 2006.285.11:57:04.98#ibcon#flushed, iclass 4, count 2 2006.285.11:57:04.98#ibcon#about to write, iclass 4, count 2 2006.285.11:57:04.98#ibcon#wrote, iclass 4, count 2 2006.285.11:57:04.98#ibcon#about to read 3, iclass 4, count 2 2006.285.11:57:05.01#ibcon#read 3, iclass 4, count 2 2006.285.11:57:05.01#ibcon#about to read 4, iclass 4, count 2 2006.285.11:57:05.01#ibcon#read 4, iclass 4, count 2 2006.285.11:57:05.01#ibcon#about to read 5, iclass 4, count 2 2006.285.11:57:05.01#ibcon#read 5, iclass 4, count 2 2006.285.11:57:05.01#ibcon#about to read 6, iclass 4, count 2 2006.285.11:57:05.01#ibcon#read 6, iclass 4, count 2 2006.285.11:57:05.01#ibcon#end of sib2, iclass 4, count 2 2006.285.11:57:05.01#ibcon#*after write, iclass 4, count 2 2006.285.11:57:05.01#ibcon#*before return 0, iclass 4, count 2 2006.285.11:57:05.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:57:05.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.11:57:05.01#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.11:57:05.01#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:05.01#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:57:05.13#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:57:05.13#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:57:05.13#ibcon#enter wrdev, iclass 4, count 0 2006.285.11:57:05.13#ibcon#first serial, iclass 4, count 0 2006.285.11:57:05.13#ibcon#enter sib2, iclass 4, count 0 2006.285.11:57:05.13#ibcon#flushed, iclass 4, count 0 2006.285.11:57:05.13#ibcon#about to write, iclass 4, count 0 2006.285.11:57:05.13#ibcon#wrote, iclass 4, count 0 2006.285.11:57:05.13#ibcon#about to read 3, iclass 4, count 0 2006.285.11:57:05.15#ibcon#read 3, iclass 4, count 0 2006.285.11:57:05.15#ibcon#about to read 4, iclass 4, count 0 2006.285.11:57:05.15#ibcon#read 4, iclass 4, count 0 2006.285.11:57:05.15#ibcon#about to read 5, iclass 4, count 0 2006.285.11:57:05.15#ibcon#read 5, iclass 4, count 0 2006.285.11:57:05.15#ibcon#about to read 6, iclass 4, count 0 2006.285.11:57:05.15#ibcon#read 6, iclass 4, count 0 2006.285.11:57:05.15#ibcon#end of sib2, iclass 4, count 0 2006.285.11:57:05.15#ibcon#*mode == 0, iclass 4, count 0 2006.285.11:57:05.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.11:57:05.15#ibcon#[25=USB\r\n] 2006.285.11:57:05.15#ibcon#*before write, iclass 4, count 0 2006.285.11:57:05.15#ibcon#enter sib2, iclass 4, count 0 2006.285.11:57:05.15#ibcon#flushed, iclass 4, count 0 2006.285.11:57:05.15#ibcon#about to write, iclass 4, count 0 2006.285.11:57:05.15#ibcon#wrote, iclass 4, count 0 2006.285.11:57:05.15#ibcon#about to read 3, iclass 4, count 0 2006.285.11:57:05.18#ibcon#read 3, iclass 4, count 0 2006.285.11:57:05.18#ibcon#about to read 4, iclass 4, count 0 2006.285.11:57:05.18#ibcon#read 4, iclass 4, count 0 2006.285.11:57:05.18#ibcon#about to read 5, iclass 4, count 0 2006.285.11:57:05.18#ibcon#read 5, iclass 4, count 0 2006.285.11:57:05.18#ibcon#about to read 6, iclass 4, count 0 2006.285.11:57:05.18#ibcon#read 6, iclass 4, count 0 2006.285.11:57:05.18#ibcon#end of sib2, iclass 4, count 0 2006.285.11:57:05.18#ibcon#*after write, iclass 4, count 0 2006.285.11:57:05.18#ibcon#*before return 0, iclass 4, count 0 2006.285.11:57:05.18#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:57:05.18#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.11:57:05.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.11:57:05.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.11:57:05.18$vck44/valo=8,884.99 2006.285.11:57:05.18#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.11:57:05.18#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.11:57:05.18#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:05.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:57:05.18#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:57:05.18#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:57:05.18#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:57:05.18#ibcon#first serial, iclass 6, count 0 2006.285.11:57:05.18#ibcon#enter sib2, iclass 6, count 0 2006.285.11:57:05.18#ibcon#flushed, iclass 6, count 0 2006.285.11:57:05.18#ibcon#about to write, iclass 6, count 0 2006.285.11:57:05.18#ibcon#wrote, iclass 6, count 0 2006.285.11:57:05.18#ibcon#about to read 3, iclass 6, count 0 2006.285.11:57:05.20#ibcon#read 3, iclass 6, count 0 2006.285.11:57:05.20#ibcon#about to read 4, iclass 6, count 0 2006.285.11:57:05.20#ibcon#read 4, iclass 6, count 0 2006.285.11:57:05.20#ibcon#about to read 5, iclass 6, count 0 2006.285.11:57:05.20#ibcon#read 5, iclass 6, count 0 2006.285.11:57:05.20#ibcon#about to read 6, iclass 6, count 0 2006.285.11:57:05.20#ibcon#read 6, iclass 6, count 0 2006.285.11:57:05.20#ibcon#end of sib2, iclass 6, count 0 2006.285.11:57:05.20#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:57:05.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:57:05.20#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.11:57:05.20#ibcon#*before write, iclass 6, count 0 2006.285.11:57:05.20#ibcon#enter sib2, iclass 6, count 0 2006.285.11:57:05.20#ibcon#flushed, iclass 6, count 0 2006.285.11:57:05.20#ibcon#about to write, iclass 6, count 0 2006.285.11:57:05.20#ibcon#wrote, iclass 6, count 0 2006.285.11:57:05.20#ibcon#about to read 3, iclass 6, count 0 2006.285.11:57:05.24#ibcon#read 3, iclass 6, count 0 2006.285.11:57:05.24#ibcon#about to read 4, iclass 6, count 0 2006.285.11:57:05.24#ibcon#read 4, iclass 6, count 0 2006.285.11:57:05.24#ibcon#about to read 5, iclass 6, count 0 2006.285.11:57:05.24#ibcon#read 5, iclass 6, count 0 2006.285.11:57:05.24#ibcon#about to read 6, iclass 6, count 0 2006.285.11:57:05.24#ibcon#read 6, iclass 6, count 0 2006.285.11:57:05.24#ibcon#end of sib2, iclass 6, count 0 2006.285.11:57:05.24#ibcon#*after write, iclass 6, count 0 2006.285.11:57:05.24#ibcon#*before return 0, iclass 6, count 0 2006.285.11:57:05.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:57:05.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:57:05.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:57:05.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:57:05.24$vck44/va=8,3 2006.285.11:57:05.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.11:57:05.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.11:57:05.24#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:05.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:57:05.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:57:05.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:57:05.30#ibcon#enter wrdev, iclass 10, count 2 2006.285.11:57:05.30#ibcon#first serial, iclass 10, count 2 2006.285.11:57:05.30#ibcon#enter sib2, iclass 10, count 2 2006.285.11:57:05.30#ibcon#flushed, iclass 10, count 2 2006.285.11:57:05.30#ibcon#about to write, iclass 10, count 2 2006.285.11:57:05.30#ibcon#wrote, iclass 10, count 2 2006.285.11:57:05.30#ibcon#about to read 3, iclass 10, count 2 2006.285.11:57:05.32#ibcon#read 3, iclass 10, count 2 2006.285.11:57:05.32#ibcon#about to read 4, iclass 10, count 2 2006.285.11:57:05.32#ibcon#read 4, iclass 10, count 2 2006.285.11:57:05.32#ibcon#about to read 5, iclass 10, count 2 2006.285.11:57:05.32#ibcon#read 5, iclass 10, count 2 2006.285.11:57:05.32#ibcon#about to read 6, iclass 10, count 2 2006.285.11:57:05.32#ibcon#read 6, iclass 10, count 2 2006.285.11:57:05.32#ibcon#end of sib2, iclass 10, count 2 2006.285.11:57:05.32#ibcon#*mode == 0, iclass 10, count 2 2006.285.11:57:05.32#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.11:57:05.32#ibcon#[25=AT08-03\r\n] 2006.285.11:57:05.32#ibcon#*before write, iclass 10, count 2 2006.285.11:57:05.32#ibcon#enter sib2, iclass 10, count 2 2006.285.11:57:05.32#ibcon#flushed, iclass 10, count 2 2006.285.11:57:05.32#ibcon#about to write, iclass 10, count 2 2006.285.11:57:05.32#ibcon#wrote, iclass 10, count 2 2006.285.11:57:05.32#ibcon#about to read 3, iclass 10, count 2 2006.285.11:57:05.35#ibcon#read 3, iclass 10, count 2 2006.285.11:57:05.35#ibcon#about to read 4, iclass 10, count 2 2006.285.11:57:05.35#ibcon#read 4, iclass 10, count 2 2006.285.11:57:05.35#ibcon#about to read 5, iclass 10, count 2 2006.285.11:57:05.35#ibcon#read 5, iclass 10, count 2 2006.285.11:57:05.35#ibcon#about to read 6, iclass 10, count 2 2006.285.11:57:05.35#ibcon#read 6, iclass 10, count 2 2006.285.11:57:05.35#ibcon#end of sib2, iclass 10, count 2 2006.285.11:57:05.35#ibcon#*after write, iclass 10, count 2 2006.285.11:57:05.35#ibcon#*before return 0, iclass 10, count 2 2006.285.11:57:05.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:57:05.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:57:05.35#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.11:57:05.35#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:05.35#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:57:05.47#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:57:05.47#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:57:05.47#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:57:05.47#ibcon#first serial, iclass 10, count 0 2006.285.11:57:05.47#ibcon#enter sib2, iclass 10, count 0 2006.285.11:57:05.47#ibcon#flushed, iclass 10, count 0 2006.285.11:57:05.47#ibcon#about to write, iclass 10, count 0 2006.285.11:57:05.47#ibcon#wrote, iclass 10, count 0 2006.285.11:57:05.47#ibcon#about to read 3, iclass 10, count 0 2006.285.11:57:05.49#ibcon#read 3, iclass 10, count 0 2006.285.11:57:05.49#ibcon#about to read 4, iclass 10, count 0 2006.285.11:57:05.49#ibcon#read 4, iclass 10, count 0 2006.285.11:57:05.49#ibcon#about to read 5, iclass 10, count 0 2006.285.11:57:05.49#ibcon#read 5, iclass 10, count 0 2006.285.11:57:05.49#ibcon#about to read 6, iclass 10, count 0 2006.285.11:57:05.49#ibcon#read 6, iclass 10, count 0 2006.285.11:57:05.49#ibcon#end of sib2, iclass 10, count 0 2006.285.11:57:05.49#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:57:05.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:57:05.49#ibcon#[25=USB\r\n] 2006.285.11:57:05.49#ibcon#*before write, iclass 10, count 0 2006.285.11:57:05.49#ibcon#enter sib2, iclass 10, count 0 2006.285.11:57:05.49#ibcon#flushed, iclass 10, count 0 2006.285.11:57:05.49#ibcon#about to write, iclass 10, count 0 2006.285.11:57:05.49#ibcon#wrote, iclass 10, count 0 2006.285.11:57:05.49#ibcon#about to read 3, iclass 10, count 0 2006.285.11:57:05.52#ibcon#read 3, iclass 10, count 0 2006.285.11:57:05.52#ibcon#about to read 4, iclass 10, count 0 2006.285.11:57:05.52#ibcon#read 4, iclass 10, count 0 2006.285.11:57:05.52#ibcon#about to read 5, iclass 10, count 0 2006.285.11:57:05.52#ibcon#read 5, iclass 10, count 0 2006.285.11:57:05.52#ibcon#about to read 6, iclass 10, count 0 2006.285.11:57:05.52#ibcon#read 6, iclass 10, count 0 2006.285.11:57:05.52#ibcon#end of sib2, iclass 10, count 0 2006.285.11:57:05.52#ibcon#*after write, iclass 10, count 0 2006.285.11:57:05.52#ibcon#*before return 0, iclass 10, count 0 2006.285.11:57:05.52#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:57:05.52#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:57:05.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:57:05.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:57:05.52$vck44/vblo=1,629.99 2006.285.11:57:05.52#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.11:57:05.52#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.11:57:05.52#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:05.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:57:05.52#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:57:05.52#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:57:05.52#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:57:05.52#ibcon#first serial, iclass 12, count 0 2006.285.11:57:05.52#ibcon#enter sib2, iclass 12, count 0 2006.285.11:57:05.52#ibcon#flushed, iclass 12, count 0 2006.285.11:57:05.52#ibcon#about to write, iclass 12, count 0 2006.285.11:57:05.52#ibcon#wrote, iclass 12, count 0 2006.285.11:57:05.52#ibcon#about to read 3, iclass 12, count 0 2006.285.11:57:05.54#ibcon#read 3, iclass 12, count 0 2006.285.11:57:05.54#ibcon#about to read 4, iclass 12, count 0 2006.285.11:57:05.54#ibcon#read 4, iclass 12, count 0 2006.285.11:57:05.54#ibcon#about to read 5, iclass 12, count 0 2006.285.11:57:05.54#ibcon#read 5, iclass 12, count 0 2006.285.11:57:05.54#ibcon#about to read 6, iclass 12, count 0 2006.285.11:57:05.54#ibcon#read 6, iclass 12, count 0 2006.285.11:57:05.54#ibcon#end of sib2, iclass 12, count 0 2006.285.11:57:05.54#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:57:05.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:57:05.54#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.11:57:05.54#ibcon#*before write, iclass 12, count 0 2006.285.11:57:05.54#ibcon#enter sib2, iclass 12, count 0 2006.285.11:57:05.54#ibcon#flushed, iclass 12, count 0 2006.285.11:57:05.54#ibcon#about to write, iclass 12, count 0 2006.285.11:57:05.54#ibcon#wrote, iclass 12, count 0 2006.285.11:57:05.54#ibcon#about to read 3, iclass 12, count 0 2006.285.11:57:05.58#ibcon#read 3, iclass 12, count 0 2006.285.11:57:05.58#ibcon#about to read 4, iclass 12, count 0 2006.285.11:57:05.58#ibcon#read 4, iclass 12, count 0 2006.285.11:57:05.58#ibcon#about to read 5, iclass 12, count 0 2006.285.11:57:05.58#ibcon#read 5, iclass 12, count 0 2006.285.11:57:05.58#ibcon#about to read 6, iclass 12, count 0 2006.285.11:57:05.58#ibcon#read 6, iclass 12, count 0 2006.285.11:57:05.58#ibcon#end of sib2, iclass 12, count 0 2006.285.11:57:05.58#ibcon#*after write, iclass 12, count 0 2006.285.11:57:05.58#ibcon#*before return 0, iclass 12, count 0 2006.285.11:57:05.58#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:57:05.58#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:57:05.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:57:05.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:57:05.58$vck44/vb=1,4 2006.285.11:57:05.58#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.11:57:05.58#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.11:57:05.58#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:05.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:57:05.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:57:05.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:57:05.58#ibcon#enter wrdev, iclass 14, count 2 2006.285.11:57:05.58#ibcon#first serial, iclass 14, count 2 2006.285.11:57:05.58#ibcon#enter sib2, iclass 14, count 2 2006.285.11:57:05.58#ibcon#flushed, iclass 14, count 2 2006.285.11:57:05.58#ibcon#about to write, iclass 14, count 2 2006.285.11:57:05.58#ibcon#wrote, iclass 14, count 2 2006.285.11:57:05.58#ibcon#about to read 3, iclass 14, count 2 2006.285.11:57:05.60#ibcon#read 3, iclass 14, count 2 2006.285.11:57:05.60#ibcon#about to read 4, iclass 14, count 2 2006.285.11:57:05.60#ibcon#read 4, iclass 14, count 2 2006.285.11:57:05.60#ibcon#about to read 5, iclass 14, count 2 2006.285.11:57:05.60#ibcon#read 5, iclass 14, count 2 2006.285.11:57:05.60#ibcon#about to read 6, iclass 14, count 2 2006.285.11:57:05.60#ibcon#read 6, iclass 14, count 2 2006.285.11:57:05.60#ibcon#end of sib2, iclass 14, count 2 2006.285.11:57:05.60#ibcon#*mode == 0, iclass 14, count 2 2006.285.11:57:05.60#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.11:57:05.60#ibcon#[27=AT01-04\r\n] 2006.285.11:57:05.60#ibcon#*before write, iclass 14, count 2 2006.285.11:57:05.60#ibcon#enter sib2, iclass 14, count 2 2006.285.11:57:05.60#ibcon#flushed, iclass 14, count 2 2006.285.11:57:05.60#ibcon#about to write, iclass 14, count 2 2006.285.11:57:05.60#ibcon#wrote, iclass 14, count 2 2006.285.11:57:05.60#ibcon#about to read 3, iclass 14, count 2 2006.285.11:57:05.63#ibcon#read 3, iclass 14, count 2 2006.285.11:57:05.63#ibcon#about to read 4, iclass 14, count 2 2006.285.11:57:05.63#ibcon#read 4, iclass 14, count 2 2006.285.11:57:05.63#ibcon#about to read 5, iclass 14, count 2 2006.285.11:57:05.63#ibcon#read 5, iclass 14, count 2 2006.285.11:57:05.63#ibcon#about to read 6, iclass 14, count 2 2006.285.11:57:05.63#ibcon#read 6, iclass 14, count 2 2006.285.11:57:05.63#ibcon#end of sib2, iclass 14, count 2 2006.285.11:57:05.63#ibcon#*after write, iclass 14, count 2 2006.285.11:57:05.63#ibcon#*before return 0, iclass 14, count 2 2006.285.11:57:05.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:57:05.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.11:57:05.63#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.11:57:05.63#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:05.63#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:57:05.75#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:57:05.75#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:57:05.75#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:57:05.75#ibcon#first serial, iclass 14, count 0 2006.285.11:57:05.75#ibcon#enter sib2, iclass 14, count 0 2006.285.11:57:05.75#ibcon#flushed, iclass 14, count 0 2006.285.11:57:05.75#ibcon#about to write, iclass 14, count 0 2006.285.11:57:05.75#ibcon#wrote, iclass 14, count 0 2006.285.11:57:05.75#ibcon#about to read 3, iclass 14, count 0 2006.285.11:57:05.77#ibcon#read 3, iclass 14, count 0 2006.285.11:57:05.77#ibcon#about to read 4, iclass 14, count 0 2006.285.11:57:05.77#ibcon#read 4, iclass 14, count 0 2006.285.11:57:05.77#ibcon#about to read 5, iclass 14, count 0 2006.285.11:57:05.77#ibcon#read 5, iclass 14, count 0 2006.285.11:57:05.77#ibcon#about to read 6, iclass 14, count 0 2006.285.11:57:05.77#ibcon#read 6, iclass 14, count 0 2006.285.11:57:05.77#ibcon#end of sib2, iclass 14, count 0 2006.285.11:57:05.77#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:57:05.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:57:05.77#ibcon#[27=USB\r\n] 2006.285.11:57:05.77#ibcon#*before write, iclass 14, count 0 2006.285.11:57:05.77#ibcon#enter sib2, iclass 14, count 0 2006.285.11:57:05.77#ibcon#flushed, iclass 14, count 0 2006.285.11:57:05.77#ibcon#about to write, iclass 14, count 0 2006.285.11:57:05.77#ibcon#wrote, iclass 14, count 0 2006.285.11:57:05.77#ibcon#about to read 3, iclass 14, count 0 2006.285.11:57:05.80#ibcon#read 3, iclass 14, count 0 2006.285.11:57:05.80#ibcon#about to read 4, iclass 14, count 0 2006.285.11:57:05.80#ibcon#read 4, iclass 14, count 0 2006.285.11:57:05.80#ibcon#about to read 5, iclass 14, count 0 2006.285.11:57:05.80#ibcon#read 5, iclass 14, count 0 2006.285.11:57:05.80#ibcon#about to read 6, iclass 14, count 0 2006.285.11:57:05.80#ibcon#read 6, iclass 14, count 0 2006.285.11:57:05.80#ibcon#end of sib2, iclass 14, count 0 2006.285.11:57:05.80#ibcon#*after write, iclass 14, count 0 2006.285.11:57:05.80#ibcon#*before return 0, iclass 14, count 0 2006.285.11:57:05.80#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:57:05.80#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.11:57:05.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:57:05.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:57:05.80$vck44/vblo=2,634.99 2006.285.11:57:05.80#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.11:57:05.80#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.11:57:05.80#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:05.80#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:57:05.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:57:05.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:57:05.80#ibcon#enter wrdev, iclass 16, count 0 2006.285.11:57:05.80#ibcon#first serial, iclass 16, count 0 2006.285.11:57:05.80#ibcon#enter sib2, iclass 16, count 0 2006.285.11:57:05.80#ibcon#flushed, iclass 16, count 0 2006.285.11:57:05.80#ibcon#about to write, iclass 16, count 0 2006.285.11:57:05.80#ibcon#wrote, iclass 16, count 0 2006.285.11:57:05.80#ibcon#about to read 3, iclass 16, count 0 2006.285.11:57:05.82#ibcon#read 3, iclass 16, count 0 2006.285.11:57:05.82#ibcon#about to read 4, iclass 16, count 0 2006.285.11:57:05.82#ibcon#read 4, iclass 16, count 0 2006.285.11:57:05.82#ibcon#about to read 5, iclass 16, count 0 2006.285.11:57:05.82#ibcon#read 5, iclass 16, count 0 2006.285.11:57:05.82#ibcon#about to read 6, iclass 16, count 0 2006.285.11:57:05.82#ibcon#read 6, iclass 16, count 0 2006.285.11:57:05.82#ibcon#end of sib2, iclass 16, count 0 2006.285.11:57:05.82#ibcon#*mode == 0, iclass 16, count 0 2006.285.11:57:05.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.11:57:05.82#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.11:57:05.82#ibcon#*before write, iclass 16, count 0 2006.285.11:57:05.82#ibcon#enter sib2, iclass 16, count 0 2006.285.11:57:05.82#ibcon#flushed, iclass 16, count 0 2006.285.11:57:05.82#ibcon#about to write, iclass 16, count 0 2006.285.11:57:05.82#ibcon#wrote, iclass 16, count 0 2006.285.11:57:05.82#ibcon#about to read 3, iclass 16, count 0 2006.285.11:57:05.86#ibcon#read 3, iclass 16, count 0 2006.285.11:57:05.86#ibcon#about to read 4, iclass 16, count 0 2006.285.11:57:05.86#ibcon#read 4, iclass 16, count 0 2006.285.11:57:05.86#ibcon#about to read 5, iclass 16, count 0 2006.285.11:57:05.86#ibcon#read 5, iclass 16, count 0 2006.285.11:57:05.86#ibcon#about to read 6, iclass 16, count 0 2006.285.11:57:05.86#ibcon#read 6, iclass 16, count 0 2006.285.11:57:05.86#ibcon#end of sib2, iclass 16, count 0 2006.285.11:57:05.86#ibcon#*after write, iclass 16, count 0 2006.285.11:57:05.86#ibcon#*before return 0, iclass 16, count 0 2006.285.11:57:05.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:57:05.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.11:57:05.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.11:57:05.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.11:57:05.86$vck44/vb=2,5 2006.285.11:57:05.86#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.11:57:05.86#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.11:57:05.86#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:05.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:57:05.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:57:05.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:57:05.92#ibcon#enter wrdev, iclass 18, count 2 2006.285.11:57:05.92#ibcon#first serial, iclass 18, count 2 2006.285.11:57:05.92#ibcon#enter sib2, iclass 18, count 2 2006.285.11:57:05.92#ibcon#flushed, iclass 18, count 2 2006.285.11:57:05.92#ibcon#about to write, iclass 18, count 2 2006.285.11:57:05.92#ibcon#wrote, iclass 18, count 2 2006.285.11:57:05.92#ibcon#about to read 3, iclass 18, count 2 2006.285.11:57:05.94#ibcon#read 3, iclass 18, count 2 2006.285.11:57:05.94#ibcon#about to read 4, iclass 18, count 2 2006.285.11:57:05.94#ibcon#read 4, iclass 18, count 2 2006.285.11:57:05.94#ibcon#about to read 5, iclass 18, count 2 2006.285.11:57:05.94#ibcon#read 5, iclass 18, count 2 2006.285.11:57:05.94#ibcon#about to read 6, iclass 18, count 2 2006.285.11:57:05.94#ibcon#read 6, iclass 18, count 2 2006.285.11:57:05.94#ibcon#end of sib2, iclass 18, count 2 2006.285.11:57:05.94#ibcon#*mode == 0, iclass 18, count 2 2006.285.11:57:05.94#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.11:57:05.94#ibcon#[27=AT02-05\r\n] 2006.285.11:57:05.94#ibcon#*before write, iclass 18, count 2 2006.285.11:57:05.94#ibcon#enter sib2, iclass 18, count 2 2006.285.11:57:05.94#ibcon#flushed, iclass 18, count 2 2006.285.11:57:05.94#ibcon#about to write, iclass 18, count 2 2006.285.11:57:05.94#ibcon#wrote, iclass 18, count 2 2006.285.11:57:05.94#ibcon#about to read 3, iclass 18, count 2 2006.285.11:57:05.97#ibcon#read 3, iclass 18, count 2 2006.285.11:57:05.97#ibcon#about to read 4, iclass 18, count 2 2006.285.11:57:05.97#ibcon#read 4, iclass 18, count 2 2006.285.11:57:05.97#ibcon#about to read 5, iclass 18, count 2 2006.285.11:57:05.97#ibcon#read 5, iclass 18, count 2 2006.285.11:57:05.97#ibcon#about to read 6, iclass 18, count 2 2006.285.11:57:05.97#ibcon#read 6, iclass 18, count 2 2006.285.11:57:05.97#ibcon#end of sib2, iclass 18, count 2 2006.285.11:57:05.97#ibcon#*after write, iclass 18, count 2 2006.285.11:57:05.97#ibcon#*before return 0, iclass 18, count 2 2006.285.11:57:05.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:57:05.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.11:57:05.97#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.11:57:05.97#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:05.97#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:57:06.09#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:57:06.09#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:57:06.09#ibcon#enter wrdev, iclass 18, count 0 2006.285.11:57:06.09#ibcon#first serial, iclass 18, count 0 2006.285.11:57:06.09#ibcon#enter sib2, iclass 18, count 0 2006.285.11:57:06.09#ibcon#flushed, iclass 18, count 0 2006.285.11:57:06.09#ibcon#about to write, iclass 18, count 0 2006.285.11:57:06.09#ibcon#wrote, iclass 18, count 0 2006.285.11:57:06.09#ibcon#about to read 3, iclass 18, count 0 2006.285.11:57:06.11#ibcon#read 3, iclass 18, count 0 2006.285.11:57:06.11#ibcon#about to read 4, iclass 18, count 0 2006.285.11:57:06.11#ibcon#read 4, iclass 18, count 0 2006.285.11:57:06.11#ibcon#about to read 5, iclass 18, count 0 2006.285.11:57:06.11#ibcon#read 5, iclass 18, count 0 2006.285.11:57:06.11#ibcon#about to read 6, iclass 18, count 0 2006.285.11:57:06.11#ibcon#read 6, iclass 18, count 0 2006.285.11:57:06.11#ibcon#end of sib2, iclass 18, count 0 2006.285.11:57:06.11#ibcon#*mode == 0, iclass 18, count 0 2006.285.11:57:06.11#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.11:57:06.11#ibcon#[27=USB\r\n] 2006.285.11:57:06.11#ibcon#*before write, iclass 18, count 0 2006.285.11:57:06.11#ibcon#enter sib2, iclass 18, count 0 2006.285.11:57:06.11#ibcon#flushed, iclass 18, count 0 2006.285.11:57:06.11#ibcon#about to write, iclass 18, count 0 2006.285.11:57:06.11#ibcon#wrote, iclass 18, count 0 2006.285.11:57:06.11#ibcon#about to read 3, iclass 18, count 0 2006.285.11:57:06.14#ibcon#read 3, iclass 18, count 0 2006.285.11:57:06.14#ibcon#about to read 4, iclass 18, count 0 2006.285.11:57:06.14#ibcon#read 4, iclass 18, count 0 2006.285.11:57:06.14#ibcon#about to read 5, iclass 18, count 0 2006.285.11:57:06.14#ibcon#read 5, iclass 18, count 0 2006.285.11:57:06.14#ibcon#about to read 6, iclass 18, count 0 2006.285.11:57:06.14#ibcon#read 6, iclass 18, count 0 2006.285.11:57:06.14#ibcon#end of sib2, iclass 18, count 0 2006.285.11:57:06.14#ibcon#*after write, iclass 18, count 0 2006.285.11:57:06.14#ibcon#*before return 0, iclass 18, count 0 2006.285.11:57:06.14#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:57:06.14#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.11:57:06.14#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.11:57:06.14#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.11:57:06.14$vck44/vblo=3,649.99 2006.285.11:57:06.14#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.11:57:06.14#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.11:57:06.14#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:06.14#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:57:06.14#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:57:06.14#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:57:06.14#ibcon#enter wrdev, iclass 20, count 0 2006.285.11:57:06.14#ibcon#first serial, iclass 20, count 0 2006.285.11:57:06.14#ibcon#enter sib2, iclass 20, count 0 2006.285.11:57:06.14#ibcon#flushed, iclass 20, count 0 2006.285.11:57:06.14#ibcon#about to write, iclass 20, count 0 2006.285.11:57:06.14#ibcon#wrote, iclass 20, count 0 2006.285.11:57:06.14#ibcon#about to read 3, iclass 20, count 0 2006.285.11:57:06.16#ibcon#read 3, iclass 20, count 0 2006.285.11:57:06.16#ibcon#about to read 4, iclass 20, count 0 2006.285.11:57:06.16#ibcon#read 4, iclass 20, count 0 2006.285.11:57:06.16#ibcon#about to read 5, iclass 20, count 0 2006.285.11:57:06.16#ibcon#read 5, iclass 20, count 0 2006.285.11:57:06.16#ibcon#about to read 6, iclass 20, count 0 2006.285.11:57:06.16#ibcon#read 6, iclass 20, count 0 2006.285.11:57:06.16#ibcon#end of sib2, iclass 20, count 0 2006.285.11:57:06.16#ibcon#*mode == 0, iclass 20, count 0 2006.285.11:57:06.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.11:57:06.16#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.11:57:06.16#ibcon#*before write, iclass 20, count 0 2006.285.11:57:06.16#ibcon#enter sib2, iclass 20, count 0 2006.285.11:57:06.16#ibcon#flushed, iclass 20, count 0 2006.285.11:57:06.16#ibcon#about to write, iclass 20, count 0 2006.285.11:57:06.16#ibcon#wrote, iclass 20, count 0 2006.285.11:57:06.16#ibcon#about to read 3, iclass 20, count 0 2006.285.11:57:06.20#ibcon#read 3, iclass 20, count 0 2006.285.11:57:06.20#ibcon#about to read 4, iclass 20, count 0 2006.285.11:57:06.20#ibcon#read 4, iclass 20, count 0 2006.285.11:57:06.20#ibcon#about to read 5, iclass 20, count 0 2006.285.11:57:06.20#ibcon#read 5, iclass 20, count 0 2006.285.11:57:06.20#ibcon#about to read 6, iclass 20, count 0 2006.285.11:57:06.20#ibcon#read 6, iclass 20, count 0 2006.285.11:57:06.20#ibcon#end of sib2, iclass 20, count 0 2006.285.11:57:06.20#ibcon#*after write, iclass 20, count 0 2006.285.11:57:06.20#ibcon#*before return 0, iclass 20, count 0 2006.285.11:57:06.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:57:06.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.11:57:06.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.11:57:06.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.11:57:06.20$vck44/vb=3,4 2006.285.11:57:06.20#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.11:57:06.20#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.11:57:06.20#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:06.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:57:06.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:57:06.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:57:06.26#ibcon#enter wrdev, iclass 22, count 2 2006.285.11:57:06.26#ibcon#first serial, iclass 22, count 2 2006.285.11:57:06.26#ibcon#enter sib2, iclass 22, count 2 2006.285.11:57:06.26#ibcon#flushed, iclass 22, count 2 2006.285.11:57:06.26#ibcon#about to write, iclass 22, count 2 2006.285.11:57:06.26#ibcon#wrote, iclass 22, count 2 2006.285.11:57:06.26#ibcon#about to read 3, iclass 22, count 2 2006.285.11:57:06.28#ibcon#read 3, iclass 22, count 2 2006.285.11:57:06.28#ibcon#about to read 4, iclass 22, count 2 2006.285.11:57:06.28#ibcon#read 4, iclass 22, count 2 2006.285.11:57:06.28#ibcon#about to read 5, iclass 22, count 2 2006.285.11:57:06.28#ibcon#read 5, iclass 22, count 2 2006.285.11:57:06.28#ibcon#about to read 6, iclass 22, count 2 2006.285.11:57:06.28#ibcon#read 6, iclass 22, count 2 2006.285.11:57:06.28#ibcon#end of sib2, iclass 22, count 2 2006.285.11:57:06.28#ibcon#*mode == 0, iclass 22, count 2 2006.285.11:57:06.28#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.11:57:06.28#ibcon#[27=AT03-04\r\n] 2006.285.11:57:06.28#ibcon#*before write, iclass 22, count 2 2006.285.11:57:06.28#ibcon#enter sib2, iclass 22, count 2 2006.285.11:57:06.28#ibcon#flushed, iclass 22, count 2 2006.285.11:57:06.28#ibcon#about to write, iclass 22, count 2 2006.285.11:57:06.28#ibcon#wrote, iclass 22, count 2 2006.285.11:57:06.28#ibcon#about to read 3, iclass 22, count 2 2006.285.11:57:06.31#ibcon#read 3, iclass 22, count 2 2006.285.11:57:06.31#ibcon#about to read 4, iclass 22, count 2 2006.285.11:57:06.31#ibcon#read 4, iclass 22, count 2 2006.285.11:57:06.31#ibcon#about to read 5, iclass 22, count 2 2006.285.11:57:06.31#ibcon#read 5, iclass 22, count 2 2006.285.11:57:06.31#ibcon#about to read 6, iclass 22, count 2 2006.285.11:57:06.31#ibcon#read 6, iclass 22, count 2 2006.285.11:57:06.31#ibcon#end of sib2, iclass 22, count 2 2006.285.11:57:06.31#ibcon#*after write, iclass 22, count 2 2006.285.11:57:06.31#ibcon#*before return 0, iclass 22, count 2 2006.285.11:57:06.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:57:06.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.11:57:06.31#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.11:57:06.31#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:06.31#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:57:06.43#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:57:06.43#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:57:06.43#ibcon#enter wrdev, iclass 22, count 0 2006.285.11:57:06.43#ibcon#first serial, iclass 22, count 0 2006.285.11:57:06.43#ibcon#enter sib2, iclass 22, count 0 2006.285.11:57:06.43#ibcon#flushed, iclass 22, count 0 2006.285.11:57:06.43#ibcon#about to write, iclass 22, count 0 2006.285.11:57:06.43#ibcon#wrote, iclass 22, count 0 2006.285.11:57:06.43#ibcon#about to read 3, iclass 22, count 0 2006.285.11:57:06.45#ibcon#read 3, iclass 22, count 0 2006.285.11:57:06.45#ibcon#about to read 4, iclass 22, count 0 2006.285.11:57:06.45#ibcon#read 4, iclass 22, count 0 2006.285.11:57:06.45#ibcon#about to read 5, iclass 22, count 0 2006.285.11:57:06.45#ibcon#read 5, iclass 22, count 0 2006.285.11:57:06.45#ibcon#about to read 6, iclass 22, count 0 2006.285.11:57:06.45#ibcon#read 6, iclass 22, count 0 2006.285.11:57:06.45#ibcon#end of sib2, iclass 22, count 0 2006.285.11:57:06.45#ibcon#*mode == 0, iclass 22, count 0 2006.285.11:57:06.45#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.11:57:06.45#ibcon#[27=USB\r\n] 2006.285.11:57:06.45#ibcon#*before write, iclass 22, count 0 2006.285.11:57:06.45#ibcon#enter sib2, iclass 22, count 0 2006.285.11:57:06.45#ibcon#flushed, iclass 22, count 0 2006.285.11:57:06.45#ibcon#about to write, iclass 22, count 0 2006.285.11:57:06.45#ibcon#wrote, iclass 22, count 0 2006.285.11:57:06.45#ibcon#about to read 3, iclass 22, count 0 2006.285.11:57:06.48#ibcon#read 3, iclass 22, count 0 2006.285.11:57:06.48#ibcon#about to read 4, iclass 22, count 0 2006.285.11:57:06.48#ibcon#read 4, iclass 22, count 0 2006.285.11:57:06.48#ibcon#about to read 5, iclass 22, count 0 2006.285.11:57:06.48#ibcon#read 5, iclass 22, count 0 2006.285.11:57:06.48#ibcon#about to read 6, iclass 22, count 0 2006.285.11:57:06.48#ibcon#read 6, iclass 22, count 0 2006.285.11:57:06.48#ibcon#end of sib2, iclass 22, count 0 2006.285.11:57:06.48#ibcon#*after write, iclass 22, count 0 2006.285.11:57:06.48#ibcon#*before return 0, iclass 22, count 0 2006.285.11:57:06.48#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:57:06.48#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.11:57:06.48#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.11:57:06.48#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.11:57:06.48$vck44/vblo=4,679.99 2006.285.11:57:06.48#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.11:57:06.48#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.11:57:06.48#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:06.48#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:57:06.48#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:57:06.48#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:57:06.48#ibcon#enter wrdev, iclass 24, count 0 2006.285.11:57:06.48#ibcon#first serial, iclass 24, count 0 2006.285.11:57:06.48#ibcon#enter sib2, iclass 24, count 0 2006.285.11:57:06.48#ibcon#flushed, iclass 24, count 0 2006.285.11:57:06.48#ibcon#about to write, iclass 24, count 0 2006.285.11:57:06.48#ibcon#wrote, iclass 24, count 0 2006.285.11:57:06.48#ibcon#about to read 3, iclass 24, count 0 2006.285.11:57:06.50#ibcon#read 3, iclass 24, count 0 2006.285.11:57:06.50#ibcon#about to read 4, iclass 24, count 0 2006.285.11:57:06.50#ibcon#read 4, iclass 24, count 0 2006.285.11:57:06.50#ibcon#about to read 5, iclass 24, count 0 2006.285.11:57:06.50#ibcon#read 5, iclass 24, count 0 2006.285.11:57:06.50#ibcon#about to read 6, iclass 24, count 0 2006.285.11:57:06.50#ibcon#read 6, iclass 24, count 0 2006.285.11:57:06.50#ibcon#end of sib2, iclass 24, count 0 2006.285.11:57:06.50#ibcon#*mode == 0, iclass 24, count 0 2006.285.11:57:06.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.11:57:06.50#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.11:57:06.50#ibcon#*before write, iclass 24, count 0 2006.285.11:57:06.50#ibcon#enter sib2, iclass 24, count 0 2006.285.11:57:06.50#ibcon#flushed, iclass 24, count 0 2006.285.11:57:06.50#ibcon#about to write, iclass 24, count 0 2006.285.11:57:06.50#ibcon#wrote, iclass 24, count 0 2006.285.11:57:06.50#ibcon#about to read 3, iclass 24, count 0 2006.285.11:57:06.54#ibcon#read 3, iclass 24, count 0 2006.285.11:57:06.54#ibcon#about to read 4, iclass 24, count 0 2006.285.11:57:06.54#ibcon#read 4, iclass 24, count 0 2006.285.11:57:06.54#ibcon#about to read 5, iclass 24, count 0 2006.285.11:57:06.54#ibcon#read 5, iclass 24, count 0 2006.285.11:57:06.54#ibcon#about to read 6, iclass 24, count 0 2006.285.11:57:06.54#ibcon#read 6, iclass 24, count 0 2006.285.11:57:06.54#ibcon#end of sib2, iclass 24, count 0 2006.285.11:57:06.54#ibcon#*after write, iclass 24, count 0 2006.285.11:57:06.54#ibcon#*before return 0, iclass 24, count 0 2006.285.11:57:06.54#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:57:06.54#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.11:57:06.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.11:57:06.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.11:57:06.54$vck44/vb=4,5 2006.285.11:57:06.54#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.11:57:06.54#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.11:57:06.54#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:06.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:57:06.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:57:06.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:57:06.60#ibcon#enter wrdev, iclass 26, count 2 2006.285.11:57:06.60#ibcon#first serial, iclass 26, count 2 2006.285.11:57:06.60#ibcon#enter sib2, iclass 26, count 2 2006.285.11:57:06.60#ibcon#flushed, iclass 26, count 2 2006.285.11:57:06.60#ibcon#about to write, iclass 26, count 2 2006.285.11:57:06.60#ibcon#wrote, iclass 26, count 2 2006.285.11:57:06.60#ibcon#about to read 3, iclass 26, count 2 2006.285.11:57:06.62#ibcon#read 3, iclass 26, count 2 2006.285.11:57:06.62#ibcon#about to read 4, iclass 26, count 2 2006.285.11:57:06.62#ibcon#read 4, iclass 26, count 2 2006.285.11:57:06.62#ibcon#about to read 5, iclass 26, count 2 2006.285.11:57:06.62#ibcon#read 5, iclass 26, count 2 2006.285.11:57:06.62#ibcon#about to read 6, iclass 26, count 2 2006.285.11:57:06.62#ibcon#read 6, iclass 26, count 2 2006.285.11:57:06.62#ibcon#end of sib2, iclass 26, count 2 2006.285.11:57:06.62#ibcon#*mode == 0, iclass 26, count 2 2006.285.11:57:06.62#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.11:57:06.62#ibcon#[27=AT04-05\r\n] 2006.285.11:57:06.62#ibcon#*before write, iclass 26, count 2 2006.285.11:57:06.62#ibcon#enter sib2, iclass 26, count 2 2006.285.11:57:06.62#ibcon#flushed, iclass 26, count 2 2006.285.11:57:06.62#ibcon#about to write, iclass 26, count 2 2006.285.11:57:06.62#ibcon#wrote, iclass 26, count 2 2006.285.11:57:06.62#ibcon#about to read 3, iclass 26, count 2 2006.285.11:57:06.65#ibcon#read 3, iclass 26, count 2 2006.285.11:57:06.65#ibcon#about to read 4, iclass 26, count 2 2006.285.11:57:06.65#ibcon#read 4, iclass 26, count 2 2006.285.11:57:06.65#ibcon#about to read 5, iclass 26, count 2 2006.285.11:57:06.65#ibcon#read 5, iclass 26, count 2 2006.285.11:57:06.65#ibcon#about to read 6, iclass 26, count 2 2006.285.11:57:06.65#ibcon#read 6, iclass 26, count 2 2006.285.11:57:06.65#ibcon#end of sib2, iclass 26, count 2 2006.285.11:57:06.65#ibcon#*after write, iclass 26, count 2 2006.285.11:57:06.65#ibcon#*before return 0, iclass 26, count 2 2006.285.11:57:06.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:57:06.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.11:57:06.65#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.11:57:06.65#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:06.65#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:57:06.77#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:57:06.77#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:57:06.77#ibcon#enter wrdev, iclass 26, count 0 2006.285.11:57:06.77#ibcon#first serial, iclass 26, count 0 2006.285.11:57:06.77#ibcon#enter sib2, iclass 26, count 0 2006.285.11:57:06.77#ibcon#flushed, iclass 26, count 0 2006.285.11:57:06.77#ibcon#about to write, iclass 26, count 0 2006.285.11:57:06.77#ibcon#wrote, iclass 26, count 0 2006.285.11:57:06.77#ibcon#about to read 3, iclass 26, count 0 2006.285.11:57:06.79#ibcon#read 3, iclass 26, count 0 2006.285.11:57:06.79#ibcon#about to read 4, iclass 26, count 0 2006.285.11:57:06.79#ibcon#read 4, iclass 26, count 0 2006.285.11:57:06.79#ibcon#about to read 5, iclass 26, count 0 2006.285.11:57:06.79#ibcon#read 5, iclass 26, count 0 2006.285.11:57:06.79#ibcon#about to read 6, iclass 26, count 0 2006.285.11:57:06.79#ibcon#read 6, iclass 26, count 0 2006.285.11:57:06.79#ibcon#end of sib2, iclass 26, count 0 2006.285.11:57:06.79#ibcon#*mode == 0, iclass 26, count 0 2006.285.11:57:06.79#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.11:57:06.79#ibcon#[27=USB\r\n] 2006.285.11:57:06.79#ibcon#*before write, iclass 26, count 0 2006.285.11:57:06.79#ibcon#enter sib2, iclass 26, count 0 2006.285.11:57:06.79#ibcon#flushed, iclass 26, count 0 2006.285.11:57:06.79#ibcon#about to write, iclass 26, count 0 2006.285.11:57:06.79#ibcon#wrote, iclass 26, count 0 2006.285.11:57:06.79#ibcon#about to read 3, iclass 26, count 0 2006.285.11:57:06.82#ibcon#read 3, iclass 26, count 0 2006.285.11:57:06.82#ibcon#about to read 4, iclass 26, count 0 2006.285.11:57:06.82#ibcon#read 4, iclass 26, count 0 2006.285.11:57:06.82#ibcon#about to read 5, iclass 26, count 0 2006.285.11:57:06.82#ibcon#read 5, iclass 26, count 0 2006.285.11:57:06.82#ibcon#about to read 6, iclass 26, count 0 2006.285.11:57:06.82#ibcon#read 6, iclass 26, count 0 2006.285.11:57:06.82#ibcon#end of sib2, iclass 26, count 0 2006.285.11:57:06.82#ibcon#*after write, iclass 26, count 0 2006.285.11:57:06.82#ibcon#*before return 0, iclass 26, count 0 2006.285.11:57:06.82#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:57:06.82#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.11:57:06.82#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.11:57:06.82#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.11:57:06.82$vck44/vblo=5,709.99 2006.285.11:57:06.82#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.11:57:06.82#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.11:57:06.82#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:06.82#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:57:06.82#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:57:06.82#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:57:06.82#ibcon#enter wrdev, iclass 28, count 0 2006.285.11:57:06.82#ibcon#first serial, iclass 28, count 0 2006.285.11:57:06.82#ibcon#enter sib2, iclass 28, count 0 2006.285.11:57:06.82#ibcon#flushed, iclass 28, count 0 2006.285.11:57:06.82#ibcon#about to write, iclass 28, count 0 2006.285.11:57:06.82#ibcon#wrote, iclass 28, count 0 2006.285.11:57:06.82#ibcon#about to read 3, iclass 28, count 0 2006.285.11:57:06.84#ibcon#read 3, iclass 28, count 0 2006.285.11:57:06.84#ibcon#about to read 4, iclass 28, count 0 2006.285.11:57:06.84#ibcon#read 4, iclass 28, count 0 2006.285.11:57:06.84#ibcon#about to read 5, iclass 28, count 0 2006.285.11:57:06.84#ibcon#read 5, iclass 28, count 0 2006.285.11:57:06.84#ibcon#about to read 6, iclass 28, count 0 2006.285.11:57:06.84#ibcon#read 6, iclass 28, count 0 2006.285.11:57:06.84#ibcon#end of sib2, iclass 28, count 0 2006.285.11:57:06.84#ibcon#*mode == 0, iclass 28, count 0 2006.285.11:57:06.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.11:57:06.84#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.11:57:06.84#ibcon#*before write, iclass 28, count 0 2006.285.11:57:06.84#ibcon#enter sib2, iclass 28, count 0 2006.285.11:57:06.84#ibcon#flushed, iclass 28, count 0 2006.285.11:57:06.84#ibcon#about to write, iclass 28, count 0 2006.285.11:57:06.84#ibcon#wrote, iclass 28, count 0 2006.285.11:57:06.84#ibcon#about to read 3, iclass 28, count 0 2006.285.11:57:06.88#ibcon#read 3, iclass 28, count 0 2006.285.11:57:06.88#ibcon#about to read 4, iclass 28, count 0 2006.285.11:57:06.88#ibcon#read 4, iclass 28, count 0 2006.285.11:57:06.88#ibcon#about to read 5, iclass 28, count 0 2006.285.11:57:06.88#ibcon#read 5, iclass 28, count 0 2006.285.11:57:06.88#ibcon#about to read 6, iclass 28, count 0 2006.285.11:57:06.88#ibcon#read 6, iclass 28, count 0 2006.285.11:57:06.88#ibcon#end of sib2, iclass 28, count 0 2006.285.11:57:06.88#ibcon#*after write, iclass 28, count 0 2006.285.11:57:06.88#ibcon#*before return 0, iclass 28, count 0 2006.285.11:57:06.88#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:57:06.88#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.11:57:06.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.11:57:06.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.11:57:06.88$vck44/vb=5,4 2006.285.11:57:06.88#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.11:57:06.88#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.11:57:06.88#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:06.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:57:06.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:57:06.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:57:06.94#ibcon#enter wrdev, iclass 30, count 2 2006.285.11:57:06.94#ibcon#first serial, iclass 30, count 2 2006.285.11:57:06.94#ibcon#enter sib2, iclass 30, count 2 2006.285.11:57:06.94#ibcon#flushed, iclass 30, count 2 2006.285.11:57:06.94#ibcon#about to write, iclass 30, count 2 2006.285.11:57:06.94#ibcon#wrote, iclass 30, count 2 2006.285.11:57:06.94#ibcon#about to read 3, iclass 30, count 2 2006.285.11:57:06.96#ibcon#read 3, iclass 30, count 2 2006.285.11:57:06.96#ibcon#about to read 4, iclass 30, count 2 2006.285.11:57:06.96#ibcon#read 4, iclass 30, count 2 2006.285.11:57:06.96#ibcon#about to read 5, iclass 30, count 2 2006.285.11:57:06.96#ibcon#read 5, iclass 30, count 2 2006.285.11:57:06.96#ibcon#about to read 6, iclass 30, count 2 2006.285.11:57:06.96#ibcon#read 6, iclass 30, count 2 2006.285.11:57:06.96#ibcon#end of sib2, iclass 30, count 2 2006.285.11:57:06.96#ibcon#*mode == 0, iclass 30, count 2 2006.285.11:57:06.96#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.11:57:06.96#ibcon#[27=AT05-04\r\n] 2006.285.11:57:06.96#ibcon#*before write, iclass 30, count 2 2006.285.11:57:06.96#ibcon#enter sib2, iclass 30, count 2 2006.285.11:57:06.96#ibcon#flushed, iclass 30, count 2 2006.285.11:57:06.96#ibcon#about to write, iclass 30, count 2 2006.285.11:57:06.96#ibcon#wrote, iclass 30, count 2 2006.285.11:57:06.96#ibcon#about to read 3, iclass 30, count 2 2006.285.11:57:06.99#ibcon#read 3, iclass 30, count 2 2006.285.11:57:06.99#ibcon#about to read 4, iclass 30, count 2 2006.285.11:57:06.99#ibcon#read 4, iclass 30, count 2 2006.285.11:57:06.99#ibcon#about to read 5, iclass 30, count 2 2006.285.11:57:06.99#ibcon#read 5, iclass 30, count 2 2006.285.11:57:06.99#ibcon#about to read 6, iclass 30, count 2 2006.285.11:57:06.99#ibcon#read 6, iclass 30, count 2 2006.285.11:57:06.99#ibcon#end of sib2, iclass 30, count 2 2006.285.11:57:06.99#ibcon#*after write, iclass 30, count 2 2006.285.11:57:06.99#ibcon#*before return 0, iclass 30, count 2 2006.285.11:57:06.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:57:06.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.11:57:06.99#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.11:57:06.99#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:06.99#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:57:07.11#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:57:07.11#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:57:07.11#ibcon#enter wrdev, iclass 30, count 0 2006.285.11:57:07.11#ibcon#first serial, iclass 30, count 0 2006.285.11:57:07.11#ibcon#enter sib2, iclass 30, count 0 2006.285.11:57:07.11#ibcon#flushed, iclass 30, count 0 2006.285.11:57:07.11#ibcon#about to write, iclass 30, count 0 2006.285.11:57:07.11#ibcon#wrote, iclass 30, count 0 2006.285.11:57:07.11#ibcon#about to read 3, iclass 30, count 0 2006.285.11:57:07.13#ibcon#read 3, iclass 30, count 0 2006.285.11:57:07.13#ibcon#about to read 4, iclass 30, count 0 2006.285.11:57:07.13#ibcon#read 4, iclass 30, count 0 2006.285.11:57:07.13#ibcon#about to read 5, iclass 30, count 0 2006.285.11:57:07.13#ibcon#read 5, iclass 30, count 0 2006.285.11:57:07.13#ibcon#about to read 6, iclass 30, count 0 2006.285.11:57:07.13#ibcon#read 6, iclass 30, count 0 2006.285.11:57:07.13#ibcon#end of sib2, iclass 30, count 0 2006.285.11:57:07.13#ibcon#*mode == 0, iclass 30, count 0 2006.285.11:57:07.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.11:57:07.13#ibcon#[27=USB\r\n] 2006.285.11:57:07.13#ibcon#*before write, iclass 30, count 0 2006.285.11:57:07.13#ibcon#enter sib2, iclass 30, count 0 2006.285.11:57:07.13#ibcon#flushed, iclass 30, count 0 2006.285.11:57:07.13#ibcon#about to write, iclass 30, count 0 2006.285.11:57:07.13#ibcon#wrote, iclass 30, count 0 2006.285.11:57:07.13#ibcon#about to read 3, iclass 30, count 0 2006.285.11:57:07.16#ibcon#read 3, iclass 30, count 0 2006.285.11:57:07.16#ibcon#about to read 4, iclass 30, count 0 2006.285.11:57:07.16#ibcon#read 4, iclass 30, count 0 2006.285.11:57:07.16#ibcon#about to read 5, iclass 30, count 0 2006.285.11:57:07.16#ibcon#read 5, iclass 30, count 0 2006.285.11:57:07.16#ibcon#about to read 6, iclass 30, count 0 2006.285.11:57:07.16#ibcon#read 6, iclass 30, count 0 2006.285.11:57:07.16#ibcon#end of sib2, iclass 30, count 0 2006.285.11:57:07.16#ibcon#*after write, iclass 30, count 0 2006.285.11:57:07.16#ibcon#*before return 0, iclass 30, count 0 2006.285.11:57:07.16#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:57:07.16#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.11:57:07.16#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.11:57:07.16#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.11:57:07.16$vck44/vblo=6,719.99 2006.285.11:57:07.16#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.11:57:07.16#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.11:57:07.16#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:07.16#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:57:07.16#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:57:07.16#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:57:07.16#ibcon#enter wrdev, iclass 32, count 0 2006.285.11:57:07.16#ibcon#first serial, iclass 32, count 0 2006.285.11:57:07.16#ibcon#enter sib2, iclass 32, count 0 2006.285.11:57:07.16#ibcon#flushed, iclass 32, count 0 2006.285.11:57:07.16#ibcon#about to write, iclass 32, count 0 2006.285.11:57:07.16#ibcon#wrote, iclass 32, count 0 2006.285.11:57:07.16#ibcon#about to read 3, iclass 32, count 0 2006.285.11:57:07.18#ibcon#read 3, iclass 32, count 0 2006.285.11:57:07.18#ibcon#about to read 4, iclass 32, count 0 2006.285.11:57:07.18#ibcon#read 4, iclass 32, count 0 2006.285.11:57:07.18#ibcon#about to read 5, iclass 32, count 0 2006.285.11:57:07.18#ibcon#read 5, iclass 32, count 0 2006.285.11:57:07.18#ibcon#about to read 6, iclass 32, count 0 2006.285.11:57:07.18#ibcon#read 6, iclass 32, count 0 2006.285.11:57:07.18#ibcon#end of sib2, iclass 32, count 0 2006.285.11:57:07.18#ibcon#*mode == 0, iclass 32, count 0 2006.285.11:57:07.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.11:57:07.18#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.11:57:07.18#ibcon#*before write, iclass 32, count 0 2006.285.11:57:07.18#ibcon#enter sib2, iclass 32, count 0 2006.285.11:57:07.18#ibcon#flushed, iclass 32, count 0 2006.285.11:57:07.18#ibcon#about to write, iclass 32, count 0 2006.285.11:57:07.18#ibcon#wrote, iclass 32, count 0 2006.285.11:57:07.18#ibcon#about to read 3, iclass 32, count 0 2006.285.11:57:07.22#ibcon#read 3, iclass 32, count 0 2006.285.11:57:07.22#ibcon#about to read 4, iclass 32, count 0 2006.285.11:57:07.22#ibcon#read 4, iclass 32, count 0 2006.285.11:57:07.22#ibcon#about to read 5, iclass 32, count 0 2006.285.11:57:07.22#ibcon#read 5, iclass 32, count 0 2006.285.11:57:07.22#ibcon#about to read 6, iclass 32, count 0 2006.285.11:57:07.22#ibcon#read 6, iclass 32, count 0 2006.285.11:57:07.22#ibcon#end of sib2, iclass 32, count 0 2006.285.11:57:07.22#ibcon#*after write, iclass 32, count 0 2006.285.11:57:07.22#ibcon#*before return 0, iclass 32, count 0 2006.285.11:57:07.22#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:57:07.22#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.11:57:07.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.11:57:07.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.11:57:07.22$vck44/vb=6,3 2006.285.11:57:07.22#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.11:57:07.22#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.11:57:07.22#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:07.22#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:57:07.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:57:07.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:57:07.28#ibcon#enter wrdev, iclass 34, count 2 2006.285.11:57:07.28#ibcon#first serial, iclass 34, count 2 2006.285.11:57:07.28#ibcon#enter sib2, iclass 34, count 2 2006.285.11:57:07.28#ibcon#flushed, iclass 34, count 2 2006.285.11:57:07.28#ibcon#about to write, iclass 34, count 2 2006.285.11:57:07.28#ibcon#wrote, iclass 34, count 2 2006.285.11:57:07.28#ibcon#about to read 3, iclass 34, count 2 2006.285.11:57:07.30#ibcon#read 3, iclass 34, count 2 2006.285.11:57:07.30#ibcon#about to read 4, iclass 34, count 2 2006.285.11:57:07.30#ibcon#read 4, iclass 34, count 2 2006.285.11:57:07.30#ibcon#about to read 5, iclass 34, count 2 2006.285.11:57:07.30#ibcon#read 5, iclass 34, count 2 2006.285.11:57:07.30#ibcon#about to read 6, iclass 34, count 2 2006.285.11:57:07.30#ibcon#read 6, iclass 34, count 2 2006.285.11:57:07.30#ibcon#end of sib2, iclass 34, count 2 2006.285.11:57:07.30#ibcon#*mode == 0, iclass 34, count 2 2006.285.11:57:07.30#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.11:57:07.30#ibcon#[27=AT06-03\r\n] 2006.285.11:57:07.30#ibcon#*before write, iclass 34, count 2 2006.285.11:57:07.30#ibcon#enter sib2, iclass 34, count 2 2006.285.11:57:07.30#ibcon#flushed, iclass 34, count 2 2006.285.11:57:07.30#ibcon#about to write, iclass 34, count 2 2006.285.11:57:07.30#ibcon#wrote, iclass 34, count 2 2006.285.11:57:07.30#ibcon#about to read 3, iclass 34, count 2 2006.285.11:57:07.33#ibcon#read 3, iclass 34, count 2 2006.285.11:57:07.33#ibcon#about to read 4, iclass 34, count 2 2006.285.11:57:07.33#ibcon#read 4, iclass 34, count 2 2006.285.11:57:07.33#ibcon#about to read 5, iclass 34, count 2 2006.285.11:57:07.33#ibcon#read 5, iclass 34, count 2 2006.285.11:57:07.33#ibcon#about to read 6, iclass 34, count 2 2006.285.11:57:07.33#ibcon#read 6, iclass 34, count 2 2006.285.11:57:07.33#ibcon#end of sib2, iclass 34, count 2 2006.285.11:57:07.33#ibcon#*after write, iclass 34, count 2 2006.285.11:57:07.33#ibcon#*before return 0, iclass 34, count 2 2006.285.11:57:07.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:57:07.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.11:57:07.33#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.11:57:07.33#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:07.33#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:57:07.45#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:57:07.45#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:57:07.45#ibcon#enter wrdev, iclass 34, count 0 2006.285.11:57:07.45#ibcon#first serial, iclass 34, count 0 2006.285.11:57:07.45#ibcon#enter sib2, iclass 34, count 0 2006.285.11:57:07.45#ibcon#flushed, iclass 34, count 0 2006.285.11:57:07.45#ibcon#about to write, iclass 34, count 0 2006.285.11:57:07.45#ibcon#wrote, iclass 34, count 0 2006.285.11:57:07.45#ibcon#about to read 3, iclass 34, count 0 2006.285.11:57:07.47#ibcon#read 3, iclass 34, count 0 2006.285.11:57:07.47#ibcon#about to read 4, iclass 34, count 0 2006.285.11:57:07.47#ibcon#read 4, iclass 34, count 0 2006.285.11:57:07.47#ibcon#about to read 5, iclass 34, count 0 2006.285.11:57:07.47#ibcon#read 5, iclass 34, count 0 2006.285.11:57:07.47#ibcon#about to read 6, iclass 34, count 0 2006.285.11:57:07.47#ibcon#read 6, iclass 34, count 0 2006.285.11:57:07.47#ibcon#end of sib2, iclass 34, count 0 2006.285.11:57:07.47#ibcon#*mode == 0, iclass 34, count 0 2006.285.11:57:07.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.11:57:07.47#ibcon#[27=USB\r\n] 2006.285.11:57:07.47#ibcon#*before write, iclass 34, count 0 2006.285.11:57:07.47#ibcon#enter sib2, iclass 34, count 0 2006.285.11:57:07.47#ibcon#flushed, iclass 34, count 0 2006.285.11:57:07.47#ibcon#about to write, iclass 34, count 0 2006.285.11:57:07.47#ibcon#wrote, iclass 34, count 0 2006.285.11:57:07.47#ibcon#about to read 3, iclass 34, count 0 2006.285.11:57:07.50#ibcon#read 3, iclass 34, count 0 2006.285.11:57:07.50#ibcon#about to read 4, iclass 34, count 0 2006.285.11:57:07.50#ibcon#read 4, iclass 34, count 0 2006.285.11:57:07.50#ibcon#about to read 5, iclass 34, count 0 2006.285.11:57:07.50#ibcon#read 5, iclass 34, count 0 2006.285.11:57:07.50#ibcon#about to read 6, iclass 34, count 0 2006.285.11:57:07.50#ibcon#read 6, iclass 34, count 0 2006.285.11:57:07.50#ibcon#end of sib2, iclass 34, count 0 2006.285.11:57:07.50#ibcon#*after write, iclass 34, count 0 2006.285.11:57:07.50#ibcon#*before return 0, iclass 34, count 0 2006.285.11:57:07.50#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:57:07.50#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.11:57:07.50#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.11:57:07.50#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.11:57:07.50$vck44/vblo=7,734.99 2006.285.11:57:07.50#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.11:57:07.50#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.11:57:07.50#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:07.50#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:57:07.50#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:57:07.50#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:57:07.50#ibcon#enter wrdev, iclass 36, count 0 2006.285.11:57:07.50#ibcon#first serial, iclass 36, count 0 2006.285.11:57:07.50#ibcon#enter sib2, iclass 36, count 0 2006.285.11:57:07.50#ibcon#flushed, iclass 36, count 0 2006.285.11:57:07.50#ibcon#about to write, iclass 36, count 0 2006.285.11:57:07.50#ibcon#wrote, iclass 36, count 0 2006.285.11:57:07.50#ibcon#about to read 3, iclass 36, count 0 2006.285.11:57:07.52#ibcon#read 3, iclass 36, count 0 2006.285.11:57:07.52#ibcon#about to read 4, iclass 36, count 0 2006.285.11:57:07.52#ibcon#read 4, iclass 36, count 0 2006.285.11:57:07.52#ibcon#about to read 5, iclass 36, count 0 2006.285.11:57:07.52#ibcon#read 5, iclass 36, count 0 2006.285.11:57:07.52#ibcon#about to read 6, iclass 36, count 0 2006.285.11:57:07.52#ibcon#read 6, iclass 36, count 0 2006.285.11:57:07.52#ibcon#end of sib2, iclass 36, count 0 2006.285.11:57:07.52#ibcon#*mode == 0, iclass 36, count 0 2006.285.11:57:07.52#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.11:57:07.52#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.11:57:07.52#ibcon#*before write, iclass 36, count 0 2006.285.11:57:07.52#ibcon#enter sib2, iclass 36, count 0 2006.285.11:57:07.52#ibcon#flushed, iclass 36, count 0 2006.285.11:57:07.52#ibcon#about to write, iclass 36, count 0 2006.285.11:57:07.52#ibcon#wrote, iclass 36, count 0 2006.285.11:57:07.52#ibcon#about to read 3, iclass 36, count 0 2006.285.11:57:07.56#ibcon#read 3, iclass 36, count 0 2006.285.11:57:07.56#ibcon#about to read 4, iclass 36, count 0 2006.285.11:57:07.56#ibcon#read 4, iclass 36, count 0 2006.285.11:57:07.56#ibcon#about to read 5, iclass 36, count 0 2006.285.11:57:07.56#ibcon#read 5, iclass 36, count 0 2006.285.11:57:07.56#ibcon#about to read 6, iclass 36, count 0 2006.285.11:57:07.56#ibcon#read 6, iclass 36, count 0 2006.285.11:57:07.56#ibcon#end of sib2, iclass 36, count 0 2006.285.11:57:07.56#ibcon#*after write, iclass 36, count 0 2006.285.11:57:07.56#ibcon#*before return 0, iclass 36, count 0 2006.285.11:57:07.56#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:57:07.56#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.11:57:07.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.11:57:07.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.11:57:07.56$vck44/vb=7,4 2006.285.11:57:07.56#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.11:57:07.56#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.11:57:07.56#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:07.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:57:07.59#abcon#<5=/04 1.0 1.6 19.03 951015.4\r\n> 2006.285.11:57:07.61#abcon#{5=INTERFACE CLEAR} 2006.285.11:57:07.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:57:07.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:57:07.62#ibcon#enter wrdev, iclass 39, count 2 2006.285.11:57:07.62#ibcon#first serial, iclass 39, count 2 2006.285.11:57:07.62#ibcon#enter sib2, iclass 39, count 2 2006.285.11:57:07.62#ibcon#flushed, iclass 39, count 2 2006.285.11:57:07.62#ibcon#about to write, iclass 39, count 2 2006.285.11:57:07.62#ibcon#wrote, iclass 39, count 2 2006.285.11:57:07.62#ibcon#about to read 3, iclass 39, count 2 2006.285.11:57:07.64#ibcon#read 3, iclass 39, count 2 2006.285.11:57:07.64#ibcon#about to read 4, iclass 39, count 2 2006.285.11:57:07.64#ibcon#read 4, iclass 39, count 2 2006.285.11:57:07.64#ibcon#about to read 5, iclass 39, count 2 2006.285.11:57:07.64#ibcon#read 5, iclass 39, count 2 2006.285.11:57:07.64#ibcon#about to read 6, iclass 39, count 2 2006.285.11:57:07.64#ibcon#read 6, iclass 39, count 2 2006.285.11:57:07.64#ibcon#end of sib2, iclass 39, count 2 2006.285.11:57:07.64#ibcon#*mode == 0, iclass 39, count 2 2006.285.11:57:07.64#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.11:57:07.64#ibcon#[27=AT07-04\r\n] 2006.285.11:57:07.64#ibcon#*before write, iclass 39, count 2 2006.285.11:57:07.64#ibcon#enter sib2, iclass 39, count 2 2006.285.11:57:07.64#ibcon#flushed, iclass 39, count 2 2006.285.11:57:07.64#ibcon#about to write, iclass 39, count 2 2006.285.11:57:07.64#ibcon#wrote, iclass 39, count 2 2006.285.11:57:07.64#ibcon#about to read 3, iclass 39, count 2 2006.285.11:57:07.67#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:57:07.67#ibcon#read 3, iclass 39, count 2 2006.285.11:57:07.67#ibcon#about to read 4, iclass 39, count 2 2006.285.11:57:07.67#ibcon#read 4, iclass 39, count 2 2006.285.11:57:07.67#ibcon#about to read 5, iclass 39, count 2 2006.285.11:57:07.67#ibcon#read 5, iclass 39, count 2 2006.285.11:57:07.67#ibcon#about to read 6, iclass 39, count 2 2006.285.11:57:07.67#ibcon#read 6, iclass 39, count 2 2006.285.11:57:07.67#ibcon#end of sib2, iclass 39, count 2 2006.285.11:57:07.67#ibcon#*after write, iclass 39, count 2 2006.285.11:57:07.67#ibcon#*before return 0, iclass 39, count 2 2006.285.11:57:07.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:57:07.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.11:57:07.67#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.11:57:07.67#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:07.67#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:57:07.79#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:57:07.79#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:57:07.79#ibcon#enter wrdev, iclass 39, count 0 2006.285.11:57:07.79#ibcon#first serial, iclass 39, count 0 2006.285.11:57:07.79#ibcon#enter sib2, iclass 39, count 0 2006.285.11:57:07.79#ibcon#flushed, iclass 39, count 0 2006.285.11:57:07.79#ibcon#about to write, iclass 39, count 0 2006.285.11:57:07.79#ibcon#wrote, iclass 39, count 0 2006.285.11:57:07.79#ibcon#about to read 3, iclass 39, count 0 2006.285.11:57:07.81#ibcon#read 3, iclass 39, count 0 2006.285.11:57:07.81#ibcon#about to read 4, iclass 39, count 0 2006.285.11:57:07.81#ibcon#read 4, iclass 39, count 0 2006.285.11:57:07.81#ibcon#about to read 5, iclass 39, count 0 2006.285.11:57:07.81#ibcon#read 5, iclass 39, count 0 2006.285.11:57:07.81#ibcon#about to read 6, iclass 39, count 0 2006.285.11:57:07.81#ibcon#read 6, iclass 39, count 0 2006.285.11:57:07.81#ibcon#end of sib2, iclass 39, count 0 2006.285.11:57:07.81#ibcon#*mode == 0, iclass 39, count 0 2006.285.11:57:07.81#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.11:57:07.81#ibcon#[27=USB\r\n] 2006.285.11:57:07.81#ibcon#*before write, iclass 39, count 0 2006.285.11:57:07.81#ibcon#enter sib2, iclass 39, count 0 2006.285.11:57:07.81#ibcon#flushed, iclass 39, count 0 2006.285.11:57:07.81#ibcon#about to write, iclass 39, count 0 2006.285.11:57:07.81#ibcon#wrote, iclass 39, count 0 2006.285.11:57:07.81#ibcon#about to read 3, iclass 39, count 0 2006.285.11:57:07.84#ibcon#read 3, iclass 39, count 0 2006.285.11:57:07.84#ibcon#about to read 4, iclass 39, count 0 2006.285.11:57:07.84#ibcon#read 4, iclass 39, count 0 2006.285.11:57:07.84#ibcon#about to read 5, iclass 39, count 0 2006.285.11:57:07.84#ibcon#read 5, iclass 39, count 0 2006.285.11:57:07.84#ibcon#about to read 6, iclass 39, count 0 2006.285.11:57:07.84#ibcon#read 6, iclass 39, count 0 2006.285.11:57:07.84#ibcon#end of sib2, iclass 39, count 0 2006.285.11:57:07.84#ibcon#*after write, iclass 39, count 0 2006.285.11:57:07.84#ibcon#*before return 0, iclass 39, count 0 2006.285.11:57:07.84#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:57:07.84#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.11:57:07.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.11:57:07.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.11:57:07.84$vck44/vblo=8,744.99 2006.285.11:57:07.84#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.11:57:07.84#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.11:57:07.84#ibcon#ireg 17 cls_cnt 0 2006.285.11:57:07.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:57:07.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:57:07.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:57:07.84#ibcon#enter wrdev, iclass 6, count 0 2006.285.11:57:07.84#ibcon#first serial, iclass 6, count 0 2006.285.11:57:07.84#ibcon#enter sib2, iclass 6, count 0 2006.285.11:57:07.84#ibcon#flushed, iclass 6, count 0 2006.285.11:57:07.84#ibcon#about to write, iclass 6, count 0 2006.285.11:57:07.84#ibcon#wrote, iclass 6, count 0 2006.285.11:57:07.84#ibcon#about to read 3, iclass 6, count 0 2006.285.11:57:07.86#ibcon#read 3, iclass 6, count 0 2006.285.11:57:07.86#ibcon#about to read 4, iclass 6, count 0 2006.285.11:57:07.86#ibcon#read 4, iclass 6, count 0 2006.285.11:57:07.86#ibcon#about to read 5, iclass 6, count 0 2006.285.11:57:07.86#ibcon#read 5, iclass 6, count 0 2006.285.11:57:07.86#ibcon#about to read 6, iclass 6, count 0 2006.285.11:57:07.86#ibcon#read 6, iclass 6, count 0 2006.285.11:57:07.86#ibcon#end of sib2, iclass 6, count 0 2006.285.11:57:07.86#ibcon#*mode == 0, iclass 6, count 0 2006.285.11:57:07.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.11:57:07.86#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.11:57:07.86#ibcon#*before write, iclass 6, count 0 2006.285.11:57:07.86#ibcon#enter sib2, iclass 6, count 0 2006.285.11:57:07.86#ibcon#flushed, iclass 6, count 0 2006.285.11:57:07.86#ibcon#about to write, iclass 6, count 0 2006.285.11:57:07.86#ibcon#wrote, iclass 6, count 0 2006.285.11:57:07.86#ibcon#about to read 3, iclass 6, count 0 2006.285.11:57:07.90#ibcon#read 3, iclass 6, count 0 2006.285.11:57:07.90#ibcon#about to read 4, iclass 6, count 0 2006.285.11:57:07.90#ibcon#read 4, iclass 6, count 0 2006.285.11:57:07.90#ibcon#about to read 5, iclass 6, count 0 2006.285.11:57:07.90#ibcon#read 5, iclass 6, count 0 2006.285.11:57:07.90#ibcon#about to read 6, iclass 6, count 0 2006.285.11:57:07.90#ibcon#read 6, iclass 6, count 0 2006.285.11:57:07.90#ibcon#end of sib2, iclass 6, count 0 2006.285.11:57:07.90#ibcon#*after write, iclass 6, count 0 2006.285.11:57:07.90#ibcon#*before return 0, iclass 6, count 0 2006.285.11:57:07.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:57:07.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.11:57:07.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.11:57:07.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.11:57:07.90$vck44/vb=8,4 2006.285.11:57:07.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.11:57:07.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.11:57:07.90#ibcon#ireg 11 cls_cnt 2 2006.285.11:57:07.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:57:07.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:57:07.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:57:07.96#ibcon#enter wrdev, iclass 10, count 2 2006.285.11:57:07.96#ibcon#first serial, iclass 10, count 2 2006.285.11:57:07.96#ibcon#enter sib2, iclass 10, count 2 2006.285.11:57:07.96#ibcon#flushed, iclass 10, count 2 2006.285.11:57:07.96#ibcon#about to write, iclass 10, count 2 2006.285.11:57:07.96#ibcon#wrote, iclass 10, count 2 2006.285.11:57:07.96#ibcon#about to read 3, iclass 10, count 2 2006.285.11:57:07.98#ibcon#read 3, iclass 10, count 2 2006.285.11:57:07.98#ibcon#about to read 4, iclass 10, count 2 2006.285.11:57:07.98#ibcon#read 4, iclass 10, count 2 2006.285.11:57:07.98#ibcon#about to read 5, iclass 10, count 2 2006.285.11:57:07.98#ibcon#read 5, iclass 10, count 2 2006.285.11:57:07.98#ibcon#about to read 6, iclass 10, count 2 2006.285.11:57:07.98#ibcon#read 6, iclass 10, count 2 2006.285.11:57:07.98#ibcon#end of sib2, iclass 10, count 2 2006.285.11:57:07.98#ibcon#*mode == 0, iclass 10, count 2 2006.285.11:57:07.98#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.11:57:07.98#ibcon#[27=AT08-04\r\n] 2006.285.11:57:07.98#ibcon#*before write, iclass 10, count 2 2006.285.11:57:07.98#ibcon#enter sib2, iclass 10, count 2 2006.285.11:57:07.98#ibcon#flushed, iclass 10, count 2 2006.285.11:57:07.98#ibcon#about to write, iclass 10, count 2 2006.285.11:57:07.98#ibcon#wrote, iclass 10, count 2 2006.285.11:57:07.98#ibcon#about to read 3, iclass 10, count 2 2006.285.11:57:08.01#ibcon#read 3, iclass 10, count 2 2006.285.11:57:08.01#ibcon#about to read 4, iclass 10, count 2 2006.285.11:57:08.01#ibcon#read 4, iclass 10, count 2 2006.285.11:57:08.01#ibcon#about to read 5, iclass 10, count 2 2006.285.11:57:08.01#ibcon#read 5, iclass 10, count 2 2006.285.11:57:08.01#ibcon#about to read 6, iclass 10, count 2 2006.285.11:57:08.01#ibcon#read 6, iclass 10, count 2 2006.285.11:57:08.01#ibcon#end of sib2, iclass 10, count 2 2006.285.11:57:08.01#ibcon#*after write, iclass 10, count 2 2006.285.11:57:08.01#ibcon#*before return 0, iclass 10, count 2 2006.285.11:57:08.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:57:08.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.11:57:08.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.11:57:08.01#ibcon#ireg 7 cls_cnt 0 2006.285.11:57:08.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:57:08.13#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:57:08.13#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:57:08.13#ibcon#enter wrdev, iclass 10, count 0 2006.285.11:57:08.13#ibcon#first serial, iclass 10, count 0 2006.285.11:57:08.13#ibcon#enter sib2, iclass 10, count 0 2006.285.11:57:08.13#ibcon#flushed, iclass 10, count 0 2006.285.11:57:08.13#ibcon#about to write, iclass 10, count 0 2006.285.11:57:08.13#ibcon#wrote, iclass 10, count 0 2006.285.11:57:08.13#ibcon#about to read 3, iclass 10, count 0 2006.285.11:57:08.15#ibcon#read 3, iclass 10, count 0 2006.285.11:57:08.15#ibcon#about to read 4, iclass 10, count 0 2006.285.11:57:08.15#ibcon#read 4, iclass 10, count 0 2006.285.11:57:08.15#ibcon#about to read 5, iclass 10, count 0 2006.285.11:57:08.15#ibcon#read 5, iclass 10, count 0 2006.285.11:57:08.15#ibcon#about to read 6, iclass 10, count 0 2006.285.11:57:08.15#ibcon#read 6, iclass 10, count 0 2006.285.11:57:08.15#ibcon#end of sib2, iclass 10, count 0 2006.285.11:57:08.15#ibcon#*mode == 0, iclass 10, count 0 2006.285.11:57:08.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.11:57:08.15#ibcon#[27=USB\r\n] 2006.285.11:57:08.15#ibcon#*before write, iclass 10, count 0 2006.285.11:57:08.15#ibcon#enter sib2, iclass 10, count 0 2006.285.11:57:08.15#ibcon#flushed, iclass 10, count 0 2006.285.11:57:08.15#ibcon#about to write, iclass 10, count 0 2006.285.11:57:08.15#ibcon#wrote, iclass 10, count 0 2006.285.11:57:08.15#ibcon#about to read 3, iclass 10, count 0 2006.285.11:57:08.18#ibcon#read 3, iclass 10, count 0 2006.285.11:57:08.18#ibcon#about to read 4, iclass 10, count 0 2006.285.11:57:08.18#ibcon#read 4, iclass 10, count 0 2006.285.11:57:08.18#ibcon#about to read 5, iclass 10, count 0 2006.285.11:57:08.18#ibcon#read 5, iclass 10, count 0 2006.285.11:57:08.18#ibcon#about to read 6, iclass 10, count 0 2006.285.11:57:08.18#ibcon#read 6, iclass 10, count 0 2006.285.11:57:08.18#ibcon#end of sib2, iclass 10, count 0 2006.285.11:57:08.18#ibcon#*after write, iclass 10, count 0 2006.285.11:57:08.18#ibcon#*before return 0, iclass 10, count 0 2006.285.11:57:08.18#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:57:08.18#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.11:57:08.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.11:57:08.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.11:57:08.18$vck44/vabw=wide 2006.285.11:57:08.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.11:57:08.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.11:57:08.18#ibcon#ireg 8 cls_cnt 0 2006.285.11:57:08.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:57:08.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:57:08.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:57:08.18#ibcon#enter wrdev, iclass 12, count 0 2006.285.11:57:08.18#ibcon#first serial, iclass 12, count 0 2006.285.11:57:08.18#ibcon#enter sib2, iclass 12, count 0 2006.285.11:57:08.18#ibcon#flushed, iclass 12, count 0 2006.285.11:57:08.18#ibcon#about to write, iclass 12, count 0 2006.285.11:57:08.18#ibcon#wrote, iclass 12, count 0 2006.285.11:57:08.18#ibcon#about to read 3, iclass 12, count 0 2006.285.11:57:08.20#ibcon#read 3, iclass 12, count 0 2006.285.11:57:08.20#ibcon#about to read 4, iclass 12, count 0 2006.285.11:57:08.20#ibcon#read 4, iclass 12, count 0 2006.285.11:57:08.20#ibcon#about to read 5, iclass 12, count 0 2006.285.11:57:08.20#ibcon#read 5, iclass 12, count 0 2006.285.11:57:08.20#ibcon#about to read 6, iclass 12, count 0 2006.285.11:57:08.20#ibcon#read 6, iclass 12, count 0 2006.285.11:57:08.20#ibcon#end of sib2, iclass 12, count 0 2006.285.11:57:08.20#ibcon#*mode == 0, iclass 12, count 0 2006.285.11:57:08.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.11:57:08.20#ibcon#[25=BW32\r\n] 2006.285.11:57:08.20#ibcon#*before write, iclass 12, count 0 2006.285.11:57:08.20#ibcon#enter sib2, iclass 12, count 0 2006.285.11:57:08.20#ibcon#flushed, iclass 12, count 0 2006.285.11:57:08.20#ibcon#about to write, iclass 12, count 0 2006.285.11:57:08.20#ibcon#wrote, iclass 12, count 0 2006.285.11:57:08.20#ibcon#about to read 3, iclass 12, count 0 2006.285.11:57:08.23#ibcon#read 3, iclass 12, count 0 2006.285.11:57:08.23#ibcon#about to read 4, iclass 12, count 0 2006.285.11:57:08.23#ibcon#read 4, iclass 12, count 0 2006.285.11:57:08.23#ibcon#about to read 5, iclass 12, count 0 2006.285.11:57:08.23#ibcon#read 5, iclass 12, count 0 2006.285.11:57:08.23#ibcon#about to read 6, iclass 12, count 0 2006.285.11:57:08.23#ibcon#read 6, iclass 12, count 0 2006.285.11:57:08.23#ibcon#end of sib2, iclass 12, count 0 2006.285.11:57:08.23#ibcon#*after write, iclass 12, count 0 2006.285.11:57:08.23#ibcon#*before return 0, iclass 12, count 0 2006.285.11:57:08.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:57:08.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.11:57:08.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.11:57:08.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.11:57:08.23$vck44/vbbw=wide 2006.285.11:57:08.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.11:57:08.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.11:57:08.23#ibcon#ireg 8 cls_cnt 0 2006.285.11:57:08.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:57:08.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:57:08.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:57:08.30#ibcon#enter wrdev, iclass 14, count 0 2006.285.11:57:08.30#ibcon#first serial, iclass 14, count 0 2006.285.11:57:08.30#ibcon#enter sib2, iclass 14, count 0 2006.285.11:57:08.30#ibcon#flushed, iclass 14, count 0 2006.285.11:57:08.30#ibcon#about to write, iclass 14, count 0 2006.285.11:57:08.30#ibcon#wrote, iclass 14, count 0 2006.285.11:57:08.30#ibcon#about to read 3, iclass 14, count 0 2006.285.11:57:08.32#ibcon#read 3, iclass 14, count 0 2006.285.11:57:08.32#ibcon#about to read 4, iclass 14, count 0 2006.285.11:57:08.32#ibcon#read 4, iclass 14, count 0 2006.285.11:57:08.32#ibcon#about to read 5, iclass 14, count 0 2006.285.11:57:08.32#ibcon#read 5, iclass 14, count 0 2006.285.11:57:08.32#ibcon#about to read 6, iclass 14, count 0 2006.285.11:57:08.32#ibcon#read 6, iclass 14, count 0 2006.285.11:57:08.32#ibcon#end of sib2, iclass 14, count 0 2006.285.11:57:08.32#ibcon#*mode == 0, iclass 14, count 0 2006.285.11:57:08.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.11:57:08.32#ibcon#[27=BW32\r\n] 2006.285.11:57:08.32#ibcon#*before write, iclass 14, count 0 2006.285.11:57:08.32#ibcon#enter sib2, iclass 14, count 0 2006.285.11:57:08.32#ibcon#flushed, iclass 14, count 0 2006.285.11:57:08.32#ibcon#about to write, iclass 14, count 0 2006.285.11:57:08.32#ibcon#wrote, iclass 14, count 0 2006.285.11:57:08.32#ibcon#about to read 3, iclass 14, count 0 2006.285.11:57:08.35#ibcon#read 3, iclass 14, count 0 2006.285.11:57:08.35#ibcon#about to read 4, iclass 14, count 0 2006.285.11:57:08.35#ibcon#read 4, iclass 14, count 0 2006.285.11:57:08.35#ibcon#about to read 5, iclass 14, count 0 2006.285.11:57:08.35#ibcon#read 5, iclass 14, count 0 2006.285.11:57:08.35#ibcon#about to read 6, iclass 14, count 0 2006.285.11:57:08.35#ibcon#read 6, iclass 14, count 0 2006.285.11:57:08.35#ibcon#end of sib2, iclass 14, count 0 2006.285.11:57:08.35#ibcon#*after write, iclass 14, count 0 2006.285.11:57:08.35#ibcon#*before return 0, iclass 14, count 0 2006.285.11:57:08.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:57:08.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.11:57:08.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.11:57:08.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.11:57:08.35$setupk4/ifdk4 2006.285.11:57:08.35$ifdk4/lo= 2006.285.11:57:08.35$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.11:57:08.35$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.11:57:08.35$ifdk4/patch= 2006.285.11:57:08.35$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.11:57:08.35$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.11:57:08.35$setupk4/!*+20s 2006.285.11:57:17.76#abcon#<5=/04 1.0 1.6 19.03 951015.4\r\n> 2006.285.11:57:17.78#abcon#{5=INTERFACE CLEAR} 2006.285.11:57:17.84#abcon#[5=S1D000X0/0*\r\n] 2006.285.11:57:22.86$setupk4/"tpicd 2006.285.11:57:22.86$setupk4/echo=off 2006.285.11:57:22.86$setupk4/xlog=off 2006.285.11:57:22.86:!2006.285.12:01:23 2006.285.11:57:36.14#trakl#Source acquired 2006.285.11:57:36.14#flagr#flagr/antenna,acquired 2006.285.12:01:23.00:preob 2006.285.12:01:23.14/onsource/TRACKING 2006.285.12:01:23.14:!2006.285.12:01:33 2006.285.12:01:33.00:"tape 2006.285.12:01:33.00:"st=record 2006.285.12:01:33.00:data_valid=on 2006.285.12:01:33.00:midob 2006.285.12:01:33.14/onsource/TRACKING 2006.285.12:01:33.14/wx/19.02,1015.5,95 2006.285.12:01:33.31/cable/+6.4950E-03 2006.285.12:01:34.40/va/01,07,usb,yes,36,39 2006.285.12:01:34.40/va/02,06,usb,yes,36,36 2006.285.12:01:34.40/va/03,07,usb,yes,35,38 2006.285.12:01:34.40/va/04,06,usb,yes,37,39 2006.285.12:01:34.40/va/05,03,usb,yes,37,37 2006.285.12:01:34.40/va/06,04,usb,yes,33,33 2006.285.12:01:34.40/va/07,04,usb,yes,34,34 2006.285.12:01:34.40/va/08,03,usb,yes,35,42 2006.285.12:01:34.63/valo/01,524.99,yes,locked 2006.285.12:01:34.63/valo/02,534.99,yes,locked 2006.285.12:01:34.63/valo/03,564.99,yes,locked 2006.285.12:01:34.63/valo/04,624.99,yes,locked 2006.285.12:01:34.63/valo/05,734.99,yes,locked 2006.285.12:01:34.63/valo/06,814.99,yes,locked 2006.285.12:01:34.63/valo/07,864.99,yes,locked 2006.285.12:01:34.63/valo/08,884.99,yes,locked 2006.285.12:01:35.72/vb/01,04,usb,yes,33,31 2006.285.12:01:35.72/vb/02,05,usb,yes,31,31 2006.285.12:01:35.72/vb/03,04,usb,yes,32,35 2006.285.12:01:35.72/vb/04,05,usb,yes,33,31 2006.285.12:01:35.72/vb/05,04,usb,yes,29,31 2006.285.12:01:35.72/vb/06,03,usb,yes,41,37 2006.285.12:01:35.72/vb/07,04,usb,yes,33,33 2006.285.12:01:35.72/vb/08,04,usb,yes,30,34 2006.285.12:01:35.95/vblo/01,629.99,yes,locked 2006.285.12:01:35.95/vblo/02,634.99,yes,locked 2006.285.12:01:35.95/vblo/03,649.99,yes,locked 2006.285.12:01:35.95/vblo/04,679.99,yes,locked 2006.285.12:01:35.95/vblo/05,709.99,yes,locked 2006.285.12:01:35.95/vblo/06,719.99,yes,locked 2006.285.12:01:35.95/vblo/07,734.99,yes,locked 2006.285.12:01:35.95/vblo/08,744.99,yes,locked 2006.285.12:01:36.10/vabw/8 2006.285.12:01:36.25/vbbw/8 2006.285.12:01:36.36/xfe/off,on,12.2 2006.285.12:01:36.73/ifatt/23,28,28,28 2006.285.12:01:37.07/fmout-gps/S +2.51E-07 2006.285.12:01:37.09:!2006.285.12:02:53 2006.285.12:02:53.00:data_valid=off 2006.285.12:02:53.00:"et 2006.285.12:02:53.00:!+3s 2006.285.12:02:56.01:"tape 2006.285.12:02:56.01:postob 2006.285.12:02:56.11/cable/+6.4952E-03 2006.285.12:02:56.11/wx/19.01,1015.5,95 2006.285.12:02:57.07/fmout-gps/S +2.46E-07 2006.285.12:02:57.07:scan_name=285-1208,jd0610,150 2006.285.12:02:57.07:source=1958-179,200057.09,-174857.7,2000.0,ccw 2006.285.12:02:58.13#flagr#flagr/antenna,new-source 2006.285.12:02:58.13:checkk5 2006.285.12:02:58.51/chk_autoobs//k5ts1/ autoobs is running! 2006.285.12:02:59.14/chk_autoobs//k5ts2/ autoobs is running! 2006.285.12:02:59.53/chk_autoobs//k5ts3/ autoobs is running! 2006.285.12:02:59.92/chk_autoobs//k5ts4/ autoobs is running! 2006.285.12:03:00.29/chk_obsdata//k5ts1/T2851201??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.12:03:00.67/chk_obsdata//k5ts2/T2851201??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.12:03:01.03/chk_obsdata//k5ts3/T2851201??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.12:03:01.70/chk_obsdata//k5ts4/T2851201??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.12:03:02.38/k5log//k5ts1_log_newline 2006.285.12:03:03.10/k5log//k5ts2_log_newline 2006.285.12:03:03.81/k5log//k5ts3_log_newline 2006.285.12:03:04.53/k5log//k5ts4_log_newline 2006.285.12:03:04.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.12:03:04.55:setupk4=1 2006.285.12:03:04.55$setupk4/echo=on 2006.285.12:03:04.55$setupk4/pcalon 2006.285.12:03:04.55$pcalon/"no phase cal control is implemented here 2006.285.12:03:04.55$setupk4/"tpicd=stop 2006.285.12:03:04.55$setupk4/"rec=synch_on 2006.285.12:03:04.55$setupk4/"rec_mode=128 2006.285.12:03:04.55$setupk4/!* 2006.285.12:03:04.55$setupk4/recpk4 2006.285.12:03:04.55$recpk4/recpatch= 2006.285.12:03:04.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.12:03:04.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.12:03:04.55$setupk4/vck44 2006.285.12:03:04.55$vck44/valo=1,524.99 2006.285.12:03:04.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.12:03:04.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.12:03:04.55#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:04.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:03:04.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:03:04.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:03:04.55#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:03:04.55#ibcon#first serial, iclass 15, count 0 2006.285.12:03:04.55#ibcon#enter sib2, iclass 15, count 0 2006.285.12:03:04.55#ibcon#flushed, iclass 15, count 0 2006.285.12:03:04.55#ibcon#about to write, iclass 15, count 0 2006.285.12:03:04.55#ibcon#wrote, iclass 15, count 0 2006.285.12:03:04.55#ibcon#about to read 3, iclass 15, count 0 2006.285.12:03:04.57#ibcon#read 3, iclass 15, count 0 2006.285.12:03:04.57#ibcon#about to read 4, iclass 15, count 0 2006.285.12:03:04.57#ibcon#read 4, iclass 15, count 0 2006.285.12:03:04.57#ibcon#about to read 5, iclass 15, count 0 2006.285.12:03:04.57#ibcon#read 5, iclass 15, count 0 2006.285.12:03:04.57#ibcon#about to read 6, iclass 15, count 0 2006.285.12:03:04.57#ibcon#read 6, iclass 15, count 0 2006.285.12:03:04.57#ibcon#end of sib2, iclass 15, count 0 2006.285.12:03:04.57#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:03:04.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:03:04.57#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.12:03:04.57#ibcon#*before write, iclass 15, count 0 2006.285.12:03:04.57#ibcon#enter sib2, iclass 15, count 0 2006.285.12:03:04.57#ibcon#flushed, iclass 15, count 0 2006.285.12:03:04.57#ibcon#about to write, iclass 15, count 0 2006.285.12:03:04.57#ibcon#wrote, iclass 15, count 0 2006.285.12:03:04.57#ibcon#about to read 3, iclass 15, count 0 2006.285.12:03:04.62#ibcon#read 3, iclass 15, count 0 2006.285.12:03:04.62#ibcon#about to read 4, iclass 15, count 0 2006.285.12:03:04.62#ibcon#read 4, iclass 15, count 0 2006.285.12:03:04.62#ibcon#about to read 5, iclass 15, count 0 2006.285.12:03:04.62#ibcon#read 5, iclass 15, count 0 2006.285.12:03:04.62#ibcon#about to read 6, iclass 15, count 0 2006.285.12:03:04.62#ibcon#read 6, iclass 15, count 0 2006.285.12:03:04.62#ibcon#end of sib2, iclass 15, count 0 2006.285.12:03:04.62#ibcon#*after write, iclass 15, count 0 2006.285.12:03:04.62#ibcon#*before return 0, iclass 15, count 0 2006.285.12:03:04.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:03:04.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:03:04.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:03:04.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:03:04.62$vck44/va=1,7 2006.285.12:03:04.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.12:03:04.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.12:03:04.62#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:04.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:03:04.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:03:04.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:03:04.62#ibcon#enter wrdev, iclass 17, count 2 2006.285.12:03:04.62#ibcon#first serial, iclass 17, count 2 2006.285.12:03:04.62#ibcon#enter sib2, iclass 17, count 2 2006.285.12:03:04.62#ibcon#flushed, iclass 17, count 2 2006.285.12:03:04.62#ibcon#about to write, iclass 17, count 2 2006.285.12:03:04.62#ibcon#wrote, iclass 17, count 2 2006.285.12:03:04.62#ibcon#about to read 3, iclass 17, count 2 2006.285.12:03:04.64#ibcon#read 3, iclass 17, count 2 2006.285.12:03:04.64#ibcon#about to read 4, iclass 17, count 2 2006.285.12:03:04.64#ibcon#read 4, iclass 17, count 2 2006.285.12:03:04.64#ibcon#about to read 5, iclass 17, count 2 2006.285.12:03:04.64#ibcon#read 5, iclass 17, count 2 2006.285.12:03:04.64#ibcon#about to read 6, iclass 17, count 2 2006.285.12:03:04.64#ibcon#read 6, iclass 17, count 2 2006.285.12:03:04.64#ibcon#end of sib2, iclass 17, count 2 2006.285.12:03:04.64#ibcon#*mode == 0, iclass 17, count 2 2006.285.12:03:04.64#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.12:03:04.64#ibcon#[25=AT01-07\r\n] 2006.285.12:03:04.64#ibcon#*before write, iclass 17, count 2 2006.285.12:03:04.64#ibcon#enter sib2, iclass 17, count 2 2006.285.12:03:04.64#ibcon#flushed, iclass 17, count 2 2006.285.12:03:04.64#ibcon#about to write, iclass 17, count 2 2006.285.12:03:04.64#ibcon#wrote, iclass 17, count 2 2006.285.12:03:04.64#ibcon#about to read 3, iclass 17, count 2 2006.285.12:03:04.67#ibcon#read 3, iclass 17, count 2 2006.285.12:03:04.67#ibcon#about to read 4, iclass 17, count 2 2006.285.12:03:04.67#ibcon#read 4, iclass 17, count 2 2006.285.12:03:04.67#ibcon#about to read 5, iclass 17, count 2 2006.285.12:03:04.67#ibcon#read 5, iclass 17, count 2 2006.285.12:03:04.67#ibcon#about to read 6, iclass 17, count 2 2006.285.12:03:04.67#ibcon#read 6, iclass 17, count 2 2006.285.12:03:04.67#ibcon#end of sib2, iclass 17, count 2 2006.285.12:03:04.67#ibcon#*after write, iclass 17, count 2 2006.285.12:03:04.67#ibcon#*before return 0, iclass 17, count 2 2006.285.12:03:04.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:03:04.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:03:04.67#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.12:03:04.67#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:04.67#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:03:04.79#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:03:04.79#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:03:04.79#ibcon#enter wrdev, iclass 17, count 0 2006.285.12:03:04.79#ibcon#first serial, iclass 17, count 0 2006.285.12:03:04.79#ibcon#enter sib2, iclass 17, count 0 2006.285.12:03:04.79#ibcon#flushed, iclass 17, count 0 2006.285.12:03:04.79#ibcon#about to write, iclass 17, count 0 2006.285.12:03:04.79#ibcon#wrote, iclass 17, count 0 2006.285.12:03:04.79#ibcon#about to read 3, iclass 17, count 0 2006.285.12:03:04.81#ibcon#read 3, iclass 17, count 0 2006.285.12:03:04.81#ibcon#about to read 4, iclass 17, count 0 2006.285.12:03:04.81#ibcon#read 4, iclass 17, count 0 2006.285.12:03:04.81#ibcon#about to read 5, iclass 17, count 0 2006.285.12:03:04.81#ibcon#read 5, iclass 17, count 0 2006.285.12:03:04.81#ibcon#about to read 6, iclass 17, count 0 2006.285.12:03:04.81#ibcon#read 6, iclass 17, count 0 2006.285.12:03:04.81#ibcon#end of sib2, iclass 17, count 0 2006.285.12:03:04.81#ibcon#*mode == 0, iclass 17, count 0 2006.285.12:03:04.81#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.12:03:04.81#ibcon#[25=USB\r\n] 2006.285.12:03:04.81#ibcon#*before write, iclass 17, count 0 2006.285.12:03:04.81#ibcon#enter sib2, iclass 17, count 0 2006.285.12:03:04.81#ibcon#flushed, iclass 17, count 0 2006.285.12:03:04.81#ibcon#about to write, iclass 17, count 0 2006.285.12:03:04.81#ibcon#wrote, iclass 17, count 0 2006.285.12:03:04.81#ibcon#about to read 3, iclass 17, count 0 2006.285.12:03:04.84#ibcon#read 3, iclass 17, count 0 2006.285.12:03:04.84#ibcon#about to read 4, iclass 17, count 0 2006.285.12:03:04.84#ibcon#read 4, iclass 17, count 0 2006.285.12:03:04.84#ibcon#about to read 5, iclass 17, count 0 2006.285.12:03:04.84#ibcon#read 5, iclass 17, count 0 2006.285.12:03:04.84#ibcon#about to read 6, iclass 17, count 0 2006.285.12:03:04.84#ibcon#read 6, iclass 17, count 0 2006.285.12:03:04.84#ibcon#end of sib2, iclass 17, count 0 2006.285.12:03:04.84#ibcon#*after write, iclass 17, count 0 2006.285.12:03:04.84#ibcon#*before return 0, iclass 17, count 0 2006.285.12:03:04.84#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:03:04.84#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:03:04.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.12:03:04.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.12:03:04.84$vck44/valo=2,534.99 2006.285.12:03:04.84#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.12:03:04.84#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.12:03:04.84#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:04.84#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:03:04.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:03:04.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:03:04.84#ibcon#enter wrdev, iclass 19, count 0 2006.285.12:03:04.84#ibcon#first serial, iclass 19, count 0 2006.285.12:03:04.84#ibcon#enter sib2, iclass 19, count 0 2006.285.12:03:04.84#ibcon#flushed, iclass 19, count 0 2006.285.12:03:04.84#ibcon#about to write, iclass 19, count 0 2006.285.12:03:04.84#ibcon#wrote, iclass 19, count 0 2006.285.12:03:04.84#ibcon#about to read 3, iclass 19, count 0 2006.285.12:03:04.86#ibcon#read 3, iclass 19, count 0 2006.285.12:03:04.86#ibcon#about to read 4, iclass 19, count 0 2006.285.12:03:04.86#ibcon#read 4, iclass 19, count 0 2006.285.12:03:04.86#ibcon#about to read 5, iclass 19, count 0 2006.285.12:03:04.86#ibcon#read 5, iclass 19, count 0 2006.285.12:03:04.86#ibcon#about to read 6, iclass 19, count 0 2006.285.12:03:04.86#ibcon#read 6, iclass 19, count 0 2006.285.12:03:04.86#ibcon#end of sib2, iclass 19, count 0 2006.285.12:03:04.86#ibcon#*mode == 0, iclass 19, count 0 2006.285.12:03:04.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.12:03:04.86#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.12:03:04.86#ibcon#*before write, iclass 19, count 0 2006.285.12:03:04.86#ibcon#enter sib2, iclass 19, count 0 2006.285.12:03:04.86#ibcon#flushed, iclass 19, count 0 2006.285.12:03:04.86#ibcon#about to write, iclass 19, count 0 2006.285.12:03:04.86#ibcon#wrote, iclass 19, count 0 2006.285.12:03:04.86#ibcon#about to read 3, iclass 19, count 0 2006.285.12:03:04.90#ibcon#read 3, iclass 19, count 0 2006.285.12:03:04.90#ibcon#about to read 4, iclass 19, count 0 2006.285.12:03:04.90#ibcon#read 4, iclass 19, count 0 2006.285.12:03:04.90#ibcon#about to read 5, iclass 19, count 0 2006.285.12:03:04.90#ibcon#read 5, iclass 19, count 0 2006.285.12:03:04.90#ibcon#about to read 6, iclass 19, count 0 2006.285.12:03:04.90#ibcon#read 6, iclass 19, count 0 2006.285.12:03:04.90#ibcon#end of sib2, iclass 19, count 0 2006.285.12:03:04.90#ibcon#*after write, iclass 19, count 0 2006.285.12:03:04.90#ibcon#*before return 0, iclass 19, count 0 2006.285.12:03:04.90#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:03:04.90#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:03:04.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.12:03:04.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.12:03:04.90$vck44/va=2,6 2006.285.12:03:04.90#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.12:03:04.90#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.12:03:04.90#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:04.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:03:04.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:03:04.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:03:04.96#ibcon#enter wrdev, iclass 21, count 2 2006.285.12:03:04.96#ibcon#first serial, iclass 21, count 2 2006.285.12:03:04.96#ibcon#enter sib2, iclass 21, count 2 2006.285.12:03:04.96#ibcon#flushed, iclass 21, count 2 2006.285.12:03:04.96#ibcon#about to write, iclass 21, count 2 2006.285.12:03:04.96#ibcon#wrote, iclass 21, count 2 2006.285.12:03:04.96#ibcon#about to read 3, iclass 21, count 2 2006.285.12:03:04.98#ibcon#read 3, iclass 21, count 2 2006.285.12:03:04.98#ibcon#about to read 4, iclass 21, count 2 2006.285.12:03:04.98#ibcon#read 4, iclass 21, count 2 2006.285.12:03:04.98#ibcon#about to read 5, iclass 21, count 2 2006.285.12:03:04.98#ibcon#read 5, iclass 21, count 2 2006.285.12:03:04.98#ibcon#about to read 6, iclass 21, count 2 2006.285.12:03:04.98#ibcon#read 6, iclass 21, count 2 2006.285.12:03:04.98#ibcon#end of sib2, iclass 21, count 2 2006.285.12:03:04.98#ibcon#*mode == 0, iclass 21, count 2 2006.285.12:03:04.98#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.12:03:04.98#ibcon#[25=AT02-06\r\n] 2006.285.12:03:04.98#ibcon#*before write, iclass 21, count 2 2006.285.12:03:04.98#ibcon#enter sib2, iclass 21, count 2 2006.285.12:03:04.98#ibcon#flushed, iclass 21, count 2 2006.285.12:03:04.98#ibcon#about to write, iclass 21, count 2 2006.285.12:03:04.98#ibcon#wrote, iclass 21, count 2 2006.285.12:03:04.98#ibcon#about to read 3, iclass 21, count 2 2006.285.12:03:05.01#ibcon#read 3, iclass 21, count 2 2006.285.12:03:05.01#ibcon#about to read 4, iclass 21, count 2 2006.285.12:03:05.01#ibcon#read 4, iclass 21, count 2 2006.285.12:03:05.01#ibcon#about to read 5, iclass 21, count 2 2006.285.12:03:05.01#ibcon#read 5, iclass 21, count 2 2006.285.12:03:05.01#ibcon#about to read 6, iclass 21, count 2 2006.285.12:03:05.01#ibcon#read 6, iclass 21, count 2 2006.285.12:03:05.01#ibcon#end of sib2, iclass 21, count 2 2006.285.12:03:05.01#ibcon#*after write, iclass 21, count 2 2006.285.12:03:05.01#ibcon#*before return 0, iclass 21, count 2 2006.285.12:03:05.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:03:05.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:03:05.01#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.12:03:05.01#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:05.01#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:03:05.13#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:03:05.13#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:03:05.13#ibcon#enter wrdev, iclass 21, count 0 2006.285.12:03:05.13#ibcon#first serial, iclass 21, count 0 2006.285.12:03:05.13#ibcon#enter sib2, iclass 21, count 0 2006.285.12:03:05.13#ibcon#flushed, iclass 21, count 0 2006.285.12:03:05.13#ibcon#about to write, iclass 21, count 0 2006.285.12:03:05.13#ibcon#wrote, iclass 21, count 0 2006.285.12:03:05.13#ibcon#about to read 3, iclass 21, count 0 2006.285.12:03:05.15#ibcon#read 3, iclass 21, count 0 2006.285.12:03:05.15#ibcon#about to read 4, iclass 21, count 0 2006.285.12:03:05.15#ibcon#read 4, iclass 21, count 0 2006.285.12:03:05.15#ibcon#about to read 5, iclass 21, count 0 2006.285.12:03:05.15#ibcon#read 5, iclass 21, count 0 2006.285.12:03:05.15#ibcon#about to read 6, iclass 21, count 0 2006.285.12:03:05.15#ibcon#read 6, iclass 21, count 0 2006.285.12:03:05.15#ibcon#end of sib2, iclass 21, count 0 2006.285.12:03:05.15#ibcon#*mode == 0, iclass 21, count 0 2006.285.12:03:05.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.12:03:05.15#ibcon#[25=USB\r\n] 2006.285.12:03:05.15#ibcon#*before write, iclass 21, count 0 2006.285.12:03:05.15#ibcon#enter sib2, iclass 21, count 0 2006.285.12:03:05.15#ibcon#flushed, iclass 21, count 0 2006.285.12:03:05.15#ibcon#about to write, iclass 21, count 0 2006.285.12:03:05.15#ibcon#wrote, iclass 21, count 0 2006.285.12:03:05.15#ibcon#about to read 3, iclass 21, count 0 2006.285.12:03:05.18#ibcon#read 3, iclass 21, count 0 2006.285.12:03:05.18#ibcon#about to read 4, iclass 21, count 0 2006.285.12:03:05.18#ibcon#read 4, iclass 21, count 0 2006.285.12:03:05.18#ibcon#about to read 5, iclass 21, count 0 2006.285.12:03:05.18#ibcon#read 5, iclass 21, count 0 2006.285.12:03:05.18#ibcon#about to read 6, iclass 21, count 0 2006.285.12:03:05.18#ibcon#read 6, iclass 21, count 0 2006.285.12:03:05.18#ibcon#end of sib2, iclass 21, count 0 2006.285.12:03:05.18#ibcon#*after write, iclass 21, count 0 2006.285.12:03:05.18#ibcon#*before return 0, iclass 21, count 0 2006.285.12:03:05.18#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:03:05.18#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:03:05.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.12:03:05.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.12:03:05.18$vck44/valo=3,564.99 2006.285.12:03:05.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.12:03:05.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.12:03:05.18#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:05.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:03:05.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:03:05.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:03:05.18#ibcon#enter wrdev, iclass 23, count 0 2006.285.12:03:05.18#ibcon#first serial, iclass 23, count 0 2006.285.12:03:05.18#ibcon#enter sib2, iclass 23, count 0 2006.285.12:03:05.18#ibcon#flushed, iclass 23, count 0 2006.285.12:03:05.18#ibcon#about to write, iclass 23, count 0 2006.285.12:03:05.18#ibcon#wrote, iclass 23, count 0 2006.285.12:03:05.18#ibcon#about to read 3, iclass 23, count 0 2006.285.12:03:05.20#ibcon#read 3, iclass 23, count 0 2006.285.12:03:05.20#ibcon#about to read 4, iclass 23, count 0 2006.285.12:03:05.20#ibcon#read 4, iclass 23, count 0 2006.285.12:03:05.20#ibcon#about to read 5, iclass 23, count 0 2006.285.12:03:05.20#ibcon#read 5, iclass 23, count 0 2006.285.12:03:05.20#ibcon#about to read 6, iclass 23, count 0 2006.285.12:03:05.20#ibcon#read 6, iclass 23, count 0 2006.285.12:03:05.20#ibcon#end of sib2, iclass 23, count 0 2006.285.12:03:05.20#ibcon#*mode == 0, iclass 23, count 0 2006.285.12:03:05.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.12:03:05.20#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.12:03:05.20#ibcon#*before write, iclass 23, count 0 2006.285.12:03:05.20#ibcon#enter sib2, iclass 23, count 0 2006.285.12:03:05.20#ibcon#flushed, iclass 23, count 0 2006.285.12:03:05.20#ibcon#about to write, iclass 23, count 0 2006.285.12:03:05.20#ibcon#wrote, iclass 23, count 0 2006.285.12:03:05.20#ibcon#about to read 3, iclass 23, count 0 2006.285.12:03:05.24#ibcon#read 3, iclass 23, count 0 2006.285.12:03:05.24#ibcon#about to read 4, iclass 23, count 0 2006.285.12:03:05.24#ibcon#read 4, iclass 23, count 0 2006.285.12:03:05.24#ibcon#about to read 5, iclass 23, count 0 2006.285.12:03:05.24#ibcon#read 5, iclass 23, count 0 2006.285.12:03:05.24#ibcon#about to read 6, iclass 23, count 0 2006.285.12:03:05.24#ibcon#read 6, iclass 23, count 0 2006.285.12:03:05.24#ibcon#end of sib2, iclass 23, count 0 2006.285.12:03:05.24#ibcon#*after write, iclass 23, count 0 2006.285.12:03:05.24#ibcon#*before return 0, iclass 23, count 0 2006.285.12:03:05.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:03:05.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:03:05.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.12:03:05.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.12:03:05.24$vck44/va=3,7 2006.285.12:03:05.24#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.12:03:05.24#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.12:03:05.24#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:05.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:03:05.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:03:05.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:03:05.30#ibcon#enter wrdev, iclass 25, count 2 2006.285.12:03:05.30#ibcon#first serial, iclass 25, count 2 2006.285.12:03:05.30#ibcon#enter sib2, iclass 25, count 2 2006.285.12:03:05.30#ibcon#flushed, iclass 25, count 2 2006.285.12:03:05.30#ibcon#about to write, iclass 25, count 2 2006.285.12:03:05.30#ibcon#wrote, iclass 25, count 2 2006.285.12:03:05.30#ibcon#about to read 3, iclass 25, count 2 2006.285.12:03:05.32#ibcon#read 3, iclass 25, count 2 2006.285.12:03:05.32#ibcon#about to read 4, iclass 25, count 2 2006.285.12:03:05.32#ibcon#read 4, iclass 25, count 2 2006.285.12:03:05.32#ibcon#about to read 5, iclass 25, count 2 2006.285.12:03:05.32#ibcon#read 5, iclass 25, count 2 2006.285.12:03:05.32#ibcon#about to read 6, iclass 25, count 2 2006.285.12:03:05.32#ibcon#read 6, iclass 25, count 2 2006.285.12:03:05.32#ibcon#end of sib2, iclass 25, count 2 2006.285.12:03:05.32#ibcon#*mode == 0, iclass 25, count 2 2006.285.12:03:05.32#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.12:03:05.32#ibcon#[25=AT03-07\r\n] 2006.285.12:03:05.32#ibcon#*before write, iclass 25, count 2 2006.285.12:03:05.32#ibcon#enter sib2, iclass 25, count 2 2006.285.12:03:05.32#ibcon#flushed, iclass 25, count 2 2006.285.12:03:05.32#ibcon#about to write, iclass 25, count 2 2006.285.12:03:05.32#ibcon#wrote, iclass 25, count 2 2006.285.12:03:05.32#ibcon#about to read 3, iclass 25, count 2 2006.285.12:03:05.35#ibcon#read 3, iclass 25, count 2 2006.285.12:03:05.35#ibcon#about to read 4, iclass 25, count 2 2006.285.12:03:05.35#ibcon#read 4, iclass 25, count 2 2006.285.12:03:05.35#ibcon#about to read 5, iclass 25, count 2 2006.285.12:03:05.35#ibcon#read 5, iclass 25, count 2 2006.285.12:03:05.35#ibcon#about to read 6, iclass 25, count 2 2006.285.12:03:05.35#ibcon#read 6, iclass 25, count 2 2006.285.12:03:05.35#ibcon#end of sib2, iclass 25, count 2 2006.285.12:03:05.35#ibcon#*after write, iclass 25, count 2 2006.285.12:03:05.35#ibcon#*before return 0, iclass 25, count 2 2006.285.12:03:05.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:03:05.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:03:05.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.12:03:05.35#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:05.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:03:05.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:03:05.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:03:05.47#ibcon#enter wrdev, iclass 25, count 0 2006.285.12:03:05.47#ibcon#first serial, iclass 25, count 0 2006.285.12:03:05.47#ibcon#enter sib2, iclass 25, count 0 2006.285.12:03:05.47#ibcon#flushed, iclass 25, count 0 2006.285.12:03:05.47#ibcon#about to write, iclass 25, count 0 2006.285.12:03:05.47#ibcon#wrote, iclass 25, count 0 2006.285.12:03:05.47#ibcon#about to read 3, iclass 25, count 0 2006.285.12:03:05.49#ibcon#read 3, iclass 25, count 0 2006.285.12:03:05.49#ibcon#about to read 4, iclass 25, count 0 2006.285.12:03:05.49#ibcon#read 4, iclass 25, count 0 2006.285.12:03:05.49#ibcon#about to read 5, iclass 25, count 0 2006.285.12:03:05.49#ibcon#read 5, iclass 25, count 0 2006.285.12:03:05.49#ibcon#about to read 6, iclass 25, count 0 2006.285.12:03:05.49#ibcon#read 6, iclass 25, count 0 2006.285.12:03:05.49#ibcon#end of sib2, iclass 25, count 0 2006.285.12:03:05.49#ibcon#*mode == 0, iclass 25, count 0 2006.285.12:03:05.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.12:03:05.49#ibcon#[25=USB\r\n] 2006.285.12:03:05.49#ibcon#*before write, iclass 25, count 0 2006.285.12:03:05.49#ibcon#enter sib2, iclass 25, count 0 2006.285.12:03:05.49#ibcon#flushed, iclass 25, count 0 2006.285.12:03:05.49#ibcon#about to write, iclass 25, count 0 2006.285.12:03:05.49#ibcon#wrote, iclass 25, count 0 2006.285.12:03:05.49#ibcon#about to read 3, iclass 25, count 0 2006.285.12:03:05.52#ibcon#read 3, iclass 25, count 0 2006.285.12:03:05.52#ibcon#about to read 4, iclass 25, count 0 2006.285.12:03:05.52#ibcon#read 4, iclass 25, count 0 2006.285.12:03:05.52#ibcon#about to read 5, iclass 25, count 0 2006.285.12:03:05.52#ibcon#read 5, iclass 25, count 0 2006.285.12:03:05.52#ibcon#about to read 6, iclass 25, count 0 2006.285.12:03:05.52#ibcon#read 6, iclass 25, count 0 2006.285.12:03:05.52#ibcon#end of sib2, iclass 25, count 0 2006.285.12:03:05.52#ibcon#*after write, iclass 25, count 0 2006.285.12:03:05.52#ibcon#*before return 0, iclass 25, count 0 2006.285.12:03:05.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:03:05.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:03:05.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.12:03:05.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.12:03:05.52$vck44/valo=4,624.99 2006.285.12:03:05.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.12:03:05.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.12:03:05.52#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:05.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:03:05.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:03:05.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:03:05.52#ibcon#enter wrdev, iclass 27, count 0 2006.285.12:03:05.52#ibcon#first serial, iclass 27, count 0 2006.285.12:03:05.52#ibcon#enter sib2, iclass 27, count 0 2006.285.12:03:05.52#ibcon#flushed, iclass 27, count 0 2006.285.12:03:05.52#ibcon#about to write, iclass 27, count 0 2006.285.12:03:05.52#ibcon#wrote, iclass 27, count 0 2006.285.12:03:05.52#ibcon#about to read 3, iclass 27, count 0 2006.285.12:03:05.54#ibcon#read 3, iclass 27, count 0 2006.285.12:03:05.54#ibcon#about to read 4, iclass 27, count 0 2006.285.12:03:05.54#ibcon#read 4, iclass 27, count 0 2006.285.12:03:05.54#ibcon#about to read 5, iclass 27, count 0 2006.285.12:03:05.54#ibcon#read 5, iclass 27, count 0 2006.285.12:03:05.54#ibcon#about to read 6, iclass 27, count 0 2006.285.12:03:05.54#ibcon#read 6, iclass 27, count 0 2006.285.12:03:05.54#ibcon#end of sib2, iclass 27, count 0 2006.285.12:03:05.54#ibcon#*mode == 0, iclass 27, count 0 2006.285.12:03:05.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.12:03:05.54#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.12:03:05.54#ibcon#*before write, iclass 27, count 0 2006.285.12:03:05.54#ibcon#enter sib2, iclass 27, count 0 2006.285.12:03:05.54#ibcon#flushed, iclass 27, count 0 2006.285.12:03:05.54#ibcon#about to write, iclass 27, count 0 2006.285.12:03:05.54#ibcon#wrote, iclass 27, count 0 2006.285.12:03:05.54#ibcon#about to read 3, iclass 27, count 0 2006.285.12:03:05.58#ibcon#read 3, iclass 27, count 0 2006.285.12:03:05.58#ibcon#about to read 4, iclass 27, count 0 2006.285.12:03:05.58#ibcon#read 4, iclass 27, count 0 2006.285.12:03:05.58#ibcon#about to read 5, iclass 27, count 0 2006.285.12:03:05.58#ibcon#read 5, iclass 27, count 0 2006.285.12:03:05.58#ibcon#about to read 6, iclass 27, count 0 2006.285.12:03:05.58#ibcon#read 6, iclass 27, count 0 2006.285.12:03:05.58#ibcon#end of sib2, iclass 27, count 0 2006.285.12:03:05.58#ibcon#*after write, iclass 27, count 0 2006.285.12:03:05.58#ibcon#*before return 0, iclass 27, count 0 2006.285.12:03:05.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:03:05.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:03:05.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.12:03:05.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.12:03:05.58$vck44/va=4,6 2006.285.12:03:05.58#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.12:03:05.58#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.12:03:05.58#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:05.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:03:05.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:03:05.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:03:05.64#ibcon#enter wrdev, iclass 29, count 2 2006.285.12:03:05.64#ibcon#first serial, iclass 29, count 2 2006.285.12:03:05.64#ibcon#enter sib2, iclass 29, count 2 2006.285.12:03:05.64#ibcon#flushed, iclass 29, count 2 2006.285.12:03:05.64#ibcon#about to write, iclass 29, count 2 2006.285.12:03:05.64#ibcon#wrote, iclass 29, count 2 2006.285.12:03:05.64#ibcon#about to read 3, iclass 29, count 2 2006.285.12:03:05.66#ibcon#read 3, iclass 29, count 2 2006.285.12:03:05.66#ibcon#about to read 4, iclass 29, count 2 2006.285.12:03:05.66#ibcon#read 4, iclass 29, count 2 2006.285.12:03:05.66#ibcon#about to read 5, iclass 29, count 2 2006.285.12:03:05.66#ibcon#read 5, iclass 29, count 2 2006.285.12:03:05.66#ibcon#about to read 6, iclass 29, count 2 2006.285.12:03:05.66#ibcon#read 6, iclass 29, count 2 2006.285.12:03:05.66#ibcon#end of sib2, iclass 29, count 2 2006.285.12:03:05.66#ibcon#*mode == 0, iclass 29, count 2 2006.285.12:03:05.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.12:03:05.66#ibcon#[25=AT04-06\r\n] 2006.285.12:03:05.66#ibcon#*before write, iclass 29, count 2 2006.285.12:03:05.66#ibcon#enter sib2, iclass 29, count 2 2006.285.12:03:05.66#ibcon#flushed, iclass 29, count 2 2006.285.12:03:05.66#ibcon#about to write, iclass 29, count 2 2006.285.12:03:05.66#ibcon#wrote, iclass 29, count 2 2006.285.12:03:05.66#ibcon#about to read 3, iclass 29, count 2 2006.285.12:03:05.69#ibcon#read 3, iclass 29, count 2 2006.285.12:03:05.69#ibcon#about to read 4, iclass 29, count 2 2006.285.12:03:05.69#ibcon#read 4, iclass 29, count 2 2006.285.12:03:05.69#ibcon#about to read 5, iclass 29, count 2 2006.285.12:03:05.69#ibcon#read 5, iclass 29, count 2 2006.285.12:03:05.69#ibcon#about to read 6, iclass 29, count 2 2006.285.12:03:05.69#ibcon#read 6, iclass 29, count 2 2006.285.12:03:05.69#ibcon#end of sib2, iclass 29, count 2 2006.285.12:03:05.69#ibcon#*after write, iclass 29, count 2 2006.285.12:03:05.69#ibcon#*before return 0, iclass 29, count 2 2006.285.12:03:05.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:03:05.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:03:05.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.12:03:05.69#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:05.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:03:05.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:03:05.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:03:05.81#ibcon#enter wrdev, iclass 29, count 0 2006.285.12:03:05.81#ibcon#first serial, iclass 29, count 0 2006.285.12:03:05.81#ibcon#enter sib2, iclass 29, count 0 2006.285.12:03:05.81#ibcon#flushed, iclass 29, count 0 2006.285.12:03:05.81#ibcon#about to write, iclass 29, count 0 2006.285.12:03:05.81#ibcon#wrote, iclass 29, count 0 2006.285.12:03:05.81#ibcon#about to read 3, iclass 29, count 0 2006.285.12:03:05.83#ibcon#read 3, iclass 29, count 0 2006.285.12:03:05.83#ibcon#about to read 4, iclass 29, count 0 2006.285.12:03:05.83#ibcon#read 4, iclass 29, count 0 2006.285.12:03:05.83#ibcon#about to read 5, iclass 29, count 0 2006.285.12:03:05.83#ibcon#read 5, iclass 29, count 0 2006.285.12:03:05.83#ibcon#about to read 6, iclass 29, count 0 2006.285.12:03:05.83#ibcon#read 6, iclass 29, count 0 2006.285.12:03:05.83#ibcon#end of sib2, iclass 29, count 0 2006.285.12:03:05.83#ibcon#*mode == 0, iclass 29, count 0 2006.285.12:03:05.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.12:03:05.83#ibcon#[25=USB\r\n] 2006.285.12:03:05.83#ibcon#*before write, iclass 29, count 0 2006.285.12:03:05.83#ibcon#enter sib2, iclass 29, count 0 2006.285.12:03:05.83#ibcon#flushed, iclass 29, count 0 2006.285.12:03:05.83#ibcon#about to write, iclass 29, count 0 2006.285.12:03:05.83#ibcon#wrote, iclass 29, count 0 2006.285.12:03:05.83#ibcon#about to read 3, iclass 29, count 0 2006.285.12:03:05.86#ibcon#read 3, iclass 29, count 0 2006.285.12:03:05.86#ibcon#about to read 4, iclass 29, count 0 2006.285.12:03:05.86#ibcon#read 4, iclass 29, count 0 2006.285.12:03:05.86#ibcon#about to read 5, iclass 29, count 0 2006.285.12:03:05.86#ibcon#read 5, iclass 29, count 0 2006.285.12:03:05.86#ibcon#about to read 6, iclass 29, count 0 2006.285.12:03:05.86#ibcon#read 6, iclass 29, count 0 2006.285.12:03:05.86#ibcon#end of sib2, iclass 29, count 0 2006.285.12:03:05.86#ibcon#*after write, iclass 29, count 0 2006.285.12:03:05.86#ibcon#*before return 0, iclass 29, count 0 2006.285.12:03:05.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:03:05.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:03:05.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.12:03:05.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.12:03:05.86$vck44/valo=5,734.99 2006.285.12:03:05.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.12:03:05.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.12:03:05.86#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:05.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:03:05.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:03:05.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:03:05.86#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:03:05.86#ibcon#first serial, iclass 31, count 0 2006.285.12:03:05.86#ibcon#enter sib2, iclass 31, count 0 2006.285.12:03:05.86#ibcon#flushed, iclass 31, count 0 2006.285.12:03:05.86#ibcon#about to write, iclass 31, count 0 2006.285.12:03:05.86#ibcon#wrote, iclass 31, count 0 2006.285.12:03:05.86#ibcon#about to read 3, iclass 31, count 0 2006.285.12:03:05.88#ibcon#read 3, iclass 31, count 0 2006.285.12:03:05.88#ibcon#about to read 4, iclass 31, count 0 2006.285.12:03:05.88#ibcon#read 4, iclass 31, count 0 2006.285.12:03:05.88#ibcon#about to read 5, iclass 31, count 0 2006.285.12:03:05.88#ibcon#read 5, iclass 31, count 0 2006.285.12:03:05.88#ibcon#about to read 6, iclass 31, count 0 2006.285.12:03:05.88#ibcon#read 6, iclass 31, count 0 2006.285.12:03:05.88#ibcon#end of sib2, iclass 31, count 0 2006.285.12:03:05.88#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:03:05.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:03:05.88#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.12:03:05.88#ibcon#*before write, iclass 31, count 0 2006.285.12:03:05.88#ibcon#enter sib2, iclass 31, count 0 2006.285.12:03:05.88#ibcon#flushed, iclass 31, count 0 2006.285.12:03:05.88#ibcon#about to write, iclass 31, count 0 2006.285.12:03:05.88#ibcon#wrote, iclass 31, count 0 2006.285.12:03:05.88#ibcon#about to read 3, iclass 31, count 0 2006.285.12:03:05.92#ibcon#read 3, iclass 31, count 0 2006.285.12:03:05.92#ibcon#about to read 4, iclass 31, count 0 2006.285.12:03:05.92#ibcon#read 4, iclass 31, count 0 2006.285.12:03:05.92#ibcon#about to read 5, iclass 31, count 0 2006.285.12:03:05.92#ibcon#read 5, iclass 31, count 0 2006.285.12:03:05.92#ibcon#about to read 6, iclass 31, count 0 2006.285.12:03:05.92#ibcon#read 6, iclass 31, count 0 2006.285.12:03:05.92#ibcon#end of sib2, iclass 31, count 0 2006.285.12:03:05.92#ibcon#*after write, iclass 31, count 0 2006.285.12:03:05.92#ibcon#*before return 0, iclass 31, count 0 2006.285.12:03:05.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:03:05.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:03:05.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:03:05.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:03:05.92$vck44/va=5,3 2006.285.12:03:05.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.12:03:05.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.12:03:05.92#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:05.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:03:05.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:03:05.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:03:05.98#ibcon#enter wrdev, iclass 33, count 2 2006.285.12:03:05.98#ibcon#first serial, iclass 33, count 2 2006.285.12:03:05.98#ibcon#enter sib2, iclass 33, count 2 2006.285.12:03:05.98#ibcon#flushed, iclass 33, count 2 2006.285.12:03:05.98#ibcon#about to write, iclass 33, count 2 2006.285.12:03:05.98#ibcon#wrote, iclass 33, count 2 2006.285.12:03:05.98#ibcon#about to read 3, iclass 33, count 2 2006.285.12:03:06.00#ibcon#read 3, iclass 33, count 2 2006.285.12:03:06.00#ibcon#about to read 4, iclass 33, count 2 2006.285.12:03:06.00#ibcon#read 4, iclass 33, count 2 2006.285.12:03:06.00#ibcon#about to read 5, iclass 33, count 2 2006.285.12:03:06.00#ibcon#read 5, iclass 33, count 2 2006.285.12:03:06.00#ibcon#about to read 6, iclass 33, count 2 2006.285.12:03:06.00#ibcon#read 6, iclass 33, count 2 2006.285.12:03:06.00#ibcon#end of sib2, iclass 33, count 2 2006.285.12:03:06.00#ibcon#*mode == 0, iclass 33, count 2 2006.285.12:03:06.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.12:03:06.00#ibcon#[25=AT05-03\r\n] 2006.285.12:03:06.00#ibcon#*before write, iclass 33, count 2 2006.285.12:03:06.00#ibcon#enter sib2, iclass 33, count 2 2006.285.12:03:06.00#ibcon#flushed, iclass 33, count 2 2006.285.12:03:06.00#ibcon#about to write, iclass 33, count 2 2006.285.12:03:06.00#ibcon#wrote, iclass 33, count 2 2006.285.12:03:06.00#ibcon#about to read 3, iclass 33, count 2 2006.285.12:03:06.03#ibcon#read 3, iclass 33, count 2 2006.285.12:03:06.03#ibcon#about to read 4, iclass 33, count 2 2006.285.12:03:06.03#ibcon#read 4, iclass 33, count 2 2006.285.12:03:06.03#ibcon#about to read 5, iclass 33, count 2 2006.285.12:03:06.03#ibcon#read 5, iclass 33, count 2 2006.285.12:03:06.03#ibcon#about to read 6, iclass 33, count 2 2006.285.12:03:06.03#ibcon#read 6, iclass 33, count 2 2006.285.12:03:06.03#ibcon#end of sib2, iclass 33, count 2 2006.285.12:03:06.03#ibcon#*after write, iclass 33, count 2 2006.285.12:03:06.03#ibcon#*before return 0, iclass 33, count 2 2006.285.12:03:06.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:03:06.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:03:06.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.12:03:06.03#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:06.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:03:06.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:03:06.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:03:06.15#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:03:06.15#ibcon#first serial, iclass 33, count 0 2006.285.12:03:06.15#ibcon#enter sib2, iclass 33, count 0 2006.285.12:03:06.15#ibcon#flushed, iclass 33, count 0 2006.285.12:03:06.15#ibcon#about to write, iclass 33, count 0 2006.285.12:03:06.15#ibcon#wrote, iclass 33, count 0 2006.285.12:03:06.15#ibcon#about to read 3, iclass 33, count 0 2006.285.12:03:06.17#ibcon#read 3, iclass 33, count 0 2006.285.12:03:06.17#ibcon#about to read 4, iclass 33, count 0 2006.285.12:03:06.17#ibcon#read 4, iclass 33, count 0 2006.285.12:03:06.17#ibcon#about to read 5, iclass 33, count 0 2006.285.12:03:06.17#ibcon#read 5, iclass 33, count 0 2006.285.12:03:06.17#ibcon#about to read 6, iclass 33, count 0 2006.285.12:03:06.17#ibcon#read 6, iclass 33, count 0 2006.285.12:03:06.17#ibcon#end of sib2, iclass 33, count 0 2006.285.12:03:06.17#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:03:06.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:03:06.17#ibcon#[25=USB\r\n] 2006.285.12:03:06.17#ibcon#*before write, iclass 33, count 0 2006.285.12:03:06.17#ibcon#enter sib2, iclass 33, count 0 2006.285.12:03:06.17#ibcon#flushed, iclass 33, count 0 2006.285.12:03:06.17#ibcon#about to write, iclass 33, count 0 2006.285.12:03:06.17#ibcon#wrote, iclass 33, count 0 2006.285.12:03:06.17#ibcon#about to read 3, iclass 33, count 0 2006.285.12:03:06.20#ibcon#read 3, iclass 33, count 0 2006.285.12:03:06.20#ibcon#about to read 4, iclass 33, count 0 2006.285.12:03:06.20#ibcon#read 4, iclass 33, count 0 2006.285.12:03:06.20#ibcon#about to read 5, iclass 33, count 0 2006.285.12:03:06.20#ibcon#read 5, iclass 33, count 0 2006.285.12:03:06.20#ibcon#about to read 6, iclass 33, count 0 2006.285.12:03:06.20#ibcon#read 6, iclass 33, count 0 2006.285.12:03:06.20#ibcon#end of sib2, iclass 33, count 0 2006.285.12:03:06.20#ibcon#*after write, iclass 33, count 0 2006.285.12:03:06.20#ibcon#*before return 0, iclass 33, count 0 2006.285.12:03:06.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:03:06.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:03:06.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:03:06.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:03:06.20$vck44/valo=6,814.99 2006.285.12:03:06.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.12:03:06.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.12:03:06.20#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:06.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:03:06.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:03:06.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:03:06.20#ibcon#enter wrdev, iclass 35, count 0 2006.285.12:03:06.20#ibcon#first serial, iclass 35, count 0 2006.285.12:03:06.20#ibcon#enter sib2, iclass 35, count 0 2006.285.12:03:06.20#ibcon#flushed, iclass 35, count 0 2006.285.12:03:06.20#ibcon#about to write, iclass 35, count 0 2006.285.12:03:06.20#ibcon#wrote, iclass 35, count 0 2006.285.12:03:06.20#ibcon#about to read 3, iclass 35, count 0 2006.285.12:03:06.22#ibcon#read 3, iclass 35, count 0 2006.285.12:03:06.22#ibcon#about to read 4, iclass 35, count 0 2006.285.12:03:06.22#ibcon#read 4, iclass 35, count 0 2006.285.12:03:06.22#ibcon#about to read 5, iclass 35, count 0 2006.285.12:03:06.22#ibcon#read 5, iclass 35, count 0 2006.285.12:03:06.22#ibcon#about to read 6, iclass 35, count 0 2006.285.12:03:06.22#ibcon#read 6, iclass 35, count 0 2006.285.12:03:06.22#ibcon#end of sib2, iclass 35, count 0 2006.285.12:03:06.22#ibcon#*mode == 0, iclass 35, count 0 2006.285.12:03:06.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.12:03:06.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.12:03:06.22#ibcon#*before write, iclass 35, count 0 2006.285.12:03:06.22#ibcon#enter sib2, iclass 35, count 0 2006.285.12:03:06.22#ibcon#flushed, iclass 35, count 0 2006.285.12:03:06.22#ibcon#about to write, iclass 35, count 0 2006.285.12:03:06.22#ibcon#wrote, iclass 35, count 0 2006.285.12:03:06.22#ibcon#about to read 3, iclass 35, count 0 2006.285.12:03:06.26#ibcon#read 3, iclass 35, count 0 2006.285.12:03:06.26#ibcon#about to read 4, iclass 35, count 0 2006.285.12:03:06.26#ibcon#read 4, iclass 35, count 0 2006.285.12:03:06.26#ibcon#about to read 5, iclass 35, count 0 2006.285.12:03:06.26#ibcon#read 5, iclass 35, count 0 2006.285.12:03:06.26#ibcon#about to read 6, iclass 35, count 0 2006.285.12:03:06.26#ibcon#read 6, iclass 35, count 0 2006.285.12:03:06.26#ibcon#end of sib2, iclass 35, count 0 2006.285.12:03:06.26#ibcon#*after write, iclass 35, count 0 2006.285.12:03:06.26#ibcon#*before return 0, iclass 35, count 0 2006.285.12:03:06.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:03:06.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:03:06.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.12:03:06.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.12:03:06.26$vck44/va=6,4 2006.285.12:03:06.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.12:03:06.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.12:03:06.26#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:06.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:03:06.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:03:06.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:03:06.32#ibcon#enter wrdev, iclass 37, count 2 2006.285.12:03:06.32#ibcon#first serial, iclass 37, count 2 2006.285.12:03:06.32#ibcon#enter sib2, iclass 37, count 2 2006.285.12:03:06.32#ibcon#flushed, iclass 37, count 2 2006.285.12:03:06.32#ibcon#about to write, iclass 37, count 2 2006.285.12:03:06.32#ibcon#wrote, iclass 37, count 2 2006.285.12:03:06.32#ibcon#about to read 3, iclass 37, count 2 2006.285.12:03:06.34#ibcon#read 3, iclass 37, count 2 2006.285.12:03:06.34#ibcon#about to read 4, iclass 37, count 2 2006.285.12:03:06.34#ibcon#read 4, iclass 37, count 2 2006.285.12:03:06.34#ibcon#about to read 5, iclass 37, count 2 2006.285.12:03:06.34#ibcon#read 5, iclass 37, count 2 2006.285.12:03:06.34#ibcon#about to read 6, iclass 37, count 2 2006.285.12:03:06.34#ibcon#read 6, iclass 37, count 2 2006.285.12:03:06.34#ibcon#end of sib2, iclass 37, count 2 2006.285.12:03:06.34#ibcon#*mode == 0, iclass 37, count 2 2006.285.12:03:06.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.12:03:06.34#ibcon#[25=AT06-04\r\n] 2006.285.12:03:06.34#ibcon#*before write, iclass 37, count 2 2006.285.12:03:06.34#ibcon#enter sib2, iclass 37, count 2 2006.285.12:03:06.34#ibcon#flushed, iclass 37, count 2 2006.285.12:03:06.34#ibcon#about to write, iclass 37, count 2 2006.285.12:03:06.34#ibcon#wrote, iclass 37, count 2 2006.285.12:03:06.34#ibcon#about to read 3, iclass 37, count 2 2006.285.12:03:06.37#ibcon#read 3, iclass 37, count 2 2006.285.12:03:06.37#ibcon#about to read 4, iclass 37, count 2 2006.285.12:03:06.37#ibcon#read 4, iclass 37, count 2 2006.285.12:03:06.37#ibcon#about to read 5, iclass 37, count 2 2006.285.12:03:06.37#ibcon#read 5, iclass 37, count 2 2006.285.12:03:06.37#ibcon#about to read 6, iclass 37, count 2 2006.285.12:03:06.37#ibcon#read 6, iclass 37, count 2 2006.285.12:03:06.37#ibcon#end of sib2, iclass 37, count 2 2006.285.12:03:06.37#ibcon#*after write, iclass 37, count 2 2006.285.12:03:06.37#ibcon#*before return 0, iclass 37, count 2 2006.285.12:03:06.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:03:06.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:03:06.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.12:03:06.37#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:06.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:03:06.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:03:06.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:03:06.49#ibcon#enter wrdev, iclass 37, count 0 2006.285.12:03:06.49#ibcon#first serial, iclass 37, count 0 2006.285.12:03:06.49#ibcon#enter sib2, iclass 37, count 0 2006.285.12:03:06.49#ibcon#flushed, iclass 37, count 0 2006.285.12:03:06.49#ibcon#about to write, iclass 37, count 0 2006.285.12:03:06.49#ibcon#wrote, iclass 37, count 0 2006.285.12:03:06.49#ibcon#about to read 3, iclass 37, count 0 2006.285.12:03:06.51#ibcon#read 3, iclass 37, count 0 2006.285.12:03:06.51#ibcon#about to read 4, iclass 37, count 0 2006.285.12:03:06.51#ibcon#read 4, iclass 37, count 0 2006.285.12:03:06.51#ibcon#about to read 5, iclass 37, count 0 2006.285.12:03:06.51#ibcon#read 5, iclass 37, count 0 2006.285.12:03:06.51#ibcon#about to read 6, iclass 37, count 0 2006.285.12:03:06.51#ibcon#read 6, iclass 37, count 0 2006.285.12:03:06.51#ibcon#end of sib2, iclass 37, count 0 2006.285.12:03:06.51#ibcon#*mode == 0, iclass 37, count 0 2006.285.12:03:06.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.12:03:06.51#ibcon#[25=USB\r\n] 2006.285.12:03:06.51#ibcon#*before write, iclass 37, count 0 2006.285.12:03:06.51#ibcon#enter sib2, iclass 37, count 0 2006.285.12:03:06.51#ibcon#flushed, iclass 37, count 0 2006.285.12:03:06.51#ibcon#about to write, iclass 37, count 0 2006.285.12:03:06.51#ibcon#wrote, iclass 37, count 0 2006.285.12:03:06.51#ibcon#about to read 3, iclass 37, count 0 2006.285.12:03:06.54#ibcon#read 3, iclass 37, count 0 2006.285.12:03:06.54#ibcon#about to read 4, iclass 37, count 0 2006.285.12:03:06.54#ibcon#read 4, iclass 37, count 0 2006.285.12:03:06.54#ibcon#about to read 5, iclass 37, count 0 2006.285.12:03:06.54#ibcon#read 5, iclass 37, count 0 2006.285.12:03:06.54#ibcon#about to read 6, iclass 37, count 0 2006.285.12:03:06.54#ibcon#read 6, iclass 37, count 0 2006.285.12:03:06.54#ibcon#end of sib2, iclass 37, count 0 2006.285.12:03:06.54#ibcon#*after write, iclass 37, count 0 2006.285.12:03:06.54#ibcon#*before return 0, iclass 37, count 0 2006.285.12:03:06.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:03:06.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:03:06.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.12:03:06.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.12:03:06.54$vck44/valo=7,864.99 2006.285.12:03:06.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.12:03:06.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.12:03:06.54#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:06.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:03:06.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:03:06.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:03:06.54#ibcon#enter wrdev, iclass 39, count 0 2006.285.12:03:06.54#ibcon#first serial, iclass 39, count 0 2006.285.12:03:06.54#ibcon#enter sib2, iclass 39, count 0 2006.285.12:03:06.54#ibcon#flushed, iclass 39, count 0 2006.285.12:03:06.54#ibcon#about to write, iclass 39, count 0 2006.285.12:03:06.54#ibcon#wrote, iclass 39, count 0 2006.285.12:03:06.54#ibcon#about to read 3, iclass 39, count 0 2006.285.12:03:06.56#ibcon#read 3, iclass 39, count 0 2006.285.12:03:06.56#ibcon#about to read 4, iclass 39, count 0 2006.285.12:03:06.56#ibcon#read 4, iclass 39, count 0 2006.285.12:03:06.56#ibcon#about to read 5, iclass 39, count 0 2006.285.12:03:06.56#ibcon#read 5, iclass 39, count 0 2006.285.12:03:06.56#ibcon#about to read 6, iclass 39, count 0 2006.285.12:03:06.56#ibcon#read 6, iclass 39, count 0 2006.285.12:03:06.56#ibcon#end of sib2, iclass 39, count 0 2006.285.12:03:06.56#ibcon#*mode == 0, iclass 39, count 0 2006.285.12:03:06.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.12:03:06.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.12:03:06.56#ibcon#*before write, iclass 39, count 0 2006.285.12:03:06.56#ibcon#enter sib2, iclass 39, count 0 2006.285.12:03:06.56#ibcon#flushed, iclass 39, count 0 2006.285.12:03:06.56#ibcon#about to write, iclass 39, count 0 2006.285.12:03:06.56#ibcon#wrote, iclass 39, count 0 2006.285.12:03:06.56#ibcon#about to read 3, iclass 39, count 0 2006.285.12:03:06.60#ibcon#read 3, iclass 39, count 0 2006.285.12:03:06.60#ibcon#about to read 4, iclass 39, count 0 2006.285.12:03:06.60#ibcon#read 4, iclass 39, count 0 2006.285.12:03:06.60#ibcon#about to read 5, iclass 39, count 0 2006.285.12:03:06.60#ibcon#read 5, iclass 39, count 0 2006.285.12:03:06.60#ibcon#about to read 6, iclass 39, count 0 2006.285.12:03:06.60#ibcon#read 6, iclass 39, count 0 2006.285.12:03:06.60#ibcon#end of sib2, iclass 39, count 0 2006.285.12:03:06.60#ibcon#*after write, iclass 39, count 0 2006.285.12:03:06.60#ibcon#*before return 0, iclass 39, count 0 2006.285.12:03:06.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:03:06.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:03:06.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.12:03:06.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.12:03:06.60$vck44/va=7,4 2006.285.12:03:06.60#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.12:03:06.60#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.12:03:06.60#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:06.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:03:06.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:03:06.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:03:06.66#ibcon#enter wrdev, iclass 3, count 2 2006.285.12:03:06.66#ibcon#first serial, iclass 3, count 2 2006.285.12:03:06.66#ibcon#enter sib2, iclass 3, count 2 2006.285.12:03:06.66#ibcon#flushed, iclass 3, count 2 2006.285.12:03:06.66#ibcon#about to write, iclass 3, count 2 2006.285.12:03:06.66#ibcon#wrote, iclass 3, count 2 2006.285.12:03:06.66#ibcon#about to read 3, iclass 3, count 2 2006.285.12:03:06.68#ibcon#read 3, iclass 3, count 2 2006.285.12:03:06.68#ibcon#about to read 4, iclass 3, count 2 2006.285.12:03:06.68#ibcon#read 4, iclass 3, count 2 2006.285.12:03:06.68#ibcon#about to read 5, iclass 3, count 2 2006.285.12:03:06.68#ibcon#read 5, iclass 3, count 2 2006.285.12:03:06.68#ibcon#about to read 6, iclass 3, count 2 2006.285.12:03:06.68#ibcon#read 6, iclass 3, count 2 2006.285.12:03:06.68#ibcon#end of sib2, iclass 3, count 2 2006.285.12:03:06.68#ibcon#*mode == 0, iclass 3, count 2 2006.285.12:03:06.68#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.12:03:06.68#ibcon#[25=AT07-04\r\n] 2006.285.12:03:06.68#ibcon#*before write, iclass 3, count 2 2006.285.12:03:06.68#ibcon#enter sib2, iclass 3, count 2 2006.285.12:03:06.68#ibcon#flushed, iclass 3, count 2 2006.285.12:03:06.68#ibcon#about to write, iclass 3, count 2 2006.285.12:03:06.68#ibcon#wrote, iclass 3, count 2 2006.285.12:03:06.68#ibcon#about to read 3, iclass 3, count 2 2006.285.12:03:06.71#ibcon#read 3, iclass 3, count 2 2006.285.12:03:06.71#ibcon#about to read 4, iclass 3, count 2 2006.285.12:03:06.71#ibcon#read 4, iclass 3, count 2 2006.285.12:03:06.71#ibcon#about to read 5, iclass 3, count 2 2006.285.12:03:06.71#ibcon#read 5, iclass 3, count 2 2006.285.12:03:06.71#ibcon#about to read 6, iclass 3, count 2 2006.285.12:03:06.71#ibcon#read 6, iclass 3, count 2 2006.285.12:03:06.71#ibcon#end of sib2, iclass 3, count 2 2006.285.12:03:06.71#ibcon#*after write, iclass 3, count 2 2006.285.12:03:06.71#ibcon#*before return 0, iclass 3, count 2 2006.285.12:03:06.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:03:06.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:03:06.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.12:03:06.71#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:06.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:03:06.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:03:06.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:03:06.83#ibcon#enter wrdev, iclass 3, count 0 2006.285.12:03:06.83#ibcon#first serial, iclass 3, count 0 2006.285.12:03:06.83#ibcon#enter sib2, iclass 3, count 0 2006.285.12:03:06.83#ibcon#flushed, iclass 3, count 0 2006.285.12:03:06.83#ibcon#about to write, iclass 3, count 0 2006.285.12:03:06.83#ibcon#wrote, iclass 3, count 0 2006.285.12:03:06.83#ibcon#about to read 3, iclass 3, count 0 2006.285.12:03:06.85#ibcon#read 3, iclass 3, count 0 2006.285.12:03:06.85#ibcon#about to read 4, iclass 3, count 0 2006.285.12:03:06.85#ibcon#read 4, iclass 3, count 0 2006.285.12:03:06.85#ibcon#about to read 5, iclass 3, count 0 2006.285.12:03:06.85#ibcon#read 5, iclass 3, count 0 2006.285.12:03:06.85#ibcon#about to read 6, iclass 3, count 0 2006.285.12:03:06.85#ibcon#read 6, iclass 3, count 0 2006.285.12:03:06.85#ibcon#end of sib2, iclass 3, count 0 2006.285.12:03:06.85#ibcon#*mode == 0, iclass 3, count 0 2006.285.12:03:06.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.12:03:06.85#ibcon#[25=USB\r\n] 2006.285.12:03:06.85#ibcon#*before write, iclass 3, count 0 2006.285.12:03:06.85#ibcon#enter sib2, iclass 3, count 0 2006.285.12:03:06.85#ibcon#flushed, iclass 3, count 0 2006.285.12:03:06.85#ibcon#about to write, iclass 3, count 0 2006.285.12:03:06.85#ibcon#wrote, iclass 3, count 0 2006.285.12:03:06.85#ibcon#about to read 3, iclass 3, count 0 2006.285.12:03:06.88#ibcon#read 3, iclass 3, count 0 2006.285.12:03:06.88#ibcon#about to read 4, iclass 3, count 0 2006.285.12:03:06.88#ibcon#read 4, iclass 3, count 0 2006.285.12:03:06.88#ibcon#about to read 5, iclass 3, count 0 2006.285.12:03:06.88#ibcon#read 5, iclass 3, count 0 2006.285.12:03:06.88#ibcon#about to read 6, iclass 3, count 0 2006.285.12:03:06.88#ibcon#read 6, iclass 3, count 0 2006.285.12:03:06.88#ibcon#end of sib2, iclass 3, count 0 2006.285.12:03:06.88#ibcon#*after write, iclass 3, count 0 2006.285.12:03:06.88#ibcon#*before return 0, iclass 3, count 0 2006.285.12:03:06.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:03:06.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:03:06.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.12:03:06.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.12:03:06.88$vck44/valo=8,884.99 2006.285.12:03:06.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.12:03:06.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.12:03:06.88#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:06.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:03:06.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:03:06.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:03:06.88#ibcon#enter wrdev, iclass 5, count 0 2006.285.12:03:06.88#ibcon#first serial, iclass 5, count 0 2006.285.12:03:06.88#ibcon#enter sib2, iclass 5, count 0 2006.285.12:03:06.88#ibcon#flushed, iclass 5, count 0 2006.285.12:03:06.88#ibcon#about to write, iclass 5, count 0 2006.285.12:03:06.88#ibcon#wrote, iclass 5, count 0 2006.285.12:03:06.88#ibcon#about to read 3, iclass 5, count 0 2006.285.12:03:06.90#ibcon#read 3, iclass 5, count 0 2006.285.12:03:06.90#ibcon#about to read 4, iclass 5, count 0 2006.285.12:03:06.90#ibcon#read 4, iclass 5, count 0 2006.285.12:03:06.90#ibcon#about to read 5, iclass 5, count 0 2006.285.12:03:06.90#ibcon#read 5, iclass 5, count 0 2006.285.12:03:06.90#ibcon#about to read 6, iclass 5, count 0 2006.285.12:03:06.90#ibcon#read 6, iclass 5, count 0 2006.285.12:03:06.90#ibcon#end of sib2, iclass 5, count 0 2006.285.12:03:06.90#ibcon#*mode == 0, iclass 5, count 0 2006.285.12:03:06.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.12:03:06.90#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.12:03:06.90#ibcon#*before write, iclass 5, count 0 2006.285.12:03:06.90#ibcon#enter sib2, iclass 5, count 0 2006.285.12:03:06.90#ibcon#flushed, iclass 5, count 0 2006.285.12:03:06.90#ibcon#about to write, iclass 5, count 0 2006.285.12:03:06.90#ibcon#wrote, iclass 5, count 0 2006.285.12:03:06.90#ibcon#about to read 3, iclass 5, count 0 2006.285.12:03:06.94#ibcon#read 3, iclass 5, count 0 2006.285.12:03:06.94#ibcon#about to read 4, iclass 5, count 0 2006.285.12:03:06.94#ibcon#read 4, iclass 5, count 0 2006.285.12:03:06.94#ibcon#about to read 5, iclass 5, count 0 2006.285.12:03:06.94#ibcon#read 5, iclass 5, count 0 2006.285.12:03:06.94#ibcon#about to read 6, iclass 5, count 0 2006.285.12:03:06.94#ibcon#read 6, iclass 5, count 0 2006.285.12:03:06.94#ibcon#end of sib2, iclass 5, count 0 2006.285.12:03:06.94#ibcon#*after write, iclass 5, count 0 2006.285.12:03:06.94#ibcon#*before return 0, iclass 5, count 0 2006.285.12:03:06.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:03:06.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:03:06.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.12:03:06.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.12:03:06.94$vck44/va=8,3 2006.285.12:03:06.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.12:03:06.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.12:03:06.94#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:06.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:03:07.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:03:07.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:03:07.00#ibcon#enter wrdev, iclass 7, count 2 2006.285.12:03:07.00#ibcon#first serial, iclass 7, count 2 2006.285.12:03:07.00#ibcon#enter sib2, iclass 7, count 2 2006.285.12:03:07.00#ibcon#flushed, iclass 7, count 2 2006.285.12:03:07.00#ibcon#about to write, iclass 7, count 2 2006.285.12:03:07.00#ibcon#wrote, iclass 7, count 2 2006.285.12:03:07.00#ibcon#about to read 3, iclass 7, count 2 2006.285.12:03:07.02#ibcon#read 3, iclass 7, count 2 2006.285.12:03:07.02#ibcon#about to read 4, iclass 7, count 2 2006.285.12:03:07.02#ibcon#read 4, iclass 7, count 2 2006.285.12:03:07.02#ibcon#about to read 5, iclass 7, count 2 2006.285.12:03:07.02#ibcon#read 5, iclass 7, count 2 2006.285.12:03:07.02#ibcon#about to read 6, iclass 7, count 2 2006.285.12:03:07.02#ibcon#read 6, iclass 7, count 2 2006.285.12:03:07.02#ibcon#end of sib2, iclass 7, count 2 2006.285.12:03:07.02#ibcon#*mode == 0, iclass 7, count 2 2006.285.12:03:07.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.12:03:07.02#ibcon#[25=AT08-03\r\n] 2006.285.12:03:07.02#ibcon#*before write, iclass 7, count 2 2006.285.12:03:07.02#ibcon#enter sib2, iclass 7, count 2 2006.285.12:03:07.02#ibcon#flushed, iclass 7, count 2 2006.285.12:03:07.02#ibcon#about to write, iclass 7, count 2 2006.285.12:03:07.02#ibcon#wrote, iclass 7, count 2 2006.285.12:03:07.02#ibcon#about to read 3, iclass 7, count 2 2006.285.12:03:07.05#ibcon#read 3, iclass 7, count 2 2006.285.12:03:07.05#ibcon#about to read 4, iclass 7, count 2 2006.285.12:03:07.05#ibcon#read 4, iclass 7, count 2 2006.285.12:03:07.05#ibcon#about to read 5, iclass 7, count 2 2006.285.12:03:07.05#ibcon#read 5, iclass 7, count 2 2006.285.12:03:07.05#ibcon#about to read 6, iclass 7, count 2 2006.285.12:03:07.05#ibcon#read 6, iclass 7, count 2 2006.285.12:03:07.05#ibcon#end of sib2, iclass 7, count 2 2006.285.12:03:07.05#ibcon#*after write, iclass 7, count 2 2006.285.12:03:07.05#ibcon#*before return 0, iclass 7, count 2 2006.285.12:03:07.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:03:07.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:03:07.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.12:03:07.05#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:07.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:03:07.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:03:07.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:03:07.17#ibcon#enter wrdev, iclass 7, count 0 2006.285.12:03:07.17#ibcon#first serial, iclass 7, count 0 2006.285.12:03:07.17#ibcon#enter sib2, iclass 7, count 0 2006.285.12:03:07.17#ibcon#flushed, iclass 7, count 0 2006.285.12:03:07.17#ibcon#about to write, iclass 7, count 0 2006.285.12:03:07.17#ibcon#wrote, iclass 7, count 0 2006.285.12:03:07.17#ibcon#about to read 3, iclass 7, count 0 2006.285.12:03:07.19#ibcon#read 3, iclass 7, count 0 2006.285.12:03:07.19#ibcon#about to read 4, iclass 7, count 0 2006.285.12:03:07.19#ibcon#read 4, iclass 7, count 0 2006.285.12:03:07.19#ibcon#about to read 5, iclass 7, count 0 2006.285.12:03:07.19#ibcon#read 5, iclass 7, count 0 2006.285.12:03:07.19#ibcon#about to read 6, iclass 7, count 0 2006.285.12:03:07.19#ibcon#read 6, iclass 7, count 0 2006.285.12:03:07.19#ibcon#end of sib2, iclass 7, count 0 2006.285.12:03:07.19#ibcon#*mode == 0, iclass 7, count 0 2006.285.12:03:07.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.12:03:07.19#ibcon#[25=USB\r\n] 2006.285.12:03:07.19#ibcon#*before write, iclass 7, count 0 2006.285.12:03:07.19#ibcon#enter sib2, iclass 7, count 0 2006.285.12:03:07.19#ibcon#flushed, iclass 7, count 0 2006.285.12:03:07.19#ibcon#about to write, iclass 7, count 0 2006.285.12:03:07.19#ibcon#wrote, iclass 7, count 0 2006.285.12:03:07.19#ibcon#about to read 3, iclass 7, count 0 2006.285.12:03:07.22#ibcon#read 3, iclass 7, count 0 2006.285.12:03:07.22#ibcon#about to read 4, iclass 7, count 0 2006.285.12:03:07.22#ibcon#read 4, iclass 7, count 0 2006.285.12:03:07.22#ibcon#about to read 5, iclass 7, count 0 2006.285.12:03:07.22#ibcon#read 5, iclass 7, count 0 2006.285.12:03:07.22#ibcon#about to read 6, iclass 7, count 0 2006.285.12:03:07.22#ibcon#read 6, iclass 7, count 0 2006.285.12:03:07.22#ibcon#end of sib2, iclass 7, count 0 2006.285.12:03:07.22#ibcon#*after write, iclass 7, count 0 2006.285.12:03:07.22#ibcon#*before return 0, iclass 7, count 0 2006.285.12:03:07.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:03:07.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:03:07.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.12:03:07.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.12:03:07.22$vck44/vblo=1,629.99 2006.285.12:03:07.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.12:03:07.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.12:03:07.22#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:07.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:03:07.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:03:07.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:03:07.22#ibcon#enter wrdev, iclass 11, count 0 2006.285.12:03:07.22#ibcon#first serial, iclass 11, count 0 2006.285.12:03:07.22#ibcon#enter sib2, iclass 11, count 0 2006.285.12:03:07.22#ibcon#flushed, iclass 11, count 0 2006.285.12:03:07.22#ibcon#about to write, iclass 11, count 0 2006.285.12:03:07.22#ibcon#wrote, iclass 11, count 0 2006.285.12:03:07.22#ibcon#about to read 3, iclass 11, count 0 2006.285.12:03:07.24#ibcon#read 3, iclass 11, count 0 2006.285.12:03:07.24#ibcon#about to read 4, iclass 11, count 0 2006.285.12:03:07.24#ibcon#read 4, iclass 11, count 0 2006.285.12:03:07.24#ibcon#about to read 5, iclass 11, count 0 2006.285.12:03:07.24#ibcon#read 5, iclass 11, count 0 2006.285.12:03:07.24#ibcon#about to read 6, iclass 11, count 0 2006.285.12:03:07.24#ibcon#read 6, iclass 11, count 0 2006.285.12:03:07.24#ibcon#end of sib2, iclass 11, count 0 2006.285.12:03:07.24#ibcon#*mode == 0, iclass 11, count 0 2006.285.12:03:07.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.12:03:07.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.12:03:07.24#ibcon#*before write, iclass 11, count 0 2006.285.12:03:07.24#ibcon#enter sib2, iclass 11, count 0 2006.285.12:03:07.24#ibcon#flushed, iclass 11, count 0 2006.285.12:03:07.24#ibcon#about to write, iclass 11, count 0 2006.285.12:03:07.24#ibcon#wrote, iclass 11, count 0 2006.285.12:03:07.24#ibcon#about to read 3, iclass 11, count 0 2006.285.12:03:07.28#ibcon#read 3, iclass 11, count 0 2006.285.12:03:07.28#ibcon#about to read 4, iclass 11, count 0 2006.285.12:03:07.28#ibcon#read 4, iclass 11, count 0 2006.285.12:03:07.28#ibcon#about to read 5, iclass 11, count 0 2006.285.12:03:07.28#ibcon#read 5, iclass 11, count 0 2006.285.12:03:07.28#ibcon#about to read 6, iclass 11, count 0 2006.285.12:03:07.28#ibcon#read 6, iclass 11, count 0 2006.285.12:03:07.28#ibcon#end of sib2, iclass 11, count 0 2006.285.12:03:07.28#ibcon#*after write, iclass 11, count 0 2006.285.12:03:07.28#ibcon#*before return 0, iclass 11, count 0 2006.285.12:03:07.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:03:07.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:03:07.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.12:03:07.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.12:03:07.28$vck44/vb=1,4 2006.285.12:03:07.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.12:03:07.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.12:03:07.28#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:07.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:03:07.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:03:07.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:03:07.28#ibcon#enter wrdev, iclass 13, count 2 2006.285.12:03:07.28#ibcon#first serial, iclass 13, count 2 2006.285.12:03:07.28#ibcon#enter sib2, iclass 13, count 2 2006.285.12:03:07.28#ibcon#flushed, iclass 13, count 2 2006.285.12:03:07.28#ibcon#about to write, iclass 13, count 2 2006.285.12:03:07.28#ibcon#wrote, iclass 13, count 2 2006.285.12:03:07.28#ibcon#about to read 3, iclass 13, count 2 2006.285.12:03:07.30#ibcon#read 3, iclass 13, count 2 2006.285.12:03:07.30#ibcon#about to read 4, iclass 13, count 2 2006.285.12:03:07.30#ibcon#read 4, iclass 13, count 2 2006.285.12:03:07.30#ibcon#about to read 5, iclass 13, count 2 2006.285.12:03:07.30#ibcon#read 5, iclass 13, count 2 2006.285.12:03:07.30#ibcon#about to read 6, iclass 13, count 2 2006.285.12:03:07.30#ibcon#read 6, iclass 13, count 2 2006.285.12:03:07.30#ibcon#end of sib2, iclass 13, count 2 2006.285.12:03:07.30#ibcon#*mode == 0, iclass 13, count 2 2006.285.12:03:07.30#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.12:03:07.30#ibcon#[27=AT01-04\r\n] 2006.285.12:03:07.30#ibcon#*before write, iclass 13, count 2 2006.285.12:03:07.30#ibcon#enter sib2, iclass 13, count 2 2006.285.12:03:07.30#ibcon#flushed, iclass 13, count 2 2006.285.12:03:07.30#ibcon#about to write, iclass 13, count 2 2006.285.12:03:07.30#ibcon#wrote, iclass 13, count 2 2006.285.12:03:07.30#ibcon#about to read 3, iclass 13, count 2 2006.285.12:03:07.33#ibcon#read 3, iclass 13, count 2 2006.285.12:03:07.33#ibcon#about to read 4, iclass 13, count 2 2006.285.12:03:07.33#ibcon#read 4, iclass 13, count 2 2006.285.12:03:07.33#ibcon#about to read 5, iclass 13, count 2 2006.285.12:03:07.33#ibcon#read 5, iclass 13, count 2 2006.285.12:03:07.33#ibcon#about to read 6, iclass 13, count 2 2006.285.12:03:07.33#ibcon#read 6, iclass 13, count 2 2006.285.12:03:07.33#ibcon#end of sib2, iclass 13, count 2 2006.285.12:03:07.33#ibcon#*after write, iclass 13, count 2 2006.285.12:03:07.33#ibcon#*before return 0, iclass 13, count 2 2006.285.12:03:07.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:03:07.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:03:07.33#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.12:03:07.33#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:07.33#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:03:07.45#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:03:07.45#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:03:07.45#ibcon#enter wrdev, iclass 13, count 0 2006.285.12:03:07.45#ibcon#first serial, iclass 13, count 0 2006.285.12:03:07.45#ibcon#enter sib2, iclass 13, count 0 2006.285.12:03:07.45#ibcon#flushed, iclass 13, count 0 2006.285.12:03:07.45#ibcon#about to write, iclass 13, count 0 2006.285.12:03:07.45#ibcon#wrote, iclass 13, count 0 2006.285.12:03:07.45#ibcon#about to read 3, iclass 13, count 0 2006.285.12:03:07.47#ibcon#read 3, iclass 13, count 0 2006.285.12:03:07.47#ibcon#about to read 4, iclass 13, count 0 2006.285.12:03:07.47#ibcon#read 4, iclass 13, count 0 2006.285.12:03:07.47#ibcon#about to read 5, iclass 13, count 0 2006.285.12:03:07.47#ibcon#read 5, iclass 13, count 0 2006.285.12:03:07.47#ibcon#about to read 6, iclass 13, count 0 2006.285.12:03:07.47#ibcon#read 6, iclass 13, count 0 2006.285.12:03:07.47#ibcon#end of sib2, iclass 13, count 0 2006.285.12:03:07.47#ibcon#*mode == 0, iclass 13, count 0 2006.285.12:03:07.47#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.12:03:07.47#ibcon#[27=USB\r\n] 2006.285.12:03:07.47#ibcon#*before write, iclass 13, count 0 2006.285.12:03:07.47#ibcon#enter sib2, iclass 13, count 0 2006.285.12:03:07.47#ibcon#flushed, iclass 13, count 0 2006.285.12:03:07.47#ibcon#about to write, iclass 13, count 0 2006.285.12:03:07.47#ibcon#wrote, iclass 13, count 0 2006.285.12:03:07.47#ibcon#about to read 3, iclass 13, count 0 2006.285.12:03:07.50#ibcon#read 3, iclass 13, count 0 2006.285.12:03:07.50#ibcon#about to read 4, iclass 13, count 0 2006.285.12:03:07.50#ibcon#read 4, iclass 13, count 0 2006.285.12:03:07.50#ibcon#about to read 5, iclass 13, count 0 2006.285.12:03:07.50#ibcon#read 5, iclass 13, count 0 2006.285.12:03:07.50#ibcon#about to read 6, iclass 13, count 0 2006.285.12:03:07.50#ibcon#read 6, iclass 13, count 0 2006.285.12:03:07.50#ibcon#end of sib2, iclass 13, count 0 2006.285.12:03:07.50#ibcon#*after write, iclass 13, count 0 2006.285.12:03:07.50#ibcon#*before return 0, iclass 13, count 0 2006.285.12:03:07.50#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:03:07.50#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:03:07.50#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.12:03:07.50#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.12:03:07.50$vck44/vblo=2,634.99 2006.285.12:03:07.50#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.12:03:07.50#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.12:03:07.50#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:07.50#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:03:07.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:03:07.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:03:07.50#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:03:07.50#ibcon#first serial, iclass 15, count 0 2006.285.12:03:07.50#ibcon#enter sib2, iclass 15, count 0 2006.285.12:03:07.50#ibcon#flushed, iclass 15, count 0 2006.285.12:03:07.50#ibcon#about to write, iclass 15, count 0 2006.285.12:03:07.50#ibcon#wrote, iclass 15, count 0 2006.285.12:03:07.50#ibcon#about to read 3, iclass 15, count 0 2006.285.12:03:07.52#ibcon#read 3, iclass 15, count 0 2006.285.12:03:07.52#ibcon#about to read 4, iclass 15, count 0 2006.285.12:03:07.52#ibcon#read 4, iclass 15, count 0 2006.285.12:03:07.52#ibcon#about to read 5, iclass 15, count 0 2006.285.12:03:07.52#ibcon#read 5, iclass 15, count 0 2006.285.12:03:07.52#ibcon#about to read 6, iclass 15, count 0 2006.285.12:03:07.52#ibcon#read 6, iclass 15, count 0 2006.285.12:03:07.52#ibcon#end of sib2, iclass 15, count 0 2006.285.12:03:07.52#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:03:07.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:03:07.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.12:03:07.52#ibcon#*before write, iclass 15, count 0 2006.285.12:03:07.52#ibcon#enter sib2, iclass 15, count 0 2006.285.12:03:07.52#ibcon#flushed, iclass 15, count 0 2006.285.12:03:07.52#ibcon#about to write, iclass 15, count 0 2006.285.12:03:07.52#ibcon#wrote, iclass 15, count 0 2006.285.12:03:07.52#ibcon#about to read 3, iclass 15, count 0 2006.285.12:03:07.56#ibcon#read 3, iclass 15, count 0 2006.285.12:03:07.56#ibcon#about to read 4, iclass 15, count 0 2006.285.12:03:07.56#ibcon#read 4, iclass 15, count 0 2006.285.12:03:07.56#ibcon#about to read 5, iclass 15, count 0 2006.285.12:03:07.56#ibcon#read 5, iclass 15, count 0 2006.285.12:03:07.56#ibcon#about to read 6, iclass 15, count 0 2006.285.12:03:07.56#ibcon#read 6, iclass 15, count 0 2006.285.12:03:07.56#ibcon#end of sib2, iclass 15, count 0 2006.285.12:03:07.56#ibcon#*after write, iclass 15, count 0 2006.285.12:03:07.56#ibcon#*before return 0, iclass 15, count 0 2006.285.12:03:07.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:03:07.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:03:07.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:03:07.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:03:07.56$vck44/vb=2,5 2006.285.12:03:07.56#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.12:03:07.56#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.12:03:07.56#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:07.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:03:07.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:03:07.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:03:07.62#ibcon#enter wrdev, iclass 17, count 2 2006.285.12:03:07.62#ibcon#first serial, iclass 17, count 2 2006.285.12:03:07.62#ibcon#enter sib2, iclass 17, count 2 2006.285.12:03:07.62#ibcon#flushed, iclass 17, count 2 2006.285.12:03:07.62#ibcon#about to write, iclass 17, count 2 2006.285.12:03:07.62#ibcon#wrote, iclass 17, count 2 2006.285.12:03:07.62#ibcon#about to read 3, iclass 17, count 2 2006.285.12:03:07.64#ibcon#read 3, iclass 17, count 2 2006.285.12:03:07.64#ibcon#about to read 4, iclass 17, count 2 2006.285.12:03:07.64#ibcon#read 4, iclass 17, count 2 2006.285.12:03:07.64#ibcon#about to read 5, iclass 17, count 2 2006.285.12:03:07.64#ibcon#read 5, iclass 17, count 2 2006.285.12:03:07.64#ibcon#about to read 6, iclass 17, count 2 2006.285.12:03:07.64#ibcon#read 6, iclass 17, count 2 2006.285.12:03:07.64#ibcon#end of sib2, iclass 17, count 2 2006.285.12:03:07.64#ibcon#*mode == 0, iclass 17, count 2 2006.285.12:03:07.64#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.12:03:07.64#ibcon#[27=AT02-05\r\n] 2006.285.12:03:07.64#ibcon#*before write, iclass 17, count 2 2006.285.12:03:07.64#ibcon#enter sib2, iclass 17, count 2 2006.285.12:03:07.64#ibcon#flushed, iclass 17, count 2 2006.285.12:03:07.64#ibcon#about to write, iclass 17, count 2 2006.285.12:03:07.64#ibcon#wrote, iclass 17, count 2 2006.285.12:03:07.64#ibcon#about to read 3, iclass 17, count 2 2006.285.12:03:07.67#ibcon#read 3, iclass 17, count 2 2006.285.12:03:07.67#ibcon#about to read 4, iclass 17, count 2 2006.285.12:03:07.67#ibcon#read 4, iclass 17, count 2 2006.285.12:03:07.67#ibcon#about to read 5, iclass 17, count 2 2006.285.12:03:07.67#ibcon#read 5, iclass 17, count 2 2006.285.12:03:07.67#ibcon#about to read 6, iclass 17, count 2 2006.285.12:03:07.67#ibcon#read 6, iclass 17, count 2 2006.285.12:03:07.67#ibcon#end of sib2, iclass 17, count 2 2006.285.12:03:07.67#ibcon#*after write, iclass 17, count 2 2006.285.12:03:07.67#ibcon#*before return 0, iclass 17, count 2 2006.285.12:03:07.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:03:07.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:03:07.67#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.12:03:07.67#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:07.67#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:03:07.79#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:03:07.79#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:03:07.79#ibcon#enter wrdev, iclass 17, count 0 2006.285.12:03:07.79#ibcon#first serial, iclass 17, count 0 2006.285.12:03:07.79#ibcon#enter sib2, iclass 17, count 0 2006.285.12:03:07.79#ibcon#flushed, iclass 17, count 0 2006.285.12:03:07.79#ibcon#about to write, iclass 17, count 0 2006.285.12:03:07.79#ibcon#wrote, iclass 17, count 0 2006.285.12:03:07.79#ibcon#about to read 3, iclass 17, count 0 2006.285.12:03:07.81#ibcon#read 3, iclass 17, count 0 2006.285.12:03:07.81#ibcon#about to read 4, iclass 17, count 0 2006.285.12:03:07.81#ibcon#read 4, iclass 17, count 0 2006.285.12:03:07.81#ibcon#about to read 5, iclass 17, count 0 2006.285.12:03:07.81#ibcon#read 5, iclass 17, count 0 2006.285.12:03:07.81#ibcon#about to read 6, iclass 17, count 0 2006.285.12:03:07.81#ibcon#read 6, iclass 17, count 0 2006.285.12:03:07.81#ibcon#end of sib2, iclass 17, count 0 2006.285.12:03:07.81#ibcon#*mode == 0, iclass 17, count 0 2006.285.12:03:07.81#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.12:03:07.81#ibcon#[27=USB\r\n] 2006.285.12:03:07.81#ibcon#*before write, iclass 17, count 0 2006.285.12:03:07.81#ibcon#enter sib2, iclass 17, count 0 2006.285.12:03:07.81#ibcon#flushed, iclass 17, count 0 2006.285.12:03:07.81#ibcon#about to write, iclass 17, count 0 2006.285.12:03:07.81#ibcon#wrote, iclass 17, count 0 2006.285.12:03:07.81#ibcon#about to read 3, iclass 17, count 0 2006.285.12:03:07.84#ibcon#read 3, iclass 17, count 0 2006.285.12:03:07.84#ibcon#about to read 4, iclass 17, count 0 2006.285.12:03:07.84#ibcon#read 4, iclass 17, count 0 2006.285.12:03:07.84#ibcon#about to read 5, iclass 17, count 0 2006.285.12:03:07.84#ibcon#read 5, iclass 17, count 0 2006.285.12:03:07.84#ibcon#about to read 6, iclass 17, count 0 2006.285.12:03:07.84#ibcon#read 6, iclass 17, count 0 2006.285.12:03:07.84#ibcon#end of sib2, iclass 17, count 0 2006.285.12:03:07.84#ibcon#*after write, iclass 17, count 0 2006.285.12:03:07.84#ibcon#*before return 0, iclass 17, count 0 2006.285.12:03:07.84#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:03:07.84#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:03:07.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.12:03:07.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.12:03:07.84$vck44/vblo=3,649.99 2006.285.12:03:07.84#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.12:03:07.84#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.12:03:07.84#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:07.84#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:03:07.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:03:07.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:03:07.84#ibcon#enter wrdev, iclass 19, count 0 2006.285.12:03:07.84#ibcon#first serial, iclass 19, count 0 2006.285.12:03:07.84#ibcon#enter sib2, iclass 19, count 0 2006.285.12:03:07.84#ibcon#flushed, iclass 19, count 0 2006.285.12:03:07.84#ibcon#about to write, iclass 19, count 0 2006.285.12:03:07.84#ibcon#wrote, iclass 19, count 0 2006.285.12:03:07.84#ibcon#about to read 3, iclass 19, count 0 2006.285.12:03:07.86#ibcon#read 3, iclass 19, count 0 2006.285.12:03:07.86#ibcon#about to read 4, iclass 19, count 0 2006.285.12:03:07.86#ibcon#read 4, iclass 19, count 0 2006.285.12:03:07.86#ibcon#about to read 5, iclass 19, count 0 2006.285.12:03:07.86#ibcon#read 5, iclass 19, count 0 2006.285.12:03:07.86#ibcon#about to read 6, iclass 19, count 0 2006.285.12:03:07.86#ibcon#read 6, iclass 19, count 0 2006.285.12:03:07.86#ibcon#end of sib2, iclass 19, count 0 2006.285.12:03:07.86#ibcon#*mode == 0, iclass 19, count 0 2006.285.12:03:07.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.12:03:07.86#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.12:03:07.86#ibcon#*before write, iclass 19, count 0 2006.285.12:03:07.86#ibcon#enter sib2, iclass 19, count 0 2006.285.12:03:07.86#ibcon#flushed, iclass 19, count 0 2006.285.12:03:07.86#ibcon#about to write, iclass 19, count 0 2006.285.12:03:07.86#ibcon#wrote, iclass 19, count 0 2006.285.12:03:07.86#ibcon#about to read 3, iclass 19, count 0 2006.285.12:03:07.90#ibcon#read 3, iclass 19, count 0 2006.285.12:03:07.90#ibcon#about to read 4, iclass 19, count 0 2006.285.12:03:07.90#ibcon#read 4, iclass 19, count 0 2006.285.12:03:07.90#ibcon#about to read 5, iclass 19, count 0 2006.285.12:03:07.90#ibcon#read 5, iclass 19, count 0 2006.285.12:03:07.90#ibcon#about to read 6, iclass 19, count 0 2006.285.12:03:07.90#ibcon#read 6, iclass 19, count 0 2006.285.12:03:07.90#ibcon#end of sib2, iclass 19, count 0 2006.285.12:03:07.90#ibcon#*after write, iclass 19, count 0 2006.285.12:03:07.90#ibcon#*before return 0, iclass 19, count 0 2006.285.12:03:07.90#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:03:07.90#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:03:07.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.12:03:07.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.12:03:07.90$vck44/vb=3,4 2006.285.12:03:07.90#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.12:03:07.90#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.12:03:07.90#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:07.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:03:07.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:03:07.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:03:07.96#ibcon#enter wrdev, iclass 21, count 2 2006.285.12:03:07.96#ibcon#first serial, iclass 21, count 2 2006.285.12:03:07.96#ibcon#enter sib2, iclass 21, count 2 2006.285.12:03:07.96#ibcon#flushed, iclass 21, count 2 2006.285.12:03:07.96#ibcon#about to write, iclass 21, count 2 2006.285.12:03:07.96#ibcon#wrote, iclass 21, count 2 2006.285.12:03:07.96#ibcon#about to read 3, iclass 21, count 2 2006.285.12:03:07.98#ibcon#read 3, iclass 21, count 2 2006.285.12:03:07.98#ibcon#about to read 4, iclass 21, count 2 2006.285.12:03:07.98#ibcon#read 4, iclass 21, count 2 2006.285.12:03:07.98#ibcon#about to read 5, iclass 21, count 2 2006.285.12:03:07.98#ibcon#read 5, iclass 21, count 2 2006.285.12:03:07.98#ibcon#about to read 6, iclass 21, count 2 2006.285.12:03:07.98#ibcon#read 6, iclass 21, count 2 2006.285.12:03:07.98#ibcon#end of sib2, iclass 21, count 2 2006.285.12:03:07.98#ibcon#*mode == 0, iclass 21, count 2 2006.285.12:03:07.98#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.12:03:07.98#ibcon#[27=AT03-04\r\n] 2006.285.12:03:07.98#ibcon#*before write, iclass 21, count 2 2006.285.12:03:07.98#ibcon#enter sib2, iclass 21, count 2 2006.285.12:03:07.98#ibcon#flushed, iclass 21, count 2 2006.285.12:03:07.98#ibcon#about to write, iclass 21, count 2 2006.285.12:03:07.98#ibcon#wrote, iclass 21, count 2 2006.285.12:03:07.98#ibcon#about to read 3, iclass 21, count 2 2006.285.12:03:08.01#ibcon#read 3, iclass 21, count 2 2006.285.12:03:08.01#ibcon#about to read 4, iclass 21, count 2 2006.285.12:03:08.01#ibcon#read 4, iclass 21, count 2 2006.285.12:03:08.01#ibcon#about to read 5, iclass 21, count 2 2006.285.12:03:08.01#ibcon#read 5, iclass 21, count 2 2006.285.12:03:08.01#ibcon#about to read 6, iclass 21, count 2 2006.285.12:03:08.01#ibcon#read 6, iclass 21, count 2 2006.285.12:03:08.01#ibcon#end of sib2, iclass 21, count 2 2006.285.12:03:08.01#ibcon#*after write, iclass 21, count 2 2006.285.12:03:08.01#ibcon#*before return 0, iclass 21, count 2 2006.285.12:03:08.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:03:08.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:03:08.01#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.12:03:08.01#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:08.01#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:03:08.13#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:03:08.13#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:03:08.13#ibcon#enter wrdev, iclass 21, count 0 2006.285.12:03:08.13#ibcon#first serial, iclass 21, count 0 2006.285.12:03:08.13#ibcon#enter sib2, iclass 21, count 0 2006.285.12:03:08.13#ibcon#flushed, iclass 21, count 0 2006.285.12:03:08.13#ibcon#about to write, iclass 21, count 0 2006.285.12:03:08.13#ibcon#wrote, iclass 21, count 0 2006.285.12:03:08.13#ibcon#about to read 3, iclass 21, count 0 2006.285.12:03:08.15#ibcon#read 3, iclass 21, count 0 2006.285.12:03:08.15#ibcon#about to read 4, iclass 21, count 0 2006.285.12:03:08.15#ibcon#read 4, iclass 21, count 0 2006.285.12:03:08.15#ibcon#about to read 5, iclass 21, count 0 2006.285.12:03:08.15#ibcon#read 5, iclass 21, count 0 2006.285.12:03:08.15#ibcon#about to read 6, iclass 21, count 0 2006.285.12:03:08.15#ibcon#read 6, iclass 21, count 0 2006.285.12:03:08.15#ibcon#end of sib2, iclass 21, count 0 2006.285.12:03:08.15#ibcon#*mode == 0, iclass 21, count 0 2006.285.12:03:08.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.12:03:08.15#ibcon#[27=USB\r\n] 2006.285.12:03:08.15#ibcon#*before write, iclass 21, count 0 2006.285.12:03:08.15#ibcon#enter sib2, iclass 21, count 0 2006.285.12:03:08.15#ibcon#flushed, iclass 21, count 0 2006.285.12:03:08.15#ibcon#about to write, iclass 21, count 0 2006.285.12:03:08.15#ibcon#wrote, iclass 21, count 0 2006.285.12:03:08.15#ibcon#about to read 3, iclass 21, count 0 2006.285.12:03:08.18#ibcon#read 3, iclass 21, count 0 2006.285.12:03:08.18#ibcon#about to read 4, iclass 21, count 0 2006.285.12:03:08.18#ibcon#read 4, iclass 21, count 0 2006.285.12:03:08.18#ibcon#about to read 5, iclass 21, count 0 2006.285.12:03:08.18#ibcon#read 5, iclass 21, count 0 2006.285.12:03:08.18#ibcon#about to read 6, iclass 21, count 0 2006.285.12:03:08.18#ibcon#read 6, iclass 21, count 0 2006.285.12:03:08.18#ibcon#end of sib2, iclass 21, count 0 2006.285.12:03:08.18#ibcon#*after write, iclass 21, count 0 2006.285.12:03:08.18#ibcon#*before return 0, iclass 21, count 0 2006.285.12:03:08.18#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:03:08.18#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:03:08.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.12:03:08.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.12:03:08.18$vck44/vblo=4,679.99 2006.285.12:03:08.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.12:03:08.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.12:03:08.18#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:08.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:03:08.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:03:08.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:03:08.18#ibcon#enter wrdev, iclass 23, count 0 2006.285.12:03:08.18#ibcon#first serial, iclass 23, count 0 2006.285.12:03:08.18#ibcon#enter sib2, iclass 23, count 0 2006.285.12:03:08.18#ibcon#flushed, iclass 23, count 0 2006.285.12:03:08.18#ibcon#about to write, iclass 23, count 0 2006.285.12:03:08.18#ibcon#wrote, iclass 23, count 0 2006.285.12:03:08.18#ibcon#about to read 3, iclass 23, count 0 2006.285.12:03:08.20#ibcon#read 3, iclass 23, count 0 2006.285.12:03:08.20#ibcon#about to read 4, iclass 23, count 0 2006.285.12:03:08.20#ibcon#read 4, iclass 23, count 0 2006.285.12:03:08.20#ibcon#about to read 5, iclass 23, count 0 2006.285.12:03:08.20#ibcon#read 5, iclass 23, count 0 2006.285.12:03:08.20#ibcon#about to read 6, iclass 23, count 0 2006.285.12:03:08.20#ibcon#read 6, iclass 23, count 0 2006.285.12:03:08.20#ibcon#end of sib2, iclass 23, count 0 2006.285.12:03:08.20#ibcon#*mode == 0, iclass 23, count 0 2006.285.12:03:08.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.12:03:08.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.12:03:08.20#ibcon#*before write, iclass 23, count 0 2006.285.12:03:08.20#ibcon#enter sib2, iclass 23, count 0 2006.285.12:03:08.20#ibcon#flushed, iclass 23, count 0 2006.285.12:03:08.20#ibcon#about to write, iclass 23, count 0 2006.285.12:03:08.20#ibcon#wrote, iclass 23, count 0 2006.285.12:03:08.20#ibcon#about to read 3, iclass 23, count 0 2006.285.12:03:08.24#ibcon#read 3, iclass 23, count 0 2006.285.12:03:08.24#ibcon#about to read 4, iclass 23, count 0 2006.285.12:03:08.24#ibcon#read 4, iclass 23, count 0 2006.285.12:03:08.24#ibcon#about to read 5, iclass 23, count 0 2006.285.12:03:08.24#ibcon#read 5, iclass 23, count 0 2006.285.12:03:08.24#ibcon#about to read 6, iclass 23, count 0 2006.285.12:03:08.24#ibcon#read 6, iclass 23, count 0 2006.285.12:03:08.24#ibcon#end of sib2, iclass 23, count 0 2006.285.12:03:08.24#ibcon#*after write, iclass 23, count 0 2006.285.12:03:08.24#ibcon#*before return 0, iclass 23, count 0 2006.285.12:03:08.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:03:08.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:03:08.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.12:03:08.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.12:03:08.24$vck44/vb=4,5 2006.285.12:03:08.24#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.12:03:08.24#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.12:03:08.24#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:08.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:03:08.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:03:08.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:03:08.30#ibcon#enter wrdev, iclass 25, count 2 2006.285.12:03:08.30#ibcon#first serial, iclass 25, count 2 2006.285.12:03:08.30#ibcon#enter sib2, iclass 25, count 2 2006.285.12:03:08.30#ibcon#flushed, iclass 25, count 2 2006.285.12:03:08.30#ibcon#about to write, iclass 25, count 2 2006.285.12:03:08.30#ibcon#wrote, iclass 25, count 2 2006.285.12:03:08.30#ibcon#about to read 3, iclass 25, count 2 2006.285.12:03:08.32#ibcon#read 3, iclass 25, count 2 2006.285.12:03:08.32#ibcon#about to read 4, iclass 25, count 2 2006.285.12:03:08.32#ibcon#read 4, iclass 25, count 2 2006.285.12:03:08.32#ibcon#about to read 5, iclass 25, count 2 2006.285.12:03:08.32#ibcon#read 5, iclass 25, count 2 2006.285.12:03:08.32#ibcon#about to read 6, iclass 25, count 2 2006.285.12:03:08.32#ibcon#read 6, iclass 25, count 2 2006.285.12:03:08.32#ibcon#end of sib2, iclass 25, count 2 2006.285.12:03:08.32#ibcon#*mode == 0, iclass 25, count 2 2006.285.12:03:08.32#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.12:03:08.32#ibcon#[27=AT04-05\r\n] 2006.285.12:03:08.32#ibcon#*before write, iclass 25, count 2 2006.285.12:03:08.32#ibcon#enter sib2, iclass 25, count 2 2006.285.12:03:08.32#ibcon#flushed, iclass 25, count 2 2006.285.12:03:08.32#ibcon#about to write, iclass 25, count 2 2006.285.12:03:08.32#ibcon#wrote, iclass 25, count 2 2006.285.12:03:08.32#ibcon#about to read 3, iclass 25, count 2 2006.285.12:03:08.35#ibcon#read 3, iclass 25, count 2 2006.285.12:03:08.35#ibcon#about to read 4, iclass 25, count 2 2006.285.12:03:08.35#ibcon#read 4, iclass 25, count 2 2006.285.12:03:08.35#ibcon#about to read 5, iclass 25, count 2 2006.285.12:03:08.35#ibcon#read 5, iclass 25, count 2 2006.285.12:03:08.35#ibcon#about to read 6, iclass 25, count 2 2006.285.12:03:08.35#ibcon#read 6, iclass 25, count 2 2006.285.12:03:08.35#ibcon#end of sib2, iclass 25, count 2 2006.285.12:03:08.35#ibcon#*after write, iclass 25, count 2 2006.285.12:03:08.35#ibcon#*before return 0, iclass 25, count 2 2006.285.12:03:08.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:03:08.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:03:08.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.12:03:08.35#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:08.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:03:08.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:03:08.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:03:08.47#ibcon#enter wrdev, iclass 25, count 0 2006.285.12:03:08.47#ibcon#first serial, iclass 25, count 0 2006.285.12:03:08.47#ibcon#enter sib2, iclass 25, count 0 2006.285.12:03:08.47#ibcon#flushed, iclass 25, count 0 2006.285.12:03:08.47#ibcon#about to write, iclass 25, count 0 2006.285.12:03:08.47#ibcon#wrote, iclass 25, count 0 2006.285.12:03:08.47#ibcon#about to read 3, iclass 25, count 0 2006.285.12:03:08.49#ibcon#read 3, iclass 25, count 0 2006.285.12:03:08.49#ibcon#about to read 4, iclass 25, count 0 2006.285.12:03:08.49#ibcon#read 4, iclass 25, count 0 2006.285.12:03:08.49#ibcon#about to read 5, iclass 25, count 0 2006.285.12:03:08.49#ibcon#read 5, iclass 25, count 0 2006.285.12:03:08.49#ibcon#about to read 6, iclass 25, count 0 2006.285.12:03:08.49#ibcon#read 6, iclass 25, count 0 2006.285.12:03:08.49#ibcon#end of sib2, iclass 25, count 0 2006.285.12:03:08.49#ibcon#*mode == 0, iclass 25, count 0 2006.285.12:03:08.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.12:03:08.49#ibcon#[27=USB\r\n] 2006.285.12:03:08.49#ibcon#*before write, iclass 25, count 0 2006.285.12:03:08.49#ibcon#enter sib2, iclass 25, count 0 2006.285.12:03:08.49#ibcon#flushed, iclass 25, count 0 2006.285.12:03:08.49#ibcon#about to write, iclass 25, count 0 2006.285.12:03:08.49#ibcon#wrote, iclass 25, count 0 2006.285.12:03:08.49#ibcon#about to read 3, iclass 25, count 0 2006.285.12:03:08.52#ibcon#read 3, iclass 25, count 0 2006.285.12:03:08.52#ibcon#about to read 4, iclass 25, count 0 2006.285.12:03:08.52#ibcon#read 4, iclass 25, count 0 2006.285.12:03:08.52#ibcon#about to read 5, iclass 25, count 0 2006.285.12:03:08.52#ibcon#read 5, iclass 25, count 0 2006.285.12:03:08.52#ibcon#about to read 6, iclass 25, count 0 2006.285.12:03:08.52#ibcon#read 6, iclass 25, count 0 2006.285.12:03:08.52#ibcon#end of sib2, iclass 25, count 0 2006.285.12:03:08.52#ibcon#*after write, iclass 25, count 0 2006.285.12:03:08.52#ibcon#*before return 0, iclass 25, count 0 2006.285.12:03:08.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:03:08.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:03:08.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.12:03:08.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.12:03:08.52$vck44/vblo=5,709.99 2006.285.12:03:08.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.12:03:08.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.12:03:08.52#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:08.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:03:08.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:03:08.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:03:08.52#ibcon#enter wrdev, iclass 27, count 0 2006.285.12:03:08.52#ibcon#first serial, iclass 27, count 0 2006.285.12:03:08.52#ibcon#enter sib2, iclass 27, count 0 2006.285.12:03:08.52#ibcon#flushed, iclass 27, count 0 2006.285.12:03:08.52#ibcon#about to write, iclass 27, count 0 2006.285.12:03:08.52#ibcon#wrote, iclass 27, count 0 2006.285.12:03:08.52#ibcon#about to read 3, iclass 27, count 0 2006.285.12:03:08.54#ibcon#read 3, iclass 27, count 0 2006.285.12:03:08.54#ibcon#about to read 4, iclass 27, count 0 2006.285.12:03:08.54#ibcon#read 4, iclass 27, count 0 2006.285.12:03:08.54#ibcon#about to read 5, iclass 27, count 0 2006.285.12:03:08.54#ibcon#read 5, iclass 27, count 0 2006.285.12:03:08.54#ibcon#about to read 6, iclass 27, count 0 2006.285.12:03:08.54#ibcon#read 6, iclass 27, count 0 2006.285.12:03:08.54#ibcon#end of sib2, iclass 27, count 0 2006.285.12:03:08.54#ibcon#*mode == 0, iclass 27, count 0 2006.285.12:03:08.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.12:03:08.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.12:03:08.54#ibcon#*before write, iclass 27, count 0 2006.285.12:03:08.54#ibcon#enter sib2, iclass 27, count 0 2006.285.12:03:08.54#ibcon#flushed, iclass 27, count 0 2006.285.12:03:08.54#ibcon#about to write, iclass 27, count 0 2006.285.12:03:08.54#ibcon#wrote, iclass 27, count 0 2006.285.12:03:08.54#ibcon#about to read 3, iclass 27, count 0 2006.285.12:03:08.58#ibcon#read 3, iclass 27, count 0 2006.285.12:03:08.58#ibcon#about to read 4, iclass 27, count 0 2006.285.12:03:08.58#ibcon#read 4, iclass 27, count 0 2006.285.12:03:08.58#ibcon#about to read 5, iclass 27, count 0 2006.285.12:03:08.58#ibcon#read 5, iclass 27, count 0 2006.285.12:03:08.58#ibcon#about to read 6, iclass 27, count 0 2006.285.12:03:08.58#ibcon#read 6, iclass 27, count 0 2006.285.12:03:08.58#ibcon#end of sib2, iclass 27, count 0 2006.285.12:03:08.58#ibcon#*after write, iclass 27, count 0 2006.285.12:03:08.58#ibcon#*before return 0, iclass 27, count 0 2006.285.12:03:08.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:03:08.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:03:08.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.12:03:08.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.12:03:08.58$vck44/vb=5,4 2006.285.12:03:08.58#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.12:03:08.58#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.12:03:08.58#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:08.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:03:08.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:03:08.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:03:08.64#ibcon#enter wrdev, iclass 29, count 2 2006.285.12:03:08.64#ibcon#first serial, iclass 29, count 2 2006.285.12:03:08.64#ibcon#enter sib2, iclass 29, count 2 2006.285.12:03:08.64#ibcon#flushed, iclass 29, count 2 2006.285.12:03:08.64#ibcon#about to write, iclass 29, count 2 2006.285.12:03:08.64#ibcon#wrote, iclass 29, count 2 2006.285.12:03:08.64#ibcon#about to read 3, iclass 29, count 2 2006.285.12:03:08.66#ibcon#read 3, iclass 29, count 2 2006.285.12:03:08.66#ibcon#about to read 4, iclass 29, count 2 2006.285.12:03:08.66#ibcon#read 4, iclass 29, count 2 2006.285.12:03:08.66#ibcon#about to read 5, iclass 29, count 2 2006.285.12:03:08.66#ibcon#read 5, iclass 29, count 2 2006.285.12:03:08.66#ibcon#about to read 6, iclass 29, count 2 2006.285.12:03:08.66#ibcon#read 6, iclass 29, count 2 2006.285.12:03:08.66#ibcon#end of sib2, iclass 29, count 2 2006.285.12:03:08.66#ibcon#*mode == 0, iclass 29, count 2 2006.285.12:03:08.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.12:03:08.66#ibcon#[27=AT05-04\r\n] 2006.285.12:03:08.66#ibcon#*before write, iclass 29, count 2 2006.285.12:03:08.66#ibcon#enter sib2, iclass 29, count 2 2006.285.12:03:08.66#ibcon#flushed, iclass 29, count 2 2006.285.12:03:08.66#ibcon#about to write, iclass 29, count 2 2006.285.12:03:08.66#ibcon#wrote, iclass 29, count 2 2006.285.12:03:08.66#ibcon#about to read 3, iclass 29, count 2 2006.285.12:03:08.69#ibcon#read 3, iclass 29, count 2 2006.285.12:03:08.69#ibcon#about to read 4, iclass 29, count 2 2006.285.12:03:08.69#ibcon#read 4, iclass 29, count 2 2006.285.12:03:08.69#ibcon#about to read 5, iclass 29, count 2 2006.285.12:03:08.69#ibcon#read 5, iclass 29, count 2 2006.285.12:03:08.69#ibcon#about to read 6, iclass 29, count 2 2006.285.12:03:08.69#ibcon#read 6, iclass 29, count 2 2006.285.12:03:08.69#ibcon#end of sib2, iclass 29, count 2 2006.285.12:03:08.69#ibcon#*after write, iclass 29, count 2 2006.285.12:03:08.69#ibcon#*before return 0, iclass 29, count 2 2006.285.12:03:08.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:03:08.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:03:08.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.12:03:08.69#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:08.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:03:08.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:03:08.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:03:08.81#ibcon#enter wrdev, iclass 29, count 0 2006.285.12:03:08.81#ibcon#first serial, iclass 29, count 0 2006.285.12:03:08.81#ibcon#enter sib2, iclass 29, count 0 2006.285.12:03:08.81#ibcon#flushed, iclass 29, count 0 2006.285.12:03:08.81#ibcon#about to write, iclass 29, count 0 2006.285.12:03:08.81#ibcon#wrote, iclass 29, count 0 2006.285.12:03:08.81#ibcon#about to read 3, iclass 29, count 0 2006.285.12:03:08.83#ibcon#read 3, iclass 29, count 0 2006.285.12:03:08.83#ibcon#about to read 4, iclass 29, count 0 2006.285.12:03:08.83#ibcon#read 4, iclass 29, count 0 2006.285.12:03:08.83#ibcon#about to read 5, iclass 29, count 0 2006.285.12:03:08.83#ibcon#read 5, iclass 29, count 0 2006.285.12:03:08.83#ibcon#about to read 6, iclass 29, count 0 2006.285.12:03:08.83#ibcon#read 6, iclass 29, count 0 2006.285.12:03:08.83#ibcon#end of sib2, iclass 29, count 0 2006.285.12:03:08.83#ibcon#*mode == 0, iclass 29, count 0 2006.285.12:03:08.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.12:03:08.83#ibcon#[27=USB\r\n] 2006.285.12:03:08.83#ibcon#*before write, iclass 29, count 0 2006.285.12:03:08.83#ibcon#enter sib2, iclass 29, count 0 2006.285.12:03:08.83#ibcon#flushed, iclass 29, count 0 2006.285.12:03:08.83#ibcon#about to write, iclass 29, count 0 2006.285.12:03:08.83#ibcon#wrote, iclass 29, count 0 2006.285.12:03:08.83#ibcon#about to read 3, iclass 29, count 0 2006.285.12:03:08.86#ibcon#read 3, iclass 29, count 0 2006.285.12:03:08.86#ibcon#about to read 4, iclass 29, count 0 2006.285.12:03:08.86#ibcon#read 4, iclass 29, count 0 2006.285.12:03:08.86#ibcon#about to read 5, iclass 29, count 0 2006.285.12:03:08.86#ibcon#read 5, iclass 29, count 0 2006.285.12:03:08.86#ibcon#about to read 6, iclass 29, count 0 2006.285.12:03:08.86#ibcon#read 6, iclass 29, count 0 2006.285.12:03:08.86#ibcon#end of sib2, iclass 29, count 0 2006.285.12:03:08.86#ibcon#*after write, iclass 29, count 0 2006.285.12:03:08.86#ibcon#*before return 0, iclass 29, count 0 2006.285.12:03:08.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:03:08.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:03:08.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.12:03:08.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.12:03:08.86$vck44/vblo=6,719.99 2006.285.12:03:08.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.12:03:08.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.12:03:08.86#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:08.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:03:08.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:03:08.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:03:08.86#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:03:08.86#ibcon#first serial, iclass 31, count 0 2006.285.12:03:08.86#ibcon#enter sib2, iclass 31, count 0 2006.285.12:03:08.86#ibcon#flushed, iclass 31, count 0 2006.285.12:03:08.86#ibcon#about to write, iclass 31, count 0 2006.285.12:03:08.86#ibcon#wrote, iclass 31, count 0 2006.285.12:03:08.86#ibcon#about to read 3, iclass 31, count 0 2006.285.12:03:08.88#ibcon#read 3, iclass 31, count 0 2006.285.12:03:08.88#ibcon#about to read 4, iclass 31, count 0 2006.285.12:03:08.88#ibcon#read 4, iclass 31, count 0 2006.285.12:03:08.88#ibcon#about to read 5, iclass 31, count 0 2006.285.12:03:08.88#ibcon#read 5, iclass 31, count 0 2006.285.12:03:08.88#ibcon#about to read 6, iclass 31, count 0 2006.285.12:03:08.88#ibcon#read 6, iclass 31, count 0 2006.285.12:03:08.88#ibcon#end of sib2, iclass 31, count 0 2006.285.12:03:08.88#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:03:08.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:03:08.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.12:03:08.88#ibcon#*before write, iclass 31, count 0 2006.285.12:03:08.88#ibcon#enter sib2, iclass 31, count 0 2006.285.12:03:08.88#ibcon#flushed, iclass 31, count 0 2006.285.12:03:08.88#ibcon#about to write, iclass 31, count 0 2006.285.12:03:08.88#ibcon#wrote, iclass 31, count 0 2006.285.12:03:08.88#ibcon#about to read 3, iclass 31, count 0 2006.285.12:03:08.92#ibcon#read 3, iclass 31, count 0 2006.285.12:03:08.92#ibcon#about to read 4, iclass 31, count 0 2006.285.12:03:08.92#ibcon#read 4, iclass 31, count 0 2006.285.12:03:08.92#ibcon#about to read 5, iclass 31, count 0 2006.285.12:03:08.92#ibcon#read 5, iclass 31, count 0 2006.285.12:03:08.92#ibcon#about to read 6, iclass 31, count 0 2006.285.12:03:08.92#ibcon#read 6, iclass 31, count 0 2006.285.12:03:08.92#ibcon#end of sib2, iclass 31, count 0 2006.285.12:03:08.92#ibcon#*after write, iclass 31, count 0 2006.285.12:03:08.92#ibcon#*before return 0, iclass 31, count 0 2006.285.12:03:08.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:03:08.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:03:08.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:03:08.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:03:08.92$vck44/vb=6,3 2006.285.12:03:08.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.12:03:08.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.12:03:08.92#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:08.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:03:08.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:03:08.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:03:08.98#ibcon#enter wrdev, iclass 33, count 2 2006.285.12:03:08.98#ibcon#first serial, iclass 33, count 2 2006.285.12:03:08.98#ibcon#enter sib2, iclass 33, count 2 2006.285.12:03:08.98#ibcon#flushed, iclass 33, count 2 2006.285.12:03:08.98#ibcon#about to write, iclass 33, count 2 2006.285.12:03:08.98#ibcon#wrote, iclass 33, count 2 2006.285.12:03:08.98#ibcon#about to read 3, iclass 33, count 2 2006.285.12:03:09.00#ibcon#read 3, iclass 33, count 2 2006.285.12:03:09.00#ibcon#about to read 4, iclass 33, count 2 2006.285.12:03:09.00#ibcon#read 4, iclass 33, count 2 2006.285.12:03:09.00#ibcon#about to read 5, iclass 33, count 2 2006.285.12:03:09.00#ibcon#read 5, iclass 33, count 2 2006.285.12:03:09.00#ibcon#about to read 6, iclass 33, count 2 2006.285.12:03:09.00#ibcon#read 6, iclass 33, count 2 2006.285.12:03:09.00#ibcon#end of sib2, iclass 33, count 2 2006.285.12:03:09.00#ibcon#*mode == 0, iclass 33, count 2 2006.285.12:03:09.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.12:03:09.00#ibcon#[27=AT06-03\r\n] 2006.285.12:03:09.00#ibcon#*before write, iclass 33, count 2 2006.285.12:03:09.00#ibcon#enter sib2, iclass 33, count 2 2006.285.12:03:09.00#ibcon#flushed, iclass 33, count 2 2006.285.12:03:09.00#ibcon#about to write, iclass 33, count 2 2006.285.12:03:09.00#ibcon#wrote, iclass 33, count 2 2006.285.12:03:09.00#ibcon#about to read 3, iclass 33, count 2 2006.285.12:03:09.03#ibcon#read 3, iclass 33, count 2 2006.285.12:03:09.03#ibcon#about to read 4, iclass 33, count 2 2006.285.12:03:09.03#ibcon#read 4, iclass 33, count 2 2006.285.12:03:09.03#ibcon#about to read 5, iclass 33, count 2 2006.285.12:03:09.03#ibcon#read 5, iclass 33, count 2 2006.285.12:03:09.03#ibcon#about to read 6, iclass 33, count 2 2006.285.12:03:09.03#ibcon#read 6, iclass 33, count 2 2006.285.12:03:09.03#ibcon#end of sib2, iclass 33, count 2 2006.285.12:03:09.03#ibcon#*after write, iclass 33, count 2 2006.285.12:03:09.03#ibcon#*before return 0, iclass 33, count 2 2006.285.12:03:09.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:03:09.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:03:09.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.12:03:09.03#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:09.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:03:09.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:03:09.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:03:09.15#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:03:09.15#ibcon#first serial, iclass 33, count 0 2006.285.12:03:09.15#ibcon#enter sib2, iclass 33, count 0 2006.285.12:03:09.15#ibcon#flushed, iclass 33, count 0 2006.285.12:03:09.15#ibcon#about to write, iclass 33, count 0 2006.285.12:03:09.15#ibcon#wrote, iclass 33, count 0 2006.285.12:03:09.15#ibcon#about to read 3, iclass 33, count 0 2006.285.12:03:09.17#ibcon#read 3, iclass 33, count 0 2006.285.12:03:09.17#ibcon#about to read 4, iclass 33, count 0 2006.285.12:03:09.17#ibcon#read 4, iclass 33, count 0 2006.285.12:03:09.17#ibcon#about to read 5, iclass 33, count 0 2006.285.12:03:09.17#ibcon#read 5, iclass 33, count 0 2006.285.12:03:09.17#ibcon#about to read 6, iclass 33, count 0 2006.285.12:03:09.17#ibcon#read 6, iclass 33, count 0 2006.285.12:03:09.17#ibcon#end of sib2, iclass 33, count 0 2006.285.12:03:09.17#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:03:09.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:03:09.17#ibcon#[27=USB\r\n] 2006.285.12:03:09.17#ibcon#*before write, iclass 33, count 0 2006.285.12:03:09.17#ibcon#enter sib2, iclass 33, count 0 2006.285.12:03:09.17#ibcon#flushed, iclass 33, count 0 2006.285.12:03:09.17#ibcon#about to write, iclass 33, count 0 2006.285.12:03:09.17#ibcon#wrote, iclass 33, count 0 2006.285.12:03:09.17#ibcon#about to read 3, iclass 33, count 0 2006.285.12:03:09.20#ibcon#read 3, iclass 33, count 0 2006.285.12:03:09.20#ibcon#about to read 4, iclass 33, count 0 2006.285.12:03:09.20#ibcon#read 4, iclass 33, count 0 2006.285.12:03:09.20#ibcon#about to read 5, iclass 33, count 0 2006.285.12:03:09.20#ibcon#read 5, iclass 33, count 0 2006.285.12:03:09.20#ibcon#about to read 6, iclass 33, count 0 2006.285.12:03:09.20#ibcon#read 6, iclass 33, count 0 2006.285.12:03:09.20#ibcon#end of sib2, iclass 33, count 0 2006.285.12:03:09.20#ibcon#*after write, iclass 33, count 0 2006.285.12:03:09.20#ibcon#*before return 0, iclass 33, count 0 2006.285.12:03:09.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:03:09.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:03:09.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:03:09.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:03:09.20$vck44/vblo=7,734.99 2006.285.12:03:09.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.12:03:09.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.12:03:09.20#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:09.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:03:09.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:03:09.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:03:09.20#ibcon#enter wrdev, iclass 35, count 0 2006.285.12:03:09.20#ibcon#first serial, iclass 35, count 0 2006.285.12:03:09.20#ibcon#enter sib2, iclass 35, count 0 2006.285.12:03:09.20#ibcon#flushed, iclass 35, count 0 2006.285.12:03:09.20#ibcon#about to write, iclass 35, count 0 2006.285.12:03:09.20#ibcon#wrote, iclass 35, count 0 2006.285.12:03:09.20#ibcon#about to read 3, iclass 35, count 0 2006.285.12:03:09.22#ibcon#read 3, iclass 35, count 0 2006.285.12:03:09.22#ibcon#about to read 4, iclass 35, count 0 2006.285.12:03:09.22#ibcon#read 4, iclass 35, count 0 2006.285.12:03:09.22#ibcon#about to read 5, iclass 35, count 0 2006.285.12:03:09.22#ibcon#read 5, iclass 35, count 0 2006.285.12:03:09.22#ibcon#about to read 6, iclass 35, count 0 2006.285.12:03:09.22#ibcon#read 6, iclass 35, count 0 2006.285.12:03:09.22#ibcon#end of sib2, iclass 35, count 0 2006.285.12:03:09.22#ibcon#*mode == 0, iclass 35, count 0 2006.285.12:03:09.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.12:03:09.22#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.12:03:09.22#ibcon#*before write, iclass 35, count 0 2006.285.12:03:09.22#ibcon#enter sib2, iclass 35, count 0 2006.285.12:03:09.22#ibcon#flushed, iclass 35, count 0 2006.285.12:03:09.22#ibcon#about to write, iclass 35, count 0 2006.285.12:03:09.22#ibcon#wrote, iclass 35, count 0 2006.285.12:03:09.22#ibcon#about to read 3, iclass 35, count 0 2006.285.12:03:09.26#ibcon#read 3, iclass 35, count 0 2006.285.12:03:09.26#ibcon#about to read 4, iclass 35, count 0 2006.285.12:03:09.26#ibcon#read 4, iclass 35, count 0 2006.285.12:03:09.26#ibcon#about to read 5, iclass 35, count 0 2006.285.12:03:09.26#ibcon#read 5, iclass 35, count 0 2006.285.12:03:09.26#ibcon#about to read 6, iclass 35, count 0 2006.285.12:03:09.26#ibcon#read 6, iclass 35, count 0 2006.285.12:03:09.26#ibcon#end of sib2, iclass 35, count 0 2006.285.12:03:09.26#ibcon#*after write, iclass 35, count 0 2006.285.12:03:09.26#ibcon#*before return 0, iclass 35, count 0 2006.285.12:03:09.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:03:09.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:03:09.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.12:03:09.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.12:03:09.26$vck44/vb=7,4 2006.285.12:03:09.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.12:03:09.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.12:03:09.26#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:09.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:03:09.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:03:09.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:03:09.32#ibcon#enter wrdev, iclass 37, count 2 2006.285.12:03:09.32#ibcon#first serial, iclass 37, count 2 2006.285.12:03:09.32#ibcon#enter sib2, iclass 37, count 2 2006.285.12:03:09.32#ibcon#flushed, iclass 37, count 2 2006.285.12:03:09.32#ibcon#about to write, iclass 37, count 2 2006.285.12:03:09.32#ibcon#wrote, iclass 37, count 2 2006.285.12:03:09.32#ibcon#about to read 3, iclass 37, count 2 2006.285.12:03:09.34#ibcon#read 3, iclass 37, count 2 2006.285.12:03:09.34#ibcon#about to read 4, iclass 37, count 2 2006.285.12:03:09.34#ibcon#read 4, iclass 37, count 2 2006.285.12:03:09.34#ibcon#about to read 5, iclass 37, count 2 2006.285.12:03:09.34#ibcon#read 5, iclass 37, count 2 2006.285.12:03:09.34#ibcon#about to read 6, iclass 37, count 2 2006.285.12:03:09.34#ibcon#read 6, iclass 37, count 2 2006.285.12:03:09.34#ibcon#end of sib2, iclass 37, count 2 2006.285.12:03:09.34#ibcon#*mode == 0, iclass 37, count 2 2006.285.12:03:09.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.12:03:09.34#ibcon#[27=AT07-04\r\n] 2006.285.12:03:09.34#ibcon#*before write, iclass 37, count 2 2006.285.12:03:09.34#ibcon#enter sib2, iclass 37, count 2 2006.285.12:03:09.34#ibcon#flushed, iclass 37, count 2 2006.285.12:03:09.34#ibcon#about to write, iclass 37, count 2 2006.285.12:03:09.34#ibcon#wrote, iclass 37, count 2 2006.285.12:03:09.34#ibcon#about to read 3, iclass 37, count 2 2006.285.12:03:09.37#ibcon#read 3, iclass 37, count 2 2006.285.12:03:09.37#ibcon#about to read 4, iclass 37, count 2 2006.285.12:03:09.37#ibcon#read 4, iclass 37, count 2 2006.285.12:03:09.37#ibcon#about to read 5, iclass 37, count 2 2006.285.12:03:09.37#ibcon#read 5, iclass 37, count 2 2006.285.12:03:09.37#ibcon#about to read 6, iclass 37, count 2 2006.285.12:03:09.37#ibcon#read 6, iclass 37, count 2 2006.285.12:03:09.37#ibcon#end of sib2, iclass 37, count 2 2006.285.12:03:09.37#ibcon#*after write, iclass 37, count 2 2006.285.12:03:09.37#ibcon#*before return 0, iclass 37, count 2 2006.285.12:03:09.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:03:09.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:03:09.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.12:03:09.37#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:09.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:03:09.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:03:09.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:03:09.49#ibcon#enter wrdev, iclass 37, count 0 2006.285.12:03:09.49#ibcon#first serial, iclass 37, count 0 2006.285.12:03:09.49#ibcon#enter sib2, iclass 37, count 0 2006.285.12:03:09.49#ibcon#flushed, iclass 37, count 0 2006.285.12:03:09.49#ibcon#about to write, iclass 37, count 0 2006.285.12:03:09.49#ibcon#wrote, iclass 37, count 0 2006.285.12:03:09.49#ibcon#about to read 3, iclass 37, count 0 2006.285.12:03:09.51#ibcon#read 3, iclass 37, count 0 2006.285.12:03:09.51#ibcon#about to read 4, iclass 37, count 0 2006.285.12:03:09.51#ibcon#read 4, iclass 37, count 0 2006.285.12:03:09.51#ibcon#about to read 5, iclass 37, count 0 2006.285.12:03:09.51#ibcon#read 5, iclass 37, count 0 2006.285.12:03:09.51#ibcon#about to read 6, iclass 37, count 0 2006.285.12:03:09.51#ibcon#read 6, iclass 37, count 0 2006.285.12:03:09.51#ibcon#end of sib2, iclass 37, count 0 2006.285.12:03:09.51#ibcon#*mode == 0, iclass 37, count 0 2006.285.12:03:09.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.12:03:09.51#ibcon#[27=USB\r\n] 2006.285.12:03:09.51#ibcon#*before write, iclass 37, count 0 2006.285.12:03:09.51#ibcon#enter sib2, iclass 37, count 0 2006.285.12:03:09.51#ibcon#flushed, iclass 37, count 0 2006.285.12:03:09.51#ibcon#about to write, iclass 37, count 0 2006.285.12:03:09.51#ibcon#wrote, iclass 37, count 0 2006.285.12:03:09.51#ibcon#about to read 3, iclass 37, count 0 2006.285.12:03:09.54#ibcon#read 3, iclass 37, count 0 2006.285.12:03:09.54#ibcon#about to read 4, iclass 37, count 0 2006.285.12:03:09.54#ibcon#read 4, iclass 37, count 0 2006.285.12:03:09.54#ibcon#about to read 5, iclass 37, count 0 2006.285.12:03:09.54#ibcon#read 5, iclass 37, count 0 2006.285.12:03:09.54#ibcon#about to read 6, iclass 37, count 0 2006.285.12:03:09.54#ibcon#read 6, iclass 37, count 0 2006.285.12:03:09.54#ibcon#end of sib2, iclass 37, count 0 2006.285.12:03:09.54#ibcon#*after write, iclass 37, count 0 2006.285.12:03:09.54#ibcon#*before return 0, iclass 37, count 0 2006.285.12:03:09.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:03:09.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:03:09.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.12:03:09.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.12:03:09.54$vck44/vblo=8,744.99 2006.285.12:03:09.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.12:03:09.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.12:03:09.54#ibcon#ireg 17 cls_cnt 0 2006.285.12:03:09.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:03:09.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:03:09.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:03:09.54#ibcon#enter wrdev, iclass 39, count 0 2006.285.12:03:09.54#ibcon#first serial, iclass 39, count 0 2006.285.12:03:09.54#ibcon#enter sib2, iclass 39, count 0 2006.285.12:03:09.54#ibcon#flushed, iclass 39, count 0 2006.285.12:03:09.54#ibcon#about to write, iclass 39, count 0 2006.285.12:03:09.54#ibcon#wrote, iclass 39, count 0 2006.285.12:03:09.54#ibcon#about to read 3, iclass 39, count 0 2006.285.12:03:09.56#ibcon#read 3, iclass 39, count 0 2006.285.12:03:09.56#ibcon#about to read 4, iclass 39, count 0 2006.285.12:03:09.56#ibcon#read 4, iclass 39, count 0 2006.285.12:03:09.56#ibcon#about to read 5, iclass 39, count 0 2006.285.12:03:09.56#ibcon#read 5, iclass 39, count 0 2006.285.12:03:09.56#ibcon#about to read 6, iclass 39, count 0 2006.285.12:03:09.56#ibcon#read 6, iclass 39, count 0 2006.285.12:03:09.56#ibcon#end of sib2, iclass 39, count 0 2006.285.12:03:09.56#ibcon#*mode == 0, iclass 39, count 0 2006.285.12:03:09.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.12:03:09.56#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.12:03:09.56#ibcon#*before write, iclass 39, count 0 2006.285.12:03:09.56#ibcon#enter sib2, iclass 39, count 0 2006.285.12:03:09.56#ibcon#flushed, iclass 39, count 0 2006.285.12:03:09.56#ibcon#about to write, iclass 39, count 0 2006.285.12:03:09.56#ibcon#wrote, iclass 39, count 0 2006.285.12:03:09.56#ibcon#about to read 3, iclass 39, count 0 2006.285.12:03:09.60#ibcon#read 3, iclass 39, count 0 2006.285.12:03:09.60#ibcon#about to read 4, iclass 39, count 0 2006.285.12:03:09.60#ibcon#read 4, iclass 39, count 0 2006.285.12:03:09.60#ibcon#about to read 5, iclass 39, count 0 2006.285.12:03:09.60#ibcon#read 5, iclass 39, count 0 2006.285.12:03:09.60#ibcon#about to read 6, iclass 39, count 0 2006.285.12:03:09.60#ibcon#read 6, iclass 39, count 0 2006.285.12:03:09.60#ibcon#end of sib2, iclass 39, count 0 2006.285.12:03:09.60#ibcon#*after write, iclass 39, count 0 2006.285.12:03:09.60#ibcon#*before return 0, iclass 39, count 0 2006.285.12:03:09.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:03:09.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:03:09.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.12:03:09.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.12:03:09.60$vck44/vb=8,4 2006.285.12:03:09.60#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.12:03:09.60#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.12:03:09.60#ibcon#ireg 11 cls_cnt 2 2006.285.12:03:09.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:03:09.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:03:09.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:03:09.66#ibcon#enter wrdev, iclass 3, count 2 2006.285.12:03:09.66#ibcon#first serial, iclass 3, count 2 2006.285.12:03:09.66#ibcon#enter sib2, iclass 3, count 2 2006.285.12:03:09.66#ibcon#flushed, iclass 3, count 2 2006.285.12:03:09.66#ibcon#about to write, iclass 3, count 2 2006.285.12:03:09.66#ibcon#wrote, iclass 3, count 2 2006.285.12:03:09.66#ibcon#about to read 3, iclass 3, count 2 2006.285.12:03:09.68#ibcon#read 3, iclass 3, count 2 2006.285.12:03:09.68#ibcon#about to read 4, iclass 3, count 2 2006.285.12:03:09.68#ibcon#read 4, iclass 3, count 2 2006.285.12:03:09.68#ibcon#about to read 5, iclass 3, count 2 2006.285.12:03:09.68#ibcon#read 5, iclass 3, count 2 2006.285.12:03:09.68#ibcon#about to read 6, iclass 3, count 2 2006.285.12:03:09.68#ibcon#read 6, iclass 3, count 2 2006.285.12:03:09.68#ibcon#end of sib2, iclass 3, count 2 2006.285.12:03:09.68#ibcon#*mode == 0, iclass 3, count 2 2006.285.12:03:09.68#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.12:03:09.68#ibcon#[27=AT08-04\r\n] 2006.285.12:03:09.68#ibcon#*before write, iclass 3, count 2 2006.285.12:03:09.68#ibcon#enter sib2, iclass 3, count 2 2006.285.12:03:09.68#ibcon#flushed, iclass 3, count 2 2006.285.12:03:09.68#ibcon#about to write, iclass 3, count 2 2006.285.12:03:09.68#ibcon#wrote, iclass 3, count 2 2006.285.12:03:09.68#ibcon#about to read 3, iclass 3, count 2 2006.285.12:03:09.71#ibcon#read 3, iclass 3, count 2 2006.285.12:03:09.71#ibcon#about to read 4, iclass 3, count 2 2006.285.12:03:09.71#ibcon#read 4, iclass 3, count 2 2006.285.12:03:09.71#ibcon#about to read 5, iclass 3, count 2 2006.285.12:03:09.71#ibcon#read 5, iclass 3, count 2 2006.285.12:03:09.71#ibcon#about to read 6, iclass 3, count 2 2006.285.12:03:09.71#ibcon#read 6, iclass 3, count 2 2006.285.12:03:09.71#ibcon#end of sib2, iclass 3, count 2 2006.285.12:03:09.71#ibcon#*after write, iclass 3, count 2 2006.285.12:03:09.71#ibcon#*before return 0, iclass 3, count 2 2006.285.12:03:09.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:03:09.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:03:09.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.12:03:09.71#ibcon#ireg 7 cls_cnt 0 2006.285.12:03:09.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:03:09.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:03:09.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:03:09.83#ibcon#enter wrdev, iclass 3, count 0 2006.285.12:03:09.83#ibcon#first serial, iclass 3, count 0 2006.285.12:03:09.83#ibcon#enter sib2, iclass 3, count 0 2006.285.12:03:09.83#ibcon#flushed, iclass 3, count 0 2006.285.12:03:09.83#ibcon#about to write, iclass 3, count 0 2006.285.12:03:09.83#ibcon#wrote, iclass 3, count 0 2006.285.12:03:09.83#ibcon#about to read 3, iclass 3, count 0 2006.285.12:03:09.85#ibcon#read 3, iclass 3, count 0 2006.285.12:03:09.85#ibcon#about to read 4, iclass 3, count 0 2006.285.12:03:09.85#ibcon#read 4, iclass 3, count 0 2006.285.12:03:09.85#ibcon#about to read 5, iclass 3, count 0 2006.285.12:03:09.85#ibcon#read 5, iclass 3, count 0 2006.285.12:03:09.85#ibcon#about to read 6, iclass 3, count 0 2006.285.12:03:09.85#ibcon#read 6, iclass 3, count 0 2006.285.12:03:09.85#ibcon#end of sib2, iclass 3, count 0 2006.285.12:03:09.85#ibcon#*mode == 0, iclass 3, count 0 2006.285.12:03:09.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.12:03:09.85#ibcon#[27=USB\r\n] 2006.285.12:03:09.85#ibcon#*before write, iclass 3, count 0 2006.285.12:03:09.85#ibcon#enter sib2, iclass 3, count 0 2006.285.12:03:09.85#ibcon#flushed, iclass 3, count 0 2006.285.12:03:09.85#ibcon#about to write, iclass 3, count 0 2006.285.12:03:09.85#ibcon#wrote, iclass 3, count 0 2006.285.12:03:09.85#ibcon#about to read 3, iclass 3, count 0 2006.285.12:03:09.88#ibcon#read 3, iclass 3, count 0 2006.285.12:03:09.88#ibcon#about to read 4, iclass 3, count 0 2006.285.12:03:09.88#ibcon#read 4, iclass 3, count 0 2006.285.12:03:09.88#ibcon#about to read 5, iclass 3, count 0 2006.285.12:03:09.88#ibcon#read 5, iclass 3, count 0 2006.285.12:03:09.88#ibcon#about to read 6, iclass 3, count 0 2006.285.12:03:09.88#ibcon#read 6, iclass 3, count 0 2006.285.12:03:09.88#ibcon#end of sib2, iclass 3, count 0 2006.285.12:03:09.88#ibcon#*after write, iclass 3, count 0 2006.285.12:03:09.88#ibcon#*before return 0, iclass 3, count 0 2006.285.12:03:09.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:03:09.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:03:09.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.12:03:09.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.12:03:09.88$vck44/vabw=wide 2006.285.12:03:09.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.12:03:09.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.12:03:09.88#ibcon#ireg 8 cls_cnt 0 2006.285.12:03:09.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:03:09.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:03:09.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:03:09.88#ibcon#enter wrdev, iclass 5, count 0 2006.285.12:03:09.88#ibcon#first serial, iclass 5, count 0 2006.285.12:03:09.88#ibcon#enter sib2, iclass 5, count 0 2006.285.12:03:09.88#ibcon#flushed, iclass 5, count 0 2006.285.12:03:09.88#ibcon#about to write, iclass 5, count 0 2006.285.12:03:09.88#ibcon#wrote, iclass 5, count 0 2006.285.12:03:09.88#ibcon#about to read 3, iclass 5, count 0 2006.285.12:03:09.90#ibcon#read 3, iclass 5, count 0 2006.285.12:03:09.90#ibcon#about to read 4, iclass 5, count 0 2006.285.12:03:09.90#ibcon#read 4, iclass 5, count 0 2006.285.12:03:09.90#ibcon#about to read 5, iclass 5, count 0 2006.285.12:03:09.90#ibcon#read 5, iclass 5, count 0 2006.285.12:03:09.90#ibcon#about to read 6, iclass 5, count 0 2006.285.12:03:09.90#ibcon#read 6, iclass 5, count 0 2006.285.12:03:09.90#ibcon#end of sib2, iclass 5, count 0 2006.285.12:03:09.90#ibcon#*mode == 0, iclass 5, count 0 2006.285.12:03:09.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.12:03:09.90#ibcon#[25=BW32\r\n] 2006.285.12:03:09.90#ibcon#*before write, iclass 5, count 0 2006.285.12:03:09.90#ibcon#enter sib2, iclass 5, count 0 2006.285.12:03:09.90#ibcon#flushed, iclass 5, count 0 2006.285.12:03:09.90#ibcon#about to write, iclass 5, count 0 2006.285.12:03:09.90#ibcon#wrote, iclass 5, count 0 2006.285.12:03:09.90#ibcon#about to read 3, iclass 5, count 0 2006.285.12:03:09.93#ibcon#read 3, iclass 5, count 0 2006.285.12:03:09.93#ibcon#about to read 4, iclass 5, count 0 2006.285.12:03:09.93#ibcon#read 4, iclass 5, count 0 2006.285.12:03:09.93#ibcon#about to read 5, iclass 5, count 0 2006.285.12:03:09.93#ibcon#read 5, iclass 5, count 0 2006.285.12:03:09.93#ibcon#about to read 6, iclass 5, count 0 2006.285.12:03:09.93#ibcon#read 6, iclass 5, count 0 2006.285.12:03:09.93#ibcon#end of sib2, iclass 5, count 0 2006.285.12:03:09.93#ibcon#*after write, iclass 5, count 0 2006.285.12:03:09.93#ibcon#*before return 0, iclass 5, count 0 2006.285.12:03:09.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:03:09.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:03:09.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.12:03:09.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.12:03:09.93$vck44/vbbw=wide 2006.285.12:03:09.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.12:03:09.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.12:03:09.93#ibcon#ireg 8 cls_cnt 0 2006.285.12:03:09.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:03:10.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:03:10.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:03:10.00#ibcon#enter wrdev, iclass 7, count 0 2006.285.12:03:10.00#ibcon#first serial, iclass 7, count 0 2006.285.12:03:10.00#ibcon#enter sib2, iclass 7, count 0 2006.285.12:03:10.00#ibcon#flushed, iclass 7, count 0 2006.285.12:03:10.00#ibcon#about to write, iclass 7, count 0 2006.285.12:03:10.00#ibcon#wrote, iclass 7, count 0 2006.285.12:03:10.00#ibcon#about to read 3, iclass 7, count 0 2006.285.12:03:10.02#ibcon#read 3, iclass 7, count 0 2006.285.12:03:10.02#ibcon#about to read 4, iclass 7, count 0 2006.285.12:03:10.02#ibcon#read 4, iclass 7, count 0 2006.285.12:03:10.02#ibcon#about to read 5, iclass 7, count 0 2006.285.12:03:10.02#ibcon#read 5, iclass 7, count 0 2006.285.12:03:10.02#ibcon#about to read 6, iclass 7, count 0 2006.285.12:03:10.02#ibcon#read 6, iclass 7, count 0 2006.285.12:03:10.02#ibcon#end of sib2, iclass 7, count 0 2006.285.12:03:10.02#ibcon#*mode == 0, iclass 7, count 0 2006.285.12:03:10.02#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.12:03:10.02#ibcon#[27=BW32\r\n] 2006.285.12:03:10.02#ibcon#*before write, iclass 7, count 0 2006.285.12:03:10.02#ibcon#enter sib2, iclass 7, count 0 2006.285.12:03:10.02#ibcon#flushed, iclass 7, count 0 2006.285.12:03:10.02#ibcon#about to write, iclass 7, count 0 2006.285.12:03:10.02#ibcon#wrote, iclass 7, count 0 2006.285.12:03:10.02#ibcon#about to read 3, iclass 7, count 0 2006.285.12:03:10.05#ibcon#read 3, iclass 7, count 0 2006.285.12:03:10.05#ibcon#about to read 4, iclass 7, count 0 2006.285.12:03:10.05#ibcon#read 4, iclass 7, count 0 2006.285.12:03:10.05#ibcon#about to read 5, iclass 7, count 0 2006.285.12:03:10.05#ibcon#read 5, iclass 7, count 0 2006.285.12:03:10.05#ibcon#about to read 6, iclass 7, count 0 2006.285.12:03:10.05#ibcon#read 6, iclass 7, count 0 2006.285.12:03:10.05#ibcon#end of sib2, iclass 7, count 0 2006.285.12:03:10.05#ibcon#*after write, iclass 7, count 0 2006.285.12:03:10.05#ibcon#*before return 0, iclass 7, count 0 2006.285.12:03:10.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:03:10.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:03:10.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.12:03:10.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.12:03:10.05$setupk4/ifdk4 2006.285.12:03:10.05$ifdk4/lo= 2006.285.12:03:10.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.12:03:10.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.12:03:10.05$ifdk4/patch= 2006.285.12:03:10.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.12:03:10.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.12:03:10.05$setupk4/!*+20s 2006.285.12:03:13.82#abcon#<5=/04 1.0 1.8 19.01 951015.5\r\n> 2006.285.12:03:13.84#abcon#{5=INTERFACE CLEAR} 2006.285.12:03:13.90#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:03:23.99#abcon#<5=/04 1.0 1.8 19.01 951015.5\r\n> 2006.285.12:03:24.01#abcon#{5=INTERFACE CLEAR} 2006.285.12:03:24.07#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:03:24.56$setupk4/"tpicd 2006.285.12:03:24.56$setupk4/echo=off 2006.285.12:03:24.56$setupk4/xlog=off 2006.285.12:03:24.56:!2006.285.12:08:27 2006.285.12:03:32.13#trakl#Source acquired 2006.285.12:03:33.13#flagr#flagr/antenna,acquired 2006.285.12:08:27.00:preob 2006.285.12:08:28.14/onsource/TRACKING 2006.285.12:08:28.14:!2006.285.12:08:37 2006.285.12:08:37.00:"tape 2006.285.12:08:37.00:"st=record 2006.285.12:08:37.00:data_valid=on 2006.285.12:08:37.00:midob 2006.285.12:08:37.14/onsource/TRACKING 2006.285.12:08:37.14/wx/18.99,1015.5,94 2006.285.12:08:37.35/cable/+6.4961E-03 2006.285.12:08:38.44/va/01,07,usb,yes,33,36 2006.285.12:08:38.44/va/02,06,usb,yes,33,34 2006.285.12:08:38.44/va/03,07,usb,yes,33,35 2006.285.12:08:38.44/va/04,06,usb,yes,34,36 2006.285.12:08:38.44/va/05,03,usb,yes,34,34 2006.285.12:08:38.44/va/06,04,usb,yes,30,30 2006.285.12:08:38.44/va/07,04,usb,yes,31,32 2006.285.12:08:38.44/va/08,03,usb,yes,32,39 2006.285.12:08:38.67/valo/01,524.99,yes,locked 2006.285.12:08:38.67/valo/02,534.99,yes,locked 2006.285.12:08:38.67/valo/03,564.99,yes,locked 2006.285.12:08:38.67/valo/04,624.99,yes,locked 2006.285.12:08:38.67/valo/05,734.99,yes,locked 2006.285.12:08:38.67/valo/06,814.99,yes,locked 2006.285.12:08:38.67/valo/07,864.99,yes,locked 2006.285.12:08:38.67/valo/08,884.99,yes,locked 2006.285.12:08:39.76/vb/01,04,usb,yes,31,28 2006.285.12:08:39.76/vb/02,05,usb,yes,29,29 2006.285.12:08:39.76/vb/03,04,usb,yes,30,33 2006.285.12:08:39.76/vb/04,05,usb,yes,30,29 2006.285.12:08:39.76/vb/05,04,usb,yes,27,29 2006.285.12:08:39.76/vb/06,03,usb,yes,38,34 2006.285.12:08:39.76/vb/07,04,usb,yes,31,31 2006.285.12:08:39.76/vb/08,04,usb,yes,28,32 2006.285.12:08:40.00/vblo/01,629.99,yes,locked 2006.285.12:08:40.00/vblo/02,634.99,yes,locked 2006.285.12:08:40.00/vblo/03,649.99,yes,locked 2006.285.12:08:40.00/vblo/04,679.99,yes,locked 2006.285.12:08:40.00/vblo/05,709.99,yes,locked 2006.285.12:08:40.00/vblo/06,719.99,yes,locked 2006.285.12:08:40.00/vblo/07,734.99,yes,locked 2006.285.12:08:40.00/vblo/08,744.99,yes,locked 2006.285.12:08:40.15/vabw/8 2006.285.12:08:40.30/vbbw/8 2006.285.12:08:40.39/xfe/off,on,12.2 2006.285.12:08:40.77/ifatt/23,28,28,28 2006.285.12:08:41.07/fmout-gps/S +2.46E-07 2006.285.12:08:41.09:!2006.285.12:11:07 2006.285.12:11:07.00:data_valid=off 2006.285.12:11:07.00:"et 2006.285.12:11:07.00:!+3s 2006.285.12:11:10.01:"tape 2006.285.12:11:10.01:postob 2006.285.12:11:10.15/cable/+6.4935E-03 2006.285.12:11:10.15/wx/18.99,1015.5,94 2006.285.12:11:11.08/fmout-gps/S +2.46E-07 2006.285.12:11:11.08:scan_name=285-1213,jd0610,160 2006.285.12:11:11.08:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.285.12:11:11.13#flagr#flagr/antenna,new-source 2006.285.12:11:12.13:checkk5 2006.285.12:11:12.49/chk_autoobs//k5ts1/ autoobs is running! 2006.285.12:11:12.85/chk_autoobs//k5ts2/ autoobs is running! 2006.285.12:11:13.20/chk_autoobs//k5ts3/ autoobs is running! 2006.285.12:11:13.57/chk_autoobs//k5ts4/ autoobs is running! 2006.285.12:11:13.91/chk_obsdata//k5ts1/T2851208??a.dat file size is correct (nominal:600MB, actual:600MB). 2006.285.12:11:14.34/chk_obsdata//k5ts2/T2851208??b.dat file size is correct (nominal:600MB, actual:600MB). 2006.285.12:11:14.92/chk_obsdata//k5ts3/T2851208??c.dat file size is correct (nominal:600MB, actual:600MB). 2006.285.12:11:15.27/chk_obsdata//k5ts4/T2851208??d.dat file size is correct (nominal:600MB, actual:600MB). 2006.285.12:11:16.01/k5log//k5ts1_log_newline 2006.285.12:11:16.86/k5log//k5ts2_log_newline 2006.285.12:11:17.74/k5log//k5ts3_log_newline 2006.285.12:11:18.60/k5log//k5ts4_log_newline 2006.285.12:11:18.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.12:11:18.62:setupk4=1 2006.285.12:11:18.62$setupk4/echo=on 2006.285.12:11:18.62$setupk4/pcalon 2006.285.12:11:18.62$pcalon/"no phase cal control is implemented here 2006.285.12:11:18.62$setupk4/"tpicd=stop 2006.285.12:11:18.62$setupk4/"rec=synch_on 2006.285.12:11:18.62$setupk4/"rec_mode=128 2006.285.12:11:18.62$setupk4/!* 2006.285.12:11:18.62$setupk4/recpk4 2006.285.12:11:18.62$recpk4/recpatch= 2006.285.12:11:18.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.12:11:18.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.12:11:18.63$setupk4/vck44 2006.285.12:11:18.63$vck44/valo=1,524.99 2006.285.12:11:18.63#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.12:11:18.63#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.12:11:18.63#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:18.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:11:18.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:11:18.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:11:18.63#ibcon#enter wrdev, iclass 26, count 0 2006.285.12:11:18.63#ibcon#first serial, iclass 26, count 0 2006.285.12:11:18.63#ibcon#enter sib2, iclass 26, count 0 2006.285.12:11:18.63#ibcon#flushed, iclass 26, count 0 2006.285.12:11:18.63#ibcon#about to write, iclass 26, count 0 2006.285.12:11:18.63#ibcon#wrote, iclass 26, count 0 2006.285.12:11:18.63#ibcon#about to read 3, iclass 26, count 0 2006.285.12:11:18.65#ibcon#read 3, iclass 26, count 0 2006.285.12:11:18.65#ibcon#about to read 4, iclass 26, count 0 2006.285.12:11:18.65#ibcon#read 4, iclass 26, count 0 2006.285.12:11:18.65#ibcon#about to read 5, iclass 26, count 0 2006.285.12:11:18.65#ibcon#read 5, iclass 26, count 0 2006.285.12:11:18.65#ibcon#about to read 6, iclass 26, count 0 2006.285.12:11:18.65#ibcon#read 6, iclass 26, count 0 2006.285.12:11:18.65#ibcon#end of sib2, iclass 26, count 0 2006.285.12:11:18.65#ibcon#*mode == 0, iclass 26, count 0 2006.285.12:11:18.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.12:11:18.65#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.12:11:18.65#ibcon#*before write, iclass 26, count 0 2006.285.12:11:18.65#ibcon#enter sib2, iclass 26, count 0 2006.285.12:11:18.65#ibcon#flushed, iclass 26, count 0 2006.285.12:11:18.65#ibcon#about to write, iclass 26, count 0 2006.285.12:11:18.65#ibcon#wrote, iclass 26, count 0 2006.285.12:11:18.65#ibcon#about to read 3, iclass 26, count 0 2006.285.12:11:18.70#ibcon#read 3, iclass 26, count 0 2006.285.12:11:18.70#ibcon#about to read 4, iclass 26, count 0 2006.285.12:11:18.70#ibcon#read 4, iclass 26, count 0 2006.285.12:11:18.70#ibcon#about to read 5, iclass 26, count 0 2006.285.12:11:18.70#ibcon#read 5, iclass 26, count 0 2006.285.12:11:18.70#ibcon#about to read 6, iclass 26, count 0 2006.285.12:11:18.70#ibcon#read 6, iclass 26, count 0 2006.285.12:11:18.70#ibcon#end of sib2, iclass 26, count 0 2006.285.12:11:18.70#ibcon#*after write, iclass 26, count 0 2006.285.12:11:18.70#ibcon#*before return 0, iclass 26, count 0 2006.285.12:11:18.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:11:18.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:11:18.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.12:11:18.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.12:11:18.70$vck44/va=1,7 2006.285.12:11:18.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.12:11:18.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.12:11:18.70#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:18.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:11:18.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:11:18.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:11:18.70#ibcon#enter wrdev, iclass 28, count 2 2006.285.12:11:18.70#ibcon#first serial, iclass 28, count 2 2006.285.12:11:18.70#ibcon#enter sib2, iclass 28, count 2 2006.285.12:11:18.70#ibcon#flushed, iclass 28, count 2 2006.285.12:11:18.70#ibcon#about to write, iclass 28, count 2 2006.285.12:11:18.70#ibcon#wrote, iclass 28, count 2 2006.285.12:11:18.70#ibcon#about to read 3, iclass 28, count 2 2006.285.12:11:18.72#ibcon#read 3, iclass 28, count 2 2006.285.12:11:18.72#ibcon#about to read 4, iclass 28, count 2 2006.285.12:11:18.72#ibcon#read 4, iclass 28, count 2 2006.285.12:11:18.72#ibcon#about to read 5, iclass 28, count 2 2006.285.12:11:18.72#ibcon#read 5, iclass 28, count 2 2006.285.12:11:18.72#ibcon#about to read 6, iclass 28, count 2 2006.285.12:11:18.72#ibcon#read 6, iclass 28, count 2 2006.285.12:11:18.72#ibcon#end of sib2, iclass 28, count 2 2006.285.12:11:18.72#ibcon#*mode == 0, iclass 28, count 2 2006.285.12:11:18.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.12:11:18.72#ibcon#[25=AT01-07\r\n] 2006.285.12:11:18.72#ibcon#*before write, iclass 28, count 2 2006.285.12:11:18.72#ibcon#enter sib2, iclass 28, count 2 2006.285.12:11:18.72#ibcon#flushed, iclass 28, count 2 2006.285.12:11:18.72#ibcon#about to write, iclass 28, count 2 2006.285.12:11:18.72#ibcon#wrote, iclass 28, count 2 2006.285.12:11:18.72#ibcon#about to read 3, iclass 28, count 2 2006.285.12:11:18.75#ibcon#read 3, iclass 28, count 2 2006.285.12:11:18.75#ibcon#about to read 4, iclass 28, count 2 2006.285.12:11:18.75#ibcon#read 4, iclass 28, count 2 2006.285.12:11:18.75#ibcon#about to read 5, iclass 28, count 2 2006.285.12:11:18.75#ibcon#read 5, iclass 28, count 2 2006.285.12:11:18.75#ibcon#about to read 6, iclass 28, count 2 2006.285.12:11:18.75#ibcon#read 6, iclass 28, count 2 2006.285.12:11:18.75#ibcon#end of sib2, iclass 28, count 2 2006.285.12:11:18.75#ibcon#*after write, iclass 28, count 2 2006.285.12:11:18.75#ibcon#*before return 0, iclass 28, count 2 2006.285.12:11:18.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:11:18.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:11:18.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.12:11:18.75#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:18.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:11:18.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:11:18.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:11:18.87#ibcon#enter wrdev, iclass 28, count 0 2006.285.12:11:18.87#ibcon#first serial, iclass 28, count 0 2006.285.12:11:18.87#ibcon#enter sib2, iclass 28, count 0 2006.285.12:11:18.87#ibcon#flushed, iclass 28, count 0 2006.285.12:11:18.87#ibcon#about to write, iclass 28, count 0 2006.285.12:11:18.87#ibcon#wrote, iclass 28, count 0 2006.285.12:11:18.87#ibcon#about to read 3, iclass 28, count 0 2006.285.12:11:18.89#ibcon#read 3, iclass 28, count 0 2006.285.12:11:18.89#ibcon#about to read 4, iclass 28, count 0 2006.285.12:11:18.89#ibcon#read 4, iclass 28, count 0 2006.285.12:11:18.89#ibcon#about to read 5, iclass 28, count 0 2006.285.12:11:18.89#ibcon#read 5, iclass 28, count 0 2006.285.12:11:18.89#ibcon#about to read 6, iclass 28, count 0 2006.285.12:11:18.89#ibcon#read 6, iclass 28, count 0 2006.285.12:11:18.89#ibcon#end of sib2, iclass 28, count 0 2006.285.12:11:18.89#ibcon#*mode == 0, iclass 28, count 0 2006.285.12:11:18.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.12:11:18.89#ibcon#[25=USB\r\n] 2006.285.12:11:18.89#ibcon#*before write, iclass 28, count 0 2006.285.12:11:18.89#ibcon#enter sib2, iclass 28, count 0 2006.285.12:11:18.89#ibcon#flushed, iclass 28, count 0 2006.285.12:11:18.89#ibcon#about to write, iclass 28, count 0 2006.285.12:11:18.89#ibcon#wrote, iclass 28, count 0 2006.285.12:11:18.89#ibcon#about to read 3, iclass 28, count 0 2006.285.12:11:18.92#ibcon#read 3, iclass 28, count 0 2006.285.12:11:18.92#ibcon#about to read 4, iclass 28, count 0 2006.285.12:11:18.92#ibcon#read 4, iclass 28, count 0 2006.285.12:11:18.92#ibcon#about to read 5, iclass 28, count 0 2006.285.12:11:18.92#ibcon#read 5, iclass 28, count 0 2006.285.12:11:18.92#ibcon#about to read 6, iclass 28, count 0 2006.285.12:11:18.92#ibcon#read 6, iclass 28, count 0 2006.285.12:11:18.92#ibcon#end of sib2, iclass 28, count 0 2006.285.12:11:18.92#ibcon#*after write, iclass 28, count 0 2006.285.12:11:18.92#ibcon#*before return 0, iclass 28, count 0 2006.285.12:11:18.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:11:18.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:11:18.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.12:11:18.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.12:11:18.92$vck44/valo=2,534.99 2006.285.12:11:18.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.12:11:18.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.12:11:18.92#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:18.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:11:18.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:11:18.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:11:18.92#ibcon#enter wrdev, iclass 30, count 0 2006.285.12:11:18.92#ibcon#first serial, iclass 30, count 0 2006.285.12:11:18.92#ibcon#enter sib2, iclass 30, count 0 2006.285.12:11:18.92#ibcon#flushed, iclass 30, count 0 2006.285.12:11:18.92#ibcon#about to write, iclass 30, count 0 2006.285.12:11:18.92#ibcon#wrote, iclass 30, count 0 2006.285.12:11:18.92#ibcon#about to read 3, iclass 30, count 0 2006.285.12:11:18.94#ibcon#read 3, iclass 30, count 0 2006.285.12:11:18.94#ibcon#about to read 4, iclass 30, count 0 2006.285.12:11:18.94#ibcon#read 4, iclass 30, count 0 2006.285.12:11:18.94#ibcon#about to read 5, iclass 30, count 0 2006.285.12:11:18.94#ibcon#read 5, iclass 30, count 0 2006.285.12:11:18.94#ibcon#about to read 6, iclass 30, count 0 2006.285.12:11:18.94#ibcon#read 6, iclass 30, count 0 2006.285.12:11:18.94#ibcon#end of sib2, iclass 30, count 0 2006.285.12:11:18.94#ibcon#*mode == 0, iclass 30, count 0 2006.285.12:11:18.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.12:11:18.94#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.12:11:18.94#ibcon#*before write, iclass 30, count 0 2006.285.12:11:18.94#ibcon#enter sib2, iclass 30, count 0 2006.285.12:11:18.94#ibcon#flushed, iclass 30, count 0 2006.285.12:11:18.94#ibcon#about to write, iclass 30, count 0 2006.285.12:11:18.94#ibcon#wrote, iclass 30, count 0 2006.285.12:11:18.94#ibcon#about to read 3, iclass 30, count 0 2006.285.12:11:18.98#ibcon#read 3, iclass 30, count 0 2006.285.12:11:18.98#ibcon#about to read 4, iclass 30, count 0 2006.285.12:11:18.98#ibcon#read 4, iclass 30, count 0 2006.285.12:11:18.98#ibcon#about to read 5, iclass 30, count 0 2006.285.12:11:18.98#ibcon#read 5, iclass 30, count 0 2006.285.12:11:18.98#ibcon#about to read 6, iclass 30, count 0 2006.285.12:11:18.98#ibcon#read 6, iclass 30, count 0 2006.285.12:11:18.98#ibcon#end of sib2, iclass 30, count 0 2006.285.12:11:18.98#ibcon#*after write, iclass 30, count 0 2006.285.12:11:18.98#ibcon#*before return 0, iclass 30, count 0 2006.285.12:11:18.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:11:18.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:11:18.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.12:11:18.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.12:11:18.98$vck44/va=2,6 2006.285.12:11:18.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.12:11:18.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.12:11:18.98#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:18.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:11:19.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:11:19.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:11:19.04#ibcon#enter wrdev, iclass 32, count 2 2006.285.12:11:19.04#ibcon#first serial, iclass 32, count 2 2006.285.12:11:19.04#ibcon#enter sib2, iclass 32, count 2 2006.285.12:11:19.04#ibcon#flushed, iclass 32, count 2 2006.285.12:11:19.04#ibcon#about to write, iclass 32, count 2 2006.285.12:11:19.04#ibcon#wrote, iclass 32, count 2 2006.285.12:11:19.04#ibcon#about to read 3, iclass 32, count 2 2006.285.12:11:19.06#ibcon#read 3, iclass 32, count 2 2006.285.12:11:19.06#ibcon#about to read 4, iclass 32, count 2 2006.285.12:11:19.06#ibcon#read 4, iclass 32, count 2 2006.285.12:11:19.06#ibcon#about to read 5, iclass 32, count 2 2006.285.12:11:19.06#ibcon#read 5, iclass 32, count 2 2006.285.12:11:19.06#ibcon#about to read 6, iclass 32, count 2 2006.285.12:11:19.06#ibcon#read 6, iclass 32, count 2 2006.285.12:11:19.06#ibcon#end of sib2, iclass 32, count 2 2006.285.12:11:19.06#ibcon#*mode == 0, iclass 32, count 2 2006.285.12:11:19.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.12:11:19.06#ibcon#[25=AT02-06\r\n] 2006.285.12:11:19.06#ibcon#*before write, iclass 32, count 2 2006.285.12:11:19.06#ibcon#enter sib2, iclass 32, count 2 2006.285.12:11:19.06#ibcon#flushed, iclass 32, count 2 2006.285.12:11:19.06#ibcon#about to write, iclass 32, count 2 2006.285.12:11:19.06#ibcon#wrote, iclass 32, count 2 2006.285.12:11:19.06#ibcon#about to read 3, iclass 32, count 2 2006.285.12:11:19.09#ibcon#read 3, iclass 32, count 2 2006.285.12:11:19.09#ibcon#about to read 4, iclass 32, count 2 2006.285.12:11:19.09#ibcon#read 4, iclass 32, count 2 2006.285.12:11:19.09#ibcon#about to read 5, iclass 32, count 2 2006.285.12:11:19.09#ibcon#read 5, iclass 32, count 2 2006.285.12:11:19.09#ibcon#about to read 6, iclass 32, count 2 2006.285.12:11:19.09#ibcon#read 6, iclass 32, count 2 2006.285.12:11:19.09#ibcon#end of sib2, iclass 32, count 2 2006.285.12:11:19.09#ibcon#*after write, iclass 32, count 2 2006.285.12:11:19.09#ibcon#*before return 0, iclass 32, count 2 2006.285.12:11:19.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:11:19.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:11:19.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.12:11:19.09#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:19.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:11:19.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:11:19.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:11:19.21#ibcon#enter wrdev, iclass 32, count 0 2006.285.12:11:19.21#ibcon#first serial, iclass 32, count 0 2006.285.12:11:19.21#ibcon#enter sib2, iclass 32, count 0 2006.285.12:11:19.21#ibcon#flushed, iclass 32, count 0 2006.285.12:11:19.21#ibcon#about to write, iclass 32, count 0 2006.285.12:11:19.21#ibcon#wrote, iclass 32, count 0 2006.285.12:11:19.21#ibcon#about to read 3, iclass 32, count 0 2006.285.12:11:19.23#ibcon#read 3, iclass 32, count 0 2006.285.12:11:19.23#ibcon#about to read 4, iclass 32, count 0 2006.285.12:11:19.23#ibcon#read 4, iclass 32, count 0 2006.285.12:11:19.23#ibcon#about to read 5, iclass 32, count 0 2006.285.12:11:19.23#ibcon#read 5, iclass 32, count 0 2006.285.12:11:19.23#ibcon#about to read 6, iclass 32, count 0 2006.285.12:11:19.23#ibcon#read 6, iclass 32, count 0 2006.285.12:11:19.23#ibcon#end of sib2, iclass 32, count 0 2006.285.12:11:19.23#ibcon#*mode == 0, iclass 32, count 0 2006.285.12:11:19.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.12:11:19.23#ibcon#[25=USB\r\n] 2006.285.12:11:19.23#ibcon#*before write, iclass 32, count 0 2006.285.12:11:19.23#ibcon#enter sib2, iclass 32, count 0 2006.285.12:11:19.23#ibcon#flushed, iclass 32, count 0 2006.285.12:11:19.23#ibcon#about to write, iclass 32, count 0 2006.285.12:11:19.23#ibcon#wrote, iclass 32, count 0 2006.285.12:11:19.23#ibcon#about to read 3, iclass 32, count 0 2006.285.12:11:19.26#ibcon#read 3, iclass 32, count 0 2006.285.12:11:19.26#ibcon#about to read 4, iclass 32, count 0 2006.285.12:11:19.26#ibcon#read 4, iclass 32, count 0 2006.285.12:11:19.26#ibcon#about to read 5, iclass 32, count 0 2006.285.12:11:19.26#ibcon#read 5, iclass 32, count 0 2006.285.12:11:19.26#ibcon#about to read 6, iclass 32, count 0 2006.285.12:11:19.26#ibcon#read 6, iclass 32, count 0 2006.285.12:11:19.26#ibcon#end of sib2, iclass 32, count 0 2006.285.12:11:19.26#ibcon#*after write, iclass 32, count 0 2006.285.12:11:19.26#ibcon#*before return 0, iclass 32, count 0 2006.285.12:11:19.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:11:19.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:11:19.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.12:11:19.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.12:11:19.26$vck44/valo=3,564.99 2006.285.12:11:19.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.12:11:19.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.12:11:19.26#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:19.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:11:19.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:11:19.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:11:19.26#ibcon#enter wrdev, iclass 34, count 0 2006.285.12:11:19.26#ibcon#first serial, iclass 34, count 0 2006.285.12:11:19.26#ibcon#enter sib2, iclass 34, count 0 2006.285.12:11:19.26#ibcon#flushed, iclass 34, count 0 2006.285.12:11:19.26#ibcon#about to write, iclass 34, count 0 2006.285.12:11:19.26#ibcon#wrote, iclass 34, count 0 2006.285.12:11:19.26#ibcon#about to read 3, iclass 34, count 0 2006.285.12:11:19.28#ibcon#read 3, iclass 34, count 0 2006.285.12:11:19.28#ibcon#about to read 4, iclass 34, count 0 2006.285.12:11:19.28#ibcon#read 4, iclass 34, count 0 2006.285.12:11:19.28#ibcon#about to read 5, iclass 34, count 0 2006.285.12:11:19.28#ibcon#read 5, iclass 34, count 0 2006.285.12:11:19.28#ibcon#about to read 6, iclass 34, count 0 2006.285.12:11:19.28#ibcon#read 6, iclass 34, count 0 2006.285.12:11:19.28#ibcon#end of sib2, iclass 34, count 0 2006.285.12:11:19.28#ibcon#*mode == 0, iclass 34, count 0 2006.285.12:11:19.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.12:11:19.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.12:11:19.28#ibcon#*before write, iclass 34, count 0 2006.285.12:11:19.28#ibcon#enter sib2, iclass 34, count 0 2006.285.12:11:19.28#ibcon#flushed, iclass 34, count 0 2006.285.12:11:19.28#ibcon#about to write, iclass 34, count 0 2006.285.12:11:19.28#ibcon#wrote, iclass 34, count 0 2006.285.12:11:19.28#ibcon#about to read 3, iclass 34, count 0 2006.285.12:11:19.32#ibcon#read 3, iclass 34, count 0 2006.285.12:11:19.32#ibcon#about to read 4, iclass 34, count 0 2006.285.12:11:19.32#ibcon#read 4, iclass 34, count 0 2006.285.12:11:19.32#ibcon#about to read 5, iclass 34, count 0 2006.285.12:11:19.32#ibcon#read 5, iclass 34, count 0 2006.285.12:11:19.32#ibcon#about to read 6, iclass 34, count 0 2006.285.12:11:19.32#ibcon#read 6, iclass 34, count 0 2006.285.12:11:19.32#ibcon#end of sib2, iclass 34, count 0 2006.285.12:11:19.32#ibcon#*after write, iclass 34, count 0 2006.285.12:11:19.32#ibcon#*before return 0, iclass 34, count 0 2006.285.12:11:19.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:11:19.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:11:19.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.12:11:19.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.12:11:19.32$vck44/va=3,7 2006.285.12:11:19.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.12:11:19.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.12:11:19.32#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:19.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:11:19.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:11:19.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:11:19.38#ibcon#enter wrdev, iclass 36, count 2 2006.285.12:11:19.38#ibcon#first serial, iclass 36, count 2 2006.285.12:11:19.38#ibcon#enter sib2, iclass 36, count 2 2006.285.12:11:19.38#ibcon#flushed, iclass 36, count 2 2006.285.12:11:19.38#ibcon#about to write, iclass 36, count 2 2006.285.12:11:19.38#ibcon#wrote, iclass 36, count 2 2006.285.12:11:19.38#ibcon#about to read 3, iclass 36, count 2 2006.285.12:11:19.40#ibcon#read 3, iclass 36, count 2 2006.285.12:11:19.40#ibcon#about to read 4, iclass 36, count 2 2006.285.12:11:19.40#ibcon#read 4, iclass 36, count 2 2006.285.12:11:19.40#ibcon#about to read 5, iclass 36, count 2 2006.285.12:11:19.40#ibcon#read 5, iclass 36, count 2 2006.285.12:11:19.40#ibcon#about to read 6, iclass 36, count 2 2006.285.12:11:19.40#ibcon#read 6, iclass 36, count 2 2006.285.12:11:19.40#ibcon#end of sib2, iclass 36, count 2 2006.285.12:11:19.40#ibcon#*mode == 0, iclass 36, count 2 2006.285.12:11:19.40#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.12:11:19.40#ibcon#[25=AT03-07\r\n] 2006.285.12:11:19.40#ibcon#*before write, iclass 36, count 2 2006.285.12:11:19.40#ibcon#enter sib2, iclass 36, count 2 2006.285.12:11:19.40#ibcon#flushed, iclass 36, count 2 2006.285.12:11:19.40#ibcon#about to write, iclass 36, count 2 2006.285.12:11:19.40#ibcon#wrote, iclass 36, count 2 2006.285.12:11:19.40#ibcon#about to read 3, iclass 36, count 2 2006.285.12:11:19.43#ibcon#read 3, iclass 36, count 2 2006.285.12:11:19.43#ibcon#about to read 4, iclass 36, count 2 2006.285.12:11:19.43#ibcon#read 4, iclass 36, count 2 2006.285.12:11:19.43#ibcon#about to read 5, iclass 36, count 2 2006.285.12:11:19.43#ibcon#read 5, iclass 36, count 2 2006.285.12:11:19.43#ibcon#about to read 6, iclass 36, count 2 2006.285.12:11:19.43#ibcon#read 6, iclass 36, count 2 2006.285.12:11:19.43#ibcon#end of sib2, iclass 36, count 2 2006.285.12:11:19.43#ibcon#*after write, iclass 36, count 2 2006.285.12:11:19.43#ibcon#*before return 0, iclass 36, count 2 2006.285.12:11:19.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:11:19.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:11:19.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.12:11:19.43#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:19.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:11:19.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:11:19.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:11:19.55#ibcon#enter wrdev, iclass 36, count 0 2006.285.12:11:19.55#ibcon#first serial, iclass 36, count 0 2006.285.12:11:19.55#ibcon#enter sib2, iclass 36, count 0 2006.285.12:11:19.55#ibcon#flushed, iclass 36, count 0 2006.285.12:11:19.55#ibcon#about to write, iclass 36, count 0 2006.285.12:11:19.55#ibcon#wrote, iclass 36, count 0 2006.285.12:11:19.55#ibcon#about to read 3, iclass 36, count 0 2006.285.12:11:19.57#ibcon#read 3, iclass 36, count 0 2006.285.12:11:19.57#ibcon#about to read 4, iclass 36, count 0 2006.285.12:11:19.57#ibcon#read 4, iclass 36, count 0 2006.285.12:11:19.57#ibcon#about to read 5, iclass 36, count 0 2006.285.12:11:19.57#ibcon#read 5, iclass 36, count 0 2006.285.12:11:19.57#ibcon#about to read 6, iclass 36, count 0 2006.285.12:11:19.57#ibcon#read 6, iclass 36, count 0 2006.285.12:11:19.57#ibcon#end of sib2, iclass 36, count 0 2006.285.12:11:19.57#ibcon#*mode == 0, iclass 36, count 0 2006.285.12:11:19.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.12:11:19.57#ibcon#[25=USB\r\n] 2006.285.12:11:19.57#ibcon#*before write, iclass 36, count 0 2006.285.12:11:19.57#ibcon#enter sib2, iclass 36, count 0 2006.285.12:11:19.57#ibcon#flushed, iclass 36, count 0 2006.285.12:11:19.57#ibcon#about to write, iclass 36, count 0 2006.285.12:11:19.57#ibcon#wrote, iclass 36, count 0 2006.285.12:11:19.57#ibcon#about to read 3, iclass 36, count 0 2006.285.12:11:19.60#ibcon#read 3, iclass 36, count 0 2006.285.12:11:19.60#ibcon#about to read 4, iclass 36, count 0 2006.285.12:11:19.60#ibcon#read 4, iclass 36, count 0 2006.285.12:11:19.60#ibcon#about to read 5, iclass 36, count 0 2006.285.12:11:19.60#ibcon#read 5, iclass 36, count 0 2006.285.12:11:19.60#ibcon#about to read 6, iclass 36, count 0 2006.285.12:11:19.60#ibcon#read 6, iclass 36, count 0 2006.285.12:11:19.60#ibcon#end of sib2, iclass 36, count 0 2006.285.12:11:19.60#ibcon#*after write, iclass 36, count 0 2006.285.12:11:19.60#ibcon#*before return 0, iclass 36, count 0 2006.285.12:11:19.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:11:19.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:11:19.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.12:11:19.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.12:11:19.60$vck44/valo=4,624.99 2006.285.12:11:19.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.12:11:19.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.12:11:19.60#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:19.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:11:19.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:11:19.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:11:19.60#ibcon#enter wrdev, iclass 38, count 0 2006.285.12:11:19.60#ibcon#first serial, iclass 38, count 0 2006.285.12:11:19.60#ibcon#enter sib2, iclass 38, count 0 2006.285.12:11:19.60#ibcon#flushed, iclass 38, count 0 2006.285.12:11:19.60#ibcon#about to write, iclass 38, count 0 2006.285.12:11:19.60#ibcon#wrote, iclass 38, count 0 2006.285.12:11:19.60#ibcon#about to read 3, iclass 38, count 0 2006.285.12:11:19.62#ibcon#read 3, iclass 38, count 0 2006.285.12:11:19.62#ibcon#about to read 4, iclass 38, count 0 2006.285.12:11:19.62#ibcon#read 4, iclass 38, count 0 2006.285.12:11:19.62#ibcon#about to read 5, iclass 38, count 0 2006.285.12:11:19.62#ibcon#read 5, iclass 38, count 0 2006.285.12:11:19.62#ibcon#about to read 6, iclass 38, count 0 2006.285.12:11:19.62#ibcon#read 6, iclass 38, count 0 2006.285.12:11:19.62#ibcon#end of sib2, iclass 38, count 0 2006.285.12:11:19.62#ibcon#*mode == 0, iclass 38, count 0 2006.285.12:11:19.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.12:11:19.62#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.12:11:19.62#ibcon#*before write, iclass 38, count 0 2006.285.12:11:19.62#ibcon#enter sib2, iclass 38, count 0 2006.285.12:11:19.62#ibcon#flushed, iclass 38, count 0 2006.285.12:11:19.62#ibcon#about to write, iclass 38, count 0 2006.285.12:11:19.62#ibcon#wrote, iclass 38, count 0 2006.285.12:11:19.62#ibcon#about to read 3, iclass 38, count 0 2006.285.12:11:19.66#ibcon#read 3, iclass 38, count 0 2006.285.12:11:19.66#ibcon#about to read 4, iclass 38, count 0 2006.285.12:11:19.66#ibcon#read 4, iclass 38, count 0 2006.285.12:11:19.66#ibcon#about to read 5, iclass 38, count 0 2006.285.12:11:19.66#ibcon#read 5, iclass 38, count 0 2006.285.12:11:19.66#ibcon#about to read 6, iclass 38, count 0 2006.285.12:11:19.66#ibcon#read 6, iclass 38, count 0 2006.285.12:11:19.66#ibcon#end of sib2, iclass 38, count 0 2006.285.12:11:19.66#ibcon#*after write, iclass 38, count 0 2006.285.12:11:19.66#ibcon#*before return 0, iclass 38, count 0 2006.285.12:11:19.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:11:19.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:11:19.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.12:11:19.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.12:11:19.66$vck44/va=4,6 2006.285.12:11:19.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.12:11:19.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.12:11:19.66#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:19.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:11:19.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:11:19.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:11:19.72#ibcon#enter wrdev, iclass 40, count 2 2006.285.12:11:19.72#ibcon#first serial, iclass 40, count 2 2006.285.12:11:19.72#ibcon#enter sib2, iclass 40, count 2 2006.285.12:11:19.72#ibcon#flushed, iclass 40, count 2 2006.285.12:11:19.72#ibcon#about to write, iclass 40, count 2 2006.285.12:11:19.72#ibcon#wrote, iclass 40, count 2 2006.285.12:11:19.72#ibcon#about to read 3, iclass 40, count 2 2006.285.12:11:19.74#ibcon#read 3, iclass 40, count 2 2006.285.12:11:19.74#ibcon#about to read 4, iclass 40, count 2 2006.285.12:11:19.74#ibcon#read 4, iclass 40, count 2 2006.285.12:11:19.74#ibcon#about to read 5, iclass 40, count 2 2006.285.12:11:19.74#ibcon#read 5, iclass 40, count 2 2006.285.12:11:19.74#ibcon#about to read 6, iclass 40, count 2 2006.285.12:11:19.74#ibcon#read 6, iclass 40, count 2 2006.285.12:11:19.74#ibcon#end of sib2, iclass 40, count 2 2006.285.12:11:19.74#ibcon#*mode == 0, iclass 40, count 2 2006.285.12:11:19.74#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.12:11:19.74#ibcon#[25=AT04-06\r\n] 2006.285.12:11:19.74#ibcon#*before write, iclass 40, count 2 2006.285.12:11:19.74#ibcon#enter sib2, iclass 40, count 2 2006.285.12:11:19.74#ibcon#flushed, iclass 40, count 2 2006.285.12:11:19.74#ibcon#about to write, iclass 40, count 2 2006.285.12:11:19.74#ibcon#wrote, iclass 40, count 2 2006.285.12:11:19.74#ibcon#about to read 3, iclass 40, count 2 2006.285.12:11:19.77#ibcon#read 3, iclass 40, count 2 2006.285.12:11:19.77#ibcon#about to read 4, iclass 40, count 2 2006.285.12:11:19.77#ibcon#read 4, iclass 40, count 2 2006.285.12:11:19.77#ibcon#about to read 5, iclass 40, count 2 2006.285.12:11:19.77#ibcon#read 5, iclass 40, count 2 2006.285.12:11:19.77#ibcon#about to read 6, iclass 40, count 2 2006.285.12:11:19.77#ibcon#read 6, iclass 40, count 2 2006.285.12:11:19.77#ibcon#end of sib2, iclass 40, count 2 2006.285.12:11:19.77#ibcon#*after write, iclass 40, count 2 2006.285.12:11:19.77#ibcon#*before return 0, iclass 40, count 2 2006.285.12:11:19.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:11:19.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:11:19.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.12:11:19.77#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:19.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:11:19.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:11:19.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:11:19.89#ibcon#enter wrdev, iclass 40, count 0 2006.285.12:11:19.89#ibcon#first serial, iclass 40, count 0 2006.285.12:11:19.89#ibcon#enter sib2, iclass 40, count 0 2006.285.12:11:19.89#ibcon#flushed, iclass 40, count 0 2006.285.12:11:19.89#ibcon#about to write, iclass 40, count 0 2006.285.12:11:19.89#ibcon#wrote, iclass 40, count 0 2006.285.12:11:19.89#ibcon#about to read 3, iclass 40, count 0 2006.285.12:11:19.91#ibcon#read 3, iclass 40, count 0 2006.285.12:11:19.91#ibcon#about to read 4, iclass 40, count 0 2006.285.12:11:19.91#ibcon#read 4, iclass 40, count 0 2006.285.12:11:19.91#ibcon#about to read 5, iclass 40, count 0 2006.285.12:11:19.91#ibcon#read 5, iclass 40, count 0 2006.285.12:11:19.91#ibcon#about to read 6, iclass 40, count 0 2006.285.12:11:19.91#ibcon#read 6, iclass 40, count 0 2006.285.12:11:19.91#ibcon#end of sib2, iclass 40, count 0 2006.285.12:11:19.91#ibcon#*mode == 0, iclass 40, count 0 2006.285.12:11:19.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.12:11:19.91#ibcon#[25=USB\r\n] 2006.285.12:11:19.91#ibcon#*before write, iclass 40, count 0 2006.285.12:11:19.91#ibcon#enter sib2, iclass 40, count 0 2006.285.12:11:19.91#ibcon#flushed, iclass 40, count 0 2006.285.12:11:19.91#ibcon#about to write, iclass 40, count 0 2006.285.12:11:19.91#ibcon#wrote, iclass 40, count 0 2006.285.12:11:19.91#ibcon#about to read 3, iclass 40, count 0 2006.285.12:11:19.94#ibcon#read 3, iclass 40, count 0 2006.285.12:11:19.94#ibcon#about to read 4, iclass 40, count 0 2006.285.12:11:19.94#ibcon#read 4, iclass 40, count 0 2006.285.12:11:19.94#ibcon#about to read 5, iclass 40, count 0 2006.285.12:11:19.94#ibcon#read 5, iclass 40, count 0 2006.285.12:11:19.94#ibcon#about to read 6, iclass 40, count 0 2006.285.12:11:19.94#ibcon#read 6, iclass 40, count 0 2006.285.12:11:19.94#ibcon#end of sib2, iclass 40, count 0 2006.285.12:11:19.94#ibcon#*after write, iclass 40, count 0 2006.285.12:11:19.94#ibcon#*before return 0, iclass 40, count 0 2006.285.12:11:19.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:11:19.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:11:19.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.12:11:19.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.12:11:19.94$vck44/valo=5,734.99 2006.285.12:11:19.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.12:11:19.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.12:11:19.94#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:19.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:11:19.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:11:19.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:11:19.94#ibcon#enter wrdev, iclass 4, count 0 2006.285.12:11:19.94#ibcon#first serial, iclass 4, count 0 2006.285.12:11:19.94#ibcon#enter sib2, iclass 4, count 0 2006.285.12:11:19.94#ibcon#flushed, iclass 4, count 0 2006.285.12:11:19.94#ibcon#about to write, iclass 4, count 0 2006.285.12:11:19.94#ibcon#wrote, iclass 4, count 0 2006.285.12:11:19.94#ibcon#about to read 3, iclass 4, count 0 2006.285.12:11:19.96#ibcon#read 3, iclass 4, count 0 2006.285.12:11:19.96#ibcon#about to read 4, iclass 4, count 0 2006.285.12:11:19.96#ibcon#read 4, iclass 4, count 0 2006.285.12:11:19.96#ibcon#about to read 5, iclass 4, count 0 2006.285.12:11:19.96#ibcon#read 5, iclass 4, count 0 2006.285.12:11:19.96#ibcon#about to read 6, iclass 4, count 0 2006.285.12:11:19.96#ibcon#read 6, iclass 4, count 0 2006.285.12:11:19.96#ibcon#end of sib2, iclass 4, count 0 2006.285.12:11:19.96#ibcon#*mode == 0, iclass 4, count 0 2006.285.12:11:19.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.12:11:19.96#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.12:11:19.96#ibcon#*before write, iclass 4, count 0 2006.285.12:11:19.96#ibcon#enter sib2, iclass 4, count 0 2006.285.12:11:19.96#ibcon#flushed, iclass 4, count 0 2006.285.12:11:19.96#ibcon#about to write, iclass 4, count 0 2006.285.12:11:19.96#ibcon#wrote, iclass 4, count 0 2006.285.12:11:19.96#ibcon#about to read 3, iclass 4, count 0 2006.285.12:11:20.00#ibcon#read 3, iclass 4, count 0 2006.285.12:11:20.00#ibcon#about to read 4, iclass 4, count 0 2006.285.12:11:20.00#ibcon#read 4, iclass 4, count 0 2006.285.12:11:20.00#ibcon#about to read 5, iclass 4, count 0 2006.285.12:11:20.00#ibcon#read 5, iclass 4, count 0 2006.285.12:11:20.00#ibcon#about to read 6, iclass 4, count 0 2006.285.12:11:20.00#ibcon#read 6, iclass 4, count 0 2006.285.12:11:20.00#ibcon#end of sib2, iclass 4, count 0 2006.285.12:11:20.00#ibcon#*after write, iclass 4, count 0 2006.285.12:11:20.00#ibcon#*before return 0, iclass 4, count 0 2006.285.12:11:20.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:11:20.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:11:20.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.12:11:20.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.12:11:20.00$vck44/va=5,3 2006.285.12:11:20.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.12:11:20.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.12:11:20.00#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:20.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:11:20.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:11:20.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:11:20.06#ibcon#enter wrdev, iclass 6, count 2 2006.285.12:11:20.06#ibcon#first serial, iclass 6, count 2 2006.285.12:11:20.06#ibcon#enter sib2, iclass 6, count 2 2006.285.12:11:20.06#ibcon#flushed, iclass 6, count 2 2006.285.12:11:20.06#ibcon#about to write, iclass 6, count 2 2006.285.12:11:20.06#ibcon#wrote, iclass 6, count 2 2006.285.12:11:20.06#ibcon#about to read 3, iclass 6, count 2 2006.285.12:11:20.08#ibcon#read 3, iclass 6, count 2 2006.285.12:11:20.08#ibcon#about to read 4, iclass 6, count 2 2006.285.12:11:20.08#ibcon#read 4, iclass 6, count 2 2006.285.12:11:20.08#ibcon#about to read 5, iclass 6, count 2 2006.285.12:11:20.08#ibcon#read 5, iclass 6, count 2 2006.285.12:11:20.08#ibcon#about to read 6, iclass 6, count 2 2006.285.12:11:20.08#ibcon#read 6, iclass 6, count 2 2006.285.12:11:20.08#ibcon#end of sib2, iclass 6, count 2 2006.285.12:11:20.08#ibcon#*mode == 0, iclass 6, count 2 2006.285.12:11:20.08#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.12:11:20.08#ibcon#[25=AT05-03\r\n] 2006.285.12:11:20.08#ibcon#*before write, iclass 6, count 2 2006.285.12:11:20.08#ibcon#enter sib2, iclass 6, count 2 2006.285.12:11:20.08#ibcon#flushed, iclass 6, count 2 2006.285.12:11:20.08#ibcon#about to write, iclass 6, count 2 2006.285.12:11:20.08#ibcon#wrote, iclass 6, count 2 2006.285.12:11:20.08#ibcon#about to read 3, iclass 6, count 2 2006.285.12:11:20.11#ibcon#read 3, iclass 6, count 2 2006.285.12:11:20.11#ibcon#about to read 4, iclass 6, count 2 2006.285.12:11:20.11#ibcon#read 4, iclass 6, count 2 2006.285.12:11:20.11#ibcon#about to read 5, iclass 6, count 2 2006.285.12:11:20.11#ibcon#read 5, iclass 6, count 2 2006.285.12:11:20.11#ibcon#about to read 6, iclass 6, count 2 2006.285.12:11:20.11#ibcon#read 6, iclass 6, count 2 2006.285.12:11:20.11#ibcon#end of sib2, iclass 6, count 2 2006.285.12:11:20.11#ibcon#*after write, iclass 6, count 2 2006.285.12:11:20.11#ibcon#*before return 0, iclass 6, count 2 2006.285.12:11:20.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:11:20.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:11:20.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.12:11:20.11#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:20.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:11:20.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:11:20.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:11:20.23#ibcon#enter wrdev, iclass 6, count 0 2006.285.12:11:20.23#ibcon#first serial, iclass 6, count 0 2006.285.12:11:20.23#ibcon#enter sib2, iclass 6, count 0 2006.285.12:11:20.23#ibcon#flushed, iclass 6, count 0 2006.285.12:11:20.23#ibcon#about to write, iclass 6, count 0 2006.285.12:11:20.23#ibcon#wrote, iclass 6, count 0 2006.285.12:11:20.23#ibcon#about to read 3, iclass 6, count 0 2006.285.12:11:20.25#ibcon#read 3, iclass 6, count 0 2006.285.12:11:20.25#ibcon#about to read 4, iclass 6, count 0 2006.285.12:11:20.25#ibcon#read 4, iclass 6, count 0 2006.285.12:11:20.25#ibcon#about to read 5, iclass 6, count 0 2006.285.12:11:20.25#ibcon#read 5, iclass 6, count 0 2006.285.12:11:20.25#ibcon#about to read 6, iclass 6, count 0 2006.285.12:11:20.25#ibcon#read 6, iclass 6, count 0 2006.285.12:11:20.25#ibcon#end of sib2, iclass 6, count 0 2006.285.12:11:20.25#ibcon#*mode == 0, iclass 6, count 0 2006.285.12:11:20.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.12:11:20.25#ibcon#[25=USB\r\n] 2006.285.12:11:20.25#ibcon#*before write, iclass 6, count 0 2006.285.12:11:20.25#ibcon#enter sib2, iclass 6, count 0 2006.285.12:11:20.25#ibcon#flushed, iclass 6, count 0 2006.285.12:11:20.25#ibcon#about to write, iclass 6, count 0 2006.285.12:11:20.25#ibcon#wrote, iclass 6, count 0 2006.285.12:11:20.25#ibcon#about to read 3, iclass 6, count 0 2006.285.12:11:20.28#ibcon#read 3, iclass 6, count 0 2006.285.12:11:20.28#ibcon#about to read 4, iclass 6, count 0 2006.285.12:11:20.28#ibcon#read 4, iclass 6, count 0 2006.285.12:11:20.28#ibcon#about to read 5, iclass 6, count 0 2006.285.12:11:20.28#ibcon#read 5, iclass 6, count 0 2006.285.12:11:20.28#ibcon#about to read 6, iclass 6, count 0 2006.285.12:11:20.28#ibcon#read 6, iclass 6, count 0 2006.285.12:11:20.28#ibcon#end of sib2, iclass 6, count 0 2006.285.12:11:20.28#ibcon#*after write, iclass 6, count 0 2006.285.12:11:20.28#ibcon#*before return 0, iclass 6, count 0 2006.285.12:11:20.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:11:20.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:11:20.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.12:11:20.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.12:11:20.28$vck44/valo=6,814.99 2006.285.12:11:20.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.12:11:20.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.12:11:20.28#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:20.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:11:20.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:11:20.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:11:20.28#ibcon#enter wrdev, iclass 10, count 0 2006.285.12:11:20.28#ibcon#first serial, iclass 10, count 0 2006.285.12:11:20.28#ibcon#enter sib2, iclass 10, count 0 2006.285.12:11:20.28#ibcon#flushed, iclass 10, count 0 2006.285.12:11:20.28#ibcon#about to write, iclass 10, count 0 2006.285.12:11:20.28#ibcon#wrote, iclass 10, count 0 2006.285.12:11:20.28#ibcon#about to read 3, iclass 10, count 0 2006.285.12:11:20.30#ibcon#read 3, iclass 10, count 0 2006.285.12:11:20.30#ibcon#about to read 4, iclass 10, count 0 2006.285.12:11:20.30#ibcon#read 4, iclass 10, count 0 2006.285.12:11:20.30#ibcon#about to read 5, iclass 10, count 0 2006.285.12:11:20.30#ibcon#read 5, iclass 10, count 0 2006.285.12:11:20.30#ibcon#about to read 6, iclass 10, count 0 2006.285.12:11:20.30#ibcon#read 6, iclass 10, count 0 2006.285.12:11:20.30#ibcon#end of sib2, iclass 10, count 0 2006.285.12:11:20.30#ibcon#*mode == 0, iclass 10, count 0 2006.285.12:11:20.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.12:11:20.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.12:11:20.30#ibcon#*before write, iclass 10, count 0 2006.285.12:11:20.30#ibcon#enter sib2, iclass 10, count 0 2006.285.12:11:20.30#ibcon#flushed, iclass 10, count 0 2006.285.12:11:20.30#ibcon#about to write, iclass 10, count 0 2006.285.12:11:20.30#ibcon#wrote, iclass 10, count 0 2006.285.12:11:20.30#ibcon#about to read 3, iclass 10, count 0 2006.285.12:11:20.34#ibcon#read 3, iclass 10, count 0 2006.285.12:11:20.34#ibcon#about to read 4, iclass 10, count 0 2006.285.12:11:20.34#ibcon#read 4, iclass 10, count 0 2006.285.12:11:20.34#ibcon#about to read 5, iclass 10, count 0 2006.285.12:11:20.34#ibcon#read 5, iclass 10, count 0 2006.285.12:11:20.34#ibcon#about to read 6, iclass 10, count 0 2006.285.12:11:20.34#ibcon#read 6, iclass 10, count 0 2006.285.12:11:20.34#ibcon#end of sib2, iclass 10, count 0 2006.285.12:11:20.34#ibcon#*after write, iclass 10, count 0 2006.285.12:11:20.34#ibcon#*before return 0, iclass 10, count 0 2006.285.12:11:20.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:11:20.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:11:20.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.12:11:20.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.12:11:20.34$vck44/va=6,4 2006.285.12:11:20.34#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.12:11:20.34#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.12:11:20.34#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:20.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:11:20.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:11:20.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:11:20.40#ibcon#enter wrdev, iclass 12, count 2 2006.285.12:11:20.40#ibcon#first serial, iclass 12, count 2 2006.285.12:11:20.40#ibcon#enter sib2, iclass 12, count 2 2006.285.12:11:20.40#ibcon#flushed, iclass 12, count 2 2006.285.12:11:20.40#ibcon#about to write, iclass 12, count 2 2006.285.12:11:20.40#ibcon#wrote, iclass 12, count 2 2006.285.12:11:20.40#ibcon#about to read 3, iclass 12, count 2 2006.285.12:11:20.42#ibcon#read 3, iclass 12, count 2 2006.285.12:11:20.42#ibcon#about to read 4, iclass 12, count 2 2006.285.12:11:20.42#ibcon#read 4, iclass 12, count 2 2006.285.12:11:20.42#ibcon#about to read 5, iclass 12, count 2 2006.285.12:11:20.42#ibcon#read 5, iclass 12, count 2 2006.285.12:11:20.42#ibcon#about to read 6, iclass 12, count 2 2006.285.12:11:20.42#ibcon#read 6, iclass 12, count 2 2006.285.12:11:20.42#ibcon#end of sib2, iclass 12, count 2 2006.285.12:11:20.42#ibcon#*mode == 0, iclass 12, count 2 2006.285.12:11:20.42#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.12:11:20.42#ibcon#[25=AT06-04\r\n] 2006.285.12:11:20.42#ibcon#*before write, iclass 12, count 2 2006.285.12:11:20.42#ibcon#enter sib2, iclass 12, count 2 2006.285.12:11:20.42#ibcon#flushed, iclass 12, count 2 2006.285.12:11:20.42#ibcon#about to write, iclass 12, count 2 2006.285.12:11:20.42#ibcon#wrote, iclass 12, count 2 2006.285.12:11:20.42#ibcon#about to read 3, iclass 12, count 2 2006.285.12:11:20.45#ibcon#read 3, iclass 12, count 2 2006.285.12:11:20.45#ibcon#about to read 4, iclass 12, count 2 2006.285.12:11:20.45#ibcon#read 4, iclass 12, count 2 2006.285.12:11:20.45#ibcon#about to read 5, iclass 12, count 2 2006.285.12:11:20.45#ibcon#read 5, iclass 12, count 2 2006.285.12:11:20.45#ibcon#about to read 6, iclass 12, count 2 2006.285.12:11:20.45#ibcon#read 6, iclass 12, count 2 2006.285.12:11:20.45#ibcon#end of sib2, iclass 12, count 2 2006.285.12:11:20.45#ibcon#*after write, iclass 12, count 2 2006.285.12:11:20.45#ibcon#*before return 0, iclass 12, count 2 2006.285.12:11:20.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:11:20.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:11:20.45#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.12:11:20.45#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:20.45#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:11:20.57#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:11:20.57#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:11:20.57#ibcon#enter wrdev, iclass 12, count 0 2006.285.12:11:20.57#ibcon#first serial, iclass 12, count 0 2006.285.12:11:20.57#ibcon#enter sib2, iclass 12, count 0 2006.285.12:11:20.57#ibcon#flushed, iclass 12, count 0 2006.285.12:11:20.57#ibcon#about to write, iclass 12, count 0 2006.285.12:11:20.57#ibcon#wrote, iclass 12, count 0 2006.285.12:11:20.57#ibcon#about to read 3, iclass 12, count 0 2006.285.12:11:20.59#ibcon#read 3, iclass 12, count 0 2006.285.12:11:20.59#ibcon#about to read 4, iclass 12, count 0 2006.285.12:11:20.59#ibcon#read 4, iclass 12, count 0 2006.285.12:11:20.59#ibcon#about to read 5, iclass 12, count 0 2006.285.12:11:20.59#ibcon#read 5, iclass 12, count 0 2006.285.12:11:20.59#ibcon#about to read 6, iclass 12, count 0 2006.285.12:11:20.59#ibcon#read 6, iclass 12, count 0 2006.285.12:11:20.59#ibcon#end of sib2, iclass 12, count 0 2006.285.12:11:20.59#ibcon#*mode == 0, iclass 12, count 0 2006.285.12:11:20.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.12:11:20.59#ibcon#[25=USB\r\n] 2006.285.12:11:20.59#ibcon#*before write, iclass 12, count 0 2006.285.12:11:20.59#ibcon#enter sib2, iclass 12, count 0 2006.285.12:11:20.59#ibcon#flushed, iclass 12, count 0 2006.285.12:11:20.59#ibcon#about to write, iclass 12, count 0 2006.285.12:11:20.59#ibcon#wrote, iclass 12, count 0 2006.285.12:11:20.59#ibcon#about to read 3, iclass 12, count 0 2006.285.12:11:20.62#ibcon#read 3, iclass 12, count 0 2006.285.12:11:20.62#ibcon#about to read 4, iclass 12, count 0 2006.285.12:11:20.62#ibcon#read 4, iclass 12, count 0 2006.285.12:11:20.62#ibcon#about to read 5, iclass 12, count 0 2006.285.12:11:20.62#ibcon#read 5, iclass 12, count 0 2006.285.12:11:20.62#ibcon#about to read 6, iclass 12, count 0 2006.285.12:11:20.62#ibcon#read 6, iclass 12, count 0 2006.285.12:11:20.62#ibcon#end of sib2, iclass 12, count 0 2006.285.12:11:20.62#ibcon#*after write, iclass 12, count 0 2006.285.12:11:20.62#ibcon#*before return 0, iclass 12, count 0 2006.285.12:11:20.62#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:11:20.62#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:11:20.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.12:11:20.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.12:11:20.62$vck44/valo=7,864.99 2006.285.12:11:20.62#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.12:11:20.62#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.12:11:20.62#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:20.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:11:20.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:11:20.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:11:20.62#ibcon#enter wrdev, iclass 14, count 0 2006.285.12:11:20.62#ibcon#first serial, iclass 14, count 0 2006.285.12:11:20.62#ibcon#enter sib2, iclass 14, count 0 2006.285.12:11:20.62#ibcon#flushed, iclass 14, count 0 2006.285.12:11:20.62#ibcon#about to write, iclass 14, count 0 2006.285.12:11:20.62#ibcon#wrote, iclass 14, count 0 2006.285.12:11:20.62#ibcon#about to read 3, iclass 14, count 0 2006.285.12:11:20.64#ibcon#read 3, iclass 14, count 0 2006.285.12:11:20.64#ibcon#about to read 4, iclass 14, count 0 2006.285.12:11:20.64#ibcon#read 4, iclass 14, count 0 2006.285.12:11:20.64#ibcon#about to read 5, iclass 14, count 0 2006.285.12:11:20.64#ibcon#read 5, iclass 14, count 0 2006.285.12:11:20.64#ibcon#about to read 6, iclass 14, count 0 2006.285.12:11:20.64#ibcon#read 6, iclass 14, count 0 2006.285.12:11:20.64#ibcon#end of sib2, iclass 14, count 0 2006.285.12:11:20.64#ibcon#*mode == 0, iclass 14, count 0 2006.285.12:11:20.64#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.12:11:20.64#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.12:11:20.64#ibcon#*before write, iclass 14, count 0 2006.285.12:11:20.64#ibcon#enter sib2, iclass 14, count 0 2006.285.12:11:20.64#ibcon#flushed, iclass 14, count 0 2006.285.12:11:20.64#ibcon#about to write, iclass 14, count 0 2006.285.12:11:20.64#ibcon#wrote, iclass 14, count 0 2006.285.12:11:20.64#ibcon#about to read 3, iclass 14, count 0 2006.285.12:11:20.68#ibcon#read 3, iclass 14, count 0 2006.285.12:11:20.68#ibcon#about to read 4, iclass 14, count 0 2006.285.12:11:20.68#ibcon#read 4, iclass 14, count 0 2006.285.12:11:20.68#ibcon#about to read 5, iclass 14, count 0 2006.285.12:11:20.68#ibcon#read 5, iclass 14, count 0 2006.285.12:11:20.68#ibcon#about to read 6, iclass 14, count 0 2006.285.12:11:20.68#ibcon#read 6, iclass 14, count 0 2006.285.12:11:20.68#ibcon#end of sib2, iclass 14, count 0 2006.285.12:11:20.68#ibcon#*after write, iclass 14, count 0 2006.285.12:11:20.68#ibcon#*before return 0, iclass 14, count 0 2006.285.12:11:20.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:11:20.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:11:20.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.12:11:20.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.12:11:20.68$vck44/va=7,4 2006.285.12:11:20.68#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.12:11:20.68#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.12:11:20.68#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:20.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:11:20.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:11:20.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:11:20.74#ibcon#enter wrdev, iclass 16, count 2 2006.285.12:11:20.74#ibcon#first serial, iclass 16, count 2 2006.285.12:11:20.74#ibcon#enter sib2, iclass 16, count 2 2006.285.12:11:20.74#ibcon#flushed, iclass 16, count 2 2006.285.12:11:20.74#ibcon#about to write, iclass 16, count 2 2006.285.12:11:20.74#ibcon#wrote, iclass 16, count 2 2006.285.12:11:20.74#ibcon#about to read 3, iclass 16, count 2 2006.285.12:11:20.76#ibcon#read 3, iclass 16, count 2 2006.285.12:11:20.76#ibcon#about to read 4, iclass 16, count 2 2006.285.12:11:20.76#ibcon#read 4, iclass 16, count 2 2006.285.12:11:20.76#ibcon#about to read 5, iclass 16, count 2 2006.285.12:11:20.76#ibcon#read 5, iclass 16, count 2 2006.285.12:11:20.76#ibcon#about to read 6, iclass 16, count 2 2006.285.12:11:20.76#ibcon#read 6, iclass 16, count 2 2006.285.12:11:20.76#ibcon#end of sib2, iclass 16, count 2 2006.285.12:11:20.76#ibcon#*mode == 0, iclass 16, count 2 2006.285.12:11:20.76#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.12:11:20.76#ibcon#[25=AT07-04\r\n] 2006.285.12:11:20.76#ibcon#*before write, iclass 16, count 2 2006.285.12:11:20.76#ibcon#enter sib2, iclass 16, count 2 2006.285.12:11:20.76#ibcon#flushed, iclass 16, count 2 2006.285.12:11:20.76#ibcon#about to write, iclass 16, count 2 2006.285.12:11:20.76#ibcon#wrote, iclass 16, count 2 2006.285.12:11:20.76#ibcon#about to read 3, iclass 16, count 2 2006.285.12:11:20.79#ibcon#read 3, iclass 16, count 2 2006.285.12:11:20.79#ibcon#about to read 4, iclass 16, count 2 2006.285.12:11:20.79#ibcon#read 4, iclass 16, count 2 2006.285.12:11:20.79#ibcon#about to read 5, iclass 16, count 2 2006.285.12:11:20.79#ibcon#read 5, iclass 16, count 2 2006.285.12:11:20.79#ibcon#about to read 6, iclass 16, count 2 2006.285.12:11:20.79#ibcon#read 6, iclass 16, count 2 2006.285.12:11:20.79#ibcon#end of sib2, iclass 16, count 2 2006.285.12:11:20.79#ibcon#*after write, iclass 16, count 2 2006.285.12:11:20.79#ibcon#*before return 0, iclass 16, count 2 2006.285.12:11:20.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:11:20.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:11:20.79#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.12:11:20.79#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:20.79#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:11:20.91#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:11:20.91#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:11:20.91#ibcon#enter wrdev, iclass 16, count 0 2006.285.12:11:20.91#ibcon#first serial, iclass 16, count 0 2006.285.12:11:20.91#ibcon#enter sib2, iclass 16, count 0 2006.285.12:11:20.91#ibcon#flushed, iclass 16, count 0 2006.285.12:11:20.91#ibcon#about to write, iclass 16, count 0 2006.285.12:11:20.91#ibcon#wrote, iclass 16, count 0 2006.285.12:11:20.91#ibcon#about to read 3, iclass 16, count 0 2006.285.12:11:20.93#ibcon#read 3, iclass 16, count 0 2006.285.12:11:20.93#ibcon#about to read 4, iclass 16, count 0 2006.285.12:11:20.93#ibcon#read 4, iclass 16, count 0 2006.285.12:11:20.93#ibcon#about to read 5, iclass 16, count 0 2006.285.12:11:20.93#ibcon#read 5, iclass 16, count 0 2006.285.12:11:20.93#ibcon#about to read 6, iclass 16, count 0 2006.285.12:11:20.93#ibcon#read 6, iclass 16, count 0 2006.285.12:11:20.93#ibcon#end of sib2, iclass 16, count 0 2006.285.12:11:20.93#ibcon#*mode == 0, iclass 16, count 0 2006.285.12:11:20.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.12:11:20.93#ibcon#[25=USB\r\n] 2006.285.12:11:20.93#ibcon#*before write, iclass 16, count 0 2006.285.12:11:20.93#ibcon#enter sib2, iclass 16, count 0 2006.285.12:11:20.93#ibcon#flushed, iclass 16, count 0 2006.285.12:11:20.93#ibcon#about to write, iclass 16, count 0 2006.285.12:11:20.93#ibcon#wrote, iclass 16, count 0 2006.285.12:11:20.93#ibcon#about to read 3, iclass 16, count 0 2006.285.12:11:20.96#ibcon#read 3, iclass 16, count 0 2006.285.12:11:20.96#ibcon#about to read 4, iclass 16, count 0 2006.285.12:11:20.96#ibcon#read 4, iclass 16, count 0 2006.285.12:11:20.96#ibcon#about to read 5, iclass 16, count 0 2006.285.12:11:20.96#ibcon#read 5, iclass 16, count 0 2006.285.12:11:20.96#ibcon#about to read 6, iclass 16, count 0 2006.285.12:11:20.96#ibcon#read 6, iclass 16, count 0 2006.285.12:11:20.96#ibcon#end of sib2, iclass 16, count 0 2006.285.12:11:20.96#ibcon#*after write, iclass 16, count 0 2006.285.12:11:20.96#ibcon#*before return 0, iclass 16, count 0 2006.285.12:11:20.96#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:11:20.96#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:11:20.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.12:11:20.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.12:11:20.96$vck44/valo=8,884.99 2006.285.12:11:20.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.12:11:20.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.12:11:20.96#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:20.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:11:20.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:11:20.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:11:20.96#ibcon#enter wrdev, iclass 18, count 0 2006.285.12:11:20.96#ibcon#first serial, iclass 18, count 0 2006.285.12:11:20.96#ibcon#enter sib2, iclass 18, count 0 2006.285.12:11:20.96#ibcon#flushed, iclass 18, count 0 2006.285.12:11:20.96#ibcon#about to write, iclass 18, count 0 2006.285.12:11:20.96#ibcon#wrote, iclass 18, count 0 2006.285.12:11:20.96#ibcon#about to read 3, iclass 18, count 0 2006.285.12:11:20.98#ibcon#read 3, iclass 18, count 0 2006.285.12:11:20.98#ibcon#about to read 4, iclass 18, count 0 2006.285.12:11:20.98#ibcon#read 4, iclass 18, count 0 2006.285.12:11:20.98#ibcon#about to read 5, iclass 18, count 0 2006.285.12:11:20.98#ibcon#read 5, iclass 18, count 0 2006.285.12:11:20.98#ibcon#about to read 6, iclass 18, count 0 2006.285.12:11:20.98#ibcon#read 6, iclass 18, count 0 2006.285.12:11:20.98#ibcon#end of sib2, iclass 18, count 0 2006.285.12:11:20.98#ibcon#*mode == 0, iclass 18, count 0 2006.285.12:11:20.98#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.12:11:20.98#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.12:11:20.98#ibcon#*before write, iclass 18, count 0 2006.285.12:11:20.98#ibcon#enter sib2, iclass 18, count 0 2006.285.12:11:20.98#ibcon#flushed, iclass 18, count 0 2006.285.12:11:20.98#ibcon#about to write, iclass 18, count 0 2006.285.12:11:20.98#ibcon#wrote, iclass 18, count 0 2006.285.12:11:20.98#ibcon#about to read 3, iclass 18, count 0 2006.285.12:11:21.02#ibcon#read 3, iclass 18, count 0 2006.285.12:11:21.02#ibcon#about to read 4, iclass 18, count 0 2006.285.12:11:21.02#ibcon#read 4, iclass 18, count 0 2006.285.12:11:21.02#ibcon#about to read 5, iclass 18, count 0 2006.285.12:11:21.02#ibcon#read 5, iclass 18, count 0 2006.285.12:11:21.02#ibcon#about to read 6, iclass 18, count 0 2006.285.12:11:21.02#ibcon#read 6, iclass 18, count 0 2006.285.12:11:21.02#ibcon#end of sib2, iclass 18, count 0 2006.285.12:11:21.02#ibcon#*after write, iclass 18, count 0 2006.285.12:11:21.02#ibcon#*before return 0, iclass 18, count 0 2006.285.12:11:21.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:11:21.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:11:21.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.12:11:21.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.12:11:21.02$vck44/va=8,3 2006.285.12:11:21.02#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.12:11:21.02#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.12:11:21.02#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:21.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:11:21.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:11:21.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:11:21.08#ibcon#enter wrdev, iclass 20, count 2 2006.285.12:11:21.08#ibcon#first serial, iclass 20, count 2 2006.285.12:11:21.08#ibcon#enter sib2, iclass 20, count 2 2006.285.12:11:21.08#ibcon#flushed, iclass 20, count 2 2006.285.12:11:21.08#ibcon#about to write, iclass 20, count 2 2006.285.12:11:21.08#ibcon#wrote, iclass 20, count 2 2006.285.12:11:21.08#ibcon#about to read 3, iclass 20, count 2 2006.285.12:11:21.10#ibcon#read 3, iclass 20, count 2 2006.285.12:11:21.10#ibcon#about to read 4, iclass 20, count 2 2006.285.12:11:21.10#ibcon#read 4, iclass 20, count 2 2006.285.12:11:21.10#ibcon#about to read 5, iclass 20, count 2 2006.285.12:11:21.10#ibcon#read 5, iclass 20, count 2 2006.285.12:11:21.10#ibcon#about to read 6, iclass 20, count 2 2006.285.12:11:21.10#ibcon#read 6, iclass 20, count 2 2006.285.12:11:21.10#ibcon#end of sib2, iclass 20, count 2 2006.285.12:11:21.10#ibcon#*mode == 0, iclass 20, count 2 2006.285.12:11:21.10#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.12:11:21.10#ibcon#[25=AT08-03\r\n] 2006.285.12:11:21.10#ibcon#*before write, iclass 20, count 2 2006.285.12:11:21.10#ibcon#enter sib2, iclass 20, count 2 2006.285.12:11:21.10#ibcon#flushed, iclass 20, count 2 2006.285.12:11:21.10#ibcon#about to write, iclass 20, count 2 2006.285.12:11:21.10#ibcon#wrote, iclass 20, count 2 2006.285.12:11:21.10#ibcon#about to read 3, iclass 20, count 2 2006.285.12:11:21.13#ibcon#read 3, iclass 20, count 2 2006.285.12:11:21.13#ibcon#about to read 4, iclass 20, count 2 2006.285.12:11:21.13#ibcon#read 4, iclass 20, count 2 2006.285.12:11:21.13#ibcon#about to read 5, iclass 20, count 2 2006.285.12:11:21.13#ibcon#read 5, iclass 20, count 2 2006.285.12:11:21.13#ibcon#about to read 6, iclass 20, count 2 2006.285.12:11:21.13#ibcon#read 6, iclass 20, count 2 2006.285.12:11:21.13#ibcon#end of sib2, iclass 20, count 2 2006.285.12:11:21.13#ibcon#*after write, iclass 20, count 2 2006.285.12:11:21.13#ibcon#*before return 0, iclass 20, count 2 2006.285.12:11:21.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:11:21.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:11:21.13#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.12:11:21.13#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:21.13#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:11:21.25#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:11:21.25#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:11:21.25#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:11:21.25#ibcon#first serial, iclass 20, count 0 2006.285.12:11:21.25#ibcon#enter sib2, iclass 20, count 0 2006.285.12:11:21.25#ibcon#flushed, iclass 20, count 0 2006.285.12:11:21.25#ibcon#about to write, iclass 20, count 0 2006.285.12:11:21.25#ibcon#wrote, iclass 20, count 0 2006.285.12:11:21.25#ibcon#about to read 3, iclass 20, count 0 2006.285.12:11:21.27#ibcon#read 3, iclass 20, count 0 2006.285.12:11:21.27#ibcon#about to read 4, iclass 20, count 0 2006.285.12:11:21.27#ibcon#read 4, iclass 20, count 0 2006.285.12:11:21.27#ibcon#about to read 5, iclass 20, count 0 2006.285.12:11:21.27#ibcon#read 5, iclass 20, count 0 2006.285.12:11:21.27#ibcon#about to read 6, iclass 20, count 0 2006.285.12:11:21.27#ibcon#read 6, iclass 20, count 0 2006.285.12:11:21.27#ibcon#end of sib2, iclass 20, count 0 2006.285.12:11:21.27#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:11:21.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:11:21.27#ibcon#[25=USB\r\n] 2006.285.12:11:21.27#ibcon#*before write, iclass 20, count 0 2006.285.12:11:21.27#ibcon#enter sib2, iclass 20, count 0 2006.285.12:11:21.27#ibcon#flushed, iclass 20, count 0 2006.285.12:11:21.27#ibcon#about to write, iclass 20, count 0 2006.285.12:11:21.27#ibcon#wrote, iclass 20, count 0 2006.285.12:11:21.27#ibcon#about to read 3, iclass 20, count 0 2006.285.12:11:21.30#ibcon#read 3, iclass 20, count 0 2006.285.12:11:21.30#ibcon#about to read 4, iclass 20, count 0 2006.285.12:11:21.30#ibcon#read 4, iclass 20, count 0 2006.285.12:11:21.30#ibcon#about to read 5, iclass 20, count 0 2006.285.12:11:21.30#ibcon#read 5, iclass 20, count 0 2006.285.12:11:21.30#ibcon#about to read 6, iclass 20, count 0 2006.285.12:11:21.30#ibcon#read 6, iclass 20, count 0 2006.285.12:11:21.30#ibcon#end of sib2, iclass 20, count 0 2006.285.12:11:21.30#ibcon#*after write, iclass 20, count 0 2006.285.12:11:21.30#ibcon#*before return 0, iclass 20, count 0 2006.285.12:11:21.30#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:11:21.30#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:11:21.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:11:21.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:11:21.30$vck44/vblo=1,629.99 2006.285.12:11:21.30#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.12:11:21.30#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.12:11:21.30#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:21.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:11:21.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:11:21.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:11:21.30#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:11:21.30#ibcon#first serial, iclass 22, count 0 2006.285.12:11:21.30#ibcon#enter sib2, iclass 22, count 0 2006.285.12:11:21.30#ibcon#flushed, iclass 22, count 0 2006.285.12:11:21.30#ibcon#about to write, iclass 22, count 0 2006.285.12:11:21.30#ibcon#wrote, iclass 22, count 0 2006.285.12:11:21.30#ibcon#about to read 3, iclass 22, count 0 2006.285.12:11:21.32#ibcon#read 3, iclass 22, count 0 2006.285.12:11:21.32#ibcon#about to read 4, iclass 22, count 0 2006.285.12:11:21.32#ibcon#read 4, iclass 22, count 0 2006.285.12:11:21.32#ibcon#about to read 5, iclass 22, count 0 2006.285.12:11:21.32#ibcon#read 5, iclass 22, count 0 2006.285.12:11:21.32#ibcon#about to read 6, iclass 22, count 0 2006.285.12:11:21.32#ibcon#read 6, iclass 22, count 0 2006.285.12:11:21.32#ibcon#end of sib2, iclass 22, count 0 2006.285.12:11:21.32#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:11:21.32#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:11:21.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.12:11:21.32#ibcon#*before write, iclass 22, count 0 2006.285.12:11:21.32#ibcon#enter sib2, iclass 22, count 0 2006.285.12:11:21.32#ibcon#flushed, iclass 22, count 0 2006.285.12:11:21.32#ibcon#about to write, iclass 22, count 0 2006.285.12:11:21.32#ibcon#wrote, iclass 22, count 0 2006.285.12:11:21.32#ibcon#about to read 3, iclass 22, count 0 2006.285.12:11:21.36#ibcon#read 3, iclass 22, count 0 2006.285.12:11:21.36#ibcon#about to read 4, iclass 22, count 0 2006.285.12:11:21.36#ibcon#read 4, iclass 22, count 0 2006.285.12:11:21.36#ibcon#about to read 5, iclass 22, count 0 2006.285.12:11:21.36#ibcon#read 5, iclass 22, count 0 2006.285.12:11:21.36#ibcon#about to read 6, iclass 22, count 0 2006.285.12:11:21.36#ibcon#read 6, iclass 22, count 0 2006.285.12:11:21.36#ibcon#end of sib2, iclass 22, count 0 2006.285.12:11:21.36#ibcon#*after write, iclass 22, count 0 2006.285.12:11:21.36#ibcon#*before return 0, iclass 22, count 0 2006.285.12:11:21.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:11:21.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:11:21.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:11:21.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:11:21.36$vck44/vb=1,4 2006.285.12:11:21.36#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.12:11:21.36#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.12:11:21.36#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:21.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:11:21.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:11:21.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:11:21.36#ibcon#enter wrdev, iclass 24, count 2 2006.285.12:11:21.36#ibcon#first serial, iclass 24, count 2 2006.285.12:11:21.36#ibcon#enter sib2, iclass 24, count 2 2006.285.12:11:21.36#ibcon#flushed, iclass 24, count 2 2006.285.12:11:21.36#ibcon#about to write, iclass 24, count 2 2006.285.12:11:21.36#ibcon#wrote, iclass 24, count 2 2006.285.12:11:21.36#ibcon#about to read 3, iclass 24, count 2 2006.285.12:11:21.38#ibcon#read 3, iclass 24, count 2 2006.285.12:11:21.38#ibcon#about to read 4, iclass 24, count 2 2006.285.12:11:21.38#ibcon#read 4, iclass 24, count 2 2006.285.12:11:21.38#ibcon#about to read 5, iclass 24, count 2 2006.285.12:11:21.38#ibcon#read 5, iclass 24, count 2 2006.285.12:11:21.38#ibcon#about to read 6, iclass 24, count 2 2006.285.12:11:21.38#ibcon#read 6, iclass 24, count 2 2006.285.12:11:21.38#ibcon#end of sib2, iclass 24, count 2 2006.285.12:11:21.38#ibcon#*mode == 0, iclass 24, count 2 2006.285.12:11:21.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.12:11:21.38#ibcon#[27=AT01-04\r\n] 2006.285.12:11:21.38#ibcon#*before write, iclass 24, count 2 2006.285.12:11:21.38#ibcon#enter sib2, iclass 24, count 2 2006.285.12:11:21.38#ibcon#flushed, iclass 24, count 2 2006.285.12:11:21.38#ibcon#about to write, iclass 24, count 2 2006.285.12:11:21.38#ibcon#wrote, iclass 24, count 2 2006.285.12:11:21.38#ibcon#about to read 3, iclass 24, count 2 2006.285.12:11:21.41#ibcon#read 3, iclass 24, count 2 2006.285.12:11:21.41#ibcon#about to read 4, iclass 24, count 2 2006.285.12:11:21.41#ibcon#read 4, iclass 24, count 2 2006.285.12:11:21.41#ibcon#about to read 5, iclass 24, count 2 2006.285.12:11:21.41#ibcon#read 5, iclass 24, count 2 2006.285.12:11:21.41#ibcon#about to read 6, iclass 24, count 2 2006.285.12:11:21.41#ibcon#read 6, iclass 24, count 2 2006.285.12:11:21.41#ibcon#end of sib2, iclass 24, count 2 2006.285.12:11:21.41#ibcon#*after write, iclass 24, count 2 2006.285.12:11:21.41#ibcon#*before return 0, iclass 24, count 2 2006.285.12:11:21.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:11:21.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:11:21.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.12:11:21.41#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:21.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:11:21.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:11:21.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:11:21.53#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:11:21.53#ibcon#first serial, iclass 24, count 0 2006.285.12:11:21.53#ibcon#enter sib2, iclass 24, count 0 2006.285.12:11:21.53#ibcon#flushed, iclass 24, count 0 2006.285.12:11:21.53#ibcon#about to write, iclass 24, count 0 2006.285.12:11:21.53#ibcon#wrote, iclass 24, count 0 2006.285.12:11:21.53#ibcon#about to read 3, iclass 24, count 0 2006.285.12:11:21.55#ibcon#read 3, iclass 24, count 0 2006.285.12:11:21.55#ibcon#about to read 4, iclass 24, count 0 2006.285.12:11:21.55#ibcon#read 4, iclass 24, count 0 2006.285.12:11:21.55#ibcon#about to read 5, iclass 24, count 0 2006.285.12:11:21.55#ibcon#read 5, iclass 24, count 0 2006.285.12:11:21.55#ibcon#about to read 6, iclass 24, count 0 2006.285.12:11:21.55#ibcon#read 6, iclass 24, count 0 2006.285.12:11:21.55#ibcon#end of sib2, iclass 24, count 0 2006.285.12:11:21.55#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:11:21.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:11:21.55#ibcon#[27=USB\r\n] 2006.285.12:11:21.55#ibcon#*before write, iclass 24, count 0 2006.285.12:11:21.55#ibcon#enter sib2, iclass 24, count 0 2006.285.12:11:21.55#ibcon#flushed, iclass 24, count 0 2006.285.12:11:21.55#ibcon#about to write, iclass 24, count 0 2006.285.12:11:21.55#ibcon#wrote, iclass 24, count 0 2006.285.12:11:21.55#ibcon#about to read 3, iclass 24, count 0 2006.285.12:11:21.58#ibcon#read 3, iclass 24, count 0 2006.285.12:11:21.58#ibcon#about to read 4, iclass 24, count 0 2006.285.12:11:21.58#ibcon#read 4, iclass 24, count 0 2006.285.12:11:21.58#ibcon#about to read 5, iclass 24, count 0 2006.285.12:11:21.58#ibcon#read 5, iclass 24, count 0 2006.285.12:11:21.58#ibcon#about to read 6, iclass 24, count 0 2006.285.12:11:21.58#ibcon#read 6, iclass 24, count 0 2006.285.12:11:21.58#ibcon#end of sib2, iclass 24, count 0 2006.285.12:11:21.58#ibcon#*after write, iclass 24, count 0 2006.285.12:11:21.58#ibcon#*before return 0, iclass 24, count 0 2006.285.12:11:21.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:11:21.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:11:21.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:11:21.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:11:21.58$vck44/vblo=2,634.99 2006.285.12:11:21.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.12:11:21.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.12:11:21.58#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:21.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:11:21.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:11:21.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:11:21.58#ibcon#enter wrdev, iclass 26, count 0 2006.285.12:11:21.58#ibcon#first serial, iclass 26, count 0 2006.285.12:11:21.58#ibcon#enter sib2, iclass 26, count 0 2006.285.12:11:21.58#ibcon#flushed, iclass 26, count 0 2006.285.12:11:21.58#ibcon#about to write, iclass 26, count 0 2006.285.12:11:21.58#ibcon#wrote, iclass 26, count 0 2006.285.12:11:21.58#ibcon#about to read 3, iclass 26, count 0 2006.285.12:11:21.60#ibcon#read 3, iclass 26, count 0 2006.285.12:11:21.60#ibcon#about to read 4, iclass 26, count 0 2006.285.12:11:21.60#ibcon#read 4, iclass 26, count 0 2006.285.12:11:21.60#ibcon#about to read 5, iclass 26, count 0 2006.285.12:11:21.60#ibcon#read 5, iclass 26, count 0 2006.285.12:11:21.60#ibcon#about to read 6, iclass 26, count 0 2006.285.12:11:21.60#ibcon#read 6, iclass 26, count 0 2006.285.12:11:21.60#ibcon#end of sib2, iclass 26, count 0 2006.285.12:11:21.60#ibcon#*mode == 0, iclass 26, count 0 2006.285.12:11:21.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.12:11:21.60#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.12:11:21.60#ibcon#*before write, iclass 26, count 0 2006.285.12:11:21.60#ibcon#enter sib2, iclass 26, count 0 2006.285.12:11:21.60#ibcon#flushed, iclass 26, count 0 2006.285.12:11:21.60#ibcon#about to write, iclass 26, count 0 2006.285.12:11:21.60#ibcon#wrote, iclass 26, count 0 2006.285.12:11:21.60#ibcon#about to read 3, iclass 26, count 0 2006.285.12:11:21.64#ibcon#read 3, iclass 26, count 0 2006.285.12:11:21.64#ibcon#about to read 4, iclass 26, count 0 2006.285.12:11:21.64#ibcon#read 4, iclass 26, count 0 2006.285.12:11:21.64#ibcon#about to read 5, iclass 26, count 0 2006.285.12:11:21.64#ibcon#read 5, iclass 26, count 0 2006.285.12:11:21.64#ibcon#about to read 6, iclass 26, count 0 2006.285.12:11:21.64#ibcon#read 6, iclass 26, count 0 2006.285.12:11:21.64#ibcon#end of sib2, iclass 26, count 0 2006.285.12:11:21.64#ibcon#*after write, iclass 26, count 0 2006.285.12:11:21.64#ibcon#*before return 0, iclass 26, count 0 2006.285.12:11:21.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:11:21.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:11:21.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.12:11:21.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.12:11:21.64$vck44/vb=2,5 2006.285.12:11:21.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.12:11:21.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.12:11:21.64#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:21.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:11:21.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:11:21.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:11:21.70#ibcon#enter wrdev, iclass 28, count 2 2006.285.12:11:21.70#ibcon#first serial, iclass 28, count 2 2006.285.12:11:21.70#ibcon#enter sib2, iclass 28, count 2 2006.285.12:11:21.70#ibcon#flushed, iclass 28, count 2 2006.285.12:11:21.70#ibcon#about to write, iclass 28, count 2 2006.285.12:11:21.70#ibcon#wrote, iclass 28, count 2 2006.285.12:11:21.70#ibcon#about to read 3, iclass 28, count 2 2006.285.12:11:21.72#ibcon#read 3, iclass 28, count 2 2006.285.12:11:21.72#ibcon#about to read 4, iclass 28, count 2 2006.285.12:11:21.72#ibcon#read 4, iclass 28, count 2 2006.285.12:11:21.72#ibcon#about to read 5, iclass 28, count 2 2006.285.12:11:21.72#ibcon#read 5, iclass 28, count 2 2006.285.12:11:21.72#ibcon#about to read 6, iclass 28, count 2 2006.285.12:11:21.72#ibcon#read 6, iclass 28, count 2 2006.285.12:11:21.72#ibcon#end of sib2, iclass 28, count 2 2006.285.12:11:21.72#ibcon#*mode == 0, iclass 28, count 2 2006.285.12:11:21.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.12:11:21.72#ibcon#[27=AT02-05\r\n] 2006.285.12:11:21.72#ibcon#*before write, iclass 28, count 2 2006.285.12:11:21.72#ibcon#enter sib2, iclass 28, count 2 2006.285.12:11:21.72#ibcon#flushed, iclass 28, count 2 2006.285.12:11:21.72#ibcon#about to write, iclass 28, count 2 2006.285.12:11:21.72#ibcon#wrote, iclass 28, count 2 2006.285.12:11:21.72#ibcon#about to read 3, iclass 28, count 2 2006.285.12:11:21.75#ibcon#read 3, iclass 28, count 2 2006.285.12:11:21.75#ibcon#about to read 4, iclass 28, count 2 2006.285.12:11:21.75#ibcon#read 4, iclass 28, count 2 2006.285.12:11:21.75#ibcon#about to read 5, iclass 28, count 2 2006.285.12:11:21.75#ibcon#read 5, iclass 28, count 2 2006.285.12:11:21.75#ibcon#about to read 6, iclass 28, count 2 2006.285.12:11:21.75#ibcon#read 6, iclass 28, count 2 2006.285.12:11:21.75#ibcon#end of sib2, iclass 28, count 2 2006.285.12:11:21.75#ibcon#*after write, iclass 28, count 2 2006.285.12:11:21.75#ibcon#*before return 0, iclass 28, count 2 2006.285.12:11:21.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:11:21.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:11:21.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.12:11:21.75#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:21.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:11:21.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:11:21.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:11:21.87#ibcon#enter wrdev, iclass 28, count 0 2006.285.12:11:21.87#ibcon#first serial, iclass 28, count 0 2006.285.12:11:21.87#ibcon#enter sib2, iclass 28, count 0 2006.285.12:11:21.87#ibcon#flushed, iclass 28, count 0 2006.285.12:11:21.87#ibcon#about to write, iclass 28, count 0 2006.285.12:11:21.87#ibcon#wrote, iclass 28, count 0 2006.285.12:11:21.87#ibcon#about to read 3, iclass 28, count 0 2006.285.12:11:21.89#ibcon#read 3, iclass 28, count 0 2006.285.12:11:21.89#ibcon#about to read 4, iclass 28, count 0 2006.285.12:11:21.89#ibcon#read 4, iclass 28, count 0 2006.285.12:11:21.89#ibcon#about to read 5, iclass 28, count 0 2006.285.12:11:21.89#ibcon#read 5, iclass 28, count 0 2006.285.12:11:21.89#ibcon#about to read 6, iclass 28, count 0 2006.285.12:11:21.89#ibcon#read 6, iclass 28, count 0 2006.285.12:11:21.89#ibcon#end of sib2, iclass 28, count 0 2006.285.12:11:21.89#ibcon#*mode == 0, iclass 28, count 0 2006.285.12:11:21.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.12:11:21.89#ibcon#[27=USB\r\n] 2006.285.12:11:21.89#ibcon#*before write, iclass 28, count 0 2006.285.12:11:21.89#ibcon#enter sib2, iclass 28, count 0 2006.285.12:11:21.89#ibcon#flushed, iclass 28, count 0 2006.285.12:11:21.89#ibcon#about to write, iclass 28, count 0 2006.285.12:11:21.89#ibcon#wrote, iclass 28, count 0 2006.285.12:11:21.89#ibcon#about to read 3, iclass 28, count 0 2006.285.12:11:21.92#ibcon#read 3, iclass 28, count 0 2006.285.12:11:21.92#ibcon#about to read 4, iclass 28, count 0 2006.285.12:11:21.92#ibcon#read 4, iclass 28, count 0 2006.285.12:11:21.92#ibcon#about to read 5, iclass 28, count 0 2006.285.12:11:21.92#ibcon#read 5, iclass 28, count 0 2006.285.12:11:21.92#ibcon#about to read 6, iclass 28, count 0 2006.285.12:11:21.92#ibcon#read 6, iclass 28, count 0 2006.285.12:11:21.92#ibcon#end of sib2, iclass 28, count 0 2006.285.12:11:21.92#ibcon#*after write, iclass 28, count 0 2006.285.12:11:21.92#ibcon#*before return 0, iclass 28, count 0 2006.285.12:11:21.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:11:21.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:11:21.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.12:11:21.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.12:11:21.92$vck44/vblo=3,649.99 2006.285.12:11:21.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.12:11:21.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.12:11:21.92#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:21.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:11:21.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:11:21.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:11:21.92#ibcon#enter wrdev, iclass 30, count 0 2006.285.12:11:21.92#ibcon#first serial, iclass 30, count 0 2006.285.12:11:21.92#ibcon#enter sib2, iclass 30, count 0 2006.285.12:11:21.92#ibcon#flushed, iclass 30, count 0 2006.285.12:11:21.92#ibcon#about to write, iclass 30, count 0 2006.285.12:11:21.92#ibcon#wrote, iclass 30, count 0 2006.285.12:11:21.92#ibcon#about to read 3, iclass 30, count 0 2006.285.12:11:21.94#ibcon#read 3, iclass 30, count 0 2006.285.12:11:21.94#ibcon#about to read 4, iclass 30, count 0 2006.285.12:11:21.94#ibcon#read 4, iclass 30, count 0 2006.285.12:11:21.94#ibcon#about to read 5, iclass 30, count 0 2006.285.12:11:21.94#ibcon#read 5, iclass 30, count 0 2006.285.12:11:21.94#ibcon#about to read 6, iclass 30, count 0 2006.285.12:11:21.94#ibcon#read 6, iclass 30, count 0 2006.285.12:11:21.94#ibcon#end of sib2, iclass 30, count 0 2006.285.12:11:21.94#ibcon#*mode == 0, iclass 30, count 0 2006.285.12:11:21.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.12:11:21.94#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.12:11:21.94#ibcon#*before write, iclass 30, count 0 2006.285.12:11:21.94#ibcon#enter sib2, iclass 30, count 0 2006.285.12:11:21.94#ibcon#flushed, iclass 30, count 0 2006.285.12:11:21.94#ibcon#about to write, iclass 30, count 0 2006.285.12:11:21.94#ibcon#wrote, iclass 30, count 0 2006.285.12:11:21.94#ibcon#about to read 3, iclass 30, count 0 2006.285.12:11:21.98#ibcon#read 3, iclass 30, count 0 2006.285.12:11:21.98#ibcon#about to read 4, iclass 30, count 0 2006.285.12:11:21.98#ibcon#read 4, iclass 30, count 0 2006.285.12:11:21.98#ibcon#about to read 5, iclass 30, count 0 2006.285.12:11:21.98#ibcon#read 5, iclass 30, count 0 2006.285.12:11:21.98#ibcon#about to read 6, iclass 30, count 0 2006.285.12:11:21.98#ibcon#read 6, iclass 30, count 0 2006.285.12:11:21.98#ibcon#end of sib2, iclass 30, count 0 2006.285.12:11:21.98#ibcon#*after write, iclass 30, count 0 2006.285.12:11:21.98#ibcon#*before return 0, iclass 30, count 0 2006.285.12:11:21.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:11:21.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:11:21.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.12:11:21.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.12:11:21.98$vck44/vb=3,4 2006.285.12:11:21.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.12:11:21.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.12:11:21.98#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:21.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:11:22.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:11:22.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:11:22.04#ibcon#enter wrdev, iclass 32, count 2 2006.285.12:11:22.04#ibcon#first serial, iclass 32, count 2 2006.285.12:11:22.04#ibcon#enter sib2, iclass 32, count 2 2006.285.12:11:22.04#ibcon#flushed, iclass 32, count 2 2006.285.12:11:22.04#ibcon#about to write, iclass 32, count 2 2006.285.12:11:22.04#ibcon#wrote, iclass 32, count 2 2006.285.12:11:22.04#ibcon#about to read 3, iclass 32, count 2 2006.285.12:11:22.06#ibcon#read 3, iclass 32, count 2 2006.285.12:11:22.06#ibcon#about to read 4, iclass 32, count 2 2006.285.12:11:22.06#ibcon#read 4, iclass 32, count 2 2006.285.12:11:22.06#ibcon#about to read 5, iclass 32, count 2 2006.285.12:11:22.06#ibcon#read 5, iclass 32, count 2 2006.285.12:11:22.06#ibcon#about to read 6, iclass 32, count 2 2006.285.12:11:22.06#ibcon#read 6, iclass 32, count 2 2006.285.12:11:22.06#ibcon#end of sib2, iclass 32, count 2 2006.285.12:11:22.06#ibcon#*mode == 0, iclass 32, count 2 2006.285.12:11:22.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.12:11:22.06#ibcon#[27=AT03-04\r\n] 2006.285.12:11:22.06#ibcon#*before write, iclass 32, count 2 2006.285.12:11:22.06#ibcon#enter sib2, iclass 32, count 2 2006.285.12:11:22.06#ibcon#flushed, iclass 32, count 2 2006.285.12:11:22.06#ibcon#about to write, iclass 32, count 2 2006.285.12:11:22.06#ibcon#wrote, iclass 32, count 2 2006.285.12:11:22.06#ibcon#about to read 3, iclass 32, count 2 2006.285.12:11:22.08#abcon#<5=/04 1.1 1.7 18.98 941015.5\r\n> 2006.285.12:11:22.09#ibcon#read 3, iclass 32, count 2 2006.285.12:11:22.09#ibcon#about to read 4, iclass 32, count 2 2006.285.12:11:22.09#ibcon#read 4, iclass 32, count 2 2006.285.12:11:22.09#ibcon#about to read 5, iclass 32, count 2 2006.285.12:11:22.09#ibcon#read 5, iclass 32, count 2 2006.285.12:11:22.09#ibcon#about to read 6, iclass 32, count 2 2006.285.12:11:22.09#ibcon#read 6, iclass 32, count 2 2006.285.12:11:22.09#ibcon#end of sib2, iclass 32, count 2 2006.285.12:11:22.09#ibcon#*after write, iclass 32, count 2 2006.285.12:11:22.09#ibcon#*before return 0, iclass 32, count 2 2006.285.12:11:22.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:11:22.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:11:22.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.12:11:22.09#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:22.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:11:22.10#abcon#{5=INTERFACE CLEAR} 2006.285.12:11:22.16#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:11:22.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:11:22.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:11:22.21#ibcon#enter wrdev, iclass 32, count 0 2006.285.12:11:22.21#ibcon#first serial, iclass 32, count 0 2006.285.12:11:22.21#ibcon#enter sib2, iclass 32, count 0 2006.285.12:11:22.21#ibcon#flushed, iclass 32, count 0 2006.285.12:11:22.21#ibcon#about to write, iclass 32, count 0 2006.285.12:11:22.21#ibcon#wrote, iclass 32, count 0 2006.285.12:11:22.21#ibcon#about to read 3, iclass 32, count 0 2006.285.12:11:22.23#ibcon#read 3, iclass 32, count 0 2006.285.12:11:22.23#ibcon#about to read 4, iclass 32, count 0 2006.285.12:11:22.23#ibcon#read 4, iclass 32, count 0 2006.285.12:11:22.23#ibcon#about to read 5, iclass 32, count 0 2006.285.12:11:22.23#ibcon#read 5, iclass 32, count 0 2006.285.12:11:22.23#ibcon#about to read 6, iclass 32, count 0 2006.285.12:11:22.23#ibcon#read 6, iclass 32, count 0 2006.285.12:11:22.23#ibcon#end of sib2, iclass 32, count 0 2006.285.12:11:22.23#ibcon#*mode == 0, iclass 32, count 0 2006.285.12:11:22.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.12:11:22.23#ibcon#[27=USB\r\n] 2006.285.12:11:22.23#ibcon#*before write, iclass 32, count 0 2006.285.12:11:22.23#ibcon#enter sib2, iclass 32, count 0 2006.285.12:11:22.23#ibcon#flushed, iclass 32, count 0 2006.285.12:11:22.23#ibcon#about to write, iclass 32, count 0 2006.285.12:11:22.23#ibcon#wrote, iclass 32, count 0 2006.285.12:11:22.23#ibcon#about to read 3, iclass 32, count 0 2006.285.12:11:22.26#ibcon#read 3, iclass 32, count 0 2006.285.12:11:22.26#ibcon#about to read 4, iclass 32, count 0 2006.285.12:11:22.26#ibcon#read 4, iclass 32, count 0 2006.285.12:11:22.26#ibcon#about to read 5, iclass 32, count 0 2006.285.12:11:22.26#ibcon#read 5, iclass 32, count 0 2006.285.12:11:22.26#ibcon#about to read 6, iclass 32, count 0 2006.285.12:11:22.26#ibcon#read 6, iclass 32, count 0 2006.285.12:11:22.26#ibcon#end of sib2, iclass 32, count 0 2006.285.12:11:22.26#ibcon#*after write, iclass 32, count 0 2006.285.12:11:22.26#ibcon#*before return 0, iclass 32, count 0 2006.285.12:11:22.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:11:22.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:11:22.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.12:11:22.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.12:11:22.26$vck44/vblo=4,679.99 2006.285.12:11:22.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.12:11:22.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.12:11:22.26#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:22.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:11:22.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:11:22.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:11:22.26#ibcon#enter wrdev, iclass 38, count 0 2006.285.12:11:22.26#ibcon#first serial, iclass 38, count 0 2006.285.12:11:22.26#ibcon#enter sib2, iclass 38, count 0 2006.285.12:11:22.26#ibcon#flushed, iclass 38, count 0 2006.285.12:11:22.26#ibcon#about to write, iclass 38, count 0 2006.285.12:11:22.26#ibcon#wrote, iclass 38, count 0 2006.285.12:11:22.26#ibcon#about to read 3, iclass 38, count 0 2006.285.12:11:22.28#ibcon#read 3, iclass 38, count 0 2006.285.12:11:22.28#ibcon#about to read 4, iclass 38, count 0 2006.285.12:11:22.28#ibcon#read 4, iclass 38, count 0 2006.285.12:11:22.28#ibcon#about to read 5, iclass 38, count 0 2006.285.12:11:22.28#ibcon#read 5, iclass 38, count 0 2006.285.12:11:22.28#ibcon#about to read 6, iclass 38, count 0 2006.285.12:11:22.28#ibcon#read 6, iclass 38, count 0 2006.285.12:11:22.28#ibcon#end of sib2, iclass 38, count 0 2006.285.12:11:22.28#ibcon#*mode == 0, iclass 38, count 0 2006.285.12:11:22.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.12:11:22.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.12:11:22.28#ibcon#*before write, iclass 38, count 0 2006.285.12:11:22.28#ibcon#enter sib2, iclass 38, count 0 2006.285.12:11:22.28#ibcon#flushed, iclass 38, count 0 2006.285.12:11:22.28#ibcon#about to write, iclass 38, count 0 2006.285.12:11:22.28#ibcon#wrote, iclass 38, count 0 2006.285.12:11:22.28#ibcon#about to read 3, iclass 38, count 0 2006.285.12:11:22.32#ibcon#read 3, iclass 38, count 0 2006.285.12:11:22.32#ibcon#about to read 4, iclass 38, count 0 2006.285.12:11:22.32#ibcon#read 4, iclass 38, count 0 2006.285.12:11:22.32#ibcon#about to read 5, iclass 38, count 0 2006.285.12:11:22.32#ibcon#read 5, iclass 38, count 0 2006.285.12:11:22.32#ibcon#about to read 6, iclass 38, count 0 2006.285.12:11:22.32#ibcon#read 6, iclass 38, count 0 2006.285.12:11:22.32#ibcon#end of sib2, iclass 38, count 0 2006.285.12:11:22.32#ibcon#*after write, iclass 38, count 0 2006.285.12:11:22.32#ibcon#*before return 0, iclass 38, count 0 2006.285.12:11:22.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:11:22.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:11:22.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.12:11:22.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.12:11:22.32$vck44/vb=4,5 2006.285.12:11:22.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.12:11:22.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.12:11:22.32#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:22.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:11:22.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:11:22.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:11:22.38#ibcon#enter wrdev, iclass 40, count 2 2006.285.12:11:22.38#ibcon#first serial, iclass 40, count 2 2006.285.12:11:22.38#ibcon#enter sib2, iclass 40, count 2 2006.285.12:11:22.38#ibcon#flushed, iclass 40, count 2 2006.285.12:11:22.38#ibcon#about to write, iclass 40, count 2 2006.285.12:11:22.38#ibcon#wrote, iclass 40, count 2 2006.285.12:11:22.38#ibcon#about to read 3, iclass 40, count 2 2006.285.12:11:22.40#ibcon#read 3, iclass 40, count 2 2006.285.12:11:22.40#ibcon#about to read 4, iclass 40, count 2 2006.285.12:11:22.40#ibcon#read 4, iclass 40, count 2 2006.285.12:11:22.40#ibcon#about to read 5, iclass 40, count 2 2006.285.12:11:22.40#ibcon#read 5, iclass 40, count 2 2006.285.12:11:22.40#ibcon#about to read 6, iclass 40, count 2 2006.285.12:11:22.40#ibcon#read 6, iclass 40, count 2 2006.285.12:11:22.40#ibcon#end of sib2, iclass 40, count 2 2006.285.12:11:22.40#ibcon#*mode == 0, iclass 40, count 2 2006.285.12:11:22.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.12:11:22.40#ibcon#[27=AT04-05\r\n] 2006.285.12:11:22.40#ibcon#*before write, iclass 40, count 2 2006.285.12:11:22.40#ibcon#enter sib2, iclass 40, count 2 2006.285.12:11:22.40#ibcon#flushed, iclass 40, count 2 2006.285.12:11:22.40#ibcon#about to write, iclass 40, count 2 2006.285.12:11:22.40#ibcon#wrote, iclass 40, count 2 2006.285.12:11:22.40#ibcon#about to read 3, iclass 40, count 2 2006.285.12:11:22.43#ibcon#read 3, iclass 40, count 2 2006.285.12:11:22.43#ibcon#about to read 4, iclass 40, count 2 2006.285.12:11:22.43#ibcon#read 4, iclass 40, count 2 2006.285.12:11:22.43#ibcon#about to read 5, iclass 40, count 2 2006.285.12:11:22.43#ibcon#read 5, iclass 40, count 2 2006.285.12:11:22.43#ibcon#about to read 6, iclass 40, count 2 2006.285.12:11:22.43#ibcon#read 6, iclass 40, count 2 2006.285.12:11:22.43#ibcon#end of sib2, iclass 40, count 2 2006.285.12:11:22.43#ibcon#*after write, iclass 40, count 2 2006.285.12:11:22.43#ibcon#*before return 0, iclass 40, count 2 2006.285.12:11:22.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:11:22.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:11:22.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.12:11:22.43#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:22.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:11:22.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:11:22.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:11:22.55#ibcon#enter wrdev, iclass 40, count 0 2006.285.12:11:22.55#ibcon#first serial, iclass 40, count 0 2006.285.12:11:22.55#ibcon#enter sib2, iclass 40, count 0 2006.285.12:11:22.55#ibcon#flushed, iclass 40, count 0 2006.285.12:11:22.55#ibcon#about to write, iclass 40, count 0 2006.285.12:11:22.55#ibcon#wrote, iclass 40, count 0 2006.285.12:11:22.55#ibcon#about to read 3, iclass 40, count 0 2006.285.12:11:22.57#ibcon#read 3, iclass 40, count 0 2006.285.12:11:22.57#ibcon#about to read 4, iclass 40, count 0 2006.285.12:11:22.57#ibcon#read 4, iclass 40, count 0 2006.285.12:11:22.57#ibcon#about to read 5, iclass 40, count 0 2006.285.12:11:22.57#ibcon#read 5, iclass 40, count 0 2006.285.12:11:22.57#ibcon#about to read 6, iclass 40, count 0 2006.285.12:11:22.57#ibcon#read 6, iclass 40, count 0 2006.285.12:11:22.57#ibcon#end of sib2, iclass 40, count 0 2006.285.12:11:22.57#ibcon#*mode == 0, iclass 40, count 0 2006.285.12:11:22.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.12:11:22.57#ibcon#[27=USB\r\n] 2006.285.12:11:22.57#ibcon#*before write, iclass 40, count 0 2006.285.12:11:22.57#ibcon#enter sib2, iclass 40, count 0 2006.285.12:11:22.57#ibcon#flushed, iclass 40, count 0 2006.285.12:11:22.57#ibcon#about to write, iclass 40, count 0 2006.285.12:11:22.57#ibcon#wrote, iclass 40, count 0 2006.285.12:11:22.57#ibcon#about to read 3, iclass 40, count 0 2006.285.12:11:22.60#ibcon#read 3, iclass 40, count 0 2006.285.12:11:22.60#ibcon#about to read 4, iclass 40, count 0 2006.285.12:11:22.60#ibcon#read 4, iclass 40, count 0 2006.285.12:11:22.60#ibcon#about to read 5, iclass 40, count 0 2006.285.12:11:22.60#ibcon#read 5, iclass 40, count 0 2006.285.12:11:22.60#ibcon#about to read 6, iclass 40, count 0 2006.285.12:11:22.60#ibcon#read 6, iclass 40, count 0 2006.285.12:11:22.60#ibcon#end of sib2, iclass 40, count 0 2006.285.12:11:22.60#ibcon#*after write, iclass 40, count 0 2006.285.12:11:22.60#ibcon#*before return 0, iclass 40, count 0 2006.285.12:11:22.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:11:22.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:11:22.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.12:11:22.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.12:11:22.60$vck44/vblo=5,709.99 2006.285.12:11:22.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.12:11:22.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.12:11:22.60#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:22.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:11:22.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:11:22.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:11:22.60#ibcon#enter wrdev, iclass 4, count 0 2006.285.12:11:22.60#ibcon#first serial, iclass 4, count 0 2006.285.12:11:22.60#ibcon#enter sib2, iclass 4, count 0 2006.285.12:11:22.60#ibcon#flushed, iclass 4, count 0 2006.285.12:11:22.60#ibcon#about to write, iclass 4, count 0 2006.285.12:11:22.60#ibcon#wrote, iclass 4, count 0 2006.285.12:11:22.60#ibcon#about to read 3, iclass 4, count 0 2006.285.12:11:22.62#ibcon#read 3, iclass 4, count 0 2006.285.12:11:22.62#ibcon#about to read 4, iclass 4, count 0 2006.285.12:11:22.62#ibcon#read 4, iclass 4, count 0 2006.285.12:11:22.62#ibcon#about to read 5, iclass 4, count 0 2006.285.12:11:22.62#ibcon#read 5, iclass 4, count 0 2006.285.12:11:22.62#ibcon#about to read 6, iclass 4, count 0 2006.285.12:11:22.62#ibcon#read 6, iclass 4, count 0 2006.285.12:11:22.62#ibcon#end of sib2, iclass 4, count 0 2006.285.12:11:22.62#ibcon#*mode == 0, iclass 4, count 0 2006.285.12:11:22.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.12:11:22.62#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.12:11:22.62#ibcon#*before write, iclass 4, count 0 2006.285.12:11:22.62#ibcon#enter sib2, iclass 4, count 0 2006.285.12:11:22.62#ibcon#flushed, iclass 4, count 0 2006.285.12:11:22.62#ibcon#about to write, iclass 4, count 0 2006.285.12:11:22.62#ibcon#wrote, iclass 4, count 0 2006.285.12:11:22.62#ibcon#about to read 3, iclass 4, count 0 2006.285.12:11:22.66#ibcon#read 3, iclass 4, count 0 2006.285.12:11:22.66#ibcon#about to read 4, iclass 4, count 0 2006.285.12:11:22.66#ibcon#read 4, iclass 4, count 0 2006.285.12:11:22.66#ibcon#about to read 5, iclass 4, count 0 2006.285.12:11:22.66#ibcon#read 5, iclass 4, count 0 2006.285.12:11:22.66#ibcon#about to read 6, iclass 4, count 0 2006.285.12:11:22.66#ibcon#read 6, iclass 4, count 0 2006.285.12:11:22.66#ibcon#end of sib2, iclass 4, count 0 2006.285.12:11:22.66#ibcon#*after write, iclass 4, count 0 2006.285.12:11:22.66#ibcon#*before return 0, iclass 4, count 0 2006.285.12:11:22.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:11:22.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:11:22.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.12:11:22.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.12:11:22.66$vck44/vb=5,4 2006.285.12:11:22.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.12:11:22.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.12:11:22.66#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:22.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:11:22.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:11:22.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:11:22.72#ibcon#enter wrdev, iclass 6, count 2 2006.285.12:11:22.72#ibcon#first serial, iclass 6, count 2 2006.285.12:11:22.72#ibcon#enter sib2, iclass 6, count 2 2006.285.12:11:22.72#ibcon#flushed, iclass 6, count 2 2006.285.12:11:22.72#ibcon#about to write, iclass 6, count 2 2006.285.12:11:22.72#ibcon#wrote, iclass 6, count 2 2006.285.12:11:22.72#ibcon#about to read 3, iclass 6, count 2 2006.285.12:11:22.74#ibcon#read 3, iclass 6, count 2 2006.285.12:11:22.74#ibcon#about to read 4, iclass 6, count 2 2006.285.12:11:22.74#ibcon#read 4, iclass 6, count 2 2006.285.12:11:22.74#ibcon#about to read 5, iclass 6, count 2 2006.285.12:11:22.74#ibcon#read 5, iclass 6, count 2 2006.285.12:11:22.74#ibcon#about to read 6, iclass 6, count 2 2006.285.12:11:22.74#ibcon#read 6, iclass 6, count 2 2006.285.12:11:22.74#ibcon#end of sib2, iclass 6, count 2 2006.285.12:11:22.74#ibcon#*mode == 0, iclass 6, count 2 2006.285.12:11:22.74#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.12:11:22.74#ibcon#[27=AT05-04\r\n] 2006.285.12:11:22.74#ibcon#*before write, iclass 6, count 2 2006.285.12:11:22.74#ibcon#enter sib2, iclass 6, count 2 2006.285.12:11:22.74#ibcon#flushed, iclass 6, count 2 2006.285.12:11:22.74#ibcon#about to write, iclass 6, count 2 2006.285.12:11:22.74#ibcon#wrote, iclass 6, count 2 2006.285.12:11:22.74#ibcon#about to read 3, iclass 6, count 2 2006.285.12:11:22.77#ibcon#read 3, iclass 6, count 2 2006.285.12:11:22.77#ibcon#about to read 4, iclass 6, count 2 2006.285.12:11:22.77#ibcon#read 4, iclass 6, count 2 2006.285.12:11:22.77#ibcon#about to read 5, iclass 6, count 2 2006.285.12:11:22.77#ibcon#read 5, iclass 6, count 2 2006.285.12:11:22.77#ibcon#about to read 6, iclass 6, count 2 2006.285.12:11:22.77#ibcon#read 6, iclass 6, count 2 2006.285.12:11:22.77#ibcon#end of sib2, iclass 6, count 2 2006.285.12:11:22.77#ibcon#*after write, iclass 6, count 2 2006.285.12:11:22.77#ibcon#*before return 0, iclass 6, count 2 2006.285.12:11:22.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:11:22.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:11:22.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.12:11:22.77#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:22.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:11:22.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:11:22.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:11:22.89#ibcon#enter wrdev, iclass 6, count 0 2006.285.12:11:22.89#ibcon#first serial, iclass 6, count 0 2006.285.12:11:22.89#ibcon#enter sib2, iclass 6, count 0 2006.285.12:11:22.89#ibcon#flushed, iclass 6, count 0 2006.285.12:11:22.89#ibcon#about to write, iclass 6, count 0 2006.285.12:11:22.89#ibcon#wrote, iclass 6, count 0 2006.285.12:11:22.89#ibcon#about to read 3, iclass 6, count 0 2006.285.12:11:22.91#ibcon#read 3, iclass 6, count 0 2006.285.12:11:22.91#ibcon#about to read 4, iclass 6, count 0 2006.285.12:11:22.91#ibcon#read 4, iclass 6, count 0 2006.285.12:11:22.91#ibcon#about to read 5, iclass 6, count 0 2006.285.12:11:22.91#ibcon#read 5, iclass 6, count 0 2006.285.12:11:22.91#ibcon#about to read 6, iclass 6, count 0 2006.285.12:11:22.91#ibcon#read 6, iclass 6, count 0 2006.285.12:11:22.91#ibcon#end of sib2, iclass 6, count 0 2006.285.12:11:22.91#ibcon#*mode == 0, iclass 6, count 0 2006.285.12:11:22.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.12:11:22.91#ibcon#[27=USB\r\n] 2006.285.12:11:22.91#ibcon#*before write, iclass 6, count 0 2006.285.12:11:22.91#ibcon#enter sib2, iclass 6, count 0 2006.285.12:11:22.91#ibcon#flushed, iclass 6, count 0 2006.285.12:11:22.91#ibcon#about to write, iclass 6, count 0 2006.285.12:11:22.91#ibcon#wrote, iclass 6, count 0 2006.285.12:11:22.91#ibcon#about to read 3, iclass 6, count 0 2006.285.12:11:22.94#ibcon#read 3, iclass 6, count 0 2006.285.12:11:22.94#ibcon#about to read 4, iclass 6, count 0 2006.285.12:11:22.94#ibcon#read 4, iclass 6, count 0 2006.285.12:11:22.94#ibcon#about to read 5, iclass 6, count 0 2006.285.12:11:22.94#ibcon#read 5, iclass 6, count 0 2006.285.12:11:22.94#ibcon#about to read 6, iclass 6, count 0 2006.285.12:11:22.94#ibcon#read 6, iclass 6, count 0 2006.285.12:11:22.94#ibcon#end of sib2, iclass 6, count 0 2006.285.12:11:22.94#ibcon#*after write, iclass 6, count 0 2006.285.12:11:22.94#ibcon#*before return 0, iclass 6, count 0 2006.285.12:11:22.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:11:22.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:11:22.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.12:11:22.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.12:11:22.94$vck44/vblo=6,719.99 2006.285.12:11:22.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.12:11:22.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.12:11:22.94#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:22.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:11:22.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:11:22.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:11:22.94#ibcon#enter wrdev, iclass 10, count 0 2006.285.12:11:22.94#ibcon#first serial, iclass 10, count 0 2006.285.12:11:22.94#ibcon#enter sib2, iclass 10, count 0 2006.285.12:11:22.94#ibcon#flushed, iclass 10, count 0 2006.285.12:11:22.94#ibcon#about to write, iclass 10, count 0 2006.285.12:11:22.94#ibcon#wrote, iclass 10, count 0 2006.285.12:11:22.94#ibcon#about to read 3, iclass 10, count 0 2006.285.12:11:22.96#ibcon#read 3, iclass 10, count 0 2006.285.12:11:22.96#ibcon#about to read 4, iclass 10, count 0 2006.285.12:11:22.96#ibcon#read 4, iclass 10, count 0 2006.285.12:11:22.96#ibcon#about to read 5, iclass 10, count 0 2006.285.12:11:22.96#ibcon#read 5, iclass 10, count 0 2006.285.12:11:22.96#ibcon#about to read 6, iclass 10, count 0 2006.285.12:11:22.96#ibcon#read 6, iclass 10, count 0 2006.285.12:11:22.96#ibcon#end of sib2, iclass 10, count 0 2006.285.12:11:22.96#ibcon#*mode == 0, iclass 10, count 0 2006.285.12:11:22.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.12:11:22.96#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.12:11:22.96#ibcon#*before write, iclass 10, count 0 2006.285.12:11:22.96#ibcon#enter sib2, iclass 10, count 0 2006.285.12:11:22.96#ibcon#flushed, iclass 10, count 0 2006.285.12:11:22.96#ibcon#about to write, iclass 10, count 0 2006.285.12:11:22.96#ibcon#wrote, iclass 10, count 0 2006.285.12:11:22.96#ibcon#about to read 3, iclass 10, count 0 2006.285.12:11:23.00#ibcon#read 3, iclass 10, count 0 2006.285.12:11:23.00#ibcon#about to read 4, iclass 10, count 0 2006.285.12:11:23.00#ibcon#read 4, iclass 10, count 0 2006.285.12:11:23.00#ibcon#about to read 5, iclass 10, count 0 2006.285.12:11:23.00#ibcon#read 5, iclass 10, count 0 2006.285.12:11:23.00#ibcon#about to read 6, iclass 10, count 0 2006.285.12:11:23.00#ibcon#read 6, iclass 10, count 0 2006.285.12:11:23.00#ibcon#end of sib2, iclass 10, count 0 2006.285.12:11:23.00#ibcon#*after write, iclass 10, count 0 2006.285.12:11:23.00#ibcon#*before return 0, iclass 10, count 0 2006.285.12:11:23.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:11:23.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:11:23.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.12:11:23.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.12:11:23.00$vck44/vb=6,3 2006.285.12:11:23.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.12:11:23.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.12:11:23.00#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:23.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:11:23.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:11:23.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:11:23.06#ibcon#enter wrdev, iclass 12, count 2 2006.285.12:11:23.06#ibcon#first serial, iclass 12, count 2 2006.285.12:11:23.06#ibcon#enter sib2, iclass 12, count 2 2006.285.12:11:23.06#ibcon#flushed, iclass 12, count 2 2006.285.12:11:23.06#ibcon#about to write, iclass 12, count 2 2006.285.12:11:23.06#ibcon#wrote, iclass 12, count 2 2006.285.12:11:23.06#ibcon#about to read 3, iclass 12, count 2 2006.285.12:11:23.08#ibcon#read 3, iclass 12, count 2 2006.285.12:11:23.08#ibcon#about to read 4, iclass 12, count 2 2006.285.12:11:23.08#ibcon#read 4, iclass 12, count 2 2006.285.12:11:23.08#ibcon#about to read 5, iclass 12, count 2 2006.285.12:11:23.08#ibcon#read 5, iclass 12, count 2 2006.285.12:11:23.08#ibcon#about to read 6, iclass 12, count 2 2006.285.12:11:23.08#ibcon#read 6, iclass 12, count 2 2006.285.12:11:23.08#ibcon#end of sib2, iclass 12, count 2 2006.285.12:11:23.08#ibcon#*mode == 0, iclass 12, count 2 2006.285.12:11:23.08#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.12:11:23.08#ibcon#[27=AT06-03\r\n] 2006.285.12:11:23.08#ibcon#*before write, iclass 12, count 2 2006.285.12:11:23.08#ibcon#enter sib2, iclass 12, count 2 2006.285.12:11:23.08#ibcon#flushed, iclass 12, count 2 2006.285.12:11:23.08#ibcon#about to write, iclass 12, count 2 2006.285.12:11:23.08#ibcon#wrote, iclass 12, count 2 2006.285.12:11:23.08#ibcon#about to read 3, iclass 12, count 2 2006.285.12:11:23.11#ibcon#read 3, iclass 12, count 2 2006.285.12:11:23.11#ibcon#about to read 4, iclass 12, count 2 2006.285.12:11:23.11#ibcon#read 4, iclass 12, count 2 2006.285.12:11:23.11#ibcon#about to read 5, iclass 12, count 2 2006.285.12:11:23.11#ibcon#read 5, iclass 12, count 2 2006.285.12:11:23.11#ibcon#about to read 6, iclass 12, count 2 2006.285.12:11:23.11#ibcon#read 6, iclass 12, count 2 2006.285.12:11:23.11#ibcon#end of sib2, iclass 12, count 2 2006.285.12:11:23.11#ibcon#*after write, iclass 12, count 2 2006.285.12:11:23.11#ibcon#*before return 0, iclass 12, count 2 2006.285.12:11:23.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:11:23.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:11:23.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.12:11:23.11#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:23.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:11:23.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:11:23.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:11:23.23#ibcon#enter wrdev, iclass 12, count 0 2006.285.12:11:23.23#ibcon#first serial, iclass 12, count 0 2006.285.12:11:23.23#ibcon#enter sib2, iclass 12, count 0 2006.285.12:11:23.23#ibcon#flushed, iclass 12, count 0 2006.285.12:11:23.23#ibcon#about to write, iclass 12, count 0 2006.285.12:11:23.23#ibcon#wrote, iclass 12, count 0 2006.285.12:11:23.23#ibcon#about to read 3, iclass 12, count 0 2006.285.12:11:23.25#ibcon#read 3, iclass 12, count 0 2006.285.12:11:23.25#ibcon#about to read 4, iclass 12, count 0 2006.285.12:11:23.25#ibcon#read 4, iclass 12, count 0 2006.285.12:11:23.25#ibcon#about to read 5, iclass 12, count 0 2006.285.12:11:23.25#ibcon#read 5, iclass 12, count 0 2006.285.12:11:23.25#ibcon#about to read 6, iclass 12, count 0 2006.285.12:11:23.25#ibcon#read 6, iclass 12, count 0 2006.285.12:11:23.25#ibcon#end of sib2, iclass 12, count 0 2006.285.12:11:23.25#ibcon#*mode == 0, iclass 12, count 0 2006.285.12:11:23.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.12:11:23.25#ibcon#[27=USB\r\n] 2006.285.12:11:23.25#ibcon#*before write, iclass 12, count 0 2006.285.12:11:23.25#ibcon#enter sib2, iclass 12, count 0 2006.285.12:11:23.25#ibcon#flushed, iclass 12, count 0 2006.285.12:11:23.25#ibcon#about to write, iclass 12, count 0 2006.285.12:11:23.25#ibcon#wrote, iclass 12, count 0 2006.285.12:11:23.25#ibcon#about to read 3, iclass 12, count 0 2006.285.12:11:23.28#ibcon#read 3, iclass 12, count 0 2006.285.12:11:23.28#ibcon#about to read 4, iclass 12, count 0 2006.285.12:11:23.28#ibcon#read 4, iclass 12, count 0 2006.285.12:11:23.28#ibcon#about to read 5, iclass 12, count 0 2006.285.12:11:23.28#ibcon#read 5, iclass 12, count 0 2006.285.12:11:23.28#ibcon#about to read 6, iclass 12, count 0 2006.285.12:11:23.28#ibcon#read 6, iclass 12, count 0 2006.285.12:11:23.28#ibcon#end of sib2, iclass 12, count 0 2006.285.12:11:23.28#ibcon#*after write, iclass 12, count 0 2006.285.12:11:23.28#ibcon#*before return 0, iclass 12, count 0 2006.285.12:11:23.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:11:23.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:11:23.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.12:11:23.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.12:11:23.28$vck44/vblo=7,734.99 2006.285.12:11:23.28#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.12:11:23.28#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.12:11:23.28#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:23.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:11:23.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:11:23.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:11:23.28#ibcon#enter wrdev, iclass 14, count 0 2006.285.12:11:23.28#ibcon#first serial, iclass 14, count 0 2006.285.12:11:23.28#ibcon#enter sib2, iclass 14, count 0 2006.285.12:11:23.28#ibcon#flushed, iclass 14, count 0 2006.285.12:11:23.28#ibcon#about to write, iclass 14, count 0 2006.285.12:11:23.28#ibcon#wrote, iclass 14, count 0 2006.285.12:11:23.28#ibcon#about to read 3, iclass 14, count 0 2006.285.12:11:23.30#ibcon#read 3, iclass 14, count 0 2006.285.12:11:23.30#ibcon#about to read 4, iclass 14, count 0 2006.285.12:11:23.30#ibcon#read 4, iclass 14, count 0 2006.285.12:11:23.30#ibcon#about to read 5, iclass 14, count 0 2006.285.12:11:23.30#ibcon#read 5, iclass 14, count 0 2006.285.12:11:23.30#ibcon#about to read 6, iclass 14, count 0 2006.285.12:11:23.30#ibcon#read 6, iclass 14, count 0 2006.285.12:11:23.30#ibcon#end of sib2, iclass 14, count 0 2006.285.12:11:23.30#ibcon#*mode == 0, iclass 14, count 0 2006.285.12:11:23.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.12:11:23.30#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.12:11:23.30#ibcon#*before write, iclass 14, count 0 2006.285.12:11:23.30#ibcon#enter sib2, iclass 14, count 0 2006.285.12:11:23.30#ibcon#flushed, iclass 14, count 0 2006.285.12:11:23.30#ibcon#about to write, iclass 14, count 0 2006.285.12:11:23.30#ibcon#wrote, iclass 14, count 0 2006.285.12:11:23.30#ibcon#about to read 3, iclass 14, count 0 2006.285.12:11:23.34#ibcon#read 3, iclass 14, count 0 2006.285.12:11:23.34#ibcon#about to read 4, iclass 14, count 0 2006.285.12:11:23.34#ibcon#read 4, iclass 14, count 0 2006.285.12:11:23.34#ibcon#about to read 5, iclass 14, count 0 2006.285.12:11:23.34#ibcon#read 5, iclass 14, count 0 2006.285.12:11:23.34#ibcon#about to read 6, iclass 14, count 0 2006.285.12:11:23.34#ibcon#read 6, iclass 14, count 0 2006.285.12:11:23.34#ibcon#end of sib2, iclass 14, count 0 2006.285.12:11:23.34#ibcon#*after write, iclass 14, count 0 2006.285.12:11:23.34#ibcon#*before return 0, iclass 14, count 0 2006.285.12:11:23.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:11:23.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:11:23.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.12:11:23.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.12:11:23.34$vck44/vb=7,4 2006.285.12:11:23.34#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.12:11:23.34#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.12:11:23.34#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:23.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:11:23.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:11:23.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:11:23.40#ibcon#enter wrdev, iclass 16, count 2 2006.285.12:11:23.40#ibcon#first serial, iclass 16, count 2 2006.285.12:11:23.40#ibcon#enter sib2, iclass 16, count 2 2006.285.12:11:23.40#ibcon#flushed, iclass 16, count 2 2006.285.12:11:23.40#ibcon#about to write, iclass 16, count 2 2006.285.12:11:23.40#ibcon#wrote, iclass 16, count 2 2006.285.12:11:23.40#ibcon#about to read 3, iclass 16, count 2 2006.285.12:11:23.42#ibcon#read 3, iclass 16, count 2 2006.285.12:11:23.42#ibcon#about to read 4, iclass 16, count 2 2006.285.12:11:23.42#ibcon#read 4, iclass 16, count 2 2006.285.12:11:23.42#ibcon#about to read 5, iclass 16, count 2 2006.285.12:11:23.42#ibcon#read 5, iclass 16, count 2 2006.285.12:11:23.42#ibcon#about to read 6, iclass 16, count 2 2006.285.12:11:23.42#ibcon#read 6, iclass 16, count 2 2006.285.12:11:23.42#ibcon#end of sib2, iclass 16, count 2 2006.285.12:11:23.42#ibcon#*mode == 0, iclass 16, count 2 2006.285.12:11:23.42#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.12:11:23.42#ibcon#[27=AT07-04\r\n] 2006.285.12:11:23.42#ibcon#*before write, iclass 16, count 2 2006.285.12:11:23.42#ibcon#enter sib2, iclass 16, count 2 2006.285.12:11:23.42#ibcon#flushed, iclass 16, count 2 2006.285.12:11:23.42#ibcon#about to write, iclass 16, count 2 2006.285.12:11:23.42#ibcon#wrote, iclass 16, count 2 2006.285.12:11:23.42#ibcon#about to read 3, iclass 16, count 2 2006.285.12:11:23.45#ibcon#read 3, iclass 16, count 2 2006.285.12:11:23.45#ibcon#about to read 4, iclass 16, count 2 2006.285.12:11:23.45#ibcon#read 4, iclass 16, count 2 2006.285.12:11:23.45#ibcon#about to read 5, iclass 16, count 2 2006.285.12:11:23.45#ibcon#read 5, iclass 16, count 2 2006.285.12:11:23.45#ibcon#about to read 6, iclass 16, count 2 2006.285.12:11:23.45#ibcon#read 6, iclass 16, count 2 2006.285.12:11:23.45#ibcon#end of sib2, iclass 16, count 2 2006.285.12:11:23.45#ibcon#*after write, iclass 16, count 2 2006.285.12:11:23.45#ibcon#*before return 0, iclass 16, count 2 2006.285.12:11:23.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:11:23.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:11:23.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.12:11:23.45#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:23.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:11:23.57#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:11:23.57#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:11:23.57#ibcon#enter wrdev, iclass 16, count 0 2006.285.12:11:23.57#ibcon#first serial, iclass 16, count 0 2006.285.12:11:23.57#ibcon#enter sib2, iclass 16, count 0 2006.285.12:11:23.57#ibcon#flushed, iclass 16, count 0 2006.285.12:11:23.57#ibcon#about to write, iclass 16, count 0 2006.285.12:11:23.57#ibcon#wrote, iclass 16, count 0 2006.285.12:11:23.57#ibcon#about to read 3, iclass 16, count 0 2006.285.12:11:23.59#ibcon#read 3, iclass 16, count 0 2006.285.12:11:23.59#ibcon#about to read 4, iclass 16, count 0 2006.285.12:11:23.59#ibcon#read 4, iclass 16, count 0 2006.285.12:11:23.59#ibcon#about to read 5, iclass 16, count 0 2006.285.12:11:23.59#ibcon#read 5, iclass 16, count 0 2006.285.12:11:23.59#ibcon#about to read 6, iclass 16, count 0 2006.285.12:11:23.59#ibcon#read 6, iclass 16, count 0 2006.285.12:11:23.59#ibcon#end of sib2, iclass 16, count 0 2006.285.12:11:23.59#ibcon#*mode == 0, iclass 16, count 0 2006.285.12:11:23.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.12:11:23.59#ibcon#[27=USB\r\n] 2006.285.12:11:23.59#ibcon#*before write, iclass 16, count 0 2006.285.12:11:23.59#ibcon#enter sib2, iclass 16, count 0 2006.285.12:11:23.59#ibcon#flushed, iclass 16, count 0 2006.285.12:11:23.59#ibcon#about to write, iclass 16, count 0 2006.285.12:11:23.59#ibcon#wrote, iclass 16, count 0 2006.285.12:11:23.59#ibcon#about to read 3, iclass 16, count 0 2006.285.12:11:23.62#ibcon#read 3, iclass 16, count 0 2006.285.12:11:23.62#ibcon#about to read 4, iclass 16, count 0 2006.285.12:11:23.62#ibcon#read 4, iclass 16, count 0 2006.285.12:11:23.62#ibcon#about to read 5, iclass 16, count 0 2006.285.12:11:23.62#ibcon#read 5, iclass 16, count 0 2006.285.12:11:23.62#ibcon#about to read 6, iclass 16, count 0 2006.285.12:11:23.62#ibcon#read 6, iclass 16, count 0 2006.285.12:11:23.62#ibcon#end of sib2, iclass 16, count 0 2006.285.12:11:23.62#ibcon#*after write, iclass 16, count 0 2006.285.12:11:23.62#ibcon#*before return 0, iclass 16, count 0 2006.285.12:11:23.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:11:23.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:11:23.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.12:11:23.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.12:11:23.62$vck44/vblo=8,744.99 2006.285.12:11:23.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.12:11:23.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.12:11:23.62#ibcon#ireg 17 cls_cnt 0 2006.285.12:11:23.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:11:23.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:11:23.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:11:23.62#ibcon#enter wrdev, iclass 18, count 0 2006.285.12:11:23.62#ibcon#first serial, iclass 18, count 0 2006.285.12:11:23.62#ibcon#enter sib2, iclass 18, count 0 2006.285.12:11:23.62#ibcon#flushed, iclass 18, count 0 2006.285.12:11:23.62#ibcon#about to write, iclass 18, count 0 2006.285.12:11:23.62#ibcon#wrote, iclass 18, count 0 2006.285.12:11:23.62#ibcon#about to read 3, iclass 18, count 0 2006.285.12:11:23.64#ibcon#read 3, iclass 18, count 0 2006.285.12:11:23.64#ibcon#about to read 4, iclass 18, count 0 2006.285.12:11:23.64#ibcon#read 4, iclass 18, count 0 2006.285.12:11:23.64#ibcon#about to read 5, iclass 18, count 0 2006.285.12:11:23.64#ibcon#read 5, iclass 18, count 0 2006.285.12:11:23.64#ibcon#about to read 6, iclass 18, count 0 2006.285.12:11:23.64#ibcon#read 6, iclass 18, count 0 2006.285.12:11:23.64#ibcon#end of sib2, iclass 18, count 0 2006.285.12:11:23.64#ibcon#*mode == 0, iclass 18, count 0 2006.285.12:11:23.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.12:11:23.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.12:11:23.64#ibcon#*before write, iclass 18, count 0 2006.285.12:11:23.64#ibcon#enter sib2, iclass 18, count 0 2006.285.12:11:23.64#ibcon#flushed, iclass 18, count 0 2006.285.12:11:23.64#ibcon#about to write, iclass 18, count 0 2006.285.12:11:23.64#ibcon#wrote, iclass 18, count 0 2006.285.12:11:23.64#ibcon#about to read 3, iclass 18, count 0 2006.285.12:11:23.68#ibcon#read 3, iclass 18, count 0 2006.285.12:11:23.68#ibcon#about to read 4, iclass 18, count 0 2006.285.12:11:23.68#ibcon#read 4, iclass 18, count 0 2006.285.12:11:23.68#ibcon#about to read 5, iclass 18, count 0 2006.285.12:11:23.68#ibcon#read 5, iclass 18, count 0 2006.285.12:11:23.68#ibcon#about to read 6, iclass 18, count 0 2006.285.12:11:23.68#ibcon#read 6, iclass 18, count 0 2006.285.12:11:23.68#ibcon#end of sib2, iclass 18, count 0 2006.285.12:11:23.68#ibcon#*after write, iclass 18, count 0 2006.285.12:11:23.68#ibcon#*before return 0, iclass 18, count 0 2006.285.12:11:23.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:11:23.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:11:23.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.12:11:23.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.12:11:23.68$vck44/vb=8,4 2006.285.12:11:23.68#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.12:11:23.68#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.12:11:23.68#ibcon#ireg 11 cls_cnt 2 2006.285.12:11:23.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:11:23.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:11:23.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:11:23.74#ibcon#enter wrdev, iclass 20, count 2 2006.285.12:11:23.74#ibcon#first serial, iclass 20, count 2 2006.285.12:11:23.74#ibcon#enter sib2, iclass 20, count 2 2006.285.12:11:23.74#ibcon#flushed, iclass 20, count 2 2006.285.12:11:23.74#ibcon#about to write, iclass 20, count 2 2006.285.12:11:23.74#ibcon#wrote, iclass 20, count 2 2006.285.12:11:23.74#ibcon#about to read 3, iclass 20, count 2 2006.285.12:11:23.76#ibcon#read 3, iclass 20, count 2 2006.285.12:11:23.76#ibcon#about to read 4, iclass 20, count 2 2006.285.12:11:23.76#ibcon#read 4, iclass 20, count 2 2006.285.12:11:23.76#ibcon#about to read 5, iclass 20, count 2 2006.285.12:11:23.76#ibcon#read 5, iclass 20, count 2 2006.285.12:11:23.76#ibcon#about to read 6, iclass 20, count 2 2006.285.12:11:23.76#ibcon#read 6, iclass 20, count 2 2006.285.12:11:23.76#ibcon#end of sib2, iclass 20, count 2 2006.285.12:11:23.76#ibcon#*mode == 0, iclass 20, count 2 2006.285.12:11:23.76#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.12:11:23.76#ibcon#[27=AT08-04\r\n] 2006.285.12:11:23.76#ibcon#*before write, iclass 20, count 2 2006.285.12:11:23.76#ibcon#enter sib2, iclass 20, count 2 2006.285.12:11:23.76#ibcon#flushed, iclass 20, count 2 2006.285.12:11:23.76#ibcon#about to write, iclass 20, count 2 2006.285.12:11:23.76#ibcon#wrote, iclass 20, count 2 2006.285.12:11:23.76#ibcon#about to read 3, iclass 20, count 2 2006.285.12:11:23.79#ibcon#read 3, iclass 20, count 2 2006.285.12:11:23.79#ibcon#about to read 4, iclass 20, count 2 2006.285.12:11:23.79#ibcon#read 4, iclass 20, count 2 2006.285.12:11:23.79#ibcon#about to read 5, iclass 20, count 2 2006.285.12:11:23.79#ibcon#read 5, iclass 20, count 2 2006.285.12:11:23.79#ibcon#about to read 6, iclass 20, count 2 2006.285.12:11:23.79#ibcon#read 6, iclass 20, count 2 2006.285.12:11:23.79#ibcon#end of sib2, iclass 20, count 2 2006.285.12:11:23.79#ibcon#*after write, iclass 20, count 2 2006.285.12:11:23.79#ibcon#*before return 0, iclass 20, count 2 2006.285.12:11:23.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:11:23.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:11:23.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.12:11:23.79#ibcon#ireg 7 cls_cnt 0 2006.285.12:11:23.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:11:23.91#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:11:23.91#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:11:23.91#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:11:23.91#ibcon#first serial, iclass 20, count 0 2006.285.12:11:23.91#ibcon#enter sib2, iclass 20, count 0 2006.285.12:11:23.91#ibcon#flushed, iclass 20, count 0 2006.285.12:11:23.91#ibcon#about to write, iclass 20, count 0 2006.285.12:11:23.91#ibcon#wrote, iclass 20, count 0 2006.285.12:11:23.91#ibcon#about to read 3, iclass 20, count 0 2006.285.12:11:23.93#ibcon#read 3, iclass 20, count 0 2006.285.12:11:23.93#ibcon#about to read 4, iclass 20, count 0 2006.285.12:11:23.93#ibcon#read 4, iclass 20, count 0 2006.285.12:11:23.93#ibcon#about to read 5, iclass 20, count 0 2006.285.12:11:23.93#ibcon#read 5, iclass 20, count 0 2006.285.12:11:23.93#ibcon#about to read 6, iclass 20, count 0 2006.285.12:11:23.93#ibcon#read 6, iclass 20, count 0 2006.285.12:11:23.93#ibcon#end of sib2, iclass 20, count 0 2006.285.12:11:23.93#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:11:23.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:11:23.93#ibcon#[27=USB\r\n] 2006.285.12:11:23.93#ibcon#*before write, iclass 20, count 0 2006.285.12:11:23.93#ibcon#enter sib2, iclass 20, count 0 2006.285.12:11:23.93#ibcon#flushed, iclass 20, count 0 2006.285.12:11:23.93#ibcon#about to write, iclass 20, count 0 2006.285.12:11:23.93#ibcon#wrote, iclass 20, count 0 2006.285.12:11:23.93#ibcon#about to read 3, iclass 20, count 0 2006.285.12:11:23.96#ibcon#read 3, iclass 20, count 0 2006.285.12:11:23.96#ibcon#about to read 4, iclass 20, count 0 2006.285.12:11:23.96#ibcon#read 4, iclass 20, count 0 2006.285.12:11:23.96#ibcon#about to read 5, iclass 20, count 0 2006.285.12:11:23.96#ibcon#read 5, iclass 20, count 0 2006.285.12:11:23.96#ibcon#about to read 6, iclass 20, count 0 2006.285.12:11:23.96#ibcon#read 6, iclass 20, count 0 2006.285.12:11:23.96#ibcon#end of sib2, iclass 20, count 0 2006.285.12:11:23.96#ibcon#*after write, iclass 20, count 0 2006.285.12:11:23.96#ibcon#*before return 0, iclass 20, count 0 2006.285.12:11:23.96#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:11:23.96#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:11:23.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:11:23.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:11:23.96$vck44/vabw=wide 2006.285.12:11:23.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.12:11:23.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.12:11:23.96#ibcon#ireg 8 cls_cnt 0 2006.285.12:11:23.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:11:23.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:11:23.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:11:23.96#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:11:23.96#ibcon#first serial, iclass 22, count 0 2006.285.12:11:23.96#ibcon#enter sib2, iclass 22, count 0 2006.285.12:11:23.96#ibcon#flushed, iclass 22, count 0 2006.285.12:11:23.96#ibcon#about to write, iclass 22, count 0 2006.285.12:11:23.96#ibcon#wrote, iclass 22, count 0 2006.285.12:11:23.96#ibcon#about to read 3, iclass 22, count 0 2006.285.12:11:23.98#ibcon#read 3, iclass 22, count 0 2006.285.12:11:23.98#ibcon#about to read 4, iclass 22, count 0 2006.285.12:11:23.98#ibcon#read 4, iclass 22, count 0 2006.285.12:11:23.98#ibcon#about to read 5, iclass 22, count 0 2006.285.12:11:23.98#ibcon#read 5, iclass 22, count 0 2006.285.12:11:23.98#ibcon#about to read 6, iclass 22, count 0 2006.285.12:11:23.98#ibcon#read 6, iclass 22, count 0 2006.285.12:11:23.98#ibcon#end of sib2, iclass 22, count 0 2006.285.12:11:23.98#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:11:23.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:11:23.98#ibcon#[25=BW32\r\n] 2006.285.12:11:23.98#ibcon#*before write, iclass 22, count 0 2006.285.12:11:23.98#ibcon#enter sib2, iclass 22, count 0 2006.285.12:11:23.98#ibcon#flushed, iclass 22, count 0 2006.285.12:11:23.98#ibcon#about to write, iclass 22, count 0 2006.285.12:11:23.98#ibcon#wrote, iclass 22, count 0 2006.285.12:11:23.98#ibcon#about to read 3, iclass 22, count 0 2006.285.12:11:24.01#ibcon#read 3, iclass 22, count 0 2006.285.12:11:24.01#ibcon#about to read 4, iclass 22, count 0 2006.285.12:11:24.01#ibcon#read 4, iclass 22, count 0 2006.285.12:11:24.01#ibcon#about to read 5, iclass 22, count 0 2006.285.12:11:24.01#ibcon#read 5, iclass 22, count 0 2006.285.12:11:24.01#ibcon#about to read 6, iclass 22, count 0 2006.285.12:11:24.01#ibcon#read 6, iclass 22, count 0 2006.285.12:11:24.01#ibcon#end of sib2, iclass 22, count 0 2006.285.12:11:24.01#ibcon#*after write, iclass 22, count 0 2006.285.12:11:24.01#ibcon#*before return 0, iclass 22, count 0 2006.285.12:11:24.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:11:24.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:11:24.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:11:24.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:11:24.01$vck44/vbbw=wide 2006.285.12:11:24.01#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.12:11:24.01#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.12:11:24.01#ibcon#ireg 8 cls_cnt 0 2006.285.12:11:24.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:11:24.08#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:11:24.08#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:11:24.08#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:11:24.08#ibcon#first serial, iclass 24, count 0 2006.285.12:11:24.08#ibcon#enter sib2, iclass 24, count 0 2006.285.12:11:24.08#ibcon#flushed, iclass 24, count 0 2006.285.12:11:24.08#ibcon#about to write, iclass 24, count 0 2006.285.12:11:24.08#ibcon#wrote, iclass 24, count 0 2006.285.12:11:24.08#ibcon#about to read 3, iclass 24, count 0 2006.285.12:11:24.10#ibcon#read 3, iclass 24, count 0 2006.285.12:11:24.10#ibcon#about to read 4, iclass 24, count 0 2006.285.12:11:24.10#ibcon#read 4, iclass 24, count 0 2006.285.12:11:24.10#ibcon#about to read 5, iclass 24, count 0 2006.285.12:11:24.10#ibcon#read 5, iclass 24, count 0 2006.285.12:11:24.10#ibcon#about to read 6, iclass 24, count 0 2006.285.12:11:24.10#ibcon#read 6, iclass 24, count 0 2006.285.12:11:24.10#ibcon#end of sib2, iclass 24, count 0 2006.285.12:11:24.10#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:11:24.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:11:24.10#ibcon#[27=BW32\r\n] 2006.285.12:11:24.10#ibcon#*before write, iclass 24, count 0 2006.285.12:11:24.10#ibcon#enter sib2, iclass 24, count 0 2006.285.12:11:24.10#ibcon#flushed, iclass 24, count 0 2006.285.12:11:24.10#ibcon#about to write, iclass 24, count 0 2006.285.12:11:24.10#ibcon#wrote, iclass 24, count 0 2006.285.12:11:24.10#ibcon#about to read 3, iclass 24, count 0 2006.285.12:11:24.13#ibcon#read 3, iclass 24, count 0 2006.285.12:11:24.13#ibcon#about to read 4, iclass 24, count 0 2006.285.12:11:24.13#ibcon#read 4, iclass 24, count 0 2006.285.12:11:24.13#ibcon#about to read 5, iclass 24, count 0 2006.285.12:11:24.13#ibcon#read 5, iclass 24, count 0 2006.285.12:11:24.13#ibcon#about to read 6, iclass 24, count 0 2006.285.12:11:24.13#ibcon#read 6, iclass 24, count 0 2006.285.12:11:24.13#ibcon#end of sib2, iclass 24, count 0 2006.285.12:11:24.13#ibcon#*after write, iclass 24, count 0 2006.285.12:11:24.13#ibcon#*before return 0, iclass 24, count 0 2006.285.12:11:24.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:11:24.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:11:24.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:11:24.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:11:24.13$setupk4/ifdk4 2006.285.12:11:24.13$ifdk4/lo= 2006.285.12:11:24.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.12:11:24.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.12:11:24.13$ifdk4/patch= 2006.285.12:11:24.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.12:11:24.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.12:11:24.13$setupk4/!*+20s 2006.285.12:11:32.13#trakl#Source acquired 2006.285.12:11:32.13#flagr#flagr/antenna,acquired 2006.285.12:11:32.25#abcon#<5=/04 1.1 1.7 18.98 941015.5\r\n> 2006.285.12:11:32.27#abcon#{5=INTERFACE CLEAR} 2006.285.12:11:32.33#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:11:38.63$setupk4/"tpicd 2006.285.12:11:38.63$setupk4/echo=off 2006.285.12:11:38.63$setupk4/xlog=off 2006.285.12:11:38.63:!2006.285.12:13:34 2006.285.12:13:34.00:preob 2006.285.12:13:34.14/onsource/TRACKING 2006.285.12:13:34.14:!2006.285.12:13:44 2006.285.12:13:44.00:"tape 2006.285.12:13:44.00:"st=record 2006.285.12:13:44.00:data_valid=on 2006.285.12:13:44.00:midob 2006.285.12:13:44.14/onsource/TRACKING 2006.285.12:13:44.14/wx/18.97,1015.5,94 2006.285.12:13:44.27/cable/+6.4947E-03 2006.285.12:13:45.36/va/01,07,usb,yes,32,34 2006.285.12:13:45.36/va/02,06,usb,yes,32,32 2006.285.12:13:45.36/va/03,07,usb,yes,31,33 2006.285.12:13:45.36/va/04,06,usb,yes,33,34 2006.285.12:13:45.36/va/05,03,usb,yes,32,33 2006.285.12:13:45.36/va/06,04,usb,yes,29,29 2006.285.12:13:45.36/va/07,04,usb,yes,30,30 2006.285.12:13:45.36/va/08,03,usb,yes,30,37 2006.285.12:13:45.59/valo/01,524.99,yes,locked 2006.285.12:13:45.59/valo/02,534.99,yes,locked 2006.285.12:13:45.59/valo/03,564.99,yes,locked 2006.285.12:13:45.59/valo/04,624.99,yes,locked 2006.285.12:13:45.59/valo/05,734.99,yes,locked 2006.285.12:13:45.59/valo/06,814.99,yes,locked 2006.285.12:13:45.59/valo/07,864.99,yes,locked 2006.285.12:13:45.59/valo/08,884.99,yes,locked 2006.285.12:13:46.68/vb/01,04,usb,yes,30,28 2006.285.12:13:46.68/vb/02,05,usb,yes,29,28 2006.285.12:13:46.68/vb/03,04,usb,yes,30,33 2006.285.12:13:46.68/vb/04,05,usb,yes,30,29 2006.285.12:13:46.68/vb/05,04,usb,yes,26,29 2006.285.12:13:46.68/vb/06,03,usb,yes,38,33 2006.285.12:13:46.68/vb/07,04,usb,yes,30,30 2006.285.12:13:46.68/vb/08,04,usb,yes,28,31 2006.285.12:13:46.92/vblo/01,629.99,yes,locked 2006.285.12:13:46.92/vblo/02,634.99,yes,locked 2006.285.12:13:46.92/vblo/03,649.99,yes,locked 2006.285.12:13:46.92/vblo/04,679.99,yes,locked 2006.285.12:13:46.92/vblo/05,709.99,yes,locked 2006.285.12:13:46.92/vblo/06,719.99,yes,locked 2006.285.12:13:46.92/vblo/07,734.99,yes,locked 2006.285.12:13:46.92/vblo/08,744.99,yes,locked 2006.285.12:13:47.07/vabw/8 2006.285.12:13:47.22/vbbw/8 2006.285.12:13:47.31/xfe/off,on,12.2 2006.285.12:13:47.69/ifatt/23,28,28,28 2006.285.12:13:48.08/fmout-gps/S +2.46E-07 2006.285.12:13:48.10:!2006.285.12:16:24 2006.285.12:16:24.00:data_valid=off 2006.285.12:16:24.00:"et 2006.285.12:16:24.00:!+3s 2006.285.12:16:27.01:"tape 2006.285.12:16:27.01:postob 2006.285.12:16:27.19/cable/+6.4945E-03 2006.285.12:16:27.19/wx/18.95,1015.5,95 2006.285.12:16:28.08/fmout-gps/S +2.41E-07 2006.285.12:16:28.08:scan_name=285-1219,jd0610,160 2006.285.12:16:28.08:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.285.12:16:29.14#flagr#flagr/antenna,new-source 2006.285.12:16:29.14:checkk5 2006.285.12:16:29.50/chk_autoobs//k5ts1/ autoobs is running! 2006.285.12:16:29.91/chk_autoobs//k5ts2/ autoobs is running! 2006.285.12:16:30.51/chk_autoobs//k5ts3/ autoobs is running! 2006.285.12:16:30.88/chk_autoobs//k5ts4/ autoobs is running! 2006.285.12:16:31.25/chk_obsdata//k5ts1/T2851213??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.12:16:31.60/chk_obsdata//k5ts2/T2851213??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.12:16:31.98/chk_obsdata//k5ts3/T2851213??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.12:16:32.58/chk_obsdata//k5ts4/T2851213??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.12:16:33.40/k5log//k5ts1_log_newline 2006.285.12:16:34.63/k5log//k5ts2_log_newline 2006.285.12:16:35.41/k5log//k5ts3_log_newline 2006.285.12:16:36.20/k5log//k5ts4_log_newline 2006.285.12:16:36.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.12:16:36.22:setupk4=1 2006.285.12:16:36.22$setupk4/echo=on 2006.285.12:16:36.22$setupk4/pcalon 2006.285.12:16:36.22$pcalon/"no phase cal control is implemented here 2006.285.12:16:36.22$setupk4/"tpicd=stop 2006.285.12:16:36.22$setupk4/"rec=synch_on 2006.285.12:16:36.22$setupk4/"rec_mode=128 2006.285.12:16:36.22$setupk4/!* 2006.285.12:16:36.22$setupk4/recpk4 2006.285.12:16:36.22$recpk4/recpatch= 2006.285.12:16:36.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.12:16:36.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.12:16:36.23$setupk4/vck44 2006.285.12:16:36.23$vck44/valo=1,524.99 2006.285.12:16:36.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.12:16:36.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.12:16:36.23#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:36.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:16:36.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:16:36.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:16:36.23#ibcon#enter wrdev, iclass 36, count 0 2006.285.12:16:36.23#ibcon#first serial, iclass 36, count 0 2006.285.12:16:36.23#ibcon#enter sib2, iclass 36, count 0 2006.285.12:16:36.23#ibcon#flushed, iclass 36, count 0 2006.285.12:16:36.23#ibcon#about to write, iclass 36, count 0 2006.285.12:16:36.23#ibcon#wrote, iclass 36, count 0 2006.285.12:16:36.23#ibcon#about to read 3, iclass 36, count 0 2006.285.12:16:36.25#ibcon#read 3, iclass 36, count 0 2006.285.12:16:36.25#ibcon#about to read 4, iclass 36, count 0 2006.285.12:16:36.25#ibcon#read 4, iclass 36, count 0 2006.285.12:16:36.25#ibcon#about to read 5, iclass 36, count 0 2006.285.12:16:36.25#ibcon#read 5, iclass 36, count 0 2006.285.12:16:36.25#ibcon#about to read 6, iclass 36, count 0 2006.285.12:16:36.25#ibcon#read 6, iclass 36, count 0 2006.285.12:16:36.25#ibcon#end of sib2, iclass 36, count 0 2006.285.12:16:36.25#ibcon#*mode == 0, iclass 36, count 0 2006.285.12:16:36.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.12:16:36.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.12:16:36.25#ibcon#*before write, iclass 36, count 0 2006.285.12:16:36.25#ibcon#enter sib2, iclass 36, count 0 2006.285.12:16:36.25#ibcon#flushed, iclass 36, count 0 2006.285.12:16:36.25#ibcon#about to write, iclass 36, count 0 2006.285.12:16:36.25#ibcon#wrote, iclass 36, count 0 2006.285.12:16:36.25#ibcon#about to read 3, iclass 36, count 0 2006.285.12:16:36.30#ibcon#read 3, iclass 36, count 0 2006.285.12:16:36.30#ibcon#about to read 4, iclass 36, count 0 2006.285.12:16:36.30#ibcon#read 4, iclass 36, count 0 2006.285.12:16:36.30#ibcon#about to read 5, iclass 36, count 0 2006.285.12:16:36.30#ibcon#read 5, iclass 36, count 0 2006.285.12:16:36.30#ibcon#about to read 6, iclass 36, count 0 2006.285.12:16:36.30#ibcon#read 6, iclass 36, count 0 2006.285.12:16:36.30#ibcon#end of sib2, iclass 36, count 0 2006.285.12:16:36.30#ibcon#*after write, iclass 36, count 0 2006.285.12:16:36.30#ibcon#*before return 0, iclass 36, count 0 2006.285.12:16:36.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:16:36.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:16:36.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.12:16:36.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.12:16:36.30$vck44/va=1,7 2006.285.12:16:36.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.12:16:36.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.12:16:36.30#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:36.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:16:36.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:16:36.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:16:36.30#ibcon#enter wrdev, iclass 38, count 2 2006.285.12:16:36.30#ibcon#first serial, iclass 38, count 2 2006.285.12:16:36.30#ibcon#enter sib2, iclass 38, count 2 2006.285.12:16:36.30#ibcon#flushed, iclass 38, count 2 2006.285.12:16:36.30#ibcon#about to write, iclass 38, count 2 2006.285.12:16:36.30#ibcon#wrote, iclass 38, count 2 2006.285.12:16:36.30#ibcon#about to read 3, iclass 38, count 2 2006.285.12:16:36.32#ibcon#read 3, iclass 38, count 2 2006.285.12:16:36.32#ibcon#about to read 4, iclass 38, count 2 2006.285.12:16:36.32#ibcon#read 4, iclass 38, count 2 2006.285.12:16:36.32#ibcon#about to read 5, iclass 38, count 2 2006.285.12:16:36.32#ibcon#read 5, iclass 38, count 2 2006.285.12:16:36.32#ibcon#about to read 6, iclass 38, count 2 2006.285.12:16:36.32#ibcon#read 6, iclass 38, count 2 2006.285.12:16:36.32#ibcon#end of sib2, iclass 38, count 2 2006.285.12:16:36.32#ibcon#*mode == 0, iclass 38, count 2 2006.285.12:16:36.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.12:16:36.32#ibcon#[25=AT01-07\r\n] 2006.285.12:16:36.32#ibcon#*before write, iclass 38, count 2 2006.285.12:16:36.32#ibcon#enter sib2, iclass 38, count 2 2006.285.12:16:36.32#ibcon#flushed, iclass 38, count 2 2006.285.12:16:36.32#ibcon#about to write, iclass 38, count 2 2006.285.12:16:36.32#ibcon#wrote, iclass 38, count 2 2006.285.12:16:36.32#ibcon#about to read 3, iclass 38, count 2 2006.285.12:16:36.35#ibcon#read 3, iclass 38, count 2 2006.285.12:16:36.35#ibcon#about to read 4, iclass 38, count 2 2006.285.12:16:36.35#ibcon#read 4, iclass 38, count 2 2006.285.12:16:36.35#ibcon#about to read 5, iclass 38, count 2 2006.285.12:16:36.35#ibcon#read 5, iclass 38, count 2 2006.285.12:16:36.35#ibcon#about to read 6, iclass 38, count 2 2006.285.12:16:36.35#ibcon#read 6, iclass 38, count 2 2006.285.12:16:36.35#ibcon#end of sib2, iclass 38, count 2 2006.285.12:16:36.35#ibcon#*after write, iclass 38, count 2 2006.285.12:16:36.35#ibcon#*before return 0, iclass 38, count 2 2006.285.12:16:36.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:16:36.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:16:36.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.12:16:36.35#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:36.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:16:36.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:16:36.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:16:36.47#ibcon#enter wrdev, iclass 38, count 0 2006.285.12:16:36.47#ibcon#first serial, iclass 38, count 0 2006.285.12:16:36.47#ibcon#enter sib2, iclass 38, count 0 2006.285.12:16:36.47#ibcon#flushed, iclass 38, count 0 2006.285.12:16:36.47#ibcon#about to write, iclass 38, count 0 2006.285.12:16:36.47#ibcon#wrote, iclass 38, count 0 2006.285.12:16:36.47#ibcon#about to read 3, iclass 38, count 0 2006.285.12:16:36.49#ibcon#read 3, iclass 38, count 0 2006.285.12:16:36.49#ibcon#about to read 4, iclass 38, count 0 2006.285.12:16:36.49#ibcon#read 4, iclass 38, count 0 2006.285.12:16:36.49#ibcon#about to read 5, iclass 38, count 0 2006.285.12:16:36.49#ibcon#read 5, iclass 38, count 0 2006.285.12:16:36.49#ibcon#about to read 6, iclass 38, count 0 2006.285.12:16:36.49#ibcon#read 6, iclass 38, count 0 2006.285.12:16:36.49#ibcon#end of sib2, iclass 38, count 0 2006.285.12:16:36.49#ibcon#*mode == 0, iclass 38, count 0 2006.285.12:16:36.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.12:16:36.49#ibcon#[25=USB\r\n] 2006.285.12:16:36.49#ibcon#*before write, iclass 38, count 0 2006.285.12:16:36.49#ibcon#enter sib2, iclass 38, count 0 2006.285.12:16:36.49#ibcon#flushed, iclass 38, count 0 2006.285.12:16:36.49#ibcon#about to write, iclass 38, count 0 2006.285.12:16:36.49#ibcon#wrote, iclass 38, count 0 2006.285.12:16:36.49#ibcon#about to read 3, iclass 38, count 0 2006.285.12:16:36.52#ibcon#read 3, iclass 38, count 0 2006.285.12:16:36.52#ibcon#about to read 4, iclass 38, count 0 2006.285.12:16:36.52#ibcon#read 4, iclass 38, count 0 2006.285.12:16:36.52#ibcon#about to read 5, iclass 38, count 0 2006.285.12:16:36.52#ibcon#read 5, iclass 38, count 0 2006.285.12:16:36.52#ibcon#about to read 6, iclass 38, count 0 2006.285.12:16:36.52#ibcon#read 6, iclass 38, count 0 2006.285.12:16:36.52#ibcon#end of sib2, iclass 38, count 0 2006.285.12:16:36.52#ibcon#*after write, iclass 38, count 0 2006.285.12:16:36.52#ibcon#*before return 0, iclass 38, count 0 2006.285.12:16:36.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:16:36.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:16:36.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.12:16:36.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.12:16:36.52$vck44/valo=2,534.99 2006.285.12:16:36.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.12:16:36.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.12:16:36.52#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:36.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:16:36.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:16:36.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:16:36.52#ibcon#enter wrdev, iclass 40, count 0 2006.285.12:16:36.52#ibcon#first serial, iclass 40, count 0 2006.285.12:16:36.52#ibcon#enter sib2, iclass 40, count 0 2006.285.12:16:36.52#ibcon#flushed, iclass 40, count 0 2006.285.12:16:36.52#ibcon#about to write, iclass 40, count 0 2006.285.12:16:36.52#ibcon#wrote, iclass 40, count 0 2006.285.12:16:36.52#ibcon#about to read 3, iclass 40, count 0 2006.285.12:16:36.54#ibcon#read 3, iclass 40, count 0 2006.285.12:16:36.54#ibcon#about to read 4, iclass 40, count 0 2006.285.12:16:36.54#ibcon#read 4, iclass 40, count 0 2006.285.12:16:36.54#ibcon#about to read 5, iclass 40, count 0 2006.285.12:16:36.54#ibcon#read 5, iclass 40, count 0 2006.285.12:16:36.54#ibcon#about to read 6, iclass 40, count 0 2006.285.12:16:36.54#ibcon#read 6, iclass 40, count 0 2006.285.12:16:36.54#ibcon#end of sib2, iclass 40, count 0 2006.285.12:16:36.54#ibcon#*mode == 0, iclass 40, count 0 2006.285.12:16:36.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.12:16:36.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.12:16:36.54#ibcon#*before write, iclass 40, count 0 2006.285.12:16:36.54#ibcon#enter sib2, iclass 40, count 0 2006.285.12:16:36.54#ibcon#flushed, iclass 40, count 0 2006.285.12:16:36.54#ibcon#about to write, iclass 40, count 0 2006.285.12:16:36.54#ibcon#wrote, iclass 40, count 0 2006.285.12:16:36.54#ibcon#about to read 3, iclass 40, count 0 2006.285.12:16:36.58#ibcon#read 3, iclass 40, count 0 2006.285.12:16:36.58#ibcon#about to read 4, iclass 40, count 0 2006.285.12:16:36.58#ibcon#read 4, iclass 40, count 0 2006.285.12:16:36.58#ibcon#about to read 5, iclass 40, count 0 2006.285.12:16:36.58#ibcon#read 5, iclass 40, count 0 2006.285.12:16:36.58#ibcon#about to read 6, iclass 40, count 0 2006.285.12:16:36.58#ibcon#read 6, iclass 40, count 0 2006.285.12:16:36.58#ibcon#end of sib2, iclass 40, count 0 2006.285.12:16:36.58#ibcon#*after write, iclass 40, count 0 2006.285.12:16:36.58#ibcon#*before return 0, iclass 40, count 0 2006.285.12:16:36.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:16:36.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:16:36.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.12:16:36.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.12:16:36.58$vck44/va=2,6 2006.285.12:16:36.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.12:16:36.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.12:16:36.58#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:36.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:16:36.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:16:36.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:16:36.64#ibcon#enter wrdev, iclass 4, count 2 2006.285.12:16:36.64#ibcon#first serial, iclass 4, count 2 2006.285.12:16:36.64#ibcon#enter sib2, iclass 4, count 2 2006.285.12:16:36.64#ibcon#flushed, iclass 4, count 2 2006.285.12:16:36.64#ibcon#about to write, iclass 4, count 2 2006.285.12:16:36.64#ibcon#wrote, iclass 4, count 2 2006.285.12:16:36.64#ibcon#about to read 3, iclass 4, count 2 2006.285.12:16:36.66#ibcon#read 3, iclass 4, count 2 2006.285.12:16:36.66#ibcon#about to read 4, iclass 4, count 2 2006.285.12:16:36.66#ibcon#read 4, iclass 4, count 2 2006.285.12:16:36.66#ibcon#about to read 5, iclass 4, count 2 2006.285.12:16:36.66#ibcon#read 5, iclass 4, count 2 2006.285.12:16:36.66#ibcon#about to read 6, iclass 4, count 2 2006.285.12:16:36.66#ibcon#read 6, iclass 4, count 2 2006.285.12:16:36.66#ibcon#end of sib2, iclass 4, count 2 2006.285.12:16:36.66#ibcon#*mode == 0, iclass 4, count 2 2006.285.12:16:36.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.12:16:36.66#ibcon#[25=AT02-06\r\n] 2006.285.12:16:36.66#ibcon#*before write, iclass 4, count 2 2006.285.12:16:36.66#ibcon#enter sib2, iclass 4, count 2 2006.285.12:16:36.66#ibcon#flushed, iclass 4, count 2 2006.285.12:16:36.66#ibcon#about to write, iclass 4, count 2 2006.285.12:16:36.66#ibcon#wrote, iclass 4, count 2 2006.285.12:16:36.66#ibcon#about to read 3, iclass 4, count 2 2006.285.12:16:36.69#ibcon#read 3, iclass 4, count 2 2006.285.12:16:36.69#ibcon#about to read 4, iclass 4, count 2 2006.285.12:16:36.69#ibcon#read 4, iclass 4, count 2 2006.285.12:16:36.69#ibcon#about to read 5, iclass 4, count 2 2006.285.12:16:36.69#ibcon#read 5, iclass 4, count 2 2006.285.12:16:36.69#ibcon#about to read 6, iclass 4, count 2 2006.285.12:16:36.69#ibcon#read 6, iclass 4, count 2 2006.285.12:16:36.69#ibcon#end of sib2, iclass 4, count 2 2006.285.12:16:36.69#ibcon#*after write, iclass 4, count 2 2006.285.12:16:36.69#ibcon#*before return 0, iclass 4, count 2 2006.285.12:16:36.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:16:36.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:16:36.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.12:16:36.69#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:36.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:16:36.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:16:36.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:16:36.81#ibcon#enter wrdev, iclass 4, count 0 2006.285.12:16:36.81#ibcon#first serial, iclass 4, count 0 2006.285.12:16:36.81#ibcon#enter sib2, iclass 4, count 0 2006.285.12:16:36.81#ibcon#flushed, iclass 4, count 0 2006.285.12:16:36.81#ibcon#about to write, iclass 4, count 0 2006.285.12:16:36.81#ibcon#wrote, iclass 4, count 0 2006.285.12:16:36.81#ibcon#about to read 3, iclass 4, count 0 2006.285.12:16:36.83#ibcon#read 3, iclass 4, count 0 2006.285.12:16:36.83#ibcon#about to read 4, iclass 4, count 0 2006.285.12:16:36.83#ibcon#read 4, iclass 4, count 0 2006.285.12:16:36.83#ibcon#about to read 5, iclass 4, count 0 2006.285.12:16:36.83#ibcon#read 5, iclass 4, count 0 2006.285.12:16:36.83#ibcon#about to read 6, iclass 4, count 0 2006.285.12:16:36.83#ibcon#read 6, iclass 4, count 0 2006.285.12:16:36.83#ibcon#end of sib2, iclass 4, count 0 2006.285.12:16:36.83#ibcon#*mode == 0, iclass 4, count 0 2006.285.12:16:36.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.12:16:36.83#ibcon#[25=USB\r\n] 2006.285.12:16:36.83#ibcon#*before write, iclass 4, count 0 2006.285.12:16:36.83#ibcon#enter sib2, iclass 4, count 0 2006.285.12:16:36.83#ibcon#flushed, iclass 4, count 0 2006.285.12:16:36.83#ibcon#about to write, iclass 4, count 0 2006.285.12:16:36.83#ibcon#wrote, iclass 4, count 0 2006.285.12:16:36.83#ibcon#about to read 3, iclass 4, count 0 2006.285.12:16:36.86#ibcon#read 3, iclass 4, count 0 2006.285.12:16:36.86#ibcon#about to read 4, iclass 4, count 0 2006.285.12:16:36.86#ibcon#read 4, iclass 4, count 0 2006.285.12:16:36.86#ibcon#about to read 5, iclass 4, count 0 2006.285.12:16:36.86#ibcon#read 5, iclass 4, count 0 2006.285.12:16:36.86#ibcon#about to read 6, iclass 4, count 0 2006.285.12:16:36.86#ibcon#read 6, iclass 4, count 0 2006.285.12:16:36.86#ibcon#end of sib2, iclass 4, count 0 2006.285.12:16:36.86#ibcon#*after write, iclass 4, count 0 2006.285.12:16:36.86#ibcon#*before return 0, iclass 4, count 0 2006.285.12:16:36.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:16:36.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:16:36.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.12:16:36.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.12:16:36.86$vck44/valo=3,564.99 2006.285.12:16:36.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.12:16:36.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.12:16:36.86#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:36.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:16:36.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:16:36.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:16:36.86#ibcon#enter wrdev, iclass 6, count 0 2006.285.12:16:36.86#ibcon#first serial, iclass 6, count 0 2006.285.12:16:36.86#ibcon#enter sib2, iclass 6, count 0 2006.285.12:16:36.86#ibcon#flushed, iclass 6, count 0 2006.285.12:16:36.86#ibcon#about to write, iclass 6, count 0 2006.285.12:16:36.86#ibcon#wrote, iclass 6, count 0 2006.285.12:16:36.86#ibcon#about to read 3, iclass 6, count 0 2006.285.12:16:36.88#ibcon#read 3, iclass 6, count 0 2006.285.12:16:36.88#ibcon#about to read 4, iclass 6, count 0 2006.285.12:16:36.88#ibcon#read 4, iclass 6, count 0 2006.285.12:16:36.88#ibcon#about to read 5, iclass 6, count 0 2006.285.12:16:36.88#ibcon#read 5, iclass 6, count 0 2006.285.12:16:36.88#ibcon#about to read 6, iclass 6, count 0 2006.285.12:16:36.88#ibcon#read 6, iclass 6, count 0 2006.285.12:16:36.88#ibcon#end of sib2, iclass 6, count 0 2006.285.12:16:36.88#ibcon#*mode == 0, iclass 6, count 0 2006.285.12:16:36.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.12:16:36.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.12:16:36.88#ibcon#*before write, iclass 6, count 0 2006.285.12:16:36.88#ibcon#enter sib2, iclass 6, count 0 2006.285.12:16:36.88#ibcon#flushed, iclass 6, count 0 2006.285.12:16:36.88#ibcon#about to write, iclass 6, count 0 2006.285.12:16:36.88#ibcon#wrote, iclass 6, count 0 2006.285.12:16:36.88#ibcon#about to read 3, iclass 6, count 0 2006.285.12:16:36.92#ibcon#read 3, iclass 6, count 0 2006.285.12:16:36.92#ibcon#about to read 4, iclass 6, count 0 2006.285.12:16:36.92#ibcon#read 4, iclass 6, count 0 2006.285.12:16:36.92#ibcon#about to read 5, iclass 6, count 0 2006.285.12:16:36.92#ibcon#read 5, iclass 6, count 0 2006.285.12:16:36.92#ibcon#about to read 6, iclass 6, count 0 2006.285.12:16:36.92#ibcon#read 6, iclass 6, count 0 2006.285.12:16:36.92#ibcon#end of sib2, iclass 6, count 0 2006.285.12:16:36.92#ibcon#*after write, iclass 6, count 0 2006.285.12:16:36.92#ibcon#*before return 0, iclass 6, count 0 2006.285.12:16:36.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:16:36.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:16:36.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.12:16:36.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.12:16:36.92$vck44/va=3,7 2006.285.12:16:36.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.12:16:36.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.12:16:36.92#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:36.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:16:36.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:16:36.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:16:36.98#ibcon#enter wrdev, iclass 10, count 2 2006.285.12:16:36.98#ibcon#first serial, iclass 10, count 2 2006.285.12:16:36.98#ibcon#enter sib2, iclass 10, count 2 2006.285.12:16:36.98#ibcon#flushed, iclass 10, count 2 2006.285.12:16:36.98#ibcon#about to write, iclass 10, count 2 2006.285.12:16:36.98#ibcon#wrote, iclass 10, count 2 2006.285.12:16:36.98#ibcon#about to read 3, iclass 10, count 2 2006.285.12:16:37.00#ibcon#read 3, iclass 10, count 2 2006.285.12:16:37.00#ibcon#about to read 4, iclass 10, count 2 2006.285.12:16:37.00#ibcon#read 4, iclass 10, count 2 2006.285.12:16:37.00#ibcon#about to read 5, iclass 10, count 2 2006.285.12:16:37.00#ibcon#read 5, iclass 10, count 2 2006.285.12:16:37.00#ibcon#about to read 6, iclass 10, count 2 2006.285.12:16:37.00#ibcon#read 6, iclass 10, count 2 2006.285.12:16:37.00#ibcon#end of sib2, iclass 10, count 2 2006.285.12:16:37.00#ibcon#*mode == 0, iclass 10, count 2 2006.285.12:16:37.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.12:16:37.00#ibcon#[25=AT03-07\r\n] 2006.285.12:16:37.00#ibcon#*before write, iclass 10, count 2 2006.285.12:16:37.00#ibcon#enter sib2, iclass 10, count 2 2006.285.12:16:37.00#ibcon#flushed, iclass 10, count 2 2006.285.12:16:37.00#ibcon#about to write, iclass 10, count 2 2006.285.12:16:37.00#ibcon#wrote, iclass 10, count 2 2006.285.12:16:37.00#ibcon#about to read 3, iclass 10, count 2 2006.285.12:16:37.03#ibcon#read 3, iclass 10, count 2 2006.285.12:16:37.03#ibcon#about to read 4, iclass 10, count 2 2006.285.12:16:37.03#ibcon#read 4, iclass 10, count 2 2006.285.12:16:37.03#ibcon#about to read 5, iclass 10, count 2 2006.285.12:16:37.03#ibcon#read 5, iclass 10, count 2 2006.285.12:16:37.03#ibcon#about to read 6, iclass 10, count 2 2006.285.12:16:37.03#ibcon#read 6, iclass 10, count 2 2006.285.12:16:37.03#ibcon#end of sib2, iclass 10, count 2 2006.285.12:16:37.03#ibcon#*after write, iclass 10, count 2 2006.285.12:16:37.03#ibcon#*before return 0, iclass 10, count 2 2006.285.12:16:37.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:16:37.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:16:37.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.12:16:37.03#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:37.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:16:37.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:16:37.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:16:37.15#ibcon#enter wrdev, iclass 10, count 0 2006.285.12:16:37.15#ibcon#first serial, iclass 10, count 0 2006.285.12:16:37.15#ibcon#enter sib2, iclass 10, count 0 2006.285.12:16:37.15#ibcon#flushed, iclass 10, count 0 2006.285.12:16:37.15#ibcon#about to write, iclass 10, count 0 2006.285.12:16:37.15#ibcon#wrote, iclass 10, count 0 2006.285.12:16:37.15#ibcon#about to read 3, iclass 10, count 0 2006.285.12:16:37.17#ibcon#read 3, iclass 10, count 0 2006.285.12:16:37.17#ibcon#about to read 4, iclass 10, count 0 2006.285.12:16:37.17#ibcon#read 4, iclass 10, count 0 2006.285.12:16:37.17#ibcon#about to read 5, iclass 10, count 0 2006.285.12:16:37.17#ibcon#read 5, iclass 10, count 0 2006.285.12:16:37.17#ibcon#about to read 6, iclass 10, count 0 2006.285.12:16:37.17#ibcon#read 6, iclass 10, count 0 2006.285.12:16:37.17#ibcon#end of sib2, iclass 10, count 0 2006.285.12:16:37.17#ibcon#*mode == 0, iclass 10, count 0 2006.285.12:16:37.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.12:16:37.17#ibcon#[25=USB\r\n] 2006.285.12:16:37.17#ibcon#*before write, iclass 10, count 0 2006.285.12:16:37.17#ibcon#enter sib2, iclass 10, count 0 2006.285.12:16:37.17#ibcon#flushed, iclass 10, count 0 2006.285.12:16:37.17#ibcon#about to write, iclass 10, count 0 2006.285.12:16:37.17#ibcon#wrote, iclass 10, count 0 2006.285.12:16:37.17#ibcon#about to read 3, iclass 10, count 0 2006.285.12:16:37.20#ibcon#read 3, iclass 10, count 0 2006.285.12:16:37.20#ibcon#about to read 4, iclass 10, count 0 2006.285.12:16:37.20#ibcon#read 4, iclass 10, count 0 2006.285.12:16:37.20#ibcon#about to read 5, iclass 10, count 0 2006.285.12:16:37.20#ibcon#read 5, iclass 10, count 0 2006.285.12:16:37.20#ibcon#about to read 6, iclass 10, count 0 2006.285.12:16:37.20#ibcon#read 6, iclass 10, count 0 2006.285.12:16:37.20#ibcon#end of sib2, iclass 10, count 0 2006.285.12:16:37.20#ibcon#*after write, iclass 10, count 0 2006.285.12:16:37.20#ibcon#*before return 0, iclass 10, count 0 2006.285.12:16:37.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:16:37.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:16:37.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.12:16:37.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.12:16:37.20$vck44/valo=4,624.99 2006.285.12:16:37.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.12:16:37.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.12:16:37.20#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:37.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:16:37.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:16:37.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:16:37.20#ibcon#enter wrdev, iclass 12, count 0 2006.285.12:16:37.20#ibcon#first serial, iclass 12, count 0 2006.285.12:16:37.20#ibcon#enter sib2, iclass 12, count 0 2006.285.12:16:37.20#ibcon#flushed, iclass 12, count 0 2006.285.12:16:37.20#ibcon#about to write, iclass 12, count 0 2006.285.12:16:37.20#ibcon#wrote, iclass 12, count 0 2006.285.12:16:37.20#ibcon#about to read 3, iclass 12, count 0 2006.285.12:16:37.22#ibcon#read 3, iclass 12, count 0 2006.285.12:16:37.22#ibcon#about to read 4, iclass 12, count 0 2006.285.12:16:37.22#ibcon#read 4, iclass 12, count 0 2006.285.12:16:37.22#ibcon#about to read 5, iclass 12, count 0 2006.285.12:16:37.22#ibcon#read 5, iclass 12, count 0 2006.285.12:16:37.22#ibcon#about to read 6, iclass 12, count 0 2006.285.12:16:37.22#ibcon#read 6, iclass 12, count 0 2006.285.12:16:37.22#ibcon#end of sib2, iclass 12, count 0 2006.285.12:16:37.22#ibcon#*mode == 0, iclass 12, count 0 2006.285.12:16:37.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.12:16:37.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.12:16:37.22#ibcon#*before write, iclass 12, count 0 2006.285.12:16:37.22#ibcon#enter sib2, iclass 12, count 0 2006.285.12:16:37.22#ibcon#flushed, iclass 12, count 0 2006.285.12:16:37.22#ibcon#about to write, iclass 12, count 0 2006.285.12:16:37.22#ibcon#wrote, iclass 12, count 0 2006.285.12:16:37.22#ibcon#about to read 3, iclass 12, count 0 2006.285.12:16:37.26#ibcon#read 3, iclass 12, count 0 2006.285.12:16:37.26#ibcon#about to read 4, iclass 12, count 0 2006.285.12:16:37.26#ibcon#read 4, iclass 12, count 0 2006.285.12:16:37.26#ibcon#about to read 5, iclass 12, count 0 2006.285.12:16:37.26#ibcon#read 5, iclass 12, count 0 2006.285.12:16:37.26#ibcon#about to read 6, iclass 12, count 0 2006.285.12:16:37.26#ibcon#read 6, iclass 12, count 0 2006.285.12:16:37.26#ibcon#end of sib2, iclass 12, count 0 2006.285.12:16:37.26#ibcon#*after write, iclass 12, count 0 2006.285.12:16:37.26#ibcon#*before return 0, iclass 12, count 0 2006.285.12:16:37.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:16:37.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:16:37.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.12:16:37.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.12:16:37.26$vck44/va=4,6 2006.285.12:16:37.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.12:16:37.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.12:16:37.26#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:37.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:16:37.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:16:37.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:16:37.32#ibcon#enter wrdev, iclass 14, count 2 2006.285.12:16:37.32#ibcon#first serial, iclass 14, count 2 2006.285.12:16:37.32#ibcon#enter sib2, iclass 14, count 2 2006.285.12:16:37.32#ibcon#flushed, iclass 14, count 2 2006.285.12:16:37.32#ibcon#about to write, iclass 14, count 2 2006.285.12:16:37.32#ibcon#wrote, iclass 14, count 2 2006.285.12:16:37.32#ibcon#about to read 3, iclass 14, count 2 2006.285.12:16:37.34#ibcon#read 3, iclass 14, count 2 2006.285.12:16:37.34#ibcon#about to read 4, iclass 14, count 2 2006.285.12:16:37.34#ibcon#read 4, iclass 14, count 2 2006.285.12:16:37.34#ibcon#about to read 5, iclass 14, count 2 2006.285.12:16:37.34#ibcon#read 5, iclass 14, count 2 2006.285.12:16:37.34#ibcon#about to read 6, iclass 14, count 2 2006.285.12:16:37.34#ibcon#read 6, iclass 14, count 2 2006.285.12:16:37.34#ibcon#end of sib2, iclass 14, count 2 2006.285.12:16:37.34#ibcon#*mode == 0, iclass 14, count 2 2006.285.12:16:37.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.12:16:37.34#ibcon#[25=AT04-06\r\n] 2006.285.12:16:37.34#ibcon#*before write, iclass 14, count 2 2006.285.12:16:37.34#ibcon#enter sib2, iclass 14, count 2 2006.285.12:16:37.34#ibcon#flushed, iclass 14, count 2 2006.285.12:16:37.34#ibcon#about to write, iclass 14, count 2 2006.285.12:16:37.34#ibcon#wrote, iclass 14, count 2 2006.285.12:16:37.34#ibcon#about to read 3, iclass 14, count 2 2006.285.12:16:37.37#ibcon#read 3, iclass 14, count 2 2006.285.12:16:37.37#ibcon#about to read 4, iclass 14, count 2 2006.285.12:16:37.37#ibcon#read 4, iclass 14, count 2 2006.285.12:16:37.37#ibcon#about to read 5, iclass 14, count 2 2006.285.12:16:37.37#ibcon#read 5, iclass 14, count 2 2006.285.12:16:37.37#ibcon#about to read 6, iclass 14, count 2 2006.285.12:16:37.37#ibcon#read 6, iclass 14, count 2 2006.285.12:16:37.37#ibcon#end of sib2, iclass 14, count 2 2006.285.12:16:37.37#ibcon#*after write, iclass 14, count 2 2006.285.12:16:37.37#ibcon#*before return 0, iclass 14, count 2 2006.285.12:16:37.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:16:37.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:16:37.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.12:16:37.37#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:37.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:16:37.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:16:37.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:16:37.49#ibcon#enter wrdev, iclass 14, count 0 2006.285.12:16:37.49#ibcon#first serial, iclass 14, count 0 2006.285.12:16:37.49#ibcon#enter sib2, iclass 14, count 0 2006.285.12:16:37.49#ibcon#flushed, iclass 14, count 0 2006.285.12:16:37.49#ibcon#about to write, iclass 14, count 0 2006.285.12:16:37.49#ibcon#wrote, iclass 14, count 0 2006.285.12:16:37.49#ibcon#about to read 3, iclass 14, count 0 2006.285.12:16:37.51#ibcon#read 3, iclass 14, count 0 2006.285.12:16:37.51#ibcon#about to read 4, iclass 14, count 0 2006.285.12:16:37.51#ibcon#read 4, iclass 14, count 0 2006.285.12:16:37.51#ibcon#about to read 5, iclass 14, count 0 2006.285.12:16:37.51#ibcon#read 5, iclass 14, count 0 2006.285.12:16:37.51#ibcon#about to read 6, iclass 14, count 0 2006.285.12:16:37.51#ibcon#read 6, iclass 14, count 0 2006.285.12:16:37.51#ibcon#end of sib2, iclass 14, count 0 2006.285.12:16:37.51#ibcon#*mode == 0, iclass 14, count 0 2006.285.12:16:37.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.12:16:37.51#ibcon#[25=USB\r\n] 2006.285.12:16:37.51#ibcon#*before write, iclass 14, count 0 2006.285.12:16:37.51#ibcon#enter sib2, iclass 14, count 0 2006.285.12:16:37.51#ibcon#flushed, iclass 14, count 0 2006.285.12:16:37.51#ibcon#about to write, iclass 14, count 0 2006.285.12:16:37.51#ibcon#wrote, iclass 14, count 0 2006.285.12:16:37.51#ibcon#about to read 3, iclass 14, count 0 2006.285.12:16:37.54#ibcon#read 3, iclass 14, count 0 2006.285.12:16:37.54#ibcon#about to read 4, iclass 14, count 0 2006.285.12:16:37.54#ibcon#read 4, iclass 14, count 0 2006.285.12:16:37.54#ibcon#about to read 5, iclass 14, count 0 2006.285.12:16:37.54#ibcon#read 5, iclass 14, count 0 2006.285.12:16:37.54#ibcon#about to read 6, iclass 14, count 0 2006.285.12:16:37.54#ibcon#read 6, iclass 14, count 0 2006.285.12:16:37.54#ibcon#end of sib2, iclass 14, count 0 2006.285.12:16:37.54#ibcon#*after write, iclass 14, count 0 2006.285.12:16:37.54#ibcon#*before return 0, iclass 14, count 0 2006.285.12:16:37.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:16:37.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:16:37.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.12:16:37.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.12:16:37.54$vck44/valo=5,734.99 2006.285.12:16:37.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.12:16:37.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.12:16:37.54#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:37.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:16:37.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:16:37.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:16:37.54#ibcon#enter wrdev, iclass 16, count 0 2006.285.12:16:37.54#ibcon#first serial, iclass 16, count 0 2006.285.12:16:37.54#ibcon#enter sib2, iclass 16, count 0 2006.285.12:16:37.54#ibcon#flushed, iclass 16, count 0 2006.285.12:16:37.54#ibcon#about to write, iclass 16, count 0 2006.285.12:16:37.54#ibcon#wrote, iclass 16, count 0 2006.285.12:16:37.54#ibcon#about to read 3, iclass 16, count 0 2006.285.12:16:37.56#ibcon#read 3, iclass 16, count 0 2006.285.12:16:37.56#ibcon#about to read 4, iclass 16, count 0 2006.285.12:16:37.56#ibcon#read 4, iclass 16, count 0 2006.285.12:16:37.56#ibcon#about to read 5, iclass 16, count 0 2006.285.12:16:37.56#ibcon#read 5, iclass 16, count 0 2006.285.12:16:37.56#ibcon#about to read 6, iclass 16, count 0 2006.285.12:16:37.56#ibcon#read 6, iclass 16, count 0 2006.285.12:16:37.56#ibcon#end of sib2, iclass 16, count 0 2006.285.12:16:37.56#ibcon#*mode == 0, iclass 16, count 0 2006.285.12:16:37.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.12:16:37.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.12:16:37.56#ibcon#*before write, iclass 16, count 0 2006.285.12:16:37.56#ibcon#enter sib2, iclass 16, count 0 2006.285.12:16:37.56#ibcon#flushed, iclass 16, count 0 2006.285.12:16:37.56#ibcon#about to write, iclass 16, count 0 2006.285.12:16:37.56#ibcon#wrote, iclass 16, count 0 2006.285.12:16:37.56#ibcon#about to read 3, iclass 16, count 0 2006.285.12:16:37.60#ibcon#read 3, iclass 16, count 0 2006.285.12:16:37.60#ibcon#about to read 4, iclass 16, count 0 2006.285.12:16:37.60#ibcon#read 4, iclass 16, count 0 2006.285.12:16:37.60#ibcon#about to read 5, iclass 16, count 0 2006.285.12:16:37.60#ibcon#read 5, iclass 16, count 0 2006.285.12:16:37.60#ibcon#about to read 6, iclass 16, count 0 2006.285.12:16:37.60#ibcon#read 6, iclass 16, count 0 2006.285.12:16:37.60#ibcon#end of sib2, iclass 16, count 0 2006.285.12:16:37.60#ibcon#*after write, iclass 16, count 0 2006.285.12:16:37.60#ibcon#*before return 0, iclass 16, count 0 2006.285.12:16:37.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:16:37.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:16:37.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.12:16:37.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.12:16:37.60$vck44/va=5,3 2006.285.12:16:37.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.12:16:37.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.12:16:37.60#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:37.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:16:37.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:16:37.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:16:37.66#ibcon#enter wrdev, iclass 18, count 2 2006.285.12:16:37.66#ibcon#first serial, iclass 18, count 2 2006.285.12:16:37.66#ibcon#enter sib2, iclass 18, count 2 2006.285.12:16:37.66#ibcon#flushed, iclass 18, count 2 2006.285.12:16:37.66#ibcon#about to write, iclass 18, count 2 2006.285.12:16:37.66#ibcon#wrote, iclass 18, count 2 2006.285.12:16:37.66#ibcon#about to read 3, iclass 18, count 2 2006.285.12:16:37.68#ibcon#read 3, iclass 18, count 2 2006.285.12:16:37.68#ibcon#about to read 4, iclass 18, count 2 2006.285.12:16:37.68#ibcon#read 4, iclass 18, count 2 2006.285.12:16:37.68#ibcon#about to read 5, iclass 18, count 2 2006.285.12:16:37.68#ibcon#read 5, iclass 18, count 2 2006.285.12:16:37.68#ibcon#about to read 6, iclass 18, count 2 2006.285.12:16:37.68#ibcon#read 6, iclass 18, count 2 2006.285.12:16:37.68#ibcon#end of sib2, iclass 18, count 2 2006.285.12:16:37.68#ibcon#*mode == 0, iclass 18, count 2 2006.285.12:16:37.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.12:16:37.68#ibcon#[25=AT05-03\r\n] 2006.285.12:16:37.68#ibcon#*before write, iclass 18, count 2 2006.285.12:16:37.68#ibcon#enter sib2, iclass 18, count 2 2006.285.12:16:37.68#ibcon#flushed, iclass 18, count 2 2006.285.12:16:37.68#ibcon#about to write, iclass 18, count 2 2006.285.12:16:37.68#ibcon#wrote, iclass 18, count 2 2006.285.12:16:37.68#ibcon#about to read 3, iclass 18, count 2 2006.285.12:16:37.71#ibcon#read 3, iclass 18, count 2 2006.285.12:16:37.71#ibcon#about to read 4, iclass 18, count 2 2006.285.12:16:37.71#ibcon#read 4, iclass 18, count 2 2006.285.12:16:37.71#ibcon#about to read 5, iclass 18, count 2 2006.285.12:16:37.71#ibcon#read 5, iclass 18, count 2 2006.285.12:16:37.71#ibcon#about to read 6, iclass 18, count 2 2006.285.12:16:37.71#ibcon#read 6, iclass 18, count 2 2006.285.12:16:37.71#ibcon#end of sib2, iclass 18, count 2 2006.285.12:16:37.71#ibcon#*after write, iclass 18, count 2 2006.285.12:16:37.71#ibcon#*before return 0, iclass 18, count 2 2006.285.12:16:37.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:16:37.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:16:37.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.12:16:37.71#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:37.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:16:37.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:16:37.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:16:37.83#ibcon#enter wrdev, iclass 18, count 0 2006.285.12:16:37.83#ibcon#first serial, iclass 18, count 0 2006.285.12:16:37.83#ibcon#enter sib2, iclass 18, count 0 2006.285.12:16:37.83#ibcon#flushed, iclass 18, count 0 2006.285.12:16:37.83#ibcon#about to write, iclass 18, count 0 2006.285.12:16:37.83#ibcon#wrote, iclass 18, count 0 2006.285.12:16:37.83#ibcon#about to read 3, iclass 18, count 0 2006.285.12:16:37.85#ibcon#read 3, iclass 18, count 0 2006.285.12:16:37.85#ibcon#about to read 4, iclass 18, count 0 2006.285.12:16:37.85#ibcon#read 4, iclass 18, count 0 2006.285.12:16:37.85#ibcon#about to read 5, iclass 18, count 0 2006.285.12:16:37.85#ibcon#read 5, iclass 18, count 0 2006.285.12:16:37.85#ibcon#about to read 6, iclass 18, count 0 2006.285.12:16:37.85#ibcon#read 6, iclass 18, count 0 2006.285.12:16:37.85#ibcon#end of sib2, iclass 18, count 0 2006.285.12:16:37.85#ibcon#*mode == 0, iclass 18, count 0 2006.285.12:16:37.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.12:16:37.85#ibcon#[25=USB\r\n] 2006.285.12:16:37.85#ibcon#*before write, iclass 18, count 0 2006.285.12:16:37.85#ibcon#enter sib2, iclass 18, count 0 2006.285.12:16:37.85#ibcon#flushed, iclass 18, count 0 2006.285.12:16:37.85#ibcon#about to write, iclass 18, count 0 2006.285.12:16:37.85#ibcon#wrote, iclass 18, count 0 2006.285.12:16:37.85#ibcon#about to read 3, iclass 18, count 0 2006.285.12:16:37.88#ibcon#read 3, iclass 18, count 0 2006.285.12:16:37.88#ibcon#about to read 4, iclass 18, count 0 2006.285.12:16:37.88#ibcon#read 4, iclass 18, count 0 2006.285.12:16:37.88#ibcon#about to read 5, iclass 18, count 0 2006.285.12:16:37.88#ibcon#read 5, iclass 18, count 0 2006.285.12:16:37.88#ibcon#about to read 6, iclass 18, count 0 2006.285.12:16:37.88#ibcon#read 6, iclass 18, count 0 2006.285.12:16:37.88#ibcon#end of sib2, iclass 18, count 0 2006.285.12:16:37.88#ibcon#*after write, iclass 18, count 0 2006.285.12:16:37.88#ibcon#*before return 0, iclass 18, count 0 2006.285.12:16:37.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:16:37.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:16:37.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.12:16:37.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.12:16:37.88$vck44/valo=6,814.99 2006.285.12:16:37.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.12:16:37.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.12:16:37.88#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:37.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:16:37.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:16:37.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:16:37.88#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:16:37.88#ibcon#first serial, iclass 20, count 0 2006.285.12:16:37.88#ibcon#enter sib2, iclass 20, count 0 2006.285.12:16:37.88#ibcon#flushed, iclass 20, count 0 2006.285.12:16:37.88#ibcon#about to write, iclass 20, count 0 2006.285.12:16:37.88#ibcon#wrote, iclass 20, count 0 2006.285.12:16:37.88#ibcon#about to read 3, iclass 20, count 0 2006.285.12:16:37.90#ibcon#read 3, iclass 20, count 0 2006.285.12:16:37.90#ibcon#about to read 4, iclass 20, count 0 2006.285.12:16:37.90#ibcon#read 4, iclass 20, count 0 2006.285.12:16:37.90#ibcon#about to read 5, iclass 20, count 0 2006.285.12:16:37.90#ibcon#read 5, iclass 20, count 0 2006.285.12:16:37.90#ibcon#about to read 6, iclass 20, count 0 2006.285.12:16:37.90#ibcon#read 6, iclass 20, count 0 2006.285.12:16:37.90#ibcon#end of sib2, iclass 20, count 0 2006.285.12:16:37.90#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:16:37.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:16:37.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.12:16:37.90#ibcon#*before write, iclass 20, count 0 2006.285.12:16:37.90#ibcon#enter sib2, iclass 20, count 0 2006.285.12:16:37.90#ibcon#flushed, iclass 20, count 0 2006.285.12:16:37.90#ibcon#about to write, iclass 20, count 0 2006.285.12:16:37.90#ibcon#wrote, iclass 20, count 0 2006.285.12:16:37.90#ibcon#about to read 3, iclass 20, count 0 2006.285.12:16:37.94#ibcon#read 3, iclass 20, count 0 2006.285.12:16:37.94#ibcon#about to read 4, iclass 20, count 0 2006.285.12:16:37.94#ibcon#read 4, iclass 20, count 0 2006.285.12:16:37.94#ibcon#about to read 5, iclass 20, count 0 2006.285.12:16:37.94#ibcon#read 5, iclass 20, count 0 2006.285.12:16:37.94#ibcon#about to read 6, iclass 20, count 0 2006.285.12:16:37.94#ibcon#read 6, iclass 20, count 0 2006.285.12:16:37.94#ibcon#end of sib2, iclass 20, count 0 2006.285.12:16:37.94#ibcon#*after write, iclass 20, count 0 2006.285.12:16:37.94#ibcon#*before return 0, iclass 20, count 0 2006.285.12:16:37.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:16:37.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:16:37.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:16:37.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:16:37.94$vck44/va=6,4 2006.285.12:16:37.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.12:16:37.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.12:16:37.94#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:37.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:16:38.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:16:38.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:16:38.00#ibcon#enter wrdev, iclass 22, count 2 2006.285.12:16:38.00#ibcon#first serial, iclass 22, count 2 2006.285.12:16:38.00#ibcon#enter sib2, iclass 22, count 2 2006.285.12:16:38.00#ibcon#flushed, iclass 22, count 2 2006.285.12:16:38.00#ibcon#about to write, iclass 22, count 2 2006.285.12:16:38.00#ibcon#wrote, iclass 22, count 2 2006.285.12:16:38.00#ibcon#about to read 3, iclass 22, count 2 2006.285.12:16:38.02#ibcon#read 3, iclass 22, count 2 2006.285.12:16:38.02#ibcon#about to read 4, iclass 22, count 2 2006.285.12:16:38.02#ibcon#read 4, iclass 22, count 2 2006.285.12:16:38.02#ibcon#about to read 5, iclass 22, count 2 2006.285.12:16:38.02#ibcon#read 5, iclass 22, count 2 2006.285.12:16:38.02#ibcon#about to read 6, iclass 22, count 2 2006.285.12:16:38.02#ibcon#read 6, iclass 22, count 2 2006.285.12:16:38.02#ibcon#end of sib2, iclass 22, count 2 2006.285.12:16:38.02#ibcon#*mode == 0, iclass 22, count 2 2006.285.12:16:38.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.12:16:38.02#ibcon#[25=AT06-04\r\n] 2006.285.12:16:38.02#ibcon#*before write, iclass 22, count 2 2006.285.12:16:38.02#ibcon#enter sib2, iclass 22, count 2 2006.285.12:16:38.02#ibcon#flushed, iclass 22, count 2 2006.285.12:16:38.02#ibcon#about to write, iclass 22, count 2 2006.285.12:16:38.02#ibcon#wrote, iclass 22, count 2 2006.285.12:16:38.02#ibcon#about to read 3, iclass 22, count 2 2006.285.12:16:38.05#ibcon#read 3, iclass 22, count 2 2006.285.12:16:38.05#ibcon#about to read 4, iclass 22, count 2 2006.285.12:16:38.05#ibcon#read 4, iclass 22, count 2 2006.285.12:16:38.05#ibcon#about to read 5, iclass 22, count 2 2006.285.12:16:38.05#ibcon#read 5, iclass 22, count 2 2006.285.12:16:38.05#ibcon#about to read 6, iclass 22, count 2 2006.285.12:16:38.05#ibcon#read 6, iclass 22, count 2 2006.285.12:16:38.05#ibcon#end of sib2, iclass 22, count 2 2006.285.12:16:38.05#ibcon#*after write, iclass 22, count 2 2006.285.12:16:38.05#ibcon#*before return 0, iclass 22, count 2 2006.285.12:16:38.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:16:38.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:16:38.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.12:16:38.05#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:38.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:16:38.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:16:38.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:16:38.17#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:16:38.17#ibcon#first serial, iclass 22, count 0 2006.285.12:16:38.17#ibcon#enter sib2, iclass 22, count 0 2006.285.12:16:38.17#ibcon#flushed, iclass 22, count 0 2006.285.12:16:38.17#ibcon#about to write, iclass 22, count 0 2006.285.12:16:38.17#ibcon#wrote, iclass 22, count 0 2006.285.12:16:38.17#ibcon#about to read 3, iclass 22, count 0 2006.285.12:16:38.19#ibcon#read 3, iclass 22, count 0 2006.285.12:16:38.19#ibcon#about to read 4, iclass 22, count 0 2006.285.12:16:38.19#ibcon#read 4, iclass 22, count 0 2006.285.12:16:38.19#ibcon#about to read 5, iclass 22, count 0 2006.285.12:16:38.19#ibcon#read 5, iclass 22, count 0 2006.285.12:16:38.19#ibcon#about to read 6, iclass 22, count 0 2006.285.12:16:38.19#ibcon#read 6, iclass 22, count 0 2006.285.12:16:38.19#ibcon#end of sib2, iclass 22, count 0 2006.285.12:16:38.19#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:16:38.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:16:38.19#ibcon#[25=USB\r\n] 2006.285.12:16:38.19#ibcon#*before write, iclass 22, count 0 2006.285.12:16:38.19#ibcon#enter sib2, iclass 22, count 0 2006.285.12:16:38.19#ibcon#flushed, iclass 22, count 0 2006.285.12:16:38.19#ibcon#about to write, iclass 22, count 0 2006.285.12:16:38.19#ibcon#wrote, iclass 22, count 0 2006.285.12:16:38.19#ibcon#about to read 3, iclass 22, count 0 2006.285.12:16:38.22#ibcon#read 3, iclass 22, count 0 2006.285.12:16:38.22#ibcon#about to read 4, iclass 22, count 0 2006.285.12:16:38.22#ibcon#read 4, iclass 22, count 0 2006.285.12:16:38.22#ibcon#about to read 5, iclass 22, count 0 2006.285.12:16:38.22#ibcon#read 5, iclass 22, count 0 2006.285.12:16:38.22#ibcon#about to read 6, iclass 22, count 0 2006.285.12:16:38.22#ibcon#read 6, iclass 22, count 0 2006.285.12:16:38.22#ibcon#end of sib2, iclass 22, count 0 2006.285.12:16:38.22#ibcon#*after write, iclass 22, count 0 2006.285.12:16:38.22#ibcon#*before return 0, iclass 22, count 0 2006.285.12:16:38.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:16:38.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:16:38.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:16:38.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:16:38.22$vck44/valo=7,864.99 2006.285.12:16:38.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.12:16:38.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.12:16:38.22#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:38.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:16:38.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:16:38.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:16:38.22#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:16:38.22#ibcon#first serial, iclass 24, count 0 2006.285.12:16:38.22#ibcon#enter sib2, iclass 24, count 0 2006.285.12:16:38.22#ibcon#flushed, iclass 24, count 0 2006.285.12:16:38.22#ibcon#about to write, iclass 24, count 0 2006.285.12:16:38.22#ibcon#wrote, iclass 24, count 0 2006.285.12:16:38.22#ibcon#about to read 3, iclass 24, count 0 2006.285.12:16:38.24#ibcon#read 3, iclass 24, count 0 2006.285.12:16:38.24#ibcon#about to read 4, iclass 24, count 0 2006.285.12:16:38.24#ibcon#read 4, iclass 24, count 0 2006.285.12:16:38.24#ibcon#about to read 5, iclass 24, count 0 2006.285.12:16:38.24#ibcon#read 5, iclass 24, count 0 2006.285.12:16:38.24#ibcon#about to read 6, iclass 24, count 0 2006.285.12:16:38.24#ibcon#read 6, iclass 24, count 0 2006.285.12:16:38.24#ibcon#end of sib2, iclass 24, count 0 2006.285.12:16:38.24#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:16:38.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:16:38.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.12:16:38.24#ibcon#*before write, iclass 24, count 0 2006.285.12:16:38.24#ibcon#enter sib2, iclass 24, count 0 2006.285.12:16:38.24#ibcon#flushed, iclass 24, count 0 2006.285.12:16:38.24#ibcon#about to write, iclass 24, count 0 2006.285.12:16:38.24#ibcon#wrote, iclass 24, count 0 2006.285.12:16:38.24#ibcon#about to read 3, iclass 24, count 0 2006.285.12:16:38.28#ibcon#read 3, iclass 24, count 0 2006.285.12:16:38.28#ibcon#about to read 4, iclass 24, count 0 2006.285.12:16:38.28#ibcon#read 4, iclass 24, count 0 2006.285.12:16:38.28#ibcon#about to read 5, iclass 24, count 0 2006.285.12:16:38.28#ibcon#read 5, iclass 24, count 0 2006.285.12:16:38.28#ibcon#about to read 6, iclass 24, count 0 2006.285.12:16:38.28#ibcon#read 6, iclass 24, count 0 2006.285.12:16:38.28#ibcon#end of sib2, iclass 24, count 0 2006.285.12:16:38.28#ibcon#*after write, iclass 24, count 0 2006.285.12:16:38.28#ibcon#*before return 0, iclass 24, count 0 2006.285.12:16:38.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:16:38.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:16:38.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:16:38.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:16:38.28$vck44/va=7,4 2006.285.12:16:38.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.12:16:38.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.12:16:38.28#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:38.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:16:38.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:16:38.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:16:38.34#ibcon#enter wrdev, iclass 26, count 2 2006.285.12:16:38.34#ibcon#first serial, iclass 26, count 2 2006.285.12:16:38.34#ibcon#enter sib2, iclass 26, count 2 2006.285.12:16:38.34#ibcon#flushed, iclass 26, count 2 2006.285.12:16:38.34#ibcon#about to write, iclass 26, count 2 2006.285.12:16:38.34#ibcon#wrote, iclass 26, count 2 2006.285.12:16:38.34#ibcon#about to read 3, iclass 26, count 2 2006.285.12:16:38.36#ibcon#read 3, iclass 26, count 2 2006.285.12:16:38.36#ibcon#about to read 4, iclass 26, count 2 2006.285.12:16:38.36#ibcon#read 4, iclass 26, count 2 2006.285.12:16:38.36#ibcon#about to read 5, iclass 26, count 2 2006.285.12:16:38.36#ibcon#read 5, iclass 26, count 2 2006.285.12:16:38.36#ibcon#about to read 6, iclass 26, count 2 2006.285.12:16:38.36#ibcon#read 6, iclass 26, count 2 2006.285.12:16:38.36#ibcon#end of sib2, iclass 26, count 2 2006.285.12:16:38.36#ibcon#*mode == 0, iclass 26, count 2 2006.285.12:16:38.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.12:16:38.36#ibcon#[25=AT07-04\r\n] 2006.285.12:16:38.36#ibcon#*before write, iclass 26, count 2 2006.285.12:16:38.36#ibcon#enter sib2, iclass 26, count 2 2006.285.12:16:38.36#ibcon#flushed, iclass 26, count 2 2006.285.12:16:38.36#ibcon#about to write, iclass 26, count 2 2006.285.12:16:38.36#ibcon#wrote, iclass 26, count 2 2006.285.12:16:38.36#ibcon#about to read 3, iclass 26, count 2 2006.285.12:16:38.39#ibcon#read 3, iclass 26, count 2 2006.285.12:16:38.39#ibcon#about to read 4, iclass 26, count 2 2006.285.12:16:38.39#ibcon#read 4, iclass 26, count 2 2006.285.12:16:38.39#ibcon#about to read 5, iclass 26, count 2 2006.285.12:16:38.39#ibcon#read 5, iclass 26, count 2 2006.285.12:16:38.39#ibcon#about to read 6, iclass 26, count 2 2006.285.12:16:38.39#ibcon#read 6, iclass 26, count 2 2006.285.12:16:38.39#ibcon#end of sib2, iclass 26, count 2 2006.285.12:16:38.39#ibcon#*after write, iclass 26, count 2 2006.285.12:16:38.39#ibcon#*before return 0, iclass 26, count 2 2006.285.12:16:38.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:16:38.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:16:38.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.12:16:38.39#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:38.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:16:38.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:16:38.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:16:38.51#ibcon#enter wrdev, iclass 26, count 0 2006.285.12:16:38.51#ibcon#first serial, iclass 26, count 0 2006.285.12:16:38.51#ibcon#enter sib2, iclass 26, count 0 2006.285.12:16:38.51#ibcon#flushed, iclass 26, count 0 2006.285.12:16:38.51#ibcon#about to write, iclass 26, count 0 2006.285.12:16:38.51#ibcon#wrote, iclass 26, count 0 2006.285.12:16:38.51#ibcon#about to read 3, iclass 26, count 0 2006.285.12:16:38.53#ibcon#read 3, iclass 26, count 0 2006.285.12:16:38.53#ibcon#about to read 4, iclass 26, count 0 2006.285.12:16:38.53#ibcon#read 4, iclass 26, count 0 2006.285.12:16:38.53#ibcon#about to read 5, iclass 26, count 0 2006.285.12:16:38.53#ibcon#read 5, iclass 26, count 0 2006.285.12:16:38.53#ibcon#about to read 6, iclass 26, count 0 2006.285.12:16:38.53#ibcon#read 6, iclass 26, count 0 2006.285.12:16:38.53#ibcon#end of sib2, iclass 26, count 0 2006.285.12:16:38.53#ibcon#*mode == 0, iclass 26, count 0 2006.285.12:16:38.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.12:16:38.53#ibcon#[25=USB\r\n] 2006.285.12:16:38.53#ibcon#*before write, iclass 26, count 0 2006.285.12:16:38.53#ibcon#enter sib2, iclass 26, count 0 2006.285.12:16:38.53#ibcon#flushed, iclass 26, count 0 2006.285.12:16:38.53#ibcon#about to write, iclass 26, count 0 2006.285.12:16:38.53#ibcon#wrote, iclass 26, count 0 2006.285.12:16:38.53#ibcon#about to read 3, iclass 26, count 0 2006.285.12:16:38.56#ibcon#read 3, iclass 26, count 0 2006.285.12:16:38.56#ibcon#about to read 4, iclass 26, count 0 2006.285.12:16:38.56#ibcon#read 4, iclass 26, count 0 2006.285.12:16:38.56#ibcon#about to read 5, iclass 26, count 0 2006.285.12:16:38.56#ibcon#read 5, iclass 26, count 0 2006.285.12:16:38.56#ibcon#about to read 6, iclass 26, count 0 2006.285.12:16:38.56#ibcon#read 6, iclass 26, count 0 2006.285.12:16:38.56#ibcon#end of sib2, iclass 26, count 0 2006.285.12:16:38.56#ibcon#*after write, iclass 26, count 0 2006.285.12:16:38.56#ibcon#*before return 0, iclass 26, count 0 2006.285.12:16:38.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:16:38.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:16:38.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.12:16:38.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.12:16:38.56$vck44/valo=8,884.99 2006.285.12:16:38.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.12:16:38.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.12:16:38.56#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:38.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:16:38.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:16:38.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:16:38.56#ibcon#enter wrdev, iclass 28, count 0 2006.285.12:16:38.56#ibcon#first serial, iclass 28, count 0 2006.285.12:16:38.56#ibcon#enter sib2, iclass 28, count 0 2006.285.12:16:38.56#ibcon#flushed, iclass 28, count 0 2006.285.12:16:38.56#ibcon#about to write, iclass 28, count 0 2006.285.12:16:38.56#ibcon#wrote, iclass 28, count 0 2006.285.12:16:38.56#ibcon#about to read 3, iclass 28, count 0 2006.285.12:16:38.58#ibcon#read 3, iclass 28, count 0 2006.285.12:16:38.58#ibcon#about to read 4, iclass 28, count 0 2006.285.12:16:38.58#ibcon#read 4, iclass 28, count 0 2006.285.12:16:38.58#ibcon#about to read 5, iclass 28, count 0 2006.285.12:16:38.58#ibcon#read 5, iclass 28, count 0 2006.285.12:16:38.58#ibcon#about to read 6, iclass 28, count 0 2006.285.12:16:38.58#ibcon#read 6, iclass 28, count 0 2006.285.12:16:38.58#ibcon#end of sib2, iclass 28, count 0 2006.285.12:16:38.58#ibcon#*mode == 0, iclass 28, count 0 2006.285.12:16:38.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.12:16:38.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.12:16:38.58#ibcon#*before write, iclass 28, count 0 2006.285.12:16:38.58#ibcon#enter sib2, iclass 28, count 0 2006.285.12:16:38.58#ibcon#flushed, iclass 28, count 0 2006.285.12:16:38.58#ibcon#about to write, iclass 28, count 0 2006.285.12:16:38.58#ibcon#wrote, iclass 28, count 0 2006.285.12:16:38.58#ibcon#about to read 3, iclass 28, count 0 2006.285.12:16:38.62#ibcon#read 3, iclass 28, count 0 2006.285.12:16:38.62#ibcon#about to read 4, iclass 28, count 0 2006.285.12:16:38.62#ibcon#read 4, iclass 28, count 0 2006.285.12:16:38.62#ibcon#about to read 5, iclass 28, count 0 2006.285.12:16:38.62#ibcon#read 5, iclass 28, count 0 2006.285.12:16:38.62#ibcon#about to read 6, iclass 28, count 0 2006.285.12:16:38.62#ibcon#read 6, iclass 28, count 0 2006.285.12:16:38.62#ibcon#end of sib2, iclass 28, count 0 2006.285.12:16:38.62#ibcon#*after write, iclass 28, count 0 2006.285.12:16:38.62#ibcon#*before return 0, iclass 28, count 0 2006.285.12:16:38.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:16:38.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:16:38.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.12:16:38.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.12:16:38.62$vck44/va=8,3 2006.285.12:16:38.62#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.12:16:38.62#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.12:16:38.62#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:38.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:16:38.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:16:38.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:16:38.68#ibcon#enter wrdev, iclass 30, count 2 2006.285.12:16:38.68#ibcon#first serial, iclass 30, count 2 2006.285.12:16:38.68#ibcon#enter sib2, iclass 30, count 2 2006.285.12:16:38.68#ibcon#flushed, iclass 30, count 2 2006.285.12:16:38.68#ibcon#about to write, iclass 30, count 2 2006.285.12:16:38.68#ibcon#wrote, iclass 30, count 2 2006.285.12:16:38.68#ibcon#about to read 3, iclass 30, count 2 2006.285.12:16:38.70#ibcon#read 3, iclass 30, count 2 2006.285.12:16:38.70#ibcon#about to read 4, iclass 30, count 2 2006.285.12:16:38.70#ibcon#read 4, iclass 30, count 2 2006.285.12:16:38.70#ibcon#about to read 5, iclass 30, count 2 2006.285.12:16:38.70#ibcon#read 5, iclass 30, count 2 2006.285.12:16:38.70#ibcon#about to read 6, iclass 30, count 2 2006.285.12:16:38.70#ibcon#read 6, iclass 30, count 2 2006.285.12:16:38.70#ibcon#end of sib2, iclass 30, count 2 2006.285.12:16:38.70#ibcon#*mode == 0, iclass 30, count 2 2006.285.12:16:38.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.12:16:38.70#ibcon#[25=AT08-03\r\n] 2006.285.12:16:38.70#ibcon#*before write, iclass 30, count 2 2006.285.12:16:38.70#ibcon#enter sib2, iclass 30, count 2 2006.285.12:16:38.70#ibcon#flushed, iclass 30, count 2 2006.285.12:16:38.70#ibcon#about to write, iclass 30, count 2 2006.285.12:16:38.70#ibcon#wrote, iclass 30, count 2 2006.285.12:16:38.70#ibcon#about to read 3, iclass 30, count 2 2006.285.12:16:38.73#ibcon#read 3, iclass 30, count 2 2006.285.12:16:38.73#ibcon#about to read 4, iclass 30, count 2 2006.285.12:16:38.73#ibcon#read 4, iclass 30, count 2 2006.285.12:16:38.73#ibcon#about to read 5, iclass 30, count 2 2006.285.12:16:38.73#ibcon#read 5, iclass 30, count 2 2006.285.12:16:38.73#ibcon#about to read 6, iclass 30, count 2 2006.285.12:16:38.73#ibcon#read 6, iclass 30, count 2 2006.285.12:16:38.73#ibcon#end of sib2, iclass 30, count 2 2006.285.12:16:38.73#ibcon#*after write, iclass 30, count 2 2006.285.12:16:38.73#ibcon#*before return 0, iclass 30, count 2 2006.285.12:16:38.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:16:38.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:16:38.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.12:16:38.73#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:38.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:16:38.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:16:38.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:16:38.85#ibcon#enter wrdev, iclass 30, count 0 2006.285.12:16:38.85#ibcon#first serial, iclass 30, count 0 2006.285.12:16:38.85#ibcon#enter sib2, iclass 30, count 0 2006.285.12:16:38.85#ibcon#flushed, iclass 30, count 0 2006.285.12:16:38.85#ibcon#about to write, iclass 30, count 0 2006.285.12:16:38.85#ibcon#wrote, iclass 30, count 0 2006.285.12:16:38.85#ibcon#about to read 3, iclass 30, count 0 2006.285.12:16:38.87#ibcon#read 3, iclass 30, count 0 2006.285.12:16:38.87#ibcon#about to read 4, iclass 30, count 0 2006.285.12:16:38.87#ibcon#read 4, iclass 30, count 0 2006.285.12:16:38.87#ibcon#about to read 5, iclass 30, count 0 2006.285.12:16:38.87#ibcon#read 5, iclass 30, count 0 2006.285.12:16:38.87#ibcon#about to read 6, iclass 30, count 0 2006.285.12:16:38.87#ibcon#read 6, iclass 30, count 0 2006.285.12:16:38.87#ibcon#end of sib2, iclass 30, count 0 2006.285.12:16:38.87#ibcon#*mode == 0, iclass 30, count 0 2006.285.12:16:38.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.12:16:38.87#ibcon#[25=USB\r\n] 2006.285.12:16:38.87#ibcon#*before write, iclass 30, count 0 2006.285.12:16:38.87#ibcon#enter sib2, iclass 30, count 0 2006.285.12:16:38.87#ibcon#flushed, iclass 30, count 0 2006.285.12:16:38.87#ibcon#about to write, iclass 30, count 0 2006.285.12:16:38.87#ibcon#wrote, iclass 30, count 0 2006.285.12:16:38.87#ibcon#about to read 3, iclass 30, count 0 2006.285.12:16:38.90#ibcon#read 3, iclass 30, count 0 2006.285.12:16:38.90#ibcon#about to read 4, iclass 30, count 0 2006.285.12:16:38.90#ibcon#read 4, iclass 30, count 0 2006.285.12:16:38.90#ibcon#about to read 5, iclass 30, count 0 2006.285.12:16:38.90#ibcon#read 5, iclass 30, count 0 2006.285.12:16:38.90#ibcon#about to read 6, iclass 30, count 0 2006.285.12:16:38.90#ibcon#read 6, iclass 30, count 0 2006.285.12:16:38.90#ibcon#end of sib2, iclass 30, count 0 2006.285.12:16:38.90#ibcon#*after write, iclass 30, count 0 2006.285.12:16:38.90#ibcon#*before return 0, iclass 30, count 0 2006.285.12:16:38.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:16:38.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:16:38.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.12:16:38.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.12:16:38.90$vck44/vblo=1,629.99 2006.285.12:16:38.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.12:16:38.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.12:16:38.90#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:38.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:16:38.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:16:38.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:16:38.90#ibcon#enter wrdev, iclass 32, count 0 2006.285.12:16:38.90#ibcon#first serial, iclass 32, count 0 2006.285.12:16:38.90#ibcon#enter sib2, iclass 32, count 0 2006.285.12:16:38.90#ibcon#flushed, iclass 32, count 0 2006.285.12:16:38.90#ibcon#about to write, iclass 32, count 0 2006.285.12:16:38.90#ibcon#wrote, iclass 32, count 0 2006.285.12:16:38.90#ibcon#about to read 3, iclass 32, count 0 2006.285.12:16:38.92#ibcon#read 3, iclass 32, count 0 2006.285.12:16:38.92#ibcon#about to read 4, iclass 32, count 0 2006.285.12:16:38.92#ibcon#read 4, iclass 32, count 0 2006.285.12:16:38.92#ibcon#about to read 5, iclass 32, count 0 2006.285.12:16:38.92#ibcon#read 5, iclass 32, count 0 2006.285.12:16:38.92#ibcon#about to read 6, iclass 32, count 0 2006.285.12:16:38.92#ibcon#read 6, iclass 32, count 0 2006.285.12:16:38.92#ibcon#end of sib2, iclass 32, count 0 2006.285.12:16:38.92#ibcon#*mode == 0, iclass 32, count 0 2006.285.12:16:38.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.12:16:38.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.12:16:38.92#ibcon#*before write, iclass 32, count 0 2006.285.12:16:38.92#ibcon#enter sib2, iclass 32, count 0 2006.285.12:16:38.92#ibcon#flushed, iclass 32, count 0 2006.285.12:16:38.92#ibcon#about to write, iclass 32, count 0 2006.285.12:16:38.92#ibcon#wrote, iclass 32, count 0 2006.285.12:16:38.92#ibcon#about to read 3, iclass 32, count 0 2006.285.12:16:38.96#ibcon#read 3, iclass 32, count 0 2006.285.12:16:38.96#ibcon#about to read 4, iclass 32, count 0 2006.285.12:16:38.96#ibcon#read 4, iclass 32, count 0 2006.285.12:16:38.96#ibcon#about to read 5, iclass 32, count 0 2006.285.12:16:38.96#ibcon#read 5, iclass 32, count 0 2006.285.12:16:38.96#ibcon#about to read 6, iclass 32, count 0 2006.285.12:16:38.96#ibcon#read 6, iclass 32, count 0 2006.285.12:16:38.96#ibcon#end of sib2, iclass 32, count 0 2006.285.12:16:38.96#ibcon#*after write, iclass 32, count 0 2006.285.12:16:38.96#ibcon#*before return 0, iclass 32, count 0 2006.285.12:16:38.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:16:38.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:16:38.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.12:16:38.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.12:16:38.96$vck44/vb=1,4 2006.285.12:16:38.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.12:16:38.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.12:16:38.96#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:38.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.12:16:38.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.12:16:38.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.12:16:38.96#ibcon#enter wrdev, iclass 34, count 2 2006.285.12:16:38.96#ibcon#first serial, iclass 34, count 2 2006.285.12:16:38.96#ibcon#enter sib2, iclass 34, count 2 2006.285.12:16:38.96#ibcon#flushed, iclass 34, count 2 2006.285.12:16:38.96#ibcon#about to write, iclass 34, count 2 2006.285.12:16:38.96#ibcon#wrote, iclass 34, count 2 2006.285.12:16:38.96#ibcon#about to read 3, iclass 34, count 2 2006.285.12:16:38.98#ibcon#read 3, iclass 34, count 2 2006.285.12:16:38.98#ibcon#about to read 4, iclass 34, count 2 2006.285.12:16:38.98#ibcon#read 4, iclass 34, count 2 2006.285.12:16:38.98#ibcon#about to read 5, iclass 34, count 2 2006.285.12:16:38.98#ibcon#read 5, iclass 34, count 2 2006.285.12:16:38.98#ibcon#about to read 6, iclass 34, count 2 2006.285.12:16:38.98#ibcon#read 6, iclass 34, count 2 2006.285.12:16:38.98#ibcon#end of sib2, iclass 34, count 2 2006.285.12:16:38.98#ibcon#*mode == 0, iclass 34, count 2 2006.285.12:16:38.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.12:16:38.98#ibcon#[27=AT01-04\r\n] 2006.285.12:16:38.98#ibcon#*before write, iclass 34, count 2 2006.285.12:16:38.98#ibcon#enter sib2, iclass 34, count 2 2006.285.12:16:38.98#ibcon#flushed, iclass 34, count 2 2006.285.12:16:38.98#ibcon#about to write, iclass 34, count 2 2006.285.12:16:38.98#ibcon#wrote, iclass 34, count 2 2006.285.12:16:38.98#ibcon#about to read 3, iclass 34, count 2 2006.285.12:16:39.01#ibcon#read 3, iclass 34, count 2 2006.285.12:16:39.01#ibcon#about to read 4, iclass 34, count 2 2006.285.12:16:39.01#ibcon#read 4, iclass 34, count 2 2006.285.12:16:39.01#ibcon#about to read 5, iclass 34, count 2 2006.285.12:16:39.01#ibcon#read 5, iclass 34, count 2 2006.285.12:16:39.01#ibcon#about to read 6, iclass 34, count 2 2006.285.12:16:39.01#ibcon#read 6, iclass 34, count 2 2006.285.12:16:39.01#ibcon#end of sib2, iclass 34, count 2 2006.285.12:16:39.01#ibcon#*after write, iclass 34, count 2 2006.285.12:16:39.01#ibcon#*before return 0, iclass 34, count 2 2006.285.12:16:39.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.12:16:39.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.12:16:39.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.12:16:39.01#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:39.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.12:16:39.13#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.12:16:39.13#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.12:16:39.13#ibcon#enter wrdev, iclass 34, count 0 2006.285.12:16:39.13#ibcon#first serial, iclass 34, count 0 2006.285.12:16:39.13#ibcon#enter sib2, iclass 34, count 0 2006.285.12:16:39.13#ibcon#flushed, iclass 34, count 0 2006.285.12:16:39.13#ibcon#about to write, iclass 34, count 0 2006.285.12:16:39.13#ibcon#wrote, iclass 34, count 0 2006.285.12:16:39.13#ibcon#about to read 3, iclass 34, count 0 2006.285.12:16:39.15#ibcon#read 3, iclass 34, count 0 2006.285.12:16:39.15#ibcon#about to read 4, iclass 34, count 0 2006.285.12:16:39.15#ibcon#read 4, iclass 34, count 0 2006.285.12:16:39.15#ibcon#about to read 5, iclass 34, count 0 2006.285.12:16:39.15#ibcon#read 5, iclass 34, count 0 2006.285.12:16:39.15#ibcon#about to read 6, iclass 34, count 0 2006.285.12:16:39.15#ibcon#read 6, iclass 34, count 0 2006.285.12:16:39.15#ibcon#end of sib2, iclass 34, count 0 2006.285.12:16:39.15#ibcon#*mode == 0, iclass 34, count 0 2006.285.12:16:39.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.12:16:39.15#ibcon#[27=USB\r\n] 2006.285.12:16:39.15#ibcon#*before write, iclass 34, count 0 2006.285.12:16:39.15#ibcon#enter sib2, iclass 34, count 0 2006.285.12:16:39.15#ibcon#flushed, iclass 34, count 0 2006.285.12:16:39.15#ibcon#about to write, iclass 34, count 0 2006.285.12:16:39.15#ibcon#wrote, iclass 34, count 0 2006.285.12:16:39.15#ibcon#about to read 3, iclass 34, count 0 2006.285.12:16:39.18#ibcon#read 3, iclass 34, count 0 2006.285.12:16:39.18#ibcon#about to read 4, iclass 34, count 0 2006.285.12:16:39.18#ibcon#read 4, iclass 34, count 0 2006.285.12:16:39.18#ibcon#about to read 5, iclass 34, count 0 2006.285.12:16:39.18#ibcon#read 5, iclass 34, count 0 2006.285.12:16:39.18#ibcon#about to read 6, iclass 34, count 0 2006.285.12:16:39.18#ibcon#read 6, iclass 34, count 0 2006.285.12:16:39.18#ibcon#end of sib2, iclass 34, count 0 2006.285.12:16:39.18#ibcon#*after write, iclass 34, count 0 2006.285.12:16:39.18#ibcon#*before return 0, iclass 34, count 0 2006.285.12:16:39.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.12:16:39.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.12:16:39.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.12:16:39.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.12:16:39.18$vck44/vblo=2,634.99 2006.285.12:16:39.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.12:16:39.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.12:16:39.18#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:39.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:16:39.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:16:39.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:16:39.18#ibcon#enter wrdev, iclass 36, count 0 2006.285.12:16:39.18#ibcon#first serial, iclass 36, count 0 2006.285.12:16:39.18#ibcon#enter sib2, iclass 36, count 0 2006.285.12:16:39.18#ibcon#flushed, iclass 36, count 0 2006.285.12:16:39.18#ibcon#about to write, iclass 36, count 0 2006.285.12:16:39.18#ibcon#wrote, iclass 36, count 0 2006.285.12:16:39.18#ibcon#about to read 3, iclass 36, count 0 2006.285.12:16:39.20#ibcon#read 3, iclass 36, count 0 2006.285.12:16:39.20#ibcon#about to read 4, iclass 36, count 0 2006.285.12:16:39.20#ibcon#read 4, iclass 36, count 0 2006.285.12:16:39.20#ibcon#about to read 5, iclass 36, count 0 2006.285.12:16:39.20#ibcon#read 5, iclass 36, count 0 2006.285.12:16:39.20#ibcon#about to read 6, iclass 36, count 0 2006.285.12:16:39.20#ibcon#read 6, iclass 36, count 0 2006.285.12:16:39.20#ibcon#end of sib2, iclass 36, count 0 2006.285.12:16:39.20#ibcon#*mode == 0, iclass 36, count 0 2006.285.12:16:39.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.12:16:39.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.12:16:39.20#ibcon#*before write, iclass 36, count 0 2006.285.12:16:39.20#ibcon#enter sib2, iclass 36, count 0 2006.285.12:16:39.20#ibcon#flushed, iclass 36, count 0 2006.285.12:16:39.20#ibcon#about to write, iclass 36, count 0 2006.285.12:16:39.20#ibcon#wrote, iclass 36, count 0 2006.285.12:16:39.20#ibcon#about to read 3, iclass 36, count 0 2006.285.12:16:39.24#ibcon#read 3, iclass 36, count 0 2006.285.12:16:39.24#ibcon#about to read 4, iclass 36, count 0 2006.285.12:16:39.24#ibcon#read 4, iclass 36, count 0 2006.285.12:16:39.24#ibcon#about to read 5, iclass 36, count 0 2006.285.12:16:39.24#ibcon#read 5, iclass 36, count 0 2006.285.12:16:39.24#ibcon#about to read 6, iclass 36, count 0 2006.285.12:16:39.24#ibcon#read 6, iclass 36, count 0 2006.285.12:16:39.24#ibcon#end of sib2, iclass 36, count 0 2006.285.12:16:39.24#ibcon#*after write, iclass 36, count 0 2006.285.12:16:39.24#ibcon#*before return 0, iclass 36, count 0 2006.285.12:16:39.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:16:39.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:16:39.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.12:16:39.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.12:16:39.24$vck44/vb=2,5 2006.285.12:16:39.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.12:16:39.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.12:16:39.24#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:39.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:16:39.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:16:39.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:16:39.30#ibcon#enter wrdev, iclass 38, count 2 2006.285.12:16:39.30#ibcon#first serial, iclass 38, count 2 2006.285.12:16:39.30#ibcon#enter sib2, iclass 38, count 2 2006.285.12:16:39.30#ibcon#flushed, iclass 38, count 2 2006.285.12:16:39.30#ibcon#about to write, iclass 38, count 2 2006.285.12:16:39.30#ibcon#wrote, iclass 38, count 2 2006.285.12:16:39.30#ibcon#about to read 3, iclass 38, count 2 2006.285.12:16:39.32#ibcon#read 3, iclass 38, count 2 2006.285.12:16:39.32#ibcon#about to read 4, iclass 38, count 2 2006.285.12:16:39.32#ibcon#read 4, iclass 38, count 2 2006.285.12:16:39.32#ibcon#about to read 5, iclass 38, count 2 2006.285.12:16:39.32#ibcon#read 5, iclass 38, count 2 2006.285.12:16:39.32#ibcon#about to read 6, iclass 38, count 2 2006.285.12:16:39.32#ibcon#read 6, iclass 38, count 2 2006.285.12:16:39.32#ibcon#end of sib2, iclass 38, count 2 2006.285.12:16:39.32#ibcon#*mode == 0, iclass 38, count 2 2006.285.12:16:39.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.12:16:39.32#ibcon#[27=AT02-05\r\n] 2006.285.12:16:39.32#ibcon#*before write, iclass 38, count 2 2006.285.12:16:39.32#ibcon#enter sib2, iclass 38, count 2 2006.285.12:16:39.32#ibcon#flushed, iclass 38, count 2 2006.285.12:16:39.32#ibcon#about to write, iclass 38, count 2 2006.285.12:16:39.32#ibcon#wrote, iclass 38, count 2 2006.285.12:16:39.32#ibcon#about to read 3, iclass 38, count 2 2006.285.12:16:39.35#ibcon#read 3, iclass 38, count 2 2006.285.12:16:39.35#ibcon#about to read 4, iclass 38, count 2 2006.285.12:16:39.35#ibcon#read 4, iclass 38, count 2 2006.285.12:16:39.35#ibcon#about to read 5, iclass 38, count 2 2006.285.12:16:39.35#ibcon#read 5, iclass 38, count 2 2006.285.12:16:39.35#ibcon#about to read 6, iclass 38, count 2 2006.285.12:16:39.35#ibcon#read 6, iclass 38, count 2 2006.285.12:16:39.35#ibcon#end of sib2, iclass 38, count 2 2006.285.12:16:39.35#ibcon#*after write, iclass 38, count 2 2006.285.12:16:39.35#ibcon#*before return 0, iclass 38, count 2 2006.285.12:16:39.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:16:39.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:16:39.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.12:16:39.35#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:39.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:16:39.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:16:39.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:16:39.47#ibcon#enter wrdev, iclass 38, count 0 2006.285.12:16:39.47#ibcon#first serial, iclass 38, count 0 2006.285.12:16:39.47#ibcon#enter sib2, iclass 38, count 0 2006.285.12:16:39.47#ibcon#flushed, iclass 38, count 0 2006.285.12:16:39.47#ibcon#about to write, iclass 38, count 0 2006.285.12:16:39.47#ibcon#wrote, iclass 38, count 0 2006.285.12:16:39.47#ibcon#about to read 3, iclass 38, count 0 2006.285.12:16:39.49#ibcon#read 3, iclass 38, count 0 2006.285.12:16:39.49#ibcon#about to read 4, iclass 38, count 0 2006.285.12:16:39.49#ibcon#read 4, iclass 38, count 0 2006.285.12:16:39.49#ibcon#about to read 5, iclass 38, count 0 2006.285.12:16:39.49#ibcon#read 5, iclass 38, count 0 2006.285.12:16:39.49#ibcon#about to read 6, iclass 38, count 0 2006.285.12:16:39.49#ibcon#read 6, iclass 38, count 0 2006.285.12:16:39.49#ibcon#end of sib2, iclass 38, count 0 2006.285.12:16:39.49#ibcon#*mode == 0, iclass 38, count 0 2006.285.12:16:39.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.12:16:39.49#ibcon#[27=USB\r\n] 2006.285.12:16:39.49#ibcon#*before write, iclass 38, count 0 2006.285.12:16:39.49#ibcon#enter sib2, iclass 38, count 0 2006.285.12:16:39.49#ibcon#flushed, iclass 38, count 0 2006.285.12:16:39.49#ibcon#about to write, iclass 38, count 0 2006.285.12:16:39.49#ibcon#wrote, iclass 38, count 0 2006.285.12:16:39.49#ibcon#about to read 3, iclass 38, count 0 2006.285.12:16:39.52#ibcon#read 3, iclass 38, count 0 2006.285.12:16:39.52#ibcon#about to read 4, iclass 38, count 0 2006.285.12:16:39.52#ibcon#read 4, iclass 38, count 0 2006.285.12:16:39.52#ibcon#about to read 5, iclass 38, count 0 2006.285.12:16:39.52#ibcon#read 5, iclass 38, count 0 2006.285.12:16:39.52#ibcon#about to read 6, iclass 38, count 0 2006.285.12:16:39.52#ibcon#read 6, iclass 38, count 0 2006.285.12:16:39.52#ibcon#end of sib2, iclass 38, count 0 2006.285.12:16:39.52#ibcon#*after write, iclass 38, count 0 2006.285.12:16:39.52#ibcon#*before return 0, iclass 38, count 0 2006.285.12:16:39.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:16:39.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:16:39.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.12:16:39.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.12:16:39.52$vck44/vblo=3,649.99 2006.285.12:16:39.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.12:16:39.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.12:16:39.52#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:39.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:16:39.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:16:39.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:16:39.52#ibcon#enter wrdev, iclass 40, count 0 2006.285.12:16:39.52#ibcon#first serial, iclass 40, count 0 2006.285.12:16:39.52#ibcon#enter sib2, iclass 40, count 0 2006.285.12:16:39.52#ibcon#flushed, iclass 40, count 0 2006.285.12:16:39.52#ibcon#about to write, iclass 40, count 0 2006.285.12:16:39.52#ibcon#wrote, iclass 40, count 0 2006.285.12:16:39.52#ibcon#about to read 3, iclass 40, count 0 2006.285.12:16:39.54#ibcon#read 3, iclass 40, count 0 2006.285.12:16:39.54#ibcon#about to read 4, iclass 40, count 0 2006.285.12:16:39.54#ibcon#read 4, iclass 40, count 0 2006.285.12:16:39.54#ibcon#about to read 5, iclass 40, count 0 2006.285.12:16:39.54#ibcon#read 5, iclass 40, count 0 2006.285.12:16:39.54#ibcon#about to read 6, iclass 40, count 0 2006.285.12:16:39.54#ibcon#read 6, iclass 40, count 0 2006.285.12:16:39.54#ibcon#end of sib2, iclass 40, count 0 2006.285.12:16:39.54#ibcon#*mode == 0, iclass 40, count 0 2006.285.12:16:39.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.12:16:39.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.12:16:39.54#ibcon#*before write, iclass 40, count 0 2006.285.12:16:39.54#ibcon#enter sib2, iclass 40, count 0 2006.285.12:16:39.54#ibcon#flushed, iclass 40, count 0 2006.285.12:16:39.54#ibcon#about to write, iclass 40, count 0 2006.285.12:16:39.54#ibcon#wrote, iclass 40, count 0 2006.285.12:16:39.54#ibcon#about to read 3, iclass 40, count 0 2006.285.12:16:39.58#ibcon#read 3, iclass 40, count 0 2006.285.12:16:39.58#ibcon#about to read 4, iclass 40, count 0 2006.285.12:16:39.58#ibcon#read 4, iclass 40, count 0 2006.285.12:16:39.58#ibcon#about to read 5, iclass 40, count 0 2006.285.12:16:39.58#ibcon#read 5, iclass 40, count 0 2006.285.12:16:39.58#ibcon#about to read 6, iclass 40, count 0 2006.285.12:16:39.58#ibcon#read 6, iclass 40, count 0 2006.285.12:16:39.58#ibcon#end of sib2, iclass 40, count 0 2006.285.12:16:39.58#ibcon#*after write, iclass 40, count 0 2006.285.12:16:39.58#ibcon#*before return 0, iclass 40, count 0 2006.285.12:16:39.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:16:39.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:16:39.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.12:16:39.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.12:16:39.58$vck44/vb=3,4 2006.285.12:16:39.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.12:16:39.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.12:16:39.58#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:39.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:16:39.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:16:39.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:16:39.64#ibcon#enter wrdev, iclass 4, count 2 2006.285.12:16:39.64#ibcon#first serial, iclass 4, count 2 2006.285.12:16:39.64#ibcon#enter sib2, iclass 4, count 2 2006.285.12:16:39.64#ibcon#flushed, iclass 4, count 2 2006.285.12:16:39.64#ibcon#about to write, iclass 4, count 2 2006.285.12:16:39.64#ibcon#wrote, iclass 4, count 2 2006.285.12:16:39.64#ibcon#about to read 3, iclass 4, count 2 2006.285.12:16:39.66#ibcon#read 3, iclass 4, count 2 2006.285.12:16:39.66#ibcon#about to read 4, iclass 4, count 2 2006.285.12:16:39.66#ibcon#read 4, iclass 4, count 2 2006.285.12:16:39.66#ibcon#about to read 5, iclass 4, count 2 2006.285.12:16:39.66#ibcon#read 5, iclass 4, count 2 2006.285.12:16:39.66#ibcon#about to read 6, iclass 4, count 2 2006.285.12:16:39.66#ibcon#read 6, iclass 4, count 2 2006.285.12:16:39.66#ibcon#end of sib2, iclass 4, count 2 2006.285.12:16:39.66#ibcon#*mode == 0, iclass 4, count 2 2006.285.12:16:39.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.12:16:39.66#ibcon#[27=AT03-04\r\n] 2006.285.12:16:39.66#ibcon#*before write, iclass 4, count 2 2006.285.12:16:39.66#ibcon#enter sib2, iclass 4, count 2 2006.285.12:16:39.66#ibcon#flushed, iclass 4, count 2 2006.285.12:16:39.66#ibcon#about to write, iclass 4, count 2 2006.285.12:16:39.66#ibcon#wrote, iclass 4, count 2 2006.285.12:16:39.66#ibcon#about to read 3, iclass 4, count 2 2006.285.12:16:39.69#ibcon#read 3, iclass 4, count 2 2006.285.12:16:39.69#ibcon#about to read 4, iclass 4, count 2 2006.285.12:16:39.69#ibcon#read 4, iclass 4, count 2 2006.285.12:16:39.69#ibcon#about to read 5, iclass 4, count 2 2006.285.12:16:39.69#ibcon#read 5, iclass 4, count 2 2006.285.12:16:39.69#ibcon#about to read 6, iclass 4, count 2 2006.285.12:16:39.69#ibcon#read 6, iclass 4, count 2 2006.285.12:16:39.69#ibcon#end of sib2, iclass 4, count 2 2006.285.12:16:39.69#ibcon#*after write, iclass 4, count 2 2006.285.12:16:39.69#ibcon#*before return 0, iclass 4, count 2 2006.285.12:16:39.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:16:39.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:16:39.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.12:16:39.69#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:39.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:16:39.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:16:39.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:16:39.81#ibcon#enter wrdev, iclass 4, count 0 2006.285.12:16:39.81#ibcon#first serial, iclass 4, count 0 2006.285.12:16:39.81#ibcon#enter sib2, iclass 4, count 0 2006.285.12:16:39.81#ibcon#flushed, iclass 4, count 0 2006.285.12:16:39.81#ibcon#about to write, iclass 4, count 0 2006.285.12:16:39.81#ibcon#wrote, iclass 4, count 0 2006.285.12:16:39.81#ibcon#about to read 3, iclass 4, count 0 2006.285.12:16:39.83#ibcon#read 3, iclass 4, count 0 2006.285.12:16:39.83#ibcon#about to read 4, iclass 4, count 0 2006.285.12:16:39.83#ibcon#read 4, iclass 4, count 0 2006.285.12:16:39.83#ibcon#about to read 5, iclass 4, count 0 2006.285.12:16:39.83#ibcon#read 5, iclass 4, count 0 2006.285.12:16:39.83#ibcon#about to read 6, iclass 4, count 0 2006.285.12:16:39.83#ibcon#read 6, iclass 4, count 0 2006.285.12:16:39.83#ibcon#end of sib2, iclass 4, count 0 2006.285.12:16:39.83#ibcon#*mode == 0, iclass 4, count 0 2006.285.12:16:39.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.12:16:39.83#ibcon#[27=USB\r\n] 2006.285.12:16:39.83#ibcon#*before write, iclass 4, count 0 2006.285.12:16:39.83#ibcon#enter sib2, iclass 4, count 0 2006.285.12:16:39.83#ibcon#flushed, iclass 4, count 0 2006.285.12:16:39.83#ibcon#about to write, iclass 4, count 0 2006.285.12:16:39.83#ibcon#wrote, iclass 4, count 0 2006.285.12:16:39.83#ibcon#about to read 3, iclass 4, count 0 2006.285.12:16:39.86#ibcon#read 3, iclass 4, count 0 2006.285.12:16:39.86#ibcon#about to read 4, iclass 4, count 0 2006.285.12:16:39.86#ibcon#read 4, iclass 4, count 0 2006.285.12:16:39.86#ibcon#about to read 5, iclass 4, count 0 2006.285.12:16:39.86#ibcon#read 5, iclass 4, count 0 2006.285.12:16:39.86#ibcon#about to read 6, iclass 4, count 0 2006.285.12:16:39.86#ibcon#read 6, iclass 4, count 0 2006.285.12:16:39.86#ibcon#end of sib2, iclass 4, count 0 2006.285.12:16:39.86#ibcon#*after write, iclass 4, count 0 2006.285.12:16:39.86#ibcon#*before return 0, iclass 4, count 0 2006.285.12:16:39.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:16:39.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:16:39.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.12:16:39.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.12:16:39.86$vck44/vblo=4,679.99 2006.285.12:16:39.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.12:16:39.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.12:16:39.86#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:39.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:16:39.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:16:39.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:16:39.86#ibcon#enter wrdev, iclass 6, count 0 2006.285.12:16:39.86#ibcon#first serial, iclass 6, count 0 2006.285.12:16:39.86#ibcon#enter sib2, iclass 6, count 0 2006.285.12:16:39.86#ibcon#flushed, iclass 6, count 0 2006.285.12:16:39.86#ibcon#about to write, iclass 6, count 0 2006.285.12:16:39.86#ibcon#wrote, iclass 6, count 0 2006.285.12:16:39.86#ibcon#about to read 3, iclass 6, count 0 2006.285.12:16:39.88#ibcon#read 3, iclass 6, count 0 2006.285.12:16:39.88#ibcon#about to read 4, iclass 6, count 0 2006.285.12:16:39.88#ibcon#read 4, iclass 6, count 0 2006.285.12:16:39.88#ibcon#about to read 5, iclass 6, count 0 2006.285.12:16:39.88#ibcon#read 5, iclass 6, count 0 2006.285.12:16:39.88#ibcon#about to read 6, iclass 6, count 0 2006.285.12:16:39.88#ibcon#read 6, iclass 6, count 0 2006.285.12:16:39.88#ibcon#end of sib2, iclass 6, count 0 2006.285.12:16:39.88#ibcon#*mode == 0, iclass 6, count 0 2006.285.12:16:39.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.12:16:39.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.12:16:39.88#ibcon#*before write, iclass 6, count 0 2006.285.12:16:39.88#ibcon#enter sib2, iclass 6, count 0 2006.285.12:16:39.88#ibcon#flushed, iclass 6, count 0 2006.285.12:16:39.88#ibcon#about to write, iclass 6, count 0 2006.285.12:16:39.88#ibcon#wrote, iclass 6, count 0 2006.285.12:16:39.88#ibcon#about to read 3, iclass 6, count 0 2006.285.12:16:39.92#ibcon#read 3, iclass 6, count 0 2006.285.12:16:39.92#ibcon#about to read 4, iclass 6, count 0 2006.285.12:16:39.92#ibcon#read 4, iclass 6, count 0 2006.285.12:16:39.92#ibcon#about to read 5, iclass 6, count 0 2006.285.12:16:39.92#ibcon#read 5, iclass 6, count 0 2006.285.12:16:39.92#ibcon#about to read 6, iclass 6, count 0 2006.285.12:16:39.92#ibcon#read 6, iclass 6, count 0 2006.285.12:16:39.92#ibcon#end of sib2, iclass 6, count 0 2006.285.12:16:39.92#ibcon#*after write, iclass 6, count 0 2006.285.12:16:39.92#ibcon#*before return 0, iclass 6, count 0 2006.285.12:16:39.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:16:39.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:16:39.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.12:16:39.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.12:16:39.92$vck44/vb=4,5 2006.285.12:16:39.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.12:16:39.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.12:16:39.92#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:39.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:16:39.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:16:39.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:16:39.98#ibcon#enter wrdev, iclass 10, count 2 2006.285.12:16:39.98#ibcon#first serial, iclass 10, count 2 2006.285.12:16:39.98#ibcon#enter sib2, iclass 10, count 2 2006.285.12:16:39.98#ibcon#flushed, iclass 10, count 2 2006.285.12:16:39.98#ibcon#about to write, iclass 10, count 2 2006.285.12:16:39.98#ibcon#wrote, iclass 10, count 2 2006.285.12:16:39.98#ibcon#about to read 3, iclass 10, count 2 2006.285.12:16:40.00#ibcon#read 3, iclass 10, count 2 2006.285.12:16:40.00#ibcon#about to read 4, iclass 10, count 2 2006.285.12:16:40.00#ibcon#read 4, iclass 10, count 2 2006.285.12:16:40.00#ibcon#about to read 5, iclass 10, count 2 2006.285.12:16:40.00#ibcon#read 5, iclass 10, count 2 2006.285.12:16:40.00#ibcon#about to read 6, iclass 10, count 2 2006.285.12:16:40.00#ibcon#read 6, iclass 10, count 2 2006.285.12:16:40.00#ibcon#end of sib2, iclass 10, count 2 2006.285.12:16:40.00#ibcon#*mode == 0, iclass 10, count 2 2006.285.12:16:40.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.12:16:40.00#ibcon#[27=AT04-05\r\n] 2006.285.12:16:40.00#ibcon#*before write, iclass 10, count 2 2006.285.12:16:40.00#ibcon#enter sib2, iclass 10, count 2 2006.285.12:16:40.00#ibcon#flushed, iclass 10, count 2 2006.285.12:16:40.00#ibcon#about to write, iclass 10, count 2 2006.285.12:16:40.00#ibcon#wrote, iclass 10, count 2 2006.285.12:16:40.00#ibcon#about to read 3, iclass 10, count 2 2006.285.12:16:40.03#ibcon#read 3, iclass 10, count 2 2006.285.12:16:40.03#ibcon#about to read 4, iclass 10, count 2 2006.285.12:16:40.03#ibcon#read 4, iclass 10, count 2 2006.285.12:16:40.03#ibcon#about to read 5, iclass 10, count 2 2006.285.12:16:40.03#ibcon#read 5, iclass 10, count 2 2006.285.12:16:40.03#ibcon#about to read 6, iclass 10, count 2 2006.285.12:16:40.03#ibcon#read 6, iclass 10, count 2 2006.285.12:16:40.03#ibcon#end of sib2, iclass 10, count 2 2006.285.12:16:40.03#ibcon#*after write, iclass 10, count 2 2006.285.12:16:40.03#ibcon#*before return 0, iclass 10, count 2 2006.285.12:16:40.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:16:40.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:16:40.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.12:16:40.03#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:40.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:16:40.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:16:40.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:16:40.15#ibcon#enter wrdev, iclass 10, count 0 2006.285.12:16:40.15#ibcon#first serial, iclass 10, count 0 2006.285.12:16:40.15#ibcon#enter sib2, iclass 10, count 0 2006.285.12:16:40.15#ibcon#flushed, iclass 10, count 0 2006.285.12:16:40.15#ibcon#about to write, iclass 10, count 0 2006.285.12:16:40.15#ibcon#wrote, iclass 10, count 0 2006.285.12:16:40.15#ibcon#about to read 3, iclass 10, count 0 2006.285.12:16:40.17#ibcon#read 3, iclass 10, count 0 2006.285.12:16:40.17#ibcon#about to read 4, iclass 10, count 0 2006.285.12:16:40.17#ibcon#read 4, iclass 10, count 0 2006.285.12:16:40.17#ibcon#about to read 5, iclass 10, count 0 2006.285.12:16:40.17#ibcon#read 5, iclass 10, count 0 2006.285.12:16:40.17#ibcon#about to read 6, iclass 10, count 0 2006.285.12:16:40.17#ibcon#read 6, iclass 10, count 0 2006.285.12:16:40.17#ibcon#end of sib2, iclass 10, count 0 2006.285.12:16:40.17#ibcon#*mode == 0, iclass 10, count 0 2006.285.12:16:40.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.12:16:40.17#ibcon#[27=USB\r\n] 2006.285.12:16:40.17#ibcon#*before write, iclass 10, count 0 2006.285.12:16:40.17#ibcon#enter sib2, iclass 10, count 0 2006.285.12:16:40.17#ibcon#flushed, iclass 10, count 0 2006.285.12:16:40.17#ibcon#about to write, iclass 10, count 0 2006.285.12:16:40.17#ibcon#wrote, iclass 10, count 0 2006.285.12:16:40.17#ibcon#about to read 3, iclass 10, count 0 2006.285.12:16:40.20#ibcon#read 3, iclass 10, count 0 2006.285.12:16:40.20#ibcon#about to read 4, iclass 10, count 0 2006.285.12:16:40.20#ibcon#read 4, iclass 10, count 0 2006.285.12:16:40.20#ibcon#about to read 5, iclass 10, count 0 2006.285.12:16:40.20#ibcon#read 5, iclass 10, count 0 2006.285.12:16:40.20#ibcon#about to read 6, iclass 10, count 0 2006.285.12:16:40.20#ibcon#read 6, iclass 10, count 0 2006.285.12:16:40.20#ibcon#end of sib2, iclass 10, count 0 2006.285.12:16:40.20#ibcon#*after write, iclass 10, count 0 2006.285.12:16:40.20#ibcon#*before return 0, iclass 10, count 0 2006.285.12:16:40.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:16:40.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:16:40.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.12:16:40.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.12:16:40.20$vck44/vblo=5,709.99 2006.285.12:16:40.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.12:16:40.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.12:16:40.20#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:40.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:16:40.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:16:40.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:16:40.20#ibcon#enter wrdev, iclass 12, count 0 2006.285.12:16:40.20#ibcon#first serial, iclass 12, count 0 2006.285.12:16:40.20#ibcon#enter sib2, iclass 12, count 0 2006.285.12:16:40.20#ibcon#flushed, iclass 12, count 0 2006.285.12:16:40.20#ibcon#about to write, iclass 12, count 0 2006.285.12:16:40.20#ibcon#wrote, iclass 12, count 0 2006.285.12:16:40.20#ibcon#about to read 3, iclass 12, count 0 2006.285.12:16:40.22#ibcon#read 3, iclass 12, count 0 2006.285.12:16:40.22#ibcon#about to read 4, iclass 12, count 0 2006.285.12:16:40.22#ibcon#read 4, iclass 12, count 0 2006.285.12:16:40.22#ibcon#about to read 5, iclass 12, count 0 2006.285.12:16:40.22#ibcon#read 5, iclass 12, count 0 2006.285.12:16:40.22#ibcon#about to read 6, iclass 12, count 0 2006.285.12:16:40.22#ibcon#read 6, iclass 12, count 0 2006.285.12:16:40.22#ibcon#end of sib2, iclass 12, count 0 2006.285.12:16:40.22#ibcon#*mode == 0, iclass 12, count 0 2006.285.12:16:40.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.12:16:40.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.12:16:40.22#ibcon#*before write, iclass 12, count 0 2006.285.12:16:40.22#ibcon#enter sib2, iclass 12, count 0 2006.285.12:16:40.22#ibcon#flushed, iclass 12, count 0 2006.285.12:16:40.22#ibcon#about to write, iclass 12, count 0 2006.285.12:16:40.22#ibcon#wrote, iclass 12, count 0 2006.285.12:16:40.22#ibcon#about to read 3, iclass 12, count 0 2006.285.12:16:40.26#ibcon#read 3, iclass 12, count 0 2006.285.12:16:40.26#ibcon#about to read 4, iclass 12, count 0 2006.285.12:16:40.26#ibcon#read 4, iclass 12, count 0 2006.285.12:16:40.26#ibcon#about to read 5, iclass 12, count 0 2006.285.12:16:40.26#ibcon#read 5, iclass 12, count 0 2006.285.12:16:40.26#ibcon#about to read 6, iclass 12, count 0 2006.285.12:16:40.26#ibcon#read 6, iclass 12, count 0 2006.285.12:16:40.26#ibcon#end of sib2, iclass 12, count 0 2006.285.12:16:40.26#ibcon#*after write, iclass 12, count 0 2006.285.12:16:40.26#ibcon#*before return 0, iclass 12, count 0 2006.285.12:16:40.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:16:40.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:16:40.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.12:16:40.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.12:16:40.26$vck44/vb=5,4 2006.285.12:16:40.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.12:16:40.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.12:16:40.26#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:40.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:16:40.27#abcon#<5=/04 1.1 1.7 18.95 951015.5\r\n> 2006.285.12:16:40.29#abcon#{5=INTERFACE CLEAR} 2006.285.12:16:40.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:16:40.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:16:40.32#ibcon#enter wrdev, iclass 15, count 2 2006.285.12:16:40.32#ibcon#first serial, iclass 15, count 2 2006.285.12:16:40.32#ibcon#enter sib2, iclass 15, count 2 2006.285.12:16:40.32#ibcon#flushed, iclass 15, count 2 2006.285.12:16:40.32#ibcon#about to write, iclass 15, count 2 2006.285.12:16:40.32#ibcon#wrote, iclass 15, count 2 2006.285.12:16:40.32#ibcon#about to read 3, iclass 15, count 2 2006.285.12:16:40.34#ibcon#read 3, iclass 15, count 2 2006.285.12:16:40.34#ibcon#about to read 4, iclass 15, count 2 2006.285.12:16:40.34#ibcon#read 4, iclass 15, count 2 2006.285.12:16:40.34#ibcon#about to read 5, iclass 15, count 2 2006.285.12:16:40.34#ibcon#read 5, iclass 15, count 2 2006.285.12:16:40.34#ibcon#about to read 6, iclass 15, count 2 2006.285.12:16:40.34#ibcon#read 6, iclass 15, count 2 2006.285.12:16:40.34#ibcon#end of sib2, iclass 15, count 2 2006.285.12:16:40.34#ibcon#*mode == 0, iclass 15, count 2 2006.285.12:16:40.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.12:16:40.34#ibcon#[27=AT05-04\r\n] 2006.285.12:16:40.34#ibcon#*before write, iclass 15, count 2 2006.285.12:16:40.34#ibcon#enter sib2, iclass 15, count 2 2006.285.12:16:40.34#ibcon#flushed, iclass 15, count 2 2006.285.12:16:40.34#ibcon#about to write, iclass 15, count 2 2006.285.12:16:40.34#ibcon#wrote, iclass 15, count 2 2006.285.12:16:40.34#ibcon#about to read 3, iclass 15, count 2 2006.285.12:16:40.35#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:16:40.37#ibcon#read 3, iclass 15, count 2 2006.285.12:16:40.37#ibcon#about to read 4, iclass 15, count 2 2006.285.12:16:40.37#ibcon#read 4, iclass 15, count 2 2006.285.12:16:40.37#ibcon#about to read 5, iclass 15, count 2 2006.285.12:16:40.37#ibcon#read 5, iclass 15, count 2 2006.285.12:16:40.37#ibcon#about to read 6, iclass 15, count 2 2006.285.12:16:40.37#ibcon#read 6, iclass 15, count 2 2006.285.12:16:40.37#ibcon#end of sib2, iclass 15, count 2 2006.285.12:16:40.37#ibcon#*after write, iclass 15, count 2 2006.285.12:16:40.37#ibcon#*before return 0, iclass 15, count 2 2006.285.12:16:40.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:16:40.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:16:40.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.12:16:40.37#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:40.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:16:40.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:16:40.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:16:40.49#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:16:40.49#ibcon#first serial, iclass 15, count 0 2006.285.12:16:40.49#ibcon#enter sib2, iclass 15, count 0 2006.285.12:16:40.49#ibcon#flushed, iclass 15, count 0 2006.285.12:16:40.49#ibcon#about to write, iclass 15, count 0 2006.285.12:16:40.49#ibcon#wrote, iclass 15, count 0 2006.285.12:16:40.49#ibcon#about to read 3, iclass 15, count 0 2006.285.12:16:40.51#ibcon#read 3, iclass 15, count 0 2006.285.12:16:40.51#ibcon#about to read 4, iclass 15, count 0 2006.285.12:16:40.51#ibcon#read 4, iclass 15, count 0 2006.285.12:16:40.51#ibcon#about to read 5, iclass 15, count 0 2006.285.12:16:40.51#ibcon#read 5, iclass 15, count 0 2006.285.12:16:40.51#ibcon#about to read 6, iclass 15, count 0 2006.285.12:16:40.51#ibcon#read 6, iclass 15, count 0 2006.285.12:16:40.51#ibcon#end of sib2, iclass 15, count 0 2006.285.12:16:40.51#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:16:40.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:16:40.51#ibcon#[27=USB\r\n] 2006.285.12:16:40.51#ibcon#*before write, iclass 15, count 0 2006.285.12:16:40.51#ibcon#enter sib2, iclass 15, count 0 2006.285.12:16:40.51#ibcon#flushed, iclass 15, count 0 2006.285.12:16:40.51#ibcon#about to write, iclass 15, count 0 2006.285.12:16:40.51#ibcon#wrote, iclass 15, count 0 2006.285.12:16:40.51#ibcon#about to read 3, iclass 15, count 0 2006.285.12:16:40.54#ibcon#read 3, iclass 15, count 0 2006.285.12:16:40.54#ibcon#about to read 4, iclass 15, count 0 2006.285.12:16:40.54#ibcon#read 4, iclass 15, count 0 2006.285.12:16:40.54#ibcon#about to read 5, iclass 15, count 0 2006.285.12:16:40.54#ibcon#read 5, iclass 15, count 0 2006.285.12:16:40.54#ibcon#about to read 6, iclass 15, count 0 2006.285.12:16:40.54#ibcon#read 6, iclass 15, count 0 2006.285.12:16:40.54#ibcon#end of sib2, iclass 15, count 0 2006.285.12:16:40.54#ibcon#*after write, iclass 15, count 0 2006.285.12:16:40.54#ibcon#*before return 0, iclass 15, count 0 2006.285.12:16:40.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:16:40.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:16:40.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:16:40.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:16:40.54$vck44/vblo=6,719.99 2006.285.12:16:40.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.12:16:40.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.12:16:40.54#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:40.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:16:40.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:16:40.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:16:40.54#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:16:40.54#ibcon#first serial, iclass 20, count 0 2006.285.12:16:40.54#ibcon#enter sib2, iclass 20, count 0 2006.285.12:16:40.54#ibcon#flushed, iclass 20, count 0 2006.285.12:16:40.54#ibcon#about to write, iclass 20, count 0 2006.285.12:16:40.54#ibcon#wrote, iclass 20, count 0 2006.285.12:16:40.54#ibcon#about to read 3, iclass 20, count 0 2006.285.12:16:40.56#ibcon#read 3, iclass 20, count 0 2006.285.12:16:40.56#ibcon#about to read 4, iclass 20, count 0 2006.285.12:16:40.56#ibcon#read 4, iclass 20, count 0 2006.285.12:16:40.56#ibcon#about to read 5, iclass 20, count 0 2006.285.12:16:40.56#ibcon#read 5, iclass 20, count 0 2006.285.12:16:40.56#ibcon#about to read 6, iclass 20, count 0 2006.285.12:16:40.56#ibcon#read 6, iclass 20, count 0 2006.285.12:16:40.56#ibcon#end of sib2, iclass 20, count 0 2006.285.12:16:40.56#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:16:40.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:16:40.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.12:16:40.56#ibcon#*before write, iclass 20, count 0 2006.285.12:16:40.56#ibcon#enter sib2, iclass 20, count 0 2006.285.12:16:40.56#ibcon#flushed, iclass 20, count 0 2006.285.12:16:40.56#ibcon#about to write, iclass 20, count 0 2006.285.12:16:40.56#ibcon#wrote, iclass 20, count 0 2006.285.12:16:40.56#ibcon#about to read 3, iclass 20, count 0 2006.285.12:16:40.60#ibcon#read 3, iclass 20, count 0 2006.285.12:16:40.60#ibcon#about to read 4, iclass 20, count 0 2006.285.12:16:40.60#ibcon#read 4, iclass 20, count 0 2006.285.12:16:40.60#ibcon#about to read 5, iclass 20, count 0 2006.285.12:16:40.60#ibcon#read 5, iclass 20, count 0 2006.285.12:16:40.60#ibcon#about to read 6, iclass 20, count 0 2006.285.12:16:40.60#ibcon#read 6, iclass 20, count 0 2006.285.12:16:40.60#ibcon#end of sib2, iclass 20, count 0 2006.285.12:16:40.60#ibcon#*after write, iclass 20, count 0 2006.285.12:16:40.60#ibcon#*before return 0, iclass 20, count 0 2006.285.12:16:40.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:16:40.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:16:40.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:16:40.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:16:40.60$vck44/vb=6,3 2006.285.12:16:40.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.12:16:40.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.12:16:40.60#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:40.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:16:40.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:16:40.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:16:40.66#ibcon#enter wrdev, iclass 22, count 2 2006.285.12:16:40.66#ibcon#first serial, iclass 22, count 2 2006.285.12:16:40.66#ibcon#enter sib2, iclass 22, count 2 2006.285.12:16:40.66#ibcon#flushed, iclass 22, count 2 2006.285.12:16:40.66#ibcon#about to write, iclass 22, count 2 2006.285.12:16:40.66#ibcon#wrote, iclass 22, count 2 2006.285.12:16:40.66#ibcon#about to read 3, iclass 22, count 2 2006.285.12:16:40.68#ibcon#read 3, iclass 22, count 2 2006.285.12:16:40.68#ibcon#about to read 4, iclass 22, count 2 2006.285.12:16:40.68#ibcon#read 4, iclass 22, count 2 2006.285.12:16:40.68#ibcon#about to read 5, iclass 22, count 2 2006.285.12:16:40.68#ibcon#read 5, iclass 22, count 2 2006.285.12:16:40.68#ibcon#about to read 6, iclass 22, count 2 2006.285.12:16:40.68#ibcon#read 6, iclass 22, count 2 2006.285.12:16:40.68#ibcon#end of sib2, iclass 22, count 2 2006.285.12:16:40.68#ibcon#*mode == 0, iclass 22, count 2 2006.285.12:16:40.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.12:16:40.68#ibcon#[27=AT06-03\r\n] 2006.285.12:16:40.68#ibcon#*before write, iclass 22, count 2 2006.285.12:16:40.68#ibcon#enter sib2, iclass 22, count 2 2006.285.12:16:40.68#ibcon#flushed, iclass 22, count 2 2006.285.12:16:40.68#ibcon#about to write, iclass 22, count 2 2006.285.12:16:40.68#ibcon#wrote, iclass 22, count 2 2006.285.12:16:40.68#ibcon#about to read 3, iclass 22, count 2 2006.285.12:16:40.71#ibcon#read 3, iclass 22, count 2 2006.285.12:16:40.71#ibcon#about to read 4, iclass 22, count 2 2006.285.12:16:40.71#ibcon#read 4, iclass 22, count 2 2006.285.12:16:40.71#ibcon#about to read 5, iclass 22, count 2 2006.285.12:16:40.71#ibcon#read 5, iclass 22, count 2 2006.285.12:16:40.71#ibcon#about to read 6, iclass 22, count 2 2006.285.12:16:40.71#ibcon#read 6, iclass 22, count 2 2006.285.12:16:40.71#ibcon#end of sib2, iclass 22, count 2 2006.285.12:16:40.71#ibcon#*after write, iclass 22, count 2 2006.285.12:16:40.71#ibcon#*before return 0, iclass 22, count 2 2006.285.12:16:40.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:16:40.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:16:40.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.12:16:40.71#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:40.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:16:40.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:16:40.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:16:40.83#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:16:40.83#ibcon#first serial, iclass 22, count 0 2006.285.12:16:40.83#ibcon#enter sib2, iclass 22, count 0 2006.285.12:16:40.83#ibcon#flushed, iclass 22, count 0 2006.285.12:16:40.83#ibcon#about to write, iclass 22, count 0 2006.285.12:16:40.83#ibcon#wrote, iclass 22, count 0 2006.285.12:16:40.83#ibcon#about to read 3, iclass 22, count 0 2006.285.12:16:40.85#ibcon#read 3, iclass 22, count 0 2006.285.12:16:40.85#ibcon#about to read 4, iclass 22, count 0 2006.285.12:16:40.85#ibcon#read 4, iclass 22, count 0 2006.285.12:16:40.85#ibcon#about to read 5, iclass 22, count 0 2006.285.12:16:40.85#ibcon#read 5, iclass 22, count 0 2006.285.12:16:40.85#ibcon#about to read 6, iclass 22, count 0 2006.285.12:16:40.85#ibcon#read 6, iclass 22, count 0 2006.285.12:16:40.85#ibcon#end of sib2, iclass 22, count 0 2006.285.12:16:40.85#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:16:40.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:16:40.85#ibcon#[27=USB\r\n] 2006.285.12:16:40.85#ibcon#*before write, iclass 22, count 0 2006.285.12:16:40.85#ibcon#enter sib2, iclass 22, count 0 2006.285.12:16:40.85#ibcon#flushed, iclass 22, count 0 2006.285.12:16:40.85#ibcon#about to write, iclass 22, count 0 2006.285.12:16:40.85#ibcon#wrote, iclass 22, count 0 2006.285.12:16:40.85#ibcon#about to read 3, iclass 22, count 0 2006.285.12:16:40.88#ibcon#read 3, iclass 22, count 0 2006.285.12:16:40.88#ibcon#about to read 4, iclass 22, count 0 2006.285.12:16:40.88#ibcon#read 4, iclass 22, count 0 2006.285.12:16:40.88#ibcon#about to read 5, iclass 22, count 0 2006.285.12:16:40.88#ibcon#read 5, iclass 22, count 0 2006.285.12:16:40.88#ibcon#about to read 6, iclass 22, count 0 2006.285.12:16:40.88#ibcon#read 6, iclass 22, count 0 2006.285.12:16:40.88#ibcon#end of sib2, iclass 22, count 0 2006.285.12:16:40.88#ibcon#*after write, iclass 22, count 0 2006.285.12:16:40.88#ibcon#*before return 0, iclass 22, count 0 2006.285.12:16:40.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:16:40.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:16:40.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:16:40.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:16:40.88$vck44/vblo=7,734.99 2006.285.12:16:40.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.12:16:40.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.12:16:40.88#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:40.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:16:40.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:16:40.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:16:40.88#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:16:40.88#ibcon#first serial, iclass 24, count 0 2006.285.12:16:40.88#ibcon#enter sib2, iclass 24, count 0 2006.285.12:16:40.88#ibcon#flushed, iclass 24, count 0 2006.285.12:16:40.88#ibcon#about to write, iclass 24, count 0 2006.285.12:16:40.88#ibcon#wrote, iclass 24, count 0 2006.285.12:16:40.88#ibcon#about to read 3, iclass 24, count 0 2006.285.12:16:40.90#ibcon#read 3, iclass 24, count 0 2006.285.12:16:40.90#ibcon#about to read 4, iclass 24, count 0 2006.285.12:16:40.90#ibcon#read 4, iclass 24, count 0 2006.285.12:16:40.90#ibcon#about to read 5, iclass 24, count 0 2006.285.12:16:40.90#ibcon#read 5, iclass 24, count 0 2006.285.12:16:40.90#ibcon#about to read 6, iclass 24, count 0 2006.285.12:16:40.90#ibcon#read 6, iclass 24, count 0 2006.285.12:16:40.90#ibcon#end of sib2, iclass 24, count 0 2006.285.12:16:40.90#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:16:40.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:16:40.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.12:16:40.90#ibcon#*before write, iclass 24, count 0 2006.285.12:16:40.90#ibcon#enter sib2, iclass 24, count 0 2006.285.12:16:40.90#ibcon#flushed, iclass 24, count 0 2006.285.12:16:40.90#ibcon#about to write, iclass 24, count 0 2006.285.12:16:40.90#ibcon#wrote, iclass 24, count 0 2006.285.12:16:40.90#ibcon#about to read 3, iclass 24, count 0 2006.285.12:16:40.94#ibcon#read 3, iclass 24, count 0 2006.285.12:16:40.94#ibcon#about to read 4, iclass 24, count 0 2006.285.12:16:40.94#ibcon#read 4, iclass 24, count 0 2006.285.12:16:40.94#ibcon#about to read 5, iclass 24, count 0 2006.285.12:16:40.94#ibcon#read 5, iclass 24, count 0 2006.285.12:16:40.94#ibcon#about to read 6, iclass 24, count 0 2006.285.12:16:40.94#ibcon#read 6, iclass 24, count 0 2006.285.12:16:40.94#ibcon#end of sib2, iclass 24, count 0 2006.285.12:16:40.94#ibcon#*after write, iclass 24, count 0 2006.285.12:16:40.94#ibcon#*before return 0, iclass 24, count 0 2006.285.12:16:40.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:16:40.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:16:40.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:16:40.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:16:40.94$vck44/vb=7,4 2006.285.12:16:40.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.12:16:40.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.12:16:40.94#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:40.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:16:41.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:16:41.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:16:41.00#ibcon#enter wrdev, iclass 26, count 2 2006.285.12:16:41.00#ibcon#first serial, iclass 26, count 2 2006.285.12:16:41.00#ibcon#enter sib2, iclass 26, count 2 2006.285.12:16:41.00#ibcon#flushed, iclass 26, count 2 2006.285.12:16:41.00#ibcon#about to write, iclass 26, count 2 2006.285.12:16:41.00#ibcon#wrote, iclass 26, count 2 2006.285.12:16:41.00#ibcon#about to read 3, iclass 26, count 2 2006.285.12:16:41.02#ibcon#read 3, iclass 26, count 2 2006.285.12:16:41.02#ibcon#about to read 4, iclass 26, count 2 2006.285.12:16:41.02#ibcon#read 4, iclass 26, count 2 2006.285.12:16:41.02#ibcon#about to read 5, iclass 26, count 2 2006.285.12:16:41.02#ibcon#read 5, iclass 26, count 2 2006.285.12:16:41.02#ibcon#about to read 6, iclass 26, count 2 2006.285.12:16:41.02#ibcon#read 6, iclass 26, count 2 2006.285.12:16:41.02#ibcon#end of sib2, iclass 26, count 2 2006.285.12:16:41.02#ibcon#*mode == 0, iclass 26, count 2 2006.285.12:16:41.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.12:16:41.02#ibcon#[27=AT07-04\r\n] 2006.285.12:16:41.02#ibcon#*before write, iclass 26, count 2 2006.285.12:16:41.02#ibcon#enter sib2, iclass 26, count 2 2006.285.12:16:41.02#ibcon#flushed, iclass 26, count 2 2006.285.12:16:41.02#ibcon#about to write, iclass 26, count 2 2006.285.12:16:41.02#ibcon#wrote, iclass 26, count 2 2006.285.12:16:41.02#ibcon#about to read 3, iclass 26, count 2 2006.285.12:16:41.05#ibcon#read 3, iclass 26, count 2 2006.285.12:16:41.05#ibcon#about to read 4, iclass 26, count 2 2006.285.12:16:41.05#ibcon#read 4, iclass 26, count 2 2006.285.12:16:41.05#ibcon#about to read 5, iclass 26, count 2 2006.285.12:16:41.05#ibcon#read 5, iclass 26, count 2 2006.285.12:16:41.05#ibcon#about to read 6, iclass 26, count 2 2006.285.12:16:41.05#ibcon#read 6, iclass 26, count 2 2006.285.12:16:41.05#ibcon#end of sib2, iclass 26, count 2 2006.285.12:16:41.05#ibcon#*after write, iclass 26, count 2 2006.285.12:16:41.05#ibcon#*before return 0, iclass 26, count 2 2006.285.12:16:41.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:16:41.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:16:41.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.12:16:41.05#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:41.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:16:41.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:16:41.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:16:41.17#ibcon#enter wrdev, iclass 26, count 0 2006.285.12:16:41.17#ibcon#first serial, iclass 26, count 0 2006.285.12:16:41.17#ibcon#enter sib2, iclass 26, count 0 2006.285.12:16:41.17#ibcon#flushed, iclass 26, count 0 2006.285.12:16:41.17#ibcon#about to write, iclass 26, count 0 2006.285.12:16:41.17#ibcon#wrote, iclass 26, count 0 2006.285.12:16:41.17#ibcon#about to read 3, iclass 26, count 0 2006.285.12:16:41.19#ibcon#read 3, iclass 26, count 0 2006.285.12:16:41.19#ibcon#about to read 4, iclass 26, count 0 2006.285.12:16:41.19#ibcon#read 4, iclass 26, count 0 2006.285.12:16:41.19#ibcon#about to read 5, iclass 26, count 0 2006.285.12:16:41.19#ibcon#read 5, iclass 26, count 0 2006.285.12:16:41.19#ibcon#about to read 6, iclass 26, count 0 2006.285.12:16:41.19#ibcon#read 6, iclass 26, count 0 2006.285.12:16:41.19#ibcon#end of sib2, iclass 26, count 0 2006.285.12:16:41.19#ibcon#*mode == 0, iclass 26, count 0 2006.285.12:16:41.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.12:16:41.19#ibcon#[27=USB\r\n] 2006.285.12:16:41.19#ibcon#*before write, iclass 26, count 0 2006.285.12:16:41.19#ibcon#enter sib2, iclass 26, count 0 2006.285.12:16:41.19#ibcon#flushed, iclass 26, count 0 2006.285.12:16:41.19#ibcon#about to write, iclass 26, count 0 2006.285.12:16:41.19#ibcon#wrote, iclass 26, count 0 2006.285.12:16:41.19#ibcon#about to read 3, iclass 26, count 0 2006.285.12:16:41.22#ibcon#read 3, iclass 26, count 0 2006.285.12:16:41.22#ibcon#about to read 4, iclass 26, count 0 2006.285.12:16:41.22#ibcon#read 4, iclass 26, count 0 2006.285.12:16:41.22#ibcon#about to read 5, iclass 26, count 0 2006.285.12:16:41.22#ibcon#read 5, iclass 26, count 0 2006.285.12:16:41.22#ibcon#about to read 6, iclass 26, count 0 2006.285.12:16:41.22#ibcon#read 6, iclass 26, count 0 2006.285.12:16:41.22#ibcon#end of sib2, iclass 26, count 0 2006.285.12:16:41.22#ibcon#*after write, iclass 26, count 0 2006.285.12:16:41.22#ibcon#*before return 0, iclass 26, count 0 2006.285.12:16:41.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:16:41.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:16:41.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.12:16:41.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.12:16:41.22$vck44/vblo=8,744.99 2006.285.12:16:41.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.12:16:41.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.12:16:41.22#ibcon#ireg 17 cls_cnt 0 2006.285.12:16:41.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:16:41.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:16:41.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:16:41.22#ibcon#enter wrdev, iclass 28, count 0 2006.285.12:16:41.22#ibcon#first serial, iclass 28, count 0 2006.285.12:16:41.22#ibcon#enter sib2, iclass 28, count 0 2006.285.12:16:41.22#ibcon#flushed, iclass 28, count 0 2006.285.12:16:41.22#ibcon#about to write, iclass 28, count 0 2006.285.12:16:41.22#ibcon#wrote, iclass 28, count 0 2006.285.12:16:41.22#ibcon#about to read 3, iclass 28, count 0 2006.285.12:16:41.24#ibcon#read 3, iclass 28, count 0 2006.285.12:16:41.24#ibcon#about to read 4, iclass 28, count 0 2006.285.12:16:41.24#ibcon#read 4, iclass 28, count 0 2006.285.12:16:41.24#ibcon#about to read 5, iclass 28, count 0 2006.285.12:16:41.24#ibcon#read 5, iclass 28, count 0 2006.285.12:16:41.24#ibcon#about to read 6, iclass 28, count 0 2006.285.12:16:41.24#ibcon#read 6, iclass 28, count 0 2006.285.12:16:41.24#ibcon#end of sib2, iclass 28, count 0 2006.285.12:16:41.24#ibcon#*mode == 0, iclass 28, count 0 2006.285.12:16:41.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.12:16:41.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.12:16:41.24#ibcon#*before write, iclass 28, count 0 2006.285.12:16:41.24#ibcon#enter sib2, iclass 28, count 0 2006.285.12:16:41.24#ibcon#flushed, iclass 28, count 0 2006.285.12:16:41.24#ibcon#about to write, iclass 28, count 0 2006.285.12:16:41.24#ibcon#wrote, iclass 28, count 0 2006.285.12:16:41.24#ibcon#about to read 3, iclass 28, count 0 2006.285.12:16:41.28#ibcon#read 3, iclass 28, count 0 2006.285.12:16:41.28#ibcon#about to read 4, iclass 28, count 0 2006.285.12:16:41.28#ibcon#read 4, iclass 28, count 0 2006.285.12:16:41.28#ibcon#about to read 5, iclass 28, count 0 2006.285.12:16:41.28#ibcon#read 5, iclass 28, count 0 2006.285.12:16:41.28#ibcon#about to read 6, iclass 28, count 0 2006.285.12:16:41.28#ibcon#read 6, iclass 28, count 0 2006.285.12:16:41.28#ibcon#end of sib2, iclass 28, count 0 2006.285.12:16:41.28#ibcon#*after write, iclass 28, count 0 2006.285.12:16:41.28#ibcon#*before return 0, iclass 28, count 0 2006.285.12:16:41.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:16:41.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:16:41.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.12:16:41.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.12:16:41.28$vck44/vb=8,4 2006.285.12:16:41.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.12:16:41.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.12:16:41.28#ibcon#ireg 11 cls_cnt 2 2006.285.12:16:41.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:16:41.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:16:41.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:16:41.34#ibcon#enter wrdev, iclass 30, count 2 2006.285.12:16:41.34#ibcon#first serial, iclass 30, count 2 2006.285.12:16:41.34#ibcon#enter sib2, iclass 30, count 2 2006.285.12:16:41.34#ibcon#flushed, iclass 30, count 2 2006.285.12:16:41.34#ibcon#about to write, iclass 30, count 2 2006.285.12:16:41.34#ibcon#wrote, iclass 30, count 2 2006.285.12:16:41.34#ibcon#about to read 3, iclass 30, count 2 2006.285.12:16:41.36#ibcon#read 3, iclass 30, count 2 2006.285.12:16:41.36#ibcon#about to read 4, iclass 30, count 2 2006.285.12:16:41.36#ibcon#read 4, iclass 30, count 2 2006.285.12:16:41.36#ibcon#about to read 5, iclass 30, count 2 2006.285.12:16:41.36#ibcon#read 5, iclass 30, count 2 2006.285.12:16:41.36#ibcon#about to read 6, iclass 30, count 2 2006.285.12:16:41.36#ibcon#read 6, iclass 30, count 2 2006.285.12:16:41.36#ibcon#end of sib2, iclass 30, count 2 2006.285.12:16:41.36#ibcon#*mode == 0, iclass 30, count 2 2006.285.12:16:41.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.12:16:41.36#ibcon#[27=AT08-04\r\n] 2006.285.12:16:41.36#ibcon#*before write, iclass 30, count 2 2006.285.12:16:41.36#ibcon#enter sib2, iclass 30, count 2 2006.285.12:16:41.36#ibcon#flushed, iclass 30, count 2 2006.285.12:16:41.36#ibcon#about to write, iclass 30, count 2 2006.285.12:16:41.36#ibcon#wrote, iclass 30, count 2 2006.285.12:16:41.36#ibcon#about to read 3, iclass 30, count 2 2006.285.12:16:41.39#ibcon#read 3, iclass 30, count 2 2006.285.12:16:41.39#ibcon#about to read 4, iclass 30, count 2 2006.285.12:16:41.39#ibcon#read 4, iclass 30, count 2 2006.285.12:16:41.39#ibcon#about to read 5, iclass 30, count 2 2006.285.12:16:41.39#ibcon#read 5, iclass 30, count 2 2006.285.12:16:41.39#ibcon#about to read 6, iclass 30, count 2 2006.285.12:16:41.39#ibcon#read 6, iclass 30, count 2 2006.285.12:16:41.39#ibcon#end of sib2, iclass 30, count 2 2006.285.12:16:41.39#ibcon#*after write, iclass 30, count 2 2006.285.12:16:41.39#ibcon#*before return 0, iclass 30, count 2 2006.285.12:16:41.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:16:41.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:16:41.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.12:16:41.39#ibcon#ireg 7 cls_cnt 0 2006.285.12:16:41.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:16:41.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:16:41.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:16:41.51#ibcon#enter wrdev, iclass 30, count 0 2006.285.12:16:41.51#ibcon#first serial, iclass 30, count 0 2006.285.12:16:41.51#ibcon#enter sib2, iclass 30, count 0 2006.285.12:16:41.51#ibcon#flushed, iclass 30, count 0 2006.285.12:16:41.51#ibcon#about to write, iclass 30, count 0 2006.285.12:16:41.51#ibcon#wrote, iclass 30, count 0 2006.285.12:16:41.51#ibcon#about to read 3, iclass 30, count 0 2006.285.12:16:41.53#ibcon#read 3, iclass 30, count 0 2006.285.12:16:41.53#ibcon#about to read 4, iclass 30, count 0 2006.285.12:16:41.53#ibcon#read 4, iclass 30, count 0 2006.285.12:16:41.53#ibcon#about to read 5, iclass 30, count 0 2006.285.12:16:41.53#ibcon#read 5, iclass 30, count 0 2006.285.12:16:41.53#ibcon#about to read 6, iclass 30, count 0 2006.285.12:16:41.53#ibcon#read 6, iclass 30, count 0 2006.285.12:16:41.53#ibcon#end of sib2, iclass 30, count 0 2006.285.12:16:41.53#ibcon#*mode == 0, iclass 30, count 0 2006.285.12:16:41.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.12:16:41.53#ibcon#[27=USB\r\n] 2006.285.12:16:41.53#ibcon#*before write, iclass 30, count 0 2006.285.12:16:41.53#ibcon#enter sib2, iclass 30, count 0 2006.285.12:16:41.53#ibcon#flushed, iclass 30, count 0 2006.285.12:16:41.53#ibcon#about to write, iclass 30, count 0 2006.285.12:16:41.53#ibcon#wrote, iclass 30, count 0 2006.285.12:16:41.53#ibcon#about to read 3, iclass 30, count 0 2006.285.12:16:41.56#ibcon#read 3, iclass 30, count 0 2006.285.12:16:41.56#ibcon#about to read 4, iclass 30, count 0 2006.285.12:16:41.56#ibcon#read 4, iclass 30, count 0 2006.285.12:16:41.56#ibcon#about to read 5, iclass 30, count 0 2006.285.12:16:41.56#ibcon#read 5, iclass 30, count 0 2006.285.12:16:41.56#ibcon#about to read 6, iclass 30, count 0 2006.285.12:16:41.56#ibcon#read 6, iclass 30, count 0 2006.285.12:16:41.56#ibcon#end of sib2, iclass 30, count 0 2006.285.12:16:41.56#ibcon#*after write, iclass 30, count 0 2006.285.12:16:41.56#ibcon#*before return 0, iclass 30, count 0 2006.285.12:16:41.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:16:41.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:16:41.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.12:16:41.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.12:16:41.56$vck44/vabw=wide 2006.285.12:16:41.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.12:16:41.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.12:16:41.56#ibcon#ireg 8 cls_cnt 0 2006.285.12:16:41.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:16:41.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:16:41.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:16:41.56#ibcon#enter wrdev, iclass 32, count 0 2006.285.12:16:41.56#ibcon#first serial, iclass 32, count 0 2006.285.12:16:41.56#ibcon#enter sib2, iclass 32, count 0 2006.285.12:16:41.56#ibcon#flushed, iclass 32, count 0 2006.285.12:16:41.56#ibcon#about to write, iclass 32, count 0 2006.285.12:16:41.56#ibcon#wrote, iclass 32, count 0 2006.285.12:16:41.56#ibcon#about to read 3, iclass 32, count 0 2006.285.12:16:41.58#ibcon#read 3, iclass 32, count 0 2006.285.12:16:41.58#ibcon#about to read 4, iclass 32, count 0 2006.285.12:16:41.58#ibcon#read 4, iclass 32, count 0 2006.285.12:16:41.58#ibcon#about to read 5, iclass 32, count 0 2006.285.12:16:41.58#ibcon#read 5, iclass 32, count 0 2006.285.12:16:41.58#ibcon#about to read 6, iclass 32, count 0 2006.285.12:16:41.58#ibcon#read 6, iclass 32, count 0 2006.285.12:16:41.58#ibcon#end of sib2, iclass 32, count 0 2006.285.12:16:41.58#ibcon#*mode == 0, iclass 32, count 0 2006.285.12:16:41.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.12:16:41.58#ibcon#[25=BW32\r\n] 2006.285.12:16:41.58#ibcon#*before write, iclass 32, count 0 2006.285.12:16:41.58#ibcon#enter sib2, iclass 32, count 0 2006.285.12:16:41.58#ibcon#flushed, iclass 32, count 0 2006.285.12:16:41.58#ibcon#about to write, iclass 32, count 0 2006.285.12:16:41.58#ibcon#wrote, iclass 32, count 0 2006.285.12:16:41.58#ibcon#about to read 3, iclass 32, count 0 2006.285.12:16:41.61#ibcon#read 3, iclass 32, count 0 2006.285.12:16:41.61#ibcon#about to read 4, iclass 32, count 0 2006.285.12:16:41.61#ibcon#read 4, iclass 32, count 0 2006.285.12:16:41.61#ibcon#about to read 5, iclass 32, count 0 2006.285.12:16:41.61#ibcon#read 5, iclass 32, count 0 2006.285.12:16:41.61#ibcon#about to read 6, iclass 32, count 0 2006.285.12:16:41.61#ibcon#read 6, iclass 32, count 0 2006.285.12:16:41.61#ibcon#end of sib2, iclass 32, count 0 2006.285.12:16:41.61#ibcon#*after write, iclass 32, count 0 2006.285.12:16:41.61#ibcon#*before return 0, iclass 32, count 0 2006.285.12:16:41.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:16:41.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:16:41.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.12:16:41.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.12:16:41.61$vck44/vbbw=wide 2006.285.12:16:41.61#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.12:16:41.61#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.12:16:41.61#ibcon#ireg 8 cls_cnt 0 2006.285.12:16:41.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:16:41.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:16:41.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:16:41.68#ibcon#enter wrdev, iclass 34, count 0 2006.285.12:16:41.68#ibcon#first serial, iclass 34, count 0 2006.285.12:16:41.68#ibcon#enter sib2, iclass 34, count 0 2006.285.12:16:41.68#ibcon#flushed, iclass 34, count 0 2006.285.12:16:41.68#ibcon#about to write, iclass 34, count 0 2006.285.12:16:41.68#ibcon#wrote, iclass 34, count 0 2006.285.12:16:41.68#ibcon#about to read 3, iclass 34, count 0 2006.285.12:16:41.70#ibcon#read 3, iclass 34, count 0 2006.285.12:16:41.70#ibcon#about to read 4, iclass 34, count 0 2006.285.12:16:41.70#ibcon#read 4, iclass 34, count 0 2006.285.12:16:41.70#ibcon#about to read 5, iclass 34, count 0 2006.285.12:16:41.70#ibcon#read 5, iclass 34, count 0 2006.285.12:16:41.70#ibcon#about to read 6, iclass 34, count 0 2006.285.12:16:41.70#ibcon#read 6, iclass 34, count 0 2006.285.12:16:41.70#ibcon#end of sib2, iclass 34, count 0 2006.285.12:16:41.70#ibcon#*mode == 0, iclass 34, count 0 2006.285.12:16:41.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.12:16:41.70#ibcon#[27=BW32\r\n] 2006.285.12:16:41.70#ibcon#*before write, iclass 34, count 0 2006.285.12:16:41.70#ibcon#enter sib2, iclass 34, count 0 2006.285.12:16:41.70#ibcon#flushed, iclass 34, count 0 2006.285.12:16:41.70#ibcon#about to write, iclass 34, count 0 2006.285.12:16:41.70#ibcon#wrote, iclass 34, count 0 2006.285.12:16:41.70#ibcon#about to read 3, iclass 34, count 0 2006.285.12:16:41.73#ibcon#read 3, iclass 34, count 0 2006.285.12:16:41.73#ibcon#about to read 4, iclass 34, count 0 2006.285.12:16:41.73#ibcon#read 4, iclass 34, count 0 2006.285.12:16:41.73#ibcon#about to read 5, iclass 34, count 0 2006.285.12:16:41.73#ibcon#read 5, iclass 34, count 0 2006.285.12:16:41.73#ibcon#about to read 6, iclass 34, count 0 2006.285.12:16:41.73#ibcon#read 6, iclass 34, count 0 2006.285.12:16:41.73#ibcon#end of sib2, iclass 34, count 0 2006.285.12:16:41.73#ibcon#*after write, iclass 34, count 0 2006.285.12:16:41.73#ibcon#*before return 0, iclass 34, count 0 2006.285.12:16:41.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:16:41.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:16:41.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.12:16:41.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.12:16:41.73$setupk4/ifdk4 2006.285.12:16:41.73$ifdk4/lo= 2006.285.12:16:41.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.12:16:41.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.12:16:41.73$ifdk4/patch= 2006.285.12:16:41.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.12:16:41.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.12:16:41.73$setupk4/!*+20s 2006.285.12:16:50.44#abcon#<5=/04 1.1 1.7 18.95 951015.5\r\n> 2006.285.12:16:50.46#abcon#{5=INTERFACE CLEAR} 2006.285.12:16:50.52#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:16:56.23$setupk4/"tpicd 2006.285.12:16:56.23$setupk4/echo=off 2006.285.12:16:56.23$setupk4/xlog=off 2006.285.12:16:56.23:!2006.285.12:19:01 2006.285.12:16:57.14#trakl#Source acquired 2006.285.12:16:57.14#flagr#flagr/antenna,acquired 2006.285.12:19:01.00:preob 2006.285.12:19:01.14/onsource/TRACKING 2006.285.12:19:01.14:!2006.285.12:19:11 2006.285.12:19:11.00:"tape 2006.285.12:19:11.00:"st=record 2006.285.12:19:11.00:data_valid=on 2006.285.12:19:11.00:midob 2006.285.12:19:12.14/onsource/TRACKING 2006.285.12:19:12.14/wx/18.92,1015.5,95 2006.285.12:19:12.23/cable/+6.4935E-03 2006.285.12:19:13.32/va/01,07,usb,yes,31,34 2006.285.12:19:13.32/va/02,06,usb,yes,31,32 2006.285.12:19:13.32/va/03,07,usb,yes,31,33 2006.285.12:19:13.32/va/04,06,usb,yes,32,34 2006.285.12:19:13.32/va/05,03,usb,yes,32,32 2006.285.12:19:13.32/va/06,04,usb,yes,29,28 2006.285.12:19:13.32/va/07,04,usb,yes,29,30 2006.285.12:19:13.32/va/08,03,usb,yes,30,36 2006.285.12:19:13.55/valo/01,524.99,yes,locked 2006.285.12:19:13.55/valo/02,534.99,yes,locked 2006.285.12:19:13.55/valo/03,564.99,yes,locked 2006.285.12:19:13.55/valo/04,624.99,yes,locked 2006.285.12:19:13.55/valo/05,734.99,yes,locked 2006.285.12:19:13.55/valo/06,814.99,yes,locked 2006.285.12:19:13.55/valo/07,864.99,yes,locked 2006.285.12:19:13.55/valo/08,884.99,yes,locked 2006.285.12:19:14.64/vb/01,04,usb,yes,30,28 2006.285.12:19:14.64/vb/02,05,usb,yes,28,28 2006.285.12:19:14.64/vb/03,04,usb,yes,29,32 2006.285.12:19:14.64/vb/04,05,usb,yes,29,28 2006.285.12:19:14.64/vb/05,04,usb,yes,26,28 2006.285.12:19:14.64/vb/06,03,usb,yes,37,33 2006.285.12:19:14.64/vb/07,04,usb,yes,30,30 2006.285.12:19:14.64/vb/08,04,usb,yes,27,31 2006.285.12:19:14.87/vblo/01,629.99,yes,locked 2006.285.12:19:14.87/vblo/02,634.99,yes,locked 2006.285.12:19:14.87/vblo/03,649.99,yes,locked 2006.285.12:19:14.87/vblo/04,679.99,yes,locked 2006.285.12:19:14.87/vblo/05,709.99,yes,locked 2006.285.12:19:14.87/vblo/06,719.99,yes,locked 2006.285.12:19:14.87/vblo/07,734.99,yes,locked 2006.285.12:19:14.87/vblo/08,744.99,yes,locked 2006.285.12:19:15.02/vabw/8 2006.285.12:19:15.17/vbbw/8 2006.285.12:19:15.26/xfe/off,on,12.2 2006.285.12:19:15.66/ifatt/23,28,28,28 2006.285.12:19:16.08/fmout-gps/S +2.47E-07 2006.285.12:19:16.10:!2006.285.12:21:51 2006.285.12:21:51.02:data_valid=off 2006.285.12:21:51.02:"et 2006.285.12:21:51.02:!+3s 2006.285.12:21:54.04:"tape 2006.285.12:21:54.05:postob 2006.285.12:21:54.15/cable/+6.4947E-03 2006.285.12:21:54.15/wx/18.84,1015.5,95 2006.285.12:21:54.21/fmout-gps/S +2.54E-07 2006.285.12:21:54.21:scan_name=285-1227,jd0610,80 2006.285.12:21:54.21:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.285.12:21:56.14#flagr#flagr/antenna,new-source 2006.285.12:21:56.14:checkk5 2006.285.12:21:56.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.12:21:56.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.12:21:57.33/chk_autoobs//k5ts3/ autoobs is running! 2006.285.12:21:57.67/chk_autoobs//k5ts4/ autoobs is running! 2006.285.12:21:58.15/chk_obsdata//k5ts1/T2851219??a.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.12:21:58.60/chk_obsdata//k5ts2/T2851219??b.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.12:21:58.98/chk_obsdata//k5ts3/T2851219??c.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.12:21:59.39/chk_obsdata//k5ts4/T2851219??d.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.12:22:00.23/k5log//k5ts1_log_newline 2006.285.12:22:01.01/k5log//k5ts2_log_newline 2006.285.12:22:01.77/k5log//k5ts3_log_newline 2006.285.12:22:02.59/k5log//k5ts4_log_newline 2006.285.12:22:02.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.12:22:02.61:setupk4=1 2006.285.12:22:02.61$setupk4/echo=on 2006.285.12:22:02.61$setupk4/pcalon 2006.285.12:22:02.61$pcalon/"no phase cal control is implemented here 2006.285.12:22:02.61$setupk4/"tpicd=stop 2006.285.12:22:02.61$setupk4/"rec=synch_on 2006.285.12:22:02.61$setupk4/"rec_mode=128 2006.285.12:22:02.61$setupk4/!* 2006.285.12:22:02.61$setupk4/recpk4 2006.285.12:22:02.61$recpk4/recpatch= 2006.285.12:22:02.61$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.12:22:02.61$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.12:22:02.61$setupk4/vck44 2006.285.12:22:02.61$vck44/valo=1,524.99 2006.285.12:22:02.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.12:22:02.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.12:22:02.61#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:02.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:22:02.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:22:02.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:22:02.61#ibcon#enter wrdev, iclass 19, count 0 2006.285.12:22:02.61#ibcon#first serial, iclass 19, count 0 2006.285.12:22:02.61#ibcon#enter sib2, iclass 19, count 0 2006.285.12:22:02.61#ibcon#flushed, iclass 19, count 0 2006.285.12:22:02.61#ibcon#about to write, iclass 19, count 0 2006.285.12:22:02.61#ibcon#wrote, iclass 19, count 0 2006.285.12:22:02.61#ibcon#about to read 3, iclass 19, count 0 2006.285.12:22:02.62#ibcon#read 3, iclass 19, count 0 2006.285.12:22:02.62#ibcon#about to read 4, iclass 19, count 0 2006.285.12:22:02.62#ibcon#read 4, iclass 19, count 0 2006.285.12:22:02.62#ibcon#about to read 5, iclass 19, count 0 2006.285.12:22:02.62#ibcon#read 5, iclass 19, count 0 2006.285.12:22:02.62#ibcon#about to read 6, iclass 19, count 0 2006.285.12:22:02.62#ibcon#read 6, iclass 19, count 0 2006.285.12:22:02.62#ibcon#end of sib2, iclass 19, count 0 2006.285.12:22:02.62#ibcon#*mode == 0, iclass 19, count 0 2006.285.12:22:02.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.12:22:02.63#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.12:22:02.63#ibcon#*before write, iclass 19, count 0 2006.285.12:22:02.63#ibcon#enter sib2, iclass 19, count 0 2006.285.12:22:02.63#ibcon#flushed, iclass 19, count 0 2006.285.12:22:02.63#ibcon#about to write, iclass 19, count 0 2006.285.12:22:02.63#ibcon#wrote, iclass 19, count 0 2006.285.12:22:02.63#ibcon#about to read 3, iclass 19, count 0 2006.285.12:22:02.67#ibcon#read 3, iclass 19, count 0 2006.285.12:22:02.67#ibcon#about to read 4, iclass 19, count 0 2006.285.12:22:02.67#ibcon#read 4, iclass 19, count 0 2006.285.12:22:02.67#ibcon#about to read 5, iclass 19, count 0 2006.285.12:22:02.67#ibcon#read 5, iclass 19, count 0 2006.285.12:22:02.67#ibcon#about to read 6, iclass 19, count 0 2006.285.12:22:02.67#ibcon#read 6, iclass 19, count 0 2006.285.12:22:02.67#ibcon#end of sib2, iclass 19, count 0 2006.285.12:22:02.67#ibcon#*after write, iclass 19, count 0 2006.285.12:22:02.68#ibcon#*before return 0, iclass 19, count 0 2006.285.12:22:02.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:22:02.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:22:02.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.12:22:02.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.12:22:02.68$vck44/va=1,7 2006.285.12:22:02.68#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.12:22:02.68#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.12:22:02.68#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:02.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:22:02.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:22:02.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:22:02.68#ibcon#enter wrdev, iclass 21, count 2 2006.285.12:22:02.68#ibcon#first serial, iclass 21, count 2 2006.285.12:22:02.68#ibcon#enter sib2, iclass 21, count 2 2006.285.12:22:02.68#ibcon#flushed, iclass 21, count 2 2006.285.12:22:02.68#ibcon#about to write, iclass 21, count 2 2006.285.12:22:02.68#ibcon#wrote, iclass 21, count 2 2006.285.12:22:02.68#ibcon#about to read 3, iclass 21, count 2 2006.285.12:22:02.69#ibcon#read 3, iclass 21, count 2 2006.285.12:22:02.69#ibcon#about to read 4, iclass 21, count 2 2006.285.12:22:02.69#ibcon#read 4, iclass 21, count 2 2006.285.12:22:02.69#ibcon#about to read 5, iclass 21, count 2 2006.285.12:22:02.69#ibcon#read 5, iclass 21, count 2 2006.285.12:22:02.69#ibcon#about to read 6, iclass 21, count 2 2006.285.12:22:02.69#ibcon#read 6, iclass 21, count 2 2006.285.12:22:02.69#ibcon#end of sib2, iclass 21, count 2 2006.285.12:22:02.69#ibcon#*mode == 0, iclass 21, count 2 2006.285.12:22:02.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.12:22:02.70#ibcon#[25=AT01-07\r\n] 2006.285.12:22:02.70#ibcon#*before write, iclass 21, count 2 2006.285.12:22:02.70#ibcon#enter sib2, iclass 21, count 2 2006.285.12:22:02.70#ibcon#flushed, iclass 21, count 2 2006.285.12:22:02.70#ibcon#about to write, iclass 21, count 2 2006.285.12:22:02.70#ibcon#wrote, iclass 21, count 2 2006.285.12:22:02.70#ibcon#about to read 3, iclass 21, count 2 2006.285.12:22:02.72#ibcon#read 3, iclass 21, count 2 2006.285.12:22:02.72#ibcon#about to read 4, iclass 21, count 2 2006.285.12:22:02.72#ibcon#read 4, iclass 21, count 2 2006.285.12:22:02.72#ibcon#about to read 5, iclass 21, count 2 2006.285.12:22:02.72#ibcon#read 5, iclass 21, count 2 2006.285.12:22:02.72#ibcon#about to read 6, iclass 21, count 2 2006.285.12:22:02.72#ibcon#read 6, iclass 21, count 2 2006.285.12:22:02.72#ibcon#end of sib2, iclass 21, count 2 2006.285.12:22:02.72#ibcon#*after write, iclass 21, count 2 2006.285.12:22:02.72#ibcon#*before return 0, iclass 21, count 2 2006.285.12:22:02.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:22:02.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:22:02.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.12:22:02.73#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:02.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:22:02.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:22:02.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:22:02.84#ibcon#enter wrdev, iclass 21, count 0 2006.285.12:22:02.84#ibcon#first serial, iclass 21, count 0 2006.285.12:22:02.84#ibcon#enter sib2, iclass 21, count 0 2006.285.12:22:02.84#ibcon#flushed, iclass 21, count 0 2006.285.12:22:02.84#ibcon#about to write, iclass 21, count 0 2006.285.12:22:02.84#ibcon#wrote, iclass 21, count 0 2006.285.12:22:02.84#ibcon#about to read 3, iclass 21, count 0 2006.285.12:22:02.86#ibcon#read 3, iclass 21, count 0 2006.285.12:22:02.86#ibcon#about to read 4, iclass 21, count 0 2006.285.12:22:02.86#ibcon#read 4, iclass 21, count 0 2006.285.12:22:02.86#ibcon#about to read 5, iclass 21, count 0 2006.285.12:22:02.86#ibcon#read 5, iclass 21, count 0 2006.285.12:22:02.86#ibcon#about to read 6, iclass 21, count 0 2006.285.12:22:02.86#ibcon#read 6, iclass 21, count 0 2006.285.12:22:02.86#ibcon#end of sib2, iclass 21, count 0 2006.285.12:22:02.86#ibcon#*mode == 0, iclass 21, count 0 2006.285.12:22:02.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.12:22:02.87#ibcon#[25=USB\r\n] 2006.285.12:22:02.87#ibcon#*before write, iclass 21, count 0 2006.285.12:22:02.87#ibcon#enter sib2, iclass 21, count 0 2006.285.12:22:02.87#ibcon#flushed, iclass 21, count 0 2006.285.12:22:02.87#ibcon#about to write, iclass 21, count 0 2006.285.12:22:02.87#ibcon#wrote, iclass 21, count 0 2006.285.12:22:02.87#ibcon#about to read 3, iclass 21, count 0 2006.285.12:22:02.89#ibcon#read 3, iclass 21, count 0 2006.285.12:22:02.89#ibcon#about to read 4, iclass 21, count 0 2006.285.12:22:02.89#ibcon#read 4, iclass 21, count 0 2006.285.12:22:02.89#ibcon#about to read 5, iclass 21, count 0 2006.285.12:22:02.89#ibcon#read 5, iclass 21, count 0 2006.285.12:22:02.89#ibcon#about to read 6, iclass 21, count 0 2006.285.12:22:02.89#ibcon#read 6, iclass 21, count 0 2006.285.12:22:02.89#ibcon#end of sib2, iclass 21, count 0 2006.285.12:22:02.89#ibcon#*after write, iclass 21, count 0 2006.285.12:22:02.89#ibcon#*before return 0, iclass 21, count 0 2006.285.12:22:02.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:22:02.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:22:02.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.12:22:02.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.12:22:02.90$vck44/valo=2,534.99 2006.285.12:22:02.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.12:22:02.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.12:22:02.90#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:02.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:22:02.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:22:02.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:22:02.90#ibcon#enter wrdev, iclass 23, count 0 2006.285.12:22:02.90#ibcon#first serial, iclass 23, count 0 2006.285.12:22:02.90#ibcon#enter sib2, iclass 23, count 0 2006.285.12:22:02.90#ibcon#flushed, iclass 23, count 0 2006.285.12:22:02.90#ibcon#about to write, iclass 23, count 0 2006.285.12:22:02.90#ibcon#wrote, iclass 23, count 0 2006.285.12:22:02.90#ibcon#about to read 3, iclass 23, count 0 2006.285.12:22:02.91#ibcon#read 3, iclass 23, count 0 2006.285.12:22:02.91#ibcon#about to read 4, iclass 23, count 0 2006.285.12:22:02.91#ibcon#read 4, iclass 23, count 0 2006.285.12:22:02.91#ibcon#about to read 5, iclass 23, count 0 2006.285.12:22:02.91#ibcon#read 5, iclass 23, count 0 2006.285.12:22:02.91#ibcon#about to read 6, iclass 23, count 0 2006.285.12:22:02.91#ibcon#read 6, iclass 23, count 0 2006.285.12:22:02.91#ibcon#end of sib2, iclass 23, count 0 2006.285.12:22:02.91#ibcon#*mode == 0, iclass 23, count 0 2006.285.12:22:02.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.12:22:02.92#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.12:22:02.92#ibcon#*before write, iclass 23, count 0 2006.285.12:22:02.92#ibcon#enter sib2, iclass 23, count 0 2006.285.12:22:02.92#ibcon#flushed, iclass 23, count 0 2006.285.12:22:02.92#ibcon#about to write, iclass 23, count 0 2006.285.12:22:02.92#ibcon#wrote, iclass 23, count 0 2006.285.12:22:02.92#ibcon#about to read 3, iclass 23, count 0 2006.285.12:22:02.95#ibcon#read 3, iclass 23, count 0 2006.285.12:22:02.95#ibcon#about to read 4, iclass 23, count 0 2006.285.12:22:02.95#ibcon#read 4, iclass 23, count 0 2006.285.12:22:02.95#ibcon#about to read 5, iclass 23, count 0 2006.285.12:22:02.95#ibcon#read 5, iclass 23, count 0 2006.285.12:22:02.95#ibcon#about to read 6, iclass 23, count 0 2006.285.12:22:02.95#ibcon#read 6, iclass 23, count 0 2006.285.12:22:02.95#ibcon#end of sib2, iclass 23, count 0 2006.285.12:22:02.95#ibcon#*after write, iclass 23, count 0 2006.285.12:22:02.95#ibcon#*before return 0, iclass 23, count 0 2006.285.12:22:02.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:22:02.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:22:02.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.12:22:02.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.12:22:02.96$vck44/va=2,6 2006.285.12:22:02.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.12:22:02.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.12:22:02.96#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:02.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:22:03.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:22:03.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:22:03.01#ibcon#enter wrdev, iclass 25, count 2 2006.285.12:22:03.01#ibcon#first serial, iclass 25, count 2 2006.285.12:22:03.01#ibcon#enter sib2, iclass 25, count 2 2006.285.12:22:03.02#ibcon#flushed, iclass 25, count 2 2006.285.12:22:03.02#ibcon#about to write, iclass 25, count 2 2006.285.12:22:03.02#ibcon#wrote, iclass 25, count 2 2006.285.12:22:03.02#ibcon#about to read 3, iclass 25, count 2 2006.285.12:22:03.03#ibcon#read 3, iclass 25, count 2 2006.285.12:22:03.03#ibcon#about to read 4, iclass 25, count 2 2006.285.12:22:03.03#ibcon#read 4, iclass 25, count 2 2006.285.12:22:03.03#ibcon#about to read 5, iclass 25, count 2 2006.285.12:22:03.03#ibcon#read 5, iclass 25, count 2 2006.285.12:22:03.03#ibcon#about to read 6, iclass 25, count 2 2006.285.12:22:03.03#ibcon#read 6, iclass 25, count 2 2006.285.12:22:03.03#ibcon#end of sib2, iclass 25, count 2 2006.285.12:22:03.03#ibcon#*mode == 0, iclass 25, count 2 2006.285.12:22:03.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.12:22:03.04#ibcon#[25=AT02-06\r\n] 2006.285.12:22:03.04#ibcon#*before write, iclass 25, count 2 2006.285.12:22:03.04#ibcon#enter sib2, iclass 25, count 2 2006.285.12:22:03.04#ibcon#flushed, iclass 25, count 2 2006.285.12:22:03.04#ibcon#about to write, iclass 25, count 2 2006.285.12:22:03.04#ibcon#wrote, iclass 25, count 2 2006.285.12:22:03.04#ibcon#about to read 3, iclass 25, count 2 2006.285.12:22:03.06#ibcon#read 3, iclass 25, count 2 2006.285.12:22:03.06#ibcon#about to read 4, iclass 25, count 2 2006.285.12:22:03.06#ibcon#read 4, iclass 25, count 2 2006.285.12:22:03.06#ibcon#about to read 5, iclass 25, count 2 2006.285.12:22:03.06#ibcon#read 5, iclass 25, count 2 2006.285.12:22:03.06#ibcon#about to read 6, iclass 25, count 2 2006.285.12:22:03.06#ibcon#read 6, iclass 25, count 2 2006.285.12:22:03.06#ibcon#end of sib2, iclass 25, count 2 2006.285.12:22:03.07#ibcon#*after write, iclass 25, count 2 2006.285.12:22:03.07#ibcon#*before return 0, iclass 25, count 2 2006.285.12:22:03.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:22:03.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:22:03.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.12:22:03.07#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:03.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:22:03.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:22:03.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:22:03.18#ibcon#enter wrdev, iclass 25, count 0 2006.285.12:22:03.18#ibcon#first serial, iclass 25, count 0 2006.285.12:22:03.18#ibcon#enter sib2, iclass 25, count 0 2006.285.12:22:03.18#ibcon#flushed, iclass 25, count 0 2006.285.12:22:03.18#ibcon#about to write, iclass 25, count 0 2006.285.12:22:03.18#ibcon#wrote, iclass 25, count 0 2006.285.12:22:03.18#ibcon#about to read 3, iclass 25, count 0 2006.285.12:22:03.20#ibcon#read 3, iclass 25, count 0 2006.285.12:22:03.20#ibcon#about to read 4, iclass 25, count 0 2006.285.12:22:03.20#ibcon#read 4, iclass 25, count 0 2006.285.12:22:03.20#ibcon#about to read 5, iclass 25, count 0 2006.285.12:22:03.20#ibcon#read 5, iclass 25, count 0 2006.285.12:22:03.20#ibcon#about to read 6, iclass 25, count 0 2006.285.12:22:03.20#ibcon#read 6, iclass 25, count 0 2006.285.12:22:03.20#ibcon#end of sib2, iclass 25, count 0 2006.285.12:22:03.21#ibcon#*mode == 0, iclass 25, count 0 2006.285.12:22:03.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.12:22:03.21#ibcon#[25=USB\r\n] 2006.285.12:22:03.21#ibcon#*before write, iclass 25, count 0 2006.285.12:22:03.21#ibcon#enter sib2, iclass 25, count 0 2006.285.12:22:03.21#ibcon#flushed, iclass 25, count 0 2006.285.12:22:03.21#ibcon#about to write, iclass 25, count 0 2006.285.12:22:03.21#ibcon#wrote, iclass 25, count 0 2006.285.12:22:03.21#ibcon#about to read 3, iclass 25, count 0 2006.285.12:22:03.23#ibcon#read 3, iclass 25, count 0 2006.285.12:22:03.23#ibcon#about to read 4, iclass 25, count 0 2006.285.12:22:03.23#ibcon#read 4, iclass 25, count 0 2006.285.12:22:03.23#ibcon#about to read 5, iclass 25, count 0 2006.285.12:22:03.23#ibcon#read 5, iclass 25, count 0 2006.285.12:22:03.23#ibcon#about to read 6, iclass 25, count 0 2006.285.12:22:03.23#ibcon#read 6, iclass 25, count 0 2006.285.12:22:03.23#ibcon#end of sib2, iclass 25, count 0 2006.285.12:22:03.23#ibcon#*after write, iclass 25, count 0 2006.285.12:22:03.23#ibcon#*before return 0, iclass 25, count 0 2006.285.12:22:03.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:22:03.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:22:03.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.12:22:03.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.12:22:03.24$vck44/valo=3,564.99 2006.285.12:22:03.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.12:22:03.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.12:22:03.24#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:03.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:22:03.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:22:03.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:22:03.24#ibcon#enter wrdev, iclass 27, count 0 2006.285.12:22:03.24#ibcon#first serial, iclass 27, count 0 2006.285.12:22:03.24#ibcon#enter sib2, iclass 27, count 0 2006.285.12:22:03.24#ibcon#flushed, iclass 27, count 0 2006.285.12:22:03.24#ibcon#about to write, iclass 27, count 0 2006.285.12:22:03.24#ibcon#wrote, iclass 27, count 0 2006.285.12:22:03.24#ibcon#about to read 3, iclass 27, count 0 2006.285.12:22:03.25#ibcon#read 3, iclass 27, count 0 2006.285.12:22:03.25#ibcon#about to read 4, iclass 27, count 0 2006.285.12:22:03.25#ibcon#read 4, iclass 27, count 0 2006.285.12:22:03.25#ibcon#about to read 5, iclass 27, count 0 2006.285.12:22:03.25#ibcon#read 5, iclass 27, count 0 2006.285.12:22:03.25#ibcon#about to read 6, iclass 27, count 0 2006.285.12:22:03.25#ibcon#read 6, iclass 27, count 0 2006.285.12:22:03.25#ibcon#end of sib2, iclass 27, count 0 2006.285.12:22:03.25#ibcon#*mode == 0, iclass 27, count 0 2006.285.12:22:03.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.12:22:03.26#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.12:22:03.26#ibcon#*before write, iclass 27, count 0 2006.285.12:22:03.26#ibcon#enter sib2, iclass 27, count 0 2006.285.12:22:03.26#ibcon#flushed, iclass 27, count 0 2006.285.12:22:03.26#ibcon#about to write, iclass 27, count 0 2006.285.12:22:03.26#ibcon#wrote, iclass 27, count 0 2006.285.12:22:03.26#ibcon#about to read 3, iclass 27, count 0 2006.285.12:22:03.29#ibcon#read 3, iclass 27, count 0 2006.285.12:22:03.29#ibcon#about to read 4, iclass 27, count 0 2006.285.12:22:03.29#ibcon#read 4, iclass 27, count 0 2006.285.12:22:03.29#ibcon#about to read 5, iclass 27, count 0 2006.285.12:22:03.29#ibcon#read 5, iclass 27, count 0 2006.285.12:22:03.29#ibcon#about to read 6, iclass 27, count 0 2006.285.12:22:03.29#ibcon#read 6, iclass 27, count 0 2006.285.12:22:03.29#ibcon#end of sib2, iclass 27, count 0 2006.285.12:22:03.29#ibcon#*after write, iclass 27, count 0 2006.285.12:22:03.29#ibcon#*before return 0, iclass 27, count 0 2006.285.12:22:03.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:22:03.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:22:03.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.12:22:03.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.12:22:03.30$vck44/va=3,7 2006.285.12:22:03.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.12:22:03.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.12:22:03.30#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:03.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:22:03.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:22:03.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:22:03.35#ibcon#enter wrdev, iclass 29, count 2 2006.285.12:22:03.35#ibcon#first serial, iclass 29, count 2 2006.285.12:22:03.35#ibcon#enter sib2, iclass 29, count 2 2006.285.12:22:03.35#ibcon#flushed, iclass 29, count 2 2006.285.12:22:03.35#ibcon#about to write, iclass 29, count 2 2006.285.12:22:03.35#ibcon#wrote, iclass 29, count 2 2006.285.12:22:03.35#ibcon#about to read 3, iclass 29, count 2 2006.285.12:22:03.37#ibcon#read 3, iclass 29, count 2 2006.285.12:22:03.37#ibcon#about to read 4, iclass 29, count 2 2006.285.12:22:03.37#ibcon#read 4, iclass 29, count 2 2006.285.12:22:03.37#ibcon#about to read 5, iclass 29, count 2 2006.285.12:22:03.37#ibcon#read 5, iclass 29, count 2 2006.285.12:22:03.37#ibcon#about to read 6, iclass 29, count 2 2006.285.12:22:03.37#ibcon#read 6, iclass 29, count 2 2006.285.12:22:03.37#ibcon#end of sib2, iclass 29, count 2 2006.285.12:22:03.37#ibcon#*mode == 0, iclass 29, count 2 2006.285.12:22:03.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.12:22:03.38#ibcon#[25=AT03-07\r\n] 2006.285.12:22:03.38#ibcon#*before write, iclass 29, count 2 2006.285.12:22:03.38#ibcon#enter sib2, iclass 29, count 2 2006.285.12:22:03.38#ibcon#flushed, iclass 29, count 2 2006.285.12:22:03.38#ibcon#about to write, iclass 29, count 2 2006.285.12:22:03.38#ibcon#wrote, iclass 29, count 2 2006.285.12:22:03.38#ibcon#about to read 3, iclass 29, count 2 2006.285.12:22:03.40#ibcon#read 3, iclass 29, count 2 2006.285.12:22:03.40#ibcon#about to read 4, iclass 29, count 2 2006.285.12:22:03.40#ibcon#read 4, iclass 29, count 2 2006.285.12:22:03.40#ibcon#about to read 5, iclass 29, count 2 2006.285.12:22:03.40#ibcon#read 5, iclass 29, count 2 2006.285.12:22:03.40#ibcon#about to read 6, iclass 29, count 2 2006.285.12:22:03.40#ibcon#read 6, iclass 29, count 2 2006.285.12:22:03.40#ibcon#end of sib2, iclass 29, count 2 2006.285.12:22:03.40#ibcon#*after write, iclass 29, count 2 2006.285.12:22:03.40#ibcon#*before return 0, iclass 29, count 2 2006.285.12:22:03.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:22:03.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:22:03.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.12:22:03.41#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:03.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:22:03.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:22:03.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:22:03.52#ibcon#enter wrdev, iclass 29, count 0 2006.285.12:22:03.52#ibcon#first serial, iclass 29, count 0 2006.285.12:22:03.52#ibcon#enter sib2, iclass 29, count 0 2006.285.12:22:03.53#ibcon#flushed, iclass 29, count 0 2006.285.12:22:03.53#ibcon#about to write, iclass 29, count 0 2006.285.12:22:03.53#ibcon#wrote, iclass 29, count 0 2006.285.12:22:03.53#ibcon#about to read 3, iclass 29, count 0 2006.285.12:22:03.54#ibcon#read 3, iclass 29, count 0 2006.285.12:22:03.54#ibcon#about to read 4, iclass 29, count 0 2006.285.12:22:03.54#ibcon#read 4, iclass 29, count 0 2006.285.12:22:03.54#ibcon#about to read 5, iclass 29, count 0 2006.285.12:22:03.54#ibcon#read 5, iclass 29, count 0 2006.285.12:22:03.54#ibcon#about to read 6, iclass 29, count 0 2006.285.12:22:03.54#ibcon#read 6, iclass 29, count 0 2006.285.12:22:03.54#ibcon#end of sib2, iclass 29, count 0 2006.285.12:22:03.55#ibcon#*mode == 0, iclass 29, count 0 2006.285.12:22:03.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.12:22:03.55#ibcon#[25=USB\r\n] 2006.285.12:22:03.55#ibcon#*before write, iclass 29, count 0 2006.285.12:22:03.55#ibcon#enter sib2, iclass 29, count 0 2006.285.12:22:03.55#ibcon#flushed, iclass 29, count 0 2006.285.12:22:03.55#ibcon#about to write, iclass 29, count 0 2006.285.12:22:03.55#ibcon#wrote, iclass 29, count 0 2006.285.12:22:03.55#ibcon#about to read 3, iclass 29, count 0 2006.285.12:22:03.57#ibcon#read 3, iclass 29, count 0 2006.285.12:22:03.57#ibcon#about to read 4, iclass 29, count 0 2006.285.12:22:03.57#ibcon#read 4, iclass 29, count 0 2006.285.12:22:03.57#ibcon#about to read 5, iclass 29, count 0 2006.285.12:22:03.57#ibcon#read 5, iclass 29, count 0 2006.285.12:22:03.57#ibcon#about to read 6, iclass 29, count 0 2006.285.12:22:03.57#ibcon#read 6, iclass 29, count 0 2006.285.12:22:03.57#ibcon#end of sib2, iclass 29, count 0 2006.285.12:22:03.58#ibcon#*after write, iclass 29, count 0 2006.285.12:22:03.58#ibcon#*before return 0, iclass 29, count 0 2006.285.12:22:03.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:22:03.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:22:03.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.12:22:03.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.12:22:03.58$vck44/valo=4,624.99 2006.285.12:22:03.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.12:22:03.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.12:22:03.58#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:03.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:22:03.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:22:03.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:22:03.58#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:22:03.58#ibcon#first serial, iclass 31, count 0 2006.285.12:22:03.58#ibcon#enter sib2, iclass 31, count 0 2006.285.12:22:03.58#ibcon#flushed, iclass 31, count 0 2006.285.12:22:03.58#ibcon#about to write, iclass 31, count 0 2006.285.12:22:03.58#ibcon#wrote, iclass 31, count 0 2006.285.12:22:03.58#ibcon#about to read 3, iclass 31, count 0 2006.285.12:22:03.59#ibcon#read 3, iclass 31, count 0 2006.285.12:22:03.59#ibcon#about to read 4, iclass 31, count 0 2006.285.12:22:03.59#ibcon#read 4, iclass 31, count 0 2006.285.12:22:03.59#ibcon#about to read 5, iclass 31, count 0 2006.285.12:22:03.59#ibcon#read 5, iclass 31, count 0 2006.285.12:22:03.59#ibcon#about to read 6, iclass 31, count 0 2006.285.12:22:03.59#ibcon#read 6, iclass 31, count 0 2006.285.12:22:03.59#ibcon#end of sib2, iclass 31, count 0 2006.285.12:22:03.60#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:22:03.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:22:03.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.12:22:03.60#ibcon#*before write, iclass 31, count 0 2006.285.12:22:03.60#ibcon#enter sib2, iclass 31, count 0 2006.285.12:22:03.60#ibcon#flushed, iclass 31, count 0 2006.285.12:22:03.60#ibcon#about to write, iclass 31, count 0 2006.285.12:22:03.60#ibcon#wrote, iclass 31, count 0 2006.285.12:22:03.60#ibcon#about to read 3, iclass 31, count 0 2006.285.12:22:03.63#ibcon#read 3, iclass 31, count 0 2006.285.12:22:03.63#ibcon#about to read 4, iclass 31, count 0 2006.285.12:22:03.63#ibcon#read 4, iclass 31, count 0 2006.285.12:22:03.63#ibcon#about to read 5, iclass 31, count 0 2006.285.12:22:03.63#ibcon#read 5, iclass 31, count 0 2006.285.12:22:03.63#ibcon#about to read 6, iclass 31, count 0 2006.285.12:22:03.63#ibcon#read 6, iclass 31, count 0 2006.285.12:22:03.63#ibcon#end of sib2, iclass 31, count 0 2006.285.12:22:03.64#ibcon#*after write, iclass 31, count 0 2006.285.12:22:03.64#ibcon#*before return 0, iclass 31, count 0 2006.285.12:22:03.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:22:03.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:22:03.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:22:03.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:22:03.64$vck44/va=4,6 2006.285.12:22:03.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.12:22:03.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.12:22:03.64#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:03.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:22:03.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:22:03.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:22:03.69#ibcon#enter wrdev, iclass 33, count 2 2006.285.12:22:03.69#ibcon#first serial, iclass 33, count 2 2006.285.12:22:03.69#ibcon#enter sib2, iclass 33, count 2 2006.285.12:22:03.69#ibcon#flushed, iclass 33, count 2 2006.285.12:22:03.69#ibcon#about to write, iclass 33, count 2 2006.285.12:22:03.69#ibcon#wrote, iclass 33, count 2 2006.285.12:22:03.70#ibcon#about to read 3, iclass 33, count 2 2006.285.12:22:03.71#ibcon#read 3, iclass 33, count 2 2006.285.12:22:03.71#ibcon#about to read 4, iclass 33, count 2 2006.285.12:22:03.71#ibcon#read 4, iclass 33, count 2 2006.285.12:22:03.71#ibcon#about to read 5, iclass 33, count 2 2006.285.12:22:03.71#ibcon#read 5, iclass 33, count 2 2006.285.12:22:03.71#ibcon#about to read 6, iclass 33, count 2 2006.285.12:22:03.71#ibcon#read 6, iclass 33, count 2 2006.285.12:22:03.71#ibcon#end of sib2, iclass 33, count 2 2006.285.12:22:03.71#ibcon#*mode == 0, iclass 33, count 2 2006.285.12:22:03.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.12:22:03.72#ibcon#[25=AT04-06\r\n] 2006.285.12:22:03.72#ibcon#*before write, iclass 33, count 2 2006.285.12:22:03.72#ibcon#enter sib2, iclass 33, count 2 2006.285.12:22:03.72#ibcon#flushed, iclass 33, count 2 2006.285.12:22:03.72#ibcon#about to write, iclass 33, count 2 2006.285.12:22:03.72#ibcon#wrote, iclass 33, count 2 2006.285.12:22:03.72#ibcon#about to read 3, iclass 33, count 2 2006.285.12:22:03.74#ibcon#read 3, iclass 33, count 2 2006.285.12:22:03.74#ibcon#about to read 4, iclass 33, count 2 2006.285.12:22:03.74#ibcon#read 4, iclass 33, count 2 2006.285.12:22:03.74#ibcon#about to read 5, iclass 33, count 2 2006.285.12:22:03.74#ibcon#read 5, iclass 33, count 2 2006.285.12:22:03.74#ibcon#about to read 6, iclass 33, count 2 2006.285.12:22:03.74#ibcon#read 6, iclass 33, count 2 2006.285.12:22:03.74#ibcon#end of sib2, iclass 33, count 2 2006.285.12:22:03.74#ibcon#*after write, iclass 33, count 2 2006.285.12:22:03.74#ibcon#*before return 0, iclass 33, count 2 2006.285.12:22:03.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:22:03.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:22:03.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.12:22:03.75#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:03.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:22:03.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:22:03.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:22:03.86#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:22:03.86#ibcon#first serial, iclass 33, count 0 2006.285.12:22:03.86#ibcon#enter sib2, iclass 33, count 0 2006.285.12:22:03.86#ibcon#flushed, iclass 33, count 0 2006.285.12:22:03.86#ibcon#about to write, iclass 33, count 0 2006.285.12:22:03.86#ibcon#wrote, iclass 33, count 0 2006.285.12:22:03.86#ibcon#about to read 3, iclass 33, count 0 2006.285.12:22:03.88#ibcon#read 3, iclass 33, count 0 2006.285.12:22:03.88#ibcon#about to read 4, iclass 33, count 0 2006.285.12:22:03.88#ibcon#read 4, iclass 33, count 0 2006.285.12:22:03.88#ibcon#about to read 5, iclass 33, count 0 2006.285.12:22:03.88#ibcon#read 5, iclass 33, count 0 2006.285.12:22:03.88#ibcon#about to read 6, iclass 33, count 0 2006.285.12:22:03.88#ibcon#read 6, iclass 33, count 0 2006.285.12:22:03.88#ibcon#end of sib2, iclass 33, count 0 2006.285.12:22:03.88#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:22:03.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:22:03.89#ibcon#[25=USB\r\n] 2006.285.12:22:03.89#ibcon#*before write, iclass 33, count 0 2006.285.12:22:03.89#ibcon#enter sib2, iclass 33, count 0 2006.285.12:22:03.89#ibcon#flushed, iclass 33, count 0 2006.285.12:22:03.89#ibcon#about to write, iclass 33, count 0 2006.285.12:22:03.89#ibcon#wrote, iclass 33, count 0 2006.285.12:22:03.89#ibcon#about to read 3, iclass 33, count 0 2006.285.12:22:03.91#ibcon#read 3, iclass 33, count 0 2006.285.12:22:03.91#ibcon#about to read 4, iclass 33, count 0 2006.285.12:22:03.91#ibcon#read 4, iclass 33, count 0 2006.285.12:22:03.91#ibcon#about to read 5, iclass 33, count 0 2006.285.12:22:03.91#ibcon#read 5, iclass 33, count 0 2006.285.12:22:03.91#ibcon#about to read 6, iclass 33, count 0 2006.285.12:22:03.91#ibcon#read 6, iclass 33, count 0 2006.285.12:22:03.91#ibcon#end of sib2, iclass 33, count 0 2006.285.12:22:03.91#ibcon#*after write, iclass 33, count 0 2006.285.12:22:03.91#ibcon#*before return 0, iclass 33, count 0 2006.285.12:22:03.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:22:03.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:22:03.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:22:03.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:22:03.92$vck44/valo=5,734.99 2006.285.12:22:03.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.12:22:03.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.12:22:03.92#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:03.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:22:03.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:22:03.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:22:03.92#ibcon#enter wrdev, iclass 35, count 0 2006.285.12:22:03.92#ibcon#first serial, iclass 35, count 0 2006.285.12:22:03.92#ibcon#enter sib2, iclass 35, count 0 2006.285.12:22:03.92#ibcon#flushed, iclass 35, count 0 2006.285.12:22:03.92#ibcon#about to write, iclass 35, count 0 2006.285.12:22:03.92#ibcon#wrote, iclass 35, count 0 2006.285.12:22:03.92#ibcon#about to read 3, iclass 35, count 0 2006.285.12:22:03.93#ibcon#read 3, iclass 35, count 0 2006.285.12:22:03.93#ibcon#about to read 4, iclass 35, count 0 2006.285.12:22:03.93#ibcon#read 4, iclass 35, count 0 2006.285.12:22:03.93#ibcon#about to read 5, iclass 35, count 0 2006.285.12:22:03.93#ibcon#read 5, iclass 35, count 0 2006.285.12:22:03.93#ibcon#about to read 6, iclass 35, count 0 2006.285.12:22:03.93#ibcon#read 6, iclass 35, count 0 2006.285.12:22:03.93#ibcon#end of sib2, iclass 35, count 0 2006.285.12:22:03.93#ibcon#*mode == 0, iclass 35, count 0 2006.285.12:22:03.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.12:22:03.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.12:22:03.94#ibcon#*before write, iclass 35, count 0 2006.285.12:22:03.94#ibcon#enter sib2, iclass 35, count 0 2006.285.12:22:03.94#ibcon#flushed, iclass 35, count 0 2006.285.12:22:03.94#ibcon#about to write, iclass 35, count 0 2006.285.12:22:03.94#ibcon#wrote, iclass 35, count 0 2006.285.12:22:03.94#ibcon#about to read 3, iclass 35, count 0 2006.285.12:22:03.97#ibcon#read 3, iclass 35, count 0 2006.285.12:22:03.97#ibcon#about to read 4, iclass 35, count 0 2006.285.12:22:03.97#ibcon#read 4, iclass 35, count 0 2006.285.12:22:03.97#ibcon#about to read 5, iclass 35, count 0 2006.285.12:22:03.97#ibcon#read 5, iclass 35, count 0 2006.285.12:22:03.97#ibcon#about to read 6, iclass 35, count 0 2006.285.12:22:03.97#ibcon#read 6, iclass 35, count 0 2006.285.12:22:03.97#ibcon#end of sib2, iclass 35, count 0 2006.285.12:22:03.97#ibcon#*after write, iclass 35, count 0 2006.285.12:22:03.97#ibcon#*before return 0, iclass 35, count 0 2006.285.12:22:03.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:22:03.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:22:03.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.12:22:03.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.12:22:03.98$vck44/va=5,3 2006.285.12:22:03.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.12:22:03.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.12:22:03.98#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:03.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:22:04.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:22:04.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:22:04.03#ibcon#enter wrdev, iclass 37, count 2 2006.285.12:22:04.03#ibcon#first serial, iclass 37, count 2 2006.285.12:22:04.03#ibcon#enter sib2, iclass 37, count 2 2006.285.12:22:04.03#ibcon#flushed, iclass 37, count 2 2006.285.12:22:04.03#ibcon#about to write, iclass 37, count 2 2006.285.12:22:04.03#ibcon#wrote, iclass 37, count 2 2006.285.12:22:04.03#ibcon#about to read 3, iclass 37, count 2 2006.285.12:22:04.05#ibcon#read 3, iclass 37, count 2 2006.285.12:22:04.05#ibcon#about to read 4, iclass 37, count 2 2006.285.12:22:04.05#ibcon#read 4, iclass 37, count 2 2006.285.12:22:04.05#ibcon#about to read 5, iclass 37, count 2 2006.285.12:22:04.05#ibcon#read 5, iclass 37, count 2 2006.285.12:22:04.05#ibcon#about to read 6, iclass 37, count 2 2006.285.12:22:04.05#ibcon#read 6, iclass 37, count 2 2006.285.12:22:04.05#ibcon#end of sib2, iclass 37, count 2 2006.285.12:22:04.05#ibcon#*mode == 0, iclass 37, count 2 2006.285.12:22:04.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.12:22:04.06#ibcon#[25=AT05-03\r\n] 2006.285.12:22:04.06#ibcon#*before write, iclass 37, count 2 2006.285.12:22:04.06#ibcon#enter sib2, iclass 37, count 2 2006.285.12:22:04.06#ibcon#flushed, iclass 37, count 2 2006.285.12:22:04.06#ibcon#about to write, iclass 37, count 2 2006.285.12:22:04.06#ibcon#wrote, iclass 37, count 2 2006.285.12:22:04.06#ibcon#about to read 3, iclass 37, count 2 2006.285.12:22:04.08#ibcon#read 3, iclass 37, count 2 2006.285.12:22:04.08#ibcon#about to read 4, iclass 37, count 2 2006.285.12:22:04.08#ibcon#read 4, iclass 37, count 2 2006.285.12:22:04.08#ibcon#about to read 5, iclass 37, count 2 2006.285.12:22:04.08#ibcon#read 5, iclass 37, count 2 2006.285.12:22:04.08#ibcon#about to read 6, iclass 37, count 2 2006.285.12:22:04.08#ibcon#read 6, iclass 37, count 2 2006.285.12:22:04.08#ibcon#end of sib2, iclass 37, count 2 2006.285.12:22:04.08#ibcon#*after write, iclass 37, count 2 2006.285.12:22:04.09#ibcon#*before return 0, iclass 37, count 2 2006.285.12:22:04.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:22:04.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:22:04.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.12:22:04.09#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:04.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:22:04.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:22:04.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:22:04.20#ibcon#enter wrdev, iclass 37, count 0 2006.285.12:22:04.20#ibcon#first serial, iclass 37, count 0 2006.285.12:22:04.20#ibcon#enter sib2, iclass 37, count 0 2006.285.12:22:04.20#ibcon#flushed, iclass 37, count 0 2006.285.12:22:04.20#ibcon#about to write, iclass 37, count 0 2006.285.12:22:04.21#ibcon#wrote, iclass 37, count 0 2006.285.12:22:04.21#ibcon#about to read 3, iclass 37, count 0 2006.285.12:22:04.22#ibcon#read 3, iclass 37, count 0 2006.285.12:22:04.22#ibcon#about to read 4, iclass 37, count 0 2006.285.12:22:04.22#ibcon#read 4, iclass 37, count 0 2006.285.12:22:04.22#ibcon#about to read 5, iclass 37, count 0 2006.285.12:22:04.22#ibcon#read 5, iclass 37, count 0 2006.285.12:22:04.22#ibcon#about to read 6, iclass 37, count 0 2006.285.12:22:04.22#ibcon#read 6, iclass 37, count 0 2006.285.12:22:04.22#ibcon#end of sib2, iclass 37, count 0 2006.285.12:22:04.22#ibcon#*mode == 0, iclass 37, count 0 2006.285.12:22:04.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.12:22:04.23#ibcon#[25=USB\r\n] 2006.285.12:22:04.23#ibcon#*before write, iclass 37, count 0 2006.285.12:22:04.23#ibcon#enter sib2, iclass 37, count 0 2006.285.12:22:04.23#ibcon#flushed, iclass 37, count 0 2006.285.12:22:04.23#ibcon#about to write, iclass 37, count 0 2006.285.12:22:04.23#ibcon#wrote, iclass 37, count 0 2006.285.12:22:04.23#ibcon#about to read 3, iclass 37, count 0 2006.285.12:22:04.25#ibcon#read 3, iclass 37, count 0 2006.285.12:22:04.25#ibcon#about to read 4, iclass 37, count 0 2006.285.12:22:04.25#ibcon#read 4, iclass 37, count 0 2006.285.12:22:04.25#ibcon#about to read 5, iclass 37, count 0 2006.285.12:22:04.25#ibcon#read 5, iclass 37, count 0 2006.285.12:22:04.25#ibcon#about to read 6, iclass 37, count 0 2006.285.12:22:04.25#ibcon#read 6, iclass 37, count 0 2006.285.12:22:04.25#ibcon#end of sib2, iclass 37, count 0 2006.285.12:22:04.25#ibcon#*after write, iclass 37, count 0 2006.285.12:22:04.25#ibcon#*before return 0, iclass 37, count 0 2006.285.12:22:04.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:22:04.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:22:04.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.12:22:04.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.12:22:04.26$vck44/valo=6,814.99 2006.285.12:22:04.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.12:22:04.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.12:22:04.26#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:04.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:22:04.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:22:04.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:22:04.26#ibcon#enter wrdev, iclass 39, count 0 2006.285.12:22:04.26#ibcon#first serial, iclass 39, count 0 2006.285.12:22:04.26#ibcon#enter sib2, iclass 39, count 0 2006.285.12:22:04.26#ibcon#flushed, iclass 39, count 0 2006.285.12:22:04.26#ibcon#about to write, iclass 39, count 0 2006.285.12:22:04.26#ibcon#wrote, iclass 39, count 0 2006.285.12:22:04.26#ibcon#about to read 3, iclass 39, count 0 2006.285.12:22:04.27#ibcon#read 3, iclass 39, count 0 2006.285.12:22:04.27#ibcon#about to read 4, iclass 39, count 0 2006.285.12:22:04.27#ibcon#read 4, iclass 39, count 0 2006.285.12:22:04.27#ibcon#about to read 5, iclass 39, count 0 2006.285.12:22:04.27#ibcon#read 5, iclass 39, count 0 2006.285.12:22:04.27#ibcon#about to read 6, iclass 39, count 0 2006.285.12:22:04.27#ibcon#read 6, iclass 39, count 0 2006.285.12:22:04.27#ibcon#end of sib2, iclass 39, count 0 2006.285.12:22:04.27#ibcon#*mode == 0, iclass 39, count 0 2006.285.12:22:04.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.12:22:04.28#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.12:22:04.28#ibcon#*before write, iclass 39, count 0 2006.285.12:22:04.28#ibcon#enter sib2, iclass 39, count 0 2006.285.12:22:04.28#ibcon#flushed, iclass 39, count 0 2006.285.12:22:04.28#ibcon#about to write, iclass 39, count 0 2006.285.12:22:04.28#ibcon#wrote, iclass 39, count 0 2006.285.12:22:04.28#ibcon#about to read 3, iclass 39, count 0 2006.285.12:22:04.31#ibcon#read 3, iclass 39, count 0 2006.285.12:22:04.31#ibcon#about to read 4, iclass 39, count 0 2006.285.12:22:04.31#ibcon#read 4, iclass 39, count 0 2006.285.12:22:04.31#ibcon#about to read 5, iclass 39, count 0 2006.285.12:22:04.31#ibcon#read 5, iclass 39, count 0 2006.285.12:22:04.31#ibcon#about to read 6, iclass 39, count 0 2006.285.12:22:04.31#ibcon#read 6, iclass 39, count 0 2006.285.12:22:04.31#ibcon#end of sib2, iclass 39, count 0 2006.285.12:22:04.31#ibcon#*after write, iclass 39, count 0 2006.285.12:22:04.31#ibcon#*before return 0, iclass 39, count 0 2006.285.12:22:04.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:22:04.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:22:04.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.12:22:04.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.12:22:04.32$vck44/va=6,4 2006.285.12:22:04.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.12:22:04.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.12:22:04.32#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:04.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:22:04.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:22:04.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:22:04.37#ibcon#enter wrdev, iclass 3, count 2 2006.285.12:22:04.37#ibcon#first serial, iclass 3, count 2 2006.285.12:22:04.37#ibcon#enter sib2, iclass 3, count 2 2006.285.12:22:04.37#ibcon#flushed, iclass 3, count 2 2006.285.12:22:04.37#ibcon#about to write, iclass 3, count 2 2006.285.12:22:04.37#ibcon#wrote, iclass 3, count 2 2006.285.12:22:04.37#ibcon#about to read 3, iclass 3, count 2 2006.285.12:22:04.39#ibcon#read 3, iclass 3, count 2 2006.285.12:22:04.39#ibcon#about to read 4, iclass 3, count 2 2006.285.12:22:04.39#ibcon#read 4, iclass 3, count 2 2006.285.12:22:04.39#ibcon#about to read 5, iclass 3, count 2 2006.285.12:22:04.39#ibcon#read 5, iclass 3, count 2 2006.285.12:22:04.39#ibcon#about to read 6, iclass 3, count 2 2006.285.12:22:04.39#ibcon#read 6, iclass 3, count 2 2006.285.12:22:04.39#ibcon#end of sib2, iclass 3, count 2 2006.285.12:22:04.39#ibcon#*mode == 0, iclass 3, count 2 2006.285.12:22:04.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.12:22:04.40#ibcon#[25=AT06-04\r\n] 2006.285.12:22:04.40#ibcon#*before write, iclass 3, count 2 2006.285.12:22:04.40#ibcon#enter sib2, iclass 3, count 2 2006.285.12:22:04.40#ibcon#flushed, iclass 3, count 2 2006.285.12:22:04.40#ibcon#about to write, iclass 3, count 2 2006.285.12:22:04.40#ibcon#wrote, iclass 3, count 2 2006.285.12:22:04.40#ibcon#about to read 3, iclass 3, count 2 2006.285.12:22:04.42#ibcon#read 3, iclass 3, count 2 2006.285.12:22:04.42#ibcon#about to read 4, iclass 3, count 2 2006.285.12:22:04.42#ibcon#read 4, iclass 3, count 2 2006.285.12:22:04.42#ibcon#about to read 5, iclass 3, count 2 2006.285.12:22:04.42#ibcon#read 5, iclass 3, count 2 2006.285.12:22:04.42#ibcon#about to read 6, iclass 3, count 2 2006.285.12:22:04.42#ibcon#read 6, iclass 3, count 2 2006.285.12:22:04.42#ibcon#end of sib2, iclass 3, count 2 2006.285.12:22:04.42#ibcon#*after write, iclass 3, count 2 2006.285.12:22:04.42#ibcon#*before return 0, iclass 3, count 2 2006.285.12:22:04.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:22:04.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:22:04.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.12:22:04.43#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:04.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:22:04.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:22:04.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:22:04.54#ibcon#enter wrdev, iclass 3, count 0 2006.285.12:22:04.54#ibcon#first serial, iclass 3, count 0 2006.285.12:22:04.54#ibcon#enter sib2, iclass 3, count 0 2006.285.12:22:04.54#ibcon#flushed, iclass 3, count 0 2006.285.12:22:04.54#ibcon#about to write, iclass 3, count 0 2006.285.12:22:04.54#ibcon#wrote, iclass 3, count 0 2006.285.12:22:04.55#ibcon#about to read 3, iclass 3, count 0 2006.285.12:22:04.56#ibcon#read 3, iclass 3, count 0 2006.285.12:22:04.56#ibcon#about to read 4, iclass 3, count 0 2006.285.12:22:04.56#ibcon#read 4, iclass 3, count 0 2006.285.12:22:04.56#ibcon#about to read 5, iclass 3, count 0 2006.285.12:22:04.56#ibcon#read 5, iclass 3, count 0 2006.285.12:22:04.56#ibcon#about to read 6, iclass 3, count 0 2006.285.12:22:04.56#ibcon#read 6, iclass 3, count 0 2006.285.12:22:04.56#ibcon#end of sib2, iclass 3, count 0 2006.285.12:22:04.56#ibcon#*mode == 0, iclass 3, count 0 2006.285.12:22:04.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.12:22:04.57#ibcon#[25=USB\r\n] 2006.285.12:22:04.57#ibcon#*before write, iclass 3, count 0 2006.285.12:22:04.57#ibcon#enter sib2, iclass 3, count 0 2006.285.12:22:04.57#ibcon#flushed, iclass 3, count 0 2006.285.12:22:04.57#ibcon#about to write, iclass 3, count 0 2006.285.12:22:04.57#ibcon#wrote, iclass 3, count 0 2006.285.12:22:04.57#ibcon#about to read 3, iclass 3, count 0 2006.285.12:22:04.59#ibcon#read 3, iclass 3, count 0 2006.285.12:22:04.59#ibcon#about to read 4, iclass 3, count 0 2006.285.12:22:04.59#ibcon#read 4, iclass 3, count 0 2006.285.12:22:04.59#ibcon#about to read 5, iclass 3, count 0 2006.285.12:22:04.59#ibcon#read 5, iclass 3, count 0 2006.285.12:22:04.59#ibcon#about to read 6, iclass 3, count 0 2006.285.12:22:04.59#ibcon#read 6, iclass 3, count 0 2006.285.12:22:04.59#ibcon#end of sib2, iclass 3, count 0 2006.285.12:22:04.59#ibcon#*after write, iclass 3, count 0 2006.285.12:22:04.59#ibcon#*before return 0, iclass 3, count 0 2006.285.12:22:04.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:22:04.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:22:04.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.12:22:04.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.12:22:04.60$vck44/valo=7,864.99 2006.285.12:22:04.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.12:22:04.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.12:22:04.60#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:04.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:22:04.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:22:04.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:22:04.60#ibcon#enter wrdev, iclass 5, count 0 2006.285.12:22:04.60#ibcon#first serial, iclass 5, count 0 2006.285.12:22:04.60#ibcon#enter sib2, iclass 5, count 0 2006.285.12:22:04.60#ibcon#flushed, iclass 5, count 0 2006.285.12:22:04.60#ibcon#about to write, iclass 5, count 0 2006.285.12:22:04.60#ibcon#wrote, iclass 5, count 0 2006.285.12:22:04.60#ibcon#about to read 3, iclass 5, count 0 2006.285.12:22:04.61#ibcon#read 3, iclass 5, count 0 2006.285.12:22:04.61#ibcon#about to read 4, iclass 5, count 0 2006.285.12:22:04.61#ibcon#read 4, iclass 5, count 0 2006.285.12:22:04.61#ibcon#about to read 5, iclass 5, count 0 2006.285.12:22:04.61#ibcon#read 5, iclass 5, count 0 2006.285.12:22:04.61#ibcon#about to read 6, iclass 5, count 0 2006.285.12:22:04.61#ibcon#read 6, iclass 5, count 0 2006.285.12:22:04.61#ibcon#end of sib2, iclass 5, count 0 2006.285.12:22:04.61#ibcon#*mode == 0, iclass 5, count 0 2006.285.12:22:04.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.12:22:04.62#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.12:22:04.62#ibcon#*before write, iclass 5, count 0 2006.285.12:22:04.62#ibcon#enter sib2, iclass 5, count 0 2006.285.12:22:04.62#ibcon#flushed, iclass 5, count 0 2006.285.12:22:04.62#ibcon#about to write, iclass 5, count 0 2006.285.12:22:04.62#ibcon#wrote, iclass 5, count 0 2006.285.12:22:04.62#ibcon#about to read 3, iclass 5, count 0 2006.285.12:22:04.65#ibcon#read 3, iclass 5, count 0 2006.285.12:22:04.65#ibcon#about to read 4, iclass 5, count 0 2006.285.12:22:04.65#ibcon#read 4, iclass 5, count 0 2006.285.12:22:04.65#ibcon#about to read 5, iclass 5, count 0 2006.285.12:22:04.65#ibcon#read 5, iclass 5, count 0 2006.285.12:22:04.65#ibcon#about to read 6, iclass 5, count 0 2006.285.12:22:04.65#ibcon#read 6, iclass 5, count 0 2006.285.12:22:04.65#ibcon#end of sib2, iclass 5, count 0 2006.285.12:22:04.65#ibcon#*after write, iclass 5, count 0 2006.285.12:22:04.65#ibcon#*before return 0, iclass 5, count 0 2006.285.12:22:04.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:22:04.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:22:04.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.12:22:04.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.12:22:04.66$vck44/va=7,4 2006.285.12:22:04.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.12:22:04.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.12:22:04.66#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:04.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:22:04.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:22:04.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:22:04.71#ibcon#enter wrdev, iclass 7, count 2 2006.285.12:22:04.71#ibcon#first serial, iclass 7, count 2 2006.285.12:22:04.71#ibcon#enter sib2, iclass 7, count 2 2006.285.12:22:04.71#ibcon#flushed, iclass 7, count 2 2006.285.12:22:04.71#ibcon#about to write, iclass 7, count 2 2006.285.12:22:04.71#ibcon#wrote, iclass 7, count 2 2006.285.12:22:04.72#ibcon#about to read 3, iclass 7, count 2 2006.285.12:22:04.73#ibcon#read 3, iclass 7, count 2 2006.285.12:22:04.73#ibcon#about to read 4, iclass 7, count 2 2006.285.12:22:04.73#ibcon#read 4, iclass 7, count 2 2006.285.12:22:04.73#ibcon#about to read 5, iclass 7, count 2 2006.285.12:22:04.73#ibcon#read 5, iclass 7, count 2 2006.285.12:22:04.73#ibcon#about to read 6, iclass 7, count 2 2006.285.12:22:04.73#ibcon#read 6, iclass 7, count 2 2006.285.12:22:04.73#ibcon#end of sib2, iclass 7, count 2 2006.285.12:22:04.73#ibcon#*mode == 0, iclass 7, count 2 2006.285.12:22:04.73#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.12:22:04.74#ibcon#[25=AT07-04\r\n] 2006.285.12:22:04.74#ibcon#*before write, iclass 7, count 2 2006.285.12:22:04.74#ibcon#enter sib2, iclass 7, count 2 2006.285.12:22:04.74#ibcon#flushed, iclass 7, count 2 2006.285.12:22:04.74#ibcon#about to write, iclass 7, count 2 2006.285.12:22:04.74#ibcon#wrote, iclass 7, count 2 2006.285.12:22:04.74#ibcon#about to read 3, iclass 7, count 2 2006.285.12:22:04.76#ibcon#read 3, iclass 7, count 2 2006.285.12:22:04.76#ibcon#about to read 4, iclass 7, count 2 2006.285.12:22:04.76#ibcon#read 4, iclass 7, count 2 2006.285.12:22:04.76#ibcon#about to read 5, iclass 7, count 2 2006.285.12:22:04.76#ibcon#read 5, iclass 7, count 2 2006.285.12:22:04.76#ibcon#about to read 6, iclass 7, count 2 2006.285.12:22:04.76#ibcon#read 6, iclass 7, count 2 2006.285.12:22:04.76#ibcon#end of sib2, iclass 7, count 2 2006.285.12:22:04.76#ibcon#*after write, iclass 7, count 2 2006.285.12:22:04.76#ibcon#*before return 0, iclass 7, count 2 2006.285.12:22:04.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:22:04.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:22:04.77#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.12:22:04.77#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:04.77#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:22:04.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:22:04.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:22:04.88#ibcon#enter wrdev, iclass 7, count 0 2006.285.12:22:04.88#ibcon#first serial, iclass 7, count 0 2006.285.12:22:04.88#ibcon#enter sib2, iclass 7, count 0 2006.285.12:22:04.88#ibcon#flushed, iclass 7, count 0 2006.285.12:22:04.88#ibcon#about to write, iclass 7, count 0 2006.285.12:22:04.88#ibcon#wrote, iclass 7, count 0 2006.285.12:22:04.88#ibcon#about to read 3, iclass 7, count 0 2006.285.12:22:04.90#ibcon#read 3, iclass 7, count 0 2006.285.12:22:04.90#ibcon#about to read 4, iclass 7, count 0 2006.285.12:22:04.90#ibcon#read 4, iclass 7, count 0 2006.285.12:22:04.90#ibcon#about to read 5, iclass 7, count 0 2006.285.12:22:04.90#ibcon#read 5, iclass 7, count 0 2006.285.12:22:04.90#ibcon#about to read 6, iclass 7, count 0 2006.285.12:22:04.90#ibcon#read 6, iclass 7, count 0 2006.285.12:22:04.90#ibcon#end of sib2, iclass 7, count 0 2006.285.12:22:04.90#ibcon#*mode == 0, iclass 7, count 0 2006.285.12:22:04.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.12:22:04.90#ibcon#[25=USB\r\n] 2006.285.12:22:04.91#ibcon#*before write, iclass 7, count 0 2006.285.12:22:04.91#ibcon#enter sib2, iclass 7, count 0 2006.285.12:22:04.91#ibcon#flushed, iclass 7, count 0 2006.285.12:22:04.91#ibcon#about to write, iclass 7, count 0 2006.285.12:22:04.91#ibcon#wrote, iclass 7, count 0 2006.285.12:22:04.91#ibcon#about to read 3, iclass 7, count 0 2006.285.12:22:04.93#ibcon#read 3, iclass 7, count 0 2006.285.12:22:04.93#ibcon#about to read 4, iclass 7, count 0 2006.285.12:22:04.93#ibcon#read 4, iclass 7, count 0 2006.285.12:22:04.93#ibcon#about to read 5, iclass 7, count 0 2006.285.12:22:04.93#ibcon#read 5, iclass 7, count 0 2006.285.12:22:04.93#ibcon#about to read 6, iclass 7, count 0 2006.285.12:22:04.93#ibcon#read 6, iclass 7, count 0 2006.285.12:22:04.93#ibcon#end of sib2, iclass 7, count 0 2006.285.12:22:04.93#ibcon#*after write, iclass 7, count 0 2006.285.12:22:04.93#ibcon#*before return 0, iclass 7, count 0 2006.285.12:22:04.94#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:22:04.94#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:22:04.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.12:22:04.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.12:22:04.94$vck44/valo=8,884.99 2006.285.12:22:04.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.12:22:04.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.12:22:04.94#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:04.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:22:04.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:22:04.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:22:04.94#ibcon#enter wrdev, iclass 11, count 0 2006.285.12:22:04.94#ibcon#first serial, iclass 11, count 0 2006.285.12:22:04.94#ibcon#enter sib2, iclass 11, count 0 2006.285.12:22:04.94#ibcon#flushed, iclass 11, count 0 2006.285.12:22:04.94#ibcon#about to write, iclass 11, count 0 2006.285.12:22:04.94#ibcon#wrote, iclass 11, count 0 2006.285.12:22:04.94#ibcon#about to read 3, iclass 11, count 0 2006.285.12:22:04.95#ibcon#read 3, iclass 11, count 0 2006.285.12:22:04.95#ibcon#about to read 4, iclass 11, count 0 2006.285.12:22:04.95#ibcon#read 4, iclass 11, count 0 2006.285.12:22:04.95#ibcon#about to read 5, iclass 11, count 0 2006.285.12:22:04.95#ibcon#read 5, iclass 11, count 0 2006.285.12:22:04.95#ibcon#about to read 6, iclass 11, count 0 2006.285.12:22:04.95#ibcon#read 6, iclass 11, count 0 2006.285.12:22:04.95#ibcon#end of sib2, iclass 11, count 0 2006.285.12:22:04.95#ibcon#*mode == 0, iclass 11, count 0 2006.285.12:22:04.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.12:22:04.96#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.12:22:04.96#ibcon#*before write, iclass 11, count 0 2006.285.12:22:04.96#ibcon#enter sib2, iclass 11, count 0 2006.285.12:22:04.96#ibcon#flushed, iclass 11, count 0 2006.285.12:22:04.96#ibcon#about to write, iclass 11, count 0 2006.285.12:22:04.96#ibcon#wrote, iclass 11, count 0 2006.285.12:22:04.96#ibcon#about to read 3, iclass 11, count 0 2006.285.12:22:04.99#ibcon#read 3, iclass 11, count 0 2006.285.12:22:04.99#ibcon#about to read 4, iclass 11, count 0 2006.285.12:22:04.99#ibcon#read 4, iclass 11, count 0 2006.285.12:22:04.99#ibcon#about to read 5, iclass 11, count 0 2006.285.12:22:04.99#ibcon#read 5, iclass 11, count 0 2006.285.12:22:04.99#ibcon#about to read 6, iclass 11, count 0 2006.285.12:22:04.99#ibcon#read 6, iclass 11, count 0 2006.285.12:22:04.99#ibcon#end of sib2, iclass 11, count 0 2006.285.12:22:04.99#ibcon#*after write, iclass 11, count 0 2006.285.12:22:04.99#ibcon#*before return 0, iclass 11, count 0 2006.285.12:22:05.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:22:05.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:22:05.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.12:22:05.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.12:22:05.00$vck44/va=8,3 2006.285.12:22:05.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.12:22:05.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.12:22:05.00#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:05.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:22:05.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:22:05.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:22:05.05#ibcon#enter wrdev, iclass 13, count 2 2006.285.12:22:05.05#ibcon#first serial, iclass 13, count 2 2006.285.12:22:05.05#ibcon#enter sib2, iclass 13, count 2 2006.285.12:22:05.05#ibcon#flushed, iclass 13, count 2 2006.285.12:22:05.05#ibcon#about to write, iclass 13, count 2 2006.285.12:22:05.05#ibcon#wrote, iclass 13, count 2 2006.285.12:22:05.05#ibcon#about to read 3, iclass 13, count 2 2006.285.12:22:05.07#ibcon#read 3, iclass 13, count 2 2006.285.12:22:05.07#ibcon#about to read 4, iclass 13, count 2 2006.285.12:22:05.07#ibcon#read 4, iclass 13, count 2 2006.285.12:22:05.07#ibcon#about to read 5, iclass 13, count 2 2006.285.12:22:05.07#ibcon#read 5, iclass 13, count 2 2006.285.12:22:05.07#ibcon#about to read 6, iclass 13, count 2 2006.285.12:22:05.07#ibcon#read 6, iclass 13, count 2 2006.285.12:22:05.07#ibcon#end of sib2, iclass 13, count 2 2006.285.12:22:05.08#ibcon#*mode == 0, iclass 13, count 2 2006.285.12:22:05.08#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.12:22:05.08#ibcon#[25=AT08-03\r\n] 2006.285.12:22:05.08#ibcon#*before write, iclass 13, count 2 2006.285.12:22:05.08#ibcon#enter sib2, iclass 13, count 2 2006.285.12:22:05.08#ibcon#flushed, iclass 13, count 2 2006.285.12:22:05.08#ibcon#about to write, iclass 13, count 2 2006.285.12:22:05.08#ibcon#wrote, iclass 13, count 2 2006.285.12:22:05.08#ibcon#about to read 3, iclass 13, count 2 2006.285.12:22:05.10#ibcon#read 3, iclass 13, count 2 2006.285.12:22:05.10#ibcon#about to read 4, iclass 13, count 2 2006.285.12:22:05.10#ibcon#read 4, iclass 13, count 2 2006.285.12:22:05.10#ibcon#about to read 5, iclass 13, count 2 2006.285.12:22:05.10#ibcon#read 5, iclass 13, count 2 2006.285.12:22:05.10#ibcon#about to read 6, iclass 13, count 2 2006.285.12:22:05.10#ibcon#read 6, iclass 13, count 2 2006.285.12:22:05.10#ibcon#end of sib2, iclass 13, count 2 2006.285.12:22:05.10#ibcon#*after write, iclass 13, count 2 2006.285.12:22:05.10#ibcon#*before return 0, iclass 13, count 2 2006.285.12:22:05.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:22:05.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:22:05.11#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.12:22:05.11#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:05.11#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:22:05.22#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:22:05.22#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:22:05.22#ibcon#enter wrdev, iclass 13, count 0 2006.285.12:22:05.22#ibcon#first serial, iclass 13, count 0 2006.285.12:22:05.22#ibcon#enter sib2, iclass 13, count 0 2006.285.12:22:05.22#ibcon#flushed, iclass 13, count 0 2006.285.12:22:05.22#ibcon#about to write, iclass 13, count 0 2006.285.12:22:05.22#ibcon#wrote, iclass 13, count 0 2006.285.12:22:05.23#ibcon#about to read 3, iclass 13, count 0 2006.285.12:22:05.24#ibcon#read 3, iclass 13, count 0 2006.285.12:22:05.24#ibcon#about to read 4, iclass 13, count 0 2006.285.12:22:05.24#ibcon#read 4, iclass 13, count 0 2006.285.12:22:05.24#ibcon#about to read 5, iclass 13, count 0 2006.285.12:22:05.24#ibcon#read 5, iclass 13, count 0 2006.285.12:22:05.24#ibcon#about to read 6, iclass 13, count 0 2006.285.12:22:05.24#ibcon#read 6, iclass 13, count 0 2006.285.12:22:05.24#ibcon#end of sib2, iclass 13, count 0 2006.285.12:22:05.24#ibcon#*mode == 0, iclass 13, count 0 2006.285.12:22:05.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.12:22:05.25#ibcon#[25=USB\r\n] 2006.285.12:22:05.25#ibcon#*before write, iclass 13, count 0 2006.285.12:22:05.25#ibcon#enter sib2, iclass 13, count 0 2006.285.12:22:05.25#ibcon#flushed, iclass 13, count 0 2006.285.12:22:05.25#ibcon#about to write, iclass 13, count 0 2006.285.12:22:05.25#ibcon#wrote, iclass 13, count 0 2006.285.12:22:05.25#ibcon#about to read 3, iclass 13, count 0 2006.285.12:22:05.27#ibcon#read 3, iclass 13, count 0 2006.285.12:22:05.27#ibcon#about to read 4, iclass 13, count 0 2006.285.12:22:05.27#ibcon#read 4, iclass 13, count 0 2006.285.12:22:05.27#ibcon#about to read 5, iclass 13, count 0 2006.285.12:22:05.27#ibcon#read 5, iclass 13, count 0 2006.285.12:22:05.27#ibcon#about to read 6, iclass 13, count 0 2006.285.12:22:05.27#ibcon#read 6, iclass 13, count 0 2006.285.12:22:05.27#ibcon#end of sib2, iclass 13, count 0 2006.285.12:22:05.27#ibcon#*after write, iclass 13, count 0 2006.285.12:22:05.27#ibcon#*before return 0, iclass 13, count 0 2006.285.12:22:05.28#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:22:05.28#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:22:05.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.12:22:05.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.12:22:05.28$vck44/vblo=1,629.99 2006.285.12:22:05.28#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.12:22:05.28#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.12:22:05.28#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:05.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:22:05.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:22:05.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:22:05.28#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:22:05.28#ibcon#first serial, iclass 15, count 0 2006.285.12:22:05.28#ibcon#enter sib2, iclass 15, count 0 2006.285.12:22:05.28#ibcon#flushed, iclass 15, count 0 2006.285.12:22:05.28#ibcon#about to write, iclass 15, count 0 2006.285.12:22:05.28#ibcon#wrote, iclass 15, count 0 2006.285.12:22:05.28#ibcon#about to read 3, iclass 15, count 0 2006.285.12:22:05.29#ibcon#read 3, iclass 15, count 0 2006.285.12:22:05.29#ibcon#about to read 4, iclass 15, count 0 2006.285.12:22:05.29#ibcon#read 4, iclass 15, count 0 2006.285.12:22:05.29#ibcon#about to read 5, iclass 15, count 0 2006.285.12:22:05.29#ibcon#read 5, iclass 15, count 0 2006.285.12:22:05.29#ibcon#about to read 6, iclass 15, count 0 2006.285.12:22:05.29#ibcon#read 6, iclass 15, count 0 2006.285.12:22:05.29#ibcon#end of sib2, iclass 15, count 0 2006.285.12:22:05.29#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:22:05.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:22:05.30#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.12:22:05.30#ibcon#*before write, iclass 15, count 0 2006.285.12:22:05.30#ibcon#enter sib2, iclass 15, count 0 2006.285.12:22:05.30#ibcon#flushed, iclass 15, count 0 2006.285.12:22:05.30#ibcon#about to write, iclass 15, count 0 2006.285.12:22:05.30#ibcon#wrote, iclass 15, count 0 2006.285.12:22:05.30#ibcon#about to read 3, iclass 15, count 0 2006.285.12:22:05.33#ibcon#read 3, iclass 15, count 0 2006.285.12:22:05.33#ibcon#about to read 4, iclass 15, count 0 2006.285.12:22:05.33#ibcon#read 4, iclass 15, count 0 2006.285.12:22:05.33#ibcon#about to read 5, iclass 15, count 0 2006.285.12:22:05.33#ibcon#read 5, iclass 15, count 0 2006.285.12:22:05.33#ibcon#about to read 6, iclass 15, count 0 2006.285.12:22:05.33#ibcon#read 6, iclass 15, count 0 2006.285.12:22:05.33#ibcon#end of sib2, iclass 15, count 0 2006.285.12:22:05.33#ibcon#*after write, iclass 15, count 0 2006.285.12:22:05.33#ibcon#*before return 0, iclass 15, count 0 2006.285.12:22:05.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:22:05.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:22:05.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:22:05.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:22:05.34$vck44/vb=1,4 2006.285.12:22:05.34#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.12:22:05.34#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.12:22:05.34#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:05.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:22:05.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:22:05.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:22:05.34#ibcon#enter wrdev, iclass 17, count 2 2006.285.12:22:05.34#ibcon#first serial, iclass 17, count 2 2006.285.12:22:05.34#ibcon#enter sib2, iclass 17, count 2 2006.285.12:22:05.34#ibcon#flushed, iclass 17, count 2 2006.285.12:22:05.34#ibcon#about to write, iclass 17, count 2 2006.285.12:22:05.34#ibcon#wrote, iclass 17, count 2 2006.285.12:22:05.34#ibcon#about to read 3, iclass 17, count 2 2006.285.12:22:05.35#ibcon#read 3, iclass 17, count 2 2006.285.12:22:05.35#ibcon#about to read 4, iclass 17, count 2 2006.285.12:22:05.35#ibcon#read 4, iclass 17, count 2 2006.285.12:22:05.35#ibcon#about to read 5, iclass 17, count 2 2006.285.12:22:05.35#ibcon#read 5, iclass 17, count 2 2006.285.12:22:05.35#ibcon#about to read 6, iclass 17, count 2 2006.285.12:22:05.35#ibcon#read 6, iclass 17, count 2 2006.285.12:22:05.35#ibcon#end of sib2, iclass 17, count 2 2006.285.12:22:05.35#ibcon#*mode == 0, iclass 17, count 2 2006.285.12:22:05.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.12:22:05.36#ibcon#[27=AT01-04\r\n] 2006.285.12:22:05.36#ibcon#*before write, iclass 17, count 2 2006.285.12:22:05.36#ibcon#enter sib2, iclass 17, count 2 2006.285.12:22:05.36#ibcon#flushed, iclass 17, count 2 2006.285.12:22:05.36#ibcon#about to write, iclass 17, count 2 2006.285.12:22:05.36#ibcon#wrote, iclass 17, count 2 2006.285.12:22:05.36#ibcon#about to read 3, iclass 17, count 2 2006.285.12:22:05.38#ibcon#read 3, iclass 17, count 2 2006.285.12:22:05.38#ibcon#about to read 4, iclass 17, count 2 2006.285.12:22:05.38#ibcon#read 4, iclass 17, count 2 2006.285.12:22:05.38#ibcon#about to read 5, iclass 17, count 2 2006.285.12:22:05.38#ibcon#read 5, iclass 17, count 2 2006.285.12:22:05.38#ibcon#about to read 6, iclass 17, count 2 2006.285.12:22:05.38#ibcon#read 6, iclass 17, count 2 2006.285.12:22:05.38#ibcon#end of sib2, iclass 17, count 2 2006.285.12:22:05.38#ibcon#*after write, iclass 17, count 2 2006.285.12:22:05.38#ibcon#*before return 0, iclass 17, count 2 2006.285.12:22:05.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:22:05.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:22:05.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.12:22:05.39#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:05.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:22:05.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:22:05.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:22:05.50#ibcon#enter wrdev, iclass 17, count 0 2006.285.12:22:05.50#ibcon#first serial, iclass 17, count 0 2006.285.12:22:05.50#ibcon#enter sib2, iclass 17, count 0 2006.285.12:22:05.50#ibcon#flushed, iclass 17, count 0 2006.285.12:22:05.50#ibcon#about to write, iclass 17, count 0 2006.285.12:22:05.51#ibcon#wrote, iclass 17, count 0 2006.285.12:22:05.51#ibcon#about to read 3, iclass 17, count 0 2006.285.12:22:05.52#ibcon#read 3, iclass 17, count 0 2006.285.12:22:05.52#ibcon#about to read 4, iclass 17, count 0 2006.285.12:22:05.52#ibcon#read 4, iclass 17, count 0 2006.285.12:22:05.52#ibcon#about to read 5, iclass 17, count 0 2006.285.12:22:05.52#ibcon#read 5, iclass 17, count 0 2006.285.12:22:05.52#ibcon#about to read 6, iclass 17, count 0 2006.285.12:22:05.52#ibcon#read 6, iclass 17, count 0 2006.285.12:22:05.52#ibcon#end of sib2, iclass 17, count 0 2006.285.12:22:05.53#ibcon#*mode == 0, iclass 17, count 0 2006.285.12:22:05.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.12:22:05.53#ibcon#[27=USB\r\n] 2006.285.12:22:05.53#ibcon#*before write, iclass 17, count 0 2006.285.12:22:05.53#ibcon#enter sib2, iclass 17, count 0 2006.285.12:22:05.53#ibcon#flushed, iclass 17, count 0 2006.285.12:22:05.53#ibcon#about to write, iclass 17, count 0 2006.285.12:22:05.53#ibcon#wrote, iclass 17, count 0 2006.285.12:22:05.53#ibcon#about to read 3, iclass 17, count 0 2006.285.12:22:05.55#ibcon#read 3, iclass 17, count 0 2006.285.12:22:05.55#ibcon#about to read 4, iclass 17, count 0 2006.285.12:22:05.55#ibcon#read 4, iclass 17, count 0 2006.285.12:22:05.55#ibcon#about to read 5, iclass 17, count 0 2006.285.12:22:05.55#ibcon#read 5, iclass 17, count 0 2006.285.12:22:05.55#ibcon#about to read 6, iclass 17, count 0 2006.285.12:22:05.55#ibcon#read 6, iclass 17, count 0 2006.285.12:22:05.55#ibcon#end of sib2, iclass 17, count 0 2006.285.12:22:05.55#ibcon#*after write, iclass 17, count 0 2006.285.12:22:05.56#ibcon#*before return 0, iclass 17, count 0 2006.285.12:22:05.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:22:05.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:22:05.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.12:22:05.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.12:22:05.56$vck44/vblo=2,634.99 2006.285.12:22:05.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.12:22:05.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.12:22:05.56#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:05.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:22:05.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:22:05.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:22:05.56#ibcon#enter wrdev, iclass 19, count 0 2006.285.12:22:05.56#ibcon#first serial, iclass 19, count 0 2006.285.12:22:05.56#ibcon#enter sib2, iclass 19, count 0 2006.285.12:22:05.56#ibcon#flushed, iclass 19, count 0 2006.285.12:22:05.56#ibcon#about to write, iclass 19, count 0 2006.285.12:22:05.56#ibcon#wrote, iclass 19, count 0 2006.285.12:22:05.56#ibcon#about to read 3, iclass 19, count 0 2006.285.12:22:05.57#ibcon#read 3, iclass 19, count 0 2006.285.12:22:05.57#ibcon#about to read 4, iclass 19, count 0 2006.285.12:22:05.57#ibcon#read 4, iclass 19, count 0 2006.285.12:22:05.57#ibcon#about to read 5, iclass 19, count 0 2006.285.12:22:05.57#ibcon#read 5, iclass 19, count 0 2006.285.12:22:05.57#ibcon#about to read 6, iclass 19, count 0 2006.285.12:22:05.57#ibcon#read 6, iclass 19, count 0 2006.285.12:22:05.57#ibcon#end of sib2, iclass 19, count 0 2006.285.12:22:05.57#ibcon#*mode == 0, iclass 19, count 0 2006.285.12:22:05.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.12:22:05.58#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.12:22:05.58#ibcon#*before write, iclass 19, count 0 2006.285.12:22:05.58#ibcon#enter sib2, iclass 19, count 0 2006.285.12:22:05.58#ibcon#flushed, iclass 19, count 0 2006.285.12:22:05.58#ibcon#about to write, iclass 19, count 0 2006.285.12:22:05.58#ibcon#wrote, iclass 19, count 0 2006.285.12:22:05.58#ibcon#about to read 3, iclass 19, count 0 2006.285.12:22:05.61#ibcon#read 3, iclass 19, count 0 2006.285.12:22:05.61#ibcon#about to read 4, iclass 19, count 0 2006.285.12:22:05.61#ibcon#read 4, iclass 19, count 0 2006.285.12:22:05.61#ibcon#about to read 5, iclass 19, count 0 2006.285.12:22:05.61#ibcon#read 5, iclass 19, count 0 2006.285.12:22:05.61#ibcon#about to read 6, iclass 19, count 0 2006.285.12:22:05.61#ibcon#read 6, iclass 19, count 0 2006.285.12:22:05.61#ibcon#end of sib2, iclass 19, count 0 2006.285.12:22:05.61#ibcon#*after write, iclass 19, count 0 2006.285.12:22:05.61#ibcon#*before return 0, iclass 19, count 0 2006.285.12:22:05.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:22:05.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:22:05.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.12:22:05.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.12:22:05.62$vck44/vb=2,5 2006.285.12:22:05.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.12:22:05.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.12:22:05.62#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:05.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:22:05.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:22:05.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:22:05.67#ibcon#enter wrdev, iclass 21, count 2 2006.285.12:22:05.67#ibcon#first serial, iclass 21, count 2 2006.285.12:22:05.67#ibcon#enter sib2, iclass 21, count 2 2006.285.12:22:05.67#ibcon#flushed, iclass 21, count 2 2006.285.12:22:05.67#ibcon#about to write, iclass 21, count 2 2006.285.12:22:05.67#ibcon#wrote, iclass 21, count 2 2006.285.12:22:05.67#ibcon#about to read 3, iclass 21, count 2 2006.285.12:22:05.69#ibcon#read 3, iclass 21, count 2 2006.285.12:22:05.69#ibcon#about to read 4, iclass 21, count 2 2006.285.12:22:05.69#ibcon#read 4, iclass 21, count 2 2006.285.12:22:05.69#ibcon#about to read 5, iclass 21, count 2 2006.285.12:22:05.69#ibcon#read 5, iclass 21, count 2 2006.285.12:22:05.69#ibcon#about to read 6, iclass 21, count 2 2006.285.12:22:05.69#ibcon#read 6, iclass 21, count 2 2006.285.12:22:05.69#ibcon#end of sib2, iclass 21, count 2 2006.285.12:22:05.69#ibcon#*mode == 0, iclass 21, count 2 2006.285.12:22:05.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.12:22:05.70#ibcon#[27=AT02-05\r\n] 2006.285.12:22:05.70#ibcon#*before write, iclass 21, count 2 2006.285.12:22:05.70#ibcon#enter sib2, iclass 21, count 2 2006.285.12:22:05.70#ibcon#flushed, iclass 21, count 2 2006.285.12:22:05.70#ibcon#about to write, iclass 21, count 2 2006.285.12:22:05.70#ibcon#wrote, iclass 21, count 2 2006.285.12:22:05.70#ibcon#about to read 3, iclass 21, count 2 2006.285.12:22:05.72#ibcon#read 3, iclass 21, count 2 2006.285.12:22:05.72#ibcon#about to read 4, iclass 21, count 2 2006.285.12:22:05.72#ibcon#read 4, iclass 21, count 2 2006.285.12:22:05.72#ibcon#about to read 5, iclass 21, count 2 2006.285.12:22:05.72#ibcon#read 5, iclass 21, count 2 2006.285.12:22:05.72#ibcon#about to read 6, iclass 21, count 2 2006.285.12:22:05.72#ibcon#read 6, iclass 21, count 2 2006.285.12:22:05.72#ibcon#end of sib2, iclass 21, count 2 2006.285.12:22:05.72#ibcon#*after write, iclass 21, count 2 2006.285.12:22:05.72#ibcon#*before return 0, iclass 21, count 2 2006.285.12:22:05.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:22:05.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:22:05.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.12:22:05.73#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:05.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:22:05.79#abcon#<5=/05 1.1 1.8 18.84 951015.5\r\n> 2006.285.12:22:05.81#abcon#{5=INTERFACE CLEAR} 2006.285.12:22:05.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:22:05.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:22:05.84#ibcon#enter wrdev, iclass 21, count 0 2006.285.12:22:05.84#ibcon#first serial, iclass 21, count 0 2006.285.12:22:05.84#ibcon#enter sib2, iclass 21, count 0 2006.285.12:22:05.84#ibcon#flushed, iclass 21, count 0 2006.285.12:22:05.84#ibcon#about to write, iclass 21, count 0 2006.285.12:22:05.84#ibcon#wrote, iclass 21, count 0 2006.285.12:22:05.84#ibcon#about to read 3, iclass 21, count 0 2006.285.12:22:05.86#ibcon#read 3, iclass 21, count 0 2006.285.12:22:05.86#ibcon#about to read 4, iclass 21, count 0 2006.285.12:22:05.86#ibcon#read 4, iclass 21, count 0 2006.285.12:22:05.86#ibcon#about to read 5, iclass 21, count 0 2006.285.12:22:05.86#ibcon#read 5, iclass 21, count 0 2006.285.12:22:05.86#ibcon#about to read 6, iclass 21, count 0 2006.285.12:22:05.86#ibcon#read 6, iclass 21, count 0 2006.285.12:22:05.86#ibcon#end of sib2, iclass 21, count 0 2006.285.12:22:05.86#ibcon#*mode == 0, iclass 21, count 0 2006.285.12:22:05.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.12:22:05.87#ibcon#[27=USB\r\n] 2006.285.12:22:05.87#ibcon#*before write, iclass 21, count 0 2006.285.12:22:05.87#ibcon#enter sib2, iclass 21, count 0 2006.285.12:22:05.87#ibcon#flushed, iclass 21, count 0 2006.285.12:22:05.87#ibcon#about to write, iclass 21, count 0 2006.285.12:22:05.87#ibcon#wrote, iclass 21, count 0 2006.285.12:22:05.87#ibcon#about to read 3, iclass 21, count 0 2006.285.12:22:05.87#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:22:05.89#ibcon#read 3, iclass 21, count 0 2006.285.12:22:05.89#ibcon#about to read 4, iclass 21, count 0 2006.285.12:22:05.89#ibcon#read 4, iclass 21, count 0 2006.285.12:22:05.89#ibcon#about to read 5, iclass 21, count 0 2006.285.12:22:05.89#ibcon#read 5, iclass 21, count 0 2006.285.12:22:05.89#ibcon#about to read 6, iclass 21, count 0 2006.285.12:22:05.89#ibcon#read 6, iclass 21, count 0 2006.285.12:22:05.89#ibcon#end of sib2, iclass 21, count 0 2006.285.12:22:05.89#ibcon#*after write, iclass 21, count 0 2006.285.12:22:05.89#ibcon#*before return 0, iclass 21, count 0 2006.285.12:22:05.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:22:05.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:22:05.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.12:22:05.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.12:22:05.90$vck44/vblo=3,649.99 2006.285.12:22:05.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.12:22:05.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.12:22:05.90#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:05.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:22:05.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:22:05.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:22:05.90#ibcon#enter wrdev, iclass 27, count 0 2006.285.12:22:05.90#ibcon#first serial, iclass 27, count 0 2006.285.12:22:05.90#ibcon#enter sib2, iclass 27, count 0 2006.285.12:22:05.90#ibcon#flushed, iclass 27, count 0 2006.285.12:22:05.90#ibcon#about to write, iclass 27, count 0 2006.285.12:22:05.90#ibcon#wrote, iclass 27, count 0 2006.285.12:22:05.90#ibcon#about to read 3, iclass 27, count 0 2006.285.12:22:05.91#ibcon#read 3, iclass 27, count 0 2006.285.12:22:05.91#ibcon#about to read 4, iclass 27, count 0 2006.285.12:22:05.91#ibcon#read 4, iclass 27, count 0 2006.285.12:22:05.91#ibcon#about to read 5, iclass 27, count 0 2006.285.12:22:05.91#ibcon#read 5, iclass 27, count 0 2006.285.12:22:05.91#ibcon#about to read 6, iclass 27, count 0 2006.285.12:22:05.91#ibcon#read 6, iclass 27, count 0 2006.285.12:22:05.91#ibcon#end of sib2, iclass 27, count 0 2006.285.12:22:05.91#ibcon#*mode == 0, iclass 27, count 0 2006.285.12:22:05.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.12:22:05.92#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.12:22:05.92#ibcon#*before write, iclass 27, count 0 2006.285.12:22:05.92#ibcon#enter sib2, iclass 27, count 0 2006.285.12:22:05.92#ibcon#flushed, iclass 27, count 0 2006.285.12:22:05.92#ibcon#about to write, iclass 27, count 0 2006.285.12:22:05.92#ibcon#wrote, iclass 27, count 0 2006.285.12:22:05.92#ibcon#about to read 3, iclass 27, count 0 2006.285.12:22:05.95#ibcon#read 3, iclass 27, count 0 2006.285.12:22:05.95#ibcon#about to read 4, iclass 27, count 0 2006.285.12:22:05.95#ibcon#read 4, iclass 27, count 0 2006.285.12:22:05.95#ibcon#about to read 5, iclass 27, count 0 2006.285.12:22:05.95#ibcon#read 5, iclass 27, count 0 2006.285.12:22:05.95#ibcon#about to read 6, iclass 27, count 0 2006.285.12:22:05.95#ibcon#read 6, iclass 27, count 0 2006.285.12:22:05.95#ibcon#end of sib2, iclass 27, count 0 2006.285.12:22:05.95#ibcon#*after write, iclass 27, count 0 2006.285.12:22:05.95#ibcon#*before return 0, iclass 27, count 0 2006.285.12:22:05.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:22:05.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:22:05.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.12:22:05.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.12:22:05.96$vck44/vb=3,4 2006.285.12:22:05.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.12:22:05.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.12:22:05.96#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:05.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:22:06.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:22:06.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:22:06.01#ibcon#enter wrdev, iclass 29, count 2 2006.285.12:22:06.01#ibcon#first serial, iclass 29, count 2 2006.285.12:22:06.01#ibcon#enter sib2, iclass 29, count 2 2006.285.12:22:06.02#ibcon#flushed, iclass 29, count 2 2006.285.12:22:06.02#ibcon#about to write, iclass 29, count 2 2006.285.12:22:06.02#ibcon#wrote, iclass 29, count 2 2006.285.12:22:06.02#ibcon#about to read 3, iclass 29, count 2 2006.285.12:22:06.03#ibcon#read 3, iclass 29, count 2 2006.285.12:22:06.03#ibcon#about to read 4, iclass 29, count 2 2006.285.12:22:06.03#ibcon#read 4, iclass 29, count 2 2006.285.12:22:06.03#ibcon#about to read 5, iclass 29, count 2 2006.285.12:22:06.03#ibcon#read 5, iclass 29, count 2 2006.285.12:22:06.03#ibcon#about to read 6, iclass 29, count 2 2006.285.12:22:06.03#ibcon#read 6, iclass 29, count 2 2006.285.12:22:06.03#ibcon#end of sib2, iclass 29, count 2 2006.285.12:22:06.03#ibcon#*mode == 0, iclass 29, count 2 2006.285.12:22:06.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.12:22:06.04#ibcon#[27=AT03-04\r\n] 2006.285.12:22:06.04#ibcon#*before write, iclass 29, count 2 2006.285.12:22:06.04#ibcon#enter sib2, iclass 29, count 2 2006.285.12:22:06.04#ibcon#flushed, iclass 29, count 2 2006.285.12:22:06.04#ibcon#about to write, iclass 29, count 2 2006.285.12:22:06.04#ibcon#wrote, iclass 29, count 2 2006.285.12:22:06.04#ibcon#about to read 3, iclass 29, count 2 2006.285.12:22:06.06#ibcon#read 3, iclass 29, count 2 2006.285.12:22:06.06#ibcon#about to read 4, iclass 29, count 2 2006.285.12:22:06.06#ibcon#read 4, iclass 29, count 2 2006.285.12:22:06.06#ibcon#about to read 5, iclass 29, count 2 2006.285.12:22:06.06#ibcon#read 5, iclass 29, count 2 2006.285.12:22:06.06#ibcon#about to read 6, iclass 29, count 2 2006.285.12:22:06.06#ibcon#read 6, iclass 29, count 2 2006.285.12:22:06.06#ibcon#end of sib2, iclass 29, count 2 2006.285.12:22:06.06#ibcon#*after write, iclass 29, count 2 2006.285.12:22:06.07#ibcon#*before return 0, iclass 29, count 2 2006.285.12:22:06.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:22:06.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:22:06.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.12:22:06.07#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:06.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:22:06.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:22:06.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:22:06.18#ibcon#enter wrdev, iclass 29, count 0 2006.285.12:22:06.18#ibcon#first serial, iclass 29, count 0 2006.285.12:22:06.18#ibcon#enter sib2, iclass 29, count 0 2006.285.12:22:06.18#ibcon#flushed, iclass 29, count 0 2006.285.12:22:06.18#ibcon#about to write, iclass 29, count 0 2006.285.12:22:06.18#ibcon#wrote, iclass 29, count 0 2006.285.12:22:06.18#ibcon#about to read 3, iclass 29, count 0 2006.285.12:22:06.20#ibcon#read 3, iclass 29, count 0 2006.285.12:22:06.20#ibcon#about to read 4, iclass 29, count 0 2006.285.12:22:06.20#ibcon#read 4, iclass 29, count 0 2006.285.12:22:06.20#ibcon#about to read 5, iclass 29, count 0 2006.285.12:22:06.20#ibcon#read 5, iclass 29, count 0 2006.285.12:22:06.20#ibcon#about to read 6, iclass 29, count 0 2006.285.12:22:06.20#ibcon#read 6, iclass 29, count 0 2006.285.12:22:06.20#ibcon#end of sib2, iclass 29, count 0 2006.285.12:22:06.21#ibcon#*mode == 0, iclass 29, count 0 2006.285.12:22:06.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.12:22:06.21#ibcon#[27=USB\r\n] 2006.285.12:22:06.21#ibcon#*before write, iclass 29, count 0 2006.285.12:22:06.21#ibcon#enter sib2, iclass 29, count 0 2006.285.12:22:06.21#ibcon#flushed, iclass 29, count 0 2006.285.12:22:06.21#ibcon#about to write, iclass 29, count 0 2006.285.12:22:06.21#ibcon#wrote, iclass 29, count 0 2006.285.12:22:06.21#ibcon#about to read 3, iclass 29, count 0 2006.285.12:22:06.23#ibcon#read 3, iclass 29, count 0 2006.285.12:22:06.23#ibcon#about to read 4, iclass 29, count 0 2006.285.12:22:06.23#ibcon#read 4, iclass 29, count 0 2006.285.12:22:06.23#ibcon#about to read 5, iclass 29, count 0 2006.285.12:22:06.23#ibcon#read 5, iclass 29, count 0 2006.285.12:22:06.23#ibcon#about to read 6, iclass 29, count 0 2006.285.12:22:06.23#ibcon#read 6, iclass 29, count 0 2006.285.12:22:06.23#ibcon#end of sib2, iclass 29, count 0 2006.285.12:22:06.23#ibcon#*after write, iclass 29, count 0 2006.285.12:22:06.23#ibcon#*before return 0, iclass 29, count 0 2006.285.12:22:06.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:22:06.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:22:06.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.12:22:06.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.12:22:06.24$vck44/vblo=4,679.99 2006.285.12:22:06.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.12:22:06.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.12:22:06.24#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:06.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:22:06.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:22:06.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:22:06.24#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:22:06.24#ibcon#first serial, iclass 31, count 0 2006.285.12:22:06.24#ibcon#enter sib2, iclass 31, count 0 2006.285.12:22:06.24#ibcon#flushed, iclass 31, count 0 2006.285.12:22:06.24#ibcon#about to write, iclass 31, count 0 2006.285.12:22:06.24#ibcon#wrote, iclass 31, count 0 2006.285.12:22:06.24#ibcon#about to read 3, iclass 31, count 0 2006.285.12:22:06.25#ibcon#read 3, iclass 31, count 0 2006.285.12:22:06.25#ibcon#about to read 4, iclass 31, count 0 2006.285.12:22:06.25#ibcon#read 4, iclass 31, count 0 2006.285.12:22:06.25#ibcon#about to read 5, iclass 31, count 0 2006.285.12:22:06.25#ibcon#read 5, iclass 31, count 0 2006.285.12:22:06.25#ibcon#about to read 6, iclass 31, count 0 2006.285.12:22:06.25#ibcon#read 6, iclass 31, count 0 2006.285.12:22:06.25#ibcon#end of sib2, iclass 31, count 0 2006.285.12:22:06.25#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:22:06.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:22:06.26#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.12:22:06.26#ibcon#*before write, iclass 31, count 0 2006.285.12:22:06.26#ibcon#enter sib2, iclass 31, count 0 2006.285.12:22:06.26#ibcon#flushed, iclass 31, count 0 2006.285.12:22:06.26#ibcon#about to write, iclass 31, count 0 2006.285.12:22:06.26#ibcon#wrote, iclass 31, count 0 2006.285.12:22:06.26#ibcon#about to read 3, iclass 31, count 0 2006.285.12:22:06.29#ibcon#read 3, iclass 31, count 0 2006.285.12:22:06.29#ibcon#about to read 4, iclass 31, count 0 2006.285.12:22:06.29#ibcon#read 4, iclass 31, count 0 2006.285.12:22:06.29#ibcon#about to read 5, iclass 31, count 0 2006.285.12:22:06.29#ibcon#read 5, iclass 31, count 0 2006.285.12:22:06.29#ibcon#about to read 6, iclass 31, count 0 2006.285.12:22:06.29#ibcon#read 6, iclass 31, count 0 2006.285.12:22:06.29#ibcon#end of sib2, iclass 31, count 0 2006.285.12:22:06.29#ibcon#*after write, iclass 31, count 0 2006.285.12:22:06.29#ibcon#*before return 0, iclass 31, count 0 2006.285.12:22:06.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:22:06.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:22:06.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:22:06.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:22:06.30$vck44/vb=4,5 2006.285.12:22:06.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.12:22:06.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.12:22:06.30#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:06.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:22:06.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:22:06.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:22:06.35#ibcon#enter wrdev, iclass 33, count 2 2006.285.12:22:06.35#ibcon#first serial, iclass 33, count 2 2006.285.12:22:06.35#ibcon#enter sib2, iclass 33, count 2 2006.285.12:22:06.35#ibcon#flushed, iclass 33, count 2 2006.285.12:22:06.35#ibcon#about to write, iclass 33, count 2 2006.285.12:22:06.35#ibcon#wrote, iclass 33, count 2 2006.285.12:22:06.35#ibcon#about to read 3, iclass 33, count 2 2006.285.12:22:06.37#ibcon#read 3, iclass 33, count 2 2006.285.12:22:06.37#ibcon#about to read 4, iclass 33, count 2 2006.285.12:22:06.37#ibcon#read 4, iclass 33, count 2 2006.285.12:22:06.37#ibcon#about to read 5, iclass 33, count 2 2006.285.12:22:06.37#ibcon#read 5, iclass 33, count 2 2006.285.12:22:06.37#ibcon#about to read 6, iclass 33, count 2 2006.285.12:22:06.37#ibcon#read 6, iclass 33, count 2 2006.285.12:22:06.37#ibcon#end of sib2, iclass 33, count 2 2006.285.12:22:06.37#ibcon#*mode == 0, iclass 33, count 2 2006.285.12:22:06.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.12:22:06.37#ibcon#[27=AT04-05\r\n] 2006.285.12:22:06.38#ibcon#*before write, iclass 33, count 2 2006.285.12:22:06.38#ibcon#enter sib2, iclass 33, count 2 2006.285.12:22:06.38#ibcon#flushed, iclass 33, count 2 2006.285.12:22:06.38#ibcon#about to write, iclass 33, count 2 2006.285.12:22:06.38#ibcon#wrote, iclass 33, count 2 2006.285.12:22:06.38#ibcon#about to read 3, iclass 33, count 2 2006.285.12:22:06.40#ibcon#read 3, iclass 33, count 2 2006.285.12:22:06.40#ibcon#about to read 4, iclass 33, count 2 2006.285.12:22:06.40#ibcon#read 4, iclass 33, count 2 2006.285.12:22:06.40#ibcon#about to read 5, iclass 33, count 2 2006.285.12:22:06.40#ibcon#read 5, iclass 33, count 2 2006.285.12:22:06.40#ibcon#about to read 6, iclass 33, count 2 2006.285.12:22:06.40#ibcon#read 6, iclass 33, count 2 2006.285.12:22:06.40#ibcon#end of sib2, iclass 33, count 2 2006.285.12:22:06.40#ibcon#*after write, iclass 33, count 2 2006.285.12:22:06.40#ibcon#*before return 0, iclass 33, count 2 2006.285.12:22:06.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:22:06.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:22:06.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.12:22:06.41#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:06.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:22:06.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:22:06.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:22:06.52#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:22:06.52#ibcon#first serial, iclass 33, count 0 2006.285.12:22:06.52#ibcon#enter sib2, iclass 33, count 0 2006.285.12:22:06.52#ibcon#flushed, iclass 33, count 0 2006.285.12:22:06.52#ibcon#about to write, iclass 33, count 0 2006.285.12:22:06.53#ibcon#wrote, iclass 33, count 0 2006.285.12:22:06.53#ibcon#about to read 3, iclass 33, count 0 2006.285.12:22:06.54#ibcon#read 3, iclass 33, count 0 2006.285.12:22:06.54#ibcon#about to read 4, iclass 33, count 0 2006.285.12:22:06.54#ibcon#read 4, iclass 33, count 0 2006.285.12:22:06.54#ibcon#about to read 5, iclass 33, count 0 2006.285.12:22:06.54#ibcon#read 5, iclass 33, count 0 2006.285.12:22:06.54#ibcon#about to read 6, iclass 33, count 0 2006.285.12:22:06.54#ibcon#read 6, iclass 33, count 0 2006.285.12:22:06.54#ibcon#end of sib2, iclass 33, count 0 2006.285.12:22:06.54#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:22:06.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:22:06.55#ibcon#[27=USB\r\n] 2006.285.12:22:06.55#ibcon#*before write, iclass 33, count 0 2006.285.12:22:06.55#ibcon#enter sib2, iclass 33, count 0 2006.285.12:22:06.55#ibcon#flushed, iclass 33, count 0 2006.285.12:22:06.55#ibcon#about to write, iclass 33, count 0 2006.285.12:22:06.55#ibcon#wrote, iclass 33, count 0 2006.285.12:22:06.55#ibcon#about to read 3, iclass 33, count 0 2006.285.12:22:06.57#ibcon#read 3, iclass 33, count 0 2006.285.12:22:06.57#ibcon#about to read 4, iclass 33, count 0 2006.285.12:22:06.57#ibcon#read 4, iclass 33, count 0 2006.285.12:22:06.57#ibcon#about to read 5, iclass 33, count 0 2006.285.12:22:06.57#ibcon#read 5, iclass 33, count 0 2006.285.12:22:06.57#ibcon#about to read 6, iclass 33, count 0 2006.285.12:22:06.57#ibcon#read 6, iclass 33, count 0 2006.285.12:22:06.57#ibcon#end of sib2, iclass 33, count 0 2006.285.12:22:06.57#ibcon#*after write, iclass 33, count 0 2006.285.12:22:06.58#ibcon#*before return 0, iclass 33, count 0 2006.285.12:22:06.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:22:06.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:22:06.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:22:06.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:22:06.58$vck44/vblo=5,709.99 2006.285.12:22:06.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.12:22:06.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.12:22:06.58#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:06.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:22:06.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:22:06.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:22:06.58#ibcon#enter wrdev, iclass 35, count 0 2006.285.12:22:06.58#ibcon#first serial, iclass 35, count 0 2006.285.12:22:06.58#ibcon#enter sib2, iclass 35, count 0 2006.285.12:22:06.58#ibcon#flushed, iclass 35, count 0 2006.285.12:22:06.58#ibcon#about to write, iclass 35, count 0 2006.285.12:22:06.58#ibcon#wrote, iclass 35, count 0 2006.285.12:22:06.58#ibcon#about to read 3, iclass 35, count 0 2006.285.12:22:06.59#ibcon#read 3, iclass 35, count 0 2006.285.12:22:06.59#ibcon#about to read 4, iclass 35, count 0 2006.285.12:22:06.59#ibcon#read 4, iclass 35, count 0 2006.285.12:22:06.59#ibcon#about to read 5, iclass 35, count 0 2006.285.12:22:06.59#ibcon#read 5, iclass 35, count 0 2006.285.12:22:06.59#ibcon#about to read 6, iclass 35, count 0 2006.285.12:22:06.59#ibcon#read 6, iclass 35, count 0 2006.285.12:22:06.59#ibcon#end of sib2, iclass 35, count 0 2006.285.12:22:06.60#ibcon#*mode == 0, iclass 35, count 0 2006.285.12:22:06.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.12:22:06.60#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.12:22:06.60#ibcon#*before write, iclass 35, count 0 2006.285.12:22:06.60#ibcon#enter sib2, iclass 35, count 0 2006.285.12:22:06.60#ibcon#flushed, iclass 35, count 0 2006.285.12:22:06.60#ibcon#about to write, iclass 35, count 0 2006.285.12:22:06.60#ibcon#wrote, iclass 35, count 0 2006.285.12:22:06.60#ibcon#about to read 3, iclass 35, count 0 2006.285.12:22:06.63#ibcon#read 3, iclass 35, count 0 2006.285.12:22:06.63#ibcon#about to read 4, iclass 35, count 0 2006.285.12:22:06.63#ibcon#read 4, iclass 35, count 0 2006.285.12:22:06.63#ibcon#about to read 5, iclass 35, count 0 2006.285.12:22:06.63#ibcon#read 5, iclass 35, count 0 2006.285.12:22:06.63#ibcon#about to read 6, iclass 35, count 0 2006.285.12:22:06.63#ibcon#read 6, iclass 35, count 0 2006.285.12:22:06.63#ibcon#end of sib2, iclass 35, count 0 2006.285.12:22:06.63#ibcon#*after write, iclass 35, count 0 2006.285.12:22:06.63#ibcon#*before return 0, iclass 35, count 0 2006.285.12:22:06.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:22:06.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:22:06.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.12:22:06.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.12:22:06.64$vck44/vb=5,4 2006.285.12:22:06.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.12:22:06.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.12:22:06.64#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:06.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:22:06.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:22:06.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:22:06.70#ibcon#enter wrdev, iclass 37, count 2 2006.285.12:22:06.70#ibcon#first serial, iclass 37, count 2 2006.285.12:22:06.70#ibcon#enter sib2, iclass 37, count 2 2006.285.12:22:06.70#ibcon#flushed, iclass 37, count 2 2006.285.12:22:06.70#ibcon#about to write, iclass 37, count 2 2006.285.12:22:06.70#ibcon#wrote, iclass 37, count 2 2006.285.12:22:06.70#ibcon#about to read 3, iclass 37, count 2 2006.285.12:22:06.71#ibcon#read 3, iclass 37, count 2 2006.285.12:22:06.71#ibcon#about to read 4, iclass 37, count 2 2006.285.12:22:06.71#ibcon#read 4, iclass 37, count 2 2006.285.12:22:06.71#ibcon#about to read 5, iclass 37, count 2 2006.285.12:22:06.71#ibcon#read 5, iclass 37, count 2 2006.285.12:22:06.71#ibcon#about to read 6, iclass 37, count 2 2006.285.12:22:06.71#ibcon#read 6, iclass 37, count 2 2006.285.12:22:06.71#ibcon#end of sib2, iclass 37, count 2 2006.285.12:22:06.71#ibcon#*mode == 0, iclass 37, count 2 2006.285.12:22:06.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.12:22:06.71#ibcon#[27=AT05-04\r\n] 2006.285.12:22:06.72#ibcon#*before write, iclass 37, count 2 2006.285.12:22:06.72#ibcon#enter sib2, iclass 37, count 2 2006.285.12:22:06.72#ibcon#flushed, iclass 37, count 2 2006.285.12:22:06.72#ibcon#about to write, iclass 37, count 2 2006.285.12:22:06.72#ibcon#wrote, iclass 37, count 2 2006.285.12:22:06.72#ibcon#about to read 3, iclass 37, count 2 2006.285.12:22:06.74#ibcon#read 3, iclass 37, count 2 2006.285.12:22:06.74#ibcon#about to read 4, iclass 37, count 2 2006.285.12:22:06.74#ibcon#read 4, iclass 37, count 2 2006.285.12:22:06.74#ibcon#about to read 5, iclass 37, count 2 2006.285.12:22:06.74#ibcon#read 5, iclass 37, count 2 2006.285.12:22:06.74#ibcon#about to read 6, iclass 37, count 2 2006.285.12:22:06.74#ibcon#read 6, iclass 37, count 2 2006.285.12:22:06.74#ibcon#end of sib2, iclass 37, count 2 2006.285.12:22:06.74#ibcon#*after write, iclass 37, count 2 2006.285.12:22:06.74#ibcon#*before return 0, iclass 37, count 2 2006.285.12:22:06.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:22:06.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:22:06.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.12:22:06.75#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:06.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:22:06.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:22:06.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:22:06.86#ibcon#enter wrdev, iclass 37, count 0 2006.285.12:22:06.86#ibcon#first serial, iclass 37, count 0 2006.285.12:22:06.86#ibcon#enter sib2, iclass 37, count 0 2006.285.12:22:06.86#ibcon#flushed, iclass 37, count 0 2006.285.12:22:06.86#ibcon#about to write, iclass 37, count 0 2006.285.12:22:06.86#ibcon#wrote, iclass 37, count 0 2006.285.12:22:06.86#ibcon#about to read 3, iclass 37, count 0 2006.285.12:22:06.88#ibcon#read 3, iclass 37, count 0 2006.285.12:22:06.88#ibcon#about to read 4, iclass 37, count 0 2006.285.12:22:06.88#ibcon#read 4, iclass 37, count 0 2006.285.12:22:06.88#ibcon#about to read 5, iclass 37, count 0 2006.285.12:22:06.88#ibcon#read 5, iclass 37, count 0 2006.285.12:22:06.88#ibcon#about to read 6, iclass 37, count 0 2006.285.12:22:06.88#ibcon#read 6, iclass 37, count 0 2006.285.12:22:06.88#ibcon#end of sib2, iclass 37, count 0 2006.285.12:22:06.88#ibcon#*mode == 0, iclass 37, count 0 2006.285.12:22:06.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.12:22:06.89#ibcon#[27=USB\r\n] 2006.285.12:22:06.89#ibcon#*before write, iclass 37, count 0 2006.285.12:22:06.89#ibcon#enter sib2, iclass 37, count 0 2006.285.12:22:06.89#ibcon#flushed, iclass 37, count 0 2006.285.12:22:06.89#ibcon#about to write, iclass 37, count 0 2006.285.12:22:06.89#ibcon#wrote, iclass 37, count 0 2006.285.12:22:06.89#ibcon#about to read 3, iclass 37, count 0 2006.285.12:22:06.91#ibcon#read 3, iclass 37, count 0 2006.285.12:22:06.91#ibcon#about to read 4, iclass 37, count 0 2006.285.12:22:06.91#ibcon#read 4, iclass 37, count 0 2006.285.12:22:06.91#ibcon#about to read 5, iclass 37, count 0 2006.285.12:22:06.91#ibcon#read 5, iclass 37, count 0 2006.285.12:22:06.91#ibcon#about to read 6, iclass 37, count 0 2006.285.12:22:06.91#ibcon#read 6, iclass 37, count 0 2006.285.12:22:06.91#ibcon#end of sib2, iclass 37, count 0 2006.285.12:22:06.91#ibcon#*after write, iclass 37, count 0 2006.285.12:22:06.91#ibcon#*before return 0, iclass 37, count 0 2006.285.12:22:06.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:22:06.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:22:06.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.12:22:06.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.12:22:06.92$vck44/vblo=6,719.99 2006.285.12:22:06.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.12:22:06.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.12:22:06.92#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:06.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:22:06.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:22:06.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:22:06.92#ibcon#enter wrdev, iclass 39, count 0 2006.285.12:22:06.92#ibcon#first serial, iclass 39, count 0 2006.285.12:22:06.92#ibcon#enter sib2, iclass 39, count 0 2006.285.12:22:06.92#ibcon#flushed, iclass 39, count 0 2006.285.12:22:06.92#ibcon#about to write, iclass 39, count 0 2006.285.12:22:06.92#ibcon#wrote, iclass 39, count 0 2006.285.12:22:06.92#ibcon#about to read 3, iclass 39, count 0 2006.285.12:22:06.93#ibcon#read 3, iclass 39, count 0 2006.285.12:22:06.93#ibcon#about to read 4, iclass 39, count 0 2006.285.12:22:06.93#ibcon#read 4, iclass 39, count 0 2006.285.12:22:06.93#ibcon#about to read 5, iclass 39, count 0 2006.285.12:22:06.93#ibcon#read 5, iclass 39, count 0 2006.285.12:22:06.93#ibcon#about to read 6, iclass 39, count 0 2006.285.12:22:06.93#ibcon#read 6, iclass 39, count 0 2006.285.12:22:06.93#ibcon#end of sib2, iclass 39, count 0 2006.285.12:22:06.93#ibcon#*mode == 0, iclass 39, count 0 2006.285.12:22:06.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.12:22:06.94#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.12:22:06.94#ibcon#*before write, iclass 39, count 0 2006.285.12:22:06.94#ibcon#enter sib2, iclass 39, count 0 2006.285.12:22:06.94#ibcon#flushed, iclass 39, count 0 2006.285.12:22:06.94#ibcon#about to write, iclass 39, count 0 2006.285.12:22:06.94#ibcon#wrote, iclass 39, count 0 2006.285.12:22:06.94#ibcon#about to read 3, iclass 39, count 0 2006.285.12:22:06.97#ibcon#read 3, iclass 39, count 0 2006.285.12:22:06.97#ibcon#about to read 4, iclass 39, count 0 2006.285.12:22:06.97#ibcon#read 4, iclass 39, count 0 2006.285.12:22:06.97#ibcon#about to read 5, iclass 39, count 0 2006.285.12:22:06.97#ibcon#read 5, iclass 39, count 0 2006.285.12:22:06.97#ibcon#about to read 6, iclass 39, count 0 2006.285.12:22:06.97#ibcon#read 6, iclass 39, count 0 2006.285.12:22:06.97#ibcon#end of sib2, iclass 39, count 0 2006.285.12:22:06.97#ibcon#*after write, iclass 39, count 0 2006.285.12:22:06.97#ibcon#*before return 0, iclass 39, count 0 2006.285.12:22:06.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:22:06.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:22:06.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.12:22:06.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.12:22:06.98$vck44/vb=6,3 2006.285.12:22:06.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.12:22:06.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.12:22:06.98#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:06.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:22:07.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:22:07.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:22:07.03#ibcon#enter wrdev, iclass 3, count 2 2006.285.12:22:07.03#ibcon#first serial, iclass 3, count 2 2006.285.12:22:07.03#ibcon#enter sib2, iclass 3, count 2 2006.285.12:22:07.03#ibcon#flushed, iclass 3, count 2 2006.285.12:22:07.03#ibcon#about to write, iclass 3, count 2 2006.285.12:22:07.03#ibcon#wrote, iclass 3, count 2 2006.285.12:22:07.03#ibcon#about to read 3, iclass 3, count 2 2006.285.12:22:07.05#ibcon#read 3, iclass 3, count 2 2006.285.12:22:07.05#ibcon#about to read 4, iclass 3, count 2 2006.285.12:22:07.05#ibcon#read 4, iclass 3, count 2 2006.285.12:22:07.05#ibcon#about to read 5, iclass 3, count 2 2006.285.12:22:07.05#ibcon#read 5, iclass 3, count 2 2006.285.12:22:07.05#ibcon#about to read 6, iclass 3, count 2 2006.285.12:22:07.05#ibcon#read 6, iclass 3, count 2 2006.285.12:22:07.05#ibcon#end of sib2, iclass 3, count 2 2006.285.12:22:07.05#ibcon#*mode == 0, iclass 3, count 2 2006.285.12:22:07.06#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.12:22:07.06#ibcon#[27=AT06-03\r\n] 2006.285.12:22:07.06#ibcon#*before write, iclass 3, count 2 2006.285.12:22:07.06#ibcon#enter sib2, iclass 3, count 2 2006.285.12:22:07.06#ibcon#flushed, iclass 3, count 2 2006.285.12:22:07.06#ibcon#about to write, iclass 3, count 2 2006.285.12:22:07.06#ibcon#wrote, iclass 3, count 2 2006.285.12:22:07.06#ibcon#about to read 3, iclass 3, count 2 2006.285.12:22:07.08#ibcon#read 3, iclass 3, count 2 2006.285.12:22:07.08#ibcon#about to read 4, iclass 3, count 2 2006.285.12:22:07.08#ibcon#read 4, iclass 3, count 2 2006.285.12:22:07.08#ibcon#about to read 5, iclass 3, count 2 2006.285.12:22:07.08#ibcon#read 5, iclass 3, count 2 2006.285.12:22:07.08#ibcon#about to read 6, iclass 3, count 2 2006.285.12:22:07.08#ibcon#read 6, iclass 3, count 2 2006.285.12:22:07.08#ibcon#end of sib2, iclass 3, count 2 2006.285.12:22:07.08#ibcon#*after write, iclass 3, count 2 2006.285.12:22:07.08#ibcon#*before return 0, iclass 3, count 2 2006.285.12:22:07.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:22:07.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:22:07.09#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.12:22:07.09#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:07.09#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:22:07.20#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:22:07.20#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:22:07.20#ibcon#enter wrdev, iclass 3, count 0 2006.285.12:22:07.20#ibcon#first serial, iclass 3, count 0 2006.285.12:22:07.20#ibcon#enter sib2, iclass 3, count 0 2006.285.12:22:07.20#ibcon#flushed, iclass 3, count 0 2006.285.12:22:07.20#ibcon#about to write, iclass 3, count 0 2006.285.12:22:07.20#ibcon#wrote, iclass 3, count 0 2006.285.12:22:07.21#ibcon#about to read 3, iclass 3, count 0 2006.285.12:22:07.22#ibcon#read 3, iclass 3, count 0 2006.285.12:22:07.22#ibcon#about to read 4, iclass 3, count 0 2006.285.12:22:07.22#ibcon#read 4, iclass 3, count 0 2006.285.12:22:07.22#ibcon#about to read 5, iclass 3, count 0 2006.285.12:22:07.22#ibcon#read 5, iclass 3, count 0 2006.285.12:22:07.22#ibcon#about to read 6, iclass 3, count 0 2006.285.12:22:07.22#ibcon#read 6, iclass 3, count 0 2006.285.12:22:07.22#ibcon#end of sib2, iclass 3, count 0 2006.285.12:22:07.22#ibcon#*mode == 0, iclass 3, count 0 2006.285.12:22:07.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.12:22:07.23#ibcon#[27=USB\r\n] 2006.285.12:22:07.23#ibcon#*before write, iclass 3, count 0 2006.285.12:22:07.23#ibcon#enter sib2, iclass 3, count 0 2006.285.12:22:07.23#ibcon#flushed, iclass 3, count 0 2006.285.12:22:07.23#ibcon#about to write, iclass 3, count 0 2006.285.12:22:07.23#ibcon#wrote, iclass 3, count 0 2006.285.12:22:07.23#ibcon#about to read 3, iclass 3, count 0 2006.285.12:22:07.25#ibcon#read 3, iclass 3, count 0 2006.285.12:22:07.25#ibcon#about to read 4, iclass 3, count 0 2006.285.12:22:07.25#ibcon#read 4, iclass 3, count 0 2006.285.12:22:07.25#ibcon#about to read 5, iclass 3, count 0 2006.285.12:22:07.25#ibcon#read 5, iclass 3, count 0 2006.285.12:22:07.25#ibcon#about to read 6, iclass 3, count 0 2006.285.12:22:07.25#ibcon#read 6, iclass 3, count 0 2006.285.12:22:07.25#ibcon#end of sib2, iclass 3, count 0 2006.285.12:22:07.25#ibcon#*after write, iclass 3, count 0 2006.285.12:22:07.25#ibcon#*before return 0, iclass 3, count 0 2006.285.12:22:07.26#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:22:07.26#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:22:07.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.12:22:07.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.12:22:07.26$vck44/vblo=7,734.99 2006.285.12:22:07.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.12:22:07.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.12:22:07.26#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:07.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:22:07.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:22:07.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:22:07.26#ibcon#enter wrdev, iclass 5, count 0 2006.285.12:22:07.26#ibcon#first serial, iclass 5, count 0 2006.285.12:22:07.26#ibcon#enter sib2, iclass 5, count 0 2006.285.12:22:07.26#ibcon#flushed, iclass 5, count 0 2006.285.12:22:07.26#ibcon#about to write, iclass 5, count 0 2006.285.12:22:07.26#ibcon#wrote, iclass 5, count 0 2006.285.12:22:07.26#ibcon#about to read 3, iclass 5, count 0 2006.285.12:22:07.27#ibcon#read 3, iclass 5, count 0 2006.285.12:22:07.27#ibcon#about to read 4, iclass 5, count 0 2006.285.12:22:07.27#ibcon#read 4, iclass 5, count 0 2006.285.12:22:07.27#ibcon#about to read 5, iclass 5, count 0 2006.285.12:22:07.27#ibcon#read 5, iclass 5, count 0 2006.285.12:22:07.27#ibcon#about to read 6, iclass 5, count 0 2006.285.12:22:07.27#ibcon#read 6, iclass 5, count 0 2006.285.12:22:07.27#ibcon#end of sib2, iclass 5, count 0 2006.285.12:22:07.27#ibcon#*mode == 0, iclass 5, count 0 2006.285.12:22:07.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.12:22:07.28#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.12:22:07.28#ibcon#*before write, iclass 5, count 0 2006.285.12:22:07.28#ibcon#enter sib2, iclass 5, count 0 2006.285.12:22:07.28#ibcon#flushed, iclass 5, count 0 2006.285.12:22:07.28#ibcon#about to write, iclass 5, count 0 2006.285.12:22:07.28#ibcon#wrote, iclass 5, count 0 2006.285.12:22:07.28#ibcon#about to read 3, iclass 5, count 0 2006.285.12:22:07.31#ibcon#read 3, iclass 5, count 0 2006.285.12:22:07.31#ibcon#about to read 4, iclass 5, count 0 2006.285.12:22:07.31#ibcon#read 4, iclass 5, count 0 2006.285.12:22:07.31#ibcon#about to read 5, iclass 5, count 0 2006.285.12:22:07.31#ibcon#read 5, iclass 5, count 0 2006.285.12:22:07.31#ibcon#about to read 6, iclass 5, count 0 2006.285.12:22:07.31#ibcon#read 6, iclass 5, count 0 2006.285.12:22:07.31#ibcon#end of sib2, iclass 5, count 0 2006.285.12:22:07.31#ibcon#*after write, iclass 5, count 0 2006.285.12:22:07.31#ibcon#*before return 0, iclass 5, count 0 2006.285.12:22:07.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:22:07.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:22:07.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.12:22:07.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.12:22:07.32$vck44/vb=7,4 2006.285.12:22:07.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.12:22:07.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.12:22:07.32#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:07.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:22:07.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:22:07.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:22:07.37#ibcon#enter wrdev, iclass 7, count 2 2006.285.12:22:07.37#ibcon#first serial, iclass 7, count 2 2006.285.12:22:07.37#ibcon#enter sib2, iclass 7, count 2 2006.285.12:22:07.37#ibcon#flushed, iclass 7, count 2 2006.285.12:22:07.37#ibcon#about to write, iclass 7, count 2 2006.285.12:22:07.37#ibcon#wrote, iclass 7, count 2 2006.285.12:22:07.37#ibcon#about to read 3, iclass 7, count 2 2006.285.12:22:07.39#ibcon#read 3, iclass 7, count 2 2006.285.12:22:07.39#ibcon#about to read 4, iclass 7, count 2 2006.285.12:22:07.39#ibcon#read 4, iclass 7, count 2 2006.285.12:22:07.39#ibcon#about to read 5, iclass 7, count 2 2006.285.12:22:07.39#ibcon#read 5, iclass 7, count 2 2006.285.12:22:07.39#ibcon#about to read 6, iclass 7, count 2 2006.285.12:22:07.39#ibcon#read 6, iclass 7, count 2 2006.285.12:22:07.39#ibcon#end of sib2, iclass 7, count 2 2006.285.12:22:07.39#ibcon#*mode == 0, iclass 7, count 2 2006.285.12:22:07.39#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.12:22:07.39#ibcon#[27=AT07-04\r\n] 2006.285.12:22:07.40#ibcon#*before write, iclass 7, count 2 2006.285.12:22:07.40#ibcon#enter sib2, iclass 7, count 2 2006.285.12:22:07.40#ibcon#flushed, iclass 7, count 2 2006.285.12:22:07.40#ibcon#about to write, iclass 7, count 2 2006.285.12:22:07.40#ibcon#wrote, iclass 7, count 2 2006.285.12:22:07.40#ibcon#about to read 3, iclass 7, count 2 2006.285.12:22:07.42#ibcon#read 3, iclass 7, count 2 2006.285.12:22:07.42#ibcon#about to read 4, iclass 7, count 2 2006.285.12:22:07.42#ibcon#read 4, iclass 7, count 2 2006.285.12:22:07.42#ibcon#about to read 5, iclass 7, count 2 2006.285.12:22:07.42#ibcon#read 5, iclass 7, count 2 2006.285.12:22:07.42#ibcon#about to read 6, iclass 7, count 2 2006.285.12:22:07.42#ibcon#read 6, iclass 7, count 2 2006.285.12:22:07.42#ibcon#end of sib2, iclass 7, count 2 2006.285.12:22:07.42#ibcon#*after write, iclass 7, count 2 2006.285.12:22:07.42#ibcon#*before return 0, iclass 7, count 2 2006.285.12:22:07.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:22:07.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:22:07.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.12:22:07.43#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:07.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:22:07.54#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:22:07.54#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:22:07.54#ibcon#enter wrdev, iclass 7, count 0 2006.285.12:22:07.54#ibcon#first serial, iclass 7, count 0 2006.285.12:22:07.54#ibcon#enter sib2, iclass 7, count 0 2006.285.12:22:07.54#ibcon#flushed, iclass 7, count 0 2006.285.12:22:07.54#ibcon#about to write, iclass 7, count 0 2006.285.12:22:07.55#ibcon#wrote, iclass 7, count 0 2006.285.12:22:07.55#ibcon#about to read 3, iclass 7, count 0 2006.285.12:22:07.56#ibcon#read 3, iclass 7, count 0 2006.285.12:22:07.56#ibcon#about to read 4, iclass 7, count 0 2006.285.12:22:07.56#ibcon#read 4, iclass 7, count 0 2006.285.12:22:07.56#ibcon#about to read 5, iclass 7, count 0 2006.285.12:22:07.56#ibcon#read 5, iclass 7, count 0 2006.285.12:22:07.56#ibcon#about to read 6, iclass 7, count 0 2006.285.12:22:07.56#ibcon#read 6, iclass 7, count 0 2006.285.12:22:07.56#ibcon#end of sib2, iclass 7, count 0 2006.285.12:22:07.56#ibcon#*mode == 0, iclass 7, count 0 2006.285.12:22:07.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.12:22:07.57#ibcon#[27=USB\r\n] 2006.285.12:22:07.57#ibcon#*before write, iclass 7, count 0 2006.285.12:22:07.57#ibcon#enter sib2, iclass 7, count 0 2006.285.12:22:07.57#ibcon#flushed, iclass 7, count 0 2006.285.12:22:07.57#ibcon#about to write, iclass 7, count 0 2006.285.12:22:07.57#ibcon#wrote, iclass 7, count 0 2006.285.12:22:07.57#ibcon#about to read 3, iclass 7, count 0 2006.285.12:22:07.59#ibcon#read 3, iclass 7, count 0 2006.285.12:22:07.59#ibcon#about to read 4, iclass 7, count 0 2006.285.12:22:07.59#ibcon#read 4, iclass 7, count 0 2006.285.12:22:07.59#ibcon#about to read 5, iclass 7, count 0 2006.285.12:22:07.59#ibcon#read 5, iclass 7, count 0 2006.285.12:22:07.59#ibcon#about to read 6, iclass 7, count 0 2006.285.12:22:07.59#ibcon#read 6, iclass 7, count 0 2006.285.12:22:07.59#ibcon#end of sib2, iclass 7, count 0 2006.285.12:22:07.59#ibcon#*after write, iclass 7, count 0 2006.285.12:22:07.59#ibcon#*before return 0, iclass 7, count 0 2006.285.12:22:07.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:22:07.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:22:07.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.12:22:07.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.12:22:07.60$vck44/vblo=8,744.99 2006.285.12:22:07.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.12:22:07.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.12:22:07.60#ibcon#ireg 17 cls_cnt 0 2006.285.12:22:07.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:22:07.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:22:07.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:22:07.60#ibcon#enter wrdev, iclass 11, count 0 2006.285.12:22:07.60#ibcon#first serial, iclass 11, count 0 2006.285.12:22:07.60#ibcon#enter sib2, iclass 11, count 0 2006.285.12:22:07.60#ibcon#flushed, iclass 11, count 0 2006.285.12:22:07.60#ibcon#about to write, iclass 11, count 0 2006.285.12:22:07.60#ibcon#wrote, iclass 11, count 0 2006.285.12:22:07.60#ibcon#about to read 3, iclass 11, count 0 2006.285.12:22:07.61#ibcon#read 3, iclass 11, count 0 2006.285.12:22:07.61#ibcon#about to read 4, iclass 11, count 0 2006.285.12:22:07.61#ibcon#read 4, iclass 11, count 0 2006.285.12:22:07.61#ibcon#about to read 5, iclass 11, count 0 2006.285.12:22:07.61#ibcon#read 5, iclass 11, count 0 2006.285.12:22:07.61#ibcon#about to read 6, iclass 11, count 0 2006.285.12:22:07.61#ibcon#read 6, iclass 11, count 0 2006.285.12:22:07.61#ibcon#end of sib2, iclass 11, count 0 2006.285.12:22:07.61#ibcon#*mode == 0, iclass 11, count 0 2006.285.12:22:07.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.12:22:07.62#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.12:22:07.62#ibcon#*before write, iclass 11, count 0 2006.285.12:22:07.62#ibcon#enter sib2, iclass 11, count 0 2006.285.12:22:07.62#ibcon#flushed, iclass 11, count 0 2006.285.12:22:07.62#ibcon#about to write, iclass 11, count 0 2006.285.12:22:07.62#ibcon#wrote, iclass 11, count 0 2006.285.12:22:07.62#ibcon#about to read 3, iclass 11, count 0 2006.285.12:22:07.65#ibcon#read 3, iclass 11, count 0 2006.285.12:22:07.65#ibcon#about to read 4, iclass 11, count 0 2006.285.12:22:07.65#ibcon#read 4, iclass 11, count 0 2006.285.12:22:07.65#ibcon#about to read 5, iclass 11, count 0 2006.285.12:22:07.65#ibcon#read 5, iclass 11, count 0 2006.285.12:22:07.65#ibcon#about to read 6, iclass 11, count 0 2006.285.12:22:07.65#ibcon#read 6, iclass 11, count 0 2006.285.12:22:07.65#ibcon#end of sib2, iclass 11, count 0 2006.285.12:22:07.65#ibcon#*after write, iclass 11, count 0 2006.285.12:22:07.65#ibcon#*before return 0, iclass 11, count 0 2006.285.12:22:07.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:22:07.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:22:07.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.12:22:07.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.12:22:07.66$vck44/vb=8,4 2006.285.12:22:07.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.12:22:07.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.12:22:07.66#ibcon#ireg 11 cls_cnt 2 2006.285.12:22:07.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:22:07.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:22:07.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:22:07.71#ibcon#enter wrdev, iclass 13, count 2 2006.285.12:22:07.71#ibcon#first serial, iclass 13, count 2 2006.285.12:22:07.71#ibcon#enter sib2, iclass 13, count 2 2006.285.12:22:07.71#ibcon#flushed, iclass 13, count 2 2006.285.12:22:07.71#ibcon#about to write, iclass 13, count 2 2006.285.12:22:07.71#ibcon#wrote, iclass 13, count 2 2006.285.12:22:07.72#ibcon#about to read 3, iclass 13, count 2 2006.285.12:22:07.73#ibcon#read 3, iclass 13, count 2 2006.285.12:22:07.73#ibcon#about to read 4, iclass 13, count 2 2006.285.12:22:07.73#ibcon#read 4, iclass 13, count 2 2006.285.12:22:07.73#ibcon#about to read 5, iclass 13, count 2 2006.285.12:22:07.73#ibcon#read 5, iclass 13, count 2 2006.285.12:22:07.73#ibcon#about to read 6, iclass 13, count 2 2006.285.12:22:07.73#ibcon#read 6, iclass 13, count 2 2006.285.12:22:07.73#ibcon#end of sib2, iclass 13, count 2 2006.285.12:22:07.73#ibcon#*mode == 0, iclass 13, count 2 2006.285.12:22:07.73#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.12:22:07.74#ibcon#[27=AT08-04\r\n] 2006.285.12:22:07.74#ibcon#*before write, iclass 13, count 2 2006.285.12:22:07.74#ibcon#enter sib2, iclass 13, count 2 2006.285.12:22:07.74#ibcon#flushed, iclass 13, count 2 2006.285.12:22:07.74#ibcon#about to write, iclass 13, count 2 2006.285.12:22:07.74#ibcon#wrote, iclass 13, count 2 2006.285.12:22:07.74#ibcon#about to read 3, iclass 13, count 2 2006.285.12:22:07.76#ibcon#read 3, iclass 13, count 2 2006.285.12:22:07.76#ibcon#about to read 4, iclass 13, count 2 2006.285.12:22:07.76#ibcon#read 4, iclass 13, count 2 2006.285.12:22:07.76#ibcon#about to read 5, iclass 13, count 2 2006.285.12:22:07.76#ibcon#read 5, iclass 13, count 2 2006.285.12:22:07.76#ibcon#about to read 6, iclass 13, count 2 2006.285.12:22:07.76#ibcon#read 6, iclass 13, count 2 2006.285.12:22:07.76#ibcon#end of sib2, iclass 13, count 2 2006.285.12:22:07.76#ibcon#*after write, iclass 13, count 2 2006.285.12:22:07.76#ibcon#*before return 0, iclass 13, count 2 2006.285.12:22:07.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:22:07.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:22:07.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.12:22:07.77#ibcon#ireg 7 cls_cnt 0 2006.285.12:22:07.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:22:07.88#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:22:07.88#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:22:07.88#ibcon#enter wrdev, iclass 13, count 0 2006.285.12:22:07.88#ibcon#first serial, iclass 13, count 0 2006.285.12:22:07.88#ibcon#enter sib2, iclass 13, count 0 2006.285.12:22:07.88#ibcon#flushed, iclass 13, count 0 2006.285.12:22:07.88#ibcon#about to write, iclass 13, count 0 2006.285.12:22:07.88#ibcon#wrote, iclass 13, count 0 2006.285.12:22:07.88#ibcon#about to read 3, iclass 13, count 0 2006.285.12:22:07.90#ibcon#read 3, iclass 13, count 0 2006.285.12:22:07.90#ibcon#about to read 4, iclass 13, count 0 2006.285.12:22:07.90#ibcon#read 4, iclass 13, count 0 2006.285.12:22:07.90#ibcon#about to read 5, iclass 13, count 0 2006.285.12:22:07.90#ibcon#read 5, iclass 13, count 0 2006.285.12:22:07.90#ibcon#about to read 6, iclass 13, count 0 2006.285.12:22:07.90#ibcon#read 6, iclass 13, count 0 2006.285.12:22:07.90#ibcon#end of sib2, iclass 13, count 0 2006.285.12:22:07.90#ibcon#*mode == 0, iclass 13, count 0 2006.285.12:22:07.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.12:22:07.90#ibcon#[27=USB\r\n] 2006.285.12:22:07.91#ibcon#*before write, iclass 13, count 0 2006.285.12:22:07.91#ibcon#enter sib2, iclass 13, count 0 2006.285.12:22:07.91#ibcon#flushed, iclass 13, count 0 2006.285.12:22:07.91#ibcon#about to write, iclass 13, count 0 2006.285.12:22:07.91#ibcon#wrote, iclass 13, count 0 2006.285.12:22:07.91#ibcon#about to read 3, iclass 13, count 0 2006.285.12:22:07.93#ibcon#read 3, iclass 13, count 0 2006.285.12:22:07.93#ibcon#about to read 4, iclass 13, count 0 2006.285.12:22:07.93#ibcon#read 4, iclass 13, count 0 2006.285.12:22:07.93#ibcon#about to read 5, iclass 13, count 0 2006.285.12:22:07.93#ibcon#read 5, iclass 13, count 0 2006.285.12:22:07.93#ibcon#about to read 6, iclass 13, count 0 2006.285.12:22:07.93#ibcon#read 6, iclass 13, count 0 2006.285.12:22:07.93#ibcon#end of sib2, iclass 13, count 0 2006.285.12:22:07.93#ibcon#*after write, iclass 13, count 0 2006.285.12:22:07.93#ibcon#*before return 0, iclass 13, count 0 2006.285.12:22:07.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:22:07.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:22:07.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.12:22:07.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.12:22:07.94$vck44/vabw=wide 2006.285.12:22:07.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.12:22:07.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.12:22:07.94#ibcon#ireg 8 cls_cnt 0 2006.285.12:22:07.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:22:07.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:22:07.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:22:07.94#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:22:07.94#ibcon#first serial, iclass 15, count 0 2006.285.12:22:07.94#ibcon#enter sib2, iclass 15, count 0 2006.285.12:22:07.94#ibcon#flushed, iclass 15, count 0 2006.285.12:22:07.94#ibcon#about to write, iclass 15, count 0 2006.285.12:22:07.94#ibcon#wrote, iclass 15, count 0 2006.285.12:22:07.94#ibcon#about to read 3, iclass 15, count 0 2006.285.12:22:07.95#ibcon#read 3, iclass 15, count 0 2006.285.12:22:07.95#ibcon#about to read 4, iclass 15, count 0 2006.285.12:22:07.95#ibcon#read 4, iclass 15, count 0 2006.285.12:22:07.95#ibcon#about to read 5, iclass 15, count 0 2006.285.12:22:07.95#ibcon#read 5, iclass 15, count 0 2006.285.12:22:07.95#ibcon#about to read 6, iclass 15, count 0 2006.285.12:22:07.95#ibcon#read 6, iclass 15, count 0 2006.285.12:22:07.95#ibcon#end of sib2, iclass 15, count 0 2006.285.12:22:07.95#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:22:07.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:22:07.96#ibcon#[25=BW32\r\n] 2006.285.12:22:07.96#ibcon#*before write, iclass 15, count 0 2006.285.12:22:07.96#ibcon#enter sib2, iclass 15, count 0 2006.285.12:22:07.96#ibcon#flushed, iclass 15, count 0 2006.285.12:22:07.96#ibcon#about to write, iclass 15, count 0 2006.285.12:22:07.96#ibcon#wrote, iclass 15, count 0 2006.285.12:22:07.96#ibcon#about to read 3, iclass 15, count 0 2006.285.12:22:07.98#ibcon#read 3, iclass 15, count 0 2006.285.12:22:07.98#ibcon#about to read 4, iclass 15, count 0 2006.285.12:22:07.98#ibcon#read 4, iclass 15, count 0 2006.285.12:22:07.98#ibcon#about to read 5, iclass 15, count 0 2006.285.12:22:07.98#ibcon#read 5, iclass 15, count 0 2006.285.12:22:07.98#ibcon#about to read 6, iclass 15, count 0 2006.285.12:22:07.98#ibcon#read 6, iclass 15, count 0 2006.285.12:22:07.98#ibcon#end of sib2, iclass 15, count 0 2006.285.12:22:07.98#ibcon#*after write, iclass 15, count 0 2006.285.12:22:07.98#ibcon#*before return 0, iclass 15, count 0 2006.285.12:22:07.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:22:07.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:22:07.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:22:07.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:22:07.99$vck44/vbbw=wide 2006.285.12:22:07.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.12:22:07.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.12:22:07.99#ibcon#ireg 8 cls_cnt 0 2006.285.12:22:07.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:22:08.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:22:08.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:22:08.05#ibcon#enter wrdev, iclass 17, count 0 2006.285.12:22:08.05#ibcon#first serial, iclass 17, count 0 2006.285.12:22:08.05#ibcon#enter sib2, iclass 17, count 0 2006.285.12:22:08.05#ibcon#flushed, iclass 17, count 0 2006.285.12:22:08.05#ibcon#about to write, iclass 17, count 0 2006.285.12:22:08.05#ibcon#wrote, iclass 17, count 0 2006.285.12:22:08.05#ibcon#about to read 3, iclass 17, count 0 2006.285.12:22:08.07#ibcon#read 3, iclass 17, count 0 2006.285.12:22:08.07#ibcon#about to read 4, iclass 17, count 0 2006.285.12:22:08.07#ibcon#read 4, iclass 17, count 0 2006.285.12:22:08.07#ibcon#about to read 5, iclass 17, count 0 2006.285.12:22:08.07#ibcon#read 5, iclass 17, count 0 2006.285.12:22:08.07#ibcon#about to read 6, iclass 17, count 0 2006.285.12:22:08.07#ibcon#read 6, iclass 17, count 0 2006.285.12:22:08.07#ibcon#end of sib2, iclass 17, count 0 2006.285.12:22:08.07#ibcon#*mode == 0, iclass 17, count 0 2006.285.12:22:08.08#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.12:22:08.08#ibcon#[27=BW32\r\n] 2006.285.12:22:08.08#ibcon#*before write, iclass 17, count 0 2006.285.12:22:08.08#ibcon#enter sib2, iclass 17, count 0 2006.285.12:22:08.08#ibcon#flushed, iclass 17, count 0 2006.285.12:22:08.08#ibcon#about to write, iclass 17, count 0 2006.285.12:22:08.08#ibcon#wrote, iclass 17, count 0 2006.285.12:22:08.08#ibcon#about to read 3, iclass 17, count 0 2006.285.12:22:08.10#ibcon#read 3, iclass 17, count 0 2006.285.12:22:08.10#ibcon#about to read 4, iclass 17, count 0 2006.285.12:22:08.10#ibcon#read 4, iclass 17, count 0 2006.285.12:22:08.10#ibcon#about to read 5, iclass 17, count 0 2006.285.12:22:08.10#ibcon#read 5, iclass 17, count 0 2006.285.12:22:08.10#ibcon#about to read 6, iclass 17, count 0 2006.285.12:22:08.10#ibcon#read 6, iclass 17, count 0 2006.285.12:22:08.10#ibcon#end of sib2, iclass 17, count 0 2006.285.12:22:08.10#ibcon#*after write, iclass 17, count 0 2006.285.12:22:08.10#ibcon#*before return 0, iclass 17, count 0 2006.285.12:22:08.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:22:08.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:22:08.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.12:22:08.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.12:22:08.11$setupk4/ifdk4 2006.285.12:22:08.11$ifdk4/lo= 2006.285.12:22:08.11$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.12:22:08.11$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.12:22:08.11$ifdk4/patch= 2006.285.12:22:08.11$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.12:22:08.11$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.12:22:08.11$setupk4/!*+20s 2006.285.12:22:15.96#abcon#<5=/05 1.1 1.8 18.84 951015.5\r\n> 2006.285.12:22:15.98#abcon#{5=INTERFACE CLEAR} 2006.285.12:22:16.04#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:22:16.14#trakl#Source acquired 2006.285.12:22:18.15#flagr#flagr/antenna,acquired 2006.285.12:22:22.63$setupk4/"tpicd 2006.285.12:22:22.64$setupk4/echo=off 2006.285.12:22:22.64$setupk4/xlog=off 2006.285.12:22:22.64:!2006.285.12:26:58 2006.285.12:26:58.01:preob 2006.285.12:26:59.14/onsource/TRACKING 2006.285.12:26:59.14:!2006.285.12:27:08 2006.285.12:27:08.00:"tape 2006.285.12:27:08.00:"st=record 2006.285.12:27:08.00:data_valid=on 2006.285.12:27:08.00:midob 2006.285.12:27:08.14/onsource/TRACKING 2006.285.12:27:08.15/wx/18.79,1015.5,96 2006.285.12:27:08.23/cable/+6.4940E-03 2006.285.12:27:09.32/va/01,07,usb,yes,32,34 2006.285.12:27:09.32/va/02,06,usb,yes,32,32 2006.285.12:27:09.32/va/03,07,usb,yes,31,33 2006.285.12:27:09.32/va/04,06,usb,yes,33,34 2006.285.12:27:09.32/va/05,03,usb,yes,32,32 2006.285.12:27:09.32/va/06,04,usb,yes,29,28 2006.285.12:27:09.32/va/07,04,usb,yes,29,30 2006.285.12:27:09.32/va/08,03,usb,yes,30,37 2006.285.12:27:09.55/valo/01,524.99,yes,locked 2006.285.12:27:09.55/valo/02,534.99,yes,locked 2006.285.12:27:09.55/valo/03,564.99,yes,locked 2006.285.12:27:09.55/valo/04,624.99,yes,locked 2006.285.12:27:09.55/valo/05,734.99,yes,locked 2006.285.12:27:09.55/valo/06,814.99,yes,locked 2006.285.12:27:09.55/valo/07,864.99,yes,locked 2006.285.12:27:09.55/valo/08,884.99,yes,locked 2006.285.12:27:10.64/vb/01,04,usb,yes,30,28 2006.285.12:27:10.64/vb/02,05,usb,yes,28,28 2006.285.12:27:10.64/vb/03,04,usb,yes,29,32 2006.285.12:27:10.64/vb/04,05,usb,yes,29,28 2006.285.12:27:10.64/vb/05,04,usb,yes,26,28 2006.285.12:27:10.64/vb/06,03,usb,yes,37,33 2006.285.12:27:10.64/vb/07,04,usb,yes,30,30 2006.285.12:27:10.64/vb/08,04,usb,yes,27,31 2006.285.12:27:10.87/vblo/01,629.99,yes,locked 2006.285.12:27:10.87/vblo/02,634.99,yes,locked 2006.285.12:27:10.87/vblo/03,649.99,yes,locked 2006.285.12:27:10.87/vblo/04,679.99,yes,locked 2006.285.12:27:10.87/vblo/05,709.99,yes,locked 2006.285.12:27:10.87/vblo/06,719.99,yes,locked 2006.285.12:27:10.87/vblo/07,734.99,yes,locked 2006.285.12:27:10.87/vblo/08,744.99,yes,locked 2006.285.12:27:11.02/vabw/8 2006.285.12:27:11.17/vbbw/8 2006.285.12:27:11.26/xfe/off,on,12.2 2006.285.12:27:11.65/ifatt/23,28,28,28 2006.285.12:27:12.07/fmout-gps/S +2.56E-07 2006.285.12:27:12.09:!2006.285.12:28:28 2006.285.12:28:28.00:data_valid=off 2006.285.12:28:28.00:"et 2006.285.12:28:28.00:!+3s 2006.285.12:28:31.02:"tape 2006.285.12:28:31.02:postob 2006.285.12:28:31.14/cable/+6.4948E-03 2006.285.12:28:31.14/wx/18.78,1015.5,96 2006.285.12:28:31.20/fmout-gps/S +2.54E-07 2006.285.12:28:31.20:scan_name=285-1230,jd0610,40 2006.285.12:28:31.20:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.285.12:28:32.13#flagr#flagr/antenna,new-source 2006.285.12:28:32.14:checkk5 2006.285.12:28:32.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.12:28:32.93/chk_autoobs//k5ts2/ autoobs is running! 2006.285.12:28:33.32/chk_autoobs//k5ts3/ autoobs is running! 2006.285.12:28:33.82/chk_autoobs//k5ts4/ autoobs is running! 2006.285.12:28:34.17/chk_obsdata//k5ts1/T2851227??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.12:28:34.60/chk_obsdata//k5ts2/T2851227??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.12:28:34.95/chk_obsdata//k5ts3/T2851227??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.12:28:35.31/chk_obsdata//k5ts4/T2851227??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.12:28:36.13/k5log//k5ts1_log_newline 2006.285.12:28:36.96/k5log//k5ts2_log_newline 2006.285.12:28:37.76/k5log//k5ts3_log_newline 2006.285.12:28:38.59/k5log//k5ts4_log_newline 2006.285.12:28:38.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.12:28:38.61:setupk4=1 2006.285.12:28:38.61$setupk4/echo=on 2006.285.12:28:38.61$setupk4/pcalon 2006.285.12:28:38.61$pcalon/"no phase cal control is implemented here 2006.285.12:28:38.61$setupk4/"tpicd=stop 2006.285.12:28:38.61$setupk4/"rec=synch_on 2006.285.12:28:38.61$setupk4/"rec_mode=128 2006.285.12:28:38.61$setupk4/!* 2006.285.12:28:38.61$setupk4/recpk4 2006.285.12:28:38.61$recpk4/recpatch= 2006.285.12:28:38.61$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.12:28:38.61$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.12:28:38.61$setupk4/vck44 2006.285.12:28:38.61$vck44/valo=1,524.99 2006.285.12:28:38.61#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.12:28:38.61#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.12:28:38.61#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:38.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:28:38.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:28:38.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:28:38.61#ibcon#enter wrdev, iclass 30, count 0 2006.285.12:28:38.61#ibcon#first serial, iclass 30, count 0 2006.285.12:28:38.61#ibcon#enter sib2, iclass 30, count 0 2006.285.12:28:38.61#ibcon#flushed, iclass 30, count 0 2006.285.12:28:38.61#ibcon#about to write, iclass 30, count 0 2006.285.12:28:38.61#ibcon#wrote, iclass 30, count 0 2006.285.12:28:38.61#ibcon#about to read 3, iclass 30, count 0 2006.285.12:28:38.63#ibcon#read 3, iclass 30, count 0 2006.285.12:28:38.63#ibcon#about to read 4, iclass 30, count 0 2006.285.12:28:38.63#ibcon#read 4, iclass 30, count 0 2006.285.12:28:38.63#ibcon#about to read 5, iclass 30, count 0 2006.285.12:28:38.63#ibcon#read 5, iclass 30, count 0 2006.285.12:28:38.63#ibcon#about to read 6, iclass 30, count 0 2006.285.12:28:38.63#ibcon#read 6, iclass 30, count 0 2006.285.12:28:38.63#ibcon#end of sib2, iclass 30, count 0 2006.285.12:28:38.63#ibcon#*mode == 0, iclass 30, count 0 2006.285.12:28:38.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.12:28:38.63#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.12:28:38.63#ibcon#*before write, iclass 30, count 0 2006.285.12:28:38.63#ibcon#enter sib2, iclass 30, count 0 2006.285.12:28:38.63#ibcon#flushed, iclass 30, count 0 2006.285.12:28:38.63#ibcon#about to write, iclass 30, count 0 2006.285.12:28:38.63#ibcon#wrote, iclass 30, count 0 2006.285.12:28:38.63#ibcon#about to read 3, iclass 30, count 0 2006.285.12:28:38.68#ibcon#read 3, iclass 30, count 0 2006.285.12:28:38.68#ibcon#about to read 4, iclass 30, count 0 2006.285.12:28:38.68#ibcon#read 4, iclass 30, count 0 2006.285.12:28:38.68#ibcon#about to read 5, iclass 30, count 0 2006.285.12:28:38.68#ibcon#read 5, iclass 30, count 0 2006.285.12:28:38.68#ibcon#about to read 6, iclass 30, count 0 2006.285.12:28:38.68#ibcon#read 6, iclass 30, count 0 2006.285.12:28:38.68#ibcon#end of sib2, iclass 30, count 0 2006.285.12:28:38.68#ibcon#*after write, iclass 30, count 0 2006.285.12:28:38.68#ibcon#*before return 0, iclass 30, count 0 2006.285.12:28:38.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:28:38.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:28:38.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.12:28:38.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.12:28:38.68$vck44/va=1,7 2006.285.12:28:38.68#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.12:28:38.68#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.12:28:38.68#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:38.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:28:38.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:28:38.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:28:38.68#ibcon#enter wrdev, iclass 32, count 2 2006.285.12:28:38.68#ibcon#first serial, iclass 32, count 2 2006.285.12:28:38.68#ibcon#enter sib2, iclass 32, count 2 2006.285.12:28:38.68#ibcon#flushed, iclass 32, count 2 2006.285.12:28:38.68#ibcon#about to write, iclass 32, count 2 2006.285.12:28:38.68#ibcon#wrote, iclass 32, count 2 2006.285.12:28:38.68#ibcon#about to read 3, iclass 32, count 2 2006.285.12:28:38.70#ibcon#read 3, iclass 32, count 2 2006.285.12:28:38.70#ibcon#about to read 4, iclass 32, count 2 2006.285.12:28:38.70#ibcon#read 4, iclass 32, count 2 2006.285.12:28:38.70#ibcon#about to read 5, iclass 32, count 2 2006.285.12:28:38.70#ibcon#read 5, iclass 32, count 2 2006.285.12:28:38.70#ibcon#about to read 6, iclass 32, count 2 2006.285.12:28:38.70#ibcon#read 6, iclass 32, count 2 2006.285.12:28:38.70#ibcon#end of sib2, iclass 32, count 2 2006.285.12:28:38.70#ibcon#*mode == 0, iclass 32, count 2 2006.285.12:28:38.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.12:28:38.70#ibcon#[25=AT01-07\r\n] 2006.285.12:28:38.70#ibcon#*before write, iclass 32, count 2 2006.285.12:28:38.70#ibcon#enter sib2, iclass 32, count 2 2006.285.12:28:38.70#ibcon#flushed, iclass 32, count 2 2006.285.12:28:38.70#ibcon#about to write, iclass 32, count 2 2006.285.12:28:38.70#ibcon#wrote, iclass 32, count 2 2006.285.12:28:38.70#ibcon#about to read 3, iclass 32, count 2 2006.285.12:28:38.73#ibcon#read 3, iclass 32, count 2 2006.285.12:28:38.73#ibcon#about to read 4, iclass 32, count 2 2006.285.12:28:38.73#ibcon#read 4, iclass 32, count 2 2006.285.12:28:38.73#ibcon#about to read 5, iclass 32, count 2 2006.285.12:28:38.73#ibcon#read 5, iclass 32, count 2 2006.285.12:28:38.73#ibcon#about to read 6, iclass 32, count 2 2006.285.12:28:38.73#ibcon#read 6, iclass 32, count 2 2006.285.12:28:38.73#ibcon#end of sib2, iclass 32, count 2 2006.285.12:28:38.73#ibcon#*after write, iclass 32, count 2 2006.285.12:28:38.73#ibcon#*before return 0, iclass 32, count 2 2006.285.12:28:38.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:28:38.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:28:38.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.12:28:38.73#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:38.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:28:38.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:28:38.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:28:38.85#ibcon#enter wrdev, iclass 32, count 0 2006.285.12:28:38.85#ibcon#first serial, iclass 32, count 0 2006.285.12:28:38.85#ibcon#enter sib2, iclass 32, count 0 2006.285.12:28:38.85#ibcon#flushed, iclass 32, count 0 2006.285.12:28:38.85#ibcon#about to write, iclass 32, count 0 2006.285.12:28:38.85#ibcon#wrote, iclass 32, count 0 2006.285.12:28:38.85#ibcon#about to read 3, iclass 32, count 0 2006.285.12:28:38.87#ibcon#read 3, iclass 32, count 0 2006.285.12:28:38.87#ibcon#about to read 4, iclass 32, count 0 2006.285.12:28:38.87#ibcon#read 4, iclass 32, count 0 2006.285.12:28:38.87#ibcon#about to read 5, iclass 32, count 0 2006.285.12:28:38.87#ibcon#read 5, iclass 32, count 0 2006.285.12:28:38.87#ibcon#about to read 6, iclass 32, count 0 2006.285.12:28:38.87#ibcon#read 6, iclass 32, count 0 2006.285.12:28:38.87#ibcon#end of sib2, iclass 32, count 0 2006.285.12:28:38.87#ibcon#*mode == 0, iclass 32, count 0 2006.285.12:28:38.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.12:28:38.87#ibcon#[25=USB\r\n] 2006.285.12:28:38.87#ibcon#*before write, iclass 32, count 0 2006.285.12:28:38.87#ibcon#enter sib2, iclass 32, count 0 2006.285.12:28:38.87#ibcon#flushed, iclass 32, count 0 2006.285.12:28:38.87#ibcon#about to write, iclass 32, count 0 2006.285.12:28:38.87#ibcon#wrote, iclass 32, count 0 2006.285.12:28:38.87#ibcon#about to read 3, iclass 32, count 0 2006.285.12:28:38.90#ibcon#read 3, iclass 32, count 0 2006.285.12:28:38.90#ibcon#about to read 4, iclass 32, count 0 2006.285.12:28:38.90#ibcon#read 4, iclass 32, count 0 2006.285.12:28:38.90#ibcon#about to read 5, iclass 32, count 0 2006.285.12:28:38.90#ibcon#read 5, iclass 32, count 0 2006.285.12:28:38.90#ibcon#about to read 6, iclass 32, count 0 2006.285.12:28:38.90#ibcon#read 6, iclass 32, count 0 2006.285.12:28:38.90#ibcon#end of sib2, iclass 32, count 0 2006.285.12:28:38.90#ibcon#*after write, iclass 32, count 0 2006.285.12:28:38.90#ibcon#*before return 0, iclass 32, count 0 2006.285.12:28:38.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:28:38.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:28:38.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.12:28:38.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.12:28:38.90$vck44/valo=2,534.99 2006.285.12:28:38.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.12:28:38.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.12:28:38.90#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:38.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:28:38.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:28:38.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:28:38.90#ibcon#enter wrdev, iclass 34, count 0 2006.285.12:28:38.90#ibcon#first serial, iclass 34, count 0 2006.285.12:28:38.90#ibcon#enter sib2, iclass 34, count 0 2006.285.12:28:38.90#ibcon#flushed, iclass 34, count 0 2006.285.12:28:38.90#ibcon#about to write, iclass 34, count 0 2006.285.12:28:38.90#ibcon#wrote, iclass 34, count 0 2006.285.12:28:38.90#ibcon#about to read 3, iclass 34, count 0 2006.285.12:28:38.92#ibcon#read 3, iclass 34, count 0 2006.285.12:28:38.92#ibcon#about to read 4, iclass 34, count 0 2006.285.12:28:38.92#ibcon#read 4, iclass 34, count 0 2006.285.12:28:38.92#ibcon#about to read 5, iclass 34, count 0 2006.285.12:28:38.92#ibcon#read 5, iclass 34, count 0 2006.285.12:28:38.92#ibcon#about to read 6, iclass 34, count 0 2006.285.12:28:38.92#ibcon#read 6, iclass 34, count 0 2006.285.12:28:38.92#ibcon#end of sib2, iclass 34, count 0 2006.285.12:28:38.92#ibcon#*mode == 0, iclass 34, count 0 2006.285.12:28:38.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.12:28:38.92#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.12:28:38.92#ibcon#*before write, iclass 34, count 0 2006.285.12:28:38.92#ibcon#enter sib2, iclass 34, count 0 2006.285.12:28:38.92#ibcon#flushed, iclass 34, count 0 2006.285.12:28:38.92#ibcon#about to write, iclass 34, count 0 2006.285.12:28:38.92#ibcon#wrote, iclass 34, count 0 2006.285.12:28:38.92#ibcon#about to read 3, iclass 34, count 0 2006.285.12:28:38.96#ibcon#read 3, iclass 34, count 0 2006.285.12:28:38.96#ibcon#about to read 4, iclass 34, count 0 2006.285.12:28:38.96#ibcon#read 4, iclass 34, count 0 2006.285.12:28:38.96#ibcon#about to read 5, iclass 34, count 0 2006.285.12:28:38.96#ibcon#read 5, iclass 34, count 0 2006.285.12:28:38.96#ibcon#about to read 6, iclass 34, count 0 2006.285.12:28:38.96#ibcon#read 6, iclass 34, count 0 2006.285.12:28:38.96#ibcon#end of sib2, iclass 34, count 0 2006.285.12:28:38.96#ibcon#*after write, iclass 34, count 0 2006.285.12:28:38.96#ibcon#*before return 0, iclass 34, count 0 2006.285.12:28:38.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:28:38.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:28:38.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.12:28:38.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.12:28:38.96$vck44/va=2,6 2006.285.12:28:38.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.12:28:38.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.12:28:38.96#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:38.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:28:39.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:28:39.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:28:39.02#ibcon#enter wrdev, iclass 36, count 2 2006.285.12:28:39.02#ibcon#first serial, iclass 36, count 2 2006.285.12:28:39.02#ibcon#enter sib2, iclass 36, count 2 2006.285.12:28:39.02#ibcon#flushed, iclass 36, count 2 2006.285.12:28:39.02#ibcon#about to write, iclass 36, count 2 2006.285.12:28:39.02#ibcon#wrote, iclass 36, count 2 2006.285.12:28:39.02#ibcon#about to read 3, iclass 36, count 2 2006.285.12:28:39.04#ibcon#read 3, iclass 36, count 2 2006.285.12:28:39.04#ibcon#about to read 4, iclass 36, count 2 2006.285.12:28:39.04#ibcon#read 4, iclass 36, count 2 2006.285.12:28:39.04#ibcon#about to read 5, iclass 36, count 2 2006.285.12:28:39.04#ibcon#read 5, iclass 36, count 2 2006.285.12:28:39.04#ibcon#about to read 6, iclass 36, count 2 2006.285.12:28:39.04#ibcon#read 6, iclass 36, count 2 2006.285.12:28:39.04#ibcon#end of sib2, iclass 36, count 2 2006.285.12:28:39.04#ibcon#*mode == 0, iclass 36, count 2 2006.285.12:28:39.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.12:28:39.04#ibcon#[25=AT02-06\r\n] 2006.285.12:28:39.04#ibcon#*before write, iclass 36, count 2 2006.285.12:28:39.04#ibcon#enter sib2, iclass 36, count 2 2006.285.12:28:39.04#ibcon#flushed, iclass 36, count 2 2006.285.12:28:39.04#ibcon#about to write, iclass 36, count 2 2006.285.12:28:39.04#ibcon#wrote, iclass 36, count 2 2006.285.12:28:39.04#ibcon#about to read 3, iclass 36, count 2 2006.285.12:28:39.07#ibcon#read 3, iclass 36, count 2 2006.285.12:28:39.07#ibcon#about to read 4, iclass 36, count 2 2006.285.12:28:39.07#ibcon#read 4, iclass 36, count 2 2006.285.12:28:39.07#ibcon#about to read 5, iclass 36, count 2 2006.285.12:28:39.07#ibcon#read 5, iclass 36, count 2 2006.285.12:28:39.07#ibcon#about to read 6, iclass 36, count 2 2006.285.12:28:39.07#ibcon#read 6, iclass 36, count 2 2006.285.12:28:39.07#ibcon#end of sib2, iclass 36, count 2 2006.285.12:28:39.07#ibcon#*after write, iclass 36, count 2 2006.285.12:28:39.07#ibcon#*before return 0, iclass 36, count 2 2006.285.12:28:39.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:28:39.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:28:39.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.12:28:39.07#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:39.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:28:39.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:28:39.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:28:39.19#ibcon#enter wrdev, iclass 36, count 0 2006.285.12:28:39.19#ibcon#first serial, iclass 36, count 0 2006.285.12:28:39.19#ibcon#enter sib2, iclass 36, count 0 2006.285.12:28:39.19#ibcon#flushed, iclass 36, count 0 2006.285.12:28:39.19#ibcon#about to write, iclass 36, count 0 2006.285.12:28:39.19#ibcon#wrote, iclass 36, count 0 2006.285.12:28:39.19#ibcon#about to read 3, iclass 36, count 0 2006.285.12:28:39.21#ibcon#read 3, iclass 36, count 0 2006.285.12:28:39.21#ibcon#about to read 4, iclass 36, count 0 2006.285.12:28:39.21#ibcon#read 4, iclass 36, count 0 2006.285.12:28:39.21#ibcon#about to read 5, iclass 36, count 0 2006.285.12:28:39.21#ibcon#read 5, iclass 36, count 0 2006.285.12:28:39.21#ibcon#about to read 6, iclass 36, count 0 2006.285.12:28:39.21#ibcon#read 6, iclass 36, count 0 2006.285.12:28:39.21#ibcon#end of sib2, iclass 36, count 0 2006.285.12:28:39.21#ibcon#*mode == 0, iclass 36, count 0 2006.285.12:28:39.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.12:28:39.21#ibcon#[25=USB\r\n] 2006.285.12:28:39.21#ibcon#*before write, iclass 36, count 0 2006.285.12:28:39.21#ibcon#enter sib2, iclass 36, count 0 2006.285.12:28:39.21#ibcon#flushed, iclass 36, count 0 2006.285.12:28:39.21#ibcon#about to write, iclass 36, count 0 2006.285.12:28:39.21#ibcon#wrote, iclass 36, count 0 2006.285.12:28:39.21#ibcon#about to read 3, iclass 36, count 0 2006.285.12:28:39.24#ibcon#read 3, iclass 36, count 0 2006.285.12:28:39.24#ibcon#about to read 4, iclass 36, count 0 2006.285.12:28:39.24#ibcon#read 4, iclass 36, count 0 2006.285.12:28:39.24#ibcon#about to read 5, iclass 36, count 0 2006.285.12:28:39.24#ibcon#read 5, iclass 36, count 0 2006.285.12:28:39.24#ibcon#about to read 6, iclass 36, count 0 2006.285.12:28:39.24#ibcon#read 6, iclass 36, count 0 2006.285.12:28:39.24#ibcon#end of sib2, iclass 36, count 0 2006.285.12:28:39.24#ibcon#*after write, iclass 36, count 0 2006.285.12:28:39.24#ibcon#*before return 0, iclass 36, count 0 2006.285.12:28:39.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:28:39.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:28:39.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.12:28:39.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.12:28:39.24$vck44/valo=3,564.99 2006.285.12:28:39.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.12:28:39.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.12:28:39.24#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:39.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:28:39.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:28:39.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:28:39.24#ibcon#enter wrdev, iclass 38, count 0 2006.285.12:28:39.24#ibcon#first serial, iclass 38, count 0 2006.285.12:28:39.24#ibcon#enter sib2, iclass 38, count 0 2006.285.12:28:39.24#ibcon#flushed, iclass 38, count 0 2006.285.12:28:39.24#ibcon#about to write, iclass 38, count 0 2006.285.12:28:39.24#ibcon#wrote, iclass 38, count 0 2006.285.12:28:39.24#ibcon#about to read 3, iclass 38, count 0 2006.285.12:28:39.26#ibcon#read 3, iclass 38, count 0 2006.285.12:28:39.26#ibcon#about to read 4, iclass 38, count 0 2006.285.12:28:39.26#ibcon#read 4, iclass 38, count 0 2006.285.12:28:39.26#ibcon#about to read 5, iclass 38, count 0 2006.285.12:28:39.26#ibcon#read 5, iclass 38, count 0 2006.285.12:28:39.26#ibcon#about to read 6, iclass 38, count 0 2006.285.12:28:39.26#ibcon#read 6, iclass 38, count 0 2006.285.12:28:39.26#ibcon#end of sib2, iclass 38, count 0 2006.285.12:28:39.26#ibcon#*mode == 0, iclass 38, count 0 2006.285.12:28:39.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.12:28:39.26#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.12:28:39.26#ibcon#*before write, iclass 38, count 0 2006.285.12:28:39.26#ibcon#enter sib2, iclass 38, count 0 2006.285.12:28:39.26#ibcon#flushed, iclass 38, count 0 2006.285.12:28:39.26#ibcon#about to write, iclass 38, count 0 2006.285.12:28:39.26#ibcon#wrote, iclass 38, count 0 2006.285.12:28:39.26#ibcon#about to read 3, iclass 38, count 0 2006.285.12:28:39.30#ibcon#read 3, iclass 38, count 0 2006.285.12:28:39.30#ibcon#about to read 4, iclass 38, count 0 2006.285.12:28:39.30#ibcon#read 4, iclass 38, count 0 2006.285.12:28:39.30#ibcon#about to read 5, iclass 38, count 0 2006.285.12:28:39.30#ibcon#read 5, iclass 38, count 0 2006.285.12:28:39.30#ibcon#about to read 6, iclass 38, count 0 2006.285.12:28:39.30#ibcon#read 6, iclass 38, count 0 2006.285.12:28:39.30#ibcon#end of sib2, iclass 38, count 0 2006.285.12:28:39.30#ibcon#*after write, iclass 38, count 0 2006.285.12:28:39.30#ibcon#*before return 0, iclass 38, count 0 2006.285.12:28:39.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:28:39.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:28:39.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.12:28:39.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.12:28:39.30$vck44/va=3,7 2006.285.12:28:39.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.12:28:39.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.12:28:39.30#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:39.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:28:39.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:28:39.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:28:39.36#ibcon#enter wrdev, iclass 40, count 2 2006.285.12:28:39.36#ibcon#first serial, iclass 40, count 2 2006.285.12:28:39.36#ibcon#enter sib2, iclass 40, count 2 2006.285.12:28:39.36#ibcon#flushed, iclass 40, count 2 2006.285.12:28:39.36#ibcon#about to write, iclass 40, count 2 2006.285.12:28:39.36#ibcon#wrote, iclass 40, count 2 2006.285.12:28:39.36#ibcon#about to read 3, iclass 40, count 2 2006.285.12:28:39.38#ibcon#read 3, iclass 40, count 2 2006.285.12:28:39.38#ibcon#about to read 4, iclass 40, count 2 2006.285.12:28:39.38#ibcon#read 4, iclass 40, count 2 2006.285.12:28:39.38#ibcon#about to read 5, iclass 40, count 2 2006.285.12:28:39.38#ibcon#read 5, iclass 40, count 2 2006.285.12:28:39.38#ibcon#about to read 6, iclass 40, count 2 2006.285.12:28:39.38#ibcon#read 6, iclass 40, count 2 2006.285.12:28:39.38#ibcon#end of sib2, iclass 40, count 2 2006.285.12:28:39.38#ibcon#*mode == 0, iclass 40, count 2 2006.285.12:28:39.38#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.12:28:39.38#ibcon#[25=AT03-07\r\n] 2006.285.12:28:39.38#ibcon#*before write, iclass 40, count 2 2006.285.12:28:39.38#ibcon#enter sib2, iclass 40, count 2 2006.285.12:28:39.38#ibcon#flushed, iclass 40, count 2 2006.285.12:28:39.38#ibcon#about to write, iclass 40, count 2 2006.285.12:28:39.38#ibcon#wrote, iclass 40, count 2 2006.285.12:28:39.38#ibcon#about to read 3, iclass 40, count 2 2006.285.12:28:39.41#ibcon#read 3, iclass 40, count 2 2006.285.12:28:39.41#ibcon#about to read 4, iclass 40, count 2 2006.285.12:28:39.41#ibcon#read 4, iclass 40, count 2 2006.285.12:28:39.41#ibcon#about to read 5, iclass 40, count 2 2006.285.12:28:39.41#ibcon#read 5, iclass 40, count 2 2006.285.12:28:39.41#ibcon#about to read 6, iclass 40, count 2 2006.285.12:28:39.41#ibcon#read 6, iclass 40, count 2 2006.285.12:28:39.41#ibcon#end of sib2, iclass 40, count 2 2006.285.12:28:39.41#ibcon#*after write, iclass 40, count 2 2006.285.12:28:39.41#ibcon#*before return 0, iclass 40, count 2 2006.285.12:28:39.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:28:39.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:28:39.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.12:28:39.41#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:39.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:28:39.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:28:39.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:28:39.53#ibcon#enter wrdev, iclass 40, count 0 2006.285.12:28:39.53#ibcon#first serial, iclass 40, count 0 2006.285.12:28:39.53#ibcon#enter sib2, iclass 40, count 0 2006.285.12:28:39.53#ibcon#flushed, iclass 40, count 0 2006.285.12:28:39.53#ibcon#about to write, iclass 40, count 0 2006.285.12:28:39.53#ibcon#wrote, iclass 40, count 0 2006.285.12:28:39.53#ibcon#about to read 3, iclass 40, count 0 2006.285.12:28:39.55#ibcon#read 3, iclass 40, count 0 2006.285.12:28:39.55#ibcon#about to read 4, iclass 40, count 0 2006.285.12:28:39.55#ibcon#read 4, iclass 40, count 0 2006.285.12:28:39.55#ibcon#about to read 5, iclass 40, count 0 2006.285.12:28:39.55#ibcon#read 5, iclass 40, count 0 2006.285.12:28:39.55#ibcon#about to read 6, iclass 40, count 0 2006.285.12:28:39.55#ibcon#read 6, iclass 40, count 0 2006.285.12:28:39.55#ibcon#end of sib2, iclass 40, count 0 2006.285.12:28:39.55#ibcon#*mode == 0, iclass 40, count 0 2006.285.12:28:39.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.12:28:39.55#ibcon#[25=USB\r\n] 2006.285.12:28:39.55#ibcon#*before write, iclass 40, count 0 2006.285.12:28:39.55#ibcon#enter sib2, iclass 40, count 0 2006.285.12:28:39.55#ibcon#flushed, iclass 40, count 0 2006.285.12:28:39.55#ibcon#about to write, iclass 40, count 0 2006.285.12:28:39.55#ibcon#wrote, iclass 40, count 0 2006.285.12:28:39.55#ibcon#about to read 3, iclass 40, count 0 2006.285.12:28:39.58#ibcon#read 3, iclass 40, count 0 2006.285.12:28:39.58#ibcon#about to read 4, iclass 40, count 0 2006.285.12:28:39.58#ibcon#read 4, iclass 40, count 0 2006.285.12:28:39.58#ibcon#about to read 5, iclass 40, count 0 2006.285.12:28:39.58#ibcon#read 5, iclass 40, count 0 2006.285.12:28:39.58#ibcon#about to read 6, iclass 40, count 0 2006.285.12:28:39.58#ibcon#read 6, iclass 40, count 0 2006.285.12:28:39.58#ibcon#end of sib2, iclass 40, count 0 2006.285.12:28:39.58#ibcon#*after write, iclass 40, count 0 2006.285.12:28:39.58#ibcon#*before return 0, iclass 40, count 0 2006.285.12:28:39.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:28:39.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:28:39.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.12:28:39.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.12:28:39.58$vck44/valo=4,624.99 2006.285.12:28:39.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.12:28:39.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.12:28:39.58#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:39.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:28:39.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:28:39.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:28:39.58#ibcon#enter wrdev, iclass 4, count 0 2006.285.12:28:39.58#ibcon#first serial, iclass 4, count 0 2006.285.12:28:39.58#ibcon#enter sib2, iclass 4, count 0 2006.285.12:28:39.58#ibcon#flushed, iclass 4, count 0 2006.285.12:28:39.58#ibcon#about to write, iclass 4, count 0 2006.285.12:28:39.58#ibcon#wrote, iclass 4, count 0 2006.285.12:28:39.58#ibcon#about to read 3, iclass 4, count 0 2006.285.12:28:39.60#ibcon#read 3, iclass 4, count 0 2006.285.12:28:39.60#ibcon#about to read 4, iclass 4, count 0 2006.285.12:28:39.60#ibcon#read 4, iclass 4, count 0 2006.285.12:28:39.60#ibcon#about to read 5, iclass 4, count 0 2006.285.12:28:39.60#ibcon#read 5, iclass 4, count 0 2006.285.12:28:39.60#ibcon#about to read 6, iclass 4, count 0 2006.285.12:28:39.60#ibcon#read 6, iclass 4, count 0 2006.285.12:28:39.60#ibcon#end of sib2, iclass 4, count 0 2006.285.12:28:39.60#ibcon#*mode == 0, iclass 4, count 0 2006.285.12:28:39.60#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.12:28:39.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.12:28:39.60#ibcon#*before write, iclass 4, count 0 2006.285.12:28:39.60#ibcon#enter sib2, iclass 4, count 0 2006.285.12:28:39.60#ibcon#flushed, iclass 4, count 0 2006.285.12:28:39.60#ibcon#about to write, iclass 4, count 0 2006.285.12:28:39.60#ibcon#wrote, iclass 4, count 0 2006.285.12:28:39.60#ibcon#about to read 3, iclass 4, count 0 2006.285.12:28:39.64#ibcon#read 3, iclass 4, count 0 2006.285.12:28:39.64#ibcon#about to read 4, iclass 4, count 0 2006.285.12:28:39.64#ibcon#read 4, iclass 4, count 0 2006.285.12:28:39.64#ibcon#about to read 5, iclass 4, count 0 2006.285.12:28:39.64#ibcon#read 5, iclass 4, count 0 2006.285.12:28:39.64#ibcon#about to read 6, iclass 4, count 0 2006.285.12:28:39.64#ibcon#read 6, iclass 4, count 0 2006.285.12:28:39.64#ibcon#end of sib2, iclass 4, count 0 2006.285.12:28:39.64#ibcon#*after write, iclass 4, count 0 2006.285.12:28:39.64#ibcon#*before return 0, iclass 4, count 0 2006.285.12:28:39.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:28:39.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:28:39.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.12:28:39.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.12:28:39.64$vck44/va=4,6 2006.285.12:28:39.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.12:28:39.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.12:28:39.64#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:39.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:28:39.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:28:39.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:28:39.70#ibcon#enter wrdev, iclass 6, count 2 2006.285.12:28:39.70#ibcon#first serial, iclass 6, count 2 2006.285.12:28:39.70#ibcon#enter sib2, iclass 6, count 2 2006.285.12:28:39.70#ibcon#flushed, iclass 6, count 2 2006.285.12:28:39.70#ibcon#about to write, iclass 6, count 2 2006.285.12:28:39.70#ibcon#wrote, iclass 6, count 2 2006.285.12:28:39.70#ibcon#about to read 3, iclass 6, count 2 2006.285.12:28:39.72#ibcon#read 3, iclass 6, count 2 2006.285.12:28:39.72#ibcon#about to read 4, iclass 6, count 2 2006.285.12:28:39.72#ibcon#read 4, iclass 6, count 2 2006.285.12:28:39.72#ibcon#about to read 5, iclass 6, count 2 2006.285.12:28:39.72#ibcon#read 5, iclass 6, count 2 2006.285.12:28:39.72#ibcon#about to read 6, iclass 6, count 2 2006.285.12:28:39.72#ibcon#read 6, iclass 6, count 2 2006.285.12:28:39.72#ibcon#end of sib2, iclass 6, count 2 2006.285.12:28:39.72#ibcon#*mode == 0, iclass 6, count 2 2006.285.12:28:39.72#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.12:28:39.72#ibcon#[25=AT04-06\r\n] 2006.285.12:28:39.72#ibcon#*before write, iclass 6, count 2 2006.285.12:28:39.72#ibcon#enter sib2, iclass 6, count 2 2006.285.12:28:39.72#ibcon#flushed, iclass 6, count 2 2006.285.12:28:39.72#ibcon#about to write, iclass 6, count 2 2006.285.12:28:39.72#ibcon#wrote, iclass 6, count 2 2006.285.12:28:39.72#ibcon#about to read 3, iclass 6, count 2 2006.285.12:28:39.75#ibcon#read 3, iclass 6, count 2 2006.285.12:28:39.75#ibcon#about to read 4, iclass 6, count 2 2006.285.12:28:39.75#ibcon#read 4, iclass 6, count 2 2006.285.12:28:39.75#ibcon#about to read 5, iclass 6, count 2 2006.285.12:28:39.75#ibcon#read 5, iclass 6, count 2 2006.285.12:28:39.75#ibcon#about to read 6, iclass 6, count 2 2006.285.12:28:39.75#ibcon#read 6, iclass 6, count 2 2006.285.12:28:39.75#ibcon#end of sib2, iclass 6, count 2 2006.285.12:28:39.75#ibcon#*after write, iclass 6, count 2 2006.285.12:28:39.75#ibcon#*before return 0, iclass 6, count 2 2006.285.12:28:39.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:28:39.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:28:39.75#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.12:28:39.75#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:39.75#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:28:39.87#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:28:39.87#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:28:39.87#ibcon#enter wrdev, iclass 6, count 0 2006.285.12:28:39.87#ibcon#first serial, iclass 6, count 0 2006.285.12:28:39.87#ibcon#enter sib2, iclass 6, count 0 2006.285.12:28:39.87#ibcon#flushed, iclass 6, count 0 2006.285.12:28:39.87#ibcon#about to write, iclass 6, count 0 2006.285.12:28:39.87#ibcon#wrote, iclass 6, count 0 2006.285.12:28:39.87#ibcon#about to read 3, iclass 6, count 0 2006.285.12:28:39.89#ibcon#read 3, iclass 6, count 0 2006.285.12:28:39.89#ibcon#about to read 4, iclass 6, count 0 2006.285.12:28:39.89#ibcon#read 4, iclass 6, count 0 2006.285.12:28:39.89#ibcon#about to read 5, iclass 6, count 0 2006.285.12:28:39.89#ibcon#read 5, iclass 6, count 0 2006.285.12:28:39.89#ibcon#about to read 6, iclass 6, count 0 2006.285.12:28:39.89#ibcon#read 6, iclass 6, count 0 2006.285.12:28:39.89#ibcon#end of sib2, iclass 6, count 0 2006.285.12:28:39.89#ibcon#*mode == 0, iclass 6, count 0 2006.285.12:28:39.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.12:28:39.89#ibcon#[25=USB\r\n] 2006.285.12:28:39.89#ibcon#*before write, iclass 6, count 0 2006.285.12:28:39.89#ibcon#enter sib2, iclass 6, count 0 2006.285.12:28:39.89#ibcon#flushed, iclass 6, count 0 2006.285.12:28:39.89#ibcon#about to write, iclass 6, count 0 2006.285.12:28:39.89#ibcon#wrote, iclass 6, count 0 2006.285.12:28:39.89#ibcon#about to read 3, iclass 6, count 0 2006.285.12:28:39.92#ibcon#read 3, iclass 6, count 0 2006.285.12:28:39.92#ibcon#about to read 4, iclass 6, count 0 2006.285.12:28:39.92#ibcon#read 4, iclass 6, count 0 2006.285.12:28:39.92#ibcon#about to read 5, iclass 6, count 0 2006.285.12:28:39.92#ibcon#read 5, iclass 6, count 0 2006.285.12:28:39.92#ibcon#about to read 6, iclass 6, count 0 2006.285.12:28:39.92#ibcon#read 6, iclass 6, count 0 2006.285.12:28:39.92#ibcon#end of sib2, iclass 6, count 0 2006.285.12:28:39.92#ibcon#*after write, iclass 6, count 0 2006.285.12:28:39.92#ibcon#*before return 0, iclass 6, count 0 2006.285.12:28:39.92#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:28:39.92#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:28:39.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.12:28:39.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.12:28:39.92$vck44/valo=5,734.99 2006.285.12:28:39.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.12:28:39.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.12:28:39.92#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:39.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:28:39.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:28:39.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:28:39.92#ibcon#enter wrdev, iclass 10, count 0 2006.285.12:28:39.92#ibcon#first serial, iclass 10, count 0 2006.285.12:28:39.92#ibcon#enter sib2, iclass 10, count 0 2006.285.12:28:39.92#ibcon#flushed, iclass 10, count 0 2006.285.12:28:39.92#ibcon#about to write, iclass 10, count 0 2006.285.12:28:39.92#ibcon#wrote, iclass 10, count 0 2006.285.12:28:39.92#ibcon#about to read 3, iclass 10, count 0 2006.285.12:28:39.94#ibcon#read 3, iclass 10, count 0 2006.285.12:28:39.94#ibcon#about to read 4, iclass 10, count 0 2006.285.12:28:39.94#ibcon#read 4, iclass 10, count 0 2006.285.12:28:39.94#ibcon#about to read 5, iclass 10, count 0 2006.285.12:28:39.94#ibcon#read 5, iclass 10, count 0 2006.285.12:28:39.94#ibcon#about to read 6, iclass 10, count 0 2006.285.12:28:39.94#ibcon#read 6, iclass 10, count 0 2006.285.12:28:39.94#ibcon#end of sib2, iclass 10, count 0 2006.285.12:28:39.94#ibcon#*mode == 0, iclass 10, count 0 2006.285.12:28:39.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.12:28:39.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.12:28:39.94#ibcon#*before write, iclass 10, count 0 2006.285.12:28:39.94#ibcon#enter sib2, iclass 10, count 0 2006.285.12:28:39.94#ibcon#flushed, iclass 10, count 0 2006.285.12:28:39.94#ibcon#about to write, iclass 10, count 0 2006.285.12:28:39.94#ibcon#wrote, iclass 10, count 0 2006.285.12:28:39.94#ibcon#about to read 3, iclass 10, count 0 2006.285.12:28:39.98#ibcon#read 3, iclass 10, count 0 2006.285.12:28:39.98#ibcon#about to read 4, iclass 10, count 0 2006.285.12:28:39.98#ibcon#read 4, iclass 10, count 0 2006.285.12:28:39.98#ibcon#about to read 5, iclass 10, count 0 2006.285.12:28:39.98#ibcon#read 5, iclass 10, count 0 2006.285.12:28:39.98#ibcon#about to read 6, iclass 10, count 0 2006.285.12:28:39.98#ibcon#read 6, iclass 10, count 0 2006.285.12:28:39.98#ibcon#end of sib2, iclass 10, count 0 2006.285.12:28:39.98#ibcon#*after write, iclass 10, count 0 2006.285.12:28:39.98#ibcon#*before return 0, iclass 10, count 0 2006.285.12:28:39.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:28:39.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:28:39.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.12:28:39.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.12:28:39.98$vck44/va=5,3 2006.285.12:28:39.98#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.12:28:39.98#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.12:28:39.98#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:39.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:28:40.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:28:40.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:28:40.04#ibcon#enter wrdev, iclass 12, count 2 2006.285.12:28:40.04#ibcon#first serial, iclass 12, count 2 2006.285.12:28:40.04#ibcon#enter sib2, iclass 12, count 2 2006.285.12:28:40.04#ibcon#flushed, iclass 12, count 2 2006.285.12:28:40.04#ibcon#about to write, iclass 12, count 2 2006.285.12:28:40.04#ibcon#wrote, iclass 12, count 2 2006.285.12:28:40.04#ibcon#about to read 3, iclass 12, count 2 2006.285.12:28:40.06#ibcon#read 3, iclass 12, count 2 2006.285.12:28:40.06#ibcon#about to read 4, iclass 12, count 2 2006.285.12:28:40.06#ibcon#read 4, iclass 12, count 2 2006.285.12:28:40.06#ibcon#about to read 5, iclass 12, count 2 2006.285.12:28:40.06#ibcon#read 5, iclass 12, count 2 2006.285.12:28:40.06#ibcon#about to read 6, iclass 12, count 2 2006.285.12:28:40.06#ibcon#read 6, iclass 12, count 2 2006.285.12:28:40.06#ibcon#end of sib2, iclass 12, count 2 2006.285.12:28:40.06#ibcon#*mode == 0, iclass 12, count 2 2006.285.12:28:40.06#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.12:28:40.06#ibcon#[25=AT05-03\r\n] 2006.285.12:28:40.06#ibcon#*before write, iclass 12, count 2 2006.285.12:28:40.06#ibcon#enter sib2, iclass 12, count 2 2006.285.12:28:40.06#ibcon#flushed, iclass 12, count 2 2006.285.12:28:40.06#ibcon#about to write, iclass 12, count 2 2006.285.12:28:40.06#ibcon#wrote, iclass 12, count 2 2006.285.12:28:40.06#ibcon#about to read 3, iclass 12, count 2 2006.285.12:28:40.09#ibcon#read 3, iclass 12, count 2 2006.285.12:28:40.09#ibcon#about to read 4, iclass 12, count 2 2006.285.12:28:40.09#ibcon#read 4, iclass 12, count 2 2006.285.12:28:40.09#ibcon#about to read 5, iclass 12, count 2 2006.285.12:28:40.09#ibcon#read 5, iclass 12, count 2 2006.285.12:28:40.09#ibcon#about to read 6, iclass 12, count 2 2006.285.12:28:40.09#ibcon#read 6, iclass 12, count 2 2006.285.12:28:40.09#ibcon#end of sib2, iclass 12, count 2 2006.285.12:28:40.09#ibcon#*after write, iclass 12, count 2 2006.285.12:28:40.09#ibcon#*before return 0, iclass 12, count 2 2006.285.12:28:40.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:28:40.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:28:40.09#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.12:28:40.09#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:40.09#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:28:40.21#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:28:40.21#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:28:40.21#ibcon#enter wrdev, iclass 12, count 0 2006.285.12:28:40.21#ibcon#first serial, iclass 12, count 0 2006.285.12:28:40.21#ibcon#enter sib2, iclass 12, count 0 2006.285.12:28:40.21#ibcon#flushed, iclass 12, count 0 2006.285.12:28:40.21#ibcon#about to write, iclass 12, count 0 2006.285.12:28:40.21#ibcon#wrote, iclass 12, count 0 2006.285.12:28:40.21#ibcon#about to read 3, iclass 12, count 0 2006.285.12:28:40.23#ibcon#read 3, iclass 12, count 0 2006.285.12:28:40.23#ibcon#about to read 4, iclass 12, count 0 2006.285.12:28:40.23#ibcon#read 4, iclass 12, count 0 2006.285.12:28:40.23#ibcon#about to read 5, iclass 12, count 0 2006.285.12:28:40.23#ibcon#read 5, iclass 12, count 0 2006.285.12:28:40.23#ibcon#about to read 6, iclass 12, count 0 2006.285.12:28:40.23#ibcon#read 6, iclass 12, count 0 2006.285.12:28:40.23#ibcon#end of sib2, iclass 12, count 0 2006.285.12:28:40.23#ibcon#*mode == 0, iclass 12, count 0 2006.285.12:28:40.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.12:28:40.23#ibcon#[25=USB\r\n] 2006.285.12:28:40.23#ibcon#*before write, iclass 12, count 0 2006.285.12:28:40.23#ibcon#enter sib2, iclass 12, count 0 2006.285.12:28:40.23#ibcon#flushed, iclass 12, count 0 2006.285.12:28:40.23#ibcon#about to write, iclass 12, count 0 2006.285.12:28:40.23#ibcon#wrote, iclass 12, count 0 2006.285.12:28:40.23#ibcon#about to read 3, iclass 12, count 0 2006.285.12:28:40.26#ibcon#read 3, iclass 12, count 0 2006.285.12:28:40.26#ibcon#about to read 4, iclass 12, count 0 2006.285.12:28:40.26#ibcon#read 4, iclass 12, count 0 2006.285.12:28:40.26#ibcon#about to read 5, iclass 12, count 0 2006.285.12:28:40.26#ibcon#read 5, iclass 12, count 0 2006.285.12:28:40.26#ibcon#about to read 6, iclass 12, count 0 2006.285.12:28:40.26#ibcon#read 6, iclass 12, count 0 2006.285.12:28:40.26#ibcon#end of sib2, iclass 12, count 0 2006.285.12:28:40.26#ibcon#*after write, iclass 12, count 0 2006.285.12:28:40.26#ibcon#*before return 0, iclass 12, count 0 2006.285.12:28:40.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:28:40.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:28:40.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.12:28:40.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.12:28:40.26$vck44/valo=6,814.99 2006.285.12:28:40.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.12:28:40.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.12:28:40.26#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:40.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:28:40.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:28:40.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:28:40.26#ibcon#enter wrdev, iclass 14, count 0 2006.285.12:28:40.26#ibcon#first serial, iclass 14, count 0 2006.285.12:28:40.26#ibcon#enter sib2, iclass 14, count 0 2006.285.12:28:40.26#ibcon#flushed, iclass 14, count 0 2006.285.12:28:40.26#ibcon#about to write, iclass 14, count 0 2006.285.12:28:40.26#ibcon#wrote, iclass 14, count 0 2006.285.12:28:40.26#ibcon#about to read 3, iclass 14, count 0 2006.285.12:28:40.28#ibcon#read 3, iclass 14, count 0 2006.285.12:28:40.28#ibcon#about to read 4, iclass 14, count 0 2006.285.12:28:40.28#ibcon#read 4, iclass 14, count 0 2006.285.12:28:40.28#ibcon#about to read 5, iclass 14, count 0 2006.285.12:28:40.28#ibcon#read 5, iclass 14, count 0 2006.285.12:28:40.28#ibcon#about to read 6, iclass 14, count 0 2006.285.12:28:40.28#ibcon#read 6, iclass 14, count 0 2006.285.12:28:40.28#ibcon#end of sib2, iclass 14, count 0 2006.285.12:28:40.28#ibcon#*mode == 0, iclass 14, count 0 2006.285.12:28:40.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.12:28:40.28#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.12:28:40.28#ibcon#*before write, iclass 14, count 0 2006.285.12:28:40.28#ibcon#enter sib2, iclass 14, count 0 2006.285.12:28:40.28#ibcon#flushed, iclass 14, count 0 2006.285.12:28:40.28#ibcon#about to write, iclass 14, count 0 2006.285.12:28:40.28#ibcon#wrote, iclass 14, count 0 2006.285.12:28:40.28#ibcon#about to read 3, iclass 14, count 0 2006.285.12:28:40.32#ibcon#read 3, iclass 14, count 0 2006.285.12:28:40.32#ibcon#about to read 4, iclass 14, count 0 2006.285.12:28:40.32#ibcon#read 4, iclass 14, count 0 2006.285.12:28:40.32#ibcon#about to read 5, iclass 14, count 0 2006.285.12:28:40.32#ibcon#read 5, iclass 14, count 0 2006.285.12:28:40.32#ibcon#about to read 6, iclass 14, count 0 2006.285.12:28:40.32#ibcon#read 6, iclass 14, count 0 2006.285.12:28:40.32#ibcon#end of sib2, iclass 14, count 0 2006.285.12:28:40.32#ibcon#*after write, iclass 14, count 0 2006.285.12:28:40.32#ibcon#*before return 0, iclass 14, count 0 2006.285.12:28:40.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:28:40.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:28:40.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.12:28:40.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.12:28:40.32$vck44/va=6,4 2006.285.12:28:40.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.12:28:40.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.12:28:40.32#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:40.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:28:40.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:28:40.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:28:40.38#ibcon#enter wrdev, iclass 16, count 2 2006.285.12:28:40.38#ibcon#first serial, iclass 16, count 2 2006.285.12:28:40.38#ibcon#enter sib2, iclass 16, count 2 2006.285.12:28:40.38#ibcon#flushed, iclass 16, count 2 2006.285.12:28:40.38#ibcon#about to write, iclass 16, count 2 2006.285.12:28:40.38#ibcon#wrote, iclass 16, count 2 2006.285.12:28:40.38#ibcon#about to read 3, iclass 16, count 2 2006.285.12:28:40.40#ibcon#read 3, iclass 16, count 2 2006.285.12:28:40.40#ibcon#about to read 4, iclass 16, count 2 2006.285.12:28:40.40#ibcon#read 4, iclass 16, count 2 2006.285.12:28:40.40#ibcon#about to read 5, iclass 16, count 2 2006.285.12:28:40.40#ibcon#read 5, iclass 16, count 2 2006.285.12:28:40.40#ibcon#about to read 6, iclass 16, count 2 2006.285.12:28:40.40#ibcon#read 6, iclass 16, count 2 2006.285.12:28:40.40#ibcon#end of sib2, iclass 16, count 2 2006.285.12:28:40.40#ibcon#*mode == 0, iclass 16, count 2 2006.285.12:28:40.40#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.12:28:40.40#ibcon#[25=AT06-04\r\n] 2006.285.12:28:40.40#ibcon#*before write, iclass 16, count 2 2006.285.12:28:40.40#ibcon#enter sib2, iclass 16, count 2 2006.285.12:28:40.40#ibcon#flushed, iclass 16, count 2 2006.285.12:28:40.40#ibcon#about to write, iclass 16, count 2 2006.285.12:28:40.40#ibcon#wrote, iclass 16, count 2 2006.285.12:28:40.40#ibcon#about to read 3, iclass 16, count 2 2006.285.12:28:40.43#ibcon#read 3, iclass 16, count 2 2006.285.12:28:40.43#ibcon#about to read 4, iclass 16, count 2 2006.285.12:28:40.43#ibcon#read 4, iclass 16, count 2 2006.285.12:28:40.43#ibcon#about to read 5, iclass 16, count 2 2006.285.12:28:40.43#ibcon#read 5, iclass 16, count 2 2006.285.12:28:40.43#ibcon#about to read 6, iclass 16, count 2 2006.285.12:28:40.43#ibcon#read 6, iclass 16, count 2 2006.285.12:28:40.43#ibcon#end of sib2, iclass 16, count 2 2006.285.12:28:40.43#ibcon#*after write, iclass 16, count 2 2006.285.12:28:40.43#ibcon#*before return 0, iclass 16, count 2 2006.285.12:28:40.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:28:40.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:28:40.43#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.12:28:40.43#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:40.43#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:28:40.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:28:40.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:28:40.55#ibcon#enter wrdev, iclass 16, count 0 2006.285.12:28:40.55#ibcon#first serial, iclass 16, count 0 2006.285.12:28:40.55#ibcon#enter sib2, iclass 16, count 0 2006.285.12:28:40.55#ibcon#flushed, iclass 16, count 0 2006.285.12:28:40.55#ibcon#about to write, iclass 16, count 0 2006.285.12:28:40.55#ibcon#wrote, iclass 16, count 0 2006.285.12:28:40.55#ibcon#about to read 3, iclass 16, count 0 2006.285.12:28:40.57#ibcon#read 3, iclass 16, count 0 2006.285.12:28:40.57#ibcon#about to read 4, iclass 16, count 0 2006.285.12:28:40.57#ibcon#read 4, iclass 16, count 0 2006.285.12:28:40.57#ibcon#about to read 5, iclass 16, count 0 2006.285.12:28:40.57#ibcon#read 5, iclass 16, count 0 2006.285.12:28:40.57#ibcon#about to read 6, iclass 16, count 0 2006.285.12:28:40.57#ibcon#read 6, iclass 16, count 0 2006.285.12:28:40.57#ibcon#end of sib2, iclass 16, count 0 2006.285.12:28:40.57#ibcon#*mode == 0, iclass 16, count 0 2006.285.12:28:40.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.12:28:40.57#ibcon#[25=USB\r\n] 2006.285.12:28:40.57#ibcon#*before write, iclass 16, count 0 2006.285.12:28:40.57#ibcon#enter sib2, iclass 16, count 0 2006.285.12:28:40.57#ibcon#flushed, iclass 16, count 0 2006.285.12:28:40.57#ibcon#about to write, iclass 16, count 0 2006.285.12:28:40.57#ibcon#wrote, iclass 16, count 0 2006.285.12:28:40.57#ibcon#about to read 3, iclass 16, count 0 2006.285.12:28:40.60#ibcon#read 3, iclass 16, count 0 2006.285.12:28:40.60#ibcon#about to read 4, iclass 16, count 0 2006.285.12:28:40.60#ibcon#read 4, iclass 16, count 0 2006.285.12:28:40.60#ibcon#about to read 5, iclass 16, count 0 2006.285.12:28:40.60#ibcon#read 5, iclass 16, count 0 2006.285.12:28:40.60#ibcon#about to read 6, iclass 16, count 0 2006.285.12:28:40.60#ibcon#read 6, iclass 16, count 0 2006.285.12:28:40.60#ibcon#end of sib2, iclass 16, count 0 2006.285.12:28:40.60#ibcon#*after write, iclass 16, count 0 2006.285.12:28:40.60#ibcon#*before return 0, iclass 16, count 0 2006.285.12:28:40.60#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:28:40.60#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:28:40.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.12:28:40.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.12:28:40.60$vck44/valo=7,864.99 2006.285.12:28:40.60#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.12:28:40.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.12:28:40.60#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:40.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:28:40.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:28:40.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:28:40.60#ibcon#enter wrdev, iclass 18, count 0 2006.285.12:28:40.60#ibcon#first serial, iclass 18, count 0 2006.285.12:28:40.60#ibcon#enter sib2, iclass 18, count 0 2006.285.12:28:40.60#ibcon#flushed, iclass 18, count 0 2006.285.12:28:40.60#ibcon#about to write, iclass 18, count 0 2006.285.12:28:40.60#ibcon#wrote, iclass 18, count 0 2006.285.12:28:40.60#ibcon#about to read 3, iclass 18, count 0 2006.285.12:28:40.62#ibcon#read 3, iclass 18, count 0 2006.285.12:28:40.62#ibcon#about to read 4, iclass 18, count 0 2006.285.12:28:40.62#ibcon#read 4, iclass 18, count 0 2006.285.12:28:40.62#ibcon#about to read 5, iclass 18, count 0 2006.285.12:28:40.62#ibcon#read 5, iclass 18, count 0 2006.285.12:28:40.62#ibcon#about to read 6, iclass 18, count 0 2006.285.12:28:40.62#ibcon#read 6, iclass 18, count 0 2006.285.12:28:40.62#ibcon#end of sib2, iclass 18, count 0 2006.285.12:28:40.62#ibcon#*mode == 0, iclass 18, count 0 2006.285.12:28:40.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.12:28:40.62#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.12:28:40.62#ibcon#*before write, iclass 18, count 0 2006.285.12:28:40.62#ibcon#enter sib2, iclass 18, count 0 2006.285.12:28:40.62#ibcon#flushed, iclass 18, count 0 2006.285.12:28:40.62#ibcon#about to write, iclass 18, count 0 2006.285.12:28:40.62#ibcon#wrote, iclass 18, count 0 2006.285.12:28:40.62#ibcon#about to read 3, iclass 18, count 0 2006.285.12:28:40.66#ibcon#read 3, iclass 18, count 0 2006.285.12:28:40.66#ibcon#about to read 4, iclass 18, count 0 2006.285.12:28:40.66#ibcon#read 4, iclass 18, count 0 2006.285.12:28:40.66#ibcon#about to read 5, iclass 18, count 0 2006.285.12:28:40.66#ibcon#read 5, iclass 18, count 0 2006.285.12:28:40.66#ibcon#about to read 6, iclass 18, count 0 2006.285.12:28:40.66#ibcon#read 6, iclass 18, count 0 2006.285.12:28:40.66#ibcon#end of sib2, iclass 18, count 0 2006.285.12:28:40.66#ibcon#*after write, iclass 18, count 0 2006.285.12:28:40.66#ibcon#*before return 0, iclass 18, count 0 2006.285.12:28:40.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:28:40.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:28:40.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.12:28:40.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.12:28:40.66$vck44/va=7,4 2006.285.12:28:40.66#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.12:28:40.66#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.12:28:40.66#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:40.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:28:40.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:28:40.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:28:40.72#ibcon#enter wrdev, iclass 20, count 2 2006.285.12:28:40.72#ibcon#first serial, iclass 20, count 2 2006.285.12:28:40.72#ibcon#enter sib2, iclass 20, count 2 2006.285.12:28:40.72#ibcon#flushed, iclass 20, count 2 2006.285.12:28:40.72#ibcon#about to write, iclass 20, count 2 2006.285.12:28:40.72#ibcon#wrote, iclass 20, count 2 2006.285.12:28:40.72#ibcon#about to read 3, iclass 20, count 2 2006.285.12:28:40.74#ibcon#read 3, iclass 20, count 2 2006.285.12:28:40.74#ibcon#about to read 4, iclass 20, count 2 2006.285.12:28:40.74#ibcon#read 4, iclass 20, count 2 2006.285.12:28:40.74#ibcon#about to read 5, iclass 20, count 2 2006.285.12:28:40.74#ibcon#read 5, iclass 20, count 2 2006.285.12:28:40.74#ibcon#about to read 6, iclass 20, count 2 2006.285.12:28:40.74#ibcon#read 6, iclass 20, count 2 2006.285.12:28:40.74#ibcon#end of sib2, iclass 20, count 2 2006.285.12:28:40.74#ibcon#*mode == 0, iclass 20, count 2 2006.285.12:28:40.74#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.12:28:40.74#ibcon#[25=AT07-04\r\n] 2006.285.12:28:40.74#ibcon#*before write, iclass 20, count 2 2006.285.12:28:40.74#ibcon#enter sib2, iclass 20, count 2 2006.285.12:28:40.74#ibcon#flushed, iclass 20, count 2 2006.285.12:28:40.74#ibcon#about to write, iclass 20, count 2 2006.285.12:28:40.74#ibcon#wrote, iclass 20, count 2 2006.285.12:28:40.74#ibcon#about to read 3, iclass 20, count 2 2006.285.12:28:40.77#ibcon#read 3, iclass 20, count 2 2006.285.12:28:40.77#ibcon#about to read 4, iclass 20, count 2 2006.285.12:28:40.77#ibcon#read 4, iclass 20, count 2 2006.285.12:28:40.77#ibcon#about to read 5, iclass 20, count 2 2006.285.12:28:40.77#ibcon#read 5, iclass 20, count 2 2006.285.12:28:40.77#ibcon#about to read 6, iclass 20, count 2 2006.285.12:28:40.77#ibcon#read 6, iclass 20, count 2 2006.285.12:28:40.77#ibcon#end of sib2, iclass 20, count 2 2006.285.12:28:40.77#ibcon#*after write, iclass 20, count 2 2006.285.12:28:40.77#ibcon#*before return 0, iclass 20, count 2 2006.285.12:28:40.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:28:40.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:28:40.77#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.12:28:40.77#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:40.77#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:28:40.89#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:28:40.89#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:28:40.89#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:28:40.89#ibcon#first serial, iclass 20, count 0 2006.285.12:28:40.89#ibcon#enter sib2, iclass 20, count 0 2006.285.12:28:40.89#ibcon#flushed, iclass 20, count 0 2006.285.12:28:40.89#ibcon#about to write, iclass 20, count 0 2006.285.12:28:40.89#ibcon#wrote, iclass 20, count 0 2006.285.12:28:40.89#ibcon#about to read 3, iclass 20, count 0 2006.285.12:28:40.91#ibcon#read 3, iclass 20, count 0 2006.285.12:28:40.91#ibcon#about to read 4, iclass 20, count 0 2006.285.12:28:40.91#ibcon#read 4, iclass 20, count 0 2006.285.12:28:40.91#ibcon#about to read 5, iclass 20, count 0 2006.285.12:28:40.91#ibcon#read 5, iclass 20, count 0 2006.285.12:28:40.91#ibcon#about to read 6, iclass 20, count 0 2006.285.12:28:40.91#ibcon#read 6, iclass 20, count 0 2006.285.12:28:40.91#ibcon#end of sib2, iclass 20, count 0 2006.285.12:28:40.91#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:28:40.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:28:40.91#ibcon#[25=USB\r\n] 2006.285.12:28:40.91#ibcon#*before write, iclass 20, count 0 2006.285.12:28:40.91#ibcon#enter sib2, iclass 20, count 0 2006.285.12:28:40.91#ibcon#flushed, iclass 20, count 0 2006.285.12:28:40.91#ibcon#about to write, iclass 20, count 0 2006.285.12:28:40.91#ibcon#wrote, iclass 20, count 0 2006.285.12:28:40.91#ibcon#about to read 3, iclass 20, count 0 2006.285.12:28:40.94#ibcon#read 3, iclass 20, count 0 2006.285.12:28:40.94#ibcon#about to read 4, iclass 20, count 0 2006.285.12:28:40.94#ibcon#read 4, iclass 20, count 0 2006.285.12:28:40.94#ibcon#about to read 5, iclass 20, count 0 2006.285.12:28:40.94#ibcon#read 5, iclass 20, count 0 2006.285.12:28:40.94#ibcon#about to read 6, iclass 20, count 0 2006.285.12:28:40.94#ibcon#read 6, iclass 20, count 0 2006.285.12:28:40.94#ibcon#end of sib2, iclass 20, count 0 2006.285.12:28:40.94#ibcon#*after write, iclass 20, count 0 2006.285.12:28:40.94#ibcon#*before return 0, iclass 20, count 0 2006.285.12:28:40.94#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:28:40.94#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:28:40.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:28:40.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:28:40.94$vck44/valo=8,884.99 2006.285.12:28:40.94#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.12:28:40.94#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.12:28:40.94#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:40.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:28:40.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:28:40.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:28:40.94#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:28:40.94#ibcon#first serial, iclass 22, count 0 2006.285.12:28:40.94#ibcon#enter sib2, iclass 22, count 0 2006.285.12:28:40.94#ibcon#flushed, iclass 22, count 0 2006.285.12:28:40.94#ibcon#about to write, iclass 22, count 0 2006.285.12:28:40.94#ibcon#wrote, iclass 22, count 0 2006.285.12:28:40.94#ibcon#about to read 3, iclass 22, count 0 2006.285.12:28:40.96#ibcon#read 3, iclass 22, count 0 2006.285.12:28:40.96#ibcon#about to read 4, iclass 22, count 0 2006.285.12:28:40.96#ibcon#read 4, iclass 22, count 0 2006.285.12:28:40.96#ibcon#about to read 5, iclass 22, count 0 2006.285.12:28:40.96#ibcon#read 5, iclass 22, count 0 2006.285.12:28:40.96#ibcon#about to read 6, iclass 22, count 0 2006.285.12:28:40.96#ibcon#read 6, iclass 22, count 0 2006.285.12:28:40.96#ibcon#end of sib2, iclass 22, count 0 2006.285.12:28:40.96#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:28:40.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:28:40.96#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.12:28:40.96#ibcon#*before write, iclass 22, count 0 2006.285.12:28:40.96#ibcon#enter sib2, iclass 22, count 0 2006.285.12:28:40.96#ibcon#flushed, iclass 22, count 0 2006.285.12:28:40.96#ibcon#about to write, iclass 22, count 0 2006.285.12:28:40.96#ibcon#wrote, iclass 22, count 0 2006.285.12:28:40.96#ibcon#about to read 3, iclass 22, count 0 2006.285.12:28:41.00#ibcon#read 3, iclass 22, count 0 2006.285.12:28:41.00#ibcon#about to read 4, iclass 22, count 0 2006.285.12:28:41.00#ibcon#read 4, iclass 22, count 0 2006.285.12:28:41.00#ibcon#about to read 5, iclass 22, count 0 2006.285.12:28:41.00#ibcon#read 5, iclass 22, count 0 2006.285.12:28:41.00#ibcon#about to read 6, iclass 22, count 0 2006.285.12:28:41.00#ibcon#read 6, iclass 22, count 0 2006.285.12:28:41.00#ibcon#end of sib2, iclass 22, count 0 2006.285.12:28:41.00#ibcon#*after write, iclass 22, count 0 2006.285.12:28:41.00#ibcon#*before return 0, iclass 22, count 0 2006.285.12:28:41.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:28:41.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:28:41.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:28:41.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:28:41.00$vck44/va=8,3 2006.285.12:28:41.00#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.12:28:41.00#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.12:28:41.00#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:41.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:28:41.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:28:41.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:28:41.06#ibcon#enter wrdev, iclass 24, count 2 2006.285.12:28:41.06#ibcon#first serial, iclass 24, count 2 2006.285.12:28:41.06#ibcon#enter sib2, iclass 24, count 2 2006.285.12:28:41.06#ibcon#flushed, iclass 24, count 2 2006.285.12:28:41.06#ibcon#about to write, iclass 24, count 2 2006.285.12:28:41.06#ibcon#wrote, iclass 24, count 2 2006.285.12:28:41.06#ibcon#about to read 3, iclass 24, count 2 2006.285.12:28:41.08#ibcon#read 3, iclass 24, count 2 2006.285.12:28:41.08#ibcon#about to read 4, iclass 24, count 2 2006.285.12:28:41.08#ibcon#read 4, iclass 24, count 2 2006.285.12:28:41.08#ibcon#about to read 5, iclass 24, count 2 2006.285.12:28:41.08#ibcon#read 5, iclass 24, count 2 2006.285.12:28:41.08#ibcon#about to read 6, iclass 24, count 2 2006.285.12:28:41.08#ibcon#read 6, iclass 24, count 2 2006.285.12:28:41.08#ibcon#end of sib2, iclass 24, count 2 2006.285.12:28:41.08#ibcon#*mode == 0, iclass 24, count 2 2006.285.12:28:41.08#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.12:28:41.08#ibcon#[25=AT08-03\r\n] 2006.285.12:28:41.08#ibcon#*before write, iclass 24, count 2 2006.285.12:28:41.08#ibcon#enter sib2, iclass 24, count 2 2006.285.12:28:41.08#ibcon#flushed, iclass 24, count 2 2006.285.12:28:41.08#ibcon#about to write, iclass 24, count 2 2006.285.12:28:41.08#ibcon#wrote, iclass 24, count 2 2006.285.12:28:41.08#ibcon#about to read 3, iclass 24, count 2 2006.285.12:28:41.11#ibcon#read 3, iclass 24, count 2 2006.285.12:28:41.11#ibcon#about to read 4, iclass 24, count 2 2006.285.12:28:41.11#ibcon#read 4, iclass 24, count 2 2006.285.12:28:41.11#ibcon#about to read 5, iclass 24, count 2 2006.285.12:28:41.11#ibcon#read 5, iclass 24, count 2 2006.285.12:28:41.11#ibcon#about to read 6, iclass 24, count 2 2006.285.12:28:41.11#ibcon#read 6, iclass 24, count 2 2006.285.12:28:41.11#ibcon#end of sib2, iclass 24, count 2 2006.285.12:28:41.11#ibcon#*after write, iclass 24, count 2 2006.285.12:28:41.11#ibcon#*before return 0, iclass 24, count 2 2006.285.12:28:41.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:28:41.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:28:41.11#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.12:28:41.11#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:41.11#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:28:41.23#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:28:41.23#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:28:41.23#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:28:41.23#ibcon#first serial, iclass 24, count 0 2006.285.12:28:41.23#ibcon#enter sib2, iclass 24, count 0 2006.285.12:28:41.23#ibcon#flushed, iclass 24, count 0 2006.285.12:28:41.23#ibcon#about to write, iclass 24, count 0 2006.285.12:28:41.23#ibcon#wrote, iclass 24, count 0 2006.285.12:28:41.23#ibcon#about to read 3, iclass 24, count 0 2006.285.12:28:41.25#ibcon#read 3, iclass 24, count 0 2006.285.12:28:41.25#ibcon#about to read 4, iclass 24, count 0 2006.285.12:28:41.25#ibcon#read 4, iclass 24, count 0 2006.285.12:28:41.25#ibcon#about to read 5, iclass 24, count 0 2006.285.12:28:41.25#ibcon#read 5, iclass 24, count 0 2006.285.12:28:41.25#ibcon#about to read 6, iclass 24, count 0 2006.285.12:28:41.25#ibcon#read 6, iclass 24, count 0 2006.285.12:28:41.25#ibcon#end of sib2, iclass 24, count 0 2006.285.12:28:41.25#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:28:41.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:28:41.25#ibcon#[25=USB\r\n] 2006.285.12:28:41.25#ibcon#*before write, iclass 24, count 0 2006.285.12:28:41.25#ibcon#enter sib2, iclass 24, count 0 2006.285.12:28:41.25#ibcon#flushed, iclass 24, count 0 2006.285.12:28:41.25#ibcon#about to write, iclass 24, count 0 2006.285.12:28:41.25#ibcon#wrote, iclass 24, count 0 2006.285.12:28:41.25#ibcon#about to read 3, iclass 24, count 0 2006.285.12:28:41.28#ibcon#read 3, iclass 24, count 0 2006.285.12:28:41.28#ibcon#about to read 4, iclass 24, count 0 2006.285.12:28:41.28#ibcon#read 4, iclass 24, count 0 2006.285.12:28:41.28#ibcon#about to read 5, iclass 24, count 0 2006.285.12:28:41.28#ibcon#read 5, iclass 24, count 0 2006.285.12:28:41.28#ibcon#about to read 6, iclass 24, count 0 2006.285.12:28:41.28#ibcon#read 6, iclass 24, count 0 2006.285.12:28:41.28#ibcon#end of sib2, iclass 24, count 0 2006.285.12:28:41.28#ibcon#*after write, iclass 24, count 0 2006.285.12:28:41.28#ibcon#*before return 0, iclass 24, count 0 2006.285.12:28:41.28#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:28:41.28#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:28:41.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:28:41.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:28:41.28$vck44/vblo=1,629.99 2006.285.12:28:41.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.12:28:41.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.12:28:41.28#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:41.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:28:41.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:28:41.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:28:41.28#ibcon#enter wrdev, iclass 26, count 0 2006.285.12:28:41.28#ibcon#first serial, iclass 26, count 0 2006.285.12:28:41.28#ibcon#enter sib2, iclass 26, count 0 2006.285.12:28:41.28#ibcon#flushed, iclass 26, count 0 2006.285.12:28:41.28#ibcon#about to write, iclass 26, count 0 2006.285.12:28:41.28#ibcon#wrote, iclass 26, count 0 2006.285.12:28:41.28#ibcon#about to read 3, iclass 26, count 0 2006.285.12:28:41.30#ibcon#read 3, iclass 26, count 0 2006.285.12:28:41.30#ibcon#about to read 4, iclass 26, count 0 2006.285.12:28:41.30#ibcon#read 4, iclass 26, count 0 2006.285.12:28:41.30#ibcon#about to read 5, iclass 26, count 0 2006.285.12:28:41.30#ibcon#read 5, iclass 26, count 0 2006.285.12:28:41.30#ibcon#about to read 6, iclass 26, count 0 2006.285.12:28:41.30#ibcon#read 6, iclass 26, count 0 2006.285.12:28:41.30#ibcon#end of sib2, iclass 26, count 0 2006.285.12:28:41.30#ibcon#*mode == 0, iclass 26, count 0 2006.285.12:28:41.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.12:28:41.30#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.12:28:41.30#ibcon#*before write, iclass 26, count 0 2006.285.12:28:41.30#ibcon#enter sib2, iclass 26, count 0 2006.285.12:28:41.30#ibcon#flushed, iclass 26, count 0 2006.285.12:28:41.30#ibcon#about to write, iclass 26, count 0 2006.285.12:28:41.30#ibcon#wrote, iclass 26, count 0 2006.285.12:28:41.30#ibcon#about to read 3, iclass 26, count 0 2006.285.12:28:41.34#ibcon#read 3, iclass 26, count 0 2006.285.12:28:41.34#ibcon#about to read 4, iclass 26, count 0 2006.285.12:28:41.34#ibcon#read 4, iclass 26, count 0 2006.285.12:28:41.34#ibcon#about to read 5, iclass 26, count 0 2006.285.12:28:41.34#ibcon#read 5, iclass 26, count 0 2006.285.12:28:41.34#ibcon#about to read 6, iclass 26, count 0 2006.285.12:28:41.34#ibcon#read 6, iclass 26, count 0 2006.285.12:28:41.34#ibcon#end of sib2, iclass 26, count 0 2006.285.12:28:41.34#ibcon#*after write, iclass 26, count 0 2006.285.12:28:41.34#ibcon#*before return 0, iclass 26, count 0 2006.285.12:28:41.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:28:41.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:28:41.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.12:28:41.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.12:28:41.34$vck44/vb=1,4 2006.285.12:28:41.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.12:28:41.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.12:28:41.34#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:41.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:28:41.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:28:41.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:28:41.34#ibcon#enter wrdev, iclass 28, count 2 2006.285.12:28:41.34#ibcon#first serial, iclass 28, count 2 2006.285.12:28:41.34#ibcon#enter sib2, iclass 28, count 2 2006.285.12:28:41.34#ibcon#flushed, iclass 28, count 2 2006.285.12:28:41.34#ibcon#about to write, iclass 28, count 2 2006.285.12:28:41.34#ibcon#wrote, iclass 28, count 2 2006.285.12:28:41.34#ibcon#about to read 3, iclass 28, count 2 2006.285.12:28:41.36#ibcon#read 3, iclass 28, count 2 2006.285.12:28:41.36#ibcon#about to read 4, iclass 28, count 2 2006.285.12:28:41.36#ibcon#read 4, iclass 28, count 2 2006.285.12:28:41.36#ibcon#about to read 5, iclass 28, count 2 2006.285.12:28:41.36#ibcon#read 5, iclass 28, count 2 2006.285.12:28:41.36#ibcon#about to read 6, iclass 28, count 2 2006.285.12:28:41.36#ibcon#read 6, iclass 28, count 2 2006.285.12:28:41.36#ibcon#end of sib2, iclass 28, count 2 2006.285.12:28:41.36#ibcon#*mode == 0, iclass 28, count 2 2006.285.12:28:41.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.12:28:41.36#ibcon#[27=AT01-04\r\n] 2006.285.12:28:41.36#ibcon#*before write, iclass 28, count 2 2006.285.12:28:41.36#ibcon#enter sib2, iclass 28, count 2 2006.285.12:28:41.36#ibcon#flushed, iclass 28, count 2 2006.285.12:28:41.36#ibcon#about to write, iclass 28, count 2 2006.285.12:28:41.36#ibcon#wrote, iclass 28, count 2 2006.285.12:28:41.36#ibcon#about to read 3, iclass 28, count 2 2006.285.12:28:41.39#ibcon#read 3, iclass 28, count 2 2006.285.12:28:41.39#ibcon#about to read 4, iclass 28, count 2 2006.285.12:28:41.39#ibcon#read 4, iclass 28, count 2 2006.285.12:28:41.39#ibcon#about to read 5, iclass 28, count 2 2006.285.12:28:41.39#ibcon#read 5, iclass 28, count 2 2006.285.12:28:41.39#ibcon#about to read 6, iclass 28, count 2 2006.285.12:28:41.39#ibcon#read 6, iclass 28, count 2 2006.285.12:28:41.39#ibcon#end of sib2, iclass 28, count 2 2006.285.12:28:41.39#ibcon#*after write, iclass 28, count 2 2006.285.12:28:41.39#ibcon#*before return 0, iclass 28, count 2 2006.285.12:28:41.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:28:41.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:28:41.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.12:28:41.39#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:41.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:28:41.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:28:41.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:28:41.51#ibcon#enter wrdev, iclass 28, count 0 2006.285.12:28:41.51#ibcon#first serial, iclass 28, count 0 2006.285.12:28:41.51#ibcon#enter sib2, iclass 28, count 0 2006.285.12:28:41.51#ibcon#flushed, iclass 28, count 0 2006.285.12:28:41.51#ibcon#about to write, iclass 28, count 0 2006.285.12:28:41.51#ibcon#wrote, iclass 28, count 0 2006.285.12:28:41.51#ibcon#about to read 3, iclass 28, count 0 2006.285.12:28:41.53#ibcon#read 3, iclass 28, count 0 2006.285.12:28:41.53#ibcon#about to read 4, iclass 28, count 0 2006.285.12:28:41.53#ibcon#read 4, iclass 28, count 0 2006.285.12:28:41.53#ibcon#about to read 5, iclass 28, count 0 2006.285.12:28:41.53#ibcon#read 5, iclass 28, count 0 2006.285.12:28:41.53#ibcon#about to read 6, iclass 28, count 0 2006.285.12:28:41.53#ibcon#read 6, iclass 28, count 0 2006.285.12:28:41.53#ibcon#end of sib2, iclass 28, count 0 2006.285.12:28:41.53#ibcon#*mode == 0, iclass 28, count 0 2006.285.12:28:41.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.12:28:41.53#ibcon#[27=USB\r\n] 2006.285.12:28:41.53#ibcon#*before write, iclass 28, count 0 2006.285.12:28:41.53#ibcon#enter sib2, iclass 28, count 0 2006.285.12:28:41.53#ibcon#flushed, iclass 28, count 0 2006.285.12:28:41.53#ibcon#about to write, iclass 28, count 0 2006.285.12:28:41.53#ibcon#wrote, iclass 28, count 0 2006.285.12:28:41.53#ibcon#about to read 3, iclass 28, count 0 2006.285.12:28:41.56#ibcon#read 3, iclass 28, count 0 2006.285.12:28:41.56#ibcon#about to read 4, iclass 28, count 0 2006.285.12:28:41.56#ibcon#read 4, iclass 28, count 0 2006.285.12:28:41.56#ibcon#about to read 5, iclass 28, count 0 2006.285.12:28:41.56#ibcon#read 5, iclass 28, count 0 2006.285.12:28:41.56#ibcon#about to read 6, iclass 28, count 0 2006.285.12:28:41.56#ibcon#read 6, iclass 28, count 0 2006.285.12:28:41.56#ibcon#end of sib2, iclass 28, count 0 2006.285.12:28:41.56#ibcon#*after write, iclass 28, count 0 2006.285.12:28:41.56#ibcon#*before return 0, iclass 28, count 0 2006.285.12:28:41.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:28:41.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:28:41.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.12:28:41.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.12:28:41.56$vck44/vblo=2,634.99 2006.285.12:28:41.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.12:28:41.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.12:28:41.56#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:41.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:28:41.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:28:41.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:28:41.56#ibcon#enter wrdev, iclass 30, count 0 2006.285.12:28:41.56#ibcon#first serial, iclass 30, count 0 2006.285.12:28:41.56#ibcon#enter sib2, iclass 30, count 0 2006.285.12:28:41.56#ibcon#flushed, iclass 30, count 0 2006.285.12:28:41.56#ibcon#about to write, iclass 30, count 0 2006.285.12:28:41.56#ibcon#wrote, iclass 30, count 0 2006.285.12:28:41.56#ibcon#about to read 3, iclass 30, count 0 2006.285.12:28:41.58#ibcon#read 3, iclass 30, count 0 2006.285.12:28:41.58#ibcon#about to read 4, iclass 30, count 0 2006.285.12:28:41.58#ibcon#read 4, iclass 30, count 0 2006.285.12:28:41.58#ibcon#about to read 5, iclass 30, count 0 2006.285.12:28:41.58#ibcon#read 5, iclass 30, count 0 2006.285.12:28:41.58#ibcon#about to read 6, iclass 30, count 0 2006.285.12:28:41.58#ibcon#read 6, iclass 30, count 0 2006.285.12:28:41.58#ibcon#end of sib2, iclass 30, count 0 2006.285.12:28:41.58#ibcon#*mode == 0, iclass 30, count 0 2006.285.12:28:41.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.12:28:41.58#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.12:28:41.58#ibcon#*before write, iclass 30, count 0 2006.285.12:28:41.58#ibcon#enter sib2, iclass 30, count 0 2006.285.12:28:41.58#ibcon#flushed, iclass 30, count 0 2006.285.12:28:41.58#ibcon#about to write, iclass 30, count 0 2006.285.12:28:41.58#ibcon#wrote, iclass 30, count 0 2006.285.12:28:41.58#ibcon#about to read 3, iclass 30, count 0 2006.285.12:28:41.62#ibcon#read 3, iclass 30, count 0 2006.285.12:28:41.62#ibcon#about to read 4, iclass 30, count 0 2006.285.12:28:41.62#ibcon#read 4, iclass 30, count 0 2006.285.12:28:41.62#ibcon#about to read 5, iclass 30, count 0 2006.285.12:28:41.62#ibcon#read 5, iclass 30, count 0 2006.285.12:28:41.62#ibcon#about to read 6, iclass 30, count 0 2006.285.12:28:41.62#ibcon#read 6, iclass 30, count 0 2006.285.12:28:41.62#ibcon#end of sib2, iclass 30, count 0 2006.285.12:28:41.62#ibcon#*after write, iclass 30, count 0 2006.285.12:28:41.62#ibcon#*before return 0, iclass 30, count 0 2006.285.12:28:41.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:28:41.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:28:41.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.12:28:41.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.12:28:41.62$vck44/vb=2,5 2006.285.12:28:41.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.12:28:41.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.12:28:41.62#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:41.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:28:41.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:28:41.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:28:41.68#ibcon#enter wrdev, iclass 32, count 2 2006.285.12:28:41.68#ibcon#first serial, iclass 32, count 2 2006.285.12:28:41.68#ibcon#enter sib2, iclass 32, count 2 2006.285.12:28:41.68#ibcon#flushed, iclass 32, count 2 2006.285.12:28:41.68#ibcon#about to write, iclass 32, count 2 2006.285.12:28:41.68#ibcon#wrote, iclass 32, count 2 2006.285.12:28:41.68#ibcon#about to read 3, iclass 32, count 2 2006.285.12:28:41.70#ibcon#read 3, iclass 32, count 2 2006.285.12:28:41.70#ibcon#about to read 4, iclass 32, count 2 2006.285.12:28:41.70#ibcon#read 4, iclass 32, count 2 2006.285.12:28:41.70#ibcon#about to read 5, iclass 32, count 2 2006.285.12:28:41.70#ibcon#read 5, iclass 32, count 2 2006.285.12:28:41.70#ibcon#about to read 6, iclass 32, count 2 2006.285.12:28:41.70#ibcon#read 6, iclass 32, count 2 2006.285.12:28:41.70#ibcon#end of sib2, iclass 32, count 2 2006.285.12:28:41.70#ibcon#*mode == 0, iclass 32, count 2 2006.285.12:28:41.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.12:28:41.70#ibcon#[27=AT02-05\r\n] 2006.285.12:28:41.70#ibcon#*before write, iclass 32, count 2 2006.285.12:28:41.70#ibcon#enter sib2, iclass 32, count 2 2006.285.12:28:41.70#ibcon#flushed, iclass 32, count 2 2006.285.12:28:41.70#ibcon#about to write, iclass 32, count 2 2006.285.12:28:41.70#ibcon#wrote, iclass 32, count 2 2006.285.12:28:41.70#ibcon#about to read 3, iclass 32, count 2 2006.285.12:28:41.73#ibcon#read 3, iclass 32, count 2 2006.285.12:28:41.73#ibcon#about to read 4, iclass 32, count 2 2006.285.12:28:41.73#ibcon#read 4, iclass 32, count 2 2006.285.12:28:41.73#ibcon#about to read 5, iclass 32, count 2 2006.285.12:28:41.73#ibcon#read 5, iclass 32, count 2 2006.285.12:28:41.73#ibcon#about to read 6, iclass 32, count 2 2006.285.12:28:41.73#ibcon#read 6, iclass 32, count 2 2006.285.12:28:41.73#ibcon#end of sib2, iclass 32, count 2 2006.285.12:28:41.73#ibcon#*after write, iclass 32, count 2 2006.285.12:28:41.73#ibcon#*before return 0, iclass 32, count 2 2006.285.12:28:41.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:28:41.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:28:41.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.12:28:41.73#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:41.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:28:41.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:28:41.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:28:41.85#ibcon#enter wrdev, iclass 32, count 0 2006.285.12:28:41.85#ibcon#first serial, iclass 32, count 0 2006.285.12:28:41.85#ibcon#enter sib2, iclass 32, count 0 2006.285.12:28:41.85#ibcon#flushed, iclass 32, count 0 2006.285.12:28:41.85#ibcon#about to write, iclass 32, count 0 2006.285.12:28:41.85#ibcon#wrote, iclass 32, count 0 2006.285.12:28:41.85#ibcon#about to read 3, iclass 32, count 0 2006.285.12:28:41.87#ibcon#read 3, iclass 32, count 0 2006.285.12:28:41.87#ibcon#about to read 4, iclass 32, count 0 2006.285.12:28:41.87#ibcon#read 4, iclass 32, count 0 2006.285.12:28:41.87#ibcon#about to read 5, iclass 32, count 0 2006.285.12:28:41.87#ibcon#read 5, iclass 32, count 0 2006.285.12:28:41.87#ibcon#about to read 6, iclass 32, count 0 2006.285.12:28:41.87#ibcon#read 6, iclass 32, count 0 2006.285.12:28:41.87#ibcon#end of sib2, iclass 32, count 0 2006.285.12:28:41.87#ibcon#*mode == 0, iclass 32, count 0 2006.285.12:28:41.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.12:28:41.87#ibcon#[27=USB\r\n] 2006.285.12:28:41.87#ibcon#*before write, iclass 32, count 0 2006.285.12:28:41.87#ibcon#enter sib2, iclass 32, count 0 2006.285.12:28:41.87#ibcon#flushed, iclass 32, count 0 2006.285.12:28:41.87#ibcon#about to write, iclass 32, count 0 2006.285.12:28:41.87#ibcon#wrote, iclass 32, count 0 2006.285.12:28:41.87#ibcon#about to read 3, iclass 32, count 0 2006.285.12:28:41.90#ibcon#read 3, iclass 32, count 0 2006.285.12:28:41.90#ibcon#about to read 4, iclass 32, count 0 2006.285.12:28:41.90#ibcon#read 4, iclass 32, count 0 2006.285.12:28:41.90#ibcon#about to read 5, iclass 32, count 0 2006.285.12:28:41.90#ibcon#read 5, iclass 32, count 0 2006.285.12:28:41.90#ibcon#about to read 6, iclass 32, count 0 2006.285.12:28:41.90#ibcon#read 6, iclass 32, count 0 2006.285.12:28:41.90#ibcon#end of sib2, iclass 32, count 0 2006.285.12:28:41.90#ibcon#*after write, iclass 32, count 0 2006.285.12:28:41.90#ibcon#*before return 0, iclass 32, count 0 2006.285.12:28:41.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:28:41.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:28:41.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.12:28:41.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.12:28:41.90$vck44/vblo=3,649.99 2006.285.12:28:41.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.12:28:41.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.12:28:41.90#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:41.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:28:41.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:28:41.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:28:41.90#ibcon#enter wrdev, iclass 34, count 0 2006.285.12:28:41.90#ibcon#first serial, iclass 34, count 0 2006.285.12:28:41.90#ibcon#enter sib2, iclass 34, count 0 2006.285.12:28:41.90#ibcon#flushed, iclass 34, count 0 2006.285.12:28:41.90#ibcon#about to write, iclass 34, count 0 2006.285.12:28:41.90#ibcon#wrote, iclass 34, count 0 2006.285.12:28:41.90#ibcon#about to read 3, iclass 34, count 0 2006.285.12:28:41.92#ibcon#read 3, iclass 34, count 0 2006.285.12:28:41.92#ibcon#about to read 4, iclass 34, count 0 2006.285.12:28:41.92#ibcon#read 4, iclass 34, count 0 2006.285.12:28:41.92#ibcon#about to read 5, iclass 34, count 0 2006.285.12:28:41.92#ibcon#read 5, iclass 34, count 0 2006.285.12:28:41.92#ibcon#about to read 6, iclass 34, count 0 2006.285.12:28:41.92#ibcon#read 6, iclass 34, count 0 2006.285.12:28:41.92#ibcon#end of sib2, iclass 34, count 0 2006.285.12:28:41.92#ibcon#*mode == 0, iclass 34, count 0 2006.285.12:28:41.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.12:28:41.92#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.12:28:41.92#ibcon#*before write, iclass 34, count 0 2006.285.12:28:41.92#ibcon#enter sib2, iclass 34, count 0 2006.285.12:28:41.92#ibcon#flushed, iclass 34, count 0 2006.285.12:28:41.92#ibcon#about to write, iclass 34, count 0 2006.285.12:28:41.92#ibcon#wrote, iclass 34, count 0 2006.285.12:28:41.92#ibcon#about to read 3, iclass 34, count 0 2006.285.12:28:41.96#ibcon#read 3, iclass 34, count 0 2006.285.12:28:41.96#ibcon#about to read 4, iclass 34, count 0 2006.285.12:28:41.96#ibcon#read 4, iclass 34, count 0 2006.285.12:28:41.96#ibcon#about to read 5, iclass 34, count 0 2006.285.12:28:41.96#ibcon#read 5, iclass 34, count 0 2006.285.12:28:41.96#ibcon#about to read 6, iclass 34, count 0 2006.285.12:28:41.96#ibcon#read 6, iclass 34, count 0 2006.285.12:28:41.96#ibcon#end of sib2, iclass 34, count 0 2006.285.12:28:41.96#ibcon#*after write, iclass 34, count 0 2006.285.12:28:41.96#ibcon#*before return 0, iclass 34, count 0 2006.285.12:28:41.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:28:41.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:28:41.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.12:28:41.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.12:28:41.96$vck44/vb=3,4 2006.285.12:28:41.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.12:28:41.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.12:28:41.96#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:41.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:28:42.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:28:42.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:28:42.02#ibcon#enter wrdev, iclass 36, count 2 2006.285.12:28:42.02#ibcon#first serial, iclass 36, count 2 2006.285.12:28:42.02#ibcon#enter sib2, iclass 36, count 2 2006.285.12:28:42.02#ibcon#flushed, iclass 36, count 2 2006.285.12:28:42.02#ibcon#about to write, iclass 36, count 2 2006.285.12:28:42.02#ibcon#wrote, iclass 36, count 2 2006.285.12:28:42.02#ibcon#about to read 3, iclass 36, count 2 2006.285.12:28:42.04#ibcon#read 3, iclass 36, count 2 2006.285.12:28:42.04#ibcon#about to read 4, iclass 36, count 2 2006.285.12:28:42.04#ibcon#read 4, iclass 36, count 2 2006.285.12:28:42.04#ibcon#about to read 5, iclass 36, count 2 2006.285.12:28:42.04#ibcon#read 5, iclass 36, count 2 2006.285.12:28:42.04#ibcon#about to read 6, iclass 36, count 2 2006.285.12:28:42.04#ibcon#read 6, iclass 36, count 2 2006.285.12:28:42.04#ibcon#end of sib2, iclass 36, count 2 2006.285.12:28:42.04#ibcon#*mode == 0, iclass 36, count 2 2006.285.12:28:42.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.12:28:42.04#ibcon#[27=AT03-04\r\n] 2006.285.12:28:42.04#ibcon#*before write, iclass 36, count 2 2006.285.12:28:42.04#ibcon#enter sib2, iclass 36, count 2 2006.285.12:28:42.04#ibcon#flushed, iclass 36, count 2 2006.285.12:28:42.04#ibcon#about to write, iclass 36, count 2 2006.285.12:28:42.04#ibcon#wrote, iclass 36, count 2 2006.285.12:28:42.04#ibcon#about to read 3, iclass 36, count 2 2006.285.12:28:42.07#ibcon#read 3, iclass 36, count 2 2006.285.12:28:42.07#ibcon#about to read 4, iclass 36, count 2 2006.285.12:28:42.07#ibcon#read 4, iclass 36, count 2 2006.285.12:28:42.07#ibcon#about to read 5, iclass 36, count 2 2006.285.12:28:42.07#ibcon#read 5, iclass 36, count 2 2006.285.12:28:42.07#ibcon#about to read 6, iclass 36, count 2 2006.285.12:28:42.07#ibcon#read 6, iclass 36, count 2 2006.285.12:28:42.07#ibcon#end of sib2, iclass 36, count 2 2006.285.12:28:42.07#ibcon#*after write, iclass 36, count 2 2006.285.12:28:42.07#ibcon#*before return 0, iclass 36, count 2 2006.285.12:28:42.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:28:42.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:28:42.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.12:28:42.07#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:42.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:28:42.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:28:42.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:28:42.19#ibcon#enter wrdev, iclass 36, count 0 2006.285.12:28:42.19#ibcon#first serial, iclass 36, count 0 2006.285.12:28:42.19#ibcon#enter sib2, iclass 36, count 0 2006.285.12:28:42.19#ibcon#flushed, iclass 36, count 0 2006.285.12:28:42.19#ibcon#about to write, iclass 36, count 0 2006.285.12:28:42.19#ibcon#wrote, iclass 36, count 0 2006.285.12:28:42.19#ibcon#about to read 3, iclass 36, count 0 2006.285.12:28:42.21#ibcon#read 3, iclass 36, count 0 2006.285.12:28:42.21#ibcon#about to read 4, iclass 36, count 0 2006.285.12:28:42.21#ibcon#read 4, iclass 36, count 0 2006.285.12:28:42.21#ibcon#about to read 5, iclass 36, count 0 2006.285.12:28:42.21#ibcon#read 5, iclass 36, count 0 2006.285.12:28:42.21#ibcon#about to read 6, iclass 36, count 0 2006.285.12:28:42.21#ibcon#read 6, iclass 36, count 0 2006.285.12:28:42.21#ibcon#end of sib2, iclass 36, count 0 2006.285.12:28:42.21#ibcon#*mode == 0, iclass 36, count 0 2006.285.12:28:42.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.12:28:42.21#ibcon#[27=USB\r\n] 2006.285.12:28:42.21#ibcon#*before write, iclass 36, count 0 2006.285.12:28:42.21#ibcon#enter sib2, iclass 36, count 0 2006.285.12:28:42.21#ibcon#flushed, iclass 36, count 0 2006.285.12:28:42.21#ibcon#about to write, iclass 36, count 0 2006.285.12:28:42.21#ibcon#wrote, iclass 36, count 0 2006.285.12:28:42.21#ibcon#about to read 3, iclass 36, count 0 2006.285.12:28:42.24#ibcon#read 3, iclass 36, count 0 2006.285.12:28:42.24#ibcon#about to read 4, iclass 36, count 0 2006.285.12:28:42.24#ibcon#read 4, iclass 36, count 0 2006.285.12:28:42.24#ibcon#about to read 5, iclass 36, count 0 2006.285.12:28:42.24#ibcon#read 5, iclass 36, count 0 2006.285.12:28:42.24#ibcon#about to read 6, iclass 36, count 0 2006.285.12:28:42.24#ibcon#read 6, iclass 36, count 0 2006.285.12:28:42.24#ibcon#end of sib2, iclass 36, count 0 2006.285.12:28:42.24#ibcon#*after write, iclass 36, count 0 2006.285.12:28:42.24#ibcon#*before return 0, iclass 36, count 0 2006.285.12:28:42.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:28:42.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:28:42.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.12:28:42.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.12:28:42.24$vck44/vblo=4,679.99 2006.285.12:28:42.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.12:28:42.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.12:28:42.24#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:42.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:28:42.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:28:42.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:28:42.24#ibcon#enter wrdev, iclass 38, count 0 2006.285.12:28:42.24#ibcon#first serial, iclass 38, count 0 2006.285.12:28:42.24#ibcon#enter sib2, iclass 38, count 0 2006.285.12:28:42.24#ibcon#flushed, iclass 38, count 0 2006.285.12:28:42.24#ibcon#about to write, iclass 38, count 0 2006.285.12:28:42.24#ibcon#wrote, iclass 38, count 0 2006.285.12:28:42.24#ibcon#about to read 3, iclass 38, count 0 2006.285.12:28:42.26#ibcon#read 3, iclass 38, count 0 2006.285.12:28:42.26#ibcon#about to read 4, iclass 38, count 0 2006.285.12:28:42.26#ibcon#read 4, iclass 38, count 0 2006.285.12:28:42.26#ibcon#about to read 5, iclass 38, count 0 2006.285.12:28:42.26#ibcon#read 5, iclass 38, count 0 2006.285.12:28:42.26#ibcon#about to read 6, iclass 38, count 0 2006.285.12:28:42.26#ibcon#read 6, iclass 38, count 0 2006.285.12:28:42.26#ibcon#end of sib2, iclass 38, count 0 2006.285.12:28:42.26#ibcon#*mode == 0, iclass 38, count 0 2006.285.12:28:42.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.12:28:42.26#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.12:28:42.26#ibcon#*before write, iclass 38, count 0 2006.285.12:28:42.26#ibcon#enter sib2, iclass 38, count 0 2006.285.12:28:42.26#ibcon#flushed, iclass 38, count 0 2006.285.12:28:42.26#ibcon#about to write, iclass 38, count 0 2006.285.12:28:42.26#ibcon#wrote, iclass 38, count 0 2006.285.12:28:42.26#ibcon#about to read 3, iclass 38, count 0 2006.285.12:28:42.30#ibcon#read 3, iclass 38, count 0 2006.285.12:28:42.30#ibcon#about to read 4, iclass 38, count 0 2006.285.12:28:42.30#ibcon#read 4, iclass 38, count 0 2006.285.12:28:42.30#ibcon#about to read 5, iclass 38, count 0 2006.285.12:28:42.30#ibcon#read 5, iclass 38, count 0 2006.285.12:28:42.30#ibcon#about to read 6, iclass 38, count 0 2006.285.12:28:42.30#ibcon#read 6, iclass 38, count 0 2006.285.12:28:42.30#ibcon#end of sib2, iclass 38, count 0 2006.285.12:28:42.30#ibcon#*after write, iclass 38, count 0 2006.285.12:28:42.30#ibcon#*before return 0, iclass 38, count 0 2006.285.12:28:42.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:28:42.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:28:42.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.12:28:42.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.12:28:42.30$vck44/vb=4,5 2006.285.12:28:42.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.12:28:42.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.12:28:42.30#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:42.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:28:42.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:28:42.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:28:42.36#ibcon#enter wrdev, iclass 40, count 2 2006.285.12:28:42.36#ibcon#first serial, iclass 40, count 2 2006.285.12:28:42.36#ibcon#enter sib2, iclass 40, count 2 2006.285.12:28:42.36#ibcon#flushed, iclass 40, count 2 2006.285.12:28:42.36#ibcon#about to write, iclass 40, count 2 2006.285.12:28:42.36#ibcon#wrote, iclass 40, count 2 2006.285.12:28:42.36#ibcon#about to read 3, iclass 40, count 2 2006.285.12:28:42.38#ibcon#read 3, iclass 40, count 2 2006.285.12:28:42.38#ibcon#about to read 4, iclass 40, count 2 2006.285.12:28:42.38#ibcon#read 4, iclass 40, count 2 2006.285.12:28:42.38#ibcon#about to read 5, iclass 40, count 2 2006.285.12:28:42.38#ibcon#read 5, iclass 40, count 2 2006.285.12:28:42.38#ibcon#about to read 6, iclass 40, count 2 2006.285.12:28:42.38#ibcon#read 6, iclass 40, count 2 2006.285.12:28:42.38#ibcon#end of sib2, iclass 40, count 2 2006.285.12:28:42.38#ibcon#*mode == 0, iclass 40, count 2 2006.285.12:28:42.38#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.12:28:42.38#ibcon#[27=AT04-05\r\n] 2006.285.12:28:42.38#ibcon#*before write, iclass 40, count 2 2006.285.12:28:42.38#ibcon#enter sib2, iclass 40, count 2 2006.285.12:28:42.38#ibcon#flushed, iclass 40, count 2 2006.285.12:28:42.38#ibcon#about to write, iclass 40, count 2 2006.285.12:28:42.38#ibcon#wrote, iclass 40, count 2 2006.285.12:28:42.38#ibcon#about to read 3, iclass 40, count 2 2006.285.12:28:42.41#ibcon#read 3, iclass 40, count 2 2006.285.12:28:42.41#ibcon#about to read 4, iclass 40, count 2 2006.285.12:28:42.41#ibcon#read 4, iclass 40, count 2 2006.285.12:28:42.41#ibcon#about to read 5, iclass 40, count 2 2006.285.12:28:42.41#ibcon#read 5, iclass 40, count 2 2006.285.12:28:42.41#ibcon#about to read 6, iclass 40, count 2 2006.285.12:28:42.41#ibcon#read 6, iclass 40, count 2 2006.285.12:28:42.41#ibcon#end of sib2, iclass 40, count 2 2006.285.12:28:42.41#ibcon#*after write, iclass 40, count 2 2006.285.12:28:42.41#ibcon#*before return 0, iclass 40, count 2 2006.285.12:28:42.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:28:42.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:28:42.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.12:28:42.41#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:42.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:28:42.51#abcon#<5=/05 1.2 2.2 18.78 961015.5\r\n> 2006.285.12:28:42.53#abcon#{5=INTERFACE CLEAR} 2006.285.12:28:42.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:28:42.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:28:42.53#ibcon#enter wrdev, iclass 40, count 0 2006.285.12:28:42.53#ibcon#first serial, iclass 40, count 0 2006.285.12:28:42.53#ibcon#enter sib2, iclass 40, count 0 2006.285.12:28:42.53#ibcon#flushed, iclass 40, count 0 2006.285.12:28:42.53#ibcon#about to write, iclass 40, count 0 2006.285.12:28:42.53#ibcon#wrote, iclass 40, count 0 2006.285.12:28:42.53#ibcon#about to read 3, iclass 40, count 0 2006.285.12:28:42.55#ibcon#read 3, iclass 40, count 0 2006.285.12:28:42.55#ibcon#about to read 4, iclass 40, count 0 2006.285.12:28:42.55#ibcon#read 4, iclass 40, count 0 2006.285.12:28:42.55#ibcon#about to read 5, iclass 40, count 0 2006.285.12:28:42.55#ibcon#read 5, iclass 40, count 0 2006.285.12:28:42.55#ibcon#about to read 6, iclass 40, count 0 2006.285.12:28:42.55#ibcon#read 6, iclass 40, count 0 2006.285.12:28:42.55#ibcon#end of sib2, iclass 40, count 0 2006.285.12:28:42.55#ibcon#*mode == 0, iclass 40, count 0 2006.285.12:28:42.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.12:28:42.55#ibcon#[27=USB\r\n] 2006.285.12:28:42.55#ibcon#*before write, iclass 40, count 0 2006.285.12:28:42.55#ibcon#enter sib2, iclass 40, count 0 2006.285.12:28:42.55#ibcon#flushed, iclass 40, count 0 2006.285.12:28:42.55#ibcon#about to write, iclass 40, count 0 2006.285.12:28:42.55#ibcon#wrote, iclass 40, count 0 2006.285.12:28:42.55#ibcon#about to read 3, iclass 40, count 0 2006.285.12:28:42.58#ibcon#read 3, iclass 40, count 0 2006.285.12:28:42.58#ibcon#about to read 4, iclass 40, count 0 2006.285.12:28:42.58#ibcon#read 4, iclass 40, count 0 2006.285.12:28:42.58#ibcon#about to read 5, iclass 40, count 0 2006.285.12:28:42.58#ibcon#read 5, iclass 40, count 0 2006.285.12:28:42.58#ibcon#about to read 6, iclass 40, count 0 2006.285.12:28:42.58#ibcon#read 6, iclass 40, count 0 2006.285.12:28:42.58#ibcon#end of sib2, iclass 40, count 0 2006.285.12:28:42.58#ibcon#*after write, iclass 40, count 0 2006.285.12:28:42.58#ibcon#*before return 0, iclass 40, count 0 2006.285.12:28:42.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:28:42.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:28:42.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.12:28:42.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.12:28:42.58$vck44/vblo=5,709.99 2006.285.12:28:42.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.12:28:42.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.12:28:42.58#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:42.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:28:42.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:28:42.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:28:42.58#ibcon#enter wrdev, iclass 10, count 0 2006.285.12:28:42.58#ibcon#first serial, iclass 10, count 0 2006.285.12:28:42.58#ibcon#enter sib2, iclass 10, count 0 2006.285.12:28:42.58#ibcon#flushed, iclass 10, count 0 2006.285.12:28:42.58#ibcon#about to write, iclass 10, count 0 2006.285.12:28:42.58#ibcon#wrote, iclass 10, count 0 2006.285.12:28:42.58#ibcon#about to read 3, iclass 10, count 0 2006.285.12:28:42.59#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:28:42.60#ibcon#read 3, iclass 10, count 0 2006.285.12:28:42.60#ibcon#about to read 4, iclass 10, count 0 2006.285.12:28:42.60#ibcon#read 4, iclass 10, count 0 2006.285.12:28:42.60#ibcon#about to read 5, iclass 10, count 0 2006.285.12:28:42.60#ibcon#read 5, iclass 10, count 0 2006.285.12:28:42.60#ibcon#about to read 6, iclass 10, count 0 2006.285.12:28:42.60#ibcon#read 6, iclass 10, count 0 2006.285.12:28:42.60#ibcon#end of sib2, iclass 10, count 0 2006.285.12:28:42.60#ibcon#*mode == 0, iclass 10, count 0 2006.285.12:28:42.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.12:28:42.60#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.12:28:42.60#ibcon#*before write, iclass 10, count 0 2006.285.12:28:42.60#ibcon#enter sib2, iclass 10, count 0 2006.285.12:28:42.60#ibcon#flushed, iclass 10, count 0 2006.285.12:28:42.60#ibcon#about to write, iclass 10, count 0 2006.285.12:28:42.60#ibcon#wrote, iclass 10, count 0 2006.285.12:28:42.60#ibcon#about to read 3, iclass 10, count 0 2006.285.12:28:42.64#ibcon#read 3, iclass 10, count 0 2006.285.12:28:42.64#ibcon#about to read 4, iclass 10, count 0 2006.285.12:28:42.64#ibcon#read 4, iclass 10, count 0 2006.285.12:28:42.64#ibcon#about to read 5, iclass 10, count 0 2006.285.12:28:42.64#ibcon#read 5, iclass 10, count 0 2006.285.12:28:42.64#ibcon#about to read 6, iclass 10, count 0 2006.285.12:28:42.64#ibcon#read 6, iclass 10, count 0 2006.285.12:28:42.64#ibcon#end of sib2, iclass 10, count 0 2006.285.12:28:42.64#ibcon#*after write, iclass 10, count 0 2006.285.12:28:42.64#ibcon#*before return 0, iclass 10, count 0 2006.285.12:28:42.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:28:42.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:28:42.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.12:28:42.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.12:28:42.64$vck44/vb=5,4 2006.285.12:28:42.64#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.12:28:42.64#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.12:28:42.64#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:42.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:28:42.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:28:42.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:28:42.70#ibcon#enter wrdev, iclass 12, count 2 2006.285.12:28:42.70#ibcon#first serial, iclass 12, count 2 2006.285.12:28:42.70#ibcon#enter sib2, iclass 12, count 2 2006.285.12:28:42.70#ibcon#flushed, iclass 12, count 2 2006.285.12:28:42.70#ibcon#about to write, iclass 12, count 2 2006.285.12:28:42.70#ibcon#wrote, iclass 12, count 2 2006.285.12:28:42.70#ibcon#about to read 3, iclass 12, count 2 2006.285.12:28:42.72#ibcon#read 3, iclass 12, count 2 2006.285.12:28:42.72#ibcon#about to read 4, iclass 12, count 2 2006.285.12:28:42.72#ibcon#read 4, iclass 12, count 2 2006.285.12:28:42.72#ibcon#about to read 5, iclass 12, count 2 2006.285.12:28:42.72#ibcon#read 5, iclass 12, count 2 2006.285.12:28:42.72#ibcon#about to read 6, iclass 12, count 2 2006.285.12:28:42.72#ibcon#read 6, iclass 12, count 2 2006.285.12:28:42.72#ibcon#end of sib2, iclass 12, count 2 2006.285.12:28:42.72#ibcon#*mode == 0, iclass 12, count 2 2006.285.12:28:42.72#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.12:28:42.72#ibcon#[27=AT05-04\r\n] 2006.285.12:28:42.72#ibcon#*before write, iclass 12, count 2 2006.285.12:28:42.72#ibcon#enter sib2, iclass 12, count 2 2006.285.12:28:42.72#ibcon#flushed, iclass 12, count 2 2006.285.12:28:42.72#ibcon#about to write, iclass 12, count 2 2006.285.12:28:42.72#ibcon#wrote, iclass 12, count 2 2006.285.12:28:42.72#ibcon#about to read 3, iclass 12, count 2 2006.285.12:28:42.75#ibcon#read 3, iclass 12, count 2 2006.285.12:28:42.75#ibcon#about to read 4, iclass 12, count 2 2006.285.12:28:42.75#ibcon#read 4, iclass 12, count 2 2006.285.12:28:42.75#ibcon#about to read 5, iclass 12, count 2 2006.285.12:28:42.75#ibcon#read 5, iclass 12, count 2 2006.285.12:28:42.75#ibcon#about to read 6, iclass 12, count 2 2006.285.12:28:42.75#ibcon#read 6, iclass 12, count 2 2006.285.12:28:42.75#ibcon#end of sib2, iclass 12, count 2 2006.285.12:28:42.75#ibcon#*after write, iclass 12, count 2 2006.285.12:28:42.75#ibcon#*before return 0, iclass 12, count 2 2006.285.12:28:42.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:28:42.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:28:42.75#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.12:28:42.75#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:42.75#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:28:42.87#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:28:42.87#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:28:42.87#ibcon#enter wrdev, iclass 12, count 0 2006.285.12:28:42.87#ibcon#first serial, iclass 12, count 0 2006.285.12:28:42.87#ibcon#enter sib2, iclass 12, count 0 2006.285.12:28:42.87#ibcon#flushed, iclass 12, count 0 2006.285.12:28:42.87#ibcon#about to write, iclass 12, count 0 2006.285.12:28:42.87#ibcon#wrote, iclass 12, count 0 2006.285.12:28:42.87#ibcon#about to read 3, iclass 12, count 0 2006.285.12:28:42.89#ibcon#read 3, iclass 12, count 0 2006.285.12:28:42.89#ibcon#about to read 4, iclass 12, count 0 2006.285.12:28:42.89#ibcon#read 4, iclass 12, count 0 2006.285.12:28:42.89#ibcon#about to read 5, iclass 12, count 0 2006.285.12:28:42.89#ibcon#read 5, iclass 12, count 0 2006.285.12:28:42.89#ibcon#about to read 6, iclass 12, count 0 2006.285.12:28:42.89#ibcon#read 6, iclass 12, count 0 2006.285.12:28:42.89#ibcon#end of sib2, iclass 12, count 0 2006.285.12:28:42.89#ibcon#*mode == 0, iclass 12, count 0 2006.285.12:28:42.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.12:28:42.89#ibcon#[27=USB\r\n] 2006.285.12:28:42.89#ibcon#*before write, iclass 12, count 0 2006.285.12:28:42.89#ibcon#enter sib2, iclass 12, count 0 2006.285.12:28:42.89#ibcon#flushed, iclass 12, count 0 2006.285.12:28:42.89#ibcon#about to write, iclass 12, count 0 2006.285.12:28:42.89#ibcon#wrote, iclass 12, count 0 2006.285.12:28:42.89#ibcon#about to read 3, iclass 12, count 0 2006.285.12:28:42.92#ibcon#read 3, iclass 12, count 0 2006.285.12:28:42.92#ibcon#about to read 4, iclass 12, count 0 2006.285.12:28:42.92#ibcon#read 4, iclass 12, count 0 2006.285.12:28:42.92#ibcon#about to read 5, iclass 12, count 0 2006.285.12:28:42.92#ibcon#read 5, iclass 12, count 0 2006.285.12:28:42.92#ibcon#about to read 6, iclass 12, count 0 2006.285.12:28:42.92#ibcon#read 6, iclass 12, count 0 2006.285.12:28:42.92#ibcon#end of sib2, iclass 12, count 0 2006.285.12:28:42.92#ibcon#*after write, iclass 12, count 0 2006.285.12:28:42.92#ibcon#*before return 0, iclass 12, count 0 2006.285.12:28:42.92#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:28:42.92#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:28:42.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.12:28:42.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.12:28:42.92$vck44/vblo=6,719.99 2006.285.12:28:42.92#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.12:28:42.92#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.12:28:42.92#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:42.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:28:42.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:28:42.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:28:42.92#ibcon#enter wrdev, iclass 14, count 0 2006.285.12:28:42.92#ibcon#first serial, iclass 14, count 0 2006.285.12:28:42.92#ibcon#enter sib2, iclass 14, count 0 2006.285.12:28:42.92#ibcon#flushed, iclass 14, count 0 2006.285.12:28:42.92#ibcon#about to write, iclass 14, count 0 2006.285.12:28:42.92#ibcon#wrote, iclass 14, count 0 2006.285.12:28:42.92#ibcon#about to read 3, iclass 14, count 0 2006.285.12:28:42.94#ibcon#read 3, iclass 14, count 0 2006.285.12:28:42.94#ibcon#about to read 4, iclass 14, count 0 2006.285.12:28:42.94#ibcon#read 4, iclass 14, count 0 2006.285.12:28:42.94#ibcon#about to read 5, iclass 14, count 0 2006.285.12:28:42.94#ibcon#read 5, iclass 14, count 0 2006.285.12:28:42.94#ibcon#about to read 6, iclass 14, count 0 2006.285.12:28:42.94#ibcon#read 6, iclass 14, count 0 2006.285.12:28:42.94#ibcon#end of sib2, iclass 14, count 0 2006.285.12:28:42.94#ibcon#*mode == 0, iclass 14, count 0 2006.285.12:28:42.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.12:28:42.94#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.12:28:42.94#ibcon#*before write, iclass 14, count 0 2006.285.12:28:42.94#ibcon#enter sib2, iclass 14, count 0 2006.285.12:28:42.94#ibcon#flushed, iclass 14, count 0 2006.285.12:28:42.94#ibcon#about to write, iclass 14, count 0 2006.285.12:28:42.94#ibcon#wrote, iclass 14, count 0 2006.285.12:28:42.94#ibcon#about to read 3, iclass 14, count 0 2006.285.12:28:42.98#ibcon#read 3, iclass 14, count 0 2006.285.12:28:42.98#ibcon#about to read 4, iclass 14, count 0 2006.285.12:28:42.98#ibcon#read 4, iclass 14, count 0 2006.285.12:28:42.98#ibcon#about to read 5, iclass 14, count 0 2006.285.12:28:42.98#ibcon#read 5, iclass 14, count 0 2006.285.12:28:42.98#ibcon#about to read 6, iclass 14, count 0 2006.285.12:28:42.98#ibcon#read 6, iclass 14, count 0 2006.285.12:28:42.98#ibcon#end of sib2, iclass 14, count 0 2006.285.12:28:42.98#ibcon#*after write, iclass 14, count 0 2006.285.12:28:42.98#ibcon#*before return 0, iclass 14, count 0 2006.285.12:28:42.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:28:42.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:28:42.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.12:28:42.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.12:28:42.98$vck44/vb=6,3 2006.285.12:28:42.98#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.12:28:42.98#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.12:28:42.98#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:42.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:28:43.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:28:43.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:28:43.04#ibcon#enter wrdev, iclass 16, count 2 2006.285.12:28:43.04#ibcon#first serial, iclass 16, count 2 2006.285.12:28:43.04#ibcon#enter sib2, iclass 16, count 2 2006.285.12:28:43.04#ibcon#flushed, iclass 16, count 2 2006.285.12:28:43.04#ibcon#about to write, iclass 16, count 2 2006.285.12:28:43.04#ibcon#wrote, iclass 16, count 2 2006.285.12:28:43.04#ibcon#about to read 3, iclass 16, count 2 2006.285.12:28:43.06#ibcon#read 3, iclass 16, count 2 2006.285.12:28:43.06#ibcon#about to read 4, iclass 16, count 2 2006.285.12:28:43.06#ibcon#read 4, iclass 16, count 2 2006.285.12:28:43.06#ibcon#about to read 5, iclass 16, count 2 2006.285.12:28:43.06#ibcon#read 5, iclass 16, count 2 2006.285.12:28:43.06#ibcon#about to read 6, iclass 16, count 2 2006.285.12:28:43.06#ibcon#read 6, iclass 16, count 2 2006.285.12:28:43.06#ibcon#end of sib2, iclass 16, count 2 2006.285.12:28:43.06#ibcon#*mode == 0, iclass 16, count 2 2006.285.12:28:43.06#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.12:28:43.06#ibcon#[27=AT06-03\r\n] 2006.285.12:28:43.06#ibcon#*before write, iclass 16, count 2 2006.285.12:28:43.06#ibcon#enter sib2, iclass 16, count 2 2006.285.12:28:43.06#ibcon#flushed, iclass 16, count 2 2006.285.12:28:43.06#ibcon#about to write, iclass 16, count 2 2006.285.12:28:43.06#ibcon#wrote, iclass 16, count 2 2006.285.12:28:43.06#ibcon#about to read 3, iclass 16, count 2 2006.285.12:28:43.09#ibcon#read 3, iclass 16, count 2 2006.285.12:28:43.09#ibcon#about to read 4, iclass 16, count 2 2006.285.12:28:43.09#ibcon#read 4, iclass 16, count 2 2006.285.12:28:43.09#ibcon#about to read 5, iclass 16, count 2 2006.285.12:28:43.09#ibcon#read 5, iclass 16, count 2 2006.285.12:28:43.09#ibcon#about to read 6, iclass 16, count 2 2006.285.12:28:43.09#ibcon#read 6, iclass 16, count 2 2006.285.12:28:43.09#ibcon#end of sib2, iclass 16, count 2 2006.285.12:28:43.09#ibcon#*after write, iclass 16, count 2 2006.285.12:28:43.09#ibcon#*before return 0, iclass 16, count 2 2006.285.12:28:43.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:28:43.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:28:43.09#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.12:28:43.09#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:43.09#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:28:43.21#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:28:43.21#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:28:43.21#ibcon#enter wrdev, iclass 16, count 0 2006.285.12:28:43.21#ibcon#first serial, iclass 16, count 0 2006.285.12:28:43.21#ibcon#enter sib2, iclass 16, count 0 2006.285.12:28:43.21#ibcon#flushed, iclass 16, count 0 2006.285.12:28:43.21#ibcon#about to write, iclass 16, count 0 2006.285.12:28:43.21#ibcon#wrote, iclass 16, count 0 2006.285.12:28:43.21#ibcon#about to read 3, iclass 16, count 0 2006.285.12:28:43.23#ibcon#read 3, iclass 16, count 0 2006.285.12:28:43.23#ibcon#about to read 4, iclass 16, count 0 2006.285.12:28:43.23#ibcon#read 4, iclass 16, count 0 2006.285.12:28:43.23#ibcon#about to read 5, iclass 16, count 0 2006.285.12:28:43.23#ibcon#read 5, iclass 16, count 0 2006.285.12:28:43.23#ibcon#about to read 6, iclass 16, count 0 2006.285.12:28:43.23#ibcon#read 6, iclass 16, count 0 2006.285.12:28:43.23#ibcon#end of sib2, iclass 16, count 0 2006.285.12:28:43.23#ibcon#*mode == 0, iclass 16, count 0 2006.285.12:28:43.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.12:28:43.23#ibcon#[27=USB\r\n] 2006.285.12:28:43.23#ibcon#*before write, iclass 16, count 0 2006.285.12:28:43.23#ibcon#enter sib2, iclass 16, count 0 2006.285.12:28:43.23#ibcon#flushed, iclass 16, count 0 2006.285.12:28:43.23#ibcon#about to write, iclass 16, count 0 2006.285.12:28:43.23#ibcon#wrote, iclass 16, count 0 2006.285.12:28:43.23#ibcon#about to read 3, iclass 16, count 0 2006.285.12:28:43.26#ibcon#read 3, iclass 16, count 0 2006.285.12:28:43.26#ibcon#about to read 4, iclass 16, count 0 2006.285.12:28:43.26#ibcon#read 4, iclass 16, count 0 2006.285.12:28:43.26#ibcon#about to read 5, iclass 16, count 0 2006.285.12:28:43.26#ibcon#read 5, iclass 16, count 0 2006.285.12:28:43.26#ibcon#about to read 6, iclass 16, count 0 2006.285.12:28:43.26#ibcon#read 6, iclass 16, count 0 2006.285.12:28:43.26#ibcon#end of sib2, iclass 16, count 0 2006.285.12:28:43.26#ibcon#*after write, iclass 16, count 0 2006.285.12:28:43.26#ibcon#*before return 0, iclass 16, count 0 2006.285.12:28:43.26#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:28:43.26#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:28:43.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.12:28:43.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.12:28:43.26$vck44/vblo=7,734.99 2006.285.12:28:43.26#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.12:28:43.26#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.12:28:43.26#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:43.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:28:43.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:28:43.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:28:43.26#ibcon#enter wrdev, iclass 18, count 0 2006.285.12:28:43.26#ibcon#first serial, iclass 18, count 0 2006.285.12:28:43.26#ibcon#enter sib2, iclass 18, count 0 2006.285.12:28:43.26#ibcon#flushed, iclass 18, count 0 2006.285.12:28:43.26#ibcon#about to write, iclass 18, count 0 2006.285.12:28:43.26#ibcon#wrote, iclass 18, count 0 2006.285.12:28:43.26#ibcon#about to read 3, iclass 18, count 0 2006.285.12:28:43.28#ibcon#read 3, iclass 18, count 0 2006.285.12:28:43.28#ibcon#about to read 4, iclass 18, count 0 2006.285.12:28:43.28#ibcon#read 4, iclass 18, count 0 2006.285.12:28:43.28#ibcon#about to read 5, iclass 18, count 0 2006.285.12:28:43.28#ibcon#read 5, iclass 18, count 0 2006.285.12:28:43.28#ibcon#about to read 6, iclass 18, count 0 2006.285.12:28:43.28#ibcon#read 6, iclass 18, count 0 2006.285.12:28:43.28#ibcon#end of sib2, iclass 18, count 0 2006.285.12:28:43.28#ibcon#*mode == 0, iclass 18, count 0 2006.285.12:28:43.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.12:28:43.28#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.12:28:43.28#ibcon#*before write, iclass 18, count 0 2006.285.12:28:43.28#ibcon#enter sib2, iclass 18, count 0 2006.285.12:28:43.28#ibcon#flushed, iclass 18, count 0 2006.285.12:28:43.28#ibcon#about to write, iclass 18, count 0 2006.285.12:28:43.28#ibcon#wrote, iclass 18, count 0 2006.285.12:28:43.28#ibcon#about to read 3, iclass 18, count 0 2006.285.12:28:43.32#ibcon#read 3, iclass 18, count 0 2006.285.12:28:43.32#ibcon#about to read 4, iclass 18, count 0 2006.285.12:28:43.32#ibcon#read 4, iclass 18, count 0 2006.285.12:28:43.32#ibcon#about to read 5, iclass 18, count 0 2006.285.12:28:43.32#ibcon#read 5, iclass 18, count 0 2006.285.12:28:43.32#ibcon#about to read 6, iclass 18, count 0 2006.285.12:28:43.32#ibcon#read 6, iclass 18, count 0 2006.285.12:28:43.32#ibcon#end of sib2, iclass 18, count 0 2006.285.12:28:43.32#ibcon#*after write, iclass 18, count 0 2006.285.12:28:43.32#ibcon#*before return 0, iclass 18, count 0 2006.285.12:28:43.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:28:43.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:28:43.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.12:28:43.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.12:28:43.32$vck44/vb=7,4 2006.285.12:28:43.32#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.12:28:43.32#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.12:28:43.32#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:43.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:28:43.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:28:43.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:28:43.38#ibcon#enter wrdev, iclass 20, count 2 2006.285.12:28:43.38#ibcon#first serial, iclass 20, count 2 2006.285.12:28:43.38#ibcon#enter sib2, iclass 20, count 2 2006.285.12:28:43.38#ibcon#flushed, iclass 20, count 2 2006.285.12:28:43.38#ibcon#about to write, iclass 20, count 2 2006.285.12:28:43.38#ibcon#wrote, iclass 20, count 2 2006.285.12:28:43.38#ibcon#about to read 3, iclass 20, count 2 2006.285.12:28:43.40#ibcon#read 3, iclass 20, count 2 2006.285.12:28:43.40#ibcon#about to read 4, iclass 20, count 2 2006.285.12:28:43.40#ibcon#read 4, iclass 20, count 2 2006.285.12:28:43.40#ibcon#about to read 5, iclass 20, count 2 2006.285.12:28:43.40#ibcon#read 5, iclass 20, count 2 2006.285.12:28:43.40#ibcon#about to read 6, iclass 20, count 2 2006.285.12:28:43.40#ibcon#read 6, iclass 20, count 2 2006.285.12:28:43.40#ibcon#end of sib2, iclass 20, count 2 2006.285.12:28:43.40#ibcon#*mode == 0, iclass 20, count 2 2006.285.12:28:43.40#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.12:28:43.40#ibcon#[27=AT07-04\r\n] 2006.285.12:28:43.40#ibcon#*before write, iclass 20, count 2 2006.285.12:28:43.40#ibcon#enter sib2, iclass 20, count 2 2006.285.12:28:43.40#ibcon#flushed, iclass 20, count 2 2006.285.12:28:43.40#ibcon#about to write, iclass 20, count 2 2006.285.12:28:43.40#ibcon#wrote, iclass 20, count 2 2006.285.12:28:43.40#ibcon#about to read 3, iclass 20, count 2 2006.285.12:28:43.43#ibcon#read 3, iclass 20, count 2 2006.285.12:28:43.43#ibcon#about to read 4, iclass 20, count 2 2006.285.12:28:43.43#ibcon#read 4, iclass 20, count 2 2006.285.12:28:43.43#ibcon#about to read 5, iclass 20, count 2 2006.285.12:28:43.43#ibcon#read 5, iclass 20, count 2 2006.285.12:28:43.43#ibcon#about to read 6, iclass 20, count 2 2006.285.12:28:43.43#ibcon#read 6, iclass 20, count 2 2006.285.12:28:43.43#ibcon#end of sib2, iclass 20, count 2 2006.285.12:28:43.43#ibcon#*after write, iclass 20, count 2 2006.285.12:28:43.43#ibcon#*before return 0, iclass 20, count 2 2006.285.12:28:43.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:28:43.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:28:43.43#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.12:28:43.43#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:43.43#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:28:43.55#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:28:43.55#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:28:43.55#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:28:43.55#ibcon#first serial, iclass 20, count 0 2006.285.12:28:43.55#ibcon#enter sib2, iclass 20, count 0 2006.285.12:28:43.55#ibcon#flushed, iclass 20, count 0 2006.285.12:28:43.55#ibcon#about to write, iclass 20, count 0 2006.285.12:28:43.55#ibcon#wrote, iclass 20, count 0 2006.285.12:28:43.55#ibcon#about to read 3, iclass 20, count 0 2006.285.12:28:43.57#ibcon#read 3, iclass 20, count 0 2006.285.12:28:43.57#ibcon#about to read 4, iclass 20, count 0 2006.285.12:28:43.57#ibcon#read 4, iclass 20, count 0 2006.285.12:28:43.57#ibcon#about to read 5, iclass 20, count 0 2006.285.12:28:43.57#ibcon#read 5, iclass 20, count 0 2006.285.12:28:43.57#ibcon#about to read 6, iclass 20, count 0 2006.285.12:28:43.57#ibcon#read 6, iclass 20, count 0 2006.285.12:28:43.57#ibcon#end of sib2, iclass 20, count 0 2006.285.12:28:43.57#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:28:43.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:28:43.57#ibcon#[27=USB\r\n] 2006.285.12:28:43.57#ibcon#*before write, iclass 20, count 0 2006.285.12:28:43.57#ibcon#enter sib2, iclass 20, count 0 2006.285.12:28:43.57#ibcon#flushed, iclass 20, count 0 2006.285.12:28:43.57#ibcon#about to write, iclass 20, count 0 2006.285.12:28:43.57#ibcon#wrote, iclass 20, count 0 2006.285.12:28:43.57#ibcon#about to read 3, iclass 20, count 0 2006.285.12:28:43.60#ibcon#read 3, iclass 20, count 0 2006.285.12:28:43.60#ibcon#about to read 4, iclass 20, count 0 2006.285.12:28:43.60#ibcon#read 4, iclass 20, count 0 2006.285.12:28:43.60#ibcon#about to read 5, iclass 20, count 0 2006.285.12:28:43.60#ibcon#read 5, iclass 20, count 0 2006.285.12:28:43.60#ibcon#about to read 6, iclass 20, count 0 2006.285.12:28:43.60#ibcon#read 6, iclass 20, count 0 2006.285.12:28:43.60#ibcon#end of sib2, iclass 20, count 0 2006.285.12:28:43.60#ibcon#*after write, iclass 20, count 0 2006.285.12:28:43.60#ibcon#*before return 0, iclass 20, count 0 2006.285.12:28:43.60#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:28:43.60#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:28:43.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:28:43.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:28:43.60$vck44/vblo=8,744.99 2006.285.12:28:43.60#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.12:28:43.60#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.12:28:43.60#ibcon#ireg 17 cls_cnt 0 2006.285.12:28:43.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:28:43.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:28:43.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:28:43.60#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:28:43.60#ibcon#first serial, iclass 22, count 0 2006.285.12:28:43.60#ibcon#enter sib2, iclass 22, count 0 2006.285.12:28:43.60#ibcon#flushed, iclass 22, count 0 2006.285.12:28:43.60#ibcon#about to write, iclass 22, count 0 2006.285.12:28:43.60#ibcon#wrote, iclass 22, count 0 2006.285.12:28:43.60#ibcon#about to read 3, iclass 22, count 0 2006.285.12:28:43.62#ibcon#read 3, iclass 22, count 0 2006.285.12:28:43.62#ibcon#about to read 4, iclass 22, count 0 2006.285.12:28:43.62#ibcon#read 4, iclass 22, count 0 2006.285.12:28:43.62#ibcon#about to read 5, iclass 22, count 0 2006.285.12:28:43.62#ibcon#read 5, iclass 22, count 0 2006.285.12:28:43.62#ibcon#about to read 6, iclass 22, count 0 2006.285.12:28:43.62#ibcon#read 6, iclass 22, count 0 2006.285.12:28:43.62#ibcon#end of sib2, iclass 22, count 0 2006.285.12:28:43.62#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:28:43.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:28:43.62#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.12:28:43.62#ibcon#*before write, iclass 22, count 0 2006.285.12:28:43.62#ibcon#enter sib2, iclass 22, count 0 2006.285.12:28:43.62#ibcon#flushed, iclass 22, count 0 2006.285.12:28:43.62#ibcon#about to write, iclass 22, count 0 2006.285.12:28:43.62#ibcon#wrote, iclass 22, count 0 2006.285.12:28:43.62#ibcon#about to read 3, iclass 22, count 0 2006.285.12:28:43.66#ibcon#read 3, iclass 22, count 0 2006.285.12:28:43.66#ibcon#about to read 4, iclass 22, count 0 2006.285.12:28:43.66#ibcon#read 4, iclass 22, count 0 2006.285.12:28:43.66#ibcon#about to read 5, iclass 22, count 0 2006.285.12:28:43.66#ibcon#read 5, iclass 22, count 0 2006.285.12:28:43.66#ibcon#about to read 6, iclass 22, count 0 2006.285.12:28:43.66#ibcon#read 6, iclass 22, count 0 2006.285.12:28:43.66#ibcon#end of sib2, iclass 22, count 0 2006.285.12:28:43.66#ibcon#*after write, iclass 22, count 0 2006.285.12:28:43.66#ibcon#*before return 0, iclass 22, count 0 2006.285.12:28:43.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:28:43.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:28:43.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:28:43.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:28:43.66$vck44/vb=8,4 2006.285.12:28:43.66#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.12:28:43.66#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.12:28:43.66#ibcon#ireg 11 cls_cnt 2 2006.285.12:28:43.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:28:43.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:28:43.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:28:43.72#ibcon#enter wrdev, iclass 24, count 2 2006.285.12:28:43.72#ibcon#first serial, iclass 24, count 2 2006.285.12:28:43.72#ibcon#enter sib2, iclass 24, count 2 2006.285.12:28:43.72#ibcon#flushed, iclass 24, count 2 2006.285.12:28:43.72#ibcon#about to write, iclass 24, count 2 2006.285.12:28:43.72#ibcon#wrote, iclass 24, count 2 2006.285.12:28:43.72#ibcon#about to read 3, iclass 24, count 2 2006.285.12:28:43.74#ibcon#read 3, iclass 24, count 2 2006.285.12:28:43.74#ibcon#about to read 4, iclass 24, count 2 2006.285.12:28:43.74#ibcon#read 4, iclass 24, count 2 2006.285.12:28:43.74#ibcon#about to read 5, iclass 24, count 2 2006.285.12:28:43.74#ibcon#read 5, iclass 24, count 2 2006.285.12:28:43.74#ibcon#about to read 6, iclass 24, count 2 2006.285.12:28:43.74#ibcon#read 6, iclass 24, count 2 2006.285.12:28:43.74#ibcon#end of sib2, iclass 24, count 2 2006.285.12:28:43.74#ibcon#*mode == 0, iclass 24, count 2 2006.285.12:28:43.74#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.12:28:43.74#ibcon#[27=AT08-04\r\n] 2006.285.12:28:43.74#ibcon#*before write, iclass 24, count 2 2006.285.12:28:43.74#ibcon#enter sib2, iclass 24, count 2 2006.285.12:28:43.74#ibcon#flushed, iclass 24, count 2 2006.285.12:28:43.74#ibcon#about to write, iclass 24, count 2 2006.285.12:28:43.74#ibcon#wrote, iclass 24, count 2 2006.285.12:28:43.74#ibcon#about to read 3, iclass 24, count 2 2006.285.12:28:43.77#ibcon#read 3, iclass 24, count 2 2006.285.12:28:43.77#ibcon#about to read 4, iclass 24, count 2 2006.285.12:28:43.77#ibcon#read 4, iclass 24, count 2 2006.285.12:28:43.77#ibcon#about to read 5, iclass 24, count 2 2006.285.12:28:43.77#ibcon#read 5, iclass 24, count 2 2006.285.12:28:43.77#ibcon#about to read 6, iclass 24, count 2 2006.285.12:28:43.77#ibcon#read 6, iclass 24, count 2 2006.285.12:28:43.77#ibcon#end of sib2, iclass 24, count 2 2006.285.12:28:43.77#ibcon#*after write, iclass 24, count 2 2006.285.12:28:43.77#ibcon#*before return 0, iclass 24, count 2 2006.285.12:28:43.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:28:43.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:28:43.77#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.12:28:43.77#ibcon#ireg 7 cls_cnt 0 2006.285.12:28:43.77#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:28:43.89#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:28:43.89#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:28:43.89#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:28:43.89#ibcon#first serial, iclass 24, count 0 2006.285.12:28:43.89#ibcon#enter sib2, iclass 24, count 0 2006.285.12:28:43.89#ibcon#flushed, iclass 24, count 0 2006.285.12:28:43.89#ibcon#about to write, iclass 24, count 0 2006.285.12:28:43.89#ibcon#wrote, iclass 24, count 0 2006.285.12:28:43.89#ibcon#about to read 3, iclass 24, count 0 2006.285.12:28:43.91#ibcon#read 3, iclass 24, count 0 2006.285.12:28:43.91#ibcon#about to read 4, iclass 24, count 0 2006.285.12:28:43.91#ibcon#read 4, iclass 24, count 0 2006.285.12:28:43.91#ibcon#about to read 5, iclass 24, count 0 2006.285.12:28:43.91#ibcon#read 5, iclass 24, count 0 2006.285.12:28:43.91#ibcon#about to read 6, iclass 24, count 0 2006.285.12:28:43.91#ibcon#read 6, iclass 24, count 0 2006.285.12:28:43.91#ibcon#end of sib2, iclass 24, count 0 2006.285.12:28:43.91#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:28:43.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:28:43.91#ibcon#[27=USB\r\n] 2006.285.12:28:43.91#ibcon#*before write, iclass 24, count 0 2006.285.12:28:43.91#ibcon#enter sib2, iclass 24, count 0 2006.285.12:28:43.91#ibcon#flushed, iclass 24, count 0 2006.285.12:28:43.91#ibcon#about to write, iclass 24, count 0 2006.285.12:28:43.91#ibcon#wrote, iclass 24, count 0 2006.285.12:28:43.91#ibcon#about to read 3, iclass 24, count 0 2006.285.12:28:43.94#ibcon#read 3, iclass 24, count 0 2006.285.12:28:43.94#ibcon#about to read 4, iclass 24, count 0 2006.285.12:28:43.94#ibcon#read 4, iclass 24, count 0 2006.285.12:28:43.94#ibcon#about to read 5, iclass 24, count 0 2006.285.12:28:43.94#ibcon#read 5, iclass 24, count 0 2006.285.12:28:43.94#ibcon#about to read 6, iclass 24, count 0 2006.285.12:28:43.94#ibcon#read 6, iclass 24, count 0 2006.285.12:28:43.94#ibcon#end of sib2, iclass 24, count 0 2006.285.12:28:43.94#ibcon#*after write, iclass 24, count 0 2006.285.12:28:43.94#ibcon#*before return 0, iclass 24, count 0 2006.285.12:28:43.94#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:28:43.94#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:28:43.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:28:43.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:28:43.94$vck44/vabw=wide 2006.285.12:28:43.94#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.12:28:43.94#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.12:28:43.94#ibcon#ireg 8 cls_cnt 0 2006.285.12:28:43.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:28:43.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:28:43.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:28:43.94#ibcon#enter wrdev, iclass 26, count 0 2006.285.12:28:43.94#ibcon#first serial, iclass 26, count 0 2006.285.12:28:43.94#ibcon#enter sib2, iclass 26, count 0 2006.285.12:28:43.94#ibcon#flushed, iclass 26, count 0 2006.285.12:28:43.94#ibcon#about to write, iclass 26, count 0 2006.285.12:28:43.94#ibcon#wrote, iclass 26, count 0 2006.285.12:28:43.94#ibcon#about to read 3, iclass 26, count 0 2006.285.12:28:43.96#ibcon#read 3, iclass 26, count 0 2006.285.12:28:43.96#ibcon#about to read 4, iclass 26, count 0 2006.285.12:28:43.96#ibcon#read 4, iclass 26, count 0 2006.285.12:28:43.96#ibcon#about to read 5, iclass 26, count 0 2006.285.12:28:43.96#ibcon#read 5, iclass 26, count 0 2006.285.12:28:43.96#ibcon#about to read 6, iclass 26, count 0 2006.285.12:28:43.96#ibcon#read 6, iclass 26, count 0 2006.285.12:28:43.96#ibcon#end of sib2, iclass 26, count 0 2006.285.12:28:43.96#ibcon#*mode == 0, iclass 26, count 0 2006.285.12:28:43.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.12:28:43.96#ibcon#[25=BW32\r\n] 2006.285.12:28:43.96#ibcon#*before write, iclass 26, count 0 2006.285.12:28:43.96#ibcon#enter sib2, iclass 26, count 0 2006.285.12:28:43.96#ibcon#flushed, iclass 26, count 0 2006.285.12:28:43.96#ibcon#about to write, iclass 26, count 0 2006.285.12:28:43.96#ibcon#wrote, iclass 26, count 0 2006.285.12:28:43.96#ibcon#about to read 3, iclass 26, count 0 2006.285.12:28:43.99#ibcon#read 3, iclass 26, count 0 2006.285.12:28:43.99#ibcon#about to read 4, iclass 26, count 0 2006.285.12:28:43.99#ibcon#read 4, iclass 26, count 0 2006.285.12:28:43.99#ibcon#about to read 5, iclass 26, count 0 2006.285.12:28:43.99#ibcon#read 5, iclass 26, count 0 2006.285.12:28:43.99#ibcon#about to read 6, iclass 26, count 0 2006.285.12:28:43.99#ibcon#read 6, iclass 26, count 0 2006.285.12:28:43.99#ibcon#end of sib2, iclass 26, count 0 2006.285.12:28:43.99#ibcon#*after write, iclass 26, count 0 2006.285.12:28:43.99#ibcon#*before return 0, iclass 26, count 0 2006.285.12:28:43.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:28:43.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:28:43.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.12:28:43.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.12:28:43.99$vck44/vbbw=wide 2006.285.12:28:43.99#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.12:28:43.99#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.12:28:43.99#ibcon#ireg 8 cls_cnt 0 2006.285.12:28:43.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:28:44.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:28:44.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:28:44.06#ibcon#enter wrdev, iclass 28, count 0 2006.285.12:28:44.06#ibcon#first serial, iclass 28, count 0 2006.285.12:28:44.06#ibcon#enter sib2, iclass 28, count 0 2006.285.12:28:44.06#ibcon#flushed, iclass 28, count 0 2006.285.12:28:44.06#ibcon#about to write, iclass 28, count 0 2006.285.12:28:44.06#ibcon#wrote, iclass 28, count 0 2006.285.12:28:44.06#ibcon#about to read 3, iclass 28, count 0 2006.285.12:28:44.08#ibcon#read 3, iclass 28, count 0 2006.285.12:28:44.08#ibcon#about to read 4, iclass 28, count 0 2006.285.12:28:44.08#ibcon#read 4, iclass 28, count 0 2006.285.12:28:44.08#ibcon#about to read 5, iclass 28, count 0 2006.285.12:28:44.08#ibcon#read 5, iclass 28, count 0 2006.285.12:28:44.08#ibcon#about to read 6, iclass 28, count 0 2006.285.12:28:44.08#ibcon#read 6, iclass 28, count 0 2006.285.12:28:44.08#ibcon#end of sib2, iclass 28, count 0 2006.285.12:28:44.08#ibcon#*mode == 0, iclass 28, count 0 2006.285.12:28:44.08#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.12:28:44.08#ibcon#[27=BW32\r\n] 2006.285.12:28:44.08#ibcon#*before write, iclass 28, count 0 2006.285.12:28:44.08#ibcon#enter sib2, iclass 28, count 0 2006.285.12:28:44.08#ibcon#flushed, iclass 28, count 0 2006.285.12:28:44.08#ibcon#about to write, iclass 28, count 0 2006.285.12:28:44.08#ibcon#wrote, iclass 28, count 0 2006.285.12:28:44.08#ibcon#about to read 3, iclass 28, count 0 2006.285.12:28:44.11#ibcon#read 3, iclass 28, count 0 2006.285.12:28:44.11#ibcon#about to read 4, iclass 28, count 0 2006.285.12:28:44.11#ibcon#read 4, iclass 28, count 0 2006.285.12:28:44.11#ibcon#about to read 5, iclass 28, count 0 2006.285.12:28:44.11#ibcon#read 5, iclass 28, count 0 2006.285.12:28:44.11#ibcon#about to read 6, iclass 28, count 0 2006.285.12:28:44.11#ibcon#read 6, iclass 28, count 0 2006.285.12:28:44.11#ibcon#end of sib2, iclass 28, count 0 2006.285.12:28:44.11#ibcon#*after write, iclass 28, count 0 2006.285.12:28:44.11#ibcon#*before return 0, iclass 28, count 0 2006.285.12:28:44.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:28:44.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:28:44.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.12:28:44.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.12:28:44.11$setupk4/ifdk4 2006.285.12:28:44.11$ifdk4/lo= 2006.285.12:28:44.11$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.12:28:44.11$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.12:28:44.11$ifdk4/patch= 2006.285.12:28:44.11$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.12:28:44.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.12:28:44.12$setupk4/!*+20s 2006.285.12:28:52.68#abcon#<5=/05 1.2 2.2 18.77 961015.5\r\n> 2006.285.12:28:52.70#abcon#{5=INTERFACE CLEAR} 2006.285.12:28:52.76#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:28:57.13#trakl#Source acquired 2006.285.12:28:58.13#flagr#flagr/antenna,acquired 2006.285.12:28:58.63$setupk4/"tpicd 2006.285.12:28:58.63$setupk4/echo=off 2006.285.12:28:58.63$setupk4/xlog=off 2006.285.12:28:58.63:!2006.285.12:29:55 2006.285.12:29:55.00:preob 2006.285.12:29:56.13/onsource/TRACKING 2006.285.12:29:56.13:!2006.285.12:30:05 2006.285.12:30:05.00:"tape 2006.285.12:30:05.00:"st=record 2006.285.12:30:05.00:data_valid=on 2006.285.12:30:05.00:midob 2006.285.12:30:05.13/onsource/TRACKING 2006.285.12:30:05.13/wx/18.77,1015.5,96 2006.285.12:30:05.26/cable/+6.4937E-03 2006.285.12:30:06.35/va/01,07,usb,yes,39,42 2006.285.12:30:06.35/va/02,06,usb,yes,39,39 2006.285.12:30:06.35/va/03,07,usb,yes,38,40 2006.285.12:30:06.35/va/04,06,usb,yes,40,42 2006.285.12:30:06.35/va/05,03,usb,yes,40,40 2006.285.12:30:06.35/va/06,04,usb,yes,36,35 2006.285.12:30:06.35/va/07,04,usb,yes,37,37 2006.285.12:30:06.35/va/08,03,usb,yes,38,45 2006.285.12:30:06.58/valo/01,524.99,yes,locked 2006.285.12:30:06.58/valo/02,534.99,yes,locked 2006.285.12:30:06.58/valo/03,564.99,yes,locked 2006.285.12:30:06.58/valo/04,624.99,yes,locked 2006.285.12:30:06.58/valo/05,734.99,yes,locked 2006.285.12:30:06.58/valo/06,814.99,yes,locked 2006.285.12:30:06.58/valo/07,864.99,yes,locked 2006.285.12:30:06.58/valo/08,884.99,yes,locked 2006.285.12:30:07.67/vb/01,04,usb,yes,33,31 2006.285.12:30:07.67/vb/02,05,usb,yes,32,31 2006.285.12:30:07.67/vb/03,04,usb,yes,33,36 2006.285.12:30:07.67/vb/04,05,usb,yes,33,32 2006.285.12:30:07.67/vb/05,04,usb,yes,29,32 2006.285.12:30:07.67/vb/06,03,usb,yes,42,37 2006.285.12:30:07.67/vb/07,04,usb,yes,34,34 2006.285.12:30:07.67/vb/08,04,usb,yes,31,35 2006.285.12:30:07.90/vblo/01,629.99,yes,locked 2006.285.12:30:07.90/vblo/02,634.99,yes,locked 2006.285.12:30:07.90/vblo/03,649.99,yes,locked 2006.285.12:30:07.90/vblo/04,679.99,yes,locked 2006.285.12:30:07.90/vblo/05,709.99,yes,locked 2006.285.12:30:07.90/vblo/06,719.99,yes,locked 2006.285.12:30:07.90/vblo/07,734.99,yes,locked 2006.285.12:30:07.90/vblo/08,744.99,yes,locked 2006.285.12:30:08.05/vabw/8 2006.285.12:30:08.20/vbbw/8 2006.285.12:30:08.29/xfe/off,on,12.2 2006.285.12:30:08.66/ifatt/23,28,28,28 2006.285.12:30:09.07/fmout-gps/S +2.55E-07 2006.285.12:30:09.09:!2006.285.12:30:45 2006.285.12:30:45.00:data_valid=off 2006.285.12:30:45.00:"et 2006.285.12:30:45.00:!+3s 2006.285.12:30:48.01:"tape 2006.285.12:30:48.01:postob 2006.285.12:30:48.10/cable/+6.4961E-03 2006.285.12:30:48.10/wx/18.77,1015.5,96 2006.285.12:30:49.07/fmout-gps/S +2.53E-07 2006.285.12:30:49.07:scan_name=285-1236,jd0610,70 2006.285.12:30:49.07:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.285.12:30:50.14#flagr#flagr/antenna,new-source 2006.285.12:30:50.14:checkk5 2006.285.12:30:50.74/chk_autoobs//k5ts1/ autoobs is running! 2006.285.12:30:51.08/chk_autoobs//k5ts2/ autoobs is running! 2006.285.12:30:51.44/chk_autoobs//k5ts3/ autoobs is running! 2006.285.12:30:51.79/chk_autoobs//k5ts4/ autoobs is running! 2006.285.12:30:52.18/chk_obsdata//k5ts1/T2851230??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.12:30:52.59/chk_obsdata//k5ts2/T2851230??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.12:30:52.95/chk_obsdata//k5ts3/T2851230??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.12:30:53.30/chk_obsdata//k5ts4/T2851230??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.12:30:54.15/k5log//k5ts1_log_newline 2006.285.12:30:55.62/k5log//k5ts2_log_newline 2006.285.12:30:56.44/k5log//k5ts3_log_newline 2006.285.12:30:57.20/k5log//k5ts4_log_newline 2006.285.12:30:57.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.12:30:57.23:setupk4=1 2006.285.12:30:57.23$setupk4/echo=on 2006.285.12:30:57.23$setupk4/pcalon 2006.285.12:30:57.23$pcalon/"no phase cal control is implemented here 2006.285.12:30:57.23$setupk4/"tpicd=stop 2006.285.12:30:57.23$setupk4/"rec=synch_on 2006.285.12:30:57.23$setupk4/"rec_mode=128 2006.285.12:30:57.23$setupk4/!* 2006.285.12:30:57.23$setupk4/recpk4 2006.285.12:30:57.23$recpk4/recpatch= 2006.285.12:30:57.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.12:30:57.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.12:30:57.23$setupk4/vck44 2006.285.12:30:57.23$vck44/valo=1,524.99 2006.285.12:30:57.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.12:30:57.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.12:30:57.23#ibcon#ireg 17 cls_cnt 0 2006.285.12:30:57.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:30:57.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:30:57.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:30:57.23#ibcon#enter wrdev, iclass 13, count 0 2006.285.12:30:57.23#ibcon#first serial, iclass 13, count 0 2006.285.12:30:57.23#ibcon#enter sib2, iclass 13, count 0 2006.285.12:30:57.23#ibcon#flushed, iclass 13, count 0 2006.285.12:30:57.23#ibcon#about to write, iclass 13, count 0 2006.285.12:30:57.23#ibcon#wrote, iclass 13, count 0 2006.285.12:30:57.23#ibcon#about to read 3, iclass 13, count 0 2006.285.12:30:57.24#ibcon#read 3, iclass 13, count 0 2006.285.12:30:57.24#ibcon#about to read 4, iclass 13, count 0 2006.285.12:30:57.24#ibcon#read 4, iclass 13, count 0 2006.285.12:30:57.24#ibcon#about to read 5, iclass 13, count 0 2006.285.12:30:57.24#ibcon#read 5, iclass 13, count 0 2006.285.12:30:57.24#ibcon#about to read 6, iclass 13, count 0 2006.285.12:30:57.24#ibcon#read 6, iclass 13, count 0 2006.285.12:30:57.24#ibcon#end of sib2, iclass 13, count 0 2006.285.12:30:57.24#ibcon#*mode == 0, iclass 13, count 0 2006.285.12:30:57.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.12:30:57.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.12:30:57.24#ibcon#*before write, iclass 13, count 0 2006.285.12:30:57.24#ibcon#enter sib2, iclass 13, count 0 2006.285.12:30:57.24#ibcon#flushed, iclass 13, count 0 2006.285.12:30:57.24#ibcon#about to write, iclass 13, count 0 2006.285.12:30:57.24#ibcon#wrote, iclass 13, count 0 2006.285.12:30:57.24#ibcon#about to read 3, iclass 13, count 0 2006.285.12:30:57.29#ibcon#read 3, iclass 13, count 0 2006.285.12:30:57.29#ibcon#about to read 4, iclass 13, count 0 2006.285.12:30:57.29#ibcon#read 4, iclass 13, count 0 2006.285.12:30:57.29#ibcon#about to read 5, iclass 13, count 0 2006.285.12:30:57.29#ibcon#read 5, iclass 13, count 0 2006.285.12:30:57.29#ibcon#about to read 6, iclass 13, count 0 2006.285.12:30:57.29#ibcon#read 6, iclass 13, count 0 2006.285.12:30:57.29#ibcon#end of sib2, iclass 13, count 0 2006.285.12:30:57.29#ibcon#*after write, iclass 13, count 0 2006.285.12:30:57.29#ibcon#*before return 0, iclass 13, count 0 2006.285.12:30:57.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:30:57.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:30:57.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.12:30:57.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.12:30:57.29$vck44/va=1,7 2006.285.12:30:57.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.12:30:57.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.12:30:57.29#ibcon#ireg 11 cls_cnt 2 2006.285.12:30:57.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:30:57.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:30:57.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:30:57.29#ibcon#enter wrdev, iclass 15, count 2 2006.285.12:30:57.29#ibcon#first serial, iclass 15, count 2 2006.285.12:30:57.29#ibcon#enter sib2, iclass 15, count 2 2006.285.12:30:57.29#ibcon#flushed, iclass 15, count 2 2006.285.12:30:57.29#ibcon#about to write, iclass 15, count 2 2006.285.12:30:57.29#ibcon#wrote, iclass 15, count 2 2006.285.12:30:57.29#ibcon#about to read 3, iclass 15, count 2 2006.285.12:30:57.31#ibcon#read 3, iclass 15, count 2 2006.285.12:30:57.31#ibcon#about to read 4, iclass 15, count 2 2006.285.12:30:57.31#ibcon#read 4, iclass 15, count 2 2006.285.12:30:57.31#ibcon#about to read 5, iclass 15, count 2 2006.285.12:30:57.31#ibcon#read 5, iclass 15, count 2 2006.285.12:30:57.31#ibcon#about to read 6, iclass 15, count 2 2006.285.12:30:57.31#ibcon#read 6, iclass 15, count 2 2006.285.12:30:57.31#ibcon#end of sib2, iclass 15, count 2 2006.285.12:30:57.31#ibcon#*mode == 0, iclass 15, count 2 2006.285.12:30:57.31#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.12:30:57.31#ibcon#[25=AT01-07\r\n] 2006.285.12:30:57.31#ibcon#*before write, iclass 15, count 2 2006.285.12:30:57.31#ibcon#enter sib2, iclass 15, count 2 2006.285.12:30:57.31#ibcon#flushed, iclass 15, count 2 2006.285.12:30:57.31#ibcon#about to write, iclass 15, count 2 2006.285.12:30:57.31#ibcon#wrote, iclass 15, count 2 2006.285.12:30:57.31#ibcon#about to read 3, iclass 15, count 2 2006.285.12:30:57.34#ibcon#read 3, iclass 15, count 2 2006.285.12:30:57.34#ibcon#about to read 4, iclass 15, count 2 2006.285.12:30:57.34#ibcon#read 4, iclass 15, count 2 2006.285.12:30:57.34#ibcon#about to read 5, iclass 15, count 2 2006.285.12:30:57.34#ibcon#read 5, iclass 15, count 2 2006.285.12:30:57.34#ibcon#about to read 6, iclass 15, count 2 2006.285.12:30:57.34#ibcon#read 6, iclass 15, count 2 2006.285.12:30:57.34#ibcon#end of sib2, iclass 15, count 2 2006.285.12:30:57.34#ibcon#*after write, iclass 15, count 2 2006.285.12:30:57.34#ibcon#*before return 0, iclass 15, count 2 2006.285.12:30:57.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:30:57.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:30:57.34#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.12:30:57.34#ibcon#ireg 7 cls_cnt 0 2006.285.12:30:57.34#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:30:57.46#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:30:57.46#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:30:57.46#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:30:57.46#ibcon#first serial, iclass 15, count 0 2006.285.12:30:57.46#ibcon#enter sib2, iclass 15, count 0 2006.285.12:30:57.46#ibcon#flushed, iclass 15, count 0 2006.285.12:30:57.46#ibcon#about to write, iclass 15, count 0 2006.285.12:30:57.46#ibcon#wrote, iclass 15, count 0 2006.285.12:30:57.46#ibcon#about to read 3, iclass 15, count 0 2006.285.12:30:57.48#ibcon#read 3, iclass 15, count 0 2006.285.12:30:57.48#ibcon#about to read 4, iclass 15, count 0 2006.285.12:30:57.48#ibcon#read 4, iclass 15, count 0 2006.285.12:30:57.48#ibcon#about to read 5, iclass 15, count 0 2006.285.12:30:57.48#ibcon#read 5, iclass 15, count 0 2006.285.12:30:57.48#ibcon#about to read 6, iclass 15, count 0 2006.285.12:30:57.48#ibcon#read 6, iclass 15, count 0 2006.285.12:30:57.48#ibcon#end of sib2, iclass 15, count 0 2006.285.12:30:57.48#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:30:57.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:30:57.48#ibcon#[25=USB\r\n] 2006.285.12:30:57.48#ibcon#*before write, iclass 15, count 0 2006.285.12:30:57.48#ibcon#enter sib2, iclass 15, count 0 2006.285.12:30:57.48#ibcon#flushed, iclass 15, count 0 2006.285.12:30:57.48#ibcon#about to write, iclass 15, count 0 2006.285.12:30:57.48#ibcon#wrote, iclass 15, count 0 2006.285.12:30:57.48#ibcon#about to read 3, iclass 15, count 0 2006.285.12:30:57.51#ibcon#read 3, iclass 15, count 0 2006.285.12:30:57.51#ibcon#about to read 4, iclass 15, count 0 2006.285.12:30:57.51#ibcon#read 4, iclass 15, count 0 2006.285.12:30:57.51#ibcon#about to read 5, iclass 15, count 0 2006.285.12:30:57.51#ibcon#read 5, iclass 15, count 0 2006.285.12:30:57.51#ibcon#about to read 6, iclass 15, count 0 2006.285.12:30:57.51#ibcon#read 6, iclass 15, count 0 2006.285.12:30:57.51#ibcon#end of sib2, iclass 15, count 0 2006.285.12:30:57.51#ibcon#*after write, iclass 15, count 0 2006.285.12:30:57.51#ibcon#*before return 0, iclass 15, count 0 2006.285.12:30:57.51#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:30:57.51#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:30:57.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:30:57.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:30:57.51$vck44/valo=2,534.99 2006.285.12:30:57.51#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.12:30:57.51#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.12:30:57.51#ibcon#ireg 17 cls_cnt 0 2006.285.12:30:57.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:30:57.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:30:57.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:30:57.51#ibcon#enter wrdev, iclass 17, count 0 2006.285.12:30:57.51#ibcon#first serial, iclass 17, count 0 2006.285.12:30:57.51#ibcon#enter sib2, iclass 17, count 0 2006.285.12:30:57.51#ibcon#flushed, iclass 17, count 0 2006.285.12:30:57.51#ibcon#about to write, iclass 17, count 0 2006.285.12:30:57.51#ibcon#wrote, iclass 17, count 0 2006.285.12:30:57.51#ibcon#about to read 3, iclass 17, count 0 2006.285.12:30:57.53#ibcon#read 3, iclass 17, count 0 2006.285.12:30:57.53#ibcon#about to read 4, iclass 17, count 0 2006.285.12:30:57.53#ibcon#read 4, iclass 17, count 0 2006.285.12:30:57.53#ibcon#about to read 5, iclass 17, count 0 2006.285.12:30:57.53#ibcon#read 5, iclass 17, count 0 2006.285.12:30:57.53#ibcon#about to read 6, iclass 17, count 0 2006.285.12:30:57.53#ibcon#read 6, iclass 17, count 0 2006.285.12:30:57.53#ibcon#end of sib2, iclass 17, count 0 2006.285.12:30:57.53#ibcon#*mode == 0, iclass 17, count 0 2006.285.12:30:57.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.12:30:57.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.12:30:57.53#ibcon#*before write, iclass 17, count 0 2006.285.12:30:57.53#ibcon#enter sib2, iclass 17, count 0 2006.285.12:30:57.53#ibcon#flushed, iclass 17, count 0 2006.285.12:30:57.53#ibcon#about to write, iclass 17, count 0 2006.285.12:30:57.53#ibcon#wrote, iclass 17, count 0 2006.285.12:30:57.53#ibcon#about to read 3, iclass 17, count 0 2006.285.12:30:57.57#ibcon#read 3, iclass 17, count 0 2006.285.12:30:57.57#ibcon#about to read 4, iclass 17, count 0 2006.285.12:30:57.57#ibcon#read 4, iclass 17, count 0 2006.285.12:30:57.57#ibcon#about to read 5, iclass 17, count 0 2006.285.12:30:57.57#ibcon#read 5, iclass 17, count 0 2006.285.12:30:57.57#ibcon#about to read 6, iclass 17, count 0 2006.285.12:30:57.57#ibcon#read 6, iclass 17, count 0 2006.285.12:30:57.57#ibcon#end of sib2, iclass 17, count 0 2006.285.12:30:57.57#ibcon#*after write, iclass 17, count 0 2006.285.12:30:57.57#ibcon#*before return 0, iclass 17, count 0 2006.285.12:30:57.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:30:57.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:30:57.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.12:30:57.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.12:30:57.57$vck44/va=2,6 2006.285.12:30:57.57#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.12:30:57.57#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.12:30:57.57#ibcon#ireg 11 cls_cnt 2 2006.285.12:30:57.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:30:57.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:30:57.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:30:57.63#ibcon#enter wrdev, iclass 19, count 2 2006.285.12:30:57.63#ibcon#first serial, iclass 19, count 2 2006.285.12:30:57.63#ibcon#enter sib2, iclass 19, count 2 2006.285.12:30:57.63#ibcon#flushed, iclass 19, count 2 2006.285.12:30:57.63#ibcon#about to write, iclass 19, count 2 2006.285.12:30:57.63#ibcon#wrote, iclass 19, count 2 2006.285.12:30:57.63#ibcon#about to read 3, iclass 19, count 2 2006.285.12:30:57.65#ibcon#read 3, iclass 19, count 2 2006.285.12:30:57.65#ibcon#about to read 4, iclass 19, count 2 2006.285.12:30:57.65#ibcon#read 4, iclass 19, count 2 2006.285.12:30:57.65#ibcon#about to read 5, iclass 19, count 2 2006.285.12:30:57.65#ibcon#read 5, iclass 19, count 2 2006.285.12:30:57.65#ibcon#about to read 6, iclass 19, count 2 2006.285.12:30:57.65#ibcon#read 6, iclass 19, count 2 2006.285.12:30:57.65#ibcon#end of sib2, iclass 19, count 2 2006.285.12:30:57.65#ibcon#*mode == 0, iclass 19, count 2 2006.285.12:30:57.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.12:30:57.65#ibcon#[25=AT02-06\r\n] 2006.285.12:30:57.65#ibcon#*before write, iclass 19, count 2 2006.285.12:30:57.65#ibcon#enter sib2, iclass 19, count 2 2006.285.12:30:57.65#ibcon#flushed, iclass 19, count 2 2006.285.12:30:57.65#ibcon#about to write, iclass 19, count 2 2006.285.12:30:57.65#ibcon#wrote, iclass 19, count 2 2006.285.12:30:57.65#ibcon#about to read 3, iclass 19, count 2 2006.285.12:30:57.68#ibcon#read 3, iclass 19, count 2 2006.285.12:30:57.68#ibcon#about to read 4, iclass 19, count 2 2006.285.12:30:57.68#ibcon#read 4, iclass 19, count 2 2006.285.12:30:57.68#ibcon#about to read 5, iclass 19, count 2 2006.285.12:30:57.68#ibcon#read 5, iclass 19, count 2 2006.285.12:30:57.68#ibcon#about to read 6, iclass 19, count 2 2006.285.12:30:57.68#ibcon#read 6, iclass 19, count 2 2006.285.12:30:57.68#ibcon#end of sib2, iclass 19, count 2 2006.285.12:30:57.68#ibcon#*after write, iclass 19, count 2 2006.285.12:30:57.68#ibcon#*before return 0, iclass 19, count 2 2006.285.12:30:57.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:30:57.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:30:57.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.12:30:57.68#ibcon#ireg 7 cls_cnt 0 2006.285.12:30:57.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:30:57.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:30:57.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:30:57.80#ibcon#enter wrdev, iclass 19, count 0 2006.285.12:30:57.80#ibcon#first serial, iclass 19, count 0 2006.285.12:30:57.80#ibcon#enter sib2, iclass 19, count 0 2006.285.12:30:57.80#ibcon#flushed, iclass 19, count 0 2006.285.12:30:57.80#ibcon#about to write, iclass 19, count 0 2006.285.12:30:57.80#ibcon#wrote, iclass 19, count 0 2006.285.12:30:57.80#ibcon#about to read 3, iclass 19, count 0 2006.285.12:30:57.82#ibcon#read 3, iclass 19, count 0 2006.285.12:30:57.82#ibcon#about to read 4, iclass 19, count 0 2006.285.12:30:57.82#ibcon#read 4, iclass 19, count 0 2006.285.12:30:57.82#ibcon#about to read 5, iclass 19, count 0 2006.285.12:30:57.82#ibcon#read 5, iclass 19, count 0 2006.285.12:30:57.82#ibcon#about to read 6, iclass 19, count 0 2006.285.12:30:57.82#ibcon#read 6, iclass 19, count 0 2006.285.12:30:57.82#ibcon#end of sib2, iclass 19, count 0 2006.285.12:30:57.82#ibcon#*mode == 0, iclass 19, count 0 2006.285.12:30:57.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.12:30:57.82#ibcon#[25=USB\r\n] 2006.285.12:30:57.82#ibcon#*before write, iclass 19, count 0 2006.285.12:30:57.82#ibcon#enter sib2, iclass 19, count 0 2006.285.12:30:57.82#ibcon#flushed, iclass 19, count 0 2006.285.12:30:57.82#ibcon#about to write, iclass 19, count 0 2006.285.12:30:57.82#ibcon#wrote, iclass 19, count 0 2006.285.12:30:57.82#ibcon#about to read 3, iclass 19, count 0 2006.285.12:30:57.85#ibcon#read 3, iclass 19, count 0 2006.285.12:30:57.85#ibcon#about to read 4, iclass 19, count 0 2006.285.12:30:57.85#ibcon#read 4, iclass 19, count 0 2006.285.12:30:57.85#ibcon#about to read 5, iclass 19, count 0 2006.285.12:30:57.85#ibcon#read 5, iclass 19, count 0 2006.285.12:30:57.85#ibcon#about to read 6, iclass 19, count 0 2006.285.12:30:57.85#ibcon#read 6, iclass 19, count 0 2006.285.12:30:57.85#ibcon#end of sib2, iclass 19, count 0 2006.285.12:30:57.85#ibcon#*after write, iclass 19, count 0 2006.285.12:30:57.85#ibcon#*before return 0, iclass 19, count 0 2006.285.12:30:57.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:30:57.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:30:57.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.12:30:57.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.12:30:57.85$vck44/valo=3,564.99 2006.285.12:30:57.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.12:30:57.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.12:30:57.85#ibcon#ireg 17 cls_cnt 0 2006.285.12:30:57.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:30:57.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:30:57.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:30:57.85#ibcon#enter wrdev, iclass 21, count 0 2006.285.12:30:57.85#ibcon#first serial, iclass 21, count 0 2006.285.12:30:57.85#ibcon#enter sib2, iclass 21, count 0 2006.285.12:30:57.85#ibcon#flushed, iclass 21, count 0 2006.285.12:30:57.85#ibcon#about to write, iclass 21, count 0 2006.285.12:30:57.85#ibcon#wrote, iclass 21, count 0 2006.285.12:30:57.85#ibcon#about to read 3, iclass 21, count 0 2006.285.12:30:57.87#ibcon#read 3, iclass 21, count 0 2006.285.12:30:57.87#ibcon#about to read 4, iclass 21, count 0 2006.285.12:30:57.87#ibcon#read 4, iclass 21, count 0 2006.285.12:30:57.87#ibcon#about to read 5, iclass 21, count 0 2006.285.12:30:57.87#ibcon#read 5, iclass 21, count 0 2006.285.12:30:57.87#ibcon#about to read 6, iclass 21, count 0 2006.285.12:30:57.87#ibcon#read 6, iclass 21, count 0 2006.285.12:30:57.87#ibcon#end of sib2, iclass 21, count 0 2006.285.12:30:57.87#ibcon#*mode == 0, iclass 21, count 0 2006.285.12:30:57.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.12:30:57.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.12:30:57.87#ibcon#*before write, iclass 21, count 0 2006.285.12:30:57.87#ibcon#enter sib2, iclass 21, count 0 2006.285.12:30:57.87#ibcon#flushed, iclass 21, count 0 2006.285.12:30:57.87#ibcon#about to write, iclass 21, count 0 2006.285.12:30:57.87#ibcon#wrote, iclass 21, count 0 2006.285.12:30:57.87#ibcon#about to read 3, iclass 21, count 0 2006.285.12:30:57.91#ibcon#read 3, iclass 21, count 0 2006.285.12:30:57.91#ibcon#about to read 4, iclass 21, count 0 2006.285.12:30:57.91#ibcon#read 4, iclass 21, count 0 2006.285.12:30:57.91#ibcon#about to read 5, iclass 21, count 0 2006.285.12:30:57.91#ibcon#read 5, iclass 21, count 0 2006.285.12:30:57.91#ibcon#about to read 6, iclass 21, count 0 2006.285.12:30:57.91#ibcon#read 6, iclass 21, count 0 2006.285.12:30:57.91#ibcon#end of sib2, iclass 21, count 0 2006.285.12:30:57.91#ibcon#*after write, iclass 21, count 0 2006.285.12:30:57.91#ibcon#*before return 0, iclass 21, count 0 2006.285.12:30:57.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:30:57.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:30:57.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.12:30:57.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.12:30:57.91$vck44/va=3,7 2006.285.12:30:57.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.12:30:57.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.12:30:57.91#ibcon#ireg 11 cls_cnt 2 2006.285.12:30:57.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:30:57.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:30:57.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:30:57.97#ibcon#enter wrdev, iclass 23, count 2 2006.285.12:30:57.97#ibcon#first serial, iclass 23, count 2 2006.285.12:30:57.97#ibcon#enter sib2, iclass 23, count 2 2006.285.12:30:57.97#ibcon#flushed, iclass 23, count 2 2006.285.12:30:57.97#ibcon#about to write, iclass 23, count 2 2006.285.12:30:57.97#ibcon#wrote, iclass 23, count 2 2006.285.12:30:57.97#ibcon#about to read 3, iclass 23, count 2 2006.285.12:30:57.99#ibcon#read 3, iclass 23, count 2 2006.285.12:30:57.99#ibcon#about to read 4, iclass 23, count 2 2006.285.12:30:57.99#ibcon#read 4, iclass 23, count 2 2006.285.12:30:57.99#ibcon#about to read 5, iclass 23, count 2 2006.285.12:30:57.99#ibcon#read 5, iclass 23, count 2 2006.285.12:30:57.99#ibcon#about to read 6, iclass 23, count 2 2006.285.12:30:57.99#ibcon#read 6, iclass 23, count 2 2006.285.12:30:57.99#ibcon#end of sib2, iclass 23, count 2 2006.285.12:30:57.99#ibcon#*mode == 0, iclass 23, count 2 2006.285.12:30:57.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.12:30:57.99#ibcon#[25=AT03-07\r\n] 2006.285.12:30:57.99#ibcon#*before write, iclass 23, count 2 2006.285.12:30:57.99#ibcon#enter sib2, iclass 23, count 2 2006.285.12:30:57.99#ibcon#flushed, iclass 23, count 2 2006.285.12:30:57.99#ibcon#about to write, iclass 23, count 2 2006.285.12:30:57.99#ibcon#wrote, iclass 23, count 2 2006.285.12:30:57.99#ibcon#about to read 3, iclass 23, count 2 2006.285.12:30:58.02#ibcon#read 3, iclass 23, count 2 2006.285.12:30:58.02#ibcon#about to read 4, iclass 23, count 2 2006.285.12:30:58.02#ibcon#read 4, iclass 23, count 2 2006.285.12:30:58.02#ibcon#about to read 5, iclass 23, count 2 2006.285.12:30:58.02#ibcon#read 5, iclass 23, count 2 2006.285.12:30:58.02#ibcon#about to read 6, iclass 23, count 2 2006.285.12:30:58.02#ibcon#read 6, iclass 23, count 2 2006.285.12:30:58.02#ibcon#end of sib2, iclass 23, count 2 2006.285.12:30:58.02#ibcon#*after write, iclass 23, count 2 2006.285.12:30:58.02#ibcon#*before return 0, iclass 23, count 2 2006.285.12:30:58.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:30:58.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:30:58.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.12:30:58.02#ibcon#ireg 7 cls_cnt 0 2006.285.12:30:58.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:30:58.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:30:58.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:30:58.14#ibcon#enter wrdev, iclass 23, count 0 2006.285.12:30:58.14#ibcon#first serial, iclass 23, count 0 2006.285.12:30:58.14#ibcon#enter sib2, iclass 23, count 0 2006.285.12:30:58.14#ibcon#flushed, iclass 23, count 0 2006.285.12:30:58.14#ibcon#about to write, iclass 23, count 0 2006.285.12:30:58.14#ibcon#wrote, iclass 23, count 0 2006.285.12:30:58.14#ibcon#about to read 3, iclass 23, count 0 2006.285.12:30:58.16#ibcon#read 3, iclass 23, count 0 2006.285.12:30:58.16#ibcon#about to read 4, iclass 23, count 0 2006.285.12:30:58.16#ibcon#read 4, iclass 23, count 0 2006.285.12:30:58.16#ibcon#about to read 5, iclass 23, count 0 2006.285.12:30:58.16#ibcon#read 5, iclass 23, count 0 2006.285.12:30:58.16#ibcon#about to read 6, iclass 23, count 0 2006.285.12:30:58.16#ibcon#read 6, iclass 23, count 0 2006.285.12:30:58.16#ibcon#end of sib2, iclass 23, count 0 2006.285.12:30:58.16#ibcon#*mode == 0, iclass 23, count 0 2006.285.12:30:58.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.12:30:58.16#ibcon#[25=USB\r\n] 2006.285.12:30:58.16#ibcon#*before write, iclass 23, count 0 2006.285.12:30:58.16#ibcon#enter sib2, iclass 23, count 0 2006.285.12:30:58.16#ibcon#flushed, iclass 23, count 0 2006.285.12:30:58.16#ibcon#about to write, iclass 23, count 0 2006.285.12:30:58.16#ibcon#wrote, iclass 23, count 0 2006.285.12:30:58.16#ibcon#about to read 3, iclass 23, count 0 2006.285.12:30:58.19#ibcon#read 3, iclass 23, count 0 2006.285.12:30:58.19#ibcon#about to read 4, iclass 23, count 0 2006.285.12:30:58.19#ibcon#read 4, iclass 23, count 0 2006.285.12:30:58.19#ibcon#about to read 5, iclass 23, count 0 2006.285.12:30:58.19#ibcon#read 5, iclass 23, count 0 2006.285.12:30:58.19#ibcon#about to read 6, iclass 23, count 0 2006.285.12:30:58.19#ibcon#read 6, iclass 23, count 0 2006.285.12:30:58.19#ibcon#end of sib2, iclass 23, count 0 2006.285.12:30:58.19#ibcon#*after write, iclass 23, count 0 2006.285.12:30:58.19#ibcon#*before return 0, iclass 23, count 0 2006.285.12:30:58.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:30:58.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:30:58.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.12:30:58.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.12:30:58.19$vck44/valo=4,624.99 2006.285.12:30:58.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.12:30:58.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.12:30:58.19#ibcon#ireg 17 cls_cnt 0 2006.285.12:30:58.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:30:58.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:30:58.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:30:58.19#ibcon#enter wrdev, iclass 25, count 0 2006.285.12:30:58.19#ibcon#first serial, iclass 25, count 0 2006.285.12:30:58.19#ibcon#enter sib2, iclass 25, count 0 2006.285.12:30:58.19#ibcon#flushed, iclass 25, count 0 2006.285.12:30:58.19#ibcon#about to write, iclass 25, count 0 2006.285.12:30:58.19#ibcon#wrote, iclass 25, count 0 2006.285.12:30:58.19#ibcon#about to read 3, iclass 25, count 0 2006.285.12:30:58.21#ibcon#read 3, iclass 25, count 0 2006.285.12:30:58.21#ibcon#about to read 4, iclass 25, count 0 2006.285.12:30:58.21#ibcon#read 4, iclass 25, count 0 2006.285.12:30:58.21#ibcon#about to read 5, iclass 25, count 0 2006.285.12:30:58.21#ibcon#read 5, iclass 25, count 0 2006.285.12:30:58.21#ibcon#about to read 6, iclass 25, count 0 2006.285.12:30:58.21#ibcon#read 6, iclass 25, count 0 2006.285.12:30:58.21#ibcon#end of sib2, iclass 25, count 0 2006.285.12:30:58.21#ibcon#*mode == 0, iclass 25, count 0 2006.285.12:30:58.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.12:30:58.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.12:30:58.21#ibcon#*before write, iclass 25, count 0 2006.285.12:30:58.21#ibcon#enter sib2, iclass 25, count 0 2006.285.12:30:58.21#ibcon#flushed, iclass 25, count 0 2006.285.12:30:58.21#ibcon#about to write, iclass 25, count 0 2006.285.12:30:58.21#ibcon#wrote, iclass 25, count 0 2006.285.12:30:58.21#ibcon#about to read 3, iclass 25, count 0 2006.285.12:30:58.25#ibcon#read 3, iclass 25, count 0 2006.285.12:30:58.25#ibcon#about to read 4, iclass 25, count 0 2006.285.12:30:58.25#ibcon#read 4, iclass 25, count 0 2006.285.12:30:58.25#ibcon#about to read 5, iclass 25, count 0 2006.285.12:30:58.25#ibcon#read 5, iclass 25, count 0 2006.285.12:30:58.25#ibcon#about to read 6, iclass 25, count 0 2006.285.12:30:58.25#ibcon#read 6, iclass 25, count 0 2006.285.12:30:58.25#ibcon#end of sib2, iclass 25, count 0 2006.285.12:30:58.25#ibcon#*after write, iclass 25, count 0 2006.285.12:30:58.25#ibcon#*before return 0, iclass 25, count 0 2006.285.12:30:58.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:30:58.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:30:58.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.12:30:58.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.12:30:58.25$vck44/va=4,6 2006.285.12:30:58.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.12:30:58.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.12:30:58.25#ibcon#ireg 11 cls_cnt 2 2006.285.12:30:58.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:30:58.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:30:58.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:30:58.31#ibcon#enter wrdev, iclass 27, count 2 2006.285.12:30:58.31#ibcon#first serial, iclass 27, count 2 2006.285.12:30:58.31#ibcon#enter sib2, iclass 27, count 2 2006.285.12:30:58.31#ibcon#flushed, iclass 27, count 2 2006.285.12:30:58.31#ibcon#about to write, iclass 27, count 2 2006.285.12:30:58.31#ibcon#wrote, iclass 27, count 2 2006.285.12:30:58.31#ibcon#about to read 3, iclass 27, count 2 2006.285.12:30:58.33#ibcon#read 3, iclass 27, count 2 2006.285.12:30:58.33#ibcon#about to read 4, iclass 27, count 2 2006.285.12:30:58.33#ibcon#read 4, iclass 27, count 2 2006.285.12:30:58.33#ibcon#about to read 5, iclass 27, count 2 2006.285.12:30:58.33#ibcon#read 5, iclass 27, count 2 2006.285.12:30:58.33#ibcon#about to read 6, iclass 27, count 2 2006.285.12:30:58.33#ibcon#read 6, iclass 27, count 2 2006.285.12:30:58.33#ibcon#end of sib2, iclass 27, count 2 2006.285.12:30:58.33#ibcon#*mode == 0, iclass 27, count 2 2006.285.12:30:58.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.12:30:58.33#ibcon#[25=AT04-06\r\n] 2006.285.12:30:58.33#ibcon#*before write, iclass 27, count 2 2006.285.12:30:58.33#ibcon#enter sib2, iclass 27, count 2 2006.285.12:30:58.33#ibcon#flushed, iclass 27, count 2 2006.285.12:30:58.33#ibcon#about to write, iclass 27, count 2 2006.285.12:30:58.33#ibcon#wrote, iclass 27, count 2 2006.285.12:30:58.33#ibcon#about to read 3, iclass 27, count 2 2006.285.12:30:58.36#ibcon#read 3, iclass 27, count 2 2006.285.12:30:58.36#ibcon#about to read 4, iclass 27, count 2 2006.285.12:30:58.36#ibcon#read 4, iclass 27, count 2 2006.285.12:30:58.36#ibcon#about to read 5, iclass 27, count 2 2006.285.12:30:58.36#ibcon#read 5, iclass 27, count 2 2006.285.12:30:58.36#ibcon#about to read 6, iclass 27, count 2 2006.285.12:30:58.36#ibcon#read 6, iclass 27, count 2 2006.285.12:30:58.36#ibcon#end of sib2, iclass 27, count 2 2006.285.12:30:58.36#ibcon#*after write, iclass 27, count 2 2006.285.12:30:58.36#ibcon#*before return 0, iclass 27, count 2 2006.285.12:30:58.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:30:58.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:30:58.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.12:30:58.36#ibcon#ireg 7 cls_cnt 0 2006.285.12:30:58.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:30:58.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:30:58.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:30:58.48#ibcon#enter wrdev, iclass 27, count 0 2006.285.12:30:58.48#ibcon#first serial, iclass 27, count 0 2006.285.12:30:58.48#ibcon#enter sib2, iclass 27, count 0 2006.285.12:30:58.48#ibcon#flushed, iclass 27, count 0 2006.285.12:30:58.48#ibcon#about to write, iclass 27, count 0 2006.285.12:30:58.48#ibcon#wrote, iclass 27, count 0 2006.285.12:30:58.48#ibcon#about to read 3, iclass 27, count 0 2006.285.12:30:58.50#ibcon#read 3, iclass 27, count 0 2006.285.12:30:58.50#ibcon#about to read 4, iclass 27, count 0 2006.285.12:30:58.50#ibcon#read 4, iclass 27, count 0 2006.285.12:30:58.50#ibcon#about to read 5, iclass 27, count 0 2006.285.12:30:58.50#ibcon#read 5, iclass 27, count 0 2006.285.12:30:58.50#ibcon#about to read 6, iclass 27, count 0 2006.285.12:30:58.50#ibcon#read 6, iclass 27, count 0 2006.285.12:30:58.50#ibcon#end of sib2, iclass 27, count 0 2006.285.12:30:58.50#ibcon#*mode == 0, iclass 27, count 0 2006.285.12:30:58.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.12:30:58.50#ibcon#[25=USB\r\n] 2006.285.12:30:58.50#ibcon#*before write, iclass 27, count 0 2006.285.12:30:58.50#ibcon#enter sib2, iclass 27, count 0 2006.285.12:30:58.50#ibcon#flushed, iclass 27, count 0 2006.285.12:30:58.50#ibcon#about to write, iclass 27, count 0 2006.285.12:30:58.50#ibcon#wrote, iclass 27, count 0 2006.285.12:30:58.50#ibcon#about to read 3, iclass 27, count 0 2006.285.12:30:58.53#ibcon#read 3, iclass 27, count 0 2006.285.12:30:58.53#ibcon#about to read 4, iclass 27, count 0 2006.285.12:30:58.53#ibcon#read 4, iclass 27, count 0 2006.285.12:30:58.53#ibcon#about to read 5, iclass 27, count 0 2006.285.12:30:58.53#ibcon#read 5, iclass 27, count 0 2006.285.12:30:58.53#ibcon#about to read 6, iclass 27, count 0 2006.285.12:30:58.53#ibcon#read 6, iclass 27, count 0 2006.285.12:30:58.53#ibcon#end of sib2, iclass 27, count 0 2006.285.12:30:58.53#ibcon#*after write, iclass 27, count 0 2006.285.12:30:58.53#ibcon#*before return 0, iclass 27, count 0 2006.285.12:30:58.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:30:58.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:30:58.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.12:30:58.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.12:30:58.53$vck44/valo=5,734.99 2006.285.12:30:58.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.12:30:58.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.12:30:58.53#ibcon#ireg 17 cls_cnt 0 2006.285.12:30:58.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:30:58.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:30:58.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:30:58.53#ibcon#enter wrdev, iclass 29, count 0 2006.285.12:30:58.53#ibcon#first serial, iclass 29, count 0 2006.285.12:30:58.53#ibcon#enter sib2, iclass 29, count 0 2006.285.12:30:58.53#ibcon#flushed, iclass 29, count 0 2006.285.12:30:58.53#ibcon#about to write, iclass 29, count 0 2006.285.12:30:58.53#ibcon#wrote, iclass 29, count 0 2006.285.12:30:58.53#ibcon#about to read 3, iclass 29, count 0 2006.285.12:30:58.55#ibcon#read 3, iclass 29, count 0 2006.285.12:30:58.55#ibcon#about to read 4, iclass 29, count 0 2006.285.12:30:58.55#ibcon#read 4, iclass 29, count 0 2006.285.12:30:58.55#ibcon#about to read 5, iclass 29, count 0 2006.285.12:30:58.55#ibcon#read 5, iclass 29, count 0 2006.285.12:30:58.55#ibcon#about to read 6, iclass 29, count 0 2006.285.12:30:58.55#ibcon#read 6, iclass 29, count 0 2006.285.12:30:58.55#ibcon#end of sib2, iclass 29, count 0 2006.285.12:30:58.55#ibcon#*mode == 0, iclass 29, count 0 2006.285.12:30:58.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.12:30:58.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.12:30:58.55#ibcon#*before write, iclass 29, count 0 2006.285.12:30:58.55#ibcon#enter sib2, iclass 29, count 0 2006.285.12:30:58.55#ibcon#flushed, iclass 29, count 0 2006.285.12:30:58.55#ibcon#about to write, iclass 29, count 0 2006.285.12:30:58.55#ibcon#wrote, iclass 29, count 0 2006.285.12:30:58.55#ibcon#about to read 3, iclass 29, count 0 2006.285.12:30:58.59#ibcon#read 3, iclass 29, count 0 2006.285.12:30:58.59#ibcon#about to read 4, iclass 29, count 0 2006.285.12:30:58.59#ibcon#read 4, iclass 29, count 0 2006.285.12:30:58.59#ibcon#about to read 5, iclass 29, count 0 2006.285.12:30:58.59#ibcon#read 5, iclass 29, count 0 2006.285.12:30:58.59#ibcon#about to read 6, iclass 29, count 0 2006.285.12:30:58.59#ibcon#read 6, iclass 29, count 0 2006.285.12:30:58.59#ibcon#end of sib2, iclass 29, count 0 2006.285.12:30:58.59#ibcon#*after write, iclass 29, count 0 2006.285.12:30:58.59#ibcon#*before return 0, iclass 29, count 0 2006.285.12:30:58.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:30:58.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:30:58.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.12:30:58.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.12:30:58.59$vck44/va=5,3 2006.285.12:30:58.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.12:30:58.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.12:30:58.59#ibcon#ireg 11 cls_cnt 2 2006.285.12:30:58.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:30:58.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:30:58.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:30:58.65#ibcon#enter wrdev, iclass 31, count 2 2006.285.12:30:58.65#ibcon#first serial, iclass 31, count 2 2006.285.12:30:58.65#ibcon#enter sib2, iclass 31, count 2 2006.285.12:30:58.65#ibcon#flushed, iclass 31, count 2 2006.285.12:30:58.65#ibcon#about to write, iclass 31, count 2 2006.285.12:30:58.65#ibcon#wrote, iclass 31, count 2 2006.285.12:30:58.65#ibcon#about to read 3, iclass 31, count 2 2006.285.12:30:58.67#ibcon#read 3, iclass 31, count 2 2006.285.12:30:58.67#ibcon#about to read 4, iclass 31, count 2 2006.285.12:30:58.67#ibcon#read 4, iclass 31, count 2 2006.285.12:30:58.67#ibcon#about to read 5, iclass 31, count 2 2006.285.12:30:58.67#ibcon#read 5, iclass 31, count 2 2006.285.12:30:58.67#ibcon#about to read 6, iclass 31, count 2 2006.285.12:30:58.67#ibcon#read 6, iclass 31, count 2 2006.285.12:30:58.67#ibcon#end of sib2, iclass 31, count 2 2006.285.12:30:58.67#ibcon#*mode == 0, iclass 31, count 2 2006.285.12:30:58.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.12:30:58.67#ibcon#[25=AT05-03\r\n] 2006.285.12:30:58.67#ibcon#*before write, iclass 31, count 2 2006.285.12:30:58.67#ibcon#enter sib2, iclass 31, count 2 2006.285.12:30:58.67#ibcon#flushed, iclass 31, count 2 2006.285.12:30:58.67#ibcon#about to write, iclass 31, count 2 2006.285.12:30:58.67#ibcon#wrote, iclass 31, count 2 2006.285.12:30:58.67#ibcon#about to read 3, iclass 31, count 2 2006.285.12:30:58.70#ibcon#read 3, iclass 31, count 2 2006.285.12:30:58.70#ibcon#about to read 4, iclass 31, count 2 2006.285.12:30:58.70#ibcon#read 4, iclass 31, count 2 2006.285.12:30:58.70#ibcon#about to read 5, iclass 31, count 2 2006.285.12:30:58.70#ibcon#read 5, iclass 31, count 2 2006.285.12:30:58.70#ibcon#about to read 6, iclass 31, count 2 2006.285.12:30:58.70#ibcon#read 6, iclass 31, count 2 2006.285.12:30:58.70#ibcon#end of sib2, iclass 31, count 2 2006.285.12:30:58.70#ibcon#*after write, iclass 31, count 2 2006.285.12:30:58.70#ibcon#*before return 0, iclass 31, count 2 2006.285.12:30:58.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:30:58.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:30:58.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.12:30:58.70#ibcon#ireg 7 cls_cnt 0 2006.285.12:30:58.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:30:58.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:30:58.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:30:58.82#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:30:58.82#ibcon#first serial, iclass 31, count 0 2006.285.12:30:58.82#ibcon#enter sib2, iclass 31, count 0 2006.285.12:30:58.82#ibcon#flushed, iclass 31, count 0 2006.285.12:30:58.82#ibcon#about to write, iclass 31, count 0 2006.285.12:30:58.82#ibcon#wrote, iclass 31, count 0 2006.285.12:30:58.82#ibcon#about to read 3, iclass 31, count 0 2006.285.12:30:58.84#ibcon#read 3, iclass 31, count 0 2006.285.12:30:58.84#ibcon#about to read 4, iclass 31, count 0 2006.285.12:30:58.84#ibcon#read 4, iclass 31, count 0 2006.285.12:30:58.84#ibcon#about to read 5, iclass 31, count 0 2006.285.12:30:58.84#ibcon#read 5, iclass 31, count 0 2006.285.12:30:58.84#ibcon#about to read 6, iclass 31, count 0 2006.285.12:30:58.84#ibcon#read 6, iclass 31, count 0 2006.285.12:30:58.84#ibcon#end of sib2, iclass 31, count 0 2006.285.12:30:58.84#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:30:58.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:30:58.84#ibcon#[25=USB\r\n] 2006.285.12:30:58.84#ibcon#*before write, iclass 31, count 0 2006.285.12:30:58.84#ibcon#enter sib2, iclass 31, count 0 2006.285.12:30:58.84#ibcon#flushed, iclass 31, count 0 2006.285.12:30:58.84#ibcon#about to write, iclass 31, count 0 2006.285.12:30:58.84#ibcon#wrote, iclass 31, count 0 2006.285.12:30:58.84#ibcon#about to read 3, iclass 31, count 0 2006.285.12:30:58.87#ibcon#read 3, iclass 31, count 0 2006.285.12:30:58.87#ibcon#about to read 4, iclass 31, count 0 2006.285.12:30:58.87#ibcon#read 4, iclass 31, count 0 2006.285.12:30:58.87#ibcon#about to read 5, iclass 31, count 0 2006.285.12:30:58.87#ibcon#read 5, iclass 31, count 0 2006.285.12:30:58.87#ibcon#about to read 6, iclass 31, count 0 2006.285.12:30:58.87#ibcon#read 6, iclass 31, count 0 2006.285.12:30:58.87#ibcon#end of sib2, iclass 31, count 0 2006.285.12:30:58.87#ibcon#*after write, iclass 31, count 0 2006.285.12:30:58.87#ibcon#*before return 0, iclass 31, count 0 2006.285.12:30:58.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:30:58.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:30:58.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:30:58.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:30:58.87$vck44/valo=6,814.99 2006.285.12:30:58.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.12:30:58.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.12:30:58.87#ibcon#ireg 17 cls_cnt 0 2006.285.12:30:58.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:30:58.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:30:58.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:30:58.87#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:30:58.87#ibcon#first serial, iclass 33, count 0 2006.285.12:30:58.87#ibcon#enter sib2, iclass 33, count 0 2006.285.12:30:58.87#ibcon#flushed, iclass 33, count 0 2006.285.12:30:58.87#ibcon#about to write, iclass 33, count 0 2006.285.12:30:58.87#ibcon#wrote, iclass 33, count 0 2006.285.12:30:58.87#ibcon#about to read 3, iclass 33, count 0 2006.285.12:30:58.89#ibcon#read 3, iclass 33, count 0 2006.285.12:30:58.89#ibcon#about to read 4, iclass 33, count 0 2006.285.12:30:58.89#ibcon#read 4, iclass 33, count 0 2006.285.12:30:58.89#ibcon#about to read 5, iclass 33, count 0 2006.285.12:30:58.89#ibcon#read 5, iclass 33, count 0 2006.285.12:30:58.89#ibcon#about to read 6, iclass 33, count 0 2006.285.12:30:58.89#ibcon#read 6, iclass 33, count 0 2006.285.12:30:58.89#ibcon#end of sib2, iclass 33, count 0 2006.285.12:30:58.89#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:30:58.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:30:58.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.12:30:58.89#ibcon#*before write, iclass 33, count 0 2006.285.12:30:58.89#ibcon#enter sib2, iclass 33, count 0 2006.285.12:30:58.89#ibcon#flushed, iclass 33, count 0 2006.285.12:30:58.89#ibcon#about to write, iclass 33, count 0 2006.285.12:30:58.89#ibcon#wrote, iclass 33, count 0 2006.285.12:30:58.89#ibcon#about to read 3, iclass 33, count 0 2006.285.12:30:58.93#ibcon#read 3, iclass 33, count 0 2006.285.12:30:58.93#ibcon#about to read 4, iclass 33, count 0 2006.285.12:30:58.93#ibcon#read 4, iclass 33, count 0 2006.285.12:30:58.93#ibcon#about to read 5, iclass 33, count 0 2006.285.12:30:58.93#ibcon#read 5, iclass 33, count 0 2006.285.12:30:58.93#ibcon#about to read 6, iclass 33, count 0 2006.285.12:30:58.93#ibcon#read 6, iclass 33, count 0 2006.285.12:30:58.93#ibcon#end of sib2, iclass 33, count 0 2006.285.12:30:58.93#ibcon#*after write, iclass 33, count 0 2006.285.12:30:58.93#ibcon#*before return 0, iclass 33, count 0 2006.285.12:30:58.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:30:58.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:30:58.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:30:58.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:30:58.93$vck44/va=6,4 2006.285.12:30:58.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.12:30:58.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.12:30:58.93#ibcon#ireg 11 cls_cnt 2 2006.285.12:30:58.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:30:58.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:30:58.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:30:58.99#ibcon#enter wrdev, iclass 35, count 2 2006.285.12:30:58.99#ibcon#first serial, iclass 35, count 2 2006.285.12:30:58.99#ibcon#enter sib2, iclass 35, count 2 2006.285.12:30:58.99#ibcon#flushed, iclass 35, count 2 2006.285.12:30:58.99#ibcon#about to write, iclass 35, count 2 2006.285.12:30:58.99#ibcon#wrote, iclass 35, count 2 2006.285.12:30:58.99#ibcon#about to read 3, iclass 35, count 2 2006.285.12:30:59.01#ibcon#read 3, iclass 35, count 2 2006.285.12:30:59.01#ibcon#about to read 4, iclass 35, count 2 2006.285.12:30:59.01#ibcon#read 4, iclass 35, count 2 2006.285.12:30:59.01#ibcon#about to read 5, iclass 35, count 2 2006.285.12:30:59.01#ibcon#read 5, iclass 35, count 2 2006.285.12:30:59.01#ibcon#about to read 6, iclass 35, count 2 2006.285.12:30:59.01#ibcon#read 6, iclass 35, count 2 2006.285.12:30:59.01#ibcon#end of sib2, iclass 35, count 2 2006.285.12:30:59.01#ibcon#*mode == 0, iclass 35, count 2 2006.285.12:30:59.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.12:30:59.01#ibcon#[25=AT06-04\r\n] 2006.285.12:30:59.01#ibcon#*before write, iclass 35, count 2 2006.285.12:30:59.01#ibcon#enter sib2, iclass 35, count 2 2006.285.12:30:59.01#ibcon#flushed, iclass 35, count 2 2006.285.12:30:59.01#ibcon#about to write, iclass 35, count 2 2006.285.12:30:59.01#ibcon#wrote, iclass 35, count 2 2006.285.12:30:59.01#ibcon#about to read 3, iclass 35, count 2 2006.285.12:30:59.04#ibcon#read 3, iclass 35, count 2 2006.285.12:30:59.04#ibcon#about to read 4, iclass 35, count 2 2006.285.12:30:59.04#ibcon#read 4, iclass 35, count 2 2006.285.12:30:59.04#ibcon#about to read 5, iclass 35, count 2 2006.285.12:30:59.04#ibcon#read 5, iclass 35, count 2 2006.285.12:30:59.04#ibcon#about to read 6, iclass 35, count 2 2006.285.12:30:59.04#ibcon#read 6, iclass 35, count 2 2006.285.12:30:59.04#ibcon#end of sib2, iclass 35, count 2 2006.285.12:30:59.04#ibcon#*after write, iclass 35, count 2 2006.285.12:30:59.04#ibcon#*before return 0, iclass 35, count 2 2006.285.12:30:59.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:30:59.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:30:59.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.12:30:59.04#ibcon#ireg 7 cls_cnt 0 2006.285.12:30:59.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:30:59.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:30:59.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:30:59.16#ibcon#enter wrdev, iclass 35, count 0 2006.285.12:30:59.16#ibcon#first serial, iclass 35, count 0 2006.285.12:30:59.16#ibcon#enter sib2, iclass 35, count 0 2006.285.12:30:59.16#ibcon#flushed, iclass 35, count 0 2006.285.12:30:59.16#ibcon#about to write, iclass 35, count 0 2006.285.12:30:59.16#ibcon#wrote, iclass 35, count 0 2006.285.12:30:59.16#ibcon#about to read 3, iclass 35, count 0 2006.285.12:30:59.18#ibcon#read 3, iclass 35, count 0 2006.285.12:30:59.18#ibcon#about to read 4, iclass 35, count 0 2006.285.12:30:59.18#ibcon#read 4, iclass 35, count 0 2006.285.12:30:59.18#ibcon#about to read 5, iclass 35, count 0 2006.285.12:30:59.18#ibcon#read 5, iclass 35, count 0 2006.285.12:30:59.18#ibcon#about to read 6, iclass 35, count 0 2006.285.12:30:59.18#ibcon#read 6, iclass 35, count 0 2006.285.12:30:59.18#ibcon#end of sib2, iclass 35, count 0 2006.285.12:30:59.18#ibcon#*mode == 0, iclass 35, count 0 2006.285.12:30:59.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.12:30:59.18#ibcon#[25=USB\r\n] 2006.285.12:30:59.18#ibcon#*before write, iclass 35, count 0 2006.285.12:30:59.18#ibcon#enter sib2, iclass 35, count 0 2006.285.12:30:59.18#ibcon#flushed, iclass 35, count 0 2006.285.12:30:59.18#ibcon#about to write, iclass 35, count 0 2006.285.12:30:59.18#ibcon#wrote, iclass 35, count 0 2006.285.12:30:59.18#ibcon#about to read 3, iclass 35, count 0 2006.285.12:30:59.21#ibcon#read 3, iclass 35, count 0 2006.285.12:30:59.21#ibcon#about to read 4, iclass 35, count 0 2006.285.12:30:59.21#ibcon#read 4, iclass 35, count 0 2006.285.12:30:59.21#ibcon#about to read 5, iclass 35, count 0 2006.285.12:30:59.21#ibcon#read 5, iclass 35, count 0 2006.285.12:30:59.21#ibcon#about to read 6, iclass 35, count 0 2006.285.12:30:59.21#ibcon#read 6, iclass 35, count 0 2006.285.12:30:59.21#ibcon#end of sib2, iclass 35, count 0 2006.285.12:30:59.21#ibcon#*after write, iclass 35, count 0 2006.285.12:30:59.21#ibcon#*before return 0, iclass 35, count 0 2006.285.12:30:59.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:30:59.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:30:59.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.12:30:59.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.12:30:59.21$vck44/valo=7,864.99 2006.285.12:30:59.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.12:30:59.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.12:30:59.21#ibcon#ireg 17 cls_cnt 0 2006.285.12:30:59.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:30:59.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:30:59.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:30:59.21#ibcon#enter wrdev, iclass 37, count 0 2006.285.12:30:59.21#ibcon#first serial, iclass 37, count 0 2006.285.12:30:59.21#ibcon#enter sib2, iclass 37, count 0 2006.285.12:30:59.21#ibcon#flushed, iclass 37, count 0 2006.285.12:30:59.21#ibcon#about to write, iclass 37, count 0 2006.285.12:30:59.21#ibcon#wrote, iclass 37, count 0 2006.285.12:30:59.21#ibcon#about to read 3, iclass 37, count 0 2006.285.12:30:59.23#ibcon#read 3, iclass 37, count 0 2006.285.12:30:59.23#ibcon#about to read 4, iclass 37, count 0 2006.285.12:30:59.23#ibcon#read 4, iclass 37, count 0 2006.285.12:30:59.23#ibcon#about to read 5, iclass 37, count 0 2006.285.12:30:59.23#ibcon#read 5, iclass 37, count 0 2006.285.12:30:59.23#ibcon#about to read 6, iclass 37, count 0 2006.285.12:30:59.23#ibcon#read 6, iclass 37, count 0 2006.285.12:30:59.23#ibcon#end of sib2, iclass 37, count 0 2006.285.12:30:59.23#ibcon#*mode == 0, iclass 37, count 0 2006.285.12:30:59.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.12:30:59.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.12:30:59.23#ibcon#*before write, iclass 37, count 0 2006.285.12:30:59.23#ibcon#enter sib2, iclass 37, count 0 2006.285.12:30:59.23#ibcon#flushed, iclass 37, count 0 2006.285.12:30:59.23#ibcon#about to write, iclass 37, count 0 2006.285.12:30:59.23#ibcon#wrote, iclass 37, count 0 2006.285.12:30:59.23#ibcon#about to read 3, iclass 37, count 0 2006.285.12:30:59.27#ibcon#read 3, iclass 37, count 0 2006.285.12:30:59.27#ibcon#about to read 4, iclass 37, count 0 2006.285.12:30:59.27#ibcon#read 4, iclass 37, count 0 2006.285.12:30:59.27#ibcon#about to read 5, iclass 37, count 0 2006.285.12:30:59.27#ibcon#read 5, iclass 37, count 0 2006.285.12:30:59.27#ibcon#about to read 6, iclass 37, count 0 2006.285.12:30:59.27#ibcon#read 6, iclass 37, count 0 2006.285.12:30:59.27#ibcon#end of sib2, iclass 37, count 0 2006.285.12:30:59.27#ibcon#*after write, iclass 37, count 0 2006.285.12:30:59.27#ibcon#*before return 0, iclass 37, count 0 2006.285.12:30:59.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:30:59.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:30:59.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.12:30:59.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.12:30:59.27$vck44/va=7,4 2006.285.12:30:59.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.12:30:59.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.12:30:59.27#ibcon#ireg 11 cls_cnt 2 2006.285.12:30:59.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:30:59.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:30:59.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:30:59.33#ibcon#enter wrdev, iclass 39, count 2 2006.285.12:30:59.33#ibcon#first serial, iclass 39, count 2 2006.285.12:30:59.33#ibcon#enter sib2, iclass 39, count 2 2006.285.12:30:59.33#ibcon#flushed, iclass 39, count 2 2006.285.12:30:59.33#ibcon#about to write, iclass 39, count 2 2006.285.12:30:59.33#ibcon#wrote, iclass 39, count 2 2006.285.12:30:59.33#ibcon#about to read 3, iclass 39, count 2 2006.285.12:30:59.35#ibcon#read 3, iclass 39, count 2 2006.285.12:30:59.35#ibcon#about to read 4, iclass 39, count 2 2006.285.12:30:59.35#ibcon#read 4, iclass 39, count 2 2006.285.12:30:59.35#ibcon#about to read 5, iclass 39, count 2 2006.285.12:30:59.35#ibcon#read 5, iclass 39, count 2 2006.285.12:30:59.35#ibcon#about to read 6, iclass 39, count 2 2006.285.12:30:59.35#ibcon#read 6, iclass 39, count 2 2006.285.12:30:59.35#ibcon#end of sib2, iclass 39, count 2 2006.285.12:30:59.35#ibcon#*mode == 0, iclass 39, count 2 2006.285.12:30:59.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.12:30:59.35#ibcon#[25=AT07-04\r\n] 2006.285.12:30:59.35#ibcon#*before write, iclass 39, count 2 2006.285.12:30:59.35#ibcon#enter sib2, iclass 39, count 2 2006.285.12:30:59.35#ibcon#flushed, iclass 39, count 2 2006.285.12:30:59.35#ibcon#about to write, iclass 39, count 2 2006.285.12:30:59.35#ibcon#wrote, iclass 39, count 2 2006.285.12:30:59.35#ibcon#about to read 3, iclass 39, count 2 2006.285.12:30:59.38#ibcon#read 3, iclass 39, count 2 2006.285.12:30:59.38#ibcon#about to read 4, iclass 39, count 2 2006.285.12:30:59.38#ibcon#read 4, iclass 39, count 2 2006.285.12:30:59.38#ibcon#about to read 5, iclass 39, count 2 2006.285.12:30:59.38#ibcon#read 5, iclass 39, count 2 2006.285.12:30:59.38#ibcon#about to read 6, iclass 39, count 2 2006.285.12:30:59.38#ibcon#read 6, iclass 39, count 2 2006.285.12:30:59.38#ibcon#end of sib2, iclass 39, count 2 2006.285.12:30:59.38#ibcon#*after write, iclass 39, count 2 2006.285.12:30:59.38#ibcon#*before return 0, iclass 39, count 2 2006.285.12:30:59.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:30:59.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:30:59.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.12:30:59.38#ibcon#ireg 7 cls_cnt 0 2006.285.12:30:59.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:30:59.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:30:59.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:30:59.50#ibcon#enter wrdev, iclass 39, count 0 2006.285.12:30:59.50#ibcon#first serial, iclass 39, count 0 2006.285.12:30:59.50#ibcon#enter sib2, iclass 39, count 0 2006.285.12:30:59.50#ibcon#flushed, iclass 39, count 0 2006.285.12:30:59.50#ibcon#about to write, iclass 39, count 0 2006.285.12:30:59.50#ibcon#wrote, iclass 39, count 0 2006.285.12:30:59.50#ibcon#about to read 3, iclass 39, count 0 2006.285.12:30:59.52#ibcon#read 3, iclass 39, count 0 2006.285.12:30:59.52#ibcon#about to read 4, iclass 39, count 0 2006.285.12:30:59.52#ibcon#read 4, iclass 39, count 0 2006.285.12:30:59.52#ibcon#about to read 5, iclass 39, count 0 2006.285.12:30:59.52#ibcon#read 5, iclass 39, count 0 2006.285.12:30:59.52#ibcon#about to read 6, iclass 39, count 0 2006.285.12:30:59.52#ibcon#read 6, iclass 39, count 0 2006.285.12:30:59.52#ibcon#end of sib2, iclass 39, count 0 2006.285.12:30:59.52#ibcon#*mode == 0, iclass 39, count 0 2006.285.12:30:59.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.12:30:59.52#ibcon#[25=USB\r\n] 2006.285.12:30:59.52#ibcon#*before write, iclass 39, count 0 2006.285.12:30:59.52#ibcon#enter sib2, iclass 39, count 0 2006.285.12:30:59.52#ibcon#flushed, iclass 39, count 0 2006.285.12:30:59.52#ibcon#about to write, iclass 39, count 0 2006.285.12:30:59.52#ibcon#wrote, iclass 39, count 0 2006.285.12:30:59.52#ibcon#about to read 3, iclass 39, count 0 2006.285.12:30:59.55#ibcon#read 3, iclass 39, count 0 2006.285.12:30:59.55#ibcon#about to read 4, iclass 39, count 0 2006.285.12:30:59.55#ibcon#read 4, iclass 39, count 0 2006.285.12:30:59.55#ibcon#about to read 5, iclass 39, count 0 2006.285.12:30:59.55#ibcon#read 5, iclass 39, count 0 2006.285.12:30:59.55#ibcon#about to read 6, iclass 39, count 0 2006.285.12:30:59.55#ibcon#read 6, iclass 39, count 0 2006.285.12:30:59.55#ibcon#end of sib2, iclass 39, count 0 2006.285.12:30:59.55#ibcon#*after write, iclass 39, count 0 2006.285.12:30:59.55#ibcon#*before return 0, iclass 39, count 0 2006.285.12:30:59.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:30:59.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:30:59.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.12:30:59.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.12:30:59.55$vck44/valo=8,884.99 2006.285.12:30:59.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.12:30:59.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.12:30:59.55#ibcon#ireg 17 cls_cnt 0 2006.285.12:30:59.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:30:59.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:30:59.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:30:59.55#ibcon#enter wrdev, iclass 3, count 0 2006.285.12:30:59.55#ibcon#first serial, iclass 3, count 0 2006.285.12:30:59.55#ibcon#enter sib2, iclass 3, count 0 2006.285.12:30:59.55#ibcon#flushed, iclass 3, count 0 2006.285.12:30:59.55#ibcon#about to write, iclass 3, count 0 2006.285.12:30:59.55#ibcon#wrote, iclass 3, count 0 2006.285.12:30:59.55#ibcon#about to read 3, iclass 3, count 0 2006.285.12:30:59.57#ibcon#read 3, iclass 3, count 0 2006.285.12:30:59.57#ibcon#about to read 4, iclass 3, count 0 2006.285.12:30:59.57#ibcon#read 4, iclass 3, count 0 2006.285.12:30:59.57#ibcon#about to read 5, iclass 3, count 0 2006.285.12:30:59.57#ibcon#read 5, iclass 3, count 0 2006.285.12:30:59.57#ibcon#about to read 6, iclass 3, count 0 2006.285.12:30:59.57#ibcon#read 6, iclass 3, count 0 2006.285.12:30:59.57#ibcon#end of sib2, iclass 3, count 0 2006.285.12:30:59.57#ibcon#*mode == 0, iclass 3, count 0 2006.285.12:30:59.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.12:30:59.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.12:30:59.57#ibcon#*before write, iclass 3, count 0 2006.285.12:30:59.57#ibcon#enter sib2, iclass 3, count 0 2006.285.12:30:59.57#ibcon#flushed, iclass 3, count 0 2006.285.12:30:59.57#ibcon#about to write, iclass 3, count 0 2006.285.12:30:59.57#ibcon#wrote, iclass 3, count 0 2006.285.12:30:59.57#ibcon#about to read 3, iclass 3, count 0 2006.285.12:30:59.61#ibcon#read 3, iclass 3, count 0 2006.285.12:30:59.61#ibcon#about to read 4, iclass 3, count 0 2006.285.12:30:59.61#ibcon#read 4, iclass 3, count 0 2006.285.12:30:59.61#ibcon#about to read 5, iclass 3, count 0 2006.285.12:30:59.61#ibcon#read 5, iclass 3, count 0 2006.285.12:30:59.61#ibcon#about to read 6, iclass 3, count 0 2006.285.12:30:59.61#ibcon#read 6, iclass 3, count 0 2006.285.12:30:59.61#ibcon#end of sib2, iclass 3, count 0 2006.285.12:30:59.61#ibcon#*after write, iclass 3, count 0 2006.285.12:30:59.61#ibcon#*before return 0, iclass 3, count 0 2006.285.12:30:59.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:30:59.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:30:59.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.12:30:59.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.12:30:59.61$vck44/va=8,3 2006.285.12:30:59.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.12:30:59.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.12:30:59.61#ibcon#ireg 11 cls_cnt 2 2006.285.12:30:59.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:30:59.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:30:59.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:30:59.67#ibcon#enter wrdev, iclass 5, count 2 2006.285.12:30:59.67#ibcon#first serial, iclass 5, count 2 2006.285.12:30:59.67#ibcon#enter sib2, iclass 5, count 2 2006.285.12:30:59.67#ibcon#flushed, iclass 5, count 2 2006.285.12:30:59.67#ibcon#about to write, iclass 5, count 2 2006.285.12:30:59.67#ibcon#wrote, iclass 5, count 2 2006.285.12:30:59.67#ibcon#about to read 3, iclass 5, count 2 2006.285.12:30:59.69#ibcon#read 3, iclass 5, count 2 2006.285.12:30:59.69#ibcon#about to read 4, iclass 5, count 2 2006.285.12:30:59.69#ibcon#read 4, iclass 5, count 2 2006.285.12:30:59.69#ibcon#about to read 5, iclass 5, count 2 2006.285.12:30:59.69#ibcon#read 5, iclass 5, count 2 2006.285.12:30:59.69#ibcon#about to read 6, iclass 5, count 2 2006.285.12:30:59.69#ibcon#read 6, iclass 5, count 2 2006.285.12:30:59.69#ibcon#end of sib2, iclass 5, count 2 2006.285.12:30:59.69#ibcon#*mode == 0, iclass 5, count 2 2006.285.12:30:59.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.12:30:59.69#ibcon#[25=AT08-03\r\n] 2006.285.12:30:59.69#ibcon#*before write, iclass 5, count 2 2006.285.12:30:59.69#ibcon#enter sib2, iclass 5, count 2 2006.285.12:30:59.69#ibcon#flushed, iclass 5, count 2 2006.285.12:30:59.69#ibcon#about to write, iclass 5, count 2 2006.285.12:30:59.69#ibcon#wrote, iclass 5, count 2 2006.285.12:30:59.69#ibcon#about to read 3, iclass 5, count 2 2006.285.12:30:59.72#ibcon#read 3, iclass 5, count 2 2006.285.12:30:59.72#ibcon#about to read 4, iclass 5, count 2 2006.285.12:30:59.72#ibcon#read 4, iclass 5, count 2 2006.285.12:30:59.72#ibcon#about to read 5, iclass 5, count 2 2006.285.12:30:59.72#ibcon#read 5, iclass 5, count 2 2006.285.12:30:59.72#ibcon#about to read 6, iclass 5, count 2 2006.285.12:30:59.72#ibcon#read 6, iclass 5, count 2 2006.285.12:30:59.72#ibcon#end of sib2, iclass 5, count 2 2006.285.12:30:59.72#ibcon#*after write, iclass 5, count 2 2006.285.12:30:59.72#ibcon#*before return 0, iclass 5, count 2 2006.285.12:30:59.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:30:59.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:30:59.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.12:30:59.72#ibcon#ireg 7 cls_cnt 0 2006.285.12:30:59.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:30:59.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:30:59.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:30:59.84#ibcon#enter wrdev, iclass 5, count 0 2006.285.12:30:59.84#ibcon#first serial, iclass 5, count 0 2006.285.12:30:59.84#ibcon#enter sib2, iclass 5, count 0 2006.285.12:30:59.84#ibcon#flushed, iclass 5, count 0 2006.285.12:30:59.84#ibcon#about to write, iclass 5, count 0 2006.285.12:30:59.84#ibcon#wrote, iclass 5, count 0 2006.285.12:30:59.84#ibcon#about to read 3, iclass 5, count 0 2006.285.12:30:59.86#ibcon#read 3, iclass 5, count 0 2006.285.12:30:59.86#ibcon#about to read 4, iclass 5, count 0 2006.285.12:30:59.86#ibcon#read 4, iclass 5, count 0 2006.285.12:30:59.86#ibcon#about to read 5, iclass 5, count 0 2006.285.12:30:59.86#ibcon#read 5, iclass 5, count 0 2006.285.12:30:59.86#ibcon#about to read 6, iclass 5, count 0 2006.285.12:30:59.86#ibcon#read 6, iclass 5, count 0 2006.285.12:30:59.86#ibcon#end of sib2, iclass 5, count 0 2006.285.12:30:59.86#ibcon#*mode == 0, iclass 5, count 0 2006.285.12:30:59.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.12:30:59.86#ibcon#[25=USB\r\n] 2006.285.12:30:59.86#ibcon#*before write, iclass 5, count 0 2006.285.12:30:59.86#ibcon#enter sib2, iclass 5, count 0 2006.285.12:30:59.86#ibcon#flushed, iclass 5, count 0 2006.285.12:30:59.86#ibcon#about to write, iclass 5, count 0 2006.285.12:30:59.86#ibcon#wrote, iclass 5, count 0 2006.285.12:30:59.86#ibcon#about to read 3, iclass 5, count 0 2006.285.12:30:59.89#ibcon#read 3, iclass 5, count 0 2006.285.12:30:59.89#ibcon#about to read 4, iclass 5, count 0 2006.285.12:30:59.89#ibcon#read 4, iclass 5, count 0 2006.285.12:30:59.89#ibcon#about to read 5, iclass 5, count 0 2006.285.12:30:59.89#ibcon#read 5, iclass 5, count 0 2006.285.12:30:59.89#ibcon#about to read 6, iclass 5, count 0 2006.285.12:30:59.89#ibcon#read 6, iclass 5, count 0 2006.285.12:30:59.89#ibcon#end of sib2, iclass 5, count 0 2006.285.12:30:59.89#ibcon#*after write, iclass 5, count 0 2006.285.12:30:59.89#ibcon#*before return 0, iclass 5, count 0 2006.285.12:30:59.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:30:59.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:30:59.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.12:30:59.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.12:30:59.89$vck44/vblo=1,629.99 2006.285.12:30:59.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.12:30:59.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.12:30:59.89#ibcon#ireg 17 cls_cnt 0 2006.285.12:30:59.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:30:59.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:30:59.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:30:59.89#ibcon#enter wrdev, iclass 7, count 0 2006.285.12:30:59.89#ibcon#first serial, iclass 7, count 0 2006.285.12:30:59.89#ibcon#enter sib2, iclass 7, count 0 2006.285.12:30:59.89#ibcon#flushed, iclass 7, count 0 2006.285.12:30:59.89#ibcon#about to write, iclass 7, count 0 2006.285.12:30:59.89#ibcon#wrote, iclass 7, count 0 2006.285.12:30:59.89#ibcon#about to read 3, iclass 7, count 0 2006.285.12:30:59.91#ibcon#read 3, iclass 7, count 0 2006.285.12:30:59.91#ibcon#about to read 4, iclass 7, count 0 2006.285.12:30:59.91#ibcon#read 4, iclass 7, count 0 2006.285.12:30:59.91#ibcon#about to read 5, iclass 7, count 0 2006.285.12:30:59.91#ibcon#read 5, iclass 7, count 0 2006.285.12:30:59.91#ibcon#about to read 6, iclass 7, count 0 2006.285.12:30:59.91#ibcon#read 6, iclass 7, count 0 2006.285.12:30:59.91#ibcon#end of sib2, iclass 7, count 0 2006.285.12:30:59.91#ibcon#*mode == 0, iclass 7, count 0 2006.285.12:30:59.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.12:30:59.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.12:30:59.91#ibcon#*before write, iclass 7, count 0 2006.285.12:30:59.91#ibcon#enter sib2, iclass 7, count 0 2006.285.12:30:59.91#ibcon#flushed, iclass 7, count 0 2006.285.12:30:59.91#ibcon#about to write, iclass 7, count 0 2006.285.12:30:59.91#ibcon#wrote, iclass 7, count 0 2006.285.12:30:59.91#ibcon#about to read 3, iclass 7, count 0 2006.285.12:30:59.95#ibcon#read 3, iclass 7, count 0 2006.285.12:30:59.95#ibcon#about to read 4, iclass 7, count 0 2006.285.12:30:59.95#ibcon#read 4, iclass 7, count 0 2006.285.12:30:59.95#ibcon#about to read 5, iclass 7, count 0 2006.285.12:30:59.95#ibcon#read 5, iclass 7, count 0 2006.285.12:30:59.95#ibcon#about to read 6, iclass 7, count 0 2006.285.12:30:59.95#ibcon#read 6, iclass 7, count 0 2006.285.12:30:59.95#ibcon#end of sib2, iclass 7, count 0 2006.285.12:30:59.95#ibcon#*after write, iclass 7, count 0 2006.285.12:30:59.95#ibcon#*before return 0, iclass 7, count 0 2006.285.12:30:59.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:30:59.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:30:59.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.12:30:59.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.12:30:59.95$vck44/vb=1,4 2006.285.12:30:59.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.12:30:59.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.12:30:59.95#ibcon#ireg 11 cls_cnt 2 2006.285.12:30:59.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:30:59.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:30:59.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:30:59.95#ibcon#enter wrdev, iclass 11, count 2 2006.285.12:30:59.95#ibcon#first serial, iclass 11, count 2 2006.285.12:30:59.95#ibcon#enter sib2, iclass 11, count 2 2006.285.12:30:59.95#ibcon#flushed, iclass 11, count 2 2006.285.12:30:59.95#ibcon#about to write, iclass 11, count 2 2006.285.12:30:59.95#ibcon#wrote, iclass 11, count 2 2006.285.12:30:59.95#ibcon#about to read 3, iclass 11, count 2 2006.285.12:30:59.97#ibcon#read 3, iclass 11, count 2 2006.285.12:30:59.97#ibcon#about to read 4, iclass 11, count 2 2006.285.12:30:59.97#ibcon#read 4, iclass 11, count 2 2006.285.12:30:59.97#ibcon#about to read 5, iclass 11, count 2 2006.285.12:30:59.97#ibcon#read 5, iclass 11, count 2 2006.285.12:30:59.97#ibcon#about to read 6, iclass 11, count 2 2006.285.12:30:59.97#ibcon#read 6, iclass 11, count 2 2006.285.12:30:59.97#ibcon#end of sib2, iclass 11, count 2 2006.285.12:30:59.97#ibcon#*mode == 0, iclass 11, count 2 2006.285.12:30:59.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.12:30:59.97#ibcon#[27=AT01-04\r\n] 2006.285.12:30:59.97#ibcon#*before write, iclass 11, count 2 2006.285.12:30:59.97#ibcon#enter sib2, iclass 11, count 2 2006.285.12:30:59.97#ibcon#flushed, iclass 11, count 2 2006.285.12:30:59.97#ibcon#about to write, iclass 11, count 2 2006.285.12:30:59.97#ibcon#wrote, iclass 11, count 2 2006.285.12:30:59.97#ibcon#about to read 3, iclass 11, count 2 2006.285.12:31:00.00#ibcon#read 3, iclass 11, count 2 2006.285.12:31:00.00#ibcon#about to read 4, iclass 11, count 2 2006.285.12:31:00.00#ibcon#read 4, iclass 11, count 2 2006.285.12:31:00.00#ibcon#about to read 5, iclass 11, count 2 2006.285.12:31:00.00#ibcon#read 5, iclass 11, count 2 2006.285.12:31:00.00#ibcon#about to read 6, iclass 11, count 2 2006.285.12:31:00.00#ibcon#read 6, iclass 11, count 2 2006.285.12:31:00.00#ibcon#end of sib2, iclass 11, count 2 2006.285.12:31:00.00#ibcon#*after write, iclass 11, count 2 2006.285.12:31:00.00#ibcon#*before return 0, iclass 11, count 2 2006.285.12:31:00.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:31:00.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:31:00.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.12:31:00.00#ibcon#ireg 7 cls_cnt 0 2006.285.12:31:00.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:31:00.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:31:00.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:31:00.12#ibcon#enter wrdev, iclass 11, count 0 2006.285.12:31:00.12#ibcon#first serial, iclass 11, count 0 2006.285.12:31:00.12#ibcon#enter sib2, iclass 11, count 0 2006.285.12:31:00.12#ibcon#flushed, iclass 11, count 0 2006.285.12:31:00.12#ibcon#about to write, iclass 11, count 0 2006.285.12:31:00.12#ibcon#wrote, iclass 11, count 0 2006.285.12:31:00.12#ibcon#about to read 3, iclass 11, count 0 2006.285.12:31:00.14#ibcon#read 3, iclass 11, count 0 2006.285.12:31:00.14#ibcon#about to read 4, iclass 11, count 0 2006.285.12:31:00.14#ibcon#read 4, iclass 11, count 0 2006.285.12:31:00.14#ibcon#about to read 5, iclass 11, count 0 2006.285.12:31:00.14#ibcon#read 5, iclass 11, count 0 2006.285.12:31:00.14#ibcon#about to read 6, iclass 11, count 0 2006.285.12:31:00.14#ibcon#read 6, iclass 11, count 0 2006.285.12:31:00.14#ibcon#end of sib2, iclass 11, count 0 2006.285.12:31:00.14#ibcon#*mode == 0, iclass 11, count 0 2006.285.12:31:00.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.12:31:00.14#ibcon#[27=USB\r\n] 2006.285.12:31:00.14#ibcon#*before write, iclass 11, count 0 2006.285.12:31:00.14#ibcon#enter sib2, iclass 11, count 0 2006.285.12:31:00.14#ibcon#flushed, iclass 11, count 0 2006.285.12:31:00.14#ibcon#about to write, iclass 11, count 0 2006.285.12:31:00.14#ibcon#wrote, iclass 11, count 0 2006.285.12:31:00.14#ibcon#about to read 3, iclass 11, count 0 2006.285.12:31:00.17#ibcon#read 3, iclass 11, count 0 2006.285.12:31:00.17#ibcon#about to read 4, iclass 11, count 0 2006.285.12:31:00.17#ibcon#read 4, iclass 11, count 0 2006.285.12:31:00.17#ibcon#about to read 5, iclass 11, count 0 2006.285.12:31:00.17#ibcon#read 5, iclass 11, count 0 2006.285.12:31:00.17#ibcon#about to read 6, iclass 11, count 0 2006.285.12:31:00.17#ibcon#read 6, iclass 11, count 0 2006.285.12:31:00.17#ibcon#end of sib2, iclass 11, count 0 2006.285.12:31:00.17#ibcon#*after write, iclass 11, count 0 2006.285.12:31:00.17#ibcon#*before return 0, iclass 11, count 0 2006.285.12:31:00.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:31:00.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:31:00.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.12:31:00.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.12:31:00.17$vck44/vblo=2,634.99 2006.285.12:31:00.17#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.12:31:00.17#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.12:31:00.17#ibcon#ireg 17 cls_cnt 0 2006.285.12:31:00.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:31:00.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:31:00.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:31:00.17#ibcon#enter wrdev, iclass 13, count 0 2006.285.12:31:00.17#ibcon#first serial, iclass 13, count 0 2006.285.12:31:00.17#ibcon#enter sib2, iclass 13, count 0 2006.285.12:31:00.17#ibcon#flushed, iclass 13, count 0 2006.285.12:31:00.17#ibcon#about to write, iclass 13, count 0 2006.285.12:31:00.17#ibcon#wrote, iclass 13, count 0 2006.285.12:31:00.17#ibcon#about to read 3, iclass 13, count 0 2006.285.12:31:00.19#ibcon#read 3, iclass 13, count 0 2006.285.12:31:00.19#ibcon#about to read 4, iclass 13, count 0 2006.285.12:31:00.19#ibcon#read 4, iclass 13, count 0 2006.285.12:31:00.19#ibcon#about to read 5, iclass 13, count 0 2006.285.12:31:00.19#ibcon#read 5, iclass 13, count 0 2006.285.12:31:00.19#ibcon#about to read 6, iclass 13, count 0 2006.285.12:31:00.19#ibcon#read 6, iclass 13, count 0 2006.285.12:31:00.19#ibcon#end of sib2, iclass 13, count 0 2006.285.12:31:00.19#ibcon#*mode == 0, iclass 13, count 0 2006.285.12:31:00.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.12:31:00.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.12:31:00.19#ibcon#*before write, iclass 13, count 0 2006.285.12:31:00.19#ibcon#enter sib2, iclass 13, count 0 2006.285.12:31:00.19#ibcon#flushed, iclass 13, count 0 2006.285.12:31:00.19#ibcon#about to write, iclass 13, count 0 2006.285.12:31:00.19#ibcon#wrote, iclass 13, count 0 2006.285.12:31:00.19#ibcon#about to read 3, iclass 13, count 0 2006.285.12:31:00.23#ibcon#read 3, iclass 13, count 0 2006.285.12:31:00.23#ibcon#about to read 4, iclass 13, count 0 2006.285.12:31:00.23#ibcon#read 4, iclass 13, count 0 2006.285.12:31:00.23#ibcon#about to read 5, iclass 13, count 0 2006.285.12:31:00.23#ibcon#read 5, iclass 13, count 0 2006.285.12:31:00.23#ibcon#about to read 6, iclass 13, count 0 2006.285.12:31:00.23#ibcon#read 6, iclass 13, count 0 2006.285.12:31:00.23#ibcon#end of sib2, iclass 13, count 0 2006.285.12:31:00.23#ibcon#*after write, iclass 13, count 0 2006.285.12:31:00.23#ibcon#*before return 0, iclass 13, count 0 2006.285.12:31:00.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:31:00.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:31:00.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.12:31:00.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.12:31:00.23$vck44/vb=2,5 2006.285.12:31:00.23#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.12:31:00.23#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.12:31:00.23#ibcon#ireg 11 cls_cnt 2 2006.285.12:31:00.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:31:00.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:31:00.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:31:00.29#ibcon#enter wrdev, iclass 15, count 2 2006.285.12:31:00.29#ibcon#first serial, iclass 15, count 2 2006.285.12:31:00.29#ibcon#enter sib2, iclass 15, count 2 2006.285.12:31:00.29#ibcon#flushed, iclass 15, count 2 2006.285.12:31:00.29#ibcon#about to write, iclass 15, count 2 2006.285.12:31:00.29#ibcon#wrote, iclass 15, count 2 2006.285.12:31:00.29#ibcon#about to read 3, iclass 15, count 2 2006.285.12:31:00.31#ibcon#read 3, iclass 15, count 2 2006.285.12:31:00.31#ibcon#about to read 4, iclass 15, count 2 2006.285.12:31:00.31#ibcon#read 4, iclass 15, count 2 2006.285.12:31:00.31#ibcon#about to read 5, iclass 15, count 2 2006.285.12:31:00.31#ibcon#read 5, iclass 15, count 2 2006.285.12:31:00.31#ibcon#about to read 6, iclass 15, count 2 2006.285.12:31:00.31#ibcon#read 6, iclass 15, count 2 2006.285.12:31:00.31#ibcon#end of sib2, iclass 15, count 2 2006.285.12:31:00.31#ibcon#*mode == 0, iclass 15, count 2 2006.285.12:31:00.31#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.12:31:00.31#ibcon#[27=AT02-05\r\n] 2006.285.12:31:00.31#ibcon#*before write, iclass 15, count 2 2006.285.12:31:00.31#ibcon#enter sib2, iclass 15, count 2 2006.285.12:31:00.31#ibcon#flushed, iclass 15, count 2 2006.285.12:31:00.31#ibcon#about to write, iclass 15, count 2 2006.285.12:31:00.31#ibcon#wrote, iclass 15, count 2 2006.285.12:31:00.31#ibcon#about to read 3, iclass 15, count 2 2006.285.12:31:00.34#ibcon#read 3, iclass 15, count 2 2006.285.12:31:00.34#ibcon#about to read 4, iclass 15, count 2 2006.285.12:31:00.34#ibcon#read 4, iclass 15, count 2 2006.285.12:31:00.34#ibcon#about to read 5, iclass 15, count 2 2006.285.12:31:00.34#ibcon#read 5, iclass 15, count 2 2006.285.12:31:00.34#ibcon#about to read 6, iclass 15, count 2 2006.285.12:31:00.34#ibcon#read 6, iclass 15, count 2 2006.285.12:31:00.34#ibcon#end of sib2, iclass 15, count 2 2006.285.12:31:00.34#ibcon#*after write, iclass 15, count 2 2006.285.12:31:00.34#ibcon#*before return 0, iclass 15, count 2 2006.285.12:31:00.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:31:00.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:31:00.34#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.12:31:00.34#ibcon#ireg 7 cls_cnt 0 2006.285.12:31:00.34#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:31:00.46#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:31:00.46#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:31:00.46#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:31:00.46#ibcon#first serial, iclass 15, count 0 2006.285.12:31:00.46#ibcon#enter sib2, iclass 15, count 0 2006.285.12:31:00.46#ibcon#flushed, iclass 15, count 0 2006.285.12:31:00.46#ibcon#about to write, iclass 15, count 0 2006.285.12:31:00.46#ibcon#wrote, iclass 15, count 0 2006.285.12:31:00.46#ibcon#about to read 3, iclass 15, count 0 2006.285.12:31:00.48#ibcon#read 3, iclass 15, count 0 2006.285.12:31:00.48#ibcon#about to read 4, iclass 15, count 0 2006.285.12:31:00.48#ibcon#read 4, iclass 15, count 0 2006.285.12:31:00.48#ibcon#about to read 5, iclass 15, count 0 2006.285.12:31:00.48#ibcon#read 5, iclass 15, count 0 2006.285.12:31:00.48#ibcon#about to read 6, iclass 15, count 0 2006.285.12:31:00.48#ibcon#read 6, iclass 15, count 0 2006.285.12:31:00.48#ibcon#end of sib2, iclass 15, count 0 2006.285.12:31:00.48#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:31:00.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:31:00.48#ibcon#[27=USB\r\n] 2006.285.12:31:00.48#ibcon#*before write, iclass 15, count 0 2006.285.12:31:00.48#ibcon#enter sib2, iclass 15, count 0 2006.285.12:31:00.48#ibcon#flushed, iclass 15, count 0 2006.285.12:31:00.48#ibcon#about to write, iclass 15, count 0 2006.285.12:31:00.48#ibcon#wrote, iclass 15, count 0 2006.285.12:31:00.48#ibcon#about to read 3, iclass 15, count 0 2006.285.12:31:00.51#ibcon#read 3, iclass 15, count 0 2006.285.12:31:00.51#ibcon#about to read 4, iclass 15, count 0 2006.285.12:31:00.51#ibcon#read 4, iclass 15, count 0 2006.285.12:31:00.51#ibcon#about to read 5, iclass 15, count 0 2006.285.12:31:00.51#ibcon#read 5, iclass 15, count 0 2006.285.12:31:00.51#ibcon#about to read 6, iclass 15, count 0 2006.285.12:31:00.51#ibcon#read 6, iclass 15, count 0 2006.285.12:31:00.51#ibcon#end of sib2, iclass 15, count 0 2006.285.12:31:00.51#ibcon#*after write, iclass 15, count 0 2006.285.12:31:00.51#ibcon#*before return 0, iclass 15, count 0 2006.285.12:31:00.51#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:31:00.51#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:31:00.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:31:00.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:31:00.51$vck44/vblo=3,649.99 2006.285.12:31:00.51#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.12:31:00.51#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.12:31:00.51#ibcon#ireg 17 cls_cnt 0 2006.285.12:31:00.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:31:00.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:31:00.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:31:00.51#ibcon#enter wrdev, iclass 17, count 0 2006.285.12:31:00.51#ibcon#first serial, iclass 17, count 0 2006.285.12:31:00.51#ibcon#enter sib2, iclass 17, count 0 2006.285.12:31:00.51#ibcon#flushed, iclass 17, count 0 2006.285.12:31:00.51#ibcon#about to write, iclass 17, count 0 2006.285.12:31:00.51#ibcon#wrote, iclass 17, count 0 2006.285.12:31:00.51#ibcon#about to read 3, iclass 17, count 0 2006.285.12:31:00.53#ibcon#read 3, iclass 17, count 0 2006.285.12:31:00.53#ibcon#about to read 4, iclass 17, count 0 2006.285.12:31:00.53#ibcon#read 4, iclass 17, count 0 2006.285.12:31:00.53#ibcon#about to read 5, iclass 17, count 0 2006.285.12:31:00.53#ibcon#read 5, iclass 17, count 0 2006.285.12:31:00.53#ibcon#about to read 6, iclass 17, count 0 2006.285.12:31:00.53#ibcon#read 6, iclass 17, count 0 2006.285.12:31:00.53#ibcon#end of sib2, iclass 17, count 0 2006.285.12:31:00.53#ibcon#*mode == 0, iclass 17, count 0 2006.285.12:31:00.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.12:31:00.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.12:31:00.53#ibcon#*before write, iclass 17, count 0 2006.285.12:31:00.53#ibcon#enter sib2, iclass 17, count 0 2006.285.12:31:00.53#ibcon#flushed, iclass 17, count 0 2006.285.12:31:00.53#ibcon#about to write, iclass 17, count 0 2006.285.12:31:00.53#ibcon#wrote, iclass 17, count 0 2006.285.12:31:00.53#ibcon#about to read 3, iclass 17, count 0 2006.285.12:31:00.57#ibcon#read 3, iclass 17, count 0 2006.285.12:31:00.57#ibcon#about to read 4, iclass 17, count 0 2006.285.12:31:00.57#ibcon#read 4, iclass 17, count 0 2006.285.12:31:00.57#ibcon#about to read 5, iclass 17, count 0 2006.285.12:31:00.57#ibcon#read 5, iclass 17, count 0 2006.285.12:31:00.57#ibcon#about to read 6, iclass 17, count 0 2006.285.12:31:00.57#ibcon#read 6, iclass 17, count 0 2006.285.12:31:00.57#ibcon#end of sib2, iclass 17, count 0 2006.285.12:31:00.57#ibcon#*after write, iclass 17, count 0 2006.285.12:31:00.57#ibcon#*before return 0, iclass 17, count 0 2006.285.12:31:00.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:31:00.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:31:00.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.12:31:00.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.12:31:00.57$vck44/vb=3,4 2006.285.12:31:00.57#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.12:31:00.57#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.12:31:00.57#ibcon#ireg 11 cls_cnt 2 2006.285.12:31:00.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:31:00.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:31:00.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:31:00.63#ibcon#enter wrdev, iclass 19, count 2 2006.285.12:31:00.63#ibcon#first serial, iclass 19, count 2 2006.285.12:31:00.63#ibcon#enter sib2, iclass 19, count 2 2006.285.12:31:00.63#ibcon#flushed, iclass 19, count 2 2006.285.12:31:00.63#ibcon#about to write, iclass 19, count 2 2006.285.12:31:00.63#ibcon#wrote, iclass 19, count 2 2006.285.12:31:00.63#ibcon#about to read 3, iclass 19, count 2 2006.285.12:31:00.65#ibcon#read 3, iclass 19, count 2 2006.285.12:31:00.65#ibcon#about to read 4, iclass 19, count 2 2006.285.12:31:00.65#ibcon#read 4, iclass 19, count 2 2006.285.12:31:00.65#ibcon#about to read 5, iclass 19, count 2 2006.285.12:31:00.65#ibcon#read 5, iclass 19, count 2 2006.285.12:31:00.65#ibcon#about to read 6, iclass 19, count 2 2006.285.12:31:00.65#ibcon#read 6, iclass 19, count 2 2006.285.12:31:00.65#ibcon#end of sib2, iclass 19, count 2 2006.285.12:31:00.65#ibcon#*mode == 0, iclass 19, count 2 2006.285.12:31:00.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.12:31:00.65#ibcon#[27=AT03-04\r\n] 2006.285.12:31:00.65#ibcon#*before write, iclass 19, count 2 2006.285.12:31:00.65#ibcon#enter sib2, iclass 19, count 2 2006.285.12:31:00.65#ibcon#flushed, iclass 19, count 2 2006.285.12:31:00.65#ibcon#about to write, iclass 19, count 2 2006.285.12:31:00.65#ibcon#wrote, iclass 19, count 2 2006.285.12:31:00.65#ibcon#about to read 3, iclass 19, count 2 2006.285.12:31:00.68#ibcon#read 3, iclass 19, count 2 2006.285.12:31:00.68#ibcon#about to read 4, iclass 19, count 2 2006.285.12:31:00.68#ibcon#read 4, iclass 19, count 2 2006.285.12:31:00.68#ibcon#about to read 5, iclass 19, count 2 2006.285.12:31:00.68#ibcon#read 5, iclass 19, count 2 2006.285.12:31:00.68#ibcon#about to read 6, iclass 19, count 2 2006.285.12:31:00.68#ibcon#read 6, iclass 19, count 2 2006.285.12:31:00.68#ibcon#end of sib2, iclass 19, count 2 2006.285.12:31:00.68#ibcon#*after write, iclass 19, count 2 2006.285.12:31:00.68#ibcon#*before return 0, iclass 19, count 2 2006.285.12:31:00.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:31:00.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:31:00.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.12:31:00.68#ibcon#ireg 7 cls_cnt 0 2006.285.12:31:00.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:31:00.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:31:00.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:31:00.80#ibcon#enter wrdev, iclass 19, count 0 2006.285.12:31:00.80#ibcon#first serial, iclass 19, count 0 2006.285.12:31:00.80#ibcon#enter sib2, iclass 19, count 0 2006.285.12:31:00.80#ibcon#flushed, iclass 19, count 0 2006.285.12:31:00.80#ibcon#about to write, iclass 19, count 0 2006.285.12:31:00.80#ibcon#wrote, iclass 19, count 0 2006.285.12:31:00.80#ibcon#about to read 3, iclass 19, count 0 2006.285.12:31:00.82#ibcon#read 3, iclass 19, count 0 2006.285.12:31:00.82#ibcon#about to read 4, iclass 19, count 0 2006.285.12:31:00.82#ibcon#read 4, iclass 19, count 0 2006.285.12:31:00.82#ibcon#about to read 5, iclass 19, count 0 2006.285.12:31:00.82#ibcon#read 5, iclass 19, count 0 2006.285.12:31:00.82#ibcon#about to read 6, iclass 19, count 0 2006.285.12:31:00.82#ibcon#read 6, iclass 19, count 0 2006.285.12:31:00.82#ibcon#end of sib2, iclass 19, count 0 2006.285.12:31:00.82#ibcon#*mode == 0, iclass 19, count 0 2006.285.12:31:00.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.12:31:00.82#ibcon#[27=USB\r\n] 2006.285.12:31:00.82#ibcon#*before write, iclass 19, count 0 2006.285.12:31:00.82#ibcon#enter sib2, iclass 19, count 0 2006.285.12:31:00.82#ibcon#flushed, iclass 19, count 0 2006.285.12:31:00.82#ibcon#about to write, iclass 19, count 0 2006.285.12:31:00.82#ibcon#wrote, iclass 19, count 0 2006.285.12:31:00.82#ibcon#about to read 3, iclass 19, count 0 2006.285.12:31:00.85#ibcon#read 3, iclass 19, count 0 2006.285.12:31:00.85#ibcon#about to read 4, iclass 19, count 0 2006.285.12:31:00.85#ibcon#read 4, iclass 19, count 0 2006.285.12:31:00.85#ibcon#about to read 5, iclass 19, count 0 2006.285.12:31:00.85#ibcon#read 5, iclass 19, count 0 2006.285.12:31:00.85#ibcon#about to read 6, iclass 19, count 0 2006.285.12:31:00.85#ibcon#read 6, iclass 19, count 0 2006.285.12:31:00.85#ibcon#end of sib2, iclass 19, count 0 2006.285.12:31:00.85#ibcon#*after write, iclass 19, count 0 2006.285.12:31:00.85#ibcon#*before return 0, iclass 19, count 0 2006.285.12:31:00.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:31:00.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:31:00.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.12:31:00.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.12:31:00.85$vck44/vblo=4,679.99 2006.285.12:31:00.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.12:31:00.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.12:31:00.85#ibcon#ireg 17 cls_cnt 0 2006.285.12:31:00.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:31:00.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:31:00.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:31:00.85#ibcon#enter wrdev, iclass 21, count 0 2006.285.12:31:00.85#ibcon#first serial, iclass 21, count 0 2006.285.12:31:00.85#ibcon#enter sib2, iclass 21, count 0 2006.285.12:31:00.85#ibcon#flushed, iclass 21, count 0 2006.285.12:31:00.85#ibcon#about to write, iclass 21, count 0 2006.285.12:31:00.85#ibcon#wrote, iclass 21, count 0 2006.285.12:31:00.85#ibcon#about to read 3, iclass 21, count 0 2006.285.12:31:00.87#ibcon#read 3, iclass 21, count 0 2006.285.12:31:00.87#ibcon#about to read 4, iclass 21, count 0 2006.285.12:31:00.87#ibcon#read 4, iclass 21, count 0 2006.285.12:31:00.87#ibcon#about to read 5, iclass 21, count 0 2006.285.12:31:00.87#ibcon#read 5, iclass 21, count 0 2006.285.12:31:00.87#ibcon#about to read 6, iclass 21, count 0 2006.285.12:31:00.87#ibcon#read 6, iclass 21, count 0 2006.285.12:31:00.87#ibcon#end of sib2, iclass 21, count 0 2006.285.12:31:00.87#ibcon#*mode == 0, iclass 21, count 0 2006.285.12:31:00.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.12:31:00.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.12:31:00.87#ibcon#*before write, iclass 21, count 0 2006.285.12:31:00.87#ibcon#enter sib2, iclass 21, count 0 2006.285.12:31:00.87#ibcon#flushed, iclass 21, count 0 2006.285.12:31:00.87#ibcon#about to write, iclass 21, count 0 2006.285.12:31:00.87#ibcon#wrote, iclass 21, count 0 2006.285.12:31:00.87#ibcon#about to read 3, iclass 21, count 0 2006.285.12:31:00.91#ibcon#read 3, iclass 21, count 0 2006.285.12:31:00.91#ibcon#about to read 4, iclass 21, count 0 2006.285.12:31:00.91#ibcon#read 4, iclass 21, count 0 2006.285.12:31:00.91#ibcon#about to read 5, iclass 21, count 0 2006.285.12:31:00.91#ibcon#read 5, iclass 21, count 0 2006.285.12:31:00.91#ibcon#about to read 6, iclass 21, count 0 2006.285.12:31:00.91#ibcon#read 6, iclass 21, count 0 2006.285.12:31:00.91#ibcon#end of sib2, iclass 21, count 0 2006.285.12:31:00.91#ibcon#*after write, iclass 21, count 0 2006.285.12:31:00.91#ibcon#*before return 0, iclass 21, count 0 2006.285.12:31:00.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:31:00.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:31:00.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.12:31:00.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.12:31:00.91$vck44/vb=4,5 2006.285.12:31:00.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.12:31:00.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.12:31:00.91#ibcon#ireg 11 cls_cnt 2 2006.285.12:31:00.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:31:00.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:31:00.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:31:00.97#ibcon#enter wrdev, iclass 23, count 2 2006.285.12:31:00.97#ibcon#first serial, iclass 23, count 2 2006.285.12:31:00.97#ibcon#enter sib2, iclass 23, count 2 2006.285.12:31:00.97#ibcon#flushed, iclass 23, count 2 2006.285.12:31:00.97#ibcon#about to write, iclass 23, count 2 2006.285.12:31:00.97#ibcon#wrote, iclass 23, count 2 2006.285.12:31:00.97#ibcon#about to read 3, iclass 23, count 2 2006.285.12:31:00.99#ibcon#read 3, iclass 23, count 2 2006.285.12:31:00.99#ibcon#about to read 4, iclass 23, count 2 2006.285.12:31:00.99#ibcon#read 4, iclass 23, count 2 2006.285.12:31:00.99#ibcon#about to read 5, iclass 23, count 2 2006.285.12:31:00.99#ibcon#read 5, iclass 23, count 2 2006.285.12:31:00.99#ibcon#about to read 6, iclass 23, count 2 2006.285.12:31:00.99#ibcon#read 6, iclass 23, count 2 2006.285.12:31:00.99#ibcon#end of sib2, iclass 23, count 2 2006.285.12:31:00.99#ibcon#*mode == 0, iclass 23, count 2 2006.285.12:31:00.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.12:31:00.99#ibcon#[27=AT04-05\r\n] 2006.285.12:31:00.99#ibcon#*before write, iclass 23, count 2 2006.285.12:31:00.99#ibcon#enter sib2, iclass 23, count 2 2006.285.12:31:00.99#ibcon#flushed, iclass 23, count 2 2006.285.12:31:00.99#ibcon#about to write, iclass 23, count 2 2006.285.12:31:00.99#ibcon#wrote, iclass 23, count 2 2006.285.12:31:00.99#ibcon#about to read 3, iclass 23, count 2 2006.285.12:31:01.02#ibcon#read 3, iclass 23, count 2 2006.285.12:31:01.02#ibcon#about to read 4, iclass 23, count 2 2006.285.12:31:01.02#ibcon#read 4, iclass 23, count 2 2006.285.12:31:01.02#ibcon#about to read 5, iclass 23, count 2 2006.285.12:31:01.02#ibcon#read 5, iclass 23, count 2 2006.285.12:31:01.02#ibcon#about to read 6, iclass 23, count 2 2006.285.12:31:01.02#ibcon#read 6, iclass 23, count 2 2006.285.12:31:01.02#ibcon#end of sib2, iclass 23, count 2 2006.285.12:31:01.02#ibcon#*after write, iclass 23, count 2 2006.285.12:31:01.02#ibcon#*before return 0, iclass 23, count 2 2006.285.12:31:01.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:31:01.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:31:01.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.12:31:01.02#ibcon#ireg 7 cls_cnt 0 2006.285.12:31:01.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:31:01.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:31:01.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:31:01.14#ibcon#enter wrdev, iclass 23, count 0 2006.285.12:31:01.14#ibcon#first serial, iclass 23, count 0 2006.285.12:31:01.14#ibcon#enter sib2, iclass 23, count 0 2006.285.12:31:01.14#ibcon#flushed, iclass 23, count 0 2006.285.12:31:01.14#ibcon#about to write, iclass 23, count 0 2006.285.12:31:01.14#ibcon#wrote, iclass 23, count 0 2006.285.12:31:01.14#ibcon#about to read 3, iclass 23, count 0 2006.285.12:31:01.16#ibcon#read 3, iclass 23, count 0 2006.285.12:31:01.16#ibcon#about to read 4, iclass 23, count 0 2006.285.12:31:01.16#ibcon#read 4, iclass 23, count 0 2006.285.12:31:01.16#ibcon#about to read 5, iclass 23, count 0 2006.285.12:31:01.16#ibcon#read 5, iclass 23, count 0 2006.285.12:31:01.16#ibcon#about to read 6, iclass 23, count 0 2006.285.12:31:01.16#ibcon#read 6, iclass 23, count 0 2006.285.12:31:01.16#ibcon#end of sib2, iclass 23, count 0 2006.285.12:31:01.16#ibcon#*mode == 0, iclass 23, count 0 2006.285.12:31:01.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.12:31:01.16#ibcon#[27=USB\r\n] 2006.285.12:31:01.16#ibcon#*before write, iclass 23, count 0 2006.285.12:31:01.16#ibcon#enter sib2, iclass 23, count 0 2006.285.12:31:01.16#ibcon#flushed, iclass 23, count 0 2006.285.12:31:01.16#ibcon#about to write, iclass 23, count 0 2006.285.12:31:01.16#ibcon#wrote, iclass 23, count 0 2006.285.12:31:01.16#ibcon#about to read 3, iclass 23, count 0 2006.285.12:31:01.19#ibcon#read 3, iclass 23, count 0 2006.285.12:31:01.19#ibcon#about to read 4, iclass 23, count 0 2006.285.12:31:01.19#ibcon#read 4, iclass 23, count 0 2006.285.12:31:01.19#ibcon#about to read 5, iclass 23, count 0 2006.285.12:31:01.19#ibcon#read 5, iclass 23, count 0 2006.285.12:31:01.19#ibcon#about to read 6, iclass 23, count 0 2006.285.12:31:01.19#ibcon#read 6, iclass 23, count 0 2006.285.12:31:01.19#ibcon#end of sib2, iclass 23, count 0 2006.285.12:31:01.19#ibcon#*after write, iclass 23, count 0 2006.285.12:31:01.19#ibcon#*before return 0, iclass 23, count 0 2006.285.12:31:01.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:31:01.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:31:01.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.12:31:01.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.12:31:01.19$vck44/vblo=5,709.99 2006.285.12:31:01.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.12:31:01.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.12:31:01.19#ibcon#ireg 17 cls_cnt 0 2006.285.12:31:01.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:31:01.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:31:01.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:31:01.19#ibcon#enter wrdev, iclass 25, count 0 2006.285.12:31:01.19#ibcon#first serial, iclass 25, count 0 2006.285.12:31:01.19#ibcon#enter sib2, iclass 25, count 0 2006.285.12:31:01.19#ibcon#flushed, iclass 25, count 0 2006.285.12:31:01.19#ibcon#about to write, iclass 25, count 0 2006.285.12:31:01.19#ibcon#wrote, iclass 25, count 0 2006.285.12:31:01.19#ibcon#about to read 3, iclass 25, count 0 2006.285.12:31:01.21#ibcon#read 3, iclass 25, count 0 2006.285.12:31:01.21#ibcon#about to read 4, iclass 25, count 0 2006.285.12:31:01.21#ibcon#read 4, iclass 25, count 0 2006.285.12:31:01.21#ibcon#about to read 5, iclass 25, count 0 2006.285.12:31:01.21#ibcon#read 5, iclass 25, count 0 2006.285.12:31:01.21#ibcon#about to read 6, iclass 25, count 0 2006.285.12:31:01.21#ibcon#read 6, iclass 25, count 0 2006.285.12:31:01.21#ibcon#end of sib2, iclass 25, count 0 2006.285.12:31:01.21#ibcon#*mode == 0, iclass 25, count 0 2006.285.12:31:01.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.12:31:01.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.12:31:01.21#ibcon#*before write, iclass 25, count 0 2006.285.12:31:01.21#ibcon#enter sib2, iclass 25, count 0 2006.285.12:31:01.21#ibcon#flushed, iclass 25, count 0 2006.285.12:31:01.21#ibcon#about to write, iclass 25, count 0 2006.285.12:31:01.21#ibcon#wrote, iclass 25, count 0 2006.285.12:31:01.21#ibcon#about to read 3, iclass 25, count 0 2006.285.12:31:01.25#ibcon#read 3, iclass 25, count 0 2006.285.12:31:01.25#ibcon#about to read 4, iclass 25, count 0 2006.285.12:31:01.25#ibcon#read 4, iclass 25, count 0 2006.285.12:31:01.25#ibcon#about to read 5, iclass 25, count 0 2006.285.12:31:01.25#ibcon#read 5, iclass 25, count 0 2006.285.12:31:01.25#ibcon#about to read 6, iclass 25, count 0 2006.285.12:31:01.25#ibcon#read 6, iclass 25, count 0 2006.285.12:31:01.25#ibcon#end of sib2, iclass 25, count 0 2006.285.12:31:01.25#ibcon#*after write, iclass 25, count 0 2006.285.12:31:01.25#ibcon#*before return 0, iclass 25, count 0 2006.285.12:31:01.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:31:01.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:31:01.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.12:31:01.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.12:31:01.25$vck44/vb=5,4 2006.285.12:31:01.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.12:31:01.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.12:31:01.25#ibcon#ireg 11 cls_cnt 2 2006.285.12:31:01.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:31:01.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:31:01.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:31:01.31#ibcon#enter wrdev, iclass 27, count 2 2006.285.12:31:01.31#ibcon#first serial, iclass 27, count 2 2006.285.12:31:01.31#ibcon#enter sib2, iclass 27, count 2 2006.285.12:31:01.31#ibcon#flushed, iclass 27, count 2 2006.285.12:31:01.31#ibcon#about to write, iclass 27, count 2 2006.285.12:31:01.31#ibcon#wrote, iclass 27, count 2 2006.285.12:31:01.31#ibcon#about to read 3, iclass 27, count 2 2006.285.12:31:01.33#ibcon#read 3, iclass 27, count 2 2006.285.12:31:01.33#ibcon#about to read 4, iclass 27, count 2 2006.285.12:31:01.33#ibcon#read 4, iclass 27, count 2 2006.285.12:31:01.33#ibcon#about to read 5, iclass 27, count 2 2006.285.12:31:01.33#ibcon#read 5, iclass 27, count 2 2006.285.12:31:01.33#ibcon#about to read 6, iclass 27, count 2 2006.285.12:31:01.33#ibcon#read 6, iclass 27, count 2 2006.285.12:31:01.33#ibcon#end of sib2, iclass 27, count 2 2006.285.12:31:01.33#ibcon#*mode == 0, iclass 27, count 2 2006.285.12:31:01.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.12:31:01.33#ibcon#[27=AT05-04\r\n] 2006.285.12:31:01.33#ibcon#*before write, iclass 27, count 2 2006.285.12:31:01.33#ibcon#enter sib2, iclass 27, count 2 2006.285.12:31:01.33#ibcon#flushed, iclass 27, count 2 2006.285.12:31:01.33#ibcon#about to write, iclass 27, count 2 2006.285.12:31:01.33#ibcon#wrote, iclass 27, count 2 2006.285.12:31:01.33#ibcon#about to read 3, iclass 27, count 2 2006.285.12:31:01.36#ibcon#read 3, iclass 27, count 2 2006.285.12:31:01.36#ibcon#about to read 4, iclass 27, count 2 2006.285.12:31:01.36#ibcon#read 4, iclass 27, count 2 2006.285.12:31:01.36#ibcon#about to read 5, iclass 27, count 2 2006.285.12:31:01.36#ibcon#read 5, iclass 27, count 2 2006.285.12:31:01.36#ibcon#about to read 6, iclass 27, count 2 2006.285.12:31:01.36#ibcon#read 6, iclass 27, count 2 2006.285.12:31:01.36#ibcon#end of sib2, iclass 27, count 2 2006.285.12:31:01.36#ibcon#*after write, iclass 27, count 2 2006.285.12:31:01.36#ibcon#*before return 0, iclass 27, count 2 2006.285.12:31:01.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:31:01.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:31:01.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.12:31:01.36#ibcon#ireg 7 cls_cnt 0 2006.285.12:31:01.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:31:01.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:31:01.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:31:01.48#ibcon#enter wrdev, iclass 27, count 0 2006.285.12:31:01.48#ibcon#first serial, iclass 27, count 0 2006.285.12:31:01.48#ibcon#enter sib2, iclass 27, count 0 2006.285.12:31:01.48#ibcon#flushed, iclass 27, count 0 2006.285.12:31:01.48#ibcon#about to write, iclass 27, count 0 2006.285.12:31:01.48#ibcon#wrote, iclass 27, count 0 2006.285.12:31:01.48#ibcon#about to read 3, iclass 27, count 0 2006.285.12:31:01.50#ibcon#read 3, iclass 27, count 0 2006.285.12:31:01.50#ibcon#about to read 4, iclass 27, count 0 2006.285.12:31:01.50#ibcon#read 4, iclass 27, count 0 2006.285.12:31:01.50#ibcon#about to read 5, iclass 27, count 0 2006.285.12:31:01.50#ibcon#read 5, iclass 27, count 0 2006.285.12:31:01.50#ibcon#about to read 6, iclass 27, count 0 2006.285.12:31:01.50#ibcon#read 6, iclass 27, count 0 2006.285.12:31:01.50#ibcon#end of sib2, iclass 27, count 0 2006.285.12:31:01.50#ibcon#*mode == 0, iclass 27, count 0 2006.285.12:31:01.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.12:31:01.50#ibcon#[27=USB\r\n] 2006.285.12:31:01.50#ibcon#*before write, iclass 27, count 0 2006.285.12:31:01.50#ibcon#enter sib2, iclass 27, count 0 2006.285.12:31:01.50#ibcon#flushed, iclass 27, count 0 2006.285.12:31:01.50#ibcon#about to write, iclass 27, count 0 2006.285.12:31:01.50#ibcon#wrote, iclass 27, count 0 2006.285.12:31:01.50#ibcon#about to read 3, iclass 27, count 0 2006.285.12:31:01.53#ibcon#read 3, iclass 27, count 0 2006.285.12:31:01.53#ibcon#about to read 4, iclass 27, count 0 2006.285.12:31:01.53#ibcon#read 4, iclass 27, count 0 2006.285.12:31:01.53#ibcon#about to read 5, iclass 27, count 0 2006.285.12:31:01.53#ibcon#read 5, iclass 27, count 0 2006.285.12:31:01.53#ibcon#about to read 6, iclass 27, count 0 2006.285.12:31:01.53#ibcon#read 6, iclass 27, count 0 2006.285.12:31:01.53#ibcon#end of sib2, iclass 27, count 0 2006.285.12:31:01.53#ibcon#*after write, iclass 27, count 0 2006.285.12:31:01.53#ibcon#*before return 0, iclass 27, count 0 2006.285.12:31:01.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:31:01.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:31:01.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.12:31:01.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.12:31:01.53$vck44/vblo=6,719.99 2006.285.12:31:01.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.12:31:01.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.12:31:01.53#ibcon#ireg 17 cls_cnt 0 2006.285.12:31:01.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:31:01.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:31:01.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:31:01.53#ibcon#enter wrdev, iclass 29, count 0 2006.285.12:31:01.53#ibcon#first serial, iclass 29, count 0 2006.285.12:31:01.53#ibcon#enter sib2, iclass 29, count 0 2006.285.12:31:01.53#ibcon#flushed, iclass 29, count 0 2006.285.12:31:01.53#ibcon#about to write, iclass 29, count 0 2006.285.12:31:01.53#ibcon#wrote, iclass 29, count 0 2006.285.12:31:01.53#ibcon#about to read 3, iclass 29, count 0 2006.285.12:31:01.55#ibcon#read 3, iclass 29, count 0 2006.285.12:31:01.55#ibcon#about to read 4, iclass 29, count 0 2006.285.12:31:01.55#ibcon#read 4, iclass 29, count 0 2006.285.12:31:01.55#ibcon#about to read 5, iclass 29, count 0 2006.285.12:31:01.55#ibcon#read 5, iclass 29, count 0 2006.285.12:31:01.55#ibcon#about to read 6, iclass 29, count 0 2006.285.12:31:01.55#ibcon#read 6, iclass 29, count 0 2006.285.12:31:01.55#ibcon#end of sib2, iclass 29, count 0 2006.285.12:31:01.55#ibcon#*mode == 0, iclass 29, count 0 2006.285.12:31:01.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.12:31:01.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.12:31:01.55#ibcon#*before write, iclass 29, count 0 2006.285.12:31:01.55#ibcon#enter sib2, iclass 29, count 0 2006.285.12:31:01.55#ibcon#flushed, iclass 29, count 0 2006.285.12:31:01.55#ibcon#about to write, iclass 29, count 0 2006.285.12:31:01.55#ibcon#wrote, iclass 29, count 0 2006.285.12:31:01.55#ibcon#about to read 3, iclass 29, count 0 2006.285.12:31:01.59#ibcon#read 3, iclass 29, count 0 2006.285.12:31:01.59#ibcon#about to read 4, iclass 29, count 0 2006.285.12:31:01.59#ibcon#read 4, iclass 29, count 0 2006.285.12:31:01.59#ibcon#about to read 5, iclass 29, count 0 2006.285.12:31:01.59#ibcon#read 5, iclass 29, count 0 2006.285.12:31:01.59#ibcon#about to read 6, iclass 29, count 0 2006.285.12:31:01.59#ibcon#read 6, iclass 29, count 0 2006.285.12:31:01.59#ibcon#end of sib2, iclass 29, count 0 2006.285.12:31:01.59#ibcon#*after write, iclass 29, count 0 2006.285.12:31:01.59#ibcon#*before return 0, iclass 29, count 0 2006.285.12:31:01.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:31:01.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:31:01.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.12:31:01.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.12:31:01.59$vck44/vb=6,3 2006.285.12:31:01.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.12:31:01.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.12:31:01.59#ibcon#ireg 11 cls_cnt 2 2006.285.12:31:01.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:31:01.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:31:01.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:31:01.65#ibcon#enter wrdev, iclass 31, count 2 2006.285.12:31:01.65#ibcon#first serial, iclass 31, count 2 2006.285.12:31:01.65#ibcon#enter sib2, iclass 31, count 2 2006.285.12:31:01.65#ibcon#flushed, iclass 31, count 2 2006.285.12:31:01.65#ibcon#about to write, iclass 31, count 2 2006.285.12:31:01.65#ibcon#wrote, iclass 31, count 2 2006.285.12:31:01.65#ibcon#about to read 3, iclass 31, count 2 2006.285.12:31:01.67#ibcon#read 3, iclass 31, count 2 2006.285.12:31:01.67#ibcon#about to read 4, iclass 31, count 2 2006.285.12:31:01.67#ibcon#read 4, iclass 31, count 2 2006.285.12:31:01.67#ibcon#about to read 5, iclass 31, count 2 2006.285.12:31:01.67#ibcon#read 5, iclass 31, count 2 2006.285.12:31:01.67#ibcon#about to read 6, iclass 31, count 2 2006.285.12:31:01.67#ibcon#read 6, iclass 31, count 2 2006.285.12:31:01.67#ibcon#end of sib2, iclass 31, count 2 2006.285.12:31:01.67#ibcon#*mode == 0, iclass 31, count 2 2006.285.12:31:01.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.12:31:01.67#ibcon#[27=AT06-03\r\n] 2006.285.12:31:01.67#ibcon#*before write, iclass 31, count 2 2006.285.12:31:01.67#ibcon#enter sib2, iclass 31, count 2 2006.285.12:31:01.67#ibcon#flushed, iclass 31, count 2 2006.285.12:31:01.67#ibcon#about to write, iclass 31, count 2 2006.285.12:31:01.67#ibcon#wrote, iclass 31, count 2 2006.285.12:31:01.67#ibcon#about to read 3, iclass 31, count 2 2006.285.12:31:01.70#ibcon#read 3, iclass 31, count 2 2006.285.12:31:01.70#ibcon#about to read 4, iclass 31, count 2 2006.285.12:31:01.70#ibcon#read 4, iclass 31, count 2 2006.285.12:31:01.70#ibcon#about to read 5, iclass 31, count 2 2006.285.12:31:01.70#ibcon#read 5, iclass 31, count 2 2006.285.12:31:01.70#ibcon#about to read 6, iclass 31, count 2 2006.285.12:31:01.70#ibcon#read 6, iclass 31, count 2 2006.285.12:31:01.70#ibcon#end of sib2, iclass 31, count 2 2006.285.12:31:01.70#ibcon#*after write, iclass 31, count 2 2006.285.12:31:01.70#ibcon#*before return 0, iclass 31, count 2 2006.285.12:31:01.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:31:01.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:31:01.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.12:31:01.70#ibcon#ireg 7 cls_cnt 0 2006.285.12:31:01.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:31:01.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:31:01.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:31:01.82#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:31:01.82#ibcon#first serial, iclass 31, count 0 2006.285.12:31:01.82#ibcon#enter sib2, iclass 31, count 0 2006.285.12:31:01.82#ibcon#flushed, iclass 31, count 0 2006.285.12:31:01.82#ibcon#about to write, iclass 31, count 0 2006.285.12:31:01.82#ibcon#wrote, iclass 31, count 0 2006.285.12:31:01.82#ibcon#about to read 3, iclass 31, count 0 2006.285.12:31:01.84#ibcon#read 3, iclass 31, count 0 2006.285.12:31:01.84#ibcon#about to read 4, iclass 31, count 0 2006.285.12:31:01.84#ibcon#read 4, iclass 31, count 0 2006.285.12:31:01.84#ibcon#about to read 5, iclass 31, count 0 2006.285.12:31:01.84#ibcon#read 5, iclass 31, count 0 2006.285.12:31:01.84#ibcon#about to read 6, iclass 31, count 0 2006.285.12:31:01.84#ibcon#read 6, iclass 31, count 0 2006.285.12:31:01.84#ibcon#end of sib2, iclass 31, count 0 2006.285.12:31:01.84#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:31:01.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:31:01.84#ibcon#[27=USB\r\n] 2006.285.12:31:01.84#ibcon#*before write, iclass 31, count 0 2006.285.12:31:01.84#ibcon#enter sib2, iclass 31, count 0 2006.285.12:31:01.84#ibcon#flushed, iclass 31, count 0 2006.285.12:31:01.84#ibcon#about to write, iclass 31, count 0 2006.285.12:31:01.84#ibcon#wrote, iclass 31, count 0 2006.285.12:31:01.84#ibcon#about to read 3, iclass 31, count 0 2006.285.12:31:01.87#ibcon#read 3, iclass 31, count 0 2006.285.12:31:01.87#ibcon#about to read 4, iclass 31, count 0 2006.285.12:31:01.87#ibcon#read 4, iclass 31, count 0 2006.285.12:31:01.87#ibcon#about to read 5, iclass 31, count 0 2006.285.12:31:01.87#ibcon#read 5, iclass 31, count 0 2006.285.12:31:01.87#ibcon#about to read 6, iclass 31, count 0 2006.285.12:31:01.87#ibcon#read 6, iclass 31, count 0 2006.285.12:31:01.87#ibcon#end of sib2, iclass 31, count 0 2006.285.12:31:01.87#ibcon#*after write, iclass 31, count 0 2006.285.12:31:01.87#ibcon#*before return 0, iclass 31, count 0 2006.285.12:31:01.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:31:01.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:31:01.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:31:01.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:31:01.87$vck44/vblo=7,734.99 2006.285.12:31:01.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.12:31:01.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.12:31:01.87#ibcon#ireg 17 cls_cnt 0 2006.285.12:31:01.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:31:01.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:31:01.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:31:01.87#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:31:01.87#ibcon#first serial, iclass 33, count 0 2006.285.12:31:01.87#ibcon#enter sib2, iclass 33, count 0 2006.285.12:31:01.87#ibcon#flushed, iclass 33, count 0 2006.285.12:31:01.87#ibcon#about to write, iclass 33, count 0 2006.285.12:31:01.87#ibcon#wrote, iclass 33, count 0 2006.285.12:31:01.87#ibcon#about to read 3, iclass 33, count 0 2006.285.12:31:01.89#ibcon#read 3, iclass 33, count 0 2006.285.12:31:01.89#ibcon#about to read 4, iclass 33, count 0 2006.285.12:31:01.89#ibcon#read 4, iclass 33, count 0 2006.285.12:31:01.89#ibcon#about to read 5, iclass 33, count 0 2006.285.12:31:01.89#ibcon#read 5, iclass 33, count 0 2006.285.12:31:01.89#ibcon#about to read 6, iclass 33, count 0 2006.285.12:31:01.89#ibcon#read 6, iclass 33, count 0 2006.285.12:31:01.89#ibcon#end of sib2, iclass 33, count 0 2006.285.12:31:01.89#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:31:01.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:31:01.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.12:31:01.89#ibcon#*before write, iclass 33, count 0 2006.285.12:31:01.89#ibcon#enter sib2, iclass 33, count 0 2006.285.12:31:01.89#ibcon#flushed, iclass 33, count 0 2006.285.12:31:01.89#ibcon#about to write, iclass 33, count 0 2006.285.12:31:01.89#ibcon#wrote, iclass 33, count 0 2006.285.12:31:01.89#ibcon#about to read 3, iclass 33, count 0 2006.285.12:31:01.93#ibcon#read 3, iclass 33, count 0 2006.285.12:31:01.93#ibcon#about to read 4, iclass 33, count 0 2006.285.12:31:01.93#ibcon#read 4, iclass 33, count 0 2006.285.12:31:01.93#ibcon#about to read 5, iclass 33, count 0 2006.285.12:31:01.93#ibcon#read 5, iclass 33, count 0 2006.285.12:31:01.93#ibcon#about to read 6, iclass 33, count 0 2006.285.12:31:01.93#ibcon#read 6, iclass 33, count 0 2006.285.12:31:01.93#ibcon#end of sib2, iclass 33, count 0 2006.285.12:31:01.93#ibcon#*after write, iclass 33, count 0 2006.285.12:31:01.93#ibcon#*before return 0, iclass 33, count 0 2006.285.12:31:01.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:31:01.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:31:01.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:31:01.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:31:01.93$vck44/vb=7,4 2006.285.12:31:01.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.12:31:01.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.12:31:01.93#ibcon#ireg 11 cls_cnt 2 2006.285.12:31:01.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:31:01.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:31:01.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:31:01.99#ibcon#enter wrdev, iclass 35, count 2 2006.285.12:31:01.99#ibcon#first serial, iclass 35, count 2 2006.285.12:31:01.99#ibcon#enter sib2, iclass 35, count 2 2006.285.12:31:01.99#ibcon#flushed, iclass 35, count 2 2006.285.12:31:01.99#ibcon#about to write, iclass 35, count 2 2006.285.12:31:01.99#ibcon#wrote, iclass 35, count 2 2006.285.12:31:01.99#ibcon#about to read 3, iclass 35, count 2 2006.285.12:31:02.01#ibcon#read 3, iclass 35, count 2 2006.285.12:31:02.01#ibcon#about to read 4, iclass 35, count 2 2006.285.12:31:02.01#ibcon#read 4, iclass 35, count 2 2006.285.12:31:02.01#ibcon#about to read 5, iclass 35, count 2 2006.285.12:31:02.01#ibcon#read 5, iclass 35, count 2 2006.285.12:31:02.01#ibcon#about to read 6, iclass 35, count 2 2006.285.12:31:02.01#ibcon#read 6, iclass 35, count 2 2006.285.12:31:02.01#ibcon#end of sib2, iclass 35, count 2 2006.285.12:31:02.01#ibcon#*mode == 0, iclass 35, count 2 2006.285.12:31:02.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.12:31:02.01#ibcon#[27=AT07-04\r\n] 2006.285.12:31:02.01#ibcon#*before write, iclass 35, count 2 2006.285.12:31:02.01#ibcon#enter sib2, iclass 35, count 2 2006.285.12:31:02.01#ibcon#flushed, iclass 35, count 2 2006.285.12:31:02.01#ibcon#about to write, iclass 35, count 2 2006.285.12:31:02.01#ibcon#wrote, iclass 35, count 2 2006.285.12:31:02.01#ibcon#about to read 3, iclass 35, count 2 2006.285.12:31:02.04#ibcon#read 3, iclass 35, count 2 2006.285.12:31:02.04#ibcon#about to read 4, iclass 35, count 2 2006.285.12:31:02.04#ibcon#read 4, iclass 35, count 2 2006.285.12:31:02.04#ibcon#about to read 5, iclass 35, count 2 2006.285.12:31:02.04#ibcon#read 5, iclass 35, count 2 2006.285.12:31:02.04#ibcon#about to read 6, iclass 35, count 2 2006.285.12:31:02.04#ibcon#read 6, iclass 35, count 2 2006.285.12:31:02.04#ibcon#end of sib2, iclass 35, count 2 2006.285.12:31:02.04#ibcon#*after write, iclass 35, count 2 2006.285.12:31:02.04#ibcon#*before return 0, iclass 35, count 2 2006.285.12:31:02.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:31:02.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:31:02.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.12:31:02.04#ibcon#ireg 7 cls_cnt 0 2006.285.12:31:02.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:31:02.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:31:02.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:31:02.16#ibcon#enter wrdev, iclass 35, count 0 2006.285.12:31:02.16#ibcon#first serial, iclass 35, count 0 2006.285.12:31:02.16#ibcon#enter sib2, iclass 35, count 0 2006.285.12:31:02.16#ibcon#flushed, iclass 35, count 0 2006.285.12:31:02.16#ibcon#about to write, iclass 35, count 0 2006.285.12:31:02.16#ibcon#wrote, iclass 35, count 0 2006.285.12:31:02.16#ibcon#about to read 3, iclass 35, count 0 2006.285.12:31:02.18#ibcon#read 3, iclass 35, count 0 2006.285.12:31:02.18#ibcon#about to read 4, iclass 35, count 0 2006.285.12:31:02.18#ibcon#read 4, iclass 35, count 0 2006.285.12:31:02.18#ibcon#about to read 5, iclass 35, count 0 2006.285.12:31:02.18#ibcon#read 5, iclass 35, count 0 2006.285.12:31:02.18#ibcon#about to read 6, iclass 35, count 0 2006.285.12:31:02.18#ibcon#read 6, iclass 35, count 0 2006.285.12:31:02.18#ibcon#end of sib2, iclass 35, count 0 2006.285.12:31:02.18#ibcon#*mode == 0, iclass 35, count 0 2006.285.12:31:02.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.12:31:02.18#ibcon#[27=USB\r\n] 2006.285.12:31:02.18#ibcon#*before write, iclass 35, count 0 2006.285.12:31:02.18#ibcon#enter sib2, iclass 35, count 0 2006.285.12:31:02.18#ibcon#flushed, iclass 35, count 0 2006.285.12:31:02.18#ibcon#about to write, iclass 35, count 0 2006.285.12:31:02.18#ibcon#wrote, iclass 35, count 0 2006.285.12:31:02.18#ibcon#about to read 3, iclass 35, count 0 2006.285.12:31:02.21#ibcon#read 3, iclass 35, count 0 2006.285.12:31:02.21#ibcon#about to read 4, iclass 35, count 0 2006.285.12:31:02.21#ibcon#read 4, iclass 35, count 0 2006.285.12:31:02.21#ibcon#about to read 5, iclass 35, count 0 2006.285.12:31:02.21#ibcon#read 5, iclass 35, count 0 2006.285.12:31:02.21#ibcon#about to read 6, iclass 35, count 0 2006.285.12:31:02.21#ibcon#read 6, iclass 35, count 0 2006.285.12:31:02.21#ibcon#end of sib2, iclass 35, count 0 2006.285.12:31:02.21#ibcon#*after write, iclass 35, count 0 2006.285.12:31:02.21#ibcon#*before return 0, iclass 35, count 0 2006.285.12:31:02.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:31:02.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:31:02.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.12:31:02.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.12:31:02.21$vck44/vblo=8,744.99 2006.285.12:31:02.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.12:31:02.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.12:31:02.21#ibcon#ireg 17 cls_cnt 0 2006.285.12:31:02.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:31:02.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:31:02.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:31:02.21#ibcon#enter wrdev, iclass 37, count 0 2006.285.12:31:02.21#ibcon#first serial, iclass 37, count 0 2006.285.12:31:02.21#ibcon#enter sib2, iclass 37, count 0 2006.285.12:31:02.21#ibcon#flushed, iclass 37, count 0 2006.285.12:31:02.21#ibcon#about to write, iclass 37, count 0 2006.285.12:31:02.21#ibcon#wrote, iclass 37, count 0 2006.285.12:31:02.21#ibcon#about to read 3, iclass 37, count 0 2006.285.12:31:02.23#ibcon#read 3, iclass 37, count 0 2006.285.12:31:02.23#ibcon#about to read 4, iclass 37, count 0 2006.285.12:31:02.23#ibcon#read 4, iclass 37, count 0 2006.285.12:31:02.23#ibcon#about to read 5, iclass 37, count 0 2006.285.12:31:02.23#ibcon#read 5, iclass 37, count 0 2006.285.12:31:02.23#ibcon#about to read 6, iclass 37, count 0 2006.285.12:31:02.23#ibcon#read 6, iclass 37, count 0 2006.285.12:31:02.23#ibcon#end of sib2, iclass 37, count 0 2006.285.12:31:02.23#ibcon#*mode == 0, iclass 37, count 0 2006.285.12:31:02.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.12:31:02.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.12:31:02.23#ibcon#*before write, iclass 37, count 0 2006.285.12:31:02.23#ibcon#enter sib2, iclass 37, count 0 2006.285.12:31:02.23#ibcon#flushed, iclass 37, count 0 2006.285.12:31:02.23#ibcon#about to write, iclass 37, count 0 2006.285.12:31:02.23#ibcon#wrote, iclass 37, count 0 2006.285.12:31:02.23#ibcon#about to read 3, iclass 37, count 0 2006.285.12:31:02.27#ibcon#read 3, iclass 37, count 0 2006.285.12:31:02.27#ibcon#about to read 4, iclass 37, count 0 2006.285.12:31:02.27#ibcon#read 4, iclass 37, count 0 2006.285.12:31:02.27#ibcon#about to read 5, iclass 37, count 0 2006.285.12:31:02.27#ibcon#read 5, iclass 37, count 0 2006.285.12:31:02.27#ibcon#about to read 6, iclass 37, count 0 2006.285.12:31:02.27#ibcon#read 6, iclass 37, count 0 2006.285.12:31:02.27#ibcon#end of sib2, iclass 37, count 0 2006.285.12:31:02.27#ibcon#*after write, iclass 37, count 0 2006.285.12:31:02.27#ibcon#*before return 0, iclass 37, count 0 2006.285.12:31:02.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:31:02.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:31:02.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.12:31:02.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.12:31:02.27$vck44/vb=8,4 2006.285.12:31:02.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.12:31:02.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.12:31:02.27#ibcon#ireg 11 cls_cnt 2 2006.285.12:31:02.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:31:02.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:31:02.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:31:02.33#ibcon#enter wrdev, iclass 39, count 2 2006.285.12:31:02.33#ibcon#first serial, iclass 39, count 2 2006.285.12:31:02.33#ibcon#enter sib2, iclass 39, count 2 2006.285.12:31:02.33#ibcon#flushed, iclass 39, count 2 2006.285.12:31:02.33#ibcon#about to write, iclass 39, count 2 2006.285.12:31:02.33#ibcon#wrote, iclass 39, count 2 2006.285.12:31:02.33#ibcon#about to read 3, iclass 39, count 2 2006.285.12:31:02.35#ibcon#read 3, iclass 39, count 2 2006.285.12:31:02.35#ibcon#about to read 4, iclass 39, count 2 2006.285.12:31:02.35#ibcon#read 4, iclass 39, count 2 2006.285.12:31:02.35#ibcon#about to read 5, iclass 39, count 2 2006.285.12:31:02.35#ibcon#read 5, iclass 39, count 2 2006.285.12:31:02.35#ibcon#about to read 6, iclass 39, count 2 2006.285.12:31:02.35#ibcon#read 6, iclass 39, count 2 2006.285.12:31:02.35#ibcon#end of sib2, iclass 39, count 2 2006.285.12:31:02.35#ibcon#*mode == 0, iclass 39, count 2 2006.285.12:31:02.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.12:31:02.35#ibcon#[27=AT08-04\r\n] 2006.285.12:31:02.35#ibcon#*before write, iclass 39, count 2 2006.285.12:31:02.35#ibcon#enter sib2, iclass 39, count 2 2006.285.12:31:02.35#ibcon#flushed, iclass 39, count 2 2006.285.12:31:02.35#ibcon#about to write, iclass 39, count 2 2006.285.12:31:02.35#ibcon#wrote, iclass 39, count 2 2006.285.12:31:02.35#ibcon#about to read 3, iclass 39, count 2 2006.285.12:31:02.38#ibcon#read 3, iclass 39, count 2 2006.285.12:31:02.38#ibcon#about to read 4, iclass 39, count 2 2006.285.12:31:02.38#ibcon#read 4, iclass 39, count 2 2006.285.12:31:02.38#ibcon#about to read 5, iclass 39, count 2 2006.285.12:31:02.38#ibcon#read 5, iclass 39, count 2 2006.285.12:31:02.38#ibcon#about to read 6, iclass 39, count 2 2006.285.12:31:02.38#ibcon#read 6, iclass 39, count 2 2006.285.12:31:02.38#ibcon#end of sib2, iclass 39, count 2 2006.285.12:31:02.38#ibcon#*after write, iclass 39, count 2 2006.285.12:31:02.38#ibcon#*before return 0, iclass 39, count 2 2006.285.12:31:02.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:31:02.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:31:02.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.12:31:02.38#ibcon#ireg 7 cls_cnt 0 2006.285.12:31:02.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:31:02.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:31:02.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:31:02.50#ibcon#enter wrdev, iclass 39, count 0 2006.285.12:31:02.50#ibcon#first serial, iclass 39, count 0 2006.285.12:31:02.50#ibcon#enter sib2, iclass 39, count 0 2006.285.12:31:02.50#ibcon#flushed, iclass 39, count 0 2006.285.12:31:02.50#ibcon#about to write, iclass 39, count 0 2006.285.12:31:02.50#ibcon#wrote, iclass 39, count 0 2006.285.12:31:02.50#ibcon#about to read 3, iclass 39, count 0 2006.285.12:31:02.52#ibcon#read 3, iclass 39, count 0 2006.285.12:31:02.52#ibcon#about to read 4, iclass 39, count 0 2006.285.12:31:02.52#ibcon#read 4, iclass 39, count 0 2006.285.12:31:02.52#ibcon#about to read 5, iclass 39, count 0 2006.285.12:31:02.52#ibcon#read 5, iclass 39, count 0 2006.285.12:31:02.52#ibcon#about to read 6, iclass 39, count 0 2006.285.12:31:02.52#ibcon#read 6, iclass 39, count 0 2006.285.12:31:02.52#ibcon#end of sib2, iclass 39, count 0 2006.285.12:31:02.52#ibcon#*mode == 0, iclass 39, count 0 2006.285.12:31:02.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.12:31:02.52#ibcon#[27=USB\r\n] 2006.285.12:31:02.52#ibcon#*before write, iclass 39, count 0 2006.285.12:31:02.52#ibcon#enter sib2, iclass 39, count 0 2006.285.12:31:02.52#ibcon#flushed, iclass 39, count 0 2006.285.12:31:02.52#ibcon#about to write, iclass 39, count 0 2006.285.12:31:02.52#ibcon#wrote, iclass 39, count 0 2006.285.12:31:02.52#ibcon#about to read 3, iclass 39, count 0 2006.285.12:31:02.55#ibcon#read 3, iclass 39, count 0 2006.285.12:31:02.55#ibcon#about to read 4, iclass 39, count 0 2006.285.12:31:02.55#ibcon#read 4, iclass 39, count 0 2006.285.12:31:02.55#ibcon#about to read 5, iclass 39, count 0 2006.285.12:31:02.55#ibcon#read 5, iclass 39, count 0 2006.285.12:31:02.55#ibcon#about to read 6, iclass 39, count 0 2006.285.12:31:02.55#ibcon#read 6, iclass 39, count 0 2006.285.12:31:02.55#ibcon#end of sib2, iclass 39, count 0 2006.285.12:31:02.55#ibcon#*after write, iclass 39, count 0 2006.285.12:31:02.55#ibcon#*before return 0, iclass 39, count 0 2006.285.12:31:02.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:31:02.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:31:02.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.12:31:02.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.12:31:02.55$vck44/vabw=wide 2006.285.12:31:02.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.12:31:02.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.12:31:02.55#ibcon#ireg 8 cls_cnt 0 2006.285.12:31:02.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:31:02.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:31:02.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:31:02.55#ibcon#enter wrdev, iclass 3, count 0 2006.285.12:31:02.55#ibcon#first serial, iclass 3, count 0 2006.285.12:31:02.55#ibcon#enter sib2, iclass 3, count 0 2006.285.12:31:02.55#ibcon#flushed, iclass 3, count 0 2006.285.12:31:02.55#ibcon#about to write, iclass 3, count 0 2006.285.12:31:02.55#ibcon#wrote, iclass 3, count 0 2006.285.12:31:02.55#ibcon#about to read 3, iclass 3, count 0 2006.285.12:31:02.57#ibcon#read 3, iclass 3, count 0 2006.285.12:31:02.57#ibcon#about to read 4, iclass 3, count 0 2006.285.12:31:02.57#ibcon#read 4, iclass 3, count 0 2006.285.12:31:02.57#ibcon#about to read 5, iclass 3, count 0 2006.285.12:31:02.57#ibcon#read 5, iclass 3, count 0 2006.285.12:31:02.57#ibcon#about to read 6, iclass 3, count 0 2006.285.12:31:02.57#ibcon#read 6, iclass 3, count 0 2006.285.12:31:02.57#ibcon#end of sib2, iclass 3, count 0 2006.285.12:31:02.57#ibcon#*mode == 0, iclass 3, count 0 2006.285.12:31:02.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.12:31:02.57#ibcon#[25=BW32\r\n] 2006.285.12:31:02.57#ibcon#*before write, iclass 3, count 0 2006.285.12:31:02.57#ibcon#enter sib2, iclass 3, count 0 2006.285.12:31:02.57#ibcon#flushed, iclass 3, count 0 2006.285.12:31:02.57#ibcon#about to write, iclass 3, count 0 2006.285.12:31:02.57#ibcon#wrote, iclass 3, count 0 2006.285.12:31:02.57#ibcon#about to read 3, iclass 3, count 0 2006.285.12:31:02.60#ibcon#read 3, iclass 3, count 0 2006.285.12:31:02.60#ibcon#about to read 4, iclass 3, count 0 2006.285.12:31:02.60#ibcon#read 4, iclass 3, count 0 2006.285.12:31:02.60#ibcon#about to read 5, iclass 3, count 0 2006.285.12:31:02.60#ibcon#read 5, iclass 3, count 0 2006.285.12:31:02.60#ibcon#about to read 6, iclass 3, count 0 2006.285.12:31:02.60#ibcon#read 6, iclass 3, count 0 2006.285.12:31:02.60#ibcon#end of sib2, iclass 3, count 0 2006.285.12:31:02.60#ibcon#*after write, iclass 3, count 0 2006.285.12:31:02.60#ibcon#*before return 0, iclass 3, count 0 2006.285.12:31:02.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:31:02.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:31:02.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.12:31:02.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.12:31:02.60$vck44/vbbw=wide 2006.285.12:31:02.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.12:31:02.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.12:31:02.60#ibcon#ireg 8 cls_cnt 0 2006.285.12:31:02.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:31:02.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:31:02.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:31:02.67#ibcon#enter wrdev, iclass 5, count 0 2006.285.12:31:02.67#ibcon#first serial, iclass 5, count 0 2006.285.12:31:02.67#ibcon#enter sib2, iclass 5, count 0 2006.285.12:31:02.67#ibcon#flushed, iclass 5, count 0 2006.285.12:31:02.67#ibcon#about to write, iclass 5, count 0 2006.285.12:31:02.67#ibcon#wrote, iclass 5, count 0 2006.285.12:31:02.67#ibcon#about to read 3, iclass 5, count 0 2006.285.12:31:02.69#ibcon#read 3, iclass 5, count 0 2006.285.12:31:02.69#ibcon#about to read 4, iclass 5, count 0 2006.285.12:31:02.69#ibcon#read 4, iclass 5, count 0 2006.285.12:31:02.69#ibcon#about to read 5, iclass 5, count 0 2006.285.12:31:02.69#ibcon#read 5, iclass 5, count 0 2006.285.12:31:02.69#ibcon#about to read 6, iclass 5, count 0 2006.285.12:31:02.69#ibcon#read 6, iclass 5, count 0 2006.285.12:31:02.69#ibcon#end of sib2, iclass 5, count 0 2006.285.12:31:02.69#ibcon#*mode == 0, iclass 5, count 0 2006.285.12:31:02.69#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.12:31:02.69#ibcon#[27=BW32\r\n] 2006.285.12:31:02.69#ibcon#*before write, iclass 5, count 0 2006.285.12:31:02.69#ibcon#enter sib2, iclass 5, count 0 2006.285.12:31:02.69#ibcon#flushed, iclass 5, count 0 2006.285.12:31:02.69#ibcon#about to write, iclass 5, count 0 2006.285.12:31:02.69#ibcon#wrote, iclass 5, count 0 2006.285.12:31:02.69#ibcon#about to read 3, iclass 5, count 0 2006.285.12:31:02.72#ibcon#read 3, iclass 5, count 0 2006.285.12:31:02.72#ibcon#about to read 4, iclass 5, count 0 2006.285.12:31:02.72#ibcon#read 4, iclass 5, count 0 2006.285.12:31:02.72#ibcon#about to read 5, iclass 5, count 0 2006.285.12:31:02.72#ibcon#read 5, iclass 5, count 0 2006.285.12:31:02.72#ibcon#about to read 6, iclass 5, count 0 2006.285.12:31:02.72#ibcon#read 6, iclass 5, count 0 2006.285.12:31:02.72#ibcon#end of sib2, iclass 5, count 0 2006.285.12:31:02.72#ibcon#*after write, iclass 5, count 0 2006.285.12:31:02.72#ibcon#*before return 0, iclass 5, count 0 2006.285.12:31:02.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:31:02.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:31:02.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.12:31:02.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.12:31:02.72$setupk4/ifdk4 2006.285.12:31:02.72$ifdk4/lo= 2006.285.12:31:02.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.12:31:02.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.12:31:02.72$ifdk4/patch= 2006.285.12:31:02.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.12:31:02.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.12:31:02.73$setupk4/!*+20s 2006.285.12:31:04.98#abcon#<5=/05 1.3 2.2 18.77 961015.5\r\n> 2006.285.12:31:05.00#abcon#{5=INTERFACE CLEAR} 2006.285.12:31:05.06#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:31:15.15#abcon#<5=/05 1.3 2.2 18.77 961015.5\r\n> 2006.285.12:31:15.17#abcon#{5=INTERFACE CLEAR} 2006.285.12:31:15.23#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:31:17.14#trakl#Source acquired 2006.285.12:31:17.25$setupk4/"tpicd 2006.285.12:31:17.25$setupk4/echo=off 2006.285.12:31:17.25$setupk4/xlog=off 2006.285.12:31:17.25:!2006.285.12:36:02 2006.285.12:31:18.14#flagr#flagr/antenna,acquired 2006.285.12:36:02.00:preob 2006.285.12:36:02.14/onsource/TRACKING 2006.285.12:36:02.14:!2006.285.12:36:12 2006.285.12:36:12.00:"tape 2006.285.12:36:12.00:"st=record 2006.285.12:36:12.00:data_valid=on 2006.285.12:36:12.00:midob 2006.285.12:36:12.14/onsource/TRACKING 2006.285.12:36:12.14/wx/18.82,1015.4,96 2006.285.12:36:12.27/cable/+6.4942E-03 2006.285.12:36:13.36/va/01,07,usb,yes,31,34 2006.285.12:36:13.36/va/02,06,usb,yes,32,32 2006.285.12:36:13.36/va/03,07,usb,yes,31,33 2006.285.12:36:13.36/va/04,06,usb,yes,33,34 2006.285.12:36:13.36/va/05,03,usb,yes,32,32 2006.285.12:36:13.36/va/06,04,usb,yes,29,28 2006.285.12:36:13.36/va/07,04,usb,yes,29,30 2006.285.12:36:13.36/va/08,03,usb,yes,30,37 2006.285.12:36:13.59/valo/01,524.99,yes,locked 2006.285.12:36:13.59/valo/02,534.99,yes,locked 2006.285.12:36:13.59/valo/03,564.99,yes,locked 2006.285.12:36:13.59/valo/04,624.99,yes,locked 2006.285.12:36:13.59/valo/05,734.99,yes,locked 2006.285.12:36:13.59/valo/06,814.99,yes,locked 2006.285.12:36:13.59/valo/07,864.99,yes,locked 2006.285.12:36:13.59/valo/08,884.99,yes,locked 2006.285.12:36:14.68/vb/01,04,usb,yes,29,27 2006.285.12:36:14.68/vb/02,05,usb,yes,28,28 2006.285.12:36:14.68/vb/03,04,usb,yes,29,32 2006.285.12:36:14.68/vb/04,05,usb,yes,29,28 2006.285.12:36:14.68/vb/05,04,usb,yes,26,28 2006.285.12:36:14.68/vb/06,03,usb,yes,37,33 2006.285.12:36:14.68/vb/07,04,usb,yes,30,30 2006.285.12:36:14.68/vb/08,04,usb,yes,27,30 2006.285.12:36:14.91/vblo/01,629.99,yes,locked 2006.285.12:36:14.91/vblo/02,634.99,yes,locked 2006.285.12:36:14.91/vblo/03,649.99,yes,locked 2006.285.12:36:14.91/vblo/04,679.99,yes,locked 2006.285.12:36:14.91/vblo/05,709.99,yes,locked 2006.285.12:36:14.91/vblo/06,719.99,yes,locked 2006.285.12:36:14.91/vblo/07,734.99,yes,locked 2006.285.12:36:14.91/vblo/08,744.99,yes,locked 2006.285.12:36:15.06/vabw/8 2006.285.12:36:15.21/vbbw/8 2006.285.12:36:15.30/xfe/off,on,12.0 2006.285.12:36:15.67/ifatt/23,28,28,28 2006.285.12:36:16.08/fmout-gps/S +2.57E-07 2006.285.12:36:16.10:!2006.285.12:37:22 2006.285.12:37:22.00:data_valid=off 2006.285.12:37:22.00:"et 2006.285.12:37:22.00:!+3s 2006.285.12:37:25.01:"tape 2006.285.12:37:25.01:postob 2006.285.12:37:25.08/cable/+6.4951E-03 2006.285.12:37:25.08/wx/18.84,1015.4,96 2006.285.12:37:26.07/fmout-gps/S +2.56E-07 2006.285.12:37:26.07:scan_name=285-1245,jd0610,180 2006.285.12:37:26.07:source=1958-179,200057.09,-174857.7,2000.0,ccw 2006.285.12:37:27.13#flagr#flagr/antenna,new-source 2006.285.12:37:27.13:checkk5 2006.285.12:37:27.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.12:37:28.08/chk_autoobs//k5ts2/ autoobs is running! 2006.285.12:37:28.47/chk_autoobs//k5ts3/ autoobs is running! 2006.285.12:37:28.89/chk_autoobs//k5ts4/ autoobs is running! 2006.285.12:37:29.24/chk_obsdata//k5ts1/T2851236??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.12:37:29.64/chk_obsdata//k5ts2/T2851236??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.12:37:30.08/chk_obsdata//k5ts3/T2851236??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.12:37:30.43/chk_obsdata//k5ts4/T2851236??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.12:37:31.39/k5log//k5ts1_log_newline 2006.285.12:37:32.43/k5log//k5ts2_log_newline 2006.285.12:37:33.15/k5log//k5ts3_log_newline 2006.285.12:37:33.93/k5log//k5ts4_log_newline 2006.285.12:37:33.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.12:37:33.95:setupk4=1 2006.285.12:37:33.95$setupk4/echo=on 2006.285.12:37:33.95$setupk4/pcalon 2006.285.12:37:33.95$pcalon/"no phase cal control is implemented here 2006.285.12:37:33.95$setupk4/"tpicd=stop 2006.285.12:37:33.95$setupk4/"rec=synch_on 2006.285.12:37:33.95$setupk4/"rec_mode=128 2006.285.12:37:33.95$setupk4/!* 2006.285.12:37:33.95$setupk4/recpk4 2006.285.12:37:33.95$recpk4/recpatch= 2006.285.12:37:33.95$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.12:37:33.95$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.12:37:33.95$setupk4/vck44 2006.285.12:37:33.95$vck44/valo=1,524.99 2006.285.12:37:33.95#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.12:37:33.95#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.12:37:33.95#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:33.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:37:33.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:37:33.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:37:33.95#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:37:33.95#ibcon#first serial, iclass 15, count 0 2006.285.12:37:33.95#ibcon#enter sib2, iclass 15, count 0 2006.285.12:37:33.95#ibcon#flushed, iclass 15, count 0 2006.285.12:37:33.95#ibcon#about to write, iclass 15, count 0 2006.285.12:37:33.95#ibcon#wrote, iclass 15, count 0 2006.285.12:37:33.95#ibcon#about to read 3, iclass 15, count 0 2006.285.12:37:33.97#ibcon#read 3, iclass 15, count 0 2006.285.12:37:33.97#ibcon#about to read 4, iclass 15, count 0 2006.285.12:37:33.97#ibcon#read 4, iclass 15, count 0 2006.285.12:37:33.97#ibcon#about to read 5, iclass 15, count 0 2006.285.12:37:33.97#ibcon#read 5, iclass 15, count 0 2006.285.12:37:33.97#ibcon#about to read 6, iclass 15, count 0 2006.285.12:37:33.97#ibcon#read 6, iclass 15, count 0 2006.285.12:37:33.97#ibcon#end of sib2, iclass 15, count 0 2006.285.12:37:33.97#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:37:33.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:37:33.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.12:37:33.97#ibcon#*before write, iclass 15, count 0 2006.285.12:37:33.97#ibcon#enter sib2, iclass 15, count 0 2006.285.12:37:33.97#ibcon#flushed, iclass 15, count 0 2006.285.12:37:33.97#ibcon#about to write, iclass 15, count 0 2006.285.12:37:33.97#ibcon#wrote, iclass 15, count 0 2006.285.12:37:33.97#ibcon#about to read 3, iclass 15, count 0 2006.285.12:37:34.02#ibcon#read 3, iclass 15, count 0 2006.285.12:37:34.02#ibcon#about to read 4, iclass 15, count 0 2006.285.12:37:34.02#ibcon#read 4, iclass 15, count 0 2006.285.12:37:34.02#ibcon#about to read 5, iclass 15, count 0 2006.285.12:37:34.02#ibcon#read 5, iclass 15, count 0 2006.285.12:37:34.02#ibcon#about to read 6, iclass 15, count 0 2006.285.12:37:34.02#ibcon#read 6, iclass 15, count 0 2006.285.12:37:34.02#ibcon#end of sib2, iclass 15, count 0 2006.285.12:37:34.02#ibcon#*after write, iclass 15, count 0 2006.285.12:37:34.02#ibcon#*before return 0, iclass 15, count 0 2006.285.12:37:34.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:37:34.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:37:34.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:37:34.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:37:34.02$vck44/va=1,7 2006.285.12:37:34.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.12:37:34.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.12:37:34.02#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:34.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:37:34.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:37:34.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:37:34.02#ibcon#enter wrdev, iclass 17, count 2 2006.285.12:37:34.02#ibcon#first serial, iclass 17, count 2 2006.285.12:37:34.02#ibcon#enter sib2, iclass 17, count 2 2006.285.12:37:34.02#ibcon#flushed, iclass 17, count 2 2006.285.12:37:34.02#ibcon#about to write, iclass 17, count 2 2006.285.12:37:34.02#ibcon#wrote, iclass 17, count 2 2006.285.12:37:34.02#ibcon#about to read 3, iclass 17, count 2 2006.285.12:37:34.04#ibcon#read 3, iclass 17, count 2 2006.285.12:37:34.04#ibcon#about to read 4, iclass 17, count 2 2006.285.12:37:34.04#ibcon#read 4, iclass 17, count 2 2006.285.12:37:34.04#ibcon#about to read 5, iclass 17, count 2 2006.285.12:37:34.04#ibcon#read 5, iclass 17, count 2 2006.285.12:37:34.04#ibcon#about to read 6, iclass 17, count 2 2006.285.12:37:34.04#ibcon#read 6, iclass 17, count 2 2006.285.12:37:34.04#ibcon#end of sib2, iclass 17, count 2 2006.285.12:37:34.04#ibcon#*mode == 0, iclass 17, count 2 2006.285.12:37:34.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.12:37:34.04#ibcon#[25=AT01-07\r\n] 2006.285.12:37:34.04#ibcon#*before write, iclass 17, count 2 2006.285.12:37:34.04#ibcon#enter sib2, iclass 17, count 2 2006.285.12:37:34.04#ibcon#flushed, iclass 17, count 2 2006.285.12:37:34.04#ibcon#about to write, iclass 17, count 2 2006.285.12:37:34.04#ibcon#wrote, iclass 17, count 2 2006.285.12:37:34.04#ibcon#about to read 3, iclass 17, count 2 2006.285.12:37:34.07#ibcon#read 3, iclass 17, count 2 2006.285.12:37:34.07#ibcon#about to read 4, iclass 17, count 2 2006.285.12:37:34.07#ibcon#read 4, iclass 17, count 2 2006.285.12:37:34.07#ibcon#about to read 5, iclass 17, count 2 2006.285.12:37:34.07#ibcon#read 5, iclass 17, count 2 2006.285.12:37:34.07#ibcon#about to read 6, iclass 17, count 2 2006.285.12:37:34.07#ibcon#read 6, iclass 17, count 2 2006.285.12:37:34.07#ibcon#end of sib2, iclass 17, count 2 2006.285.12:37:34.07#ibcon#*after write, iclass 17, count 2 2006.285.12:37:34.07#ibcon#*before return 0, iclass 17, count 2 2006.285.12:37:34.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:37:34.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:37:34.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.12:37:34.07#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:34.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:37:34.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:37:34.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:37:34.19#ibcon#enter wrdev, iclass 17, count 0 2006.285.12:37:34.19#ibcon#first serial, iclass 17, count 0 2006.285.12:37:34.19#ibcon#enter sib2, iclass 17, count 0 2006.285.12:37:34.19#ibcon#flushed, iclass 17, count 0 2006.285.12:37:34.19#ibcon#about to write, iclass 17, count 0 2006.285.12:37:34.19#ibcon#wrote, iclass 17, count 0 2006.285.12:37:34.19#ibcon#about to read 3, iclass 17, count 0 2006.285.12:37:34.21#ibcon#read 3, iclass 17, count 0 2006.285.12:37:34.21#ibcon#about to read 4, iclass 17, count 0 2006.285.12:37:34.21#ibcon#read 4, iclass 17, count 0 2006.285.12:37:34.21#ibcon#about to read 5, iclass 17, count 0 2006.285.12:37:34.21#ibcon#read 5, iclass 17, count 0 2006.285.12:37:34.21#ibcon#about to read 6, iclass 17, count 0 2006.285.12:37:34.21#ibcon#read 6, iclass 17, count 0 2006.285.12:37:34.21#ibcon#end of sib2, iclass 17, count 0 2006.285.12:37:34.21#ibcon#*mode == 0, iclass 17, count 0 2006.285.12:37:34.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.12:37:34.21#ibcon#[25=USB\r\n] 2006.285.12:37:34.21#ibcon#*before write, iclass 17, count 0 2006.285.12:37:34.21#ibcon#enter sib2, iclass 17, count 0 2006.285.12:37:34.21#ibcon#flushed, iclass 17, count 0 2006.285.12:37:34.21#ibcon#about to write, iclass 17, count 0 2006.285.12:37:34.21#ibcon#wrote, iclass 17, count 0 2006.285.12:37:34.21#ibcon#about to read 3, iclass 17, count 0 2006.285.12:37:34.24#ibcon#read 3, iclass 17, count 0 2006.285.12:37:34.24#ibcon#about to read 4, iclass 17, count 0 2006.285.12:37:34.24#ibcon#read 4, iclass 17, count 0 2006.285.12:37:34.24#ibcon#about to read 5, iclass 17, count 0 2006.285.12:37:34.24#ibcon#read 5, iclass 17, count 0 2006.285.12:37:34.24#ibcon#about to read 6, iclass 17, count 0 2006.285.12:37:34.24#ibcon#read 6, iclass 17, count 0 2006.285.12:37:34.24#ibcon#end of sib2, iclass 17, count 0 2006.285.12:37:34.24#ibcon#*after write, iclass 17, count 0 2006.285.12:37:34.24#ibcon#*before return 0, iclass 17, count 0 2006.285.12:37:34.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:37:34.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:37:34.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.12:37:34.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.12:37:34.24$vck44/valo=2,534.99 2006.285.12:37:34.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.12:37:34.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.12:37:34.24#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:34.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:37:34.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:37:34.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:37:34.24#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:37:34.24#ibcon#first serial, iclass 20, count 0 2006.285.12:37:34.24#ibcon#enter sib2, iclass 20, count 0 2006.285.12:37:34.24#ibcon#flushed, iclass 20, count 0 2006.285.12:37:34.24#ibcon#about to write, iclass 20, count 0 2006.285.12:37:34.24#ibcon#wrote, iclass 20, count 0 2006.285.12:37:34.24#ibcon#about to read 3, iclass 20, count 0 2006.285.12:37:34.26#ibcon#read 3, iclass 20, count 0 2006.285.12:37:34.26#ibcon#about to read 4, iclass 20, count 0 2006.285.12:37:34.26#ibcon#read 4, iclass 20, count 0 2006.285.12:37:34.26#ibcon#about to read 5, iclass 20, count 0 2006.285.12:37:34.26#ibcon#read 5, iclass 20, count 0 2006.285.12:37:34.26#ibcon#about to read 6, iclass 20, count 0 2006.285.12:37:34.26#ibcon#read 6, iclass 20, count 0 2006.285.12:37:34.26#ibcon#end of sib2, iclass 20, count 0 2006.285.12:37:34.26#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:37:34.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:37:34.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.12:37:34.26#ibcon#*before write, iclass 20, count 0 2006.285.12:37:34.26#ibcon#enter sib2, iclass 20, count 0 2006.285.12:37:34.26#ibcon#flushed, iclass 20, count 0 2006.285.12:37:34.26#ibcon#about to write, iclass 20, count 0 2006.285.12:37:34.26#ibcon#wrote, iclass 20, count 0 2006.285.12:37:34.26#ibcon#about to read 3, iclass 20, count 0 2006.285.12:37:34.27#abcon#<5=/04 1.4 2.2 18.84 961015.4\r\n> 2006.285.12:37:34.29#abcon#{5=INTERFACE CLEAR} 2006.285.12:37:34.30#ibcon#read 3, iclass 20, count 0 2006.285.12:37:34.30#ibcon#about to read 4, iclass 20, count 0 2006.285.12:37:34.30#ibcon#read 4, iclass 20, count 0 2006.285.12:37:34.30#ibcon#about to read 5, iclass 20, count 0 2006.285.12:37:34.30#ibcon#read 5, iclass 20, count 0 2006.285.12:37:34.30#ibcon#about to read 6, iclass 20, count 0 2006.285.12:37:34.30#ibcon#read 6, iclass 20, count 0 2006.285.12:37:34.30#ibcon#end of sib2, iclass 20, count 0 2006.285.12:37:34.30#ibcon#*after write, iclass 20, count 0 2006.285.12:37:34.30#ibcon#*before return 0, iclass 20, count 0 2006.285.12:37:34.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:37:34.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:37:34.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:37:34.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:37:34.30$vck44/va=2,6 2006.285.12:37:34.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.12:37:34.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.12:37:34.30#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:34.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:37:34.35#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:37:34.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:37:34.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:37:34.36#ibcon#enter wrdev, iclass 24, count 2 2006.285.12:37:34.36#ibcon#first serial, iclass 24, count 2 2006.285.12:37:34.36#ibcon#enter sib2, iclass 24, count 2 2006.285.12:37:34.36#ibcon#flushed, iclass 24, count 2 2006.285.12:37:34.36#ibcon#about to write, iclass 24, count 2 2006.285.12:37:34.36#ibcon#wrote, iclass 24, count 2 2006.285.12:37:34.36#ibcon#about to read 3, iclass 24, count 2 2006.285.12:37:34.38#ibcon#read 3, iclass 24, count 2 2006.285.12:37:34.38#ibcon#about to read 4, iclass 24, count 2 2006.285.12:37:34.38#ibcon#read 4, iclass 24, count 2 2006.285.12:37:34.38#ibcon#about to read 5, iclass 24, count 2 2006.285.12:37:34.38#ibcon#read 5, iclass 24, count 2 2006.285.12:37:34.38#ibcon#about to read 6, iclass 24, count 2 2006.285.12:37:34.38#ibcon#read 6, iclass 24, count 2 2006.285.12:37:34.38#ibcon#end of sib2, iclass 24, count 2 2006.285.12:37:34.38#ibcon#*mode == 0, iclass 24, count 2 2006.285.12:37:34.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.12:37:34.38#ibcon#[25=AT02-06\r\n] 2006.285.12:37:34.38#ibcon#*before write, iclass 24, count 2 2006.285.12:37:34.38#ibcon#enter sib2, iclass 24, count 2 2006.285.12:37:34.38#ibcon#flushed, iclass 24, count 2 2006.285.12:37:34.38#ibcon#about to write, iclass 24, count 2 2006.285.12:37:34.38#ibcon#wrote, iclass 24, count 2 2006.285.12:37:34.38#ibcon#about to read 3, iclass 24, count 2 2006.285.12:37:34.41#ibcon#read 3, iclass 24, count 2 2006.285.12:37:34.41#ibcon#about to read 4, iclass 24, count 2 2006.285.12:37:34.41#ibcon#read 4, iclass 24, count 2 2006.285.12:37:34.41#ibcon#about to read 5, iclass 24, count 2 2006.285.12:37:34.41#ibcon#read 5, iclass 24, count 2 2006.285.12:37:34.41#ibcon#about to read 6, iclass 24, count 2 2006.285.12:37:34.41#ibcon#read 6, iclass 24, count 2 2006.285.12:37:34.41#ibcon#end of sib2, iclass 24, count 2 2006.285.12:37:34.41#ibcon#*after write, iclass 24, count 2 2006.285.12:37:34.41#ibcon#*before return 0, iclass 24, count 2 2006.285.12:37:34.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:37:34.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:37:34.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.12:37:34.41#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:34.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:37:34.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:37:34.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:37:34.53#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:37:34.53#ibcon#first serial, iclass 24, count 0 2006.285.12:37:34.53#ibcon#enter sib2, iclass 24, count 0 2006.285.12:37:34.53#ibcon#flushed, iclass 24, count 0 2006.285.12:37:34.53#ibcon#about to write, iclass 24, count 0 2006.285.12:37:34.53#ibcon#wrote, iclass 24, count 0 2006.285.12:37:34.53#ibcon#about to read 3, iclass 24, count 0 2006.285.12:37:34.55#ibcon#read 3, iclass 24, count 0 2006.285.12:37:34.55#ibcon#about to read 4, iclass 24, count 0 2006.285.12:37:34.55#ibcon#read 4, iclass 24, count 0 2006.285.12:37:34.55#ibcon#about to read 5, iclass 24, count 0 2006.285.12:37:34.55#ibcon#read 5, iclass 24, count 0 2006.285.12:37:34.55#ibcon#about to read 6, iclass 24, count 0 2006.285.12:37:34.55#ibcon#read 6, iclass 24, count 0 2006.285.12:37:34.55#ibcon#end of sib2, iclass 24, count 0 2006.285.12:37:34.55#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:37:34.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:37:34.55#ibcon#[25=USB\r\n] 2006.285.12:37:34.55#ibcon#*before write, iclass 24, count 0 2006.285.12:37:34.55#ibcon#enter sib2, iclass 24, count 0 2006.285.12:37:34.55#ibcon#flushed, iclass 24, count 0 2006.285.12:37:34.55#ibcon#about to write, iclass 24, count 0 2006.285.12:37:34.55#ibcon#wrote, iclass 24, count 0 2006.285.12:37:34.55#ibcon#about to read 3, iclass 24, count 0 2006.285.12:37:34.58#ibcon#read 3, iclass 24, count 0 2006.285.12:37:34.58#ibcon#about to read 4, iclass 24, count 0 2006.285.12:37:34.58#ibcon#read 4, iclass 24, count 0 2006.285.12:37:34.58#ibcon#about to read 5, iclass 24, count 0 2006.285.12:37:34.58#ibcon#read 5, iclass 24, count 0 2006.285.12:37:34.58#ibcon#about to read 6, iclass 24, count 0 2006.285.12:37:34.58#ibcon#read 6, iclass 24, count 0 2006.285.12:37:34.58#ibcon#end of sib2, iclass 24, count 0 2006.285.12:37:34.58#ibcon#*after write, iclass 24, count 0 2006.285.12:37:34.58#ibcon#*before return 0, iclass 24, count 0 2006.285.12:37:34.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:37:34.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:37:34.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:37:34.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:37:34.58$vck44/valo=3,564.99 2006.285.12:37:34.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.12:37:34.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.12:37:34.58#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:34.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:37:34.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:37:34.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:37:34.58#ibcon#enter wrdev, iclass 27, count 0 2006.285.12:37:34.58#ibcon#first serial, iclass 27, count 0 2006.285.12:37:34.58#ibcon#enter sib2, iclass 27, count 0 2006.285.12:37:34.58#ibcon#flushed, iclass 27, count 0 2006.285.12:37:34.58#ibcon#about to write, iclass 27, count 0 2006.285.12:37:34.58#ibcon#wrote, iclass 27, count 0 2006.285.12:37:34.58#ibcon#about to read 3, iclass 27, count 0 2006.285.12:37:34.60#ibcon#read 3, iclass 27, count 0 2006.285.12:37:34.60#ibcon#about to read 4, iclass 27, count 0 2006.285.12:37:34.60#ibcon#read 4, iclass 27, count 0 2006.285.12:37:34.60#ibcon#about to read 5, iclass 27, count 0 2006.285.12:37:34.60#ibcon#read 5, iclass 27, count 0 2006.285.12:37:34.60#ibcon#about to read 6, iclass 27, count 0 2006.285.12:37:34.60#ibcon#read 6, iclass 27, count 0 2006.285.12:37:34.60#ibcon#end of sib2, iclass 27, count 0 2006.285.12:37:34.60#ibcon#*mode == 0, iclass 27, count 0 2006.285.12:37:34.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.12:37:34.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.12:37:34.60#ibcon#*before write, iclass 27, count 0 2006.285.12:37:34.60#ibcon#enter sib2, iclass 27, count 0 2006.285.12:37:34.60#ibcon#flushed, iclass 27, count 0 2006.285.12:37:34.60#ibcon#about to write, iclass 27, count 0 2006.285.12:37:34.60#ibcon#wrote, iclass 27, count 0 2006.285.12:37:34.60#ibcon#about to read 3, iclass 27, count 0 2006.285.12:37:34.64#ibcon#read 3, iclass 27, count 0 2006.285.12:37:34.64#ibcon#about to read 4, iclass 27, count 0 2006.285.12:37:34.64#ibcon#read 4, iclass 27, count 0 2006.285.12:37:34.64#ibcon#about to read 5, iclass 27, count 0 2006.285.12:37:34.64#ibcon#read 5, iclass 27, count 0 2006.285.12:37:34.64#ibcon#about to read 6, iclass 27, count 0 2006.285.12:37:34.64#ibcon#read 6, iclass 27, count 0 2006.285.12:37:34.64#ibcon#end of sib2, iclass 27, count 0 2006.285.12:37:34.64#ibcon#*after write, iclass 27, count 0 2006.285.12:37:34.64#ibcon#*before return 0, iclass 27, count 0 2006.285.12:37:34.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:37:34.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:37:34.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.12:37:34.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.12:37:34.64$vck44/va=3,7 2006.285.12:37:34.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.12:37:34.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.12:37:34.64#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:34.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:37:34.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:37:34.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:37:34.70#ibcon#enter wrdev, iclass 29, count 2 2006.285.12:37:34.70#ibcon#first serial, iclass 29, count 2 2006.285.12:37:34.70#ibcon#enter sib2, iclass 29, count 2 2006.285.12:37:34.70#ibcon#flushed, iclass 29, count 2 2006.285.12:37:34.70#ibcon#about to write, iclass 29, count 2 2006.285.12:37:34.70#ibcon#wrote, iclass 29, count 2 2006.285.12:37:34.70#ibcon#about to read 3, iclass 29, count 2 2006.285.12:37:34.72#ibcon#read 3, iclass 29, count 2 2006.285.12:37:34.72#ibcon#about to read 4, iclass 29, count 2 2006.285.12:37:34.72#ibcon#read 4, iclass 29, count 2 2006.285.12:37:34.72#ibcon#about to read 5, iclass 29, count 2 2006.285.12:37:34.72#ibcon#read 5, iclass 29, count 2 2006.285.12:37:34.72#ibcon#about to read 6, iclass 29, count 2 2006.285.12:37:34.72#ibcon#read 6, iclass 29, count 2 2006.285.12:37:34.72#ibcon#end of sib2, iclass 29, count 2 2006.285.12:37:34.72#ibcon#*mode == 0, iclass 29, count 2 2006.285.12:37:34.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.12:37:34.72#ibcon#[25=AT03-07\r\n] 2006.285.12:37:34.72#ibcon#*before write, iclass 29, count 2 2006.285.12:37:34.72#ibcon#enter sib2, iclass 29, count 2 2006.285.12:37:34.72#ibcon#flushed, iclass 29, count 2 2006.285.12:37:34.72#ibcon#about to write, iclass 29, count 2 2006.285.12:37:34.72#ibcon#wrote, iclass 29, count 2 2006.285.12:37:34.72#ibcon#about to read 3, iclass 29, count 2 2006.285.12:37:34.75#ibcon#read 3, iclass 29, count 2 2006.285.12:37:34.75#ibcon#about to read 4, iclass 29, count 2 2006.285.12:37:34.75#ibcon#read 4, iclass 29, count 2 2006.285.12:37:34.75#ibcon#about to read 5, iclass 29, count 2 2006.285.12:37:34.75#ibcon#read 5, iclass 29, count 2 2006.285.12:37:34.75#ibcon#about to read 6, iclass 29, count 2 2006.285.12:37:34.75#ibcon#read 6, iclass 29, count 2 2006.285.12:37:34.75#ibcon#end of sib2, iclass 29, count 2 2006.285.12:37:34.75#ibcon#*after write, iclass 29, count 2 2006.285.12:37:34.75#ibcon#*before return 0, iclass 29, count 2 2006.285.12:37:34.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:37:34.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:37:34.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.12:37:34.75#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:34.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:37:34.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:37:35.28#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:37:35.28#ibcon#enter wrdev, iclass 29, count 0 2006.285.12:37:35.28#ibcon#first serial, iclass 29, count 0 2006.285.12:37:35.28#ibcon#enter sib2, iclass 29, count 0 2006.285.12:37:35.28#ibcon#flushed, iclass 29, count 0 2006.285.12:37:35.28#ibcon#about to write, iclass 29, count 0 2006.285.12:37:35.28#ibcon#wrote, iclass 29, count 0 2006.285.12:37:35.28#ibcon#about to read 3, iclass 29, count 0 2006.285.12:37:35.29#ibcon#read 3, iclass 29, count 0 2006.285.12:37:35.29#ibcon#about to read 4, iclass 29, count 0 2006.285.12:37:35.29#ibcon#read 4, iclass 29, count 0 2006.285.12:37:35.29#ibcon#about to read 5, iclass 29, count 0 2006.285.12:37:35.29#ibcon#read 5, iclass 29, count 0 2006.285.12:37:35.29#ibcon#about to read 6, iclass 29, count 0 2006.285.12:37:35.29#ibcon#read 6, iclass 29, count 0 2006.285.12:37:35.29#ibcon#end of sib2, iclass 29, count 0 2006.285.12:37:35.29#ibcon#*mode == 0, iclass 29, count 0 2006.285.12:37:35.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.12:37:35.29#ibcon#[25=USB\r\n] 2006.285.12:37:35.29#ibcon#*before write, iclass 29, count 0 2006.285.12:37:35.29#ibcon#enter sib2, iclass 29, count 0 2006.285.12:37:35.29#ibcon#flushed, iclass 29, count 0 2006.285.12:37:35.29#ibcon#about to write, iclass 29, count 0 2006.285.12:37:35.29#ibcon#wrote, iclass 29, count 0 2006.285.12:37:35.29#ibcon#about to read 3, iclass 29, count 0 2006.285.12:37:35.32#ibcon#read 3, iclass 29, count 0 2006.285.12:37:35.32#ibcon#about to read 4, iclass 29, count 0 2006.285.12:37:35.32#ibcon#read 4, iclass 29, count 0 2006.285.12:37:35.32#ibcon#about to read 5, iclass 29, count 0 2006.285.12:37:35.32#ibcon#read 5, iclass 29, count 0 2006.285.12:37:35.32#ibcon#about to read 6, iclass 29, count 0 2006.285.12:37:35.32#ibcon#read 6, iclass 29, count 0 2006.285.12:37:35.32#ibcon#end of sib2, iclass 29, count 0 2006.285.12:37:35.32#ibcon#*after write, iclass 29, count 0 2006.285.12:37:35.32#ibcon#*before return 0, iclass 29, count 0 2006.285.12:37:35.32#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:37:35.32#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:37:35.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.12:37:35.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.12:37:35.32$vck44/valo=4,624.99 2006.285.12:37:35.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.12:37:35.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.12:37:35.32#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:35.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:37:35.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:37:35.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:37:35.32#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:37:35.32#ibcon#first serial, iclass 31, count 0 2006.285.12:37:35.32#ibcon#enter sib2, iclass 31, count 0 2006.285.12:37:35.32#ibcon#flushed, iclass 31, count 0 2006.285.12:37:35.32#ibcon#about to write, iclass 31, count 0 2006.285.12:37:35.32#ibcon#wrote, iclass 31, count 0 2006.285.12:37:35.32#ibcon#about to read 3, iclass 31, count 0 2006.285.12:37:35.34#ibcon#read 3, iclass 31, count 0 2006.285.12:37:35.34#ibcon#about to read 4, iclass 31, count 0 2006.285.12:37:35.34#ibcon#read 4, iclass 31, count 0 2006.285.12:37:35.34#ibcon#about to read 5, iclass 31, count 0 2006.285.12:37:35.34#ibcon#read 5, iclass 31, count 0 2006.285.12:37:35.34#ibcon#about to read 6, iclass 31, count 0 2006.285.12:37:35.34#ibcon#read 6, iclass 31, count 0 2006.285.12:37:35.34#ibcon#end of sib2, iclass 31, count 0 2006.285.12:37:35.34#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:37:35.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:37:35.34#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.12:37:35.34#ibcon#*before write, iclass 31, count 0 2006.285.12:37:35.34#ibcon#enter sib2, iclass 31, count 0 2006.285.12:37:35.34#ibcon#flushed, iclass 31, count 0 2006.285.12:37:35.34#ibcon#about to write, iclass 31, count 0 2006.285.12:37:35.34#ibcon#wrote, iclass 31, count 0 2006.285.12:37:35.34#ibcon#about to read 3, iclass 31, count 0 2006.285.12:37:35.38#ibcon#read 3, iclass 31, count 0 2006.285.12:37:35.38#ibcon#about to read 4, iclass 31, count 0 2006.285.12:37:35.38#ibcon#read 4, iclass 31, count 0 2006.285.12:37:35.38#ibcon#about to read 5, iclass 31, count 0 2006.285.12:37:35.38#ibcon#read 5, iclass 31, count 0 2006.285.12:37:35.38#ibcon#about to read 6, iclass 31, count 0 2006.285.12:37:35.38#ibcon#read 6, iclass 31, count 0 2006.285.12:37:35.38#ibcon#end of sib2, iclass 31, count 0 2006.285.12:37:35.38#ibcon#*after write, iclass 31, count 0 2006.285.12:37:35.38#ibcon#*before return 0, iclass 31, count 0 2006.285.12:37:35.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:37:35.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:37:35.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:37:35.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:37:35.38$vck44/va=4,6 2006.285.12:37:35.38#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.12:37:35.38#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.12:37:35.38#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:35.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:37:35.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:37:35.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:37:35.44#ibcon#enter wrdev, iclass 33, count 2 2006.285.12:37:35.44#ibcon#first serial, iclass 33, count 2 2006.285.12:37:35.44#ibcon#enter sib2, iclass 33, count 2 2006.285.12:37:35.44#ibcon#flushed, iclass 33, count 2 2006.285.12:37:35.44#ibcon#about to write, iclass 33, count 2 2006.285.12:37:35.44#ibcon#wrote, iclass 33, count 2 2006.285.12:37:35.44#ibcon#about to read 3, iclass 33, count 2 2006.285.12:37:35.46#ibcon#read 3, iclass 33, count 2 2006.285.12:37:35.46#ibcon#about to read 4, iclass 33, count 2 2006.285.12:37:35.46#ibcon#read 4, iclass 33, count 2 2006.285.12:37:35.46#ibcon#about to read 5, iclass 33, count 2 2006.285.12:37:35.46#ibcon#read 5, iclass 33, count 2 2006.285.12:37:35.46#ibcon#about to read 6, iclass 33, count 2 2006.285.12:37:35.46#ibcon#read 6, iclass 33, count 2 2006.285.12:37:35.46#ibcon#end of sib2, iclass 33, count 2 2006.285.12:37:35.46#ibcon#*mode == 0, iclass 33, count 2 2006.285.12:37:35.46#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.12:37:35.46#ibcon#[25=AT04-06\r\n] 2006.285.12:37:35.46#ibcon#*before write, iclass 33, count 2 2006.285.12:37:35.46#ibcon#enter sib2, iclass 33, count 2 2006.285.12:37:35.46#ibcon#flushed, iclass 33, count 2 2006.285.12:37:35.46#ibcon#about to write, iclass 33, count 2 2006.285.12:37:35.46#ibcon#wrote, iclass 33, count 2 2006.285.12:37:35.46#ibcon#about to read 3, iclass 33, count 2 2006.285.12:37:35.49#ibcon#read 3, iclass 33, count 2 2006.285.12:37:35.49#ibcon#about to read 4, iclass 33, count 2 2006.285.12:37:35.49#ibcon#read 4, iclass 33, count 2 2006.285.12:37:35.49#ibcon#about to read 5, iclass 33, count 2 2006.285.12:37:35.49#ibcon#read 5, iclass 33, count 2 2006.285.12:37:35.49#ibcon#about to read 6, iclass 33, count 2 2006.285.12:37:35.49#ibcon#read 6, iclass 33, count 2 2006.285.12:37:35.49#ibcon#end of sib2, iclass 33, count 2 2006.285.12:37:35.49#ibcon#*after write, iclass 33, count 2 2006.285.12:37:35.49#ibcon#*before return 0, iclass 33, count 2 2006.285.12:37:35.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:37:35.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:37:35.49#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.12:37:35.49#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:35.49#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:37:35.61#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:37:35.61#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:37:35.61#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:37:35.61#ibcon#first serial, iclass 33, count 0 2006.285.12:37:35.61#ibcon#enter sib2, iclass 33, count 0 2006.285.12:37:35.61#ibcon#flushed, iclass 33, count 0 2006.285.12:37:35.61#ibcon#about to write, iclass 33, count 0 2006.285.12:37:35.61#ibcon#wrote, iclass 33, count 0 2006.285.12:37:35.61#ibcon#about to read 3, iclass 33, count 0 2006.285.12:37:35.63#ibcon#read 3, iclass 33, count 0 2006.285.12:37:35.63#ibcon#about to read 4, iclass 33, count 0 2006.285.12:37:35.63#ibcon#read 4, iclass 33, count 0 2006.285.12:37:35.63#ibcon#about to read 5, iclass 33, count 0 2006.285.12:37:35.63#ibcon#read 5, iclass 33, count 0 2006.285.12:37:35.63#ibcon#about to read 6, iclass 33, count 0 2006.285.12:37:35.63#ibcon#read 6, iclass 33, count 0 2006.285.12:37:35.63#ibcon#end of sib2, iclass 33, count 0 2006.285.12:37:35.63#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:37:35.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:37:35.63#ibcon#[25=USB\r\n] 2006.285.12:37:35.63#ibcon#*before write, iclass 33, count 0 2006.285.12:37:35.63#ibcon#enter sib2, iclass 33, count 0 2006.285.12:37:35.63#ibcon#flushed, iclass 33, count 0 2006.285.12:37:35.63#ibcon#about to write, iclass 33, count 0 2006.285.12:37:35.63#ibcon#wrote, iclass 33, count 0 2006.285.12:37:35.63#ibcon#about to read 3, iclass 33, count 0 2006.285.12:37:35.66#ibcon#read 3, iclass 33, count 0 2006.285.12:37:35.66#ibcon#about to read 4, iclass 33, count 0 2006.285.12:37:35.66#ibcon#read 4, iclass 33, count 0 2006.285.12:37:35.66#ibcon#about to read 5, iclass 33, count 0 2006.285.12:37:35.66#ibcon#read 5, iclass 33, count 0 2006.285.12:37:35.66#ibcon#about to read 6, iclass 33, count 0 2006.285.12:37:35.66#ibcon#read 6, iclass 33, count 0 2006.285.12:37:35.66#ibcon#end of sib2, iclass 33, count 0 2006.285.12:37:35.66#ibcon#*after write, iclass 33, count 0 2006.285.12:37:35.66#ibcon#*before return 0, iclass 33, count 0 2006.285.12:37:35.66#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:37:35.66#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:37:35.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:37:35.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:37:35.66$vck44/valo=5,734.99 2006.285.12:37:35.66#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.12:37:35.66#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.12:37:35.66#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:35.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:37:35.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:37:35.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:37:35.66#ibcon#enter wrdev, iclass 35, count 0 2006.285.12:37:35.66#ibcon#first serial, iclass 35, count 0 2006.285.12:37:35.66#ibcon#enter sib2, iclass 35, count 0 2006.285.12:37:35.66#ibcon#flushed, iclass 35, count 0 2006.285.12:37:35.66#ibcon#about to write, iclass 35, count 0 2006.285.12:37:35.66#ibcon#wrote, iclass 35, count 0 2006.285.12:37:35.66#ibcon#about to read 3, iclass 35, count 0 2006.285.12:37:35.68#ibcon#read 3, iclass 35, count 0 2006.285.12:37:36.01#ibcon#about to read 4, iclass 35, count 0 2006.285.12:37:36.01#ibcon#read 4, iclass 35, count 0 2006.285.12:37:36.01#ibcon#about to read 5, iclass 35, count 0 2006.285.12:37:36.01#ibcon#read 5, iclass 35, count 0 2006.285.12:37:36.01#ibcon#about to read 6, iclass 35, count 0 2006.285.12:37:36.01#ibcon#read 6, iclass 35, count 0 2006.285.12:37:36.01#ibcon#end of sib2, iclass 35, count 0 2006.285.12:37:36.01#ibcon#*mode == 0, iclass 35, count 0 2006.285.12:37:36.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.12:37:36.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.12:37:36.01#ibcon#*before write, iclass 35, count 0 2006.285.12:37:36.01#ibcon#enter sib2, iclass 35, count 0 2006.285.12:37:36.01#ibcon#flushed, iclass 35, count 0 2006.285.12:37:36.01#ibcon#about to write, iclass 35, count 0 2006.285.12:37:36.01#ibcon#wrote, iclass 35, count 0 2006.285.12:37:36.01#ibcon#about to read 3, iclass 35, count 0 2006.285.12:37:36.05#ibcon#read 3, iclass 35, count 0 2006.285.12:37:36.05#ibcon#about to read 4, iclass 35, count 0 2006.285.12:37:36.05#ibcon#read 4, iclass 35, count 0 2006.285.12:37:36.05#ibcon#about to read 5, iclass 35, count 0 2006.285.12:37:36.05#ibcon#read 5, iclass 35, count 0 2006.285.12:37:36.05#ibcon#about to read 6, iclass 35, count 0 2006.285.12:37:36.05#ibcon#read 6, iclass 35, count 0 2006.285.12:37:36.05#ibcon#end of sib2, iclass 35, count 0 2006.285.12:37:36.05#ibcon#*after write, iclass 35, count 0 2006.285.12:37:36.05#ibcon#*before return 0, iclass 35, count 0 2006.285.12:37:36.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:37:36.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:37:36.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.12:37:36.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.12:37:36.05$vck44/va=5,3 2006.285.12:37:36.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.12:37:36.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.12:37:36.05#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:36.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:37:36.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:37:36.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:37:36.05#ibcon#enter wrdev, iclass 37, count 2 2006.285.12:37:36.05#ibcon#first serial, iclass 37, count 2 2006.285.12:37:36.05#ibcon#enter sib2, iclass 37, count 2 2006.285.12:37:36.05#ibcon#flushed, iclass 37, count 2 2006.285.12:37:36.05#ibcon#about to write, iclass 37, count 2 2006.285.12:37:36.05#ibcon#wrote, iclass 37, count 2 2006.285.12:37:36.05#ibcon#about to read 3, iclass 37, count 2 2006.285.12:37:36.07#ibcon#read 3, iclass 37, count 2 2006.285.12:37:36.07#ibcon#about to read 4, iclass 37, count 2 2006.285.12:37:36.07#ibcon#read 4, iclass 37, count 2 2006.285.12:37:36.07#ibcon#about to read 5, iclass 37, count 2 2006.285.12:37:36.07#ibcon#read 5, iclass 37, count 2 2006.285.12:37:36.07#ibcon#about to read 6, iclass 37, count 2 2006.285.12:37:36.07#ibcon#read 6, iclass 37, count 2 2006.285.12:37:36.07#ibcon#end of sib2, iclass 37, count 2 2006.285.12:37:36.07#ibcon#*mode == 0, iclass 37, count 2 2006.285.12:37:36.07#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.12:37:36.07#ibcon#[25=AT05-03\r\n] 2006.285.12:37:36.07#ibcon#*before write, iclass 37, count 2 2006.285.12:37:36.07#ibcon#enter sib2, iclass 37, count 2 2006.285.12:37:36.07#ibcon#flushed, iclass 37, count 2 2006.285.12:37:36.07#ibcon#about to write, iclass 37, count 2 2006.285.12:37:36.07#ibcon#wrote, iclass 37, count 2 2006.285.12:37:36.07#ibcon#about to read 3, iclass 37, count 2 2006.285.12:37:36.10#ibcon#read 3, iclass 37, count 2 2006.285.12:37:36.10#ibcon#about to read 4, iclass 37, count 2 2006.285.12:37:36.10#ibcon#read 4, iclass 37, count 2 2006.285.12:37:36.10#ibcon#about to read 5, iclass 37, count 2 2006.285.12:37:36.10#ibcon#read 5, iclass 37, count 2 2006.285.12:37:36.10#ibcon#about to read 6, iclass 37, count 2 2006.285.12:37:36.10#ibcon#read 6, iclass 37, count 2 2006.285.12:37:36.10#ibcon#end of sib2, iclass 37, count 2 2006.285.12:37:36.10#ibcon#*after write, iclass 37, count 2 2006.285.12:37:36.10#ibcon#*before return 0, iclass 37, count 2 2006.285.12:37:36.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:37:36.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:37:36.10#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.12:37:36.10#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:36.10#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:37:36.22#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:37:36.22#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:37:36.22#ibcon#enter wrdev, iclass 37, count 0 2006.285.12:37:36.22#ibcon#first serial, iclass 37, count 0 2006.285.12:37:36.22#ibcon#enter sib2, iclass 37, count 0 2006.285.12:37:36.22#ibcon#flushed, iclass 37, count 0 2006.285.12:37:36.22#ibcon#about to write, iclass 37, count 0 2006.285.12:37:36.22#ibcon#wrote, iclass 37, count 0 2006.285.12:37:36.22#ibcon#about to read 3, iclass 37, count 0 2006.285.12:37:36.24#ibcon#read 3, iclass 37, count 0 2006.285.12:37:36.24#ibcon#about to read 4, iclass 37, count 0 2006.285.12:37:36.24#ibcon#read 4, iclass 37, count 0 2006.285.12:37:36.24#ibcon#about to read 5, iclass 37, count 0 2006.285.12:37:36.24#ibcon#read 5, iclass 37, count 0 2006.285.12:37:36.24#ibcon#about to read 6, iclass 37, count 0 2006.285.12:37:36.24#ibcon#read 6, iclass 37, count 0 2006.285.12:37:36.24#ibcon#end of sib2, iclass 37, count 0 2006.285.12:37:36.24#ibcon#*mode == 0, iclass 37, count 0 2006.285.12:37:36.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.12:37:36.24#ibcon#[25=USB\r\n] 2006.285.12:37:36.24#ibcon#*before write, iclass 37, count 0 2006.285.12:37:36.24#ibcon#enter sib2, iclass 37, count 0 2006.285.12:37:36.24#ibcon#flushed, iclass 37, count 0 2006.285.12:37:36.24#ibcon#about to write, iclass 37, count 0 2006.285.12:37:36.24#ibcon#wrote, iclass 37, count 0 2006.285.12:37:36.24#ibcon#about to read 3, iclass 37, count 0 2006.285.12:37:36.27#ibcon#read 3, iclass 37, count 0 2006.285.12:37:36.27#ibcon#about to read 4, iclass 37, count 0 2006.285.12:37:36.27#ibcon#read 4, iclass 37, count 0 2006.285.12:37:36.27#ibcon#about to read 5, iclass 37, count 0 2006.285.12:37:36.27#ibcon#read 5, iclass 37, count 0 2006.285.12:37:36.27#ibcon#about to read 6, iclass 37, count 0 2006.285.12:37:36.27#ibcon#read 6, iclass 37, count 0 2006.285.12:37:36.27#ibcon#end of sib2, iclass 37, count 0 2006.285.12:37:36.27#ibcon#*after write, iclass 37, count 0 2006.285.12:37:36.27#ibcon#*before return 0, iclass 37, count 0 2006.285.12:37:36.27#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:37:36.27#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:37:36.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.12:37:36.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.12:37:36.27$vck44/valo=6,814.99 2006.285.12:37:36.27#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.12:37:36.27#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.12:37:36.27#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:36.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:37:36.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:37:36.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:37:36.27#ibcon#enter wrdev, iclass 39, count 0 2006.285.12:37:36.27#ibcon#first serial, iclass 39, count 0 2006.285.12:37:36.27#ibcon#enter sib2, iclass 39, count 0 2006.285.12:37:36.27#ibcon#flushed, iclass 39, count 0 2006.285.12:37:36.27#ibcon#about to write, iclass 39, count 0 2006.285.12:37:36.27#ibcon#wrote, iclass 39, count 0 2006.285.12:37:36.27#ibcon#about to read 3, iclass 39, count 0 2006.285.12:37:36.29#ibcon#read 3, iclass 39, count 0 2006.285.12:37:36.29#ibcon#about to read 4, iclass 39, count 0 2006.285.12:37:36.29#ibcon#read 4, iclass 39, count 0 2006.285.12:37:36.29#ibcon#about to read 5, iclass 39, count 0 2006.285.12:37:36.29#ibcon#read 5, iclass 39, count 0 2006.285.12:37:36.29#ibcon#about to read 6, iclass 39, count 0 2006.285.12:37:36.29#ibcon#read 6, iclass 39, count 0 2006.285.12:37:36.29#ibcon#end of sib2, iclass 39, count 0 2006.285.12:37:36.29#ibcon#*mode == 0, iclass 39, count 0 2006.285.12:37:36.29#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.12:37:36.29#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.12:37:36.29#ibcon#*before write, iclass 39, count 0 2006.285.12:37:36.29#ibcon#enter sib2, iclass 39, count 0 2006.285.12:37:36.29#ibcon#flushed, iclass 39, count 0 2006.285.12:37:36.29#ibcon#about to write, iclass 39, count 0 2006.285.12:37:36.29#ibcon#wrote, iclass 39, count 0 2006.285.12:37:36.29#ibcon#about to read 3, iclass 39, count 0 2006.285.12:37:36.33#ibcon#read 3, iclass 39, count 0 2006.285.12:37:36.33#ibcon#about to read 4, iclass 39, count 0 2006.285.12:37:36.33#ibcon#read 4, iclass 39, count 0 2006.285.12:37:36.33#ibcon#about to read 5, iclass 39, count 0 2006.285.12:37:36.33#ibcon#read 5, iclass 39, count 0 2006.285.12:37:36.33#ibcon#about to read 6, iclass 39, count 0 2006.285.12:37:36.33#ibcon#read 6, iclass 39, count 0 2006.285.12:37:36.33#ibcon#end of sib2, iclass 39, count 0 2006.285.12:37:36.33#ibcon#*after write, iclass 39, count 0 2006.285.12:37:36.33#ibcon#*before return 0, iclass 39, count 0 2006.285.12:37:36.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:37:36.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:37:36.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.12:37:36.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.12:37:36.33$vck44/va=6,4 2006.285.12:37:36.33#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.12:37:36.33#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.12:37:36.33#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:36.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:37:36.39#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:37:36.39#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:37:36.39#ibcon#enter wrdev, iclass 3, count 2 2006.285.12:37:36.39#ibcon#first serial, iclass 3, count 2 2006.285.12:37:36.39#ibcon#enter sib2, iclass 3, count 2 2006.285.12:37:36.39#ibcon#flushed, iclass 3, count 2 2006.285.12:37:36.39#ibcon#about to write, iclass 3, count 2 2006.285.12:37:36.39#ibcon#wrote, iclass 3, count 2 2006.285.12:37:36.39#ibcon#about to read 3, iclass 3, count 2 2006.285.12:37:36.41#ibcon#read 3, iclass 3, count 2 2006.285.12:37:36.41#ibcon#about to read 4, iclass 3, count 2 2006.285.12:37:36.41#ibcon#read 4, iclass 3, count 2 2006.285.12:37:36.41#ibcon#about to read 5, iclass 3, count 2 2006.285.12:37:36.41#ibcon#read 5, iclass 3, count 2 2006.285.12:37:36.41#ibcon#about to read 6, iclass 3, count 2 2006.285.12:37:36.41#ibcon#read 6, iclass 3, count 2 2006.285.12:37:36.41#ibcon#end of sib2, iclass 3, count 2 2006.285.12:37:36.41#ibcon#*mode == 0, iclass 3, count 2 2006.285.12:37:36.41#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.12:37:36.41#ibcon#[25=AT06-04\r\n] 2006.285.12:37:36.41#ibcon#*before write, iclass 3, count 2 2006.285.12:37:36.41#ibcon#enter sib2, iclass 3, count 2 2006.285.12:37:36.41#ibcon#flushed, iclass 3, count 2 2006.285.12:37:36.41#ibcon#about to write, iclass 3, count 2 2006.285.12:37:36.41#ibcon#wrote, iclass 3, count 2 2006.285.12:37:36.41#ibcon#about to read 3, iclass 3, count 2 2006.285.12:37:36.44#ibcon#read 3, iclass 3, count 2 2006.285.12:37:36.44#ibcon#about to read 4, iclass 3, count 2 2006.285.12:37:36.44#ibcon#read 4, iclass 3, count 2 2006.285.12:37:36.44#ibcon#about to read 5, iclass 3, count 2 2006.285.12:37:36.44#ibcon#read 5, iclass 3, count 2 2006.285.12:37:36.44#ibcon#about to read 6, iclass 3, count 2 2006.285.12:37:36.44#ibcon#read 6, iclass 3, count 2 2006.285.12:37:36.44#ibcon#end of sib2, iclass 3, count 2 2006.285.12:37:36.44#ibcon#*after write, iclass 3, count 2 2006.285.12:37:36.44#ibcon#*before return 0, iclass 3, count 2 2006.285.12:37:36.44#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:37:36.44#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:37:36.44#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.12:37:36.44#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:36.44#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:37:36.56#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:37:36.56#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:37:36.56#ibcon#enter wrdev, iclass 3, count 0 2006.285.12:37:36.56#ibcon#first serial, iclass 3, count 0 2006.285.12:37:36.56#ibcon#enter sib2, iclass 3, count 0 2006.285.12:37:36.56#ibcon#flushed, iclass 3, count 0 2006.285.12:37:36.56#ibcon#about to write, iclass 3, count 0 2006.285.12:37:36.56#ibcon#wrote, iclass 3, count 0 2006.285.12:37:36.56#ibcon#about to read 3, iclass 3, count 0 2006.285.12:37:36.58#ibcon#read 3, iclass 3, count 0 2006.285.12:37:36.58#ibcon#about to read 4, iclass 3, count 0 2006.285.12:37:36.58#ibcon#read 4, iclass 3, count 0 2006.285.12:37:36.58#ibcon#about to read 5, iclass 3, count 0 2006.285.12:37:36.58#ibcon#read 5, iclass 3, count 0 2006.285.12:37:36.58#ibcon#about to read 6, iclass 3, count 0 2006.285.12:37:36.58#ibcon#read 6, iclass 3, count 0 2006.285.12:37:36.58#ibcon#end of sib2, iclass 3, count 0 2006.285.12:37:36.58#ibcon#*mode == 0, iclass 3, count 0 2006.285.12:37:36.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.12:37:36.58#ibcon#[25=USB\r\n] 2006.285.12:37:36.58#ibcon#*before write, iclass 3, count 0 2006.285.12:37:36.58#ibcon#enter sib2, iclass 3, count 0 2006.285.12:37:36.58#ibcon#flushed, iclass 3, count 0 2006.285.12:37:36.58#ibcon#about to write, iclass 3, count 0 2006.285.12:37:36.58#ibcon#wrote, iclass 3, count 0 2006.285.12:37:36.58#ibcon#about to read 3, iclass 3, count 0 2006.285.12:37:36.61#ibcon#read 3, iclass 3, count 0 2006.285.12:37:36.61#ibcon#about to read 4, iclass 3, count 0 2006.285.12:37:36.61#ibcon#read 4, iclass 3, count 0 2006.285.12:37:36.61#ibcon#about to read 5, iclass 3, count 0 2006.285.12:37:36.61#ibcon#read 5, iclass 3, count 0 2006.285.12:37:36.61#ibcon#about to read 6, iclass 3, count 0 2006.285.12:37:36.61#ibcon#read 6, iclass 3, count 0 2006.285.12:37:36.61#ibcon#end of sib2, iclass 3, count 0 2006.285.12:37:36.61#ibcon#*after write, iclass 3, count 0 2006.285.12:37:36.61#ibcon#*before return 0, iclass 3, count 0 2006.285.12:37:36.61#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:37:36.61#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:37:36.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.12:37:36.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.12:37:36.61$vck44/valo=7,864.99 2006.285.12:37:36.61#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.12:37:36.61#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.12:37:36.61#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:36.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:37:36.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:37:36.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:37:36.61#ibcon#enter wrdev, iclass 5, count 0 2006.285.12:37:36.61#ibcon#first serial, iclass 5, count 0 2006.285.12:37:36.61#ibcon#enter sib2, iclass 5, count 0 2006.285.12:37:36.61#ibcon#flushed, iclass 5, count 0 2006.285.12:37:36.61#ibcon#about to write, iclass 5, count 0 2006.285.12:37:36.61#ibcon#wrote, iclass 5, count 0 2006.285.12:37:36.61#ibcon#about to read 3, iclass 5, count 0 2006.285.12:37:36.63#ibcon#read 3, iclass 5, count 0 2006.285.12:37:36.63#ibcon#about to read 4, iclass 5, count 0 2006.285.12:37:36.63#ibcon#read 4, iclass 5, count 0 2006.285.12:37:36.63#ibcon#about to read 5, iclass 5, count 0 2006.285.12:37:36.63#ibcon#read 5, iclass 5, count 0 2006.285.12:37:36.63#ibcon#about to read 6, iclass 5, count 0 2006.285.12:37:36.63#ibcon#read 6, iclass 5, count 0 2006.285.12:37:36.63#ibcon#end of sib2, iclass 5, count 0 2006.285.12:37:36.63#ibcon#*mode == 0, iclass 5, count 0 2006.285.12:37:36.63#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.12:37:36.63#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.12:37:36.63#ibcon#*before write, iclass 5, count 0 2006.285.12:37:36.63#ibcon#enter sib2, iclass 5, count 0 2006.285.12:37:36.63#ibcon#flushed, iclass 5, count 0 2006.285.12:37:36.63#ibcon#about to write, iclass 5, count 0 2006.285.12:37:36.63#ibcon#wrote, iclass 5, count 0 2006.285.12:37:36.63#ibcon#about to read 3, iclass 5, count 0 2006.285.12:37:36.67#ibcon#read 3, iclass 5, count 0 2006.285.12:37:36.67#ibcon#about to read 4, iclass 5, count 0 2006.285.12:37:36.67#ibcon#read 4, iclass 5, count 0 2006.285.12:37:36.67#ibcon#about to read 5, iclass 5, count 0 2006.285.12:37:36.67#ibcon#read 5, iclass 5, count 0 2006.285.12:37:36.67#ibcon#about to read 6, iclass 5, count 0 2006.285.12:37:36.67#ibcon#read 6, iclass 5, count 0 2006.285.12:37:36.67#ibcon#end of sib2, iclass 5, count 0 2006.285.12:37:36.67#ibcon#*after write, iclass 5, count 0 2006.285.12:37:36.67#ibcon#*before return 0, iclass 5, count 0 2006.285.12:37:36.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:37:36.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:37:36.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.12:37:36.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.12:37:36.67$vck44/va=7,4 2006.285.12:37:36.67#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.12:37:36.67#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.12:37:36.67#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:36.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:37:36.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:37:36.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:37:36.73#ibcon#enter wrdev, iclass 7, count 2 2006.285.12:37:36.73#ibcon#first serial, iclass 7, count 2 2006.285.12:37:36.73#ibcon#enter sib2, iclass 7, count 2 2006.285.12:37:36.73#ibcon#flushed, iclass 7, count 2 2006.285.12:37:36.73#ibcon#about to write, iclass 7, count 2 2006.285.12:37:36.73#ibcon#wrote, iclass 7, count 2 2006.285.12:37:36.73#ibcon#about to read 3, iclass 7, count 2 2006.285.12:37:36.75#ibcon#read 3, iclass 7, count 2 2006.285.12:37:36.75#ibcon#about to read 4, iclass 7, count 2 2006.285.12:37:36.75#ibcon#read 4, iclass 7, count 2 2006.285.12:37:36.75#ibcon#about to read 5, iclass 7, count 2 2006.285.12:37:36.75#ibcon#read 5, iclass 7, count 2 2006.285.12:37:36.75#ibcon#about to read 6, iclass 7, count 2 2006.285.12:37:36.75#ibcon#read 6, iclass 7, count 2 2006.285.12:37:36.75#ibcon#end of sib2, iclass 7, count 2 2006.285.12:37:36.75#ibcon#*mode == 0, iclass 7, count 2 2006.285.12:37:36.75#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.12:37:36.75#ibcon#[25=AT07-04\r\n] 2006.285.12:37:36.75#ibcon#*before write, iclass 7, count 2 2006.285.12:37:36.75#ibcon#enter sib2, iclass 7, count 2 2006.285.12:37:36.75#ibcon#flushed, iclass 7, count 2 2006.285.12:37:36.75#ibcon#about to write, iclass 7, count 2 2006.285.12:37:36.75#ibcon#wrote, iclass 7, count 2 2006.285.12:37:36.75#ibcon#about to read 3, iclass 7, count 2 2006.285.12:37:36.78#ibcon#read 3, iclass 7, count 2 2006.285.12:37:36.78#ibcon#about to read 4, iclass 7, count 2 2006.285.12:37:36.78#ibcon#read 4, iclass 7, count 2 2006.285.12:37:36.78#ibcon#about to read 5, iclass 7, count 2 2006.285.12:37:36.78#ibcon#read 5, iclass 7, count 2 2006.285.12:37:36.78#ibcon#about to read 6, iclass 7, count 2 2006.285.12:37:36.78#ibcon#read 6, iclass 7, count 2 2006.285.12:37:36.78#ibcon#end of sib2, iclass 7, count 2 2006.285.12:37:36.78#ibcon#*after write, iclass 7, count 2 2006.285.12:37:36.78#ibcon#*before return 0, iclass 7, count 2 2006.285.12:37:36.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:37:36.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:37:36.78#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.12:37:36.78#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:36.78#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:37:36.90#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:37:36.90#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:37:36.90#ibcon#enter wrdev, iclass 7, count 0 2006.285.12:37:36.90#ibcon#first serial, iclass 7, count 0 2006.285.12:37:36.90#ibcon#enter sib2, iclass 7, count 0 2006.285.12:37:36.90#ibcon#flushed, iclass 7, count 0 2006.285.12:37:36.90#ibcon#about to write, iclass 7, count 0 2006.285.12:37:36.90#ibcon#wrote, iclass 7, count 0 2006.285.12:37:36.90#ibcon#about to read 3, iclass 7, count 0 2006.285.12:37:36.92#ibcon#read 3, iclass 7, count 0 2006.285.12:37:36.92#ibcon#about to read 4, iclass 7, count 0 2006.285.12:37:36.92#ibcon#read 4, iclass 7, count 0 2006.285.12:37:36.92#ibcon#about to read 5, iclass 7, count 0 2006.285.12:37:36.92#ibcon#read 5, iclass 7, count 0 2006.285.12:37:36.92#ibcon#about to read 6, iclass 7, count 0 2006.285.12:37:36.92#ibcon#read 6, iclass 7, count 0 2006.285.12:37:36.92#ibcon#end of sib2, iclass 7, count 0 2006.285.12:37:36.92#ibcon#*mode == 0, iclass 7, count 0 2006.285.12:37:36.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.12:37:36.92#ibcon#[25=USB\r\n] 2006.285.12:37:36.92#ibcon#*before write, iclass 7, count 0 2006.285.12:37:36.92#ibcon#enter sib2, iclass 7, count 0 2006.285.12:37:36.92#ibcon#flushed, iclass 7, count 0 2006.285.12:37:36.92#ibcon#about to write, iclass 7, count 0 2006.285.12:37:36.92#ibcon#wrote, iclass 7, count 0 2006.285.12:37:36.92#ibcon#about to read 3, iclass 7, count 0 2006.285.12:37:36.95#ibcon#read 3, iclass 7, count 0 2006.285.12:37:36.95#ibcon#about to read 4, iclass 7, count 0 2006.285.12:37:36.95#ibcon#read 4, iclass 7, count 0 2006.285.12:37:36.95#ibcon#about to read 5, iclass 7, count 0 2006.285.12:37:36.95#ibcon#read 5, iclass 7, count 0 2006.285.12:37:36.95#ibcon#about to read 6, iclass 7, count 0 2006.285.12:37:36.95#ibcon#read 6, iclass 7, count 0 2006.285.12:37:36.95#ibcon#end of sib2, iclass 7, count 0 2006.285.12:37:36.95#ibcon#*after write, iclass 7, count 0 2006.285.12:37:36.95#ibcon#*before return 0, iclass 7, count 0 2006.285.12:37:36.95#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:37:36.95#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:37:36.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.12:37:36.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.12:37:36.95$vck44/valo=8,884.99 2006.285.12:37:36.95#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.12:37:36.95#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.12:37:36.95#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:36.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:37:36.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:37:36.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:37:36.95#ibcon#enter wrdev, iclass 11, count 0 2006.285.12:37:36.95#ibcon#first serial, iclass 11, count 0 2006.285.12:37:36.95#ibcon#enter sib2, iclass 11, count 0 2006.285.12:37:36.95#ibcon#flushed, iclass 11, count 0 2006.285.12:37:36.95#ibcon#about to write, iclass 11, count 0 2006.285.12:37:36.95#ibcon#wrote, iclass 11, count 0 2006.285.12:37:36.95#ibcon#about to read 3, iclass 11, count 0 2006.285.12:37:36.97#ibcon#read 3, iclass 11, count 0 2006.285.12:37:36.97#ibcon#about to read 4, iclass 11, count 0 2006.285.12:37:36.97#ibcon#read 4, iclass 11, count 0 2006.285.12:37:36.97#ibcon#about to read 5, iclass 11, count 0 2006.285.12:37:36.97#ibcon#read 5, iclass 11, count 0 2006.285.12:37:36.97#ibcon#about to read 6, iclass 11, count 0 2006.285.12:37:36.97#ibcon#read 6, iclass 11, count 0 2006.285.12:37:36.97#ibcon#end of sib2, iclass 11, count 0 2006.285.12:37:36.97#ibcon#*mode == 0, iclass 11, count 0 2006.285.12:37:36.97#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.12:37:36.97#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.12:37:36.97#ibcon#*before write, iclass 11, count 0 2006.285.12:37:36.97#ibcon#enter sib2, iclass 11, count 0 2006.285.12:37:36.97#ibcon#flushed, iclass 11, count 0 2006.285.12:37:36.97#ibcon#about to write, iclass 11, count 0 2006.285.12:37:36.97#ibcon#wrote, iclass 11, count 0 2006.285.12:37:36.97#ibcon#about to read 3, iclass 11, count 0 2006.285.12:37:37.01#ibcon#read 3, iclass 11, count 0 2006.285.12:37:37.01#ibcon#about to read 4, iclass 11, count 0 2006.285.12:37:37.01#ibcon#read 4, iclass 11, count 0 2006.285.12:37:37.01#ibcon#about to read 5, iclass 11, count 0 2006.285.12:37:37.01#ibcon#read 5, iclass 11, count 0 2006.285.12:37:37.01#ibcon#about to read 6, iclass 11, count 0 2006.285.12:37:37.01#ibcon#read 6, iclass 11, count 0 2006.285.12:37:37.01#ibcon#end of sib2, iclass 11, count 0 2006.285.12:37:37.01#ibcon#*after write, iclass 11, count 0 2006.285.12:37:37.01#ibcon#*before return 0, iclass 11, count 0 2006.285.12:37:37.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:37:37.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:37:37.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.12:37:37.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.12:37:37.01$vck44/va=8,3 2006.285.12:37:37.01#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.12:37:37.01#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.12:37:37.01#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:37.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:37:37.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:37:37.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:37:37.07#ibcon#enter wrdev, iclass 13, count 2 2006.285.12:37:37.07#ibcon#first serial, iclass 13, count 2 2006.285.12:37:37.07#ibcon#enter sib2, iclass 13, count 2 2006.285.12:37:37.07#ibcon#flushed, iclass 13, count 2 2006.285.12:37:37.07#ibcon#about to write, iclass 13, count 2 2006.285.12:37:37.07#ibcon#wrote, iclass 13, count 2 2006.285.12:37:37.07#ibcon#about to read 3, iclass 13, count 2 2006.285.12:37:37.09#ibcon#read 3, iclass 13, count 2 2006.285.12:37:37.09#ibcon#about to read 4, iclass 13, count 2 2006.285.12:37:37.09#ibcon#read 4, iclass 13, count 2 2006.285.12:37:37.09#ibcon#about to read 5, iclass 13, count 2 2006.285.12:37:37.09#ibcon#read 5, iclass 13, count 2 2006.285.12:37:37.09#ibcon#about to read 6, iclass 13, count 2 2006.285.12:37:37.09#ibcon#read 6, iclass 13, count 2 2006.285.12:37:37.09#ibcon#end of sib2, iclass 13, count 2 2006.285.12:37:37.09#ibcon#*mode == 0, iclass 13, count 2 2006.285.12:37:37.09#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.12:37:37.09#ibcon#[25=AT08-03\r\n] 2006.285.12:37:37.09#ibcon#*before write, iclass 13, count 2 2006.285.12:37:37.09#ibcon#enter sib2, iclass 13, count 2 2006.285.12:37:37.09#ibcon#flushed, iclass 13, count 2 2006.285.12:37:37.09#ibcon#about to write, iclass 13, count 2 2006.285.12:37:37.09#ibcon#wrote, iclass 13, count 2 2006.285.12:37:37.09#ibcon#about to read 3, iclass 13, count 2 2006.285.12:37:37.12#ibcon#read 3, iclass 13, count 2 2006.285.12:37:37.12#ibcon#about to read 4, iclass 13, count 2 2006.285.12:37:37.12#ibcon#read 4, iclass 13, count 2 2006.285.12:37:37.12#ibcon#about to read 5, iclass 13, count 2 2006.285.12:37:37.12#ibcon#read 5, iclass 13, count 2 2006.285.12:37:37.12#ibcon#about to read 6, iclass 13, count 2 2006.285.12:37:37.12#ibcon#read 6, iclass 13, count 2 2006.285.12:37:37.12#ibcon#end of sib2, iclass 13, count 2 2006.285.12:37:37.12#ibcon#*after write, iclass 13, count 2 2006.285.12:37:37.12#ibcon#*before return 0, iclass 13, count 2 2006.285.12:37:37.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:37:37.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.12:37:37.12#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.12:37:37.12#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:37.12#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:37:37.24#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:37:37.24#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:37:37.24#ibcon#enter wrdev, iclass 13, count 0 2006.285.12:37:37.24#ibcon#first serial, iclass 13, count 0 2006.285.12:37:37.24#ibcon#enter sib2, iclass 13, count 0 2006.285.12:37:37.24#ibcon#flushed, iclass 13, count 0 2006.285.12:37:37.24#ibcon#about to write, iclass 13, count 0 2006.285.12:37:37.24#ibcon#wrote, iclass 13, count 0 2006.285.12:37:37.24#ibcon#about to read 3, iclass 13, count 0 2006.285.12:37:37.26#ibcon#read 3, iclass 13, count 0 2006.285.12:37:37.26#ibcon#about to read 4, iclass 13, count 0 2006.285.12:37:37.26#ibcon#read 4, iclass 13, count 0 2006.285.12:37:37.26#ibcon#about to read 5, iclass 13, count 0 2006.285.12:37:37.26#ibcon#read 5, iclass 13, count 0 2006.285.12:37:37.26#ibcon#about to read 6, iclass 13, count 0 2006.285.12:37:37.26#ibcon#read 6, iclass 13, count 0 2006.285.12:37:37.26#ibcon#end of sib2, iclass 13, count 0 2006.285.12:37:37.26#ibcon#*mode == 0, iclass 13, count 0 2006.285.12:37:37.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.12:37:37.26#ibcon#[25=USB\r\n] 2006.285.12:37:37.26#ibcon#*before write, iclass 13, count 0 2006.285.12:37:37.26#ibcon#enter sib2, iclass 13, count 0 2006.285.12:37:37.26#ibcon#flushed, iclass 13, count 0 2006.285.12:37:37.26#ibcon#about to write, iclass 13, count 0 2006.285.12:37:37.26#ibcon#wrote, iclass 13, count 0 2006.285.12:37:37.26#ibcon#about to read 3, iclass 13, count 0 2006.285.12:37:37.29#ibcon#read 3, iclass 13, count 0 2006.285.12:37:37.29#ibcon#about to read 4, iclass 13, count 0 2006.285.12:37:37.29#ibcon#read 4, iclass 13, count 0 2006.285.12:37:37.29#ibcon#about to read 5, iclass 13, count 0 2006.285.12:37:37.29#ibcon#read 5, iclass 13, count 0 2006.285.12:37:37.29#ibcon#about to read 6, iclass 13, count 0 2006.285.12:37:37.29#ibcon#read 6, iclass 13, count 0 2006.285.12:37:37.29#ibcon#end of sib2, iclass 13, count 0 2006.285.12:37:37.29#ibcon#*after write, iclass 13, count 0 2006.285.12:37:37.29#ibcon#*before return 0, iclass 13, count 0 2006.285.12:37:37.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:37:37.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.12:37:37.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.12:37:37.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.12:37:37.29$vck44/vblo=1,629.99 2006.285.12:37:37.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.12:37:37.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.12:37:37.29#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:37.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:37:37.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:37:37.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:37:37.29#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:37:37.29#ibcon#first serial, iclass 15, count 0 2006.285.12:37:37.29#ibcon#enter sib2, iclass 15, count 0 2006.285.12:37:37.29#ibcon#flushed, iclass 15, count 0 2006.285.12:37:37.29#ibcon#about to write, iclass 15, count 0 2006.285.12:37:37.29#ibcon#wrote, iclass 15, count 0 2006.285.12:37:37.29#ibcon#about to read 3, iclass 15, count 0 2006.285.12:37:37.31#ibcon#read 3, iclass 15, count 0 2006.285.12:37:37.31#ibcon#about to read 4, iclass 15, count 0 2006.285.12:37:37.31#ibcon#read 4, iclass 15, count 0 2006.285.12:37:37.31#ibcon#about to read 5, iclass 15, count 0 2006.285.12:37:37.31#ibcon#read 5, iclass 15, count 0 2006.285.12:37:37.31#ibcon#about to read 6, iclass 15, count 0 2006.285.12:37:37.31#ibcon#read 6, iclass 15, count 0 2006.285.12:37:37.31#ibcon#end of sib2, iclass 15, count 0 2006.285.12:37:37.31#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:37:37.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:37:37.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.12:37:37.31#ibcon#*before write, iclass 15, count 0 2006.285.12:37:37.31#ibcon#enter sib2, iclass 15, count 0 2006.285.12:37:37.31#ibcon#flushed, iclass 15, count 0 2006.285.12:37:37.31#ibcon#about to write, iclass 15, count 0 2006.285.12:37:37.31#ibcon#wrote, iclass 15, count 0 2006.285.12:37:37.31#ibcon#about to read 3, iclass 15, count 0 2006.285.12:37:37.35#ibcon#read 3, iclass 15, count 0 2006.285.12:37:37.35#ibcon#about to read 4, iclass 15, count 0 2006.285.12:37:37.35#ibcon#read 4, iclass 15, count 0 2006.285.12:37:37.35#ibcon#about to read 5, iclass 15, count 0 2006.285.12:37:37.35#ibcon#read 5, iclass 15, count 0 2006.285.12:37:37.35#ibcon#about to read 6, iclass 15, count 0 2006.285.12:37:37.35#ibcon#read 6, iclass 15, count 0 2006.285.12:37:37.35#ibcon#end of sib2, iclass 15, count 0 2006.285.12:37:37.35#ibcon#*after write, iclass 15, count 0 2006.285.12:37:37.35#ibcon#*before return 0, iclass 15, count 0 2006.285.12:37:37.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:37:37.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.12:37:37.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:37:37.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:37:37.35$vck44/vb=1,4 2006.285.12:37:37.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.12:37:37.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.12:37:37.35#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:37.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:37:37.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:37:37.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:37:37.35#ibcon#enter wrdev, iclass 17, count 2 2006.285.12:37:37.35#ibcon#first serial, iclass 17, count 2 2006.285.12:37:37.35#ibcon#enter sib2, iclass 17, count 2 2006.285.12:37:37.35#ibcon#flushed, iclass 17, count 2 2006.285.12:37:37.35#ibcon#about to write, iclass 17, count 2 2006.285.12:37:37.35#ibcon#wrote, iclass 17, count 2 2006.285.12:37:37.35#ibcon#about to read 3, iclass 17, count 2 2006.285.12:37:37.37#ibcon#read 3, iclass 17, count 2 2006.285.12:37:37.37#ibcon#about to read 4, iclass 17, count 2 2006.285.12:37:37.37#ibcon#read 4, iclass 17, count 2 2006.285.12:37:37.37#ibcon#about to read 5, iclass 17, count 2 2006.285.12:37:37.37#ibcon#read 5, iclass 17, count 2 2006.285.12:37:37.37#ibcon#about to read 6, iclass 17, count 2 2006.285.12:37:37.37#ibcon#read 6, iclass 17, count 2 2006.285.12:37:37.37#ibcon#end of sib2, iclass 17, count 2 2006.285.12:37:37.37#ibcon#*mode == 0, iclass 17, count 2 2006.285.12:37:37.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.12:37:37.37#ibcon#[27=AT01-04\r\n] 2006.285.12:37:37.37#ibcon#*before write, iclass 17, count 2 2006.285.12:37:37.37#ibcon#enter sib2, iclass 17, count 2 2006.285.12:37:37.37#ibcon#flushed, iclass 17, count 2 2006.285.12:37:37.37#ibcon#about to write, iclass 17, count 2 2006.285.12:37:37.37#ibcon#wrote, iclass 17, count 2 2006.285.12:37:37.37#ibcon#about to read 3, iclass 17, count 2 2006.285.12:37:37.40#ibcon#read 3, iclass 17, count 2 2006.285.12:37:37.40#ibcon#about to read 4, iclass 17, count 2 2006.285.12:37:37.40#ibcon#read 4, iclass 17, count 2 2006.285.12:37:37.40#ibcon#about to read 5, iclass 17, count 2 2006.285.12:37:37.40#ibcon#read 5, iclass 17, count 2 2006.285.12:37:37.40#ibcon#about to read 6, iclass 17, count 2 2006.285.12:37:37.40#ibcon#read 6, iclass 17, count 2 2006.285.12:37:37.40#ibcon#end of sib2, iclass 17, count 2 2006.285.12:37:37.40#ibcon#*after write, iclass 17, count 2 2006.285.12:37:37.40#ibcon#*before return 0, iclass 17, count 2 2006.285.12:37:37.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:37:37.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.12:37:37.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.12:37:37.40#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:37.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:37:37.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:37:37.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:37:37.52#ibcon#enter wrdev, iclass 17, count 0 2006.285.12:37:37.52#ibcon#first serial, iclass 17, count 0 2006.285.12:37:37.52#ibcon#enter sib2, iclass 17, count 0 2006.285.12:37:37.52#ibcon#flushed, iclass 17, count 0 2006.285.12:37:37.52#ibcon#about to write, iclass 17, count 0 2006.285.12:37:37.52#ibcon#wrote, iclass 17, count 0 2006.285.12:37:37.52#ibcon#about to read 3, iclass 17, count 0 2006.285.12:37:37.54#ibcon#read 3, iclass 17, count 0 2006.285.12:37:37.54#ibcon#about to read 4, iclass 17, count 0 2006.285.12:37:37.54#ibcon#read 4, iclass 17, count 0 2006.285.12:37:37.54#ibcon#about to read 5, iclass 17, count 0 2006.285.12:37:37.54#ibcon#read 5, iclass 17, count 0 2006.285.12:37:37.54#ibcon#about to read 6, iclass 17, count 0 2006.285.12:37:37.54#ibcon#read 6, iclass 17, count 0 2006.285.12:37:37.54#ibcon#end of sib2, iclass 17, count 0 2006.285.12:37:37.54#ibcon#*mode == 0, iclass 17, count 0 2006.285.12:37:37.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.12:37:37.54#ibcon#[27=USB\r\n] 2006.285.12:37:37.54#ibcon#*before write, iclass 17, count 0 2006.285.12:37:37.54#ibcon#enter sib2, iclass 17, count 0 2006.285.12:37:37.54#ibcon#flushed, iclass 17, count 0 2006.285.12:37:37.54#ibcon#about to write, iclass 17, count 0 2006.285.12:37:37.54#ibcon#wrote, iclass 17, count 0 2006.285.12:37:37.54#ibcon#about to read 3, iclass 17, count 0 2006.285.12:37:37.57#ibcon#read 3, iclass 17, count 0 2006.285.12:37:37.57#ibcon#about to read 4, iclass 17, count 0 2006.285.12:37:37.57#ibcon#read 4, iclass 17, count 0 2006.285.12:37:37.57#ibcon#about to read 5, iclass 17, count 0 2006.285.12:37:37.57#ibcon#read 5, iclass 17, count 0 2006.285.12:37:37.57#ibcon#about to read 6, iclass 17, count 0 2006.285.12:37:37.57#ibcon#read 6, iclass 17, count 0 2006.285.12:37:37.57#ibcon#end of sib2, iclass 17, count 0 2006.285.12:37:37.57#ibcon#*after write, iclass 17, count 0 2006.285.12:37:37.57#ibcon#*before return 0, iclass 17, count 0 2006.285.12:37:37.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:37:37.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.12:37:37.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.12:37:37.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.12:37:37.57$vck44/vblo=2,634.99 2006.285.12:37:37.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.12:37:37.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.12:37:37.57#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:37.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:37:37.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:37:37.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:37:37.57#ibcon#enter wrdev, iclass 19, count 0 2006.285.12:37:37.57#ibcon#first serial, iclass 19, count 0 2006.285.12:37:37.57#ibcon#enter sib2, iclass 19, count 0 2006.285.12:37:37.57#ibcon#flushed, iclass 19, count 0 2006.285.12:37:37.57#ibcon#about to write, iclass 19, count 0 2006.285.12:37:37.57#ibcon#wrote, iclass 19, count 0 2006.285.12:37:37.57#ibcon#about to read 3, iclass 19, count 0 2006.285.12:37:37.59#ibcon#read 3, iclass 19, count 0 2006.285.12:37:37.59#ibcon#about to read 4, iclass 19, count 0 2006.285.12:37:37.59#ibcon#read 4, iclass 19, count 0 2006.285.12:37:37.59#ibcon#about to read 5, iclass 19, count 0 2006.285.12:37:37.59#ibcon#read 5, iclass 19, count 0 2006.285.12:37:37.59#ibcon#about to read 6, iclass 19, count 0 2006.285.12:37:37.59#ibcon#read 6, iclass 19, count 0 2006.285.12:37:37.59#ibcon#end of sib2, iclass 19, count 0 2006.285.12:37:37.59#ibcon#*mode == 0, iclass 19, count 0 2006.285.12:37:37.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.12:37:37.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.12:37:37.59#ibcon#*before write, iclass 19, count 0 2006.285.12:37:37.59#ibcon#enter sib2, iclass 19, count 0 2006.285.12:37:37.59#ibcon#flushed, iclass 19, count 0 2006.285.12:37:37.59#ibcon#about to write, iclass 19, count 0 2006.285.12:37:37.59#ibcon#wrote, iclass 19, count 0 2006.285.12:37:37.59#ibcon#about to read 3, iclass 19, count 0 2006.285.12:37:37.63#ibcon#read 3, iclass 19, count 0 2006.285.12:37:37.63#ibcon#about to read 4, iclass 19, count 0 2006.285.12:37:37.63#ibcon#read 4, iclass 19, count 0 2006.285.12:37:37.63#ibcon#about to read 5, iclass 19, count 0 2006.285.12:37:37.63#ibcon#read 5, iclass 19, count 0 2006.285.12:37:37.63#ibcon#about to read 6, iclass 19, count 0 2006.285.12:37:37.63#ibcon#read 6, iclass 19, count 0 2006.285.12:37:37.63#ibcon#end of sib2, iclass 19, count 0 2006.285.12:37:37.63#ibcon#*after write, iclass 19, count 0 2006.285.12:37:37.63#ibcon#*before return 0, iclass 19, count 0 2006.285.12:37:37.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:37:37.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.12:37:37.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.12:37:37.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.12:37:37.63$vck44/vb=2,5 2006.285.12:37:37.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.12:37:37.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.12:37:37.63#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:37.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:37:37.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:37:37.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:37:37.69#ibcon#enter wrdev, iclass 21, count 2 2006.285.12:37:37.69#ibcon#first serial, iclass 21, count 2 2006.285.12:37:37.69#ibcon#enter sib2, iclass 21, count 2 2006.285.12:37:37.69#ibcon#flushed, iclass 21, count 2 2006.285.12:37:37.69#ibcon#about to write, iclass 21, count 2 2006.285.12:37:37.69#ibcon#wrote, iclass 21, count 2 2006.285.12:37:37.69#ibcon#about to read 3, iclass 21, count 2 2006.285.12:37:37.71#ibcon#read 3, iclass 21, count 2 2006.285.12:37:37.71#ibcon#about to read 4, iclass 21, count 2 2006.285.12:37:37.71#ibcon#read 4, iclass 21, count 2 2006.285.12:37:37.71#ibcon#about to read 5, iclass 21, count 2 2006.285.12:37:37.71#ibcon#read 5, iclass 21, count 2 2006.285.12:37:37.71#ibcon#about to read 6, iclass 21, count 2 2006.285.12:37:37.71#ibcon#read 6, iclass 21, count 2 2006.285.12:37:37.71#ibcon#end of sib2, iclass 21, count 2 2006.285.12:37:37.71#ibcon#*mode == 0, iclass 21, count 2 2006.285.12:37:37.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.12:37:37.71#ibcon#[27=AT02-05\r\n] 2006.285.12:37:37.71#ibcon#*before write, iclass 21, count 2 2006.285.12:37:37.71#ibcon#enter sib2, iclass 21, count 2 2006.285.12:37:37.71#ibcon#flushed, iclass 21, count 2 2006.285.12:37:37.71#ibcon#about to write, iclass 21, count 2 2006.285.12:37:37.71#ibcon#wrote, iclass 21, count 2 2006.285.12:37:37.71#ibcon#about to read 3, iclass 21, count 2 2006.285.12:37:37.74#ibcon#read 3, iclass 21, count 2 2006.285.12:37:37.74#ibcon#about to read 4, iclass 21, count 2 2006.285.12:37:37.74#ibcon#read 4, iclass 21, count 2 2006.285.12:37:37.74#ibcon#about to read 5, iclass 21, count 2 2006.285.12:37:37.74#ibcon#read 5, iclass 21, count 2 2006.285.12:37:37.74#ibcon#about to read 6, iclass 21, count 2 2006.285.12:37:37.74#ibcon#read 6, iclass 21, count 2 2006.285.12:37:37.74#ibcon#end of sib2, iclass 21, count 2 2006.285.12:37:37.74#ibcon#*after write, iclass 21, count 2 2006.285.12:37:37.74#ibcon#*before return 0, iclass 21, count 2 2006.285.12:37:37.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:37:37.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.12:37:37.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.12:37:37.74#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:37.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:37:37.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:37:37.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:37:37.86#ibcon#enter wrdev, iclass 21, count 0 2006.285.12:37:37.86#ibcon#first serial, iclass 21, count 0 2006.285.12:37:37.86#ibcon#enter sib2, iclass 21, count 0 2006.285.12:37:37.86#ibcon#flushed, iclass 21, count 0 2006.285.12:37:37.86#ibcon#about to write, iclass 21, count 0 2006.285.12:37:37.86#ibcon#wrote, iclass 21, count 0 2006.285.12:37:37.86#ibcon#about to read 3, iclass 21, count 0 2006.285.12:37:37.88#ibcon#read 3, iclass 21, count 0 2006.285.12:37:37.88#ibcon#about to read 4, iclass 21, count 0 2006.285.12:37:37.88#ibcon#read 4, iclass 21, count 0 2006.285.12:37:37.88#ibcon#about to read 5, iclass 21, count 0 2006.285.12:37:37.88#ibcon#read 5, iclass 21, count 0 2006.285.12:37:37.88#ibcon#about to read 6, iclass 21, count 0 2006.285.12:37:37.88#ibcon#read 6, iclass 21, count 0 2006.285.12:37:37.88#ibcon#end of sib2, iclass 21, count 0 2006.285.12:37:37.88#ibcon#*mode == 0, iclass 21, count 0 2006.285.12:37:37.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.12:37:37.88#ibcon#[27=USB\r\n] 2006.285.12:37:37.88#ibcon#*before write, iclass 21, count 0 2006.285.12:37:37.88#ibcon#enter sib2, iclass 21, count 0 2006.285.12:37:37.88#ibcon#flushed, iclass 21, count 0 2006.285.12:37:37.88#ibcon#about to write, iclass 21, count 0 2006.285.12:37:37.88#ibcon#wrote, iclass 21, count 0 2006.285.12:37:37.88#ibcon#about to read 3, iclass 21, count 0 2006.285.12:37:37.91#ibcon#read 3, iclass 21, count 0 2006.285.12:37:37.91#ibcon#about to read 4, iclass 21, count 0 2006.285.12:37:37.91#ibcon#read 4, iclass 21, count 0 2006.285.12:37:37.91#ibcon#about to read 5, iclass 21, count 0 2006.285.12:37:37.91#ibcon#read 5, iclass 21, count 0 2006.285.12:37:37.91#ibcon#about to read 6, iclass 21, count 0 2006.285.12:37:37.91#ibcon#read 6, iclass 21, count 0 2006.285.12:37:37.91#ibcon#end of sib2, iclass 21, count 0 2006.285.12:37:37.91#ibcon#*after write, iclass 21, count 0 2006.285.12:37:37.91#ibcon#*before return 0, iclass 21, count 0 2006.285.12:37:37.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:37:37.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.12:37:37.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.12:37:37.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.12:37:37.91$vck44/vblo=3,649.99 2006.285.12:37:37.98#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.12:37:37.98#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.12:37:37.98#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:37.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:37:37.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:37:37.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:37:37.98#ibcon#enter wrdev, iclass 23, count 0 2006.285.12:37:37.98#ibcon#first serial, iclass 23, count 0 2006.285.12:37:37.98#ibcon#enter sib2, iclass 23, count 0 2006.285.12:37:37.98#ibcon#flushed, iclass 23, count 0 2006.285.12:37:37.98#ibcon#about to write, iclass 23, count 0 2006.285.12:37:37.98#ibcon#wrote, iclass 23, count 0 2006.285.12:37:37.98#ibcon#about to read 3, iclass 23, count 0 2006.285.12:37:38.00#ibcon#read 3, iclass 23, count 0 2006.285.12:37:38.00#ibcon#about to read 4, iclass 23, count 0 2006.285.12:37:38.00#ibcon#read 4, iclass 23, count 0 2006.285.12:37:38.00#ibcon#about to read 5, iclass 23, count 0 2006.285.12:37:38.00#ibcon#read 5, iclass 23, count 0 2006.285.12:37:38.00#ibcon#about to read 6, iclass 23, count 0 2006.285.12:37:38.00#ibcon#read 6, iclass 23, count 0 2006.285.12:37:38.00#ibcon#end of sib2, iclass 23, count 0 2006.285.12:37:38.00#ibcon#*mode == 0, iclass 23, count 0 2006.285.12:37:38.00#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.12:37:38.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.12:37:38.00#ibcon#*before write, iclass 23, count 0 2006.285.12:37:38.00#ibcon#enter sib2, iclass 23, count 0 2006.285.12:37:38.00#ibcon#flushed, iclass 23, count 0 2006.285.12:37:38.00#ibcon#about to write, iclass 23, count 0 2006.285.12:37:38.00#ibcon#wrote, iclass 23, count 0 2006.285.12:37:38.00#ibcon#about to read 3, iclass 23, count 0 2006.285.12:37:38.04#ibcon#read 3, iclass 23, count 0 2006.285.12:37:38.04#ibcon#about to read 4, iclass 23, count 0 2006.285.12:37:38.04#ibcon#read 4, iclass 23, count 0 2006.285.12:37:38.04#ibcon#about to read 5, iclass 23, count 0 2006.285.12:37:38.04#ibcon#read 5, iclass 23, count 0 2006.285.12:37:38.04#ibcon#about to read 6, iclass 23, count 0 2006.285.12:37:38.04#ibcon#read 6, iclass 23, count 0 2006.285.12:37:38.04#ibcon#end of sib2, iclass 23, count 0 2006.285.12:37:38.04#ibcon#*after write, iclass 23, count 0 2006.285.12:37:38.04#ibcon#*before return 0, iclass 23, count 0 2006.285.12:37:38.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:37:38.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.12:37:38.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.12:37:38.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.12:37:38.04$vck44/vb=3,4 2006.285.12:37:38.04#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.12:37:38.04#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.12:37:38.04#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:38.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:37:38.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:37:38.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:37:38.04#ibcon#enter wrdev, iclass 25, count 2 2006.285.12:37:38.04#ibcon#first serial, iclass 25, count 2 2006.285.12:37:38.04#ibcon#enter sib2, iclass 25, count 2 2006.285.12:37:38.04#ibcon#flushed, iclass 25, count 2 2006.285.12:37:38.04#ibcon#about to write, iclass 25, count 2 2006.285.12:37:38.04#ibcon#wrote, iclass 25, count 2 2006.285.12:37:38.04#ibcon#about to read 3, iclass 25, count 2 2006.285.12:37:38.06#ibcon#read 3, iclass 25, count 2 2006.285.12:37:38.06#ibcon#about to read 4, iclass 25, count 2 2006.285.12:37:38.06#ibcon#read 4, iclass 25, count 2 2006.285.12:37:38.06#ibcon#about to read 5, iclass 25, count 2 2006.285.12:37:38.06#ibcon#read 5, iclass 25, count 2 2006.285.12:37:38.06#ibcon#about to read 6, iclass 25, count 2 2006.285.12:37:38.06#ibcon#read 6, iclass 25, count 2 2006.285.12:37:38.06#ibcon#end of sib2, iclass 25, count 2 2006.285.12:37:38.06#ibcon#*mode == 0, iclass 25, count 2 2006.285.12:37:38.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.12:37:38.06#ibcon#[27=AT03-04\r\n] 2006.285.12:37:38.06#ibcon#*before write, iclass 25, count 2 2006.285.12:37:38.06#ibcon#enter sib2, iclass 25, count 2 2006.285.12:37:38.06#ibcon#flushed, iclass 25, count 2 2006.285.12:37:38.06#ibcon#about to write, iclass 25, count 2 2006.285.12:37:38.06#ibcon#wrote, iclass 25, count 2 2006.285.12:37:38.06#ibcon#about to read 3, iclass 25, count 2 2006.285.12:37:38.09#ibcon#read 3, iclass 25, count 2 2006.285.12:37:38.09#ibcon#about to read 4, iclass 25, count 2 2006.285.12:37:38.09#ibcon#read 4, iclass 25, count 2 2006.285.12:37:38.09#ibcon#about to read 5, iclass 25, count 2 2006.285.12:37:38.09#ibcon#read 5, iclass 25, count 2 2006.285.12:37:38.09#ibcon#about to read 6, iclass 25, count 2 2006.285.12:37:38.09#ibcon#read 6, iclass 25, count 2 2006.285.12:37:38.09#ibcon#end of sib2, iclass 25, count 2 2006.285.12:37:38.09#ibcon#*after write, iclass 25, count 2 2006.285.12:37:38.09#ibcon#*before return 0, iclass 25, count 2 2006.285.12:37:38.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:37:38.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.12:37:38.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.12:37:38.09#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:38.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:37:38.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:37:38.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:37:38.21#ibcon#enter wrdev, iclass 25, count 0 2006.285.12:37:38.21#ibcon#first serial, iclass 25, count 0 2006.285.12:37:38.21#ibcon#enter sib2, iclass 25, count 0 2006.285.12:37:38.21#ibcon#flushed, iclass 25, count 0 2006.285.12:37:38.21#ibcon#about to write, iclass 25, count 0 2006.285.12:37:38.21#ibcon#wrote, iclass 25, count 0 2006.285.12:37:38.21#ibcon#about to read 3, iclass 25, count 0 2006.285.12:37:38.23#ibcon#read 3, iclass 25, count 0 2006.285.12:37:38.23#ibcon#about to read 4, iclass 25, count 0 2006.285.12:37:38.23#ibcon#read 4, iclass 25, count 0 2006.285.12:37:38.23#ibcon#about to read 5, iclass 25, count 0 2006.285.12:37:38.23#ibcon#read 5, iclass 25, count 0 2006.285.12:37:38.23#ibcon#about to read 6, iclass 25, count 0 2006.285.12:37:38.23#ibcon#read 6, iclass 25, count 0 2006.285.12:37:38.23#ibcon#end of sib2, iclass 25, count 0 2006.285.12:37:38.23#ibcon#*mode == 0, iclass 25, count 0 2006.285.12:37:38.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.12:37:38.23#ibcon#[27=USB\r\n] 2006.285.12:37:38.23#ibcon#*before write, iclass 25, count 0 2006.285.12:37:38.23#ibcon#enter sib2, iclass 25, count 0 2006.285.12:37:38.23#ibcon#flushed, iclass 25, count 0 2006.285.12:37:38.23#ibcon#about to write, iclass 25, count 0 2006.285.12:37:38.23#ibcon#wrote, iclass 25, count 0 2006.285.12:37:38.23#ibcon#about to read 3, iclass 25, count 0 2006.285.12:37:38.26#ibcon#read 3, iclass 25, count 0 2006.285.12:37:38.26#ibcon#about to read 4, iclass 25, count 0 2006.285.12:37:38.26#ibcon#read 4, iclass 25, count 0 2006.285.12:37:38.26#ibcon#about to read 5, iclass 25, count 0 2006.285.12:37:38.26#ibcon#read 5, iclass 25, count 0 2006.285.12:37:38.26#ibcon#about to read 6, iclass 25, count 0 2006.285.12:37:38.26#ibcon#read 6, iclass 25, count 0 2006.285.12:37:38.26#ibcon#end of sib2, iclass 25, count 0 2006.285.12:37:38.26#ibcon#*after write, iclass 25, count 0 2006.285.12:37:38.26#ibcon#*before return 0, iclass 25, count 0 2006.285.12:37:38.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:37:38.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.12:37:38.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.12:37:38.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.12:37:38.26$vck44/vblo=4,679.99 2006.285.12:37:38.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.12:37:38.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.12:37:38.26#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:38.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:37:38.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:37:38.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:37:38.26#ibcon#enter wrdev, iclass 27, count 0 2006.285.12:37:38.26#ibcon#first serial, iclass 27, count 0 2006.285.12:37:38.26#ibcon#enter sib2, iclass 27, count 0 2006.285.12:37:38.26#ibcon#flushed, iclass 27, count 0 2006.285.12:37:38.26#ibcon#about to write, iclass 27, count 0 2006.285.12:37:38.26#ibcon#wrote, iclass 27, count 0 2006.285.12:37:38.26#ibcon#about to read 3, iclass 27, count 0 2006.285.12:37:38.28#ibcon#read 3, iclass 27, count 0 2006.285.12:37:38.28#ibcon#about to read 4, iclass 27, count 0 2006.285.12:37:38.28#ibcon#read 4, iclass 27, count 0 2006.285.12:37:38.28#ibcon#about to read 5, iclass 27, count 0 2006.285.12:37:38.28#ibcon#read 5, iclass 27, count 0 2006.285.12:37:38.28#ibcon#about to read 6, iclass 27, count 0 2006.285.12:37:38.28#ibcon#read 6, iclass 27, count 0 2006.285.12:37:38.28#ibcon#end of sib2, iclass 27, count 0 2006.285.12:37:38.28#ibcon#*mode == 0, iclass 27, count 0 2006.285.12:37:38.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.12:37:38.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.12:37:38.28#ibcon#*before write, iclass 27, count 0 2006.285.12:37:38.28#ibcon#enter sib2, iclass 27, count 0 2006.285.12:37:38.28#ibcon#flushed, iclass 27, count 0 2006.285.12:37:38.28#ibcon#about to write, iclass 27, count 0 2006.285.12:37:38.28#ibcon#wrote, iclass 27, count 0 2006.285.12:37:38.28#ibcon#about to read 3, iclass 27, count 0 2006.285.12:37:38.32#ibcon#read 3, iclass 27, count 0 2006.285.12:37:38.32#ibcon#about to read 4, iclass 27, count 0 2006.285.12:37:38.32#ibcon#read 4, iclass 27, count 0 2006.285.12:37:38.32#ibcon#about to read 5, iclass 27, count 0 2006.285.12:37:38.32#ibcon#read 5, iclass 27, count 0 2006.285.12:37:38.32#ibcon#about to read 6, iclass 27, count 0 2006.285.12:37:38.32#ibcon#read 6, iclass 27, count 0 2006.285.12:37:38.32#ibcon#end of sib2, iclass 27, count 0 2006.285.12:37:38.32#ibcon#*after write, iclass 27, count 0 2006.285.12:37:38.32#ibcon#*before return 0, iclass 27, count 0 2006.285.12:37:38.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:37:38.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:37:38.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.12:37:38.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.12:37:38.32$vck44/vb=4,5 2006.285.12:37:38.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.12:37:38.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.12:37:38.32#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:38.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:37:38.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:37:38.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:37:38.38#ibcon#enter wrdev, iclass 29, count 2 2006.285.12:37:38.38#ibcon#first serial, iclass 29, count 2 2006.285.12:37:38.38#ibcon#enter sib2, iclass 29, count 2 2006.285.12:37:38.38#ibcon#flushed, iclass 29, count 2 2006.285.12:37:38.38#ibcon#about to write, iclass 29, count 2 2006.285.12:37:38.38#ibcon#wrote, iclass 29, count 2 2006.285.12:37:38.38#ibcon#about to read 3, iclass 29, count 2 2006.285.12:37:38.40#ibcon#read 3, iclass 29, count 2 2006.285.12:37:38.40#ibcon#about to read 4, iclass 29, count 2 2006.285.12:37:38.40#ibcon#read 4, iclass 29, count 2 2006.285.12:37:38.40#ibcon#about to read 5, iclass 29, count 2 2006.285.12:37:38.40#ibcon#read 5, iclass 29, count 2 2006.285.12:37:38.40#ibcon#about to read 6, iclass 29, count 2 2006.285.12:37:38.40#ibcon#read 6, iclass 29, count 2 2006.285.12:37:38.40#ibcon#end of sib2, iclass 29, count 2 2006.285.12:37:38.40#ibcon#*mode == 0, iclass 29, count 2 2006.285.12:37:38.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.12:37:38.40#ibcon#[27=AT04-05\r\n] 2006.285.12:37:38.40#ibcon#*before write, iclass 29, count 2 2006.285.12:37:38.40#ibcon#enter sib2, iclass 29, count 2 2006.285.12:37:38.40#ibcon#flushed, iclass 29, count 2 2006.285.12:37:38.40#ibcon#about to write, iclass 29, count 2 2006.285.12:37:38.40#ibcon#wrote, iclass 29, count 2 2006.285.12:37:38.40#ibcon#about to read 3, iclass 29, count 2 2006.285.12:37:38.43#ibcon#read 3, iclass 29, count 2 2006.285.12:37:38.43#ibcon#about to read 4, iclass 29, count 2 2006.285.12:37:38.43#ibcon#read 4, iclass 29, count 2 2006.285.12:37:38.43#ibcon#about to read 5, iclass 29, count 2 2006.285.12:37:38.43#ibcon#read 5, iclass 29, count 2 2006.285.12:37:38.43#ibcon#about to read 6, iclass 29, count 2 2006.285.12:37:38.43#ibcon#read 6, iclass 29, count 2 2006.285.12:37:38.43#ibcon#end of sib2, iclass 29, count 2 2006.285.12:37:38.43#ibcon#*after write, iclass 29, count 2 2006.285.12:37:38.43#ibcon#*before return 0, iclass 29, count 2 2006.285.12:37:38.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:37:38.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.12:37:38.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.12:37:38.43#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:38.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:37:38.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:37:38.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:37:38.55#ibcon#enter wrdev, iclass 29, count 0 2006.285.12:37:38.55#ibcon#first serial, iclass 29, count 0 2006.285.12:37:38.55#ibcon#enter sib2, iclass 29, count 0 2006.285.12:37:38.55#ibcon#flushed, iclass 29, count 0 2006.285.12:37:38.55#ibcon#about to write, iclass 29, count 0 2006.285.12:37:38.55#ibcon#wrote, iclass 29, count 0 2006.285.12:37:38.55#ibcon#about to read 3, iclass 29, count 0 2006.285.12:37:38.57#ibcon#read 3, iclass 29, count 0 2006.285.12:37:38.57#ibcon#about to read 4, iclass 29, count 0 2006.285.12:37:38.57#ibcon#read 4, iclass 29, count 0 2006.285.12:37:38.57#ibcon#about to read 5, iclass 29, count 0 2006.285.12:37:38.57#ibcon#read 5, iclass 29, count 0 2006.285.12:37:38.57#ibcon#about to read 6, iclass 29, count 0 2006.285.12:37:38.57#ibcon#read 6, iclass 29, count 0 2006.285.12:37:38.57#ibcon#end of sib2, iclass 29, count 0 2006.285.12:37:38.57#ibcon#*mode == 0, iclass 29, count 0 2006.285.12:37:38.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.12:37:38.57#ibcon#[27=USB\r\n] 2006.285.12:37:38.57#ibcon#*before write, iclass 29, count 0 2006.285.12:37:38.57#ibcon#enter sib2, iclass 29, count 0 2006.285.12:37:38.57#ibcon#flushed, iclass 29, count 0 2006.285.12:37:38.57#ibcon#about to write, iclass 29, count 0 2006.285.12:37:38.57#ibcon#wrote, iclass 29, count 0 2006.285.12:37:38.57#ibcon#about to read 3, iclass 29, count 0 2006.285.12:37:38.60#ibcon#read 3, iclass 29, count 0 2006.285.12:37:38.60#ibcon#about to read 4, iclass 29, count 0 2006.285.12:37:38.60#ibcon#read 4, iclass 29, count 0 2006.285.12:37:38.60#ibcon#about to read 5, iclass 29, count 0 2006.285.12:37:38.60#ibcon#read 5, iclass 29, count 0 2006.285.12:37:38.60#ibcon#about to read 6, iclass 29, count 0 2006.285.12:37:38.60#ibcon#read 6, iclass 29, count 0 2006.285.12:37:38.60#ibcon#end of sib2, iclass 29, count 0 2006.285.12:37:38.60#ibcon#*after write, iclass 29, count 0 2006.285.12:37:38.60#ibcon#*before return 0, iclass 29, count 0 2006.285.12:37:38.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:37:38.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.12:37:38.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.12:37:38.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.12:37:38.60$vck44/vblo=5,709.99 2006.285.12:37:38.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.12:37:38.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.12:37:38.60#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:38.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:37:38.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:37:38.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:37:38.60#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:37:38.60#ibcon#first serial, iclass 31, count 0 2006.285.12:37:38.60#ibcon#enter sib2, iclass 31, count 0 2006.285.12:37:38.60#ibcon#flushed, iclass 31, count 0 2006.285.12:37:38.60#ibcon#about to write, iclass 31, count 0 2006.285.12:37:38.60#ibcon#wrote, iclass 31, count 0 2006.285.12:37:38.60#ibcon#about to read 3, iclass 31, count 0 2006.285.12:37:38.62#ibcon#read 3, iclass 31, count 0 2006.285.12:37:38.62#ibcon#about to read 4, iclass 31, count 0 2006.285.12:37:38.62#ibcon#read 4, iclass 31, count 0 2006.285.12:37:38.62#ibcon#about to read 5, iclass 31, count 0 2006.285.12:37:38.62#ibcon#read 5, iclass 31, count 0 2006.285.12:37:38.62#ibcon#about to read 6, iclass 31, count 0 2006.285.12:37:38.62#ibcon#read 6, iclass 31, count 0 2006.285.12:37:38.62#ibcon#end of sib2, iclass 31, count 0 2006.285.12:37:38.62#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:37:38.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:37:38.62#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.12:37:38.62#ibcon#*before write, iclass 31, count 0 2006.285.12:37:38.62#ibcon#enter sib2, iclass 31, count 0 2006.285.12:37:38.62#ibcon#flushed, iclass 31, count 0 2006.285.12:37:38.62#ibcon#about to write, iclass 31, count 0 2006.285.12:37:38.62#ibcon#wrote, iclass 31, count 0 2006.285.12:37:38.62#ibcon#about to read 3, iclass 31, count 0 2006.285.12:37:38.66#ibcon#read 3, iclass 31, count 0 2006.285.12:37:38.66#ibcon#about to read 4, iclass 31, count 0 2006.285.12:37:38.66#ibcon#read 4, iclass 31, count 0 2006.285.12:37:38.66#ibcon#about to read 5, iclass 31, count 0 2006.285.12:37:38.66#ibcon#read 5, iclass 31, count 0 2006.285.12:37:38.66#ibcon#about to read 6, iclass 31, count 0 2006.285.12:37:38.66#ibcon#read 6, iclass 31, count 0 2006.285.12:37:38.66#ibcon#end of sib2, iclass 31, count 0 2006.285.12:37:38.66#ibcon#*after write, iclass 31, count 0 2006.285.12:37:38.66#ibcon#*before return 0, iclass 31, count 0 2006.285.12:37:38.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:37:38.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:37:38.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:37:38.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:37:38.66$vck44/vb=5,4 2006.285.12:37:38.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.12:37:38.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.12:37:38.66#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:38.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:37:38.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:37:38.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:37:38.72#ibcon#enter wrdev, iclass 33, count 2 2006.285.12:37:38.72#ibcon#first serial, iclass 33, count 2 2006.285.12:37:38.72#ibcon#enter sib2, iclass 33, count 2 2006.285.12:37:38.72#ibcon#flushed, iclass 33, count 2 2006.285.12:37:38.72#ibcon#about to write, iclass 33, count 2 2006.285.12:37:38.72#ibcon#wrote, iclass 33, count 2 2006.285.12:37:38.72#ibcon#about to read 3, iclass 33, count 2 2006.285.12:37:38.74#ibcon#read 3, iclass 33, count 2 2006.285.12:37:38.74#ibcon#about to read 4, iclass 33, count 2 2006.285.12:37:38.74#ibcon#read 4, iclass 33, count 2 2006.285.12:37:38.74#ibcon#about to read 5, iclass 33, count 2 2006.285.12:37:38.74#ibcon#read 5, iclass 33, count 2 2006.285.12:37:38.74#ibcon#about to read 6, iclass 33, count 2 2006.285.12:37:38.74#ibcon#read 6, iclass 33, count 2 2006.285.12:37:38.74#ibcon#end of sib2, iclass 33, count 2 2006.285.12:37:38.74#ibcon#*mode == 0, iclass 33, count 2 2006.285.12:37:38.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.12:37:38.74#ibcon#[27=AT05-04\r\n] 2006.285.12:37:38.74#ibcon#*before write, iclass 33, count 2 2006.285.12:37:38.74#ibcon#enter sib2, iclass 33, count 2 2006.285.12:37:38.74#ibcon#flushed, iclass 33, count 2 2006.285.12:37:38.74#ibcon#about to write, iclass 33, count 2 2006.285.12:37:38.74#ibcon#wrote, iclass 33, count 2 2006.285.12:37:38.74#ibcon#about to read 3, iclass 33, count 2 2006.285.12:37:38.77#ibcon#read 3, iclass 33, count 2 2006.285.12:37:38.77#ibcon#about to read 4, iclass 33, count 2 2006.285.12:37:38.77#ibcon#read 4, iclass 33, count 2 2006.285.12:37:38.77#ibcon#about to read 5, iclass 33, count 2 2006.285.12:37:38.77#ibcon#read 5, iclass 33, count 2 2006.285.12:37:38.77#ibcon#about to read 6, iclass 33, count 2 2006.285.12:37:38.77#ibcon#read 6, iclass 33, count 2 2006.285.12:37:38.77#ibcon#end of sib2, iclass 33, count 2 2006.285.12:37:38.77#ibcon#*after write, iclass 33, count 2 2006.285.12:37:38.77#ibcon#*before return 0, iclass 33, count 2 2006.285.12:37:38.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:37:38.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.12:37:38.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.12:37:38.77#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:38.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:37:38.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:37:38.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:37:38.89#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:37:38.89#ibcon#first serial, iclass 33, count 0 2006.285.12:37:38.89#ibcon#enter sib2, iclass 33, count 0 2006.285.12:37:38.89#ibcon#flushed, iclass 33, count 0 2006.285.12:37:38.89#ibcon#about to write, iclass 33, count 0 2006.285.12:37:38.89#ibcon#wrote, iclass 33, count 0 2006.285.12:37:38.89#ibcon#about to read 3, iclass 33, count 0 2006.285.12:37:38.91#ibcon#read 3, iclass 33, count 0 2006.285.12:37:38.91#ibcon#about to read 4, iclass 33, count 0 2006.285.12:37:38.91#ibcon#read 4, iclass 33, count 0 2006.285.12:37:38.91#ibcon#about to read 5, iclass 33, count 0 2006.285.12:37:38.91#ibcon#read 5, iclass 33, count 0 2006.285.12:37:38.91#ibcon#about to read 6, iclass 33, count 0 2006.285.12:37:38.91#ibcon#read 6, iclass 33, count 0 2006.285.12:37:38.91#ibcon#end of sib2, iclass 33, count 0 2006.285.12:37:38.91#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:37:39.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:37:39.13#ibcon#[27=USB\r\n] 2006.285.12:37:39.13#ibcon#*before write, iclass 33, count 0 2006.285.12:37:39.13#ibcon#enter sib2, iclass 33, count 0 2006.285.12:37:39.13#ibcon#flushed, iclass 33, count 0 2006.285.12:37:39.13#ibcon#about to write, iclass 33, count 0 2006.285.12:37:39.13#ibcon#wrote, iclass 33, count 0 2006.285.12:37:39.13#ibcon#about to read 3, iclass 33, count 0 2006.285.12:37:39.15#ibcon#read 3, iclass 33, count 0 2006.285.12:37:39.15#ibcon#about to read 4, iclass 33, count 0 2006.285.12:37:39.15#ibcon#read 4, iclass 33, count 0 2006.285.12:37:39.15#ibcon#about to read 5, iclass 33, count 0 2006.285.12:37:39.15#ibcon#read 5, iclass 33, count 0 2006.285.12:37:39.15#ibcon#about to read 6, iclass 33, count 0 2006.285.12:37:39.15#ibcon#read 6, iclass 33, count 0 2006.285.12:37:39.15#ibcon#end of sib2, iclass 33, count 0 2006.285.12:37:39.15#ibcon#*after write, iclass 33, count 0 2006.285.12:37:39.15#ibcon#*before return 0, iclass 33, count 0 2006.285.12:37:39.15#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:37:39.15#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.12:37:39.15#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:37:39.15#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:37:39.15$vck44/vblo=6,719.99 2006.285.12:37:39.15#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.12:37:39.15#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.12:37:39.15#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:39.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:37:39.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:37:39.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:37:39.15#ibcon#enter wrdev, iclass 35, count 0 2006.285.12:37:39.15#ibcon#first serial, iclass 35, count 0 2006.285.12:37:39.15#ibcon#enter sib2, iclass 35, count 0 2006.285.12:37:39.15#ibcon#flushed, iclass 35, count 0 2006.285.12:37:39.15#ibcon#about to write, iclass 35, count 0 2006.285.12:37:39.15#ibcon#wrote, iclass 35, count 0 2006.285.12:37:39.15#ibcon#about to read 3, iclass 35, count 0 2006.285.12:37:39.17#ibcon#read 3, iclass 35, count 0 2006.285.12:37:39.17#ibcon#about to read 4, iclass 35, count 0 2006.285.12:37:39.17#ibcon#read 4, iclass 35, count 0 2006.285.12:37:39.17#ibcon#about to read 5, iclass 35, count 0 2006.285.12:37:39.17#ibcon#read 5, iclass 35, count 0 2006.285.12:37:39.17#ibcon#about to read 6, iclass 35, count 0 2006.285.12:37:39.17#ibcon#read 6, iclass 35, count 0 2006.285.12:37:39.17#ibcon#end of sib2, iclass 35, count 0 2006.285.12:37:39.17#ibcon#*mode == 0, iclass 35, count 0 2006.285.12:37:39.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.12:37:39.17#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.12:37:39.17#ibcon#*before write, iclass 35, count 0 2006.285.12:37:39.17#ibcon#enter sib2, iclass 35, count 0 2006.285.12:37:39.17#ibcon#flushed, iclass 35, count 0 2006.285.12:37:39.17#ibcon#about to write, iclass 35, count 0 2006.285.12:37:39.17#ibcon#wrote, iclass 35, count 0 2006.285.12:37:39.17#ibcon#about to read 3, iclass 35, count 0 2006.285.12:37:39.21#ibcon#read 3, iclass 35, count 0 2006.285.12:37:39.21#ibcon#about to read 4, iclass 35, count 0 2006.285.12:37:39.21#ibcon#read 4, iclass 35, count 0 2006.285.12:37:39.21#ibcon#about to read 5, iclass 35, count 0 2006.285.12:37:39.21#ibcon#read 5, iclass 35, count 0 2006.285.12:37:39.21#ibcon#about to read 6, iclass 35, count 0 2006.285.12:37:39.21#ibcon#read 6, iclass 35, count 0 2006.285.12:37:39.21#ibcon#end of sib2, iclass 35, count 0 2006.285.12:37:39.21#ibcon#*after write, iclass 35, count 0 2006.285.12:37:39.21#ibcon#*before return 0, iclass 35, count 0 2006.285.12:37:39.21#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:37:39.21#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.12:37:39.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.12:37:39.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.12:37:39.21$vck44/vb=6,3 2006.285.12:37:39.21#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.12:37:39.21#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.12:37:39.21#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:39.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:37:39.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:37:39.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:37:39.27#ibcon#enter wrdev, iclass 37, count 2 2006.285.12:37:39.27#ibcon#first serial, iclass 37, count 2 2006.285.12:37:39.27#ibcon#enter sib2, iclass 37, count 2 2006.285.12:37:39.27#ibcon#flushed, iclass 37, count 2 2006.285.12:37:39.27#ibcon#about to write, iclass 37, count 2 2006.285.12:37:39.27#ibcon#wrote, iclass 37, count 2 2006.285.12:37:39.27#ibcon#about to read 3, iclass 37, count 2 2006.285.12:37:39.29#ibcon#read 3, iclass 37, count 2 2006.285.12:37:39.29#ibcon#about to read 4, iclass 37, count 2 2006.285.12:37:39.29#ibcon#read 4, iclass 37, count 2 2006.285.12:37:39.29#ibcon#about to read 5, iclass 37, count 2 2006.285.12:37:39.29#ibcon#read 5, iclass 37, count 2 2006.285.12:37:39.29#ibcon#about to read 6, iclass 37, count 2 2006.285.12:37:39.29#ibcon#read 6, iclass 37, count 2 2006.285.12:37:39.29#ibcon#end of sib2, iclass 37, count 2 2006.285.12:37:39.29#ibcon#*mode == 0, iclass 37, count 2 2006.285.12:37:39.29#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.12:37:39.29#ibcon#[27=AT06-03\r\n] 2006.285.12:37:39.29#ibcon#*before write, iclass 37, count 2 2006.285.12:37:39.29#ibcon#enter sib2, iclass 37, count 2 2006.285.12:37:39.29#ibcon#flushed, iclass 37, count 2 2006.285.12:37:39.29#ibcon#about to write, iclass 37, count 2 2006.285.12:37:39.29#ibcon#wrote, iclass 37, count 2 2006.285.12:37:39.29#ibcon#about to read 3, iclass 37, count 2 2006.285.12:37:39.32#ibcon#read 3, iclass 37, count 2 2006.285.12:37:39.32#ibcon#about to read 4, iclass 37, count 2 2006.285.12:37:39.32#ibcon#read 4, iclass 37, count 2 2006.285.12:37:39.32#ibcon#about to read 5, iclass 37, count 2 2006.285.12:37:39.32#ibcon#read 5, iclass 37, count 2 2006.285.12:37:39.32#ibcon#about to read 6, iclass 37, count 2 2006.285.12:37:39.32#ibcon#read 6, iclass 37, count 2 2006.285.12:37:39.32#ibcon#end of sib2, iclass 37, count 2 2006.285.12:37:39.32#ibcon#*after write, iclass 37, count 2 2006.285.12:37:39.32#ibcon#*before return 0, iclass 37, count 2 2006.285.12:37:39.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:37:39.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.12:37:39.32#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.12:37:39.32#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:39.32#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:37:39.44#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:37:39.44#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:37:39.44#ibcon#enter wrdev, iclass 37, count 0 2006.285.12:37:39.44#ibcon#first serial, iclass 37, count 0 2006.285.12:37:39.44#ibcon#enter sib2, iclass 37, count 0 2006.285.12:37:39.44#ibcon#flushed, iclass 37, count 0 2006.285.12:37:39.44#ibcon#about to write, iclass 37, count 0 2006.285.12:37:39.44#ibcon#wrote, iclass 37, count 0 2006.285.12:37:39.44#ibcon#about to read 3, iclass 37, count 0 2006.285.12:37:39.46#ibcon#read 3, iclass 37, count 0 2006.285.12:37:39.46#ibcon#about to read 4, iclass 37, count 0 2006.285.12:37:39.46#ibcon#read 4, iclass 37, count 0 2006.285.12:37:39.46#ibcon#about to read 5, iclass 37, count 0 2006.285.12:37:39.46#ibcon#read 5, iclass 37, count 0 2006.285.12:37:39.46#ibcon#about to read 6, iclass 37, count 0 2006.285.12:37:39.46#ibcon#read 6, iclass 37, count 0 2006.285.12:37:39.46#ibcon#end of sib2, iclass 37, count 0 2006.285.12:37:39.46#ibcon#*mode == 0, iclass 37, count 0 2006.285.12:37:39.46#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.12:37:39.46#ibcon#[27=USB\r\n] 2006.285.12:37:39.46#ibcon#*before write, iclass 37, count 0 2006.285.12:37:39.46#ibcon#enter sib2, iclass 37, count 0 2006.285.12:37:39.46#ibcon#flushed, iclass 37, count 0 2006.285.12:37:39.46#ibcon#about to write, iclass 37, count 0 2006.285.12:37:39.46#ibcon#wrote, iclass 37, count 0 2006.285.12:37:39.46#ibcon#about to read 3, iclass 37, count 0 2006.285.12:37:39.49#ibcon#read 3, iclass 37, count 0 2006.285.12:37:39.49#ibcon#about to read 4, iclass 37, count 0 2006.285.12:37:39.49#ibcon#read 4, iclass 37, count 0 2006.285.12:37:39.49#ibcon#about to read 5, iclass 37, count 0 2006.285.12:37:39.49#ibcon#read 5, iclass 37, count 0 2006.285.12:37:39.49#ibcon#about to read 6, iclass 37, count 0 2006.285.12:37:39.49#ibcon#read 6, iclass 37, count 0 2006.285.12:37:39.49#ibcon#end of sib2, iclass 37, count 0 2006.285.12:37:39.49#ibcon#*after write, iclass 37, count 0 2006.285.12:37:39.49#ibcon#*before return 0, iclass 37, count 0 2006.285.12:37:39.49#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:37:39.49#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.12:37:39.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.12:37:39.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.12:37:39.49$vck44/vblo=7,734.99 2006.285.12:37:39.49#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.12:37:39.49#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.12:37:39.49#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:39.49#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:37:39.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:37:39.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:37:39.49#ibcon#enter wrdev, iclass 39, count 0 2006.285.12:37:39.49#ibcon#first serial, iclass 39, count 0 2006.285.12:37:39.49#ibcon#enter sib2, iclass 39, count 0 2006.285.12:37:39.49#ibcon#flushed, iclass 39, count 0 2006.285.12:37:39.49#ibcon#about to write, iclass 39, count 0 2006.285.12:37:39.49#ibcon#wrote, iclass 39, count 0 2006.285.12:37:39.49#ibcon#about to read 3, iclass 39, count 0 2006.285.12:37:39.51#ibcon#read 3, iclass 39, count 0 2006.285.12:37:39.51#ibcon#about to read 4, iclass 39, count 0 2006.285.12:37:39.51#ibcon#read 4, iclass 39, count 0 2006.285.12:37:39.51#ibcon#about to read 5, iclass 39, count 0 2006.285.12:37:39.51#ibcon#read 5, iclass 39, count 0 2006.285.12:37:39.51#ibcon#about to read 6, iclass 39, count 0 2006.285.12:37:39.51#ibcon#read 6, iclass 39, count 0 2006.285.12:37:39.51#ibcon#end of sib2, iclass 39, count 0 2006.285.12:37:39.51#ibcon#*mode == 0, iclass 39, count 0 2006.285.12:37:39.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.12:37:39.51#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.12:37:39.51#ibcon#*before write, iclass 39, count 0 2006.285.12:37:39.51#ibcon#enter sib2, iclass 39, count 0 2006.285.12:37:39.51#ibcon#flushed, iclass 39, count 0 2006.285.12:37:39.51#ibcon#about to write, iclass 39, count 0 2006.285.12:37:39.51#ibcon#wrote, iclass 39, count 0 2006.285.12:37:39.51#ibcon#about to read 3, iclass 39, count 0 2006.285.12:37:39.55#ibcon#read 3, iclass 39, count 0 2006.285.12:37:39.55#ibcon#about to read 4, iclass 39, count 0 2006.285.12:37:39.55#ibcon#read 4, iclass 39, count 0 2006.285.12:37:39.55#ibcon#about to read 5, iclass 39, count 0 2006.285.12:37:39.55#ibcon#read 5, iclass 39, count 0 2006.285.12:37:39.55#ibcon#about to read 6, iclass 39, count 0 2006.285.12:37:39.55#ibcon#read 6, iclass 39, count 0 2006.285.12:37:39.55#ibcon#end of sib2, iclass 39, count 0 2006.285.12:37:39.55#ibcon#*after write, iclass 39, count 0 2006.285.12:37:39.55#ibcon#*before return 0, iclass 39, count 0 2006.285.12:37:39.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:37:39.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.12:37:39.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.12:37:39.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.12:37:39.55$vck44/vb=7,4 2006.285.12:37:39.55#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.12:37:39.55#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.12:37:39.55#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:39.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:37:39.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:37:39.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:37:39.61#ibcon#enter wrdev, iclass 3, count 2 2006.285.12:37:39.61#ibcon#first serial, iclass 3, count 2 2006.285.12:37:39.61#ibcon#enter sib2, iclass 3, count 2 2006.285.12:37:39.61#ibcon#flushed, iclass 3, count 2 2006.285.12:37:39.61#ibcon#about to write, iclass 3, count 2 2006.285.12:37:39.61#ibcon#wrote, iclass 3, count 2 2006.285.12:37:39.61#ibcon#about to read 3, iclass 3, count 2 2006.285.12:37:39.63#ibcon#read 3, iclass 3, count 2 2006.285.12:37:39.63#ibcon#about to read 4, iclass 3, count 2 2006.285.12:37:39.63#ibcon#read 4, iclass 3, count 2 2006.285.12:37:39.63#ibcon#about to read 5, iclass 3, count 2 2006.285.12:37:39.63#ibcon#read 5, iclass 3, count 2 2006.285.12:37:39.63#ibcon#about to read 6, iclass 3, count 2 2006.285.12:37:39.63#ibcon#read 6, iclass 3, count 2 2006.285.12:37:39.63#ibcon#end of sib2, iclass 3, count 2 2006.285.12:37:39.63#ibcon#*mode == 0, iclass 3, count 2 2006.285.12:37:39.63#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.12:37:39.63#ibcon#[27=AT07-04\r\n] 2006.285.12:37:39.63#ibcon#*before write, iclass 3, count 2 2006.285.12:37:39.63#ibcon#enter sib2, iclass 3, count 2 2006.285.12:37:39.63#ibcon#flushed, iclass 3, count 2 2006.285.12:37:39.63#ibcon#about to write, iclass 3, count 2 2006.285.12:37:39.63#ibcon#wrote, iclass 3, count 2 2006.285.12:37:39.63#ibcon#about to read 3, iclass 3, count 2 2006.285.12:37:39.66#ibcon#read 3, iclass 3, count 2 2006.285.12:37:39.66#ibcon#about to read 4, iclass 3, count 2 2006.285.12:37:39.66#ibcon#read 4, iclass 3, count 2 2006.285.12:37:39.66#ibcon#about to read 5, iclass 3, count 2 2006.285.12:37:39.66#ibcon#read 5, iclass 3, count 2 2006.285.12:37:39.66#ibcon#about to read 6, iclass 3, count 2 2006.285.12:37:39.66#ibcon#read 6, iclass 3, count 2 2006.285.12:37:39.66#ibcon#end of sib2, iclass 3, count 2 2006.285.12:37:39.66#ibcon#*after write, iclass 3, count 2 2006.285.12:37:39.66#ibcon#*before return 0, iclass 3, count 2 2006.285.12:37:39.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:37:39.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.12:37:39.66#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.12:37:39.66#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:39.66#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:37:39.78#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:37:39.78#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:37:39.78#ibcon#enter wrdev, iclass 3, count 0 2006.285.12:37:39.78#ibcon#first serial, iclass 3, count 0 2006.285.12:37:39.78#ibcon#enter sib2, iclass 3, count 0 2006.285.12:37:39.78#ibcon#flushed, iclass 3, count 0 2006.285.12:37:39.78#ibcon#about to write, iclass 3, count 0 2006.285.12:37:39.78#ibcon#wrote, iclass 3, count 0 2006.285.12:37:39.78#ibcon#about to read 3, iclass 3, count 0 2006.285.12:37:39.80#ibcon#read 3, iclass 3, count 0 2006.285.12:37:39.80#ibcon#about to read 4, iclass 3, count 0 2006.285.12:37:39.80#ibcon#read 4, iclass 3, count 0 2006.285.12:37:39.80#ibcon#about to read 5, iclass 3, count 0 2006.285.12:37:39.80#ibcon#read 5, iclass 3, count 0 2006.285.12:37:39.80#ibcon#about to read 6, iclass 3, count 0 2006.285.12:37:39.80#ibcon#read 6, iclass 3, count 0 2006.285.12:37:39.80#ibcon#end of sib2, iclass 3, count 0 2006.285.12:37:39.80#ibcon#*mode == 0, iclass 3, count 0 2006.285.12:37:39.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.12:37:39.80#ibcon#[27=USB\r\n] 2006.285.12:37:39.80#ibcon#*before write, iclass 3, count 0 2006.285.12:37:39.80#ibcon#enter sib2, iclass 3, count 0 2006.285.12:37:39.80#ibcon#flushed, iclass 3, count 0 2006.285.12:37:39.80#ibcon#about to write, iclass 3, count 0 2006.285.12:37:39.80#ibcon#wrote, iclass 3, count 0 2006.285.12:37:39.80#ibcon#about to read 3, iclass 3, count 0 2006.285.12:37:39.83#ibcon#read 3, iclass 3, count 0 2006.285.12:37:39.83#ibcon#about to read 4, iclass 3, count 0 2006.285.12:37:39.83#ibcon#read 4, iclass 3, count 0 2006.285.12:37:39.83#ibcon#about to read 5, iclass 3, count 0 2006.285.12:37:39.83#ibcon#read 5, iclass 3, count 0 2006.285.12:37:39.83#ibcon#about to read 6, iclass 3, count 0 2006.285.12:37:39.83#ibcon#read 6, iclass 3, count 0 2006.285.12:37:39.83#ibcon#end of sib2, iclass 3, count 0 2006.285.12:37:39.83#ibcon#*after write, iclass 3, count 0 2006.285.12:37:39.83#ibcon#*before return 0, iclass 3, count 0 2006.285.12:37:39.83#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:37:39.83#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.12:37:39.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.12:37:39.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.12:37:39.83$vck44/vblo=8,744.99 2006.285.12:37:39.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.12:37:39.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.12:37:39.83#ibcon#ireg 17 cls_cnt 0 2006.285.12:37:39.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:37:39.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:37:39.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:37:39.83#ibcon#enter wrdev, iclass 5, count 0 2006.285.12:37:39.83#ibcon#first serial, iclass 5, count 0 2006.285.12:37:39.83#ibcon#enter sib2, iclass 5, count 0 2006.285.12:37:39.83#ibcon#flushed, iclass 5, count 0 2006.285.12:37:39.83#ibcon#about to write, iclass 5, count 0 2006.285.12:37:39.83#ibcon#wrote, iclass 5, count 0 2006.285.12:37:39.83#ibcon#about to read 3, iclass 5, count 0 2006.285.12:37:39.85#ibcon#read 3, iclass 5, count 0 2006.285.12:37:39.88#ibcon#about to read 4, iclass 5, count 0 2006.285.12:37:39.88#ibcon#read 4, iclass 5, count 0 2006.285.12:37:39.88#ibcon#about to read 5, iclass 5, count 0 2006.285.12:37:39.88#ibcon#read 5, iclass 5, count 0 2006.285.12:37:39.88#ibcon#about to read 6, iclass 5, count 0 2006.285.12:37:39.88#ibcon#read 6, iclass 5, count 0 2006.285.12:37:39.88#ibcon#end of sib2, iclass 5, count 0 2006.285.12:37:39.88#ibcon#*mode == 0, iclass 5, count 0 2006.285.12:37:39.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.12:37:39.88#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.12:37:39.88#ibcon#*before write, iclass 5, count 0 2006.285.12:37:39.88#ibcon#enter sib2, iclass 5, count 0 2006.285.12:37:39.88#ibcon#flushed, iclass 5, count 0 2006.285.12:37:39.88#ibcon#about to write, iclass 5, count 0 2006.285.12:37:39.88#ibcon#wrote, iclass 5, count 0 2006.285.12:37:39.88#ibcon#about to read 3, iclass 5, count 0 2006.285.12:37:39.92#ibcon#read 3, iclass 5, count 0 2006.285.12:37:39.92#ibcon#about to read 4, iclass 5, count 0 2006.285.12:37:39.92#ibcon#read 4, iclass 5, count 0 2006.285.12:37:39.92#ibcon#about to read 5, iclass 5, count 0 2006.285.12:37:39.92#ibcon#read 5, iclass 5, count 0 2006.285.12:37:39.92#ibcon#about to read 6, iclass 5, count 0 2006.285.12:37:39.92#ibcon#read 6, iclass 5, count 0 2006.285.12:37:39.92#ibcon#end of sib2, iclass 5, count 0 2006.285.12:37:39.92#ibcon#*after write, iclass 5, count 0 2006.285.12:37:39.92#ibcon#*before return 0, iclass 5, count 0 2006.285.12:37:39.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:37:39.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.12:37:39.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.12:37:39.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.12:37:39.92$vck44/vb=8,4 2006.285.12:37:39.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.12:37:39.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.12:37:39.92#ibcon#ireg 11 cls_cnt 2 2006.285.12:37:39.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:37:39.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:37:39.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:37:39.95#ibcon#enter wrdev, iclass 7, count 2 2006.285.12:37:39.95#ibcon#first serial, iclass 7, count 2 2006.285.12:37:39.95#ibcon#enter sib2, iclass 7, count 2 2006.285.12:37:39.95#ibcon#flushed, iclass 7, count 2 2006.285.12:37:39.95#ibcon#about to write, iclass 7, count 2 2006.285.12:37:39.95#ibcon#wrote, iclass 7, count 2 2006.285.12:37:39.95#ibcon#about to read 3, iclass 7, count 2 2006.285.12:37:39.97#ibcon#read 3, iclass 7, count 2 2006.285.12:37:39.97#ibcon#about to read 4, iclass 7, count 2 2006.285.12:37:39.97#ibcon#read 4, iclass 7, count 2 2006.285.12:37:39.97#ibcon#about to read 5, iclass 7, count 2 2006.285.12:37:39.97#ibcon#read 5, iclass 7, count 2 2006.285.12:37:39.97#ibcon#about to read 6, iclass 7, count 2 2006.285.12:37:39.97#ibcon#read 6, iclass 7, count 2 2006.285.12:37:39.97#ibcon#end of sib2, iclass 7, count 2 2006.285.12:37:39.97#ibcon#*mode == 0, iclass 7, count 2 2006.285.12:37:39.97#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.12:37:39.97#ibcon#[27=AT08-04\r\n] 2006.285.12:37:39.97#ibcon#*before write, iclass 7, count 2 2006.285.12:37:39.97#ibcon#enter sib2, iclass 7, count 2 2006.285.12:37:39.97#ibcon#flushed, iclass 7, count 2 2006.285.12:37:39.97#ibcon#about to write, iclass 7, count 2 2006.285.12:37:39.97#ibcon#wrote, iclass 7, count 2 2006.285.12:37:39.97#ibcon#about to read 3, iclass 7, count 2 2006.285.12:37:40.00#ibcon#read 3, iclass 7, count 2 2006.285.12:37:40.00#ibcon#about to read 4, iclass 7, count 2 2006.285.12:37:40.00#ibcon#read 4, iclass 7, count 2 2006.285.12:37:40.00#ibcon#about to read 5, iclass 7, count 2 2006.285.12:37:40.00#ibcon#read 5, iclass 7, count 2 2006.285.12:37:40.00#ibcon#about to read 6, iclass 7, count 2 2006.285.12:37:40.00#ibcon#read 6, iclass 7, count 2 2006.285.12:37:40.00#ibcon#end of sib2, iclass 7, count 2 2006.285.12:37:40.00#ibcon#*after write, iclass 7, count 2 2006.285.12:37:40.00#ibcon#*before return 0, iclass 7, count 2 2006.285.12:37:40.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:37:40.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.12:37:40.00#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.12:37:40.00#ibcon#ireg 7 cls_cnt 0 2006.285.12:37:40.00#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:37:40.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:37:40.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:37:40.12#ibcon#enter wrdev, iclass 7, count 0 2006.285.12:37:40.12#ibcon#first serial, iclass 7, count 0 2006.285.12:37:40.12#ibcon#enter sib2, iclass 7, count 0 2006.285.12:37:40.12#ibcon#flushed, iclass 7, count 0 2006.285.12:37:40.12#ibcon#about to write, iclass 7, count 0 2006.285.12:37:40.12#ibcon#wrote, iclass 7, count 0 2006.285.12:37:40.12#ibcon#about to read 3, iclass 7, count 0 2006.285.12:37:40.14#ibcon#read 3, iclass 7, count 0 2006.285.12:37:40.14#ibcon#about to read 4, iclass 7, count 0 2006.285.12:37:40.14#ibcon#read 4, iclass 7, count 0 2006.285.12:37:40.14#ibcon#about to read 5, iclass 7, count 0 2006.285.12:37:40.14#ibcon#read 5, iclass 7, count 0 2006.285.12:37:40.14#ibcon#about to read 6, iclass 7, count 0 2006.285.12:37:40.14#ibcon#read 6, iclass 7, count 0 2006.285.12:37:40.14#ibcon#end of sib2, iclass 7, count 0 2006.285.12:37:40.14#ibcon#*mode == 0, iclass 7, count 0 2006.285.12:37:40.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.12:37:40.14#ibcon#[27=USB\r\n] 2006.285.12:37:40.14#ibcon#*before write, iclass 7, count 0 2006.285.12:37:40.14#ibcon#enter sib2, iclass 7, count 0 2006.285.12:37:40.14#ibcon#flushed, iclass 7, count 0 2006.285.12:37:40.14#ibcon#about to write, iclass 7, count 0 2006.285.12:37:40.14#ibcon#wrote, iclass 7, count 0 2006.285.12:37:40.14#ibcon#about to read 3, iclass 7, count 0 2006.285.12:37:40.17#ibcon#read 3, iclass 7, count 0 2006.285.12:37:40.17#ibcon#about to read 4, iclass 7, count 0 2006.285.12:37:40.17#ibcon#read 4, iclass 7, count 0 2006.285.12:37:40.17#ibcon#about to read 5, iclass 7, count 0 2006.285.12:37:40.17#ibcon#read 5, iclass 7, count 0 2006.285.12:37:40.17#ibcon#about to read 6, iclass 7, count 0 2006.285.12:37:40.17#ibcon#read 6, iclass 7, count 0 2006.285.12:37:40.17#ibcon#end of sib2, iclass 7, count 0 2006.285.12:37:40.17#ibcon#*after write, iclass 7, count 0 2006.285.12:37:40.17#ibcon#*before return 0, iclass 7, count 0 2006.285.12:37:40.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:37:40.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.12:37:40.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.12:37:40.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.12:37:40.17$vck44/vabw=wide 2006.285.12:37:40.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.12:37:40.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.12:37:40.17#ibcon#ireg 8 cls_cnt 0 2006.285.12:37:40.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:37:40.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:37:40.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:37:40.17#ibcon#enter wrdev, iclass 11, count 0 2006.285.12:37:40.17#ibcon#first serial, iclass 11, count 0 2006.285.12:37:40.17#ibcon#enter sib2, iclass 11, count 0 2006.285.12:37:40.17#ibcon#flushed, iclass 11, count 0 2006.285.12:37:40.17#ibcon#about to write, iclass 11, count 0 2006.285.12:37:40.17#ibcon#wrote, iclass 11, count 0 2006.285.12:37:40.17#ibcon#about to read 3, iclass 11, count 0 2006.285.12:37:40.19#ibcon#read 3, iclass 11, count 0 2006.285.12:37:40.19#ibcon#about to read 4, iclass 11, count 0 2006.285.12:37:40.19#ibcon#read 4, iclass 11, count 0 2006.285.12:37:40.19#ibcon#about to read 5, iclass 11, count 0 2006.285.12:37:40.19#ibcon#read 5, iclass 11, count 0 2006.285.12:37:40.19#ibcon#about to read 6, iclass 11, count 0 2006.285.12:37:40.19#ibcon#read 6, iclass 11, count 0 2006.285.12:37:40.19#ibcon#end of sib2, iclass 11, count 0 2006.285.12:37:40.19#ibcon#*mode == 0, iclass 11, count 0 2006.285.12:37:40.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.12:37:40.19#ibcon#[25=BW32\r\n] 2006.285.12:37:40.19#ibcon#*before write, iclass 11, count 0 2006.285.12:37:40.19#ibcon#enter sib2, iclass 11, count 0 2006.285.12:37:40.19#ibcon#flushed, iclass 11, count 0 2006.285.12:37:40.19#ibcon#about to write, iclass 11, count 0 2006.285.12:37:40.19#ibcon#wrote, iclass 11, count 0 2006.285.12:37:40.19#ibcon#about to read 3, iclass 11, count 0 2006.285.12:37:40.22#ibcon#read 3, iclass 11, count 0 2006.285.12:37:40.22#ibcon#about to read 4, iclass 11, count 0 2006.285.12:37:40.22#ibcon#read 4, iclass 11, count 0 2006.285.12:37:40.22#ibcon#about to read 5, iclass 11, count 0 2006.285.12:37:40.22#ibcon#read 5, iclass 11, count 0 2006.285.12:37:40.22#ibcon#about to read 6, iclass 11, count 0 2006.285.12:37:40.22#ibcon#read 6, iclass 11, count 0 2006.285.12:37:40.22#ibcon#end of sib2, iclass 11, count 0 2006.285.12:37:40.22#ibcon#*after write, iclass 11, count 0 2006.285.12:37:40.22#ibcon#*before return 0, iclass 11, count 0 2006.285.12:37:40.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:37:40.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.12:37:40.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.12:37:40.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.12:37:40.22$vck44/vbbw=wide 2006.285.12:37:40.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.12:37:40.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.12:37:40.22#ibcon#ireg 8 cls_cnt 0 2006.285.12:37:40.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:37:40.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:37:40.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:37:40.29#ibcon#enter wrdev, iclass 13, count 0 2006.285.12:37:40.29#ibcon#first serial, iclass 13, count 0 2006.285.12:37:40.29#ibcon#enter sib2, iclass 13, count 0 2006.285.12:37:40.29#ibcon#flushed, iclass 13, count 0 2006.285.12:37:40.29#ibcon#about to write, iclass 13, count 0 2006.285.12:37:40.29#ibcon#wrote, iclass 13, count 0 2006.285.12:37:40.29#ibcon#about to read 3, iclass 13, count 0 2006.285.12:37:40.31#ibcon#read 3, iclass 13, count 0 2006.285.12:37:40.31#ibcon#about to read 4, iclass 13, count 0 2006.285.12:37:40.31#ibcon#read 4, iclass 13, count 0 2006.285.12:37:40.31#ibcon#about to read 5, iclass 13, count 0 2006.285.12:37:40.31#ibcon#read 5, iclass 13, count 0 2006.285.12:37:40.31#ibcon#about to read 6, iclass 13, count 0 2006.285.12:37:40.31#ibcon#read 6, iclass 13, count 0 2006.285.12:37:40.31#ibcon#end of sib2, iclass 13, count 0 2006.285.12:37:40.31#ibcon#*mode == 0, iclass 13, count 0 2006.285.12:37:40.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.12:37:40.31#ibcon#[27=BW32\r\n] 2006.285.12:37:40.31#ibcon#*before write, iclass 13, count 0 2006.285.12:37:40.31#ibcon#enter sib2, iclass 13, count 0 2006.285.12:37:40.31#ibcon#flushed, iclass 13, count 0 2006.285.12:37:40.31#ibcon#about to write, iclass 13, count 0 2006.285.12:37:40.31#ibcon#wrote, iclass 13, count 0 2006.285.12:37:40.31#ibcon#about to read 3, iclass 13, count 0 2006.285.12:37:40.34#ibcon#read 3, iclass 13, count 0 2006.285.12:37:40.34#ibcon#about to read 4, iclass 13, count 0 2006.285.12:37:40.34#ibcon#read 4, iclass 13, count 0 2006.285.12:37:40.34#ibcon#about to read 5, iclass 13, count 0 2006.285.12:37:40.34#ibcon#read 5, iclass 13, count 0 2006.285.12:37:40.34#ibcon#about to read 6, iclass 13, count 0 2006.285.12:37:40.34#ibcon#read 6, iclass 13, count 0 2006.285.12:37:40.34#ibcon#end of sib2, iclass 13, count 0 2006.285.12:37:40.34#ibcon#*after write, iclass 13, count 0 2006.285.12:37:40.34#ibcon#*before return 0, iclass 13, count 0 2006.285.12:37:40.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:37:40.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:37:40.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.12:37:40.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.12:37:40.34$setupk4/ifdk4 2006.285.12:37:40.34$ifdk4/lo= 2006.285.12:37:40.34$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.12:37:40.34$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.12:37:40.34$ifdk4/patch= 2006.285.12:37:40.34$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.12:37:40.34$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.12:37:40.34$setupk4/!*+20s 2006.285.12:37:44.44#abcon#<5=/04 1.4 2.2 18.85 961015.4\r\n> 2006.285.12:37:44.46#abcon#{5=INTERFACE CLEAR} 2006.285.12:37:44.52#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:37:52.13#trakl#Source acquired 2006.285.12:37:52.13#flagr#flagr/antenna,acquired 2006.285.12:37:53.96$setupk4/"tpicd 2006.285.12:37:53.96$setupk4/echo=off 2006.285.12:37:53.96$setupk4/xlog=off 2006.285.12:37:53.96:!2006.285.12:45:36 2006.285.12:45:36.00:preob 2006.285.12:45:36.13/onsource/TRACKING 2006.285.12:45:36.13:!2006.285.12:45:46 2006.285.12:45:46.00:"tape 2006.285.12:45:46.00:"st=record 2006.285.12:45:46.00:data_valid=on 2006.285.12:45:46.00:midob 2006.285.12:45:46.13/onsource/TRACKING 2006.285.12:45:46.13/wx/18.93,1015.4,96 2006.285.12:45:46.23/cable/+6.4947E-03 2006.285.12:45:47.32/va/01,07,usb,yes,34,37 2006.285.12:45:47.32/va/02,06,usb,yes,34,35 2006.285.12:45:47.32/va/03,07,usb,yes,34,36 2006.285.12:45:47.32/va/04,06,usb,yes,36,37 2006.285.12:45:47.32/va/05,03,usb,yes,35,35 2006.285.12:45:47.32/va/06,04,usb,yes,32,31 2006.285.12:45:47.32/va/07,04,usb,yes,32,33 2006.285.12:45:47.32/va/08,03,usb,yes,33,40 2006.285.12:45:47.55/valo/01,524.99,yes,locked 2006.285.12:45:47.55/valo/02,534.99,yes,locked 2006.285.12:45:47.55/valo/03,564.99,yes,locked 2006.285.12:45:47.55/valo/04,624.99,yes,locked 2006.285.12:45:47.55/valo/05,734.99,yes,locked 2006.285.12:45:47.55/valo/06,814.99,yes,locked 2006.285.12:45:47.55/valo/07,864.99,yes,locked 2006.285.12:45:47.55/valo/08,884.99,yes,locked 2006.285.12:45:48.64/vb/01,04,usb,yes,31,29 2006.285.12:45:48.64/vb/02,05,usb,yes,30,29 2006.285.12:45:48.64/vb/03,04,usb,yes,31,34 2006.285.12:45:48.64/vb/04,05,usb,yes,31,30 2006.285.12:45:48.64/vb/05,04,usb,yes,27,30 2006.285.12:45:48.64/vb/06,03,usb,yes,39,35 2006.285.12:45:48.64/vb/07,04,usb,yes,32,31 2006.285.12:45:48.64/vb/08,04,usb,yes,29,32 2006.285.12:45:48.87/vblo/01,629.99,yes,locked 2006.285.12:45:48.87/vblo/02,634.99,yes,locked 2006.285.12:45:48.87/vblo/03,649.99,yes,locked 2006.285.12:45:48.87/vblo/04,679.99,yes,locked 2006.285.12:45:48.87/vblo/05,709.99,yes,locked 2006.285.12:45:48.87/vblo/06,719.99,yes,locked 2006.285.12:45:48.87/vblo/07,734.99,yes,locked 2006.285.12:45:48.87/vblo/08,744.99,yes,locked 2006.285.12:45:49.02/vabw/8 2006.285.12:45:49.17/vbbw/8 2006.285.12:45:49.26/xfe/off,on,12.2 2006.285.12:45:49.64/ifatt/23,28,28,28 2006.285.12:45:50.08/fmout-gps/S +2.58E-07 2006.285.12:45:50.10:!2006.285.12:48:46 2006.285.12:48:46.00:data_valid=off 2006.285.12:48:46.00:"et 2006.285.12:48:46.00:!+3s 2006.285.12:48:49.01:"tape 2006.285.12:48:49.01:postob 2006.285.12:48:49.23/cable/+6.4958E-03 2006.285.12:48:49.23/wx/18.95,1015.4,96 2006.285.12:48:50.08/fmout-gps/S +2.69E-07 2006.285.12:48:50.08:scan_name=285-1251,jd0610,170 2006.285.12:48:50.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.285.12:48:50.14#flagr#flagr/antenna,new-source 2006.285.12:48:51.14:checkk5 2006.285.12:48:51.59/chk_autoobs//k5ts1/ autoobs is running! 2006.285.12:48:51.98/chk_autoobs//k5ts2/ autoobs is running! 2006.285.12:48:52.38/chk_autoobs//k5ts3/ autoobs is running! 2006.285.12:48:52.92/chk_autoobs//k5ts4/ autoobs is running! 2006.285.12:48:53.25/chk_obsdata//k5ts1/T2851245??a.dat file size is correct (nominal:720MB, actual:716MB). 2006.285.12:48:53.82/chk_obsdata//k5ts2/T2851245??b.dat file size is correct (nominal:720MB, actual:716MB). 2006.285.12:48:54.21/chk_obsdata//k5ts3/T2851245??c.dat file size is correct (nominal:720MB, actual:716MB). 2006.285.12:48:54.79/chk_obsdata//k5ts4/T2851245??d.dat file size is correct (nominal:720MB, actual:716MB). 2006.285.12:48:55.69/k5log//k5ts1_log_newline 2006.285.12:48:56.50/k5log//k5ts2_log_newline 2006.285.12:48:57.30/k5log//k5ts3_log_newline 2006.285.12:48:58.07/k5log//k5ts4_log_newline 2006.285.12:48:58.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.12:48:58.09:setupk4=1 2006.285.12:48:58.09$setupk4/echo=on 2006.285.12:48:58.09$setupk4/pcalon 2006.285.12:48:58.09$pcalon/"no phase cal control is implemented here 2006.285.12:48:58.09$setupk4/"tpicd=stop 2006.285.12:48:58.09$setupk4/"rec=synch_on 2006.285.12:48:58.09$setupk4/"rec_mode=128 2006.285.12:48:58.09$setupk4/!* 2006.285.12:48:58.09$setupk4/recpk4 2006.285.12:48:58.09$recpk4/recpatch= 2006.285.12:48:58.09$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.12:48:58.09$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.12:48:58.09$setupk4/vck44 2006.285.12:48:58.09$vck44/valo=1,524.99 2006.285.12:48:58.10#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.12:48:58.10#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.12:48:58.10#ibcon#ireg 17 cls_cnt 0 2006.285.12:48:58.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:48:58.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:48:58.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:48:58.10#ibcon#enter wrdev, iclass 34, count 0 2006.285.12:48:58.10#ibcon#first serial, iclass 34, count 0 2006.285.12:48:58.10#ibcon#enter sib2, iclass 34, count 0 2006.285.12:48:58.10#ibcon#flushed, iclass 34, count 0 2006.285.12:48:58.10#ibcon#about to write, iclass 34, count 0 2006.285.12:48:58.10#ibcon#wrote, iclass 34, count 0 2006.285.12:48:58.10#ibcon#about to read 3, iclass 34, count 0 2006.285.12:48:58.11#ibcon#read 3, iclass 34, count 0 2006.285.12:48:58.11#ibcon#about to read 4, iclass 34, count 0 2006.285.12:48:58.11#ibcon#read 4, iclass 34, count 0 2006.285.12:48:58.11#ibcon#about to read 5, iclass 34, count 0 2006.285.12:48:58.11#ibcon#read 5, iclass 34, count 0 2006.285.12:48:58.11#ibcon#about to read 6, iclass 34, count 0 2006.285.12:48:58.11#ibcon#read 6, iclass 34, count 0 2006.285.12:48:58.11#ibcon#end of sib2, iclass 34, count 0 2006.285.12:48:58.11#ibcon#*mode == 0, iclass 34, count 0 2006.285.12:48:58.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.12:48:58.11#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.12:48:58.11#ibcon#*before write, iclass 34, count 0 2006.285.12:48:58.11#ibcon#enter sib2, iclass 34, count 0 2006.285.12:48:58.11#ibcon#flushed, iclass 34, count 0 2006.285.12:48:58.11#ibcon#about to write, iclass 34, count 0 2006.285.12:48:58.11#ibcon#wrote, iclass 34, count 0 2006.285.12:48:58.11#ibcon#about to read 3, iclass 34, count 0 2006.285.12:48:58.16#ibcon#read 3, iclass 34, count 0 2006.285.12:48:58.16#ibcon#about to read 4, iclass 34, count 0 2006.285.12:48:58.16#ibcon#read 4, iclass 34, count 0 2006.285.12:48:58.16#ibcon#about to read 5, iclass 34, count 0 2006.285.12:48:58.16#ibcon#read 5, iclass 34, count 0 2006.285.12:48:58.16#ibcon#about to read 6, iclass 34, count 0 2006.285.12:48:58.16#ibcon#read 6, iclass 34, count 0 2006.285.12:48:58.16#ibcon#end of sib2, iclass 34, count 0 2006.285.12:48:58.16#ibcon#*after write, iclass 34, count 0 2006.285.12:48:58.16#ibcon#*before return 0, iclass 34, count 0 2006.285.12:48:58.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:48:58.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:48:58.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.12:48:58.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.12:48:58.16$vck44/va=1,7 2006.285.12:48:58.16#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.12:48:58.16#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.12:48:58.16#ibcon#ireg 11 cls_cnt 2 2006.285.12:48:58.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:48:58.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:48:58.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:48:58.16#ibcon#enter wrdev, iclass 36, count 2 2006.285.12:48:58.16#ibcon#first serial, iclass 36, count 2 2006.285.12:48:58.16#ibcon#enter sib2, iclass 36, count 2 2006.285.12:48:58.16#ibcon#flushed, iclass 36, count 2 2006.285.12:48:58.16#ibcon#about to write, iclass 36, count 2 2006.285.12:48:58.16#ibcon#wrote, iclass 36, count 2 2006.285.12:48:58.16#ibcon#about to read 3, iclass 36, count 2 2006.285.12:48:58.18#ibcon#read 3, iclass 36, count 2 2006.285.12:48:58.18#ibcon#about to read 4, iclass 36, count 2 2006.285.12:48:58.18#ibcon#read 4, iclass 36, count 2 2006.285.12:48:58.18#ibcon#about to read 5, iclass 36, count 2 2006.285.12:48:58.18#ibcon#read 5, iclass 36, count 2 2006.285.12:48:58.18#ibcon#about to read 6, iclass 36, count 2 2006.285.12:48:58.18#ibcon#read 6, iclass 36, count 2 2006.285.12:48:58.18#ibcon#end of sib2, iclass 36, count 2 2006.285.12:48:58.18#ibcon#*mode == 0, iclass 36, count 2 2006.285.12:48:58.18#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.12:48:58.18#ibcon#[25=AT01-07\r\n] 2006.285.12:48:58.18#ibcon#*before write, iclass 36, count 2 2006.285.12:48:58.18#ibcon#enter sib2, iclass 36, count 2 2006.285.12:48:58.18#ibcon#flushed, iclass 36, count 2 2006.285.12:48:58.18#ibcon#about to write, iclass 36, count 2 2006.285.12:48:58.18#ibcon#wrote, iclass 36, count 2 2006.285.12:48:58.18#ibcon#about to read 3, iclass 36, count 2 2006.285.12:48:58.21#ibcon#read 3, iclass 36, count 2 2006.285.12:48:58.21#ibcon#about to read 4, iclass 36, count 2 2006.285.12:48:58.21#ibcon#read 4, iclass 36, count 2 2006.285.12:48:58.21#ibcon#about to read 5, iclass 36, count 2 2006.285.12:48:58.21#ibcon#read 5, iclass 36, count 2 2006.285.12:48:58.21#ibcon#about to read 6, iclass 36, count 2 2006.285.12:48:58.21#ibcon#read 6, iclass 36, count 2 2006.285.12:48:58.21#ibcon#end of sib2, iclass 36, count 2 2006.285.12:48:58.21#ibcon#*after write, iclass 36, count 2 2006.285.12:48:58.21#ibcon#*before return 0, iclass 36, count 2 2006.285.12:48:58.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:48:58.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:48:58.21#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.12:48:58.21#ibcon#ireg 7 cls_cnt 0 2006.285.12:48:58.21#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:48:58.33#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:48:58.33#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:48:58.33#ibcon#enter wrdev, iclass 36, count 0 2006.285.12:48:58.33#ibcon#first serial, iclass 36, count 0 2006.285.12:48:58.33#ibcon#enter sib2, iclass 36, count 0 2006.285.12:48:58.33#ibcon#flushed, iclass 36, count 0 2006.285.12:48:58.33#ibcon#about to write, iclass 36, count 0 2006.285.12:48:58.33#ibcon#wrote, iclass 36, count 0 2006.285.12:48:58.33#ibcon#about to read 3, iclass 36, count 0 2006.285.12:48:58.35#ibcon#read 3, iclass 36, count 0 2006.285.12:48:58.35#ibcon#about to read 4, iclass 36, count 0 2006.285.12:48:58.35#ibcon#read 4, iclass 36, count 0 2006.285.12:48:58.35#ibcon#about to read 5, iclass 36, count 0 2006.285.12:48:58.35#ibcon#read 5, iclass 36, count 0 2006.285.12:48:58.35#ibcon#about to read 6, iclass 36, count 0 2006.285.12:48:58.35#ibcon#read 6, iclass 36, count 0 2006.285.12:48:58.35#ibcon#end of sib2, iclass 36, count 0 2006.285.12:48:58.35#ibcon#*mode == 0, iclass 36, count 0 2006.285.12:48:58.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.12:48:58.35#ibcon#[25=USB\r\n] 2006.285.12:48:58.35#ibcon#*before write, iclass 36, count 0 2006.285.12:48:58.35#ibcon#enter sib2, iclass 36, count 0 2006.285.12:48:58.35#ibcon#flushed, iclass 36, count 0 2006.285.12:48:58.35#ibcon#about to write, iclass 36, count 0 2006.285.12:48:58.35#ibcon#wrote, iclass 36, count 0 2006.285.12:48:58.35#ibcon#about to read 3, iclass 36, count 0 2006.285.12:48:58.38#ibcon#read 3, iclass 36, count 0 2006.285.12:48:58.38#ibcon#about to read 4, iclass 36, count 0 2006.285.12:48:58.38#ibcon#read 4, iclass 36, count 0 2006.285.12:48:58.38#ibcon#about to read 5, iclass 36, count 0 2006.285.12:48:58.38#ibcon#read 5, iclass 36, count 0 2006.285.12:48:58.38#ibcon#about to read 6, iclass 36, count 0 2006.285.12:48:58.38#ibcon#read 6, iclass 36, count 0 2006.285.12:48:58.38#ibcon#end of sib2, iclass 36, count 0 2006.285.12:48:58.38#ibcon#*after write, iclass 36, count 0 2006.285.12:48:58.38#ibcon#*before return 0, iclass 36, count 0 2006.285.12:48:58.38#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:48:58.38#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:48:58.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.12:48:58.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.12:48:58.38$vck44/valo=2,534.99 2006.285.12:48:58.38#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.12:48:58.38#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.12:48:58.38#ibcon#ireg 17 cls_cnt 0 2006.285.12:48:58.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:48:58.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:48:58.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:48:58.38#ibcon#enter wrdev, iclass 38, count 0 2006.285.12:48:58.38#ibcon#first serial, iclass 38, count 0 2006.285.12:48:58.38#ibcon#enter sib2, iclass 38, count 0 2006.285.12:48:58.38#ibcon#flushed, iclass 38, count 0 2006.285.12:48:58.38#ibcon#about to write, iclass 38, count 0 2006.285.12:48:58.38#ibcon#wrote, iclass 38, count 0 2006.285.12:48:58.38#ibcon#about to read 3, iclass 38, count 0 2006.285.12:48:58.40#ibcon#read 3, iclass 38, count 0 2006.285.12:48:58.40#ibcon#about to read 4, iclass 38, count 0 2006.285.12:48:58.40#ibcon#read 4, iclass 38, count 0 2006.285.12:48:58.40#ibcon#about to read 5, iclass 38, count 0 2006.285.12:48:58.40#ibcon#read 5, iclass 38, count 0 2006.285.12:48:58.40#ibcon#about to read 6, iclass 38, count 0 2006.285.12:48:58.40#ibcon#read 6, iclass 38, count 0 2006.285.12:48:58.40#ibcon#end of sib2, iclass 38, count 0 2006.285.12:48:58.40#ibcon#*mode == 0, iclass 38, count 0 2006.285.12:48:58.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.12:48:58.40#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.12:48:58.40#ibcon#*before write, iclass 38, count 0 2006.285.12:48:58.40#ibcon#enter sib2, iclass 38, count 0 2006.285.12:48:58.40#ibcon#flushed, iclass 38, count 0 2006.285.12:48:58.40#ibcon#about to write, iclass 38, count 0 2006.285.12:48:58.40#ibcon#wrote, iclass 38, count 0 2006.285.12:48:58.40#ibcon#about to read 3, iclass 38, count 0 2006.285.12:48:58.44#ibcon#read 3, iclass 38, count 0 2006.285.12:48:58.44#ibcon#about to read 4, iclass 38, count 0 2006.285.12:48:58.44#ibcon#read 4, iclass 38, count 0 2006.285.12:48:58.44#ibcon#about to read 5, iclass 38, count 0 2006.285.12:48:58.44#ibcon#read 5, iclass 38, count 0 2006.285.12:48:58.44#ibcon#about to read 6, iclass 38, count 0 2006.285.12:48:58.44#ibcon#read 6, iclass 38, count 0 2006.285.12:48:58.44#ibcon#end of sib2, iclass 38, count 0 2006.285.12:48:58.44#ibcon#*after write, iclass 38, count 0 2006.285.12:48:58.44#ibcon#*before return 0, iclass 38, count 0 2006.285.12:48:58.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:48:58.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:48:58.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.12:48:58.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.12:48:58.44$vck44/va=2,6 2006.285.12:48:58.44#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.12:48:58.44#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.12:48:58.44#ibcon#ireg 11 cls_cnt 2 2006.285.12:48:58.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:48:58.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:48:58.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:48:58.50#ibcon#enter wrdev, iclass 40, count 2 2006.285.12:48:58.50#ibcon#first serial, iclass 40, count 2 2006.285.12:48:58.50#ibcon#enter sib2, iclass 40, count 2 2006.285.12:48:58.50#ibcon#flushed, iclass 40, count 2 2006.285.12:48:58.50#ibcon#about to write, iclass 40, count 2 2006.285.12:48:58.50#ibcon#wrote, iclass 40, count 2 2006.285.12:48:58.50#ibcon#about to read 3, iclass 40, count 2 2006.285.12:48:58.52#ibcon#read 3, iclass 40, count 2 2006.285.12:48:58.52#ibcon#about to read 4, iclass 40, count 2 2006.285.12:48:58.52#ibcon#read 4, iclass 40, count 2 2006.285.12:48:58.52#ibcon#about to read 5, iclass 40, count 2 2006.285.12:48:58.52#ibcon#read 5, iclass 40, count 2 2006.285.12:48:58.52#ibcon#about to read 6, iclass 40, count 2 2006.285.12:48:58.52#ibcon#read 6, iclass 40, count 2 2006.285.12:48:58.52#ibcon#end of sib2, iclass 40, count 2 2006.285.12:48:58.52#ibcon#*mode == 0, iclass 40, count 2 2006.285.12:48:58.52#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.12:48:58.52#ibcon#[25=AT02-06\r\n] 2006.285.12:48:58.52#ibcon#*before write, iclass 40, count 2 2006.285.12:48:58.52#ibcon#enter sib2, iclass 40, count 2 2006.285.12:48:58.52#ibcon#flushed, iclass 40, count 2 2006.285.12:48:58.52#ibcon#about to write, iclass 40, count 2 2006.285.12:48:58.52#ibcon#wrote, iclass 40, count 2 2006.285.12:48:58.52#ibcon#about to read 3, iclass 40, count 2 2006.285.12:48:58.55#ibcon#read 3, iclass 40, count 2 2006.285.12:48:58.55#ibcon#about to read 4, iclass 40, count 2 2006.285.12:48:58.55#ibcon#read 4, iclass 40, count 2 2006.285.12:48:58.55#ibcon#about to read 5, iclass 40, count 2 2006.285.12:48:58.55#ibcon#read 5, iclass 40, count 2 2006.285.12:48:58.55#ibcon#about to read 6, iclass 40, count 2 2006.285.12:48:58.55#ibcon#read 6, iclass 40, count 2 2006.285.12:48:58.55#ibcon#end of sib2, iclass 40, count 2 2006.285.12:48:58.55#ibcon#*after write, iclass 40, count 2 2006.285.12:48:58.55#ibcon#*before return 0, iclass 40, count 2 2006.285.12:48:58.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:48:58.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:48:58.55#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.12:48:58.55#ibcon#ireg 7 cls_cnt 0 2006.285.12:48:58.55#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:48:58.67#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:48:59.03#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:48:59.03#ibcon#enter wrdev, iclass 40, count 0 2006.285.12:48:59.03#ibcon#first serial, iclass 40, count 0 2006.285.12:48:59.03#ibcon#enter sib2, iclass 40, count 0 2006.285.12:48:59.03#ibcon#flushed, iclass 40, count 0 2006.285.12:48:59.03#ibcon#about to write, iclass 40, count 0 2006.285.12:48:59.03#ibcon#wrote, iclass 40, count 0 2006.285.12:48:59.03#ibcon#about to read 3, iclass 40, count 0 2006.285.12:48:59.05#ibcon#read 3, iclass 40, count 0 2006.285.12:48:59.05#ibcon#about to read 4, iclass 40, count 0 2006.285.12:48:59.05#ibcon#read 4, iclass 40, count 0 2006.285.12:48:59.05#ibcon#about to read 5, iclass 40, count 0 2006.285.12:48:59.05#ibcon#read 5, iclass 40, count 0 2006.285.12:48:59.05#ibcon#about to read 6, iclass 40, count 0 2006.285.12:48:59.05#ibcon#read 6, iclass 40, count 0 2006.285.12:48:59.05#ibcon#end of sib2, iclass 40, count 0 2006.285.12:48:59.05#ibcon#*mode == 0, iclass 40, count 0 2006.285.12:48:59.05#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.12:48:59.05#ibcon#[25=USB\r\n] 2006.285.12:48:59.05#ibcon#*before write, iclass 40, count 0 2006.285.12:48:59.05#ibcon#enter sib2, iclass 40, count 0 2006.285.12:48:59.05#ibcon#flushed, iclass 40, count 0 2006.285.12:48:59.05#ibcon#about to write, iclass 40, count 0 2006.285.12:48:59.05#ibcon#wrote, iclass 40, count 0 2006.285.12:48:59.05#ibcon#about to read 3, iclass 40, count 0 2006.285.12:48:59.08#ibcon#read 3, iclass 40, count 0 2006.285.12:48:59.08#ibcon#about to read 4, iclass 40, count 0 2006.285.12:48:59.08#ibcon#read 4, iclass 40, count 0 2006.285.12:48:59.08#ibcon#about to read 5, iclass 40, count 0 2006.285.12:48:59.08#ibcon#read 5, iclass 40, count 0 2006.285.12:48:59.08#ibcon#about to read 6, iclass 40, count 0 2006.285.12:48:59.08#ibcon#read 6, iclass 40, count 0 2006.285.12:48:59.08#ibcon#end of sib2, iclass 40, count 0 2006.285.12:48:59.08#ibcon#*after write, iclass 40, count 0 2006.285.12:48:59.08#ibcon#*before return 0, iclass 40, count 0 2006.285.12:48:59.08#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:48:59.08#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:48:59.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.12:48:59.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.12:48:59.08$vck44/valo=3,564.99 2006.285.12:48:59.08#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.12:48:59.08#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.12:48:59.08#ibcon#ireg 17 cls_cnt 0 2006.285.12:48:59.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:48:59.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:48:59.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:48:59.08#ibcon#enter wrdev, iclass 4, count 0 2006.285.12:48:59.08#ibcon#first serial, iclass 4, count 0 2006.285.12:48:59.08#ibcon#enter sib2, iclass 4, count 0 2006.285.12:48:59.08#ibcon#flushed, iclass 4, count 0 2006.285.12:48:59.08#ibcon#about to write, iclass 4, count 0 2006.285.12:48:59.08#ibcon#wrote, iclass 4, count 0 2006.285.12:48:59.08#ibcon#about to read 3, iclass 4, count 0 2006.285.12:48:59.10#ibcon#read 3, iclass 4, count 0 2006.285.12:48:59.10#ibcon#about to read 4, iclass 4, count 0 2006.285.12:48:59.10#ibcon#read 4, iclass 4, count 0 2006.285.12:48:59.10#ibcon#about to read 5, iclass 4, count 0 2006.285.12:48:59.10#ibcon#read 5, iclass 4, count 0 2006.285.12:48:59.10#ibcon#about to read 6, iclass 4, count 0 2006.285.12:48:59.10#ibcon#read 6, iclass 4, count 0 2006.285.12:48:59.10#ibcon#end of sib2, iclass 4, count 0 2006.285.12:48:59.10#ibcon#*mode == 0, iclass 4, count 0 2006.285.12:48:59.10#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.12:48:59.10#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.12:48:59.10#ibcon#*before write, iclass 4, count 0 2006.285.12:48:59.10#ibcon#enter sib2, iclass 4, count 0 2006.285.12:48:59.10#ibcon#flushed, iclass 4, count 0 2006.285.12:48:59.10#ibcon#about to write, iclass 4, count 0 2006.285.12:48:59.10#ibcon#wrote, iclass 4, count 0 2006.285.12:48:59.10#ibcon#about to read 3, iclass 4, count 0 2006.285.12:48:59.14#ibcon#read 3, iclass 4, count 0 2006.285.12:48:59.14#ibcon#about to read 4, iclass 4, count 0 2006.285.12:48:59.14#ibcon#read 4, iclass 4, count 0 2006.285.12:48:59.14#ibcon#about to read 5, iclass 4, count 0 2006.285.12:48:59.14#ibcon#read 5, iclass 4, count 0 2006.285.12:48:59.14#ibcon#about to read 6, iclass 4, count 0 2006.285.12:48:59.14#ibcon#read 6, iclass 4, count 0 2006.285.12:48:59.14#ibcon#end of sib2, iclass 4, count 0 2006.285.12:48:59.14#ibcon#*after write, iclass 4, count 0 2006.285.12:48:59.14#ibcon#*before return 0, iclass 4, count 0 2006.285.12:48:59.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:48:59.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:48:59.14#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.12:48:59.14#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.12:48:59.14$vck44/va=3,7 2006.285.12:48:59.14#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.12:48:59.14#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.12:48:59.14#ibcon#ireg 11 cls_cnt 2 2006.285.12:48:59.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:48:59.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:48:59.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:48:59.20#ibcon#enter wrdev, iclass 6, count 2 2006.285.12:48:59.20#ibcon#first serial, iclass 6, count 2 2006.285.12:48:59.20#ibcon#enter sib2, iclass 6, count 2 2006.285.12:48:59.20#ibcon#flushed, iclass 6, count 2 2006.285.12:48:59.20#ibcon#about to write, iclass 6, count 2 2006.285.12:48:59.20#ibcon#wrote, iclass 6, count 2 2006.285.12:48:59.20#ibcon#about to read 3, iclass 6, count 2 2006.285.12:48:59.22#ibcon#read 3, iclass 6, count 2 2006.285.12:48:59.22#ibcon#about to read 4, iclass 6, count 2 2006.285.12:48:59.22#ibcon#read 4, iclass 6, count 2 2006.285.12:48:59.22#ibcon#about to read 5, iclass 6, count 2 2006.285.12:48:59.22#ibcon#read 5, iclass 6, count 2 2006.285.12:48:59.22#ibcon#about to read 6, iclass 6, count 2 2006.285.12:48:59.22#ibcon#read 6, iclass 6, count 2 2006.285.12:48:59.22#ibcon#end of sib2, iclass 6, count 2 2006.285.12:48:59.22#ibcon#*mode == 0, iclass 6, count 2 2006.285.12:48:59.22#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.12:48:59.22#ibcon#[25=AT03-07\r\n] 2006.285.12:48:59.22#ibcon#*before write, iclass 6, count 2 2006.285.12:48:59.22#ibcon#enter sib2, iclass 6, count 2 2006.285.12:48:59.22#ibcon#flushed, iclass 6, count 2 2006.285.12:48:59.22#ibcon#about to write, iclass 6, count 2 2006.285.12:48:59.22#ibcon#wrote, iclass 6, count 2 2006.285.12:48:59.22#ibcon#about to read 3, iclass 6, count 2 2006.285.12:48:59.25#ibcon#read 3, iclass 6, count 2 2006.285.12:48:59.25#ibcon#about to read 4, iclass 6, count 2 2006.285.12:48:59.25#ibcon#read 4, iclass 6, count 2 2006.285.12:48:59.25#ibcon#about to read 5, iclass 6, count 2 2006.285.12:48:59.25#ibcon#read 5, iclass 6, count 2 2006.285.12:48:59.25#ibcon#about to read 6, iclass 6, count 2 2006.285.12:48:59.25#ibcon#read 6, iclass 6, count 2 2006.285.12:48:59.25#ibcon#end of sib2, iclass 6, count 2 2006.285.12:48:59.25#ibcon#*after write, iclass 6, count 2 2006.285.12:48:59.25#ibcon#*before return 0, iclass 6, count 2 2006.285.12:48:59.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:48:59.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:48:59.25#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.12:48:59.25#ibcon#ireg 7 cls_cnt 0 2006.285.12:48:59.25#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:48:59.37#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:48:59.37#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:48:59.37#ibcon#enter wrdev, iclass 6, count 0 2006.285.12:48:59.37#ibcon#first serial, iclass 6, count 0 2006.285.12:48:59.37#ibcon#enter sib2, iclass 6, count 0 2006.285.12:48:59.37#ibcon#flushed, iclass 6, count 0 2006.285.12:48:59.37#ibcon#about to write, iclass 6, count 0 2006.285.12:48:59.37#ibcon#wrote, iclass 6, count 0 2006.285.12:48:59.37#ibcon#about to read 3, iclass 6, count 0 2006.285.12:48:59.39#ibcon#read 3, iclass 6, count 0 2006.285.12:48:59.39#ibcon#about to read 4, iclass 6, count 0 2006.285.12:48:59.39#ibcon#read 4, iclass 6, count 0 2006.285.12:48:59.39#ibcon#about to read 5, iclass 6, count 0 2006.285.12:48:59.39#ibcon#read 5, iclass 6, count 0 2006.285.12:48:59.39#ibcon#about to read 6, iclass 6, count 0 2006.285.12:48:59.39#ibcon#read 6, iclass 6, count 0 2006.285.12:48:59.39#ibcon#end of sib2, iclass 6, count 0 2006.285.12:48:59.39#ibcon#*mode == 0, iclass 6, count 0 2006.285.12:48:59.39#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.12:48:59.39#ibcon#[25=USB\r\n] 2006.285.12:48:59.39#ibcon#*before write, iclass 6, count 0 2006.285.12:48:59.39#ibcon#enter sib2, iclass 6, count 0 2006.285.12:48:59.39#ibcon#flushed, iclass 6, count 0 2006.285.12:48:59.39#ibcon#about to write, iclass 6, count 0 2006.285.12:48:59.39#ibcon#wrote, iclass 6, count 0 2006.285.12:48:59.39#ibcon#about to read 3, iclass 6, count 0 2006.285.12:48:59.42#ibcon#read 3, iclass 6, count 0 2006.285.12:48:59.42#ibcon#about to read 4, iclass 6, count 0 2006.285.12:48:59.42#ibcon#read 4, iclass 6, count 0 2006.285.12:48:59.42#ibcon#about to read 5, iclass 6, count 0 2006.285.12:48:59.42#ibcon#read 5, iclass 6, count 0 2006.285.12:48:59.42#ibcon#about to read 6, iclass 6, count 0 2006.285.12:48:59.42#ibcon#read 6, iclass 6, count 0 2006.285.12:48:59.42#ibcon#end of sib2, iclass 6, count 0 2006.285.12:48:59.42#ibcon#*after write, iclass 6, count 0 2006.285.12:48:59.42#ibcon#*before return 0, iclass 6, count 0 2006.285.12:48:59.42#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:48:59.42#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:48:59.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.12:48:59.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.12:48:59.42$vck44/valo=4,624.99 2006.285.12:48:59.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.12:48:59.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.12:48:59.59#ibcon#ireg 17 cls_cnt 0 2006.285.12:48:59.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:48:59.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:48:59.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:48:59.59#ibcon#enter wrdev, iclass 10, count 0 2006.285.12:48:59.59#ibcon#first serial, iclass 10, count 0 2006.285.12:48:59.59#ibcon#enter sib2, iclass 10, count 0 2006.285.12:48:59.59#ibcon#flushed, iclass 10, count 0 2006.285.12:48:59.59#ibcon#about to write, iclass 10, count 0 2006.285.12:48:59.59#ibcon#wrote, iclass 10, count 0 2006.285.12:48:59.59#ibcon#about to read 3, iclass 10, count 0 2006.285.12:48:59.61#ibcon#read 3, iclass 10, count 0 2006.285.12:48:59.61#ibcon#about to read 4, iclass 10, count 0 2006.285.12:48:59.61#ibcon#read 4, iclass 10, count 0 2006.285.12:48:59.61#ibcon#about to read 5, iclass 10, count 0 2006.285.12:48:59.61#ibcon#read 5, iclass 10, count 0 2006.285.12:48:59.61#ibcon#about to read 6, iclass 10, count 0 2006.285.12:48:59.61#ibcon#read 6, iclass 10, count 0 2006.285.12:48:59.61#ibcon#end of sib2, iclass 10, count 0 2006.285.12:48:59.61#ibcon#*mode == 0, iclass 10, count 0 2006.285.12:48:59.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.12:48:59.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.12:48:59.61#ibcon#*before write, iclass 10, count 0 2006.285.12:48:59.61#ibcon#enter sib2, iclass 10, count 0 2006.285.12:48:59.61#ibcon#flushed, iclass 10, count 0 2006.285.12:48:59.61#ibcon#about to write, iclass 10, count 0 2006.285.12:48:59.61#ibcon#wrote, iclass 10, count 0 2006.285.12:48:59.61#ibcon#about to read 3, iclass 10, count 0 2006.285.12:48:59.65#ibcon#read 3, iclass 10, count 0 2006.285.12:48:59.65#ibcon#about to read 4, iclass 10, count 0 2006.285.12:48:59.65#ibcon#read 4, iclass 10, count 0 2006.285.12:48:59.65#ibcon#about to read 5, iclass 10, count 0 2006.285.12:48:59.65#ibcon#read 5, iclass 10, count 0 2006.285.12:48:59.65#ibcon#about to read 6, iclass 10, count 0 2006.285.12:48:59.65#ibcon#read 6, iclass 10, count 0 2006.285.12:48:59.65#ibcon#end of sib2, iclass 10, count 0 2006.285.12:48:59.65#ibcon#*after write, iclass 10, count 0 2006.285.12:48:59.65#ibcon#*before return 0, iclass 10, count 0 2006.285.12:48:59.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:48:59.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:48:59.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.12:48:59.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.12:48:59.65$vck44/va=4,6 2006.285.12:48:59.65#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.12:48:59.65#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.12:48:59.65#ibcon#ireg 11 cls_cnt 2 2006.285.12:48:59.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:48:59.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:48:59.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:48:59.65#ibcon#enter wrdev, iclass 12, count 2 2006.285.12:48:59.65#ibcon#first serial, iclass 12, count 2 2006.285.12:48:59.65#ibcon#enter sib2, iclass 12, count 2 2006.285.12:48:59.65#ibcon#flushed, iclass 12, count 2 2006.285.12:48:59.65#ibcon#about to write, iclass 12, count 2 2006.285.12:48:59.65#ibcon#wrote, iclass 12, count 2 2006.285.12:48:59.65#ibcon#about to read 3, iclass 12, count 2 2006.285.12:48:59.67#ibcon#read 3, iclass 12, count 2 2006.285.12:48:59.67#ibcon#about to read 4, iclass 12, count 2 2006.285.12:48:59.67#ibcon#read 4, iclass 12, count 2 2006.285.12:48:59.67#ibcon#about to read 5, iclass 12, count 2 2006.285.12:48:59.67#ibcon#read 5, iclass 12, count 2 2006.285.12:48:59.67#ibcon#about to read 6, iclass 12, count 2 2006.285.12:48:59.67#ibcon#read 6, iclass 12, count 2 2006.285.12:48:59.67#ibcon#end of sib2, iclass 12, count 2 2006.285.12:48:59.67#ibcon#*mode == 0, iclass 12, count 2 2006.285.12:48:59.67#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.12:48:59.67#ibcon#[25=AT04-06\r\n] 2006.285.12:48:59.67#ibcon#*before write, iclass 12, count 2 2006.285.12:48:59.67#ibcon#enter sib2, iclass 12, count 2 2006.285.12:48:59.67#ibcon#flushed, iclass 12, count 2 2006.285.12:48:59.67#ibcon#about to write, iclass 12, count 2 2006.285.12:48:59.67#ibcon#wrote, iclass 12, count 2 2006.285.12:48:59.67#ibcon#about to read 3, iclass 12, count 2 2006.285.12:48:59.70#ibcon#read 3, iclass 12, count 2 2006.285.12:48:59.70#ibcon#about to read 4, iclass 12, count 2 2006.285.12:48:59.70#ibcon#read 4, iclass 12, count 2 2006.285.12:48:59.70#ibcon#about to read 5, iclass 12, count 2 2006.285.12:48:59.70#ibcon#read 5, iclass 12, count 2 2006.285.12:48:59.70#ibcon#about to read 6, iclass 12, count 2 2006.285.12:48:59.70#ibcon#read 6, iclass 12, count 2 2006.285.12:48:59.70#ibcon#end of sib2, iclass 12, count 2 2006.285.12:48:59.70#ibcon#*after write, iclass 12, count 2 2006.285.12:48:59.70#ibcon#*before return 0, iclass 12, count 2 2006.285.12:48:59.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:48:59.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:48:59.70#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.12:48:59.70#ibcon#ireg 7 cls_cnt 0 2006.285.12:48:59.70#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:48:59.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:48:59.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:48:59.82#ibcon#enter wrdev, iclass 12, count 0 2006.285.12:48:59.82#ibcon#first serial, iclass 12, count 0 2006.285.12:48:59.82#ibcon#enter sib2, iclass 12, count 0 2006.285.12:48:59.82#ibcon#flushed, iclass 12, count 0 2006.285.12:48:59.82#ibcon#about to write, iclass 12, count 0 2006.285.12:48:59.82#ibcon#wrote, iclass 12, count 0 2006.285.12:48:59.82#ibcon#about to read 3, iclass 12, count 0 2006.285.12:48:59.84#ibcon#read 3, iclass 12, count 0 2006.285.12:48:59.84#ibcon#about to read 4, iclass 12, count 0 2006.285.12:48:59.84#ibcon#read 4, iclass 12, count 0 2006.285.12:48:59.84#ibcon#about to read 5, iclass 12, count 0 2006.285.12:48:59.84#ibcon#read 5, iclass 12, count 0 2006.285.12:48:59.84#ibcon#about to read 6, iclass 12, count 0 2006.285.12:48:59.84#ibcon#read 6, iclass 12, count 0 2006.285.12:48:59.84#ibcon#end of sib2, iclass 12, count 0 2006.285.12:48:59.84#ibcon#*mode == 0, iclass 12, count 0 2006.285.12:48:59.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.12:48:59.84#ibcon#[25=USB\r\n] 2006.285.12:48:59.84#ibcon#*before write, iclass 12, count 0 2006.285.12:48:59.84#ibcon#enter sib2, iclass 12, count 0 2006.285.12:48:59.84#ibcon#flushed, iclass 12, count 0 2006.285.12:48:59.84#ibcon#about to write, iclass 12, count 0 2006.285.12:48:59.84#ibcon#wrote, iclass 12, count 0 2006.285.12:48:59.84#ibcon#about to read 3, iclass 12, count 0 2006.285.12:48:59.87#ibcon#read 3, iclass 12, count 0 2006.285.12:48:59.87#ibcon#about to read 4, iclass 12, count 0 2006.285.12:48:59.87#ibcon#read 4, iclass 12, count 0 2006.285.12:48:59.87#ibcon#about to read 5, iclass 12, count 0 2006.285.12:48:59.87#ibcon#read 5, iclass 12, count 0 2006.285.12:48:59.87#ibcon#about to read 6, iclass 12, count 0 2006.285.12:48:59.87#ibcon#read 6, iclass 12, count 0 2006.285.12:48:59.87#ibcon#end of sib2, iclass 12, count 0 2006.285.12:48:59.87#ibcon#*after write, iclass 12, count 0 2006.285.12:48:59.87#ibcon#*before return 0, iclass 12, count 0 2006.285.12:48:59.87#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:48:59.87#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:48:59.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.12:48:59.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.12:48:59.87$vck44/valo=5,734.99 2006.285.12:48:59.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.12:48:59.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.12:48:59.87#ibcon#ireg 17 cls_cnt 0 2006.285.12:48:59.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:48:59.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:48:59.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:48:59.87#ibcon#enter wrdev, iclass 14, count 0 2006.285.12:48:59.87#ibcon#first serial, iclass 14, count 0 2006.285.12:48:59.87#ibcon#enter sib2, iclass 14, count 0 2006.285.12:48:59.87#ibcon#flushed, iclass 14, count 0 2006.285.12:48:59.87#ibcon#about to write, iclass 14, count 0 2006.285.12:48:59.87#ibcon#wrote, iclass 14, count 0 2006.285.12:48:59.87#ibcon#about to read 3, iclass 14, count 0 2006.285.12:48:59.89#ibcon#read 3, iclass 14, count 0 2006.285.12:48:59.89#ibcon#about to read 4, iclass 14, count 0 2006.285.12:48:59.89#ibcon#read 4, iclass 14, count 0 2006.285.12:48:59.89#ibcon#about to read 5, iclass 14, count 0 2006.285.12:48:59.89#ibcon#read 5, iclass 14, count 0 2006.285.12:48:59.89#ibcon#about to read 6, iclass 14, count 0 2006.285.12:48:59.89#ibcon#read 6, iclass 14, count 0 2006.285.12:48:59.89#ibcon#end of sib2, iclass 14, count 0 2006.285.12:48:59.89#ibcon#*mode == 0, iclass 14, count 0 2006.285.12:48:59.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.12:48:59.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.12:48:59.89#ibcon#*before write, iclass 14, count 0 2006.285.12:48:59.89#ibcon#enter sib2, iclass 14, count 0 2006.285.12:48:59.89#ibcon#flushed, iclass 14, count 0 2006.285.12:48:59.89#ibcon#about to write, iclass 14, count 0 2006.285.12:48:59.89#ibcon#wrote, iclass 14, count 0 2006.285.12:48:59.89#ibcon#about to read 3, iclass 14, count 0 2006.285.12:48:59.93#ibcon#read 3, iclass 14, count 0 2006.285.12:48:59.93#ibcon#about to read 4, iclass 14, count 0 2006.285.12:48:59.93#ibcon#read 4, iclass 14, count 0 2006.285.12:48:59.93#ibcon#about to read 5, iclass 14, count 0 2006.285.12:48:59.93#ibcon#read 5, iclass 14, count 0 2006.285.12:48:59.93#ibcon#about to read 6, iclass 14, count 0 2006.285.12:48:59.93#ibcon#read 6, iclass 14, count 0 2006.285.12:48:59.93#ibcon#end of sib2, iclass 14, count 0 2006.285.12:48:59.93#ibcon#*after write, iclass 14, count 0 2006.285.12:48:59.93#ibcon#*before return 0, iclass 14, count 0 2006.285.12:48:59.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:48:59.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:48:59.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.12:48:59.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.12:48:59.93$vck44/va=5,3 2006.285.12:48:59.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.12:48:59.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.12:48:59.93#ibcon#ireg 11 cls_cnt 2 2006.285.12:48:59.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:48:59.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:48:59.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:48:59.99#ibcon#enter wrdev, iclass 16, count 2 2006.285.12:48:59.99#ibcon#first serial, iclass 16, count 2 2006.285.12:48:59.99#ibcon#enter sib2, iclass 16, count 2 2006.285.12:48:59.99#ibcon#flushed, iclass 16, count 2 2006.285.12:48:59.99#ibcon#about to write, iclass 16, count 2 2006.285.12:48:59.99#ibcon#wrote, iclass 16, count 2 2006.285.12:48:59.99#ibcon#about to read 3, iclass 16, count 2 2006.285.12:49:00.01#ibcon#read 3, iclass 16, count 2 2006.285.12:49:00.01#ibcon#about to read 4, iclass 16, count 2 2006.285.12:49:00.01#ibcon#read 4, iclass 16, count 2 2006.285.12:49:00.01#ibcon#about to read 5, iclass 16, count 2 2006.285.12:49:00.01#ibcon#read 5, iclass 16, count 2 2006.285.12:49:00.01#ibcon#about to read 6, iclass 16, count 2 2006.285.12:49:00.01#ibcon#read 6, iclass 16, count 2 2006.285.12:49:00.01#ibcon#end of sib2, iclass 16, count 2 2006.285.12:49:00.01#ibcon#*mode == 0, iclass 16, count 2 2006.285.12:49:00.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.12:49:00.01#ibcon#[25=AT05-03\r\n] 2006.285.12:49:00.01#ibcon#*before write, iclass 16, count 2 2006.285.12:49:00.01#ibcon#enter sib2, iclass 16, count 2 2006.285.12:49:00.01#ibcon#flushed, iclass 16, count 2 2006.285.12:49:00.01#ibcon#about to write, iclass 16, count 2 2006.285.12:49:00.01#ibcon#wrote, iclass 16, count 2 2006.285.12:49:00.01#ibcon#about to read 3, iclass 16, count 2 2006.285.12:49:00.04#ibcon#read 3, iclass 16, count 2 2006.285.12:49:00.04#ibcon#about to read 4, iclass 16, count 2 2006.285.12:49:00.04#ibcon#read 4, iclass 16, count 2 2006.285.12:49:00.04#ibcon#about to read 5, iclass 16, count 2 2006.285.12:49:00.04#ibcon#read 5, iclass 16, count 2 2006.285.12:49:00.04#ibcon#about to read 6, iclass 16, count 2 2006.285.12:49:00.04#ibcon#read 6, iclass 16, count 2 2006.285.12:49:00.04#ibcon#end of sib2, iclass 16, count 2 2006.285.12:49:00.04#ibcon#*after write, iclass 16, count 2 2006.285.12:49:00.04#ibcon#*before return 0, iclass 16, count 2 2006.285.12:49:00.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:49:00.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:49:00.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.12:49:00.04#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:00.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:49:00.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:49:00.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:49:00.16#ibcon#enter wrdev, iclass 16, count 0 2006.285.12:49:00.16#ibcon#first serial, iclass 16, count 0 2006.285.12:49:00.16#ibcon#enter sib2, iclass 16, count 0 2006.285.12:49:00.16#ibcon#flushed, iclass 16, count 0 2006.285.12:49:00.16#ibcon#about to write, iclass 16, count 0 2006.285.12:49:00.16#ibcon#wrote, iclass 16, count 0 2006.285.12:49:00.16#ibcon#about to read 3, iclass 16, count 0 2006.285.12:49:00.18#ibcon#read 3, iclass 16, count 0 2006.285.12:49:00.18#ibcon#about to read 4, iclass 16, count 0 2006.285.12:49:00.18#ibcon#read 4, iclass 16, count 0 2006.285.12:49:00.18#ibcon#about to read 5, iclass 16, count 0 2006.285.12:49:00.18#ibcon#read 5, iclass 16, count 0 2006.285.12:49:00.18#ibcon#about to read 6, iclass 16, count 0 2006.285.12:49:00.18#ibcon#read 6, iclass 16, count 0 2006.285.12:49:00.18#ibcon#end of sib2, iclass 16, count 0 2006.285.12:49:00.18#ibcon#*mode == 0, iclass 16, count 0 2006.285.12:49:00.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.12:49:00.18#ibcon#[25=USB\r\n] 2006.285.12:49:00.18#ibcon#*before write, iclass 16, count 0 2006.285.12:49:00.18#ibcon#enter sib2, iclass 16, count 0 2006.285.12:49:00.18#ibcon#flushed, iclass 16, count 0 2006.285.12:49:00.18#ibcon#about to write, iclass 16, count 0 2006.285.12:49:00.18#ibcon#wrote, iclass 16, count 0 2006.285.12:49:00.18#ibcon#about to read 3, iclass 16, count 0 2006.285.12:49:00.21#ibcon#read 3, iclass 16, count 0 2006.285.12:49:00.21#ibcon#about to read 4, iclass 16, count 0 2006.285.12:49:00.21#ibcon#read 4, iclass 16, count 0 2006.285.12:49:00.21#ibcon#about to read 5, iclass 16, count 0 2006.285.12:49:00.21#ibcon#read 5, iclass 16, count 0 2006.285.12:49:00.21#ibcon#about to read 6, iclass 16, count 0 2006.285.12:49:00.21#ibcon#read 6, iclass 16, count 0 2006.285.12:49:00.21#ibcon#end of sib2, iclass 16, count 0 2006.285.12:49:00.21#ibcon#*after write, iclass 16, count 0 2006.285.12:49:00.21#ibcon#*before return 0, iclass 16, count 0 2006.285.12:49:00.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:49:00.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:49:00.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.12:49:00.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.12:49:00.21$vck44/valo=6,814.99 2006.285.12:49:00.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.12:49:00.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.12:49:00.21#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:00.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:49:00.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:49:00.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:49:00.21#ibcon#enter wrdev, iclass 18, count 0 2006.285.12:49:00.21#ibcon#first serial, iclass 18, count 0 2006.285.12:49:00.21#ibcon#enter sib2, iclass 18, count 0 2006.285.12:49:00.21#ibcon#flushed, iclass 18, count 0 2006.285.12:49:00.21#ibcon#about to write, iclass 18, count 0 2006.285.12:49:00.21#ibcon#wrote, iclass 18, count 0 2006.285.12:49:00.21#ibcon#about to read 3, iclass 18, count 0 2006.285.12:49:00.23#ibcon#read 3, iclass 18, count 0 2006.285.12:49:00.23#ibcon#about to read 4, iclass 18, count 0 2006.285.12:49:00.23#ibcon#read 4, iclass 18, count 0 2006.285.12:49:00.23#ibcon#about to read 5, iclass 18, count 0 2006.285.12:49:00.23#ibcon#read 5, iclass 18, count 0 2006.285.12:49:00.23#ibcon#about to read 6, iclass 18, count 0 2006.285.12:49:00.23#ibcon#read 6, iclass 18, count 0 2006.285.12:49:00.23#ibcon#end of sib2, iclass 18, count 0 2006.285.12:49:00.23#ibcon#*mode == 0, iclass 18, count 0 2006.285.12:49:00.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.12:49:00.23#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.12:49:00.23#ibcon#*before write, iclass 18, count 0 2006.285.12:49:00.23#ibcon#enter sib2, iclass 18, count 0 2006.285.12:49:00.23#ibcon#flushed, iclass 18, count 0 2006.285.12:49:00.23#ibcon#about to write, iclass 18, count 0 2006.285.12:49:00.23#ibcon#wrote, iclass 18, count 0 2006.285.12:49:00.23#ibcon#about to read 3, iclass 18, count 0 2006.285.12:49:00.27#ibcon#read 3, iclass 18, count 0 2006.285.12:49:00.27#ibcon#about to read 4, iclass 18, count 0 2006.285.12:49:00.27#ibcon#read 4, iclass 18, count 0 2006.285.12:49:00.27#ibcon#about to read 5, iclass 18, count 0 2006.285.12:49:00.27#ibcon#read 5, iclass 18, count 0 2006.285.12:49:00.27#ibcon#about to read 6, iclass 18, count 0 2006.285.12:49:00.27#ibcon#read 6, iclass 18, count 0 2006.285.12:49:00.27#ibcon#end of sib2, iclass 18, count 0 2006.285.12:49:00.27#ibcon#*after write, iclass 18, count 0 2006.285.12:49:00.27#ibcon#*before return 0, iclass 18, count 0 2006.285.12:49:00.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:49:00.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:49:00.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.12:49:00.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.12:49:00.27$vck44/va=6,4 2006.285.12:49:00.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.12:49:00.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.12:49:00.27#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:00.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:49:00.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:49:00.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:49:00.33#ibcon#enter wrdev, iclass 20, count 2 2006.285.12:49:00.33#ibcon#first serial, iclass 20, count 2 2006.285.12:49:00.33#ibcon#enter sib2, iclass 20, count 2 2006.285.12:49:00.33#ibcon#flushed, iclass 20, count 2 2006.285.12:49:00.33#ibcon#about to write, iclass 20, count 2 2006.285.12:49:00.33#ibcon#wrote, iclass 20, count 2 2006.285.12:49:00.33#ibcon#about to read 3, iclass 20, count 2 2006.285.12:49:00.35#ibcon#read 3, iclass 20, count 2 2006.285.12:49:00.35#ibcon#about to read 4, iclass 20, count 2 2006.285.12:49:00.35#ibcon#read 4, iclass 20, count 2 2006.285.12:49:00.35#ibcon#about to read 5, iclass 20, count 2 2006.285.12:49:00.35#ibcon#read 5, iclass 20, count 2 2006.285.12:49:00.35#ibcon#about to read 6, iclass 20, count 2 2006.285.12:49:00.35#ibcon#read 6, iclass 20, count 2 2006.285.12:49:00.35#ibcon#end of sib2, iclass 20, count 2 2006.285.12:49:00.35#ibcon#*mode == 0, iclass 20, count 2 2006.285.12:49:00.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.12:49:00.35#ibcon#[25=AT06-04\r\n] 2006.285.12:49:00.35#ibcon#*before write, iclass 20, count 2 2006.285.12:49:00.35#ibcon#enter sib2, iclass 20, count 2 2006.285.12:49:00.35#ibcon#flushed, iclass 20, count 2 2006.285.12:49:00.35#ibcon#about to write, iclass 20, count 2 2006.285.12:49:00.35#ibcon#wrote, iclass 20, count 2 2006.285.12:49:00.35#ibcon#about to read 3, iclass 20, count 2 2006.285.12:49:00.38#ibcon#read 3, iclass 20, count 2 2006.285.12:49:00.38#ibcon#about to read 4, iclass 20, count 2 2006.285.12:49:00.38#ibcon#read 4, iclass 20, count 2 2006.285.12:49:00.38#ibcon#about to read 5, iclass 20, count 2 2006.285.12:49:00.38#ibcon#read 5, iclass 20, count 2 2006.285.12:49:00.38#ibcon#about to read 6, iclass 20, count 2 2006.285.12:49:00.38#ibcon#read 6, iclass 20, count 2 2006.285.12:49:00.38#ibcon#end of sib2, iclass 20, count 2 2006.285.12:49:00.38#ibcon#*after write, iclass 20, count 2 2006.285.12:49:00.38#ibcon#*before return 0, iclass 20, count 2 2006.285.12:49:00.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:49:00.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:49:00.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.12:49:00.38#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:00.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:49:00.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:49:00.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:49:00.50#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:49:00.50#ibcon#first serial, iclass 20, count 0 2006.285.12:49:00.50#ibcon#enter sib2, iclass 20, count 0 2006.285.12:49:00.50#ibcon#flushed, iclass 20, count 0 2006.285.12:49:00.50#ibcon#about to write, iclass 20, count 0 2006.285.12:49:00.50#ibcon#wrote, iclass 20, count 0 2006.285.12:49:00.50#ibcon#about to read 3, iclass 20, count 0 2006.285.12:49:00.52#ibcon#read 3, iclass 20, count 0 2006.285.12:49:00.52#ibcon#about to read 4, iclass 20, count 0 2006.285.12:49:00.52#ibcon#read 4, iclass 20, count 0 2006.285.12:49:00.52#ibcon#about to read 5, iclass 20, count 0 2006.285.12:49:00.52#ibcon#read 5, iclass 20, count 0 2006.285.12:49:00.52#ibcon#about to read 6, iclass 20, count 0 2006.285.12:49:00.52#ibcon#read 6, iclass 20, count 0 2006.285.12:49:00.52#ibcon#end of sib2, iclass 20, count 0 2006.285.12:49:00.52#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:49:00.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:49:00.52#ibcon#[25=USB\r\n] 2006.285.12:49:00.52#ibcon#*before write, iclass 20, count 0 2006.285.12:49:00.52#ibcon#enter sib2, iclass 20, count 0 2006.285.12:49:00.52#ibcon#flushed, iclass 20, count 0 2006.285.12:49:00.52#ibcon#about to write, iclass 20, count 0 2006.285.12:49:00.52#ibcon#wrote, iclass 20, count 0 2006.285.12:49:00.52#ibcon#about to read 3, iclass 20, count 0 2006.285.12:49:00.55#ibcon#read 3, iclass 20, count 0 2006.285.12:49:00.55#ibcon#about to read 4, iclass 20, count 0 2006.285.12:49:00.55#ibcon#read 4, iclass 20, count 0 2006.285.12:49:00.55#ibcon#about to read 5, iclass 20, count 0 2006.285.12:49:00.55#ibcon#read 5, iclass 20, count 0 2006.285.12:49:00.55#ibcon#about to read 6, iclass 20, count 0 2006.285.12:49:00.55#ibcon#read 6, iclass 20, count 0 2006.285.12:49:00.55#ibcon#end of sib2, iclass 20, count 0 2006.285.12:49:00.55#ibcon#*after write, iclass 20, count 0 2006.285.12:49:00.55#ibcon#*before return 0, iclass 20, count 0 2006.285.12:49:00.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:49:00.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:49:00.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:49:00.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:49:00.55$vck44/valo=7,864.99 2006.285.12:49:00.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.12:49:00.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.12:49:00.55#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:00.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:49:00.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:49:00.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:49:00.55#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:49:00.55#ibcon#first serial, iclass 22, count 0 2006.285.12:49:00.55#ibcon#enter sib2, iclass 22, count 0 2006.285.12:49:00.55#ibcon#flushed, iclass 22, count 0 2006.285.12:49:00.55#ibcon#about to write, iclass 22, count 0 2006.285.12:49:00.55#ibcon#wrote, iclass 22, count 0 2006.285.12:49:00.55#ibcon#about to read 3, iclass 22, count 0 2006.285.12:49:00.57#ibcon#read 3, iclass 22, count 0 2006.285.12:49:00.71#ibcon#about to read 4, iclass 22, count 0 2006.285.12:49:00.71#ibcon#read 4, iclass 22, count 0 2006.285.12:49:00.71#ibcon#about to read 5, iclass 22, count 0 2006.285.12:49:00.71#ibcon#read 5, iclass 22, count 0 2006.285.12:49:00.71#ibcon#about to read 6, iclass 22, count 0 2006.285.12:49:00.71#ibcon#read 6, iclass 22, count 0 2006.285.12:49:00.71#ibcon#end of sib2, iclass 22, count 0 2006.285.12:49:00.71#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:49:00.71#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:49:00.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.12:49:00.71#ibcon#*before write, iclass 22, count 0 2006.285.12:49:00.71#ibcon#enter sib2, iclass 22, count 0 2006.285.12:49:00.71#ibcon#flushed, iclass 22, count 0 2006.285.12:49:00.71#ibcon#about to write, iclass 22, count 0 2006.285.12:49:00.71#ibcon#wrote, iclass 22, count 0 2006.285.12:49:00.71#ibcon#about to read 3, iclass 22, count 0 2006.285.12:49:00.76#ibcon#read 3, iclass 22, count 0 2006.285.12:49:00.76#ibcon#about to read 4, iclass 22, count 0 2006.285.12:49:00.76#ibcon#read 4, iclass 22, count 0 2006.285.12:49:00.76#ibcon#about to read 5, iclass 22, count 0 2006.285.12:49:00.76#ibcon#read 5, iclass 22, count 0 2006.285.12:49:00.76#ibcon#about to read 6, iclass 22, count 0 2006.285.12:49:00.76#ibcon#read 6, iclass 22, count 0 2006.285.12:49:00.76#ibcon#end of sib2, iclass 22, count 0 2006.285.12:49:00.76#ibcon#*after write, iclass 22, count 0 2006.285.12:49:00.76#ibcon#*before return 0, iclass 22, count 0 2006.285.12:49:00.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:49:00.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:49:00.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:49:00.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:49:00.76$vck44/va=7,4 2006.285.12:49:00.76#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.12:49:00.76#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.12:49:00.76#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:00.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:49:00.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:49:00.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:49:00.76#ibcon#enter wrdev, iclass 24, count 2 2006.285.12:49:00.76#ibcon#first serial, iclass 24, count 2 2006.285.12:49:00.76#ibcon#enter sib2, iclass 24, count 2 2006.285.12:49:00.76#ibcon#flushed, iclass 24, count 2 2006.285.12:49:00.76#ibcon#about to write, iclass 24, count 2 2006.285.12:49:00.76#ibcon#wrote, iclass 24, count 2 2006.285.12:49:00.76#ibcon#about to read 3, iclass 24, count 2 2006.285.12:49:00.78#ibcon#read 3, iclass 24, count 2 2006.285.12:49:00.78#ibcon#about to read 4, iclass 24, count 2 2006.285.12:49:00.78#ibcon#read 4, iclass 24, count 2 2006.285.12:49:00.78#ibcon#about to read 5, iclass 24, count 2 2006.285.12:49:00.78#ibcon#read 5, iclass 24, count 2 2006.285.12:49:00.78#ibcon#about to read 6, iclass 24, count 2 2006.285.12:49:00.78#ibcon#read 6, iclass 24, count 2 2006.285.12:49:00.78#ibcon#end of sib2, iclass 24, count 2 2006.285.12:49:00.78#ibcon#*mode == 0, iclass 24, count 2 2006.285.12:49:00.78#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.12:49:00.78#ibcon#[25=AT07-04\r\n] 2006.285.12:49:00.78#ibcon#*before write, iclass 24, count 2 2006.285.12:49:00.78#ibcon#enter sib2, iclass 24, count 2 2006.285.12:49:00.78#ibcon#flushed, iclass 24, count 2 2006.285.12:49:00.78#ibcon#about to write, iclass 24, count 2 2006.285.12:49:00.78#ibcon#wrote, iclass 24, count 2 2006.285.12:49:00.78#ibcon#about to read 3, iclass 24, count 2 2006.285.12:49:00.81#ibcon#read 3, iclass 24, count 2 2006.285.12:49:00.81#ibcon#about to read 4, iclass 24, count 2 2006.285.12:49:00.81#ibcon#read 4, iclass 24, count 2 2006.285.12:49:00.81#ibcon#about to read 5, iclass 24, count 2 2006.285.12:49:00.81#ibcon#read 5, iclass 24, count 2 2006.285.12:49:00.81#ibcon#about to read 6, iclass 24, count 2 2006.285.12:49:00.81#ibcon#read 6, iclass 24, count 2 2006.285.12:49:00.81#ibcon#end of sib2, iclass 24, count 2 2006.285.12:49:00.81#ibcon#*after write, iclass 24, count 2 2006.285.12:49:00.81#ibcon#*before return 0, iclass 24, count 2 2006.285.12:49:00.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:49:00.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:49:00.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.12:49:00.81#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:00.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:49:00.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:49:00.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:49:00.93#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:49:00.93#ibcon#first serial, iclass 24, count 0 2006.285.12:49:00.93#ibcon#enter sib2, iclass 24, count 0 2006.285.12:49:00.93#ibcon#flushed, iclass 24, count 0 2006.285.12:49:00.93#ibcon#about to write, iclass 24, count 0 2006.285.12:49:00.93#ibcon#wrote, iclass 24, count 0 2006.285.12:49:00.93#ibcon#about to read 3, iclass 24, count 0 2006.285.12:49:00.95#ibcon#read 3, iclass 24, count 0 2006.285.12:49:00.95#ibcon#about to read 4, iclass 24, count 0 2006.285.12:49:00.95#ibcon#read 4, iclass 24, count 0 2006.285.12:49:00.95#ibcon#about to read 5, iclass 24, count 0 2006.285.12:49:00.95#ibcon#read 5, iclass 24, count 0 2006.285.12:49:00.95#ibcon#about to read 6, iclass 24, count 0 2006.285.12:49:00.95#ibcon#read 6, iclass 24, count 0 2006.285.12:49:00.95#ibcon#end of sib2, iclass 24, count 0 2006.285.12:49:00.95#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:49:00.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:49:00.95#ibcon#[25=USB\r\n] 2006.285.12:49:00.95#ibcon#*before write, iclass 24, count 0 2006.285.12:49:00.95#ibcon#enter sib2, iclass 24, count 0 2006.285.12:49:00.95#ibcon#flushed, iclass 24, count 0 2006.285.12:49:00.95#ibcon#about to write, iclass 24, count 0 2006.285.12:49:00.95#ibcon#wrote, iclass 24, count 0 2006.285.12:49:00.95#ibcon#about to read 3, iclass 24, count 0 2006.285.12:49:00.98#ibcon#read 3, iclass 24, count 0 2006.285.12:49:00.98#ibcon#about to read 4, iclass 24, count 0 2006.285.12:49:00.98#ibcon#read 4, iclass 24, count 0 2006.285.12:49:00.98#ibcon#about to read 5, iclass 24, count 0 2006.285.12:49:00.98#ibcon#read 5, iclass 24, count 0 2006.285.12:49:00.98#ibcon#about to read 6, iclass 24, count 0 2006.285.12:49:00.98#ibcon#read 6, iclass 24, count 0 2006.285.12:49:00.98#ibcon#end of sib2, iclass 24, count 0 2006.285.12:49:00.98#ibcon#*after write, iclass 24, count 0 2006.285.12:49:00.98#ibcon#*before return 0, iclass 24, count 0 2006.285.12:49:00.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:49:00.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:49:00.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:49:00.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:49:00.98$vck44/valo=8,884.99 2006.285.12:49:00.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.12:49:00.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.12:49:00.98#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:00.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:49:00.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:49:00.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:49:00.98#ibcon#enter wrdev, iclass 26, count 0 2006.285.12:49:00.98#ibcon#first serial, iclass 26, count 0 2006.285.12:49:00.98#ibcon#enter sib2, iclass 26, count 0 2006.285.12:49:00.98#ibcon#flushed, iclass 26, count 0 2006.285.12:49:00.98#ibcon#about to write, iclass 26, count 0 2006.285.12:49:00.98#ibcon#wrote, iclass 26, count 0 2006.285.12:49:00.98#ibcon#about to read 3, iclass 26, count 0 2006.285.12:49:01.00#ibcon#read 3, iclass 26, count 0 2006.285.12:49:01.00#ibcon#about to read 4, iclass 26, count 0 2006.285.12:49:01.00#ibcon#read 4, iclass 26, count 0 2006.285.12:49:01.00#ibcon#about to read 5, iclass 26, count 0 2006.285.12:49:01.00#ibcon#read 5, iclass 26, count 0 2006.285.12:49:01.00#ibcon#about to read 6, iclass 26, count 0 2006.285.12:49:01.00#ibcon#read 6, iclass 26, count 0 2006.285.12:49:01.00#ibcon#end of sib2, iclass 26, count 0 2006.285.12:49:01.00#ibcon#*mode == 0, iclass 26, count 0 2006.285.12:49:01.00#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.12:49:01.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.12:49:01.00#ibcon#*before write, iclass 26, count 0 2006.285.12:49:01.00#ibcon#enter sib2, iclass 26, count 0 2006.285.12:49:01.00#ibcon#flushed, iclass 26, count 0 2006.285.12:49:01.00#ibcon#about to write, iclass 26, count 0 2006.285.12:49:01.00#ibcon#wrote, iclass 26, count 0 2006.285.12:49:01.00#ibcon#about to read 3, iclass 26, count 0 2006.285.12:49:01.04#ibcon#read 3, iclass 26, count 0 2006.285.12:49:01.04#ibcon#about to read 4, iclass 26, count 0 2006.285.12:49:01.04#ibcon#read 4, iclass 26, count 0 2006.285.12:49:01.04#ibcon#about to read 5, iclass 26, count 0 2006.285.12:49:01.04#ibcon#read 5, iclass 26, count 0 2006.285.12:49:01.04#ibcon#about to read 6, iclass 26, count 0 2006.285.12:49:01.04#ibcon#read 6, iclass 26, count 0 2006.285.12:49:01.04#ibcon#end of sib2, iclass 26, count 0 2006.285.12:49:01.04#ibcon#*after write, iclass 26, count 0 2006.285.12:49:01.04#ibcon#*before return 0, iclass 26, count 0 2006.285.12:49:01.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:49:01.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:49:01.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.12:49:01.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.12:49:01.04$vck44/va=8,3 2006.285.12:49:01.04#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.12:49:01.04#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.12:49:01.04#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:01.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:49:01.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:49:01.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:49:01.10#ibcon#enter wrdev, iclass 28, count 2 2006.285.12:49:01.10#ibcon#first serial, iclass 28, count 2 2006.285.12:49:01.10#ibcon#enter sib2, iclass 28, count 2 2006.285.12:49:01.10#ibcon#flushed, iclass 28, count 2 2006.285.12:49:01.10#ibcon#about to write, iclass 28, count 2 2006.285.12:49:01.10#ibcon#wrote, iclass 28, count 2 2006.285.12:49:01.10#ibcon#about to read 3, iclass 28, count 2 2006.285.12:49:01.12#ibcon#read 3, iclass 28, count 2 2006.285.12:49:01.12#ibcon#about to read 4, iclass 28, count 2 2006.285.12:49:01.12#ibcon#read 4, iclass 28, count 2 2006.285.12:49:01.12#ibcon#about to read 5, iclass 28, count 2 2006.285.12:49:01.12#ibcon#read 5, iclass 28, count 2 2006.285.12:49:01.12#ibcon#about to read 6, iclass 28, count 2 2006.285.12:49:01.12#ibcon#read 6, iclass 28, count 2 2006.285.12:49:01.12#ibcon#end of sib2, iclass 28, count 2 2006.285.12:49:01.12#ibcon#*mode == 0, iclass 28, count 2 2006.285.12:49:01.12#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.12:49:01.12#ibcon#[25=AT08-03\r\n] 2006.285.12:49:01.12#ibcon#*before write, iclass 28, count 2 2006.285.12:49:01.12#ibcon#enter sib2, iclass 28, count 2 2006.285.12:49:01.12#ibcon#flushed, iclass 28, count 2 2006.285.12:49:01.12#ibcon#about to write, iclass 28, count 2 2006.285.12:49:01.12#ibcon#wrote, iclass 28, count 2 2006.285.12:49:01.12#ibcon#about to read 3, iclass 28, count 2 2006.285.12:49:01.15#ibcon#read 3, iclass 28, count 2 2006.285.12:49:01.15#ibcon#about to read 4, iclass 28, count 2 2006.285.12:49:01.15#ibcon#read 4, iclass 28, count 2 2006.285.12:49:01.15#ibcon#about to read 5, iclass 28, count 2 2006.285.12:49:01.15#ibcon#read 5, iclass 28, count 2 2006.285.12:49:01.15#ibcon#about to read 6, iclass 28, count 2 2006.285.12:49:01.15#ibcon#read 6, iclass 28, count 2 2006.285.12:49:01.15#ibcon#end of sib2, iclass 28, count 2 2006.285.12:49:01.15#ibcon#*after write, iclass 28, count 2 2006.285.12:49:01.15#ibcon#*before return 0, iclass 28, count 2 2006.285.12:49:01.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:49:01.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.12:49:01.15#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.12:49:01.15#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:01.15#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:49:01.27#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:49:01.27#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:49:01.27#ibcon#enter wrdev, iclass 28, count 0 2006.285.12:49:01.27#ibcon#first serial, iclass 28, count 0 2006.285.12:49:01.27#ibcon#enter sib2, iclass 28, count 0 2006.285.12:49:01.27#ibcon#flushed, iclass 28, count 0 2006.285.12:49:01.27#ibcon#about to write, iclass 28, count 0 2006.285.12:49:01.27#ibcon#wrote, iclass 28, count 0 2006.285.12:49:01.27#ibcon#about to read 3, iclass 28, count 0 2006.285.12:49:01.29#ibcon#read 3, iclass 28, count 0 2006.285.12:49:01.29#ibcon#about to read 4, iclass 28, count 0 2006.285.12:49:01.29#ibcon#read 4, iclass 28, count 0 2006.285.12:49:01.29#ibcon#about to read 5, iclass 28, count 0 2006.285.12:49:01.29#ibcon#read 5, iclass 28, count 0 2006.285.12:49:01.29#ibcon#about to read 6, iclass 28, count 0 2006.285.12:49:01.29#ibcon#read 6, iclass 28, count 0 2006.285.12:49:01.29#ibcon#end of sib2, iclass 28, count 0 2006.285.12:49:01.29#ibcon#*mode == 0, iclass 28, count 0 2006.285.12:49:01.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.12:49:01.29#ibcon#[25=USB\r\n] 2006.285.12:49:01.29#ibcon#*before write, iclass 28, count 0 2006.285.12:49:01.29#ibcon#enter sib2, iclass 28, count 0 2006.285.12:49:01.29#ibcon#flushed, iclass 28, count 0 2006.285.12:49:01.29#ibcon#about to write, iclass 28, count 0 2006.285.12:49:01.29#ibcon#wrote, iclass 28, count 0 2006.285.12:49:01.29#ibcon#about to read 3, iclass 28, count 0 2006.285.12:49:01.32#ibcon#read 3, iclass 28, count 0 2006.285.12:49:01.32#ibcon#about to read 4, iclass 28, count 0 2006.285.12:49:01.32#ibcon#read 4, iclass 28, count 0 2006.285.12:49:01.32#ibcon#about to read 5, iclass 28, count 0 2006.285.12:49:01.32#ibcon#read 5, iclass 28, count 0 2006.285.12:49:01.32#ibcon#about to read 6, iclass 28, count 0 2006.285.12:49:01.32#ibcon#read 6, iclass 28, count 0 2006.285.12:49:01.32#ibcon#end of sib2, iclass 28, count 0 2006.285.12:49:01.32#ibcon#*after write, iclass 28, count 0 2006.285.12:49:01.32#ibcon#*before return 0, iclass 28, count 0 2006.285.12:49:01.32#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:49:01.32#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.12:49:01.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.12:49:01.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.12:49:01.32$vck44/vblo=1,629.99 2006.285.12:49:01.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.12:49:01.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.12:49:01.32#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:01.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:49:01.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:49:01.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:49:01.32#ibcon#enter wrdev, iclass 30, count 0 2006.285.12:49:01.32#ibcon#first serial, iclass 30, count 0 2006.285.12:49:01.32#ibcon#enter sib2, iclass 30, count 0 2006.285.12:49:01.32#ibcon#flushed, iclass 30, count 0 2006.285.12:49:01.32#ibcon#about to write, iclass 30, count 0 2006.285.12:49:01.32#ibcon#wrote, iclass 30, count 0 2006.285.12:49:01.32#ibcon#about to read 3, iclass 30, count 0 2006.285.12:49:01.34#ibcon#read 3, iclass 30, count 0 2006.285.12:49:01.34#ibcon#about to read 4, iclass 30, count 0 2006.285.12:49:01.34#ibcon#read 4, iclass 30, count 0 2006.285.12:49:01.34#ibcon#about to read 5, iclass 30, count 0 2006.285.12:49:01.34#ibcon#read 5, iclass 30, count 0 2006.285.12:49:01.34#ibcon#about to read 6, iclass 30, count 0 2006.285.12:49:01.34#ibcon#read 6, iclass 30, count 0 2006.285.12:49:01.34#ibcon#end of sib2, iclass 30, count 0 2006.285.12:49:01.34#ibcon#*mode == 0, iclass 30, count 0 2006.285.12:49:01.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.12:49:01.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.12:49:01.34#ibcon#*before write, iclass 30, count 0 2006.285.12:49:01.34#ibcon#enter sib2, iclass 30, count 0 2006.285.12:49:01.34#ibcon#flushed, iclass 30, count 0 2006.285.12:49:01.34#ibcon#about to write, iclass 30, count 0 2006.285.12:49:01.34#ibcon#wrote, iclass 30, count 0 2006.285.12:49:01.34#ibcon#about to read 3, iclass 30, count 0 2006.285.12:49:01.38#ibcon#read 3, iclass 30, count 0 2006.285.12:49:01.38#ibcon#about to read 4, iclass 30, count 0 2006.285.12:49:01.38#ibcon#read 4, iclass 30, count 0 2006.285.12:49:01.38#ibcon#about to read 5, iclass 30, count 0 2006.285.12:49:01.38#ibcon#read 5, iclass 30, count 0 2006.285.12:49:01.38#ibcon#about to read 6, iclass 30, count 0 2006.285.12:49:01.38#ibcon#read 6, iclass 30, count 0 2006.285.12:49:01.38#ibcon#end of sib2, iclass 30, count 0 2006.285.12:49:01.38#ibcon#*after write, iclass 30, count 0 2006.285.12:49:01.38#ibcon#*before return 0, iclass 30, count 0 2006.285.12:49:01.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:49:01.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.12:49:01.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.12:49:01.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.12:49:01.38$vck44/vb=1,4 2006.285.12:49:01.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.12:49:01.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.12:49:01.38#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:01.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:49:01.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:49:01.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:49:01.38#ibcon#enter wrdev, iclass 32, count 2 2006.285.12:49:01.38#ibcon#first serial, iclass 32, count 2 2006.285.12:49:01.38#ibcon#enter sib2, iclass 32, count 2 2006.285.12:49:01.38#ibcon#flushed, iclass 32, count 2 2006.285.12:49:01.38#ibcon#about to write, iclass 32, count 2 2006.285.12:49:01.38#ibcon#wrote, iclass 32, count 2 2006.285.12:49:01.38#ibcon#about to read 3, iclass 32, count 2 2006.285.12:49:01.40#ibcon#read 3, iclass 32, count 2 2006.285.12:49:01.40#ibcon#about to read 4, iclass 32, count 2 2006.285.12:49:01.40#ibcon#read 4, iclass 32, count 2 2006.285.12:49:01.40#ibcon#about to read 5, iclass 32, count 2 2006.285.12:49:01.40#ibcon#read 5, iclass 32, count 2 2006.285.12:49:01.40#ibcon#about to read 6, iclass 32, count 2 2006.285.12:49:01.40#ibcon#read 6, iclass 32, count 2 2006.285.12:49:01.40#ibcon#end of sib2, iclass 32, count 2 2006.285.12:49:01.40#ibcon#*mode == 0, iclass 32, count 2 2006.285.12:49:01.40#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.12:49:01.40#ibcon#[27=AT01-04\r\n] 2006.285.12:49:01.40#ibcon#*before write, iclass 32, count 2 2006.285.12:49:01.40#ibcon#enter sib2, iclass 32, count 2 2006.285.12:49:01.40#ibcon#flushed, iclass 32, count 2 2006.285.12:49:01.40#ibcon#about to write, iclass 32, count 2 2006.285.12:49:01.40#ibcon#wrote, iclass 32, count 2 2006.285.12:49:01.40#ibcon#about to read 3, iclass 32, count 2 2006.285.12:49:01.43#ibcon#read 3, iclass 32, count 2 2006.285.12:49:01.43#ibcon#about to read 4, iclass 32, count 2 2006.285.12:49:01.43#ibcon#read 4, iclass 32, count 2 2006.285.12:49:01.43#ibcon#about to read 5, iclass 32, count 2 2006.285.12:49:01.43#ibcon#read 5, iclass 32, count 2 2006.285.12:49:01.43#ibcon#about to read 6, iclass 32, count 2 2006.285.12:49:01.43#ibcon#read 6, iclass 32, count 2 2006.285.12:49:01.43#ibcon#end of sib2, iclass 32, count 2 2006.285.12:49:01.43#ibcon#*after write, iclass 32, count 2 2006.285.12:49:01.43#ibcon#*before return 0, iclass 32, count 2 2006.285.12:49:01.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:49:01.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.12:49:01.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.12:49:01.43#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:01.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:49:01.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:49:01.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:49:01.55#ibcon#enter wrdev, iclass 32, count 0 2006.285.12:49:01.55#ibcon#first serial, iclass 32, count 0 2006.285.12:49:01.55#ibcon#enter sib2, iclass 32, count 0 2006.285.12:49:01.55#ibcon#flushed, iclass 32, count 0 2006.285.12:49:01.55#ibcon#about to write, iclass 32, count 0 2006.285.12:49:01.55#ibcon#wrote, iclass 32, count 0 2006.285.12:49:01.55#ibcon#about to read 3, iclass 32, count 0 2006.285.12:49:01.57#ibcon#read 3, iclass 32, count 0 2006.285.12:49:01.57#ibcon#about to read 4, iclass 32, count 0 2006.285.12:49:01.57#ibcon#read 4, iclass 32, count 0 2006.285.12:49:01.57#ibcon#about to read 5, iclass 32, count 0 2006.285.12:49:01.57#ibcon#read 5, iclass 32, count 0 2006.285.12:49:01.57#ibcon#about to read 6, iclass 32, count 0 2006.285.12:49:01.57#ibcon#read 6, iclass 32, count 0 2006.285.12:49:01.57#ibcon#end of sib2, iclass 32, count 0 2006.285.12:49:01.57#ibcon#*mode == 0, iclass 32, count 0 2006.285.12:49:01.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.12:49:01.57#ibcon#[27=USB\r\n] 2006.285.12:49:01.57#ibcon#*before write, iclass 32, count 0 2006.285.12:49:01.57#ibcon#enter sib2, iclass 32, count 0 2006.285.12:49:01.57#ibcon#flushed, iclass 32, count 0 2006.285.12:49:01.57#ibcon#about to write, iclass 32, count 0 2006.285.12:49:01.57#ibcon#wrote, iclass 32, count 0 2006.285.12:49:01.57#ibcon#about to read 3, iclass 32, count 0 2006.285.12:49:01.60#ibcon#read 3, iclass 32, count 0 2006.285.12:49:01.60#ibcon#about to read 4, iclass 32, count 0 2006.285.12:49:01.60#ibcon#read 4, iclass 32, count 0 2006.285.12:49:01.60#ibcon#about to read 5, iclass 32, count 0 2006.285.12:49:01.60#ibcon#read 5, iclass 32, count 0 2006.285.12:49:01.60#ibcon#about to read 6, iclass 32, count 0 2006.285.12:49:01.60#ibcon#read 6, iclass 32, count 0 2006.285.12:49:01.60#ibcon#end of sib2, iclass 32, count 0 2006.285.12:49:01.60#ibcon#*after write, iclass 32, count 0 2006.285.12:49:01.60#ibcon#*before return 0, iclass 32, count 0 2006.285.12:49:01.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:49:01.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.12:49:01.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.12:49:01.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.12:49:01.60$vck44/vblo=2,634.99 2006.285.12:49:01.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.12:49:01.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.12:49:01.60#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:01.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:49:01.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:49:01.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:49:01.60#ibcon#enter wrdev, iclass 34, count 0 2006.285.12:49:01.60#ibcon#first serial, iclass 34, count 0 2006.285.12:49:01.60#ibcon#enter sib2, iclass 34, count 0 2006.285.12:49:01.60#ibcon#flushed, iclass 34, count 0 2006.285.12:49:01.60#ibcon#about to write, iclass 34, count 0 2006.285.12:49:01.60#ibcon#wrote, iclass 34, count 0 2006.285.12:49:01.60#ibcon#about to read 3, iclass 34, count 0 2006.285.12:49:01.62#ibcon#read 3, iclass 34, count 0 2006.285.12:49:01.83#ibcon#about to read 4, iclass 34, count 0 2006.285.12:49:01.83#ibcon#read 4, iclass 34, count 0 2006.285.12:49:01.84#ibcon#about to read 5, iclass 34, count 0 2006.285.12:49:01.84#ibcon#read 5, iclass 34, count 0 2006.285.12:49:01.84#ibcon#about to read 6, iclass 34, count 0 2006.285.12:49:01.84#ibcon#read 6, iclass 34, count 0 2006.285.12:49:01.84#ibcon#end of sib2, iclass 34, count 0 2006.285.12:49:01.84#ibcon#*mode == 0, iclass 34, count 0 2006.285.12:49:01.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.12:49:01.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.12:49:01.84#ibcon#*before write, iclass 34, count 0 2006.285.12:49:01.84#ibcon#enter sib2, iclass 34, count 0 2006.285.12:49:01.84#ibcon#flushed, iclass 34, count 0 2006.285.12:49:01.84#ibcon#about to write, iclass 34, count 0 2006.285.12:49:01.84#ibcon#wrote, iclass 34, count 0 2006.285.12:49:01.84#ibcon#about to read 3, iclass 34, count 0 2006.285.12:49:01.88#ibcon#read 3, iclass 34, count 0 2006.285.12:49:01.88#ibcon#about to read 4, iclass 34, count 0 2006.285.12:49:01.88#ibcon#read 4, iclass 34, count 0 2006.285.12:49:01.88#ibcon#about to read 5, iclass 34, count 0 2006.285.12:49:01.88#ibcon#read 5, iclass 34, count 0 2006.285.12:49:01.88#ibcon#about to read 6, iclass 34, count 0 2006.285.12:49:01.88#ibcon#read 6, iclass 34, count 0 2006.285.12:49:01.88#ibcon#end of sib2, iclass 34, count 0 2006.285.12:49:01.88#ibcon#*after write, iclass 34, count 0 2006.285.12:49:01.88#ibcon#*before return 0, iclass 34, count 0 2006.285.12:49:01.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:49:01.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.12:49:01.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.12:49:01.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.12:49:01.88$vck44/vb=2,5 2006.285.12:49:01.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.12:49:01.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.12:49:01.88#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:01.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:49:01.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:49:01.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:49:01.88#ibcon#enter wrdev, iclass 36, count 2 2006.285.12:49:01.88#ibcon#first serial, iclass 36, count 2 2006.285.12:49:01.88#ibcon#enter sib2, iclass 36, count 2 2006.285.12:49:01.88#ibcon#flushed, iclass 36, count 2 2006.285.12:49:01.88#ibcon#about to write, iclass 36, count 2 2006.285.12:49:01.88#ibcon#wrote, iclass 36, count 2 2006.285.12:49:01.88#ibcon#about to read 3, iclass 36, count 2 2006.285.12:49:01.90#ibcon#read 3, iclass 36, count 2 2006.285.12:49:01.90#ibcon#about to read 4, iclass 36, count 2 2006.285.12:49:01.90#ibcon#read 4, iclass 36, count 2 2006.285.12:49:01.90#ibcon#about to read 5, iclass 36, count 2 2006.285.12:49:01.90#ibcon#read 5, iclass 36, count 2 2006.285.12:49:01.90#ibcon#about to read 6, iclass 36, count 2 2006.285.12:49:01.90#ibcon#read 6, iclass 36, count 2 2006.285.12:49:01.90#ibcon#end of sib2, iclass 36, count 2 2006.285.12:49:01.90#ibcon#*mode == 0, iclass 36, count 2 2006.285.12:49:01.90#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.12:49:01.90#ibcon#[27=AT02-05\r\n] 2006.285.12:49:01.90#ibcon#*before write, iclass 36, count 2 2006.285.12:49:01.90#ibcon#enter sib2, iclass 36, count 2 2006.285.12:49:01.90#ibcon#flushed, iclass 36, count 2 2006.285.12:49:01.90#ibcon#about to write, iclass 36, count 2 2006.285.12:49:01.90#ibcon#wrote, iclass 36, count 2 2006.285.12:49:01.90#ibcon#about to read 3, iclass 36, count 2 2006.285.12:49:01.93#ibcon#read 3, iclass 36, count 2 2006.285.12:49:01.93#ibcon#about to read 4, iclass 36, count 2 2006.285.12:49:01.93#ibcon#read 4, iclass 36, count 2 2006.285.12:49:01.93#ibcon#about to read 5, iclass 36, count 2 2006.285.12:49:01.93#ibcon#read 5, iclass 36, count 2 2006.285.12:49:01.93#ibcon#about to read 6, iclass 36, count 2 2006.285.12:49:01.93#ibcon#read 6, iclass 36, count 2 2006.285.12:49:01.93#ibcon#end of sib2, iclass 36, count 2 2006.285.12:49:01.93#ibcon#*after write, iclass 36, count 2 2006.285.12:49:01.93#ibcon#*before return 0, iclass 36, count 2 2006.285.12:49:01.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:49:01.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.12:49:01.93#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.12:49:01.93#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:01.93#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:49:02.05#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:49:02.05#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:49:02.05#ibcon#enter wrdev, iclass 36, count 0 2006.285.12:49:02.05#ibcon#first serial, iclass 36, count 0 2006.285.12:49:02.05#ibcon#enter sib2, iclass 36, count 0 2006.285.12:49:02.05#ibcon#flushed, iclass 36, count 0 2006.285.12:49:02.05#ibcon#about to write, iclass 36, count 0 2006.285.12:49:02.05#ibcon#wrote, iclass 36, count 0 2006.285.12:49:02.05#ibcon#about to read 3, iclass 36, count 0 2006.285.12:49:02.07#ibcon#read 3, iclass 36, count 0 2006.285.12:49:02.07#ibcon#about to read 4, iclass 36, count 0 2006.285.12:49:02.07#ibcon#read 4, iclass 36, count 0 2006.285.12:49:02.07#ibcon#about to read 5, iclass 36, count 0 2006.285.12:49:02.07#ibcon#read 5, iclass 36, count 0 2006.285.12:49:02.07#ibcon#about to read 6, iclass 36, count 0 2006.285.12:49:02.07#ibcon#read 6, iclass 36, count 0 2006.285.12:49:02.07#ibcon#end of sib2, iclass 36, count 0 2006.285.12:49:02.07#ibcon#*mode == 0, iclass 36, count 0 2006.285.12:49:02.07#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.12:49:02.07#ibcon#[27=USB\r\n] 2006.285.12:49:02.07#ibcon#*before write, iclass 36, count 0 2006.285.12:49:02.07#ibcon#enter sib2, iclass 36, count 0 2006.285.12:49:02.07#ibcon#flushed, iclass 36, count 0 2006.285.12:49:02.07#ibcon#about to write, iclass 36, count 0 2006.285.12:49:02.07#ibcon#wrote, iclass 36, count 0 2006.285.12:49:02.07#ibcon#about to read 3, iclass 36, count 0 2006.285.12:49:02.10#ibcon#read 3, iclass 36, count 0 2006.285.12:49:02.10#ibcon#about to read 4, iclass 36, count 0 2006.285.12:49:02.10#ibcon#read 4, iclass 36, count 0 2006.285.12:49:02.10#ibcon#about to read 5, iclass 36, count 0 2006.285.12:49:02.10#ibcon#read 5, iclass 36, count 0 2006.285.12:49:02.10#ibcon#about to read 6, iclass 36, count 0 2006.285.12:49:02.10#ibcon#read 6, iclass 36, count 0 2006.285.12:49:02.10#ibcon#end of sib2, iclass 36, count 0 2006.285.12:49:02.10#ibcon#*after write, iclass 36, count 0 2006.285.12:49:02.10#ibcon#*before return 0, iclass 36, count 0 2006.285.12:49:02.10#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:49:02.10#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.12:49:02.10#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.12:49:02.10#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.12:49:02.10$vck44/vblo=3,649.99 2006.285.12:49:02.10#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.12:49:02.10#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.12:49:02.10#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:02.10#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:49:02.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:49:02.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:49:02.10#ibcon#enter wrdev, iclass 38, count 0 2006.285.12:49:02.10#ibcon#first serial, iclass 38, count 0 2006.285.12:49:02.10#ibcon#enter sib2, iclass 38, count 0 2006.285.12:49:02.10#ibcon#flushed, iclass 38, count 0 2006.285.12:49:02.10#ibcon#about to write, iclass 38, count 0 2006.285.12:49:02.10#ibcon#wrote, iclass 38, count 0 2006.285.12:49:02.10#ibcon#about to read 3, iclass 38, count 0 2006.285.12:49:02.12#ibcon#read 3, iclass 38, count 0 2006.285.12:49:02.12#ibcon#about to read 4, iclass 38, count 0 2006.285.12:49:02.12#ibcon#read 4, iclass 38, count 0 2006.285.12:49:02.12#ibcon#about to read 5, iclass 38, count 0 2006.285.12:49:02.12#ibcon#read 5, iclass 38, count 0 2006.285.12:49:02.12#ibcon#about to read 6, iclass 38, count 0 2006.285.12:49:02.12#ibcon#read 6, iclass 38, count 0 2006.285.12:49:02.12#ibcon#end of sib2, iclass 38, count 0 2006.285.12:49:02.12#ibcon#*mode == 0, iclass 38, count 0 2006.285.12:49:02.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.12:49:02.12#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.12:49:02.12#ibcon#*before write, iclass 38, count 0 2006.285.12:49:02.12#ibcon#enter sib2, iclass 38, count 0 2006.285.12:49:02.12#ibcon#flushed, iclass 38, count 0 2006.285.12:49:02.12#ibcon#about to write, iclass 38, count 0 2006.285.12:49:02.12#ibcon#wrote, iclass 38, count 0 2006.285.12:49:02.12#ibcon#about to read 3, iclass 38, count 0 2006.285.12:49:02.16#ibcon#read 3, iclass 38, count 0 2006.285.12:49:02.16#ibcon#about to read 4, iclass 38, count 0 2006.285.12:49:02.16#ibcon#read 4, iclass 38, count 0 2006.285.12:49:02.16#ibcon#about to read 5, iclass 38, count 0 2006.285.12:49:02.16#ibcon#read 5, iclass 38, count 0 2006.285.12:49:02.16#ibcon#about to read 6, iclass 38, count 0 2006.285.12:49:02.16#ibcon#read 6, iclass 38, count 0 2006.285.12:49:02.16#ibcon#end of sib2, iclass 38, count 0 2006.285.12:49:02.16#ibcon#*after write, iclass 38, count 0 2006.285.12:49:02.16#ibcon#*before return 0, iclass 38, count 0 2006.285.12:49:02.16#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:49:02.16#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.12:49:02.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.12:49:02.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.12:49:02.16$vck44/vb=3,4 2006.285.12:49:02.16#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.12:49:02.16#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.12:49:02.16#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:02.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:49:02.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:49:02.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:49:02.22#ibcon#enter wrdev, iclass 40, count 2 2006.285.12:49:02.22#ibcon#first serial, iclass 40, count 2 2006.285.12:49:02.22#ibcon#enter sib2, iclass 40, count 2 2006.285.12:49:02.22#ibcon#flushed, iclass 40, count 2 2006.285.12:49:02.22#ibcon#about to write, iclass 40, count 2 2006.285.12:49:02.22#ibcon#wrote, iclass 40, count 2 2006.285.12:49:02.22#ibcon#about to read 3, iclass 40, count 2 2006.285.12:49:02.24#ibcon#read 3, iclass 40, count 2 2006.285.12:49:02.24#ibcon#about to read 4, iclass 40, count 2 2006.285.12:49:02.24#ibcon#read 4, iclass 40, count 2 2006.285.12:49:02.24#ibcon#about to read 5, iclass 40, count 2 2006.285.12:49:02.24#ibcon#read 5, iclass 40, count 2 2006.285.12:49:02.24#ibcon#about to read 6, iclass 40, count 2 2006.285.12:49:02.24#ibcon#read 6, iclass 40, count 2 2006.285.12:49:02.24#ibcon#end of sib2, iclass 40, count 2 2006.285.12:49:02.24#ibcon#*mode == 0, iclass 40, count 2 2006.285.12:49:02.24#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.12:49:02.24#ibcon#[27=AT03-04\r\n] 2006.285.12:49:02.24#ibcon#*before write, iclass 40, count 2 2006.285.12:49:02.24#ibcon#enter sib2, iclass 40, count 2 2006.285.12:49:02.24#ibcon#flushed, iclass 40, count 2 2006.285.12:49:02.24#ibcon#about to write, iclass 40, count 2 2006.285.12:49:02.24#ibcon#wrote, iclass 40, count 2 2006.285.12:49:02.24#ibcon#about to read 3, iclass 40, count 2 2006.285.12:49:02.27#ibcon#read 3, iclass 40, count 2 2006.285.12:49:02.27#ibcon#about to read 4, iclass 40, count 2 2006.285.12:49:02.27#ibcon#read 4, iclass 40, count 2 2006.285.12:49:02.27#ibcon#about to read 5, iclass 40, count 2 2006.285.12:49:02.27#ibcon#read 5, iclass 40, count 2 2006.285.12:49:02.27#ibcon#about to read 6, iclass 40, count 2 2006.285.12:49:02.27#ibcon#read 6, iclass 40, count 2 2006.285.12:49:02.27#ibcon#end of sib2, iclass 40, count 2 2006.285.12:49:02.27#ibcon#*after write, iclass 40, count 2 2006.285.12:49:02.27#ibcon#*before return 0, iclass 40, count 2 2006.285.12:49:02.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:49:02.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.12:49:02.27#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.12:49:02.27#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:02.27#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:49:02.39#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:49:02.39#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:49:02.39#ibcon#enter wrdev, iclass 40, count 0 2006.285.12:49:02.39#ibcon#first serial, iclass 40, count 0 2006.285.12:49:02.39#ibcon#enter sib2, iclass 40, count 0 2006.285.12:49:02.39#ibcon#flushed, iclass 40, count 0 2006.285.12:49:02.39#ibcon#about to write, iclass 40, count 0 2006.285.12:49:02.39#ibcon#wrote, iclass 40, count 0 2006.285.12:49:02.39#ibcon#about to read 3, iclass 40, count 0 2006.285.12:49:02.41#ibcon#read 3, iclass 40, count 0 2006.285.12:49:02.41#ibcon#about to read 4, iclass 40, count 0 2006.285.12:49:02.41#ibcon#read 4, iclass 40, count 0 2006.285.12:49:02.41#ibcon#about to read 5, iclass 40, count 0 2006.285.12:49:02.41#ibcon#read 5, iclass 40, count 0 2006.285.12:49:02.41#ibcon#about to read 6, iclass 40, count 0 2006.285.12:49:02.41#ibcon#read 6, iclass 40, count 0 2006.285.12:49:02.41#ibcon#end of sib2, iclass 40, count 0 2006.285.12:49:02.41#ibcon#*mode == 0, iclass 40, count 0 2006.285.12:49:02.41#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.12:49:02.41#ibcon#[27=USB\r\n] 2006.285.12:49:02.41#ibcon#*before write, iclass 40, count 0 2006.285.12:49:02.41#ibcon#enter sib2, iclass 40, count 0 2006.285.12:49:02.41#ibcon#flushed, iclass 40, count 0 2006.285.12:49:02.41#ibcon#about to write, iclass 40, count 0 2006.285.12:49:02.41#ibcon#wrote, iclass 40, count 0 2006.285.12:49:02.41#ibcon#about to read 3, iclass 40, count 0 2006.285.12:49:02.44#ibcon#read 3, iclass 40, count 0 2006.285.12:49:02.44#ibcon#about to read 4, iclass 40, count 0 2006.285.12:49:02.44#ibcon#read 4, iclass 40, count 0 2006.285.12:49:02.44#ibcon#about to read 5, iclass 40, count 0 2006.285.12:49:02.44#ibcon#read 5, iclass 40, count 0 2006.285.12:49:02.44#ibcon#about to read 6, iclass 40, count 0 2006.285.12:49:02.44#ibcon#read 6, iclass 40, count 0 2006.285.12:49:02.44#ibcon#end of sib2, iclass 40, count 0 2006.285.12:49:02.44#ibcon#*after write, iclass 40, count 0 2006.285.12:49:02.44#ibcon#*before return 0, iclass 40, count 0 2006.285.12:49:02.44#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:49:02.44#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.12:49:02.44#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.12:49:02.44#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.12:49:02.44$vck44/vblo=4,679.99 2006.285.12:49:02.44#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.12:49:02.44#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.12:49:02.44#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:02.44#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:49:02.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:49:02.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:49:02.44#ibcon#enter wrdev, iclass 4, count 0 2006.285.12:49:02.44#ibcon#first serial, iclass 4, count 0 2006.285.12:49:02.44#ibcon#enter sib2, iclass 4, count 0 2006.285.12:49:02.44#ibcon#flushed, iclass 4, count 0 2006.285.12:49:02.44#ibcon#about to write, iclass 4, count 0 2006.285.12:49:02.44#ibcon#wrote, iclass 4, count 0 2006.285.12:49:02.44#ibcon#about to read 3, iclass 4, count 0 2006.285.12:49:02.46#ibcon#read 3, iclass 4, count 0 2006.285.12:49:02.46#ibcon#about to read 4, iclass 4, count 0 2006.285.12:49:02.46#ibcon#read 4, iclass 4, count 0 2006.285.12:49:02.46#ibcon#about to read 5, iclass 4, count 0 2006.285.12:49:02.46#ibcon#read 5, iclass 4, count 0 2006.285.12:49:02.46#ibcon#about to read 6, iclass 4, count 0 2006.285.12:49:02.46#ibcon#read 6, iclass 4, count 0 2006.285.12:49:02.46#ibcon#end of sib2, iclass 4, count 0 2006.285.12:49:02.46#ibcon#*mode == 0, iclass 4, count 0 2006.285.12:49:02.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.12:49:02.46#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.12:49:02.46#ibcon#*before write, iclass 4, count 0 2006.285.12:49:02.46#ibcon#enter sib2, iclass 4, count 0 2006.285.12:49:02.46#ibcon#flushed, iclass 4, count 0 2006.285.12:49:02.46#ibcon#about to write, iclass 4, count 0 2006.285.12:49:02.46#ibcon#wrote, iclass 4, count 0 2006.285.12:49:02.46#ibcon#about to read 3, iclass 4, count 0 2006.285.12:49:02.50#ibcon#read 3, iclass 4, count 0 2006.285.12:49:02.50#ibcon#about to read 4, iclass 4, count 0 2006.285.12:49:02.50#ibcon#read 4, iclass 4, count 0 2006.285.12:49:02.50#ibcon#about to read 5, iclass 4, count 0 2006.285.12:49:02.50#ibcon#read 5, iclass 4, count 0 2006.285.12:49:02.50#ibcon#about to read 6, iclass 4, count 0 2006.285.12:49:02.50#ibcon#read 6, iclass 4, count 0 2006.285.12:49:02.50#ibcon#end of sib2, iclass 4, count 0 2006.285.12:49:02.50#ibcon#*after write, iclass 4, count 0 2006.285.12:49:02.50#ibcon#*before return 0, iclass 4, count 0 2006.285.12:49:02.50#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:49:02.50#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.12:49:02.50#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.12:49:02.50#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.12:49:02.50$vck44/vb=4,5 2006.285.12:49:02.50#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.12:49:02.50#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.12:49:02.50#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:02.50#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:49:02.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:49:02.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:49:02.56#ibcon#enter wrdev, iclass 6, count 2 2006.285.12:49:02.56#ibcon#first serial, iclass 6, count 2 2006.285.12:49:02.56#ibcon#enter sib2, iclass 6, count 2 2006.285.12:49:02.56#ibcon#flushed, iclass 6, count 2 2006.285.12:49:02.56#ibcon#about to write, iclass 6, count 2 2006.285.12:49:02.56#ibcon#wrote, iclass 6, count 2 2006.285.12:49:02.56#ibcon#about to read 3, iclass 6, count 2 2006.285.12:49:02.58#ibcon#read 3, iclass 6, count 2 2006.285.12:49:02.58#ibcon#about to read 4, iclass 6, count 2 2006.285.12:49:02.58#ibcon#read 4, iclass 6, count 2 2006.285.12:49:02.58#ibcon#about to read 5, iclass 6, count 2 2006.285.12:49:02.58#ibcon#read 5, iclass 6, count 2 2006.285.12:49:02.58#ibcon#about to read 6, iclass 6, count 2 2006.285.12:49:02.58#ibcon#read 6, iclass 6, count 2 2006.285.12:49:02.58#ibcon#end of sib2, iclass 6, count 2 2006.285.12:49:02.58#ibcon#*mode == 0, iclass 6, count 2 2006.285.12:49:02.58#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.12:49:02.58#ibcon#[27=AT04-05\r\n] 2006.285.12:49:02.58#ibcon#*before write, iclass 6, count 2 2006.285.12:49:02.58#ibcon#enter sib2, iclass 6, count 2 2006.285.12:49:02.58#ibcon#flushed, iclass 6, count 2 2006.285.12:49:02.58#ibcon#about to write, iclass 6, count 2 2006.285.12:49:02.58#ibcon#wrote, iclass 6, count 2 2006.285.12:49:02.58#ibcon#about to read 3, iclass 6, count 2 2006.285.12:49:02.61#ibcon#read 3, iclass 6, count 2 2006.285.12:49:02.61#ibcon#about to read 4, iclass 6, count 2 2006.285.12:49:02.61#ibcon#read 4, iclass 6, count 2 2006.285.12:49:02.61#ibcon#about to read 5, iclass 6, count 2 2006.285.12:49:02.61#ibcon#read 5, iclass 6, count 2 2006.285.12:49:02.61#ibcon#about to read 6, iclass 6, count 2 2006.285.12:49:02.61#ibcon#read 6, iclass 6, count 2 2006.285.12:49:02.61#ibcon#end of sib2, iclass 6, count 2 2006.285.12:49:02.61#ibcon#*after write, iclass 6, count 2 2006.285.12:49:02.61#ibcon#*before return 0, iclass 6, count 2 2006.285.12:49:02.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:49:02.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.12:49:02.61#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.12:49:02.61#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:02.61#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:49:02.73#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:49:02.73#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:49:02.73#ibcon#enter wrdev, iclass 6, count 0 2006.285.12:49:02.73#ibcon#first serial, iclass 6, count 0 2006.285.12:49:02.73#ibcon#enter sib2, iclass 6, count 0 2006.285.12:49:02.73#ibcon#flushed, iclass 6, count 0 2006.285.12:49:02.73#ibcon#about to write, iclass 6, count 0 2006.285.12:49:02.73#ibcon#wrote, iclass 6, count 0 2006.285.12:49:02.73#ibcon#about to read 3, iclass 6, count 0 2006.285.12:49:02.75#ibcon#read 3, iclass 6, count 0 2006.285.12:49:02.75#ibcon#about to read 4, iclass 6, count 0 2006.285.12:49:02.75#ibcon#read 4, iclass 6, count 0 2006.285.12:49:02.75#ibcon#about to read 5, iclass 6, count 0 2006.285.12:49:02.75#ibcon#read 5, iclass 6, count 0 2006.285.12:49:02.75#ibcon#about to read 6, iclass 6, count 0 2006.285.12:49:02.75#ibcon#read 6, iclass 6, count 0 2006.285.12:49:02.75#ibcon#end of sib2, iclass 6, count 0 2006.285.12:49:02.75#ibcon#*mode == 0, iclass 6, count 0 2006.285.12:49:02.75#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.12:49:02.75#ibcon#[27=USB\r\n] 2006.285.12:49:02.75#ibcon#*before write, iclass 6, count 0 2006.285.12:49:02.75#ibcon#enter sib2, iclass 6, count 0 2006.285.12:49:02.75#ibcon#flushed, iclass 6, count 0 2006.285.12:49:02.75#ibcon#about to write, iclass 6, count 0 2006.285.12:49:02.75#ibcon#wrote, iclass 6, count 0 2006.285.12:49:02.75#ibcon#about to read 3, iclass 6, count 0 2006.285.12:49:02.78#ibcon#read 3, iclass 6, count 0 2006.285.12:49:02.78#ibcon#about to read 4, iclass 6, count 0 2006.285.12:49:02.78#ibcon#read 4, iclass 6, count 0 2006.285.12:49:02.78#ibcon#about to read 5, iclass 6, count 0 2006.285.12:49:02.78#ibcon#read 5, iclass 6, count 0 2006.285.12:49:02.78#ibcon#about to read 6, iclass 6, count 0 2006.285.12:49:02.78#ibcon#read 6, iclass 6, count 0 2006.285.12:49:02.78#ibcon#end of sib2, iclass 6, count 0 2006.285.12:49:02.78#ibcon#*after write, iclass 6, count 0 2006.285.12:49:02.78#ibcon#*before return 0, iclass 6, count 0 2006.285.12:49:02.78#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:49:02.78#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.12:49:02.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.12:49:02.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.12:49:02.78$vck44/vblo=5,709.99 2006.285.12:49:02.78#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.12:49:02.78#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.12:49:02.78#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:02.78#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:49:02.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:49:02.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:49:02.78#ibcon#enter wrdev, iclass 10, count 0 2006.285.12:49:02.78#ibcon#first serial, iclass 10, count 0 2006.285.12:49:02.78#ibcon#enter sib2, iclass 10, count 0 2006.285.12:49:02.78#ibcon#flushed, iclass 10, count 0 2006.285.12:49:02.78#ibcon#about to write, iclass 10, count 0 2006.285.12:49:02.78#ibcon#wrote, iclass 10, count 0 2006.285.12:49:02.78#ibcon#about to read 3, iclass 10, count 0 2006.285.12:49:02.80#ibcon#read 3, iclass 10, count 0 2006.285.12:49:02.80#ibcon#about to read 4, iclass 10, count 0 2006.285.12:49:02.80#ibcon#read 4, iclass 10, count 0 2006.285.12:49:02.80#ibcon#about to read 5, iclass 10, count 0 2006.285.12:49:02.80#ibcon#read 5, iclass 10, count 0 2006.285.12:49:02.80#ibcon#about to read 6, iclass 10, count 0 2006.285.12:49:02.80#ibcon#read 6, iclass 10, count 0 2006.285.12:49:02.80#ibcon#end of sib2, iclass 10, count 0 2006.285.12:49:02.80#ibcon#*mode == 0, iclass 10, count 0 2006.285.12:49:02.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.12:49:02.80#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.12:49:02.80#ibcon#*before write, iclass 10, count 0 2006.285.12:49:02.80#ibcon#enter sib2, iclass 10, count 0 2006.285.12:49:02.80#ibcon#flushed, iclass 10, count 0 2006.285.12:49:02.80#ibcon#about to write, iclass 10, count 0 2006.285.12:49:02.80#ibcon#wrote, iclass 10, count 0 2006.285.12:49:02.80#ibcon#about to read 3, iclass 10, count 0 2006.285.12:49:02.84#ibcon#read 3, iclass 10, count 0 2006.285.12:49:02.84#ibcon#about to read 4, iclass 10, count 0 2006.285.12:49:02.84#ibcon#read 4, iclass 10, count 0 2006.285.12:49:02.84#ibcon#about to read 5, iclass 10, count 0 2006.285.12:49:02.84#ibcon#read 5, iclass 10, count 0 2006.285.12:49:02.84#ibcon#about to read 6, iclass 10, count 0 2006.285.12:49:02.84#ibcon#read 6, iclass 10, count 0 2006.285.12:49:02.84#ibcon#end of sib2, iclass 10, count 0 2006.285.12:49:02.84#ibcon#*after write, iclass 10, count 0 2006.285.12:49:02.84#ibcon#*before return 0, iclass 10, count 0 2006.285.12:49:02.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:49:02.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.12:49:02.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.12:49:02.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.12:49:02.84$vck44/vb=5,4 2006.285.12:49:02.84#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.12:49:02.84#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.12:49:02.84#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:02.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:49:02.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:49:02.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:49:02.90#ibcon#enter wrdev, iclass 12, count 2 2006.285.12:49:02.90#ibcon#first serial, iclass 12, count 2 2006.285.12:49:02.90#ibcon#enter sib2, iclass 12, count 2 2006.285.12:49:02.90#ibcon#flushed, iclass 12, count 2 2006.285.12:49:02.90#ibcon#about to write, iclass 12, count 2 2006.285.12:49:02.90#ibcon#wrote, iclass 12, count 2 2006.285.12:49:02.90#ibcon#about to read 3, iclass 12, count 2 2006.285.12:49:02.92#ibcon#read 3, iclass 12, count 2 2006.285.12:49:02.92#ibcon#about to read 4, iclass 12, count 2 2006.285.12:49:02.92#ibcon#read 4, iclass 12, count 2 2006.285.12:49:02.92#ibcon#about to read 5, iclass 12, count 2 2006.285.12:49:02.92#ibcon#read 5, iclass 12, count 2 2006.285.12:49:02.92#ibcon#about to read 6, iclass 12, count 2 2006.285.12:49:02.92#ibcon#read 6, iclass 12, count 2 2006.285.12:49:02.92#ibcon#end of sib2, iclass 12, count 2 2006.285.12:49:02.92#ibcon#*mode == 0, iclass 12, count 2 2006.285.12:49:02.92#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.12:49:02.92#ibcon#[27=AT05-04\r\n] 2006.285.12:49:02.92#ibcon#*before write, iclass 12, count 2 2006.285.12:49:02.92#ibcon#enter sib2, iclass 12, count 2 2006.285.12:49:02.92#ibcon#flushed, iclass 12, count 2 2006.285.12:49:02.92#ibcon#about to write, iclass 12, count 2 2006.285.12:49:02.92#ibcon#wrote, iclass 12, count 2 2006.285.12:49:02.92#ibcon#about to read 3, iclass 12, count 2 2006.285.12:49:02.95#ibcon#read 3, iclass 12, count 2 2006.285.12:49:02.95#ibcon#about to read 4, iclass 12, count 2 2006.285.12:49:02.95#ibcon#read 4, iclass 12, count 2 2006.285.12:49:02.95#ibcon#about to read 5, iclass 12, count 2 2006.285.12:49:02.95#ibcon#read 5, iclass 12, count 2 2006.285.12:49:02.95#ibcon#about to read 6, iclass 12, count 2 2006.285.12:49:02.95#ibcon#read 6, iclass 12, count 2 2006.285.12:49:02.95#ibcon#end of sib2, iclass 12, count 2 2006.285.12:49:02.95#ibcon#*after write, iclass 12, count 2 2006.285.12:49:02.95#ibcon#*before return 0, iclass 12, count 2 2006.285.12:49:02.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:49:02.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.12:49:02.95#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.12:49:02.95#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:02.95#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:49:03.07#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:49:03.07#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:49:03.07#ibcon#enter wrdev, iclass 12, count 0 2006.285.12:49:03.07#ibcon#first serial, iclass 12, count 0 2006.285.12:49:03.07#ibcon#enter sib2, iclass 12, count 0 2006.285.12:49:03.07#ibcon#flushed, iclass 12, count 0 2006.285.12:49:03.07#ibcon#about to write, iclass 12, count 0 2006.285.12:49:03.07#ibcon#wrote, iclass 12, count 0 2006.285.12:49:03.07#ibcon#about to read 3, iclass 12, count 0 2006.285.12:49:03.09#ibcon#read 3, iclass 12, count 0 2006.285.12:49:03.09#ibcon#about to read 4, iclass 12, count 0 2006.285.12:49:03.09#ibcon#read 4, iclass 12, count 0 2006.285.12:49:03.09#ibcon#about to read 5, iclass 12, count 0 2006.285.12:49:03.09#ibcon#read 5, iclass 12, count 0 2006.285.12:49:03.09#ibcon#about to read 6, iclass 12, count 0 2006.285.12:49:03.09#ibcon#read 6, iclass 12, count 0 2006.285.12:49:03.09#ibcon#end of sib2, iclass 12, count 0 2006.285.12:49:03.09#ibcon#*mode == 0, iclass 12, count 0 2006.285.12:49:03.09#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.12:49:03.09#ibcon#[27=USB\r\n] 2006.285.12:49:03.09#ibcon#*before write, iclass 12, count 0 2006.285.12:49:03.09#ibcon#enter sib2, iclass 12, count 0 2006.285.12:49:03.09#ibcon#flushed, iclass 12, count 0 2006.285.12:49:03.09#ibcon#about to write, iclass 12, count 0 2006.285.12:49:03.09#ibcon#wrote, iclass 12, count 0 2006.285.12:49:03.09#ibcon#about to read 3, iclass 12, count 0 2006.285.12:49:03.12#ibcon#read 3, iclass 12, count 0 2006.285.12:49:03.12#ibcon#about to read 4, iclass 12, count 0 2006.285.12:49:03.12#ibcon#read 4, iclass 12, count 0 2006.285.12:49:03.12#ibcon#about to read 5, iclass 12, count 0 2006.285.12:49:03.12#ibcon#read 5, iclass 12, count 0 2006.285.12:49:03.12#ibcon#about to read 6, iclass 12, count 0 2006.285.12:49:03.12#ibcon#read 6, iclass 12, count 0 2006.285.12:49:03.12#ibcon#end of sib2, iclass 12, count 0 2006.285.12:49:03.12#ibcon#*after write, iclass 12, count 0 2006.285.12:49:03.12#ibcon#*before return 0, iclass 12, count 0 2006.285.12:49:03.12#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:49:03.12#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.12:49:03.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.12:49:03.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.12:49:03.12$vck44/vblo=6,719.99 2006.285.12:49:03.12#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.12:49:03.12#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.12:49:03.12#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:03.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:49:03.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:49:03.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:49:03.12#ibcon#enter wrdev, iclass 14, count 0 2006.285.12:49:03.12#ibcon#first serial, iclass 14, count 0 2006.285.12:49:03.12#ibcon#enter sib2, iclass 14, count 0 2006.285.12:49:03.12#ibcon#flushed, iclass 14, count 0 2006.285.12:49:03.12#ibcon#about to write, iclass 14, count 0 2006.285.12:49:03.12#ibcon#wrote, iclass 14, count 0 2006.285.12:49:03.12#ibcon#about to read 3, iclass 14, count 0 2006.285.12:49:03.14#ibcon#read 3, iclass 14, count 0 2006.285.12:49:03.14#ibcon#about to read 4, iclass 14, count 0 2006.285.12:49:03.14#ibcon#read 4, iclass 14, count 0 2006.285.12:49:03.14#ibcon#about to read 5, iclass 14, count 0 2006.285.12:49:03.14#ibcon#read 5, iclass 14, count 0 2006.285.12:49:03.14#ibcon#about to read 6, iclass 14, count 0 2006.285.12:49:03.14#ibcon#read 6, iclass 14, count 0 2006.285.12:49:03.14#ibcon#end of sib2, iclass 14, count 0 2006.285.12:49:03.14#ibcon#*mode == 0, iclass 14, count 0 2006.285.12:49:03.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.12:49:03.14#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.12:49:03.14#ibcon#*before write, iclass 14, count 0 2006.285.12:49:03.14#ibcon#enter sib2, iclass 14, count 0 2006.285.12:49:03.14#ibcon#flushed, iclass 14, count 0 2006.285.12:49:03.14#ibcon#about to write, iclass 14, count 0 2006.285.12:49:03.14#ibcon#wrote, iclass 14, count 0 2006.285.12:49:03.14#ibcon#about to read 3, iclass 14, count 0 2006.285.12:49:03.18#ibcon#read 3, iclass 14, count 0 2006.285.12:49:03.18#ibcon#about to read 4, iclass 14, count 0 2006.285.12:49:03.18#ibcon#read 4, iclass 14, count 0 2006.285.12:49:03.18#ibcon#about to read 5, iclass 14, count 0 2006.285.12:49:03.18#ibcon#read 5, iclass 14, count 0 2006.285.12:49:03.18#ibcon#about to read 6, iclass 14, count 0 2006.285.12:49:03.18#ibcon#read 6, iclass 14, count 0 2006.285.12:49:03.18#ibcon#end of sib2, iclass 14, count 0 2006.285.12:49:03.18#ibcon#*after write, iclass 14, count 0 2006.285.12:49:03.18#ibcon#*before return 0, iclass 14, count 0 2006.285.12:49:03.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:49:03.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.12:49:03.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.12:49:03.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.12:49:03.18$vck44/vb=6,3 2006.285.12:49:03.18#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.12:49:03.18#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.12:49:03.18#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:03.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:49:03.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:49:03.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:49:03.24#ibcon#enter wrdev, iclass 16, count 2 2006.285.12:49:03.24#ibcon#first serial, iclass 16, count 2 2006.285.12:49:03.24#ibcon#enter sib2, iclass 16, count 2 2006.285.12:49:03.24#ibcon#flushed, iclass 16, count 2 2006.285.12:49:03.24#ibcon#about to write, iclass 16, count 2 2006.285.12:49:03.24#ibcon#wrote, iclass 16, count 2 2006.285.12:49:03.24#ibcon#about to read 3, iclass 16, count 2 2006.285.12:49:03.26#ibcon#read 3, iclass 16, count 2 2006.285.12:49:03.26#ibcon#about to read 4, iclass 16, count 2 2006.285.12:49:03.26#ibcon#read 4, iclass 16, count 2 2006.285.12:49:03.26#ibcon#about to read 5, iclass 16, count 2 2006.285.12:49:03.26#ibcon#read 5, iclass 16, count 2 2006.285.12:49:03.26#ibcon#about to read 6, iclass 16, count 2 2006.285.12:49:03.26#ibcon#read 6, iclass 16, count 2 2006.285.12:49:03.26#ibcon#end of sib2, iclass 16, count 2 2006.285.12:49:03.26#ibcon#*mode == 0, iclass 16, count 2 2006.285.12:49:03.26#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.12:49:03.26#ibcon#[27=AT06-03\r\n] 2006.285.12:49:03.26#ibcon#*before write, iclass 16, count 2 2006.285.12:49:03.26#ibcon#enter sib2, iclass 16, count 2 2006.285.12:49:03.26#ibcon#flushed, iclass 16, count 2 2006.285.12:49:03.26#ibcon#about to write, iclass 16, count 2 2006.285.12:49:03.26#ibcon#wrote, iclass 16, count 2 2006.285.12:49:03.26#ibcon#about to read 3, iclass 16, count 2 2006.285.12:49:03.29#ibcon#read 3, iclass 16, count 2 2006.285.12:49:03.29#ibcon#about to read 4, iclass 16, count 2 2006.285.12:49:03.29#ibcon#read 4, iclass 16, count 2 2006.285.12:49:03.29#ibcon#about to read 5, iclass 16, count 2 2006.285.12:49:03.29#ibcon#read 5, iclass 16, count 2 2006.285.12:49:03.29#ibcon#about to read 6, iclass 16, count 2 2006.285.12:49:03.29#ibcon#read 6, iclass 16, count 2 2006.285.12:49:03.29#ibcon#end of sib2, iclass 16, count 2 2006.285.12:49:03.29#ibcon#*after write, iclass 16, count 2 2006.285.12:49:03.29#ibcon#*before return 0, iclass 16, count 2 2006.285.12:49:03.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:49:03.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.12:49:03.29#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.12:49:03.29#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:03.29#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:49:03.41#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:49:03.41#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:49:03.41#ibcon#enter wrdev, iclass 16, count 0 2006.285.12:49:03.41#ibcon#first serial, iclass 16, count 0 2006.285.12:49:03.41#ibcon#enter sib2, iclass 16, count 0 2006.285.12:49:03.41#ibcon#flushed, iclass 16, count 0 2006.285.12:49:03.41#ibcon#about to write, iclass 16, count 0 2006.285.12:49:03.41#ibcon#wrote, iclass 16, count 0 2006.285.12:49:03.41#ibcon#about to read 3, iclass 16, count 0 2006.285.12:49:03.43#ibcon#read 3, iclass 16, count 0 2006.285.12:49:03.43#ibcon#about to read 4, iclass 16, count 0 2006.285.12:49:03.43#ibcon#read 4, iclass 16, count 0 2006.285.12:49:03.43#ibcon#about to read 5, iclass 16, count 0 2006.285.12:49:03.43#ibcon#read 5, iclass 16, count 0 2006.285.12:49:03.43#ibcon#about to read 6, iclass 16, count 0 2006.285.12:49:03.43#ibcon#read 6, iclass 16, count 0 2006.285.12:49:03.43#ibcon#end of sib2, iclass 16, count 0 2006.285.12:49:03.43#ibcon#*mode == 0, iclass 16, count 0 2006.285.12:49:03.43#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.12:49:03.43#ibcon#[27=USB\r\n] 2006.285.12:49:03.43#ibcon#*before write, iclass 16, count 0 2006.285.12:49:03.43#ibcon#enter sib2, iclass 16, count 0 2006.285.12:49:03.43#ibcon#flushed, iclass 16, count 0 2006.285.12:49:03.43#ibcon#about to write, iclass 16, count 0 2006.285.12:49:03.43#ibcon#wrote, iclass 16, count 0 2006.285.12:49:03.43#ibcon#about to read 3, iclass 16, count 0 2006.285.12:49:03.46#ibcon#read 3, iclass 16, count 0 2006.285.12:49:03.46#ibcon#about to read 4, iclass 16, count 0 2006.285.12:49:03.46#ibcon#read 4, iclass 16, count 0 2006.285.12:49:03.46#ibcon#about to read 5, iclass 16, count 0 2006.285.12:49:03.46#ibcon#read 5, iclass 16, count 0 2006.285.12:49:03.46#ibcon#about to read 6, iclass 16, count 0 2006.285.12:49:03.46#ibcon#read 6, iclass 16, count 0 2006.285.12:49:03.46#ibcon#end of sib2, iclass 16, count 0 2006.285.12:49:03.46#ibcon#*after write, iclass 16, count 0 2006.285.12:49:03.46#ibcon#*before return 0, iclass 16, count 0 2006.285.12:49:03.46#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:49:03.46#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.12:49:03.46#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.12:49:03.46#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.12:49:03.46$vck44/vblo=7,734.99 2006.285.12:49:03.46#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.12:49:03.46#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.12:49:03.46#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:03.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:49:03.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:49:03.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:49:03.46#ibcon#enter wrdev, iclass 18, count 0 2006.285.12:49:03.46#ibcon#first serial, iclass 18, count 0 2006.285.12:49:03.46#ibcon#enter sib2, iclass 18, count 0 2006.285.12:49:03.46#ibcon#flushed, iclass 18, count 0 2006.285.12:49:03.46#ibcon#about to write, iclass 18, count 0 2006.285.12:49:03.46#ibcon#wrote, iclass 18, count 0 2006.285.12:49:03.46#ibcon#about to read 3, iclass 18, count 0 2006.285.12:49:03.48#ibcon#read 3, iclass 18, count 0 2006.285.12:49:03.48#ibcon#about to read 4, iclass 18, count 0 2006.285.12:49:03.48#ibcon#read 4, iclass 18, count 0 2006.285.12:49:03.48#ibcon#about to read 5, iclass 18, count 0 2006.285.12:49:03.48#ibcon#read 5, iclass 18, count 0 2006.285.12:49:03.48#ibcon#about to read 6, iclass 18, count 0 2006.285.12:49:03.48#ibcon#read 6, iclass 18, count 0 2006.285.12:49:03.48#ibcon#end of sib2, iclass 18, count 0 2006.285.12:49:03.48#ibcon#*mode == 0, iclass 18, count 0 2006.285.12:49:03.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.12:49:03.48#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.12:49:03.48#ibcon#*before write, iclass 18, count 0 2006.285.12:49:03.48#ibcon#enter sib2, iclass 18, count 0 2006.285.12:49:03.48#ibcon#flushed, iclass 18, count 0 2006.285.12:49:03.48#ibcon#about to write, iclass 18, count 0 2006.285.12:49:03.48#ibcon#wrote, iclass 18, count 0 2006.285.12:49:03.48#ibcon#about to read 3, iclass 18, count 0 2006.285.12:49:03.52#ibcon#read 3, iclass 18, count 0 2006.285.12:49:03.52#ibcon#about to read 4, iclass 18, count 0 2006.285.12:49:03.52#ibcon#read 4, iclass 18, count 0 2006.285.12:49:03.52#ibcon#about to read 5, iclass 18, count 0 2006.285.12:49:03.52#ibcon#read 5, iclass 18, count 0 2006.285.12:49:03.52#ibcon#about to read 6, iclass 18, count 0 2006.285.12:49:03.52#ibcon#read 6, iclass 18, count 0 2006.285.12:49:03.52#ibcon#end of sib2, iclass 18, count 0 2006.285.12:49:03.52#ibcon#*after write, iclass 18, count 0 2006.285.12:49:03.52#ibcon#*before return 0, iclass 18, count 0 2006.285.12:49:03.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:49:03.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:49:03.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.12:49:03.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.12:49:03.52$vck44/vb=7,4 2006.285.12:49:03.52#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.12:49:03.52#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.12:49:03.52#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:03.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:49:03.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:49:03.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:49:03.58#ibcon#enter wrdev, iclass 20, count 2 2006.285.12:49:03.58#ibcon#first serial, iclass 20, count 2 2006.285.12:49:03.58#ibcon#enter sib2, iclass 20, count 2 2006.285.12:49:03.58#ibcon#flushed, iclass 20, count 2 2006.285.12:49:03.58#ibcon#about to write, iclass 20, count 2 2006.285.12:49:03.58#ibcon#wrote, iclass 20, count 2 2006.285.12:49:03.58#ibcon#about to read 3, iclass 20, count 2 2006.285.12:49:03.60#ibcon#read 3, iclass 20, count 2 2006.285.12:49:03.60#ibcon#about to read 4, iclass 20, count 2 2006.285.12:49:03.60#ibcon#read 4, iclass 20, count 2 2006.285.12:49:03.60#ibcon#about to read 5, iclass 20, count 2 2006.285.12:49:03.60#ibcon#read 5, iclass 20, count 2 2006.285.12:49:03.60#ibcon#about to read 6, iclass 20, count 2 2006.285.12:49:03.60#ibcon#read 6, iclass 20, count 2 2006.285.12:49:03.60#ibcon#end of sib2, iclass 20, count 2 2006.285.12:49:03.60#ibcon#*mode == 0, iclass 20, count 2 2006.285.12:49:03.60#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.12:49:03.60#ibcon#[27=AT07-04\r\n] 2006.285.12:49:03.60#ibcon#*before write, iclass 20, count 2 2006.285.12:49:03.60#ibcon#enter sib2, iclass 20, count 2 2006.285.12:49:03.60#ibcon#flushed, iclass 20, count 2 2006.285.12:49:03.60#ibcon#about to write, iclass 20, count 2 2006.285.12:49:03.60#ibcon#wrote, iclass 20, count 2 2006.285.12:49:03.60#ibcon#about to read 3, iclass 20, count 2 2006.285.12:49:03.63#ibcon#read 3, iclass 20, count 2 2006.285.12:49:03.63#ibcon#about to read 4, iclass 20, count 2 2006.285.12:49:03.63#ibcon#read 4, iclass 20, count 2 2006.285.12:49:03.63#ibcon#about to read 5, iclass 20, count 2 2006.285.12:49:03.63#ibcon#read 5, iclass 20, count 2 2006.285.12:49:03.63#ibcon#about to read 6, iclass 20, count 2 2006.285.12:49:03.63#ibcon#read 6, iclass 20, count 2 2006.285.12:49:03.63#ibcon#end of sib2, iclass 20, count 2 2006.285.12:49:03.63#ibcon#*after write, iclass 20, count 2 2006.285.12:49:03.63#ibcon#*before return 0, iclass 20, count 2 2006.285.12:49:03.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:49:03.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.12:49:03.63#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.12:49:03.63#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:03.63#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:49:03.75#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:49:03.75#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:49:03.75#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:49:03.75#ibcon#first serial, iclass 20, count 0 2006.285.12:49:03.75#ibcon#enter sib2, iclass 20, count 0 2006.285.12:49:03.75#ibcon#flushed, iclass 20, count 0 2006.285.12:49:03.75#ibcon#about to write, iclass 20, count 0 2006.285.12:49:03.75#ibcon#wrote, iclass 20, count 0 2006.285.12:49:03.75#ibcon#about to read 3, iclass 20, count 0 2006.285.12:49:03.77#ibcon#read 3, iclass 20, count 0 2006.285.12:49:03.77#ibcon#about to read 4, iclass 20, count 0 2006.285.12:49:03.77#ibcon#read 4, iclass 20, count 0 2006.285.12:49:03.77#ibcon#about to read 5, iclass 20, count 0 2006.285.12:49:03.77#ibcon#read 5, iclass 20, count 0 2006.285.12:49:03.77#ibcon#about to read 6, iclass 20, count 0 2006.285.12:49:03.77#ibcon#read 6, iclass 20, count 0 2006.285.12:49:03.77#ibcon#end of sib2, iclass 20, count 0 2006.285.12:49:03.77#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:49:03.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:49:03.77#ibcon#[27=USB\r\n] 2006.285.12:49:03.77#ibcon#*before write, iclass 20, count 0 2006.285.12:49:03.77#ibcon#enter sib2, iclass 20, count 0 2006.285.12:49:03.77#ibcon#flushed, iclass 20, count 0 2006.285.12:49:03.77#ibcon#about to write, iclass 20, count 0 2006.285.12:49:03.77#ibcon#wrote, iclass 20, count 0 2006.285.12:49:03.77#ibcon#about to read 3, iclass 20, count 0 2006.285.12:49:03.80#ibcon#read 3, iclass 20, count 0 2006.285.12:49:03.80#ibcon#about to read 4, iclass 20, count 0 2006.285.12:49:03.80#ibcon#read 4, iclass 20, count 0 2006.285.12:49:03.80#ibcon#about to read 5, iclass 20, count 0 2006.285.12:49:03.80#ibcon#read 5, iclass 20, count 0 2006.285.12:49:03.80#ibcon#about to read 6, iclass 20, count 0 2006.285.12:49:03.80#ibcon#read 6, iclass 20, count 0 2006.285.12:49:03.80#ibcon#end of sib2, iclass 20, count 0 2006.285.12:49:03.80#ibcon#*after write, iclass 20, count 0 2006.285.12:49:03.80#ibcon#*before return 0, iclass 20, count 0 2006.285.12:49:03.80#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:49:03.80#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.12:49:03.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:49:03.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:49:03.80$vck44/vblo=8,744.99 2006.285.12:49:03.80#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.12:49:03.80#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.12:49:03.80#ibcon#ireg 17 cls_cnt 0 2006.285.12:49:03.80#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:49:03.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:49:03.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:49:03.80#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:49:03.80#ibcon#first serial, iclass 22, count 0 2006.285.12:49:03.80#ibcon#enter sib2, iclass 22, count 0 2006.285.12:49:03.80#ibcon#flushed, iclass 22, count 0 2006.285.12:49:03.80#ibcon#about to write, iclass 22, count 0 2006.285.12:49:03.80#ibcon#wrote, iclass 22, count 0 2006.285.12:49:03.80#ibcon#about to read 3, iclass 22, count 0 2006.285.12:49:03.82#ibcon#read 3, iclass 22, count 0 2006.285.12:49:03.82#ibcon#about to read 4, iclass 22, count 0 2006.285.12:49:03.82#ibcon#read 4, iclass 22, count 0 2006.285.12:49:03.82#ibcon#about to read 5, iclass 22, count 0 2006.285.12:49:03.82#ibcon#read 5, iclass 22, count 0 2006.285.12:49:03.82#ibcon#about to read 6, iclass 22, count 0 2006.285.12:49:03.82#ibcon#read 6, iclass 22, count 0 2006.285.12:49:03.82#ibcon#end of sib2, iclass 22, count 0 2006.285.12:49:03.82#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:49:03.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:49:03.82#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.12:49:03.82#ibcon#*before write, iclass 22, count 0 2006.285.12:49:03.82#ibcon#enter sib2, iclass 22, count 0 2006.285.12:49:03.82#ibcon#flushed, iclass 22, count 0 2006.285.12:49:03.82#ibcon#about to write, iclass 22, count 0 2006.285.12:49:03.82#ibcon#wrote, iclass 22, count 0 2006.285.12:49:03.82#ibcon#about to read 3, iclass 22, count 0 2006.285.12:49:03.86#ibcon#read 3, iclass 22, count 0 2006.285.12:49:03.86#ibcon#about to read 4, iclass 22, count 0 2006.285.12:49:03.86#ibcon#read 4, iclass 22, count 0 2006.285.12:49:03.86#ibcon#about to read 5, iclass 22, count 0 2006.285.12:49:03.86#ibcon#read 5, iclass 22, count 0 2006.285.12:49:03.86#ibcon#about to read 6, iclass 22, count 0 2006.285.12:49:03.86#ibcon#read 6, iclass 22, count 0 2006.285.12:49:03.86#ibcon#end of sib2, iclass 22, count 0 2006.285.12:49:03.86#ibcon#*after write, iclass 22, count 0 2006.285.12:49:03.86#ibcon#*before return 0, iclass 22, count 0 2006.285.12:49:03.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:49:03.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.12:49:03.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:49:03.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:49:03.86$vck44/vb=8,4 2006.285.12:49:03.86#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.12:49:03.86#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.12:49:03.86#ibcon#ireg 11 cls_cnt 2 2006.285.12:49:03.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:49:03.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:49:03.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:49:03.92#ibcon#enter wrdev, iclass 24, count 2 2006.285.12:49:03.92#ibcon#first serial, iclass 24, count 2 2006.285.12:49:03.92#ibcon#enter sib2, iclass 24, count 2 2006.285.12:49:03.92#ibcon#flushed, iclass 24, count 2 2006.285.12:49:03.92#ibcon#about to write, iclass 24, count 2 2006.285.12:49:03.92#ibcon#wrote, iclass 24, count 2 2006.285.12:49:03.92#ibcon#about to read 3, iclass 24, count 2 2006.285.12:49:03.94#ibcon#read 3, iclass 24, count 2 2006.285.12:49:03.94#ibcon#about to read 4, iclass 24, count 2 2006.285.12:49:03.94#ibcon#read 4, iclass 24, count 2 2006.285.12:49:03.94#ibcon#about to read 5, iclass 24, count 2 2006.285.12:49:03.94#ibcon#read 5, iclass 24, count 2 2006.285.12:49:03.94#ibcon#about to read 6, iclass 24, count 2 2006.285.12:49:03.94#ibcon#read 6, iclass 24, count 2 2006.285.12:49:03.94#ibcon#end of sib2, iclass 24, count 2 2006.285.12:49:03.94#ibcon#*mode == 0, iclass 24, count 2 2006.285.12:49:03.94#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.12:49:03.94#ibcon#[27=AT08-04\r\n] 2006.285.12:49:03.94#ibcon#*before write, iclass 24, count 2 2006.285.12:49:03.94#ibcon#enter sib2, iclass 24, count 2 2006.285.12:49:03.94#ibcon#flushed, iclass 24, count 2 2006.285.12:49:03.94#ibcon#about to write, iclass 24, count 2 2006.285.12:49:03.94#ibcon#wrote, iclass 24, count 2 2006.285.12:49:03.94#ibcon#about to read 3, iclass 24, count 2 2006.285.12:49:03.97#ibcon#read 3, iclass 24, count 2 2006.285.12:49:03.97#ibcon#about to read 4, iclass 24, count 2 2006.285.12:49:03.97#ibcon#read 4, iclass 24, count 2 2006.285.12:49:03.97#ibcon#about to read 5, iclass 24, count 2 2006.285.12:49:03.97#ibcon#read 5, iclass 24, count 2 2006.285.12:49:03.97#ibcon#about to read 6, iclass 24, count 2 2006.285.12:49:03.97#ibcon#read 6, iclass 24, count 2 2006.285.12:49:03.97#ibcon#end of sib2, iclass 24, count 2 2006.285.12:49:03.97#ibcon#*after write, iclass 24, count 2 2006.285.12:49:03.97#ibcon#*before return 0, iclass 24, count 2 2006.285.12:49:03.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:49:03.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.12:49:03.97#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.12:49:03.97#ibcon#ireg 7 cls_cnt 0 2006.285.12:49:03.97#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:49:04.09#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:49:04.09#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:49:04.09#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:49:04.09#ibcon#first serial, iclass 24, count 0 2006.285.12:49:04.09#ibcon#enter sib2, iclass 24, count 0 2006.285.12:49:04.09#ibcon#flushed, iclass 24, count 0 2006.285.12:49:04.09#ibcon#about to write, iclass 24, count 0 2006.285.12:49:04.09#ibcon#wrote, iclass 24, count 0 2006.285.12:49:04.09#ibcon#about to read 3, iclass 24, count 0 2006.285.12:49:04.11#ibcon#read 3, iclass 24, count 0 2006.285.12:49:04.11#ibcon#about to read 4, iclass 24, count 0 2006.285.12:49:04.11#ibcon#read 4, iclass 24, count 0 2006.285.12:49:04.11#ibcon#about to read 5, iclass 24, count 0 2006.285.12:49:04.11#ibcon#read 5, iclass 24, count 0 2006.285.12:49:04.11#ibcon#about to read 6, iclass 24, count 0 2006.285.12:49:04.11#ibcon#read 6, iclass 24, count 0 2006.285.12:49:04.11#ibcon#end of sib2, iclass 24, count 0 2006.285.12:49:04.11#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:49:04.11#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:49:04.11#ibcon#[27=USB\r\n] 2006.285.12:49:04.11#ibcon#*before write, iclass 24, count 0 2006.285.12:49:04.11#ibcon#enter sib2, iclass 24, count 0 2006.285.12:49:04.11#ibcon#flushed, iclass 24, count 0 2006.285.12:49:04.11#ibcon#about to write, iclass 24, count 0 2006.285.12:49:04.11#ibcon#wrote, iclass 24, count 0 2006.285.12:49:04.11#ibcon#about to read 3, iclass 24, count 0 2006.285.12:49:04.14#ibcon#read 3, iclass 24, count 0 2006.285.12:49:04.14#ibcon#about to read 4, iclass 24, count 0 2006.285.12:49:04.14#ibcon#read 4, iclass 24, count 0 2006.285.12:49:04.14#ibcon#about to read 5, iclass 24, count 0 2006.285.12:49:04.14#ibcon#read 5, iclass 24, count 0 2006.285.12:49:04.14#ibcon#about to read 6, iclass 24, count 0 2006.285.12:49:04.14#ibcon#read 6, iclass 24, count 0 2006.285.12:49:04.14#ibcon#end of sib2, iclass 24, count 0 2006.285.12:49:04.14#ibcon#*after write, iclass 24, count 0 2006.285.12:49:04.14#ibcon#*before return 0, iclass 24, count 0 2006.285.12:49:04.14#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:49:04.14#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.12:49:04.14#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:49:04.14#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:49:04.14$vck44/vabw=wide 2006.285.12:49:04.14#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.12:49:04.14#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.12:49:04.14#ibcon#ireg 8 cls_cnt 0 2006.285.12:49:04.14#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:49:04.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:49:04.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:49:04.14#ibcon#enter wrdev, iclass 26, count 0 2006.285.12:49:04.14#ibcon#first serial, iclass 26, count 0 2006.285.12:49:04.14#ibcon#enter sib2, iclass 26, count 0 2006.285.12:49:04.14#ibcon#flushed, iclass 26, count 0 2006.285.12:49:04.14#ibcon#about to write, iclass 26, count 0 2006.285.12:49:04.14#ibcon#wrote, iclass 26, count 0 2006.285.12:49:04.14#ibcon#about to read 3, iclass 26, count 0 2006.285.12:49:04.16#ibcon#read 3, iclass 26, count 0 2006.285.12:49:04.16#ibcon#about to read 4, iclass 26, count 0 2006.285.12:49:04.16#ibcon#read 4, iclass 26, count 0 2006.285.12:49:04.16#ibcon#about to read 5, iclass 26, count 0 2006.285.12:49:04.16#ibcon#read 5, iclass 26, count 0 2006.285.12:49:04.16#ibcon#about to read 6, iclass 26, count 0 2006.285.12:49:04.16#ibcon#read 6, iclass 26, count 0 2006.285.12:49:04.16#ibcon#end of sib2, iclass 26, count 0 2006.285.12:49:04.16#ibcon#*mode == 0, iclass 26, count 0 2006.285.12:49:04.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.12:49:04.16#ibcon#[25=BW32\r\n] 2006.285.12:49:04.16#ibcon#*before write, iclass 26, count 0 2006.285.12:49:04.16#ibcon#enter sib2, iclass 26, count 0 2006.285.12:49:04.16#ibcon#flushed, iclass 26, count 0 2006.285.12:49:04.16#ibcon#about to write, iclass 26, count 0 2006.285.12:49:04.16#ibcon#wrote, iclass 26, count 0 2006.285.12:49:04.16#ibcon#about to read 3, iclass 26, count 0 2006.285.12:49:04.19#ibcon#read 3, iclass 26, count 0 2006.285.12:49:04.19#ibcon#about to read 4, iclass 26, count 0 2006.285.12:49:04.19#ibcon#read 4, iclass 26, count 0 2006.285.12:49:04.19#ibcon#about to read 5, iclass 26, count 0 2006.285.12:49:04.19#ibcon#read 5, iclass 26, count 0 2006.285.12:49:04.19#ibcon#about to read 6, iclass 26, count 0 2006.285.12:49:04.19#ibcon#read 6, iclass 26, count 0 2006.285.12:49:04.19#ibcon#end of sib2, iclass 26, count 0 2006.285.12:49:04.19#ibcon#*after write, iclass 26, count 0 2006.285.12:49:04.19#ibcon#*before return 0, iclass 26, count 0 2006.285.12:49:04.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:49:04.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.12:49:04.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.12:49:04.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.12:49:04.19$vck44/vbbw=wide 2006.285.12:49:04.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.12:49:04.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.12:49:04.19#ibcon#ireg 8 cls_cnt 0 2006.285.12:49:04.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:49:04.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:49:04.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:49:04.26#ibcon#enter wrdev, iclass 28, count 0 2006.285.12:49:04.26#ibcon#first serial, iclass 28, count 0 2006.285.12:49:04.26#ibcon#enter sib2, iclass 28, count 0 2006.285.12:49:04.26#ibcon#flushed, iclass 28, count 0 2006.285.12:49:04.26#ibcon#about to write, iclass 28, count 0 2006.285.12:49:04.26#ibcon#wrote, iclass 28, count 0 2006.285.12:49:04.26#ibcon#about to read 3, iclass 28, count 0 2006.285.12:49:04.28#ibcon#read 3, iclass 28, count 0 2006.285.12:49:04.28#ibcon#about to read 4, iclass 28, count 0 2006.285.12:49:04.28#ibcon#read 4, iclass 28, count 0 2006.285.12:49:04.28#ibcon#about to read 5, iclass 28, count 0 2006.285.12:49:04.28#ibcon#read 5, iclass 28, count 0 2006.285.12:49:04.28#ibcon#about to read 6, iclass 28, count 0 2006.285.12:49:04.28#ibcon#read 6, iclass 28, count 0 2006.285.12:49:04.28#ibcon#end of sib2, iclass 28, count 0 2006.285.12:49:04.28#ibcon#*mode == 0, iclass 28, count 0 2006.285.12:49:04.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.12:49:04.28#ibcon#[27=BW32\r\n] 2006.285.12:49:04.28#ibcon#*before write, iclass 28, count 0 2006.285.12:49:04.28#ibcon#enter sib2, iclass 28, count 0 2006.285.12:49:04.28#ibcon#flushed, iclass 28, count 0 2006.285.12:49:04.28#ibcon#about to write, iclass 28, count 0 2006.285.12:49:04.28#ibcon#wrote, iclass 28, count 0 2006.285.12:49:04.28#ibcon#about to read 3, iclass 28, count 0 2006.285.12:49:04.31#ibcon#read 3, iclass 28, count 0 2006.285.12:49:04.31#ibcon#about to read 4, iclass 28, count 0 2006.285.12:49:04.31#ibcon#read 4, iclass 28, count 0 2006.285.12:49:04.31#ibcon#about to read 5, iclass 28, count 0 2006.285.12:49:04.31#ibcon#read 5, iclass 28, count 0 2006.285.12:49:04.31#ibcon#about to read 6, iclass 28, count 0 2006.285.12:49:04.31#ibcon#read 6, iclass 28, count 0 2006.285.12:49:04.31#ibcon#end of sib2, iclass 28, count 0 2006.285.12:49:04.31#ibcon#*after write, iclass 28, count 0 2006.285.12:49:04.31#ibcon#*before return 0, iclass 28, count 0 2006.285.12:49:04.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:49:04.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:49:04.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.12:49:04.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.12:49:04.31$setupk4/ifdk4 2006.285.12:49:04.31$ifdk4/lo= 2006.285.12:49:04.31$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.12:49:04.31$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.12:49:04.31$ifdk4/patch= 2006.285.12:49:04.31$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.12:49:04.31$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.12:49:04.31$setupk4/!*+20s 2006.285.12:49:06.30#abcon#<5=/04 1.3 3.1 18.95 961015.4\r\n> 2006.285.12:49:06.32#abcon#{5=INTERFACE CLEAR} 2006.285.12:49:06.38#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:49:16.47#abcon#<5=/04 1.3 3.1 18.95 961015.4\r\n> 2006.285.12:49:16.49#abcon#{5=INTERFACE CLEAR} 2006.285.12:49:16.55#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:49:18.10$setupk4/"tpicd 2006.285.12:49:18.10$setupk4/echo=off 2006.285.12:49:18.10$setupk4/xlog=off 2006.285.12:49:18.10:!2006.285.12:51:45 2006.285.12:49:50.14#trakl#Source acquired 2006.285.12:49:50.14#flagr#flagr/antenna,acquired 2006.285.12:51:45.00:preob 2006.285.12:51:45.14/onsource/TRACKING 2006.285.12:51:45.14:!2006.285.12:51:55 2006.285.12:51:55.00:"tape 2006.285.12:51:55.00:"st=record 2006.285.12:51:55.00:data_valid=on 2006.285.12:51:55.00:midob 2006.285.12:51:56.14/onsource/TRACKING 2006.285.12:51:56.14/wx/18.96,1015.5,96 2006.285.12:51:56.36/cable/+6.4953E-03 2006.285.12:51:57.45/va/01,07,usb,yes,38,41 2006.285.12:51:57.45/va/02,06,usb,yes,38,39 2006.285.12:51:57.45/va/03,07,usb,yes,38,40 2006.285.12:51:57.45/va/04,06,usb,yes,39,41 2006.285.12:51:57.45/va/05,03,usb,yes,39,39 2006.285.12:51:57.45/va/06,04,usb,yes,35,35 2006.285.12:51:57.45/va/07,04,usb,yes,36,36 2006.285.12:51:57.45/va/08,03,usb,yes,37,44 2006.285.12:51:57.68/valo/01,524.99,yes,locked 2006.285.12:51:57.68/valo/02,534.99,yes,locked 2006.285.12:51:57.68/valo/03,564.99,yes,locked 2006.285.12:51:57.68/valo/04,624.99,yes,locked 2006.285.12:51:57.68/valo/05,734.99,yes,locked 2006.285.12:51:57.68/valo/06,814.99,yes,locked 2006.285.12:51:57.68/valo/07,864.99,yes,locked 2006.285.12:51:57.68/valo/08,884.99,yes,locked 2006.285.12:51:58.77/vb/01,04,usb,yes,33,31 2006.285.12:51:58.77/vb/02,05,usb,yes,32,31 2006.285.12:51:58.77/vb/03,04,usb,yes,33,36 2006.285.12:51:58.77/vb/04,05,usb,yes,33,32 2006.285.12:51:58.77/vb/05,04,usb,yes,29,32 2006.285.12:51:58.77/vb/06,03,usb,yes,42,38 2006.285.12:51:58.77/vb/07,04,usb,yes,34,34 2006.285.12:51:58.77/vb/08,04,usb,yes,31,35 2006.285.12:51:59.01/vblo/01,629.99,yes,locked 2006.285.12:51:59.01/vblo/02,634.99,yes,locked 2006.285.12:51:59.01/vblo/03,649.99,yes,locked 2006.285.12:51:59.01/vblo/04,679.99,yes,locked 2006.285.12:51:59.01/vblo/05,709.99,yes,locked 2006.285.12:51:59.01/vblo/06,719.99,yes,locked 2006.285.12:51:59.01/vblo/07,734.99,yes,locked 2006.285.12:51:59.01/vblo/08,744.99,yes,locked 2006.285.12:51:59.16/vabw/8 2006.285.12:51:59.31/vbbw/8 2006.285.12:51:59.40/xfe/off,on,12.0 2006.285.12:51:59.78/ifatt/23,28,28,28 2006.285.12:52:00.08/fmout-gps/S +2.69E-07 2006.285.12:52:00.10:!2006.285.12:54:45 2006.285.12:54:45.00:data_valid=off 2006.285.12:54:45.00:"et 2006.285.12:54:45.00:!+3s 2006.285.12:54:48.01:"tape 2006.285.12:54:48.01:postob 2006.285.12:54:48.12/cable/+6.4958E-03 2006.285.12:54:48.12/wx/18.96,1015.5,96 2006.285.12:54:49.08/fmout-gps/S +2.67E-07 2006.285.12:54:49.08:scan_name=285-1255,jd0610,60 2006.285.12:54:49.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.285.12:54:50.13#flagr#flagr/antenna,new-source 2006.285.12:54:50.13:checkk5 2006.285.12:54:50.60/chk_autoobs//k5ts1/ autoobs is running! 2006.285.12:54:50.99/chk_autoobs//k5ts2/ autoobs is running! 2006.285.12:54:51.59/chk_autoobs//k5ts3/ autoobs is running! 2006.285.12:54:51.98/chk_autoobs//k5ts4/ autoobs is running! 2006.285.12:54:52.45/chk_obsdata//k5ts1/T2851251??a.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.12:54:52.84/chk_obsdata//k5ts2/T2851251??b.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.12:54:53.32/chk_obsdata//k5ts3/T2851251??c.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.12:54:53.73/chk_obsdata//k5ts4/T2851251??d.dat file size is correct (nominal:680MB, actual:680MB). 2006.285.12:54:54.59/k5log//k5ts1_log_newline 2006.285.12:54:55.38/k5log//k5ts2_log_newline 2006.285.12:54:56.09/k5log//k5ts3_log_newline 2006.285.12:54:56.80/k5log//k5ts4_log_newline 2006.285.12:54:56.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.12:54:56.82:setupk4=1 2006.285.12:54:56.82$setupk4/echo=on 2006.285.12:54:56.82$setupk4/pcalon 2006.285.12:54:56.82$pcalon/"no phase cal control is implemented here 2006.285.12:54:56.82$setupk4/"tpicd=stop 2006.285.12:54:56.82$setupk4/"rec=synch_on 2006.285.12:54:56.82$setupk4/"rec_mode=128 2006.285.12:54:56.82$setupk4/!* 2006.285.12:54:56.82$setupk4/recpk4 2006.285.12:54:56.82$recpk4/recpatch= 2006.285.12:54:56.83$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.12:54:56.83$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.12:54:56.83$setupk4/vck44 2006.285.12:54:56.83$vck44/valo=1,524.99 2006.285.12:54:56.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.12:54:56.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.12:54:56.83#ibcon#ireg 17 cls_cnt 0 2006.285.12:54:56.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:54:56.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:54:56.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:54:56.83#ibcon#enter wrdev, iclass 29, count 0 2006.285.12:54:56.83#ibcon#first serial, iclass 29, count 0 2006.285.12:54:56.83#ibcon#enter sib2, iclass 29, count 0 2006.285.12:54:56.83#ibcon#flushed, iclass 29, count 0 2006.285.12:54:56.83#ibcon#about to write, iclass 29, count 0 2006.285.12:54:56.83#ibcon#wrote, iclass 29, count 0 2006.285.12:54:56.83#ibcon#about to read 3, iclass 29, count 0 2006.285.12:54:56.85#ibcon#read 3, iclass 29, count 0 2006.285.12:54:56.85#ibcon#about to read 4, iclass 29, count 0 2006.285.12:54:56.85#ibcon#read 4, iclass 29, count 0 2006.285.12:54:56.85#ibcon#about to read 5, iclass 29, count 0 2006.285.12:54:56.85#ibcon#read 5, iclass 29, count 0 2006.285.12:54:56.85#ibcon#about to read 6, iclass 29, count 0 2006.285.12:54:56.85#ibcon#read 6, iclass 29, count 0 2006.285.12:54:56.85#ibcon#end of sib2, iclass 29, count 0 2006.285.12:54:56.85#ibcon#*mode == 0, iclass 29, count 0 2006.285.12:54:56.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.12:54:56.85#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.12:54:56.85#ibcon#*before write, iclass 29, count 0 2006.285.12:54:56.85#ibcon#enter sib2, iclass 29, count 0 2006.285.12:54:56.85#ibcon#flushed, iclass 29, count 0 2006.285.12:54:56.85#ibcon#about to write, iclass 29, count 0 2006.285.12:54:56.85#ibcon#wrote, iclass 29, count 0 2006.285.12:54:56.85#ibcon#about to read 3, iclass 29, count 0 2006.285.12:54:56.90#ibcon#read 3, iclass 29, count 0 2006.285.12:54:56.90#ibcon#about to read 4, iclass 29, count 0 2006.285.12:54:56.90#ibcon#read 4, iclass 29, count 0 2006.285.12:54:56.90#ibcon#about to read 5, iclass 29, count 0 2006.285.12:54:56.90#ibcon#read 5, iclass 29, count 0 2006.285.12:54:56.90#ibcon#about to read 6, iclass 29, count 0 2006.285.12:54:56.90#ibcon#read 6, iclass 29, count 0 2006.285.12:54:56.90#ibcon#end of sib2, iclass 29, count 0 2006.285.12:54:56.90#ibcon#*after write, iclass 29, count 0 2006.285.12:54:56.90#ibcon#*before return 0, iclass 29, count 0 2006.285.12:54:56.90#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:54:56.90#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:54:56.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.12:54:56.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.12:54:56.90$vck44/va=1,7 2006.285.12:54:56.90#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.12:54:56.90#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.12:54:56.90#ibcon#ireg 11 cls_cnt 2 2006.285.12:54:56.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:54:56.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:54:56.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:54:56.90#ibcon#enter wrdev, iclass 31, count 2 2006.285.12:54:56.90#ibcon#first serial, iclass 31, count 2 2006.285.12:54:56.90#ibcon#enter sib2, iclass 31, count 2 2006.285.12:54:56.90#ibcon#flushed, iclass 31, count 2 2006.285.12:54:56.90#ibcon#about to write, iclass 31, count 2 2006.285.12:54:56.90#ibcon#wrote, iclass 31, count 2 2006.285.12:54:56.90#ibcon#about to read 3, iclass 31, count 2 2006.285.12:54:56.92#ibcon#read 3, iclass 31, count 2 2006.285.12:54:56.92#ibcon#about to read 4, iclass 31, count 2 2006.285.12:54:56.92#ibcon#read 4, iclass 31, count 2 2006.285.12:54:56.92#ibcon#about to read 5, iclass 31, count 2 2006.285.12:54:56.92#ibcon#read 5, iclass 31, count 2 2006.285.12:54:56.92#ibcon#about to read 6, iclass 31, count 2 2006.285.12:54:56.92#ibcon#read 6, iclass 31, count 2 2006.285.12:54:56.92#ibcon#end of sib2, iclass 31, count 2 2006.285.12:54:56.92#ibcon#*mode == 0, iclass 31, count 2 2006.285.12:54:56.92#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.12:54:56.92#ibcon#[25=AT01-07\r\n] 2006.285.12:54:56.92#ibcon#*before write, iclass 31, count 2 2006.285.12:54:56.92#ibcon#enter sib2, iclass 31, count 2 2006.285.12:54:56.92#ibcon#flushed, iclass 31, count 2 2006.285.12:54:56.92#ibcon#about to write, iclass 31, count 2 2006.285.12:54:56.92#ibcon#wrote, iclass 31, count 2 2006.285.12:54:56.92#ibcon#about to read 3, iclass 31, count 2 2006.285.12:54:56.95#ibcon#read 3, iclass 31, count 2 2006.285.12:54:56.95#ibcon#about to read 4, iclass 31, count 2 2006.285.12:54:56.95#ibcon#read 4, iclass 31, count 2 2006.285.12:54:56.95#ibcon#about to read 5, iclass 31, count 2 2006.285.12:54:56.95#ibcon#read 5, iclass 31, count 2 2006.285.12:54:56.95#ibcon#about to read 6, iclass 31, count 2 2006.285.12:54:56.95#ibcon#read 6, iclass 31, count 2 2006.285.12:54:56.95#ibcon#end of sib2, iclass 31, count 2 2006.285.12:54:56.95#ibcon#*after write, iclass 31, count 2 2006.285.12:54:56.95#ibcon#*before return 0, iclass 31, count 2 2006.285.12:54:56.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:54:56.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:54:56.95#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.12:54:56.95#ibcon#ireg 7 cls_cnt 0 2006.285.12:54:56.95#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:54:57.07#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:54:57.07#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:54:57.07#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:54:57.07#ibcon#first serial, iclass 31, count 0 2006.285.12:54:57.07#ibcon#enter sib2, iclass 31, count 0 2006.285.12:54:57.07#ibcon#flushed, iclass 31, count 0 2006.285.12:54:57.07#ibcon#about to write, iclass 31, count 0 2006.285.12:54:57.07#ibcon#wrote, iclass 31, count 0 2006.285.12:54:57.07#ibcon#about to read 3, iclass 31, count 0 2006.285.12:54:57.09#ibcon#read 3, iclass 31, count 0 2006.285.12:54:57.09#ibcon#about to read 4, iclass 31, count 0 2006.285.12:54:57.09#ibcon#read 4, iclass 31, count 0 2006.285.12:54:57.09#ibcon#about to read 5, iclass 31, count 0 2006.285.12:54:57.09#ibcon#read 5, iclass 31, count 0 2006.285.12:54:57.09#ibcon#about to read 6, iclass 31, count 0 2006.285.12:54:57.09#ibcon#read 6, iclass 31, count 0 2006.285.12:54:57.09#ibcon#end of sib2, iclass 31, count 0 2006.285.12:54:57.09#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:54:57.09#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:54:57.09#ibcon#[25=USB\r\n] 2006.285.12:54:57.09#ibcon#*before write, iclass 31, count 0 2006.285.12:54:57.09#ibcon#enter sib2, iclass 31, count 0 2006.285.12:54:57.09#ibcon#flushed, iclass 31, count 0 2006.285.12:54:57.09#ibcon#about to write, iclass 31, count 0 2006.285.12:54:57.09#ibcon#wrote, iclass 31, count 0 2006.285.12:54:57.09#ibcon#about to read 3, iclass 31, count 0 2006.285.12:54:57.12#ibcon#read 3, iclass 31, count 0 2006.285.12:54:57.12#ibcon#about to read 4, iclass 31, count 0 2006.285.12:54:57.12#ibcon#read 4, iclass 31, count 0 2006.285.12:54:57.12#ibcon#about to read 5, iclass 31, count 0 2006.285.12:54:57.12#ibcon#read 5, iclass 31, count 0 2006.285.12:54:57.12#ibcon#about to read 6, iclass 31, count 0 2006.285.12:54:57.12#ibcon#read 6, iclass 31, count 0 2006.285.12:54:57.12#ibcon#end of sib2, iclass 31, count 0 2006.285.12:54:57.12#ibcon#*after write, iclass 31, count 0 2006.285.12:54:57.12#ibcon#*before return 0, iclass 31, count 0 2006.285.12:54:57.12#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:54:57.12#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:54:57.12#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:54:57.12#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:54:57.12$vck44/valo=2,534.99 2006.285.12:54:57.12#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.12:54:57.12#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.12:54:57.12#ibcon#ireg 17 cls_cnt 0 2006.285.12:54:57.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:54:57.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:54:57.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:54:57.12#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:54:57.12#ibcon#first serial, iclass 33, count 0 2006.285.12:54:57.12#ibcon#enter sib2, iclass 33, count 0 2006.285.12:54:57.12#ibcon#flushed, iclass 33, count 0 2006.285.12:54:57.12#ibcon#about to write, iclass 33, count 0 2006.285.12:54:57.12#ibcon#wrote, iclass 33, count 0 2006.285.12:54:57.12#ibcon#about to read 3, iclass 33, count 0 2006.285.12:54:57.55#ibcon#read 3, iclass 33, count 0 2006.285.12:54:57.55#ibcon#about to read 4, iclass 33, count 0 2006.285.12:54:57.55#ibcon#read 4, iclass 33, count 0 2006.285.12:54:57.55#ibcon#about to read 5, iclass 33, count 0 2006.285.12:54:57.55#ibcon#read 5, iclass 33, count 0 2006.285.12:54:57.55#ibcon#about to read 6, iclass 33, count 0 2006.285.12:54:57.55#ibcon#read 6, iclass 33, count 0 2006.285.12:54:57.55#ibcon#end of sib2, iclass 33, count 0 2006.285.12:54:57.55#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:54:57.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:54:57.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.12:54:57.55#ibcon#*before write, iclass 33, count 0 2006.285.12:54:57.55#ibcon#enter sib2, iclass 33, count 0 2006.285.12:54:57.55#ibcon#flushed, iclass 33, count 0 2006.285.12:54:57.55#ibcon#about to write, iclass 33, count 0 2006.285.12:54:57.55#ibcon#wrote, iclass 33, count 0 2006.285.12:54:57.55#ibcon#about to read 3, iclass 33, count 0 2006.285.12:54:57.60#ibcon#read 3, iclass 33, count 0 2006.285.12:54:57.60#ibcon#about to read 4, iclass 33, count 0 2006.285.12:54:57.60#ibcon#read 4, iclass 33, count 0 2006.285.12:54:57.60#ibcon#about to read 5, iclass 33, count 0 2006.285.12:54:57.60#ibcon#read 5, iclass 33, count 0 2006.285.12:54:57.60#ibcon#about to read 6, iclass 33, count 0 2006.285.12:54:57.60#ibcon#read 6, iclass 33, count 0 2006.285.12:54:57.60#ibcon#end of sib2, iclass 33, count 0 2006.285.12:54:57.60#ibcon#*after write, iclass 33, count 0 2006.285.12:54:57.60#ibcon#*before return 0, iclass 33, count 0 2006.285.12:54:57.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:54:57.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:54:57.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:54:57.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:54:57.60$vck44/va=2,6 2006.285.12:54:57.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.12:54:57.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.12:54:57.60#ibcon#ireg 11 cls_cnt 2 2006.285.12:54:57.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:54:57.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:54:57.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:54:57.60#ibcon#enter wrdev, iclass 35, count 2 2006.285.12:54:57.60#ibcon#first serial, iclass 35, count 2 2006.285.12:54:57.60#ibcon#enter sib2, iclass 35, count 2 2006.285.12:54:57.60#ibcon#flushed, iclass 35, count 2 2006.285.12:54:57.60#ibcon#about to write, iclass 35, count 2 2006.285.12:54:57.60#ibcon#wrote, iclass 35, count 2 2006.285.12:54:57.60#ibcon#about to read 3, iclass 35, count 2 2006.285.12:54:57.62#ibcon#read 3, iclass 35, count 2 2006.285.12:54:57.62#ibcon#about to read 4, iclass 35, count 2 2006.285.12:54:57.62#ibcon#read 4, iclass 35, count 2 2006.285.12:54:57.62#ibcon#about to read 5, iclass 35, count 2 2006.285.12:54:57.62#ibcon#read 5, iclass 35, count 2 2006.285.12:54:57.62#ibcon#about to read 6, iclass 35, count 2 2006.285.12:54:57.62#ibcon#read 6, iclass 35, count 2 2006.285.12:54:57.62#ibcon#end of sib2, iclass 35, count 2 2006.285.12:54:57.62#ibcon#*mode == 0, iclass 35, count 2 2006.285.12:54:57.62#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.12:54:57.62#ibcon#[25=AT02-06\r\n] 2006.285.12:54:57.62#ibcon#*before write, iclass 35, count 2 2006.285.12:54:57.62#ibcon#enter sib2, iclass 35, count 2 2006.285.12:54:57.62#ibcon#flushed, iclass 35, count 2 2006.285.12:54:57.62#ibcon#about to write, iclass 35, count 2 2006.285.12:54:57.62#ibcon#wrote, iclass 35, count 2 2006.285.12:54:57.62#ibcon#about to read 3, iclass 35, count 2 2006.285.12:54:57.65#ibcon#read 3, iclass 35, count 2 2006.285.12:54:57.65#ibcon#about to read 4, iclass 35, count 2 2006.285.12:54:57.65#ibcon#read 4, iclass 35, count 2 2006.285.12:54:57.65#ibcon#about to read 5, iclass 35, count 2 2006.285.12:54:57.65#ibcon#read 5, iclass 35, count 2 2006.285.12:54:57.65#ibcon#about to read 6, iclass 35, count 2 2006.285.12:54:57.65#ibcon#read 6, iclass 35, count 2 2006.285.12:54:57.65#ibcon#end of sib2, iclass 35, count 2 2006.285.12:54:57.65#ibcon#*after write, iclass 35, count 2 2006.285.12:54:57.65#ibcon#*before return 0, iclass 35, count 2 2006.285.12:54:57.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:54:57.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:54:57.65#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.12:54:57.65#ibcon#ireg 7 cls_cnt 0 2006.285.12:54:57.65#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:54:57.77#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:54:57.77#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:54:57.77#ibcon#enter wrdev, iclass 35, count 0 2006.285.12:54:57.77#ibcon#first serial, iclass 35, count 0 2006.285.12:54:57.77#ibcon#enter sib2, iclass 35, count 0 2006.285.12:54:57.77#ibcon#flushed, iclass 35, count 0 2006.285.12:54:57.77#ibcon#about to write, iclass 35, count 0 2006.285.12:54:57.77#ibcon#wrote, iclass 35, count 0 2006.285.12:54:57.77#ibcon#about to read 3, iclass 35, count 0 2006.285.12:54:57.79#ibcon#read 3, iclass 35, count 0 2006.285.12:54:57.79#ibcon#about to read 4, iclass 35, count 0 2006.285.12:54:57.79#ibcon#read 4, iclass 35, count 0 2006.285.12:54:57.79#ibcon#about to read 5, iclass 35, count 0 2006.285.12:54:57.79#ibcon#read 5, iclass 35, count 0 2006.285.12:54:57.79#ibcon#about to read 6, iclass 35, count 0 2006.285.12:54:57.79#ibcon#read 6, iclass 35, count 0 2006.285.12:54:57.79#ibcon#end of sib2, iclass 35, count 0 2006.285.12:54:57.79#ibcon#*mode == 0, iclass 35, count 0 2006.285.12:54:57.79#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.12:54:57.79#ibcon#[25=USB\r\n] 2006.285.12:54:57.79#ibcon#*before write, iclass 35, count 0 2006.285.12:54:57.79#ibcon#enter sib2, iclass 35, count 0 2006.285.12:54:57.79#ibcon#flushed, iclass 35, count 0 2006.285.12:54:57.79#ibcon#about to write, iclass 35, count 0 2006.285.12:54:57.79#ibcon#wrote, iclass 35, count 0 2006.285.12:54:57.79#ibcon#about to read 3, iclass 35, count 0 2006.285.12:54:57.82#ibcon#read 3, iclass 35, count 0 2006.285.12:54:57.82#ibcon#about to read 4, iclass 35, count 0 2006.285.12:54:57.82#ibcon#read 4, iclass 35, count 0 2006.285.12:54:57.82#ibcon#about to read 5, iclass 35, count 0 2006.285.12:54:57.82#ibcon#read 5, iclass 35, count 0 2006.285.12:54:57.82#ibcon#about to read 6, iclass 35, count 0 2006.285.12:54:57.82#ibcon#read 6, iclass 35, count 0 2006.285.12:54:57.82#ibcon#end of sib2, iclass 35, count 0 2006.285.12:54:57.82#ibcon#*after write, iclass 35, count 0 2006.285.12:54:57.82#ibcon#*before return 0, iclass 35, count 0 2006.285.12:54:57.82#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:54:57.82#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:54:57.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.12:54:57.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.12:54:57.82$vck44/valo=3,564.99 2006.285.12:54:57.82#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.12:54:57.82#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.12:54:57.82#ibcon#ireg 17 cls_cnt 0 2006.285.12:54:57.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:54:57.82#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:54:57.82#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:54:57.82#ibcon#enter wrdev, iclass 37, count 0 2006.285.12:54:57.82#ibcon#first serial, iclass 37, count 0 2006.285.12:54:57.82#ibcon#enter sib2, iclass 37, count 0 2006.285.12:54:57.82#ibcon#flushed, iclass 37, count 0 2006.285.12:54:57.82#ibcon#about to write, iclass 37, count 0 2006.285.12:54:57.82#ibcon#wrote, iclass 37, count 0 2006.285.12:54:57.82#ibcon#about to read 3, iclass 37, count 0 2006.285.12:54:57.91#ibcon#read 3, iclass 37, count 0 2006.285.12:54:57.91#ibcon#about to read 4, iclass 37, count 0 2006.285.12:54:57.91#ibcon#read 4, iclass 37, count 0 2006.285.12:54:57.91#ibcon#about to read 5, iclass 37, count 0 2006.285.12:54:57.91#ibcon#read 5, iclass 37, count 0 2006.285.12:54:57.91#ibcon#about to read 6, iclass 37, count 0 2006.285.12:54:57.91#ibcon#read 6, iclass 37, count 0 2006.285.12:54:57.91#ibcon#end of sib2, iclass 37, count 0 2006.285.12:54:57.91#ibcon#*mode == 0, iclass 37, count 0 2006.285.12:54:57.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.12:54:57.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.12:54:57.91#ibcon#*before write, iclass 37, count 0 2006.285.12:54:57.91#ibcon#enter sib2, iclass 37, count 0 2006.285.12:54:57.91#ibcon#flushed, iclass 37, count 0 2006.285.12:54:57.91#ibcon#about to write, iclass 37, count 0 2006.285.12:54:57.91#ibcon#wrote, iclass 37, count 0 2006.285.12:54:57.91#ibcon#about to read 3, iclass 37, count 0 2006.285.12:54:57.95#ibcon#read 3, iclass 37, count 0 2006.285.12:54:57.95#ibcon#about to read 4, iclass 37, count 0 2006.285.12:54:57.95#ibcon#read 4, iclass 37, count 0 2006.285.12:54:57.95#ibcon#about to read 5, iclass 37, count 0 2006.285.12:54:57.95#ibcon#read 5, iclass 37, count 0 2006.285.12:54:57.95#ibcon#about to read 6, iclass 37, count 0 2006.285.12:54:57.95#ibcon#read 6, iclass 37, count 0 2006.285.12:54:57.95#ibcon#end of sib2, iclass 37, count 0 2006.285.12:54:57.95#ibcon#*after write, iclass 37, count 0 2006.285.12:54:57.95#ibcon#*before return 0, iclass 37, count 0 2006.285.12:54:57.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:54:57.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:54:57.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.12:54:57.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.12:54:57.95$vck44/va=3,7 2006.285.12:54:57.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.12:54:57.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.12:54:57.95#ibcon#ireg 11 cls_cnt 2 2006.285.12:54:57.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:54:57.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:54:57.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:54:57.95#ibcon#enter wrdev, iclass 39, count 2 2006.285.12:54:57.95#ibcon#first serial, iclass 39, count 2 2006.285.12:54:57.95#ibcon#enter sib2, iclass 39, count 2 2006.285.12:54:57.95#ibcon#flushed, iclass 39, count 2 2006.285.12:54:57.95#ibcon#about to write, iclass 39, count 2 2006.285.12:54:57.95#ibcon#wrote, iclass 39, count 2 2006.285.12:54:57.95#ibcon#about to read 3, iclass 39, count 2 2006.285.12:54:57.97#ibcon#read 3, iclass 39, count 2 2006.285.12:54:57.97#ibcon#about to read 4, iclass 39, count 2 2006.285.12:54:57.97#ibcon#read 4, iclass 39, count 2 2006.285.12:54:57.97#ibcon#about to read 5, iclass 39, count 2 2006.285.12:54:57.97#ibcon#read 5, iclass 39, count 2 2006.285.12:54:57.97#ibcon#about to read 6, iclass 39, count 2 2006.285.12:54:57.97#ibcon#read 6, iclass 39, count 2 2006.285.12:54:57.97#ibcon#end of sib2, iclass 39, count 2 2006.285.12:54:57.97#ibcon#*mode == 0, iclass 39, count 2 2006.285.12:54:57.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.12:54:57.97#ibcon#[25=AT03-07\r\n] 2006.285.12:54:57.97#ibcon#*before write, iclass 39, count 2 2006.285.12:54:57.97#ibcon#enter sib2, iclass 39, count 2 2006.285.12:54:57.97#ibcon#flushed, iclass 39, count 2 2006.285.12:54:57.97#ibcon#about to write, iclass 39, count 2 2006.285.12:54:57.97#ibcon#wrote, iclass 39, count 2 2006.285.12:54:57.97#ibcon#about to read 3, iclass 39, count 2 2006.285.12:54:58.00#ibcon#read 3, iclass 39, count 2 2006.285.12:54:58.00#ibcon#about to read 4, iclass 39, count 2 2006.285.12:54:58.00#ibcon#read 4, iclass 39, count 2 2006.285.12:54:58.00#ibcon#about to read 5, iclass 39, count 2 2006.285.12:54:58.00#ibcon#read 5, iclass 39, count 2 2006.285.12:54:58.00#ibcon#about to read 6, iclass 39, count 2 2006.285.12:54:58.00#ibcon#read 6, iclass 39, count 2 2006.285.12:54:58.00#ibcon#end of sib2, iclass 39, count 2 2006.285.12:54:58.00#ibcon#*after write, iclass 39, count 2 2006.285.12:54:58.00#ibcon#*before return 0, iclass 39, count 2 2006.285.12:54:58.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:54:58.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:54:58.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.12:54:58.00#ibcon#ireg 7 cls_cnt 0 2006.285.12:54:58.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:54:58.12#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:54:58.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:54:58.12#ibcon#enter wrdev, iclass 39, count 0 2006.285.12:54:58.12#ibcon#first serial, iclass 39, count 0 2006.285.12:54:58.12#ibcon#enter sib2, iclass 39, count 0 2006.285.12:54:58.12#ibcon#flushed, iclass 39, count 0 2006.285.12:54:58.12#ibcon#about to write, iclass 39, count 0 2006.285.12:54:58.12#ibcon#wrote, iclass 39, count 0 2006.285.12:54:58.12#ibcon#about to read 3, iclass 39, count 0 2006.285.12:54:58.14#ibcon#read 3, iclass 39, count 0 2006.285.12:54:58.14#ibcon#about to read 4, iclass 39, count 0 2006.285.12:54:58.14#ibcon#read 4, iclass 39, count 0 2006.285.12:54:58.14#ibcon#about to read 5, iclass 39, count 0 2006.285.12:54:58.14#ibcon#read 5, iclass 39, count 0 2006.285.12:54:58.14#ibcon#about to read 6, iclass 39, count 0 2006.285.12:54:58.14#ibcon#read 6, iclass 39, count 0 2006.285.12:54:58.14#ibcon#end of sib2, iclass 39, count 0 2006.285.12:54:58.14#ibcon#*mode == 0, iclass 39, count 0 2006.285.12:54:58.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.12:54:58.14#ibcon#[25=USB\r\n] 2006.285.12:54:58.14#ibcon#*before write, iclass 39, count 0 2006.285.12:54:58.14#ibcon#enter sib2, iclass 39, count 0 2006.285.12:54:58.14#ibcon#flushed, iclass 39, count 0 2006.285.12:54:58.14#ibcon#about to write, iclass 39, count 0 2006.285.12:54:58.14#ibcon#wrote, iclass 39, count 0 2006.285.12:54:58.14#ibcon#about to read 3, iclass 39, count 0 2006.285.12:54:58.17#ibcon#read 3, iclass 39, count 0 2006.285.12:54:58.17#ibcon#about to read 4, iclass 39, count 0 2006.285.12:54:58.17#ibcon#read 4, iclass 39, count 0 2006.285.12:54:58.17#ibcon#about to read 5, iclass 39, count 0 2006.285.12:54:58.17#ibcon#read 5, iclass 39, count 0 2006.285.12:54:58.17#ibcon#about to read 6, iclass 39, count 0 2006.285.12:54:58.17#ibcon#read 6, iclass 39, count 0 2006.285.12:54:58.17#ibcon#end of sib2, iclass 39, count 0 2006.285.12:54:58.17#ibcon#*after write, iclass 39, count 0 2006.285.12:54:58.17#ibcon#*before return 0, iclass 39, count 0 2006.285.12:54:58.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:54:58.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:54:58.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.12:54:58.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.12:54:58.17$vck44/valo=4,624.99 2006.285.12:54:58.17#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.12:54:58.17#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.12:54:58.17#ibcon#ireg 17 cls_cnt 0 2006.285.12:54:58.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:54:58.17#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:54:58.17#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:54:58.17#ibcon#enter wrdev, iclass 3, count 0 2006.285.12:54:58.17#ibcon#first serial, iclass 3, count 0 2006.285.12:54:58.17#ibcon#enter sib2, iclass 3, count 0 2006.285.12:54:58.17#ibcon#flushed, iclass 3, count 0 2006.285.12:54:58.17#ibcon#about to write, iclass 3, count 0 2006.285.12:54:58.17#ibcon#wrote, iclass 3, count 0 2006.285.12:54:58.17#ibcon#about to read 3, iclass 3, count 0 2006.285.12:54:58.19#ibcon#read 3, iclass 3, count 0 2006.285.12:54:58.24#ibcon#about to read 4, iclass 3, count 0 2006.285.12:54:58.24#ibcon#read 4, iclass 3, count 0 2006.285.12:54:58.24#ibcon#about to read 5, iclass 3, count 0 2006.285.12:54:58.24#ibcon#read 5, iclass 3, count 0 2006.285.12:54:58.24#ibcon#about to read 6, iclass 3, count 0 2006.285.12:54:58.24#ibcon#read 6, iclass 3, count 0 2006.285.12:54:58.24#ibcon#end of sib2, iclass 3, count 0 2006.285.12:54:58.24#ibcon#*mode == 0, iclass 3, count 0 2006.285.12:54:58.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.12:54:58.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.12:54:58.24#ibcon#*before write, iclass 3, count 0 2006.285.12:54:58.24#ibcon#enter sib2, iclass 3, count 0 2006.285.12:54:58.24#ibcon#flushed, iclass 3, count 0 2006.285.12:54:58.24#ibcon#about to write, iclass 3, count 0 2006.285.12:54:58.24#ibcon#wrote, iclass 3, count 0 2006.285.12:54:58.24#ibcon#about to read 3, iclass 3, count 0 2006.285.12:54:58.29#ibcon#read 3, iclass 3, count 0 2006.285.12:54:58.29#ibcon#about to read 4, iclass 3, count 0 2006.285.12:54:58.29#ibcon#read 4, iclass 3, count 0 2006.285.12:54:58.29#ibcon#about to read 5, iclass 3, count 0 2006.285.12:54:58.29#ibcon#read 5, iclass 3, count 0 2006.285.12:54:58.29#ibcon#about to read 6, iclass 3, count 0 2006.285.12:54:58.29#ibcon#read 6, iclass 3, count 0 2006.285.12:54:58.29#ibcon#end of sib2, iclass 3, count 0 2006.285.12:54:58.29#ibcon#*after write, iclass 3, count 0 2006.285.12:54:58.29#ibcon#*before return 0, iclass 3, count 0 2006.285.12:54:58.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:54:58.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:54:58.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.12:54:58.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.12:54:58.29$vck44/va=4,6 2006.285.12:54:58.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.12:54:58.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.12:54:58.29#ibcon#ireg 11 cls_cnt 2 2006.285.12:54:58.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:54:58.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:54:58.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:54:58.29#ibcon#enter wrdev, iclass 5, count 2 2006.285.12:54:58.29#ibcon#first serial, iclass 5, count 2 2006.285.12:54:58.29#ibcon#enter sib2, iclass 5, count 2 2006.285.12:54:58.29#ibcon#flushed, iclass 5, count 2 2006.285.12:54:58.29#ibcon#about to write, iclass 5, count 2 2006.285.12:54:58.29#ibcon#wrote, iclass 5, count 2 2006.285.12:54:58.29#ibcon#about to read 3, iclass 5, count 2 2006.285.12:54:58.31#ibcon#read 3, iclass 5, count 2 2006.285.12:54:58.31#ibcon#about to read 4, iclass 5, count 2 2006.285.12:54:58.31#ibcon#read 4, iclass 5, count 2 2006.285.12:54:58.31#ibcon#about to read 5, iclass 5, count 2 2006.285.12:54:58.31#ibcon#read 5, iclass 5, count 2 2006.285.12:54:58.31#ibcon#about to read 6, iclass 5, count 2 2006.285.12:54:58.31#ibcon#read 6, iclass 5, count 2 2006.285.12:54:58.31#ibcon#end of sib2, iclass 5, count 2 2006.285.12:54:58.31#ibcon#*mode == 0, iclass 5, count 2 2006.285.12:54:58.31#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.12:54:58.31#ibcon#[25=AT04-06\r\n] 2006.285.12:54:58.31#ibcon#*before write, iclass 5, count 2 2006.285.12:54:58.31#ibcon#enter sib2, iclass 5, count 2 2006.285.12:54:58.31#ibcon#flushed, iclass 5, count 2 2006.285.12:54:58.31#ibcon#about to write, iclass 5, count 2 2006.285.12:54:58.31#ibcon#wrote, iclass 5, count 2 2006.285.12:54:58.31#ibcon#about to read 3, iclass 5, count 2 2006.285.12:54:58.34#ibcon#read 3, iclass 5, count 2 2006.285.12:54:58.34#ibcon#about to read 4, iclass 5, count 2 2006.285.12:54:58.34#ibcon#read 4, iclass 5, count 2 2006.285.12:54:58.34#ibcon#about to read 5, iclass 5, count 2 2006.285.12:54:58.34#ibcon#read 5, iclass 5, count 2 2006.285.12:54:58.34#ibcon#about to read 6, iclass 5, count 2 2006.285.12:54:58.34#ibcon#read 6, iclass 5, count 2 2006.285.12:54:58.34#ibcon#end of sib2, iclass 5, count 2 2006.285.12:54:58.34#ibcon#*after write, iclass 5, count 2 2006.285.12:54:58.34#ibcon#*before return 0, iclass 5, count 2 2006.285.12:54:58.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:54:58.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:54:58.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.12:54:58.34#ibcon#ireg 7 cls_cnt 0 2006.285.12:54:58.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:54:58.46#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:54:58.46#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:54:58.46#ibcon#enter wrdev, iclass 5, count 0 2006.285.12:54:58.46#ibcon#first serial, iclass 5, count 0 2006.285.12:54:58.46#ibcon#enter sib2, iclass 5, count 0 2006.285.12:54:58.46#ibcon#flushed, iclass 5, count 0 2006.285.12:54:58.46#ibcon#about to write, iclass 5, count 0 2006.285.12:54:58.46#ibcon#wrote, iclass 5, count 0 2006.285.12:54:58.46#ibcon#about to read 3, iclass 5, count 0 2006.285.12:54:58.48#ibcon#read 3, iclass 5, count 0 2006.285.12:54:58.48#ibcon#about to read 4, iclass 5, count 0 2006.285.12:54:58.48#ibcon#read 4, iclass 5, count 0 2006.285.12:54:58.48#ibcon#about to read 5, iclass 5, count 0 2006.285.12:54:58.48#ibcon#read 5, iclass 5, count 0 2006.285.12:54:58.48#ibcon#about to read 6, iclass 5, count 0 2006.285.12:54:58.48#ibcon#read 6, iclass 5, count 0 2006.285.12:54:58.48#ibcon#end of sib2, iclass 5, count 0 2006.285.12:54:58.48#ibcon#*mode == 0, iclass 5, count 0 2006.285.12:54:58.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.12:54:58.48#ibcon#[25=USB\r\n] 2006.285.12:54:58.48#ibcon#*before write, iclass 5, count 0 2006.285.12:54:58.48#ibcon#enter sib2, iclass 5, count 0 2006.285.12:54:58.48#ibcon#flushed, iclass 5, count 0 2006.285.12:54:58.48#ibcon#about to write, iclass 5, count 0 2006.285.12:54:58.48#ibcon#wrote, iclass 5, count 0 2006.285.12:54:58.48#ibcon#about to read 3, iclass 5, count 0 2006.285.12:54:58.51#ibcon#read 3, iclass 5, count 0 2006.285.12:54:58.51#ibcon#about to read 4, iclass 5, count 0 2006.285.12:54:58.51#ibcon#read 4, iclass 5, count 0 2006.285.12:54:58.51#ibcon#about to read 5, iclass 5, count 0 2006.285.12:54:58.51#ibcon#read 5, iclass 5, count 0 2006.285.12:54:58.51#ibcon#about to read 6, iclass 5, count 0 2006.285.12:54:58.51#ibcon#read 6, iclass 5, count 0 2006.285.12:54:58.51#ibcon#end of sib2, iclass 5, count 0 2006.285.12:54:58.51#ibcon#*after write, iclass 5, count 0 2006.285.12:54:58.51#ibcon#*before return 0, iclass 5, count 0 2006.285.12:54:58.51#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:54:58.51#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:54:58.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.12:54:58.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.12:54:58.51$vck44/valo=5,734.99 2006.285.12:54:58.51#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.12:54:58.51#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.12:54:58.51#ibcon#ireg 17 cls_cnt 0 2006.285.12:54:58.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:54:58.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:54:58.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:54:58.51#ibcon#enter wrdev, iclass 7, count 0 2006.285.12:54:58.51#ibcon#first serial, iclass 7, count 0 2006.285.12:54:58.51#ibcon#enter sib2, iclass 7, count 0 2006.285.12:54:58.51#ibcon#flushed, iclass 7, count 0 2006.285.12:54:58.51#ibcon#about to write, iclass 7, count 0 2006.285.12:54:58.51#ibcon#wrote, iclass 7, count 0 2006.285.12:54:58.51#ibcon#about to read 3, iclass 7, count 0 2006.285.12:54:58.53#ibcon#read 3, iclass 7, count 0 2006.285.12:54:58.53#ibcon#about to read 4, iclass 7, count 0 2006.285.12:54:58.53#ibcon#read 4, iclass 7, count 0 2006.285.12:54:58.53#ibcon#about to read 5, iclass 7, count 0 2006.285.12:54:58.53#ibcon#read 5, iclass 7, count 0 2006.285.12:54:58.53#ibcon#about to read 6, iclass 7, count 0 2006.285.12:54:58.53#ibcon#read 6, iclass 7, count 0 2006.285.12:54:58.53#ibcon#end of sib2, iclass 7, count 0 2006.285.12:54:58.53#ibcon#*mode == 0, iclass 7, count 0 2006.285.12:54:58.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.12:54:58.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.12:54:58.53#ibcon#*before write, iclass 7, count 0 2006.285.12:54:58.53#ibcon#enter sib2, iclass 7, count 0 2006.285.12:54:58.53#ibcon#flushed, iclass 7, count 0 2006.285.12:54:58.53#ibcon#about to write, iclass 7, count 0 2006.285.12:54:58.53#ibcon#wrote, iclass 7, count 0 2006.285.12:54:58.53#ibcon#about to read 3, iclass 7, count 0 2006.285.12:54:58.57#ibcon#read 3, iclass 7, count 0 2006.285.12:54:58.57#ibcon#about to read 4, iclass 7, count 0 2006.285.12:54:58.57#ibcon#read 4, iclass 7, count 0 2006.285.12:54:58.57#ibcon#about to read 5, iclass 7, count 0 2006.285.12:54:58.57#ibcon#read 5, iclass 7, count 0 2006.285.12:54:58.57#ibcon#about to read 6, iclass 7, count 0 2006.285.12:54:58.57#ibcon#read 6, iclass 7, count 0 2006.285.12:54:58.57#ibcon#end of sib2, iclass 7, count 0 2006.285.12:54:58.57#ibcon#*after write, iclass 7, count 0 2006.285.12:54:58.57#ibcon#*before return 0, iclass 7, count 0 2006.285.12:54:58.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:54:58.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:54:58.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.12:54:58.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.12:54:58.57$vck44/va=5,3 2006.285.12:54:58.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.12:54:58.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.12:54:58.57#ibcon#ireg 11 cls_cnt 2 2006.285.12:54:58.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:54:58.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:54:58.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:54:58.63#ibcon#enter wrdev, iclass 11, count 2 2006.285.12:54:58.63#ibcon#first serial, iclass 11, count 2 2006.285.12:54:58.63#ibcon#enter sib2, iclass 11, count 2 2006.285.12:54:58.63#ibcon#flushed, iclass 11, count 2 2006.285.12:54:58.63#ibcon#about to write, iclass 11, count 2 2006.285.12:54:58.63#ibcon#wrote, iclass 11, count 2 2006.285.12:54:58.63#ibcon#about to read 3, iclass 11, count 2 2006.285.12:54:58.65#ibcon#read 3, iclass 11, count 2 2006.285.12:54:58.65#ibcon#about to read 4, iclass 11, count 2 2006.285.12:54:58.65#ibcon#read 4, iclass 11, count 2 2006.285.12:54:58.65#ibcon#about to read 5, iclass 11, count 2 2006.285.12:54:58.65#ibcon#read 5, iclass 11, count 2 2006.285.12:54:58.65#ibcon#about to read 6, iclass 11, count 2 2006.285.12:54:58.65#ibcon#read 6, iclass 11, count 2 2006.285.12:54:58.65#ibcon#end of sib2, iclass 11, count 2 2006.285.12:54:58.65#ibcon#*mode == 0, iclass 11, count 2 2006.285.12:54:58.65#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.12:54:58.65#ibcon#[25=AT05-03\r\n] 2006.285.12:54:58.65#ibcon#*before write, iclass 11, count 2 2006.285.12:54:58.65#ibcon#enter sib2, iclass 11, count 2 2006.285.12:54:58.65#ibcon#flushed, iclass 11, count 2 2006.285.12:54:58.65#ibcon#about to write, iclass 11, count 2 2006.285.12:54:58.65#ibcon#wrote, iclass 11, count 2 2006.285.12:54:58.65#ibcon#about to read 3, iclass 11, count 2 2006.285.12:54:58.68#ibcon#read 3, iclass 11, count 2 2006.285.12:54:58.68#ibcon#about to read 4, iclass 11, count 2 2006.285.12:54:58.68#ibcon#read 4, iclass 11, count 2 2006.285.12:54:58.68#ibcon#about to read 5, iclass 11, count 2 2006.285.12:54:58.68#ibcon#read 5, iclass 11, count 2 2006.285.12:54:58.68#ibcon#about to read 6, iclass 11, count 2 2006.285.12:54:58.68#ibcon#read 6, iclass 11, count 2 2006.285.12:54:58.68#ibcon#end of sib2, iclass 11, count 2 2006.285.12:54:58.68#ibcon#*after write, iclass 11, count 2 2006.285.12:54:58.68#ibcon#*before return 0, iclass 11, count 2 2006.285.12:54:58.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:54:58.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:54:58.68#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.12:54:58.68#ibcon#ireg 7 cls_cnt 0 2006.285.12:54:58.68#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:54:58.80#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:54:58.80#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:54:58.80#ibcon#enter wrdev, iclass 11, count 0 2006.285.12:54:58.80#ibcon#first serial, iclass 11, count 0 2006.285.12:54:58.80#ibcon#enter sib2, iclass 11, count 0 2006.285.12:54:58.80#ibcon#flushed, iclass 11, count 0 2006.285.12:54:58.80#ibcon#about to write, iclass 11, count 0 2006.285.12:54:58.80#ibcon#wrote, iclass 11, count 0 2006.285.12:54:58.80#ibcon#about to read 3, iclass 11, count 0 2006.285.12:54:58.82#ibcon#read 3, iclass 11, count 0 2006.285.12:54:58.82#ibcon#about to read 4, iclass 11, count 0 2006.285.12:54:58.82#ibcon#read 4, iclass 11, count 0 2006.285.12:54:58.82#ibcon#about to read 5, iclass 11, count 0 2006.285.12:54:58.82#ibcon#read 5, iclass 11, count 0 2006.285.12:54:58.82#ibcon#about to read 6, iclass 11, count 0 2006.285.12:54:58.82#ibcon#read 6, iclass 11, count 0 2006.285.12:54:58.82#ibcon#end of sib2, iclass 11, count 0 2006.285.12:54:58.82#ibcon#*mode == 0, iclass 11, count 0 2006.285.12:54:58.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.12:54:58.82#ibcon#[25=USB\r\n] 2006.285.12:54:58.82#ibcon#*before write, iclass 11, count 0 2006.285.12:54:58.82#ibcon#enter sib2, iclass 11, count 0 2006.285.12:54:58.82#ibcon#flushed, iclass 11, count 0 2006.285.12:54:58.82#ibcon#about to write, iclass 11, count 0 2006.285.12:54:58.82#ibcon#wrote, iclass 11, count 0 2006.285.12:54:58.82#ibcon#about to read 3, iclass 11, count 0 2006.285.12:54:58.85#ibcon#read 3, iclass 11, count 0 2006.285.12:54:58.85#ibcon#about to read 4, iclass 11, count 0 2006.285.12:54:58.85#ibcon#read 4, iclass 11, count 0 2006.285.12:54:58.85#ibcon#about to read 5, iclass 11, count 0 2006.285.12:54:58.85#ibcon#read 5, iclass 11, count 0 2006.285.12:54:58.85#ibcon#about to read 6, iclass 11, count 0 2006.285.12:54:58.85#ibcon#read 6, iclass 11, count 0 2006.285.12:54:58.85#ibcon#end of sib2, iclass 11, count 0 2006.285.12:54:58.85#ibcon#*after write, iclass 11, count 0 2006.285.12:54:58.85#ibcon#*before return 0, iclass 11, count 0 2006.285.12:54:58.85#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:54:58.85#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:54:58.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.12:54:58.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.12:54:58.85$vck44/valo=6,814.99 2006.285.12:54:58.85#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.12:54:58.85#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.12:54:58.85#ibcon#ireg 17 cls_cnt 0 2006.285.12:54:58.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:54:58.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:54:58.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:54:58.85#ibcon#enter wrdev, iclass 13, count 0 2006.285.12:54:58.85#ibcon#first serial, iclass 13, count 0 2006.285.12:54:58.85#ibcon#enter sib2, iclass 13, count 0 2006.285.12:54:58.85#ibcon#flushed, iclass 13, count 0 2006.285.12:54:58.85#ibcon#about to write, iclass 13, count 0 2006.285.12:54:58.85#ibcon#wrote, iclass 13, count 0 2006.285.12:54:58.85#ibcon#about to read 3, iclass 13, count 0 2006.285.12:54:58.87#ibcon#read 3, iclass 13, count 0 2006.285.12:54:58.87#ibcon#about to read 4, iclass 13, count 0 2006.285.12:54:58.87#ibcon#read 4, iclass 13, count 0 2006.285.12:54:58.87#ibcon#about to read 5, iclass 13, count 0 2006.285.12:54:58.87#ibcon#read 5, iclass 13, count 0 2006.285.12:54:58.87#ibcon#about to read 6, iclass 13, count 0 2006.285.12:54:58.87#ibcon#read 6, iclass 13, count 0 2006.285.12:54:58.87#ibcon#end of sib2, iclass 13, count 0 2006.285.12:54:58.87#ibcon#*mode == 0, iclass 13, count 0 2006.285.12:54:58.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.12:54:58.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.12:54:58.87#ibcon#*before write, iclass 13, count 0 2006.285.12:54:58.87#ibcon#enter sib2, iclass 13, count 0 2006.285.12:54:58.87#ibcon#flushed, iclass 13, count 0 2006.285.12:54:58.87#ibcon#about to write, iclass 13, count 0 2006.285.12:54:58.87#ibcon#wrote, iclass 13, count 0 2006.285.12:54:58.87#ibcon#about to read 3, iclass 13, count 0 2006.285.12:54:58.91#ibcon#read 3, iclass 13, count 0 2006.285.12:54:58.91#ibcon#about to read 4, iclass 13, count 0 2006.285.12:54:58.91#ibcon#read 4, iclass 13, count 0 2006.285.12:54:58.91#ibcon#about to read 5, iclass 13, count 0 2006.285.12:54:58.91#ibcon#read 5, iclass 13, count 0 2006.285.12:54:58.91#ibcon#about to read 6, iclass 13, count 0 2006.285.12:54:58.91#ibcon#read 6, iclass 13, count 0 2006.285.12:54:58.91#ibcon#end of sib2, iclass 13, count 0 2006.285.12:54:58.91#ibcon#*after write, iclass 13, count 0 2006.285.12:54:58.91#ibcon#*before return 0, iclass 13, count 0 2006.285.12:54:58.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:54:58.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:54:58.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.12:54:58.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.12:54:58.91$vck44/va=6,4 2006.285.12:54:58.91#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.12:54:58.91#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.12:54:58.91#ibcon#ireg 11 cls_cnt 2 2006.285.12:54:58.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:54:58.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:54:58.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:54:58.97#ibcon#enter wrdev, iclass 15, count 2 2006.285.12:54:58.97#ibcon#first serial, iclass 15, count 2 2006.285.12:54:58.97#ibcon#enter sib2, iclass 15, count 2 2006.285.12:54:58.97#ibcon#flushed, iclass 15, count 2 2006.285.12:54:58.97#ibcon#about to write, iclass 15, count 2 2006.285.12:54:58.97#ibcon#wrote, iclass 15, count 2 2006.285.12:54:58.97#ibcon#about to read 3, iclass 15, count 2 2006.285.12:54:58.99#ibcon#read 3, iclass 15, count 2 2006.285.12:54:58.99#ibcon#about to read 4, iclass 15, count 2 2006.285.12:54:58.99#ibcon#read 4, iclass 15, count 2 2006.285.12:54:58.99#ibcon#about to read 5, iclass 15, count 2 2006.285.12:54:58.99#ibcon#read 5, iclass 15, count 2 2006.285.12:54:58.99#ibcon#about to read 6, iclass 15, count 2 2006.285.12:54:58.99#ibcon#read 6, iclass 15, count 2 2006.285.12:54:58.99#ibcon#end of sib2, iclass 15, count 2 2006.285.12:54:58.99#ibcon#*mode == 0, iclass 15, count 2 2006.285.12:54:58.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.12:54:58.99#ibcon#[25=AT06-04\r\n] 2006.285.12:54:58.99#ibcon#*before write, iclass 15, count 2 2006.285.12:54:58.99#ibcon#enter sib2, iclass 15, count 2 2006.285.12:54:58.99#ibcon#flushed, iclass 15, count 2 2006.285.12:54:58.99#ibcon#about to write, iclass 15, count 2 2006.285.12:54:58.99#ibcon#wrote, iclass 15, count 2 2006.285.12:54:58.99#ibcon#about to read 3, iclass 15, count 2 2006.285.12:54:59.02#ibcon#read 3, iclass 15, count 2 2006.285.12:54:59.02#ibcon#about to read 4, iclass 15, count 2 2006.285.12:54:59.02#ibcon#read 4, iclass 15, count 2 2006.285.12:54:59.02#ibcon#about to read 5, iclass 15, count 2 2006.285.12:54:59.02#ibcon#read 5, iclass 15, count 2 2006.285.12:54:59.02#ibcon#about to read 6, iclass 15, count 2 2006.285.12:54:59.02#ibcon#read 6, iclass 15, count 2 2006.285.12:54:59.02#ibcon#end of sib2, iclass 15, count 2 2006.285.12:54:59.02#ibcon#*after write, iclass 15, count 2 2006.285.12:54:59.02#ibcon#*before return 0, iclass 15, count 2 2006.285.12:54:59.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:54:59.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:54:59.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.12:54:59.02#ibcon#ireg 7 cls_cnt 0 2006.285.12:54:59.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:54:59.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:54:59.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:54:59.14#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:54:59.14#ibcon#first serial, iclass 15, count 0 2006.285.12:54:59.14#ibcon#enter sib2, iclass 15, count 0 2006.285.12:54:59.14#ibcon#flushed, iclass 15, count 0 2006.285.12:54:59.14#ibcon#about to write, iclass 15, count 0 2006.285.12:54:59.14#ibcon#wrote, iclass 15, count 0 2006.285.12:54:59.14#ibcon#about to read 3, iclass 15, count 0 2006.285.12:54:59.16#ibcon#read 3, iclass 15, count 0 2006.285.12:54:59.16#ibcon#about to read 4, iclass 15, count 0 2006.285.12:54:59.16#ibcon#read 4, iclass 15, count 0 2006.285.12:54:59.16#ibcon#about to read 5, iclass 15, count 0 2006.285.12:54:59.16#ibcon#read 5, iclass 15, count 0 2006.285.12:54:59.16#ibcon#about to read 6, iclass 15, count 0 2006.285.12:54:59.16#ibcon#read 6, iclass 15, count 0 2006.285.12:54:59.16#ibcon#end of sib2, iclass 15, count 0 2006.285.12:54:59.16#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:54:59.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:54:59.16#ibcon#[25=USB\r\n] 2006.285.12:54:59.16#ibcon#*before write, iclass 15, count 0 2006.285.12:54:59.16#ibcon#enter sib2, iclass 15, count 0 2006.285.12:54:59.16#ibcon#flushed, iclass 15, count 0 2006.285.12:54:59.16#ibcon#about to write, iclass 15, count 0 2006.285.12:54:59.16#ibcon#wrote, iclass 15, count 0 2006.285.12:54:59.16#ibcon#about to read 3, iclass 15, count 0 2006.285.12:54:59.19#ibcon#read 3, iclass 15, count 0 2006.285.12:54:59.19#ibcon#about to read 4, iclass 15, count 0 2006.285.12:54:59.19#ibcon#read 4, iclass 15, count 0 2006.285.12:54:59.19#ibcon#about to read 5, iclass 15, count 0 2006.285.12:54:59.19#ibcon#read 5, iclass 15, count 0 2006.285.12:54:59.19#ibcon#about to read 6, iclass 15, count 0 2006.285.12:54:59.19#ibcon#read 6, iclass 15, count 0 2006.285.12:54:59.19#ibcon#end of sib2, iclass 15, count 0 2006.285.12:54:59.19#ibcon#*after write, iclass 15, count 0 2006.285.12:54:59.19#ibcon#*before return 0, iclass 15, count 0 2006.285.12:54:59.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:54:59.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:54:59.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:54:59.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:54:59.19$vck44/valo=7,864.99 2006.285.12:54:59.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.12:54:59.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.12:54:59.19#ibcon#ireg 17 cls_cnt 0 2006.285.12:54:59.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:54:59.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:54:59.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:54:59.19#ibcon#enter wrdev, iclass 17, count 0 2006.285.12:54:59.19#ibcon#first serial, iclass 17, count 0 2006.285.12:54:59.19#ibcon#enter sib2, iclass 17, count 0 2006.285.12:54:59.19#ibcon#flushed, iclass 17, count 0 2006.285.12:54:59.19#ibcon#about to write, iclass 17, count 0 2006.285.12:54:59.19#ibcon#wrote, iclass 17, count 0 2006.285.12:54:59.19#ibcon#about to read 3, iclass 17, count 0 2006.285.12:54:59.21#ibcon#read 3, iclass 17, count 0 2006.285.12:54:59.26#ibcon#about to read 4, iclass 17, count 0 2006.285.12:54:59.26#ibcon#read 4, iclass 17, count 0 2006.285.12:54:59.26#ibcon#about to read 5, iclass 17, count 0 2006.285.12:54:59.26#ibcon#read 5, iclass 17, count 0 2006.285.12:54:59.26#ibcon#about to read 6, iclass 17, count 0 2006.285.12:54:59.26#ibcon#read 6, iclass 17, count 0 2006.285.12:54:59.26#ibcon#end of sib2, iclass 17, count 0 2006.285.12:54:59.26#ibcon#*mode == 0, iclass 17, count 0 2006.285.12:54:59.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.12:54:59.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.12:54:59.26#ibcon#*before write, iclass 17, count 0 2006.285.12:54:59.26#ibcon#enter sib2, iclass 17, count 0 2006.285.12:54:59.26#ibcon#flushed, iclass 17, count 0 2006.285.12:54:59.26#ibcon#about to write, iclass 17, count 0 2006.285.12:54:59.26#ibcon#wrote, iclass 17, count 0 2006.285.12:54:59.26#ibcon#about to read 3, iclass 17, count 0 2006.285.12:54:59.31#ibcon#read 3, iclass 17, count 0 2006.285.12:54:59.31#ibcon#about to read 4, iclass 17, count 0 2006.285.12:54:59.31#ibcon#read 4, iclass 17, count 0 2006.285.12:54:59.31#ibcon#about to read 5, iclass 17, count 0 2006.285.12:54:59.31#ibcon#read 5, iclass 17, count 0 2006.285.12:54:59.31#ibcon#about to read 6, iclass 17, count 0 2006.285.12:54:59.31#ibcon#read 6, iclass 17, count 0 2006.285.12:54:59.31#ibcon#end of sib2, iclass 17, count 0 2006.285.12:54:59.31#ibcon#*after write, iclass 17, count 0 2006.285.12:54:59.31#ibcon#*before return 0, iclass 17, count 0 2006.285.12:54:59.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:54:59.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.12:54:59.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.12:54:59.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.12:54:59.31$vck44/va=7,4 2006.285.12:54:59.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.12:54:59.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.12:54:59.31#ibcon#ireg 11 cls_cnt 2 2006.285.12:54:59.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:54:59.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:54:59.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:54:59.31#ibcon#enter wrdev, iclass 19, count 2 2006.285.12:54:59.31#ibcon#first serial, iclass 19, count 2 2006.285.12:54:59.31#ibcon#enter sib2, iclass 19, count 2 2006.285.12:54:59.31#ibcon#flushed, iclass 19, count 2 2006.285.12:54:59.31#ibcon#about to write, iclass 19, count 2 2006.285.12:54:59.31#ibcon#wrote, iclass 19, count 2 2006.285.12:54:59.31#ibcon#about to read 3, iclass 19, count 2 2006.285.12:54:59.33#ibcon#read 3, iclass 19, count 2 2006.285.12:54:59.33#ibcon#about to read 4, iclass 19, count 2 2006.285.12:54:59.33#ibcon#read 4, iclass 19, count 2 2006.285.12:54:59.33#ibcon#about to read 5, iclass 19, count 2 2006.285.12:54:59.33#ibcon#read 5, iclass 19, count 2 2006.285.12:54:59.33#ibcon#about to read 6, iclass 19, count 2 2006.285.12:54:59.33#ibcon#read 6, iclass 19, count 2 2006.285.12:54:59.33#ibcon#end of sib2, iclass 19, count 2 2006.285.12:54:59.33#ibcon#*mode == 0, iclass 19, count 2 2006.285.12:54:59.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.12:54:59.33#ibcon#[25=AT07-04\r\n] 2006.285.12:54:59.33#ibcon#*before write, iclass 19, count 2 2006.285.12:54:59.33#ibcon#enter sib2, iclass 19, count 2 2006.285.12:54:59.33#ibcon#flushed, iclass 19, count 2 2006.285.12:54:59.33#ibcon#about to write, iclass 19, count 2 2006.285.12:54:59.33#ibcon#wrote, iclass 19, count 2 2006.285.12:54:59.33#ibcon#about to read 3, iclass 19, count 2 2006.285.12:54:59.36#ibcon#read 3, iclass 19, count 2 2006.285.12:54:59.36#ibcon#about to read 4, iclass 19, count 2 2006.285.12:54:59.36#ibcon#read 4, iclass 19, count 2 2006.285.12:54:59.36#ibcon#about to read 5, iclass 19, count 2 2006.285.12:54:59.36#ibcon#read 5, iclass 19, count 2 2006.285.12:54:59.36#ibcon#about to read 6, iclass 19, count 2 2006.285.12:54:59.36#ibcon#read 6, iclass 19, count 2 2006.285.12:54:59.36#ibcon#end of sib2, iclass 19, count 2 2006.285.12:54:59.36#ibcon#*after write, iclass 19, count 2 2006.285.12:54:59.36#ibcon#*before return 0, iclass 19, count 2 2006.285.12:54:59.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:54:59.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.12:54:59.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.12:54:59.36#ibcon#ireg 7 cls_cnt 0 2006.285.12:54:59.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:54:59.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:54:59.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:54:59.48#ibcon#enter wrdev, iclass 19, count 0 2006.285.12:54:59.48#ibcon#first serial, iclass 19, count 0 2006.285.12:54:59.48#ibcon#enter sib2, iclass 19, count 0 2006.285.12:54:59.48#ibcon#flushed, iclass 19, count 0 2006.285.12:54:59.48#ibcon#about to write, iclass 19, count 0 2006.285.12:54:59.48#ibcon#wrote, iclass 19, count 0 2006.285.12:54:59.48#ibcon#about to read 3, iclass 19, count 0 2006.285.12:54:59.50#ibcon#read 3, iclass 19, count 0 2006.285.12:54:59.50#ibcon#about to read 4, iclass 19, count 0 2006.285.12:54:59.50#ibcon#read 4, iclass 19, count 0 2006.285.12:54:59.50#ibcon#about to read 5, iclass 19, count 0 2006.285.12:54:59.50#ibcon#read 5, iclass 19, count 0 2006.285.12:54:59.50#ibcon#about to read 6, iclass 19, count 0 2006.285.12:54:59.50#ibcon#read 6, iclass 19, count 0 2006.285.12:54:59.50#ibcon#end of sib2, iclass 19, count 0 2006.285.12:54:59.50#ibcon#*mode == 0, iclass 19, count 0 2006.285.12:54:59.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.12:54:59.50#ibcon#[25=USB\r\n] 2006.285.12:54:59.50#ibcon#*before write, iclass 19, count 0 2006.285.12:54:59.50#ibcon#enter sib2, iclass 19, count 0 2006.285.12:54:59.50#ibcon#flushed, iclass 19, count 0 2006.285.12:54:59.50#ibcon#about to write, iclass 19, count 0 2006.285.12:54:59.50#ibcon#wrote, iclass 19, count 0 2006.285.12:54:59.50#ibcon#about to read 3, iclass 19, count 0 2006.285.12:54:59.53#ibcon#read 3, iclass 19, count 0 2006.285.12:54:59.53#ibcon#about to read 4, iclass 19, count 0 2006.285.12:54:59.53#ibcon#read 4, iclass 19, count 0 2006.285.12:54:59.53#ibcon#about to read 5, iclass 19, count 0 2006.285.12:54:59.53#ibcon#read 5, iclass 19, count 0 2006.285.12:54:59.53#ibcon#about to read 6, iclass 19, count 0 2006.285.12:54:59.53#ibcon#read 6, iclass 19, count 0 2006.285.12:54:59.53#ibcon#end of sib2, iclass 19, count 0 2006.285.12:54:59.53#ibcon#*after write, iclass 19, count 0 2006.285.12:54:59.53#ibcon#*before return 0, iclass 19, count 0 2006.285.12:54:59.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:54:59.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.12:54:59.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.12:54:59.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.12:54:59.53$vck44/valo=8,884.99 2006.285.12:54:59.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.12:54:59.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.12:54:59.53#ibcon#ireg 17 cls_cnt 0 2006.285.12:54:59.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:54:59.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:54:59.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:54:59.53#ibcon#enter wrdev, iclass 21, count 0 2006.285.12:54:59.53#ibcon#first serial, iclass 21, count 0 2006.285.12:54:59.53#ibcon#enter sib2, iclass 21, count 0 2006.285.12:54:59.53#ibcon#flushed, iclass 21, count 0 2006.285.12:54:59.53#ibcon#about to write, iclass 21, count 0 2006.285.12:54:59.53#ibcon#wrote, iclass 21, count 0 2006.285.12:54:59.53#ibcon#about to read 3, iclass 21, count 0 2006.285.12:54:59.55#ibcon#read 3, iclass 21, count 0 2006.285.12:54:59.55#ibcon#about to read 4, iclass 21, count 0 2006.285.12:54:59.55#ibcon#read 4, iclass 21, count 0 2006.285.12:54:59.55#ibcon#about to read 5, iclass 21, count 0 2006.285.12:54:59.55#ibcon#read 5, iclass 21, count 0 2006.285.12:54:59.55#ibcon#about to read 6, iclass 21, count 0 2006.285.12:54:59.55#ibcon#read 6, iclass 21, count 0 2006.285.12:54:59.55#ibcon#end of sib2, iclass 21, count 0 2006.285.12:54:59.55#ibcon#*mode == 0, iclass 21, count 0 2006.285.12:54:59.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.12:54:59.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.12:54:59.55#ibcon#*before write, iclass 21, count 0 2006.285.12:54:59.55#ibcon#enter sib2, iclass 21, count 0 2006.285.12:54:59.55#ibcon#flushed, iclass 21, count 0 2006.285.12:54:59.55#ibcon#about to write, iclass 21, count 0 2006.285.12:54:59.55#ibcon#wrote, iclass 21, count 0 2006.285.12:54:59.55#ibcon#about to read 3, iclass 21, count 0 2006.285.12:54:59.59#ibcon#read 3, iclass 21, count 0 2006.285.12:54:59.59#ibcon#about to read 4, iclass 21, count 0 2006.285.12:54:59.59#ibcon#read 4, iclass 21, count 0 2006.285.12:54:59.59#ibcon#about to read 5, iclass 21, count 0 2006.285.12:54:59.59#ibcon#read 5, iclass 21, count 0 2006.285.12:54:59.59#ibcon#about to read 6, iclass 21, count 0 2006.285.12:54:59.59#ibcon#read 6, iclass 21, count 0 2006.285.12:54:59.59#ibcon#end of sib2, iclass 21, count 0 2006.285.12:54:59.59#ibcon#*after write, iclass 21, count 0 2006.285.12:54:59.59#ibcon#*before return 0, iclass 21, count 0 2006.285.12:54:59.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:54:59.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.12:54:59.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.12:54:59.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.12:54:59.59$vck44/va=8,3 2006.285.12:54:59.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.12:54:59.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.12:54:59.59#ibcon#ireg 11 cls_cnt 2 2006.285.12:54:59.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:54:59.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:54:59.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:54:59.65#ibcon#enter wrdev, iclass 23, count 2 2006.285.12:54:59.65#ibcon#first serial, iclass 23, count 2 2006.285.12:54:59.65#ibcon#enter sib2, iclass 23, count 2 2006.285.12:54:59.65#ibcon#flushed, iclass 23, count 2 2006.285.12:54:59.65#ibcon#about to write, iclass 23, count 2 2006.285.12:54:59.65#ibcon#wrote, iclass 23, count 2 2006.285.12:54:59.65#ibcon#about to read 3, iclass 23, count 2 2006.285.12:54:59.67#ibcon#read 3, iclass 23, count 2 2006.285.12:54:59.67#ibcon#about to read 4, iclass 23, count 2 2006.285.12:54:59.67#ibcon#read 4, iclass 23, count 2 2006.285.12:54:59.67#ibcon#about to read 5, iclass 23, count 2 2006.285.12:54:59.67#ibcon#read 5, iclass 23, count 2 2006.285.12:54:59.67#ibcon#about to read 6, iclass 23, count 2 2006.285.12:54:59.67#ibcon#read 6, iclass 23, count 2 2006.285.12:54:59.67#ibcon#end of sib2, iclass 23, count 2 2006.285.12:54:59.67#ibcon#*mode == 0, iclass 23, count 2 2006.285.12:54:59.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.12:54:59.67#ibcon#[25=AT08-03\r\n] 2006.285.12:54:59.67#ibcon#*before write, iclass 23, count 2 2006.285.12:54:59.67#ibcon#enter sib2, iclass 23, count 2 2006.285.12:54:59.67#ibcon#flushed, iclass 23, count 2 2006.285.12:54:59.67#ibcon#about to write, iclass 23, count 2 2006.285.12:54:59.67#ibcon#wrote, iclass 23, count 2 2006.285.12:54:59.67#ibcon#about to read 3, iclass 23, count 2 2006.285.12:54:59.70#ibcon#read 3, iclass 23, count 2 2006.285.12:54:59.70#ibcon#about to read 4, iclass 23, count 2 2006.285.12:54:59.70#ibcon#read 4, iclass 23, count 2 2006.285.12:54:59.70#ibcon#about to read 5, iclass 23, count 2 2006.285.12:54:59.70#ibcon#read 5, iclass 23, count 2 2006.285.12:54:59.70#ibcon#about to read 6, iclass 23, count 2 2006.285.12:54:59.70#ibcon#read 6, iclass 23, count 2 2006.285.12:54:59.70#ibcon#end of sib2, iclass 23, count 2 2006.285.12:54:59.70#ibcon#*after write, iclass 23, count 2 2006.285.12:54:59.70#ibcon#*before return 0, iclass 23, count 2 2006.285.12:54:59.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:54:59.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.12:54:59.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.12:54:59.70#ibcon#ireg 7 cls_cnt 0 2006.285.12:54:59.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:54:59.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:54:59.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:54:59.82#ibcon#enter wrdev, iclass 23, count 0 2006.285.12:54:59.82#ibcon#first serial, iclass 23, count 0 2006.285.12:54:59.82#ibcon#enter sib2, iclass 23, count 0 2006.285.12:54:59.82#ibcon#flushed, iclass 23, count 0 2006.285.12:54:59.82#ibcon#about to write, iclass 23, count 0 2006.285.12:54:59.82#ibcon#wrote, iclass 23, count 0 2006.285.12:54:59.82#ibcon#about to read 3, iclass 23, count 0 2006.285.12:54:59.84#ibcon#read 3, iclass 23, count 0 2006.285.12:54:59.84#ibcon#about to read 4, iclass 23, count 0 2006.285.12:54:59.84#ibcon#read 4, iclass 23, count 0 2006.285.12:54:59.84#ibcon#about to read 5, iclass 23, count 0 2006.285.12:54:59.84#ibcon#read 5, iclass 23, count 0 2006.285.12:54:59.84#ibcon#about to read 6, iclass 23, count 0 2006.285.12:54:59.84#ibcon#read 6, iclass 23, count 0 2006.285.12:54:59.84#ibcon#end of sib2, iclass 23, count 0 2006.285.12:54:59.84#ibcon#*mode == 0, iclass 23, count 0 2006.285.12:54:59.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.12:54:59.84#ibcon#[25=USB\r\n] 2006.285.12:54:59.84#ibcon#*before write, iclass 23, count 0 2006.285.12:54:59.84#ibcon#enter sib2, iclass 23, count 0 2006.285.12:54:59.84#ibcon#flushed, iclass 23, count 0 2006.285.12:54:59.84#ibcon#about to write, iclass 23, count 0 2006.285.12:54:59.84#ibcon#wrote, iclass 23, count 0 2006.285.12:54:59.84#ibcon#about to read 3, iclass 23, count 0 2006.285.12:54:59.87#ibcon#read 3, iclass 23, count 0 2006.285.12:54:59.87#ibcon#about to read 4, iclass 23, count 0 2006.285.12:54:59.87#ibcon#read 4, iclass 23, count 0 2006.285.12:54:59.87#ibcon#about to read 5, iclass 23, count 0 2006.285.12:54:59.87#ibcon#read 5, iclass 23, count 0 2006.285.12:54:59.87#ibcon#about to read 6, iclass 23, count 0 2006.285.12:54:59.87#ibcon#read 6, iclass 23, count 0 2006.285.12:54:59.87#ibcon#end of sib2, iclass 23, count 0 2006.285.12:54:59.87#ibcon#*after write, iclass 23, count 0 2006.285.12:54:59.87#ibcon#*before return 0, iclass 23, count 0 2006.285.12:54:59.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:54:59.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.12:54:59.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.12:54:59.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.12:54:59.87$vck44/vblo=1,629.99 2006.285.12:54:59.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.12:54:59.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.12:54:59.87#ibcon#ireg 17 cls_cnt 0 2006.285.12:54:59.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:54:59.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:54:59.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:54:59.87#ibcon#enter wrdev, iclass 25, count 0 2006.285.12:54:59.87#ibcon#first serial, iclass 25, count 0 2006.285.12:54:59.87#ibcon#enter sib2, iclass 25, count 0 2006.285.12:54:59.87#ibcon#flushed, iclass 25, count 0 2006.285.12:54:59.87#ibcon#about to write, iclass 25, count 0 2006.285.12:54:59.87#ibcon#wrote, iclass 25, count 0 2006.285.12:54:59.87#ibcon#about to read 3, iclass 25, count 0 2006.285.12:54:59.89#ibcon#read 3, iclass 25, count 0 2006.285.12:54:59.89#ibcon#about to read 4, iclass 25, count 0 2006.285.12:54:59.89#ibcon#read 4, iclass 25, count 0 2006.285.12:54:59.89#ibcon#about to read 5, iclass 25, count 0 2006.285.12:54:59.89#ibcon#read 5, iclass 25, count 0 2006.285.12:54:59.89#ibcon#about to read 6, iclass 25, count 0 2006.285.12:54:59.89#ibcon#read 6, iclass 25, count 0 2006.285.12:54:59.89#ibcon#end of sib2, iclass 25, count 0 2006.285.12:54:59.89#ibcon#*mode == 0, iclass 25, count 0 2006.285.12:54:59.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.12:54:59.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.12:54:59.89#ibcon#*before write, iclass 25, count 0 2006.285.12:54:59.89#ibcon#enter sib2, iclass 25, count 0 2006.285.12:54:59.89#ibcon#flushed, iclass 25, count 0 2006.285.12:54:59.89#ibcon#about to write, iclass 25, count 0 2006.285.12:54:59.89#ibcon#wrote, iclass 25, count 0 2006.285.12:54:59.89#ibcon#about to read 3, iclass 25, count 0 2006.285.12:54:59.93#ibcon#read 3, iclass 25, count 0 2006.285.12:54:59.93#ibcon#about to read 4, iclass 25, count 0 2006.285.12:54:59.93#ibcon#read 4, iclass 25, count 0 2006.285.12:54:59.93#ibcon#about to read 5, iclass 25, count 0 2006.285.12:54:59.93#ibcon#read 5, iclass 25, count 0 2006.285.12:54:59.93#ibcon#about to read 6, iclass 25, count 0 2006.285.12:54:59.93#ibcon#read 6, iclass 25, count 0 2006.285.12:54:59.93#ibcon#end of sib2, iclass 25, count 0 2006.285.12:54:59.93#ibcon#*after write, iclass 25, count 0 2006.285.12:54:59.93#ibcon#*before return 0, iclass 25, count 0 2006.285.12:54:59.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:54:59.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:54:59.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.12:54:59.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.12:54:59.93$vck44/vb=1,4 2006.285.12:54:59.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.12:54:59.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.12:54:59.93#ibcon#ireg 11 cls_cnt 2 2006.285.12:54:59.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:54:59.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:54:59.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:54:59.93#ibcon#enter wrdev, iclass 27, count 2 2006.285.12:54:59.93#ibcon#first serial, iclass 27, count 2 2006.285.12:54:59.93#ibcon#enter sib2, iclass 27, count 2 2006.285.12:54:59.93#ibcon#flushed, iclass 27, count 2 2006.285.12:54:59.93#ibcon#about to write, iclass 27, count 2 2006.285.12:54:59.93#ibcon#wrote, iclass 27, count 2 2006.285.12:54:59.93#ibcon#about to read 3, iclass 27, count 2 2006.285.12:54:59.95#ibcon#read 3, iclass 27, count 2 2006.285.12:54:59.95#ibcon#about to read 4, iclass 27, count 2 2006.285.12:54:59.95#ibcon#read 4, iclass 27, count 2 2006.285.12:54:59.95#ibcon#about to read 5, iclass 27, count 2 2006.285.12:54:59.95#ibcon#read 5, iclass 27, count 2 2006.285.12:54:59.95#ibcon#about to read 6, iclass 27, count 2 2006.285.12:54:59.95#ibcon#read 6, iclass 27, count 2 2006.285.12:54:59.95#ibcon#end of sib2, iclass 27, count 2 2006.285.12:54:59.95#ibcon#*mode == 0, iclass 27, count 2 2006.285.12:54:59.95#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.12:54:59.95#ibcon#[27=AT01-04\r\n] 2006.285.12:54:59.95#ibcon#*before write, iclass 27, count 2 2006.285.12:54:59.95#ibcon#enter sib2, iclass 27, count 2 2006.285.12:54:59.95#ibcon#flushed, iclass 27, count 2 2006.285.12:54:59.95#ibcon#about to write, iclass 27, count 2 2006.285.12:54:59.95#ibcon#wrote, iclass 27, count 2 2006.285.12:54:59.95#ibcon#about to read 3, iclass 27, count 2 2006.285.12:54:59.98#ibcon#read 3, iclass 27, count 2 2006.285.12:54:59.98#ibcon#about to read 4, iclass 27, count 2 2006.285.12:54:59.98#ibcon#read 4, iclass 27, count 2 2006.285.12:54:59.98#ibcon#about to read 5, iclass 27, count 2 2006.285.12:54:59.98#ibcon#read 5, iclass 27, count 2 2006.285.12:54:59.98#ibcon#about to read 6, iclass 27, count 2 2006.285.12:54:59.98#ibcon#read 6, iclass 27, count 2 2006.285.12:54:59.98#ibcon#end of sib2, iclass 27, count 2 2006.285.12:54:59.98#ibcon#*after write, iclass 27, count 2 2006.285.12:54:59.98#ibcon#*before return 0, iclass 27, count 2 2006.285.12:54:59.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:54:59.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.12:54:59.98#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.12:54:59.98#ibcon#ireg 7 cls_cnt 0 2006.285.12:54:59.98#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:55:00.10#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:55:00.10#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:55:00.10#ibcon#enter wrdev, iclass 27, count 0 2006.285.12:55:00.10#ibcon#first serial, iclass 27, count 0 2006.285.12:55:00.10#ibcon#enter sib2, iclass 27, count 0 2006.285.12:55:00.10#ibcon#flushed, iclass 27, count 0 2006.285.12:55:00.10#ibcon#about to write, iclass 27, count 0 2006.285.12:55:00.10#ibcon#wrote, iclass 27, count 0 2006.285.12:55:00.10#ibcon#about to read 3, iclass 27, count 0 2006.285.12:55:00.12#ibcon#read 3, iclass 27, count 0 2006.285.12:55:00.12#ibcon#about to read 4, iclass 27, count 0 2006.285.12:55:00.12#ibcon#read 4, iclass 27, count 0 2006.285.12:55:00.12#ibcon#about to read 5, iclass 27, count 0 2006.285.12:55:00.12#ibcon#read 5, iclass 27, count 0 2006.285.12:55:00.12#ibcon#about to read 6, iclass 27, count 0 2006.285.12:55:00.12#ibcon#read 6, iclass 27, count 0 2006.285.12:55:00.12#ibcon#end of sib2, iclass 27, count 0 2006.285.12:55:00.12#ibcon#*mode == 0, iclass 27, count 0 2006.285.12:55:00.12#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.12:55:00.12#ibcon#[27=USB\r\n] 2006.285.12:55:00.12#ibcon#*before write, iclass 27, count 0 2006.285.12:55:00.12#ibcon#enter sib2, iclass 27, count 0 2006.285.12:55:00.12#ibcon#flushed, iclass 27, count 0 2006.285.12:55:00.12#ibcon#about to write, iclass 27, count 0 2006.285.12:55:00.12#ibcon#wrote, iclass 27, count 0 2006.285.12:55:00.12#ibcon#about to read 3, iclass 27, count 0 2006.285.12:55:00.15#ibcon#read 3, iclass 27, count 0 2006.285.12:55:00.15#ibcon#about to read 4, iclass 27, count 0 2006.285.12:55:00.15#ibcon#read 4, iclass 27, count 0 2006.285.12:55:00.15#ibcon#about to read 5, iclass 27, count 0 2006.285.12:55:00.15#ibcon#read 5, iclass 27, count 0 2006.285.12:55:00.15#ibcon#about to read 6, iclass 27, count 0 2006.285.12:55:00.15#ibcon#read 6, iclass 27, count 0 2006.285.12:55:00.15#ibcon#end of sib2, iclass 27, count 0 2006.285.12:55:00.15#ibcon#*after write, iclass 27, count 0 2006.285.12:55:00.15#ibcon#*before return 0, iclass 27, count 0 2006.285.12:55:00.15#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:55:00.15#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.12:55:00.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.12:55:00.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.12:55:00.15$vck44/vblo=2,634.99 2006.285.12:55:00.15#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.12:55:00.15#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.12:55:00.15#ibcon#ireg 17 cls_cnt 0 2006.285.12:55:00.15#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:55:00.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:55:00.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:55:00.15#ibcon#enter wrdev, iclass 29, count 0 2006.285.12:55:00.15#ibcon#first serial, iclass 29, count 0 2006.285.12:55:00.15#ibcon#enter sib2, iclass 29, count 0 2006.285.12:55:00.15#ibcon#flushed, iclass 29, count 0 2006.285.12:55:00.15#ibcon#about to write, iclass 29, count 0 2006.285.12:55:00.15#ibcon#wrote, iclass 29, count 0 2006.285.12:55:00.15#ibcon#about to read 3, iclass 29, count 0 2006.285.12:55:00.17#ibcon#read 3, iclass 29, count 0 2006.285.12:55:00.26#ibcon#about to read 4, iclass 29, count 0 2006.285.12:55:00.26#ibcon#read 4, iclass 29, count 0 2006.285.12:55:00.26#ibcon#about to read 5, iclass 29, count 0 2006.285.12:55:00.26#ibcon#read 5, iclass 29, count 0 2006.285.12:55:00.26#ibcon#about to read 6, iclass 29, count 0 2006.285.12:55:00.26#ibcon#read 6, iclass 29, count 0 2006.285.12:55:00.26#ibcon#end of sib2, iclass 29, count 0 2006.285.12:55:00.26#ibcon#*mode == 0, iclass 29, count 0 2006.285.12:55:00.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.12:55:00.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.12:55:00.26#ibcon#*before write, iclass 29, count 0 2006.285.12:55:00.26#ibcon#enter sib2, iclass 29, count 0 2006.285.12:55:00.26#ibcon#flushed, iclass 29, count 0 2006.285.12:55:00.26#ibcon#about to write, iclass 29, count 0 2006.285.12:55:00.26#ibcon#wrote, iclass 29, count 0 2006.285.12:55:00.26#ibcon#about to read 3, iclass 29, count 0 2006.285.12:55:00.30#ibcon#read 3, iclass 29, count 0 2006.285.12:55:00.30#ibcon#about to read 4, iclass 29, count 0 2006.285.12:55:00.30#ibcon#read 4, iclass 29, count 0 2006.285.12:55:00.30#ibcon#about to read 5, iclass 29, count 0 2006.285.12:55:00.30#ibcon#read 5, iclass 29, count 0 2006.285.12:55:00.30#ibcon#about to read 6, iclass 29, count 0 2006.285.12:55:00.30#ibcon#read 6, iclass 29, count 0 2006.285.12:55:00.30#ibcon#end of sib2, iclass 29, count 0 2006.285.12:55:00.30#ibcon#*after write, iclass 29, count 0 2006.285.12:55:00.30#ibcon#*before return 0, iclass 29, count 0 2006.285.12:55:00.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:55:00.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.12:55:00.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.12:55:00.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.12:55:00.30$vck44/vb=2,5 2006.285.12:55:00.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.12:55:00.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.12:55:00.30#ibcon#ireg 11 cls_cnt 2 2006.285.12:55:00.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:55:00.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:55:00.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:55:00.30#ibcon#enter wrdev, iclass 31, count 2 2006.285.12:55:00.30#ibcon#first serial, iclass 31, count 2 2006.285.12:55:00.30#ibcon#enter sib2, iclass 31, count 2 2006.285.12:55:00.30#ibcon#flushed, iclass 31, count 2 2006.285.12:55:00.30#ibcon#about to write, iclass 31, count 2 2006.285.12:55:00.30#ibcon#wrote, iclass 31, count 2 2006.285.12:55:00.30#ibcon#about to read 3, iclass 31, count 2 2006.285.12:55:00.32#ibcon#read 3, iclass 31, count 2 2006.285.12:55:00.32#ibcon#about to read 4, iclass 31, count 2 2006.285.12:55:00.32#ibcon#read 4, iclass 31, count 2 2006.285.12:55:00.32#ibcon#about to read 5, iclass 31, count 2 2006.285.12:55:00.32#ibcon#read 5, iclass 31, count 2 2006.285.12:55:00.32#ibcon#about to read 6, iclass 31, count 2 2006.285.12:55:00.32#ibcon#read 6, iclass 31, count 2 2006.285.12:55:00.32#ibcon#end of sib2, iclass 31, count 2 2006.285.12:55:00.32#ibcon#*mode == 0, iclass 31, count 2 2006.285.12:55:00.32#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.12:55:00.32#ibcon#[27=AT02-05\r\n] 2006.285.12:55:00.32#ibcon#*before write, iclass 31, count 2 2006.285.12:55:00.32#ibcon#enter sib2, iclass 31, count 2 2006.285.12:55:00.32#ibcon#flushed, iclass 31, count 2 2006.285.12:55:00.32#ibcon#about to write, iclass 31, count 2 2006.285.12:55:00.32#ibcon#wrote, iclass 31, count 2 2006.285.12:55:00.32#ibcon#about to read 3, iclass 31, count 2 2006.285.12:55:00.35#ibcon#read 3, iclass 31, count 2 2006.285.12:55:00.35#ibcon#about to read 4, iclass 31, count 2 2006.285.12:55:00.35#ibcon#read 4, iclass 31, count 2 2006.285.12:55:00.35#ibcon#about to read 5, iclass 31, count 2 2006.285.12:55:00.35#ibcon#read 5, iclass 31, count 2 2006.285.12:55:00.35#ibcon#about to read 6, iclass 31, count 2 2006.285.12:55:00.35#ibcon#read 6, iclass 31, count 2 2006.285.12:55:00.35#ibcon#end of sib2, iclass 31, count 2 2006.285.12:55:00.35#ibcon#*after write, iclass 31, count 2 2006.285.12:55:00.35#ibcon#*before return 0, iclass 31, count 2 2006.285.12:55:00.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:55:00.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.12:55:00.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.12:55:00.35#ibcon#ireg 7 cls_cnt 0 2006.285.12:55:00.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:55:00.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:55:00.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:55:00.47#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:55:00.47#ibcon#first serial, iclass 31, count 0 2006.285.12:55:00.47#ibcon#enter sib2, iclass 31, count 0 2006.285.12:55:00.47#ibcon#flushed, iclass 31, count 0 2006.285.12:55:00.47#ibcon#about to write, iclass 31, count 0 2006.285.12:55:00.47#ibcon#wrote, iclass 31, count 0 2006.285.12:55:00.47#ibcon#about to read 3, iclass 31, count 0 2006.285.12:55:00.49#ibcon#read 3, iclass 31, count 0 2006.285.12:55:00.49#ibcon#about to read 4, iclass 31, count 0 2006.285.12:55:00.49#ibcon#read 4, iclass 31, count 0 2006.285.12:55:00.49#ibcon#about to read 5, iclass 31, count 0 2006.285.12:55:00.49#ibcon#read 5, iclass 31, count 0 2006.285.12:55:00.49#ibcon#about to read 6, iclass 31, count 0 2006.285.12:55:00.49#ibcon#read 6, iclass 31, count 0 2006.285.12:55:00.49#ibcon#end of sib2, iclass 31, count 0 2006.285.12:55:00.49#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:55:00.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:55:00.49#ibcon#[27=USB\r\n] 2006.285.12:55:00.49#ibcon#*before write, iclass 31, count 0 2006.285.12:55:00.49#ibcon#enter sib2, iclass 31, count 0 2006.285.12:55:00.49#ibcon#flushed, iclass 31, count 0 2006.285.12:55:00.49#ibcon#about to write, iclass 31, count 0 2006.285.12:55:00.49#ibcon#wrote, iclass 31, count 0 2006.285.12:55:00.49#ibcon#about to read 3, iclass 31, count 0 2006.285.12:55:00.52#ibcon#read 3, iclass 31, count 0 2006.285.12:55:00.52#ibcon#about to read 4, iclass 31, count 0 2006.285.12:55:00.52#ibcon#read 4, iclass 31, count 0 2006.285.12:55:00.52#ibcon#about to read 5, iclass 31, count 0 2006.285.12:55:00.52#ibcon#read 5, iclass 31, count 0 2006.285.12:55:00.52#ibcon#about to read 6, iclass 31, count 0 2006.285.12:55:00.52#ibcon#read 6, iclass 31, count 0 2006.285.12:55:00.52#ibcon#end of sib2, iclass 31, count 0 2006.285.12:55:00.52#ibcon#*after write, iclass 31, count 0 2006.285.12:55:00.52#ibcon#*before return 0, iclass 31, count 0 2006.285.12:55:00.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:55:00.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.12:55:00.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:55:00.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:55:00.52$vck44/vblo=3,649.99 2006.285.12:55:00.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.12:55:00.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.12:55:00.52#ibcon#ireg 17 cls_cnt 0 2006.285.12:55:00.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:55:00.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:55:00.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:55:00.52#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:55:00.52#ibcon#first serial, iclass 33, count 0 2006.285.12:55:00.52#ibcon#enter sib2, iclass 33, count 0 2006.285.12:55:00.52#ibcon#flushed, iclass 33, count 0 2006.285.12:55:00.52#ibcon#about to write, iclass 33, count 0 2006.285.12:55:00.52#ibcon#wrote, iclass 33, count 0 2006.285.12:55:00.52#ibcon#about to read 3, iclass 33, count 0 2006.285.12:55:00.54#ibcon#read 3, iclass 33, count 0 2006.285.12:55:00.54#ibcon#about to read 4, iclass 33, count 0 2006.285.12:55:00.54#ibcon#read 4, iclass 33, count 0 2006.285.12:55:00.54#ibcon#about to read 5, iclass 33, count 0 2006.285.12:55:00.54#ibcon#read 5, iclass 33, count 0 2006.285.12:55:00.54#ibcon#about to read 6, iclass 33, count 0 2006.285.12:55:00.54#ibcon#read 6, iclass 33, count 0 2006.285.12:55:00.54#ibcon#end of sib2, iclass 33, count 0 2006.285.12:55:00.54#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:55:00.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:55:00.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.12:55:00.54#ibcon#*before write, iclass 33, count 0 2006.285.12:55:00.54#ibcon#enter sib2, iclass 33, count 0 2006.285.12:55:00.54#ibcon#flushed, iclass 33, count 0 2006.285.12:55:00.54#ibcon#about to write, iclass 33, count 0 2006.285.12:55:00.54#ibcon#wrote, iclass 33, count 0 2006.285.12:55:00.54#ibcon#about to read 3, iclass 33, count 0 2006.285.12:55:00.58#ibcon#read 3, iclass 33, count 0 2006.285.12:55:00.58#ibcon#about to read 4, iclass 33, count 0 2006.285.12:55:00.58#ibcon#read 4, iclass 33, count 0 2006.285.12:55:00.58#ibcon#about to read 5, iclass 33, count 0 2006.285.12:55:00.58#ibcon#read 5, iclass 33, count 0 2006.285.12:55:00.58#ibcon#about to read 6, iclass 33, count 0 2006.285.12:55:00.58#ibcon#read 6, iclass 33, count 0 2006.285.12:55:00.58#ibcon#end of sib2, iclass 33, count 0 2006.285.12:55:00.58#ibcon#*after write, iclass 33, count 0 2006.285.12:55:00.58#ibcon#*before return 0, iclass 33, count 0 2006.285.12:55:00.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:55:00.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:55:00.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:55:00.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:55:00.58$vck44/vb=3,4 2006.285.12:55:00.58#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.12:55:00.58#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.12:55:00.58#ibcon#ireg 11 cls_cnt 2 2006.285.12:55:00.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:55:00.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:55:00.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:55:00.64#ibcon#enter wrdev, iclass 35, count 2 2006.285.12:55:00.64#ibcon#first serial, iclass 35, count 2 2006.285.12:55:00.64#ibcon#enter sib2, iclass 35, count 2 2006.285.12:55:00.64#ibcon#flushed, iclass 35, count 2 2006.285.12:55:00.64#ibcon#about to write, iclass 35, count 2 2006.285.12:55:00.64#ibcon#wrote, iclass 35, count 2 2006.285.12:55:00.64#ibcon#about to read 3, iclass 35, count 2 2006.285.12:55:00.66#ibcon#read 3, iclass 35, count 2 2006.285.12:55:00.66#ibcon#about to read 4, iclass 35, count 2 2006.285.12:55:00.66#ibcon#read 4, iclass 35, count 2 2006.285.12:55:00.66#ibcon#about to read 5, iclass 35, count 2 2006.285.12:55:00.66#ibcon#read 5, iclass 35, count 2 2006.285.12:55:00.66#ibcon#about to read 6, iclass 35, count 2 2006.285.12:55:00.66#ibcon#read 6, iclass 35, count 2 2006.285.12:55:00.66#ibcon#end of sib2, iclass 35, count 2 2006.285.12:55:00.66#ibcon#*mode == 0, iclass 35, count 2 2006.285.12:55:00.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.12:55:00.66#ibcon#[27=AT03-04\r\n] 2006.285.12:55:00.66#ibcon#*before write, iclass 35, count 2 2006.285.12:55:00.66#ibcon#enter sib2, iclass 35, count 2 2006.285.12:55:00.66#ibcon#flushed, iclass 35, count 2 2006.285.12:55:00.66#ibcon#about to write, iclass 35, count 2 2006.285.12:55:00.66#ibcon#wrote, iclass 35, count 2 2006.285.12:55:00.66#ibcon#about to read 3, iclass 35, count 2 2006.285.12:55:00.69#ibcon#read 3, iclass 35, count 2 2006.285.12:55:00.69#ibcon#about to read 4, iclass 35, count 2 2006.285.12:55:00.69#ibcon#read 4, iclass 35, count 2 2006.285.12:55:00.69#ibcon#about to read 5, iclass 35, count 2 2006.285.12:55:00.69#ibcon#read 5, iclass 35, count 2 2006.285.12:55:00.69#ibcon#about to read 6, iclass 35, count 2 2006.285.12:55:00.69#ibcon#read 6, iclass 35, count 2 2006.285.12:55:00.69#ibcon#end of sib2, iclass 35, count 2 2006.285.12:55:00.69#ibcon#*after write, iclass 35, count 2 2006.285.12:55:00.69#ibcon#*before return 0, iclass 35, count 2 2006.285.12:55:00.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:55:00.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.12:55:00.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.12:55:00.69#ibcon#ireg 7 cls_cnt 0 2006.285.12:55:00.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:55:00.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:55:00.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:55:00.81#ibcon#enter wrdev, iclass 35, count 0 2006.285.12:55:00.81#ibcon#first serial, iclass 35, count 0 2006.285.12:55:00.81#ibcon#enter sib2, iclass 35, count 0 2006.285.12:55:00.81#ibcon#flushed, iclass 35, count 0 2006.285.12:55:00.81#ibcon#about to write, iclass 35, count 0 2006.285.12:55:00.81#ibcon#wrote, iclass 35, count 0 2006.285.12:55:00.81#ibcon#about to read 3, iclass 35, count 0 2006.285.12:55:00.83#ibcon#read 3, iclass 35, count 0 2006.285.12:55:00.83#ibcon#about to read 4, iclass 35, count 0 2006.285.12:55:00.83#ibcon#read 4, iclass 35, count 0 2006.285.12:55:00.83#ibcon#about to read 5, iclass 35, count 0 2006.285.12:55:00.83#ibcon#read 5, iclass 35, count 0 2006.285.12:55:00.83#ibcon#about to read 6, iclass 35, count 0 2006.285.12:55:00.83#ibcon#read 6, iclass 35, count 0 2006.285.12:55:00.83#ibcon#end of sib2, iclass 35, count 0 2006.285.12:55:00.83#ibcon#*mode == 0, iclass 35, count 0 2006.285.12:55:00.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.12:55:00.83#ibcon#[27=USB\r\n] 2006.285.12:55:00.83#ibcon#*before write, iclass 35, count 0 2006.285.12:55:00.83#ibcon#enter sib2, iclass 35, count 0 2006.285.12:55:00.83#ibcon#flushed, iclass 35, count 0 2006.285.12:55:00.83#ibcon#about to write, iclass 35, count 0 2006.285.12:55:00.83#ibcon#wrote, iclass 35, count 0 2006.285.12:55:00.83#ibcon#about to read 3, iclass 35, count 0 2006.285.12:55:00.86#ibcon#read 3, iclass 35, count 0 2006.285.12:55:00.86#ibcon#about to read 4, iclass 35, count 0 2006.285.12:55:00.86#ibcon#read 4, iclass 35, count 0 2006.285.12:55:00.86#ibcon#about to read 5, iclass 35, count 0 2006.285.12:55:00.86#ibcon#read 5, iclass 35, count 0 2006.285.12:55:00.86#ibcon#about to read 6, iclass 35, count 0 2006.285.12:55:00.86#ibcon#read 6, iclass 35, count 0 2006.285.12:55:00.86#ibcon#end of sib2, iclass 35, count 0 2006.285.12:55:00.86#ibcon#*after write, iclass 35, count 0 2006.285.12:55:00.86#ibcon#*before return 0, iclass 35, count 0 2006.285.12:55:00.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:55:00.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.12:55:00.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.12:55:00.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.12:55:00.86$vck44/vblo=4,679.99 2006.285.12:55:00.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.12:55:00.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.12:55:00.86#ibcon#ireg 17 cls_cnt 0 2006.285.12:55:00.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:55:00.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:55:00.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:55:00.86#ibcon#enter wrdev, iclass 37, count 0 2006.285.12:55:00.86#ibcon#first serial, iclass 37, count 0 2006.285.12:55:00.86#ibcon#enter sib2, iclass 37, count 0 2006.285.12:55:00.86#ibcon#flushed, iclass 37, count 0 2006.285.12:55:00.86#ibcon#about to write, iclass 37, count 0 2006.285.12:55:00.86#ibcon#wrote, iclass 37, count 0 2006.285.12:55:00.86#ibcon#about to read 3, iclass 37, count 0 2006.285.12:55:00.88#ibcon#read 3, iclass 37, count 0 2006.285.12:55:00.88#ibcon#about to read 4, iclass 37, count 0 2006.285.12:55:00.88#ibcon#read 4, iclass 37, count 0 2006.285.12:55:00.88#ibcon#about to read 5, iclass 37, count 0 2006.285.12:55:00.88#ibcon#read 5, iclass 37, count 0 2006.285.12:55:00.88#ibcon#about to read 6, iclass 37, count 0 2006.285.12:55:00.88#ibcon#read 6, iclass 37, count 0 2006.285.12:55:00.88#ibcon#end of sib2, iclass 37, count 0 2006.285.12:55:00.88#ibcon#*mode == 0, iclass 37, count 0 2006.285.12:55:00.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.12:55:00.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.12:55:00.88#ibcon#*before write, iclass 37, count 0 2006.285.12:55:00.88#ibcon#enter sib2, iclass 37, count 0 2006.285.12:55:00.88#ibcon#flushed, iclass 37, count 0 2006.285.12:55:00.88#ibcon#about to write, iclass 37, count 0 2006.285.12:55:00.88#ibcon#wrote, iclass 37, count 0 2006.285.12:55:00.88#ibcon#about to read 3, iclass 37, count 0 2006.285.12:55:00.92#ibcon#read 3, iclass 37, count 0 2006.285.12:55:00.92#ibcon#about to read 4, iclass 37, count 0 2006.285.12:55:00.92#ibcon#read 4, iclass 37, count 0 2006.285.12:55:00.92#ibcon#about to read 5, iclass 37, count 0 2006.285.12:55:00.92#ibcon#read 5, iclass 37, count 0 2006.285.12:55:00.92#ibcon#about to read 6, iclass 37, count 0 2006.285.12:55:00.92#ibcon#read 6, iclass 37, count 0 2006.285.12:55:00.92#ibcon#end of sib2, iclass 37, count 0 2006.285.12:55:00.92#ibcon#*after write, iclass 37, count 0 2006.285.12:55:00.92#ibcon#*before return 0, iclass 37, count 0 2006.285.12:55:00.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:55:00.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.12:55:00.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.12:55:00.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.12:55:00.92$vck44/vb=4,5 2006.285.12:55:00.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.12:55:00.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.12:55:00.92#ibcon#ireg 11 cls_cnt 2 2006.285.12:55:00.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:55:00.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:55:00.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:55:00.98#ibcon#enter wrdev, iclass 39, count 2 2006.285.12:55:00.98#ibcon#first serial, iclass 39, count 2 2006.285.12:55:00.98#ibcon#enter sib2, iclass 39, count 2 2006.285.12:55:00.98#ibcon#flushed, iclass 39, count 2 2006.285.12:55:00.98#ibcon#about to write, iclass 39, count 2 2006.285.12:55:00.98#ibcon#wrote, iclass 39, count 2 2006.285.12:55:00.98#ibcon#about to read 3, iclass 39, count 2 2006.285.12:55:01.00#ibcon#read 3, iclass 39, count 2 2006.285.12:55:01.00#ibcon#about to read 4, iclass 39, count 2 2006.285.12:55:01.00#ibcon#read 4, iclass 39, count 2 2006.285.12:55:01.00#ibcon#about to read 5, iclass 39, count 2 2006.285.12:55:01.00#ibcon#read 5, iclass 39, count 2 2006.285.12:55:01.00#ibcon#about to read 6, iclass 39, count 2 2006.285.12:55:01.00#ibcon#read 6, iclass 39, count 2 2006.285.12:55:01.00#ibcon#end of sib2, iclass 39, count 2 2006.285.12:55:01.00#ibcon#*mode == 0, iclass 39, count 2 2006.285.12:55:01.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.12:55:01.00#ibcon#[27=AT04-05\r\n] 2006.285.12:55:01.00#ibcon#*before write, iclass 39, count 2 2006.285.12:55:01.00#ibcon#enter sib2, iclass 39, count 2 2006.285.12:55:01.00#ibcon#flushed, iclass 39, count 2 2006.285.12:55:01.00#ibcon#about to write, iclass 39, count 2 2006.285.12:55:01.00#ibcon#wrote, iclass 39, count 2 2006.285.12:55:01.00#ibcon#about to read 3, iclass 39, count 2 2006.285.12:55:01.03#ibcon#read 3, iclass 39, count 2 2006.285.12:55:01.03#ibcon#about to read 4, iclass 39, count 2 2006.285.12:55:01.03#ibcon#read 4, iclass 39, count 2 2006.285.12:55:01.03#ibcon#about to read 5, iclass 39, count 2 2006.285.12:55:01.03#ibcon#read 5, iclass 39, count 2 2006.285.12:55:01.03#ibcon#about to read 6, iclass 39, count 2 2006.285.12:55:01.03#ibcon#read 6, iclass 39, count 2 2006.285.12:55:01.03#ibcon#end of sib2, iclass 39, count 2 2006.285.12:55:01.03#ibcon#*after write, iclass 39, count 2 2006.285.12:55:01.03#ibcon#*before return 0, iclass 39, count 2 2006.285.12:55:01.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:55:01.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.12:55:01.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.12:55:01.03#ibcon#ireg 7 cls_cnt 0 2006.285.12:55:01.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:55:01.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:55:01.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:55:01.15#ibcon#enter wrdev, iclass 39, count 0 2006.285.12:55:01.15#ibcon#first serial, iclass 39, count 0 2006.285.12:55:01.15#ibcon#enter sib2, iclass 39, count 0 2006.285.12:55:01.15#ibcon#flushed, iclass 39, count 0 2006.285.12:55:01.15#ibcon#about to write, iclass 39, count 0 2006.285.12:55:01.15#ibcon#wrote, iclass 39, count 0 2006.285.12:55:01.15#ibcon#about to read 3, iclass 39, count 0 2006.285.12:55:01.17#ibcon#read 3, iclass 39, count 0 2006.285.12:55:01.17#ibcon#about to read 4, iclass 39, count 0 2006.285.12:55:01.17#ibcon#read 4, iclass 39, count 0 2006.285.12:55:01.17#ibcon#about to read 5, iclass 39, count 0 2006.285.12:55:01.17#ibcon#read 5, iclass 39, count 0 2006.285.12:55:01.17#ibcon#about to read 6, iclass 39, count 0 2006.285.12:55:01.17#ibcon#read 6, iclass 39, count 0 2006.285.12:55:01.17#ibcon#end of sib2, iclass 39, count 0 2006.285.12:55:01.17#ibcon#*mode == 0, iclass 39, count 0 2006.285.12:55:01.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.12:55:01.17#ibcon#[27=USB\r\n] 2006.285.12:55:01.17#ibcon#*before write, iclass 39, count 0 2006.285.12:55:01.17#ibcon#enter sib2, iclass 39, count 0 2006.285.12:55:01.17#ibcon#flushed, iclass 39, count 0 2006.285.12:55:01.17#ibcon#about to write, iclass 39, count 0 2006.285.12:55:01.17#ibcon#wrote, iclass 39, count 0 2006.285.12:55:01.17#ibcon#about to read 3, iclass 39, count 0 2006.285.12:55:01.20#ibcon#read 3, iclass 39, count 0 2006.285.12:55:01.20#ibcon#about to read 4, iclass 39, count 0 2006.285.12:55:01.20#ibcon#read 4, iclass 39, count 0 2006.285.12:55:01.20#ibcon#about to read 5, iclass 39, count 0 2006.285.12:55:01.20#ibcon#read 5, iclass 39, count 0 2006.285.12:55:01.20#ibcon#about to read 6, iclass 39, count 0 2006.285.12:55:01.20#ibcon#read 6, iclass 39, count 0 2006.285.12:55:01.20#ibcon#end of sib2, iclass 39, count 0 2006.285.12:55:01.20#ibcon#*after write, iclass 39, count 0 2006.285.12:55:01.20#ibcon#*before return 0, iclass 39, count 0 2006.285.12:55:01.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:55:01.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.12:55:01.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.12:55:01.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.12:55:01.20$vck44/vblo=5,709.99 2006.285.12:55:01.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.12:55:01.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.12:55:01.20#ibcon#ireg 17 cls_cnt 0 2006.285.12:55:01.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:55:01.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:55:01.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:55:01.20#ibcon#enter wrdev, iclass 3, count 0 2006.285.12:55:01.20#ibcon#first serial, iclass 3, count 0 2006.285.12:55:01.20#ibcon#enter sib2, iclass 3, count 0 2006.285.12:55:01.20#ibcon#flushed, iclass 3, count 0 2006.285.12:55:01.20#ibcon#about to write, iclass 3, count 0 2006.285.12:55:01.20#ibcon#wrote, iclass 3, count 0 2006.285.12:55:01.20#ibcon#about to read 3, iclass 3, count 0 2006.285.12:55:01.22#ibcon#read 3, iclass 3, count 0 2006.285.12:55:01.22#ibcon#about to read 4, iclass 3, count 0 2006.285.12:55:01.22#ibcon#read 4, iclass 3, count 0 2006.285.12:55:01.22#ibcon#about to read 5, iclass 3, count 0 2006.285.12:55:01.22#ibcon#read 5, iclass 3, count 0 2006.285.12:55:01.22#ibcon#about to read 6, iclass 3, count 0 2006.285.12:55:01.22#ibcon#read 6, iclass 3, count 0 2006.285.12:55:01.22#ibcon#end of sib2, iclass 3, count 0 2006.285.12:55:01.22#ibcon#*mode == 0, iclass 3, count 0 2006.285.12:55:01.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.12:55:01.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.12:55:01.22#ibcon#*before write, iclass 3, count 0 2006.285.12:55:01.22#ibcon#enter sib2, iclass 3, count 0 2006.285.12:55:01.22#ibcon#flushed, iclass 3, count 0 2006.285.12:55:01.22#ibcon#about to write, iclass 3, count 0 2006.285.12:55:01.22#ibcon#wrote, iclass 3, count 0 2006.285.12:55:01.22#ibcon#about to read 3, iclass 3, count 0 2006.285.12:55:01.26#ibcon#read 3, iclass 3, count 0 2006.285.12:55:01.26#ibcon#about to read 4, iclass 3, count 0 2006.285.12:55:01.26#ibcon#read 4, iclass 3, count 0 2006.285.12:55:01.26#ibcon#about to read 5, iclass 3, count 0 2006.285.12:55:01.26#ibcon#read 5, iclass 3, count 0 2006.285.12:55:01.26#ibcon#about to read 6, iclass 3, count 0 2006.285.12:55:01.26#ibcon#read 6, iclass 3, count 0 2006.285.12:55:01.26#ibcon#end of sib2, iclass 3, count 0 2006.285.12:55:01.26#ibcon#*after write, iclass 3, count 0 2006.285.12:55:01.26#ibcon#*before return 0, iclass 3, count 0 2006.285.12:55:01.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:55:01.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.12:55:01.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.12:55:01.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.12:55:01.26$vck44/vb=5,4 2006.285.12:55:01.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.12:55:01.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.12:55:01.26#ibcon#ireg 11 cls_cnt 2 2006.285.12:55:01.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:55:01.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:55:01.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:55:01.32#ibcon#enter wrdev, iclass 5, count 2 2006.285.12:55:01.32#ibcon#first serial, iclass 5, count 2 2006.285.12:55:01.32#ibcon#enter sib2, iclass 5, count 2 2006.285.12:55:01.32#ibcon#flushed, iclass 5, count 2 2006.285.12:55:01.32#ibcon#about to write, iclass 5, count 2 2006.285.12:55:01.32#ibcon#wrote, iclass 5, count 2 2006.285.12:55:01.32#ibcon#about to read 3, iclass 5, count 2 2006.285.12:55:01.34#ibcon#read 3, iclass 5, count 2 2006.285.12:55:01.34#ibcon#about to read 4, iclass 5, count 2 2006.285.12:55:01.34#ibcon#read 4, iclass 5, count 2 2006.285.12:55:01.34#ibcon#about to read 5, iclass 5, count 2 2006.285.12:55:01.34#ibcon#read 5, iclass 5, count 2 2006.285.12:55:01.34#ibcon#about to read 6, iclass 5, count 2 2006.285.12:55:01.34#ibcon#read 6, iclass 5, count 2 2006.285.12:55:01.34#ibcon#end of sib2, iclass 5, count 2 2006.285.12:55:01.34#ibcon#*mode == 0, iclass 5, count 2 2006.285.12:55:01.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.12:55:01.34#ibcon#[27=AT05-04\r\n] 2006.285.12:55:01.34#ibcon#*before write, iclass 5, count 2 2006.285.12:55:01.34#ibcon#enter sib2, iclass 5, count 2 2006.285.12:55:01.34#ibcon#flushed, iclass 5, count 2 2006.285.12:55:01.34#ibcon#about to write, iclass 5, count 2 2006.285.12:55:01.34#ibcon#wrote, iclass 5, count 2 2006.285.12:55:01.34#ibcon#about to read 3, iclass 5, count 2 2006.285.12:55:01.37#ibcon#read 3, iclass 5, count 2 2006.285.12:55:01.37#ibcon#about to read 4, iclass 5, count 2 2006.285.12:55:01.37#ibcon#read 4, iclass 5, count 2 2006.285.12:55:01.37#ibcon#about to read 5, iclass 5, count 2 2006.285.12:55:01.37#ibcon#read 5, iclass 5, count 2 2006.285.12:55:01.37#ibcon#about to read 6, iclass 5, count 2 2006.285.12:55:01.37#ibcon#read 6, iclass 5, count 2 2006.285.12:55:01.37#ibcon#end of sib2, iclass 5, count 2 2006.285.12:55:01.37#ibcon#*after write, iclass 5, count 2 2006.285.12:55:01.37#ibcon#*before return 0, iclass 5, count 2 2006.285.12:55:01.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:55:01.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.12:55:01.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.12:55:01.37#ibcon#ireg 7 cls_cnt 0 2006.285.12:55:01.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:55:01.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:55:01.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:55:01.49#ibcon#enter wrdev, iclass 5, count 0 2006.285.12:55:01.49#ibcon#first serial, iclass 5, count 0 2006.285.12:55:01.49#ibcon#enter sib2, iclass 5, count 0 2006.285.12:55:01.49#ibcon#flushed, iclass 5, count 0 2006.285.12:55:01.49#ibcon#about to write, iclass 5, count 0 2006.285.12:55:01.49#ibcon#wrote, iclass 5, count 0 2006.285.12:55:01.49#ibcon#about to read 3, iclass 5, count 0 2006.285.12:55:01.51#ibcon#read 3, iclass 5, count 0 2006.285.12:55:01.51#ibcon#about to read 4, iclass 5, count 0 2006.285.12:55:01.51#ibcon#read 4, iclass 5, count 0 2006.285.12:55:01.51#ibcon#about to read 5, iclass 5, count 0 2006.285.12:55:01.51#ibcon#read 5, iclass 5, count 0 2006.285.12:55:01.51#ibcon#about to read 6, iclass 5, count 0 2006.285.12:55:01.51#ibcon#read 6, iclass 5, count 0 2006.285.12:55:01.51#ibcon#end of sib2, iclass 5, count 0 2006.285.12:55:01.51#ibcon#*mode == 0, iclass 5, count 0 2006.285.12:55:01.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.12:55:01.51#ibcon#[27=USB\r\n] 2006.285.12:55:01.51#ibcon#*before write, iclass 5, count 0 2006.285.12:55:01.51#ibcon#enter sib2, iclass 5, count 0 2006.285.12:55:01.51#ibcon#flushed, iclass 5, count 0 2006.285.12:55:01.51#ibcon#about to write, iclass 5, count 0 2006.285.12:55:01.51#ibcon#wrote, iclass 5, count 0 2006.285.12:55:01.51#ibcon#about to read 3, iclass 5, count 0 2006.285.12:55:01.54#ibcon#read 3, iclass 5, count 0 2006.285.12:55:01.54#ibcon#about to read 4, iclass 5, count 0 2006.285.12:55:01.54#ibcon#read 4, iclass 5, count 0 2006.285.12:55:01.54#ibcon#about to read 5, iclass 5, count 0 2006.285.12:55:01.54#ibcon#read 5, iclass 5, count 0 2006.285.12:55:01.54#ibcon#about to read 6, iclass 5, count 0 2006.285.12:55:01.54#ibcon#read 6, iclass 5, count 0 2006.285.12:55:01.54#ibcon#end of sib2, iclass 5, count 0 2006.285.12:55:01.54#ibcon#*after write, iclass 5, count 0 2006.285.12:55:01.54#ibcon#*before return 0, iclass 5, count 0 2006.285.12:55:01.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:55:01.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.12:55:01.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.12:55:01.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.12:55:01.54$vck44/vblo=6,719.99 2006.285.12:55:01.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.12:55:01.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.12:55:01.54#ibcon#ireg 17 cls_cnt 0 2006.285.12:55:01.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:55:01.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:55:01.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:55:01.54#ibcon#enter wrdev, iclass 7, count 0 2006.285.12:55:01.54#ibcon#first serial, iclass 7, count 0 2006.285.12:55:01.54#ibcon#enter sib2, iclass 7, count 0 2006.285.12:55:01.54#ibcon#flushed, iclass 7, count 0 2006.285.12:55:01.54#ibcon#about to write, iclass 7, count 0 2006.285.12:55:01.54#ibcon#wrote, iclass 7, count 0 2006.285.12:55:01.54#ibcon#about to read 3, iclass 7, count 0 2006.285.12:55:01.56#ibcon#read 3, iclass 7, count 0 2006.285.12:55:01.56#ibcon#about to read 4, iclass 7, count 0 2006.285.12:55:01.56#ibcon#read 4, iclass 7, count 0 2006.285.12:55:01.56#ibcon#about to read 5, iclass 7, count 0 2006.285.12:55:01.56#ibcon#read 5, iclass 7, count 0 2006.285.12:55:01.56#ibcon#about to read 6, iclass 7, count 0 2006.285.12:55:01.56#ibcon#read 6, iclass 7, count 0 2006.285.12:55:01.56#ibcon#end of sib2, iclass 7, count 0 2006.285.12:55:01.56#ibcon#*mode == 0, iclass 7, count 0 2006.285.12:55:01.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.12:55:01.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.12:55:01.56#ibcon#*before write, iclass 7, count 0 2006.285.12:55:01.56#ibcon#enter sib2, iclass 7, count 0 2006.285.12:55:01.56#ibcon#flushed, iclass 7, count 0 2006.285.12:55:01.56#ibcon#about to write, iclass 7, count 0 2006.285.12:55:01.56#ibcon#wrote, iclass 7, count 0 2006.285.12:55:01.56#ibcon#about to read 3, iclass 7, count 0 2006.285.12:55:01.60#ibcon#read 3, iclass 7, count 0 2006.285.12:55:01.60#ibcon#about to read 4, iclass 7, count 0 2006.285.12:55:01.60#ibcon#read 4, iclass 7, count 0 2006.285.12:55:01.60#ibcon#about to read 5, iclass 7, count 0 2006.285.12:55:01.60#ibcon#read 5, iclass 7, count 0 2006.285.12:55:01.60#ibcon#about to read 6, iclass 7, count 0 2006.285.12:55:01.60#ibcon#read 6, iclass 7, count 0 2006.285.12:55:01.60#ibcon#end of sib2, iclass 7, count 0 2006.285.12:55:01.60#ibcon#*after write, iclass 7, count 0 2006.285.12:55:01.60#ibcon#*before return 0, iclass 7, count 0 2006.285.12:55:01.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:55:01.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.12:55:01.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.12:55:01.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.12:55:01.60$vck44/vb=6,3 2006.285.12:55:01.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.12:55:01.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.12:55:01.60#ibcon#ireg 11 cls_cnt 2 2006.285.12:55:01.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:55:01.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:55:01.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:55:01.66#ibcon#enter wrdev, iclass 11, count 2 2006.285.12:55:01.66#ibcon#first serial, iclass 11, count 2 2006.285.12:55:01.66#ibcon#enter sib2, iclass 11, count 2 2006.285.12:55:01.66#ibcon#flushed, iclass 11, count 2 2006.285.12:55:01.66#ibcon#about to write, iclass 11, count 2 2006.285.12:55:01.66#ibcon#wrote, iclass 11, count 2 2006.285.12:55:01.66#ibcon#about to read 3, iclass 11, count 2 2006.285.12:55:01.68#ibcon#read 3, iclass 11, count 2 2006.285.12:55:01.68#ibcon#about to read 4, iclass 11, count 2 2006.285.12:55:01.68#ibcon#read 4, iclass 11, count 2 2006.285.12:55:01.68#ibcon#about to read 5, iclass 11, count 2 2006.285.12:55:01.68#ibcon#read 5, iclass 11, count 2 2006.285.12:55:01.68#ibcon#about to read 6, iclass 11, count 2 2006.285.12:55:01.68#ibcon#read 6, iclass 11, count 2 2006.285.12:55:01.68#ibcon#end of sib2, iclass 11, count 2 2006.285.12:55:01.68#ibcon#*mode == 0, iclass 11, count 2 2006.285.12:55:01.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.12:55:01.68#ibcon#[27=AT06-03\r\n] 2006.285.12:55:01.68#ibcon#*before write, iclass 11, count 2 2006.285.12:55:01.68#ibcon#enter sib2, iclass 11, count 2 2006.285.12:55:01.68#ibcon#flushed, iclass 11, count 2 2006.285.12:55:01.68#ibcon#about to write, iclass 11, count 2 2006.285.12:55:01.68#ibcon#wrote, iclass 11, count 2 2006.285.12:55:01.68#ibcon#about to read 3, iclass 11, count 2 2006.285.12:55:01.71#ibcon#read 3, iclass 11, count 2 2006.285.12:55:01.71#ibcon#about to read 4, iclass 11, count 2 2006.285.12:55:01.71#ibcon#read 4, iclass 11, count 2 2006.285.12:55:01.71#ibcon#about to read 5, iclass 11, count 2 2006.285.12:55:01.71#ibcon#read 5, iclass 11, count 2 2006.285.12:55:01.71#ibcon#about to read 6, iclass 11, count 2 2006.285.12:55:01.71#ibcon#read 6, iclass 11, count 2 2006.285.12:55:01.71#ibcon#end of sib2, iclass 11, count 2 2006.285.12:55:01.71#ibcon#*after write, iclass 11, count 2 2006.285.12:55:01.71#ibcon#*before return 0, iclass 11, count 2 2006.285.12:55:01.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:55:01.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.12:55:01.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.12:55:01.71#ibcon#ireg 7 cls_cnt 0 2006.285.12:55:01.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:55:01.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:55:01.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:55:01.83#ibcon#enter wrdev, iclass 11, count 0 2006.285.12:55:01.83#ibcon#first serial, iclass 11, count 0 2006.285.12:55:01.83#ibcon#enter sib2, iclass 11, count 0 2006.285.12:55:01.83#ibcon#flushed, iclass 11, count 0 2006.285.12:55:01.83#ibcon#about to write, iclass 11, count 0 2006.285.12:55:01.83#ibcon#wrote, iclass 11, count 0 2006.285.12:55:01.83#ibcon#about to read 3, iclass 11, count 0 2006.285.12:55:01.85#ibcon#read 3, iclass 11, count 0 2006.285.12:55:01.85#ibcon#about to read 4, iclass 11, count 0 2006.285.12:55:01.85#ibcon#read 4, iclass 11, count 0 2006.285.12:55:01.85#ibcon#about to read 5, iclass 11, count 0 2006.285.12:55:01.85#ibcon#read 5, iclass 11, count 0 2006.285.12:55:01.85#ibcon#about to read 6, iclass 11, count 0 2006.285.12:55:01.85#ibcon#read 6, iclass 11, count 0 2006.285.12:55:01.85#ibcon#end of sib2, iclass 11, count 0 2006.285.12:55:01.85#ibcon#*mode == 0, iclass 11, count 0 2006.285.12:55:01.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.12:55:01.85#ibcon#[27=USB\r\n] 2006.285.12:55:01.85#ibcon#*before write, iclass 11, count 0 2006.285.12:55:01.85#ibcon#enter sib2, iclass 11, count 0 2006.285.12:55:01.85#ibcon#flushed, iclass 11, count 0 2006.285.12:55:01.85#ibcon#about to write, iclass 11, count 0 2006.285.12:55:01.85#ibcon#wrote, iclass 11, count 0 2006.285.12:55:01.85#ibcon#about to read 3, iclass 11, count 0 2006.285.12:55:01.88#ibcon#read 3, iclass 11, count 0 2006.285.12:55:01.88#ibcon#about to read 4, iclass 11, count 0 2006.285.12:55:01.88#ibcon#read 4, iclass 11, count 0 2006.285.12:55:01.88#ibcon#about to read 5, iclass 11, count 0 2006.285.12:55:01.88#ibcon#read 5, iclass 11, count 0 2006.285.12:55:01.88#ibcon#about to read 6, iclass 11, count 0 2006.285.12:55:01.88#ibcon#read 6, iclass 11, count 0 2006.285.12:55:01.88#ibcon#end of sib2, iclass 11, count 0 2006.285.12:55:01.88#ibcon#*after write, iclass 11, count 0 2006.285.12:55:01.88#ibcon#*before return 0, iclass 11, count 0 2006.285.12:55:01.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:55:01.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.12:55:01.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.12:55:01.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.12:55:01.88$vck44/vblo=7,734.99 2006.285.12:55:01.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.12:55:01.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.12:55:01.88#ibcon#ireg 17 cls_cnt 0 2006.285.12:55:01.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:55:01.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:55:01.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:55:01.88#ibcon#enter wrdev, iclass 13, count 0 2006.285.12:55:01.88#ibcon#first serial, iclass 13, count 0 2006.285.12:55:01.88#ibcon#enter sib2, iclass 13, count 0 2006.285.12:55:01.88#ibcon#flushed, iclass 13, count 0 2006.285.12:55:01.88#ibcon#about to write, iclass 13, count 0 2006.285.12:55:01.88#ibcon#wrote, iclass 13, count 0 2006.285.12:55:01.88#ibcon#about to read 3, iclass 13, count 0 2006.285.12:55:01.90#ibcon#read 3, iclass 13, count 0 2006.285.12:55:01.90#ibcon#about to read 4, iclass 13, count 0 2006.285.12:55:01.90#ibcon#read 4, iclass 13, count 0 2006.285.12:55:01.90#ibcon#about to read 5, iclass 13, count 0 2006.285.12:55:01.90#ibcon#read 5, iclass 13, count 0 2006.285.12:55:01.90#ibcon#about to read 6, iclass 13, count 0 2006.285.12:55:01.90#ibcon#read 6, iclass 13, count 0 2006.285.12:55:01.90#ibcon#end of sib2, iclass 13, count 0 2006.285.12:55:01.90#ibcon#*mode == 0, iclass 13, count 0 2006.285.12:55:01.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.12:55:01.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.12:55:01.90#ibcon#*before write, iclass 13, count 0 2006.285.12:55:01.90#ibcon#enter sib2, iclass 13, count 0 2006.285.12:55:01.90#ibcon#flushed, iclass 13, count 0 2006.285.12:55:01.90#ibcon#about to write, iclass 13, count 0 2006.285.12:55:01.90#ibcon#wrote, iclass 13, count 0 2006.285.12:55:01.90#ibcon#about to read 3, iclass 13, count 0 2006.285.12:55:01.94#ibcon#read 3, iclass 13, count 0 2006.285.12:55:01.94#ibcon#about to read 4, iclass 13, count 0 2006.285.12:55:01.94#ibcon#read 4, iclass 13, count 0 2006.285.12:55:01.94#ibcon#about to read 5, iclass 13, count 0 2006.285.12:55:01.94#ibcon#read 5, iclass 13, count 0 2006.285.12:55:01.94#ibcon#about to read 6, iclass 13, count 0 2006.285.12:55:01.94#ibcon#read 6, iclass 13, count 0 2006.285.12:55:01.94#ibcon#end of sib2, iclass 13, count 0 2006.285.12:55:01.94#ibcon#*after write, iclass 13, count 0 2006.285.12:55:01.94#ibcon#*before return 0, iclass 13, count 0 2006.285.12:55:01.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:55:01.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.12:55:01.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.12:55:01.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.12:55:01.94$vck44/vb=7,4 2006.285.12:55:01.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.12:55:01.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.12:55:01.94#ibcon#ireg 11 cls_cnt 2 2006.285.12:55:01.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:55:02.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:55:02.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:55:02.00#ibcon#enter wrdev, iclass 15, count 2 2006.285.12:55:02.00#ibcon#first serial, iclass 15, count 2 2006.285.12:55:02.00#ibcon#enter sib2, iclass 15, count 2 2006.285.12:55:02.00#ibcon#flushed, iclass 15, count 2 2006.285.12:55:02.00#ibcon#about to write, iclass 15, count 2 2006.285.12:55:02.00#ibcon#wrote, iclass 15, count 2 2006.285.12:55:02.00#ibcon#about to read 3, iclass 15, count 2 2006.285.12:55:02.02#ibcon#read 3, iclass 15, count 2 2006.285.12:55:02.02#ibcon#about to read 4, iclass 15, count 2 2006.285.12:55:02.02#ibcon#read 4, iclass 15, count 2 2006.285.12:55:02.02#ibcon#about to read 5, iclass 15, count 2 2006.285.12:55:02.02#ibcon#read 5, iclass 15, count 2 2006.285.12:55:02.02#ibcon#about to read 6, iclass 15, count 2 2006.285.12:55:02.02#ibcon#read 6, iclass 15, count 2 2006.285.12:55:02.02#ibcon#end of sib2, iclass 15, count 2 2006.285.12:55:02.02#ibcon#*mode == 0, iclass 15, count 2 2006.285.12:55:02.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.12:55:02.02#ibcon#[27=AT07-04\r\n] 2006.285.12:55:02.02#ibcon#*before write, iclass 15, count 2 2006.285.12:55:02.02#ibcon#enter sib2, iclass 15, count 2 2006.285.12:55:02.02#ibcon#flushed, iclass 15, count 2 2006.285.12:55:02.02#ibcon#about to write, iclass 15, count 2 2006.285.12:55:02.02#ibcon#wrote, iclass 15, count 2 2006.285.12:55:02.02#ibcon#about to read 3, iclass 15, count 2 2006.285.12:55:02.05#ibcon#read 3, iclass 15, count 2 2006.285.12:55:02.05#ibcon#about to read 4, iclass 15, count 2 2006.285.12:55:02.05#ibcon#read 4, iclass 15, count 2 2006.285.12:55:02.05#ibcon#about to read 5, iclass 15, count 2 2006.285.12:55:02.05#ibcon#read 5, iclass 15, count 2 2006.285.12:55:02.05#ibcon#about to read 6, iclass 15, count 2 2006.285.12:55:02.05#ibcon#read 6, iclass 15, count 2 2006.285.12:55:02.05#ibcon#end of sib2, iclass 15, count 2 2006.285.12:55:02.05#ibcon#*after write, iclass 15, count 2 2006.285.12:55:02.05#ibcon#*before return 0, iclass 15, count 2 2006.285.12:55:02.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:55:02.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.12:55:02.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.12:55:02.05#ibcon#ireg 7 cls_cnt 0 2006.285.12:55:02.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:55:02.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:55:02.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:55:02.17#ibcon#enter wrdev, iclass 15, count 0 2006.285.12:55:02.17#ibcon#first serial, iclass 15, count 0 2006.285.12:55:02.17#ibcon#enter sib2, iclass 15, count 0 2006.285.12:55:02.17#ibcon#flushed, iclass 15, count 0 2006.285.12:55:02.17#ibcon#about to write, iclass 15, count 0 2006.285.12:55:02.17#ibcon#wrote, iclass 15, count 0 2006.285.12:55:02.17#ibcon#about to read 3, iclass 15, count 0 2006.285.12:55:02.19#ibcon#read 3, iclass 15, count 0 2006.285.12:55:02.19#ibcon#about to read 4, iclass 15, count 0 2006.285.12:55:02.19#ibcon#read 4, iclass 15, count 0 2006.285.12:55:02.19#ibcon#about to read 5, iclass 15, count 0 2006.285.12:55:02.19#ibcon#read 5, iclass 15, count 0 2006.285.12:55:02.19#ibcon#about to read 6, iclass 15, count 0 2006.285.12:55:02.19#ibcon#read 6, iclass 15, count 0 2006.285.12:55:02.19#ibcon#end of sib2, iclass 15, count 0 2006.285.12:55:02.19#ibcon#*mode == 0, iclass 15, count 0 2006.285.12:55:02.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.12:55:02.19#ibcon#[27=USB\r\n] 2006.285.12:55:02.19#ibcon#*before write, iclass 15, count 0 2006.285.12:55:02.19#ibcon#enter sib2, iclass 15, count 0 2006.285.12:55:02.19#ibcon#flushed, iclass 15, count 0 2006.285.12:55:02.19#ibcon#about to write, iclass 15, count 0 2006.285.12:55:02.19#ibcon#wrote, iclass 15, count 0 2006.285.12:55:02.19#ibcon#about to read 3, iclass 15, count 0 2006.285.12:55:02.22#ibcon#read 3, iclass 15, count 0 2006.285.12:55:02.22#ibcon#about to read 4, iclass 15, count 0 2006.285.12:55:02.22#ibcon#read 4, iclass 15, count 0 2006.285.12:55:02.22#ibcon#about to read 5, iclass 15, count 0 2006.285.12:55:02.22#ibcon#read 5, iclass 15, count 0 2006.285.12:55:02.22#ibcon#about to read 6, iclass 15, count 0 2006.285.12:55:02.22#ibcon#read 6, iclass 15, count 0 2006.285.12:55:02.22#ibcon#end of sib2, iclass 15, count 0 2006.285.12:55:02.22#ibcon#*after write, iclass 15, count 0 2006.285.12:55:02.22#ibcon#*before return 0, iclass 15, count 0 2006.285.12:55:02.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:55:02.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.12:55:02.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.12:55:02.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.12:55:02.22$vck44/vblo=8,744.99 2006.285.12:55:02.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.12:55:02.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.12:55:02.22#ibcon#ireg 17 cls_cnt 0 2006.285.12:55:02.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:55:02.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:55:02.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:55:02.22#ibcon#enter wrdev, iclass 18, count 0 2006.285.12:55:02.22#ibcon#first serial, iclass 18, count 0 2006.285.12:55:02.22#ibcon#enter sib2, iclass 18, count 0 2006.285.12:55:02.22#ibcon#flushed, iclass 18, count 0 2006.285.12:55:02.22#ibcon#about to write, iclass 18, count 0 2006.285.12:55:02.22#ibcon#wrote, iclass 18, count 0 2006.285.12:55:02.22#ibcon#about to read 3, iclass 18, count 0 2006.285.12:55:02.24#ibcon#read 3, iclass 18, count 0 2006.285.12:55:02.29#ibcon#about to read 4, iclass 18, count 0 2006.285.12:55:02.29#ibcon#read 4, iclass 18, count 0 2006.285.12:55:02.29#ibcon#about to read 5, iclass 18, count 0 2006.285.12:55:02.29#ibcon#read 5, iclass 18, count 0 2006.285.12:55:02.29#ibcon#about to read 6, iclass 18, count 0 2006.285.12:55:02.29#ibcon#read 6, iclass 18, count 0 2006.285.12:55:02.29#ibcon#end of sib2, iclass 18, count 0 2006.285.12:55:02.29#ibcon#*mode == 0, iclass 18, count 0 2006.285.12:55:02.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.12:55:02.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.12:55:02.29#ibcon#*before write, iclass 18, count 0 2006.285.12:55:02.29#ibcon#enter sib2, iclass 18, count 0 2006.285.12:55:02.29#ibcon#flushed, iclass 18, count 0 2006.285.12:55:02.29#ibcon#about to write, iclass 18, count 0 2006.285.12:55:02.29#ibcon#wrote, iclass 18, count 0 2006.285.12:55:02.29#ibcon#about to read 3, iclass 18, count 0 2006.285.12:55:02.25#abcon#<5=/04 1.3 3.1 18.96 961015.5\r\n> 2006.285.12:55:02.31#abcon#{5=INTERFACE CLEAR} 2006.285.12:55:02.34#ibcon#read 3, iclass 18, count 0 2006.285.12:55:02.34#ibcon#about to read 4, iclass 18, count 0 2006.285.12:55:02.34#ibcon#read 4, iclass 18, count 0 2006.285.12:55:02.34#ibcon#about to read 5, iclass 18, count 0 2006.285.12:55:02.34#ibcon#read 5, iclass 18, count 0 2006.285.12:55:02.34#ibcon#about to read 6, iclass 18, count 0 2006.285.12:55:02.34#ibcon#read 6, iclass 18, count 0 2006.285.12:55:02.34#ibcon#end of sib2, iclass 18, count 0 2006.285.12:55:02.34#ibcon#*after write, iclass 18, count 0 2006.285.12:55:02.34#ibcon#*before return 0, iclass 18, count 0 2006.285.12:55:02.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:55:02.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.12:55:02.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.12:55:02.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.12:55:02.34$vck44/vb=8,4 2006.285.12:55:02.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.12:55:02.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.12:55:02.34#ibcon#ireg 11 cls_cnt 2 2006.285.12:55:02.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:55:02.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:55:02.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:55:02.34#ibcon#enter wrdev, iclass 22, count 2 2006.285.12:55:02.34#ibcon#first serial, iclass 22, count 2 2006.285.12:55:02.34#ibcon#enter sib2, iclass 22, count 2 2006.285.12:55:02.34#ibcon#flushed, iclass 22, count 2 2006.285.12:55:02.34#ibcon#about to write, iclass 22, count 2 2006.285.12:55:02.34#ibcon#wrote, iclass 22, count 2 2006.285.12:55:02.34#ibcon#about to read 3, iclass 22, count 2 2006.285.12:55:02.36#ibcon#read 3, iclass 22, count 2 2006.285.12:55:02.36#ibcon#about to read 4, iclass 22, count 2 2006.285.12:55:02.36#ibcon#read 4, iclass 22, count 2 2006.285.12:55:02.36#ibcon#about to read 5, iclass 22, count 2 2006.285.12:55:02.36#ibcon#read 5, iclass 22, count 2 2006.285.12:55:02.36#ibcon#about to read 6, iclass 22, count 2 2006.285.12:55:02.36#ibcon#read 6, iclass 22, count 2 2006.285.12:55:02.36#ibcon#end of sib2, iclass 22, count 2 2006.285.12:55:02.36#ibcon#*mode == 0, iclass 22, count 2 2006.285.12:55:02.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.12:55:02.36#ibcon#[27=AT08-04\r\n] 2006.285.12:55:02.36#ibcon#*before write, iclass 22, count 2 2006.285.12:55:02.36#ibcon#enter sib2, iclass 22, count 2 2006.285.12:55:02.36#ibcon#flushed, iclass 22, count 2 2006.285.12:55:02.36#ibcon#about to write, iclass 22, count 2 2006.285.12:55:02.36#ibcon#wrote, iclass 22, count 2 2006.285.12:55:02.36#ibcon#about to read 3, iclass 22, count 2 2006.285.12:55:02.37#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:55:02.39#ibcon#read 3, iclass 22, count 2 2006.285.12:55:02.39#ibcon#about to read 4, iclass 22, count 2 2006.285.12:55:02.39#ibcon#read 4, iclass 22, count 2 2006.285.12:55:02.39#ibcon#about to read 5, iclass 22, count 2 2006.285.12:55:02.39#ibcon#read 5, iclass 22, count 2 2006.285.12:55:02.39#ibcon#about to read 6, iclass 22, count 2 2006.285.12:55:02.39#ibcon#read 6, iclass 22, count 2 2006.285.12:55:02.39#ibcon#end of sib2, iclass 22, count 2 2006.285.12:55:02.39#ibcon#*after write, iclass 22, count 2 2006.285.12:55:02.39#ibcon#*before return 0, iclass 22, count 2 2006.285.12:55:02.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:55:02.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:55:02.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.12:55:02.39#ibcon#ireg 7 cls_cnt 0 2006.285.12:55:02.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:55:02.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:55:02.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:55:02.51#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:55:02.51#ibcon#first serial, iclass 22, count 0 2006.285.12:55:02.51#ibcon#enter sib2, iclass 22, count 0 2006.285.12:55:02.51#ibcon#flushed, iclass 22, count 0 2006.285.12:55:02.51#ibcon#about to write, iclass 22, count 0 2006.285.12:55:02.51#ibcon#wrote, iclass 22, count 0 2006.285.12:55:02.51#ibcon#about to read 3, iclass 22, count 0 2006.285.12:55:02.53#ibcon#read 3, iclass 22, count 0 2006.285.12:55:02.53#ibcon#about to read 4, iclass 22, count 0 2006.285.12:55:02.53#ibcon#read 4, iclass 22, count 0 2006.285.12:55:02.53#ibcon#about to read 5, iclass 22, count 0 2006.285.12:55:02.53#ibcon#read 5, iclass 22, count 0 2006.285.12:55:02.53#ibcon#about to read 6, iclass 22, count 0 2006.285.12:55:02.53#ibcon#read 6, iclass 22, count 0 2006.285.12:55:02.53#ibcon#end of sib2, iclass 22, count 0 2006.285.12:55:02.53#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:55:02.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:55:02.53#ibcon#[27=USB\r\n] 2006.285.12:55:02.53#ibcon#*before write, iclass 22, count 0 2006.285.12:55:02.53#ibcon#enter sib2, iclass 22, count 0 2006.285.12:55:02.53#ibcon#flushed, iclass 22, count 0 2006.285.12:55:02.53#ibcon#about to write, iclass 22, count 0 2006.285.12:55:02.53#ibcon#wrote, iclass 22, count 0 2006.285.12:55:02.53#ibcon#about to read 3, iclass 22, count 0 2006.285.12:55:02.56#ibcon#read 3, iclass 22, count 0 2006.285.12:55:02.56#ibcon#about to read 4, iclass 22, count 0 2006.285.12:55:02.56#ibcon#read 4, iclass 22, count 0 2006.285.12:55:02.56#ibcon#about to read 5, iclass 22, count 0 2006.285.12:55:02.56#ibcon#read 5, iclass 22, count 0 2006.285.12:55:02.56#ibcon#about to read 6, iclass 22, count 0 2006.285.12:55:02.56#ibcon#read 6, iclass 22, count 0 2006.285.12:55:02.56#ibcon#end of sib2, iclass 22, count 0 2006.285.12:55:02.56#ibcon#*after write, iclass 22, count 0 2006.285.12:55:02.56#ibcon#*before return 0, iclass 22, count 0 2006.285.12:55:02.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:55:02.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:55:02.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:55:02.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:55:02.56$vck44/vabw=wide 2006.285.12:55:02.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.12:55:02.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.12:55:02.56#ibcon#ireg 8 cls_cnt 0 2006.285.12:55:02.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:55:02.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:55:02.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:55:02.56#ibcon#enter wrdev, iclass 25, count 0 2006.285.12:55:02.56#ibcon#first serial, iclass 25, count 0 2006.285.12:55:02.56#ibcon#enter sib2, iclass 25, count 0 2006.285.12:55:02.56#ibcon#flushed, iclass 25, count 0 2006.285.12:55:02.56#ibcon#about to write, iclass 25, count 0 2006.285.12:55:02.56#ibcon#wrote, iclass 25, count 0 2006.285.12:55:02.56#ibcon#about to read 3, iclass 25, count 0 2006.285.12:55:02.58#ibcon#read 3, iclass 25, count 0 2006.285.12:55:02.58#ibcon#about to read 4, iclass 25, count 0 2006.285.12:55:02.58#ibcon#read 4, iclass 25, count 0 2006.285.12:55:02.58#ibcon#about to read 5, iclass 25, count 0 2006.285.12:55:02.58#ibcon#read 5, iclass 25, count 0 2006.285.12:55:02.58#ibcon#about to read 6, iclass 25, count 0 2006.285.12:55:02.58#ibcon#read 6, iclass 25, count 0 2006.285.12:55:02.58#ibcon#end of sib2, iclass 25, count 0 2006.285.12:55:02.58#ibcon#*mode == 0, iclass 25, count 0 2006.285.12:55:02.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.12:55:02.58#ibcon#[25=BW32\r\n] 2006.285.12:55:02.58#ibcon#*before write, iclass 25, count 0 2006.285.12:55:02.58#ibcon#enter sib2, iclass 25, count 0 2006.285.12:55:02.58#ibcon#flushed, iclass 25, count 0 2006.285.12:55:02.58#ibcon#about to write, iclass 25, count 0 2006.285.12:55:02.58#ibcon#wrote, iclass 25, count 0 2006.285.12:55:02.58#ibcon#about to read 3, iclass 25, count 0 2006.285.12:55:02.61#ibcon#read 3, iclass 25, count 0 2006.285.12:55:02.61#ibcon#about to read 4, iclass 25, count 0 2006.285.12:55:02.61#ibcon#read 4, iclass 25, count 0 2006.285.12:55:02.61#ibcon#about to read 5, iclass 25, count 0 2006.285.12:55:02.61#ibcon#read 5, iclass 25, count 0 2006.285.12:55:02.61#ibcon#about to read 6, iclass 25, count 0 2006.285.12:55:02.61#ibcon#read 6, iclass 25, count 0 2006.285.12:55:02.61#ibcon#end of sib2, iclass 25, count 0 2006.285.12:55:02.61#ibcon#*after write, iclass 25, count 0 2006.285.12:55:02.61#ibcon#*before return 0, iclass 25, count 0 2006.285.12:55:02.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:55:02.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.12:55:02.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.12:55:02.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.12:55:02.61$vck44/vbbw=wide 2006.285.12:55:02.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.12:55:02.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.12:55:02.61#ibcon#ireg 8 cls_cnt 0 2006.285.12:55:02.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:55:02.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:55:02.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:55:02.68#ibcon#enter wrdev, iclass 27, count 0 2006.285.12:55:02.68#ibcon#first serial, iclass 27, count 0 2006.285.12:55:02.68#ibcon#enter sib2, iclass 27, count 0 2006.285.12:55:02.68#ibcon#flushed, iclass 27, count 0 2006.285.12:55:02.68#ibcon#about to write, iclass 27, count 0 2006.285.12:55:02.68#ibcon#wrote, iclass 27, count 0 2006.285.12:55:02.68#ibcon#about to read 3, iclass 27, count 0 2006.285.12:55:02.70#ibcon#read 3, iclass 27, count 0 2006.285.12:55:02.70#ibcon#about to read 4, iclass 27, count 0 2006.285.12:55:02.70#ibcon#read 4, iclass 27, count 0 2006.285.12:55:02.70#ibcon#about to read 5, iclass 27, count 0 2006.285.12:55:02.70#ibcon#read 5, iclass 27, count 0 2006.285.12:55:02.70#ibcon#about to read 6, iclass 27, count 0 2006.285.12:55:02.70#ibcon#read 6, iclass 27, count 0 2006.285.12:55:02.70#ibcon#end of sib2, iclass 27, count 0 2006.285.12:55:02.70#ibcon#*mode == 0, iclass 27, count 0 2006.285.12:55:02.70#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.12:55:02.70#ibcon#[27=BW32\r\n] 2006.285.12:55:02.70#ibcon#*before write, iclass 27, count 0 2006.285.12:55:02.70#ibcon#enter sib2, iclass 27, count 0 2006.285.12:55:02.70#ibcon#flushed, iclass 27, count 0 2006.285.12:55:02.70#ibcon#about to write, iclass 27, count 0 2006.285.12:55:02.70#ibcon#wrote, iclass 27, count 0 2006.285.12:55:02.70#ibcon#about to read 3, iclass 27, count 0 2006.285.12:55:02.73#ibcon#read 3, iclass 27, count 0 2006.285.12:55:02.73#ibcon#about to read 4, iclass 27, count 0 2006.285.12:55:02.73#ibcon#read 4, iclass 27, count 0 2006.285.12:55:02.73#ibcon#about to read 5, iclass 27, count 0 2006.285.12:55:02.73#ibcon#read 5, iclass 27, count 0 2006.285.12:55:02.73#ibcon#about to read 6, iclass 27, count 0 2006.285.12:55:02.73#ibcon#read 6, iclass 27, count 0 2006.285.12:55:02.73#ibcon#end of sib2, iclass 27, count 0 2006.285.12:55:02.73#ibcon#*after write, iclass 27, count 0 2006.285.12:55:02.73#ibcon#*before return 0, iclass 27, count 0 2006.285.12:55:02.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:55:02.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.12:55:02.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.12:55:02.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.12:55:02.73$setupk4/ifdk4 2006.285.12:55:02.73$ifdk4/lo= 2006.285.12:55:02.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.12:55:02.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.12:55:02.73$ifdk4/patch= 2006.285.12:55:02.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.12:55:02.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.12:55:02.73$setupk4/!*+20s 2006.285.12:55:10.13#trakl#Source acquired 2006.285.12:55:10.13#flagr#flagr/antenna,acquired 2006.285.12:55:12.46#abcon#<5=/04 1.3 3.1 18.96 961015.4\r\n> 2006.285.12:55:12.48#abcon#{5=INTERFACE CLEAR} 2006.285.12:55:12.54#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:55:16.83$setupk4/"tpicd 2006.285.12:55:16.83$setupk4/echo=off 2006.285.12:55:16.83$setupk4/xlog=off 2006.285.12:55:16.83:!2006.285.12:55:26 2006.285.12:55:26.00:preob 2006.285.12:55:26.13/onsource/TRACKING 2006.285.12:55:26.13:!2006.285.12:55:36 2006.285.12:55:36.00:"tape 2006.285.12:55:36.00:"st=record 2006.285.12:55:36.00:data_valid=on 2006.285.12:55:36.00:midob 2006.285.12:55:37.13/onsource/TRACKING 2006.285.12:55:37.13/wx/18.97,1015.5,96 2006.285.12:55:37.28/cable/+6.4967E-03 2006.285.12:55:38.37/va/01,07,usb,yes,34,37 2006.285.12:55:38.37/va/02,06,usb,yes,34,34 2006.285.12:55:38.37/va/03,07,usb,yes,33,35 2006.285.12:55:38.37/va/04,06,usb,yes,35,36 2006.285.12:55:38.37/va/05,03,usb,yes,35,35 2006.285.12:55:38.37/va/06,04,usb,yes,31,31 2006.285.12:55:38.37/va/07,04,usb,yes,32,32 2006.285.12:55:38.37/va/08,03,usb,yes,32,39 2006.285.12:55:38.60/valo/01,524.99,yes,locked 2006.285.12:55:38.60/valo/02,534.99,yes,locked 2006.285.12:55:38.60/valo/03,564.99,yes,locked 2006.285.12:55:38.60/valo/04,624.99,yes,locked 2006.285.12:55:38.60/valo/05,734.99,yes,locked 2006.285.12:55:38.60/valo/06,814.99,yes,locked 2006.285.12:55:38.60/valo/07,864.99,yes,locked 2006.285.12:55:38.60/valo/08,884.99,yes,locked 2006.285.12:55:39.69/vb/01,04,usb,yes,31,29 2006.285.12:55:39.69/vb/02,05,usb,yes,30,29 2006.285.12:55:39.69/vb/03,04,usb,yes,31,34 2006.285.12:55:39.69/vb/04,05,usb,yes,31,30 2006.285.12:55:39.69/vb/05,04,usb,yes,27,30 2006.285.12:55:39.69/vb/06,03,usb,yes,39,35 2006.285.12:55:39.69/vb/07,04,usb,yes,32,32 2006.285.12:55:39.69/vb/08,04,usb,yes,29,32 2006.285.12:55:39.92/vblo/01,629.99,yes,locked 2006.285.12:55:39.92/vblo/02,634.99,yes,locked 2006.285.12:55:39.92/vblo/03,649.99,yes,locked 2006.285.12:55:39.92/vblo/04,679.99,yes,locked 2006.285.12:55:39.92/vblo/05,709.99,yes,locked 2006.285.12:55:39.92/vblo/06,719.99,yes,locked 2006.285.12:55:39.92/vblo/07,734.99,yes,locked 2006.285.12:55:39.92/vblo/08,744.99,yes,locked 2006.285.12:55:40.07/vabw/8 2006.285.12:55:40.22/vbbw/8 2006.285.12:55:40.31/xfe/off,on,12.2 2006.285.12:55:40.68/ifatt/23,28,28,28 2006.285.12:55:41.08/fmout-gps/S +2.67E-07 2006.285.12:55:41.10:!2006.285.12:56:36 2006.285.12:56:36.01:data_valid=off 2006.285.12:56:36.01:"et 2006.285.12:56:36.01:!+3s 2006.285.12:56:39.02:"tape 2006.285.12:56:39.02:postob 2006.285.12:56:39.24/cable/+6.4980E-03 2006.285.12:56:39.24/wx/18.97,1015.5,96 2006.285.12:56:40.08/fmout-gps/S +2.68E-07 2006.285.12:56:40.08:scan_name=285-1302,jd0610,100 2006.285.12:56:40.08:source=2128-123,213135.26,-120704.8,2000.0,ccw 2006.285.12:56:40.14#flagr#flagr/antenna,new-source 2006.285.12:56:41.14:checkk5 2006.285.12:56:41.65/chk_autoobs//k5ts1/ autoobs is running! 2006.285.12:56:42.22/chk_autoobs//k5ts2/ autoobs is running! 2006.285.12:56:42.70/chk_autoobs//k5ts3/ autoobs is running! 2006.285.12:56:43.10/chk_autoobs//k5ts4/ autoobs is running! 2006.285.12:56:43.52/chk_obsdata//k5ts1/T2851255??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.12:56:43.87/chk_obsdata//k5ts2/T2851255??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.12:56:44.36/chk_obsdata//k5ts3/T2851255??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.12:56:44.83/chk_obsdata//k5ts4/T2851255??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.12:56:45.82/k5log//k5ts1_log_newline 2006.285.12:56:46.52/k5log//k5ts2_log_newline 2006.285.12:56:47.26/k5log//k5ts3_log_newline 2006.285.12:56:47.95/k5log//k5ts4_log_newline 2006.285.12:56:47.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.12:56:47.98:setupk4=1 2006.285.12:56:47.98$setupk4/echo=on 2006.285.12:56:47.98$setupk4/pcalon 2006.285.12:56:47.98$pcalon/"no phase cal control is implemented here 2006.285.12:56:47.98$setupk4/"tpicd=stop 2006.285.12:56:47.98$setupk4/"rec=synch_on 2006.285.12:56:47.98$setupk4/"rec_mode=128 2006.285.12:56:47.98$setupk4/!* 2006.285.12:56:47.98$setupk4/recpk4 2006.285.12:56:47.98$recpk4/recpatch= 2006.285.12:56:47.98$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.12:56:47.98$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.12:56:47.98$setupk4/vck44 2006.285.12:56:47.98$vck44/valo=1,524.99 2006.285.12:56:47.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.12:56:47.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.12:56:47.98#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:47.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:56:47.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:56:47.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:56:47.98#ibcon#enter wrdev, iclass 36, count 0 2006.285.12:56:47.98#ibcon#first serial, iclass 36, count 0 2006.285.12:56:47.98#ibcon#enter sib2, iclass 36, count 0 2006.285.12:56:47.98#ibcon#flushed, iclass 36, count 0 2006.285.12:56:47.98#ibcon#about to write, iclass 36, count 0 2006.285.12:56:47.98#ibcon#wrote, iclass 36, count 0 2006.285.12:56:47.98#ibcon#about to read 3, iclass 36, count 0 2006.285.12:56:48.00#ibcon#read 3, iclass 36, count 0 2006.285.12:56:48.00#ibcon#about to read 4, iclass 36, count 0 2006.285.12:56:48.00#ibcon#read 4, iclass 36, count 0 2006.285.12:56:48.00#ibcon#about to read 5, iclass 36, count 0 2006.285.12:56:48.00#ibcon#read 5, iclass 36, count 0 2006.285.12:56:48.00#ibcon#about to read 6, iclass 36, count 0 2006.285.12:56:48.00#ibcon#read 6, iclass 36, count 0 2006.285.12:56:48.00#ibcon#end of sib2, iclass 36, count 0 2006.285.12:56:48.00#ibcon#*mode == 0, iclass 36, count 0 2006.285.12:56:48.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.12:56:48.00#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.12:56:48.00#ibcon#*before write, iclass 36, count 0 2006.285.12:56:48.00#ibcon#enter sib2, iclass 36, count 0 2006.285.12:56:48.00#ibcon#flushed, iclass 36, count 0 2006.285.12:56:48.00#ibcon#about to write, iclass 36, count 0 2006.285.12:56:48.00#ibcon#wrote, iclass 36, count 0 2006.285.12:56:48.00#ibcon#about to read 3, iclass 36, count 0 2006.285.12:56:48.05#ibcon#read 3, iclass 36, count 0 2006.285.12:56:48.05#ibcon#about to read 4, iclass 36, count 0 2006.285.12:56:48.05#ibcon#read 4, iclass 36, count 0 2006.285.12:56:48.05#ibcon#about to read 5, iclass 36, count 0 2006.285.12:56:48.05#ibcon#read 5, iclass 36, count 0 2006.285.12:56:48.05#ibcon#about to read 6, iclass 36, count 0 2006.285.12:56:48.05#ibcon#read 6, iclass 36, count 0 2006.285.12:56:48.05#ibcon#end of sib2, iclass 36, count 0 2006.285.12:56:48.05#ibcon#*after write, iclass 36, count 0 2006.285.12:56:48.05#ibcon#*before return 0, iclass 36, count 0 2006.285.12:56:48.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:56:48.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:56:48.05#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.12:56:48.05#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.12:56:48.05$vck44/va=1,7 2006.285.12:56:48.05#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.12:56:48.05#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.12:56:48.05#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:48.05#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:56:48.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:56:48.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:56:48.05#ibcon#enter wrdev, iclass 38, count 2 2006.285.12:56:48.05#ibcon#first serial, iclass 38, count 2 2006.285.12:56:48.05#ibcon#enter sib2, iclass 38, count 2 2006.285.12:56:48.05#ibcon#flushed, iclass 38, count 2 2006.285.12:56:48.05#ibcon#about to write, iclass 38, count 2 2006.285.12:56:48.05#ibcon#wrote, iclass 38, count 2 2006.285.12:56:48.05#ibcon#about to read 3, iclass 38, count 2 2006.285.12:56:48.07#ibcon#read 3, iclass 38, count 2 2006.285.12:56:48.07#ibcon#about to read 4, iclass 38, count 2 2006.285.12:56:48.07#ibcon#read 4, iclass 38, count 2 2006.285.12:56:48.07#ibcon#about to read 5, iclass 38, count 2 2006.285.12:56:48.07#ibcon#read 5, iclass 38, count 2 2006.285.12:56:48.07#ibcon#about to read 6, iclass 38, count 2 2006.285.12:56:48.07#ibcon#read 6, iclass 38, count 2 2006.285.12:56:48.07#ibcon#end of sib2, iclass 38, count 2 2006.285.12:56:48.07#ibcon#*mode == 0, iclass 38, count 2 2006.285.12:56:48.07#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.12:56:48.07#ibcon#[25=AT01-07\r\n] 2006.285.12:56:48.07#ibcon#*before write, iclass 38, count 2 2006.285.12:56:48.07#ibcon#enter sib2, iclass 38, count 2 2006.285.12:56:48.07#ibcon#flushed, iclass 38, count 2 2006.285.12:56:48.07#ibcon#about to write, iclass 38, count 2 2006.285.12:56:48.07#ibcon#wrote, iclass 38, count 2 2006.285.12:56:48.07#ibcon#about to read 3, iclass 38, count 2 2006.285.12:56:48.10#ibcon#read 3, iclass 38, count 2 2006.285.12:56:48.10#ibcon#about to read 4, iclass 38, count 2 2006.285.12:56:48.10#ibcon#read 4, iclass 38, count 2 2006.285.12:56:48.10#ibcon#about to read 5, iclass 38, count 2 2006.285.12:56:48.10#ibcon#read 5, iclass 38, count 2 2006.285.12:56:48.10#ibcon#about to read 6, iclass 38, count 2 2006.285.12:56:48.10#ibcon#read 6, iclass 38, count 2 2006.285.12:56:48.10#ibcon#end of sib2, iclass 38, count 2 2006.285.12:56:48.10#ibcon#*after write, iclass 38, count 2 2006.285.12:56:48.10#ibcon#*before return 0, iclass 38, count 2 2006.285.12:56:48.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:56:48.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:56:48.10#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.12:56:48.10#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:48.10#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:56:48.22#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:56:48.22#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:56:48.22#ibcon#enter wrdev, iclass 38, count 0 2006.285.12:56:48.22#ibcon#first serial, iclass 38, count 0 2006.285.12:56:48.22#ibcon#enter sib2, iclass 38, count 0 2006.285.12:56:48.22#ibcon#flushed, iclass 38, count 0 2006.285.12:56:48.22#ibcon#about to write, iclass 38, count 0 2006.285.12:56:48.22#ibcon#wrote, iclass 38, count 0 2006.285.12:56:48.22#ibcon#about to read 3, iclass 38, count 0 2006.285.12:56:48.24#ibcon#read 3, iclass 38, count 0 2006.285.12:56:48.24#ibcon#about to read 4, iclass 38, count 0 2006.285.12:56:48.24#ibcon#read 4, iclass 38, count 0 2006.285.12:56:48.24#ibcon#about to read 5, iclass 38, count 0 2006.285.12:56:48.24#ibcon#read 5, iclass 38, count 0 2006.285.12:56:48.24#ibcon#about to read 6, iclass 38, count 0 2006.285.12:56:48.24#ibcon#read 6, iclass 38, count 0 2006.285.12:56:48.24#ibcon#end of sib2, iclass 38, count 0 2006.285.12:56:48.24#ibcon#*mode == 0, iclass 38, count 0 2006.285.12:56:48.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.12:56:48.24#ibcon#[25=USB\r\n] 2006.285.12:56:48.24#ibcon#*before write, iclass 38, count 0 2006.285.12:56:48.24#ibcon#enter sib2, iclass 38, count 0 2006.285.12:56:48.24#ibcon#flushed, iclass 38, count 0 2006.285.12:56:48.24#ibcon#about to write, iclass 38, count 0 2006.285.12:56:48.24#ibcon#wrote, iclass 38, count 0 2006.285.12:56:48.24#ibcon#about to read 3, iclass 38, count 0 2006.285.12:56:48.27#ibcon#read 3, iclass 38, count 0 2006.285.12:56:48.27#ibcon#about to read 4, iclass 38, count 0 2006.285.12:56:48.27#ibcon#read 4, iclass 38, count 0 2006.285.12:56:48.27#ibcon#about to read 5, iclass 38, count 0 2006.285.12:56:48.27#ibcon#read 5, iclass 38, count 0 2006.285.12:56:48.27#ibcon#about to read 6, iclass 38, count 0 2006.285.12:56:48.27#ibcon#read 6, iclass 38, count 0 2006.285.12:56:48.27#ibcon#end of sib2, iclass 38, count 0 2006.285.12:56:48.27#ibcon#*after write, iclass 38, count 0 2006.285.12:56:48.27#ibcon#*before return 0, iclass 38, count 0 2006.285.12:56:48.27#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:56:48.27#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:56:48.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.12:56:48.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.12:56:48.27$vck44/valo=2,534.99 2006.285.12:56:48.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.12:56:48.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.12:56:48.27#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:48.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:56:48.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:56:48.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:56:48.27#ibcon#enter wrdev, iclass 40, count 0 2006.285.12:56:48.27#ibcon#first serial, iclass 40, count 0 2006.285.12:56:48.27#ibcon#enter sib2, iclass 40, count 0 2006.285.12:56:48.27#ibcon#flushed, iclass 40, count 0 2006.285.12:56:48.81#ibcon#about to write, iclass 40, count 0 2006.285.12:56:48.81#ibcon#wrote, iclass 40, count 0 2006.285.12:56:48.81#ibcon#about to read 3, iclass 40, count 0 2006.285.12:56:48.83#ibcon#read 3, iclass 40, count 0 2006.285.12:56:48.83#ibcon#about to read 4, iclass 40, count 0 2006.285.12:56:48.83#ibcon#read 4, iclass 40, count 0 2006.285.12:56:48.83#ibcon#about to read 5, iclass 40, count 0 2006.285.12:56:48.83#ibcon#read 5, iclass 40, count 0 2006.285.12:56:48.83#ibcon#about to read 6, iclass 40, count 0 2006.285.12:56:48.83#ibcon#read 6, iclass 40, count 0 2006.285.12:56:48.83#ibcon#end of sib2, iclass 40, count 0 2006.285.12:56:48.83#ibcon#*mode == 0, iclass 40, count 0 2006.285.12:56:48.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.12:56:48.83#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.12:56:48.83#ibcon#*before write, iclass 40, count 0 2006.285.12:56:48.83#ibcon#enter sib2, iclass 40, count 0 2006.285.12:56:48.83#ibcon#flushed, iclass 40, count 0 2006.285.12:56:48.83#ibcon#about to write, iclass 40, count 0 2006.285.12:56:48.83#ibcon#wrote, iclass 40, count 0 2006.285.12:56:48.83#ibcon#about to read 3, iclass 40, count 0 2006.285.12:56:48.87#ibcon#read 3, iclass 40, count 0 2006.285.12:56:48.87#ibcon#about to read 4, iclass 40, count 0 2006.285.12:56:48.87#ibcon#read 4, iclass 40, count 0 2006.285.12:56:48.87#ibcon#about to read 5, iclass 40, count 0 2006.285.12:56:48.87#ibcon#read 5, iclass 40, count 0 2006.285.12:56:48.87#ibcon#about to read 6, iclass 40, count 0 2006.285.12:56:48.87#ibcon#read 6, iclass 40, count 0 2006.285.12:56:48.87#ibcon#end of sib2, iclass 40, count 0 2006.285.12:56:48.87#ibcon#*after write, iclass 40, count 0 2006.285.12:56:48.87#ibcon#*before return 0, iclass 40, count 0 2006.285.12:56:48.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:56:48.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:56:48.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.12:56:48.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.12:56:48.87$vck44/va=2,6 2006.285.12:56:48.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.12:56:48.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.12:56:48.87#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:48.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:56:48.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:56:48.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:56:48.87#ibcon#enter wrdev, iclass 4, count 2 2006.285.12:56:48.87#ibcon#first serial, iclass 4, count 2 2006.285.12:56:48.87#ibcon#enter sib2, iclass 4, count 2 2006.285.12:56:48.87#ibcon#flushed, iclass 4, count 2 2006.285.12:56:48.87#ibcon#about to write, iclass 4, count 2 2006.285.12:56:48.87#ibcon#wrote, iclass 4, count 2 2006.285.12:56:48.87#ibcon#about to read 3, iclass 4, count 2 2006.285.12:56:48.89#ibcon#read 3, iclass 4, count 2 2006.285.12:56:48.89#ibcon#about to read 4, iclass 4, count 2 2006.285.12:56:48.89#ibcon#read 4, iclass 4, count 2 2006.285.12:56:48.89#ibcon#about to read 5, iclass 4, count 2 2006.285.12:56:48.89#ibcon#read 5, iclass 4, count 2 2006.285.12:56:48.89#ibcon#about to read 6, iclass 4, count 2 2006.285.12:56:48.89#ibcon#read 6, iclass 4, count 2 2006.285.12:56:48.89#ibcon#end of sib2, iclass 4, count 2 2006.285.12:56:48.89#ibcon#*mode == 0, iclass 4, count 2 2006.285.12:56:48.89#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.12:56:48.89#ibcon#[25=AT02-06\r\n] 2006.285.12:56:48.89#ibcon#*before write, iclass 4, count 2 2006.285.12:56:48.89#ibcon#enter sib2, iclass 4, count 2 2006.285.12:56:48.89#ibcon#flushed, iclass 4, count 2 2006.285.12:56:48.89#ibcon#about to write, iclass 4, count 2 2006.285.12:56:48.89#ibcon#wrote, iclass 4, count 2 2006.285.12:56:48.89#ibcon#about to read 3, iclass 4, count 2 2006.285.12:56:48.92#ibcon#read 3, iclass 4, count 2 2006.285.12:56:48.92#ibcon#about to read 4, iclass 4, count 2 2006.285.12:56:48.92#ibcon#read 4, iclass 4, count 2 2006.285.12:56:48.92#ibcon#about to read 5, iclass 4, count 2 2006.285.12:56:48.92#ibcon#read 5, iclass 4, count 2 2006.285.12:56:48.92#ibcon#about to read 6, iclass 4, count 2 2006.285.12:56:48.92#ibcon#read 6, iclass 4, count 2 2006.285.12:56:48.92#ibcon#end of sib2, iclass 4, count 2 2006.285.12:56:48.92#ibcon#*after write, iclass 4, count 2 2006.285.12:56:48.92#ibcon#*before return 0, iclass 4, count 2 2006.285.12:56:48.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:56:48.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:56:48.92#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.12:56:48.92#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:48.92#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:56:49.04#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:56:49.04#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:56:49.04#ibcon#enter wrdev, iclass 4, count 0 2006.285.12:56:49.04#ibcon#first serial, iclass 4, count 0 2006.285.12:56:49.04#ibcon#enter sib2, iclass 4, count 0 2006.285.12:56:49.04#ibcon#flushed, iclass 4, count 0 2006.285.12:56:49.04#ibcon#about to write, iclass 4, count 0 2006.285.12:56:49.04#ibcon#wrote, iclass 4, count 0 2006.285.12:56:49.04#ibcon#about to read 3, iclass 4, count 0 2006.285.12:56:49.06#ibcon#read 3, iclass 4, count 0 2006.285.12:56:49.06#ibcon#about to read 4, iclass 4, count 0 2006.285.12:56:49.06#ibcon#read 4, iclass 4, count 0 2006.285.12:56:49.06#ibcon#about to read 5, iclass 4, count 0 2006.285.12:56:49.06#ibcon#read 5, iclass 4, count 0 2006.285.12:56:49.06#ibcon#about to read 6, iclass 4, count 0 2006.285.12:56:49.06#ibcon#read 6, iclass 4, count 0 2006.285.12:56:49.06#ibcon#end of sib2, iclass 4, count 0 2006.285.12:56:49.06#ibcon#*mode == 0, iclass 4, count 0 2006.285.12:56:49.06#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.12:56:49.06#ibcon#[25=USB\r\n] 2006.285.12:56:49.06#ibcon#*before write, iclass 4, count 0 2006.285.12:56:49.06#ibcon#enter sib2, iclass 4, count 0 2006.285.12:56:49.06#ibcon#flushed, iclass 4, count 0 2006.285.12:56:49.06#ibcon#about to write, iclass 4, count 0 2006.285.12:56:49.06#ibcon#wrote, iclass 4, count 0 2006.285.12:56:49.06#ibcon#about to read 3, iclass 4, count 0 2006.285.12:56:49.09#ibcon#read 3, iclass 4, count 0 2006.285.12:56:49.09#ibcon#about to read 4, iclass 4, count 0 2006.285.12:56:49.09#ibcon#read 4, iclass 4, count 0 2006.285.12:56:49.09#ibcon#about to read 5, iclass 4, count 0 2006.285.12:56:49.09#ibcon#read 5, iclass 4, count 0 2006.285.12:56:49.09#ibcon#about to read 6, iclass 4, count 0 2006.285.12:56:49.09#ibcon#read 6, iclass 4, count 0 2006.285.12:56:49.09#ibcon#end of sib2, iclass 4, count 0 2006.285.12:56:49.09#ibcon#*after write, iclass 4, count 0 2006.285.12:56:49.09#ibcon#*before return 0, iclass 4, count 0 2006.285.12:56:49.09#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:56:49.09#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:56:49.09#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.12:56:49.09#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.12:56:49.09$vck44/valo=3,564.99 2006.285.12:56:49.09#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.12:56:49.09#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.12:56:49.09#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:49.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:56:49.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:56:49.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:56:49.09#ibcon#enter wrdev, iclass 6, count 0 2006.285.12:56:49.09#ibcon#first serial, iclass 6, count 0 2006.285.12:56:49.09#ibcon#enter sib2, iclass 6, count 0 2006.285.12:56:49.09#ibcon#flushed, iclass 6, count 0 2006.285.12:56:49.09#ibcon#about to write, iclass 6, count 0 2006.285.12:56:49.09#ibcon#wrote, iclass 6, count 0 2006.285.12:56:49.09#ibcon#about to read 3, iclass 6, count 0 2006.285.12:56:49.11#ibcon#read 3, iclass 6, count 0 2006.285.12:56:49.18#ibcon#about to read 4, iclass 6, count 0 2006.285.12:56:49.18#ibcon#read 4, iclass 6, count 0 2006.285.12:56:49.18#ibcon#about to read 5, iclass 6, count 0 2006.285.12:56:49.18#ibcon#read 5, iclass 6, count 0 2006.285.12:56:49.18#ibcon#about to read 6, iclass 6, count 0 2006.285.12:56:49.18#ibcon#read 6, iclass 6, count 0 2006.285.12:56:49.18#ibcon#end of sib2, iclass 6, count 0 2006.285.12:56:49.18#ibcon#*mode == 0, iclass 6, count 0 2006.285.12:56:49.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.12:56:49.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.12:56:49.18#ibcon#*before write, iclass 6, count 0 2006.285.12:56:49.18#ibcon#enter sib2, iclass 6, count 0 2006.285.12:56:49.18#ibcon#flushed, iclass 6, count 0 2006.285.12:56:49.18#ibcon#about to write, iclass 6, count 0 2006.285.12:56:49.18#ibcon#wrote, iclass 6, count 0 2006.285.12:56:49.18#ibcon#about to read 3, iclass 6, count 0 2006.285.12:56:49.23#ibcon#read 3, iclass 6, count 0 2006.285.12:56:49.23#ibcon#about to read 4, iclass 6, count 0 2006.285.12:56:49.23#ibcon#read 4, iclass 6, count 0 2006.285.12:56:49.23#ibcon#about to read 5, iclass 6, count 0 2006.285.12:56:49.23#ibcon#read 5, iclass 6, count 0 2006.285.12:56:49.23#ibcon#about to read 6, iclass 6, count 0 2006.285.12:56:49.23#ibcon#read 6, iclass 6, count 0 2006.285.12:56:49.23#ibcon#end of sib2, iclass 6, count 0 2006.285.12:56:49.23#ibcon#*after write, iclass 6, count 0 2006.285.12:56:49.23#ibcon#*before return 0, iclass 6, count 0 2006.285.12:56:49.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:56:49.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:56:49.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.12:56:49.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.12:56:49.23$vck44/va=3,7 2006.285.12:56:49.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.12:56:49.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.12:56:49.23#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:49.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:56:49.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:56:49.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:56:49.23#ibcon#enter wrdev, iclass 10, count 2 2006.285.12:56:49.23#ibcon#first serial, iclass 10, count 2 2006.285.12:56:49.23#ibcon#enter sib2, iclass 10, count 2 2006.285.12:56:49.23#ibcon#flushed, iclass 10, count 2 2006.285.12:56:49.23#ibcon#about to write, iclass 10, count 2 2006.285.12:56:49.23#ibcon#wrote, iclass 10, count 2 2006.285.12:56:49.23#ibcon#about to read 3, iclass 10, count 2 2006.285.12:56:49.25#ibcon#read 3, iclass 10, count 2 2006.285.12:56:49.25#ibcon#about to read 4, iclass 10, count 2 2006.285.12:56:49.25#ibcon#read 4, iclass 10, count 2 2006.285.12:56:49.25#ibcon#about to read 5, iclass 10, count 2 2006.285.12:56:49.25#ibcon#read 5, iclass 10, count 2 2006.285.12:56:49.25#ibcon#about to read 6, iclass 10, count 2 2006.285.12:56:49.25#ibcon#read 6, iclass 10, count 2 2006.285.12:56:49.25#ibcon#end of sib2, iclass 10, count 2 2006.285.12:56:49.25#ibcon#*mode == 0, iclass 10, count 2 2006.285.12:56:49.25#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.12:56:49.25#ibcon#[25=AT03-07\r\n] 2006.285.12:56:49.25#ibcon#*before write, iclass 10, count 2 2006.285.12:56:49.25#ibcon#enter sib2, iclass 10, count 2 2006.285.12:56:49.25#ibcon#flushed, iclass 10, count 2 2006.285.12:56:49.25#ibcon#about to write, iclass 10, count 2 2006.285.12:56:49.25#ibcon#wrote, iclass 10, count 2 2006.285.12:56:49.25#ibcon#about to read 3, iclass 10, count 2 2006.285.12:56:49.28#ibcon#read 3, iclass 10, count 2 2006.285.12:56:49.28#ibcon#about to read 4, iclass 10, count 2 2006.285.12:56:49.28#ibcon#read 4, iclass 10, count 2 2006.285.12:56:49.28#ibcon#about to read 5, iclass 10, count 2 2006.285.12:56:49.28#ibcon#read 5, iclass 10, count 2 2006.285.12:56:49.28#ibcon#about to read 6, iclass 10, count 2 2006.285.12:56:49.28#ibcon#read 6, iclass 10, count 2 2006.285.12:56:49.28#ibcon#end of sib2, iclass 10, count 2 2006.285.12:56:49.28#ibcon#*after write, iclass 10, count 2 2006.285.12:56:49.28#ibcon#*before return 0, iclass 10, count 2 2006.285.12:56:49.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:56:49.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:56:49.28#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.12:56:49.28#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:49.28#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:56:49.40#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:56:49.40#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:56:49.40#ibcon#enter wrdev, iclass 10, count 0 2006.285.12:56:49.40#ibcon#first serial, iclass 10, count 0 2006.285.12:56:49.40#ibcon#enter sib2, iclass 10, count 0 2006.285.12:56:49.40#ibcon#flushed, iclass 10, count 0 2006.285.12:56:49.40#ibcon#about to write, iclass 10, count 0 2006.285.12:56:49.40#ibcon#wrote, iclass 10, count 0 2006.285.12:56:49.40#ibcon#about to read 3, iclass 10, count 0 2006.285.12:56:49.42#ibcon#read 3, iclass 10, count 0 2006.285.12:56:49.42#ibcon#about to read 4, iclass 10, count 0 2006.285.12:56:49.42#ibcon#read 4, iclass 10, count 0 2006.285.12:56:49.42#ibcon#about to read 5, iclass 10, count 0 2006.285.12:56:49.42#ibcon#read 5, iclass 10, count 0 2006.285.12:56:49.42#ibcon#about to read 6, iclass 10, count 0 2006.285.12:56:49.42#ibcon#read 6, iclass 10, count 0 2006.285.12:56:49.42#ibcon#end of sib2, iclass 10, count 0 2006.285.12:56:49.42#ibcon#*mode == 0, iclass 10, count 0 2006.285.12:56:49.42#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.12:56:49.42#ibcon#[25=USB\r\n] 2006.285.12:56:49.42#ibcon#*before write, iclass 10, count 0 2006.285.12:56:49.42#ibcon#enter sib2, iclass 10, count 0 2006.285.12:56:49.42#ibcon#flushed, iclass 10, count 0 2006.285.12:56:49.42#ibcon#about to write, iclass 10, count 0 2006.285.12:56:49.42#ibcon#wrote, iclass 10, count 0 2006.285.12:56:49.42#ibcon#about to read 3, iclass 10, count 0 2006.285.12:56:49.45#ibcon#read 3, iclass 10, count 0 2006.285.12:56:49.45#ibcon#about to read 4, iclass 10, count 0 2006.285.12:56:49.45#ibcon#read 4, iclass 10, count 0 2006.285.12:56:49.45#ibcon#about to read 5, iclass 10, count 0 2006.285.12:56:49.45#ibcon#read 5, iclass 10, count 0 2006.285.12:56:49.45#ibcon#about to read 6, iclass 10, count 0 2006.285.12:56:49.45#ibcon#read 6, iclass 10, count 0 2006.285.12:56:49.45#ibcon#end of sib2, iclass 10, count 0 2006.285.12:56:49.45#ibcon#*after write, iclass 10, count 0 2006.285.12:56:49.45#ibcon#*before return 0, iclass 10, count 0 2006.285.12:56:49.45#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:56:49.45#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:56:49.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.12:56:49.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.12:56:49.45$vck44/valo=4,624.99 2006.285.12:56:49.45#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.12:56:49.45#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.12:56:49.45#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:49.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:56:49.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:56:49.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:56:49.45#ibcon#enter wrdev, iclass 12, count 0 2006.285.12:56:49.45#ibcon#first serial, iclass 12, count 0 2006.285.12:56:49.45#ibcon#enter sib2, iclass 12, count 0 2006.285.12:56:49.45#ibcon#flushed, iclass 12, count 0 2006.285.12:56:49.45#ibcon#about to write, iclass 12, count 0 2006.285.12:56:49.45#ibcon#wrote, iclass 12, count 0 2006.285.12:56:49.45#ibcon#about to read 3, iclass 12, count 0 2006.285.12:56:49.47#ibcon#read 3, iclass 12, count 0 2006.285.12:56:49.47#ibcon#about to read 4, iclass 12, count 0 2006.285.12:56:49.47#ibcon#read 4, iclass 12, count 0 2006.285.12:56:49.47#ibcon#about to read 5, iclass 12, count 0 2006.285.12:56:49.47#ibcon#read 5, iclass 12, count 0 2006.285.12:56:49.47#ibcon#about to read 6, iclass 12, count 0 2006.285.12:56:49.47#ibcon#read 6, iclass 12, count 0 2006.285.12:56:49.47#ibcon#end of sib2, iclass 12, count 0 2006.285.12:56:49.47#ibcon#*mode == 0, iclass 12, count 0 2006.285.12:56:49.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.12:56:49.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.12:56:49.47#ibcon#*before write, iclass 12, count 0 2006.285.12:56:49.47#ibcon#enter sib2, iclass 12, count 0 2006.285.12:56:49.47#ibcon#flushed, iclass 12, count 0 2006.285.12:56:49.47#ibcon#about to write, iclass 12, count 0 2006.285.12:56:49.47#ibcon#wrote, iclass 12, count 0 2006.285.12:56:49.47#ibcon#about to read 3, iclass 12, count 0 2006.285.12:56:49.51#ibcon#read 3, iclass 12, count 0 2006.285.12:56:49.51#ibcon#about to read 4, iclass 12, count 0 2006.285.12:56:49.51#ibcon#read 4, iclass 12, count 0 2006.285.12:56:49.51#ibcon#about to read 5, iclass 12, count 0 2006.285.12:56:49.51#ibcon#read 5, iclass 12, count 0 2006.285.12:56:49.51#ibcon#about to read 6, iclass 12, count 0 2006.285.12:56:49.51#ibcon#read 6, iclass 12, count 0 2006.285.12:56:49.51#ibcon#end of sib2, iclass 12, count 0 2006.285.12:56:49.51#ibcon#*after write, iclass 12, count 0 2006.285.12:56:49.51#ibcon#*before return 0, iclass 12, count 0 2006.285.12:56:49.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:56:49.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:56:49.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.12:56:49.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.12:56:49.51$vck44/va=4,6 2006.285.12:56:49.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.12:56:49.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.12:56:49.64#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:49.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:56:49.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:56:49.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:56:49.64#ibcon#enter wrdev, iclass 14, count 2 2006.285.12:56:49.64#ibcon#first serial, iclass 14, count 2 2006.285.12:56:49.64#ibcon#enter sib2, iclass 14, count 2 2006.285.12:56:49.64#ibcon#flushed, iclass 14, count 2 2006.285.12:56:49.64#ibcon#about to write, iclass 14, count 2 2006.285.12:56:49.64#ibcon#wrote, iclass 14, count 2 2006.285.12:56:49.64#ibcon#about to read 3, iclass 14, count 2 2006.285.12:56:49.66#ibcon#read 3, iclass 14, count 2 2006.285.12:56:49.66#ibcon#about to read 4, iclass 14, count 2 2006.285.12:56:49.66#ibcon#read 4, iclass 14, count 2 2006.285.12:56:49.66#ibcon#about to read 5, iclass 14, count 2 2006.285.12:56:49.66#ibcon#read 5, iclass 14, count 2 2006.285.12:56:49.66#ibcon#about to read 6, iclass 14, count 2 2006.285.12:56:49.66#ibcon#read 6, iclass 14, count 2 2006.285.12:56:49.66#ibcon#end of sib2, iclass 14, count 2 2006.285.12:56:49.66#ibcon#*mode == 0, iclass 14, count 2 2006.285.12:56:49.66#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.12:56:49.66#ibcon#[25=AT04-06\r\n] 2006.285.12:56:49.66#ibcon#*before write, iclass 14, count 2 2006.285.12:56:49.66#ibcon#enter sib2, iclass 14, count 2 2006.285.12:56:49.66#ibcon#flushed, iclass 14, count 2 2006.285.12:56:49.66#ibcon#about to write, iclass 14, count 2 2006.285.12:56:49.66#ibcon#wrote, iclass 14, count 2 2006.285.12:56:49.66#ibcon#about to read 3, iclass 14, count 2 2006.285.12:56:49.69#ibcon#read 3, iclass 14, count 2 2006.285.12:56:49.69#ibcon#about to read 4, iclass 14, count 2 2006.285.12:56:49.69#ibcon#read 4, iclass 14, count 2 2006.285.12:56:49.69#ibcon#about to read 5, iclass 14, count 2 2006.285.12:56:49.69#ibcon#read 5, iclass 14, count 2 2006.285.12:56:49.69#ibcon#about to read 6, iclass 14, count 2 2006.285.12:56:49.69#ibcon#read 6, iclass 14, count 2 2006.285.12:56:49.69#ibcon#end of sib2, iclass 14, count 2 2006.285.12:56:49.69#ibcon#*after write, iclass 14, count 2 2006.285.12:56:49.69#ibcon#*before return 0, iclass 14, count 2 2006.285.12:56:49.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:56:49.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:56:49.69#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.12:56:49.69#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:49.69#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:56:49.81#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:56:49.81#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:56:49.81#ibcon#enter wrdev, iclass 14, count 0 2006.285.12:56:49.81#ibcon#first serial, iclass 14, count 0 2006.285.12:56:49.81#ibcon#enter sib2, iclass 14, count 0 2006.285.12:56:49.81#ibcon#flushed, iclass 14, count 0 2006.285.12:56:49.81#ibcon#about to write, iclass 14, count 0 2006.285.12:56:49.81#ibcon#wrote, iclass 14, count 0 2006.285.12:56:49.81#ibcon#about to read 3, iclass 14, count 0 2006.285.12:56:49.83#ibcon#read 3, iclass 14, count 0 2006.285.12:56:49.83#ibcon#about to read 4, iclass 14, count 0 2006.285.12:56:49.83#ibcon#read 4, iclass 14, count 0 2006.285.12:56:49.83#ibcon#about to read 5, iclass 14, count 0 2006.285.12:56:49.83#ibcon#read 5, iclass 14, count 0 2006.285.12:56:49.83#ibcon#about to read 6, iclass 14, count 0 2006.285.12:56:49.83#ibcon#read 6, iclass 14, count 0 2006.285.12:56:49.83#ibcon#end of sib2, iclass 14, count 0 2006.285.12:56:49.83#ibcon#*mode == 0, iclass 14, count 0 2006.285.12:56:49.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.12:56:49.83#ibcon#[25=USB\r\n] 2006.285.12:56:49.83#ibcon#*before write, iclass 14, count 0 2006.285.12:56:49.83#ibcon#enter sib2, iclass 14, count 0 2006.285.12:56:49.83#ibcon#flushed, iclass 14, count 0 2006.285.12:56:49.83#ibcon#about to write, iclass 14, count 0 2006.285.12:56:49.83#ibcon#wrote, iclass 14, count 0 2006.285.12:56:49.83#ibcon#about to read 3, iclass 14, count 0 2006.285.12:56:49.86#ibcon#read 3, iclass 14, count 0 2006.285.12:56:49.86#ibcon#about to read 4, iclass 14, count 0 2006.285.12:56:49.86#ibcon#read 4, iclass 14, count 0 2006.285.12:56:49.86#ibcon#about to read 5, iclass 14, count 0 2006.285.12:56:49.86#ibcon#read 5, iclass 14, count 0 2006.285.12:56:49.86#ibcon#about to read 6, iclass 14, count 0 2006.285.12:56:49.86#ibcon#read 6, iclass 14, count 0 2006.285.12:56:49.86#ibcon#end of sib2, iclass 14, count 0 2006.285.12:56:49.86#ibcon#*after write, iclass 14, count 0 2006.285.12:56:49.86#ibcon#*before return 0, iclass 14, count 0 2006.285.12:56:49.86#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:56:49.86#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:56:49.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.12:56:49.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.12:56:49.86$vck44/valo=5,734.99 2006.285.12:56:49.86#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.12:56:49.86#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.12:56:49.86#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:49.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:56:49.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:56:49.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:56:49.86#ibcon#enter wrdev, iclass 16, count 0 2006.285.12:56:49.86#ibcon#first serial, iclass 16, count 0 2006.285.12:56:49.86#ibcon#enter sib2, iclass 16, count 0 2006.285.12:56:49.86#ibcon#flushed, iclass 16, count 0 2006.285.12:56:49.86#ibcon#about to write, iclass 16, count 0 2006.285.12:56:49.86#ibcon#wrote, iclass 16, count 0 2006.285.12:56:49.86#ibcon#about to read 3, iclass 16, count 0 2006.285.12:56:49.88#ibcon#read 3, iclass 16, count 0 2006.285.12:56:49.88#ibcon#about to read 4, iclass 16, count 0 2006.285.12:56:49.88#ibcon#read 4, iclass 16, count 0 2006.285.12:56:49.88#ibcon#about to read 5, iclass 16, count 0 2006.285.12:56:49.88#ibcon#read 5, iclass 16, count 0 2006.285.12:56:49.88#ibcon#about to read 6, iclass 16, count 0 2006.285.12:56:49.88#ibcon#read 6, iclass 16, count 0 2006.285.12:56:49.88#ibcon#end of sib2, iclass 16, count 0 2006.285.12:56:49.88#ibcon#*mode == 0, iclass 16, count 0 2006.285.12:56:49.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.12:56:49.88#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.12:56:49.88#ibcon#*before write, iclass 16, count 0 2006.285.12:56:49.88#ibcon#enter sib2, iclass 16, count 0 2006.285.12:56:49.88#ibcon#flushed, iclass 16, count 0 2006.285.12:56:49.88#ibcon#about to write, iclass 16, count 0 2006.285.12:56:49.88#ibcon#wrote, iclass 16, count 0 2006.285.12:56:49.88#ibcon#about to read 3, iclass 16, count 0 2006.285.12:56:49.92#ibcon#read 3, iclass 16, count 0 2006.285.12:56:49.92#ibcon#about to read 4, iclass 16, count 0 2006.285.12:56:49.92#ibcon#read 4, iclass 16, count 0 2006.285.12:56:49.92#ibcon#about to read 5, iclass 16, count 0 2006.285.12:56:49.92#ibcon#read 5, iclass 16, count 0 2006.285.12:56:49.92#ibcon#about to read 6, iclass 16, count 0 2006.285.12:56:49.92#ibcon#read 6, iclass 16, count 0 2006.285.12:56:49.92#ibcon#end of sib2, iclass 16, count 0 2006.285.12:56:49.92#ibcon#*after write, iclass 16, count 0 2006.285.12:56:49.92#ibcon#*before return 0, iclass 16, count 0 2006.285.12:56:49.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:56:49.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:56:49.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.12:56:49.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.12:56:49.92$vck44/va=5,3 2006.285.12:56:49.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.12:56:49.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.12:56:49.92#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:49.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:56:49.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:56:49.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:56:49.98#ibcon#enter wrdev, iclass 18, count 2 2006.285.12:56:49.98#ibcon#first serial, iclass 18, count 2 2006.285.12:56:49.98#ibcon#enter sib2, iclass 18, count 2 2006.285.12:56:49.98#ibcon#flushed, iclass 18, count 2 2006.285.12:56:49.98#ibcon#about to write, iclass 18, count 2 2006.285.12:56:49.98#ibcon#wrote, iclass 18, count 2 2006.285.12:56:49.98#ibcon#about to read 3, iclass 18, count 2 2006.285.12:56:50.00#ibcon#read 3, iclass 18, count 2 2006.285.12:56:50.00#ibcon#about to read 4, iclass 18, count 2 2006.285.12:56:50.00#ibcon#read 4, iclass 18, count 2 2006.285.12:56:50.00#ibcon#about to read 5, iclass 18, count 2 2006.285.12:56:50.00#ibcon#read 5, iclass 18, count 2 2006.285.12:56:50.00#ibcon#about to read 6, iclass 18, count 2 2006.285.12:56:50.00#ibcon#read 6, iclass 18, count 2 2006.285.12:56:50.00#ibcon#end of sib2, iclass 18, count 2 2006.285.12:56:50.00#ibcon#*mode == 0, iclass 18, count 2 2006.285.12:56:50.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.12:56:50.00#ibcon#[25=AT05-03\r\n] 2006.285.12:56:50.00#ibcon#*before write, iclass 18, count 2 2006.285.12:56:50.00#ibcon#enter sib2, iclass 18, count 2 2006.285.12:56:50.00#ibcon#flushed, iclass 18, count 2 2006.285.12:56:50.00#ibcon#about to write, iclass 18, count 2 2006.285.12:56:50.00#ibcon#wrote, iclass 18, count 2 2006.285.12:56:50.00#ibcon#about to read 3, iclass 18, count 2 2006.285.12:56:50.03#ibcon#read 3, iclass 18, count 2 2006.285.12:56:50.03#ibcon#about to read 4, iclass 18, count 2 2006.285.12:56:50.03#ibcon#read 4, iclass 18, count 2 2006.285.12:56:50.03#ibcon#about to read 5, iclass 18, count 2 2006.285.12:56:50.03#ibcon#read 5, iclass 18, count 2 2006.285.12:56:50.03#ibcon#about to read 6, iclass 18, count 2 2006.285.12:56:50.03#ibcon#read 6, iclass 18, count 2 2006.285.12:56:50.03#ibcon#end of sib2, iclass 18, count 2 2006.285.12:56:50.03#ibcon#*after write, iclass 18, count 2 2006.285.12:56:50.03#ibcon#*before return 0, iclass 18, count 2 2006.285.12:56:50.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:56:50.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:56:50.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.12:56:50.03#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:50.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:56:50.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:56:50.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:56:50.15#ibcon#enter wrdev, iclass 18, count 0 2006.285.12:56:50.15#ibcon#first serial, iclass 18, count 0 2006.285.12:56:50.15#ibcon#enter sib2, iclass 18, count 0 2006.285.12:56:50.15#ibcon#flushed, iclass 18, count 0 2006.285.12:56:50.15#ibcon#about to write, iclass 18, count 0 2006.285.12:56:50.15#ibcon#wrote, iclass 18, count 0 2006.285.12:56:50.15#ibcon#about to read 3, iclass 18, count 0 2006.285.12:56:50.17#ibcon#read 3, iclass 18, count 0 2006.285.12:56:50.17#ibcon#about to read 4, iclass 18, count 0 2006.285.12:56:50.17#ibcon#read 4, iclass 18, count 0 2006.285.12:56:50.17#ibcon#about to read 5, iclass 18, count 0 2006.285.12:56:50.17#ibcon#read 5, iclass 18, count 0 2006.285.12:56:50.17#ibcon#about to read 6, iclass 18, count 0 2006.285.12:56:50.17#ibcon#read 6, iclass 18, count 0 2006.285.12:56:50.17#ibcon#end of sib2, iclass 18, count 0 2006.285.12:56:50.17#ibcon#*mode == 0, iclass 18, count 0 2006.285.12:56:50.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.12:56:50.17#ibcon#[25=USB\r\n] 2006.285.12:56:50.17#ibcon#*before write, iclass 18, count 0 2006.285.12:56:50.17#ibcon#enter sib2, iclass 18, count 0 2006.285.12:56:50.17#ibcon#flushed, iclass 18, count 0 2006.285.12:56:50.17#ibcon#about to write, iclass 18, count 0 2006.285.12:56:50.17#ibcon#wrote, iclass 18, count 0 2006.285.12:56:50.17#ibcon#about to read 3, iclass 18, count 0 2006.285.12:56:50.20#ibcon#read 3, iclass 18, count 0 2006.285.12:56:50.20#ibcon#about to read 4, iclass 18, count 0 2006.285.12:56:50.20#ibcon#read 4, iclass 18, count 0 2006.285.12:56:50.20#ibcon#about to read 5, iclass 18, count 0 2006.285.12:56:50.20#ibcon#read 5, iclass 18, count 0 2006.285.12:56:50.20#ibcon#about to read 6, iclass 18, count 0 2006.285.12:56:50.20#ibcon#read 6, iclass 18, count 0 2006.285.12:56:50.20#ibcon#end of sib2, iclass 18, count 0 2006.285.12:56:50.20#ibcon#*after write, iclass 18, count 0 2006.285.12:56:50.20#ibcon#*before return 0, iclass 18, count 0 2006.285.12:56:50.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:56:50.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:56:50.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.12:56:50.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.12:56:50.20$vck44/valo=6,814.99 2006.285.12:56:50.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.12:56:50.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.12:56:50.20#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:50.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:56:50.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:56:50.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:56:50.20#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:56:50.20#ibcon#first serial, iclass 20, count 0 2006.285.12:56:50.20#ibcon#enter sib2, iclass 20, count 0 2006.285.12:56:50.20#ibcon#flushed, iclass 20, count 0 2006.285.12:56:50.20#ibcon#about to write, iclass 20, count 0 2006.285.12:56:50.20#ibcon#wrote, iclass 20, count 0 2006.285.12:56:50.20#ibcon#about to read 3, iclass 20, count 0 2006.285.12:56:50.22#ibcon#read 3, iclass 20, count 0 2006.285.12:56:50.22#ibcon#about to read 4, iclass 20, count 0 2006.285.12:56:50.22#ibcon#read 4, iclass 20, count 0 2006.285.12:56:50.48#ibcon#about to read 5, iclass 20, count 0 2006.285.12:56:50.48#ibcon#read 5, iclass 20, count 0 2006.285.12:56:50.48#ibcon#about to read 6, iclass 20, count 0 2006.285.12:56:50.48#ibcon#read 6, iclass 20, count 0 2006.285.12:56:50.48#ibcon#end of sib2, iclass 20, count 0 2006.285.12:56:50.48#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:56:50.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:56:50.48#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.12:56:50.48#ibcon#*before write, iclass 20, count 0 2006.285.12:56:50.48#ibcon#enter sib2, iclass 20, count 0 2006.285.12:56:50.48#ibcon#flushed, iclass 20, count 0 2006.285.12:56:50.48#ibcon#about to write, iclass 20, count 0 2006.285.12:56:50.48#ibcon#wrote, iclass 20, count 0 2006.285.12:56:50.48#ibcon#about to read 3, iclass 20, count 0 2006.285.12:56:50.52#ibcon#read 3, iclass 20, count 0 2006.285.12:56:50.52#ibcon#about to read 4, iclass 20, count 0 2006.285.12:56:50.52#ibcon#read 4, iclass 20, count 0 2006.285.12:56:50.52#ibcon#about to read 5, iclass 20, count 0 2006.285.12:56:50.52#ibcon#read 5, iclass 20, count 0 2006.285.12:56:50.52#ibcon#about to read 6, iclass 20, count 0 2006.285.12:56:50.52#ibcon#read 6, iclass 20, count 0 2006.285.12:56:50.52#ibcon#end of sib2, iclass 20, count 0 2006.285.12:56:50.52#ibcon#*after write, iclass 20, count 0 2006.285.12:56:50.52#ibcon#*before return 0, iclass 20, count 0 2006.285.12:56:50.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:56:50.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:56:50.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:56:50.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:56:50.52$vck44/va=6,4 2006.285.12:56:50.52#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.12:56:50.52#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.12:56:50.52#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:50.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:56:50.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:56:50.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:56:50.52#ibcon#enter wrdev, iclass 22, count 2 2006.285.12:56:50.52#ibcon#first serial, iclass 22, count 2 2006.285.12:56:50.52#ibcon#enter sib2, iclass 22, count 2 2006.285.12:56:50.52#ibcon#flushed, iclass 22, count 2 2006.285.12:56:50.52#ibcon#about to write, iclass 22, count 2 2006.285.12:56:50.52#ibcon#wrote, iclass 22, count 2 2006.285.12:56:50.52#ibcon#about to read 3, iclass 22, count 2 2006.285.12:56:50.54#ibcon#read 3, iclass 22, count 2 2006.285.12:56:50.54#ibcon#about to read 4, iclass 22, count 2 2006.285.12:56:50.54#ibcon#read 4, iclass 22, count 2 2006.285.12:56:50.54#ibcon#about to read 5, iclass 22, count 2 2006.285.12:56:50.54#ibcon#read 5, iclass 22, count 2 2006.285.12:56:50.54#ibcon#about to read 6, iclass 22, count 2 2006.285.12:56:50.54#ibcon#read 6, iclass 22, count 2 2006.285.12:56:50.54#ibcon#end of sib2, iclass 22, count 2 2006.285.12:56:50.54#ibcon#*mode == 0, iclass 22, count 2 2006.285.12:56:50.54#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.12:56:50.54#ibcon#[25=AT06-04\r\n] 2006.285.12:56:50.54#ibcon#*before write, iclass 22, count 2 2006.285.12:56:50.54#ibcon#enter sib2, iclass 22, count 2 2006.285.12:56:50.54#ibcon#flushed, iclass 22, count 2 2006.285.12:56:50.54#ibcon#about to write, iclass 22, count 2 2006.285.12:56:50.54#ibcon#wrote, iclass 22, count 2 2006.285.12:56:50.54#ibcon#about to read 3, iclass 22, count 2 2006.285.12:56:50.57#ibcon#read 3, iclass 22, count 2 2006.285.12:56:50.57#ibcon#about to read 4, iclass 22, count 2 2006.285.12:56:50.57#ibcon#read 4, iclass 22, count 2 2006.285.12:56:50.57#ibcon#about to read 5, iclass 22, count 2 2006.285.12:56:50.57#ibcon#read 5, iclass 22, count 2 2006.285.12:56:50.57#ibcon#about to read 6, iclass 22, count 2 2006.285.12:56:50.57#ibcon#read 6, iclass 22, count 2 2006.285.12:56:50.57#ibcon#end of sib2, iclass 22, count 2 2006.285.12:56:50.57#ibcon#*after write, iclass 22, count 2 2006.285.12:56:50.57#ibcon#*before return 0, iclass 22, count 2 2006.285.12:56:50.57#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:56:50.57#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:56:50.57#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.12:56:50.57#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:50.57#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:56:50.69#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:56:50.69#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:56:50.69#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:56:50.69#ibcon#first serial, iclass 22, count 0 2006.285.12:56:50.69#ibcon#enter sib2, iclass 22, count 0 2006.285.12:56:50.69#ibcon#flushed, iclass 22, count 0 2006.285.12:56:50.69#ibcon#about to write, iclass 22, count 0 2006.285.12:56:50.69#ibcon#wrote, iclass 22, count 0 2006.285.12:56:50.69#ibcon#about to read 3, iclass 22, count 0 2006.285.12:56:50.71#ibcon#read 3, iclass 22, count 0 2006.285.12:56:50.71#ibcon#about to read 4, iclass 22, count 0 2006.285.12:56:50.71#ibcon#read 4, iclass 22, count 0 2006.285.12:56:50.71#ibcon#about to read 5, iclass 22, count 0 2006.285.12:56:50.71#ibcon#read 5, iclass 22, count 0 2006.285.12:56:50.71#ibcon#about to read 6, iclass 22, count 0 2006.285.12:56:50.71#ibcon#read 6, iclass 22, count 0 2006.285.12:56:50.71#ibcon#end of sib2, iclass 22, count 0 2006.285.12:56:50.71#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:56:50.71#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:56:50.71#ibcon#[25=USB\r\n] 2006.285.12:56:50.71#ibcon#*before write, iclass 22, count 0 2006.285.12:56:50.71#ibcon#enter sib2, iclass 22, count 0 2006.285.12:56:50.71#ibcon#flushed, iclass 22, count 0 2006.285.12:56:50.71#ibcon#about to write, iclass 22, count 0 2006.285.12:56:50.71#ibcon#wrote, iclass 22, count 0 2006.285.12:56:50.71#ibcon#about to read 3, iclass 22, count 0 2006.285.12:56:50.74#ibcon#read 3, iclass 22, count 0 2006.285.12:56:50.74#ibcon#about to read 4, iclass 22, count 0 2006.285.12:56:50.74#ibcon#read 4, iclass 22, count 0 2006.285.12:56:50.74#ibcon#about to read 5, iclass 22, count 0 2006.285.12:56:50.74#ibcon#read 5, iclass 22, count 0 2006.285.12:56:50.74#ibcon#about to read 6, iclass 22, count 0 2006.285.12:56:50.74#ibcon#read 6, iclass 22, count 0 2006.285.12:56:50.74#ibcon#end of sib2, iclass 22, count 0 2006.285.12:56:50.74#ibcon#*after write, iclass 22, count 0 2006.285.12:56:50.74#ibcon#*before return 0, iclass 22, count 0 2006.285.12:56:50.74#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:56:50.74#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:56:50.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:56:50.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:56:50.74$vck44/valo=7,864.99 2006.285.12:56:50.74#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.12:56:50.74#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.12:56:50.74#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:50.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:56:50.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:56:50.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:56:50.74#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:56:50.74#ibcon#first serial, iclass 24, count 0 2006.285.12:56:50.74#ibcon#enter sib2, iclass 24, count 0 2006.285.12:56:50.74#ibcon#flushed, iclass 24, count 0 2006.285.12:56:50.74#ibcon#about to write, iclass 24, count 0 2006.285.12:56:50.74#ibcon#wrote, iclass 24, count 0 2006.285.12:56:50.74#ibcon#about to read 3, iclass 24, count 0 2006.285.12:56:50.76#ibcon#read 3, iclass 24, count 0 2006.285.12:56:50.76#ibcon#about to read 4, iclass 24, count 0 2006.285.12:56:50.76#ibcon#read 4, iclass 24, count 0 2006.285.12:56:50.76#ibcon#about to read 5, iclass 24, count 0 2006.285.12:56:50.76#ibcon#read 5, iclass 24, count 0 2006.285.12:56:50.76#ibcon#about to read 6, iclass 24, count 0 2006.285.12:56:50.76#ibcon#read 6, iclass 24, count 0 2006.285.12:56:50.76#ibcon#end of sib2, iclass 24, count 0 2006.285.12:56:50.76#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:56:50.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:56:50.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.12:56:50.76#ibcon#*before write, iclass 24, count 0 2006.285.12:56:50.76#ibcon#enter sib2, iclass 24, count 0 2006.285.12:56:50.76#ibcon#flushed, iclass 24, count 0 2006.285.12:56:50.76#ibcon#about to write, iclass 24, count 0 2006.285.12:56:50.76#ibcon#wrote, iclass 24, count 0 2006.285.12:56:50.76#ibcon#about to read 3, iclass 24, count 0 2006.285.12:56:50.80#ibcon#read 3, iclass 24, count 0 2006.285.12:56:50.80#ibcon#about to read 4, iclass 24, count 0 2006.285.12:56:50.80#ibcon#read 4, iclass 24, count 0 2006.285.12:56:50.80#ibcon#about to read 5, iclass 24, count 0 2006.285.12:56:50.80#ibcon#read 5, iclass 24, count 0 2006.285.12:56:50.80#ibcon#about to read 6, iclass 24, count 0 2006.285.12:56:50.80#ibcon#read 6, iclass 24, count 0 2006.285.12:56:50.80#ibcon#end of sib2, iclass 24, count 0 2006.285.12:56:50.80#ibcon#*after write, iclass 24, count 0 2006.285.12:56:50.80#ibcon#*before return 0, iclass 24, count 0 2006.285.12:56:50.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:56:50.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:56:50.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:56:50.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:56:50.80$vck44/va=7,4 2006.285.12:56:50.80#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.12:56:50.80#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.12:56:50.80#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:50.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:56:50.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:56:50.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:56:50.86#ibcon#enter wrdev, iclass 26, count 2 2006.285.12:56:50.86#ibcon#first serial, iclass 26, count 2 2006.285.12:56:50.86#ibcon#enter sib2, iclass 26, count 2 2006.285.12:56:50.86#ibcon#flushed, iclass 26, count 2 2006.285.12:56:50.86#ibcon#about to write, iclass 26, count 2 2006.285.12:56:50.86#ibcon#wrote, iclass 26, count 2 2006.285.12:56:50.86#ibcon#about to read 3, iclass 26, count 2 2006.285.12:56:50.88#ibcon#read 3, iclass 26, count 2 2006.285.12:56:50.88#ibcon#about to read 4, iclass 26, count 2 2006.285.12:56:50.88#ibcon#read 4, iclass 26, count 2 2006.285.12:56:50.88#ibcon#about to read 5, iclass 26, count 2 2006.285.12:56:50.88#ibcon#read 5, iclass 26, count 2 2006.285.12:56:50.88#ibcon#about to read 6, iclass 26, count 2 2006.285.12:56:50.88#ibcon#read 6, iclass 26, count 2 2006.285.12:56:50.88#ibcon#end of sib2, iclass 26, count 2 2006.285.12:56:50.88#ibcon#*mode == 0, iclass 26, count 2 2006.285.12:56:50.88#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.12:56:50.88#ibcon#[25=AT07-04\r\n] 2006.285.12:56:50.88#ibcon#*before write, iclass 26, count 2 2006.285.12:56:50.88#ibcon#enter sib2, iclass 26, count 2 2006.285.12:56:50.88#ibcon#flushed, iclass 26, count 2 2006.285.12:56:50.88#ibcon#about to write, iclass 26, count 2 2006.285.12:56:50.88#ibcon#wrote, iclass 26, count 2 2006.285.12:56:50.88#ibcon#about to read 3, iclass 26, count 2 2006.285.12:56:50.91#ibcon#read 3, iclass 26, count 2 2006.285.12:56:50.91#ibcon#about to read 4, iclass 26, count 2 2006.285.12:56:50.91#ibcon#read 4, iclass 26, count 2 2006.285.12:56:50.91#ibcon#about to read 5, iclass 26, count 2 2006.285.12:56:50.91#ibcon#read 5, iclass 26, count 2 2006.285.12:56:50.91#ibcon#about to read 6, iclass 26, count 2 2006.285.12:56:50.91#ibcon#read 6, iclass 26, count 2 2006.285.12:56:50.91#ibcon#end of sib2, iclass 26, count 2 2006.285.12:56:50.91#ibcon#*after write, iclass 26, count 2 2006.285.12:56:50.91#ibcon#*before return 0, iclass 26, count 2 2006.285.12:56:50.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:56:50.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:56:50.91#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.12:56:50.91#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:50.91#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:56:51.03#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:56:51.03#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:56:51.03#ibcon#enter wrdev, iclass 26, count 0 2006.285.12:56:51.03#ibcon#first serial, iclass 26, count 0 2006.285.12:56:51.03#ibcon#enter sib2, iclass 26, count 0 2006.285.12:56:51.03#ibcon#flushed, iclass 26, count 0 2006.285.12:56:51.03#ibcon#about to write, iclass 26, count 0 2006.285.12:56:51.03#ibcon#wrote, iclass 26, count 0 2006.285.12:56:51.03#ibcon#about to read 3, iclass 26, count 0 2006.285.12:56:51.05#ibcon#read 3, iclass 26, count 0 2006.285.12:56:51.05#ibcon#about to read 4, iclass 26, count 0 2006.285.12:56:51.05#ibcon#read 4, iclass 26, count 0 2006.285.12:56:51.05#ibcon#about to read 5, iclass 26, count 0 2006.285.12:56:51.05#ibcon#read 5, iclass 26, count 0 2006.285.12:56:51.05#ibcon#about to read 6, iclass 26, count 0 2006.285.12:56:51.05#ibcon#read 6, iclass 26, count 0 2006.285.12:56:51.05#ibcon#end of sib2, iclass 26, count 0 2006.285.12:56:51.05#ibcon#*mode == 0, iclass 26, count 0 2006.285.12:56:51.05#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.12:56:51.05#ibcon#[25=USB\r\n] 2006.285.12:56:51.05#ibcon#*before write, iclass 26, count 0 2006.285.12:56:51.05#ibcon#enter sib2, iclass 26, count 0 2006.285.12:56:51.05#ibcon#flushed, iclass 26, count 0 2006.285.12:56:51.05#ibcon#about to write, iclass 26, count 0 2006.285.12:56:51.05#ibcon#wrote, iclass 26, count 0 2006.285.12:56:51.05#ibcon#about to read 3, iclass 26, count 0 2006.285.12:56:51.08#ibcon#read 3, iclass 26, count 0 2006.285.12:56:51.08#ibcon#about to read 4, iclass 26, count 0 2006.285.12:56:51.08#ibcon#read 4, iclass 26, count 0 2006.285.12:56:51.08#ibcon#about to read 5, iclass 26, count 0 2006.285.12:56:51.08#ibcon#read 5, iclass 26, count 0 2006.285.12:56:51.08#ibcon#about to read 6, iclass 26, count 0 2006.285.12:56:51.08#ibcon#read 6, iclass 26, count 0 2006.285.12:56:51.08#ibcon#end of sib2, iclass 26, count 0 2006.285.12:56:51.08#ibcon#*after write, iclass 26, count 0 2006.285.12:56:51.08#ibcon#*before return 0, iclass 26, count 0 2006.285.12:56:51.08#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:56:51.08#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:56:51.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.12:56:51.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.12:56:51.08$vck44/valo=8,884.99 2006.285.12:56:51.08#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.12:56:51.08#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.12:56:51.08#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:51.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:56:51.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:56:51.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:56:51.08#ibcon#enter wrdev, iclass 28, count 0 2006.285.12:56:51.08#ibcon#first serial, iclass 28, count 0 2006.285.12:56:51.08#ibcon#enter sib2, iclass 28, count 0 2006.285.12:56:51.08#ibcon#flushed, iclass 28, count 0 2006.285.12:56:51.08#ibcon#about to write, iclass 28, count 0 2006.285.12:56:51.08#ibcon#wrote, iclass 28, count 0 2006.285.12:56:51.08#ibcon#about to read 3, iclass 28, count 0 2006.285.12:56:51.10#ibcon#read 3, iclass 28, count 0 2006.285.12:56:51.10#ibcon#about to read 4, iclass 28, count 0 2006.285.12:56:51.10#ibcon#read 4, iclass 28, count 0 2006.285.12:56:51.10#ibcon#about to read 5, iclass 28, count 0 2006.285.12:56:51.10#ibcon#read 5, iclass 28, count 0 2006.285.12:56:51.10#ibcon#about to read 6, iclass 28, count 0 2006.285.12:56:51.10#ibcon#read 6, iclass 28, count 0 2006.285.12:56:51.10#ibcon#end of sib2, iclass 28, count 0 2006.285.12:56:51.10#ibcon#*mode == 0, iclass 28, count 0 2006.285.12:56:51.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.12:56:51.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.12:56:51.10#ibcon#*before write, iclass 28, count 0 2006.285.12:56:51.10#ibcon#enter sib2, iclass 28, count 0 2006.285.12:56:51.10#ibcon#flushed, iclass 28, count 0 2006.285.12:56:51.10#ibcon#about to write, iclass 28, count 0 2006.285.12:56:51.10#ibcon#wrote, iclass 28, count 0 2006.285.12:56:51.10#ibcon#about to read 3, iclass 28, count 0 2006.285.12:56:51.14#ibcon#read 3, iclass 28, count 0 2006.285.12:56:51.14#ibcon#about to read 4, iclass 28, count 0 2006.285.12:56:51.14#ibcon#read 4, iclass 28, count 0 2006.285.12:56:51.14#ibcon#about to read 5, iclass 28, count 0 2006.285.12:56:51.14#ibcon#read 5, iclass 28, count 0 2006.285.12:56:51.14#ibcon#about to read 6, iclass 28, count 0 2006.285.12:56:51.14#ibcon#read 6, iclass 28, count 0 2006.285.12:56:51.14#ibcon#end of sib2, iclass 28, count 0 2006.285.12:56:51.14#ibcon#*after write, iclass 28, count 0 2006.285.12:56:51.14#ibcon#*before return 0, iclass 28, count 0 2006.285.12:56:51.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:56:51.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.12:56:51.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.12:56:51.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.12:56:51.14$vck44/va=8,3 2006.285.12:56:51.14#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.12:56:51.14#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.12:56:51.14#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:51.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:56:51.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:56:51.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:56:51.20#ibcon#enter wrdev, iclass 30, count 2 2006.285.12:56:51.20#ibcon#first serial, iclass 30, count 2 2006.285.12:56:51.20#ibcon#enter sib2, iclass 30, count 2 2006.285.12:56:51.20#ibcon#flushed, iclass 30, count 2 2006.285.12:56:51.20#ibcon#about to write, iclass 30, count 2 2006.285.12:56:51.20#ibcon#wrote, iclass 30, count 2 2006.285.12:56:51.20#ibcon#about to read 3, iclass 30, count 2 2006.285.12:56:51.22#ibcon#read 3, iclass 30, count 2 2006.285.12:56:51.22#ibcon#about to read 4, iclass 30, count 2 2006.285.12:56:51.22#ibcon#read 4, iclass 30, count 2 2006.285.12:56:51.22#ibcon#about to read 5, iclass 30, count 2 2006.285.12:56:51.22#ibcon#read 5, iclass 30, count 2 2006.285.12:56:51.22#ibcon#about to read 6, iclass 30, count 2 2006.285.12:56:51.22#ibcon#read 6, iclass 30, count 2 2006.285.12:56:51.22#ibcon#end of sib2, iclass 30, count 2 2006.285.12:56:51.22#ibcon#*mode == 0, iclass 30, count 2 2006.285.12:56:51.22#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.12:56:51.22#ibcon#[25=AT08-03\r\n] 2006.285.12:56:51.22#ibcon#*before write, iclass 30, count 2 2006.285.12:56:51.22#ibcon#enter sib2, iclass 30, count 2 2006.285.12:56:51.22#ibcon#flushed, iclass 30, count 2 2006.285.12:56:51.22#ibcon#about to write, iclass 30, count 2 2006.285.12:56:51.22#ibcon#wrote, iclass 30, count 2 2006.285.12:56:51.22#ibcon#about to read 3, iclass 30, count 2 2006.285.12:56:51.25#ibcon#read 3, iclass 30, count 2 2006.285.12:56:51.25#ibcon#about to read 4, iclass 30, count 2 2006.285.12:56:51.25#ibcon#read 4, iclass 30, count 2 2006.285.12:56:51.25#ibcon#about to read 5, iclass 30, count 2 2006.285.12:56:51.25#ibcon#read 5, iclass 30, count 2 2006.285.12:56:51.25#ibcon#about to read 6, iclass 30, count 2 2006.285.12:56:51.25#ibcon#read 6, iclass 30, count 2 2006.285.12:56:51.25#ibcon#end of sib2, iclass 30, count 2 2006.285.12:56:51.25#ibcon#*after write, iclass 30, count 2 2006.285.12:56:51.25#ibcon#*before return 0, iclass 30, count 2 2006.285.12:56:51.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:56:51.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.12:56:51.25#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.12:56:51.25#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:51.25#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:56:51.37#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:56:51.37#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:56:51.37#ibcon#enter wrdev, iclass 30, count 0 2006.285.12:56:51.37#ibcon#first serial, iclass 30, count 0 2006.285.12:56:51.37#ibcon#enter sib2, iclass 30, count 0 2006.285.12:56:51.37#ibcon#flushed, iclass 30, count 0 2006.285.12:56:51.37#ibcon#about to write, iclass 30, count 0 2006.285.12:56:51.37#ibcon#wrote, iclass 30, count 0 2006.285.12:56:51.37#ibcon#about to read 3, iclass 30, count 0 2006.285.12:56:51.39#ibcon#read 3, iclass 30, count 0 2006.285.12:56:51.39#ibcon#about to read 4, iclass 30, count 0 2006.285.12:56:51.39#ibcon#read 4, iclass 30, count 0 2006.285.12:56:51.39#ibcon#about to read 5, iclass 30, count 0 2006.285.12:56:51.39#ibcon#read 5, iclass 30, count 0 2006.285.12:56:51.39#ibcon#about to read 6, iclass 30, count 0 2006.285.12:56:51.39#ibcon#read 6, iclass 30, count 0 2006.285.12:56:51.39#ibcon#end of sib2, iclass 30, count 0 2006.285.12:56:51.39#ibcon#*mode == 0, iclass 30, count 0 2006.285.12:56:51.39#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.12:56:51.39#ibcon#[25=USB\r\n] 2006.285.12:56:51.39#ibcon#*before write, iclass 30, count 0 2006.285.12:56:51.39#ibcon#enter sib2, iclass 30, count 0 2006.285.12:56:51.39#ibcon#flushed, iclass 30, count 0 2006.285.12:56:51.39#ibcon#about to write, iclass 30, count 0 2006.285.12:56:51.39#ibcon#wrote, iclass 30, count 0 2006.285.12:56:51.39#ibcon#about to read 3, iclass 30, count 0 2006.285.12:56:51.42#ibcon#read 3, iclass 30, count 0 2006.285.12:56:51.42#ibcon#about to read 4, iclass 30, count 0 2006.285.12:56:51.42#ibcon#read 4, iclass 30, count 0 2006.285.12:56:51.42#ibcon#about to read 5, iclass 30, count 0 2006.285.12:56:51.42#ibcon#read 5, iclass 30, count 0 2006.285.12:56:51.42#ibcon#about to read 6, iclass 30, count 0 2006.285.12:56:51.42#ibcon#read 6, iclass 30, count 0 2006.285.12:56:51.42#ibcon#end of sib2, iclass 30, count 0 2006.285.12:56:51.42#ibcon#*after write, iclass 30, count 0 2006.285.12:56:51.42#ibcon#*before return 0, iclass 30, count 0 2006.285.12:56:51.42#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:56:51.42#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.12:56:51.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.12:56:51.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.12:56:51.42$vck44/vblo=1,629.99 2006.285.12:56:51.42#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.12:56:51.42#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.12:56:51.42#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:51.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:56:51.42#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:56:51.42#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:56:51.42#ibcon#enter wrdev, iclass 32, count 0 2006.285.12:56:51.42#ibcon#first serial, iclass 32, count 0 2006.285.12:56:51.42#ibcon#enter sib2, iclass 32, count 0 2006.285.12:56:51.42#ibcon#flushed, iclass 32, count 0 2006.285.12:56:51.42#ibcon#about to write, iclass 32, count 0 2006.285.12:56:51.42#ibcon#wrote, iclass 32, count 0 2006.285.12:56:51.42#ibcon#about to read 3, iclass 32, count 0 2006.285.12:56:51.44#ibcon#read 3, iclass 32, count 0 2006.285.12:56:51.44#ibcon#about to read 4, iclass 32, count 0 2006.285.12:56:51.44#ibcon#read 4, iclass 32, count 0 2006.285.12:56:51.44#ibcon#about to read 5, iclass 32, count 0 2006.285.12:56:51.44#ibcon#read 5, iclass 32, count 0 2006.285.12:56:51.44#ibcon#about to read 6, iclass 32, count 0 2006.285.12:56:51.44#ibcon#read 6, iclass 32, count 0 2006.285.12:56:51.44#ibcon#end of sib2, iclass 32, count 0 2006.285.12:56:51.44#ibcon#*mode == 0, iclass 32, count 0 2006.285.12:56:51.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.12:56:51.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.12:56:51.44#ibcon#*before write, iclass 32, count 0 2006.285.12:56:51.44#ibcon#enter sib2, iclass 32, count 0 2006.285.12:56:51.44#ibcon#flushed, iclass 32, count 0 2006.285.12:56:51.44#ibcon#about to write, iclass 32, count 0 2006.285.12:56:51.44#ibcon#wrote, iclass 32, count 0 2006.285.12:56:51.44#ibcon#about to read 3, iclass 32, count 0 2006.285.12:56:51.48#ibcon#read 3, iclass 32, count 0 2006.285.12:56:51.48#ibcon#about to read 4, iclass 32, count 0 2006.285.12:56:51.48#ibcon#read 4, iclass 32, count 0 2006.285.12:56:51.48#ibcon#about to read 5, iclass 32, count 0 2006.285.12:56:51.48#ibcon#read 5, iclass 32, count 0 2006.285.12:56:51.48#ibcon#about to read 6, iclass 32, count 0 2006.285.12:56:51.48#ibcon#read 6, iclass 32, count 0 2006.285.12:56:51.48#ibcon#end of sib2, iclass 32, count 0 2006.285.12:56:51.48#ibcon#*after write, iclass 32, count 0 2006.285.12:56:51.48#ibcon#*before return 0, iclass 32, count 0 2006.285.12:56:51.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:56:51.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.12:56:51.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.12:56:51.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.12:56:51.48$vck44/vb=1,4 2006.285.12:56:51.48#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.12:56:51.48#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.12:56:51.48#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:51.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.12:56:51.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.12:56:51.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.12:56:51.48#ibcon#enter wrdev, iclass 34, count 2 2006.285.12:56:51.48#ibcon#first serial, iclass 34, count 2 2006.285.12:56:51.48#ibcon#enter sib2, iclass 34, count 2 2006.285.12:56:51.48#ibcon#flushed, iclass 34, count 2 2006.285.12:56:51.48#ibcon#about to write, iclass 34, count 2 2006.285.12:56:51.48#ibcon#wrote, iclass 34, count 2 2006.285.12:56:51.48#ibcon#about to read 3, iclass 34, count 2 2006.285.12:56:51.50#ibcon#read 3, iclass 34, count 2 2006.285.12:56:51.50#ibcon#about to read 4, iclass 34, count 2 2006.285.12:56:51.50#ibcon#read 4, iclass 34, count 2 2006.285.12:56:51.50#ibcon#about to read 5, iclass 34, count 2 2006.285.12:56:51.50#ibcon#read 5, iclass 34, count 2 2006.285.12:56:51.50#ibcon#about to read 6, iclass 34, count 2 2006.285.12:56:51.50#ibcon#read 6, iclass 34, count 2 2006.285.12:56:51.50#ibcon#end of sib2, iclass 34, count 2 2006.285.12:56:51.50#ibcon#*mode == 0, iclass 34, count 2 2006.285.12:56:51.50#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.12:56:51.50#ibcon#[27=AT01-04\r\n] 2006.285.12:56:51.50#ibcon#*before write, iclass 34, count 2 2006.285.12:56:51.50#ibcon#enter sib2, iclass 34, count 2 2006.285.12:56:51.50#ibcon#flushed, iclass 34, count 2 2006.285.12:56:51.50#ibcon#about to write, iclass 34, count 2 2006.285.12:56:51.50#ibcon#wrote, iclass 34, count 2 2006.285.12:56:51.50#ibcon#about to read 3, iclass 34, count 2 2006.285.12:56:51.53#ibcon#read 3, iclass 34, count 2 2006.285.12:56:51.53#ibcon#about to read 4, iclass 34, count 2 2006.285.12:56:51.53#ibcon#read 4, iclass 34, count 2 2006.285.12:56:51.53#ibcon#about to read 5, iclass 34, count 2 2006.285.12:56:51.53#ibcon#read 5, iclass 34, count 2 2006.285.12:56:51.53#ibcon#about to read 6, iclass 34, count 2 2006.285.12:56:51.53#ibcon#read 6, iclass 34, count 2 2006.285.12:56:51.53#ibcon#end of sib2, iclass 34, count 2 2006.285.12:56:51.53#ibcon#*after write, iclass 34, count 2 2006.285.12:56:51.53#ibcon#*before return 0, iclass 34, count 2 2006.285.12:56:51.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.12:56:51.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.12:56:51.53#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.12:56:51.53#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:51.53#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.12:56:51.65#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.12:56:51.65#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.12:56:51.65#ibcon#enter wrdev, iclass 34, count 0 2006.285.12:56:51.65#ibcon#first serial, iclass 34, count 0 2006.285.12:56:51.65#ibcon#enter sib2, iclass 34, count 0 2006.285.12:56:51.65#ibcon#flushed, iclass 34, count 0 2006.285.12:56:51.65#ibcon#about to write, iclass 34, count 0 2006.285.12:56:51.65#ibcon#wrote, iclass 34, count 0 2006.285.12:56:51.65#ibcon#about to read 3, iclass 34, count 0 2006.285.12:56:51.67#ibcon#read 3, iclass 34, count 0 2006.285.12:56:51.67#ibcon#about to read 4, iclass 34, count 0 2006.285.12:56:51.67#ibcon#read 4, iclass 34, count 0 2006.285.12:56:51.67#ibcon#about to read 5, iclass 34, count 0 2006.285.12:56:51.67#ibcon#read 5, iclass 34, count 0 2006.285.12:56:51.67#ibcon#about to read 6, iclass 34, count 0 2006.285.12:56:51.67#ibcon#read 6, iclass 34, count 0 2006.285.12:56:51.67#ibcon#end of sib2, iclass 34, count 0 2006.285.12:56:51.67#ibcon#*mode == 0, iclass 34, count 0 2006.285.12:56:51.67#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.12:56:51.67#ibcon#[27=USB\r\n] 2006.285.12:56:51.67#ibcon#*before write, iclass 34, count 0 2006.285.12:56:51.67#ibcon#enter sib2, iclass 34, count 0 2006.285.12:56:51.67#ibcon#flushed, iclass 34, count 0 2006.285.12:56:51.67#ibcon#about to write, iclass 34, count 0 2006.285.12:56:51.67#ibcon#wrote, iclass 34, count 0 2006.285.12:56:51.67#ibcon#about to read 3, iclass 34, count 0 2006.285.12:56:51.70#ibcon#read 3, iclass 34, count 0 2006.285.12:56:51.70#ibcon#about to read 4, iclass 34, count 0 2006.285.12:56:51.70#ibcon#read 4, iclass 34, count 0 2006.285.12:56:51.70#ibcon#about to read 5, iclass 34, count 0 2006.285.12:56:51.70#ibcon#read 5, iclass 34, count 0 2006.285.12:56:51.70#ibcon#about to read 6, iclass 34, count 0 2006.285.12:56:51.70#ibcon#read 6, iclass 34, count 0 2006.285.12:56:51.70#ibcon#end of sib2, iclass 34, count 0 2006.285.12:56:51.70#ibcon#*after write, iclass 34, count 0 2006.285.12:56:51.70#ibcon#*before return 0, iclass 34, count 0 2006.285.12:56:51.70#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.12:56:51.70#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.12:56:51.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.12:56:51.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.12:56:51.70$vck44/vblo=2,634.99 2006.285.12:56:51.70#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.12:56:51.70#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.12:56:51.70#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:51.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:56:51.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:56:51.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:56:51.70#ibcon#enter wrdev, iclass 36, count 0 2006.285.12:56:51.70#ibcon#first serial, iclass 36, count 0 2006.285.12:56:51.70#ibcon#enter sib2, iclass 36, count 0 2006.285.12:56:51.70#ibcon#flushed, iclass 36, count 0 2006.285.12:56:51.70#ibcon#about to write, iclass 36, count 0 2006.285.12:56:51.70#ibcon#wrote, iclass 36, count 0 2006.285.12:56:51.70#ibcon#about to read 3, iclass 36, count 0 2006.285.12:56:51.72#ibcon#read 3, iclass 36, count 0 2006.285.12:56:51.72#ibcon#about to read 4, iclass 36, count 0 2006.285.12:56:51.72#ibcon#read 4, iclass 36, count 0 2006.285.12:56:51.72#ibcon#about to read 5, iclass 36, count 0 2006.285.12:56:51.72#ibcon#read 5, iclass 36, count 0 2006.285.12:56:51.72#ibcon#about to read 6, iclass 36, count 0 2006.285.12:56:51.72#ibcon#read 6, iclass 36, count 0 2006.285.12:56:51.72#ibcon#end of sib2, iclass 36, count 0 2006.285.12:56:51.72#ibcon#*mode == 0, iclass 36, count 0 2006.285.12:56:51.72#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.12:56:51.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.12:56:51.72#ibcon#*before write, iclass 36, count 0 2006.285.12:56:51.72#ibcon#enter sib2, iclass 36, count 0 2006.285.12:56:51.72#ibcon#flushed, iclass 36, count 0 2006.285.12:56:51.72#ibcon#about to write, iclass 36, count 0 2006.285.12:56:51.72#ibcon#wrote, iclass 36, count 0 2006.285.12:56:51.72#ibcon#about to read 3, iclass 36, count 0 2006.285.12:56:51.76#ibcon#read 3, iclass 36, count 0 2006.285.12:56:51.76#ibcon#about to read 4, iclass 36, count 0 2006.285.12:56:51.76#ibcon#read 4, iclass 36, count 0 2006.285.12:56:51.76#ibcon#about to read 5, iclass 36, count 0 2006.285.12:56:51.76#ibcon#read 5, iclass 36, count 0 2006.285.12:56:51.76#ibcon#about to read 6, iclass 36, count 0 2006.285.12:56:51.76#ibcon#read 6, iclass 36, count 0 2006.285.12:56:51.76#ibcon#end of sib2, iclass 36, count 0 2006.285.12:56:51.76#ibcon#*after write, iclass 36, count 0 2006.285.12:56:51.76#ibcon#*before return 0, iclass 36, count 0 2006.285.12:56:51.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:56:51.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.12:56:51.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.12:56:51.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.12:56:51.76$vck44/vb=2,5 2006.285.12:56:51.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.12:56:51.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.12:56:51.76#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:51.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:56:51.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:56:51.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:56:51.82#ibcon#enter wrdev, iclass 38, count 2 2006.285.12:56:51.82#ibcon#first serial, iclass 38, count 2 2006.285.12:56:51.82#ibcon#enter sib2, iclass 38, count 2 2006.285.12:56:51.82#ibcon#flushed, iclass 38, count 2 2006.285.12:56:51.82#ibcon#about to write, iclass 38, count 2 2006.285.12:56:51.82#ibcon#wrote, iclass 38, count 2 2006.285.12:56:51.82#ibcon#about to read 3, iclass 38, count 2 2006.285.12:56:51.84#ibcon#read 3, iclass 38, count 2 2006.285.12:56:51.84#ibcon#about to read 4, iclass 38, count 2 2006.285.12:56:51.84#ibcon#read 4, iclass 38, count 2 2006.285.12:56:51.84#ibcon#about to read 5, iclass 38, count 2 2006.285.12:56:51.84#ibcon#read 5, iclass 38, count 2 2006.285.12:56:51.84#ibcon#about to read 6, iclass 38, count 2 2006.285.12:56:51.84#ibcon#read 6, iclass 38, count 2 2006.285.12:56:51.84#ibcon#end of sib2, iclass 38, count 2 2006.285.12:56:51.84#ibcon#*mode == 0, iclass 38, count 2 2006.285.12:56:51.84#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.12:56:51.84#ibcon#[27=AT02-05\r\n] 2006.285.12:56:51.84#ibcon#*before write, iclass 38, count 2 2006.285.12:56:51.84#ibcon#enter sib2, iclass 38, count 2 2006.285.12:56:51.84#ibcon#flushed, iclass 38, count 2 2006.285.12:56:51.84#ibcon#about to write, iclass 38, count 2 2006.285.12:56:51.84#ibcon#wrote, iclass 38, count 2 2006.285.12:56:51.84#ibcon#about to read 3, iclass 38, count 2 2006.285.12:56:51.87#ibcon#read 3, iclass 38, count 2 2006.285.12:56:51.87#ibcon#about to read 4, iclass 38, count 2 2006.285.12:56:51.87#ibcon#read 4, iclass 38, count 2 2006.285.12:56:51.87#ibcon#about to read 5, iclass 38, count 2 2006.285.12:56:51.87#ibcon#read 5, iclass 38, count 2 2006.285.12:56:51.87#ibcon#about to read 6, iclass 38, count 2 2006.285.12:56:51.87#ibcon#read 6, iclass 38, count 2 2006.285.12:56:51.87#ibcon#end of sib2, iclass 38, count 2 2006.285.12:56:51.87#ibcon#*after write, iclass 38, count 2 2006.285.12:56:51.87#ibcon#*before return 0, iclass 38, count 2 2006.285.12:56:51.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:56:51.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.12:56:51.87#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.12:56:51.87#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:51.87#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:56:51.99#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:56:51.99#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:56:51.99#ibcon#enter wrdev, iclass 38, count 0 2006.285.12:56:51.99#ibcon#first serial, iclass 38, count 0 2006.285.12:56:51.99#ibcon#enter sib2, iclass 38, count 0 2006.285.12:56:51.99#ibcon#flushed, iclass 38, count 0 2006.285.12:56:51.99#ibcon#about to write, iclass 38, count 0 2006.285.12:56:51.99#ibcon#wrote, iclass 38, count 0 2006.285.12:56:51.99#ibcon#about to read 3, iclass 38, count 0 2006.285.12:56:52.01#ibcon#read 3, iclass 38, count 0 2006.285.12:56:52.01#ibcon#about to read 4, iclass 38, count 0 2006.285.12:56:52.01#ibcon#read 4, iclass 38, count 0 2006.285.12:56:52.01#ibcon#about to read 5, iclass 38, count 0 2006.285.12:56:52.01#ibcon#read 5, iclass 38, count 0 2006.285.12:56:52.01#ibcon#about to read 6, iclass 38, count 0 2006.285.12:56:52.01#ibcon#read 6, iclass 38, count 0 2006.285.12:56:52.01#ibcon#end of sib2, iclass 38, count 0 2006.285.12:56:52.01#ibcon#*mode == 0, iclass 38, count 0 2006.285.12:56:52.01#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.12:56:52.01#ibcon#[27=USB\r\n] 2006.285.12:56:52.01#ibcon#*before write, iclass 38, count 0 2006.285.12:56:52.01#ibcon#enter sib2, iclass 38, count 0 2006.285.12:56:52.01#ibcon#flushed, iclass 38, count 0 2006.285.12:56:52.01#ibcon#about to write, iclass 38, count 0 2006.285.12:56:52.01#ibcon#wrote, iclass 38, count 0 2006.285.12:56:52.01#ibcon#about to read 3, iclass 38, count 0 2006.285.12:56:52.04#ibcon#read 3, iclass 38, count 0 2006.285.12:56:52.04#ibcon#about to read 4, iclass 38, count 0 2006.285.12:56:52.04#ibcon#read 4, iclass 38, count 0 2006.285.12:56:52.04#ibcon#about to read 5, iclass 38, count 0 2006.285.12:56:52.04#ibcon#read 5, iclass 38, count 0 2006.285.12:56:52.04#ibcon#about to read 6, iclass 38, count 0 2006.285.12:56:52.04#ibcon#read 6, iclass 38, count 0 2006.285.12:56:52.04#ibcon#end of sib2, iclass 38, count 0 2006.285.12:56:52.04#ibcon#*after write, iclass 38, count 0 2006.285.12:56:52.04#ibcon#*before return 0, iclass 38, count 0 2006.285.12:56:52.04#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:56:52.04#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.12:56:52.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.12:56:52.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.12:56:52.04$vck44/vblo=3,649.99 2006.285.12:56:52.04#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.12:56:52.04#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.12:56:52.04#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:52.04#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:56:52.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:56:52.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:56:52.04#ibcon#enter wrdev, iclass 40, count 0 2006.285.12:56:52.04#ibcon#first serial, iclass 40, count 0 2006.285.12:56:52.04#ibcon#enter sib2, iclass 40, count 0 2006.285.12:56:52.04#ibcon#flushed, iclass 40, count 0 2006.285.12:56:52.04#ibcon#about to write, iclass 40, count 0 2006.285.12:56:52.04#ibcon#wrote, iclass 40, count 0 2006.285.12:56:52.04#ibcon#about to read 3, iclass 40, count 0 2006.285.12:56:52.06#ibcon#read 3, iclass 40, count 0 2006.285.12:56:52.06#ibcon#about to read 4, iclass 40, count 0 2006.285.12:56:52.06#ibcon#read 4, iclass 40, count 0 2006.285.12:56:52.06#ibcon#about to read 5, iclass 40, count 0 2006.285.12:56:52.06#ibcon#read 5, iclass 40, count 0 2006.285.12:56:52.06#ibcon#about to read 6, iclass 40, count 0 2006.285.12:56:52.06#ibcon#read 6, iclass 40, count 0 2006.285.12:56:52.06#ibcon#end of sib2, iclass 40, count 0 2006.285.12:56:52.06#ibcon#*mode == 0, iclass 40, count 0 2006.285.12:56:52.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.12:56:52.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.12:56:52.06#ibcon#*before write, iclass 40, count 0 2006.285.12:56:52.06#ibcon#enter sib2, iclass 40, count 0 2006.285.12:56:52.06#ibcon#flushed, iclass 40, count 0 2006.285.12:56:52.06#ibcon#about to write, iclass 40, count 0 2006.285.12:56:52.06#ibcon#wrote, iclass 40, count 0 2006.285.12:56:52.06#ibcon#about to read 3, iclass 40, count 0 2006.285.12:56:52.10#ibcon#read 3, iclass 40, count 0 2006.285.12:56:52.10#ibcon#about to read 4, iclass 40, count 0 2006.285.12:56:52.10#ibcon#read 4, iclass 40, count 0 2006.285.12:56:52.10#ibcon#about to read 5, iclass 40, count 0 2006.285.12:56:52.10#ibcon#read 5, iclass 40, count 0 2006.285.12:56:52.10#ibcon#about to read 6, iclass 40, count 0 2006.285.12:56:52.10#ibcon#read 6, iclass 40, count 0 2006.285.12:56:52.10#ibcon#end of sib2, iclass 40, count 0 2006.285.12:56:52.10#ibcon#*after write, iclass 40, count 0 2006.285.12:56:52.10#ibcon#*before return 0, iclass 40, count 0 2006.285.12:56:52.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:56:52.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.12:56:52.10#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.12:56:52.10#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.12:56:52.10$vck44/vb=3,4 2006.285.12:56:52.10#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.12:56:52.10#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.12:56:52.10#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:52.10#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:56:52.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:56:52.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:56:52.16#ibcon#enter wrdev, iclass 4, count 2 2006.285.12:56:52.16#ibcon#first serial, iclass 4, count 2 2006.285.12:56:52.16#ibcon#enter sib2, iclass 4, count 2 2006.285.12:56:52.16#ibcon#flushed, iclass 4, count 2 2006.285.12:56:52.16#ibcon#about to write, iclass 4, count 2 2006.285.12:56:52.16#ibcon#wrote, iclass 4, count 2 2006.285.12:56:52.16#ibcon#about to read 3, iclass 4, count 2 2006.285.12:56:52.18#ibcon#read 3, iclass 4, count 2 2006.285.12:56:52.18#ibcon#about to read 4, iclass 4, count 2 2006.285.12:56:52.18#ibcon#read 4, iclass 4, count 2 2006.285.12:56:52.18#ibcon#about to read 5, iclass 4, count 2 2006.285.12:56:52.18#ibcon#read 5, iclass 4, count 2 2006.285.12:56:52.18#ibcon#about to read 6, iclass 4, count 2 2006.285.12:56:52.18#ibcon#read 6, iclass 4, count 2 2006.285.12:56:52.18#ibcon#end of sib2, iclass 4, count 2 2006.285.12:56:52.18#ibcon#*mode == 0, iclass 4, count 2 2006.285.12:56:52.18#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.12:56:52.18#ibcon#[27=AT03-04\r\n] 2006.285.12:56:52.18#ibcon#*before write, iclass 4, count 2 2006.285.12:56:52.18#ibcon#enter sib2, iclass 4, count 2 2006.285.12:56:52.18#ibcon#flushed, iclass 4, count 2 2006.285.12:56:52.18#ibcon#about to write, iclass 4, count 2 2006.285.12:56:52.18#ibcon#wrote, iclass 4, count 2 2006.285.12:56:52.18#ibcon#about to read 3, iclass 4, count 2 2006.285.12:56:52.21#ibcon#read 3, iclass 4, count 2 2006.285.12:56:52.21#ibcon#about to read 4, iclass 4, count 2 2006.285.12:56:52.21#ibcon#read 4, iclass 4, count 2 2006.285.12:56:52.21#ibcon#about to read 5, iclass 4, count 2 2006.285.12:56:52.21#ibcon#read 5, iclass 4, count 2 2006.285.12:56:52.21#ibcon#about to read 6, iclass 4, count 2 2006.285.12:56:52.21#ibcon#read 6, iclass 4, count 2 2006.285.12:56:52.21#ibcon#end of sib2, iclass 4, count 2 2006.285.12:56:52.21#ibcon#*after write, iclass 4, count 2 2006.285.12:56:52.21#ibcon#*before return 0, iclass 4, count 2 2006.285.12:56:52.21#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:56:52.21#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.12:56:52.21#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.12:56:52.21#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:52.21#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:56:52.33#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:56:52.33#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:56:52.33#ibcon#enter wrdev, iclass 4, count 0 2006.285.12:56:52.33#ibcon#first serial, iclass 4, count 0 2006.285.12:56:52.33#ibcon#enter sib2, iclass 4, count 0 2006.285.12:56:52.33#ibcon#flushed, iclass 4, count 0 2006.285.12:56:52.33#ibcon#about to write, iclass 4, count 0 2006.285.12:56:52.33#ibcon#wrote, iclass 4, count 0 2006.285.12:56:52.33#ibcon#about to read 3, iclass 4, count 0 2006.285.12:56:52.35#ibcon#read 3, iclass 4, count 0 2006.285.12:56:52.35#ibcon#about to read 4, iclass 4, count 0 2006.285.12:56:52.35#ibcon#read 4, iclass 4, count 0 2006.285.12:56:52.35#ibcon#about to read 5, iclass 4, count 0 2006.285.12:56:52.35#ibcon#read 5, iclass 4, count 0 2006.285.12:56:52.35#ibcon#about to read 6, iclass 4, count 0 2006.285.12:56:52.35#ibcon#read 6, iclass 4, count 0 2006.285.12:56:52.35#ibcon#end of sib2, iclass 4, count 0 2006.285.12:56:52.35#ibcon#*mode == 0, iclass 4, count 0 2006.285.12:56:52.35#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.12:56:52.35#ibcon#[27=USB\r\n] 2006.285.12:56:52.35#ibcon#*before write, iclass 4, count 0 2006.285.12:56:52.43#ibcon#enter sib2, iclass 4, count 0 2006.285.12:56:52.43#ibcon#flushed, iclass 4, count 0 2006.285.12:56:52.43#ibcon#about to write, iclass 4, count 0 2006.285.12:56:52.43#ibcon#wrote, iclass 4, count 0 2006.285.12:56:52.43#ibcon#about to read 3, iclass 4, count 0 2006.285.12:56:52.46#ibcon#read 3, iclass 4, count 0 2006.285.12:56:52.46#ibcon#about to read 4, iclass 4, count 0 2006.285.12:56:52.46#ibcon#read 4, iclass 4, count 0 2006.285.12:56:52.46#ibcon#about to read 5, iclass 4, count 0 2006.285.12:56:52.46#ibcon#read 5, iclass 4, count 0 2006.285.12:56:52.46#ibcon#about to read 6, iclass 4, count 0 2006.285.12:56:52.46#ibcon#read 6, iclass 4, count 0 2006.285.12:56:52.46#ibcon#end of sib2, iclass 4, count 0 2006.285.12:56:52.46#ibcon#*after write, iclass 4, count 0 2006.285.12:56:52.46#ibcon#*before return 0, iclass 4, count 0 2006.285.12:56:52.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:56:52.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.12:56:52.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.12:56:52.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.12:56:52.46$vck44/vblo=4,679.99 2006.285.12:56:52.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.12:56:52.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.12:56:52.46#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:52.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:56:52.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:56:52.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:56:52.46#ibcon#enter wrdev, iclass 6, count 0 2006.285.12:56:52.46#ibcon#first serial, iclass 6, count 0 2006.285.12:56:52.46#ibcon#enter sib2, iclass 6, count 0 2006.285.12:56:52.46#ibcon#flushed, iclass 6, count 0 2006.285.12:56:52.46#ibcon#about to write, iclass 6, count 0 2006.285.12:56:52.46#ibcon#wrote, iclass 6, count 0 2006.285.12:56:52.46#ibcon#about to read 3, iclass 6, count 0 2006.285.12:56:52.48#ibcon#read 3, iclass 6, count 0 2006.285.12:56:52.48#ibcon#about to read 4, iclass 6, count 0 2006.285.12:56:52.48#ibcon#read 4, iclass 6, count 0 2006.285.12:56:52.48#ibcon#about to read 5, iclass 6, count 0 2006.285.12:56:52.48#ibcon#read 5, iclass 6, count 0 2006.285.12:56:52.48#ibcon#about to read 6, iclass 6, count 0 2006.285.12:56:52.48#ibcon#read 6, iclass 6, count 0 2006.285.12:56:52.48#ibcon#end of sib2, iclass 6, count 0 2006.285.12:56:52.48#ibcon#*mode == 0, iclass 6, count 0 2006.285.12:56:52.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.12:56:52.48#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.12:56:52.48#ibcon#*before write, iclass 6, count 0 2006.285.12:56:52.48#ibcon#enter sib2, iclass 6, count 0 2006.285.12:56:52.48#ibcon#flushed, iclass 6, count 0 2006.285.12:56:52.48#ibcon#about to write, iclass 6, count 0 2006.285.12:56:52.48#ibcon#wrote, iclass 6, count 0 2006.285.12:56:52.48#ibcon#about to read 3, iclass 6, count 0 2006.285.12:56:52.52#ibcon#read 3, iclass 6, count 0 2006.285.12:56:52.52#ibcon#about to read 4, iclass 6, count 0 2006.285.12:56:52.52#ibcon#read 4, iclass 6, count 0 2006.285.12:56:52.52#ibcon#about to read 5, iclass 6, count 0 2006.285.12:56:52.52#ibcon#read 5, iclass 6, count 0 2006.285.12:56:52.52#ibcon#about to read 6, iclass 6, count 0 2006.285.12:56:52.52#ibcon#read 6, iclass 6, count 0 2006.285.12:56:52.52#ibcon#end of sib2, iclass 6, count 0 2006.285.12:56:52.52#ibcon#*after write, iclass 6, count 0 2006.285.12:56:52.52#ibcon#*before return 0, iclass 6, count 0 2006.285.12:56:52.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:56:52.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.12:56:52.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.12:56:52.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.12:56:52.52$vck44/vb=4,5 2006.285.12:56:52.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.12:56:52.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.12:56:52.52#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:52.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:56:52.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:56:52.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:56:52.58#ibcon#enter wrdev, iclass 10, count 2 2006.285.12:56:52.58#ibcon#first serial, iclass 10, count 2 2006.285.12:56:52.58#ibcon#enter sib2, iclass 10, count 2 2006.285.12:56:52.58#ibcon#flushed, iclass 10, count 2 2006.285.12:56:52.58#ibcon#about to write, iclass 10, count 2 2006.285.12:56:52.58#ibcon#wrote, iclass 10, count 2 2006.285.12:56:52.58#ibcon#about to read 3, iclass 10, count 2 2006.285.12:56:52.60#ibcon#read 3, iclass 10, count 2 2006.285.12:56:52.60#ibcon#about to read 4, iclass 10, count 2 2006.285.12:56:52.60#ibcon#read 4, iclass 10, count 2 2006.285.12:56:52.60#ibcon#about to read 5, iclass 10, count 2 2006.285.12:56:52.60#ibcon#read 5, iclass 10, count 2 2006.285.12:56:52.60#ibcon#about to read 6, iclass 10, count 2 2006.285.12:56:52.60#ibcon#read 6, iclass 10, count 2 2006.285.12:56:52.60#ibcon#end of sib2, iclass 10, count 2 2006.285.12:56:52.60#ibcon#*mode == 0, iclass 10, count 2 2006.285.12:56:52.60#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.12:56:52.60#ibcon#[27=AT04-05\r\n] 2006.285.12:56:52.60#ibcon#*before write, iclass 10, count 2 2006.285.12:56:52.60#ibcon#enter sib2, iclass 10, count 2 2006.285.12:56:52.60#ibcon#flushed, iclass 10, count 2 2006.285.12:56:52.60#ibcon#about to write, iclass 10, count 2 2006.285.12:56:52.60#ibcon#wrote, iclass 10, count 2 2006.285.12:56:52.60#ibcon#about to read 3, iclass 10, count 2 2006.285.12:56:52.63#ibcon#read 3, iclass 10, count 2 2006.285.12:56:52.63#ibcon#about to read 4, iclass 10, count 2 2006.285.12:56:52.63#ibcon#read 4, iclass 10, count 2 2006.285.12:56:52.63#ibcon#about to read 5, iclass 10, count 2 2006.285.12:56:52.63#ibcon#read 5, iclass 10, count 2 2006.285.12:56:52.63#ibcon#about to read 6, iclass 10, count 2 2006.285.12:56:52.63#ibcon#read 6, iclass 10, count 2 2006.285.12:56:52.63#ibcon#end of sib2, iclass 10, count 2 2006.285.12:56:52.63#ibcon#*after write, iclass 10, count 2 2006.285.12:56:52.63#ibcon#*before return 0, iclass 10, count 2 2006.285.12:56:52.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:56:52.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.12:56:52.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.12:56:52.63#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:52.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:56:52.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:56:52.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:56:52.75#ibcon#enter wrdev, iclass 10, count 0 2006.285.12:56:52.75#ibcon#first serial, iclass 10, count 0 2006.285.12:56:52.75#ibcon#enter sib2, iclass 10, count 0 2006.285.12:56:52.75#ibcon#flushed, iclass 10, count 0 2006.285.12:56:52.75#ibcon#about to write, iclass 10, count 0 2006.285.12:56:52.75#ibcon#wrote, iclass 10, count 0 2006.285.12:56:52.75#ibcon#about to read 3, iclass 10, count 0 2006.285.12:56:52.77#ibcon#read 3, iclass 10, count 0 2006.285.12:56:52.77#ibcon#about to read 4, iclass 10, count 0 2006.285.12:56:52.77#ibcon#read 4, iclass 10, count 0 2006.285.12:56:52.77#ibcon#about to read 5, iclass 10, count 0 2006.285.12:56:52.77#ibcon#read 5, iclass 10, count 0 2006.285.12:56:52.77#ibcon#about to read 6, iclass 10, count 0 2006.285.12:56:52.77#ibcon#read 6, iclass 10, count 0 2006.285.12:56:52.77#ibcon#end of sib2, iclass 10, count 0 2006.285.12:56:52.77#ibcon#*mode == 0, iclass 10, count 0 2006.285.12:56:52.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.12:56:52.77#ibcon#[27=USB\r\n] 2006.285.12:56:52.77#ibcon#*before write, iclass 10, count 0 2006.285.12:56:52.77#ibcon#enter sib2, iclass 10, count 0 2006.285.12:56:52.77#ibcon#flushed, iclass 10, count 0 2006.285.12:56:52.77#ibcon#about to write, iclass 10, count 0 2006.285.12:56:52.77#ibcon#wrote, iclass 10, count 0 2006.285.12:56:52.77#ibcon#about to read 3, iclass 10, count 0 2006.285.12:56:52.80#ibcon#read 3, iclass 10, count 0 2006.285.12:56:52.80#ibcon#about to read 4, iclass 10, count 0 2006.285.12:56:52.80#ibcon#read 4, iclass 10, count 0 2006.285.12:56:52.80#ibcon#about to read 5, iclass 10, count 0 2006.285.12:56:52.80#ibcon#read 5, iclass 10, count 0 2006.285.12:56:52.80#ibcon#about to read 6, iclass 10, count 0 2006.285.12:56:52.80#ibcon#read 6, iclass 10, count 0 2006.285.12:56:52.80#ibcon#end of sib2, iclass 10, count 0 2006.285.12:56:52.80#ibcon#*after write, iclass 10, count 0 2006.285.12:56:52.80#ibcon#*before return 0, iclass 10, count 0 2006.285.12:56:52.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:56:52.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.12:56:52.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.12:56:52.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.12:56:52.80$vck44/vblo=5,709.99 2006.285.12:56:52.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.12:56:52.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.12:56:52.80#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:52.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:56:52.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:56:52.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:56:52.80#ibcon#enter wrdev, iclass 12, count 0 2006.285.12:56:52.80#ibcon#first serial, iclass 12, count 0 2006.285.12:56:52.80#ibcon#enter sib2, iclass 12, count 0 2006.285.12:56:52.80#ibcon#flushed, iclass 12, count 0 2006.285.12:56:52.80#ibcon#about to write, iclass 12, count 0 2006.285.12:56:52.80#ibcon#wrote, iclass 12, count 0 2006.285.12:56:52.80#ibcon#about to read 3, iclass 12, count 0 2006.285.12:56:52.82#ibcon#read 3, iclass 12, count 0 2006.285.12:56:52.82#ibcon#about to read 4, iclass 12, count 0 2006.285.12:56:52.82#ibcon#read 4, iclass 12, count 0 2006.285.12:56:52.82#ibcon#about to read 5, iclass 12, count 0 2006.285.12:56:52.82#ibcon#read 5, iclass 12, count 0 2006.285.12:56:52.82#ibcon#about to read 6, iclass 12, count 0 2006.285.12:56:52.82#ibcon#read 6, iclass 12, count 0 2006.285.12:56:52.82#ibcon#end of sib2, iclass 12, count 0 2006.285.12:56:52.82#ibcon#*mode == 0, iclass 12, count 0 2006.285.12:56:52.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.12:56:52.82#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.12:56:52.82#ibcon#*before write, iclass 12, count 0 2006.285.12:56:52.82#ibcon#enter sib2, iclass 12, count 0 2006.285.12:56:52.82#ibcon#flushed, iclass 12, count 0 2006.285.12:56:52.82#ibcon#about to write, iclass 12, count 0 2006.285.12:56:52.82#ibcon#wrote, iclass 12, count 0 2006.285.12:56:52.82#ibcon#about to read 3, iclass 12, count 0 2006.285.12:56:52.86#ibcon#read 3, iclass 12, count 0 2006.285.12:56:52.86#ibcon#about to read 4, iclass 12, count 0 2006.285.12:56:52.86#ibcon#read 4, iclass 12, count 0 2006.285.12:56:52.86#ibcon#about to read 5, iclass 12, count 0 2006.285.12:56:52.86#ibcon#read 5, iclass 12, count 0 2006.285.12:56:52.86#ibcon#about to read 6, iclass 12, count 0 2006.285.12:56:52.86#ibcon#read 6, iclass 12, count 0 2006.285.12:56:52.86#ibcon#end of sib2, iclass 12, count 0 2006.285.12:56:52.86#ibcon#*after write, iclass 12, count 0 2006.285.12:56:52.86#ibcon#*before return 0, iclass 12, count 0 2006.285.12:56:52.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:56:52.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.12:56:52.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.12:56:52.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.12:56:52.86$vck44/vb=5,4 2006.285.12:56:52.86#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.12:56:52.86#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.12:56:52.86#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:52.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:56:52.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:56:52.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:56:52.92#ibcon#enter wrdev, iclass 14, count 2 2006.285.12:56:52.92#ibcon#first serial, iclass 14, count 2 2006.285.12:56:52.92#ibcon#enter sib2, iclass 14, count 2 2006.285.12:56:52.92#ibcon#flushed, iclass 14, count 2 2006.285.12:56:52.92#ibcon#about to write, iclass 14, count 2 2006.285.12:56:52.92#ibcon#wrote, iclass 14, count 2 2006.285.12:56:52.92#ibcon#about to read 3, iclass 14, count 2 2006.285.12:56:52.94#ibcon#read 3, iclass 14, count 2 2006.285.12:56:52.94#ibcon#about to read 4, iclass 14, count 2 2006.285.12:56:52.94#ibcon#read 4, iclass 14, count 2 2006.285.12:56:52.94#ibcon#about to read 5, iclass 14, count 2 2006.285.12:56:52.94#ibcon#read 5, iclass 14, count 2 2006.285.12:56:52.94#ibcon#about to read 6, iclass 14, count 2 2006.285.12:56:52.94#ibcon#read 6, iclass 14, count 2 2006.285.12:56:52.94#ibcon#end of sib2, iclass 14, count 2 2006.285.12:56:52.94#ibcon#*mode == 0, iclass 14, count 2 2006.285.12:56:52.94#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.12:56:52.94#ibcon#[27=AT05-04\r\n] 2006.285.12:56:52.94#ibcon#*before write, iclass 14, count 2 2006.285.12:56:52.94#ibcon#enter sib2, iclass 14, count 2 2006.285.12:56:52.94#ibcon#flushed, iclass 14, count 2 2006.285.12:56:52.94#ibcon#about to write, iclass 14, count 2 2006.285.12:56:52.94#ibcon#wrote, iclass 14, count 2 2006.285.12:56:52.94#ibcon#about to read 3, iclass 14, count 2 2006.285.12:56:52.97#ibcon#read 3, iclass 14, count 2 2006.285.12:56:52.97#ibcon#about to read 4, iclass 14, count 2 2006.285.12:56:52.97#ibcon#read 4, iclass 14, count 2 2006.285.12:56:52.97#ibcon#about to read 5, iclass 14, count 2 2006.285.12:56:52.97#ibcon#read 5, iclass 14, count 2 2006.285.12:56:52.97#ibcon#about to read 6, iclass 14, count 2 2006.285.12:56:52.97#ibcon#read 6, iclass 14, count 2 2006.285.12:56:52.97#ibcon#end of sib2, iclass 14, count 2 2006.285.12:56:52.97#ibcon#*after write, iclass 14, count 2 2006.285.12:56:52.97#ibcon#*before return 0, iclass 14, count 2 2006.285.12:56:52.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:56:52.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.12:56:52.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.12:56:52.97#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:52.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:56:53.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:56:53.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:56:53.09#ibcon#enter wrdev, iclass 14, count 0 2006.285.12:56:53.09#ibcon#first serial, iclass 14, count 0 2006.285.12:56:53.09#ibcon#enter sib2, iclass 14, count 0 2006.285.12:56:53.09#ibcon#flushed, iclass 14, count 0 2006.285.12:56:53.09#ibcon#about to write, iclass 14, count 0 2006.285.12:56:53.09#ibcon#wrote, iclass 14, count 0 2006.285.12:56:53.09#ibcon#about to read 3, iclass 14, count 0 2006.285.12:56:53.11#ibcon#read 3, iclass 14, count 0 2006.285.12:56:53.11#ibcon#about to read 4, iclass 14, count 0 2006.285.12:56:53.11#ibcon#read 4, iclass 14, count 0 2006.285.12:56:53.11#ibcon#about to read 5, iclass 14, count 0 2006.285.12:56:53.11#ibcon#read 5, iclass 14, count 0 2006.285.12:56:53.11#ibcon#about to read 6, iclass 14, count 0 2006.285.12:56:53.11#ibcon#read 6, iclass 14, count 0 2006.285.12:56:53.11#ibcon#end of sib2, iclass 14, count 0 2006.285.12:56:53.11#ibcon#*mode == 0, iclass 14, count 0 2006.285.12:56:53.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.12:56:53.11#ibcon#[27=USB\r\n] 2006.285.12:56:53.11#ibcon#*before write, iclass 14, count 0 2006.285.12:56:53.11#ibcon#enter sib2, iclass 14, count 0 2006.285.12:56:53.11#ibcon#flushed, iclass 14, count 0 2006.285.12:56:53.11#ibcon#about to write, iclass 14, count 0 2006.285.12:56:53.11#ibcon#wrote, iclass 14, count 0 2006.285.12:56:53.11#ibcon#about to read 3, iclass 14, count 0 2006.285.12:56:53.14#ibcon#read 3, iclass 14, count 0 2006.285.12:56:53.14#ibcon#about to read 4, iclass 14, count 0 2006.285.12:56:53.14#ibcon#read 4, iclass 14, count 0 2006.285.12:56:53.14#ibcon#about to read 5, iclass 14, count 0 2006.285.12:56:53.14#ibcon#read 5, iclass 14, count 0 2006.285.12:56:53.14#ibcon#about to read 6, iclass 14, count 0 2006.285.12:56:53.14#ibcon#read 6, iclass 14, count 0 2006.285.12:56:53.14#ibcon#end of sib2, iclass 14, count 0 2006.285.12:56:53.14#ibcon#*after write, iclass 14, count 0 2006.285.12:56:53.14#ibcon#*before return 0, iclass 14, count 0 2006.285.12:56:53.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:56:53.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.12:56:53.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.12:56:53.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.12:56:53.14$vck44/vblo=6,719.99 2006.285.12:56:53.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.12:56:53.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.12:56:53.14#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:53.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:56:53.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:56:53.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:56:53.14#ibcon#enter wrdev, iclass 16, count 0 2006.285.12:56:53.14#ibcon#first serial, iclass 16, count 0 2006.285.12:56:53.14#ibcon#enter sib2, iclass 16, count 0 2006.285.12:56:53.14#ibcon#flushed, iclass 16, count 0 2006.285.12:56:53.14#ibcon#about to write, iclass 16, count 0 2006.285.12:56:53.14#ibcon#wrote, iclass 16, count 0 2006.285.12:56:53.14#ibcon#about to read 3, iclass 16, count 0 2006.285.12:56:53.16#ibcon#read 3, iclass 16, count 0 2006.285.12:56:53.16#ibcon#about to read 4, iclass 16, count 0 2006.285.12:56:53.16#ibcon#read 4, iclass 16, count 0 2006.285.12:56:53.16#ibcon#about to read 5, iclass 16, count 0 2006.285.12:56:53.16#ibcon#read 5, iclass 16, count 0 2006.285.12:56:53.16#ibcon#about to read 6, iclass 16, count 0 2006.285.12:56:53.16#ibcon#read 6, iclass 16, count 0 2006.285.12:56:53.16#ibcon#end of sib2, iclass 16, count 0 2006.285.12:56:53.16#ibcon#*mode == 0, iclass 16, count 0 2006.285.12:56:53.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.12:56:53.16#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.12:56:53.16#ibcon#*before write, iclass 16, count 0 2006.285.12:56:53.16#ibcon#enter sib2, iclass 16, count 0 2006.285.12:56:53.16#ibcon#flushed, iclass 16, count 0 2006.285.12:56:53.16#ibcon#about to write, iclass 16, count 0 2006.285.12:56:53.16#ibcon#wrote, iclass 16, count 0 2006.285.12:56:53.16#ibcon#about to read 3, iclass 16, count 0 2006.285.12:56:53.20#ibcon#read 3, iclass 16, count 0 2006.285.12:56:53.20#ibcon#about to read 4, iclass 16, count 0 2006.285.12:56:53.20#ibcon#read 4, iclass 16, count 0 2006.285.12:56:53.20#ibcon#about to read 5, iclass 16, count 0 2006.285.12:56:53.20#ibcon#read 5, iclass 16, count 0 2006.285.12:56:53.20#ibcon#about to read 6, iclass 16, count 0 2006.285.12:56:53.20#ibcon#read 6, iclass 16, count 0 2006.285.12:56:53.20#ibcon#end of sib2, iclass 16, count 0 2006.285.12:56:53.20#ibcon#*after write, iclass 16, count 0 2006.285.12:56:53.20#ibcon#*before return 0, iclass 16, count 0 2006.285.12:56:53.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:56:53.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.12:56:53.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.12:56:53.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.12:56:53.20$vck44/vb=6,3 2006.285.12:56:53.20#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.12:56:53.20#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.12:56:53.20#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:53.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:56:53.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:56:53.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:56:53.26#ibcon#enter wrdev, iclass 18, count 2 2006.285.12:56:53.26#ibcon#first serial, iclass 18, count 2 2006.285.12:56:53.26#ibcon#enter sib2, iclass 18, count 2 2006.285.12:56:53.26#ibcon#flushed, iclass 18, count 2 2006.285.12:56:53.26#ibcon#about to write, iclass 18, count 2 2006.285.12:56:53.26#ibcon#wrote, iclass 18, count 2 2006.285.12:56:53.26#ibcon#about to read 3, iclass 18, count 2 2006.285.12:56:53.28#ibcon#read 3, iclass 18, count 2 2006.285.12:56:53.28#ibcon#about to read 4, iclass 18, count 2 2006.285.12:56:53.28#ibcon#read 4, iclass 18, count 2 2006.285.12:56:53.28#ibcon#about to read 5, iclass 18, count 2 2006.285.12:56:53.28#ibcon#read 5, iclass 18, count 2 2006.285.12:56:53.28#ibcon#about to read 6, iclass 18, count 2 2006.285.12:56:53.28#ibcon#read 6, iclass 18, count 2 2006.285.12:56:53.28#ibcon#end of sib2, iclass 18, count 2 2006.285.12:56:53.28#ibcon#*mode == 0, iclass 18, count 2 2006.285.12:56:53.28#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.12:56:53.28#ibcon#[27=AT06-03\r\n] 2006.285.12:56:53.28#ibcon#*before write, iclass 18, count 2 2006.285.12:56:53.28#ibcon#enter sib2, iclass 18, count 2 2006.285.12:56:53.28#ibcon#flushed, iclass 18, count 2 2006.285.12:56:53.28#ibcon#about to write, iclass 18, count 2 2006.285.12:56:53.28#ibcon#wrote, iclass 18, count 2 2006.285.12:56:53.28#ibcon#about to read 3, iclass 18, count 2 2006.285.12:56:53.31#ibcon#read 3, iclass 18, count 2 2006.285.12:56:53.31#ibcon#about to read 4, iclass 18, count 2 2006.285.12:56:53.31#ibcon#read 4, iclass 18, count 2 2006.285.12:56:53.31#ibcon#about to read 5, iclass 18, count 2 2006.285.12:56:53.31#ibcon#read 5, iclass 18, count 2 2006.285.12:56:53.31#ibcon#about to read 6, iclass 18, count 2 2006.285.12:56:53.31#ibcon#read 6, iclass 18, count 2 2006.285.12:56:53.31#ibcon#end of sib2, iclass 18, count 2 2006.285.12:56:53.31#ibcon#*after write, iclass 18, count 2 2006.285.12:56:53.31#ibcon#*before return 0, iclass 18, count 2 2006.285.12:56:53.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:56:53.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.12:56:53.31#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.12:56:53.31#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:53.31#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:56:53.43#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:56:53.43#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:56:53.43#ibcon#enter wrdev, iclass 18, count 0 2006.285.12:56:53.43#ibcon#first serial, iclass 18, count 0 2006.285.12:56:53.43#ibcon#enter sib2, iclass 18, count 0 2006.285.12:56:53.43#ibcon#flushed, iclass 18, count 0 2006.285.12:56:53.43#ibcon#about to write, iclass 18, count 0 2006.285.12:56:53.43#ibcon#wrote, iclass 18, count 0 2006.285.12:56:53.43#ibcon#about to read 3, iclass 18, count 0 2006.285.12:56:53.45#ibcon#read 3, iclass 18, count 0 2006.285.12:56:53.45#ibcon#about to read 4, iclass 18, count 0 2006.285.12:56:53.45#ibcon#read 4, iclass 18, count 0 2006.285.12:56:53.45#ibcon#about to read 5, iclass 18, count 0 2006.285.12:56:53.45#ibcon#read 5, iclass 18, count 0 2006.285.12:56:53.45#ibcon#about to read 6, iclass 18, count 0 2006.285.12:56:53.45#ibcon#read 6, iclass 18, count 0 2006.285.12:56:53.45#ibcon#end of sib2, iclass 18, count 0 2006.285.12:56:53.45#ibcon#*mode == 0, iclass 18, count 0 2006.285.12:56:53.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.12:56:53.45#ibcon#[27=USB\r\n] 2006.285.12:56:53.45#ibcon#*before write, iclass 18, count 0 2006.285.12:56:53.45#ibcon#enter sib2, iclass 18, count 0 2006.285.12:56:53.45#ibcon#flushed, iclass 18, count 0 2006.285.12:56:53.45#ibcon#about to write, iclass 18, count 0 2006.285.12:56:53.45#ibcon#wrote, iclass 18, count 0 2006.285.12:56:53.45#ibcon#about to read 3, iclass 18, count 0 2006.285.12:56:53.48#ibcon#read 3, iclass 18, count 0 2006.285.12:56:53.48#ibcon#about to read 4, iclass 18, count 0 2006.285.12:56:53.48#ibcon#read 4, iclass 18, count 0 2006.285.12:56:53.48#ibcon#about to read 5, iclass 18, count 0 2006.285.12:56:53.48#ibcon#read 5, iclass 18, count 0 2006.285.12:56:53.48#ibcon#about to read 6, iclass 18, count 0 2006.285.12:56:53.48#ibcon#read 6, iclass 18, count 0 2006.285.12:56:53.48#ibcon#end of sib2, iclass 18, count 0 2006.285.12:56:53.48#ibcon#*after write, iclass 18, count 0 2006.285.12:56:53.48#ibcon#*before return 0, iclass 18, count 0 2006.285.12:56:53.48#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:56:53.48#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.12:56:53.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.12:56:53.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.12:56:53.48$vck44/vblo=7,734.99 2006.285.12:56:53.48#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.12:56:53.48#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.12:56:53.48#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:53.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:56:53.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:56:53.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:56:53.48#ibcon#enter wrdev, iclass 20, count 0 2006.285.12:56:53.48#ibcon#first serial, iclass 20, count 0 2006.285.12:56:53.48#ibcon#enter sib2, iclass 20, count 0 2006.285.12:56:53.48#ibcon#flushed, iclass 20, count 0 2006.285.12:56:53.48#ibcon#about to write, iclass 20, count 0 2006.285.12:56:53.48#ibcon#wrote, iclass 20, count 0 2006.285.12:56:53.48#ibcon#about to read 3, iclass 20, count 0 2006.285.12:56:53.50#ibcon#read 3, iclass 20, count 0 2006.285.12:56:53.50#ibcon#about to read 4, iclass 20, count 0 2006.285.12:56:53.50#ibcon#read 4, iclass 20, count 0 2006.285.12:56:53.50#ibcon#about to read 5, iclass 20, count 0 2006.285.12:56:53.50#ibcon#read 5, iclass 20, count 0 2006.285.12:56:53.50#ibcon#about to read 6, iclass 20, count 0 2006.285.12:56:53.50#ibcon#read 6, iclass 20, count 0 2006.285.12:56:53.50#ibcon#end of sib2, iclass 20, count 0 2006.285.12:56:53.50#ibcon#*mode == 0, iclass 20, count 0 2006.285.12:56:53.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.12:56:53.50#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.12:56:53.50#ibcon#*before write, iclass 20, count 0 2006.285.12:56:53.50#ibcon#enter sib2, iclass 20, count 0 2006.285.12:56:53.50#ibcon#flushed, iclass 20, count 0 2006.285.12:56:53.50#ibcon#about to write, iclass 20, count 0 2006.285.12:56:53.50#ibcon#wrote, iclass 20, count 0 2006.285.12:56:53.50#ibcon#about to read 3, iclass 20, count 0 2006.285.12:56:53.54#ibcon#read 3, iclass 20, count 0 2006.285.12:56:53.54#ibcon#about to read 4, iclass 20, count 0 2006.285.12:56:53.54#ibcon#read 4, iclass 20, count 0 2006.285.12:56:53.54#ibcon#about to read 5, iclass 20, count 0 2006.285.12:56:53.54#ibcon#read 5, iclass 20, count 0 2006.285.12:56:53.54#ibcon#about to read 6, iclass 20, count 0 2006.285.12:56:53.54#ibcon#read 6, iclass 20, count 0 2006.285.12:56:53.54#ibcon#end of sib2, iclass 20, count 0 2006.285.12:56:53.54#ibcon#*after write, iclass 20, count 0 2006.285.12:56:53.54#ibcon#*before return 0, iclass 20, count 0 2006.285.12:56:53.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:56:53.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.12:56:53.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.12:56:53.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.12:56:53.54$vck44/vb=7,4 2006.285.12:56:53.54#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.12:56:53.54#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.12:56:53.54#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:53.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:56:53.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:56:53.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:56:53.60#ibcon#enter wrdev, iclass 22, count 2 2006.285.12:56:53.60#ibcon#first serial, iclass 22, count 2 2006.285.12:56:53.60#ibcon#enter sib2, iclass 22, count 2 2006.285.12:56:53.60#ibcon#flushed, iclass 22, count 2 2006.285.12:56:53.60#ibcon#about to write, iclass 22, count 2 2006.285.12:56:53.60#ibcon#wrote, iclass 22, count 2 2006.285.12:56:53.60#ibcon#about to read 3, iclass 22, count 2 2006.285.12:56:53.62#ibcon#read 3, iclass 22, count 2 2006.285.12:56:53.62#ibcon#about to read 4, iclass 22, count 2 2006.285.12:56:53.62#ibcon#read 4, iclass 22, count 2 2006.285.12:56:53.62#ibcon#about to read 5, iclass 22, count 2 2006.285.12:56:53.62#ibcon#read 5, iclass 22, count 2 2006.285.12:56:53.62#ibcon#about to read 6, iclass 22, count 2 2006.285.12:56:53.62#ibcon#read 6, iclass 22, count 2 2006.285.12:56:53.62#ibcon#end of sib2, iclass 22, count 2 2006.285.12:56:53.62#ibcon#*mode == 0, iclass 22, count 2 2006.285.12:56:53.62#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.12:56:53.62#ibcon#[27=AT07-04\r\n] 2006.285.12:56:53.62#ibcon#*before write, iclass 22, count 2 2006.285.12:56:53.62#ibcon#enter sib2, iclass 22, count 2 2006.285.12:56:53.62#ibcon#flushed, iclass 22, count 2 2006.285.12:56:53.62#ibcon#about to write, iclass 22, count 2 2006.285.12:56:53.62#ibcon#wrote, iclass 22, count 2 2006.285.12:56:53.62#ibcon#about to read 3, iclass 22, count 2 2006.285.12:56:53.65#ibcon#read 3, iclass 22, count 2 2006.285.12:56:53.65#ibcon#about to read 4, iclass 22, count 2 2006.285.12:56:53.65#ibcon#read 4, iclass 22, count 2 2006.285.12:56:53.65#ibcon#about to read 5, iclass 22, count 2 2006.285.12:56:53.65#ibcon#read 5, iclass 22, count 2 2006.285.12:56:53.65#ibcon#about to read 6, iclass 22, count 2 2006.285.12:56:53.65#ibcon#read 6, iclass 22, count 2 2006.285.12:56:53.65#ibcon#end of sib2, iclass 22, count 2 2006.285.12:56:53.65#ibcon#*after write, iclass 22, count 2 2006.285.12:56:53.65#ibcon#*before return 0, iclass 22, count 2 2006.285.12:56:53.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:56:53.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.12:56:53.65#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.12:56:53.65#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:53.65#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:56:53.77#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:56:53.77#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:56:53.77#ibcon#enter wrdev, iclass 22, count 0 2006.285.12:56:53.77#ibcon#first serial, iclass 22, count 0 2006.285.12:56:53.77#ibcon#enter sib2, iclass 22, count 0 2006.285.12:56:53.77#ibcon#flushed, iclass 22, count 0 2006.285.12:56:53.77#ibcon#about to write, iclass 22, count 0 2006.285.12:56:53.77#ibcon#wrote, iclass 22, count 0 2006.285.12:56:53.77#ibcon#about to read 3, iclass 22, count 0 2006.285.12:56:53.79#ibcon#read 3, iclass 22, count 0 2006.285.12:56:53.79#ibcon#about to read 4, iclass 22, count 0 2006.285.12:56:53.79#ibcon#read 4, iclass 22, count 0 2006.285.12:56:53.79#ibcon#about to read 5, iclass 22, count 0 2006.285.12:56:53.79#ibcon#read 5, iclass 22, count 0 2006.285.12:56:53.79#ibcon#about to read 6, iclass 22, count 0 2006.285.12:56:53.79#ibcon#read 6, iclass 22, count 0 2006.285.12:56:53.79#ibcon#end of sib2, iclass 22, count 0 2006.285.12:56:53.79#ibcon#*mode == 0, iclass 22, count 0 2006.285.12:56:53.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.12:56:53.79#ibcon#[27=USB\r\n] 2006.285.12:56:53.79#ibcon#*before write, iclass 22, count 0 2006.285.12:56:53.79#ibcon#enter sib2, iclass 22, count 0 2006.285.12:56:53.79#ibcon#flushed, iclass 22, count 0 2006.285.12:56:53.79#ibcon#about to write, iclass 22, count 0 2006.285.12:56:53.79#ibcon#wrote, iclass 22, count 0 2006.285.12:56:53.79#ibcon#about to read 3, iclass 22, count 0 2006.285.12:56:53.82#ibcon#read 3, iclass 22, count 0 2006.285.12:56:53.82#ibcon#about to read 4, iclass 22, count 0 2006.285.12:56:53.82#ibcon#read 4, iclass 22, count 0 2006.285.12:56:53.82#ibcon#about to read 5, iclass 22, count 0 2006.285.12:56:53.82#ibcon#read 5, iclass 22, count 0 2006.285.12:56:53.82#ibcon#about to read 6, iclass 22, count 0 2006.285.12:56:53.82#ibcon#read 6, iclass 22, count 0 2006.285.12:56:53.82#ibcon#end of sib2, iclass 22, count 0 2006.285.12:56:53.82#ibcon#*after write, iclass 22, count 0 2006.285.12:56:53.82#ibcon#*before return 0, iclass 22, count 0 2006.285.12:56:53.82#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:56:53.82#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.12:56:53.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.12:56:53.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.12:56:53.82$vck44/vblo=8,744.99 2006.285.12:56:53.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.12:56:53.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.12:56:53.82#ibcon#ireg 17 cls_cnt 0 2006.285.12:56:53.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:56:53.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:56:53.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:56:53.82#ibcon#enter wrdev, iclass 24, count 0 2006.285.12:56:53.82#ibcon#first serial, iclass 24, count 0 2006.285.12:56:53.82#ibcon#enter sib2, iclass 24, count 0 2006.285.12:56:53.82#ibcon#flushed, iclass 24, count 0 2006.285.12:56:53.82#ibcon#about to write, iclass 24, count 0 2006.285.12:56:53.82#ibcon#wrote, iclass 24, count 0 2006.285.12:56:53.82#ibcon#about to read 3, iclass 24, count 0 2006.285.12:56:53.84#ibcon#read 3, iclass 24, count 0 2006.285.12:56:53.84#ibcon#about to read 4, iclass 24, count 0 2006.285.12:56:53.84#ibcon#read 4, iclass 24, count 0 2006.285.12:56:53.84#ibcon#about to read 5, iclass 24, count 0 2006.285.12:56:53.84#ibcon#read 5, iclass 24, count 0 2006.285.12:56:53.84#ibcon#about to read 6, iclass 24, count 0 2006.285.12:56:53.84#ibcon#read 6, iclass 24, count 0 2006.285.12:56:53.84#ibcon#end of sib2, iclass 24, count 0 2006.285.12:56:53.84#ibcon#*mode == 0, iclass 24, count 0 2006.285.12:56:53.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.12:56:53.84#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.12:56:53.84#ibcon#*before write, iclass 24, count 0 2006.285.12:56:53.84#ibcon#enter sib2, iclass 24, count 0 2006.285.12:56:53.84#ibcon#flushed, iclass 24, count 0 2006.285.12:56:53.84#ibcon#about to write, iclass 24, count 0 2006.285.12:56:53.84#ibcon#wrote, iclass 24, count 0 2006.285.12:56:53.84#ibcon#about to read 3, iclass 24, count 0 2006.285.12:56:53.88#ibcon#read 3, iclass 24, count 0 2006.285.12:56:53.88#ibcon#about to read 4, iclass 24, count 0 2006.285.12:56:53.88#ibcon#read 4, iclass 24, count 0 2006.285.12:56:53.88#ibcon#about to read 5, iclass 24, count 0 2006.285.12:56:53.88#ibcon#read 5, iclass 24, count 0 2006.285.12:56:53.88#ibcon#about to read 6, iclass 24, count 0 2006.285.12:56:53.88#ibcon#read 6, iclass 24, count 0 2006.285.12:56:53.88#ibcon#end of sib2, iclass 24, count 0 2006.285.12:56:53.88#ibcon#*after write, iclass 24, count 0 2006.285.12:56:53.88#ibcon#*before return 0, iclass 24, count 0 2006.285.12:56:53.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:56:53.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.12:56:53.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.12:56:53.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.12:56:53.88$vck44/vb=8,4 2006.285.12:56:53.88#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.12:56:53.88#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.12:56:53.88#ibcon#ireg 11 cls_cnt 2 2006.285.12:56:53.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:56:53.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:56:53.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:56:53.94#ibcon#enter wrdev, iclass 26, count 2 2006.285.12:56:53.94#ibcon#first serial, iclass 26, count 2 2006.285.12:56:53.94#ibcon#enter sib2, iclass 26, count 2 2006.285.12:56:53.94#ibcon#flushed, iclass 26, count 2 2006.285.12:56:53.94#ibcon#about to write, iclass 26, count 2 2006.285.12:56:53.94#ibcon#wrote, iclass 26, count 2 2006.285.12:56:53.94#ibcon#about to read 3, iclass 26, count 2 2006.285.12:56:53.96#ibcon#read 3, iclass 26, count 2 2006.285.12:56:53.96#ibcon#about to read 4, iclass 26, count 2 2006.285.12:56:53.96#ibcon#read 4, iclass 26, count 2 2006.285.12:56:53.96#ibcon#about to read 5, iclass 26, count 2 2006.285.12:56:53.96#ibcon#read 5, iclass 26, count 2 2006.285.12:56:53.96#ibcon#about to read 6, iclass 26, count 2 2006.285.12:56:53.96#ibcon#read 6, iclass 26, count 2 2006.285.12:56:53.96#ibcon#end of sib2, iclass 26, count 2 2006.285.12:56:53.96#ibcon#*mode == 0, iclass 26, count 2 2006.285.12:56:53.96#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.12:56:53.96#ibcon#[27=AT08-04\r\n] 2006.285.12:56:53.96#ibcon#*before write, iclass 26, count 2 2006.285.12:56:53.96#ibcon#enter sib2, iclass 26, count 2 2006.285.12:56:53.96#ibcon#flushed, iclass 26, count 2 2006.285.12:56:53.96#ibcon#about to write, iclass 26, count 2 2006.285.12:56:53.96#ibcon#wrote, iclass 26, count 2 2006.285.12:56:53.96#ibcon#about to read 3, iclass 26, count 2 2006.285.12:56:53.99#ibcon#read 3, iclass 26, count 2 2006.285.12:56:53.99#ibcon#about to read 4, iclass 26, count 2 2006.285.12:56:53.99#ibcon#read 4, iclass 26, count 2 2006.285.12:56:53.99#ibcon#about to read 5, iclass 26, count 2 2006.285.12:56:53.99#ibcon#read 5, iclass 26, count 2 2006.285.12:56:53.99#ibcon#about to read 6, iclass 26, count 2 2006.285.12:56:53.99#ibcon#read 6, iclass 26, count 2 2006.285.12:56:53.99#ibcon#end of sib2, iclass 26, count 2 2006.285.12:56:53.99#ibcon#*after write, iclass 26, count 2 2006.285.12:56:53.99#ibcon#*before return 0, iclass 26, count 2 2006.285.12:56:53.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:56:53.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.12:56:53.99#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.12:56:53.99#ibcon#ireg 7 cls_cnt 0 2006.285.12:56:53.99#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:56:54.11#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:56:54.11#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:56:54.11#ibcon#enter wrdev, iclass 26, count 0 2006.285.12:56:54.11#ibcon#first serial, iclass 26, count 0 2006.285.12:56:54.11#ibcon#enter sib2, iclass 26, count 0 2006.285.12:56:54.11#ibcon#flushed, iclass 26, count 0 2006.285.12:56:54.11#ibcon#about to write, iclass 26, count 0 2006.285.12:56:54.11#ibcon#wrote, iclass 26, count 0 2006.285.12:56:54.11#ibcon#about to read 3, iclass 26, count 0 2006.285.12:56:54.13#ibcon#read 3, iclass 26, count 0 2006.285.12:56:54.13#ibcon#about to read 4, iclass 26, count 0 2006.285.12:56:54.13#ibcon#read 4, iclass 26, count 0 2006.285.12:56:54.13#ibcon#about to read 5, iclass 26, count 0 2006.285.12:56:54.13#ibcon#read 5, iclass 26, count 0 2006.285.12:56:54.13#ibcon#about to read 6, iclass 26, count 0 2006.285.12:56:54.13#ibcon#read 6, iclass 26, count 0 2006.285.12:56:54.13#ibcon#end of sib2, iclass 26, count 0 2006.285.12:56:54.13#ibcon#*mode == 0, iclass 26, count 0 2006.285.12:56:54.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.12:56:54.13#ibcon#[27=USB\r\n] 2006.285.12:56:54.13#ibcon#*before write, iclass 26, count 0 2006.285.12:56:54.13#ibcon#enter sib2, iclass 26, count 0 2006.285.12:56:54.13#ibcon#flushed, iclass 26, count 0 2006.285.12:56:54.13#ibcon#about to write, iclass 26, count 0 2006.285.12:56:54.13#ibcon#wrote, iclass 26, count 0 2006.285.12:56:54.13#ibcon#about to read 3, iclass 26, count 0 2006.285.12:56:54.16#abcon#<5=/04 1.4 3.1 18.98 961015.4\r\n> 2006.285.12:56:54.16#ibcon#read 3, iclass 26, count 0 2006.285.12:56:54.16#ibcon#about to read 4, iclass 26, count 0 2006.285.12:56:54.16#ibcon#read 4, iclass 26, count 0 2006.285.12:56:54.16#ibcon#about to read 5, iclass 26, count 0 2006.285.12:56:54.16#ibcon#read 5, iclass 26, count 0 2006.285.12:56:54.16#ibcon#about to read 6, iclass 26, count 0 2006.285.12:56:54.16#ibcon#read 6, iclass 26, count 0 2006.285.12:56:54.16#ibcon#end of sib2, iclass 26, count 0 2006.285.12:56:54.16#ibcon#*after write, iclass 26, count 0 2006.285.12:56:54.16#ibcon#*before return 0, iclass 26, count 0 2006.285.12:56:54.16#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:56:54.16#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.12:56:54.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.12:56:54.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.12:56:54.16$vck44/vabw=wide 2006.285.12:56:54.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.12:56:54.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.12:56:54.16#ibcon#ireg 8 cls_cnt 0 2006.285.12:56:54.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:56:54.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:56:54.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:56:54.16#ibcon#enter wrdev, iclass 31, count 0 2006.285.12:56:54.16#ibcon#first serial, iclass 31, count 0 2006.285.12:56:54.16#ibcon#enter sib2, iclass 31, count 0 2006.285.12:56:54.16#ibcon#flushed, iclass 31, count 0 2006.285.12:56:54.16#ibcon#about to write, iclass 31, count 0 2006.285.12:56:54.16#ibcon#wrote, iclass 31, count 0 2006.285.12:56:54.16#ibcon#about to read 3, iclass 31, count 0 2006.285.12:56:54.18#abcon#{5=INTERFACE CLEAR} 2006.285.12:56:54.18#ibcon#read 3, iclass 31, count 0 2006.285.12:56:54.18#ibcon#about to read 4, iclass 31, count 0 2006.285.12:56:54.18#ibcon#read 4, iclass 31, count 0 2006.285.12:56:54.18#ibcon#about to read 5, iclass 31, count 0 2006.285.12:56:54.18#ibcon#read 5, iclass 31, count 0 2006.285.12:56:54.18#ibcon#about to read 6, iclass 31, count 0 2006.285.12:56:54.18#ibcon#read 6, iclass 31, count 0 2006.285.12:56:54.18#ibcon#end of sib2, iclass 31, count 0 2006.285.12:56:54.18#ibcon#*mode == 0, iclass 31, count 0 2006.285.12:56:54.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.12:56:54.18#ibcon#[25=BW32\r\n] 2006.285.12:56:54.18#ibcon#*before write, iclass 31, count 0 2006.285.12:56:54.18#ibcon#enter sib2, iclass 31, count 0 2006.285.12:56:54.18#ibcon#flushed, iclass 31, count 0 2006.285.12:56:54.18#ibcon#about to write, iclass 31, count 0 2006.285.12:56:54.18#ibcon#wrote, iclass 31, count 0 2006.285.12:56:54.18#ibcon#about to read 3, iclass 31, count 0 2006.285.12:56:54.21#ibcon#read 3, iclass 31, count 0 2006.285.12:56:54.21#ibcon#about to read 4, iclass 31, count 0 2006.285.12:56:54.21#ibcon#read 4, iclass 31, count 0 2006.285.12:56:54.21#ibcon#about to read 5, iclass 31, count 0 2006.285.12:56:54.21#ibcon#read 5, iclass 31, count 0 2006.285.12:56:54.21#ibcon#about to read 6, iclass 31, count 0 2006.285.12:56:54.21#ibcon#read 6, iclass 31, count 0 2006.285.12:56:54.21#ibcon#end of sib2, iclass 31, count 0 2006.285.12:56:54.21#ibcon#*after write, iclass 31, count 0 2006.285.12:56:54.21#ibcon#*before return 0, iclass 31, count 0 2006.285.12:56:54.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:56:54.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.12:56:54.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.12:56:54.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.12:56:54.21$vck44/vbbw=wide 2006.285.12:56:54.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.12:56:54.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.12:56:54.21#ibcon#ireg 8 cls_cnt 0 2006.285.12:56:54.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:56:54.24#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:56:54.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:56:54.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:56:54.28#ibcon#enter wrdev, iclass 33, count 0 2006.285.12:56:54.28#ibcon#first serial, iclass 33, count 0 2006.285.12:56:54.28#ibcon#enter sib2, iclass 33, count 0 2006.285.12:56:54.28#ibcon#flushed, iclass 33, count 0 2006.285.12:56:54.28#ibcon#about to write, iclass 33, count 0 2006.285.12:56:54.28#ibcon#wrote, iclass 33, count 0 2006.285.12:56:54.28#ibcon#about to read 3, iclass 33, count 0 2006.285.12:56:54.30#ibcon#read 3, iclass 33, count 0 2006.285.12:56:54.31#ibcon#about to read 4, iclass 33, count 0 2006.285.12:56:54.31#ibcon#read 4, iclass 33, count 0 2006.285.12:56:54.31#ibcon#about to read 5, iclass 33, count 0 2006.285.12:56:54.31#ibcon#read 5, iclass 33, count 0 2006.285.12:56:54.31#ibcon#about to read 6, iclass 33, count 0 2006.285.12:56:54.31#ibcon#read 6, iclass 33, count 0 2006.285.12:56:54.31#ibcon#end of sib2, iclass 33, count 0 2006.285.12:56:54.31#ibcon#*mode == 0, iclass 33, count 0 2006.285.12:56:54.31#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.12:56:54.31#ibcon#[27=BW32\r\n] 2006.285.12:56:54.31#ibcon#*before write, iclass 33, count 0 2006.285.12:56:54.31#ibcon#enter sib2, iclass 33, count 0 2006.285.12:56:54.31#ibcon#flushed, iclass 33, count 0 2006.285.12:56:54.31#ibcon#about to write, iclass 33, count 0 2006.285.12:56:54.31#ibcon#wrote, iclass 33, count 0 2006.285.12:56:54.31#ibcon#about to read 3, iclass 33, count 0 2006.285.12:56:54.34#ibcon#read 3, iclass 33, count 0 2006.285.12:56:54.34#ibcon#about to read 4, iclass 33, count 0 2006.285.12:56:54.34#ibcon#read 4, iclass 33, count 0 2006.285.12:56:54.34#ibcon#about to read 5, iclass 33, count 0 2006.285.12:56:54.34#ibcon#read 5, iclass 33, count 0 2006.285.12:56:54.34#ibcon#about to read 6, iclass 33, count 0 2006.285.12:56:54.34#ibcon#read 6, iclass 33, count 0 2006.285.12:56:54.34#ibcon#end of sib2, iclass 33, count 0 2006.285.12:56:54.34#ibcon#*after write, iclass 33, count 0 2006.285.12:56:54.34#ibcon#*before return 0, iclass 33, count 0 2006.285.12:56:54.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:56:54.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.12:56:54.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.12:56:54.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.12:56:54.34$setupk4/ifdk4 2006.285.12:56:54.34$ifdk4/lo= 2006.285.12:56:54.34$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.12:56:54.34$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.12:56:54.34$ifdk4/patch= 2006.285.12:56:54.34$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.12:56:54.34$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.12:56:54.34$setupk4/!*+20s 2006.285.12:57:04.33#abcon#<5=/04 1.4 3.1 18.98 961015.4\r\n> 2006.285.12:57:04.35#abcon#{5=INTERFACE CLEAR} 2006.285.12:57:04.41#abcon#[5=S1D000X0/0*\r\n] 2006.285.12:57:07.99$setupk4/"tpicd 2006.285.12:57:07.99$setupk4/echo=off 2006.285.12:57:07.99$setupk4/xlog=off 2006.285.12:57:07.99:!2006.285.13:02:00 2006.285.12:57:41.14#trakl#Source acquired 2006.285.12:57:43.14#flagr#flagr/antenna,acquired 2006.285.13:02:00.02:preob 2006.285.13:02:01.15/onsource/TRACKING 2006.285.13:02:01.15:!2006.285.13:02:10 2006.285.13:02:10.02:"tape 2006.285.13:02:10.02:"st=record 2006.285.13:02:10.02:data_valid=on 2006.285.13:02:10.02:midob 2006.285.13:02:11.14/onsource/TRACKING 2006.285.13:02:11.14/wx/18.98,1015.5,96 2006.285.13:02:11.27/cable/+6.4975E-03 2006.285.13:02:12.36/va/01,07,usb,yes,34,36 2006.285.13:02:12.36/va/02,06,usb,yes,34,34 2006.285.13:02:12.36/va/03,07,usb,yes,33,35 2006.285.13:02:12.36/va/04,06,usb,yes,34,35 2006.285.13:02:12.36/va/05,03,usb,yes,33,33 2006.285.13:02:12.36/va/06,04,usb,yes,30,29 2006.285.13:02:12.36/va/07,04,usb,yes,30,31 2006.285.13:02:12.36/va/08,03,usb,yes,31,38 2006.285.13:02:12.59/valo/01,524.99,yes,locked 2006.285.13:02:12.59/valo/02,534.99,yes,locked 2006.285.13:02:12.59/valo/03,564.99,yes,locked 2006.285.13:02:12.59/valo/04,624.99,yes,locked 2006.285.13:02:12.59/valo/05,734.99,yes,locked 2006.285.13:02:12.59/valo/06,814.99,yes,locked 2006.285.13:02:12.59/valo/07,864.99,yes,locked 2006.285.13:02:12.59/valo/08,884.99,yes,locked 2006.285.13:02:13.68/vb/01,04,usb,yes,31,28 2006.285.13:02:13.68/vb/02,05,usb,yes,29,29 2006.285.13:02:13.68/vb/03,04,usb,yes,30,33 2006.285.13:02:13.68/vb/04,05,usb,yes,30,29 2006.285.13:02:13.68/vb/05,04,usb,yes,26,29 2006.285.13:02:13.68/vb/06,03,usb,yes,38,34 2006.285.13:02:13.68/vb/07,04,usb,yes,31,31 2006.285.13:02:13.68/vb/08,04,usb,yes,28,31 2006.285.13:02:13.91/vblo/01,629.99,yes,locked 2006.285.13:02:13.91/vblo/02,634.99,yes,locked 2006.285.13:02:13.91/vblo/03,649.99,yes,locked 2006.285.13:02:13.91/vblo/04,679.99,yes,locked 2006.285.13:02:13.91/vblo/05,709.99,yes,locked 2006.285.13:02:13.91/vblo/06,719.99,yes,locked 2006.285.13:02:13.91/vblo/07,734.99,yes,locked 2006.285.13:02:13.91/vblo/08,744.99,yes,locked 2006.285.13:02:14.06/vabw/8 2006.285.13:02:14.21/vbbw/8 2006.285.13:02:14.30/xfe/off,on,12.2 2006.285.13:02:14.67/ifatt/23,28,28,28 2006.285.13:02:15.07/fmout-gps/S +2.71E-07 2006.285.13:02:15.09:!2006.285.13:03:50 2006.285.13:03:50.01:data_valid=off 2006.285.13:03:50.02:"et 2006.285.13:03:50.02:!+3s 2006.285.13:03:53.04:"tape 2006.285.13:03:53.04:postob 2006.285.13:03:53.23/cable/+6.4962E-03 2006.285.13:03:53.24/wx/18.99,1015.5,95 2006.285.13:03:53.29/fmout-gps/S +2.72E-07 2006.285.13:03:53.29:scan_name=285-1308,jd0610,80 2006.285.13:03:53.29:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.285.13:03:55.13#flagr#flagr/antenna,new-source 2006.285.13:03:55.14:checkk5 2006.285.13:03:55.64/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:03:56.04/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:03:56.70/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:03:57.11/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:03:57.74/chk_obsdata//k5ts1/T2851302??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.13:03:58.12/chk_obsdata//k5ts2/T2851302??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.13:03:58.60/chk_obsdata//k5ts3/T2851302??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.13:03:59.05/chk_obsdata//k5ts4/T2851302??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.13:04:00.06/k5log//k5ts1_log_newline 2006.285.13:04:00.88/k5log//k5ts2_log_newline 2006.285.13:04:01.64/k5log//k5ts3_log_newline 2006.285.13:04:02.40/k5log//k5ts4_log_newline 2006.285.13:04:02.43/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:04:02.43:setupk4=1 2006.285.13:04:02.43$setupk4/echo=on 2006.285.13:04:02.43$setupk4/pcalon 2006.285.13:04:02.43$pcalon/"no phase cal control is implemented here 2006.285.13:04:02.43$setupk4/"tpicd=stop 2006.285.13:04:02.43$setupk4/"rec=synch_on 2006.285.13:04:02.43$setupk4/"rec_mode=128 2006.285.13:04:02.43$setupk4/!* 2006.285.13:04:02.43$setupk4/recpk4 2006.285.13:04:02.43$recpk4/recpatch= 2006.285.13:04:02.43$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:04:02.43$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:04:02.43$setupk4/vck44 2006.285.13:04:02.43$vck44/valo=1,524.99 2006.285.13:04:02.43#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.13:04:02.43#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.13:04:02.43#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:02.43#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:04:02.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:04:02.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:04:02.43#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:04:02.43#ibcon#first serial, iclass 27, count 0 2006.285.13:04:02.43#ibcon#enter sib2, iclass 27, count 0 2006.285.13:04:02.43#ibcon#flushed, iclass 27, count 0 2006.285.13:04:02.43#ibcon#about to write, iclass 27, count 0 2006.285.13:04:02.43#ibcon#wrote, iclass 27, count 0 2006.285.13:04:02.43#ibcon#about to read 3, iclass 27, count 0 2006.285.13:04:02.44#ibcon#read 3, iclass 27, count 0 2006.285.13:04:02.44#ibcon#about to read 4, iclass 27, count 0 2006.285.13:04:02.44#ibcon#read 4, iclass 27, count 0 2006.285.13:04:02.44#ibcon#about to read 5, iclass 27, count 0 2006.285.13:04:02.44#ibcon#read 5, iclass 27, count 0 2006.285.13:04:02.44#ibcon#about to read 6, iclass 27, count 0 2006.285.13:04:02.44#ibcon#read 6, iclass 27, count 0 2006.285.13:04:02.44#ibcon#end of sib2, iclass 27, count 0 2006.285.13:04:02.44#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:04:02.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:04:02.44#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:04:02.44#ibcon#*before write, iclass 27, count 0 2006.285.13:04:02.44#ibcon#enter sib2, iclass 27, count 0 2006.285.13:04:02.44#ibcon#flushed, iclass 27, count 0 2006.285.13:04:02.44#ibcon#about to write, iclass 27, count 0 2006.285.13:04:02.44#ibcon#wrote, iclass 27, count 0 2006.285.13:04:02.44#ibcon#about to read 3, iclass 27, count 0 2006.285.13:04:02.49#ibcon#read 3, iclass 27, count 0 2006.285.13:04:02.49#ibcon#about to read 4, iclass 27, count 0 2006.285.13:04:02.49#ibcon#read 4, iclass 27, count 0 2006.285.13:04:02.49#ibcon#about to read 5, iclass 27, count 0 2006.285.13:04:02.49#ibcon#read 5, iclass 27, count 0 2006.285.13:04:02.49#ibcon#about to read 6, iclass 27, count 0 2006.285.13:04:02.49#ibcon#read 6, iclass 27, count 0 2006.285.13:04:02.49#ibcon#end of sib2, iclass 27, count 0 2006.285.13:04:02.49#ibcon#*after write, iclass 27, count 0 2006.285.13:04:02.49#ibcon#*before return 0, iclass 27, count 0 2006.285.13:04:02.49#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:04:02.49#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:04:02.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:04:02.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:04:02.49$vck44/va=1,7 2006.285.13:04:02.49#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.13:04:02.49#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.13:04:02.49#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:02.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:04:02.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:04:02.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:04:02.49#ibcon#enter wrdev, iclass 29, count 2 2006.285.13:04:02.49#ibcon#first serial, iclass 29, count 2 2006.285.13:04:02.49#ibcon#enter sib2, iclass 29, count 2 2006.285.13:04:02.49#ibcon#flushed, iclass 29, count 2 2006.285.13:04:02.49#ibcon#about to write, iclass 29, count 2 2006.285.13:04:02.49#ibcon#wrote, iclass 29, count 2 2006.285.13:04:02.49#ibcon#about to read 3, iclass 29, count 2 2006.285.13:04:02.51#ibcon#read 3, iclass 29, count 2 2006.285.13:04:02.51#ibcon#about to read 4, iclass 29, count 2 2006.285.13:04:02.51#ibcon#read 4, iclass 29, count 2 2006.285.13:04:02.51#ibcon#about to read 5, iclass 29, count 2 2006.285.13:04:02.51#ibcon#read 5, iclass 29, count 2 2006.285.13:04:02.51#ibcon#about to read 6, iclass 29, count 2 2006.285.13:04:02.51#ibcon#read 6, iclass 29, count 2 2006.285.13:04:02.51#ibcon#end of sib2, iclass 29, count 2 2006.285.13:04:02.51#ibcon#*mode == 0, iclass 29, count 2 2006.285.13:04:02.51#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.13:04:02.51#ibcon#[25=AT01-07\r\n] 2006.285.13:04:02.51#ibcon#*before write, iclass 29, count 2 2006.285.13:04:02.51#ibcon#enter sib2, iclass 29, count 2 2006.285.13:04:02.51#ibcon#flushed, iclass 29, count 2 2006.285.13:04:02.51#ibcon#about to write, iclass 29, count 2 2006.285.13:04:02.51#ibcon#wrote, iclass 29, count 2 2006.285.13:04:02.51#ibcon#about to read 3, iclass 29, count 2 2006.285.13:04:02.54#ibcon#read 3, iclass 29, count 2 2006.285.13:04:02.54#ibcon#about to read 4, iclass 29, count 2 2006.285.13:04:02.54#ibcon#read 4, iclass 29, count 2 2006.285.13:04:02.54#ibcon#about to read 5, iclass 29, count 2 2006.285.13:04:02.54#ibcon#read 5, iclass 29, count 2 2006.285.13:04:02.54#ibcon#about to read 6, iclass 29, count 2 2006.285.13:04:02.54#ibcon#read 6, iclass 29, count 2 2006.285.13:04:02.54#ibcon#end of sib2, iclass 29, count 2 2006.285.13:04:02.54#ibcon#*after write, iclass 29, count 2 2006.285.13:04:02.54#ibcon#*before return 0, iclass 29, count 2 2006.285.13:04:02.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:04:02.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:04:02.54#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.13:04:02.54#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:02.54#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:04:02.66#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:04:02.66#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:04:02.66#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:04:02.66#ibcon#first serial, iclass 29, count 0 2006.285.13:04:02.66#ibcon#enter sib2, iclass 29, count 0 2006.285.13:04:02.66#ibcon#flushed, iclass 29, count 0 2006.285.13:04:02.66#ibcon#about to write, iclass 29, count 0 2006.285.13:04:02.66#ibcon#wrote, iclass 29, count 0 2006.285.13:04:02.66#ibcon#about to read 3, iclass 29, count 0 2006.285.13:04:02.68#ibcon#read 3, iclass 29, count 0 2006.285.13:04:02.68#ibcon#about to read 4, iclass 29, count 0 2006.285.13:04:02.68#ibcon#read 4, iclass 29, count 0 2006.285.13:04:02.68#ibcon#about to read 5, iclass 29, count 0 2006.285.13:04:02.68#ibcon#read 5, iclass 29, count 0 2006.285.13:04:02.68#ibcon#about to read 6, iclass 29, count 0 2006.285.13:04:02.68#ibcon#read 6, iclass 29, count 0 2006.285.13:04:02.68#ibcon#end of sib2, iclass 29, count 0 2006.285.13:04:02.68#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:04:02.68#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:04:02.68#ibcon#[25=USB\r\n] 2006.285.13:04:02.68#ibcon#*before write, iclass 29, count 0 2006.285.13:04:02.68#ibcon#enter sib2, iclass 29, count 0 2006.285.13:04:02.68#ibcon#flushed, iclass 29, count 0 2006.285.13:04:02.68#ibcon#about to write, iclass 29, count 0 2006.285.13:04:02.68#ibcon#wrote, iclass 29, count 0 2006.285.13:04:02.68#ibcon#about to read 3, iclass 29, count 0 2006.285.13:04:02.71#ibcon#read 3, iclass 29, count 0 2006.285.13:04:02.71#ibcon#about to read 4, iclass 29, count 0 2006.285.13:04:02.71#ibcon#read 4, iclass 29, count 0 2006.285.13:04:02.71#ibcon#about to read 5, iclass 29, count 0 2006.285.13:04:02.71#ibcon#read 5, iclass 29, count 0 2006.285.13:04:02.71#ibcon#about to read 6, iclass 29, count 0 2006.285.13:04:02.71#ibcon#read 6, iclass 29, count 0 2006.285.13:04:02.71#ibcon#end of sib2, iclass 29, count 0 2006.285.13:04:02.71#ibcon#*after write, iclass 29, count 0 2006.285.13:04:02.71#ibcon#*before return 0, iclass 29, count 0 2006.285.13:04:02.71#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:04:02.71#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:04:02.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:04:02.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:04:02.71$vck44/valo=2,534.99 2006.285.13:04:02.71#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.13:04:02.71#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.13:04:02.71#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:02.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:04:02.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:04:02.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:04:02.71#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:04:02.71#ibcon#first serial, iclass 31, count 0 2006.285.13:04:02.71#ibcon#enter sib2, iclass 31, count 0 2006.285.13:04:02.71#ibcon#flushed, iclass 31, count 0 2006.285.13:04:02.71#ibcon#about to write, iclass 31, count 0 2006.285.13:04:02.71#ibcon#wrote, iclass 31, count 0 2006.285.13:04:02.71#ibcon#about to read 3, iclass 31, count 0 2006.285.13:04:02.73#ibcon#read 3, iclass 31, count 0 2006.285.13:04:02.73#ibcon#about to read 4, iclass 31, count 0 2006.285.13:04:02.73#ibcon#read 4, iclass 31, count 0 2006.285.13:04:02.73#ibcon#about to read 5, iclass 31, count 0 2006.285.13:04:02.73#ibcon#read 5, iclass 31, count 0 2006.285.13:04:02.73#ibcon#about to read 6, iclass 31, count 0 2006.285.13:04:02.73#ibcon#read 6, iclass 31, count 0 2006.285.13:04:02.73#ibcon#end of sib2, iclass 31, count 0 2006.285.13:04:02.73#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:04:02.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:04:02.73#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:04:02.73#ibcon#*before write, iclass 31, count 0 2006.285.13:04:02.73#ibcon#enter sib2, iclass 31, count 0 2006.285.13:04:02.73#ibcon#flushed, iclass 31, count 0 2006.285.13:04:02.73#ibcon#about to write, iclass 31, count 0 2006.285.13:04:02.73#ibcon#wrote, iclass 31, count 0 2006.285.13:04:02.73#ibcon#about to read 3, iclass 31, count 0 2006.285.13:04:02.77#ibcon#read 3, iclass 31, count 0 2006.285.13:04:02.77#ibcon#about to read 4, iclass 31, count 0 2006.285.13:04:02.77#ibcon#read 4, iclass 31, count 0 2006.285.13:04:02.77#ibcon#about to read 5, iclass 31, count 0 2006.285.13:04:02.77#ibcon#read 5, iclass 31, count 0 2006.285.13:04:02.77#ibcon#about to read 6, iclass 31, count 0 2006.285.13:04:02.77#ibcon#read 6, iclass 31, count 0 2006.285.13:04:02.77#ibcon#end of sib2, iclass 31, count 0 2006.285.13:04:02.77#ibcon#*after write, iclass 31, count 0 2006.285.13:04:02.77#ibcon#*before return 0, iclass 31, count 0 2006.285.13:04:02.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:04:02.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:04:02.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:04:02.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:04:02.77$vck44/va=2,6 2006.285.13:04:02.77#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.13:04:02.77#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.13:04:02.77#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:02.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:04:02.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:04:02.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:04:02.83#ibcon#enter wrdev, iclass 33, count 2 2006.285.13:04:02.83#ibcon#first serial, iclass 33, count 2 2006.285.13:04:02.83#ibcon#enter sib2, iclass 33, count 2 2006.285.13:04:02.83#ibcon#flushed, iclass 33, count 2 2006.285.13:04:02.83#ibcon#about to write, iclass 33, count 2 2006.285.13:04:02.83#ibcon#wrote, iclass 33, count 2 2006.285.13:04:02.83#ibcon#about to read 3, iclass 33, count 2 2006.285.13:04:02.85#ibcon#read 3, iclass 33, count 2 2006.285.13:04:02.85#ibcon#about to read 4, iclass 33, count 2 2006.285.13:04:02.85#ibcon#read 4, iclass 33, count 2 2006.285.13:04:02.85#ibcon#about to read 5, iclass 33, count 2 2006.285.13:04:02.85#ibcon#read 5, iclass 33, count 2 2006.285.13:04:02.85#ibcon#about to read 6, iclass 33, count 2 2006.285.13:04:02.85#ibcon#read 6, iclass 33, count 2 2006.285.13:04:02.85#ibcon#end of sib2, iclass 33, count 2 2006.285.13:04:02.85#ibcon#*mode == 0, iclass 33, count 2 2006.285.13:04:02.85#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.13:04:02.85#ibcon#[25=AT02-06\r\n] 2006.285.13:04:02.85#ibcon#*before write, iclass 33, count 2 2006.285.13:04:02.85#ibcon#enter sib2, iclass 33, count 2 2006.285.13:04:02.85#ibcon#flushed, iclass 33, count 2 2006.285.13:04:02.85#ibcon#about to write, iclass 33, count 2 2006.285.13:04:02.85#ibcon#wrote, iclass 33, count 2 2006.285.13:04:02.85#ibcon#about to read 3, iclass 33, count 2 2006.285.13:04:02.88#ibcon#read 3, iclass 33, count 2 2006.285.13:04:02.88#ibcon#about to read 4, iclass 33, count 2 2006.285.13:04:02.88#ibcon#read 4, iclass 33, count 2 2006.285.13:04:02.88#ibcon#about to read 5, iclass 33, count 2 2006.285.13:04:02.88#ibcon#read 5, iclass 33, count 2 2006.285.13:04:02.88#ibcon#about to read 6, iclass 33, count 2 2006.285.13:04:02.88#ibcon#read 6, iclass 33, count 2 2006.285.13:04:02.88#ibcon#end of sib2, iclass 33, count 2 2006.285.13:04:02.88#ibcon#*after write, iclass 33, count 2 2006.285.13:04:02.88#ibcon#*before return 0, iclass 33, count 2 2006.285.13:04:02.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:04:02.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:04:02.88#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.13:04:02.88#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:02.88#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:04:03.00#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:04:03.00#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:04:03.00#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:04:03.00#ibcon#first serial, iclass 33, count 0 2006.285.13:04:03.00#ibcon#enter sib2, iclass 33, count 0 2006.285.13:04:03.00#ibcon#flushed, iclass 33, count 0 2006.285.13:04:03.00#ibcon#about to write, iclass 33, count 0 2006.285.13:04:03.00#ibcon#wrote, iclass 33, count 0 2006.285.13:04:03.00#ibcon#about to read 3, iclass 33, count 0 2006.285.13:04:03.02#ibcon#read 3, iclass 33, count 0 2006.285.13:04:03.02#ibcon#about to read 4, iclass 33, count 0 2006.285.13:04:03.02#ibcon#read 4, iclass 33, count 0 2006.285.13:04:03.02#ibcon#about to read 5, iclass 33, count 0 2006.285.13:04:03.02#ibcon#read 5, iclass 33, count 0 2006.285.13:04:03.02#ibcon#about to read 6, iclass 33, count 0 2006.285.13:04:03.02#ibcon#read 6, iclass 33, count 0 2006.285.13:04:03.02#ibcon#end of sib2, iclass 33, count 0 2006.285.13:04:03.02#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:04:03.02#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:04:03.02#ibcon#[25=USB\r\n] 2006.285.13:04:03.02#ibcon#*before write, iclass 33, count 0 2006.285.13:04:03.02#ibcon#enter sib2, iclass 33, count 0 2006.285.13:04:03.02#ibcon#flushed, iclass 33, count 0 2006.285.13:04:03.02#ibcon#about to write, iclass 33, count 0 2006.285.13:04:03.02#ibcon#wrote, iclass 33, count 0 2006.285.13:04:03.02#ibcon#about to read 3, iclass 33, count 0 2006.285.13:04:03.05#ibcon#read 3, iclass 33, count 0 2006.285.13:04:03.05#ibcon#about to read 4, iclass 33, count 0 2006.285.13:04:03.05#ibcon#read 4, iclass 33, count 0 2006.285.13:04:03.05#ibcon#about to read 5, iclass 33, count 0 2006.285.13:04:03.05#ibcon#read 5, iclass 33, count 0 2006.285.13:04:03.05#ibcon#about to read 6, iclass 33, count 0 2006.285.13:04:03.05#ibcon#read 6, iclass 33, count 0 2006.285.13:04:03.05#ibcon#end of sib2, iclass 33, count 0 2006.285.13:04:03.05#ibcon#*after write, iclass 33, count 0 2006.285.13:04:03.05#ibcon#*before return 0, iclass 33, count 0 2006.285.13:04:03.05#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:04:03.05#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:04:03.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:04:03.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:04:03.05$vck44/valo=3,564.99 2006.285.13:04:03.05#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.13:04:03.05#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.13:04:03.05#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:03.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:04:03.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:04:03.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:04:03.05#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:04:03.05#ibcon#first serial, iclass 35, count 0 2006.285.13:04:03.05#ibcon#enter sib2, iclass 35, count 0 2006.285.13:04:03.05#ibcon#flushed, iclass 35, count 0 2006.285.13:04:03.05#ibcon#about to write, iclass 35, count 0 2006.285.13:04:03.05#ibcon#wrote, iclass 35, count 0 2006.285.13:04:03.05#ibcon#about to read 3, iclass 35, count 0 2006.285.13:04:03.07#ibcon#read 3, iclass 35, count 0 2006.285.13:04:03.07#ibcon#about to read 4, iclass 35, count 0 2006.285.13:04:03.07#ibcon#read 4, iclass 35, count 0 2006.285.13:04:03.07#ibcon#about to read 5, iclass 35, count 0 2006.285.13:04:03.07#ibcon#read 5, iclass 35, count 0 2006.285.13:04:03.07#ibcon#about to read 6, iclass 35, count 0 2006.285.13:04:03.07#ibcon#read 6, iclass 35, count 0 2006.285.13:04:03.07#ibcon#end of sib2, iclass 35, count 0 2006.285.13:04:03.07#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:04:03.07#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:04:03.07#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:04:03.07#ibcon#*before write, iclass 35, count 0 2006.285.13:04:03.07#ibcon#enter sib2, iclass 35, count 0 2006.285.13:04:03.07#ibcon#flushed, iclass 35, count 0 2006.285.13:04:03.07#ibcon#about to write, iclass 35, count 0 2006.285.13:04:03.07#ibcon#wrote, iclass 35, count 0 2006.285.13:04:03.07#ibcon#about to read 3, iclass 35, count 0 2006.285.13:04:03.11#ibcon#read 3, iclass 35, count 0 2006.285.13:04:03.11#ibcon#about to read 4, iclass 35, count 0 2006.285.13:04:03.11#ibcon#read 4, iclass 35, count 0 2006.285.13:04:03.11#ibcon#about to read 5, iclass 35, count 0 2006.285.13:04:03.11#ibcon#read 5, iclass 35, count 0 2006.285.13:04:03.11#ibcon#about to read 6, iclass 35, count 0 2006.285.13:04:03.11#ibcon#read 6, iclass 35, count 0 2006.285.13:04:03.11#ibcon#end of sib2, iclass 35, count 0 2006.285.13:04:03.11#ibcon#*after write, iclass 35, count 0 2006.285.13:04:03.11#ibcon#*before return 0, iclass 35, count 0 2006.285.13:04:03.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:04:03.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:04:03.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:04:03.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:04:03.11$vck44/va=3,7 2006.285.13:04:03.11#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.13:04:03.11#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.13:04:03.11#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:03.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:04:03.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:04:03.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:04:03.17#ibcon#enter wrdev, iclass 37, count 2 2006.285.13:04:03.17#ibcon#first serial, iclass 37, count 2 2006.285.13:04:03.17#ibcon#enter sib2, iclass 37, count 2 2006.285.13:04:03.17#ibcon#flushed, iclass 37, count 2 2006.285.13:04:03.17#ibcon#about to write, iclass 37, count 2 2006.285.13:04:03.17#ibcon#wrote, iclass 37, count 2 2006.285.13:04:03.17#ibcon#about to read 3, iclass 37, count 2 2006.285.13:04:03.19#ibcon#read 3, iclass 37, count 2 2006.285.13:04:03.19#ibcon#about to read 4, iclass 37, count 2 2006.285.13:04:03.19#ibcon#read 4, iclass 37, count 2 2006.285.13:04:03.19#ibcon#about to read 5, iclass 37, count 2 2006.285.13:04:03.19#ibcon#read 5, iclass 37, count 2 2006.285.13:04:03.19#ibcon#about to read 6, iclass 37, count 2 2006.285.13:04:03.19#ibcon#read 6, iclass 37, count 2 2006.285.13:04:03.19#ibcon#end of sib2, iclass 37, count 2 2006.285.13:04:03.19#ibcon#*mode == 0, iclass 37, count 2 2006.285.13:04:03.19#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.13:04:03.19#ibcon#[25=AT03-07\r\n] 2006.285.13:04:03.19#ibcon#*before write, iclass 37, count 2 2006.285.13:04:03.19#ibcon#enter sib2, iclass 37, count 2 2006.285.13:04:03.19#ibcon#flushed, iclass 37, count 2 2006.285.13:04:03.19#ibcon#about to write, iclass 37, count 2 2006.285.13:04:03.19#ibcon#wrote, iclass 37, count 2 2006.285.13:04:03.19#ibcon#about to read 3, iclass 37, count 2 2006.285.13:04:03.22#ibcon#read 3, iclass 37, count 2 2006.285.13:04:03.22#ibcon#about to read 4, iclass 37, count 2 2006.285.13:04:03.22#ibcon#read 4, iclass 37, count 2 2006.285.13:04:03.22#ibcon#about to read 5, iclass 37, count 2 2006.285.13:04:03.22#ibcon#read 5, iclass 37, count 2 2006.285.13:04:03.22#ibcon#about to read 6, iclass 37, count 2 2006.285.13:04:03.22#ibcon#read 6, iclass 37, count 2 2006.285.13:04:03.22#ibcon#end of sib2, iclass 37, count 2 2006.285.13:04:03.22#ibcon#*after write, iclass 37, count 2 2006.285.13:04:03.22#ibcon#*before return 0, iclass 37, count 2 2006.285.13:04:03.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:04:03.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:04:03.22#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.13:04:03.22#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:03.22#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:04:03.34#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:04:03.34#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:04:03.34#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:04:03.34#ibcon#first serial, iclass 37, count 0 2006.285.13:04:03.34#ibcon#enter sib2, iclass 37, count 0 2006.285.13:04:03.34#ibcon#flushed, iclass 37, count 0 2006.285.13:04:03.34#ibcon#about to write, iclass 37, count 0 2006.285.13:04:03.34#ibcon#wrote, iclass 37, count 0 2006.285.13:04:03.34#ibcon#about to read 3, iclass 37, count 0 2006.285.13:04:03.36#ibcon#read 3, iclass 37, count 0 2006.285.13:04:03.36#ibcon#about to read 4, iclass 37, count 0 2006.285.13:04:03.36#ibcon#read 4, iclass 37, count 0 2006.285.13:04:03.36#ibcon#about to read 5, iclass 37, count 0 2006.285.13:04:03.36#ibcon#read 5, iclass 37, count 0 2006.285.13:04:03.36#ibcon#about to read 6, iclass 37, count 0 2006.285.13:04:03.36#ibcon#read 6, iclass 37, count 0 2006.285.13:04:03.36#ibcon#end of sib2, iclass 37, count 0 2006.285.13:04:03.36#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:04:03.36#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:04:03.36#ibcon#[25=USB\r\n] 2006.285.13:04:03.36#ibcon#*before write, iclass 37, count 0 2006.285.13:04:03.36#ibcon#enter sib2, iclass 37, count 0 2006.285.13:04:03.36#ibcon#flushed, iclass 37, count 0 2006.285.13:04:03.36#ibcon#about to write, iclass 37, count 0 2006.285.13:04:03.36#ibcon#wrote, iclass 37, count 0 2006.285.13:04:03.36#ibcon#about to read 3, iclass 37, count 0 2006.285.13:04:03.39#ibcon#read 3, iclass 37, count 0 2006.285.13:04:03.39#ibcon#about to read 4, iclass 37, count 0 2006.285.13:04:03.39#ibcon#read 4, iclass 37, count 0 2006.285.13:04:03.39#ibcon#about to read 5, iclass 37, count 0 2006.285.13:04:03.39#ibcon#read 5, iclass 37, count 0 2006.285.13:04:03.39#ibcon#about to read 6, iclass 37, count 0 2006.285.13:04:03.39#ibcon#read 6, iclass 37, count 0 2006.285.13:04:03.39#ibcon#end of sib2, iclass 37, count 0 2006.285.13:04:03.39#ibcon#*after write, iclass 37, count 0 2006.285.13:04:03.39#ibcon#*before return 0, iclass 37, count 0 2006.285.13:04:03.39#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:04:03.39#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:04:03.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:04:03.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:04:03.39$vck44/valo=4,624.99 2006.285.13:04:03.39#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.13:04:03.39#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.13:04:03.39#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:03.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:04:03.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:04:03.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:04:03.39#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:04:03.39#ibcon#first serial, iclass 39, count 0 2006.285.13:04:03.39#ibcon#enter sib2, iclass 39, count 0 2006.285.13:04:03.39#ibcon#flushed, iclass 39, count 0 2006.285.13:04:03.39#ibcon#about to write, iclass 39, count 0 2006.285.13:04:03.39#ibcon#wrote, iclass 39, count 0 2006.285.13:04:03.39#ibcon#about to read 3, iclass 39, count 0 2006.285.13:04:03.41#ibcon#read 3, iclass 39, count 0 2006.285.13:04:03.41#ibcon#about to read 4, iclass 39, count 0 2006.285.13:04:03.41#ibcon#read 4, iclass 39, count 0 2006.285.13:04:03.41#ibcon#about to read 5, iclass 39, count 0 2006.285.13:04:03.41#ibcon#read 5, iclass 39, count 0 2006.285.13:04:03.41#ibcon#about to read 6, iclass 39, count 0 2006.285.13:04:03.41#ibcon#read 6, iclass 39, count 0 2006.285.13:04:03.41#ibcon#end of sib2, iclass 39, count 0 2006.285.13:04:03.41#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:04:03.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:04:03.41#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:04:03.41#ibcon#*before write, iclass 39, count 0 2006.285.13:04:03.41#ibcon#enter sib2, iclass 39, count 0 2006.285.13:04:03.41#ibcon#flushed, iclass 39, count 0 2006.285.13:04:03.41#ibcon#about to write, iclass 39, count 0 2006.285.13:04:03.41#ibcon#wrote, iclass 39, count 0 2006.285.13:04:03.41#ibcon#about to read 3, iclass 39, count 0 2006.285.13:04:03.45#ibcon#read 3, iclass 39, count 0 2006.285.13:04:03.45#ibcon#about to read 4, iclass 39, count 0 2006.285.13:04:03.45#ibcon#read 4, iclass 39, count 0 2006.285.13:04:03.45#ibcon#about to read 5, iclass 39, count 0 2006.285.13:04:03.45#ibcon#read 5, iclass 39, count 0 2006.285.13:04:03.45#ibcon#about to read 6, iclass 39, count 0 2006.285.13:04:03.45#ibcon#read 6, iclass 39, count 0 2006.285.13:04:03.45#ibcon#end of sib2, iclass 39, count 0 2006.285.13:04:03.45#ibcon#*after write, iclass 39, count 0 2006.285.13:04:03.45#ibcon#*before return 0, iclass 39, count 0 2006.285.13:04:03.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:04:03.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:04:03.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:04:03.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:04:03.45$vck44/va=4,6 2006.285.13:04:03.45#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.13:04:03.45#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.13:04:03.45#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:03.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:04:03.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:04:03.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:04:03.51#ibcon#enter wrdev, iclass 3, count 2 2006.285.13:04:03.51#ibcon#first serial, iclass 3, count 2 2006.285.13:04:03.51#ibcon#enter sib2, iclass 3, count 2 2006.285.13:04:03.51#ibcon#flushed, iclass 3, count 2 2006.285.13:04:03.51#ibcon#about to write, iclass 3, count 2 2006.285.13:04:03.51#ibcon#wrote, iclass 3, count 2 2006.285.13:04:03.51#ibcon#about to read 3, iclass 3, count 2 2006.285.13:04:03.53#ibcon#read 3, iclass 3, count 2 2006.285.13:04:03.53#ibcon#about to read 4, iclass 3, count 2 2006.285.13:04:03.53#ibcon#read 4, iclass 3, count 2 2006.285.13:04:03.53#ibcon#about to read 5, iclass 3, count 2 2006.285.13:04:03.53#ibcon#read 5, iclass 3, count 2 2006.285.13:04:03.53#ibcon#about to read 6, iclass 3, count 2 2006.285.13:04:03.53#ibcon#read 6, iclass 3, count 2 2006.285.13:04:03.53#ibcon#end of sib2, iclass 3, count 2 2006.285.13:04:03.53#ibcon#*mode == 0, iclass 3, count 2 2006.285.13:04:03.53#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.13:04:03.53#ibcon#[25=AT04-06\r\n] 2006.285.13:04:03.53#ibcon#*before write, iclass 3, count 2 2006.285.13:04:03.53#ibcon#enter sib2, iclass 3, count 2 2006.285.13:04:03.53#ibcon#flushed, iclass 3, count 2 2006.285.13:04:03.53#ibcon#about to write, iclass 3, count 2 2006.285.13:04:03.53#ibcon#wrote, iclass 3, count 2 2006.285.13:04:03.53#ibcon#about to read 3, iclass 3, count 2 2006.285.13:04:03.56#ibcon#read 3, iclass 3, count 2 2006.285.13:04:03.56#ibcon#about to read 4, iclass 3, count 2 2006.285.13:04:03.56#ibcon#read 4, iclass 3, count 2 2006.285.13:04:03.56#ibcon#about to read 5, iclass 3, count 2 2006.285.13:04:03.56#ibcon#read 5, iclass 3, count 2 2006.285.13:04:03.56#ibcon#about to read 6, iclass 3, count 2 2006.285.13:04:03.56#ibcon#read 6, iclass 3, count 2 2006.285.13:04:03.56#ibcon#end of sib2, iclass 3, count 2 2006.285.13:04:03.56#ibcon#*after write, iclass 3, count 2 2006.285.13:04:03.56#ibcon#*before return 0, iclass 3, count 2 2006.285.13:04:03.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:04:03.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:04:03.56#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.13:04:03.56#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:03.56#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:04:03.68#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:04:04.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:04:04.10#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:04:04.10#ibcon#first serial, iclass 3, count 0 2006.285.13:04:04.10#ibcon#enter sib2, iclass 3, count 0 2006.285.13:04:04.10#ibcon#flushed, iclass 3, count 0 2006.285.13:04:04.10#ibcon#about to write, iclass 3, count 0 2006.285.13:04:04.10#ibcon#wrote, iclass 3, count 0 2006.285.13:04:04.10#ibcon#about to read 3, iclass 3, count 0 2006.285.13:04:04.11#ibcon#read 3, iclass 3, count 0 2006.285.13:04:04.11#ibcon#about to read 4, iclass 3, count 0 2006.285.13:04:04.11#ibcon#read 4, iclass 3, count 0 2006.285.13:04:04.11#ibcon#about to read 5, iclass 3, count 0 2006.285.13:04:04.11#ibcon#read 5, iclass 3, count 0 2006.285.13:04:04.11#ibcon#about to read 6, iclass 3, count 0 2006.285.13:04:04.11#ibcon#read 6, iclass 3, count 0 2006.285.13:04:04.11#ibcon#end of sib2, iclass 3, count 0 2006.285.13:04:04.11#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:04:04.11#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:04:04.11#ibcon#[25=USB\r\n] 2006.285.13:04:04.11#ibcon#*before write, iclass 3, count 0 2006.285.13:04:04.11#ibcon#enter sib2, iclass 3, count 0 2006.285.13:04:04.11#ibcon#flushed, iclass 3, count 0 2006.285.13:04:04.11#ibcon#about to write, iclass 3, count 0 2006.285.13:04:04.11#ibcon#wrote, iclass 3, count 0 2006.285.13:04:04.11#ibcon#about to read 3, iclass 3, count 0 2006.285.13:04:04.14#ibcon#read 3, iclass 3, count 0 2006.285.13:04:04.14#ibcon#about to read 4, iclass 3, count 0 2006.285.13:04:04.14#ibcon#read 4, iclass 3, count 0 2006.285.13:04:04.14#ibcon#about to read 5, iclass 3, count 0 2006.285.13:04:04.14#ibcon#read 5, iclass 3, count 0 2006.285.13:04:04.14#ibcon#about to read 6, iclass 3, count 0 2006.285.13:04:04.14#ibcon#read 6, iclass 3, count 0 2006.285.13:04:04.14#ibcon#end of sib2, iclass 3, count 0 2006.285.13:04:04.14#ibcon#*after write, iclass 3, count 0 2006.285.13:04:04.14#ibcon#*before return 0, iclass 3, count 0 2006.285.13:04:04.14#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:04:04.14#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:04:04.14#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:04:04.14#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:04:04.14$vck44/valo=5,734.99 2006.285.13:04:04.14#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.13:04:04.14#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.13:04:04.14#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:04.14#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:04:04.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:04:04.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:04:04.14#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:04:04.14#ibcon#first serial, iclass 5, count 0 2006.285.13:04:04.14#ibcon#enter sib2, iclass 5, count 0 2006.285.13:04:04.14#ibcon#flushed, iclass 5, count 0 2006.285.13:04:04.14#ibcon#about to write, iclass 5, count 0 2006.285.13:04:04.14#ibcon#wrote, iclass 5, count 0 2006.285.13:04:04.14#ibcon#about to read 3, iclass 5, count 0 2006.285.13:04:04.16#ibcon#read 3, iclass 5, count 0 2006.285.13:04:04.16#ibcon#about to read 4, iclass 5, count 0 2006.285.13:04:04.16#ibcon#read 4, iclass 5, count 0 2006.285.13:04:04.16#ibcon#about to read 5, iclass 5, count 0 2006.285.13:04:04.16#ibcon#read 5, iclass 5, count 0 2006.285.13:04:04.16#ibcon#about to read 6, iclass 5, count 0 2006.285.13:04:04.16#ibcon#read 6, iclass 5, count 0 2006.285.13:04:04.16#ibcon#end of sib2, iclass 5, count 0 2006.285.13:04:04.16#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:04:04.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:04:04.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:04:04.16#ibcon#*before write, iclass 5, count 0 2006.285.13:04:04.16#ibcon#enter sib2, iclass 5, count 0 2006.285.13:04:04.16#ibcon#flushed, iclass 5, count 0 2006.285.13:04:04.16#ibcon#about to write, iclass 5, count 0 2006.285.13:04:04.16#ibcon#wrote, iclass 5, count 0 2006.285.13:04:04.16#ibcon#about to read 3, iclass 5, count 0 2006.285.13:04:04.20#ibcon#read 3, iclass 5, count 0 2006.285.13:04:04.20#ibcon#about to read 4, iclass 5, count 0 2006.285.13:04:04.20#ibcon#read 4, iclass 5, count 0 2006.285.13:04:04.20#ibcon#about to read 5, iclass 5, count 0 2006.285.13:04:04.20#ibcon#read 5, iclass 5, count 0 2006.285.13:04:04.20#ibcon#about to read 6, iclass 5, count 0 2006.285.13:04:04.20#ibcon#read 6, iclass 5, count 0 2006.285.13:04:04.20#ibcon#end of sib2, iclass 5, count 0 2006.285.13:04:04.20#ibcon#*after write, iclass 5, count 0 2006.285.13:04:04.20#ibcon#*before return 0, iclass 5, count 0 2006.285.13:04:04.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:04:04.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:04:04.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:04:04.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:04:04.20$vck44/va=5,3 2006.285.13:04:04.20#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.13:04:04.20#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.13:04:04.20#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:04.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:04:04.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:04:04.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:04:04.26#ibcon#enter wrdev, iclass 7, count 2 2006.285.13:04:04.26#ibcon#first serial, iclass 7, count 2 2006.285.13:04:04.26#ibcon#enter sib2, iclass 7, count 2 2006.285.13:04:04.26#ibcon#flushed, iclass 7, count 2 2006.285.13:04:04.26#ibcon#about to write, iclass 7, count 2 2006.285.13:04:04.26#ibcon#wrote, iclass 7, count 2 2006.285.13:04:04.26#ibcon#about to read 3, iclass 7, count 2 2006.285.13:04:04.28#ibcon#read 3, iclass 7, count 2 2006.285.13:04:04.28#ibcon#about to read 4, iclass 7, count 2 2006.285.13:04:04.28#ibcon#read 4, iclass 7, count 2 2006.285.13:04:04.28#ibcon#about to read 5, iclass 7, count 2 2006.285.13:04:04.28#ibcon#read 5, iclass 7, count 2 2006.285.13:04:04.28#ibcon#about to read 6, iclass 7, count 2 2006.285.13:04:04.28#ibcon#read 6, iclass 7, count 2 2006.285.13:04:04.28#ibcon#end of sib2, iclass 7, count 2 2006.285.13:04:04.28#ibcon#*mode == 0, iclass 7, count 2 2006.285.13:04:04.28#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.13:04:04.28#ibcon#[25=AT05-03\r\n] 2006.285.13:04:04.28#ibcon#*before write, iclass 7, count 2 2006.285.13:04:04.28#ibcon#enter sib2, iclass 7, count 2 2006.285.13:04:04.28#ibcon#flushed, iclass 7, count 2 2006.285.13:04:04.28#ibcon#about to write, iclass 7, count 2 2006.285.13:04:04.28#ibcon#wrote, iclass 7, count 2 2006.285.13:04:04.28#ibcon#about to read 3, iclass 7, count 2 2006.285.13:04:04.31#ibcon#read 3, iclass 7, count 2 2006.285.13:04:04.31#ibcon#about to read 4, iclass 7, count 2 2006.285.13:04:04.31#ibcon#read 4, iclass 7, count 2 2006.285.13:04:04.31#ibcon#about to read 5, iclass 7, count 2 2006.285.13:04:04.31#ibcon#read 5, iclass 7, count 2 2006.285.13:04:04.31#ibcon#about to read 6, iclass 7, count 2 2006.285.13:04:04.31#ibcon#read 6, iclass 7, count 2 2006.285.13:04:04.31#ibcon#end of sib2, iclass 7, count 2 2006.285.13:04:04.31#ibcon#*after write, iclass 7, count 2 2006.285.13:04:04.31#ibcon#*before return 0, iclass 7, count 2 2006.285.13:04:04.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:04:04.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:04:04.31#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.13:04:04.31#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:04.31#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:04:04.43#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:04:04.43#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:04:04.43#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:04:04.43#ibcon#first serial, iclass 7, count 0 2006.285.13:04:04.43#ibcon#enter sib2, iclass 7, count 0 2006.285.13:04:04.43#ibcon#flushed, iclass 7, count 0 2006.285.13:04:04.43#ibcon#about to write, iclass 7, count 0 2006.285.13:04:04.43#ibcon#wrote, iclass 7, count 0 2006.285.13:04:04.43#ibcon#about to read 3, iclass 7, count 0 2006.285.13:04:04.45#ibcon#read 3, iclass 7, count 0 2006.285.13:04:04.45#ibcon#about to read 4, iclass 7, count 0 2006.285.13:04:04.45#ibcon#read 4, iclass 7, count 0 2006.285.13:04:04.45#ibcon#about to read 5, iclass 7, count 0 2006.285.13:04:04.45#ibcon#read 5, iclass 7, count 0 2006.285.13:04:04.45#ibcon#about to read 6, iclass 7, count 0 2006.285.13:04:04.45#ibcon#read 6, iclass 7, count 0 2006.285.13:04:04.45#ibcon#end of sib2, iclass 7, count 0 2006.285.13:04:04.45#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:04:04.45#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:04:04.45#ibcon#[25=USB\r\n] 2006.285.13:04:04.45#ibcon#*before write, iclass 7, count 0 2006.285.13:04:04.45#ibcon#enter sib2, iclass 7, count 0 2006.285.13:04:04.45#ibcon#flushed, iclass 7, count 0 2006.285.13:04:04.45#ibcon#about to write, iclass 7, count 0 2006.285.13:04:04.45#ibcon#wrote, iclass 7, count 0 2006.285.13:04:04.45#ibcon#about to read 3, iclass 7, count 0 2006.285.13:04:04.48#ibcon#read 3, iclass 7, count 0 2006.285.13:04:04.48#ibcon#about to read 4, iclass 7, count 0 2006.285.13:04:04.48#ibcon#read 4, iclass 7, count 0 2006.285.13:04:04.48#ibcon#about to read 5, iclass 7, count 0 2006.285.13:04:04.48#ibcon#read 5, iclass 7, count 0 2006.285.13:04:04.48#ibcon#about to read 6, iclass 7, count 0 2006.285.13:04:04.48#ibcon#read 6, iclass 7, count 0 2006.285.13:04:04.48#ibcon#end of sib2, iclass 7, count 0 2006.285.13:04:04.48#ibcon#*after write, iclass 7, count 0 2006.285.13:04:04.48#ibcon#*before return 0, iclass 7, count 0 2006.285.13:04:04.48#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:04:04.48#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:04:04.48#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:04:04.48#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:04:04.48$vck44/valo=6,814.99 2006.285.13:04:04.48#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.13:04:04.48#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.13:04:04.48#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:04.48#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:04:04.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:04:04.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:04:04.48#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:04:04.48#ibcon#first serial, iclass 11, count 0 2006.285.13:04:04.48#ibcon#enter sib2, iclass 11, count 0 2006.285.13:04:04.48#ibcon#flushed, iclass 11, count 0 2006.285.13:04:04.48#ibcon#about to write, iclass 11, count 0 2006.285.13:04:04.48#ibcon#wrote, iclass 11, count 0 2006.285.13:04:04.48#ibcon#about to read 3, iclass 11, count 0 2006.285.13:04:04.50#ibcon#read 3, iclass 11, count 0 2006.285.13:04:04.74#ibcon#about to read 4, iclass 11, count 0 2006.285.13:04:04.74#ibcon#read 4, iclass 11, count 0 2006.285.13:04:04.74#ibcon#about to read 5, iclass 11, count 0 2006.285.13:04:04.74#ibcon#read 5, iclass 11, count 0 2006.285.13:04:04.74#ibcon#about to read 6, iclass 11, count 0 2006.285.13:04:04.74#ibcon#read 6, iclass 11, count 0 2006.285.13:04:04.74#ibcon#end of sib2, iclass 11, count 0 2006.285.13:04:04.74#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:04:04.74#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:04:04.74#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:04:04.74#ibcon#*before write, iclass 11, count 0 2006.285.13:04:04.74#ibcon#enter sib2, iclass 11, count 0 2006.285.13:04:04.74#ibcon#flushed, iclass 11, count 0 2006.285.13:04:04.74#ibcon#about to write, iclass 11, count 0 2006.285.13:04:04.74#ibcon#wrote, iclass 11, count 0 2006.285.13:04:04.74#ibcon#about to read 3, iclass 11, count 0 2006.285.13:04:04.78#ibcon#read 3, iclass 11, count 0 2006.285.13:04:04.78#ibcon#about to read 4, iclass 11, count 0 2006.285.13:04:04.78#ibcon#read 4, iclass 11, count 0 2006.285.13:04:04.78#ibcon#about to read 5, iclass 11, count 0 2006.285.13:04:04.78#ibcon#read 5, iclass 11, count 0 2006.285.13:04:04.78#ibcon#about to read 6, iclass 11, count 0 2006.285.13:04:04.78#ibcon#read 6, iclass 11, count 0 2006.285.13:04:04.78#ibcon#end of sib2, iclass 11, count 0 2006.285.13:04:04.78#ibcon#*after write, iclass 11, count 0 2006.285.13:04:04.78#ibcon#*before return 0, iclass 11, count 0 2006.285.13:04:04.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:04:04.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:04:04.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:04:04.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:04:04.78$vck44/va=6,4 2006.285.13:04:04.78#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.13:04:04.78#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.13:04:04.78#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:04.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:04:04.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:04:04.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:04:04.78#ibcon#enter wrdev, iclass 13, count 2 2006.285.13:04:04.78#ibcon#first serial, iclass 13, count 2 2006.285.13:04:04.78#ibcon#enter sib2, iclass 13, count 2 2006.285.13:04:04.78#ibcon#flushed, iclass 13, count 2 2006.285.13:04:04.78#ibcon#about to write, iclass 13, count 2 2006.285.13:04:04.78#ibcon#wrote, iclass 13, count 2 2006.285.13:04:04.78#ibcon#about to read 3, iclass 13, count 2 2006.285.13:04:04.80#ibcon#read 3, iclass 13, count 2 2006.285.13:04:04.80#ibcon#about to read 4, iclass 13, count 2 2006.285.13:04:04.80#ibcon#read 4, iclass 13, count 2 2006.285.13:04:04.80#ibcon#about to read 5, iclass 13, count 2 2006.285.13:04:04.80#ibcon#read 5, iclass 13, count 2 2006.285.13:04:04.80#ibcon#about to read 6, iclass 13, count 2 2006.285.13:04:04.80#ibcon#read 6, iclass 13, count 2 2006.285.13:04:04.80#ibcon#end of sib2, iclass 13, count 2 2006.285.13:04:04.80#ibcon#*mode == 0, iclass 13, count 2 2006.285.13:04:04.80#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.13:04:04.80#ibcon#[25=AT06-04\r\n] 2006.285.13:04:04.80#ibcon#*before write, iclass 13, count 2 2006.285.13:04:04.80#ibcon#enter sib2, iclass 13, count 2 2006.285.13:04:04.80#ibcon#flushed, iclass 13, count 2 2006.285.13:04:04.80#ibcon#about to write, iclass 13, count 2 2006.285.13:04:04.80#ibcon#wrote, iclass 13, count 2 2006.285.13:04:04.80#ibcon#about to read 3, iclass 13, count 2 2006.285.13:04:04.83#ibcon#read 3, iclass 13, count 2 2006.285.13:04:04.83#ibcon#about to read 4, iclass 13, count 2 2006.285.13:04:04.83#ibcon#read 4, iclass 13, count 2 2006.285.13:04:04.83#ibcon#about to read 5, iclass 13, count 2 2006.285.13:04:04.83#ibcon#read 5, iclass 13, count 2 2006.285.13:04:04.83#ibcon#about to read 6, iclass 13, count 2 2006.285.13:04:04.83#ibcon#read 6, iclass 13, count 2 2006.285.13:04:04.83#ibcon#end of sib2, iclass 13, count 2 2006.285.13:04:04.83#ibcon#*after write, iclass 13, count 2 2006.285.13:04:04.83#ibcon#*before return 0, iclass 13, count 2 2006.285.13:04:04.83#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:04:04.83#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:04:04.83#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.13:04:04.83#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:04.83#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:04:04.95#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:04:04.95#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:04:04.95#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:04:04.95#ibcon#first serial, iclass 13, count 0 2006.285.13:04:04.95#ibcon#enter sib2, iclass 13, count 0 2006.285.13:04:04.95#ibcon#flushed, iclass 13, count 0 2006.285.13:04:04.95#ibcon#about to write, iclass 13, count 0 2006.285.13:04:04.95#ibcon#wrote, iclass 13, count 0 2006.285.13:04:04.95#ibcon#about to read 3, iclass 13, count 0 2006.285.13:04:04.97#ibcon#read 3, iclass 13, count 0 2006.285.13:04:04.97#ibcon#about to read 4, iclass 13, count 0 2006.285.13:04:04.97#ibcon#read 4, iclass 13, count 0 2006.285.13:04:04.97#ibcon#about to read 5, iclass 13, count 0 2006.285.13:04:04.97#ibcon#read 5, iclass 13, count 0 2006.285.13:04:04.97#ibcon#about to read 6, iclass 13, count 0 2006.285.13:04:04.97#ibcon#read 6, iclass 13, count 0 2006.285.13:04:04.97#ibcon#end of sib2, iclass 13, count 0 2006.285.13:04:04.97#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:04:04.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:04:04.97#ibcon#[25=USB\r\n] 2006.285.13:04:04.97#ibcon#*before write, iclass 13, count 0 2006.285.13:04:04.97#ibcon#enter sib2, iclass 13, count 0 2006.285.13:04:04.97#ibcon#flushed, iclass 13, count 0 2006.285.13:04:04.97#ibcon#about to write, iclass 13, count 0 2006.285.13:04:04.97#ibcon#wrote, iclass 13, count 0 2006.285.13:04:04.97#ibcon#about to read 3, iclass 13, count 0 2006.285.13:04:05.00#ibcon#read 3, iclass 13, count 0 2006.285.13:04:05.00#ibcon#about to read 4, iclass 13, count 0 2006.285.13:04:05.00#ibcon#read 4, iclass 13, count 0 2006.285.13:04:05.00#ibcon#about to read 5, iclass 13, count 0 2006.285.13:04:05.00#ibcon#read 5, iclass 13, count 0 2006.285.13:04:05.00#ibcon#about to read 6, iclass 13, count 0 2006.285.13:04:05.00#ibcon#read 6, iclass 13, count 0 2006.285.13:04:05.00#ibcon#end of sib2, iclass 13, count 0 2006.285.13:04:05.00#ibcon#*after write, iclass 13, count 0 2006.285.13:04:05.00#ibcon#*before return 0, iclass 13, count 0 2006.285.13:04:05.00#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:04:05.00#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:04:05.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:04:05.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:04:05.00$vck44/valo=7,864.99 2006.285.13:04:05.00#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.13:04:05.00#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.13:04:05.00#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:05.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:04:05.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:04:05.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:04:05.00#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:04:05.00#ibcon#first serial, iclass 15, count 0 2006.285.13:04:05.00#ibcon#enter sib2, iclass 15, count 0 2006.285.13:04:05.00#ibcon#flushed, iclass 15, count 0 2006.285.13:04:05.00#ibcon#about to write, iclass 15, count 0 2006.285.13:04:05.00#ibcon#wrote, iclass 15, count 0 2006.285.13:04:05.00#ibcon#about to read 3, iclass 15, count 0 2006.285.13:04:05.02#ibcon#read 3, iclass 15, count 0 2006.285.13:04:05.02#ibcon#about to read 4, iclass 15, count 0 2006.285.13:04:05.02#ibcon#read 4, iclass 15, count 0 2006.285.13:04:05.02#ibcon#about to read 5, iclass 15, count 0 2006.285.13:04:05.02#ibcon#read 5, iclass 15, count 0 2006.285.13:04:05.02#ibcon#about to read 6, iclass 15, count 0 2006.285.13:04:05.02#ibcon#read 6, iclass 15, count 0 2006.285.13:04:05.02#ibcon#end of sib2, iclass 15, count 0 2006.285.13:04:05.02#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:04:05.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:04:05.02#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:04:05.02#ibcon#*before write, iclass 15, count 0 2006.285.13:04:05.02#ibcon#enter sib2, iclass 15, count 0 2006.285.13:04:05.02#ibcon#flushed, iclass 15, count 0 2006.285.13:04:05.02#ibcon#about to write, iclass 15, count 0 2006.285.13:04:05.02#ibcon#wrote, iclass 15, count 0 2006.285.13:04:05.02#ibcon#about to read 3, iclass 15, count 0 2006.285.13:04:05.06#ibcon#read 3, iclass 15, count 0 2006.285.13:04:05.06#ibcon#about to read 4, iclass 15, count 0 2006.285.13:04:05.06#ibcon#read 4, iclass 15, count 0 2006.285.13:04:05.06#ibcon#about to read 5, iclass 15, count 0 2006.285.13:04:05.06#ibcon#read 5, iclass 15, count 0 2006.285.13:04:05.06#ibcon#about to read 6, iclass 15, count 0 2006.285.13:04:05.06#ibcon#read 6, iclass 15, count 0 2006.285.13:04:05.06#ibcon#end of sib2, iclass 15, count 0 2006.285.13:04:05.06#ibcon#*after write, iclass 15, count 0 2006.285.13:04:05.06#ibcon#*before return 0, iclass 15, count 0 2006.285.13:04:05.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:04:05.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:04:05.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:04:05.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:04:05.06$vck44/va=7,4 2006.285.13:04:05.06#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.13:04:05.06#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.13:04:05.06#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:05.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:04:05.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:04:05.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:04:05.12#ibcon#enter wrdev, iclass 17, count 2 2006.285.13:04:05.12#ibcon#first serial, iclass 17, count 2 2006.285.13:04:05.12#ibcon#enter sib2, iclass 17, count 2 2006.285.13:04:05.12#ibcon#flushed, iclass 17, count 2 2006.285.13:04:05.12#ibcon#about to write, iclass 17, count 2 2006.285.13:04:05.12#ibcon#wrote, iclass 17, count 2 2006.285.13:04:05.12#ibcon#about to read 3, iclass 17, count 2 2006.285.13:04:05.14#ibcon#read 3, iclass 17, count 2 2006.285.13:04:05.14#ibcon#about to read 4, iclass 17, count 2 2006.285.13:04:05.14#ibcon#read 4, iclass 17, count 2 2006.285.13:04:05.14#ibcon#about to read 5, iclass 17, count 2 2006.285.13:04:05.14#ibcon#read 5, iclass 17, count 2 2006.285.13:04:05.14#ibcon#about to read 6, iclass 17, count 2 2006.285.13:04:05.14#ibcon#read 6, iclass 17, count 2 2006.285.13:04:05.14#ibcon#end of sib2, iclass 17, count 2 2006.285.13:04:05.14#ibcon#*mode == 0, iclass 17, count 2 2006.285.13:04:05.14#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.13:04:05.14#ibcon#[25=AT07-04\r\n] 2006.285.13:04:05.14#ibcon#*before write, iclass 17, count 2 2006.285.13:04:05.14#ibcon#enter sib2, iclass 17, count 2 2006.285.13:04:05.14#ibcon#flushed, iclass 17, count 2 2006.285.13:04:05.14#ibcon#about to write, iclass 17, count 2 2006.285.13:04:05.14#ibcon#wrote, iclass 17, count 2 2006.285.13:04:05.14#ibcon#about to read 3, iclass 17, count 2 2006.285.13:04:05.17#ibcon#read 3, iclass 17, count 2 2006.285.13:04:05.17#ibcon#about to read 4, iclass 17, count 2 2006.285.13:04:05.17#ibcon#read 4, iclass 17, count 2 2006.285.13:04:05.17#ibcon#about to read 5, iclass 17, count 2 2006.285.13:04:05.17#ibcon#read 5, iclass 17, count 2 2006.285.13:04:05.17#ibcon#about to read 6, iclass 17, count 2 2006.285.13:04:05.17#ibcon#read 6, iclass 17, count 2 2006.285.13:04:05.17#ibcon#end of sib2, iclass 17, count 2 2006.285.13:04:05.17#ibcon#*after write, iclass 17, count 2 2006.285.13:04:05.17#ibcon#*before return 0, iclass 17, count 2 2006.285.13:04:05.17#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:04:05.17#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:04:05.17#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.13:04:05.17#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:05.17#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:04:05.29#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:04:05.29#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:04:05.29#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:04:05.29#ibcon#first serial, iclass 17, count 0 2006.285.13:04:05.29#ibcon#enter sib2, iclass 17, count 0 2006.285.13:04:05.29#ibcon#flushed, iclass 17, count 0 2006.285.13:04:05.29#ibcon#about to write, iclass 17, count 0 2006.285.13:04:05.29#ibcon#wrote, iclass 17, count 0 2006.285.13:04:05.29#ibcon#about to read 3, iclass 17, count 0 2006.285.13:04:05.31#ibcon#read 3, iclass 17, count 0 2006.285.13:04:05.31#ibcon#about to read 4, iclass 17, count 0 2006.285.13:04:05.31#ibcon#read 4, iclass 17, count 0 2006.285.13:04:05.31#ibcon#about to read 5, iclass 17, count 0 2006.285.13:04:05.31#ibcon#read 5, iclass 17, count 0 2006.285.13:04:05.31#ibcon#about to read 6, iclass 17, count 0 2006.285.13:04:05.31#ibcon#read 6, iclass 17, count 0 2006.285.13:04:05.31#ibcon#end of sib2, iclass 17, count 0 2006.285.13:04:05.31#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:04:05.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:04:05.31#ibcon#[25=USB\r\n] 2006.285.13:04:05.31#ibcon#*before write, iclass 17, count 0 2006.285.13:04:05.31#ibcon#enter sib2, iclass 17, count 0 2006.285.13:04:05.31#ibcon#flushed, iclass 17, count 0 2006.285.13:04:05.31#ibcon#about to write, iclass 17, count 0 2006.285.13:04:05.31#ibcon#wrote, iclass 17, count 0 2006.285.13:04:05.31#ibcon#about to read 3, iclass 17, count 0 2006.285.13:04:05.34#ibcon#read 3, iclass 17, count 0 2006.285.13:04:05.34#ibcon#about to read 4, iclass 17, count 0 2006.285.13:04:05.34#ibcon#read 4, iclass 17, count 0 2006.285.13:04:05.34#ibcon#about to read 5, iclass 17, count 0 2006.285.13:04:05.34#ibcon#read 5, iclass 17, count 0 2006.285.13:04:05.34#ibcon#about to read 6, iclass 17, count 0 2006.285.13:04:05.34#ibcon#read 6, iclass 17, count 0 2006.285.13:04:05.34#ibcon#end of sib2, iclass 17, count 0 2006.285.13:04:05.34#ibcon#*after write, iclass 17, count 0 2006.285.13:04:05.34#ibcon#*before return 0, iclass 17, count 0 2006.285.13:04:05.34#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:04:05.34#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:04:05.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:04:05.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:04:05.34$vck44/valo=8,884.99 2006.285.13:04:05.34#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.13:04:05.34#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.13:04:05.34#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:05.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:04:05.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:04:05.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:04:05.34#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:04:05.34#ibcon#first serial, iclass 19, count 0 2006.285.13:04:05.34#ibcon#enter sib2, iclass 19, count 0 2006.285.13:04:05.34#ibcon#flushed, iclass 19, count 0 2006.285.13:04:05.34#ibcon#about to write, iclass 19, count 0 2006.285.13:04:05.34#ibcon#wrote, iclass 19, count 0 2006.285.13:04:05.34#ibcon#about to read 3, iclass 19, count 0 2006.285.13:04:05.36#ibcon#read 3, iclass 19, count 0 2006.285.13:04:05.36#ibcon#about to read 4, iclass 19, count 0 2006.285.13:04:05.36#ibcon#read 4, iclass 19, count 0 2006.285.13:04:05.36#ibcon#about to read 5, iclass 19, count 0 2006.285.13:04:05.36#ibcon#read 5, iclass 19, count 0 2006.285.13:04:05.36#ibcon#about to read 6, iclass 19, count 0 2006.285.13:04:05.36#ibcon#read 6, iclass 19, count 0 2006.285.13:04:05.36#ibcon#end of sib2, iclass 19, count 0 2006.285.13:04:05.36#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:04:05.36#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:04:05.36#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:04:05.36#ibcon#*before write, iclass 19, count 0 2006.285.13:04:05.36#ibcon#enter sib2, iclass 19, count 0 2006.285.13:04:05.36#ibcon#flushed, iclass 19, count 0 2006.285.13:04:05.36#ibcon#about to write, iclass 19, count 0 2006.285.13:04:05.36#ibcon#wrote, iclass 19, count 0 2006.285.13:04:05.36#ibcon#about to read 3, iclass 19, count 0 2006.285.13:04:05.40#ibcon#read 3, iclass 19, count 0 2006.285.13:04:05.40#ibcon#about to read 4, iclass 19, count 0 2006.285.13:04:05.40#ibcon#read 4, iclass 19, count 0 2006.285.13:04:05.40#ibcon#about to read 5, iclass 19, count 0 2006.285.13:04:05.40#ibcon#read 5, iclass 19, count 0 2006.285.13:04:05.40#ibcon#about to read 6, iclass 19, count 0 2006.285.13:04:05.40#ibcon#read 6, iclass 19, count 0 2006.285.13:04:05.40#ibcon#end of sib2, iclass 19, count 0 2006.285.13:04:05.40#ibcon#*after write, iclass 19, count 0 2006.285.13:04:05.40#ibcon#*before return 0, iclass 19, count 0 2006.285.13:04:05.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:04:05.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:04:05.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:04:05.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:04:05.40$vck44/va=8,3 2006.285.13:04:05.40#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.13:04:05.40#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.13:04:05.40#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:05.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:04:05.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:04:05.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:04:05.46#ibcon#enter wrdev, iclass 21, count 2 2006.285.13:04:05.46#ibcon#first serial, iclass 21, count 2 2006.285.13:04:05.46#ibcon#enter sib2, iclass 21, count 2 2006.285.13:04:05.46#ibcon#flushed, iclass 21, count 2 2006.285.13:04:05.46#ibcon#about to write, iclass 21, count 2 2006.285.13:04:05.46#ibcon#wrote, iclass 21, count 2 2006.285.13:04:05.46#ibcon#about to read 3, iclass 21, count 2 2006.285.13:04:05.48#ibcon#read 3, iclass 21, count 2 2006.285.13:04:05.48#ibcon#about to read 4, iclass 21, count 2 2006.285.13:04:05.48#ibcon#read 4, iclass 21, count 2 2006.285.13:04:05.48#ibcon#about to read 5, iclass 21, count 2 2006.285.13:04:05.48#ibcon#read 5, iclass 21, count 2 2006.285.13:04:05.48#ibcon#about to read 6, iclass 21, count 2 2006.285.13:04:05.48#ibcon#read 6, iclass 21, count 2 2006.285.13:04:05.48#ibcon#end of sib2, iclass 21, count 2 2006.285.13:04:05.48#ibcon#*mode == 0, iclass 21, count 2 2006.285.13:04:05.48#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.13:04:05.48#ibcon#[25=AT08-03\r\n] 2006.285.13:04:05.48#ibcon#*before write, iclass 21, count 2 2006.285.13:04:05.48#ibcon#enter sib2, iclass 21, count 2 2006.285.13:04:05.48#ibcon#flushed, iclass 21, count 2 2006.285.13:04:05.48#ibcon#about to write, iclass 21, count 2 2006.285.13:04:05.48#ibcon#wrote, iclass 21, count 2 2006.285.13:04:05.48#ibcon#about to read 3, iclass 21, count 2 2006.285.13:04:05.51#ibcon#read 3, iclass 21, count 2 2006.285.13:04:05.51#ibcon#about to read 4, iclass 21, count 2 2006.285.13:04:05.51#ibcon#read 4, iclass 21, count 2 2006.285.13:04:05.51#ibcon#about to read 5, iclass 21, count 2 2006.285.13:04:05.51#ibcon#read 5, iclass 21, count 2 2006.285.13:04:05.51#ibcon#about to read 6, iclass 21, count 2 2006.285.13:04:05.51#ibcon#read 6, iclass 21, count 2 2006.285.13:04:05.51#ibcon#end of sib2, iclass 21, count 2 2006.285.13:04:05.51#ibcon#*after write, iclass 21, count 2 2006.285.13:04:05.51#ibcon#*before return 0, iclass 21, count 2 2006.285.13:04:05.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:04:05.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:04:05.51#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.13:04:05.51#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:05.51#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:04:05.63#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:04:05.63#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:04:05.63#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:04:05.63#ibcon#first serial, iclass 21, count 0 2006.285.13:04:05.63#ibcon#enter sib2, iclass 21, count 0 2006.285.13:04:05.63#ibcon#flushed, iclass 21, count 0 2006.285.13:04:05.63#ibcon#about to write, iclass 21, count 0 2006.285.13:04:05.63#ibcon#wrote, iclass 21, count 0 2006.285.13:04:05.63#ibcon#about to read 3, iclass 21, count 0 2006.285.13:04:05.65#ibcon#read 3, iclass 21, count 0 2006.285.13:04:05.65#ibcon#about to read 4, iclass 21, count 0 2006.285.13:04:05.65#ibcon#read 4, iclass 21, count 0 2006.285.13:04:05.65#ibcon#about to read 5, iclass 21, count 0 2006.285.13:04:05.65#ibcon#read 5, iclass 21, count 0 2006.285.13:04:05.65#ibcon#about to read 6, iclass 21, count 0 2006.285.13:04:05.65#ibcon#read 6, iclass 21, count 0 2006.285.13:04:05.65#ibcon#end of sib2, iclass 21, count 0 2006.285.13:04:05.65#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:04:05.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:04:05.65#ibcon#[25=USB\r\n] 2006.285.13:04:05.65#ibcon#*before write, iclass 21, count 0 2006.285.13:04:05.65#ibcon#enter sib2, iclass 21, count 0 2006.285.13:04:05.65#ibcon#flushed, iclass 21, count 0 2006.285.13:04:05.65#ibcon#about to write, iclass 21, count 0 2006.285.13:04:05.65#ibcon#wrote, iclass 21, count 0 2006.285.13:04:05.65#ibcon#about to read 3, iclass 21, count 0 2006.285.13:04:05.68#ibcon#read 3, iclass 21, count 0 2006.285.13:04:05.68#ibcon#about to read 4, iclass 21, count 0 2006.285.13:04:05.68#ibcon#read 4, iclass 21, count 0 2006.285.13:04:05.68#ibcon#about to read 5, iclass 21, count 0 2006.285.13:04:05.68#ibcon#read 5, iclass 21, count 0 2006.285.13:04:05.68#ibcon#about to read 6, iclass 21, count 0 2006.285.13:04:05.68#ibcon#read 6, iclass 21, count 0 2006.285.13:04:05.68#ibcon#end of sib2, iclass 21, count 0 2006.285.13:04:05.68#ibcon#*after write, iclass 21, count 0 2006.285.13:04:05.68#ibcon#*before return 0, iclass 21, count 0 2006.285.13:04:05.68#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:04:05.68#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:04:05.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:04:05.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:04:05.68$vck44/vblo=1,629.99 2006.285.13:04:05.68#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.13:04:05.68#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.13:04:05.68#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:05.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:04:05.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:04:05.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:04:05.68#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:04:05.68#ibcon#first serial, iclass 23, count 0 2006.285.13:04:05.68#ibcon#enter sib2, iclass 23, count 0 2006.285.13:04:05.68#ibcon#flushed, iclass 23, count 0 2006.285.13:04:05.68#ibcon#about to write, iclass 23, count 0 2006.285.13:04:05.68#ibcon#wrote, iclass 23, count 0 2006.285.13:04:05.68#ibcon#about to read 3, iclass 23, count 0 2006.285.13:04:05.70#ibcon#read 3, iclass 23, count 0 2006.285.13:04:05.70#ibcon#about to read 4, iclass 23, count 0 2006.285.13:04:05.70#ibcon#read 4, iclass 23, count 0 2006.285.13:04:05.70#ibcon#about to read 5, iclass 23, count 0 2006.285.13:04:05.70#ibcon#read 5, iclass 23, count 0 2006.285.13:04:05.70#ibcon#about to read 6, iclass 23, count 0 2006.285.13:04:05.70#ibcon#read 6, iclass 23, count 0 2006.285.13:04:05.70#ibcon#end of sib2, iclass 23, count 0 2006.285.13:04:05.70#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:04:05.70#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:04:05.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:04:05.70#ibcon#*before write, iclass 23, count 0 2006.285.13:04:05.70#ibcon#enter sib2, iclass 23, count 0 2006.285.13:04:05.70#ibcon#flushed, iclass 23, count 0 2006.285.13:04:05.70#ibcon#about to write, iclass 23, count 0 2006.285.13:04:05.70#ibcon#wrote, iclass 23, count 0 2006.285.13:04:05.70#ibcon#about to read 3, iclass 23, count 0 2006.285.13:04:05.74#ibcon#read 3, iclass 23, count 0 2006.285.13:04:05.74#ibcon#about to read 4, iclass 23, count 0 2006.285.13:04:05.74#ibcon#read 4, iclass 23, count 0 2006.285.13:04:05.74#ibcon#about to read 5, iclass 23, count 0 2006.285.13:04:05.74#ibcon#read 5, iclass 23, count 0 2006.285.13:04:05.74#ibcon#about to read 6, iclass 23, count 0 2006.285.13:04:05.74#ibcon#read 6, iclass 23, count 0 2006.285.13:04:05.74#ibcon#end of sib2, iclass 23, count 0 2006.285.13:04:05.74#ibcon#*after write, iclass 23, count 0 2006.285.13:04:05.74#ibcon#*before return 0, iclass 23, count 0 2006.285.13:04:05.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:04:05.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:04:05.74#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:04:05.74#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:04:05.74$vck44/vb=1,4 2006.285.13:04:05.74#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.13:04:05.74#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.13:04:05.74#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:05.74#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:04:05.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:04:05.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:04:05.74#ibcon#enter wrdev, iclass 25, count 2 2006.285.13:04:05.74#ibcon#first serial, iclass 25, count 2 2006.285.13:04:05.74#ibcon#enter sib2, iclass 25, count 2 2006.285.13:04:05.74#ibcon#flushed, iclass 25, count 2 2006.285.13:04:05.74#ibcon#about to write, iclass 25, count 2 2006.285.13:04:05.74#ibcon#wrote, iclass 25, count 2 2006.285.13:04:05.74#ibcon#about to read 3, iclass 25, count 2 2006.285.13:04:05.76#ibcon#read 3, iclass 25, count 2 2006.285.13:04:05.76#ibcon#about to read 4, iclass 25, count 2 2006.285.13:04:05.76#ibcon#read 4, iclass 25, count 2 2006.285.13:04:05.76#ibcon#about to read 5, iclass 25, count 2 2006.285.13:04:05.76#ibcon#read 5, iclass 25, count 2 2006.285.13:04:05.76#ibcon#about to read 6, iclass 25, count 2 2006.285.13:04:05.76#ibcon#read 6, iclass 25, count 2 2006.285.13:04:05.76#ibcon#end of sib2, iclass 25, count 2 2006.285.13:04:05.76#ibcon#*mode == 0, iclass 25, count 2 2006.285.13:04:05.76#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.13:04:05.76#ibcon#[27=AT01-04\r\n] 2006.285.13:04:05.76#ibcon#*before write, iclass 25, count 2 2006.285.13:04:05.76#ibcon#enter sib2, iclass 25, count 2 2006.285.13:04:05.76#ibcon#flushed, iclass 25, count 2 2006.285.13:04:05.76#ibcon#about to write, iclass 25, count 2 2006.285.13:04:05.76#ibcon#wrote, iclass 25, count 2 2006.285.13:04:05.76#ibcon#about to read 3, iclass 25, count 2 2006.285.13:04:05.79#ibcon#read 3, iclass 25, count 2 2006.285.13:04:05.79#ibcon#about to read 4, iclass 25, count 2 2006.285.13:04:05.79#ibcon#read 4, iclass 25, count 2 2006.285.13:04:05.79#ibcon#about to read 5, iclass 25, count 2 2006.285.13:04:05.79#ibcon#read 5, iclass 25, count 2 2006.285.13:04:05.79#ibcon#about to read 6, iclass 25, count 2 2006.285.13:04:05.79#ibcon#read 6, iclass 25, count 2 2006.285.13:04:05.79#ibcon#end of sib2, iclass 25, count 2 2006.285.13:04:05.79#ibcon#*after write, iclass 25, count 2 2006.285.13:04:05.79#ibcon#*before return 0, iclass 25, count 2 2006.285.13:04:05.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:04:05.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:04:05.79#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.13:04:05.79#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:05.79#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:04:05.91#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:04:05.91#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:04:05.91#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:04:05.91#ibcon#first serial, iclass 25, count 0 2006.285.13:04:05.91#ibcon#enter sib2, iclass 25, count 0 2006.285.13:04:05.91#ibcon#flushed, iclass 25, count 0 2006.285.13:04:05.91#ibcon#about to write, iclass 25, count 0 2006.285.13:04:05.91#ibcon#wrote, iclass 25, count 0 2006.285.13:04:05.91#ibcon#about to read 3, iclass 25, count 0 2006.285.13:04:05.93#ibcon#read 3, iclass 25, count 0 2006.285.13:04:05.93#ibcon#about to read 4, iclass 25, count 0 2006.285.13:04:05.93#ibcon#read 4, iclass 25, count 0 2006.285.13:04:05.93#ibcon#about to read 5, iclass 25, count 0 2006.285.13:04:05.93#ibcon#read 5, iclass 25, count 0 2006.285.13:04:05.93#ibcon#about to read 6, iclass 25, count 0 2006.285.13:04:05.93#ibcon#read 6, iclass 25, count 0 2006.285.13:04:05.93#ibcon#end of sib2, iclass 25, count 0 2006.285.13:04:05.93#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:04:05.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:04:05.93#ibcon#[27=USB\r\n] 2006.285.13:04:05.93#ibcon#*before write, iclass 25, count 0 2006.285.13:04:05.93#ibcon#enter sib2, iclass 25, count 0 2006.285.13:04:05.93#ibcon#flushed, iclass 25, count 0 2006.285.13:04:05.93#ibcon#about to write, iclass 25, count 0 2006.285.13:04:05.93#ibcon#wrote, iclass 25, count 0 2006.285.13:04:05.93#ibcon#about to read 3, iclass 25, count 0 2006.285.13:04:05.96#ibcon#read 3, iclass 25, count 0 2006.285.13:04:05.96#ibcon#about to read 4, iclass 25, count 0 2006.285.13:04:05.96#ibcon#read 4, iclass 25, count 0 2006.285.13:04:05.96#ibcon#about to read 5, iclass 25, count 0 2006.285.13:04:05.96#ibcon#read 5, iclass 25, count 0 2006.285.13:04:05.96#ibcon#about to read 6, iclass 25, count 0 2006.285.13:04:05.96#ibcon#read 6, iclass 25, count 0 2006.285.13:04:05.96#ibcon#end of sib2, iclass 25, count 0 2006.285.13:04:05.96#ibcon#*after write, iclass 25, count 0 2006.285.13:04:05.96#ibcon#*before return 0, iclass 25, count 0 2006.285.13:04:05.96#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:04:05.96#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:04:05.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:04:05.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:04:05.96$vck44/vblo=2,634.99 2006.285.13:04:05.96#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.13:04:05.96#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.13:04:05.96#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:05.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:04:05.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:04:05.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:04:05.96#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:04:05.96#ibcon#first serial, iclass 27, count 0 2006.285.13:04:05.96#ibcon#enter sib2, iclass 27, count 0 2006.285.13:04:05.96#ibcon#flushed, iclass 27, count 0 2006.285.13:04:05.96#ibcon#about to write, iclass 27, count 0 2006.285.13:04:05.96#ibcon#wrote, iclass 27, count 0 2006.285.13:04:05.96#ibcon#about to read 3, iclass 27, count 0 2006.285.13:04:05.98#ibcon#read 3, iclass 27, count 0 2006.285.13:04:05.98#ibcon#about to read 4, iclass 27, count 0 2006.285.13:04:05.98#ibcon#read 4, iclass 27, count 0 2006.285.13:04:05.98#ibcon#about to read 5, iclass 27, count 0 2006.285.13:04:05.98#ibcon#read 5, iclass 27, count 0 2006.285.13:04:05.98#ibcon#about to read 6, iclass 27, count 0 2006.285.13:04:05.98#ibcon#read 6, iclass 27, count 0 2006.285.13:04:05.98#ibcon#end of sib2, iclass 27, count 0 2006.285.13:04:05.98#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:04:05.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:04:05.98#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:04:05.98#ibcon#*before write, iclass 27, count 0 2006.285.13:04:05.98#ibcon#enter sib2, iclass 27, count 0 2006.285.13:04:05.98#ibcon#flushed, iclass 27, count 0 2006.285.13:04:05.98#ibcon#about to write, iclass 27, count 0 2006.285.13:04:05.98#ibcon#wrote, iclass 27, count 0 2006.285.13:04:05.98#ibcon#about to read 3, iclass 27, count 0 2006.285.13:04:06.02#ibcon#read 3, iclass 27, count 0 2006.285.13:04:06.02#ibcon#about to read 4, iclass 27, count 0 2006.285.13:04:06.02#ibcon#read 4, iclass 27, count 0 2006.285.13:04:06.02#ibcon#about to read 5, iclass 27, count 0 2006.285.13:04:06.02#ibcon#read 5, iclass 27, count 0 2006.285.13:04:06.02#ibcon#about to read 6, iclass 27, count 0 2006.285.13:04:06.02#ibcon#read 6, iclass 27, count 0 2006.285.13:04:06.02#ibcon#end of sib2, iclass 27, count 0 2006.285.13:04:06.02#ibcon#*after write, iclass 27, count 0 2006.285.13:04:06.02#ibcon#*before return 0, iclass 27, count 0 2006.285.13:04:06.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:04:06.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:04:06.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:04:06.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:04:06.02$vck44/vb=2,5 2006.285.13:04:06.02#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.13:04:06.02#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.13:04:06.02#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:06.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:04:06.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:04:06.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:04:06.08#ibcon#enter wrdev, iclass 29, count 2 2006.285.13:04:06.08#ibcon#first serial, iclass 29, count 2 2006.285.13:04:06.08#ibcon#enter sib2, iclass 29, count 2 2006.285.13:04:06.08#ibcon#flushed, iclass 29, count 2 2006.285.13:04:06.08#ibcon#about to write, iclass 29, count 2 2006.285.13:04:06.08#ibcon#wrote, iclass 29, count 2 2006.285.13:04:06.08#ibcon#about to read 3, iclass 29, count 2 2006.285.13:04:06.10#ibcon#read 3, iclass 29, count 2 2006.285.13:04:06.10#ibcon#about to read 4, iclass 29, count 2 2006.285.13:04:06.10#ibcon#read 4, iclass 29, count 2 2006.285.13:04:06.10#ibcon#about to read 5, iclass 29, count 2 2006.285.13:04:06.10#ibcon#read 5, iclass 29, count 2 2006.285.13:04:06.10#ibcon#about to read 6, iclass 29, count 2 2006.285.13:04:06.10#ibcon#read 6, iclass 29, count 2 2006.285.13:04:06.10#ibcon#end of sib2, iclass 29, count 2 2006.285.13:04:06.10#ibcon#*mode == 0, iclass 29, count 2 2006.285.13:04:06.10#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.13:04:06.10#ibcon#[27=AT02-05\r\n] 2006.285.13:04:06.10#ibcon#*before write, iclass 29, count 2 2006.285.13:04:06.10#ibcon#enter sib2, iclass 29, count 2 2006.285.13:04:06.10#ibcon#flushed, iclass 29, count 2 2006.285.13:04:06.10#ibcon#about to write, iclass 29, count 2 2006.285.13:04:06.10#ibcon#wrote, iclass 29, count 2 2006.285.13:04:06.10#ibcon#about to read 3, iclass 29, count 2 2006.285.13:04:06.13#ibcon#read 3, iclass 29, count 2 2006.285.13:04:06.13#ibcon#about to read 4, iclass 29, count 2 2006.285.13:04:06.13#ibcon#read 4, iclass 29, count 2 2006.285.13:04:06.13#ibcon#about to read 5, iclass 29, count 2 2006.285.13:04:06.13#ibcon#read 5, iclass 29, count 2 2006.285.13:04:06.13#ibcon#about to read 6, iclass 29, count 2 2006.285.13:04:06.13#ibcon#read 6, iclass 29, count 2 2006.285.13:04:06.13#ibcon#end of sib2, iclass 29, count 2 2006.285.13:04:06.13#ibcon#*after write, iclass 29, count 2 2006.285.13:04:06.13#ibcon#*before return 0, iclass 29, count 2 2006.285.13:04:06.13#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:04:06.13#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:04:06.13#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.13:04:06.13#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:06.13#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:04:06.25#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:04:06.25#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:04:06.25#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:04:06.25#ibcon#first serial, iclass 29, count 0 2006.285.13:04:06.25#ibcon#enter sib2, iclass 29, count 0 2006.285.13:04:06.25#ibcon#flushed, iclass 29, count 0 2006.285.13:04:06.25#ibcon#about to write, iclass 29, count 0 2006.285.13:04:06.25#ibcon#wrote, iclass 29, count 0 2006.285.13:04:06.25#ibcon#about to read 3, iclass 29, count 0 2006.285.13:04:06.27#ibcon#read 3, iclass 29, count 0 2006.285.13:04:06.27#ibcon#about to read 4, iclass 29, count 0 2006.285.13:04:06.27#ibcon#read 4, iclass 29, count 0 2006.285.13:04:06.27#ibcon#about to read 5, iclass 29, count 0 2006.285.13:04:06.27#ibcon#read 5, iclass 29, count 0 2006.285.13:04:06.27#ibcon#about to read 6, iclass 29, count 0 2006.285.13:04:06.27#ibcon#read 6, iclass 29, count 0 2006.285.13:04:06.27#ibcon#end of sib2, iclass 29, count 0 2006.285.13:04:06.27#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:04:06.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:04:06.27#ibcon#[27=USB\r\n] 2006.285.13:04:06.27#ibcon#*before write, iclass 29, count 0 2006.285.13:04:06.27#ibcon#enter sib2, iclass 29, count 0 2006.285.13:04:06.27#ibcon#flushed, iclass 29, count 0 2006.285.13:04:06.27#ibcon#about to write, iclass 29, count 0 2006.285.13:04:06.27#ibcon#wrote, iclass 29, count 0 2006.285.13:04:06.27#ibcon#about to read 3, iclass 29, count 0 2006.285.13:04:06.30#ibcon#read 3, iclass 29, count 0 2006.285.13:04:06.30#ibcon#about to read 4, iclass 29, count 0 2006.285.13:04:06.30#ibcon#read 4, iclass 29, count 0 2006.285.13:04:06.30#ibcon#about to read 5, iclass 29, count 0 2006.285.13:04:06.30#ibcon#read 5, iclass 29, count 0 2006.285.13:04:06.30#ibcon#about to read 6, iclass 29, count 0 2006.285.13:04:06.30#ibcon#read 6, iclass 29, count 0 2006.285.13:04:06.30#ibcon#end of sib2, iclass 29, count 0 2006.285.13:04:06.30#ibcon#*after write, iclass 29, count 0 2006.285.13:04:06.30#ibcon#*before return 0, iclass 29, count 0 2006.285.13:04:06.30#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:04:06.30#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:04:06.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:04:06.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:04:06.30$vck44/vblo=3,649.99 2006.285.13:04:06.30#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.13:04:06.30#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.13:04:06.30#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:06.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:04:06.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:04:06.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:04:06.30#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:04:06.30#ibcon#first serial, iclass 31, count 0 2006.285.13:04:06.30#ibcon#enter sib2, iclass 31, count 0 2006.285.13:04:06.30#ibcon#flushed, iclass 31, count 0 2006.285.13:04:06.30#ibcon#about to write, iclass 31, count 0 2006.285.13:04:06.30#ibcon#wrote, iclass 31, count 0 2006.285.13:04:06.30#ibcon#about to read 3, iclass 31, count 0 2006.285.13:04:06.32#ibcon#read 3, iclass 31, count 0 2006.285.13:04:06.32#ibcon#about to read 4, iclass 31, count 0 2006.285.13:04:06.32#ibcon#read 4, iclass 31, count 0 2006.285.13:04:06.32#ibcon#about to read 5, iclass 31, count 0 2006.285.13:04:06.32#ibcon#read 5, iclass 31, count 0 2006.285.13:04:06.32#ibcon#about to read 6, iclass 31, count 0 2006.285.13:04:06.32#ibcon#read 6, iclass 31, count 0 2006.285.13:04:06.32#ibcon#end of sib2, iclass 31, count 0 2006.285.13:04:06.32#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:04:06.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:04:06.32#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:04:06.32#ibcon#*before write, iclass 31, count 0 2006.285.13:04:06.32#ibcon#enter sib2, iclass 31, count 0 2006.285.13:04:06.32#ibcon#flushed, iclass 31, count 0 2006.285.13:04:06.32#ibcon#about to write, iclass 31, count 0 2006.285.13:04:06.32#ibcon#wrote, iclass 31, count 0 2006.285.13:04:06.32#ibcon#about to read 3, iclass 31, count 0 2006.285.13:04:06.36#ibcon#read 3, iclass 31, count 0 2006.285.13:04:06.36#ibcon#about to read 4, iclass 31, count 0 2006.285.13:04:06.36#ibcon#read 4, iclass 31, count 0 2006.285.13:04:06.36#ibcon#about to read 5, iclass 31, count 0 2006.285.13:04:06.36#ibcon#read 5, iclass 31, count 0 2006.285.13:04:06.36#ibcon#about to read 6, iclass 31, count 0 2006.285.13:04:06.36#ibcon#read 6, iclass 31, count 0 2006.285.13:04:06.36#ibcon#end of sib2, iclass 31, count 0 2006.285.13:04:06.36#ibcon#*after write, iclass 31, count 0 2006.285.13:04:06.36#ibcon#*before return 0, iclass 31, count 0 2006.285.13:04:06.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:04:06.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:04:06.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:04:06.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:04:06.36$vck44/vb=3,4 2006.285.13:04:06.36#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.13:04:06.36#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.13:04:06.36#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:06.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:04:06.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:04:06.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:04:06.42#ibcon#enter wrdev, iclass 33, count 2 2006.285.13:04:06.42#ibcon#first serial, iclass 33, count 2 2006.285.13:04:06.42#ibcon#enter sib2, iclass 33, count 2 2006.285.13:04:06.42#ibcon#flushed, iclass 33, count 2 2006.285.13:04:06.42#ibcon#about to write, iclass 33, count 2 2006.285.13:04:06.42#ibcon#wrote, iclass 33, count 2 2006.285.13:04:06.42#ibcon#about to read 3, iclass 33, count 2 2006.285.13:04:06.44#ibcon#read 3, iclass 33, count 2 2006.285.13:04:06.44#ibcon#about to read 4, iclass 33, count 2 2006.285.13:04:06.44#ibcon#read 4, iclass 33, count 2 2006.285.13:04:06.44#ibcon#about to read 5, iclass 33, count 2 2006.285.13:04:06.44#ibcon#read 5, iclass 33, count 2 2006.285.13:04:06.44#ibcon#about to read 6, iclass 33, count 2 2006.285.13:04:06.44#ibcon#read 6, iclass 33, count 2 2006.285.13:04:06.44#ibcon#end of sib2, iclass 33, count 2 2006.285.13:04:06.44#ibcon#*mode == 0, iclass 33, count 2 2006.285.13:04:06.44#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.13:04:06.44#ibcon#[27=AT03-04\r\n] 2006.285.13:04:06.44#ibcon#*before write, iclass 33, count 2 2006.285.13:04:06.44#ibcon#enter sib2, iclass 33, count 2 2006.285.13:04:06.44#ibcon#flushed, iclass 33, count 2 2006.285.13:04:06.44#ibcon#about to write, iclass 33, count 2 2006.285.13:04:06.44#ibcon#wrote, iclass 33, count 2 2006.285.13:04:06.44#ibcon#about to read 3, iclass 33, count 2 2006.285.13:04:06.47#ibcon#read 3, iclass 33, count 2 2006.285.13:04:06.47#ibcon#about to read 4, iclass 33, count 2 2006.285.13:04:06.47#ibcon#read 4, iclass 33, count 2 2006.285.13:04:06.47#ibcon#about to read 5, iclass 33, count 2 2006.285.13:04:06.47#ibcon#read 5, iclass 33, count 2 2006.285.13:04:06.47#ibcon#about to read 6, iclass 33, count 2 2006.285.13:04:06.47#ibcon#read 6, iclass 33, count 2 2006.285.13:04:06.47#ibcon#end of sib2, iclass 33, count 2 2006.285.13:04:06.47#ibcon#*after write, iclass 33, count 2 2006.285.13:04:06.47#ibcon#*before return 0, iclass 33, count 2 2006.285.13:04:06.47#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:04:06.47#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:04:06.47#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.13:04:06.47#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:06.47#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:04:06.59#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:04:06.59#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:04:06.59#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:04:06.59#ibcon#first serial, iclass 33, count 0 2006.285.13:04:06.59#ibcon#enter sib2, iclass 33, count 0 2006.285.13:04:06.59#ibcon#flushed, iclass 33, count 0 2006.285.13:04:06.59#ibcon#about to write, iclass 33, count 0 2006.285.13:04:06.59#ibcon#wrote, iclass 33, count 0 2006.285.13:04:06.59#ibcon#about to read 3, iclass 33, count 0 2006.285.13:04:06.61#ibcon#read 3, iclass 33, count 0 2006.285.13:04:06.61#ibcon#about to read 4, iclass 33, count 0 2006.285.13:04:06.61#ibcon#read 4, iclass 33, count 0 2006.285.13:04:06.61#ibcon#about to read 5, iclass 33, count 0 2006.285.13:04:06.61#ibcon#read 5, iclass 33, count 0 2006.285.13:04:06.61#ibcon#about to read 6, iclass 33, count 0 2006.285.13:04:06.61#ibcon#read 6, iclass 33, count 0 2006.285.13:04:06.61#ibcon#end of sib2, iclass 33, count 0 2006.285.13:04:06.61#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:04:06.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:04:06.61#ibcon#[27=USB\r\n] 2006.285.13:04:06.61#ibcon#*before write, iclass 33, count 0 2006.285.13:04:06.61#ibcon#enter sib2, iclass 33, count 0 2006.285.13:04:06.61#ibcon#flushed, iclass 33, count 0 2006.285.13:04:06.61#ibcon#about to write, iclass 33, count 0 2006.285.13:04:06.61#ibcon#wrote, iclass 33, count 0 2006.285.13:04:06.61#ibcon#about to read 3, iclass 33, count 0 2006.285.13:04:06.64#ibcon#read 3, iclass 33, count 0 2006.285.13:04:06.64#ibcon#about to read 4, iclass 33, count 0 2006.285.13:04:06.64#ibcon#read 4, iclass 33, count 0 2006.285.13:04:06.64#ibcon#about to read 5, iclass 33, count 0 2006.285.13:04:06.64#ibcon#read 5, iclass 33, count 0 2006.285.13:04:06.64#ibcon#about to read 6, iclass 33, count 0 2006.285.13:04:06.64#ibcon#read 6, iclass 33, count 0 2006.285.13:04:06.64#ibcon#end of sib2, iclass 33, count 0 2006.285.13:04:06.64#ibcon#*after write, iclass 33, count 0 2006.285.13:04:06.64#ibcon#*before return 0, iclass 33, count 0 2006.285.13:04:06.64#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:04:06.64#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:04:06.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:04:06.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:04:06.64$vck44/vblo=4,679.99 2006.285.13:04:06.64#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.13:04:06.64#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.13:04:06.64#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:06.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:04:06.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:04:06.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:04:06.64#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:04:06.64#ibcon#first serial, iclass 35, count 0 2006.285.13:04:06.64#ibcon#enter sib2, iclass 35, count 0 2006.285.13:04:06.64#ibcon#flushed, iclass 35, count 0 2006.285.13:04:06.64#ibcon#about to write, iclass 35, count 0 2006.285.13:04:06.64#ibcon#wrote, iclass 35, count 0 2006.285.13:04:06.64#ibcon#about to read 3, iclass 35, count 0 2006.285.13:04:06.66#ibcon#read 3, iclass 35, count 0 2006.285.13:04:06.73#ibcon#about to read 4, iclass 35, count 0 2006.285.13:04:06.73#ibcon#read 4, iclass 35, count 0 2006.285.13:04:06.73#ibcon#about to read 5, iclass 35, count 0 2006.285.13:04:06.73#ibcon#read 5, iclass 35, count 0 2006.285.13:04:06.73#ibcon#about to read 6, iclass 35, count 0 2006.285.13:04:06.73#ibcon#read 6, iclass 35, count 0 2006.285.13:04:06.73#ibcon#end of sib2, iclass 35, count 0 2006.285.13:04:06.73#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:04:06.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:04:06.73#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:04:06.73#ibcon#*before write, iclass 35, count 0 2006.285.13:04:06.73#ibcon#enter sib2, iclass 35, count 0 2006.285.13:04:06.73#ibcon#flushed, iclass 35, count 0 2006.285.13:04:06.73#ibcon#about to write, iclass 35, count 0 2006.285.13:04:06.73#ibcon#wrote, iclass 35, count 0 2006.285.13:04:06.73#ibcon#about to read 3, iclass 35, count 0 2006.285.13:04:06.77#ibcon#read 3, iclass 35, count 0 2006.285.13:04:06.77#ibcon#about to read 4, iclass 35, count 0 2006.285.13:04:06.77#ibcon#read 4, iclass 35, count 0 2006.285.13:04:06.77#ibcon#about to read 5, iclass 35, count 0 2006.285.13:04:06.77#ibcon#read 5, iclass 35, count 0 2006.285.13:04:06.77#ibcon#about to read 6, iclass 35, count 0 2006.285.13:04:06.77#ibcon#read 6, iclass 35, count 0 2006.285.13:04:06.77#ibcon#end of sib2, iclass 35, count 0 2006.285.13:04:06.77#ibcon#*after write, iclass 35, count 0 2006.285.13:04:06.77#ibcon#*before return 0, iclass 35, count 0 2006.285.13:04:06.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:04:06.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:04:06.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:04:06.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:04:06.77$vck44/vb=4,5 2006.285.13:04:06.77#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.13:04:06.77#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.13:04:06.77#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:06.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:04:06.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:04:06.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:04:06.77#ibcon#enter wrdev, iclass 37, count 2 2006.285.13:04:06.77#ibcon#first serial, iclass 37, count 2 2006.285.13:04:06.77#ibcon#enter sib2, iclass 37, count 2 2006.285.13:04:06.77#ibcon#flushed, iclass 37, count 2 2006.285.13:04:06.77#ibcon#about to write, iclass 37, count 2 2006.285.13:04:06.77#ibcon#wrote, iclass 37, count 2 2006.285.13:04:06.77#ibcon#about to read 3, iclass 37, count 2 2006.285.13:04:06.79#ibcon#read 3, iclass 37, count 2 2006.285.13:04:06.79#ibcon#about to read 4, iclass 37, count 2 2006.285.13:04:06.79#ibcon#read 4, iclass 37, count 2 2006.285.13:04:06.79#ibcon#about to read 5, iclass 37, count 2 2006.285.13:04:06.79#ibcon#read 5, iclass 37, count 2 2006.285.13:04:06.79#ibcon#about to read 6, iclass 37, count 2 2006.285.13:04:06.79#ibcon#read 6, iclass 37, count 2 2006.285.13:04:06.79#ibcon#end of sib2, iclass 37, count 2 2006.285.13:04:06.79#ibcon#*mode == 0, iclass 37, count 2 2006.285.13:04:06.79#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.13:04:06.79#ibcon#[27=AT04-05\r\n] 2006.285.13:04:06.79#ibcon#*before write, iclass 37, count 2 2006.285.13:04:06.79#ibcon#enter sib2, iclass 37, count 2 2006.285.13:04:06.79#ibcon#flushed, iclass 37, count 2 2006.285.13:04:06.79#ibcon#about to write, iclass 37, count 2 2006.285.13:04:06.79#ibcon#wrote, iclass 37, count 2 2006.285.13:04:06.79#ibcon#about to read 3, iclass 37, count 2 2006.285.13:04:06.82#ibcon#read 3, iclass 37, count 2 2006.285.13:04:06.82#ibcon#about to read 4, iclass 37, count 2 2006.285.13:04:06.82#ibcon#read 4, iclass 37, count 2 2006.285.13:04:06.82#ibcon#about to read 5, iclass 37, count 2 2006.285.13:04:06.82#ibcon#read 5, iclass 37, count 2 2006.285.13:04:06.82#ibcon#about to read 6, iclass 37, count 2 2006.285.13:04:06.82#ibcon#read 6, iclass 37, count 2 2006.285.13:04:06.82#ibcon#end of sib2, iclass 37, count 2 2006.285.13:04:06.82#ibcon#*after write, iclass 37, count 2 2006.285.13:04:06.82#ibcon#*before return 0, iclass 37, count 2 2006.285.13:04:06.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:04:06.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:04:06.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.13:04:06.82#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:06.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:04:06.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:04:06.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:04:06.94#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:04:06.94#ibcon#first serial, iclass 37, count 0 2006.285.13:04:06.94#ibcon#enter sib2, iclass 37, count 0 2006.285.13:04:06.94#ibcon#flushed, iclass 37, count 0 2006.285.13:04:06.94#ibcon#about to write, iclass 37, count 0 2006.285.13:04:06.94#ibcon#wrote, iclass 37, count 0 2006.285.13:04:06.94#ibcon#about to read 3, iclass 37, count 0 2006.285.13:04:06.96#ibcon#read 3, iclass 37, count 0 2006.285.13:04:06.96#ibcon#about to read 4, iclass 37, count 0 2006.285.13:04:06.96#ibcon#read 4, iclass 37, count 0 2006.285.13:04:06.96#ibcon#about to read 5, iclass 37, count 0 2006.285.13:04:06.96#ibcon#read 5, iclass 37, count 0 2006.285.13:04:06.96#ibcon#about to read 6, iclass 37, count 0 2006.285.13:04:06.96#ibcon#read 6, iclass 37, count 0 2006.285.13:04:06.96#ibcon#end of sib2, iclass 37, count 0 2006.285.13:04:06.96#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:04:06.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:04:06.96#ibcon#[27=USB\r\n] 2006.285.13:04:06.96#ibcon#*before write, iclass 37, count 0 2006.285.13:04:06.96#ibcon#enter sib2, iclass 37, count 0 2006.285.13:04:06.96#ibcon#flushed, iclass 37, count 0 2006.285.13:04:06.96#ibcon#about to write, iclass 37, count 0 2006.285.13:04:06.96#ibcon#wrote, iclass 37, count 0 2006.285.13:04:06.96#ibcon#about to read 3, iclass 37, count 0 2006.285.13:04:06.99#ibcon#read 3, iclass 37, count 0 2006.285.13:04:06.99#ibcon#about to read 4, iclass 37, count 0 2006.285.13:04:06.99#ibcon#read 4, iclass 37, count 0 2006.285.13:04:06.99#ibcon#about to read 5, iclass 37, count 0 2006.285.13:04:06.99#ibcon#read 5, iclass 37, count 0 2006.285.13:04:06.99#ibcon#about to read 6, iclass 37, count 0 2006.285.13:04:06.99#ibcon#read 6, iclass 37, count 0 2006.285.13:04:06.99#ibcon#end of sib2, iclass 37, count 0 2006.285.13:04:06.99#ibcon#*after write, iclass 37, count 0 2006.285.13:04:06.99#ibcon#*before return 0, iclass 37, count 0 2006.285.13:04:06.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:04:06.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:04:06.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:04:06.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:04:06.99$vck44/vblo=5,709.99 2006.285.13:04:06.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.13:04:06.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.13:04:06.99#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:06.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:04:06.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:04:06.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:04:06.99#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:04:06.99#ibcon#first serial, iclass 39, count 0 2006.285.13:04:06.99#ibcon#enter sib2, iclass 39, count 0 2006.285.13:04:06.99#ibcon#flushed, iclass 39, count 0 2006.285.13:04:06.99#ibcon#about to write, iclass 39, count 0 2006.285.13:04:06.99#ibcon#wrote, iclass 39, count 0 2006.285.13:04:06.99#ibcon#about to read 3, iclass 39, count 0 2006.285.13:04:07.01#ibcon#read 3, iclass 39, count 0 2006.285.13:04:07.01#ibcon#about to read 4, iclass 39, count 0 2006.285.13:04:07.01#ibcon#read 4, iclass 39, count 0 2006.285.13:04:07.01#ibcon#about to read 5, iclass 39, count 0 2006.285.13:04:07.01#ibcon#read 5, iclass 39, count 0 2006.285.13:04:07.01#ibcon#about to read 6, iclass 39, count 0 2006.285.13:04:07.01#ibcon#read 6, iclass 39, count 0 2006.285.13:04:07.01#ibcon#end of sib2, iclass 39, count 0 2006.285.13:04:07.01#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:04:07.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:04:07.01#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:04:07.01#ibcon#*before write, iclass 39, count 0 2006.285.13:04:07.01#ibcon#enter sib2, iclass 39, count 0 2006.285.13:04:07.01#ibcon#flushed, iclass 39, count 0 2006.285.13:04:07.01#ibcon#about to write, iclass 39, count 0 2006.285.13:04:07.01#ibcon#wrote, iclass 39, count 0 2006.285.13:04:07.01#ibcon#about to read 3, iclass 39, count 0 2006.285.13:04:07.05#ibcon#read 3, iclass 39, count 0 2006.285.13:04:07.05#ibcon#about to read 4, iclass 39, count 0 2006.285.13:04:07.05#ibcon#read 4, iclass 39, count 0 2006.285.13:04:07.05#ibcon#about to read 5, iclass 39, count 0 2006.285.13:04:07.05#ibcon#read 5, iclass 39, count 0 2006.285.13:04:07.05#ibcon#about to read 6, iclass 39, count 0 2006.285.13:04:07.05#ibcon#read 6, iclass 39, count 0 2006.285.13:04:07.05#ibcon#end of sib2, iclass 39, count 0 2006.285.13:04:07.05#ibcon#*after write, iclass 39, count 0 2006.285.13:04:07.05#ibcon#*before return 0, iclass 39, count 0 2006.285.13:04:07.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:04:07.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:04:07.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:04:07.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:04:07.05$vck44/vb=5,4 2006.285.13:04:07.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.13:04:07.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.13:04:07.05#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:07.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:04:07.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:04:07.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:04:07.11#ibcon#enter wrdev, iclass 3, count 2 2006.285.13:04:07.11#ibcon#first serial, iclass 3, count 2 2006.285.13:04:07.11#ibcon#enter sib2, iclass 3, count 2 2006.285.13:04:07.11#ibcon#flushed, iclass 3, count 2 2006.285.13:04:07.11#ibcon#about to write, iclass 3, count 2 2006.285.13:04:07.11#ibcon#wrote, iclass 3, count 2 2006.285.13:04:07.11#ibcon#about to read 3, iclass 3, count 2 2006.285.13:04:07.13#ibcon#read 3, iclass 3, count 2 2006.285.13:04:07.13#ibcon#about to read 4, iclass 3, count 2 2006.285.13:04:07.13#ibcon#read 4, iclass 3, count 2 2006.285.13:04:07.13#ibcon#about to read 5, iclass 3, count 2 2006.285.13:04:07.13#ibcon#read 5, iclass 3, count 2 2006.285.13:04:07.13#ibcon#about to read 6, iclass 3, count 2 2006.285.13:04:07.13#ibcon#read 6, iclass 3, count 2 2006.285.13:04:07.13#ibcon#end of sib2, iclass 3, count 2 2006.285.13:04:07.13#ibcon#*mode == 0, iclass 3, count 2 2006.285.13:04:07.13#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.13:04:07.13#ibcon#[27=AT05-04\r\n] 2006.285.13:04:07.13#ibcon#*before write, iclass 3, count 2 2006.285.13:04:07.13#ibcon#enter sib2, iclass 3, count 2 2006.285.13:04:07.13#ibcon#flushed, iclass 3, count 2 2006.285.13:04:07.13#ibcon#about to write, iclass 3, count 2 2006.285.13:04:07.13#ibcon#wrote, iclass 3, count 2 2006.285.13:04:07.13#ibcon#about to read 3, iclass 3, count 2 2006.285.13:04:07.16#ibcon#read 3, iclass 3, count 2 2006.285.13:04:07.16#ibcon#about to read 4, iclass 3, count 2 2006.285.13:04:07.16#ibcon#read 4, iclass 3, count 2 2006.285.13:04:07.16#ibcon#about to read 5, iclass 3, count 2 2006.285.13:04:07.16#ibcon#read 5, iclass 3, count 2 2006.285.13:04:07.16#ibcon#about to read 6, iclass 3, count 2 2006.285.13:04:07.16#ibcon#read 6, iclass 3, count 2 2006.285.13:04:07.16#ibcon#end of sib2, iclass 3, count 2 2006.285.13:04:07.16#ibcon#*after write, iclass 3, count 2 2006.285.13:04:07.16#ibcon#*before return 0, iclass 3, count 2 2006.285.13:04:07.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:04:07.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:04:07.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.13:04:07.16#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:07.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:04:07.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:04:07.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:04:07.28#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:04:07.28#ibcon#first serial, iclass 3, count 0 2006.285.13:04:07.28#ibcon#enter sib2, iclass 3, count 0 2006.285.13:04:07.28#ibcon#flushed, iclass 3, count 0 2006.285.13:04:07.28#ibcon#about to write, iclass 3, count 0 2006.285.13:04:07.28#ibcon#wrote, iclass 3, count 0 2006.285.13:04:07.28#ibcon#about to read 3, iclass 3, count 0 2006.285.13:04:07.30#ibcon#read 3, iclass 3, count 0 2006.285.13:04:07.30#ibcon#about to read 4, iclass 3, count 0 2006.285.13:04:07.30#ibcon#read 4, iclass 3, count 0 2006.285.13:04:07.30#ibcon#about to read 5, iclass 3, count 0 2006.285.13:04:07.30#ibcon#read 5, iclass 3, count 0 2006.285.13:04:07.30#ibcon#about to read 6, iclass 3, count 0 2006.285.13:04:07.30#ibcon#read 6, iclass 3, count 0 2006.285.13:04:07.30#ibcon#end of sib2, iclass 3, count 0 2006.285.13:04:07.30#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:04:07.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:04:07.30#ibcon#[27=USB\r\n] 2006.285.13:04:07.30#ibcon#*before write, iclass 3, count 0 2006.285.13:04:07.30#ibcon#enter sib2, iclass 3, count 0 2006.285.13:04:07.30#ibcon#flushed, iclass 3, count 0 2006.285.13:04:07.30#ibcon#about to write, iclass 3, count 0 2006.285.13:04:07.30#ibcon#wrote, iclass 3, count 0 2006.285.13:04:07.30#ibcon#about to read 3, iclass 3, count 0 2006.285.13:04:07.33#ibcon#read 3, iclass 3, count 0 2006.285.13:04:07.33#ibcon#about to read 4, iclass 3, count 0 2006.285.13:04:07.33#ibcon#read 4, iclass 3, count 0 2006.285.13:04:07.33#ibcon#about to read 5, iclass 3, count 0 2006.285.13:04:07.33#ibcon#read 5, iclass 3, count 0 2006.285.13:04:07.33#ibcon#about to read 6, iclass 3, count 0 2006.285.13:04:07.33#ibcon#read 6, iclass 3, count 0 2006.285.13:04:07.33#ibcon#end of sib2, iclass 3, count 0 2006.285.13:04:07.33#ibcon#*after write, iclass 3, count 0 2006.285.13:04:07.33#ibcon#*before return 0, iclass 3, count 0 2006.285.13:04:07.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:04:07.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:04:07.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:04:07.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:04:07.33$vck44/vblo=6,719.99 2006.285.13:04:07.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.13:04:07.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.13:04:07.33#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:07.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:04:07.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:04:07.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:04:07.33#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:04:07.33#ibcon#first serial, iclass 5, count 0 2006.285.13:04:07.33#ibcon#enter sib2, iclass 5, count 0 2006.285.13:04:07.33#ibcon#flushed, iclass 5, count 0 2006.285.13:04:07.33#ibcon#about to write, iclass 5, count 0 2006.285.13:04:07.33#ibcon#wrote, iclass 5, count 0 2006.285.13:04:07.33#ibcon#about to read 3, iclass 5, count 0 2006.285.13:04:07.35#ibcon#read 3, iclass 5, count 0 2006.285.13:04:07.35#ibcon#about to read 4, iclass 5, count 0 2006.285.13:04:07.35#ibcon#read 4, iclass 5, count 0 2006.285.13:04:07.35#ibcon#about to read 5, iclass 5, count 0 2006.285.13:04:07.35#ibcon#read 5, iclass 5, count 0 2006.285.13:04:07.35#ibcon#about to read 6, iclass 5, count 0 2006.285.13:04:07.35#ibcon#read 6, iclass 5, count 0 2006.285.13:04:07.35#ibcon#end of sib2, iclass 5, count 0 2006.285.13:04:07.35#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:04:07.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:04:07.35#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:04:07.35#ibcon#*before write, iclass 5, count 0 2006.285.13:04:07.35#ibcon#enter sib2, iclass 5, count 0 2006.285.13:04:07.35#ibcon#flushed, iclass 5, count 0 2006.285.13:04:07.35#ibcon#about to write, iclass 5, count 0 2006.285.13:04:07.35#ibcon#wrote, iclass 5, count 0 2006.285.13:04:07.35#ibcon#about to read 3, iclass 5, count 0 2006.285.13:04:07.39#ibcon#read 3, iclass 5, count 0 2006.285.13:04:07.39#ibcon#about to read 4, iclass 5, count 0 2006.285.13:04:07.39#ibcon#read 4, iclass 5, count 0 2006.285.13:04:07.39#ibcon#about to read 5, iclass 5, count 0 2006.285.13:04:07.39#ibcon#read 5, iclass 5, count 0 2006.285.13:04:07.39#ibcon#about to read 6, iclass 5, count 0 2006.285.13:04:07.39#ibcon#read 6, iclass 5, count 0 2006.285.13:04:07.39#ibcon#end of sib2, iclass 5, count 0 2006.285.13:04:07.39#ibcon#*after write, iclass 5, count 0 2006.285.13:04:07.39#ibcon#*before return 0, iclass 5, count 0 2006.285.13:04:07.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:04:07.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:04:07.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:04:07.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:04:07.39$vck44/vb=6,3 2006.285.13:04:07.39#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.13:04:07.39#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.13:04:07.39#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:07.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:04:07.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:04:07.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:04:07.45#ibcon#enter wrdev, iclass 7, count 2 2006.285.13:04:07.45#ibcon#first serial, iclass 7, count 2 2006.285.13:04:07.45#ibcon#enter sib2, iclass 7, count 2 2006.285.13:04:07.45#ibcon#flushed, iclass 7, count 2 2006.285.13:04:07.45#ibcon#about to write, iclass 7, count 2 2006.285.13:04:07.45#ibcon#wrote, iclass 7, count 2 2006.285.13:04:07.45#ibcon#about to read 3, iclass 7, count 2 2006.285.13:04:07.47#ibcon#read 3, iclass 7, count 2 2006.285.13:04:07.47#ibcon#about to read 4, iclass 7, count 2 2006.285.13:04:07.47#ibcon#read 4, iclass 7, count 2 2006.285.13:04:07.47#ibcon#about to read 5, iclass 7, count 2 2006.285.13:04:07.47#ibcon#read 5, iclass 7, count 2 2006.285.13:04:07.47#ibcon#about to read 6, iclass 7, count 2 2006.285.13:04:07.47#ibcon#read 6, iclass 7, count 2 2006.285.13:04:07.47#ibcon#end of sib2, iclass 7, count 2 2006.285.13:04:07.47#ibcon#*mode == 0, iclass 7, count 2 2006.285.13:04:07.47#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.13:04:07.47#ibcon#[27=AT06-03\r\n] 2006.285.13:04:07.47#ibcon#*before write, iclass 7, count 2 2006.285.13:04:07.47#ibcon#enter sib2, iclass 7, count 2 2006.285.13:04:07.47#ibcon#flushed, iclass 7, count 2 2006.285.13:04:07.47#ibcon#about to write, iclass 7, count 2 2006.285.13:04:07.47#ibcon#wrote, iclass 7, count 2 2006.285.13:04:07.47#ibcon#about to read 3, iclass 7, count 2 2006.285.13:04:07.50#ibcon#read 3, iclass 7, count 2 2006.285.13:04:07.50#ibcon#about to read 4, iclass 7, count 2 2006.285.13:04:07.50#ibcon#read 4, iclass 7, count 2 2006.285.13:04:07.50#ibcon#about to read 5, iclass 7, count 2 2006.285.13:04:07.50#ibcon#read 5, iclass 7, count 2 2006.285.13:04:07.50#ibcon#about to read 6, iclass 7, count 2 2006.285.13:04:07.50#ibcon#read 6, iclass 7, count 2 2006.285.13:04:07.50#ibcon#end of sib2, iclass 7, count 2 2006.285.13:04:07.50#ibcon#*after write, iclass 7, count 2 2006.285.13:04:07.50#ibcon#*before return 0, iclass 7, count 2 2006.285.13:04:07.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:04:07.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:04:07.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.13:04:07.50#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:07.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:04:07.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:04:07.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:04:07.62#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:04:07.62#ibcon#first serial, iclass 7, count 0 2006.285.13:04:07.62#ibcon#enter sib2, iclass 7, count 0 2006.285.13:04:07.62#ibcon#flushed, iclass 7, count 0 2006.285.13:04:07.62#ibcon#about to write, iclass 7, count 0 2006.285.13:04:07.62#ibcon#wrote, iclass 7, count 0 2006.285.13:04:07.62#ibcon#about to read 3, iclass 7, count 0 2006.285.13:04:07.64#ibcon#read 3, iclass 7, count 0 2006.285.13:04:07.64#ibcon#about to read 4, iclass 7, count 0 2006.285.13:04:07.64#ibcon#read 4, iclass 7, count 0 2006.285.13:04:07.64#ibcon#about to read 5, iclass 7, count 0 2006.285.13:04:07.64#ibcon#read 5, iclass 7, count 0 2006.285.13:04:07.64#ibcon#about to read 6, iclass 7, count 0 2006.285.13:04:07.64#ibcon#read 6, iclass 7, count 0 2006.285.13:04:07.64#ibcon#end of sib2, iclass 7, count 0 2006.285.13:04:07.64#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:04:07.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:04:07.64#ibcon#[27=USB\r\n] 2006.285.13:04:07.64#ibcon#*before write, iclass 7, count 0 2006.285.13:04:07.64#ibcon#enter sib2, iclass 7, count 0 2006.285.13:04:07.64#ibcon#flushed, iclass 7, count 0 2006.285.13:04:07.64#ibcon#about to write, iclass 7, count 0 2006.285.13:04:07.64#ibcon#wrote, iclass 7, count 0 2006.285.13:04:07.64#ibcon#about to read 3, iclass 7, count 0 2006.285.13:04:07.67#ibcon#read 3, iclass 7, count 0 2006.285.13:04:07.67#ibcon#about to read 4, iclass 7, count 0 2006.285.13:04:07.67#ibcon#read 4, iclass 7, count 0 2006.285.13:04:07.67#ibcon#about to read 5, iclass 7, count 0 2006.285.13:04:07.67#ibcon#read 5, iclass 7, count 0 2006.285.13:04:07.67#ibcon#about to read 6, iclass 7, count 0 2006.285.13:04:07.67#ibcon#read 6, iclass 7, count 0 2006.285.13:04:07.67#ibcon#end of sib2, iclass 7, count 0 2006.285.13:04:07.67#ibcon#*after write, iclass 7, count 0 2006.285.13:04:07.67#ibcon#*before return 0, iclass 7, count 0 2006.285.13:04:07.67#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:04:07.67#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:04:07.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:04:07.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:04:07.67$vck44/vblo=7,734.99 2006.285.13:04:07.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.13:04:07.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.13:04:07.67#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:07.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:04:07.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:04:07.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:04:07.67#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:04:07.67#ibcon#first serial, iclass 11, count 0 2006.285.13:04:07.67#ibcon#enter sib2, iclass 11, count 0 2006.285.13:04:07.67#ibcon#flushed, iclass 11, count 0 2006.285.13:04:07.67#ibcon#about to write, iclass 11, count 0 2006.285.13:04:07.67#ibcon#wrote, iclass 11, count 0 2006.285.13:04:07.67#ibcon#about to read 3, iclass 11, count 0 2006.285.13:04:07.69#ibcon#read 3, iclass 11, count 0 2006.285.13:04:07.77#ibcon#about to read 4, iclass 11, count 0 2006.285.13:04:07.77#ibcon#read 4, iclass 11, count 0 2006.285.13:04:07.77#ibcon#about to read 5, iclass 11, count 0 2006.285.13:04:07.77#ibcon#read 5, iclass 11, count 0 2006.285.13:04:07.77#ibcon#about to read 6, iclass 11, count 0 2006.285.13:04:07.77#ibcon#read 6, iclass 11, count 0 2006.285.13:04:07.77#ibcon#end of sib2, iclass 11, count 0 2006.285.13:04:07.77#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:04:07.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:04:07.77#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:04:07.77#ibcon#*before write, iclass 11, count 0 2006.285.13:04:07.77#ibcon#enter sib2, iclass 11, count 0 2006.285.13:04:07.77#ibcon#flushed, iclass 11, count 0 2006.285.13:04:07.77#ibcon#about to write, iclass 11, count 0 2006.285.13:04:07.77#ibcon#wrote, iclass 11, count 0 2006.285.13:04:07.77#ibcon#about to read 3, iclass 11, count 0 2006.285.13:04:07.80#ibcon#read 3, iclass 11, count 0 2006.285.13:04:07.80#ibcon#about to read 4, iclass 11, count 0 2006.285.13:04:07.80#ibcon#read 4, iclass 11, count 0 2006.285.13:04:07.80#ibcon#about to read 5, iclass 11, count 0 2006.285.13:04:07.80#ibcon#read 5, iclass 11, count 0 2006.285.13:04:07.80#ibcon#about to read 6, iclass 11, count 0 2006.285.13:04:07.80#ibcon#read 6, iclass 11, count 0 2006.285.13:04:07.80#ibcon#end of sib2, iclass 11, count 0 2006.285.13:04:07.80#ibcon#*after write, iclass 11, count 0 2006.285.13:04:07.80#ibcon#*before return 0, iclass 11, count 0 2006.285.13:04:07.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:04:07.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:04:07.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:04:07.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:04:07.80$vck44/vb=7,4 2006.285.13:04:07.80#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.13:04:07.80#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.13:04:07.80#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:07.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:04:07.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:04:07.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:04:07.80#ibcon#enter wrdev, iclass 13, count 2 2006.285.13:04:07.80#ibcon#first serial, iclass 13, count 2 2006.285.13:04:07.80#ibcon#enter sib2, iclass 13, count 2 2006.285.13:04:07.80#ibcon#flushed, iclass 13, count 2 2006.285.13:04:07.80#ibcon#about to write, iclass 13, count 2 2006.285.13:04:07.80#ibcon#wrote, iclass 13, count 2 2006.285.13:04:07.80#ibcon#about to read 3, iclass 13, count 2 2006.285.13:04:07.82#ibcon#read 3, iclass 13, count 2 2006.285.13:04:07.82#ibcon#about to read 4, iclass 13, count 2 2006.285.13:04:07.82#ibcon#read 4, iclass 13, count 2 2006.285.13:04:07.82#ibcon#about to read 5, iclass 13, count 2 2006.285.13:04:07.82#ibcon#read 5, iclass 13, count 2 2006.285.13:04:07.82#ibcon#about to read 6, iclass 13, count 2 2006.285.13:04:07.82#ibcon#read 6, iclass 13, count 2 2006.285.13:04:07.82#ibcon#end of sib2, iclass 13, count 2 2006.285.13:04:07.82#ibcon#*mode == 0, iclass 13, count 2 2006.285.13:04:07.82#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.13:04:07.82#ibcon#[27=AT07-04\r\n] 2006.285.13:04:07.82#ibcon#*before write, iclass 13, count 2 2006.285.13:04:07.82#ibcon#enter sib2, iclass 13, count 2 2006.285.13:04:07.82#ibcon#flushed, iclass 13, count 2 2006.285.13:04:07.82#ibcon#about to write, iclass 13, count 2 2006.285.13:04:07.82#ibcon#wrote, iclass 13, count 2 2006.285.13:04:07.82#ibcon#about to read 3, iclass 13, count 2 2006.285.13:04:07.85#ibcon#read 3, iclass 13, count 2 2006.285.13:04:07.85#ibcon#about to read 4, iclass 13, count 2 2006.285.13:04:07.85#ibcon#read 4, iclass 13, count 2 2006.285.13:04:07.85#ibcon#about to read 5, iclass 13, count 2 2006.285.13:04:07.85#ibcon#read 5, iclass 13, count 2 2006.285.13:04:07.85#ibcon#about to read 6, iclass 13, count 2 2006.285.13:04:07.85#ibcon#read 6, iclass 13, count 2 2006.285.13:04:07.85#ibcon#end of sib2, iclass 13, count 2 2006.285.13:04:07.85#ibcon#*after write, iclass 13, count 2 2006.285.13:04:07.85#ibcon#*before return 0, iclass 13, count 2 2006.285.13:04:07.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:04:07.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:04:07.85#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.13:04:07.85#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:07.85#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:04:07.97#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:04:07.97#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:04:07.97#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:04:07.97#ibcon#first serial, iclass 13, count 0 2006.285.13:04:07.97#ibcon#enter sib2, iclass 13, count 0 2006.285.13:04:07.97#ibcon#flushed, iclass 13, count 0 2006.285.13:04:07.97#ibcon#about to write, iclass 13, count 0 2006.285.13:04:07.97#ibcon#wrote, iclass 13, count 0 2006.285.13:04:07.97#ibcon#about to read 3, iclass 13, count 0 2006.285.13:04:07.99#ibcon#read 3, iclass 13, count 0 2006.285.13:04:07.99#ibcon#about to read 4, iclass 13, count 0 2006.285.13:04:07.99#ibcon#read 4, iclass 13, count 0 2006.285.13:04:07.99#ibcon#about to read 5, iclass 13, count 0 2006.285.13:04:07.99#ibcon#read 5, iclass 13, count 0 2006.285.13:04:07.99#ibcon#about to read 6, iclass 13, count 0 2006.285.13:04:07.99#ibcon#read 6, iclass 13, count 0 2006.285.13:04:07.99#ibcon#end of sib2, iclass 13, count 0 2006.285.13:04:07.99#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:04:07.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:04:07.99#ibcon#[27=USB\r\n] 2006.285.13:04:07.99#ibcon#*before write, iclass 13, count 0 2006.285.13:04:07.99#ibcon#enter sib2, iclass 13, count 0 2006.285.13:04:07.99#ibcon#flushed, iclass 13, count 0 2006.285.13:04:07.99#ibcon#about to write, iclass 13, count 0 2006.285.13:04:07.99#ibcon#wrote, iclass 13, count 0 2006.285.13:04:07.99#ibcon#about to read 3, iclass 13, count 0 2006.285.13:04:08.02#ibcon#read 3, iclass 13, count 0 2006.285.13:04:08.02#ibcon#about to read 4, iclass 13, count 0 2006.285.13:04:08.02#ibcon#read 4, iclass 13, count 0 2006.285.13:04:08.02#ibcon#about to read 5, iclass 13, count 0 2006.285.13:04:08.02#ibcon#read 5, iclass 13, count 0 2006.285.13:04:08.02#ibcon#about to read 6, iclass 13, count 0 2006.285.13:04:08.02#ibcon#read 6, iclass 13, count 0 2006.285.13:04:08.02#ibcon#end of sib2, iclass 13, count 0 2006.285.13:04:08.02#ibcon#*after write, iclass 13, count 0 2006.285.13:04:08.02#ibcon#*before return 0, iclass 13, count 0 2006.285.13:04:08.02#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:04:08.02#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:04:08.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:04:08.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:04:08.02$vck44/vblo=8,744.99 2006.285.13:04:08.02#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.13:04:08.02#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.13:04:08.02#ibcon#ireg 17 cls_cnt 0 2006.285.13:04:08.02#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:04:08.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:04:08.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:04:08.02#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:04:08.02#ibcon#first serial, iclass 15, count 0 2006.285.13:04:08.02#ibcon#enter sib2, iclass 15, count 0 2006.285.13:04:08.02#ibcon#flushed, iclass 15, count 0 2006.285.13:04:08.02#ibcon#about to write, iclass 15, count 0 2006.285.13:04:08.02#ibcon#wrote, iclass 15, count 0 2006.285.13:04:08.02#ibcon#about to read 3, iclass 15, count 0 2006.285.13:04:08.04#ibcon#read 3, iclass 15, count 0 2006.285.13:04:08.04#ibcon#about to read 4, iclass 15, count 0 2006.285.13:04:08.04#ibcon#read 4, iclass 15, count 0 2006.285.13:04:08.04#ibcon#about to read 5, iclass 15, count 0 2006.285.13:04:08.04#ibcon#read 5, iclass 15, count 0 2006.285.13:04:08.04#ibcon#about to read 6, iclass 15, count 0 2006.285.13:04:08.04#ibcon#read 6, iclass 15, count 0 2006.285.13:04:08.04#ibcon#end of sib2, iclass 15, count 0 2006.285.13:04:08.04#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:04:08.04#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:04:08.04#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:04:08.04#ibcon#*before write, iclass 15, count 0 2006.285.13:04:08.04#ibcon#enter sib2, iclass 15, count 0 2006.285.13:04:08.04#ibcon#flushed, iclass 15, count 0 2006.285.13:04:08.04#ibcon#about to write, iclass 15, count 0 2006.285.13:04:08.04#ibcon#wrote, iclass 15, count 0 2006.285.13:04:08.04#ibcon#about to read 3, iclass 15, count 0 2006.285.13:04:08.08#ibcon#read 3, iclass 15, count 0 2006.285.13:04:08.08#ibcon#about to read 4, iclass 15, count 0 2006.285.13:04:08.08#ibcon#read 4, iclass 15, count 0 2006.285.13:04:08.08#ibcon#about to read 5, iclass 15, count 0 2006.285.13:04:08.08#ibcon#read 5, iclass 15, count 0 2006.285.13:04:08.08#ibcon#about to read 6, iclass 15, count 0 2006.285.13:04:08.08#ibcon#read 6, iclass 15, count 0 2006.285.13:04:08.08#ibcon#end of sib2, iclass 15, count 0 2006.285.13:04:08.08#ibcon#*after write, iclass 15, count 0 2006.285.13:04:08.08#ibcon#*before return 0, iclass 15, count 0 2006.285.13:04:08.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:04:08.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:04:08.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:04:08.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:04:08.08$vck44/vb=8,4 2006.285.13:04:08.08#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.13:04:08.08#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.13:04:08.08#ibcon#ireg 11 cls_cnt 2 2006.285.13:04:08.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:04:08.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:04:08.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:04:08.14#ibcon#enter wrdev, iclass 17, count 2 2006.285.13:04:08.14#ibcon#first serial, iclass 17, count 2 2006.285.13:04:08.14#ibcon#enter sib2, iclass 17, count 2 2006.285.13:04:08.14#ibcon#flushed, iclass 17, count 2 2006.285.13:04:08.14#ibcon#about to write, iclass 17, count 2 2006.285.13:04:08.14#ibcon#wrote, iclass 17, count 2 2006.285.13:04:08.14#ibcon#about to read 3, iclass 17, count 2 2006.285.13:04:08.16#ibcon#read 3, iclass 17, count 2 2006.285.13:04:08.16#ibcon#about to read 4, iclass 17, count 2 2006.285.13:04:08.16#ibcon#read 4, iclass 17, count 2 2006.285.13:04:08.16#ibcon#about to read 5, iclass 17, count 2 2006.285.13:04:08.16#ibcon#read 5, iclass 17, count 2 2006.285.13:04:08.16#ibcon#about to read 6, iclass 17, count 2 2006.285.13:04:08.16#ibcon#read 6, iclass 17, count 2 2006.285.13:04:08.16#ibcon#end of sib2, iclass 17, count 2 2006.285.13:04:08.16#ibcon#*mode == 0, iclass 17, count 2 2006.285.13:04:08.16#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.13:04:08.16#ibcon#[27=AT08-04\r\n] 2006.285.13:04:08.16#ibcon#*before write, iclass 17, count 2 2006.285.13:04:08.16#ibcon#enter sib2, iclass 17, count 2 2006.285.13:04:08.16#ibcon#flushed, iclass 17, count 2 2006.285.13:04:08.16#ibcon#about to write, iclass 17, count 2 2006.285.13:04:08.16#ibcon#wrote, iclass 17, count 2 2006.285.13:04:08.16#ibcon#about to read 3, iclass 17, count 2 2006.285.13:04:08.19#ibcon#read 3, iclass 17, count 2 2006.285.13:04:08.19#ibcon#about to read 4, iclass 17, count 2 2006.285.13:04:08.19#ibcon#read 4, iclass 17, count 2 2006.285.13:04:08.19#ibcon#about to read 5, iclass 17, count 2 2006.285.13:04:08.19#ibcon#read 5, iclass 17, count 2 2006.285.13:04:08.19#ibcon#about to read 6, iclass 17, count 2 2006.285.13:04:08.19#ibcon#read 6, iclass 17, count 2 2006.285.13:04:08.19#ibcon#end of sib2, iclass 17, count 2 2006.285.13:04:08.19#ibcon#*after write, iclass 17, count 2 2006.285.13:04:08.19#ibcon#*before return 0, iclass 17, count 2 2006.285.13:04:08.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:04:08.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:04:08.19#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.13:04:08.19#ibcon#ireg 7 cls_cnt 0 2006.285.13:04:08.19#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:04:08.31#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:04:08.31#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:04:08.31#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:04:08.31#ibcon#first serial, iclass 17, count 0 2006.285.13:04:08.31#ibcon#enter sib2, iclass 17, count 0 2006.285.13:04:08.31#ibcon#flushed, iclass 17, count 0 2006.285.13:04:08.31#ibcon#about to write, iclass 17, count 0 2006.285.13:04:08.31#ibcon#wrote, iclass 17, count 0 2006.285.13:04:08.31#ibcon#about to read 3, iclass 17, count 0 2006.285.13:04:08.33#ibcon#read 3, iclass 17, count 0 2006.285.13:04:08.33#ibcon#about to read 4, iclass 17, count 0 2006.285.13:04:08.33#ibcon#read 4, iclass 17, count 0 2006.285.13:04:08.33#ibcon#about to read 5, iclass 17, count 0 2006.285.13:04:08.33#ibcon#read 5, iclass 17, count 0 2006.285.13:04:08.33#ibcon#about to read 6, iclass 17, count 0 2006.285.13:04:08.33#ibcon#read 6, iclass 17, count 0 2006.285.13:04:08.33#ibcon#end of sib2, iclass 17, count 0 2006.285.13:04:08.33#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:04:08.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:04:08.33#ibcon#[27=USB\r\n] 2006.285.13:04:08.33#ibcon#*before write, iclass 17, count 0 2006.285.13:04:08.33#ibcon#enter sib2, iclass 17, count 0 2006.285.13:04:08.33#ibcon#flushed, iclass 17, count 0 2006.285.13:04:08.33#ibcon#about to write, iclass 17, count 0 2006.285.13:04:08.33#ibcon#wrote, iclass 17, count 0 2006.285.13:04:08.33#ibcon#about to read 3, iclass 17, count 0 2006.285.13:04:08.36#ibcon#read 3, iclass 17, count 0 2006.285.13:04:08.36#ibcon#about to read 4, iclass 17, count 0 2006.285.13:04:08.36#ibcon#read 4, iclass 17, count 0 2006.285.13:04:08.36#ibcon#about to read 5, iclass 17, count 0 2006.285.13:04:08.36#ibcon#read 5, iclass 17, count 0 2006.285.13:04:08.36#ibcon#about to read 6, iclass 17, count 0 2006.285.13:04:08.36#ibcon#read 6, iclass 17, count 0 2006.285.13:04:08.36#ibcon#end of sib2, iclass 17, count 0 2006.285.13:04:08.36#ibcon#*after write, iclass 17, count 0 2006.285.13:04:08.36#ibcon#*before return 0, iclass 17, count 0 2006.285.13:04:08.36#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:04:08.36#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:04:08.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:04:08.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:04:08.36$vck44/vabw=wide 2006.285.13:04:08.36#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.13:04:08.36#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.13:04:08.36#ibcon#ireg 8 cls_cnt 0 2006.285.13:04:08.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:04:08.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:04:08.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:04:08.36#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:04:08.36#ibcon#first serial, iclass 19, count 0 2006.285.13:04:08.36#ibcon#enter sib2, iclass 19, count 0 2006.285.13:04:08.36#ibcon#flushed, iclass 19, count 0 2006.285.13:04:08.36#ibcon#about to write, iclass 19, count 0 2006.285.13:04:08.36#ibcon#wrote, iclass 19, count 0 2006.285.13:04:08.36#ibcon#about to read 3, iclass 19, count 0 2006.285.13:04:08.38#ibcon#read 3, iclass 19, count 0 2006.285.13:04:08.38#ibcon#about to read 4, iclass 19, count 0 2006.285.13:04:08.38#ibcon#read 4, iclass 19, count 0 2006.285.13:04:08.38#ibcon#about to read 5, iclass 19, count 0 2006.285.13:04:08.38#ibcon#read 5, iclass 19, count 0 2006.285.13:04:08.38#ibcon#about to read 6, iclass 19, count 0 2006.285.13:04:08.38#ibcon#read 6, iclass 19, count 0 2006.285.13:04:08.38#ibcon#end of sib2, iclass 19, count 0 2006.285.13:04:08.38#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:04:08.38#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:04:08.38#ibcon#[25=BW32\r\n] 2006.285.13:04:08.38#ibcon#*before write, iclass 19, count 0 2006.285.13:04:08.38#ibcon#enter sib2, iclass 19, count 0 2006.285.13:04:08.38#ibcon#flushed, iclass 19, count 0 2006.285.13:04:08.38#ibcon#about to write, iclass 19, count 0 2006.285.13:04:08.38#ibcon#wrote, iclass 19, count 0 2006.285.13:04:08.38#ibcon#about to read 3, iclass 19, count 0 2006.285.13:04:08.41#ibcon#read 3, iclass 19, count 0 2006.285.13:04:08.41#ibcon#about to read 4, iclass 19, count 0 2006.285.13:04:08.41#ibcon#read 4, iclass 19, count 0 2006.285.13:04:08.41#ibcon#about to read 5, iclass 19, count 0 2006.285.13:04:08.41#ibcon#read 5, iclass 19, count 0 2006.285.13:04:08.41#ibcon#about to read 6, iclass 19, count 0 2006.285.13:04:08.41#ibcon#read 6, iclass 19, count 0 2006.285.13:04:08.41#ibcon#end of sib2, iclass 19, count 0 2006.285.13:04:08.41#ibcon#*after write, iclass 19, count 0 2006.285.13:04:08.41#ibcon#*before return 0, iclass 19, count 0 2006.285.13:04:08.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:04:08.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:04:08.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:04:08.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:04:08.41$vck44/vbbw=wide 2006.285.13:04:08.41#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.13:04:08.41#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.13:04:08.41#ibcon#ireg 8 cls_cnt 0 2006.285.13:04:08.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:04:08.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:04:08.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:04:08.48#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:04:08.48#ibcon#first serial, iclass 21, count 0 2006.285.13:04:08.48#ibcon#enter sib2, iclass 21, count 0 2006.285.13:04:08.48#ibcon#flushed, iclass 21, count 0 2006.285.13:04:08.48#ibcon#about to write, iclass 21, count 0 2006.285.13:04:08.48#ibcon#wrote, iclass 21, count 0 2006.285.13:04:08.48#ibcon#about to read 3, iclass 21, count 0 2006.285.13:04:08.50#ibcon#read 3, iclass 21, count 0 2006.285.13:04:08.50#ibcon#about to read 4, iclass 21, count 0 2006.285.13:04:08.50#ibcon#read 4, iclass 21, count 0 2006.285.13:04:08.50#ibcon#about to read 5, iclass 21, count 0 2006.285.13:04:08.50#ibcon#read 5, iclass 21, count 0 2006.285.13:04:08.50#ibcon#about to read 6, iclass 21, count 0 2006.285.13:04:08.50#ibcon#read 6, iclass 21, count 0 2006.285.13:04:08.50#ibcon#end of sib2, iclass 21, count 0 2006.285.13:04:08.50#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:04:08.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:04:08.50#ibcon#[27=BW32\r\n] 2006.285.13:04:08.50#ibcon#*before write, iclass 21, count 0 2006.285.13:04:08.50#ibcon#enter sib2, iclass 21, count 0 2006.285.13:04:08.50#ibcon#flushed, iclass 21, count 0 2006.285.13:04:08.50#ibcon#about to write, iclass 21, count 0 2006.285.13:04:08.50#ibcon#wrote, iclass 21, count 0 2006.285.13:04:08.50#ibcon#about to read 3, iclass 21, count 0 2006.285.13:04:08.53#ibcon#read 3, iclass 21, count 0 2006.285.13:04:08.53#ibcon#about to read 4, iclass 21, count 0 2006.285.13:04:08.53#ibcon#read 4, iclass 21, count 0 2006.285.13:04:08.53#ibcon#about to read 5, iclass 21, count 0 2006.285.13:04:08.53#ibcon#read 5, iclass 21, count 0 2006.285.13:04:08.53#ibcon#about to read 6, iclass 21, count 0 2006.285.13:04:08.53#ibcon#read 6, iclass 21, count 0 2006.285.13:04:08.53#ibcon#end of sib2, iclass 21, count 0 2006.285.13:04:08.53#ibcon#*after write, iclass 21, count 0 2006.285.13:04:08.53#ibcon#*before return 0, iclass 21, count 0 2006.285.13:04:08.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:04:08.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:04:08.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:04:08.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:04:08.53$setupk4/ifdk4 2006.285.13:04:08.53$ifdk4/lo= 2006.285.13:04:08.53$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:04:08.54$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:04:08.54$ifdk4/patch= 2006.285.13:04:08.54$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:04:08.54$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:04:08.54$setupk4/!*+20s 2006.285.13:04:10.13#trakl#Source acquired 2006.285.13:04:11.13#flagr#flagr/antenna,acquired 2006.285.13:04:11.56#abcon#<5=/04 1.4 2.8 18.99 951015.5\r\n> 2006.285.13:04:11.58#abcon#{5=INTERFACE CLEAR} 2006.285.13:04:11.64#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:04:21.73#abcon#<5=/04 1.4 2.8 18.99 951015.5\r\n> 2006.285.13:04:21.75#abcon#{5=INTERFACE CLEAR} 2006.285.13:04:21.81#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:04:22.45$setupk4/"tpicd 2006.285.13:04:22.45$setupk4/echo=off 2006.285.13:04:22.45$setupk4/xlog=off 2006.285.13:04:22.45:!2006.285.13:08:27 2006.285.13:08:27.00:preob 2006.285.13:08:27.14/onsource/TRACKING 2006.285.13:08:27.14:!2006.285.13:08:37 2006.285.13:08:37.00:"tape 2006.285.13:08:37.00:"st=record 2006.285.13:08:37.00:data_valid=on 2006.285.13:08:37.00:midob 2006.285.13:08:38.14/onsource/TRACKING 2006.285.13:08:38.14/wx/19.00,1015.4,96 2006.285.13:08:38.30/cable/+6.4971E-03 2006.285.13:08:39.39/va/01,07,usb,yes,32,34 2006.285.13:08:39.39/va/02,06,usb,yes,32,32 2006.285.13:08:39.39/va/03,07,usb,yes,31,33 2006.285.13:08:39.39/va/04,06,usb,yes,33,34 2006.285.13:08:39.39/va/05,03,usb,yes,32,33 2006.285.13:08:39.39/va/06,04,usb,yes,29,29 2006.285.13:08:39.39/va/07,04,usb,yes,30,30 2006.285.13:08:39.39/va/08,03,usb,yes,30,37 2006.285.13:08:39.62/valo/01,524.99,yes,locked 2006.285.13:08:39.62/valo/02,534.99,yes,locked 2006.285.13:08:39.62/valo/03,564.99,yes,locked 2006.285.13:08:39.62/valo/04,624.99,yes,locked 2006.285.13:08:39.62/valo/05,734.99,yes,locked 2006.285.13:08:39.62/valo/06,814.99,yes,locked 2006.285.13:08:39.62/valo/07,864.99,yes,locked 2006.285.13:08:39.62/valo/08,884.99,yes,locked 2006.285.13:08:40.71/vb/01,04,usb,yes,30,28 2006.285.13:08:40.71/vb/02,05,usb,yes,28,28 2006.285.13:08:40.71/vb/03,04,usb,yes,29,32 2006.285.13:08:40.71/vb/04,05,usb,yes,30,28 2006.285.13:08:40.71/vb/05,04,usb,yes,26,28 2006.285.13:08:40.71/vb/06,03,usb,yes,37,33 2006.285.13:08:40.71/vb/07,04,usb,yes,30,30 2006.285.13:08:40.71/vb/08,04,usb,yes,27,31 2006.285.13:08:40.95/vblo/01,629.99,yes,locked 2006.285.13:08:40.95/vblo/02,634.99,yes,locked 2006.285.13:08:40.95/vblo/03,649.99,yes,locked 2006.285.13:08:40.95/vblo/04,679.99,yes,locked 2006.285.13:08:40.95/vblo/05,709.99,yes,locked 2006.285.13:08:40.95/vblo/06,719.99,yes,locked 2006.285.13:08:40.95/vblo/07,734.99,yes,locked 2006.285.13:08:40.95/vblo/08,744.99,yes,locked 2006.285.13:08:41.10/vabw/8 2006.285.13:08:41.25/vbbw/8 2006.285.13:08:41.34/xfe/off,on,12.2 2006.285.13:08:41.71/ifatt/23,28,28,28 2006.285.13:08:42.07/fmout-gps/S +2.70E-07 2006.285.13:08:42.09:!2006.285.13:09:57 2006.285.13:09:57.00:data_valid=off 2006.285.13:09:57.00:"et 2006.285.13:09:57.00:!+3s 2006.285.13:10:00.01:"tape 2006.285.13:10:00.01:postob 2006.285.13:10:00.22/cable/+6.4971E-03 2006.285.13:10:00.22/wx/19.01,1015.3,96 2006.285.13:10:01.07/fmout-gps/S +2.66E-07 2006.285.13:10:01.07:scan_name=285-1311,jd0610,160 2006.285.13:10:01.07:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.285.13:10:02.14#flagr#flagr/antenna,new-source 2006.285.13:10:02.14:checkk5 2006.285.13:10:02.73/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:10:03.17/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:10:03.65/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:10:04.01/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:10:04.52/chk_obsdata//k5ts1/T2851308??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.13:10:04.92/chk_obsdata//k5ts2/T2851308??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.13:10:05.40/chk_obsdata//k5ts3/T2851308??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.13:10:05.77/chk_obsdata//k5ts4/T2851308??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.13:10:06.62/k5log//k5ts1_log_newline 2006.285.13:10:07.36/k5log//k5ts2_log_newline 2006.285.13:10:08.13/k5log//k5ts3_log_newline 2006.285.13:10:09.15/k5log//k5ts4_log_newline 2006.285.13:10:09.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:10:09.18:setupk4=1 2006.285.13:10:09.18$setupk4/echo=on 2006.285.13:10:09.18$setupk4/pcalon 2006.285.13:10:09.18$pcalon/"no phase cal control is implemented here 2006.285.13:10:09.18$setupk4/"tpicd=stop 2006.285.13:10:09.18$setupk4/"rec=synch_on 2006.285.13:10:09.18$setupk4/"rec_mode=128 2006.285.13:10:09.18$setupk4/!* 2006.285.13:10:09.18$setupk4/recpk4 2006.285.13:10:09.18$recpk4/recpatch= 2006.285.13:10:09.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:10:09.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:10:09.18$setupk4/vck44 2006.285.13:10:09.18$vck44/valo=1,524.99 2006.285.13:10:09.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.13:10:09.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.13:10:09.18#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:09.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:10:09.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:10:09.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:10:09.18#ibcon#enter wrdev, iclass 26, count 0 2006.285.13:10:09.18#ibcon#first serial, iclass 26, count 0 2006.285.13:10:09.18#ibcon#enter sib2, iclass 26, count 0 2006.285.13:10:09.18#ibcon#flushed, iclass 26, count 0 2006.285.13:10:09.18#ibcon#about to write, iclass 26, count 0 2006.285.13:10:09.18#ibcon#wrote, iclass 26, count 0 2006.285.13:10:09.18#ibcon#about to read 3, iclass 26, count 0 2006.285.13:10:09.20#ibcon#read 3, iclass 26, count 0 2006.285.13:10:09.20#ibcon#about to read 4, iclass 26, count 0 2006.285.13:10:09.20#ibcon#read 4, iclass 26, count 0 2006.285.13:10:09.20#ibcon#about to read 5, iclass 26, count 0 2006.285.13:10:09.20#ibcon#read 5, iclass 26, count 0 2006.285.13:10:09.20#ibcon#about to read 6, iclass 26, count 0 2006.285.13:10:09.20#ibcon#read 6, iclass 26, count 0 2006.285.13:10:09.20#ibcon#end of sib2, iclass 26, count 0 2006.285.13:10:09.20#ibcon#*mode == 0, iclass 26, count 0 2006.285.13:10:09.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.13:10:09.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:10:09.20#ibcon#*before write, iclass 26, count 0 2006.285.13:10:09.20#ibcon#enter sib2, iclass 26, count 0 2006.285.13:10:09.20#ibcon#flushed, iclass 26, count 0 2006.285.13:10:09.20#ibcon#about to write, iclass 26, count 0 2006.285.13:10:09.20#ibcon#wrote, iclass 26, count 0 2006.285.13:10:09.20#ibcon#about to read 3, iclass 26, count 0 2006.285.13:10:09.25#ibcon#read 3, iclass 26, count 0 2006.285.13:10:09.25#ibcon#about to read 4, iclass 26, count 0 2006.285.13:10:09.25#ibcon#read 4, iclass 26, count 0 2006.285.13:10:09.25#ibcon#about to read 5, iclass 26, count 0 2006.285.13:10:09.25#ibcon#read 5, iclass 26, count 0 2006.285.13:10:09.25#ibcon#about to read 6, iclass 26, count 0 2006.285.13:10:09.25#ibcon#read 6, iclass 26, count 0 2006.285.13:10:09.25#ibcon#end of sib2, iclass 26, count 0 2006.285.13:10:09.25#ibcon#*after write, iclass 26, count 0 2006.285.13:10:09.25#ibcon#*before return 0, iclass 26, count 0 2006.285.13:10:09.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:10:09.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:10:09.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.13:10:09.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.13:10:09.25$vck44/va=1,7 2006.285.13:10:09.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.13:10:09.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.13:10:09.25#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:09.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:10:09.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:10:09.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:10:09.25#ibcon#enter wrdev, iclass 28, count 2 2006.285.13:10:09.25#ibcon#first serial, iclass 28, count 2 2006.285.13:10:09.25#ibcon#enter sib2, iclass 28, count 2 2006.285.13:10:09.25#ibcon#flushed, iclass 28, count 2 2006.285.13:10:09.25#ibcon#about to write, iclass 28, count 2 2006.285.13:10:09.25#ibcon#wrote, iclass 28, count 2 2006.285.13:10:09.25#ibcon#about to read 3, iclass 28, count 2 2006.285.13:10:09.27#ibcon#read 3, iclass 28, count 2 2006.285.13:10:09.27#ibcon#about to read 4, iclass 28, count 2 2006.285.13:10:09.27#ibcon#read 4, iclass 28, count 2 2006.285.13:10:09.27#ibcon#about to read 5, iclass 28, count 2 2006.285.13:10:09.27#ibcon#read 5, iclass 28, count 2 2006.285.13:10:09.27#ibcon#about to read 6, iclass 28, count 2 2006.285.13:10:09.27#ibcon#read 6, iclass 28, count 2 2006.285.13:10:09.27#ibcon#end of sib2, iclass 28, count 2 2006.285.13:10:09.27#ibcon#*mode == 0, iclass 28, count 2 2006.285.13:10:09.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.13:10:09.27#ibcon#[25=AT01-07\r\n] 2006.285.13:10:09.27#ibcon#*before write, iclass 28, count 2 2006.285.13:10:09.27#ibcon#enter sib2, iclass 28, count 2 2006.285.13:10:09.27#ibcon#flushed, iclass 28, count 2 2006.285.13:10:09.27#ibcon#about to write, iclass 28, count 2 2006.285.13:10:09.27#ibcon#wrote, iclass 28, count 2 2006.285.13:10:09.27#ibcon#about to read 3, iclass 28, count 2 2006.285.13:10:09.30#ibcon#read 3, iclass 28, count 2 2006.285.13:10:09.30#ibcon#about to read 4, iclass 28, count 2 2006.285.13:10:09.30#ibcon#read 4, iclass 28, count 2 2006.285.13:10:09.30#ibcon#about to read 5, iclass 28, count 2 2006.285.13:10:09.30#ibcon#read 5, iclass 28, count 2 2006.285.13:10:09.30#ibcon#about to read 6, iclass 28, count 2 2006.285.13:10:09.30#ibcon#read 6, iclass 28, count 2 2006.285.13:10:09.30#ibcon#end of sib2, iclass 28, count 2 2006.285.13:10:09.30#ibcon#*after write, iclass 28, count 2 2006.285.13:10:09.30#ibcon#*before return 0, iclass 28, count 2 2006.285.13:10:09.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:10:09.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:10:09.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.13:10:09.30#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:09.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:10:09.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:10:09.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:10:09.42#ibcon#enter wrdev, iclass 28, count 0 2006.285.13:10:09.42#ibcon#first serial, iclass 28, count 0 2006.285.13:10:09.42#ibcon#enter sib2, iclass 28, count 0 2006.285.13:10:09.42#ibcon#flushed, iclass 28, count 0 2006.285.13:10:09.42#ibcon#about to write, iclass 28, count 0 2006.285.13:10:09.42#ibcon#wrote, iclass 28, count 0 2006.285.13:10:09.42#ibcon#about to read 3, iclass 28, count 0 2006.285.13:10:09.44#ibcon#read 3, iclass 28, count 0 2006.285.13:10:09.44#ibcon#about to read 4, iclass 28, count 0 2006.285.13:10:09.44#ibcon#read 4, iclass 28, count 0 2006.285.13:10:09.44#ibcon#about to read 5, iclass 28, count 0 2006.285.13:10:09.44#ibcon#read 5, iclass 28, count 0 2006.285.13:10:09.44#ibcon#about to read 6, iclass 28, count 0 2006.285.13:10:09.44#ibcon#read 6, iclass 28, count 0 2006.285.13:10:09.44#ibcon#end of sib2, iclass 28, count 0 2006.285.13:10:09.44#ibcon#*mode == 0, iclass 28, count 0 2006.285.13:10:09.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.13:10:09.44#ibcon#[25=USB\r\n] 2006.285.13:10:09.44#ibcon#*before write, iclass 28, count 0 2006.285.13:10:09.44#ibcon#enter sib2, iclass 28, count 0 2006.285.13:10:09.44#ibcon#flushed, iclass 28, count 0 2006.285.13:10:09.44#ibcon#about to write, iclass 28, count 0 2006.285.13:10:09.44#ibcon#wrote, iclass 28, count 0 2006.285.13:10:09.44#ibcon#about to read 3, iclass 28, count 0 2006.285.13:10:09.47#ibcon#read 3, iclass 28, count 0 2006.285.13:10:09.47#ibcon#about to read 4, iclass 28, count 0 2006.285.13:10:09.47#ibcon#read 4, iclass 28, count 0 2006.285.13:10:09.47#ibcon#about to read 5, iclass 28, count 0 2006.285.13:10:09.47#ibcon#read 5, iclass 28, count 0 2006.285.13:10:09.47#ibcon#about to read 6, iclass 28, count 0 2006.285.13:10:09.47#ibcon#read 6, iclass 28, count 0 2006.285.13:10:09.47#ibcon#end of sib2, iclass 28, count 0 2006.285.13:10:09.47#ibcon#*after write, iclass 28, count 0 2006.285.13:10:09.47#ibcon#*before return 0, iclass 28, count 0 2006.285.13:10:09.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:10:09.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:10:09.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.13:10:09.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.13:10:09.47$vck44/valo=2,534.99 2006.285.13:10:09.47#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.13:10:09.47#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.13:10:09.47#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:09.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:10:09.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:10:09.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:10:09.47#ibcon#enter wrdev, iclass 30, count 0 2006.285.13:10:09.47#ibcon#first serial, iclass 30, count 0 2006.285.13:10:09.47#ibcon#enter sib2, iclass 30, count 0 2006.285.13:10:09.47#ibcon#flushed, iclass 30, count 0 2006.285.13:10:09.47#ibcon#about to write, iclass 30, count 0 2006.285.13:10:09.47#ibcon#wrote, iclass 30, count 0 2006.285.13:10:09.47#ibcon#about to read 3, iclass 30, count 0 2006.285.13:10:09.49#ibcon#read 3, iclass 30, count 0 2006.285.13:10:09.49#ibcon#about to read 4, iclass 30, count 0 2006.285.13:10:09.49#ibcon#read 4, iclass 30, count 0 2006.285.13:10:09.49#ibcon#about to read 5, iclass 30, count 0 2006.285.13:10:09.49#ibcon#read 5, iclass 30, count 0 2006.285.13:10:09.49#ibcon#about to read 6, iclass 30, count 0 2006.285.13:10:09.49#ibcon#read 6, iclass 30, count 0 2006.285.13:10:09.49#ibcon#end of sib2, iclass 30, count 0 2006.285.13:10:09.49#ibcon#*mode == 0, iclass 30, count 0 2006.285.13:10:09.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.13:10:09.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:10:09.49#ibcon#*before write, iclass 30, count 0 2006.285.13:10:09.49#ibcon#enter sib2, iclass 30, count 0 2006.285.13:10:09.49#ibcon#flushed, iclass 30, count 0 2006.285.13:10:09.49#ibcon#about to write, iclass 30, count 0 2006.285.13:10:09.49#ibcon#wrote, iclass 30, count 0 2006.285.13:10:09.49#ibcon#about to read 3, iclass 30, count 0 2006.285.13:10:09.53#ibcon#read 3, iclass 30, count 0 2006.285.13:10:09.53#ibcon#about to read 4, iclass 30, count 0 2006.285.13:10:09.53#ibcon#read 4, iclass 30, count 0 2006.285.13:10:09.53#ibcon#about to read 5, iclass 30, count 0 2006.285.13:10:09.53#ibcon#read 5, iclass 30, count 0 2006.285.13:10:09.53#ibcon#about to read 6, iclass 30, count 0 2006.285.13:10:09.53#ibcon#read 6, iclass 30, count 0 2006.285.13:10:09.53#ibcon#end of sib2, iclass 30, count 0 2006.285.13:10:09.53#ibcon#*after write, iclass 30, count 0 2006.285.13:10:09.53#ibcon#*before return 0, iclass 30, count 0 2006.285.13:10:09.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:10:09.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:10:09.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.13:10:09.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.13:10:09.53$vck44/va=2,6 2006.285.13:10:09.53#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.13:10:09.53#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.13:10:09.53#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:09.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:10:09.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:10:09.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:10:09.59#ibcon#enter wrdev, iclass 32, count 2 2006.285.13:10:09.59#ibcon#first serial, iclass 32, count 2 2006.285.13:10:09.59#ibcon#enter sib2, iclass 32, count 2 2006.285.13:10:09.59#ibcon#flushed, iclass 32, count 2 2006.285.13:10:09.59#ibcon#about to write, iclass 32, count 2 2006.285.13:10:09.59#ibcon#wrote, iclass 32, count 2 2006.285.13:10:09.59#ibcon#about to read 3, iclass 32, count 2 2006.285.13:10:09.61#ibcon#read 3, iclass 32, count 2 2006.285.13:10:09.61#ibcon#about to read 4, iclass 32, count 2 2006.285.13:10:09.61#ibcon#read 4, iclass 32, count 2 2006.285.13:10:09.61#ibcon#about to read 5, iclass 32, count 2 2006.285.13:10:09.61#ibcon#read 5, iclass 32, count 2 2006.285.13:10:09.61#ibcon#about to read 6, iclass 32, count 2 2006.285.13:10:09.61#ibcon#read 6, iclass 32, count 2 2006.285.13:10:09.61#ibcon#end of sib2, iclass 32, count 2 2006.285.13:10:09.61#ibcon#*mode == 0, iclass 32, count 2 2006.285.13:10:09.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.13:10:09.61#ibcon#[25=AT02-06\r\n] 2006.285.13:10:09.61#ibcon#*before write, iclass 32, count 2 2006.285.13:10:09.61#ibcon#enter sib2, iclass 32, count 2 2006.285.13:10:09.61#ibcon#flushed, iclass 32, count 2 2006.285.13:10:09.61#ibcon#about to write, iclass 32, count 2 2006.285.13:10:09.61#ibcon#wrote, iclass 32, count 2 2006.285.13:10:09.61#ibcon#about to read 3, iclass 32, count 2 2006.285.13:10:09.64#ibcon#read 3, iclass 32, count 2 2006.285.13:10:09.64#ibcon#about to read 4, iclass 32, count 2 2006.285.13:10:09.64#ibcon#read 4, iclass 32, count 2 2006.285.13:10:09.64#ibcon#about to read 5, iclass 32, count 2 2006.285.13:10:09.64#ibcon#read 5, iclass 32, count 2 2006.285.13:10:09.64#ibcon#about to read 6, iclass 32, count 2 2006.285.13:10:09.64#ibcon#read 6, iclass 32, count 2 2006.285.13:10:09.64#ibcon#end of sib2, iclass 32, count 2 2006.285.13:10:09.64#ibcon#*after write, iclass 32, count 2 2006.285.13:10:09.64#ibcon#*before return 0, iclass 32, count 2 2006.285.13:10:09.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:10:09.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:10:09.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.13:10:09.64#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:09.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:10:09.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:10:09.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:10:09.76#ibcon#enter wrdev, iclass 32, count 0 2006.285.13:10:09.76#ibcon#first serial, iclass 32, count 0 2006.285.13:10:09.76#ibcon#enter sib2, iclass 32, count 0 2006.285.13:10:09.76#ibcon#flushed, iclass 32, count 0 2006.285.13:10:09.76#ibcon#about to write, iclass 32, count 0 2006.285.13:10:09.76#ibcon#wrote, iclass 32, count 0 2006.285.13:10:09.76#ibcon#about to read 3, iclass 32, count 0 2006.285.13:10:09.78#ibcon#read 3, iclass 32, count 0 2006.285.13:10:09.78#ibcon#about to read 4, iclass 32, count 0 2006.285.13:10:09.78#ibcon#read 4, iclass 32, count 0 2006.285.13:10:09.78#ibcon#about to read 5, iclass 32, count 0 2006.285.13:10:09.78#ibcon#read 5, iclass 32, count 0 2006.285.13:10:09.78#ibcon#about to read 6, iclass 32, count 0 2006.285.13:10:09.78#ibcon#read 6, iclass 32, count 0 2006.285.13:10:09.78#ibcon#end of sib2, iclass 32, count 0 2006.285.13:10:09.78#ibcon#*mode == 0, iclass 32, count 0 2006.285.13:10:09.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.13:10:09.78#ibcon#[25=USB\r\n] 2006.285.13:10:09.78#ibcon#*before write, iclass 32, count 0 2006.285.13:10:09.78#ibcon#enter sib2, iclass 32, count 0 2006.285.13:10:09.78#ibcon#flushed, iclass 32, count 0 2006.285.13:10:09.78#ibcon#about to write, iclass 32, count 0 2006.285.13:10:09.78#ibcon#wrote, iclass 32, count 0 2006.285.13:10:09.78#ibcon#about to read 3, iclass 32, count 0 2006.285.13:10:09.81#ibcon#read 3, iclass 32, count 0 2006.285.13:10:09.81#ibcon#about to read 4, iclass 32, count 0 2006.285.13:10:09.81#ibcon#read 4, iclass 32, count 0 2006.285.13:10:09.81#ibcon#about to read 5, iclass 32, count 0 2006.285.13:10:09.81#ibcon#read 5, iclass 32, count 0 2006.285.13:10:09.81#ibcon#about to read 6, iclass 32, count 0 2006.285.13:10:09.81#ibcon#read 6, iclass 32, count 0 2006.285.13:10:09.81#ibcon#end of sib2, iclass 32, count 0 2006.285.13:10:09.81#ibcon#*after write, iclass 32, count 0 2006.285.13:10:09.81#ibcon#*before return 0, iclass 32, count 0 2006.285.13:10:09.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:10:09.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:10:09.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.13:10:09.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.13:10:09.81$vck44/valo=3,564.99 2006.285.13:10:09.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.13:10:09.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.13:10:09.81#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:09.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:10:09.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:10:09.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:10:09.81#ibcon#enter wrdev, iclass 34, count 0 2006.285.13:10:09.81#ibcon#first serial, iclass 34, count 0 2006.285.13:10:09.81#ibcon#enter sib2, iclass 34, count 0 2006.285.13:10:09.81#ibcon#flushed, iclass 34, count 0 2006.285.13:10:09.81#ibcon#about to write, iclass 34, count 0 2006.285.13:10:09.81#ibcon#wrote, iclass 34, count 0 2006.285.13:10:09.81#ibcon#about to read 3, iclass 34, count 0 2006.285.13:10:09.83#ibcon#read 3, iclass 34, count 0 2006.285.13:10:09.83#ibcon#about to read 4, iclass 34, count 0 2006.285.13:10:09.83#ibcon#read 4, iclass 34, count 0 2006.285.13:10:09.83#ibcon#about to read 5, iclass 34, count 0 2006.285.13:10:09.83#ibcon#read 5, iclass 34, count 0 2006.285.13:10:09.83#ibcon#about to read 6, iclass 34, count 0 2006.285.13:10:09.83#ibcon#read 6, iclass 34, count 0 2006.285.13:10:09.83#ibcon#end of sib2, iclass 34, count 0 2006.285.13:10:09.83#ibcon#*mode == 0, iclass 34, count 0 2006.285.13:10:09.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.13:10:09.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:10:09.83#ibcon#*before write, iclass 34, count 0 2006.285.13:10:09.83#ibcon#enter sib2, iclass 34, count 0 2006.285.13:10:09.83#ibcon#flushed, iclass 34, count 0 2006.285.13:10:09.83#ibcon#about to write, iclass 34, count 0 2006.285.13:10:09.83#ibcon#wrote, iclass 34, count 0 2006.285.13:10:09.83#ibcon#about to read 3, iclass 34, count 0 2006.285.13:10:09.87#ibcon#read 3, iclass 34, count 0 2006.285.13:10:09.87#ibcon#about to read 4, iclass 34, count 0 2006.285.13:10:09.87#ibcon#read 4, iclass 34, count 0 2006.285.13:10:09.87#ibcon#about to read 5, iclass 34, count 0 2006.285.13:10:09.87#ibcon#read 5, iclass 34, count 0 2006.285.13:10:09.87#ibcon#about to read 6, iclass 34, count 0 2006.285.13:10:09.87#ibcon#read 6, iclass 34, count 0 2006.285.13:10:09.87#ibcon#end of sib2, iclass 34, count 0 2006.285.13:10:09.87#ibcon#*after write, iclass 34, count 0 2006.285.13:10:09.87#ibcon#*before return 0, iclass 34, count 0 2006.285.13:10:09.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:10:09.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:10:09.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.13:10:09.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.13:10:09.87$vck44/va=3,7 2006.285.13:10:09.87#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.13:10:09.87#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.13:10:09.87#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:09.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:10:09.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:10:09.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:10:09.93#ibcon#enter wrdev, iclass 36, count 2 2006.285.13:10:09.93#ibcon#first serial, iclass 36, count 2 2006.285.13:10:09.93#ibcon#enter sib2, iclass 36, count 2 2006.285.13:10:09.93#ibcon#flushed, iclass 36, count 2 2006.285.13:10:09.93#ibcon#about to write, iclass 36, count 2 2006.285.13:10:09.93#ibcon#wrote, iclass 36, count 2 2006.285.13:10:09.93#ibcon#about to read 3, iclass 36, count 2 2006.285.13:10:09.95#ibcon#read 3, iclass 36, count 2 2006.285.13:10:09.95#ibcon#about to read 4, iclass 36, count 2 2006.285.13:10:09.95#ibcon#read 4, iclass 36, count 2 2006.285.13:10:09.95#ibcon#about to read 5, iclass 36, count 2 2006.285.13:10:09.95#ibcon#read 5, iclass 36, count 2 2006.285.13:10:09.95#ibcon#about to read 6, iclass 36, count 2 2006.285.13:10:09.95#ibcon#read 6, iclass 36, count 2 2006.285.13:10:09.95#ibcon#end of sib2, iclass 36, count 2 2006.285.13:10:09.95#ibcon#*mode == 0, iclass 36, count 2 2006.285.13:10:09.95#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.13:10:09.95#ibcon#[25=AT03-07\r\n] 2006.285.13:10:09.95#ibcon#*before write, iclass 36, count 2 2006.285.13:10:09.95#ibcon#enter sib2, iclass 36, count 2 2006.285.13:10:09.95#ibcon#flushed, iclass 36, count 2 2006.285.13:10:09.95#ibcon#about to write, iclass 36, count 2 2006.285.13:10:09.95#ibcon#wrote, iclass 36, count 2 2006.285.13:10:09.95#ibcon#about to read 3, iclass 36, count 2 2006.285.13:10:09.98#ibcon#read 3, iclass 36, count 2 2006.285.13:10:09.98#ibcon#about to read 4, iclass 36, count 2 2006.285.13:10:09.98#ibcon#read 4, iclass 36, count 2 2006.285.13:10:09.98#ibcon#about to read 5, iclass 36, count 2 2006.285.13:10:09.98#ibcon#read 5, iclass 36, count 2 2006.285.13:10:09.98#ibcon#about to read 6, iclass 36, count 2 2006.285.13:10:09.98#ibcon#read 6, iclass 36, count 2 2006.285.13:10:09.98#ibcon#end of sib2, iclass 36, count 2 2006.285.13:10:09.98#ibcon#*after write, iclass 36, count 2 2006.285.13:10:09.98#ibcon#*before return 0, iclass 36, count 2 2006.285.13:10:09.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:10:09.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:10:09.98#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.13:10:09.98#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:09.98#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:10:10.10#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:10:10.10#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:10:10.10#ibcon#enter wrdev, iclass 36, count 0 2006.285.13:10:10.10#ibcon#first serial, iclass 36, count 0 2006.285.13:10:10.10#ibcon#enter sib2, iclass 36, count 0 2006.285.13:10:10.10#ibcon#flushed, iclass 36, count 0 2006.285.13:10:10.10#ibcon#about to write, iclass 36, count 0 2006.285.13:10:10.10#ibcon#wrote, iclass 36, count 0 2006.285.13:10:10.10#ibcon#about to read 3, iclass 36, count 0 2006.285.13:10:10.12#ibcon#read 3, iclass 36, count 0 2006.285.13:10:10.12#ibcon#about to read 4, iclass 36, count 0 2006.285.13:10:10.12#ibcon#read 4, iclass 36, count 0 2006.285.13:10:10.12#ibcon#about to read 5, iclass 36, count 0 2006.285.13:10:10.12#ibcon#read 5, iclass 36, count 0 2006.285.13:10:10.12#ibcon#about to read 6, iclass 36, count 0 2006.285.13:10:10.12#ibcon#read 6, iclass 36, count 0 2006.285.13:10:10.12#ibcon#end of sib2, iclass 36, count 0 2006.285.13:10:10.12#ibcon#*mode == 0, iclass 36, count 0 2006.285.13:10:10.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.13:10:10.12#ibcon#[25=USB\r\n] 2006.285.13:10:10.12#ibcon#*before write, iclass 36, count 0 2006.285.13:10:10.12#ibcon#enter sib2, iclass 36, count 0 2006.285.13:10:10.12#ibcon#flushed, iclass 36, count 0 2006.285.13:10:10.12#ibcon#about to write, iclass 36, count 0 2006.285.13:10:10.12#ibcon#wrote, iclass 36, count 0 2006.285.13:10:10.12#ibcon#about to read 3, iclass 36, count 0 2006.285.13:10:10.15#ibcon#read 3, iclass 36, count 0 2006.285.13:10:10.15#ibcon#about to read 4, iclass 36, count 0 2006.285.13:10:10.15#ibcon#read 4, iclass 36, count 0 2006.285.13:10:10.15#ibcon#about to read 5, iclass 36, count 0 2006.285.13:10:10.15#ibcon#read 5, iclass 36, count 0 2006.285.13:10:10.15#ibcon#about to read 6, iclass 36, count 0 2006.285.13:10:10.15#ibcon#read 6, iclass 36, count 0 2006.285.13:10:10.15#ibcon#end of sib2, iclass 36, count 0 2006.285.13:10:10.15#ibcon#*after write, iclass 36, count 0 2006.285.13:10:10.15#ibcon#*before return 0, iclass 36, count 0 2006.285.13:10:10.15#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:10:10.15#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:10:10.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.13:10:10.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.13:10:10.15$vck44/valo=4,624.99 2006.285.13:10:10.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.13:10:10.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.13:10:10.15#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:10.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:10:10.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:10:10.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:10:10.15#ibcon#enter wrdev, iclass 38, count 0 2006.285.13:10:10.15#ibcon#first serial, iclass 38, count 0 2006.285.13:10:10.15#ibcon#enter sib2, iclass 38, count 0 2006.285.13:10:10.15#ibcon#flushed, iclass 38, count 0 2006.285.13:10:10.15#ibcon#about to write, iclass 38, count 0 2006.285.13:10:10.15#ibcon#wrote, iclass 38, count 0 2006.285.13:10:10.57#ibcon#about to read 3, iclass 38, count 0 2006.285.13:10:10.57#ibcon#read 3, iclass 38, count 0 2006.285.13:10:10.57#ibcon#about to read 4, iclass 38, count 0 2006.285.13:10:10.57#ibcon#read 4, iclass 38, count 0 2006.285.13:10:10.57#ibcon#about to read 5, iclass 38, count 0 2006.285.13:10:10.57#ibcon#read 5, iclass 38, count 0 2006.285.13:10:10.57#ibcon#about to read 6, iclass 38, count 0 2006.285.13:10:10.57#ibcon#read 6, iclass 38, count 0 2006.285.13:10:10.57#ibcon#end of sib2, iclass 38, count 0 2006.285.13:10:10.57#ibcon#*mode == 0, iclass 38, count 0 2006.285.13:10:10.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.13:10:10.57#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:10:10.57#ibcon#*before write, iclass 38, count 0 2006.285.13:10:10.57#ibcon#enter sib2, iclass 38, count 0 2006.285.13:10:10.57#ibcon#flushed, iclass 38, count 0 2006.285.13:10:10.57#ibcon#about to write, iclass 38, count 0 2006.285.13:10:10.57#ibcon#wrote, iclass 38, count 0 2006.285.13:10:10.57#ibcon#about to read 3, iclass 38, count 0 2006.285.13:10:10.61#ibcon#read 3, iclass 38, count 0 2006.285.13:10:10.61#ibcon#about to read 4, iclass 38, count 0 2006.285.13:10:10.61#ibcon#read 4, iclass 38, count 0 2006.285.13:10:10.61#ibcon#about to read 5, iclass 38, count 0 2006.285.13:10:10.61#ibcon#read 5, iclass 38, count 0 2006.285.13:10:10.61#ibcon#about to read 6, iclass 38, count 0 2006.285.13:10:10.61#ibcon#read 6, iclass 38, count 0 2006.285.13:10:10.61#ibcon#end of sib2, iclass 38, count 0 2006.285.13:10:10.61#ibcon#*after write, iclass 38, count 0 2006.285.13:10:10.61#ibcon#*before return 0, iclass 38, count 0 2006.285.13:10:10.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:10:10.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:10:10.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.13:10:10.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.13:10:10.61$vck44/va=4,6 2006.285.13:10:10.61#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.13:10:10.61#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.13:10:10.61#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:10.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:10:10.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:10:10.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:10:10.61#ibcon#enter wrdev, iclass 40, count 2 2006.285.13:10:10.61#ibcon#first serial, iclass 40, count 2 2006.285.13:10:10.61#ibcon#enter sib2, iclass 40, count 2 2006.285.13:10:10.61#ibcon#flushed, iclass 40, count 2 2006.285.13:10:10.61#ibcon#about to write, iclass 40, count 2 2006.285.13:10:10.61#ibcon#wrote, iclass 40, count 2 2006.285.13:10:10.61#ibcon#about to read 3, iclass 40, count 2 2006.285.13:10:10.63#ibcon#read 3, iclass 40, count 2 2006.285.13:10:10.63#ibcon#about to read 4, iclass 40, count 2 2006.285.13:10:10.63#ibcon#read 4, iclass 40, count 2 2006.285.13:10:10.63#ibcon#about to read 5, iclass 40, count 2 2006.285.13:10:10.63#ibcon#read 5, iclass 40, count 2 2006.285.13:10:10.63#ibcon#about to read 6, iclass 40, count 2 2006.285.13:10:10.63#ibcon#read 6, iclass 40, count 2 2006.285.13:10:10.63#ibcon#end of sib2, iclass 40, count 2 2006.285.13:10:10.63#ibcon#*mode == 0, iclass 40, count 2 2006.285.13:10:10.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.13:10:10.63#ibcon#[25=AT04-06\r\n] 2006.285.13:10:10.63#ibcon#*before write, iclass 40, count 2 2006.285.13:10:10.63#ibcon#enter sib2, iclass 40, count 2 2006.285.13:10:10.63#ibcon#flushed, iclass 40, count 2 2006.285.13:10:10.63#ibcon#about to write, iclass 40, count 2 2006.285.13:10:10.63#ibcon#wrote, iclass 40, count 2 2006.285.13:10:10.63#ibcon#about to read 3, iclass 40, count 2 2006.285.13:10:10.66#ibcon#read 3, iclass 40, count 2 2006.285.13:10:10.66#ibcon#about to read 4, iclass 40, count 2 2006.285.13:10:10.66#ibcon#read 4, iclass 40, count 2 2006.285.13:10:10.66#ibcon#about to read 5, iclass 40, count 2 2006.285.13:10:10.66#ibcon#read 5, iclass 40, count 2 2006.285.13:10:10.66#ibcon#about to read 6, iclass 40, count 2 2006.285.13:10:10.66#ibcon#read 6, iclass 40, count 2 2006.285.13:10:10.66#ibcon#end of sib2, iclass 40, count 2 2006.285.13:10:10.66#ibcon#*after write, iclass 40, count 2 2006.285.13:10:10.66#ibcon#*before return 0, iclass 40, count 2 2006.285.13:10:10.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:10:10.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:10:10.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.13:10:10.66#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:10.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:10:10.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:10:10.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:10:10.78#ibcon#enter wrdev, iclass 40, count 0 2006.285.13:10:10.78#ibcon#first serial, iclass 40, count 0 2006.285.13:10:10.78#ibcon#enter sib2, iclass 40, count 0 2006.285.13:10:10.78#ibcon#flushed, iclass 40, count 0 2006.285.13:10:10.78#ibcon#about to write, iclass 40, count 0 2006.285.13:10:10.78#ibcon#wrote, iclass 40, count 0 2006.285.13:10:10.78#ibcon#about to read 3, iclass 40, count 0 2006.285.13:10:10.80#ibcon#read 3, iclass 40, count 0 2006.285.13:10:10.80#ibcon#about to read 4, iclass 40, count 0 2006.285.13:10:10.80#ibcon#read 4, iclass 40, count 0 2006.285.13:10:10.80#ibcon#about to read 5, iclass 40, count 0 2006.285.13:10:10.80#ibcon#read 5, iclass 40, count 0 2006.285.13:10:10.80#ibcon#about to read 6, iclass 40, count 0 2006.285.13:10:10.80#ibcon#read 6, iclass 40, count 0 2006.285.13:10:10.80#ibcon#end of sib2, iclass 40, count 0 2006.285.13:10:10.80#ibcon#*mode == 0, iclass 40, count 0 2006.285.13:10:10.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.13:10:10.80#ibcon#[25=USB\r\n] 2006.285.13:10:10.80#ibcon#*before write, iclass 40, count 0 2006.285.13:10:10.80#ibcon#enter sib2, iclass 40, count 0 2006.285.13:10:10.80#ibcon#flushed, iclass 40, count 0 2006.285.13:10:10.80#ibcon#about to write, iclass 40, count 0 2006.285.13:10:10.80#ibcon#wrote, iclass 40, count 0 2006.285.13:10:10.80#ibcon#about to read 3, iclass 40, count 0 2006.285.13:10:10.83#ibcon#read 3, iclass 40, count 0 2006.285.13:10:10.83#ibcon#about to read 4, iclass 40, count 0 2006.285.13:10:10.83#ibcon#read 4, iclass 40, count 0 2006.285.13:10:10.83#ibcon#about to read 5, iclass 40, count 0 2006.285.13:10:10.83#ibcon#read 5, iclass 40, count 0 2006.285.13:10:10.83#ibcon#about to read 6, iclass 40, count 0 2006.285.13:10:10.83#ibcon#read 6, iclass 40, count 0 2006.285.13:10:10.83#ibcon#end of sib2, iclass 40, count 0 2006.285.13:10:10.83#ibcon#*after write, iclass 40, count 0 2006.285.13:10:10.83#ibcon#*before return 0, iclass 40, count 0 2006.285.13:10:10.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:10:10.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:10:10.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.13:10:10.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.13:10:10.83$vck44/valo=5,734.99 2006.285.13:10:10.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.13:10:10.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.13:10:10.83#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:10.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:10:10.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:10:10.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:10:10.83#ibcon#enter wrdev, iclass 4, count 0 2006.285.13:10:10.83#ibcon#first serial, iclass 4, count 0 2006.285.13:10:10.83#ibcon#enter sib2, iclass 4, count 0 2006.285.13:10:10.83#ibcon#flushed, iclass 4, count 0 2006.285.13:10:10.83#ibcon#about to write, iclass 4, count 0 2006.285.13:10:10.83#ibcon#wrote, iclass 4, count 0 2006.285.13:10:10.83#ibcon#about to read 3, iclass 4, count 0 2006.285.13:10:10.85#ibcon#read 3, iclass 4, count 0 2006.285.13:10:11.02#ibcon#about to read 4, iclass 4, count 0 2006.285.13:10:11.02#ibcon#read 4, iclass 4, count 0 2006.285.13:10:11.02#ibcon#about to read 5, iclass 4, count 0 2006.285.13:10:11.02#ibcon#read 5, iclass 4, count 0 2006.285.13:10:11.02#ibcon#about to read 6, iclass 4, count 0 2006.285.13:10:11.02#ibcon#read 6, iclass 4, count 0 2006.285.13:10:11.02#ibcon#end of sib2, iclass 4, count 0 2006.285.13:10:11.02#ibcon#*mode == 0, iclass 4, count 0 2006.285.13:10:11.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.13:10:11.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:10:11.02#ibcon#*before write, iclass 4, count 0 2006.285.13:10:11.02#ibcon#enter sib2, iclass 4, count 0 2006.285.13:10:11.02#ibcon#flushed, iclass 4, count 0 2006.285.13:10:11.02#ibcon#about to write, iclass 4, count 0 2006.285.13:10:11.02#ibcon#wrote, iclass 4, count 0 2006.285.13:10:11.02#ibcon#about to read 3, iclass 4, count 0 2006.285.13:10:11.06#ibcon#read 3, iclass 4, count 0 2006.285.13:10:11.06#ibcon#about to read 4, iclass 4, count 0 2006.285.13:10:11.06#ibcon#read 4, iclass 4, count 0 2006.285.13:10:11.06#ibcon#about to read 5, iclass 4, count 0 2006.285.13:10:11.06#ibcon#read 5, iclass 4, count 0 2006.285.13:10:11.06#ibcon#about to read 6, iclass 4, count 0 2006.285.13:10:11.06#ibcon#read 6, iclass 4, count 0 2006.285.13:10:11.06#ibcon#end of sib2, iclass 4, count 0 2006.285.13:10:11.06#ibcon#*after write, iclass 4, count 0 2006.285.13:10:11.06#ibcon#*before return 0, iclass 4, count 0 2006.285.13:10:11.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:10:11.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:10:11.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.13:10:11.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.13:10:11.06$vck44/va=5,3 2006.285.13:10:11.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.13:10:11.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.13:10:11.06#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:11.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:10:11.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:10:11.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:10:11.06#ibcon#enter wrdev, iclass 6, count 2 2006.285.13:10:11.06#ibcon#first serial, iclass 6, count 2 2006.285.13:10:11.06#ibcon#enter sib2, iclass 6, count 2 2006.285.13:10:11.06#ibcon#flushed, iclass 6, count 2 2006.285.13:10:11.06#ibcon#about to write, iclass 6, count 2 2006.285.13:10:11.06#ibcon#wrote, iclass 6, count 2 2006.285.13:10:11.06#ibcon#about to read 3, iclass 6, count 2 2006.285.13:10:11.08#ibcon#read 3, iclass 6, count 2 2006.285.13:10:11.08#ibcon#about to read 4, iclass 6, count 2 2006.285.13:10:11.08#ibcon#read 4, iclass 6, count 2 2006.285.13:10:11.08#ibcon#about to read 5, iclass 6, count 2 2006.285.13:10:11.08#ibcon#read 5, iclass 6, count 2 2006.285.13:10:11.08#ibcon#about to read 6, iclass 6, count 2 2006.285.13:10:11.08#ibcon#read 6, iclass 6, count 2 2006.285.13:10:11.08#ibcon#end of sib2, iclass 6, count 2 2006.285.13:10:11.08#ibcon#*mode == 0, iclass 6, count 2 2006.285.13:10:11.08#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.13:10:11.08#ibcon#[25=AT05-03\r\n] 2006.285.13:10:11.08#ibcon#*before write, iclass 6, count 2 2006.285.13:10:11.08#ibcon#enter sib2, iclass 6, count 2 2006.285.13:10:11.08#ibcon#flushed, iclass 6, count 2 2006.285.13:10:11.08#ibcon#about to write, iclass 6, count 2 2006.285.13:10:11.08#ibcon#wrote, iclass 6, count 2 2006.285.13:10:11.08#ibcon#about to read 3, iclass 6, count 2 2006.285.13:10:11.11#ibcon#read 3, iclass 6, count 2 2006.285.13:10:11.11#ibcon#about to read 4, iclass 6, count 2 2006.285.13:10:11.11#ibcon#read 4, iclass 6, count 2 2006.285.13:10:11.11#ibcon#about to read 5, iclass 6, count 2 2006.285.13:10:11.11#ibcon#read 5, iclass 6, count 2 2006.285.13:10:11.11#ibcon#about to read 6, iclass 6, count 2 2006.285.13:10:11.11#ibcon#read 6, iclass 6, count 2 2006.285.13:10:11.11#ibcon#end of sib2, iclass 6, count 2 2006.285.13:10:11.11#ibcon#*after write, iclass 6, count 2 2006.285.13:10:11.11#ibcon#*before return 0, iclass 6, count 2 2006.285.13:10:11.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:10:11.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:10:11.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.13:10:11.11#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:11.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:10:11.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:10:11.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:10:11.23#ibcon#enter wrdev, iclass 6, count 0 2006.285.13:10:11.23#ibcon#first serial, iclass 6, count 0 2006.285.13:10:11.23#ibcon#enter sib2, iclass 6, count 0 2006.285.13:10:11.23#ibcon#flushed, iclass 6, count 0 2006.285.13:10:11.23#ibcon#about to write, iclass 6, count 0 2006.285.13:10:11.23#ibcon#wrote, iclass 6, count 0 2006.285.13:10:11.23#ibcon#about to read 3, iclass 6, count 0 2006.285.13:10:11.25#ibcon#read 3, iclass 6, count 0 2006.285.13:10:11.25#ibcon#about to read 4, iclass 6, count 0 2006.285.13:10:11.25#ibcon#read 4, iclass 6, count 0 2006.285.13:10:11.25#ibcon#about to read 5, iclass 6, count 0 2006.285.13:10:11.25#ibcon#read 5, iclass 6, count 0 2006.285.13:10:11.25#ibcon#about to read 6, iclass 6, count 0 2006.285.13:10:11.25#ibcon#read 6, iclass 6, count 0 2006.285.13:10:11.25#ibcon#end of sib2, iclass 6, count 0 2006.285.13:10:11.25#ibcon#*mode == 0, iclass 6, count 0 2006.285.13:10:11.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.13:10:11.25#ibcon#[25=USB\r\n] 2006.285.13:10:11.25#ibcon#*before write, iclass 6, count 0 2006.285.13:10:11.25#ibcon#enter sib2, iclass 6, count 0 2006.285.13:10:11.25#ibcon#flushed, iclass 6, count 0 2006.285.13:10:11.25#ibcon#about to write, iclass 6, count 0 2006.285.13:10:11.25#ibcon#wrote, iclass 6, count 0 2006.285.13:10:11.25#ibcon#about to read 3, iclass 6, count 0 2006.285.13:10:11.28#ibcon#read 3, iclass 6, count 0 2006.285.13:10:11.28#ibcon#about to read 4, iclass 6, count 0 2006.285.13:10:11.28#ibcon#read 4, iclass 6, count 0 2006.285.13:10:11.28#ibcon#about to read 5, iclass 6, count 0 2006.285.13:10:11.28#ibcon#read 5, iclass 6, count 0 2006.285.13:10:11.28#ibcon#about to read 6, iclass 6, count 0 2006.285.13:10:11.28#ibcon#read 6, iclass 6, count 0 2006.285.13:10:11.28#ibcon#end of sib2, iclass 6, count 0 2006.285.13:10:11.28#ibcon#*after write, iclass 6, count 0 2006.285.13:10:11.28#ibcon#*before return 0, iclass 6, count 0 2006.285.13:10:11.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:10:11.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:10:11.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.13:10:11.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.13:10:11.28$vck44/valo=6,814.99 2006.285.13:10:11.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.13:10:11.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.13:10:11.28#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:11.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:10:11.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:10:11.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:10:11.28#ibcon#enter wrdev, iclass 10, count 0 2006.285.13:10:11.28#ibcon#first serial, iclass 10, count 0 2006.285.13:10:11.28#ibcon#enter sib2, iclass 10, count 0 2006.285.13:10:11.28#ibcon#flushed, iclass 10, count 0 2006.285.13:10:11.28#ibcon#about to write, iclass 10, count 0 2006.285.13:10:11.28#ibcon#wrote, iclass 10, count 0 2006.285.13:10:11.28#ibcon#about to read 3, iclass 10, count 0 2006.285.13:10:11.30#ibcon#read 3, iclass 10, count 0 2006.285.13:10:11.42#ibcon#about to read 4, iclass 10, count 0 2006.285.13:10:11.42#ibcon#read 4, iclass 10, count 0 2006.285.13:10:11.42#ibcon#about to read 5, iclass 10, count 0 2006.285.13:10:11.42#ibcon#read 5, iclass 10, count 0 2006.285.13:10:11.42#ibcon#about to read 6, iclass 10, count 0 2006.285.13:10:11.42#ibcon#read 6, iclass 10, count 0 2006.285.13:10:11.42#ibcon#end of sib2, iclass 10, count 0 2006.285.13:10:11.42#ibcon#*mode == 0, iclass 10, count 0 2006.285.13:10:11.42#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.13:10:11.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:10:11.42#ibcon#*before write, iclass 10, count 0 2006.285.13:10:11.42#ibcon#enter sib2, iclass 10, count 0 2006.285.13:10:11.42#ibcon#flushed, iclass 10, count 0 2006.285.13:10:11.42#ibcon#about to write, iclass 10, count 0 2006.285.13:10:11.42#ibcon#wrote, iclass 10, count 0 2006.285.13:10:11.42#ibcon#about to read 3, iclass 10, count 0 2006.285.13:10:11.46#ibcon#read 3, iclass 10, count 0 2006.285.13:10:11.46#ibcon#about to read 4, iclass 10, count 0 2006.285.13:10:11.46#ibcon#read 4, iclass 10, count 0 2006.285.13:10:11.46#ibcon#about to read 5, iclass 10, count 0 2006.285.13:10:11.46#ibcon#read 5, iclass 10, count 0 2006.285.13:10:11.46#ibcon#about to read 6, iclass 10, count 0 2006.285.13:10:11.46#ibcon#read 6, iclass 10, count 0 2006.285.13:10:11.46#ibcon#end of sib2, iclass 10, count 0 2006.285.13:10:11.46#ibcon#*after write, iclass 10, count 0 2006.285.13:10:11.46#ibcon#*before return 0, iclass 10, count 0 2006.285.13:10:11.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:10:11.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:10:11.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.13:10:11.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.13:10:11.46$vck44/va=6,4 2006.285.13:10:11.46#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.13:10:11.46#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.13:10:11.46#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:11.46#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:10:11.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:10:11.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:10:11.46#ibcon#enter wrdev, iclass 12, count 2 2006.285.13:10:11.46#ibcon#first serial, iclass 12, count 2 2006.285.13:10:11.46#ibcon#enter sib2, iclass 12, count 2 2006.285.13:10:11.46#ibcon#flushed, iclass 12, count 2 2006.285.13:10:11.46#ibcon#about to write, iclass 12, count 2 2006.285.13:10:11.46#ibcon#wrote, iclass 12, count 2 2006.285.13:10:11.46#ibcon#about to read 3, iclass 12, count 2 2006.285.13:10:11.48#ibcon#read 3, iclass 12, count 2 2006.285.13:10:11.48#ibcon#about to read 4, iclass 12, count 2 2006.285.13:10:11.48#ibcon#read 4, iclass 12, count 2 2006.285.13:10:11.48#ibcon#about to read 5, iclass 12, count 2 2006.285.13:10:11.48#ibcon#read 5, iclass 12, count 2 2006.285.13:10:11.48#ibcon#about to read 6, iclass 12, count 2 2006.285.13:10:11.48#ibcon#read 6, iclass 12, count 2 2006.285.13:10:11.48#ibcon#end of sib2, iclass 12, count 2 2006.285.13:10:11.48#ibcon#*mode == 0, iclass 12, count 2 2006.285.13:10:11.48#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.13:10:11.48#ibcon#[25=AT06-04\r\n] 2006.285.13:10:11.48#ibcon#*before write, iclass 12, count 2 2006.285.13:10:11.48#ibcon#enter sib2, iclass 12, count 2 2006.285.13:10:11.48#ibcon#flushed, iclass 12, count 2 2006.285.13:10:11.48#ibcon#about to write, iclass 12, count 2 2006.285.13:10:11.48#ibcon#wrote, iclass 12, count 2 2006.285.13:10:11.48#ibcon#about to read 3, iclass 12, count 2 2006.285.13:10:11.51#ibcon#read 3, iclass 12, count 2 2006.285.13:10:11.51#ibcon#about to read 4, iclass 12, count 2 2006.285.13:10:11.51#ibcon#read 4, iclass 12, count 2 2006.285.13:10:11.51#ibcon#about to read 5, iclass 12, count 2 2006.285.13:10:11.51#ibcon#read 5, iclass 12, count 2 2006.285.13:10:11.51#ibcon#about to read 6, iclass 12, count 2 2006.285.13:10:11.51#ibcon#read 6, iclass 12, count 2 2006.285.13:10:11.51#ibcon#end of sib2, iclass 12, count 2 2006.285.13:10:11.51#ibcon#*after write, iclass 12, count 2 2006.285.13:10:11.51#ibcon#*before return 0, iclass 12, count 2 2006.285.13:10:11.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:10:11.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:10:11.51#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.13:10:11.51#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:11.51#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:10:11.63#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:10:11.63#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:10:11.63#ibcon#enter wrdev, iclass 12, count 0 2006.285.13:10:11.63#ibcon#first serial, iclass 12, count 0 2006.285.13:10:11.63#ibcon#enter sib2, iclass 12, count 0 2006.285.13:10:11.63#ibcon#flushed, iclass 12, count 0 2006.285.13:10:11.63#ibcon#about to write, iclass 12, count 0 2006.285.13:10:11.63#ibcon#wrote, iclass 12, count 0 2006.285.13:10:11.63#ibcon#about to read 3, iclass 12, count 0 2006.285.13:10:11.65#ibcon#read 3, iclass 12, count 0 2006.285.13:10:11.65#ibcon#about to read 4, iclass 12, count 0 2006.285.13:10:11.65#ibcon#read 4, iclass 12, count 0 2006.285.13:10:11.65#ibcon#about to read 5, iclass 12, count 0 2006.285.13:10:11.65#ibcon#read 5, iclass 12, count 0 2006.285.13:10:11.65#ibcon#about to read 6, iclass 12, count 0 2006.285.13:10:11.65#ibcon#read 6, iclass 12, count 0 2006.285.13:10:11.65#ibcon#end of sib2, iclass 12, count 0 2006.285.13:10:11.65#ibcon#*mode == 0, iclass 12, count 0 2006.285.13:10:11.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.13:10:11.65#ibcon#[25=USB\r\n] 2006.285.13:10:11.65#ibcon#*before write, iclass 12, count 0 2006.285.13:10:11.65#ibcon#enter sib2, iclass 12, count 0 2006.285.13:10:11.65#ibcon#flushed, iclass 12, count 0 2006.285.13:10:11.65#ibcon#about to write, iclass 12, count 0 2006.285.13:10:11.65#ibcon#wrote, iclass 12, count 0 2006.285.13:10:11.65#ibcon#about to read 3, iclass 12, count 0 2006.285.13:10:11.68#ibcon#read 3, iclass 12, count 0 2006.285.13:10:11.68#ibcon#about to read 4, iclass 12, count 0 2006.285.13:10:11.68#ibcon#read 4, iclass 12, count 0 2006.285.13:10:11.68#ibcon#about to read 5, iclass 12, count 0 2006.285.13:10:11.68#ibcon#read 5, iclass 12, count 0 2006.285.13:10:11.68#ibcon#about to read 6, iclass 12, count 0 2006.285.13:10:11.68#ibcon#read 6, iclass 12, count 0 2006.285.13:10:11.68#ibcon#end of sib2, iclass 12, count 0 2006.285.13:10:11.68#ibcon#*after write, iclass 12, count 0 2006.285.13:10:11.68#ibcon#*before return 0, iclass 12, count 0 2006.285.13:10:11.68#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:10:11.68#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:10:11.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.13:10:11.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.13:10:11.68$vck44/valo=7,864.99 2006.285.13:10:11.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.13:10:11.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.13:10:11.68#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:11.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:10:11.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:10:11.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:10:11.68#ibcon#enter wrdev, iclass 14, count 0 2006.285.13:10:11.68#ibcon#first serial, iclass 14, count 0 2006.285.13:10:11.68#ibcon#enter sib2, iclass 14, count 0 2006.285.13:10:11.68#ibcon#flushed, iclass 14, count 0 2006.285.13:10:11.68#ibcon#about to write, iclass 14, count 0 2006.285.13:10:11.68#ibcon#wrote, iclass 14, count 0 2006.285.13:10:11.68#ibcon#about to read 3, iclass 14, count 0 2006.285.13:10:11.70#ibcon#read 3, iclass 14, count 0 2006.285.13:10:11.70#ibcon#about to read 4, iclass 14, count 0 2006.285.13:10:11.70#ibcon#read 4, iclass 14, count 0 2006.285.13:10:11.70#ibcon#about to read 5, iclass 14, count 0 2006.285.13:10:11.70#ibcon#read 5, iclass 14, count 0 2006.285.13:10:11.70#ibcon#about to read 6, iclass 14, count 0 2006.285.13:10:11.70#ibcon#read 6, iclass 14, count 0 2006.285.13:10:11.70#ibcon#end of sib2, iclass 14, count 0 2006.285.13:10:11.70#ibcon#*mode == 0, iclass 14, count 0 2006.285.13:10:11.70#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.13:10:11.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:10:11.70#ibcon#*before write, iclass 14, count 0 2006.285.13:10:11.70#ibcon#enter sib2, iclass 14, count 0 2006.285.13:10:11.70#ibcon#flushed, iclass 14, count 0 2006.285.13:10:11.70#ibcon#about to write, iclass 14, count 0 2006.285.13:10:11.70#ibcon#wrote, iclass 14, count 0 2006.285.13:10:11.70#ibcon#about to read 3, iclass 14, count 0 2006.285.13:10:11.74#ibcon#read 3, iclass 14, count 0 2006.285.13:10:11.74#ibcon#about to read 4, iclass 14, count 0 2006.285.13:10:11.74#ibcon#read 4, iclass 14, count 0 2006.285.13:10:11.74#ibcon#about to read 5, iclass 14, count 0 2006.285.13:10:11.74#ibcon#read 5, iclass 14, count 0 2006.285.13:10:11.74#ibcon#about to read 6, iclass 14, count 0 2006.285.13:10:11.74#ibcon#read 6, iclass 14, count 0 2006.285.13:10:11.74#ibcon#end of sib2, iclass 14, count 0 2006.285.13:10:11.74#ibcon#*after write, iclass 14, count 0 2006.285.13:10:11.74#ibcon#*before return 0, iclass 14, count 0 2006.285.13:10:11.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:10:11.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:10:11.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.13:10:11.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.13:10:11.74$vck44/va=7,4 2006.285.13:10:11.74#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.13:10:11.74#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.13:10:11.74#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:11.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:10:11.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:10:11.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:10:11.80#ibcon#enter wrdev, iclass 16, count 2 2006.285.13:10:11.80#ibcon#first serial, iclass 16, count 2 2006.285.13:10:11.80#ibcon#enter sib2, iclass 16, count 2 2006.285.13:10:11.80#ibcon#flushed, iclass 16, count 2 2006.285.13:10:11.80#ibcon#about to write, iclass 16, count 2 2006.285.13:10:11.80#ibcon#wrote, iclass 16, count 2 2006.285.13:10:11.80#ibcon#about to read 3, iclass 16, count 2 2006.285.13:10:11.82#ibcon#read 3, iclass 16, count 2 2006.285.13:10:11.82#ibcon#about to read 4, iclass 16, count 2 2006.285.13:10:11.82#ibcon#read 4, iclass 16, count 2 2006.285.13:10:11.82#ibcon#about to read 5, iclass 16, count 2 2006.285.13:10:11.82#ibcon#read 5, iclass 16, count 2 2006.285.13:10:11.82#ibcon#about to read 6, iclass 16, count 2 2006.285.13:10:11.82#ibcon#read 6, iclass 16, count 2 2006.285.13:10:11.82#ibcon#end of sib2, iclass 16, count 2 2006.285.13:10:11.82#ibcon#*mode == 0, iclass 16, count 2 2006.285.13:10:11.82#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.13:10:11.82#ibcon#[25=AT07-04\r\n] 2006.285.13:10:11.82#ibcon#*before write, iclass 16, count 2 2006.285.13:10:11.82#ibcon#enter sib2, iclass 16, count 2 2006.285.13:10:11.82#ibcon#flushed, iclass 16, count 2 2006.285.13:10:11.82#ibcon#about to write, iclass 16, count 2 2006.285.13:10:11.82#ibcon#wrote, iclass 16, count 2 2006.285.13:10:11.82#ibcon#about to read 3, iclass 16, count 2 2006.285.13:10:11.85#ibcon#read 3, iclass 16, count 2 2006.285.13:10:11.85#ibcon#about to read 4, iclass 16, count 2 2006.285.13:10:11.85#ibcon#read 4, iclass 16, count 2 2006.285.13:10:11.85#ibcon#about to read 5, iclass 16, count 2 2006.285.13:10:11.85#ibcon#read 5, iclass 16, count 2 2006.285.13:10:11.85#ibcon#about to read 6, iclass 16, count 2 2006.285.13:10:11.85#ibcon#read 6, iclass 16, count 2 2006.285.13:10:11.85#ibcon#end of sib2, iclass 16, count 2 2006.285.13:10:11.85#ibcon#*after write, iclass 16, count 2 2006.285.13:10:11.85#ibcon#*before return 0, iclass 16, count 2 2006.285.13:10:11.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:10:11.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:10:11.85#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.13:10:11.85#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:11.85#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:10:11.97#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:10:11.97#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:10:11.97#ibcon#enter wrdev, iclass 16, count 0 2006.285.13:10:11.97#ibcon#first serial, iclass 16, count 0 2006.285.13:10:11.97#ibcon#enter sib2, iclass 16, count 0 2006.285.13:10:11.97#ibcon#flushed, iclass 16, count 0 2006.285.13:10:11.97#ibcon#about to write, iclass 16, count 0 2006.285.13:10:11.97#ibcon#wrote, iclass 16, count 0 2006.285.13:10:11.97#ibcon#about to read 3, iclass 16, count 0 2006.285.13:10:11.99#ibcon#read 3, iclass 16, count 0 2006.285.13:10:11.99#ibcon#about to read 4, iclass 16, count 0 2006.285.13:10:11.99#ibcon#read 4, iclass 16, count 0 2006.285.13:10:11.99#ibcon#about to read 5, iclass 16, count 0 2006.285.13:10:11.99#ibcon#read 5, iclass 16, count 0 2006.285.13:10:11.99#ibcon#about to read 6, iclass 16, count 0 2006.285.13:10:11.99#ibcon#read 6, iclass 16, count 0 2006.285.13:10:11.99#ibcon#end of sib2, iclass 16, count 0 2006.285.13:10:11.99#ibcon#*mode == 0, iclass 16, count 0 2006.285.13:10:11.99#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.13:10:11.99#ibcon#[25=USB\r\n] 2006.285.13:10:11.99#ibcon#*before write, iclass 16, count 0 2006.285.13:10:11.99#ibcon#enter sib2, iclass 16, count 0 2006.285.13:10:11.99#ibcon#flushed, iclass 16, count 0 2006.285.13:10:11.99#ibcon#about to write, iclass 16, count 0 2006.285.13:10:11.99#ibcon#wrote, iclass 16, count 0 2006.285.13:10:11.99#ibcon#about to read 3, iclass 16, count 0 2006.285.13:10:12.02#ibcon#read 3, iclass 16, count 0 2006.285.13:10:12.02#ibcon#about to read 4, iclass 16, count 0 2006.285.13:10:12.02#ibcon#read 4, iclass 16, count 0 2006.285.13:10:12.02#ibcon#about to read 5, iclass 16, count 0 2006.285.13:10:12.02#ibcon#read 5, iclass 16, count 0 2006.285.13:10:12.02#ibcon#about to read 6, iclass 16, count 0 2006.285.13:10:12.02#ibcon#read 6, iclass 16, count 0 2006.285.13:10:12.02#ibcon#end of sib2, iclass 16, count 0 2006.285.13:10:12.02#ibcon#*after write, iclass 16, count 0 2006.285.13:10:12.02#ibcon#*before return 0, iclass 16, count 0 2006.285.13:10:12.02#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:10:12.02#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:10:12.02#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.13:10:12.02#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.13:10:12.02$vck44/valo=8,884.99 2006.285.13:10:12.02#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.13:10:12.02#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.13:10:12.02#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:12.02#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:10:12.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:10:12.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:10:12.02#ibcon#enter wrdev, iclass 18, count 0 2006.285.13:10:12.02#ibcon#first serial, iclass 18, count 0 2006.285.13:10:12.02#ibcon#enter sib2, iclass 18, count 0 2006.285.13:10:12.02#ibcon#flushed, iclass 18, count 0 2006.285.13:10:12.02#ibcon#about to write, iclass 18, count 0 2006.285.13:10:12.02#ibcon#wrote, iclass 18, count 0 2006.285.13:10:12.02#ibcon#about to read 3, iclass 18, count 0 2006.285.13:10:12.04#ibcon#read 3, iclass 18, count 0 2006.285.13:10:12.04#ibcon#about to read 4, iclass 18, count 0 2006.285.13:10:12.04#ibcon#read 4, iclass 18, count 0 2006.285.13:10:12.04#ibcon#about to read 5, iclass 18, count 0 2006.285.13:10:12.04#ibcon#read 5, iclass 18, count 0 2006.285.13:10:12.04#ibcon#about to read 6, iclass 18, count 0 2006.285.13:10:12.04#ibcon#read 6, iclass 18, count 0 2006.285.13:10:12.04#ibcon#end of sib2, iclass 18, count 0 2006.285.13:10:12.04#ibcon#*mode == 0, iclass 18, count 0 2006.285.13:10:12.04#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.13:10:12.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:10:12.04#ibcon#*before write, iclass 18, count 0 2006.285.13:10:12.04#ibcon#enter sib2, iclass 18, count 0 2006.285.13:10:12.04#ibcon#flushed, iclass 18, count 0 2006.285.13:10:12.04#ibcon#about to write, iclass 18, count 0 2006.285.13:10:12.04#ibcon#wrote, iclass 18, count 0 2006.285.13:10:12.04#ibcon#about to read 3, iclass 18, count 0 2006.285.13:10:12.08#ibcon#read 3, iclass 18, count 0 2006.285.13:10:12.08#ibcon#about to read 4, iclass 18, count 0 2006.285.13:10:12.08#ibcon#read 4, iclass 18, count 0 2006.285.13:10:12.08#ibcon#about to read 5, iclass 18, count 0 2006.285.13:10:12.08#ibcon#read 5, iclass 18, count 0 2006.285.13:10:12.08#ibcon#about to read 6, iclass 18, count 0 2006.285.13:10:12.08#ibcon#read 6, iclass 18, count 0 2006.285.13:10:12.08#ibcon#end of sib2, iclass 18, count 0 2006.285.13:10:12.08#ibcon#*after write, iclass 18, count 0 2006.285.13:10:12.08#ibcon#*before return 0, iclass 18, count 0 2006.285.13:10:12.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:10:12.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:10:12.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.13:10:12.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.13:10:12.08$vck44/va=8,3 2006.285.13:10:12.08#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.13:10:12.08#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.13:10:12.08#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:12.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:10:12.14#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:10:12.14#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:10:12.14#ibcon#enter wrdev, iclass 20, count 2 2006.285.13:10:12.14#ibcon#first serial, iclass 20, count 2 2006.285.13:10:12.14#ibcon#enter sib2, iclass 20, count 2 2006.285.13:10:12.14#ibcon#flushed, iclass 20, count 2 2006.285.13:10:12.14#ibcon#about to write, iclass 20, count 2 2006.285.13:10:12.14#ibcon#wrote, iclass 20, count 2 2006.285.13:10:12.14#ibcon#about to read 3, iclass 20, count 2 2006.285.13:10:12.16#ibcon#read 3, iclass 20, count 2 2006.285.13:10:12.16#ibcon#about to read 4, iclass 20, count 2 2006.285.13:10:12.16#ibcon#read 4, iclass 20, count 2 2006.285.13:10:12.16#ibcon#about to read 5, iclass 20, count 2 2006.285.13:10:12.16#ibcon#read 5, iclass 20, count 2 2006.285.13:10:12.16#ibcon#about to read 6, iclass 20, count 2 2006.285.13:10:12.16#ibcon#read 6, iclass 20, count 2 2006.285.13:10:12.16#ibcon#end of sib2, iclass 20, count 2 2006.285.13:10:12.16#ibcon#*mode == 0, iclass 20, count 2 2006.285.13:10:12.16#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.13:10:12.16#ibcon#[25=AT08-03\r\n] 2006.285.13:10:12.16#ibcon#*before write, iclass 20, count 2 2006.285.13:10:12.16#ibcon#enter sib2, iclass 20, count 2 2006.285.13:10:12.16#ibcon#flushed, iclass 20, count 2 2006.285.13:10:12.16#ibcon#about to write, iclass 20, count 2 2006.285.13:10:12.16#ibcon#wrote, iclass 20, count 2 2006.285.13:10:12.16#ibcon#about to read 3, iclass 20, count 2 2006.285.13:10:12.19#ibcon#read 3, iclass 20, count 2 2006.285.13:10:12.19#ibcon#about to read 4, iclass 20, count 2 2006.285.13:10:12.19#ibcon#read 4, iclass 20, count 2 2006.285.13:10:12.19#ibcon#about to read 5, iclass 20, count 2 2006.285.13:10:12.19#ibcon#read 5, iclass 20, count 2 2006.285.13:10:12.19#ibcon#about to read 6, iclass 20, count 2 2006.285.13:10:12.19#ibcon#read 6, iclass 20, count 2 2006.285.13:10:12.19#ibcon#end of sib2, iclass 20, count 2 2006.285.13:10:12.19#ibcon#*after write, iclass 20, count 2 2006.285.13:10:12.19#ibcon#*before return 0, iclass 20, count 2 2006.285.13:10:12.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:10:12.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:10:12.19#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.13:10:12.19#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:12.19#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:10:12.31#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:10:12.31#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:10:12.31#ibcon#enter wrdev, iclass 20, count 0 2006.285.13:10:12.31#ibcon#first serial, iclass 20, count 0 2006.285.13:10:12.31#ibcon#enter sib2, iclass 20, count 0 2006.285.13:10:12.31#ibcon#flushed, iclass 20, count 0 2006.285.13:10:12.31#ibcon#about to write, iclass 20, count 0 2006.285.13:10:12.31#ibcon#wrote, iclass 20, count 0 2006.285.13:10:12.31#ibcon#about to read 3, iclass 20, count 0 2006.285.13:10:12.33#ibcon#read 3, iclass 20, count 0 2006.285.13:10:12.33#ibcon#about to read 4, iclass 20, count 0 2006.285.13:10:12.33#ibcon#read 4, iclass 20, count 0 2006.285.13:10:12.33#ibcon#about to read 5, iclass 20, count 0 2006.285.13:10:12.33#ibcon#read 5, iclass 20, count 0 2006.285.13:10:12.33#ibcon#about to read 6, iclass 20, count 0 2006.285.13:10:12.33#ibcon#read 6, iclass 20, count 0 2006.285.13:10:12.33#ibcon#end of sib2, iclass 20, count 0 2006.285.13:10:12.33#ibcon#*mode == 0, iclass 20, count 0 2006.285.13:10:12.33#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.13:10:12.33#ibcon#[25=USB\r\n] 2006.285.13:10:12.33#ibcon#*before write, iclass 20, count 0 2006.285.13:10:12.33#ibcon#enter sib2, iclass 20, count 0 2006.285.13:10:12.33#ibcon#flushed, iclass 20, count 0 2006.285.13:10:12.33#ibcon#about to write, iclass 20, count 0 2006.285.13:10:12.33#ibcon#wrote, iclass 20, count 0 2006.285.13:10:12.33#ibcon#about to read 3, iclass 20, count 0 2006.285.13:10:12.36#ibcon#read 3, iclass 20, count 0 2006.285.13:10:12.36#ibcon#about to read 4, iclass 20, count 0 2006.285.13:10:12.36#ibcon#read 4, iclass 20, count 0 2006.285.13:10:12.36#ibcon#about to read 5, iclass 20, count 0 2006.285.13:10:12.36#ibcon#read 5, iclass 20, count 0 2006.285.13:10:12.36#ibcon#about to read 6, iclass 20, count 0 2006.285.13:10:12.36#ibcon#read 6, iclass 20, count 0 2006.285.13:10:12.36#ibcon#end of sib2, iclass 20, count 0 2006.285.13:10:12.36#ibcon#*after write, iclass 20, count 0 2006.285.13:10:12.36#ibcon#*before return 0, iclass 20, count 0 2006.285.13:10:12.36#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:10:12.36#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:10:12.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.13:10:12.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.13:10:12.36$vck44/vblo=1,629.99 2006.285.13:10:12.36#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.13:10:12.36#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.13:10:12.36#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:12.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:10:12.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:10:12.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:10:12.36#ibcon#enter wrdev, iclass 22, count 0 2006.285.13:10:12.36#ibcon#first serial, iclass 22, count 0 2006.285.13:10:12.36#ibcon#enter sib2, iclass 22, count 0 2006.285.13:10:12.36#ibcon#flushed, iclass 22, count 0 2006.285.13:10:12.36#ibcon#about to write, iclass 22, count 0 2006.285.13:10:12.36#ibcon#wrote, iclass 22, count 0 2006.285.13:10:12.36#ibcon#about to read 3, iclass 22, count 0 2006.285.13:10:12.38#ibcon#read 3, iclass 22, count 0 2006.285.13:10:12.38#ibcon#about to read 4, iclass 22, count 0 2006.285.13:10:12.38#ibcon#read 4, iclass 22, count 0 2006.285.13:10:12.38#ibcon#about to read 5, iclass 22, count 0 2006.285.13:10:12.38#ibcon#read 5, iclass 22, count 0 2006.285.13:10:12.38#ibcon#about to read 6, iclass 22, count 0 2006.285.13:10:12.38#ibcon#read 6, iclass 22, count 0 2006.285.13:10:12.38#ibcon#end of sib2, iclass 22, count 0 2006.285.13:10:12.38#ibcon#*mode == 0, iclass 22, count 0 2006.285.13:10:12.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.13:10:12.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:10:12.38#ibcon#*before write, iclass 22, count 0 2006.285.13:10:12.38#ibcon#enter sib2, iclass 22, count 0 2006.285.13:10:12.38#ibcon#flushed, iclass 22, count 0 2006.285.13:10:12.38#ibcon#about to write, iclass 22, count 0 2006.285.13:10:12.38#ibcon#wrote, iclass 22, count 0 2006.285.13:10:12.38#ibcon#about to read 3, iclass 22, count 0 2006.285.13:10:12.42#ibcon#read 3, iclass 22, count 0 2006.285.13:10:12.42#ibcon#about to read 4, iclass 22, count 0 2006.285.13:10:12.42#ibcon#read 4, iclass 22, count 0 2006.285.13:10:12.42#ibcon#about to read 5, iclass 22, count 0 2006.285.13:10:12.42#ibcon#read 5, iclass 22, count 0 2006.285.13:10:12.42#ibcon#about to read 6, iclass 22, count 0 2006.285.13:10:12.42#ibcon#read 6, iclass 22, count 0 2006.285.13:10:12.42#ibcon#end of sib2, iclass 22, count 0 2006.285.13:10:12.42#ibcon#*after write, iclass 22, count 0 2006.285.13:10:12.42#ibcon#*before return 0, iclass 22, count 0 2006.285.13:10:12.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:10:12.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:10:12.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.13:10:12.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.13:10:12.42$vck44/vb=1,4 2006.285.13:10:12.42#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.13:10:12.42#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.13:10:12.42#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:12.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:10:12.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:10:12.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:10:12.42#ibcon#enter wrdev, iclass 24, count 2 2006.285.13:10:12.42#ibcon#first serial, iclass 24, count 2 2006.285.13:10:12.42#ibcon#enter sib2, iclass 24, count 2 2006.285.13:10:12.42#ibcon#flushed, iclass 24, count 2 2006.285.13:10:12.42#ibcon#about to write, iclass 24, count 2 2006.285.13:10:12.42#ibcon#wrote, iclass 24, count 2 2006.285.13:10:12.42#ibcon#about to read 3, iclass 24, count 2 2006.285.13:10:12.44#ibcon#read 3, iclass 24, count 2 2006.285.13:10:12.44#ibcon#about to read 4, iclass 24, count 2 2006.285.13:10:12.44#ibcon#read 4, iclass 24, count 2 2006.285.13:10:12.44#ibcon#about to read 5, iclass 24, count 2 2006.285.13:10:12.44#ibcon#read 5, iclass 24, count 2 2006.285.13:10:12.44#ibcon#about to read 6, iclass 24, count 2 2006.285.13:10:12.44#ibcon#read 6, iclass 24, count 2 2006.285.13:10:12.44#ibcon#end of sib2, iclass 24, count 2 2006.285.13:10:12.44#ibcon#*mode == 0, iclass 24, count 2 2006.285.13:10:12.44#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.13:10:12.44#ibcon#[27=AT01-04\r\n] 2006.285.13:10:12.44#ibcon#*before write, iclass 24, count 2 2006.285.13:10:12.44#ibcon#enter sib2, iclass 24, count 2 2006.285.13:10:12.44#ibcon#flushed, iclass 24, count 2 2006.285.13:10:12.44#ibcon#about to write, iclass 24, count 2 2006.285.13:10:12.44#ibcon#wrote, iclass 24, count 2 2006.285.13:10:12.44#ibcon#about to read 3, iclass 24, count 2 2006.285.13:10:12.47#ibcon#read 3, iclass 24, count 2 2006.285.13:10:12.47#ibcon#about to read 4, iclass 24, count 2 2006.285.13:10:12.47#ibcon#read 4, iclass 24, count 2 2006.285.13:10:12.47#ibcon#about to read 5, iclass 24, count 2 2006.285.13:10:12.47#ibcon#read 5, iclass 24, count 2 2006.285.13:10:12.47#ibcon#about to read 6, iclass 24, count 2 2006.285.13:10:12.47#ibcon#read 6, iclass 24, count 2 2006.285.13:10:12.47#ibcon#end of sib2, iclass 24, count 2 2006.285.13:10:12.47#ibcon#*after write, iclass 24, count 2 2006.285.13:10:12.47#ibcon#*before return 0, iclass 24, count 2 2006.285.13:10:12.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:10:12.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:10:12.47#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.13:10:12.47#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:12.47#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:10:12.59#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:10:12.59#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:10:12.59#ibcon#enter wrdev, iclass 24, count 0 2006.285.13:10:12.59#ibcon#first serial, iclass 24, count 0 2006.285.13:10:12.59#ibcon#enter sib2, iclass 24, count 0 2006.285.13:10:12.59#ibcon#flushed, iclass 24, count 0 2006.285.13:10:12.59#ibcon#about to write, iclass 24, count 0 2006.285.13:10:12.59#ibcon#wrote, iclass 24, count 0 2006.285.13:10:12.59#ibcon#about to read 3, iclass 24, count 0 2006.285.13:10:12.61#ibcon#read 3, iclass 24, count 0 2006.285.13:10:12.61#ibcon#about to read 4, iclass 24, count 0 2006.285.13:10:12.61#ibcon#read 4, iclass 24, count 0 2006.285.13:10:12.61#ibcon#about to read 5, iclass 24, count 0 2006.285.13:10:12.61#ibcon#read 5, iclass 24, count 0 2006.285.13:10:12.61#ibcon#about to read 6, iclass 24, count 0 2006.285.13:10:12.61#ibcon#read 6, iclass 24, count 0 2006.285.13:10:12.61#ibcon#end of sib2, iclass 24, count 0 2006.285.13:10:12.61#ibcon#*mode == 0, iclass 24, count 0 2006.285.13:10:12.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.13:10:12.61#ibcon#[27=USB\r\n] 2006.285.13:10:12.61#ibcon#*before write, iclass 24, count 0 2006.285.13:10:12.61#ibcon#enter sib2, iclass 24, count 0 2006.285.13:10:12.61#ibcon#flushed, iclass 24, count 0 2006.285.13:10:12.61#ibcon#about to write, iclass 24, count 0 2006.285.13:10:12.61#ibcon#wrote, iclass 24, count 0 2006.285.13:10:12.61#ibcon#about to read 3, iclass 24, count 0 2006.285.13:10:12.64#ibcon#read 3, iclass 24, count 0 2006.285.13:10:12.64#ibcon#about to read 4, iclass 24, count 0 2006.285.13:10:12.64#ibcon#read 4, iclass 24, count 0 2006.285.13:10:12.64#ibcon#about to read 5, iclass 24, count 0 2006.285.13:10:12.64#ibcon#read 5, iclass 24, count 0 2006.285.13:10:12.64#ibcon#about to read 6, iclass 24, count 0 2006.285.13:10:12.64#ibcon#read 6, iclass 24, count 0 2006.285.13:10:12.64#ibcon#end of sib2, iclass 24, count 0 2006.285.13:10:12.64#ibcon#*after write, iclass 24, count 0 2006.285.13:10:12.64#ibcon#*before return 0, iclass 24, count 0 2006.285.13:10:12.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:10:12.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:10:12.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.13:10:12.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.13:10:12.64$vck44/vblo=2,634.99 2006.285.13:10:12.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.13:10:12.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.13:10:12.64#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:12.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:10:12.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:10:12.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:10:12.64#ibcon#enter wrdev, iclass 26, count 0 2006.285.13:10:12.64#ibcon#first serial, iclass 26, count 0 2006.285.13:10:12.64#ibcon#enter sib2, iclass 26, count 0 2006.285.13:10:12.64#ibcon#flushed, iclass 26, count 0 2006.285.13:10:12.64#ibcon#about to write, iclass 26, count 0 2006.285.13:10:12.64#ibcon#wrote, iclass 26, count 0 2006.285.13:10:12.64#ibcon#about to read 3, iclass 26, count 0 2006.285.13:10:12.66#ibcon#read 3, iclass 26, count 0 2006.285.13:10:12.66#ibcon#about to read 4, iclass 26, count 0 2006.285.13:10:12.66#ibcon#read 4, iclass 26, count 0 2006.285.13:10:12.66#ibcon#about to read 5, iclass 26, count 0 2006.285.13:10:12.66#ibcon#read 5, iclass 26, count 0 2006.285.13:10:12.66#ibcon#about to read 6, iclass 26, count 0 2006.285.13:10:12.66#ibcon#read 6, iclass 26, count 0 2006.285.13:10:12.66#ibcon#end of sib2, iclass 26, count 0 2006.285.13:10:12.66#ibcon#*mode == 0, iclass 26, count 0 2006.285.13:10:12.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.13:10:12.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:10:12.66#ibcon#*before write, iclass 26, count 0 2006.285.13:10:12.66#ibcon#enter sib2, iclass 26, count 0 2006.285.13:10:12.66#ibcon#flushed, iclass 26, count 0 2006.285.13:10:12.66#ibcon#about to write, iclass 26, count 0 2006.285.13:10:12.66#ibcon#wrote, iclass 26, count 0 2006.285.13:10:12.66#ibcon#about to read 3, iclass 26, count 0 2006.285.13:10:12.70#ibcon#read 3, iclass 26, count 0 2006.285.13:10:12.70#ibcon#about to read 4, iclass 26, count 0 2006.285.13:10:12.70#ibcon#read 4, iclass 26, count 0 2006.285.13:10:12.70#ibcon#about to read 5, iclass 26, count 0 2006.285.13:10:12.70#ibcon#read 5, iclass 26, count 0 2006.285.13:10:12.70#ibcon#about to read 6, iclass 26, count 0 2006.285.13:10:12.70#ibcon#read 6, iclass 26, count 0 2006.285.13:10:12.70#ibcon#end of sib2, iclass 26, count 0 2006.285.13:10:12.70#ibcon#*after write, iclass 26, count 0 2006.285.13:10:12.70#ibcon#*before return 0, iclass 26, count 0 2006.285.13:10:12.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:10:12.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:10:12.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.13:10:12.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.13:10:12.70$vck44/vb=2,5 2006.285.13:10:12.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.13:10:12.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.13:10:12.70#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:12.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:10:12.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:10:12.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:10:12.76#ibcon#enter wrdev, iclass 28, count 2 2006.285.13:10:12.76#ibcon#first serial, iclass 28, count 2 2006.285.13:10:12.76#ibcon#enter sib2, iclass 28, count 2 2006.285.13:10:12.76#ibcon#flushed, iclass 28, count 2 2006.285.13:10:12.76#ibcon#about to write, iclass 28, count 2 2006.285.13:10:12.76#ibcon#wrote, iclass 28, count 2 2006.285.13:10:12.76#ibcon#about to read 3, iclass 28, count 2 2006.285.13:10:12.78#ibcon#read 3, iclass 28, count 2 2006.285.13:10:12.78#ibcon#about to read 4, iclass 28, count 2 2006.285.13:10:12.78#ibcon#read 4, iclass 28, count 2 2006.285.13:10:12.78#ibcon#about to read 5, iclass 28, count 2 2006.285.13:10:12.78#ibcon#read 5, iclass 28, count 2 2006.285.13:10:12.78#ibcon#about to read 6, iclass 28, count 2 2006.285.13:10:12.78#ibcon#read 6, iclass 28, count 2 2006.285.13:10:12.78#ibcon#end of sib2, iclass 28, count 2 2006.285.13:10:12.78#ibcon#*mode == 0, iclass 28, count 2 2006.285.13:10:12.78#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.13:10:12.78#ibcon#[27=AT02-05\r\n] 2006.285.13:10:12.78#ibcon#*before write, iclass 28, count 2 2006.285.13:10:12.78#ibcon#enter sib2, iclass 28, count 2 2006.285.13:10:12.78#ibcon#flushed, iclass 28, count 2 2006.285.13:10:12.78#ibcon#about to write, iclass 28, count 2 2006.285.13:10:12.78#ibcon#wrote, iclass 28, count 2 2006.285.13:10:12.78#ibcon#about to read 3, iclass 28, count 2 2006.285.13:10:12.81#ibcon#read 3, iclass 28, count 2 2006.285.13:10:12.81#ibcon#about to read 4, iclass 28, count 2 2006.285.13:10:12.81#ibcon#read 4, iclass 28, count 2 2006.285.13:10:12.81#ibcon#about to read 5, iclass 28, count 2 2006.285.13:10:12.81#ibcon#read 5, iclass 28, count 2 2006.285.13:10:12.81#ibcon#about to read 6, iclass 28, count 2 2006.285.13:10:12.81#ibcon#read 6, iclass 28, count 2 2006.285.13:10:12.81#ibcon#end of sib2, iclass 28, count 2 2006.285.13:10:12.81#ibcon#*after write, iclass 28, count 2 2006.285.13:10:12.81#ibcon#*before return 0, iclass 28, count 2 2006.285.13:10:12.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:10:12.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:10:12.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.13:10:12.81#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:12.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:10:12.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:10:12.93#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:10:12.93#ibcon#enter wrdev, iclass 28, count 0 2006.285.13:10:12.93#ibcon#first serial, iclass 28, count 0 2006.285.13:10:12.93#ibcon#enter sib2, iclass 28, count 0 2006.285.13:10:12.93#ibcon#flushed, iclass 28, count 0 2006.285.13:10:12.93#ibcon#about to write, iclass 28, count 0 2006.285.13:10:12.93#ibcon#wrote, iclass 28, count 0 2006.285.13:10:12.93#ibcon#about to read 3, iclass 28, count 0 2006.285.13:10:12.95#ibcon#read 3, iclass 28, count 0 2006.285.13:10:12.95#ibcon#about to read 4, iclass 28, count 0 2006.285.13:10:12.95#ibcon#read 4, iclass 28, count 0 2006.285.13:10:12.95#ibcon#about to read 5, iclass 28, count 0 2006.285.13:10:12.95#ibcon#read 5, iclass 28, count 0 2006.285.13:10:12.95#ibcon#about to read 6, iclass 28, count 0 2006.285.13:10:12.95#ibcon#read 6, iclass 28, count 0 2006.285.13:10:12.95#ibcon#end of sib2, iclass 28, count 0 2006.285.13:10:12.95#ibcon#*mode == 0, iclass 28, count 0 2006.285.13:10:12.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.13:10:12.95#ibcon#[27=USB\r\n] 2006.285.13:10:12.95#ibcon#*before write, iclass 28, count 0 2006.285.13:10:12.95#ibcon#enter sib2, iclass 28, count 0 2006.285.13:10:12.95#ibcon#flushed, iclass 28, count 0 2006.285.13:10:12.95#ibcon#about to write, iclass 28, count 0 2006.285.13:10:12.95#ibcon#wrote, iclass 28, count 0 2006.285.13:10:12.95#ibcon#about to read 3, iclass 28, count 0 2006.285.13:10:12.98#ibcon#read 3, iclass 28, count 0 2006.285.13:10:12.98#ibcon#about to read 4, iclass 28, count 0 2006.285.13:10:12.98#ibcon#read 4, iclass 28, count 0 2006.285.13:10:12.98#ibcon#about to read 5, iclass 28, count 0 2006.285.13:10:12.98#ibcon#read 5, iclass 28, count 0 2006.285.13:10:12.98#ibcon#about to read 6, iclass 28, count 0 2006.285.13:10:12.98#ibcon#read 6, iclass 28, count 0 2006.285.13:10:12.98#ibcon#end of sib2, iclass 28, count 0 2006.285.13:10:12.98#ibcon#*after write, iclass 28, count 0 2006.285.13:10:12.98#ibcon#*before return 0, iclass 28, count 0 2006.285.13:10:12.98#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:10:12.98#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:10:12.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.13:10:12.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.13:10:12.98$vck44/vblo=3,649.99 2006.285.13:10:12.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.13:10:12.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.13:10:12.98#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:12.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:10:12.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:10:12.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:10:12.98#ibcon#enter wrdev, iclass 30, count 0 2006.285.13:10:12.98#ibcon#first serial, iclass 30, count 0 2006.285.13:10:12.98#ibcon#enter sib2, iclass 30, count 0 2006.285.13:10:12.98#ibcon#flushed, iclass 30, count 0 2006.285.13:10:12.98#ibcon#about to write, iclass 30, count 0 2006.285.13:10:12.98#ibcon#wrote, iclass 30, count 0 2006.285.13:10:12.98#ibcon#about to read 3, iclass 30, count 0 2006.285.13:10:13.00#ibcon#read 3, iclass 30, count 0 2006.285.13:10:13.00#ibcon#about to read 4, iclass 30, count 0 2006.285.13:10:13.00#ibcon#read 4, iclass 30, count 0 2006.285.13:10:13.00#ibcon#about to read 5, iclass 30, count 0 2006.285.13:10:13.00#ibcon#read 5, iclass 30, count 0 2006.285.13:10:13.00#ibcon#about to read 6, iclass 30, count 0 2006.285.13:10:13.00#ibcon#read 6, iclass 30, count 0 2006.285.13:10:13.00#ibcon#end of sib2, iclass 30, count 0 2006.285.13:10:13.00#ibcon#*mode == 0, iclass 30, count 0 2006.285.13:10:13.00#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.13:10:13.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:10:13.00#ibcon#*before write, iclass 30, count 0 2006.285.13:10:13.00#ibcon#enter sib2, iclass 30, count 0 2006.285.13:10:13.00#ibcon#flushed, iclass 30, count 0 2006.285.13:10:13.00#ibcon#about to write, iclass 30, count 0 2006.285.13:10:13.00#ibcon#wrote, iclass 30, count 0 2006.285.13:10:13.00#ibcon#about to read 3, iclass 30, count 0 2006.285.13:10:13.04#ibcon#read 3, iclass 30, count 0 2006.285.13:10:13.04#ibcon#about to read 4, iclass 30, count 0 2006.285.13:10:13.04#ibcon#read 4, iclass 30, count 0 2006.285.13:10:13.04#ibcon#about to read 5, iclass 30, count 0 2006.285.13:10:13.04#ibcon#read 5, iclass 30, count 0 2006.285.13:10:13.04#ibcon#about to read 6, iclass 30, count 0 2006.285.13:10:13.04#ibcon#read 6, iclass 30, count 0 2006.285.13:10:13.04#ibcon#end of sib2, iclass 30, count 0 2006.285.13:10:13.04#ibcon#*after write, iclass 30, count 0 2006.285.13:10:13.04#ibcon#*before return 0, iclass 30, count 0 2006.285.13:10:13.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:10:13.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:10:13.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.13:10:13.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.13:10:13.04$vck44/vb=3,4 2006.285.13:10:13.04#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.13:10:13.04#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.13:10:13.04#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:13.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:10:13.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:10:13.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:10:13.10#ibcon#enter wrdev, iclass 32, count 2 2006.285.13:10:13.10#ibcon#first serial, iclass 32, count 2 2006.285.13:10:13.10#ibcon#enter sib2, iclass 32, count 2 2006.285.13:10:13.10#ibcon#flushed, iclass 32, count 2 2006.285.13:10:13.10#ibcon#about to write, iclass 32, count 2 2006.285.13:10:13.10#ibcon#wrote, iclass 32, count 2 2006.285.13:10:13.10#ibcon#about to read 3, iclass 32, count 2 2006.285.13:10:13.12#ibcon#read 3, iclass 32, count 2 2006.285.13:10:13.12#ibcon#about to read 4, iclass 32, count 2 2006.285.13:10:13.12#ibcon#read 4, iclass 32, count 2 2006.285.13:10:13.12#ibcon#about to read 5, iclass 32, count 2 2006.285.13:10:13.12#ibcon#read 5, iclass 32, count 2 2006.285.13:10:13.12#ibcon#about to read 6, iclass 32, count 2 2006.285.13:10:13.12#ibcon#read 6, iclass 32, count 2 2006.285.13:10:13.12#ibcon#end of sib2, iclass 32, count 2 2006.285.13:10:13.12#ibcon#*mode == 0, iclass 32, count 2 2006.285.13:10:13.12#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.13:10:13.12#ibcon#[27=AT03-04\r\n] 2006.285.13:10:13.12#ibcon#*before write, iclass 32, count 2 2006.285.13:10:13.12#ibcon#enter sib2, iclass 32, count 2 2006.285.13:10:13.12#ibcon#flushed, iclass 32, count 2 2006.285.13:10:13.12#ibcon#about to write, iclass 32, count 2 2006.285.13:10:13.12#ibcon#wrote, iclass 32, count 2 2006.285.13:10:13.12#ibcon#about to read 3, iclass 32, count 2 2006.285.13:10:13.15#ibcon#read 3, iclass 32, count 2 2006.285.13:10:13.15#ibcon#about to read 4, iclass 32, count 2 2006.285.13:10:13.15#ibcon#read 4, iclass 32, count 2 2006.285.13:10:13.15#ibcon#about to read 5, iclass 32, count 2 2006.285.13:10:13.15#ibcon#read 5, iclass 32, count 2 2006.285.13:10:13.15#ibcon#about to read 6, iclass 32, count 2 2006.285.13:10:13.15#ibcon#read 6, iclass 32, count 2 2006.285.13:10:13.15#ibcon#end of sib2, iclass 32, count 2 2006.285.13:10:13.15#ibcon#*after write, iclass 32, count 2 2006.285.13:10:13.15#ibcon#*before return 0, iclass 32, count 2 2006.285.13:10:13.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:10:13.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:10:13.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.13:10:13.15#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:13.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:10:13.27#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:10:13.27#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:10:13.27#ibcon#enter wrdev, iclass 32, count 0 2006.285.13:10:13.27#ibcon#first serial, iclass 32, count 0 2006.285.13:10:13.27#ibcon#enter sib2, iclass 32, count 0 2006.285.13:10:13.27#ibcon#flushed, iclass 32, count 0 2006.285.13:10:13.27#ibcon#about to write, iclass 32, count 0 2006.285.13:10:13.27#ibcon#wrote, iclass 32, count 0 2006.285.13:10:13.27#ibcon#about to read 3, iclass 32, count 0 2006.285.13:10:13.29#ibcon#read 3, iclass 32, count 0 2006.285.13:10:13.29#ibcon#about to read 4, iclass 32, count 0 2006.285.13:10:13.29#ibcon#read 4, iclass 32, count 0 2006.285.13:10:13.29#ibcon#about to read 5, iclass 32, count 0 2006.285.13:10:13.29#ibcon#read 5, iclass 32, count 0 2006.285.13:10:13.29#ibcon#about to read 6, iclass 32, count 0 2006.285.13:10:13.29#ibcon#read 6, iclass 32, count 0 2006.285.13:10:13.29#ibcon#end of sib2, iclass 32, count 0 2006.285.13:10:13.29#ibcon#*mode == 0, iclass 32, count 0 2006.285.13:10:13.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.13:10:13.29#ibcon#[27=USB\r\n] 2006.285.13:10:13.29#ibcon#*before write, iclass 32, count 0 2006.285.13:10:13.29#ibcon#enter sib2, iclass 32, count 0 2006.285.13:10:13.29#ibcon#flushed, iclass 32, count 0 2006.285.13:10:13.29#ibcon#about to write, iclass 32, count 0 2006.285.13:10:13.29#ibcon#wrote, iclass 32, count 0 2006.285.13:10:13.29#ibcon#about to read 3, iclass 32, count 0 2006.285.13:10:13.32#ibcon#read 3, iclass 32, count 0 2006.285.13:10:13.32#ibcon#about to read 4, iclass 32, count 0 2006.285.13:10:13.32#ibcon#read 4, iclass 32, count 0 2006.285.13:10:13.32#ibcon#about to read 5, iclass 32, count 0 2006.285.13:10:13.32#ibcon#read 5, iclass 32, count 0 2006.285.13:10:13.32#ibcon#about to read 6, iclass 32, count 0 2006.285.13:10:13.32#ibcon#read 6, iclass 32, count 0 2006.285.13:10:13.32#ibcon#end of sib2, iclass 32, count 0 2006.285.13:10:13.32#ibcon#*after write, iclass 32, count 0 2006.285.13:10:13.32#ibcon#*before return 0, iclass 32, count 0 2006.285.13:10:13.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:10:13.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:10:13.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.13:10:13.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.13:10:13.32$vck44/vblo=4,679.99 2006.285.13:10:13.38#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.13:10:13.38#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.13:10:13.38#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:13.38#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:10:13.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:10:13.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:10:13.38#ibcon#enter wrdev, iclass 34, count 0 2006.285.13:10:13.38#ibcon#first serial, iclass 34, count 0 2006.285.13:10:13.38#ibcon#enter sib2, iclass 34, count 0 2006.285.13:10:13.38#ibcon#flushed, iclass 34, count 0 2006.285.13:10:13.38#ibcon#about to write, iclass 34, count 0 2006.285.13:10:13.38#ibcon#wrote, iclass 34, count 0 2006.285.13:10:13.38#ibcon#about to read 3, iclass 34, count 0 2006.285.13:10:13.39#ibcon#read 3, iclass 34, count 0 2006.285.13:10:13.39#ibcon#about to read 4, iclass 34, count 0 2006.285.13:10:13.39#ibcon#read 4, iclass 34, count 0 2006.285.13:10:13.39#ibcon#about to read 5, iclass 34, count 0 2006.285.13:10:13.39#ibcon#read 5, iclass 34, count 0 2006.285.13:10:13.39#ibcon#about to read 6, iclass 34, count 0 2006.285.13:10:13.39#ibcon#read 6, iclass 34, count 0 2006.285.13:10:13.39#ibcon#end of sib2, iclass 34, count 0 2006.285.13:10:13.39#ibcon#*mode == 0, iclass 34, count 0 2006.285.13:10:13.39#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.13:10:13.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:10:13.39#ibcon#*before write, iclass 34, count 0 2006.285.13:10:13.39#ibcon#enter sib2, iclass 34, count 0 2006.285.13:10:13.39#ibcon#flushed, iclass 34, count 0 2006.285.13:10:13.39#ibcon#about to write, iclass 34, count 0 2006.285.13:10:13.39#ibcon#wrote, iclass 34, count 0 2006.285.13:10:13.39#ibcon#about to read 3, iclass 34, count 0 2006.285.13:10:13.43#ibcon#read 3, iclass 34, count 0 2006.285.13:10:13.43#ibcon#about to read 4, iclass 34, count 0 2006.285.13:10:13.43#ibcon#read 4, iclass 34, count 0 2006.285.13:10:13.43#ibcon#about to read 5, iclass 34, count 0 2006.285.13:10:13.43#ibcon#read 5, iclass 34, count 0 2006.285.13:10:13.43#ibcon#about to read 6, iclass 34, count 0 2006.285.13:10:13.43#ibcon#read 6, iclass 34, count 0 2006.285.13:10:13.43#ibcon#end of sib2, iclass 34, count 0 2006.285.13:10:13.43#ibcon#*after write, iclass 34, count 0 2006.285.13:10:13.43#ibcon#*before return 0, iclass 34, count 0 2006.285.13:10:13.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:10:13.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:10:13.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.13:10:13.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.13:10:13.43$vck44/vb=4,5 2006.285.13:10:13.43#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.13:10:13.43#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.13:10:13.43#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:13.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:10:13.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:10:13.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:10:13.43#ibcon#enter wrdev, iclass 36, count 2 2006.285.13:10:13.43#ibcon#first serial, iclass 36, count 2 2006.285.13:10:13.43#ibcon#enter sib2, iclass 36, count 2 2006.285.13:10:13.43#ibcon#flushed, iclass 36, count 2 2006.285.13:10:13.43#ibcon#about to write, iclass 36, count 2 2006.285.13:10:13.43#ibcon#wrote, iclass 36, count 2 2006.285.13:10:13.43#ibcon#about to read 3, iclass 36, count 2 2006.285.13:10:13.45#ibcon#read 3, iclass 36, count 2 2006.285.13:10:13.45#ibcon#about to read 4, iclass 36, count 2 2006.285.13:10:13.45#ibcon#read 4, iclass 36, count 2 2006.285.13:10:13.45#ibcon#about to read 5, iclass 36, count 2 2006.285.13:10:13.45#ibcon#read 5, iclass 36, count 2 2006.285.13:10:13.45#ibcon#about to read 6, iclass 36, count 2 2006.285.13:10:13.45#ibcon#read 6, iclass 36, count 2 2006.285.13:10:13.45#ibcon#end of sib2, iclass 36, count 2 2006.285.13:10:13.45#ibcon#*mode == 0, iclass 36, count 2 2006.285.13:10:13.45#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.13:10:13.45#ibcon#[27=AT04-05\r\n] 2006.285.13:10:13.45#ibcon#*before write, iclass 36, count 2 2006.285.13:10:13.45#ibcon#enter sib2, iclass 36, count 2 2006.285.13:10:13.45#ibcon#flushed, iclass 36, count 2 2006.285.13:10:13.45#ibcon#about to write, iclass 36, count 2 2006.285.13:10:13.45#ibcon#wrote, iclass 36, count 2 2006.285.13:10:13.45#ibcon#about to read 3, iclass 36, count 2 2006.285.13:10:13.48#ibcon#read 3, iclass 36, count 2 2006.285.13:10:13.48#ibcon#about to read 4, iclass 36, count 2 2006.285.13:10:13.48#ibcon#read 4, iclass 36, count 2 2006.285.13:10:13.48#ibcon#about to read 5, iclass 36, count 2 2006.285.13:10:13.48#ibcon#read 5, iclass 36, count 2 2006.285.13:10:13.48#ibcon#about to read 6, iclass 36, count 2 2006.285.13:10:13.48#ibcon#read 6, iclass 36, count 2 2006.285.13:10:13.48#ibcon#end of sib2, iclass 36, count 2 2006.285.13:10:13.48#ibcon#*after write, iclass 36, count 2 2006.285.13:10:13.48#ibcon#*before return 0, iclass 36, count 2 2006.285.13:10:13.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:10:13.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:10:13.48#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.13:10:13.48#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:13.48#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:10:13.60#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:10:13.60#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:10:13.60#ibcon#enter wrdev, iclass 36, count 0 2006.285.13:10:13.60#ibcon#first serial, iclass 36, count 0 2006.285.13:10:13.60#ibcon#enter sib2, iclass 36, count 0 2006.285.13:10:13.60#ibcon#flushed, iclass 36, count 0 2006.285.13:10:13.60#ibcon#about to write, iclass 36, count 0 2006.285.13:10:13.60#ibcon#wrote, iclass 36, count 0 2006.285.13:10:13.60#ibcon#about to read 3, iclass 36, count 0 2006.285.13:10:13.62#ibcon#read 3, iclass 36, count 0 2006.285.13:10:13.62#ibcon#about to read 4, iclass 36, count 0 2006.285.13:10:13.62#ibcon#read 4, iclass 36, count 0 2006.285.13:10:13.62#ibcon#about to read 5, iclass 36, count 0 2006.285.13:10:13.62#ibcon#read 5, iclass 36, count 0 2006.285.13:10:13.62#ibcon#about to read 6, iclass 36, count 0 2006.285.13:10:13.62#ibcon#read 6, iclass 36, count 0 2006.285.13:10:13.62#ibcon#end of sib2, iclass 36, count 0 2006.285.13:10:13.62#ibcon#*mode == 0, iclass 36, count 0 2006.285.13:10:13.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.13:10:13.62#ibcon#[27=USB\r\n] 2006.285.13:10:13.62#ibcon#*before write, iclass 36, count 0 2006.285.13:10:13.62#ibcon#enter sib2, iclass 36, count 0 2006.285.13:10:13.62#ibcon#flushed, iclass 36, count 0 2006.285.13:10:13.62#ibcon#about to write, iclass 36, count 0 2006.285.13:10:13.62#ibcon#wrote, iclass 36, count 0 2006.285.13:10:13.62#ibcon#about to read 3, iclass 36, count 0 2006.285.13:10:13.65#ibcon#read 3, iclass 36, count 0 2006.285.13:10:13.65#ibcon#about to read 4, iclass 36, count 0 2006.285.13:10:13.65#ibcon#read 4, iclass 36, count 0 2006.285.13:10:13.65#ibcon#about to read 5, iclass 36, count 0 2006.285.13:10:13.65#ibcon#read 5, iclass 36, count 0 2006.285.13:10:13.65#ibcon#about to read 6, iclass 36, count 0 2006.285.13:10:13.65#ibcon#read 6, iclass 36, count 0 2006.285.13:10:13.65#ibcon#end of sib2, iclass 36, count 0 2006.285.13:10:13.65#ibcon#*after write, iclass 36, count 0 2006.285.13:10:13.65#ibcon#*before return 0, iclass 36, count 0 2006.285.13:10:13.65#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:10:13.65#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:10:13.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.13:10:13.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.13:10:13.65$vck44/vblo=5,709.99 2006.285.13:10:13.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.13:10:13.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.13:10:13.65#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:13.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:10:13.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:10:13.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:10:13.65#ibcon#enter wrdev, iclass 38, count 0 2006.285.13:10:13.65#ibcon#first serial, iclass 38, count 0 2006.285.13:10:13.65#ibcon#enter sib2, iclass 38, count 0 2006.285.13:10:13.65#ibcon#flushed, iclass 38, count 0 2006.285.13:10:13.65#ibcon#about to write, iclass 38, count 0 2006.285.13:10:13.65#ibcon#wrote, iclass 38, count 0 2006.285.13:10:13.65#ibcon#about to read 3, iclass 38, count 0 2006.285.13:10:13.67#ibcon#read 3, iclass 38, count 0 2006.285.13:10:13.67#ibcon#about to read 4, iclass 38, count 0 2006.285.13:10:13.67#ibcon#read 4, iclass 38, count 0 2006.285.13:10:13.67#ibcon#about to read 5, iclass 38, count 0 2006.285.13:10:13.67#ibcon#read 5, iclass 38, count 0 2006.285.13:10:13.67#ibcon#about to read 6, iclass 38, count 0 2006.285.13:10:13.67#ibcon#read 6, iclass 38, count 0 2006.285.13:10:13.67#ibcon#end of sib2, iclass 38, count 0 2006.285.13:10:13.67#ibcon#*mode == 0, iclass 38, count 0 2006.285.13:10:13.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.13:10:13.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:10:13.67#ibcon#*before write, iclass 38, count 0 2006.285.13:10:13.67#ibcon#enter sib2, iclass 38, count 0 2006.285.13:10:13.67#ibcon#flushed, iclass 38, count 0 2006.285.13:10:13.67#ibcon#about to write, iclass 38, count 0 2006.285.13:10:13.67#ibcon#wrote, iclass 38, count 0 2006.285.13:10:13.67#ibcon#about to read 3, iclass 38, count 0 2006.285.13:10:13.71#ibcon#read 3, iclass 38, count 0 2006.285.13:10:13.71#ibcon#about to read 4, iclass 38, count 0 2006.285.13:10:13.71#ibcon#read 4, iclass 38, count 0 2006.285.13:10:13.71#ibcon#about to read 5, iclass 38, count 0 2006.285.13:10:13.71#ibcon#read 5, iclass 38, count 0 2006.285.13:10:13.71#ibcon#about to read 6, iclass 38, count 0 2006.285.13:10:13.71#ibcon#read 6, iclass 38, count 0 2006.285.13:10:13.71#ibcon#end of sib2, iclass 38, count 0 2006.285.13:10:13.71#ibcon#*after write, iclass 38, count 0 2006.285.13:10:13.71#ibcon#*before return 0, iclass 38, count 0 2006.285.13:10:13.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:10:13.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:10:13.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.13:10:13.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.13:10:13.71$vck44/vb=5,4 2006.285.13:10:13.71#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.13:10:13.71#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.13:10:13.71#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:13.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:10:13.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:10:13.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:10:13.77#ibcon#enter wrdev, iclass 40, count 2 2006.285.13:10:13.77#ibcon#first serial, iclass 40, count 2 2006.285.13:10:13.77#ibcon#enter sib2, iclass 40, count 2 2006.285.13:10:13.77#ibcon#flushed, iclass 40, count 2 2006.285.13:10:13.77#ibcon#about to write, iclass 40, count 2 2006.285.13:10:13.77#ibcon#wrote, iclass 40, count 2 2006.285.13:10:13.77#ibcon#about to read 3, iclass 40, count 2 2006.285.13:10:13.79#ibcon#read 3, iclass 40, count 2 2006.285.13:10:13.79#ibcon#about to read 4, iclass 40, count 2 2006.285.13:10:13.79#ibcon#read 4, iclass 40, count 2 2006.285.13:10:13.79#ibcon#about to read 5, iclass 40, count 2 2006.285.13:10:13.79#ibcon#read 5, iclass 40, count 2 2006.285.13:10:13.79#ibcon#about to read 6, iclass 40, count 2 2006.285.13:10:13.79#ibcon#read 6, iclass 40, count 2 2006.285.13:10:13.79#ibcon#end of sib2, iclass 40, count 2 2006.285.13:10:13.79#ibcon#*mode == 0, iclass 40, count 2 2006.285.13:10:13.79#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.13:10:13.79#ibcon#[27=AT05-04\r\n] 2006.285.13:10:13.79#ibcon#*before write, iclass 40, count 2 2006.285.13:10:13.79#ibcon#enter sib2, iclass 40, count 2 2006.285.13:10:13.79#ibcon#flushed, iclass 40, count 2 2006.285.13:10:13.79#ibcon#about to write, iclass 40, count 2 2006.285.13:10:13.79#ibcon#wrote, iclass 40, count 2 2006.285.13:10:13.79#ibcon#about to read 3, iclass 40, count 2 2006.285.13:10:13.82#ibcon#read 3, iclass 40, count 2 2006.285.13:10:13.82#ibcon#about to read 4, iclass 40, count 2 2006.285.13:10:13.82#ibcon#read 4, iclass 40, count 2 2006.285.13:10:13.82#ibcon#about to read 5, iclass 40, count 2 2006.285.13:10:13.82#ibcon#read 5, iclass 40, count 2 2006.285.13:10:13.82#ibcon#about to read 6, iclass 40, count 2 2006.285.13:10:13.82#ibcon#read 6, iclass 40, count 2 2006.285.13:10:13.82#ibcon#end of sib2, iclass 40, count 2 2006.285.13:10:13.82#ibcon#*after write, iclass 40, count 2 2006.285.13:10:13.82#ibcon#*before return 0, iclass 40, count 2 2006.285.13:10:13.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:10:13.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:10:13.82#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.13:10:13.82#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:13.82#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:10:13.94#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:10:13.94#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:10:13.94#ibcon#enter wrdev, iclass 40, count 0 2006.285.13:10:13.94#ibcon#first serial, iclass 40, count 0 2006.285.13:10:13.94#ibcon#enter sib2, iclass 40, count 0 2006.285.13:10:13.94#ibcon#flushed, iclass 40, count 0 2006.285.13:10:13.94#ibcon#about to write, iclass 40, count 0 2006.285.13:10:13.94#ibcon#wrote, iclass 40, count 0 2006.285.13:10:13.94#ibcon#about to read 3, iclass 40, count 0 2006.285.13:10:13.96#ibcon#read 3, iclass 40, count 0 2006.285.13:10:13.96#ibcon#about to read 4, iclass 40, count 0 2006.285.13:10:13.96#ibcon#read 4, iclass 40, count 0 2006.285.13:10:13.96#ibcon#about to read 5, iclass 40, count 0 2006.285.13:10:13.96#ibcon#read 5, iclass 40, count 0 2006.285.13:10:13.96#ibcon#about to read 6, iclass 40, count 0 2006.285.13:10:13.96#ibcon#read 6, iclass 40, count 0 2006.285.13:10:13.96#ibcon#end of sib2, iclass 40, count 0 2006.285.13:10:13.96#ibcon#*mode == 0, iclass 40, count 0 2006.285.13:10:13.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.13:10:13.96#ibcon#[27=USB\r\n] 2006.285.13:10:13.96#ibcon#*before write, iclass 40, count 0 2006.285.13:10:13.96#ibcon#enter sib2, iclass 40, count 0 2006.285.13:10:13.96#ibcon#flushed, iclass 40, count 0 2006.285.13:10:13.96#ibcon#about to write, iclass 40, count 0 2006.285.13:10:13.96#ibcon#wrote, iclass 40, count 0 2006.285.13:10:13.96#ibcon#about to read 3, iclass 40, count 0 2006.285.13:10:13.99#ibcon#read 3, iclass 40, count 0 2006.285.13:10:13.99#ibcon#about to read 4, iclass 40, count 0 2006.285.13:10:13.99#ibcon#read 4, iclass 40, count 0 2006.285.13:10:13.99#ibcon#about to read 5, iclass 40, count 0 2006.285.13:10:13.99#ibcon#read 5, iclass 40, count 0 2006.285.13:10:13.99#ibcon#about to read 6, iclass 40, count 0 2006.285.13:10:13.99#ibcon#read 6, iclass 40, count 0 2006.285.13:10:13.99#ibcon#end of sib2, iclass 40, count 0 2006.285.13:10:13.99#ibcon#*after write, iclass 40, count 0 2006.285.13:10:13.99#ibcon#*before return 0, iclass 40, count 0 2006.285.13:10:13.99#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:10:13.99#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:10:13.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.13:10:13.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.13:10:13.99$vck44/vblo=6,719.99 2006.285.13:10:13.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.13:10:13.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.13:10:13.99#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:13.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:10:13.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:10:13.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:10:13.99#ibcon#enter wrdev, iclass 4, count 0 2006.285.13:10:13.99#ibcon#first serial, iclass 4, count 0 2006.285.13:10:13.99#ibcon#enter sib2, iclass 4, count 0 2006.285.13:10:13.99#ibcon#flushed, iclass 4, count 0 2006.285.13:10:13.99#ibcon#about to write, iclass 4, count 0 2006.285.13:10:13.99#ibcon#wrote, iclass 4, count 0 2006.285.13:10:13.99#ibcon#about to read 3, iclass 4, count 0 2006.285.13:10:14.01#ibcon#read 3, iclass 4, count 0 2006.285.13:10:14.01#ibcon#about to read 4, iclass 4, count 0 2006.285.13:10:14.01#ibcon#read 4, iclass 4, count 0 2006.285.13:10:14.01#ibcon#about to read 5, iclass 4, count 0 2006.285.13:10:14.01#ibcon#read 5, iclass 4, count 0 2006.285.13:10:14.01#ibcon#about to read 6, iclass 4, count 0 2006.285.13:10:14.01#ibcon#read 6, iclass 4, count 0 2006.285.13:10:14.01#ibcon#end of sib2, iclass 4, count 0 2006.285.13:10:14.01#ibcon#*mode == 0, iclass 4, count 0 2006.285.13:10:14.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.13:10:14.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:10:14.01#ibcon#*before write, iclass 4, count 0 2006.285.13:10:14.01#ibcon#enter sib2, iclass 4, count 0 2006.285.13:10:14.01#ibcon#flushed, iclass 4, count 0 2006.285.13:10:14.01#ibcon#about to write, iclass 4, count 0 2006.285.13:10:14.01#ibcon#wrote, iclass 4, count 0 2006.285.13:10:14.01#ibcon#about to read 3, iclass 4, count 0 2006.285.13:10:14.05#ibcon#read 3, iclass 4, count 0 2006.285.13:10:14.05#ibcon#about to read 4, iclass 4, count 0 2006.285.13:10:14.05#ibcon#read 4, iclass 4, count 0 2006.285.13:10:14.05#ibcon#about to read 5, iclass 4, count 0 2006.285.13:10:14.05#ibcon#read 5, iclass 4, count 0 2006.285.13:10:14.05#ibcon#about to read 6, iclass 4, count 0 2006.285.13:10:14.05#ibcon#read 6, iclass 4, count 0 2006.285.13:10:14.05#ibcon#end of sib2, iclass 4, count 0 2006.285.13:10:14.05#ibcon#*after write, iclass 4, count 0 2006.285.13:10:14.05#ibcon#*before return 0, iclass 4, count 0 2006.285.13:10:14.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:10:14.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:10:14.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.13:10:14.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.13:10:14.05$vck44/vb=6,3 2006.285.13:10:14.05#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.13:10:14.05#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.13:10:14.05#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:14.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:10:14.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:10:14.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:10:14.11#ibcon#enter wrdev, iclass 6, count 2 2006.285.13:10:14.11#ibcon#first serial, iclass 6, count 2 2006.285.13:10:14.11#ibcon#enter sib2, iclass 6, count 2 2006.285.13:10:14.11#ibcon#flushed, iclass 6, count 2 2006.285.13:10:14.11#ibcon#about to write, iclass 6, count 2 2006.285.13:10:14.11#ibcon#wrote, iclass 6, count 2 2006.285.13:10:14.11#ibcon#about to read 3, iclass 6, count 2 2006.285.13:10:14.13#ibcon#read 3, iclass 6, count 2 2006.285.13:10:14.13#ibcon#about to read 4, iclass 6, count 2 2006.285.13:10:14.13#ibcon#read 4, iclass 6, count 2 2006.285.13:10:14.13#ibcon#about to read 5, iclass 6, count 2 2006.285.13:10:14.13#ibcon#read 5, iclass 6, count 2 2006.285.13:10:14.13#ibcon#about to read 6, iclass 6, count 2 2006.285.13:10:14.13#ibcon#read 6, iclass 6, count 2 2006.285.13:10:14.13#ibcon#end of sib2, iclass 6, count 2 2006.285.13:10:14.13#ibcon#*mode == 0, iclass 6, count 2 2006.285.13:10:14.13#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.13:10:14.13#ibcon#[27=AT06-03\r\n] 2006.285.13:10:14.13#ibcon#*before write, iclass 6, count 2 2006.285.13:10:14.13#ibcon#enter sib2, iclass 6, count 2 2006.285.13:10:14.13#ibcon#flushed, iclass 6, count 2 2006.285.13:10:14.13#ibcon#about to write, iclass 6, count 2 2006.285.13:10:14.13#ibcon#wrote, iclass 6, count 2 2006.285.13:10:14.13#ibcon#about to read 3, iclass 6, count 2 2006.285.13:10:14.16#ibcon#read 3, iclass 6, count 2 2006.285.13:10:14.16#ibcon#about to read 4, iclass 6, count 2 2006.285.13:10:14.16#ibcon#read 4, iclass 6, count 2 2006.285.13:10:14.16#ibcon#about to read 5, iclass 6, count 2 2006.285.13:10:14.16#ibcon#read 5, iclass 6, count 2 2006.285.13:10:14.16#ibcon#about to read 6, iclass 6, count 2 2006.285.13:10:14.16#ibcon#read 6, iclass 6, count 2 2006.285.13:10:14.16#ibcon#end of sib2, iclass 6, count 2 2006.285.13:10:14.16#ibcon#*after write, iclass 6, count 2 2006.285.13:10:14.16#ibcon#*before return 0, iclass 6, count 2 2006.285.13:10:14.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:10:14.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:10:14.16#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.13:10:14.16#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:14.16#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:10:14.28#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:10:14.28#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:10:14.28#ibcon#enter wrdev, iclass 6, count 0 2006.285.13:10:14.28#ibcon#first serial, iclass 6, count 0 2006.285.13:10:14.28#ibcon#enter sib2, iclass 6, count 0 2006.285.13:10:14.28#ibcon#flushed, iclass 6, count 0 2006.285.13:10:14.28#ibcon#about to write, iclass 6, count 0 2006.285.13:10:14.28#ibcon#wrote, iclass 6, count 0 2006.285.13:10:14.28#ibcon#about to read 3, iclass 6, count 0 2006.285.13:10:14.30#ibcon#read 3, iclass 6, count 0 2006.285.13:10:14.30#ibcon#about to read 4, iclass 6, count 0 2006.285.13:10:14.30#ibcon#read 4, iclass 6, count 0 2006.285.13:10:14.30#ibcon#about to read 5, iclass 6, count 0 2006.285.13:10:14.30#ibcon#read 5, iclass 6, count 0 2006.285.13:10:14.30#ibcon#about to read 6, iclass 6, count 0 2006.285.13:10:14.30#ibcon#read 6, iclass 6, count 0 2006.285.13:10:14.30#ibcon#end of sib2, iclass 6, count 0 2006.285.13:10:14.30#ibcon#*mode == 0, iclass 6, count 0 2006.285.13:10:14.30#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.13:10:14.30#ibcon#[27=USB\r\n] 2006.285.13:10:14.30#ibcon#*before write, iclass 6, count 0 2006.285.13:10:14.30#ibcon#enter sib2, iclass 6, count 0 2006.285.13:10:14.30#ibcon#flushed, iclass 6, count 0 2006.285.13:10:14.30#ibcon#about to write, iclass 6, count 0 2006.285.13:10:14.30#ibcon#wrote, iclass 6, count 0 2006.285.13:10:14.30#ibcon#about to read 3, iclass 6, count 0 2006.285.13:10:14.33#ibcon#read 3, iclass 6, count 0 2006.285.13:10:14.33#ibcon#about to read 4, iclass 6, count 0 2006.285.13:10:14.33#ibcon#read 4, iclass 6, count 0 2006.285.13:10:14.33#ibcon#about to read 5, iclass 6, count 0 2006.285.13:10:14.33#ibcon#read 5, iclass 6, count 0 2006.285.13:10:14.33#ibcon#about to read 6, iclass 6, count 0 2006.285.13:10:14.33#ibcon#read 6, iclass 6, count 0 2006.285.13:10:14.33#ibcon#end of sib2, iclass 6, count 0 2006.285.13:10:14.33#ibcon#*after write, iclass 6, count 0 2006.285.13:10:14.33#ibcon#*before return 0, iclass 6, count 0 2006.285.13:10:14.33#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:10:14.33#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:10:14.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.13:10:14.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.13:10:14.33$vck44/vblo=7,734.99 2006.285.13:10:14.38#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.13:10:14.38#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.13:10:14.38#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:14.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:10:14.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:10:14.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:10:14.39#ibcon#enter wrdev, iclass 10, count 0 2006.285.13:10:14.39#ibcon#first serial, iclass 10, count 0 2006.285.13:10:14.39#ibcon#enter sib2, iclass 10, count 0 2006.285.13:10:14.39#ibcon#flushed, iclass 10, count 0 2006.285.13:10:14.39#ibcon#about to write, iclass 10, count 0 2006.285.13:10:14.39#ibcon#wrote, iclass 10, count 0 2006.285.13:10:14.39#ibcon#about to read 3, iclass 10, count 0 2006.285.13:10:14.40#ibcon#read 3, iclass 10, count 0 2006.285.13:10:14.40#ibcon#about to read 4, iclass 10, count 0 2006.285.13:10:14.40#ibcon#read 4, iclass 10, count 0 2006.285.13:10:14.40#ibcon#about to read 5, iclass 10, count 0 2006.285.13:10:14.40#ibcon#read 5, iclass 10, count 0 2006.285.13:10:14.40#ibcon#about to read 6, iclass 10, count 0 2006.285.13:10:14.40#ibcon#read 6, iclass 10, count 0 2006.285.13:10:14.40#ibcon#end of sib2, iclass 10, count 0 2006.285.13:10:14.40#ibcon#*mode == 0, iclass 10, count 0 2006.285.13:10:14.40#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.13:10:14.40#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:10:14.40#ibcon#*before write, iclass 10, count 0 2006.285.13:10:14.40#ibcon#enter sib2, iclass 10, count 0 2006.285.13:10:14.40#ibcon#flushed, iclass 10, count 0 2006.285.13:10:14.40#ibcon#about to write, iclass 10, count 0 2006.285.13:10:14.40#ibcon#wrote, iclass 10, count 0 2006.285.13:10:14.40#ibcon#about to read 3, iclass 10, count 0 2006.285.13:10:14.44#ibcon#read 3, iclass 10, count 0 2006.285.13:10:14.44#ibcon#about to read 4, iclass 10, count 0 2006.285.13:10:14.44#ibcon#read 4, iclass 10, count 0 2006.285.13:10:14.44#ibcon#about to read 5, iclass 10, count 0 2006.285.13:10:14.44#ibcon#read 5, iclass 10, count 0 2006.285.13:10:14.44#ibcon#about to read 6, iclass 10, count 0 2006.285.13:10:14.44#ibcon#read 6, iclass 10, count 0 2006.285.13:10:14.44#ibcon#end of sib2, iclass 10, count 0 2006.285.13:10:14.44#ibcon#*after write, iclass 10, count 0 2006.285.13:10:14.44#ibcon#*before return 0, iclass 10, count 0 2006.285.13:10:14.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:10:14.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:10:14.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.13:10:14.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.13:10:14.44$vck44/vb=7,4 2006.285.13:10:14.44#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.13:10:14.44#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.13:10:14.44#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:14.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:10:14.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:10:14.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:10:14.44#ibcon#enter wrdev, iclass 12, count 2 2006.285.13:10:14.44#ibcon#first serial, iclass 12, count 2 2006.285.13:10:14.44#ibcon#enter sib2, iclass 12, count 2 2006.285.13:10:14.44#ibcon#flushed, iclass 12, count 2 2006.285.13:10:14.44#ibcon#about to write, iclass 12, count 2 2006.285.13:10:14.44#ibcon#wrote, iclass 12, count 2 2006.285.13:10:14.44#ibcon#about to read 3, iclass 12, count 2 2006.285.13:10:14.46#ibcon#read 3, iclass 12, count 2 2006.285.13:10:14.46#ibcon#about to read 4, iclass 12, count 2 2006.285.13:10:14.46#ibcon#read 4, iclass 12, count 2 2006.285.13:10:14.46#ibcon#about to read 5, iclass 12, count 2 2006.285.13:10:14.46#ibcon#read 5, iclass 12, count 2 2006.285.13:10:14.46#ibcon#about to read 6, iclass 12, count 2 2006.285.13:10:14.46#ibcon#read 6, iclass 12, count 2 2006.285.13:10:14.46#ibcon#end of sib2, iclass 12, count 2 2006.285.13:10:14.46#ibcon#*mode == 0, iclass 12, count 2 2006.285.13:10:14.46#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.13:10:14.46#ibcon#[27=AT07-04\r\n] 2006.285.13:10:14.46#ibcon#*before write, iclass 12, count 2 2006.285.13:10:14.46#ibcon#enter sib2, iclass 12, count 2 2006.285.13:10:14.46#ibcon#flushed, iclass 12, count 2 2006.285.13:10:14.46#ibcon#about to write, iclass 12, count 2 2006.285.13:10:14.46#ibcon#wrote, iclass 12, count 2 2006.285.13:10:14.46#ibcon#about to read 3, iclass 12, count 2 2006.285.13:10:14.49#ibcon#read 3, iclass 12, count 2 2006.285.13:10:14.49#ibcon#about to read 4, iclass 12, count 2 2006.285.13:10:14.49#ibcon#read 4, iclass 12, count 2 2006.285.13:10:14.49#ibcon#about to read 5, iclass 12, count 2 2006.285.13:10:14.49#ibcon#read 5, iclass 12, count 2 2006.285.13:10:14.49#ibcon#about to read 6, iclass 12, count 2 2006.285.13:10:14.49#ibcon#read 6, iclass 12, count 2 2006.285.13:10:14.49#ibcon#end of sib2, iclass 12, count 2 2006.285.13:10:14.49#ibcon#*after write, iclass 12, count 2 2006.285.13:10:14.49#ibcon#*before return 0, iclass 12, count 2 2006.285.13:10:14.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:10:14.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:10:14.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.13:10:14.49#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:14.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:10:14.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:10:14.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:10:14.61#ibcon#enter wrdev, iclass 12, count 0 2006.285.13:10:14.61#ibcon#first serial, iclass 12, count 0 2006.285.13:10:14.61#ibcon#enter sib2, iclass 12, count 0 2006.285.13:10:14.61#ibcon#flushed, iclass 12, count 0 2006.285.13:10:14.61#ibcon#about to write, iclass 12, count 0 2006.285.13:10:14.61#ibcon#wrote, iclass 12, count 0 2006.285.13:10:14.61#ibcon#about to read 3, iclass 12, count 0 2006.285.13:10:14.63#ibcon#read 3, iclass 12, count 0 2006.285.13:10:14.63#ibcon#about to read 4, iclass 12, count 0 2006.285.13:10:14.63#ibcon#read 4, iclass 12, count 0 2006.285.13:10:14.63#ibcon#about to read 5, iclass 12, count 0 2006.285.13:10:14.63#ibcon#read 5, iclass 12, count 0 2006.285.13:10:14.63#ibcon#about to read 6, iclass 12, count 0 2006.285.13:10:14.63#ibcon#read 6, iclass 12, count 0 2006.285.13:10:14.63#ibcon#end of sib2, iclass 12, count 0 2006.285.13:10:14.63#ibcon#*mode == 0, iclass 12, count 0 2006.285.13:10:14.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.13:10:14.63#ibcon#[27=USB\r\n] 2006.285.13:10:14.63#ibcon#*before write, iclass 12, count 0 2006.285.13:10:14.63#ibcon#enter sib2, iclass 12, count 0 2006.285.13:10:14.63#ibcon#flushed, iclass 12, count 0 2006.285.13:10:14.63#ibcon#about to write, iclass 12, count 0 2006.285.13:10:14.63#ibcon#wrote, iclass 12, count 0 2006.285.13:10:14.63#ibcon#about to read 3, iclass 12, count 0 2006.285.13:10:14.66#ibcon#read 3, iclass 12, count 0 2006.285.13:10:14.66#ibcon#about to read 4, iclass 12, count 0 2006.285.13:10:14.66#ibcon#read 4, iclass 12, count 0 2006.285.13:10:14.66#ibcon#about to read 5, iclass 12, count 0 2006.285.13:10:14.66#ibcon#read 5, iclass 12, count 0 2006.285.13:10:14.66#ibcon#about to read 6, iclass 12, count 0 2006.285.13:10:14.66#ibcon#read 6, iclass 12, count 0 2006.285.13:10:14.66#ibcon#end of sib2, iclass 12, count 0 2006.285.13:10:14.66#ibcon#*after write, iclass 12, count 0 2006.285.13:10:14.66#ibcon#*before return 0, iclass 12, count 0 2006.285.13:10:14.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:10:14.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:10:14.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.13:10:14.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.13:10:14.66$vck44/vblo=8,744.99 2006.285.13:10:14.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.13:10:14.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.13:10:14.66#ibcon#ireg 17 cls_cnt 0 2006.285.13:10:14.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:10:14.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:10:14.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:10:14.66#ibcon#enter wrdev, iclass 14, count 0 2006.285.13:10:14.66#ibcon#first serial, iclass 14, count 0 2006.285.13:10:14.66#ibcon#enter sib2, iclass 14, count 0 2006.285.13:10:14.66#ibcon#flushed, iclass 14, count 0 2006.285.13:10:14.66#ibcon#about to write, iclass 14, count 0 2006.285.13:10:14.66#ibcon#wrote, iclass 14, count 0 2006.285.13:10:14.66#ibcon#about to read 3, iclass 14, count 0 2006.285.13:10:14.68#ibcon#read 3, iclass 14, count 0 2006.285.13:10:14.68#ibcon#about to read 4, iclass 14, count 0 2006.285.13:10:14.68#ibcon#read 4, iclass 14, count 0 2006.285.13:10:14.68#ibcon#about to read 5, iclass 14, count 0 2006.285.13:10:14.68#ibcon#read 5, iclass 14, count 0 2006.285.13:10:14.68#ibcon#about to read 6, iclass 14, count 0 2006.285.13:10:14.68#ibcon#read 6, iclass 14, count 0 2006.285.13:10:14.68#ibcon#end of sib2, iclass 14, count 0 2006.285.13:10:14.68#ibcon#*mode == 0, iclass 14, count 0 2006.285.13:10:14.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.13:10:14.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:10:14.68#ibcon#*before write, iclass 14, count 0 2006.285.13:10:14.68#ibcon#enter sib2, iclass 14, count 0 2006.285.13:10:14.68#ibcon#flushed, iclass 14, count 0 2006.285.13:10:14.68#ibcon#about to write, iclass 14, count 0 2006.285.13:10:14.68#ibcon#wrote, iclass 14, count 0 2006.285.13:10:14.68#ibcon#about to read 3, iclass 14, count 0 2006.285.13:10:14.72#ibcon#read 3, iclass 14, count 0 2006.285.13:10:14.72#ibcon#about to read 4, iclass 14, count 0 2006.285.13:10:14.72#ibcon#read 4, iclass 14, count 0 2006.285.13:10:14.72#ibcon#about to read 5, iclass 14, count 0 2006.285.13:10:14.72#ibcon#read 5, iclass 14, count 0 2006.285.13:10:14.72#ibcon#about to read 6, iclass 14, count 0 2006.285.13:10:14.72#ibcon#read 6, iclass 14, count 0 2006.285.13:10:14.72#ibcon#end of sib2, iclass 14, count 0 2006.285.13:10:14.72#ibcon#*after write, iclass 14, count 0 2006.285.13:10:14.72#ibcon#*before return 0, iclass 14, count 0 2006.285.13:10:14.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:10:14.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:10:14.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.13:10:14.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.13:10:14.72$vck44/vb=8,4 2006.285.13:10:14.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.13:10:14.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.13:10:14.72#ibcon#ireg 11 cls_cnt 2 2006.285.13:10:14.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:10:14.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:10:14.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:10:14.78#ibcon#enter wrdev, iclass 16, count 2 2006.285.13:10:14.78#ibcon#first serial, iclass 16, count 2 2006.285.13:10:14.78#ibcon#enter sib2, iclass 16, count 2 2006.285.13:10:14.78#ibcon#flushed, iclass 16, count 2 2006.285.13:10:14.78#ibcon#about to write, iclass 16, count 2 2006.285.13:10:14.78#ibcon#wrote, iclass 16, count 2 2006.285.13:10:14.78#ibcon#about to read 3, iclass 16, count 2 2006.285.13:10:14.80#ibcon#read 3, iclass 16, count 2 2006.285.13:10:14.80#ibcon#about to read 4, iclass 16, count 2 2006.285.13:10:14.80#ibcon#read 4, iclass 16, count 2 2006.285.13:10:14.80#ibcon#about to read 5, iclass 16, count 2 2006.285.13:10:14.80#ibcon#read 5, iclass 16, count 2 2006.285.13:10:14.80#ibcon#about to read 6, iclass 16, count 2 2006.285.13:10:14.80#ibcon#read 6, iclass 16, count 2 2006.285.13:10:14.80#ibcon#end of sib2, iclass 16, count 2 2006.285.13:10:14.80#ibcon#*mode == 0, iclass 16, count 2 2006.285.13:10:14.80#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.13:10:14.80#ibcon#[27=AT08-04\r\n] 2006.285.13:10:14.80#ibcon#*before write, iclass 16, count 2 2006.285.13:10:14.80#ibcon#enter sib2, iclass 16, count 2 2006.285.13:10:14.80#ibcon#flushed, iclass 16, count 2 2006.285.13:10:14.80#ibcon#about to write, iclass 16, count 2 2006.285.13:10:14.80#ibcon#wrote, iclass 16, count 2 2006.285.13:10:14.80#ibcon#about to read 3, iclass 16, count 2 2006.285.13:10:14.83#ibcon#read 3, iclass 16, count 2 2006.285.13:10:14.83#ibcon#about to read 4, iclass 16, count 2 2006.285.13:10:14.83#ibcon#read 4, iclass 16, count 2 2006.285.13:10:14.83#ibcon#about to read 5, iclass 16, count 2 2006.285.13:10:14.83#ibcon#read 5, iclass 16, count 2 2006.285.13:10:14.83#ibcon#about to read 6, iclass 16, count 2 2006.285.13:10:14.83#ibcon#read 6, iclass 16, count 2 2006.285.13:10:14.83#ibcon#end of sib2, iclass 16, count 2 2006.285.13:10:14.83#ibcon#*after write, iclass 16, count 2 2006.285.13:10:14.83#ibcon#*before return 0, iclass 16, count 2 2006.285.13:10:14.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:10:14.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:10:14.83#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.13:10:14.83#ibcon#ireg 7 cls_cnt 0 2006.285.13:10:14.83#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:10:14.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:10:14.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:10:14.95#ibcon#enter wrdev, iclass 16, count 0 2006.285.13:10:14.95#ibcon#first serial, iclass 16, count 0 2006.285.13:10:14.95#ibcon#enter sib2, iclass 16, count 0 2006.285.13:10:14.95#ibcon#flushed, iclass 16, count 0 2006.285.13:10:14.95#ibcon#about to write, iclass 16, count 0 2006.285.13:10:14.95#ibcon#wrote, iclass 16, count 0 2006.285.13:10:14.95#ibcon#about to read 3, iclass 16, count 0 2006.285.13:10:14.97#ibcon#read 3, iclass 16, count 0 2006.285.13:10:14.97#ibcon#about to read 4, iclass 16, count 0 2006.285.13:10:14.97#ibcon#read 4, iclass 16, count 0 2006.285.13:10:14.97#ibcon#about to read 5, iclass 16, count 0 2006.285.13:10:14.97#ibcon#read 5, iclass 16, count 0 2006.285.13:10:14.97#ibcon#about to read 6, iclass 16, count 0 2006.285.13:10:14.97#ibcon#read 6, iclass 16, count 0 2006.285.13:10:14.97#ibcon#end of sib2, iclass 16, count 0 2006.285.13:10:14.97#ibcon#*mode == 0, iclass 16, count 0 2006.285.13:10:14.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.13:10:14.97#ibcon#[27=USB\r\n] 2006.285.13:10:14.97#ibcon#*before write, iclass 16, count 0 2006.285.13:10:14.97#ibcon#enter sib2, iclass 16, count 0 2006.285.13:10:14.97#ibcon#flushed, iclass 16, count 0 2006.285.13:10:14.97#ibcon#about to write, iclass 16, count 0 2006.285.13:10:14.97#ibcon#wrote, iclass 16, count 0 2006.285.13:10:14.97#ibcon#about to read 3, iclass 16, count 0 2006.285.13:10:15.00#ibcon#read 3, iclass 16, count 0 2006.285.13:10:15.00#ibcon#about to read 4, iclass 16, count 0 2006.285.13:10:15.00#ibcon#read 4, iclass 16, count 0 2006.285.13:10:15.00#ibcon#about to read 5, iclass 16, count 0 2006.285.13:10:15.00#ibcon#read 5, iclass 16, count 0 2006.285.13:10:15.00#ibcon#about to read 6, iclass 16, count 0 2006.285.13:10:15.00#ibcon#read 6, iclass 16, count 0 2006.285.13:10:15.00#ibcon#end of sib2, iclass 16, count 0 2006.285.13:10:15.00#ibcon#*after write, iclass 16, count 0 2006.285.13:10:15.00#ibcon#*before return 0, iclass 16, count 0 2006.285.13:10:15.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:10:15.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:10:15.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.13:10:15.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.13:10:15.00$vck44/vabw=wide 2006.285.13:10:15.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.13:10:15.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.13:10:15.00#ibcon#ireg 8 cls_cnt 0 2006.285.13:10:15.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:10:15.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:10:15.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:10:15.00#ibcon#enter wrdev, iclass 18, count 0 2006.285.13:10:15.00#ibcon#first serial, iclass 18, count 0 2006.285.13:10:15.00#ibcon#enter sib2, iclass 18, count 0 2006.285.13:10:15.00#ibcon#flushed, iclass 18, count 0 2006.285.13:10:15.00#ibcon#about to write, iclass 18, count 0 2006.285.13:10:15.00#ibcon#wrote, iclass 18, count 0 2006.285.13:10:15.00#ibcon#about to read 3, iclass 18, count 0 2006.285.13:10:15.02#ibcon#read 3, iclass 18, count 0 2006.285.13:10:15.02#ibcon#about to read 4, iclass 18, count 0 2006.285.13:10:15.02#ibcon#read 4, iclass 18, count 0 2006.285.13:10:15.02#ibcon#about to read 5, iclass 18, count 0 2006.285.13:10:15.02#ibcon#read 5, iclass 18, count 0 2006.285.13:10:15.02#ibcon#about to read 6, iclass 18, count 0 2006.285.13:10:15.02#ibcon#read 6, iclass 18, count 0 2006.285.13:10:15.02#ibcon#end of sib2, iclass 18, count 0 2006.285.13:10:15.02#ibcon#*mode == 0, iclass 18, count 0 2006.285.13:10:15.02#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.13:10:15.02#ibcon#[25=BW32\r\n] 2006.285.13:10:15.02#ibcon#*before write, iclass 18, count 0 2006.285.13:10:15.02#ibcon#enter sib2, iclass 18, count 0 2006.285.13:10:15.02#ibcon#flushed, iclass 18, count 0 2006.285.13:10:15.02#ibcon#about to write, iclass 18, count 0 2006.285.13:10:15.02#ibcon#wrote, iclass 18, count 0 2006.285.13:10:15.02#ibcon#about to read 3, iclass 18, count 0 2006.285.13:10:15.05#ibcon#read 3, iclass 18, count 0 2006.285.13:10:15.05#ibcon#about to read 4, iclass 18, count 0 2006.285.13:10:15.05#ibcon#read 4, iclass 18, count 0 2006.285.13:10:15.05#ibcon#about to read 5, iclass 18, count 0 2006.285.13:10:15.05#ibcon#read 5, iclass 18, count 0 2006.285.13:10:15.05#ibcon#about to read 6, iclass 18, count 0 2006.285.13:10:15.05#ibcon#read 6, iclass 18, count 0 2006.285.13:10:15.05#ibcon#end of sib2, iclass 18, count 0 2006.285.13:10:15.05#ibcon#*after write, iclass 18, count 0 2006.285.13:10:15.05#ibcon#*before return 0, iclass 18, count 0 2006.285.13:10:15.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:10:15.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:10:15.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.13:10:15.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.13:10:15.05$vck44/vbbw=wide 2006.285.13:10:15.05#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.13:10:15.05#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.13:10:15.05#ibcon#ireg 8 cls_cnt 0 2006.285.13:10:15.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:10:15.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:10:15.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:10:15.12#ibcon#enter wrdev, iclass 20, count 0 2006.285.13:10:15.12#ibcon#first serial, iclass 20, count 0 2006.285.13:10:15.12#ibcon#enter sib2, iclass 20, count 0 2006.285.13:10:15.12#ibcon#flushed, iclass 20, count 0 2006.285.13:10:15.12#ibcon#about to write, iclass 20, count 0 2006.285.13:10:15.12#ibcon#wrote, iclass 20, count 0 2006.285.13:10:15.12#ibcon#about to read 3, iclass 20, count 0 2006.285.13:10:15.14#ibcon#read 3, iclass 20, count 0 2006.285.13:10:15.14#ibcon#about to read 4, iclass 20, count 0 2006.285.13:10:15.14#ibcon#read 4, iclass 20, count 0 2006.285.13:10:15.14#ibcon#about to read 5, iclass 20, count 0 2006.285.13:10:15.14#ibcon#read 5, iclass 20, count 0 2006.285.13:10:15.14#ibcon#about to read 6, iclass 20, count 0 2006.285.13:10:15.14#ibcon#read 6, iclass 20, count 0 2006.285.13:10:15.14#ibcon#end of sib2, iclass 20, count 0 2006.285.13:10:15.14#ibcon#*mode == 0, iclass 20, count 0 2006.285.13:10:15.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.13:10:15.14#ibcon#[27=BW32\r\n] 2006.285.13:10:15.14#ibcon#*before write, iclass 20, count 0 2006.285.13:10:15.14#ibcon#enter sib2, iclass 20, count 0 2006.285.13:10:15.14#ibcon#flushed, iclass 20, count 0 2006.285.13:10:15.14#ibcon#about to write, iclass 20, count 0 2006.285.13:10:15.14#ibcon#wrote, iclass 20, count 0 2006.285.13:10:15.14#ibcon#about to read 3, iclass 20, count 0 2006.285.13:10:15.17#ibcon#read 3, iclass 20, count 0 2006.285.13:10:15.17#ibcon#about to read 4, iclass 20, count 0 2006.285.13:10:15.17#ibcon#read 4, iclass 20, count 0 2006.285.13:10:15.17#ibcon#about to read 5, iclass 20, count 0 2006.285.13:10:15.17#ibcon#read 5, iclass 20, count 0 2006.285.13:10:15.17#ibcon#about to read 6, iclass 20, count 0 2006.285.13:10:15.17#ibcon#read 6, iclass 20, count 0 2006.285.13:10:15.17#ibcon#end of sib2, iclass 20, count 0 2006.285.13:10:15.17#ibcon#*after write, iclass 20, count 0 2006.285.13:10:15.17#ibcon#*before return 0, iclass 20, count 0 2006.285.13:10:15.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:10:15.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:10:15.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.13:10:15.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.13:10:15.17$setupk4/ifdk4 2006.285.13:10:15.17$ifdk4/lo= 2006.285.13:10:15.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:10:15.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:10:15.17$ifdk4/patch= 2006.285.13:10:15.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:10:15.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:10:15.17$setupk4/!*+20s 2006.285.13:10:17.84#abcon#<5=/04 1.5 3.2 19.02 961015.4\r\n> 2006.285.13:10:17.86#abcon#{5=INTERFACE CLEAR} 2006.285.13:10:17.92#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:10:21.14#trakl#Source acquired 2006.285.13:10:22.14#flagr#flagr/antenna,acquired 2006.285.13:10:28.01#abcon#<5=/04 1.5 3.2 19.02 961015.4\r\n> 2006.285.13:10:28.03#abcon#{5=INTERFACE CLEAR} 2006.285.13:10:28.09#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:10:29.19$setupk4/"tpicd 2006.285.13:10:29.19$setupk4/echo=off 2006.285.13:10:29.19$setupk4/xlog=off 2006.285.13:10:29.19:!2006.285.13:11:24 2006.285.13:11:24.00:preob 2006.285.13:11:24.13/onsource/TRACKING 2006.285.13:11:24.13:!2006.285.13:11:34 2006.285.13:11:34.00:"tape 2006.285.13:11:34.00:"st=record 2006.285.13:11:34.00:data_valid=on 2006.285.13:11:34.00:midob 2006.285.13:11:34.13/onsource/TRACKING 2006.285.13:11:34.13/wx/19.02,1015.4,96 2006.285.13:11:34.23/cable/+6.4978E-03 2006.285.13:11:35.32/va/01,07,usb,yes,31,34 2006.285.13:11:35.32/va/02,06,usb,yes,31,32 2006.285.13:11:35.32/va/03,07,usb,yes,31,33 2006.285.13:11:35.32/va/04,06,usb,yes,32,34 2006.285.13:11:35.32/va/05,03,usb,yes,32,32 2006.285.13:11:35.32/va/06,04,usb,yes,29,28 2006.285.13:11:35.32/va/07,04,usb,yes,29,30 2006.285.13:11:35.32/va/08,03,usb,yes,30,36 2006.285.13:11:35.55/valo/01,524.99,yes,locked 2006.285.13:11:35.55/valo/02,534.99,yes,locked 2006.285.13:11:35.55/valo/03,564.99,yes,locked 2006.285.13:11:35.55/valo/04,624.99,yes,locked 2006.285.13:11:35.55/valo/05,734.99,yes,locked 2006.285.13:11:35.55/valo/06,814.99,yes,locked 2006.285.13:11:35.55/valo/07,864.99,yes,locked 2006.285.13:11:35.55/valo/08,884.99,yes,locked 2006.285.13:11:36.64/vb/01,04,usb,yes,30,28 2006.285.13:11:36.64/vb/02,05,usb,yes,28,28 2006.285.13:11:36.64/vb/03,04,usb,yes,29,32 2006.285.13:11:36.64/vb/04,05,usb,yes,29,28 2006.285.13:11:36.64/vb/05,04,usb,yes,26,28 2006.285.13:11:36.64/vb/06,03,usb,yes,37,33 2006.285.13:11:36.64/vb/07,04,usb,yes,30,30 2006.285.13:11:36.64/vb/08,04,usb,yes,27,31 2006.285.13:11:36.87/vblo/01,629.99,yes,locked 2006.285.13:11:36.87/vblo/02,634.99,yes,locked 2006.285.13:11:36.87/vblo/03,649.99,yes,locked 2006.285.13:11:36.87/vblo/04,679.99,yes,locked 2006.285.13:11:36.87/vblo/05,709.99,yes,locked 2006.285.13:11:36.87/vblo/06,719.99,yes,locked 2006.285.13:11:36.87/vblo/07,734.99,yes,locked 2006.285.13:11:36.87/vblo/08,744.99,yes,locked 2006.285.13:11:37.02/vabw/8 2006.285.13:11:37.17/vbbw/8 2006.285.13:11:37.26/xfe/off,on,12.2 2006.285.13:11:37.63/ifatt/23,28,28,28 2006.285.13:11:38.08/fmout-gps/S +2.62E-07 2006.285.13:11:38.10:!2006.285.13:14:14 2006.285.13:14:14.01:data_valid=off 2006.285.13:14:14.01:"et 2006.285.13:14:14.01:!+3s 2006.285.13:14:17.02:"tape 2006.285.13:14:17.02:postob 2006.285.13:14:17.08/cable/+6.4965E-03 2006.285.13:14:17.08/wx/19.03,1015.3,96 2006.285.13:14:18.08/fmout-gps/S +2.62E-07 2006.285.13:14:18.08:scan_name=285-1319,jd0610,110 2006.285.13:14:18.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.285.13:14:19.14#flagr#flagr/antenna,new-source 2006.285.13:14:19.14:checkk5 2006.285.13:14:19.49/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:14:19.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:14:20.32/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:14:20.69/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:14:21.14/chk_obsdata//k5ts1/T2851311??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.13:14:21.52/chk_obsdata//k5ts2/T2851311??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.13:14:22.01/chk_obsdata//k5ts3/T2851311??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.13:14:22.36/chk_obsdata//k5ts4/T2851311??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.13:14:23.24/k5log//k5ts1_log_newline 2006.285.13:14:24.02/k5log//k5ts2_log_newline 2006.285.13:14:24.88/k5log//k5ts3_log_newline 2006.285.13:14:26.06/k5log//k5ts4_log_newline 2006.285.13:14:26.08/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:14:26.08:setupk4=1 2006.285.13:14:26.08$setupk4/echo=on 2006.285.13:14:26.08$setupk4/pcalon 2006.285.13:14:26.08$pcalon/"no phase cal control is implemented here 2006.285.13:14:26.08$setupk4/"tpicd=stop 2006.285.13:14:26.08$setupk4/"rec=synch_on 2006.285.13:14:26.08$setupk4/"rec_mode=128 2006.285.13:14:26.08$setupk4/!* 2006.285.13:14:26.08$setupk4/recpk4 2006.285.13:14:26.08$recpk4/recpatch= 2006.285.13:14:26.08$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:14:26.09$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:14:26.09$setupk4/vck44 2006.285.13:14:26.09$vck44/valo=1,524.99 2006.285.13:14:26.09#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.13:14:26.09#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.13:14:26.09#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:26.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:14:26.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:14:26.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:14:26.09#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:14:26.09#ibcon#first serial, iclass 17, count 0 2006.285.13:14:26.09#ibcon#enter sib2, iclass 17, count 0 2006.285.13:14:26.09#ibcon#flushed, iclass 17, count 0 2006.285.13:14:26.09#ibcon#about to write, iclass 17, count 0 2006.285.13:14:26.09#ibcon#wrote, iclass 17, count 0 2006.285.13:14:26.09#ibcon#about to read 3, iclass 17, count 0 2006.285.13:14:26.10#ibcon#read 3, iclass 17, count 0 2006.285.13:14:26.10#ibcon#about to read 4, iclass 17, count 0 2006.285.13:14:26.10#ibcon#read 4, iclass 17, count 0 2006.285.13:14:26.10#ibcon#about to read 5, iclass 17, count 0 2006.285.13:14:26.10#ibcon#read 5, iclass 17, count 0 2006.285.13:14:26.10#ibcon#about to read 6, iclass 17, count 0 2006.285.13:14:26.10#ibcon#read 6, iclass 17, count 0 2006.285.13:14:26.10#ibcon#end of sib2, iclass 17, count 0 2006.285.13:14:26.10#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:14:26.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:14:26.10#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:14:26.10#ibcon#*before write, iclass 17, count 0 2006.285.13:14:26.10#ibcon#enter sib2, iclass 17, count 0 2006.285.13:14:26.10#ibcon#flushed, iclass 17, count 0 2006.285.13:14:26.10#ibcon#about to write, iclass 17, count 0 2006.285.13:14:26.10#ibcon#wrote, iclass 17, count 0 2006.285.13:14:26.10#ibcon#about to read 3, iclass 17, count 0 2006.285.13:14:26.15#ibcon#read 3, iclass 17, count 0 2006.285.13:14:26.15#ibcon#about to read 4, iclass 17, count 0 2006.285.13:14:26.15#ibcon#read 4, iclass 17, count 0 2006.285.13:14:26.15#ibcon#about to read 5, iclass 17, count 0 2006.285.13:14:26.15#ibcon#read 5, iclass 17, count 0 2006.285.13:14:26.15#ibcon#about to read 6, iclass 17, count 0 2006.285.13:14:26.15#ibcon#read 6, iclass 17, count 0 2006.285.13:14:26.15#ibcon#end of sib2, iclass 17, count 0 2006.285.13:14:26.15#ibcon#*after write, iclass 17, count 0 2006.285.13:14:26.15#ibcon#*before return 0, iclass 17, count 0 2006.285.13:14:26.15#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:14:26.15#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:14:26.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:14:26.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:14:26.15$vck44/va=1,7 2006.285.13:14:26.15#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.13:14:26.15#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.13:14:26.15#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:26.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:14:26.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:14:26.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:14:26.15#ibcon#enter wrdev, iclass 19, count 2 2006.285.13:14:26.15#ibcon#first serial, iclass 19, count 2 2006.285.13:14:26.15#ibcon#enter sib2, iclass 19, count 2 2006.285.13:14:26.15#ibcon#flushed, iclass 19, count 2 2006.285.13:14:26.15#ibcon#about to write, iclass 19, count 2 2006.285.13:14:26.15#ibcon#wrote, iclass 19, count 2 2006.285.13:14:26.15#ibcon#about to read 3, iclass 19, count 2 2006.285.13:14:26.17#ibcon#read 3, iclass 19, count 2 2006.285.13:14:26.17#ibcon#about to read 4, iclass 19, count 2 2006.285.13:14:26.17#ibcon#read 4, iclass 19, count 2 2006.285.13:14:26.17#ibcon#about to read 5, iclass 19, count 2 2006.285.13:14:26.17#ibcon#read 5, iclass 19, count 2 2006.285.13:14:26.17#ibcon#about to read 6, iclass 19, count 2 2006.285.13:14:26.17#ibcon#read 6, iclass 19, count 2 2006.285.13:14:26.17#ibcon#end of sib2, iclass 19, count 2 2006.285.13:14:26.17#ibcon#*mode == 0, iclass 19, count 2 2006.285.13:14:26.17#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.13:14:26.17#ibcon#[25=AT01-07\r\n] 2006.285.13:14:26.17#ibcon#*before write, iclass 19, count 2 2006.285.13:14:26.17#ibcon#enter sib2, iclass 19, count 2 2006.285.13:14:26.17#ibcon#flushed, iclass 19, count 2 2006.285.13:14:26.17#ibcon#about to write, iclass 19, count 2 2006.285.13:14:26.17#ibcon#wrote, iclass 19, count 2 2006.285.13:14:26.17#ibcon#about to read 3, iclass 19, count 2 2006.285.13:14:26.20#ibcon#read 3, iclass 19, count 2 2006.285.13:14:26.20#ibcon#about to read 4, iclass 19, count 2 2006.285.13:14:26.20#ibcon#read 4, iclass 19, count 2 2006.285.13:14:26.20#ibcon#about to read 5, iclass 19, count 2 2006.285.13:14:26.20#ibcon#read 5, iclass 19, count 2 2006.285.13:14:26.20#ibcon#about to read 6, iclass 19, count 2 2006.285.13:14:26.20#ibcon#read 6, iclass 19, count 2 2006.285.13:14:26.20#ibcon#end of sib2, iclass 19, count 2 2006.285.13:14:26.20#ibcon#*after write, iclass 19, count 2 2006.285.13:14:26.20#ibcon#*before return 0, iclass 19, count 2 2006.285.13:14:26.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:14:26.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:14:26.20#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.13:14:26.20#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:26.20#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:14:26.32#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:14:26.32#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:14:26.32#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:14:26.32#ibcon#first serial, iclass 19, count 0 2006.285.13:14:26.32#ibcon#enter sib2, iclass 19, count 0 2006.285.13:14:26.32#ibcon#flushed, iclass 19, count 0 2006.285.13:14:26.32#ibcon#about to write, iclass 19, count 0 2006.285.13:14:26.32#ibcon#wrote, iclass 19, count 0 2006.285.13:14:26.32#ibcon#about to read 3, iclass 19, count 0 2006.285.13:14:26.34#ibcon#read 3, iclass 19, count 0 2006.285.13:14:26.34#ibcon#about to read 4, iclass 19, count 0 2006.285.13:14:26.34#ibcon#read 4, iclass 19, count 0 2006.285.13:14:26.34#ibcon#about to read 5, iclass 19, count 0 2006.285.13:14:26.34#ibcon#read 5, iclass 19, count 0 2006.285.13:14:26.34#ibcon#about to read 6, iclass 19, count 0 2006.285.13:14:26.34#ibcon#read 6, iclass 19, count 0 2006.285.13:14:26.34#ibcon#end of sib2, iclass 19, count 0 2006.285.13:14:26.34#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:14:26.34#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:14:26.34#ibcon#[25=USB\r\n] 2006.285.13:14:26.34#ibcon#*before write, iclass 19, count 0 2006.285.13:14:26.34#ibcon#enter sib2, iclass 19, count 0 2006.285.13:14:26.34#ibcon#flushed, iclass 19, count 0 2006.285.13:14:26.34#ibcon#about to write, iclass 19, count 0 2006.285.13:14:26.34#ibcon#wrote, iclass 19, count 0 2006.285.13:14:26.34#ibcon#about to read 3, iclass 19, count 0 2006.285.13:14:26.37#ibcon#read 3, iclass 19, count 0 2006.285.13:14:26.37#ibcon#about to read 4, iclass 19, count 0 2006.285.13:14:26.37#ibcon#read 4, iclass 19, count 0 2006.285.13:14:26.37#ibcon#about to read 5, iclass 19, count 0 2006.285.13:14:26.37#ibcon#read 5, iclass 19, count 0 2006.285.13:14:26.37#ibcon#about to read 6, iclass 19, count 0 2006.285.13:14:26.37#ibcon#read 6, iclass 19, count 0 2006.285.13:14:26.37#ibcon#end of sib2, iclass 19, count 0 2006.285.13:14:26.37#ibcon#*after write, iclass 19, count 0 2006.285.13:14:26.37#ibcon#*before return 0, iclass 19, count 0 2006.285.13:14:26.37#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:14:26.37#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:14:26.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:14:26.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:14:26.37$vck44/valo=2,534.99 2006.285.13:14:26.37#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.13:14:26.37#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.13:14:26.37#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:26.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:14:26.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:14:26.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:14:26.37#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:14:26.37#ibcon#first serial, iclass 21, count 0 2006.285.13:14:26.37#ibcon#enter sib2, iclass 21, count 0 2006.285.13:14:26.37#ibcon#flushed, iclass 21, count 0 2006.285.13:14:26.37#ibcon#about to write, iclass 21, count 0 2006.285.13:14:26.37#ibcon#wrote, iclass 21, count 0 2006.285.13:14:26.37#ibcon#about to read 3, iclass 21, count 0 2006.285.13:14:26.39#ibcon#read 3, iclass 21, count 0 2006.285.13:14:26.39#ibcon#about to read 4, iclass 21, count 0 2006.285.13:14:26.39#ibcon#read 4, iclass 21, count 0 2006.285.13:14:26.39#ibcon#about to read 5, iclass 21, count 0 2006.285.13:14:26.39#ibcon#read 5, iclass 21, count 0 2006.285.13:14:26.39#ibcon#about to read 6, iclass 21, count 0 2006.285.13:14:26.39#ibcon#read 6, iclass 21, count 0 2006.285.13:14:26.39#ibcon#end of sib2, iclass 21, count 0 2006.285.13:14:26.39#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:14:26.39#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:14:26.39#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:14:26.39#ibcon#*before write, iclass 21, count 0 2006.285.13:14:26.39#ibcon#enter sib2, iclass 21, count 0 2006.285.13:14:26.39#ibcon#flushed, iclass 21, count 0 2006.285.13:14:26.39#ibcon#about to write, iclass 21, count 0 2006.285.13:14:26.39#ibcon#wrote, iclass 21, count 0 2006.285.13:14:26.39#ibcon#about to read 3, iclass 21, count 0 2006.285.13:14:26.43#ibcon#read 3, iclass 21, count 0 2006.285.13:14:26.43#ibcon#about to read 4, iclass 21, count 0 2006.285.13:14:26.43#ibcon#read 4, iclass 21, count 0 2006.285.13:14:26.43#ibcon#about to read 5, iclass 21, count 0 2006.285.13:14:26.43#ibcon#read 5, iclass 21, count 0 2006.285.13:14:26.43#ibcon#about to read 6, iclass 21, count 0 2006.285.13:14:26.43#ibcon#read 6, iclass 21, count 0 2006.285.13:14:26.43#ibcon#end of sib2, iclass 21, count 0 2006.285.13:14:26.43#ibcon#*after write, iclass 21, count 0 2006.285.13:14:26.43#ibcon#*before return 0, iclass 21, count 0 2006.285.13:14:26.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:14:26.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:14:26.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:14:26.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:14:26.43$vck44/va=2,6 2006.285.13:14:26.43#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.13:14:26.43#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.13:14:26.43#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:26.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:14:26.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:14:26.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:14:26.49#ibcon#enter wrdev, iclass 23, count 2 2006.285.13:14:26.49#ibcon#first serial, iclass 23, count 2 2006.285.13:14:26.49#ibcon#enter sib2, iclass 23, count 2 2006.285.13:14:26.49#ibcon#flushed, iclass 23, count 2 2006.285.13:14:26.49#ibcon#about to write, iclass 23, count 2 2006.285.13:14:26.49#ibcon#wrote, iclass 23, count 2 2006.285.13:14:26.49#ibcon#about to read 3, iclass 23, count 2 2006.285.13:14:26.51#ibcon#read 3, iclass 23, count 2 2006.285.13:14:26.51#ibcon#about to read 4, iclass 23, count 2 2006.285.13:14:26.51#ibcon#read 4, iclass 23, count 2 2006.285.13:14:26.51#ibcon#about to read 5, iclass 23, count 2 2006.285.13:14:26.51#ibcon#read 5, iclass 23, count 2 2006.285.13:14:26.51#ibcon#about to read 6, iclass 23, count 2 2006.285.13:14:26.51#ibcon#read 6, iclass 23, count 2 2006.285.13:14:26.51#ibcon#end of sib2, iclass 23, count 2 2006.285.13:14:26.51#ibcon#*mode == 0, iclass 23, count 2 2006.285.13:14:26.51#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.13:14:26.51#ibcon#[25=AT02-06\r\n] 2006.285.13:14:26.51#ibcon#*before write, iclass 23, count 2 2006.285.13:14:26.51#ibcon#enter sib2, iclass 23, count 2 2006.285.13:14:26.51#ibcon#flushed, iclass 23, count 2 2006.285.13:14:26.51#ibcon#about to write, iclass 23, count 2 2006.285.13:14:26.51#ibcon#wrote, iclass 23, count 2 2006.285.13:14:26.51#ibcon#about to read 3, iclass 23, count 2 2006.285.13:14:26.54#ibcon#read 3, iclass 23, count 2 2006.285.13:14:26.54#ibcon#about to read 4, iclass 23, count 2 2006.285.13:14:26.54#ibcon#read 4, iclass 23, count 2 2006.285.13:14:26.54#ibcon#about to read 5, iclass 23, count 2 2006.285.13:14:26.54#ibcon#read 5, iclass 23, count 2 2006.285.13:14:26.54#ibcon#about to read 6, iclass 23, count 2 2006.285.13:14:26.54#ibcon#read 6, iclass 23, count 2 2006.285.13:14:26.54#ibcon#end of sib2, iclass 23, count 2 2006.285.13:14:26.54#ibcon#*after write, iclass 23, count 2 2006.285.13:14:26.54#ibcon#*before return 0, iclass 23, count 2 2006.285.13:14:26.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:14:26.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:14:26.54#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.13:14:26.54#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:26.54#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:14:26.66#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:14:26.66#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:14:26.66#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:14:26.66#ibcon#first serial, iclass 23, count 0 2006.285.13:14:26.66#ibcon#enter sib2, iclass 23, count 0 2006.285.13:14:26.66#ibcon#flushed, iclass 23, count 0 2006.285.13:14:26.66#ibcon#about to write, iclass 23, count 0 2006.285.13:14:26.66#ibcon#wrote, iclass 23, count 0 2006.285.13:14:26.66#ibcon#about to read 3, iclass 23, count 0 2006.285.13:14:26.68#ibcon#read 3, iclass 23, count 0 2006.285.13:14:26.68#ibcon#about to read 4, iclass 23, count 0 2006.285.13:14:26.68#ibcon#read 4, iclass 23, count 0 2006.285.13:14:26.68#ibcon#about to read 5, iclass 23, count 0 2006.285.13:14:26.68#ibcon#read 5, iclass 23, count 0 2006.285.13:14:26.68#ibcon#about to read 6, iclass 23, count 0 2006.285.13:14:26.68#ibcon#read 6, iclass 23, count 0 2006.285.13:14:26.68#ibcon#end of sib2, iclass 23, count 0 2006.285.13:14:26.68#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:14:26.68#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:14:26.68#ibcon#[25=USB\r\n] 2006.285.13:14:26.68#ibcon#*before write, iclass 23, count 0 2006.285.13:14:26.68#ibcon#enter sib2, iclass 23, count 0 2006.285.13:14:26.68#ibcon#flushed, iclass 23, count 0 2006.285.13:14:26.68#ibcon#about to write, iclass 23, count 0 2006.285.13:14:26.68#ibcon#wrote, iclass 23, count 0 2006.285.13:14:26.68#ibcon#about to read 3, iclass 23, count 0 2006.285.13:14:26.71#ibcon#read 3, iclass 23, count 0 2006.285.13:14:26.71#ibcon#about to read 4, iclass 23, count 0 2006.285.13:14:26.71#ibcon#read 4, iclass 23, count 0 2006.285.13:14:26.71#ibcon#about to read 5, iclass 23, count 0 2006.285.13:14:26.71#ibcon#read 5, iclass 23, count 0 2006.285.13:14:26.71#ibcon#about to read 6, iclass 23, count 0 2006.285.13:14:26.71#ibcon#read 6, iclass 23, count 0 2006.285.13:14:26.71#ibcon#end of sib2, iclass 23, count 0 2006.285.13:14:26.71#ibcon#*after write, iclass 23, count 0 2006.285.13:14:26.71#ibcon#*before return 0, iclass 23, count 0 2006.285.13:14:26.71#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:14:26.71#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:14:26.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:14:26.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:14:26.71$vck44/valo=3,564.99 2006.285.13:14:26.71#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.13:14:26.71#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.13:14:26.71#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:26.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:14:26.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:14:26.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:14:26.71#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:14:26.71#ibcon#first serial, iclass 25, count 0 2006.285.13:14:26.71#ibcon#enter sib2, iclass 25, count 0 2006.285.13:14:26.71#ibcon#flushed, iclass 25, count 0 2006.285.13:14:26.71#ibcon#about to write, iclass 25, count 0 2006.285.13:14:26.71#ibcon#wrote, iclass 25, count 0 2006.285.13:14:26.71#ibcon#about to read 3, iclass 25, count 0 2006.285.13:14:27.24#ibcon#read 3, iclass 25, count 0 2006.285.13:14:27.24#ibcon#about to read 4, iclass 25, count 0 2006.285.13:14:27.24#ibcon#read 4, iclass 25, count 0 2006.285.13:14:27.24#ibcon#about to read 5, iclass 25, count 0 2006.285.13:14:27.24#ibcon#read 5, iclass 25, count 0 2006.285.13:14:27.24#ibcon#about to read 6, iclass 25, count 0 2006.285.13:14:27.24#ibcon#read 6, iclass 25, count 0 2006.285.13:14:27.24#ibcon#end of sib2, iclass 25, count 0 2006.285.13:14:27.24#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:14:27.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:14:27.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:14:27.24#ibcon#*before write, iclass 25, count 0 2006.285.13:14:27.24#ibcon#enter sib2, iclass 25, count 0 2006.285.13:14:27.24#ibcon#flushed, iclass 25, count 0 2006.285.13:14:27.24#ibcon#about to write, iclass 25, count 0 2006.285.13:14:27.24#ibcon#wrote, iclass 25, count 0 2006.285.13:14:27.24#ibcon#about to read 3, iclass 25, count 0 2006.285.13:14:27.28#ibcon#read 3, iclass 25, count 0 2006.285.13:14:27.28#ibcon#about to read 4, iclass 25, count 0 2006.285.13:14:27.28#ibcon#read 4, iclass 25, count 0 2006.285.13:14:27.28#ibcon#about to read 5, iclass 25, count 0 2006.285.13:14:27.28#ibcon#read 5, iclass 25, count 0 2006.285.13:14:27.28#ibcon#about to read 6, iclass 25, count 0 2006.285.13:14:27.28#ibcon#read 6, iclass 25, count 0 2006.285.13:14:27.28#ibcon#end of sib2, iclass 25, count 0 2006.285.13:14:27.28#ibcon#*after write, iclass 25, count 0 2006.285.13:14:27.28#ibcon#*before return 0, iclass 25, count 0 2006.285.13:14:27.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:14:27.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:14:27.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:14:27.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:14:27.28$vck44/va=3,7 2006.285.13:14:27.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.13:14:27.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.13:14:27.28#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:27.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:14:27.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:14:27.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:14:27.28#ibcon#enter wrdev, iclass 27, count 2 2006.285.13:14:27.28#ibcon#first serial, iclass 27, count 2 2006.285.13:14:27.28#ibcon#enter sib2, iclass 27, count 2 2006.285.13:14:27.28#ibcon#flushed, iclass 27, count 2 2006.285.13:14:27.28#ibcon#about to write, iclass 27, count 2 2006.285.13:14:27.28#ibcon#wrote, iclass 27, count 2 2006.285.13:14:27.28#ibcon#about to read 3, iclass 27, count 2 2006.285.13:14:27.30#ibcon#read 3, iclass 27, count 2 2006.285.13:14:27.30#ibcon#about to read 4, iclass 27, count 2 2006.285.13:14:27.30#ibcon#read 4, iclass 27, count 2 2006.285.13:14:27.30#ibcon#about to read 5, iclass 27, count 2 2006.285.13:14:27.30#ibcon#read 5, iclass 27, count 2 2006.285.13:14:27.30#ibcon#about to read 6, iclass 27, count 2 2006.285.13:14:27.30#ibcon#read 6, iclass 27, count 2 2006.285.13:14:27.30#ibcon#end of sib2, iclass 27, count 2 2006.285.13:14:27.30#ibcon#*mode == 0, iclass 27, count 2 2006.285.13:14:27.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.13:14:27.30#ibcon#[25=AT03-07\r\n] 2006.285.13:14:27.30#ibcon#*before write, iclass 27, count 2 2006.285.13:14:27.30#ibcon#enter sib2, iclass 27, count 2 2006.285.13:14:27.30#ibcon#flushed, iclass 27, count 2 2006.285.13:14:27.30#ibcon#about to write, iclass 27, count 2 2006.285.13:14:27.30#ibcon#wrote, iclass 27, count 2 2006.285.13:14:27.30#ibcon#about to read 3, iclass 27, count 2 2006.285.13:14:27.33#ibcon#read 3, iclass 27, count 2 2006.285.13:14:27.33#ibcon#about to read 4, iclass 27, count 2 2006.285.13:14:27.33#ibcon#read 4, iclass 27, count 2 2006.285.13:14:27.33#ibcon#about to read 5, iclass 27, count 2 2006.285.13:14:27.33#ibcon#read 5, iclass 27, count 2 2006.285.13:14:27.33#ibcon#about to read 6, iclass 27, count 2 2006.285.13:14:27.33#ibcon#read 6, iclass 27, count 2 2006.285.13:14:27.33#ibcon#end of sib2, iclass 27, count 2 2006.285.13:14:27.33#ibcon#*after write, iclass 27, count 2 2006.285.13:14:27.33#ibcon#*before return 0, iclass 27, count 2 2006.285.13:14:27.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:14:27.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:14:27.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.13:14:27.33#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:27.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:14:27.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:14:27.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:14:27.45#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:14:27.45#ibcon#first serial, iclass 27, count 0 2006.285.13:14:27.45#ibcon#enter sib2, iclass 27, count 0 2006.285.13:14:27.45#ibcon#flushed, iclass 27, count 0 2006.285.13:14:27.45#ibcon#about to write, iclass 27, count 0 2006.285.13:14:27.45#ibcon#wrote, iclass 27, count 0 2006.285.13:14:27.45#ibcon#about to read 3, iclass 27, count 0 2006.285.13:14:27.47#ibcon#read 3, iclass 27, count 0 2006.285.13:14:27.47#ibcon#about to read 4, iclass 27, count 0 2006.285.13:14:27.47#ibcon#read 4, iclass 27, count 0 2006.285.13:14:27.47#ibcon#about to read 5, iclass 27, count 0 2006.285.13:14:27.47#ibcon#read 5, iclass 27, count 0 2006.285.13:14:27.47#ibcon#about to read 6, iclass 27, count 0 2006.285.13:14:27.47#ibcon#read 6, iclass 27, count 0 2006.285.13:14:27.47#ibcon#end of sib2, iclass 27, count 0 2006.285.13:14:27.47#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:14:27.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:14:27.47#ibcon#[25=USB\r\n] 2006.285.13:14:27.47#ibcon#*before write, iclass 27, count 0 2006.285.13:14:27.47#ibcon#enter sib2, iclass 27, count 0 2006.285.13:14:27.47#ibcon#flushed, iclass 27, count 0 2006.285.13:14:27.47#ibcon#about to write, iclass 27, count 0 2006.285.13:14:27.47#ibcon#wrote, iclass 27, count 0 2006.285.13:14:27.47#ibcon#about to read 3, iclass 27, count 0 2006.285.13:14:27.50#ibcon#read 3, iclass 27, count 0 2006.285.13:14:27.50#ibcon#about to read 4, iclass 27, count 0 2006.285.13:14:27.50#ibcon#read 4, iclass 27, count 0 2006.285.13:14:27.50#ibcon#about to read 5, iclass 27, count 0 2006.285.13:14:27.50#ibcon#read 5, iclass 27, count 0 2006.285.13:14:27.50#ibcon#about to read 6, iclass 27, count 0 2006.285.13:14:27.50#ibcon#read 6, iclass 27, count 0 2006.285.13:14:27.50#ibcon#end of sib2, iclass 27, count 0 2006.285.13:14:27.50#ibcon#*after write, iclass 27, count 0 2006.285.13:14:27.50#ibcon#*before return 0, iclass 27, count 0 2006.285.13:14:27.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:14:27.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:14:27.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:14:27.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:14:27.50$vck44/valo=4,624.99 2006.285.13:14:27.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.13:14:27.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.13:14:27.50#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:27.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:14:27.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:14:27.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:14:27.50#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:14:27.50#ibcon#first serial, iclass 29, count 0 2006.285.13:14:27.50#ibcon#enter sib2, iclass 29, count 0 2006.285.13:14:27.50#ibcon#flushed, iclass 29, count 0 2006.285.13:14:27.50#ibcon#about to write, iclass 29, count 0 2006.285.13:14:27.50#ibcon#wrote, iclass 29, count 0 2006.285.13:14:27.50#ibcon#about to read 3, iclass 29, count 0 2006.285.13:14:27.52#ibcon#read 3, iclass 29, count 0 2006.285.13:14:27.60#ibcon#about to read 4, iclass 29, count 0 2006.285.13:14:27.60#ibcon#read 4, iclass 29, count 0 2006.285.13:14:27.60#ibcon#about to read 5, iclass 29, count 0 2006.285.13:14:27.60#ibcon#read 5, iclass 29, count 0 2006.285.13:14:27.60#ibcon#about to read 6, iclass 29, count 0 2006.285.13:14:27.60#ibcon#read 6, iclass 29, count 0 2006.285.13:14:27.60#ibcon#end of sib2, iclass 29, count 0 2006.285.13:14:27.60#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:14:27.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:14:27.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:14:27.60#ibcon#*before write, iclass 29, count 0 2006.285.13:14:27.60#ibcon#enter sib2, iclass 29, count 0 2006.285.13:14:27.60#ibcon#flushed, iclass 29, count 0 2006.285.13:14:27.60#ibcon#about to write, iclass 29, count 0 2006.285.13:14:27.60#ibcon#wrote, iclass 29, count 0 2006.285.13:14:27.60#ibcon#about to read 3, iclass 29, count 0 2006.285.13:14:27.64#ibcon#read 3, iclass 29, count 0 2006.285.13:14:27.64#ibcon#about to read 4, iclass 29, count 0 2006.285.13:14:27.64#ibcon#read 4, iclass 29, count 0 2006.285.13:14:27.64#ibcon#about to read 5, iclass 29, count 0 2006.285.13:14:27.64#ibcon#read 5, iclass 29, count 0 2006.285.13:14:27.64#ibcon#about to read 6, iclass 29, count 0 2006.285.13:14:27.64#ibcon#read 6, iclass 29, count 0 2006.285.13:14:27.64#ibcon#end of sib2, iclass 29, count 0 2006.285.13:14:27.64#ibcon#*after write, iclass 29, count 0 2006.285.13:14:27.64#ibcon#*before return 0, iclass 29, count 0 2006.285.13:14:27.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:14:27.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:14:27.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:14:27.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:14:27.64$vck44/va=4,6 2006.285.13:14:27.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.13:14:27.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.13:14:27.64#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:27.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:14:27.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:14:27.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:14:27.64#ibcon#enter wrdev, iclass 31, count 2 2006.285.13:14:27.64#ibcon#first serial, iclass 31, count 2 2006.285.13:14:27.64#ibcon#enter sib2, iclass 31, count 2 2006.285.13:14:27.64#ibcon#flushed, iclass 31, count 2 2006.285.13:14:27.64#ibcon#about to write, iclass 31, count 2 2006.285.13:14:27.64#ibcon#wrote, iclass 31, count 2 2006.285.13:14:27.64#ibcon#about to read 3, iclass 31, count 2 2006.285.13:14:27.66#ibcon#read 3, iclass 31, count 2 2006.285.13:14:27.66#ibcon#about to read 4, iclass 31, count 2 2006.285.13:14:27.66#ibcon#read 4, iclass 31, count 2 2006.285.13:14:27.66#ibcon#about to read 5, iclass 31, count 2 2006.285.13:14:27.66#ibcon#read 5, iclass 31, count 2 2006.285.13:14:27.66#ibcon#about to read 6, iclass 31, count 2 2006.285.13:14:27.66#ibcon#read 6, iclass 31, count 2 2006.285.13:14:27.66#ibcon#end of sib2, iclass 31, count 2 2006.285.13:14:27.66#ibcon#*mode == 0, iclass 31, count 2 2006.285.13:14:27.66#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.13:14:27.66#ibcon#[25=AT04-06\r\n] 2006.285.13:14:27.66#ibcon#*before write, iclass 31, count 2 2006.285.13:14:27.66#ibcon#enter sib2, iclass 31, count 2 2006.285.13:14:27.66#ibcon#flushed, iclass 31, count 2 2006.285.13:14:27.66#ibcon#about to write, iclass 31, count 2 2006.285.13:14:27.66#ibcon#wrote, iclass 31, count 2 2006.285.13:14:27.66#ibcon#about to read 3, iclass 31, count 2 2006.285.13:14:27.69#ibcon#read 3, iclass 31, count 2 2006.285.13:14:27.69#ibcon#about to read 4, iclass 31, count 2 2006.285.13:14:27.69#ibcon#read 4, iclass 31, count 2 2006.285.13:14:27.69#ibcon#about to read 5, iclass 31, count 2 2006.285.13:14:27.69#ibcon#read 5, iclass 31, count 2 2006.285.13:14:27.69#ibcon#about to read 6, iclass 31, count 2 2006.285.13:14:27.69#ibcon#read 6, iclass 31, count 2 2006.285.13:14:27.69#ibcon#end of sib2, iclass 31, count 2 2006.285.13:14:27.69#ibcon#*after write, iclass 31, count 2 2006.285.13:14:27.69#ibcon#*before return 0, iclass 31, count 2 2006.285.13:14:27.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:14:27.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:14:27.69#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.13:14:27.69#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:27.69#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:14:27.81#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:14:27.81#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:14:27.81#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:14:27.81#ibcon#first serial, iclass 31, count 0 2006.285.13:14:27.81#ibcon#enter sib2, iclass 31, count 0 2006.285.13:14:27.81#ibcon#flushed, iclass 31, count 0 2006.285.13:14:27.81#ibcon#about to write, iclass 31, count 0 2006.285.13:14:27.81#ibcon#wrote, iclass 31, count 0 2006.285.13:14:27.81#ibcon#about to read 3, iclass 31, count 0 2006.285.13:14:27.83#ibcon#read 3, iclass 31, count 0 2006.285.13:14:27.83#ibcon#about to read 4, iclass 31, count 0 2006.285.13:14:27.83#ibcon#read 4, iclass 31, count 0 2006.285.13:14:27.83#ibcon#about to read 5, iclass 31, count 0 2006.285.13:14:27.83#ibcon#read 5, iclass 31, count 0 2006.285.13:14:27.83#ibcon#about to read 6, iclass 31, count 0 2006.285.13:14:27.83#ibcon#read 6, iclass 31, count 0 2006.285.13:14:27.83#ibcon#end of sib2, iclass 31, count 0 2006.285.13:14:27.83#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:14:27.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:14:27.83#ibcon#[25=USB\r\n] 2006.285.13:14:27.83#ibcon#*before write, iclass 31, count 0 2006.285.13:14:27.83#ibcon#enter sib2, iclass 31, count 0 2006.285.13:14:27.83#ibcon#flushed, iclass 31, count 0 2006.285.13:14:27.83#ibcon#about to write, iclass 31, count 0 2006.285.13:14:27.83#ibcon#wrote, iclass 31, count 0 2006.285.13:14:27.83#ibcon#about to read 3, iclass 31, count 0 2006.285.13:14:27.86#ibcon#read 3, iclass 31, count 0 2006.285.13:14:27.86#ibcon#about to read 4, iclass 31, count 0 2006.285.13:14:27.86#ibcon#read 4, iclass 31, count 0 2006.285.13:14:27.86#ibcon#about to read 5, iclass 31, count 0 2006.285.13:14:27.86#ibcon#read 5, iclass 31, count 0 2006.285.13:14:27.86#ibcon#about to read 6, iclass 31, count 0 2006.285.13:14:27.86#ibcon#read 6, iclass 31, count 0 2006.285.13:14:27.86#ibcon#end of sib2, iclass 31, count 0 2006.285.13:14:27.86#ibcon#*after write, iclass 31, count 0 2006.285.13:14:27.86#ibcon#*before return 0, iclass 31, count 0 2006.285.13:14:27.86#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:14:27.86#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:14:27.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:14:27.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:14:27.86$vck44/valo=5,734.99 2006.285.13:14:27.86#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.13:14:27.86#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.13:14:27.86#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:27.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:14:27.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:14:27.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:14:27.86#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:14:27.86#ibcon#first serial, iclass 33, count 0 2006.285.13:14:27.86#ibcon#enter sib2, iclass 33, count 0 2006.285.13:14:27.86#ibcon#flushed, iclass 33, count 0 2006.285.13:14:27.86#ibcon#about to write, iclass 33, count 0 2006.285.13:14:27.86#ibcon#wrote, iclass 33, count 0 2006.285.13:14:27.86#ibcon#about to read 3, iclass 33, count 0 2006.285.13:14:27.88#ibcon#read 3, iclass 33, count 0 2006.285.13:14:27.88#ibcon#about to read 4, iclass 33, count 0 2006.285.13:14:27.88#ibcon#read 4, iclass 33, count 0 2006.285.13:14:27.88#ibcon#about to read 5, iclass 33, count 0 2006.285.13:14:27.88#ibcon#read 5, iclass 33, count 0 2006.285.13:14:27.88#ibcon#about to read 6, iclass 33, count 0 2006.285.13:14:27.88#ibcon#read 6, iclass 33, count 0 2006.285.13:14:27.88#ibcon#end of sib2, iclass 33, count 0 2006.285.13:14:27.88#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:14:27.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:14:27.88#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:14:27.88#ibcon#*before write, iclass 33, count 0 2006.285.13:14:27.88#ibcon#enter sib2, iclass 33, count 0 2006.285.13:14:27.88#ibcon#flushed, iclass 33, count 0 2006.285.13:14:27.88#ibcon#about to write, iclass 33, count 0 2006.285.13:14:27.88#ibcon#wrote, iclass 33, count 0 2006.285.13:14:27.88#ibcon#about to read 3, iclass 33, count 0 2006.285.13:14:27.92#ibcon#read 3, iclass 33, count 0 2006.285.13:14:27.92#ibcon#about to read 4, iclass 33, count 0 2006.285.13:14:27.92#ibcon#read 4, iclass 33, count 0 2006.285.13:14:27.92#ibcon#about to read 5, iclass 33, count 0 2006.285.13:14:27.92#ibcon#read 5, iclass 33, count 0 2006.285.13:14:27.92#ibcon#about to read 6, iclass 33, count 0 2006.285.13:14:27.92#ibcon#read 6, iclass 33, count 0 2006.285.13:14:27.92#ibcon#end of sib2, iclass 33, count 0 2006.285.13:14:27.92#ibcon#*after write, iclass 33, count 0 2006.285.13:14:27.92#ibcon#*before return 0, iclass 33, count 0 2006.285.13:14:27.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:14:27.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:14:27.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:14:27.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:14:27.92$vck44/va=5,3 2006.285.13:14:27.92#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.13:14:27.92#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.13:14:27.92#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:27.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:14:27.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:14:27.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:14:27.98#ibcon#enter wrdev, iclass 35, count 2 2006.285.13:14:27.98#ibcon#first serial, iclass 35, count 2 2006.285.13:14:27.98#ibcon#enter sib2, iclass 35, count 2 2006.285.13:14:27.98#ibcon#flushed, iclass 35, count 2 2006.285.13:14:27.98#ibcon#about to write, iclass 35, count 2 2006.285.13:14:27.98#ibcon#wrote, iclass 35, count 2 2006.285.13:14:27.98#ibcon#about to read 3, iclass 35, count 2 2006.285.13:14:28.00#ibcon#read 3, iclass 35, count 2 2006.285.13:14:28.00#ibcon#about to read 4, iclass 35, count 2 2006.285.13:14:28.00#ibcon#read 4, iclass 35, count 2 2006.285.13:14:28.00#ibcon#about to read 5, iclass 35, count 2 2006.285.13:14:28.00#ibcon#read 5, iclass 35, count 2 2006.285.13:14:28.00#ibcon#about to read 6, iclass 35, count 2 2006.285.13:14:28.00#ibcon#read 6, iclass 35, count 2 2006.285.13:14:28.00#ibcon#end of sib2, iclass 35, count 2 2006.285.13:14:28.00#ibcon#*mode == 0, iclass 35, count 2 2006.285.13:14:28.00#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.13:14:28.00#ibcon#[25=AT05-03\r\n] 2006.285.13:14:28.00#ibcon#*before write, iclass 35, count 2 2006.285.13:14:28.00#ibcon#enter sib2, iclass 35, count 2 2006.285.13:14:28.00#ibcon#flushed, iclass 35, count 2 2006.285.13:14:28.00#ibcon#about to write, iclass 35, count 2 2006.285.13:14:28.00#ibcon#wrote, iclass 35, count 2 2006.285.13:14:28.00#ibcon#about to read 3, iclass 35, count 2 2006.285.13:14:28.03#ibcon#read 3, iclass 35, count 2 2006.285.13:14:28.03#ibcon#about to read 4, iclass 35, count 2 2006.285.13:14:28.03#ibcon#read 4, iclass 35, count 2 2006.285.13:14:28.03#ibcon#about to read 5, iclass 35, count 2 2006.285.13:14:28.03#ibcon#read 5, iclass 35, count 2 2006.285.13:14:28.03#ibcon#about to read 6, iclass 35, count 2 2006.285.13:14:28.03#ibcon#read 6, iclass 35, count 2 2006.285.13:14:28.03#ibcon#end of sib2, iclass 35, count 2 2006.285.13:14:28.03#ibcon#*after write, iclass 35, count 2 2006.285.13:14:28.03#ibcon#*before return 0, iclass 35, count 2 2006.285.13:14:28.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:14:28.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:14:28.03#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.13:14:28.03#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:28.03#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:14:28.15#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:14:28.15#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:14:28.15#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:14:28.15#ibcon#first serial, iclass 35, count 0 2006.285.13:14:28.15#ibcon#enter sib2, iclass 35, count 0 2006.285.13:14:28.15#ibcon#flushed, iclass 35, count 0 2006.285.13:14:28.15#ibcon#about to write, iclass 35, count 0 2006.285.13:14:28.15#ibcon#wrote, iclass 35, count 0 2006.285.13:14:28.15#ibcon#about to read 3, iclass 35, count 0 2006.285.13:14:28.17#ibcon#read 3, iclass 35, count 0 2006.285.13:14:28.17#ibcon#about to read 4, iclass 35, count 0 2006.285.13:14:28.17#ibcon#read 4, iclass 35, count 0 2006.285.13:14:28.17#ibcon#about to read 5, iclass 35, count 0 2006.285.13:14:28.17#ibcon#read 5, iclass 35, count 0 2006.285.13:14:28.17#ibcon#about to read 6, iclass 35, count 0 2006.285.13:14:28.17#ibcon#read 6, iclass 35, count 0 2006.285.13:14:28.17#ibcon#end of sib2, iclass 35, count 0 2006.285.13:14:28.17#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:14:28.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:14:28.17#ibcon#[25=USB\r\n] 2006.285.13:14:28.17#ibcon#*before write, iclass 35, count 0 2006.285.13:14:28.17#ibcon#enter sib2, iclass 35, count 0 2006.285.13:14:28.17#ibcon#flushed, iclass 35, count 0 2006.285.13:14:28.17#ibcon#about to write, iclass 35, count 0 2006.285.13:14:28.17#ibcon#wrote, iclass 35, count 0 2006.285.13:14:28.17#ibcon#about to read 3, iclass 35, count 0 2006.285.13:14:28.20#ibcon#read 3, iclass 35, count 0 2006.285.13:14:28.20#ibcon#about to read 4, iclass 35, count 0 2006.285.13:14:28.20#ibcon#read 4, iclass 35, count 0 2006.285.13:14:28.20#ibcon#about to read 5, iclass 35, count 0 2006.285.13:14:28.20#ibcon#read 5, iclass 35, count 0 2006.285.13:14:28.20#ibcon#about to read 6, iclass 35, count 0 2006.285.13:14:28.20#ibcon#read 6, iclass 35, count 0 2006.285.13:14:28.20#ibcon#end of sib2, iclass 35, count 0 2006.285.13:14:28.20#ibcon#*after write, iclass 35, count 0 2006.285.13:14:28.20#ibcon#*before return 0, iclass 35, count 0 2006.285.13:14:28.20#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:14:28.20#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:14:28.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:14:28.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:14:28.20$vck44/valo=6,814.99 2006.285.13:14:28.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.13:14:28.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.13:14:28.20#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:28.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:14:28.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:14:28.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:14:28.20#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:14:28.20#ibcon#first serial, iclass 37, count 0 2006.285.13:14:28.20#ibcon#enter sib2, iclass 37, count 0 2006.285.13:14:28.20#ibcon#flushed, iclass 37, count 0 2006.285.13:14:28.20#ibcon#about to write, iclass 37, count 0 2006.285.13:14:28.20#ibcon#wrote, iclass 37, count 0 2006.285.13:14:28.20#ibcon#about to read 3, iclass 37, count 0 2006.285.13:14:28.22#ibcon#read 3, iclass 37, count 0 2006.285.13:14:28.22#ibcon#about to read 4, iclass 37, count 0 2006.285.13:14:28.22#ibcon#read 4, iclass 37, count 0 2006.285.13:14:28.22#ibcon#about to read 5, iclass 37, count 0 2006.285.13:14:28.22#ibcon#read 5, iclass 37, count 0 2006.285.13:14:28.22#ibcon#about to read 6, iclass 37, count 0 2006.285.13:14:28.22#ibcon#read 6, iclass 37, count 0 2006.285.13:14:28.22#ibcon#end of sib2, iclass 37, count 0 2006.285.13:14:28.22#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:14:28.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:14:28.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:14:28.22#ibcon#*before write, iclass 37, count 0 2006.285.13:14:28.22#ibcon#enter sib2, iclass 37, count 0 2006.285.13:14:28.22#ibcon#flushed, iclass 37, count 0 2006.285.13:14:28.22#ibcon#about to write, iclass 37, count 0 2006.285.13:14:28.22#ibcon#wrote, iclass 37, count 0 2006.285.13:14:28.22#ibcon#about to read 3, iclass 37, count 0 2006.285.13:14:28.26#ibcon#read 3, iclass 37, count 0 2006.285.13:14:28.26#ibcon#about to read 4, iclass 37, count 0 2006.285.13:14:28.26#ibcon#read 4, iclass 37, count 0 2006.285.13:14:28.26#ibcon#about to read 5, iclass 37, count 0 2006.285.13:14:28.26#ibcon#read 5, iclass 37, count 0 2006.285.13:14:28.26#ibcon#about to read 6, iclass 37, count 0 2006.285.13:14:28.26#ibcon#read 6, iclass 37, count 0 2006.285.13:14:28.26#ibcon#end of sib2, iclass 37, count 0 2006.285.13:14:28.26#ibcon#*after write, iclass 37, count 0 2006.285.13:14:28.26#ibcon#*before return 0, iclass 37, count 0 2006.285.13:14:28.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:14:28.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:14:28.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:14:28.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:14:28.26$vck44/va=6,4 2006.285.13:14:28.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.13:14:28.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.13:14:28.26#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:28.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:14:28.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:14:28.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:14:28.32#ibcon#enter wrdev, iclass 39, count 2 2006.285.13:14:28.32#ibcon#first serial, iclass 39, count 2 2006.285.13:14:28.32#ibcon#enter sib2, iclass 39, count 2 2006.285.13:14:28.32#ibcon#flushed, iclass 39, count 2 2006.285.13:14:28.32#ibcon#about to write, iclass 39, count 2 2006.285.13:14:28.32#ibcon#wrote, iclass 39, count 2 2006.285.13:14:28.32#ibcon#about to read 3, iclass 39, count 2 2006.285.13:14:28.34#ibcon#read 3, iclass 39, count 2 2006.285.13:14:28.34#ibcon#about to read 4, iclass 39, count 2 2006.285.13:14:28.34#ibcon#read 4, iclass 39, count 2 2006.285.13:14:28.34#ibcon#about to read 5, iclass 39, count 2 2006.285.13:14:28.34#ibcon#read 5, iclass 39, count 2 2006.285.13:14:28.34#ibcon#about to read 6, iclass 39, count 2 2006.285.13:14:28.34#ibcon#read 6, iclass 39, count 2 2006.285.13:14:28.34#ibcon#end of sib2, iclass 39, count 2 2006.285.13:14:28.34#ibcon#*mode == 0, iclass 39, count 2 2006.285.13:14:28.34#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.13:14:28.34#ibcon#[25=AT06-04\r\n] 2006.285.13:14:28.34#ibcon#*before write, iclass 39, count 2 2006.285.13:14:28.34#ibcon#enter sib2, iclass 39, count 2 2006.285.13:14:28.34#ibcon#flushed, iclass 39, count 2 2006.285.13:14:28.34#ibcon#about to write, iclass 39, count 2 2006.285.13:14:28.34#ibcon#wrote, iclass 39, count 2 2006.285.13:14:28.34#ibcon#about to read 3, iclass 39, count 2 2006.285.13:14:28.37#ibcon#read 3, iclass 39, count 2 2006.285.13:14:28.37#ibcon#about to read 4, iclass 39, count 2 2006.285.13:14:28.37#ibcon#read 4, iclass 39, count 2 2006.285.13:14:28.37#ibcon#about to read 5, iclass 39, count 2 2006.285.13:14:28.37#ibcon#read 5, iclass 39, count 2 2006.285.13:14:28.37#ibcon#about to read 6, iclass 39, count 2 2006.285.13:14:28.37#ibcon#read 6, iclass 39, count 2 2006.285.13:14:28.37#ibcon#end of sib2, iclass 39, count 2 2006.285.13:14:28.37#ibcon#*after write, iclass 39, count 2 2006.285.13:14:28.37#ibcon#*before return 0, iclass 39, count 2 2006.285.13:14:28.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:14:28.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:14:28.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.13:14:28.37#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:28.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:14:28.49#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:14:28.49#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:14:28.49#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:14:28.49#ibcon#first serial, iclass 39, count 0 2006.285.13:14:28.49#ibcon#enter sib2, iclass 39, count 0 2006.285.13:14:28.49#ibcon#flushed, iclass 39, count 0 2006.285.13:14:28.49#ibcon#about to write, iclass 39, count 0 2006.285.13:14:28.49#ibcon#wrote, iclass 39, count 0 2006.285.13:14:28.49#ibcon#about to read 3, iclass 39, count 0 2006.285.13:14:28.51#ibcon#read 3, iclass 39, count 0 2006.285.13:14:28.51#ibcon#about to read 4, iclass 39, count 0 2006.285.13:14:28.51#ibcon#read 4, iclass 39, count 0 2006.285.13:14:28.51#ibcon#about to read 5, iclass 39, count 0 2006.285.13:14:28.51#ibcon#read 5, iclass 39, count 0 2006.285.13:14:28.51#ibcon#about to read 6, iclass 39, count 0 2006.285.13:14:28.51#ibcon#read 6, iclass 39, count 0 2006.285.13:14:28.51#ibcon#end of sib2, iclass 39, count 0 2006.285.13:14:28.51#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:14:28.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:14:28.51#ibcon#[25=USB\r\n] 2006.285.13:14:28.51#ibcon#*before write, iclass 39, count 0 2006.285.13:14:28.51#ibcon#enter sib2, iclass 39, count 0 2006.285.13:14:28.51#ibcon#flushed, iclass 39, count 0 2006.285.13:14:28.51#ibcon#about to write, iclass 39, count 0 2006.285.13:14:28.51#ibcon#wrote, iclass 39, count 0 2006.285.13:14:28.51#ibcon#about to read 3, iclass 39, count 0 2006.285.13:14:28.54#ibcon#read 3, iclass 39, count 0 2006.285.13:14:28.54#ibcon#about to read 4, iclass 39, count 0 2006.285.13:14:28.54#ibcon#read 4, iclass 39, count 0 2006.285.13:14:28.54#ibcon#about to read 5, iclass 39, count 0 2006.285.13:14:28.54#ibcon#read 5, iclass 39, count 0 2006.285.13:14:28.54#ibcon#about to read 6, iclass 39, count 0 2006.285.13:14:28.54#ibcon#read 6, iclass 39, count 0 2006.285.13:14:28.54#ibcon#end of sib2, iclass 39, count 0 2006.285.13:14:28.54#ibcon#*after write, iclass 39, count 0 2006.285.13:14:28.54#ibcon#*before return 0, iclass 39, count 0 2006.285.13:14:28.54#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:14:28.54#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:14:28.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:14:28.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:14:28.54$vck44/valo=7,864.99 2006.285.13:14:28.54#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.13:14:28.54#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.13:14:28.54#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:28.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:14:28.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:14:28.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:14:28.54#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:14:28.54#ibcon#first serial, iclass 3, count 0 2006.285.13:14:28.54#ibcon#enter sib2, iclass 3, count 0 2006.285.13:14:28.54#ibcon#flushed, iclass 3, count 0 2006.285.13:14:28.54#ibcon#about to write, iclass 3, count 0 2006.285.13:14:28.54#ibcon#wrote, iclass 3, count 0 2006.285.13:14:28.54#ibcon#about to read 3, iclass 3, count 0 2006.285.13:14:28.56#ibcon#read 3, iclass 3, count 0 2006.285.13:14:28.56#ibcon#about to read 4, iclass 3, count 0 2006.285.13:14:28.56#ibcon#read 4, iclass 3, count 0 2006.285.13:14:28.56#ibcon#about to read 5, iclass 3, count 0 2006.285.13:14:28.56#ibcon#read 5, iclass 3, count 0 2006.285.13:14:28.56#ibcon#about to read 6, iclass 3, count 0 2006.285.13:14:28.56#ibcon#read 6, iclass 3, count 0 2006.285.13:14:28.56#ibcon#end of sib2, iclass 3, count 0 2006.285.13:14:28.56#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:14:28.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:14:28.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:14:28.56#ibcon#*before write, iclass 3, count 0 2006.285.13:14:28.56#ibcon#enter sib2, iclass 3, count 0 2006.285.13:14:28.56#ibcon#flushed, iclass 3, count 0 2006.285.13:14:28.56#ibcon#about to write, iclass 3, count 0 2006.285.13:14:28.56#ibcon#wrote, iclass 3, count 0 2006.285.13:14:28.56#ibcon#about to read 3, iclass 3, count 0 2006.285.13:14:28.60#ibcon#read 3, iclass 3, count 0 2006.285.13:14:28.60#ibcon#about to read 4, iclass 3, count 0 2006.285.13:14:28.60#ibcon#read 4, iclass 3, count 0 2006.285.13:14:28.60#ibcon#about to read 5, iclass 3, count 0 2006.285.13:14:28.60#ibcon#read 5, iclass 3, count 0 2006.285.13:14:28.60#ibcon#about to read 6, iclass 3, count 0 2006.285.13:14:28.60#ibcon#read 6, iclass 3, count 0 2006.285.13:14:28.60#ibcon#end of sib2, iclass 3, count 0 2006.285.13:14:28.60#ibcon#*after write, iclass 3, count 0 2006.285.13:14:28.60#ibcon#*before return 0, iclass 3, count 0 2006.285.13:14:28.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:14:28.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:14:28.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:14:28.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:14:28.60$vck44/va=7,4 2006.285.13:14:28.60#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.13:14:28.60#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.13:14:28.60#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:28.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:14:28.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:14:28.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:14:28.66#ibcon#enter wrdev, iclass 5, count 2 2006.285.13:14:28.66#ibcon#first serial, iclass 5, count 2 2006.285.13:14:28.66#ibcon#enter sib2, iclass 5, count 2 2006.285.13:14:28.66#ibcon#flushed, iclass 5, count 2 2006.285.13:14:28.66#ibcon#about to write, iclass 5, count 2 2006.285.13:14:28.66#ibcon#wrote, iclass 5, count 2 2006.285.13:14:28.66#ibcon#about to read 3, iclass 5, count 2 2006.285.13:14:28.68#ibcon#read 3, iclass 5, count 2 2006.285.13:14:28.68#ibcon#about to read 4, iclass 5, count 2 2006.285.13:14:28.68#ibcon#read 4, iclass 5, count 2 2006.285.13:14:28.68#ibcon#about to read 5, iclass 5, count 2 2006.285.13:14:28.68#ibcon#read 5, iclass 5, count 2 2006.285.13:14:28.68#ibcon#about to read 6, iclass 5, count 2 2006.285.13:14:28.68#ibcon#read 6, iclass 5, count 2 2006.285.13:14:28.68#ibcon#end of sib2, iclass 5, count 2 2006.285.13:14:28.68#ibcon#*mode == 0, iclass 5, count 2 2006.285.13:14:28.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.13:14:28.68#ibcon#[25=AT07-04\r\n] 2006.285.13:14:28.68#ibcon#*before write, iclass 5, count 2 2006.285.13:14:28.68#ibcon#enter sib2, iclass 5, count 2 2006.285.13:14:28.68#ibcon#flushed, iclass 5, count 2 2006.285.13:14:28.68#ibcon#about to write, iclass 5, count 2 2006.285.13:14:28.68#ibcon#wrote, iclass 5, count 2 2006.285.13:14:28.68#ibcon#about to read 3, iclass 5, count 2 2006.285.13:14:28.71#ibcon#read 3, iclass 5, count 2 2006.285.13:14:28.71#ibcon#about to read 4, iclass 5, count 2 2006.285.13:14:28.71#ibcon#read 4, iclass 5, count 2 2006.285.13:14:28.71#ibcon#about to read 5, iclass 5, count 2 2006.285.13:14:28.71#ibcon#read 5, iclass 5, count 2 2006.285.13:14:28.71#ibcon#about to read 6, iclass 5, count 2 2006.285.13:14:28.71#ibcon#read 6, iclass 5, count 2 2006.285.13:14:28.71#ibcon#end of sib2, iclass 5, count 2 2006.285.13:14:28.71#ibcon#*after write, iclass 5, count 2 2006.285.13:14:28.71#ibcon#*before return 0, iclass 5, count 2 2006.285.13:14:28.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:14:28.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:14:28.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.13:14:28.71#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:28.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:14:28.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:14:28.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:14:28.83#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:14:28.83#ibcon#first serial, iclass 5, count 0 2006.285.13:14:28.83#ibcon#enter sib2, iclass 5, count 0 2006.285.13:14:28.83#ibcon#flushed, iclass 5, count 0 2006.285.13:14:28.83#ibcon#about to write, iclass 5, count 0 2006.285.13:14:28.83#ibcon#wrote, iclass 5, count 0 2006.285.13:14:28.83#ibcon#about to read 3, iclass 5, count 0 2006.285.13:14:28.85#ibcon#read 3, iclass 5, count 0 2006.285.13:14:28.85#ibcon#about to read 4, iclass 5, count 0 2006.285.13:14:28.85#ibcon#read 4, iclass 5, count 0 2006.285.13:14:29.37#ibcon#about to read 5, iclass 5, count 0 2006.285.13:14:29.37#ibcon#read 5, iclass 5, count 0 2006.285.13:14:29.37#ibcon#about to read 6, iclass 5, count 0 2006.285.13:14:29.37#ibcon#read 6, iclass 5, count 0 2006.285.13:14:29.37#ibcon#end of sib2, iclass 5, count 0 2006.285.13:14:29.37#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:14:29.37#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:14:29.37#ibcon#[25=USB\r\n] 2006.285.13:14:29.37#ibcon#*before write, iclass 5, count 0 2006.285.13:14:29.37#ibcon#enter sib2, iclass 5, count 0 2006.285.13:14:29.37#ibcon#flushed, iclass 5, count 0 2006.285.13:14:29.37#ibcon#about to write, iclass 5, count 0 2006.285.13:14:29.37#ibcon#wrote, iclass 5, count 0 2006.285.13:14:29.37#ibcon#about to read 3, iclass 5, count 0 2006.285.13:14:29.40#ibcon#read 3, iclass 5, count 0 2006.285.13:14:29.40#ibcon#about to read 4, iclass 5, count 0 2006.285.13:14:29.40#ibcon#read 4, iclass 5, count 0 2006.285.13:14:29.40#ibcon#about to read 5, iclass 5, count 0 2006.285.13:14:29.40#ibcon#read 5, iclass 5, count 0 2006.285.13:14:29.40#ibcon#about to read 6, iclass 5, count 0 2006.285.13:14:29.40#ibcon#read 6, iclass 5, count 0 2006.285.13:14:29.40#ibcon#end of sib2, iclass 5, count 0 2006.285.13:14:29.40#ibcon#*after write, iclass 5, count 0 2006.285.13:14:29.40#ibcon#*before return 0, iclass 5, count 0 2006.285.13:14:29.40#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:14:29.40#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:14:29.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:14:29.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:14:29.40$vck44/valo=8,884.99 2006.285.13:14:29.40#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.13:14:29.40#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.13:14:29.40#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:29.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:14:29.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:14:29.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:14:29.40#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:14:29.40#ibcon#first serial, iclass 7, count 0 2006.285.13:14:29.40#ibcon#enter sib2, iclass 7, count 0 2006.285.13:14:29.40#ibcon#flushed, iclass 7, count 0 2006.285.13:14:29.40#ibcon#about to write, iclass 7, count 0 2006.285.13:14:29.40#ibcon#wrote, iclass 7, count 0 2006.285.13:14:29.40#ibcon#about to read 3, iclass 7, count 0 2006.285.13:14:29.42#ibcon#read 3, iclass 7, count 0 2006.285.13:14:29.42#ibcon#about to read 4, iclass 7, count 0 2006.285.13:14:29.42#ibcon#read 4, iclass 7, count 0 2006.285.13:14:29.42#ibcon#about to read 5, iclass 7, count 0 2006.285.13:14:29.42#ibcon#read 5, iclass 7, count 0 2006.285.13:14:29.42#ibcon#about to read 6, iclass 7, count 0 2006.285.13:14:29.42#ibcon#read 6, iclass 7, count 0 2006.285.13:14:29.42#ibcon#end of sib2, iclass 7, count 0 2006.285.13:14:29.42#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:14:29.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:14:29.42#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:14:29.42#ibcon#*before write, iclass 7, count 0 2006.285.13:14:29.42#ibcon#enter sib2, iclass 7, count 0 2006.285.13:14:29.42#ibcon#flushed, iclass 7, count 0 2006.285.13:14:29.42#ibcon#about to write, iclass 7, count 0 2006.285.13:14:29.42#ibcon#wrote, iclass 7, count 0 2006.285.13:14:29.42#ibcon#about to read 3, iclass 7, count 0 2006.285.13:14:29.46#ibcon#read 3, iclass 7, count 0 2006.285.13:14:29.46#ibcon#about to read 4, iclass 7, count 0 2006.285.13:14:29.46#ibcon#read 4, iclass 7, count 0 2006.285.13:14:29.46#ibcon#about to read 5, iclass 7, count 0 2006.285.13:14:29.46#ibcon#read 5, iclass 7, count 0 2006.285.13:14:29.46#ibcon#about to read 6, iclass 7, count 0 2006.285.13:14:29.46#ibcon#read 6, iclass 7, count 0 2006.285.13:14:29.46#ibcon#end of sib2, iclass 7, count 0 2006.285.13:14:29.46#ibcon#*after write, iclass 7, count 0 2006.285.13:14:29.46#ibcon#*before return 0, iclass 7, count 0 2006.285.13:14:29.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:14:29.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:14:29.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:14:29.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:14:29.46$vck44/va=8,3 2006.285.13:14:29.46#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.13:14:29.46#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.13:14:29.46#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:29.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:14:29.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:14:29.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:14:29.52#ibcon#enter wrdev, iclass 11, count 2 2006.285.13:14:29.52#ibcon#first serial, iclass 11, count 2 2006.285.13:14:29.52#ibcon#enter sib2, iclass 11, count 2 2006.285.13:14:29.52#ibcon#flushed, iclass 11, count 2 2006.285.13:14:29.52#ibcon#about to write, iclass 11, count 2 2006.285.13:14:29.52#ibcon#wrote, iclass 11, count 2 2006.285.13:14:29.52#ibcon#about to read 3, iclass 11, count 2 2006.285.13:14:29.54#ibcon#read 3, iclass 11, count 2 2006.285.13:14:29.54#ibcon#about to read 4, iclass 11, count 2 2006.285.13:14:29.54#ibcon#read 4, iclass 11, count 2 2006.285.13:14:29.54#ibcon#about to read 5, iclass 11, count 2 2006.285.13:14:29.54#ibcon#read 5, iclass 11, count 2 2006.285.13:14:29.54#ibcon#about to read 6, iclass 11, count 2 2006.285.13:14:29.54#ibcon#read 6, iclass 11, count 2 2006.285.13:14:29.54#ibcon#end of sib2, iclass 11, count 2 2006.285.13:14:29.54#ibcon#*mode == 0, iclass 11, count 2 2006.285.13:14:29.54#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.13:14:29.54#ibcon#[25=AT08-03\r\n] 2006.285.13:14:29.54#ibcon#*before write, iclass 11, count 2 2006.285.13:14:29.54#ibcon#enter sib2, iclass 11, count 2 2006.285.13:14:29.54#ibcon#flushed, iclass 11, count 2 2006.285.13:14:29.54#ibcon#about to write, iclass 11, count 2 2006.285.13:14:29.54#ibcon#wrote, iclass 11, count 2 2006.285.13:14:29.54#ibcon#about to read 3, iclass 11, count 2 2006.285.13:14:29.57#ibcon#read 3, iclass 11, count 2 2006.285.13:14:29.57#ibcon#about to read 4, iclass 11, count 2 2006.285.13:14:29.57#ibcon#read 4, iclass 11, count 2 2006.285.13:14:29.57#ibcon#about to read 5, iclass 11, count 2 2006.285.13:14:29.57#ibcon#read 5, iclass 11, count 2 2006.285.13:14:29.57#ibcon#about to read 6, iclass 11, count 2 2006.285.13:14:29.57#ibcon#read 6, iclass 11, count 2 2006.285.13:14:29.57#ibcon#end of sib2, iclass 11, count 2 2006.285.13:14:29.57#ibcon#*after write, iclass 11, count 2 2006.285.13:14:29.57#ibcon#*before return 0, iclass 11, count 2 2006.285.13:14:29.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:14:29.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:14:29.57#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.13:14:29.57#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:29.57#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:14:29.69#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:14:29.69#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:14:29.69#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:14:29.69#ibcon#first serial, iclass 11, count 0 2006.285.13:14:29.69#ibcon#enter sib2, iclass 11, count 0 2006.285.13:14:29.69#ibcon#flushed, iclass 11, count 0 2006.285.13:14:29.69#ibcon#about to write, iclass 11, count 0 2006.285.13:14:29.69#ibcon#wrote, iclass 11, count 0 2006.285.13:14:29.69#ibcon#about to read 3, iclass 11, count 0 2006.285.13:14:29.71#ibcon#read 3, iclass 11, count 0 2006.285.13:14:29.71#ibcon#about to read 4, iclass 11, count 0 2006.285.13:14:29.71#ibcon#read 4, iclass 11, count 0 2006.285.13:14:29.71#ibcon#about to read 5, iclass 11, count 0 2006.285.13:14:29.71#ibcon#read 5, iclass 11, count 0 2006.285.13:14:29.71#ibcon#about to read 6, iclass 11, count 0 2006.285.13:14:29.71#ibcon#read 6, iclass 11, count 0 2006.285.13:14:29.71#ibcon#end of sib2, iclass 11, count 0 2006.285.13:14:29.71#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:14:29.71#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:14:29.71#ibcon#[25=USB\r\n] 2006.285.13:14:29.71#ibcon#*before write, iclass 11, count 0 2006.285.13:14:29.71#ibcon#enter sib2, iclass 11, count 0 2006.285.13:14:29.71#ibcon#flushed, iclass 11, count 0 2006.285.13:14:29.71#ibcon#about to write, iclass 11, count 0 2006.285.13:14:29.71#ibcon#wrote, iclass 11, count 0 2006.285.13:14:29.71#ibcon#about to read 3, iclass 11, count 0 2006.285.13:14:29.74#ibcon#read 3, iclass 11, count 0 2006.285.13:14:29.74#ibcon#about to read 4, iclass 11, count 0 2006.285.13:14:29.74#ibcon#read 4, iclass 11, count 0 2006.285.13:14:29.74#ibcon#about to read 5, iclass 11, count 0 2006.285.13:14:29.74#ibcon#read 5, iclass 11, count 0 2006.285.13:14:29.74#ibcon#about to read 6, iclass 11, count 0 2006.285.13:14:29.74#ibcon#read 6, iclass 11, count 0 2006.285.13:14:29.74#ibcon#end of sib2, iclass 11, count 0 2006.285.13:14:29.74#ibcon#*after write, iclass 11, count 0 2006.285.13:14:29.74#ibcon#*before return 0, iclass 11, count 0 2006.285.13:14:29.74#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:14:29.74#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:14:29.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:14:29.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:14:29.74$vck44/vblo=1,629.99 2006.285.13:14:29.74#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.13:14:29.74#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.13:14:29.74#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:29.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:14:29.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:14:29.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:14:29.74#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:14:29.74#ibcon#first serial, iclass 13, count 0 2006.285.13:14:29.74#ibcon#enter sib2, iclass 13, count 0 2006.285.13:14:29.74#ibcon#flushed, iclass 13, count 0 2006.285.13:14:29.74#ibcon#about to write, iclass 13, count 0 2006.285.13:14:29.74#ibcon#wrote, iclass 13, count 0 2006.285.13:14:29.74#ibcon#about to read 3, iclass 13, count 0 2006.285.13:14:29.76#ibcon#read 3, iclass 13, count 0 2006.285.13:14:29.76#ibcon#about to read 4, iclass 13, count 0 2006.285.13:14:29.76#ibcon#read 4, iclass 13, count 0 2006.285.13:14:29.76#ibcon#about to read 5, iclass 13, count 0 2006.285.13:14:29.76#ibcon#read 5, iclass 13, count 0 2006.285.13:14:29.76#ibcon#about to read 6, iclass 13, count 0 2006.285.13:14:29.76#ibcon#read 6, iclass 13, count 0 2006.285.13:14:29.76#ibcon#end of sib2, iclass 13, count 0 2006.285.13:14:29.76#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:14:29.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:14:29.76#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:14:29.76#ibcon#*before write, iclass 13, count 0 2006.285.13:14:29.76#ibcon#enter sib2, iclass 13, count 0 2006.285.13:14:29.76#ibcon#flushed, iclass 13, count 0 2006.285.13:14:29.76#ibcon#about to write, iclass 13, count 0 2006.285.13:14:29.76#ibcon#wrote, iclass 13, count 0 2006.285.13:14:29.76#ibcon#about to read 3, iclass 13, count 0 2006.285.13:14:29.80#ibcon#read 3, iclass 13, count 0 2006.285.13:14:29.80#ibcon#about to read 4, iclass 13, count 0 2006.285.13:14:29.80#ibcon#read 4, iclass 13, count 0 2006.285.13:14:29.80#ibcon#about to read 5, iclass 13, count 0 2006.285.13:14:29.80#ibcon#read 5, iclass 13, count 0 2006.285.13:14:29.80#ibcon#about to read 6, iclass 13, count 0 2006.285.13:14:29.80#ibcon#read 6, iclass 13, count 0 2006.285.13:14:29.80#ibcon#end of sib2, iclass 13, count 0 2006.285.13:14:29.80#ibcon#*after write, iclass 13, count 0 2006.285.13:14:29.80#ibcon#*before return 0, iclass 13, count 0 2006.285.13:14:29.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:14:29.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:14:29.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:14:29.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:14:29.80$vck44/vb=1,4 2006.285.13:14:29.80#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.13:14:29.80#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.13:14:29.80#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:29.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:14:29.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:14:29.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:14:29.80#ibcon#enter wrdev, iclass 15, count 2 2006.285.13:14:29.80#ibcon#first serial, iclass 15, count 2 2006.285.13:14:29.80#ibcon#enter sib2, iclass 15, count 2 2006.285.13:14:29.80#ibcon#flushed, iclass 15, count 2 2006.285.13:14:29.80#ibcon#about to write, iclass 15, count 2 2006.285.13:14:29.80#ibcon#wrote, iclass 15, count 2 2006.285.13:14:29.80#ibcon#about to read 3, iclass 15, count 2 2006.285.13:14:29.82#ibcon#read 3, iclass 15, count 2 2006.285.13:14:29.82#ibcon#about to read 4, iclass 15, count 2 2006.285.13:14:29.82#ibcon#read 4, iclass 15, count 2 2006.285.13:14:29.82#ibcon#about to read 5, iclass 15, count 2 2006.285.13:14:29.82#ibcon#read 5, iclass 15, count 2 2006.285.13:14:29.82#ibcon#about to read 6, iclass 15, count 2 2006.285.13:14:29.82#ibcon#read 6, iclass 15, count 2 2006.285.13:14:29.82#ibcon#end of sib2, iclass 15, count 2 2006.285.13:14:29.82#ibcon#*mode == 0, iclass 15, count 2 2006.285.13:14:29.82#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.13:14:29.82#ibcon#[27=AT01-04\r\n] 2006.285.13:14:29.82#ibcon#*before write, iclass 15, count 2 2006.285.13:14:29.82#ibcon#enter sib2, iclass 15, count 2 2006.285.13:14:29.82#ibcon#flushed, iclass 15, count 2 2006.285.13:14:29.82#ibcon#about to write, iclass 15, count 2 2006.285.13:14:29.82#ibcon#wrote, iclass 15, count 2 2006.285.13:14:29.82#ibcon#about to read 3, iclass 15, count 2 2006.285.13:14:29.85#ibcon#read 3, iclass 15, count 2 2006.285.13:14:29.85#ibcon#about to read 4, iclass 15, count 2 2006.285.13:14:29.85#ibcon#read 4, iclass 15, count 2 2006.285.13:14:29.85#ibcon#about to read 5, iclass 15, count 2 2006.285.13:14:29.85#ibcon#read 5, iclass 15, count 2 2006.285.13:14:29.85#ibcon#about to read 6, iclass 15, count 2 2006.285.13:14:29.85#ibcon#read 6, iclass 15, count 2 2006.285.13:14:29.85#ibcon#end of sib2, iclass 15, count 2 2006.285.13:14:29.85#ibcon#*after write, iclass 15, count 2 2006.285.13:14:29.85#ibcon#*before return 0, iclass 15, count 2 2006.285.13:14:29.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:14:29.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:14:29.85#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.13:14:29.85#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:29.85#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:14:29.97#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:14:29.97#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:14:29.97#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:14:29.97#ibcon#first serial, iclass 15, count 0 2006.285.13:14:29.97#ibcon#enter sib2, iclass 15, count 0 2006.285.13:14:29.97#ibcon#flushed, iclass 15, count 0 2006.285.13:14:29.97#ibcon#about to write, iclass 15, count 0 2006.285.13:14:29.97#ibcon#wrote, iclass 15, count 0 2006.285.13:14:29.97#ibcon#about to read 3, iclass 15, count 0 2006.285.13:14:29.99#ibcon#read 3, iclass 15, count 0 2006.285.13:14:29.99#ibcon#about to read 4, iclass 15, count 0 2006.285.13:14:29.99#ibcon#read 4, iclass 15, count 0 2006.285.13:14:29.99#ibcon#about to read 5, iclass 15, count 0 2006.285.13:14:29.99#ibcon#read 5, iclass 15, count 0 2006.285.13:14:29.99#ibcon#about to read 6, iclass 15, count 0 2006.285.13:14:29.99#ibcon#read 6, iclass 15, count 0 2006.285.13:14:29.99#ibcon#end of sib2, iclass 15, count 0 2006.285.13:14:29.99#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:14:29.99#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:14:29.99#ibcon#[27=USB\r\n] 2006.285.13:14:29.99#ibcon#*before write, iclass 15, count 0 2006.285.13:14:29.99#ibcon#enter sib2, iclass 15, count 0 2006.285.13:14:29.99#ibcon#flushed, iclass 15, count 0 2006.285.13:14:29.99#ibcon#about to write, iclass 15, count 0 2006.285.13:14:29.99#ibcon#wrote, iclass 15, count 0 2006.285.13:14:29.99#ibcon#about to read 3, iclass 15, count 0 2006.285.13:14:30.02#ibcon#read 3, iclass 15, count 0 2006.285.13:14:30.02#ibcon#about to read 4, iclass 15, count 0 2006.285.13:14:30.02#ibcon#read 4, iclass 15, count 0 2006.285.13:14:30.02#ibcon#about to read 5, iclass 15, count 0 2006.285.13:14:30.02#ibcon#read 5, iclass 15, count 0 2006.285.13:14:30.02#ibcon#about to read 6, iclass 15, count 0 2006.285.13:14:30.02#ibcon#read 6, iclass 15, count 0 2006.285.13:14:30.02#ibcon#end of sib2, iclass 15, count 0 2006.285.13:14:30.02#ibcon#*after write, iclass 15, count 0 2006.285.13:14:30.02#ibcon#*before return 0, iclass 15, count 0 2006.285.13:14:30.02#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:14:30.02#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:14:30.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:14:30.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:14:30.02$vck44/vblo=2,634.99 2006.285.13:14:30.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.13:14:30.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.13:14:30.02#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:30.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:14:30.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:14:30.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:14:30.02#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:14:30.02#ibcon#first serial, iclass 17, count 0 2006.285.13:14:30.02#ibcon#enter sib2, iclass 17, count 0 2006.285.13:14:30.02#ibcon#flushed, iclass 17, count 0 2006.285.13:14:30.02#ibcon#about to write, iclass 17, count 0 2006.285.13:14:30.02#ibcon#wrote, iclass 17, count 0 2006.285.13:14:30.02#ibcon#about to read 3, iclass 17, count 0 2006.285.13:14:30.04#ibcon#read 3, iclass 17, count 0 2006.285.13:14:30.04#ibcon#about to read 4, iclass 17, count 0 2006.285.13:14:30.04#ibcon#read 4, iclass 17, count 0 2006.285.13:14:30.04#ibcon#about to read 5, iclass 17, count 0 2006.285.13:14:30.04#ibcon#read 5, iclass 17, count 0 2006.285.13:14:30.04#ibcon#about to read 6, iclass 17, count 0 2006.285.13:14:30.04#ibcon#read 6, iclass 17, count 0 2006.285.13:14:30.04#ibcon#end of sib2, iclass 17, count 0 2006.285.13:14:30.04#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:14:30.04#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:14:30.04#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:14:30.04#ibcon#*before write, iclass 17, count 0 2006.285.13:14:30.04#ibcon#enter sib2, iclass 17, count 0 2006.285.13:14:30.04#ibcon#flushed, iclass 17, count 0 2006.285.13:14:30.04#ibcon#about to write, iclass 17, count 0 2006.285.13:14:30.04#ibcon#wrote, iclass 17, count 0 2006.285.13:14:30.04#ibcon#about to read 3, iclass 17, count 0 2006.285.13:14:30.08#ibcon#read 3, iclass 17, count 0 2006.285.13:14:30.08#ibcon#about to read 4, iclass 17, count 0 2006.285.13:14:30.08#ibcon#read 4, iclass 17, count 0 2006.285.13:14:30.08#ibcon#about to read 5, iclass 17, count 0 2006.285.13:14:30.08#ibcon#read 5, iclass 17, count 0 2006.285.13:14:30.08#ibcon#about to read 6, iclass 17, count 0 2006.285.13:14:30.08#ibcon#read 6, iclass 17, count 0 2006.285.13:14:30.08#ibcon#end of sib2, iclass 17, count 0 2006.285.13:14:30.08#ibcon#*after write, iclass 17, count 0 2006.285.13:14:30.08#ibcon#*before return 0, iclass 17, count 0 2006.285.13:14:30.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:14:30.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:14:30.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:14:30.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:14:30.08$vck44/vb=2,5 2006.285.13:14:30.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.13:14:30.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.13:14:30.08#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:30.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:14:30.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:14:30.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:14:30.14#ibcon#enter wrdev, iclass 19, count 2 2006.285.13:14:30.14#ibcon#first serial, iclass 19, count 2 2006.285.13:14:30.14#ibcon#enter sib2, iclass 19, count 2 2006.285.13:14:30.14#ibcon#flushed, iclass 19, count 2 2006.285.13:14:30.14#ibcon#about to write, iclass 19, count 2 2006.285.13:14:30.14#ibcon#wrote, iclass 19, count 2 2006.285.13:14:30.14#ibcon#about to read 3, iclass 19, count 2 2006.285.13:14:30.16#ibcon#read 3, iclass 19, count 2 2006.285.13:14:30.16#ibcon#about to read 4, iclass 19, count 2 2006.285.13:14:30.16#ibcon#read 4, iclass 19, count 2 2006.285.13:14:30.16#ibcon#about to read 5, iclass 19, count 2 2006.285.13:14:30.16#ibcon#read 5, iclass 19, count 2 2006.285.13:14:30.16#ibcon#about to read 6, iclass 19, count 2 2006.285.13:14:30.16#ibcon#read 6, iclass 19, count 2 2006.285.13:14:30.16#ibcon#end of sib2, iclass 19, count 2 2006.285.13:14:30.16#ibcon#*mode == 0, iclass 19, count 2 2006.285.13:14:30.16#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.13:14:30.16#ibcon#[27=AT02-05\r\n] 2006.285.13:14:30.16#ibcon#*before write, iclass 19, count 2 2006.285.13:14:30.16#ibcon#enter sib2, iclass 19, count 2 2006.285.13:14:30.16#ibcon#flushed, iclass 19, count 2 2006.285.13:14:30.16#ibcon#about to write, iclass 19, count 2 2006.285.13:14:30.16#ibcon#wrote, iclass 19, count 2 2006.285.13:14:30.16#ibcon#about to read 3, iclass 19, count 2 2006.285.13:14:30.19#ibcon#read 3, iclass 19, count 2 2006.285.13:14:30.19#ibcon#about to read 4, iclass 19, count 2 2006.285.13:14:30.19#ibcon#read 4, iclass 19, count 2 2006.285.13:14:30.19#ibcon#about to read 5, iclass 19, count 2 2006.285.13:14:30.19#ibcon#read 5, iclass 19, count 2 2006.285.13:14:30.19#ibcon#about to read 6, iclass 19, count 2 2006.285.13:14:30.19#ibcon#read 6, iclass 19, count 2 2006.285.13:14:30.19#ibcon#end of sib2, iclass 19, count 2 2006.285.13:14:30.19#ibcon#*after write, iclass 19, count 2 2006.285.13:14:30.19#ibcon#*before return 0, iclass 19, count 2 2006.285.13:14:30.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:14:30.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:14:30.19#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.13:14:30.19#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:30.19#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:14:30.31#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:14:30.31#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:14:30.31#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:14:30.31#ibcon#first serial, iclass 19, count 0 2006.285.13:14:30.31#ibcon#enter sib2, iclass 19, count 0 2006.285.13:14:30.31#ibcon#flushed, iclass 19, count 0 2006.285.13:14:30.31#ibcon#about to write, iclass 19, count 0 2006.285.13:14:30.31#ibcon#wrote, iclass 19, count 0 2006.285.13:14:30.31#ibcon#about to read 3, iclass 19, count 0 2006.285.13:14:30.33#ibcon#read 3, iclass 19, count 0 2006.285.13:14:30.33#ibcon#about to read 4, iclass 19, count 0 2006.285.13:14:30.33#ibcon#read 4, iclass 19, count 0 2006.285.13:14:30.33#ibcon#about to read 5, iclass 19, count 0 2006.285.13:14:30.33#ibcon#read 5, iclass 19, count 0 2006.285.13:14:30.33#ibcon#about to read 6, iclass 19, count 0 2006.285.13:14:30.33#ibcon#read 6, iclass 19, count 0 2006.285.13:14:30.33#ibcon#end of sib2, iclass 19, count 0 2006.285.13:14:30.33#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:14:30.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:14:30.33#ibcon#[27=USB\r\n] 2006.285.13:14:30.33#ibcon#*before write, iclass 19, count 0 2006.285.13:14:30.33#ibcon#enter sib2, iclass 19, count 0 2006.285.13:14:30.33#ibcon#flushed, iclass 19, count 0 2006.285.13:14:30.33#ibcon#about to write, iclass 19, count 0 2006.285.13:14:30.33#ibcon#wrote, iclass 19, count 0 2006.285.13:14:30.33#ibcon#about to read 3, iclass 19, count 0 2006.285.13:14:30.36#ibcon#read 3, iclass 19, count 0 2006.285.13:14:30.36#ibcon#about to read 4, iclass 19, count 0 2006.285.13:14:30.36#ibcon#read 4, iclass 19, count 0 2006.285.13:14:30.36#ibcon#about to read 5, iclass 19, count 0 2006.285.13:14:30.36#ibcon#read 5, iclass 19, count 0 2006.285.13:14:30.36#ibcon#about to read 6, iclass 19, count 0 2006.285.13:14:30.36#ibcon#read 6, iclass 19, count 0 2006.285.13:14:30.36#ibcon#end of sib2, iclass 19, count 0 2006.285.13:14:30.36#ibcon#*after write, iclass 19, count 0 2006.285.13:14:30.36#ibcon#*before return 0, iclass 19, count 0 2006.285.13:14:30.36#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:14:30.36#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:14:30.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:14:30.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:14:30.36$vck44/vblo=3,649.99 2006.285.13:14:30.36#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.13:14:30.36#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.13:14:30.36#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:30.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:14:30.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:14:30.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:14:30.36#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:14:30.36#ibcon#first serial, iclass 21, count 0 2006.285.13:14:30.36#ibcon#enter sib2, iclass 21, count 0 2006.285.13:14:30.36#ibcon#flushed, iclass 21, count 0 2006.285.13:14:30.36#ibcon#about to write, iclass 21, count 0 2006.285.13:14:30.36#ibcon#wrote, iclass 21, count 0 2006.285.13:14:30.36#ibcon#about to read 3, iclass 21, count 0 2006.285.13:14:30.38#ibcon#read 3, iclass 21, count 0 2006.285.13:14:30.38#ibcon#about to read 4, iclass 21, count 0 2006.285.13:14:30.38#ibcon#read 4, iclass 21, count 0 2006.285.13:14:30.38#ibcon#about to read 5, iclass 21, count 0 2006.285.13:14:30.38#ibcon#read 5, iclass 21, count 0 2006.285.13:14:30.38#ibcon#about to read 6, iclass 21, count 0 2006.285.13:14:30.38#ibcon#read 6, iclass 21, count 0 2006.285.13:14:30.38#ibcon#end of sib2, iclass 21, count 0 2006.285.13:14:30.38#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:14:30.38#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:14:30.38#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:14:30.38#ibcon#*before write, iclass 21, count 0 2006.285.13:14:30.38#ibcon#enter sib2, iclass 21, count 0 2006.285.13:14:30.38#ibcon#flushed, iclass 21, count 0 2006.285.13:14:30.38#ibcon#about to write, iclass 21, count 0 2006.285.13:14:30.38#ibcon#wrote, iclass 21, count 0 2006.285.13:14:30.38#ibcon#about to read 3, iclass 21, count 0 2006.285.13:14:30.42#ibcon#read 3, iclass 21, count 0 2006.285.13:14:30.42#ibcon#about to read 4, iclass 21, count 0 2006.285.13:14:30.42#ibcon#read 4, iclass 21, count 0 2006.285.13:14:30.42#ibcon#about to read 5, iclass 21, count 0 2006.285.13:14:30.42#ibcon#read 5, iclass 21, count 0 2006.285.13:14:30.42#ibcon#about to read 6, iclass 21, count 0 2006.285.13:14:30.42#ibcon#read 6, iclass 21, count 0 2006.285.13:14:30.42#ibcon#end of sib2, iclass 21, count 0 2006.285.13:14:30.42#ibcon#*after write, iclass 21, count 0 2006.285.13:14:30.42#ibcon#*before return 0, iclass 21, count 0 2006.285.13:14:30.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:14:30.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:14:30.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:14:30.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:14:30.42$vck44/vb=3,4 2006.285.13:14:30.42#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.13:14:30.42#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.13:14:30.42#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:30.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:14:30.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:14:30.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:14:30.48#ibcon#enter wrdev, iclass 23, count 2 2006.285.13:14:30.48#ibcon#first serial, iclass 23, count 2 2006.285.13:14:30.48#ibcon#enter sib2, iclass 23, count 2 2006.285.13:14:30.48#ibcon#flushed, iclass 23, count 2 2006.285.13:14:30.48#ibcon#about to write, iclass 23, count 2 2006.285.13:14:30.48#ibcon#wrote, iclass 23, count 2 2006.285.13:14:30.48#ibcon#about to read 3, iclass 23, count 2 2006.285.13:14:30.50#ibcon#read 3, iclass 23, count 2 2006.285.13:14:30.50#ibcon#about to read 4, iclass 23, count 2 2006.285.13:14:30.50#ibcon#read 4, iclass 23, count 2 2006.285.13:14:30.50#ibcon#about to read 5, iclass 23, count 2 2006.285.13:14:30.50#ibcon#read 5, iclass 23, count 2 2006.285.13:14:30.50#ibcon#about to read 6, iclass 23, count 2 2006.285.13:14:30.50#ibcon#read 6, iclass 23, count 2 2006.285.13:14:30.50#ibcon#end of sib2, iclass 23, count 2 2006.285.13:14:30.50#ibcon#*mode == 0, iclass 23, count 2 2006.285.13:14:30.50#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.13:14:30.50#ibcon#[27=AT03-04\r\n] 2006.285.13:14:30.50#ibcon#*before write, iclass 23, count 2 2006.285.13:14:30.50#ibcon#enter sib2, iclass 23, count 2 2006.285.13:14:30.50#ibcon#flushed, iclass 23, count 2 2006.285.13:14:30.50#ibcon#about to write, iclass 23, count 2 2006.285.13:14:30.50#ibcon#wrote, iclass 23, count 2 2006.285.13:14:30.50#ibcon#about to read 3, iclass 23, count 2 2006.285.13:14:30.53#ibcon#read 3, iclass 23, count 2 2006.285.13:14:30.53#ibcon#about to read 4, iclass 23, count 2 2006.285.13:14:30.53#ibcon#read 4, iclass 23, count 2 2006.285.13:14:30.53#ibcon#about to read 5, iclass 23, count 2 2006.285.13:14:30.53#ibcon#read 5, iclass 23, count 2 2006.285.13:14:30.53#ibcon#about to read 6, iclass 23, count 2 2006.285.13:14:30.53#ibcon#read 6, iclass 23, count 2 2006.285.13:14:30.53#ibcon#end of sib2, iclass 23, count 2 2006.285.13:14:30.53#ibcon#*after write, iclass 23, count 2 2006.285.13:14:30.53#ibcon#*before return 0, iclass 23, count 2 2006.285.13:14:30.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:14:30.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:14:30.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.13:14:30.53#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:30.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:14:30.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:14:30.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:14:30.65#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:14:30.65#ibcon#first serial, iclass 23, count 0 2006.285.13:14:30.65#ibcon#enter sib2, iclass 23, count 0 2006.285.13:14:30.65#ibcon#flushed, iclass 23, count 0 2006.285.13:14:30.65#ibcon#about to write, iclass 23, count 0 2006.285.13:14:30.65#ibcon#wrote, iclass 23, count 0 2006.285.13:14:30.65#ibcon#about to read 3, iclass 23, count 0 2006.285.13:14:30.67#ibcon#read 3, iclass 23, count 0 2006.285.13:14:30.67#ibcon#about to read 4, iclass 23, count 0 2006.285.13:14:30.67#ibcon#read 4, iclass 23, count 0 2006.285.13:14:30.67#ibcon#about to read 5, iclass 23, count 0 2006.285.13:14:30.67#ibcon#read 5, iclass 23, count 0 2006.285.13:14:30.67#ibcon#about to read 6, iclass 23, count 0 2006.285.13:14:30.67#ibcon#read 6, iclass 23, count 0 2006.285.13:14:30.67#ibcon#end of sib2, iclass 23, count 0 2006.285.13:14:30.67#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:14:30.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:14:30.67#ibcon#[27=USB\r\n] 2006.285.13:14:30.67#ibcon#*before write, iclass 23, count 0 2006.285.13:14:30.67#ibcon#enter sib2, iclass 23, count 0 2006.285.13:14:30.67#ibcon#flushed, iclass 23, count 0 2006.285.13:14:30.67#ibcon#about to write, iclass 23, count 0 2006.285.13:14:30.67#ibcon#wrote, iclass 23, count 0 2006.285.13:14:30.67#ibcon#about to read 3, iclass 23, count 0 2006.285.13:14:30.70#ibcon#read 3, iclass 23, count 0 2006.285.13:14:30.70#ibcon#about to read 4, iclass 23, count 0 2006.285.13:14:30.70#ibcon#read 4, iclass 23, count 0 2006.285.13:14:30.70#ibcon#about to read 5, iclass 23, count 0 2006.285.13:14:30.70#ibcon#read 5, iclass 23, count 0 2006.285.13:14:30.70#ibcon#about to read 6, iclass 23, count 0 2006.285.13:14:30.70#ibcon#read 6, iclass 23, count 0 2006.285.13:14:30.70#ibcon#end of sib2, iclass 23, count 0 2006.285.13:14:30.70#ibcon#*after write, iclass 23, count 0 2006.285.13:14:30.70#ibcon#*before return 0, iclass 23, count 0 2006.285.13:14:30.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:14:30.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:14:30.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:14:30.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:14:30.70$vck44/vblo=4,679.99 2006.285.13:14:30.70#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.13:14:30.70#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.13:14:30.70#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:30.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:14:30.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:14:30.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:14:30.70#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:14:30.70#ibcon#first serial, iclass 25, count 0 2006.285.13:14:30.70#ibcon#enter sib2, iclass 25, count 0 2006.285.13:14:30.70#ibcon#flushed, iclass 25, count 0 2006.285.13:14:30.70#ibcon#about to write, iclass 25, count 0 2006.285.13:14:30.70#ibcon#wrote, iclass 25, count 0 2006.285.13:14:30.70#ibcon#about to read 3, iclass 25, count 0 2006.285.13:14:30.72#ibcon#read 3, iclass 25, count 0 2006.285.13:14:30.72#ibcon#about to read 4, iclass 25, count 0 2006.285.13:14:30.72#ibcon#read 4, iclass 25, count 0 2006.285.13:14:30.72#ibcon#about to read 5, iclass 25, count 0 2006.285.13:14:30.72#ibcon#read 5, iclass 25, count 0 2006.285.13:14:30.72#ibcon#about to read 6, iclass 25, count 0 2006.285.13:14:30.72#ibcon#read 6, iclass 25, count 0 2006.285.13:14:30.72#ibcon#end of sib2, iclass 25, count 0 2006.285.13:14:30.72#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:14:30.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:14:30.72#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:14:30.72#ibcon#*before write, iclass 25, count 0 2006.285.13:14:30.72#ibcon#enter sib2, iclass 25, count 0 2006.285.13:14:30.72#ibcon#flushed, iclass 25, count 0 2006.285.13:14:30.72#ibcon#about to write, iclass 25, count 0 2006.285.13:14:30.72#ibcon#wrote, iclass 25, count 0 2006.285.13:14:30.72#ibcon#about to read 3, iclass 25, count 0 2006.285.13:14:30.76#ibcon#read 3, iclass 25, count 0 2006.285.13:14:30.76#ibcon#about to read 4, iclass 25, count 0 2006.285.13:14:30.76#ibcon#read 4, iclass 25, count 0 2006.285.13:14:30.76#ibcon#about to read 5, iclass 25, count 0 2006.285.13:14:30.76#ibcon#read 5, iclass 25, count 0 2006.285.13:14:30.76#ibcon#about to read 6, iclass 25, count 0 2006.285.13:14:30.76#ibcon#read 6, iclass 25, count 0 2006.285.13:14:30.76#ibcon#end of sib2, iclass 25, count 0 2006.285.13:14:30.76#ibcon#*after write, iclass 25, count 0 2006.285.13:14:30.76#ibcon#*before return 0, iclass 25, count 0 2006.285.13:14:30.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:14:30.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:14:30.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:14:30.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:14:30.76$vck44/vb=4,5 2006.285.13:14:30.87#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.13:14:30.87#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.13:14:30.87#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:30.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:14:30.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:14:30.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:14:30.87#ibcon#enter wrdev, iclass 27, count 2 2006.285.13:14:30.87#ibcon#first serial, iclass 27, count 2 2006.285.13:14:30.87#ibcon#enter sib2, iclass 27, count 2 2006.285.13:14:30.87#ibcon#flushed, iclass 27, count 2 2006.285.13:14:30.87#ibcon#about to write, iclass 27, count 2 2006.285.13:14:30.87#ibcon#wrote, iclass 27, count 2 2006.285.13:14:30.87#ibcon#about to read 3, iclass 27, count 2 2006.285.13:14:30.89#ibcon#read 3, iclass 27, count 2 2006.285.13:14:30.89#ibcon#about to read 4, iclass 27, count 2 2006.285.13:14:30.89#ibcon#read 4, iclass 27, count 2 2006.285.13:14:30.89#ibcon#about to read 5, iclass 27, count 2 2006.285.13:14:30.89#ibcon#read 5, iclass 27, count 2 2006.285.13:14:30.89#ibcon#about to read 6, iclass 27, count 2 2006.285.13:14:30.89#ibcon#read 6, iclass 27, count 2 2006.285.13:14:30.89#ibcon#end of sib2, iclass 27, count 2 2006.285.13:14:30.89#ibcon#*mode == 0, iclass 27, count 2 2006.285.13:14:30.89#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.13:14:30.89#ibcon#[27=AT04-05\r\n] 2006.285.13:14:30.89#ibcon#*before write, iclass 27, count 2 2006.285.13:14:30.89#ibcon#enter sib2, iclass 27, count 2 2006.285.13:14:30.89#ibcon#flushed, iclass 27, count 2 2006.285.13:14:30.89#ibcon#about to write, iclass 27, count 2 2006.285.13:14:30.89#ibcon#wrote, iclass 27, count 2 2006.285.13:14:30.89#ibcon#about to read 3, iclass 27, count 2 2006.285.13:14:30.92#ibcon#read 3, iclass 27, count 2 2006.285.13:14:30.92#ibcon#about to read 4, iclass 27, count 2 2006.285.13:14:30.92#ibcon#read 4, iclass 27, count 2 2006.285.13:14:30.92#ibcon#about to read 5, iclass 27, count 2 2006.285.13:14:30.92#ibcon#read 5, iclass 27, count 2 2006.285.13:14:30.92#ibcon#about to read 6, iclass 27, count 2 2006.285.13:14:30.92#ibcon#read 6, iclass 27, count 2 2006.285.13:14:30.92#ibcon#end of sib2, iclass 27, count 2 2006.285.13:14:30.92#ibcon#*after write, iclass 27, count 2 2006.285.13:14:30.92#ibcon#*before return 0, iclass 27, count 2 2006.285.13:14:30.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:14:30.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:14:30.92#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.13:14:30.92#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:30.92#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:14:31.04#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:14:31.04#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:14:31.04#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:14:31.04#ibcon#first serial, iclass 27, count 0 2006.285.13:14:31.04#ibcon#enter sib2, iclass 27, count 0 2006.285.13:14:31.04#ibcon#flushed, iclass 27, count 0 2006.285.13:14:31.04#ibcon#about to write, iclass 27, count 0 2006.285.13:14:31.04#ibcon#wrote, iclass 27, count 0 2006.285.13:14:31.04#ibcon#about to read 3, iclass 27, count 0 2006.285.13:14:31.06#ibcon#read 3, iclass 27, count 0 2006.285.13:14:31.06#ibcon#about to read 4, iclass 27, count 0 2006.285.13:14:31.06#ibcon#read 4, iclass 27, count 0 2006.285.13:14:31.06#ibcon#about to read 5, iclass 27, count 0 2006.285.13:14:31.06#ibcon#read 5, iclass 27, count 0 2006.285.13:14:31.06#ibcon#about to read 6, iclass 27, count 0 2006.285.13:14:31.06#ibcon#read 6, iclass 27, count 0 2006.285.13:14:31.06#ibcon#end of sib2, iclass 27, count 0 2006.285.13:14:31.06#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:14:31.06#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:14:31.06#ibcon#[27=USB\r\n] 2006.285.13:14:31.06#ibcon#*before write, iclass 27, count 0 2006.285.13:14:31.06#ibcon#enter sib2, iclass 27, count 0 2006.285.13:14:31.06#ibcon#flushed, iclass 27, count 0 2006.285.13:14:31.06#ibcon#about to write, iclass 27, count 0 2006.285.13:14:31.06#ibcon#wrote, iclass 27, count 0 2006.285.13:14:31.06#ibcon#about to read 3, iclass 27, count 0 2006.285.13:14:31.09#ibcon#read 3, iclass 27, count 0 2006.285.13:14:31.09#ibcon#about to read 4, iclass 27, count 0 2006.285.13:14:31.09#ibcon#read 4, iclass 27, count 0 2006.285.13:14:31.09#ibcon#about to read 5, iclass 27, count 0 2006.285.13:14:31.09#ibcon#read 5, iclass 27, count 0 2006.285.13:14:31.09#ibcon#about to read 6, iclass 27, count 0 2006.285.13:14:31.09#ibcon#read 6, iclass 27, count 0 2006.285.13:14:31.09#ibcon#end of sib2, iclass 27, count 0 2006.285.13:14:31.09#ibcon#*after write, iclass 27, count 0 2006.285.13:14:31.09#ibcon#*before return 0, iclass 27, count 0 2006.285.13:14:31.09#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:14:31.09#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:14:31.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:14:31.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:14:31.09$vck44/vblo=5,709.99 2006.285.13:14:31.09#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.13:14:31.09#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.13:14:31.09#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:31.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:14:31.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:14:31.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:14:31.09#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:14:31.09#ibcon#first serial, iclass 29, count 0 2006.285.13:14:31.09#ibcon#enter sib2, iclass 29, count 0 2006.285.13:14:31.09#ibcon#flushed, iclass 29, count 0 2006.285.13:14:31.09#ibcon#about to write, iclass 29, count 0 2006.285.13:14:31.09#ibcon#wrote, iclass 29, count 0 2006.285.13:14:31.09#ibcon#about to read 3, iclass 29, count 0 2006.285.13:14:31.11#ibcon#read 3, iclass 29, count 0 2006.285.13:14:31.11#ibcon#about to read 4, iclass 29, count 0 2006.285.13:14:31.11#ibcon#read 4, iclass 29, count 0 2006.285.13:14:31.11#ibcon#about to read 5, iclass 29, count 0 2006.285.13:14:31.11#ibcon#read 5, iclass 29, count 0 2006.285.13:14:31.11#ibcon#about to read 6, iclass 29, count 0 2006.285.13:14:31.11#ibcon#read 6, iclass 29, count 0 2006.285.13:14:31.11#ibcon#end of sib2, iclass 29, count 0 2006.285.13:14:31.11#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:14:31.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:14:31.11#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:14:31.11#ibcon#*before write, iclass 29, count 0 2006.285.13:14:31.11#ibcon#enter sib2, iclass 29, count 0 2006.285.13:14:31.11#ibcon#flushed, iclass 29, count 0 2006.285.13:14:31.11#ibcon#about to write, iclass 29, count 0 2006.285.13:14:31.11#ibcon#wrote, iclass 29, count 0 2006.285.13:14:31.11#ibcon#about to read 3, iclass 29, count 0 2006.285.13:14:31.15#ibcon#read 3, iclass 29, count 0 2006.285.13:14:31.15#ibcon#about to read 4, iclass 29, count 0 2006.285.13:14:31.15#ibcon#read 4, iclass 29, count 0 2006.285.13:14:31.15#ibcon#about to read 5, iclass 29, count 0 2006.285.13:14:31.15#ibcon#read 5, iclass 29, count 0 2006.285.13:14:31.15#ibcon#about to read 6, iclass 29, count 0 2006.285.13:14:31.15#ibcon#read 6, iclass 29, count 0 2006.285.13:14:31.15#ibcon#end of sib2, iclass 29, count 0 2006.285.13:14:31.15#ibcon#*after write, iclass 29, count 0 2006.285.13:14:31.15#ibcon#*before return 0, iclass 29, count 0 2006.285.13:14:31.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:14:31.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:14:31.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:14:31.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:14:31.15$vck44/vb=5,4 2006.285.13:14:31.15#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.13:14:31.15#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.13:14:31.15#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:31.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:14:31.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:14:31.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:14:31.21#ibcon#enter wrdev, iclass 31, count 2 2006.285.13:14:31.21#ibcon#first serial, iclass 31, count 2 2006.285.13:14:31.21#ibcon#enter sib2, iclass 31, count 2 2006.285.13:14:31.21#ibcon#flushed, iclass 31, count 2 2006.285.13:14:31.21#ibcon#about to write, iclass 31, count 2 2006.285.13:14:31.21#ibcon#wrote, iclass 31, count 2 2006.285.13:14:31.21#ibcon#about to read 3, iclass 31, count 2 2006.285.13:14:31.23#ibcon#read 3, iclass 31, count 2 2006.285.13:14:31.23#ibcon#about to read 4, iclass 31, count 2 2006.285.13:14:31.23#ibcon#read 4, iclass 31, count 2 2006.285.13:14:31.23#ibcon#about to read 5, iclass 31, count 2 2006.285.13:14:31.23#ibcon#read 5, iclass 31, count 2 2006.285.13:14:31.23#ibcon#about to read 6, iclass 31, count 2 2006.285.13:14:31.23#ibcon#read 6, iclass 31, count 2 2006.285.13:14:31.23#ibcon#end of sib2, iclass 31, count 2 2006.285.13:14:31.23#ibcon#*mode == 0, iclass 31, count 2 2006.285.13:14:31.23#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.13:14:31.23#ibcon#[27=AT05-04\r\n] 2006.285.13:14:31.23#ibcon#*before write, iclass 31, count 2 2006.285.13:14:31.23#ibcon#enter sib2, iclass 31, count 2 2006.285.13:14:31.23#ibcon#flushed, iclass 31, count 2 2006.285.13:14:31.23#ibcon#about to write, iclass 31, count 2 2006.285.13:14:31.23#ibcon#wrote, iclass 31, count 2 2006.285.13:14:31.23#ibcon#about to read 3, iclass 31, count 2 2006.285.13:14:31.26#ibcon#read 3, iclass 31, count 2 2006.285.13:14:31.26#ibcon#about to read 4, iclass 31, count 2 2006.285.13:14:31.26#ibcon#read 4, iclass 31, count 2 2006.285.13:14:31.26#ibcon#about to read 5, iclass 31, count 2 2006.285.13:14:31.26#ibcon#read 5, iclass 31, count 2 2006.285.13:14:31.26#ibcon#about to read 6, iclass 31, count 2 2006.285.13:14:31.26#ibcon#read 6, iclass 31, count 2 2006.285.13:14:31.26#ibcon#end of sib2, iclass 31, count 2 2006.285.13:14:31.26#ibcon#*after write, iclass 31, count 2 2006.285.13:14:31.26#ibcon#*before return 0, iclass 31, count 2 2006.285.13:14:31.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:14:31.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:14:31.26#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.13:14:31.26#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:31.26#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:14:31.38#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:14:31.38#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:14:31.38#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:14:31.38#ibcon#first serial, iclass 31, count 0 2006.285.13:14:31.38#ibcon#enter sib2, iclass 31, count 0 2006.285.13:14:31.38#ibcon#flushed, iclass 31, count 0 2006.285.13:14:31.38#ibcon#about to write, iclass 31, count 0 2006.285.13:14:31.38#ibcon#wrote, iclass 31, count 0 2006.285.13:14:31.38#ibcon#about to read 3, iclass 31, count 0 2006.285.13:14:31.40#ibcon#read 3, iclass 31, count 0 2006.285.13:14:31.40#ibcon#about to read 4, iclass 31, count 0 2006.285.13:14:31.40#ibcon#read 4, iclass 31, count 0 2006.285.13:14:31.40#ibcon#about to read 5, iclass 31, count 0 2006.285.13:14:31.40#ibcon#read 5, iclass 31, count 0 2006.285.13:14:31.40#ibcon#about to read 6, iclass 31, count 0 2006.285.13:14:31.40#ibcon#read 6, iclass 31, count 0 2006.285.13:14:31.40#ibcon#end of sib2, iclass 31, count 0 2006.285.13:14:31.40#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:14:31.40#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:14:31.40#ibcon#[27=USB\r\n] 2006.285.13:14:31.40#ibcon#*before write, iclass 31, count 0 2006.285.13:14:31.40#ibcon#enter sib2, iclass 31, count 0 2006.285.13:14:31.40#ibcon#flushed, iclass 31, count 0 2006.285.13:14:31.40#ibcon#about to write, iclass 31, count 0 2006.285.13:14:31.40#ibcon#wrote, iclass 31, count 0 2006.285.13:14:31.40#ibcon#about to read 3, iclass 31, count 0 2006.285.13:14:31.43#ibcon#read 3, iclass 31, count 0 2006.285.13:14:31.43#ibcon#about to read 4, iclass 31, count 0 2006.285.13:14:31.43#ibcon#read 4, iclass 31, count 0 2006.285.13:14:31.43#ibcon#about to read 5, iclass 31, count 0 2006.285.13:14:31.43#ibcon#read 5, iclass 31, count 0 2006.285.13:14:31.43#ibcon#about to read 6, iclass 31, count 0 2006.285.13:14:31.43#ibcon#read 6, iclass 31, count 0 2006.285.13:14:31.43#ibcon#end of sib2, iclass 31, count 0 2006.285.13:14:31.43#ibcon#*after write, iclass 31, count 0 2006.285.13:14:31.43#ibcon#*before return 0, iclass 31, count 0 2006.285.13:14:31.43#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:14:31.43#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:14:31.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:14:31.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:14:31.43$vck44/vblo=6,719.99 2006.285.13:14:31.43#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.13:14:31.43#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.13:14:31.43#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:31.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:14:31.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:14:31.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:14:31.43#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:14:31.43#ibcon#first serial, iclass 33, count 0 2006.285.13:14:31.43#ibcon#enter sib2, iclass 33, count 0 2006.285.13:14:31.43#ibcon#flushed, iclass 33, count 0 2006.285.13:14:31.43#ibcon#about to write, iclass 33, count 0 2006.285.13:14:31.43#ibcon#wrote, iclass 33, count 0 2006.285.13:14:31.43#ibcon#about to read 3, iclass 33, count 0 2006.285.13:14:31.45#ibcon#read 3, iclass 33, count 0 2006.285.13:14:31.45#ibcon#about to read 4, iclass 33, count 0 2006.285.13:14:31.45#ibcon#read 4, iclass 33, count 0 2006.285.13:14:31.45#ibcon#about to read 5, iclass 33, count 0 2006.285.13:14:31.45#ibcon#read 5, iclass 33, count 0 2006.285.13:14:31.45#ibcon#about to read 6, iclass 33, count 0 2006.285.13:14:31.45#ibcon#read 6, iclass 33, count 0 2006.285.13:14:31.45#ibcon#end of sib2, iclass 33, count 0 2006.285.13:14:31.45#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:14:31.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:14:31.45#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:14:31.45#ibcon#*before write, iclass 33, count 0 2006.285.13:14:31.45#ibcon#enter sib2, iclass 33, count 0 2006.285.13:14:31.45#ibcon#flushed, iclass 33, count 0 2006.285.13:14:31.45#ibcon#about to write, iclass 33, count 0 2006.285.13:14:31.45#ibcon#wrote, iclass 33, count 0 2006.285.13:14:31.45#ibcon#about to read 3, iclass 33, count 0 2006.285.13:14:31.49#ibcon#read 3, iclass 33, count 0 2006.285.13:14:31.49#ibcon#about to read 4, iclass 33, count 0 2006.285.13:14:31.49#ibcon#read 4, iclass 33, count 0 2006.285.13:14:31.49#ibcon#about to read 5, iclass 33, count 0 2006.285.13:14:31.49#ibcon#read 5, iclass 33, count 0 2006.285.13:14:31.49#ibcon#about to read 6, iclass 33, count 0 2006.285.13:14:31.49#ibcon#read 6, iclass 33, count 0 2006.285.13:14:31.49#ibcon#end of sib2, iclass 33, count 0 2006.285.13:14:31.49#ibcon#*after write, iclass 33, count 0 2006.285.13:14:31.49#ibcon#*before return 0, iclass 33, count 0 2006.285.13:14:31.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:14:31.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:14:31.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:14:31.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:14:31.49$vck44/vb=6,3 2006.285.13:14:31.49#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.13:14:31.49#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.13:14:31.49#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:31.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:14:31.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:14:31.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:14:31.55#ibcon#enter wrdev, iclass 35, count 2 2006.285.13:14:31.55#ibcon#first serial, iclass 35, count 2 2006.285.13:14:31.55#ibcon#enter sib2, iclass 35, count 2 2006.285.13:14:31.55#ibcon#flushed, iclass 35, count 2 2006.285.13:14:31.55#ibcon#about to write, iclass 35, count 2 2006.285.13:14:31.55#ibcon#wrote, iclass 35, count 2 2006.285.13:14:31.55#ibcon#about to read 3, iclass 35, count 2 2006.285.13:14:31.57#ibcon#read 3, iclass 35, count 2 2006.285.13:14:31.57#ibcon#about to read 4, iclass 35, count 2 2006.285.13:14:31.57#ibcon#read 4, iclass 35, count 2 2006.285.13:14:31.57#ibcon#about to read 5, iclass 35, count 2 2006.285.13:14:31.57#ibcon#read 5, iclass 35, count 2 2006.285.13:14:31.57#ibcon#about to read 6, iclass 35, count 2 2006.285.13:14:31.57#ibcon#read 6, iclass 35, count 2 2006.285.13:14:31.57#ibcon#end of sib2, iclass 35, count 2 2006.285.13:14:31.57#ibcon#*mode == 0, iclass 35, count 2 2006.285.13:14:31.57#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.13:14:31.57#ibcon#[27=AT06-03\r\n] 2006.285.13:14:31.57#ibcon#*before write, iclass 35, count 2 2006.285.13:14:31.57#ibcon#enter sib2, iclass 35, count 2 2006.285.13:14:31.57#ibcon#flushed, iclass 35, count 2 2006.285.13:14:31.57#ibcon#about to write, iclass 35, count 2 2006.285.13:14:31.57#ibcon#wrote, iclass 35, count 2 2006.285.13:14:31.57#ibcon#about to read 3, iclass 35, count 2 2006.285.13:14:31.60#ibcon#read 3, iclass 35, count 2 2006.285.13:14:31.60#ibcon#about to read 4, iclass 35, count 2 2006.285.13:14:31.60#ibcon#read 4, iclass 35, count 2 2006.285.13:14:31.60#ibcon#about to read 5, iclass 35, count 2 2006.285.13:14:31.60#ibcon#read 5, iclass 35, count 2 2006.285.13:14:31.60#ibcon#about to read 6, iclass 35, count 2 2006.285.13:14:31.60#ibcon#read 6, iclass 35, count 2 2006.285.13:14:31.60#ibcon#end of sib2, iclass 35, count 2 2006.285.13:14:31.60#ibcon#*after write, iclass 35, count 2 2006.285.13:14:31.60#ibcon#*before return 0, iclass 35, count 2 2006.285.13:14:31.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:14:31.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:14:31.60#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.13:14:31.60#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:31.60#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:14:31.72#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:14:31.72#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:14:31.72#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:14:31.72#ibcon#first serial, iclass 35, count 0 2006.285.13:14:31.72#ibcon#enter sib2, iclass 35, count 0 2006.285.13:14:31.72#ibcon#flushed, iclass 35, count 0 2006.285.13:14:31.72#ibcon#about to write, iclass 35, count 0 2006.285.13:14:31.72#ibcon#wrote, iclass 35, count 0 2006.285.13:14:31.72#ibcon#about to read 3, iclass 35, count 0 2006.285.13:14:31.74#ibcon#read 3, iclass 35, count 0 2006.285.13:14:31.74#ibcon#about to read 4, iclass 35, count 0 2006.285.13:14:31.74#ibcon#read 4, iclass 35, count 0 2006.285.13:14:31.74#ibcon#about to read 5, iclass 35, count 0 2006.285.13:14:31.74#ibcon#read 5, iclass 35, count 0 2006.285.13:14:31.74#ibcon#about to read 6, iclass 35, count 0 2006.285.13:14:31.74#ibcon#read 6, iclass 35, count 0 2006.285.13:14:31.74#ibcon#end of sib2, iclass 35, count 0 2006.285.13:14:31.74#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:14:31.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:14:31.74#ibcon#[27=USB\r\n] 2006.285.13:14:31.74#ibcon#*before write, iclass 35, count 0 2006.285.13:14:31.74#ibcon#enter sib2, iclass 35, count 0 2006.285.13:14:31.74#ibcon#flushed, iclass 35, count 0 2006.285.13:14:31.74#ibcon#about to write, iclass 35, count 0 2006.285.13:14:31.74#ibcon#wrote, iclass 35, count 0 2006.285.13:14:31.74#ibcon#about to read 3, iclass 35, count 0 2006.285.13:14:31.77#ibcon#read 3, iclass 35, count 0 2006.285.13:14:31.77#ibcon#about to read 4, iclass 35, count 0 2006.285.13:14:31.77#ibcon#read 4, iclass 35, count 0 2006.285.13:14:31.77#ibcon#about to read 5, iclass 35, count 0 2006.285.13:14:31.77#ibcon#read 5, iclass 35, count 0 2006.285.13:14:31.77#ibcon#about to read 6, iclass 35, count 0 2006.285.13:14:31.77#ibcon#read 6, iclass 35, count 0 2006.285.13:14:31.77#ibcon#end of sib2, iclass 35, count 0 2006.285.13:14:31.77#ibcon#*after write, iclass 35, count 0 2006.285.13:14:31.77#ibcon#*before return 0, iclass 35, count 0 2006.285.13:14:31.77#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:14:31.77#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:14:31.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:14:31.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:14:31.77$vck44/vblo=7,734.99 2006.285.13:14:31.77#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.13:14:31.77#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.13:14:31.77#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:31.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:14:31.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:14:31.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:14:31.77#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:14:31.77#ibcon#first serial, iclass 37, count 0 2006.285.13:14:31.77#ibcon#enter sib2, iclass 37, count 0 2006.285.13:14:31.77#ibcon#flushed, iclass 37, count 0 2006.285.13:14:31.77#ibcon#about to write, iclass 37, count 0 2006.285.13:14:31.77#ibcon#wrote, iclass 37, count 0 2006.285.13:14:31.77#ibcon#about to read 3, iclass 37, count 0 2006.285.13:14:31.79#ibcon#read 3, iclass 37, count 0 2006.285.13:14:31.94#ibcon#about to read 4, iclass 37, count 0 2006.285.13:14:31.94#ibcon#read 4, iclass 37, count 0 2006.285.13:14:31.94#ibcon#about to read 5, iclass 37, count 0 2006.285.13:14:31.94#ibcon#read 5, iclass 37, count 0 2006.285.13:14:31.94#ibcon#about to read 6, iclass 37, count 0 2006.285.13:14:31.94#ibcon#read 6, iclass 37, count 0 2006.285.13:14:31.94#ibcon#end of sib2, iclass 37, count 0 2006.285.13:14:31.94#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:14:31.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:14:31.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:14:31.94#ibcon#*before write, iclass 37, count 0 2006.285.13:14:31.94#ibcon#enter sib2, iclass 37, count 0 2006.285.13:14:31.94#ibcon#flushed, iclass 37, count 0 2006.285.13:14:31.94#ibcon#about to write, iclass 37, count 0 2006.285.13:14:31.94#ibcon#wrote, iclass 37, count 0 2006.285.13:14:31.94#ibcon#about to read 3, iclass 37, count 0 2006.285.13:14:31.98#ibcon#read 3, iclass 37, count 0 2006.285.13:14:31.98#ibcon#about to read 4, iclass 37, count 0 2006.285.13:14:31.98#ibcon#read 4, iclass 37, count 0 2006.285.13:14:31.98#ibcon#about to read 5, iclass 37, count 0 2006.285.13:14:31.98#ibcon#read 5, iclass 37, count 0 2006.285.13:14:31.98#ibcon#about to read 6, iclass 37, count 0 2006.285.13:14:31.98#ibcon#read 6, iclass 37, count 0 2006.285.13:14:31.98#ibcon#end of sib2, iclass 37, count 0 2006.285.13:14:31.98#ibcon#*after write, iclass 37, count 0 2006.285.13:14:31.98#ibcon#*before return 0, iclass 37, count 0 2006.285.13:14:31.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:14:31.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:14:31.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:14:31.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:14:31.98$vck44/vb=7,4 2006.285.13:14:31.98#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.13:14:31.98#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.13:14:31.98#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:31.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:14:31.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:14:31.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:14:31.98#ibcon#enter wrdev, iclass 39, count 2 2006.285.13:14:31.98#ibcon#first serial, iclass 39, count 2 2006.285.13:14:31.98#ibcon#enter sib2, iclass 39, count 2 2006.285.13:14:31.98#ibcon#flushed, iclass 39, count 2 2006.285.13:14:31.98#ibcon#about to write, iclass 39, count 2 2006.285.13:14:31.98#ibcon#wrote, iclass 39, count 2 2006.285.13:14:31.98#ibcon#about to read 3, iclass 39, count 2 2006.285.13:14:32.00#ibcon#read 3, iclass 39, count 2 2006.285.13:14:32.00#ibcon#about to read 4, iclass 39, count 2 2006.285.13:14:32.00#ibcon#read 4, iclass 39, count 2 2006.285.13:14:32.00#ibcon#about to read 5, iclass 39, count 2 2006.285.13:14:32.00#ibcon#read 5, iclass 39, count 2 2006.285.13:14:32.00#ibcon#about to read 6, iclass 39, count 2 2006.285.13:14:32.00#ibcon#read 6, iclass 39, count 2 2006.285.13:14:32.00#ibcon#end of sib2, iclass 39, count 2 2006.285.13:14:32.00#ibcon#*mode == 0, iclass 39, count 2 2006.285.13:14:32.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.13:14:32.00#ibcon#[27=AT07-04\r\n] 2006.285.13:14:32.00#ibcon#*before write, iclass 39, count 2 2006.285.13:14:32.00#ibcon#enter sib2, iclass 39, count 2 2006.285.13:14:32.00#ibcon#flushed, iclass 39, count 2 2006.285.13:14:32.00#ibcon#about to write, iclass 39, count 2 2006.285.13:14:32.00#ibcon#wrote, iclass 39, count 2 2006.285.13:14:32.00#ibcon#about to read 3, iclass 39, count 2 2006.285.13:14:32.03#ibcon#read 3, iclass 39, count 2 2006.285.13:14:32.03#ibcon#about to read 4, iclass 39, count 2 2006.285.13:14:32.03#ibcon#read 4, iclass 39, count 2 2006.285.13:14:32.03#ibcon#about to read 5, iclass 39, count 2 2006.285.13:14:32.03#ibcon#read 5, iclass 39, count 2 2006.285.13:14:32.03#ibcon#about to read 6, iclass 39, count 2 2006.285.13:14:32.03#ibcon#read 6, iclass 39, count 2 2006.285.13:14:32.03#ibcon#end of sib2, iclass 39, count 2 2006.285.13:14:32.03#ibcon#*after write, iclass 39, count 2 2006.285.13:14:32.03#ibcon#*before return 0, iclass 39, count 2 2006.285.13:14:32.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:14:32.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:14:32.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.13:14:32.03#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:32.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:14:32.10#abcon#<5=/04 1.5 3.2 19.03 961015.3\r\n> 2006.285.13:14:32.12#abcon#{5=INTERFACE CLEAR} 2006.285.13:14:32.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:14:32.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:14:32.15#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:14:32.15#ibcon#first serial, iclass 39, count 0 2006.285.13:14:32.15#ibcon#enter sib2, iclass 39, count 0 2006.285.13:14:32.15#ibcon#flushed, iclass 39, count 0 2006.285.13:14:32.15#ibcon#about to write, iclass 39, count 0 2006.285.13:14:32.15#ibcon#wrote, iclass 39, count 0 2006.285.13:14:32.15#ibcon#about to read 3, iclass 39, count 0 2006.285.13:14:32.17#ibcon#read 3, iclass 39, count 0 2006.285.13:14:32.17#ibcon#about to read 4, iclass 39, count 0 2006.285.13:14:32.17#ibcon#read 4, iclass 39, count 0 2006.285.13:14:32.17#ibcon#about to read 5, iclass 39, count 0 2006.285.13:14:32.17#ibcon#read 5, iclass 39, count 0 2006.285.13:14:32.17#ibcon#about to read 6, iclass 39, count 0 2006.285.13:14:32.17#ibcon#read 6, iclass 39, count 0 2006.285.13:14:32.17#ibcon#end of sib2, iclass 39, count 0 2006.285.13:14:32.17#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:14:32.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:14:32.17#ibcon#[27=USB\r\n] 2006.285.13:14:32.17#ibcon#*before write, iclass 39, count 0 2006.285.13:14:32.17#ibcon#enter sib2, iclass 39, count 0 2006.285.13:14:32.17#ibcon#flushed, iclass 39, count 0 2006.285.13:14:32.17#ibcon#about to write, iclass 39, count 0 2006.285.13:14:32.17#ibcon#wrote, iclass 39, count 0 2006.285.13:14:32.17#ibcon#about to read 3, iclass 39, count 0 2006.285.13:14:32.18#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:14:32.20#ibcon#read 3, iclass 39, count 0 2006.285.13:14:32.20#ibcon#about to read 4, iclass 39, count 0 2006.285.13:14:32.20#ibcon#read 4, iclass 39, count 0 2006.285.13:14:32.20#ibcon#about to read 5, iclass 39, count 0 2006.285.13:14:32.20#ibcon#read 5, iclass 39, count 0 2006.285.13:14:32.20#ibcon#about to read 6, iclass 39, count 0 2006.285.13:14:32.20#ibcon#read 6, iclass 39, count 0 2006.285.13:14:32.20#ibcon#end of sib2, iclass 39, count 0 2006.285.13:14:32.20#ibcon#*after write, iclass 39, count 0 2006.285.13:14:32.20#ibcon#*before return 0, iclass 39, count 0 2006.285.13:14:32.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:14:32.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:14:32.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:14:32.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:14:32.20$vck44/vblo=8,744.99 2006.285.13:14:32.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.13:14:32.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.13:14:32.20#ibcon#ireg 17 cls_cnt 0 2006.285.13:14:32.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:14:32.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:14:32.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:14:32.20#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:14:32.20#ibcon#first serial, iclass 7, count 0 2006.285.13:14:32.20#ibcon#enter sib2, iclass 7, count 0 2006.285.13:14:32.20#ibcon#flushed, iclass 7, count 0 2006.285.13:14:32.20#ibcon#about to write, iclass 7, count 0 2006.285.13:14:32.20#ibcon#wrote, iclass 7, count 0 2006.285.13:14:32.20#ibcon#about to read 3, iclass 7, count 0 2006.285.13:14:32.22#ibcon#read 3, iclass 7, count 0 2006.285.13:14:32.22#ibcon#about to read 4, iclass 7, count 0 2006.285.13:14:32.22#ibcon#read 4, iclass 7, count 0 2006.285.13:14:32.22#ibcon#about to read 5, iclass 7, count 0 2006.285.13:14:32.22#ibcon#read 5, iclass 7, count 0 2006.285.13:14:32.22#ibcon#about to read 6, iclass 7, count 0 2006.285.13:14:32.22#ibcon#read 6, iclass 7, count 0 2006.285.13:14:32.22#ibcon#end of sib2, iclass 7, count 0 2006.285.13:14:32.22#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:14:32.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:14:32.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:14:32.22#ibcon#*before write, iclass 7, count 0 2006.285.13:14:32.22#ibcon#enter sib2, iclass 7, count 0 2006.285.13:14:32.22#ibcon#flushed, iclass 7, count 0 2006.285.13:14:32.22#ibcon#about to write, iclass 7, count 0 2006.285.13:14:32.22#ibcon#wrote, iclass 7, count 0 2006.285.13:14:32.22#ibcon#about to read 3, iclass 7, count 0 2006.285.13:14:32.26#ibcon#read 3, iclass 7, count 0 2006.285.13:14:32.26#ibcon#about to read 4, iclass 7, count 0 2006.285.13:14:32.26#ibcon#read 4, iclass 7, count 0 2006.285.13:14:32.26#ibcon#about to read 5, iclass 7, count 0 2006.285.13:14:32.26#ibcon#read 5, iclass 7, count 0 2006.285.13:14:32.26#ibcon#about to read 6, iclass 7, count 0 2006.285.13:14:32.26#ibcon#read 6, iclass 7, count 0 2006.285.13:14:32.26#ibcon#end of sib2, iclass 7, count 0 2006.285.13:14:32.26#ibcon#*after write, iclass 7, count 0 2006.285.13:14:32.26#ibcon#*before return 0, iclass 7, count 0 2006.285.13:14:32.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:14:32.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:14:32.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:14:32.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:14:32.26$vck44/vb=8,4 2006.285.13:14:32.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.13:14:32.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.13:14:32.26#ibcon#ireg 11 cls_cnt 2 2006.285.13:14:32.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:14:32.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:14:32.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:14:32.32#ibcon#enter wrdev, iclass 11, count 2 2006.285.13:14:32.32#ibcon#first serial, iclass 11, count 2 2006.285.13:14:32.32#ibcon#enter sib2, iclass 11, count 2 2006.285.13:14:32.32#ibcon#flushed, iclass 11, count 2 2006.285.13:14:32.32#ibcon#about to write, iclass 11, count 2 2006.285.13:14:32.32#ibcon#wrote, iclass 11, count 2 2006.285.13:14:32.32#ibcon#about to read 3, iclass 11, count 2 2006.285.13:14:32.34#ibcon#read 3, iclass 11, count 2 2006.285.13:14:32.34#ibcon#about to read 4, iclass 11, count 2 2006.285.13:14:32.34#ibcon#read 4, iclass 11, count 2 2006.285.13:14:32.34#ibcon#about to read 5, iclass 11, count 2 2006.285.13:14:32.34#ibcon#read 5, iclass 11, count 2 2006.285.13:14:32.34#ibcon#about to read 6, iclass 11, count 2 2006.285.13:14:32.34#ibcon#read 6, iclass 11, count 2 2006.285.13:14:32.34#ibcon#end of sib2, iclass 11, count 2 2006.285.13:14:32.34#ibcon#*mode == 0, iclass 11, count 2 2006.285.13:14:32.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.13:14:32.34#ibcon#[27=AT08-04\r\n] 2006.285.13:14:32.34#ibcon#*before write, iclass 11, count 2 2006.285.13:14:32.34#ibcon#enter sib2, iclass 11, count 2 2006.285.13:14:32.34#ibcon#flushed, iclass 11, count 2 2006.285.13:14:32.34#ibcon#about to write, iclass 11, count 2 2006.285.13:14:32.34#ibcon#wrote, iclass 11, count 2 2006.285.13:14:32.34#ibcon#about to read 3, iclass 11, count 2 2006.285.13:14:32.37#ibcon#read 3, iclass 11, count 2 2006.285.13:14:32.37#ibcon#about to read 4, iclass 11, count 2 2006.285.13:14:32.37#ibcon#read 4, iclass 11, count 2 2006.285.13:14:32.37#ibcon#about to read 5, iclass 11, count 2 2006.285.13:14:32.37#ibcon#read 5, iclass 11, count 2 2006.285.13:14:32.37#ibcon#about to read 6, iclass 11, count 2 2006.285.13:14:32.37#ibcon#read 6, iclass 11, count 2 2006.285.13:14:32.37#ibcon#end of sib2, iclass 11, count 2 2006.285.13:14:32.37#ibcon#*after write, iclass 11, count 2 2006.285.13:14:32.37#ibcon#*before return 0, iclass 11, count 2 2006.285.13:14:32.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:14:32.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:14:32.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.13:14:32.37#ibcon#ireg 7 cls_cnt 0 2006.285.13:14:32.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:14:32.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:14:32.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:14:32.49#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:14:32.49#ibcon#first serial, iclass 11, count 0 2006.285.13:14:32.49#ibcon#enter sib2, iclass 11, count 0 2006.285.13:14:32.49#ibcon#flushed, iclass 11, count 0 2006.285.13:14:32.49#ibcon#about to write, iclass 11, count 0 2006.285.13:14:32.49#ibcon#wrote, iclass 11, count 0 2006.285.13:14:32.49#ibcon#about to read 3, iclass 11, count 0 2006.285.13:14:32.51#ibcon#read 3, iclass 11, count 0 2006.285.13:14:32.51#ibcon#about to read 4, iclass 11, count 0 2006.285.13:14:32.51#ibcon#read 4, iclass 11, count 0 2006.285.13:14:32.51#ibcon#about to read 5, iclass 11, count 0 2006.285.13:14:32.51#ibcon#read 5, iclass 11, count 0 2006.285.13:14:32.51#ibcon#about to read 6, iclass 11, count 0 2006.285.13:14:32.51#ibcon#read 6, iclass 11, count 0 2006.285.13:14:32.51#ibcon#end of sib2, iclass 11, count 0 2006.285.13:14:32.51#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:14:32.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:14:32.51#ibcon#[27=USB\r\n] 2006.285.13:14:32.51#ibcon#*before write, iclass 11, count 0 2006.285.13:14:32.51#ibcon#enter sib2, iclass 11, count 0 2006.285.13:14:32.51#ibcon#flushed, iclass 11, count 0 2006.285.13:14:32.51#ibcon#about to write, iclass 11, count 0 2006.285.13:14:32.51#ibcon#wrote, iclass 11, count 0 2006.285.13:14:32.51#ibcon#about to read 3, iclass 11, count 0 2006.285.13:14:32.54#ibcon#read 3, iclass 11, count 0 2006.285.13:14:32.54#ibcon#about to read 4, iclass 11, count 0 2006.285.13:14:32.54#ibcon#read 4, iclass 11, count 0 2006.285.13:14:32.54#ibcon#about to read 5, iclass 11, count 0 2006.285.13:14:32.54#ibcon#read 5, iclass 11, count 0 2006.285.13:14:32.54#ibcon#about to read 6, iclass 11, count 0 2006.285.13:14:32.54#ibcon#read 6, iclass 11, count 0 2006.285.13:14:32.54#ibcon#end of sib2, iclass 11, count 0 2006.285.13:14:32.54#ibcon#*after write, iclass 11, count 0 2006.285.13:14:32.54#ibcon#*before return 0, iclass 11, count 0 2006.285.13:14:32.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:14:32.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:14:32.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:14:32.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:14:32.54$vck44/vabw=wide 2006.285.13:14:32.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.13:14:32.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.13:14:32.54#ibcon#ireg 8 cls_cnt 0 2006.285.13:14:32.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:14:32.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:14:32.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:14:32.54#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:14:32.54#ibcon#first serial, iclass 13, count 0 2006.285.13:14:32.54#ibcon#enter sib2, iclass 13, count 0 2006.285.13:14:32.54#ibcon#flushed, iclass 13, count 0 2006.285.13:14:32.54#ibcon#about to write, iclass 13, count 0 2006.285.13:14:32.54#ibcon#wrote, iclass 13, count 0 2006.285.13:14:32.54#ibcon#about to read 3, iclass 13, count 0 2006.285.13:14:32.56#ibcon#read 3, iclass 13, count 0 2006.285.13:14:32.56#ibcon#about to read 4, iclass 13, count 0 2006.285.13:14:32.56#ibcon#read 4, iclass 13, count 0 2006.285.13:14:32.56#ibcon#about to read 5, iclass 13, count 0 2006.285.13:14:32.56#ibcon#read 5, iclass 13, count 0 2006.285.13:14:32.56#ibcon#about to read 6, iclass 13, count 0 2006.285.13:14:32.56#ibcon#read 6, iclass 13, count 0 2006.285.13:14:32.56#ibcon#end of sib2, iclass 13, count 0 2006.285.13:14:32.56#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:14:32.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:14:32.56#ibcon#[25=BW32\r\n] 2006.285.13:14:32.56#ibcon#*before write, iclass 13, count 0 2006.285.13:14:32.56#ibcon#enter sib2, iclass 13, count 0 2006.285.13:14:32.56#ibcon#flushed, iclass 13, count 0 2006.285.13:14:32.56#ibcon#about to write, iclass 13, count 0 2006.285.13:14:32.56#ibcon#wrote, iclass 13, count 0 2006.285.13:14:32.56#ibcon#about to read 3, iclass 13, count 0 2006.285.13:14:32.59#ibcon#read 3, iclass 13, count 0 2006.285.13:14:32.59#ibcon#about to read 4, iclass 13, count 0 2006.285.13:14:32.59#ibcon#read 4, iclass 13, count 0 2006.285.13:14:32.59#ibcon#about to read 5, iclass 13, count 0 2006.285.13:14:32.59#ibcon#read 5, iclass 13, count 0 2006.285.13:14:32.59#ibcon#about to read 6, iclass 13, count 0 2006.285.13:14:32.59#ibcon#read 6, iclass 13, count 0 2006.285.13:14:32.59#ibcon#end of sib2, iclass 13, count 0 2006.285.13:14:32.59#ibcon#*after write, iclass 13, count 0 2006.285.13:14:32.59#ibcon#*before return 0, iclass 13, count 0 2006.285.13:14:32.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:14:32.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:14:32.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:14:32.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:14:32.59$vck44/vbbw=wide 2006.285.13:14:32.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.13:14:32.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.13:14:32.59#ibcon#ireg 8 cls_cnt 0 2006.285.13:14:32.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:14:32.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:14:32.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:14:32.66#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:14:32.66#ibcon#first serial, iclass 15, count 0 2006.285.13:14:32.66#ibcon#enter sib2, iclass 15, count 0 2006.285.13:14:32.66#ibcon#flushed, iclass 15, count 0 2006.285.13:14:32.66#ibcon#about to write, iclass 15, count 0 2006.285.13:14:32.66#ibcon#wrote, iclass 15, count 0 2006.285.13:14:32.66#ibcon#about to read 3, iclass 15, count 0 2006.285.13:14:32.68#ibcon#read 3, iclass 15, count 0 2006.285.13:14:32.68#ibcon#about to read 4, iclass 15, count 0 2006.285.13:14:32.68#ibcon#read 4, iclass 15, count 0 2006.285.13:14:32.68#ibcon#about to read 5, iclass 15, count 0 2006.285.13:14:32.68#ibcon#read 5, iclass 15, count 0 2006.285.13:14:32.68#ibcon#about to read 6, iclass 15, count 0 2006.285.13:14:32.68#ibcon#read 6, iclass 15, count 0 2006.285.13:14:32.68#ibcon#end of sib2, iclass 15, count 0 2006.285.13:14:32.68#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:14:32.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:14:32.68#ibcon#[27=BW32\r\n] 2006.285.13:14:32.68#ibcon#*before write, iclass 15, count 0 2006.285.13:14:32.68#ibcon#enter sib2, iclass 15, count 0 2006.285.13:14:32.68#ibcon#flushed, iclass 15, count 0 2006.285.13:14:32.68#ibcon#about to write, iclass 15, count 0 2006.285.13:14:32.68#ibcon#wrote, iclass 15, count 0 2006.285.13:14:32.68#ibcon#about to read 3, iclass 15, count 0 2006.285.13:14:32.71#ibcon#read 3, iclass 15, count 0 2006.285.13:14:32.71#ibcon#about to read 4, iclass 15, count 0 2006.285.13:14:32.71#ibcon#read 4, iclass 15, count 0 2006.285.13:14:32.71#ibcon#about to read 5, iclass 15, count 0 2006.285.13:14:32.71#ibcon#read 5, iclass 15, count 0 2006.285.13:14:32.71#ibcon#about to read 6, iclass 15, count 0 2006.285.13:14:32.71#ibcon#read 6, iclass 15, count 0 2006.285.13:14:32.71#ibcon#end of sib2, iclass 15, count 0 2006.285.13:14:32.71#ibcon#*after write, iclass 15, count 0 2006.285.13:14:32.71#ibcon#*before return 0, iclass 15, count 0 2006.285.13:14:32.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:14:32.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:14:32.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:14:32.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:14:32.71$setupk4/ifdk4 2006.285.13:14:32.71$ifdk4/lo= 2006.285.13:14:32.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:14:32.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:14:32.71$ifdk4/patch= 2006.285.13:14:32.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:14:32.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:14:32.71$setupk4/!*+20s 2006.285.13:14:42.27#abcon#<5=/04 1.5 3.2 19.03 961015.3\r\n> 2006.285.13:14:42.29#abcon#{5=INTERFACE CLEAR} 2006.285.13:14:42.35#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:14:46.09$setupk4/"tpicd 2006.285.13:14:46.09$setupk4/echo=off 2006.285.13:14:46.09$setupk4/xlog=off 2006.285.13:14:46.09:!2006.285.13:19:37 2006.285.13:15:03.14#trakl#Source acquired 2006.285.13:15:05.14#flagr#flagr/antenna,acquired 2006.285.13:19:37.00:preob 2006.285.13:19:37.13/onsource/TRACKING 2006.285.13:19:37.13:!2006.285.13:19:47 2006.285.13:19:47.00:"tape 2006.285.13:19:47.00:"st=record 2006.285.13:19:47.00:data_valid=on 2006.285.13:19:47.00:midob 2006.285.13:19:47.13/onsource/TRACKING 2006.285.13:19:47.13/wx/19.04,1015.3,97 2006.285.13:19:47.22/cable/+6.4960E-03 2006.285.13:19:48.31/va/01,07,usb,yes,31,34 2006.285.13:19:48.31/va/02,06,usb,yes,32,32 2006.285.13:19:48.31/va/03,07,usb,yes,31,33 2006.285.13:19:48.31/va/04,06,usb,yes,33,34 2006.285.13:19:48.31/va/05,03,usb,yes,32,32 2006.285.13:19:48.31/va/06,04,usb,yes,29,28 2006.285.13:19:48.31/va/07,04,usb,yes,29,30 2006.285.13:19:48.31/va/08,03,usb,yes,30,37 2006.285.13:19:48.54/valo/01,524.99,yes,locked 2006.285.13:19:48.54/valo/02,534.99,yes,locked 2006.285.13:19:48.54/valo/03,564.99,yes,locked 2006.285.13:19:48.54/valo/04,624.99,yes,locked 2006.285.13:19:48.54/valo/05,734.99,yes,locked 2006.285.13:19:48.54/valo/06,814.99,yes,locked 2006.285.13:19:48.54/valo/07,864.99,yes,locked 2006.285.13:19:48.54/valo/08,884.99,yes,locked 2006.285.13:19:49.63/vb/01,04,usb,yes,30,28 2006.285.13:19:49.63/vb/02,05,usb,yes,28,28 2006.285.13:19:49.63/vb/03,04,usb,yes,29,32 2006.285.13:19:49.63/vb/04,05,usb,yes,30,28 2006.285.13:19:49.63/vb/05,04,usb,yes,26,28 2006.285.13:19:49.63/vb/06,03,usb,yes,38,33 2006.285.13:19:49.63/vb/07,04,usb,yes,30,30 2006.285.13:19:49.63/vb/08,04,usb,yes,27,31 2006.285.13:19:49.86/vblo/01,629.99,yes,locked 2006.285.13:19:49.86/vblo/02,634.99,yes,locked 2006.285.13:19:49.86/vblo/03,649.99,yes,locked 2006.285.13:19:49.86/vblo/04,679.99,yes,locked 2006.285.13:19:49.86/vblo/05,709.99,yes,locked 2006.285.13:19:49.86/vblo/06,719.99,yes,locked 2006.285.13:19:49.86/vblo/07,734.99,yes,locked 2006.285.13:19:49.86/vblo/08,744.99,yes,locked 2006.285.13:19:50.01/vabw/8 2006.285.13:19:50.16/vbbw/8 2006.285.13:19:50.25/xfe/off,on,12.0 2006.285.13:19:50.62/ifatt/23,28,28,28 2006.285.13:19:51.08/fmout-gps/S +2.69E-07 2006.285.13:19:51.10:!2006.285.13:21:37 2006.285.13:21:37.01:data_valid=off 2006.285.13:21:37.01:"et 2006.285.13:21:37.01:!+3s 2006.285.13:21:40.02:"tape 2006.285.13:21:40.02:postob 2006.285.13:21:40.19/cable/+6.4963E-03 2006.285.13:21:40.19/wx/19.06,1015.3,97 2006.285.13:21:41.08/fmout-gps/S +2.70E-07 2006.285.13:21:41.08:scan_name=285-1324,jd0610,40 2006.285.13:21:41.08:source=3c345,164258.81,394837.0,2000.0,ccw 2006.285.13:21:42.14#flagr#flagr/antenna,new-source 2006.285.13:21:42.14:checkk5 2006.285.13:21:42.59/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:21:43.00/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:21:43.77/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:21:44.41/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:21:44.78/chk_obsdata//k5ts1/T2851319??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.13:21:45.26/chk_obsdata//k5ts2/T2851319??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.13:21:45.67/chk_obsdata//k5ts3/T2851319??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.13:21:46.06/chk_obsdata//k5ts4/T2851319??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.13:21:47.03/k5log//k5ts1_log_newline 2006.285.13:21:48.25/k5log//k5ts2_log_newline 2006.285.13:21:49.03/k5log//k5ts3_log_newline 2006.285.13:21:49.89/k5log//k5ts4_log_newline 2006.285.13:21:49.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:21:49.91:setupk4=1 2006.285.13:21:49.91$setupk4/echo=on 2006.285.13:21:49.91$setupk4/pcalon 2006.285.13:21:49.91$pcalon/"no phase cal control is implemented here 2006.285.13:21:49.91$setupk4/"tpicd=stop 2006.285.13:21:49.91$setupk4/"rec=synch_on 2006.285.13:21:49.91$setupk4/"rec_mode=128 2006.285.13:21:49.91$setupk4/!* 2006.285.13:21:49.91$setupk4/recpk4 2006.285.13:21:49.91$recpk4/recpatch= 2006.285.13:21:49.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:21:49.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:21:49.92$setupk4/vck44 2006.285.13:21:49.92$vck44/valo=1,524.99 2006.285.13:21:49.92#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.13:21:49.92#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.13:21:49.92#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:49.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:21:49.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:21:49.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:21:49.92#ibcon#enter wrdev, iclass 12, count 0 2006.285.13:21:49.92#ibcon#first serial, iclass 12, count 0 2006.285.13:21:49.92#ibcon#enter sib2, iclass 12, count 0 2006.285.13:21:49.92#ibcon#flushed, iclass 12, count 0 2006.285.13:21:49.92#ibcon#about to write, iclass 12, count 0 2006.285.13:21:49.92#ibcon#wrote, iclass 12, count 0 2006.285.13:21:49.92#ibcon#about to read 3, iclass 12, count 0 2006.285.13:21:49.93#ibcon#read 3, iclass 12, count 0 2006.285.13:21:49.93#ibcon#about to read 4, iclass 12, count 0 2006.285.13:21:49.93#ibcon#read 4, iclass 12, count 0 2006.285.13:21:49.93#ibcon#about to read 5, iclass 12, count 0 2006.285.13:21:49.93#ibcon#read 5, iclass 12, count 0 2006.285.13:21:49.93#ibcon#about to read 6, iclass 12, count 0 2006.285.13:21:49.93#ibcon#read 6, iclass 12, count 0 2006.285.13:21:49.93#ibcon#end of sib2, iclass 12, count 0 2006.285.13:21:49.93#ibcon#*mode == 0, iclass 12, count 0 2006.285.13:21:49.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.13:21:49.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:21:49.93#ibcon#*before write, iclass 12, count 0 2006.285.13:21:49.93#ibcon#enter sib2, iclass 12, count 0 2006.285.13:21:49.93#ibcon#flushed, iclass 12, count 0 2006.285.13:21:49.93#ibcon#about to write, iclass 12, count 0 2006.285.13:21:49.93#ibcon#wrote, iclass 12, count 0 2006.285.13:21:49.93#ibcon#about to read 3, iclass 12, count 0 2006.285.13:21:49.98#ibcon#read 3, iclass 12, count 0 2006.285.13:21:49.98#ibcon#about to read 4, iclass 12, count 0 2006.285.13:21:49.98#ibcon#read 4, iclass 12, count 0 2006.285.13:21:49.98#ibcon#about to read 5, iclass 12, count 0 2006.285.13:21:49.98#ibcon#read 5, iclass 12, count 0 2006.285.13:21:49.98#ibcon#about to read 6, iclass 12, count 0 2006.285.13:21:49.98#ibcon#read 6, iclass 12, count 0 2006.285.13:21:49.98#ibcon#end of sib2, iclass 12, count 0 2006.285.13:21:49.98#ibcon#*after write, iclass 12, count 0 2006.285.13:21:49.98#ibcon#*before return 0, iclass 12, count 0 2006.285.13:21:49.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:21:49.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:21:49.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.13:21:49.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.13:21:49.98$vck44/va=1,7 2006.285.13:21:49.98#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.13:21:49.98#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.13:21:49.98#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:49.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:21:49.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:21:49.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:21:49.98#ibcon#enter wrdev, iclass 14, count 2 2006.285.13:21:49.98#ibcon#first serial, iclass 14, count 2 2006.285.13:21:49.98#ibcon#enter sib2, iclass 14, count 2 2006.285.13:21:49.98#ibcon#flushed, iclass 14, count 2 2006.285.13:21:49.98#ibcon#about to write, iclass 14, count 2 2006.285.13:21:49.98#ibcon#wrote, iclass 14, count 2 2006.285.13:21:49.98#ibcon#about to read 3, iclass 14, count 2 2006.285.13:21:50.00#ibcon#read 3, iclass 14, count 2 2006.285.13:21:50.00#ibcon#about to read 4, iclass 14, count 2 2006.285.13:21:50.00#ibcon#read 4, iclass 14, count 2 2006.285.13:21:50.00#ibcon#about to read 5, iclass 14, count 2 2006.285.13:21:50.00#ibcon#read 5, iclass 14, count 2 2006.285.13:21:50.00#ibcon#about to read 6, iclass 14, count 2 2006.285.13:21:50.00#ibcon#read 6, iclass 14, count 2 2006.285.13:21:50.00#ibcon#end of sib2, iclass 14, count 2 2006.285.13:21:50.00#ibcon#*mode == 0, iclass 14, count 2 2006.285.13:21:50.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.13:21:50.00#ibcon#[25=AT01-07\r\n] 2006.285.13:21:50.00#ibcon#*before write, iclass 14, count 2 2006.285.13:21:50.00#ibcon#enter sib2, iclass 14, count 2 2006.285.13:21:50.00#ibcon#flushed, iclass 14, count 2 2006.285.13:21:50.00#ibcon#about to write, iclass 14, count 2 2006.285.13:21:50.00#ibcon#wrote, iclass 14, count 2 2006.285.13:21:50.00#ibcon#about to read 3, iclass 14, count 2 2006.285.13:21:50.03#ibcon#read 3, iclass 14, count 2 2006.285.13:21:50.03#ibcon#about to read 4, iclass 14, count 2 2006.285.13:21:50.03#ibcon#read 4, iclass 14, count 2 2006.285.13:21:50.03#ibcon#about to read 5, iclass 14, count 2 2006.285.13:21:50.03#ibcon#read 5, iclass 14, count 2 2006.285.13:21:50.03#ibcon#about to read 6, iclass 14, count 2 2006.285.13:21:50.03#ibcon#read 6, iclass 14, count 2 2006.285.13:21:50.03#ibcon#end of sib2, iclass 14, count 2 2006.285.13:21:50.03#ibcon#*after write, iclass 14, count 2 2006.285.13:21:50.03#ibcon#*before return 0, iclass 14, count 2 2006.285.13:21:50.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:21:50.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:21:50.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.13:21:50.03#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:50.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:21:50.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:21:50.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:21:50.15#ibcon#enter wrdev, iclass 14, count 0 2006.285.13:21:50.15#ibcon#first serial, iclass 14, count 0 2006.285.13:21:50.15#ibcon#enter sib2, iclass 14, count 0 2006.285.13:21:50.15#ibcon#flushed, iclass 14, count 0 2006.285.13:21:50.15#ibcon#about to write, iclass 14, count 0 2006.285.13:21:50.15#ibcon#wrote, iclass 14, count 0 2006.285.13:21:50.15#ibcon#about to read 3, iclass 14, count 0 2006.285.13:21:50.17#ibcon#read 3, iclass 14, count 0 2006.285.13:21:50.17#ibcon#about to read 4, iclass 14, count 0 2006.285.13:21:50.17#ibcon#read 4, iclass 14, count 0 2006.285.13:21:50.17#ibcon#about to read 5, iclass 14, count 0 2006.285.13:21:50.17#ibcon#read 5, iclass 14, count 0 2006.285.13:21:50.17#ibcon#about to read 6, iclass 14, count 0 2006.285.13:21:50.17#ibcon#read 6, iclass 14, count 0 2006.285.13:21:50.17#ibcon#end of sib2, iclass 14, count 0 2006.285.13:21:50.17#ibcon#*mode == 0, iclass 14, count 0 2006.285.13:21:50.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.13:21:50.17#ibcon#[25=USB\r\n] 2006.285.13:21:50.17#ibcon#*before write, iclass 14, count 0 2006.285.13:21:50.17#ibcon#enter sib2, iclass 14, count 0 2006.285.13:21:50.17#ibcon#flushed, iclass 14, count 0 2006.285.13:21:50.17#ibcon#about to write, iclass 14, count 0 2006.285.13:21:50.17#ibcon#wrote, iclass 14, count 0 2006.285.13:21:50.17#ibcon#about to read 3, iclass 14, count 0 2006.285.13:21:50.20#ibcon#read 3, iclass 14, count 0 2006.285.13:21:50.20#ibcon#about to read 4, iclass 14, count 0 2006.285.13:21:50.20#ibcon#read 4, iclass 14, count 0 2006.285.13:21:50.20#ibcon#about to read 5, iclass 14, count 0 2006.285.13:21:50.20#ibcon#read 5, iclass 14, count 0 2006.285.13:21:50.20#ibcon#about to read 6, iclass 14, count 0 2006.285.13:21:50.20#ibcon#read 6, iclass 14, count 0 2006.285.13:21:50.20#ibcon#end of sib2, iclass 14, count 0 2006.285.13:21:50.20#ibcon#*after write, iclass 14, count 0 2006.285.13:21:50.20#ibcon#*before return 0, iclass 14, count 0 2006.285.13:21:50.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:21:50.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:21:50.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.13:21:50.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.13:21:50.20$vck44/valo=2,534.99 2006.285.13:21:50.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.13:21:50.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.13:21:50.20#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:50.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:21:50.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:21:50.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:21:50.20#ibcon#enter wrdev, iclass 16, count 0 2006.285.13:21:50.20#ibcon#first serial, iclass 16, count 0 2006.285.13:21:50.20#ibcon#enter sib2, iclass 16, count 0 2006.285.13:21:50.20#ibcon#flushed, iclass 16, count 0 2006.285.13:21:50.20#ibcon#about to write, iclass 16, count 0 2006.285.13:21:50.20#ibcon#wrote, iclass 16, count 0 2006.285.13:21:50.20#ibcon#about to read 3, iclass 16, count 0 2006.285.13:21:50.60#ibcon#read 3, iclass 16, count 0 2006.285.13:21:50.60#ibcon#about to read 4, iclass 16, count 0 2006.285.13:21:50.60#ibcon#read 4, iclass 16, count 0 2006.285.13:21:50.60#ibcon#about to read 5, iclass 16, count 0 2006.285.13:21:50.60#ibcon#read 5, iclass 16, count 0 2006.285.13:21:50.60#ibcon#about to read 6, iclass 16, count 0 2006.285.13:21:50.60#ibcon#read 6, iclass 16, count 0 2006.285.13:21:50.60#ibcon#end of sib2, iclass 16, count 0 2006.285.13:21:50.60#ibcon#*mode == 0, iclass 16, count 0 2006.285.13:21:50.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.13:21:50.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:21:50.60#ibcon#*before write, iclass 16, count 0 2006.285.13:21:50.60#ibcon#enter sib2, iclass 16, count 0 2006.285.13:21:50.60#ibcon#flushed, iclass 16, count 0 2006.285.13:21:50.60#ibcon#about to write, iclass 16, count 0 2006.285.13:21:50.60#ibcon#wrote, iclass 16, count 0 2006.285.13:21:50.60#ibcon#about to read 3, iclass 16, count 0 2006.285.13:21:50.64#ibcon#read 3, iclass 16, count 0 2006.285.13:21:50.64#ibcon#about to read 4, iclass 16, count 0 2006.285.13:21:50.64#ibcon#read 4, iclass 16, count 0 2006.285.13:21:50.64#ibcon#about to read 5, iclass 16, count 0 2006.285.13:21:50.64#ibcon#read 5, iclass 16, count 0 2006.285.13:21:50.64#ibcon#about to read 6, iclass 16, count 0 2006.285.13:21:50.64#ibcon#read 6, iclass 16, count 0 2006.285.13:21:50.64#ibcon#end of sib2, iclass 16, count 0 2006.285.13:21:50.64#ibcon#*after write, iclass 16, count 0 2006.285.13:21:50.64#ibcon#*before return 0, iclass 16, count 0 2006.285.13:21:50.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:21:50.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:21:50.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.13:21:50.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.13:21:50.64$vck44/va=2,6 2006.285.13:21:50.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.13:21:50.64#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.13:21:50.64#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:50.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:21:50.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:21:50.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:21:50.64#ibcon#enter wrdev, iclass 18, count 2 2006.285.13:21:50.64#ibcon#first serial, iclass 18, count 2 2006.285.13:21:50.64#ibcon#enter sib2, iclass 18, count 2 2006.285.13:21:50.64#ibcon#flushed, iclass 18, count 2 2006.285.13:21:50.64#ibcon#about to write, iclass 18, count 2 2006.285.13:21:50.64#ibcon#wrote, iclass 18, count 2 2006.285.13:21:50.64#ibcon#about to read 3, iclass 18, count 2 2006.285.13:21:50.66#ibcon#read 3, iclass 18, count 2 2006.285.13:21:50.66#ibcon#about to read 4, iclass 18, count 2 2006.285.13:21:50.66#ibcon#read 4, iclass 18, count 2 2006.285.13:21:50.66#ibcon#about to read 5, iclass 18, count 2 2006.285.13:21:50.66#ibcon#read 5, iclass 18, count 2 2006.285.13:21:50.66#ibcon#about to read 6, iclass 18, count 2 2006.285.13:21:50.66#ibcon#read 6, iclass 18, count 2 2006.285.13:21:50.66#ibcon#end of sib2, iclass 18, count 2 2006.285.13:21:50.66#ibcon#*mode == 0, iclass 18, count 2 2006.285.13:21:50.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.13:21:50.66#ibcon#[25=AT02-06\r\n] 2006.285.13:21:50.66#ibcon#*before write, iclass 18, count 2 2006.285.13:21:50.66#ibcon#enter sib2, iclass 18, count 2 2006.285.13:21:50.66#ibcon#flushed, iclass 18, count 2 2006.285.13:21:50.66#ibcon#about to write, iclass 18, count 2 2006.285.13:21:50.66#ibcon#wrote, iclass 18, count 2 2006.285.13:21:50.66#ibcon#about to read 3, iclass 18, count 2 2006.285.13:21:50.69#ibcon#read 3, iclass 18, count 2 2006.285.13:21:50.69#ibcon#about to read 4, iclass 18, count 2 2006.285.13:21:50.69#ibcon#read 4, iclass 18, count 2 2006.285.13:21:50.69#ibcon#about to read 5, iclass 18, count 2 2006.285.13:21:50.69#ibcon#read 5, iclass 18, count 2 2006.285.13:21:50.69#ibcon#about to read 6, iclass 18, count 2 2006.285.13:21:50.69#ibcon#read 6, iclass 18, count 2 2006.285.13:21:50.69#ibcon#end of sib2, iclass 18, count 2 2006.285.13:21:50.69#ibcon#*after write, iclass 18, count 2 2006.285.13:21:50.69#ibcon#*before return 0, iclass 18, count 2 2006.285.13:21:50.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:21:50.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:21:50.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.13:21:50.69#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:50.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:21:50.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:21:50.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:21:50.81#ibcon#enter wrdev, iclass 18, count 0 2006.285.13:21:50.81#ibcon#first serial, iclass 18, count 0 2006.285.13:21:50.81#ibcon#enter sib2, iclass 18, count 0 2006.285.13:21:50.81#ibcon#flushed, iclass 18, count 0 2006.285.13:21:50.81#ibcon#about to write, iclass 18, count 0 2006.285.13:21:50.81#ibcon#wrote, iclass 18, count 0 2006.285.13:21:50.81#ibcon#about to read 3, iclass 18, count 0 2006.285.13:21:50.83#ibcon#read 3, iclass 18, count 0 2006.285.13:21:50.83#ibcon#about to read 4, iclass 18, count 0 2006.285.13:21:50.83#ibcon#read 4, iclass 18, count 0 2006.285.13:21:50.83#ibcon#about to read 5, iclass 18, count 0 2006.285.13:21:50.83#ibcon#read 5, iclass 18, count 0 2006.285.13:21:50.83#ibcon#about to read 6, iclass 18, count 0 2006.285.13:21:50.83#ibcon#read 6, iclass 18, count 0 2006.285.13:21:50.83#ibcon#end of sib2, iclass 18, count 0 2006.285.13:21:50.83#ibcon#*mode == 0, iclass 18, count 0 2006.285.13:21:50.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.13:21:50.83#ibcon#[25=USB\r\n] 2006.285.13:21:50.83#ibcon#*before write, iclass 18, count 0 2006.285.13:21:50.83#ibcon#enter sib2, iclass 18, count 0 2006.285.13:21:50.83#ibcon#flushed, iclass 18, count 0 2006.285.13:21:50.83#ibcon#about to write, iclass 18, count 0 2006.285.13:21:50.83#ibcon#wrote, iclass 18, count 0 2006.285.13:21:50.83#ibcon#about to read 3, iclass 18, count 0 2006.285.13:21:50.86#ibcon#read 3, iclass 18, count 0 2006.285.13:21:50.86#ibcon#about to read 4, iclass 18, count 0 2006.285.13:21:50.86#ibcon#read 4, iclass 18, count 0 2006.285.13:21:50.86#ibcon#about to read 5, iclass 18, count 0 2006.285.13:21:50.86#ibcon#read 5, iclass 18, count 0 2006.285.13:21:50.86#ibcon#about to read 6, iclass 18, count 0 2006.285.13:21:50.86#ibcon#read 6, iclass 18, count 0 2006.285.13:21:50.86#ibcon#end of sib2, iclass 18, count 0 2006.285.13:21:50.86#ibcon#*after write, iclass 18, count 0 2006.285.13:21:50.86#ibcon#*before return 0, iclass 18, count 0 2006.285.13:21:50.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:21:50.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:21:50.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.13:21:50.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.13:21:50.86$vck44/valo=3,564.99 2006.285.13:21:50.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.13:21:50.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.13:21:50.86#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:50.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:21:50.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:21:50.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:21:50.86#ibcon#enter wrdev, iclass 20, count 0 2006.285.13:21:50.86#ibcon#first serial, iclass 20, count 0 2006.285.13:21:50.86#ibcon#enter sib2, iclass 20, count 0 2006.285.13:21:50.86#ibcon#flushed, iclass 20, count 0 2006.285.13:21:50.86#ibcon#about to write, iclass 20, count 0 2006.285.13:21:50.86#ibcon#wrote, iclass 20, count 0 2006.285.13:21:50.86#ibcon#about to read 3, iclass 20, count 0 2006.285.13:21:50.88#ibcon#read 3, iclass 20, count 0 2006.285.13:21:51.07#ibcon#about to read 4, iclass 20, count 0 2006.285.13:21:51.07#ibcon#read 4, iclass 20, count 0 2006.285.13:21:51.07#ibcon#about to read 5, iclass 20, count 0 2006.285.13:21:51.07#ibcon#read 5, iclass 20, count 0 2006.285.13:21:51.07#ibcon#about to read 6, iclass 20, count 0 2006.285.13:21:51.07#ibcon#read 6, iclass 20, count 0 2006.285.13:21:51.07#ibcon#end of sib2, iclass 20, count 0 2006.285.13:21:51.07#ibcon#*mode == 0, iclass 20, count 0 2006.285.13:21:51.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.13:21:51.07#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:21:51.07#ibcon#*before write, iclass 20, count 0 2006.285.13:21:51.07#ibcon#enter sib2, iclass 20, count 0 2006.285.13:21:51.07#ibcon#flushed, iclass 20, count 0 2006.285.13:21:51.07#ibcon#about to write, iclass 20, count 0 2006.285.13:21:51.07#ibcon#wrote, iclass 20, count 0 2006.285.13:21:51.07#ibcon#about to read 3, iclass 20, count 0 2006.285.13:21:51.11#ibcon#read 3, iclass 20, count 0 2006.285.13:21:51.11#ibcon#about to read 4, iclass 20, count 0 2006.285.13:21:51.11#ibcon#read 4, iclass 20, count 0 2006.285.13:21:51.11#ibcon#about to read 5, iclass 20, count 0 2006.285.13:21:51.11#ibcon#read 5, iclass 20, count 0 2006.285.13:21:51.11#ibcon#about to read 6, iclass 20, count 0 2006.285.13:21:51.11#ibcon#read 6, iclass 20, count 0 2006.285.13:21:51.11#ibcon#end of sib2, iclass 20, count 0 2006.285.13:21:51.11#ibcon#*after write, iclass 20, count 0 2006.285.13:21:51.11#ibcon#*before return 0, iclass 20, count 0 2006.285.13:21:51.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:21:51.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:21:51.11#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.13:21:51.11#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.13:21:51.11$vck44/va=3,7 2006.285.13:21:51.11#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.13:21:51.11#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.13:21:51.11#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:51.11#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:21:51.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:21:51.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:21:51.11#ibcon#enter wrdev, iclass 22, count 2 2006.285.13:21:51.11#ibcon#first serial, iclass 22, count 2 2006.285.13:21:51.11#ibcon#enter sib2, iclass 22, count 2 2006.285.13:21:51.11#ibcon#flushed, iclass 22, count 2 2006.285.13:21:51.11#ibcon#about to write, iclass 22, count 2 2006.285.13:21:51.11#ibcon#wrote, iclass 22, count 2 2006.285.13:21:51.11#ibcon#about to read 3, iclass 22, count 2 2006.285.13:21:51.13#ibcon#read 3, iclass 22, count 2 2006.285.13:21:51.13#ibcon#about to read 4, iclass 22, count 2 2006.285.13:21:51.13#ibcon#read 4, iclass 22, count 2 2006.285.13:21:51.13#ibcon#about to read 5, iclass 22, count 2 2006.285.13:21:51.13#ibcon#read 5, iclass 22, count 2 2006.285.13:21:51.13#ibcon#about to read 6, iclass 22, count 2 2006.285.13:21:51.13#ibcon#read 6, iclass 22, count 2 2006.285.13:21:51.13#ibcon#end of sib2, iclass 22, count 2 2006.285.13:21:51.13#ibcon#*mode == 0, iclass 22, count 2 2006.285.13:21:51.13#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.13:21:51.13#ibcon#[25=AT03-07\r\n] 2006.285.13:21:51.13#ibcon#*before write, iclass 22, count 2 2006.285.13:21:51.13#ibcon#enter sib2, iclass 22, count 2 2006.285.13:21:51.13#ibcon#flushed, iclass 22, count 2 2006.285.13:21:51.13#ibcon#about to write, iclass 22, count 2 2006.285.13:21:51.13#ibcon#wrote, iclass 22, count 2 2006.285.13:21:51.13#ibcon#about to read 3, iclass 22, count 2 2006.285.13:21:51.16#ibcon#read 3, iclass 22, count 2 2006.285.13:21:51.16#ibcon#about to read 4, iclass 22, count 2 2006.285.13:21:51.16#ibcon#read 4, iclass 22, count 2 2006.285.13:21:51.16#ibcon#about to read 5, iclass 22, count 2 2006.285.13:21:51.16#ibcon#read 5, iclass 22, count 2 2006.285.13:21:51.16#ibcon#about to read 6, iclass 22, count 2 2006.285.13:21:51.16#ibcon#read 6, iclass 22, count 2 2006.285.13:21:51.16#ibcon#end of sib2, iclass 22, count 2 2006.285.13:21:51.16#ibcon#*after write, iclass 22, count 2 2006.285.13:21:51.16#ibcon#*before return 0, iclass 22, count 2 2006.285.13:21:51.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:21:51.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:21:51.16#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.13:21:51.16#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:51.16#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:21:51.28#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:21:51.28#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:21:51.28#ibcon#enter wrdev, iclass 22, count 0 2006.285.13:21:51.28#ibcon#first serial, iclass 22, count 0 2006.285.13:21:51.28#ibcon#enter sib2, iclass 22, count 0 2006.285.13:21:51.28#ibcon#flushed, iclass 22, count 0 2006.285.13:21:51.28#ibcon#about to write, iclass 22, count 0 2006.285.13:21:51.28#ibcon#wrote, iclass 22, count 0 2006.285.13:21:51.28#ibcon#about to read 3, iclass 22, count 0 2006.285.13:21:51.30#ibcon#read 3, iclass 22, count 0 2006.285.13:21:51.30#ibcon#about to read 4, iclass 22, count 0 2006.285.13:21:51.30#ibcon#read 4, iclass 22, count 0 2006.285.13:21:51.30#ibcon#about to read 5, iclass 22, count 0 2006.285.13:21:51.30#ibcon#read 5, iclass 22, count 0 2006.285.13:21:51.30#ibcon#about to read 6, iclass 22, count 0 2006.285.13:21:51.30#ibcon#read 6, iclass 22, count 0 2006.285.13:21:51.30#ibcon#end of sib2, iclass 22, count 0 2006.285.13:21:51.30#ibcon#*mode == 0, iclass 22, count 0 2006.285.13:21:51.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.13:21:51.30#ibcon#[25=USB\r\n] 2006.285.13:21:51.30#ibcon#*before write, iclass 22, count 0 2006.285.13:21:51.30#ibcon#enter sib2, iclass 22, count 0 2006.285.13:21:51.30#ibcon#flushed, iclass 22, count 0 2006.285.13:21:51.30#ibcon#about to write, iclass 22, count 0 2006.285.13:21:51.30#ibcon#wrote, iclass 22, count 0 2006.285.13:21:51.30#ibcon#about to read 3, iclass 22, count 0 2006.285.13:21:51.33#ibcon#read 3, iclass 22, count 0 2006.285.13:21:51.33#ibcon#about to read 4, iclass 22, count 0 2006.285.13:21:51.33#ibcon#read 4, iclass 22, count 0 2006.285.13:21:51.33#ibcon#about to read 5, iclass 22, count 0 2006.285.13:21:51.33#ibcon#read 5, iclass 22, count 0 2006.285.13:21:51.33#ibcon#about to read 6, iclass 22, count 0 2006.285.13:21:51.33#ibcon#read 6, iclass 22, count 0 2006.285.13:21:51.33#ibcon#end of sib2, iclass 22, count 0 2006.285.13:21:51.33#ibcon#*after write, iclass 22, count 0 2006.285.13:21:51.33#ibcon#*before return 0, iclass 22, count 0 2006.285.13:21:51.33#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:21:51.33#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:21:51.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.13:21:51.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.13:21:51.33$vck44/valo=4,624.99 2006.285.13:21:51.33#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.13:21:51.33#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.13:21:51.33#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:51.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:21:51.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:21:51.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:21:51.33#ibcon#enter wrdev, iclass 24, count 0 2006.285.13:21:51.33#ibcon#first serial, iclass 24, count 0 2006.285.13:21:51.33#ibcon#enter sib2, iclass 24, count 0 2006.285.13:21:51.33#ibcon#flushed, iclass 24, count 0 2006.285.13:21:51.33#ibcon#about to write, iclass 24, count 0 2006.285.13:21:51.33#ibcon#wrote, iclass 24, count 0 2006.285.13:21:51.33#ibcon#about to read 3, iclass 24, count 0 2006.285.13:21:51.35#ibcon#read 3, iclass 24, count 0 2006.285.13:21:51.35#ibcon#about to read 4, iclass 24, count 0 2006.285.13:21:51.35#ibcon#read 4, iclass 24, count 0 2006.285.13:21:51.35#ibcon#about to read 5, iclass 24, count 0 2006.285.13:21:51.35#ibcon#read 5, iclass 24, count 0 2006.285.13:21:51.35#ibcon#about to read 6, iclass 24, count 0 2006.285.13:21:51.35#ibcon#read 6, iclass 24, count 0 2006.285.13:21:51.35#ibcon#end of sib2, iclass 24, count 0 2006.285.13:21:51.35#ibcon#*mode == 0, iclass 24, count 0 2006.285.13:21:51.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.13:21:51.35#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:21:51.35#ibcon#*before write, iclass 24, count 0 2006.285.13:21:51.35#ibcon#enter sib2, iclass 24, count 0 2006.285.13:21:51.35#ibcon#flushed, iclass 24, count 0 2006.285.13:21:51.35#ibcon#about to write, iclass 24, count 0 2006.285.13:21:51.35#ibcon#wrote, iclass 24, count 0 2006.285.13:21:51.35#ibcon#about to read 3, iclass 24, count 0 2006.285.13:21:51.39#ibcon#read 3, iclass 24, count 0 2006.285.13:21:51.39#ibcon#about to read 4, iclass 24, count 0 2006.285.13:21:51.39#ibcon#read 4, iclass 24, count 0 2006.285.13:21:51.39#ibcon#about to read 5, iclass 24, count 0 2006.285.13:21:51.39#ibcon#read 5, iclass 24, count 0 2006.285.13:21:51.39#ibcon#about to read 6, iclass 24, count 0 2006.285.13:21:51.39#ibcon#read 6, iclass 24, count 0 2006.285.13:21:51.39#ibcon#end of sib2, iclass 24, count 0 2006.285.13:21:51.39#ibcon#*after write, iclass 24, count 0 2006.285.13:21:51.39#ibcon#*before return 0, iclass 24, count 0 2006.285.13:21:51.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:21:51.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:21:51.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.13:21:51.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.13:21:51.39$vck44/va=4,6 2006.285.13:21:51.39#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.13:21:51.39#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.13:21:51.39#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:51.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:21:51.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:21:51.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:21:51.45#ibcon#enter wrdev, iclass 26, count 2 2006.285.13:21:51.45#ibcon#first serial, iclass 26, count 2 2006.285.13:21:51.45#ibcon#enter sib2, iclass 26, count 2 2006.285.13:21:51.45#ibcon#flushed, iclass 26, count 2 2006.285.13:21:51.45#ibcon#about to write, iclass 26, count 2 2006.285.13:21:51.45#ibcon#wrote, iclass 26, count 2 2006.285.13:21:51.45#ibcon#about to read 3, iclass 26, count 2 2006.285.13:21:51.47#ibcon#read 3, iclass 26, count 2 2006.285.13:21:51.47#ibcon#about to read 4, iclass 26, count 2 2006.285.13:21:51.47#ibcon#read 4, iclass 26, count 2 2006.285.13:21:51.47#ibcon#about to read 5, iclass 26, count 2 2006.285.13:21:51.47#ibcon#read 5, iclass 26, count 2 2006.285.13:21:51.47#ibcon#about to read 6, iclass 26, count 2 2006.285.13:21:51.47#ibcon#read 6, iclass 26, count 2 2006.285.13:21:51.47#ibcon#end of sib2, iclass 26, count 2 2006.285.13:21:51.47#ibcon#*mode == 0, iclass 26, count 2 2006.285.13:21:51.47#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.13:21:51.47#ibcon#[25=AT04-06\r\n] 2006.285.13:21:51.47#ibcon#*before write, iclass 26, count 2 2006.285.13:21:51.47#ibcon#enter sib2, iclass 26, count 2 2006.285.13:21:51.47#ibcon#flushed, iclass 26, count 2 2006.285.13:21:51.47#ibcon#about to write, iclass 26, count 2 2006.285.13:21:51.47#ibcon#wrote, iclass 26, count 2 2006.285.13:21:51.47#ibcon#about to read 3, iclass 26, count 2 2006.285.13:21:51.50#ibcon#read 3, iclass 26, count 2 2006.285.13:21:51.50#ibcon#about to read 4, iclass 26, count 2 2006.285.13:21:51.50#ibcon#read 4, iclass 26, count 2 2006.285.13:21:51.50#ibcon#about to read 5, iclass 26, count 2 2006.285.13:21:51.50#ibcon#read 5, iclass 26, count 2 2006.285.13:21:51.50#ibcon#about to read 6, iclass 26, count 2 2006.285.13:21:51.50#ibcon#read 6, iclass 26, count 2 2006.285.13:21:51.50#ibcon#end of sib2, iclass 26, count 2 2006.285.13:21:51.50#ibcon#*after write, iclass 26, count 2 2006.285.13:21:51.50#ibcon#*before return 0, iclass 26, count 2 2006.285.13:21:51.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:21:51.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:21:51.50#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.13:21:51.50#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:51.50#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:21:51.62#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:21:51.62#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:21:51.62#ibcon#enter wrdev, iclass 26, count 0 2006.285.13:21:51.62#ibcon#first serial, iclass 26, count 0 2006.285.13:21:51.62#ibcon#enter sib2, iclass 26, count 0 2006.285.13:21:51.62#ibcon#flushed, iclass 26, count 0 2006.285.13:21:51.62#ibcon#about to write, iclass 26, count 0 2006.285.13:21:51.62#ibcon#wrote, iclass 26, count 0 2006.285.13:21:51.62#ibcon#about to read 3, iclass 26, count 0 2006.285.13:21:51.64#ibcon#read 3, iclass 26, count 0 2006.285.13:21:51.64#ibcon#about to read 4, iclass 26, count 0 2006.285.13:21:51.64#ibcon#read 4, iclass 26, count 0 2006.285.13:21:51.64#ibcon#about to read 5, iclass 26, count 0 2006.285.13:21:51.64#ibcon#read 5, iclass 26, count 0 2006.285.13:21:51.64#ibcon#about to read 6, iclass 26, count 0 2006.285.13:21:51.64#ibcon#read 6, iclass 26, count 0 2006.285.13:21:51.64#ibcon#end of sib2, iclass 26, count 0 2006.285.13:21:51.64#ibcon#*mode == 0, iclass 26, count 0 2006.285.13:21:51.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.13:21:51.64#ibcon#[25=USB\r\n] 2006.285.13:21:51.64#ibcon#*before write, iclass 26, count 0 2006.285.13:21:51.64#ibcon#enter sib2, iclass 26, count 0 2006.285.13:21:51.64#ibcon#flushed, iclass 26, count 0 2006.285.13:21:51.64#ibcon#about to write, iclass 26, count 0 2006.285.13:21:51.64#ibcon#wrote, iclass 26, count 0 2006.285.13:21:51.64#ibcon#about to read 3, iclass 26, count 0 2006.285.13:21:51.67#ibcon#read 3, iclass 26, count 0 2006.285.13:21:51.67#ibcon#about to read 4, iclass 26, count 0 2006.285.13:21:51.67#ibcon#read 4, iclass 26, count 0 2006.285.13:21:51.67#ibcon#about to read 5, iclass 26, count 0 2006.285.13:21:51.67#ibcon#read 5, iclass 26, count 0 2006.285.13:21:51.67#ibcon#about to read 6, iclass 26, count 0 2006.285.13:21:51.67#ibcon#read 6, iclass 26, count 0 2006.285.13:21:51.67#ibcon#end of sib2, iclass 26, count 0 2006.285.13:21:51.67#ibcon#*after write, iclass 26, count 0 2006.285.13:21:51.67#ibcon#*before return 0, iclass 26, count 0 2006.285.13:21:51.67#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:21:51.67#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:21:51.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.13:21:51.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.13:21:51.67$vck44/valo=5,734.99 2006.285.13:21:51.67#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.13:21:51.67#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.13:21:51.67#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:51.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:21:51.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:21:51.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:21:51.67#ibcon#enter wrdev, iclass 28, count 0 2006.285.13:21:51.67#ibcon#first serial, iclass 28, count 0 2006.285.13:21:51.67#ibcon#enter sib2, iclass 28, count 0 2006.285.13:21:51.67#ibcon#flushed, iclass 28, count 0 2006.285.13:21:51.67#ibcon#about to write, iclass 28, count 0 2006.285.13:21:51.67#ibcon#wrote, iclass 28, count 0 2006.285.13:21:51.67#ibcon#about to read 3, iclass 28, count 0 2006.285.13:21:51.69#ibcon#read 3, iclass 28, count 0 2006.285.13:21:51.69#ibcon#about to read 4, iclass 28, count 0 2006.285.13:21:51.69#ibcon#read 4, iclass 28, count 0 2006.285.13:21:51.69#ibcon#about to read 5, iclass 28, count 0 2006.285.13:21:51.69#ibcon#read 5, iclass 28, count 0 2006.285.13:21:51.69#ibcon#about to read 6, iclass 28, count 0 2006.285.13:21:51.69#ibcon#read 6, iclass 28, count 0 2006.285.13:21:51.69#ibcon#end of sib2, iclass 28, count 0 2006.285.13:21:51.69#ibcon#*mode == 0, iclass 28, count 0 2006.285.13:21:51.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.13:21:51.69#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:21:51.69#ibcon#*before write, iclass 28, count 0 2006.285.13:21:51.69#ibcon#enter sib2, iclass 28, count 0 2006.285.13:21:51.69#ibcon#flushed, iclass 28, count 0 2006.285.13:21:51.69#ibcon#about to write, iclass 28, count 0 2006.285.13:21:51.69#ibcon#wrote, iclass 28, count 0 2006.285.13:21:51.69#ibcon#about to read 3, iclass 28, count 0 2006.285.13:21:51.73#ibcon#read 3, iclass 28, count 0 2006.285.13:21:51.73#ibcon#about to read 4, iclass 28, count 0 2006.285.13:21:51.73#ibcon#read 4, iclass 28, count 0 2006.285.13:21:51.73#ibcon#about to read 5, iclass 28, count 0 2006.285.13:21:51.73#ibcon#read 5, iclass 28, count 0 2006.285.13:21:51.73#ibcon#about to read 6, iclass 28, count 0 2006.285.13:21:51.73#ibcon#read 6, iclass 28, count 0 2006.285.13:21:51.73#ibcon#end of sib2, iclass 28, count 0 2006.285.13:21:51.73#ibcon#*after write, iclass 28, count 0 2006.285.13:21:51.73#ibcon#*before return 0, iclass 28, count 0 2006.285.13:21:51.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:21:51.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:21:51.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.13:21:51.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.13:21:51.73$vck44/va=5,3 2006.285.13:21:51.73#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.13:21:51.73#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.13:21:51.73#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:51.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:21:51.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:21:51.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:21:51.79#ibcon#enter wrdev, iclass 30, count 2 2006.285.13:21:51.79#ibcon#first serial, iclass 30, count 2 2006.285.13:21:51.79#ibcon#enter sib2, iclass 30, count 2 2006.285.13:21:51.79#ibcon#flushed, iclass 30, count 2 2006.285.13:21:51.79#ibcon#about to write, iclass 30, count 2 2006.285.13:21:51.79#ibcon#wrote, iclass 30, count 2 2006.285.13:21:51.79#ibcon#about to read 3, iclass 30, count 2 2006.285.13:21:51.81#ibcon#read 3, iclass 30, count 2 2006.285.13:21:51.81#ibcon#about to read 4, iclass 30, count 2 2006.285.13:21:51.81#ibcon#read 4, iclass 30, count 2 2006.285.13:21:51.81#ibcon#about to read 5, iclass 30, count 2 2006.285.13:21:51.81#ibcon#read 5, iclass 30, count 2 2006.285.13:21:51.81#ibcon#about to read 6, iclass 30, count 2 2006.285.13:21:51.81#ibcon#read 6, iclass 30, count 2 2006.285.13:21:51.81#ibcon#end of sib2, iclass 30, count 2 2006.285.13:21:51.81#ibcon#*mode == 0, iclass 30, count 2 2006.285.13:21:51.81#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.13:21:51.81#ibcon#[25=AT05-03\r\n] 2006.285.13:21:51.81#ibcon#*before write, iclass 30, count 2 2006.285.13:21:51.81#ibcon#enter sib2, iclass 30, count 2 2006.285.13:21:51.81#ibcon#flushed, iclass 30, count 2 2006.285.13:21:51.81#ibcon#about to write, iclass 30, count 2 2006.285.13:21:51.81#ibcon#wrote, iclass 30, count 2 2006.285.13:21:51.81#ibcon#about to read 3, iclass 30, count 2 2006.285.13:21:51.84#ibcon#read 3, iclass 30, count 2 2006.285.13:21:51.84#ibcon#about to read 4, iclass 30, count 2 2006.285.13:21:51.84#ibcon#read 4, iclass 30, count 2 2006.285.13:21:51.84#ibcon#about to read 5, iclass 30, count 2 2006.285.13:21:51.84#ibcon#read 5, iclass 30, count 2 2006.285.13:21:51.84#ibcon#about to read 6, iclass 30, count 2 2006.285.13:21:51.84#ibcon#read 6, iclass 30, count 2 2006.285.13:21:51.84#ibcon#end of sib2, iclass 30, count 2 2006.285.13:21:51.84#ibcon#*after write, iclass 30, count 2 2006.285.13:21:51.84#ibcon#*before return 0, iclass 30, count 2 2006.285.13:21:51.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:21:51.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:21:51.84#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.13:21:51.84#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:51.84#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:21:51.96#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:21:51.96#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:21:51.96#ibcon#enter wrdev, iclass 30, count 0 2006.285.13:21:51.96#ibcon#first serial, iclass 30, count 0 2006.285.13:21:51.96#ibcon#enter sib2, iclass 30, count 0 2006.285.13:21:51.96#ibcon#flushed, iclass 30, count 0 2006.285.13:21:51.96#ibcon#about to write, iclass 30, count 0 2006.285.13:21:51.96#ibcon#wrote, iclass 30, count 0 2006.285.13:21:51.96#ibcon#about to read 3, iclass 30, count 0 2006.285.13:21:51.98#ibcon#read 3, iclass 30, count 0 2006.285.13:21:51.98#ibcon#about to read 4, iclass 30, count 0 2006.285.13:21:51.98#ibcon#read 4, iclass 30, count 0 2006.285.13:21:51.98#ibcon#about to read 5, iclass 30, count 0 2006.285.13:21:51.98#ibcon#read 5, iclass 30, count 0 2006.285.13:21:51.98#ibcon#about to read 6, iclass 30, count 0 2006.285.13:21:51.98#ibcon#read 6, iclass 30, count 0 2006.285.13:21:51.98#ibcon#end of sib2, iclass 30, count 0 2006.285.13:21:51.98#ibcon#*mode == 0, iclass 30, count 0 2006.285.13:21:51.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.13:21:51.98#ibcon#[25=USB\r\n] 2006.285.13:21:51.98#ibcon#*before write, iclass 30, count 0 2006.285.13:21:51.98#ibcon#enter sib2, iclass 30, count 0 2006.285.13:21:51.98#ibcon#flushed, iclass 30, count 0 2006.285.13:21:51.98#ibcon#about to write, iclass 30, count 0 2006.285.13:21:51.98#ibcon#wrote, iclass 30, count 0 2006.285.13:21:51.98#ibcon#about to read 3, iclass 30, count 0 2006.285.13:21:52.01#ibcon#read 3, iclass 30, count 0 2006.285.13:21:52.01#ibcon#about to read 4, iclass 30, count 0 2006.285.13:21:52.01#ibcon#read 4, iclass 30, count 0 2006.285.13:21:52.01#ibcon#about to read 5, iclass 30, count 0 2006.285.13:21:52.01#ibcon#read 5, iclass 30, count 0 2006.285.13:21:52.01#ibcon#about to read 6, iclass 30, count 0 2006.285.13:21:52.01#ibcon#read 6, iclass 30, count 0 2006.285.13:21:52.01#ibcon#end of sib2, iclass 30, count 0 2006.285.13:21:52.01#ibcon#*after write, iclass 30, count 0 2006.285.13:21:52.01#ibcon#*before return 0, iclass 30, count 0 2006.285.13:21:52.01#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:21:52.01#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:21:52.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.13:21:52.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.13:21:52.01$vck44/valo=6,814.99 2006.285.13:21:52.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.13:21:52.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.13:21:52.01#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:52.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:21:52.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:21:52.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:21:52.01#ibcon#enter wrdev, iclass 32, count 0 2006.285.13:21:52.01#ibcon#first serial, iclass 32, count 0 2006.285.13:21:52.01#ibcon#enter sib2, iclass 32, count 0 2006.285.13:21:52.01#ibcon#flushed, iclass 32, count 0 2006.285.13:21:52.01#ibcon#about to write, iclass 32, count 0 2006.285.13:21:52.01#ibcon#wrote, iclass 32, count 0 2006.285.13:21:52.01#ibcon#about to read 3, iclass 32, count 0 2006.285.13:21:52.03#ibcon#read 3, iclass 32, count 0 2006.285.13:21:52.03#ibcon#about to read 4, iclass 32, count 0 2006.285.13:21:52.03#ibcon#read 4, iclass 32, count 0 2006.285.13:21:52.03#ibcon#about to read 5, iclass 32, count 0 2006.285.13:21:52.03#ibcon#read 5, iclass 32, count 0 2006.285.13:21:52.03#ibcon#about to read 6, iclass 32, count 0 2006.285.13:21:52.03#ibcon#read 6, iclass 32, count 0 2006.285.13:21:52.03#ibcon#end of sib2, iclass 32, count 0 2006.285.13:21:52.03#ibcon#*mode == 0, iclass 32, count 0 2006.285.13:21:52.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.13:21:52.03#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:21:52.03#ibcon#*before write, iclass 32, count 0 2006.285.13:21:52.03#ibcon#enter sib2, iclass 32, count 0 2006.285.13:21:52.03#ibcon#flushed, iclass 32, count 0 2006.285.13:21:52.03#ibcon#about to write, iclass 32, count 0 2006.285.13:21:52.03#ibcon#wrote, iclass 32, count 0 2006.285.13:21:52.03#ibcon#about to read 3, iclass 32, count 0 2006.285.13:21:52.07#ibcon#read 3, iclass 32, count 0 2006.285.13:21:52.07#ibcon#about to read 4, iclass 32, count 0 2006.285.13:21:52.07#ibcon#read 4, iclass 32, count 0 2006.285.13:21:52.07#ibcon#about to read 5, iclass 32, count 0 2006.285.13:21:52.07#ibcon#read 5, iclass 32, count 0 2006.285.13:21:52.07#ibcon#about to read 6, iclass 32, count 0 2006.285.13:21:52.07#ibcon#read 6, iclass 32, count 0 2006.285.13:21:52.07#ibcon#end of sib2, iclass 32, count 0 2006.285.13:21:52.07#ibcon#*after write, iclass 32, count 0 2006.285.13:21:52.07#ibcon#*before return 0, iclass 32, count 0 2006.285.13:21:52.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:21:52.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:21:52.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.13:21:52.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.13:21:52.07$vck44/va=6,4 2006.285.13:21:52.07#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.13:21:52.07#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.13:21:52.07#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:52.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:21:52.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:21:52.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:21:52.13#ibcon#enter wrdev, iclass 34, count 2 2006.285.13:21:52.13#ibcon#first serial, iclass 34, count 2 2006.285.13:21:52.13#ibcon#enter sib2, iclass 34, count 2 2006.285.13:21:52.13#ibcon#flushed, iclass 34, count 2 2006.285.13:21:52.13#ibcon#about to write, iclass 34, count 2 2006.285.13:21:52.13#ibcon#wrote, iclass 34, count 2 2006.285.13:21:52.13#ibcon#about to read 3, iclass 34, count 2 2006.285.13:21:52.15#ibcon#read 3, iclass 34, count 2 2006.285.13:21:52.15#ibcon#about to read 4, iclass 34, count 2 2006.285.13:21:52.15#ibcon#read 4, iclass 34, count 2 2006.285.13:21:52.15#ibcon#about to read 5, iclass 34, count 2 2006.285.13:21:52.15#ibcon#read 5, iclass 34, count 2 2006.285.13:21:52.15#ibcon#about to read 6, iclass 34, count 2 2006.285.13:21:52.15#ibcon#read 6, iclass 34, count 2 2006.285.13:21:52.15#ibcon#end of sib2, iclass 34, count 2 2006.285.13:21:52.15#ibcon#*mode == 0, iclass 34, count 2 2006.285.13:21:52.15#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.13:21:52.15#ibcon#[25=AT06-04\r\n] 2006.285.13:21:52.15#ibcon#*before write, iclass 34, count 2 2006.285.13:21:52.15#ibcon#enter sib2, iclass 34, count 2 2006.285.13:21:52.15#ibcon#flushed, iclass 34, count 2 2006.285.13:21:52.15#ibcon#about to write, iclass 34, count 2 2006.285.13:21:52.15#ibcon#wrote, iclass 34, count 2 2006.285.13:21:52.15#ibcon#about to read 3, iclass 34, count 2 2006.285.13:21:52.18#ibcon#read 3, iclass 34, count 2 2006.285.13:21:52.18#ibcon#about to read 4, iclass 34, count 2 2006.285.13:21:52.18#ibcon#read 4, iclass 34, count 2 2006.285.13:21:52.18#ibcon#about to read 5, iclass 34, count 2 2006.285.13:21:52.18#ibcon#read 5, iclass 34, count 2 2006.285.13:21:52.18#ibcon#about to read 6, iclass 34, count 2 2006.285.13:21:52.18#ibcon#read 6, iclass 34, count 2 2006.285.13:21:52.18#ibcon#end of sib2, iclass 34, count 2 2006.285.13:21:52.18#ibcon#*after write, iclass 34, count 2 2006.285.13:21:52.18#ibcon#*before return 0, iclass 34, count 2 2006.285.13:21:52.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:21:52.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:21:52.18#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.13:21:52.18#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:52.18#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:21:52.30#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:21:52.36#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:21:52.36#ibcon#enter wrdev, iclass 34, count 0 2006.285.13:21:52.36#ibcon#first serial, iclass 34, count 0 2006.285.13:21:52.36#ibcon#enter sib2, iclass 34, count 0 2006.285.13:21:52.36#ibcon#flushed, iclass 34, count 0 2006.285.13:21:52.36#ibcon#about to write, iclass 34, count 0 2006.285.13:21:52.36#ibcon#wrote, iclass 34, count 0 2006.285.13:21:52.36#ibcon#about to read 3, iclass 34, count 0 2006.285.13:21:52.37#ibcon#read 3, iclass 34, count 0 2006.285.13:21:52.37#ibcon#about to read 4, iclass 34, count 0 2006.285.13:21:52.37#ibcon#read 4, iclass 34, count 0 2006.285.13:21:52.37#ibcon#about to read 5, iclass 34, count 0 2006.285.13:21:52.37#ibcon#read 5, iclass 34, count 0 2006.285.13:21:52.37#ibcon#about to read 6, iclass 34, count 0 2006.285.13:21:52.37#ibcon#read 6, iclass 34, count 0 2006.285.13:21:52.37#ibcon#end of sib2, iclass 34, count 0 2006.285.13:21:52.37#ibcon#*mode == 0, iclass 34, count 0 2006.285.13:21:52.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.13:21:52.37#ibcon#[25=USB\r\n] 2006.285.13:21:52.37#ibcon#*before write, iclass 34, count 0 2006.285.13:21:52.37#ibcon#enter sib2, iclass 34, count 0 2006.285.13:21:52.37#ibcon#flushed, iclass 34, count 0 2006.285.13:21:52.37#ibcon#about to write, iclass 34, count 0 2006.285.13:21:52.37#ibcon#wrote, iclass 34, count 0 2006.285.13:21:52.37#ibcon#about to read 3, iclass 34, count 0 2006.285.13:21:52.40#ibcon#read 3, iclass 34, count 0 2006.285.13:21:52.40#ibcon#about to read 4, iclass 34, count 0 2006.285.13:21:52.40#ibcon#read 4, iclass 34, count 0 2006.285.13:21:52.40#ibcon#about to read 5, iclass 34, count 0 2006.285.13:21:52.40#ibcon#read 5, iclass 34, count 0 2006.285.13:21:52.40#ibcon#about to read 6, iclass 34, count 0 2006.285.13:21:52.40#ibcon#read 6, iclass 34, count 0 2006.285.13:21:52.40#ibcon#end of sib2, iclass 34, count 0 2006.285.13:21:52.40#ibcon#*after write, iclass 34, count 0 2006.285.13:21:52.40#ibcon#*before return 0, iclass 34, count 0 2006.285.13:21:52.40#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:21:52.40#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:21:52.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.13:21:52.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.13:21:52.40$vck44/valo=7,864.99 2006.285.13:21:52.40#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.13:21:52.40#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.13:21:52.40#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:52.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:21:52.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:21:52.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:21:52.40#ibcon#enter wrdev, iclass 36, count 0 2006.285.13:21:52.40#ibcon#first serial, iclass 36, count 0 2006.285.13:21:52.40#ibcon#enter sib2, iclass 36, count 0 2006.285.13:21:52.40#ibcon#flushed, iclass 36, count 0 2006.285.13:21:52.40#ibcon#about to write, iclass 36, count 0 2006.285.13:21:52.40#ibcon#wrote, iclass 36, count 0 2006.285.13:21:52.40#ibcon#about to read 3, iclass 36, count 0 2006.285.13:21:52.42#ibcon#read 3, iclass 36, count 0 2006.285.13:21:52.42#ibcon#about to read 4, iclass 36, count 0 2006.285.13:21:52.42#ibcon#read 4, iclass 36, count 0 2006.285.13:21:52.42#ibcon#about to read 5, iclass 36, count 0 2006.285.13:21:52.42#ibcon#read 5, iclass 36, count 0 2006.285.13:21:52.42#ibcon#about to read 6, iclass 36, count 0 2006.285.13:21:52.42#ibcon#read 6, iclass 36, count 0 2006.285.13:21:52.42#ibcon#end of sib2, iclass 36, count 0 2006.285.13:21:52.42#ibcon#*mode == 0, iclass 36, count 0 2006.285.13:21:52.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.13:21:52.42#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:21:52.42#ibcon#*before write, iclass 36, count 0 2006.285.13:21:52.42#ibcon#enter sib2, iclass 36, count 0 2006.285.13:21:52.42#ibcon#flushed, iclass 36, count 0 2006.285.13:21:52.42#ibcon#about to write, iclass 36, count 0 2006.285.13:21:52.42#ibcon#wrote, iclass 36, count 0 2006.285.13:21:52.42#ibcon#about to read 3, iclass 36, count 0 2006.285.13:21:52.46#ibcon#read 3, iclass 36, count 0 2006.285.13:21:52.46#ibcon#about to read 4, iclass 36, count 0 2006.285.13:21:52.46#ibcon#read 4, iclass 36, count 0 2006.285.13:21:52.46#ibcon#about to read 5, iclass 36, count 0 2006.285.13:21:52.46#ibcon#read 5, iclass 36, count 0 2006.285.13:21:52.46#ibcon#about to read 6, iclass 36, count 0 2006.285.13:21:52.46#ibcon#read 6, iclass 36, count 0 2006.285.13:21:52.46#ibcon#end of sib2, iclass 36, count 0 2006.285.13:21:52.46#ibcon#*after write, iclass 36, count 0 2006.285.13:21:52.46#ibcon#*before return 0, iclass 36, count 0 2006.285.13:21:52.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:21:52.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:21:52.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.13:21:52.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.13:21:52.46$vck44/va=7,4 2006.285.13:21:52.46#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.13:21:52.46#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.13:21:52.46#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:52.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:21:52.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:21:52.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:21:52.52#ibcon#enter wrdev, iclass 38, count 2 2006.285.13:21:52.52#ibcon#first serial, iclass 38, count 2 2006.285.13:21:52.52#ibcon#enter sib2, iclass 38, count 2 2006.285.13:21:52.52#ibcon#flushed, iclass 38, count 2 2006.285.13:21:52.52#ibcon#about to write, iclass 38, count 2 2006.285.13:21:52.52#ibcon#wrote, iclass 38, count 2 2006.285.13:21:52.52#ibcon#about to read 3, iclass 38, count 2 2006.285.13:21:52.54#ibcon#read 3, iclass 38, count 2 2006.285.13:21:52.54#ibcon#about to read 4, iclass 38, count 2 2006.285.13:21:52.54#ibcon#read 4, iclass 38, count 2 2006.285.13:21:52.54#ibcon#about to read 5, iclass 38, count 2 2006.285.13:21:52.54#ibcon#read 5, iclass 38, count 2 2006.285.13:21:52.54#ibcon#about to read 6, iclass 38, count 2 2006.285.13:21:52.54#ibcon#read 6, iclass 38, count 2 2006.285.13:21:52.54#ibcon#end of sib2, iclass 38, count 2 2006.285.13:21:52.54#ibcon#*mode == 0, iclass 38, count 2 2006.285.13:21:52.54#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.13:21:52.54#ibcon#[25=AT07-04\r\n] 2006.285.13:21:52.54#ibcon#*before write, iclass 38, count 2 2006.285.13:21:52.54#ibcon#enter sib2, iclass 38, count 2 2006.285.13:21:52.54#ibcon#flushed, iclass 38, count 2 2006.285.13:21:52.54#ibcon#about to write, iclass 38, count 2 2006.285.13:21:52.54#ibcon#wrote, iclass 38, count 2 2006.285.13:21:52.54#ibcon#about to read 3, iclass 38, count 2 2006.285.13:21:52.57#ibcon#read 3, iclass 38, count 2 2006.285.13:21:52.57#ibcon#about to read 4, iclass 38, count 2 2006.285.13:21:52.57#ibcon#read 4, iclass 38, count 2 2006.285.13:21:52.57#ibcon#about to read 5, iclass 38, count 2 2006.285.13:21:52.57#ibcon#read 5, iclass 38, count 2 2006.285.13:21:52.57#ibcon#about to read 6, iclass 38, count 2 2006.285.13:21:52.57#ibcon#read 6, iclass 38, count 2 2006.285.13:21:52.57#ibcon#end of sib2, iclass 38, count 2 2006.285.13:21:52.57#ibcon#*after write, iclass 38, count 2 2006.285.13:21:52.57#ibcon#*before return 0, iclass 38, count 2 2006.285.13:21:52.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:21:52.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:21:52.57#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.13:21:52.57#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:52.57#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:21:52.69#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:21:52.69#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:21:52.69#ibcon#enter wrdev, iclass 38, count 0 2006.285.13:21:52.69#ibcon#first serial, iclass 38, count 0 2006.285.13:21:52.69#ibcon#enter sib2, iclass 38, count 0 2006.285.13:21:52.69#ibcon#flushed, iclass 38, count 0 2006.285.13:21:52.69#ibcon#about to write, iclass 38, count 0 2006.285.13:21:52.69#ibcon#wrote, iclass 38, count 0 2006.285.13:21:52.69#ibcon#about to read 3, iclass 38, count 0 2006.285.13:21:52.71#ibcon#read 3, iclass 38, count 0 2006.285.13:21:52.71#ibcon#about to read 4, iclass 38, count 0 2006.285.13:21:52.71#ibcon#read 4, iclass 38, count 0 2006.285.13:21:52.71#ibcon#about to read 5, iclass 38, count 0 2006.285.13:21:52.71#ibcon#read 5, iclass 38, count 0 2006.285.13:21:52.71#ibcon#about to read 6, iclass 38, count 0 2006.285.13:21:52.71#ibcon#read 6, iclass 38, count 0 2006.285.13:21:52.71#ibcon#end of sib2, iclass 38, count 0 2006.285.13:21:52.71#ibcon#*mode == 0, iclass 38, count 0 2006.285.13:21:52.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.13:21:52.71#ibcon#[25=USB\r\n] 2006.285.13:21:52.71#ibcon#*before write, iclass 38, count 0 2006.285.13:21:52.71#ibcon#enter sib2, iclass 38, count 0 2006.285.13:21:52.71#ibcon#flushed, iclass 38, count 0 2006.285.13:21:52.71#ibcon#about to write, iclass 38, count 0 2006.285.13:21:52.71#ibcon#wrote, iclass 38, count 0 2006.285.13:21:52.71#ibcon#about to read 3, iclass 38, count 0 2006.285.13:21:52.74#ibcon#read 3, iclass 38, count 0 2006.285.13:21:52.74#ibcon#about to read 4, iclass 38, count 0 2006.285.13:21:52.74#ibcon#read 4, iclass 38, count 0 2006.285.13:21:52.74#ibcon#about to read 5, iclass 38, count 0 2006.285.13:21:52.74#ibcon#read 5, iclass 38, count 0 2006.285.13:21:52.74#ibcon#about to read 6, iclass 38, count 0 2006.285.13:21:52.74#ibcon#read 6, iclass 38, count 0 2006.285.13:21:52.74#ibcon#end of sib2, iclass 38, count 0 2006.285.13:21:52.74#ibcon#*after write, iclass 38, count 0 2006.285.13:21:52.74#ibcon#*before return 0, iclass 38, count 0 2006.285.13:21:52.74#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:21:52.74#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:21:52.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.13:21:52.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.13:21:52.74$vck44/valo=8,884.99 2006.285.13:21:52.74#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.13:21:52.74#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.13:21:52.74#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:52.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:21:52.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:21:52.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:21:52.74#ibcon#enter wrdev, iclass 40, count 0 2006.285.13:21:52.74#ibcon#first serial, iclass 40, count 0 2006.285.13:21:52.74#ibcon#enter sib2, iclass 40, count 0 2006.285.13:21:52.74#ibcon#flushed, iclass 40, count 0 2006.285.13:21:52.74#ibcon#about to write, iclass 40, count 0 2006.285.13:21:52.74#ibcon#wrote, iclass 40, count 0 2006.285.13:21:52.74#ibcon#about to read 3, iclass 40, count 0 2006.285.13:21:52.76#ibcon#read 3, iclass 40, count 0 2006.285.13:21:52.76#ibcon#about to read 4, iclass 40, count 0 2006.285.13:21:52.76#ibcon#read 4, iclass 40, count 0 2006.285.13:21:52.76#ibcon#about to read 5, iclass 40, count 0 2006.285.13:21:52.76#ibcon#read 5, iclass 40, count 0 2006.285.13:21:52.76#ibcon#about to read 6, iclass 40, count 0 2006.285.13:21:52.76#ibcon#read 6, iclass 40, count 0 2006.285.13:21:52.76#ibcon#end of sib2, iclass 40, count 0 2006.285.13:21:52.76#ibcon#*mode == 0, iclass 40, count 0 2006.285.13:21:52.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.13:21:52.76#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:21:52.76#ibcon#*before write, iclass 40, count 0 2006.285.13:21:52.76#ibcon#enter sib2, iclass 40, count 0 2006.285.13:21:52.76#ibcon#flushed, iclass 40, count 0 2006.285.13:21:52.76#ibcon#about to write, iclass 40, count 0 2006.285.13:21:52.76#ibcon#wrote, iclass 40, count 0 2006.285.13:21:52.76#ibcon#about to read 3, iclass 40, count 0 2006.285.13:21:52.80#ibcon#read 3, iclass 40, count 0 2006.285.13:21:52.80#ibcon#about to read 4, iclass 40, count 0 2006.285.13:21:52.80#ibcon#read 4, iclass 40, count 0 2006.285.13:21:52.80#ibcon#about to read 5, iclass 40, count 0 2006.285.13:21:52.80#ibcon#read 5, iclass 40, count 0 2006.285.13:21:52.80#ibcon#about to read 6, iclass 40, count 0 2006.285.13:21:52.80#ibcon#read 6, iclass 40, count 0 2006.285.13:21:52.80#ibcon#end of sib2, iclass 40, count 0 2006.285.13:21:52.80#ibcon#*after write, iclass 40, count 0 2006.285.13:21:52.80#ibcon#*before return 0, iclass 40, count 0 2006.285.13:21:52.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:21:52.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:21:52.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.13:21:52.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.13:21:52.80$vck44/va=8,3 2006.285.13:21:52.80#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.13:21:52.80#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.13:21:52.80#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:52.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:21:52.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:21:52.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:21:52.86#ibcon#enter wrdev, iclass 4, count 2 2006.285.13:21:52.86#ibcon#first serial, iclass 4, count 2 2006.285.13:21:52.86#ibcon#enter sib2, iclass 4, count 2 2006.285.13:21:52.86#ibcon#flushed, iclass 4, count 2 2006.285.13:21:52.86#ibcon#about to write, iclass 4, count 2 2006.285.13:21:52.86#ibcon#wrote, iclass 4, count 2 2006.285.13:21:52.86#ibcon#about to read 3, iclass 4, count 2 2006.285.13:21:52.88#ibcon#read 3, iclass 4, count 2 2006.285.13:21:52.88#ibcon#about to read 4, iclass 4, count 2 2006.285.13:21:52.88#ibcon#read 4, iclass 4, count 2 2006.285.13:21:52.88#ibcon#about to read 5, iclass 4, count 2 2006.285.13:21:52.88#ibcon#read 5, iclass 4, count 2 2006.285.13:21:52.88#ibcon#about to read 6, iclass 4, count 2 2006.285.13:21:52.88#ibcon#read 6, iclass 4, count 2 2006.285.13:21:52.88#ibcon#end of sib2, iclass 4, count 2 2006.285.13:21:52.88#ibcon#*mode == 0, iclass 4, count 2 2006.285.13:21:52.88#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.13:21:52.88#ibcon#[25=AT08-03\r\n] 2006.285.13:21:52.88#ibcon#*before write, iclass 4, count 2 2006.285.13:21:52.88#ibcon#enter sib2, iclass 4, count 2 2006.285.13:21:52.88#ibcon#flushed, iclass 4, count 2 2006.285.13:21:52.88#ibcon#about to write, iclass 4, count 2 2006.285.13:21:52.88#ibcon#wrote, iclass 4, count 2 2006.285.13:21:52.88#ibcon#about to read 3, iclass 4, count 2 2006.285.13:21:52.91#ibcon#read 3, iclass 4, count 2 2006.285.13:21:52.91#ibcon#about to read 4, iclass 4, count 2 2006.285.13:21:52.91#ibcon#read 4, iclass 4, count 2 2006.285.13:21:52.91#ibcon#about to read 5, iclass 4, count 2 2006.285.13:21:52.91#ibcon#read 5, iclass 4, count 2 2006.285.13:21:52.91#ibcon#about to read 6, iclass 4, count 2 2006.285.13:21:52.91#ibcon#read 6, iclass 4, count 2 2006.285.13:21:52.91#ibcon#end of sib2, iclass 4, count 2 2006.285.13:21:52.91#ibcon#*after write, iclass 4, count 2 2006.285.13:21:52.91#ibcon#*before return 0, iclass 4, count 2 2006.285.13:21:52.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:21:52.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:21:52.91#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.13:21:52.91#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:52.91#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:21:53.03#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:21:53.03#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:21:53.03#ibcon#enter wrdev, iclass 4, count 0 2006.285.13:21:53.03#ibcon#first serial, iclass 4, count 0 2006.285.13:21:53.03#ibcon#enter sib2, iclass 4, count 0 2006.285.13:21:53.03#ibcon#flushed, iclass 4, count 0 2006.285.13:21:53.03#ibcon#about to write, iclass 4, count 0 2006.285.13:21:53.03#ibcon#wrote, iclass 4, count 0 2006.285.13:21:53.03#ibcon#about to read 3, iclass 4, count 0 2006.285.13:21:53.05#ibcon#read 3, iclass 4, count 0 2006.285.13:21:53.05#ibcon#about to read 4, iclass 4, count 0 2006.285.13:21:53.05#ibcon#read 4, iclass 4, count 0 2006.285.13:21:53.05#ibcon#about to read 5, iclass 4, count 0 2006.285.13:21:53.05#ibcon#read 5, iclass 4, count 0 2006.285.13:21:53.05#ibcon#about to read 6, iclass 4, count 0 2006.285.13:21:53.05#ibcon#read 6, iclass 4, count 0 2006.285.13:21:53.05#ibcon#end of sib2, iclass 4, count 0 2006.285.13:21:53.05#ibcon#*mode == 0, iclass 4, count 0 2006.285.13:21:53.05#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.13:21:53.05#ibcon#[25=USB\r\n] 2006.285.13:21:53.05#ibcon#*before write, iclass 4, count 0 2006.285.13:21:53.05#ibcon#enter sib2, iclass 4, count 0 2006.285.13:21:53.05#ibcon#flushed, iclass 4, count 0 2006.285.13:21:53.05#ibcon#about to write, iclass 4, count 0 2006.285.13:21:53.05#ibcon#wrote, iclass 4, count 0 2006.285.13:21:53.05#ibcon#about to read 3, iclass 4, count 0 2006.285.13:21:53.08#ibcon#read 3, iclass 4, count 0 2006.285.13:21:53.08#ibcon#about to read 4, iclass 4, count 0 2006.285.13:21:53.08#ibcon#read 4, iclass 4, count 0 2006.285.13:21:53.08#ibcon#about to read 5, iclass 4, count 0 2006.285.13:21:53.08#ibcon#read 5, iclass 4, count 0 2006.285.13:21:53.08#ibcon#about to read 6, iclass 4, count 0 2006.285.13:21:53.08#ibcon#read 6, iclass 4, count 0 2006.285.13:21:53.08#ibcon#end of sib2, iclass 4, count 0 2006.285.13:21:53.08#ibcon#*after write, iclass 4, count 0 2006.285.13:21:53.08#ibcon#*before return 0, iclass 4, count 0 2006.285.13:21:53.08#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:21:53.08#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:21:53.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.13:21:53.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.13:21:53.08$vck44/vblo=1,629.99 2006.285.13:21:53.08#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.13:21:53.08#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.13:21:53.08#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:53.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:21:53.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:21:53.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:21:53.08#ibcon#enter wrdev, iclass 6, count 0 2006.285.13:21:53.08#ibcon#first serial, iclass 6, count 0 2006.285.13:21:53.08#ibcon#enter sib2, iclass 6, count 0 2006.285.13:21:53.08#ibcon#flushed, iclass 6, count 0 2006.285.13:21:53.08#ibcon#about to write, iclass 6, count 0 2006.285.13:21:53.08#ibcon#wrote, iclass 6, count 0 2006.285.13:21:53.08#ibcon#about to read 3, iclass 6, count 0 2006.285.13:21:53.10#ibcon#read 3, iclass 6, count 0 2006.285.13:21:53.10#ibcon#about to read 4, iclass 6, count 0 2006.285.13:21:53.10#ibcon#read 4, iclass 6, count 0 2006.285.13:21:53.10#ibcon#about to read 5, iclass 6, count 0 2006.285.13:21:53.10#ibcon#read 5, iclass 6, count 0 2006.285.13:21:53.10#ibcon#about to read 6, iclass 6, count 0 2006.285.13:21:53.10#ibcon#read 6, iclass 6, count 0 2006.285.13:21:53.10#ibcon#end of sib2, iclass 6, count 0 2006.285.13:21:53.10#ibcon#*mode == 0, iclass 6, count 0 2006.285.13:21:53.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.13:21:53.10#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:21:53.10#ibcon#*before write, iclass 6, count 0 2006.285.13:21:53.10#ibcon#enter sib2, iclass 6, count 0 2006.285.13:21:53.10#ibcon#flushed, iclass 6, count 0 2006.285.13:21:53.10#ibcon#about to write, iclass 6, count 0 2006.285.13:21:53.10#ibcon#wrote, iclass 6, count 0 2006.285.13:21:53.10#ibcon#about to read 3, iclass 6, count 0 2006.285.13:21:53.14#ibcon#read 3, iclass 6, count 0 2006.285.13:21:53.14#ibcon#about to read 4, iclass 6, count 0 2006.285.13:21:53.14#ibcon#read 4, iclass 6, count 0 2006.285.13:21:53.14#ibcon#about to read 5, iclass 6, count 0 2006.285.13:21:53.14#ibcon#read 5, iclass 6, count 0 2006.285.13:21:53.14#ibcon#about to read 6, iclass 6, count 0 2006.285.13:21:53.14#ibcon#read 6, iclass 6, count 0 2006.285.13:21:53.14#ibcon#end of sib2, iclass 6, count 0 2006.285.13:21:53.14#ibcon#*after write, iclass 6, count 0 2006.285.13:21:53.14#ibcon#*before return 0, iclass 6, count 0 2006.285.13:21:53.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:21:53.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:21:53.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.13:21:53.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.13:21:53.14$vck44/vb=1,4 2006.285.13:21:53.14#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.13:21:53.14#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.13:21:53.14#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:53.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:21:53.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:21:53.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:21:53.14#ibcon#enter wrdev, iclass 10, count 2 2006.285.13:21:53.14#ibcon#first serial, iclass 10, count 2 2006.285.13:21:53.14#ibcon#enter sib2, iclass 10, count 2 2006.285.13:21:53.14#ibcon#flushed, iclass 10, count 2 2006.285.13:21:53.14#ibcon#about to write, iclass 10, count 2 2006.285.13:21:53.14#ibcon#wrote, iclass 10, count 2 2006.285.13:21:53.14#ibcon#about to read 3, iclass 10, count 2 2006.285.13:21:53.16#ibcon#read 3, iclass 10, count 2 2006.285.13:21:53.16#ibcon#about to read 4, iclass 10, count 2 2006.285.13:21:53.16#ibcon#read 4, iclass 10, count 2 2006.285.13:21:53.16#ibcon#about to read 5, iclass 10, count 2 2006.285.13:21:53.16#ibcon#read 5, iclass 10, count 2 2006.285.13:21:53.16#ibcon#about to read 6, iclass 10, count 2 2006.285.13:21:53.21#ibcon#read 6, iclass 10, count 2 2006.285.13:21:53.21#ibcon#end of sib2, iclass 10, count 2 2006.285.13:21:53.21#ibcon#*mode == 0, iclass 10, count 2 2006.285.13:21:53.21#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.13:21:53.21#ibcon#[27=AT01-04\r\n] 2006.285.13:21:53.21#ibcon#*before write, iclass 10, count 2 2006.285.13:21:53.21#ibcon#enter sib2, iclass 10, count 2 2006.285.13:21:53.21#ibcon#flushed, iclass 10, count 2 2006.285.13:21:53.21#ibcon#about to write, iclass 10, count 2 2006.285.13:21:53.21#ibcon#wrote, iclass 10, count 2 2006.285.13:21:53.21#ibcon#about to read 3, iclass 10, count 2 2006.285.13:21:53.24#ibcon#read 3, iclass 10, count 2 2006.285.13:21:53.24#ibcon#about to read 4, iclass 10, count 2 2006.285.13:21:53.24#ibcon#read 4, iclass 10, count 2 2006.285.13:21:53.24#ibcon#about to read 5, iclass 10, count 2 2006.285.13:21:53.24#ibcon#read 5, iclass 10, count 2 2006.285.13:21:53.24#ibcon#about to read 6, iclass 10, count 2 2006.285.13:21:53.24#ibcon#read 6, iclass 10, count 2 2006.285.13:21:53.24#ibcon#end of sib2, iclass 10, count 2 2006.285.13:21:53.24#ibcon#*after write, iclass 10, count 2 2006.285.13:21:53.24#ibcon#*before return 0, iclass 10, count 2 2006.285.13:21:53.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:21:53.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:21:53.24#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.13:21:53.24#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:53.24#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:21:53.36#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:21:53.36#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:21:53.36#ibcon#enter wrdev, iclass 10, count 0 2006.285.13:21:53.36#ibcon#first serial, iclass 10, count 0 2006.285.13:21:53.36#ibcon#enter sib2, iclass 10, count 0 2006.285.13:21:53.36#ibcon#flushed, iclass 10, count 0 2006.285.13:21:53.36#ibcon#about to write, iclass 10, count 0 2006.285.13:21:53.36#ibcon#wrote, iclass 10, count 0 2006.285.13:21:53.36#ibcon#about to read 3, iclass 10, count 0 2006.285.13:21:53.38#ibcon#read 3, iclass 10, count 0 2006.285.13:21:53.38#ibcon#about to read 4, iclass 10, count 0 2006.285.13:21:53.38#ibcon#read 4, iclass 10, count 0 2006.285.13:21:53.38#ibcon#about to read 5, iclass 10, count 0 2006.285.13:21:53.38#ibcon#read 5, iclass 10, count 0 2006.285.13:21:53.38#ibcon#about to read 6, iclass 10, count 0 2006.285.13:21:53.38#ibcon#read 6, iclass 10, count 0 2006.285.13:21:53.38#ibcon#end of sib2, iclass 10, count 0 2006.285.13:21:53.38#ibcon#*mode == 0, iclass 10, count 0 2006.285.13:21:53.38#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.13:21:53.38#ibcon#[27=USB\r\n] 2006.285.13:21:53.38#ibcon#*before write, iclass 10, count 0 2006.285.13:21:53.38#ibcon#enter sib2, iclass 10, count 0 2006.285.13:21:53.38#ibcon#flushed, iclass 10, count 0 2006.285.13:21:53.38#ibcon#about to write, iclass 10, count 0 2006.285.13:21:53.38#ibcon#wrote, iclass 10, count 0 2006.285.13:21:53.38#ibcon#about to read 3, iclass 10, count 0 2006.285.13:21:53.41#ibcon#read 3, iclass 10, count 0 2006.285.13:21:53.41#ibcon#about to read 4, iclass 10, count 0 2006.285.13:21:53.41#ibcon#read 4, iclass 10, count 0 2006.285.13:21:53.41#ibcon#about to read 5, iclass 10, count 0 2006.285.13:21:53.41#ibcon#read 5, iclass 10, count 0 2006.285.13:21:53.41#ibcon#about to read 6, iclass 10, count 0 2006.285.13:21:53.41#ibcon#read 6, iclass 10, count 0 2006.285.13:21:53.41#ibcon#end of sib2, iclass 10, count 0 2006.285.13:21:53.41#ibcon#*after write, iclass 10, count 0 2006.285.13:21:53.41#ibcon#*before return 0, iclass 10, count 0 2006.285.13:21:53.41#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:21:53.41#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:21:53.41#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.13:21:53.41#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.13:21:53.41$vck44/vblo=2,634.99 2006.285.13:21:53.41#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.13:21:53.41#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.13:21:53.41#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:53.41#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:21:53.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:21:53.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:21:53.41#ibcon#enter wrdev, iclass 12, count 0 2006.285.13:21:53.41#ibcon#first serial, iclass 12, count 0 2006.285.13:21:53.41#ibcon#enter sib2, iclass 12, count 0 2006.285.13:21:53.41#ibcon#flushed, iclass 12, count 0 2006.285.13:21:53.41#ibcon#about to write, iclass 12, count 0 2006.285.13:21:53.41#ibcon#wrote, iclass 12, count 0 2006.285.13:21:53.41#ibcon#about to read 3, iclass 12, count 0 2006.285.13:21:53.43#ibcon#read 3, iclass 12, count 0 2006.285.13:21:53.43#ibcon#about to read 4, iclass 12, count 0 2006.285.13:21:53.43#ibcon#read 4, iclass 12, count 0 2006.285.13:21:53.43#ibcon#about to read 5, iclass 12, count 0 2006.285.13:21:53.43#ibcon#read 5, iclass 12, count 0 2006.285.13:21:53.43#ibcon#about to read 6, iclass 12, count 0 2006.285.13:21:53.43#ibcon#read 6, iclass 12, count 0 2006.285.13:21:53.43#ibcon#end of sib2, iclass 12, count 0 2006.285.13:21:53.43#ibcon#*mode == 0, iclass 12, count 0 2006.285.13:21:53.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.13:21:53.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:21:53.43#ibcon#*before write, iclass 12, count 0 2006.285.13:21:53.43#ibcon#enter sib2, iclass 12, count 0 2006.285.13:21:53.43#ibcon#flushed, iclass 12, count 0 2006.285.13:21:53.43#ibcon#about to write, iclass 12, count 0 2006.285.13:21:53.43#ibcon#wrote, iclass 12, count 0 2006.285.13:21:53.43#ibcon#about to read 3, iclass 12, count 0 2006.285.13:21:53.47#ibcon#read 3, iclass 12, count 0 2006.285.13:21:53.47#ibcon#about to read 4, iclass 12, count 0 2006.285.13:21:53.47#ibcon#read 4, iclass 12, count 0 2006.285.13:21:53.47#ibcon#about to read 5, iclass 12, count 0 2006.285.13:21:53.47#ibcon#read 5, iclass 12, count 0 2006.285.13:21:53.47#ibcon#about to read 6, iclass 12, count 0 2006.285.13:21:53.47#ibcon#read 6, iclass 12, count 0 2006.285.13:21:53.47#ibcon#end of sib2, iclass 12, count 0 2006.285.13:21:53.47#ibcon#*after write, iclass 12, count 0 2006.285.13:21:53.47#ibcon#*before return 0, iclass 12, count 0 2006.285.13:21:53.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:21:53.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:21:53.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.13:21:53.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.13:21:53.47$vck44/vb=2,5 2006.285.13:21:53.47#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.13:21:53.47#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.13:21:53.47#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:53.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:21:53.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:21:53.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:21:53.53#ibcon#enter wrdev, iclass 14, count 2 2006.285.13:21:53.53#ibcon#first serial, iclass 14, count 2 2006.285.13:21:53.53#ibcon#enter sib2, iclass 14, count 2 2006.285.13:21:53.53#ibcon#flushed, iclass 14, count 2 2006.285.13:21:53.53#ibcon#about to write, iclass 14, count 2 2006.285.13:21:53.53#ibcon#wrote, iclass 14, count 2 2006.285.13:21:53.53#ibcon#about to read 3, iclass 14, count 2 2006.285.13:21:53.55#ibcon#read 3, iclass 14, count 2 2006.285.13:21:53.55#ibcon#about to read 4, iclass 14, count 2 2006.285.13:21:53.55#ibcon#read 4, iclass 14, count 2 2006.285.13:21:53.55#ibcon#about to read 5, iclass 14, count 2 2006.285.13:21:53.55#ibcon#read 5, iclass 14, count 2 2006.285.13:21:53.55#ibcon#about to read 6, iclass 14, count 2 2006.285.13:21:53.55#ibcon#read 6, iclass 14, count 2 2006.285.13:21:53.55#ibcon#end of sib2, iclass 14, count 2 2006.285.13:21:53.55#ibcon#*mode == 0, iclass 14, count 2 2006.285.13:21:53.55#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.13:21:53.55#ibcon#[27=AT02-05\r\n] 2006.285.13:21:53.55#ibcon#*before write, iclass 14, count 2 2006.285.13:21:53.55#ibcon#enter sib2, iclass 14, count 2 2006.285.13:21:53.55#ibcon#flushed, iclass 14, count 2 2006.285.13:21:53.55#ibcon#about to write, iclass 14, count 2 2006.285.13:21:53.55#ibcon#wrote, iclass 14, count 2 2006.285.13:21:53.55#ibcon#about to read 3, iclass 14, count 2 2006.285.13:21:53.58#ibcon#read 3, iclass 14, count 2 2006.285.13:21:53.58#ibcon#about to read 4, iclass 14, count 2 2006.285.13:21:53.58#ibcon#read 4, iclass 14, count 2 2006.285.13:21:53.58#ibcon#about to read 5, iclass 14, count 2 2006.285.13:21:53.58#ibcon#read 5, iclass 14, count 2 2006.285.13:21:53.58#ibcon#about to read 6, iclass 14, count 2 2006.285.13:21:53.58#ibcon#read 6, iclass 14, count 2 2006.285.13:21:53.58#ibcon#end of sib2, iclass 14, count 2 2006.285.13:21:53.58#ibcon#*after write, iclass 14, count 2 2006.285.13:21:53.58#ibcon#*before return 0, iclass 14, count 2 2006.285.13:21:53.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:21:53.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:21:53.58#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.13:21:53.58#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:53.58#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:21:53.70#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:21:53.70#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:21:53.70#ibcon#enter wrdev, iclass 14, count 0 2006.285.13:21:53.70#ibcon#first serial, iclass 14, count 0 2006.285.13:21:53.70#ibcon#enter sib2, iclass 14, count 0 2006.285.13:21:53.70#ibcon#flushed, iclass 14, count 0 2006.285.13:21:53.70#ibcon#about to write, iclass 14, count 0 2006.285.13:21:53.70#ibcon#wrote, iclass 14, count 0 2006.285.13:21:53.70#ibcon#about to read 3, iclass 14, count 0 2006.285.13:21:53.72#ibcon#read 3, iclass 14, count 0 2006.285.13:21:53.72#ibcon#about to read 4, iclass 14, count 0 2006.285.13:21:53.72#ibcon#read 4, iclass 14, count 0 2006.285.13:21:53.72#ibcon#about to read 5, iclass 14, count 0 2006.285.13:21:53.72#ibcon#read 5, iclass 14, count 0 2006.285.13:21:53.72#ibcon#about to read 6, iclass 14, count 0 2006.285.13:21:53.72#ibcon#read 6, iclass 14, count 0 2006.285.13:21:53.72#ibcon#end of sib2, iclass 14, count 0 2006.285.13:21:53.72#ibcon#*mode == 0, iclass 14, count 0 2006.285.13:21:53.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.13:21:53.72#ibcon#[27=USB\r\n] 2006.285.13:21:53.72#ibcon#*before write, iclass 14, count 0 2006.285.13:21:53.72#ibcon#enter sib2, iclass 14, count 0 2006.285.13:21:53.72#ibcon#flushed, iclass 14, count 0 2006.285.13:21:53.72#ibcon#about to write, iclass 14, count 0 2006.285.13:21:53.72#ibcon#wrote, iclass 14, count 0 2006.285.13:21:53.72#ibcon#about to read 3, iclass 14, count 0 2006.285.13:21:53.75#ibcon#read 3, iclass 14, count 0 2006.285.13:21:53.75#ibcon#about to read 4, iclass 14, count 0 2006.285.13:21:53.75#ibcon#read 4, iclass 14, count 0 2006.285.13:21:53.75#ibcon#about to read 5, iclass 14, count 0 2006.285.13:21:53.75#ibcon#read 5, iclass 14, count 0 2006.285.13:21:53.75#ibcon#about to read 6, iclass 14, count 0 2006.285.13:21:53.75#ibcon#read 6, iclass 14, count 0 2006.285.13:21:53.75#ibcon#end of sib2, iclass 14, count 0 2006.285.13:21:53.75#ibcon#*after write, iclass 14, count 0 2006.285.13:21:53.75#ibcon#*before return 0, iclass 14, count 0 2006.285.13:21:53.75#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:21:53.75#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:21:53.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.13:21:53.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.13:21:53.75$vck44/vblo=3,649.99 2006.285.13:21:53.75#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.13:21:53.75#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.13:21:53.75#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:53.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:21:53.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:21:53.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:21:53.75#ibcon#enter wrdev, iclass 16, count 0 2006.285.13:21:53.75#ibcon#first serial, iclass 16, count 0 2006.285.13:21:53.75#ibcon#enter sib2, iclass 16, count 0 2006.285.13:21:53.75#ibcon#flushed, iclass 16, count 0 2006.285.13:21:53.75#ibcon#about to write, iclass 16, count 0 2006.285.13:21:53.75#ibcon#wrote, iclass 16, count 0 2006.285.13:21:53.75#ibcon#about to read 3, iclass 16, count 0 2006.285.13:21:53.77#ibcon#read 3, iclass 16, count 0 2006.285.13:21:53.77#ibcon#about to read 4, iclass 16, count 0 2006.285.13:21:53.77#ibcon#read 4, iclass 16, count 0 2006.285.13:21:53.77#ibcon#about to read 5, iclass 16, count 0 2006.285.13:21:53.77#ibcon#read 5, iclass 16, count 0 2006.285.13:21:53.77#ibcon#about to read 6, iclass 16, count 0 2006.285.13:21:53.77#ibcon#read 6, iclass 16, count 0 2006.285.13:21:53.77#ibcon#end of sib2, iclass 16, count 0 2006.285.13:21:53.77#ibcon#*mode == 0, iclass 16, count 0 2006.285.13:21:53.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.13:21:53.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:21:53.77#ibcon#*before write, iclass 16, count 0 2006.285.13:21:53.77#ibcon#enter sib2, iclass 16, count 0 2006.285.13:21:53.77#ibcon#flushed, iclass 16, count 0 2006.285.13:21:53.77#ibcon#about to write, iclass 16, count 0 2006.285.13:21:53.77#ibcon#wrote, iclass 16, count 0 2006.285.13:21:53.77#ibcon#about to read 3, iclass 16, count 0 2006.285.13:21:53.81#ibcon#read 3, iclass 16, count 0 2006.285.13:21:53.81#ibcon#about to read 4, iclass 16, count 0 2006.285.13:21:53.81#ibcon#read 4, iclass 16, count 0 2006.285.13:21:53.81#ibcon#about to read 5, iclass 16, count 0 2006.285.13:21:53.81#ibcon#read 5, iclass 16, count 0 2006.285.13:21:53.81#ibcon#about to read 6, iclass 16, count 0 2006.285.13:21:53.81#ibcon#read 6, iclass 16, count 0 2006.285.13:21:53.81#ibcon#end of sib2, iclass 16, count 0 2006.285.13:21:53.81#ibcon#*after write, iclass 16, count 0 2006.285.13:21:53.81#ibcon#*before return 0, iclass 16, count 0 2006.285.13:21:53.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:21:53.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:21:53.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.13:21:53.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.13:21:53.81$vck44/vb=3,4 2006.285.13:21:53.81#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.13:21:53.81#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.13:21:53.81#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:53.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:21:53.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:21:53.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:21:53.87#ibcon#enter wrdev, iclass 18, count 2 2006.285.13:21:53.87#ibcon#first serial, iclass 18, count 2 2006.285.13:21:53.87#ibcon#enter sib2, iclass 18, count 2 2006.285.13:21:53.87#ibcon#flushed, iclass 18, count 2 2006.285.13:21:53.87#ibcon#about to write, iclass 18, count 2 2006.285.13:21:53.87#ibcon#wrote, iclass 18, count 2 2006.285.13:21:53.87#ibcon#about to read 3, iclass 18, count 2 2006.285.13:21:53.89#ibcon#read 3, iclass 18, count 2 2006.285.13:21:53.89#ibcon#about to read 4, iclass 18, count 2 2006.285.13:21:53.89#ibcon#read 4, iclass 18, count 2 2006.285.13:21:53.89#ibcon#about to read 5, iclass 18, count 2 2006.285.13:21:53.89#ibcon#read 5, iclass 18, count 2 2006.285.13:21:53.89#ibcon#about to read 6, iclass 18, count 2 2006.285.13:21:53.89#ibcon#read 6, iclass 18, count 2 2006.285.13:21:53.89#ibcon#end of sib2, iclass 18, count 2 2006.285.13:21:53.89#ibcon#*mode == 0, iclass 18, count 2 2006.285.13:21:53.89#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.13:21:53.89#ibcon#[27=AT03-04\r\n] 2006.285.13:21:53.89#ibcon#*before write, iclass 18, count 2 2006.285.13:21:53.89#ibcon#enter sib2, iclass 18, count 2 2006.285.13:21:53.89#ibcon#flushed, iclass 18, count 2 2006.285.13:21:53.89#ibcon#about to write, iclass 18, count 2 2006.285.13:21:53.89#ibcon#wrote, iclass 18, count 2 2006.285.13:21:53.89#ibcon#about to read 3, iclass 18, count 2 2006.285.13:21:53.92#ibcon#read 3, iclass 18, count 2 2006.285.13:21:53.92#ibcon#about to read 4, iclass 18, count 2 2006.285.13:21:53.92#ibcon#read 4, iclass 18, count 2 2006.285.13:21:53.92#ibcon#about to read 5, iclass 18, count 2 2006.285.13:21:53.92#ibcon#read 5, iclass 18, count 2 2006.285.13:21:53.92#ibcon#about to read 6, iclass 18, count 2 2006.285.13:21:53.92#ibcon#read 6, iclass 18, count 2 2006.285.13:21:53.92#ibcon#end of sib2, iclass 18, count 2 2006.285.13:21:53.92#ibcon#*after write, iclass 18, count 2 2006.285.13:21:53.92#ibcon#*before return 0, iclass 18, count 2 2006.285.13:21:53.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:21:53.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:21:53.92#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.13:21:53.92#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:53.92#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:21:54.04#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:21:54.04#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:21:54.04#ibcon#enter wrdev, iclass 18, count 0 2006.285.13:21:54.04#ibcon#first serial, iclass 18, count 0 2006.285.13:21:54.04#ibcon#enter sib2, iclass 18, count 0 2006.285.13:21:54.04#ibcon#flushed, iclass 18, count 0 2006.285.13:21:54.04#ibcon#about to write, iclass 18, count 0 2006.285.13:21:54.04#ibcon#wrote, iclass 18, count 0 2006.285.13:21:54.04#ibcon#about to read 3, iclass 18, count 0 2006.285.13:21:54.06#ibcon#read 3, iclass 18, count 0 2006.285.13:21:54.06#ibcon#about to read 4, iclass 18, count 0 2006.285.13:21:54.06#ibcon#read 4, iclass 18, count 0 2006.285.13:21:54.06#ibcon#about to read 5, iclass 18, count 0 2006.285.13:21:54.06#ibcon#read 5, iclass 18, count 0 2006.285.13:21:54.06#ibcon#about to read 6, iclass 18, count 0 2006.285.13:21:54.06#ibcon#read 6, iclass 18, count 0 2006.285.13:21:54.06#ibcon#end of sib2, iclass 18, count 0 2006.285.13:21:54.06#ibcon#*mode == 0, iclass 18, count 0 2006.285.13:21:54.06#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.13:21:54.06#ibcon#[27=USB\r\n] 2006.285.13:21:54.06#ibcon#*before write, iclass 18, count 0 2006.285.13:21:54.06#ibcon#enter sib2, iclass 18, count 0 2006.285.13:21:54.06#ibcon#flushed, iclass 18, count 0 2006.285.13:21:54.06#ibcon#about to write, iclass 18, count 0 2006.285.13:21:54.06#ibcon#wrote, iclass 18, count 0 2006.285.13:21:54.06#ibcon#about to read 3, iclass 18, count 0 2006.285.13:21:54.09#ibcon#read 3, iclass 18, count 0 2006.285.13:21:54.09#ibcon#about to read 4, iclass 18, count 0 2006.285.13:21:54.09#ibcon#read 4, iclass 18, count 0 2006.285.13:21:54.09#ibcon#about to read 5, iclass 18, count 0 2006.285.13:21:54.09#ibcon#read 5, iclass 18, count 0 2006.285.13:21:54.09#ibcon#about to read 6, iclass 18, count 0 2006.285.13:21:54.09#ibcon#read 6, iclass 18, count 0 2006.285.13:21:54.09#ibcon#end of sib2, iclass 18, count 0 2006.285.13:21:54.09#ibcon#*after write, iclass 18, count 0 2006.285.13:21:54.09#ibcon#*before return 0, iclass 18, count 0 2006.285.13:21:54.09#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:21:54.09#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:21:54.09#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.13:21:54.09#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.13:21:54.09$vck44/vblo=4,679.99 2006.285.13:21:54.09#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.13:21:54.09#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.13:21:54.09#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:54.09#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:21:54.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:21:54.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:21:54.09#ibcon#enter wrdev, iclass 20, count 0 2006.285.13:21:54.09#ibcon#first serial, iclass 20, count 0 2006.285.13:21:54.09#ibcon#enter sib2, iclass 20, count 0 2006.285.13:21:54.09#ibcon#flushed, iclass 20, count 0 2006.285.13:21:54.09#ibcon#about to write, iclass 20, count 0 2006.285.13:21:54.09#ibcon#wrote, iclass 20, count 0 2006.285.13:21:54.09#ibcon#about to read 3, iclass 20, count 0 2006.285.13:21:54.11#ibcon#read 3, iclass 20, count 0 2006.285.13:21:54.11#ibcon#about to read 4, iclass 20, count 0 2006.285.13:21:54.11#ibcon#read 4, iclass 20, count 0 2006.285.13:21:54.11#ibcon#about to read 5, iclass 20, count 0 2006.285.13:21:54.11#ibcon#read 5, iclass 20, count 0 2006.285.13:21:54.11#ibcon#about to read 6, iclass 20, count 0 2006.285.13:21:54.11#ibcon#read 6, iclass 20, count 0 2006.285.13:21:54.11#ibcon#end of sib2, iclass 20, count 0 2006.285.13:21:54.11#ibcon#*mode == 0, iclass 20, count 0 2006.285.13:21:54.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.13:21:54.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:21:54.11#ibcon#*before write, iclass 20, count 0 2006.285.13:21:54.11#ibcon#enter sib2, iclass 20, count 0 2006.285.13:21:54.11#ibcon#flushed, iclass 20, count 0 2006.285.13:21:54.11#ibcon#about to write, iclass 20, count 0 2006.285.13:21:54.11#ibcon#wrote, iclass 20, count 0 2006.285.13:21:54.11#ibcon#about to read 3, iclass 20, count 0 2006.285.13:21:54.15#ibcon#read 3, iclass 20, count 0 2006.285.13:21:54.15#ibcon#about to read 4, iclass 20, count 0 2006.285.13:21:54.15#ibcon#read 4, iclass 20, count 0 2006.285.13:21:54.15#ibcon#about to read 5, iclass 20, count 0 2006.285.13:21:54.15#ibcon#read 5, iclass 20, count 0 2006.285.13:21:54.15#ibcon#about to read 6, iclass 20, count 0 2006.285.13:21:54.15#ibcon#read 6, iclass 20, count 0 2006.285.13:21:54.15#ibcon#end of sib2, iclass 20, count 0 2006.285.13:21:54.15#ibcon#*after write, iclass 20, count 0 2006.285.13:21:54.15#ibcon#*before return 0, iclass 20, count 0 2006.285.13:21:54.15#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:21:54.15#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:21:54.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.13:21:54.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.13:21:54.15$vck44/vb=4,5 2006.285.13:21:54.15#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.13:21:54.15#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.13:21:54.15#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:54.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:21:54.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:21:54.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:21:54.21#ibcon#enter wrdev, iclass 22, count 2 2006.285.13:21:54.21#ibcon#first serial, iclass 22, count 2 2006.285.13:21:54.21#ibcon#enter sib2, iclass 22, count 2 2006.285.13:21:54.21#ibcon#flushed, iclass 22, count 2 2006.285.13:21:54.21#ibcon#about to write, iclass 22, count 2 2006.285.13:21:54.21#ibcon#wrote, iclass 22, count 2 2006.285.13:21:54.21#ibcon#about to read 3, iclass 22, count 2 2006.285.13:21:54.23#ibcon#read 3, iclass 22, count 2 2006.285.13:21:54.23#ibcon#about to read 4, iclass 22, count 2 2006.285.13:21:54.23#ibcon#read 4, iclass 22, count 2 2006.285.13:21:54.23#ibcon#about to read 5, iclass 22, count 2 2006.285.13:21:54.30#ibcon#read 5, iclass 22, count 2 2006.285.13:21:54.30#ibcon#about to read 6, iclass 22, count 2 2006.285.13:21:54.30#ibcon#read 6, iclass 22, count 2 2006.285.13:21:54.30#ibcon#end of sib2, iclass 22, count 2 2006.285.13:21:54.30#ibcon#*mode == 0, iclass 22, count 2 2006.285.13:21:54.30#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.13:21:54.30#ibcon#[27=AT04-05\r\n] 2006.285.13:21:54.30#ibcon#*before write, iclass 22, count 2 2006.285.13:21:54.30#ibcon#enter sib2, iclass 22, count 2 2006.285.13:21:54.30#ibcon#flushed, iclass 22, count 2 2006.285.13:21:54.30#ibcon#about to write, iclass 22, count 2 2006.285.13:21:54.30#ibcon#wrote, iclass 22, count 2 2006.285.13:21:54.30#ibcon#about to read 3, iclass 22, count 2 2006.285.13:21:54.33#ibcon#read 3, iclass 22, count 2 2006.285.13:21:54.33#ibcon#about to read 4, iclass 22, count 2 2006.285.13:21:54.33#ibcon#read 4, iclass 22, count 2 2006.285.13:21:54.33#ibcon#about to read 5, iclass 22, count 2 2006.285.13:21:54.33#ibcon#read 5, iclass 22, count 2 2006.285.13:21:54.33#ibcon#about to read 6, iclass 22, count 2 2006.285.13:21:54.33#ibcon#read 6, iclass 22, count 2 2006.285.13:21:54.33#ibcon#end of sib2, iclass 22, count 2 2006.285.13:21:54.33#ibcon#*after write, iclass 22, count 2 2006.285.13:21:54.33#ibcon#*before return 0, iclass 22, count 2 2006.285.13:21:54.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:21:54.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:21:54.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.13:21:54.33#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:54.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:21:54.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:21:54.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:21:54.45#ibcon#enter wrdev, iclass 22, count 0 2006.285.13:21:54.45#ibcon#first serial, iclass 22, count 0 2006.285.13:21:54.45#ibcon#enter sib2, iclass 22, count 0 2006.285.13:21:54.45#ibcon#flushed, iclass 22, count 0 2006.285.13:21:54.45#ibcon#about to write, iclass 22, count 0 2006.285.13:21:54.45#ibcon#wrote, iclass 22, count 0 2006.285.13:21:54.45#ibcon#about to read 3, iclass 22, count 0 2006.285.13:21:54.47#ibcon#read 3, iclass 22, count 0 2006.285.13:21:54.47#ibcon#about to read 4, iclass 22, count 0 2006.285.13:21:54.47#ibcon#read 4, iclass 22, count 0 2006.285.13:21:54.47#ibcon#about to read 5, iclass 22, count 0 2006.285.13:21:54.47#ibcon#read 5, iclass 22, count 0 2006.285.13:21:54.47#ibcon#about to read 6, iclass 22, count 0 2006.285.13:21:54.47#ibcon#read 6, iclass 22, count 0 2006.285.13:21:54.47#ibcon#end of sib2, iclass 22, count 0 2006.285.13:21:54.47#ibcon#*mode == 0, iclass 22, count 0 2006.285.13:21:54.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.13:21:54.47#ibcon#[27=USB\r\n] 2006.285.13:21:54.47#ibcon#*before write, iclass 22, count 0 2006.285.13:21:54.47#ibcon#enter sib2, iclass 22, count 0 2006.285.13:21:54.47#ibcon#flushed, iclass 22, count 0 2006.285.13:21:54.47#ibcon#about to write, iclass 22, count 0 2006.285.13:21:54.47#ibcon#wrote, iclass 22, count 0 2006.285.13:21:54.47#ibcon#about to read 3, iclass 22, count 0 2006.285.13:21:54.50#ibcon#read 3, iclass 22, count 0 2006.285.13:21:54.50#ibcon#about to read 4, iclass 22, count 0 2006.285.13:21:54.50#ibcon#read 4, iclass 22, count 0 2006.285.13:21:54.50#ibcon#about to read 5, iclass 22, count 0 2006.285.13:21:54.50#ibcon#read 5, iclass 22, count 0 2006.285.13:21:54.50#ibcon#about to read 6, iclass 22, count 0 2006.285.13:21:54.50#ibcon#read 6, iclass 22, count 0 2006.285.13:21:54.50#ibcon#end of sib2, iclass 22, count 0 2006.285.13:21:54.50#ibcon#*after write, iclass 22, count 0 2006.285.13:21:54.50#ibcon#*before return 0, iclass 22, count 0 2006.285.13:21:54.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:21:54.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:21:54.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.13:21:54.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.13:21:54.50$vck44/vblo=5,709.99 2006.285.13:21:54.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.13:21:54.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.13:21:54.50#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:54.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:21:54.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:21:54.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:21:54.50#ibcon#enter wrdev, iclass 24, count 0 2006.285.13:21:54.50#ibcon#first serial, iclass 24, count 0 2006.285.13:21:54.50#ibcon#enter sib2, iclass 24, count 0 2006.285.13:21:54.50#ibcon#flushed, iclass 24, count 0 2006.285.13:21:54.50#ibcon#about to write, iclass 24, count 0 2006.285.13:21:54.50#ibcon#wrote, iclass 24, count 0 2006.285.13:21:54.50#ibcon#about to read 3, iclass 24, count 0 2006.285.13:21:54.52#ibcon#read 3, iclass 24, count 0 2006.285.13:21:54.52#ibcon#about to read 4, iclass 24, count 0 2006.285.13:21:54.52#ibcon#read 4, iclass 24, count 0 2006.285.13:21:54.52#ibcon#about to read 5, iclass 24, count 0 2006.285.13:21:54.52#ibcon#read 5, iclass 24, count 0 2006.285.13:21:54.52#ibcon#about to read 6, iclass 24, count 0 2006.285.13:21:54.52#ibcon#read 6, iclass 24, count 0 2006.285.13:21:54.52#ibcon#end of sib2, iclass 24, count 0 2006.285.13:21:54.52#ibcon#*mode == 0, iclass 24, count 0 2006.285.13:21:54.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.13:21:54.52#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:21:54.52#ibcon#*before write, iclass 24, count 0 2006.285.13:21:54.52#ibcon#enter sib2, iclass 24, count 0 2006.285.13:21:54.52#ibcon#flushed, iclass 24, count 0 2006.285.13:21:54.52#ibcon#about to write, iclass 24, count 0 2006.285.13:21:54.52#ibcon#wrote, iclass 24, count 0 2006.285.13:21:54.52#ibcon#about to read 3, iclass 24, count 0 2006.285.13:21:54.56#ibcon#read 3, iclass 24, count 0 2006.285.13:21:54.56#ibcon#about to read 4, iclass 24, count 0 2006.285.13:21:54.56#ibcon#read 4, iclass 24, count 0 2006.285.13:21:54.56#ibcon#about to read 5, iclass 24, count 0 2006.285.13:21:54.56#ibcon#read 5, iclass 24, count 0 2006.285.13:21:54.56#ibcon#about to read 6, iclass 24, count 0 2006.285.13:21:54.56#ibcon#read 6, iclass 24, count 0 2006.285.13:21:54.56#ibcon#end of sib2, iclass 24, count 0 2006.285.13:21:54.56#ibcon#*after write, iclass 24, count 0 2006.285.13:21:54.56#ibcon#*before return 0, iclass 24, count 0 2006.285.13:21:54.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:21:54.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:21:54.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.13:21:54.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.13:21:54.56$vck44/vb=5,4 2006.285.13:21:54.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.13:21:54.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.13:21:54.56#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:54.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:21:54.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:21:54.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:21:54.62#ibcon#enter wrdev, iclass 26, count 2 2006.285.13:21:54.62#ibcon#first serial, iclass 26, count 2 2006.285.13:21:54.62#ibcon#enter sib2, iclass 26, count 2 2006.285.13:21:54.62#ibcon#flushed, iclass 26, count 2 2006.285.13:21:54.62#ibcon#about to write, iclass 26, count 2 2006.285.13:21:54.62#ibcon#wrote, iclass 26, count 2 2006.285.13:21:54.62#ibcon#about to read 3, iclass 26, count 2 2006.285.13:21:54.64#ibcon#read 3, iclass 26, count 2 2006.285.13:21:54.64#ibcon#about to read 4, iclass 26, count 2 2006.285.13:21:54.64#ibcon#read 4, iclass 26, count 2 2006.285.13:21:54.64#ibcon#about to read 5, iclass 26, count 2 2006.285.13:21:54.64#ibcon#read 5, iclass 26, count 2 2006.285.13:21:54.64#ibcon#about to read 6, iclass 26, count 2 2006.285.13:21:54.64#ibcon#read 6, iclass 26, count 2 2006.285.13:21:54.64#ibcon#end of sib2, iclass 26, count 2 2006.285.13:21:54.64#ibcon#*mode == 0, iclass 26, count 2 2006.285.13:21:54.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.13:21:54.64#ibcon#[27=AT05-04\r\n] 2006.285.13:21:54.64#ibcon#*before write, iclass 26, count 2 2006.285.13:21:54.64#ibcon#enter sib2, iclass 26, count 2 2006.285.13:21:54.64#ibcon#flushed, iclass 26, count 2 2006.285.13:21:54.64#ibcon#about to write, iclass 26, count 2 2006.285.13:21:54.64#ibcon#wrote, iclass 26, count 2 2006.285.13:21:54.64#ibcon#about to read 3, iclass 26, count 2 2006.285.13:21:54.67#ibcon#read 3, iclass 26, count 2 2006.285.13:21:54.67#ibcon#about to read 4, iclass 26, count 2 2006.285.13:21:54.67#ibcon#read 4, iclass 26, count 2 2006.285.13:21:54.67#ibcon#about to read 5, iclass 26, count 2 2006.285.13:21:54.67#ibcon#read 5, iclass 26, count 2 2006.285.13:21:54.67#ibcon#about to read 6, iclass 26, count 2 2006.285.13:21:54.67#ibcon#read 6, iclass 26, count 2 2006.285.13:21:54.67#ibcon#end of sib2, iclass 26, count 2 2006.285.13:21:54.67#ibcon#*after write, iclass 26, count 2 2006.285.13:21:54.67#ibcon#*before return 0, iclass 26, count 2 2006.285.13:21:54.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:21:54.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:21:54.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.13:21:54.67#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:54.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:21:54.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:21:54.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:21:54.79#ibcon#enter wrdev, iclass 26, count 0 2006.285.13:21:54.79#ibcon#first serial, iclass 26, count 0 2006.285.13:21:54.79#ibcon#enter sib2, iclass 26, count 0 2006.285.13:21:54.79#ibcon#flushed, iclass 26, count 0 2006.285.13:21:54.79#ibcon#about to write, iclass 26, count 0 2006.285.13:21:54.79#ibcon#wrote, iclass 26, count 0 2006.285.13:21:54.79#ibcon#about to read 3, iclass 26, count 0 2006.285.13:21:54.81#ibcon#read 3, iclass 26, count 0 2006.285.13:21:54.81#ibcon#about to read 4, iclass 26, count 0 2006.285.13:21:54.81#ibcon#read 4, iclass 26, count 0 2006.285.13:21:54.81#ibcon#about to read 5, iclass 26, count 0 2006.285.13:21:54.81#ibcon#read 5, iclass 26, count 0 2006.285.13:21:54.81#ibcon#about to read 6, iclass 26, count 0 2006.285.13:21:54.81#ibcon#read 6, iclass 26, count 0 2006.285.13:21:54.81#ibcon#end of sib2, iclass 26, count 0 2006.285.13:21:54.81#ibcon#*mode == 0, iclass 26, count 0 2006.285.13:21:54.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.13:21:54.81#ibcon#[27=USB\r\n] 2006.285.13:21:54.81#ibcon#*before write, iclass 26, count 0 2006.285.13:21:54.81#ibcon#enter sib2, iclass 26, count 0 2006.285.13:21:54.81#ibcon#flushed, iclass 26, count 0 2006.285.13:21:54.81#ibcon#about to write, iclass 26, count 0 2006.285.13:21:54.81#ibcon#wrote, iclass 26, count 0 2006.285.13:21:54.81#ibcon#about to read 3, iclass 26, count 0 2006.285.13:21:54.84#ibcon#read 3, iclass 26, count 0 2006.285.13:21:54.84#ibcon#about to read 4, iclass 26, count 0 2006.285.13:21:54.84#ibcon#read 4, iclass 26, count 0 2006.285.13:21:54.84#ibcon#about to read 5, iclass 26, count 0 2006.285.13:21:54.84#ibcon#read 5, iclass 26, count 0 2006.285.13:21:54.84#ibcon#about to read 6, iclass 26, count 0 2006.285.13:21:54.84#ibcon#read 6, iclass 26, count 0 2006.285.13:21:54.84#ibcon#end of sib2, iclass 26, count 0 2006.285.13:21:54.84#ibcon#*after write, iclass 26, count 0 2006.285.13:21:54.84#ibcon#*before return 0, iclass 26, count 0 2006.285.13:21:54.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:21:54.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:21:54.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.13:21:54.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.13:21:54.84$vck44/vblo=6,719.99 2006.285.13:21:54.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.13:21:54.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.13:21:54.84#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:54.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:21:54.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:21:54.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:21:54.84#ibcon#enter wrdev, iclass 28, count 0 2006.285.13:21:54.84#ibcon#first serial, iclass 28, count 0 2006.285.13:21:54.84#ibcon#enter sib2, iclass 28, count 0 2006.285.13:21:54.84#ibcon#flushed, iclass 28, count 0 2006.285.13:21:54.84#ibcon#about to write, iclass 28, count 0 2006.285.13:21:54.84#ibcon#wrote, iclass 28, count 0 2006.285.13:21:54.84#ibcon#about to read 3, iclass 28, count 0 2006.285.13:21:54.86#ibcon#read 3, iclass 28, count 0 2006.285.13:21:54.86#ibcon#about to read 4, iclass 28, count 0 2006.285.13:21:54.86#ibcon#read 4, iclass 28, count 0 2006.285.13:21:54.86#ibcon#about to read 5, iclass 28, count 0 2006.285.13:21:54.86#ibcon#read 5, iclass 28, count 0 2006.285.13:21:54.86#ibcon#about to read 6, iclass 28, count 0 2006.285.13:21:54.86#ibcon#read 6, iclass 28, count 0 2006.285.13:21:54.86#ibcon#end of sib2, iclass 28, count 0 2006.285.13:21:54.86#ibcon#*mode == 0, iclass 28, count 0 2006.285.13:21:54.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.13:21:54.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:21:54.86#ibcon#*before write, iclass 28, count 0 2006.285.13:21:54.86#ibcon#enter sib2, iclass 28, count 0 2006.285.13:21:54.86#ibcon#flushed, iclass 28, count 0 2006.285.13:21:54.86#ibcon#about to write, iclass 28, count 0 2006.285.13:21:54.86#ibcon#wrote, iclass 28, count 0 2006.285.13:21:54.86#ibcon#about to read 3, iclass 28, count 0 2006.285.13:21:54.90#ibcon#read 3, iclass 28, count 0 2006.285.13:21:54.90#ibcon#about to read 4, iclass 28, count 0 2006.285.13:21:54.90#ibcon#read 4, iclass 28, count 0 2006.285.13:21:54.90#ibcon#about to read 5, iclass 28, count 0 2006.285.13:21:54.90#ibcon#read 5, iclass 28, count 0 2006.285.13:21:54.90#ibcon#about to read 6, iclass 28, count 0 2006.285.13:21:54.90#ibcon#read 6, iclass 28, count 0 2006.285.13:21:54.90#ibcon#end of sib2, iclass 28, count 0 2006.285.13:21:54.90#ibcon#*after write, iclass 28, count 0 2006.285.13:21:54.90#ibcon#*before return 0, iclass 28, count 0 2006.285.13:21:54.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:21:54.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:21:54.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.13:21:54.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.13:21:54.90$vck44/vb=6,3 2006.285.13:21:54.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.13:21:54.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.13:21:54.90#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:54.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:21:54.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:21:54.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:21:54.96#ibcon#enter wrdev, iclass 30, count 2 2006.285.13:21:54.96#ibcon#first serial, iclass 30, count 2 2006.285.13:21:54.96#ibcon#enter sib2, iclass 30, count 2 2006.285.13:21:54.96#ibcon#flushed, iclass 30, count 2 2006.285.13:21:54.96#ibcon#about to write, iclass 30, count 2 2006.285.13:21:54.96#ibcon#wrote, iclass 30, count 2 2006.285.13:21:54.96#ibcon#about to read 3, iclass 30, count 2 2006.285.13:21:54.98#ibcon#read 3, iclass 30, count 2 2006.285.13:21:54.98#ibcon#about to read 4, iclass 30, count 2 2006.285.13:21:54.98#ibcon#read 4, iclass 30, count 2 2006.285.13:21:54.98#ibcon#about to read 5, iclass 30, count 2 2006.285.13:21:54.98#ibcon#read 5, iclass 30, count 2 2006.285.13:21:54.98#ibcon#about to read 6, iclass 30, count 2 2006.285.13:21:54.98#ibcon#read 6, iclass 30, count 2 2006.285.13:21:54.98#ibcon#end of sib2, iclass 30, count 2 2006.285.13:21:54.98#ibcon#*mode == 0, iclass 30, count 2 2006.285.13:21:54.98#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.13:21:54.98#ibcon#[27=AT06-03\r\n] 2006.285.13:21:54.98#ibcon#*before write, iclass 30, count 2 2006.285.13:21:54.98#ibcon#enter sib2, iclass 30, count 2 2006.285.13:21:54.98#ibcon#flushed, iclass 30, count 2 2006.285.13:21:54.98#ibcon#about to write, iclass 30, count 2 2006.285.13:21:54.98#ibcon#wrote, iclass 30, count 2 2006.285.13:21:54.98#ibcon#about to read 3, iclass 30, count 2 2006.285.13:21:55.01#ibcon#read 3, iclass 30, count 2 2006.285.13:21:55.01#ibcon#about to read 4, iclass 30, count 2 2006.285.13:21:55.01#ibcon#read 4, iclass 30, count 2 2006.285.13:21:55.01#ibcon#about to read 5, iclass 30, count 2 2006.285.13:21:55.01#ibcon#read 5, iclass 30, count 2 2006.285.13:21:55.01#ibcon#about to read 6, iclass 30, count 2 2006.285.13:21:55.01#ibcon#read 6, iclass 30, count 2 2006.285.13:21:55.01#ibcon#end of sib2, iclass 30, count 2 2006.285.13:21:55.01#ibcon#*after write, iclass 30, count 2 2006.285.13:21:55.01#ibcon#*before return 0, iclass 30, count 2 2006.285.13:21:55.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:21:55.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:21:55.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.13:21:55.01#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:55.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:21:55.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:21:55.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:21:55.13#ibcon#enter wrdev, iclass 30, count 0 2006.285.13:21:55.13#ibcon#first serial, iclass 30, count 0 2006.285.13:21:55.13#ibcon#enter sib2, iclass 30, count 0 2006.285.13:21:55.13#ibcon#flushed, iclass 30, count 0 2006.285.13:21:55.13#ibcon#about to write, iclass 30, count 0 2006.285.13:21:55.13#ibcon#wrote, iclass 30, count 0 2006.285.13:21:55.13#ibcon#about to read 3, iclass 30, count 0 2006.285.13:21:55.15#ibcon#read 3, iclass 30, count 0 2006.285.13:21:55.15#ibcon#about to read 4, iclass 30, count 0 2006.285.13:21:55.15#ibcon#read 4, iclass 30, count 0 2006.285.13:21:55.15#ibcon#about to read 5, iclass 30, count 0 2006.285.13:21:55.15#ibcon#read 5, iclass 30, count 0 2006.285.13:21:55.15#ibcon#about to read 6, iclass 30, count 0 2006.285.13:21:55.15#ibcon#read 6, iclass 30, count 0 2006.285.13:21:55.15#ibcon#end of sib2, iclass 30, count 0 2006.285.13:21:55.15#ibcon#*mode == 0, iclass 30, count 0 2006.285.13:21:55.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.13:21:55.15#ibcon#[27=USB\r\n] 2006.285.13:21:55.15#ibcon#*before write, iclass 30, count 0 2006.285.13:21:55.15#ibcon#enter sib2, iclass 30, count 0 2006.285.13:21:55.15#ibcon#flushed, iclass 30, count 0 2006.285.13:21:55.15#ibcon#about to write, iclass 30, count 0 2006.285.13:21:55.15#ibcon#wrote, iclass 30, count 0 2006.285.13:21:55.15#ibcon#about to read 3, iclass 30, count 0 2006.285.13:21:55.18#ibcon#read 3, iclass 30, count 0 2006.285.13:21:55.18#ibcon#about to read 4, iclass 30, count 0 2006.285.13:21:55.18#ibcon#read 4, iclass 30, count 0 2006.285.13:21:55.18#ibcon#about to read 5, iclass 30, count 0 2006.285.13:21:55.18#ibcon#read 5, iclass 30, count 0 2006.285.13:21:55.18#ibcon#about to read 6, iclass 30, count 0 2006.285.13:21:55.18#ibcon#read 6, iclass 30, count 0 2006.285.13:21:55.18#ibcon#end of sib2, iclass 30, count 0 2006.285.13:21:55.18#ibcon#*after write, iclass 30, count 0 2006.285.13:21:55.18#ibcon#*before return 0, iclass 30, count 0 2006.285.13:21:55.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:21:55.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:21:55.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.13:21:55.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.13:21:55.18$vck44/vblo=7,734.99 2006.285.13:21:55.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.13:21:55.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.13:21:55.18#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:55.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:21:55.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:21:55.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:21:55.18#ibcon#enter wrdev, iclass 32, count 0 2006.285.13:21:55.18#ibcon#first serial, iclass 32, count 0 2006.285.13:21:55.18#ibcon#enter sib2, iclass 32, count 0 2006.285.13:21:55.18#ibcon#flushed, iclass 32, count 0 2006.285.13:21:55.18#ibcon#about to write, iclass 32, count 0 2006.285.13:21:55.18#ibcon#wrote, iclass 32, count 0 2006.285.13:21:55.18#ibcon#about to read 3, iclass 32, count 0 2006.285.13:21:55.20#ibcon#read 3, iclass 32, count 0 2006.285.13:21:55.38#ibcon#about to read 4, iclass 32, count 0 2006.285.13:21:55.38#ibcon#read 4, iclass 32, count 0 2006.285.13:21:55.38#ibcon#about to read 5, iclass 32, count 0 2006.285.13:21:55.38#ibcon#read 5, iclass 32, count 0 2006.285.13:21:55.38#ibcon#about to read 6, iclass 32, count 0 2006.285.13:21:55.38#ibcon#read 6, iclass 32, count 0 2006.285.13:21:55.38#ibcon#end of sib2, iclass 32, count 0 2006.285.13:21:55.38#ibcon#*mode == 0, iclass 32, count 0 2006.285.13:21:55.38#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.13:21:55.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:21:55.38#ibcon#*before write, iclass 32, count 0 2006.285.13:21:55.38#ibcon#enter sib2, iclass 32, count 0 2006.285.13:21:55.38#ibcon#flushed, iclass 32, count 0 2006.285.13:21:55.38#ibcon#about to write, iclass 32, count 0 2006.285.13:21:55.38#ibcon#wrote, iclass 32, count 0 2006.285.13:21:55.38#ibcon#about to read 3, iclass 32, count 0 2006.285.13:21:55.42#ibcon#read 3, iclass 32, count 0 2006.285.13:21:55.42#ibcon#about to read 4, iclass 32, count 0 2006.285.13:21:55.42#ibcon#read 4, iclass 32, count 0 2006.285.13:21:55.42#ibcon#about to read 5, iclass 32, count 0 2006.285.13:21:55.42#ibcon#read 5, iclass 32, count 0 2006.285.13:21:55.42#ibcon#about to read 6, iclass 32, count 0 2006.285.13:21:55.42#ibcon#read 6, iclass 32, count 0 2006.285.13:21:55.42#ibcon#end of sib2, iclass 32, count 0 2006.285.13:21:55.42#ibcon#*after write, iclass 32, count 0 2006.285.13:21:55.42#ibcon#*before return 0, iclass 32, count 0 2006.285.13:21:55.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:21:55.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:21:55.42#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.13:21:55.42#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.13:21:55.42$vck44/vb=7,4 2006.285.13:21:55.42#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.13:21:55.42#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.13:21:55.42#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:55.42#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:21:55.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:21:55.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:21:55.42#ibcon#enter wrdev, iclass 34, count 2 2006.285.13:21:55.42#ibcon#first serial, iclass 34, count 2 2006.285.13:21:55.42#ibcon#enter sib2, iclass 34, count 2 2006.285.13:21:55.42#ibcon#flushed, iclass 34, count 2 2006.285.13:21:55.42#ibcon#about to write, iclass 34, count 2 2006.285.13:21:55.42#ibcon#wrote, iclass 34, count 2 2006.285.13:21:55.42#ibcon#about to read 3, iclass 34, count 2 2006.285.13:21:55.44#ibcon#read 3, iclass 34, count 2 2006.285.13:21:55.44#ibcon#about to read 4, iclass 34, count 2 2006.285.13:21:55.44#ibcon#read 4, iclass 34, count 2 2006.285.13:21:55.44#ibcon#about to read 5, iclass 34, count 2 2006.285.13:21:55.44#ibcon#read 5, iclass 34, count 2 2006.285.13:21:55.44#ibcon#about to read 6, iclass 34, count 2 2006.285.13:21:55.44#ibcon#read 6, iclass 34, count 2 2006.285.13:21:55.44#ibcon#end of sib2, iclass 34, count 2 2006.285.13:21:55.44#ibcon#*mode == 0, iclass 34, count 2 2006.285.13:21:55.44#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.13:21:55.44#ibcon#[27=AT07-04\r\n] 2006.285.13:21:55.44#ibcon#*before write, iclass 34, count 2 2006.285.13:21:55.44#ibcon#enter sib2, iclass 34, count 2 2006.285.13:21:55.44#ibcon#flushed, iclass 34, count 2 2006.285.13:21:55.44#ibcon#about to write, iclass 34, count 2 2006.285.13:21:55.44#ibcon#wrote, iclass 34, count 2 2006.285.13:21:55.44#ibcon#about to read 3, iclass 34, count 2 2006.285.13:21:55.47#ibcon#read 3, iclass 34, count 2 2006.285.13:21:55.47#ibcon#about to read 4, iclass 34, count 2 2006.285.13:21:55.47#ibcon#read 4, iclass 34, count 2 2006.285.13:21:55.47#ibcon#about to read 5, iclass 34, count 2 2006.285.13:21:55.47#ibcon#read 5, iclass 34, count 2 2006.285.13:21:55.47#ibcon#about to read 6, iclass 34, count 2 2006.285.13:21:55.47#ibcon#read 6, iclass 34, count 2 2006.285.13:21:55.47#ibcon#end of sib2, iclass 34, count 2 2006.285.13:21:55.47#ibcon#*after write, iclass 34, count 2 2006.285.13:21:55.47#ibcon#*before return 0, iclass 34, count 2 2006.285.13:21:55.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:21:55.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:21:55.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.13:21:55.47#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:55.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:21:55.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:21:55.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:21:55.59#ibcon#enter wrdev, iclass 34, count 0 2006.285.13:21:55.59#ibcon#first serial, iclass 34, count 0 2006.285.13:21:55.59#ibcon#enter sib2, iclass 34, count 0 2006.285.13:21:55.59#ibcon#flushed, iclass 34, count 0 2006.285.13:21:55.59#ibcon#about to write, iclass 34, count 0 2006.285.13:21:55.59#ibcon#wrote, iclass 34, count 0 2006.285.13:21:55.59#ibcon#about to read 3, iclass 34, count 0 2006.285.13:21:55.61#ibcon#read 3, iclass 34, count 0 2006.285.13:21:55.61#ibcon#about to read 4, iclass 34, count 0 2006.285.13:21:55.61#ibcon#read 4, iclass 34, count 0 2006.285.13:21:55.61#ibcon#about to read 5, iclass 34, count 0 2006.285.13:21:55.61#ibcon#read 5, iclass 34, count 0 2006.285.13:21:55.61#ibcon#about to read 6, iclass 34, count 0 2006.285.13:21:55.61#ibcon#read 6, iclass 34, count 0 2006.285.13:21:55.61#ibcon#end of sib2, iclass 34, count 0 2006.285.13:21:55.61#ibcon#*mode == 0, iclass 34, count 0 2006.285.13:21:55.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.13:21:55.61#ibcon#[27=USB\r\n] 2006.285.13:21:55.61#ibcon#*before write, iclass 34, count 0 2006.285.13:21:55.61#ibcon#enter sib2, iclass 34, count 0 2006.285.13:21:55.61#ibcon#flushed, iclass 34, count 0 2006.285.13:21:55.61#ibcon#about to write, iclass 34, count 0 2006.285.13:21:55.61#ibcon#wrote, iclass 34, count 0 2006.285.13:21:55.61#ibcon#about to read 3, iclass 34, count 0 2006.285.13:21:55.64#ibcon#read 3, iclass 34, count 0 2006.285.13:21:55.64#ibcon#about to read 4, iclass 34, count 0 2006.285.13:21:55.64#ibcon#read 4, iclass 34, count 0 2006.285.13:21:55.64#ibcon#about to read 5, iclass 34, count 0 2006.285.13:21:55.64#ibcon#read 5, iclass 34, count 0 2006.285.13:21:55.64#ibcon#about to read 6, iclass 34, count 0 2006.285.13:21:55.64#ibcon#read 6, iclass 34, count 0 2006.285.13:21:55.64#ibcon#end of sib2, iclass 34, count 0 2006.285.13:21:55.64#ibcon#*after write, iclass 34, count 0 2006.285.13:21:55.64#ibcon#*before return 0, iclass 34, count 0 2006.285.13:21:55.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:21:55.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:21:55.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.13:21:55.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.13:21:55.64$vck44/vblo=8,744.99 2006.285.13:21:55.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.13:21:55.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.13:21:55.64#ibcon#ireg 17 cls_cnt 0 2006.285.13:21:55.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:21:55.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:21:55.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:21:55.64#ibcon#enter wrdev, iclass 36, count 0 2006.285.13:21:55.64#ibcon#first serial, iclass 36, count 0 2006.285.13:21:55.64#ibcon#enter sib2, iclass 36, count 0 2006.285.13:21:55.64#ibcon#flushed, iclass 36, count 0 2006.285.13:21:55.64#ibcon#about to write, iclass 36, count 0 2006.285.13:21:55.64#ibcon#wrote, iclass 36, count 0 2006.285.13:21:55.64#ibcon#about to read 3, iclass 36, count 0 2006.285.13:21:55.66#ibcon#read 3, iclass 36, count 0 2006.285.13:21:55.66#ibcon#about to read 4, iclass 36, count 0 2006.285.13:21:55.66#ibcon#read 4, iclass 36, count 0 2006.285.13:21:55.66#ibcon#about to read 5, iclass 36, count 0 2006.285.13:21:55.66#ibcon#read 5, iclass 36, count 0 2006.285.13:21:55.66#ibcon#about to read 6, iclass 36, count 0 2006.285.13:21:55.66#ibcon#read 6, iclass 36, count 0 2006.285.13:21:55.66#ibcon#end of sib2, iclass 36, count 0 2006.285.13:21:55.66#ibcon#*mode == 0, iclass 36, count 0 2006.285.13:21:55.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.13:21:55.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:21:55.66#ibcon#*before write, iclass 36, count 0 2006.285.13:21:55.66#ibcon#enter sib2, iclass 36, count 0 2006.285.13:21:55.66#ibcon#flushed, iclass 36, count 0 2006.285.13:21:55.66#ibcon#about to write, iclass 36, count 0 2006.285.13:21:55.66#ibcon#wrote, iclass 36, count 0 2006.285.13:21:55.66#ibcon#about to read 3, iclass 36, count 0 2006.285.13:21:55.70#ibcon#read 3, iclass 36, count 0 2006.285.13:21:55.70#ibcon#about to read 4, iclass 36, count 0 2006.285.13:21:55.70#ibcon#read 4, iclass 36, count 0 2006.285.13:21:55.70#ibcon#about to read 5, iclass 36, count 0 2006.285.13:21:55.70#ibcon#read 5, iclass 36, count 0 2006.285.13:21:55.70#ibcon#about to read 6, iclass 36, count 0 2006.285.13:21:55.70#ibcon#read 6, iclass 36, count 0 2006.285.13:21:55.70#ibcon#end of sib2, iclass 36, count 0 2006.285.13:21:55.70#ibcon#*after write, iclass 36, count 0 2006.285.13:21:55.70#ibcon#*before return 0, iclass 36, count 0 2006.285.13:21:55.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:21:55.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:21:55.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.13:21:55.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.13:21:55.70$vck44/vb=8,4 2006.285.13:21:55.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.13:21:55.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.13:21:55.70#ibcon#ireg 11 cls_cnt 2 2006.285.13:21:55.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:21:55.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:21:55.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:21:55.76#ibcon#enter wrdev, iclass 38, count 2 2006.285.13:21:55.76#ibcon#first serial, iclass 38, count 2 2006.285.13:21:55.76#ibcon#enter sib2, iclass 38, count 2 2006.285.13:21:55.76#ibcon#flushed, iclass 38, count 2 2006.285.13:21:55.76#ibcon#about to write, iclass 38, count 2 2006.285.13:21:55.76#ibcon#wrote, iclass 38, count 2 2006.285.13:21:55.76#ibcon#about to read 3, iclass 38, count 2 2006.285.13:21:55.78#ibcon#read 3, iclass 38, count 2 2006.285.13:21:55.78#ibcon#about to read 4, iclass 38, count 2 2006.285.13:21:55.78#ibcon#read 4, iclass 38, count 2 2006.285.13:21:55.78#ibcon#about to read 5, iclass 38, count 2 2006.285.13:21:55.78#ibcon#read 5, iclass 38, count 2 2006.285.13:21:55.78#ibcon#about to read 6, iclass 38, count 2 2006.285.13:21:55.78#ibcon#read 6, iclass 38, count 2 2006.285.13:21:55.78#ibcon#end of sib2, iclass 38, count 2 2006.285.13:21:55.78#ibcon#*mode == 0, iclass 38, count 2 2006.285.13:21:55.78#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.13:21:55.78#ibcon#[27=AT08-04\r\n] 2006.285.13:21:55.78#ibcon#*before write, iclass 38, count 2 2006.285.13:21:55.78#ibcon#enter sib2, iclass 38, count 2 2006.285.13:21:55.78#ibcon#flushed, iclass 38, count 2 2006.285.13:21:55.78#ibcon#about to write, iclass 38, count 2 2006.285.13:21:55.78#ibcon#wrote, iclass 38, count 2 2006.285.13:21:55.78#ibcon#about to read 3, iclass 38, count 2 2006.285.13:21:55.81#ibcon#read 3, iclass 38, count 2 2006.285.13:21:55.81#ibcon#about to read 4, iclass 38, count 2 2006.285.13:21:55.81#ibcon#read 4, iclass 38, count 2 2006.285.13:21:55.81#ibcon#about to read 5, iclass 38, count 2 2006.285.13:21:55.81#ibcon#read 5, iclass 38, count 2 2006.285.13:21:55.81#ibcon#about to read 6, iclass 38, count 2 2006.285.13:21:55.81#ibcon#read 6, iclass 38, count 2 2006.285.13:21:55.81#ibcon#end of sib2, iclass 38, count 2 2006.285.13:21:55.81#ibcon#*after write, iclass 38, count 2 2006.285.13:21:55.81#ibcon#*before return 0, iclass 38, count 2 2006.285.13:21:55.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:21:55.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:21:55.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.13:21:55.81#ibcon#ireg 7 cls_cnt 0 2006.285.13:21:55.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:21:55.93#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:21:55.93#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:21:55.93#ibcon#enter wrdev, iclass 38, count 0 2006.285.13:21:55.93#ibcon#first serial, iclass 38, count 0 2006.285.13:21:55.93#ibcon#enter sib2, iclass 38, count 0 2006.285.13:21:55.93#ibcon#flushed, iclass 38, count 0 2006.285.13:21:55.93#ibcon#about to write, iclass 38, count 0 2006.285.13:21:55.93#ibcon#wrote, iclass 38, count 0 2006.285.13:21:55.93#ibcon#about to read 3, iclass 38, count 0 2006.285.13:21:55.95#ibcon#read 3, iclass 38, count 0 2006.285.13:21:55.95#ibcon#about to read 4, iclass 38, count 0 2006.285.13:21:55.95#ibcon#read 4, iclass 38, count 0 2006.285.13:21:55.95#ibcon#about to read 5, iclass 38, count 0 2006.285.13:21:55.95#ibcon#read 5, iclass 38, count 0 2006.285.13:21:55.95#ibcon#about to read 6, iclass 38, count 0 2006.285.13:21:55.95#ibcon#read 6, iclass 38, count 0 2006.285.13:21:55.95#ibcon#end of sib2, iclass 38, count 0 2006.285.13:21:55.95#ibcon#*mode == 0, iclass 38, count 0 2006.285.13:21:55.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.13:21:55.95#ibcon#[27=USB\r\n] 2006.285.13:21:55.95#ibcon#*before write, iclass 38, count 0 2006.285.13:21:55.95#ibcon#enter sib2, iclass 38, count 0 2006.285.13:21:55.95#ibcon#flushed, iclass 38, count 0 2006.285.13:21:55.95#ibcon#about to write, iclass 38, count 0 2006.285.13:21:55.95#ibcon#wrote, iclass 38, count 0 2006.285.13:21:55.95#ibcon#about to read 3, iclass 38, count 0 2006.285.13:21:55.98#ibcon#read 3, iclass 38, count 0 2006.285.13:21:55.98#ibcon#about to read 4, iclass 38, count 0 2006.285.13:21:55.98#ibcon#read 4, iclass 38, count 0 2006.285.13:21:55.98#ibcon#about to read 5, iclass 38, count 0 2006.285.13:21:55.98#ibcon#read 5, iclass 38, count 0 2006.285.13:21:55.98#ibcon#about to read 6, iclass 38, count 0 2006.285.13:21:55.98#ibcon#read 6, iclass 38, count 0 2006.285.13:21:55.98#ibcon#end of sib2, iclass 38, count 0 2006.285.13:21:55.98#ibcon#*after write, iclass 38, count 0 2006.285.13:21:55.98#ibcon#*before return 0, iclass 38, count 0 2006.285.13:21:55.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:21:55.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:21:55.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.13:21:55.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.13:21:55.98$vck44/vabw=wide 2006.285.13:21:55.98#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.13:21:55.98#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.13:21:55.98#ibcon#ireg 8 cls_cnt 0 2006.285.13:21:55.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:21:55.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:21:55.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:21:55.98#ibcon#enter wrdev, iclass 40, count 0 2006.285.13:21:55.98#ibcon#first serial, iclass 40, count 0 2006.285.13:21:55.98#ibcon#enter sib2, iclass 40, count 0 2006.285.13:21:55.98#ibcon#flushed, iclass 40, count 0 2006.285.13:21:55.98#ibcon#about to write, iclass 40, count 0 2006.285.13:21:55.98#ibcon#wrote, iclass 40, count 0 2006.285.13:21:55.98#ibcon#about to read 3, iclass 40, count 0 2006.285.13:21:56.00#ibcon#read 3, iclass 40, count 0 2006.285.13:21:56.00#ibcon#about to read 4, iclass 40, count 0 2006.285.13:21:56.00#ibcon#read 4, iclass 40, count 0 2006.285.13:21:56.00#ibcon#about to read 5, iclass 40, count 0 2006.285.13:21:56.00#ibcon#read 5, iclass 40, count 0 2006.285.13:21:56.00#ibcon#about to read 6, iclass 40, count 0 2006.285.13:21:56.00#ibcon#read 6, iclass 40, count 0 2006.285.13:21:56.00#ibcon#end of sib2, iclass 40, count 0 2006.285.13:21:56.00#ibcon#*mode == 0, iclass 40, count 0 2006.285.13:21:56.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.13:21:56.00#ibcon#[25=BW32\r\n] 2006.285.13:21:56.00#ibcon#*before write, iclass 40, count 0 2006.285.13:21:56.00#ibcon#enter sib2, iclass 40, count 0 2006.285.13:21:56.00#ibcon#flushed, iclass 40, count 0 2006.285.13:21:56.00#ibcon#about to write, iclass 40, count 0 2006.285.13:21:56.00#ibcon#wrote, iclass 40, count 0 2006.285.13:21:56.00#ibcon#about to read 3, iclass 40, count 0 2006.285.13:21:56.03#ibcon#read 3, iclass 40, count 0 2006.285.13:21:56.03#ibcon#about to read 4, iclass 40, count 0 2006.285.13:21:56.03#ibcon#read 4, iclass 40, count 0 2006.285.13:21:56.03#ibcon#about to read 5, iclass 40, count 0 2006.285.13:21:56.03#ibcon#read 5, iclass 40, count 0 2006.285.13:21:56.03#ibcon#about to read 6, iclass 40, count 0 2006.285.13:21:56.03#ibcon#read 6, iclass 40, count 0 2006.285.13:21:56.03#ibcon#end of sib2, iclass 40, count 0 2006.285.13:21:56.03#ibcon#*after write, iclass 40, count 0 2006.285.13:21:56.03#ibcon#*before return 0, iclass 40, count 0 2006.285.13:21:56.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:21:56.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:21:56.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.13:21:56.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.13:21:56.03$vck44/vbbw=wide 2006.285.13:21:56.03#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.13:21:56.03#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.13:21:56.03#ibcon#ireg 8 cls_cnt 0 2006.285.13:21:56.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:21:56.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:21:56.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:21:56.10#ibcon#enter wrdev, iclass 4, count 0 2006.285.13:21:56.10#ibcon#first serial, iclass 4, count 0 2006.285.13:21:56.10#ibcon#enter sib2, iclass 4, count 0 2006.285.13:21:56.10#ibcon#flushed, iclass 4, count 0 2006.285.13:21:56.10#ibcon#about to write, iclass 4, count 0 2006.285.13:21:56.10#ibcon#wrote, iclass 4, count 0 2006.285.13:21:56.10#ibcon#about to read 3, iclass 4, count 0 2006.285.13:21:56.12#ibcon#read 3, iclass 4, count 0 2006.285.13:21:56.12#ibcon#about to read 4, iclass 4, count 0 2006.285.13:21:56.12#ibcon#read 4, iclass 4, count 0 2006.285.13:21:56.12#ibcon#about to read 5, iclass 4, count 0 2006.285.13:21:56.12#ibcon#read 5, iclass 4, count 0 2006.285.13:21:56.12#ibcon#about to read 6, iclass 4, count 0 2006.285.13:21:56.12#ibcon#read 6, iclass 4, count 0 2006.285.13:21:56.12#ibcon#end of sib2, iclass 4, count 0 2006.285.13:21:56.12#ibcon#*mode == 0, iclass 4, count 0 2006.285.13:21:56.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.13:21:56.12#ibcon#[27=BW32\r\n] 2006.285.13:21:56.12#ibcon#*before write, iclass 4, count 0 2006.285.13:21:56.12#ibcon#enter sib2, iclass 4, count 0 2006.285.13:21:56.12#ibcon#flushed, iclass 4, count 0 2006.285.13:21:56.12#ibcon#about to write, iclass 4, count 0 2006.285.13:21:56.12#ibcon#wrote, iclass 4, count 0 2006.285.13:21:56.12#ibcon#about to read 3, iclass 4, count 0 2006.285.13:21:56.15#ibcon#read 3, iclass 4, count 0 2006.285.13:21:56.15#ibcon#about to read 4, iclass 4, count 0 2006.285.13:21:56.15#ibcon#read 4, iclass 4, count 0 2006.285.13:21:56.15#ibcon#about to read 5, iclass 4, count 0 2006.285.13:21:56.15#ibcon#read 5, iclass 4, count 0 2006.285.13:21:56.15#ibcon#about to read 6, iclass 4, count 0 2006.285.13:21:56.15#ibcon#read 6, iclass 4, count 0 2006.285.13:21:56.15#ibcon#end of sib2, iclass 4, count 0 2006.285.13:21:56.15#ibcon#*after write, iclass 4, count 0 2006.285.13:21:56.15#ibcon#*before return 0, iclass 4, count 0 2006.285.13:21:56.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:21:56.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:21:56.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.13:21:56.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.13:21:56.15$setupk4/ifdk4 2006.285.13:21:56.15$ifdk4/lo= 2006.285.13:21:56.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:21:56.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:21:56.15$ifdk4/patch= 2006.285.13:21:56.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:21:56.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:21:56.15$setupk4/!*+20s 2006.285.13:21:59.78#abcon#<5=/04 1.5 2.5 19.06 971015.3\r\n> 2006.285.13:21:59.80#abcon#{5=INTERFACE CLEAR} 2006.285.13:21:59.86#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:22:09.92$setupk4/"tpicd 2006.285.13:22:09.92$setupk4/echo=off 2006.285.13:22:09.92$setupk4/xlog=off 2006.285.13:22:09.92:!2006.285.13:24:08 2006.285.13:22:09.95#abcon#<5=/04 1.5 2.5 19.06 971015.3\r\n> 2006.285.13:22:14.14#trakl#Source acquired 2006.285.13:22:14.14#flagr#flagr/antenna,acquired 2006.285.13:24:08.00:preob 2006.285.13:24:09.14/onsource/TRACKING 2006.285.13:24:09.14:!2006.285.13:24:18 2006.285.13:24:18.00:"tape 2006.285.13:24:18.00:"st=record 2006.285.13:24:18.00:data_valid=on 2006.285.13:24:18.00:midob 2006.285.13:24:18.14/onsource/TRACKING 2006.285.13:24:18.14/wx/19.08,1015.3,97 2006.285.13:24:18.27/cable/+6.4970E-03 2006.285.13:24:19.36/va/01,07,usb,yes,50,54 2006.285.13:24:19.36/va/02,06,usb,yes,50,51 2006.285.13:24:19.36/va/03,07,usb,yes,50,52 2006.285.13:24:19.36/va/04,06,usb,yes,52,55 2006.285.13:24:19.36/va/05,03,usb,yes,51,52 2006.285.13:24:19.36/va/06,04,usb,yes,47,46 2006.285.13:24:19.36/va/07,04,usb,yes,47,48 2006.285.13:24:19.36/va/08,03,usb,yes,48,57 2006.285.13:24:19.59/valo/01,524.99,yes,locked 2006.285.13:24:19.59/valo/02,534.99,yes,locked 2006.285.13:24:19.59/valo/03,564.99,yes,locked 2006.285.13:24:19.59/valo/04,624.99,yes,locked 2006.285.13:24:19.59/valo/05,734.99,yes,locked 2006.285.13:24:19.59/valo/06,814.99,yes,locked 2006.285.13:24:19.59/valo/07,864.99,yes,locked 2006.285.13:24:19.59/valo/08,884.99,yes,locked 2006.285.13:24:20.68/vb/01,04,usb,yes,44,41 2006.285.13:24:20.68/vb/02,05,usb,yes,42,41 2006.285.13:24:20.68/vb/03,04,usb,yes,43,47 2006.285.13:24:20.68/vb/04,05,usb,yes,43,42 2006.285.13:24:20.68/vb/05,04,usb,yes,39,42 2006.285.13:24:20.68/vb/06,03,usb,yes,55,49 2006.285.13:24:20.68/vb/07,04,usb,yes,44,45 2006.285.13:24:20.68/vb/08,04,usb,yes,40,45 2006.285.13:24:20.91/vblo/01,629.99,yes,locked 2006.285.13:24:20.91/vblo/02,634.99,yes,locked 2006.285.13:24:20.91/vblo/03,649.99,yes,locked 2006.285.13:24:20.91/vblo/04,679.99,yes,locked 2006.285.13:24:20.91/vblo/05,709.99,yes,locked 2006.285.13:24:20.91/vblo/06,719.99,yes,locked 2006.285.13:24:20.91/vblo/07,734.99,yes,locked 2006.285.13:24:20.91/vblo/08,744.99,yes,locked 2006.285.13:24:21.06/vabw/8 2006.285.13:24:21.21/vbbw/8 2006.285.13:24:21.30/xfe/off,on,12.2 2006.285.13:24:21.67/ifatt/23,28,28,28 2006.285.13:24:22.08/fmout-gps/S +2.72E-07 2006.285.13:24:22.11:!2006.285.13:24:58 2006.285.13:24:58.01:data_valid=off 2006.285.13:24:58.01:"et 2006.285.13:24:58.01:!+3s 2006.285.13:25:01.02:"tape 2006.285.13:25:01.02:postob 2006.285.13:25:01.19/cable/+6.4985E-03 2006.285.13:25:01.19/wx/19.09,1015.3,97 2006.285.13:25:02.08/fmout-gps/S +2.71E-07 2006.285.13:25:02.08:scan_name=285-1327,jd0610,160 2006.285.13:25:02.08:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.285.13:25:03.14#flagr#flagr/antenna,new-source 2006.285.13:25:03.14:checkk5 2006.285.13:25:03.89/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:25:04.44/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:25:04.86/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:25:05.34/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:25:05.94/chk_obsdata//k5ts1/T2851324??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.13:25:06.71/chk_obsdata//k5ts2/T2851324??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.13:25:07.09/chk_obsdata//k5ts3/T2851324??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.13:25:07.50/chk_obsdata//k5ts4/T2851324??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.13:25:08.33/k5log//k5ts1_log_newline 2006.285.13:25:09.20/k5log//k5ts2_log_newline 2006.285.13:25:09.90/k5log//k5ts3_log_newline 2006.285.13:25:10.66/k5log//k5ts4_log_newline 2006.285.13:25:10.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:25:10.68:setupk4=1 2006.285.13:25:10.68$setupk4/echo=on 2006.285.13:25:10.68$setupk4/pcalon 2006.285.13:25:10.68$pcalon/"no phase cal control is implemented here 2006.285.13:25:10.68$setupk4/"tpicd=stop 2006.285.13:25:10.68$setupk4/"rec=synch_on 2006.285.13:25:10.68$setupk4/"rec_mode=128 2006.285.13:25:10.68$setupk4/!* 2006.285.13:25:10.68$setupk4/recpk4 2006.285.13:25:10.68$recpk4/recpatch= 2006.285.13:25:10.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:25:10.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:25:10.68$setupk4/vck44 2006.285.13:25:10.68$vck44/valo=1,524.99 2006.285.13:25:10.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.13:25:10.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.13:25:10.68#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:10.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:25:10.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:25:10.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:25:10.68#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:25:10.68#ibcon#first serial, iclass 15, count 0 2006.285.13:25:10.68#ibcon#enter sib2, iclass 15, count 0 2006.285.13:25:10.68#ibcon#flushed, iclass 15, count 0 2006.285.13:25:10.68#ibcon#about to write, iclass 15, count 0 2006.285.13:25:10.68#ibcon#wrote, iclass 15, count 0 2006.285.13:25:10.68#ibcon#about to read 3, iclass 15, count 0 2006.285.13:25:10.70#ibcon#read 3, iclass 15, count 0 2006.285.13:25:10.70#ibcon#about to read 4, iclass 15, count 0 2006.285.13:25:10.70#ibcon#read 4, iclass 15, count 0 2006.285.13:25:10.70#ibcon#about to read 5, iclass 15, count 0 2006.285.13:25:10.70#ibcon#read 5, iclass 15, count 0 2006.285.13:25:10.70#ibcon#about to read 6, iclass 15, count 0 2006.285.13:25:10.70#ibcon#read 6, iclass 15, count 0 2006.285.13:25:10.70#ibcon#end of sib2, iclass 15, count 0 2006.285.13:25:10.70#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:25:10.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:25:10.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:25:10.70#ibcon#*before write, iclass 15, count 0 2006.285.13:25:10.70#ibcon#enter sib2, iclass 15, count 0 2006.285.13:25:10.70#ibcon#flushed, iclass 15, count 0 2006.285.13:25:10.70#ibcon#about to write, iclass 15, count 0 2006.285.13:25:10.70#ibcon#wrote, iclass 15, count 0 2006.285.13:25:10.70#ibcon#about to read 3, iclass 15, count 0 2006.285.13:25:10.75#ibcon#read 3, iclass 15, count 0 2006.285.13:25:10.75#ibcon#about to read 4, iclass 15, count 0 2006.285.13:25:10.75#ibcon#read 4, iclass 15, count 0 2006.285.13:25:10.75#ibcon#about to read 5, iclass 15, count 0 2006.285.13:25:10.75#ibcon#read 5, iclass 15, count 0 2006.285.13:25:10.75#ibcon#about to read 6, iclass 15, count 0 2006.285.13:25:10.75#ibcon#read 6, iclass 15, count 0 2006.285.13:25:10.75#ibcon#end of sib2, iclass 15, count 0 2006.285.13:25:10.75#ibcon#*after write, iclass 15, count 0 2006.285.13:25:10.75#ibcon#*before return 0, iclass 15, count 0 2006.285.13:25:10.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:25:10.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:25:10.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:25:10.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:25:10.75$vck44/va=1,7 2006.285.13:25:10.75#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.13:25:10.75#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.13:25:10.75#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:10.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:25:10.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:25:10.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:25:10.75#ibcon#enter wrdev, iclass 17, count 2 2006.285.13:25:10.75#ibcon#first serial, iclass 17, count 2 2006.285.13:25:10.75#ibcon#enter sib2, iclass 17, count 2 2006.285.13:25:10.75#ibcon#flushed, iclass 17, count 2 2006.285.13:25:10.75#ibcon#about to write, iclass 17, count 2 2006.285.13:25:10.75#ibcon#wrote, iclass 17, count 2 2006.285.13:25:10.75#ibcon#about to read 3, iclass 17, count 2 2006.285.13:25:10.77#ibcon#read 3, iclass 17, count 2 2006.285.13:25:10.77#ibcon#about to read 4, iclass 17, count 2 2006.285.13:25:10.77#ibcon#read 4, iclass 17, count 2 2006.285.13:25:10.77#ibcon#about to read 5, iclass 17, count 2 2006.285.13:25:10.77#ibcon#read 5, iclass 17, count 2 2006.285.13:25:10.77#ibcon#about to read 6, iclass 17, count 2 2006.285.13:25:10.77#ibcon#read 6, iclass 17, count 2 2006.285.13:25:10.77#ibcon#end of sib2, iclass 17, count 2 2006.285.13:25:10.77#ibcon#*mode == 0, iclass 17, count 2 2006.285.13:25:10.77#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.13:25:10.77#ibcon#[25=AT01-07\r\n] 2006.285.13:25:10.77#ibcon#*before write, iclass 17, count 2 2006.285.13:25:10.77#ibcon#enter sib2, iclass 17, count 2 2006.285.13:25:10.77#ibcon#flushed, iclass 17, count 2 2006.285.13:25:10.77#ibcon#about to write, iclass 17, count 2 2006.285.13:25:10.77#ibcon#wrote, iclass 17, count 2 2006.285.13:25:10.77#ibcon#about to read 3, iclass 17, count 2 2006.285.13:25:10.80#ibcon#read 3, iclass 17, count 2 2006.285.13:25:10.80#ibcon#about to read 4, iclass 17, count 2 2006.285.13:25:10.80#ibcon#read 4, iclass 17, count 2 2006.285.13:25:10.80#ibcon#about to read 5, iclass 17, count 2 2006.285.13:25:10.80#ibcon#read 5, iclass 17, count 2 2006.285.13:25:10.80#ibcon#about to read 6, iclass 17, count 2 2006.285.13:25:10.80#ibcon#read 6, iclass 17, count 2 2006.285.13:25:10.80#ibcon#end of sib2, iclass 17, count 2 2006.285.13:25:10.80#ibcon#*after write, iclass 17, count 2 2006.285.13:25:10.80#ibcon#*before return 0, iclass 17, count 2 2006.285.13:25:10.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:25:10.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:25:10.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.13:25:10.80#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:10.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:25:10.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:25:10.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:25:10.92#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:25:10.92#ibcon#first serial, iclass 17, count 0 2006.285.13:25:10.92#ibcon#enter sib2, iclass 17, count 0 2006.285.13:25:10.92#ibcon#flushed, iclass 17, count 0 2006.285.13:25:10.92#ibcon#about to write, iclass 17, count 0 2006.285.13:25:10.92#ibcon#wrote, iclass 17, count 0 2006.285.13:25:10.92#ibcon#about to read 3, iclass 17, count 0 2006.285.13:25:10.94#ibcon#read 3, iclass 17, count 0 2006.285.13:25:10.94#ibcon#about to read 4, iclass 17, count 0 2006.285.13:25:10.94#ibcon#read 4, iclass 17, count 0 2006.285.13:25:10.94#ibcon#about to read 5, iclass 17, count 0 2006.285.13:25:10.94#ibcon#read 5, iclass 17, count 0 2006.285.13:25:10.94#ibcon#about to read 6, iclass 17, count 0 2006.285.13:25:10.94#ibcon#read 6, iclass 17, count 0 2006.285.13:25:10.94#ibcon#end of sib2, iclass 17, count 0 2006.285.13:25:10.94#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:25:10.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:25:10.94#ibcon#[25=USB\r\n] 2006.285.13:25:10.94#ibcon#*before write, iclass 17, count 0 2006.285.13:25:10.94#ibcon#enter sib2, iclass 17, count 0 2006.285.13:25:10.94#ibcon#flushed, iclass 17, count 0 2006.285.13:25:10.94#ibcon#about to write, iclass 17, count 0 2006.285.13:25:10.94#ibcon#wrote, iclass 17, count 0 2006.285.13:25:10.94#ibcon#about to read 3, iclass 17, count 0 2006.285.13:25:10.97#ibcon#read 3, iclass 17, count 0 2006.285.13:25:10.97#ibcon#about to read 4, iclass 17, count 0 2006.285.13:25:10.97#ibcon#read 4, iclass 17, count 0 2006.285.13:25:10.97#ibcon#about to read 5, iclass 17, count 0 2006.285.13:25:10.97#ibcon#read 5, iclass 17, count 0 2006.285.13:25:10.97#ibcon#about to read 6, iclass 17, count 0 2006.285.13:25:10.97#ibcon#read 6, iclass 17, count 0 2006.285.13:25:10.97#ibcon#end of sib2, iclass 17, count 0 2006.285.13:25:10.97#ibcon#*after write, iclass 17, count 0 2006.285.13:25:10.97#ibcon#*before return 0, iclass 17, count 0 2006.285.13:25:10.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:25:10.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:25:10.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:25:10.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:25:10.97$vck44/valo=2,534.99 2006.285.13:25:10.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.13:25:10.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.13:25:10.97#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:10.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:25:10.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:25:10.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:25:10.97#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:25:10.97#ibcon#first serial, iclass 19, count 0 2006.285.13:25:10.97#ibcon#enter sib2, iclass 19, count 0 2006.285.13:25:10.97#ibcon#flushed, iclass 19, count 0 2006.285.13:25:10.97#ibcon#about to write, iclass 19, count 0 2006.285.13:25:10.97#ibcon#wrote, iclass 19, count 0 2006.285.13:25:10.97#ibcon#about to read 3, iclass 19, count 0 2006.285.13:25:10.99#ibcon#read 3, iclass 19, count 0 2006.285.13:25:10.99#ibcon#about to read 4, iclass 19, count 0 2006.285.13:25:10.99#ibcon#read 4, iclass 19, count 0 2006.285.13:25:10.99#ibcon#about to read 5, iclass 19, count 0 2006.285.13:25:10.99#ibcon#read 5, iclass 19, count 0 2006.285.13:25:10.99#ibcon#about to read 6, iclass 19, count 0 2006.285.13:25:10.99#ibcon#read 6, iclass 19, count 0 2006.285.13:25:10.99#ibcon#end of sib2, iclass 19, count 0 2006.285.13:25:10.99#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:25:10.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:25:10.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:25:10.99#ibcon#*before write, iclass 19, count 0 2006.285.13:25:10.99#ibcon#enter sib2, iclass 19, count 0 2006.285.13:25:10.99#ibcon#flushed, iclass 19, count 0 2006.285.13:25:10.99#ibcon#about to write, iclass 19, count 0 2006.285.13:25:10.99#ibcon#wrote, iclass 19, count 0 2006.285.13:25:10.99#ibcon#about to read 3, iclass 19, count 0 2006.285.13:25:11.03#ibcon#read 3, iclass 19, count 0 2006.285.13:25:11.03#ibcon#about to read 4, iclass 19, count 0 2006.285.13:25:11.03#ibcon#read 4, iclass 19, count 0 2006.285.13:25:11.03#ibcon#about to read 5, iclass 19, count 0 2006.285.13:25:11.03#ibcon#read 5, iclass 19, count 0 2006.285.13:25:11.03#ibcon#about to read 6, iclass 19, count 0 2006.285.13:25:11.03#ibcon#read 6, iclass 19, count 0 2006.285.13:25:11.03#ibcon#end of sib2, iclass 19, count 0 2006.285.13:25:11.03#ibcon#*after write, iclass 19, count 0 2006.285.13:25:11.03#ibcon#*before return 0, iclass 19, count 0 2006.285.13:25:11.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:25:11.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:25:11.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:25:11.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:25:11.03$vck44/va=2,6 2006.285.13:25:11.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.13:25:11.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.13:25:11.03#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:11.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:25:11.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:25:11.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:25:11.09#ibcon#enter wrdev, iclass 21, count 2 2006.285.13:25:11.09#ibcon#first serial, iclass 21, count 2 2006.285.13:25:11.09#ibcon#enter sib2, iclass 21, count 2 2006.285.13:25:11.09#ibcon#flushed, iclass 21, count 2 2006.285.13:25:11.09#ibcon#about to write, iclass 21, count 2 2006.285.13:25:11.09#ibcon#wrote, iclass 21, count 2 2006.285.13:25:11.09#ibcon#about to read 3, iclass 21, count 2 2006.285.13:25:11.11#ibcon#read 3, iclass 21, count 2 2006.285.13:25:11.11#ibcon#about to read 4, iclass 21, count 2 2006.285.13:25:11.11#ibcon#read 4, iclass 21, count 2 2006.285.13:25:11.11#ibcon#about to read 5, iclass 21, count 2 2006.285.13:25:11.11#ibcon#read 5, iclass 21, count 2 2006.285.13:25:11.11#ibcon#about to read 6, iclass 21, count 2 2006.285.13:25:11.11#ibcon#read 6, iclass 21, count 2 2006.285.13:25:11.11#ibcon#end of sib2, iclass 21, count 2 2006.285.13:25:11.11#ibcon#*mode == 0, iclass 21, count 2 2006.285.13:25:11.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.13:25:11.11#ibcon#[25=AT02-06\r\n] 2006.285.13:25:11.11#ibcon#*before write, iclass 21, count 2 2006.285.13:25:11.11#ibcon#enter sib2, iclass 21, count 2 2006.285.13:25:11.11#ibcon#flushed, iclass 21, count 2 2006.285.13:25:11.11#ibcon#about to write, iclass 21, count 2 2006.285.13:25:11.11#ibcon#wrote, iclass 21, count 2 2006.285.13:25:11.11#ibcon#about to read 3, iclass 21, count 2 2006.285.13:25:11.14#ibcon#read 3, iclass 21, count 2 2006.285.13:25:11.14#ibcon#about to read 4, iclass 21, count 2 2006.285.13:25:11.14#ibcon#read 4, iclass 21, count 2 2006.285.13:25:11.14#ibcon#about to read 5, iclass 21, count 2 2006.285.13:25:11.14#ibcon#read 5, iclass 21, count 2 2006.285.13:25:11.14#ibcon#about to read 6, iclass 21, count 2 2006.285.13:25:11.14#ibcon#read 6, iclass 21, count 2 2006.285.13:25:11.14#ibcon#end of sib2, iclass 21, count 2 2006.285.13:25:11.14#ibcon#*after write, iclass 21, count 2 2006.285.13:25:11.14#ibcon#*before return 0, iclass 21, count 2 2006.285.13:25:11.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:25:11.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:25:11.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.13:25:11.14#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:11.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:25:11.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:25:11.60#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:25:11.60#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:25:11.60#ibcon#first serial, iclass 21, count 0 2006.285.13:25:11.60#ibcon#enter sib2, iclass 21, count 0 2006.285.13:25:11.60#ibcon#flushed, iclass 21, count 0 2006.285.13:25:11.60#ibcon#about to write, iclass 21, count 0 2006.285.13:25:11.60#ibcon#wrote, iclass 21, count 0 2006.285.13:25:11.60#ibcon#about to read 3, iclass 21, count 0 2006.285.13:25:11.61#ibcon#read 3, iclass 21, count 0 2006.285.13:25:11.61#ibcon#about to read 4, iclass 21, count 0 2006.285.13:25:11.61#ibcon#read 4, iclass 21, count 0 2006.285.13:25:11.61#ibcon#about to read 5, iclass 21, count 0 2006.285.13:25:11.61#ibcon#read 5, iclass 21, count 0 2006.285.13:25:11.61#ibcon#about to read 6, iclass 21, count 0 2006.285.13:25:11.61#ibcon#read 6, iclass 21, count 0 2006.285.13:25:11.61#ibcon#end of sib2, iclass 21, count 0 2006.285.13:25:11.61#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:25:11.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:25:11.61#ibcon#[25=USB\r\n] 2006.285.13:25:11.61#ibcon#*before write, iclass 21, count 0 2006.285.13:25:11.61#ibcon#enter sib2, iclass 21, count 0 2006.285.13:25:11.61#ibcon#flushed, iclass 21, count 0 2006.285.13:25:11.61#ibcon#about to write, iclass 21, count 0 2006.285.13:25:11.61#ibcon#wrote, iclass 21, count 0 2006.285.13:25:11.61#ibcon#about to read 3, iclass 21, count 0 2006.285.13:25:11.64#ibcon#read 3, iclass 21, count 0 2006.285.13:25:11.64#ibcon#about to read 4, iclass 21, count 0 2006.285.13:25:11.64#ibcon#read 4, iclass 21, count 0 2006.285.13:25:11.64#ibcon#about to read 5, iclass 21, count 0 2006.285.13:25:11.64#ibcon#read 5, iclass 21, count 0 2006.285.13:25:11.64#ibcon#about to read 6, iclass 21, count 0 2006.285.13:25:11.64#ibcon#read 6, iclass 21, count 0 2006.285.13:25:11.64#ibcon#end of sib2, iclass 21, count 0 2006.285.13:25:11.64#ibcon#*after write, iclass 21, count 0 2006.285.13:25:11.64#ibcon#*before return 0, iclass 21, count 0 2006.285.13:25:11.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:25:11.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:25:11.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:25:11.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:25:11.64$vck44/valo=3,564.99 2006.285.13:25:11.64#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.13:25:11.64#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.13:25:11.64#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:11.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:25:11.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:25:11.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:25:11.64#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:25:11.64#ibcon#first serial, iclass 23, count 0 2006.285.13:25:11.64#ibcon#enter sib2, iclass 23, count 0 2006.285.13:25:11.64#ibcon#flushed, iclass 23, count 0 2006.285.13:25:11.64#ibcon#about to write, iclass 23, count 0 2006.285.13:25:11.64#ibcon#wrote, iclass 23, count 0 2006.285.13:25:11.64#ibcon#about to read 3, iclass 23, count 0 2006.285.13:25:11.66#ibcon#read 3, iclass 23, count 0 2006.285.13:25:11.66#ibcon#about to read 4, iclass 23, count 0 2006.285.13:25:11.66#ibcon#read 4, iclass 23, count 0 2006.285.13:25:11.66#ibcon#about to read 5, iclass 23, count 0 2006.285.13:25:11.66#ibcon#read 5, iclass 23, count 0 2006.285.13:25:11.66#ibcon#about to read 6, iclass 23, count 0 2006.285.13:25:11.66#ibcon#read 6, iclass 23, count 0 2006.285.13:25:11.66#ibcon#end of sib2, iclass 23, count 0 2006.285.13:25:11.66#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:25:11.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:25:11.66#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:25:11.66#ibcon#*before write, iclass 23, count 0 2006.285.13:25:11.66#ibcon#enter sib2, iclass 23, count 0 2006.285.13:25:11.66#ibcon#flushed, iclass 23, count 0 2006.285.13:25:11.66#ibcon#about to write, iclass 23, count 0 2006.285.13:25:11.66#ibcon#wrote, iclass 23, count 0 2006.285.13:25:11.66#ibcon#about to read 3, iclass 23, count 0 2006.285.13:25:11.70#ibcon#read 3, iclass 23, count 0 2006.285.13:25:11.70#ibcon#about to read 4, iclass 23, count 0 2006.285.13:25:11.70#ibcon#read 4, iclass 23, count 0 2006.285.13:25:11.70#ibcon#about to read 5, iclass 23, count 0 2006.285.13:25:11.70#ibcon#read 5, iclass 23, count 0 2006.285.13:25:11.70#ibcon#about to read 6, iclass 23, count 0 2006.285.13:25:11.70#ibcon#read 6, iclass 23, count 0 2006.285.13:25:11.70#ibcon#end of sib2, iclass 23, count 0 2006.285.13:25:11.70#ibcon#*after write, iclass 23, count 0 2006.285.13:25:11.70#ibcon#*before return 0, iclass 23, count 0 2006.285.13:25:11.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:25:11.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:25:11.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:25:11.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:25:11.70$vck44/va=3,7 2006.285.13:25:11.70#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.13:25:11.70#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.13:25:11.70#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:11.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:25:11.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:25:11.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:25:11.76#ibcon#enter wrdev, iclass 25, count 2 2006.285.13:25:11.76#ibcon#first serial, iclass 25, count 2 2006.285.13:25:11.76#ibcon#enter sib2, iclass 25, count 2 2006.285.13:25:11.76#ibcon#flushed, iclass 25, count 2 2006.285.13:25:11.76#ibcon#about to write, iclass 25, count 2 2006.285.13:25:11.76#ibcon#wrote, iclass 25, count 2 2006.285.13:25:11.76#ibcon#about to read 3, iclass 25, count 2 2006.285.13:25:11.78#ibcon#read 3, iclass 25, count 2 2006.285.13:25:11.78#ibcon#about to read 4, iclass 25, count 2 2006.285.13:25:11.78#ibcon#read 4, iclass 25, count 2 2006.285.13:25:11.78#ibcon#about to read 5, iclass 25, count 2 2006.285.13:25:11.78#ibcon#read 5, iclass 25, count 2 2006.285.13:25:11.78#ibcon#about to read 6, iclass 25, count 2 2006.285.13:25:11.78#ibcon#read 6, iclass 25, count 2 2006.285.13:25:11.78#ibcon#end of sib2, iclass 25, count 2 2006.285.13:25:11.78#ibcon#*mode == 0, iclass 25, count 2 2006.285.13:25:11.78#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.13:25:11.78#ibcon#[25=AT03-07\r\n] 2006.285.13:25:11.78#ibcon#*before write, iclass 25, count 2 2006.285.13:25:11.78#ibcon#enter sib2, iclass 25, count 2 2006.285.13:25:11.78#ibcon#flushed, iclass 25, count 2 2006.285.13:25:11.78#ibcon#about to write, iclass 25, count 2 2006.285.13:25:11.78#ibcon#wrote, iclass 25, count 2 2006.285.13:25:11.78#ibcon#about to read 3, iclass 25, count 2 2006.285.13:25:11.81#ibcon#read 3, iclass 25, count 2 2006.285.13:25:11.81#ibcon#about to read 4, iclass 25, count 2 2006.285.13:25:11.81#ibcon#read 4, iclass 25, count 2 2006.285.13:25:11.81#ibcon#about to read 5, iclass 25, count 2 2006.285.13:25:11.81#ibcon#read 5, iclass 25, count 2 2006.285.13:25:11.81#ibcon#about to read 6, iclass 25, count 2 2006.285.13:25:11.81#ibcon#read 6, iclass 25, count 2 2006.285.13:25:11.81#ibcon#end of sib2, iclass 25, count 2 2006.285.13:25:11.81#ibcon#*after write, iclass 25, count 2 2006.285.13:25:11.81#ibcon#*before return 0, iclass 25, count 2 2006.285.13:25:11.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:25:11.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:25:11.81#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.13:25:11.81#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:11.81#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:25:11.93#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:25:11.93#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:25:11.93#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:25:11.93#ibcon#first serial, iclass 25, count 0 2006.285.13:25:11.93#ibcon#enter sib2, iclass 25, count 0 2006.285.13:25:11.93#ibcon#flushed, iclass 25, count 0 2006.285.13:25:11.93#ibcon#about to write, iclass 25, count 0 2006.285.13:25:11.93#ibcon#wrote, iclass 25, count 0 2006.285.13:25:11.93#ibcon#about to read 3, iclass 25, count 0 2006.285.13:25:11.95#ibcon#read 3, iclass 25, count 0 2006.285.13:25:11.97#ibcon#about to read 4, iclass 25, count 0 2006.285.13:25:11.97#ibcon#read 4, iclass 25, count 0 2006.285.13:25:11.97#ibcon#about to read 5, iclass 25, count 0 2006.285.13:25:11.97#ibcon#read 5, iclass 25, count 0 2006.285.13:25:11.97#ibcon#about to read 6, iclass 25, count 0 2006.285.13:25:11.97#ibcon#read 6, iclass 25, count 0 2006.285.13:25:11.97#ibcon#end of sib2, iclass 25, count 0 2006.285.13:25:11.97#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:25:11.97#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:25:11.97#ibcon#[25=USB\r\n] 2006.285.13:25:11.97#ibcon#*before write, iclass 25, count 0 2006.285.13:25:11.97#ibcon#enter sib2, iclass 25, count 0 2006.285.13:25:11.97#ibcon#flushed, iclass 25, count 0 2006.285.13:25:11.97#ibcon#about to write, iclass 25, count 0 2006.285.13:25:11.97#ibcon#wrote, iclass 25, count 0 2006.285.13:25:11.97#ibcon#about to read 3, iclass 25, count 0 2006.285.13:25:12.00#ibcon#read 3, iclass 25, count 0 2006.285.13:25:12.00#ibcon#about to read 4, iclass 25, count 0 2006.285.13:25:12.00#ibcon#read 4, iclass 25, count 0 2006.285.13:25:12.00#ibcon#about to read 5, iclass 25, count 0 2006.285.13:25:12.00#ibcon#read 5, iclass 25, count 0 2006.285.13:25:12.00#ibcon#about to read 6, iclass 25, count 0 2006.285.13:25:12.00#ibcon#read 6, iclass 25, count 0 2006.285.13:25:12.00#ibcon#end of sib2, iclass 25, count 0 2006.285.13:25:12.00#ibcon#*after write, iclass 25, count 0 2006.285.13:25:12.00#ibcon#*before return 0, iclass 25, count 0 2006.285.13:25:12.00#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:25:12.00#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:25:12.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:25:12.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:25:12.00$vck44/valo=4,624.99 2006.285.13:25:12.00#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.13:25:12.00#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.13:25:12.00#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:12.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:25:12.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:25:12.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:25:12.00#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:25:12.00#ibcon#first serial, iclass 27, count 0 2006.285.13:25:12.00#ibcon#enter sib2, iclass 27, count 0 2006.285.13:25:12.00#ibcon#flushed, iclass 27, count 0 2006.285.13:25:12.00#ibcon#about to write, iclass 27, count 0 2006.285.13:25:12.00#ibcon#wrote, iclass 27, count 0 2006.285.13:25:12.00#ibcon#about to read 3, iclass 27, count 0 2006.285.13:25:12.02#ibcon#read 3, iclass 27, count 0 2006.285.13:25:12.02#ibcon#about to read 4, iclass 27, count 0 2006.285.13:25:12.02#ibcon#read 4, iclass 27, count 0 2006.285.13:25:12.02#ibcon#about to read 5, iclass 27, count 0 2006.285.13:25:12.02#ibcon#read 5, iclass 27, count 0 2006.285.13:25:12.02#ibcon#about to read 6, iclass 27, count 0 2006.285.13:25:12.02#ibcon#read 6, iclass 27, count 0 2006.285.13:25:12.02#ibcon#end of sib2, iclass 27, count 0 2006.285.13:25:12.02#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:25:12.02#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:25:12.02#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:25:12.02#ibcon#*before write, iclass 27, count 0 2006.285.13:25:12.02#ibcon#enter sib2, iclass 27, count 0 2006.285.13:25:12.02#ibcon#flushed, iclass 27, count 0 2006.285.13:25:12.02#ibcon#about to write, iclass 27, count 0 2006.285.13:25:12.02#ibcon#wrote, iclass 27, count 0 2006.285.13:25:12.02#ibcon#about to read 3, iclass 27, count 0 2006.285.13:25:12.06#ibcon#read 3, iclass 27, count 0 2006.285.13:25:12.06#ibcon#about to read 4, iclass 27, count 0 2006.285.13:25:12.06#ibcon#read 4, iclass 27, count 0 2006.285.13:25:12.06#ibcon#about to read 5, iclass 27, count 0 2006.285.13:25:12.06#ibcon#read 5, iclass 27, count 0 2006.285.13:25:12.06#ibcon#about to read 6, iclass 27, count 0 2006.285.13:25:12.06#ibcon#read 6, iclass 27, count 0 2006.285.13:25:12.06#ibcon#end of sib2, iclass 27, count 0 2006.285.13:25:12.06#ibcon#*after write, iclass 27, count 0 2006.285.13:25:12.06#ibcon#*before return 0, iclass 27, count 0 2006.285.13:25:12.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:25:12.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:25:12.06#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:25:12.06#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:25:12.06$vck44/va=4,6 2006.285.13:25:12.06#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.13:25:12.06#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.13:25:12.06#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:12.06#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:25:12.12#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:25:12.12#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:25:12.12#ibcon#enter wrdev, iclass 29, count 2 2006.285.13:25:12.12#ibcon#first serial, iclass 29, count 2 2006.285.13:25:12.12#ibcon#enter sib2, iclass 29, count 2 2006.285.13:25:12.12#ibcon#flushed, iclass 29, count 2 2006.285.13:25:12.12#ibcon#about to write, iclass 29, count 2 2006.285.13:25:12.12#ibcon#wrote, iclass 29, count 2 2006.285.13:25:12.12#ibcon#about to read 3, iclass 29, count 2 2006.285.13:25:12.14#ibcon#read 3, iclass 29, count 2 2006.285.13:25:12.14#ibcon#about to read 4, iclass 29, count 2 2006.285.13:25:12.14#ibcon#read 4, iclass 29, count 2 2006.285.13:25:12.14#ibcon#about to read 5, iclass 29, count 2 2006.285.13:25:12.14#ibcon#read 5, iclass 29, count 2 2006.285.13:25:12.14#ibcon#about to read 6, iclass 29, count 2 2006.285.13:25:12.14#ibcon#read 6, iclass 29, count 2 2006.285.13:25:12.14#ibcon#end of sib2, iclass 29, count 2 2006.285.13:25:12.14#ibcon#*mode == 0, iclass 29, count 2 2006.285.13:25:12.14#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.13:25:12.14#ibcon#[25=AT04-06\r\n] 2006.285.13:25:12.14#ibcon#*before write, iclass 29, count 2 2006.285.13:25:12.14#ibcon#enter sib2, iclass 29, count 2 2006.285.13:25:12.14#ibcon#flushed, iclass 29, count 2 2006.285.13:25:12.14#ibcon#about to write, iclass 29, count 2 2006.285.13:25:12.14#ibcon#wrote, iclass 29, count 2 2006.285.13:25:12.14#ibcon#about to read 3, iclass 29, count 2 2006.285.13:25:12.17#ibcon#read 3, iclass 29, count 2 2006.285.13:25:12.17#ibcon#about to read 4, iclass 29, count 2 2006.285.13:25:12.17#ibcon#read 4, iclass 29, count 2 2006.285.13:25:12.17#ibcon#about to read 5, iclass 29, count 2 2006.285.13:25:12.17#ibcon#read 5, iclass 29, count 2 2006.285.13:25:12.17#ibcon#about to read 6, iclass 29, count 2 2006.285.13:25:12.17#ibcon#read 6, iclass 29, count 2 2006.285.13:25:12.17#ibcon#end of sib2, iclass 29, count 2 2006.285.13:25:12.17#ibcon#*after write, iclass 29, count 2 2006.285.13:25:12.17#ibcon#*before return 0, iclass 29, count 2 2006.285.13:25:12.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:25:12.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:25:12.17#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.13:25:12.17#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:12.17#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:25:12.29#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:25:12.29#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:25:12.29#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:25:12.29#ibcon#first serial, iclass 29, count 0 2006.285.13:25:12.29#ibcon#enter sib2, iclass 29, count 0 2006.285.13:25:12.29#ibcon#flushed, iclass 29, count 0 2006.285.13:25:12.29#ibcon#about to write, iclass 29, count 0 2006.285.13:25:12.29#ibcon#wrote, iclass 29, count 0 2006.285.13:25:12.29#ibcon#about to read 3, iclass 29, count 0 2006.285.13:25:12.31#ibcon#read 3, iclass 29, count 0 2006.285.13:25:12.31#ibcon#about to read 4, iclass 29, count 0 2006.285.13:25:12.31#ibcon#read 4, iclass 29, count 0 2006.285.13:25:12.31#ibcon#about to read 5, iclass 29, count 0 2006.285.13:25:12.35#ibcon#read 5, iclass 29, count 0 2006.285.13:25:12.35#ibcon#about to read 6, iclass 29, count 0 2006.285.13:25:12.35#ibcon#read 6, iclass 29, count 0 2006.285.13:25:12.35#ibcon#end of sib2, iclass 29, count 0 2006.285.13:25:12.35#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:25:12.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:25:12.35#ibcon#[25=USB\r\n] 2006.285.13:25:12.35#ibcon#*before write, iclass 29, count 0 2006.285.13:25:12.35#ibcon#enter sib2, iclass 29, count 0 2006.285.13:25:12.35#ibcon#flushed, iclass 29, count 0 2006.285.13:25:12.35#ibcon#about to write, iclass 29, count 0 2006.285.13:25:12.35#ibcon#wrote, iclass 29, count 0 2006.285.13:25:12.35#ibcon#about to read 3, iclass 29, count 0 2006.285.13:25:12.38#ibcon#read 3, iclass 29, count 0 2006.285.13:25:12.38#ibcon#about to read 4, iclass 29, count 0 2006.285.13:25:12.38#ibcon#read 4, iclass 29, count 0 2006.285.13:25:12.38#ibcon#about to read 5, iclass 29, count 0 2006.285.13:25:12.38#ibcon#read 5, iclass 29, count 0 2006.285.13:25:12.38#ibcon#about to read 6, iclass 29, count 0 2006.285.13:25:12.38#ibcon#read 6, iclass 29, count 0 2006.285.13:25:12.38#ibcon#end of sib2, iclass 29, count 0 2006.285.13:25:12.38#ibcon#*after write, iclass 29, count 0 2006.285.13:25:12.38#ibcon#*before return 0, iclass 29, count 0 2006.285.13:25:12.38#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:25:12.38#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:25:12.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:25:12.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:25:12.38$vck44/valo=5,734.99 2006.285.13:25:12.38#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.13:25:12.38#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.13:25:12.38#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:12.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:25:12.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:25:12.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:25:12.38#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:25:12.38#ibcon#first serial, iclass 31, count 0 2006.285.13:25:12.38#ibcon#enter sib2, iclass 31, count 0 2006.285.13:25:12.38#ibcon#flushed, iclass 31, count 0 2006.285.13:25:12.38#ibcon#about to write, iclass 31, count 0 2006.285.13:25:12.38#ibcon#wrote, iclass 31, count 0 2006.285.13:25:12.38#ibcon#about to read 3, iclass 31, count 0 2006.285.13:25:12.40#ibcon#read 3, iclass 31, count 0 2006.285.13:25:12.40#ibcon#about to read 4, iclass 31, count 0 2006.285.13:25:12.40#ibcon#read 4, iclass 31, count 0 2006.285.13:25:12.40#ibcon#about to read 5, iclass 31, count 0 2006.285.13:25:12.40#ibcon#read 5, iclass 31, count 0 2006.285.13:25:12.40#ibcon#about to read 6, iclass 31, count 0 2006.285.13:25:12.40#ibcon#read 6, iclass 31, count 0 2006.285.13:25:12.40#ibcon#end of sib2, iclass 31, count 0 2006.285.13:25:12.40#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:25:12.40#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:25:12.40#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:25:12.40#ibcon#*before write, iclass 31, count 0 2006.285.13:25:12.40#ibcon#enter sib2, iclass 31, count 0 2006.285.13:25:12.40#ibcon#flushed, iclass 31, count 0 2006.285.13:25:12.40#ibcon#about to write, iclass 31, count 0 2006.285.13:25:12.40#ibcon#wrote, iclass 31, count 0 2006.285.13:25:12.40#ibcon#about to read 3, iclass 31, count 0 2006.285.13:25:12.44#ibcon#read 3, iclass 31, count 0 2006.285.13:25:12.44#ibcon#about to read 4, iclass 31, count 0 2006.285.13:25:12.44#ibcon#read 4, iclass 31, count 0 2006.285.13:25:12.44#ibcon#about to read 5, iclass 31, count 0 2006.285.13:25:12.44#ibcon#read 5, iclass 31, count 0 2006.285.13:25:12.44#ibcon#about to read 6, iclass 31, count 0 2006.285.13:25:12.44#ibcon#read 6, iclass 31, count 0 2006.285.13:25:12.44#ibcon#end of sib2, iclass 31, count 0 2006.285.13:25:12.44#ibcon#*after write, iclass 31, count 0 2006.285.13:25:12.44#ibcon#*before return 0, iclass 31, count 0 2006.285.13:25:12.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:25:12.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:25:12.44#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:25:12.44#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:25:12.44$vck44/va=5,3 2006.285.13:25:12.44#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.13:25:12.44#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.13:25:12.44#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:12.44#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:25:12.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:25:12.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:25:12.50#ibcon#enter wrdev, iclass 33, count 2 2006.285.13:25:12.50#ibcon#first serial, iclass 33, count 2 2006.285.13:25:12.50#ibcon#enter sib2, iclass 33, count 2 2006.285.13:25:12.50#ibcon#flushed, iclass 33, count 2 2006.285.13:25:12.50#ibcon#about to write, iclass 33, count 2 2006.285.13:25:12.50#ibcon#wrote, iclass 33, count 2 2006.285.13:25:12.50#ibcon#about to read 3, iclass 33, count 2 2006.285.13:25:12.52#ibcon#read 3, iclass 33, count 2 2006.285.13:25:12.52#ibcon#about to read 4, iclass 33, count 2 2006.285.13:25:12.52#ibcon#read 4, iclass 33, count 2 2006.285.13:25:12.52#ibcon#about to read 5, iclass 33, count 2 2006.285.13:25:12.52#ibcon#read 5, iclass 33, count 2 2006.285.13:25:12.52#ibcon#about to read 6, iclass 33, count 2 2006.285.13:25:12.52#ibcon#read 6, iclass 33, count 2 2006.285.13:25:12.52#ibcon#end of sib2, iclass 33, count 2 2006.285.13:25:12.52#ibcon#*mode == 0, iclass 33, count 2 2006.285.13:25:12.52#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.13:25:12.52#ibcon#[25=AT05-03\r\n] 2006.285.13:25:12.52#ibcon#*before write, iclass 33, count 2 2006.285.13:25:12.52#ibcon#enter sib2, iclass 33, count 2 2006.285.13:25:12.52#ibcon#flushed, iclass 33, count 2 2006.285.13:25:12.52#ibcon#about to write, iclass 33, count 2 2006.285.13:25:12.52#ibcon#wrote, iclass 33, count 2 2006.285.13:25:12.52#ibcon#about to read 3, iclass 33, count 2 2006.285.13:25:12.55#ibcon#read 3, iclass 33, count 2 2006.285.13:25:12.55#ibcon#about to read 4, iclass 33, count 2 2006.285.13:25:12.55#ibcon#read 4, iclass 33, count 2 2006.285.13:25:12.55#ibcon#about to read 5, iclass 33, count 2 2006.285.13:25:12.55#ibcon#read 5, iclass 33, count 2 2006.285.13:25:12.55#ibcon#about to read 6, iclass 33, count 2 2006.285.13:25:12.55#ibcon#read 6, iclass 33, count 2 2006.285.13:25:12.55#ibcon#end of sib2, iclass 33, count 2 2006.285.13:25:12.55#ibcon#*after write, iclass 33, count 2 2006.285.13:25:12.55#ibcon#*before return 0, iclass 33, count 2 2006.285.13:25:12.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:25:12.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:25:12.55#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.13:25:12.55#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:12.55#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:25:12.67#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:25:12.67#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:25:12.67#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:25:12.67#ibcon#first serial, iclass 33, count 0 2006.285.13:25:12.67#ibcon#enter sib2, iclass 33, count 0 2006.285.13:25:12.67#ibcon#flushed, iclass 33, count 0 2006.285.13:25:12.67#ibcon#about to write, iclass 33, count 0 2006.285.13:25:12.67#ibcon#wrote, iclass 33, count 0 2006.285.13:25:12.67#ibcon#about to read 3, iclass 33, count 0 2006.285.13:25:12.69#ibcon#read 3, iclass 33, count 0 2006.285.13:25:12.69#ibcon#about to read 4, iclass 33, count 0 2006.285.13:25:12.69#ibcon#read 4, iclass 33, count 0 2006.285.13:25:12.69#ibcon#about to read 5, iclass 33, count 0 2006.285.13:25:12.69#ibcon#read 5, iclass 33, count 0 2006.285.13:25:12.69#ibcon#about to read 6, iclass 33, count 0 2006.285.13:25:12.69#ibcon#read 6, iclass 33, count 0 2006.285.13:25:12.69#ibcon#end of sib2, iclass 33, count 0 2006.285.13:25:12.69#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:25:12.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:25:12.69#ibcon#[25=USB\r\n] 2006.285.13:25:12.69#ibcon#*before write, iclass 33, count 0 2006.285.13:25:12.69#ibcon#enter sib2, iclass 33, count 0 2006.285.13:25:12.69#ibcon#flushed, iclass 33, count 0 2006.285.13:25:12.69#ibcon#about to write, iclass 33, count 0 2006.285.13:25:12.69#ibcon#wrote, iclass 33, count 0 2006.285.13:25:12.69#ibcon#about to read 3, iclass 33, count 0 2006.285.13:25:12.72#ibcon#read 3, iclass 33, count 0 2006.285.13:25:12.72#ibcon#about to read 4, iclass 33, count 0 2006.285.13:25:12.72#ibcon#read 4, iclass 33, count 0 2006.285.13:25:12.72#ibcon#about to read 5, iclass 33, count 0 2006.285.13:25:12.72#ibcon#read 5, iclass 33, count 0 2006.285.13:25:12.72#ibcon#about to read 6, iclass 33, count 0 2006.285.13:25:12.72#ibcon#read 6, iclass 33, count 0 2006.285.13:25:12.72#ibcon#end of sib2, iclass 33, count 0 2006.285.13:25:12.72#ibcon#*after write, iclass 33, count 0 2006.285.13:25:12.72#ibcon#*before return 0, iclass 33, count 0 2006.285.13:25:12.72#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:25:12.72#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:25:12.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:25:12.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:25:12.72$vck44/valo=6,814.99 2006.285.13:25:12.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.13:25:12.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.13:25:12.72#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:12.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:25:12.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:25:12.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:25:12.72#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:25:12.72#ibcon#first serial, iclass 35, count 0 2006.285.13:25:12.72#ibcon#enter sib2, iclass 35, count 0 2006.285.13:25:12.72#ibcon#flushed, iclass 35, count 0 2006.285.13:25:12.72#ibcon#about to write, iclass 35, count 0 2006.285.13:25:12.72#ibcon#wrote, iclass 35, count 0 2006.285.13:25:12.72#ibcon#about to read 3, iclass 35, count 0 2006.285.13:25:12.74#ibcon#read 3, iclass 35, count 0 2006.285.13:25:12.74#ibcon#about to read 4, iclass 35, count 0 2006.285.13:25:12.74#ibcon#read 4, iclass 35, count 0 2006.285.13:25:12.74#ibcon#about to read 5, iclass 35, count 0 2006.285.13:25:12.74#ibcon#read 5, iclass 35, count 0 2006.285.13:25:12.74#ibcon#about to read 6, iclass 35, count 0 2006.285.13:25:12.74#ibcon#read 6, iclass 35, count 0 2006.285.13:25:12.74#ibcon#end of sib2, iclass 35, count 0 2006.285.13:25:12.74#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:25:12.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:25:12.74#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:25:12.74#ibcon#*before write, iclass 35, count 0 2006.285.13:25:12.74#ibcon#enter sib2, iclass 35, count 0 2006.285.13:25:12.74#ibcon#flushed, iclass 35, count 0 2006.285.13:25:12.74#ibcon#about to write, iclass 35, count 0 2006.285.13:25:12.74#ibcon#wrote, iclass 35, count 0 2006.285.13:25:12.74#ibcon#about to read 3, iclass 35, count 0 2006.285.13:25:12.78#ibcon#read 3, iclass 35, count 0 2006.285.13:25:12.78#ibcon#about to read 4, iclass 35, count 0 2006.285.13:25:12.78#ibcon#read 4, iclass 35, count 0 2006.285.13:25:12.78#ibcon#about to read 5, iclass 35, count 0 2006.285.13:25:12.78#ibcon#read 5, iclass 35, count 0 2006.285.13:25:12.78#ibcon#about to read 6, iclass 35, count 0 2006.285.13:25:12.78#ibcon#read 6, iclass 35, count 0 2006.285.13:25:12.78#ibcon#end of sib2, iclass 35, count 0 2006.285.13:25:12.78#ibcon#*after write, iclass 35, count 0 2006.285.13:25:12.78#ibcon#*before return 0, iclass 35, count 0 2006.285.13:25:12.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:25:12.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:25:12.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:25:12.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:25:12.78$vck44/va=6,4 2006.285.13:25:12.78#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.13:25:12.78#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.13:25:12.78#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:12.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:25:12.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:25:12.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:25:12.84#ibcon#enter wrdev, iclass 37, count 2 2006.285.13:25:12.84#ibcon#first serial, iclass 37, count 2 2006.285.13:25:12.84#ibcon#enter sib2, iclass 37, count 2 2006.285.13:25:12.84#ibcon#flushed, iclass 37, count 2 2006.285.13:25:12.84#ibcon#about to write, iclass 37, count 2 2006.285.13:25:12.84#ibcon#wrote, iclass 37, count 2 2006.285.13:25:12.84#ibcon#about to read 3, iclass 37, count 2 2006.285.13:25:12.86#ibcon#read 3, iclass 37, count 2 2006.285.13:25:12.86#ibcon#about to read 4, iclass 37, count 2 2006.285.13:25:12.86#ibcon#read 4, iclass 37, count 2 2006.285.13:25:12.86#ibcon#about to read 5, iclass 37, count 2 2006.285.13:25:12.86#ibcon#read 5, iclass 37, count 2 2006.285.13:25:12.86#ibcon#about to read 6, iclass 37, count 2 2006.285.13:25:12.86#ibcon#read 6, iclass 37, count 2 2006.285.13:25:12.86#ibcon#end of sib2, iclass 37, count 2 2006.285.13:25:12.86#ibcon#*mode == 0, iclass 37, count 2 2006.285.13:25:12.86#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.13:25:12.86#ibcon#[25=AT06-04\r\n] 2006.285.13:25:12.86#ibcon#*before write, iclass 37, count 2 2006.285.13:25:12.86#ibcon#enter sib2, iclass 37, count 2 2006.285.13:25:12.86#ibcon#flushed, iclass 37, count 2 2006.285.13:25:12.86#ibcon#about to write, iclass 37, count 2 2006.285.13:25:12.86#ibcon#wrote, iclass 37, count 2 2006.285.13:25:12.86#ibcon#about to read 3, iclass 37, count 2 2006.285.13:25:12.89#ibcon#read 3, iclass 37, count 2 2006.285.13:25:12.89#ibcon#about to read 4, iclass 37, count 2 2006.285.13:25:12.89#ibcon#read 4, iclass 37, count 2 2006.285.13:25:12.89#ibcon#about to read 5, iclass 37, count 2 2006.285.13:25:12.89#ibcon#read 5, iclass 37, count 2 2006.285.13:25:12.89#ibcon#about to read 6, iclass 37, count 2 2006.285.13:25:12.89#ibcon#read 6, iclass 37, count 2 2006.285.13:25:12.89#ibcon#end of sib2, iclass 37, count 2 2006.285.13:25:12.89#ibcon#*after write, iclass 37, count 2 2006.285.13:25:12.89#ibcon#*before return 0, iclass 37, count 2 2006.285.13:25:12.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:25:12.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:25:12.89#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.13:25:12.89#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:12.89#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:25:13.01#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:25:13.01#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:25:13.01#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:25:13.01#ibcon#first serial, iclass 37, count 0 2006.285.13:25:13.01#ibcon#enter sib2, iclass 37, count 0 2006.285.13:25:13.01#ibcon#flushed, iclass 37, count 0 2006.285.13:25:13.01#ibcon#about to write, iclass 37, count 0 2006.285.13:25:13.01#ibcon#wrote, iclass 37, count 0 2006.285.13:25:13.01#ibcon#about to read 3, iclass 37, count 0 2006.285.13:25:13.03#ibcon#read 3, iclass 37, count 0 2006.285.13:25:13.03#ibcon#about to read 4, iclass 37, count 0 2006.285.13:25:13.03#ibcon#read 4, iclass 37, count 0 2006.285.13:25:13.03#ibcon#about to read 5, iclass 37, count 0 2006.285.13:25:13.03#ibcon#read 5, iclass 37, count 0 2006.285.13:25:13.03#ibcon#about to read 6, iclass 37, count 0 2006.285.13:25:13.03#ibcon#read 6, iclass 37, count 0 2006.285.13:25:13.03#ibcon#end of sib2, iclass 37, count 0 2006.285.13:25:13.03#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:25:13.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:25:13.03#ibcon#[25=USB\r\n] 2006.285.13:25:13.03#ibcon#*before write, iclass 37, count 0 2006.285.13:25:13.03#ibcon#enter sib2, iclass 37, count 0 2006.285.13:25:13.03#ibcon#flushed, iclass 37, count 0 2006.285.13:25:13.03#ibcon#about to write, iclass 37, count 0 2006.285.13:25:13.03#ibcon#wrote, iclass 37, count 0 2006.285.13:25:13.03#ibcon#about to read 3, iclass 37, count 0 2006.285.13:25:13.06#ibcon#read 3, iclass 37, count 0 2006.285.13:25:13.06#ibcon#about to read 4, iclass 37, count 0 2006.285.13:25:13.06#ibcon#read 4, iclass 37, count 0 2006.285.13:25:13.06#ibcon#about to read 5, iclass 37, count 0 2006.285.13:25:13.06#ibcon#read 5, iclass 37, count 0 2006.285.13:25:13.06#ibcon#about to read 6, iclass 37, count 0 2006.285.13:25:13.06#ibcon#read 6, iclass 37, count 0 2006.285.13:25:13.06#ibcon#end of sib2, iclass 37, count 0 2006.285.13:25:13.06#ibcon#*after write, iclass 37, count 0 2006.285.13:25:13.06#ibcon#*before return 0, iclass 37, count 0 2006.285.13:25:13.06#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:25:13.06#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:25:13.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:25:13.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:25:13.06$vck44/valo=7,864.99 2006.285.13:25:13.06#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.13:25:13.06#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.13:25:13.06#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:13.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:25:13.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:25:13.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:25:13.06#ibcon#enter wrdev, iclass 40, count 0 2006.285.13:25:13.06#ibcon#first serial, iclass 40, count 0 2006.285.13:25:13.06#ibcon#enter sib2, iclass 40, count 0 2006.285.13:25:13.06#ibcon#flushed, iclass 40, count 0 2006.285.13:25:13.06#ibcon#about to write, iclass 40, count 0 2006.285.13:25:13.06#ibcon#wrote, iclass 40, count 0 2006.285.13:25:13.06#ibcon#about to read 3, iclass 40, count 0 2006.285.13:25:13.08#ibcon#read 3, iclass 40, count 0 2006.285.13:25:13.08#ibcon#about to read 4, iclass 40, count 0 2006.285.13:25:13.08#ibcon#read 4, iclass 40, count 0 2006.285.13:25:13.08#ibcon#about to read 5, iclass 40, count 0 2006.285.13:25:13.08#ibcon#read 5, iclass 40, count 0 2006.285.13:25:13.08#ibcon#about to read 6, iclass 40, count 0 2006.285.13:25:13.08#ibcon#read 6, iclass 40, count 0 2006.285.13:25:13.08#ibcon#end of sib2, iclass 40, count 0 2006.285.13:25:13.08#ibcon#*mode == 0, iclass 40, count 0 2006.285.13:25:13.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.13:25:13.08#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:25:13.08#ibcon#*before write, iclass 40, count 0 2006.285.13:25:13.08#ibcon#enter sib2, iclass 40, count 0 2006.285.13:25:13.08#ibcon#flushed, iclass 40, count 0 2006.285.13:25:13.08#ibcon#about to write, iclass 40, count 0 2006.285.13:25:13.08#ibcon#wrote, iclass 40, count 0 2006.285.13:25:13.08#ibcon#about to read 3, iclass 40, count 0 2006.285.13:25:13.10#abcon#<5=/04 1.5 2.4 19.09 971015.3\r\n> 2006.285.13:25:13.12#abcon#{5=INTERFACE CLEAR} 2006.285.13:25:13.12#ibcon#read 3, iclass 40, count 0 2006.285.13:25:13.12#ibcon#about to read 4, iclass 40, count 0 2006.285.13:25:13.12#ibcon#read 4, iclass 40, count 0 2006.285.13:25:13.12#ibcon#about to read 5, iclass 40, count 0 2006.285.13:25:13.12#ibcon#read 5, iclass 40, count 0 2006.285.13:25:13.12#ibcon#about to read 6, iclass 40, count 0 2006.285.13:25:13.12#ibcon#read 6, iclass 40, count 0 2006.285.13:25:13.12#ibcon#end of sib2, iclass 40, count 0 2006.285.13:25:13.12#ibcon#*after write, iclass 40, count 0 2006.285.13:25:13.12#ibcon#*before return 0, iclass 40, count 0 2006.285.13:25:13.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:25:13.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:25:13.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.13:25:13.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.13:25:13.21$vck44/va=7,4 2006.285.13:25:13.21#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.13:25:13.21#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.13:25:13.21#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:13.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:25:13.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:25:13.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:25:13.21#ibcon#enter wrdev, iclass 6, count 2 2006.285.13:25:13.21#ibcon#first serial, iclass 6, count 2 2006.285.13:25:13.21#ibcon#enter sib2, iclass 6, count 2 2006.285.13:25:13.21#ibcon#flushed, iclass 6, count 2 2006.285.13:25:13.21#ibcon#about to write, iclass 6, count 2 2006.285.13:25:13.21#ibcon#wrote, iclass 6, count 2 2006.285.13:25:13.21#ibcon#about to read 3, iclass 6, count 2 2006.285.13:25:13.22#ibcon#read 3, iclass 6, count 2 2006.285.13:25:13.22#ibcon#about to read 4, iclass 6, count 2 2006.285.13:25:13.22#ibcon#read 4, iclass 6, count 2 2006.285.13:25:13.22#ibcon#about to read 5, iclass 6, count 2 2006.285.13:25:13.22#ibcon#read 5, iclass 6, count 2 2006.285.13:25:13.22#ibcon#about to read 6, iclass 6, count 2 2006.285.13:25:13.22#ibcon#read 6, iclass 6, count 2 2006.285.13:25:13.22#ibcon#end of sib2, iclass 6, count 2 2006.285.13:25:13.22#ibcon#*mode == 0, iclass 6, count 2 2006.285.13:25:13.22#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.13:25:13.22#ibcon#[25=AT07-04\r\n] 2006.285.13:25:13.22#ibcon#*before write, iclass 6, count 2 2006.285.13:25:13.22#ibcon#enter sib2, iclass 6, count 2 2006.285.13:25:13.22#ibcon#flushed, iclass 6, count 2 2006.285.13:25:13.22#ibcon#about to write, iclass 6, count 2 2006.285.13:25:13.22#ibcon#wrote, iclass 6, count 2 2006.285.13:25:13.22#ibcon#about to read 3, iclass 6, count 2 2006.285.13:25:13.23#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:25:13.25#ibcon#read 3, iclass 6, count 2 2006.285.13:25:13.25#ibcon#about to read 4, iclass 6, count 2 2006.285.13:25:13.25#ibcon#read 4, iclass 6, count 2 2006.285.13:25:13.25#ibcon#about to read 5, iclass 6, count 2 2006.285.13:25:13.25#ibcon#read 5, iclass 6, count 2 2006.285.13:25:13.25#ibcon#about to read 6, iclass 6, count 2 2006.285.13:25:13.25#ibcon#read 6, iclass 6, count 2 2006.285.13:25:13.25#ibcon#end of sib2, iclass 6, count 2 2006.285.13:25:13.25#ibcon#*after write, iclass 6, count 2 2006.285.13:25:13.25#ibcon#*before return 0, iclass 6, count 2 2006.285.13:25:13.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:25:13.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:25:13.25#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.13:25:13.25#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:13.25#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:25:13.37#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:25:13.37#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:25:13.37#ibcon#enter wrdev, iclass 6, count 0 2006.285.13:25:13.37#ibcon#first serial, iclass 6, count 0 2006.285.13:25:13.37#ibcon#enter sib2, iclass 6, count 0 2006.285.13:25:13.37#ibcon#flushed, iclass 6, count 0 2006.285.13:25:13.37#ibcon#about to write, iclass 6, count 0 2006.285.13:25:13.37#ibcon#wrote, iclass 6, count 0 2006.285.13:25:13.37#ibcon#about to read 3, iclass 6, count 0 2006.285.13:25:13.39#ibcon#read 3, iclass 6, count 0 2006.285.13:25:13.39#ibcon#about to read 4, iclass 6, count 0 2006.285.13:25:13.39#ibcon#read 4, iclass 6, count 0 2006.285.13:25:13.39#ibcon#about to read 5, iclass 6, count 0 2006.285.13:25:13.39#ibcon#read 5, iclass 6, count 0 2006.285.13:25:13.39#ibcon#about to read 6, iclass 6, count 0 2006.285.13:25:13.39#ibcon#read 6, iclass 6, count 0 2006.285.13:25:13.39#ibcon#end of sib2, iclass 6, count 0 2006.285.13:25:13.39#ibcon#*mode == 0, iclass 6, count 0 2006.285.13:25:13.39#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.13:25:13.39#ibcon#[25=USB\r\n] 2006.285.13:25:13.39#ibcon#*before write, iclass 6, count 0 2006.285.13:25:13.39#ibcon#enter sib2, iclass 6, count 0 2006.285.13:25:13.39#ibcon#flushed, iclass 6, count 0 2006.285.13:25:13.39#ibcon#about to write, iclass 6, count 0 2006.285.13:25:13.39#ibcon#wrote, iclass 6, count 0 2006.285.13:25:13.39#ibcon#about to read 3, iclass 6, count 0 2006.285.13:25:13.42#ibcon#read 3, iclass 6, count 0 2006.285.13:25:13.42#ibcon#about to read 4, iclass 6, count 0 2006.285.13:25:13.42#ibcon#read 4, iclass 6, count 0 2006.285.13:25:13.42#ibcon#about to read 5, iclass 6, count 0 2006.285.13:25:13.42#ibcon#read 5, iclass 6, count 0 2006.285.13:25:13.42#ibcon#about to read 6, iclass 6, count 0 2006.285.13:25:13.42#ibcon#read 6, iclass 6, count 0 2006.285.13:25:13.42#ibcon#end of sib2, iclass 6, count 0 2006.285.13:25:13.42#ibcon#*after write, iclass 6, count 0 2006.285.13:25:13.42#ibcon#*before return 0, iclass 6, count 0 2006.285.13:25:13.42#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:25:13.42#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:25:13.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.13:25:13.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.13:25:13.42$vck44/valo=8,884.99 2006.285.13:25:13.42#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.13:25:13.42#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.13:25:13.42#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:13.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:25:13.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:25:13.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:25:13.42#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:25:13.42#ibcon#first serial, iclass 11, count 0 2006.285.13:25:13.42#ibcon#enter sib2, iclass 11, count 0 2006.285.13:25:13.42#ibcon#flushed, iclass 11, count 0 2006.285.13:25:13.42#ibcon#about to write, iclass 11, count 0 2006.285.13:25:13.42#ibcon#wrote, iclass 11, count 0 2006.285.13:25:13.42#ibcon#about to read 3, iclass 11, count 0 2006.285.13:25:13.44#ibcon#read 3, iclass 11, count 0 2006.285.13:25:13.44#ibcon#about to read 4, iclass 11, count 0 2006.285.13:25:13.44#ibcon#read 4, iclass 11, count 0 2006.285.13:25:13.44#ibcon#about to read 5, iclass 11, count 0 2006.285.13:25:13.44#ibcon#read 5, iclass 11, count 0 2006.285.13:25:13.44#ibcon#about to read 6, iclass 11, count 0 2006.285.13:25:13.44#ibcon#read 6, iclass 11, count 0 2006.285.13:25:13.44#ibcon#end of sib2, iclass 11, count 0 2006.285.13:25:13.44#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:25:13.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:25:13.44#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:25:13.44#ibcon#*before write, iclass 11, count 0 2006.285.13:25:13.44#ibcon#enter sib2, iclass 11, count 0 2006.285.13:25:13.44#ibcon#flushed, iclass 11, count 0 2006.285.13:25:13.44#ibcon#about to write, iclass 11, count 0 2006.285.13:25:13.44#ibcon#wrote, iclass 11, count 0 2006.285.13:25:13.44#ibcon#about to read 3, iclass 11, count 0 2006.285.13:25:13.48#ibcon#read 3, iclass 11, count 0 2006.285.13:25:13.48#ibcon#about to read 4, iclass 11, count 0 2006.285.13:25:13.48#ibcon#read 4, iclass 11, count 0 2006.285.13:25:13.48#ibcon#about to read 5, iclass 11, count 0 2006.285.13:25:13.48#ibcon#read 5, iclass 11, count 0 2006.285.13:25:13.48#ibcon#about to read 6, iclass 11, count 0 2006.285.13:25:13.48#ibcon#read 6, iclass 11, count 0 2006.285.13:25:13.48#ibcon#end of sib2, iclass 11, count 0 2006.285.13:25:13.48#ibcon#*after write, iclass 11, count 0 2006.285.13:25:13.48#ibcon#*before return 0, iclass 11, count 0 2006.285.13:25:13.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:25:13.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:25:13.48#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:25:13.48#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:25:13.48$vck44/va=8,3 2006.285.13:25:13.48#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.13:25:13.48#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.13:25:13.48#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:13.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:25:13.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:25:13.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:25:13.54#ibcon#enter wrdev, iclass 13, count 2 2006.285.13:25:13.54#ibcon#first serial, iclass 13, count 2 2006.285.13:25:13.54#ibcon#enter sib2, iclass 13, count 2 2006.285.13:25:13.54#ibcon#flushed, iclass 13, count 2 2006.285.13:25:13.54#ibcon#about to write, iclass 13, count 2 2006.285.13:25:13.54#ibcon#wrote, iclass 13, count 2 2006.285.13:25:13.54#ibcon#about to read 3, iclass 13, count 2 2006.285.13:25:13.56#ibcon#read 3, iclass 13, count 2 2006.285.13:25:13.56#ibcon#about to read 4, iclass 13, count 2 2006.285.13:25:13.56#ibcon#read 4, iclass 13, count 2 2006.285.13:25:13.56#ibcon#about to read 5, iclass 13, count 2 2006.285.13:25:13.56#ibcon#read 5, iclass 13, count 2 2006.285.13:25:13.56#ibcon#about to read 6, iclass 13, count 2 2006.285.13:25:13.56#ibcon#read 6, iclass 13, count 2 2006.285.13:25:13.56#ibcon#end of sib2, iclass 13, count 2 2006.285.13:25:13.56#ibcon#*mode == 0, iclass 13, count 2 2006.285.13:25:13.56#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.13:25:13.56#ibcon#[25=AT08-03\r\n] 2006.285.13:25:13.56#ibcon#*before write, iclass 13, count 2 2006.285.13:25:13.56#ibcon#enter sib2, iclass 13, count 2 2006.285.13:25:13.56#ibcon#flushed, iclass 13, count 2 2006.285.13:25:13.56#ibcon#about to write, iclass 13, count 2 2006.285.13:25:13.56#ibcon#wrote, iclass 13, count 2 2006.285.13:25:13.56#ibcon#about to read 3, iclass 13, count 2 2006.285.13:25:13.59#ibcon#read 3, iclass 13, count 2 2006.285.13:25:13.59#ibcon#about to read 4, iclass 13, count 2 2006.285.13:25:13.59#ibcon#read 4, iclass 13, count 2 2006.285.13:25:13.59#ibcon#about to read 5, iclass 13, count 2 2006.285.13:25:13.59#ibcon#read 5, iclass 13, count 2 2006.285.13:25:13.59#ibcon#about to read 6, iclass 13, count 2 2006.285.13:25:13.59#ibcon#read 6, iclass 13, count 2 2006.285.13:25:13.59#ibcon#end of sib2, iclass 13, count 2 2006.285.13:25:13.59#ibcon#*after write, iclass 13, count 2 2006.285.13:25:13.59#ibcon#*before return 0, iclass 13, count 2 2006.285.13:25:13.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:25:13.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:25:13.59#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.13:25:13.59#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:13.59#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:25:13.71#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:25:13.71#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:25:13.71#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:25:13.71#ibcon#first serial, iclass 13, count 0 2006.285.13:25:13.71#ibcon#enter sib2, iclass 13, count 0 2006.285.13:25:13.71#ibcon#flushed, iclass 13, count 0 2006.285.13:25:13.71#ibcon#about to write, iclass 13, count 0 2006.285.13:25:13.71#ibcon#wrote, iclass 13, count 0 2006.285.13:25:13.71#ibcon#about to read 3, iclass 13, count 0 2006.285.13:25:13.73#ibcon#read 3, iclass 13, count 0 2006.285.13:25:13.73#ibcon#about to read 4, iclass 13, count 0 2006.285.13:25:13.73#ibcon#read 4, iclass 13, count 0 2006.285.13:25:13.73#ibcon#about to read 5, iclass 13, count 0 2006.285.13:25:13.73#ibcon#read 5, iclass 13, count 0 2006.285.13:25:13.73#ibcon#about to read 6, iclass 13, count 0 2006.285.13:25:13.73#ibcon#read 6, iclass 13, count 0 2006.285.13:25:13.73#ibcon#end of sib2, iclass 13, count 0 2006.285.13:25:13.73#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:25:13.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:25:13.73#ibcon#[25=USB\r\n] 2006.285.13:25:13.73#ibcon#*before write, iclass 13, count 0 2006.285.13:25:13.73#ibcon#enter sib2, iclass 13, count 0 2006.285.13:25:13.73#ibcon#flushed, iclass 13, count 0 2006.285.13:25:13.73#ibcon#about to write, iclass 13, count 0 2006.285.13:25:13.73#ibcon#wrote, iclass 13, count 0 2006.285.13:25:13.73#ibcon#about to read 3, iclass 13, count 0 2006.285.13:25:13.76#ibcon#read 3, iclass 13, count 0 2006.285.13:25:13.76#ibcon#about to read 4, iclass 13, count 0 2006.285.13:25:13.76#ibcon#read 4, iclass 13, count 0 2006.285.13:25:13.76#ibcon#about to read 5, iclass 13, count 0 2006.285.13:25:13.76#ibcon#read 5, iclass 13, count 0 2006.285.13:25:13.76#ibcon#about to read 6, iclass 13, count 0 2006.285.13:25:13.76#ibcon#read 6, iclass 13, count 0 2006.285.13:25:13.76#ibcon#end of sib2, iclass 13, count 0 2006.285.13:25:13.76#ibcon#*after write, iclass 13, count 0 2006.285.13:25:13.76#ibcon#*before return 0, iclass 13, count 0 2006.285.13:25:13.76#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:25:13.76#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:25:13.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:25:13.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:25:13.76$vck44/vblo=1,629.99 2006.285.13:25:13.76#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.13:25:13.76#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.13:25:13.76#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:13.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:25:13.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:25:13.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:25:13.76#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:25:13.76#ibcon#first serial, iclass 15, count 0 2006.285.13:25:13.76#ibcon#enter sib2, iclass 15, count 0 2006.285.13:25:13.76#ibcon#flushed, iclass 15, count 0 2006.285.13:25:13.76#ibcon#about to write, iclass 15, count 0 2006.285.13:25:13.76#ibcon#wrote, iclass 15, count 0 2006.285.13:25:13.76#ibcon#about to read 3, iclass 15, count 0 2006.285.13:25:13.78#ibcon#read 3, iclass 15, count 0 2006.285.13:25:13.78#ibcon#about to read 4, iclass 15, count 0 2006.285.13:25:13.78#ibcon#read 4, iclass 15, count 0 2006.285.13:25:13.78#ibcon#about to read 5, iclass 15, count 0 2006.285.13:25:13.78#ibcon#read 5, iclass 15, count 0 2006.285.13:25:13.78#ibcon#about to read 6, iclass 15, count 0 2006.285.13:25:13.78#ibcon#read 6, iclass 15, count 0 2006.285.13:25:13.78#ibcon#end of sib2, iclass 15, count 0 2006.285.13:25:13.78#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:25:13.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:25:13.78#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:25:13.78#ibcon#*before write, iclass 15, count 0 2006.285.13:25:13.78#ibcon#enter sib2, iclass 15, count 0 2006.285.13:25:13.78#ibcon#flushed, iclass 15, count 0 2006.285.13:25:13.78#ibcon#about to write, iclass 15, count 0 2006.285.13:25:13.78#ibcon#wrote, iclass 15, count 0 2006.285.13:25:13.78#ibcon#about to read 3, iclass 15, count 0 2006.285.13:25:13.82#ibcon#read 3, iclass 15, count 0 2006.285.13:25:13.82#ibcon#about to read 4, iclass 15, count 0 2006.285.13:25:13.82#ibcon#read 4, iclass 15, count 0 2006.285.13:25:13.82#ibcon#about to read 5, iclass 15, count 0 2006.285.13:25:13.82#ibcon#read 5, iclass 15, count 0 2006.285.13:25:13.82#ibcon#about to read 6, iclass 15, count 0 2006.285.13:25:13.82#ibcon#read 6, iclass 15, count 0 2006.285.13:25:13.82#ibcon#end of sib2, iclass 15, count 0 2006.285.13:25:13.82#ibcon#*after write, iclass 15, count 0 2006.285.13:25:13.82#ibcon#*before return 0, iclass 15, count 0 2006.285.13:25:13.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:25:13.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:25:13.82#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:25:13.82#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:25:13.82$vck44/vb=1,4 2006.285.13:25:13.82#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.13:25:13.82#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.13:25:13.82#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:13.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:25:13.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:25:13.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:25:13.82#ibcon#enter wrdev, iclass 17, count 2 2006.285.13:25:13.82#ibcon#first serial, iclass 17, count 2 2006.285.13:25:13.82#ibcon#enter sib2, iclass 17, count 2 2006.285.13:25:13.82#ibcon#flushed, iclass 17, count 2 2006.285.13:25:13.82#ibcon#about to write, iclass 17, count 2 2006.285.13:25:13.82#ibcon#wrote, iclass 17, count 2 2006.285.13:25:13.82#ibcon#about to read 3, iclass 17, count 2 2006.285.13:25:13.84#ibcon#read 3, iclass 17, count 2 2006.285.13:25:13.84#ibcon#about to read 4, iclass 17, count 2 2006.285.13:25:13.84#ibcon#read 4, iclass 17, count 2 2006.285.13:25:13.84#ibcon#about to read 5, iclass 17, count 2 2006.285.13:25:13.84#ibcon#read 5, iclass 17, count 2 2006.285.13:25:13.84#ibcon#about to read 6, iclass 17, count 2 2006.285.13:25:13.84#ibcon#read 6, iclass 17, count 2 2006.285.13:25:13.84#ibcon#end of sib2, iclass 17, count 2 2006.285.13:25:13.84#ibcon#*mode == 0, iclass 17, count 2 2006.285.13:25:13.84#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.13:25:13.84#ibcon#[27=AT01-04\r\n] 2006.285.13:25:13.84#ibcon#*before write, iclass 17, count 2 2006.285.13:25:13.84#ibcon#enter sib2, iclass 17, count 2 2006.285.13:25:13.84#ibcon#flushed, iclass 17, count 2 2006.285.13:25:13.84#ibcon#about to write, iclass 17, count 2 2006.285.13:25:13.84#ibcon#wrote, iclass 17, count 2 2006.285.13:25:13.84#ibcon#about to read 3, iclass 17, count 2 2006.285.13:25:13.87#ibcon#read 3, iclass 17, count 2 2006.285.13:25:13.87#ibcon#about to read 4, iclass 17, count 2 2006.285.13:25:13.87#ibcon#read 4, iclass 17, count 2 2006.285.13:25:13.87#ibcon#about to read 5, iclass 17, count 2 2006.285.13:25:13.87#ibcon#read 5, iclass 17, count 2 2006.285.13:25:13.87#ibcon#about to read 6, iclass 17, count 2 2006.285.13:25:13.87#ibcon#read 6, iclass 17, count 2 2006.285.13:25:13.87#ibcon#end of sib2, iclass 17, count 2 2006.285.13:25:13.87#ibcon#*after write, iclass 17, count 2 2006.285.13:25:13.87#ibcon#*before return 0, iclass 17, count 2 2006.285.13:25:13.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:25:13.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:25:13.87#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.13:25:13.87#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:13.87#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:25:13.99#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:25:13.99#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:25:13.99#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:25:13.99#ibcon#first serial, iclass 17, count 0 2006.285.13:25:13.99#ibcon#enter sib2, iclass 17, count 0 2006.285.13:25:13.99#ibcon#flushed, iclass 17, count 0 2006.285.13:25:13.99#ibcon#about to write, iclass 17, count 0 2006.285.13:25:13.99#ibcon#wrote, iclass 17, count 0 2006.285.13:25:13.99#ibcon#about to read 3, iclass 17, count 0 2006.285.13:25:14.01#ibcon#read 3, iclass 17, count 0 2006.285.13:25:14.01#ibcon#about to read 4, iclass 17, count 0 2006.285.13:25:14.01#ibcon#read 4, iclass 17, count 0 2006.285.13:25:14.01#ibcon#about to read 5, iclass 17, count 0 2006.285.13:25:14.01#ibcon#read 5, iclass 17, count 0 2006.285.13:25:14.01#ibcon#about to read 6, iclass 17, count 0 2006.285.13:25:14.01#ibcon#read 6, iclass 17, count 0 2006.285.13:25:14.01#ibcon#end of sib2, iclass 17, count 0 2006.285.13:25:14.01#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:25:14.01#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:25:14.01#ibcon#[27=USB\r\n] 2006.285.13:25:14.01#ibcon#*before write, iclass 17, count 0 2006.285.13:25:14.01#ibcon#enter sib2, iclass 17, count 0 2006.285.13:25:14.01#ibcon#flushed, iclass 17, count 0 2006.285.13:25:14.01#ibcon#about to write, iclass 17, count 0 2006.285.13:25:14.01#ibcon#wrote, iclass 17, count 0 2006.285.13:25:14.01#ibcon#about to read 3, iclass 17, count 0 2006.285.13:25:14.04#ibcon#read 3, iclass 17, count 0 2006.285.13:25:14.04#ibcon#about to read 4, iclass 17, count 0 2006.285.13:25:14.04#ibcon#read 4, iclass 17, count 0 2006.285.13:25:14.04#ibcon#about to read 5, iclass 17, count 0 2006.285.13:25:14.04#ibcon#read 5, iclass 17, count 0 2006.285.13:25:14.04#ibcon#about to read 6, iclass 17, count 0 2006.285.13:25:14.04#ibcon#read 6, iclass 17, count 0 2006.285.13:25:14.04#ibcon#end of sib2, iclass 17, count 0 2006.285.13:25:14.04#ibcon#*after write, iclass 17, count 0 2006.285.13:25:14.04#ibcon#*before return 0, iclass 17, count 0 2006.285.13:25:14.04#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:25:14.04#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:25:14.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:25:14.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:25:14.04$vck44/vblo=2,634.99 2006.285.13:25:14.04#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.13:25:14.04#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.13:25:14.04#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:14.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:25:14.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:25:14.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:25:14.04#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:25:14.04#ibcon#first serial, iclass 19, count 0 2006.285.13:25:14.04#ibcon#enter sib2, iclass 19, count 0 2006.285.13:25:14.04#ibcon#flushed, iclass 19, count 0 2006.285.13:25:14.04#ibcon#about to write, iclass 19, count 0 2006.285.13:25:14.04#ibcon#wrote, iclass 19, count 0 2006.285.13:25:14.04#ibcon#about to read 3, iclass 19, count 0 2006.285.13:25:14.06#ibcon#read 3, iclass 19, count 0 2006.285.13:25:14.06#ibcon#about to read 4, iclass 19, count 0 2006.285.13:25:14.06#ibcon#read 4, iclass 19, count 0 2006.285.13:25:14.06#ibcon#about to read 5, iclass 19, count 0 2006.285.13:25:14.06#ibcon#read 5, iclass 19, count 0 2006.285.13:25:14.06#ibcon#about to read 6, iclass 19, count 0 2006.285.13:25:14.06#ibcon#read 6, iclass 19, count 0 2006.285.13:25:14.06#ibcon#end of sib2, iclass 19, count 0 2006.285.13:25:14.06#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:25:14.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:25:14.06#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:25:14.06#ibcon#*before write, iclass 19, count 0 2006.285.13:25:14.06#ibcon#enter sib2, iclass 19, count 0 2006.285.13:25:14.06#ibcon#flushed, iclass 19, count 0 2006.285.13:25:14.06#ibcon#about to write, iclass 19, count 0 2006.285.13:25:14.06#ibcon#wrote, iclass 19, count 0 2006.285.13:25:14.06#ibcon#about to read 3, iclass 19, count 0 2006.285.13:25:14.10#ibcon#read 3, iclass 19, count 0 2006.285.13:25:14.10#ibcon#about to read 4, iclass 19, count 0 2006.285.13:25:14.10#ibcon#read 4, iclass 19, count 0 2006.285.13:25:14.10#ibcon#about to read 5, iclass 19, count 0 2006.285.13:25:14.10#ibcon#read 5, iclass 19, count 0 2006.285.13:25:14.10#ibcon#about to read 6, iclass 19, count 0 2006.285.13:25:14.10#ibcon#read 6, iclass 19, count 0 2006.285.13:25:14.10#ibcon#end of sib2, iclass 19, count 0 2006.285.13:25:14.10#ibcon#*after write, iclass 19, count 0 2006.285.13:25:14.10#ibcon#*before return 0, iclass 19, count 0 2006.285.13:25:14.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:25:14.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:25:14.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:25:14.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:25:14.10$vck44/vb=2,5 2006.285.13:25:14.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.13:25:14.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.13:25:14.10#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:14.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:25:14.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:25:14.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:25:14.16#ibcon#enter wrdev, iclass 21, count 2 2006.285.13:25:14.16#ibcon#first serial, iclass 21, count 2 2006.285.13:25:14.16#ibcon#enter sib2, iclass 21, count 2 2006.285.13:25:14.16#ibcon#flushed, iclass 21, count 2 2006.285.13:25:14.16#ibcon#about to write, iclass 21, count 2 2006.285.13:25:14.16#ibcon#wrote, iclass 21, count 2 2006.285.13:25:14.16#ibcon#about to read 3, iclass 21, count 2 2006.285.13:25:14.18#ibcon#read 3, iclass 21, count 2 2006.285.13:25:14.18#ibcon#about to read 4, iclass 21, count 2 2006.285.13:25:14.18#ibcon#read 4, iclass 21, count 2 2006.285.13:25:14.18#ibcon#about to read 5, iclass 21, count 2 2006.285.13:25:14.18#ibcon#read 5, iclass 21, count 2 2006.285.13:25:14.18#ibcon#about to read 6, iclass 21, count 2 2006.285.13:25:14.18#ibcon#read 6, iclass 21, count 2 2006.285.13:25:14.18#ibcon#end of sib2, iclass 21, count 2 2006.285.13:25:14.18#ibcon#*mode == 0, iclass 21, count 2 2006.285.13:25:14.18#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.13:25:14.18#ibcon#[27=AT02-05\r\n] 2006.285.13:25:14.18#ibcon#*before write, iclass 21, count 2 2006.285.13:25:14.18#ibcon#enter sib2, iclass 21, count 2 2006.285.13:25:14.18#ibcon#flushed, iclass 21, count 2 2006.285.13:25:14.18#ibcon#about to write, iclass 21, count 2 2006.285.13:25:14.18#ibcon#wrote, iclass 21, count 2 2006.285.13:25:14.18#ibcon#about to read 3, iclass 21, count 2 2006.285.13:25:14.21#ibcon#read 3, iclass 21, count 2 2006.285.13:25:14.21#ibcon#about to read 4, iclass 21, count 2 2006.285.13:25:14.21#ibcon#read 4, iclass 21, count 2 2006.285.13:25:14.21#ibcon#about to read 5, iclass 21, count 2 2006.285.13:25:14.21#ibcon#read 5, iclass 21, count 2 2006.285.13:25:14.21#ibcon#about to read 6, iclass 21, count 2 2006.285.13:25:14.21#ibcon#read 6, iclass 21, count 2 2006.285.13:25:14.21#ibcon#end of sib2, iclass 21, count 2 2006.285.13:25:14.21#ibcon#*after write, iclass 21, count 2 2006.285.13:25:14.21#ibcon#*before return 0, iclass 21, count 2 2006.285.13:25:14.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:25:14.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:25:14.21#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.13:25:14.21#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:14.21#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:25:14.33#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:25:14.43#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:25:14.43#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:25:14.43#ibcon#first serial, iclass 21, count 0 2006.285.13:25:14.43#ibcon#enter sib2, iclass 21, count 0 2006.285.13:25:14.43#ibcon#flushed, iclass 21, count 0 2006.285.13:25:14.43#ibcon#about to write, iclass 21, count 0 2006.285.13:25:14.43#ibcon#wrote, iclass 21, count 0 2006.285.13:25:14.43#ibcon#about to read 3, iclass 21, count 0 2006.285.13:25:14.45#ibcon#read 3, iclass 21, count 0 2006.285.13:25:14.45#ibcon#about to read 4, iclass 21, count 0 2006.285.13:25:14.45#ibcon#read 4, iclass 21, count 0 2006.285.13:25:14.45#ibcon#about to read 5, iclass 21, count 0 2006.285.13:25:14.45#ibcon#read 5, iclass 21, count 0 2006.285.13:25:14.45#ibcon#about to read 6, iclass 21, count 0 2006.285.13:25:14.45#ibcon#read 6, iclass 21, count 0 2006.285.13:25:14.45#ibcon#end of sib2, iclass 21, count 0 2006.285.13:25:14.45#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:25:14.45#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:25:14.45#ibcon#[27=USB\r\n] 2006.285.13:25:14.45#ibcon#*before write, iclass 21, count 0 2006.285.13:25:14.45#ibcon#enter sib2, iclass 21, count 0 2006.285.13:25:14.45#ibcon#flushed, iclass 21, count 0 2006.285.13:25:14.45#ibcon#about to write, iclass 21, count 0 2006.285.13:25:14.45#ibcon#wrote, iclass 21, count 0 2006.285.13:25:14.45#ibcon#about to read 3, iclass 21, count 0 2006.285.13:25:14.48#ibcon#read 3, iclass 21, count 0 2006.285.13:25:14.48#ibcon#about to read 4, iclass 21, count 0 2006.285.13:25:14.48#ibcon#read 4, iclass 21, count 0 2006.285.13:25:14.48#ibcon#about to read 5, iclass 21, count 0 2006.285.13:25:14.48#ibcon#read 5, iclass 21, count 0 2006.285.13:25:14.48#ibcon#about to read 6, iclass 21, count 0 2006.285.13:25:14.48#ibcon#read 6, iclass 21, count 0 2006.285.13:25:14.48#ibcon#end of sib2, iclass 21, count 0 2006.285.13:25:14.48#ibcon#*after write, iclass 21, count 0 2006.285.13:25:14.48#ibcon#*before return 0, iclass 21, count 0 2006.285.13:25:14.48#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:25:14.48#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:25:14.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:25:14.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:25:14.48$vck44/vblo=3,649.99 2006.285.13:25:14.48#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.13:25:14.48#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.13:25:14.48#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:14.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:25:14.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:25:14.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:25:14.48#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:25:14.48#ibcon#first serial, iclass 23, count 0 2006.285.13:25:14.48#ibcon#enter sib2, iclass 23, count 0 2006.285.13:25:14.48#ibcon#flushed, iclass 23, count 0 2006.285.13:25:14.48#ibcon#about to write, iclass 23, count 0 2006.285.13:25:14.48#ibcon#wrote, iclass 23, count 0 2006.285.13:25:14.48#ibcon#about to read 3, iclass 23, count 0 2006.285.13:25:14.50#ibcon#read 3, iclass 23, count 0 2006.285.13:25:14.50#ibcon#about to read 4, iclass 23, count 0 2006.285.13:25:14.50#ibcon#read 4, iclass 23, count 0 2006.285.13:25:14.50#ibcon#about to read 5, iclass 23, count 0 2006.285.13:25:14.50#ibcon#read 5, iclass 23, count 0 2006.285.13:25:14.50#ibcon#about to read 6, iclass 23, count 0 2006.285.13:25:14.50#ibcon#read 6, iclass 23, count 0 2006.285.13:25:14.50#ibcon#end of sib2, iclass 23, count 0 2006.285.13:25:14.50#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:25:14.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:25:14.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:25:14.50#ibcon#*before write, iclass 23, count 0 2006.285.13:25:14.50#ibcon#enter sib2, iclass 23, count 0 2006.285.13:25:14.50#ibcon#flushed, iclass 23, count 0 2006.285.13:25:14.50#ibcon#about to write, iclass 23, count 0 2006.285.13:25:14.50#ibcon#wrote, iclass 23, count 0 2006.285.13:25:14.50#ibcon#about to read 3, iclass 23, count 0 2006.285.13:25:14.54#ibcon#read 3, iclass 23, count 0 2006.285.13:25:14.54#ibcon#about to read 4, iclass 23, count 0 2006.285.13:25:14.54#ibcon#read 4, iclass 23, count 0 2006.285.13:25:14.54#ibcon#about to read 5, iclass 23, count 0 2006.285.13:25:14.54#ibcon#read 5, iclass 23, count 0 2006.285.13:25:14.54#ibcon#about to read 6, iclass 23, count 0 2006.285.13:25:14.54#ibcon#read 6, iclass 23, count 0 2006.285.13:25:14.54#ibcon#end of sib2, iclass 23, count 0 2006.285.13:25:14.54#ibcon#*after write, iclass 23, count 0 2006.285.13:25:14.54#ibcon#*before return 0, iclass 23, count 0 2006.285.13:25:14.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:25:14.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:25:14.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:25:14.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:25:14.54$vck44/vb=3,4 2006.285.13:25:14.54#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.13:25:14.54#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.13:25:14.54#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:14.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:25:14.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:25:14.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:25:14.60#ibcon#enter wrdev, iclass 25, count 2 2006.285.13:25:14.60#ibcon#first serial, iclass 25, count 2 2006.285.13:25:14.60#ibcon#enter sib2, iclass 25, count 2 2006.285.13:25:14.60#ibcon#flushed, iclass 25, count 2 2006.285.13:25:14.60#ibcon#about to write, iclass 25, count 2 2006.285.13:25:14.60#ibcon#wrote, iclass 25, count 2 2006.285.13:25:14.60#ibcon#about to read 3, iclass 25, count 2 2006.285.13:25:14.62#ibcon#read 3, iclass 25, count 2 2006.285.13:25:14.62#ibcon#about to read 4, iclass 25, count 2 2006.285.13:25:14.62#ibcon#read 4, iclass 25, count 2 2006.285.13:25:14.62#ibcon#about to read 5, iclass 25, count 2 2006.285.13:25:14.62#ibcon#read 5, iclass 25, count 2 2006.285.13:25:14.62#ibcon#about to read 6, iclass 25, count 2 2006.285.13:25:14.62#ibcon#read 6, iclass 25, count 2 2006.285.13:25:14.62#ibcon#end of sib2, iclass 25, count 2 2006.285.13:25:14.62#ibcon#*mode == 0, iclass 25, count 2 2006.285.13:25:14.62#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.13:25:14.62#ibcon#[27=AT03-04\r\n] 2006.285.13:25:14.62#ibcon#*before write, iclass 25, count 2 2006.285.13:25:14.62#ibcon#enter sib2, iclass 25, count 2 2006.285.13:25:14.62#ibcon#flushed, iclass 25, count 2 2006.285.13:25:14.62#ibcon#about to write, iclass 25, count 2 2006.285.13:25:14.62#ibcon#wrote, iclass 25, count 2 2006.285.13:25:14.62#ibcon#about to read 3, iclass 25, count 2 2006.285.13:25:14.65#ibcon#read 3, iclass 25, count 2 2006.285.13:25:14.65#ibcon#about to read 4, iclass 25, count 2 2006.285.13:25:14.65#ibcon#read 4, iclass 25, count 2 2006.285.13:25:14.65#ibcon#about to read 5, iclass 25, count 2 2006.285.13:25:14.65#ibcon#read 5, iclass 25, count 2 2006.285.13:25:14.65#ibcon#about to read 6, iclass 25, count 2 2006.285.13:25:14.65#ibcon#read 6, iclass 25, count 2 2006.285.13:25:14.65#ibcon#end of sib2, iclass 25, count 2 2006.285.13:25:14.65#ibcon#*after write, iclass 25, count 2 2006.285.13:25:14.65#ibcon#*before return 0, iclass 25, count 2 2006.285.13:25:14.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:25:14.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:25:14.65#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.13:25:14.65#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:14.65#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:25:14.77#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:25:14.77#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:25:14.77#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:25:14.77#ibcon#first serial, iclass 25, count 0 2006.285.13:25:14.77#ibcon#enter sib2, iclass 25, count 0 2006.285.13:25:14.77#ibcon#flushed, iclass 25, count 0 2006.285.13:25:14.77#ibcon#about to write, iclass 25, count 0 2006.285.13:25:14.77#ibcon#wrote, iclass 25, count 0 2006.285.13:25:14.77#ibcon#about to read 3, iclass 25, count 0 2006.285.13:25:14.79#ibcon#read 3, iclass 25, count 0 2006.285.13:25:14.79#ibcon#about to read 4, iclass 25, count 0 2006.285.13:25:14.79#ibcon#read 4, iclass 25, count 0 2006.285.13:25:14.79#ibcon#about to read 5, iclass 25, count 0 2006.285.13:25:14.79#ibcon#read 5, iclass 25, count 0 2006.285.13:25:14.79#ibcon#about to read 6, iclass 25, count 0 2006.285.13:25:14.79#ibcon#read 6, iclass 25, count 0 2006.285.13:25:14.79#ibcon#end of sib2, iclass 25, count 0 2006.285.13:25:14.79#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:25:14.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:25:14.79#ibcon#[27=USB\r\n] 2006.285.13:25:14.79#ibcon#*before write, iclass 25, count 0 2006.285.13:25:14.79#ibcon#enter sib2, iclass 25, count 0 2006.285.13:25:14.79#ibcon#flushed, iclass 25, count 0 2006.285.13:25:14.79#ibcon#about to write, iclass 25, count 0 2006.285.13:25:14.79#ibcon#wrote, iclass 25, count 0 2006.285.13:25:14.79#ibcon#about to read 3, iclass 25, count 0 2006.285.13:25:14.82#ibcon#read 3, iclass 25, count 0 2006.285.13:25:14.82#ibcon#about to read 4, iclass 25, count 0 2006.285.13:25:14.82#ibcon#read 4, iclass 25, count 0 2006.285.13:25:14.82#ibcon#about to read 5, iclass 25, count 0 2006.285.13:25:14.82#ibcon#read 5, iclass 25, count 0 2006.285.13:25:14.82#ibcon#about to read 6, iclass 25, count 0 2006.285.13:25:14.82#ibcon#read 6, iclass 25, count 0 2006.285.13:25:14.82#ibcon#end of sib2, iclass 25, count 0 2006.285.13:25:14.82#ibcon#*after write, iclass 25, count 0 2006.285.13:25:14.82#ibcon#*before return 0, iclass 25, count 0 2006.285.13:25:14.82#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:25:14.82#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:25:14.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:25:14.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:25:14.82$vck44/vblo=4,679.99 2006.285.13:25:14.82#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.13:25:14.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.13:25:14.82#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:14.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:25:14.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:25:14.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:25:14.82#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:25:14.82#ibcon#first serial, iclass 27, count 0 2006.285.13:25:14.82#ibcon#enter sib2, iclass 27, count 0 2006.285.13:25:14.82#ibcon#flushed, iclass 27, count 0 2006.285.13:25:14.82#ibcon#about to write, iclass 27, count 0 2006.285.13:25:14.82#ibcon#wrote, iclass 27, count 0 2006.285.13:25:14.82#ibcon#about to read 3, iclass 27, count 0 2006.285.13:25:14.84#ibcon#read 3, iclass 27, count 0 2006.285.13:25:14.84#ibcon#about to read 4, iclass 27, count 0 2006.285.13:25:14.84#ibcon#read 4, iclass 27, count 0 2006.285.13:25:14.84#ibcon#about to read 5, iclass 27, count 0 2006.285.13:25:14.84#ibcon#read 5, iclass 27, count 0 2006.285.13:25:14.84#ibcon#about to read 6, iclass 27, count 0 2006.285.13:25:14.84#ibcon#read 6, iclass 27, count 0 2006.285.13:25:14.84#ibcon#end of sib2, iclass 27, count 0 2006.285.13:25:14.84#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:25:14.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:25:14.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:25:14.84#ibcon#*before write, iclass 27, count 0 2006.285.13:25:14.84#ibcon#enter sib2, iclass 27, count 0 2006.285.13:25:14.84#ibcon#flushed, iclass 27, count 0 2006.285.13:25:14.84#ibcon#about to write, iclass 27, count 0 2006.285.13:25:14.84#ibcon#wrote, iclass 27, count 0 2006.285.13:25:14.84#ibcon#about to read 3, iclass 27, count 0 2006.285.13:25:14.88#ibcon#read 3, iclass 27, count 0 2006.285.13:25:14.88#ibcon#about to read 4, iclass 27, count 0 2006.285.13:25:14.88#ibcon#read 4, iclass 27, count 0 2006.285.13:25:14.88#ibcon#about to read 5, iclass 27, count 0 2006.285.13:25:14.88#ibcon#read 5, iclass 27, count 0 2006.285.13:25:14.88#ibcon#about to read 6, iclass 27, count 0 2006.285.13:25:14.88#ibcon#read 6, iclass 27, count 0 2006.285.13:25:14.88#ibcon#end of sib2, iclass 27, count 0 2006.285.13:25:14.88#ibcon#*after write, iclass 27, count 0 2006.285.13:25:14.88#ibcon#*before return 0, iclass 27, count 0 2006.285.13:25:14.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:25:14.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:25:14.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:25:14.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:25:14.88$vck44/vb=4,5 2006.285.13:25:14.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.13:25:14.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.13:25:14.88#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:14.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:25:14.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:25:14.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:25:14.94#ibcon#enter wrdev, iclass 29, count 2 2006.285.13:25:14.94#ibcon#first serial, iclass 29, count 2 2006.285.13:25:14.94#ibcon#enter sib2, iclass 29, count 2 2006.285.13:25:14.94#ibcon#flushed, iclass 29, count 2 2006.285.13:25:14.94#ibcon#about to write, iclass 29, count 2 2006.285.13:25:14.94#ibcon#wrote, iclass 29, count 2 2006.285.13:25:14.94#ibcon#about to read 3, iclass 29, count 2 2006.285.13:25:14.96#ibcon#read 3, iclass 29, count 2 2006.285.13:25:14.96#ibcon#about to read 4, iclass 29, count 2 2006.285.13:25:14.96#ibcon#read 4, iclass 29, count 2 2006.285.13:25:14.96#ibcon#about to read 5, iclass 29, count 2 2006.285.13:25:14.96#ibcon#read 5, iclass 29, count 2 2006.285.13:25:14.96#ibcon#about to read 6, iclass 29, count 2 2006.285.13:25:14.96#ibcon#read 6, iclass 29, count 2 2006.285.13:25:14.96#ibcon#end of sib2, iclass 29, count 2 2006.285.13:25:14.96#ibcon#*mode == 0, iclass 29, count 2 2006.285.13:25:14.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.13:25:14.96#ibcon#[27=AT04-05\r\n] 2006.285.13:25:14.96#ibcon#*before write, iclass 29, count 2 2006.285.13:25:14.96#ibcon#enter sib2, iclass 29, count 2 2006.285.13:25:14.96#ibcon#flushed, iclass 29, count 2 2006.285.13:25:14.96#ibcon#about to write, iclass 29, count 2 2006.285.13:25:14.96#ibcon#wrote, iclass 29, count 2 2006.285.13:25:14.96#ibcon#about to read 3, iclass 29, count 2 2006.285.13:25:14.99#ibcon#read 3, iclass 29, count 2 2006.285.13:25:14.99#ibcon#about to read 4, iclass 29, count 2 2006.285.13:25:14.99#ibcon#read 4, iclass 29, count 2 2006.285.13:25:14.99#ibcon#about to read 5, iclass 29, count 2 2006.285.13:25:14.99#ibcon#read 5, iclass 29, count 2 2006.285.13:25:14.99#ibcon#about to read 6, iclass 29, count 2 2006.285.13:25:14.99#ibcon#read 6, iclass 29, count 2 2006.285.13:25:14.99#ibcon#end of sib2, iclass 29, count 2 2006.285.13:25:14.99#ibcon#*after write, iclass 29, count 2 2006.285.13:25:14.99#ibcon#*before return 0, iclass 29, count 2 2006.285.13:25:14.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:25:14.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:25:14.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.13:25:14.99#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:14.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:25:15.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:25:15.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:25:15.11#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:25:15.11#ibcon#first serial, iclass 29, count 0 2006.285.13:25:15.11#ibcon#enter sib2, iclass 29, count 0 2006.285.13:25:15.11#ibcon#flushed, iclass 29, count 0 2006.285.13:25:15.11#ibcon#about to write, iclass 29, count 0 2006.285.13:25:15.11#ibcon#wrote, iclass 29, count 0 2006.285.13:25:15.11#ibcon#about to read 3, iclass 29, count 0 2006.285.13:25:15.13#ibcon#read 3, iclass 29, count 0 2006.285.13:25:15.13#ibcon#about to read 4, iclass 29, count 0 2006.285.13:25:15.13#ibcon#read 4, iclass 29, count 0 2006.285.13:25:15.13#ibcon#about to read 5, iclass 29, count 0 2006.285.13:25:15.13#ibcon#read 5, iclass 29, count 0 2006.285.13:25:15.13#ibcon#about to read 6, iclass 29, count 0 2006.285.13:25:15.13#ibcon#read 6, iclass 29, count 0 2006.285.13:25:15.13#ibcon#end of sib2, iclass 29, count 0 2006.285.13:25:15.13#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:25:15.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:25:15.13#ibcon#[27=USB\r\n] 2006.285.13:25:15.13#ibcon#*before write, iclass 29, count 0 2006.285.13:25:15.13#ibcon#enter sib2, iclass 29, count 0 2006.285.13:25:15.13#ibcon#flushed, iclass 29, count 0 2006.285.13:25:15.13#ibcon#about to write, iclass 29, count 0 2006.285.13:25:15.13#ibcon#wrote, iclass 29, count 0 2006.285.13:25:15.13#ibcon#about to read 3, iclass 29, count 0 2006.285.13:25:15.16#ibcon#read 3, iclass 29, count 0 2006.285.13:25:15.16#ibcon#about to read 4, iclass 29, count 0 2006.285.13:25:15.16#ibcon#read 4, iclass 29, count 0 2006.285.13:25:15.16#ibcon#about to read 5, iclass 29, count 0 2006.285.13:25:15.16#ibcon#read 5, iclass 29, count 0 2006.285.13:25:15.16#ibcon#about to read 6, iclass 29, count 0 2006.285.13:25:15.16#ibcon#read 6, iclass 29, count 0 2006.285.13:25:15.16#ibcon#end of sib2, iclass 29, count 0 2006.285.13:25:15.16#ibcon#*after write, iclass 29, count 0 2006.285.13:25:15.16#ibcon#*before return 0, iclass 29, count 0 2006.285.13:25:15.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:25:15.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:25:15.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:25:15.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:25:15.16$vck44/vblo=5,709.99 2006.285.13:25:15.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.13:25:15.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.13:25:15.16#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:15.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:25:15.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:25:15.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:25:15.16#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:25:15.16#ibcon#first serial, iclass 31, count 0 2006.285.13:25:15.16#ibcon#enter sib2, iclass 31, count 0 2006.285.13:25:15.16#ibcon#flushed, iclass 31, count 0 2006.285.13:25:15.16#ibcon#about to write, iclass 31, count 0 2006.285.13:25:15.16#ibcon#wrote, iclass 31, count 0 2006.285.13:25:15.16#ibcon#about to read 3, iclass 31, count 0 2006.285.13:25:15.18#ibcon#read 3, iclass 31, count 0 2006.285.13:25:15.19#ibcon#about to read 4, iclass 31, count 0 2006.285.13:25:15.19#ibcon#read 4, iclass 31, count 0 2006.285.13:25:15.19#ibcon#about to read 5, iclass 31, count 0 2006.285.13:25:15.19#ibcon#read 5, iclass 31, count 0 2006.285.13:25:15.19#ibcon#about to read 6, iclass 31, count 0 2006.285.13:25:15.19#ibcon#read 6, iclass 31, count 0 2006.285.13:25:15.19#ibcon#end of sib2, iclass 31, count 0 2006.285.13:25:15.19#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:25:15.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:25:15.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:25:15.19#ibcon#*before write, iclass 31, count 0 2006.285.13:25:15.19#ibcon#enter sib2, iclass 31, count 0 2006.285.13:25:15.19#ibcon#flushed, iclass 31, count 0 2006.285.13:25:15.19#ibcon#about to write, iclass 31, count 0 2006.285.13:25:15.19#ibcon#wrote, iclass 31, count 0 2006.285.13:25:15.19#ibcon#about to read 3, iclass 31, count 0 2006.285.13:25:15.23#ibcon#read 3, iclass 31, count 0 2006.285.13:25:15.23#ibcon#about to read 4, iclass 31, count 0 2006.285.13:25:15.23#ibcon#read 4, iclass 31, count 0 2006.285.13:25:15.23#ibcon#about to read 5, iclass 31, count 0 2006.285.13:25:15.23#ibcon#read 5, iclass 31, count 0 2006.285.13:25:15.23#ibcon#about to read 6, iclass 31, count 0 2006.285.13:25:15.23#ibcon#read 6, iclass 31, count 0 2006.285.13:25:15.23#ibcon#end of sib2, iclass 31, count 0 2006.285.13:25:15.23#ibcon#*after write, iclass 31, count 0 2006.285.13:25:15.23#ibcon#*before return 0, iclass 31, count 0 2006.285.13:25:15.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:25:15.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:25:15.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:25:15.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:25:15.23$vck44/vb=5,4 2006.285.13:25:15.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.13:25:15.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.13:25:15.23#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:15.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:25:15.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:25:15.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:25:15.28#ibcon#enter wrdev, iclass 33, count 2 2006.285.13:25:15.28#ibcon#first serial, iclass 33, count 2 2006.285.13:25:15.28#ibcon#enter sib2, iclass 33, count 2 2006.285.13:25:15.28#ibcon#flushed, iclass 33, count 2 2006.285.13:25:15.28#ibcon#about to write, iclass 33, count 2 2006.285.13:25:15.28#ibcon#wrote, iclass 33, count 2 2006.285.13:25:15.28#ibcon#about to read 3, iclass 33, count 2 2006.285.13:25:15.30#ibcon#read 3, iclass 33, count 2 2006.285.13:25:15.30#ibcon#about to read 4, iclass 33, count 2 2006.285.13:25:15.30#ibcon#read 4, iclass 33, count 2 2006.285.13:25:15.30#ibcon#about to read 5, iclass 33, count 2 2006.285.13:25:15.30#ibcon#read 5, iclass 33, count 2 2006.285.13:25:15.30#ibcon#about to read 6, iclass 33, count 2 2006.285.13:25:15.30#ibcon#read 6, iclass 33, count 2 2006.285.13:25:15.30#ibcon#end of sib2, iclass 33, count 2 2006.285.13:25:15.30#ibcon#*mode == 0, iclass 33, count 2 2006.285.13:25:15.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.13:25:15.30#ibcon#[27=AT05-04\r\n] 2006.285.13:25:15.30#ibcon#*before write, iclass 33, count 2 2006.285.13:25:15.30#ibcon#enter sib2, iclass 33, count 2 2006.285.13:25:15.30#ibcon#flushed, iclass 33, count 2 2006.285.13:25:15.30#ibcon#about to write, iclass 33, count 2 2006.285.13:25:15.30#ibcon#wrote, iclass 33, count 2 2006.285.13:25:15.30#ibcon#about to read 3, iclass 33, count 2 2006.285.13:25:15.33#ibcon#read 3, iclass 33, count 2 2006.285.13:25:15.33#ibcon#about to read 4, iclass 33, count 2 2006.285.13:25:15.33#ibcon#read 4, iclass 33, count 2 2006.285.13:25:15.33#ibcon#about to read 5, iclass 33, count 2 2006.285.13:25:15.33#ibcon#read 5, iclass 33, count 2 2006.285.13:25:15.33#ibcon#about to read 6, iclass 33, count 2 2006.285.13:25:15.33#ibcon#read 6, iclass 33, count 2 2006.285.13:25:15.33#ibcon#end of sib2, iclass 33, count 2 2006.285.13:25:15.33#ibcon#*after write, iclass 33, count 2 2006.285.13:25:15.33#ibcon#*before return 0, iclass 33, count 2 2006.285.13:25:15.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:25:15.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:25:15.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.13:25:15.33#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:15.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:25:15.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:25:15.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:25:15.45#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:25:15.45#ibcon#first serial, iclass 33, count 0 2006.285.13:25:15.45#ibcon#enter sib2, iclass 33, count 0 2006.285.13:25:15.45#ibcon#flushed, iclass 33, count 0 2006.285.13:25:15.45#ibcon#about to write, iclass 33, count 0 2006.285.13:25:15.45#ibcon#wrote, iclass 33, count 0 2006.285.13:25:15.45#ibcon#about to read 3, iclass 33, count 0 2006.285.13:25:15.47#ibcon#read 3, iclass 33, count 0 2006.285.13:25:15.47#ibcon#about to read 4, iclass 33, count 0 2006.285.13:25:15.47#ibcon#read 4, iclass 33, count 0 2006.285.13:25:15.47#ibcon#about to read 5, iclass 33, count 0 2006.285.13:25:15.47#ibcon#read 5, iclass 33, count 0 2006.285.13:25:15.47#ibcon#about to read 6, iclass 33, count 0 2006.285.13:25:15.47#ibcon#read 6, iclass 33, count 0 2006.285.13:25:15.47#ibcon#end of sib2, iclass 33, count 0 2006.285.13:25:15.47#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:25:15.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:25:15.47#ibcon#[27=USB\r\n] 2006.285.13:25:15.47#ibcon#*before write, iclass 33, count 0 2006.285.13:25:15.47#ibcon#enter sib2, iclass 33, count 0 2006.285.13:25:15.47#ibcon#flushed, iclass 33, count 0 2006.285.13:25:15.47#ibcon#about to write, iclass 33, count 0 2006.285.13:25:15.47#ibcon#wrote, iclass 33, count 0 2006.285.13:25:15.47#ibcon#about to read 3, iclass 33, count 0 2006.285.13:25:15.50#ibcon#read 3, iclass 33, count 0 2006.285.13:25:15.50#ibcon#about to read 4, iclass 33, count 0 2006.285.13:25:15.50#ibcon#read 4, iclass 33, count 0 2006.285.13:25:15.50#ibcon#about to read 5, iclass 33, count 0 2006.285.13:25:15.50#ibcon#read 5, iclass 33, count 0 2006.285.13:25:15.50#ibcon#about to read 6, iclass 33, count 0 2006.285.13:25:15.50#ibcon#read 6, iclass 33, count 0 2006.285.13:25:15.50#ibcon#end of sib2, iclass 33, count 0 2006.285.13:25:15.50#ibcon#*after write, iclass 33, count 0 2006.285.13:25:15.50#ibcon#*before return 0, iclass 33, count 0 2006.285.13:25:15.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:25:15.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:25:15.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:25:15.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:25:15.50$vck44/vblo=6,719.99 2006.285.13:25:15.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.13:25:15.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.13:25:15.50#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:15.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:25:15.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:25:15.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:25:15.50#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:25:15.50#ibcon#first serial, iclass 35, count 0 2006.285.13:25:15.50#ibcon#enter sib2, iclass 35, count 0 2006.285.13:25:15.50#ibcon#flushed, iclass 35, count 0 2006.285.13:25:15.50#ibcon#about to write, iclass 35, count 0 2006.285.13:25:15.50#ibcon#wrote, iclass 35, count 0 2006.285.13:25:15.50#ibcon#about to read 3, iclass 35, count 0 2006.285.13:25:15.52#ibcon#read 3, iclass 35, count 0 2006.285.13:25:15.52#ibcon#about to read 4, iclass 35, count 0 2006.285.13:25:15.52#ibcon#read 4, iclass 35, count 0 2006.285.13:25:15.52#ibcon#about to read 5, iclass 35, count 0 2006.285.13:25:15.52#ibcon#read 5, iclass 35, count 0 2006.285.13:25:15.52#ibcon#about to read 6, iclass 35, count 0 2006.285.13:25:15.52#ibcon#read 6, iclass 35, count 0 2006.285.13:25:15.52#ibcon#end of sib2, iclass 35, count 0 2006.285.13:25:15.52#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:25:15.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:25:15.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:25:15.52#ibcon#*before write, iclass 35, count 0 2006.285.13:25:15.52#ibcon#enter sib2, iclass 35, count 0 2006.285.13:25:15.52#ibcon#flushed, iclass 35, count 0 2006.285.13:25:15.52#ibcon#about to write, iclass 35, count 0 2006.285.13:25:15.52#ibcon#wrote, iclass 35, count 0 2006.285.13:25:15.52#ibcon#about to read 3, iclass 35, count 0 2006.285.13:25:15.56#ibcon#read 3, iclass 35, count 0 2006.285.13:25:15.56#ibcon#about to read 4, iclass 35, count 0 2006.285.13:25:15.56#ibcon#read 4, iclass 35, count 0 2006.285.13:25:15.56#ibcon#about to read 5, iclass 35, count 0 2006.285.13:25:15.56#ibcon#read 5, iclass 35, count 0 2006.285.13:25:15.56#ibcon#about to read 6, iclass 35, count 0 2006.285.13:25:15.56#ibcon#read 6, iclass 35, count 0 2006.285.13:25:15.56#ibcon#end of sib2, iclass 35, count 0 2006.285.13:25:15.56#ibcon#*after write, iclass 35, count 0 2006.285.13:25:15.56#ibcon#*before return 0, iclass 35, count 0 2006.285.13:25:15.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:25:15.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:25:15.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:25:15.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:25:15.56$vck44/vb=6,3 2006.285.13:25:15.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.13:25:15.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.13:25:15.56#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:15.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:25:15.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:25:15.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:25:15.62#ibcon#enter wrdev, iclass 37, count 2 2006.285.13:25:15.62#ibcon#first serial, iclass 37, count 2 2006.285.13:25:15.62#ibcon#enter sib2, iclass 37, count 2 2006.285.13:25:15.62#ibcon#flushed, iclass 37, count 2 2006.285.13:25:15.62#ibcon#about to write, iclass 37, count 2 2006.285.13:25:15.62#ibcon#wrote, iclass 37, count 2 2006.285.13:25:15.62#ibcon#about to read 3, iclass 37, count 2 2006.285.13:25:15.64#ibcon#read 3, iclass 37, count 2 2006.285.13:25:15.64#ibcon#about to read 4, iclass 37, count 2 2006.285.13:25:15.64#ibcon#read 4, iclass 37, count 2 2006.285.13:25:15.64#ibcon#about to read 5, iclass 37, count 2 2006.285.13:25:15.64#ibcon#read 5, iclass 37, count 2 2006.285.13:25:15.64#ibcon#about to read 6, iclass 37, count 2 2006.285.13:25:15.64#ibcon#read 6, iclass 37, count 2 2006.285.13:25:15.64#ibcon#end of sib2, iclass 37, count 2 2006.285.13:25:15.64#ibcon#*mode == 0, iclass 37, count 2 2006.285.13:25:15.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.13:25:15.64#ibcon#[27=AT06-03\r\n] 2006.285.13:25:15.64#ibcon#*before write, iclass 37, count 2 2006.285.13:25:15.64#ibcon#enter sib2, iclass 37, count 2 2006.285.13:25:15.64#ibcon#flushed, iclass 37, count 2 2006.285.13:25:15.64#ibcon#about to write, iclass 37, count 2 2006.285.13:25:15.64#ibcon#wrote, iclass 37, count 2 2006.285.13:25:15.64#ibcon#about to read 3, iclass 37, count 2 2006.285.13:25:15.67#ibcon#read 3, iclass 37, count 2 2006.285.13:25:15.67#ibcon#about to read 4, iclass 37, count 2 2006.285.13:25:15.67#ibcon#read 4, iclass 37, count 2 2006.285.13:25:15.67#ibcon#about to read 5, iclass 37, count 2 2006.285.13:25:15.67#ibcon#read 5, iclass 37, count 2 2006.285.13:25:15.67#ibcon#about to read 6, iclass 37, count 2 2006.285.13:25:15.67#ibcon#read 6, iclass 37, count 2 2006.285.13:25:15.67#ibcon#end of sib2, iclass 37, count 2 2006.285.13:25:15.67#ibcon#*after write, iclass 37, count 2 2006.285.13:25:15.67#ibcon#*before return 0, iclass 37, count 2 2006.285.13:25:15.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:25:15.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:25:15.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.13:25:15.67#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:15.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:25:15.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:25:15.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:25:15.79#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:25:15.79#ibcon#first serial, iclass 37, count 0 2006.285.13:25:15.79#ibcon#enter sib2, iclass 37, count 0 2006.285.13:25:15.79#ibcon#flushed, iclass 37, count 0 2006.285.13:25:15.79#ibcon#about to write, iclass 37, count 0 2006.285.13:25:15.79#ibcon#wrote, iclass 37, count 0 2006.285.13:25:15.79#ibcon#about to read 3, iclass 37, count 0 2006.285.13:25:15.81#ibcon#read 3, iclass 37, count 0 2006.285.13:25:15.81#ibcon#about to read 4, iclass 37, count 0 2006.285.13:25:15.81#ibcon#read 4, iclass 37, count 0 2006.285.13:25:15.81#ibcon#about to read 5, iclass 37, count 0 2006.285.13:25:15.81#ibcon#read 5, iclass 37, count 0 2006.285.13:25:15.81#ibcon#about to read 6, iclass 37, count 0 2006.285.13:25:15.81#ibcon#read 6, iclass 37, count 0 2006.285.13:25:15.81#ibcon#end of sib2, iclass 37, count 0 2006.285.13:25:15.81#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:25:15.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:25:15.81#ibcon#[27=USB\r\n] 2006.285.13:25:15.81#ibcon#*before write, iclass 37, count 0 2006.285.13:25:15.81#ibcon#enter sib2, iclass 37, count 0 2006.285.13:25:15.81#ibcon#flushed, iclass 37, count 0 2006.285.13:25:15.81#ibcon#about to write, iclass 37, count 0 2006.285.13:25:15.81#ibcon#wrote, iclass 37, count 0 2006.285.13:25:15.81#ibcon#about to read 3, iclass 37, count 0 2006.285.13:25:15.84#ibcon#read 3, iclass 37, count 0 2006.285.13:25:15.84#ibcon#about to read 4, iclass 37, count 0 2006.285.13:25:15.84#ibcon#read 4, iclass 37, count 0 2006.285.13:25:15.84#ibcon#about to read 5, iclass 37, count 0 2006.285.13:25:15.84#ibcon#read 5, iclass 37, count 0 2006.285.13:25:15.84#ibcon#about to read 6, iclass 37, count 0 2006.285.13:25:15.84#ibcon#read 6, iclass 37, count 0 2006.285.13:25:15.84#ibcon#end of sib2, iclass 37, count 0 2006.285.13:25:15.84#ibcon#*after write, iclass 37, count 0 2006.285.13:25:15.84#ibcon#*before return 0, iclass 37, count 0 2006.285.13:25:15.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:25:15.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:25:15.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:25:15.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:25:15.84$vck44/vblo=7,734.99 2006.285.13:25:15.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.13:25:15.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.13:25:15.84#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:15.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:25:15.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:25:15.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:25:15.84#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:25:15.84#ibcon#first serial, iclass 39, count 0 2006.285.13:25:15.84#ibcon#enter sib2, iclass 39, count 0 2006.285.13:25:15.84#ibcon#flushed, iclass 39, count 0 2006.285.13:25:15.84#ibcon#about to write, iclass 39, count 0 2006.285.13:25:15.84#ibcon#wrote, iclass 39, count 0 2006.285.13:25:15.84#ibcon#about to read 3, iclass 39, count 0 2006.285.13:25:15.86#ibcon#read 3, iclass 39, count 0 2006.285.13:25:15.86#ibcon#about to read 4, iclass 39, count 0 2006.285.13:25:15.86#ibcon#read 4, iclass 39, count 0 2006.285.13:25:15.86#ibcon#about to read 5, iclass 39, count 0 2006.285.13:25:15.86#ibcon#read 5, iclass 39, count 0 2006.285.13:25:15.86#ibcon#about to read 6, iclass 39, count 0 2006.285.13:25:15.86#ibcon#read 6, iclass 39, count 0 2006.285.13:25:15.86#ibcon#end of sib2, iclass 39, count 0 2006.285.13:25:15.86#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:25:15.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:25:15.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:25:15.86#ibcon#*before write, iclass 39, count 0 2006.285.13:25:15.86#ibcon#enter sib2, iclass 39, count 0 2006.285.13:25:15.86#ibcon#flushed, iclass 39, count 0 2006.285.13:25:15.86#ibcon#about to write, iclass 39, count 0 2006.285.13:25:15.86#ibcon#wrote, iclass 39, count 0 2006.285.13:25:15.86#ibcon#about to read 3, iclass 39, count 0 2006.285.13:25:15.90#ibcon#read 3, iclass 39, count 0 2006.285.13:25:15.90#ibcon#about to read 4, iclass 39, count 0 2006.285.13:25:15.90#ibcon#read 4, iclass 39, count 0 2006.285.13:25:15.90#ibcon#about to read 5, iclass 39, count 0 2006.285.13:25:15.90#ibcon#read 5, iclass 39, count 0 2006.285.13:25:15.90#ibcon#about to read 6, iclass 39, count 0 2006.285.13:25:15.90#ibcon#read 6, iclass 39, count 0 2006.285.13:25:15.90#ibcon#end of sib2, iclass 39, count 0 2006.285.13:25:15.90#ibcon#*after write, iclass 39, count 0 2006.285.13:25:15.90#ibcon#*before return 0, iclass 39, count 0 2006.285.13:25:15.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:25:15.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:25:15.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:25:15.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:25:15.90$vck44/vb=7,4 2006.285.13:25:15.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.13:25:15.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.13:25:15.90#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:15.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:25:15.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:25:15.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:25:15.96#ibcon#enter wrdev, iclass 3, count 2 2006.285.13:25:15.96#ibcon#first serial, iclass 3, count 2 2006.285.13:25:15.96#ibcon#enter sib2, iclass 3, count 2 2006.285.13:25:15.96#ibcon#flushed, iclass 3, count 2 2006.285.13:25:15.96#ibcon#about to write, iclass 3, count 2 2006.285.13:25:15.96#ibcon#wrote, iclass 3, count 2 2006.285.13:25:15.96#ibcon#about to read 3, iclass 3, count 2 2006.285.13:25:15.98#ibcon#read 3, iclass 3, count 2 2006.285.13:25:15.98#ibcon#about to read 4, iclass 3, count 2 2006.285.13:25:15.98#ibcon#read 4, iclass 3, count 2 2006.285.13:25:15.98#ibcon#about to read 5, iclass 3, count 2 2006.285.13:25:15.98#ibcon#read 5, iclass 3, count 2 2006.285.13:25:15.98#ibcon#about to read 6, iclass 3, count 2 2006.285.13:25:15.98#ibcon#read 6, iclass 3, count 2 2006.285.13:25:15.98#ibcon#end of sib2, iclass 3, count 2 2006.285.13:25:15.98#ibcon#*mode == 0, iclass 3, count 2 2006.285.13:25:15.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.13:25:15.98#ibcon#[27=AT07-04\r\n] 2006.285.13:25:15.98#ibcon#*before write, iclass 3, count 2 2006.285.13:25:15.98#ibcon#enter sib2, iclass 3, count 2 2006.285.13:25:15.98#ibcon#flushed, iclass 3, count 2 2006.285.13:25:15.98#ibcon#about to write, iclass 3, count 2 2006.285.13:25:15.98#ibcon#wrote, iclass 3, count 2 2006.285.13:25:15.98#ibcon#about to read 3, iclass 3, count 2 2006.285.13:25:16.01#ibcon#read 3, iclass 3, count 2 2006.285.13:25:16.01#ibcon#about to read 4, iclass 3, count 2 2006.285.13:25:16.01#ibcon#read 4, iclass 3, count 2 2006.285.13:25:16.01#ibcon#about to read 5, iclass 3, count 2 2006.285.13:25:16.01#ibcon#read 5, iclass 3, count 2 2006.285.13:25:16.01#ibcon#about to read 6, iclass 3, count 2 2006.285.13:25:16.01#ibcon#read 6, iclass 3, count 2 2006.285.13:25:16.01#ibcon#end of sib2, iclass 3, count 2 2006.285.13:25:16.01#ibcon#*after write, iclass 3, count 2 2006.285.13:25:16.01#ibcon#*before return 0, iclass 3, count 2 2006.285.13:25:16.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:25:16.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:25:16.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.13:25:16.01#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:16.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:25:16.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:25:16.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:25:16.13#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:25:16.13#ibcon#first serial, iclass 3, count 0 2006.285.13:25:16.13#ibcon#enter sib2, iclass 3, count 0 2006.285.13:25:16.13#ibcon#flushed, iclass 3, count 0 2006.285.13:25:16.13#ibcon#about to write, iclass 3, count 0 2006.285.13:25:16.13#ibcon#wrote, iclass 3, count 0 2006.285.13:25:16.13#ibcon#about to read 3, iclass 3, count 0 2006.285.13:25:16.15#ibcon#read 3, iclass 3, count 0 2006.285.13:25:16.15#ibcon#about to read 4, iclass 3, count 0 2006.285.13:25:16.15#ibcon#read 4, iclass 3, count 0 2006.285.13:25:16.15#ibcon#about to read 5, iclass 3, count 0 2006.285.13:25:16.15#ibcon#read 5, iclass 3, count 0 2006.285.13:25:16.15#ibcon#about to read 6, iclass 3, count 0 2006.285.13:25:16.15#ibcon#read 6, iclass 3, count 0 2006.285.13:25:16.15#ibcon#end of sib2, iclass 3, count 0 2006.285.13:25:16.15#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:25:16.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:25:16.15#ibcon#[27=USB\r\n] 2006.285.13:25:16.15#ibcon#*before write, iclass 3, count 0 2006.285.13:25:16.15#ibcon#enter sib2, iclass 3, count 0 2006.285.13:25:16.15#ibcon#flushed, iclass 3, count 0 2006.285.13:25:16.15#ibcon#about to write, iclass 3, count 0 2006.285.13:25:16.15#ibcon#wrote, iclass 3, count 0 2006.285.13:25:16.15#ibcon#about to read 3, iclass 3, count 0 2006.285.13:25:16.18#ibcon#read 3, iclass 3, count 0 2006.285.13:25:16.18#ibcon#about to read 4, iclass 3, count 0 2006.285.13:25:16.18#ibcon#read 4, iclass 3, count 0 2006.285.13:25:16.18#ibcon#about to read 5, iclass 3, count 0 2006.285.13:25:16.18#ibcon#read 5, iclass 3, count 0 2006.285.13:25:16.18#ibcon#about to read 6, iclass 3, count 0 2006.285.13:25:16.18#ibcon#read 6, iclass 3, count 0 2006.285.13:25:16.18#ibcon#end of sib2, iclass 3, count 0 2006.285.13:25:16.18#ibcon#*after write, iclass 3, count 0 2006.285.13:25:16.18#ibcon#*before return 0, iclass 3, count 0 2006.285.13:25:16.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:25:16.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:25:16.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:25:16.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:25:16.18$vck44/vblo=8,744.99 2006.285.13:25:16.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.13:25:16.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.13:25:16.18#ibcon#ireg 17 cls_cnt 0 2006.285.13:25:16.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:25:16.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:25:16.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:25:16.18#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:25:16.18#ibcon#first serial, iclass 5, count 0 2006.285.13:25:16.18#ibcon#enter sib2, iclass 5, count 0 2006.285.13:25:16.18#ibcon#flushed, iclass 5, count 0 2006.285.13:25:16.18#ibcon#about to write, iclass 5, count 0 2006.285.13:25:16.18#ibcon#wrote, iclass 5, count 0 2006.285.13:25:16.18#ibcon#about to read 3, iclass 5, count 0 2006.285.13:25:16.20#ibcon#read 3, iclass 5, count 0 2006.285.13:25:16.29#ibcon#about to read 4, iclass 5, count 0 2006.285.13:25:16.29#ibcon#read 4, iclass 5, count 0 2006.285.13:25:16.29#ibcon#about to read 5, iclass 5, count 0 2006.285.13:25:16.29#ibcon#read 5, iclass 5, count 0 2006.285.13:25:16.29#ibcon#about to read 6, iclass 5, count 0 2006.285.13:25:16.29#ibcon#read 6, iclass 5, count 0 2006.285.13:25:16.29#ibcon#end of sib2, iclass 5, count 0 2006.285.13:25:16.29#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:25:16.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:25:16.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:25:16.29#ibcon#*before write, iclass 5, count 0 2006.285.13:25:16.29#ibcon#enter sib2, iclass 5, count 0 2006.285.13:25:16.29#ibcon#flushed, iclass 5, count 0 2006.285.13:25:16.29#ibcon#about to write, iclass 5, count 0 2006.285.13:25:16.29#ibcon#wrote, iclass 5, count 0 2006.285.13:25:16.29#ibcon#about to read 3, iclass 5, count 0 2006.285.13:25:16.33#ibcon#read 3, iclass 5, count 0 2006.285.13:25:16.33#ibcon#about to read 4, iclass 5, count 0 2006.285.13:25:16.33#ibcon#read 4, iclass 5, count 0 2006.285.13:25:16.33#ibcon#about to read 5, iclass 5, count 0 2006.285.13:25:16.33#ibcon#read 5, iclass 5, count 0 2006.285.13:25:16.33#ibcon#about to read 6, iclass 5, count 0 2006.285.13:25:16.33#ibcon#read 6, iclass 5, count 0 2006.285.13:25:16.33#ibcon#end of sib2, iclass 5, count 0 2006.285.13:25:16.33#ibcon#*after write, iclass 5, count 0 2006.285.13:25:16.33#ibcon#*before return 0, iclass 5, count 0 2006.285.13:25:16.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:25:16.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:25:16.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:25:16.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:25:16.33$vck44/vb=8,4 2006.285.13:25:16.33#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.13:25:16.33#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.13:25:16.33#ibcon#ireg 11 cls_cnt 2 2006.285.13:25:16.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:25:16.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:25:16.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:25:16.33#ibcon#enter wrdev, iclass 7, count 2 2006.285.13:25:16.33#ibcon#first serial, iclass 7, count 2 2006.285.13:25:16.33#ibcon#enter sib2, iclass 7, count 2 2006.285.13:25:16.33#ibcon#flushed, iclass 7, count 2 2006.285.13:25:16.33#ibcon#about to write, iclass 7, count 2 2006.285.13:25:16.33#ibcon#wrote, iclass 7, count 2 2006.285.13:25:16.33#ibcon#about to read 3, iclass 7, count 2 2006.285.13:25:16.35#ibcon#read 3, iclass 7, count 2 2006.285.13:25:16.35#ibcon#about to read 4, iclass 7, count 2 2006.285.13:25:16.35#ibcon#read 4, iclass 7, count 2 2006.285.13:25:16.35#ibcon#about to read 5, iclass 7, count 2 2006.285.13:25:16.35#ibcon#read 5, iclass 7, count 2 2006.285.13:25:16.35#ibcon#about to read 6, iclass 7, count 2 2006.285.13:25:16.35#ibcon#read 6, iclass 7, count 2 2006.285.13:25:16.35#ibcon#end of sib2, iclass 7, count 2 2006.285.13:25:16.35#ibcon#*mode == 0, iclass 7, count 2 2006.285.13:25:16.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.13:25:16.35#ibcon#[27=AT08-04\r\n] 2006.285.13:25:16.35#ibcon#*before write, iclass 7, count 2 2006.285.13:25:16.35#ibcon#enter sib2, iclass 7, count 2 2006.285.13:25:16.35#ibcon#flushed, iclass 7, count 2 2006.285.13:25:16.35#ibcon#about to write, iclass 7, count 2 2006.285.13:25:16.35#ibcon#wrote, iclass 7, count 2 2006.285.13:25:16.35#ibcon#about to read 3, iclass 7, count 2 2006.285.13:25:16.38#ibcon#read 3, iclass 7, count 2 2006.285.13:25:16.38#ibcon#about to read 4, iclass 7, count 2 2006.285.13:25:16.38#ibcon#read 4, iclass 7, count 2 2006.285.13:25:16.38#ibcon#about to read 5, iclass 7, count 2 2006.285.13:25:16.38#ibcon#read 5, iclass 7, count 2 2006.285.13:25:16.38#ibcon#about to read 6, iclass 7, count 2 2006.285.13:25:16.38#ibcon#read 6, iclass 7, count 2 2006.285.13:25:16.38#ibcon#end of sib2, iclass 7, count 2 2006.285.13:25:16.38#ibcon#*after write, iclass 7, count 2 2006.285.13:25:16.38#ibcon#*before return 0, iclass 7, count 2 2006.285.13:25:16.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:25:16.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:25:16.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.13:25:16.38#ibcon#ireg 7 cls_cnt 0 2006.285.13:25:16.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:25:16.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:25:16.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:25:16.50#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:25:16.50#ibcon#first serial, iclass 7, count 0 2006.285.13:25:16.50#ibcon#enter sib2, iclass 7, count 0 2006.285.13:25:16.50#ibcon#flushed, iclass 7, count 0 2006.285.13:25:16.50#ibcon#about to write, iclass 7, count 0 2006.285.13:25:16.50#ibcon#wrote, iclass 7, count 0 2006.285.13:25:16.50#ibcon#about to read 3, iclass 7, count 0 2006.285.13:25:16.52#ibcon#read 3, iclass 7, count 0 2006.285.13:25:16.52#ibcon#about to read 4, iclass 7, count 0 2006.285.13:25:16.52#ibcon#read 4, iclass 7, count 0 2006.285.13:25:16.52#ibcon#about to read 5, iclass 7, count 0 2006.285.13:25:16.52#ibcon#read 5, iclass 7, count 0 2006.285.13:25:16.52#ibcon#about to read 6, iclass 7, count 0 2006.285.13:25:16.52#ibcon#read 6, iclass 7, count 0 2006.285.13:25:16.52#ibcon#end of sib2, iclass 7, count 0 2006.285.13:25:16.52#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:25:16.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:25:16.52#ibcon#[27=USB\r\n] 2006.285.13:25:16.52#ibcon#*before write, iclass 7, count 0 2006.285.13:25:16.52#ibcon#enter sib2, iclass 7, count 0 2006.285.13:25:16.52#ibcon#flushed, iclass 7, count 0 2006.285.13:25:16.52#ibcon#about to write, iclass 7, count 0 2006.285.13:25:16.52#ibcon#wrote, iclass 7, count 0 2006.285.13:25:16.52#ibcon#about to read 3, iclass 7, count 0 2006.285.13:25:16.55#ibcon#read 3, iclass 7, count 0 2006.285.13:25:16.55#ibcon#about to read 4, iclass 7, count 0 2006.285.13:25:16.55#ibcon#read 4, iclass 7, count 0 2006.285.13:25:16.55#ibcon#about to read 5, iclass 7, count 0 2006.285.13:25:16.55#ibcon#read 5, iclass 7, count 0 2006.285.13:25:16.55#ibcon#about to read 6, iclass 7, count 0 2006.285.13:25:16.55#ibcon#read 6, iclass 7, count 0 2006.285.13:25:16.55#ibcon#end of sib2, iclass 7, count 0 2006.285.13:25:16.55#ibcon#*after write, iclass 7, count 0 2006.285.13:25:16.55#ibcon#*before return 0, iclass 7, count 0 2006.285.13:25:16.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:25:16.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:25:16.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:25:16.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:25:16.55$vck44/vabw=wide 2006.285.13:25:16.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.13:25:16.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.13:25:16.55#ibcon#ireg 8 cls_cnt 0 2006.285.13:25:16.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:25:16.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:25:16.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:25:16.55#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:25:16.55#ibcon#first serial, iclass 11, count 0 2006.285.13:25:16.55#ibcon#enter sib2, iclass 11, count 0 2006.285.13:25:16.55#ibcon#flushed, iclass 11, count 0 2006.285.13:25:16.55#ibcon#about to write, iclass 11, count 0 2006.285.13:25:16.55#ibcon#wrote, iclass 11, count 0 2006.285.13:25:16.55#ibcon#about to read 3, iclass 11, count 0 2006.285.13:25:16.57#ibcon#read 3, iclass 11, count 0 2006.285.13:25:16.57#ibcon#about to read 4, iclass 11, count 0 2006.285.13:25:16.57#ibcon#read 4, iclass 11, count 0 2006.285.13:25:16.57#ibcon#about to read 5, iclass 11, count 0 2006.285.13:25:16.57#ibcon#read 5, iclass 11, count 0 2006.285.13:25:16.57#ibcon#about to read 6, iclass 11, count 0 2006.285.13:25:16.57#ibcon#read 6, iclass 11, count 0 2006.285.13:25:16.57#ibcon#end of sib2, iclass 11, count 0 2006.285.13:25:16.57#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:25:16.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:25:16.57#ibcon#[25=BW32\r\n] 2006.285.13:25:16.57#ibcon#*before write, iclass 11, count 0 2006.285.13:25:16.57#ibcon#enter sib2, iclass 11, count 0 2006.285.13:25:16.57#ibcon#flushed, iclass 11, count 0 2006.285.13:25:16.57#ibcon#about to write, iclass 11, count 0 2006.285.13:25:16.57#ibcon#wrote, iclass 11, count 0 2006.285.13:25:16.57#ibcon#about to read 3, iclass 11, count 0 2006.285.13:25:16.60#ibcon#read 3, iclass 11, count 0 2006.285.13:25:16.60#ibcon#about to read 4, iclass 11, count 0 2006.285.13:25:16.60#ibcon#read 4, iclass 11, count 0 2006.285.13:25:16.60#ibcon#about to read 5, iclass 11, count 0 2006.285.13:25:16.60#ibcon#read 5, iclass 11, count 0 2006.285.13:25:16.60#ibcon#about to read 6, iclass 11, count 0 2006.285.13:25:16.60#ibcon#read 6, iclass 11, count 0 2006.285.13:25:16.60#ibcon#end of sib2, iclass 11, count 0 2006.285.13:25:16.60#ibcon#*after write, iclass 11, count 0 2006.285.13:25:16.60#ibcon#*before return 0, iclass 11, count 0 2006.285.13:25:16.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:25:16.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:25:16.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:25:16.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:25:16.60$vck44/vbbw=wide 2006.285.13:25:16.60#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.13:25:16.60#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.13:25:16.60#ibcon#ireg 8 cls_cnt 0 2006.285.13:25:16.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:25:16.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:25:16.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:25:16.67#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:25:16.67#ibcon#first serial, iclass 13, count 0 2006.285.13:25:16.67#ibcon#enter sib2, iclass 13, count 0 2006.285.13:25:16.67#ibcon#flushed, iclass 13, count 0 2006.285.13:25:16.67#ibcon#about to write, iclass 13, count 0 2006.285.13:25:16.67#ibcon#wrote, iclass 13, count 0 2006.285.13:25:16.67#ibcon#about to read 3, iclass 13, count 0 2006.285.13:25:16.69#ibcon#read 3, iclass 13, count 0 2006.285.13:25:16.69#ibcon#about to read 4, iclass 13, count 0 2006.285.13:25:16.69#ibcon#read 4, iclass 13, count 0 2006.285.13:25:16.69#ibcon#about to read 5, iclass 13, count 0 2006.285.13:25:16.69#ibcon#read 5, iclass 13, count 0 2006.285.13:25:16.69#ibcon#about to read 6, iclass 13, count 0 2006.285.13:25:16.69#ibcon#read 6, iclass 13, count 0 2006.285.13:25:16.69#ibcon#end of sib2, iclass 13, count 0 2006.285.13:25:16.69#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:25:16.69#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:25:16.69#ibcon#[27=BW32\r\n] 2006.285.13:25:16.69#ibcon#*before write, iclass 13, count 0 2006.285.13:25:16.69#ibcon#enter sib2, iclass 13, count 0 2006.285.13:25:16.69#ibcon#flushed, iclass 13, count 0 2006.285.13:25:16.69#ibcon#about to write, iclass 13, count 0 2006.285.13:25:16.69#ibcon#wrote, iclass 13, count 0 2006.285.13:25:16.69#ibcon#about to read 3, iclass 13, count 0 2006.285.13:25:16.72#ibcon#read 3, iclass 13, count 0 2006.285.13:25:16.72#ibcon#about to read 4, iclass 13, count 0 2006.285.13:25:16.72#ibcon#read 4, iclass 13, count 0 2006.285.13:25:16.72#ibcon#about to read 5, iclass 13, count 0 2006.285.13:25:16.72#ibcon#read 5, iclass 13, count 0 2006.285.13:25:16.72#ibcon#about to read 6, iclass 13, count 0 2006.285.13:25:16.72#ibcon#read 6, iclass 13, count 0 2006.285.13:25:16.72#ibcon#end of sib2, iclass 13, count 0 2006.285.13:25:16.72#ibcon#*after write, iclass 13, count 0 2006.285.13:25:16.72#ibcon#*before return 0, iclass 13, count 0 2006.285.13:25:16.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:25:16.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:25:16.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:25:16.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:25:16.72$setupk4/ifdk4 2006.285.13:25:16.72$ifdk4/lo= 2006.285.13:25:16.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:25:16.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:25:16.72$ifdk4/patch= 2006.285.13:25:16.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:25:16.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:25:16.72$setupk4/!*+20s 2006.285.13:25:23.32#abcon#<5=/04 1.5 2.4 19.09 971015.3\r\n> 2006.285.13:25:23.34#abcon#{5=INTERFACE CLEAR} 2006.285.13:25:23.40#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:25:30.69$setupk4/"tpicd 2006.285.13:25:30.69$setupk4/echo=off 2006.285.13:25:30.69$setupk4/xlog=off 2006.285.13:25:30.69:!2006.285.13:26:53 2006.285.13:25:43.14#trakl#Source acquired 2006.285.13:25:43.14#flagr#flagr/antenna,acquired 2006.285.13:26:53.00:preob 2006.285.13:26:53.14/onsource/TRACKING 2006.285.13:26:53.14:!2006.285.13:27:03 2006.285.13:27:03.00:"tape 2006.285.13:27:03.00:"st=record 2006.285.13:27:03.00:data_valid=on 2006.285.13:27:03.00:midob 2006.285.13:27:04.14/onsource/TRACKING 2006.285.13:27:04.14/wx/19.09,1015.3,97 2006.285.13:27:04.27/cable/+6.4985E-03 2006.285.13:27:05.36/va/01,07,usb,yes,32,35 2006.285.13:27:05.36/va/02,06,usb,yes,32,33 2006.285.13:27:05.36/va/03,07,usb,yes,32,34 2006.285.13:27:05.36/va/04,06,usb,yes,33,35 2006.285.13:27:05.36/va/05,03,usb,yes,33,33 2006.285.13:27:05.36/va/06,04,usb,yes,30,29 2006.285.13:27:05.36/va/07,04,usb,yes,30,31 2006.285.13:27:05.36/va/08,03,usb,yes,31,37 2006.285.13:27:05.59/valo/01,524.99,yes,locked 2006.285.13:27:05.59/valo/02,534.99,yes,locked 2006.285.13:27:05.59/valo/03,564.99,yes,locked 2006.285.13:27:05.59/valo/04,624.99,yes,locked 2006.285.13:27:05.59/valo/05,734.99,yes,locked 2006.285.13:27:05.59/valo/06,814.99,yes,locked 2006.285.13:27:05.59/valo/07,864.99,yes,locked 2006.285.13:27:05.59/valo/08,884.99,yes,locked 2006.285.13:27:06.68/vb/01,04,usb,yes,30,28 2006.285.13:27:06.68/vb/02,05,usb,yes,29,29 2006.285.13:27:06.68/vb/03,04,usb,yes,30,33 2006.285.13:27:06.68/vb/04,05,usb,yes,30,29 2006.285.13:27:06.68/vb/05,04,usb,yes,26,29 2006.285.13:27:06.68/vb/06,03,usb,yes,38,33 2006.285.13:27:06.68/vb/07,04,usb,yes,30,30 2006.285.13:27:06.68/vb/08,04,usb,yes,28,31 2006.285.13:27:06.91/vblo/01,629.99,yes,locked 2006.285.13:27:06.91/vblo/02,634.99,yes,locked 2006.285.13:27:06.91/vblo/03,649.99,yes,locked 2006.285.13:27:06.91/vblo/04,679.99,yes,locked 2006.285.13:27:06.91/vblo/05,709.99,yes,locked 2006.285.13:27:06.91/vblo/06,719.99,yes,locked 2006.285.13:27:06.91/vblo/07,734.99,yes,locked 2006.285.13:27:06.91/vblo/08,744.99,yes,locked 2006.285.13:27:07.06/vabw/8 2006.285.13:27:07.21/vbbw/8 2006.285.13:27:07.30/xfe/off,on,12.2 2006.285.13:27:07.67/ifatt/23,28,28,28 2006.285.13:27:08.08/fmout-gps/S +2.74E-07 2006.285.13:27:08.10:!2006.285.13:29:43 2006.285.13:29:43.01:data_valid=off 2006.285.13:29:43.01:"et 2006.285.13:29:43.01:!+3s 2006.285.13:29:46.02:"tape 2006.285.13:29:46.02:postob 2006.285.13:29:46.23/cable/+6.4987E-03 2006.285.13:29:46.23/wx/19.10,1015.3,97 2006.285.13:29:47.08/fmout-gps/S +2.75E-07 2006.285.13:29:47.08:scan_name=285-1332,jd0610,130 2006.285.13:29:47.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.285.13:29:48.14#flagr#flagr/antenna,new-source 2006.285.13:29:48.14:checkk5 2006.285.13:29:48.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:29:49.01/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:29:49.42/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:29:49.81/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:29:50.33/chk_obsdata//k5ts1/T2851327??a.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.13:29:50.72/chk_obsdata//k5ts2/T2851327??b.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.13:29:51.37/chk_obsdata//k5ts3/T2851327??c.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.13:29:51.73/chk_obsdata//k5ts4/T2851327??d.dat file size is correct (nominal:640MB, actual:636MB). 2006.285.13:29:52.64/k5log//k5ts1_log_newline 2006.285.13:29:53.65/k5log//k5ts2_log_newline 2006.285.13:29:54.41/k5log//k5ts3_log_newline 2006.285.13:29:55.18/k5log//k5ts4_log_newline 2006.285.13:29:55.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:29:55.21:setupk4=1 2006.285.13:29:55.21$setupk4/echo=on 2006.285.13:29:55.21$setupk4/pcalon 2006.285.13:29:55.21$pcalon/"no phase cal control is implemented here 2006.285.13:29:55.21$setupk4/"tpicd=stop 2006.285.13:29:55.21$setupk4/"rec=synch_on 2006.285.13:29:55.21$setupk4/"rec_mode=128 2006.285.13:29:55.21$setupk4/!* 2006.285.13:29:55.21$setupk4/recpk4 2006.285.13:29:55.21$recpk4/recpatch= 2006.285.13:29:55.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:29:55.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:29:55.21$setupk4/vck44 2006.285.13:29:55.21$vck44/valo=1,524.99 2006.285.13:29:55.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.13:29:55.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.13:29:55.21#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:55.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:29:55.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:29:55.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:29:55.21#ibcon#enter wrdev, iclass 18, count 0 2006.285.13:29:55.21#ibcon#first serial, iclass 18, count 0 2006.285.13:29:55.21#ibcon#enter sib2, iclass 18, count 0 2006.285.13:29:55.21#ibcon#flushed, iclass 18, count 0 2006.285.13:29:55.21#ibcon#about to write, iclass 18, count 0 2006.285.13:29:55.21#ibcon#wrote, iclass 18, count 0 2006.285.13:29:55.21#ibcon#about to read 3, iclass 18, count 0 2006.285.13:29:55.23#ibcon#read 3, iclass 18, count 0 2006.285.13:29:55.23#ibcon#about to read 4, iclass 18, count 0 2006.285.13:29:55.23#ibcon#read 4, iclass 18, count 0 2006.285.13:29:55.23#ibcon#about to read 5, iclass 18, count 0 2006.285.13:29:55.23#ibcon#read 5, iclass 18, count 0 2006.285.13:29:55.23#ibcon#about to read 6, iclass 18, count 0 2006.285.13:29:55.23#ibcon#read 6, iclass 18, count 0 2006.285.13:29:55.23#ibcon#end of sib2, iclass 18, count 0 2006.285.13:29:55.23#ibcon#*mode == 0, iclass 18, count 0 2006.285.13:29:55.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.13:29:55.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:29:55.23#ibcon#*before write, iclass 18, count 0 2006.285.13:29:55.23#ibcon#enter sib2, iclass 18, count 0 2006.285.13:29:55.23#ibcon#flushed, iclass 18, count 0 2006.285.13:29:55.23#ibcon#about to write, iclass 18, count 0 2006.285.13:29:55.23#ibcon#wrote, iclass 18, count 0 2006.285.13:29:55.23#ibcon#about to read 3, iclass 18, count 0 2006.285.13:29:55.28#ibcon#read 3, iclass 18, count 0 2006.285.13:29:55.28#ibcon#about to read 4, iclass 18, count 0 2006.285.13:29:55.28#ibcon#read 4, iclass 18, count 0 2006.285.13:29:55.28#ibcon#about to read 5, iclass 18, count 0 2006.285.13:29:55.28#ibcon#read 5, iclass 18, count 0 2006.285.13:29:55.28#ibcon#about to read 6, iclass 18, count 0 2006.285.13:29:55.28#ibcon#read 6, iclass 18, count 0 2006.285.13:29:55.28#ibcon#end of sib2, iclass 18, count 0 2006.285.13:29:55.28#ibcon#*after write, iclass 18, count 0 2006.285.13:29:55.28#ibcon#*before return 0, iclass 18, count 0 2006.285.13:29:55.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:29:55.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:29:55.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.13:29:55.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.13:29:55.28$vck44/va=1,7 2006.285.13:29:55.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.13:29:55.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.13:29:55.28#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:55.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:29:55.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:29:55.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:29:55.28#ibcon#enter wrdev, iclass 20, count 2 2006.285.13:29:55.28#ibcon#first serial, iclass 20, count 2 2006.285.13:29:55.28#ibcon#enter sib2, iclass 20, count 2 2006.285.13:29:55.28#ibcon#flushed, iclass 20, count 2 2006.285.13:29:55.28#ibcon#about to write, iclass 20, count 2 2006.285.13:29:55.28#ibcon#wrote, iclass 20, count 2 2006.285.13:29:55.28#ibcon#about to read 3, iclass 20, count 2 2006.285.13:29:55.30#ibcon#read 3, iclass 20, count 2 2006.285.13:29:55.30#ibcon#about to read 4, iclass 20, count 2 2006.285.13:29:55.30#ibcon#read 4, iclass 20, count 2 2006.285.13:29:55.30#ibcon#about to read 5, iclass 20, count 2 2006.285.13:29:55.30#ibcon#read 5, iclass 20, count 2 2006.285.13:29:55.30#ibcon#about to read 6, iclass 20, count 2 2006.285.13:29:55.30#ibcon#read 6, iclass 20, count 2 2006.285.13:29:55.30#ibcon#end of sib2, iclass 20, count 2 2006.285.13:29:55.30#ibcon#*mode == 0, iclass 20, count 2 2006.285.13:29:55.30#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.13:29:55.30#ibcon#[25=AT01-07\r\n] 2006.285.13:29:55.30#ibcon#*before write, iclass 20, count 2 2006.285.13:29:55.30#ibcon#enter sib2, iclass 20, count 2 2006.285.13:29:55.30#ibcon#flushed, iclass 20, count 2 2006.285.13:29:55.30#ibcon#about to write, iclass 20, count 2 2006.285.13:29:55.30#ibcon#wrote, iclass 20, count 2 2006.285.13:29:55.30#ibcon#about to read 3, iclass 20, count 2 2006.285.13:29:55.33#ibcon#read 3, iclass 20, count 2 2006.285.13:29:55.33#ibcon#about to read 4, iclass 20, count 2 2006.285.13:29:55.33#ibcon#read 4, iclass 20, count 2 2006.285.13:29:55.33#ibcon#about to read 5, iclass 20, count 2 2006.285.13:29:55.33#ibcon#read 5, iclass 20, count 2 2006.285.13:29:55.33#ibcon#about to read 6, iclass 20, count 2 2006.285.13:29:55.33#ibcon#read 6, iclass 20, count 2 2006.285.13:29:55.33#ibcon#end of sib2, iclass 20, count 2 2006.285.13:29:55.33#ibcon#*after write, iclass 20, count 2 2006.285.13:29:55.33#ibcon#*before return 0, iclass 20, count 2 2006.285.13:29:55.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:29:55.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:29:55.33#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.13:29:55.33#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:55.33#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:29:55.45#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:29:55.45#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:29:55.45#ibcon#enter wrdev, iclass 20, count 0 2006.285.13:29:55.45#ibcon#first serial, iclass 20, count 0 2006.285.13:29:55.45#ibcon#enter sib2, iclass 20, count 0 2006.285.13:29:55.45#ibcon#flushed, iclass 20, count 0 2006.285.13:29:55.45#ibcon#about to write, iclass 20, count 0 2006.285.13:29:55.45#ibcon#wrote, iclass 20, count 0 2006.285.13:29:55.45#ibcon#about to read 3, iclass 20, count 0 2006.285.13:29:55.47#ibcon#read 3, iclass 20, count 0 2006.285.13:29:55.47#ibcon#about to read 4, iclass 20, count 0 2006.285.13:29:55.47#ibcon#read 4, iclass 20, count 0 2006.285.13:29:55.47#ibcon#about to read 5, iclass 20, count 0 2006.285.13:29:55.47#ibcon#read 5, iclass 20, count 0 2006.285.13:29:55.47#ibcon#about to read 6, iclass 20, count 0 2006.285.13:29:55.47#ibcon#read 6, iclass 20, count 0 2006.285.13:29:55.47#ibcon#end of sib2, iclass 20, count 0 2006.285.13:29:55.47#ibcon#*mode == 0, iclass 20, count 0 2006.285.13:29:55.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.13:29:55.47#ibcon#[25=USB\r\n] 2006.285.13:29:55.47#ibcon#*before write, iclass 20, count 0 2006.285.13:29:55.47#ibcon#enter sib2, iclass 20, count 0 2006.285.13:29:55.47#ibcon#flushed, iclass 20, count 0 2006.285.13:29:55.47#ibcon#about to write, iclass 20, count 0 2006.285.13:29:55.47#ibcon#wrote, iclass 20, count 0 2006.285.13:29:55.47#ibcon#about to read 3, iclass 20, count 0 2006.285.13:29:55.50#ibcon#read 3, iclass 20, count 0 2006.285.13:29:55.50#ibcon#about to read 4, iclass 20, count 0 2006.285.13:29:55.50#ibcon#read 4, iclass 20, count 0 2006.285.13:29:55.50#ibcon#about to read 5, iclass 20, count 0 2006.285.13:29:55.50#ibcon#read 5, iclass 20, count 0 2006.285.13:29:55.50#ibcon#about to read 6, iclass 20, count 0 2006.285.13:29:55.50#ibcon#read 6, iclass 20, count 0 2006.285.13:29:55.50#ibcon#end of sib2, iclass 20, count 0 2006.285.13:29:55.50#ibcon#*after write, iclass 20, count 0 2006.285.13:29:55.50#ibcon#*before return 0, iclass 20, count 0 2006.285.13:29:55.50#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:29:55.50#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:29:55.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.13:29:55.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.13:29:55.50$vck44/valo=2,534.99 2006.285.13:29:55.50#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.13:29:55.50#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.13:29:55.50#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:55.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:29:55.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:29:55.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:29:55.50#ibcon#enter wrdev, iclass 22, count 0 2006.285.13:29:55.50#ibcon#first serial, iclass 22, count 0 2006.285.13:29:55.50#ibcon#enter sib2, iclass 22, count 0 2006.285.13:29:55.50#ibcon#flushed, iclass 22, count 0 2006.285.13:29:55.50#ibcon#about to write, iclass 22, count 0 2006.285.13:29:55.50#ibcon#wrote, iclass 22, count 0 2006.285.13:29:55.50#ibcon#about to read 3, iclass 22, count 0 2006.285.13:29:55.52#ibcon#read 3, iclass 22, count 0 2006.285.13:29:55.52#ibcon#about to read 4, iclass 22, count 0 2006.285.13:29:55.52#ibcon#read 4, iclass 22, count 0 2006.285.13:29:55.52#ibcon#about to read 5, iclass 22, count 0 2006.285.13:29:55.52#ibcon#read 5, iclass 22, count 0 2006.285.13:29:55.52#ibcon#about to read 6, iclass 22, count 0 2006.285.13:29:55.52#ibcon#read 6, iclass 22, count 0 2006.285.13:29:55.52#ibcon#end of sib2, iclass 22, count 0 2006.285.13:29:55.52#ibcon#*mode == 0, iclass 22, count 0 2006.285.13:29:55.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.13:29:55.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:29:55.52#ibcon#*before write, iclass 22, count 0 2006.285.13:29:55.52#ibcon#enter sib2, iclass 22, count 0 2006.285.13:29:55.52#ibcon#flushed, iclass 22, count 0 2006.285.13:29:55.52#ibcon#about to write, iclass 22, count 0 2006.285.13:29:55.52#ibcon#wrote, iclass 22, count 0 2006.285.13:29:55.52#ibcon#about to read 3, iclass 22, count 0 2006.285.13:29:55.56#ibcon#read 3, iclass 22, count 0 2006.285.13:29:55.56#ibcon#about to read 4, iclass 22, count 0 2006.285.13:29:55.56#ibcon#read 4, iclass 22, count 0 2006.285.13:29:55.56#ibcon#about to read 5, iclass 22, count 0 2006.285.13:29:55.56#ibcon#read 5, iclass 22, count 0 2006.285.13:29:55.56#ibcon#about to read 6, iclass 22, count 0 2006.285.13:29:55.56#ibcon#read 6, iclass 22, count 0 2006.285.13:29:55.56#ibcon#end of sib2, iclass 22, count 0 2006.285.13:29:55.56#ibcon#*after write, iclass 22, count 0 2006.285.13:29:55.56#ibcon#*before return 0, iclass 22, count 0 2006.285.13:29:55.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:29:55.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:29:55.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.13:29:55.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.13:29:55.56$vck44/va=2,6 2006.285.13:29:55.56#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.13:29:55.56#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.13:29:55.56#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:55.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:29:55.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:29:55.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:29:55.62#ibcon#enter wrdev, iclass 24, count 2 2006.285.13:29:55.62#ibcon#first serial, iclass 24, count 2 2006.285.13:29:55.62#ibcon#enter sib2, iclass 24, count 2 2006.285.13:29:55.62#ibcon#flushed, iclass 24, count 2 2006.285.13:29:55.62#ibcon#about to write, iclass 24, count 2 2006.285.13:29:55.62#ibcon#wrote, iclass 24, count 2 2006.285.13:29:55.62#ibcon#about to read 3, iclass 24, count 2 2006.285.13:29:55.64#ibcon#read 3, iclass 24, count 2 2006.285.13:29:55.64#ibcon#about to read 4, iclass 24, count 2 2006.285.13:29:55.64#ibcon#read 4, iclass 24, count 2 2006.285.13:29:55.64#ibcon#about to read 5, iclass 24, count 2 2006.285.13:29:55.64#ibcon#read 5, iclass 24, count 2 2006.285.13:29:55.64#ibcon#about to read 6, iclass 24, count 2 2006.285.13:29:55.64#ibcon#read 6, iclass 24, count 2 2006.285.13:29:55.64#ibcon#end of sib2, iclass 24, count 2 2006.285.13:29:55.64#ibcon#*mode == 0, iclass 24, count 2 2006.285.13:29:55.64#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.13:29:55.64#ibcon#[25=AT02-06\r\n] 2006.285.13:29:55.64#ibcon#*before write, iclass 24, count 2 2006.285.13:29:55.64#ibcon#enter sib2, iclass 24, count 2 2006.285.13:29:55.64#ibcon#flushed, iclass 24, count 2 2006.285.13:29:55.64#ibcon#about to write, iclass 24, count 2 2006.285.13:29:55.64#ibcon#wrote, iclass 24, count 2 2006.285.13:29:55.64#ibcon#about to read 3, iclass 24, count 2 2006.285.13:29:55.67#ibcon#read 3, iclass 24, count 2 2006.285.13:29:55.67#ibcon#about to read 4, iclass 24, count 2 2006.285.13:29:55.67#ibcon#read 4, iclass 24, count 2 2006.285.13:29:55.67#ibcon#about to read 5, iclass 24, count 2 2006.285.13:29:55.67#ibcon#read 5, iclass 24, count 2 2006.285.13:29:55.67#ibcon#about to read 6, iclass 24, count 2 2006.285.13:29:55.67#ibcon#read 6, iclass 24, count 2 2006.285.13:29:55.67#ibcon#end of sib2, iclass 24, count 2 2006.285.13:29:55.67#ibcon#*after write, iclass 24, count 2 2006.285.13:29:55.67#ibcon#*before return 0, iclass 24, count 2 2006.285.13:29:55.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:29:55.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:29:55.67#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.13:29:55.67#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:55.67#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:29:55.79#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:29:55.79#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:29:55.79#ibcon#enter wrdev, iclass 24, count 0 2006.285.13:29:55.79#ibcon#first serial, iclass 24, count 0 2006.285.13:29:55.79#ibcon#enter sib2, iclass 24, count 0 2006.285.13:29:55.79#ibcon#flushed, iclass 24, count 0 2006.285.13:29:55.79#ibcon#about to write, iclass 24, count 0 2006.285.13:29:55.79#ibcon#wrote, iclass 24, count 0 2006.285.13:29:55.79#ibcon#about to read 3, iclass 24, count 0 2006.285.13:29:55.81#ibcon#read 3, iclass 24, count 0 2006.285.13:29:55.81#ibcon#about to read 4, iclass 24, count 0 2006.285.13:29:55.81#ibcon#read 4, iclass 24, count 0 2006.285.13:29:55.81#ibcon#about to read 5, iclass 24, count 0 2006.285.13:29:55.81#ibcon#read 5, iclass 24, count 0 2006.285.13:29:55.81#ibcon#about to read 6, iclass 24, count 0 2006.285.13:29:55.81#ibcon#read 6, iclass 24, count 0 2006.285.13:29:55.81#ibcon#end of sib2, iclass 24, count 0 2006.285.13:29:55.81#ibcon#*mode == 0, iclass 24, count 0 2006.285.13:29:55.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.13:29:55.81#ibcon#[25=USB\r\n] 2006.285.13:29:55.81#ibcon#*before write, iclass 24, count 0 2006.285.13:29:55.81#ibcon#enter sib2, iclass 24, count 0 2006.285.13:29:55.81#ibcon#flushed, iclass 24, count 0 2006.285.13:29:55.81#ibcon#about to write, iclass 24, count 0 2006.285.13:29:55.81#ibcon#wrote, iclass 24, count 0 2006.285.13:29:55.81#ibcon#about to read 3, iclass 24, count 0 2006.285.13:29:55.84#ibcon#read 3, iclass 24, count 0 2006.285.13:29:55.84#ibcon#about to read 4, iclass 24, count 0 2006.285.13:29:55.84#ibcon#read 4, iclass 24, count 0 2006.285.13:29:55.84#ibcon#about to read 5, iclass 24, count 0 2006.285.13:29:55.84#ibcon#read 5, iclass 24, count 0 2006.285.13:29:55.84#ibcon#about to read 6, iclass 24, count 0 2006.285.13:29:55.84#ibcon#read 6, iclass 24, count 0 2006.285.13:29:55.84#ibcon#end of sib2, iclass 24, count 0 2006.285.13:29:55.84#ibcon#*after write, iclass 24, count 0 2006.285.13:29:55.84#ibcon#*before return 0, iclass 24, count 0 2006.285.13:29:55.84#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:29:55.84#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:29:55.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.13:29:55.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.13:29:55.84$vck44/valo=3,564.99 2006.285.13:29:55.84#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.13:29:55.84#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.13:29:55.84#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:55.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:29:55.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:29:55.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:29:55.84#ibcon#enter wrdev, iclass 26, count 0 2006.285.13:29:55.84#ibcon#first serial, iclass 26, count 0 2006.285.13:29:55.84#ibcon#enter sib2, iclass 26, count 0 2006.285.13:29:55.84#ibcon#flushed, iclass 26, count 0 2006.285.13:29:55.84#ibcon#about to write, iclass 26, count 0 2006.285.13:29:55.84#ibcon#wrote, iclass 26, count 0 2006.285.13:29:55.84#ibcon#about to read 3, iclass 26, count 0 2006.285.13:29:55.86#ibcon#read 3, iclass 26, count 0 2006.285.13:29:55.86#ibcon#about to read 4, iclass 26, count 0 2006.285.13:29:55.86#ibcon#read 4, iclass 26, count 0 2006.285.13:29:55.86#ibcon#about to read 5, iclass 26, count 0 2006.285.13:29:55.86#ibcon#read 5, iclass 26, count 0 2006.285.13:29:55.86#ibcon#about to read 6, iclass 26, count 0 2006.285.13:29:55.86#ibcon#read 6, iclass 26, count 0 2006.285.13:29:55.86#ibcon#end of sib2, iclass 26, count 0 2006.285.13:29:55.86#ibcon#*mode == 0, iclass 26, count 0 2006.285.13:29:55.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.13:29:55.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:29:55.86#ibcon#*before write, iclass 26, count 0 2006.285.13:29:55.86#ibcon#enter sib2, iclass 26, count 0 2006.285.13:29:55.86#ibcon#flushed, iclass 26, count 0 2006.285.13:29:55.86#ibcon#about to write, iclass 26, count 0 2006.285.13:29:55.86#ibcon#wrote, iclass 26, count 0 2006.285.13:29:55.86#ibcon#about to read 3, iclass 26, count 0 2006.285.13:29:55.90#ibcon#read 3, iclass 26, count 0 2006.285.13:29:55.90#ibcon#about to read 4, iclass 26, count 0 2006.285.13:29:55.90#ibcon#read 4, iclass 26, count 0 2006.285.13:29:55.90#ibcon#about to read 5, iclass 26, count 0 2006.285.13:29:55.90#ibcon#read 5, iclass 26, count 0 2006.285.13:29:55.90#ibcon#about to read 6, iclass 26, count 0 2006.285.13:29:55.90#ibcon#read 6, iclass 26, count 0 2006.285.13:29:55.90#ibcon#end of sib2, iclass 26, count 0 2006.285.13:29:55.90#ibcon#*after write, iclass 26, count 0 2006.285.13:29:55.90#ibcon#*before return 0, iclass 26, count 0 2006.285.13:29:55.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:29:55.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:29:55.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.13:29:55.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.13:29:55.90$vck44/va=3,7 2006.285.13:29:55.90#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.13:29:55.90#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.13:29:55.90#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:55.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:29:55.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:29:55.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:29:55.96#ibcon#enter wrdev, iclass 28, count 2 2006.285.13:29:55.96#ibcon#first serial, iclass 28, count 2 2006.285.13:29:55.96#ibcon#enter sib2, iclass 28, count 2 2006.285.13:29:55.96#ibcon#flushed, iclass 28, count 2 2006.285.13:29:55.96#ibcon#about to write, iclass 28, count 2 2006.285.13:29:55.96#ibcon#wrote, iclass 28, count 2 2006.285.13:29:55.96#ibcon#about to read 3, iclass 28, count 2 2006.285.13:29:55.98#ibcon#read 3, iclass 28, count 2 2006.285.13:29:55.98#ibcon#about to read 4, iclass 28, count 2 2006.285.13:29:55.98#ibcon#read 4, iclass 28, count 2 2006.285.13:29:55.98#ibcon#about to read 5, iclass 28, count 2 2006.285.13:29:55.98#ibcon#read 5, iclass 28, count 2 2006.285.13:29:55.98#ibcon#about to read 6, iclass 28, count 2 2006.285.13:29:55.98#ibcon#read 6, iclass 28, count 2 2006.285.13:29:55.98#ibcon#end of sib2, iclass 28, count 2 2006.285.13:29:55.98#ibcon#*mode == 0, iclass 28, count 2 2006.285.13:29:55.98#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.13:29:55.98#ibcon#[25=AT03-07\r\n] 2006.285.13:29:55.98#ibcon#*before write, iclass 28, count 2 2006.285.13:29:55.98#ibcon#enter sib2, iclass 28, count 2 2006.285.13:29:55.98#ibcon#flushed, iclass 28, count 2 2006.285.13:29:55.98#ibcon#about to write, iclass 28, count 2 2006.285.13:29:55.98#ibcon#wrote, iclass 28, count 2 2006.285.13:29:55.98#ibcon#about to read 3, iclass 28, count 2 2006.285.13:29:56.01#ibcon#read 3, iclass 28, count 2 2006.285.13:29:56.40#ibcon#about to read 4, iclass 28, count 2 2006.285.13:29:56.40#ibcon#read 4, iclass 28, count 2 2006.285.13:29:56.40#ibcon#about to read 5, iclass 28, count 2 2006.285.13:29:56.40#ibcon#read 5, iclass 28, count 2 2006.285.13:29:56.40#ibcon#about to read 6, iclass 28, count 2 2006.285.13:29:56.40#ibcon#read 6, iclass 28, count 2 2006.285.13:29:56.40#ibcon#end of sib2, iclass 28, count 2 2006.285.13:29:56.40#ibcon#*after write, iclass 28, count 2 2006.285.13:29:56.40#ibcon#*before return 0, iclass 28, count 2 2006.285.13:29:56.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:29:56.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:29:56.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.13:29:56.40#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:56.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:29:56.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:29:56.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:29:56.52#ibcon#enter wrdev, iclass 28, count 0 2006.285.13:29:56.52#ibcon#first serial, iclass 28, count 0 2006.285.13:29:56.52#ibcon#enter sib2, iclass 28, count 0 2006.285.13:29:56.52#ibcon#flushed, iclass 28, count 0 2006.285.13:29:56.52#ibcon#about to write, iclass 28, count 0 2006.285.13:29:56.52#ibcon#wrote, iclass 28, count 0 2006.285.13:29:56.52#ibcon#about to read 3, iclass 28, count 0 2006.285.13:29:56.54#ibcon#read 3, iclass 28, count 0 2006.285.13:29:56.54#ibcon#about to read 4, iclass 28, count 0 2006.285.13:29:56.54#ibcon#read 4, iclass 28, count 0 2006.285.13:29:56.54#ibcon#about to read 5, iclass 28, count 0 2006.285.13:29:56.54#ibcon#read 5, iclass 28, count 0 2006.285.13:29:56.54#ibcon#about to read 6, iclass 28, count 0 2006.285.13:29:56.54#ibcon#read 6, iclass 28, count 0 2006.285.13:29:56.54#ibcon#end of sib2, iclass 28, count 0 2006.285.13:29:56.54#ibcon#*mode == 0, iclass 28, count 0 2006.285.13:29:56.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.13:29:56.54#ibcon#[25=USB\r\n] 2006.285.13:29:56.54#ibcon#*before write, iclass 28, count 0 2006.285.13:29:56.54#ibcon#enter sib2, iclass 28, count 0 2006.285.13:29:56.54#ibcon#flushed, iclass 28, count 0 2006.285.13:29:56.54#ibcon#about to write, iclass 28, count 0 2006.285.13:29:56.54#ibcon#wrote, iclass 28, count 0 2006.285.13:29:56.54#ibcon#about to read 3, iclass 28, count 0 2006.285.13:29:56.57#ibcon#read 3, iclass 28, count 0 2006.285.13:29:56.57#ibcon#about to read 4, iclass 28, count 0 2006.285.13:29:56.57#ibcon#read 4, iclass 28, count 0 2006.285.13:29:56.57#ibcon#about to read 5, iclass 28, count 0 2006.285.13:29:56.57#ibcon#read 5, iclass 28, count 0 2006.285.13:29:56.57#ibcon#about to read 6, iclass 28, count 0 2006.285.13:29:56.57#ibcon#read 6, iclass 28, count 0 2006.285.13:29:56.57#ibcon#end of sib2, iclass 28, count 0 2006.285.13:29:56.57#ibcon#*after write, iclass 28, count 0 2006.285.13:29:56.57#ibcon#*before return 0, iclass 28, count 0 2006.285.13:29:56.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:29:56.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:29:56.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.13:29:56.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.13:29:56.57$vck44/valo=4,624.99 2006.285.13:29:56.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.13:29:56.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.13:29:56.57#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:56.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:29:56.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:29:56.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:29:56.57#ibcon#enter wrdev, iclass 30, count 0 2006.285.13:29:56.57#ibcon#first serial, iclass 30, count 0 2006.285.13:29:56.57#ibcon#enter sib2, iclass 30, count 0 2006.285.13:29:56.57#ibcon#flushed, iclass 30, count 0 2006.285.13:29:56.57#ibcon#about to write, iclass 30, count 0 2006.285.13:29:56.57#ibcon#wrote, iclass 30, count 0 2006.285.13:29:56.57#ibcon#about to read 3, iclass 30, count 0 2006.285.13:29:56.59#ibcon#read 3, iclass 30, count 0 2006.285.13:29:56.59#ibcon#about to read 4, iclass 30, count 0 2006.285.13:29:56.59#ibcon#read 4, iclass 30, count 0 2006.285.13:29:56.59#ibcon#about to read 5, iclass 30, count 0 2006.285.13:29:56.59#ibcon#read 5, iclass 30, count 0 2006.285.13:29:56.59#ibcon#about to read 6, iclass 30, count 0 2006.285.13:29:56.59#ibcon#read 6, iclass 30, count 0 2006.285.13:29:56.59#ibcon#end of sib2, iclass 30, count 0 2006.285.13:29:56.59#ibcon#*mode == 0, iclass 30, count 0 2006.285.13:29:56.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.13:29:56.59#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:29:56.59#ibcon#*before write, iclass 30, count 0 2006.285.13:29:56.59#ibcon#enter sib2, iclass 30, count 0 2006.285.13:29:56.59#ibcon#flushed, iclass 30, count 0 2006.285.13:29:56.59#ibcon#about to write, iclass 30, count 0 2006.285.13:29:56.59#ibcon#wrote, iclass 30, count 0 2006.285.13:29:56.59#ibcon#about to read 3, iclass 30, count 0 2006.285.13:29:56.63#ibcon#read 3, iclass 30, count 0 2006.285.13:29:56.63#ibcon#about to read 4, iclass 30, count 0 2006.285.13:29:56.63#ibcon#read 4, iclass 30, count 0 2006.285.13:29:56.63#ibcon#about to read 5, iclass 30, count 0 2006.285.13:29:56.63#ibcon#read 5, iclass 30, count 0 2006.285.13:29:56.63#ibcon#about to read 6, iclass 30, count 0 2006.285.13:29:56.63#ibcon#read 6, iclass 30, count 0 2006.285.13:29:56.63#ibcon#end of sib2, iclass 30, count 0 2006.285.13:29:56.63#ibcon#*after write, iclass 30, count 0 2006.285.13:29:56.63#ibcon#*before return 0, iclass 30, count 0 2006.285.13:29:56.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:29:56.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:29:56.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.13:29:56.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.13:29:56.63$vck44/va=4,6 2006.285.13:29:56.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.13:29:56.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.13:29:56.63#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:56.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:29:56.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:29:56.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:29:56.69#ibcon#enter wrdev, iclass 32, count 2 2006.285.13:29:56.69#ibcon#first serial, iclass 32, count 2 2006.285.13:29:56.69#ibcon#enter sib2, iclass 32, count 2 2006.285.13:29:56.69#ibcon#flushed, iclass 32, count 2 2006.285.13:29:56.69#ibcon#about to write, iclass 32, count 2 2006.285.13:29:56.69#ibcon#wrote, iclass 32, count 2 2006.285.13:29:56.69#ibcon#about to read 3, iclass 32, count 2 2006.285.13:29:56.71#ibcon#read 3, iclass 32, count 2 2006.285.13:29:56.71#ibcon#about to read 4, iclass 32, count 2 2006.285.13:29:56.71#ibcon#read 4, iclass 32, count 2 2006.285.13:29:56.71#ibcon#about to read 5, iclass 32, count 2 2006.285.13:29:56.71#ibcon#read 5, iclass 32, count 2 2006.285.13:29:56.71#ibcon#about to read 6, iclass 32, count 2 2006.285.13:29:56.71#ibcon#read 6, iclass 32, count 2 2006.285.13:29:56.71#ibcon#end of sib2, iclass 32, count 2 2006.285.13:29:56.71#ibcon#*mode == 0, iclass 32, count 2 2006.285.13:29:56.71#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.13:29:56.71#ibcon#[25=AT04-06\r\n] 2006.285.13:29:56.71#ibcon#*before write, iclass 32, count 2 2006.285.13:29:56.71#ibcon#enter sib2, iclass 32, count 2 2006.285.13:29:56.71#ibcon#flushed, iclass 32, count 2 2006.285.13:29:56.71#ibcon#about to write, iclass 32, count 2 2006.285.13:29:56.71#ibcon#wrote, iclass 32, count 2 2006.285.13:29:56.71#ibcon#about to read 3, iclass 32, count 2 2006.285.13:29:56.74#ibcon#read 3, iclass 32, count 2 2006.285.13:29:56.97#ibcon#about to read 4, iclass 32, count 2 2006.285.13:29:56.97#ibcon#read 4, iclass 32, count 2 2006.285.13:29:56.97#ibcon#about to read 5, iclass 32, count 2 2006.285.13:29:56.97#ibcon#read 5, iclass 32, count 2 2006.285.13:29:56.97#ibcon#about to read 6, iclass 32, count 2 2006.285.13:29:56.97#ibcon#read 6, iclass 32, count 2 2006.285.13:29:56.97#ibcon#end of sib2, iclass 32, count 2 2006.285.13:29:56.97#ibcon#*after write, iclass 32, count 2 2006.285.13:29:56.97#ibcon#*before return 0, iclass 32, count 2 2006.285.13:29:56.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:29:56.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:29:56.97#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.13:29:56.97#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:56.97#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:29:57.09#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:29:57.09#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:29:57.09#ibcon#enter wrdev, iclass 32, count 0 2006.285.13:29:57.09#ibcon#first serial, iclass 32, count 0 2006.285.13:29:57.09#ibcon#enter sib2, iclass 32, count 0 2006.285.13:29:57.09#ibcon#flushed, iclass 32, count 0 2006.285.13:29:57.09#ibcon#about to write, iclass 32, count 0 2006.285.13:29:57.09#ibcon#wrote, iclass 32, count 0 2006.285.13:29:57.09#ibcon#about to read 3, iclass 32, count 0 2006.285.13:29:57.11#ibcon#read 3, iclass 32, count 0 2006.285.13:29:57.11#ibcon#about to read 4, iclass 32, count 0 2006.285.13:29:57.11#ibcon#read 4, iclass 32, count 0 2006.285.13:29:57.11#ibcon#about to read 5, iclass 32, count 0 2006.285.13:29:57.11#ibcon#read 5, iclass 32, count 0 2006.285.13:29:57.11#ibcon#about to read 6, iclass 32, count 0 2006.285.13:29:57.11#ibcon#read 6, iclass 32, count 0 2006.285.13:29:57.11#ibcon#end of sib2, iclass 32, count 0 2006.285.13:29:57.11#ibcon#*mode == 0, iclass 32, count 0 2006.285.13:29:57.11#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.13:29:57.11#ibcon#[25=USB\r\n] 2006.285.13:29:57.11#ibcon#*before write, iclass 32, count 0 2006.285.13:29:57.11#ibcon#enter sib2, iclass 32, count 0 2006.285.13:29:57.11#ibcon#flushed, iclass 32, count 0 2006.285.13:29:57.11#ibcon#about to write, iclass 32, count 0 2006.285.13:29:57.11#ibcon#wrote, iclass 32, count 0 2006.285.13:29:57.11#ibcon#about to read 3, iclass 32, count 0 2006.285.13:29:57.14#ibcon#read 3, iclass 32, count 0 2006.285.13:29:57.14#ibcon#about to read 4, iclass 32, count 0 2006.285.13:29:57.14#ibcon#read 4, iclass 32, count 0 2006.285.13:29:57.14#ibcon#about to read 5, iclass 32, count 0 2006.285.13:29:57.14#ibcon#read 5, iclass 32, count 0 2006.285.13:29:57.14#ibcon#about to read 6, iclass 32, count 0 2006.285.13:29:57.14#ibcon#read 6, iclass 32, count 0 2006.285.13:29:57.14#ibcon#end of sib2, iclass 32, count 0 2006.285.13:29:57.14#ibcon#*after write, iclass 32, count 0 2006.285.13:29:57.14#ibcon#*before return 0, iclass 32, count 0 2006.285.13:29:57.14#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:29:57.14#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:29:57.14#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.13:29:57.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.13:29:57.14$vck44/valo=5,734.99 2006.285.13:29:57.14#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.13:29:57.14#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.13:29:57.14#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:57.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:29:57.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:29:57.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:29:57.14#ibcon#enter wrdev, iclass 34, count 0 2006.285.13:29:57.14#ibcon#first serial, iclass 34, count 0 2006.285.13:29:57.14#ibcon#enter sib2, iclass 34, count 0 2006.285.13:29:57.14#ibcon#flushed, iclass 34, count 0 2006.285.13:29:57.14#ibcon#about to write, iclass 34, count 0 2006.285.13:29:57.14#ibcon#wrote, iclass 34, count 0 2006.285.13:29:57.14#ibcon#about to read 3, iclass 34, count 0 2006.285.13:29:57.16#ibcon#read 3, iclass 34, count 0 2006.285.13:29:57.16#ibcon#about to read 4, iclass 34, count 0 2006.285.13:29:57.16#ibcon#read 4, iclass 34, count 0 2006.285.13:29:57.16#ibcon#about to read 5, iclass 34, count 0 2006.285.13:29:57.16#ibcon#read 5, iclass 34, count 0 2006.285.13:29:57.16#ibcon#about to read 6, iclass 34, count 0 2006.285.13:29:57.16#ibcon#read 6, iclass 34, count 0 2006.285.13:29:57.16#ibcon#end of sib2, iclass 34, count 0 2006.285.13:29:57.16#ibcon#*mode == 0, iclass 34, count 0 2006.285.13:29:57.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.13:29:57.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:29:57.16#ibcon#*before write, iclass 34, count 0 2006.285.13:29:57.16#ibcon#enter sib2, iclass 34, count 0 2006.285.13:29:57.16#ibcon#flushed, iclass 34, count 0 2006.285.13:29:57.16#ibcon#about to write, iclass 34, count 0 2006.285.13:29:57.16#ibcon#wrote, iclass 34, count 0 2006.285.13:29:57.16#ibcon#about to read 3, iclass 34, count 0 2006.285.13:29:57.20#ibcon#read 3, iclass 34, count 0 2006.285.13:29:57.20#ibcon#about to read 4, iclass 34, count 0 2006.285.13:29:57.20#ibcon#read 4, iclass 34, count 0 2006.285.13:29:57.20#ibcon#about to read 5, iclass 34, count 0 2006.285.13:29:57.20#ibcon#read 5, iclass 34, count 0 2006.285.13:29:57.20#ibcon#about to read 6, iclass 34, count 0 2006.285.13:29:57.20#ibcon#read 6, iclass 34, count 0 2006.285.13:29:57.20#ibcon#end of sib2, iclass 34, count 0 2006.285.13:29:57.20#ibcon#*after write, iclass 34, count 0 2006.285.13:29:57.20#ibcon#*before return 0, iclass 34, count 0 2006.285.13:29:57.20#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:29:57.20#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:29:57.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.13:29:57.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.13:29:57.20$vck44/va=5,3 2006.285.13:29:57.28#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.13:29:57.28#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.13:29:57.28#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:57.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:29:57.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:29:57.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:29:57.28#ibcon#enter wrdev, iclass 36, count 2 2006.285.13:29:57.28#ibcon#first serial, iclass 36, count 2 2006.285.13:29:57.28#ibcon#enter sib2, iclass 36, count 2 2006.285.13:29:57.28#ibcon#flushed, iclass 36, count 2 2006.285.13:29:57.28#ibcon#about to write, iclass 36, count 2 2006.285.13:29:57.28#ibcon#wrote, iclass 36, count 2 2006.285.13:29:57.28#ibcon#about to read 3, iclass 36, count 2 2006.285.13:29:57.30#ibcon#read 3, iclass 36, count 2 2006.285.13:29:57.30#ibcon#about to read 4, iclass 36, count 2 2006.285.13:29:57.30#ibcon#read 4, iclass 36, count 2 2006.285.13:29:57.30#ibcon#about to read 5, iclass 36, count 2 2006.285.13:29:57.30#ibcon#read 5, iclass 36, count 2 2006.285.13:29:57.30#ibcon#about to read 6, iclass 36, count 2 2006.285.13:29:57.30#ibcon#read 6, iclass 36, count 2 2006.285.13:29:57.30#ibcon#end of sib2, iclass 36, count 2 2006.285.13:29:57.30#ibcon#*mode == 0, iclass 36, count 2 2006.285.13:29:57.30#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.13:29:57.30#ibcon#[25=AT05-03\r\n] 2006.285.13:29:57.30#ibcon#*before write, iclass 36, count 2 2006.285.13:29:57.30#ibcon#enter sib2, iclass 36, count 2 2006.285.13:29:57.30#ibcon#flushed, iclass 36, count 2 2006.285.13:29:57.30#ibcon#about to write, iclass 36, count 2 2006.285.13:29:57.30#ibcon#wrote, iclass 36, count 2 2006.285.13:29:57.30#ibcon#about to read 3, iclass 36, count 2 2006.285.13:29:57.33#ibcon#read 3, iclass 36, count 2 2006.285.13:29:57.33#ibcon#about to read 4, iclass 36, count 2 2006.285.13:29:57.33#ibcon#read 4, iclass 36, count 2 2006.285.13:29:57.33#ibcon#about to read 5, iclass 36, count 2 2006.285.13:29:57.33#ibcon#read 5, iclass 36, count 2 2006.285.13:29:57.33#ibcon#about to read 6, iclass 36, count 2 2006.285.13:29:57.33#ibcon#read 6, iclass 36, count 2 2006.285.13:29:57.33#ibcon#end of sib2, iclass 36, count 2 2006.285.13:29:57.33#ibcon#*after write, iclass 36, count 2 2006.285.13:29:57.33#ibcon#*before return 0, iclass 36, count 2 2006.285.13:29:57.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:29:57.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:29:57.33#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.13:29:57.33#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:57.33#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:29:57.45#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:29:57.45#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:29:57.45#ibcon#enter wrdev, iclass 36, count 0 2006.285.13:29:57.45#ibcon#first serial, iclass 36, count 0 2006.285.13:29:57.45#ibcon#enter sib2, iclass 36, count 0 2006.285.13:29:57.45#ibcon#flushed, iclass 36, count 0 2006.285.13:29:57.45#ibcon#about to write, iclass 36, count 0 2006.285.13:29:57.45#ibcon#wrote, iclass 36, count 0 2006.285.13:29:57.45#ibcon#about to read 3, iclass 36, count 0 2006.285.13:29:57.47#ibcon#read 3, iclass 36, count 0 2006.285.13:29:57.47#ibcon#about to read 4, iclass 36, count 0 2006.285.13:29:57.47#ibcon#read 4, iclass 36, count 0 2006.285.13:29:57.47#ibcon#about to read 5, iclass 36, count 0 2006.285.13:29:57.47#ibcon#read 5, iclass 36, count 0 2006.285.13:29:57.47#ibcon#about to read 6, iclass 36, count 0 2006.285.13:29:57.47#ibcon#read 6, iclass 36, count 0 2006.285.13:29:57.47#ibcon#end of sib2, iclass 36, count 0 2006.285.13:29:57.47#ibcon#*mode == 0, iclass 36, count 0 2006.285.13:29:57.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.13:29:57.47#ibcon#[25=USB\r\n] 2006.285.13:29:57.47#ibcon#*before write, iclass 36, count 0 2006.285.13:29:57.47#ibcon#enter sib2, iclass 36, count 0 2006.285.13:29:57.47#ibcon#flushed, iclass 36, count 0 2006.285.13:29:57.47#ibcon#about to write, iclass 36, count 0 2006.285.13:29:57.47#ibcon#wrote, iclass 36, count 0 2006.285.13:29:57.47#ibcon#about to read 3, iclass 36, count 0 2006.285.13:29:57.50#ibcon#read 3, iclass 36, count 0 2006.285.13:29:57.50#ibcon#about to read 4, iclass 36, count 0 2006.285.13:29:57.50#ibcon#read 4, iclass 36, count 0 2006.285.13:29:57.50#ibcon#about to read 5, iclass 36, count 0 2006.285.13:29:57.50#ibcon#read 5, iclass 36, count 0 2006.285.13:29:57.50#ibcon#about to read 6, iclass 36, count 0 2006.285.13:29:57.50#ibcon#read 6, iclass 36, count 0 2006.285.13:29:57.50#ibcon#end of sib2, iclass 36, count 0 2006.285.13:29:57.50#ibcon#*after write, iclass 36, count 0 2006.285.13:29:57.50#ibcon#*before return 0, iclass 36, count 0 2006.285.13:29:57.50#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:29:57.50#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:29:57.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.13:29:57.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.13:29:57.50$vck44/valo=6,814.99 2006.285.13:29:57.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.13:29:57.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.13:29:57.50#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:57.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:29:57.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:29:57.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:29:57.50#ibcon#enter wrdev, iclass 38, count 0 2006.285.13:29:57.50#ibcon#first serial, iclass 38, count 0 2006.285.13:29:57.50#ibcon#enter sib2, iclass 38, count 0 2006.285.13:29:57.50#ibcon#flushed, iclass 38, count 0 2006.285.13:29:57.50#ibcon#about to write, iclass 38, count 0 2006.285.13:29:57.50#ibcon#wrote, iclass 38, count 0 2006.285.13:29:57.50#ibcon#about to read 3, iclass 38, count 0 2006.285.13:29:57.52#ibcon#read 3, iclass 38, count 0 2006.285.13:29:57.52#ibcon#about to read 4, iclass 38, count 0 2006.285.13:29:57.52#ibcon#read 4, iclass 38, count 0 2006.285.13:29:57.52#ibcon#about to read 5, iclass 38, count 0 2006.285.13:29:57.52#ibcon#read 5, iclass 38, count 0 2006.285.13:29:57.52#ibcon#about to read 6, iclass 38, count 0 2006.285.13:29:57.52#ibcon#read 6, iclass 38, count 0 2006.285.13:29:57.52#ibcon#end of sib2, iclass 38, count 0 2006.285.13:29:57.52#ibcon#*mode == 0, iclass 38, count 0 2006.285.13:29:57.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.13:29:57.52#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:29:57.52#ibcon#*before write, iclass 38, count 0 2006.285.13:29:57.52#ibcon#enter sib2, iclass 38, count 0 2006.285.13:29:57.52#ibcon#flushed, iclass 38, count 0 2006.285.13:29:57.52#ibcon#about to write, iclass 38, count 0 2006.285.13:29:57.52#ibcon#wrote, iclass 38, count 0 2006.285.13:29:57.52#ibcon#about to read 3, iclass 38, count 0 2006.285.13:29:57.56#ibcon#read 3, iclass 38, count 0 2006.285.13:29:57.56#ibcon#about to read 4, iclass 38, count 0 2006.285.13:29:57.56#ibcon#read 4, iclass 38, count 0 2006.285.13:29:57.56#ibcon#about to read 5, iclass 38, count 0 2006.285.13:29:57.56#ibcon#read 5, iclass 38, count 0 2006.285.13:29:57.56#ibcon#about to read 6, iclass 38, count 0 2006.285.13:29:57.56#ibcon#read 6, iclass 38, count 0 2006.285.13:29:57.56#ibcon#end of sib2, iclass 38, count 0 2006.285.13:29:57.56#ibcon#*after write, iclass 38, count 0 2006.285.13:29:57.56#ibcon#*before return 0, iclass 38, count 0 2006.285.13:29:57.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:29:57.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:29:57.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.13:29:57.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.13:29:57.56$vck44/va=6,4 2006.285.13:29:57.56#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.13:29:57.56#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.13:29:57.56#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:57.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:29:57.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:29:57.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:29:57.62#ibcon#enter wrdev, iclass 40, count 2 2006.285.13:29:57.62#ibcon#first serial, iclass 40, count 2 2006.285.13:29:57.62#ibcon#enter sib2, iclass 40, count 2 2006.285.13:29:57.62#ibcon#flushed, iclass 40, count 2 2006.285.13:29:57.62#ibcon#about to write, iclass 40, count 2 2006.285.13:29:57.62#ibcon#wrote, iclass 40, count 2 2006.285.13:29:57.62#ibcon#about to read 3, iclass 40, count 2 2006.285.13:29:57.64#ibcon#read 3, iclass 40, count 2 2006.285.13:29:57.64#ibcon#about to read 4, iclass 40, count 2 2006.285.13:29:57.64#ibcon#read 4, iclass 40, count 2 2006.285.13:29:57.64#ibcon#about to read 5, iclass 40, count 2 2006.285.13:29:57.64#ibcon#read 5, iclass 40, count 2 2006.285.13:29:57.64#ibcon#about to read 6, iclass 40, count 2 2006.285.13:29:57.64#ibcon#read 6, iclass 40, count 2 2006.285.13:29:57.64#ibcon#end of sib2, iclass 40, count 2 2006.285.13:29:57.64#ibcon#*mode == 0, iclass 40, count 2 2006.285.13:29:57.64#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.13:29:57.64#ibcon#[25=AT06-04\r\n] 2006.285.13:29:57.64#ibcon#*before write, iclass 40, count 2 2006.285.13:29:57.64#ibcon#enter sib2, iclass 40, count 2 2006.285.13:29:57.64#ibcon#flushed, iclass 40, count 2 2006.285.13:29:57.64#ibcon#about to write, iclass 40, count 2 2006.285.13:29:57.64#ibcon#wrote, iclass 40, count 2 2006.285.13:29:57.64#ibcon#about to read 3, iclass 40, count 2 2006.285.13:29:57.67#ibcon#read 3, iclass 40, count 2 2006.285.13:29:57.67#ibcon#about to read 4, iclass 40, count 2 2006.285.13:29:57.67#ibcon#read 4, iclass 40, count 2 2006.285.13:29:57.67#ibcon#about to read 5, iclass 40, count 2 2006.285.13:29:57.67#ibcon#read 5, iclass 40, count 2 2006.285.13:29:57.67#ibcon#about to read 6, iclass 40, count 2 2006.285.13:29:57.67#ibcon#read 6, iclass 40, count 2 2006.285.13:29:57.67#ibcon#end of sib2, iclass 40, count 2 2006.285.13:29:57.67#ibcon#*after write, iclass 40, count 2 2006.285.13:29:57.67#ibcon#*before return 0, iclass 40, count 2 2006.285.13:29:57.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:29:57.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:29:57.67#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.13:29:57.67#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:57.67#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:29:57.79#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:29:57.79#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:29:57.79#ibcon#enter wrdev, iclass 40, count 0 2006.285.13:29:57.79#ibcon#first serial, iclass 40, count 0 2006.285.13:29:57.79#ibcon#enter sib2, iclass 40, count 0 2006.285.13:29:57.79#ibcon#flushed, iclass 40, count 0 2006.285.13:29:57.79#ibcon#about to write, iclass 40, count 0 2006.285.13:29:57.79#ibcon#wrote, iclass 40, count 0 2006.285.13:29:57.79#ibcon#about to read 3, iclass 40, count 0 2006.285.13:29:57.81#ibcon#read 3, iclass 40, count 0 2006.285.13:29:57.81#ibcon#about to read 4, iclass 40, count 0 2006.285.13:29:57.81#ibcon#read 4, iclass 40, count 0 2006.285.13:29:57.81#ibcon#about to read 5, iclass 40, count 0 2006.285.13:29:57.81#ibcon#read 5, iclass 40, count 0 2006.285.13:29:57.81#ibcon#about to read 6, iclass 40, count 0 2006.285.13:29:57.81#ibcon#read 6, iclass 40, count 0 2006.285.13:29:57.81#ibcon#end of sib2, iclass 40, count 0 2006.285.13:29:57.81#ibcon#*mode == 0, iclass 40, count 0 2006.285.13:29:57.81#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.13:29:57.81#ibcon#[25=USB\r\n] 2006.285.13:29:57.81#ibcon#*before write, iclass 40, count 0 2006.285.13:29:57.81#ibcon#enter sib2, iclass 40, count 0 2006.285.13:29:57.81#ibcon#flushed, iclass 40, count 0 2006.285.13:29:57.81#ibcon#about to write, iclass 40, count 0 2006.285.13:29:57.81#ibcon#wrote, iclass 40, count 0 2006.285.13:29:57.81#ibcon#about to read 3, iclass 40, count 0 2006.285.13:29:57.84#ibcon#read 3, iclass 40, count 0 2006.285.13:29:57.84#ibcon#about to read 4, iclass 40, count 0 2006.285.13:29:57.84#ibcon#read 4, iclass 40, count 0 2006.285.13:29:57.84#ibcon#about to read 5, iclass 40, count 0 2006.285.13:29:57.84#ibcon#read 5, iclass 40, count 0 2006.285.13:29:57.84#ibcon#about to read 6, iclass 40, count 0 2006.285.13:29:57.84#ibcon#read 6, iclass 40, count 0 2006.285.13:29:57.84#ibcon#end of sib2, iclass 40, count 0 2006.285.13:29:57.84#ibcon#*after write, iclass 40, count 0 2006.285.13:29:57.84#ibcon#*before return 0, iclass 40, count 0 2006.285.13:29:57.84#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:29:57.84#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:29:57.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.13:29:57.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.13:29:57.84$vck44/valo=7,864.99 2006.285.13:29:57.84#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.13:29:57.84#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.13:29:57.84#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:57.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:29:57.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:29:57.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:29:57.84#ibcon#enter wrdev, iclass 4, count 0 2006.285.13:29:57.84#ibcon#first serial, iclass 4, count 0 2006.285.13:29:57.84#ibcon#enter sib2, iclass 4, count 0 2006.285.13:29:57.84#ibcon#flushed, iclass 4, count 0 2006.285.13:29:57.84#ibcon#about to write, iclass 4, count 0 2006.285.13:29:57.84#ibcon#wrote, iclass 4, count 0 2006.285.13:29:57.84#ibcon#about to read 3, iclass 4, count 0 2006.285.13:29:57.86#ibcon#read 3, iclass 4, count 0 2006.285.13:29:57.86#ibcon#about to read 4, iclass 4, count 0 2006.285.13:29:57.86#ibcon#read 4, iclass 4, count 0 2006.285.13:29:57.86#ibcon#about to read 5, iclass 4, count 0 2006.285.13:29:57.86#ibcon#read 5, iclass 4, count 0 2006.285.13:29:57.86#ibcon#about to read 6, iclass 4, count 0 2006.285.13:29:57.86#ibcon#read 6, iclass 4, count 0 2006.285.13:29:57.86#ibcon#end of sib2, iclass 4, count 0 2006.285.13:29:57.86#ibcon#*mode == 0, iclass 4, count 0 2006.285.13:29:57.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.13:29:57.86#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:29:57.86#ibcon#*before write, iclass 4, count 0 2006.285.13:29:57.86#ibcon#enter sib2, iclass 4, count 0 2006.285.13:29:57.86#ibcon#flushed, iclass 4, count 0 2006.285.13:29:57.86#ibcon#about to write, iclass 4, count 0 2006.285.13:29:57.86#ibcon#wrote, iclass 4, count 0 2006.285.13:29:57.86#ibcon#about to read 3, iclass 4, count 0 2006.285.13:29:57.90#ibcon#read 3, iclass 4, count 0 2006.285.13:29:57.90#ibcon#about to read 4, iclass 4, count 0 2006.285.13:29:57.90#ibcon#read 4, iclass 4, count 0 2006.285.13:29:57.90#ibcon#about to read 5, iclass 4, count 0 2006.285.13:29:57.90#ibcon#read 5, iclass 4, count 0 2006.285.13:29:57.90#ibcon#about to read 6, iclass 4, count 0 2006.285.13:29:57.90#ibcon#read 6, iclass 4, count 0 2006.285.13:29:57.90#ibcon#end of sib2, iclass 4, count 0 2006.285.13:29:57.90#ibcon#*after write, iclass 4, count 0 2006.285.13:29:57.90#ibcon#*before return 0, iclass 4, count 0 2006.285.13:29:57.90#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:29:57.90#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:29:57.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.13:29:57.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.13:29:57.90$vck44/va=7,4 2006.285.13:29:57.90#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.13:29:57.90#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.13:29:57.90#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:57.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:29:57.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:29:57.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:29:57.96#ibcon#enter wrdev, iclass 6, count 2 2006.285.13:29:57.96#ibcon#first serial, iclass 6, count 2 2006.285.13:29:57.96#ibcon#enter sib2, iclass 6, count 2 2006.285.13:29:57.96#ibcon#flushed, iclass 6, count 2 2006.285.13:29:57.96#ibcon#about to write, iclass 6, count 2 2006.285.13:29:57.96#ibcon#wrote, iclass 6, count 2 2006.285.13:29:57.96#ibcon#about to read 3, iclass 6, count 2 2006.285.13:29:57.98#ibcon#read 3, iclass 6, count 2 2006.285.13:29:57.98#ibcon#about to read 4, iclass 6, count 2 2006.285.13:29:57.98#ibcon#read 4, iclass 6, count 2 2006.285.13:29:57.98#ibcon#about to read 5, iclass 6, count 2 2006.285.13:29:57.98#ibcon#read 5, iclass 6, count 2 2006.285.13:29:57.98#ibcon#about to read 6, iclass 6, count 2 2006.285.13:29:57.98#ibcon#read 6, iclass 6, count 2 2006.285.13:29:57.98#ibcon#end of sib2, iclass 6, count 2 2006.285.13:29:57.98#ibcon#*mode == 0, iclass 6, count 2 2006.285.13:29:57.98#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.13:29:57.98#ibcon#[25=AT07-04\r\n] 2006.285.13:29:57.98#ibcon#*before write, iclass 6, count 2 2006.285.13:29:57.98#ibcon#enter sib2, iclass 6, count 2 2006.285.13:29:57.98#ibcon#flushed, iclass 6, count 2 2006.285.13:29:57.98#ibcon#about to write, iclass 6, count 2 2006.285.13:29:57.98#ibcon#wrote, iclass 6, count 2 2006.285.13:29:57.98#ibcon#about to read 3, iclass 6, count 2 2006.285.13:29:58.00#abcon#<5=/04 1.5 2.4 19.10 971015.3\r\n> 2006.285.13:29:58.01#ibcon#read 3, iclass 6, count 2 2006.285.13:29:58.01#ibcon#about to read 4, iclass 6, count 2 2006.285.13:29:58.01#ibcon#read 4, iclass 6, count 2 2006.285.13:29:58.01#ibcon#about to read 5, iclass 6, count 2 2006.285.13:29:58.01#ibcon#read 5, iclass 6, count 2 2006.285.13:29:58.01#ibcon#about to read 6, iclass 6, count 2 2006.285.13:29:58.01#ibcon#read 6, iclass 6, count 2 2006.285.13:29:58.01#ibcon#end of sib2, iclass 6, count 2 2006.285.13:29:58.01#ibcon#*after write, iclass 6, count 2 2006.285.13:29:58.01#ibcon#*before return 0, iclass 6, count 2 2006.285.13:29:58.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:29:58.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:29:58.01#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.13:29:58.01#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:58.01#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:29:58.02#abcon#{5=INTERFACE CLEAR} 2006.285.13:29:58.13#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:29:58.13#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:29:58.13#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:29:58.13#ibcon#enter wrdev, iclass 6, count 0 2006.285.13:29:58.13#ibcon#first serial, iclass 6, count 0 2006.285.13:29:58.13#ibcon#enter sib2, iclass 6, count 0 2006.285.13:29:58.13#ibcon#flushed, iclass 6, count 0 2006.285.13:29:58.13#ibcon#about to write, iclass 6, count 0 2006.285.13:29:58.13#ibcon#wrote, iclass 6, count 0 2006.285.13:29:58.13#ibcon#about to read 3, iclass 6, count 0 2006.285.13:29:58.15#ibcon#read 3, iclass 6, count 0 2006.285.13:29:58.15#ibcon#about to read 4, iclass 6, count 0 2006.285.13:29:58.15#ibcon#read 4, iclass 6, count 0 2006.285.13:29:58.15#ibcon#about to read 5, iclass 6, count 0 2006.285.13:29:58.15#ibcon#read 5, iclass 6, count 0 2006.285.13:29:58.15#ibcon#about to read 6, iclass 6, count 0 2006.285.13:29:58.15#ibcon#read 6, iclass 6, count 0 2006.285.13:29:58.15#ibcon#end of sib2, iclass 6, count 0 2006.285.13:29:58.15#ibcon#*mode == 0, iclass 6, count 0 2006.285.13:29:58.15#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.13:29:58.15#ibcon#[25=USB\r\n] 2006.285.13:29:58.15#ibcon#*before write, iclass 6, count 0 2006.285.13:29:58.15#ibcon#enter sib2, iclass 6, count 0 2006.285.13:29:58.15#ibcon#flushed, iclass 6, count 0 2006.285.13:29:58.15#ibcon#about to write, iclass 6, count 0 2006.285.13:29:58.15#ibcon#wrote, iclass 6, count 0 2006.285.13:29:58.15#ibcon#about to read 3, iclass 6, count 0 2006.285.13:29:58.18#ibcon#read 3, iclass 6, count 0 2006.285.13:29:58.18#ibcon#about to read 4, iclass 6, count 0 2006.285.13:29:58.18#ibcon#read 4, iclass 6, count 0 2006.285.13:29:58.18#ibcon#about to read 5, iclass 6, count 0 2006.285.13:29:58.18#ibcon#read 5, iclass 6, count 0 2006.285.13:29:58.18#ibcon#about to read 6, iclass 6, count 0 2006.285.13:29:58.18#ibcon#read 6, iclass 6, count 0 2006.285.13:29:58.18#ibcon#end of sib2, iclass 6, count 0 2006.285.13:29:58.18#ibcon#*after write, iclass 6, count 0 2006.285.13:29:58.18#ibcon#*before return 0, iclass 6, count 0 2006.285.13:29:58.18#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:29:58.18#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:29:58.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.13:29:58.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.13:29:58.18$vck44/valo=8,884.99 2006.285.13:29:58.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.13:29:58.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.13:29:58.18#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:58.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:29:58.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:29:58.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:29:58.18#ibcon#enter wrdev, iclass 14, count 0 2006.285.13:29:58.18#ibcon#first serial, iclass 14, count 0 2006.285.13:29:58.18#ibcon#enter sib2, iclass 14, count 0 2006.285.13:29:58.18#ibcon#flushed, iclass 14, count 0 2006.285.13:29:58.18#ibcon#about to write, iclass 14, count 0 2006.285.13:29:58.18#ibcon#wrote, iclass 14, count 0 2006.285.13:29:58.18#ibcon#about to read 3, iclass 14, count 0 2006.285.13:29:58.20#ibcon#read 3, iclass 14, count 0 2006.285.13:29:58.20#ibcon#about to read 4, iclass 14, count 0 2006.285.13:29:58.20#ibcon#read 4, iclass 14, count 0 2006.285.13:29:58.20#ibcon#about to read 5, iclass 14, count 0 2006.285.13:29:58.20#ibcon#read 5, iclass 14, count 0 2006.285.13:29:58.20#ibcon#about to read 6, iclass 14, count 0 2006.285.13:29:58.20#ibcon#read 6, iclass 14, count 0 2006.285.13:29:58.20#ibcon#end of sib2, iclass 14, count 0 2006.285.13:29:58.20#ibcon#*mode == 0, iclass 14, count 0 2006.285.13:29:58.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.13:29:58.20#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:29:58.20#ibcon#*before write, iclass 14, count 0 2006.285.13:29:58.20#ibcon#enter sib2, iclass 14, count 0 2006.285.13:29:58.20#ibcon#flushed, iclass 14, count 0 2006.285.13:29:58.20#ibcon#about to write, iclass 14, count 0 2006.285.13:29:58.20#ibcon#wrote, iclass 14, count 0 2006.285.13:29:58.20#ibcon#about to read 3, iclass 14, count 0 2006.285.13:29:58.24#ibcon#read 3, iclass 14, count 0 2006.285.13:29:58.24#ibcon#about to read 4, iclass 14, count 0 2006.285.13:29:58.24#ibcon#read 4, iclass 14, count 0 2006.285.13:29:58.24#ibcon#about to read 5, iclass 14, count 0 2006.285.13:29:58.24#ibcon#read 5, iclass 14, count 0 2006.285.13:29:58.24#ibcon#about to read 6, iclass 14, count 0 2006.285.13:29:58.24#ibcon#read 6, iclass 14, count 0 2006.285.13:29:58.24#ibcon#end of sib2, iclass 14, count 0 2006.285.13:29:58.24#ibcon#*after write, iclass 14, count 0 2006.285.13:29:58.24#ibcon#*before return 0, iclass 14, count 0 2006.285.13:29:58.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:29:58.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:29:58.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.13:29:58.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.13:29:58.24$vck44/va=8,3 2006.285.13:29:58.24#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.13:29:58.24#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.13:29:58.24#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:58.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:29:58.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:29:58.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:29:58.30#ibcon#enter wrdev, iclass 16, count 2 2006.285.13:29:58.30#ibcon#first serial, iclass 16, count 2 2006.285.13:29:58.30#ibcon#enter sib2, iclass 16, count 2 2006.285.13:29:58.30#ibcon#flushed, iclass 16, count 2 2006.285.13:29:58.30#ibcon#about to write, iclass 16, count 2 2006.285.13:29:58.30#ibcon#wrote, iclass 16, count 2 2006.285.13:29:58.30#ibcon#about to read 3, iclass 16, count 2 2006.285.13:29:58.32#ibcon#read 3, iclass 16, count 2 2006.285.13:29:58.32#ibcon#about to read 4, iclass 16, count 2 2006.285.13:29:58.32#ibcon#read 4, iclass 16, count 2 2006.285.13:29:58.32#ibcon#about to read 5, iclass 16, count 2 2006.285.13:29:58.32#ibcon#read 5, iclass 16, count 2 2006.285.13:29:58.32#ibcon#about to read 6, iclass 16, count 2 2006.285.13:29:58.32#ibcon#read 6, iclass 16, count 2 2006.285.13:29:58.32#ibcon#end of sib2, iclass 16, count 2 2006.285.13:29:58.32#ibcon#*mode == 0, iclass 16, count 2 2006.285.13:29:58.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.13:29:58.32#ibcon#[25=AT08-03\r\n] 2006.285.13:29:58.32#ibcon#*before write, iclass 16, count 2 2006.285.13:29:58.32#ibcon#enter sib2, iclass 16, count 2 2006.285.13:29:58.32#ibcon#flushed, iclass 16, count 2 2006.285.13:29:58.32#ibcon#about to write, iclass 16, count 2 2006.285.13:29:58.32#ibcon#wrote, iclass 16, count 2 2006.285.13:29:58.32#ibcon#about to read 3, iclass 16, count 2 2006.285.13:29:58.35#ibcon#read 3, iclass 16, count 2 2006.285.13:29:58.35#ibcon#about to read 4, iclass 16, count 2 2006.285.13:29:58.35#ibcon#read 4, iclass 16, count 2 2006.285.13:29:58.35#ibcon#about to read 5, iclass 16, count 2 2006.285.13:29:58.35#ibcon#read 5, iclass 16, count 2 2006.285.13:29:58.35#ibcon#about to read 6, iclass 16, count 2 2006.285.13:29:58.35#ibcon#read 6, iclass 16, count 2 2006.285.13:29:58.35#ibcon#end of sib2, iclass 16, count 2 2006.285.13:29:58.35#ibcon#*after write, iclass 16, count 2 2006.285.13:29:58.35#ibcon#*before return 0, iclass 16, count 2 2006.285.13:29:58.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:29:58.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.13:29:58.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.13:29:58.35#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:58.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:29:58.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:29:58.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:29:58.47#ibcon#enter wrdev, iclass 16, count 0 2006.285.13:29:58.47#ibcon#first serial, iclass 16, count 0 2006.285.13:29:58.47#ibcon#enter sib2, iclass 16, count 0 2006.285.13:29:58.47#ibcon#flushed, iclass 16, count 0 2006.285.13:29:58.47#ibcon#about to write, iclass 16, count 0 2006.285.13:29:58.47#ibcon#wrote, iclass 16, count 0 2006.285.13:29:58.47#ibcon#about to read 3, iclass 16, count 0 2006.285.13:29:58.49#ibcon#read 3, iclass 16, count 0 2006.285.13:29:58.49#ibcon#about to read 4, iclass 16, count 0 2006.285.13:29:58.49#ibcon#read 4, iclass 16, count 0 2006.285.13:29:58.49#ibcon#about to read 5, iclass 16, count 0 2006.285.13:29:58.49#ibcon#read 5, iclass 16, count 0 2006.285.13:29:58.49#ibcon#about to read 6, iclass 16, count 0 2006.285.13:29:58.49#ibcon#read 6, iclass 16, count 0 2006.285.13:29:58.49#ibcon#end of sib2, iclass 16, count 0 2006.285.13:29:58.49#ibcon#*mode == 0, iclass 16, count 0 2006.285.13:29:58.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.13:29:58.49#ibcon#[25=USB\r\n] 2006.285.13:29:58.49#ibcon#*before write, iclass 16, count 0 2006.285.13:29:58.49#ibcon#enter sib2, iclass 16, count 0 2006.285.13:29:58.49#ibcon#flushed, iclass 16, count 0 2006.285.13:29:58.49#ibcon#about to write, iclass 16, count 0 2006.285.13:29:58.49#ibcon#wrote, iclass 16, count 0 2006.285.13:29:58.49#ibcon#about to read 3, iclass 16, count 0 2006.285.13:29:58.52#ibcon#read 3, iclass 16, count 0 2006.285.13:29:58.52#ibcon#about to read 4, iclass 16, count 0 2006.285.13:29:58.52#ibcon#read 4, iclass 16, count 0 2006.285.13:29:58.52#ibcon#about to read 5, iclass 16, count 0 2006.285.13:29:58.52#ibcon#read 5, iclass 16, count 0 2006.285.13:29:58.52#ibcon#about to read 6, iclass 16, count 0 2006.285.13:29:58.52#ibcon#read 6, iclass 16, count 0 2006.285.13:29:58.52#ibcon#end of sib2, iclass 16, count 0 2006.285.13:29:58.52#ibcon#*after write, iclass 16, count 0 2006.285.13:29:58.52#ibcon#*before return 0, iclass 16, count 0 2006.285.13:29:58.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:29:58.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.13:29:58.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.13:29:58.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.13:29:58.52$vck44/vblo=1,629.99 2006.285.13:29:58.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.13:29:58.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.13:29:58.52#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:58.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:29:58.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:29:58.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:29:58.52#ibcon#enter wrdev, iclass 18, count 0 2006.285.13:29:58.52#ibcon#first serial, iclass 18, count 0 2006.285.13:29:58.52#ibcon#enter sib2, iclass 18, count 0 2006.285.13:29:58.52#ibcon#flushed, iclass 18, count 0 2006.285.13:29:58.52#ibcon#about to write, iclass 18, count 0 2006.285.13:29:58.52#ibcon#wrote, iclass 18, count 0 2006.285.13:29:58.52#ibcon#about to read 3, iclass 18, count 0 2006.285.13:29:58.54#ibcon#read 3, iclass 18, count 0 2006.285.13:29:58.54#ibcon#about to read 4, iclass 18, count 0 2006.285.13:29:58.54#ibcon#read 4, iclass 18, count 0 2006.285.13:29:58.54#ibcon#about to read 5, iclass 18, count 0 2006.285.13:29:58.54#ibcon#read 5, iclass 18, count 0 2006.285.13:29:58.54#ibcon#about to read 6, iclass 18, count 0 2006.285.13:29:58.54#ibcon#read 6, iclass 18, count 0 2006.285.13:29:58.54#ibcon#end of sib2, iclass 18, count 0 2006.285.13:29:58.54#ibcon#*mode == 0, iclass 18, count 0 2006.285.13:29:58.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.13:29:58.54#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:29:58.54#ibcon#*before write, iclass 18, count 0 2006.285.13:29:58.54#ibcon#enter sib2, iclass 18, count 0 2006.285.13:29:58.54#ibcon#flushed, iclass 18, count 0 2006.285.13:29:58.54#ibcon#about to write, iclass 18, count 0 2006.285.13:29:58.54#ibcon#wrote, iclass 18, count 0 2006.285.13:29:58.54#ibcon#about to read 3, iclass 18, count 0 2006.285.13:29:58.58#ibcon#read 3, iclass 18, count 0 2006.285.13:29:58.58#ibcon#about to read 4, iclass 18, count 0 2006.285.13:29:58.58#ibcon#read 4, iclass 18, count 0 2006.285.13:29:58.58#ibcon#about to read 5, iclass 18, count 0 2006.285.13:29:58.58#ibcon#read 5, iclass 18, count 0 2006.285.13:29:58.58#ibcon#about to read 6, iclass 18, count 0 2006.285.13:29:58.58#ibcon#read 6, iclass 18, count 0 2006.285.13:29:58.58#ibcon#end of sib2, iclass 18, count 0 2006.285.13:29:58.58#ibcon#*after write, iclass 18, count 0 2006.285.13:29:58.58#ibcon#*before return 0, iclass 18, count 0 2006.285.13:29:58.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:29:58.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.13:29:58.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.13:29:58.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.13:29:58.58$vck44/vb=1,4 2006.285.13:29:58.58#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.13:29:58.58#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.13:29:58.58#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:58.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:29:58.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:29:58.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:29:58.58#ibcon#enter wrdev, iclass 20, count 2 2006.285.13:29:58.58#ibcon#first serial, iclass 20, count 2 2006.285.13:29:58.58#ibcon#enter sib2, iclass 20, count 2 2006.285.13:29:58.58#ibcon#flushed, iclass 20, count 2 2006.285.13:29:58.58#ibcon#about to write, iclass 20, count 2 2006.285.13:29:58.58#ibcon#wrote, iclass 20, count 2 2006.285.13:29:58.58#ibcon#about to read 3, iclass 20, count 2 2006.285.13:29:58.60#ibcon#read 3, iclass 20, count 2 2006.285.13:29:58.60#ibcon#about to read 4, iclass 20, count 2 2006.285.13:29:58.60#ibcon#read 4, iclass 20, count 2 2006.285.13:29:58.60#ibcon#about to read 5, iclass 20, count 2 2006.285.13:29:58.60#ibcon#read 5, iclass 20, count 2 2006.285.13:29:58.60#ibcon#about to read 6, iclass 20, count 2 2006.285.13:29:58.60#ibcon#read 6, iclass 20, count 2 2006.285.13:29:58.60#ibcon#end of sib2, iclass 20, count 2 2006.285.13:29:58.60#ibcon#*mode == 0, iclass 20, count 2 2006.285.13:29:58.60#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.13:29:58.60#ibcon#[27=AT01-04\r\n] 2006.285.13:29:58.60#ibcon#*before write, iclass 20, count 2 2006.285.13:29:58.60#ibcon#enter sib2, iclass 20, count 2 2006.285.13:29:58.60#ibcon#flushed, iclass 20, count 2 2006.285.13:29:58.60#ibcon#about to write, iclass 20, count 2 2006.285.13:29:58.60#ibcon#wrote, iclass 20, count 2 2006.285.13:29:58.60#ibcon#about to read 3, iclass 20, count 2 2006.285.13:29:58.63#ibcon#read 3, iclass 20, count 2 2006.285.13:29:58.63#ibcon#about to read 4, iclass 20, count 2 2006.285.13:29:58.63#ibcon#read 4, iclass 20, count 2 2006.285.13:29:58.63#ibcon#about to read 5, iclass 20, count 2 2006.285.13:29:58.63#ibcon#read 5, iclass 20, count 2 2006.285.13:29:58.63#ibcon#about to read 6, iclass 20, count 2 2006.285.13:29:58.63#ibcon#read 6, iclass 20, count 2 2006.285.13:29:58.63#ibcon#end of sib2, iclass 20, count 2 2006.285.13:29:58.63#ibcon#*after write, iclass 20, count 2 2006.285.13:29:58.63#ibcon#*before return 0, iclass 20, count 2 2006.285.13:29:58.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:29:58.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.13:29:58.63#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.13:29:58.63#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:58.63#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:29:58.75#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:29:58.75#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:29:58.75#ibcon#enter wrdev, iclass 20, count 0 2006.285.13:29:58.75#ibcon#first serial, iclass 20, count 0 2006.285.13:29:58.75#ibcon#enter sib2, iclass 20, count 0 2006.285.13:29:58.75#ibcon#flushed, iclass 20, count 0 2006.285.13:29:58.75#ibcon#about to write, iclass 20, count 0 2006.285.13:29:58.75#ibcon#wrote, iclass 20, count 0 2006.285.13:29:58.75#ibcon#about to read 3, iclass 20, count 0 2006.285.13:29:58.77#ibcon#read 3, iclass 20, count 0 2006.285.13:29:58.77#ibcon#about to read 4, iclass 20, count 0 2006.285.13:29:58.77#ibcon#read 4, iclass 20, count 0 2006.285.13:29:58.77#ibcon#about to read 5, iclass 20, count 0 2006.285.13:29:58.77#ibcon#read 5, iclass 20, count 0 2006.285.13:29:58.77#ibcon#about to read 6, iclass 20, count 0 2006.285.13:29:58.77#ibcon#read 6, iclass 20, count 0 2006.285.13:29:58.77#ibcon#end of sib2, iclass 20, count 0 2006.285.13:29:58.77#ibcon#*mode == 0, iclass 20, count 0 2006.285.13:29:58.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.13:29:58.77#ibcon#[27=USB\r\n] 2006.285.13:29:58.77#ibcon#*before write, iclass 20, count 0 2006.285.13:29:58.77#ibcon#enter sib2, iclass 20, count 0 2006.285.13:29:58.77#ibcon#flushed, iclass 20, count 0 2006.285.13:29:58.77#ibcon#about to write, iclass 20, count 0 2006.285.13:29:58.77#ibcon#wrote, iclass 20, count 0 2006.285.13:29:58.77#ibcon#about to read 3, iclass 20, count 0 2006.285.13:29:58.80#ibcon#read 3, iclass 20, count 0 2006.285.13:29:58.80#ibcon#about to read 4, iclass 20, count 0 2006.285.13:29:58.80#ibcon#read 4, iclass 20, count 0 2006.285.13:29:58.80#ibcon#about to read 5, iclass 20, count 0 2006.285.13:29:58.80#ibcon#read 5, iclass 20, count 0 2006.285.13:29:58.80#ibcon#about to read 6, iclass 20, count 0 2006.285.13:29:58.80#ibcon#read 6, iclass 20, count 0 2006.285.13:29:58.80#ibcon#end of sib2, iclass 20, count 0 2006.285.13:29:58.80#ibcon#*after write, iclass 20, count 0 2006.285.13:29:58.80#ibcon#*before return 0, iclass 20, count 0 2006.285.13:29:58.80#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:29:58.80#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.13:29:58.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.13:29:58.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.13:29:58.80$vck44/vblo=2,634.99 2006.285.13:29:58.80#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.13:29:58.80#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.13:29:58.80#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:58.80#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:29:58.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:29:58.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:29:58.80#ibcon#enter wrdev, iclass 22, count 0 2006.285.13:29:58.80#ibcon#first serial, iclass 22, count 0 2006.285.13:29:58.80#ibcon#enter sib2, iclass 22, count 0 2006.285.13:29:58.80#ibcon#flushed, iclass 22, count 0 2006.285.13:29:58.80#ibcon#about to write, iclass 22, count 0 2006.285.13:29:58.80#ibcon#wrote, iclass 22, count 0 2006.285.13:29:58.80#ibcon#about to read 3, iclass 22, count 0 2006.285.13:29:58.82#ibcon#read 3, iclass 22, count 0 2006.285.13:29:58.82#ibcon#about to read 4, iclass 22, count 0 2006.285.13:29:58.82#ibcon#read 4, iclass 22, count 0 2006.285.13:29:58.82#ibcon#about to read 5, iclass 22, count 0 2006.285.13:29:58.82#ibcon#read 5, iclass 22, count 0 2006.285.13:29:58.82#ibcon#about to read 6, iclass 22, count 0 2006.285.13:29:58.82#ibcon#read 6, iclass 22, count 0 2006.285.13:29:58.82#ibcon#end of sib2, iclass 22, count 0 2006.285.13:29:58.82#ibcon#*mode == 0, iclass 22, count 0 2006.285.13:29:58.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.13:29:58.82#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:29:58.82#ibcon#*before write, iclass 22, count 0 2006.285.13:29:58.82#ibcon#enter sib2, iclass 22, count 0 2006.285.13:29:58.82#ibcon#flushed, iclass 22, count 0 2006.285.13:29:58.82#ibcon#about to write, iclass 22, count 0 2006.285.13:29:58.82#ibcon#wrote, iclass 22, count 0 2006.285.13:29:58.82#ibcon#about to read 3, iclass 22, count 0 2006.285.13:29:58.86#ibcon#read 3, iclass 22, count 0 2006.285.13:29:58.86#ibcon#about to read 4, iclass 22, count 0 2006.285.13:29:58.86#ibcon#read 4, iclass 22, count 0 2006.285.13:29:58.86#ibcon#about to read 5, iclass 22, count 0 2006.285.13:29:58.86#ibcon#read 5, iclass 22, count 0 2006.285.13:29:58.86#ibcon#about to read 6, iclass 22, count 0 2006.285.13:29:58.86#ibcon#read 6, iclass 22, count 0 2006.285.13:29:58.86#ibcon#end of sib2, iclass 22, count 0 2006.285.13:29:58.86#ibcon#*after write, iclass 22, count 0 2006.285.13:29:58.86#ibcon#*before return 0, iclass 22, count 0 2006.285.13:29:58.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:29:58.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.13:29:58.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.13:29:58.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.13:29:58.86$vck44/vb=2,5 2006.285.13:29:58.86#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.13:29:58.86#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.13:29:58.86#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:58.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:29:58.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:29:58.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:29:58.92#ibcon#enter wrdev, iclass 24, count 2 2006.285.13:29:58.92#ibcon#first serial, iclass 24, count 2 2006.285.13:29:58.92#ibcon#enter sib2, iclass 24, count 2 2006.285.13:29:58.92#ibcon#flushed, iclass 24, count 2 2006.285.13:29:58.92#ibcon#about to write, iclass 24, count 2 2006.285.13:29:58.92#ibcon#wrote, iclass 24, count 2 2006.285.13:29:58.92#ibcon#about to read 3, iclass 24, count 2 2006.285.13:29:58.94#ibcon#read 3, iclass 24, count 2 2006.285.13:29:58.94#ibcon#about to read 4, iclass 24, count 2 2006.285.13:29:58.94#ibcon#read 4, iclass 24, count 2 2006.285.13:29:58.94#ibcon#about to read 5, iclass 24, count 2 2006.285.13:29:58.94#ibcon#read 5, iclass 24, count 2 2006.285.13:29:58.94#ibcon#about to read 6, iclass 24, count 2 2006.285.13:29:58.94#ibcon#read 6, iclass 24, count 2 2006.285.13:29:58.94#ibcon#end of sib2, iclass 24, count 2 2006.285.13:29:58.94#ibcon#*mode == 0, iclass 24, count 2 2006.285.13:29:58.94#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.13:29:58.94#ibcon#[27=AT02-05\r\n] 2006.285.13:29:58.94#ibcon#*before write, iclass 24, count 2 2006.285.13:29:58.94#ibcon#enter sib2, iclass 24, count 2 2006.285.13:29:58.94#ibcon#flushed, iclass 24, count 2 2006.285.13:29:58.94#ibcon#about to write, iclass 24, count 2 2006.285.13:29:58.94#ibcon#wrote, iclass 24, count 2 2006.285.13:29:58.94#ibcon#about to read 3, iclass 24, count 2 2006.285.13:29:58.97#ibcon#read 3, iclass 24, count 2 2006.285.13:29:58.97#ibcon#about to read 4, iclass 24, count 2 2006.285.13:29:58.97#ibcon#read 4, iclass 24, count 2 2006.285.13:29:58.97#ibcon#about to read 5, iclass 24, count 2 2006.285.13:29:58.97#ibcon#read 5, iclass 24, count 2 2006.285.13:29:58.97#ibcon#about to read 6, iclass 24, count 2 2006.285.13:29:58.97#ibcon#read 6, iclass 24, count 2 2006.285.13:29:58.97#ibcon#end of sib2, iclass 24, count 2 2006.285.13:29:58.97#ibcon#*after write, iclass 24, count 2 2006.285.13:29:58.97#ibcon#*before return 0, iclass 24, count 2 2006.285.13:29:58.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:29:58.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.13:29:58.97#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.13:29:58.97#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:58.97#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:29:59.09#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:29:59.31#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:29:59.31#ibcon#enter wrdev, iclass 24, count 0 2006.285.13:29:59.31#ibcon#first serial, iclass 24, count 0 2006.285.13:29:59.31#ibcon#enter sib2, iclass 24, count 0 2006.285.13:29:59.31#ibcon#flushed, iclass 24, count 0 2006.285.13:29:59.31#ibcon#about to write, iclass 24, count 0 2006.285.13:29:59.31#ibcon#wrote, iclass 24, count 0 2006.285.13:29:59.31#ibcon#about to read 3, iclass 24, count 0 2006.285.13:29:59.33#ibcon#read 3, iclass 24, count 0 2006.285.13:29:59.33#ibcon#about to read 4, iclass 24, count 0 2006.285.13:29:59.33#ibcon#read 4, iclass 24, count 0 2006.285.13:29:59.33#ibcon#about to read 5, iclass 24, count 0 2006.285.13:29:59.33#ibcon#read 5, iclass 24, count 0 2006.285.13:29:59.33#ibcon#about to read 6, iclass 24, count 0 2006.285.13:29:59.33#ibcon#read 6, iclass 24, count 0 2006.285.13:29:59.33#ibcon#end of sib2, iclass 24, count 0 2006.285.13:29:59.33#ibcon#*mode == 0, iclass 24, count 0 2006.285.13:29:59.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.13:29:59.33#ibcon#[27=USB\r\n] 2006.285.13:29:59.33#ibcon#*before write, iclass 24, count 0 2006.285.13:29:59.33#ibcon#enter sib2, iclass 24, count 0 2006.285.13:29:59.33#ibcon#flushed, iclass 24, count 0 2006.285.13:29:59.33#ibcon#about to write, iclass 24, count 0 2006.285.13:29:59.33#ibcon#wrote, iclass 24, count 0 2006.285.13:29:59.33#ibcon#about to read 3, iclass 24, count 0 2006.285.13:29:59.36#ibcon#read 3, iclass 24, count 0 2006.285.13:29:59.36#ibcon#about to read 4, iclass 24, count 0 2006.285.13:29:59.36#ibcon#read 4, iclass 24, count 0 2006.285.13:29:59.36#ibcon#about to read 5, iclass 24, count 0 2006.285.13:29:59.36#ibcon#read 5, iclass 24, count 0 2006.285.13:29:59.36#ibcon#about to read 6, iclass 24, count 0 2006.285.13:29:59.36#ibcon#read 6, iclass 24, count 0 2006.285.13:29:59.36#ibcon#end of sib2, iclass 24, count 0 2006.285.13:29:59.36#ibcon#*after write, iclass 24, count 0 2006.285.13:29:59.36#ibcon#*before return 0, iclass 24, count 0 2006.285.13:29:59.36#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:29:59.36#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.13:29:59.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.13:29:59.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.13:29:59.36$vck44/vblo=3,649.99 2006.285.13:29:59.36#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.13:29:59.36#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.13:29:59.36#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:59.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:29:59.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:29:59.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:29:59.36#ibcon#enter wrdev, iclass 26, count 0 2006.285.13:29:59.36#ibcon#first serial, iclass 26, count 0 2006.285.13:29:59.36#ibcon#enter sib2, iclass 26, count 0 2006.285.13:29:59.36#ibcon#flushed, iclass 26, count 0 2006.285.13:29:59.36#ibcon#about to write, iclass 26, count 0 2006.285.13:29:59.36#ibcon#wrote, iclass 26, count 0 2006.285.13:29:59.36#ibcon#about to read 3, iclass 26, count 0 2006.285.13:29:59.38#ibcon#read 3, iclass 26, count 0 2006.285.13:29:59.38#ibcon#about to read 4, iclass 26, count 0 2006.285.13:29:59.38#ibcon#read 4, iclass 26, count 0 2006.285.13:29:59.38#ibcon#about to read 5, iclass 26, count 0 2006.285.13:29:59.38#ibcon#read 5, iclass 26, count 0 2006.285.13:29:59.38#ibcon#about to read 6, iclass 26, count 0 2006.285.13:29:59.38#ibcon#read 6, iclass 26, count 0 2006.285.13:29:59.38#ibcon#end of sib2, iclass 26, count 0 2006.285.13:29:59.38#ibcon#*mode == 0, iclass 26, count 0 2006.285.13:29:59.38#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.13:29:59.38#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:29:59.38#ibcon#*before write, iclass 26, count 0 2006.285.13:29:59.38#ibcon#enter sib2, iclass 26, count 0 2006.285.13:29:59.38#ibcon#flushed, iclass 26, count 0 2006.285.13:29:59.38#ibcon#about to write, iclass 26, count 0 2006.285.13:29:59.38#ibcon#wrote, iclass 26, count 0 2006.285.13:29:59.38#ibcon#about to read 3, iclass 26, count 0 2006.285.13:29:59.42#ibcon#read 3, iclass 26, count 0 2006.285.13:29:59.42#ibcon#about to read 4, iclass 26, count 0 2006.285.13:29:59.42#ibcon#read 4, iclass 26, count 0 2006.285.13:29:59.42#ibcon#about to read 5, iclass 26, count 0 2006.285.13:29:59.42#ibcon#read 5, iclass 26, count 0 2006.285.13:29:59.42#ibcon#about to read 6, iclass 26, count 0 2006.285.13:29:59.42#ibcon#read 6, iclass 26, count 0 2006.285.13:29:59.42#ibcon#end of sib2, iclass 26, count 0 2006.285.13:29:59.42#ibcon#*after write, iclass 26, count 0 2006.285.13:29:59.42#ibcon#*before return 0, iclass 26, count 0 2006.285.13:29:59.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:29:59.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.13:29:59.42#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.13:29:59.42#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.13:29:59.42$vck44/vb=3,4 2006.285.13:29:59.42#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.13:29:59.42#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.13:29:59.42#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:59.42#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:29:59.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:29:59.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:29:59.48#ibcon#enter wrdev, iclass 28, count 2 2006.285.13:29:59.48#ibcon#first serial, iclass 28, count 2 2006.285.13:29:59.48#ibcon#enter sib2, iclass 28, count 2 2006.285.13:29:59.48#ibcon#flushed, iclass 28, count 2 2006.285.13:29:59.48#ibcon#about to write, iclass 28, count 2 2006.285.13:29:59.48#ibcon#wrote, iclass 28, count 2 2006.285.13:29:59.48#ibcon#about to read 3, iclass 28, count 2 2006.285.13:29:59.50#ibcon#read 3, iclass 28, count 2 2006.285.13:29:59.50#ibcon#about to read 4, iclass 28, count 2 2006.285.13:29:59.50#ibcon#read 4, iclass 28, count 2 2006.285.13:29:59.50#ibcon#about to read 5, iclass 28, count 2 2006.285.13:29:59.50#ibcon#read 5, iclass 28, count 2 2006.285.13:29:59.50#ibcon#about to read 6, iclass 28, count 2 2006.285.13:29:59.50#ibcon#read 6, iclass 28, count 2 2006.285.13:29:59.50#ibcon#end of sib2, iclass 28, count 2 2006.285.13:29:59.50#ibcon#*mode == 0, iclass 28, count 2 2006.285.13:29:59.50#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.13:29:59.50#ibcon#[27=AT03-04\r\n] 2006.285.13:29:59.50#ibcon#*before write, iclass 28, count 2 2006.285.13:29:59.50#ibcon#enter sib2, iclass 28, count 2 2006.285.13:29:59.50#ibcon#flushed, iclass 28, count 2 2006.285.13:29:59.50#ibcon#about to write, iclass 28, count 2 2006.285.13:29:59.50#ibcon#wrote, iclass 28, count 2 2006.285.13:29:59.50#ibcon#about to read 3, iclass 28, count 2 2006.285.13:29:59.53#ibcon#read 3, iclass 28, count 2 2006.285.13:29:59.53#ibcon#about to read 4, iclass 28, count 2 2006.285.13:29:59.53#ibcon#read 4, iclass 28, count 2 2006.285.13:29:59.53#ibcon#about to read 5, iclass 28, count 2 2006.285.13:29:59.53#ibcon#read 5, iclass 28, count 2 2006.285.13:29:59.53#ibcon#about to read 6, iclass 28, count 2 2006.285.13:29:59.53#ibcon#read 6, iclass 28, count 2 2006.285.13:29:59.53#ibcon#end of sib2, iclass 28, count 2 2006.285.13:29:59.53#ibcon#*after write, iclass 28, count 2 2006.285.13:29:59.53#ibcon#*before return 0, iclass 28, count 2 2006.285.13:29:59.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:29:59.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.13:29:59.53#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.13:29:59.53#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:59.53#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:29:59.65#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:29:59.65#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:29:59.65#ibcon#enter wrdev, iclass 28, count 0 2006.285.13:29:59.65#ibcon#first serial, iclass 28, count 0 2006.285.13:29:59.65#ibcon#enter sib2, iclass 28, count 0 2006.285.13:29:59.65#ibcon#flushed, iclass 28, count 0 2006.285.13:29:59.65#ibcon#about to write, iclass 28, count 0 2006.285.13:29:59.65#ibcon#wrote, iclass 28, count 0 2006.285.13:29:59.65#ibcon#about to read 3, iclass 28, count 0 2006.285.13:29:59.67#ibcon#read 3, iclass 28, count 0 2006.285.13:29:59.67#ibcon#about to read 4, iclass 28, count 0 2006.285.13:29:59.67#ibcon#read 4, iclass 28, count 0 2006.285.13:29:59.67#ibcon#about to read 5, iclass 28, count 0 2006.285.13:29:59.67#ibcon#read 5, iclass 28, count 0 2006.285.13:29:59.67#ibcon#about to read 6, iclass 28, count 0 2006.285.13:29:59.67#ibcon#read 6, iclass 28, count 0 2006.285.13:29:59.67#ibcon#end of sib2, iclass 28, count 0 2006.285.13:29:59.67#ibcon#*mode == 0, iclass 28, count 0 2006.285.13:29:59.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.13:29:59.67#ibcon#[27=USB\r\n] 2006.285.13:29:59.67#ibcon#*before write, iclass 28, count 0 2006.285.13:29:59.67#ibcon#enter sib2, iclass 28, count 0 2006.285.13:29:59.67#ibcon#flushed, iclass 28, count 0 2006.285.13:29:59.67#ibcon#about to write, iclass 28, count 0 2006.285.13:29:59.67#ibcon#wrote, iclass 28, count 0 2006.285.13:29:59.67#ibcon#about to read 3, iclass 28, count 0 2006.285.13:29:59.70#ibcon#read 3, iclass 28, count 0 2006.285.13:29:59.70#ibcon#about to read 4, iclass 28, count 0 2006.285.13:29:59.70#ibcon#read 4, iclass 28, count 0 2006.285.13:29:59.70#ibcon#about to read 5, iclass 28, count 0 2006.285.13:29:59.70#ibcon#read 5, iclass 28, count 0 2006.285.13:29:59.70#ibcon#about to read 6, iclass 28, count 0 2006.285.13:29:59.70#ibcon#read 6, iclass 28, count 0 2006.285.13:29:59.70#ibcon#end of sib2, iclass 28, count 0 2006.285.13:29:59.70#ibcon#*after write, iclass 28, count 0 2006.285.13:29:59.70#ibcon#*before return 0, iclass 28, count 0 2006.285.13:29:59.70#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:29:59.70#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.13:29:59.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.13:29:59.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.13:29:59.70$vck44/vblo=4,679.99 2006.285.13:29:59.70#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.13:29:59.70#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.13:29:59.70#ibcon#ireg 17 cls_cnt 0 2006.285.13:29:59.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:29:59.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:29:59.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:29:59.70#ibcon#enter wrdev, iclass 30, count 0 2006.285.13:29:59.70#ibcon#first serial, iclass 30, count 0 2006.285.13:29:59.70#ibcon#enter sib2, iclass 30, count 0 2006.285.13:29:59.70#ibcon#flushed, iclass 30, count 0 2006.285.13:29:59.70#ibcon#about to write, iclass 30, count 0 2006.285.13:29:59.70#ibcon#wrote, iclass 30, count 0 2006.285.13:29:59.70#ibcon#about to read 3, iclass 30, count 0 2006.285.13:29:59.72#ibcon#read 3, iclass 30, count 0 2006.285.13:29:59.72#ibcon#about to read 4, iclass 30, count 0 2006.285.13:29:59.72#ibcon#read 4, iclass 30, count 0 2006.285.13:29:59.72#ibcon#about to read 5, iclass 30, count 0 2006.285.13:29:59.72#ibcon#read 5, iclass 30, count 0 2006.285.13:29:59.72#ibcon#about to read 6, iclass 30, count 0 2006.285.13:29:59.72#ibcon#read 6, iclass 30, count 0 2006.285.13:29:59.72#ibcon#end of sib2, iclass 30, count 0 2006.285.13:29:59.72#ibcon#*mode == 0, iclass 30, count 0 2006.285.13:29:59.72#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.13:29:59.72#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:29:59.72#ibcon#*before write, iclass 30, count 0 2006.285.13:29:59.72#ibcon#enter sib2, iclass 30, count 0 2006.285.13:29:59.72#ibcon#flushed, iclass 30, count 0 2006.285.13:29:59.72#ibcon#about to write, iclass 30, count 0 2006.285.13:29:59.72#ibcon#wrote, iclass 30, count 0 2006.285.13:29:59.72#ibcon#about to read 3, iclass 30, count 0 2006.285.13:29:59.76#ibcon#read 3, iclass 30, count 0 2006.285.13:29:59.76#ibcon#about to read 4, iclass 30, count 0 2006.285.13:29:59.76#ibcon#read 4, iclass 30, count 0 2006.285.13:29:59.76#ibcon#about to read 5, iclass 30, count 0 2006.285.13:29:59.76#ibcon#read 5, iclass 30, count 0 2006.285.13:29:59.76#ibcon#about to read 6, iclass 30, count 0 2006.285.13:29:59.76#ibcon#read 6, iclass 30, count 0 2006.285.13:29:59.76#ibcon#end of sib2, iclass 30, count 0 2006.285.13:29:59.76#ibcon#*after write, iclass 30, count 0 2006.285.13:29:59.76#ibcon#*before return 0, iclass 30, count 0 2006.285.13:29:59.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:29:59.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:29:59.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.13:29:59.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.13:29:59.76$vck44/vb=4,5 2006.285.13:29:59.76#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.13:29:59.76#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.13:29:59.76#ibcon#ireg 11 cls_cnt 2 2006.285.13:29:59.76#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:29:59.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:29:59.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:29:59.82#ibcon#enter wrdev, iclass 32, count 2 2006.285.13:29:59.82#ibcon#first serial, iclass 32, count 2 2006.285.13:29:59.82#ibcon#enter sib2, iclass 32, count 2 2006.285.13:29:59.82#ibcon#flushed, iclass 32, count 2 2006.285.13:29:59.82#ibcon#about to write, iclass 32, count 2 2006.285.13:29:59.82#ibcon#wrote, iclass 32, count 2 2006.285.13:29:59.82#ibcon#about to read 3, iclass 32, count 2 2006.285.13:29:59.84#ibcon#read 3, iclass 32, count 2 2006.285.13:29:59.84#ibcon#about to read 4, iclass 32, count 2 2006.285.13:29:59.84#ibcon#read 4, iclass 32, count 2 2006.285.13:29:59.84#ibcon#about to read 5, iclass 32, count 2 2006.285.13:29:59.84#ibcon#read 5, iclass 32, count 2 2006.285.13:29:59.84#ibcon#about to read 6, iclass 32, count 2 2006.285.13:29:59.84#ibcon#read 6, iclass 32, count 2 2006.285.13:29:59.84#ibcon#end of sib2, iclass 32, count 2 2006.285.13:29:59.84#ibcon#*mode == 0, iclass 32, count 2 2006.285.13:29:59.84#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.13:29:59.84#ibcon#[27=AT04-05\r\n] 2006.285.13:29:59.84#ibcon#*before write, iclass 32, count 2 2006.285.13:29:59.84#ibcon#enter sib2, iclass 32, count 2 2006.285.13:29:59.84#ibcon#flushed, iclass 32, count 2 2006.285.13:29:59.84#ibcon#about to write, iclass 32, count 2 2006.285.13:29:59.84#ibcon#wrote, iclass 32, count 2 2006.285.13:29:59.84#ibcon#about to read 3, iclass 32, count 2 2006.285.13:29:59.87#ibcon#read 3, iclass 32, count 2 2006.285.13:29:59.87#ibcon#about to read 4, iclass 32, count 2 2006.285.13:29:59.87#ibcon#read 4, iclass 32, count 2 2006.285.13:29:59.87#ibcon#about to read 5, iclass 32, count 2 2006.285.13:29:59.87#ibcon#read 5, iclass 32, count 2 2006.285.13:29:59.87#ibcon#about to read 6, iclass 32, count 2 2006.285.13:29:59.87#ibcon#read 6, iclass 32, count 2 2006.285.13:29:59.87#ibcon#end of sib2, iclass 32, count 2 2006.285.13:29:59.87#ibcon#*after write, iclass 32, count 2 2006.285.13:29:59.87#ibcon#*before return 0, iclass 32, count 2 2006.285.13:29:59.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:29:59.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.13:29:59.87#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.13:29:59.87#ibcon#ireg 7 cls_cnt 0 2006.285.13:29:59.87#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:29:59.99#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:29:59.99#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:29:59.99#ibcon#enter wrdev, iclass 32, count 0 2006.285.13:29:59.99#ibcon#first serial, iclass 32, count 0 2006.285.13:29:59.99#ibcon#enter sib2, iclass 32, count 0 2006.285.13:29:59.99#ibcon#flushed, iclass 32, count 0 2006.285.13:29:59.99#ibcon#about to write, iclass 32, count 0 2006.285.13:29:59.99#ibcon#wrote, iclass 32, count 0 2006.285.13:29:59.99#ibcon#about to read 3, iclass 32, count 0 2006.285.13:30:00.01#ibcon#read 3, iclass 32, count 0 2006.285.13:30:00.01#ibcon#about to read 4, iclass 32, count 0 2006.285.13:30:00.01#ibcon#read 4, iclass 32, count 0 2006.285.13:30:00.01#ibcon#about to read 5, iclass 32, count 0 2006.285.13:30:00.01#ibcon#read 5, iclass 32, count 0 2006.285.13:30:00.01#ibcon#about to read 6, iclass 32, count 0 2006.285.13:30:00.01#ibcon#read 6, iclass 32, count 0 2006.285.13:30:00.01#ibcon#end of sib2, iclass 32, count 0 2006.285.13:30:00.01#ibcon#*mode == 0, iclass 32, count 0 2006.285.13:30:00.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.13:30:00.01#ibcon#[27=USB\r\n] 2006.285.13:30:00.01#ibcon#*before write, iclass 32, count 0 2006.285.13:30:00.01#ibcon#enter sib2, iclass 32, count 0 2006.285.13:30:00.01#ibcon#flushed, iclass 32, count 0 2006.285.13:30:00.01#ibcon#about to write, iclass 32, count 0 2006.285.13:30:00.01#ibcon#wrote, iclass 32, count 0 2006.285.13:30:00.01#ibcon#about to read 3, iclass 32, count 0 2006.285.13:30:00.04#ibcon#read 3, iclass 32, count 0 2006.285.13:30:00.04#ibcon#about to read 4, iclass 32, count 0 2006.285.13:30:00.04#ibcon#read 4, iclass 32, count 0 2006.285.13:30:00.04#ibcon#about to read 5, iclass 32, count 0 2006.285.13:30:00.04#ibcon#read 5, iclass 32, count 0 2006.285.13:30:00.04#ibcon#about to read 6, iclass 32, count 0 2006.285.13:30:00.04#ibcon#read 6, iclass 32, count 0 2006.285.13:30:00.04#ibcon#end of sib2, iclass 32, count 0 2006.285.13:30:00.04#ibcon#*after write, iclass 32, count 0 2006.285.13:30:00.04#ibcon#*before return 0, iclass 32, count 0 2006.285.13:30:00.04#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:30:00.04#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.13:30:00.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.13:30:00.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.13:30:00.04$vck44/vblo=5,709.99 2006.285.13:30:00.04#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.13:30:00.04#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.13:30:00.04#ibcon#ireg 17 cls_cnt 0 2006.285.13:30:00.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:30:00.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:30:00.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:30:00.04#ibcon#enter wrdev, iclass 34, count 0 2006.285.13:30:00.04#ibcon#first serial, iclass 34, count 0 2006.285.13:30:00.04#ibcon#enter sib2, iclass 34, count 0 2006.285.13:30:00.04#ibcon#flushed, iclass 34, count 0 2006.285.13:30:00.04#ibcon#about to write, iclass 34, count 0 2006.285.13:30:00.04#ibcon#wrote, iclass 34, count 0 2006.285.13:30:00.04#ibcon#about to read 3, iclass 34, count 0 2006.285.13:30:00.06#ibcon#read 3, iclass 34, count 0 2006.285.13:30:00.06#ibcon#about to read 4, iclass 34, count 0 2006.285.13:30:00.06#ibcon#read 4, iclass 34, count 0 2006.285.13:30:00.06#ibcon#about to read 5, iclass 34, count 0 2006.285.13:30:00.06#ibcon#read 5, iclass 34, count 0 2006.285.13:30:00.06#ibcon#about to read 6, iclass 34, count 0 2006.285.13:30:00.06#ibcon#read 6, iclass 34, count 0 2006.285.13:30:00.06#ibcon#end of sib2, iclass 34, count 0 2006.285.13:30:00.06#ibcon#*mode == 0, iclass 34, count 0 2006.285.13:30:00.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.13:30:00.06#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:30:00.06#ibcon#*before write, iclass 34, count 0 2006.285.13:30:00.06#ibcon#enter sib2, iclass 34, count 0 2006.285.13:30:00.06#ibcon#flushed, iclass 34, count 0 2006.285.13:30:00.06#ibcon#about to write, iclass 34, count 0 2006.285.13:30:00.06#ibcon#wrote, iclass 34, count 0 2006.285.13:30:00.06#ibcon#about to read 3, iclass 34, count 0 2006.285.13:30:00.10#ibcon#read 3, iclass 34, count 0 2006.285.13:30:00.10#ibcon#about to read 4, iclass 34, count 0 2006.285.13:30:00.10#ibcon#read 4, iclass 34, count 0 2006.285.13:30:00.10#ibcon#about to read 5, iclass 34, count 0 2006.285.13:30:00.10#ibcon#read 5, iclass 34, count 0 2006.285.13:30:00.10#ibcon#about to read 6, iclass 34, count 0 2006.285.13:30:00.10#ibcon#read 6, iclass 34, count 0 2006.285.13:30:00.10#ibcon#end of sib2, iclass 34, count 0 2006.285.13:30:00.10#ibcon#*after write, iclass 34, count 0 2006.285.13:30:00.10#ibcon#*before return 0, iclass 34, count 0 2006.285.13:30:00.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:30:00.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.13:30:00.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.13:30:00.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.13:30:00.10$vck44/vb=5,4 2006.285.13:30:00.10#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.13:30:00.10#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.13:30:00.10#ibcon#ireg 11 cls_cnt 2 2006.285.13:30:00.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:30:00.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:30:00.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:30:00.16#ibcon#enter wrdev, iclass 36, count 2 2006.285.13:30:00.16#ibcon#first serial, iclass 36, count 2 2006.285.13:30:00.16#ibcon#enter sib2, iclass 36, count 2 2006.285.13:30:00.16#ibcon#flushed, iclass 36, count 2 2006.285.13:30:00.16#ibcon#about to write, iclass 36, count 2 2006.285.13:30:00.16#ibcon#wrote, iclass 36, count 2 2006.285.13:30:00.16#ibcon#about to read 3, iclass 36, count 2 2006.285.13:30:00.18#ibcon#read 3, iclass 36, count 2 2006.285.13:30:00.18#ibcon#about to read 4, iclass 36, count 2 2006.285.13:30:00.18#ibcon#read 4, iclass 36, count 2 2006.285.13:30:00.18#ibcon#about to read 5, iclass 36, count 2 2006.285.13:30:00.18#ibcon#read 5, iclass 36, count 2 2006.285.13:30:00.18#ibcon#about to read 6, iclass 36, count 2 2006.285.13:30:00.18#ibcon#read 6, iclass 36, count 2 2006.285.13:30:00.18#ibcon#end of sib2, iclass 36, count 2 2006.285.13:30:00.18#ibcon#*mode == 0, iclass 36, count 2 2006.285.13:30:00.18#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.13:30:00.18#ibcon#[27=AT05-04\r\n] 2006.285.13:30:00.18#ibcon#*before write, iclass 36, count 2 2006.285.13:30:00.18#ibcon#enter sib2, iclass 36, count 2 2006.285.13:30:00.18#ibcon#flushed, iclass 36, count 2 2006.285.13:30:00.18#ibcon#about to write, iclass 36, count 2 2006.285.13:30:00.18#ibcon#wrote, iclass 36, count 2 2006.285.13:30:00.18#ibcon#about to read 3, iclass 36, count 2 2006.285.13:30:00.21#ibcon#read 3, iclass 36, count 2 2006.285.13:30:00.21#ibcon#about to read 4, iclass 36, count 2 2006.285.13:30:00.21#ibcon#read 4, iclass 36, count 2 2006.285.13:30:00.21#ibcon#about to read 5, iclass 36, count 2 2006.285.13:30:00.21#ibcon#read 5, iclass 36, count 2 2006.285.13:30:00.21#ibcon#about to read 6, iclass 36, count 2 2006.285.13:30:00.21#ibcon#read 6, iclass 36, count 2 2006.285.13:30:00.21#ibcon#end of sib2, iclass 36, count 2 2006.285.13:30:00.21#ibcon#*after write, iclass 36, count 2 2006.285.13:30:00.21#ibcon#*before return 0, iclass 36, count 2 2006.285.13:30:00.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:30:00.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.13:30:00.21#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.13:30:00.21#ibcon#ireg 7 cls_cnt 0 2006.285.13:30:00.21#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:30:00.33#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:30:00.33#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:30:00.33#ibcon#enter wrdev, iclass 36, count 0 2006.285.13:30:00.33#ibcon#first serial, iclass 36, count 0 2006.285.13:30:00.33#ibcon#enter sib2, iclass 36, count 0 2006.285.13:30:00.33#ibcon#flushed, iclass 36, count 0 2006.285.13:30:00.33#ibcon#about to write, iclass 36, count 0 2006.285.13:30:00.33#ibcon#wrote, iclass 36, count 0 2006.285.13:30:00.33#ibcon#about to read 3, iclass 36, count 0 2006.285.13:30:00.35#ibcon#read 3, iclass 36, count 0 2006.285.13:30:00.35#ibcon#about to read 4, iclass 36, count 0 2006.285.13:30:00.35#ibcon#read 4, iclass 36, count 0 2006.285.13:30:00.35#ibcon#about to read 5, iclass 36, count 0 2006.285.13:30:00.35#ibcon#read 5, iclass 36, count 0 2006.285.13:30:00.35#ibcon#about to read 6, iclass 36, count 0 2006.285.13:30:00.35#ibcon#read 6, iclass 36, count 0 2006.285.13:30:00.35#ibcon#end of sib2, iclass 36, count 0 2006.285.13:30:00.35#ibcon#*mode == 0, iclass 36, count 0 2006.285.13:30:00.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.13:30:00.35#ibcon#[27=USB\r\n] 2006.285.13:30:00.35#ibcon#*before write, iclass 36, count 0 2006.285.13:30:00.35#ibcon#enter sib2, iclass 36, count 0 2006.285.13:30:00.35#ibcon#flushed, iclass 36, count 0 2006.285.13:30:00.35#ibcon#about to write, iclass 36, count 0 2006.285.13:30:00.35#ibcon#wrote, iclass 36, count 0 2006.285.13:30:00.35#ibcon#about to read 3, iclass 36, count 0 2006.285.13:30:00.38#ibcon#read 3, iclass 36, count 0 2006.285.13:30:00.38#ibcon#about to read 4, iclass 36, count 0 2006.285.13:30:00.38#ibcon#read 4, iclass 36, count 0 2006.285.13:30:00.38#ibcon#about to read 5, iclass 36, count 0 2006.285.13:30:00.38#ibcon#read 5, iclass 36, count 0 2006.285.13:30:00.38#ibcon#about to read 6, iclass 36, count 0 2006.285.13:30:00.38#ibcon#read 6, iclass 36, count 0 2006.285.13:30:00.38#ibcon#end of sib2, iclass 36, count 0 2006.285.13:30:00.38#ibcon#*after write, iclass 36, count 0 2006.285.13:30:00.38#ibcon#*before return 0, iclass 36, count 0 2006.285.13:30:00.38#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:30:00.38#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.13:30:00.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.13:30:00.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.13:30:00.38$vck44/vblo=6,719.99 2006.285.13:30:00.38#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.13:30:00.38#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.13:30:00.38#ibcon#ireg 17 cls_cnt 0 2006.285.13:30:00.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:30:00.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:30:00.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:30:00.38#ibcon#enter wrdev, iclass 38, count 0 2006.285.13:30:00.38#ibcon#first serial, iclass 38, count 0 2006.285.13:30:00.38#ibcon#enter sib2, iclass 38, count 0 2006.285.13:30:00.38#ibcon#flushed, iclass 38, count 0 2006.285.13:30:00.38#ibcon#about to write, iclass 38, count 0 2006.285.13:30:00.38#ibcon#wrote, iclass 38, count 0 2006.285.13:30:00.38#ibcon#about to read 3, iclass 38, count 0 2006.285.13:30:00.40#ibcon#read 3, iclass 38, count 0 2006.285.13:30:00.40#ibcon#about to read 4, iclass 38, count 0 2006.285.13:30:00.40#ibcon#read 4, iclass 38, count 0 2006.285.13:30:00.40#ibcon#about to read 5, iclass 38, count 0 2006.285.13:30:00.40#ibcon#read 5, iclass 38, count 0 2006.285.13:30:00.40#ibcon#about to read 6, iclass 38, count 0 2006.285.13:30:00.40#ibcon#read 6, iclass 38, count 0 2006.285.13:30:00.40#ibcon#end of sib2, iclass 38, count 0 2006.285.13:30:00.40#ibcon#*mode == 0, iclass 38, count 0 2006.285.13:30:00.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.13:30:00.40#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:30:00.40#ibcon#*before write, iclass 38, count 0 2006.285.13:30:00.40#ibcon#enter sib2, iclass 38, count 0 2006.285.13:30:00.40#ibcon#flushed, iclass 38, count 0 2006.285.13:30:00.40#ibcon#about to write, iclass 38, count 0 2006.285.13:30:00.40#ibcon#wrote, iclass 38, count 0 2006.285.13:30:00.40#ibcon#about to read 3, iclass 38, count 0 2006.285.13:30:00.44#ibcon#read 3, iclass 38, count 0 2006.285.13:30:00.44#ibcon#about to read 4, iclass 38, count 0 2006.285.13:30:00.44#ibcon#read 4, iclass 38, count 0 2006.285.13:30:00.44#ibcon#about to read 5, iclass 38, count 0 2006.285.13:30:00.44#ibcon#read 5, iclass 38, count 0 2006.285.13:30:00.44#ibcon#about to read 6, iclass 38, count 0 2006.285.13:30:00.44#ibcon#read 6, iclass 38, count 0 2006.285.13:30:00.44#ibcon#end of sib2, iclass 38, count 0 2006.285.13:30:00.44#ibcon#*after write, iclass 38, count 0 2006.285.13:30:00.44#ibcon#*before return 0, iclass 38, count 0 2006.285.13:30:00.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:30:00.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.13:30:00.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.13:30:00.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.13:30:00.44$vck44/vb=6,3 2006.285.13:30:00.44#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.13:30:00.44#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.13:30:00.44#ibcon#ireg 11 cls_cnt 2 2006.285.13:30:00.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:30:00.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:30:00.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:30:00.50#ibcon#enter wrdev, iclass 40, count 2 2006.285.13:30:00.50#ibcon#first serial, iclass 40, count 2 2006.285.13:30:00.50#ibcon#enter sib2, iclass 40, count 2 2006.285.13:30:00.50#ibcon#flushed, iclass 40, count 2 2006.285.13:30:00.50#ibcon#about to write, iclass 40, count 2 2006.285.13:30:00.50#ibcon#wrote, iclass 40, count 2 2006.285.13:30:00.50#ibcon#about to read 3, iclass 40, count 2 2006.285.13:30:00.52#ibcon#read 3, iclass 40, count 2 2006.285.13:30:00.52#ibcon#about to read 4, iclass 40, count 2 2006.285.13:30:00.52#ibcon#read 4, iclass 40, count 2 2006.285.13:30:00.52#ibcon#about to read 5, iclass 40, count 2 2006.285.13:30:00.52#ibcon#read 5, iclass 40, count 2 2006.285.13:30:00.52#ibcon#about to read 6, iclass 40, count 2 2006.285.13:30:00.52#ibcon#read 6, iclass 40, count 2 2006.285.13:30:00.52#ibcon#end of sib2, iclass 40, count 2 2006.285.13:30:00.52#ibcon#*mode == 0, iclass 40, count 2 2006.285.13:30:00.52#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.13:30:00.52#ibcon#[27=AT06-03\r\n] 2006.285.13:30:00.52#ibcon#*before write, iclass 40, count 2 2006.285.13:30:00.52#ibcon#enter sib2, iclass 40, count 2 2006.285.13:30:00.52#ibcon#flushed, iclass 40, count 2 2006.285.13:30:00.52#ibcon#about to write, iclass 40, count 2 2006.285.13:30:00.52#ibcon#wrote, iclass 40, count 2 2006.285.13:30:00.52#ibcon#about to read 3, iclass 40, count 2 2006.285.13:30:00.55#ibcon#read 3, iclass 40, count 2 2006.285.13:30:00.55#ibcon#about to read 4, iclass 40, count 2 2006.285.13:30:00.55#ibcon#read 4, iclass 40, count 2 2006.285.13:30:00.55#ibcon#about to read 5, iclass 40, count 2 2006.285.13:30:00.55#ibcon#read 5, iclass 40, count 2 2006.285.13:30:00.55#ibcon#about to read 6, iclass 40, count 2 2006.285.13:30:00.55#ibcon#read 6, iclass 40, count 2 2006.285.13:30:00.55#ibcon#end of sib2, iclass 40, count 2 2006.285.13:30:00.55#ibcon#*after write, iclass 40, count 2 2006.285.13:30:00.55#ibcon#*before return 0, iclass 40, count 2 2006.285.13:30:00.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:30:00.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.13:30:00.55#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.13:30:00.55#ibcon#ireg 7 cls_cnt 0 2006.285.13:30:00.55#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:30:00.67#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:30:00.67#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:30:00.67#ibcon#enter wrdev, iclass 40, count 0 2006.285.13:30:00.67#ibcon#first serial, iclass 40, count 0 2006.285.13:30:00.67#ibcon#enter sib2, iclass 40, count 0 2006.285.13:30:00.67#ibcon#flushed, iclass 40, count 0 2006.285.13:30:00.67#ibcon#about to write, iclass 40, count 0 2006.285.13:30:00.67#ibcon#wrote, iclass 40, count 0 2006.285.13:30:00.67#ibcon#about to read 3, iclass 40, count 0 2006.285.13:30:00.69#ibcon#read 3, iclass 40, count 0 2006.285.13:30:00.69#ibcon#about to read 4, iclass 40, count 0 2006.285.13:30:00.69#ibcon#read 4, iclass 40, count 0 2006.285.13:30:00.69#ibcon#about to read 5, iclass 40, count 0 2006.285.13:30:00.69#ibcon#read 5, iclass 40, count 0 2006.285.13:30:00.69#ibcon#about to read 6, iclass 40, count 0 2006.285.13:30:00.69#ibcon#read 6, iclass 40, count 0 2006.285.13:30:00.69#ibcon#end of sib2, iclass 40, count 0 2006.285.13:30:00.69#ibcon#*mode == 0, iclass 40, count 0 2006.285.13:30:00.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.13:30:00.69#ibcon#[27=USB\r\n] 2006.285.13:30:00.69#ibcon#*before write, iclass 40, count 0 2006.285.13:30:00.69#ibcon#enter sib2, iclass 40, count 0 2006.285.13:30:00.69#ibcon#flushed, iclass 40, count 0 2006.285.13:30:00.69#ibcon#about to write, iclass 40, count 0 2006.285.13:30:00.69#ibcon#wrote, iclass 40, count 0 2006.285.13:30:00.69#ibcon#about to read 3, iclass 40, count 0 2006.285.13:30:00.72#ibcon#read 3, iclass 40, count 0 2006.285.13:30:00.72#ibcon#about to read 4, iclass 40, count 0 2006.285.13:30:00.72#ibcon#read 4, iclass 40, count 0 2006.285.13:30:00.72#ibcon#about to read 5, iclass 40, count 0 2006.285.13:30:00.72#ibcon#read 5, iclass 40, count 0 2006.285.13:30:00.72#ibcon#about to read 6, iclass 40, count 0 2006.285.13:30:00.72#ibcon#read 6, iclass 40, count 0 2006.285.13:30:00.72#ibcon#end of sib2, iclass 40, count 0 2006.285.13:30:00.72#ibcon#*after write, iclass 40, count 0 2006.285.13:30:00.72#ibcon#*before return 0, iclass 40, count 0 2006.285.13:30:00.72#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:30:00.72#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.13:30:00.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.13:30:00.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.13:30:00.72$vck44/vblo=7,734.99 2006.285.13:30:00.72#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.13:30:00.72#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.13:30:00.72#ibcon#ireg 17 cls_cnt 0 2006.285.13:30:00.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:30:00.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:30:00.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:30:00.72#ibcon#enter wrdev, iclass 4, count 0 2006.285.13:30:00.72#ibcon#first serial, iclass 4, count 0 2006.285.13:30:00.72#ibcon#enter sib2, iclass 4, count 0 2006.285.13:30:00.72#ibcon#flushed, iclass 4, count 0 2006.285.13:30:00.72#ibcon#about to write, iclass 4, count 0 2006.285.13:30:00.72#ibcon#wrote, iclass 4, count 0 2006.285.13:30:00.72#ibcon#about to read 3, iclass 4, count 0 2006.285.13:30:00.74#ibcon#read 3, iclass 4, count 0 2006.285.13:30:00.74#ibcon#about to read 4, iclass 4, count 0 2006.285.13:30:00.74#ibcon#read 4, iclass 4, count 0 2006.285.13:30:00.74#ibcon#about to read 5, iclass 4, count 0 2006.285.13:30:00.74#ibcon#read 5, iclass 4, count 0 2006.285.13:30:00.74#ibcon#about to read 6, iclass 4, count 0 2006.285.13:30:00.74#ibcon#read 6, iclass 4, count 0 2006.285.13:30:00.74#ibcon#end of sib2, iclass 4, count 0 2006.285.13:30:00.74#ibcon#*mode == 0, iclass 4, count 0 2006.285.13:30:00.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.13:30:00.74#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:30:00.74#ibcon#*before write, iclass 4, count 0 2006.285.13:30:00.74#ibcon#enter sib2, iclass 4, count 0 2006.285.13:30:00.74#ibcon#flushed, iclass 4, count 0 2006.285.13:30:00.74#ibcon#about to write, iclass 4, count 0 2006.285.13:30:00.74#ibcon#wrote, iclass 4, count 0 2006.285.13:30:00.74#ibcon#about to read 3, iclass 4, count 0 2006.285.13:30:00.78#ibcon#read 3, iclass 4, count 0 2006.285.13:30:00.78#ibcon#about to read 4, iclass 4, count 0 2006.285.13:30:00.78#ibcon#read 4, iclass 4, count 0 2006.285.13:30:00.78#ibcon#about to read 5, iclass 4, count 0 2006.285.13:30:00.78#ibcon#read 5, iclass 4, count 0 2006.285.13:30:00.78#ibcon#about to read 6, iclass 4, count 0 2006.285.13:30:00.78#ibcon#read 6, iclass 4, count 0 2006.285.13:30:00.78#ibcon#end of sib2, iclass 4, count 0 2006.285.13:30:00.78#ibcon#*after write, iclass 4, count 0 2006.285.13:30:00.78#ibcon#*before return 0, iclass 4, count 0 2006.285.13:30:00.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:30:00.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.13:30:00.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.13:30:00.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.13:30:00.78$vck44/vb=7,4 2006.285.13:30:00.78#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.13:30:00.78#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.13:30:00.78#ibcon#ireg 11 cls_cnt 2 2006.285.13:30:00.78#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:30:00.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:30:00.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:30:00.84#ibcon#enter wrdev, iclass 6, count 2 2006.285.13:30:00.84#ibcon#first serial, iclass 6, count 2 2006.285.13:30:00.84#ibcon#enter sib2, iclass 6, count 2 2006.285.13:30:00.84#ibcon#flushed, iclass 6, count 2 2006.285.13:30:00.84#ibcon#about to write, iclass 6, count 2 2006.285.13:30:00.84#ibcon#wrote, iclass 6, count 2 2006.285.13:30:00.84#ibcon#about to read 3, iclass 6, count 2 2006.285.13:30:00.86#ibcon#read 3, iclass 6, count 2 2006.285.13:30:00.86#ibcon#about to read 4, iclass 6, count 2 2006.285.13:30:00.86#ibcon#read 4, iclass 6, count 2 2006.285.13:30:00.86#ibcon#about to read 5, iclass 6, count 2 2006.285.13:30:00.86#ibcon#read 5, iclass 6, count 2 2006.285.13:30:00.86#ibcon#about to read 6, iclass 6, count 2 2006.285.13:30:00.86#ibcon#read 6, iclass 6, count 2 2006.285.13:30:00.86#ibcon#end of sib2, iclass 6, count 2 2006.285.13:30:00.86#ibcon#*mode == 0, iclass 6, count 2 2006.285.13:30:00.86#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.13:30:00.86#ibcon#[27=AT07-04\r\n] 2006.285.13:30:00.86#ibcon#*before write, iclass 6, count 2 2006.285.13:30:00.86#ibcon#enter sib2, iclass 6, count 2 2006.285.13:30:00.86#ibcon#flushed, iclass 6, count 2 2006.285.13:30:00.86#ibcon#about to write, iclass 6, count 2 2006.285.13:30:00.86#ibcon#wrote, iclass 6, count 2 2006.285.13:30:00.86#ibcon#about to read 3, iclass 6, count 2 2006.285.13:30:00.89#ibcon#read 3, iclass 6, count 2 2006.285.13:30:00.89#ibcon#about to read 4, iclass 6, count 2 2006.285.13:30:00.89#ibcon#read 4, iclass 6, count 2 2006.285.13:30:00.89#ibcon#about to read 5, iclass 6, count 2 2006.285.13:30:00.89#ibcon#read 5, iclass 6, count 2 2006.285.13:30:00.89#ibcon#about to read 6, iclass 6, count 2 2006.285.13:30:00.89#ibcon#read 6, iclass 6, count 2 2006.285.13:30:00.89#ibcon#end of sib2, iclass 6, count 2 2006.285.13:30:00.89#ibcon#*after write, iclass 6, count 2 2006.285.13:30:00.89#ibcon#*before return 0, iclass 6, count 2 2006.285.13:30:00.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:30:00.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.13:30:00.89#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.13:30:00.89#ibcon#ireg 7 cls_cnt 0 2006.285.13:30:00.89#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:30:01.01#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:30:01.01#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:30:01.01#ibcon#enter wrdev, iclass 6, count 0 2006.285.13:30:01.01#ibcon#first serial, iclass 6, count 0 2006.285.13:30:01.01#ibcon#enter sib2, iclass 6, count 0 2006.285.13:30:01.01#ibcon#flushed, iclass 6, count 0 2006.285.13:30:01.01#ibcon#about to write, iclass 6, count 0 2006.285.13:30:01.01#ibcon#wrote, iclass 6, count 0 2006.285.13:30:01.01#ibcon#about to read 3, iclass 6, count 0 2006.285.13:30:01.03#ibcon#read 3, iclass 6, count 0 2006.285.13:30:01.03#ibcon#about to read 4, iclass 6, count 0 2006.285.13:30:01.03#ibcon#read 4, iclass 6, count 0 2006.285.13:30:01.03#ibcon#about to read 5, iclass 6, count 0 2006.285.13:30:01.03#ibcon#read 5, iclass 6, count 0 2006.285.13:30:01.03#ibcon#about to read 6, iclass 6, count 0 2006.285.13:30:01.03#ibcon#read 6, iclass 6, count 0 2006.285.13:30:01.03#ibcon#end of sib2, iclass 6, count 0 2006.285.13:30:01.03#ibcon#*mode == 0, iclass 6, count 0 2006.285.13:30:01.03#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.13:30:01.03#ibcon#[27=USB\r\n] 2006.285.13:30:01.03#ibcon#*before write, iclass 6, count 0 2006.285.13:30:01.03#ibcon#enter sib2, iclass 6, count 0 2006.285.13:30:01.03#ibcon#flushed, iclass 6, count 0 2006.285.13:30:01.03#ibcon#about to write, iclass 6, count 0 2006.285.13:30:01.03#ibcon#wrote, iclass 6, count 0 2006.285.13:30:01.03#ibcon#about to read 3, iclass 6, count 0 2006.285.13:30:01.06#ibcon#read 3, iclass 6, count 0 2006.285.13:30:01.06#ibcon#about to read 4, iclass 6, count 0 2006.285.13:30:01.06#ibcon#read 4, iclass 6, count 0 2006.285.13:30:01.06#ibcon#about to read 5, iclass 6, count 0 2006.285.13:30:01.06#ibcon#read 5, iclass 6, count 0 2006.285.13:30:01.06#ibcon#about to read 6, iclass 6, count 0 2006.285.13:30:01.06#ibcon#read 6, iclass 6, count 0 2006.285.13:30:01.06#ibcon#end of sib2, iclass 6, count 0 2006.285.13:30:01.06#ibcon#*after write, iclass 6, count 0 2006.285.13:30:01.06#ibcon#*before return 0, iclass 6, count 0 2006.285.13:30:01.06#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:30:01.06#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.13:30:01.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.13:30:01.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.13:30:01.06$vck44/vblo=8,744.99 2006.285.13:30:01.06#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.13:30:01.06#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.13:30:01.06#ibcon#ireg 17 cls_cnt 0 2006.285.13:30:01.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:30:01.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:30:01.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:30:01.06#ibcon#enter wrdev, iclass 10, count 0 2006.285.13:30:01.06#ibcon#first serial, iclass 10, count 0 2006.285.13:30:01.06#ibcon#enter sib2, iclass 10, count 0 2006.285.13:30:01.06#ibcon#flushed, iclass 10, count 0 2006.285.13:30:01.06#ibcon#about to write, iclass 10, count 0 2006.285.13:30:01.06#ibcon#wrote, iclass 10, count 0 2006.285.13:30:01.06#ibcon#about to read 3, iclass 10, count 0 2006.285.13:30:01.08#ibcon#read 3, iclass 10, count 0 2006.285.13:30:01.21#ibcon#about to read 4, iclass 10, count 0 2006.285.13:30:01.21#ibcon#read 4, iclass 10, count 0 2006.285.13:30:01.21#ibcon#about to read 5, iclass 10, count 0 2006.285.13:30:01.21#ibcon#read 5, iclass 10, count 0 2006.285.13:30:01.21#ibcon#about to read 6, iclass 10, count 0 2006.285.13:30:01.21#ibcon#read 6, iclass 10, count 0 2006.285.13:30:01.21#ibcon#end of sib2, iclass 10, count 0 2006.285.13:30:01.21#ibcon#*mode == 0, iclass 10, count 0 2006.285.13:30:01.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.13:30:01.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:30:01.21#ibcon#*before write, iclass 10, count 0 2006.285.13:30:01.21#ibcon#enter sib2, iclass 10, count 0 2006.285.13:30:01.21#ibcon#flushed, iclass 10, count 0 2006.285.13:30:01.21#ibcon#about to write, iclass 10, count 0 2006.285.13:30:01.21#ibcon#wrote, iclass 10, count 0 2006.285.13:30:01.21#ibcon#about to read 3, iclass 10, count 0 2006.285.13:30:01.26#ibcon#read 3, iclass 10, count 0 2006.285.13:30:01.26#ibcon#about to read 4, iclass 10, count 0 2006.285.13:30:01.26#ibcon#read 4, iclass 10, count 0 2006.285.13:30:01.26#ibcon#about to read 5, iclass 10, count 0 2006.285.13:30:01.26#ibcon#read 5, iclass 10, count 0 2006.285.13:30:01.26#ibcon#about to read 6, iclass 10, count 0 2006.285.13:30:01.26#ibcon#read 6, iclass 10, count 0 2006.285.13:30:01.26#ibcon#end of sib2, iclass 10, count 0 2006.285.13:30:01.26#ibcon#*after write, iclass 10, count 0 2006.285.13:30:01.26#ibcon#*before return 0, iclass 10, count 0 2006.285.13:30:01.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:30:01.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.13:30:01.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.13:30:01.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.13:30:01.26$vck44/vb=8,4 2006.285.13:30:01.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.13:30:01.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.13:30:01.26#ibcon#ireg 11 cls_cnt 2 2006.285.13:30:01.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:30:01.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:30:01.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:30:01.26#ibcon#enter wrdev, iclass 12, count 2 2006.285.13:30:01.26#ibcon#first serial, iclass 12, count 2 2006.285.13:30:01.26#ibcon#enter sib2, iclass 12, count 2 2006.285.13:30:01.26#ibcon#flushed, iclass 12, count 2 2006.285.13:30:01.26#ibcon#about to write, iclass 12, count 2 2006.285.13:30:01.26#ibcon#wrote, iclass 12, count 2 2006.285.13:30:01.26#ibcon#about to read 3, iclass 12, count 2 2006.285.13:30:01.28#ibcon#read 3, iclass 12, count 2 2006.285.13:30:01.28#ibcon#about to read 4, iclass 12, count 2 2006.285.13:30:01.28#ibcon#read 4, iclass 12, count 2 2006.285.13:30:01.28#ibcon#about to read 5, iclass 12, count 2 2006.285.13:30:01.28#ibcon#read 5, iclass 12, count 2 2006.285.13:30:01.28#ibcon#about to read 6, iclass 12, count 2 2006.285.13:30:01.28#ibcon#read 6, iclass 12, count 2 2006.285.13:30:01.28#ibcon#end of sib2, iclass 12, count 2 2006.285.13:30:01.28#ibcon#*mode == 0, iclass 12, count 2 2006.285.13:30:01.28#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.13:30:01.28#ibcon#[27=AT08-04\r\n] 2006.285.13:30:01.28#ibcon#*before write, iclass 12, count 2 2006.285.13:30:01.28#ibcon#enter sib2, iclass 12, count 2 2006.285.13:30:01.28#ibcon#flushed, iclass 12, count 2 2006.285.13:30:01.28#ibcon#about to write, iclass 12, count 2 2006.285.13:30:01.28#ibcon#wrote, iclass 12, count 2 2006.285.13:30:01.28#ibcon#about to read 3, iclass 12, count 2 2006.285.13:30:01.31#ibcon#read 3, iclass 12, count 2 2006.285.13:30:01.31#ibcon#about to read 4, iclass 12, count 2 2006.285.13:30:01.31#ibcon#read 4, iclass 12, count 2 2006.285.13:30:01.31#ibcon#about to read 5, iclass 12, count 2 2006.285.13:30:01.31#ibcon#read 5, iclass 12, count 2 2006.285.13:30:01.31#ibcon#about to read 6, iclass 12, count 2 2006.285.13:30:01.31#ibcon#read 6, iclass 12, count 2 2006.285.13:30:01.31#ibcon#end of sib2, iclass 12, count 2 2006.285.13:30:01.31#ibcon#*after write, iclass 12, count 2 2006.285.13:30:01.31#ibcon#*before return 0, iclass 12, count 2 2006.285.13:30:01.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:30:01.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.13:30:01.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.13:30:01.31#ibcon#ireg 7 cls_cnt 0 2006.285.13:30:01.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:30:01.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:30:01.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:30:01.43#ibcon#enter wrdev, iclass 12, count 0 2006.285.13:30:01.43#ibcon#first serial, iclass 12, count 0 2006.285.13:30:01.43#ibcon#enter sib2, iclass 12, count 0 2006.285.13:30:01.43#ibcon#flushed, iclass 12, count 0 2006.285.13:30:01.43#ibcon#about to write, iclass 12, count 0 2006.285.13:30:01.43#ibcon#wrote, iclass 12, count 0 2006.285.13:30:01.43#ibcon#about to read 3, iclass 12, count 0 2006.285.13:30:01.45#ibcon#read 3, iclass 12, count 0 2006.285.13:30:01.45#ibcon#about to read 4, iclass 12, count 0 2006.285.13:30:01.45#ibcon#read 4, iclass 12, count 0 2006.285.13:30:01.45#ibcon#about to read 5, iclass 12, count 0 2006.285.13:30:01.45#ibcon#read 5, iclass 12, count 0 2006.285.13:30:01.45#ibcon#about to read 6, iclass 12, count 0 2006.285.13:30:01.45#ibcon#read 6, iclass 12, count 0 2006.285.13:30:01.45#ibcon#end of sib2, iclass 12, count 0 2006.285.13:30:01.45#ibcon#*mode == 0, iclass 12, count 0 2006.285.13:30:01.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.13:30:01.45#ibcon#[27=USB\r\n] 2006.285.13:30:01.45#ibcon#*before write, iclass 12, count 0 2006.285.13:30:01.45#ibcon#enter sib2, iclass 12, count 0 2006.285.13:30:01.45#ibcon#flushed, iclass 12, count 0 2006.285.13:30:01.45#ibcon#about to write, iclass 12, count 0 2006.285.13:30:01.45#ibcon#wrote, iclass 12, count 0 2006.285.13:30:01.45#ibcon#about to read 3, iclass 12, count 0 2006.285.13:30:01.48#ibcon#read 3, iclass 12, count 0 2006.285.13:30:01.48#ibcon#about to read 4, iclass 12, count 0 2006.285.13:30:01.48#ibcon#read 4, iclass 12, count 0 2006.285.13:30:01.48#ibcon#about to read 5, iclass 12, count 0 2006.285.13:30:01.48#ibcon#read 5, iclass 12, count 0 2006.285.13:30:01.48#ibcon#about to read 6, iclass 12, count 0 2006.285.13:30:01.48#ibcon#read 6, iclass 12, count 0 2006.285.13:30:01.48#ibcon#end of sib2, iclass 12, count 0 2006.285.13:30:01.48#ibcon#*after write, iclass 12, count 0 2006.285.13:30:01.48#ibcon#*before return 0, iclass 12, count 0 2006.285.13:30:01.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:30:01.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.13:30:01.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.13:30:01.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.13:30:01.48$vck44/vabw=wide 2006.285.13:30:01.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.13:30:01.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.13:30:01.48#ibcon#ireg 8 cls_cnt 0 2006.285.13:30:01.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:30:01.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:30:01.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:30:01.48#ibcon#enter wrdev, iclass 14, count 0 2006.285.13:30:01.48#ibcon#first serial, iclass 14, count 0 2006.285.13:30:01.48#ibcon#enter sib2, iclass 14, count 0 2006.285.13:30:01.48#ibcon#flushed, iclass 14, count 0 2006.285.13:30:01.48#ibcon#about to write, iclass 14, count 0 2006.285.13:30:01.48#ibcon#wrote, iclass 14, count 0 2006.285.13:30:01.48#ibcon#about to read 3, iclass 14, count 0 2006.285.13:30:01.50#ibcon#read 3, iclass 14, count 0 2006.285.13:30:01.50#ibcon#about to read 4, iclass 14, count 0 2006.285.13:30:01.50#ibcon#read 4, iclass 14, count 0 2006.285.13:30:01.50#ibcon#about to read 5, iclass 14, count 0 2006.285.13:30:01.50#ibcon#read 5, iclass 14, count 0 2006.285.13:30:01.50#ibcon#about to read 6, iclass 14, count 0 2006.285.13:30:01.50#ibcon#read 6, iclass 14, count 0 2006.285.13:30:01.50#ibcon#end of sib2, iclass 14, count 0 2006.285.13:30:01.50#ibcon#*mode == 0, iclass 14, count 0 2006.285.13:30:01.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.13:30:01.50#ibcon#[25=BW32\r\n] 2006.285.13:30:01.50#ibcon#*before write, iclass 14, count 0 2006.285.13:30:01.50#ibcon#enter sib2, iclass 14, count 0 2006.285.13:30:01.50#ibcon#flushed, iclass 14, count 0 2006.285.13:30:01.50#ibcon#about to write, iclass 14, count 0 2006.285.13:30:01.50#ibcon#wrote, iclass 14, count 0 2006.285.13:30:01.50#ibcon#about to read 3, iclass 14, count 0 2006.285.13:30:01.53#ibcon#read 3, iclass 14, count 0 2006.285.13:30:01.53#ibcon#about to read 4, iclass 14, count 0 2006.285.13:30:01.53#ibcon#read 4, iclass 14, count 0 2006.285.13:30:01.53#ibcon#about to read 5, iclass 14, count 0 2006.285.13:30:01.53#ibcon#read 5, iclass 14, count 0 2006.285.13:30:01.53#ibcon#about to read 6, iclass 14, count 0 2006.285.13:30:01.53#ibcon#read 6, iclass 14, count 0 2006.285.13:30:01.53#ibcon#end of sib2, iclass 14, count 0 2006.285.13:30:01.53#ibcon#*after write, iclass 14, count 0 2006.285.13:30:01.53#ibcon#*before return 0, iclass 14, count 0 2006.285.13:30:01.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:30:01.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.13:30:01.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.13:30:01.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.13:30:01.53$vck44/vbbw=wide 2006.285.13:30:01.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.13:30:01.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.13:30:01.53#ibcon#ireg 8 cls_cnt 0 2006.285.13:30:01.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:30:01.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:30:01.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:30:01.60#ibcon#enter wrdev, iclass 16, count 0 2006.285.13:30:01.60#ibcon#first serial, iclass 16, count 0 2006.285.13:30:01.60#ibcon#enter sib2, iclass 16, count 0 2006.285.13:30:01.60#ibcon#flushed, iclass 16, count 0 2006.285.13:30:01.60#ibcon#about to write, iclass 16, count 0 2006.285.13:30:01.60#ibcon#wrote, iclass 16, count 0 2006.285.13:30:01.60#ibcon#about to read 3, iclass 16, count 0 2006.285.13:30:01.62#ibcon#read 3, iclass 16, count 0 2006.285.13:30:01.62#ibcon#about to read 4, iclass 16, count 0 2006.285.13:30:01.62#ibcon#read 4, iclass 16, count 0 2006.285.13:30:01.62#ibcon#about to read 5, iclass 16, count 0 2006.285.13:30:01.62#ibcon#read 5, iclass 16, count 0 2006.285.13:30:01.62#ibcon#about to read 6, iclass 16, count 0 2006.285.13:30:01.62#ibcon#read 6, iclass 16, count 0 2006.285.13:30:01.62#ibcon#end of sib2, iclass 16, count 0 2006.285.13:30:01.62#ibcon#*mode == 0, iclass 16, count 0 2006.285.13:30:01.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.13:30:01.62#ibcon#[27=BW32\r\n] 2006.285.13:30:01.62#ibcon#*before write, iclass 16, count 0 2006.285.13:30:01.62#ibcon#enter sib2, iclass 16, count 0 2006.285.13:30:01.62#ibcon#flushed, iclass 16, count 0 2006.285.13:30:01.62#ibcon#about to write, iclass 16, count 0 2006.285.13:30:01.62#ibcon#wrote, iclass 16, count 0 2006.285.13:30:01.62#ibcon#about to read 3, iclass 16, count 0 2006.285.13:30:01.65#ibcon#read 3, iclass 16, count 0 2006.285.13:30:01.65#ibcon#about to read 4, iclass 16, count 0 2006.285.13:30:01.65#ibcon#read 4, iclass 16, count 0 2006.285.13:30:01.65#ibcon#about to read 5, iclass 16, count 0 2006.285.13:30:01.65#ibcon#read 5, iclass 16, count 0 2006.285.13:30:01.65#ibcon#about to read 6, iclass 16, count 0 2006.285.13:30:01.65#ibcon#read 6, iclass 16, count 0 2006.285.13:30:01.65#ibcon#end of sib2, iclass 16, count 0 2006.285.13:30:01.65#ibcon#*after write, iclass 16, count 0 2006.285.13:30:01.65#ibcon#*before return 0, iclass 16, count 0 2006.285.13:30:01.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:30:01.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:30:01.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.13:30:01.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.13:30:01.65$setupk4/ifdk4 2006.285.13:30:01.65$ifdk4/lo= 2006.285.13:30:01.65$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:30:01.65$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:30:01.65$ifdk4/patch= 2006.285.13:30:01.65$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:30:01.65$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:30:01.65$setupk4/!*+20s 2006.285.13:30:08.22#abcon#<5=/04 1.4 2.4 19.10 971015.3\r\n> 2006.285.13:30:08.24#abcon#{5=INTERFACE CLEAR} 2006.285.13:30:08.30#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:30:15.22$setupk4/"tpicd 2006.285.13:30:15.22$setupk4/echo=off 2006.285.13:30:15.22$setupk4/xlog=off 2006.285.13:30:15.22:!2006.285.13:32:37 2006.285.13:30:39.14#trakl#Source acquired 2006.285.13:30:40.14#flagr#flagr/antenna,acquired 2006.285.13:32:37.00:preob 2006.285.13:32:38.14/onsource/TRACKING 2006.285.13:32:38.14:!2006.285.13:32:47 2006.285.13:32:47.00:"tape 2006.285.13:32:47.00:"st=record 2006.285.13:32:47.00:data_valid=on 2006.285.13:32:47.00:midob 2006.285.13:32:47.14/onsource/TRACKING 2006.285.13:32:47.14/wx/19.11,1015.3,97 2006.285.13:32:47.35/cable/+6.4982E-03 2006.285.13:32:48.44/va/01,07,usb,yes,34,37 2006.285.13:32:48.44/va/02,06,usb,yes,35,35 2006.285.13:32:48.44/va/03,07,usb,yes,34,36 2006.285.13:32:48.44/va/04,06,usb,yes,36,37 2006.285.13:32:48.44/va/05,03,usb,yes,35,36 2006.285.13:32:48.44/va/06,04,usb,yes,32,31 2006.285.13:32:48.44/va/07,04,usb,yes,32,33 2006.285.13:32:48.44/va/08,03,usb,yes,33,40 2006.285.13:32:48.67/valo/01,524.99,yes,locked 2006.285.13:32:48.67/valo/02,534.99,yes,locked 2006.285.13:32:48.67/valo/03,564.99,yes,locked 2006.285.13:32:48.67/valo/04,624.99,yes,locked 2006.285.13:32:48.67/valo/05,734.99,yes,locked 2006.285.13:32:48.67/valo/06,814.99,yes,locked 2006.285.13:32:48.67/valo/07,864.99,yes,locked 2006.285.13:32:48.67/valo/08,884.99,yes,locked 2006.285.13:32:49.76/vb/01,04,usb,yes,32,29 2006.285.13:32:49.76/vb/02,05,usb,yes,30,30 2006.285.13:32:49.76/vb/03,04,usb,yes,31,34 2006.285.13:32:49.76/vb/04,05,usb,yes,31,30 2006.285.13:32:49.76/vb/05,04,usb,yes,27,30 2006.285.13:32:49.76/vb/06,03,usb,yes,40,35 2006.285.13:32:49.76/vb/07,04,usb,yes,32,32 2006.285.13:32:49.76/vb/08,04,usb,yes,29,33 2006.285.13:32:49.99/vblo/01,629.99,yes,locked 2006.285.13:32:49.99/vblo/02,634.99,yes,locked 2006.285.13:32:49.99/vblo/03,649.99,yes,locked 2006.285.13:32:49.99/vblo/04,679.99,yes,locked 2006.285.13:32:49.99/vblo/05,709.99,yes,locked 2006.285.13:32:49.99/vblo/06,719.99,yes,locked 2006.285.13:32:49.99/vblo/07,734.99,yes,locked 2006.285.13:32:49.99/vblo/08,744.99,yes,locked 2006.285.13:32:50.14/vabw/8 2006.285.13:32:50.29/vbbw/8 2006.285.13:32:50.38/xfe/off,on,12.2 2006.285.13:32:50.76/ifatt/23,28,28,28 2006.285.13:32:51.08/fmout-gps/S +2.78E-07 2006.285.13:32:51.10:!2006.285.13:34:57 2006.285.13:34:57.00:data_valid=off 2006.285.13:34:57.00:"et 2006.285.13:34:57.00:!+3s 2006.285.13:35:00.01:"tape 2006.285.13:35:00.01:postob 2006.285.13:35:00.20/cable/+6.4970E-03 2006.285.13:35:00.20/wx/19.12,1015.3,97 2006.285.13:35:01.08/fmout-gps/S +2.83E-07 2006.285.13:35:01.08:scan_name=285-1340,jd0610,80 2006.285.13:35:01.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.285.13:35:02.14#flagr#flagr/antenna,new-source 2006.285.13:35:02.14:checkk5 2006.285.13:35:02.76/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:35:03.22/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:35:03.56/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:35:04.00/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:35:04.56/chk_obsdata//k5ts1/T2851332??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.285.13:35:04.89/chk_obsdata//k5ts2/T2851332??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.285.13:35:05.57/chk_obsdata//k5ts3/T2851332??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.285.13:35:05.93/chk_obsdata//k5ts4/T2851332??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.285.13:35:07.09/k5log//k5ts1_log_newline 2006.285.13:35:08.08/k5log//k5ts2_log_newline 2006.285.13:35:08.78/k5log//k5ts3_log_newline 2006.285.13:35:09.95/k5log//k5ts4_log_newline 2006.285.13:35:09.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:35:09.97:setupk4=1 2006.285.13:35:09.97$setupk4/echo=on 2006.285.13:35:09.97$setupk4/pcalon 2006.285.13:35:09.97$pcalon/"no phase cal control is implemented here 2006.285.13:35:09.97$setupk4/"tpicd=stop 2006.285.13:35:09.97$setupk4/"rec=synch_on 2006.285.13:35:09.97$setupk4/"rec_mode=128 2006.285.13:35:09.97$setupk4/!* 2006.285.13:35:09.97$setupk4/recpk4 2006.285.13:35:09.97$recpk4/recpatch= 2006.285.13:35:09.98$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:35:09.98$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:35:09.98$setupk4/vck44 2006.285.13:35:09.98$vck44/valo=1,524.99 2006.285.13:35:09.98#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.13:35:09.98#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.13:35:09.98#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:09.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:35:09.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:35:09.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:35:09.98#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:35:09.98#ibcon#first serial, iclass 33, count 0 2006.285.13:35:09.98#ibcon#enter sib2, iclass 33, count 0 2006.285.13:35:09.98#ibcon#flushed, iclass 33, count 0 2006.285.13:35:09.98#ibcon#about to write, iclass 33, count 0 2006.285.13:35:09.98#ibcon#wrote, iclass 33, count 0 2006.285.13:35:09.98#ibcon#about to read 3, iclass 33, count 0 2006.285.13:35:09.99#ibcon#read 3, iclass 33, count 0 2006.285.13:35:09.99#ibcon#about to read 4, iclass 33, count 0 2006.285.13:35:10.00#ibcon#read 4, iclass 33, count 0 2006.285.13:35:10.00#ibcon#about to read 5, iclass 33, count 0 2006.285.13:35:10.00#ibcon#read 5, iclass 33, count 0 2006.285.13:35:10.00#ibcon#about to read 6, iclass 33, count 0 2006.285.13:35:10.00#ibcon#read 6, iclass 33, count 0 2006.285.13:35:10.00#ibcon#end of sib2, iclass 33, count 0 2006.285.13:35:10.00#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:35:10.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:35:10.00#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:35:10.00#ibcon#*before write, iclass 33, count 0 2006.285.13:35:10.00#ibcon#enter sib2, iclass 33, count 0 2006.285.13:35:10.00#ibcon#flushed, iclass 33, count 0 2006.285.13:35:10.00#ibcon#about to write, iclass 33, count 0 2006.285.13:35:10.00#ibcon#wrote, iclass 33, count 0 2006.285.13:35:10.00#ibcon#about to read 3, iclass 33, count 0 2006.285.13:35:10.04#ibcon#read 3, iclass 33, count 0 2006.285.13:35:10.05#ibcon#about to read 4, iclass 33, count 0 2006.285.13:35:10.05#ibcon#read 4, iclass 33, count 0 2006.285.13:35:10.05#ibcon#about to read 5, iclass 33, count 0 2006.285.13:35:10.05#ibcon#read 5, iclass 33, count 0 2006.285.13:35:10.05#ibcon#about to read 6, iclass 33, count 0 2006.285.13:35:10.05#ibcon#read 6, iclass 33, count 0 2006.285.13:35:10.05#ibcon#end of sib2, iclass 33, count 0 2006.285.13:35:10.05#ibcon#*after write, iclass 33, count 0 2006.285.13:35:10.05#ibcon#*before return 0, iclass 33, count 0 2006.285.13:35:10.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:35:10.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:35:10.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:35:10.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:35:10.05$vck44/va=1,7 2006.285.13:35:10.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.13:35:10.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.13:35:10.05#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:10.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:35:10.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:35:10.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:35:10.05#ibcon#enter wrdev, iclass 35, count 2 2006.285.13:35:10.05#ibcon#first serial, iclass 35, count 2 2006.285.13:35:10.05#ibcon#enter sib2, iclass 35, count 2 2006.285.13:35:10.05#ibcon#flushed, iclass 35, count 2 2006.285.13:35:10.05#ibcon#about to write, iclass 35, count 2 2006.285.13:35:10.05#ibcon#wrote, iclass 35, count 2 2006.285.13:35:10.05#ibcon#about to read 3, iclass 35, count 2 2006.285.13:35:10.06#ibcon#read 3, iclass 35, count 2 2006.285.13:35:10.07#ibcon#about to read 4, iclass 35, count 2 2006.285.13:35:10.07#ibcon#read 4, iclass 35, count 2 2006.285.13:35:10.07#ibcon#about to read 5, iclass 35, count 2 2006.285.13:35:10.07#ibcon#read 5, iclass 35, count 2 2006.285.13:35:10.07#ibcon#about to read 6, iclass 35, count 2 2006.285.13:35:10.07#ibcon#read 6, iclass 35, count 2 2006.285.13:35:10.07#ibcon#end of sib2, iclass 35, count 2 2006.285.13:35:10.07#ibcon#*mode == 0, iclass 35, count 2 2006.285.13:35:10.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.13:35:10.07#ibcon#[25=AT01-07\r\n] 2006.285.13:35:10.07#ibcon#*before write, iclass 35, count 2 2006.285.13:35:10.07#ibcon#enter sib2, iclass 35, count 2 2006.285.13:35:10.07#ibcon#flushed, iclass 35, count 2 2006.285.13:35:10.07#ibcon#about to write, iclass 35, count 2 2006.285.13:35:10.07#ibcon#wrote, iclass 35, count 2 2006.285.13:35:10.07#ibcon#about to read 3, iclass 35, count 2 2006.285.13:35:10.09#ibcon#read 3, iclass 35, count 2 2006.285.13:35:10.10#ibcon#about to read 4, iclass 35, count 2 2006.285.13:35:10.10#ibcon#read 4, iclass 35, count 2 2006.285.13:35:10.10#ibcon#about to read 5, iclass 35, count 2 2006.285.13:35:10.10#ibcon#read 5, iclass 35, count 2 2006.285.13:35:10.10#ibcon#about to read 6, iclass 35, count 2 2006.285.13:35:10.10#ibcon#read 6, iclass 35, count 2 2006.285.13:35:10.10#ibcon#end of sib2, iclass 35, count 2 2006.285.13:35:10.10#ibcon#*after write, iclass 35, count 2 2006.285.13:35:10.10#ibcon#*before return 0, iclass 35, count 2 2006.285.13:35:10.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:35:10.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:35:10.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.13:35:10.10#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:10.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:35:10.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:35:10.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:35:10.22#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:35:10.22#ibcon#first serial, iclass 35, count 0 2006.285.13:35:10.22#ibcon#enter sib2, iclass 35, count 0 2006.285.13:35:10.22#ibcon#flushed, iclass 35, count 0 2006.285.13:35:10.22#ibcon#about to write, iclass 35, count 0 2006.285.13:35:10.22#ibcon#wrote, iclass 35, count 0 2006.285.13:35:10.22#ibcon#about to read 3, iclass 35, count 0 2006.285.13:35:10.23#ibcon#read 3, iclass 35, count 0 2006.285.13:35:10.23#ibcon#about to read 4, iclass 35, count 0 2006.285.13:35:10.24#ibcon#read 4, iclass 35, count 0 2006.285.13:35:10.24#ibcon#about to read 5, iclass 35, count 0 2006.285.13:35:10.24#ibcon#read 5, iclass 35, count 0 2006.285.13:35:10.24#ibcon#about to read 6, iclass 35, count 0 2006.285.13:35:10.24#ibcon#read 6, iclass 35, count 0 2006.285.13:35:10.24#ibcon#end of sib2, iclass 35, count 0 2006.285.13:35:10.24#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:35:10.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:35:10.24#ibcon#[25=USB\r\n] 2006.285.13:35:10.24#ibcon#*before write, iclass 35, count 0 2006.285.13:35:10.24#ibcon#enter sib2, iclass 35, count 0 2006.285.13:35:10.24#ibcon#flushed, iclass 35, count 0 2006.285.13:35:10.24#ibcon#about to write, iclass 35, count 0 2006.285.13:35:10.24#ibcon#wrote, iclass 35, count 0 2006.285.13:35:10.24#ibcon#about to read 3, iclass 35, count 0 2006.285.13:35:10.26#ibcon#read 3, iclass 35, count 0 2006.285.13:35:10.26#ibcon#about to read 4, iclass 35, count 0 2006.285.13:35:10.27#ibcon#read 4, iclass 35, count 0 2006.285.13:35:10.27#ibcon#about to read 5, iclass 35, count 0 2006.285.13:35:10.27#ibcon#read 5, iclass 35, count 0 2006.285.13:35:10.27#ibcon#about to read 6, iclass 35, count 0 2006.285.13:35:10.27#ibcon#read 6, iclass 35, count 0 2006.285.13:35:10.27#ibcon#end of sib2, iclass 35, count 0 2006.285.13:35:10.27#ibcon#*after write, iclass 35, count 0 2006.285.13:35:10.27#ibcon#*before return 0, iclass 35, count 0 2006.285.13:35:10.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:35:10.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:35:10.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:35:10.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:35:10.27$vck44/valo=2,534.99 2006.285.13:35:10.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.13:35:10.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.13:35:10.27#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:10.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:35:10.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:35:10.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:35:10.27#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:35:10.27#ibcon#first serial, iclass 37, count 0 2006.285.13:35:10.27#ibcon#enter sib2, iclass 37, count 0 2006.285.13:35:10.27#ibcon#flushed, iclass 37, count 0 2006.285.13:35:10.27#ibcon#about to write, iclass 37, count 0 2006.285.13:35:10.27#ibcon#wrote, iclass 37, count 0 2006.285.13:35:10.27#ibcon#about to read 3, iclass 37, count 0 2006.285.13:35:10.28#ibcon#read 3, iclass 37, count 0 2006.285.13:35:10.28#ibcon#about to read 4, iclass 37, count 0 2006.285.13:35:10.29#ibcon#read 4, iclass 37, count 0 2006.285.13:35:10.29#ibcon#about to read 5, iclass 37, count 0 2006.285.13:35:10.29#ibcon#read 5, iclass 37, count 0 2006.285.13:35:10.29#ibcon#about to read 6, iclass 37, count 0 2006.285.13:35:10.29#ibcon#read 6, iclass 37, count 0 2006.285.13:35:10.29#ibcon#end of sib2, iclass 37, count 0 2006.285.13:35:10.29#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:35:10.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:35:10.29#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:35:10.29#ibcon#*before write, iclass 37, count 0 2006.285.13:35:10.29#ibcon#enter sib2, iclass 37, count 0 2006.285.13:35:10.29#ibcon#flushed, iclass 37, count 0 2006.285.13:35:10.29#ibcon#about to write, iclass 37, count 0 2006.285.13:35:10.29#ibcon#wrote, iclass 37, count 0 2006.285.13:35:10.29#ibcon#about to read 3, iclass 37, count 0 2006.285.13:35:10.32#ibcon#read 3, iclass 37, count 0 2006.285.13:35:10.32#ibcon#about to read 4, iclass 37, count 0 2006.285.13:35:10.32#ibcon#read 4, iclass 37, count 0 2006.285.13:35:10.33#ibcon#about to read 5, iclass 37, count 0 2006.285.13:35:10.33#ibcon#read 5, iclass 37, count 0 2006.285.13:35:10.33#ibcon#about to read 6, iclass 37, count 0 2006.285.13:35:10.33#ibcon#read 6, iclass 37, count 0 2006.285.13:35:10.33#ibcon#end of sib2, iclass 37, count 0 2006.285.13:35:10.33#ibcon#*after write, iclass 37, count 0 2006.285.13:35:10.33#ibcon#*before return 0, iclass 37, count 0 2006.285.13:35:10.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:35:10.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:35:10.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:35:10.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:35:10.33$vck44/va=2,6 2006.285.13:35:10.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.13:35:10.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.13:35:10.33#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:10.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:35:10.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:35:10.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:35:10.38#ibcon#enter wrdev, iclass 39, count 2 2006.285.13:35:10.39#ibcon#first serial, iclass 39, count 2 2006.285.13:35:10.39#ibcon#enter sib2, iclass 39, count 2 2006.285.13:35:10.39#ibcon#flushed, iclass 39, count 2 2006.285.13:35:10.39#ibcon#about to write, iclass 39, count 2 2006.285.13:35:10.39#ibcon#wrote, iclass 39, count 2 2006.285.13:35:10.39#ibcon#about to read 3, iclass 39, count 2 2006.285.13:35:10.40#ibcon#read 3, iclass 39, count 2 2006.285.13:35:10.40#ibcon#about to read 4, iclass 39, count 2 2006.285.13:35:10.40#ibcon#read 4, iclass 39, count 2 2006.285.13:35:10.41#ibcon#about to read 5, iclass 39, count 2 2006.285.13:35:10.41#ibcon#read 5, iclass 39, count 2 2006.285.13:35:10.41#ibcon#about to read 6, iclass 39, count 2 2006.285.13:35:10.41#ibcon#read 6, iclass 39, count 2 2006.285.13:35:10.41#ibcon#end of sib2, iclass 39, count 2 2006.285.13:35:10.41#ibcon#*mode == 0, iclass 39, count 2 2006.285.13:35:10.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.13:35:10.41#ibcon#[25=AT02-06\r\n] 2006.285.13:35:10.41#ibcon#*before write, iclass 39, count 2 2006.285.13:35:10.41#ibcon#enter sib2, iclass 39, count 2 2006.285.13:35:10.41#ibcon#flushed, iclass 39, count 2 2006.285.13:35:10.41#ibcon#about to write, iclass 39, count 2 2006.285.13:35:10.41#ibcon#wrote, iclass 39, count 2 2006.285.13:35:10.41#ibcon#about to read 3, iclass 39, count 2 2006.285.13:35:10.43#ibcon#read 3, iclass 39, count 2 2006.285.13:35:10.43#ibcon#about to read 4, iclass 39, count 2 2006.285.13:35:10.43#ibcon#read 4, iclass 39, count 2 2006.285.13:35:10.44#ibcon#about to read 5, iclass 39, count 2 2006.285.13:35:10.44#ibcon#read 5, iclass 39, count 2 2006.285.13:35:10.44#ibcon#about to read 6, iclass 39, count 2 2006.285.13:35:10.44#ibcon#read 6, iclass 39, count 2 2006.285.13:35:10.44#ibcon#end of sib2, iclass 39, count 2 2006.285.13:35:10.44#ibcon#*after write, iclass 39, count 2 2006.285.13:35:10.44#ibcon#*before return 0, iclass 39, count 2 2006.285.13:35:10.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:35:10.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:35:10.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.13:35:10.44#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:10.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:35:10.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:35:10.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:35:10.55#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:35:10.56#ibcon#first serial, iclass 39, count 0 2006.285.13:35:10.56#ibcon#enter sib2, iclass 39, count 0 2006.285.13:35:10.56#ibcon#flushed, iclass 39, count 0 2006.285.13:35:10.56#ibcon#about to write, iclass 39, count 0 2006.285.13:35:10.56#ibcon#wrote, iclass 39, count 0 2006.285.13:35:10.56#ibcon#about to read 3, iclass 39, count 0 2006.285.13:35:10.57#ibcon#read 3, iclass 39, count 0 2006.285.13:35:10.57#ibcon#about to read 4, iclass 39, count 0 2006.285.13:35:10.57#ibcon#read 4, iclass 39, count 0 2006.285.13:35:10.58#ibcon#about to read 5, iclass 39, count 0 2006.285.13:35:10.58#ibcon#read 5, iclass 39, count 0 2006.285.13:35:10.58#ibcon#about to read 6, iclass 39, count 0 2006.285.13:35:10.58#ibcon#read 6, iclass 39, count 0 2006.285.13:35:10.58#ibcon#end of sib2, iclass 39, count 0 2006.285.13:35:10.58#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:35:10.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:35:10.58#ibcon#[25=USB\r\n] 2006.285.13:35:10.58#ibcon#*before write, iclass 39, count 0 2006.285.13:35:10.58#ibcon#enter sib2, iclass 39, count 0 2006.285.13:35:10.58#ibcon#flushed, iclass 39, count 0 2006.285.13:35:10.58#ibcon#about to write, iclass 39, count 0 2006.285.13:35:10.58#ibcon#wrote, iclass 39, count 0 2006.285.13:35:10.58#ibcon#about to read 3, iclass 39, count 0 2006.285.13:35:10.60#ibcon#read 3, iclass 39, count 0 2006.285.13:35:10.60#ibcon#about to read 4, iclass 39, count 0 2006.285.13:35:10.60#ibcon#read 4, iclass 39, count 0 2006.285.13:35:10.61#ibcon#about to read 5, iclass 39, count 0 2006.285.13:35:10.61#ibcon#read 5, iclass 39, count 0 2006.285.13:35:10.61#ibcon#about to read 6, iclass 39, count 0 2006.285.13:35:10.61#ibcon#read 6, iclass 39, count 0 2006.285.13:35:10.61#ibcon#end of sib2, iclass 39, count 0 2006.285.13:35:10.61#ibcon#*after write, iclass 39, count 0 2006.285.13:35:10.61#ibcon#*before return 0, iclass 39, count 0 2006.285.13:35:10.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:35:10.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:35:10.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:35:10.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:35:10.61$vck44/valo=3,564.99 2006.285.13:35:10.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.13:35:10.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.13:35:10.61#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:10.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:35:10.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:35:10.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:35:10.61#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:35:10.61#ibcon#first serial, iclass 3, count 0 2006.285.13:35:10.61#ibcon#enter sib2, iclass 3, count 0 2006.285.13:35:10.61#ibcon#flushed, iclass 3, count 0 2006.285.13:35:10.61#ibcon#about to write, iclass 3, count 0 2006.285.13:35:10.61#ibcon#wrote, iclass 3, count 0 2006.285.13:35:10.61#ibcon#about to read 3, iclass 3, count 0 2006.285.13:35:10.62#ibcon#read 3, iclass 3, count 0 2006.285.13:35:10.62#ibcon#about to read 4, iclass 3, count 0 2006.285.13:35:10.63#ibcon#read 4, iclass 3, count 0 2006.285.13:35:10.63#ibcon#about to read 5, iclass 3, count 0 2006.285.13:35:10.63#ibcon#read 5, iclass 3, count 0 2006.285.13:35:10.63#ibcon#about to read 6, iclass 3, count 0 2006.285.13:35:10.63#ibcon#read 6, iclass 3, count 0 2006.285.13:35:10.63#ibcon#end of sib2, iclass 3, count 0 2006.285.13:35:10.63#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:35:10.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:35:10.63#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:35:10.63#ibcon#*before write, iclass 3, count 0 2006.285.13:35:10.63#ibcon#enter sib2, iclass 3, count 0 2006.285.13:35:10.63#ibcon#flushed, iclass 3, count 0 2006.285.13:35:10.63#ibcon#about to write, iclass 3, count 0 2006.285.13:35:10.63#ibcon#wrote, iclass 3, count 0 2006.285.13:35:10.63#ibcon#about to read 3, iclass 3, count 0 2006.285.13:35:10.66#ibcon#read 3, iclass 3, count 0 2006.285.13:35:10.66#ibcon#about to read 4, iclass 3, count 0 2006.285.13:35:10.66#ibcon#read 4, iclass 3, count 0 2006.285.13:35:10.67#ibcon#about to read 5, iclass 3, count 0 2006.285.13:35:10.67#ibcon#read 5, iclass 3, count 0 2006.285.13:35:10.67#ibcon#about to read 6, iclass 3, count 0 2006.285.13:35:10.67#ibcon#read 6, iclass 3, count 0 2006.285.13:35:10.67#ibcon#end of sib2, iclass 3, count 0 2006.285.13:35:10.67#ibcon#*after write, iclass 3, count 0 2006.285.13:35:10.67#ibcon#*before return 0, iclass 3, count 0 2006.285.13:35:10.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:35:10.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:35:10.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:35:10.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:35:10.67$vck44/va=3,7 2006.285.13:35:10.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.13:35:10.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.13:35:10.67#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:10.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:35:10.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:35:10.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:35:10.72#ibcon#enter wrdev, iclass 5, count 2 2006.285.13:35:10.73#ibcon#first serial, iclass 5, count 2 2006.285.13:35:10.73#ibcon#enter sib2, iclass 5, count 2 2006.285.13:35:10.73#ibcon#flushed, iclass 5, count 2 2006.285.13:35:10.73#ibcon#about to write, iclass 5, count 2 2006.285.13:35:10.73#ibcon#wrote, iclass 5, count 2 2006.285.13:35:10.73#ibcon#about to read 3, iclass 5, count 2 2006.285.13:35:10.74#ibcon#read 3, iclass 5, count 2 2006.285.13:35:10.74#ibcon#about to read 4, iclass 5, count 2 2006.285.13:35:10.74#ibcon#read 4, iclass 5, count 2 2006.285.13:35:10.75#ibcon#about to read 5, iclass 5, count 2 2006.285.13:35:10.75#ibcon#read 5, iclass 5, count 2 2006.285.13:35:10.75#ibcon#about to read 6, iclass 5, count 2 2006.285.13:35:10.75#ibcon#read 6, iclass 5, count 2 2006.285.13:35:10.75#ibcon#end of sib2, iclass 5, count 2 2006.285.13:35:10.75#ibcon#*mode == 0, iclass 5, count 2 2006.285.13:35:10.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.13:35:10.75#ibcon#[25=AT03-07\r\n] 2006.285.13:35:10.75#ibcon#*before write, iclass 5, count 2 2006.285.13:35:10.75#ibcon#enter sib2, iclass 5, count 2 2006.285.13:35:10.75#ibcon#flushed, iclass 5, count 2 2006.285.13:35:10.75#ibcon#about to write, iclass 5, count 2 2006.285.13:35:10.75#ibcon#wrote, iclass 5, count 2 2006.285.13:35:10.75#ibcon#about to read 3, iclass 5, count 2 2006.285.13:35:10.77#ibcon#read 3, iclass 5, count 2 2006.285.13:35:10.77#ibcon#about to read 4, iclass 5, count 2 2006.285.13:35:10.77#ibcon#read 4, iclass 5, count 2 2006.285.13:35:10.78#ibcon#about to read 5, iclass 5, count 2 2006.285.13:35:10.78#ibcon#read 5, iclass 5, count 2 2006.285.13:35:10.78#ibcon#about to read 6, iclass 5, count 2 2006.285.13:35:10.78#ibcon#read 6, iclass 5, count 2 2006.285.13:35:10.78#ibcon#end of sib2, iclass 5, count 2 2006.285.13:35:10.78#ibcon#*after write, iclass 5, count 2 2006.285.13:35:10.78#ibcon#*before return 0, iclass 5, count 2 2006.285.13:35:10.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:35:10.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:35:10.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.13:35:10.78#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:10.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:35:10.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:35:10.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:35:10.89#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:35:10.90#ibcon#first serial, iclass 5, count 0 2006.285.13:35:10.90#ibcon#enter sib2, iclass 5, count 0 2006.285.13:35:10.90#ibcon#flushed, iclass 5, count 0 2006.285.13:35:10.90#ibcon#about to write, iclass 5, count 0 2006.285.13:35:10.90#ibcon#wrote, iclass 5, count 0 2006.285.13:35:10.90#ibcon#about to read 3, iclass 5, count 0 2006.285.13:35:10.91#ibcon#read 3, iclass 5, count 0 2006.285.13:35:10.91#ibcon#about to read 4, iclass 5, count 0 2006.285.13:35:10.91#ibcon#read 4, iclass 5, count 0 2006.285.13:35:10.92#ibcon#about to read 5, iclass 5, count 0 2006.285.13:35:10.92#ibcon#read 5, iclass 5, count 0 2006.285.13:35:10.92#ibcon#about to read 6, iclass 5, count 0 2006.285.13:35:10.92#ibcon#read 6, iclass 5, count 0 2006.285.13:35:10.92#ibcon#end of sib2, iclass 5, count 0 2006.285.13:35:10.92#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:35:10.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:35:10.92#ibcon#[25=USB\r\n] 2006.285.13:35:10.92#ibcon#*before write, iclass 5, count 0 2006.285.13:35:10.92#ibcon#enter sib2, iclass 5, count 0 2006.285.13:35:10.92#ibcon#flushed, iclass 5, count 0 2006.285.13:35:10.92#ibcon#about to write, iclass 5, count 0 2006.285.13:35:10.92#ibcon#wrote, iclass 5, count 0 2006.285.13:35:10.92#ibcon#about to read 3, iclass 5, count 0 2006.285.13:35:10.94#ibcon#read 3, iclass 5, count 0 2006.285.13:35:10.94#ibcon#about to read 4, iclass 5, count 0 2006.285.13:35:10.94#ibcon#read 4, iclass 5, count 0 2006.285.13:35:10.95#ibcon#about to read 5, iclass 5, count 0 2006.285.13:35:10.95#ibcon#read 5, iclass 5, count 0 2006.285.13:35:10.95#ibcon#about to read 6, iclass 5, count 0 2006.285.13:35:10.95#ibcon#read 6, iclass 5, count 0 2006.285.13:35:10.95#ibcon#end of sib2, iclass 5, count 0 2006.285.13:35:10.95#ibcon#*after write, iclass 5, count 0 2006.285.13:35:10.95#ibcon#*before return 0, iclass 5, count 0 2006.285.13:35:10.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:35:10.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:35:10.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:35:10.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:35:10.95$vck44/valo=4,624.99 2006.285.13:35:10.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.13:35:10.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.13:35:10.95#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:10.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:35:10.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:35:10.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:35:10.95#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:35:10.95#ibcon#first serial, iclass 7, count 0 2006.285.13:35:10.95#ibcon#enter sib2, iclass 7, count 0 2006.285.13:35:10.95#ibcon#flushed, iclass 7, count 0 2006.285.13:35:10.95#ibcon#about to write, iclass 7, count 0 2006.285.13:35:10.95#ibcon#wrote, iclass 7, count 0 2006.285.13:35:10.95#ibcon#about to read 3, iclass 7, count 0 2006.285.13:35:10.96#ibcon#read 3, iclass 7, count 0 2006.285.13:35:10.96#ibcon#about to read 4, iclass 7, count 0 2006.285.13:35:10.97#ibcon#read 4, iclass 7, count 0 2006.285.13:35:10.97#ibcon#about to read 5, iclass 7, count 0 2006.285.13:35:10.97#ibcon#read 5, iclass 7, count 0 2006.285.13:35:10.97#ibcon#about to read 6, iclass 7, count 0 2006.285.13:35:10.97#ibcon#read 6, iclass 7, count 0 2006.285.13:35:10.97#ibcon#end of sib2, iclass 7, count 0 2006.285.13:35:10.97#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:35:10.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:35:10.97#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:35:10.97#ibcon#*before write, iclass 7, count 0 2006.285.13:35:10.97#ibcon#enter sib2, iclass 7, count 0 2006.285.13:35:10.97#ibcon#flushed, iclass 7, count 0 2006.285.13:35:10.97#ibcon#about to write, iclass 7, count 0 2006.285.13:35:10.97#ibcon#wrote, iclass 7, count 0 2006.285.13:35:10.97#ibcon#about to read 3, iclass 7, count 0 2006.285.13:35:11.00#ibcon#read 3, iclass 7, count 0 2006.285.13:35:11.01#ibcon#about to read 4, iclass 7, count 0 2006.285.13:35:11.01#ibcon#read 4, iclass 7, count 0 2006.285.13:35:11.01#ibcon#about to read 5, iclass 7, count 0 2006.285.13:35:11.01#ibcon#read 5, iclass 7, count 0 2006.285.13:35:11.01#ibcon#about to read 6, iclass 7, count 0 2006.285.13:35:11.01#ibcon#read 6, iclass 7, count 0 2006.285.13:35:11.01#ibcon#end of sib2, iclass 7, count 0 2006.285.13:35:11.01#ibcon#*after write, iclass 7, count 0 2006.285.13:35:11.01#ibcon#*before return 0, iclass 7, count 0 2006.285.13:35:11.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:35:11.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:35:11.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:35:11.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:35:11.01$vck44/va=4,6 2006.285.13:35:11.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.13:35:11.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.13:35:11.01#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:11.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:35:11.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:35:11.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:35:11.07#ibcon#enter wrdev, iclass 11, count 2 2006.285.13:35:11.07#ibcon#first serial, iclass 11, count 2 2006.285.13:35:11.07#ibcon#enter sib2, iclass 11, count 2 2006.285.13:35:11.07#ibcon#flushed, iclass 11, count 2 2006.285.13:35:11.07#ibcon#about to write, iclass 11, count 2 2006.285.13:35:11.07#ibcon#wrote, iclass 11, count 2 2006.285.13:35:11.07#ibcon#about to read 3, iclass 11, count 2 2006.285.13:35:11.08#ibcon#read 3, iclass 11, count 2 2006.285.13:35:11.08#ibcon#about to read 4, iclass 11, count 2 2006.285.13:35:11.08#ibcon#read 4, iclass 11, count 2 2006.285.13:35:11.08#ibcon#about to read 5, iclass 11, count 2 2006.285.13:35:11.09#ibcon#read 5, iclass 11, count 2 2006.285.13:35:11.09#ibcon#about to read 6, iclass 11, count 2 2006.285.13:35:11.09#ibcon#read 6, iclass 11, count 2 2006.285.13:35:11.09#ibcon#end of sib2, iclass 11, count 2 2006.285.13:35:11.09#ibcon#*mode == 0, iclass 11, count 2 2006.285.13:35:11.09#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.13:35:11.09#ibcon#[25=AT04-06\r\n] 2006.285.13:35:11.09#ibcon#*before write, iclass 11, count 2 2006.285.13:35:11.09#ibcon#enter sib2, iclass 11, count 2 2006.285.13:35:11.09#ibcon#flushed, iclass 11, count 2 2006.285.13:35:11.09#ibcon#about to write, iclass 11, count 2 2006.285.13:35:11.09#ibcon#wrote, iclass 11, count 2 2006.285.13:35:11.09#ibcon#about to read 3, iclass 11, count 2 2006.285.13:35:11.11#ibcon#read 3, iclass 11, count 2 2006.285.13:35:11.11#ibcon#about to read 4, iclass 11, count 2 2006.285.13:35:11.11#ibcon#read 4, iclass 11, count 2 2006.285.13:35:11.11#ibcon#about to read 5, iclass 11, count 2 2006.285.13:35:11.11#ibcon#read 5, iclass 11, count 2 2006.285.13:35:11.12#ibcon#about to read 6, iclass 11, count 2 2006.285.13:35:11.12#ibcon#read 6, iclass 11, count 2 2006.285.13:35:11.12#ibcon#end of sib2, iclass 11, count 2 2006.285.13:35:11.12#ibcon#*after write, iclass 11, count 2 2006.285.13:35:11.12#ibcon#*before return 0, iclass 11, count 2 2006.285.13:35:11.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:35:11.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:35:11.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.13:35:11.12#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:11.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:35:11.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:35:11.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:35:11.58#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:35:11.58#ibcon#first serial, iclass 11, count 0 2006.285.13:35:11.58#ibcon#enter sib2, iclass 11, count 0 2006.285.13:35:11.58#ibcon#flushed, iclass 11, count 0 2006.285.13:35:11.58#ibcon#about to write, iclass 11, count 0 2006.285.13:35:11.58#ibcon#wrote, iclass 11, count 0 2006.285.13:35:11.58#ibcon#about to read 3, iclass 11, count 0 2006.285.13:35:11.59#ibcon#read 3, iclass 11, count 0 2006.285.13:35:11.60#ibcon#about to read 4, iclass 11, count 0 2006.285.13:35:11.60#ibcon#read 4, iclass 11, count 0 2006.285.13:35:11.60#ibcon#about to read 5, iclass 11, count 0 2006.285.13:35:11.60#ibcon#read 5, iclass 11, count 0 2006.285.13:35:11.60#ibcon#about to read 6, iclass 11, count 0 2006.285.13:35:11.60#ibcon#read 6, iclass 11, count 0 2006.285.13:35:11.60#ibcon#end of sib2, iclass 11, count 0 2006.285.13:35:11.60#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:35:11.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:35:11.60#ibcon#[25=USB\r\n] 2006.285.13:35:11.60#ibcon#*before write, iclass 11, count 0 2006.285.13:35:11.60#ibcon#enter sib2, iclass 11, count 0 2006.285.13:35:11.60#ibcon#flushed, iclass 11, count 0 2006.285.13:35:11.60#ibcon#about to write, iclass 11, count 0 2006.285.13:35:11.60#ibcon#wrote, iclass 11, count 0 2006.285.13:35:11.60#ibcon#about to read 3, iclass 11, count 0 2006.285.13:35:11.62#ibcon#read 3, iclass 11, count 0 2006.285.13:35:11.63#ibcon#about to read 4, iclass 11, count 0 2006.285.13:35:11.63#ibcon#read 4, iclass 11, count 0 2006.285.13:35:11.63#ibcon#about to read 5, iclass 11, count 0 2006.285.13:35:11.63#ibcon#read 5, iclass 11, count 0 2006.285.13:35:11.63#ibcon#about to read 6, iclass 11, count 0 2006.285.13:35:11.63#ibcon#read 6, iclass 11, count 0 2006.285.13:35:11.63#ibcon#end of sib2, iclass 11, count 0 2006.285.13:35:11.63#ibcon#*after write, iclass 11, count 0 2006.285.13:35:11.63#ibcon#*before return 0, iclass 11, count 0 2006.285.13:35:11.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:35:11.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:35:11.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:35:11.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:35:11.63$vck44/valo=5,734.99 2006.285.13:35:11.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.13:35:11.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.13:35:11.63#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:11.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:35:11.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:35:11.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:35:11.63#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:35:11.63#ibcon#first serial, iclass 13, count 0 2006.285.13:35:11.63#ibcon#enter sib2, iclass 13, count 0 2006.285.13:35:11.63#ibcon#flushed, iclass 13, count 0 2006.285.13:35:11.63#ibcon#about to write, iclass 13, count 0 2006.285.13:35:11.63#ibcon#wrote, iclass 13, count 0 2006.285.13:35:11.63#ibcon#about to read 3, iclass 13, count 0 2006.285.13:35:11.64#ibcon#read 3, iclass 13, count 0 2006.285.13:35:11.65#ibcon#about to read 4, iclass 13, count 0 2006.285.13:35:11.65#ibcon#read 4, iclass 13, count 0 2006.285.13:35:11.65#ibcon#about to read 5, iclass 13, count 0 2006.285.13:35:11.65#ibcon#read 5, iclass 13, count 0 2006.285.13:35:11.65#ibcon#about to read 6, iclass 13, count 0 2006.285.13:35:11.65#ibcon#read 6, iclass 13, count 0 2006.285.13:35:11.65#ibcon#end of sib2, iclass 13, count 0 2006.285.13:35:11.65#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:35:11.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:35:11.65#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:35:11.65#ibcon#*before write, iclass 13, count 0 2006.285.13:35:11.65#ibcon#enter sib2, iclass 13, count 0 2006.285.13:35:11.65#ibcon#flushed, iclass 13, count 0 2006.285.13:35:11.65#ibcon#about to write, iclass 13, count 0 2006.285.13:35:11.65#ibcon#wrote, iclass 13, count 0 2006.285.13:35:11.65#ibcon#about to read 3, iclass 13, count 0 2006.285.13:35:11.68#ibcon#read 3, iclass 13, count 0 2006.285.13:35:11.69#ibcon#about to read 4, iclass 13, count 0 2006.285.13:35:11.69#ibcon#read 4, iclass 13, count 0 2006.285.13:35:11.69#ibcon#about to read 5, iclass 13, count 0 2006.285.13:35:11.69#ibcon#read 5, iclass 13, count 0 2006.285.13:35:11.69#ibcon#about to read 6, iclass 13, count 0 2006.285.13:35:11.69#ibcon#read 6, iclass 13, count 0 2006.285.13:35:11.69#ibcon#end of sib2, iclass 13, count 0 2006.285.13:35:11.69#ibcon#*after write, iclass 13, count 0 2006.285.13:35:11.69#ibcon#*before return 0, iclass 13, count 0 2006.285.13:35:11.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:35:11.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:35:11.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:35:11.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:35:11.69$vck44/va=5,3 2006.285.13:35:11.69#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.13:35:11.69#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.13:35:11.69#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:11.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:35:11.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:35:11.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:35:11.75#ibcon#enter wrdev, iclass 15, count 2 2006.285.13:35:11.75#ibcon#first serial, iclass 15, count 2 2006.285.13:35:11.75#ibcon#enter sib2, iclass 15, count 2 2006.285.13:35:11.75#ibcon#flushed, iclass 15, count 2 2006.285.13:35:11.75#ibcon#about to write, iclass 15, count 2 2006.285.13:35:11.75#ibcon#wrote, iclass 15, count 2 2006.285.13:35:11.75#ibcon#about to read 3, iclass 15, count 2 2006.285.13:35:11.76#ibcon#read 3, iclass 15, count 2 2006.285.13:35:11.77#ibcon#about to read 4, iclass 15, count 2 2006.285.13:35:11.77#ibcon#read 4, iclass 15, count 2 2006.285.13:35:11.77#ibcon#about to read 5, iclass 15, count 2 2006.285.13:35:11.77#ibcon#read 5, iclass 15, count 2 2006.285.13:35:11.77#ibcon#about to read 6, iclass 15, count 2 2006.285.13:35:11.77#ibcon#read 6, iclass 15, count 2 2006.285.13:35:11.77#ibcon#end of sib2, iclass 15, count 2 2006.285.13:35:11.77#ibcon#*mode == 0, iclass 15, count 2 2006.285.13:35:11.77#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.13:35:11.77#ibcon#[25=AT05-03\r\n] 2006.285.13:35:11.77#ibcon#*before write, iclass 15, count 2 2006.285.13:35:11.77#ibcon#enter sib2, iclass 15, count 2 2006.285.13:35:11.77#ibcon#flushed, iclass 15, count 2 2006.285.13:35:11.77#ibcon#about to write, iclass 15, count 2 2006.285.13:35:11.77#ibcon#wrote, iclass 15, count 2 2006.285.13:35:11.77#ibcon#about to read 3, iclass 15, count 2 2006.285.13:35:11.79#ibcon#read 3, iclass 15, count 2 2006.285.13:35:11.80#ibcon#about to read 4, iclass 15, count 2 2006.285.13:35:11.80#ibcon#read 4, iclass 15, count 2 2006.285.13:35:11.80#ibcon#about to read 5, iclass 15, count 2 2006.285.13:35:11.80#ibcon#read 5, iclass 15, count 2 2006.285.13:35:11.80#ibcon#about to read 6, iclass 15, count 2 2006.285.13:35:11.80#ibcon#read 6, iclass 15, count 2 2006.285.13:35:11.80#ibcon#end of sib2, iclass 15, count 2 2006.285.13:35:11.80#ibcon#*after write, iclass 15, count 2 2006.285.13:35:11.80#ibcon#*before return 0, iclass 15, count 2 2006.285.13:35:11.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:35:11.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:35:11.80#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.13:35:11.80#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:11.80#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:35:11.91#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:35:12.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:35:12.14#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:35:12.14#ibcon#first serial, iclass 15, count 0 2006.285.13:35:12.14#ibcon#enter sib2, iclass 15, count 0 2006.285.13:35:12.14#ibcon#flushed, iclass 15, count 0 2006.285.13:35:12.14#ibcon#about to write, iclass 15, count 0 2006.285.13:35:12.14#ibcon#wrote, iclass 15, count 0 2006.285.13:35:12.14#ibcon#about to read 3, iclass 15, count 0 2006.285.13:35:12.15#ibcon#read 3, iclass 15, count 0 2006.285.13:35:12.16#ibcon#about to read 4, iclass 15, count 0 2006.285.13:35:12.16#ibcon#read 4, iclass 15, count 0 2006.285.13:35:12.16#ibcon#about to read 5, iclass 15, count 0 2006.285.13:35:12.16#ibcon#read 5, iclass 15, count 0 2006.285.13:35:12.16#ibcon#about to read 6, iclass 15, count 0 2006.285.13:35:12.16#ibcon#read 6, iclass 15, count 0 2006.285.13:35:12.16#ibcon#end of sib2, iclass 15, count 0 2006.285.13:35:12.16#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:35:12.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:35:12.16#ibcon#[25=USB\r\n] 2006.285.13:35:12.16#ibcon#*before write, iclass 15, count 0 2006.285.13:35:12.16#ibcon#enter sib2, iclass 15, count 0 2006.285.13:35:12.16#ibcon#flushed, iclass 15, count 0 2006.285.13:35:12.16#ibcon#about to write, iclass 15, count 0 2006.285.13:35:12.16#ibcon#wrote, iclass 15, count 0 2006.285.13:35:12.16#ibcon#about to read 3, iclass 15, count 0 2006.285.13:35:12.18#ibcon#read 3, iclass 15, count 0 2006.285.13:35:12.18#ibcon#about to read 4, iclass 15, count 0 2006.285.13:35:12.19#ibcon#read 4, iclass 15, count 0 2006.285.13:35:12.19#ibcon#about to read 5, iclass 15, count 0 2006.285.13:35:12.19#ibcon#read 5, iclass 15, count 0 2006.285.13:35:12.19#ibcon#about to read 6, iclass 15, count 0 2006.285.13:35:12.19#ibcon#read 6, iclass 15, count 0 2006.285.13:35:12.19#ibcon#end of sib2, iclass 15, count 0 2006.285.13:35:12.19#ibcon#*after write, iclass 15, count 0 2006.285.13:35:12.19#ibcon#*before return 0, iclass 15, count 0 2006.285.13:35:12.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:35:12.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:35:12.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:35:12.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:35:12.19$vck44/valo=6,814.99 2006.285.13:35:12.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.13:35:12.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.13:35:12.19#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:12.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:35:12.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:35:12.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:35:12.19#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:35:12.19#ibcon#first serial, iclass 17, count 0 2006.285.13:35:12.19#ibcon#enter sib2, iclass 17, count 0 2006.285.13:35:12.19#ibcon#flushed, iclass 17, count 0 2006.285.13:35:12.19#ibcon#about to write, iclass 17, count 0 2006.285.13:35:12.19#ibcon#wrote, iclass 17, count 0 2006.285.13:35:12.19#ibcon#about to read 3, iclass 17, count 0 2006.285.13:35:12.20#ibcon#read 3, iclass 17, count 0 2006.285.13:35:12.20#ibcon#about to read 4, iclass 17, count 0 2006.285.13:35:12.21#ibcon#read 4, iclass 17, count 0 2006.285.13:35:12.21#ibcon#about to read 5, iclass 17, count 0 2006.285.13:35:12.21#ibcon#read 5, iclass 17, count 0 2006.285.13:35:12.21#ibcon#about to read 6, iclass 17, count 0 2006.285.13:35:12.21#ibcon#read 6, iclass 17, count 0 2006.285.13:35:12.21#ibcon#end of sib2, iclass 17, count 0 2006.285.13:35:12.21#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:35:12.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:35:12.21#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:35:12.21#ibcon#*before write, iclass 17, count 0 2006.285.13:35:12.21#ibcon#enter sib2, iclass 17, count 0 2006.285.13:35:12.21#ibcon#flushed, iclass 17, count 0 2006.285.13:35:12.21#ibcon#about to write, iclass 17, count 0 2006.285.13:35:12.21#ibcon#wrote, iclass 17, count 0 2006.285.13:35:12.21#ibcon#about to read 3, iclass 17, count 0 2006.285.13:35:12.24#ibcon#read 3, iclass 17, count 0 2006.285.13:35:12.24#ibcon#about to read 4, iclass 17, count 0 2006.285.13:35:12.25#ibcon#read 4, iclass 17, count 0 2006.285.13:35:12.25#ibcon#about to read 5, iclass 17, count 0 2006.285.13:35:12.25#ibcon#read 5, iclass 17, count 0 2006.285.13:35:12.25#ibcon#about to read 6, iclass 17, count 0 2006.285.13:35:12.25#ibcon#read 6, iclass 17, count 0 2006.285.13:35:12.25#ibcon#end of sib2, iclass 17, count 0 2006.285.13:35:12.25#ibcon#*after write, iclass 17, count 0 2006.285.13:35:12.25#ibcon#*before return 0, iclass 17, count 0 2006.285.13:35:12.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:35:12.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:35:12.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:35:12.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:35:12.25$vck44/va=6,4 2006.285.13:35:12.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.13:35:12.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.13:35:12.25#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:12.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:35:12.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:35:12.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:35:12.31#ibcon#enter wrdev, iclass 19, count 2 2006.285.13:35:12.31#ibcon#first serial, iclass 19, count 2 2006.285.13:35:12.31#ibcon#enter sib2, iclass 19, count 2 2006.285.13:35:12.31#ibcon#flushed, iclass 19, count 2 2006.285.13:35:12.31#ibcon#about to write, iclass 19, count 2 2006.285.13:35:12.31#ibcon#wrote, iclass 19, count 2 2006.285.13:35:12.31#ibcon#about to read 3, iclass 19, count 2 2006.285.13:35:12.32#ibcon#read 3, iclass 19, count 2 2006.285.13:35:12.33#ibcon#about to read 4, iclass 19, count 2 2006.285.13:35:12.33#ibcon#read 4, iclass 19, count 2 2006.285.13:35:12.33#ibcon#about to read 5, iclass 19, count 2 2006.285.13:35:12.33#ibcon#read 5, iclass 19, count 2 2006.285.13:35:12.33#ibcon#about to read 6, iclass 19, count 2 2006.285.13:35:12.33#ibcon#read 6, iclass 19, count 2 2006.285.13:35:12.33#ibcon#end of sib2, iclass 19, count 2 2006.285.13:35:12.33#ibcon#*mode == 0, iclass 19, count 2 2006.285.13:35:12.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.13:35:12.33#ibcon#[25=AT06-04\r\n] 2006.285.13:35:12.33#ibcon#*before write, iclass 19, count 2 2006.285.13:35:12.33#ibcon#enter sib2, iclass 19, count 2 2006.285.13:35:12.33#ibcon#flushed, iclass 19, count 2 2006.285.13:35:12.33#ibcon#about to write, iclass 19, count 2 2006.285.13:35:12.33#ibcon#wrote, iclass 19, count 2 2006.285.13:35:12.33#ibcon#about to read 3, iclass 19, count 2 2006.285.13:35:12.35#ibcon#read 3, iclass 19, count 2 2006.285.13:35:12.35#ibcon#about to read 4, iclass 19, count 2 2006.285.13:35:12.35#ibcon#read 4, iclass 19, count 2 2006.285.13:35:12.36#ibcon#about to read 5, iclass 19, count 2 2006.285.13:35:12.36#ibcon#read 5, iclass 19, count 2 2006.285.13:35:12.36#ibcon#about to read 6, iclass 19, count 2 2006.285.13:35:12.36#ibcon#read 6, iclass 19, count 2 2006.285.13:35:12.36#ibcon#end of sib2, iclass 19, count 2 2006.285.13:35:12.36#ibcon#*after write, iclass 19, count 2 2006.285.13:35:12.36#ibcon#*before return 0, iclass 19, count 2 2006.285.13:35:12.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:35:12.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:35:12.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.13:35:12.36#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:12.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:35:12.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:35:12.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:35:12.48#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:35:12.48#ibcon#first serial, iclass 19, count 0 2006.285.13:35:12.48#ibcon#enter sib2, iclass 19, count 0 2006.285.13:35:12.48#ibcon#flushed, iclass 19, count 0 2006.285.13:35:12.48#ibcon#about to write, iclass 19, count 0 2006.285.13:35:12.48#ibcon#wrote, iclass 19, count 0 2006.285.13:35:12.48#ibcon#about to read 3, iclass 19, count 0 2006.285.13:35:12.49#ibcon#read 3, iclass 19, count 0 2006.285.13:35:12.49#ibcon#about to read 4, iclass 19, count 0 2006.285.13:35:12.50#ibcon#read 4, iclass 19, count 0 2006.285.13:35:12.50#ibcon#about to read 5, iclass 19, count 0 2006.285.13:35:12.50#ibcon#read 5, iclass 19, count 0 2006.285.13:35:12.50#ibcon#about to read 6, iclass 19, count 0 2006.285.13:35:12.50#ibcon#read 6, iclass 19, count 0 2006.285.13:35:12.50#ibcon#end of sib2, iclass 19, count 0 2006.285.13:35:12.50#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:35:12.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:35:12.50#ibcon#[25=USB\r\n] 2006.285.13:35:12.50#ibcon#*before write, iclass 19, count 0 2006.285.13:35:12.50#ibcon#enter sib2, iclass 19, count 0 2006.285.13:35:12.50#ibcon#flushed, iclass 19, count 0 2006.285.13:35:12.50#ibcon#about to write, iclass 19, count 0 2006.285.13:35:12.50#ibcon#wrote, iclass 19, count 0 2006.285.13:35:12.50#ibcon#about to read 3, iclass 19, count 0 2006.285.13:35:12.52#ibcon#read 3, iclass 19, count 0 2006.285.13:35:12.53#ibcon#about to read 4, iclass 19, count 0 2006.285.13:35:12.53#ibcon#read 4, iclass 19, count 0 2006.285.13:35:12.53#ibcon#about to read 5, iclass 19, count 0 2006.285.13:35:12.53#ibcon#read 5, iclass 19, count 0 2006.285.13:35:12.53#ibcon#about to read 6, iclass 19, count 0 2006.285.13:35:12.53#ibcon#read 6, iclass 19, count 0 2006.285.13:35:12.53#ibcon#end of sib2, iclass 19, count 0 2006.285.13:35:12.53#ibcon#*after write, iclass 19, count 0 2006.285.13:35:12.53#ibcon#*before return 0, iclass 19, count 0 2006.285.13:35:12.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:35:12.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:35:12.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:35:12.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:35:12.53$vck44/valo=7,864.99 2006.285.13:35:12.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.13:35:12.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.13:35:12.53#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:12.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:35:12.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:35:12.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:35:12.53#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:35:12.53#ibcon#first serial, iclass 21, count 0 2006.285.13:35:12.53#ibcon#enter sib2, iclass 21, count 0 2006.285.13:35:12.53#ibcon#flushed, iclass 21, count 0 2006.285.13:35:12.53#ibcon#about to write, iclass 21, count 0 2006.285.13:35:12.53#ibcon#wrote, iclass 21, count 0 2006.285.13:35:12.53#ibcon#about to read 3, iclass 21, count 0 2006.285.13:35:12.54#ibcon#read 3, iclass 21, count 0 2006.285.13:35:12.54#ibcon#about to read 4, iclass 21, count 0 2006.285.13:35:12.55#ibcon#read 4, iclass 21, count 0 2006.285.13:35:12.55#ibcon#about to read 5, iclass 21, count 0 2006.285.13:35:12.55#ibcon#read 5, iclass 21, count 0 2006.285.13:35:12.55#ibcon#about to read 6, iclass 21, count 0 2006.285.13:35:12.55#ibcon#read 6, iclass 21, count 0 2006.285.13:35:12.55#ibcon#end of sib2, iclass 21, count 0 2006.285.13:35:12.55#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:35:12.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:35:12.55#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:35:12.55#ibcon#*before write, iclass 21, count 0 2006.285.13:35:12.55#ibcon#enter sib2, iclass 21, count 0 2006.285.13:35:12.55#ibcon#flushed, iclass 21, count 0 2006.285.13:35:12.55#ibcon#about to write, iclass 21, count 0 2006.285.13:35:12.55#ibcon#wrote, iclass 21, count 0 2006.285.13:35:12.55#ibcon#about to read 3, iclass 21, count 0 2006.285.13:35:12.58#ibcon#read 3, iclass 21, count 0 2006.285.13:35:12.58#ibcon#about to read 4, iclass 21, count 0 2006.285.13:35:12.59#ibcon#read 4, iclass 21, count 0 2006.285.13:35:12.59#ibcon#about to read 5, iclass 21, count 0 2006.285.13:35:12.59#ibcon#read 5, iclass 21, count 0 2006.285.13:35:12.59#ibcon#about to read 6, iclass 21, count 0 2006.285.13:35:12.59#ibcon#read 6, iclass 21, count 0 2006.285.13:35:12.59#ibcon#end of sib2, iclass 21, count 0 2006.285.13:35:12.59#ibcon#*after write, iclass 21, count 0 2006.285.13:35:12.59#ibcon#*before return 0, iclass 21, count 0 2006.285.13:35:12.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:35:12.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:35:12.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:35:12.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:35:12.59$vck44/va=7,4 2006.285.13:35:12.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.13:35:12.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.13:35:12.59#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:12.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:35:12.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:35:12.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:35:12.65#ibcon#enter wrdev, iclass 23, count 2 2006.285.13:35:12.65#ibcon#first serial, iclass 23, count 2 2006.285.13:35:12.65#ibcon#enter sib2, iclass 23, count 2 2006.285.13:35:12.65#ibcon#flushed, iclass 23, count 2 2006.285.13:35:12.65#ibcon#about to write, iclass 23, count 2 2006.285.13:35:12.65#ibcon#wrote, iclass 23, count 2 2006.285.13:35:12.65#ibcon#about to read 3, iclass 23, count 2 2006.285.13:35:12.66#ibcon#read 3, iclass 23, count 2 2006.285.13:35:12.66#ibcon#about to read 4, iclass 23, count 2 2006.285.13:35:12.66#ibcon#read 4, iclass 23, count 2 2006.285.13:35:12.67#ibcon#about to read 5, iclass 23, count 2 2006.285.13:35:12.67#ibcon#read 5, iclass 23, count 2 2006.285.13:35:12.67#ibcon#about to read 6, iclass 23, count 2 2006.285.13:35:12.67#ibcon#read 6, iclass 23, count 2 2006.285.13:35:12.67#ibcon#end of sib2, iclass 23, count 2 2006.285.13:35:12.67#ibcon#*mode == 0, iclass 23, count 2 2006.285.13:35:12.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.13:35:12.67#ibcon#[25=AT07-04\r\n] 2006.285.13:35:12.67#ibcon#*before write, iclass 23, count 2 2006.285.13:35:12.67#ibcon#enter sib2, iclass 23, count 2 2006.285.13:35:12.67#ibcon#flushed, iclass 23, count 2 2006.285.13:35:12.67#ibcon#about to write, iclass 23, count 2 2006.285.13:35:12.67#ibcon#wrote, iclass 23, count 2 2006.285.13:35:12.67#ibcon#about to read 3, iclass 23, count 2 2006.285.13:35:12.69#ibcon#read 3, iclass 23, count 2 2006.285.13:35:12.69#ibcon#about to read 4, iclass 23, count 2 2006.285.13:35:12.69#ibcon#read 4, iclass 23, count 2 2006.285.13:35:12.70#ibcon#about to read 5, iclass 23, count 2 2006.285.13:35:12.70#ibcon#read 5, iclass 23, count 2 2006.285.13:35:12.70#ibcon#about to read 6, iclass 23, count 2 2006.285.13:35:12.70#ibcon#read 6, iclass 23, count 2 2006.285.13:35:12.70#ibcon#end of sib2, iclass 23, count 2 2006.285.13:35:12.70#ibcon#*after write, iclass 23, count 2 2006.285.13:35:12.70#ibcon#*before return 0, iclass 23, count 2 2006.285.13:35:12.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:35:12.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:35:12.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.13:35:12.70#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:12.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:35:12.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:35:12.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:35:12.81#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:35:12.81#ibcon#first serial, iclass 23, count 0 2006.285.13:35:12.82#ibcon#enter sib2, iclass 23, count 0 2006.285.13:35:12.82#ibcon#flushed, iclass 23, count 0 2006.285.13:35:12.82#ibcon#about to write, iclass 23, count 0 2006.285.13:35:12.82#ibcon#wrote, iclass 23, count 0 2006.285.13:35:12.82#ibcon#about to read 3, iclass 23, count 0 2006.285.13:35:12.83#ibcon#read 3, iclass 23, count 0 2006.285.13:35:12.83#ibcon#about to read 4, iclass 23, count 0 2006.285.13:35:12.83#ibcon#read 4, iclass 23, count 0 2006.285.13:35:12.83#ibcon#about to read 5, iclass 23, count 0 2006.285.13:35:12.84#ibcon#read 5, iclass 23, count 0 2006.285.13:35:12.84#ibcon#about to read 6, iclass 23, count 0 2006.285.13:35:12.84#ibcon#read 6, iclass 23, count 0 2006.285.13:35:12.84#ibcon#end of sib2, iclass 23, count 0 2006.285.13:35:12.84#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:35:12.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:35:12.84#ibcon#[25=USB\r\n] 2006.285.13:35:12.84#ibcon#*before write, iclass 23, count 0 2006.285.13:35:12.84#ibcon#enter sib2, iclass 23, count 0 2006.285.13:35:12.84#ibcon#flushed, iclass 23, count 0 2006.285.13:35:12.84#ibcon#about to write, iclass 23, count 0 2006.285.13:35:12.84#ibcon#wrote, iclass 23, count 0 2006.285.13:35:12.84#ibcon#about to read 3, iclass 23, count 0 2006.285.13:35:12.86#ibcon#read 3, iclass 23, count 0 2006.285.13:35:12.86#ibcon#about to read 4, iclass 23, count 0 2006.285.13:35:12.86#ibcon#read 4, iclass 23, count 0 2006.285.13:35:12.87#ibcon#about to read 5, iclass 23, count 0 2006.285.13:35:12.87#ibcon#read 5, iclass 23, count 0 2006.285.13:35:12.87#ibcon#about to read 6, iclass 23, count 0 2006.285.13:35:12.87#ibcon#read 6, iclass 23, count 0 2006.285.13:35:12.87#ibcon#end of sib2, iclass 23, count 0 2006.285.13:35:12.87#ibcon#*after write, iclass 23, count 0 2006.285.13:35:12.87#ibcon#*before return 0, iclass 23, count 0 2006.285.13:35:12.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:35:12.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:35:12.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:35:12.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:35:12.87$vck44/valo=8,884.99 2006.285.13:35:12.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.13:35:12.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.13:35:12.87#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:12.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:35:12.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:35:12.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:35:12.87#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:35:12.87#ibcon#first serial, iclass 25, count 0 2006.285.13:35:12.87#ibcon#enter sib2, iclass 25, count 0 2006.285.13:35:12.87#ibcon#flushed, iclass 25, count 0 2006.285.13:35:12.87#ibcon#about to write, iclass 25, count 0 2006.285.13:35:12.87#ibcon#wrote, iclass 25, count 0 2006.285.13:35:12.87#ibcon#about to read 3, iclass 25, count 0 2006.285.13:35:12.88#ibcon#read 3, iclass 25, count 0 2006.285.13:35:12.88#ibcon#about to read 4, iclass 25, count 0 2006.285.13:35:12.88#ibcon#read 4, iclass 25, count 0 2006.285.13:35:12.89#ibcon#about to read 5, iclass 25, count 0 2006.285.13:35:12.89#ibcon#read 5, iclass 25, count 0 2006.285.13:35:12.89#ibcon#about to read 6, iclass 25, count 0 2006.285.13:35:12.89#ibcon#read 6, iclass 25, count 0 2006.285.13:35:12.89#ibcon#end of sib2, iclass 25, count 0 2006.285.13:35:12.89#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:35:12.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:35:12.89#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:35:12.89#ibcon#*before write, iclass 25, count 0 2006.285.13:35:12.89#ibcon#enter sib2, iclass 25, count 0 2006.285.13:35:12.89#ibcon#flushed, iclass 25, count 0 2006.285.13:35:12.89#ibcon#about to write, iclass 25, count 0 2006.285.13:35:12.89#ibcon#wrote, iclass 25, count 0 2006.285.13:35:12.89#ibcon#about to read 3, iclass 25, count 0 2006.285.13:35:12.92#ibcon#read 3, iclass 25, count 0 2006.285.13:35:12.92#ibcon#about to read 4, iclass 25, count 0 2006.285.13:35:12.92#ibcon#read 4, iclass 25, count 0 2006.285.13:35:12.93#ibcon#about to read 5, iclass 25, count 0 2006.285.13:35:12.93#ibcon#read 5, iclass 25, count 0 2006.285.13:35:12.93#ibcon#about to read 6, iclass 25, count 0 2006.285.13:35:12.93#ibcon#read 6, iclass 25, count 0 2006.285.13:35:12.93#ibcon#end of sib2, iclass 25, count 0 2006.285.13:35:12.93#ibcon#*after write, iclass 25, count 0 2006.285.13:35:12.93#ibcon#*before return 0, iclass 25, count 0 2006.285.13:35:12.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:35:12.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:35:12.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:35:12.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:35:12.93$vck44/va=8,3 2006.285.13:35:12.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.13:35:12.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.13:35:12.93#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:12.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:35:12.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:35:12.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:35:12.98#ibcon#enter wrdev, iclass 27, count 2 2006.285.13:35:12.98#ibcon#first serial, iclass 27, count 2 2006.285.13:35:12.99#ibcon#enter sib2, iclass 27, count 2 2006.285.13:35:12.99#ibcon#flushed, iclass 27, count 2 2006.285.13:35:12.99#ibcon#about to write, iclass 27, count 2 2006.285.13:35:12.99#ibcon#wrote, iclass 27, count 2 2006.285.13:35:12.99#ibcon#about to read 3, iclass 27, count 2 2006.285.13:35:13.00#ibcon#read 3, iclass 27, count 2 2006.285.13:35:13.01#ibcon#about to read 4, iclass 27, count 2 2006.285.13:35:13.01#ibcon#read 4, iclass 27, count 2 2006.285.13:35:13.01#ibcon#about to read 5, iclass 27, count 2 2006.285.13:35:13.01#ibcon#read 5, iclass 27, count 2 2006.285.13:35:13.01#ibcon#about to read 6, iclass 27, count 2 2006.285.13:35:13.01#ibcon#read 6, iclass 27, count 2 2006.285.13:35:13.01#ibcon#end of sib2, iclass 27, count 2 2006.285.13:35:13.01#ibcon#*mode == 0, iclass 27, count 2 2006.285.13:35:13.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.13:35:13.01#ibcon#[25=AT08-03\r\n] 2006.285.13:35:13.01#ibcon#*before write, iclass 27, count 2 2006.285.13:35:13.01#ibcon#enter sib2, iclass 27, count 2 2006.285.13:35:13.01#ibcon#flushed, iclass 27, count 2 2006.285.13:35:13.01#ibcon#about to write, iclass 27, count 2 2006.285.13:35:13.01#ibcon#wrote, iclass 27, count 2 2006.285.13:35:13.01#ibcon#about to read 3, iclass 27, count 2 2006.285.13:35:13.03#ibcon#read 3, iclass 27, count 2 2006.285.13:35:13.04#ibcon#about to read 4, iclass 27, count 2 2006.285.13:35:13.04#ibcon#read 4, iclass 27, count 2 2006.285.13:35:13.04#ibcon#about to read 5, iclass 27, count 2 2006.285.13:35:13.04#ibcon#read 5, iclass 27, count 2 2006.285.13:35:13.04#ibcon#about to read 6, iclass 27, count 2 2006.285.13:35:13.04#ibcon#read 6, iclass 27, count 2 2006.285.13:35:13.04#ibcon#end of sib2, iclass 27, count 2 2006.285.13:35:13.04#ibcon#*after write, iclass 27, count 2 2006.285.13:35:13.04#ibcon#*before return 0, iclass 27, count 2 2006.285.13:35:13.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:35:13.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:35:13.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.13:35:13.04#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:13.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:35:13.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:35:13.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:35:13.15#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:35:13.16#ibcon#first serial, iclass 27, count 0 2006.285.13:35:13.16#ibcon#enter sib2, iclass 27, count 0 2006.285.13:35:13.16#ibcon#flushed, iclass 27, count 0 2006.285.13:35:13.16#ibcon#about to write, iclass 27, count 0 2006.285.13:35:13.16#ibcon#wrote, iclass 27, count 0 2006.285.13:35:13.16#ibcon#about to read 3, iclass 27, count 0 2006.285.13:35:13.17#ibcon#read 3, iclass 27, count 0 2006.285.13:35:13.17#ibcon#about to read 4, iclass 27, count 0 2006.285.13:35:13.17#ibcon#read 4, iclass 27, count 0 2006.285.13:35:13.18#ibcon#about to read 5, iclass 27, count 0 2006.285.13:35:13.18#ibcon#read 5, iclass 27, count 0 2006.285.13:35:13.18#ibcon#about to read 6, iclass 27, count 0 2006.285.13:35:13.18#ibcon#read 6, iclass 27, count 0 2006.285.13:35:13.18#ibcon#end of sib2, iclass 27, count 0 2006.285.13:35:13.18#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:35:13.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:35:13.18#ibcon#[25=USB\r\n] 2006.285.13:35:13.18#ibcon#*before write, iclass 27, count 0 2006.285.13:35:13.18#ibcon#enter sib2, iclass 27, count 0 2006.285.13:35:13.18#ibcon#flushed, iclass 27, count 0 2006.285.13:35:13.18#ibcon#about to write, iclass 27, count 0 2006.285.13:35:13.18#ibcon#wrote, iclass 27, count 0 2006.285.13:35:13.18#ibcon#about to read 3, iclass 27, count 0 2006.285.13:35:13.20#ibcon#read 3, iclass 27, count 0 2006.285.13:35:13.20#ibcon#about to read 4, iclass 27, count 0 2006.285.13:35:13.30#ibcon#read 4, iclass 27, count 0 2006.285.13:35:13.30#ibcon#about to read 5, iclass 27, count 0 2006.285.13:35:13.30#ibcon#read 5, iclass 27, count 0 2006.285.13:35:13.30#ibcon#about to read 6, iclass 27, count 0 2006.285.13:35:13.30#ibcon#read 6, iclass 27, count 0 2006.285.13:35:13.30#ibcon#end of sib2, iclass 27, count 0 2006.285.13:35:13.30#ibcon#*after write, iclass 27, count 0 2006.285.13:35:13.30#ibcon#*before return 0, iclass 27, count 0 2006.285.13:35:13.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:35:13.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:35:13.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:35:13.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:35:13.30$vck44/vblo=1,629.99 2006.285.13:35:13.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.13:35:13.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.13:35:13.30#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:13.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:35:13.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:35:13.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:35:13.30#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:35:13.30#ibcon#first serial, iclass 29, count 0 2006.285.13:35:13.30#ibcon#enter sib2, iclass 29, count 0 2006.285.13:35:13.30#ibcon#flushed, iclass 29, count 0 2006.285.13:35:13.30#ibcon#about to write, iclass 29, count 0 2006.285.13:35:13.30#ibcon#wrote, iclass 29, count 0 2006.285.13:35:13.30#ibcon#about to read 3, iclass 29, count 0 2006.285.13:35:13.31#ibcon#read 3, iclass 29, count 0 2006.285.13:35:13.31#ibcon#about to read 4, iclass 29, count 0 2006.285.13:35:13.32#ibcon#read 4, iclass 29, count 0 2006.285.13:35:13.32#ibcon#about to read 5, iclass 29, count 0 2006.285.13:35:13.32#ibcon#read 5, iclass 29, count 0 2006.285.13:35:13.32#ibcon#about to read 6, iclass 29, count 0 2006.285.13:35:13.32#ibcon#read 6, iclass 29, count 0 2006.285.13:35:13.32#ibcon#end of sib2, iclass 29, count 0 2006.285.13:35:13.32#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:35:13.32#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:35:13.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:35:13.32#ibcon#*before write, iclass 29, count 0 2006.285.13:35:13.32#ibcon#enter sib2, iclass 29, count 0 2006.285.13:35:13.32#ibcon#flushed, iclass 29, count 0 2006.285.13:35:13.32#ibcon#about to write, iclass 29, count 0 2006.285.13:35:13.32#ibcon#wrote, iclass 29, count 0 2006.285.13:35:13.32#ibcon#about to read 3, iclass 29, count 0 2006.285.13:35:13.34#abcon#<5=/04 1.4 2.4 19.12 971015.3\r\n> 2006.285.13:35:13.35#ibcon#read 3, iclass 29, count 0 2006.285.13:35:13.35#ibcon#about to read 4, iclass 29, count 0 2006.285.13:35:13.36#ibcon#read 4, iclass 29, count 0 2006.285.13:35:13.36#ibcon#about to read 5, iclass 29, count 0 2006.285.13:35:13.36#ibcon#read 5, iclass 29, count 0 2006.285.13:35:13.36#ibcon#about to read 6, iclass 29, count 0 2006.285.13:35:13.36#ibcon#read 6, iclass 29, count 0 2006.285.13:35:13.36#ibcon#end of sib2, iclass 29, count 0 2006.285.13:35:13.36#ibcon#*after write, iclass 29, count 0 2006.285.13:35:13.36#ibcon#*before return 0, iclass 29, count 0 2006.285.13:35:13.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:35:13.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:35:13.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:35:13.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:35:13.36$vck44/vb=1,4 2006.285.13:35:13.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.13:35:13.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.13:35:13.36#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:13.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:35:13.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:35:13.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:35:13.36#ibcon#enter wrdev, iclass 34, count 2 2006.285.13:35:13.36#ibcon#first serial, iclass 34, count 2 2006.285.13:35:13.36#ibcon#enter sib2, iclass 34, count 2 2006.285.13:35:13.36#ibcon#flushed, iclass 34, count 2 2006.285.13:35:13.36#ibcon#about to write, iclass 34, count 2 2006.285.13:35:13.36#ibcon#wrote, iclass 34, count 2 2006.285.13:35:13.36#ibcon#about to read 3, iclass 34, count 2 2006.285.13:35:13.36#abcon#{5=INTERFACE CLEAR} 2006.285.13:35:13.37#ibcon#read 3, iclass 34, count 2 2006.285.13:35:13.37#ibcon#about to read 4, iclass 34, count 2 2006.285.13:35:13.38#ibcon#read 4, iclass 34, count 2 2006.285.13:35:13.38#ibcon#about to read 5, iclass 34, count 2 2006.285.13:35:13.38#ibcon#read 5, iclass 34, count 2 2006.285.13:35:13.38#ibcon#about to read 6, iclass 34, count 2 2006.285.13:35:13.38#ibcon#read 6, iclass 34, count 2 2006.285.13:35:13.38#ibcon#end of sib2, iclass 34, count 2 2006.285.13:35:13.38#ibcon#*mode == 0, iclass 34, count 2 2006.285.13:35:13.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.13:35:13.38#ibcon#[27=AT01-04\r\n] 2006.285.13:35:13.38#ibcon#*before write, iclass 34, count 2 2006.285.13:35:13.38#ibcon#enter sib2, iclass 34, count 2 2006.285.13:35:13.38#ibcon#flushed, iclass 34, count 2 2006.285.13:35:13.38#ibcon#about to write, iclass 34, count 2 2006.285.13:35:13.38#ibcon#wrote, iclass 34, count 2 2006.285.13:35:13.38#ibcon#about to read 3, iclass 34, count 2 2006.285.13:35:13.40#ibcon#read 3, iclass 34, count 2 2006.285.13:35:13.40#ibcon#about to read 4, iclass 34, count 2 2006.285.13:35:13.41#ibcon#read 4, iclass 34, count 2 2006.285.13:35:13.41#ibcon#about to read 5, iclass 34, count 2 2006.285.13:35:13.41#ibcon#read 5, iclass 34, count 2 2006.285.13:35:13.41#ibcon#about to read 6, iclass 34, count 2 2006.285.13:35:13.41#ibcon#read 6, iclass 34, count 2 2006.285.13:35:13.41#ibcon#end of sib2, iclass 34, count 2 2006.285.13:35:13.41#ibcon#*after write, iclass 34, count 2 2006.285.13:35:13.41#ibcon#*before return 0, iclass 34, count 2 2006.285.13:35:13.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:35:13.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:35:13.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.13:35:13.41#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:13.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:35:13.42#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:35:13.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:35:13.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:35:13.52#ibcon#enter wrdev, iclass 34, count 0 2006.285.13:35:13.53#ibcon#first serial, iclass 34, count 0 2006.285.13:35:13.53#ibcon#enter sib2, iclass 34, count 0 2006.285.13:35:13.53#ibcon#flushed, iclass 34, count 0 2006.285.13:35:13.53#ibcon#about to write, iclass 34, count 0 2006.285.13:35:13.53#ibcon#wrote, iclass 34, count 0 2006.285.13:35:13.53#ibcon#about to read 3, iclass 34, count 0 2006.285.13:35:13.54#ibcon#read 3, iclass 34, count 0 2006.285.13:35:13.54#ibcon#about to read 4, iclass 34, count 0 2006.285.13:35:13.54#ibcon#read 4, iclass 34, count 0 2006.285.13:35:13.55#ibcon#about to read 5, iclass 34, count 0 2006.285.13:35:13.55#ibcon#read 5, iclass 34, count 0 2006.285.13:35:13.55#ibcon#about to read 6, iclass 34, count 0 2006.285.13:35:13.55#ibcon#read 6, iclass 34, count 0 2006.285.13:35:13.55#ibcon#end of sib2, iclass 34, count 0 2006.285.13:35:13.55#ibcon#*mode == 0, iclass 34, count 0 2006.285.13:35:13.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.13:35:13.55#ibcon#[27=USB\r\n] 2006.285.13:35:13.55#ibcon#*before write, iclass 34, count 0 2006.285.13:35:13.55#ibcon#enter sib2, iclass 34, count 0 2006.285.13:35:13.55#ibcon#flushed, iclass 34, count 0 2006.285.13:35:13.55#ibcon#about to write, iclass 34, count 0 2006.285.13:35:13.55#ibcon#wrote, iclass 34, count 0 2006.285.13:35:13.55#ibcon#about to read 3, iclass 34, count 0 2006.285.13:35:13.57#ibcon#read 3, iclass 34, count 0 2006.285.13:35:13.57#ibcon#about to read 4, iclass 34, count 0 2006.285.13:35:13.57#ibcon#read 4, iclass 34, count 0 2006.285.13:35:13.58#ibcon#about to read 5, iclass 34, count 0 2006.285.13:35:13.58#ibcon#read 5, iclass 34, count 0 2006.285.13:35:13.58#ibcon#about to read 6, iclass 34, count 0 2006.285.13:35:13.58#ibcon#read 6, iclass 34, count 0 2006.285.13:35:13.58#ibcon#end of sib2, iclass 34, count 0 2006.285.13:35:13.58#ibcon#*after write, iclass 34, count 0 2006.285.13:35:13.58#ibcon#*before return 0, iclass 34, count 0 2006.285.13:35:13.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:35:13.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:35:13.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.13:35:13.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.13:35:13.58$vck44/vblo=2,634.99 2006.285.13:35:13.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.13:35:13.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.13:35:13.58#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:13.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:35:13.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:35:13.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:35:13.58#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:35:13.58#ibcon#first serial, iclass 37, count 0 2006.285.13:35:13.58#ibcon#enter sib2, iclass 37, count 0 2006.285.13:35:13.58#ibcon#flushed, iclass 37, count 0 2006.285.13:35:13.58#ibcon#about to write, iclass 37, count 0 2006.285.13:35:13.58#ibcon#wrote, iclass 37, count 0 2006.285.13:35:13.58#ibcon#about to read 3, iclass 37, count 0 2006.285.13:35:13.59#ibcon#read 3, iclass 37, count 0 2006.285.13:35:13.59#ibcon#about to read 4, iclass 37, count 0 2006.285.13:35:13.59#ibcon#read 4, iclass 37, count 0 2006.285.13:35:13.60#ibcon#about to read 5, iclass 37, count 0 2006.285.13:35:13.60#ibcon#read 5, iclass 37, count 0 2006.285.13:35:13.60#ibcon#about to read 6, iclass 37, count 0 2006.285.13:35:13.60#ibcon#read 6, iclass 37, count 0 2006.285.13:35:13.60#ibcon#end of sib2, iclass 37, count 0 2006.285.13:35:13.60#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:35:13.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:35:13.60#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:35:13.60#ibcon#*before write, iclass 37, count 0 2006.285.13:35:13.60#ibcon#enter sib2, iclass 37, count 0 2006.285.13:35:13.60#ibcon#flushed, iclass 37, count 0 2006.285.13:35:13.60#ibcon#about to write, iclass 37, count 0 2006.285.13:35:13.60#ibcon#wrote, iclass 37, count 0 2006.285.13:35:13.60#ibcon#about to read 3, iclass 37, count 0 2006.285.13:35:13.63#ibcon#read 3, iclass 37, count 0 2006.285.13:35:13.63#ibcon#about to read 4, iclass 37, count 0 2006.285.13:35:13.63#ibcon#read 4, iclass 37, count 0 2006.285.13:35:13.63#ibcon#about to read 5, iclass 37, count 0 2006.285.13:35:13.64#ibcon#read 5, iclass 37, count 0 2006.285.13:35:13.64#ibcon#about to read 6, iclass 37, count 0 2006.285.13:35:13.64#ibcon#read 6, iclass 37, count 0 2006.285.13:35:13.64#ibcon#end of sib2, iclass 37, count 0 2006.285.13:35:13.64#ibcon#*after write, iclass 37, count 0 2006.285.13:35:13.64#ibcon#*before return 0, iclass 37, count 0 2006.285.13:35:13.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:35:13.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:35:13.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:35:13.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:35:13.64$vck44/vb=2,5 2006.285.13:35:13.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.13:35:13.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.13:35:13.64#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:13.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:35:13.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:35:13.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:35:13.69#ibcon#enter wrdev, iclass 39, count 2 2006.285.13:35:13.69#ibcon#first serial, iclass 39, count 2 2006.285.13:35:13.70#ibcon#enter sib2, iclass 39, count 2 2006.285.13:35:13.70#ibcon#flushed, iclass 39, count 2 2006.285.13:35:13.70#ibcon#about to write, iclass 39, count 2 2006.285.13:35:13.70#ibcon#wrote, iclass 39, count 2 2006.285.13:35:13.70#ibcon#about to read 3, iclass 39, count 2 2006.285.13:35:13.71#ibcon#read 3, iclass 39, count 2 2006.285.13:35:13.71#ibcon#about to read 4, iclass 39, count 2 2006.285.13:35:13.71#ibcon#read 4, iclass 39, count 2 2006.285.13:35:13.71#ibcon#about to read 5, iclass 39, count 2 2006.285.13:35:13.72#ibcon#read 5, iclass 39, count 2 2006.285.13:35:13.72#ibcon#about to read 6, iclass 39, count 2 2006.285.13:35:13.72#ibcon#read 6, iclass 39, count 2 2006.285.13:35:13.72#ibcon#end of sib2, iclass 39, count 2 2006.285.13:35:13.72#ibcon#*mode == 0, iclass 39, count 2 2006.285.13:35:13.72#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.13:35:13.72#ibcon#[27=AT02-05\r\n] 2006.285.13:35:13.72#ibcon#*before write, iclass 39, count 2 2006.285.13:35:13.72#ibcon#enter sib2, iclass 39, count 2 2006.285.13:35:13.72#ibcon#flushed, iclass 39, count 2 2006.285.13:35:13.72#ibcon#about to write, iclass 39, count 2 2006.285.13:35:13.72#ibcon#wrote, iclass 39, count 2 2006.285.13:35:13.72#ibcon#about to read 3, iclass 39, count 2 2006.285.13:35:13.74#ibcon#read 3, iclass 39, count 2 2006.285.13:35:13.74#ibcon#about to read 4, iclass 39, count 2 2006.285.13:35:13.74#ibcon#read 4, iclass 39, count 2 2006.285.13:35:13.75#ibcon#about to read 5, iclass 39, count 2 2006.285.13:35:13.75#ibcon#read 5, iclass 39, count 2 2006.285.13:35:13.75#ibcon#about to read 6, iclass 39, count 2 2006.285.13:35:13.75#ibcon#read 6, iclass 39, count 2 2006.285.13:35:13.75#ibcon#end of sib2, iclass 39, count 2 2006.285.13:35:13.75#ibcon#*after write, iclass 39, count 2 2006.285.13:35:13.75#ibcon#*before return 0, iclass 39, count 2 2006.285.13:35:13.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:35:13.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:35:13.75#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.13:35:13.75#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:13.75#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:35:13.86#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:35:13.86#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:35:13.86#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:35:13.86#ibcon#first serial, iclass 39, count 0 2006.285.13:35:13.87#ibcon#enter sib2, iclass 39, count 0 2006.285.13:35:13.87#ibcon#flushed, iclass 39, count 0 2006.285.13:35:13.87#ibcon#about to write, iclass 39, count 0 2006.285.13:35:13.87#ibcon#wrote, iclass 39, count 0 2006.285.13:35:13.87#ibcon#about to read 3, iclass 39, count 0 2006.285.13:35:13.88#ibcon#read 3, iclass 39, count 0 2006.285.13:35:13.88#ibcon#about to read 4, iclass 39, count 0 2006.285.13:35:13.88#ibcon#read 4, iclass 39, count 0 2006.285.13:35:13.88#ibcon#about to read 5, iclass 39, count 0 2006.285.13:35:13.89#ibcon#read 5, iclass 39, count 0 2006.285.13:35:13.89#ibcon#about to read 6, iclass 39, count 0 2006.285.13:35:13.89#ibcon#read 6, iclass 39, count 0 2006.285.13:35:13.89#ibcon#end of sib2, iclass 39, count 0 2006.285.13:35:13.89#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:35:13.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:35:13.89#ibcon#[27=USB\r\n] 2006.285.13:35:13.89#ibcon#*before write, iclass 39, count 0 2006.285.13:35:13.89#ibcon#enter sib2, iclass 39, count 0 2006.285.13:35:13.89#ibcon#flushed, iclass 39, count 0 2006.285.13:35:13.89#ibcon#about to write, iclass 39, count 0 2006.285.13:35:13.89#ibcon#wrote, iclass 39, count 0 2006.285.13:35:13.89#ibcon#about to read 3, iclass 39, count 0 2006.285.13:35:13.91#ibcon#read 3, iclass 39, count 0 2006.285.13:35:13.91#ibcon#about to read 4, iclass 39, count 0 2006.285.13:35:13.91#ibcon#read 4, iclass 39, count 0 2006.285.13:35:13.91#ibcon#about to read 5, iclass 39, count 0 2006.285.13:35:13.92#ibcon#read 5, iclass 39, count 0 2006.285.13:35:13.92#ibcon#about to read 6, iclass 39, count 0 2006.285.13:35:13.92#ibcon#read 6, iclass 39, count 0 2006.285.13:35:13.92#ibcon#end of sib2, iclass 39, count 0 2006.285.13:35:13.92#ibcon#*after write, iclass 39, count 0 2006.285.13:35:13.92#ibcon#*before return 0, iclass 39, count 0 2006.285.13:35:13.92#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:35:13.92#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:35:13.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:35:13.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:35:13.92$vck44/vblo=3,649.99 2006.285.13:35:13.92#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.13:35:13.92#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.13:35:13.92#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:13.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:35:13.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:35:13.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:35:13.92#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:35:13.92#ibcon#first serial, iclass 3, count 0 2006.285.13:35:13.92#ibcon#enter sib2, iclass 3, count 0 2006.285.13:35:13.92#ibcon#flushed, iclass 3, count 0 2006.285.13:35:13.92#ibcon#about to write, iclass 3, count 0 2006.285.13:35:13.92#ibcon#wrote, iclass 3, count 0 2006.285.13:35:13.92#ibcon#about to read 3, iclass 3, count 0 2006.285.13:35:13.93#ibcon#read 3, iclass 3, count 0 2006.285.13:35:13.93#ibcon#about to read 4, iclass 3, count 0 2006.285.13:35:13.93#ibcon#read 4, iclass 3, count 0 2006.285.13:35:13.94#ibcon#about to read 5, iclass 3, count 0 2006.285.13:35:13.94#ibcon#read 5, iclass 3, count 0 2006.285.13:35:13.94#ibcon#about to read 6, iclass 3, count 0 2006.285.13:35:13.94#ibcon#read 6, iclass 3, count 0 2006.285.13:35:13.94#ibcon#end of sib2, iclass 3, count 0 2006.285.13:35:13.94#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:35:13.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:35:13.94#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:35:13.94#ibcon#*before write, iclass 3, count 0 2006.285.13:35:13.94#ibcon#enter sib2, iclass 3, count 0 2006.285.13:35:13.94#ibcon#flushed, iclass 3, count 0 2006.285.13:35:13.94#ibcon#about to write, iclass 3, count 0 2006.285.13:35:13.94#ibcon#wrote, iclass 3, count 0 2006.285.13:35:13.94#ibcon#about to read 3, iclass 3, count 0 2006.285.13:35:13.97#ibcon#read 3, iclass 3, count 0 2006.285.13:35:13.97#ibcon#about to read 4, iclass 3, count 0 2006.285.13:35:13.97#ibcon#read 4, iclass 3, count 0 2006.285.13:35:13.97#ibcon#about to read 5, iclass 3, count 0 2006.285.13:35:13.98#ibcon#read 5, iclass 3, count 0 2006.285.13:35:13.98#ibcon#about to read 6, iclass 3, count 0 2006.285.13:35:13.98#ibcon#read 6, iclass 3, count 0 2006.285.13:35:13.98#ibcon#end of sib2, iclass 3, count 0 2006.285.13:35:13.98#ibcon#*after write, iclass 3, count 0 2006.285.13:35:13.98#ibcon#*before return 0, iclass 3, count 0 2006.285.13:35:13.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:35:13.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:35:13.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:35:13.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:35:13.98$vck44/vb=3,4 2006.285.13:35:13.98#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.13:35:13.98#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.13:35:13.98#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:13.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:35:14.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:35:14.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:35:14.04#ibcon#enter wrdev, iclass 5, count 2 2006.285.13:35:14.04#ibcon#first serial, iclass 5, count 2 2006.285.13:35:14.04#ibcon#enter sib2, iclass 5, count 2 2006.285.13:35:14.04#ibcon#flushed, iclass 5, count 2 2006.285.13:35:14.04#ibcon#about to write, iclass 5, count 2 2006.285.13:35:14.04#ibcon#wrote, iclass 5, count 2 2006.285.13:35:14.04#ibcon#about to read 3, iclass 5, count 2 2006.285.13:35:14.05#ibcon#read 3, iclass 5, count 2 2006.285.13:35:14.05#ibcon#about to read 4, iclass 5, count 2 2006.285.13:35:14.05#ibcon#read 4, iclass 5, count 2 2006.285.13:35:14.05#ibcon#about to read 5, iclass 5, count 2 2006.285.13:35:14.06#ibcon#read 5, iclass 5, count 2 2006.285.13:35:14.06#ibcon#about to read 6, iclass 5, count 2 2006.285.13:35:14.06#ibcon#read 6, iclass 5, count 2 2006.285.13:35:14.06#ibcon#end of sib2, iclass 5, count 2 2006.285.13:35:14.06#ibcon#*mode == 0, iclass 5, count 2 2006.285.13:35:14.06#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.13:35:14.06#ibcon#[27=AT03-04\r\n] 2006.285.13:35:14.06#ibcon#*before write, iclass 5, count 2 2006.285.13:35:14.06#ibcon#enter sib2, iclass 5, count 2 2006.285.13:35:14.06#ibcon#flushed, iclass 5, count 2 2006.285.13:35:14.06#ibcon#about to write, iclass 5, count 2 2006.285.13:35:14.06#ibcon#wrote, iclass 5, count 2 2006.285.13:35:14.06#ibcon#about to read 3, iclass 5, count 2 2006.285.13:35:14.08#ibcon#read 3, iclass 5, count 2 2006.285.13:35:14.08#ibcon#about to read 4, iclass 5, count 2 2006.285.13:35:14.09#ibcon#read 4, iclass 5, count 2 2006.285.13:35:14.09#ibcon#about to read 5, iclass 5, count 2 2006.285.13:35:14.09#ibcon#read 5, iclass 5, count 2 2006.285.13:35:14.09#ibcon#about to read 6, iclass 5, count 2 2006.285.13:35:14.09#ibcon#read 6, iclass 5, count 2 2006.285.13:35:14.09#ibcon#end of sib2, iclass 5, count 2 2006.285.13:35:14.09#ibcon#*after write, iclass 5, count 2 2006.285.13:35:14.09#ibcon#*before return 0, iclass 5, count 2 2006.285.13:35:14.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:35:14.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:35:14.09#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.13:35:14.09#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:14.09#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:35:14.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:35:14.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:35:14.20#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:35:14.21#ibcon#first serial, iclass 5, count 0 2006.285.13:35:14.21#ibcon#enter sib2, iclass 5, count 0 2006.285.13:35:14.21#ibcon#flushed, iclass 5, count 0 2006.285.13:35:14.21#ibcon#about to write, iclass 5, count 0 2006.285.13:35:14.21#ibcon#wrote, iclass 5, count 0 2006.285.13:35:14.21#ibcon#about to read 3, iclass 5, count 0 2006.285.13:35:14.22#ibcon#read 3, iclass 5, count 0 2006.285.13:35:14.22#ibcon#about to read 4, iclass 5, count 0 2006.285.13:35:14.22#ibcon#read 4, iclass 5, count 0 2006.285.13:35:14.23#ibcon#about to read 5, iclass 5, count 0 2006.285.13:35:14.23#ibcon#read 5, iclass 5, count 0 2006.285.13:35:14.23#ibcon#about to read 6, iclass 5, count 0 2006.285.13:35:14.23#ibcon#read 6, iclass 5, count 0 2006.285.13:35:14.23#ibcon#end of sib2, iclass 5, count 0 2006.285.13:35:14.23#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:35:14.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:35:14.33#ibcon#[27=USB\r\n] 2006.285.13:35:14.33#ibcon#*before write, iclass 5, count 0 2006.285.13:35:14.33#ibcon#enter sib2, iclass 5, count 0 2006.285.13:35:14.33#ibcon#flushed, iclass 5, count 0 2006.285.13:35:14.33#ibcon#about to write, iclass 5, count 0 2006.285.13:35:14.33#ibcon#wrote, iclass 5, count 0 2006.285.13:35:14.33#ibcon#about to read 3, iclass 5, count 0 2006.285.13:35:14.36#ibcon#read 3, iclass 5, count 0 2006.285.13:35:14.36#ibcon#about to read 4, iclass 5, count 0 2006.285.13:35:14.37#ibcon#read 4, iclass 5, count 0 2006.285.13:35:14.37#ibcon#about to read 5, iclass 5, count 0 2006.285.13:35:14.37#ibcon#read 5, iclass 5, count 0 2006.285.13:35:14.37#ibcon#about to read 6, iclass 5, count 0 2006.285.13:35:14.37#ibcon#read 6, iclass 5, count 0 2006.285.13:35:14.37#ibcon#end of sib2, iclass 5, count 0 2006.285.13:35:14.37#ibcon#*after write, iclass 5, count 0 2006.285.13:35:14.37#ibcon#*before return 0, iclass 5, count 0 2006.285.13:35:14.37#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:35:14.37#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:35:14.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:35:14.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:35:14.37$vck44/vblo=4,679.99 2006.285.13:35:14.37#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.13:35:14.37#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.13:35:14.37#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:14.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:35:14.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:35:14.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:35:14.37#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:35:14.37#ibcon#first serial, iclass 7, count 0 2006.285.13:35:14.37#ibcon#enter sib2, iclass 7, count 0 2006.285.13:35:14.37#ibcon#flushed, iclass 7, count 0 2006.285.13:35:14.37#ibcon#about to write, iclass 7, count 0 2006.285.13:35:14.37#ibcon#wrote, iclass 7, count 0 2006.285.13:35:14.37#ibcon#about to read 3, iclass 7, count 0 2006.285.13:35:14.38#ibcon#read 3, iclass 7, count 0 2006.285.13:35:14.38#ibcon#about to read 4, iclass 7, count 0 2006.285.13:35:14.39#ibcon#read 4, iclass 7, count 0 2006.285.13:35:14.39#ibcon#about to read 5, iclass 7, count 0 2006.285.13:35:14.39#ibcon#read 5, iclass 7, count 0 2006.285.13:35:14.39#ibcon#about to read 6, iclass 7, count 0 2006.285.13:35:14.39#ibcon#read 6, iclass 7, count 0 2006.285.13:35:14.39#ibcon#end of sib2, iclass 7, count 0 2006.285.13:35:14.39#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:35:14.39#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:35:14.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:35:14.39#ibcon#*before write, iclass 7, count 0 2006.285.13:35:14.39#ibcon#enter sib2, iclass 7, count 0 2006.285.13:35:14.39#ibcon#flushed, iclass 7, count 0 2006.285.13:35:14.39#ibcon#about to write, iclass 7, count 0 2006.285.13:35:14.39#ibcon#wrote, iclass 7, count 0 2006.285.13:35:14.39#ibcon#about to read 3, iclass 7, count 0 2006.285.13:35:14.42#ibcon#read 3, iclass 7, count 0 2006.285.13:35:14.42#ibcon#about to read 4, iclass 7, count 0 2006.285.13:35:14.43#ibcon#read 4, iclass 7, count 0 2006.285.13:35:14.43#ibcon#about to read 5, iclass 7, count 0 2006.285.13:35:14.43#ibcon#read 5, iclass 7, count 0 2006.285.13:35:14.43#ibcon#about to read 6, iclass 7, count 0 2006.285.13:35:14.43#ibcon#read 6, iclass 7, count 0 2006.285.13:35:14.43#ibcon#end of sib2, iclass 7, count 0 2006.285.13:35:14.43#ibcon#*after write, iclass 7, count 0 2006.285.13:35:14.43#ibcon#*before return 0, iclass 7, count 0 2006.285.13:35:14.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:35:14.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:35:14.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:35:14.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:35:14.43$vck44/vb=4,5 2006.285.13:35:14.43#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.13:35:14.43#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.13:35:14.43#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:14.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:35:14.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:35:14.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:35:14.48#ibcon#enter wrdev, iclass 11, count 2 2006.285.13:35:14.49#ibcon#first serial, iclass 11, count 2 2006.285.13:35:14.49#ibcon#enter sib2, iclass 11, count 2 2006.285.13:35:14.49#ibcon#flushed, iclass 11, count 2 2006.285.13:35:14.49#ibcon#about to write, iclass 11, count 2 2006.285.13:35:14.49#ibcon#wrote, iclass 11, count 2 2006.285.13:35:14.49#ibcon#about to read 3, iclass 11, count 2 2006.285.13:35:14.50#ibcon#read 3, iclass 11, count 2 2006.285.13:35:14.50#ibcon#about to read 4, iclass 11, count 2 2006.285.13:35:14.51#ibcon#read 4, iclass 11, count 2 2006.285.13:35:14.51#ibcon#about to read 5, iclass 11, count 2 2006.285.13:35:14.51#ibcon#read 5, iclass 11, count 2 2006.285.13:35:14.51#ibcon#about to read 6, iclass 11, count 2 2006.285.13:35:14.51#ibcon#read 6, iclass 11, count 2 2006.285.13:35:14.51#ibcon#end of sib2, iclass 11, count 2 2006.285.13:35:14.51#ibcon#*mode == 0, iclass 11, count 2 2006.285.13:35:14.51#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.13:35:14.51#ibcon#[27=AT04-05\r\n] 2006.285.13:35:14.51#ibcon#*before write, iclass 11, count 2 2006.285.13:35:14.51#ibcon#enter sib2, iclass 11, count 2 2006.285.13:35:14.51#ibcon#flushed, iclass 11, count 2 2006.285.13:35:14.51#ibcon#about to write, iclass 11, count 2 2006.285.13:35:14.51#ibcon#wrote, iclass 11, count 2 2006.285.13:35:14.51#ibcon#about to read 3, iclass 11, count 2 2006.285.13:35:14.53#ibcon#read 3, iclass 11, count 2 2006.285.13:35:14.53#ibcon#about to read 4, iclass 11, count 2 2006.285.13:35:14.54#ibcon#read 4, iclass 11, count 2 2006.285.13:35:14.54#ibcon#about to read 5, iclass 11, count 2 2006.285.13:35:14.54#ibcon#read 5, iclass 11, count 2 2006.285.13:35:14.54#ibcon#about to read 6, iclass 11, count 2 2006.285.13:35:14.54#ibcon#read 6, iclass 11, count 2 2006.285.13:35:14.54#ibcon#end of sib2, iclass 11, count 2 2006.285.13:35:14.54#ibcon#*after write, iclass 11, count 2 2006.285.13:35:14.54#ibcon#*before return 0, iclass 11, count 2 2006.285.13:35:14.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:35:14.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:35:14.54#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.13:35:14.54#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:14.54#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:35:14.65#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:35:14.65#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:35:14.65#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:35:14.66#ibcon#first serial, iclass 11, count 0 2006.285.13:35:14.66#ibcon#enter sib2, iclass 11, count 0 2006.285.13:35:14.66#ibcon#flushed, iclass 11, count 0 2006.285.13:35:14.66#ibcon#about to write, iclass 11, count 0 2006.285.13:35:14.66#ibcon#wrote, iclass 11, count 0 2006.285.13:35:14.66#ibcon#about to read 3, iclass 11, count 0 2006.285.13:35:14.67#ibcon#read 3, iclass 11, count 0 2006.285.13:35:14.67#ibcon#about to read 4, iclass 11, count 0 2006.285.13:35:14.67#ibcon#read 4, iclass 11, count 0 2006.285.13:35:14.67#ibcon#about to read 5, iclass 11, count 0 2006.285.13:35:14.68#ibcon#read 5, iclass 11, count 0 2006.285.13:35:14.68#ibcon#about to read 6, iclass 11, count 0 2006.285.13:35:14.68#ibcon#read 6, iclass 11, count 0 2006.285.13:35:14.68#ibcon#end of sib2, iclass 11, count 0 2006.285.13:35:14.68#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:35:14.68#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:35:14.68#ibcon#[27=USB\r\n] 2006.285.13:35:14.68#ibcon#*before write, iclass 11, count 0 2006.285.13:35:14.68#ibcon#enter sib2, iclass 11, count 0 2006.285.13:35:14.68#ibcon#flushed, iclass 11, count 0 2006.285.13:35:14.68#ibcon#about to write, iclass 11, count 0 2006.285.13:35:14.68#ibcon#wrote, iclass 11, count 0 2006.285.13:35:14.68#ibcon#about to read 3, iclass 11, count 0 2006.285.13:35:14.70#ibcon#read 3, iclass 11, count 0 2006.285.13:35:14.70#ibcon#about to read 4, iclass 11, count 0 2006.285.13:35:14.70#ibcon#read 4, iclass 11, count 0 2006.285.13:35:14.70#ibcon#about to read 5, iclass 11, count 0 2006.285.13:35:14.71#ibcon#read 5, iclass 11, count 0 2006.285.13:35:14.71#ibcon#about to read 6, iclass 11, count 0 2006.285.13:35:14.71#ibcon#read 6, iclass 11, count 0 2006.285.13:35:14.71#ibcon#end of sib2, iclass 11, count 0 2006.285.13:35:14.71#ibcon#*after write, iclass 11, count 0 2006.285.13:35:14.71#ibcon#*before return 0, iclass 11, count 0 2006.285.13:35:14.71#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:35:14.71#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:35:14.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:35:14.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:35:14.71$vck44/vblo=5,709.99 2006.285.13:35:14.71#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.13:35:14.71#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.13:35:14.71#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:14.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:35:14.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:35:14.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:35:14.71#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:35:14.71#ibcon#first serial, iclass 13, count 0 2006.285.13:35:14.71#ibcon#enter sib2, iclass 13, count 0 2006.285.13:35:14.71#ibcon#flushed, iclass 13, count 0 2006.285.13:35:14.71#ibcon#about to write, iclass 13, count 0 2006.285.13:35:14.71#ibcon#wrote, iclass 13, count 0 2006.285.13:35:14.71#ibcon#about to read 3, iclass 13, count 0 2006.285.13:35:14.72#ibcon#read 3, iclass 13, count 0 2006.285.13:35:14.72#ibcon#about to read 4, iclass 13, count 0 2006.285.13:35:14.72#ibcon#read 4, iclass 13, count 0 2006.285.13:35:14.73#ibcon#about to read 5, iclass 13, count 0 2006.285.13:35:14.73#ibcon#read 5, iclass 13, count 0 2006.285.13:35:14.73#ibcon#about to read 6, iclass 13, count 0 2006.285.13:35:14.73#ibcon#read 6, iclass 13, count 0 2006.285.13:35:14.73#ibcon#end of sib2, iclass 13, count 0 2006.285.13:35:14.73#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:35:14.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:35:14.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:35:14.73#ibcon#*before write, iclass 13, count 0 2006.285.13:35:14.73#ibcon#enter sib2, iclass 13, count 0 2006.285.13:35:14.73#ibcon#flushed, iclass 13, count 0 2006.285.13:35:14.73#ibcon#about to write, iclass 13, count 0 2006.285.13:35:14.73#ibcon#wrote, iclass 13, count 0 2006.285.13:35:14.73#ibcon#about to read 3, iclass 13, count 0 2006.285.13:35:14.76#ibcon#read 3, iclass 13, count 0 2006.285.13:35:14.76#ibcon#about to read 4, iclass 13, count 0 2006.285.13:35:14.76#ibcon#read 4, iclass 13, count 0 2006.285.13:35:14.76#ibcon#about to read 5, iclass 13, count 0 2006.285.13:35:14.77#ibcon#read 5, iclass 13, count 0 2006.285.13:35:14.77#ibcon#about to read 6, iclass 13, count 0 2006.285.13:35:14.77#ibcon#read 6, iclass 13, count 0 2006.285.13:35:14.77#ibcon#end of sib2, iclass 13, count 0 2006.285.13:35:14.77#ibcon#*after write, iclass 13, count 0 2006.285.13:35:14.77#ibcon#*before return 0, iclass 13, count 0 2006.285.13:35:14.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:35:14.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:35:14.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:35:14.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:35:14.77$vck44/vb=5,4 2006.285.13:35:14.77#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.13:35:14.77#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.13:35:14.77#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:14.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:35:14.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:35:14.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:35:14.82#ibcon#enter wrdev, iclass 15, count 2 2006.285.13:35:14.82#ibcon#first serial, iclass 15, count 2 2006.285.13:35:14.83#ibcon#enter sib2, iclass 15, count 2 2006.285.13:35:14.83#ibcon#flushed, iclass 15, count 2 2006.285.13:35:14.83#ibcon#about to write, iclass 15, count 2 2006.285.13:35:14.83#ibcon#wrote, iclass 15, count 2 2006.285.13:35:14.83#ibcon#about to read 3, iclass 15, count 2 2006.285.13:35:14.84#ibcon#read 3, iclass 15, count 2 2006.285.13:35:14.84#ibcon#about to read 4, iclass 15, count 2 2006.285.13:35:14.84#ibcon#read 4, iclass 15, count 2 2006.285.13:35:14.84#ibcon#about to read 5, iclass 15, count 2 2006.285.13:35:14.85#ibcon#read 5, iclass 15, count 2 2006.285.13:35:14.85#ibcon#about to read 6, iclass 15, count 2 2006.285.13:35:14.85#ibcon#read 6, iclass 15, count 2 2006.285.13:35:14.85#ibcon#end of sib2, iclass 15, count 2 2006.285.13:35:14.85#ibcon#*mode == 0, iclass 15, count 2 2006.285.13:35:14.85#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.13:35:14.85#ibcon#[27=AT05-04\r\n] 2006.285.13:35:14.85#ibcon#*before write, iclass 15, count 2 2006.285.13:35:14.85#ibcon#enter sib2, iclass 15, count 2 2006.285.13:35:14.85#ibcon#flushed, iclass 15, count 2 2006.285.13:35:14.85#ibcon#about to write, iclass 15, count 2 2006.285.13:35:14.85#ibcon#wrote, iclass 15, count 2 2006.285.13:35:14.85#ibcon#about to read 3, iclass 15, count 2 2006.285.13:35:14.87#ibcon#read 3, iclass 15, count 2 2006.285.13:35:14.87#ibcon#about to read 4, iclass 15, count 2 2006.285.13:35:14.87#ibcon#read 4, iclass 15, count 2 2006.285.13:35:14.88#ibcon#about to read 5, iclass 15, count 2 2006.285.13:35:14.88#ibcon#read 5, iclass 15, count 2 2006.285.13:35:14.88#ibcon#about to read 6, iclass 15, count 2 2006.285.13:35:14.88#ibcon#read 6, iclass 15, count 2 2006.285.13:35:14.88#ibcon#end of sib2, iclass 15, count 2 2006.285.13:35:14.88#ibcon#*after write, iclass 15, count 2 2006.285.13:35:14.88#ibcon#*before return 0, iclass 15, count 2 2006.285.13:35:14.88#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:35:14.88#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:35:14.88#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.13:35:14.88#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:14.88#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:35:14.99#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:35:14.99#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:35:14.99#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:35:15.00#ibcon#first serial, iclass 15, count 0 2006.285.13:35:15.00#ibcon#enter sib2, iclass 15, count 0 2006.285.13:35:15.00#ibcon#flushed, iclass 15, count 0 2006.285.13:35:15.00#ibcon#about to write, iclass 15, count 0 2006.285.13:35:15.00#ibcon#wrote, iclass 15, count 0 2006.285.13:35:15.00#ibcon#about to read 3, iclass 15, count 0 2006.285.13:35:15.01#ibcon#read 3, iclass 15, count 0 2006.285.13:35:15.01#ibcon#about to read 4, iclass 15, count 0 2006.285.13:35:15.01#ibcon#read 4, iclass 15, count 0 2006.285.13:35:15.02#ibcon#about to read 5, iclass 15, count 0 2006.285.13:35:15.02#ibcon#read 5, iclass 15, count 0 2006.285.13:35:15.02#ibcon#about to read 6, iclass 15, count 0 2006.285.13:35:15.02#ibcon#read 6, iclass 15, count 0 2006.285.13:35:15.02#ibcon#end of sib2, iclass 15, count 0 2006.285.13:35:15.02#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:35:15.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:35:15.02#ibcon#[27=USB\r\n] 2006.285.13:35:15.02#ibcon#*before write, iclass 15, count 0 2006.285.13:35:15.02#ibcon#enter sib2, iclass 15, count 0 2006.285.13:35:15.02#ibcon#flushed, iclass 15, count 0 2006.285.13:35:15.02#ibcon#about to write, iclass 15, count 0 2006.285.13:35:15.02#ibcon#wrote, iclass 15, count 0 2006.285.13:35:15.02#ibcon#about to read 3, iclass 15, count 0 2006.285.13:35:15.04#ibcon#read 3, iclass 15, count 0 2006.285.13:35:15.05#ibcon#about to read 4, iclass 15, count 0 2006.285.13:35:15.05#ibcon#read 4, iclass 15, count 0 2006.285.13:35:15.05#ibcon#about to read 5, iclass 15, count 0 2006.285.13:35:15.05#ibcon#read 5, iclass 15, count 0 2006.285.13:35:15.05#ibcon#about to read 6, iclass 15, count 0 2006.285.13:35:15.05#ibcon#read 6, iclass 15, count 0 2006.285.13:35:15.05#ibcon#end of sib2, iclass 15, count 0 2006.285.13:35:15.05#ibcon#*after write, iclass 15, count 0 2006.285.13:35:15.05#ibcon#*before return 0, iclass 15, count 0 2006.285.13:35:15.05#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:35:15.05#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:35:15.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:35:15.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:35:15.05$vck44/vblo=6,719.99 2006.285.13:35:15.05#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.13:35:15.05#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.13:35:15.05#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:15.05#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:35:15.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:35:15.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:35:15.05#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:35:15.05#ibcon#first serial, iclass 17, count 0 2006.285.13:35:15.05#ibcon#enter sib2, iclass 17, count 0 2006.285.13:35:15.05#ibcon#flushed, iclass 17, count 0 2006.285.13:35:15.05#ibcon#about to write, iclass 17, count 0 2006.285.13:35:15.05#ibcon#wrote, iclass 17, count 0 2006.285.13:35:15.05#ibcon#about to read 3, iclass 17, count 0 2006.285.13:35:15.06#ibcon#read 3, iclass 17, count 0 2006.285.13:35:15.06#ibcon#about to read 4, iclass 17, count 0 2006.285.13:35:15.07#ibcon#read 4, iclass 17, count 0 2006.285.13:35:15.07#ibcon#about to read 5, iclass 17, count 0 2006.285.13:35:15.07#ibcon#read 5, iclass 17, count 0 2006.285.13:35:15.07#ibcon#about to read 6, iclass 17, count 0 2006.285.13:35:15.07#ibcon#read 6, iclass 17, count 0 2006.285.13:35:15.07#ibcon#end of sib2, iclass 17, count 0 2006.285.13:35:15.07#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:35:15.07#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:35:15.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:35:15.07#ibcon#*before write, iclass 17, count 0 2006.285.13:35:15.07#ibcon#enter sib2, iclass 17, count 0 2006.285.13:35:15.07#ibcon#flushed, iclass 17, count 0 2006.285.13:35:15.07#ibcon#about to write, iclass 17, count 0 2006.285.13:35:15.07#ibcon#wrote, iclass 17, count 0 2006.285.13:35:15.07#ibcon#about to read 3, iclass 17, count 0 2006.285.13:35:15.10#ibcon#read 3, iclass 17, count 0 2006.285.13:35:15.11#ibcon#about to read 4, iclass 17, count 0 2006.285.13:35:15.11#ibcon#read 4, iclass 17, count 0 2006.285.13:35:15.11#ibcon#about to read 5, iclass 17, count 0 2006.285.13:35:15.11#ibcon#read 5, iclass 17, count 0 2006.285.13:35:15.11#ibcon#about to read 6, iclass 17, count 0 2006.285.13:35:15.11#ibcon#read 6, iclass 17, count 0 2006.285.13:35:15.11#ibcon#end of sib2, iclass 17, count 0 2006.285.13:35:15.11#ibcon#*after write, iclass 17, count 0 2006.285.13:35:15.11#ibcon#*before return 0, iclass 17, count 0 2006.285.13:35:15.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:35:15.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:35:15.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:35:15.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:35:15.11$vck44/vb=6,3 2006.285.13:35:15.21#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.13:35:15.21#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.13:35:15.21#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:15.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:35:15.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:35:15.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:35:15.21#ibcon#enter wrdev, iclass 19, count 2 2006.285.13:35:15.21#ibcon#first serial, iclass 19, count 2 2006.285.13:35:15.21#ibcon#enter sib2, iclass 19, count 2 2006.285.13:35:15.21#ibcon#flushed, iclass 19, count 2 2006.285.13:35:15.21#ibcon#about to write, iclass 19, count 2 2006.285.13:35:15.21#ibcon#wrote, iclass 19, count 2 2006.285.13:35:15.21#ibcon#about to read 3, iclass 19, count 2 2006.285.13:35:15.22#ibcon#read 3, iclass 19, count 2 2006.285.13:35:15.23#ibcon#about to read 4, iclass 19, count 2 2006.285.13:35:15.23#ibcon#read 4, iclass 19, count 2 2006.285.13:35:15.23#ibcon#about to read 5, iclass 19, count 2 2006.285.13:35:15.23#ibcon#read 5, iclass 19, count 2 2006.285.13:35:15.23#ibcon#about to read 6, iclass 19, count 2 2006.285.13:35:15.23#ibcon#read 6, iclass 19, count 2 2006.285.13:35:15.23#ibcon#end of sib2, iclass 19, count 2 2006.285.13:35:15.23#ibcon#*mode == 0, iclass 19, count 2 2006.285.13:35:15.23#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.13:35:15.23#ibcon#[27=AT06-03\r\n] 2006.285.13:35:15.23#ibcon#*before write, iclass 19, count 2 2006.285.13:35:15.23#ibcon#enter sib2, iclass 19, count 2 2006.285.13:35:15.23#ibcon#flushed, iclass 19, count 2 2006.285.13:35:15.23#ibcon#about to write, iclass 19, count 2 2006.285.13:35:15.23#ibcon#wrote, iclass 19, count 2 2006.285.13:35:15.23#ibcon#about to read 3, iclass 19, count 2 2006.285.13:35:15.25#ibcon#read 3, iclass 19, count 2 2006.285.13:35:15.25#ibcon#about to read 4, iclass 19, count 2 2006.285.13:35:15.26#ibcon#read 4, iclass 19, count 2 2006.285.13:35:15.26#ibcon#about to read 5, iclass 19, count 2 2006.285.13:35:15.26#ibcon#read 5, iclass 19, count 2 2006.285.13:35:15.26#ibcon#about to read 6, iclass 19, count 2 2006.285.13:35:15.26#ibcon#read 6, iclass 19, count 2 2006.285.13:35:15.26#ibcon#end of sib2, iclass 19, count 2 2006.285.13:35:15.26#ibcon#*after write, iclass 19, count 2 2006.285.13:35:15.26#ibcon#*before return 0, iclass 19, count 2 2006.285.13:35:15.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:35:15.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:35:15.26#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.13:35:15.26#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:15.26#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:35:15.37#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:35:15.37#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:35:15.37#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:35:15.38#ibcon#first serial, iclass 19, count 0 2006.285.13:35:15.38#ibcon#enter sib2, iclass 19, count 0 2006.285.13:35:15.38#ibcon#flushed, iclass 19, count 0 2006.285.13:35:15.38#ibcon#about to write, iclass 19, count 0 2006.285.13:35:15.38#ibcon#wrote, iclass 19, count 0 2006.285.13:35:15.38#ibcon#about to read 3, iclass 19, count 0 2006.285.13:35:15.39#ibcon#read 3, iclass 19, count 0 2006.285.13:35:15.39#ibcon#about to read 4, iclass 19, count 0 2006.285.13:35:15.39#ibcon#read 4, iclass 19, count 0 2006.285.13:35:15.40#ibcon#about to read 5, iclass 19, count 0 2006.285.13:35:15.40#ibcon#read 5, iclass 19, count 0 2006.285.13:35:15.40#ibcon#about to read 6, iclass 19, count 0 2006.285.13:35:15.40#ibcon#read 6, iclass 19, count 0 2006.285.13:35:15.40#ibcon#end of sib2, iclass 19, count 0 2006.285.13:35:15.40#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:35:15.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:35:15.40#ibcon#[27=USB\r\n] 2006.285.13:35:15.40#ibcon#*before write, iclass 19, count 0 2006.285.13:35:15.40#ibcon#enter sib2, iclass 19, count 0 2006.285.13:35:15.40#ibcon#flushed, iclass 19, count 0 2006.285.13:35:15.40#ibcon#about to write, iclass 19, count 0 2006.285.13:35:15.40#ibcon#wrote, iclass 19, count 0 2006.285.13:35:15.40#ibcon#about to read 3, iclass 19, count 0 2006.285.13:35:15.42#ibcon#read 3, iclass 19, count 0 2006.285.13:35:15.42#ibcon#about to read 4, iclass 19, count 0 2006.285.13:35:15.42#ibcon#read 4, iclass 19, count 0 2006.285.13:35:15.42#ibcon#about to read 5, iclass 19, count 0 2006.285.13:35:15.43#ibcon#read 5, iclass 19, count 0 2006.285.13:35:15.43#ibcon#about to read 6, iclass 19, count 0 2006.285.13:35:15.43#ibcon#read 6, iclass 19, count 0 2006.285.13:35:15.43#ibcon#end of sib2, iclass 19, count 0 2006.285.13:35:15.43#ibcon#*after write, iclass 19, count 0 2006.285.13:35:15.43#ibcon#*before return 0, iclass 19, count 0 2006.285.13:35:15.43#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:35:15.43#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:35:15.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:35:15.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:35:15.43$vck44/vblo=7,734.99 2006.285.13:35:15.43#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.13:35:15.43#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.13:35:15.43#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:15.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:35:15.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:35:15.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:35:15.43#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:35:15.43#ibcon#first serial, iclass 21, count 0 2006.285.13:35:15.43#ibcon#enter sib2, iclass 21, count 0 2006.285.13:35:15.43#ibcon#flushed, iclass 21, count 0 2006.285.13:35:15.43#ibcon#about to write, iclass 21, count 0 2006.285.13:35:15.43#ibcon#wrote, iclass 21, count 0 2006.285.13:35:15.43#ibcon#about to read 3, iclass 21, count 0 2006.285.13:35:15.44#ibcon#read 3, iclass 21, count 0 2006.285.13:35:15.44#ibcon#about to read 4, iclass 21, count 0 2006.285.13:35:15.44#ibcon#read 4, iclass 21, count 0 2006.285.13:35:15.45#ibcon#about to read 5, iclass 21, count 0 2006.285.13:35:15.45#ibcon#read 5, iclass 21, count 0 2006.285.13:35:15.45#ibcon#about to read 6, iclass 21, count 0 2006.285.13:35:15.45#ibcon#read 6, iclass 21, count 0 2006.285.13:35:15.45#ibcon#end of sib2, iclass 21, count 0 2006.285.13:35:15.45#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:35:15.45#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:35:15.45#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:35:15.45#ibcon#*before write, iclass 21, count 0 2006.285.13:35:15.45#ibcon#enter sib2, iclass 21, count 0 2006.285.13:35:15.45#ibcon#flushed, iclass 21, count 0 2006.285.13:35:15.45#ibcon#about to write, iclass 21, count 0 2006.285.13:35:15.45#ibcon#wrote, iclass 21, count 0 2006.285.13:35:15.45#ibcon#about to read 3, iclass 21, count 0 2006.285.13:35:15.48#ibcon#read 3, iclass 21, count 0 2006.285.13:35:15.48#ibcon#about to read 4, iclass 21, count 0 2006.285.13:35:15.48#ibcon#read 4, iclass 21, count 0 2006.285.13:35:15.48#ibcon#about to read 5, iclass 21, count 0 2006.285.13:35:15.49#ibcon#read 5, iclass 21, count 0 2006.285.13:35:15.49#ibcon#about to read 6, iclass 21, count 0 2006.285.13:35:15.49#ibcon#read 6, iclass 21, count 0 2006.285.13:35:15.49#ibcon#end of sib2, iclass 21, count 0 2006.285.13:35:15.49#ibcon#*after write, iclass 21, count 0 2006.285.13:35:15.49#ibcon#*before return 0, iclass 21, count 0 2006.285.13:35:15.49#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:35:15.49#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:35:15.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:35:15.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:35:15.49$vck44/vb=7,4 2006.285.13:35:15.49#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.13:35:15.49#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.13:35:15.49#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:15.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:35:15.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:35:15.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:35:15.54#ibcon#enter wrdev, iclass 23, count 2 2006.285.13:35:15.54#ibcon#first serial, iclass 23, count 2 2006.285.13:35:15.55#ibcon#enter sib2, iclass 23, count 2 2006.285.13:35:15.55#ibcon#flushed, iclass 23, count 2 2006.285.13:35:15.55#ibcon#about to write, iclass 23, count 2 2006.285.13:35:15.55#ibcon#wrote, iclass 23, count 2 2006.285.13:35:15.55#ibcon#about to read 3, iclass 23, count 2 2006.285.13:35:15.56#ibcon#read 3, iclass 23, count 2 2006.285.13:35:15.56#ibcon#about to read 4, iclass 23, count 2 2006.285.13:35:15.56#ibcon#read 4, iclass 23, count 2 2006.285.13:35:15.56#ibcon#about to read 5, iclass 23, count 2 2006.285.13:35:15.57#ibcon#read 5, iclass 23, count 2 2006.285.13:35:15.57#ibcon#about to read 6, iclass 23, count 2 2006.285.13:35:15.57#ibcon#read 6, iclass 23, count 2 2006.285.13:35:15.57#ibcon#end of sib2, iclass 23, count 2 2006.285.13:35:15.57#ibcon#*mode == 0, iclass 23, count 2 2006.285.13:35:15.57#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.13:35:15.57#ibcon#[27=AT07-04\r\n] 2006.285.13:35:15.57#ibcon#*before write, iclass 23, count 2 2006.285.13:35:15.57#ibcon#enter sib2, iclass 23, count 2 2006.285.13:35:15.57#ibcon#flushed, iclass 23, count 2 2006.285.13:35:15.57#ibcon#about to write, iclass 23, count 2 2006.285.13:35:15.57#ibcon#wrote, iclass 23, count 2 2006.285.13:35:15.57#ibcon#about to read 3, iclass 23, count 2 2006.285.13:35:15.59#ibcon#read 3, iclass 23, count 2 2006.285.13:35:15.59#ibcon#about to read 4, iclass 23, count 2 2006.285.13:35:15.59#ibcon#read 4, iclass 23, count 2 2006.285.13:35:15.59#ibcon#about to read 5, iclass 23, count 2 2006.285.13:35:15.60#ibcon#read 5, iclass 23, count 2 2006.285.13:35:15.60#ibcon#about to read 6, iclass 23, count 2 2006.285.13:35:15.60#ibcon#read 6, iclass 23, count 2 2006.285.13:35:15.60#ibcon#end of sib2, iclass 23, count 2 2006.285.13:35:15.60#ibcon#*after write, iclass 23, count 2 2006.285.13:35:15.60#ibcon#*before return 0, iclass 23, count 2 2006.285.13:35:15.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:35:15.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:35:15.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.13:35:15.60#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:15.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:35:15.71#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:35:15.71#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:35:15.71#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:35:15.71#ibcon#first serial, iclass 23, count 0 2006.285.13:35:15.71#ibcon#enter sib2, iclass 23, count 0 2006.285.13:35:15.72#ibcon#flushed, iclass 23, count 0 2006.285.13:35:15.72#ibcon#about to write, iclass 23, count 0 2006.285.13:35:15.72#ibcon#wrote, iclass 23, count 0 2006.285.13:35:15.72#ibcon#about to read 3, iclass 23, count 0 2006.285.13:35:15.73#ibcon#read 3, iclass 23, count 0 2006.285.13:35:15.73#ibcon#about to read 4, iclass 23, count 0 2006.285.13:35:15.73#ibcon#read 4, iclass 23, count 0 2006.285.13:35:15.73#ibcon#about to read 5, iclass 23, count 0 2006.285.13:35:15.73#ibcon#read 5, iclass 23, count 0 2006.285.13:35:15.74#ibcon#about to read 6, iclass 23, count 0 2006.285.13:35:15.74#ibcon#read 6, iclass 23, count 0 2006.285.13:35:15.74#ibcon#end of sib2, iclass 23, count 0 2006.285.13:35:15.74#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:35:15.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:35:15.74#ibcon#[27=USB\r\n] 2006.285.13:35:15.74#ibcon#*before write, iclass 23, count 0 2006.285.13:35:15.74#ibcon#enter sib2, iclass 23, count 0 2006.285.13:35:15.74#ibcon#flushed, iclass 23, count 0 2006.285.13:35:15.74#ibcon#about to write, iclass 23, count 0 2006.285.13:35:15.74#ibcon#wrote, iclass 23, count 0 2006.285.13:35:15.74#ibcon#about to read 3, iclass 23, count 0 2006.285.13:35:15.76#ibcon#read 3, iclass 23, count 0 2006.285.13:35:15.76#ibcon#about to read 4, iclass 23, count 0 2006.285.13:35:15.76#ibcon#read 4, iclass 23, count 0 2006.285.13:35:15.76#ibcon#about to read 5, iclass 23, count 0 2006.285.13:35:15.77#ibcon#read 5, iclass 23, count 0 2006.285.13:35:15.77#ibcon#about to read 6, iclass 23, count 0 2006.285.13:35:15.77#ibcon#read 6, iclass 23, count 0 2006.285.13:35:15.77#ibcon#end of sib2, iclass 23, count 0 2006.285.13:35:15.77#ibcon#*after write, iclass 23, count 0 2006.285.13:35:15.77#ibcon#*before return 0, iclass 23, count 0 2006.285.13:35:15.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:35:15.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:35:15.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:35:15.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:35:15.77$vck44/vblo=8,744.99 2006.285.13:35:15.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.13:35:15.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.13:35:15.77#ibcon#ireg 17 cls_cnt 0 2006.285.13:35:15.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:35:15.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:35:15.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:35:15.77#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:35:15.77#ibcon#first serial, iclass 25, count 0 2006.285.13:35:15.77#ibcon#enter sib2, iclass 25, count 0 2006.285.13:35:15.77#ibcon#flushed, iclass 25, count 0 2006.285.13:35:15.77#ibcon#about to write, iclass 25, count 0 2006.285.13:35:15.77#ibcon#wrote, iclass 25, count 0 2006.285.13:35:15.77#ibcon#about to read 3, iclass 25, count 0 2006.285.13:35:15.78#ibcon#read 3, iclass 25, count 0 2006.285.13:35:15.78#ibcon#about to read 4, iclass 25, count 0 2006.285.13:35:15.78#ibcon#read 4, iclass 25, count 0 2006.285.13:35:15.79#ibcon#about to read 5, iclass 25, count 0 2006.285.13:35:15.79#ibcon#read 5, iclass 25, count 0 2006.285.13:35:15.79#ibcon#about to read 6, iclass 25, count 0 2006.285.13:35:15.79#ibcon#read 6, iclass 25, count 0 2006.285.13:35:15.79#ibcon#end of sib2, iclass 25, count 0 2006.285.13:35:15.79#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:35:15.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:35:15.79#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:35:15.79#ibcon#*before write, iclass 25, count 0 2006.285.13:35:15.79#ibcon#enter sib2, iclass 25, count 0 2006.285.13:35:15.79#ibcon#flushed, iclass 25, count 0 2006.285.13:35:15.79#ibcon#about to write, iclass 25, count 0 2006.285.13:35:15.79#ibcon#wrote, iclass 25, count 0 2006.285.13:35:15.79#ibcon#about to read 3, iclass 25, count 0 2006.285.13:35:15.82#ibcon#read 3, iclass 25, count 0 2006.285.13:35:15.82#ibcon#about to read 4, iclass 25, count 0 2006.285.13:35:15.82#ibcon#read 4, iclass 25, count 0 2006.285.13:35:15.82#ibcon#about to read 5, iclass 25, count 0 2006.285.13:35:15.83#ibcon#read 5, iclass 25, count 0 2006.285.13:35:15.83#ibcon#about to read 6, iclass 25, count 0 2006.285.13:35:15.83#ibcon#read 6, iclass 25, count 0 2006.285.13:35:15.83#ibcon#end of sib2, iclass 25, count 0 2006.285.13:35:15.83#ibcon#*after write, iclass 25, count 0 2006.285.13:35:15.83#ibcon#*before return 0, iclass 25, count 0 2006.285.13:35:15.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:35:15.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:35:15.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:35:15.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:35:15.83$vck44/vb=8,4 2006.285.13:35:15.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.13:35:15.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.13:35:15.83#ibcon#ireg 11 cls_cnt 2 2006.285.13:35:15.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:35:15.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:35:15.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:35:15.88#ibcon#enter wrdev, iclass 27, count 2 2006.285.13:35:15.88#ibcon#first serial, iclass 27, count 2 2006.285.13:35:15.89#ibcon#enter sib2, iclass 27, count 2 2006.285.13:35:15.89#ibcon#flushed, iclass 27, count 2 2006.285.13:35:15.89#ibcon#about to write, iclass 27, count 2 2006.285.13:35:15.89#ibcon#wrote, iclass 27, count 2 2006.285.13:35:15.89#ibcon#about to read 3, iclass 27, count 2 2006.285.13:35:15.90#ibcon#read 3, iclass 27, count 2 2006.285.13:35:15.90#ibcon#about to read 4, iclass 27, count 2 2006.285.13:35:15.90#ibcon#read 4, iclass 27, count 2 2006.285.13:35:15.90#ibcon#about to read 5, iclass 27, count 2 2006.285.13:35:15.91#ibcon#read 5, iclass 27, count 2 2006.285.13:35:15.91#ibcon#about to read 6, iclass 27, count 2 2006.285.13:35:15.91#ibcon#read 6, iclass 27, count 2 2006.285.13:35:15.91#ibcon#end of sib2, iclass 27, count 2 2006.285.13:35:15.91#ibcon#*mode == 0, iclass 27, count 2 2006.285.13:35:15.91#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.13:35:15.91#ibcon#[27=AT08-04\r\n] 2006.285.13:35:15.91#ibcon#*before write, iclass 27, count 2 2006.285.13:35:15.91#ibcon#enter sib2, iclass 27, count 2 2006.285.13:35:15.91#ibcon#flushed, iclass 27, count 2 2006.285.13:35:15.91#ibcon#about to write, iclass 27, count 2 2006.285.13:35:15.91#ibcon#wrote, iclass 27, count 2 2006.285.13:35:15.91#ibcon#about to read 3, iclass 27, count 2 2006.285.13:35:15.93#ibcon#read 3, iclass 27, count 2 2006.285.13:35:15.93#ibcon#about to read 4, iclass 27, count 2 2006.285.13:35:15.93#ibcon#read 4, iclass 27, count 2 2006.285.13:35:15.93#ibcon#about to read 5, iclass 27, count 2 2006.285.13:35:15.94#ibcon#read 5, iclass 27, count 2 2006.285.13:35:15.94#ibcon#about to read 6, iclass 27, count 2 2006.285.13:35:15.94#ibcon#read 6, iclass 27, count 2 2006.285.13:35:15.94#ibcon#end of sib2, iclass 27, count 2 2006.285.13:35:15.94#ibcon#*after write, iclass 27, count 2 2006.285.13:35:15.94#ibcon#*before return 0, iclass 27, count 2 2006.285.13:35:15.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:35:15.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:35:15.94#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.13:35:15.94#ibcon#ireg 7 cls_cnt 0 2006.285.13:35:15.94#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:35:16.05#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:35:16.05#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:35:16.06#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:35:16.06#ibcon#first serial, iclass 27, count 0 2006.285.13:35:16.06#ibcon#enter sib2, iclass 27, count 0 2006.285.13:35:16.06#ibcon#flushed, iclass 27, count 0 2006.285.13:35:16.06#ibcon#about to write, iclass 27, count 0 2006.285.13:35:16.06#ibcon#wrote, iclass 27, count 0 2006.285.13:35:16.06#ibcon#about to read 3, iclass 27, count 0 2006.285.13:35:16.07#ibcon#read 3, iclass 27, count 0 2006.285.13:35:16.07#ibcon#about to read 4, iclass 27, count 0 2006.285.13:35:16.08#ibcon#read 4, iclass 27, count 0 2006.285.13:35:16.08#ibcon#about to read 5, iclass 27, count 0 2006.285.13:35:16.08#ibcon#read 5, iclass 27, count 0 2006.285.13:35:16.08#ibcon#about to read 6, iclass 27, count 0 2006.285.13:35:16.08#ibcon#read 6, iclass 27, count 0 2006.285.13:35:16.08#ibcon#end of sib2, iclass 27, count 0 2006.285.13:35:16.08#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:35:16.08#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:35:16.08#ibcon#[27=USB\r\n] 2006.285.13:35:16.08#ibcon#*before write, iclass 27, count 0 2006.285.13:35:16.08#ibcon#enter sib2, iclass 27, count 0 2006.285.13:35:16.08#ibcon#flushed, iclass 27, count 0 2006.285.13:35:16.08#ibcon#about to write, iclass 27, count 0 2006.285.13:35:16.08#ibcon#wrote, iclass 27, count 0 2006.285.13:35:16.08#ibcon#about to read 3, iclass 27, count 0 2006.285.13:35:16.10#ibcon#read 3, iclass 27, count 0 2006.285.13:35:16.11#ibcon#about to read 4, iclass 27, count 0 2006.285.13:35:16.11#ibcon#read 4, iclass 27, count 0 2006.285.13:35:16.11#ibcon#about to read 5, iclass 27, count 0 2006.285.13:35:16.11#ibcon#read 5, iclass 27, count 0 2006.285.13:35:16.11#ibcon#about to read 6, iclass 27, count 0 2006.285.13:35:16.11#ibcon#read 6, iclass 27, count 0 2006.285.13:35:16.11#ibcon#end of sib2, iclass 27, count 0 2006.285.13:35:16.11#ibcon#*after write, iclass 27, count 0 2006.285.13:35:16.11#ibcon#*before return 0, iclass 27, count 0 2006.285.13:35:16.11#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:35:16.11#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:35:16.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:35:16.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:35:16.11$vck44/vabw=wide 2006.285.13:35:16.11#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.13:35:16.11#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.13:35:16.11#ibcon#ireg 8 cls_cnt 0 2006.285.13:35:16.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:35:16.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:35:16.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:35:16.11#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:35:16.11#ibcon#first serial, iclass 29, count 0 2006.285.13:35:16.11#ibcon#enter sib2, iclass 29, count 0 2006.285.13:35:16.11#ibcon#flushed, iclass 29, count 0 2006.285.13:35:16.11#ibcon#about to write, iclass 29, count 0 2006.285.13:35:16.11#ibcon#wrote, iclass 29, count 0 2006.285.13:35:16.11#ibcon#about to read 3, iclass 29, count 0 2006.285.13:35:16.12#ibcon#read 3, iclass 29, count 0 2006.285.13:35:16.24#ibcon#about to read 4, iclass 29, count 0 2006.285.13:35:16.24#ibcon#read 4, iclass 29, count 0 2006.285.13:35:16.24#ibcon#about to read 5, iclass 29, count 0 2006.285.13:35:16.24#ibcon#read 5, iclass 29, count 0 2006.285.13:35:16.24#ibcon#about to read 6, iclass 29, count 0 2006.285.13:35:16.24#ibcon#read 6, iclass 29, count 0 2006.285.13:35:16.24#ibcon#end of sib2, iclass 29, count 0 2006.285.13:35:16.24#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:35:16.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:35:16.24#ibcon#[25=BW32\r\n] 2006.285.13:35:16.24#ibcon#*before write, iclass 29, count 0 2006.285.13:35:16.24#ibcon#enter sib2, iclass 29, count 0 2006.285.13:35:16.24#ibcon#flushed, iclass 29, count 0 2006.285.13:35:16.24#ibcon#about to write, iclass 29, count 0 2006.285.13:35:16.24#ibcon#wrote, iclass 29, count 0 2006.285.13:35:16.24#ibcon#about to read 3, iclass 29, count 0 2006.285.13:35:16.27#ibcon#read 3, iclass 29, count 0 2006.285.13:35:16.27#ibcon#about to read 4, iclass 29, count 0 2006.285.13:35:16.28#ibcon#read 4, iclass 29, count 0 2006.285.13:35:16.28#ibcon#about to read 5, iclass 29, count 0 2006.285.13:35:16.28#ibcon#read 5, iclass 29, count 0 2006.285.13:35:16.28#ibcon#about to read 6, iclass 29, count 0 2006.285.13:35:16.28#ibcon#read 6, iclass 29, count 0 2006.285.13:35:16.28#ibcon#end of sib2, iclass 29, count 0 2006.285.13:35:16.28#ibcon#*after write, iclass 29, count 0 2006.285.13:35:16.28#ibcon#*before return 0, iclass 29, count 0 2006.285.13:35:16.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:35:16.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:35:16.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:35:16.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:35:16.28$vck44/vbbw=wide 2006.285.13:35:16.28#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.13:35:16.28#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.13:35:16.28#ibcon#ireg 8 cls_cnt 0 2006.285.13:35:16.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:35:16.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:35:16.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:35:16.28#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:35:16.28#ibcon#first serial, iclass 31, count 0 2006.285.13:35:16.28#ibcon#enter sib2, iclass 31, count 0 2006.285.13:35:16.28#ibcon#flushed, iclass 31, count 0 2006.285.13:35:16.28#ibcon#about to write, iclass 31, count 0 2006.285.13:35:16.28#ibcon#wrote, iclass 31, count 0 2006.285.13:35:16.28#ibcon#about to read 3, iclass 31, count 0 2006.285.13:35:16.29#ibcon#read 3, iclass 31, count 0 2006.285.13:35:16.29#ibcon#about to read 4, iclass 31, count 0 2006.285.13:35:16.30#ibcon#read 4, iclass 31, count 0 2006.285.13:35:16.30#ibcon#about to read 5, iclass 31, count 0 2006.285.13:35:16.30#ibcon#read 5, iclass 31, count 0 2006.285.13:35:16.30#ibcon#about to read 6, iclass 31, count 0 2006.285.13:35:16.30#ibcon#read 6, iclass 31, count 0 2006.285.13:35:16.30#ibcon#end of sib2, iclass 31, count 0 2006.285.13:35:16.30#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:35:16.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:35:16.30#ibcon#[27=BW32\r\n] 2006.285.13:35:16.30#ibcon#*before write, iclass 31, count 0 2006.285.13:35:16.30#ibcon#enter sib2, iclass 31, count 0 2006.285.13:35:16.30#ibcon#flushed, iclass 31, count 0 2006.285.13:35:16.30#ibcon#about to write, iclass 31, count 0 2006.285.13:35:16.30#ibcon#wrote, iclass 31, count 0 2006.285.13:35:16.30#ibcon#about to read 3, iclass 31, count 0 2006.285.13:35:16.32#ibcon#read 3, iclass 31, count 0 2006.285.13:35:16.32#ibcon#about to read 4, iclass 31, count 0 2006.285.13:35:16.33#ibcon#read 4, iclass 31, count 0 2006.285.13:35:16.33#ibcon#about to read 5, iclass 31, count 0 2006.285.13:35:16.33#ibcon#read 5, iclass 31, count 0 2006.285.13:35:16.33#ibcon#about to read 6, iclass 31, count 0 2006.285.13:35:16.33#ibcon#read 6, iclass 31, count 0 2006.285.13:35:16.33#ibcon#end of sib2, iclass 31, count 0 2006.285.13:35:16.33#ibcon#*after write, iclass 31, count 0 2006.285.13:35:16.33#ibcon#*before return 0, iclass 31, count 0 2006.285.13:35:16.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:35:16.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:35:16.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:35:16.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:35:16.33$setupk4/ifdk4 2006.285.13:35:16.33$ifdk4/lo= 2006.285.13:35:16.33$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:35:16.33$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:35:16.33$ifdk4/patch= 2006.285.13:35:16.33$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:35:16.33$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:35:16.33$setupk4/!*+20s 2006.285.13:35:23.51#abcon#<5=/04 1.4 2.4 19.12 971015.3\r\n> 2006.285.13:35:23.53#abcon#{5=INTERFACE CLEAR} 2006.285.13:35:23.59#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:35:29.99$setupk4/"tpicd 2006.285.13:35:30.00$setupk4/echo=off 2006.285.13:35:30.00$setupk4/xlog=off 2006.285.13:35:30.00:!2006.285.13:40:03 2006.285.13:36:02.14#trakl#Source acquired 2006.285.13:36:03.14#flagr#flagr/antenna,acquired 2006.285.13:40:03.01:preob 2006.285.13:40:04.14/onsource/TRACKING 2006.285.13:40:04.14:!2006.285.13:40:13 2006.285.13:40:13.00:"tape 2006.285.13:40:13.00:"st=record 2006.285.13:40:13.00:data_valid=on 2006.285.13:40:13.00:midob 2006.285.13:40:13.14/onsource/TRACKING 2006.285.13:40:13.15/wx/19.11,1015.2,98 2006.285.13:40:13.35/cable/+6.4989E-03 2006.285.13:40:14.44/va/01,07,usb,yes,32,35 2006.285.13:40:14.44/va/02,06,usb,yes,32,32 2006.285.13:40:14.44/va/03,07,usb,yes,31,33 2006.285.13:40:14.44/va/04,06,usb,yes,33,34 2006.285.13:40:14.44/va/05,03,usb,yes,32,33 2006.285.13:40:14.44/va/06,04,usb,yes,29,29 2006.285.13:40:14.44/va/07,04,usb,yes,30,30 2006.285.13:40:14.44/va/08,03,usb,yes,30,37 2006.285.13:40:14.67/valo/01,524.99,yes,locked 2006.285.13:40:14.67/valo/02,534.99,yes,locked 2006.285.13:40:14.67/valo/03,564.99,yes,locked 2006.285.13:40:14.67/valo/04,624.99,yes,locked 2006.285.13:40:14.67/valo/05,734.99,yes,locked 2006.285.13:40:14.67/valo/06,814.99,yes,locked 2006.285.13:40:14.67/valo/07,864.99,yes,locked 2006.285.13:40:14.67/valo/08,884.99,yes,locked 2006.285.13:40:15.76/vb/01,04,usb,yes,30,28 2006.285.13:40:15.76/vb/02,05,usb,yes,28,28 2006.285.13:40:15.76/vb/03,04,usb,yes,29,32 2006.285.13:40:15.76/vb/04,05,usb,yes,29,28 2006.285.13:40:15.76/vb/05,04,usb,yes,26,28 2006.285.13:40:15.76/vb/06,03,usb,yes,37,33 2006.285.13:40:15.76/vb/07,04,usb,yes,30,30 2006.285.13:40:15.76/vb/08,04,usb,yes,27,31 2006.285.13:40:15.99/vblo/01,629.99,yes,locked 2006.285.13:40:15.99/vblo/02,634.99,yes,locked 2006.285.13:40:15.99/vblo/03,649.99,yes,locked 2006.285.13:40:15.99/vblo/04,679.99,yes,locked 2006.285.13:40:15.99/vblo/05,709.99,yes,locked 2006.285.13:40:15.99/vblo/06,719.99,yes,locked 2006.285.13:40:15.99/vblo/07,734.99,yes,locked 2006.285.13:40:15.99/vblo/08,744.99,yes,locked 2006.285.13:40:16.14/vabw/8 2006.285.13:40:16.29/vbbw/8 2006.285.13:40:16.38/xfe/off,on,12.0 2006.285.13:40:16.75/ifatt/23,28,28,28 2006.285.13:40:17.07/fmout-gps/S +2.81E-07 2006.285.13:40:17.09:!2006.285.13:41:33 2006.285.13:41:33.00:data_valid=off 2006.285.13:41:33.00:"et 2006.285.13:41:33.00:!+3s 2006.285.13:41:36.01:"tape 2006.285.13:41:36.01:postob 2006.285.13:41:36.15/cable/+6.5004E-03 2006.285.13:41:36.15/wx/19.11,1015.2,98 2006.285.13:41:37.07/fmout-gps/S +2.78E-07 2006.285.13:41:37.07:scan_name=285-1346,jd0610,240 2006.285.13:41:37.07:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.285.13:41:38.14#flagr#flagr/antenna,new-source 2006.285.13:41:38.14:checkk5 2006.285.13:41:38.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:41:39.15/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:41:39.63/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:41:40.12/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:41:40.56/chk_obsdata//k5ts1/T2851340??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.13:41:41.07/chk_obsdata//k5ts2/T2851340??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.13:41:41.50/chk_obsdata//k5ts3/T2851340??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.13:41:41.86/chk_obsdata//k5ts4/T2851340??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.13:41:42.82/k5log//k5ts1_log_newline 2006.285.13:41:43.83/k5log//k5ts2_log_newline 2006.285.13:41:44.76/k5log//k5ts3_log_newline 2006.285.13:41:45.52/k5log//k5ts4_log_newline 2006.285.13:41:45.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:41:45.54:setupk4=1 2006.285.13:41:45.54$setupk4/echo=on 2006.285.13:41:45.54$setupk4/pcalon 2006.285.13:41:45.54$pcalon/"no phase cal control is implemented here 2006.285.13:41:45.55$setupk4/"tpicd=stop 2006.285.13:41:45.55$setupk4/"rec=synch_on 2006.285.13:41:45.55$setupk4/"rec_mode=128 2006.285.13:41:45.55$setupk4/!* 2006.285.13:41:45.55$setupk4/recpk4 2006.285.13:41:45.55$recpk4/recpatch= 2006.285.13:41:45.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:41:45.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:41:45.55$setupk4/vck44 2006.285.13:41:45.55$vck44/valo=1,524.99 2006.285.13:41:45.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.13:41:45.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.13:41:45.55#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:45.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:41:45.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:41:45.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:41:45.55#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:41:45.55#ibcon#first serial, iclass 39, count 0 2006.285.13:41:45.55#ibcon#enter sib2, iclass 39, count 0 2006.285.13:41:45.55#ibcon#flushed, iclass 39, count 0 2006.285.13:41:45.55#ibcon#about to write, iclass 39, count 0 2006.285.13:41:45.55#ibcon#wrote, iclass 39, count 0 2006.285.13:41:45.55#ibcon#about to read 3, iclass 39, count 0 2006.285.13:41:45.56#ibcon#read 3, iclass 39, count 0 2006.285.13:41:45.56#ibcon#about to read 4, iclass 39, count 0 2006.285.13:41:45.56#ibcon#read 4, iclass 39, count 0 2006.285.13:41:45.56#ibcon#about to read 5, iclass 39, count 0 2006.285.13:41:45.56#ibcon#read 5, iclass 39, count 0 2006.285.13:41:45.56#ibcon#about to read 6, iclass 39, count 0 2006.285.13:41:45.56#ibcon#read 6, iclass 39, count 0 2006.285.13:41:45.56#ibcon#end of sib2, iclass 39, count 0 2006.285.13:41:45.56#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:41:45.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:41:45.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:41:45.56#ibcon#*before write, iclass 39, count 0 2006.285.13:41:45.56#ibcon#enter sib2, iclass 39, count 0 2006.285.13:41:45.56#ibcon#flushed, iclass 39, count 0 2006.285.13:41:45.56#ibcon#about to write, iclass 39, count 0 2006.285.13:41:45.56#ibcon#wrote, iclass 39, count 0 2006.285.13:41:45.56#ibcon#about to read 3, iclass 39, count 0 2006.285.13:41:45.61#ibcon#read 3, iclass 39, count 0 2006.285.13:41:45.61#ibcon#about to read 4, iclass 39, count 0 2006.285.13:41:45.61#ibcon#read 4, iclass 39, count 0 2006.285.13:41:45.61#ibcon#about to read 5, iclass 39, count 0 2006.285.13:41:45.61#ibcon#read 5, iclass 39, count 0 2006.285.13:41:45.61#ibcon#about to read 6, iclass 39, count 0 2006.285.13:41:45.61#ibcon#read 6, iclass 39, count 0 2006.285.13:41:45.61#ibcon#end of sib2, iclass 39, count 0 2006.285.13:41:45.61#ibcon#*after write, iclass 39, count 0 2006.285.13:41:45.61#ibcon#*before return 0, iclass 39, count 0 2006.285.13:41:45.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:41:45.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:41:45.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:41:45.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:41:45.62$vck44/va=1,7 2006.285.13:41:45.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.13:41:45.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.13:41:45.62#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:45.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:41:45.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:41:45.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:41:45.62#ibcon#enter wrdev, iclass 3, count 2 2006.285.13:41:45.62#ibcon#first serial, iclass 3, count 2 2006.285.13:41:45.62#ibcon#enter sib2, iclass 3, count 2 2006.285.13:41:45.62#ibcon#flushed, iclass 3, count 2 2006.285.13:41:45.62#ibcon#about to write, iclass 3, count 2 2006.285.13:41:45.62#ibcon#wrote, iclass 3, count 2 2006.285.13:41:45.62#ibcon#about to read 3, iclass 3, count 2 2006.285.13:41:45.63#ibcon#read 3, iclass 3, count 2 2006.285.13:41:45.63#ibcon#about to read 4, iclass 3, count 2 2006.285.13:41:45.63#ibcon#read 4, iclass 3, count 2 2006.285.13:41:45.63#ibcon#about to read 5, iclass 3, count 2 2006.285.13:41:45.63#ibcon#read 5, iclass 3, count 2 2006.285.13:41:45.63#ibcon#about to read 6, iclass 3, count 2 2006.285.13:41:45.63#ibcon#read 6, iclass 3, count 2 2006.285.13:41:45.63#ibcon#end of sib2, iclass 3, count 2 2006.285.13:41:45.63#ibcon#*mode == 0, iclass 3, count 2 2006.285.13:41:45.63#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.13:41:45.63#ibcon#[25=AT01-07\r\n] 2006.285.13:41:45.63#ibcon#*before write, iclass 3, count 2 2006.285.13:41:45.63#ibcon#enter sib2, iclass 3, count 2 2006.285.13:41:45.63#ibcon#flushed, iclass 3, count 2 2006.285.13:41:45.63#ibcon#about to write, iclass 3, count 2 2006.285.13:41:45.63#ibcon#wrote, iclass 3, count 2 2006.285.13:41:45.63#ibcon#about to read 3, iclass 3, count 2 2006.285.13:41:45.66#ibcon#read 3, iclass 3, count 2 2006.285.13:41:45.66#ibcon#about to read 4, iclass 3, count 2 2006.285.13:41:45.66#ibcon#read 4, iclass 3, count 2 2006.285.13:41:45.66#ibcon#about to read 5, iclass 3, count 2 2006.285.13:41:45.66#ibcon#read 5, iclass 3, count 2 2006.285.13:41:45.66#ibcon#about to read 6, iclass 3, count 2 2006.285.13:41:45.66#ibcon#read 6, iclass 3, count 2 2006.285.13:41:45.66#ibcon#end of sib2, iclass 3, count 2 2006.285.13:41:45.66#ibcon#*after write, iclass 3, count 2 2006.285.13:41:45.66#ibcon#*before return 0, iclass 3, count 2 2006.285.13:41:45.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:41:45.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:41:45.66#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.13:41:45.66#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:45.66#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:41:45.78#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:41:45.78#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:41:45.78#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:41:45.78#ibcon#first serial, iclass 3, count 0 2006.285.13:41:45.78#ibcon#enter sib2, iclass 3, count 0 2006.285.13:41:45.78#ibcon#flushed, iclass 3, count 0 2006.285.13:41:45.78#ibcon#about to write, iclass 3, count 0 2006.285.13:41:45.78#ibcon#wrote, iclass 3, count 0 2006.285.13:41:45.78#ibcon#about to read 3, iclass 3, count 0 2006.285.13:41:45.80#ibcon#read 3, iclass 3, count 0 2006.285.13:41:45.80#ibcon#about to read 4, iclass 3, count 0 2006.285.13:41:45.80#ibcon#read 4, iclass 3, count 0 2006.285.13:41:45.80#ibcon#about to read 5, iclass 3, count 0 2006.285.13:41:45.80#ibcon#read 5, iclass 3, count 0 2006.285.13:41:45.80#ibcon#about to read 6, iclass 3, count 0 2006.285.13:41:45.80#ibcon#read 6, iclass 3, count 0 2006.285.13:41:45.80#ibcon#end of sib2, iclass 3, count 0 2006.285.13:41:45.80#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:41:45.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:41:45.80#ibcon#[25=USB\r\n] 2006.285.13:41:45.80#ibcon#*before write, iclass 3, count 0 2006.285.13:41:45.80#ibcon#enter sib2, iclass 3, count 0 2006.285.13:41:45.80#ibcon#flushed, iclass 3, count 0 2006.285.13:41:45.80#ibcon#about to write, iclass 3, count 0 2006.285.13:41:45.80#ibcon#wrote, iclass 3, count 0 2006.285.13:41:45.80#ibcon#about to read 3, iclass 3, count 0 2006.285.13:41:45.83#ibcon#read 3, iclass 3, count 0 2006.285.13:41:45.83#ibcon#about to read 4, iclass 3, count 0 2006.285.13:41:45.83#ibcon#read 4, iclass 3, count 0 2006.285.13:41:45.83#ibcon#about to read 5, iclass 3, count 0 2006.285.13:41:45.83#ibcon#read 5, iclass 3, count 0 2006.285.13:41:45.83#ibcon#about to read 6, iclass 3, count 0 2006.285.13:41:45.83#ibcon#read 6, iclass 3, count 0 2006.285.13:41:45.83#ibcon#end of sib2, iclass 3, count 0 2006.285.13:41:45.83#ibcon#*after write, iclass 3, count 0 2006.285.13:41:45.83#ibcon#*before return 0, iclass 3, count 0 2006.285.13:41:45.83#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:41:45.83#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:41:45.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:41:45.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:41:45.84$vck44/valo=2,534.99 2006.285.13:41:45.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.13:41:45.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.13:41:45.84#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:45.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:41:45.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:41:45.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:41:45.84#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:41:45.84#ibcon#first serial, iclass 5, count 0 2006.285.13:41:45.84#ibcon#enter sib2, iclass 5, count 0 2006.285.13:41:45.84#ibcon#flushed, iclass 5, count 0 2006.285.13:41:45.84#ibcon#about to write, iclass 5, count 0 2006.285.13:41:45.84#ibcon#wrote, iclass 5, count 0 2006.285.13:41:45.84#ibcon#about to read 3, iclass 5, count 0 2006.285.13:41:45.85#ibcon#read 3, iclass 5, count 0 2006.285.13:41:45.85#ibcon#about to read 4, iclass 5, count 0 2006.285.13:41:45.85#ibcon#read 4, iclass 5, count 0 2006.285.13:41:45.85#ibcon#about to read 5, iclass 5, count 0 2006.285.13:41:45.85#ibcon#read 5, iclass 5, count 0 2006.285.13:41:45.85#ibcon#about to read 6, iclass 5, count 0 2006.285.13:41:45.85#ibcon#read 6, iclass 5, count 0 2006.285.13:41:45.85#ibcon#end of sib2, iclass 5, count 0 2006.285.13:41:45.85#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:41:45.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:41:45.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:41:45.85#ibcon#*before write, iclass 5, count 0 2006.285.13:41:45.85#ibcon#enter sib2, iclass 5, count 0 2006.285.13:41:45.85#ibcon#flushed, iclass 5, count 0 2006.285.13:41:45.85#ibcon#about to write, iclass 5, count 0 2006.285.13:41:45.85#ibcon#wrote, iclass 5, count 0 2006.285.13:41:45.85#ibcon#about to read 3, iclass 5, count 0 2006.285.13:41:45.89#ibcon#read 3, iclass 5, count 0 2006.285.13:41:45.89#ibcon#about to read 4, iclass 5, count 0 2006.285.13:41:45.89#ibcon#read 4, iclass 5, count 0 2006.285.13:41:45.89#ibcon#about to read 5, iclass 5, count 0 2006.285.13:41:45.89#ibcon#read 5, iclass 5, count 0 2006.285.13:41:45.89#ibcon#about to read 6, iclass 5, count 0 2006.285.13:41:45.89#ibcon#read 6, iclass 5, count 0 2006.285.13:41:45.89#ibcon#end of sib2, iclass 5, count 0 2006.285.13:41:45.89#ibcon#*after write, iclass 5, count 0 2006.285.13:41:45.89#ibcon#*before return 0, iclass 5, count 0 2006.285.13:41:45.89#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:41:45.89#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:41:45.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:41:45.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:41:45.91$vck44/va=2,6 2006.285.13:41:45.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.13:41:45.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.13:41:45.91#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:45.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:41:45.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:41:45.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:41:45.94#ibcon#enter wrdev, iclass 7, count 2 2006.285.13:41:45.94#ibcon#first serial, iclass 7, count 2 2006.285.13:41:45.94#ibcon#enter sib2, iclass 7, count 2 2006.285.13:41:45.94#ibcon#flushed, iclass 7, count 2 2006.285.13:41:45.94#ibcon#about to write, iclass 7, count 2 2006.285.13:41:45.94#ibcon#wrote, iclass 7, count 2 2006.285.13:41:45.94#ibcon#about to read 3, iclass 7, count 2 2006.285.13:41:45.96#ibcon#read 3, iclass 7, count 2 2006.285.13:41:45.96#ibcon#about to read 4, iclass 7, count 2 2006.285.13:41:45.96#ibcon#read 4, iclass 7, count 2 2006.285.13:41:45.96#ibcon#about to read 5, iclass 7, count 2 2006.285.13:41:45.96#ibcon#read 5, iclass 7, count 2 2006.285.13:41:45.96#ibcon#about to read 6, iclass 7, count 2 2006.285.13:41:45.96#ibcon#read 6, iclass 7, count 2 2006.285.13:41:45.96#ibcon#end of sib2, iclass 7, count 2 2006.285.13:41:45.96#ibcon#*mode == 0, iclass 7, count 2 2006.285.13:41:45.96#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.13:41:45.96#ibcon#[25=AT02-06\r\n] 2006.285.13:41:45.96#ibcon#*before write, iclass 7, count 2 2006.285.13:41:45.96#ibcon#enter sib2, iclass 7, count 2 2006.285.13:41:45.96#ibcon#flushed, iclass 7, count 2 2006.285.13:41:45.96#ibcon#about to write, iclass 7, count 2 2006.285.13:41:45.96#ibcon#wrote, iclass 7, count 2 2006.285.13:41:45.96#ibcon#about to read 3, iclass 7, count 2 2006.285.13:41:45.99#ibcon#read 3, iclass 7, count 2 2006.285.13:41:45.99#ibcon#about to read 4, iclass 7, count 2 2006.285.13:41:45.99#ibcon#read 4, iclass 7, count 2 2006.285.13:41:45.99#ibcon#about to read 5, iclass 7, count 2 2006.285.13:41:45.99#ibcon#read 5, iclass 7, count 2 2006.285.13:41:45.99#ibcon#about to read 6, iclass 7, count 2 2006.285.13:41:45.99#ibcon#read 6, iclass 7, count 2 2006.285.13:41:45.99#ibcon#end of sib2, iclass 7, count 2 2006.285.13:41:45.99#ibcon#*after write, iclass 7, count 2 2006.285.13:41:45.99#ibcon#*before return 0, iclass 7, count 2 2006.285.13:41:45.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:41:45.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:41:45.99#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.13:41:45.99#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:45.99#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:41:46.11#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:41:46.43#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:41:46.43#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:41:46.43#ibcon#first serial, iclass 7, count 0 2006.285.13:41:46.43#ibcon#enter sib2, iclass 7, count 0 2006.285.13:41:46.43#ibcon#flushed, iclass 7, count 0 2006.285.13:41:46.43#ibcon#about to write, iclass 7, count 0 2006.285.13:41:46.43#ibcon#wrote, iclass 7, count 0 2006.285.13:41:46.43#ibcon#about to read 3, iclass 7, count 0 2006.285.13:41:46.44#ibcon#read 3, iclass 7, count 0 2006.285.13:41:46.44#ibcon#about to read 4, iclass 7, count 0 2006.285.13:41:46.44#ibcon#read 4, iclass 7, count 0 2006.285.13:41:46.44#ibcon#about to read 5, iclass 7, count 0 2006.285.13:41:46.44#ibcon#read 5, iclass 7, count 0 2006.285.13:41:46.44#ibcon#about to read 6, iclass 7, count 0 2006.285.13:41:46.44#ibcon#read 6, iclass 7, count 0 2006.285.13:41:46.44#ibcon#end of sib2, iclass 7, count 0 2006.285.13:41:46.44#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:41:46.44#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:41:46.44#ibcon#[25=USB\r\n] 2006.285.13:41:46.44#ibcon#*before write, iclass 7, count 0 2006.285.13:41:46.44#ibcon#enter sib2, iclass 7, count 0 2006.285.13:41:46.44#ibcon#flushed, iclass 7, count 0 2006.285.13:41:46.44#ibcon#about to write, iclass 7, count 0 2006.285.13:41:46.44#ibcon#wrote, iclass 7, count 0 2006.285.13:41:46.44#ibcon#about to read 3, iclass 7, count 0 2006.285.13:41:46.47#ibcon#read 3, iclass 7, count 0 2006.285.13:41:46.47#ibcon#about to read 4, iclass 7, count 0 2006.285.13:41:46.47#ibcon#read 4, iclass 7, count 0 2006.285.13:41:46.47#ibcon#about to read 5, iclass 7, count 0 2006.285.13:41:46.47#ibcon#read 5, iclass 7, count 0 2006.285.13:41:46.47#ibcon#about to read 6, iclass 7, count 0 2006.285.13:41:46.47#ibcon#read 6, iclass 7, count 0 2006.285.13:41:46.47#ibcon#end of sib2, iclass 7, count 0 2006.285.13:41:46.47#ibcon#*after write, iclass 7, count 0 2006.285.13:41:46.47#ibcon#*before return 0, iclass 7, count 0 2006.285.13:41:46.47#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:41:46.47#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:41:46.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:41:46.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:41:46.47$vck44/valo=3,564.99 2006.285.13:41:46.47#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.13:41:46.47#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.13:41:46.47#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:46.47#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:41:46.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:41:46.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:41:46.47#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:41:46.47#ibcon#first serial, iclass 11, count 0 2006.285.13:41:46.48#ibcon#enter sib2, iclass 11, count 0 2006.285.13:41:46.48#ibcon#flushed, iclass 11, count 0 2006.285.13:41:46.48#ibcon#about to write, iclass 11, count 0 2006.285.13:41:46.48#ibcon#wrote, iclass 11, count 0 2006.285.13:41:46.48#ibcon#about to read 3, iclass 11, count 0 2006.285.13:41:46.49#ibcon#read 3, iclass 11, count 0 2006.285.13:41:46.49#ibcon#about to read 4, iclass 11, count 0 2006.285.13:41:46.49#ibcon#read 4, iclass 11, count 0 2006.285.13:41:46.49#ibcon#about to read 5, iclass 11, count 0 2006.285.13:41:46.49#ibcon#read 5, iclass 11, count 0 2006.285.13:41:46.49#ibcon#about to read 6, iclass 11, count 0 2006.285.13:41:46.49#ibcon#read 6, iclass 11, count 0 2006.285.13:41:46.49#ibcon#end of sib2, iclass 11, count 0 2006.285.13:41:46.49#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:41:46.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:41:46.49#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:41:46.49#ibcon#*before write, iclass 11, count 0 2006.285.13:41:46.49#ibcon#enter sib2, iclass 11, count 0 2006.285.13:41:46.49#ibcon#flushed, iclass 11, count 0 2006.285.13:41:46.49#ibcon#about to write, iclass 11, count 0 2006.285.13:41:46.49#ibcon#wrote, iclass 11, count 0 2006.285.13:41:46.49#ibcon#about to read 3, iclass 11, count 0 2006.285.13:41:46.53#ibcon#read 3, iclass 11, count 0 2006.285.13:41:46.53#ibcon#about to read 4, iclass 11, count 0 2006.285.13:41:46.53#ibcon#read 4, iclass 11, count 0 2006.285.13:41:46.53#ibcon#about to read 5, iclass 11, count 0 2006.285.13:41:46.53#ibcon#read 5, iclass 11, count 0 2006.285.13:41:46.53#ibcon#about to read 6, iclass 11, count 0 2006.285.13:41:46.53#ibcon#read 6, iclass 11, count 0 2006.285.13:41:46.53#ibcon#end of sib2, iclass 11, count 0 2006.285.13:41:46.53#ibcon#*after write, iclass 11, count 0 2006.285.13:41:46.53#ibcon#*before return 0, iclass 11, count 0 2006.285.13:41:46.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:41:46.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:41:46.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:41:46.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:41:46.53$vck44/va=3,7 2006.285.13:41:46.53#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.13:41:46.53#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.13:41:46.53#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:46.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:41:46.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:41:46.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:41:46.59#ibcon#enter wrdev, iclass 13, count 2 2006.285.13:41:46.59#ibcon#first serial, iclass 13, count 2 2006.285.13:41:46.59#ibcon#enter sib2, iclass 13, count 2 2006.285.13:41:46.59#ibcon#flushed, iclass 13, count 2 2006.285.13:41:46.59#ibcon#about to write, iclass 13, count 2 2006.285.13:41:46.59#ibcon#wrote, iclass 13, count 2 2006.285.13:41:46.59#ibcon#about to read 3, iclass 13, count 2 2006.285.13:41:46.61#ibcon#read 3, iclass 13, count 2 2006.285.13:41:46.61#ibcon#about to read 4, iclass 13, count 2 2006.285.13:41:46.61#ibcon#read 4, iclass 13, count 2 2006.285.13:41:46.61#ibcon#about to read 5, iclass 13, count 2 2006.285.13:41:46.61#ibcon#read 5, iclass 13, count 2 2006.285.13:41:46.61#ibcon#about to read 6, iclass 13, count 2 2006.285.13:41:46.61#ibcon#read 6, iclass 13, count 2 2006.285.13:41:46.61#ibcon#end of sib2, iclass 13, count 2 2006.285.13:41:46.61#ibcon#*mode == 0, iclass 13, count 2 2006.285.13:41:46.61#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.13:41:46.61#ibcon#[25=AT03-07\r\n] 2006.285.13:41:46.61#ibcon#*before write, iclass 13, count 2 2006.285.13:41:46.61#ibcon#enter sib2, iclass 13, count 2 2006.285.13:41:46.61#ibcon#flushed, iclass 13, count 2 2006.285.13:41:46.61#ibcon#about to write, iclass 13, count 2 2006.285.13:41:46.61#ibcon#wrote, iclass 13, count 2 2006.285.13:41:46.61#ibcon#about to read 3, iclass 13, count 2 2006.285.13:41:46.64#ibcon#read 3, iclass 13, count 2 2006.285.13:41:46.64#ibcon#about to read 4, iclass 13, count 2 2006.285.13:41:46.64#ibcon#read 4, iclass 13, count 2 2006.285.13:41:46.64#ibcon#about to read 5, iclass 13, count 2 2006.285.13:41:46.64#ibcon#read 5, iclass 13, count 2 2006.285.13:41:46.64#ibcon#about to read 6, iclass 13, count 2 2006.285.13:41:46.64#ibcon#read 6, iclass 13, count 2 2006.285.13:41:46.64#ibcon#end of sib2, iclass 13, count 2 2006.285.13:41:46.64#ibcon#*after write, iclass 13, count 2 2006.285.13:41:46.64#ibcon#*before return 0, iclass 13, count 2 2006.285.13:41:46.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:41:46.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:41:46.64#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.13:41:46.64#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:46.64#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:41:46.76#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:41:46.76#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:41:46.76#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:41:46.76#ibcon#first serial, iclass 13, count 0 2006.285.13:41:46.76#ibcon#enter sib2, iclass 13, count 0 2006.285.13:41:46.76#ibcon#flushed, iclass 13, count 0 2006.285.13:41:46.76#ibcon#about to write, iclass 13, count 0 2006.285.13:41:46.76#ibcon#wrote, iclass 13, count 0 2006.285.13:41:46.76#ibcon#about to read 3, iclass 13, count 0 2006.285.13:41:46.78#ibcon#read 3, iclass 13, count 0 2006.285.13:41:46.78#ibcon#about to read 4, iclass 13, count 0 2006.285.13:41:46.78#ibcon#read 4, iclass 13, count 0 2006.285.13:41:46.78#ibcon#about to read 5, iclass 13, count 0 2006.285.13:41:46.78#ibcon#read 5, iclass 13, count 0 2006.285.13:41:46.78#ibcon#about to read 6, iclass 13, count 0 2006.285.13:41:46.78#ibcon#read 6, iclass 13, count 0 2006.285.13:41:46.78#ibcon#end of sib2, iclass 13, count 0 2006.285.13:41:46.78#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:41:46.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:41:46.78#ibcon#[25=USB\r\n] 2006.285.13:41:46.78#ibcon#*before write, iclass 13, count 0 2006.285.13:41:46.78#ibcon#enter sib2, iclass 13, count 0 2006.285.13:41:46.78#ibcon#flushed, iclass 13, count 0 2006.285.13:41:46.78#ibcon#about to write, iclass 13, count 0 2006.285.13:41:46.78#ibcon#wrote, iclass 13, count 0 2006.285.13:41:46.78#ibcon#about to read 3, iclass 13, count 0 2006.285.13:41:46.81#ibcon#read 3, iclass 13, count 0 2006.285.13:41:46.81#ibcon#about to read 4, iclass 13, count 0 2006.285.13:41:47.04#ibcon#read 4, iclass 13, count 0 2006.285.13:41:47.04#ibcon#about to read 5, iclass 13, count 0 2006.285.13:41:47.04#ibcon#read 5, iclass 13, count 0 2006.285.13:41:47.04#ibcon#about to read 6, iclass 13, count 0 2006.285.13:41:47.04#ibcon#read 6, iclass 13, count 0 2006.285.13:41:47.04#ibcon#end of sib2, iclass 13, count 0 2006.285.13:41:47.04#ibcon#*after write, iclass 13, count 0 2006.285.13:41:47.04#ibcon#*before return 0, iclass 13, count 0 2006.285.13:41:47.04#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:41:47.04#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:41:47.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:41:47.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:41:47.04$vck44/valo=4,624.99 2006.285.13:41:47.04#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.13:41:47.04#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.13:41:47.04#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:47.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:41:47.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:41:47.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:41:47.04#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:41:47.04#ibcon#first serial, iclass 15, count 0 2006.285.13:41:47.04#ibcon#enter sib2, iclass 15, count 0 2006.285.13:41:47.04#ibcon#flushed, iclass 15, count 0 2006.285.13:41:47.04#ibcon#about to write, iclass 15, count 0 2006.285.13:41:47.04#ibcon#wrote, iclass 15, count 0 2006.285.13:41:47.04#ibcon#about to read 3, iclass 15, count 0 2006.285.13:41:47.05#ibcon#read 3, iclass 15, count 0 2006.285.13:41:47.05#ibcon#about to read 4, iclass 15, count 0 2006.285.13:41:47.05#ibcon#read 4, iclass 15, count 0 2006.285.13:41:47.05#ibcon#about to read 5, iclass 15, count 0 2006.285.13:41:47.05#ibcon#read 5, iclass 15, count 0 2006.285.13:41:47.05#ibcon#about to read 6, iclass 15, count 0 2006.285.13:41:47.05#ibcon#read 6, iclass 15, count 0 2006.285.13:41:47.05#ibcon#end of sib2, iclass 15, count 0 2006.285.13:41:47.05#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:41:47.05#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:41:47.05#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:41:47.05#ibcon#*before write, iclass 15, count 0 2006.285.13:41:47.05#ibcon#enter sib2, iclass 15, count 0 2006.285.13:41:47.05#ibcon#flushed, iclass 15, count 0 2006.285.13:41:47.05#ibcon#about to write, iclass 15, count 0 2006.285.13:41:47.05#ibcon#wrote, iclass 15, count 0 2006.285.13:41:47.05#ibcon#about to read 3, iclass 15, count 0 2006.285.13:41:47.09#ibcon#read 3, iclass 15, count 0 2006.285.13:41:47.09#ibcon#about to read 4, iclass 15, count 0 2006.285.13:41:47.09#ibcon#read 4, iclass 15, count 0 2006.285.13:41:47.09#ibcon#about to read 5, iclass 15, count 0 2006.285.13:41:47.09#ibcon#read 5, iclass 15, count 0 2006.285.13:41:47.09#ibcon#about to read 6, iclass 15, count 0 2006.285.13:41:47.09#ibcon#read 6, iclass 15, count 0 2006.285.13:41:47.09#ibcon#end of sib2, iclass 15, count 0 2006.285.13:41:47.09#ibcon#*after write, iclass 15, count 0 2006.285.13:41:47.09#ibcon#*before return 0, iclass 15, count 0 2006.285.13:41:47.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:41:47.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:41:47.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:41:47.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:41:47.09$vck44/va=4,6 2006.285.13:41:47.09#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.13:41:47.09#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.13:41:47.09#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:47.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:41:47.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:41:47.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:41:47.16#ibcon#enter wrdev, iclass 17, count 2 2006.285.13:41:47.16#ibcon#first serial, iclass 17, count 2 2006.285.13:41:47.16#ibcon#enter sib2, iclass 17, count 2 2006.285.13:41:47.16#ibcon#flushed, iclass 17, count 2 2006.285.13:41:47.16#ibcon#about to write, iclass 17, count 2 2006.285.13:41:47.16#ibcon#wrote, iclass 17, count 2 2006.285.13:41:47.16#ibcon#about to read 3, iclass 17, count 2 2006.285.13:41:47.18#ibcon#read 3, iclass 17, count 2 2006.285.13:41:47.18#ibcon#about to read 4, iclass 17, count 2 2006.285.13:41:47.18#ibcon#read 4, iclass 17, count 2 2006.285.13:41:47.18#ibcon#about to read 5, iclass 17, count 2 2006.285.13:41:47.18#ibcon#read 5, iclass 17, count 2 2006.285.13:41:47.18#ibcon#about to read 6, iclass 17, count 2 2006.285.13:41:47.18#ibcon#read 6, iclass 17, count 2 2006.285.13:41:47.18#ibcon#end of sib2, iclass 17, count 2 2006.285.13:41:47.18#ibcon#*mode == 0, iclass 17, count 2 2006.285.13:41:47.18#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.13:41:47.18#ibcon#[25=AT04-06\r\n] 2006.285.13:41:47.18#ibcon#*before write, iclass 17, count 2 2006.285.13:41:47.18#ibcon#enter sib2, iclass 17, count 2 2006.285.13:41:47.18#ibcon#flushed, iclass 17, count 2 2006.285.13:41:47.18#ibcon#about to write, iclass 17, count 2 2006.285.13:41:47.18#ibcon#wrote, iclass 17, count 2 2006.285.13:41:47.18#ibcon#about to read 3, iclass 17, count 2 2006.285.13:41:47.21#ibcon#read 3, iclass 17, count 2 2006.285.13:41:47.21#ibcon#about to read 4, iclass 17, count 2 2006.285.13:41:47.21#ibcon#read 4, iclass 17, count 2 2006.285.13:41:47.21#ibcon#about to read 5, iclass 17, count 2 2006.285.13:41:47.21#ibcon#read 5, iclass 17, count 2 2006.285.13:41:47.21#ibcon#about to read 6, iclass 17, count 2 2006.285.13:41:47.21#ibcon#read 6, iclass 17, count 2 2006.285.13:41:47.21#ibcon#end of sib2, iclass 17, count 2 2006.285.13:41:47.21#ibcon#*after write, iclass 17, count 2 2006.285.13:41:47.21#ibcon#*before return 0, iclass 17, count 2 2006.285.13:41:47.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:41:47.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:41:47.21#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.13:41:47.21#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:47.21#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:41:47.33#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:41:47.33#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:41:47.33#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:41:47.33#ibcon#first serial, iclass 17, count 0 2006.285.13:41:47.33#ibcon#enter sib2, iclass 17, count 0 2006.285.13:41:47.33#ibcon#flushed, iclass 17, count 0 2006.285.13:41:47.33#ibcon#about to write, iclass 17, count 0 2006.285.13:41:47.33#ibcon#wrote, iclass 17, count 0 2006.285.13:41:47.33#ibcon#about to read 3, iclass 17, count 0 2006.285.13:41:47.35#ibcon#read 3, iclass 17, count 0 2006.285.13:41:47.35#ibcon#about to read 4, iclass 17, count 0 2006.285.13:41:47.35#ibcon#read 4, iclass 17, count 0 2006.285.13:41:47.35#ibcon#about to read 5, iclass 17, count 0 2006.285.13:41:47.35#ibcon#read 5, iclass 17, count 0 2006.285.13:41:47.35#ibcon#about to read 6, iclass 17, count 0 2006.285.13:41:47.35#ibcon#read 6, iclass 17, count 0 2006.285.13:41:47.35#ibcon#end of sib2, iclass 17, count 0 2006.285.13:41:47.35#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:41:47.35#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:41:47.35#ibcon#[25=USB\r\n] 2006.285.13:41:47.35#ibcon#*before write, iclass 17, count 0 2006.285.13:41:47.35#ibcon#enter sib2, iclass 17, count 0 2006.285.13:41:47.35#ibcon#flushed, iclass 17, count 0 2006.285.13:41:47.35#ibcon#about to write, iclass 17, count 0 2006.285.13:41:47.35#ibcon#wrote, iclass 17, count 0 2006.285.13:41:47.35#ibcon#about to read 3, iclass 17, count 0 2006.285.13:41:47.38#ibcon#read 3, iclass 17, count 0 2006.285.13:41:47.38#ibcon#about to read 4, iclass 17, count 0 2006.285.13:41:47.38#ibcon#read 4, iclass 17, count 0 2006.285.13:41:47.38#ibcon#about to read 5, iclass 17, count 0 2006.285.13:41:47.38#ibcon#read 5, iclass 17, count 0 2006.285.13:41:47.38#ibcon#about to read 6, iclass 17, count 0 2006.285.13:41:47.38#ibcon#read 6, iclass 17, count 0 2006.285.13:41:47.38#ibcon#end of sib2, iclass 17, count 0 2006.285.13:41:47.38#ibcon#*after write, iclass 17, count 0 2006.285.13:41:47.38#ibcon#*before return 0, iclass 17, count 0 2006.285.13:41:47.38#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:41:47.38#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:41:47.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:41:47.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:41:47.38$vck44/valo=5,734.99 2006.285.13:41:47.38#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.13:41:47.38#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.13:41:47.38#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:47.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:41:47.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:41:47.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:41:47.38#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:41:47.38#ibcon#first serial, iclass 19, count 0 2006.285.13:41:47.38#ibcon#enter sib2, iclass 19, count 0 2006.285.13:41:47.39#ibcon#flushed, iclass 19, count 0 2006.285.13:41:47.39#ibcon#about to write, iclass 19, count 0 2006.285.13:41:47.39#ibcon#wrote, iclass 19, count 0 2006.285.13:41:47.39#ibcon#about to read 3, iclass 19, count 0 2006.285.13:41:47.40#ibcon#read 3, iclass 19, count 0 2006.285.13:41:47.40#ibcon#about to read 4, iclass 19, count 0 2006.285.13:41:47.40#ibcon#read 4, iclass 19, count 0 2006.285.13:41:47.40#ibcon#about to read 5, iclass 19, count 0 2006.285.13:41:47.40#ibcon#read 5, iclass 19, count 0 2006.285.13:41:47.40#ibcon#about to read 6, iclass 19, count 0 2006.285.13:41:47.40#ibcon#read 6, iclass 19, count 0 2006.285.13:41:47.40#ibcon#end of sib2, iclass 19, count 0 2006.285.13:41:47.40#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:41:47.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:41:47.40#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:41:47.40#ibcon#*before write, iclass 19, count 0 2006.285.13:41:47.40#ibcon#enter sib2, iclass 19, count 0 2006.285.13:41:47.40#ibcon#flushed, iclass 19, count 0 2006.285.13:41:47.40#ibcon#about to write, iclass 19, count 0 2006.285.13:41:47.40#ibcon#wrote, iclass 19, count 0 2006.285.13:41:47.40#ibcon#about to read 3, iclass 19, count 0 2006.285.13:41:47.44#ibcon#read 3, iclass 19, count 0 2006.285.13:41:47.44#ibcon#about to read 4, iclass 19, count 0 2006.285.13:41:47.44#ibcon#read 4, iclass 19, count 0 2006.285.13:41:47.44#ibcon#about to read 5, iclass 19, count 0 2006.285.13:41:47.44#ibcon#read 5, iclass 19, count 0 2006.285.13:41:47.44#ibcon#about to read 6, iclass 19, count 0 2006.285.13:41:47.44#ibcon#read 6, iclass 19, count 0 2006.285.13:41:47.44#ibcon#end of sib2, iclass 19, count 0 2006.285.13:41:47.44#ibcon#*after write, iclass 19, count 0 2006.285.13:41:47.44#ibcon#*before return 0, iclass 19, count 0 2006.285.13:41:47.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:41:47.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:41:47.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:41:47.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:41:47.44$vck44/va=5,3 2006.285.13:41:47.44#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.13:41:47.44#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.13:41:47.44#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:47.44#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:41:47.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:41:47.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:41:47.50#ibcon#enter wrdev, iclass 21, count 2 2006.285.13:41:47.50#ibcon#first serial, iclass 21, count 2 2006.285.13:41:47.50#ibcon#enter sib2, iclass 21, count 2 2006.285.13:41:47.50#ibcon#flushed, iclass 21, count 2 2006.285.13:41:47.50#ibcon#about to write, iclass 21, count 2 2006.285.13:41:47.50#ibcon#wrote, iclass 21, count 2 2006.285.13:41:47.50#ibcon#about to read 3, iclass 21, count 2 2006.285.13:41:47.52#ibcon#read 3, iclass 21, count 2 2006.285.13:41:47.52#ibcon#about to read 4, iclass 21, count 2 2006.285.13:41:47.52#ibcon#read 4, iclass 21, count 2 2006.285.13:41:47.52#ibcon#about to read 5, iclass 21, count 2 2006.285.13:41:47.52#ibcon#read 5, iclass 21, count 2 2006.285.13:41:47.52#ibcon#about to read 6, iclass 21, count 2 2006.285.13:41:47.52#ibcon#read 6, iclass 21, count 2 2006.285.13:41:47.52#ibcon#end of sib2, iclass 21, count 2 2006.285.13:41:47.52#ibcon#*mode == 0, iclass 21, count 2 2006.285.13:41:47.52#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.13:41:47.52#ibcon#[25=AT05-03\r\n] 2006.285.13:41:47.52#ibcon#*before write, iclass 21, count 2 2006.285.13:41:47.52#ibcon#enter sib2, iclass 21, count 2 2006.285.13:41:47.52#ibcon#flushed, iclass 21, count 2 2006.285.13:41:47.52#ibcon#about to write, iclass 21, count 2 2006.285.13:41:47.52#ibcon#wrote, iclass 21, count 2 2006.285.13:41:47.52#ibcon#about to read 3, iclass 21, count 2 2006.285.13:41:47.55#ibcon#read 3, iclass 21, count 2 2006.285.13:41:47.55#ibcon#about to read 4, iclass 21, count 2 2006.285.13:41:47.55#ibcon#read 4, iclass 21, count 2 2006.285.13:41:47.55#ibcon#about to read 5, iclass 21, count 2 2006.285.13:41:47.55#ibcon#read 5, iclass 21, count 2 2006.285.13:41:47.55#ibcon#about to read 6, iclass 21, count 2 2006.285.13:41:47.55#ibcon#read 6, iclass 21, count 2 2006.285.13:41:47.55#ibcon#end of sib2, iclass 21, count 2 2006.285.13:41:47.55#ibcon#*after write, iclass 21, count 2 2006.285.13:41:47.55#ibcon#*before return 0, iclass 21, count 2 2006.285.13:41:47.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:41:47.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:41:47.55#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.13:41:47.55#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:47.55#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:41:47.67#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:41:47.67#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:41:47.67#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:41:47.67#ibcon#first serial, iclass 21, count 0 2006.285.13:41:47.67#ibcon#enter sib2, iclass 21, count 0 2006.285.13:41:47.67#ibcon#flushed, iclass 21, count 0 2006.285.13:41:47.67#ibcon#about to write, iclass 21, count 0 2006.285.13:41:47.67#ibcon#wrote, iclass 21, count 0 2006.285.13:41:47.67#ibcon#about to read 3, iclass 21, count 0 2006.285.13:41:47.69#ibcon#read 3, iclass 21, count 0 2006.285.13:41:47.69#ibcon#about to read 4, iclass 21, count 0 2006.285.13:41:47.69#ibcon#read 4, iclass 21, count 0 2006.285.13:41:47.69#ibcon#about to read 5, iclass 21, count 0 2006.285.13:41:47.69#ibcon#read 5, iclass 21, count 0 2006.285.13:41:47.69#ibcon#about to read 6, iclass 21, count 0 2006.285.13:41:47.69#ibcon#read 6, iclass 21, count 0 2006.285.13:41:47.69#ibcon#end of sib2, iclass 21, count 0 2006.285.13:41:47.69#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:41:47.69#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:41:47.69#ibcon#[25=USB\r\n] 2006.285.13:41:47.69#ibcon#*before write, iclass 21, count 0 2006.285.13:41:47.69#ibcon#enter sib2, iclass 21, count 0 2006.285.13:41:47.69#ibcon#flushed, iclass 21, count 0 2006.285.13:41:47.69#ibcon#about to write, iclass 21, count 0 2006.285.13:41:47.69#ibcon#wrote, iclass 21, count 0 2006.285.13:41:47.69#ibcon#about to read 3, iclass 21, count 0 2006.285.13:41:47.72#ibcon#read 3, iclass 21, count 0 2006.285.13:41:47.72#ibcon#about to read 4, iclass 21, count 0 2006.285.13:41:47.72#ibcon#read 4, iclass 21, count 0 2006.285.13:41:47.72#ibcon#about to read 5, iclass 21, count 0 2006.285.13:41:47.72#ibcon#read 5, iclass 21, count 0 2006.285.13:41:47.72#ibcon#about to read 6, iclass 21, count 0 2006.285.13:41:47.72#ibcon#read 6, iclass 21, count 0 2006.285.13:41:47.72#ibcon#end of sib2, iclass 21, count 0 2006.285.13:41:47.72#ibcon#*after write, iclass 21, count 0 2006.285.13:41:47.72#ibcon#*before return 0, iclass 21, count 0 2006.285.13:41:47.72#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:41:47.72#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:41:47.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:41:47.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:41:47.72$vck44/valo=6,814.99 2006.285.13:41:47.72#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.13:41:47.72#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.13:41:47.72#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:47.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:41:47.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:41:47.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:41:47.72#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:41:47.72#ibcon#first serial, iclass 23, count 0 2006.285.13:41:47.72#ibcon#enter sib2, iclass 23, count 0 2006.285.13:41:47.72#ibcon#flushed, iclass 23, count 0 2006.285.13:41:47.72#ibcon#about to write, iclass 23, count 0 2006.285.13:41:47.72#ibcon#wrote, iclass 23, count 0 2006.285.13:41:47.72#ibcon#about to read 3, iclass 23, count 0 2006.285.13:41:47.74#ibcon#read 3, iclass 23, count 0 2006.285.13:41:47.74#ibcon#about to read 4, iclass 23, count 0 2006.285.13:41:47.74#ibcon#read 4, iclass 23, count 0 2006.285.13:41:47.74#ibcon#about to read 5, iclass 23, count 0 2006.285.13:41:47.74#ibcon#read 5, iclass 23, count 0 2006.285.13:41:47.74#ibcon#about to read 6, iclass 23, count 0 2006.285.13:41:47.74#ibcon#read 6, iclass 23, count 0 2006.285.13:41:47.74#ibcon#end of sib2, iclass 23, count 0 2006.285.13:41:47.74#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:41:47.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:41:47.74#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:41:47.74#ibcon#*before write, iclass 23, count 0 2006.285.13:41:47.74#ibcon#enter sib2, iclass 23, count 0 2006.285.13:41:47.74#ibcon#flushed, iclass 23, count 0 2006.285.13:41:47.74#ibcon#about to write, iclass 23, count 0 2006.285.13:41:47.74#ibcon#wrote, iclass 23, count 0 2006.285.13:41:47.74#ibcon#about to read 3, iclass 23, count 0 2006.285.13:41:47.78#ibcon#read 3, iclass 23, count 0 2006.285.13:41:47.78#ibcon#about to read 4, iclass 23, count 0 2006.285.13:41:47.78#ibcon#read 4, iclass 23, count 0 2006.285.13:41:47.78#ibcon#about to read 5, iclass 23, count 0 2006.285.13:41:47.78#ibcon#read 5, iclass 23, count 0 2006.285.13:41:47.78#ibcon#about to read 6, iclass 23, count 0 2006.285.13:41:47.78#ibcon#read 6, iclass 23, count 0 2006.285.13:41:47.78#ibcon#end of sib2, iclass 23, count 0 2006.285.13:41:47.78#ibcon#*after write, iclass 23, count 0 2006.285.13:41:47.78#ibcon#*before return 0, iclass 23, count 0 2006.285.13:41:47.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:41:47.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:41:47.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:41:47.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:41:47.78$vck44/va=6,4 2006.285.13:41:47.78#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.13:41:47.78#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.13:41:47.78#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:47.78#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:41:47.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:41:47.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:41:47.84#ibcon#enter wrdev, iclass 25, count 2 2006.285.13:41:47.84#ibcon#first serial, iclass 25, count 2 2006.285.13:41:47.84#ibcon#enter sib2, iclass 25, count 2 2006.285.13:41:47.84#ibcon#flushed, iclass 25, count 2 2006.285.13:41:47.84#ibcon#about to write, iclass 25, count 2 2006.285.13:41:47.84#ibcon#wrote, iclass 25, count 2 2006.285.13:41:47.84#ibcon#about to read 3, iclass 25, count 2 2006.285.13:41:47.86#ibcon#read 3, iclass 25, count 2 2006.285.13:41:47.86#ibcon#about to read 4, iclass 25, count 2 2006.285.13:41:47.86#ibcon#read 4, iclass 25, count 2 2006.285.13:41:47.86#ibcon#about to read 5, iclass 25, count 2 2006.285.13:41:47.86#ibcon#read 5, iclass 25, count 2 2006.285.13:41:47.86#ibcon#about to read 6, iclass 25, count 2 2006.285.13:41:47.86#ibcon#read 6, iclass 25, count 2 2006.285.13:41:47.86#ibcon#end of sib2, iclass 25, count 2 2006.285.13:41:47.86#ibcon#*mode == 0, iclass 25, count 2 2006.285.13:41:47.86#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.13:41:47.86#ibcon#[25=AT06-04\r\n] 2006.285.13:41:47.86#ibcon#*before write, iclass 25, count 2 2006.285.13:41:47.86#ibcon#enter sib2, iclass 25, count 2 2006.285.13:41:47.86#ibcon#flushed, iclass 25, count 2 2006.285.13:41:47.86#ibcon#about to write, iclass 25, count 2 2006.285.13:41:47.86#ibcon#wrote, iclass 25, count 2 2006.285.13:41:47.86#ibcon#about to read 3, iclass 25, count 2 2006.285.13:41:47.89#ibcon#read 3, iclass 25, count 2 2006.285.13:41:47.89#ibcon#about to read 4, iclass 25, count 2 2006.285.13:41:47.89#ibcon#read 4, iclass 25, count 2 2006.285.13:41:47.89#ibcon#about to read 5, iclass 25, count 2 2006.285.13:41:47.89#ibcon#read 5, iclass 25, count 2 2006.285.13:41:47.89#ibcon#about to read 6, iclass 25, count 2 2006.285.13:41:47.89#ibcon#read 6, iclass 25, count 2 2006.285.13:41:47.89#ibcon#end of sib2, iclass 25, count 2 2006.285.13:41:47.89#ibcon#*after write, iclass 25, count 2 2006.285.13:41:47.89#ibcon#*before return 0, iclass 25, count 2 2006.285.13:41:47.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:41:47.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:41:47.89#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.13:41:47.89#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:47.89#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:41:48.01#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:41:48.01#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:41:48.01#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:41:48.01#ibcon#first serial, iclass 25, count 0 2006.285.13:41:48.01#ibcon#enter sib2, iclass 25, count 0 2006.285.13:41:48.01#ibcon#flushed, iclass 25, count 0 2006.285.13:41:48.01#ibcon#about to write, iclass 25, count 0 2006.285.13:41:48.01#ibcon#wrote, iclass 25, count 0 2006.285.13:41:48.01#ibcon#about to read 3, iclass 25, count 0 2006.285.13:41:48.03#ibcon#read 3, iclass 25, count 0 2006.285.13:41:48.03#ibcon#about to read 4, iclass 25, count 0 2006.285.13:41:48.03#ibcon#read 4, iclass 25, count 0 2006.285.13:41:48.03#ibcon#about to read 5, iclass 25, count 0 2006.285.13:41:48.03#ibcon#read 5, iclass 25, count 0 2006.285.13:41:48.03#ibcon#about to read 6, iclass 25, count 0 2006.285.13:41:48.03#ibcon#read 6, iclass 25, count 0 2006.285.13:41:48.03#ibcon#end of sib2, iclass 25, count 0 2006.285.13:41:48.03#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:41:48.03#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:41:48.03#ibcon#[25=USB\r\n] 2006.285.13:41:48.03#ibcon#*before write, iclass 25, count 0 2006.285.13:41:48.03#ibcon#enter sib2, iclass 25, count 0 2006.285.13:41:48.03#ibcon#flushed, iclass 25, count 0 2006.285.13:41:48.03#ibcon#about to write, iclass 25, count 0 2006.285.13:41:48.03#ibcon#wrote, iclass 25, count 0 2006.285.13:41:48.03#ibcon#about to read 3, iclass 25, count 0 2006.285.13:41:48.06#ibcon#read 3, iclass 25, count 0 2006.285.13:41:48.06#ibcon#about to read 4, iclass 25, count 0 2006.285.13:41:48.06#ibcon#read 4, iclass 25, count 0 2006.285.13:41:48.06#ibcon#about to read 5, iclass 25, count 0 2006.285.13:41:48.06#ibcon#read 5, iclass 25, count 0 2006.285.13:41:48.06#ibcon#about to read 6, iclass 25, count 0 2006.285.13:41:48.06#ibcon#read 6, iclass 25, count 0 2006.285.13:41:48.06#ibcon#end of sib2, iclass 25, count 0 2006.285.13:41:48.06#ibcon#*after write, iclass 25, count 0 2006.285.13:41:48.06#ibcon#*before return 0, iclass 25, count 0 2006.285.13:41:48.06#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:41:48.06#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:41:48.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:41:48.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:41:48.06$vck44/valo=7,864.99 2006.285.13:41:48.06#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.13:41:48.06#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.13:41:48.06#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:48.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:41:48.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:41:48.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:41:48.06#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:41:48.06#ibcon#first serial, iclass 27, count 0 2006.285.13:41:48.06#ibcon#enter sib2, iclass 27, count 0 2006.285.13:41:48.06#ibcon#flushed, iclass 27, count 0 2006.285.13:41:48.06#ibcon#about to write, iclass 27, count 0 2006.285.13:41:48.06#ibcon#wrote, iclass 27, count 0 2006.285.13:41:48.06#ibcon#about to read 3, iclass 27, count 0 2006.285.13:41:48.20#ibcon#read 3, iclass 27, count 0 2006.285.13:41:48.20#ibcon#about to read 4, iclass 27, count 0 2006.285.13:41:48.20#ibcon#read 4, iclass 27, count 0 2006.285.13:41:48.20#ibcon#about to read 5, iclass 27, count 0 2006.285.13:41:48.20#ibcon#read 5, iclass 27, count 0 2006.285.13:41:48.20#ibcon#about to read 6, iclass 27, count 0 2006.285.13:41:48.20#ibcon#read 6, iclass 27, count 0 2006.285.13:41:48.20#ibcon#end of sib2, iclass 27, count 0 2006.285.13:41:48.20#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:41:48.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:41:48.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:41:48.20#ibcon#*before write, iclass 27, count 0 2006.285.13:41:48.20#ibcon#enter sib2, iclass 27, count 0 2006.285.13:41:48.20#ibcon#flushed, iclass 27, count 0 2006.285.13:41:48.20#ibcon#about to write, iclass 27, count 0 2006.285.13:41:48.20#ibcon#wrote, iclass 27, count 0 2006.285.13:41:48.20#ibcon#about to read 3, iclass 27, count 0 2006.285.13:41:48.24#ibcon#read 3, iclass 27, count 0 2006.285.13:41:48.24#ibcon#about to read 4, iclass 27, count 0 2006.285.13:41:48.24#ibcon#read 4, iclass 27, count 0 2006.285.13:41:48.24#ibcon#about to read 5, iclass 27, count 0 2006.285.13:41:48.24#ibcon#read 5, iclass 27, count 0 2006.285.13:41:48.24#ibcon#about to read 6, iclass 27, count 0 2006.285.13:41:48.24#ibcon#read 6, iclass 27, count 0 2006.285.13:41:48.24#ibcon#end of sib2, iclass 27, count 0 2006.285.13:41:48.24#ibcon#*after write, iclass 27, count 0 2006.285.13:41:48.24#ibcon#*before return 0, iclass 27, count 0 2006.285.13:41:48.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:41:48.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:41:48.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:41:48.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:41:48.24$vck44/va=7,4 2006.285.13:41:48.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.13:41:48.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.13:41:48.24#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:48.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:41:48.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:41:48.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:41:48.24#ibcon#enter wrdev, iclass 29, count 2 2006.285.13:41:48.24#ibcon#first serial, iclass 29, count 2 2006.285.13:41:48.24#ibcon#enter sib2, iclass 29, count 2 2006.285.13:41:48.24#ibcon#flushed, iclass 29, count 2 2006.285.13:41:48.24#ibcon#about to write, iclass 29, count 2 2006.285.13:41:48.24#ibcon#wrote, iclass 29, count 2 2006.285.13:41:48.24#ibcon#about to read 3, iclass 29, count 2 2006.285.13:41:48.26#ibcon#read 3, iclass 29, count 2 2006.285.13:41:48.26#ibcon#about to read 4, iclass 29, count 2 2006.285.13:41:48.26#ibcon#read 4, iclass 29, count 2 2006.285.13:41:48.26#ibcon#about to read 5, iclass 29, count 2 2006.285.13:41:48.26#ibcon#read 5, iclass 29, count 2 2006.285.13:41:48.26#ibcon#about to read 6, iclass 29, count 2 2006.285.13:41:48.26#ibcon#read 6, iclass 29, count 2 2006.285.13:41:48.26#ibcon#end of sib2, iclass 29, count 2 2006.285.13:41:48.26#ibcon#*mode == 0, iclass 29, count 2 2006.285.13:41:48.26#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.13:41:48.26#ibcon#[25=AT07-04\r\n] 2006.285.13:41:48.26#ibcon#*before write, iclass 29, count 2 2006.285.13:41:48.26#ibcon#enter sib2, iclass 29, count 2 2006.285.13:41:48.26#ibcon#flushed, iclass 29, count 2 2006.285.13:41:48.26#ibcon#about to write, iclass 29, count 2 2006.285.13:41:48.26#ibcon#wrote, iclass 29, count 2 2006.285.13:41:48.26#ibcon#about to read 3, iclass 29, count 2 2006.285.13:41:48.29#ibcon#read 3, iclass 29, count 2 2006.285.13:41:48.29#ibcon#about to read 4, iclass 29, count 2 2006.285.13:41:48.29#ibcon#read 4, iclass 29, count 2 2006.285.13:41:48.29#ibcon#about to read 5, iclass 29, count 2 2006.285.13:41:48.29#ibcon#read 5, iclass 29, count 2 2006.285.13:41:48.29#ibcon#about to read 6, iclass 29, count 2 2006.285.13:41:48.29#ibcon#read 6, iclass 29, count 2 2006.285.13:41:48.29#ibcon#end of sib2, iclass 29, count 2 2006.285.13:41:48.29#ibcon#*after write, iclass 29, count 2 2006.285.13:41:48.29#ibcon#*before return 0, iclass 29, count 2 2006.285.13:41:48.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:41:48.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:41:48.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.13:41:48.29#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:48.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:41:48.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:41:48.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:41:48.41#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:41:48.41#ibcon#first serial, iclass 29, count 0 2006.285.13:41:48.41#ibcon#enter sib2, iclass 29, count 0 2006.285.13:41:48.41#ibcon#flushed, iclass 29, count 0 2006.285.13:41:48.41#ibcon#about to write, iclass 29, count 0 2006.285.13:41:48.41#ibcon#wrote, iclass 29, count 0 2006.285.13:41:48.41#ibcon#about to read 3, iclass 29, count 0 2006.285.13:41:48.43#ibcon#read 3, iclass 29, count 0 2006.285.13:41:48.43#ibcon#about to read 4, iclass 29, count 0 2006.285.13:41:48.43#ibcon#read 4, iclass 29, count 0 2006.285.13:41:48.43#ibcon#about to read 5, iclass 29, count 0 2006.285.13:41:48.43#ibcon#read 5, iclass 29, count 0 2006.285.13:41:48.43#ibcon#about to read 6, iclass 29, count 0 2006.285.13:41:48.43#ibcon#read 6, iclass 29, count 0 2006.285.13:41:48.43#ibcon#end of sib2, iclass 29, count 0 2006.285.13:41:48.43#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:41:48.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:41:48.43#ibcon#[25=USB\r\n] 2006.285.13:41:48.43#ibcon#*before write, iclass 29, count 0 2006.285.13:41:48.43#ibcon#enter sib2, iclass 29, count 0 2006.285.13:41:48.43#ibcon#flushed, iclass 29, count 0 2006.285.13:41:48.43#ibcon#about to write, iclass 29, count 0 2006.285.13:41:48.43#ibcon#wrote, iclass 29, count 0 2006.285.13:41:48.43#ibcon#about to read 3, iclass 29, count 0 2006.285.13:41:48.46#ibcon#read 3, iclass 29, count 0 2006.285.13:41:48.46#ibcon#about to read 4, iclass 29, count 0 2006.285.13:41:48.46#ibcon#read 4, iclass 29, count 0 2006.285.13:41:48.46#ibcon#about to read 5, iclass 29, count 0 2006.285.13:41:48.46#ibcon#read 5, iclass 29, count 0 2006.285.13:41:48.46#ibcon#about to read 6, iclass 29, count 0 2006.285.13:41:48.46#ibcon#read 6, iclass 29, count 0 2006.285.13:41:48.46#ibcon#end of sib2, iclass 29, count 0 2006.285.13:41:48.46#ibcon#*after write, iclass 29, count 0 2006.285.13:41:48.46#ibcon#*before return 0, iclass 29, count 0 2006.285.13:41:48.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:41:48.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:41:48.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:41:48.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:41:48.46$vck44/valo=8,884.99 2006.285.13:41:48.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.13:41:48.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.13:41:48.46#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:48.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:41:48.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:41:48.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:41:48.46#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:41:48.46#ibcon#first serial, iclass 31, count 0 2006.285.13:41:48.46#ibcon#enter sib2, iclass 31, count 0 2006.285.13:41:48.46#ibcon#flushed, iclass 31, count 0 2006.285.13:41:48.46#ibcon#about to write, iclass 31, count 0 2006.285.13:41:48.46#ibcon#wrote, iclass 31, count 0 2006.285.13:41:48.46#ibcon#about to read 3, iclass 31, count 0 2006.285.13:41:48.48#ibcon#read 3, iclass 31, count 0 2006.285.13:41:48.48#ibcon#about to read 4, iclass 31, count 0 2006.285.13:41:48.48#ibcon#read 4, iclass 31, count 0 2006.285.13:41:48.48#ibcon#about to read 5, iclass 31, count 0 2006.285.13:41:48.48#ibcon#read 5, iclass 31, count 0 2006.285.13:41:48.48#ibcon#about to read 6, iclass 31, count 0 2006.285.13:41:48.48#ibcon#read 6, iclass 31, count 0 2006.285.13:41:48.48#ibcon#end of sib2, iclass 31, count 0 2006.285.13:41:48.48#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:41:48.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:41:48.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:41:48.48#ibcon#*before write, iclass 31, count 0 2006.285.13:41:48.48#ibcon#enter sib2, iclass 31, count 0 2006.285.13:41:48.48#ibcon#flushed, iclass 31, count 0 2006.285.13:41:48.48#ibcon#about to write, iclass 31, count 0 2006.285.13:41:48.48#ibcon#wrote, iclass 31, count 0 2006.285.13:41:48.48#ibcon#about to read 3, iclass 31, count 0 2006.285.13:41:48.52#ibcon#read 3, iclass 31, count 0 2006.285.13:41:48.52#ibcon#about to read 4, iclass 31, count 0 2006.285.13:41:48.52#ibcon#read 4, iclass 31, count 0 2006.285.13:41:48.52#ibcon#about to read 5, iclass 31, count 0 2006.285.13:41:48.52#ibcon#read 5, iclass 31, count 0 2006.285.13:41:48.52#ibcon#about to read 6, iclass 31, count 0 2006.285.13:41:48.52#ibcon#read 6, iclass 31, count 0 2006.285.13:41:48.52#ibcon#end of sib2, iclass 31, count 0 2006.285.13:41:48.52#ibcon#*after write, iclass 31, count 0 2006.285.13:41:48.52#ibcon#*before return 0, iclass 31, count 0 2006.285.13:41:48.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:41:48.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:41:48.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:41:48.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:41:48.52$vck44/va=8,3 2006.285.13:41:48.52#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.13:41:48.52#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.13:41:48.52#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:48.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:41:48.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:41:48.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:41:48.58#ibcon#enter wrdev, iclass 33, count 2 2006.285.13:41:48.58#ibcon#first serial, iclass 33, count 2 2006.285.13:41:48.58#ibcon#enter sib2, iclass 33, count 2 2006.285.13:41:48.58#ibcon#flushed, iclass 33, count 2 2006.285.13:41:48.58#ibcon#about to write, iclass 33, count 2 2006.285.13:41:48.58#ibcon#wrote, iclass 33, count 2 2006.285.13:41:48.58#ibcon#about to read 3, iclass 33, count 2 2006.285.13:41:48.60#ibcon#read 3, iclass 33, count 2 2006.285.13:41:48.60#ibcon#about to read 4, iclass 33, count 2 2006.285.13:41:48.60#ibcon#read 4, iclass 33, count 2 2006.285.13:41:48.60#ibcon#about to read 5, iclass 33, count 2 2006.285.13:41:48.60#ibcon#read 5, iclass 33, count 2 2006.285.13:41:48.60#ibcon#about to read 6, iclass 33, count 2 2006.285.13:41:48.60#ibcon#read 6, iclass 33, count 2 2006.285.13:41:48.60#ibcon#end of sib2, iclass 33, count 2 2006.285.13:41:48.60#ibcon#*mode == 0, iclass 33, count 2 2006.285.13:41:48.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.13:41:48.60#ibcon#[25=AT08-03\r\n] 2006.285.13:41:48.60#ibcon#*before write, iclass 33, count 2 2006.285.13:41:48.60#ibcon#enter sib2, iclass 33, count 2 2006.285.13:41:48.60#ibcon#flushed, iclass 33, count 2 2006.285.13:41:48.60#ibcon#about to write, iclass 33, count 2 2006.285.13:41:48.60#ibcon#wrote, iclass 33, count 2 2006.285.13:41:48.60#ibcon#about to read 3, iclass 33, count 2 2006.285.13:41:48.63#ibcon#read 3, iclass 33, count 2 2006.285.13:41:48.63#ibcon#about to read 4, iclass 33, count 2 2006.285.13:41:48.63#ibcon#read 4, iclass 33, count 2 2006.285.13:41:48.63#ibcon#about to read 5, iclass 33, count 2 2006.285.13:41:48.63#ibcon#read 5, iclass 33, count 2 2006.285.13:41:48.63#ibcon#about to read 6, iclass 33, count 2 2006.285.13:41:48.63#ibcon#read 6, iclass 33, count 2 2006.285.13:41:48.63#ibcon#end of sib2, iclass 33, count 2 2006.285.13:41:48.63#ibcon#*after write, iclass 33, count 2 2006.285.13:41:48.63#ibcon#*before return 0, iclass 33, count 2 2006.285.13:41:48.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:41:48.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:41:48.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.13:41:48.63#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:48.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:41:48.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:41:48.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:41:48.75#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:41:48.75#ibcon#first serial, iclass 33, count 0 2006.285.13:41:48.75#ibcon#enter sib2, iclass 33, count 0 2006.285.13:41:48.75#ibcon#flushed, iclass 33, count 0 2006.285.13:41:48.75#ibcon#about to write, iclass 33, count 0 2006.285.13:41:48.75#ibcon#wrote, iclass 33, count 0 2006.285.13:41:48.75#ibcon#about to read 3, iclass 33, count 0 2006.285.13:41:48.77#ibcon#read 3, iclass 33, count 0 2006.285.13:41:48.77#ibcon#about to read 4, iclass 33, count 0 2006.285.13:41:48.77#ibcon#read 4, iclass 33, count 0 2006.285.13:41:48.77#ibcon#about to read 5, iclass 33, count 0 2006.285.13:41:48.77#ibcon#read 5, iclass 33, count 0 2006.285.13:41:48.77#ibcon#about to read 6, iclass 33, count 0 2006.285.13:41:48.77#ibcon#read 6, iclass 33, count 0 2006.285.13:41:48.77#ibcon#end of sib2, iclass 33, count 0 2006.285.13:41:48.77#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:41:48.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:41:48.77#ibcon#[25=USB\r\n] 2006.285.13:41:48.77#ibcon#*before write, iclass 33, count 0 2006.285.13:41:48.77#ibcon#enter sib2, iclass 33, count 0 2006.285.13:41:48.77#ibcon#flushed, iclass 33, count 0 2006.285.13:41:48.77#ibcon#about to write, iclass 33, count 0 2006.285.13:41:48.77#ibcon#wrote, iclass 33, count 0 2006.285.13:41:48.77#ibcon#about to read 3, iclass 33, count 0 2006.285.13:41:48.80#ibcon#read 3, iclass 33, count 0 2006.285.13:41:48.80#ibcon#about to read 4, iclass 33, count 0 2006.285.13:41:48.80#ibcon#read 4, iclass 33, count 0 2006.285.13:41:48.80#ibcon#about to read 5, iclass 33, count 0 2006.285.13:41:48.80#ibcon#read 5, iclass 33, count 0 2006.285.13:41:48.80#ibcon#about to read 6, iclass 33, count 0 2006.285.13:41:48.80#ibcon#read 6, iclass 33, count 0 2006.285.13:41:48.80#ibcon#end of sib2, iclass 33, count 0 2006.285.13:41:48.80#ibcon#*after write, iclass 33, count 0 2006.285.13:41:48.80#ibcon#*before return 0, iclass 33, count 0 2006.285.13:41:48.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:41:48.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:41:48.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:41:48.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:41:48.80$vck44/vblo=1,629.99 2006.285.13:41:48.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.13:41:48.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.13:41:48.80#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:48.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:41:48.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:41:48.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:41:48.80#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:41:48.80#ibcon#first serial, iclass 35, count 0 2006.285.13:41:48.80#ibcon#enter sib2, iclass 35, count 0 2006.285.13:41:48.80#ibcon#flushed, iclass 35, count 0 2006.285.13:41:48.80#ibcon#about to write, iclass 35, count 0 2006.285.13:41:48.80#ibcon#wrote, iclass 35, count 0 2006.285.13:41:48.80#ibcon#about to read 3, iclass 35, count 0 2006.285.13:41:48.82#ibcon#read 3, iclass 35, count 0 2006.285.13:41:48.82#ibcon#about to read 4, iclass 35, count 0 2006.285.13:41:48.82#ibcon#read 4, iclass 35, count 0 2006.285.13:41:48.82#ibcon#about to read 5, iclass 35, count 0 2006.285.13:41:48.82#ibcon#read 5, iclass 35, count 0 2006.285.13:41:48.82#ibcon#about to read 6, iclass 35, count 0 2006.285.13:41:48.82#ibcon#read 6, iclass 35, count 0 2006.285.13:41:48.82#ibcon#end of sib2, iclass 35, count 0 2006.285.13:41:48.82#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:41:48.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:41:48.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:41:48.82#ibcon#*before write, iclass 35, count 0 2006.285.13:41:48.82#ibcon#enter sib2, iclass 35, count 0 2006.285.13:41:48.82#ibcon#flushed, iclass 35, count 0 2006.285.13:41:48.82#ibcon#about to write, iclass 35, count 0 2006.285.13:41:48.82#ibcon#wrote, iclass 35, count 0 2006.285.13:41:48.82#ibcon#about to read 3, iclass 35, count 0 2006.285.13:41:48.86#ibcon#read 3, iclass 35, count 0 2006.285.13:41:48.86#ibcon#about to read 4, iclass 35, count 0 2006.285.13:41:48.86#ibcon#read 4, iclass 35, count 0 2006.285.13:41:48.86#ibcon#about to read 5, iclass 35, count 0 2006.285.13:41:48.86#ibcon#read 5, iclass 35, count 0 2006.285.13:41:48.86#ibcon#about to read 6, iclass 35, count 0 2006.285.13:41:48.86#ibcon#read 6, iclass 35, count 0 2006.285.13:41:48.86#ibcon#end of sib2, iclass 35, count 0 2006.285.13:41:48.86#ibcon#*after write, iclass 35, count 0 2006.285.13:41:48.86#ibcon#*before return 0, iclass 35, count 0 2006.285.13:41:48.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:41:48.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:41:48.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:41:48.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:41:48.86$vck44/vb=1,4 2006.285.13:41:48.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.13:41:48.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.13:41:48.86#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:48.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:41:48.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:41:48.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:41:48.86#ibcon#enter wrdev, iclass 37, count 2 2006.285.13:41:48.86#ibcon#first serial, iclass 37, count 2 2006.285.13:41:48.86#ibcon#enter sib2, iclass 37, count 2 2006.285.13:41:48.86#ibcon#flushed, iclass 37, count 2 2006.285.13:41:48.86#ibcon#about to write, iclass 37, count 2 2006.285.13:41:48.86#ibcon#wrote, iclass 37, count 2 2006.285.13:41:48.86#ibcon#about to read 3, iclass 37, count 2 2006.285.13:41:48.88#ibcon#read 3, iclass 37, count 2 2006.285.13:41:48.88#ibcon#about to read 4, iclass 37, count 2 2006.285.13:41:48.88#ibcon#read 4, iclass 37, count 2 2006.285.13:41:48.88#ibcon#about to read 5, iclass 37, count 2 2006.285.13:41:48.88#ibcon#read 5, iclass 37, count 2 2006.285.13:41:48.88#ibcon#about to read 6, iclass 37, count 2 2006.285.13:41:48.88#ibcon#read 6, iclass 37, count 2 2006.285.13:41:48.88#ibcon#end of sib2, iclass 37, count 2 2006.285.13:41:48.88#ibcon#*mode == 0, iclass 37, count 2 2006.285.13:41:48.88#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.13:41:48.88#ibcon#[27=AT01-04\r\n] 2006.285.13:41:48.88#ibcon#*before write, iclass 37, count 2 2006.285.13:41:48.88#ibcon#enter sib2, iclass 37, count 2 2006.285.13:41:48.88#ibcon#flushed, iclass 37, count 2 2006.285.13:41:48.88#ibcon#about to write, iclass 37, count 2 2006.285.13:41:48.88#ibcon#wrote, iclass 37, count 2 2006.285.13:41:48.88#ibcon#about to read 3, iclass 37, count 2 2006.285.13:41:48.91#ibcon#read 3, iclass 37, count 2 2006.285.13:41:48.91#ibcon#about to read 4, iclass 37, count 2 2006.285.13:41:48.91#ibcon#read 4, iclass 37, count 2 2006.285.13:41:48.91#ibcon#about to read 5, iclass 37, count 2 2006.285.13:41:48.91#ibcon#read 5, iclass 37, count 2 2006.285.13:41:48.91#ibcon#about to read 6, iclass 37, count 2 2006.285.13:41:48.91#ibcon#read 6, iclass 37, count 2 2006.285.13:41:48.91#ibcon#end of sib2, iclass 37, count 2 2006.285.13:41:48.91#ibcon#*after write, iclass 37, count 2 2006.285.13:41:48.91#ibcon#*before return 0, iclass 37, count 2 2006.285.13:41:48.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:41:48.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:41:48.91#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.13:41:48.91#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:48.91#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:41:49.03#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:41:49.03#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:41:49.03#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:41:49.03#ibcon#first serial, iclass 37, count 0 2006.285.13:41:49.03#ibcon#enter sib2, iclass 37, count 0 2006.285.13:41:49.03#ibcon#flushed, iclass 37, count 0 2006.285.13:41:49.03#ibcon#about to write, iclass 37, count 0 2006.285.13:41:49.03#ibcon#wrote, iclass 37, count 0 2006.285.13:41:49.03#ibcon#about to read 3, iclass 37, count 0 2006.285.13:41:49.05#ibcon#read 3, iclass 37, count 0 2006.285.13:41:49.05#ibcon#about to read 4, iclass 37, count 0 2006.285.13:41:49.05#ibcon#read 4, iclass 37, count 0 2006.285.13:41:49.05#ibcon#about to read 5, iclass 37, count 0 2006.285.13:41:49.05#ibcon#read 5, iclass 37, count 0 2006.285.13:41:49.05#ibcon#about to read 6, iclass 37, count 0 2006.285.13:41:49.05#ibcon#read 6, iclass 37, count 0 2006.285.13:41:49.05#ibcon#end of sib2, iclass 37, count 0 2006.285.13:41:49.05#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:41:49.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:41:49.05#ibcon#[27=USB\r\n] 2006.285.13:41:49.05#ibcon#*before write, iclass 37, count 0 2006.285.13:41:49.05#ibcon#enter sib2, iclass 37, count 0 2006.285.13:41:49.05#ibcon#flushed, iclass 37, count 0 2006.285.13:41:49.05#ibcon#about to write, iclass 37, count 0 2006.285.13:41:49.05#ibcon#wrote, iclass 37, count 0 2006.285.13:41:49.05#ibcon#about to read 3, iclass 37, count 0 2006.285.13:41:49.08#ibcon#read 3, iclass 37, count 0 2006.285.13:41:49.08#ibcon#about to read 4, iclass 37, count 0 2006.285.13:41:49.08#ibcon#read 4, iclass 37, count 0 2006.285.13:41:49.08#ibcon#about to read 5, iclass 37, count 0 2006.285.13:41:49.08#ibcon#read 5, iclass 37, count 0 2006.285.13:41:49.08#ibcon#about to read 6, iclass 37, count 0 2006.285.13:41:49.08#ibcon#read 6, iclass 37, count 0 2006.285.13:41:49.08#ibcon#end of sib2, iclass 37, count 0 2006.285.13:41:49.08#ibcon#*after write, iclass 37, count 0 2006.285.13:41:49.08#ibcon#*before return 0, iclass 37, count 0 2006.285.13:41:49.08#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:41:49.08#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:41:49.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:41:49.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:41:49.08$vck44/vblo=2,634.99 2006.285.13:41:49.08#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.13:41:49.08#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.13:41:49.08#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:49.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:41:49.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:41:49.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:41:49.08#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:41:49.08#ibcon#first serial, iclass 39, count 0 2006.285.13:41:49.08#ibcon#enter sib2, iclass 39, count 0 2006.285.13:41:49.08#ibcon#flushed, iclass 39, count 0 2006.285.13:41:49.08#ibcon#about to write, iclass 39, count 0 2006.285.13:41:49.08#ibcon#wrote, iclass 39, count 0 2006.285.13:41:49.08#ibcon#about to read 3, iclass 39, count 0 2006.285.13:41:49.10#ibcon#read 3, iclass 39, count 0 2006.285.13:41:49.28#ibcon#about to read 4, iclass 39, count 0 2006.285.13:41:49.28#ibcon#read 4, iclass 39, count 0 2006.285.13:41:49.28#ibcon#about to read 5, iclass 39, count 0 2006.285.13:41:49.28#ibcon#read 5, iclass 39, count 0 2006.285.13:41:49.28#ibcon#about to read 6, iclass 39, count 0 2006.285.13:41:49.28#ibcon#read 6, iclass 39, count 0 2006.285.13:41:49.28#ibcon#end of sib2, iclass 39, count 0 2006.285.13:41:49.28#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:41:49.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:41:49.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:41:49.28#ibcon#*before write, iclass 39, count 0 2006.285.13:41:49.28#ibcon#enter sib2, iclass 39, count 0 2006.285.13:41:49.28#ibcon#flushed, iclass 39, count 0 2006.285.13:41:49.28#ibcon#about to write, iclass 39, count 0 2006.285.13:41:49.28#ibcon#wrote, iclass 39, count 0 2006.285.13:41:49.28#ibcon#about to read 3, iclass 39, count 0 2006.285.13:41:49.32#ibcon#read 3, iclass 39, count 0 2006.285.13:41:49.32#ibcon#about to read 4, iclass 39, count 0 2006.285.13:41:49.32#ibcon#read 4, iclass 39, count 0 2006.285.13:41:49.32#ibcon#about to read 5, iclass 39, count 0 2006.285.13:41:49.32#ibcon#read 5, iclass 39, count 0 2006.285.13:41:49.32#ibcon#about to read 6, iclass 39, count 0 2006.285.13:41:49.32#ibcon#read 6, iclass 39, count 0 2006.285.13:41:49.32#ibcon#end of sib2, iclass 39, count 0 2006.285.13:41:49.32#ibcon#*after write, iclass 39, count 0 2006.285.13:41:49.32#ibcon#*before return 0, iclass 39, count 0 2006.285.13:41:49.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:41:49.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:41:49.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:41:49.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:41:49.32$vck44/vb=2,5 2006.285.13:41:49.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.13:41:49.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.13:41:49.32#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:49.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:41:49.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:41:49.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:41:49.32#ibcon#enter wrdev, iclass 3, count 2 2006.285.13:41:49.32#ibcon#first serial, iclass 3, count 2 2006.285.13:41:49.32#ibcon#enter sib2, iclass 3, count 2 2006.285.13:41:49.32#ibcon#flushed, iclass 3, count 2 2006.285.13:41:49.32#ibcon#about to write, iclass 3, count 2 2006.285.13:41:49.32#ibcon#wrote, iclass 3, count 2 2006.285.13:41:49.32#ibcon#about to read 3, iclass 3, count 2 2006.285.13:41:49.34#ibcon#read 3, iclass 3, count 2 2006.285.13:41:49.34#ibcon#about to read 4, iclass 3, count 2 2006.285.13:41:49.34#ibcon#read 4, iclass 3, count 2 2006.285.13:41:49.34#ibcon#about to read 5, iclass 3, count 2 2006.285.13:41:49.34#ibcon#read 5, iclass 3, count 2 2006.285.13:41:49.34#ibcon#about to read 6, iclass 3, count 2 2006.285.13:41:49.34#ibcon#read 6, iclass 3, count 2 2006.285.13:41:49.34#ibcon#end of sib2, iclass 3, count 2 2006.285.13:41:49.34#ibcon#*mode == 0, iclass 3, count 2 2006.285.13:41:49.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.13:41:49.34#ibcon#[27=AT02-05\r\n] 2006.285.13:41:49.34#ibcon#*before write, iclass 3, count 2 2006.285.13:41:49.34#ibcon#enter sib2, iclass 3, count 2 2006.285.13:41:49.34#ibcon#flushed, iclass 3, count 2 2006.285.13:41:49.34#ibcon#about to write, iclass 3, count 2 2006.285.13:41:49.34#ibcon#wrote, iclass 3, count 2 2006.285.13:41:49.34#ibcon#about to read 3, iclass 3, count 2 2006.285.13:41:49.37#ibcon#read 3, iclass 3, count 2 2006.285.13:41:49.37#ibcon#about to read 4, iclass 3, count 2 2006.285.13:41:49.37#ibcon#read 4, iclass 3, count 2 2006.285.13:41:49.37#ibcon#about to read 5, iclass 3, count 2 2006.285.13:41:49.37#ibcon#read 5, iclass 3, count 2 2006.285.13:41:49.37#ibcon#about to read 6, iclass 3, count 2 2006.285.13:41:49.37#ibcon#read 6, iclass 3, count 2 2006.285.13:41:49.37#ibcon#end of sib2, iclass 3, count 2 2006.285.13:41:49.37#ibcon#*after write, iclass 3, count 2 2006.285.13:41:49.37#ibcon#*before return 0, iclass 3, count 2 2006.285.13:41:49.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:41:49.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:41:49.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.13:41:49.37#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:49.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:41:49.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:41:49.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:41:49.49#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:41:49.49#ibcon#first serial, iclass 3, count 0 2006.285.13:41:49.49#ibcon#enter sib2, iclass 3, count 0 2006.285.13:41:49.49#ibcon#flushed, iclass 3, count 0 2006.285.13:41:49.49#ibcon#about to write, iclass 3, count 0 2006.285.13:41:49.49#ibcon#wrote, iclass 3, count 0 2006.285.13:41:49.49#ibcon#about to read 3, iclass 3, count 0 2006.285.13:41:49.51#ibcon#read 3, iclass 3, count 0 2006.285.13:41:49.51#ibcon#about to read 4, iclass 3, count 0 2006.285.13:41:49.51#ibcon#read 4, iclass 3, count 0 2006.285.13:41:49.51#ibcon#about to read 5, iclass 3, count 0 2006.285.13:41:49.51#ibcon#read 5, iclass 3, count 0 2006.285.13:41:49.51#ibcon#about to read 6, iclass 3, count 0 2006.285.13:41:49.51#ibcon#read 6, iclass 3, count 0 2006.285.13:41:49.51#ibcon#end of sib2, iclass 3, count 0 2006.285.13:41:49.51#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:41:49.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:41:49.51#ibcon#[27=USB\r\n] 2006.285.13:41:49.51#ibcon#*before write, iclass 3, count 0 2006.285.13:41:49.51#ibcon#enter sib2, iclass 3, count 0 2006.285.13:41:49.51#ibcon#flushed, iclass 3, count 0 2006.285.13:41:49.51#ibcon#about to write, iclass 3, count 0 2006.285.13:41:49.51#ibcon#wrote, iclass 3, count 0 2006.285.13:41:49.51#ibcon#about to read 3, iclass 3, count 0 2006.285.13:41:49.54#ibcon#read 3, iclass 3, count 0 2006.285.13:41:49.54#ibcon#about to read 4, iclass 3, count 0 2006.285.13:41:49.54#ibcon#read 4, iclass 3, count 0 2006.285.13:41:49.54#ibcon#about to read 5, iclass 3, count 0 2006.285.13:41:49.54#ibcon#read 5, iclass 3, count 0 2006.285.13:41:49.54#ibcon#about to read 6, iclass 3, count 0 2006.285.13:41:49.54#ibcon#read 6, iclass 3, count 0 2006.285.13:41:49.54#ibcon#end of sib2, iclass 3, count 0 2006.285.13:41:49.54#ibcon#*after write, iclass 3, count 0 2006.285.13:41:49.54#ibcon#*before return 0, iclass 3, count 0 2006.285.13:41:49.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:41:49.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:41:49.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:41:49.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:41:49.54$vck44/vblo=3,649.99 2006.285.13:41:49.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.13:41:49.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.13:41:49.54#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:49.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:41:49.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:41:49.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:41:49.54#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:41:49.54#ibcon#first serial, iclass 5, count 0 2006.285.13:41:49.54#ibcon#enter sib2, iclass 5, count 0 2006.285.13:41:49.54#ibcon#flushed, iclass 5, count 0 2006.285.13:41:49.54#ibcon#about to write, iclass 5, count 0 2006.285.13:41:49.54#ibcon#wrote, iclass 5, count 0 2006.285.13:41:49.54#ibcon#about to read 3, iclass 5, count 0 2006.285.13:41:49.56#ibcon#read 3, iclass 5, count 0 2006.285.13:41:49.56#ibcon#about to read 4, iclass 5, count 0 2006.285.13:41:49.56#ibcon#read 4, iclass 5, count 0 2006.285.13:41:49.56#ibcon#about to read 5, iclass 5, count 0 2006.285.13:41:49.56#ibcon#read 5, iclass 5, count 0 2006.285.13:41:49.56#ibcon#about to read 6, iclass 5, count 0 2006.285.13:41:49.56#ibcon#read 6, iclass 5, count 0 2006.285.13:41:49.56#ibcon#end of sib2, iclass 5, count 0 2006.285.13:41:49.56#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:41:49.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:41:49.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:41:49.56#ibcon#*before write, iclass 5, count 0 2006.285.13:41:49.56#ibcon#enter sib2, iclass 5, count 0 2006.285.13:41:49.56#ibcon#flushed, iclass 5, count 0 2006.285.13:41:49.56#ibcon#about to write, iclass 5, count 0 2006.285.13:41:49.56#ibcon#wrote, iclass 5, count 0 2006.285.13:41:49.56#ibcon#about to read 3, iclass 5, count 0 2006.285.13:41:49.60#ibcon#read 3, iclass 5, count 0 2006.285.13:41:49.60#ibcon#about to read 4, iclass 5, count 0 2006.285.13:41:49.60#ibcon#read 4, iclass 5, count 0 2006.285.13:41:49.60#ibcon#about to read 5, iclass 5, count 0 2006.285.13:41:49.60#ibcon#read 5, iclass 5, count 0 2006.285.13:41:49.60#ibcon#about to read 6, iclass 5, count 0 2006.285.13:41:49.60#ibcon#read 6, iclass 5, count 0 2006.285.13:41:49.60#ibcon#end of sib2, iclass 5, count 0 2006.285.13:41:49.60#ibcon#*after write, iclass 5, count 0 2006.285.13:41:49.60#ibcon#*before return 0, iclass 5, count 0 2006.285.13:41:49.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:41:49.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:41:49.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:41:49.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:41:49.60$vck44/vb=3,4 2006.285.13:41:49.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.13:41:49.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.13:41:49.60#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:49.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:41:49.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:41:49.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:41:49.66#ibcon#enter wrdev, iclass 7, count 2 2006.285.13:41:49.66#ibcon#first serial, iclass 7, count 2 2006.285.13:41:49.66#ibcon#enter sib2, iclass 7, count 2 2006.285.13:41:49.66#ibcon#flushed, iclass 7, count 2 2006.285.13:41:49.66#ibcon#about to write, iclass 7, count 2 2006.285.13:41:49.66#ibcon#wrote, iclass 7, count 2 2006.285.13:41:49.66#ibcon#about to read 3, iclass 7, count 2 2006.285.13:41:49.68#ibcon#read 3, iclass 7, count 2 2006.285.13:41:49.68#ibcon#about to read 4, iclass 7, count 2 2006.285.13:41:49.68#ibcon#read 4, iclass 7, count 2 2006.285.13:41:49.68#ibcon#about to read 5, iclass 7, count 2 2006.285.13:41:49.68#ibcon#read 5, iclass 7, count 2 2006.285.13:41:49.68#ibcon#about to read 6, iclass 7, count 2 2006.285.13:41:49.68#ibcon#read 6, iclass 7, count 2 2006.285.13:41:49.68#ibcon#end of sib2, iclass 7, count 2 2006.285.13:41:49.68#ibcon#*mode == 0, iclass 7, count 2 2006.285.13:41:49.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.13:41:49.68#ibcon#[27=AT03-04\r\n] 2006.285.13:41:49.68#ibcon#*before write, iclass 7, count 2 2006.285.13:41:49.68#ibcon#enter sib2, iclass 7, count 2 2006.285.13:41:49.68#ibcon#flushed, iclass 7, count 2 2006.285.13:41:49.68#ibcon#about to write, iclass 7, count 2 2006.285.13:41:49.68#ibcon#wrote, iclass 7, count 2 2006.285.13:41:49.68#ibcon#about to read 3, iclass 7, count 2 2006.285.13:41:49.71#ibcon#read 3, iclass 7, count 2 2006.285.13:41:49.71#ibcon#about to read 4, iclass 7, count 2 2006.285.13:41:49.71#ibcon#read 4, iclass 7, count 2 2006.285.13:41:49.71#ibcon#about to read 5, iclass 7, count 2 2006.285.13:41:49.71#ibcon#read 5, iclass 7, count 2 2006.285.13:41:49.71#ibcon#about to read 6, iclass 7, count 2 2006.285.13:41:49.71#ibcon#read 6, iclass 7, count 2 2006.285.13:41:49.71#ibcon#end of sib2, iclass 7, count 2 2006.285.13:41:49.71#ibcon#*after write, iclass 7, count 2 2006.285.13:41:49.71#ibcon#*before return 0, iclass 7, count 2 2006.285.13:41:49.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:41:49.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:41:49.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.13:41:49.71#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:49.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:41:49.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:41:49.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:41:49.83#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:41:49.83#ibcon#first serial, iclass 7, count 0 2006.285.13:41:49.83#ibcon#enter sib2, iclass 7, count 0 2006.285.13:41:49.83#ibcon#flushed, iclass 7, count 0 2006.285.13:41:49.83#ibcon#about to write, iclass 7, count 0 2006.285.13:41:49.83#ibcon#wrote, iclass 7, count 0 2006.285.13:41:49.83#ibcon#about to read 3, iclass 7, count 0 2006.285.13:41:49.85#ibcon#read 3, iclass 7, count 0 2006.285.13:41:49.85#ibcon#about to read 4, iclass 7, count 0 2006.285.13:41:49.85#ibcon#read 4, iclass 7, count 0 2006.285.13:41:49.85#ibcon#about to read 5, iclass 7, count 0 2006.285.13:41:49.85#ibcon#read 5, iclass 7, count 0 2006.285.13:41:49.85#ibcon#about to read 6, iclass 7, count 0 2006.285.13:41:49.85#ibcon#read 6, iclass 7, count 0 2006.285.13:41:49.85#ibcon#end of sib2, iclass 7, count 0 2006.285.13:41:49.85#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:41:49.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:41:49.85#ibcon#[27=USB\r\n] 2006.285.13:41:49.85#ibcon#*before write, iclass 7, count 0 2006.285.13:41:49.85#ibcon#enter sib2, iclass 7, count 0 2006.285.13:41:49.85#ibcon#flushed, iclass 7, count 0 2006.285.13:41:49.85#ibcon#about to write, iclass 7, count 0 2006.285.13:41:49.85#ibcon#wrote, iclass 7, count 0 2006.285.13:41:49.85#ibcon#about to read 3, iclass 7, count 0 2006.285.13:41:49.88#ibcon#read 3, iclass 7, count 0 2006.285.13:41:49.88#ibcon#about to read 4, iclass 7, count 0 2006.285.13:41:49.88#ibcon#read 4, iclass 7, count 0 2006.285.13:41:49.88#ibcon#about to read 5, iclass 7, count 0 2006.285.13:41:49.88#ibcon#read 5, iclass 7, count 0 2006.285.13:41:49.88#ibcon#about to read 6, iclass 7, count 0 2006.285.13:41:49.88#ibcon#read 6, iclass 7, count 0 2006.285.13:41:49.88#ibcon#end of sib2, iclass 7, count 0 2006.285.13:41:49.88#ibcon#*after write, iclass 7, count 0 2006.285.13:41:49.88#ibcon#*before return 0, iclass 7, count 0 2006.285.13:41:49.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:41:49.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:41:49.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:41:49.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:41:49.88$vck44/vblo=4,679.99 2006.285.13:41:49.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.13:41:49.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.13:41:49.88#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:49.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:41:49.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:41:49.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:41:49.88#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:41:49.88#ibcon#first serial, iclass 11, count 0 2006.285.13:41:49.88#ibcon#enter sib2, iclass 11, count 0 2006.285.13:41:49.88#ibcon#flushed, iclass 11, count 0 2006.285.13:41:49.88#ibcon#about to write, iclass 11, count 0 2006.285.13:41:49.88#ibcon#wrote, iclass 11, count 0 2006.285.13:41:49.88#ibcon#about to read 3, iclass 11, count 0 2006.285.13:41:49.90#ibcon#read 3, iclass 11, count 0 2006.285.13:41:49.90#ibcon#about to read 4, iclass 11, count 0 2006.285.13:41:49.90#ibcon#read 4, iclass 11, count 0 2006.285.13:41:49.90#ibcon#about to read 5, iclass 11, count 0 2006.285.13:41:49.90#ibcon#read 5, iclass 11, count 0 2006.285.13:41:49.90#ibcon#about to read 6, iclass 11, count 0 2006.285.13:41:49.90#ibcon#read 6, iclass 11, count 0 2006.285.13:41:49.90#ibcon#end of sib2, iclass 11, count 0 2006.285.13:41:49.90#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:41:49.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:41:49.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:41:49.90#ibcon#*before write, iclass 11, count 0 2006.285.13:41:49.90#ibcon#enter sib2, iclass 11, count 0 2006.285.13:41:49.90#ibcon#flushed, iclass 11, count 0 2006.285.13:41:49.90#ibcon#about to write, iclass 11, count 0 2006.285.13:41:49.90#ibcon#wrote, iclass 11, count 0 2006.285.13:41:49.90#ibcon#about to read 3, iclass 11, count 0 2006.285.13:41:49.94#ibcon#read 3, iclass 11, count 0 2006.285.13:41:49.94#ibcon#about to read 4, iclass 11, count 0 2006.285.13:41:49.94#ibcon#read 4, iclass 11, count 0 2006.285.13:41:49.94#ibcon#about to read 5, iclass 11, count 0 2006.285.13:41:49.94#ibcon#read 5, iclass 11, count 0 2006.285.13:41:49.94#ibcon#about to read 6, iclass 11, count 0 2006.285.13:41:49.94#ibcon#read 6, iclass 11, count 0 2006.285.13:41:49.94#ibcon#end of sib2, iclass 11, count 0 2006.285.13:41:49.94#ibcon#*after write, iclass 11, count 0 2006.285.13:41:49.94#ibcon#*before return 0, iclass 11, count 0 2006.285.13:41:49.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:41:49.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:41:49.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:41:49.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:41:49.94$vck44/vb=4,5 2006.285.13:41:49.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.13:41:49.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.13:41:49.94#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:49.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:41:50.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:41:50.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:41:50.00#ibcon#enter wrdev, iclass 13, count 2 2006.285.13:41:50.00#ibcon#first serial, iclass 13, count 2 2006.285.13:41:50.00#ibcon#enter sib2, iclass 13, count 2 2006.285.13:41:50.00#ibcon#flushed, iclass 13, count 2 2006.285.13:41:50.00#ibcon#about to write, iclass 13, count 2 2006.285.13:41:50.00#ibcon#wrote, iclass 13, count 2 2006.285.13:41:50.00#ibcon#about to read 3, iclass 13, count 2 2006.285.13:41:50.02#ibcon#read 3, iclass 13, count 2 2006.285.13:41:50.02#ibcon#about to read 4, iclass 13, count 2 2006.285.13:41:50.02#ibcon#read 4, iclass 13, count 2 2006.285.13:41:50.02#ibcon#about to read 5, iclass 13, count 2 2006.285.13:41:50.02#ibcon#read 5, iclass 13, count 2 2006.285.13:41:50.02#ibcon#about to read 6, iclass 13, count 2 2006.285.13:41:50.02#ibcon#read 6, iclass 13, count 2 2006.285.13:41:50.02#ibcon#end of sib2, iclass 13, count 2 2006.285.13:41:50.02#ibcon#*mode == 0, iclass 13, count 2 2006.285.13:41:50.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.13:41:50.02#ibcon#[27=AT04-05\r\n] 2006.285.13:41:50.02#ibcon#*before write, iclass 13, count 2 2006.285.13:41:50.02#ibcon#enter sib2, iclass 13, count 2 2006.285.13:41:50.02#ibcon#flushed, iclass 13, count 2 2006.285.13:41:50.02#ibcon#about to write, iclass 13, count 2 2006.285.13:41:50.02#ibcon#wrote, iclass 13, count 2 2006.285.13:41:50.02#ibcon#about to read 3, iclass 13, count 2 2006.285.13:41:50.05#ibcon#read 3, iclass 13, count 2 2006.285.13:41:50.05#ibcon#about to read 4, iclass 13, count 2 2006.285.13:41:50.05#ibcon#read 4, iclass 13, count 2 2006.285.13:41:50.05#ibcon#about to read 5, iclass 13, count 2 2006.285.13:41:50.05#ibcon#read 5, iclass 13, count 2 2006.285.13:41:50.05#ibcon#about to read 6, iclass 13, count 2 2006.285.13:41:50.05#ibcon#read 6, iclass 13, count 2 2006.285.13:41:50.05#ibcon#end of sib2, iclass 13, count 2 2006.285.13:41:50.05#ibcon#*after write, iclass 13, count 2 2006.285.13:41:50.05#ibcon#*before return 0, iclass 13, count 2 2006.285.13:41:50.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:41:50.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:41:50.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.13:41:50.05#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:50.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:41:50.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:41:50.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:41:50.17#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:41:50.17#ibcon#first serial, iclass 13, count 0 2006.285.13:41:50.17#ibcon#enter sib2, iclass 13, count 0 2006.285.13:41:50.17#ibcon#flushed, iclass 13, count 0 2006.285.13:41:50.17#ibcon#about to write, iclass 13, count 0 2006.285.13:41:50.17#ibcon#wrote, iclass 13, count 0 2006.285.13:41:50.17#ibcon#about to read 3, iclass 13, count 0 2006.285.13:41:50.19#ibcon#read 3, iclass 13, count 0 2006.285.13:41:50.19#ibcon#about to read 4, iclass 13, count 0 2006.285.13:41:50.19#ibcon#read 4, iclass 13, count 0 2006.285.13:41:50.19#ibcon#about to read 5, iclass 13, count 0 2006.285.13:41:50.19#ibcon#read 5, iclass 13, count 0 2006.285.13:41:50.19#ibcon#about to read 6, iclass 13, count 0 2006.285.13:41:50.19#ibcon#read 6, iclass 13, count 0 2006.285.13:41:50.19#ibcon#end of sib2, iclass 13, count 0 2006.285.13:41:50.19#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:41:50.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:41:50.19#ibcon#[27=USB\r\n] 2006.285.13:41:50.19#ibcon#*before write, iclass 13, count 0 2006.285.13:41:50.19#ibcon#enter sib2, iclass 13, count 0 2006.285.13:41:50.19#ibcon#flushed, iclass 13, count 0 2006.285.13:41:50.19#ibcon#about to write, iclass 13, count 0 2006.285.13:41:50.19#ibcon#wrote, iclass 13, count 0 2006.285.13:41:50.19#ibcon#about to read 3, iclass 13, count 0 2006.285.13:41:50.22#ibcon#read 3, iclass 13, count 0 2006.285.13:41:50.22#ibcon#about to read 4, iclass 13, count 0 2006.285.13:41:50.22#ibcon#read 4, iclass 13, count 0 2006.285.13:41:50.22#ibcon#about to read 5, iclass 13, count 0 2006.285.13:41:50.22#ibcon#read 5, iclass 13, count 0 2006.285.13:41:50.22#ibcon#about to read 6, iclass 13, count 0 2006.285.13:41:50.22#ibcon#read 6, iclass 13, count 0 2006.285.13:41:50.22#ibcon#end of sib2, iclass 13, count 0 2006.285.13:41:50.22#ibcon#*after write, iclass 13, count 0 2006.285.13:41:50.22#ibcon#*before return 0, iclass 13, count 0 2006.285.13:41:50.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:41:50.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:41:50.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:41:50.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:41:50.22$vck44/vblo=5,709.99 2006.285.13:41:50.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.13:41:50.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.13:41:50.22#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:50.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:41:50.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:41:50.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:41:50.22#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:41:50.22#ibcon#first serial, iclass 15, count 0 2006.285.13:41:50.22#ibcon#enter sib2, iclass 15, count 0 2006.285.13:41:50.22#ibcon#flushed, iclass 15, count 0 2006.285.13:41:50.22#ibcon#about to write, iclass 15, count 0 2006.285.13:41:50.22#ibcon#wrote, iclass 15, count 0 2006.285.13:41:50.22#ibcon#about to read 3, iclass 15, count 0 2006.285.13:41:50.24#ibcon#read 3, iclass 15, count 0 2006.285.13:41:50.24#ibcon#about to read 4, iclass 15, count 0 2006.285.13:41:50.24#ibcon#read 4, iclass 15, count 0 2006.285.13:41:50.24#ibcon#about to read 5, iclass 15, count 0 2006.285.13:41:50.24#ibcon#read 5, iclass 15, count 0 2006.285.13:41:50.24#ibcon#about to read 6, iclass 15, count 0 2006.285.13:41:50.24#ibcon#read 6, iclass 15, count 0 2006.285.13:41:50.24#ibcon#end of sib2, iclass 15, count 0 2006.285.13:41:50.24#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:41:50.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:41:50.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:41:50.24#ibcon#*before write, iclass 15, count 0 2006.285.13:41:50.24#ibcon#enter sib2, iclass 15, count 0 2006.285.13:41:50.24#ibcon#flushed, iclass 15, count 0 2006.285.13:41:50.24#ibcon#about to write, iclass 15, count 0 2006.285.13:41:50.24#ibcon#wrote, iclass 15, count 0 2006.285.13:41:50.24#ibcon#about to read 3, iclass 15, count 0 2006.285.13:41:50.28#ibcon#read 3, iclass 15, count 0 2006.285.13:41:50.28#ibcon#about to read 4, iclass 15, count 0 2006.285.13:41:50.28#ibcon#read 4, iclass 15, count 0 2006.285.13:41:50.28#ibcon#about to read 5, iclass 15, count 0 2006.285.13:41:50.28#ibcon#read 5, iclass 15, count 0 2006.285.13:41:50.28#ibcon#about to read 6, iclass 15, count 0 2006.285.13:41:50.28#ibcon#read 6, iclass 15, count 0 2006.285.13:41:50.28#ibcon#end of sib2, iclass 15, count 0 2006.285.13:41:50.28#ibcon#*after write, iclass 15, count 0 2006.285.13:41:50.28#ibcon#*before return 0, iclass 15, count 0 2006.285.13:41:50.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:41:50.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:41:50.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:41:50.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:41:50.28$vck44/vb=5,4 2006.285.13:41:50.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.13:41:50.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.13:41:50.28#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:50.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:41:50.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:41:50.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:41:50.34#ibcon#enter wrdev, iclass 17, count 2 2006.285.13:41:50.34#ibcon#first serial, iclass 17, count 2 2006.285.13:41:50.34#ibcon#enter sib2, iclass 17, count 2 2006.285.13:41:50.34#ibcon#flushed, iclass 17, count 2 2006.285.13:41:50.34#ibcon#about to write, iclass 17, count 2 2006.285.13:41:50.34#ibcon#wrote, iclass 17, count 2 2006.285.13:41:50.34#ibcon#about to read 3, iclass 17, count 2 2006.285.13:41:50.36#ibcon#read 3, iclass 17, count 2 2006.285.13:41:50.36#ibcon#about to read 4, iclass 17, count 2 2006.285.13:41:50.36#ibcon#read 4, iclass 17, count 2 2006.285.13:41:50.36#ibcon#about to read 5, iclass 17, count 2 2006.285.13:41:50.36#ibcon#read 5, iclass 17, count 2 2006.285.13:41:50.36#ibcon#about to read 6, iclass 17, count 2 2006.285.13:41:50.36#ibcon#read 6, iclass 17, count 2 2006.285.13:41:50.36#ibcon#end of sib2, iclass 17, count 2 2006.285.13:41:50.36#ibcon#*mode == 0, iclass 17, count 2 2006.285.13:41:50.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.13:41:50.36#ibcon#[27=AT05-04\r\n] 2006.285.13:41:50.36#ibcon#*before write, iclass 17, count 2 2006.285.13:41:50.36#ibcon#enter sib2, iclass 17, count 2 2006.285.13:41:50.36#ibcon#flushed, iclass 17, count 2 2006.285.13:41:50.36#ibcon#about to write, iclass 17, count 2 2006.285.13:41:50.36#ibcon#wrote, iclass 17, count 2 2006.285.13:41:50.36#ibcon#about to read 3, iclass 17, count 2 2006.285.13:41:50.39#ibcon#read 3, iclass 17, count 2 2006.285.13:41:50.39#ibcon#about to read 4, iclass 17, count 2 2006.285.13:41:50.39#ibcon#read 4, iclass 17, count 2 2006.285.13:41:50.39#ibcon#about to read 5, iclass 17, count 2 2006.285.13:41:50.39#ibcon#read 5, iclass 17, count 2 2006.285.13:41:50.39#ibcon#about to read 6, iclass 17, count 2 2006.285.13:41:50.39#ibcon#read 6, iclass 17, count 2 2006.285.13:41:50.39#ibcon#end of sib2, iclass 17, count 2 2006.285.13:41:50.39#ibcon#*after write, iclass 17, count 2 2006.285.13:41:50.39#ibcon#*before return 0, iclass 17, count 2 2006.285.13:41:50.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:41:50.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:41:50.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.13:41:50.39#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:50.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:41:50.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:41:50.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:41:50.51#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:41:50.51#ibcon#first serial, iclass 17, count 0 2006.285.13:41:50.51#ibcon#enter sib2, iclass 17, count 0 2006.285.13:41:50.51#ibcon#flushed, iclass 17, count 0 2006.285.13:41:50.51#ibcon#about to write, iclass 17, count 0 2006.285.13:41:50.51#ibcon#wrote, iclass 17, count 0 2006.285.13:41:50.51#ibcon#about to read 3, iclass 17, count 0 2006.285.13:41:50.53#ibcon#read 3, iclass 17, count 0 2006.285.13:41:50.53#ibcon#about to read 4, iclass 17, count 0 2006.285.13:41:50.53#ibcon#read 4, iclass 17, count 0 2006.285.13:41:50.53#ibcon#about to read 5, iclass 17, count 0 2006.285.13:41:50.53#ibcon#read 5, iclass 17, count 0 2006.285.13:41:50.53#ibcon#about to read 6, iclass 17, count 0 2006.285.13:41:50.53#ibcon#read 6, iclass 17, count 0 2006.285.13:41:50.53#ibcon#end of sib2, iclass 17, count 0 2006.285.13:41:50.53#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:41:50.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:41:50.53#ibcon#[27=USB\r\n] 2006.285.13:41:50.53#ibcon#*before write, iclass 17, count 0 2006.285.13:41:50.53#ibcon#enter sib2, iclass 17, count 0 2006.285.13:41:50.53#ibcon#flushed, iclass 17, count 0 2006.285.13:41:50.53#ibcon#about to write, iclass 17, count 0 2006.285.13:41:50.53#ibcon#wrote, iclass 17, count 0 2006.285.13:41:50.53#ibcon#about to read 3, iclass 17, count 0 2006.285.13:41:50.56#ibcon#read 3, iclass 17, count 0 2006.285.13:41:50.56#ibcon#about to read 4, iclass 17, count 0 2006.285.13:41:50.56#ibcon#read 4, iclass 17, count 0 2006.285.13:41:50.56#ibcon#about to read 5, iclass 17, count 0 2006.285.13:41:50.56#ibcon#read 5, iclass 17, count 0 2006.285.13:41:50.56#ibcon#about to read 6, iclass 17, count 0 2006.285.13:41:50.56#ibcon#read 6, iclass 17, count 0 2006.285.13:41:50.56#ibcon#end of sib2, iclass 17, count 0 2006.285.13:41:50.56#ibcon#*after write, iclass 17, count 0 2006.285.13:41:50.56#ibcon#*before return 0, iclass 17, count 0 2006.285.13:41:50.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:41:50.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:41:50.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:41:50.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:41:50.56$vck44/vblo=6,719.99 2006.285.13:41:50.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.13:41:50.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.13:41:50.56#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:50.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:41:50.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:41:50.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:41:50.56#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:41:50.56#ibcon#first serial, iclass 19, count 0 2006.285.13:41:50.56#ibcon#enter sib2, iclass 19, count 0 2006.285.13:41:50.56#ibcon#flushed, iclass 19, count 0 2006.285.13:41:50.56#ibcon#about to write, iclass 19, count 0 2006.285.13:41:50.56#ibcon#wrote, iclass 19, count 0 2006.285.13:41:50.56#ibcon#about to read 3, iclass 19, count 0 2006.285.13:41:50.58#ibcon#read 3, iclass 19, count 0 2006.285.13:41:50.58#ibcon#about to read 4, iclass 19, count 0 2006.285.13:41:50.58#ibcon#read 4, iclass 19, count 0 2006.285.13:41:50.58#ibcon#about to read 5, iclass 19, count 0 2006.285.13:41:50.58#ibcon#read 5, iclass 19, count 0 2006.285.13:41:50.58#ibcon#about to read 6, iclass 19, count 0 2006.285.13:41:50.58#ibcon#read 6, iclass 19, count 0 2006.285.13:41:50.58#ibcon#end of sib2, iclass 19, count 0 2006.285.13:41:50.58#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:41:50.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:41:50.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:41:50.58#ibcon#*before write, iclass 19, count 0 2006.285.13:41:50.58#ibcon#enter sib2, iclass 19, count 0 2006.285.13:41:50.58#ibcon#flushed, iclass 19, count 0 2006.285.13:41:50.58#ibcon#about to write, iclass 19, count 0 2006.285.13:41:50.58#ibcon#wrote, iclass 19, count 0 2006.285.13:41:50.58#ibcon#about to read 3, iclass 19, count 0 2006.285.13:41:50.62#ibcon#read 3, iclass 19, count 0 2006.285.13:41:50.62#ibcon#about to read 4, iclass 19, count 0 2006.285.13:41:50.62#ibcon#read 4, iclass 19, count 0 2006.285.13:41:50.62#ibcon#about to read 5, iclass 19, count 0 2006.285.13:41:50.62#ibcon#read 5, iclass 19, count 0 2006.285.13:41:50.62#ibcon#about to read 6, iclass 19, count 0 2006.285.13:41:50.62#ibcon#read 6, iclass 19, count 0 2006.285.13:41:50.62#ibcon#end of sib2, iclass 19, count 0 2006.285.13:41:50.62#ibcon#*after write, iclass 19, count 0 2006.285.13:41:50.62#ibcon#*before return 0, iclass 19, count 0 2006.285.13:41:50.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:41:50.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:41:50.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:41:50.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:41:50.62$vck44/vb=6,3 2006.285.13:41:50.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.13:41:50.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.13:41:50.62#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:50.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:41:50.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:41:50.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:41:50.68#ibcon#enter wrdev, iclass 21, count 2 2006.285.13:41:50.68#ibcon#first serial, iclass 21, count 2 2006.285.13:41:50.68#ibcon#enter sib2, iclass 21, count 2 2006.285.13:41:50.68#ibcon#flushed, iclass 21, count 2 2006.285.13:41:50.68#ibcon#about to write, iclass 21, count 2 2006.285.13:41:50.68#ibcon#wrote, iclass 21, count 2 2006.285.13:41:50.68#ibcon#about to read 3, iclass 21, count 2 2006.285.13:41:50.70#ibcon#read 3, iclass 21, count 2 2006.285.13:41:50.70#ibcon#about to read 4, iclass 21, count 2 2006.285.13:41:50.70#ibcon#read 4, iclass 21, count 2 2006.285.13:41:50.70#ibcon#about to read 5, iclass 21, count 2 2006.285.13:41:50.70#ibcon#read 5, iclass 21, count 2 2006.285.13:41:50.70#ibcon#about to read 6, iclass 21, count 2 2006.285.13:41:50.70#ibcon#read 6, iclass 21, count 2 2006.285.13:41:50.70#ibcon#end of sib2, iclass 21, count 2 2006.285.13:41:50.70#ibcon#*mode == 0, iclass 21, count 2 2006.285.13:41:50.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.13:41:50.70#ibcon#[27=AT06-03\r\n] 2006.285.13:41:50.70#ibcon#*before write, iclass 21, count 2 2006.285.13:41:50.70#ibcon#enter sib2, iclass 21, count 2 2006.285.13:41:50.70#ibcon#flushed, iclass 21, count 2 2006.285.13:41:50.70#ibcon#about to write, iclass 21, count 2 2006.285.13:41:50.70#ibcon#wrote, iclass 21, count 2 2006.285.13:41:50.70#ibcon#about to read 3, iclass 21, count 2 2006.285.13:41:50.73#ibcon#read 3, iclass 21, count 2 2006.285.13:41:50.73#ibcon#about to read 4, iclass 21, count 2 2006.285.13:41:50.73#ibcon#read 4, iclass 21, count 2 2006.285.13:41:50.73#ibcon#about to read 5, iclass 21, count 2 2006.285.13:41:50.73#ibcon#read 5, iclass 21, count 2 2006.285.13:41:50.73#ibcon#about to read 6, iclass 21, count 2 2006.285.13:41:50.73#ibcon#read 6, iclass 21, count 2 2006.285.13:41:50.73#ibcon#end of sib2, iclass 21, count 2 2006.285.13:41:50.73#ibcon#*after write, iclass 21, count 2 2006.285.13:41:50.73#ibcon#*before return 0, iclass 21, count 2 2006.285.13:41:50.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:41:50.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:41:50.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.13:41:50.73#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:50.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:41:50.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:41:50.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:41:50.85#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:41:50.85#ibcon#first serial, iclass 21, count 0 2006.285.13:41:50.85#ibcon#enter sib2, iclass 21, count 0 2006.285.13:41:50.85#ibcon#flushed, iclass 21, count 0 2006.285.13:41:50.85#ibcon#about to write, iclass 21, count 0 2006.285.13:41:50.85#ibcon#wrote, iclass 21, count 0 2006.285.13:41:50.85#ibcon#about to read 3, iclass 21, count 0 2006.285.13:41:50.87#ibcon#read 3, iclass 21, count 0 2006.285.13:41:50.87#ibcon#about to read 4, iclass 21, count 0 2006.285.13:41:50.87#ibcon#read 4, iclass 21, count 0 2006.285.13:41:50.87#ibcon#about to read 5, iclass 21, count 0 2006.285.13:41:50.87#ibcon#read 5, iclass 21, count 0 2006.285.13:41:50.87#ibcon#about to read 6, iclass 21, count 0 2006.285.13:41:50.87#ibcon#read 6, iclass 21, count 0 2006.285.13:41:50.87#ibcon#end of sib2, iclass 21, count 0 2006.285.13:41:50.87#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:41:50.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:41:50.87#ibcon#[27=USB\r\n] 2006.285.13:41:50.87#ibcon#*before write, iclass 21, count 0 2006.285.13:41:50.87#ibcon#enter sib2, iclass 21, count 0 2006.285.13:41:50.87#ibcon#flushed, iclass 21, count 0 2006.285.13:41:50.87#ibcon#about to write, iclass 21, count 0 2006.285.13:41:50.87#ibcon#wrote, iclass 21, count 0 2006.285.13:41:50.87#ibcon#about to read 3, iclass 21, count 0 2006.285.13:41:50.90#ibcon#read 3, iclass 21, count 0 2006.285.13:41:50.90#ibcon#about to read 4, iclass 21, count 0 2006.285.13:41:50.90#ibcon#read 4, iclass 21, count 0 2006.285.13:41:50.90#ibcon#about to read 5, iclass 21, count 0 2006.285.13:41:50.90#ibcon#read 5, iclass 21, count 0 2006.285.13:41:50.90#ibcon#about to read 6, iclass 21, count 0 2006.285.13:41:50.90#ibcon#read 6, iclass 21, count 0 2006.285.13:41:50.90#ibcon#end of sib2, iclass 21, count 0 2006.285.13:41:50.90#ibcon#*after write, iclass 21, count 0 2006.285.13:41:50.90#ibcon#*before return 0, iclass 21, count 0 2006.285.13:41:50.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:41:50.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:41:50.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:41:50.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:41:50.90$vck44/vblo=7,734.99 2006.285.13:41:50.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.13:41:50.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.13:41:50.90#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:50.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:41:50.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:41:50.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:41:50.90#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:41:50.90#ibcon#first serial, iclass 23, count 0 2006.285.13:41:50.90#ibcon#enter sib2, iclass 23, count 0 2006.285.13:41:50.90#ibcon#flushed, iclass 23, count 0 2006.285.13:41:50.90#ibcon#about to write, iclass 23, count 0 2006.285.13:41:50.90#ibcon#wrote, iclass 23, count 0 2006.285.13:41:50.90#ibcon#about to read 3, iclass 23, count 0 2006.285.13:41:50.92#ibcon#read 3, iclass 23, count 0 2006.285.13:41:50.92#ibcon#about to read 4, iclass 23, count 0 2006.285.13:41:50.92#ibcon#read 4, iclass 23, count 0 2006.285.13:41:50.92#ibcon#about to read 5, iclass 23, count 0 2006.285.13:41:50.92#ibcon#read 5, iclass 23, count 0 2006.285.13:41:50.92#ibcon#about to read 6, iclass 23, count 0 2006.285.13:41:50.92#ibcon#read 6, iclass 23, count 0 2006.285.13:41:50.92#ibcon#end of sib2, iclass 23, count 0 2006.285.13:41:50.92#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:41:50.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:41:50.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:41:50.92#ibcon#*before write, iclass 23, count 0 2006.285.13:41:50.92#ibcon#enter sib2, iclass 23, count 0 2006.285.13:41:50.92#ibcon#flushed, iclass 23, count 0 2006.285.13:41:50.92#ibcon#about to write, iclass 23, count 0 2006.285.13:41:50.92#ibcon#wrote, iclass 23, count 0 2006.285.13:41:50.92#ibcon#about to read 3, iclass 23, count 0 2006.285.13:41:50.96#ibcon#read 3, iclass 23, count 0 2006.285.13:41:50.96#ibcon#about to read 4, iclass 23, count 0 2006.285.13:41:50.96#ibcon#read 4, iclass 23, count 0 2006.285.13:41:50.96#ibcon#about to read 5, iclass 23, count 0 2006.285.13:41:50.96#ibcon#read 5, iclass 23, count 0 2006.285.13:41:50.96#ibcon#about to read 6, iclass 23, count 0 2006.285.13:41:50.96#ibcon#read 6, iclass 23, count 0 2006.285.13:41:50.96#ibcon#end of sib2, iclass 23, count 0 2006.285.13:41:50.96#ibcon#*after write, iclass 23, count 0 2006.285.13:41:50.96#ibcon#*before return 0, iclass 23, count 0 2006.285.13:41:50.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:41:50.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:41:50.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:41:50.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:41:50.96$vck44/vb=7,4 2006.285.13:41:50.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.13:41:50.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.13:41:50.96#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:50.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:41:51.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:41:51.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:41:51.02#ibcon#enter wrdev, iclass 25, count 2 2006.285.13:41:51.02#ibcon#first serial, iclass 25, count 2 2006.285.13:41:51.02#ibcon#enter sib2, iclass 25, count 2 2006.285.13:41:51.02#ibcon#flushed, iclass 25, count 2 2006.285.13:41:51.02#ibcon#about to write, iclass 25, count 2 2006.285.13:41:51.02#ibcon#wrote, iclass 25, count 2 2006.285.13:41:51.02#ibcon#about to read 3, iclass 25, count 2 2006.285.13:41:51.04#ibcon#read 3, iclass 25, count 2 2006.285.13:41:51.04#ibcon#about to read 4, iclass 25, count 2 2006.285.13:41:51.04#ibcon#read 4, iclass 25, count 2 2006.285.13:41:51.04#ibcon#about to read 5, iclass 25, count 2 2006.285.13:41:51.04#ibcon#read 5, iclass 25, count 2 2006.285.13:41:51.04#ibcon#about to read 6, iclass 25, count 2 2006.285.13:41:51.04#ibcon#read 6, iclass 25, count 2 2006.285.13:41:51.04#ibcon#end of sib2, iclass 25, count 2 2006.285.13:41:51.04#ibcon#*mode == 0, iclass 25, count 2 2006.285.13:41:51.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.13:41:51.04#ibcon#[27=AT07-04\r\n] 2006.285.13:41:51.04#ibcon#*before write, iclass 25, count 2 2006.285.13:41:51.04#ibcon#enter sib2, iclass 25, count 2 2006.285.13:41:51.04#ibcon#flushed, iclass 25, count 2 2006.285.13:41:51.04#ibcon#about to write, iclass 25, count 2 2006.285.13:41:51.04#ibcon#wrote, iclass 25, count 2 2006.285.13:41:51.04#ibcon#about to read 3, iclass 25, count 2 2006.285.13:41:51.07#ibcon#read 3, iclass 25, count 2 2006.285.13:41:51.07#ibcon#about to read 4, iclass 25, count 2 2006.285.13:41:51.07#ibcon#read 4, iclass 25, count 2 2006.285.13:41:51.07#ibcon#about to read 5, iclass 25, count 2 2006.285.13:41:51.07#ibcon#read 5, iclass 25, count 2 2006.285.13:41:51.07#ibcon#about to read 6, iclass 25, count 2 2006.285.13:41:51.07#ibcon#read 6, iclass 25, count 2 2006.285.13:41:51.07#ibcon#end of sib2, iclass 25, count 2 2006.285.13:41:51.07#ibcon#*after write, iclass 25, count 2 2006.285.13:41:51.07#ibcon#*before return 0, iclass 25, count 2 2006.285.13:41:51.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:41:51.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:41:51.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.13:41:51.07#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:51.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:41:51.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:41:51.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:41:51.19#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:41:51.19#ibcon#first serial, iclass 25, count 0 2006.285.13:41:51.19#ibcon#enter sib2, iclass 25, count 0 2006.285.13:41:51.19#ibcon#flushed, iclass 25, count 0 2006.285.13:41:51.19#ibcon#about to write, iclass 25, count 0 2006.285.13:41:51.19#ibcon#wrote, iclass 25, count 0 2006.285.13:41:51.19#ibcon#about to read 3, iclass 25, count 0 2006.285.13:41:51.21#ibcon#read 3, iclass 25, count 0 2006.285.13:41:51.21#ibcon#about to read 4, iclass 25, count 0 2006.285.13:41:51.21#ibcon#read 4, iclass 25, count 0 2006.285.13:41:51.21#ibcon#about to read 5, iclass 25, count 0 2006.285.13:41:51.21#ibcon#read 5, iclass 25, count 0 2006.285.13:41:51.21#ibcon#about to read 6, iclass 25, count 0 2006.285.13:41:51.21#ibcon#read 6, iclass 25, count 0 2006.285.13:41:51.21#ibcon#end of sib2, iclass 25, count 0 2006.285.13:41:51.21#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:41:51.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:41:51.21#ibcon#[27=USB\r\n] 2006.285.13:41:51.21#ibcon#*before write, iclass 25, count 0 2006.285.13:41:51.21#ibcon#enter sib2, iclass 25, count 0 2006.285.13:41:51.21#ibcon#flushed, iclass 25, count 0 2006.285.13:41:51.21#ibcon#about to write, iclass 25, count 0 2006.285.13:41:51.21#ibcon#wrote, iclass 25, count 0 2006.285.13:41:51.21#ibcon#about to read 3, iclass 25, count 0 2006.285.13:41:51.24#ibcon#read 3, iclass 25, count 0 2006.285.13:41:51.24#ibcon#about to read 4, iclass 25, count 0 2006.285.13:41:51.24#ibcon#read 4, iclass 25, count 0 2006.285.13:41:51.24#ibcon#about to read 5, iclass 25, count 0 2006.285.13:41:51.24#ibcon#read 5, iclass 25, count 0 2006.285.13:41:51.24#ibcon#about to read 6, iclass 25, count 0 2006.285.13:41:51.24#ibcon#read 6, iclass 25, count 0 2006.285.13:41:51.24#ibcon#end of sib2, iclass 25, count 0 2006.285.13:41:51.24#ibcon#*after write, iclass 25, count 0 2006.285.13:41:51.24#ibcon#*before return 0, iclass 25, count 0 2006.285.13:41:51.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:41:51.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:41:51.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:41:51.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:41:51.24$vck44/vblo=8,744.99 2006.285.13:41:51.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.13:41:51.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.13:41:51.24#ibcon#ireg 17 cls_cnt 0 2006.285.13:41:51.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:41:51.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:41:51.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:41:51.24#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:41:51.24#ibcon#first serial, iclass 27, count 0 2006.285.13:41:51.24#ibcon#enter sib2, iclass 27, count 0 2006.285.13:41:51.24#ibcon#flushed, iclass 27, count 0 2006.285.13:41:51.24#ibcon#about to write, iclass 27, count 0 2006.285.13:41:51.24#ibcon#wrote, iclass 27, count 0 2006.285.13:41:51.24#ibcon#about to read 3, iclass 27, count 0 2006.285.13:41:51.26#ibcon#read 3, iclass 27, count 0 2006.285.13:41:51.26#ibcon#about to read 4, iclass 27, count 0 2006.285.13:41:51.26#ibcon#read 4, iclass 27, count 0 2006.285.13:41:51.26#ibcon#about to read 5, iclass 27, count 0 2006.285.13:41:51.26#ibcon#read 5, iclass 27, count 0 2006.285.13:41:51.26#ibcon#about to read 6, iclass 27, count 0 2006.285.13:41:51.26#ibcon#read 6, iclass 27, count 0 2006.285.13:41:51.26#ibcon#end of sib2, iclass 27, count 0 2006.285.13:41:51.26#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:41:51.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:41:51.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:41:51.26#ibcon#*before write, iclass 27, count 0 2006.285.13:41:51.26#ibcon#enter sib2, iclass 27, count 0 2006.285.13:41:51.26#ibcon#flushed, iclass 27, count 0 2006.285.13:41:51.26#ibcon#about to write, iclass 27, count 0 2006.285.13:41:51.26#ibcon#wrote, iclass 27, count 0 2006.285.13:41:51.26#ibcon#about to read 3, iclass 27, count 0 2006.285.13:41:51.30#ibcon#read 3, iclass 27, count 0 2006.285.13:41:51.30#ibcon#about to read 4, iclass 27, count 0 2006.285.13:41:51.30#ibcon#read 4, iclass 27, count 0 2006.285.13:41:51.30#ibcon#about to read 5, iclass 27, count 0 2006.285.13:41:51.30#ibcon#read 5, iclass 27, count 0 2006.285.13:41:51.30#ibcon#about to read 6, iclass 27, count 0 2006.285.13:41:51.30#ibcon#read 6, iclass 27, count 0 2006.285.13:41:51.30#ibcon#end of sib2, iclass 27, count 0 2006.285.13:41:51.30#ibcon#*after write, iclass 27, count 0 2006.285.13:41:51.30#ibcon#*before return 0, iclass 27, count 0 2006.285.13:41:51.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:41:51.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:41:51.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:41:51.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:41:51.30$vck44/vb=8,4 2006.285.13:41:51.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.13:41:51.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.13:41:51.30#ibcon#ireg 11 cls_cnt 2 2006.285.13:41:51.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:41:51.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:41:51.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:41:51.36#ibcon#enter wrdev, iclass 29, count 2 2006.285.13:41:51.36#ibcon#first serial, iclass 29, count 2 2006.285.13:41:51.36#ibcon#enter sib2, iclass 29, count 2 2006.285.13:41:51.36#ibcon#flushed, iclass 29, count 2 2006.285.13:41:51.36#ibcon#about to write, iclass 29, count 2 2006.285.13:41:51.36#ibcon#wrote, iclass 29, count 2 2006.285.13:41:51.36#ibcon#about to read 3, iclass 29, count 2 2006.285.13:41:51.38#ibcon#read 3, iclass 29, count 2 2006.285.13:41:51.38#ibcon#about to read 4, iclass 29, count 2 2006.285.13:41:51.38#ibcon#read 4, iclass 29, count 2 2006.285.13:41:51.38#ibcon#about to read 5, iclass 29, count 2 2006.285.13:41:51.38#ibcon#read 5, iclass 29, count 2 2006.285.13:41:51.38#ibcon#about to read 6, iclass 29, count 2 2006.285.13:41:51.38#ibcon#read 6, iclass 29, count 2 2006.285.13:41:51.38#ibcon#end of sib2, iclass 29, count 2 2006.285.13:41:51.38#ibcon#*mode == 0, iclass 29, count 2 2006.285.13:41:51.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.13:41:51.38#ibcon#[27=AT08-04\r\n] 2006.285.13:41:51.38#ibcon#*before write, iclass 29, count 2 2006.285.13:41:51.38#ibcon#enter sib2, iclass 29, count 2 2006.285.13:41:51.38#ibcon#flushed, iclass 29, count 2 2006.285.13:41:51.38#ibcon#about to write, iclass 29, count 2 2006.285.13:41:51.38#ibcon#wrote, iclass 29, count 2 2006.285.13:41:51.38#ibcon#about to read 3, iclass 29, count 2 2006.285.13:41:51.41#ibcon#read 3, iclass 29, count 2 2006.285.13:41:51.41#ibcon#about to read 4, iclass 29, count 2 2006.285.13:41:51.41#ibcon#read 4, iclass 29, count 2 2006.285.13:41:51.41#ibcon#about to read 5, iclass 29, count 2 2006.285.13:41:51.41#ibcon#read 5, iclass 29, count 2 2006.285.13:41:51.41#ibcon#about to read 6, iclass 29, count 2 2006.285.13:41:51.41#ibcon#read 6, iclass 29, count 2 2006.285.13:41:51.41#ibcon#end of sib2, iclass 29, count 2 2006.285.13:41:51.41#ibcon#*after write, iclass 29, count 2 2006.285.13:41:51.41#ibcon#*before return 0, iclass 29, count 2 2006.285.13:41:51.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:41:51.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:41:51.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.13:41:51.41#ibcon#ireg 7 cls_cnt 0 2006.285.13:41:51.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:41:51.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:41:51.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:41:51.53#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:41:51.53#ibcon#first serial, iclass 29, count 0 2006.285.13:41:51.53#ibcon#enter sib2, iclass 29, count 0 2006.285.13:41:51.53#ibcon#flushed, iclass 29, count 0 2006.285.13:41:51.53#ibcon#about to write, iclass 29, count 0 2006.285.13:41:51.53#ibcon#wrote, iclass 29, count 0 2006.285.13:41:51.53#ibcon#about to read 3, iclass 29, count 0 2006.285.13:41:51.55#ibcon#read 3, iclass 29, count 0 2006.285.13:41:51.55#ibcon#about to read 4, iclass 29, count 0 2006.285.13:41:51.55#ibcon#read 4, iclass 29, count 0 2006.285.13:41:51.55#ibcon#about to read 5, iclass 29, count 0 2006.285.13:41:51.55#ibcon#read 5, iclass 29, count 0 2006.285.13:41:51.55#ibcon#about to read 6, iclass 29, count 0 2006.285.13:41:51.55#ibcon#read 6, iclass 29, count 0 2006.285.13:41:51.55#ibcon#end of sib2, iclass 29, count 0 2006.285.13:41:51.55#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:41:51.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:41:51.55#ibcon#[27=USB\r\n] 2006.285.13:41:51.55#ibcon#*before write, iclass 29, count 0 2006.285.13:41:51.55#ibcon#enter sib2, iclass 29, count 0 2006.285.13:41:51.55#ibcon#flushed, iclass 29, count 0 2006.285.13:41:51.55#ibcon#about to write, iclass 29, count 0 2006.285.13:41:51.55#ibcon#wrote, iclass 29, count 0 2006.285.13:41:51.55#ibcon#about to read 3, iclass 29, count 0 2006.285.13:41:51.58#ibcon#read 3, iclass 29, count 0 2006.285.13:41:51.58#ibcon#about to read 4, iclass 29, count 0 2006.285.13:41:51.58#ibcon#read 4, iclass 29, count 0 2006.285.13:41:51.58#ibcon#about to read 5, iclass 29, count 0 2006.285.13:41:51.58#ibcon#read 5, iclass 29, count 0 2006.285.13:41:51.58#ibcon#about to read 6, iclass 29, count 0 2006.285.13:41:51.58#ibcon#read 6, iclass 29, count 0 2006.285.13:41:51.58#ibcon#end of sib2, iclass 29, count 0 2006.285.13:41:51.58#ibcon#*after write, iclass 29, count 0 2006.285.13:41:51.58#ibcon#*before return 0, iclass 29, count 0 2006.285.13:41:51.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:41:51.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:41:51.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:41:51.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:41:51.58$vck44/vabw=wide 2006.285.13:41:51.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.13:41:51.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.13:41:51.58#ibcon#ireg 8 cls_cnt 0 2006.285.13:41:51.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:41:51.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:41:51.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:41:51.58#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:41:51.58#ibcon#first serial, iclass 31, count 0 2006.285.13:41:51.58#ibcon#enter sib2, iclass 31, count 0 2006.285.13:41:51.58#ibcon#flushed, iclass 31, count 0 2006.285.13:41:51.58#ibcon#about to write, iclass 31, count 0 2006.285.13:41:51.58#ibcon#wrote, iclass 31, count 0 2006.285.13:41:51.58#ibcon#about to read 3, iclass 31, count 0 2006.285.13:41:51.60#ibcon#read 3, iclass 31, count 0 2006.285.13:41:51.60#ibcon#about to read 4, iclass 31, count 0 2006.285.13:41:51.60#ibcon#read 4, iclass 31, count 0 2006.285.13:41:51.60#ibcon#about to read 5, iclass 31, count 0 2006.285.13:41:51.60#ibcon#read 5, iclass 31, count 0 2006.285.13:41:51.60#ibcon#about to read 6, iclass 31, count 0 2006.285.13:41:51.60#ibcon#read 6, iclass 31, count 0 2006.285.13:41:51.60#ibcon#end of sib2, iclass 31, count 0 2006.285.13:41:51.60#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:41:51.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:41:51.60#ibcon#[25=BW32\r\n] 2006.285.13:41:51.60#ibcon#*before write, iclass 31, count 0 2006.285.13:41:51.60#ibcon#enter sib2, iclass 31, count 0 2006.285.13:41:51.60#ibcon#flushed, iclass 31, count 0 2006.285.13:41:51.60#ibcon#about to write, iclass 31, count 0 2006.285.13:41:51.60#ibcon#wrote, iclass 31, count 0 2006.285.13:41:51.60#ibcon#about to read 3, iclass 31, count 0 2006.285.13:41:51.63#ibcon#read 3, iclass 31, count 0 2006.285.13:41:51.63#ibcon#about to read 4, iclass 31, count 0 2006.285.13:41:51.63#ibcon#read 4, iclass 31, count 0 2006.285.13:41:51.63#ibcon#about to read 5, iclass 31, count 0 2006.285.13:41:51.63#ibcon#read 5, iclass 31, count 0 2006.285.13:41:51.63#ibcon#about to read 6, iclass 31, count 0 2006.285.13:41:51.63#ibcon#read 6, iclass 31, count 0 2006.285.13:41:51.63#ibcon#end of sib2, iclass 31, count 0 2006.285.13:41:51.63#ibcon#*after write, iclass 31, count 0 2006.285.13:41:51.63#ibcon#*before return 0, iclass 31, count 0 2006.285.13:41:51.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:41:51.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:41:51.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:41:51.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:41:51.63$vck44/vbbw=wide 2006.285.13:41:51.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.13:41:51.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.13:41:51.63#ibcon#ireg 8 cls_cnt 0 2006.285.13:41:51.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:41:51.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:41:51.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:41:51.70#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:41:51.70#ibcon#first serial, iclass 33, count 0 2006.285.13:41:51.70#ibcon#enter sib2, iclass 33, count 0 2006.285.13:41:51.70#ibcon#flushed, iclass 33, count 0 2006.285.13:41:51.70#ibcon#about to write, iclass 33, count 0 2006.285.13:41:51.70#ibcon#wrote, iclass 33, count 0 2006.285.13:41:51.70#ibcon#about to read 3, iclass 33, count 0 2006.285.13:41:51.72#ibcon#read 3, iclass 33, count 0 2006.285.13:41:51.72#ibcon#about to read 4, iclass 33, count 0 2006.285.13:41:51.72#ibcon#read 4, iclass 33, count 0 2006.285.13:41:51.72#ibcon#about to read 5, iclass 33, count 0 2006.285.13:41:51.72#ibcon#read 5, iclass 33, count 0 2006.285.13:41:51.72#ibcon#about to read 6, iclass 33, count 0 2006.285.13:41:51.72#ibcon#read 6, iclass 33, count 0 2006.285.13:41:51.72#ibcon#end of sib2, iclass 33, count 0 2006.285.13:41:51.72#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:41:51.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:41:51.72#ibcon#[27=BW32\r\n] 2006.285.13:41:51.72#ibcon#*before write, iclass 33, count 0 2006.285.13:41:51.72#ibcon#enter sib2, iclass 33, count 0 2006.285.13:41:51.72#ibcon#flushed, iclass 33, count 0 2006.285.13:41:51.72#ibcon#about to write, iclass 33, count 0 2006.285.13:41:51.72#ibcon#wrote, iclass 33, count 0 2006.285.13:41:51.72#ibcon#about to read 3, iclass 33, count 0 2006.285.13:41:51.75#ibcon#read 3, iclass 33, count 0 2006.285.13:41:51.75#ibcon#about to read 4, iclass 33, count 0 2006.285.13:41:51.75#ibcon#read 4, iclass 33, count 0 2006.285.13:41:51.75#ibcon#about to read 5, iclass 33, count 0 2006.285.13:41:51.75#ibcon#read 5, iclass 33, count 0 2006.285.13:41:51.75#ibcon#about to read 6, iclass 33, count 0 2006.285.13:41:51.75#ibcon#read 6, iclass 33, count 0 2006.285.13:41:51.75#ibcon#end of sib2, iclass 33, count 0 2006.285.13:41:51.75#ibcon#*after write, iclass 33, count 0 2006.285.13:41:51.75#ibcon#*before return 0, iclass 33, count 0 2006.285.13:41:51.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:41:51.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:41:51.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:41:51.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:41:51.75$setupk4/ifdk4 2006.285.13:41:51.75$ifdk4/lo= 2006.285.13:41:51.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:41:51.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:41:51.75$ifdk4/patch= 2006.285.13:41:51.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:41:51.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:41:51.76$setupk4/!*+20s 2006.285.13:41:52.90#abcon#<5=/04 1.2 2.6 19.11 981015.3\r\n> 2006.285.13:41:52.92#abcon#{5=INTERFACE CLEAR} 2006.285.13:41:52.98#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:42:03.07#abcon#<5=/04 1.2 2.6 19.11 981015.2\r\n> 2006.285.13:42:03.09#abcon#{5=INTERFACE CLEAR} 2006.285.13:42:03.15#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:42:05.57$setupk4/"tpicd 2006.285.13:42:05.57$setupk4/echo=off 2006.285.13:42:05.57$setupk4/xlog=off 2006.285.13:42:05.57:!2006.285.13:45:59 2006.285.13:42:24.14#trakl#Source acquired 2006.285.13:42:25.14#flagr#flagr/antenna,acquired 2006.285.13:45:59.00:preob 2006.285.13:45:59.13/onsource/TRACKING 2006.285.13:45:59.13:!2006.285.13:46:09 2006.285.13:46:09.00:"tape 2006.285.13:46:09.00:"st=record 2006.285.13:46:09.00:data_valid=on 2006.285.13:46:09.00:midob 2006.285.13:46:10.13/onsource/TRACKING 2006.285.13:46:10.13/wx/19.06,1015.3,98 2006.285.13:46:10.35/cable/+6.4975E-03 2006.285.13:46:11.44/va/01,07,usb,yes,34,37 2006.285.13:46:11.44/va/02,06,usb,yes,34,35 2006.285.13:46:11.44/va/03,07,usb,yes,34,35 2006.285.13:46:11.44/va/04,06,usb,yes,35,37 2006.285.13:46:11.44/va/05,03,usb,yes,35,35 2006.285.13:46:11.44/va/06,04,usb,yes,31,31 2006.285.13:46:11.44/va/07,04,usb,yes,32,32 2006.285.13:46:11.44/va/08,03,usb,yes,33,39 2006.285.13:46:11.67/valo/01,524.99,yes,locked 2006.285.13:46:11.67/valo/02,534.99,yes,locked 2006.285.13:46:11.67/valo/03,564.99,yes,locked 2006.285.13:46:11.67/valo/04,624.99,yes,locked 2006.285.13:46:11.67/valo/05,734.99,yes,locked 2006.285.13:46:11.67/valo/06,814.99,yes,locked 2006.285.13:46:11.67/valo/07,864.99,yes,locked 2006.285.13:46:11.67/valo/08,884.99,yes,locked 2006.285.13:46:12.76/vb/01,04,usb,yes,31,31 2006.285.13:46:12.76/vb/02,05,usb,yes,29,31 2006.285.13:46:12.76/vb/03,04,usb,yes,30,33 2006.285.13:46:12.76/vb/04,05,usb,yes,30,29 2006.285.13:46:12.76/vb/05,04,usb,yes,27,29 2006.285.13:46:12.76/vb/06,03,usb,yes,39,35 2006.285.13:46:12.76/vb/07,04,usb,yes,31,31 2006.285.13:46:12.76/vb/08,04,usb,yes,28,32 2006.285.13:46:12.99/vblo/01,629.99,yes,locked 2006.285.13:46:12.99/vblo/02,634.99,yes,locked 2006.285.13:46:12.99/vblo/03,649.99,yes,locked 2006.285.13:46:12.99/vblo/04,679.99,yes,locked 2006.285.13:46:12.99/vblo/05,709.99,yes,locked 2006.285.13:46:12.99/vblo/06,719.99,yes,locked 2006.285.13:46:12.99/vblo/07,734.99,yes,locked 2006.285.13:46:12.99/vblo/08,744.99,yes,locked 2006.285.13:46:13.14/vabw/8 2006.285.13:46:13.29/vbbw/8 2006.285.13:46:13.38/xfe/off,on,12.0 2006.285.13:46:13.77/ifatt/23,28,28,28 2006.285.13:46:14.07/fmout-gps/S +2.70E-07 2006.285.13:46:14.09:!2006.285.13:50:09 2006.285.13:50:09.01:data_valid=off 2006.285.13:50:09.01:"et 2006.285.13:50:09.01:!+3s 2006.285.13:50:12.02:"tape 2006.285.13:50:12.02:postob 2006.285.13:50:12.11/cable/+6.4987E-03 2006.285.13:50:12.11/wx/19.05,1015.3,98 2006.285.13:50:12.17/fmout-gps/S +2.62E-07 2006.285.13:50:12.17:scan_name=285-1351,jd0610,50 2006.285.13:50:12.17:source=0552+398,055530.81,394849.2,2000.0,cw 2006.285.13:50:13.14#flagr#flagr/antenna,new-source 2006.285.13:50:13.14:checkk5 2006.285.13:50:13.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:50:13.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:50:14.44/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:50:14.84/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:50:15.46/chk_obsdata//k5ts1/T2851346??a.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.13:50:15.83/chk_obsdata//k5ts2/T2851346??b.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.13:50:16.43/chk_obsdata//k5ts3/T2851346??c.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.13:50:16.90/chk_obsdata//k5ts4/T2851346??d.dat file size is correct (nominal:960MB, actual:960MB). 2006.285.13:50:17.80/k5log//k5ts1_log_newline 2006.285.13:50:18.64/k5log//k5ts2_log_newline 2006.285.13:50:19.47/k5log//k5ts3_log_newline 2006.285.13:50:20.28/k5log//k5ts4_log_newline 2006.285.13:50:20.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:50:20.31:setupk4=1 2006.285.13:50:20.31$setupk4/echo=on 2006.285.13:50:20.31$setupk4/pcalon 2006.285.13:50:20.31$pcalon/"no phase cal control is implemented here 2006.285.13:50:20.31$setupk4/"tpicd=stop 2006.285.13:50:20.31$setupk4/"rec=synch_on 2006.285.13:50:20.31$setupk4/"rec_mode=128 2006.285.13:50:20.31$setupk4/!* 2006.285.13:50:20.31$setupk4/recpk4 2006.285.13:50:20.31$recpk4/recpatch= 2006.285.13:50:20.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:50:20.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:50:20.31$setupk4/vck44 2006.285.13:50:20.31$vck44/valo=1,524.99 2006.285.13:50:20.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.13:50:20.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.13:50:20.31#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:20.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:50:20.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:50:20.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:50:20.31#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:50:20.31#ibcon#first serial, iclass 17, count 0 2006.285.13:50:20.31#ibcon#enter sib2, iclass 17, count 0 2006.285.13:50:20.31#ibcon#flushed, iclass 17, count 0 2006.285.13:50:20.31#ibcon#about to write, iclass 17, count 0 2006.285.13:50:20.31#ibcon#wrote, iclass 17, count 0 2006.285.13:50:20.31#ibcon#about to read 3, iclass 17, count 0 2006.285.13:50:20.33#ibcon#read 3, iclass 17, count 0 2006.285.13:50:20.33#ibcon#about to read 4, iclass 17, count 0 2006.285.13:50:20.33#ibcon#read 4, iclass 17, count 0 2006.285.13:50:20.33#ibcon#about to read 5, iclass 17, count 0 2006.285.13:50:20.33#ibcon#read 5, iclass 17, count 0 2006.285.13:50:20.33#ibcon#about to read 6, iclass 17, count 0 2006.285.13:50:20.33#ibcon#read 6, iclass 17, count 0 2006.285.13:50:20.33#ibcon#end of sib2, iclass 17, count 0 2006.285.13:50:20.33#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:50:20.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:50:20.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:50:20.33#ibcon#*before write, iclass 17, count 0 2006.285.13:50:20.33#ibcon#enter sib2, iclass 17, count 0 2006.285.13:50:20.33#ibcon#flushed, iclass 17, count 0 2006.285.13:50:20.33#ibcon#about to write, iclass 17, count 0 2006.285.13:50:20.33#ibcon#wrote, iclass 17, count 0 2006.285.13:50:20.33#ibcon#about to read 3, iclass 17, count 0 2006.285.13:50:20.38#ibcon#read 3, iclass 17, count 0 2006.285.13:50:20.38#ibcon#about to read 4, iclass 17, count 0 2006.285.13:50:20.38#ibcon#read 4, iclass 17, count 0 2006.285.13:50:20.38#ibcon#about to read 5, iclass 17, count 0 2006.285.13:50:20.38#ibcon#read 5, iclass 17, count 0 2006.285.13:50:20.38#ibcon#about to read 6, iclass 17, count 0 2006.285.13:50:20.38#ibcon#read 6, iclass 17, count 0 2006.285.13:50:20.38#ibcon#end of sib2, iclass 17, count 0 2006.285.13:50:20.38#ibcon#*after write, iclass 17, count 0 2006.285.13:50:20.38#ibcon#*before return 0, iclass 17, count 0 2006.285.13:50:20.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:50:20.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:50:20.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:50:20.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:50:20.38$vck44/va=1,7 2006.285.13:50:20.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.13:50:20.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.13:50:20.38#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:20.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:50:20.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:50:20.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:50:20.38#ibcon#enter wrdev, iclass 19, count 2 2006.285.13:50:20.38#ibcon#first serial, iclass 19, count 2 2006.285.13:50:20.38#ibcon#enter sib2, iclass 19, count 2 2006.285.13:50:20.38#ibcon#flushed, iclass 19, count 2 2006.285.13:50:20.38#ibcon#about to write, iclass 19, count 2 2006.285.13:50:20.38#ibcon#wrote, iclass 19, count 2 2006.285.13:50:20.38#ibcon#about to read 3, iclass 19, count 2 2006.285.13:50:20.40#ibcon#read 3, iclass 19, count 2 2006.285.13:50:20.40#ibcon#about to read 4, iclass 19, count 2 2006.285.13:50:20.40#ibcon#read 4, iclass 19, count 2 2006.285.13:50:20.40#ibcon#about to read 5, iclass 19, count 2 2006.285.13:50:20.40#ibcon#read 5, iclass 19, count 2 2006.285.13:50:20.40#ibcon#about to read 6, iclass 19, count 2 2006.285.13:50:20.40#ibcon#read 6, iclass 19, count 2 2006.285.13:50:20.40#ibcon#end of sib2, iclass 19, count 2 2006.285.13:50:20.40#ibcon#*mode == 0, iclass 19, count 2 2006.285.13:50:20.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.13:50:20.40#ibcon#[25=AT01-07\r\n] 2006.285.13:50:20.40#ibcon#*before write, iclass 19, count 2 2006.285.13:50:20.40#ibcon#enter sib2, iclass 19, count 2 2006.285.13:50:20.40#ibcon#flushed, iclass 19, count 2 2006.285.13:50:20.40#ibcon#about to write, iclass 19, count 2 2006.285.13:50:20.40#ibcon#wrote, iclass 19, count 2 2006.285.13:50:20.40#ibcon#about to read 3, iclass 19, count 2 2006.285.13:50:20.43#ibcon#read 3, iclass 19, count 2 2006.285.13:50:20.43#ibcon#about to read 4, iclass 19, count 2 2006.285.13:50:20.43#ibcon#read 4, iclass 19, count 2 2006.285.13:50:20.43#ibcon#about to read 5, iclass 19, count 2 2006.285.13:50:20.43#ibcon#read 5, iclass 19, count 2 2006.285.13:50:20.43#ibcon#about to read 6, iclass 19, count 2 2006.285.13:50:20.43#ibcon#read 6, iclass 19, count 2 2006.285.13:50:20.43#ibcon#end of sib2, iclass 19, count 2 2006.285.13:50:20.43#ibcon#*after write, iclass 19, count 2 2006.285.13:50:20.43#ibcon#*before return 0, iclass 19, count 2 2006.285.13:50:20.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:50:20.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:50:20.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.13:50:20.43#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:20.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:50:20.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:50:20.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:50:20.55#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:50:20.55#ibcon#first serial, iclass 19, count 0 2006.285.13:50:20.55#ibcon#enter sib2, iclass 19, count 0 2006.285.13:50:20.55#ibcon#flushed, iclass 19, count 0 2006.285.13:50:20.55#ibcon#about to write, iclass 19, count 0 2006.285.13:50:20.55#ibcon#wrote, iclass 19, count 0 2006.285.13:50:20.55#ibcon#about to read 3, iclass 19, count 0 2006.285.13:50:20.57#ibcon#read 3, iclass 19, count 0 2006.285.13:50:20.57#ibcon#about to read 4, iclass 19, count 0 2006.285.13:50:20.57#ibcon#read 4, iclass 19, count 0 2006.285.13:50:20.57#ibcon#about to read 5, iclass 19, count 0 2006.285.13:50:20.57#ibcon#read 5, iclass 19, count 0 2006.285.13:50:20.57#ibcon#about to read 6, iclass 19, count 0 2006.285.13:50:20.57#ibcon#read 6, iclass 19, count 0 2006.285.13:50:20.57#ibcon#end of sib2, iclass 19, count 0 2006.285.13:50:20.57#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:50:20.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:50:20.57#ibcon#[25=USB\r\n] 2006.285.13:50:20.57#ibcon#*before write, iclass 19, count 0 2006.285.13:50:20.57#ibcon#enter sib2, iclass 19, count 0 2006.285.13:50:20.57#ibcon#flushed, iclass 19, count 0 2006.285.13:50:20.57#ibcon#about to write, iclass 19, count 0 2006.285.13:50:20.57#ibcon#wrote, iclass 19, count 0 2006.285.13:50:20.57#ibcon#about to read 3, iclass 19, count 0 2006.285.13:50:20.60#ibcon#read 3, iclass 19, count 0 2006.285.13:50:20.60#ibcon#about to read 4, iclass 19, count 0 2006.285.13:50:20.60#ibcon#read 4, iclass 19, count 0 2006.285.13:50:20.60#ibcon#about to read 5, iclass 19, count 0 2006.285.13:50:20.60#ibcon#read 5, iclass 19, count 0 2006.285.13:50:20.60#ibcon#about to read 6, iclass 19, count 0 2006.285.13:50:20.60#ibcon#read 6, iclass 19, count 0 2006.285.13:50:20.60#ibcon#end of sib2, iclass 19, count 0 2006.285.13:50:20.60#ibcon#*after write, iclass 19, count 0 2006.285.13:50:20.60#ibcon#*before return 0, iclass 19, count 0 2006.285.13:50:20.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:50:20.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:50:20.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:50:20.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:50:20.60$vck44/valo=2,534.99 2006.285.13:50:20.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.13:50:20.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.13:50:20.60#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:20.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:50:20.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:50:20.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:50:20.60#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:50:20.60#ibcon#first serial, iclass 21, count 0 2006.285.13:50:20.60#ibcon#enter sib2, iclass 21, count 0 2006.285.13:50:20.60#ibcon#flushed, iclass 21, count 0 2006.285.13:50:20.60#ibcon#about to write, iclass 21, count 0 2006.285.13:50:20.60#ibcon#wrote, iclass 21, count 0 2006.285.13:50:20.60#ibcon#about to read 3, iclass 21, count 0 2006.285.13:50:20.62#ibcon#read 3, iclass 21, count 0 2006.285.13:50:20.62#ibcon#about to read 4, iclass 21, count 0 2006.285.13:50:20.62#ibcon#read 4, iclass 21, count 0 2006.285.13:50:20.62#ibcon#about to read 5, iclass 21, count 0 2006.285.13:50:20.62#ibcon#read 5, iclass 21, count 0 2006.285.13:50:20.62#ibcon#about to read 6, iclass 21, count 0 2006.285.13:50:20.62#ibcon#read 6, iclass 21, count 0 2006.285.13:50:20.62#ibcon#end of sib2, iclass 21, count 0 2006.285.13:50:20.62#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:50:20.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:50:20.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:50:20.62#ibcon#*before write, iclass 21, count 0 2006.285.13:50:20.62#ibcon#enter sib2, iclass 21, count 0 2006.285.13:50:20.62#ibcon#flushed, iclass 21, count 0 2006.285.13:50:20.62#ibcon#about to write, iclass 21, count 0 2006.285.13:50:20.62#ibcon#wrote, iclass 21, count 0 2006.285.13:50:20.62#ibcon#about to read 3, iclass 21, count 0 2006.285.13:50:20.66#ibcon#read 3, iclass 21, count 0 2006.285.13:50:20.66#ibcon#about to read 4, iclass 21, count 0 2006.285.13:50:20.66#ibcon#read 4, iclass 21, count 0 2006.285.13:50:20.66#ibcon#about to read 5, iclass 21, count 0 2006.285.13:50:20.66#ibcon#read 5, iclass 21, count 0 2006.285.13:50:20.66#ibcon#about to read 6, iclass 21, count 0 2006.285.13:50:20.66#ibcon#read 6, iclass 21, count 0 2006.285.13:50:20.66#ibcon#end of sib2, iclass 21, count 0 2006.285.13:50:20.66#ibcon#*after write, iclass 21, count 0 2006.285.13:50:20.66#ibcon#*before return 0, iclass 21, count 0 2006.285.13:50:20.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:50:20.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:50:20.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:50:20.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:50:20.66$vck44/va=2,6 2006.285.13:50:20.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.13:50:20.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.13:50:20.66#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:20.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:50:20.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:50:20.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:50:20.72#ibcon#enter wrdev, iclass 23, count 2 2006.285.13:50:20.72#ibcon#first serial, iclass 23, count 2 2006.285.13:50:20.72#ibcon#enter sib2, iclass 23, count 2 2006.285.13:50:20.72#ibcon#flushed, iclass 23, count 2 2006.285.13:50:20.72#ibcon#about to write, iclass 23, count 2 2006.285.13:50:20.72#ibcon#wrote, iclass 23, count 2 2006.285.13:50:20.72#ibcon#about to read 3, iclass 23, count 2 2006.285.13:50:20.74#ibcon#read 3, iclass 23, count 2 2006.285.13:50:20.74#ibcon#about to read 4, iclass 23, count 2 2006.285.13:50:20.74#ibcon#read 4, iclass 23, count 2 2006.285.13:50:20.74#ibcon#about to read 5, iclass 23, count 2 2006.285.13:50:20.74#ibcon#read 5, iclass 23, count 2 2006.285.13:50:20.74#ibcon#about to read 6, iclass 23, count 2 2006.285.13:50:20.74#ibcon#read 6, iclass 23, count 2 2006.285.13:50:20.74#ibcon#end of sib2, iclass 23, count 2 2006.285.13:50:20.74#ibcon#*mode == 0, iclass 23, count 2 2006.285.13:50:20.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.13:50:20.74#ibcon#[25=AT02-06\r\n] 2006.285.13:50:20.74#ibcon#*before write, iclass 23, count 2 2006.285.13:50:20.74#ibcon#enter sib2, iclass 23, count 2 2006.285.13:50:20.74#ibcon#flushed, iclass 23, count 2 2006.285.13:50:20.74#ibcon#about to write, iclass 23, count 2 2006.285.13:50:20.74#ibcon#wrote, iclass 23, count 2 2006.285.13:50:20.74#ibcon#about to read 3, iclass 23, count 2 2006.285.13:50:20.77#ibcon#read 3, iclass 23, count 2 2006.285.13:50:20.77#ibcon#about to read 4, iclass 23, count 2 2006.285.13:50:20.77#ibcon#read 4, iclass 23, count 2 2006.285.13:50:20.77#ibcon#about to read 5, iclass 23, count 2 2006.285.13:50:20.77#ibcon#read 5, iclass 23, count 2 2006.285.13:50:20.77#ibcon#about to read 6, iclass 23, count 2 2006.285.13:50:20.77#ibcon#read 6, iclass 23, count 2 2006.285.13:50:20.77#ibcon#end of sib2, iclass 23, count 2 2006.285.13:50:20.77#ibcon#*after write, iclass 23, count 2 2006.285.13:50:20.77#ibcon#*before return 0, iclass 23, count 2 2006.285.13:50:20.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:50:20.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:50:20.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.13:50:20.77#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:20.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:50:20.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:50:20.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:50:20.89#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:50:20.89#ibcon#first serial, iclass 23, count 0 2006.285.13:50:20.89#ibcon#enter sib2, iclass 23, count 0 2006.285.13:50:20.89#ibcon#flushed, iclass 23, count 0 2006.285.13:50:20.89#ibcon#about to write, iclass 23, count 0 2006.285.13:50:20.89#ibcon#wrote, iclass 23, count 0 2006.285.13:50:20.89#ibcon#about to read 3, iclass 23, count 0 2006.285.13:50:20.91#ibcon#read 3, iclass 23, count 0 2006.285.13:50:20.91#ibcon#about to read 4, iclass 23, count 0 2006.285.13:50:20.91#ibcon#read 4, iclass 23, count 0 2006.285.13:50:20.91#ibcon#about to read 5, iclass 23, count 0 2006.285.13:50:20.91#ibcon#read 5, iclass 23, count 0 2006.285.13:50:20.91#ibcon#about to read 6, iclass 23, count 0 2006.285.13:50:20.91#ibcon#read 6, iclass 23, count 0 2006.285.13:50:20.91#ibcon#end of sib2, iclass 23, count 0 2006.285.13:50:20.91#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:50:20.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:50:20.91#ibcon#[25=USB\r\n] 2006.285.13:50:20.91#ibcon#*before write, iclass 23, count 0 2006.285.13:50:20.91#ibcon#enter sib2, iclass 23, count 0 2006.285.13:50:20.91#ibcon#flushed, iclass 23, count 0 2006.285.13:50:20.91#ibcon#about to write, iclass 23, count 0 2006.285.13:50:20.91#ibcon#wrote, iclass 23, count 0 2006.285.13:50:20.91#ibcon#about to read 3, iclass 23, count 0 2006.285.13:50:20.94#ibcon#read 3, iclass 23, count 0 2006.285.13:50:20.94#ibcon#about to read 4, iclass 23, count 0 2006.285.13:50:20.94#ibcon#read 4, iclass 23, count 0 2006.285.13:50:20.94#ibcon#about to read 5, iclass 23, count 0 2006.285.13:50:20.94#ibcon#read 5, iclass 23, count 0 2006.285.13:50:20.94#ibcon#about to read 6, iclass 23, count 0 2006.285.13:50:20.94#ibcon#read 6, iclass 23, count 0 2006.285.13:50:20.94#ibcon#end of sib2, iclass 23, count 0 2006.285.13:50:20.94#ibcon#*after write, iclass 23, count 0 2006.285.13:50:20.94#ibcon#*before return 0, iclass 23, count 0 2006.285.13:50:20.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:50:20.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:50:20.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:50:20.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:50:20.94$vck44/valo=3,564.99 2006.285.13:50:20.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.13:50:20.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.13:50:20.94#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:20.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:50:20.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:50:20.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:50:20.94#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:50:20.94#ibcon#first serial, iclass 25, count 0 2006.285.13:50:20.94#ibcon#enter sib2, iclass 25, count 0 2006.285.13:50:20.94#ibcon#flushed, iclass 25, count 0 2006.285.13:50:20.94#ibcon#about to write, iclass 25, count 0 2006.285.13:50:20.94#ibcon#wrote, iclass 25, count 0 2006.285.13:50:20.94#ibcon#about to read 3, iclass 25, count 0 2006.285.13:50:20.96#ibcon#read 3, iclass 25, count 0 2006.285.13:50:20.96#ibcon#about to read 4, iclass 25, count 0 2006.285.13:50:20.96#ibcon#read 4, iclass 25, count 0 2006.285.13:50:20.96#ibcon#about to read 5, iclass 25, count 0 2006.285.13:50:20.96#ibcon#read 5, iclass 25, count 0 2006.285.13:50:20.96#ibcon#about to read 6, iclass 25, count 0 2006.285.13:50:20.96#ibcon#read 6, iclass 25, count 0 2006.285.13:50:20.96#ibcon#end of sib2, iclass 25, count 0 2006.285.13:50:20.96#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:50:20.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:50:20.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:50:20.96#ibcon#*before write, iclass 25, count 0 2006.285.13:50:20.96#ibcon#enter sib2, iclass 25, count 0 2006.285.13:50:20.96#ibcon#flushed, iclass 25, count 0 2006.285.13:50:20.96#ibcon#about to write, iclass 25, count 0 2006.285.13:50:20.96#ibcon#wrote, iclass 25, count 0 2006.285.13:50:20.96#ibcon#about to read 3, iclass 25, count 0 2006.285.13:50:21.00#ibcon#read 3, iclass 25, count 0 2006.285.13:50:21.00#ibcon#about to read 4, iclass 25, count 0 2006.285.13:50:21.00#ibcon#read 4, iclass 25, count 0 2006.285.13:50:21.00#ibcon#about to read 5, iclass 25, count 0 2006.285.13:50:21.00#ibcon#read 5, iclass 25, count 0 2006.285.13:50:21.00#ibcon#about to read 6, iclass 25, count 0 2006.285.13:50:21.00#ibcon#read 6, iclass 25, count 0 2006.285.13:50:21.00#ibcon#end of sib2, iclass 25, count 0 2006.285.13:50:21.00#ibcon#*after write, iclass 25, count 0 2006.285.13:50:21.00#ibcon#*before return 0, iclass 25, count 0 2006.285.13:50:21.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:50:21.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.13:50:21.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:50:21.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:50:21.00$vck44/va=3,7 2006.285.13:50:21.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.13:50:21.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.13:50:21.00#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:21.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:50:21.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:50:21.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:50:21.06#ibcon#enter wrdev, iclass 27, count 2 2006.285.13:50:21.06#ibcon#first serial, iclass 27, count 2 2006.285.13:50:21.06#ibcon#enter sib2, iclass 27, count 2 2006.285.13:50:21.06#ibcon#flushed, iclass 27, count 2 2006.285.13:50:21.06#ibcon#about to write, iclass 27, count 2 2006.285.13:50:21.06#ibcon#wrote, iclass 27, count 2 2006.285.13:50:21.06#ibcon#about to read 3, iclass 27, count 2 2006.285.13:50:21.08#ibcon#read 3, iclass 27, count 2 2006.285.13:50:21.08#ibcon#about to read 4, iclass 27, count 2 2006.285.13:50:21.08#ibcon#read 4, iclass 27, count 2 2006.285.13:50:21.08#ibcon#about to read 5, iclass 27, count 2 2006.285.13:50:21.08#ibcon#read 5, iclass 27, count 2 2006.285.13:50:21.08#ibcon#about to read 6, iclass 27, count 2 2006.285.13:50:21.08#ibcon#read 6, iclass 27, count 2 2006.285.13:50:21.08#ibcon#end of sib2, iclass 27, count 2 2006.285.13:50:21.08#ibcon#*mode == 0, iclass 27, count 2 2006.285.13:50:21.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.13:50:21.08#ibcon#[25=AT03-07\r\n] 2006.285.13:50:21.08#ibcon#*before write, iclass 27, count 2 2006.285.13:50:21.08#ibcon#enter sib2, iclass 27, count 2 2006.285.13:50:21.08#ibcon#flushed, iclass 27, count 2 2006.285.13:50:21.08#ibcon#about to write, iclass 27, count 2 2006.285.13:50:21.08#ibcon#wrote, iclass 27, count 2 2006.285.13:50:21.08#ibcon#about to read 3, iclass 27, count 2 2006.285.13:50:21.11#ibcon#read 3, iclass 27, count 2 2006.285.13:50:21.11#ibcon#about to read 4, iclass 27, count 2 2006.285.13:50:21.11#ibcon#read 4, iclass 27, count 2 2006.285.13:50:21.11#ibcon#about to read 5, iclass 27, count 2 2006.285.13:50:21.11#ibcon#read 5, iclass 27, count 2 2006.285.13:50:21.11#ibcon#about to read 6, iclass 27, count 2 2006.285.13:50:21.11#ibcon#read 6, iclass 27, count 2 2006.285.13:50:21.11#ibcon#end of sib2, iclass 27, count 2 2006.285.13:50:21.11#ibcon#*after write, iclass 27, count 2 2006.285.13:50:21.11#ibcon#*before return 0, iclass 27, count 2 2006.285.13:50:21.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:50:21.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.13:50:21.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.13:50:21.11#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:21.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:50:21.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:50:21.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:50:21.50#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:50:21.50#ibcon#first serial, iclass 27, count 0 2006.285.13:50:21.50#ibcon#enter sib2, iclass 27, count 0 2006.285.13:50:21.50#ibcon#flushed, iclass 27, count 0 2006.285.13:50:21.50#ibcon#about to write, iclass 27, count 0 2006.285.13:50:21.50#ibcon#wrote, iclass 27, count 0 2006.285.13:50:21.50#ibcon#about to read 3, iclass 27, count 0 2006.285.13:50:21.52#ibcon#read 3, iclass 27, count 0 2006.285.13:50:21.52#ibcon#about to read 4, iclass 27, count 0 2006.285.13:50:21.52#ibcon#read 4, iclass 27, count 0 2006.285.13:50:21.52#ibcon#about to read 5, iclass 27, count 0 2006.285.13:50:21.52#ibcon#read 5, iclass 27, count 0 2006.285.13:50:21.52#ibcon#about to read 6, iclass 27, count 0 2006.285.13:50:21.52#ibcon#read 6, iclass 27, count 0 2006.285.13:50:21.52#ibcon#end of sib2, iclass 27, count 0 2006.285.13:50:21.52#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:50:21.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:50:21.52#ibcon#[25=USB\r\n] 2006.285.13:50:21.52#ibcon#*before write, iclass 27, count 0 2006.285.13:50:21.52#ibcon#enter sib2, iclass 27, count 0 2006.285.13:50:21.52#ibcon#flushed, iclass 27, count 0 2006.285.13:50:21.52#ibcon#about to write, iclass 27, count 0 2006.285.13:50:21.52#ibcon#wrote, iclass 27, count 0 2006.285.13:50:21.52#ibcon#about to read 3, iclass 27, count 0 2006.285.13:50:21.55#ibcon#read 3, iclass 27, count 0 2006.285.13:50:21.55#ibcon#about to read 4, iclass 27, count 0 2006.285.13:50:21.55#ibcon#read 4, iclass 27, count 0 2006.285.13:50:21.55#ibcon#about to read 5, iclass 27, count 0 2006.285.13:50:21.55#ibcon#read 5, iclass 27, count 0 2006.285.13:50:21.55#ibcon#about to read 6, iclass 27, count 0 2006.285.13:50:21.55#ibcon#read 6, iclass 27, count 0 2006.285.13:50:21.55#ibcon#end of sib2, iclass 27, count 0 2006.285.13:50:21.55#ibcon#*after write, iclass 27, count 0 2006.285.13:50:21.55#ibcon#*before return 0, iclass 27, count 0 2006.285.13:50:21.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:50:21.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.13:50:21.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:50:21.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:50:21.55$vck44/valo=4,624.99 2006.285.13:50:21.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.13:50:21.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.13:50:21.55#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:21.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:50:21.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:50:21.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:50:21.55#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:50:21.55#ibcon#first serial, iclass 29, count 0 2006.285.13:50:21.55#ibcon#enter sib2, iclass 29, count 0 2006.285.13:50:21.55#ibcon#flushed, iclass 29, count 0 2006.285.13:50:21.55#ibcon#about to write, iclass 29, count 0 2006.285.13:50:21.55#ibcon#wrote, iclass 29, count 0 2006.285.13:50:21.55#ibcon#about to read 3, iclass 29, count 0 2006.285.13:50:21.57#ibcon#read 3, iclass 29, count 0 2006.285.13:50:21.57#ibcon#about to read 4, iclass 29, count 0 2006.285.13:50:21.57#ibcon#read 4, iclass 29, count 0 2006.285.13:50:21.57#ibcon#about to read 5, iclass 29, count 0 2006.285.13:50:21.57#ibcon#read 5, iclass 29, count 0 2006.285.13:50:21.57#ibcon#about to read 6, iclass 29, count 0 2006.285.13:50:21.57#ibcon#read 6, iclass 29, count 0 2006.285.13:50:21.57#ibcon#end of sib2, iclass 29, count 0 2006.285.13:50:21.57#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:50:21.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:50:21.57#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:50:21.57#ibcon#*before write, iclass 29, count 0 2006.285.13:50:21.57#ibcon#enter sib2, iclass 29, count 0 2006.285.13:50:21.57#ibcon#flushed, iclass 29, count 0 2006.285.13:50:21.57#ibcon#about to write, iclass 29, count 0 2006.285.13:50:21.57#ibcon#wrote, iclass 29, count 0 2006.285.13:50:21.57#ibcon#about to read 3, iclass 29, count 0 2006.285.13:50:21.61#ibcon#read 3, iclass 29, count 0 2006.285.13:50:21.61#ibcon#about to read 4, iclass 29, count 0 2006.285.13:50:21.61#ibcon#read 4, iclass 29, count 0 2006.285.13:50:21.61#ibcon#about to read 5, iclass 29, count 0 2006.285.13:50:21.61#ibcon#read 5, iclass 29, count 0 2006.285.13:50:21.61#ibcon#about to read 6, iclass 29, count 0 2006.285.13:50:21.61#ibcon#read 6, iclass 29, count 0 2006.285.13:50:21.61#ibcon#end of sib2, iclass 29, count 0 2006.285.13:50:21.61#ibcon#*after write, iclass 29, count 0 2006.285.13:50:21.61#ibcon#*before return 0, iclass 29, count 0 2006.285.13:50:21.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:50:21.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:50:21.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:50:21.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:50:21.61$vck44/va=4,6 2006.285.13:50:21.61#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.13:50:21.61#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.13:50:21.61#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:21.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:50:21.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:50:21.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:50:21.67#ibcon#enter wrdev, iclass 31, count 2 2006.285.13:50:21.67#ibcon#first serial, iclass 31, count 2 2006.285.13:50:21.67#ibcon#enter sib2, iclass 31, count 2 2006.285.13:50:21.67#ibcon#flushed, iclass 31, count 2 2006.285.13:50:21.67#ibcon#about to write, iclass 31, count 2 2006.285.13:50:21.67#ibcon#wrote, iclass 31, count 2 2006.285.13:50:21.67#ibcon#about to read 3, iclass 31, count 2 2006.285.13:50:21.69#ibcon#read 3, iclass 31, count 2 2006.285.13:50:21.69#ibcon#about to read 4, iclass 31, count 2 2006.285.13:50:21.69#ibcon#read 4, iclass 31, count 2 2006.285.13:50:21.69#ibcon#about to read 5, iclass 31, count 2 2006.285.13:50:21.69#ibcon#read 5, iclass 31, count 2 2006.285.13:50:21.69#ibcon#about to read 6, iclass 31, count 2 2006.285.13:50:21.69#ibcon#read 6, iclass 31, count 2 2006.285.13:50:21.69#ibcon#end of sib2, iclass 31, count 2 2006.285.13:50:21.69#ibcon#*mode == 0, iclass 31, count 2 2006.285.13:50:21.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.13:50:21.69#ibcon#[25=AT04-06\r\n] 2006.285.13:50:21.69#ibcon#*before write, iclass 31, count 2 2006.285.13:50:21.69#ibcon#enter sib2, iclass 31, count 2 2006.285.13:50:21.69#ibcon#flushed, iclass 31, count 2 2006.285.13:50:21.69#ibcon#about to write, iclass 31, count 2 2006.285.13:50:21.69#ibcon#wrote, iclass 31, count 2 2006.285.13:50:21.69#ibcon#about to read 3, iclass 31, count 2 2006.285.13:50:21.72#ibcon#read 3, iclass 31, count 2 2006.285.13:50:21.72#ibcon#about to read 4, iclass 31, count 2 2006.285.13:50:21.72#ibcon#read 4, iclass 31, count 2 2006.285.13:50:21.72#ibcon#about to read 5, iclass 31, count 2 2006.285.13:50:21.72#ibcon#read 5, iclass 31, count 2 2006.285.13:50:21.72#ibcon#about to read 6, iclass 31, count 2 2006.285.13:50:21.72#ibcon#read 6, iclass 31, count 2 2006.285.13:50:21.72#ibcon#end of sib2, iclass 31, count 2 2006.285.13:50:21.72#ibcon#*after write, iclass 31, count 2 2006.285.13:50:21.72#ibcon#*before return 0, iclass 31, count 2 2006.285.13:50:21.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:50:21.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:50:21.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.13:50:21.72#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:21.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:50:21.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:50:21.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:50:21.84#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:50:21.84#ibcon#first serial, iclass 31, count 0 2006.285.13:50:21.84#ibcon#enter sib2, iclass 31, count 0 2006.285.13:50:21.84#ibcon#flushed, iclass 31, count 0 2006.285.13:50:21.84#ibcon#about to write, iclass 31, count 0 2006.285.13:50:21.84#ibcon#wrote, iclass 31, count 0 2006.285.13:50:21.84#ibcon#about to read 3, iclass 31, count 0 2006.285.13:50:21.86#ibcon#read 3, iclass 31, count 0 2006.285.13:50:21.86#ibcon#about to read 4, iclass 31, count 0 2006.285.13:50:21.86#ibcon#read 4, iclass 31, count 0 2006.285.13:50:21.86#ibcon#about to read 5, iclass 31, count 0 2006.285.13:50:21.86#ibcon#read 5, iclass 31, count 0 2006.285.13:50:21.86#ibcon#about to read 6, iclass 31, count 0 2006.285.13:50:21.86#ibcon#read 6, iclass 31, count 0 2006.285.13:50:21.86#ibcon#end of sib2, iclass 31, count 0 2006.285.13:50:21.86#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:50:21.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:50:21.86#ibcon#[25=USB\r\n] 2006.285.13:50:21.86#ibcon#*before write, iclass 31, count 0 2006.285.13:50:21.86#ibcon#enter sib2, iclass 31, count 0 2006.285.13:50:21.86#ibcon#flushed, iclass 31, count 0 2006.285.13:50:21.86#ibcon#about to write, iclass 31, count 0 2006.285.13:50:21.86#ibcon#wrote, iclass 31, count 0 2006.285.13:50:21.86#ibcon#about to read 3, iclass 31, count 0 2006.285.13:50:21.89#ibcon#read 3, iclass 31, count 0 2006.285.13:50:21.89#ibcon#about to read 4, iclass 31, count 0 2006.285.13:50:21.89#ibcon#read 4, iclass 31, count 0 2006.285.13:50:21.89#ibcon#about to read 5, iclass 31, count 0 2006.285.13:50:21.89#ibcon#read 5, iclass 31, count 0 2006.285.13:50:21.89#ibcon#about to read 6, iclass 31, count 0 2006.285.13:50:21.89#ibcon#read 6, iclass 31, count 0 2006.285.13:50:21.89#ibcon#end of sib2, iclass 31, count 0 2006.285.13:50:21.89#ibcon#*after write, iclass 31, count 0 2006.285.13:50:21.89#ibcon#*before return 0, iclass 31, count 0 2006.285.13:50:21.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:50:21.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:50:21.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:50:21.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:50:21.89$vck44/valo=5,734.99 2006.285.13:50:21.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.13:50:22.05#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.13:50:22.05#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:22.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:50:22.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:50:22.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:50:22.05#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:50:22.05#ibcon#first serial, iclass 33, count 0 2006.285.13:50:22.05#ibcon#enter sib2, iclass 33, count 0 2006.285.13:50:22.05#ibcon#flushed, iclass 33, count 0 2006.285.13:50:22.05#ibcon#about to write, iclass 33, count 0 2006.285.13:50:22.05#ibcon#wrote, iclass 33, count 0 2006.285.13:50:22.05#ibcon#about to read 3, iclass 33, count 0 2006.285.13:50:22.07#ibcon#read 3, iclass 33, count 0 2006.285.13:50:22.07#ibcon#about to read 4, iclass 33, count 0 2006.285.13:50:22.07#ibcon#read 4, iclass 33, count 0 2006.285.13:50:22.07#ibcon#about to read 5, iclass 33, count 0 2006.285.13:50:22.07#ibcon#read 5, iclass 33, count 0 2006.285.13:50:22.07#ibcon#about to read 6, iclass 33, count 0 2006.285.13:50:22.07#ibcon#read 6, iclass 33, count 0 2006.285.13:50:22.07#ibcon#end of sib2, iclass 33, count 0 2006.285.13:50:22.07#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:50:22.07#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:50:22.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:50:22.07#ibcon#*before write, iclass 33, count 0 2006.285.13:50:22.07#ibcon#enter sib2, iclass 33, count 0 2006.285.13:50:22.07#ibcon#flushed, iclass 33, count 0 2006.285.13:50:22.07#ibcon#about to write, iclass 33, count 0 2006.285.13:50:22.07#ibcon#wrote, iclass 33, count 0 2006.285.13:50:22.07#ibcon#about to read 3, iclass 33, count 0 2006.285.13:50:22.11#ibcon#read 3, iclass 33, count 0 2006.285.13:50:22.11#ibcon#about to read 4, iclass 33, count 0 2006.285.13:50:22.11#ibcon#read 4, iclass 33, count 0 2006.285.13:50:22.11#ibcon#about to read 5, iclass 33, count 0 2006.285.13:50:22.11#ibcon#read 5, iclass 33, count 0 2006.285.13:50:22.11#ibcon#about to read 6, iclass 33, count 0 2006.285.13:50:22.11#ibcon#read 6, iclass 33, count 0 2006.285.13:50:22.11#ibcon#end of sib2, iclass 33, count 0 2006.285.13:50:22.11#ibcon#*after write, iclass 33, count 0 2006.285.13:50:22.11#ibcon#*before return 0, iclass 33, count 0 2006.285.13:50:22.11#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:50:22.11#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:50:22.11#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:50:22.11#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:50:22.11$vck44/va=5,3 2006.285.13:50:22.11#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.13:50:22.11#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.13:50:22.11#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:22.11#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:50:22.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:50:22.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:50:22.11#ibcon#enter wrdev, iclass 35, count 2 2006.285.13:50:22.11#ibcon#first serial, iclass 35, count 2 2006.285.13:50:22.11#ibcon#enter sib2, iclass 35, count 2 2006.285.13:50:22.11#ibcon#flushed, iclass 35, count 2 2006.285.13:50:22.11#ibcon#about to write, iclass 35, count 2 2006.285.13:50:22.11#ibcon#wrote, iclass 35, count 2 2006.285.13:50:22.11#ibcon#about to read 3, iclass 35, count 2 2006.285.13:50:22.13#ibcon#read 3, iclass 35, count 2 2006.285.13:50:22.13#ibcon#about to read 4, iclass 35, count 2 2006.285.13:50:22.13#ibcon#read 4, iclass 35, count 2 2006.285.13:50:22.13#ibcon#about to read 5, iclass 35, count 2 2006.285.13:50:22.13#ibcon#read 5, iclass 35, count 2 2006.285.13:50:22.13#ibcon#about to read 6, iclass 35, count 2 2006.285.13:50:22.13#ibcon#read 6, iclass 35, count 2 2006.285.13:50:22.13#ibcon#end of sib2, iclass 35, count 2 2006.285.13:50:22.13#ibcon#*mode == 0, iclass 35, count 2 2006.285.13:50:22.13#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.13:50:22.13#ibcon#[25=AT05-03\r\n] 2006.285.13:50:22.13#ibcon#*before write, iclass 35, count 2 2006.285.13:50:22.13#ibcon#enter sib2, iclass 35, count 2 2006.285.13:50:22.13#ibcon#flushed, iclass 35, count 2 2006.285.13:50:22.13#ibcon#about to write, iclass 35, count 2 2006.285.13:50:22.13#ibcon#wrote, iclass 35, count 2 2006.285.13:50:22.13#ibcon#about to read 3, iclass 35, count 2 2006.285.13:50:22.16#ibcon#read 3, iclass 35, count 2 2006.285.13:50:22.16#ibcon#about to read 4, iclass 35, count 2 2006.285.13:50:22.16#ibcon#read 4, iclass 35, count 2 2006.285.13:50:22.16#ibcon#about to read 5, iclass 35, count 2 2006.285.13:50:22.16#ibcon#read 5, iclass 35, count 2 2006.285.13:50:22.16#ibcon#about to read 6, iclass 35, count 2 2006.285.13:50:22.16#ibcon#read 6, iclass 35, count 2 2006.285.13:50:22.16#ibcon#end of sib2, iclass 35, count 2 2006.285.13:50:22.16#ibcon#*after write, iclass 35, count 2 2006.285.13:50:22.16#ibcon#*before return 0, iclass 35, count 2 2006.285.13:50:22.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:50:22.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:50:22.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.13:50:22.16#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:22.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:50:22.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:50:22.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:50:22.28#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:50:22.28#ibcon#first serial, iclass 35, count 0 2006.285.13:50:22.28#ibcon#enter sib2, iclass 35, count 0 2006.285.13:50:22.28#ibcon#flushed, iclass 35, count 0 2006.285.13:50:22.28#ibcon#about to write, iclass 35, count 0 2006.285.13:50:22.28#ibcon#wrote, iclass 35, count 0 2006.285.13:50:22.28#ibcon#about to read 3, iclass 35, count 0 2006.285.13:50:22.30#ibcon#read 3, iclass 35, count 0 2006.285.13:50:22.30#ibcon#about to read 4, iclass 35, count 0 2006.285.13:50:22.30#ibcon#read 4, iclass 35, count 0 2006.285.13:50:22.30#ibcon#about to read 5, iclass 35, count 0 2006.285.13:50:22.30#ibcon#read 5, iclass 35, count 0 2006.285.13:50:22.30#ibcon#about to read 6, iclass 35, count 0 2006.285.13:50:22.30#ibcon#read 6, iclass 35, count 0 2006.285.13:50:22.30#ibcon#end of sib2, iclass 35, count 0 2006.285.13:50:22.30#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:50:22.30#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:50:22.30#ibcon#[25=USB\r\n] 2006.285.13:50:22.30#ibcon#*before write, iclass 35, count 0 2006.285.13:50:22.30#ibcon#enter sib2, iclass 35, count 0 2006.285.13:50:22.30#ibcon#flushed, iclass 35, count 0 2006.285.13:50:22.30#ibcon#about to write, iclass 35, count 0 2006.285.13:50:22.30#ibcon#wrote, iclass 35, count 0 2006.285.13:50:22.30#ibcon#about to read 3, iclass 35, count 0 2006.285.13:50:22.33#ibcon#read 3, iclass 35, count 0 2006.285.13:50:22.33#ibcon#about to read 4, iclass 35, count 0 2006.285.13:50:22.33#ibcon#read 4, iclass 35, count 0 2006.285.13:50:22.33#ibcon#about to read 5, iclass 35, count 0 2006.285.13:50:22.33#ibcon#read 5, iclass 35, count 0 2006.285.13:50:22.33#ibcon#about to read 6, iclass 35, count 0 2006.285.13:50:22.33#ibcon#read 6, iclass 35, count 0 2006.285.13:50:22.33#ibcon#end of sib2, iclass 35, count 0 2006.285.13:50:22.33#ibcon#*after write, iclass 35, count 0 2006.285.13:50:22.33#ibcon#*before return 0, iclass 35, count 0 2006.285.13:50:22.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:50:22.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:50:22.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:50:22.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:50:22.33$vck44/valo=6,814.99 2006.285.13:50:22.33#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.13:50:22.33#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.13:50:22.33#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:22.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:50:22.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:50:22.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:50:22.33#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:50:22.33#ibcon#first serial, iclass 37, count 0 2006.285.13:50:22.33#ibcon#enter sib2, iclass 37, count 0 2006.285.13:50:22.33#ibcon#flushed, iclass 37, count 0 2006.285.13:50:22.33#ibcon#about to write, iclass 37, count 0 2006.285.13:50:22.33#ibcon#wrote, iclass 37, count 0 2006.285.13:50:22.33#ibcon#about to read 3, iclass 37, count 0 2006.285.13:50:22.35#ibcon#read 3, iclass 37, count 0 2006.285.13:50:22.35#ibcon#about to read 4, iclass 37, count 0 2006.285.13:50:22.35#ibcon#read 4, iclass 37, count 0 2006.285.13:50:22.35#ibcon#about to read 5, iclass 37, count 0 2006.285.13:50:22.35#ibcon#read 5, iclass 37, count 0 2006.285.13:50:22.35#ibcon#about to read 6, iclass 37, count 0 2006.285.13:50:22.35#ibcon#read 6, iclass 37, count 0 2006.285.13:50:22.35#ibcon#end of sib2, iclass 37, count 0 2006.285.13:50:22.35#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:50:22.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:50:22.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:50:22.35#ibcon#*before write, iclass 37, count 0 2006.285.13:50:22.35#ibcon#enter sib2, iclass 37, count 0 2006.285.13:50:22.35#ibcon#flushed, iclass 37, count 0 2006.285.13:50:22.35#ibcon#about to write, iclass 37, count 0 2006.285.13:50:22.35#ibcon#wrote, iclass 37, count 0 2006.285.13:50:22.35#ibcon#about to read 3, iclass 37, count 0 2006.285.13:50:22.39#ibcon#read 3, iclass 37, count 0 2006.285.13:50:22.39#ibcon#about to read 4, iclass 37, count 0 2006.285.13:50:22.39#ibcon#read 4, iclass 37, count 0 2006.285.13:50:22.39#ibcon#about to read 5, iclass 37, count 0 2006.285.13:50:22.39#ibcon#read 5, iclass 37, count 0 2006.285.13:50:22.39#ibcon#about to read 6, iclass 37, count 0 2006.285.13:50:22.39#ibcon#read 6, iclass 37, count 0 2006.285.13:50:22.39#ibcon#end of sib2, iclass 37, count 0 2006.285.13:50:22.39#ibcon#*after write, iclass 37, count 0 2006.285.13:50:22.39#ibcon#*before return 0, iclass 37, count 0 2006.285.13:50:22.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:50:22.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:50:22.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:50:22.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:50:22.39$vck44/va=6,4 2006.285.13:50:22.46#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.13:50:22.46#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.13:50:22.46#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:22.46#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:50:22.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:50:22.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:50:22.46#ibcon#enter wrdev, iclass 39, count 2 2006.285.13:50:22.46#ibcon#first serial, iclass 39, count 2 2006.285.13:50:22.46#ibcon#enter sib2, iclass 39, count 2 2006.285.13:50:22.46#ibcon#flushed, iclass 39, count 2 2006.285.13:50:22.46#ibcon#about to write, iclass 39, count 2 2006.285.13:50:22.46#ibcon#wrote, iclass 39, count 2 2006.285.13:50:22.46#ibcon#about to read 3, iclass 39, count 2 2006.285.13:50:22.47#ibcon#read 3, iclass 39, count 2 2006.285.13:50:22.47#ibcon#about to read 4, iclass 39, count 2 2006.285.13:50:22.47#ibcon#read 4, iclass 39, count 2 2006.285.13:50:22.47#ibcon#about to read 5, iclass 39, count 2 2006.285.13:50:22.47#ibcon#read 5, iclass 39, count 2 2006.285.13:50:22.47#ibcon#about to read 6, iclass 39, count 2 2006.285.13:50:22.47#ibcon#read 6, iclass 39, count 2 2006.285.13:50:22.47#ibcon#end of sib2, iclass 39, count 2 2006.285.13:50:22.47#ibcon#*mode == 0, iclass 39, count 2 2006.285.13:50:22.47#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.13:50:22.47#ibcon#[25=AT06-04\r\n] 2006.285.13:50:22.47#ibcon#*before write, iclass 39, count 2 2006.285.13:50:22.47#ibcon#enter sib2, iclass 39, count 2 2006.285.13:50:22.47#ibcon#flushed, iclass 39, count 2 2006.285.13:50:22.47#ibcon#about to write, iclass 39, count 2 2006.285.13:50:22.47#ibcon#wrote, iclass 39, count 2 2006.285.13:50:22.47#ibcon#about to read 3, iclass 39, count 2 2006.285.13:50:22.50#ibcon#read 3, iclass 39, count 2 2006.285.13:50:22.50#ibcon#about to read 4, iclass 39, count 2 2006.285.13:50:22.50#ibcon#read 4, iclass 39, count 2 2006.285.13:50:22.50#ibcon#about to read 5, iclass 39, count 2 2006.285.13:50:22.50#ibcon#read 5, iclass 39, count 2 2006.285.13:50:22.50#ibcon#about to read 6, iclass 39, count 2 2006.285.13:50:22.50#ibcon#read 6, iclass 39, count 2 2006.285.13:50:22.50#ibcon#end of sib2, iclass 39, count 2 2006.285.13:50:22.50#ibcon#*after write, iclass 39, count 2 2006.285.13:50:22.50#ibcon#*before return 0, iclass 39, count 2 2006.285.13:50:22.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:50:22.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:50:22.50#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.13:50:22.50#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:22.50#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:50:22.62#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:50:22.62#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:50:22.62#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:50:22.62#ibcon#first serial, iclass 39, count 0 2006.285.13:50:22.62#ibcon#enter sib2, iclass 39, count 0 2006.285.13:50:22.62#ibcon#flushed, iclass 39, count 0 2006.285.13:50:22.62#ibcon#about to write, iclass 39, count 0 2006.285.13:50:22.62#ibcon#wrote, iclass 39, count 0 2006.285.13:50:22.62#ibcon#about to read 3, iclass 39, count 0 2006.285.13:50:22.64#ibcon#read 3, iclass 39, count 0 2006.285.13:50:22.64#ibcon#about to read 4, iclass 39, count 0 2006.285.13:50:22.64#ibcon#read 4, iclass 39, count 0 2006.285.13:50:22.64#ibcon#about to read 5, iclass 39, count 0 2006.285.13:50:22.64#ibcon#read 5, iclass 39, count 0 2006.285.13:50:22.64#ibcon#about to read 6, iclass 39, count 0 2006.285.13:50:22.64#ibcon#read 6, iclass 39, count 0 2006.285.13:50:22.64#ibcon#end of sib2, iclass 39, count 0 2006.285.13:50:22.64#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:50:22.64#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:50:22.64#ibcon#[25=USB\r\n] 2006.285.13:50:22.64#ibcon#*before write, iclass 39, count 0 2006.285.13:50:22.64#ibcon#enter sib2, iclass 39, count 0 2006.285.13:50:22.64#ibcon#flushed, iclass 39, count 0 2006.285.13:50:22.64#ibcon#about to write, iclass 39, count 0 2006.285.13:50:22.64#ibcon#wrote, iclass 39, count 0 2006.285.13:50:22.64#ibcon#about to read 3, iclass 39, count 0 2006.285.13:50:22.67#ibcon#read 3, iclass 39, count 0 2006.285.13:50:22.67#ibcon#about to read 4, iclass 39, count 0 2006.285.13:50:22.67#ibcon#read 4, iclass 39, count 0 2006.285.13:50:22.67#ibcon#about to read 5, iclass 39, count 0 2006.285.13:50:22.67#ibcon#read 5, iclass 39, count 0 2006.285.13:50:22.67#ibcon#about to read 6, iclass 39, count 0 2006.285.13:50:22.67#ibcon#read 6, iclass 39, count 0 2006.285.13:50:22.67#ibcon#end of sib2, iclass 39, count 0 2006.285.13:50:22.67#ibcon#*after write, iclass 39, count 0 2006.285.13:50:22.67#ibcon#*before return 0, iclass 39, count 0 2006.285.13:50:22.67#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:50:22.67#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:50:22.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:50:22.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:50:22.67$vck44/valo=7,864.99 2006.285.13:50:22.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.13:50:22.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.13:50:22.67#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:22.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:50:22.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:50:22.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:50:22.67#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:50:22.67#ibcon#first serial, iclass 3, count 0 2006.285.13:50:22.67#ibcon#enter sib2, iclass 3, count 0 2006.285.13:50:22.67#ibcon#flushed, iclass 3, count 0 2006.285.13:50:22.67#ibcon#about to write, iclass 3, count 0 2006.285.13:50:22.67#ibcon#wrote, iclass 3, count 0 2006.285.13:50:22.67#ibcon#about to read 3, iclass 3, count 0 2006.285.13:50:22.69#ibcon#read 3, iclass 3, count 0 2006.285.13:50:22.69#ibcon#about to read 4, iclass 3, count 0 2006.285.13:50:22.69#ibcon#read 4, iclass 3, count 0 2006.285.13:50:22.69#ibcon#about to read 5, iclass 3, count 0 2006.285.13:50:22.69#ibcon#read 5, iclass 3, count 0 2006.285.13:50:22.69#ibcon#about to read 6, iclass 3, count 0 2006.285.13:50:22.69#ibcon#read 6, iclass 3, count 0 2006.285.13:50:22.69#ibcon#end of sib2, iclass 3, count 0 2006.285.13:50:22.69#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:50:22.69#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:50:22.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:50:22.69#ibcon#*before write, iclass 3, count 0 2006.285.13:50:22.69#ibcon#enter sib2, iclass 3, count 0 2006.285.13:50:22.69#ibcon#flushed, iclass 3, count 0 2006.285.13:50:22.69#ibcon#about to write, iclass 3, count 0 2006.285.13:50:22.69#ibcon#wrote, iclass 3, count 0 2006.285.13:50:22.69#ibcon#about to read 3, iclass 3, count 0 2006.285.13:50:22.73#ibcon#read 3, iclass 3, count 0 2006.285.13:50:22.73#ibcon#about to read 4, iclass 3, count 0 2006.285.13:50:22.73#ibcon#read 4, iclass 3, count 0 2006.285.13:50:22.73#ibcon#about to read 5, iclass 3, count 0 2006.285.13:50:22.73#ibcon#read 5, iclass 3, count 0 2006.285.13:50:22.73#ibcon#about to read 6, iclass 3, count 0 2006.285.13:50:22.73#ibcon#read 6, iclass 3, count 0 2006.285.13:50:22.73#ibcon#end of sib2, iclass 3, count 0 2006.285.13:50:22.73#ibcon#*after write, iclass 3, count 0 2006.285.13:50:22.73#ibcon#*before return 0, iclass 3, count 0 2006.285.13:50:22.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:50:22.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:50:22.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:50:22.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:50:22.73$vck44/va=7,4 2006.285.13:50:22.73#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.13:50:22.73#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.13:50:22.73#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:22.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:50:22.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:50:22.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:50:22.79#ibcon#enter wrdev, iclass 5, count 2 2006.285.13:50:22.79#ibcon#first serial, iclass 5, count 2 2006.285.13:50:22.79#ibcon#enter sib2, iclass 5, count 2 2006.285.13:50:22.79#ibcon#flushed, iclass 5, count 2 2006.285.13:50:22.79#ibcon#about to write, iclass 5, count 2 2006.285.13:50:22.79#ibcon#wrote, iclass 5, count 2 2006.285.13:50:22.79#ibcon#about to read 3, iclass 5, count 2 2006.285.13:50:22.81#ibcon#read 3, iclass 5, count 2 2006.285.13:50:22.81#ibcon#about to read 4, iclass 5, count 2 2006.285.13:50:22.81#ibcon#read 4, iclass 5, count 2 2006.285.13:50:22.81#ibcon#about to read 5, iclass 5, count 2 2006.285.13:50:22.81#ibcon#read 5, iclass 5, count 2 2006.285.13:50:22.81#ibcon#about to read 6, iclass 5, count 2 2006.285.13:50:22.81#ibcon#read 6, iclass 5, count 2 2006.285.13:50:22.81#ibcon#end of sib2, iclass 5, count 2 2006.285.13:50:22.81#ibcon#*mode == 0, iclass 5, count 2 2006.285.13:50:22.81#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.13:50:22.81#ibcon#[25=AT07-04\r\n] 2006.285.13:50:22.81#ibcon#*before write, iclass 5, count 2 2006.285.13:50:22.81#ibcon#enter sib2, iclass 5, count 2 2006.285.13:50:22.81#ibcon#flushed, iclass 5, count 2 2006.285.13:50:22.81#ibcon#about to write, iclass 5, count 2 2006.285.13:50:22.81#ibcon#wrote, iclass 5, count 2 2006.285.13:50:22.81#ibcon#about to read 3, iclass 5, count 2 2006.285.13:50:22.84#ibcon#read 3, iclass 5, count 2 2006.285.13:50:22.84#ibcon#about to read 4, iclass 5, count 2 2006.285.13:50:22.84#ibcon#read 4, iclass 5, count 2 2006.285.13:50:22.84#ibcon#about to read 5, iclass 5, count 2 2006.285.13:50:22.84#ibcon#read 5, iclass 5, count 2 2006.285.13:50:22.84#ibcon#about to read 6, iclass 5, count 2 2006.285.13:50:22.84#ibcon#read 6, iclass 5, count 2 2006.285.13:50:22.84#ibcon#end of sib2, iclass 5, count 2 2006.285.13:50:22.84#ibcon#*after write, iclass 5, count 2 2006.285.13:50:22.84#ibcon#*before return 0, iclass 5, count 2 2006.285.13:50:22.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:50:22.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:50:22.84#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.13:50:22.84#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:22.84#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:50:22.96#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:50:22.96#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:50:22.96#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:50:22.96#ibcon#first serial, iclass 5, count 0 2006.285.13:50:22.96#ibcon#enter sib2, iclass 5, count 0 2006.285.13:50:22.96#ibcon#flushed, iclass 5, count 0 2006.285.13:50:22.96#ibcon#about to write, iclass 5, count 0 2006.285.13:50:22.96#ibcon#wrote, iclass 5, count 0 2006.285.13:50:22.96#ibcon#about to read 3, iclass 5, count 0 2006.285.13:50:22.98#ibcon#read 3, iclass 5, count 0 2006.285.13:50:22.98#ibcon#about to read 4, iclass 5, count 0 2006.285.13:50:22.98#ibcon#read 4, iclass 5, count 0 2006.285.13:50:22.98#ibcon#about to read 5, iclass 5, count 0 2006.285.13:50:22.98#ibcon#read 5, iclass 5, count 0 2006.285.13:50:22.98#ibcon#about to read 6, iclass 5, count 0 2006.285.13:50:22.98#ibcon#read 6, iclass 5, count 0 2006.285.13:50:22.98#ibcon#end of sib2, iclass 5, count 0 2006.285.13:50:22.98#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:50:22.98#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:50:22.98#ibcon#[25=USB\r\n] 2006.285.13:50:22.98#ibcon#*before write, iclass 5, count 0 2006.285.13:50:22.98#ibcon#enter sib2, iclass 5, count 0 2006.285.13:50:22.98#ibcon#flushed, iclass 5, count 0 2006.285.13:50:22.98#ibcon#about to write, iclass 5, count 0 2006.285.13:50:22.98#ibcon#wrote, iclass 5, count 0 2006.285.13:50:22.98#ibcon#about to read 3, iclass 5, count 0 2006.285.13:50:23.01#ibcon#read 3, iclass 5, count 0 2006.285.13:50:23.01#ibcon#about to read 4, iclass 5, count 0 2006.285.13:50:23.01#ibcon#read 4, iclass 5, count 0 2006.285.13:50:23.01#ibcon#about to read 5, iclass 5, count 0 2006.285.13:50:23.01#ibcon#read 5, iclass 5, count 0 2006.285.13:50:23.01#ibcon#about to read 6, iclass 5, count 0 2006.285.13:50:23.01#ibcon#read 6, iclass 5, count 0 2006.285.13:50:23.01#ibcon#end of sib2, iclass 5, count 0 2006.285.13:50:23.01#ibcon#*after write, iclass 5, count 0 2006.285.13:50:23.01#ibcon#*before return 0, iclass 5, count 0 2006.285.13:50:23.01#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:50:23.01#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:50:23.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:50:23.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:50:23.01$vck44/valo=8,884.99 2006.285.13:50:23.01#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.13:50:23.01#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.13:50:23.01#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:23.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:50:23.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:50:23.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:50:23.01#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:50:23.01#ibcon#first serial, iclass 7, count 0 2006.285.13:50:23.01#ibcon#enter sib2, iclass 7, count 0 2006.285.13:50:23.01#ibcon#flushed, iclass 7, count 0 2006.285.13:50:23.01#ibcon#about to write, iclass 7, count 0 2006.285.13:50:23.01#ibcon#wrote, iclass 7, count 0 2006.285.13:50:23.01#ibcon#about to read 3, iclass 7, count 0 2006.285.13:50:23.03#ibcon#read 3, iclass 7, count 0 2006.285.13:50:23.03#ibcon#about to read 4, iclass 7, count 0 2006.285.13:50:23.03#ibcon#read 4, iclass 7, count 0 2006.285.13:50:23.03#ibcon#about to read 5, iclass 7, count 0 2006.285.13:50:23.03#ibcon#read 5, iclass 7, count 0 2006.285.13:50:23.03#ibcon#about to read 6, iclass 7, count 0 2006.285.13:50:23.03#ibcon#read 6, iclass 7, count 0 2006.285.13:50:23.03#ibcon#end of sib2, iclass 7, count 0 2006.285.13:50:23.03#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:50:23.03#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:50:23.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:50:23.03#ibcon#*before write, iclass 7, count 0 2006.285.13:50:23.03#ibcon#enter sib2, iclass 7, count 0 2006.285.13:50:23.03#ibcon#flushed, iclass 7, count 0 2006.285.13:50:23.03#ibcon#about to write, iclass 7, count 0 2006.285.13:50:23.03#ibcon#wrote, iclass 7, count 0 2006.285.13:50:23.03#ibcon#about to read 3, iclass 7, count 0 2006.285.13:50:23.07#ibcon#read 3, iclass 7, count 0 2006.285.13:50:23.07#ibcon#about to read 4, iclass 7, count 0 2006.285.13:50:23.07#ibcon#read 4, iclass 7, count 0 2006.285.13:50:23.07#ibcon#about to read 5, iclass 7, count 0 2006.285.13:50:23.07#ibcon#read 5, iclass 7, count 0 2006.285.13:50:23.07#ibcon#about to read 6, iclass 7, count 0 2006.285.13:50:23.07#ibcon#read 6, iclass 7, count 0 2006.285.13:50:23.07#ibcon#end of sib2, iclass 7, count 0 2006.285.13:50:23.07#ibcon#*after write, iclass 7, count 0 2006.285.13:50:23.07#ibcon#*before return 0, iclass 7, count 0 2006.285.13:50:23.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:50:23.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:50:23.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:50:23.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:50:23.07$vck44/va=8,3 2006.285.13:50:23.07#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.13:50:23.07#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.13:50:23.07#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:23.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:50:23.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:50:23.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:50:23.13#ibcon#enter wrdev, iclass 11, count 2 2006.285.13:50:23.13#ibcon#first serial, iclass 11, count 2 2006.285.13:50:23.13#ibcon#enter sib2, iclass 11, count 2 2006.285.13:50:23.13#ibcon#flushed, iclass 11, count 2 2006.285.13:50:23.13#ibcon#about to write, iclass 11, count 2 2006.285.13:50:23.13#ibcon#wrote, iclass 11, count 2 2006.285.13:50:23.13#ibcon#about to read 3, iclass 11, count 2 2006.285.13:50:23.15#ibcon#read 3, iclass 11, count 2 2006.285.13:50:23.15#ibcon#about to read 4, iclass 11, count 2 2006.285.13:50:23.15#ibcon#read 4, iclass 11, count 2 2006.285.13:50:23.15#ibcon#about to read 5, iclass 11, count 2 2006.285.13:50:23.15#ibcon#read 5, iclass 11, count 2 2006.285.13:50:23.15#ibcon#about to read 6, iclass 11, count 2 2006.285.13:50:23.15#ibcon#read 6, iclass 11, count 2 2006.285.13:50:23.15#ibcon#end of sib2, iclass 11, count 2 2006.285.13:50:23.15#ibcon#*mode == 0, iclass 11, count 2 2006.285.13:50:23.15#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.13:50:23.15#ibcon#[25=AT08-03\r\n] 2006.285.13:50:23.15#ibcon#*before write, iclass 11, count 2 2006.285.13:50:23.15#ibcon#enter sib2, iclass 11, count 2 2006.285.13:50:23.15#ibcon#flushed, iclass 11, count 2 2006.285.13:50:23.15#ibcon#about to write, iclass 11, count 2 2006.285.13:50:23.15#ibcon#wrote, iclass 11, count 2 2006.285.13:50:23.15#ibcon#about to read 3, iclass 11, count 2 2006.285.13:50:23.18#ibcon#read 3, iclass 11, count 2 2006.285.13:50:23.36#ibcon#about to read 4, iclass 11, count 2 2006.285.13:50:23.36#ibcon#read 4, iclass 11, count 2 2006.285.13:50:23.36#ibcon#about to read 5, iclass 11, count 2 2006.285.13:50:23.36#ibcon#read 5, iclass 11, count 2 2006.285.13:50:23.36#ibcon#about to read 6, iclass 11, count 2 2006.285.13:50:23.36#ibcon#read 6, iclass 11, count 2 2006.285.13:50:23.36#ibcon#end of sib2, iclass 11, count 2 2006.285.13:50:23.36#ibcon#*after write, iclass 11, count 2 2006.285.13:50:23.36#ibcon#*before return 0, iclass 11, count 2 2006.285.13:50:23.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:50:23.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:50:23.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.13:50:23.36#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:23.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:50:23.47#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:50:23.47#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:50:23.47#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:50:23.47#ibcon#first serial, iclass 11, count 0 2006.285.13:50:23.47#ibcon#enter sib2, iclass 11, count 0 2006.285.13:50:23.47#ibcon#flushed, iclass 11, count 0 2006.285.13:50:23.47#ibcon#about to write, iclass 11, count 0 2006.285.13:50:23.47#ibcon#wrote, iclass 11, count 0 2006.285.13:50:23.47#ibcon#about to read 3, iclass 11, count 0 2006.285.13:50:23.49#ibcon#read 3, iclass 11, count 0 2006.285.13:50:23.49#ibcon#about to read 4, iclass 11, count 0 2006.285.13:50:23.49#ibcon#read 4, iclass 11, count 0 2006.285.13:50:23.49#ibcon#about to read 5, iclass 11, count 0 2006.285.13:50:23.49#ibcon#read 5, iclass 11, count 0 2006.285.13:50:23.49#ibcon#about to read 6, iclass 11, count 0 2006.285.13:50:23.49#ibcon#read 6, iclass 11, count 0 2006.285.13:50:23.49#ibcon#end of sib2, iclass 11, count 0 2006.285.13:50:23.49#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:50:23.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:50:23.49#ibcon#[25=USB\r\n] 2006.285.13:50:23.49#ibcon#*before write, iclass 11, count 0 2006.285.13:50:23.49#ibcon#enter sib2, iclass 11, count 0 2006.285.13:50:23.49#ibcon#flushed, iclass 11, count 0 2006.285.13:50:23.49#ibcon#about to write, iclass 11, count 0 2006.285.13:50:23.49#ibcon#wrote, iclass 11, count 0 2006.285.13:50:23.49#ibcon#about to read 3, iclass 11, count 0 2006.285.13:50:23.52#ibcon#read 3, iclass 11, count 0 2006.285.13:50:23.52#ibcon#about to read 4, iclass 11, count 0 2006.285.13:50:23.52#ibcon#read 4, iclass 11, count 0 2006.285.13:50:23.52#ibcon#about to read 5, iclass 11, count 0 2006.285.13:50:23.52#ibcon#read 5, iclass 11, count 0 2006.285.13:50:23.52#ibcon#about to read 6, iclass 11, count 0 2006.285.13:50:23.52#ibcon#read 6, iclass 11, count 0 2006.285.13:50:23.52#ibcon#end of sib2, iclass 11, count 0 2006.285.13:50:23.52#ibcon#*after write, iclass 11, count 0 2006.285.13:50:23.52#ibcon#*before return 0, iclass 11, count 0 2006.285.13:50:23.52#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:50:23.52#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:50:23.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:50:23.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:50:23.52$vck44/vblo=1,629.99 2006.285.13:50:23.52#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.13:50:23.52#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.13:50:23.52#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:23.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:50:23.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:50:23.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:50:23.52#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:50:23.52#ibcon#first serial, iclass 13, count 0 2006.285.13:50:23.52#ibcon#enter sib2, iclass 13, count 0 2006.285.13:50:23.52#ibcon#flushed, iclass 13, count 0 2006.285.13:50:23.52#ibcon#about to write, iclass 13, count 0 2006.285.13:50:23.52#ibcon#wrote, iclass 13, count 0 2006.285.13:50:23.52#ibcon#about to read 3, iclass 13, count 0 2006.285.13:50:23.54#ibcon#read 3, iclass 13, count 0 2006.285.13:50:23.54#ibcon#about to read 4, iclass 13, count 0 2006.285.13:50:23.54#ibcon#read 4, iclass 13, count 0 2006.285.13:50:23.54#ibcon#about to read 5, iclass 13, count 0 2006.285.13:50:23.54#ibcon#read 5, iclass 13, count 0 2006.285.13:50:23.54#ibcon#about to read 6, iclass 13, count 0 2006.285.13:50:23.54#ibcon#read 6, iclass 13, count 0 2006.285.13:50:23.54#ibcon#end of sib2, iclass 13, count 0 2006.285.13:50:23.54#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:50:23.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:50:23.54#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:50:23.54#ibcon#*before write, iclass 13, count 0 2006.285.13:50:23.54#ibcon#enter sib2, iclass 13, count 0 2006.285.13:50:23.54#ibcon#flushed, iclass 13, count 0 2006.285.13:50:23.54#ibcon#about to write, iclass 13, count 0 2006.285.13:50:23.54#ibcon#wrote, iclass 13, count 0 2006.285.13:50:23.54#ibcon#about to read 3, iclass 13, count 0 2006.285.13:50:23.58#ibcon#read 3, iclass 13, count 0 2006.285.13:50:23.58#ibcon#about to read 4, iclass 13, count 0 2006.285.13:50:23.58#ibcon#read 4, iclass 13, count 0 2006.285.13:50:23.58#ibcon#about to read 5, iclass 13, count 0 2006.285.13:50:23.58#ibcon#read 5, iclass 13, count 0 2006.285.13:50:23.58#ibcon#about to read 6, iclass 13, count 0 2006.285.13:50:23.58#ibcon#read 6, iclass 13, count 0 2006.285.13:50:23.58#ibcon#end of sib2, iclass 13, count 0 2006.285.13:50:23.58#ibcon#*after write, iclass 13, count 0 2006.285.13:50:23.58#ibcon#*before return 0, iclass 13, count 0 2006.285.13:50:23.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:50:23.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:50:23.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:50:23.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:50:23.58$vck44/vb=1,4 2006.285.13:50:23.58#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.13:50:23.58#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.13:50:23.58#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:23.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:50:23.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:50:23.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:50:23.58#ibcon#enter wrdev, iclass 15, count 2 2006.285.13:50:23.58#ibcon#first serial, iclass 15, count 2 2006.285.13:50:23.58#ibcon#enter sib2, iclass 15, count 2 2006.285.13:50:23.58#ibcon#flushed, iclass 15, count 2 2006.285.13:50:23.58#ibcon#about to write, iclass 15, count 2 2006.285.13:50:23.58#ibcon#wrote, iclass 15, count 2 2006.285.13:50:23.58#ibcon#about to read 3, iclass 15, count 2 2006.285.13:50:23.60#ibcon#read 3, iclass 15, count 2 2006.285.13:50:23.60#ibcon#about to read 4, iclass 15, count 2 2006.285.13:50:23.60#ibcon#read 4, iclass 15, count 2 2006.285.13:50:23.60#ibcon#about to read 5, iclass 15, count 2 2006.285.13:50:23.60#ibcon#read 5, iclass 15, count 2 2006.285.13:50:23.60#ibcon#about to read 6, iclass 15, count 2 2006.285.13:50:23.60#ibcon#read 6, iclass 15, count 2 2006.285.13:50:23.60#ibcon#end of sib2, iclass 15, count 2 2006.285.13:50:23.60#ibcon#*mode == 0, iclass 15, count 2 2006.285.13:50:23.60#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.13:50:23.60#ibcon#[27=AT01-04\r\n] 2006.285.13:50:23.60#ibcon#*before write, iclass 15, count 2 2006.285.13:50:23.60#ibcon#enter sib2, iclass 15, count 2 2006.285.13:50:23.60#ibcon#flushed, iclass 15, count 2 2006.285.13:50:23.60#ibcon#about to write, iclass 15, count 2 2006.285.13:50:23.60#ibcon#wrote, iclass 15, count 2 2006.285.13:50:23.60#ibcon#about to read 3, iclass 15, count 2 2006.285.13:50:23.63#ibcon#read 3, iclass 15, count 2 2006.285.13:50:23.63#ibcon#about to read 4, iclass 15, count 2 2006.285.13:50:23.63#ibcon#read 4, iclass 15, count 2 2006.285.13:50:23.63#ibcon#about to read 5, iclass 15, count 2 2006.285.13:50:23.63#ibcon#read 5, iclass 15, count 2 2006.285.13:50:23.63#ibcon#about to read 6, iclass 15, count 2 2006.285.13:50:23.63#ibcon#read 6, iclass 15, count 2 2006.285.13:50:23.63#ibcon#end of sib2, iclass 15, count 2 2006.285.13:50:23.63#ibcon#*after write, iclass 15, count 2 2006.285.13:50:23.63#ibcon#*before return 0, iclass 15, count 2 2006.285.13:50:23.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:50:23.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.13:50:23.63#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.13:50:23.63#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:23.63#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:50:23.75#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:50:23.75#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:50:23.75#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:50:23.75#ibcon#first serial, iclass 15, count 0 2006.285.13:50:23.75#ibcon#enter sib2, iclass 15, count 0 2006.285.13:50:23.75#ibcon#flushed, iclass 15, count 0 2006.285.13:50:23.75#ibcon#about to write, iclass 15, count 0 2006.285.13:50:23.75#ibcon#wrote, iclass 15, count 0 2006.285.13:50:23.75#ibcon#about to read 3, iclass 15, count 0 2006.285.13:50:23.77#ibcon#read 3, iclass 15, count 0 2006.285.13:50:23.77#ibcon#about to read 4, iclass 15, count 0 2006.285.13:50:23.77#ibcon#read 4, iclass 15, count 0 2006.285.13:50:23.77#ibcon#about to read 5, iclass 15, count 0 2006.285.13:50:23.77#ibcon#read 5, iclass 15, count 0 2006.285.13:50:23.77#ibcon#about to read 6, iclass 15, count 0 2006.285.13:50:23.77#ibcon#read 6, iclass 15, count 0 2006.285.13:50:23.77#ibcon#end of sib2, iclass 15, count 0 2006.285.13:50:23.77#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:50:23.77#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:50:23.77#ibcon#[27=USB\r\n] 2006.285.13:50:23.77#ibcon#*before write, iclass 15, count 0 2006.285.13:50:23.77#ibcon#enter sib2, iclass 15, count 0 2006.285.13:50:23.77#ibcon#flushed, iclass 15, count 0 2006.285.13:50:23.77#ibcon#about to write, iclass 15, count 0 2006.285.13:50:23.77#ibcon#wrote, iclass 15, count 0 2006.285.13:50:23.77#ibcon#about to read 3, iclass 15, count 0 2006.285.13:50:23.80#ibcon#read 3, iclass 15, count 0 2006.285.13:50:23.80#ibcon#about to read 4, iclass 15, count 0 2006.285.13:50:23.80#ibcon#read 4, iclass 15, count 0 2006.285.13:50:23.80#ibcon#about to read 5, iclass 15, count 0 2006.285.13:50:23.80#ibcon#read 5, iclass 15, count 0 2006.285.13:50:23.80#ibcon#about to read 6, iclass 15, count 0 2006.285.13:50:23.80#ibcon#read 6, iclass 15, count 0 2006.285.13:50:23.80#ibcon#end of sib2, iclass 15, count 0 2006.285.13:50:23.80#ibcon#*after write, iclass 15, count 0 2006.285.13:50:23.80#ibcon#*before return 0, iclass 15, count 0 2006.285.13:50:23.80#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:50:23.80#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.13:50:23.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:50:23.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:50:23.80$vck44/vblo=2,634.99 2006.285.13:50:23.80#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.13:50:23.80#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.13:50:23.80#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:23.80#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:50:23.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:50:23.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:50:23.80#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:50:23.80#ibcon#first serial, iclass 17, count 0 2006.285.13:50:23.80#ibcon#enter sib2, iclass 17, count 0 2006.285.13:50:23.80#ibcon#flushed, iclass 17, count 0 2006.285.13:50:23.80#ibcon#about to write, iclass 17, count 0 2006.285.13:50:23.80#ibcon#wrote, iclass 17, count 0 2006.285.13:50:23.80#ibcon#about to read 3, iclass 17, count 0 2006.285.13:50:23.82#ibcon#read 3, iclass 17, count 0 2006.285.13:50:23.82#ibcon#about to read 4, iclass 17, count 0 2006.285.13:50:23.82#ibcon#read 4, iclass 17, count 0 2006.285.13:50:23.82#ibcon#about to read 5, iclass 17, count 0 2006.285.13:50:23.82#ibcon#read 5, iclass 17, count 0 2006.285.13:50:23.82#ibcon#about to read 6, iclass 17, count 0 2006.285.13:50:23.82#ibcon#read 6, iclass 17, count 0 2006.285.13:50:23.82#ibcon#end of sib2, iclass 17, count 0 2006.285.13:50:23.82#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:50:23.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:50:23.82#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:50:23.82#ibcon#*before write, iclass 17, count 0 2006.285.13:50:23.82#ibcon#enter sib2, iclass 17, count 0 2006.285.13:50:23.82#ibcon#flushed, iclass 17, count 0 2006.285.13:50:23.82#ibcon#about to write, iclass 17, count 0 2006.285.13:50:23.82#ibcon#wrote, iclass 17, count 0 2006.285.13:50:23.82#ibcon#about to read 3, iclass 17, count 0 2006.285.13:50:23.86#ibcon#read 3, iclass 17, count 0 2006.285.13:50:23.86#ibcon#about to read 4, iclass 17, count 0 2006.285.13:50:23.86#ibcon#read 4, iclass 17, count 0 2006.285.13:50:23.86#ibcon#about to read 5, iclass 17, count 0 2006.285.13:50:23.86#ibcon#read 5, iclass 17, count 0 2006.285.13:50:23.86#ibcon#about to read 6, iclass 17, count 0 2006.285.13:50:23.86#ibcon#read 6, iclass 17, count 0 2006.285.13:50:23.86#ibcon#end of sib2, iclass 17, count 0 2006.285.13:50:23.86#ibcon#*after write, iclass 17, count 0 2006.285.13:50:23.86#ibcon#*before return 0, iclass 17, count 0 2006.285.13:50:23.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:50:23.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.13:50:23.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:50:23.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:50:23.86$vck44/vb=2,5 2006.285.13:50:23.86#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.13:50:23.86#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.13:50:23.86#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:23.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:50:23.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:50:23.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:50:23.92#ibcon#enter wrdev, iclass 19, count 2 2006.285.13:50:23.92#ibcon#first serial, iclass 19, count 2 2006.285.13:50:23.92#ibcon#enter sib2, iclass 19, count 2 2006.285.13:50:23.92#ibcon#flushed, iclass 19, count 2 2006.285.13:50:23.92#ibcon#about to write, iclass 19, count 2 2006.285.13:50:23.92#ibcon#wrote, iclass 19, count 2 2006.285.13:50:23.92#ibcon#about to read 3, iclass 19, count 2 2006.285.13:50:23.94#ibcon#read 3, iclass 19, count 2 2006.285.13:50:23.94#ibcon#about to read 4, iclass 19, count 2 2006.285.13:50:23.94#ibcon#read 4, iclass 19, count 2 2006.285.13:50:23.94#ibcon#about to read 5, iclass 19, count 2 2006.285.13:50:23.94#ibcon#read 5, iclass 19, count 2 2006.285.13:50:23.94#ibcon#about to read 6, iclass 19, count 2 2006.285.13:50:23.94#ibcon#read 6, iclass 19, count 2 2006.285.13:50:23.94#ibcon#end of sib2, iclass 19, count 2 2006.285.13:50:23.94#ibcon#*mode == 0, iclass 19, count 2 2006.285.13:50:23.94#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.13:50:23.94#ibcon#[27=AT02-05\r\n] 2006.285.13:50:23.94#ibcon#*before write, iclass 19, count 2 2006.285.13:50:23.94#ibcon#enter sib2, iclass 19, count 2 2006.285.13:50:23.94#ibcon#flushed, iclass 19, count 2 2006.285.13:50:23.94#ibcon#about to write, iclass 19, count 2 2006.285.13:50:23.94#ibcon#wrote, iclass 19, count 2 2006.285.13:50:23.94#ibcon#about to read 3, iclass 19, count 2 2006.285.13:50:23.97#ibcon#read 3, iclass 19, count 2 2006.285.13:50:23.97#ibcon#about to read 4, iclass 19, count 2 2006.285.13:50:23.97#ibcon#read 4, iclass 19, count 2 2006.285.13:50:23.97#ibcon#about to read 5, iclass 19, count 2 2006.285.13:50:23.97#ibcon#read 5, iclass 19, count 2 2006.285.13:50:23.97#ibcon#about to read 6, iclass 19, count 2 2006.285.13:50:23.97#ibcon#read 6, iclass 19, count 2 2006.285.13:50:23.97#ibcon#end of sib2, iclass 19, count 2 2006.285.13:50:23.97#ibcon#*after write, iclass 19, count 2 2006.285.13:50:23.97#ibcon#*before return 0, iclass 19, count 2 2006.285.13:50:23.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:50:23.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.13:50:23.97#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.13:50:23.97#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:23.97#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:50:24.09#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:50:24.09#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:50:24.09#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:50:24.09#ibcon#first serial, iclass 19, count 0 2006.285.13:50:24.09#ibcon#enter sib2, iclass 19, count 0 2006.285.13:50:24.09#ibcon#flushed, iclass 19, count 0 2006.285.13:50:24.09#ibcon#about to write, iclass 19, count 0 2006.285.13:50:24.09#ibcon#wrote, iclass 19, count 0 2006.285.13:50:24.09#ibcon#about to read 3, iclass 19, count 0 2006.285.13:50:24.11#ibcon#read 3, iclass 19, count 0 2006.285.13:50:24.11#ibcon#about to read 4, iclass 19, count 0 2006.285.13:50:24.11#ibcon#read 4, iclass 19, count 0 2006.285.13:50:24.11#ibcon#about to read 5, iclass 19, count 0 2006.285.13:50:24.11#ibcon#read 5, iclass 19, count 0 2006.285.13:50:24.11#ibcon#about to read 6, iclass 19, count 0 2006.285.13:50:24.11#ibcon#read 6, iclass 19, count 0 2006.285.13:50:24.11#ibcon#end of sib2, iclass 19, count 0 2006.285.13:50:24.11#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:50:24.11#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:50:24.11#ibcon#[27=USB\r\n] 2006.285.13:50:24.11#ibcon#*before write, iclass 19, count 0 2006.285.13:50:24.11#ibcon#enter sib2, iclass 19, count 0 2006.285.13:50:24.11#ibcon#flushed, iclass 19, count 0 2006.285.13:50:24.11#ibcon#about to write, iclass 19, count 0 2006.285.13:50:24.11#ibcon#wrote, iclass 19, count 0 2006.285.13:50:24.11#ibcon#about to read 3, iclass 19, count 0 2006.285.13:50:24.14#ibcon#read 3, iclass 19, count 0 2006.285.13:50:24.14#ibcon#about to read 4, iclass 19, count 0 2006.285.13:50:24.14#ibcon#read 4, iclass 19, count 0 2006.285.13:50:24.14#ibcon#about to read 5, iclass 19, count 0 2006.285.13:50:24.14#ibcon#read 5, iclass 19, count 0 2006.285.13:50:24.14#ibcon#about to read 6, iclass 19, count 0 2006.285.13:50:24.14#ibcon#read 6, iclass 19, count 0 2006.285.13:50:24.14#ibcon#end of sib2, iclass 19, count 0 2006.285.13:50:24.14#ibcon#*after write, iclass 19, count 0 2006.285.13:50:24.14#ibcon#*before return 0, iclass 19, count 0 2006.285.13:50:24.14#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:50:24.14#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.13:50:24.14#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:50:24.14#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:50:24.14$vck44/vblo=3,649.99 2006.285.13:50:24.14#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.13:50:24.14#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.13:50:24.14#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:24.14#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:50:24.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:50:24.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:50:24.14#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:50:24.14#ibcon#first serial, iclass 21, count 0 2006.285.13:50:24.14#ibcon#enter sib2, iclass 21, count 0 2006.285.13:50:24.14#ibcon#flushed, iclass 21, count 0 2006.285.13:50:24.14#ibcon#about to write, iclass 21, count 0 2006.285.13:50:24.14#ibcon#wrote, iclass 21, count 0 2006.285.13:50:24.14#ibcon#about to read 3, iclass 21, count 0 2006.285.13:50:24.16#ibcon#read 3, iclass 21, count 0 2006.285.13:50:24.18#ibcon#about to read 4, iclass 21, count 0 2006.285.13:50:24.18#ibcon#read 4, iclass 21, count 0 2006.285.13:50:24.18#ibcon#about to read 5, iclass 21, count 0 2006.285.13:50:24.18#ibcon#read 5, iclass 21, count 0 2006.285.13:50:24.18#ibcon#about to read 6, iclass 21, count 0 2006.285.13:50:24.18#ibcon#read 6, iclass 21, count 0 2006.285.13:50:24.18#ibcon#end of sib2, iclass 21, count 0 2006.285.13:50:24.18#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:50:24.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:50:24.18#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:50:24.18#ibcon#*before write, iclass 21, count 0 2006.285.13:50:24.18#ibcon#enter sib2, iclass 21, count 0 2006.285.13:50:24.18#ibcon#flushed, iclass 21, count 0 2006.285.13:50:24.18#ibcon#about to write, iclass 21, count 0 2006.285.13:50:24.18#ibcon#wrote, iclass 21, count 0 2006.285.13:50:24.18#ibcon#about to read 3, iclass 21, count 0 2006.285.13:50:24.22#ibcon#read 3, iclass 21, count 0 2006.285.13:50:24.22#ibcon#about to read 4, iclass 21, count 0 2006.285.13:50:24.22#ibcon#read 4, iclass 21, count 0 2006.285.13:50:24.22#ibcon#about to read 5, iclass 21, count 0 2006.285.13:50:24.22#ibcon#read 5, iclass 21, count 0 2006.285.13:50:24.22#ibcon#about to read 6, iclass 21, count 0 2006.285.13:50:24.22#ibcon#read 6, iclass 21, count 0 2006.285.13:50:24.22#ibcon#end of sib2, iclass 21, count 0 2006.285.13:50:24.22#ibcon#*after write, iclass 21, count 0 2006.285.13:50:24.22#ibcon#*before return 0, iclass 21, count 0 2006.285.13:50:24.22#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:50:24.22#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.13:50:24.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:50:24.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:50:24.22$vck44/vb=3,4 2006.285.13:50:24.22#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.13:50:24.22#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.13:50:24.22#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:24.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:50:24.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:50:24.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:50:24.26#ibcon#enter wrdev, iclass 23, count 2 2006.285.13:50:24.26#ibcon#first serial, iclass 23, count 2 2006.285.13:50:24.26#ibcon#enter sib2, iclass 23, count 2 2006.285.13:50:24.26#ibcon#flushed, iclass 23, count 2 2006.285.13:50:24.26#ibcon#about to write, iclass 23, count 2 2006.285.13:50:24.26#ibcon#wrote, iclass 23, count 2 2006.285.13:50:24.26#ibcon#about to read 3, iclass 23, count 2 2006.285.13:50:24.28#ibcon#read 3, iclass 23, count 2 2006.285.13:50:24.28#ibcon#about to read 4, iclass 23, count 2 2006.285.13:50:24.28#ibcon#read 4, iclass 23, count 2 2006.285.13:50:24.28#ibcon#about to read 5, iclass 23, count 2 2006.285.13:50:24.28#ibcon#read 5, iclass 23, count 2 2006.285.13:50:24.28#ibcon#about to read 6, iclass 23, count 2 2006.285.13:50:24.28#ibcon#read 6, iclass 23, count 2 2006.285.13:50:24.28#ibcon#end of sib2, iclass 23, count 2 2006.285.13:50:24.28#ibcon#*mode == 0, iclass 23, count 2 2006.285.13:50:24.28#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.13:50:24.28#ibcon#[27=AT03-04\r\n] 2006.285.13:50:24.28#ibcon#*before write, iclass 23, count 2 2006.285.13:50:24.28#ibcon#enter sib2, iclass 23, count 2 2006.285.13:50:24.28#ibcon#flushed, iclass 23, count 2 2006.285.13:50:24.28#ibcon#about to write, iclass 23, count 2 2006.285.13:50:24.28#ibcon#wrote, iclass 23, count 2 2006.285.13:50:24.28#ibcon#about to read 3, iclass 23, count 2 2006.285.13:50:24.31#ibcon#read 3, iclass 23, count 2 2006.285.13:50:24.31#ibcon#about to read 4, iclass 23, count 2 2006.285.13:50:24.31#ibcon#read 4, iclass 23, count 2 2006.285.13:50:24.31#ibcon#about to read 5, iclass 23, count 2 2006.285.13:50:24.31#ibcon#read 5, iclass 23, count 2 2006.285.13:50:24.31#ibcon#about to read 6, iclass 23, count 2 2006.285.13:50:24.31#ibcon#read 6, iclass 23, count 2 2006.285.13:50:24.31#ibcon#end of sib2, iclass 23, count 2 2006.285.13:50:24.31#ibcon#*after write, iclass 23, count 2 2006.285.13:50:24.31#ibcon#*before return 0, iclass 23, count 2 2006.285.13:50:24.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:50:24.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.13:50:24.31#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.13:50:24.31#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:24.31#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:50:24.32#abcon#<5=/04 1.3 2.4 19.05 971015.3\r\n> 2006.285.13:50:24.34#abcon#{5=INTERFACE CLEAR} 2006.285.13:50:24.40#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:50:24.43#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:50:24.43#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:50:24.43#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:50:24.43#ibcon#first serial, iclass 23, count 0 2006.285.13:50:24.43#ibcon#enter sib2, iclass 23, count 0 2006.285.13:50:24.43#ibcon#flushed, iclass 23, count 0 2006.285.13:50:24.43#ibcon#about to write, iclass 23, count 0 2006.285.13:50:24.43#ibcon#wrote, iclass 23, count 0 2006.285.13:50:24.43#ibcon#about to read 3, iclass 23, count 0 2006.285.13:50:24.45#ibcon#read 3, iclass 23, count 0 2006.285.13:50:24.45#ibcon#about to read 4, iclass 23, count 0 2006.285.13:50:24.45#ibcon#read 4, iclass 23, count 0 2006.285.13:50:24.45#ibcon#about to read 5, iclass 23, count 0 2006.285.13:50:24.45#ibcon#read 5, iclass 23, count 0 2006.285.13:50:24.45#ibcon#about to read 6, iclass 23, count 0 2006.285.13:50:24.45#ibcon#read 6, iclass 23, count 0 2006.285.13:50:24.45#ibcon#end of sib2, iclass 23, count 0 2006.285.13:50:24.45#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:50:24.45#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:50:24.45#ibcon#[27=USB\r\n] 2006.285.13:50:24.45#ibcon#*before write, iclass 23, count 0 2006.285.13:50:24.45#ibcon#enter sib2, iclass 23, count 0 2006.285.13:50:24.45#ibcon#flushed, iclass 23, count 0 2006.285.13:50:24.45#ibcon#about to write, iclass 23, count 0 2006.285.13:50:24.45#ibcon#wrote, iclass 23, count 0 2006.285.13:50:24.45#ibcon#about to read 3, iclass 23, count 0 2006.285.13:50:24.48#ibcon#read 3, iclass 23, count 0 2006.285.13:50:24.48#ibcon#about to read 4, iclass 23, count 0 2006.285.13:50:24.48#ibcon#read 4, iclass 23, count 0 2006.285.13:50:24.48#ibcon#about to read 5, iclass 23, count 0 2006.285.13:50:24.48#ibcon#read 5, iclass 23, count 0 2006.285.13:50:24.48#ibcon#about to read 6, iclass 23, count 0 2006.285.13:50:24.48#ibcon#read 6, iclass 23, count 0 2006.285.13:50:24.48#ibcon#end of sib2, iclass 23, count 0 2006.285.13:50:24.48#ibcon#*after write, iclass 23, count 0 2006.285.13:50:24.48#ibcon#*before return 0, iclass 23, count 0 2006.285.13:50:24.48#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:50:24.48#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.13:50:24.48#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:50:24.48#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:50:24.48$vck44/vblo=4,679.99 2006.285.13:50:24.48#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.13:50:24.48#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.13:50:24.48#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:24.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:50:24.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:50:24.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:50:24.48#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:50:24.48#ibcon#first serial, iclass 29, count 0 2006.285.13:50:24.48#ibcon#enter sib2, iclass 29, count 0 2006.285.13:50:24.48#ibcon#flushed, iclass 29, count 0 2006.285.13:50:24.48#ibcon#about to write, iclass 29, count 0 2006.285.13:50:24.48#ibcon#wrote, iclass 29, count 0 2006.285.13:50:24.48#ibcon#about to read 3, iclass 29, count 0 2006.285.13:50:24.50#ibcon#read 3, iclass 29, count 0 2006.285.13:50:24.50#ibcon#about to read 4, iclass 29, count 0 2006.285.13:50:24.50#ibcon#read 4, iclass 29, count 0 2006.285.13:50:24.50#ibcon#about to read 5, iclass 29, count 0 2006.285.13:50:24.50#ibcon#read 5, iclass 29, count 0 2006.285.13:50:24.50#ibcon#about to read 6, iclass 29, count 0 2006.285.13:50:24.50#ibcon#read 6, iclass 29, count 0 2006.285.13:50:24.50#ibcon#end of sib2, iclass 29, count 0 2006.285.13:50:24.50#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:50:24.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:50:24.50#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:50:24.50#ibcon#*before write, iclass 29, count 0 2006.285.13:50:24.50#ibcon#enter sib2, iclass 29, count 0 2006.285.13:50:24.50#ibcon#flushed, iclass 29, count 0 2006.285.13:50:24.50#ibcon#about to write, iclass 29, count 0 2006.285.13:50:24.50#ibcon#wrote, iclass 29, count 0 2006.285.13:50:24.50#ibcon#about to read 3, iclass 29, count 0 2006.285.13:50:24.54#ibcon#read 3, iclass 29, count 0 2006.285.13:50:24.54#ibcon#about to read 4, iclass 29, count 0 2006.285.13:50:24.54#ibcon#read 4, iclass 29, count 0 2006.285.13:50:24.54#ibcon#about to read 5, iclass 29, count 0 2006.285.13:50:24.54#ibcon#read 5, iclass 29, count 0 2006.285.13:50:24.54#ibcon#about to read 6, iclass 29, count 0 2006.285.13:50:24.54#ibcon#read 6, iclass 29, count 0 2006.285.13:50:24.54#ibcon#end of sib2, iclass 29, count 0 2006.285.13:50:24.54#ibcon#*after write, iclass 29, count 0 2006.285.13:50:24.54#ibcon#*before return 0, iclass 29, count 0 2006.285.13:50:24.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:50:24.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.13:50:24.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:50:24.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:50:24.54$vck44/vb=4,5 2006.285.13:50:24.54#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.13:50:24.54#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.13:50:24.54#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:24.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:50:24.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:50:24.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:50:24.60#ibcon#enter wrdev, iclass 31, count 2 2006.285.13:50:24.60#ibcon#first serial, iclass 31, count 2 2006.285.13:50:24.60#ibcon#enter sib2, iclass 31, count 2 2006.285.13:50:24.60#ibcon#flushed, iclass 31, count 2 2006.285.13:50:24.60#ibcon#about to write, iclass 31, count 2 2006.285.13:50:24.60#ibcon#wrote, iclass 31, count 2 2006.285.13:50:24.60#ibcon#about to read 3, iclass 31, count 2 2006.285.13:50:24.62#ibcon#read 3, iclass 31, count 2 2006.285.13:50:24.62#ibcon#about to read 4, iclass 31, count 2 2006.285.13:50:24.62#ibcon#read 4, iclass 31, count 2 2006.285.13:50:24.62#ibcon#about to read 5, iclass 31, count 2 2006.285.13:50:24.62#ibcon#read 5, iclass 31, count 2 2006.285.13:50:24.62#ibcon#about to read 6, iclass 31, count 2 2006.285.13:50:24.62#ibcon#read 6, iclass 31, count 2 2006.285.13:50:24.62#ibcon#end of sib2, iclass 31, count 2 2006.285.13:50:24.62#ibcon#*mode == 0, iclass 31, count 2 2006.285.13:50:24.62#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.13:50:24.62#ibcon#[27=AT04-05\r\n] 2006.285.13:50:24.62#ibcon#*before write, iclass 31, count 2 2006.285.13:50:24.62#ibcon#enter sib2, iclass 31, count 2 2006.285.13:50:24.62#ibcon#flushed, iclass 31, count 2 2006.285.13:50:24.62#ibcon#about to write, iclass 31, count 2 2006.285.13:50:24.62#ibcon#wrote, iclass 31, count 2 2006.285.13:50:24.62#ibcon#about to read 3, iclass 31, count 2 2006.285.13:50:24.65#ibcon#read 3, iclass 31, count 2 2006.285.13:50:24.65#ibcon#about to read 4, iclass 31, count 2 2006.285.13:50:24.65#ibcon#read 4, iclass 31, count 2 2006.285.13:50:24.65#ibcon#about to read 5, iclass 31, count 2 2006.285.13:50:24.65#ibcon#read 5, iclass 31, count 2 2006.285.13:50:24.65#ibcon#about to read 6, iclass 31, count 2 2006.285.13:50:24.65#ibcon#read 6, iclass 31, count 2 2006.285.13:50:24.65#ibcon#end of sib2, iclass 31, count 2 2006.285.13:50:24.65#ibcon#*after write, iclass 31, count 2 2006.285.13:50:24.65#ibcon#*before return 0, iclass 31, count 2 2006.285.13:50:24.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:50:24.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.13:50:24.65#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.13:50:24.65#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:24.65#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:50:24.77#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:50:24.77#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:50:24.77#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:50:24.77#ibcon#first serial, iclass 31, count 0 2006.285.13:50:24.77#ibcon#enter sib2, iclass 31, count 0 2006.285.13:50:24.77#ibcon#flushed, iclass 31, count 0 2006.285.13:50:24.77#ibcon#about to write, iclass 31, count 0 2006.285.13:50:24.77#ibcon#wrote, iclass 31, count 0 2006.285.13:50:24.77#ibcon#about to read 3, iclass 31, count 0 2006.285.13:50:24.79#ibcon#read 3, iclass 31, count 0 2006.285.13:50:24.79#ibcon#about to read 4, iclass 31, count 0 2006.285.13:50:24.79#ibcon#read 4, iclass 31, count 0 2006.285.13:50:24.79#ibcon#about to read 5, iclass 31, count 0 2006.285.13:50:24.79#ibcon#read 5, iclass 31, count 0 2006.285.13:50:24.79#ibcon#about to read 6, iclass 31, count 0 2006.285.13:50:24.79#ibcon#read 6, iclass 31, count 0 2006.285.13:50:24.79#ibcon#end of sib2, iclass 31, count 0 2006.285.13:50:24.79#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:50:24.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:50:24.79#ibcon#[27=USB\r\n] 2006.285.13:50:24.79#ibcon#*before write, iclass 31, count 0 2006.285.13:50:24.79#ibcon#enter sib2, iclass 31, count 0 2006.285.13:50:24.79#ibcon#flushed, iclass 31, count 0 2006.285.13:50:24.79#ibcon#about to write, iclass 31, count 0 2006.285.13:50:24.79#ibcon#wrote, iclass 31, count 0 2006.285.13:50:24.79#ibcon#about to read 3, iclass 31, count 0 2006.285.13:50:24.82#ibcon#read 3, iclass 31, count 0 2006.285.13:50:24.82#ibcon#about to read 4, iclass 31, count 0 2006.285.13:50:24.82#ibcon#read 4, iclass 31, count 0 2006.285.13:50:24.82#ibcon#about to read 5, iclass 31, count 0 2006.285.13:50:24.82#ibcon#read 5, iclass 31, count 0 2006.285.13:50:24.82#ibcon#about to read 6, iclass 31, count 0 2006.285.13:50:24.82#ibcon#read 6, iclass 31, count 0 2006.285.13:50:24.82#ibcon#end of sib2, iclass 31, count 0 2006.285.13:50:24.82#ibcon#*after write, iclass 31, count 0 2006.285.13:50:24.82#ibcon#*before return 0, iclass 31, count 0 2006.285.13:50:24.82#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:50:24.82#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.13:50:24.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:50:24.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:50:24.82$vck44/vblo=5,709.99 2006.285.13:50:24.82#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.13:50:24.82#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.13:50:24.82#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:24.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:50:24.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:50:24.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:50:24.82#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:50:24.82#ibcon#first serial, iclass 33, count 0 2006.285.13:50:24.82#ibcon#enter sib2, iclass 33, count 0 2006.285.13:50:24.82#ibcon#flushed, iclass 33, count 0 2006.285.13:50:24.82#ibcon#about to write, iclass 33, count 0 2006.285.13:50:24.82#ibcon#wrote, iclass 33, count 0 2006.285.13:50:24.82#ibcon#about to read 3, iclass 33, count 0 2006.285.13:50:24.84#ibcon#read 3, iclass 33, count 0 2006.285.13:50:24.84#ibcon#about to read 4, iclass 33, count 0 2006.285.13:50:24.84#ibcon#read 4, iclass 33, count 0 2006.285.13:50:24.84#ibcon#about to read 5, iclass 33, count 0 2006.285.13:50:24.84#ibcon#read 5, iclass 33, count 0 2006.285.13:50:24.84#ibcon#about to read 6, iclass 33, count 0 2006.285.13:50:24.84#ibcon#read 6, iclass 33, count 0 2006.285.13:50:24.84#ibcon#end of sib2, iclass 33, count 0 2006.285.13:50:24.84#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:50:24.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:50:24.84#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:50:24.84#ibcon#*before write, iclass 33, count 0 2006.285.13:50:24.84#ibcon#enter sib2, iclass 33, count 0 2006.285.13:50:24.84#ibcon#flushed, iclass 33, count 0 2006.285.13:50:24.84#ibcon#about to write, iclass 33, count 0 2006.285.13:50:24.84#ibcon#wrote, iclass 33, count 0 2006.285.13:50:24.84#ibcon#about to read 3, iclass 33, count 0 2006.285.13:50:24.88#ibcon#read 3, iclass 33, count 0 2006.285.13:50:24.88#ibcon#about to read 4, iclass 33, count 0 2006.285.13:50:24.88#ibcon#read 4, iclass 33, count 0 2006.285.13:50:24.88#ibcon#about to read 5, iclass 33, count 0 2006.285.13:50:24.88#ibcon#read 5, iclass 33, count 0 2006.285.13:50:24.88#ibcon#about to read 6, iclass 33, count 0 2006.285.13:50:24.88#ibcon#read 6, iclass 33, count 0 2006.285.13:50:24.88#ibcon#end of sib2, iclass 33, count 0 2006.285.13:50:24.88#ibcon#*after write, iclass 33, count 0 2006.285.13:50:24.88#ibcon#*before return 0, iclass 33, count 0 2006.285.13:50:24.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:50:24.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.13:50:24.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:50:24.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:50:24.88$vck44/vb=5,4 2006.285.13:50:24.88#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.13:50:24.88#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.13:50:24.88#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:24.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:50:24.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:50:24.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:50:24.94#ibcon#enter wrdev, iclass 35, count 2 2006.285.13:50:24.94#ibcon#first serial, iclass 35, count 2 2006.285.13:50:24.94#ibcon#enter sib2, iclass 35, count 2 2006.285.13:50:24.94#ibcon#flushed, iclass 35, count 2 2006.285.13:50:24.94#ibcon#about to write, iclass 35, count 2 2006.285.13:50:24.94#ibcon#wrote, iclass 35, count 2 2006.285.13:50:24.94#ibcon#about to read 3, iclass 35, count 2 2006.285.13:50:24.96#ibcon#read 3, iclass 35, count 2 2006.285.13:50:24.96#ibcon#about to read 4, iclass 35, count 2 2006.285.13:50:24.96#ibcon#read 4, iclass 35, count 2 2006.285.13:50:24.96#ibcon#about to read 5, iclass 35, count 2 2006.285.13:50:24.96#ibcon#read 5, iclass 35, count 2 2006.285.13:50:24.96#ibcon#about to read 6, iclass 35, count 2 2006.285.13:50:24.96#ibcon#read 6, iclass 35, count 2 2006.285.13:50:24.96#ibcon#end of sib2, iclass 35, count 2 2006.285.13:50:24.96#ibcon#*mode == 0, iclass 35, count 2 2006.285.13:50:24.96#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.13:50:24.96#ibcon#[27=AT05-04\r\n] 2006.285.13:50:24.96#ibcon#*before write, iclass 35, count 2 2006.285.13:50:24.96#ibcon#enter sib2, iclass 35, count 2 2006.285.13:50:24.96#ibcon#flushed, iclass 35, count 2 2006.285.13:50:24.96#ibcon#about to write, iclass 35, count 2 2006.285.13:50:24.96#ibcon#wrote, iclass 35, count 2 2006.285.13:50:24.96#ibcon#about to read 3, iclass 35, count 2 2006.285.13:50:24.99#ibcon#read 3, iclass 35, count 2 2006.285.13:50:24.99#ibcon#about to read 4, iclass 35, count 2 2006.285.13:50:24.99#ibcon#read 4, iclass 35, count 2 2006.285.13:50:24.99#ibcon#about to read 5, iclass 35, count 2 2006.285.13:50:24.99#ibcon#read 5, iclass 35, count 2 2006.285.13:50:24.99#ibcon#about to read 6, iclass 35, count 2 2006.285.13:50:24.99#ibcon#read 6, iclass 35, count 2 2006.285.13:50:24.99#ibcon#end of sib2, iclass 35, count 2 2006.285.13:50:24.99#ibcon#*after write, iclass 35, count 2 2006.285.13:50:24.99#ibcon#*before return 0, iclass 35, count 2 2006.285.13:50:24.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:50:24.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:50:24.99#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.13:50:24.99#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:24.99#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:50:25.11#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:50:25.11#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:50:25.11#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:50:25.11#ibcon#first serial, iclass 35, count 0 2006.285.13:50:25.11#ibcon#enter sib2, iclass 35, count 0 2006.285.13:50:25.11#ibcon#flushed, iclass 35, count 0 2006.285.13:50:25.11#ibcon#about to write, iclass 35, count 0 2006.285.13:50:25.11#ibcon#wrote, iclass 35, count 0 2006.285.13:50:25.11#ibcon#about to read 3, iclass 35, count 0 2006.285.13:50:25.13#ibcon#read 3, iclass 35, count 0 2006.285.13:50:25.13#ibcon#about to read 4, iclass 35, count 0 2006.285.13:50:25.13#ibcon#read 4, iclass 35, count 0 2006.285.13:50:25.13#ibcon#about to read 5, iclass 35, count 0 2006.285.13:50:25.13#ibcon#read 5, iclass 35, count 0 2006.285.13:50:25.13#ibcon#about to read 6, iclass 35, count 0 2006.285.13:50:25.13#ibcon#read 6, iclass 35, count 0 2006.285.13:50:25.13#ibcon#end of sib2, iclass 35, count 0 2006.285.13:50:25.13#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:50:25.13#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:50:25.13#ibcon#[27=USB\r\n] 2006.285.13:50:25.13#ibcon#*before write, iclass 35, count 0 2006.285.13:50:25.13#ibcon#enter sib2, iclass 35, count 0 2006.285.13:50:25.13#ibcon#flushed, iclass 35, count 0 2006.285.13:50:25.13#ibcon#about to write, iclass 35, count 0 2006.285.13:50:25.13#ibcon#wrote, iclass 35, count 0 2006.285.13:50:25.13#ibcon#about to read 3, iclass 35, count 0 2006.285.13:50:25.16#ibcon#read 3, iclass 35, count 0 2006.285.13:50:25.16#ibcon#about to read 4, iclass 35, count 0 2006.285.13:50:25.16#ibcon#read 4, iclass 35, count 0 2006.285.13:50:25.16#ibcon#about to read 5, iclass 35, count 0 2006.285.13:50:25.16#ibcon#read 5, iclass 35, count 0 2006.285.13:50:25.16#ibcon#about to read 6, iclass 35, count 0 2006.285.13:50:25.16#ibcon#read 6, iclass 35, count 0 2006.285.13:50:25.16#ibcon#end of sib2, iclass 35, count 0 2006.285.13:50:25.16#ibcon#*after write, iclass 35, count 0 2006.285.13:50:25.16#ibcon#*before return 0, iclass 35, count 0 2006.285.13:50:25.16#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:50:25.16#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:50:25.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:50:25.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:50:25.16$vck44/vblo=6,719.99 2006.285.13:50:25.16#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.13:50:25.16#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.13:50:25.16#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:25.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:50:25.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:50:25.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:50:25.16#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:50:25.16#ibcon#first serial, iclass 37, count 0 2006.285.13:50:25.16#ibcon#enter sib2, iclass 37, count 0 2006.285.13:50:25.16#ibcon#flushed, iclass 37, count 0 2006.285.13:50:25.16#ibcon#about to write, iclass 37, count 0 2006.285.13:50:25.16#ibcon#wrote, iclass 37, count 0 2006.285.13:50:25.16#ibcon#about to read 3, iclass 37, count 0 2006.285.13:50:25.48#ibcon#read 3, iclass 37, count 0 2006.285.13:50:25.48#ibcon#about to read 4, iclass 37, count 0 2006.285.13:50:25.48#ibcon#read 4, iclass 37, count 0 2006.285.13:50:25.48#ibcon#about to read 5, iclass 37, count 0 2006.285.13:50:25.48#ibcon#read 5, iclass 37, count 0 2006.285.13:50:25.48#ibcon#about to read 6, iclass 37, count 0 2006.285.13:50:25.48#ibcon#read 6, iclass 37, count 0 2006.285.13:50:25.48#ibcon#end of sib2, iclass 37, count 0 2006.285.13:50:25.48#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:50:25.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:50:25.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:50:25.48#ibcon#*before write, iclass 37, count 0 2006.285.13:50:25.48#ibcon#enter sib2, iclass 37, count 0 2006.285.13:50:25.48#ibcon#flushed, iclass 37, count 0 2006.285.13:50:25.48#ibcon#about to write, iclass 37, count 0 2006.285.13:50:25.48#ibcon#wrote, iclass 37, count 0 2006.285.13:50:25.48#ibcon#about to read 3, iclass 37, count 0 2006.285.13:50:25.52#ibcon#read 3, iclass 37, count 0 2006.285.13:50:25.52#ibcon#about to read 4, iclass 37, count 0 2006.285.13:50:25.52#ibcon#read 4, iclass 37, count 0 2006.285.13:50:25.52#ibcon#about to read 5, iclass 37, count 0 2006.285.13:50:25.52#ibcon#read 5, iclass 37, count 0 2006.285.13:50:25.52#ibcon#about to read 6, iclass 37, count 0 2006.285.13:50:25.52#ibcon#read 6, iclass 37, count 0 2006.285.13:50:25.52#ibcon#end of sib2, iclass 37, count 0 2006.285.13:50:25.52#ibcon#*after write, iclass 37, count 0 2006.285.13:50:25.52#ibcon#*before return 0, iclass 37, count 0 2006.285.13:50:25.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:50:25.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.13:50:25.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:50:25.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:50:25.52$vck44/vb=6,3 2006.285.13:50:25.52#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.13:50:25.52#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.13:50:25.52#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:25.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:50:25.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:50:25.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:50:25.52#ibcon#enter wrdev, iclass 39, count 2 2006.285.13:50:25.52#ibcon#first serial, iclass 39, count 2 2006.285.13:50:25.52#ibcon#enter sib2, iclass 39, count 2 2006.285.13:50:25.52#ibcon#flushed, iclass 39, count 2 2006.285.13:50:25.52#ibcon#about to write, iclass 39, count 2 2006.285.13:50:25.52#ibcon#wrote, iclass 39, count 2 2006.285.13:50:25.52#ibcon#about to read 3, iclass 39, count 2 2006.285.13:50:25.54#ibcon#read 3, iclass 39, count 2 2006.285.13:50:25.54#ibcon#about to read 4, iclass 39, count 2 2006.285.13:50:25.54#ibcon#read 4, iclass 39, count 2 2006.285.13:50:25.54#ibcon#about to read 5, iclass 39, count 2 2006.285.13:50:25.54#ibcon#read 5, iclass 39, count 2 2006.285.13:50:25.54#ibcon#about to read 6, iclass 39, count 2 2006.285.13:50:25.54#ibcon#read 6, iclass 39, count 2 2006.285.13:50:25.54#ibcon#end of sib2, iclass 39, count 2 2006.285.13:50:25.54#ibcon#*mode == 0, iclass 39, count 2 2006.285.13:50:25.54#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.13:50:25.54#ibcon#[27=AT06-03\r\n] 2006.285.13:50:25.54#ibcon#*before write, iclass 39, count 2 2006.285.13:50:25.54#ibcon#enter sib2, iclass 39, count 2 2006.285.13:50:25.54#ibcon#flushed, iclass 39, count 2 2006.285.13:50:25.54#ibcon#about to write, iclass 39, count 2 2006.285.13:50:25.54#ibcon#wrote, iclass 39, count 2 2006.285.13:50:25.54#ibcon#about to read 3, iclass 39, count 2 2006.285.13:50:25.57#ibcon#read 3, iclass 39, count 2 2006.285.13:50:25.57#ibcon#about to read 4, iclass 39, count 2 2006.285.13:50:25.57#ibcon#read 4, iclass 39, count 2 2006.285.13:50:25.57#ibcon#about to read 5, iclass 39, count 2 2006.285.13:50:25.57#ibcon#read 5, iclass 39, count 2 2006.285.13:50:25.57#ibcon#about to read 6, iclass 39, count 2 2006.285.13:50:25.57#ibcon#read 6, iclass 39, count 2 2006.285.13:50:25.57#ibcon#end of sib2, iclass 39, count 2 2006.285.13:50:25.57#ibcon#*after write, iclass 39, count 2 2006.285.13:50:25.57#ibcon#*before return 0, iclass 39, count 2 2006.285.13:50:25.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:50:25.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.13:50:25.57#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.13:50:25.57#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:25.57#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:50:25.69#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:50:25.69#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:50:25.69#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:50:25.69#ibcon#first serial, iclass 39, count 0 2006.285.13:50:25.69#ibcon#enter sib2, iclass 39, count 0 2006.285.13:50:25.69#ibcon#flushed, iclass 39, count 0 2006.285.13:50:25.69#ibcon#about to write, iclass 39, count 0 2006.285.13:50:25.69#ibcon#wrote, iclass 39, count 0 2006.285.13:50:25.69#ibcon#about to read 3, iclass 39, count 0 2006.285.13:50:25.71#ibcon#read 3, iclass 39, count 0 2006.285.13:50:25.71#ibcon#about to read 4, iclass 39, count 0 2006.285.13:50:25.71#ibcon#read 4, iclass 39, count 0 2006.285.13:50:25.71#ibcon#about to read 5, iclass 39, count 0 2006.285.13:50:25.71#ibcon#read 5, iclass 39, count 0 2006.285.13:50:25.71#ibcon#about to read 6, iclass 39, count 0 2006.285.13:50:25.71#ibcon#read 6, iclass 39, count 0 2006.285.13:50:25.71#ibcon#end of sib2, iclass 39, count 0 2006.285.13:50:25.71#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:50:25.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:50:25.71#ibcon#[27=USB\r\n] 2006.285.13:50:25.71#ibcon#*before write, iclass 39, count 0 2006.285.13:50:25.71#ibcon#enter sib2, iclass 39, count 0 2006.285.13:50:25.71#ibcon#flushed, iclass 39, count 0 2006.285.13:50:25.71#ibcon#about to write, iclass 39, count 0 2006.285.13:50:25.71#ibcon#wrote, iclass 39, count 0 2006.285.13:50:25.71#ibcon#about to read 3, iclass 39, count 0 2006.285.13:50:25.74#ibcon#read 3, iclass 39, count 0 2006.285.13:50:25.74#ibcon#about to read 4, iclass 39, count 0 2006.285.13:50:25.74#ibcon#read 4, iclass 39, count 0 2006.285.13:50:25.74#ibcon#about to read 5, iclass 39, count 0 2006.285.13:50:25.74#ibcon#read 5, iclass 39, count 0 2006.285.13:50:25.74#ibcon#about to read 6, iclass 39, count 0 2006.285.13:50:25.74#ibcon#read 6, iclass 39, count 0 2006.285.13:50:25.74#ibcon#end of sib2, iclass 39, count 0 2006.285.13:50:25.74#ibcon#*after write, iclass 39, count 0 2006.285.13:50:25.74#ibcon#*before return 0, iclass 39, count 0 2006.285.13:50:25.74#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:50:25.74#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.13:50:25.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:50:25.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:50:25.74$vck44/vblo=7,734.99 2006.285.13:50:25.74#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.13:50:25.74#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.13:50:25.74#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:25.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:50:25.74#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:50:25.74#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:50:25.74#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:50:25.74#ibcon#first serial, iclass 3, count 0 2006.285.13:50:25.74#ibcon#enter sib2, iclass 3, count 0 2006.285.13:50:25.74#ibcon#flushed, iclass 3, count 0 2006.285.13:50:25.74#ibcon#about to write, iclass 3, count 0 2006.285.13:50:25.74#ibcon#wrote, iclass 3, count 0 2006.285.13:50:25.74#ibcon#about to read 3, iclass 3, count 0 2006.285.13:50:25.76#ibcon#read 3, iclass 3, count 0 2006.285.13:50:25.76#ibcon#about to read 4, iclass 3, count 0 2006.285.13:50:25.76#ibcon#read 4, iclass 3, count 0 2006.285.13:50:25.76#ibcon#about to read 5, iclass 3, count 0 2006.285.13:50:25.76#ibcon#read 5, iclass 3, count 0 2006.285.13:50:25.76#ibcon#about to read 6, iclass 3, count 0 2006.285.13:50:25.76#ibcon#read 6, iclass 3, count 0 2006.285.13:50:25.76#ibcon#end of sib2, iclass 3, count 0 2006.285.13:50:25.76#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:50:25.76#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:50:25.76#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:50:25.76#ibcon#*before write, iclass 3, count 0 2006.285.13:50:25.76#ibcon#enter sib2, iclass 3, count 0 2006.285.13:50:25.76#ibcon#flushed, iclass 3, count 0 2006.285.13:50:25.76#ibcon#about to write, iclass 3, count 0 2006.285.13:50:25.76#ibcon#wrote, iclass 3, count 0 2006.285.13:50:25.76#ibcon#about to read 3, iclass 3, count 0 2006.285.13:50:25.80#ibcon#read 3, iclass 3, count 0 2006.285.13:50:25.80#ibcon#about to read 4, iclass 3, count 0 2006.285.13:50:25.80#ibcon#read 4, iclass 3, count 0 2006.285.13:50:25.80#ibcon#about to read 5, iclass 3, count 0 2006.285.13:50:25.80#ibcon#read 5, iclass 3, count 0 2006.285.13:50:25.80#ibcon#about to read 6, iclass 3, count 0 2006.285.13:50:25.80#ibcon#read 6, iclass 3, count 0 2006.285.13:50:25.80#ibcon#end of sib2, iclass 3, count 0 2006.285.13:50:25.80#ibcon#*after write, iclass 3, count 0 2006.285.13:50:25.80#ibcon#*before return 0, iclass 3, count 0 2006.285.13:50:25.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:50:25.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.13:50:25.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:50:25.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:50:25.80$vck44/vb=7,4 2006.285.13:50:25.80#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.13:50:25.80#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.13:50:25.80#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:25.80#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:50:25.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:50:25.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:50:25.86#ibcon#enter wrdev, iclass 5, count 2 2006.285.13:50:25.86#ibcon#first serial, iclass 5, count 2 2006.285.13:50:25.86#ibcon#enter sib2, iclass 5, count 2 2006.285.13:50:25.86#ibcon#flushed, iclass 5, count 2 2006.285.13:50:25.86#ibcon#about to write, iclass 5, count 2 2006.285.13:50:25.86#ibcon#wrote, iclass 5, count 2 2006.285.13:50:25.86#ibcon#about to read 3, iclass 5, count 2 2006.285.13:50:25.88#ibcon#read 3, iclass 5, count 2 2006.285.13:50:25.88#ibcon#about to read 4, iclass 5, count 2 2006.285.13:50:25.88#ibcon#read 4, iclass 5, count 2 2006.285.13:50:25.88#ibcon#about to read 5, iclass 5, count 2 2006.285.13:50:25.88#ibcon#read 5, iclass 5, count 2 2006.285.13:50:25.88#ibcon#about to read 6, iclass 5, count 2 2006.285.13:50:25.88#ibcon#read 6, iclass 5, count 2 2006.285.13:50:25.88#ibcon#end of sib2, iclass 5, count 2 2006.285.13:50:25.88#ibcon#*mode == 0, iclass 5, count 2 2006.285.13:50:25.88#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.13:50:25.88#ibcon#[27=AT07-04\r\n] 2006.285.13:50:25.88#ibcon#*before write, iclass 5, count 2 2006.285.13:50:25.88#ibcon#enter sib2, iclass 5, count 2 2006.285.13:50:25.88#ibcon#flushed, iclass 5, count 2 2006.285.13:50:25.88#ibcon#about to write, iclass 5, count 2 2006.285.13:50:25.88#ibcon#wrote, iclass 5, count 2 2006.285.13:50:25.88#ibcon#about to read 3, iclass 5, count 2 2006.285.13:50:25.91#ibcon#read 3, iclass 5, count 2 2006.285.13:50:25.91#ibcon#about to read 4, iclass 5, count 2 2006.285.13:50:25.91#ibcon#read 4, iclass 5, count 2 2006.285.13:50:25.91#ibcon#about to read 5, iclass 5, count 2 2006.285.13:50:25.91#ibcon#read 5, iclass 5, count 2 2006.285.13:50:25.91#ibcon#about to read 6, iclass 5, count 2 2006.285.13:50:25.91#ibcon#read 6, iclass 5, count 2 2006.285.13:50:25.91#ibcon#end of sib2, iclass 5, count 2 2006.285.13:50:25.91#ibcon#*after write, iclass 5, count 2 2006.285.13:50:25.91#ibcon#*before return 0, iclass 5, count 2 2006.285.13:50:25.91#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:50:25.91#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.13:50:25.91#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.13:50:25.91#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:25.91#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:50:26.03#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:50:26.03#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:50:26.03#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:50:26.03#ibcon#first serial, iclass 5, count 0 2006.285.13:50:26.03#ibcon#enter sib2, iclass 5, count 0 2006.285.13:50:26.03#ibcon#flushed, iclass 5, count 0 2006.285.13:50:26.03#ibcon#about to write, iclass 5, count 0 2006.285.13:50:26.03#ibcon#wrote, iclass 5, count 0 2006.285.13:50:26.03#ibcon#about to read 3, iclass 5, count 0 2006.285.13:50:26.05#ibcon#read 3, iclass 5, count 0 2006.285.13:50:26.05#ibcon#about to read 4, iclass 5, count 0 2006.285.13:50:26.05#ibcon#read 4, iclass 5, count 0 2006.285.13:50:26.05#ibcon#about to read 5, iclass 5, count 0 2006.285.13:50:26.05#ibcon#read 5, iclass 5, count 0 2006.285.13:50:26.05#ibcon#about to read 6, iclass 5, count 0 2006.285.13:50:26.05#ibcon#read 6, iclass 5, count 0 2006.285.13:50:26.05#ibcon#end of sib2, iclass 5, count 0 2006.285.13:50:26.05#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:50:26.05#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:50:26.05#ibcon#[27=USB\r\n] 2006.285.13:50:26.05#ibcon#*before write, iclass 5, count 0 2006.285.13:50:26.05#ibcon#enter sib2, iclass 5, count 0 2006.285.13:50:26.05#ibcon#flushed, iclass 5, count 0 2006.285.13:50:26.05#ibcon#about to write, iclass 5, count 0 2006.285.13:50:26.05#ibcon#wrote, iclass 5, count 0 2006.285.13:50:26.05#ibcon#about to read 3, iclass 5, count 0 2006.285.13:50:26.08#ibcon#read 3, iclass 5, count 0 2006.285.13:50:26.08#ibcon#about to read 4, iclass 5, count 0 2006.285.13:50:26.08#ibcon#read 4, iclass 5, count 0 2006.285.13:50:26.08#ibcon#about to read 5, iclass 5, count 0 2006.285.13:50:26.08#ibcon#read 5, iclass 5, count 0 2006.285.13:50:26.08#ibcon#about to read 6, iclass 5, count 0 2006.285.13:50:26.08#ibcon#read 6, iclass 5, count 0 2006.285.13:50:26.08#ibcon#end of sib2, iclass 5, count 0 2006.285.13:50:26.08#ibcon#*after write, iclass 5, count 0 2006.285.13:50:26.08#ibcon#*before return 0, iclass 5, count 0 2006.285.13:50:26.08#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:50:26.08#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.13:50:26.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:50:26.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:50:26.08$vck44/vblo=8,744.99 2006.285.13:50:26.08#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.13:50:26.08#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.13:50:26.08#ibcon#ireg 17 cls_cnt 0 2006.285.13:50:26.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:50:26.08#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:50:26.08#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:50:26.08#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:50:26.08#ibcon#first serial, iclass 7, count 0 2006.285.13:50:26.08#ibcon#enter sib2, iclass 7, count 0 2006.285.13:50:26.08#ibcon#flushed, iclass 7, count 0 2006.285.13:50:26.08#ibcon#about to write, iclass 7, count 0 2006.285.13:50:26.08#ibcon#wrote, iclass 7, count 0 2006.285.13:50:26.08#ibcon#about to read 3, iclass 7, count 0 2006.285.13:50:26.10#ibcon#read 3, iclass 7, count 0 2006.285.13:50:26.10#ibcon#about to read 4, iclass 7, count 0 2006.285.13:50:26.10#ibcon#read 4, iclass 7, count 0 2006.285.13:50:26.10#ibcon#about to read 5, iclass 7, count 0 2006.285.13:50:26.10#ibcon#read 5, iclass 7, count 0 2006.285.13:50:26.10#ibcon#about to read 6, iclass 7, count 0 2006.285.13:50:26.10#ibcon#read 6, iclass 7, count 0 2006.285.13:50:26.10#ibcon#end of sib2, iclass 7, count 0 2006.285.13:50:26.10#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:50:26.10#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:50:26.10#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:50:26.10#ibcon#*before write, iclass 7, count 0 2006.285.13:50:26.10#ibcon#enter sib2, iclass 7, count 0 2006.285.13:50:26.10#ibcon#flushed, iclass 7, count 0 2006.285.13:50:26.10#ibcon#about to write, iclass 7, count 0 2006.285.13:50:26.10#ibcon#wrote, iclass 7, count 0 2006.285.13:50:26.10#ibcon#about to read 3, iclass 7, count 0 2006.285.13:50:26.14#ibcon#read 3, iclass 7, count 0 2006.285.13:50:26.14#ibcon#about to read 4, iclass 7, count 0 2006.285.13:50:26.14#ibcon#read 4, iclass 7, count 0 2006.285.13:50:26.14#ibcon#about to read 5, iclass 7, count 0 2006.285.13:50:26.14#ibcon#read 5, iclass 7, count 0 2006.285.13:50:26.14#ibcon#about to read 6, iclass 7, count 0 2006.285.13:50:26.14#ibcon#read 6, iclass 7, count 0 2006.285.13:50:26.14#ibcon#end of sib2, iclass 7, count 0 2006.285.13:50:26.14#ibcon#*after write, iclass 7, count 0 2006.285.13:50:26.14#ibcon#*before return 0, iclass 7, count 0 2006.285.13:50:26.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:50:26.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:50:26.14#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:50:26.14#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:50:26.14$vck44/vb=8,4 2006.285.13:50:26.14#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.13:50:26.14#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.13:50:26.14#ibcon#ireg 11 cls_cnt 2 2006.285.13:50:26.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:50:26.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:50:26.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:50:26.20#ibcon#enter wrdev, iclass 11, count 2 2006.285.13:50:26.20#ibcon#first serial, iclass 11, count 2 2006.285.13:50:26.20#ibcon#enter sib2, iclass 11, count 2 2006.285.13:50:26.20#ibcon#flushed, iclass 11, count 2 2006.285.13:50:26.20#ibcon#about to write, iclass 11, count 2 2006.285.13:50:26.20#ibcon#wrote, iclass 11, count 2 2006.285.13:50:26.20#ibcon#about to read 3, iclass 11, count 2 2006.285.13:50:26.22#ibcon#read 3, iclass 11, count 2 2006.285.13:50:26.26#ibcon#about to read 4, iclass 11, count 2 2006.285.13:50:26.26#ibcon#read 4, iclass 11, count 2 2006.285.13:50:26.26#ibcon#about to read 5, iclass 11, count 2 2006.285.13:50:26.26#ibcon#read 5, iclass 11, count 2 2006.285.13:50:26.26#ibcon#about to read 6, iclass 11, count 2 2006.285.13:50:26.26#ibcon#read 6, iclass 11, count 2 2006.285.13:50:26.26#ibcon#end of sib2, iclass 11, count 2 2006.285.13:50:26.26#ibcon#*mode == 0, iclass 11, count 2 2006.285.13:50:26.26#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.13:50:26.26#ibcon#[27=AT08-04\r\n] 2006.285.13:50:26.26#ibcon#*before write, iclass 11, count 2 2006.285.13:50:26.26#ibcon#enter sib2, iclass 11, count 2 2006.285.13:50:26.26#ibcon#flushed, iclass 11, count 2 2006.285.13:50:26.26#ibcon#about to write, iclass 11, count 2 2006.285.13:50:26.26#ibcon#wrote, iclass 11, count 2 2006.285.13:50:26.26#ibcon#about to read 3, iclass 11, count 2 2006.285.13:50:26.29#ibcon#read 3, iclass 11, count 2 2006.285.13:50:26.29#ibcon#about to read 4, iclass 11, count 2 2006.285.13:50:26.29#ibcon#read 4, iclass 11, count 2 2006.285.13:50:26.29#ibcon#about to read 5, iclass 11, count 2 2006.285.13:50:26.29#ibcon#read 5, iclass 11, count 2 2006.285.13:50:26.29#ibcon#about to read 6, iclass 11, count 2 2006.285.13:50:26.29#ibcon#read 6, iclass 11, count 2 2006.285.13:50:26.29#ibcon#end of sib2, iclass 11, count 2 2006.285.13:50:26.29#ibcon#*after write, iclass 11, count 2 2006.285.13:50:26.29#ibcon#*before return 0, iclass 11, count 2 2006.285.13:50:26.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:50:26.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.13:50:26.29#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.13:50:26.29#ibcon#ireg 7 cls_cnt 0 2006.285.13:50:26.29#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:50:26.41#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:50:26.41#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:50:26.41#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:50:26.41#ibcon#first serial, iclass 11, count 0 2006.285.13:50:26.41#ibcon#enter sib2, iclass 11, count 0 2006.285.13:50:26.41#ibcon#flushed, iclass 11, count 0 2006.285.13:50:26.41#ibcon#about to write, iclass 11, count 0 2006.285.13:50:26.41#ibcon#wrote, iclass 11, count 0 2006.285.13:50:26.41#ibcon#about to read 3, iclass 11, count 0 2006.285.13:50:26.43#ibcon#read 3, iclass 11, count 0 2006.285.13:50:26.43#ibcon#about to read 4, iclass 11, count 0 2006.285.13:50:26.43#ibcon#read 4, iclass 11, count 0 2006.285.13:50:26.43#ibcon#about to read 5, iclass 11, count 0 2006.285.13:50:26.43#ibcon#read 5, iclass 11, count 0 2006.285.13:50:26.43#ibcon#about to read 6, iclass 11, count 0 2006.285.13:50:26.43#ibcon#read 6, iclass 11, count 0 2006.285.13:50:26.43#ibcon#end of sib2, iclass 11, count 0 2006.285.13:50:26.43#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:50:26.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:50:26.43#ibcon#[27=USB\r\n] 2006.285.13:50:26.43#ibcon#*before write, iclass 11, count 0 2006.285.13:50:26.43#ibcon#enter sib2, iclass 11, count 0 2006.285.13:50:26.43#ibcon#flushed, iclass 11, count 0 2006.285.13:50:26.43#ibcon#about to write, iclass 11, count 0 2006.285.13:50:26.43#ibcon#wrote, iclass 11, count 0 2006.285.13:50:26.43#ibcon#about to read 3, iclass 11, count 0 2006.285.13:50:26.46#ibcon#read 3, iclass 11, count 0 2006.285.13:50:26.46#ibcon#about to read 4, iclass 11, count 0 2006.285.13:50:26.46#ibcon#read 4, iclass 11, count 0 2006.285.13:50:26.46#ibcon#about to read 5, iclass 11, count 0 2006.285.13:50:26.46#ibcon#read 5, iclass 11, count 0 2006.285.13:50:26.46#ibcon#about to read 6, iclass 11, count 0 2006.285.13:50:26.46#ibcon#read 6, iclass 11, count 0 2006.285.13:50:26.46#ibcon#end of sib2, iclass 11, count 0 2006.285.13:50:26.46#ibcon#*after write, iclass 11, count 0 2006.285.13:50:26.46#ibcon#*before return 0, iclass 11, count 0 2006.285.13:50:26.46#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:50:26.46#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.13:50:26.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:50:26.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:50:26.46$vck44/vabw=wide 2006.285.13:50:26.46#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.13:50:26.46#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.13:50:26.46#ibcon#ireg 8 cls_cnt 0 2006.285.13:50:26.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:50:26.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:50:26.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:50:26.46#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:50:26.46#ibcon#first serial, iclass 13, count 0 2006.285.13:50:26.46#ibcon#enter sib2, iclass 13, count 0 2006.285.13:50:26.46#ibcon#flushed, iclass 13, count 0 2006.285.13:50:26.46#ibcon#about to write, iclass 13, count 0 2006.285.13:50:26.46#ibcon#wrote, iclass 13, count 0 2006.285.13:50:26.46#ibcon#about to read 3, iclass 13, count 0 2006.285.13:50:26.48#ibcon#read 3, iclass 13, count 0 2006.285.13:50:26.48#ibcon#about to read 4, iclass 13, count 0 2006.285.13:50:26.48#ibcon#read 4, iclass 13, count 0 2006.285.13:50:26.48#ibcon#about to read 5, iclass 13, count 0 2006.285.13:50:26.48#ibcon#read 5, iclass 13, count 0 2006.285.13:50:26.48#ibcon#about to read 6, iclass 13, count 0 2006.285.13:50:26.48#ibcon#read 6, iclass 13, count 0 2006.285.13:50:26.48#ibcon#end of sib2, iclass 13, count 0 2006.285.13:50:26.48#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:50:26.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:50:26.48#ibcon#[25=BW32\r\n] 2006.285.13:50:26.48#ibcon#*before write, iclass 13, count 0 2006.285.13:50:26.48#ibcon#enter sib2, iclass 13, count 0 2006.285.13:50:26.48#ibcon#flushed, iclass 13, count 0 2006.285.13:50:26.48#ibcon#about to write, iclass 13, count 0 2006.285.13:50:26.48#ibcon#wrote, iclass 13, count 0 2006.285.13:50:26.48#ibcon#about to read 3, iclass 13, count 0 2006.285.13:50:26.51#ibcon#read 3, iclass 13, count 0 2006.285.13:50:26.51#ibcon#about to read 4, iclass 13, count 0 2006.285.13:50:26.51#ibcon#read 4, iclass 13, count 0 2006.285.13:50:26.51#ibcon#about to read 5, iclass 13, count 0 2006.285.13:50:26.51#ibcon#read 5, iclass 13, count 0 2006.285.13:50:26.51#ibcon#about to read 6, iclass 13, count 0 2006.285.13:50:26.51#ibcon#read 6, iclass 13, count 0 2006.285.13:50:26.51#ibcon#end of sib2, iclass 13, count 0 2006.285.13:50:26.51#ibcon#*after write, iclass 13, count 0 2006.285.13:50:26.51#ibcon#*before return 0, iclass 13, count 0 2006.285.13:50:26.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:50:26.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.13:50:26.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:50:26.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:50:26.51$vck44/vbbw=wide 2006.285.13:50:26.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.13:50:26.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.13:50:26.51#ibcon#ireg 8 cls_cnt 0 2006.285.13:50:26.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:50:26.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:50:26.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:50:26.58#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:50:26.58#ibcon#first serial, iclass 15, count 0 2006.285.13:50:26.58#ibcon#enter sib2, iclass 15, count 0 2006.285.13:50:26.58#ibcon#flushed, iclass 15, count 0 2006.285.13:50:26.58#ibcon#about to write, iclass 15, count 0 2006.285.13:50:26.58#ibcon#wrote, iclass 15, count 0 2006.285.13:50:26.58#ibcon#about to read 3, iclass 15, count 0 2006.285.13:50:26.60#ibcon#read 3, iclass 15, count 0 2006.285.13:50:26.60#ibcon#about to read 4, iclass 15, count 0 2006.285.13:50:26.60#ibcon#read 4, iclass 15, count 0 2006.285.13:50:26.60#ibcon#about to read 5, iclass 15, count 0 2006.285.13:50:26.60#ibcon#read 5, iclass 15, count 0 2006.285.13:50:26.60#ibcon#about to read 6, iclass 15, count 0 2006.285.13:50:26.60#ibcon#read 6, iclass 15, count 0 2006.285.13:50:26.60#ibcon#end of sib2, iclass 15, count 0 2006.285.13:50:26.60#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:50:26.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:50:26.60#ibcon#[27=BW32\r\n] 2006.285.13:50:26.60#ibcon#*before write, iclass 15, count 0 2006.285.13:50:26.60#ibcon#enter sib2, iclass 15, count 0 2006.285.13:50:26.60#ibcon#flushed, iclass 15, count 0 2006.285.13:50:26.60#ibcon#about to write, iclass 15, count 0 2006.285.13:50:26.60#ibcon#wrote, iclass 15, count 0 2006.285.13:50:26.60#ibcon#about to read 3, iclass 15, count 0 2006.285.13:50:26.63#ibcon#read 3, iclass 15, count 0 2006.285.13:50:26.63#ibcon#about to read 4, iclass 15, count 0 2006.285.13:50:26.63#ibcon#read 4, iclass 15, count 0 2006.285.13:50:26.63#ibcon#about to read 5, iclass 15, count 0 2006.285.13:50:26.63#ibcon#read 5, iclass 15, count 0 2006.285.13:50:26.63#ibcon#about to read 6, iclass 15, count 0 2006.285.13:50:26.63#ibcon#read 6, iclass 15, count 0 2006.285.13:50:26.63#ibcon#end of sib2, iclass 15, count 0 2006.285.13:50:26.63#ibcon#*after write, iclass 15, count 0 2006.285.13:50:26.63#ibcon#*before return 0, iclass 15, count 0 2006.285.13:50:26.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:50:26.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:50:26.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:50:26.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:50:26.63$setupk4/ifdk4 2006.285.13:50:26.63$ifdk4/lo= 2006.285.13:50:26.63$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:50:26.63$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:50:26.63$ifdk4/patch= 2006.285.13:50:26.63$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:50:26.63$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:50:26.63$setupk4/!*+20s 2006.285.13:50:34.49#abcon#<5=/04 1.4 2.4 19.05 971015.3\r\n> 2006.285.13:50:34.51#abcon#{5=INTERFACE CLEAR} 2006.285.13:50:34.57#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:50:39.14#trakl#Source acquired 2006.285.13:50:39.14#flagr#flagr/antenna,acquired 2006.285.13:50:40.32$setupk4/"tpicd 2006.285.13:50:40.32$setupk4/echo=off 2006.285.13:50:40.32$setupk4/xlog=off 2006.285.13:50:40.32:!2006.285.13:51:20 2006.285.13:51:20.00:preob 2006.285.13:51:20.14/onsource/TRACKING 2006.285.13:51:20.14:!2006.285.13:51:30 2006.285.13:51:30.00:"tape 2006.285.13:51:30.00:"st=record 2006.285.13:51:30.00:data_valid=on 2006.285.13:51:30.00:midob 2006.285.13:51:30.14/onsource/TRACKING 2006.285.13:51:30.14/wx/19.04,1015.3,98 2006.285.13:51:30.20/cable/+6.4975E-03 2006.285.13:51:31.29/va/01,07,usb,yes,33,35 2006.285.13:51:31.29/va/02,06,usb,yes,33,33 2006.285.13:51:31.29/va/03,07,usb,yes,32,34 2006.285.13:51:31.29/va/04,06,usb,yes,34,35 2006.285.13:51:31.29/va/05,03,usb,yes,33,34 2006.285.13:51:31.29/va/06,04,usb,yes,30,30 2006.285.13:51:31.29/va/07,04,usb,yes,31,31 2006.285.13:51:31.29/va/08,03,usb,yes,31,38 2006.285.13:51:31.52/valo/01,524.99,yes,locked 2006.285.13:51:31.52/valo/02,534.99,yes,locked 2006.285.13:51:31.52/valo/03,564.99,yes,locked 2006.285.13:51:31.52/valo/04,624.99,yes,locked 2006.285.13:51:31.52/valo/05,734.99,yes,locked 2006.285.13:51:31.52/valo/06,814.99,yes,locked 2006.285.13:51:31.52/valo/07,864.99,yes,locked 2006.285.13:51:31.52/valo/08,884.99,yes,locked 2006.285.13:51:32.61/vb/01,04,usb,yes,31,29 2006.285.13:51:32.61/vb/02,05,usb,yes,29,29 2006.285.13:51:32.61/vb/03,04,usb,yes,30,33 2006.285.13:51:32.61/vb/04,05,usb,yes,30,29 2006.285.13:51:32.61/vb/05,04,usb,yes,27,29 2006.285.13:51:32.61/vb/06,03,usb,yes,38,34 2006.285.13:51:32.61/vb/07,04,usb,yes,31,31 2006.285.13:51:32.61/vb/08,04,usb,yes,28,32 2006.285.13:51:32.85/vblo/01,629.99,yes,locked 2006.285.13:51:32.85/vblo/02,634.99,yes,locked 2006.285.13:51:32.85/vblo/03,649.99,yes,locked 2006.285.13:51:32.85/vblo/04,679.99,yes,locked 2006.285.13:51:32.85/vblo/05,709.99,yes,locked 2006.285.13:51:32.85/vblo/06,719.99,yes,locked 2006.285.13:51:32.85/vblo/07,734.99,yes,locked 2006.285.13:51:32.85/vblo/08,744.99,yes,locked 2006.285.13:51:33.00/vabw/8 2006.285.13:51:33.15/vbbw/8 2006.285.13:51:33.24/xfe/off,on,12.2 2006.285.13:51:33.61/ifatt/23,28,28,28 2006.285.13:51:34.07/fmout-gps/S +2.59E-07 2006.285.13:51:34.09:!2006.285.13:52:20 2006.285.13:52:20.01:data_valid=off 2006.285.13:52:20.01:"et 2006.285.13:52:20.01:!+3s 2006.285.13:52:23.02:"tape 2006.285.13:52:23.02:postob 2006.285.13:52:23.14/cable/+6.4994E-03 2006.285.13:52:23.14/wx/19.05,1015.3,97 2006.285.13:52:24.08/fmout-gps/S +2.58E-07 2006.285.13:52:24.08:scan_name=285-1355,jd0610,200 2006.285.13:52:24.08:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.285.13:52:25.14#flagr#flagr/antenna,new-source 2006.285.13:52:25.14:checkk5 2006.285.13:52:25.67/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:52:26.07/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:52:26.53/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:52:26.91/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:52:27.45/chk_obsdata//k5ts1/T2851351??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.13:52:27.92/chk_obsdata//k5ts2/T2851351??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.13:52:28.31/chk_obsdata//k5ts3/T2851351??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.13:52:28.79/chk_obsdata//k5ts4/T2851351??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.13:52:30.31/k5log//k5ts1_log_newline 2006.285.13:52:31.04/k5log//k5ts2_log_newline 2006.285.13:52:31.99/k5log//k5ts3_log_newline 2006.285.13:52:33.18/k5log//k5ts4_log_newline 2006.285.13:52:33.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:52:33.21:setupk4=1 2006.285.13:52:33.21$setupk4/echo=on 2006.285.13:52:33.21$setupk4/pcalon 2006.285.13:52:33.21$pcalon/"no phase cal control is implemented here 2006.285.13:52:33.21$setupk4/"tpicd=stop 2006.285.13:52:33.21$setupk4/"rec=synch_on 2006.285.13:52:33.21$setupk4/"rec_mode=128 2006.285.13:52:33.21$setupk4/!* 2006.285.13:52:33.21$setupk4/recpk4 2006.285.13:52:33.21$recpk4/recpatch= 2006.285.13:52:33.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:52:33.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:52:33.21$setupk4/vck44 2006.285.13:52:33.21$vck44/valo=1,524.99 2006.285.13:52:33.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.13:52:33.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.13:52:33.21#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:33.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:52:33.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:52:33.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:52:33.21#ibcon#enter wrdev, iclass 32, count 0 2006.285.13:52:33.21#ibcon#first serial, iclass 32, count 0 2006.285.13:52:33.21#ibcon#enter sib2, iclass 32, count 0 2006.285.13:52:33.21#ibcon#flushed, iclass 32, count 0 2006.285.13:52:33.21#ibcon#about to write, iclass 32, count 0 2006.285.13:52:33.21#ibcon#wrote, iclass 32, count 0 2006.285.13:52:33.21#ibcon#about to read 3, iclass 32, count 0 2006.285.13:52:33.23#ibcon#read 3, iclass 32, count 0 2006.285.13:52:33.23#ibcon#about to read 4, iclass 32, count 0 2006.285.13:52:33.23#ibcon#read 4, iclass 32, count 0 2006.285.13:52:33.23#ibcon#about to read 5, iclass 32, count 0 2006.285.13:52:33.23#ibcon#read 5, iclass 32, count 0 2006.285.13:52:33.23#ibcon#about to read 6, iclass 32, count 0 2006.285.13:52:33.23#ibcon#read 6, iclass 32, count 0 2006.285.13:52:33.23#ibcon#end of sib2, iclass 32, count 0 2006.285.13:52:33.23#ibcon#*mode == 0, iclass 32, count 0 2006.285.13:52:33.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.13:52:33.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:52:33.23#ibcon#*before write, iclass 32, count 0 2006.285.13:52:33.23#ibcon#enter sib2, iclass 32, count 0 2006.285.13:52:33.23#ibcon#flushed, iclass 32, count 0 2006.285.13:52:33.23#ibcon#about to write, iclass 32, count 0 2006.285.13:52:33.23#ibcon#wrote, iclass 32, count 0 2006.285.13:52:33.23#ibcon#about to read 3, iclass 32, count 0 2006.285.13:52:33.28#ibcon#read 3, iclass 32, count 0 2006.285.13:52:33.28#ibcon#about to read 4, iclass 32, count 0 2006.285.13:52:33.28#ibcon#read 4, iclass 32, count 0 2006.285.13:52:33.28#ibcon#about to read 5, iclass 32, count 0 2006.285.13:52:33.28#ibcon#read 5, iclass 32, count 0 2006.285.13:52:33.28#ibcon#about to read 6, iclass 32, count 0 2006.285.13:52:33.28#ibcon#read 6, iclass 32, count 0 2006.285.13:52:33.28#ibcon#end of sib2, iclass 32, count 0 2006.285.13:52:33.28#ibcon#*after write, iclass 32, count 0 2006.285.13:52:33.28#ibcon#*before return 0, iclass 32, count 0 2006.285.13:52:33.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:52:33.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:52:33.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.13:52:33.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.13:52:33.28$vck44/va=1,7 2006.285.13:52:33.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.13:52:33.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.13:52:33.28#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:33.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:52:33.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:52:33.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:52:33.28#ibcon#enter wrdev, iclass 34, count 2 2006.285.13:52:33.28#ibcon#first serial, iclass 34, count 2 2006.285.13:52:33.28#ibcon#enter sib2, iclass 34, count 2 2006.285.13:52:33.28#ibcon#flushed, iclass 34, count 2 2006.285.13:52:33.28#ibcon#about to write, iclass 34, count 2 2006.285.13:52:33.28#ibcon#wrote, iclass 34, count 2 2006.285.13:52:33.28#ibcon#about to read 3, iclass 34, count 2 2006.285.13:52:33.30#ibcon#read 3, iclass 34, count 2 2006.285.13:52:33.30#ibcon#about to read 4, iclass 34, count 2 2006.285.13:52:33.30#ibcon#read 4, iclass 34, count 2 2006.285.13:52:33.30#ibcon#about to read 5, iclass 34, count 2 2006.285.13:52:33.30#ibcon#read 5, iclass 34, count 2 2006.285.13:52:33.30#ibcon#about to read 6, iclass 34, count 2 2006.285.13:52:33.30#ibcon#read 6, iclass 34, count 2 2006.285.13:52:33.30#ibcon#end of sib2, iclass 34, count 2 2006.285.13:52:33.30#ibcon#*mode == 0, iclass 34, count 2 2006.285.13:52:33.30#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.13:52:33.30#ibcon#[25=AT01-07\r\n] 2006.285.13:52:33.30#ibcon#*before write, iclass 34, count 2 2006.285.13:52:33.30#ibcon#enter sib2, iclass 34, count 2 2006.285.13:52:33.30#ibcon#flushed, iclass 34, count 2 2006.285.13:52:33.30#ibcon#about to write, iclass 34, count 2 2006.285.13:52:33.30#ibcon#wrote, iclass 34, count 2 2006.285.13:52:33.30#ibcon#about to read 3, iclass 34, count 2 2006.285.13:52:33.33#ibcon#read 3, iclass 34, count 2 2006.285.13:52:33.33#ibcon#about to read 4, iclass 34, count 2 2006.285.13:52:33.33#ibcon#read 4, iclass 34, count 2 2006.285.13:52:33.33#ibcon#about to read 5, iclass 34, count 2 2006.285.13:52:33.33#ibcon#read 5, iclass 34, count 2 2006.285.13:52:33.33#ibcon#about to read 6, iclass 34, count 2 2006.285.13:52:33.33#ibcon#read 6, iclass 34, count 2 2006.285.13:52:33.33#ibcon#end of sib2, iclass 34, count 2 2006.285.13:52:33.33#ibcon#*after write, iclass 34, count 2 2006.285.13:52:33.33#ibcon#*before return 0, iclass 34, count 2 2006.285.13:52:33.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:52:33.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.13:52:33.33#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.13:52:33.33#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:33.33#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:52:33.45#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:52:33.45#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:52:33.45#ibcon#enter wrdev, iclass 34, count 0 2006.285.13:52:33.45#ibcon#first serial, iclass 34, count 0 2006.285.13:52:33.45#ibcon#enter sib2, iclass 34, count 0 2006.285.13:52:33.45#ibcon#flushed, iclass 34, count 0 2006.285.13:52:33.45#ibcon#about to write, iclass 34, count 0 2006.285.13:52:33.45#ibcon#wrote, iclass 34, count 0 2006.285.13:52:33.45#ibcon#about to read 3, iclass 34, count 0 2006.285.13:52:33.47#ibcon#read 3, iclass 34, count 0 2006.285.13:52:33.47#ibcon#about to read 4, iclass 34, count 0 2006.285.13:52:33.47#ibcon#read 4, iclass 34, count 0 2006.285.13:52:33.47#ibcon#about to read 5, iclass 34, count 0 2006.285.13:52:33.47#ibcon#read 5, iclass 34, count 0 2006.285.13:52:33.47#ibcon#about to read 6, iclass 34, count 0 2006.285.13:52:33.47#ibcon#read 6, iclass 34, count 0 2006.285.13:52:33.47#ibcon#end of sib2, iclass 34, count 0 2006.285.13:52:33.47#ibcon#*mode == 0, iclass 34, count 0 2006.285.13:52:33.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.13:52:33.47#ibcon#[25=USB\r\n] 2006.285.13:52:33.47#ibcon#*before write, iclass 34, count 0 2006.285.13:52:33.47#ibcon#enter sib2, iclass 34, count 0 2006.285.13:52:33.47#ibcon#flushed, iclass 34, count 0 2006.285.13:52:33.47#ibcon#about to write, iclass 34, count 0 2006.285.13:52:33.47#ibcon#wrote, iclass 34, count 0 2006.285.13:52:33.47#ibcon#about to read 3, iclass 34, count 0 2006.285.13:52:33.50#ibcon#read 3, iclass 34, count 0 2006.285.13:52:33.50#ibcon#about to read 4, iclass 34, count 0 2006.285.13:52:33.50#ibcon#read 4, iclass 34, count 0 2006.285.13:52:33.50#ibcon#about to read 5, iclass 34, count 0 2006.285.13:52:33.50#ibcon#read 5, iclass 34, count 0 2006.285.13:52:33.50#ibcon#about to read 6, iclass 34, count 0 2006.285.13:52:33.50#ibcon#read 6, iclass 34, count 0 2006.285.13:52:33.50#ibcon#end of sib2, iclass 34, count 0 2006.285.13:52:33.50#ibcon#*after write, iclass 34, count 0 2006.285.13:52:33.50#ibcon#*before return 0, iclass 34, count 0 2006.285.13:52:33.50#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:52:33.50#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.13:52:33.50#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.13:52:33.50#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.13:52:33.50$vck44/valo=2,534.99 2006.285.13:52:33.50#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.13:52:33.50#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.13:52:33.50#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:33.50#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:52:33.50#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:52:33.50#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:52:33.50#ibcon#enter wrdev, iclass 36, count 0 2006.285.13:52:33.50#ibcon#first serial, iclass 36, count 0 2006.285.13:52:33.50#ibcon#enter sib2, iclass 36, count 0 2006.285.13:52:33.50#ibcon#flushed, iclass 36, count 0 2006.285.13:52:33.50#ibcon#about to write, iclass 36, count 0 2006.285.13:52:33.50#ibcon#wrote, iclass 36, count 0 2006.285.13:52:33.50#ibcon#about to read 3, iclass 36, count 0 2006.285.13:52:33.52#ibcon#read 3, iclass 36, count 0 2006.285.13:52:33.80#ibcon#about to read 4, iclass 36, count 0 2006.285.13:52:33.80#ibcon#read 4, iclass 36, count 0 2006.285.13:52:33.80#ibcon#about to read 5, iclass 36, count 0 2006.285.13:52:33.80#ibcon#read 5, iclass 36, count 0 2006.285.13:52:33.80#ibcon#about to read 6, iclass 36, count 0 2006.285.13:52:33.80#ibcon#read 6, iclass 36, count 0 2006.285.13:52:33.80#ibcon#end of sib2, iclass 36, count 0 2006.285.13:52:33.80#ibcon#*mode == 0, iclass 36, count 0 2006.285.13:52:33.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.13:52:33.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:52:33.80#ibcon#*before write, iclass 36, count 0 2006.285.13:52:33.80#ibcon#enter sib2, iclass 36, count 0 2006.285.13:52:33.80#ibcon#flushed, iclass 36, count 0 2006.285.13:52:33.80#ibcon#about to write, iclass 36, count 0 2006.285.13:52:33.80#ibcon#wrote, iclass 36, count 0 2006.285.13:52:33.80#ibcon#about to read 3, iclass 36, count 0 2006.285.13:52:33.84#ibcon#read 3, iclass 36, count 0 2006.285.13:52:33.84#ibcon#about to read 4, iclass 36, count 0 2006.285.13:52:33.84#ibcon#read 4, iclass 36, count 0 2006.285.13:52:33.84#ibcon#about to read 5, iclass 36, count 0 2006.285.13:52:33.84#ibcon#read 5, iclass 36, count 0 2006.285.13:52:33.84#ibcon#about to read 6, iclass 36, count 0 2006.285.13:52:33.84#ibcon#read 6, iclass 36, count 0 2006.285.13:52:33.84#ibcon#end of sib2, iclass 36, count 0 2006.285.13:52:33.84#ibcon#*after write, iclass 36, count 0 2006.285.13:52:33.84#ibcon#*before return 0, iclass 36, count 0 2006.285.13:52:33.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:52:33.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.13:52:33.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.13:52:33.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.13:52:33.84$vck44/va=2,6 2006.285.13:52:33.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.13:52:33.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.13:52:33.84#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:33.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:52:33.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:52:33.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:52:33.84#ibcon#enter wrdev, iclass 38, count 2 2006.285.13:52:33.84#ibcon#first serial, iclass 38, count 2 2006.285.13:52:33.84#ibcon#enter sib2, iclass 38, count 2 2006.285.13:52:33.84#ibcon#flushed, iclass 38, count 2 2006.285.13:52:33.84#ibcon#about to write, iclass 38, count 2 2006.285.13:52:33.84#ibcon#wrote, iclass 38, count 2 2006.285.13:52:33.84#ibcon#about to read 3, iclass 38, count 2 2006.285.13:52:33.86#ibcon#read 3, iclass 38, count 2 2006.285.13:52:33.86#ibcon#about to read 4, iclass 38, count 2 2006.285.13:52:33.86#ibcon#read 4, iclass 38, count 2 2006.285.13:52:33.86#ibcon#about to read 5, iclass 38, count 2 2006.285.13:52:33.86#ibcon#read 5, iclass 38, count 2 2006.285.13:52:33.86#ibcon#about to read 6, iclass 38, count 2 2006.285.13:52:33.86#ibcon#read 6, iclass 38, count 2 2006.285.13:52:33.86#ibcon#end of sib2, iclass 38, count 2 2006.285.13:52:33.86#ibcon#*mode == 0, iclass 38, count 2 2006.285.13:52:33.86#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.13:52:33.86#ibcon#[25=AT02-06\r\n] 2006.285.13:52:33.86#ibcon#*before write, iclass 38, count 2 2006.285.13:52:33.86#ibcon#enter sib2, iclass 38, count 2 2006.285.13:52:33.86#ibcon#flushed, iclass 38, count 2 2006.285.13:52:33.86#ibcon#about to write, iclass 38, count 2 2006.285.13:52:33.86#ibcon#wrote, iclass 38, count 2 2006.285.13:52:33.86#ibcon#about to read 3, iclass 38, count 2 2006.285.13:52:33.89#ibcon#read 3, iclass 38, count 2 2006.285.13:52:33.89#ibcon#about to read 4, iclass 38, count 2 2006.285.13:52:33.89#ibcon#read 4, iclass 38, count 2 2006.285.13:52:33.89#ibcon#about to read 5, iclass 38, count 2 2006.285.13:52:33.89#ibcon#read 5, iclass 38, count 2 2006.285.13:52:33.89#ibcon#about to read 6, iclass 38, count 2 2006.285.13:52:33.89#ibcon#read 6, iclass 38, count 2 2006.285.13:52:33.89#ibcon#end of sib2, iclass 38, count 2 2006.285.13:52:33.89#ibcon#*after write, iclass 38, count 2 2006.285.13:52:33.89#ibcon#*before return 0, iclass 38, count 2 2006.285.13:52:33.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:52:33.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.13:52:33.89#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.13:52:33.89#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:33.89#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:52:34.01#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:52:34.01#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:52:34.01#ibcon#enter wrdev, iclass 38, count 0 2006.285.13:52:34.01#ibcon#first serial, iclass 38, count 0 2006.285.13:52:34.01#ibcon#enter sib2, iclass 38, count 0 2006.285.13:52:34.01#ibcon#flushed, iclass 38, count 0 2006.285.13:52:34.01#ibcon#about to write, iclass 38, count 0 2006.285.13:52:34.01#ibcon#wrote, iclass 38, count 0 2006.285.13:52:34.01#ibcon#about to read 3, iclass 38, count 0 2006.285.13:52:34.03#ibcon#read 3, iclass 38, count 0 2006.285.13:52:34.03#ibcon#about to read 4, iclass 38, count 0 2006.285.13:52:34.03#ibcon#read 4, iclass 38, count 0 2006.285.13:52:34.03#ibcon#about to read 5, iclass 38, count 0 2006.285.13:52:34.03#ibcon#read 5, iclass 38, count 0 2006.285.13:52:34.03#ibcon#about to read 6, iclass 38, count 0 2006.285.13:52:34.03#ibcon#read 6, iclass 38, count 0 2006.285.13:52:34.03#ibcon#end of sib2, iclass 38, count 0 2006.285.13:52:34.03#ibcon#*mode == 0, iclass 38, count 0 2006.285.13:52:34.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.13:52:34.03#ibcon#[25=USB\r\n] 2006.285.13:52:34.03#ibcon#*before write, iclass 38, count 0 2006.285.13:52:34.03#ibcon#enter sib2, iclass 38, count 0 2006.285.13:52:34.03#ibcon#flushed, iclass 38, count 0 2006.285.13:52:34.03#ibcon#about to write, iclass 38, count 0 2006.285.13:52:34.03#ibcon#wrote, iclass 38, count 0 2006.285.13:52:34.03#ibcon#about to read 3, iclass 38, count 0 2006.285.13:52:34.06#ibcon#read 3, iclass 38, count 0 2006.285.13:52:34.06#ibcon#about to read 4, iclass 38, count 0 2006.285.13:52:34.06#ibcon#read 4, iclass 38, count 0 2006.285.13:52:34.06#ibcon#about to read 5, iclass 38, count 0 2006.285.13:52:34.06#ibcon#read 5, iclass 38, count 0 2006.285.13:52:34.06#ibcon#about to read 6, iclass 38, count 0 2006.285.13:52:34.06#ibcon#read 6, iclass 38, count 0 2006.285.13:52:34.06#ibcon#end of sib2, iclass 38, count 0 2006.285.13:52:34.06#ibcon#*after write, iclass 38, count 0 2006.285.13:52:34.06#ibcon#*before return 0, iclass 38, count 0 2006.285.13:52:34.06#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:52:34.06#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.13:52:34.06#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.13:52:34.06#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.13:52:34.06$vck44/valo=3,564.99 2006.285.13:52:34.06#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.13:52:34.06#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.13:52:34.06#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:34.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:52:34.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:52:34.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:52:34.06#ibcon#enter wrdev, iclass 40, count 0 2006.285.13:52:34.06#ibcon#first serial, iclass 40, count 0 2006.285.13:52:34.06#ibcon#enter sib2, iclass 40, count 0 2006.285.13:52:34.06#ibcon#flushed, iclass 40, count 0 2006.285.13:52:34.06#ibcon#about to write, iclass 40, count 0 2006.285.13:52:34.06#ibcon#wrote, iclass 40, count 0 2006.285.13:52:34.06#ibcon#about to read 3, iclass 40, count 0 2006.285.13:52:34.08#ibcon#read 3, iclass 40, count 0 2006.285.13:52:34.08#ibcon#about to read 4, iclass 40, count 0 2006.285.13:52:34.08#ibcon#read 4, iclass 40, count 0 2006.285.13:52:34.08#ibcon#about to read 5, iclass 40, count 0 2006.285.13:52:34.08#ibcon#read 5, iclass 40, count 0 2006.285.13:52:34.08#ibcon#about to read 6, iclass 40, count 0 2006.285.13:52:34.08#ibcon#read 6, iclass 40, count 0 2006.285.13:52:34.08#ibcon#end of sib2, iclass 40, count 0 2006.285.13:52:34.08#ibcon#*mode == 0, iclass 40, count 0 2006.285.13:52:34.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.13:52:34.08#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:52:34.08#ibcon#*before write, iclass 40, count 0 2006.285.13:52:34.08#ibcon#enter sib2, iclass 40, count 0 2006.285.13:52:34.08#ibcon#flushed, iclass 40, count 0 2006.285.13:52:34.08#ibcon#about to write, iclass 40, count 0 2006.285.13:52:34.08#ibcon#wrote, iclass 40, count 0 2006.285.13:52:34.08#ibcon#about to read 3, iclass 40, count 0 2006.285.13:52:34.12#ibcon#read 3, iclass 40, count 0 2006.285.13:52:34.12#ibcon#about to read 4, iclass 40, count 0 2006.285.13:52:34.12#ibcon#read 4, iclass 40, count 0 2006.285.13:52:34.12#ibcon#about to read 5, iclass 40, count 0 2006.285.13:52:34.12#ibcon#read 5, iclass 40, count 0 2006.285.13:52:34.12#ibcon#about to read 6, iclass 40, count 0 2006.285.13:52:34.12#ibcon#read 6, iclass 40, count 0 2006.285.13:52:34.12#ibcon#end of sib2, iclass 40, count 0 2006.285.13:52:34.12#ibcon#*after write, iclass 40, count 0 2006.285.13:52:34.12#ibcon#*before return 0, iclass 40, count 0 2006.285.13:52:34.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:52:34.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:52:34.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.13:52:34.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.13:52:34.12$vck44/va=3,7 2006.285.13:52:34.12#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.13:52:34.12#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.13:52:34.12#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:34.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:52:34.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:52:34.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:52:34.18#ibcon#enter wrdev, iclass 4, count 2 2006.285.13:52:34.18#ibcon#first serial, iclass 4, count 2 2006.285.13:52:34.18#ibcon#enter sib2, iclass 4, count 2 2006.285.13:52:34.18#ibcon#flushed, iclass 4, count 2 2006.285.13:52:34.18#ibcon#about to write, iclass 4, count 2 2006.285.13:52:34.18#ibcon#wrote, iclass 4, count 2 2006.285.13:52:34.18#ibcon#about to read 3, iclass 4, count 2 2006.285.13:52:34.20#ibcon#read 3, iclass 4, count 2 2006.285.13:52:34.20#ibcon#about to read 4, iclass 4, count 2 2006.285.13:52:34.20#ibcon#read 4, iclass 4, count 2 2006.285.13:52:34.20#ibcon#about to read 5, iclass 4, count 2 2006.285.13:52:34.20#ibcon#read 5, iclass 4, count 2 2006.285.13:52:34.20#ibcon#about to read 6, iclass 4, count 2 2006.285.13:52:34.20#ibcon#read 6, iclass 4, count 2 2006.285.13:52:34.20#ibcon#end of sib2, iclass 4, count 2 2006.285.13:52:34.20#ibcon#*mode == 0, iclass 4, count 2 2006.285.13:52:34.20#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.13:52:34.20#ibcon#[25=AT03-07\r\n] 2006.285.13:52:34.20#ibcon#*before write, iclass 4, count 2 2006.285.13:52:34.20#ibcon#enter sib2, iclass 4, count 2 2006.285.13:52:34.20#ibcon#flushed, iclass 4, count 2 2006.285.13:52:34.20#ibcon#about to write, iclass 4, count 2 2006.285.13:52:34.20#ibcon#wrote, iclass 4, count 2 2006.285.13:52:34.20#ibcon#about to read 3, iclass 4, count 2 2006.285.13:52:34.23#ibcon#read 3, iclass 4, count 2 2006.285.13:52:34.23#ibcon#about to read 4, iclass 4, count 2 2006.285.13:52:34.23#ibcon#read 4, iclass 4, count 2 2006.285.13:52:34.23#ibcon#about to read 5, iclass 4, count 2 2006.285.13:52:34.23#ibcon#read 5, iclass 4, count 2 2006.285.13:52:34.23#ibcon#about to read 6, iclass 4, count 2 2006.285.13:52:34.23#ibcon#read 6, iclass 4, count 2 2006.285.13:52:34.23#ibcon#end of sib2, iclass 4, count 2 2006.285.13:52:34.23#ibcon#*after write, iclass 4, count 2 2006.285.13:52:34.23#ibcon#*before return 0, iclass 4, count 2 2006.285.13:52:34.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:52:34.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:52:34.23#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.13:52:34.23#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:34.23#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:52:34.35#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:52:34.35#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:52:34.35#ibcon#enter wrdev, iclass 4, count 0 2006.285.13:52:34.35#ibcon#first serial, iclass 4, count 0 2006.285.13:52:34.35#ibcon#enter sib2, iclass 4, count 0 2006.285.13:52:34.35#ibcon#flushed, iclass 4, count 0 2006.285.13:52:34.35#ibcon#about to write, iclass 4, count 0 2006.285.13:52:34.35#ibcon#wrote, iclass 4, count 0 2006.285.13:52:34.35#ibcon#about to read 3, iclass 4, count 0 2006.285.13:52:34.37#ibcon#read 3, iclass 4, count 0 2006.285.13:52:34.37#ibcon#about to read 4, iclass 4, count 0 2006.285.13:52:34.37#ibcon#read 4, iclass 4, count 0 2006.285.13:52:34.37#ibcon#about to read 5, iclass 4, count 0 2006.285.13:52:34.37#ibcon#read 5, iclass 4, count 0 2006.285.13:52:34.37#ibcon#about to read 6, iclass 4, count 0 2006.285.13:52:34.37#ibcon#read 6, iclass 4, count 0 2006.285.13:52:34.37#ibcon#end of sib2, iclass 4, count 0 2006.285.13:52:34.37#ibcon#*mode == 0, iclass 4, count 0 2006.285.13:52:34.37#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.13:52:34.37#ibcon#[25=USB\r\n] 2006.285.13:52:34.37#ibcon#*before write, iclass 4, count 0 2006.285.13:52:34.37#ibcon#enter sib2, iclass 4, count 0 2006.285.13:52:34.37#ibcon#flushed, iclass 4, count 0 2006.285.13:52:34.37#ibcon#about to write, iclass 4, count 0 2006.285.13:52:34.37#ibcon#wrote, iclass 4, count 0 2006.285.13:52:34.37#ibcon#about to read 3, iclass 4, count 0 2006.285.13:52:34.40#ibcon#read 3, iclass 4, count 0 2006.285.13:52:34.40#ibcon#about to read 4, iclass 4, count 0 2006.285.13:52:34.40#ibcon#read 4, iclass 4, count 0 2006.285.13:52:34.40#ibcon#about to read 5, iclass 4, count 0 2006.285.13:52:34.40#ibcon#read 5, iclass 4, count 0 2006.285.13:52:34.40#ibcon#about to read 6, iclass 4, count 0 2006.285.13:52:34.40#ibcon#read 6, iclass 4, count 0 2006.285.13:52:34.40#ibcon#end of sib2, iclass 4, count 0 2006.285.13:52:34.40#ibcon#*after write, iclass 4, count 0 2006.285.13:52:34.40#ibcon#*before return 0, iclass 4, count 0 2006.285.13:52:34.40#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:52:34.40#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:52:34.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.13:52:34.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.13:52:34.40$vck44/valo=4,624.99 2006.285.13:52:34.40#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.13:52:34.40#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.13:52:34.40#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:34.40#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:52:34.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:52:34.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:52:34.40#ibcon#enter wrdev, iclass 6, count 0 2006.285.13:52:34.40#ibcon#first serial, iclass 6, count 0 2006.285.13:52:34.40#ibcon#enter sib2, iclass 6, count 0 2006.285.13:52:34.40#ibcon#flushed, iclass 6, count 0 2006.285.13:52:34.40#ibcon#about to write, iclass 6, count 0 2006.285.13:52:34.40#ibcon#wrote, iclass 6, count 0 2006.285.13:52:34.40#ibcon#about to read 3, iclass 6, count 0 2006.285.13:52:34.42#ibcon#read 3, iclass 6, count 0 2006.285.13:52:34.42#ibcon#about to read 4, iclass 6, count 0 2006.285.13:52:34.42#ibcon#read 4, iclass 6, count 0 2006.285.13:52:34.42#ibcon#about to read 5, iclass 6, count 0 2006.285.13:52:34.42#ibcon#read 5, iclass 6, count 0 2006.285.13:52:34.42#ibcon#about to read 6, iclass 6, count 0 2006.285.13:52:34.42#ibcon#read 6, iclass 6, count 0 2006.285.13:52:34.42#ibcon#end of sib2, iclass 6, count 0 2006.285.13:52:34.42#ibcon#*mode == 0, iclass 6, count 0 2006.285.13:52:34.42#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.13:52:34.42#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:52:34.42#ibcon#*before write, iclass 6, count 0 2006.285.13:52:34.42#ibcon#enter sib2, iclass 6, count 0 2006.285.13:52:34.42#ibcon#flushed, iclass 6, count 0 2006.285.13:52:34.42#ibcon#about to write, iclass 6, count 0 2006.285.13:52:34.42#ibcon#wrote, iclass 6, count 0 2006.285.13:52:34.42#ibcon#about to read 3, iclass 6, count 0 2006.285.13:52:34.46#ibcon#read 3, iclass 6, count 0 2006.285.13:52:34.46#ibcon#about to read 4, iclass 6, count 0 2006.285.13:52:34.46#ibcon#read 4, iclass 6, count 0 2006.285.13:52:34.46#ibcon#about to read 5, iclass 6, count 0 2006.285.13:52:34.46#ibcon#read 5, iclass 6, count 0 2006.285.13:52:34.46#ibcon#about to read 6, iclass 6, count 0 2006.285.13:52:34.46#ibcon#read 6, iclass 6, count 0 2006.285.13:52:34.46#ibcon#end of sib2, iclass 6, count 0 2006.285.13:52:34.46#ibcon#*after write, iclass 6, count 0 2006.285.13:52:34.46#ibcon#*before return 0, iclass 6, count 0 2006.285.13:52:34.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:52:34.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:52:34.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.13:52:34.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.13:52:34.46$vck44/va=4,6 2006.285.13:52:34.54#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.13:52:34.54#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.13:52:34.54#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:34.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:52:34.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:52:34.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:52:34.54#ibcon#enter wrdev, iclass 10, count 2 2006.285.13:52:34.54#ibcon#first serial, iclass 10, count 2 2006.285.13:52:34.54#ibcon#enter sib2, iclass 10, count 2 2006.285.13:52:34.54#ibcon#flushed, iclass 10, count 2 2006.285.13:52:34.54#ibcon#about to write, iclass 10, count 2 2006.285.13:52:34.54#ibcon#wrote, iclass 10, count 2 2006.285.13:52:34.54#ibcon#about to read 3, iclass 10, count 2 2006.285.13:52:34.55#ibcon#read 3, iclass 10, count 2 2006.285.13:52:34.55#ibcon#about to read 4, iclass 10, count 2 2006.285.13:52:34.55#ibcon#read 4, iclass 10, count 2 2006.285.13:52:34.55#ibcon#about to read 5, iclass 10, count 2 2006.285.13:52:34.55#ibcon#read 5, iclass 10, count 2 2006.285.13:52:34.55#ibcon#about to read 6, iclass 10, count 2 2006.285.13:52:34.55#ibcon#read 6, iclass 10, count 2 2006.285.13:52:34.55#ibcon#end of sib2, iclass 10, count 2 2006.285.13:52:34.55#ibcon#*mode == 0, iclass 10, count 2 2006.285.13:52:34.55#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.13:52:34.55#ibcon#[25=AT04-06\r\n] 2006.285.13:52:34.55#ibcon#*before write, iclass 10, count 2 2006.285.13:52:34.55#ibcon#enter sib2, iclass 10, count 2 2006.285.13:52:34.55#ibcon#flushed, iclass 10, count 2 2006.285.13:52:34.55#ibcon#about to write, iclass 10, count 2 2006.285.13:52:34.55#ibcon#wrote, iclass 10, count 2 2006.285.13:52:34.55#ibcon#about to read 3, iclass 10, count 2 2006.285.13:52:34.58#ibcon#read 3, iclass 10, count 2 2006.285.13:52:34.58#ibcon#about to read 4, iclass 10, count 2 2006.285.13:52:34.58#ibcon#read 4, iclass 10, count 2 2006.285.13:52:34.58#ibcon#about to read 5, iclass 10, count 2 2006.285.13:52:34.58#ibcon#read 5, iclass 10, count 2 2006.285.13:52:34.58#ibcon#about to read 6, iclass 10, count 2 2006.285.13:52:34.58#ibcon#read 6, iclass 10, count 2 2006.285.13:52:34.58#ibcon#end of sib2, iclass 10, count 2 2006.285.13:52:34.58#ibcon#*after write, iclass 10, count 2 2006.285.13:52:34.58#ibcon#*before return 0, iclass 10, count 2 2006.285.13:52:34.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:52:34.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:52:34.58#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.13:52:34.58#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:34.58#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:52:34.70#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:52:34.70#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:52:34.70#ibcon#enter wrdev, iclass 10, count 0 2006.285.13:52:34.70#ibcon#first serial, iclass 10, count 0 2006.285.13:52:34.70#ibcon#enter sib2, iclass 10, count 0 2006.285.13:52:34.70#ibcon#flushed, iclass 10, count 0 2006.285.13:52:34.70#ibcon#about to write, iclass 10, count 0 2006.285.13:52:34.70#ibcon#wrote, iclass 10, count 0 2006.285.13:52:34.70#ibcon#about to read 3, iclass 10, count 0 2006.285.13:52:34.72#ibcon#read 3, iclass 10, count 0 2006.285.13:52:34.72#ibcon#about to read 4, iclass 10, count 0 2006.285.13:52:34.72#ibcon#read 4, iclass 10, count 0 2006.285.13:52:34.72#ibcon#about to read 5, iclass 10, count 0 2006.285.13:52:34.72#ibcon#read 5, iclass 10, count 0 2006.285.13:52:34.72#ibcon#about to read 6, iclass 10, count 0 2006.285.13:52:34.72#ibcon#read 6, iclass 10, count 0 2006.285.13:52:34.72#ibcon#end of sib2, iclass 10, count 0 2006.285.13:52:34.72#ibcon#*mode == 0, iclass 10, count 0 2006.285.13:52:34.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.13:52:34.72#ibcon#[25=USB\r\n] 2006.285.13:52:34.72#ibcon#*before write, iclass 10, count 0 2006.285.13:52:34.72#ibcon#enter sib2, iclass 10, count 0 2006.285.13:52:34.72#ibcon#flushed, iclass 10, count 0 2006.285.13:52:34.72#ibcon#about to write, iclass 10, count 0 2006.285.13:52:34.72#ibcon#wrote, iclass 10, count 0 2006.285.13:52:34.72#ibcon#about to read 3, iclass 10, count 0 2006.285.13:52:34.75#ibcon#read 3, iclass 10, count 0 2006.285.13:52:34.75#ibcon#about to read 4, iclass 10, count 0 2006.285.13:52:34.75#ibcon#read 4, iclass 10, count 0 2006.285.13:52:34.75#ibcon#about to read 5, iclass 10, count 0 2006.285.13:52:34.75#ibcon#read 5, iclass 10, count 0 2006.285.13:52:34.75#ibcon#about to read 6, iclass 10, count 0 2006.285.13:52:34.75#ibcon#read 6, iclass 10, count 0 2006.285.13:52:34.75#ibcon#end of sib2, iclass 10, count 0 2006.285.13:52:34.75#ibcon#*after write, iclass 10, count 0 2006.285.13:52:34.75#ibcon#*before return 0, iclass 10, count 0 2006.285.13:52:34.75#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:52:34.75#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:52:34.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.13:52:34.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.13:52:34.75$vck44/valo=5,734.99 2006.285.13:52:34.75#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.13:52:34.75#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.13:52:34.75#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:34.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:52:34.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:52:34.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:52:34.75#ibcon#enter wrdev, iclass 12, count 0 2006.285.13:52:34.75#ibcon#first serial, iclass 12, count 0 2006.285.13:52:34.75#ibcon#enter sib2, iclass 12, count 0 2006.285.13:52:34.75#ibcon#flushed, iclass 12, count 0 2006.285.13:52:34.75#ibcon#about to write, iclass 12, count 0 2006.285.13:52:34.75#ibcon#wrote, iclass 12, count 0 2006.285.13:52:34.75#ibcon#about to read 3, iclass 12, count 0 2006.285.13:52:34.77#ibcon#read 3, iclass 12, count 0 2006.285.13:52:34.77#ibcon#about to read 4, iclass 12, count 0 2006.285.13:52:34.77#ibcon#read 4, iclass 12, count 0 2006.285.13:52:34.77#ibcon#about to read 5, iclass 12, count 0 2006.285.13:52:34.77#ibcon#read 5, iclass 12, count 0 2006.285.13:52:34.77#ibcon#about to read 6, iclass 12, count 0 2006.285.13:52:34.77#ibcon#read 6, iclass 12, count 0 2006.285.13:52:34.77#ibcon#end of sib2, iclass 12, count 0 2006.285.13:52:34.77#ibcon#*mode == 0, iclass 12, count 0 2006.285.13:52:34.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.13:52:34.77#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:52:34.77#ibcon#*before write, iclass 12, count 0 2006.285.13:52:34.77#ibcon#enter sib2, iclass 12, count 0 2006.285.13:52:34.77#ibcon#flushed, iclass 12, count 0 2006.285.13:52:34.77#ibcon#about to write, iclass 12, count 0 2006.285.13:52:34.77#ibcon#wrote, iclass 12, count 0 2006.285.13:52:34.77#ibcon#about to read 3, iclass 12, count 0 2006.285.13:52:34.81#ibcon#read 3, iclass 12, count 0 2006.285.13:52:34.81#ibcon#about to read 4, iclass 12, count 0 2006.285.13:52:34.81#ibcon#read 4, iclass 12, count 0 2006.285.13:52:34.81#ibcon#about to read 5, iclass 12, count 0 2006.285.13:52:34.81#ibcon#read 5, iclass 12, count 0 2006.285.13:52:34.81#ibcon#about to read 6, iclass 12, count 0 2006.285.13:52:34.81#ibcon#read 6, iclass 12, count 0 2006.285.13:52:34.81#ibcon#end of sib2, iclass 12, count 0 2006.285.13:52:34.81#ibcon#*after write, iclass 12, count 0 2006.285.13:52:34.81#ibcon#*before return 0, iclass 12, count 0 2006.285.13:52:34.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:52:34.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:52:34.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.13:52:34.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.13:52:34.81$vck44/va=5,3 2006.285.13:52:34.81#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.13:52:34.81#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.13:52:34.81#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:34.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:52:34.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:52:34.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:52:34.87#ibcon#enter wrdev, iclass 14, count 2 2006.285.13:52:34.87#ibcon#first serial, iclass 14, count 2 2006.285.13:52:34.87#ibcon#enter sib2, iclass 14, count 2 2006.285.13:52:34.87#ibcon#flushed, iclass 14, count 2 2006.285.13:52:34.87#ibcon#about to write, iclass 14, count 2 2006.285.13:52:34.87#ibcon#wrote, iclass 14, count 2 2006.285.13:52:34.87#ibcon#about to read 3, iclass 14, count 2 2006.285.13:52:34.89#ibcon#read 3, iclass 14, count 2 2006.285.13:52:34.89#ibcon#about to read 4, iclass 14, count 2 2006.285.13:52:34.89#ibcon#read 4, iclass 14, count 2 2006.285.13:52:34.89#ibcon#about to read 5, iclass 14, count 2 2006.285.13:52:34.89#ibcon#read 5, iclass 14, count 2 2006.285.13:52:34.89#ibcon#about to read 6, iclass 14, count 2 2006.285.13:52:34.89#ibcon#read 6, iclass 14, count 2 2006.285.13:52:34.89#ibcon#end of sib2, iclass 14, count 2 2006.285.13:52:34.89#ibcon#*mode == 0, iclass 14, count 2 2006.285.13:52:34.89#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.13:52:34.89#ibcon#[25=AT05-03\r\n] 2006.285.13:52:34.89#ibcon#*before write, iclass 14, count 2 2006.285.13:52:34.89#ibcon#enter sib2, iclass 14, count 2 2006.285.13:52:34.89#ibcon#flushed, iclass 14, count 2 2006.285.13:52:34.89#ibcon#about to write, iclass 14, count 2 2006.285.13:52:34.89#ibcon#wrote, iclass 14, count 2 2006.285.13:52:34.89#ibcon#about to read 3, iclass 14, count 2 2006.285.13:52:34.92#ibcon#read 3, iclass 14, count 2 2006.285.13:52:34.92#ibcon#about to read 4, iclass 14, count 2 2006.285.13:52:34.92#ibcon#read 4, iclass 14, count 2 2006.285.13:52:34.92#ibcon#about to read 5, iclass 14, count 2 2006.285.13:52:34.92#ibcon#read 5, iclass 14, count 2 2006.285.13:52:34.92#ibcon#about to read 6, iclass 14, count 2 2006.285.13:52:34.92#ibcon#read 6, iclass 14, count 2 2006.285.13:52:34.92#ibcon#end of sib2, iclass 14, count 2 2006.285.13:52:34.92#ibcon#*after write, iclass 14, count 2 2006.285.13:52:34.92#ibcon#*before return 0, iclass 14, count 2 2006.285.13:52:34.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:52:34.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:52:34.92#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.13:52:34.92#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:34.92#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:52:35.04#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:52:35.04#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:52:35.04#ibcon#enter wrdev, iclass 14, count 0 2006.285.13:52:35.04#ibcon#first serial, iclass 14, count 0 2006.285.13:52:35.04#ibcon#enter sib2, iclass 14, count 0 2006.285.13:52:35.04#ibcon#flushed, iclass 14, count 0 2006.285.13:52:35.04#ibcon#about to write, iclass 14, count 0 2006.285.13:52:35.04#ibcon#wrote, iclass 14, count 0 2006.285.13:52:35.04#ibcon#about to read 3, iclass 14, count 0 2006.285.13:52:35.06#ibcon#read 3, iclass 14, count 0 2006.285.13:52:35.06#ibcon#about to read 4, iclass 14, count 0 2006.285.13:52:35.06#ibcon#read 4, iclass 14, count 0 2006.285.13:52:35.06#ibcon#about to read 5, iclass 14, count 0 2006.285.13:52:35.06#ibcon#read 5, iclass 14, count 0 2006.285.13:52:35.06#ibcon#about to read 6, iclass 14, count 0 2006.285.13:52:35.06#ibcon#read 6, iclass 14, count 0 2006.285.13:52:35.06#ibcon#end of sib2, iclass 14, count 0 2006.285.13:52:35.06#ibcon#*mode == 0, iclass 14, count 0 2006.285.13:52:35.06#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.13:52:35.06#ibcon#[25=USB\r\n] 2006.285.13:52:35.06#ibcon#*before write, iclass 14, count 0 2006.285.13:52:35.06#ibcon#enter sib2, iclass 14, count 0 2006.285.13:52:35.06#ibcon#flushed, iclass 14, count 0 2006.285.13:52:35.06#ibcon#about to write, iclass 14, count 0 2006.285.13:52:35.06#ibcon#wrote, iclass 14, count 0 2006.285.13:52:35.06#ibcon#about to read 3, iclass 14, count 0 2006.285.13:52:35.09#ibcon#read 3, iclass 14, count 0 2006.285.13:52:35.09#ibcon#about to read 4, iclass 14, count 0 2006.285.13:52:35.09#ibcon#read 4, iclass 14, count 0 2006.285.13:52:35.09#ibcon#about to read 5, iclass 14, count 0 2006.285.13:52:35.09#ibcon#read 5, iclass 14, count 0 2006.285.13:52:35.09#ibcon#about to read 6, iclass 14, count 0 2006.285.13:52:35.09#ibcon#read 6, iclass 14, count 0 2006.285.13:52:35.09#ibcon#end of sib2, iclass 14, count 0 2006.285.13:52:35.09#ibcon#*after write, iclass 14, count 0 2006.285.13:52:35.09#ibcon#*before return 0, iclass 14, count 0 2006.285.13:52:35.09#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:52:35.09#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:52:35.09#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.13:52:35.09#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.13:52:35.09$vck44/valo=6,814.99 2006.285.13:52:35.09#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.13:52:35.09#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.13:52:35.09#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:35.09#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:52:35.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:52:35.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:52:35.09#ibcon#enter wrdev, iclass 16, count 0 2006.285.13:52:35.09#ibcon#first serial, iclass 16, count 0 2006.285.13:52:35.09#ibcon#enter sib2, iclass 16, count 0 2006.285.13:52:35.09#ibcon#flushed, iclass 16, count 0 2006.285.13:52:35.09#ibcon#about to write, iclass 16, count 0 2006.285.13:52:35.09#ibcon#wrote, iclass 16, count 0 2006.285.13:52:35.09#ibcon#about to read 3, iclass 16, count 0 2006.285.13:52:35.11#ibcon#read 3, iclass 16, count 0 2006.285.13:52:35.11#ibcon#about to read 4, iclass 16, count 0 2006.285.13:52:35.11#ibcon#read 4, iclass 16, count 0 2006.285.13:52:35.11#ibcon#about to read 5, iclass 16, count 0 2006.285.13:52:35.11#ibcon#read 5, iclass 16, count 0 2006.285.13:52:35.11#ibcon#about to read 6, iclass 16, count 0 2006.285.13:52:35.11#ibcon#read 6, iclass 16, count 0 2006.285.13:52:35.11#ibcon#end of sib2, iclass 16, count 0 2006.285.13:52:35.11#ibcon#*mode == 0, iclass 16, count 0 2006.285.13:52:35.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.13:52:35.11#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:52:35.11#ibcon#*before write, iclass 16, count 0 2006.285.13:52:35.11#ibcon#enter sib2, iclass 16, count 0 2006.285.13:52:35.11#ibcon#flushed, iclass 16, count 0 2006.285.13:52:35.11#ibcon#about to write, iclass 16, count 0 2006.285.13:52:35.11#ibcon#wrote, iclass 16, count 0 2006.285.13:52:35.11#ibcon#about to read 3, iclass 16, count 0 2006.285.13:52:35.15#ibcon#read 3, iclass 16, count 0 2006.285.13:52:35.15#ibcon#about to read 4, iclass 16, count 0 2006.285.13:52:35.15#ibcon#read 4, iclass 16, count 0 2006.285.13:52:35.15#ibcon#about to read 5, iclass 16, count 0 2006.285.13:52:35.15#ibcon#read 5, iclass 16, count 0 2006.285.13:52:35.15#ibcon#about to read 6, iclass 16, count 0 2006.285.13:52:35.15#ibcon#read 6, iclass 16, count 0 2006.285.13:52:35.15#ibcon#end of sib2, iclass 16, count 0 2006.285.13:52:35.15#ibcon#*after write, iclass 16, count 0 2006.285.13:52:35.15#ibcon#*before return 0, iclass 16, count 0 2006.285.13:52:35.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:52:35.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:52:35.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.13:52:35.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.13:52:35.15$vck44/va=6,4 2006.285.13:52:35.15#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.13:52:35.15#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.13:52:35.15#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:35.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:52:35.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:52:35.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:52:35.21#ibcon#enter wrdev, iclass 18, count 2 2006.285.13:52:35.21#ibcon#first serial, iclass 18, count 2 2006.285.13:52:35.21#ibcon#enter sib2, iclass 18, count 2 2006.285.13:52:35.21#ibcon#flushed, iclass 18, count 2 2006.285.13:52:35.21#ibcon#about to write, iclass 18, count 2 2006.285.13:52:35.21#ibcon#wrote, iclass 18, count 2 2006.285.13:52:35.21#ibcon#about to read 3, iclass 18, count 2 2006.285.13:52:35.23#ibcon#read 3, iclass 18, count 2 2006.285.13:52:35.23#ibcon#about to read 4, iclass 18, count 2 2006.285.13:52:35.23#ibcon#read 4, iclass 18, count 2 2006.285.13:52:35.23#ibcon#about to read 5, iclass 18, count 2 2006.285.13:52:35.23#ibcon#read 5, iclass 18, count 2 2006.285.13:52:35.23#ibcon#about to read 6, iclass 18, count 2 2006.285.13:52:35.23#ibcon#read 6, iclass 18, count 2 2006.285.13:52:35.23#ibcon#end of sib2, iclass 18, count 2 2006.285.13:52:35.23#ibcon#*mode == 0, iclass 18, count 2 2006.285.13:52:35.23#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.13:52:35.23#ibcon#[25=AT06-04\r\n] 2006.285.13:52:35.23#ibcon#*before write, iclass 18, count 2 2006.285.13:52:35.23#ibcon#enter sib2, iclass 18, count 2 2006.285.13:52:35.23#ibcon#flushed, iclass 18, count 2 2006.285.13:52:35.23#ibcon#about to write, iclass 18, count 2 2006.285.13:52:35.23#ibcon#wrote, iclass 18, count 2 2006.285.13:52:35.23#ibcon#about to read 3, iclass 18, count 2 2006.285.13:52:35.26#ibcon#read 3, iclass 18, count 2 2006.285.13:52:35.26#ibcon#about to read 4, iclass 18, count 2 2006.285.13:52:35.26#ibcon#read 4, iclass 18, count 2 2006.285.13:52:35.26#ibcon#about to read 5, iclass 18, count 2 2006.285.13:52:35.26#ibcon#read 5, iclass 18, count 2 2006.285.13:52:35.26#ibcon#about to read 6, iclass 18, count 2 2006.285.13:52:35.26#ibcon#read 6, iclass 18, count 2 2006.285.13:52:35.26#ibcon#end of sib2, iclass 18, count 2 2006.285.13:52:35.26#ibcon#*after write, iclass 18, count 2 2006.285.13:52:35.26#ibcon#*before return 0, iclass 18, count 2 2006.285.13:52:35.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:52:35.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:52:35.26#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.13:52:35.26#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:35.26#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:52:35.38#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:52:35.38#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:52:35.38#ibcon#enter wrdev, iclass 18, count 0 2006.285.13:52:35.38#ibcon#first serial, iclass 18, count 0 2006.285.13:52:35.38#ibcon#enter sib2, iclass 18, count 0 2006.285.13:52:35.38#ibcon#flushed, iclass 18, count 0 2006.285.13:52:35.38#ibcon#about to write, iclass 18, count 0 2006.285.13:52:35.38#ibcon#wrote, iclass 18, count 0 2006.285.13:52:35.38#ibcon#about to read 3, iclass 18, count 0 2006.285.13:52:35.40#ibcon#read 3, iclass 18, count 0 2006.285.13:52:35.40#ibcon#about to read 4, iclass 18, count 0 2006.285.13:52:35.40#ibcon#read 4, iclass 18, count 0 2006.285.13:52:35.40#ibcon#about to read 5, iclass 18, count 0 2006.285.13:52:35.40#ibcon#read 5, iclass 18, count 0 2006.285.13:52:35.40#ibcon#about to read 6, iclass 18, count 0 2006.285.13:52:35.40#ibcon#read 6, iclass 18, count 0 2006.285.13:52:35.40#ibcon#end of sib2, iclass 18, count 0 2006.285.13:52:35.40#ibcon#*mode == 0, iclass 18, count 0 2006.285.13:52:35.40#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.13:52:35.40#ibcon#[25=USB\r\n] 2006.285.13:52:35.40#ibcon#*before write, iclass 18, count 0 2006.285.13:52:35.40#ibcon#enter sib2, iclass 18, count 0 2006.285.13:52:35.40#ibcon#flushed, iclass 18, count 0 2006.285.13:52:35.40#ibcon#about to write, iclass 18, count 0 2006.285.13:52:35.40#ibcon#wrote, iclass 18, count 0 2006.285.13:52:35.40#ibcon#about to read 3, iclass 18, count 0 2006.285.13:52:35.43#ibcon#read 3, iclass 18, count 0 2006.285.13:52:35.43#ibcon#about to read 4, iclass 18, count 0 2006.285.13:52:35.43#ibcon#read 4, iclass 18, count 0 2006.285.13:52:35.43#ibcon#about to read 5, iclass 18, count 0 2006.285.13:52:35.43#ibcon#read 5, iclass 18, count 0 2006.285.13:52:35.43#ibcon#about to read 6, iclass 18, count 0 2006.285.13:52:35.43#ibcon#read 6, iclass 18, count 0 2006.285.13:52:35.43#ibcon#end of sib2, iclass 18, count 0 2006.285.13:52:35.43#ibcon#*after write, iclass 18, count 0 2006.285.13:52:35.43#ibcon#*before return 0, iclass 18, count 0 2006.285.13:52:35.43#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:52:35.43#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:52:35.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.13:52:35.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.13:52:35.43$vck44/valo=7,864.99 2006.285.13:52:35.43#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.13:52:35.43#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.13:52:35.43#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:35.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:52:35.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:52:35.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:52:35.43#ibcon#enter wrdev, iclass 20, count 0 2006.285.13:52:35.43#ibcon#first serial, iclass 20, count 0 2006.285.13:52:35.43#ibcon#enter sib2, iclass 20, count 0 2006.285.13:52:35.43#ibcon#flushed, iclass 20, count 0 2006.285.13:52:35.43#ibcon#about to write, iclass 20, count 0 2006.285.13:52:35.43#ibcon#wrote, iclass 20, count 0 2006.285.13:52:35.43#ibcon#about to read 3, iclass 20, count 0 2006.285.13:52:35.45#ibcon#read 3, iclass 20, count 0 2006.285.13:52:35.61#ibcon#about to read 4, iclass 20, count 0 2006.285.13:52:35.61#ibcon#read 4, iclass 20, count 0 2006.285.13:52:35.61#ibcon#about to read 5, iclass 20, count 0 2006.285.13:52:35.61#ibcon#read 5, iclass 20, count 0 2006.285.13:52:35.61#ibcon#about to read 6, iclass 20, count 0 2006.285.13:52:35.61#ibcon#read 6, iclass 20, count 0 2006.285.13:52:35.61#ibcon#end of sib2, iclass 20, count 0 2006.285.13:52:35.61#ibcon#*mode == 0, iclass 20, count 0 2006.285.13:52:35.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.13:52:35.61#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:52:35.61#ibcon#*before write, iclass 20, count 0 2006.285.13:52:35.61#ibcon#enter sib2, iclass 20, count 0 2006.285.13:52:35.61#ibcon#flushed, iclass 20, count 0 2006.285.13:52:35.61#ibcon#about to write, iclass 20, count 0 2006.285.13:52:35.61#ibcon#wrote, iclass 20, count 0 2006.285.13:52:35.61#ibcon#about to read 3, iclass 20, count 0 2006.285.13:52:35.65#ibcon#read 3, iclass 20, count 0 2006.285.13:52:35.65#ibcon#about to read 4, iclass 20, count 0 2006.285.13:52:35.65#ibcon#read 4, iclass 20, count 0 2006.285.13:52:35.65#ibcon#about to read 5, iclass 20, count 0 2006.285.13:52:35.65#ibcon#read 5, iclass 20, count 0 2006.285.13:52:35.65#ibcon#about to read 6, iclass 20, count 0 2006.285.13:52:35.65#ibcon#read 6, iclass 20, count 0 2006.285.13:52:35.65#ibcon#end of sib2, iclass 20, count 0 2006.285.13:52:35.65#ibcon#*after write, iclass 20, count 0 2006.285.13:52:35.65#ibcon#*before return 0, iclass 20, count 0 2006.285.13:52:35.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:52:35.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:52:35.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.13:52:35.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.13:52:35.65$vck44/va=7,4 2006.285.13:52:35.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.13:52:35.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.13:52:35.65#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:35.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:52:35.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:52:35.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:52:35.65#ibcon#enter wrdev, iclass 22, count 2 2006.285.13:52:35.65#ibcon#first serial, iclass 22, count 2 2006.285.13:52:35.65#ibcon#enter sib2, iclass 22, count 2 2006.285.13:52:35.65#ibcon#flushed, iclass 22, count 2 2006.285.13:52:35.65#ibcon#about to write, iclass 22, count 2 2006.285.13:52:35.65#ibcon#wrote, iclass 22, count 2 2006.285.13:52:35.65#ibcon#about to read 3, iclass 22, count 2 2006.285.13:52:35.67#ibcon#read 3, iclass 22, count 2 2006.285.13:52:35.67#ibcon#about to read 4, iclass 22, count 2 2006.285.13:52:35.67#ibcon#read 4, iclass 22, count 2 2006.285.13:52:35.67#ibcon#about to read 5, iclass 22, count 2 2006.285.13:52:35.67#ibcon#read 5, iclass 22, count 2 2006.285.13:52:35.67#ibcon#about to read 6, iclass 22, count 2 2006.285.13:52:35.67#ibcon#read 6, iclass 22, count 2 2006.285.13:52:35.67#ibcon#end of sib2, iclass 22, count 2 2006.285.13:52:35.67#ibcon#*mode == 0, iclass 22, count 2 2006.285.13:52:35.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.13:52:35.67#ibcon#[25=AT07-04\r\n] 2006.285.13:52:35.67#ibcon#*before write, iclass 22, count 2 2006.285.13:52:35.67#ibcon#enter sib2, iclass 22, count 2 2006.285.13:52:35.67#ibcon#flushed, iclass 22, count 2 2006.285.13:52:35.67#ibcon#about to write, iclass 22, count 2 2006.285.13:52:35.67#ibcon#wrote, iclass 22, count 2 2006.285.13:52:35.67#ibcon#about to read 3, iclass 22, count 2 2006.285.13:52:35.70#ibcon#read 3, iclass 22, count 2 2006.285.13:52:35.70#ibcon#about to read 4, iclass 22, count 2 2006.285.13:52:35.70#ibcon#read 4, iclass 22, count 2 2006.285.13:52:35.70#ibcon#about to read 5, iclass 22, count 2 2006.285.13:52:35.70#ibcon#read 5, iclass 22, count 2 2006.285.13:52:35.70#ibcon#about to read 6, iclass 22, count 2 2006.285.13:52:35.70#ibcon#read 6, iclass 22, count 2 2006.285.13:52:35.70#ibcon#end of sib2, iclass 22, count 2 2006.285.13:52:35.70#ibcon#*after write, iclass 22, count 2 2006.285.13:52:35.70#ibcon#*before return 0, iclass 22, count 2 2006.285.13:52:35.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:52:35.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:52:35.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.13:52:35.70#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:35.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:52:35.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:52:35.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:52:35.82#ibcon#enter wrdev, iclass 22, count 0 2006.285.13:52:35.82#ibcon#first serial, iclass 22, count 0 2006.285.13:52:35.82#ibcon#enter sib2, iclass 22, count 0 2006.285.13:52:35.82#ibcon#flushed, iclass 22, count 0 2006.285.13:52:35.82#ibcon#about to write, iclass 22, count 0 2006.285.13:52:35.82#ibcon#wrote, iclass 22, count 0 2006.285.13:52:35.82#ibcon#about to read 3, iclass 22, count 0 2006.285.13:52:35.84#ibcon#read 3, iclass 22, count 0 2006.285.13:52:35.84#ibcon#about to read 4, iclass 22, count 0 2006.285.13:52:35.84#ibcon#read 4, iclass 22, count 0 2006.285.13:52:35.84#ibcon#about to read 5, iclass 22, count 0 2006.285.13:52:35.84#ibcon#read 5, iclass 22, count 0 2006.285.13:52:35.84#ibcon#about to read 6, iclass 22, count 0 2006.285.13:52:35.84#ibcon#read 6, iclass 22, count 0 2006.285.13:52:35.84#ibcon#end of sib2, iclass 22, count 0 2006.285.13:52:35.84#ibcon#*mode == 0, iclass 22, count 0 2006.285.13:52:35.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.13:52:35.84#ibcon#[25=USB\r\n] 2006.285.13:52:35.84#ibcon#*before write, iclass 22, count 0 2006.285.13:52:35.84#ibcon#enter sib2, iclass 22, count 0 2006.285.13:52:35.84#ibcon#flushed, iclass 22, count 0 2006.285.13:52:35.84#ibcon#about to write, iclass 22, count 0 2006.285.13:52:35.84#ibcon#wrote, iclass 22, count 0 2006.285.13:52:35.84#ibcon#about to read 3, iclass 22, count 0 2006.285.13:52:35.87#ibcon#read 3, iclass 22, count 0 2006.285.13:52:35.87#ibcon#about to read 4, iclass 22, count 0 2006.285.13:52:35.87#ibcon#read 4, iclass 22, count 0 2006.285.13:52:35.87#ibcon#about to read 5, iclass 22, count 0 2006.285.13:52:35.87#ibcon#read 5, iclass 22, count 0 2006.285.13:52:35.87#ibcon#about to read 6, iclass 22, count 0 2006.285.13:52:35.87#ibcon#read 6, iclass 22, count 0 2006.285.13:52:35.87#ibcon#end of sib2, iclass 22, count 0 2006.285.13:52:35.87#ibcon#*after write, iclass 22, count 0 2006.285.13:52:35.87#ibcon#*before return 0, iclass 22, count 0 2006.285.13:52:35.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:52:35.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:52:35.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.13:52:35.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.13:52:35.87$vck44/valo=8,884.99 2006.285.13:52:35.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.13:52:35.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.13:52:35.87#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:35.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:52:35.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:52:35.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:52:35.87#ibcon#enter wrdev, iclass 24, count 0 2006.285.13:52:35.87#ibcon#first serial, iclass 24, count 0 2006.285.13:52:35.87#ibcon#enter sib2, iclass 24, count 0 2006.285.13:52:35.87#ibcon#flushed, iclass 24, count 0 2006.285.13:52:35.87#ibcon#about to write, iclass 24, count 0 2006.285.13:52:35.87#ibcon#wrote, iclass 24, count 0 2006.285.13:52:35.87#ibcon#about to read 3, iclass 24, count 0 2006.285.13:52:35.89#ibcon#read 3, iclass 24, count 0 2006.285.13:52:35.89#ibcon#about to read 4, iclass 24, count 0 2006.285.13:52:35.89#ibcon#read 4, iclass 24, count 0 2006.285.13:52:35.89#ibcon#about to read 5, iclass 24, count 0 2006.285.13:52:35.89#ibcon#read 5, iclass 24, count 0 2006.285.13:52:35.89#ibcon#about to read 6, iclass 24, count 0 2006.285.13:52:35.89#ibcon#read 6, iclass 24, count 0 2006.285.13:52:35.89#ibcon#end of sib2, iclass 24, count 0 2006.285.13:52:35.89#ibcon#*mode == 0, iclass 24, count 0 2006.285.13:52:35.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.13:52:35.89#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:52:35.89#ibcon#*before write, iclass 24, count 0 2006.285.13:52:35.89#ibcon#enter sib2, iclass 24, count 0 2006.285.13:52:35.89#ibcon#flushed, iclass 24, count 0 2006.285.13:52:35.89#ibcon#about to write, iclass 24, count 0 2006.285.13:52:35.89#ibcon#wrote, iclass 24, count 0 2006.285.13:52:35.89#ibcon#about to read 3, iclass 24, count 0 2006.285.13:52:35.93#ibcon#read 3, iclass 24, count 0 2006.285.13:52:35.93#ibcon#about to read 4, iclass 24, count 0 2006.285.13:52:35.93#ibcon#read 4, iclass 24, count 0 2006.285.13:52:35.93#ibcon#about to read 5, iclass 24, count 0 2006.285.13:52:35.93#ibcon#read 5, iclass 24, count 0 2006.285.13:52:35.93#ibcon#about to read 6, iclass 24, count 0 2006.285.13:52:35.93#ibcon#read 6, iclass 24, count 0 2006.285.13:52:35.93#ibcon#end of sib2, iclass 24, count 0 2006.285.13:52:35.93#ibcon#*after write, iclass 24, count 0 2006.285.13:52:35.93#ibcon#*before return 0, iclass 24, count 0 2006.285.13:52:35.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:52:35.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:52:35.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.13:52:35.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.13:52:35.93$vck44/va=8,3 2006.285.13:52:35.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.13:52:35.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.13:52:35.93#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:35.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:52:35.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:52:35.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:52:35.99#ibcon#enter wrdev, iclass 26, count 2 2006.285.13:52:35.99#ibcon#first serial, iclass 26, count 2 2006.285.13:52:35.99#ibcon#enter sib2, iclass 26, count 2 2006.285.13:52:35.99#ibcon#flushed, iclass 26, count 2 2006.285.13:52:35.99#ibcon#about to write, iclass 26, count 2 2006.285.13:52:35.99#ibcon#wrote, iclass 26, count 2 2006.285.13:52:35.99#ibcon#about to read 3, iclass 26, count 2 2006.285.13:52:36.01#ibcon#read 3, iclass 26, count 2 2006.285.13:52:36.01#ibcon#about to read 4, iclass 26, count 2 2006.285.13:52:36.01#ibcon#read 4, iclass 26, count 2 2006.285.13:52:36.01#ibcon#about to read 5, iclass 26, count 2 2006.285.13:52:36.01#ibcon#read 5, iclass 26, count 2 2006.285.13:52:36.01#ibcon#about to read 6, iclass 26, count 2 2006.285.13:52:36.01#ibcon#read 6, iclass 26, count 2 2006.285.13:52:36.01#ibcon#end of sib2, iclass 26, count 2 2006.285.13:52:36.01#ibcon#*mode == 0, iclass 26, count 2 2006.285.13:52:36.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.13:52:36.01#ibcon#[25=AT08-03\r\n] 2006.285.13:52:36.01#ibcon#*before write, iclass 26, count 2 2006.285.13:52:36.01#ibcon#enter sib2, iclass 26, count 2 2006.285.13:52:36.01#ibcon#flushed, iclass 26, count 2 2006.285.13:52:36.01#ibcon#about to write, iclass 26, count 2 2006.285.13:52:36.01#ibcon#wrote, iclass 26, count 2 2006.285.13:52:36.01#ibcon#about to read 3, iclass 26, count 2 2006.285.13:52:36.04#ibcon#read 3, iclass 26, count 2 2006.285.13:52:36.04#ibcon#about to read 4, iclass 26, count 2 2006.285.13:52:36.04#ibcon#read 4, iclass 26, count 2 2006.285.13:52:36.04#ibcon#about to read 5, iclass 26, count 2 2006.285.13:52:36.04#ibcon#read 5, iclass 26, count 2 2006.285.13:52:36.04#ibcon#about to read 6, iclass 26, count 2 2006.285.13:52:36.04#ibcon#read 6, iclass 26, count 2 2006.285.13:52:36.04#ibcon#end of sib2, iclass 26, count 2 2006.285.13:52:36.04#ibcon#*after write, iclass 26, count 2 2006.285.13:52:36.04#ibcon#*before return 0, iclass 26, count 2 2006.285.13:52:36.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:52:36.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:52:36.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.13:52:36.04#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:36.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:52:36.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:52:36.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:52:36.16#ibcon#enter wrdev, iclass 26, count 0 2006.285.13:52:36.16#ibcon#first serial, iclass 26, count 0 2006.285.13:52:36.16#ibcon#enter sib2, iclass 26, count 0 2006.285.13:52:36.16#ibcon#flushed, iclass 26, count 0 2006.285.13:52:36.16#ibcon#about to write, iclass 26, count 0 2006.285.13:52:36.16#ibcon#wrote, iclass 26, count 0 2006.285.13:52:36.16#ibcon#about to read 3, iclass 26, count 0 2006.285.13:52:36.18#ibcon#read 3, iclass 26, count 0 2006.285.13:52:36.18#ibcon#about to read 4, iclass 26, count 0 2006.285.13:52:36.18#ibcon#read 4, iclass 26, count 0 2006.285.13:52:36.18#ibcon#about to read 5, iclass 26, count 0 2006.285.13:52:36.18#ibcon#read 5, iclass 26, count 0 2006.285.13:52:36.18#ibcon#about to read 6, iclass 26, count 0 2006.285.13:52:36.18#ibcon#read 6, iclass 26, count 0 2006.285.13:52:36.18#ibcon#end of sib2, iclass 26, count 0 2006.285.13:52:36.18#ibcon#*mode == 0, iclass 26, count 0 2006.285.13:52:36.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.13:52:36.18#ibcon#[25=USB\r\n] 2006.285.13:52:36.18#ibcon#*before write, iclass 26, count 0 2006.285.13:52:36.18#ibcon#enter sib2, iclass 26, count 0 2006.285.13:52:36.18#ibcon#flushed, iclass 26, count 0 2006.285.13:52:36.18#ibcon#about to write, iclass 26, count 0 2006.285.13:52:36.18#ibcon#wrote, iclass 26, count 0 2006.285.13:52:36.18#ibcon#about to read 3, iclass 26, count 0 2006.285.13:52:36.21#ibcon#read 3, iclass 26, count 0 2006.285.13:52:36.21#ibcon#about to read 4, iclass 26, count 0 2006.285.13:52:36.21#ibcon#read 4, iclass 26, count 0 2006.285.13:52:36.21#ibcon#about to read 5, iclass 26, count 0 2006.285.13:52:36.21#ibcon#read 5, iclass 26, count 0 2006.285.13:52:36.21#ibcon#about to read 6, iclass 26, count 0 2006.285.13:52:36.21#ibcon#read 6, iclass 26, count 0 2006.285.13:52:36.21#ibcon#end of sib2, iclass 26, count 0 2006.285.13:52:36.21#ibcon#*after write, iclass 26, count 0 2006.285.13:52:36.21#ibcon#*before return 0, iclass 26, count 0 2006.285.13:52:36.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:52:36.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:52:36.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.13:52:36.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.13:52:36.21$vck44/vblo=1,629.99 2006.285.13:52:36.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.13:52:36.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.13:52:36.21#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:36.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:52:36.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:52:36.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:52:36.21#ibcon#enter wrdev, iclass 28, count 0 2006.285.13:52:36.21#ibcon#first serial, iclass 28, count 0 2006.285.13:52:36.21#ibcon#enter sib2, iclass 28, count 0 2006.285.13:52:36.21#ibcon#flushed, iclass 28, count 0 2006.285.13:52:36.21#ibcon#about to write, iclass 28, count 0 2006.285.13:52:36.21#ibcon#wrote, iclass 28, count 0 2006.285.13:52:36.21#ibcon#about to read 3, iclass 28, count 0 2006.285.13:52:36.23#ibcon#read 3, iclass 28, count 0 2006.285.13:52:36.23#ibcon#about to read 4, iclass 28, count 0 2006.285.13:52:36.23#ibcon#read 4, iclass 28, count 0 2006.285.13:52:36.23#ibcon#about to read 5, iclass 28, count 0 2006.285.13:52:36.23#ibcon#read 5, iclass 28, count 0 2006.285.13:52:36.23#ibcon#about to read 6, iclass 28, count 0 2006.285.13:52:36.23#ibcon#read 6, iclass 28, count 0 2006.285.13:52:36.23#ibcon#end of sib2, iclass 28, count 0 2006.285.13:52:36.23#ibcon#*mode == 0, iclass 28, count 0 2006.285.13:52:36.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.13:52:36.23#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:52:36.23#ibcon#*before write, iclass 28, count 0 2006.285.13:52:36.23#ibcon#enter sib2, iclass 28, count 0 2006.285.13:52:36.23#ibcon#flushed, iclass 28, count 0 2006.285.13:52:36.23#ibcon#about to write, iclass 28, count 0 2006.285.13:52:36.23#ibcon#wrote, iclass 28, count 0 2006.285.13:52:36.23#ibcon#about to read 3, iclass 28, count 0 2006.285.13:52:36.27#ibcon#read 3, iclass 28, count 0 2006.285.13:52:36.27#ibcon#about to read 4, iclass 28, count 0 2006.285.13:52:36.27#ibcon#read 4, iclass 28, count 0 2006.285.13:52:36.27#ibcon#about to read 5, iclass 28, count 0 2006.285.13:52:36.27#ibcon#read 5, iclass 28, count 0 2006.285.13:52:36.27#ibcon#about to read 6, iclass 28, count 0 2006.285.13:52:36.27#ibcon#read 6, iclass 28, count 0 2006.285.13:52:36.27#ibcon#end of sib2, iclass 28, count 0 2006.285.13:52:36.27#ibcon#*after write, iclass 28, count 0 2006.285.13:52:36.27#ibcon#*before return 0, iclass 28, count 0 2006.285.13:52:36.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:52:36.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:52:36.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.13:52:36.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.13:52:36.27$vck44/vb=1,4 2006.285.13:52:36.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.13:52:36.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.13:52:36.27#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:36.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:52:36.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:52:36.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:52:36.27#ibcon#enter wrdev, iclass 30, count 2 2006.285.13:52:36.27#ibcon#first serial, iclass 30, count 2 2006.285.13:52:36.27#ibcon#enter sib2, iclass 30, count 2 2006.285.13:52:36.27#ibcon#flushed, iclass 30, count 2 2006.285.13:52:36.27#ibcon#about to write, iclass 30, count 2 2006.285.13:52:36.27#ibcon#wrote, iclass 30, count 2 2006.285.13:52:36.27#ibcon#about to read 3, iclass 30, count 2 2006.285.13:52:36.29#ibcon#read 3, iclass 30, count 2 2006.285.13:52:36.29#ibcon#about to read 4, iclass 30, count 2 2006.285.13:52:36.29#ibcon#read 4, iclass 30, count 2 2006.285.13:52:36.29#ibcon#about to read 5, iclass 30, count 2 2006.285.13:52:36.29#ibcon#read 5, iclass 30, count 2 2006.285.13:52:36.29#ibcon#about to read 6, iclass 30, count 2 2006.285.13:52:36.29#ibcon#read 6, iclass 30, count 2 2006.285.13:52:36.29#ibcon#end of sib2, iclass 30, count 2 2006.285.13:52:36.29#ibcon#*mode == 0, iclass 30, count 2 2006.285.13:52:36.29#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.13:52:36.29#ibcon#[27=AT01-04\r\n] 2006.285.13:52:36.29#ibcon#*before write, iclass 30, count 2 2006.285.13:52:36.29#ibcon#enter sib2, iclass 30, count 2 2006.285.13:52:36.29#ibcon#flushed, iclass 30, count 2 2006.285.13:52:36.29#ibcon#about to write, iclass 30, count 2 2006.285.13:52:36.29#ibcon#wrote, iclass 30, count 2 2006.285.13:52:36.29#ibcon#about to read 3, iclass 30, count 2 2006.285.13:52:36.32#ibcon#read 3, iclass 30, count 2 2006.285.13:52:36.32#ibcon#about to read 4, iclass 30, count 2 2006.285.13:52:36.32#ibcon#read 4, iclass 30, count 2 2006.285.13:52:36.32#ibcon#about to read 5, iclass 30, count 2 2006.285.13:52:36.32#ibcon#read 5, iclass 30, count 2 2006.285.13:52:36.32#ibcon#about to read 6, iclass 30, count 2 2006.285.13:52:36.32#ibcon#read 6, iclass 30, count 2 2006.285.13:52:36.32#ibcon#end of sib2, iclass 30, count 2 2006.285.13:52:36.32#ibcon#*after write, iclass 30, count 2 2006.285.13:52:36.32#ibcon#*before return 0, iclass 30, count 2 2006.285.13:52:36.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:52:36.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.13:52:36.32#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.13:52:36.32#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:36.32#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:52:36.44#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:52:36.44#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:52:36.44#ibcon#enter wrdev, iclass 30, count 0 2006.285.13:52:36.44#ibcon#first serial, iclass 30, count 0 2006.285.13:52:36.44#ibcon#enter sib2, iclass 30, count 0 2006.285.13:52:36.44#ibcon#flushed, iclass 30, count 0 2006.285.13:52:36.44#ibcon#about to write, iclass 30, count 0 2006.285.13:52:36.44#ibcon#wrote, iclass 30, count 0 2006.285.13:52:36.44#ibcon#about to read 3, iclass 30, count 0 2006.285.13:52:36.46#ibcon#read 3, iclass 30, count 0 2006.285.13:52:36.46#ibcon#about to read 4, iclass 30, count 0 2006.285.13:52:36.46#ibcon#read 4, iclass 30, count 0 2006.285.13:52:36.46#ibcon#about to read 5, iclass 30, count 0 2006.285.13:52:36.46#ibcon#read 5, iclass 30, count 0 2006.285.13:52:36.46#ibcon#about to read 6, iclass 30, count 0 2006.285.13:52:36.46#ibcon#read 6, iclass 30, count 0 2006.285.13:52:36.46#ibcon#end of sib2, iclass 30, count 0 2006.285.13:52:36.46#ibcon#*mode == 0, iclass 30, count 0 2006.285.13:52:36.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.13:52:36.46#ibcon#[27=USB\r\n] 2006.285.13:52:36.46#ibcon#*before write, iclass 30, count 0 2006.285.13:52:36.46#ibcon#enter sib2, iclass 30, count 0 2006.285.13:52:36.46#ibcon#flushed, iclass 30, count 0 2006.285.13:52:36.46#ibcon#about to write, iclass 30, count 0 2006.285.13:52:36.46#ibcon#wrote, iclass 30, count 0 2006.285.13:52:36.46#ibcon#about to read 3, iclass 30, count 0 2006.285.13:52:36.49#ibcon#read 3, iclass 30, count 0 2006.285.13:52:36.49#ibcon#about to read 4, iclass 30, count 0 2006.285.13:52:36.49#ibcon#read 4, iclass 30, count 0 2006.285.13:52:36.49#ibcon#about to read 5, iclass 30, count 0 2006.285.13:52:36.49#ibcon#read 5, iclass 30, count 0 2006.285.13:52:36.49#ibcon#about to read 6, iclass 30, count 0 2006.285.13:52:36.49#ibcon#read 6, iclass 30, count 0 2006.285.13:52:36.49#ibcon#end of sib2, iclass 30, count 0 2006.285.13:52:36.49#ibcon#*after write, iclass 30, count 0 2006.285.13:52:36.49#ibcon#*before return 0, iclass 30, count 0 2006.285.13:52:36.49#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:52:36.49#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.13:52:36.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.13:52:36.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.13:52:36.49$vck44/vblo=2,634.99 2006.285.13:52:36.49#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.13:52:36.49#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.13:52:36.49#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:36.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:52:36.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:52:36.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:52:36.49#ibcon#enter wrdev, iclass 32, count 0 2006.285.13:52:36.49#ibcon#first serial, iclass 32, count 0 2006.285.13:52:36.49#ibcon#enter sib2, iclass 32, count 0 2006.285.13:52:36.49#ibcon#flushed, iclass 32, count 0 2006.285.13:52:36.49#ibcon#about to write, iclass 32, count 0 2006.285.13:52:36.49#ibcon#wrote, iclass 32, count 0 2006.285.13:52:36.49#ibcon#about to read 3, iclass 32, count 0 2006.285.13:52:36.51#ibcon#read 3, iclass 32, count 0 2006.285.13:52:36.64#ibcon#about to read 4, iclass 32, count 0 2006.285.13:52:36.64#ibcon#read 4, iclass 32, count 0 2006.285.13:52:36.64#ibcon#about to read 5, iclass 32, count 0 2006.285.13:52:36.64#ibcon#read 5, iclass 32, count 0 2006.285.13:52:36.64#ibcon#about to read 6, iclass 32, count 0 2006.285.13:52:36.64#ibcon#read 6, iclass 32, count 0 2006.285.13:52:36.64#ibcon#end of sib2, iclass 32, count 0 2006.285.13:52:36.64#ibcon#*mode == 0, iclass 32, count 0 2006.285.13:52:36.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.13:52:36.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:52:36.64#ibcon#*before write, iclass 32, count 0 2006.285.13:52:36.64#ibcon#enter sib2, iclass 32, count 0 2006.285.13:52:36.64#ibcon#flushed, iclass 32, count 0 2006.285.13:52:36.64#ibcon#about to write, iclass 32, count 0 2006.285.13:52:36.64#ibcon#wrote, iclass 32, count 0 2006.285.13:52:36.64#ibcon#about to read 3, iclass 32, count 0 2006.285.13:52:36.68#ibcon#read 3, iclass 32, count 0 2006.285.13:52:36.68#ibcon#about to read 4, iclass 32, count 0 2006.285.13:52:36.68#ibcon#read 4, iclass 32, count 0 2006.285.13:52:36.68#ibcon#about to read 5, iclass 32, count 0 2006.285.13:52:36.68#ibcon#read 5, iclass 32, count 0 2006.285.13:52:36.68#ibcon#about to read 6, iclass 32, count 0 2006.285.13:52:36.68#ibcon#read 6, iclass 32, count 0 2006.285.13:52:36.68#ibcon#end of sib2, iclass 32, count 0 2006.285.13:52:36.68#ibcon#*after write, iclass 32, count 0 2006.285.13:52:36.68#ibcon#*before return 0, iclass 32, count 0 2006.285.13:52:36.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:52:36.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.13:52:36.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.13:52:36.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.13:52:36.68$vck44/vb=2,5 2006.285.13:52:36.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.13:52:36.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.13:52:36.68#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:36.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:52:36.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:52:36.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:52:36.68#ibcon#enter wrdev, iclass 35, count 2 2006.285.13:52:36.68#ibcon#first serial, iclass 35, count 2 2006.285.13:52:36.68#ibcon#enter sib2, iclass 35, count 2 2006.285.13:52:36.68#ibcon#flushed, iclass 35, count 2 2006.285.13:52:36.68#ibcon#about to write, iclass 35, count 2 2006.285.13:52:36.68#ibcon#wrote, iclass 35, count 2 2006.285.13:52:36.68#ibcon#about to read 3, iclass 35, count 2 2006.285.13:52:36.68#abcon#<5=/04 1.5 3.2 19.05 971015.3\r\n> 2006.285.13:52:36.70#ibcon#read 3, iclass 35, count 2 2006.285.13:52:36.70#ibcon#about to read 4, iclass 35, count 2 2006.285.13:52:36.70#ibcon#read 4, iclass 35, count 2 2006.285.13:52:36.70#ibcon#about to read 5, iclass 35, count 2 2006.285.13:52:36.70#ibcon#read 5, iclass 35, count 2 2006.285.13:52:36.70#ibcon#about to read 6, iclass 35, count 2 2006.285.13:52:36.70#ibcon#read 6, iclass 35, count 2 2006.285.13:52:36.70#ibcon#end of sib2, iclass 35, count 2 2006.285.13:52:36.70#ibcon#*mode == 0, iclass 35, count 2 2006.285.13:52:36.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.13:52:36.70#ibcon#[27=AT02-05\r\n] 2006.285.13:52:36.70#ibcon#*before write, iclass 35, count 2 2006.285.13:52:36.70#ibcon#enter sib2, iclass 35, count 2 2006.285.13:52:36.70#ibcon#flushed, iclass 35, count 2 2006.285.13:52:36.70#ibcon#about to write, iclass 35, count 2 2006.285.13:52:36.70#ibcon#wrote, iclass 35, count 2 2006.285.13:52:36.70#ibcon#about to read 3, iclass 35, count 2 2006.285.13:52:36.70#abcon#{5=INTERFACE CLEAR} 2006.285.13:52:36.73#ibcon#read 3, iclass 35, count 2 2006.285.13:52:36.73#ibcon#about to read 4, iclass 35, count 2 2006.285.13:52:36.73#ibcon#read 4, iclass 35, count 2 2006.285.13:52:36.73#ibcon#about to read 5, iclass 35, count 2 2006.285.13:52:36.73#ibcon#read 5, iclass 35, count 2 2006.285.13:52:36.73#ibcon#about to read 6, iclass 35, count 2 2006.285.13:52:36.73#ibcon#read 6, iclass 35, count 2 2006.285.13:52:36.73#ibcon#end of sib2, iclass 35, count 2 2006.285.13:52:36.73#ibcon#*after write, iclass 35, count 2 2006.285.13:52:36.73#ibcon#*before return 0, iclass 35, count 2 2006.285.13:52:36.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:52:36.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.13:52:36.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.13:52:36.73#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:36.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:52:36.76#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:52:36.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:52:36.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:52:36.85#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:52:36.85#ibcon#first serial, iclass 35, count 0 2006.285.13:52:36.85#ibcon#enter sib2, iclass 35, count 0 2006.285.13:52:36.85#ibcon#flushed, iclass 35, count 0 2006.285.13:52:36.85#ibcon#about to write, iclass 35, count 0 2006.285.13:52:36.85#ibcon#wrote, iclass 35, count 0 2006.285.13:52:36.85#ibcon#about to read 3, iclass 35, count 0 2006.285.13:52:36.87#ibcon#read 3, iclass 35, count 0 2006.285.13:52:36.87#ibcon#about to read 4, iclass 35, count 0 2006.285.13:52:36.87#ibcon#read 4, iclass 35, count 0 2006.285.13:52:36.87#ibcon#about to read 5, iclass 35, count 0 2006.285.13:52:36.87#ibcon#read 5, iclass 35, count 0 2006.285.13:52:36.87#ibcon#about to read 6, iclass 35, count 0 2006.285.13:52:36.87#ibcon#read 6, iclass 35, count 0 2006.285.13:52:36.87#ibcon#end of sib2, iclass 35, count 0 2006.285.13:52:36.87#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:52:36.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:52:36.87#ibcon#[27=USB\r\n] 2006.285.13:52:36.87#ibcon#*before write, iclass 35, count 0 2006.285.13:52:36.87#ibcon#enter sib2, iclass 35, count 0 2006.285.13:52:36.87#ibcon#flushed, iclass 35, count 0 2006.285.13:52:36.87#ibcon#about to write, iclass 35, count 0 2006.285.13:52:36.87#ibcon#wrote, iclass 35, count 0 2006.285.13:52:36.87#ibcon#about to read 3, iclass 35, count 0 2006.285.13:52:36.90#ibcon#read 3, iclass 35, count 0 2006.285.13:52:36.90#ibcon#about to read 4, iclass 35, count 0 2006.285.13:52:36.90#ibcon#read 4, iclass 35, count 0 2006.285.13:52:36.90#ibcon#about to read 5, iclass 35, count 0 2006.285.13:52:36.90#ibcon#read 5, iclass 35, count 0 2006.285.13:52:36.90#ibcon#about to read 6, iclass 35, count 0 2006.285.13:52:36.90#ibcon#read 6, iclass 35, count 0 2006.285.13:52:36.90#ibcon#end of sib2, iclass 35, count 0 2006.285.13:52:36.90#ibcon#*after write, iclass 35, count 0 2006.285.13:52:36.90#ibcon#*before return 0, iclass 35, count 0 2006.285.13:52:36.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:52:36.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.13:52:36.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:52:36.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:52:36.90$vck44/vblo=3,649.99 2006.285.13:52:36.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.13:52:36.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.13:52:36.90#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:36.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:52:36.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:52:36.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:52:36.90#ibcon#enter wrdev, iclass 40, count 0 2006.285.13:52:36.90#ibcon#first serial, iclass 40, count 0 2006.285.13:52:36.90#ibcon#enter sib2, iclass 40, count 0 2006.285.13:52:36.90#ibcon#flushed, iclass 40, count 0 2006.285.13:52:36.90#ibcon#about to write, iclass 40, count 0 2006.285.13:52:36.90#ibcon#wrote, iclass 40, count 0 2006.285.13:52:36.90#ibcon#about to read 3, iclass 40, count 0 2006.285.13:52:36.92#ibcon#read 3, iclass 40, count 0 2006.285.13:52:36.92#ibcon#about to read 4, iclass 40, count 0 2006.285.13:52:36.92#ibcon#read 4, iclass 40, count 0 2006.285.13:52:36.92#ibcon#about to read 5, iclass 40, count 0 2006.285.13:52:36.92#ibcon#read 5, iclass 40, count 0 2006.285.13:52:36.92#ibcon#about to read 6, iclass 40, count 0 2006.285.13:52:36.92#ibcon#read 6, iclass 40, count 0 2006.285.13:52:36.92#ibcon#end of sib2, iclass 40, count 0 2006.285.13:52:36.92#ibcon#*mode == 0, iclass 40, count 0 2006.285.13:52:36.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.13:52:36.92#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:52:36.92#ibcon#*before write, iclass 40, count 0 2006.285.13:52:36.92#ibcon#enter sib2, iclass 40, count 0 2006.285.13:52:36.92#ibcon#flushed, iclass 40, count 0 2006.285.13:52:36.92#ibcon#about to write, iclass 40, count 0 2006.285.13:52:36.92#ibcon#wrote, iclass 40, count 0 2006.285.13:52:36.92#ibcon#about to read 3, iclass 40, count 0 2006.285.13:52:36.96#ibcon#read 3, iclass 40, count 0 2006.285.13:52:36.96#ibcon#about to read 4, iclass 40, count 0 2006.285.13:52:36.96#ibcon#read 4, iclass 40, count 0 2006.285.13:52:36.96#ibcon#about to read 5, iclass 40, count 0 2006.285.13:52:36.96#ibcon#read 5, iclass 40, count 0 2006.285.13:52:36.96#ibcon#about to read 6, iclass 40, count 0 2006.285.13:52:36.96#ibcon#read 6, iclass 40, count 0 2006.285.13:52:36.96#ibcon#end of sib2, iclass 40, count 0 2006.285.13:52:36.96#ibcon#*after write, iclass 40, count 0 2006.285.13:52:36.96#ibcon#*before return 0, iclass 40, count 0 2006.285.13:52:36.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:52:36.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.13:52:36.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.13:52:36.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.13:52:36.96$vck44/vb=3,4 2006.285.13:52:36.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.13:52:36.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.13:52:36.96#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:36.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:52:37.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:52:37.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:52:37.02#ibcon#enter wrdev, iclass 4, count 2 2006.285.13:52:37.02#ibcon#first serial, iclass 4, count 2 2006.285.13:52:37.02#ibcon#enter sib2, iclass 4, count 2 2006.285.13:52:37.02#ibcon#flushed, iclass 4, count 2 2006.285.13:52:37.02#ibcon#about to write, iclass 4, count 2 2006.285.13:52:37.02#ibcon#wrote, iclass 4, count 2 2006.285.13:52:37.02#ibcon#about to read 3, iclass 4, count 2 2006.285.13:52:37.04#ibcon#read 3, iclass 4, count 2 2006.285.13:52:37.04#ibcon#about to read 4, iclass 4, count 2 2006.285.13:52:37.04#ibcon#read 4, iclass 4, count 2 2006.285.13:52:37.04#ibcon#about to read 5, iclass 4, count 2 2006.285.13:52:37.04#ibcon#read 5, iclass 4, count 2 2006.285.13:52:37.04#ibcon#about to read 6, iclass 4, count 2 2006.285.13:52:37.04#ibcon#read 6, iclass 4, count 2 2006.285.13:52:37.04#ibcon#end of sib2, iclass 4, count 2 2006.285.13:52:37.04#ibcon#*mode == 0, iclass 4, count 2 2006.285.13:52:37.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.13:52:37.04#ibcon#[27=AT03-04\r\n] 2006.285.13:52:37.04#ibcon#*before write, iclass 4, count 2 2006.285.13:52:37.04#ibcon#enter sib2, iclass 4, count 2 2006.285.13:52:37.04#ibcon#flushed, iclass 4, count 2 2006.285.13:52:37.04#ibcon#about to write, iclass 4, count 2 2006.285.13:52:37.04#ibcon#wrote, iclass 4, count 2 2006.285.13:52:37.04#ibcon#about to read 3, iclass 4, count 2 2006.285.13:52:37.07#ibcon#read 3, iclass 4, count 2 2006.285.13:52:37.07#ibcon#about to read 4, iclass 4, count 2 2006.285.13:52:37.07#ibcon#read 4, iclass 4, count 2 2006.285.13:52:37.07#ibcon#about to read 5, iclass 4, count 2 2006.285.13:52:37.07#ibcon#read 5, iclass 4, count 2 2006.285.13:52:37.07#ibcon#about to read 6, iclass 4, count 2 2006.285.13:52:37.07#ibcon#read 6, iclass 4, count 2 2006.285.13:52:37.07#ibcon#end of sib2, iclass 4, count 2 2006.285.13:52:37.07#ibcon#*after write, iclass 4, count 2 2006.285.13:52:37.07#ibcon#*before return 0, iclass 4, count 2 2006.285.13:52:37.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:52:37.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.13:52:37.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.13:52:37.07#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:37.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:52:37.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:52:37.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:52:37.19#ibcon#enter wrdev, iclass 4, count 0 2006.285.13:52:37.19#ibcon#first serial, iclass 4, count 0 2006.285.13:52:37.19#ibcon#enter sib2, iclass 4, count 0 2006.285.13:52:37.19#ibcon#flushed, iclass 4, count 0 2006.285.13:52:37.19#ibcon#about to write, iclass 4, count 0 2006.285.13:52:37.19#ibcon#wrote, iclass 4, count 0 2006.285.13:52:37.19#ibcon#about to read 3, iclass 4, count 0 2006.285.13:52:37.21#ibcon#read 3, iclass 4, count 0 2006.285.13:52:37.21#ibcon#about to read 4, iclass 4, count 0 2006.285.13:52:37.21#ibcon#read 4, iclass 4, count 0 2006.285.13:52:37.21#ibcon#about to read 5, iclass 4, count 0 2006.285.13:52:37.21#ibcon#read 5, iclass 4, count 0 2006.285.13:52:37.21#ibcon#about to read 6, iclass 4, count 0 2006.285.13:52:37.21#ibcon#read 6, iclass 4, count 0 2006.285.13:52:37.21#ibcon#end of sib2, iclass 4, count 0 2006.285.13:52:37.21#ibcon#*mode == 0, iclass 4, count 0 2006.285.13:52:37.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.13:52:37.21#ibcon#[27=USB\r\n] 2006.285.13:52:37.21#ibcon#*before write, iclass 4, count 0 2006.285.13:52:37.21#ibcon#enter sib2, iclass 4, count 0 2006.285.13:52:37.21#ibcon#flushed, iclass 4, count 0 2006.285.13:52:37.21#ibcon#about to write, iclass 4, count 0 2006.285.13:52:37.21#ibcon#wrote, iclass 4, count 0 2006.285.13:52:37.21#ibcon#about to read 3, iclass 4, count 0 2006.285.13:52:37.24#ibcon#read 3, iclass 4, count 0 2006.285.13:52:37.24#ibcon#about to read 4, iclass 4, count 0 2006.285.13:52:37.24#ibcon#read 4, iclass 4, count 0 2006.285.13:52:37.24#ibcon#about to read 5, iclass 4, count 0 2006.285.13:52:37.24#ibcon#read 5, iclass 4, count 0 2006.285.13:52:37.24#ibcon#about to read 6, iclass 4, count 0 2006.285.13:52:37.24#ibcon#read 6, iclass 4, count 0 2006.285.13:52:37.24#ibcon#end of sib2, iclass 4, count 0 2006.285.13:52:37.24#ibcon#*after write, iclass 4, count 0 2006.285.13:52:37.24#ibcon#*before return 0, iclass 4, count 0 2006.285.13:52:37.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:52:37.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.13:52:37.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.13:52:37.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.13:52:37.24$vck44/vblo=4,679.99 2006.285.13:52:37.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.13:52:37.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.13:52:37.24#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:37.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:52:37.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:52:37.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:52:37.24#ibcon#enter wrdev, iclass 6, count 0 2006.285.13:52:37.24#ibcon#first serial, iclass 6, count 0 2006.285.13:52:37.24#ibcon#enter sib2, iclass 6, count 0 2006.285.13:52:37.24#ibcon#flushed, iclass 6, count 0 2006.285.13:52:37.24#ibcon#about to write, iclass 6, count 0 2006.285.13:52:37.24#ibcon#wrote, iclass 6, count 0 2006.285.13:52:37.24#ibcon#about to read 3, iclass 6, count 0 2006.285.13:52:37.26#ibcon#read 3, iclass 6, count 0 2006.285.13:52:37.26#ibcon#about to read 4, iclass 6, count 0 2006.285.13:52:37.26#ibcon#read 4, iclass 6, count 0 2006.285.13:52:37.26#ibcon#about to read 5, iclass 6, count 0 2006.285.13:52:37.26#ibcon#read 5, iclass 6, count 0 2006.285.13:52:37.26#ibcon#about to read 6, iclass 6, count 0 2006.285.13:52:37.26#ibcon#read 6, iclass 6, count 0 2006.285.13:52:37.26#ibcon#end of sib2, iclass 6, count 0 2006.285.13:52:37.26#ibcon#*mode == 0, iclass 6, count 0 2006.285.13:52:37.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.13:52:37.26#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:52:37.26#ibcon#*before write, iclass 6, count 0 2006.285.13:52:37.26#ibcon#enter sib2, iclass 6, count 0 2006.285.13:52:37.26#ibcon#flushed, iclass 6, count 0 2006.285.13:52:37.26#ibcon#about to write, iclass 6, count 0 2006.285.13:52:37.26#ibcon#wrote, iclass 6, count 0 2006.285.13:52:37.26#ibcon#about to read 3, iclass 6, count 0 2006.285.13:52:37.30#ibcon#read 3, iclass 6, count 0 2006.285.13:52:37.30#ibcon#about to read 4, iclass 6, count 0 2006.285.13:52:37.30#ibcon#read 4, iclass 6, count 0 2006.285.13:52:37.30#ibcon#about to read 5, iclass 6, count 0 2006.285.13:52:37.30#ibcon#read 5, iclass 6, count 0 2006.285.13:52:37.30#ibcon#about to read 6, iclass 6, count 0 2006.285.13:52:37.30#ibcon#read 6, iclass 6, count 0 2006.285.13:52:37.30#ibcon#end of sib2, iclass 6, count 0 2006.285.13:52:37.30#ibcon#*after write, iclass 6, count 0 2006.285.13:52:37.30#ibcon#*before return 0, iclass 6, count 0 2006.285.13:52:37.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:52:37.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.13:52:37.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.13:52:37.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.13:52:37.30$vck44/vb=4,5 2006.285.13:52:37.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.13:52:37.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.13:52:37.30#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:37.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:52:37.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:52:37.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:52:37.36#ibcon#enter wrdev, iclass 10, count 2 2006.285.13:52:37.36#ibcon#first serial, iclass 10, count 2 2006.285.13:52:37.36#ibcon#enter sib2, iclass 10, count 2 2006.285.13:52:37.36#ibcon#flushed, iclass 10, count 2 2006.285.13:52:37.36#ibcon#about to write, iclass 10, count 2 2006.285.13:52:37.36#ibcon#wrote, iclass 10, count 2 2006.285.13:52:37.36#ibcon#about to read 3, iclass 10, count 2 2006.285.13:52:37.38#ibcon#read 3, iclass 10, count 2 2006.285.13:52:37.38#ibcon#about to read 4, iclass 10, count 2 2006.285.13:52:37.38#ibcon#read 4, iclass 10, count 2 2006.285.13:52:37.38#ibcon#about to read 5, iclass 10, count 2 2006.285.13:52:37.38#ibcon#read 5, iclass 10, count 2 2006.285.13:52:37.38#ibcon#about to read 6, iclass 10, count 2 2006.285.13:52:37.38#ibcon#read 6, iclass 10, count 2 2006.285.13:52:37.38#ibcon#end of sib2, iclass 10, count 2 2006.285.13:52:37.38#ibcon#*mode == 0, iclass 10, count 2 2006.285.13:52:37.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.13:52:37.38#ibcon#[27=AT04-05\r\n] 2006.285.13:52:37.38#ibcon#*before write, iclass 10, count 2 2006.285.13:52:37.38#ibcon#enter sib2, iclass 10, count 2 2006.285.13:52:37.38#ibcon#flushed, iclass 10, count 2 2006.285.13:52:37.38#ibcon#about to write, iclass 10, count 2 2006.285.13:52:37.38#ibcon#wrote, iclass 10, count 2 2006.285.13:52:37.38#ibcon#about to read 3, iclass 10, count 2 2006.285.13:52:37.41#ibcon#read 3, iclass 10, count 2 2006.285.13:52:37.41#ibcon#about to read 4, iclass 10, count 2 2006.285.13:52:37.41#ibcon#read 4, iclass 10, count 2 2006.285.13:52:37.41#ibcon#about to read 5, iclass 10, count 2 2006.285.13:52:37.41#ibcon#read 5, iclass 10, count 2 2006.285.13:52:37.41#ibcon#about to read 6, iclass 10, count 2 2006.285.13:52:37.41#ibcon#read 6, iclass 10, count 2 2006.285.13:52:37.41#ibcon#end of sib2, iclass 10, count 2 2006.285.13:52:37.41#ibcon#*after write, iclass 10, count 2 2006.285.13:52:37.41#ibcon#*before return 0, iclass 10, count 2 2006.285.13:52:37.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:52:37.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.13:52:37.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.13:52:37.41#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:37.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:52:37.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:52:37.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:52:37.53#ibcon#enter wrdev, iclass 10, count 0 2006.285.13:52:37.53#ibcon#first serial, iclass 10, count 0 2006.285.13:52:37.53#ibcon#enter sib2, iclass 10, count 0 2006.285.13:52:37.53#ibcon#flushed, iclass 10, count 0 2006.285.13:52:37.53#ibcon#about to write, iclass 10, count 0 2006.285.13:52:37.53#ibcon#wrote, iclass 10, count 0 2006.285.13:52:37.53#ibcon#about to read 3, iclass 10, count 0 2006.285.13:52:37.55#ibcon#read 3, iclass 10, count 0 2006.285.13:52:37.55#ibcon#about to read 4, iclass 10, count 0 2006.285.13:52:37.55#ibcon#read 4, iclass 10, count 0 2006.285.13:52:37.55#ibcon#about to read 5, iclass 10, count 0 2006.285.13:52:37.55#ibcon#read 5, iclass 10, count 0 2006.285.13:52:37.55#ibcon#about to read 6, iclass 10, count 0 2006.285.13:52:37.55#ibcon#read 6, iclass 10, count 0 2006.285.13:52:37.55#ibcon#end of sib2, iclass 10, count 0 2006.285.13:52:37.55#ibcon#*mode == 0, iclass 10, count 0 2006.285.13:52:37.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.13:52:37.55#ibcon#[27=USB\r\n] 2006.285.13:52:37.55#ibcon#*before write, iclass 10, count 0 2006.285.13:52:37.55#ibcon#enter sib2, iclass 10, count 0 2006.285.13:52:37.55#ibcon#flushed, iclass 10, count 0 2006.285.13:52:37.55#ibcon#about to write, iclass 10, count 0 2006.285.13:52:37.55#ibcon#wrote, iclass 10, count 0 2006.285.13:52:37.55#ibcon#about to read 3, iclass 10, count 0 2006.285.13:52:37.58#ibcon#read 3, iclass 10, count 0 2006.285.13:52:37.58#ibcon#about to read 4, iclass 10, count 0 2006.285.13:52:37.58#ibcon#read 4, iclass 10, count 0 2006.285.13:52:37.58#ibcon#about to read 5, iclass 10, count 0 2006.285.13:52:37.58#ibcon#read 5, iclass 10, count 0 2006.285.13:52:37.58#ibcon#about to read 6, iclass 10, count 0 2006.285.13:52:37.58#ibcon#read 6, iclass 10, count 0 2006.285.13:52:37.58#ibcon#end of sib2, iclass 10, count 0 2006.285.13:52:37.58#ibcon#*after write, iclass 10, count 0 2006.285.13:52:37.58#ibcon#*before return 0, iclass 10, count 0 2006.285.13:52:37.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:52:37.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.13:52:37.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.13:52:37.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.13:52:37.58$vck44/vblo=5,709.99 2006.285.13:52:37.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.13:52:37.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.13:52:37.58#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:37.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:52:37.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:52:37.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:52:37.58#ibcon#enter wrdev, iclass 12, count 0 2006.285.13:52:37.58#ibcon#first serial, iclass 12, count 0 2006.285.13:52:37.58#ibcon#enter sib2, iclass 12, count 0 2006.285.13:52:37.58#ibcon#flushed, iclass 12, count 0 2006.285.13:52:37.58#ibcon#about to write, iclass 12, count 0 2006.285.13:52:37.58#ibcon#wrote, iclass 12, count 0 2006.285.13:52:37.58#ibcon#about to read 3, iclass 12, count 0 2006.285.13:52:37.60#ibcon#read 3, iclass 12, count 0 2006.285.13:52:37.82#ibcon#about to read 4, iclass 12, count 0 2006.285.13:52:37.82#ibcon#read 4, iclass 12, count 0 2006.285.13:52:37.82#ibcon#about to read 5, iclass 12, count 0 2006.285.13:52:37.82#ibcon#read 5, iclass 12, count 0 2006.285.13:52:37.82#ibcon#about to read 6, iclass 12, count 0 2006.285.13:52:37.82#ibcon#read 6, iclass 12, count 0 2006.285.13:52:37.82#ibcon#end of sib2, iclass 12, count 0 2006.285.13:52:37.82#ibcon#*mode == 0, iclass 12, count 0 2006.285.13:52:37.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.13:52:37.82#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:52:37.82#ibcon#*before write, iclass 12, count 0 2006.285.13:52:37.83#ibcon#enter sib2, iclass 12, count 0 2006.285.13:52:37.83#ibcon#flushed, iclass 12, count 0 2006.285.13:52:37.83#ibcon#about to write, iclass 12, count 0 2006.285.13:52:37.83#ibcon#wrote, iclass 12, count 0 2006.285.13:52:37.83#ibcon#about to read 3, iclass 12, count 0 2006.285.13:52:37.86#ibcon#read 3, iclass 12, count 0 2006.285.13:52:37.86#ibcon#about to read 4, iclass 12, count 0 2006.285.13:52:37.86#ibcon#read 4, iclass 12, count 0 2006.285.13:52:37.86#ibcon#about to read 5, iclass 12, count 0 2006.285.13:52:37.86#ibcon#read 5, iclass 12, count 0 2006.285.13:52:37.86#ibcon#about to read 6, iclass 12, count 0 2006.285.13:52:37.86#ibcon#read 6, iclass 12, count 0 2006.285.13:52:37.86#ibcon#end of sib2, iclass 12, count 0 2006.285.13:52:37.86#ibcon#*after write, iclass 12, count 0 2006.285.13:52:37.86#ibcon#*before return 0, iclass 12, count 0 2006.285.13:52:37.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:52:37.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.13:52:37.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.13:52:37.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.13:52:37.86$vck44/vb=5,4 2006.285.13:52:37.86#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.13:52:37.86#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.13:52:37.86#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:37.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:52:37.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:52:37.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:52:37.86#ibcon#enter wrdev, iclass 14, count 2 2006.285.13:52:37.86#ibcon#first serial, iclass 14, count 2 2006.285.13:52:37.86#ibcon#enter sib2, iclass 14, count 2 2006.285.13:52:37.86#ibcon#flushed, iclass 14, count 2 2006.285.13:52:37.86#ibcon#about to write, iclass 14, count 2 2006.285.13:52:37.86#ibcon#wrote, iclass 14, count 2 2006.285.13:52:37.86#ibcon#about to read 3, iclass 14, count 2 2006.285.13:52:37.88#ibcon#read 3, iclass 14, count 2 2006.285.13:52:37.88#ibcon#about to read 4, iclass 14, count 2 2006.285.13:52:37.88#ibcon#read 4, iclass 14, count 2 2006.285.13:52:37.88#ibcon#about to read 5, iclass 14, count 2 2006.285.13:52:37.88#ibcon#read 5, iclass 14, count 2 2006.285.13:52:37.88#ibcon#about to read 6, iclass 14, count 2 2006.285.13:52:37.88#ibcon#read 6, iclass 14, count 2 2006.285.13:52:37.88#ibcon#end of sib2, iclass 14, count 2 2006.285.13:52:37.88#ibcon#*mode == 0, iclass 14, count 2 2006.285.13:52:37.88#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.13:52:37.88#ibcon#[27=AT05-04\r\n] 2006.285.13:52:37.88#ibcon#*before write, iclass 14, count 2 2006.285.13:52:37.88#ibcon#enter sib2, iclass 14, count 2 2006.285.13:52:37.88#ibcon#flushed, iclass 14, count 2 2006.285.13:52:37.88#ibcon#about to write, iclass 14, count 2 2006.285.13:52:37.88#ibcon#wrote, iclass 14, count 2 2006.285.13:52:37.88#ibcon#about to read 3, iclass 14, count 2 2006.285.13:52:37.91#ibcon#read 3, iclass 14, count 2 2006.285.13:52:37.91#ibcon#about to read 4, iclass 14, count 2 2006.285.13:52:37.91#ibcon#read 4, iclass 14, count 2 2006.285.13:52:37.91#ibcon#about to read 5, iclass 14, count 2 2006.285.13:52:37.91#ibcon#read 5, iclass 14, count 2 2006.285.13:52:37.91#ibcon#about to read 6, iclass 14, count 2 2006.285.13:52:37.91#ibcon#read 6, iclass 14, count 2 2006.285.13:52:37.91#ibcon#end of sib2, iclass 14, count 2 2006.285.13:52:37.91#ibcon#*after write, iclass 14, count 2 2006.285.13:52:37.91#ibcon#*before return 0, iclass 14, count 2 2006.285.13:52:37.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:52:37.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.13:52:37.91#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.13:52:37.91#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:37.91#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:52:38.03#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:52:38.03#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:52:38.03#ibcon#enter wrdev, iclass 14, count 0 2006.285.13:52:38.03#ibcon#first serial, iclass 14, count 0 2006.285.13:52:38.03#ibcon#enter sib2, iclass 14, count 0 2006.285.13:52:38.03#ibcon#flushed, iclass 14, count 0 2006.285.13:52:38.03#ibcon#about to write, iclass 14, count 0 2006.285.13:52:38.03#ibcon#wrote, iclass 14, count 0 2006.285.13:52:38.03#ibcon#about to read 3, iclass 14, count 0 2006.285.13:52:38.05#ibcon#read 3, iclass 14, count 0 2006.285.13:52:38.05#ibcon#about to read 4, iclass 14, count 0 2006.285.13:52:38.05#ibcon#read 4, iclass 14, count 0 2006.285.13:52:38.05#ibcon#about to read 5, iclass 14, count 0 2006.285.13:52:38.05#ibcon#read 5, iclass 14, count 0 2006.285.13:52:38.05#ibcon#about to read 6, iclass 14, count 0 2006.285.13:52:38.05#ibcon#read 6, iclass 14, count 0 2006.285.13:52:38.05#ibcon#end of sib2, iclass 14, count 0 2006.285.13:52:38.05#ibcon#*mode == 0, iclass 14, count 0 2006.285.13:52:38.05#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.13:52:38.05#ibcon#[27=USB\r\n] 2006.285.13:52:38.05#ibcon#*before write, iclass 14, count 0 2006.285.13:52:38.05#ibcon#enter sib2, iclass 14, count 0 2006.285.13:52:38.05#ibcon#flushed, iclass 14, count 0 2006.285.13:52:38.05#ibcon#about to write, iclass 14, count 0 2006.285.13:52:38.05#ibcon#wrote, iclass 14, count 0 2006.285.13:52:38.05#ibcon#about to read 3, iclass 14, count 0 2006.285.13:52:38.08#ibcon#read 3, iclass 14, count 0 2006.285.13:52:38.08#ibcon#about to read 4, iclass 14, count 0 2006.285.13:52:38.08#ibcon#read 4, iclass 14, count 0 2006.285.13:52:38.08#ibcon#about to read 5, iclass 14, count 0 2006.285.13:52:38.08#ibcon#read 5, iclass 14, count 0 2006.285.13:52:38.08#ibcon#about to read 6, iclass 14, count 0 2006.285.13:52:38.08#ibcon#read 6, iclass 14, count 0 2006.285.13:52:38.08#ibcon#end of sib2, iclass 14, count 0 2006.285.13:52:38.08#ibcon#*after write, iclass 14, count 0 2006.285.13:52:38.08#ibcon#*before return 0, iclass 14, count 0 2006.285.13:52:38.08#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:52:38.08#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.13:52:38.08#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.13:52:38.08#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.13:52:38.08$vck44/vblo=6,719.99 2006.285.13:52:38.08#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.13:52:38.08#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.13:52:38.08#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:38.08#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:52:38.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:52:38.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:52:38.08#ibcon#enter wrdev, iclass 16, count 0 2006.285.13:52:38.08#ibcon#first serial, iclass 16, count 0 2006.285.13:52:38.08#ibcon#enter sib2, iclass 16, count 0 2006.285.13:52:38.08#ibcon#flushed, iclass 16, count 0 2006.285.13:52:38.08#ibcon#about to write, iclass 16, count 0 2006.285.13:52:38.08#ibcon#wrote, iclass 16, count 0 2006.285.13:52:38.08#ibcon#about to read 3, iclass 16, count 0 2006.285.13:52:38.10#ibcon#read 3, iclass 16, count 0 2006.285.13:52:38.10#ibcon#about to read 4, iclass 16, count 0 2006.285.13:52:38.10#ibcon#read 4, iclass 16, count 0 2006.285.13:52:38.10#ibcon#about to read 5, iclass 16, count 0 2006.285.13:52:38.10#ibcon#read 5, iclass 16, count 0 2006.285.13:52:38.10#ibcon#about to read 6, iclass 16, count 0 2006.285.13:52:38.10#ibcon#read 6, iclass 16, count 0 2006.285.13:52:38.10#ibcon#end of sib2, iclass 16, count 0 2006.285.13:52:38.10#ibcon#*mode == 0, iclass 16, count 0 2006.285.13:52:38.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.13:52:38.10#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:52:38.10#ibcon#*before write, iclass 16, count 0 2006.285.13:52:38.10#ibcon#enter sib2, iclass 16, count 0 2006.285.13:52:38.10#ibcon#flushed, iclass 16, count 0 2006.285.13:52:38.10#ibcon#about to write, iclass 16, count 0 2006.285.13:52:38.10#ibcon#wrote, iclass 16, count 0 2006.285.13:52:38.10#ibcon#about to read 3, iclass 16, count 0 2006.285.13:52:38.14#ibcon#read 3, iclass 16, count 0 2006.285.13:52:38.14#ibcon#about to read 4, iclass 16, count 0 2006.285.13:52:38.14#ibcon#read 4, iclass 16, count 0 2006.285.13:52:38.14#ibcon#about to read 5, iclass 16, count 0 2006.285.13:52:38.14#ibcon#read 5, iclass 16, count 0 2006.285.13:52:38.14#ibcon#about to read 6, iclass 16, count 0 2006.285.13:52:38.14#ibcon#read 6, iclass 16, count 0 2006.285.13:52:38.14#ibcon#end of sib2, iclass 16, count 0 2006.285.13:52:38.14#ibcon#*after write, iclass 16, count 0 2006.285.13:52:38.14#ibcon#*before return 0, iclass 16, count 0 2006.285.13:52:38.14#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:52:38.14#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.13:52:38.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.13:52:38.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.13:52:38.14$vck44/vb=6,3 2006.285.13:52:38.14#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.13:52:38.14#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.13:52:38.14#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:38.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:52:38.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:52:38.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:52:38.20#ibcon#enter wrdev, iclass 18, count 2 2006.285.13:52:38.20#ibcon#first serial, iclass 18, count 2 2006.285.13:52:38.20#ibcon#enter sib2, iclass 18, count 2 2006.285.13:52:38.20#ibcon#flushed, iclass 18, count 2 2006.285.13:52:38.20#ibcon#about to write, iclass 18, count 2 2006.285.13:52:38.20#ibcon#wrote, iclass 18, count 2 2006.285.13:52:38.20#ibcon#about to read 3, iclass 18, count 2 2006.285.13:52:38.22#ibcon#read 3, iclass 18, count 2 2006.285.13:52:38.22#ibcon#about to read 4, iclass 18, count 2 2006.285.13:52:38.22#ibcon#read 4, iclass 18, count 2 2006.285.13:52:38.22#ibcon#about to read 5, iclass 18, count 2 2006.285.13:52:38.22#ibcon#read 5, iclass 18, count 2 2006.285.13:52:38.22#ibcon#about to read 6, iclass 18, count 2 2006.285.13:52:38.22#ibcon#read 6, iclass 18, count 2 2006.285.13:52:38.22#ibcon#end of sib2, iclass 18, count 2 2006.285.13:52:38.22#ibcon#*mode == 0, iclass 18, count 2 2006.285.13:52:38.22#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.13:52:38.22#ibcon#[27=AT06-03\r\n] 2006.285.13:52:38.22#ibcon#*before write, iclass 18, count 2 2006.285.13:52:38.22#ibcon#enter sib2, iclass 18, count 2 2006.285.13:52:38.22#ibcon#flushed, iclass 18, count 2 2006.285.13:52:38.22#ibcon#about to write, iclass 18, count 2 2006.285.13:52:38.22#ibcon#wrote, iclass 18, count 2 2006.285.13:52:38.22#ibcon#about to read 3, iclass 18, count 2 2006.285.13:52:38.25#ibcon#read 3, iclass 18, count 2 2006.285.13:52:38.25#ibcon#about to read 4, iclass 18, count 2 2006.285.13:52:38.25#ibcon#read 4, iclass 18, count 2 2006.285.13:52:38.25#ibcon#about to read 5, iclass 18, count 2 2006.285.13:52:38.25#ibcon#read 5, iclass 18, count 2 2006.285.13:52:38.25#ibcon#about to read 6, iclass 18, count 2 2006.285.13:52:38.25#ibcon#read 6, iclass 18, count 2 2006.285.13:52:38.25#ibcon#end of sib2, iclass 18, count 2 2006.285.13:52:38.25#ibcon#*after write, iclass 18, count 2 2006.285.13:52:38.25#ibcon#*before return 0, iclass 18, count 2 2006.285.13:52:38.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:52:38.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.13:52:38.25#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.13:52:38.25#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:38.25#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:52:38.37#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:52:38.37#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:52:38.37#ibcon#enter wrdev, iclass 18, count 0 2006.285.13:52:38.37#ibcon#first serial, iclass 18, count 0 2006.285.13:52:38.37#ibcon#enter sib2, iclass 18, count 0 2006.285.13:52:38.37#ibcon#flushed, iclass 18, count 0 2006.285.13:52:38.37#ibcon#about to write, iclass 18, count 0 2006.285.13:52:38.37#ibcon#wrote, iclass 18, count 0 2006.285.13:52:38.37#ibcon#about to read 3, iclass 18, count 0 2006.285.13:52:38.39#ibcon#read 3, iclass 18, count 0 2006.285.13:52:38.39#ibcon#about to read 4, iclass 18, count 0 2006.285.13:52:38.39#ibcon#read 4, iclass 18, count 0 2006.285.13:52:38.39#ibcon#about to read 5, iclass 18, count 0 2006.285.13:52:38.39#ibcon#read 5, iclass 18, count 0 2006.285.13:52:38.39#ibcon#about to read 6, iclass 18, count 0 2006.285.13:52:38.39#ibcon#read 6, iclass 18, count 0 2006.285.13:52:38.39#ibcon#end of sib2, iclass 18, count 0 2006.285.13:52:38.39#ibcon#*mode == 0, iclass 18, count 0 2006.285.13:52:38.39#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.13:52:38.39#ibcon#[27=USB\r\n] 2006.285.13:52:38.39#ibcon#*before write, iclass 18, count 0 2006.285.13:52:38.39#ibcon#enter sib2, iclass 18, count 0 2006.285.13:52:38.39#ibcon#flushed, iclass 18, count 0 2006.285.13:52:38.39#ibcon#about to write, iclass 18, count 0 2006.285.13:52:38.39#ibcon#wrote, iclass 18, count 0 2006.285.13:52:38.39#ibcon#about to read 3, iclass 18, count 0 2006.285.13:52:38.42#ibcon#read 3, iclass 18, count 0 2006.285.13:52:38.42#ibcon#about to read 4, iclass 18, count 0 2006.285.13:52:38.42#ibcon#read 4, iclass 18, count 0 2006.285.13:52:38.42#ibcon#about to read 5, iclass 18, count 0 2006.285.13:52:38.42#ibcon#read 5, iclass 18, count 0 2006.285.13:52:38.42#ibcon#about to read 6, iclass 18, count 0 2006.285.13:52:38.42#ibcon#read 6, iclass 18, count 0 2006.285.13:52:38.42#ibcon#end of sib2, iclass 18, count 0 2006.285.13:52:38.42#ibcon#*after write, iclass 18, count 0 2006.285.13:52:38.42#ibcon#*before return 0, iclass 18, count 0 2006.285.13:52:38.42#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:52:38.42#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.13:52:38.42#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.13:52:38.42#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.13:52:38.42$vck44/vblo=7,734.99 2006.285.13:52:38.42#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.13:52:38.42#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.13:52:38.42#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:38.42#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:52:38.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:52:38.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:52:38.42#ibcon#enter wrdev, iclass 20, count 0 2006.285.13:52:38.42#ibcon#first serial, iclass 20, count 0 2006.285.13:52:38.42#ibcon#enter sib2, iclass 20, count 0 2006.285.13:52:38.42#ibcon#flushed, iclass 20, count 0 2006.285.13:52:38.42#ibcon#about to write, iclass 20, count 0 2006.285.13:52:38.42#ibcon#wrote, iclass 20, count 0 2006.285.13:52:38.42#ibcon#about to read 3, iclass 20, count 0 2006.285.13:52:38.44#ibcon#read 3, iclass 20, count 0 2006.285.13:52:38.44#ibcon#about to read 4, iclass 20, count 0 2006.285.13:52:38.44#ibcon#read 4, iclass 20, count 0 2006.285.13:52:38.44#ibcon#about to read 5, iclass 20, count 0 2006.285.13:52:38.44#ibcon#read 5, iclass 20, count 0 2006.285.13:52:38.44#ibcon#about to read 6, iclass 20, count 0 2006.285.13:52:38.44#ibcon#read 6, iclass 20, count 0 2006.285.13:52:38.44#ibcon#end of sib2, iclass 20, count 0 2006.285.13:52:38.44#ibcon#*mode == 0, iclass 20, count 0 2006.285.13:52:38.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.13:52:38.44#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:52:38.44#ibcon#*before write, iclass 20, count 0 2006.285.13:52:38.44#ibcon#enter sib2, iclass 20, count 0 2006.285.13:52:38.44#ibcon#flushed, iclass 20, count 0 2006.285.13:52:38.44#ibcon#about to write, iclass 20, count 0 2006.285.13:52:38.44#ibcon#wrote, iclass 20, count 0 2006.285.13:52:38.44#ibcon#about to read 3, iclass 20, count 0 2006.285.13:52:38.48#ibcon#read 3, iclass 20, count 0 2006.285.13:52:38.48#ibcon#about to read 4, iclass 20, count 0 2006.285.13:52:38.48#ibcon#read 4, iclass 20, count 0 2006.285.13:52:38.48#ibcon#about to read 5, iclass 20, count 0 2006.285.13:52:38.48#ibcon#read 5, iclass 20, count 0 2006.285.13:52:38.48#ibcon#about to read 6, iclass 20, count 0 2006.285.13:52:38.48#ibcon#read 6, iclass 20, count 0 2006.285.13:52:38.48#ibcon#end of sib2, iclass 20, count 0 2006.285.13:52:38.48#ibcon#*after write, iclass 20, count 0 2006.285.13:52:38.48#ibcon#*before return 0, iclass 20, count 0 2006.285.13:52:38.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:52:38.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.13:52:38.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.13:52:38.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.13:52:38.48$vck44/vb=7,4 2006.285.13:52:38.48#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.13:52:38.48#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.13:52:38.48#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:38.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:52:38.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:52:38.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:52:38.54#ibcon#enter wrdev, iclass 22, count 2 2006.285.13:52:38.54#ibcon#first serial, iclass 22, count 2 2006.285.13:52:38.54#ibcon#enter sib2, iclass 22, count 2 2006.285.13:52:38.54#ibcon#flushed, iclass 22, count 2 2006.285.13:52:38.54#ibcon#about to write, iclass 22, count 2 2006.285.13:52:38.54#ibcon#wrote, iclass 22, count 2 2006.285.13:52:38.54#ibcon#about to read 3, iclass 22, count 2 2006.285.13:52:38.56#ibcon#read 3, iclass 22, count 2 2006.285.13:52:38.57#ibcon#about to read 4, iclass 22, count 2 2006.285.13:52:38.57#ibcon#read 4, iclass 22, count 2 2006.285.13:52:38.57#ibcon#about to read 5, iclass 22, count 2 2006.285.13:52:38.57#ibcon#read 5, iclass 22, count 2 2006.285.13:52:38.57#ibcon#about to read 6, iclass 22, count 2 2006.285.13:52:38.57#ibcon#read 6, iclass 22, count 2 2006.285.13:52:38.57#ibcon#end of sib2, iclass 22, count 2 2006.285.13:52:38.57#ibcon#*mode == 0, iclass 22, count 2 2006.285.13:52:38.57#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.13:52:38.57#ibcon#[27=AT07-04\r\n] 2006.285.13:52:38.57#ibcon#*before write, iclass 22, count 2 2006.285.13:52:38.57#ibcon#enter sib2, iclass 22, count 2 2006.285.13:52:38.57#ibcon#flushed, iclass 22, count 2 2006.285.13:52:38.57#ibcon#about to write, iclass 22, count 2 2006.285.13:52:38.57#ibcon#wrote, iclass 22, count 2 2006.285.13:52:38.57#ibcon#about to read 3, iclass 22, count 2 2006.285.13:52:38.60#ibcon#read 3, iclass 22, count 2 2006.285.13:52:38.60#ibcon#about to read 4, iclass 22, count 2 2006.285.13:52:38.60#ibcon#read 4, iclass 22, count 2 2006.285.13:52:38.60#ibcon#about to read 5, iclass 22, count 2 2006.285.13:52:38.60#ibcon#read 5, iclass 22, count 2 2006.285.13:52:38.60#ibcon#about to read 6, iclass 22, count 2 2006.285.13:52:38.60#ibcon#read 6, iclass 22, count 2 2006.285.13:52:38.60#ibcon#end of sib2, iclass 22, count 2 2006.285.13:52:38.60#ibcon#*after write, iclass 22, count 2 2006.285.13:52:38.60#ibcon#*before return 0, iclass 22, count 2 2006.285.13:52:38.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:52:38.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.13:52:38.60#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.13:52:38.60#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:38.60#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:52:38.72#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:52:38.72#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:52:38.72#ibcon#enter wrdev, iclass 22, count 0 2006.285.13:52:38.72#ibcon#first serial, iclass 22, count 0 2006.285.13:52:38.72#ibcon#enter sib2, iclass 22, count 0 2006.285.13:52:38.72#ibcon#flushed, iclass 22, count 0 2006.285.13:52:38.72#ibcon#about to write, iclass 22, count 0 2006.285.13:52:38.72#ibcon#wrote, iclass 22, count 0 2006.285.13:52:38.72#ibcon#about to read 3, iclass 22, count 0 2006.285.13:52:38.74#ibcon#read 3, iclass 22, count 0 2006.285.13:52:38.74#ibcon#about to read 4, iclass 22, count 0 2006.285.13:52:38.74#ibcon#read 4, iclass 22, count 0 2006.285.13:52:38.74#ibcon#about to read 5, iclass 22, count 0 2006.285.13:52:38.74#ibcon#read 5, iclass 22, count 0 2006.285.13:52:38.74#ibcon#about to read 6, iclass 22, count 0 2006.285.13:52:38.74#ibcon#read 6, iclass 22, count 0 2006.285.13:52:38.74#ibcon#end of sib2, iclass 22, count 0 2006.285.13:52:38.74#ibcon#*mode == 0, iclass 22, count 0 2006.285.13:52:38.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.13:52:38.74#ibcon#[27=USB\r\n] 2006.285.13:52:38.74#ibcon#*before write, iclass 22, count 0 2006.285.13:52:38.74#ibcon#enter sib2, iclass 22, count 0 2006.285.13:52:38.74#ibcon#flushed, iclass 22, count 0 2006.285.13:52:38.74#ibcon#about to write, iclass 22, count 0 2006.285.13:52:38.74#ibcon#wrote, iclass 22, count 0 2006.285.13:52:38.74#ibcon#about to read 3, iclass 22, count 0 2006.285.13:52:38.77#ibcon#read 3, iclass 22, count 0 2006.285.13:52:38.77#ibcon#about to read 4, iclass 22, count 0 2006.285.13:52:38.77#ibcon#read 4, iclass 22, count 0 2006.285.13:52:38.77#ibcon#about to read 5, iclass 22, count 0 2006.285.13:52:38.77#ibcon#read 5, iclass 22, count 0 2006.285.13:52:38.77#ibcon#about to read 6, iclass 22, count 0 2006.285.13:52:38.77#ibcon#read 6, iclass 22, count 0 2006.285.13:52:38.77#ibcon#end of sib2, iclass 22, count 0 2006.285.13:52:38.77#ibcon#*after write, iclass 22, count 0 2006.285.13:52:38.77#ibcon#*before return 0, iclass 22, count 0 2006.285.13:52:38.77#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:52:38.77#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.13:52:38.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.13:52:38.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.13:52:38.77$vck44/vblo=8,744.99 2006.285.13:52:38.77#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.13:52:38.77#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.13:52:38.77#ibcon#ireg 17 cls_cnt 0 2006.285.13:52:38.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:52:38.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:52:38.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:52:38.77#ibcon#enter wrdev, iclass 24, count 0 2006.285.13:52:38.77#ibcon#first serial, iclass 24, count 0 2006.285.13:52:38.77#ibcon#enter sib2, iclass 24, count 0 2006.285.13:52:38.77#ibcon#flushed, iclass 24, count 0 2006.285.13:52:38.77#ibcon#about to write, iclass 24, count 0 2006.285.13:52:38.77#ibcon#wrote, iclass 24, count 0 2006.285.13:52:38.77#ibcon#about to read 3, iclass 24, count 0 2006.285.13:52:38.79#ibcon#read 3, iclass 24, count 0 2006.285.13:52:38.79#ibcon#about to read 4, iclass 24, count 0 2006.285.13:52:38.79#ibcon#read 4, iclass 24, count 0 2006.285.13:52:38.79#ibcon#about to read 5, iclass 24, count 0 2006.285.13:52:38.79#ibcon#read 5, iclass 24, count 0 2006.285.13:52:38.79#ibcon#about to read 6, iclass 24, count 0 2006.285.13:52:38.79#ibcon#read 6, iclass 24, count 0 2006.285.13:52:38.79#ibcon#end of sib2, iclass 24, count 0 2006.285.13:52:38.79#ibcon#*mode == 0, iclass 24, count 0 2006.285.13:52:38.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.13:52:38.79#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:52:38.79#ibcon#*before write, iclass 24, count 0 2006.285.13:52:38.79#ibcon#enter sib2, iclass 24, count 0 2006.285.13:52:38.79#ibcon#flushed, iclass 24, count 0 2006.285.13:52:38.79#ibcon#about to write, iclass 24, count 0 2006.285.13:52:38.79#ibcon#wrote, iclass 24, count 0 2006.285.13:52:38.79#ibcon#about to read 3, iclass 24, count 0 2006.285.13:52:38.83#ibcon#read 3, iclass 24, count 0 2006.285.13:52:38.83#ibcon#about to read 4, iclass 24, count 0 2006.285.13:52:38.83#ibcon#read 4, iclass 24, count 0 2006.285.13:52:38.83#ibcon#about to read 5, iclass 24, count 0 2006.285.13:52:38.83#ibcon#read 5, iclass 24, count 0 2006.285.13:52:38.83#ibcon#about to read 6, iclass 24, count 0 2006.285.13:52:38.83#ibcon#read 6, iclass 24, count 0 2006.285.13:52:38.83#ibcon#end of sib2, iclass 24, count 0 2006.285.13:52:38.83#ibcon#*after write, iclass 24, count 0 2006.285.13:52:38.83#ibcon#*before return 0, iclass 24, count 0 2006.285.13:52:38.83#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:52:38.83#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.13:52:38.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.13:52:38.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.13:52:38.83$vck44/vb=8,4 2006.285.13:52:38.83#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.13:52:38.83#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.13:52:38.83#ibcon#ireg 11 cls_cnt 2 2006.285.13:52:38.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:52:38.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:52:38.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:52:38.89#ibcon#enter wrdev, iclass 26, count 2 2006.285.13:52:38.89#ibcon#first serial, iclass 26, count 2 2006.285.13:52:38.89#ibcon#enter sib2, iclass 26, count 2 2006.285.13:52:38.89#ibcon#flushed, iclass 26, count 2 2006.285.13:52:38.89#ibcon#about to write, iclass 26, count 2 2006.285.13:52:38.89#ibcon#wrote, iclass 26, count 2 2006.285.13:52:38.89#ibcon#about to read 3, iclass 26, count 2 2006.285.13:52:38.91#ibcon#read 3, iclass 26, count 2 2006.285.13:52:38.91#ibcon#about to read 4, iclass 26, count 2 2006.285.13:52:38.91#ibcon#read 4, iclass 26, count 2 2006.285.13:52:38.91#ibcon#about to read 5, iclass 26, count 2 2006.285.13:52:38.91#ibcon#read 5, iclass 26, count 2 2006.285.13:52:38.91#ibcon#about to read 6, iclass 26, count 2 2006.285.13:52:38.91#ibcon#read 6, iclass 26, count 2 2006.285.13:52:38.91#ibcon#end of sib2, iclass 26, count 2 2006.285.13:52:38.91#ibcon#*mode == 0, iclass 26, count 2 2006.285.13:52:38.91#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.13:52:38.91#ibcon#[27=AT08-04\r\n] 2006.285.13:52:38.91#ibcon#*before write, iclass 26, count 2 2006.285.13:52:38.91#ibcon#enter sib2, iclass 26, count 2 2006.285.13:52:38.91#ibcon#flushed, iclass 26, count 2 2006.285.13:52:38.91#ibcon#about to write, iclass 26, count 2 2006.285.13:52:38.91#ibcon#wrote, iclass 26, count 2 2006.285.13:52:38.91#ibcon#about to read 3, iclass 26, count 2 2006.285.13:52:38.94#ibcon#read 3, iclass 26, count 2 2006.285.13:52:38.94#ibcon#about to read 4, iclass 26, count 2 2006.285.13:52:38.94#ibcon#read 4, iclass 26, count 2 2006.285.13:52:38.94#ibcon#about to read 5, iclass 26, count 2 2006.285.13:52:38.94#ibcon#read 5, iclass 26, count 2 2006.285.13:52:38.94#ibcon#about to read 6, iclass 26, count 2 2006.285.13:52:38.94#ibcon#read 6, iclass 26, count 2 2006.285.13:52:38.94#ibcon#end of sib2, iclass 26, count 2 2006.285.13:52:38.94#ibcon#*after write, iclass 26, count 2 2006.285.13:52:38.94#ibcon#*before return 0, iclass 26, count 2 2006.285.13:52:38.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:52:38.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.13:52:38.94#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.13:52:38.94#ibcon#ireg 7 cls_cnt 0 2006.285.13:52:38.94#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:52:39.06#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:52:39.06#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:52:39.06#ibcon#enter wrdev, iclass 26, count 0 2006.285.13:52:39.06#ibcon#first serial, iclass 26, count 0 2006.285.13:52:39.06#ibcon#enter sib2, iclass 26, count 0 2006.285.13:52:39.06#ibcon#flushed, iclass 26, count 0 2006.285.13:52:39.06#ibcon#about to write, iclass 26, count 0 2006.285.13:52:39.06#ibcon#wrote, iclass 26, count 0 2006.285.13:52:39.06#ibcon#about to read 3, iclass 26, count 0 2006.285.13:52:39.08#ibcon#read 3, iclass 26, count 0 2006.285.13:52:39.08#ibcon#about to read 4, iclass 26, count 0 2006.285.13:52:39.08#ibcon#read 4, iclass 26, count 0 2006.285.13:52:39.08#ibcon#about to read 5, iclass 26, count 0 2006.285.13:52:39.08#ibcon#read 5, iclass 26, count 0 2006.285.13:52:39.08#ibcon#about to read 6, iclass 26, count 0 2006.285.13:52:39.08#ibcon#read 6, iclass 26, count 0 2006.285.13:52:39.08#ibcon#end of sib2, iclass 26, count 0 2006.285.13:52:39.08#ibcon#*mode == 0, iclass 26, count 0 2006.285.13:52:39.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.13:52:39.08#ibcon#[27=USB\r\n] 2006.285.13:52:39.08#ibcon#*before write, iclass 26, count 0 2006.285.13:52:39.08#ibcon#enter sib2, iclass 26, count 0 2006.285.13:52:39.08#ibcon#flushed, iclass 26, count 0 2006.285.13:52:39.08#ibcon#about to write, iclass 26, count 0 2006.285.13:52:39.08#ibcon#wrote, iclass 26, count 0 2006.285.13:52:39.08#ibcon#about to read 3, iclass 26, count 0 2006.285.13:52:39.11#ibcon#read 3, iclass 26, count 0 2006.285.13:52:39.11#ibcon#about to read 4, iclass 26, count 0 2006.285.13:52:39.11#ibcon#read 4, iclass 26, count 0 2006.285.13:52:39.11#ibcon#about to read 5, iclass 26, count 0 2006.285.13:52:39.11#ibcon#read 5, iclass 26, count 0 2006.285.13:52:39.11#ibcon#about to read 6, iclass 26, count 0 2006.285.13:52:39.11#ibcon#read 6, iclass 26, count 0 2006.285.13:52:39.11#ibcon#end of sib2, iclass 26, count 0 2006.285.13:52:39.11#ibcon#*after write, iclass 26, count 0 2006.285.13:52:39.11#ibcon#*before return 0, iclass 26, count 0 2006.285.13:52:39.11#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:52:39.11#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.13:52:39.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.13:52:39.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.13:52:39.11$vck44/vabw=wide 2006.285.13:52:39.11#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.13:52:39.11#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.13:52:39.11#ibcon#ireg 8 cls_cnt 0 2006.285.13:52:39.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:52:39.11#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:52:39.11#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:52:39.11#ibcon#enter wrdev, iclass 28, count 0 2006.285.13:52:39.11#ibcon#first serial, iclass 28, count 0 2006.285.13:52:39.11#ibcon#enter sib2, iclass 28, count 0 2006.285.13:52:39.11#ibcon#flushed, iclass 28, count 0 2006.285.13:52:39.11#ibcon#about to write, iclass 28, count 0 2006.285.13:52:39.11#ibcon#wrote, iclass 28, count 0 2006.285.13:52:39.11#ibcon#about to read 3, iclass 28, count 0 2006.285.13:52:39.13#ibcon#read 3, iclass 28, count 0 2006.285.13:52:39.13#ibcon#about to read 4, iclass 28, count 0 2006.285.13:52:39.13#ibcon#read 4, iclass 28, count 0 2006.285.13:52:39.13#ibcon#about to read 5, iclass 28, count 0 2006.285.13:52:39.13#ibcon#read 5, iclass 28, count 0 2006.285.13:52:39.13#ibcon#about to read 6, iclass 28, count 0 2006.285.13:52:39.13#ibcon#read 6, iclass 28, count 0 2006.285.13:52:39.13#ibcon#end of sib2, iclass 28, count 0 2006.285.13:52:39.13#ibcon#*mode == 0, iclass 28, count 0 2006.285.13:52:39.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.13:52:39.13#ibcon#[25=BW32\r\n] 2006.285.13:52:39.13#ibcon#*before write, iclass 28, count 0 2006.285.13:52:39.13#ibcon#enter sib2, iclass 28, count 0 2006.285.13:52:39.13#ibcon#flushed, iclass 28, count 0 2006.285.13:52:39.13#ibcon#about to write, iclass 28, count 0 2006.285.13:52:39.13#ibcon#wrote, iclass 28, count 0 2006.285.13:52:39.13#ibcon#about to read 3, iclass 28, count 0 2006.285.13:52:39.16#ibcon#read 3, iclass 28, count 0 2006.285.13:52:39.16#ibcon#about to read 4, iclass 28, count 0 2006.285.13:52:39.16#ibcon#read 4, iclass 28, count 0 2006.285.13:52:39.16#ibcon#about to read 5, iclass 28, count 0 2006.285.13:52:39.16#ibcon#read 5, iclass 28, count 0 2006.285.13:52:39.16#ibcon#about to read 6, iclass 28, count 0 2006.285.13:52:39.16#ibcon#read 6, iclass 28, count 0 2006.285.13:52:39.16#ibcon#end of sib2, iclass 28, count 0 2006.285.13:52:39.16#ibcon#*after write, iclass 28, count 0 2006.285.13:52:39.16#ibcon#*before return 0, iclass 28, count 0 2006.285.13:52:39.16#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:52:39.16#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.13:52:39.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.13:52:39.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.13:52:39.16$vck44/vbbw=wide 2006.285.13:52:39.16#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.13:52:39.16#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.13:52:39.16#ibcon#ireg 8 cls_cnt 0 2006.285.13:52:39.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:52:39.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:52:39.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:52:39.23#ibcon#enter wrdev, iclass 30, count 0 2006.285.13:52:39.23#ibcon#first serial, iclass 30, count 0 2006.285.13:52:39.23#ibcon#enter sib2, iclass 30, count 0 2006.285.13:52:39.23#ibcon#flushed, iclass 30, count 0 2006.285.13:52:39.23#ibcon#about to write, iclass 30, count 0 2006.285.13:52:39.23#ibcon#wrote, iclass 30, count 0 2006.285.13:52:39.23#ibcon#about to read 3, iclass 30, count 0 2006.285.13:52:39.25#ibcon#read 3, iclass 30, count 0 2006.285.13:52:39.25#ibcon#about to read 4, iclass 30, count 0 2006.285.13:52:39.25#ibcon#read 4, iclass 30, count 0 2006.285.13:52:39.25#ibcon#about to read 5, iclass 30, count 0 2006.285.13:52:39.25#ibcon#read 5, iclass 30, count 0 2006.285.13:52:39.25#ibcon#about to read 6, iclass 30, count 0 2006.285.13:52:39.25#ibcon#read 6, iclass 30, count 0 2006.285.13:52:39.25#ibcon#end of sib2, iclass 30, count 0 2006.285.13:52:39.25#ibcon#*mode == 0, iclass 30, count 0 2006.285.13:52:39.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.13:52:39.25#ibcon#[27=BW32\r\n] 2006.285.13:52:39.25#ibcon#*before write, iclass 30, count 0 2006.285.13:52:39.25#ibcon#enter sib2, iclass 30, count 0 2006.285.13:52:39.25#ibcon#flushed, iclass 30, count 0 2006.285.13:52:39.25#ibcon#about to write, iclass 30, count 0 2006.285.13:52:39.25#ibcon#wrote, iclass 30, count 0 2006.285.13:52:39.25#ibcon#about to read 3, iclass 30, count 0 2006.285.13:52:39.28#ibcon#read 3, iclass 30, count 0 2006.285.13:52:39.28#ibcon#about to read 4, iclass 30, count 0 2006.285.13:52:39.28#ibcon#read 4, iclass 30, count 0 2006.285.13:52:39.28#ibcon#about to read 5, iclass 30, count 0 2006.285.13:52:39.28#ibcon#read 5, iclass 30, count 0 2006.285.13:52:39.28#ibcon#about to read 6, iclass 30, count 0 2006.285.13:52:39.28#ibcon#read 6, iclass 30, count 0 2006.285.13:52:39.28#ibcon#end of sib2, iclass 30, count 0 2006.285.13:52:39.28#ibcon#*after write, iclass 30, count 0 2006.285.13:52:39.28#ibcon#*before return 0, iclass 30, count 0 2006.285.13:52:39.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:52:39.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.13:52:39.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.13:52:39.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.13:52:39.28$setupk4/ifdk4 2006.285.13:52:39.28$ifdk4/lo= 2006.285.13:52:39.28$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:52:39.28$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:52:39.28$ifdk4/patch= 2006.285.13:52:39.28$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:52:39.28$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:52:39.28$setupk4/!*+20s 2006.285.13:52:46.85#abcon#<5=/04 1.5 3.2 19.05 971015.3\r\n> 2006.285.13:52:46.87#abcon#{5=INTERFACE CLEAR} 2006.285.13:52:46.93#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:52:53.22$setupk4/"tpicd 2006.285.13:52:53.22$setupk4/echo=off 2006.285.13:52:53.22$setupk4/xlog=off 2006.285.13:52:53.22:!2006.285.13:55:37 2006.285.13:52:54.14#trakl#Source acquired 2006.285.13:52:54.14#flagr#flagr/antenna,acquired 2006.285.13:55:37.00:preob 2006.285.13:55:37.14/onsource/TRACKING 2006.285.13:55:37.14:!2006.285.13:55:47 2006.285.13:55:47.00:"tape 2006.285.13:55:47.00:"st=record 2006.285.13:55:47.00:data_valid=on 2006.285.13:55:47.00:midob 2006.285.13:55:48.14/onsource/TRACKING 2006.285.13:55:48.14/wx/19.05,1015.3,97 2006.285.13:55:48.28/cable/+6.4997E-03 2006.285.13:55:49.37/va/01,07,usb,yes,32,34 2006.285.13:55:49.37/va/02,06,usb,yes,32,32 2006.285.13:55:49.37/va/03,07,usb,yes,31,33 2006.285.13:55:49.37/va/04,06,usb,yes,33,34 2006.285.13:55:49.37/va/05,03,usb,yes,32,33 2006.285.13:55:49.37/va/06,04,usb,yes,29,29 2006.285.13:55:49.37/va/07,04,usb,yes,30,30 2006.285.13:55:49.37/va/08,03,usb,yes,30,37 2006.285.13:55:49.60/valo/01,524.99,yes,locked 2006.285.13:55:49.60/valo/02,534.99,yes,locked 2006.285.13:55:49.60/valo/03,564.99,yes,locked 2006.285.13:55:49.60/valo/04,624.99,yes,locked 2006.285.13:55:49.60/valo/05,734.99,yes,locked 2006.285.13:55:49.60/valo/06,814.99,yes,locked 2006.285.13:55:49.60/valo/07,864.99,yes,locked 2006.285.13:55:49.60/valo/08,884.99,yes,locked 2006.285.13:55:50.69/vb/01,04,usb,yes,30,28 2006.285.13:55:50.69/vb/02,05,usb,yes,28,28 2006.285.13:55:50.69/vb/03,04,usb,yes,29,32 2006.285.13:55:50.69/vb/04,05,usb,yes,30,29 2006.285.13:55:50.69/vb/05,04,usb,yes,26,29 2006.285.13:55:50.69/vb/06,03,usb,yes,38,34 2006.285.13:55:50.69/vb/07,04,usb,yes,30,30 2006.285.13:55:50.69/vb/08,04,usb,yes,28,31 2006.285.13:55:50.93/vblo/01,629.99,yes,locked 2006.285.13:55:50.93/vblo/02,634.99,yes,locked 2006.285.13:55:50.93/vblo/03,649.99,yes,locked 2006.285.13:55:50.93/vblo/04,679.99,yes,locked 2006.285.13:55:50.93/vblo/05,709.99,yes,locked 2006.285.13:55:50.93/vblo/06,719.99,yes,locked 2006.285.13:55:50.93/vblo/07,734.99,yes,locked 2006.285.13:55:50.93/vblo/08,744.99,yes,locked 2006.285.13:55:51.08/vabw/8 2006.285.13:55:51.23/vbbw/8 2006.285.13:55:51.32/xfe/off,on,12.2 2006.285.13:55:51.71/ifatt/23,28,28,28 2006.285.13:55:52.08/fmout-gps/S +2.53E-07 2006.285.13:55:52.10:!2006.285.13:59:07 2006.285.13:59:07.00:data_valid=off 2006.285.13:59:07.00:"et 2006.285.13:59:07.00:!+3s 2006.285.13:59:10.01:"tape 2006.285.13:59:10.01:postob 2006.285.13:59:10.08/cable/+6.4988E-03 2006.285.13:59:10.08/wx/19.05,1015.2,97 2006.285.13:59:11.08/fmout-gps/S +2.54E-07 2006.285.13:59:11.08:scan_name=285-1409,jd0610,160 2006.285.13:59:11.08:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.285.13:59:12.14#flagr#flagr/antenna,new-source 2006.285.13:59:12.14:checkk5 2006.285.13:59:12.60/chk_autoobs//k5ts1/ autoobs is running! 2006.285.13:59:12.99/chk_autoobs//k5ts2/ autoobs is running! 2006.285.13:59:13.57/chk_autoobs//k5ts3/ autoobs is running! 2006.285.13:59:13.98/chk_autoobs//k5ts4/ autoobs is running! 2006.285.13:59:14.34/chk_obsdata//k5ts1/T2851355??a.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.13:59:14.79/chk_obsdata//k5ts2/T2851355??b.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.13:59:15.17/chk_obsdata//k5ts3/T2851355??c.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.13:59:15.66/chk_obsdata//k5ts4/T2851355??d.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.13:59:16.58/k5log//k5ts1_log_newline 2006.285.13:59:17.33/k5log//k5ts2_log_newline 2006.285.13:59:18.50/k5log//k5ts3_log_newline 2006.285.13:59:19.24/k5log//k5ts4_log_newline 2006.285.13:59:19.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.13:59:19.26:setupk4=1 2006.285.13:59:19.26$setupk4/echo=on 2006.285.13:59:19.26$setupk4/pcalon 2006.285.13:59:19.26$pcalon/"no phase cal control is implemented here 2006.285.13:59:19.26$setupk4/"tpicd=stop 2006.285.13:59:19.26$setupk4/"rec=synch_on 2006.285.13:59:19.26$setupk4/"rec_mode=128 2006.285.13:59:19.26$setupk4/!* 2006.285.13:59:19.26$setupk4/recpk4 2006.285.13:59:19.26$recpk4/recpatch= 2006.285.13:59:19.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.13:59:19.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.13:59:19.27$setupk4/vck44 2006.285.13:59:19.27$vck44/valo=1,524.99 2006.285.13:59:19.27#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.13:59:19.27#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.13:59:19.27#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:19.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:59:19.27#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:59:19.27#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:59:19.27#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:59:19.27#ibcon#first serial, iclass 11, count 0 2006.285.13:59:19.27#ibcon#enter sib2, iclass 11, count 0 2006.285.13:59:19.27#ibcon#flushed, iclass 11, count 0 2006.285.13:59:19.27#ibcon#about to write, iclass 11, count 0 2006.285.13:59:19.27#ibcon#wrote, iclass 11, count 0 2006.285.13:59:19.27#ibcon#about to read 3, iclass 11, count 0 2006.285.13:59:19.29#ibcon#read 3, iclass 11, count 0 2006.285.13:59:19.29#ibcon#about to read 4, iclass 11, count 0 2006.285.13:59:19.29#ibcon#read 4, iclass 11, count 0 2006.285.13:59:19.29#ibcon#about to read 5, iclass 11, count 0 2006.285.13:59:19.29#ibcon#read 5, iclass 11, count 0 2006.285.13:59:19.29#ibcon#about to read 6, iclass 11, count 0 2006.285.13:59:19.29#ibcon#read 6, iclass 11, count 0 2006.285.13:59:19.29#ibcon#end of sib2, iclass 11, count 0 2006.285.13:59:19.29#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:59:19.29#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:59:19.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.13:59:19.29#ibcon#*before write, iclass 11, count 0 2006.285.13:59:19.29#ibcon#enter sib2, iclass 11, count 0 2006.285.13:59:19.29#ibcon#flushed, iclass 11, count 0 2006.285.13:59:19.29#ibcon#about to write, iclass 11, count 0 2006.285.13:59:19.29#ibcon#wrote, iclass 11, count 0 2006.285.13:59:19.29#ibcon#about to read 3, iclass 11, count 0 2006.285.13:59:19.34#ibcon#read 3, iclass 11, count 0 2006.285.13:59:19.34#ibcon#about to read 4, iclass 11, count 0 2006.285.13:59:19.34#ibcon#read 4, iclass 11, count 0 2006.285.13:59:19.34#ibcon#about to read 5, iclass 11, count 0 2006.285.13:59:19.34#ibcon#read 5, iclass 11, count 0 2006.285.13:59:19.34#ibcon#about to read 6, iclass 11, count 0 2006.285.13:59:19.34#ibcon#read 6, iclass 11, count 0 2006.285.13:59:19.34#ibcon#end of sib2, iclass 11, count 0 2006.285.13:59:19.34#ibcon#*after write, iclass 11, count 0 2006.285.13:59:19.34#ibcon#*before return 0, iclass 11, count 0 2006.285.13:59:19.34#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:59:19.34#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:59:19.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:59:19.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:59:19.34$vck44/va=1,7 2006.285.13:59:19.34#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.13:59:19.34#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.13:59:19.34#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:19.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:59:19.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:59:19.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:59:19.34#ibcon#enter wrdev, iclass 13, count 2 2006.285.13:59:19.34#ibcon#first serial, iclass 13, count 2 2006.285.13:59:19.34#ibcon#enter sib2, iclass 13, count 2 2006.285.13:59:19.34#ibcon#flushed, iclass 13, count 2 2006.285.13:59:19.34#ibcon#about to write, iclass 13, count 2 2006.285.13:59:19.34#ibcon#wrote, iclass 13, count 2 2006.285.13:59:19.34#ibcon#about to read 3, iclass 13, count 2 2006.285.13:59:19.36#ibcon#read 3, iclass 13, count 2 2006.285.13:59:19.36#ibcon#about to read 4, iclass 13, count 2 2006.285.13:59:19.36#ibcon#read 4, iclass 13, count 2 2006.285.13:59:19.36#ibcon#about to read 5, iclass 13, count 2 2006.285.13:59:19.36#ibcon#read 5, iclass 13, count 2 2006.285.13:59:19.36#ibcon#about to read 6, iclass 13, count 2 2006.285.13:59:19.36#ibcon#read 6, iclass 13, count 2 2006.285.13:59:19.36#ibcon#end of sib2, iclass 13, count 2 2006.285.13:59:19.36#ibcon#*mode == 0, iclass 13, count 2 2006.285.13:59:19.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.13:59:19.36#ibcon#[25=AT01-07\r\n] 2006.285.13:59:19.36#ibcon#*before write, iclass 13, count 2 2006.285.13:59:19.36#ibcon#enter sib2, iclass 13, count 2 2006.285.13:59:19.36#ibcon#flushed, iclass 13, count 2 2006.285.13:59:19.36#ibcon#about to write, iclass 13, count 2 2006.285.13:59:19.36#ibcon#wrote, iclass 13, count 2 2006.285.13:59:19.36#ibcon#about to read 3, iclass 13, count 2 2006.285.13:59:19.39#ibcon#read 3, iclass 13, count 2 2006.285.13:59:19.39#ibcon#about to read 4, iclass 13, count 2 2006.285.13:59:19.39#ibcon#read 4, iclass 13, count 2 2006.285.13:59:19.39#ibcon#about to read 5, iclass 13, count 2 2006.285.13:59:19.39#ibcon#read 5, iclass 13, count 2 2006.285.13:59:19.39#ibcon#about to read 6, iclass 13, count 2 2006.285.13:59:19.39#ibcon#read 6, iclass 13, count 2 2006.285.13:59:19.39#ibcon#end of sib2, iclass 13, count 2 2006.285.13:59:19.39#ibcon#*after write, iclass 13, count 2 2006.285.13:59:19.39#ibcon#*before return 0, iclass 13, count 2 2006.285.13:59:19.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:59:19.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:59:19.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.13:59:19.39#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:19.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:59:19.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:59:19.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:59:19.51#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:59:19.51#ibcon#first serial, iclass 13, count 0 2006.285.13:59:19.51#ibcon#enter sib2, iclass 13, count 0 2006.285.13:59:19.51#ibcon#flushed, iclass 13, count 0 2006.285.13:59:19.51#ibcon#about to write, iclass 13, count 0 2006.285.13:59:19.51#ibcon#wrote, iclass 13, count 0 2006.285.13:59:19.51#ibcon#about to read 3, iclass 13, count 0 2006.285.13:59:19.53#ibcon#read 3, iclass 13, count 0 2006.285.13:59:19.53#ibcon#about to read 4, iclass 13, count 0 2006.285.13:59:19.53#ibcon#read 4, iclass 13, count 0 2006.285.13:59:19.53#ibcon#about to read 5, iclass 13, count 0 2006.285.13:59:19.53#ibcon#read 5, iclass 13, count 0 2006.285.13:59:19.53#ibcon#about to read 6, iclass 13, count 0 2006.285.13:59:19.53#ibcon#read 6, iclass 13, count 0 2006.285.13:59:19.53#ibcon#end of sib2, iclass 13, count 0 2006.285.13:59:19.53#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:59:19.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:59:19.53#ibcon#[25=USB\r\n] 2006.285.13:59:19.53#ibcon#*before write, iclass 13, count 0 2006.285.13:59:19.53#ibcon#enter sib2, iclass 13, count 0 2006.285.13:59:19.53#ibcon#flushed, iclass 13, count 0 2006.285.13:59:19.53#ibcon#about to write, iclass 13, count 0 2006.285.13:59:19.53#ibcon#wrote, iclass 13, count 0 2006.285.13:59:19.53#ibcon#about to read 3, iclass 13, count 0 2006.285.13:59:19.56#ibcon#read 3, iclass 13, count 0 2006.285.13:59:19.56#ibcon#about to read 4, iclass 13, count 0 2006.285.13:59:19.56#ibcon#read 4, iclass 13, count 0 2006.285.13:59:19.56#ibcon#about to read 5, iclass 13, count 0 2006.285.13:59:19.56#ibcon#read 5, iclass 13, count 0 2006.285.13:59:19.56#ibcon#about to read 6, iclass 13, count 0 2006.285.13:59:19.56#ibcon#read 6, iclass 13, count 0 2006.285.13:59:19.56#ibcon#end of sib2, iclass 13, count 0 2006.285.13:59:19.56#ibcon#*after write, iclass 13, count 0 2006.285.13:59:19.56#ibcon#*before return 0, iclass 13, count 0 2006.285.13:59:19.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:59:19.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:59:19.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:59:19.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:59:19.56$vck44/valo=2,534.99 2006.285.13:59:19.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.13:59:19.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.13:59:19.56#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:19.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:59:19.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:59:19.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:59:19.56#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:59:19.56#ibcon#first serial, iclass 15, count 0 2006.285.13:59:19.56#ibcon#enter sib2, iclass 15, count 0 2006.285.13:59:19.56#ibcon#flushed, iclass 15, count 0 2006.285.13:59:19.56#ibcon#about to write, iclass 15, count 0 2006.285.13:59:19.56#ibcon#wrote, iclass 15, count 0 2006.285.13:59:19.56#ibcon#about to read 3, iclass 15, count 0 2006.285.13:59:19.58#ibcon#read 3, iclass 15, count 0 2006.285.13:59:19.88#ibcon#about to read 4, iclass 15, count 0 2006.285.13:59:19.88#ibcon#read 4, iclass 15, count 0 2006.285.13:59:19.88#ibcon#about to read 5, iclass 15, count 0 2006.285.13:59:19.88#ibcon#read 5, iclass 15, count 0 2006.285.13:59:19.88#ibcon#about to read 6, iclass 15, count 0 2006.285.13:59:19.88#ibcon#read 6, iclass 15, count 0 2006.285.13:59:19.88#ibcon#end of sib2, iclass 15, count 0 2006.285.13:59:19.88#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:59:19.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:59:19.88#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.13:59:19.88#ibcon#*before write, iclass 15, count 0 2006.285.13:59:19.88#ibcon#enter sib2, iclass 15, count 0 2006.285.13:59:19.88#ibcon#flushed, iclass 15, count 0 2006.285.13:59:19.88#ibcon#about to write, iclass 15, count 0 2006.285.13:59:19.88#ibcon#wrote, iclass 15, count 0 2006.285.13:59:19.88#ibcon#about to read 3, iclass 15, count 0 2006.285.13:59:19.93#ibcon#read 3, iclass 15, count 0 2006.285.13:59:19.93#ibcon#about to read 4, iclass 15, count 0 2006.285.13:59:19.93#ibcon#read 4, iclass 15, count 0 2006.285.13:59:19.93#ibcon#about to read 5, iclass 15, count 0 2006.285.13:59:19.93#ibcon#read 5, iclass 15, count 0 2006.285.13:59:19.93#ibcon#about to read 6, iclass 15, count 0 2006.285.13:59:19.93#ibcon#read 6, iclass 15, count 0 2006.285.13:59:19.93#ibcon#end of sib2, iclass 15, count 0 2006.285.13:59:19.93#ibcon#*after write, iclass 15, count 0 2006.285.13:59:19.93#ibcon#*before return 0, iclass 15, count 0 2006.285.13:59:19.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:59:19.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:59:19.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:59:19.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:59:19.93$vck44/va=2,6 2006.285.13:59:19.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.13:59:19.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.13:59:19.93#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:19.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:59:19.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:59:19.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:59:19.93#ibcon#enter wrdev, iclass 17, count 2 2006.285.13:59:19.93#ibcon#first serial, iclass 17, count 2 2006.285.13:59:19.93#ibcon#enter sib2, iclass 17, count 2 2006.285.13:59:19.93#ibcon#flushed, iclass 17, count 2 2006.285.13:59:19.93#ibcon#about to write, iclass 17, count 2 2006.285.13:59:19.93#ibcon#wrote, iclass 17, count 2 2006.285.13:59:19.93#ibcon#about to read 3, iclass 17, count 2 2006.285.13:59:19.95#ibcon#read 3, iclass 17, count 2 2006.285.13:59:19.95#ibcon#about to read 4, iclass 17, count 2 2006.285.13:59:19.95#ibcon#read 4, iclass 17, count 2 2006.285.13:59:19.95#ibcon#about to read 5, iclass 17, count 2 2006.285.13:59:19.95#ibcon#read 5, iclass 17, count 2 2006.285.13:59:19.95#ibcon#about to read 6, iclass 17, count 2 2006.285.13:59:19.95#ibcon#read 6, iclass 17, count 2 2006.285.13:59:19.95#ibcon#end of sib2, iclass 17, count 2 2006.285.13:59:19.95#ibcon#*mode == 0, iclass 17, count 2 2006.285.13:59:19.95#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.13:59:19.95#ibcon#[25=AT02-06\r\n] 2006.285.13:59:19.95#ibcon#*before write, iclass 17, count 2 2006.285.13:59:19.95#ibcon#enter sib2, iclass 17, count 2 2006.285.13:59:19.95#ibcon#flushed, iclass 17, count 2 2006.285.13:59:19.95#ibcon#about to write, iclass 17, count 2 2006.285.13:59:19.95#ibcon#wrote, iclass 17, count 2 2006.285.13:59:19.95#ibcon#about to read 3, iclass 17, count 2 2006.285.13:59:19.98#ibcon#read 3, iclass 17, count 2 2006.285.13:59:19.98#ibcon#about to read 4, iclass 17, count 2 2006.285.13:59:19.98#ibcon#read 4, iclass 17, count 2 2006.285.13:59:19.98#ibcon#about to read 5, iclass 17, count 2 2006.285.13:59:19.98#ibcon#read 5, iclass 17, count 2 2006.285.13:59:19.98#ibcon#about to read 6, iclass 17, count 2 2006.285.13:59:19.98#ibcon#read 6, iclass 17, count 2 2006.285.13:59:19.98#ibcon#end of sib2, iclass 17, count 2 2006.285.13:59:19.98#ibcon#*after write, iclass 17, count 2 2006.285.13:59:19.98#ibcon#*before return 0, iclass 17, count 2 2006.285.13:59:19.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:59:19.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:59:19.98#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.13:59:19.98#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:19.98#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:59:20.10#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:59:20.10#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:59:20.10#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:59:20.10#ibcon#first serial, iclass 17, count 0 2006.285.13:59:20.10#ibcon#enter sib2, iclass 17, count 0 2006.285.13:59:20.10#ibcon#flushed, iclass 17, count 0 2006.285.13:59:20.10#ibcon#about to write, iclass 17, count 0 2006.285.13:59:20.10#ibcon#wrote, iclass 17, count 0 2006.285.13:59:20.10#ibcon#about to read 3, iclass 17, count 0 2006.285.13:59:20.12#ibcon#read 3, iclass 17, count 0 2006.285.13:59:20.12#ibcon#about to read 4, iclass 17, count 0 2006.285.13:59:20.12#ibcon#read 4, iclass 17, count 0 2006.285.13:59:20.12#ibcon#about to read 5, iclass 17, count 0 2006.285.13:59:20.12#ibcon#read 5, iclass 17, count 0 2006.285.13:59:20.12#ibcon#about to read 6, iclass 17, count 0 2006.285.13:59:20.12#ibcon#read 6, iclass 17, count 0 2006.285.13:59:20.12#ibcon#end of sib2, iclass 17, count 0 2006.285.13:59:20.12#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:59:20.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:59:20.12#ibcon#[25=USB\r\n] 2006.285.13:59:20.12#ibcon#*before write, iclass 17, count 0 2006.285.13:59:20.12#ibcon#enter sib2, iclass 17, count 0 2006.285.13:59:20.12#ibcon#flushed, iclass 17, count 0 2006.285.13:59:20.12#ibcon#about to write, iclass 17, count 0 2006.285.13:59:20.12#ibcon#wrote, iclass 17, count 0 2006.285.13:59:20.12#ibcon#about to read 3, iclass 17, count 0 2006.285.13:59:20.15#ibcon#read 3, iclass 17, count 0 2006.285.13:59:20.15#ibcon#about to read 4, iclass 17, count 0 2006.285.13:59:20.15#ibcon#read 4, iclass 17, count 0 2006.285.13:59:20.15#ibcon#about to read 5, iclass 17, count 0 2006.285.13:59:20.15#ibcon#read 5, iclass 17, count 0 2006.285.13:59:20.15#ibcon#about to read 6, iclass 17, count 0 2006.285.13:59:20.15#ibcon#read 6, iclass 17, count 0 2006.285.13:59:20.15#ibcon#end of sib2, iclass 17, count 0 2006.285.13:59:20.15#ibcon#*after write, iclass 17, count 0 2006.285.13:59:20.15#ibcon#*before return 0, iclass 17, count 0 2006.285.13:59:20.15#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:59:20.15#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:59:20.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:59:20.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:59:20.15$vck44/valo=3,564.99 2006.285.13:59:20.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.13:59:20.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.13:59:20.15#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:20.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:59:20.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:59:20.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:59:20.15#ibcon#enter wrdev, iclass 19, count 0 2006.285.13:59:20.15#ibcon#first serial, iclass 19, count 0 2006.285.13:59:20.15#ibcon#enter sib2, iclass 19, count 0 2006.285.13:59:20.15#ibcon#flushed, iclass 19, count 0 2006.285.13:59:20.15#ibcon#about to write, iclass 19, count 0 2006.285.13:59:20.15#ibcon#wrote, iclass 19, count 0 2006.285.13:59:20.15#ibcon#about to read 3, iclass 19, count 0 2006.285.13:59:20.17#ibcon#read 3, iclass 19, count 0 2006.285.13:59:20.50#ibcon#about to read 4, iclass 19, count 0 2006.285.13:59:20.50#ibcon#read 4, iclass 19, count 0 2006.285.13:59:20.50#ibcon#about to read 5, iclass 19, count 0 2006.285.13:59:20.50#ibcon#read 5, iclass 19, count 0 2006.285.13:59:20.50#ibcon#about to read 6, iclass 19, count 0 2006.285.13:59:20.50#ibcon#read 6, iclass 19, count 0 2006.285.13:59:20.50#ibcon#end of sib2, iclass 19, count 0 2006.285.13:59:20.50#ibcon#*mode == 0, iclass 19, count 0 2006.285.13:59:20.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.13:59:20.50#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.13:59:20.50#ibcon#*before write, iclass 19, count 0 2006.285.13:59:20.50#ibcon#enter sib2, iclass 19, count 0 2006.285.13:59:20.50#ibcon#flushed, iclass 19, count 0 2006.285.13:59:20.50#ibcon#about to write, iclass 19, count 0 2006.285.13:59:20.50#ibcon#wrote, iclass 19, count 0 2006.285.13:59:20.50#ibcon#about to read 3, iclass 19, count 0 2006.285.13:59:20.54#ibcon#read 3, iclass 19, count 0 2006.285.13:59:20.54#ibcon#about to read 4, iclass 19, count 0 2006.285.13:59:20.54#ibcon#read 4, iclass 19, count 0 2006.285.13:59:20.54#ibcon#about to read 5, iclass 19, count 0 2006.285.13:59:20.54#ibcon#read 5, iclass 19, count 0 2006.285.13:59:20.54#ibcon#about to read 6, iclass 19, count 0 2006.285.13:59:20.54#ibcon#read 6, iclass 19, count 0 2006.285.13:59:20.54#ibcon#end of sib2, iclass 19, count 0 2006.285.13:59:20.54#ibcon#*after write, iclass 19, count 0 2006.285.13:59:20.54#ibcon#*before return 0, iclass 19, count 0 2006.285.13:59:20.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:59:20.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.13:59:20.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.13:59:20.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.13:59:20.54$vck44/va=3,7 2006.285.13:59:20.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.13:59:20.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.13:59:20.54#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:20.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:59:20.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:59:20.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:59:20.54#ibcon#enter wrdev, iclass 21, count 2 2006.285.13:59:20.54#ibcon#first serial, iclass 21, count 2 2006.285.13:59:20.54#ibcon#enter sib2, iclass 21, count 2 2006.285.13:59:20.54#ibcon#flushed, iclass 21, count 2 2006.285.13:59:20.54#ibcon#about to write, iclass 21, count 2 2006.285.13:59:20.54#ibcon#wrote, iclass 21, count 2 2006.285.13:59:20.54#ibcon#about to read 3, iclass 21, count 2 2006.285.13:59:20.56#ibcon#read 3, iclass 21, count 2 2006.285.13:59:20.56#ibcon#about to read 4, iclass 21, count 2 2006.285.13:59:20.56#ibcon#read 4, iclass 21, count 2 2006.285.13:59:20.56#ibcon#about to read 5, iclass 21, count 2 2006.285.13:59:20.56#ibcon#read 5, iclass 21, count 2 2006.285.13:59:20.56#ibcon#about to read 6, iclass 21, count 2 2006.285.13:59:20.56#ibcon#read 6, iclass 21, count 2 2006.285.13:59:20.56#ibcon#end of sib2, iclass 21, count 2 2006.285.13:59:20.56#ibcon#*mode == 0, iclass 21, count 2 2006.285.13:59:20.56#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.13:59:20.56#ibcon#[25=AT03-07\r\n] 2006.285.13:59:20.56#ibcon#*before write, iclass 21, count 2 2006.285.13:59:20.56#ibcon#enter sib2, iclass 21, count 2 2006.285.13:59:20.56#ibcon#flushed, iclass 21, count 2 2006.285.13:59:20.56#ibcon#about to write, iclass 21, count 2 2006.285.13:59:20.56#ibcon#wrote, iclass 21, count 2 2006.285.13:59:20.56#ibcon#about to read 3, iclass 21, count 2 2006.285.13:59:20.59#ibcon#read 3, iclass 21, count 2 2006.285.13:59:20.59#ibcon#about to read 4, iclass 21, count 2 2006.285.13:59:20.59#ibcon#read 4, iclass 21, count 2 2006.285.13:59:20.59#ibcon#about to read 5, iclass 21, count 2 2006.285.13:59:20.59#ibcon#read 5, iclass 21, count 2 2006.285.13:59:20.59#ibcon#about to read 6, iclass 21, count 2 2006.285.13:59:20.59#ibcon#read 6, iclass 21, count 2 2006.285.13:59:20.59#ibcon#end of sib2, iclass 21, count 2 2006.285.13:59:20.59#ibcon#*after write, iclass 21, count 2 2006.285.13:59:20.59#ibcon#*before return 0, iclass 21, count 2 2006.285.13:59:20.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:59:20.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.13:59:20.59#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.13:59:20.59#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:20.59#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:59:20.71#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:59:20.71#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:59:20.71#ibcon#enter wrdev, iclass 21, count 0 2006.285.13:59:20.71#ibcon#first serial, iclass 21, count 0 2006.285.13:59:20.71#ibcon#enter sib2, iclass 21, count 0 2006.285.13:59:20.71#ibcon#flushed, iclass 21, count 0 2006.285.13:59:20.71#ibcon#about to write, iclass 21, count 0 2006.285.13:59:20.71#ibcon#wrote, iclass 21, count 0 2006.285.13:59:20.71#ibcon#about to read 3, iclass 21, count 0 2006.285.13:59:20.73#ibcon#read 3, iclass 21, count 0 2006.285.13:59:20.73#ibcon#about to read 4, iclass 21, count 0 2006.285.13:59:20.73#ibcon#read 4, iclass 21, count 0 2006.285.13:59:20.73#ibcon#about to read 5, iclass 21, count 0 2006.285.13:59:20.73#ibcon#read 5, iclass 21, count 0 2006.285.13:59:20.73#ibcon#about to read 6, iclass 21, count 0 2006.285.13:59:20.73#ibcon#read 6, iclass 21, count 0 2006.285.13:59:20.73#ibcon#end of sib2, iclass 21, count 0 2006.285.13:59:20.73#ibcon#*mode == 0, iclass 21, count 0 2006.285.13:59:20.73#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.13:59:20.73#ibcon#[25=USB\r\n] 2006.285.13:59:20.73#ibcon#*before write, iclass 21, count 0 2006.285.13:59:20.73#ibcon#enter sib2, iclass 21, count 0 2006.285.13:59:20.73#ibcon#flushed, iclass 21, count 0 2006.285.13:59:20.73#ibcon#about to write, iclass 21, count 0 2006.285.13:59:20.73#ibcon#wrote, iclass 21, count 0 2006.285.13:59:20.73#ibcon#about to read 3, iclass 21, count 0 2006.285.13:59:20.76#ibcon#read 3, iclass 21, count 0 2006.285.13:59:20.76#ibcon#about to read 4, iclass 21, count 0 2006.285.13:59:20.76#ibcon#read 4, iclass 21, count 0 2006.285.13:59:20.76#ibcon#about to read 5, iclass 21, count 0 2006.285.13:59:20.76#ibcon#read 5, iclass 21, count 0 2006.285.13:59:20.76#ibcon#about to read 6, iclass 21, count 0 2006.285.13:59:20.76#ibcon#read 6, iclass 21, count 0 2006.285.13:59:20.76#ibcon#end of sib2, iclass 21, count 0 2006.285.13:59:20.76#ibcon#*after write, iclass 21, count 0 2006.285.13:59:20.76#ibcon#*before return 0, iclass 21, count 0 2006.285.13:59:20.76#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:59:20.76#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.13:59:20.76#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.13:59:20.76#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.13:59:20.76$vck44/valo=4,624.99 2006.285.13:59:20.76#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.13:59:20.76#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.13:59:20.76#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:20.76#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:59:20.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:59:20.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:59:20.76#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:59:20.76#ibcon#first serial, iclass 23, count 0 2006.285.13:59:20.76#ibcon#enter sib2, iclass 23, count 0 2006.285.13:59:20.76#ibcon#flushed, iclass 23, count 0 2006.285.13:59:20.76#ibcon#about to write, iclass 23, count 0 2006.285.13:59:20.76#ibcon#wrote, iclass 23, count 0 2006.285.13:59:20.76#ibcon#about to read 3, iclass 23, count 0 2006.285.13:59:20.78#ibcon#read 3, iclass 23, count 0 2006.285.13:59:20.78#ibcon#about to read 4, iclass 23, count 0 2006.285.13:59:20.78#ibcon#read 4, iclass 23, count 0 2006.285.13:59:20.78#ibcon#about to read 5, iclass 23, count 0 2006.285.13:59:20.78#ibcon#read 5, iclass 23, count 0 2006.285.13:59:20.78#ibcon#about to read 6, iclass 23, count 0 2006.285.13:59:20.78#ibcon#read 6, iclass 23, count 0 2006.285.13:59:20.78#ibcon#end of sib2, iclass 23, count 0 2006.285.13:59:20.78#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:59:20.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:59:20.78#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.13:59:20.78#ibcon#*before write, iclass 23, count 0 2006.285.13:59:20.78#ibcon#enter sib2, iclass 23, count 0 2006.285.13:59:20.78#ibcon#flushed, iclass 23, count 0 2006.285.13:59:20.78#ibcon#about to write, iclass 23, count 0 2006.285.13:59:20.78#ibcon#wrote, iclass 23, count 0 2006.285.13:59:20.78#ibcon#about to read 3, iclass 23, count 0 2006.285.13:59:20.82#ibcon#read 3, iclass 23, count 0 2006.285.13:59:20.82#ibcon#about to read 4, iclass 23, count 0 2006.285.13:59:20.82#ibcon#read 4, iclass 23, count 0 2006.285.13:59:20.82#ibcon#about to read 5, iclass 23, count 0 2006.285.13:59:20.82#ibcon#read 5, iclass 23, count 0 2006.285.13:59:20.82#ibcon#about to read 6, iclass 23, count 0 2006.285.13:59:20.82#ibcon#read 6, iclass 23, count 0 2006.285.13:59:20.82#ibcon#end of sib2, iclass 23, count 0 2006.285.13:59:20.82#ibcon#*after write, iclass 23, count 0 2006.285.13:59:20.82#ibcon#*before return 0, iclass 23, count 0 2006.285.13:59:20.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:59:20.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:59:20.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:59:20.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:59:20.82$vck44/va=4,6 2006.285.13:59:20.82#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.13:59:20.82#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.13:59:20.82#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:20.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:59:20.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:59:20.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:59:20.88#ibcon#enter wrdev, iclass 25, count 2 2006.285.13:59:20.88#ibcon#first serial, iclass 25, count 2 2006.285.13:59:20.88#ibcon#enter sib2, iclass 25, count 2 2006.285.13:59:20.88#ibcon#flushed, iclass 25, count 2 2006.285.13:59:20.88#ibcon#about to write, iclass 25, count 2 2006.285.13:59:20.88#ibcon#wrote, iclass 25, count 2 2006.285.13:59:20.88#ibcon#about to read 3, iclass 25, count 2 2006.285.13:59:20.90#ibcon#read 3, iclass 25, count 2 2006.285.13:59:20.90#ibcon#about to read 4, iclass 25, count 2 2006.285.13:59:20.90#ibcon#read 4, iclass 25, count 2 2006.285.13:59:20.90#ibcon#about to read 5, iclass 25, count 2 2006.285.13:59:20.90#ibcon#read 5, iclass 25, count 2 2006.285.13:59:20.90#ibcon#about to read 6, iclass 25, count 2 2006.285.13:59:20.90#ibcon#read 6, iclass 25, count 2 2006.285.13:59:20.90#ibcon#end of sib2, iclass 25, count 2 2006.285.13:59:20.90#ibcon#*mode == 0, iclass 25, count 2 2006.285.13:59:20.90#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.13:59:20.90#ibcon#[25=AT04-06\r\n] 2006.285.13:59:20.90#ibcon#*before write, iclass 25, count 2 2006.285.13:59:20.90#ibcon#enter sib2, iclass 25, count 2 2006.285.13:59:20.90#ibcon#flushed, iclass 25, count 2 2006.285.13:59:20.90#ibcon#about to write, iclass 25, count 2 2006.285.13:59:20.90#ibcon#wrote, iclass 25, count 2 2006.285.13:59:20.90#ibcon#about to read 3, iclass 25, count 2 2006.285.13:59:20.93#ibcon#read 3, iclass 25, count 2 2006.285.13:59:20.93#ibcon#about to read 4, iclass 25, count 2 2006.285.13:59:20.93#ibcon#read 4, iclass 25, count 2 2006.285.13:59:20.93#ibcon#about to read 5, iclass 25, count 2 2006.285.13:59:20.93#ibcon#read 5, iclass 25, count 2 2006.285.13:59:20.93#ibcon#about to read 6, iclass 25, count 2 2006.285.13:59:20.93#ibcon#read 6, iclass 25, count 2 2006.285.13:59:20.93#ibcon#end of sib2, iclass 25, count 2 2006.285.13:59:20.93#ibcon#*after write, iclass 25, count 2 2006.285.13:59:20.93#ibcon#*before return 0, iclass 25, count 2 2006.285.13:59:20.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:59:20.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:59:20.93#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.13:59:20.93#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:20.93#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:59:21.05#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:59:21.05#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:59:21.05#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:59:21.05#ibcon#first serial, iclass 25, count 0 2006.285.13:59:21.05#ibcon#enter sib2, iclass 25, count 0 2006.285.13:59:21.05#ibcon#flushed, iclass 25, count 0 2006.285.13:59:21.05#ibcon#about to write, iclass 25, count 0 2006.285.13:59:21.05#ibcon#wrote, iclass 25, count 0 2006.285.13:59:21.05#ibcon#about to read 3, iclass 25, count 0 2006.285.13:59:21.07#ibcon#read 3, iclass 25, count 0 2006.285.13:59:21.07#ibcon#about to read 4, iclass 25, count 0 2006.285.13:59:21.07#ibcon#read 4, iclass 25, count 0 2006.285.13:59:21.07#ibcon#about to read 5, iclass 25, count 0 2006.285.13:59:21.07#ibcon#read 5, iclass 25, count 0 2006.285.13:59:21.07#ibcon#about to read 6, iclass 25, count 0 2006.285.13:59:21.07#ibcon#read 6, iclass 25, count 0 2006.285.13:59:21.07#ibcon#end of sib2, iclass 25, count 0 2006.285.13:59:21.07#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:59:21.07#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:59:21.07#ibcon#[25=USB\r\n] 2006.285.13:59:21.07#ibcon#*before write, iclass 25, count 0 2006.285.13:59:21.07#ibcon#enter sib2, iclass 25, count 0 2006.285.13:59:21.07#ibcon#flushed, iclass 25, count 0 2006.285.13:59:21.07#ibcon#about to write, iclass 25, count 0 2006.285.13:59:21.07#ibcon#wrote, iclass 25, count 0 2006.285.13:59:21.07#ibcon#about to read 3, iclass 25, count 0 2006.285.13:59:21.10#ibcon#read 3, iclass 25, count 0 2006.285.13:59:21.10#ibcon#about to read 4, iclass 25, count 0 2006.285.13:59:21.10#ibcon#read 4, iclass 25, count 0 2006.285.13:59:21.10#ibcon#about to read 5, iclass 25, count 0 2006.285.13:59:21.10#ibcon#read 5, iclass 25, count 0 2006.285.13:59:21.10#ibcon#about to read 6, iclass 25, count 0 2006.285.13:59:21.10#ibcon#read 6, iclass 25, count 0 2006.285.13:59:21.10#ibcon#end of sib2, iclass 25, count 0 2006.285.13:59:21.10#ibcon#*after write, iclass 25, count 0 2006.285.13:59:21.10#ibcon#*before return 0, iclass 25, count 0 2006.285.13:59:21.10#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:59:21.10#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:59:21.10#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:59:21.10#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:59:21.10$vck44/valo=5,734.99 2006.285.13:59:21.10#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.13:59:21.10#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.13:59:21.10#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:21.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:59:21.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:59:21.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:59:21.10#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:59:21.10#ibcon#first serial, iclass 27, count 0 2006.285.13:59:21.10#ibcon#enter sib2, iclass 27, count 0 2006.285.13:59:21.10#ibcon#flushed, iclass 27, count 0 2006.285.13:59:21.10#ibcon#about to write, iclass 27, count 0 2006.285.13:59:21.10#ibcon#wrote, iclass 27, count 0 2006.285.13:59:21.10#ibcon#about to read 3, iclass 27, count 0 2006.285.13:59:21.12#ibcon#read 3, iclass 27, count 0 2006.285.13:59:21.12#ibcon#about to read 4, iclass 27, count 0 2006.285.13:59:21.12#ibcon#read 4, iclass 27, count 0 2006.285.13:59:21.12#ibcon#about to read 5, iclass 27, count 0 2006.285.13:59:21.12#ibcon#read 5, iclass 27, count 0 2006.285.13:59:21.12#ibcon#about to read 6, iclass 27, count 0 2006.285.13:59:21.12#ibcon#read 6, iclass 27, count 0 2006.285.13:59:21.12#ibcon#end of sib2, iclass 27, count 0 2006.285.13:59:21.12#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:59:21.12#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:59:21.12#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.13:59:21.12#ibcon#*before write, iclass 27, count 0 2006.285.13:59:21.12#ibcon#enter sib2, iclass 27, count 0 2006.285.13:59:21.12#ibcon#flushed, iclass 27, count 0 2006.285.13:59:21.12#ibcon#about to write, iclass 27, count 0 2006.285.13:59:21.12#ibcon#wrote, iclass 27, count 0 2006.285.13:59:21.12#ibcon#about to read 3, iclass 27, count 0 2006.285.13:59:21.16#ibcon#read 3, iclass 27, count 0 2006.285.13:59:21.16#ibcon#about to read 4, iclass 27, count 0 2006.285.13:59:21.16#ibcon#read 4, iclass 27, count 0 2006.285.13:59:21.16#ibcon#about to read 5, iclass 27, count 0 2006.285.13:59:21.16#ibcon#read 5, iclass 27, count 0 2006.285.13:59:21.16#ibcon#about to read 6, iclass 27, count 0 2006.285.13:59:21.16#ibcon#read 6, iclass 27, count 0 2006.285.13:59:21.16#ibcon#end of sib2, iclass 27, count 0 2006.285.13:59:21.16#ibcon#*after write, iclass 27, count 0 2006.285.13:59:21.16#ibcon#*before return 0, iclass 27, count 0 2006.285.13:59:21.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:59:21.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:59:21.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:59:21.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:59:21.16$vck44/va=5,3 2006.285.13:59:21.16#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.13:59:21.16#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.13:59:21.16#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:21.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:59:21.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:59:21.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:59:21.22#ibcon#enter wrdev, iclass 29, count 2 2006.285.13:59:21.22#ibcon#first serial, iclass 29, count 2 2006.285.13:59:21.22#ibcon#enter sib2, iclass 29, count 2 2006.285.13:59:21.22#ibcon#flushed, iclass 29, count 2 2006.285.13:59:21.22#ibcon#about to write, iclass 29, count 2 2006.285.13:59:21.22#ibcon#wrote, iclass 29, count 2 2006.285.13:59:21.22#ibcon#about to read 3, iclass 29, count 2 2006.285.13:59:21.24#ibcon#read 3, iclass 29, count 2 2006.285.13:59:21.24#ibcon#about to read 4, iclass 29, count 2 2006.285.13:59:21.24#ibcon#read 4, iclass 29, count 2 2006.285.13:59:21.24#ibcon#about to read 5, iclass 29, count 2 2006.285.13:59:21.24#ibcon#read 5, iclass 29, count 2 2006.285.13:59:21.24#ibcon#about to read 6, iclass 29, count 2 2006.285.13:59:21.24#ibcon#read 6, iclass 29, count 2 2006.285.13:59:21.24#ibcon#end of sib2, iclass 29, count 2 2006.285.13:59:21.24#ibcon#*mode == 0, iclass 29, count 2 2006.285.13:59:21.24#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.13:59:21.24#ibcon#[25=AT05-03\r\n] 2006.285.13:59:21.24#ibcon#*before write, iclass 29, count 2 2006.285.13:59:21.24#ibcon#enter sib2, iclass 29, count 2 2006.285.13:59:21.24#ibcon#flushed, iclass 29, count 2 2006.285.13:59:21.24#ibcon#about to write, iclass 29, count 2 2006.285.13:59:21.24#ibcon#wrote, iclass 29, count 2 2006.285.13:59:21.24#ibcon#about to read 3, iclass 29, count 2 2006.285.13:59:21.27#ibcon#read 3, iclass 29, count 2 2006.285.13:59:21.27#ibcon#about to read 4, iclass 29, count 2 2006.285.13:59:21.27#ibcon#read 4, iclass 29, count 2 2006.285.13:59:21.27#ibcon#about to read 5, iclass 29, count 2 2006.285.13:59:21.27#ibcon#read 5, iclass 29, count 2 2006.285.13:59:21.27#ibcon#about to read 6, iclass 29, count 2 2006.285.13:59:21.27#ibcon#read 6, iclass 29, count 2 2006.285.13:59:21.27#ibcon#end of sib2, iclass 29, count 2 2006.285.13:59:21.27#ibcon#*after write, iclass 29, count 2 2006.285.13:59:21.27#ibcon#*before return 0, iclass 29, count 2 2006.285.13:59:21.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:59:21.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:59:21.27#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.13:59:21.27#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:21.27#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:59:21.39#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:59:21.39#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:59:21.39#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:59:21.39#ibcon#first serial, iclass 29, count 0 2006.285.13:59:21.39#ibcon#enter sib2, iclass 29, count 0 2006.285.13:59:21.39#ibcon#flushed, iclass 29, count 0 2006.285.13:59:21.39#ibcon#about to write, iclass 29, count 0 2006.285.13:59:21.39#ibcon#wrote, iclass 29, count 0 2006.285.13:59:21.39#ibcon#about to read 3, iclass 29, count 0 2006.285.13:59:21.41#ibcon#read 3, iclass 29, count 0 2006.285.13:59:21.41#ibcon#about to read 4, iclass 29, count 0 2006.285.13:59:21.41#ibcon#read 4, iclass 29, count 0 2006.285.13:59:21.41#ibcon#about to read 5, iclass 29, count 0 2006.285.13:59:21.41#ibcon#read 5, iclass 29, count 0 2006.285.13:59:21.41#ibcon#about to read 6, iclass 29, count 0 2006.285.13:59:21.41#ibcon#read 6, iclass 29, count 0 2006.285.13:59:21.41#ibcon#end of sib2, iclass 29, count 0 2006.285.13:59:21.41#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:59:21.41#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:59:21.41#ibcon#[25=USB\r\n] 2006.285.13:59:21.41#ibcon#*before write, iclass 29, count 0 2006.285.13:59:21.41#ibcon#enter sib2, iclass 29, count 0 2006.285.13:59:21.41#ibcon#flushed, iclass 29, count 0 2006.285.13:59:21.41#ibcon#about to write, iclass 29, count 0 2006.285.13:59:21.41#ibcon#wrote, iclass 29, count 0 2006.285.13:59:21.41#ibcon#about to read 3, iclass 29, count 0 2006.285.13:59:21.44#ibcon#read 3, iclass 29, count 0 2006.285.13:59:21.44#ibcon#about to read 4, iclass 29, count 0 2006.285.13:59:21.44#ibcon#read 4, iclass 29, count 0 2006.285.13:59:21.44#ibcon#about to read 5, iclass 29, count 0 2006.285.13:59:21.44#ibcon#read 5, iclass 29, count 0 2006.285.13:59:21.44#ibcon#about to read 6, iclass 29, count 0 2006.285.13:59:21.44#ibcon#read 6, iclass 29, count 0 2006.285.13:59:21.44#ibcon#end of sib2, iclass 29, count 0 2006.285.13:59:21.44#ibcon#*after write, iclass 29, count 0 2006.285.13:59:21.44#ibcon#*before return 0, iclass 29, count 0 2006.285.13:59:21.44#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:59:21.44#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:59:21.44#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:59:21.44#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:59:21.44$vck44/valo=6,814.99 2006.285.13:59:21.44#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.13:59:21.44#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.13:59:21.44#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:21.44#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:59:21.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:59:21.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:59:21.44#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:59:21.44#ibcon#first serial, iclass 31, count 0 2006.285.13:59:21.44#ibcon#enter sib2, iclass 31, count 0 2006.285.13:59:21.44#ibcon#flushed, iclass 31, count 0 2006.285.13:59:21.44#ibcon#about to write, iclass 31, count 0 2006.285.13:59:21.44#ibcon#wrote, iclass 31, count 0 2006.285.13:59:21.44#ibcon#about to read 3, iclass 31, count 0 2006.285.13:59:21.46#ibcon#read 3, iclass 31, count 0 2006.285.13:59:21.46#ibcon#about to read 4, iclass 31, count 0 2006.285.13:59:21.46#ibcon#read 4, iclass 31, count 0 2006.285.13:59:21.46#ibcon#about to read 5, iclass 31, count 0 2006.285.13:59:21.46#ibcon#read 5, iclass 31, count 0 2006.285.13:59:21.46#ibcon#about to read 6, iclass 31, count 0 2006.285.13:59:21.46#ibcon#read 6, iclass 31, count 0 2006.285.13:59:21.46#ibcon#end of sib2, iclass 31, count 0 2006.285.13:59:21.46#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:59:21.46#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:59:21.46#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.13:59:21.46#ibcon#*before write, iclass 31, count 0 2006.285.13:59:21.46#ibcon#enter sib2, iclass 31, count 0 2006.285.13:59:21.46#ibcon#flushed, iclass 31, count 0 2006.285.13:59:21.46#ibcon#about to write, iclass 31, count 0 2006.285.13:59:21.46#ibcon#wrote, iclass 31, count 0 2006.285.13:59:21.46#ibcon#about to read 3, iclass 31, count 0 2006.285.13:59:21.50#ibcon#read 3, iclass 31, count 0 2006.285.13:59:21.50#ibcon#about to read 4, iclass 31, count 0 2006.285.13:59:21.50#ibcon#read 4, iclass 31, count 0 2006.285.13:59:21.50#ibcon#about to read 5, iclass 31, count 0 2006.285.13:59:21.50#ibcon#read 5, iclass 31, count 0 2006.285.13:59:21.50#ibcon#about to read 6, iclass 31, count 0 2006.285.13:59:21.50#ibcon#read 6, iclass 31, count 0 2006.285.13:59:21.50#ibcon#end of sib2, iclass 31, count 0 2006.285.13:59:21.50#ibcon#*after write, iclass 31, count 0 2006.285.13:59:21.50#ibcon#*before return 0, iclass 31, count 0 2006.285.13:59:21.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:59:21.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:59:21.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:59:21.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:59:21.50$vck44/va=6,4 2006.285.13:59:21.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.13:59:21.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.13:59:21.58#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:21.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:59:21.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:59:21.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:59:21.58#ibcon#enter wrdev, iclass 33, count 2 2006.285.13:59:21.58#ibcon#first serial, iclass 33, count 2 2006.285.13:59:21.58#ibcon#enter sib2, iclass 33, count 2 2006.285.13:59:21.58#ibcon#flushed, iclass 33, count 2 2006.285.13:59:21.58#ibcon#about to write, iclass 33, count 2 2006.285.13:59:21.58#ibcon#wrote, iclass 33, count 2 2006.285.13:59:21.58#ibcon#about to read 3, iclass 33, count 2 2006.285.13:59:21.60#ibcon#read 3, iclass 33, count 2 2006.285.13:59:21.60#ibcon#about to read 4, iclass 33, count 2 2006.285.13:59:21.60#ibcon#read 4, iclass 33, count 2 2006.285.13:59:21.60#ibcon#about to read 5, iclass 33, count 2 2006.285.13:59:21.60#ibcon#read 5, iclass 33, count 2 2006.285.13:59:21.60#ibcon#about to read 6, iclass 33, count 2 2006.285.13:59:21.60#ibcon#read 6, iclass 33, count 2 2006.285.13:59:21.60#ibcon#end of sib2, iclass 33, count 2 2006.285.13:59:21.60#ibcon#*mode == 0, iclass 33, count 2 2006.285.13:59:21.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.13:59:21.60#ibcon#[25=AT06-04\r\n] 2006.285.13:59:21.60#ibcon#*before write, iclass 33, count 2 2006.285.13:59:21.60#ibcon#enter sib2, iclass 33, count 2 2006.285.13:59:21.60#ibcon#flushed, iclass 33, count 2 2006.285.13:59:21.60#ibcon#about to write, iclass 33, count 2 2006.285.13:59:21.60#ibcon#wrote, iclass 33, count 2 2006.285.13:59:21.60#ibcon#about to read 3, iclass 33, count 2 2006.285.13:59:21.63#ibcon#read 3, iclass 33, count 2 2006.285.13:59:21.63#ibcon#about to read 4, iclass 33, count 2 2006.285.13:59:21.63#ibcon#read 4, iclass 33, count 2 2006.285.13:59:21.63#ibcon#about to read 5, iclass 33, count 2 2006.285.13:59:21.63#ibcon#read 5, iclass 33, count 2 2006.285.13:59:21.63#ibcon#about to read 6, iclass 33, count 2 2006.285.13:59:21.63#ibcon#read 6, iclass 33, count 2 2006.285.13:59:21.63#ibcon#end of sib2, iclass 33, count 2 2006.285.13:59:21.63#ibcon#*after write, iclass 33, count 2 2006.285.13:59:21.63#ibcon#*before return 0, iclass 33, count 2 2006.285.13:59:21.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:59:21.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:59:21.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.13:59:21.63#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:21.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:59:21.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:59:21.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:59:21.75#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:59:21.75#ibcon#first serial, iclass 33, count 0 2006.285.13:59:21.75#ibcon#enter sib2, iclass 33, count 0 2006.285.13:59:21.75#ibcon#flushed, iclass 33, count 0 2006.285.13:59:21.75#ibcon#about to write, iclass 33, count 0 2006.285.13:59:21.75#ibcon#wrote, iclass 33, count 0 2006.285.13:59:21.75#ibcon#about to read 3, iclass 33, count 0 2006.285.13:59:21.77#ibcon#read 3, iclass 33, count 0 2006.285.13:59:21.77#ibcon#about to read 4, iclass 33, count 0 2006.285.13:59:21.77#ibcon#read 4, iclass 33, count 0 2006.285.13:59:21.77#ibcon#about to read 5, iclass 33, count 0 2006.285.13:59:21.77#ibcon#read 5, iclass 33, count 0 2006.285.13:59:21.77#ibcon#about to read 6, iclass 33, count 0 2006.285.13:59:21.77#ibcon#read 6, iclass 33, count 0 2006.285.13:59:21.77#ibcon#end of sib2, iclass 33, count 0 2006.285.13:59:21.77#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:59:21.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:59:21.77#ibcon#[25=USB\r\n] 2006.285.13:59:21.77#ibcon#*before write, iclass 33, count 0 2006.285.13:59:21.77#ibcon#enter sib2, iclass 33, count 0 2006.285.13:59:21.77#ibcon#flushed, iclass 33, count 0 2006.285.13:59:21.77#ibcon#about to write, iclass 33, count 0 2006.285.13:59:21.77#ibcon#wrote, iclass 33, count 0 2006.285.13:59:21.77#ibcon#about to read 3, iclass 33, count 0 2006.285.13:59:21.80#ibcon#read 3, iclass 33, count 0 2006.285.13:59:21.80#ibcon#about to read 4, iclass 33, count 0 2006.285.13:59:21.80#ibcon#read 4, iclass 33, count 0 2006.285.13:59:21.80#ibcon#about to read 5, iclass 33, count 0 2006.285.13:59:21.80#ibcon#read 5, iclass 33, count 0 2006.285.13:59:21.80#ibcon#about to read 6, iclass 33, count 0 2006.285.13:59:21.80#ibcon#read 6, iclass 33, count 0 2006.285.13:59:21.80#ibcon#end of sib2, iclass 33, count 0 2006.285.13:59:21.80#ibcon#*after write, iclass 33, count 0 2006.285.13:59:21.80#ibcon#*before return 0, iclass 33, count 0 2006.285.13:59:21.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:59:21.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:59:21.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:59:21.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:59:21.80$vck44/valo=7,864.99 2006.285.13:59:21.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.13:59:21.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.13:59:21.80#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:21.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:59:21.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:59:21.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:59:21.80#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:59:21.80#ibcon#first serial, iclass 35, count 0 2006.285.13:59:21.80#ibcon#enter sib2, iclass 35, count 0 2006.285.13:59:21.80#ibcon#flushed, iclass 35, count 0 2006.285.13:59:21.80#ibcon#about to write, iclass 35, count 0 2006.285.13:59:21.80#ibcon#wrote, iclass 35, count 0 2006.285.13:59:21.80#ibcon#about to read 3, iclass 35, count 0 2006.285.13:59:21.82#ibcon#read 3, iclass 35, count 0 2006.285.13:59:21.82#ibcon#about to read 4, iclass 35, count 0 2006.285.13:59:21.82#ibcon#read 4, iclass 35, count 0 2006.285.13:59:21.82#ibcon#about to read 5, iclass 35, count 0 2006.285.13:59:21.82#ibcon#read 5, iclass 35, count 0 2006.285.13:59:21.82#ibcon#about to read 6, iclass 35, count 0 2006.285.13:59:21.82#ibcon#read 6, iclass 35, count 0 2006.285.13:59:21.82#ibcon#end of sib2, iclass 35, count 0 2006.285.13:59:21.82#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:59:21.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:59:21.82#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.13:59:21.82#ibcon#*before write, iclass 35, count 0 2006.285.13:59:21.82#ibcon#enter sib2, iclass 35, count 0 2006.285.13:59:21.82#ibcon#flushed, iclass 35, count 0 2006.285.13:59:21.82#ibcon#about to write, iclass 35, count 0 2006.285.13:59:21.82#ibcon#wrote, iclass 35, count 0 2006.285.13:59:21.82#ibcon#about to read 3, iclass 35, count 0 2006.285.13:59:21.86#ibcon#read 3, iclass 35, count 0 2006.285.13:59:21.86#ibcon#about to read 4, iclass 35, count 0 2006.285.13:59:21.86#ibcon#read 4, iclass 35, count 0 2006.285.13:59:21.86#ibcon#about to read 5, iclass 35, count 0 2006.285.13:59:21.86#ibcon#read 5, iclass 35, count 0 2006.285.13:59:21.86#ibcon#about to read 6, iclass 35, count 0 2006.285.13:59:21.86#ibcon#read 6, iclass 35, count 0 2006.285.13:59:21.86#ibcon#end of sib2, iclass 35, count 0 2006.285.13:59:21.86#ibcon#*after write, iclass 35, count 0 2006.285.13:59:21.86#ibcon#*before return 0, iclass 35, count 0 2006.285.13:59:21.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:59:21.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:59:21.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:59:21.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:59:21.86$vck44/va=7,4 2006.285.13:59:21.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.13:59:21.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.13:59:21.86#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:21.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:59:21.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:59:21.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:59:21.92#ibcon#enter wrdev, iclass 37, count 2 2006.285.13:59:21.92#ibcon#first serial, iclass 37, count 2 2006.285.13:59:21.92#ibcon#enter sib2, iclass 37, count 2 2006.285.13:59:21.92#ibcon#flushed, iclass 37, count 2 2006.285.13:59:21.92#ibcon#about to write, iclass 37, count 2 2006.285.13:59:21.92#ibcon#wrote, iclass 37, count 2 2006.285.13:59:21.92#ibcon#about to read 3, iclass 37, count 2 2006.285.13:59:21.94#ibcon#read 3, iclass 37, count 2 2006.285.13:59:21.94#ibcon#about to read 4, iclass 37, count 2 2006.285.13:59:21.94#ibcon#read 4, iclass 37, count 2 2006.285.13:59:21.94#ibcon#about to read 5, iclass 37, count 2 2006.285.13:59:21.94#ibcon#read 5, iclass 37, count 2 2006.285.13:59:21.94#ibcon#about to read 6, iclass 37, count 2 2006.285.13:59:21.94#ibcon#read 6, iclass 37, count 2 2006.285.13:59:21.94#ibcon#end of sib2, iclass 37, count 2 2006.285.13:59:21.94#ibcon#*mode == 0, iclass 37, count 2 2006.285.13:59:21.94#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.13:59:21.94#ibcon#[25=AT07-04\r\n] 2006.285.13:59:21.94#ibcon#*before write, iclass 37, count 2 2006.285.13:59:21.94#ibcon#enter sib2, iclass 37, count 2 2006.285.13:59:21.94#ibcon#flushed, iclass 37, count 2 2006.285.13:59:21.94#ibcon#about to write, iclass 37, count 2 2006.285.13:59:21.94#ibcon#wrote, iclass 37, count 2 2006.285.13:59:21.94#ibcon#about to read 3, iclass 37, count 2 2006.285.13:59:21.97#ibcon#read 3, iclass 37, count 2 2006.285.13:59:21.97#ibcon#about to read 4, iclass 37, count 2 2006.285.13:59:21.97#ibcon#read 4, iclass 37, count 2 2006.285.13:59:21.97#ibcon#about to read 5, iclass 37, count 2 2006.285.13:59:21.97#ibcon#read 5, iclass 37, count 2 2006.285.13:59:21.97#ibcon#about to read 6, iclass 37, count 2 2006.285.13:59:21.97#ibcon#read 6, iclass 37, count 2 2006.285.13:59:21.97#ibcon#end of sib2, iclass 37, count 2 2006.285.13:59:21.97#ibcon#*after write, iclass 37, count 2 2006.285.13:59:21.97#ibcon#*before return 0, iclass 37, count 2 2006.285.13:59:21.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:59:21.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:59:21.97#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.13:59:21.97#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:21.97#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:59:22.09#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:59:22.09#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:59:22.09#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:59:22.09#ibcon#first serial, iclass 37, count 0 2006.285.13:59:22.09#ibcon#enter sib2, iclass 37, count 0 2006.285.13:59:22.09#ibcon#flushed, iclass 37, count 0 2006.285.13:59:22.09#ibcon#about to write, iclass 37, count 0 2006.285.13:59:22.09#ibcon#wrote, iclass 37, count 0 2006.285.13:59:22.09#ibcon#about to read 3, iclass 37, count 0 2006.285.13:59:22.11#ibcon#read 3, iclass 37, count 0 2006.285.13:59:22.11#ibcon#about to read 4, iclass 37, count 0 2006.285.13:59:22.11#ibcon#read 4, iclass 37, count 0 2006.285.13:59:22.11#ibcon#about to read 5, iclass 37, count 0 2006.285.13:59:22.11#ibcon#read 5, iclass 37, count 0 2006.285.13:59:22.11#ibcon#about to read 6, iclass 37, count 0 2006.285.13:59:22.11#ibcon#read 6, iclass 37, count 0 2006.285.13:59:22.11#ibcon#end of sib2, iclass 37, count 0 2006.285.13:59:22.11#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:59:22.11#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:59:22.11#ibcon#[25=USB\r\n] 2006.285.13:59:22.11#ibcon#*before write, iclass 37, count 0 2006.285.13:59:22.11#ibcon#enter sib2, iclass 37, count 0 2006.285.13:59:22.11#ibcon#flushed, iclass 37, count 0 2006.285.13:59:22.11#ibcon#about to write, iclass 37, count 0 2006.285.13:59:22.11#ibcon#wrote, iclass 37, count 0 2006.285.13:59:22.11#ibcon#about to read 3, iclass 37, count 0 2006.285.13:59:22.14#ibcon#read 3, iclass 37, count 0 2006.285.13:59:22.14#ibcon#about to read 4, iclass 37, count 0 2006.285.13:59:22.14#ibcon#read 4, iclass 37, count 0 2006.285.13:59:22.14#ibcon#about to read 5, iclass 37, count 0 2006.285.13:59:22.14#ibcon#read 5, iclass 37, count 0 2006.285.13:59:22.14#ibcon#about to read 6, iclass 37, count 0 2006.285.13:59:22.14#ibcon#read 6, iclass 37, count 0 2006.285.13:59:22.14#ibcon#end of sib2, iclass 37, count 0 2006.285.13:59:22.14#ibcon#*after write, iclass 37, count 0 2006.285.13:59:22.14#ibcon#*before return 0, iclass 37, count 0 2006.285.13:59:22.14#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:59:22.14#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:59:22.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:59:22.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:59:22.14$vck44/valo=8,884.99 2006.285.13:59:22.14#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.13:59:22.14#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.13:59:22.14#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:22.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:59:22.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:59:22.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:59:22.14#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:59:22.14#ibcon#first serial, iclass 39, count 0 2006.285.13:59:22.14#ibcon#enter sib2, iclass 39, count 0 2006.285.13:59:22.14#ibcon#flushed, iclass 39, count 0 2006.285.13:59:22.14#ibcon#about to write, iclass 39, count 0 2006.285.13:59:22.14#ibcon#wrote, iclass 39, count 0 2006.285.13:59:22.14#ibcon#about to read 3, iclass 39, count 0 2006.285.13:59:22.16#ibcon#read 3, iclass 39, count 0 2006.285.13:59:22.16#ibcon#about to read 4, iclass 39, count 0 2006.285.13:59:22.16#ibcon#read 4, iclass 39, count 0 2006.285.13:59:22.16#ibcon#about to read 5, iclass 39, count 0 2006.285.13:59:22.16#ibcon#read 5, iclass 39, count 0 2006.285.13:59:22.16#ibcon#about to read 6, iclass 39, count 0 2006.285.13:59:22.16#ibcon#read 6, iclass 39, count 0 2006.285.13:59:22.16#ibcon#end of sib2, iclass 39, count 0 2006.285.13:59:22.16#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:59:22.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:59:22.16#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.13:59:22.16#ibcon#*before write, iclass 39, count 0 2006.285.13:59:22.16#ibcon#enter sib2, iclass 39, count 0 2006.285.13:59:22.16#ibcon#flushed, iclass 39, count 0 2006.285.13:59:22.16#ibcon#about to write, iclass 39, count 0 2006.285.13:59:22.16#ibcon#wrote, iclass 39, count 0 2006.285.13:59:22.16#ibcon#about to read 3, iclass 39, count 0 2006.285.13:59:22.20#ibcon#read 3, iclass 39, count 0 2006.285.13:59:22.20#ibcon#about to read 4, iclass 39, count 0 2006.285.13:59:22.20#ibcon#read 4, iclass 39, count 0 2006.285.13:59:22.20#ibcon#about to read 5, iclass 39, count 0 2006.285.13:59:22.20#ibcon#read 5, iclass 39, count 0 2006.285.13:59:22.20#ibcon#about to read 6, iclass 39, count 0 2006.285.13:59:22.20#ibcon#read 6, iclass 39, count 0 2006.285.13:59:22.20#ibcon#end of sib2, iclass 39, count 0 2006.285.13:59:22.20#ibcon#*after write, iclass 39, count 0 2006.285.13:59:22.20#ibcon#*before return 0, iclass 39, count 0 2006.285.13:59:22.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:59:22.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:59:22.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:59:22.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:59:22.20$vck44/va=8,3 2006.285.13:59:22.20#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.13:59:22.20#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.13:59:22.20#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:22.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:59:22.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:59:22.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:59:22.26#ibcon#enter wrdev, iclass 3, count 2 2006.285.13:59:22.26#ibcon#first serial, iclass 3, count 2 2006.285.13:59:22.26#ibcon#enter sib2, iclass 3, count 2 2006.285.13:59:22.26#ibcon#flushed, iclass 3, count 2 2006.285.13:59:22.26#ibcon#about to write, iclass 3, count 2 2006.285.13:59:22.26#ibcon#wrote, iclass 3, count 2 2006.285.13:59:22.26#ibcon#about to read 3, iclass 3, count 2 2006.285.13:59:22.28#ibcon#read 3, iclass 3, count 2 2006.285.13:59:22.28#ibcon#about to read 4, iclass 3, count 2 2006.285.13:59:22.28#ibcon#read 4, iclass 3, count 2 2006.285.13:59:22.28#ibcon#about to read 5, iclass 3, count 2 2006.285.13:59:22.28#ibcon#read 5, iclass 3, count 2 2006.285.13:59:22.28#ibcon#about to read 6, iclass 3, count 2 2006.285.13:59:22.28#ibcon#read 6, iclass 3, count 2 2006.285.13:59:22.28#ibcon#end of sib2, iclass 3, count 2 2006.285.13:59:22.28#ibcon#*mode == 0, iclass 3, count 2 2006.285.13:59:22.28#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.13:59:22.28#ibcon#[25=AT08-03\r\n] 2006.285.13:59:22.28#ibcon#*before write, iclass 3, count 2 2006.285.13:59:22.28#ibcon#enter sib2, iclass 3, count 2 2006.285.13:59:22.28#ibcon#flushed, iclass 3, count 2 2006.285.13:59:22.28#ibcon#about to write, iclass 3, count 2 2006.285.13:59:22.28#ibcon#wrote, iclass 3, count 2 2006.285.13:59:22.28#ibcon#about to read 3, iclass 3, count 2 2006.285.13:59:22.31#ibcon#read 3, iclass 3, count 2 2006.285.13:59:22.31#ibcon#about to read 4, iclass 3, count 2 2006.285.13:59:22.31#ibcon#read 4, iclass 3, count 2 2006.285.13:59:22.31#ibcon#about to read 5, iclass 3, count 2 2006.285.13:59:22.31#ibcon#read 5, iclass 3, count 2 2006.285.13:59:22.31#ibcon#about to read 6, iclass 3, count 2 2006.285.13:59:22.31#ibcon#read 6, iclass 3, count 2 2006.285.13:59:22.31#ibcon#end of sib2, iclass 3, count 2 2006.285.13:59:22.31#ibcon#*after write, iclass 3, count 2 2006.285.13:59:22.31#ibcon#*before return 0, iclass 3, count 2 2006.285.13:59:22.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:59:22.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:59:22.31#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.13:59:22.31#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:22.31#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:59:22.43#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:59:22.43#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:59:22.43#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:59:22.43#ibcon#first serial, iclass 3, count 0 2006.285.13:59:22.43#ibcon#enter sib2, iclass 3, count 0 2006.285.13:59:22.43#ibcon#flushed, iclass 3, count 0 2006.285.13:59:22.43#ibcon#about to write, iclass 3, count 0 2006.285.13:59:22.43#ibcon#wrote, iclass 3, count 0 2006.285.13:59:22.43#ibcon#about to read 3, iclass 3, count 0 2006.285.13:59:22.45#ibcon#read 3, iclass 3, count 0 2006.285.13:59:22.45#ibcon#about to read 4, iclass 3, count 0 2006.285.13:59:22.45#ibcon#read 4, iclass 3, count 0 2006.285.13:59:22.45#ibcon#about to read 5, iclass 3, count 0 2006.285.13:59:22.45#ibcon#read 5, iclass 3, count 0 2006.285.13:59:22.45#ibcon#about to read 6, iclass 3, count 0 2006.285.13:59:22.45#ibcon#read 6, iclass 3, count 0 2006.285.13:59:22.45#ibcon#end of sib2, iclass 3, count 0 2006.285.13:59:22.45#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:59:22.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:59:22.45#ibcon#[25=USB\r\n] 2006.285.13:59:22.45#ibcon#*before write, iclass 3, count 0 2006.285.13:59:22.45#ibcon#enter sib2, iclass 3, count 0 2006.285.13:59:22.45#ibcon#flushed, iclass 3, count 0 2006.285.13:59:22.45#ibcon#about to write, iclass 3, count 0 2006.285.13:59:22.45#ibcon#wrote, iclass 3, count 0 2006.285.13:59:22.45#ibcon#about to read 3, iclass 3, count 0 2006.285.13:59:22.48#ibcon#read 3, iclass 3, count 0 2006.285.13:59:22.48#ibcon#about to read 4, iclass 3, count 0 2006.285.13:59:22.48#ibcon#read 4, iclass 3, count 0 2006.285.13:59:22.48#ibcon#about to read 5, iclass 3, count 0 2006.285.13:59:22.48#ibcon#read 5, iclass 3, count 0 2006.285.13:59:22.48#ibcon#about to read 6, iclass 3, count 0 2006.285.13:59:22.48#ibcon#read 6, iclass 3, count 0 2006.285.13:59:22.48#ibcon#end of sib2, iclass 3, count 0 2006.285.13:59:22.48#ibcon#*after write, iclass 3, count 0 2006.285.13:59:22.48#ibcon#*before return 0, iclass 3, count 0 2006.285.13:59:22.48#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:59:22.48#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:59:22.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:59:22.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:59:22.48$vck44/vblo=1,629.99 2006.285.13:59:22.48#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.13:59:22.48#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.13:59:22.48#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:22.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:59:22.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:59:22.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:59:22.48#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:59:22.48#ibcon#first serial, iclass 5, count 0 2006.285.13:59:22.48#ibcon#enter sib2, iclass 5, count 0 2006.285.13:59:22.48#ibcon#flushed, iclass 5, count 0 2006.285.13:59:22.48#ibcon#about to write, iclass 5, count 0 2006.285.13:59:22.48#ibcon#wrote, iclass 5, count 0 2006.285.13:59:22.48#ibcon#about to read 3, iclass 5, count 0 2006.285.13:59:22.50#ibcon#read 3, iclass 5, count 0 2006.285.13:59:22.69#ibcon#about to read 4, iclass 5, count 0 2006.285.13:59:22.70#ibcon#read 4, iclass 5, count 0 2006.285.13:59:22.70#ibcon#about to read 5, iclass 5, count 0 2006.285.13:59:22.70#ibcon#read 5, iclass 5, count 0 2006.285.13:59:22.70#ibcon#about to read 6, iclass 5, count 0 2006.285.13:59:22.70#ibcon#read 6, iclass 5, count 0 2006.285.13:59:22.70#ibcon#end of sib2, iclass 5, count 0 2006.285.13:59:22.70#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:59:22.70#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:59:22.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.13:59:22.70#ibcon#*before write, iclass 5, count 0 2006.285.13:59:22.70#ibcon#enter sib2, iclass 5, count 0 2006.285.13:59:22.70#ibcon#flushed, iclass 5, count 0 2006.285.13:59:22.70#ibcon#about to write, iclass 5, count 0 2006.285.13:59:22.70#ibcon#wrote, iclass 5, count 0 2006.285.13:59:22.70#ibcon#about to read 3, iclass 5, count 0 2006.285.13:59:22.74#ibcon#read 3, iclass 5, count 0 2006.285.13:59:22.74#ibcon#about to read 4, iclass 5, count 0 2006.285.13:59:22.74#ibcon#read 4, iclass 5, count 0 2006.285.13:59:22.74#ibcon#about to read 5, iclass 5, count 0 2006.285.13:59:22.74#ibcon#read 5, iclass 5, count 0 2006.285.13:59:22.74#ibcon#about to read 6, iclass 5, count 0 2006.285.13:59:22.74#ibcon#read 6, iclass 5, count 0 2006.285.13:59:22.74#ibcon#end of sib2, iclass 5, count 0 2006.285.13:59:22.74#ibcon#*after write, iclass 5, count 0 2006.285.13:59:22.74#ibcon#*before return 0, iclass 5, count 0 2006.285.13:59:22.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:59:22.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:59:22.74#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:59:22.74#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:59:22.74$vck44/vb=1,4 2006.285.13:59:22.74#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.13:59:22.74#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.13:59:22.74#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:22.74#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:59:22.74#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:59:22.74#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:59:22.74#ibcon#enter wrdev, iclass 7, count 2 2006.285.13:59:22.74#ibcon#first serial, iclass 7, count 2 2006.285.13:59:22.74#ibcon#enter sib2, iclass 7, count 2 2006.285.13:59:22.74#ibcon#flushed, iclass 7, count 2 2006.285.13:59:22.74#ibcon#about to write, iclass 7, count 2 2006.285.13:59:22.74#ibcon#wrote, iclass 7, count 2 2006.285.13:59:22.74#ibcon#about to read 3, iclass 7, count 2 2006.285.13:59:22.76#ibcon#read 3, iclass 7, count 2 2006.285.13:59:22.76#ibcon#about to read 4, iclass 7, count 2 2006.285.13:59:22.76#ibcon#read 4, iclass 7, count 2 2006.285.13:59:22.76#ibcon#about to read 5, iclass 7, count 2 2006.285.13:59:22.76#ibcon#read 5, iclass 7, count 2 2006.285.13:59:22.76#ibcon#about to read 6, iclass 7, count 2 2006.285.13:59:22.76#ibcon#read 6, iclass 7, count 2 2006.285.13:59:22.76#ibcon#end of sib2, iclass 7, count 2 2006.285.13:59:22.76#ibcon#*mode == 0, iclass 7, count 2 2006.285.13:59:22.76#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.13:59:22.76#ibcon#[27=AT01-04\r\n] 2006.285.13:59:22.76#ibcon#*before write, iclass 7, count 2 2006.285.13:59:22.76#ibcon#enter sib2, iclass 7, count 2 2006.285.13:59:22.76#ibcon#flushed, iclass 7, count 2 2006.285.13:59:22.76#ibcon#about to write, iclass 7, count 2 2006.285.13:59:22.76#ibcon#wrote, iclass 7, count 2 2006.285.13:59:22.76#ibcon#about to read 3, iclass 7, count 2 2006.285.13:59:22.79#ibcon#read 3, iclass 7, count 2 2006.285.13:59:22.79#ibcon#about to read 4, iclass 7, count 2 2006.285.13:59:22.79#ibcon#read 4, iclass 7, count 2 2006.285.13:59:22.79#ibcon#about to read 5, iclass 7, count 2 2006.285.13:59:22.79#ibcon#read 5, iclass 7, count 2 2006.285.13:59:22.79#ibcon#about to read 6, iclass 7, count 2 2006.285.13:59:22.79#ibcon#read 6, iclass 7, count 2 2006.285.13:59:22.79#ibcon#end of sib2, iclass 7, count 2 2006.285.13:59:22.79#ibcon#*after write, iclass 7, count 2 2006.285.13:59:22.79#ibcon#*before return 0, iclass 7, count 2 2006.285.13:59:22.79#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:59:22.79#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.13:59:22.79#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.13:59:22.79#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:22.79#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:59:22.91#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:59:22.91#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:59:22.91#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:59:22.91#ibcon#first serial, iclass 7, count 0 2006.285.13:59:22.91#ibcon#enter sib2, iclass 7, count 0 2006.285.13:59:22.91#ibcon#flushed, iclass 7, count 0 2006.285.13:59:22.91#ibcon#about to write, iclass 7, count 0 2006.285.13:59:22.91#ibcon#wrote, iclass 7, count 0 2006.285.13:59:22.91#ibcon#about to read 3, iclass 7, count 0 2006.285.13:59:22.93#ibcon#read 3, iclass 7, count 0 2006.285.13:59:22.93#ibcon#about to read 4, iclass 7, count 0 2006.285.13:59:22.93#ibcon#read 4, iclass 7, count 0 2006.285.13:59:22.93#ibcon#about to read 5, iclass 7, count 0 2006.285.13:59:22.93#ibcon#read 5, iclass 7, count 0 2006.285.13:59:22.93#ibcon#about to read 6, iclass 7, count 0 2006.285.13:59:22.93#ibcon#read 6, iclass 7, count 0 2006.285.13:59:22.93#ibcon#end of sib2, iclass 7, count 0 2006.285.13:59:22.93#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:59:22.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:59:22.93#ibcon#[27=USB\r\n] 2006.285.13:59:22.93#ibcon#*before write, iclass 7, count 0 2006.285.13:59:22.93#ibcon#enter sib2, iclass 7, count 0 2006.285.13:59:22.93#ibcon#flushed, iclass 7, count 0 2006.285.13:59:22.93#ibcon#about to write, iclass 7, count 0 2006.285.13:59:22.93#ibcon#wrote, iclass 7, count 0 2006.285.13:59:22.93#ibcon#about to read 3, iclass 7, count 0 2006.285.13:59:22.96#ibcon#read 3, iclass 7, count 0 2006.285.13:59:22.96#ibcon#about to read 4, iclass 7, count 0 2006.285.13:59:22.96#ibcon#read 4, iclass 7, count 0 2006.285.13:59:22.96#ibcon#about to read 5, iclass 7, count 0 2006.285.13:59:22.96#ibcon#read 5, iclass 7, count 0 2006.285.13:59:22.96#ibcon#about to read 6, iclass 7, count 0 2006.285.13:59:22.96#ibcon#read 6, iclass 7, count 0 2006.285.13:59:22.96#ibcon#end of sib2, iclass 7, count 0 2006.285.13:59:22.96#ibcon#*after write, iclass 7, count 0 2006.285.13:59:22.96#ibcon#*before return 0, iclass 7, count 0 2006.285.13:59:22.96#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:59:22.96#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.13:59:22.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:59:22.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:59:22.96$vck44/vblo=2,634.99 2006.285.13:59:22.96#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.13:59:22.96#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.13:59:22.96#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:22.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:59:22.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:59:22.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:59:22.96#ibcon#enter wrdev, iclass 11, count 0 2006.285.13:59:22.96#ibcon#first serial, iclass 11, count 0 2006.285.13:59:22.96#ibcon#enter sib2, iclass 11, count 0 2006.285.13:59:22.96#ibcon#flushed, iclass 11, count 0 2006.285.13:59:22.96#ibcon#about to write, iclass 11, count 0 2006.285.13:59:22.96#ibcon#wrote, iclass 11, count 0 2006.285.13:59:22.96#ibcon#about to read 3, iclass 11, count 0 2006.285.13:59:22.98#ibcon#read 3, iclass 11, count 0 2006.285.13:59:22.98#ibcon#about to read 4, iclass 11, count 0 2006.285.13:59:22.98#ibcon#read 4, iclass 11, count 0 2006.285.13:59:22.98#ibcon#about to read 5, iclass 11, count 0 2006.285.13:59:22.98#ibcon#read 5, iclass 11, count 0 2006.285.13:59:22.98#ibcon#about to read 6, iclass 11, count 0 2006.285.13:59:22.98#ibcon#read 6, iclass 11, count 0 2006.285.13:59:22.98#ibcon#end of sib2, iclass 11, count 0 2006.285.13:59:22.98#ibcon#*mode == 0, iclass 11, count 0 2006.285.13:59:22.98#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.13:59:22.98#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.13:59:22.98#ibcon#*before write, iclass 11, count 0 2006.285.13:59:22.98#ibcon#enter sib2, iclass 11, count 0 2006.285.13:59:22.98#ibcon#flushed, iclass 11, count 0 2006.285.13:59:22.98#ibcon#about to write, iclass 11, count 0 2006.285.13:59:22.98#ibcon#wrote, iclass 11, count 0 2006.285.13:59:22.98#ibcon#about to read 3, iclass 11, count 0 2006.285.13:59:23.02#ibcon#read 3, iclass 11, count 0 2006.285.13:59:23.02#ibcon#about to read 4, iclass 11, count 0 2006.285.13:59:23.02#ibcon#read 4, iclass 11, count 0 2006.285.13:59:23.02#ibcon#about to read 5, iclass 11, count 0 2006.285.13:59:23.02#ibcon#read 5, iclass 11, count 0 2006.285.13:59:23.02#ibcon#about to read 6, iclass 11, count 0 2006.285.13:59:23.02#ibcon#read 6, iclass 11, count 0 2006.285.13:59:23.02#ibcon#end of sib2, iclass 11, count 0 2006.285.13:59:23.02#ibcon#*after write, iclass 11, count 0 2006.285.13:59:23.02#ibcon#*before return 0, iclass 11, count 0 2006.285.13:59:23.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:59:23.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.13:59:23.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.13:59:23.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.13:59:23.02$vck44/vb=2,5 2006.285.13:59:23.02#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.13:59:23.02#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.13:59:23.02#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:23.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:59:23.08#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:59:23.08#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:59:23.08#ibcon#enter wrdev, iclass 13, count 2 2006.285.13:59:23.08#ibcon#first serial, iclass 13, count 2 2006.285.13:59:23.08#ibcon#enter sib2, iclass 13, count 2 2006.285.13:59:23.08#ibcon#flushed, iclass 13, count 2 2006.285.13:59:23.08#ibcon#about to write, iclass 13, count 2 2006.285.13:59:23.08#ibcon#wrote, iclass 13, count 2 2006.285.13:59:23.08#ibcon#about to read 3, iclass 13, count 2 2006.285.13:59:23.10#ibcon#read 3, iclass 13, count 2 2006.285.13:59:23.10#ibcon#about to read 4, iclass 13, count 2 2006.285.13:59:23.10#ibcon#read 4, iclass 13, count 2 2006.285.13:59:23.10#ibcon#about to read 5, iclass 13, count 2 2006.285.13:59:23.10#ibcon#read 5, iclass 13, count 2 2006.285.13:59:23.10#ibcon#about to read 6, iclass 13, count 2 2006.285.13:59:23.10#ibcon#read 6, iclass 13, count 2 2006.285.13:59:23.10#ibcon#end of sib2, iclass 13, count 2 2006.285.13:59:23.10#ibcon#*mode == 0, iclass 13, count 2 2006.285.13:59:23.10#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.13:59:23.10#ibcon#[27=AT02-05\r\n] 2006.285.13:59:23.10#ibcon#*before write, iclass 13, count 2 2006.285.13:59:23.10#ibcon#enter sib2, iclass 13, count 2 2006.285.13:59:23.10#ibcon#flushed, iclass 13, count 2 2006.285.13:59:23.10#ibcon#about to write, iclass 13, count 2 2006.285.13:59:23.10#ibcon#wrote, iclass 13, count 2 2006.285.13:59:23.10#ibcon#about to read 3, iclass 13, count 2 2006.285.13:59:23.13#ibcon#read 3, iclass 13, count 2 2006.285.13:59:23.13#ibcon#about to read 4, iclass 13, count 2 2006.285.13:59:23.13#ibcon#read 4, iclass 13, count 2 2006.285.13:59:23.13#ibcon#about to read 5, iclass 13, count 2 2006.285.13:59:23.13#ibcon#read 5, iclass 13, count 2 2006.285.13:59:23.13#ibcon#about to read 6, iclass 13, count 2 2006.285.13:59:23.13#ibcon#read 6, iclass 13, count 2 2006.285.13:59:23.13#ibcon#end of sib2, iclass 13, count 2 2006.285.13:59:23.13#ibcon#*after write, iclass 13, count 2 2006.285.13:59:23.13#ibcon#*before return 0, iclass 13, count 2 2006.285.13:59:23.13#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:59:23.13#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.13:59:23.13#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.13:59:23.13#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:23.13#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:59:23.25#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:59:23.25#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:59:23.25#ibcon#enter wrdev, iclass 13, count 0 2006.285.13:59:23.25#ibcon#first serial, iclass 13, count 0 2006.285.13:59:23.25#ibcon#enter sib2, iclass 13, count 0 2006.285.13:59:23.25#ibcon#flushed, iclass 13, count 0 2006.285.13:59:23.25#ibcon#about to write, iclass 13, count 0 2006.285.13:59:23.25#ibcon#wrote, iclass 13, count 0 2006.285.13:59:23.25#ibcon#about to read 3, iclass 13, count 0 2006.285.13:59:23.27#ibcon#read 3, iclass 13, count 0 2006.285.13:59:23.27#ibcon#about to read 4, iclass 13, count 0 2006.285.13:59:23.27#ibcon#read 4, iclass 13, count 0 2006.285.13:59:23.27#ibcon#about to read 5, iclass 13, count 0 2006.285.13:59:23.27#ibcon#read 5, iclass 13, count 0 2006.285.13:59:23.27#ibcon#about to read 6, iclass 13, count 0 2006.285.13:59:23.27#ibcon#read 6, iclass 13, count 0 2006.285.13:59:23.27#ibcon#end of sib2, iclass 13, count 0 2006.285.13:59:23.27#ibcon#*mode == 0, iclass 13, count 0 2006.285.13:59:23.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.13:59:23.27#ibcon#[27=USB\r\n] 2006.285.13:59:23.27#ibcon#*before write, iclass 13, count 0 2006.285.13:59:23.27#ibcon#enter sib2, iclass 13, count 0 2006.285.13:59:23.27#ibcon#flushed, iclass 13, count 0 2006.285.13:59:23.27#ibcon#about to write, iclass 13, count 0 2006.285.13:59:23.27#ibcon#wrote, iclass 13, count 0 2006.285.13:59:23.27#ibcon#about to read 3, iclass 13, count 0 2006.285.13:59:23.30#ibcon#read 3, iclass 13, count 0 2006.285.13:59:23.30#ibcon#about to read 4, iclass 13, count 0 2006.285.13:59:23.30#ibcon#read 4, iclass 13, count 0 2006.285.13:59:23.30#ibcon#about to read 5, iclass 13, count 0 2006.285.13:59:23.30#ibcon#read 5, iclass 13, count 0 2006.285.13:59:23.30#ibcon#about to read 6, iclass 13, count 0 2006.285.13:59:23.30#ibcon#read 6, iclass 13, count 0 2006.285.13:59:23.30#ibcon#end of sib2, iclass 13, count 0 2006.285.13:59:23.30#ibcon#*after write, iclass 13, count 0 2006.285.13:59:23.30#ibcon#*before return 0, iclass 13, count 0 2006.285.13:59:23.30#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:59:23.30#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.13:59:23.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.13:59:23.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.13:59:23.30$vck44/vblo=3,649.99 2006.285.13:59:23.30#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.13:59:23.30#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.13:59:23.30#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:23.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:59:23.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:59:23.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:59:23.30#ibcon#enter wrdev, iclass 15, count 0 2006.285.13:59:23.30#ibcon#first serial, iclass 15, count 0 2006.285.13:59:23.30#ibcon#enter sib2, iclass 15, count 0 2006.285.13:59:23.30#ibcon#flushed, iclass 15, count 0 2006.285.13:59:23.30#ibcon#about to write, iclass 15, count 0 2006.285.13:59:23.30#ibcon#wrote, iclass 15, count 0 2006.285.13:59:23.30#ibcon#about to read 3, iclass 15, count 0 2006.285.13:59:23.32#ibcon#read 3, iclass 15, count 0 2006.285.13:59:23.32#ibcon#about to read 4, iclass 15, count 0 2006.285.13:59:23.32#ibcon#read 4, iclass 15, count 0 2006.285.13:59:23.32#ibcon#about to read 5, iclass 15, count 0 2006.285.13:59:23.32#ibcon#read 5, iclass 15, count 0 2006.285.13:59:23.32#ibcon#about to read 6, iclass 15, count 0 2006.285.13:59:23.32#ibcon#read 6, iclass 15, count 0 2006.285.13:59:23.32#ibcon#end of sib2, iclass 15, count 0 2006.285.13:59:23.32#ibcon#*mode == 0, iclass 15, count 0 2006.285.13:59:23.32#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.13:59:23.32#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.13:59:23.32#ibcon#*before write, iclass 15, count 0 2006.285.13:59:23.32#ibcon#enter sib2, iclass 15, count 0 2006.285.13:59:23.32#ibcon#flushed, iclass 15, count 0 2006.285.13:59:23.32#ibcon#about to write, iclass 15, count 0 2006.285.13:59:23.32#ibcon#wrote, iclass 15, count 0 2006.285.13:59:23.32#ibcon#about to read 3, iclass 15, count 0 2006.285.13:59:23.36#ibcon#read 3, iclass 15, count 0 2006.285.13:59:23.36#ibcon#about to read 4, iclass 15, count 0 2006.285.13:59:23.36#ibcon#read 4, iclass 15, count 0 2006.285.13:59:23.36#ibcon#about to read 5, iclass 15, count 0 2006.285.13:59:23.36#ibcon#read 5, iclass 15, count 0 2006.285.13:59:23.36#ibcon#about to read 6, iclass 15, count 0 2006.285.13:59:23.36#ibcon#read 6, iclass 15, count 0 2006.285.13:59:23.36#ibcon#end of sib2, iclass 15, count 0 2006.285.13:59:23.36#ibcon#*after write, iclass 15, count 0 2006.285.13:59:23.36#ibcon#*before return 0, iclass 15, count 0 2006.285.13:59:23.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:59:23.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.13:59:23.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.13:59:23.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.13:59:23.36$vck44/vb=3,4 2006.285.13:59:23.36#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.13:59:23.36#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.13:59:23.36#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:23.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:59:23.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:59:23.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:59:23.42#ibcon#enter wrdev, iclass 17, count 2 2006.285.13:59:23.42#ibcon#first serial, iclass 17, count 2 2006.285.13:59:23.42#ibcon#enter sib2, iclass 17, count 2 2006.285.13:59:23.42#ibcon#flushed, iclass 17, count 2 2006.285.13:59:23.42#ibcon#about to write, iclass 17, count 2 2006.285.13:59:23.42#ibcon#wrote, iclass 17, count 2 2006.285.13:59:23.42#ibcon#about to read 3, iclass 17, count 2 2006.285.13:59:23.44#ibcon#read 3, iclass 17, count 2 2006.285.13:59:23.44#ibcon#about to read 4, iclass 17, count 2 2006.285.13:59:23.44#ibcon#read 4, iclass 17, count 2 2006.285.13:59:23.44#ibcon#about to read 5, iclass 17, count 2 2006.285.13:59:23.44#ibcon#read 5, iclass 17, count 2 2006.285.13:59:23.44#ibcon#about to read 6, iclass 17, count 2 2006.285.13:59:23.44#ibcon#read 6, iclass 17, count 2 2006.285.13:59:23.44#ibcon#end of sib2, iclass 17, count 2 2006.285.13:59:23.44#ibcon#*mode == 0, iclass 17, count 2 2006.285.13:59:23.44#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.13:59:23.44#ibcon#[27=AT03-04\r\n] 2006.285.13:59:23.44#ibcon#*before write, iclass 17, count 2 2006.285.13:59:23.44#ibcon#enter sib2, iclass 17, count 2 2006.285.13:59:23.44#ibcon#flushed, iclass 17, count 2 2006.285.13:59:23.44#ibcon#about to write, iclass 17, count 2 2006.285.13:59:23.44#ibcon#wrote, iclass 17, count 2 2006.285.13:59:23.44#ibcon#about to read 3, iclass 17, count 2 2006.285.13:59:23.47#ibcon#read 3, iclass 17, count 2 2006.285.13:59:23.47#ibcon#about to read 4, iclass 17, count 2 2006.285.13:59:23.47#ibcon#read 4, iclass 17, count 2 2006.285.13:59:23.47#ibcon#about to read 5, iclass 17, count 2 2006.285.13:59:23.47#ibcon#read 5, iclass 17, count 2 2006.285.13:59:23.47#ibcon#about to read 6, iclass 17, count 2 2006.285.13:59:23.47#ibcon#read 6, iclass 17, count 2 2006.285.13:59:23.47#ibcon#end of sib2, iclass 17, count 2 2006.285.13:59:23.47#ibcon#*after write, iclass 17, count 2 2006.285.13:59:23.47#ibcon#*before return 0, iclass 17, count 2 2006.285.13:59:23.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:59:23.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.13:59:23.47#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.13:59:23.47#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:23.47#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:59:23.48#abcon#<5=/04 1.5 3.2 19.05 971015.2\r\n> 2006.285.13:59:23.50#abcon#{5=INTERFACE CLEAR} 2006.285.13:59:23.56#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:59:23.59#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:59:23.59#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:59:23.59#ibcon#enter wrdev, iclass 17, count 0 2006.285.13:59:23.59#ibcon#first serial, iclass 17, count 0 2006.285.13:59:23.59#ibcon#enter sib2, iclass 17, count 0 2006.285.13:59:23.59#ibcon#flushed, iclass 17, count 0 2006.285.13:59:23.59#ibcon#about to write, iclass 17, count 0 2006.285.13:59:23.59#ibcon#wrote, iclass 17, count 0 2006.285.13:59:23.59#ibcon#about to read 3, iclass 17, count 0 2006.285.13:59:23.61#ibcon#read 3, iclass 17, count 0 2006.285.13:59:23.85#ibcon#about to read 4, iclass 17, count 0 2006.285.13:59:23.85#ibcon#read 4, iclass 17, count 0 2006.285.13:59:23.85#ibcon#about to read 5, iclass 17, count 0 2006.285.13:59:23.85#ibcon#read 5, iclass 17, count 0 2006.285.13:59:23.85#ibcon#about to read 6, iclass 17, count 0 2006.285.13:59:23.85#ibcon#read 6, iclass 17, count 0 2006.285.13:59:23.85#ibcon#end of sib2, iclass 17, count 0 2006.285.13:59:23.85#ibcon#*mode == 0, iclass 17, count 0 2006.285.13:59:23.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.13:59:23.85#ibcon#[27=USB\r\n] 2006.285.13:59:23.85#ibcon#*before write, iclass 17, count 0 2006.285.13:59:23.85#ibcon#enter sib2, iclass 17, count 0 2006.285.13:59:23.85#ibcon#flushed, iclass 17, count 0 2006.285.13:59:23.85#ibcon#about to write, iclass 17, count 0 2006.285.13:59:23.85#ibcon#wrote, iclass 17, count 0 2006.285.13:59:23.85#ibcon#about to read 3, iclass 17, count 0 2006.285.13:59:23.88#ibcon#read 3, iclass 17, count 0 2006.285.13:59:23.88#ibcon#about to read 4, iclass 17, count 0 2006.285.13:59:23.88#ibcon#read 4, iclass 17, count 0 2006.285.13:59:23.88#ibcon#about to read 5, iclass 17, count 0 2006.285.13:59:23.88#ibcon#read 5, iclass 17, count 0 2006.285.13:59:23.88#ibcon#about to read 6, iclass 17, count 0 2006.285.13:59:23.88#ibcon#read 6, iclass 17, count 0 2006.285.13:59:23.88#ibcon#end of sib2, iclass 17, count 0 2006.285.13:59:23.88#ibcon#*after write, iclass 17, count 0 2006.285.13:59:23.88#ibcon#*before return 0, iclass 17, count 0 2006.285.13:59:23.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:59:23.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.13:59:23.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.13:59:23.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.13:59:23.88$vck44/vblo=4,679.99 2006.285.13:59:23.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.13:59:23.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.13:59:23.88#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:23.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:59:23.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:59:23.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:59:23.88#ibcon#enter wrdev, iclass 23, count 0 2006.285.13:59:23.88#ibcon#first serial, iclass 23, count 0 2006.285.13:59:23.88#ibcon#enter sib2, iclass 23, count 0 2006.285.13:59:23.88#ibcon#flushed, iclass 23, count 0 2006.285.13:59:23.88#ibcon#about to write, iclass 23, count 0 2006.285.13:59:23.88#ibcon#wrote, iclass 23, count 0 2006.285.13:59:23.88#ibcon#about to read 3, iclass 23, count 0 2006.285.13:59:23.90#ibcon#read 3, iclass 23, count 0 2006.285.13:59:23.90#ibcon#about to read 4, iclass 23, count 0 2006.285.13:59:23.90#ibcon#read 4, iclass 23, count 0 2006.285.13:59:23.90#ibcon#about to read 5, iclass 23, count 0 2006.285.13:59:23.90#ibcon#read 5, iclass 23, count 0 2006.285.13:59:23.90#ibcon#about to read 6, iclass 23, count 0 2006.285.13:59:23.90#ibcon#read 6, iclass 23, count 0 2006.285.13:59:23.90#ibcon#end of sib2, iclass 23, count 0 2006.285.13:59:23.90#ibcon#*mode == 0, iclass 23, count 0 2006.285.13:59:23.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.13:59:23.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.13:59:23.90#ibcon#*before write, iclass 23, count 0 2006.285.13:59:23.90#ibcon#enter sib2, iclass 23, count 0 2006.285.13:59:23.90#ibcon#flushed, iclass 23, count 0 2006.285.13:59:23.90#ibcon#about to write, iclass 23, count 0 2006.285.13:59:23.90#ibcon#wrote, iclass 23, count 0 2006.285.13:59:23.90#ibcon#about to read 3, iclass 23, count 0 2006.285.13:59:23.94#ibcon#read 3, iclass 23, count 0 2006.285.13:59:23.94#ibcon#about to read 4, iclass 23, count 0 2006.285.13:59:23.94#ibcon#read 4, iclass 23, count 0 2006.285.13:59:23.94#ibcon#about to read 5, iclass 23, count 0 2006.285.13:59:23.94#ibcon#read 5, iclass 23, count 0 2006.285.13:59:23.94#ibcon#about to read 6, iclass 23, count 0 2006.285.13:59:23.94#ibcon#read 6, iclass 23, count 0 2006.285.13:59:23.94#ibcon#end of sib2, iclass 23, count 0 2006.285.13:59:23.94#ibcon#*after write, iclass 23, count 0 2006.285.13:59:23.94#ibcon#*before return 0, iclass 23, count 0 2006.285.13:59:23.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:59:23.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.13:59:23.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.13:59:23.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.13:59:23.94$vck44/vb=4,5 2006.285.13:59:23.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.13:59:23.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.13:59:23.94#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:23.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:59:24.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:59:24.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:59:24.00#ibcon#enter wrdev, iclass 25, count 2 2006.285.13:59:24.00#ibcon#first serial, iclass 25, count 2 2006.285.13:59:24.00#ibcon#enter sib2, iclass 25, count 2 2006.285.13:59:24.00#ibcon#flushed, iclass 25, count 2 2006.285.13:59:24.00#ibcon#about to write, iclass 25, count 2 2006.285.13:59:24.00#ibcon#wrote, iclass 25, count 2 2006.285.13:59:24.00#ibcon#about to read 3, iclass 25, count 2 2006.285.13:59:24.02#ibcon#read 3, iclass 25, count 2 2006.285.13:59:24.02#ibcon#about to read 4, iclass 25, count 2 2006.285.13:59:24.02#ibcon#read 4, iclass 25, count 2 2006.285.13:59:24.02#ibcon#about to read 5, iclass 25, count 2 2006.285.13:59:24.02#ibcon#read 5, iclass 25, count 2 2006.285.13:59:24.02#ibcon#about to read 6, iclass 25, count 2 2006.285.13:59:24.02#ibcon#read 6, iclass 25, count 2 2006.285.13:59:24.02#ibcon#end of sib2, iclass 25, count 2 2006.285.13:59:24.02#ibcon#*mode == 0, iclass 25, count 2 2006.285.13:59:24.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.13:59:24.02#ibcon#[27=AT04-05\r\n] 2006.285.13:59:24.02#ibcon#*before write, iclass 25, count 2 2006.285.13:59:24.02#ibcon#enter sib2, iclass 25, count 2 2006.285.13:59:24.02#ibcon#flushed, iclass 25, count 2 2006.285.13:59:24.02#ibcon#about to write, iclass 25, count 2 2006.285.13:59:24.02#ibcon#wrote, iclass 25, count 2 2006.285.13:59:24.02#ibcon#about to read 3, iclass 25, count 2 2006.285.13:59:24.05#ibcon#read 3, iclass 25, count 2 2006.285.13:59:24.05#ibcon#about to read 4, iclass 25, count 2 2006.285.13:59:24.05#ibcon#read 4, iclass 25, count 2 2006.285.13:59:24.05#ibcon#about to read 5, iclass 25, count 2 2006.285.13:59:24.05#ibcon#read 5, iclass 25, count 2 2006.285.13:59:24.05#ibcon#about to read 6, iclass 25, count 2 2006.285.13:59:24.05#ibcon#read 6, iclass 25, count 2 2006.285.13:59:24.05#ibcon#end of sib2, iclass 25, count 2 2006.285.13:59:24.05#ibcon#*after write, iclass 25, count 2 2006.285.13:59:24.05#ibcon#*before return 0, iclass 25, count 2 2006.285.13:59:24.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:59:24.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.13:59:24.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.13:59:24.05#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:24.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:59:24.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:59:24.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:59:24.17#ibcon#enter wrdev, iclass 25, count 0 2006.285.13:59:24.17#ibcon#first serial, iclass 25, count 0 2006.285.13:59:24.17#ibcon#enter sib2, iclass 25, count 0 2006.285.13:59:24.17#ibcon#flushed, iclass 25, count 0 2006.285.13:59:24.17#ibcon#about to write, iclass 25, count 0 2006.285.13:59:24.17#ibcon#wrote, iclass 25, count 0 2006.285.13:59:24.17#ibcon#about to read 3, iclass 25, count 0 2006.285.13:59:24.19#ibcon#read 3, iclass 25, count 0 2006.285.13:59:24.19#ibcon#about to read 4, iclass 25, count 0 2006.285.13:59:24.19#ibcon#read 4, iclass 25, count 0 2006.285.13:59:24.19#ibcon#about to read 5, iclass 25, count 0 2006.285.13:59:24.19#ibcon#read 5, iclass 25, count 0 2006.285.13:59:24.19#ibcon#about to read 6, iclass 25, count 0 2006.285.13:59:24.19#ibcon#read 6, iclass 25, count 0 2006.285.13:59:24.19#ibcon#end of sib2, iclass 25, count 0 2006.285.13:59:24.19#ibcon#*mode == 0, iclass 25, count 0 2006.285.13:59:24.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.13:59:24.19#ibcon#[27=USB\r\n] 2006.285.13:59:24.19#ibcon#*before write, iclass 25, count 0 2006.285.13:59:24.19#ibcon#enter sib2, iclass 25, count 0 2006.285.13:59:24.19#ibcon#flushed, iclass 25, count 0 2006.285.13:59:24.19#ibcon#about to write, iclass 25, count 0 2006.285.13:59:24.19#ibcon#wrote, iclass 25, count 0 2006.285.13:59:24.19#ibcon#about to read 3, iclass 25, count 0 2006.285.13:59:24.22#ibcon#read 3, iclass 25, count 0 2006.285.13:59:24.22#ibcon#about to read 4, iclass 25, count 0 2006.285.13:59:24.22#ibcon#read 4, iclass 25, count 0 2006.285.13:59:24.22#ibcon#about to read 5, iclass 25, count 0 2006.285.13:59:24.22#ibcon#read 5, iclass 25, count 0 2006.285.13:59:24.22#ibcon#about to read 6, iclass 25, count 0 2006.285.13:59:24.22#ibcon#read 6, iclass 25, count 0 2006.285.13:59:24.22#ibcon#end of sib2, iclass 25, count 0 2006.285.13:59:24.22#ibcon#*after write, iclass 25, count 0 2006.285.13:59:24.22#ibcon#*before return 0, iclass 25, count 0 2006.285.13:59:24.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:59:24.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.13:59:24.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.13:59:24.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.13:59:24.22$vck44/vblo=5,709.99 2006.285.13:59:24.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.13:59:24.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.13:59:24.22#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:24.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:59:24.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:59:24.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:59:24.22#ibcon#enter wrdev, iclass 27, count 0 2006.285.13:59:24.22#ibcon#first serial, iclass 27, count 0 2006.285.13:59:24.22#ibcon#enter sib2, iclass 27, count 0 2006.285.13:59:24.22#ibcon#flushed, iclass 27, count 0 2006.285.13:59:24.22#ibcon#about to write, iclass 27, count 0 2006.285.13:59:24.22#ibcon#wrote, iclass 27, count 0 2006.285.13:59:24.22#ibcon#about to read 3, iclass 27, count 0 2006.285.13:59:24.24#ibcon#read 3, iclass 27, count 0 2006.285.13:59:24.24#ibcon#about to read 4, iclass 27, count 0 2006.285.13:59:24.24#ibcon#read 4, iclass 27, count 0 2006.285.13:59:24.24#ibcon#about to read 5, iclass 27, count 0 2006.285.13:59:24.24#ibcon#read 5, iclass 27, count 0 2006.285.13:59:24.24#ibcon#about to read 6, iclass 27, count 0 2006.285.13:59:24.24#ibcon#read 6, iclass 27, count 0 2006.285.13:59:24.24#ibcon#end of sib2, iclass 27, count 0 2006.285.13:59:24.24#ibcon#*mode == 0, iclass 27, count 0 2006.285.13:59:24.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.13:59:24.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.13:59:24.24#ibcon#*before write, iclass 27, count 0 2006.285.13:59:24.24#ibcon#enter sib2, iclass 27, count 0 2006.285.13:59:24.24#ibcon#flushed, iclass 27, count 0 2006.285.13:59:24.24#ibcon#about to write, iclass 27, count 0 2006.285.13:59:24.24#ibcon#wrote, iclass 27, count 0 2006.285.13:59:24.24#ibcon#about to read 3, iclass 27, count 0 2006.285.13:59:24.28#ibcon#read 3, iclass 27, count 0 2006.285.13:59:24.28#ibcon#about to read 4, iclass 27, count 0 2006.285.13:59:24.28#ibcon#read 4, iclass 27, count 0 2006.285.13:59:24.28#ibcon#about to read 5, iclass 27, count 0 2006.285.13:59:24.28#ibcon#read 5, iclass 27, count 0 2006.285.13:59:24.28#ibcon#about to read 6, iclass 27, count 0 2006.285.13:59:24.28#ibcon#read 6, iclass 27, count 0 2006.285.13:59:24.28#ibcon#end of sib2, iclass 27, count 0 2006.285.13:59:24.28#ibcon#*after write, iclass 27, count 0 2006.285.13:59:24.28#ibcon#*before return 0, iclass 27, count 0 2006.285.13:59:24.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:59:24.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.13:59:24.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.13:59:24.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.13:59:24.28$vck44/vb=5,4 2006.285.13:59:24.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.13:59:24.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.13:59:24.28#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:24.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:59:24.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:59:24.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:59:24.34#ibcon#enter wrdev, iclass 29, count 2 2006.285.13:59:24.34#ibcon#first serial, iclass 29, count 2 2006.285.13:59:24.34#ibcon#enter sib2, iclass 29, count 2 2006.285.13:59:24.34#ibcon#flushed, iclass 29, count 2 2006.285.13:59:24.34#ibcon#about to write, iclass 29, count 2 2006.285.13:59:24.34#ibcon#wrote, iclass 29, count 2 2006.285.13:59:24.34#ibcon#about to read 3, iclass 29, count 2 2006.285.13:59:24.36#ibcon#read 3, iclass 29, count 2 2006.285.13:59:24.36#ibcon#about to read 4, iclass 29, count 2 2006.285.13:59:24.36#ibcon#read 4, iclass 29, count 2 2006.285.13:59:24.36#ibcon#about to read 5, iclass 29, count 2 2006.285.13:59:24.36#ibcon#read 5, iclass 29, count 2 2006.285.13:59:24.36#ibcon#about to read 6, iclass 29, count 2 2006.285.13:59:24.36#ibcon#read 6, iclass 29, count 2 2006.285.13:59:24.36#ibcon#end of sib2, iclass 29, count 2 2006.285.13:59:24.36#ibcon#*mode == 0, iclass 29, count 2 2006.285.13:59:24.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.13:59:24.36#ibcon#[27=AT05-04\r\n] 2006.285.13:59:24.36#ibcon#*before write, iclass 29, count 2 2006.285.13:59:24.36#ibcon#enter sib2, iclass 29, count 2 2006.285.13:59:24.36#ibcon#flushed, iclass 29, count 2 2006.285.13:59:24.36#ibcon#about to write, iclass 29, count 2 2006.285.13:59:24.36#ibcon#wrote, iclass 29, count 2 2006.285.13:59:24.36#ibcon#about to read 3, iclass 29, count 2 2006.285.13:59:24.39#ibcon#read 3, iclass 29, count 2 2006.285.13:59:24.39#ibcon#about to read 4, iclass 29, count 2 2006.285.13:59:24.39#ibcon#read 4, iclass 29, count 2 2006.285.13:59:24.39#ibcon#about to read 5, iclass 29, count 2 2006.285.13:59:24.39#ibcon#read 5, iclass 29, count 2 2006.285.13:59:24.39#ibcon#about to read 6, iclass 29, count 2 2006.285.13:59:24.39#ibcon#read 6, iclass 29, count 2 2006.285.13:59:24.39#ibcon#end of sib2, iclass 29, count 2 2006.285.13:59:24.39#ibcon#*after write, iclass 29, count 2 2006.285.13:59:24.39#ibcon#*before return 0, iclass 29, count 2 2006.285.13:59:24.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:59:24.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.13:59:24.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.13:59:24.39#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:24.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:59:24.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:59:24.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:59:24.51#ibcon#enter wrdev, iclass 29, count 0 2006.285.13:59:24.51#ibcon#first serial, iclass 29, count 0 2006.285.13:59:24.51#ibcon#enter sib2, iclass 29, count 0 2006.285.13:59:24.51#ibcon#flushed, iclass 29, count 0 2006.285.13:59:24.51#ibcon#about to write, iclass 29, count 0 2006.285.13:59:24.51#ibcon#wrote, iclass 29, count 0 2006.285.13:59:24.51#ibcon#about to read 3, iclass 29, count 0 2006.285.13:59:24.53#ibcon#read 3, iclass 29, count 0 2006.285.13:59:24.53#ibcon#about to read 4, iclass 29, count 0 2006.285.13:59:24.53#ibcon#read 4, iclass 29, count 0 2006.285.13:59:24.53#ibcon#about to read 5, iclass 29, count 0 2006.285.13:59:24.53#ibcon#read 5, iclass 29, count 0 2006.285.13:59:24.53#ibcon#about to read 6, iclass 29, count 0 2006.285.13:59:24.53#ibcon#read 6, iclass 29, count 0 2006.285.13:59:24.53#ibcon#end of sib2, iclass 29, count 0 2006.285.13:59:24.53#ibcon#*mode == 0, iclass 29, count 0 2006.285.13:59:24.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.13:59:24.53#ibcon#[27=USB\r\n] 2006.285.13:59:24.53#ibcon#*before write, iclass 29, count 0 2006.285.13:59:24.53#ibcon#enter sib2, iclass 29, count 0 2006.285.13:59:24.53#ibcon#flushed, iclass 29, count 0 2006.285.13:59:24.53#ibcon#about to write, iclass 29, count 0 2006.285.13:59:24.53#ibcon#wrote, iclass 29, count 0 2006.285.13:59:24.53#ibcon#about to read 3, iclass 29, count 0 2006.285.13:59:24.56#ibcon#read 3, iclass 29, count 0 2006.285.13:59:24.56#ibcon#about to read 4, iclass 29, count 0 2006.285.13:59:24.56#ibcon#read 4, iclass 29, count 0 2006.285.13:59:24.56#ibcon#about to read 5, iclass 29, count 0 2006.285.13:59:24.56#ibcon#read 5, iclass 29, count 0 2006.285.13:59:24.56#ibcon#about to read 6, iclass 29, count 0 2006.285.13:59:24.56#ibcon#read 6, iclass 29, count 0 2006.285.13:59:24.56#ibcon#end of sib2, iclass 29, count 0 2006.285.13:59:24.56#ibcon#*after write, iclass 29, count 0 2006.285.13:59:24.56#ibcon#*before return 0, iclass 29, count 0 2006.285.13:59:24.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:59:24.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.13:59:24.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.13:59:24.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.13:59:24.56$vck44/vblo=6,719.99 2006.285.13:59:24.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.13:59:24.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.13:59:24.56#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:24.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:59:24.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:59:24.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:59:24.56#ibcon#enter wrdev, iclass 31, count 0 2006.285.13:59:24.56#ibcon#first serial, iclass 31, count 0 2006.285.13:59:24.56#ibcon#enter sib2, iclass 31, count 0 2006.285.13:59:24.56#ibcon#flushed, iclass 31, count 0 2006.285.13:59:24.56#ibcon#about to write, iclass 31, count 0 2006.285.13:59:24.56#ibcon#wrote, iclass 31, count 0 2006.285.13:59:24.56#ibcon#about to read 3, iclass 31, count 0 2006.285.13:59:24.58#ibcon#read 3, iclass 31, count 0 2006.285.13:59:24.68#ibcon#about to read 4, iclass 31, count 0 2006.285.13:59:24.68#ibcon#read 4, iclass 31, count 0 2006.285.13:59:24.68#ibcon#about to read 5, iclass 31, count 0 2006.285.13:59:24.68#ibcon#read 5, iclass 31, count 0 2006.285.13:59:24.68#ibcon#about to read 6, iclass 31, count 0 2006.285.13:59:24.68#ibcon#read 6, iclass 31, count 0 2006.285.13:59:24.68#ibcon#end of sib2, iclass 31, count 0 2006.285.13:59:24.68#ibcon#*mode == 0, iclass 31, count 0 2006.285.13:59:24.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.13:59:24.68#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.13:59:24.68#ibcon#*before write, iclass 31, count 0 2006.285.13:59:24.68#ibcon#enter sib2, iclass 31, count 0 2006.285.13:59:24.68#ibcon#flushed, iclass 31, count 0 2006.285.13:59:24.68#ibcon#about to write, iclass 31, count 0 2006.285.13:59:24.68#ibcon#wrote, iclass 31, count 0 2006.285.13:59:24.68#ibcon#about to read 3, iclass 31, count 0 2006.285.13:59:24.72#ibcon#read 3, iclass 31, count 0 2006.285.13:59:24.72#ibcon#about to read 4, iclass 31, count 0 2006.285.13:59:24.72#ibcon#read 4, iclass 31, count 0 2006.285.13:59:24.72#ibcon#about to read 5, iclass 31, count 0 2006.285.13:59:24.72#ibcon#read 5, iclass 31, count 0 2006.285.13:59:24.72#ibcon#about to read 6, iclass 31, count 0 2006.285.13:59:24.72#ibcon#read 6, iclass 31, count 0 2006.285.13:59:24.72#ibcon#end of sib2, iclass 31, count 0 2006.285.13:59:24.72#ibcon#*after write, iclass 31, count 0 2006.285.13:59:24.72#ibcon#*before return 0, iclass 31, count 0 2006.285.13:59:24.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:59:24.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.13:59:24.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.13:59:24.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.13:59:24.72$vck44/vb=6,3 2006.285.13:59:24.72#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.13:59:24.72#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.13:59:24.72#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:24.72#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:59:24.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:59:24.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:59:24.72#ibcon#enter wrdev, iclass 33, count 2 2006.285.13:59:24.72#ibcon#first serial, iclass 33, count 2 2006.285.13:59:24.72#ibcon#enter sib2, iclass 33, count 2 2006.285.13:59:24.72#ibcon#flushed, iclass 33, count 2 2006.285.13:59:24.72#ibcon#about to write, iclass 33, count 2 2006.285.13:59:24.72#ibcon#wrote, iclass 33, count 2 2006.285.13:59:24.72#ibcon#about to read 3, iclass 33, count 2 2006.285.13:59:24.74#ibcon#read 3, iclass 33, count 2 2006.285.13:59:24.74#ibcon#about to read 4, iclass 33, count 2 2006.285.13:59:24.74#ibcon#read 4, iclass 33, count 2 2006.285.13:59:24.74#ibcon#about to read 5, iclass 33, count 2 2006.285.13:59:24.74#ibcon#read 5, iclass 33, count 2 2006.285.13:59:24.74#ibcon#about to read 6, iclass 33, count 2 2006.285.13:59:24.74#ibcon#read 6, iclass 33, count 2 2006.285.13:59:24.74#ibcon#end of sib2, iclass 33, count 2 2006.285.13:59:24.74#ibcon#*mode == 0, iclass 33, count 2 2006.285.13:59:24.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.13:59:24.74#ibcon#[27=AT06-03\r\n] 2006.285.13:59:24.74#ibcon#*before write, iclass 33, count 2 2006.285.13:59:24.74#ibcon#enter sib2, iclass 33, count 2 2006.285.13:59:24.74#ibcon#flushed, iclass 33, count 2 2006.285.13:59:24.74#ibcon#about to write, iclass 33, count 2 2006.285.13:59:24.74#ibcon#wrote, iclass 33, count 2 2006.285.13:59:24.74#ibcon#about to read 3, iclass 33, count 2 2006.285.13:59:24.77#ibcon#read 3, iclass 33, count 2 2006.285.13:59:24.77#ibcon#about to read 4, iclass 33, count 2 2006.285.13:59:24.77#ibcon#read 4, iclass 33, count 2 2006.285.13:59:24.77#ibcon#about to read 5, iclass 33, count 2 2006.285.13:59:24.77#ibcon#read 5, iclass 33, count 2 2006.285.13:59:24.77#ibcon#about to read 6, iclass 33, count 2 2006.285.13:59:24.77#ibcon#read 6, iclass 33, count 2 2006.285.13:59:24.77#ibcon#end of sib2, iclass 33, count 2 2006.285.13:59:24.77#ibcon#*after write, iclass 33, count 2 2006.285.13:59:24.77#ibcon#*before return 0, iclass 33, count 2 2006.285.13:59:24.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:59:24.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.13:59:24.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.13:59:24.77#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:24.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:59:24.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:59:24.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:59:24.89#ibcon#enter wrdev, iclass 33, count 0 2006.285.13:59:24.89#ibcon#first serial, iclass 33, count 0 2006.285.13:59:24.89#ibcon#enter sib2, iclass 33, count 0 2006.285.13:59:24.89#ibcon#flushed, iclass 33, count 0 2006.285.13:59:24.89#ibcon#about to write, iclass 33, count 0 2006.285.13:59:24.89#ibcon#wrote, iclass 33, count 0 2006.285.13:59:24.89#ibcon#about to read 3, iclass 33, count 0 2006.285.13:59:24.91#ibcon#read 3, iclass 33, count 0 2006.285.13:59:24.91#ibcon#about to read 4, iclass 33, count 0 2006.285.13:59:24.91#ibcon#read 4, iclass 33, count 0 2006.285.13:59:24.91#ibcon#about to read 5, iclass 33, count 0 2006.285.13:59:24.91#ibcon#read 5, iclass 33, count 0 2006.285.13:59:24.91#ibcon#about to read 6, iclass 33, count 0 2006.285.13:59:24.91#ibcon#read 6, iclass 33, count 0 2006.285.13:59:24.91#ibcon#end of sib2, iclass 33, count 0 2006.285.13:59:24.91#ibcon#*mode == 0, iclass 33, count 0 2006.285.13:59:24.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.13:59:24.91#ibcon#[27=USB\r\n] 2006.285.13:59:24.91#ibcon#*before write, iclass 33, count 0 2006.285.13:59:24.91#ibcon#enter sib2, iclass 33, count 0 2006.285.13:59:24.91#ibcon#flushed, iclass 33, count 0 2006.285.13:59:24.91#ibcon#about to write, iclass 33, count 0 2006.285.13:59:24.91#ibcon#wrote, iclass 33, count 0 2006.285.13:59:24.91#ibcon#about to read 3, iclass 33, count 0 2006.285.13:59:24.94#ibcon#read 3, iclass 33, count 0 2006.285.13:59:24.94#ibcon#about to read 4, iclass 33, count 0 2006.285.13:59:24.94#ibcon#read 4, iclass 33, count 0 2006.285.13:59:24.94#ibcon#about to read 5, iclass 33, count 0 2006.285.13:59:24.94#ibcon#read 5, iclass 33, count 0 2006.285.13:59:24.94#ibcon#about to read 6, iclass 33, count 0 2006.285.13:59:24.94#ibcon#read 6, iclass 33, count 0 2006.285.13:59:24.94#ibcon#end of sib2, iclass 33, count 0 2006.285.13:59:24.94#ibcon#*after write, iclass 33, count 0 2006.285.13:59:24.94#ibcon#*before return 0, iclass 33, count 0 2006.285.13:59:24.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:59:24.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.13:59:24.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.13:59:24.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.13:59:24.94$vck44/vblo=7,734.99 2006.285.13:59:24.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.13:59:24.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.13:59:24.94#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:24.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:59:24.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:59:24.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:59:24.94#ibcon#enter wrdev, iclass 35, count 0 2006.285.13:59:24.94#ibcon#first serial, iclass 35, count 0 2006.285.13:59:24.94#ibcon#enter sib2, iclass 35, count 0 2006.285.13:59:24.94#ibcon#flushed, iclass 35, count 0 2006.285.13:59:24.94#ibcon#about to write, iclass 35, count 0 2006.285.13:59:24.94#ibcon#wrote, iclass 35, count 0 2006.285.13:59:24.94#ibcon#about to read 3, iclass 35, count 0 2006.285.13:59:24.96#ibcon#read 3, iclass 35, count 0 2006.285.13:59:24.96#ibcon#about to read 4, iclass 35, count 0 2006.285.13:59:24.96#ibcon#read 4, iclass 35, count 0 2006.285.13:59:24.96#ibcon#about to read 5, iclass 35, count 0 2006.285.13:59:24.96#ibcon#read 5, iclass 35, count 0 2006.285.13:59:24.96#ibcon#about to read 6, iclass 35, count 0 2006.285.13:59:24.96#ibcon#read 6, iclass 35, count 0 2006.285.13:59:24.96#ibcon#end of sib2, iclass 35, count 0 2006.285.13:59:24.96#ibcon#*mode == 0, iclass 35, count 0 2006.285.13:59:24.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.13:59:24.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.13:59:24.96#ibcon#*before write, iclass 35, count 0 2006.285.13:59:24.96#ibcon#enter sib2, iclass 35, count 0 2006.285.13:59:24.96#ibcon#flushed, iclass 35, count 0 2006.285.13:59:24.96#ibcon#about to write, iclass 35, count 0 2006.285.13:59:24.96#ibcon#wrote, iclass 35, count 0 2006.285.13:59:24.96#ibcon#about to read 3, iclass 35, count 0 2006.285.13:59:25.00#ibcon#read 3, iclass 35, count 0 2006.285.13:59:25.00#ibcon#about to read 4, iclass 35, count 0 2006.285.13:59:25.00#ibcon#read 4, iclass 35, count 0 2006.285.13:59:25.00#ibcon#about to read 5, iclass 35, count 0 2006.285.13:59:25.00#ibcon#read 5, iclass 35, count 0 2006.285.13:59:25.00#ibcon#about to read 6, iclass 35, count 0 2006.285.13:59:25.00#ibcon#read 6, iclass 35, count 0 2006.285.13:59:25.00#ibcon#end of sib2, iclass 35, count 0 2006.285.13:59:25.00#ibcon#*after write, iclass 35, count 0 2006.285.13:59:25.00#ibcon#*before return 0, iclass 35, count 0 2006.285.13:59:25.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:59:25.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.13:59:25.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.13:59:25.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.13:59:25.00$vck44/vb=7,4 2006.285.13:59:25.00#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.13:59:25.00#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.13:59:25.00#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:25.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:59:25.06#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:59:25.06#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:59:25.06#ibcon#enter wrdev, iclass 37, count 2 2006.285.13:59:25.06#ibcon#first serial, iclass 37, count 2 2006.285.13:59:25.06#ibcon#enter sib2, iclass 37, count 2 2006.285.13:59:25.06#ibcon#flushed, iclass 37, count 2 2006.285.13:59:25.06#ibcon#about to write, iclass 37, count 2 2006.285.13:59:25.06#ibcon#wrote, iclass 37, count 2 2006.285.13:59:25.06#ibcon#about to read 3, iclass 37, count 2 2006.285.13:59:25.08#ibcon#read 3, iclass 37, count 2 2006.285.13:59:25.08#ibcon#about to read 4, iclass 37, count 2 2006.285.13:59:25.08#ibcon#read 4, iclass 37, count 2 2006.285.13:59:25.08#ibcon#about to read 5, iclass 37, count 2 2006.285.13:59:25.08#ibcon#read 5, iclass 37, count 2 2006.285.13:59:25.08#ibcon#about to read 6, iclass 37, count 2 2006.285.13:59:25.08#ibcon#read 6, iclass 37, count 2 2006.285.13:59:25.08#ibcon#end of sib2, iclass 37, count 2 2006.285.13:59:25.08#ibcon#*mode == 0, iclass 37, count 2 2006.285.13:59:25.08#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.13:59:25.08#ibcon#[27=AT07-04\r\n] 2006.285.13:59:25.08#ibcon#*before write, iclass 37, count 2 2006.285.13:59:25.08#ibcon#enter sib2, iclass 37, count 2 2006.285.13:59:25.08#ibcon#flushed, iclass 37, count 2 2006.285.13:59:25.08#ibcon#about to write, iclass 37, count 2 2006.285.13:59:25.08#ibcon#wrote, iclass 37, count 2 2006.285.13:59:25.08#ibcon#about to read 3, iclass 37, count 2 2006.285.13:59:25.11#ibcon#read 3, iclass 37, count 2 2006.285.13:59:25.11#ibcon#about to read 4, iclass 37, count 2 2006.285.13:59:25.11#ibcon#read 4, iclass 37, count 2 2006.285.13:59:25.11#ibcon#about to read 5, iclass 37, count 2 2006.285.13:59:25.11#ibcon#read 5, iclass 37, count 2 2006.285.13:59:25.11#ibcon#about to read 6, iclass 37, count 2 2006.285.13:59:25.11#ibcon#read 6, iclass 37, count 2 2006.285.13:59:25.11#ibcon#end of sib2, iclass 37, count 2 2006.285.13:59:25.11#ibcon#*after write, iclass 37, count 2 2006.285.13:59:25.11#ibcon#*before return 0, iclass 37, count 2 2006.285.13:59:25.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:59:25.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.13:59:25.11#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.13:59:25.11#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:25.11#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:59:25.23#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:59:25.23#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:59:25.23#ibcon#enter wrdev, iclass 37, count 0 2006.285.13:59:25.23#ibcon#first serial, iclass 37, count 0 2006.285.13:59:25.23#ibcon#enter sib2, iclass 37, count 0 2006.285.13:59:25.23#ibcon#flushed, iclass 37, count 0 2006.285.13:59:25.23#ibcon#about to write, iclass 37, count 0 2006.285.13:59:25.23#ibcon#wrote, iclass 37, count 0 2006.285.13:59:25.23#ibcon#about to read 3, iclass 37, count 0 2006.285.13:59:25.25#ibcon#read 3, iclass 37, count 0 2006.285.13:59:25.25#ibcon#about to read 4, iclass 37, count 0 2006.285.13:59:25.25#ibcon#read 4, iclass 37, count 0 2006.285.13:59:25.25#ibcon#about to read 5, iclass 37, count 0 2006.285.13:59:25.25#ibcon#read 5, iclass 37, count 0 2006.285.13:59:25.25#ibcon#about to read 6, iclass 37, count 0 2006.285.13:59:25.25#ibcon#read 6, iclass 37, count 0 2006.285.13:59:25.25#ibcon#end of sib2, iclass 37, count 0 2006.285.13:59:25.25#ibcon#*mode == 0, iclass 37, count 0 2006.285.13:59:25.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.13:59:25.25#ibcon#[27=USB\r\n] 2006.285.13:59:25.25#ibcon#*before write, iclass 37, count 0 2006.285.13:59:25.25#ibcon#enter sib2, iclass 37, count 0 2006.285.13:59:25.25#ibcon#flushed, iclass 37, count 0 2006.285.13:59:25.25#ibcon#about to write, iclass 37, count 0 2006.285.13:59:25.25#ibcon#wrote, iclass 37, count 0 2006.285.13:59:25.25#ibcon#about to read 3, iclass 37, count 0 2006.285.13:59:25.28#ibcon#read 3, iclass 37, count 0 2006.285.13:59:25.28#ibcon#about to read 4, iclass 37, count 0 2006.285.13:59:25.28#ibcon#read 4, iclass 37, count 0 2006.285.13:59:25.28#ibcon#about to read 5, iclass 37, count 0 2006.285.13:59:25.28#ibcon#read 5, iclass 37, count 0 2006.285.13:59:25.28#ibcon#about to read 6, iclass 37, count 0 2006.285.13:59:25.28#ibcon#read 6, iclass 37, count 0 2006.285.13:59:25.28#ibcon#end of sib2, iclass 37, count 0 2006.285.13:59:25.28#ibcon#*after write, iclass 37, count 0 2006.285.13:59:25.28#ibcon#*before return 0, iclass 37, count 0 2006.285.13:59:25.28#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:59:25.28#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.13:59:25.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.13:59:25.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.13:59:25.28$vck44/vblo=8,744.99 2006.285.13:59:25.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.13:59:25.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.13:59:25.28#ibcon#ireg 17 cls_cnt 0 2006.285.13:59:25.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:59:25.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:59:25.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:59:25.28#ibcon#enter wrdev, iclass 39, count 0 2006.285.13:59:25.28#ibcon#first serial, iclass 39, count 0 2006.285.13:59:25.28#ibcon#enter sib2, iclass 39, count 0 2006.285.13:59:25.28#ibcon#flushed, iclass 39, count 0 2006.285.13:59:25.28#ibcon#about to write, iclass 39, count 0 2006.285.13:59:25.28#ibcon#wrote, iclass 39, count 0 2006.285.13:59:25.28#ibcon#about to read 3, iclass 39, count 0 2006.285.13:59:25.30#ibcon#read 3, iclass 39, count 0 2006.285.13:59:25.30#ibcon#about to read 4, iclass 39, count 0 2006.285.13:59:25.30#ibcon#read 4, iclass 39, count 0 2006.285.13:59:25.30#ibcon#about to read 5, iclass 39, count 0 2006.285.13:59:25.30#ibcon#read 5, iclass 39, count 0 2006.285.13:59:25.30#ibcon#about to read 6, iclass 39, count 0 2006.285.13:59:25.30#ibcon#read 6, iclass 39, count 0 2006.285.13:59:25.30#ibcon#end of sib2, iclass 39, count 0 2006.285.13:59:25.30#ibcon#*mode == 0, iclass 39, count 0 2006.285.13:59:25.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.13:59:25.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.13:59:25.30#ibcon#*before write, iclass 39, count 0 2006.285.13:59:25.30#ibcon#enter sib2, iclass 39, count 0 2006.285.13:59:25.30#ibcon#flushed, iclass 39, count 0 2006.285.13:59:25.30#ibcon#about to write, iclass 39, count 0 2006.285.13:59:25.30#ibcon#wrote, iclass 39, count 0 2006.285.13:59:25.30#ibcon#about to read 3, iclass 39, count 0 2006.285.13:59:25.34#ibcon#read 3, iclass 39, count 0 2006.285.13:59:25.34#ibcon#about to read 4, iclass 39, count 0 2006.285.13:59:25.34#ibcon#read 4, iclass 39, count 0 2006.285.13:59:25.34#ibcon#about to read 5, iclass 39, count 0 2006.285.13:59:25.34#ibcon#read 5, iclass 39, count 0 2006.285.13:59:25.34#ibcon#about to read 6, iclass 39, count 0 2006.285.13:59:25.34#ibcon#read 6, iclass 39, count 0 2006.285.13:59:25.34#ibcon#end of sib2, iclass 39, count 0 2006.285.13:59:25.34#ibcon#*after write, iclass 39, count 0 2006.285.13:59:25.34#ibcon#*before return 0, iclass 39, count 0 2006.285.13:59:25.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:59:25.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.13:59:25.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.13:59:25.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.13:59:25.34$vck44/vb=8,4 2006.285.13:59:25.34#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.13:59:25.34#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.13:59:25.34#ibcon#ireg 11 cls_cnt 2 2006.285.13:59:25.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:59:25.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:59:25.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:59:25.40#ibcon#enter wrdev, iclass 3, count 2 2006.285.13:59:25.40#ibcon#first serial, iclass 3, count 2 2006.285.13:59:25.40#ibcon#enter sib2, iclass 3, count 2 2006.285.13:59:25.40#ibcon#flushed, iclass 3, count 2 2006.285.13:59:25.40#ibcon#about to write, iclass 3, count 2 2006.285.13:59:25.40#ibcon#wrote, iclass 3, count 2 2006.285.13:59:25.40#ibcon#about to read 3, iclass 3, count 2 2006.285.13:59:25.42#ibcon#read 3, iclass 3, count 2 2006.285.13:59:25.42#ibcon#about to read 4, iclass 3, count 2 2006.285.13:59:25.42#ibcon#read 4, iclass 3, count 2 2006.285.13:59:25.42#ibcon#about to read 5, iclass 3, count 2 2006.285.13:59:25.42#ibcon#read 5, iclass 3, count 2 2006.285.13:59:25.42#ibcon#about to read 6, iclass 3, count 2 2006.285.13:59:25.42#ibcon#read 6, iclass 3, count 2 2006.285.13:59:25.42#ibcon#end of sib2, iclass 3, count 2 2006.285.13:59:25.42#ibcon#*mode == 0, iclass 3, count 2 2006.285.13:59:25.42#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.13:59:25.42#ibcon#[27=AT08-04\r\n] 2006.285.13:59:25.42#ibcon#*before write, iclass 3, count 2 2006.285.13:59:25.42#ibcon#enter sib2, iclass 3, count 2 2006.285.13:59:25.42#ibcon#flushed, iclass 3, count 2 2006.285.13:59:25.42#ibcon#about to write, iclass 3, count 2 2006.285.13:59:25.42#ibcon#wrote, iclass 3, count 2 2006.285.13:59:25.42#ibcon#about to read 3, iclass 3, count 2 2006.285.13:59:25.45#ibcon#read 3, iclass 3, count 2 2006.285.13:59:25.45#ibcon#about to read 4, iclass 3, count 2 2006.285.13:59:25.45#ibcon#read 4, iclass 3, count 2 2006.285.13:59:25.45#ibcon#about to read 5, iclass 3, count 2 2006.285.13:59:25.45#ibcon#read 5, iclass 3, count 2 2006.285.13:59:25.45#ibcon#about to read 6, iclass 3, count 2 2006.285.13:59:25.45#ibcon#read 6, iclass 3, count 2 2006.285.13:59:25.45#ibcon#end of sib2, iclass 3, count 2 2006.285.13:59:25.45#ibcon#*after write, iclass 3, count 2 2006.285.13:59:25.45#ibcon#*before return 0, iclass 3, count 2 2006.285.13:59:25.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:59:25.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.13:59:25.45#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.13:59:25.45#ibcon#ireg 7 cls_cnt 0 2006.285.13:59:25.45#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:59:25.57#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:59:25.57#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:59:25.57#ibcon#enter wrdev, iclass 3, count 0 2006.285.13:59:25.57#ibcon#first serial, iclass 3, count 0 2006.285.13:59:25.57#ibcon#enter sib2, iclass 3, count 0 2006.285.13:59:25.57#ibcon#flushed, iclass 3, count 0 2006.285.13:59:25.57#ibcon#about to write, iclass 3, count 0 2006.285.13:59:25.57#ibcon#wrote, iclass 3, count 0 2006.285.13:59:25.57#ibcon#about to read 3, iclass 3, count 0 2006.285.13:59:25.59#ibcon#read 3, iclass 3, count 0 2006.285.13:59:25.59#ibcon#about to read 4, iclass 3, count 0 2006.285.13:59:25.59#ibcon#read 4, iclass 3, count 0 2006.285.13:59:25.59#ibcon#about to read 5, iclass 3, count 0 2006.285.13:59:25.59#ibcon#read 5, iclass 3, count 0 2006.285.13:59:25.59#ibcon#about to read 6, iclass 3, count 0 2006.285.13:59:25.59#ibcon#read 6, iclass 3, count 0 2006.285.13:59:25.59#ibcon#end of sib2, iclass 3, count 0 2006.285.13:59:25.59#ibcon#*mode == 0, iclass 3, count 0 2006.285.13:59:25.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.13:59:25.59#ibcon#[27=USB\r\n] 2006.285.13:59:25.59#ibcon#*before write, iclass 3, count 0 2006.285.13:59:25.59#ibcon#enter sib2, iclass 3, count 0 2006.285.13:59:25.59#ibcon#flushed, iclass 3, count 0 2006.285.13:59:25.59#ibcon#about to write, iclass 3, count 0 2006.285.13:59:25.59#ibcon#wrote, iclass 3, count 0 2006.285.13:59:25.59#ibcon#about to read 3, iclass 3, count 0 2006.285.13:59:25.62#ibcon#read 3, iclass 3, count 0 2006.285.13:59:25.62#ibcon#about to read 4, iclass 3, count 0 2006.285.13:59:25.62#ibcon#read 4, iclass 3, count 0 2006.285.13:59:25.62#ibcon#about to read 5, iclass 3, count 0 2006.285.13:59:25.62#ibcon#read 5, iclass 3, count 0 2006.285.13:59:25.62#ibcon#about to read 6, iclass 3, count 0 2006.285.13:59:25.62#ibcon#read 6, iclass 3, count 0 2006.285.13:59:25.62#ibcon#end of sib2, iclass 3, count 0 2006.285.13:59:25.62#ibcon#*after write, iclass 3, count 0 2006.285.13:59:25.62#ibcon#*before return 0, iclass 3, count 0 2006.285.13:59:25.62#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:59:25.62#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.13:59:25.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.13:59:25.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.13:59:25.62$vck44/vabw=wide 2006.285.13:59:25.62#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.13:59:25.62#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.13:59:25.62#ibcon#ireg 8 cls_cnt 0 2006.285.13:59:25.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:59:25.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:59:25.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:59:25.62#ibcon#enter wrdev, iclass 5, count 0 2006.285.13:59:25.62#ibcon#first serial, iclass 5, count 0 2006.285.13:59:25.62#ibcon#enter sib2, iclass 5, count 0 2006.285.13:59:25.62#ibcon#flushed, iclass 5, count 0 2006.285.13:59:25.62#ibcon#about to write, iclass 5, count 0 2006.285.13:59:25.62#ibcon#wrote, iclass 5, count 0 2006.285.13:59:25.62#ibcon#about to read 3, iclass 5, count 0 2006.285.13:59:25.64#ibcon#read 3, iclass 5, count 0 2006.285.13:59:25.72#ibcon#about to read 4, iclass 5, count 0 2006.285.13:59:25.72#ibcon#read 4, iclass 5, count 0 2006.285.13:59:25.72#ibcon#about to read 5, iclass 5, count 0 2006.285.13:59:25.72#ibcon#read 5, iclass 5, count 0 2006.285.13:59:25.72#ibcon#about to read 6, iclass 5, count 0 2006.285.13:59:25.72#ibcon#read 6, iclass 5, count 0 2006.285.13:59:25.72#ibcon#end of sib2, iclass 5, count 0 2006.285.13:59:25.72#ibcon#*mode == 0, iclass 5, count 0 2006.285.13:59:25.72#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.13:59:25.72#ibcon#[25=BW32\r\n] 2006.285.13:59:25.72#ibcon#*before write, iclass 5, count 0 2006.285.13:59:25.72#ibcon#enter sib2, iclass 5, count 0 2006.285.13:59:25.72#ibcon#flushed, iclass 5, count 0 2006.285.13:59:25.72#ibcon#about to write, iclass 5, count 0 2006.285.13:59:25.72#ibcon#wrote, iclass 5, count 0 2006.285.13:59:25.72#ibcon#about to read 3, iclass 5, count 0 2006.285.13:59:25.75#ibcon#read 3, iclass 5, count 0 2006.285.13:59:25.75#ibcon#about to read 4, iclass 5, count 0 2006.285.13:59:25.75#ibcon#read 4, iclass 5, count 0 2006.285.13:59:25.75#ibcon#about to read 5, iclass 5, count 0 2006.285.13:59:25.75#ibcon#read 5, iclass 5, count 0 2006.285.13:59:25.75#ibcon#about to read 6, iclass 5, count 0 2006.285.13:59:25.75#ibcon#read 6, iclass 5, count 0 2006.285.13:59:25.75#ibcon#end of sib2, iclass 5, count 0 2006.285.13:59:25.75#ibcon#*after write, iclass 5, count 0 2006.285.13:59:25.75#ibcon#*before return 0, iclass 5, count 0 2006.285.13:59:25.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:59:25.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.13:59:25.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.13:59:25.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.13:59:25.75$vck44/vbbw=wide 2006.285.13:59:25.75#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.13:59:25.75#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.13:59:25.75#ibcon#ireg 8 cls_cnt 0 2006.285.13:59:25.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:59:25.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:59:25.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:59:25.75#ibcon#enter wrdev, iclass 7, count 0 2006.285.13:59:25.75#ibcon#first serial, iclass 7, count 0 2006.285.13:59:25.75#ibcon#enter sib2, iclass 7, count 0 2006.285.13:59:25.75#ibcon#flushed, iclass 7, count 0 2006.285.13:59:25.75#ibcon#about to write, iclass 7, count 0 2006.285.13:59:25.75#ibcon#wrote, iclass 7, count 0 2006.285.13:59:25.75#ibcon#about to read 3, iclass 7, count 0 2006.285.13:59:25.77#ibcon#read 3, iclass 7, count 0 2006.285.13:59:25.77#ibcon#about to read 4, iclass 7, count 0 2006.285.13:59:25.77#ibcon#read 4, iclass 7, count 0 2006.285.13:59:25.77#ibcon#about to read 5, iclass 7, count 0 2006.285.13:59:25.77#ibcon#read 5, iclass 7, count 0 2006.285.13:59:25.77#ibcon#about to read 6, iclass 7, count 0 2006.285.13:59:25.77#ibcon#read 6, iclass 7, count 0 2006.285.13:59:25.77#ibcon#end of sib2, iclass 7, count 0 2006.285.13:59:25.77#ibcon#*mode == 0, iclass 7, count 0 2006.285.13:59:25.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.13:59:25.77#ibcon#[27=BW32\r\n] 2006.285.13:59:25.77#ibcon#*before write, iclass 7, count 0 2006.285.13:59:25.77#ibcon#enter sib2, iclass 7, count 0 2006.285.13:59:25.77#ibcon#flushed, iclass 7, count 0 2006.285.13:59:25.77#ibcon#about to write, iclass 7, count 0 2006.285.13:59:25.77#ibcon#wrote, iclass 7, count 0 2006.285.13:59:25.77#ibcon#about to read 3, iclass 7, count 0 2006.285.13:59:25.80#ibcon#read 3, iclass 7, count 0 2006.285.13:59:25.80#ibcon#about to read 4, iclass 7, count 0 2006.285.13:59:25.80#ibcon#read 4, iclass 7, count 0 2006.285.13:59:25.80#ibcon#about to read 5, iclass 7, count 0 2006.285.13:59:25.80#ibcon#read 5, iclass 7, count 0 2006.285.13:59:25.80#ibcon#about to read 6, iclass 7, count 0 2006.285.13:59:25.80#ibcon#read 6, iclass 7, count 0 2006.285.13:59:25.80#ibcon#end of sib2, iclass 7, count 0 2006.285.13:59:25.80#ibcon#*after write, iclass 7, count 0 2006.285.13:59:25.80#ibcon#*before return 0, iclass 7, count 0 2006.285.13:59:25.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:59:25.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.13:59:25.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.13:59:25.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.13:59:25.80$setupk4/ifdk4 2006.285.13:59:25.80$ifdk4/lo= 2006.285.13:59:25.80$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.13:59:25.80$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.13:59:25.80$ifdk4/patch= 2006.285.13:59:25.80$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.13:59:25.80$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.13:59:25.80$setupk4/!*+20s 2006.285.13:59:33.65#abcon#<5=/04 1.5 3.2 19.05 971015.2\r\n> 2006.285.13:59:33.67#abcon#{5=INTERFACE CLEAR} 2006.285.13:59:33.73#abcon#[5=S1D000X0/0*\r\n] 2006.285.13:59:39.27$setupk4/"tpicd 2006.285.13:59:39.27$setupk4/echo=off 2006.285.13:59:39.27$setupk4/xlog=off 2006.285.13:59:39.27:!2006.285.14:09:35 2006.285.13:59:48.14#trakl#Source acquired 2006.285.13:59:50.14#flagr#flagr/antenna,acquired 2006.285.14:09:35.00:preob 2006.285.14:09:36.14/onsource/TRACKING 2006.285.14:09:36.14:!2006.285.14:09:45 2006.285.14:09:45.00:"tape 2006.285.14:09:45.00:"st=record 2006.285.14:09:45.00:data_valid=on 2006.285.14:09:45.00:midob 2006.285.14:09:45.14/onsource/TRACKING 2006.285.14:09:45.14/wx/19.15,1015.2,96 2006.285.14:09:45.28/cable/+6.5002E-03 2006.285.14:09:46.37/va/01,07,usb,yes,32,34 2006.285.14:09:46.37/va/02,06,usb,yes,32,32 2006.285.14:09:46.37/va/03,07,usb,yes,31,33 2006.285.14:09:46.37/va/04,06,usb,yes,33,34 2006.285.14:09:46.37/va/05,03,usb,yes,32,33 2006.285.14:09:46.37/va/06,04,usb,yes,29,28 2006.285.14:09:46.37/va/07,04,usb,yes,29,30 2006.285.14:09:46.37/va/08,03,usb,yes,30,37 2006.285.14:09:46.60/valo/01,524.99,yes,locked 2006.285.14:09:46.60/valo/02,534.99,yes,locked 2006.285.14:09:46.60/valo/03,564.99,yes,locked 2006.285.14:09:46.60/valo/04,624.99,yes,locked 2006.285.14:09:46.60/valo/05,734.99,yes,locked 2006.285.14:09:46.60/valo/06,814.99,yes,locked 2006.285.14:09:46.60/valo/07,864.99,yes,locked 2006.285.14:09:46.60/valo/08,884.99,yes,locked 2006.285.14:09:47.69/vb/01,04,usb,yes,29,27 2006.285.14:09:47.69/vb/02,05,usb,yes,28,28 2006.285.14:09:47.69/vb/03,04,usb,yes,29,32 2006.285.14:09:47.69/vb/04,05,usb,yes,29,28 2006.285.14:09:47.69/vb/05,04,usb,yes,25,28 2006.285.14:09:47.69/vb/06,03,usb,yes,36,32 2006.285.14:09:47.69/vb/07,04,usb,yes,29,29 2006.285.14:09:47.69/vb/08,04,usb,yes,27,30 2006.285.14:09:47.92/vblo/01,629.99,yes,locked 2006.285.14:09:47.92/vblo/02,634.99,yes,locked 2006.285.14:09:47.92/vblo/03,649.99,yes,locked 2006.285.14:09:47.92/vblo/04,679.99,yes,locked 2006.285.14:09:47.92/vblo/05,709.99,yes,locked 2006.285.14:09:47.92/vblo/06,719.99,yes,locked 2006.285.14:09:47.92/vblo/07,734.99,yes,locked 2006.285.14:09:47.92/vblo/08,744.99,yes,locked 2006.285.14:09:48.07/vabw/8 2006.285.14:09:48.22/vbbw/8 2006.285.14:09:48.42/xfe/off,on,12.2 2006.285.14:09:48.79/ifatt/23,28,28,28 2006.285.14:09:49.08/fmout-gps/S +2.57E-07 2006.285.14:09:49.09:!2006.285.14:12:25 2006.285.14:12:25.00:data_valid=off 2006.285.14:12:25.01:"et 2006.285.14:12:25.01:!+3s 2006.285.14:12:28.02:"tape 2006.285.14:12:28.02:postob 2006.285.14:12:28.14/cable/+6.5002E-03 2006.285.14:12:28.15/wx/19.17,1015.2,96 2006.285.14:12:29.07/fmout-gps/S +2.62E-07 2006.285.14:12:29.08:scan_name=285-1418,jd0610,60 2006.285.14:12:29.08:source=2145+067,214805.46,065738.6,2000.0,ccw 2006.285.14:12:30.14#flagr#flagr/antenna,new-source 2006.285.14:12:30.14:checkk5 2006.285.14:12:30.73/chk_autoobs//k5ts1/ autoobs is running! 2006.285.14:12:31.13/chk_autoobs//k5ts2/ autoobs is running! 2006.285.14:12:31.78/chk_autoobs//k5ts3/ autoobs is running! 2006.285.14:12:32.14/chk_autoobs//k5ts4/ autoobs is running! 2006.285.14:12:32.60/chk_obsdata//k5ts1/T2851409??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.14:12:33.09/chk_obsdata//k5ts2/T2851409??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.14:12:33.60/chk_obsdata//k5ts3/T2851409??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.14:12:34.22/chk_obsdata//k5ts4/T2851409??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.285.14:12:35.07/k5log//k5ts1_log_newline 2006.285.14:12:35.82/k5log//k5ts2_log_newline 2006.285.14:12:36.58/k5log//k5ts3_log_newline 2006.285.14:12:37.37/k5log//k5ts4_log_newline 2006.285.14:12:37.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.14:12:37.39:setupk4=1 2006.285.14:12:37.39$setupk4/echo=on 2006.285.14:12:37.39$setupk4/pcalon 2006.285.14:12:37.39$pcalon/"no phase cal control is implemented here 2006.285.14:12:37.39$setupk4/"tpicd=stop 2006.285.14:12:37.39$setupk4/"rec=synch_on 2006.285.14:12:37.39$setupk4/"rec_mode=128 2006.285.14:12:37.39$setupk4/!* 2006.285.14:12:37.39$setupk4/recpk4 2006.285.14:12:37.39$recpk4/recpatch= 2006.285.14:12:37.40$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.14:12:37.40$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.14:12:37.40$setupk4/vck44 2006.285.14:12:37.40$vck44/valo=1,524.99 2006.285.14:12:37.40#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.14:12:37.40#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.14:12:37.40#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:37.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:12:37.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:12:37.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:12:37.40#ibcon#enter wrdev, iclass 29, count 0 2006.285.14:12:37.40#ibcon#first serial, iclass 29, count 0 2006.285.14:12:37.40#ibcon#enter sib2, iclass 29, count 0 2006.285.14:12:37.40#ibcon#flushed, iclass 29, count 0 2006.285.14:12:37.40#ibcon#about to write, iclass 29, count 0 2006.285.14:12:37.40#ibcon#wrote, iclass 29, count 0 2006.285.14:12:37.40#ibcon#about to read 3, iclass 29, count 0 2006.285.14:12:37.41#ibcon#read 3, iclass 29, count 0 2006.285.14:12:37.41#ibcon#about to read 4, iclass 29, count 0 2006.285.14:12:37.41#ibcon#read 4, iclass 29, count 0 2006.285.14:12:37.41#ibcon#about to read 5, iclass 29, count 0 2006.285.14:12:37.41#ibcon#read 5, iclass 29, count 0 2006.285.14:12:37.41#ibcon#about to read 6, iclass 29, count 0 2006.285.14:12:37.41#ibcon#read 6, iclass 29, count 0 2006.285.14:12:37.41#ibcon#end of sib2, iclass 29, count 0 2006.285.14:12:37.41#ibcon#*mode == 0, iclass 29, count 0 2006.285.14:12:37.41#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.14:12:37.41#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.14:12:37.41#ibcon#*before write, iclass 29, count 0 2006.285.14:12:37.41#ibcon#enter sib2, iclass 29, count 0 2006.285.14:12:37.41#ibcon#flushed, iclass 29, count 0 2006.285.14:12:37.41#ibcon#about to write, iclass 29, count 0 2006.285.14:12:37.41#ibcon#wrote, iclass 29, count 0 2006.285.14:12:37.41#ibcon#about to read 3, iclass 29, count 0 2006.285.14:12:37.46#ibcon#read 3, iclass 29, count 0 2006.285.14:12:37.46#ibcon#about to read 4, iclass 29, count 0 2006.285.14:12:37.46#ibcon#read 4, iclass 29, count 0 2006.285.14:12:37.46#ibcon#about to read 5, iclass 29, count 0 2006.285.14:12:37.46#ibcon#read 5, iclass 29, count 0 2006.285.14:12:37.46#ibcon#about to read 6, iclass 29, count 0 2006.285.14:12:37.46#ibcon#read 6, iclass 29, count 0 2006.285.14:12:37.46#ibcon#end of sib2, iclass 29, count 0 2006.285.14:12:37.46#ibcon#*after write, iclass 29, count 0 2006.285.14:12:37.46#ibcon#*before return 0, iclass 29, count 0 2006.285.14:12:37.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:12:37.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:12:37.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.14:12:37.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.14:12:37.47$vck44/va=1,7 2006.285.14:12:37.47#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.14:12:37.47#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.14:12:37.47#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:37.47#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:12:37.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:12:37.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:12:37.47#ibcon#enter wrdev, iclass 31, count 2 2006.285.14:12:37.47#ibcon#first serial, iclass 31, count 2 2006.285.14:12:37.47#ibcon#enter sib2, iclass 31, count 2 2006.285.14:12:37.47#ibcon#flushed, iclass 31, count 2 2006.285.14:12:37.47#ibcon#about to write, iclass 31, count 2 2006.285.14:12:37.47#ibcon#wrote, iclass 31, count 2 2006.285.14:12:37.47#ibcon#about to read 3, iclass 31, count 2 2006.285.14:12:37.48#ibcon#read 3, iclass 31, count 2 2006.285.14:12:37.48#ibcon#about to read 4, iclass 31, count 2 2006.285.14:12:37.48#ibcon#read 4, iclass 31, count 2 2006.285.14:12:37.48#ibcon#about to read 5, iclass 31, count 2 2006.285.14:12:37.48#ibcon#read 5, iclass 31, count 2 2006.285.14:12:37.48#ibcon#about to read 6, iclass 31, count 2 2006.285.14:12:37.48#ibcon#read 6, iclass 31, count 2 2006.285.14:12:37.48#ibcon#end of sib2, iclass 31, count 2 2006.285.14:12:37.48#ibcon#*mode == 0, iclass 31, count 2 2006.285.14:12:37.48#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.14:12:37.48#ibcon#[25=AT01-07\r\n] 2006.285.14:12:37.48#ibcon#*before write, iclass 31, count 2 2006.285.14:12:37.48#ibcon#enter sib2, iclass 31, count 2 2006.285.14:12:37.48#ibcon#flushed, iclass 31, count 2 2006.285.14:12:37.48#ibcon#about to write, iclass 31, count 2 2006.285.14:12:37.48#ibcon#wrote, iclass 31, count 2 2006.285.14:12:37.48#ibcon#about to read 3, iclass 31, count 2 2006.285.14:12:37.51#ibcon#read 3, iclass 31, count 2 2006.285.14:12:37.51#ibcon#about to read 4, iclass 31, count 2 2006.285.14:12:37.51#ibcon#read 4, iclass 31, count 2 2006.285.14:12:37.51#ibcon#about to read 5, iclass 31, count 2 2006.285.14:12:37.51#ibcon#read 5, iclass 31, count 2 2006.285.14:12:37.51#ibcon#about to read 6, iclass 31, count 2 2006.285.14:12:37.51#ibcon#read 6, iclass 31, count 2 2006.285.14:12:37.51#ibcon#end of sib2, iclass 31, count 2 2006.285.14:12:37.51#ibcon#*after write, iclass 31, count 2 2006.285.14:12:37.51#ibcon#*before return 0, iclass 31, count 2 2006.285.14:12:37.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:12:37.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:12:37.51#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.14:12:37.51#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:37.51#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:12:37.63#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:12:37.63#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:12:37.63#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:12:37.63#ibcon#first serial, iclass 31, count 0 2006.285.14:12:37.63#ibcon#enter sib2, iclass 31, count 0 2006.285.14:12:37.63#ibcon#flushed, iclass 31, count 0 2006.285.14:12:37.63#ibcon#about to write, iclass 31, count 0 2006.285.14:12:37.63#ibcon#wrote, iclass 31, count 0 2006.285.14:12:37.63#ibcon#about to read 3, iclass 31, count 0 2006.285.14:12:37.65#ibcon#read 3, iclass 31, count 0 2006.285.14:12:37.65#ibcon#about to read 4, iclass 31, count 0 2006.285.14:12:37.65#ibcon#read 4, iclass 31, count 0 2006.285.14:12:37.65#ibcon#about to read 5, iclass 31, count 0 2006.285.14:12:37.65#ibcon#read 5, iclass 31, count 0 2006.285.14:12:37.65#ibcon#about to read 6, iclass 31, count 0 2006.285.14:12:37.65#ibcon#read 6, iclass 31, count 0 2006.285.14:12:37.65#ibcon#end of sib2, iclass 31, count 0 2006.285.14:12:37.65#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:12:37.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:12:37.65#ibcon#[25=USB\r\n] 2006.285.14:12:37.65#ibcon#*before write, iclass 31, count 0 2006.285.14:12:37.65#ibcon#enter sib2, iclass 31, count 0 2006.285.14:12:37.65#ibcon#flushed, iclass 31, count 0 2006.285.14:12:37.65#ibcon#about to write, iclass 31, count 0 2006.285.14:12:37.65#ibcon#wrote, iclass 31, count 0 2006.285.14:12:37.65#ibcon#about to read 3, iclass 31, count 0 2006.285.14:12:37.68#ibcon#read 3, iclass 31, count 0 2006.285.14:12:37.68#ibcon#about to read 4, iclass 31, count 0 2006.285.14:12:37.68#ibcon#read 4, iclass 31, count 0 2006.285.14:12:37.68#ibcon#about to read 5, iclass 31, count 0 2006.285.14:12:37.68#ibcon#read 5, iclass 31, count 0 2006.285.14:12:37.68#ibcon#about to read 6, iclass 31, count 0 2006.285.14:12:37.68#ibcon#read 6, iclass 31, count 0 2006.285.14:12:37.68#ibcon#end of sib2, iclass 31, count 0 2006.285.14:12:37.68#ibcon#*after write, iclass 31, count 0 2006.285.14:12:37.68#ibcon#*before return 0, iclass 31, count 0 2006.285.14:12:37.68#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:12:37.68#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:12:37.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:12:37.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:12:37.69$vck44/valo=2,534.99 2006.285.14:12:37.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.14:12:37.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.14:12:37.69#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:37.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:12:37.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:12:37.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:12:37.69#ibcon#enter wrdev, iclass 33, count 0 2006.285.14:12:37.69#ibcon#first serial, iclass 33, count 0 2006.285.14:12:37.69#ibcon#enter sib2, iclass 33, count 0 2006.285.14:12:37.69#ibcon#flushed, iclass 33, count 0 2006.285.14:12:37.69#ibcon#about to write, iclass 33, count 0 2006.285.14:12:37.69#ibcon#wrote, iclass 33, count 0 2006.285.14:12:37.69#ibcon#about to read 3, iclass 33, count 0 2006.285.14:12:37.70#ibcon#read 3, iclass 33, count 0 2006.285.14:12:37.70#ibcon#about to read 4, iclass 33, count 0 2006.285.14:12:37.70#ibcon#read 4, iclass 33, count 0 2006.285.14:12:37.70#ibcon#about to read 5, iclass 33, count 0 2006.285.14:12:37.70#ibcon#read 5, iclass 33, count 0 2006.285.14:12:37.70#ibcon#about to read 6, iclass 33, count 0 2006.285.14:12:37.70#ibcon#read 6, iclass 33, count 0 2006.285.14:12:37.70#ibcon#end of sib2, iclass 33, count 0 2006.285.14:12:37.70#ibcon#*mode == 0, iclass 33, count 0 2006.285.14:12:37.70#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.14:12:37.70#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.14:12:37.70#ibcon#*before write, iclass 33, count 0 2006.285.14:12:37.70#ibcon#enter sib2, iclass 33, count 0 2006.285.14:12:37.70#ibcon#flushed, iclass 33, count 0 2006.285.14:12:37.70#ibcon#about to write, iclass 33, count 0 2006.285.14:12:37.70#ibcon#wrote, iclass 33, count 0 2006.285.14:12:37.70#ibcon#about to read 3, iclass 33, count 0 2006.285.14:12:37.74#ibcon#read 3, iclass 33, count 0 2006.285.14:12:37.74#ibcon#about to read 4, iclass 33, count 0 2006.285.14:12:37.74#ibcon#read 4, iclass 33, count 0 2006.285.14:12:37.74#ibcon#about to read 5, iclass 33, count 0 2006.285.14:12:37.74#ibcon#read 5, iclass 33, count 0 2006.285.14:12:37.74#ibcon#about to read 6, iclass 33, count 0 2006.285.14:12:37.74#ibcon#read 6, iclass 33, count 0 2006.285.14:12:37.74#ibcon#end of sib2, iclass 33, count 0 2006.285.14:12:37.74#ibcon#*after write, iclass 33, count 0 2006.285.14:12:37.74#ibcon#*before return 0, iclass 33, count 0 2006.285.14:12:37.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:12:37.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:12:37.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.14:12:37.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.14:12:37.75$vck44/va=2,6 2006.285.14:12:37.75#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.14:12:37.75#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.14:12:37.75#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:37.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:12:37.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:12:37.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:12:37.79#ibcon#enter wrdev, iclass 35, count 2 2006.285.14:12:37.79#ibcon#first serial, iclass 35, count 2 2006.285.14:12:37.79#ibcon#enter sib2, iclass 35, count 2 2006.285.14:12:37.79#ibcon#flushed, iclass 35, count 2 2006.285.14:12:37.79#ibcon#about to write, iclass 35, count 2 2006.285.14:12:37.79#ibcon#wrote, iclass 35, count 2 2006.285.14:12:37.79#ibcon#about to read 3, iclass 35, count 2 2006.285.14:12:37.81#ibcon#read 3, iclass 35, count 2 2006.285.14:12:37.81#ibcon#about to read 4, iclass 35, count 2 2006.285.14:12:37.81#ibcon#read 4, iclass 35, count 2 2006.285.14:12:37.81#ibcon#about to read 5, iclass 35, count 2 2006.285.14:12:37.81#ibcon#read 5, iclass 35, count 2 2006.285.14:12:37.81#ibcon#about to read 6, iclass 35, count 2 2006.285.14:12:37.81#ibcon#read 6, iclass 35, count 2 2006.285.14:12:37.81#ibcon#end of sib2, iclass 35, count 2 2006.285.14:12:37.81#ibcon#*mode == 0, iclass 35, count 2 2006.285.14:12:37.81#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.14:12:37.81#ibcon#[25=AT02-06\r\n] 2006.285.14:12:37.81#ibcon#*before write, iclass 35, count 2 2006.285.14:12:37.81#ibcon#enter sib2, iclass 35, count 2 2006.285.14:12:37.81#ibcon#flushed, iclass 35, count 2 2006.285.14:12:37.81#ibcon#about to write, iclass 35, count 2 2006.285.14:12:37.81#ibcon#wrote, iclass 35, count 2 2006.285.14:12:37.81#ibcon#about to read 3, iclass 35, count 2 2006.285.14:12:37.84#ibcon#read 3, iclass 35, count 2 2006.285.14:12:37.84#ibcon#about to read 4, iclass 35, count 2 2006.285.14:12:37.84#ibcon#read 4, iclass 35, count 2 2006.285.14:12:37.84#ibcon#about to read 5, iclass 35, count 2 2006.285.14:12:37.84#ibcon#read 5, iclass 35, count 2 2006.285.14:12:37.84#ibcon#about to read 6, iclass 35, count 2 2006.285.14:12:37.84#ibcon#read 6, iclass 35, count 2 2006.285.14:12:37.84#ibcon#end of sib2, iclass 35, count 2 2006.285.14:12:37.84#ibcon#*after write, iclass 35, count 2 2006.285.14:12:37.84#ibcon#*before return 0, iclass 35, count 2 2006.285.14:12:37.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:12:37.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:12:37.84#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.14:12:37.84#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:37.84#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:12:37.96#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:12:37.96#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:12:37.96#ibcon#enter wrdev, iclass 35, count 0 2006.285.14:12:37.96#ibcon#first serial, iclass 35, count 0 2006.285.14:12:37.96#ibcon#enter sib2, iclass 35, count 0 2006.285.14:12:37.96#ibcon#flushed, iclass 35, count 0 2006.285.14:12:37.96#ibcon#about to write, iclass 35, count 0 2006.285.14:12:37.96#ibcon#wrote, iclass 35, count 0 2006.285.14:12:37.96#ibcon#about to read 3, iclass 35, count 0 2006.285.14:12:37.98#ibcon#read 3, iclass 35, count 0 2006.285.14:12:37.98#ibcon#about to read 4, iclass 35, count 0 2006.285.14:12:37.98#ibcon#read 4, iclass 35, count 0 2006.285.14:12:37.98#ibcon#about to read 5, iclass 35, count 0 2006.285.14:12:37.98#ibcon#read 5, iclass 35, count 0 2006.285.14:12:37.98#ibcon#about to read 6, iclass 35, count 0 2006.285.14:12:37.98#ibcon#read 6, iclass 35, count 0 2006.285.14:12:37.98#ibcon#end of sib2, iclass 35, count 0 2006.285.14:12:37.98#ibcon#*mode == 0, iclass 35, count 0 2006.285.14:12:37.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.14:12:37.98#ibcon#[25=USB\r\n] 2006.285.14:12:37.98#ibcon#*before write, iclass 35, count 0 2006.285.14:12:37.98#ibcon#enter sib2, iclass 35, count 0 2006.285.14:12:37.98#ibcon#flushed, iclass 35, count 0 2006.285.14:12:37.98#ibcon#about to write, iclass 35, count 0 2006.285.14:12:37.98#ibcon#wrote, iclass 35, count 0 2006.285.14:12:37.98#ibcon#about to read 3, iclass 35, count 0 2006.285.14:12:38.01#ibcon#read 3, iclass 35, count 0 2006.285.14:12:38.01#ibcon#about to read 4, iclass 35, count 0 2006.285.14:12:38.01#ibcon#read 4, iclass 35, count 0 2006.285.14:12:38.01#ibcon#about to read 5, iclass 35, count 0 2006.285.14:12:38.01#ibcon#read 5, iclass 35, count 0 2006.285.14:12:38.01#ibcon#about to read 6, iclass 35, count 0 2006.285.14:12:38.01#ibcon#read 6, iclass 35, count 0 2006.285.14:12:38.01#ibcon#end of sib2, iclass 35, count 0 2006.285.14:12:38.01#ibcon#*after write, iclass 35, count 0 2006.285.14:12:38.01#ibcon#*before return 0, iclass 35, count 0 2006.285.14:12:38.01#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:12:38.01#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:12:38.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.14:12:38.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.14:12:38.02$vck44/valo=3,564.99 2006.285.14:12:38.02#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.14:12:38.02#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.14:12:38.02#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:38.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:12:38.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:12:38.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:12:38.02#ibcon#enter wrdev, iclass 37, count 0 2006.285.14:12:38.02#ibcon#first serial, iclass 37, count 0 2006.285.14:12:38.02#ibcon#enter sib2, iclass 37, count 0 2006.285.14:12:38.02#ibcon#flushed, iclass 37, count 0 2006.285.14:12:38.02#ibcon#about to write, iclass 37, count 0 2006.285.14:12:38.02#ibcon#wrote, iclass 37, count 0 2006.285.14:12:38.02#ibcon#about to read 3, iclass 37, count 0 2006.285.14:12:38.03#ibcon#read 3, iclass 37, count 0 2006.285.14:12:38.03#ibcon#about to read 4, iclass 37, count 0 2006.285.14:12:38.03#ibcon#read 4, iclass 37, count 0 2006.285.14:12:38.03#ibcon#about to read 5, iclass 37, count 0 2006.285.14:12:38.03#ibcon#read 5, iclass 37, count 0 2006.285.14:12:38.03#ibcon#about to read 6, iclass 37, count 0 2006.285.14:12:38.03#ibcon#read 6, iclass 37, count 0 2006.285.14:12:38.03#ibcon#end of sib2, iclass 37, count 0 2006.285.14:12:38.03#ibcon#*mode == 0, iclass 37, count 0 2006.285.14:12:38.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.14:12:38.03#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.14:12:38.03#ibcon#*before write, iclass 37, count 0 2006.285.14:12:38.03#ibcon#enter sib2, iclass 37, count 0 2006.285.14:12:38.03#ibcon#flushed, iclass 37, count 0 2006.285.14:12:38.03#ibcon#about to write, iclass 37, count 0 2006.285.14:12:38.03#ibcon#wrote, iclass 37, count 0 2006.285.14:12:38.03#ibcon#about to read 3, iclass 37, count 0 2006.285.14:12:38.07#ibcon#read 3, iclass 37, count 0 2006.285.14:12:38.07#ibcon#about to read 4, iclass 37, count 0 2006.285.14:12:38.07#ibcon#read 4, iclass 37, count 0 2006.285.14:12:38.07#ibcon#about to read 5, iclass 37, count 0 2006.285.14:12:38.07#ibcon#read 5, iclass 37, count 0 2006.285.14:12:38.07#ibcon#about to read 6, iclass 37, count 0 2006.285.14:12:38.07#ibcon#read 6, iclass 37, count 0 2006.285.14:12:38.07#ibcon#end of sib2, iclass 37, count 0 2006.285.14:12:38.07#ibcon#*after write, iclass 37, count 0 2006.285.14:12:38.07#ibcon#*before return 0, iclass 37, count 0 2006.285.14:12:38.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:12:38.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:12:38.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.14:12:38.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.14:12:38.08$vck44/va=3,7 2006.285.14:12:38.08#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.14:12:38.08#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.14:12:38.08#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:38.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:12:38.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:12:38.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:12:38.12#ibcon#enter wrdev, iclass 39, count 2 2006.285.14:12:38.12#ibcon#first serial, iclass 39, count 2 2006.285.14:12:38.12#ibcon#enter sib2, iclass 39, count 2 2006.285.14:12:38.12#ibcon#flushed, iclass 39, count 2 2006.285.14:12:38.12#ibcon#about to write, iclass 39, count 2 2006.285.14:12:38.12#ibcon#wrote, iclass 39, count 2 2006.285.14:12:38.12#ibcon#about to read 3, iclass 39, count 2 2006.285.14:12:38.14#ibcon#read 3, iclass 39, count 2 2006.285.14:12:38.14#ibcon#about to read 4, iclass 39, count 2 2006.285.14:12:38.14#ibcon#read 4, iclass 39, count 2 2006.285.14:12:38.14#ibcon#about to read 5, iclass 39, count 2 2006.285.14:12:38.14#ibcon#read 5, iclass 39, count 2 2006.285.14:12:38.14#ibcon#about to read 6, iclass 39, count 2 2006.285.14:12:38.14#ibcon#read 6, iclass 39, count 2 2006.285.14:12:38.14#ibcon#end of sib2, iclass 39, count 2 2006.285.14:12:38.14#ibcon#*mode == 0, iclass 39, count 2 2006.285.14:12:38.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.14:12:38.14#ibcon#[25=AT03-07\r\n] 2006.285.14:12:38.14#ibcon#*before write, iclass 39, count 2 2006.285.14:12:38.14#ibcon#enter sib2, iclass 39, count 2 2006.285.14:12:38.14#ibcon#flushed, iclass 39, count 2 2006.285.14:12:38.14#ibcon#about to write, iclass 39, count 2 2006.285.14:12:38.14#ibcon#wrote, iclass 39, count 2 2006.285.14:12:38.14#ibcon#about to read 3, iclass 39, count 2 2006.285.14:12:38.17#ibcon#read 3, iclass 39, count 2 2006.285.14:12:38.17#ibcon#about to read 4, iclass 39, count 2 2006.285.14:12:38.17#ibcon#read 4, iclass 39, count 2 2006.285.14:12:38.17#ibcon#about to read 5, iclass 39, count 2 2006.285.14:12:38.17#ibcon#read 5, iclass 39, count 2 2006.285.14:12:38.17#ibcon#about to read 6, iclass 39, count 2 2006.285.14:12:38.17#ibcon#read 6, iclass 39, count 2 2006.285.14:12:38.17#ibcon#end of sib2, iclass 39, count 2 2006.285.14:12:38.17#ibcon#*after write, iclass 39, count 2 2006.285.14:12:38.17#ibcon#*before return 0, iclass 39, count 2 2006.285.14:12:38.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:12:38.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:12:38.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.14:12:38.17#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:38.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:12:38.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:12:38.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:12:38.29#ibcon#enter wrdev, iclass 39, count 0 2006.285.14:12:38.29#ibcon#first serial, iclass 39, count 0 2006.285.14:12:38.29#ibcon#enter sib2, iclass 39, count 0 2006.285.14:12:38.29#ibcon#flushed, iclass 39, count 0 2006.285.14:12:38.29#ibcon#about to write, iclass 39, count 0 2006.285.14:12:38.29#ibcon#wrote, iclass 39, count 0 2006.285.14:12:38.29#ibcon#about to read 3, iclass 39, count 0 2006.285.14:12:38.31#ibcon#read 3, iclass 39, count 0 2006.285.14:12:38.31#ibcon#about to read 4, iclass 39, count 0 2006.285.14:12:38.31#ibcon#read 4, iclass 39, count 0 2006.285.14:12:38.31#ibcon#about to read 5, iclass 39, count 0 2006.285.14:12:38.31#ibcon#read 5, iclass 39, count 0 2006.285.14:12:38.31#ibcon#about to read 6, iclass 39, count 0 2006.285.14:12:38.31#ibcon#read 6, iclass 39, count 0 2006.285.14:12:38.31#ibcon#end of sib2, iclass 39, count 0 2006.285.14:12:38.31#ibcon#*mode == 0, iclass 39, count 0 2006.285.14:12:38.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.14:12:38.31#ibcon#[25=USB\r\n] 2006.285.14:12:38.31#ibcon#*before write, iclass 39, count 0 2006.285.14:12:38.31#ibcon#enter sib2, iclass 39, count 0 2006.285.14:12:38.31#ibcon#flushed, iclass 39, count 0 2006.285.14:12:38.31#ibcon#about to write, iclass 39, count 0 2006.285.14:12:38.31#ibcon#wrote, iclass 39, count 0 2006.285.14:12:38.31#ibcon#about to read 3, iclass 39, count 0 2006.285.14:12:38.34#ibcon#read 3, iclass 39, count 0 2006.285.14:12:38.34#ibcon#about to read 4, iclass 39, count 0 2006.285.14:12:38.34#ibcon#read 4, iclass 39, count 0 2006.285.14:12:38.34#ibcon#about to read 5, iclass 39, count 0 2006.285.14:12:38.34#ibcon#read 5, iclass 39, count 0 2006.285.14:12:38.34#ibcon#about to read 6, iclass 39, count 0 2006.285.14:12:38.34#ibcon#read 6, iclass 39, count 0 2006.285.14:12:38.34#ibcon#end of sib2, iclass 39, count 0 2006.285.14:12:38.34#ibcon#*after write, iclass 39, count 0 2006.285.14:12:38.34#ibcon#*before return 0, iclass 39, count 0 2006.285.14:12:38.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:12:38.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:12:38.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.14:12:38.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.14:12:38.35$vck44/valo=4,624.99 2006.285.14:12:38.35#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.14:12:38.35#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.14:12:38.35#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:38.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:12:38.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:12:38.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:12:38.35#ibcon#enter wrdev, iclass 3, count 0 2006.285.14:12:38.35#ibcon#first serial, iclass 3, count 0 2006.285.14:12:38.35#ibcon#enter sib2, iclass 3, count 0 2006.285.14:12:38.35#ibcon#flushed, iclass 3, count 0 2006.285.14:12:38.35#ibcon#about to write, iclass 3, count 0 2006.285.14:12:38.35#ibcon#wrote, iclass 3, count 0 2006.285.14:12:38.35#ibcon#about to read 3, iclass 3, count 0 2006.285.14:12:38.36#ibcon#read 3, iclass 3, count 0 2006.285.14:12:38.36#ibcon#about to read 4, iclass 3, count 0 2006.285.14:12:38.36#ibcon#read 4, iclass 3, count 0 2006.285.14:12:38.36#ibcon#about to read 5, iclass 3, count 0 2006.285.14:12:39.01#ibcon#read 5, iclass 3, count 0 2006.285.14:12:39.01#ibcon#about to read 6, iclass 3, count 0 2006.285.14:12:39.01#ibcon#read 6, iclass 3, count 0 2006.285.14:12:39.01#ibcon#end of sib2, iclass 3, count 0 2006.285.14:12:39.01#ibcon#*mode == 0, iclass 3, count 0 2006.285.14:12:39.01#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.14:12:39.01#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.14:12:39.01#ibcon#*before write, iclass 3, count 0 2006.285.14:12:39.01#ibcon#enter sib2, iclass 3, count 0 2006.285.14:12:39.01#ibcon#flushed, iclass 3, count 0 2006.285.14:12:39.01#ibcon#about to write, iclass 3, count 0 2006.285.14:12:39.01#ibcon#wrote, iclass 3, count 0 2006.285.14:12:39.01#ibcon#about to read 3, iclass 3, count 0 2006.285.14:12:39.04#ibcon#read 3, iclass 3, count 0 2006.285.14:12:39.04#ibcon#about to read 4, iclass 3, count 0 2006.285.14:12:39.04#ibcon#read 4, iclass 3, count 0 2006.285.14:12:39.04#ibcon#about to read 5, iclass 3, count 0 2006.285.14:12:39.04#ibcon#read 5, iclass 3, count 0 2006.285.14:12:39.04#ibcon#about to read 6, iclass 3, count 0 2006.285.14:12:39.04#ibcon#read 6, iclass 3, count 0 2006.285.14:12:39.04#ibcon#end of sib2, iclass 3, count 0 2006.285.14:12:39.04#ibcon#*after write, iclass 3, count 0 2006.285.14:12:39.04#ibcon#*before return 0, iclass 3, count 0 2006.285.14:12:39.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:12:39.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:12:39.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.14:12:39.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.14:12:39.05$vck44/va=4,6 2006.285.14:12:39.05#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.14:12:39.05#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.14:12:39.05#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:39.05#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:12:39.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:12:39.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:12:39.05#ibcon#enter wrdev, iclass 5, count 2 2006.285.14:12:39.05#ibcon#first serial, iclass 5, count 2 2006.285.14:12:39.05#ibcon#enter sib2, iclass 5, count 2 2006.285.14:12:39.05#ibcon#flushed, iclass 5, count 2 2006.285.14:12:39.05#ibcon#about to write, iclass 5, count 2 2006.285.14:12:39.05#ibcon#wrote, iclass 5, count 2 2006.285.14:12:39.05#ibcon#about to read 3, iclass 5, count 2 2006.285.14:12:39.06#ibcon#read 3, iclass 5, count 2 2006.285.14:12:39.06#ibcon#about to read 4, iclass 5, count 2 2006.285.14:12:39.06#ibcon#read 4, iclass 5, count 2 2006.285.14:12:39.06#ibcon#about to read 5, iclass 5, count 2 2006.285.14:12:39.06#ibcon#read 5, iclass 5, count 2 2006.285.14:12:39.06#ibcon#about to read 6, iclass 5, count 2 2006.285.14:12:39.06#ibcon#read 6, iclass 5, count 2 2006.285.14:12:39.06#ibcon#end of sib2, iclass 5, count 2 2006.285.14:12:39.06#ibcon#*mode == 0, iclass 5, count 2 2006.285.14:12:39.06#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.14:12:39.06#ibcon#[25=AT04-06\r\n] 2006.285.14:12:39.06#ibcon#*before write, iclass 5, count 2 2006.285.14:12:39.06#ibcon#enter sib2, iclass 5, count 2 2006.285.14:12:39.06#ibcon#flushed, iclass 5, count 2 2006.285.14:12:39.06#ibcon#about to write, iclass 5, count 2 2006.285.14:12:39.06#ibcon#wrote, iclass 5, count 2 2006.285.14:12:39.06#ibcon#about to read 3, iclass 5, count 2 2006.285.14:12:39.09#ibcon#read 3, iclass 5, count 2 2006.285.14:12:39.09#ibcon#about to read 4, iclass 5, count 2 2006.285.14:12:39.09#ibcon#read 4, iclass 5, count 2 2006.285.14:12:39.09#ibcon#about to read 5, iclass 5, count 2 2006.285.14:12:39.09#ibcon#read 5, iclass 5, count 2 2006.285.14:12:39.09#ibcon#about to read 6, iclass 5, count 2 2006.285.14:12:39.09#ibcon#read 6, iclass 5, count 2 2006.285.14:12:39.09#ibcon#end of sib2, iclass 5, count 2 2006.285.14:12:39.09#ibcon#*after write, iclass 5, count 2 2006.285.14:12:39.09#ibcon#*before return 0, iclass 5, count 2 2006.285.14:12:39.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:12:39.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:12:39.09#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.14:12:39.09#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:39.09#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:12:39.21#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:12:39.21#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:12:39.21#ibcon#enter wrdev, iclass 5, count 0 2006.285.14:12:39.21#ibcon#first serial, iclass 5, count 0 2006.285.14:12:39.21#ibcon#enter sib2, iclass 5, count 0 2006.285.14:12:39.21#ibcon#flushed, iclass 5, count 0 2006.285.14:12:39.21#ibcon#about to write, iclass 5, count 0 2006.285.14:12:39.21#ibcon#wrote, iclass 5, count 0 2006.285.14:12:39.21#ibcon#about to read 3, iclass 5, count 0 2006.285.14:12:39.23#ibcon#read 3, iclass 5, count 0 2006.285.14:12:39.23#ibcon#about to read 4, iclass 5, count 0 2006.285.14:12:39.23#ibcon#read 4, iclass 5, count 0 2006.285.14:12:39.23#ibcon#about to read 5, iclass 5, count 0 2006.285.14:12:39.23#ibcon#read 5, iclass 5, count 0 2006.285.14:12:39.23#ibcon#about to read 6, iclass 5, count 0 2006.285.14:12:39.23#ibcon#read 6, iclass 5, count 0 2006.285.14:12:39.23#ibcon#end of sib2, iclass 5, count 0 2006.285.14:12:39.23#ibcon#*mode == 0, iclass 5, count 0 2006.285.14:12:39.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.14:12:39.23#ibcon#[25=USB\r\n] 2006.285.14:12:39.23#ibcon#*before write, iclass 5, count 0 2006.285.14:12:39.23#ibcon#enter sib2, iclass 5, count 0 2006.285.14:12:39.23#ibcon#flushed, iclass 5, count 0 2006.285.14:12:39.23#ibcon#about to write, iclass 5, count 0 2006.285.14:12:39.23#ibcon#wrote, iclass 5, count 0 2006.285.14:12:39.23#ibcon#about to read 3, iclass 5, count 0 2006.285.14:12:39.26#ibcon#read 3, iclass 5, count 0 2006.285.14:12:39.26#ibcon#about to read 4, iclass 5, count 0 2006.285.14:12:39.26#ibcon#read 4, iclass 5, count 0 2006.285.14:12:39.26#ibcon#about to read 5, iclass 5, count 0 2006.285.14:12:39.26#ibcon#read 5, iclass 5, count 0 2006.285.14:12:39.26#ibcon#about to read 6, iclass 5, count 0 2006.285.14:12:39.26#ibcon#read 6, iclass 5, count 0 2006.285.14:12:39.26#ibcon#end of sib2, iclass 5, count 0 2006.285.14:12:39.26#ibcon#*after write, iclass 5, count 0 2006.285.14:12:39.26#ibcon#*before return 0, iclass 5, count 0 2006.285.14:12:39.26#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:12:39.26#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:12:39.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.14:12:39.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.14:12:39.27$vck44/valo=5,734.99 2006.285.14:12:39.27#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.14:12:39.27#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.14:12:39.27#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:39.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:12:39.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:12:39.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:12:39.27#ibcon#enter wrdev, iclass 7, count 0 2006.285.14:12:39.27#ibcon#first serial, iclass 7, count 0 2006.285.14:12:39.27#ibcon#enter sib2, iclass 7, count 0 2006.285.14:12:39.27#ibcon#flushed, iclass 7, count 0 2006.285.14:12:39.27#ibcon#about to write, iclass 7, count 0 2006.285.14:12:39.27#ibcon#wrote, iclass 7, count 0 2006.285.14:12:39.27#ibcon#about to read 3, iclass 7, count 0 2006.285.14:12:39.28#ibcon#read 3, iclass 7, count 0 2006.285.14:12:39.28#ibcon#about to read 4, iclass 7, count 0 2006.285.14:12:39.28#ibcon#read 4, iclass 7, count 0 2006.285.14:12:39.28#ibcon#about to read 5, iclass 7, count 0 2006.285.14:12:39.28#ibcon#read 5, iclass 7, count 0 2006.285.14:12:39.28#ibcon#about to read 6, iclass 7, count 0 2006.285.14:12:39.28#ibcon#read 6, iclass 7, count 0 2006.285.14:12:39.28#ibcon#end of sib2, iclass 7, count 0 2006.285.14:12:39.28#ibcon#*mode == 0, iclass 7, count 0 2006.285.14:12:39.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.14:12:39.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.14:12:39.28#ibcon#*before write, iclass 7, count 0 2006.285.14:12:39.28#ibcon#enter sib2, iclass 7, count 0 2006.285.14:12:39.28#ibcon#flushed, iclass 7, count 0 2006.285.14:12:39.28#ibcon#about to write, iclass 7, count 0 2006.285.14:12:39.28#ibcon#wrote, iclass 7, count 0 2006.285.14:12:39.28#ibcon#about to read 3, iclass 7, count 0 2006.285.14:12:39.32#ibcon#read 3, iclass 7, count 0 2006.285.14:12:39.32#ibcon#about to read 4, iclass 7, count 0 2006.285.14:12:39.32#ibcon#read 4, iclass 7, count 0 2006.285.14:12:39.32#ibcon#about to read 5, iclass 7, count 0 2006.285.14:12:39.32#ibcon#read 5, iclass 7, count 0 2006.285.14:12:39.32#ibcon#about to read 6, iclass 7, count 0 2006.285.14:12:39.32#ibcon#read 6, iclass 7, count 0 2006.285.14:12:39.32#ibcon#end of sib2, iclass 7, count 0 2006.285.14:12:39.32#ibcon#*after write, iclass 7, count 0 2006.285.14:12:39.32#ibcon#*before return 0, iclass 7, count 0 2006.285.14:12:39.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:12:39.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:12:39.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.14:12:39.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.14:12:39.33$vck44/va=5,3 2006.285.14:12:39.33#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.14:12:39.33#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.14:12:39.33#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:39.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:12:39.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:12:39.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:12:39.37#ibcon#enter wrdev, iclass 11, count 2 2006.285.14:12:39.37#ibcon#first serial, iclass 11, count 2 2006.285.14:12:39.37#ibcon#enter sib2, iclass 11, count 2 2006.285.14:12:39.37#ibcon#flushed, iclass 11, count 2 2006.285.14:12:39.37#ibcon#about to write, iclass 11, count 2 2006.285.14:12:39.37#ibcon#wrote, iclass 11, count 2 2006.285.14:12:39.37#ibcon#about to read 3, iclass 11, count 2 2006.285.14:12:39.39#ibcon#read 3, iclass 11, count 2 2006.285.14:12:39.39#ibcon#about to read 4, iclass 11, count 2 2006.285.14:12:39.39#ibcon#read 4, iclass 11, count 2 2006.285.14:12:39.39#ibcon#about to read 5, iclass 11, count 2 2006.285.14:12:39.39#ibcon#read 5, iclass 11, count 2 2006.285.14:12:39.39#ibcon#about to read 6, iclass 11, count 2 2006.285.14:12:39.39#ibcon#read 6, iclass 11, count 2 2006.285.14:12:39.39#ibcon#end of sib2, iclass 11, count 2 2006.285.14:12:39.39#ibcon#*mode == 0, iclass 11, count 2 2006.285.14:12:39.39#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.14:12:39.39#ibcon#[25=AT05-03\r\n] 2006.285.14:12:39.39#ibcon#*before write, iclass 11, count 2 2006.285.14:12:39.39#ibcon#enter sib2, iclass 11, count 2 2006.285.14:12:39.39#ibcon#flushed, iclass 11, count 2 2006.285.14:12:39.39#ibcon#about to write, iclass 11, count 2 2006.285.14:12:39.39#ibcon#wrote, iclass 11, count 2 2006.285.14:12:39.39#ibcon#about to read 3, iclass 11, count 2 2006.285.14:12:39.42#ibcon#read 3, iclass 11, count 2 2006.285.14:12:39.78#ibcon#about to read 4, iclass 11, count 2 2006.285.14:12:39.78#ibcon#read 4, iclass 11, count 2 2006.285.14:12:39.78#ibcon#about to read 5, iclass 11, count 2 2006.285.14:12:39.78#ibcon#read 5, iclass 11, count 2 2006.285.14:12:39.78#ibcon#about to read 6, iclass 11, count 2 2006.285.14:12:39.78#ibcon#read 6, iclass 11, count 2 2006.285.14:12:39.78#ibcon#end of sib2, iclass 11, count 2 2006.285.14:12:39.78#ibcon#*after write, iclass 11, count 2 2006.285.14:12:39.78#ibcon#*before return 0, iclass 11, count 2 2006.285.14:12:39.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:12:39.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:12:39.78#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.14:12:39.78#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:39.78#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:12:39.82#abcon#<5=/04 1.9 3.8 19.17 961015.2\r\n> 2006.285.14:12:39.84#abcon#{5=INTERFACE CLEAR} 2006.285.14:12:39.89#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:12:39.89#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:12:39.89#ibcon#enter wrdev, iclass 11, count 0 2006.285.14:12:39.89#ibcon#first serial, iclass 11, count 0 2006.285.14:12:39.89#ibcon#enter sib2, iclass 11, count 0 2006.285.14:12:39.89#ibcon#flushed, iclass 11, count 0 2006.285.14:12:39.89#ibcon#about to write, iclass 11, count 0 2006.285.14:12:39.89#ibcon#wrote, iclass 11, count 0 2006.285.14:12:39.89#ibcon#about to read 3, iclass 11, count 0 2006.285.14:12:39.90#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:12:39.91#ibcon#read 3, iclass 11, count 0 2006.285.14:12:39.91#ibcon#about to read 4, iclass 11, count 0 2006.285.14:12:39.91#ibcon#read 4, iclass 11, count 0 2006.285.14:12:39.91#ibcon#about to read 5, iclass 11, count 0 2006.285.14:12:39.91#ibcon#read 5, iclass 11, count 0 2006.285.14:12:39.91#ibcon#about to read 6, iclass 11, count 0 2006.285.14:12:39.91#ibcon#read 6, iclass 11, count 0 2006.285.14:12:39.91#ibcon#end of sib2, iclass 11, count 0 2006.285.14:12:39.91#ibcon#*mode == 0, iclass 11, count 0 2006.285.14:12:39.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.14:12:39.91#ibcon#[25=USB\r\n] 2006.285.14:12:39.91#ibcon#*before write, iclass 11, count 0 2006.285.14:12:39.91#ibcon#enter sib2, iclass 11, count 0 2006.285.14:12:39.91#ibcon#flushed, iclass 11, count 0 2006.285.14:12:39.91#ibcon#about to write, iclass 11, count 0 2006.285.14:12:39.91#ibcon#wrote, iclass 11, count 0 2006.285.14:12:39.91#ibcon#about to read 3, iclass 11, count 0 2006.285.14:12:39.94#ibcon#read 3, iclass 11, count 0 2006.285.14:12:39.94#ibcon#about to read 4, iclass 11, count 0 2006.285.14:12:39.94#ibcon#read 4, iclass 11, count 0 2006.285.14:12:39.94#ibcon#about to read 5, iclass 11, count 0 2006.285.14:12:39.94#ibcon#read 5, iclass 11, count 0 2006.285.14:12:39.94#ibcon#about to read 6, iclass 11, count 0 2006.285.14:12:39.94#ibcon#read 6, iclass 11, count 0 2006.285.14:12:39.94#ibcon#end of sib2, iclass 11, count 0 2006.285.14:12:39.94#ibcon#*after write, iclass 11, count 0 2006.285.14:12:39.94#ibcon#*before return 0, iclass 11, count 0 2006.285.14:12:39.94#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:12:39.94#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:12:39.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.14:12:39.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.14:12:39.95$vck44/valo=6,814.99 2006.285.14:12:39.95#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.14:12:39.95#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.14:12:39.95#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:39.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:12:39.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:12:39.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:12:39.95#ibcon#enter wrdev, iclass 17, count 0 2006.285.14:12:39.95#ibcon#first serial, iclass 17, count 0 2006.285.14:12:39.95#ibcon#enter sib2, iclass 17, count 0 2006.285.14:12:39.95#ibcon#flushed, iclass 17, count 0 2006.285.14:12:39.95#ibcon#about to write, iclass 17, count 0 2006.285.14:12:39.95#ibcon#wrote, iclass 17, count 0 2006.285.14:12:39.95#ibcon#about to read 3, iclass 17, count 0 2006.285.14:12:39.96#ibcon#read 3, iclass 17, count 0 2006.285.14:12:39.96#ibcon#about to read 4, iclass 17, count 0 2006.285.14:12:39.96#ibcon#read 4, iclass 17, count 0 2006.285.14:12:39.96#ibcon#about to read 5, iclass 17, count 0 2006.285.14:12:39.96#ibcon#read 5, iclass 17, count 0 2006.285.14:12:39.96#ibcon#about to read 6, iclass 17, count 0 2006.285.14:12:39.96#ibcon#read 6, iclass 17, count 0 2006.285.14:12:39.96#ibcon#end of sib2, iclass 17, count 0 2006.285.14:12:39.96#ibcon#*mode == 0, iclass 17, count 0 2006.285.14:12:39.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.14:12:39.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.14:12:39.96#ibcon#*before write, iclass 17, count 0 2006.285.14:12:39.96#ibcon#enter sib2, iclass 17, count 0 2006.285.14:12:39.96#ibcon#flushed, iclass 17, count 0 2006.285.14:12:39.96#ibcon#about to write, iclass 17, count 0 2006.285.14:12:39.96#ibcon#wrote, iclass 17, count 0 2006.285.14:12:39.96#ibcon#about to read 3, iclass 17, count 0 2006.285.14:12:40.00#ibcon#read 3, iclass 17, count 0 2006.285.14:12:40.00#ibcon#about to read 4, iclass 17, count 0 2006.285.14:12:40.00#ibcon#read 4, iclass 17, count 0 2006.285.14:12:40.00#ibcon#about to read 5, iclass 17, count 0 2006.285.14:12:40.00#ibcon#read 5, iclass 17, count 0 2006.285.14:12:40.00#ibcon#about to read 6, iclass 17, count 0 2006.285.14:12:40.00#ibcon#read 6, iclass 17, count 0 2006.285.14:12:40.00#ibcon#end of sib2, iclass 17, count 0 2006.285.14:12:40.00#ibcon#*after write, iclass 17, count 0 2006.285.14:12:40.00#ibcon#*before return 0, iclass 17, count 0 2006.285.14:12:40.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:12:40.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:12:40.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.14:12:40.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.14:12:40.01$vck44/va=6,4 2006.285.14:12:40.01#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.14:12:40.01#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.14:12:40.01#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:40.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:12:40.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:12:40.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:12:40.05#ibcon#enter wrdev, iclass 19, count 2 2006.285.14:12:40.05#ibcon#first serial, iclass 19, count 2 2006.285.14:12:40.05#ibcon#enter sib2, iclass 19, count 2 2006.285.14:12:40.05#ibcon#flushed, iclass 19, count 2 2006.285.14:12:40.05#ibcon#about to write, iclass 19, count 2 2006.285.14:12:40.05#ibcon#wrote, iclass 19, count 2 2006.285.14:12:40.05#ibcon#about to read 3, iclass 19, count 2 2006.285.14:12:40.07#ibcon#read 3, iclass 19, count 2 2006.285.14:12:40.07#ibcon#about to read 4, iclass 19, count 2 2006.285.14:12:40.07#ibcon#read 4, iclass 19, count 2 2006.285.14:12:40.07#ibcon#about to read 5, iclass 19, count 2 2006.285.14:12:40.07#ibcon#read 5, iclass 19, count 2 2006.285.14:12:40.07#ibcon#about to read 6, iclass 19, count 2 2006.285.14:12:40.07#ibcon#read 6, iclass 19, count 2 2006.285.14:12:40.07#ibcon#end of sib2, iclass 19, count 2 2006.285.14:12:40.07#ibcon#*mode == 0, iclass 19, count 2 2006.285.14:12:40.07#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.14:12:40.07#ibcon#[25=AT06-04\r\n] 2006.285.14:12:40.07#ibcon#*before write, iclass 19, count 2 2006.285.14:12:40.07#ibcon#enter sib2, iclass 19, count 2 2006.285.14:12:40.07#ibcon#flushed, iclass 19, count 2 2006.285.14:12:40.07#ibcon#about to write, iclass 19, count 2 2006.285.14:12:40.07#ibcon#wrote, iclass 19, count 2 2006.285.14:12:40.07#ibcon#about to read 3, iclass 19, count 2 2006.285.14:12:40.10#ibcon#read 3, iclass 19, count 2 2006.285.14:12:40.10#ibcon#about to read 4, iclass 19, count 2 2006.285.14:12:40.10#ibcon#read 4, iclass 19, count 2 2006.285.14:12:40.10#ibcon#about to read 5, iclass 19, count 2 2006.285.14:12:40.10#ibcon#read 5, iclass 19, count 2 2006.285.14:12:40.10#ibcon#about to read 6, iclass 19, count 2 2006.285.14:12:40.10#ibcon#read 6, iclass 19, count 2 2006.285.14:12:40.10#ibcon#end of sib2, iclass 19, count 2 2006.285.14:12:40.10#ibcon#*after write, iclass 19, count 2 2006.285.14:12:40.10#ibcon#*before return 0, iclass 19, count 2 2006.285.14:12:40.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:12:40.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:12:40.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.14:12:40.10#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:40.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:12:40.22#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:12:40.22#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:12:40.22#ibcon#enter wrdev, iclass 19, count 0 2006.285.14:12:40.22#ibcon#first serial, iclass 19, count 0 2006.285.14:12:40.22#ibcon#enter sib2, iclass 19, count 0 2006.285.14:12:40.22#ibcon#flushed, iclass 19, count 0 2006.285.14:12:40.22#ibcon#about to write, iclass 19, count 0 2006.285.14:12:40.22#ibcon#wrote, iclass 19, count 0 2006.285.14:12:40.22#ibcon#about to read 3, iclass 19, count 0 2006.285.14:12:40.24#ibcon#read 3, iclass 19, count 0 2006.285.14:12:40.24#ibcon#about to read 4, iclass 19, count 0 2006.285.14:12:40.24#ibcon#read 4, iclass 19, count 0 2006.285.14:12:40.24#ibcon#about to read 5, iclass 19, count 0 2006.285.14:12:40.24#ibcon#read 5, iclass 19, count 0 2006.285.14:12:40.24#ibcon#about to read 6, iclass 19, count 0 2006.285.14:12:40.24#ibcon#read 6, iclass 19, count 0 2006.285.14:12:40.24#ibcon#end of sib2, iclass 19, count 0 2006.285.14:12:40.24#ibcon#*mode == 0, iclass 19, count 0 2006.285.14:12:40.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.14:12:40.24#ibcon#[25=USB\r\n] 2006.285.14:12:40.24#ibcon#*before write, iclass 19, count 0 2006.285.14:12:40.24#ibcon#enter sib2, iclass 19, count 0 2006.285.14:12:40.24#ibcon#flushed, iclass 19, count 0 2006.285.14:12:40.24#ibcon#about to write, iclass 19, count 0 2006.285.14:12:40.24#ibcon#wrote, iclass 19, count 0 2006.285.14:12:40.24#ibcon#about to read 3, iclass 19, count 0 2006.285.14:12:40.27#ibcon#read 3, iclass 19, count 0 2006.285.14:12:40.27#ibcon#about to read 4, iclass 19, count 0 2006.285.14:12:40.27#ibcon#read 4, iclass 19, count 0 2006.285.14:12:40.27#ibcon#about to read 5, iclass 19, count 0 2006.285.14:12:40.27#ibcon#read 5, iclass 19, count 0 2006.285.14:12:40.27#ibcon#about to read 6, iclass 19, count 0 2006.285.14:12:40.27#ibcon#read 6, iclass 19, count 0 2006.285.14:12:40.27#ibcon#end of sib2, iclass 19, count 0 2006.285.14:12:40.27#ibcon#*after write, iclass 19, count 0 2006.285.14:12:40.27#ibcon#*before return 0, iclass 19, count 0 2006.285.14:12:40.27#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:12:40.27#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:12:40.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.14:12:40.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.14:12:40.28$vck44/valo=7,864.99 2006.285.14:12:40.28#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.14:12:40.28#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.14:12:40.28#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:40.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:12:40.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:12:40.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:12:40.28#ibcon#enter wrdev, iclass 21, count 0 2006.285.14:12:40.28#ibcon#first serial, iclass 21, count 0 2006.285.14:12:40.28#ibcon#enter sib2, iclass 21, count 0 2006.285.14:12:40.28#ibcon#flushed, iclass 21, count 0 2006.285.14:12:40.28#ibcon#about to write, iclass 21, count 0 2006.285.14:12:40.28#ibcon#wrote, iclass 21, count 0 2006.285.14:12:40.28#ibcon#about to read 3, iclass 21, count 0 2006.285.14:12:40.29#ibcon#read 3, iclass 21, count 0 2006.285.14:12:40.29#ibcon#about to read 4, iclass 21, count 0 2006.285.14:12:40.29#ibcon#read 4, iclass 21, count 0 2006.285.14:12:40.29#ibcon#about to read 5, iclass 21, count 0 2006.285.14:12:40.29#ibcon#read 5, iclass 21, count 0 2006.285.14:12:40.29#ibcon#about to read 6, iclass 21, count 0 2006.285.14:12:40.29#ibcon#read 6, iclass 21, count 0 2006.285.14:12:40.29#ibcon#end of sib2, iclass 21, count 0 2006.285.14:12:40.29#ibcon#*mode == 0, iclass 21, count 0 2006.285.14:12:40.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.14:12:40.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.14:12:40.29#ibcon#*before write, iclass 21, count 0 2006.285.14:12:40.29#ibcon#enter sib2, iclass 21, count 0 2006.285.14:12:40.29#ibcon#flushed, iclass 21, count 0 2006.285.14:12:40.29#ibcon#about to write, iclass 21, count 0 2006.285.14:12:40.29#ibcon#wrote, iclass 21, count 0 2006.285.14:12:40.29#ibcon#about to read 3, iclass 21, count 0 2006.285.14:12:40.33#ibcon#read 3, iclass 21, count 0 2006.285.14:12:40.33#ibcon#about to read 4, iclass 21, count 0 2006.285.14:12:40.33#ibcon#read 4, iclass 21, count 0 2006.285.14:12:40.33#ibcon#about to read 5, iclass 21, count 0 2006.285.14:12:40.33#ibcon#read 5, iclass 21, count 0 2006.285.14:12:40.33#ibcon#about to read 6, iclass 21, count 0 2006.285.14:12:40.33#ibcon#read 6, iclass 21, count 0 2006.285.14:12:40.33#ibcon#end of sib2, iclass 21, count 0 2006.285.14:12:40.33#ibcon#*after write, iclass 21, count 0 2006.285.14:12:40.33#ibcon#*before return 0, iclass 21, count 0 2006.285.14:12:40.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:12:40.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:12:40.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.14:12:40.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.14:12:40.34$vck44/va=7,4 2006.285.14:12:40.34#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.14:12:40.34#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.14:12:40.34#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:40.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:12:40.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:12:40.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:12:40.38#ibcon#enter wrdev, iclass 23, count 2 2006.285.14:12:40.38#ibcon#first serial, iclass 23, count 2 2006.285.14:12:40.38#ibcon#enter sib2, iclass 23, count 2 2006.285.14:12:40.38#ibcon#flushed, iclass 23, count 2 2006.285.14:12:40.38#ibcon#about to write, iclass 23, count 2 2006.285.14:12:40.38#ibcon#wrote, iclass 23, count 2 2006.285.14:12:40.38#ibcon#about to read 3, iclass 23, count 2 2006.285.14:12:40.40#ibcon#read 3, iclass 23, count 2 2006.285.14:12:40.40#ibcon#about to read 4, iclass 23, count 2 2006.285.14:12:40.40#ibcon#read 4, iclass 23, count 2 2006.285.14:12:40.40#ibcon#about to read 5, iclass 23, count 2 2006.285.14:12:40.40#ibcon#read 5, iclass 23, count 2 2006.285.14:12:40.40#ibcon#about to read 6, iclass 23, count 2 2006.285.14:12:40.40#ibcon#read 6, iclass 23, count 2 2006.285.14:12:40.40#ibcon#end of sib2, iclass 23, count 2 2006.285.14:12:40.40#ibcon#*mode == 0, iclass 23, count 2 2006.285.14:12:40.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.14:12:40.40#ibcon#[25=AT07-04\r\n] 2006.285.14:12:40.40#ibcon#*before write, iclass 23, count 2 2006.285.14:12:40.40#ibcon#enter sib2, iclass 23, count 2 2006.285.14:12:40.40#ibcon#flushed, iclass 23, count 2 2006.285.14:12:40.40#ibcon#about to write, iclass 23, count 2 2006.285.14:12:40.40#ibcon#wrote, iclass 23, count 2 2006.285.14:12:40.40#ibcon#about to read 3, iclass 23, count 2 2006.285.14:12:40.43#ibcon#read 3, iclass 23, count 2 2006.285.14:12:40.43#ibcon#about to read 4, iclass 23, count 2 2006.285.14:12:40.43#ibcon#read 4, iclass 23, count 2 2006.285.14:12:40.43#ibcon#about to read 5, iclass 23, count 2 2006.285.14:12:40.43#ibcon#read 5, iclass 23, count 2 2006.285.14:12:40.43#ibcon#about to read 6, iclass 23, count 2 2006.285.14:12:40.43#ibcon#read 6, iclass 23, count 2 2006.285.14:12:40.43#ibcon#end of sib2, iclass 23, count 2 2006.285.14:12:40.43#ibcon#*after write, iclass 23, count 2 2006.285.14:12:40.43#ibcon#*before return 0, iclass 23, count 2 2006.285.14:12:40.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:12:40.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:12:40.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.14:12:40.43#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:40.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:12:40.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:12:40.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:12:40.72#ibcon#enter wrdev, iclass 23, count 0 2006.285.14:12:40.72#ibcon#first serial, iclass 23, count 0 2006.285.14:12:40.72#ibcon#enter sib2, iclass 23, count 0 2006.285.14:12:40.72#ibcon#flushed, iclass 23, count 0 2006.285.14:12:40.72#ibcon#about to write, iclass 23, count 0 2006.285.14:12:40.72#ibcon#wrote, iclass 23, count 0 2006.285.14:12:40.72#ibcon#about to read 3, iclass 23, count 0 2006.285.14:12:40.73#ibcon#read 3, iclass 23, count 0 2006.285.14:12:40.73#ibcon#about to read 4, iclass 23, count 0 2006.285.14:12:40.73#ibcon#read 4, iclass 23, count 0 2006.285.14:12:40.73#ibcon#about to read 5, iclass 23, count 0 2006.285.14:12:40.73#ibcon#read 5, iclass 23, count 0 2006.285.14:12:40.73#ibcon#about to read 6, iclass 23, count 0 2006.285.14:12:40.73#ibcon#read 6, iclass 23, count 0 2006.285.14:12:40.73#ibcon#end of sib2, iclass 23, count 0 2006.285.14:12:40.73#ibcon#*mode == 0, iclass 23, count 0 2006.285.14:12:40.73#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.14:12:40.73#ibcon#[25=USB\r\n] 2006.285.14:12:40.73#ibcon#*before write, iclass 23, count 0 2006.285.14:12:40.73#ibcon#enter sib2, iclass 23, count 0 2006.285.14:12:40.73#ibcon#flushed, iclass 23, count 0 2006.285.14:12:40.73#ibcon#about to write, iclass 23, count 0 2006.285.14:12:40.73#ibcon#wrote, iclass 23, count 0 2006.285.14:12:40.73#ibcon#about to read 3, iclass 23, count 0 2006.285.14:12:40.76#ibcon#read 3, iclass 23, count 0 2006.285.14:12:40.76#ibcon#about to read 4, iclass 23, count 0 2006.285.14:12:40.76#ibcon#read 4, iclass 23, count 0 2006.285.14:12:40.76#ibcon#about to read 5, iclass 23, count 0 2006.285.14:12:40.76#ibcon#read 5, iclass 23, count 0 2006.285.14:12:40.76#ibcon#about to read 6, iclass 23, count 0 2006.285.14:12:40.76#ibcon#read 6, iclass 23, count 0 2006.285.14:12:40.76#ibcon#end of sib2, iclass 23, count 0 2006.285.14:12:40.76#ibcon#*after write, iclass 23, count 0 2006.285.14:12:40.76#ibcon#*before return 0, iclass 23, count 0 2006.285.14:12:40.76#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:12:40.76#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:12:40.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.14:12:40.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.14:12:40.77$vck44/valo=8,884.99 2006.285.14:12:40.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.14:12:40.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.14:12:40.77#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:40.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:12:40.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:12:40.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:12:40.77#ibcon#enter wrdev, iclass 25, count 0 2006.285.14:12:40.77#ibcon#first serial, iclass 25, count 0 2006.285.14:12:40.77#ibcon#enter sib2, iclass 25, count 0 2006.285.14:12:40.77#ibcon#flushed, iclass 25, count 0 2006.285.14:12:40.77#ibcon#about to write, iclass 25, count 0 2006.285.14:12:40.77#ibcon#wrote, iclass 25, count 0 2006.285.14:12:40.77#ibcon#about to read 3, iclass 25, count 0 2006.285.14:12:40.78#ibcon#read 3, iclass 25, count 0 2006.285.14:12:40.78#ibcon#about to read 4, iclass 25, count 0 2006.285.14:12:40.78#ibcon#read 4, iclass 25, count 0 2006.285.14:12:40.78#ibcon#about to read 5, iclass 25, count 0 2006.285.14:12:40.78#ibcon#read 5, iclass 25, count 0 2006.285.14:12:40.78#ibcon#about to read 6, iclass 25, count 0 2006.285.14:12:40.78#ibcon#read 6, iclass 25, count 0 2006.285.14:12:40.78#ibcon#end of sib2, iclass 25, count 0 2006.285.14:12:40.78#ibcon#*mode == 0, iclass 25, count 0 2006.285.14:12:40.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.14:12:40.78#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.14:12:40.78#ibcon#*before write, iclass 25, count 0 2006.285.14:12:40.78#ibcon#enter sib2, iclass 25, count 0 2006.285.14:12:40.78#ibcon#flushed, iclass 25, count 0 2006.285.14:12:40.78#ibcon#about to write, iclass 25, count 0 2006.285.14:12:40.78#ibcon#wrote, iclass 25, count 0 2006.285.14:12:40.78#ibcon#about to read 3, iclass 25, count 0 2006.285.14:12:40.82#ibcon#read 3, iclass 25, count 0 2006.285.14:12:40.82#ibcon#about to read 4, iclass 25, count 0 2006.285.14:12:40.82#ibcon#read 4, iclass 25, count 0 2006.285.14:12:40.82#ibcon#about to read 5, iclass 25, count 0 2006.285.14:12:40.82#ibcon#read 5, iclass 25, count 0 2006.285.14:12:40.82#ibcon#about to read 6, iclass 25, count 0 2006.285.14:12:40.82#ibcon#read 6, iclass 25, count 0 2006.285.14:12:40.82#ibcon#end of sib2, iclass 25, count 0 2006.285.14:12:40.82#ibcon#*after write, iclass 25, count 0 2006.285.14:12:40.82#ibcon#*before return 0, iclass 25, count 0 2006.285.14:12:40.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:12:40.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:12:40.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.14:12:40.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.14:12:40.83$vck44/va=8,3 2006.285.14:12:40.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.14:12:40.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.14:12:40.83#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:40.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:12:40.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:12:40.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:12:40.87#ibcon#enter wrdev, iclass 27, count 2 2006.285.14:12:40.87#ibcon#first serial, iclass 27, count 2 2006.285.14:12:40.87#ibcon#enter sib2, iclass 27, count 2 2006.285.14:12:40.87#ibcon#flushed, iclass 27, count 2 2006.285.14:12:40.87#ibcon#about to write, iclass 27, count 2 2006.285.14:12:40.87#ibcon#wrote, iclass 27, count 2 2006.285.14:12:40.87#ibcon#about to read 3, iclass 27, count 2 2006.285.14:12:40.89#ibcon#read 3, iclass 27, count 2 2006.285.14:12:40.89#ibcon#about to read 4, iclass 27, count 2 2006.285.14:12:40.89#ibcon#read 4, iclass 27, count 2 2006.285.14:12:40.89#ibcon#about to read 5, iclass 27, count 2 2006.285.14:12:40.89#ibcon#read 5, iclass 27, count 2 2006.285.14:12:40.89#ibcon#about to read 6, iclass 27, count 2 2006.285.14:12:40.89#ibcon#read 6, iclass 27, count 2 2006.285.14:12:40.89#ibcon#end of sib2, iclass 27, count 2 2006.285.14:12:40.89#ibcon#*mode == 0, iclass 27, count 2 2006.285.14:12:40.89#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.14:12:40.89#ibcon#[25=AT08-03\r\n] 2006.285.14:12:40.89#ibcon#*before write, iclass 27, count 2 2006.285.14:12:40.89#ibcon#enter sib2, iclass 27, count 2 2006.285.14:12:40.89#ibcon#flushed, iclass 27, count 2 2006.285.14:12:40.89#ibcon#about to write, iclass 27, count 2 2006.285.14:12:40.89#ibcon#wrote, iclass 27, count 2 2006.285.14:12:40.89#ibcon#about to read 3, iclass 27, count 2 2006.285.14:12:40.92#ibcon#read 3, iclass 27, count 2 2006.285.14:12:40.92#ibcon#about to read 4, iclass 27, count 2 2006.285.14:12:40.92#ibcon#read 4, iclass 27, count 2 2006.285.14:12:40.92#ibcon#about to read 5, iclass 27, count 2 2006.285.14:12:40.92#ibcon#read 5, iclass 27, count 2 2006.285.14:12:40.92#ibcon#about to read 6, iclass 27, count 2 2006.285.14:12:40.92#ibcon#read 6, iclass 27, count 2 2006.285.14:12:40.92#ibcon#end of sib2, iclass 27, count 2 2006.285.14:12:40.92#ibcon#*after write, iclass 27, count 2 2006.285.14:12:40.92#ibcon#*before return 0, iclass 27, count 2 2006.285.14:12:40.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:12:40.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:12:40.92#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.14:12:40.92#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:40.92#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:12:41.04#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:12:41.04#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:12:41.04#ibcon#enter wrdev, iclass 27, count 0 2006.285.14:12:41.04#ibcon#first serial, iclass 27, count 0 2006.285.14:12:41.04#ibcon#enter sib2, iclass 27, count 0 2006.285.14:12:41.04#ibcon#flushed, iclass 27, count 0 2006.285.14:12:41.04#ibcon#about to write, iclass 27, count 0 2006.285.14:12:41.04#ibcon#wrote, iclass 27, count 0 2006.285.14:12:41.04#ibcon#about to read 3, iclass 27, count 0 2006.285.14:12:41.06#ibcon#read 3, iclass 27, count 0 2006.285.14:12:41.06#ibcon#about to read 4, iclass 27, count 0 2006.285.14:12:41.06#ibcon#read 4, iclass 27, count 0 2006.285.14:12:41.06#ibcon#about to read 5, iclass 27, count 0 2006.285.14:12:41.06#ibcon#read 5, iclass 27, count 0 2006.285.14:12:41.06#ibcon#about to read 6, iclass 27, count 0 2006.285.14:12:41.06#ibcon#read 6, iclass 27, count 0 2006.285.14:12:41.06#ibcon#end of sib2, iclass 27, count 0 2006.285.14:12:41.06#ibcon#*mode == 0, iclass 27, count 0 2006.285.14:12:41.06#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.14:12:41.06#ibcon#[25=USB\r\n] 2006.285.14:12:41.06#ibcon#*before write, iclass 27, count 0 2006.285.14:12:41.06#ibcon#enter sib2, iclass 27, count 0 2006.285.14:12:41.06#ibcon#flushed, iclass 27, count 0 2006.285.14:12:41.06#ibcon#about to write, iclass 27, count 0 2006.285.14:12:41.06#ibcon#wrote, iclass 27, count 0 2006.285.14:12:41.06#ibcon#about to read 3, iclass 27, count 0 2006.285.14:12:41.09#ibcon#read 3, iclass 27, count 0 2006.285.14:12:41.09#ibcon#about to read 4, iclass 27, count 0 2006.285.14:12:41.09#ibcon#read 4, iclass 27, count 0 2006.285.14:12:41.09#ibcon#about to read 5, iclass 27, count 0 2006.285.14:12:41.09#ibcon#read 5, iclass 27, count 0 2006.285.14:12:41.09#ibcon#about to read 6, iclass 27, count 0 2006.285.14:12:41.09#ibcon#read 6, iclass 27, count 0 2006.285.14:12:41.09#ibcon#end of sib2, iclass 27, count 0 2006.285.14:12:41.09#ibcon#*after write, iclass 27, count 0 2006.285.14:12:41.09#ibcon#*before return 0, iclass 27, count 0 2006.285.14:12:41.09#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:12:41.09#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:12:41.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.14:12:41.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.14:12:41.10$vck44/vblo=1,629.99 2006.285.14:12:41.10#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.14:12:41.10#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.14:12:41.10#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:41.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:12:41.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:12:41.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:12:41.10#ibcon#enter wrdev, iclass 29, count 0 2006.285.14:12:41.10#ibcon#first serial, iclass 29, count 0 2006.285.14:12:41.10#ibcon#enter sib2, iclass 29, count 0 2006.285.14:12:41.10#ibcon#flushed, iclass 29, count 0 2006.285.14:12:41.10#ibcon#about to write, iclass 29, count 0 2006.285.14:12:41.10#ibcon#wrote, iclass 29, count 0 2006.285.14:12:41.10#ibcon#about to read 3, iclass 29, count 0 2006.285.14:12:41.11#ibcon#read 3, iclass 29, count 0 2006.285.14:12:41.11#ibcon#about to read 4, iclass 29, count 0 2006.285.14:12:41.11#ibcon#read 4, iclass 29, count 0 2006.285.14:12:41.11#ibcon#about to read 5, iclass 29, count 0 2006.285.14:12:41.11#ibcon#read 5, iclass 29, count 0 2006.285.14:12:41.11#ibcon#about to read 6, iclass 29, count 0 2006.285.14:12:41.11#ibcon#read 6, iclass 29, count 0 2006.285.14:12:41.11#ibcon#end of sib2, iclass 29, count 0 2006.285.14:12:41.11#ibcon#*mode == 0, iclass 29, count 0 2006.285.14:12:41.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.14:12:41.11#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.14:12:41.11#ibcon#*before write, iclass 29, count 0 2006.285.14:12:41.11#ibcon#enter sib2, iclass 29, count 0 2006.285.14:12:41.11#ibcon#flushed, iclass 29, count 0 2006.285.14:12:41.11#ibcon#about to write, iclass 29, count 0 2006.285.14:12:41.11#ibcon#wrote, iclass 29, count 0 2006.285.14:12:41.11#ibcon#about to read 3, iclass 29, count 0 2006.285.14:12:41.15#ibcon#read 3, iclass 29, count 0 2006.285.14:12:41.15#ibcon#about to read 4, iclass 29, count 0 2006.285.14:12:41.15#ibcon#read 4, iclass 29, count 0 2006.285.14:12:41.15#ibcon#about to read 5, iclass 29, count 0 2006.285.14:12:41.15#ibcon#read 5, iclass 29, count 0 2006.285.14:12:41.15#ibcon#about to read 6, iclass 29, count 0 2006.285.14:12:41.15#ibcon#read 6, iclass 29, count 0 2006.285.14:12:41.15#ibcon#end of sib2, iclass 29, count 0 2006.285.14:12:41.15#ibcon#*after write, iclass 29, count 0 2006.285.14:12:41.15#ibcon#*before return 0, iclass 29, count 0 2006.285.14:12:41.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:12:41.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:12:41.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.14:12:41.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.14:12:41.16$vck44/vb=1,4 2006.285.14:12:41.16#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.14:12:41.16#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.14:12:41.16#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:41.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:12:41.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:12:41.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:12:41.16#ibcon#enter wrdev, iclass 31, count 2 2006.285.14:12:41.16#ibcon#first serial, iclass 31, count 2 2006.285.14:12:41.16#ibcon#enter sib2, iclass 31, count 2 2006.285.14:12:41.16#ibcon#flushed, iclass 31, count 2 2006.285.14:12:41.16#ibcon#about to write, iclass 31, count 2 2006.285.14:12:41.16#ibcon#wrote, iclass 31, count 2 2006.285.14:12:41.16#ibcon#about to read 3, iclass 31, count 2 2006.285.14:12:41.17#ibcon#read 3, iclass 31, count 2 2006.285.14:12:41.17#ibcon#about to read 4, iclass 31, count 2 2006.285.14:12:41.17#ibcon#read 4, iclass 31, count 2 2006.285.14:12:41.17#ibcon#about to read 5, iclass 31, count 2 2006.285.14:12:41.17#ibcon#read 5, iclass 31, count 2 2006.285.14:12:41.17#ibcon#about to read 6, iclass 31, count 2 2006.285.14:12:41.17#ibcon#read 6, iclass 31, count 2 2006.285.14:12:41.17#ibcon#end of sib2, iclass 31, count 2 2006.285.14:12:41.17#ibcon#*mode == 0, iclass 31, count 2 2006.285.14:12:41.17#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.14:12:41.17#ibcon#[27=AT01-04\r\n] 2006.285.14:12:41.17#ibcon#*before write, iclass 31, count 2 2006.285.14:12:41.17#ibcon#enter sib2, iclass 31, count 2 2006.285.14:12:41.17#ibcon#flushed, iclass 31, count 2 2006.285.14:12:41.17#ibcon#about to write, iclass 31, count 2 2006.285.14:12:41.17#ibcon#wrote, iclass 31, count 2 2006.285.14:12:41.17#ibcon#about to read 3, iclass 31, count 2 2006.285.14:12:41.20#ibcon#read 3, iclass 31, count 2 2006.285.14:12:41.20#ibcon#about to read 4, iclass 31, count 2 2006.285.14:12:41.20#ibcon#read 4, iclass 31, count 2 2006.285.14:12:41.20#ibcon#about to read 5, iclass 31, count 2 2006.285.14:12:41.20#ibcon#read 5, iclass 31, count 2 2006.285.14:12:41.20#ibcon#about to read 6, iclass 31, count 2 2006.285.14:12:41.20#ibcon#read 6, iclass 31, count 2 2006.285.14:12:41.20#ibcon#end of sib2, iclass 31, count 2 2006.285.14:12:41.20#ibcon#*after write, iclass 31, count 2 2006.285.14:12:41.20#ibcon#*before return 0, iclass 31, count 2 2006.285.14:12:41.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:12:41.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:12:41.20#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.14:12:41.20#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:41.20#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:12:41.32#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:12:41.32#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:12:41.32#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:12:41.32#ibcon#first serial, iclass 31, count 0 2006.285.14:12:41.32#ibcon#enter sib2, iclass 31, count 0 2006.285.14:12:41.32#ibcon#flushed, iclass 31, count 0 2006.285.14:12:41.32#ibcon#about to write, iclass 31, count 0 2006.285.14:12:41.32#ibcon#wrote, iclass 31, count 0 2006.285.14:12:41.32#ibcon#about to read 3, iclass 31, count 0 2006.285.14:12:41.34#ibcon#read 3, iclass 31, count 0 2006.285.14:12:41.34#ibcon#about to read 4, iclass 31, count 0 2006.285.14:12:41.34#ibcon#read 4, iclass 31, count 0 2006.285.14:12:41.34#ibcon#about to read 5, iclass 31, count 0 2006.285.14:12:41.34#ibcon#read 5, iclass 31, count 0 2006.285.14:12:41.34#ibcon#about to read 6, iclass 31, count 0 2006.285.14:12:41.34#ibcon#read 6, iclass 31, count 0 2006.285.14:12:41.34#ibcon#end of sib2, iclass 31, count 0 2006.285.14:12:41.34#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:12:41.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:12:41.34#ibcon#[27=USB\r\n] 2006.285.14:12:41.34#ibcon#*before write, iclass 31, count 0 2006.285.14:12:41.34#ibcon#enter sib2, iclass 31, count 0 2006.285.14:12:41.34#ibcon#flushed, iclass 31, count 0 2006.285.14:12:41.34#ibcon#about to write, iclass 31, count 0 2006.285.14:12:41.34#ibcon#wrote, iclass 31, count 0 2006.285.14:12:41.34#ibcon#about to read 3, iclass 31, count 0 2006.285.14:12:41.37#ibcon#read 3, iclass 31, count 0 2006.285.14:12:41.37#ibcon#about to read 4, iclass 31, count 0 2006.285.14:12:41.37#ibcon#read 4, iclass 31, count 0 2006.285.14:12:41.37#ibcon#about to read 5, iclass 31, count 0 2006.285.14:12:41.37#ibcon#read 5, iclass 31, count 0 2006.285.14:12:41.37#ibcon#about to read 6, iclass 31, count 0 2006.285.14:12:41.37#ibcon#read 6, iclass 31, count 0 2006.285.14:12:41.37#ibcon#end of sib2, iclass 31, count 0 2006.285.14:12:41.37#ibcon#*after write, iclass 31, count 0 2006.285.14:12:41.37#ibcon#*before return 0, iclass 31, count 0 2006.285.14:12:41.37#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:12:41.37#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:12:41.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:12:41.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:12:41.38$vck44/vblo=2,634.99 2006.285.14:12:41.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.14:12:41.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.14:12:41.38#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:41.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:12:41.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:12:41.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:12:41.38#ibcon#enter wrdev, iclass 33, count 0 2006.285.14:12:41.38#ibcon#first serial, iclass 33, count 0 2006.285.14:12:41.38#ibcon#enter sib2, iclass 33, count 0 2006.285.14:12:41.38#ibcon#flushed, iclass 33, count 0 2006.285.14:12:41.38#ibcon#about to write, iclass 33, count 0 2006.285.14:12:41.38#ibcon#wrote, iclass 33, count 0 2006.285.14:12:41.38#ibcon#about to read 3, iclass 33, count 0 2006.285.14:12:41.39#ibcon#read 3, iclass 33, count 0 2006.285.14:12:41.39#ibcon#about to read 4, iclass 33, count 0 2006.285.14:12:41.39#ibcon#read 4, iclass 33, count 0 2006.285.14:12:41.39#ibcon#about to read 5, iclass 33, count 0 2006.285.14:12:41.39#ibcon#read 5, iclass 33, count 0 2006.285.14:12:41.39#ibcon#about to read 6, iclass 33, count 0 2006.285.14:12:41.39#ibcon#read 6, iclass 33, count 0 2006.285.14:12:41.39#ibcon#end of sib2, iclass 33, count 0 2006.285.14:12:41.39#ibcon#*mode == 0, iclass 33, count 0 2006.285.14:12:41.39#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.14:12:41.39#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.14:12:41.39#ibcon#*before write, iclass 33, count 0 2006.285.14:12:41.39#ibcon#enter sib2, iclass 33, count 0 2006.285.14:12:41.39#ibcon#flushed, iclass 33, count 0 2006.285.14:12:41.39#ibcon#about to write, iclass 33, count 0 2006.285.14:12:41.39#ibcon#wrote, iclass 33, count 0 2006.285.14:12:41.39#ibcon#about to read 3, iclass 33, count 0 2006.285.14:12:41.43#ibcon#read 3, iclass 33, count 0 2006.285.14:12:41.43#ibcon#about to read 4, iclass 33, count 0 2006.285.14:12:41.43#ibcon#read 4, iclass 33, count 0 2006.285.14:12:41.43#ibcon#about to read 5, iclass 33, count 0 2006.285.14:12:41.43#ibcon#read 5, iclass 33, count 0 2006.285.14:12:41.43#ibcon#about to read 6, iclass 33, count 0 2006.285.14:12:41.43#ibcon#read 6, iclass 33, count 0 2006.285.14:12:41.43#ibcon#end of sib2, iclass 33, count 0 2006.285.14:12:41.43#ibcon#*after write, iclass 33, count 0 2006.285.14:12:41.43#ibcon#*before return 0, iclass 33, count 0 2006.285.14:12:41.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:12:41.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:12:41.43#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.14:12:41.43#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.14:12:41.44$vck44/vb=2,5 2006.285.14:12:41.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.14:12:41.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.14:12:41.72#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:41.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:12:41.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:12:41.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:12:41.72#ibcon#enter wrdev, iclass 35, count 2 2006.285.14:12:41.72#ibcon#first serial, iclass 35, count 2 2006.285.14:12:41.72#ibcon#enter sib2, iclass 35, count 2 2006.285.14:12:41.72#ibcon#flushed, iclass 35, count 2 2006.285.14:12:41.72#ibcon#about to write, iclass 35, count 2 2006.285.14:12:41.72#ibcon#wrote, iclass 35, count 2 2006.285.14:12:41.72#ibcon#about to read 3, iclass 35, count 2 2006.285.14:12:41.73#ibcon#read 3, iclass 35, count 2 2006.285.14:12:41.73#ibcon#about to read 4, iclass 35, count 2 2006.285.14:12:41.73#ibcon#read 4, iclass 35, count 2 2006.285.14:12:41.73#ibcon#about to read 5, iclass 35, count 2 2006.285.14:12:41.73#ibcon#read 5, iclass 35, count 2 2006.285.14:12:41.73#ibcon#about to read 6, iclass 35, count 2 2006.285.14:12:41.73#ibcon#read 6, iclass 35, count 2 2006.285.14:12:41.73#ibcon#end of sib2, iclass 35, count 2 2006.285.14:12:41.73#ibcon#*mode == 0, iclass 35, count 2 2006.285.14:12:41.73#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.14:12:41.73#ibcon#[27=AT02-05\r\n] 2006.285.14:12:41.73#ibcon#*before write, iclass 35, count 2 2006.285.14:12:41.73#ibcon#enter sib2, iclass 35, count 2 2006.285.14:12:41.73#ibcon#flushed, iclass 35, count 2 2006.285.14:12:41.73#ibcon#about to write, iclass 35, count 2 2006.285.14:12:41.73#ibcon#wrote, iclass 35, count 2 2006.285.14:12:41.73#ibcon#about to read 3, iclass 35, count 2 2006.285.14:12:41.76#ibcon#read 3, iclass 35, count 2 2006.285.14:12:41.76#ibcon#about to read 4, iclass 35, count 2 2006.285.14:12:41.76#ibcon#read 4, iclass 35, count 2 2006.285.14:12:41.76#ibcon#about to read 5, iclass 35, count 2 2006.285.14:12:41.76#ibcon#read 5, iclass 35, count 2 2006.285.14:12:41.76#ibcon#about to read 6, iclass 35, count 2 2006.285.14:12:41.76#ibcon#read 6, iclass 35, count 2 2006.285.14:12:41.76#ibcon#end of sib2, iclass 35, count 2 2006.285.14:12:41.76#ibcon#*after write, iclass 35, count 2 2006.285.14:12:41.76#ibcon#*before return 0, iclass 35, count 2 2006.285.14:12:41.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:12:41.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:12:41.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.14:12:41.76#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:41.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:12:41.88#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:12:41.88#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:12:41.88#ibcon#enter wrdev, iclass 35, count 0 2006.285.14:12:41.88#ibcon#first serial, iclass 35, count 0 2006.285.14:12:41.88#ibcon#enter sib2, iclass 35, count 0 2006.285.14:12:41.88#ibcon#flushed, iclass 35, count 0 2006.285.14:12:41.88#ibcon#about to write, iclass 35, count 0 2006.285.14:12:41.88#ibcon#wrote, iclass 35, count 0 2006.285.14:12:41.88#ibcon#about to read 3, iclass 35, count 0 2006.285.14:12:41.90#ibcon#read 3, iclass 35, count 0 2006.285.14:12:41.90#ibcon#about to read 4, iclass 35, count 0 2006.285.14:12:41.90#ibcon#read 4, iclass 35, count 0 2006.285.14:12:41.90#ibcon#about to read 5, iclass 35, count 0 2006.285.14:12:41.90#ibcon#read 5, iclass 35, count 0 2006.285.14:12:41.90#ibcon#about to read 6, iclass 35, count 0 2006.285.14:12:41.90#ibcon#read 6, iclass 35, count 0 2006.285.14:12:41.90#ibcon#end of sib2, iclass 35, count 0 2006.285.14:12:41.90#ibcon#*mode == 0, iclass 35, count 0 2006.285.14:12:41.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.14:12:41.90#ibcon#[27=USB\r\n] 2006.285.14:12:41.90#ibcon#*before write, iclass 35, count 0 2006.285.14:12:41.90#ibcon#enter sib2, iclass 35, count 0 2006.285.14:12:41.90#ibcon#flushed, iclass 35, count 0 2006.285.14:12:41.90#ibcon#about to write, iclass 35, count 0 2006.285.14:12:41.90#ibcon#wrote, iclass 35, count 0 2006.285.14:12:41.90#ibcon#about to read 3, iclass 35, count 0 2006.285.14:12:41.93#ibcon#read 3, iclass 35, count 0 2006.285.14:12:41.93#ibcon#about to read 4, iclass 35, count 0 2006.285.14:12:41.93#ibcon#read 4, iclass 35, count 0 2006.285.14:12:41.93#ibcon#about to read 5, iclass 35, count 0 2006.285.14:12:41.93#ibcon#read 5, iclass 35, count 0 2006.285.14:12:41.93#ibcon#about to read 6, iclass 35, count 0 2006.285.14:12:41.93#ibcon#read 6, iclass 35, count 0 2006.285.14:12:41.93#ibcon#end of sib2, iclass 35, count 0 2006.285.14:12:41.93#ibcon#*after write, iclass 35, count 0 2006.285.14:12:41.93#ibcon#*before return 0, iclass 35, count 0 2006.285.14:12:41.93#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:12:41.93#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:12:41.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.14:12:41.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.14:12:41.94$vck44/vblo=3,649.99 2006.285.14:12:41.94#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.14:12:41.94#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.14:12:41.94#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:41.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:12:41.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:12:41.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:12:41.94#ibcon#enter wrdev, iclass 37, count 0 2006.285.14:12:41.94#ibcon#first serial, iclass 37, count 0 2006.285.14:12:41.94#ibcon#enter sib2, iclass 37, count 0 2006.285.14:12:41.94#ibcon#flushed, iclass 37, count 0 2006.285.14:12:41.94#ibcon#about to write, iclass 37, count 0 2006.285.14:12:41.94#ibcon#wrote, iclass 37, count 0 2006.285.14:12:41.94#ibcon#about to read 3, iclass 37, count 0 2006.285.14:12:41.95#ibcon#read 3, iclass 37, count 0 2006.285.14:12:41.95#ibcon#about to read 4, iclass 37, count 0 2006.285.14:12:41.95#ibcon#read 4, iclass 37, count 0 2006.285.14:12:41.95#ibcon#about to read 5, iclass 37, count 0 2006.285.14:12:41.95#ibcon#read 5, iclass 37, count 0 2006.285.14:12:41.95#ibcon#about to read 6, iclass 37, count 0 2006.285.14:12:41.95#ibcon#read 6, iclass 37, count 0 2006.285.14:12:41.95#ibcon#end of sib2, iclass 37, count 0 2006.285.14:12:41.95#ibcon#*mode == 0, iclass 37, count 0 2006.285.14:12:41.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.14:12:41.95#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.14:12:41.95#ibcon#*before write, iclass 37, count 0 2006.285.14:12:41.95#ibcon#enter sib2, iclass 37, count 0 2006.285.14:12:41.95#ibcon#flushed, iclass 37, count 0 2006.285.14:12:41.95#ibcon#about to write, iclass 37, count 0 2006.285.14:12:41.95#ibcon#wrote, iclass 37, count 0 2006.285.14:12:41.95#ibcon#about to read 3, iclass 37, count 0 2006.285.14:12:41.99#ibcon#read 3, iclass 37, count 0 2006.285.14:12:41.99#ibcon#about to read 4, iclass 37, count 0 2006.285.14:12:41.99#ibcon#read 4, iclass 37, count 0 2006.285.14:12:41.99#ibcon#about to read 5, iclass 37, count 0 2006.285.14:12:41.99#ibcon#read 5, iclass 37, count 0 2006.285.14:12:41.99#ibcon#about to read 6, iclass 37, count 0 2006.285.14:12:41.99#ibcon#read 6, iclass 37, count 0 2006.285.14:12:41.99#ibcon#end of sib2, iclass 37, count 0 2006.285.14:12:41.99#ibcon#*after write, iclass 37, count 0 2006.285.14:12:41.99#ibcon#*before return 0, iclass 37, count 0 2006.285.14:12:41.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:12:41.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:12:41.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.14:12:41.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.14:12:42.00$vck44/vb=3,4 2006.285.14:12:42.00#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.14:12:42.00#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.14:12:42.00#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:42.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:12:42.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:12:42.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:12:42.04#ibcon#enter wrdev, iclass 39, count 2 2006.285.14:12:42.04#ibcon#first serial, iclass 39, count 2 2006.285.14:12:42.04#ibcon#enter sib2, iclass 39, count 2 2006.285.14:12:42.04#ibcon#flushed, iclass 39, count 2 2006.285.14:12:42.04#ibcon#about to write, iclass 39, count 2 2006.285.14:12:42.04#ibcon#wrote, iclass 39, count 2 2006.285.14:12:42.04#ibcon#about to read 3, iclass 39, count 2 2006.285.14:12:42.06#ibcon#read 3, iclass 39, count 2 2006.285.14:12:42.06#ibcon#about to read 4, iclass 39, count 2 2006.285.14:12:42.06#ibcon#read 4, iclass 39, count 2 2006.285.14:12:42.06#ibcon#about to read 5, iclass 39, count 2 2006.285.14:12:42.06#ibcon#read 5, iclass 39, count 2 2006.285.14:12:42.06#ibcon#about to read 6, iclass 39, count 2 2006.285.14:12:42.06#ibcon#read 6, iclass 39, count 2 2006.285.14:12:42.06#ibcon#end of sib2, iclass 39, count 2 2006.285.14:12:42.06#ibcon#*mode == 0, iclass 39, count 2 2006.285.14:12:42.06#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.14:12:42.06#ibcon#[27=AT03-04\r\n] 2006.285.14:12:42.06#ibcon#*before write, iclass 39, count 2 2006.285.14:12:42.06#ibcon#enter sib2, iclass 39, count 2 2006.285.14:12:42.06#ibcon#flushed, iclass 39, count 2 2006.285.14:12:42.06#ibcon#about to write, iclass 39, count 2 2006.285.14:12:42.06#ibcon#wrote, iclass 39, count 2 2006.285.14:12:42.06#ibcon#about to read 3, iclass 39, count 2 2006.285.14:12:42.09#ibcon#read 3, iclass 39, count 2 2006.285.14:12:42.09#ibcon#about to read 4, iclass 39, count 2 2006.285.14:12:42.09#ibcon#read 4, iclass 39, count 2 2006.285.14:12:42.09#ibcon#about to read 5, iclass 39, count 2 2006.285.14:12:42.09#ibcon#read 5, iclass 39, count 2 2006.285.14:12:42.09#ibcon#about to read 6, iclass 39, count 2 2006.285.14:12:42.09#ibcon#read 6, iclass 39, count 2 2006.285.14:12:42.09#ibcon#end of sib2, iclass 39, count 2 2006.285.14:12:42.09#ibcon#*after write, iclass 39, count 2 2006.285.14:12:42.09#ibcon#*before return 0, iclass 39, count 2 2006.285.14:12:42.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:12:42.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:12:42.09#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.14:12:42.09#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:42.09#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:12:42.21#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:12:42.21#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:12:42.21#ibcon#enter wrdev, iclass 39, count 0 2006.285.14:12:42.21#ibcon#first serial, iclass 39, count 0 2006.285.14:12:42.21#ibcon#enter sib2, iclass 39, count 0 2006.285.14:12:42.21#ibcon#flushed, iclass 39, count 0 2006.285.14:12:42.21#ibcon#about to write, iclass 39, count 0 2006.285.14:12:42.21#ibcon#wrote, iclass 39, count 0 2006.285.14:12:42.21#ibcon#about to read 3, iclass 39, count 0 2006.285.14:12:42.23#ibcon#read 3, iclass 39, count 0 2006.285.14:12:42.23#ibcon#about to read 4, iclass 39, count 0 2006.285.14:12:42.23#ibcon#read 4, iclass 39, count 0 2006.285.14:12:42.23#ibcon#about to read 5, iclass 39, count 0 2006.285.14:12:42.23#ibcon#read 5, iclass 39, count 0 2006.285.14:12:42.23#ibcon#about to read 6, iclass 39, count 0 2006.285.14:12:42.23#ibcon#read 6, iclass 39, count 0 2006.285.14:12:42.23#ibcon#end of sib2, iclass 39, count 0 2006.285.14:12:42.23#ibcon#*mode == 0, iclass 39, count 0 2006.285.14:12:42.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.14:12:42.23#ibcon#[27=USB\r\n] 2006.285.14:12:42.23#ibcon#*before write, iclass 39, count 0 2006.285.14:12:42.23#ibcon#enter sib2, iclass 39, count 0 2006.285.14:12:42.23#ibcon#flushed, iclass 39, count 0 2006.285.14:12:42.23#ibcon#about to write, iclass 39, count 0 2006.285.14:12:42.23#ibcon#wrote, iclass 39, count 0 2006.285.14:12:42.23#ibcon#about to read 3, iclass 39, count 0 2006.285.14:12:42.26#ibcon#read 3, iclass 39, count 0 2006.285.14:12:42.26#ibcon#about to read 4, iclass 39, count 0 2006.285.14:12:42.26#ibcon#read 4, iclass 39, count 0 2006.285.14:12:42.26#ibcon#about to read 5, iclass 39, count 0 2006.285.14:12:42.26#ibcon#read 5, iclass 39, count 0 2006.285.14:12:42.26#ibcon#about to read 6, iclass 39, count 0 2006.285.14:12:42.26#ibcon#read 6, iclass 39, count 0 2006.285.14:12:42.26#ibcon#end of sib2, iclass 39, count 0 2006.285.14:12:42.26#ibcon#*after write, iclass 39, count 0 2006.285.14:12:42.26#ibcon#*before return 0, iclass 39, count 0 2006.285.14:12:42.26#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:12:42.26#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:12:42.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.14:12:42.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.14:12:42.27$vck44/vblo=4,679.99 2006.285.14:12:42.27#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.14:12:42.27#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.14:12:42.27#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:42.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:12:42.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:12:42.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:12:42.27#ibcon#enter wrdev, iclass 3, count 0 2006.285.14:12:42.27#ibcon#first serial, iclass 3, count 0 2006.285.14:12:42.27#ibcon#enter sib2, iclass 3, count 0 2006.285.14:12:42.27#ibcon#flushed, iclass 3, count 0 2006.285.14:12:42.27#ibcon#about to write, iclass 3, count 0 2006.285.14:12:42.27#ibcon#wrote, iclass 3, count 0 2006.285.14:12:42.27#ibcon#about to read 3, iclass 3, count 0 2006.285.14:12:42.28#ibcon#read 3, iclass 3, count 0 2006.285.14:12:42.28#ibcon#about to read 4, iclass 3, count 0 2006.285.14:12:42.28#ibcon#read 4, iclass 3, count 0 2006.285.14:12:42.28#ibcon#about to read 5, iclass 3, count 0 2006.285.14:12:42.28#ibcon#read 5, iclass 3, count 0 2006.285.14:12:42.28#ibcon#about to read 6, iclass 3, count 0 2006.285.14:12:42.28#ibcon#read 6, iclass 3, count 0 2006.285.14:12:42.28#ibcon#end of sib2, iclass 3, count 0 2006.285.14:12:42.28#ibcon#*mode == 0, iclass 3, count 0 2006.285.14:12:42.28#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.14:12:42.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.14:12:42.28#ibcon#*before write, iclass 3, count 0 2006.285.14:12:42.28#ibcon#enter sib2, iclass 3, count 0 2006.285.14:12:42.28#ibcon#flushed, iclass 3, count 0 2006.285.14:12:42.28#ibcon#about to write, iclass 3, count 0 2006.285.14:12:42.28#ibcon#wrote, iclass 3, count 0 2006.285.14:12:42.28#ibcon#about to read 3, iclass 3, count 0 2006.285.14:12:42.32#ibcon#read 3, iclass 3, count 0 2006.285.14:12:42.32#ibcon#about to read 4, iclass 3, count 0 2006.285.14:12:42.32#ibcon#read 4, iclass 3, count 0 2006.285.14:12:42.32#ibcon#about to read 5, iclass 3, count 0 2006.285.14:12:42.32#ibcon#read 5, iclass 3, count 0 2006.285.14:12:42.32#ibcon#about to read 6, iclass 3, count 0 2006.285.14:12:42.32#ibcon#read 6, iclass 3, count 0 2006.285.14:12:42.32#ibcon#end of sib2, iclass 3, count 0 2006.285.14:12:42.32#ibcon#*after write, iclass 3, count 0 2006.285.14:12:42.32#ibcon#*before return 0, iclass 3, count 0 2006.285.14:12:42.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:12:42.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:12:42.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.14:12:42.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.14:12:42.33$vck44/vb=4,5 2006.285.14:12:42.33#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.14:12:42.33#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.14:12:42.33#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:42.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:12:42.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:12:42.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:12:42.37#ibcon#enter wrdev, iclass 5, count 2 2006.285.14:12:42.37#ibcon#first serial, iclass 5, count 2 2006.285.14:12:42.37#ibcon#enter sib2, iclass 5, count 2 2006.285.14:12:42.37#ibcon#flushed, iclass 5, count 2 2006.285.14:12:42.37#ibcon#about to write, iclass 5, count 2 2006.285.14:12:42.37#ibcon#wrote, iclass 5, count 2 2006.285.14:12:42.37#ibcon#about to read 3, iclass 5, count 2 2006.285.14:12:42.39#ibcon#read 3, iclass 5, count 2 2006.285.14:12:42.39#ibcon#about to read 4, iclass 5, count 2 2006.285.14:12:42.39#ibcon#read 4, iclass 5, count 2 2006.285.14:12:42.39#ibcon#about to read 5, iclass 5, count 2 2006.285.14:12:42.39#ibcon#read 5, iclass 5, count 2 2006.285.14:12:42.39#ibcon#about to read 6, iclass 5, count 2 2006.285.14:12:42.39#ibcon#read 6, iclass 5, count 2 2006.285.14:12:42.39#ibcon#end of sib2, iclass 5, count 2 2006.285.14:12:42.39#ibcon#*mode == 0, iclass 5, count 2 2006.285.14:12:42.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.14:12:42.39#ibcon#[27=AT04-05\r\n] 2006.285.14:12:42.39#ibcon#*before write, iclass 5, count 2 2006.285.14:12:42.39#ibcon#enter sib2, iclass 5, count 2 2006.285.14:12:42.39#ibcon#flushed, iclass 5, count 2 2006.285.14:12:42.39#ibcon#about to write, iclass 5, count 2 2006.285.14:12:42.39#ibcon#wrote, iclass 5, count 2 2006.285.14:12:42.39#ibcon#about to read 3, iclass 5, count 2 2006.285.14:12:42.42#ibcon#read 3, iclass 5, count 2 2006.285.14:12:42.42#ibcon#about to read 4, iclass 5, count 2 2006.285.14:12:42.42#ibcon#read 4, iclass 5, count 2 2006.285.14:12:42.42#ibcon#about to read 5, iclass 5, count 2 2006.285.14:12:42.42#ibcon#read 5, iclass 5, count 2 2006.285.14:12:42.42#ibcon#about to read 6, iclass 5, count 2 2006.285.14:12:42.42#ibcon#read 6, iclass 5, count 2 2006.285.14:12:42.42#ibcon#end of sib2, iclass 5, count 2 2006.285.14:12:42.42#ibcon#*after write, iclass 5, count 2 2006.285.14:12:42.42#ibcon#*before return 0, iclass 5, count 2 2006.285.14:12:42.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:12:42.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:12:42.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.14:12:42.42#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:42.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:12:42.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:12:42.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:12:42.54#ibcon#enter wrdev, iclass 5, count 0 2006.285.14:12:42.54#ibcon#first serial, iclass 5, count 0 2006.285.14:12:42.54#ibcon#enter sib2, iclass 5, count 0 2006.285.14:12:42.54#ibcon#flushed, iclass 5, count 0 2006.285.14:12:42.54#ibcon#about to write, iclass 5, count 0 2006.285.14:12:42.54#ibcon#wrote, iclass 5, count 0 2006.285.14:12:42.54#ibcon#about to read 3, iclass 5, count 0 2006.285.14:12:42.56#ibcon#read 3, iclass 5, count 0 2006.285.14:12:42.56#ibcon#about to read 4, iclass 5, count 0 2006.285.14:12:42.56#ibcon#read 4, iclass 5, count 0 2006.285.14:12:42.56#ibcon#about to read 5, iclass 5, count 0 2006.285.14:12:42.56#ibcon#read 5, iclass 5, count 0 2006.285.14:12:42.56#ibcon#about to read 6, iclass 5, count 0 2006.285.14:12:42.56#ibcon#read 6, iclass 5, count 0 2006.285.14:12:42.56#ibcon#end of sib2, iclass 5, count 0 2006.285.14:12:42.56#ibcon#*mode == 0, iclass 5, count 0 2006.285.14:12:42.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.14:12:42.56#ibcon#[27=USB\r\n] 2006.285.14:12:42.56#ibcon#*before write, iclass 5, count 0 2006.285.14:12:42.56#ibcon#enter sib2, iclass 5, count 0 2006.285.14:12:42.56#ibcon#flushed, iclass 5, count 0 2006.285.14:12:42.56#ibcon#about to write, iclass 5, count 0 2006.285.14:12:42.56#ibcon#wrote, iclass 5, count 0 2006.285.14:12:42.56#ibcon#about to read 3, iclass 5, count 0 2006.285.14:12:42.59#ibcon#read 3, iclass 5, count 0 2006.285.14:12:42.59#ibcon#about to read 4, iclass 5, count 0 2006.285.14:12:42.59#ibcon#read 4, iclass 5, count 0 2006.285.14:12:42.59#ibcon#about to read 5, iclass 5, count 0 2006.285.14:12:42.59#ibcon#read 5, iclass 5, count 0 2006.285.14:12:42.59#ibcon#about to read 6, iclass 5, count 0 2006.285.14:12:42.59#ibcon#read 6, iclass 5, count 0 2006.285.14:12:42.59#ibcon#end of sib2, iclass 5, count 0 2006.285.14:12:42.59#ibcon#*after write, iclass 5, count 0 2006.285.14:12:42.59#ibcon#*before return 0, iclass 5, count 0 2006.285.14:12:42.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:12:42.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:12:42.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.14:12:42.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.14:12:42.60$vck44/vblo=5,709.99 2006.285.14:12:42.60#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.14:12:42.60#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.14:12:42.60#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:42.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:12:42.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:12:42.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:12:42.60#ibcon#enter wrdev, iclass 7, count 0 2006.285.14:12:42.60#ibcon#first serial, iclass 7, count 0 2006.285.14:12:42.60#ibcon#enter sib2, iclass 7, count 0 2006.285.14:12:42.60#ibcon#flushed, iclass 7, count 0 2006.285.14:12:42.60#ibcon#about to write, iclass 7, count 0 2006.285.14:12:42.60#ibcon#wrote, iclass 7, count 0 2006.285.14:12:42.60#ibcon#about to read 3, iclass 7, count 0 2006.285.14:12:42.61#ibcon#read 3, iclass 7, count 0 2006.285.14:12:42.61#ibcon#about to read 4, iclass 7, count 0 2006.285.14:12:42.61#ibcon#read 4, iclass 7, count 0 2006.285.14:12:42.61#ibcon#about to read 5, iclass 7, count 0 2006.285.14:12:42.61#ibcon#read 5, iclass 7, count 0 2006.285.14:12:42.61#ibcon#about to read 6, iclass 7, count 0 2006.285.14:12:42.61#ibcon#read 6, iclass 7, count 0 2006.285.14:12:42.61#ibcon#end of sib2, iclass 7, count 0 2006.285.14:12:42.61#ibcon#*mode == 0, iclass 7, count 0 2006.285.14:12:42.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.14:12:42.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.14:12:42.61#ibcon#*before write, iclass 7, count 0 2006.285.14:12:42.61#ibcon#enter sib2, iclass 7, count 0 2006.285.14:12:42.61#ibcon#flushed, iclass 7, count 0 2006.285.14:12:42.61#ibcon#about to write, iclass 7, count 0 2006.285.14:12:42.61#ibcon#wrote, iclass 7, count 0 2006.285.14:12:42.61#ibcon#about to read 3, iclass 7, count 0 2006.285.14:12:42.65#ibcon#read 3, iclass 7, count 0 2006.285.14:12:42.65#ibcon#about to read 4, iclass 7, count 0 2006.285.14:12:42.65#ibcon#read 4, iclass 7, count 0 2006.285.14:12:42.65#ibcon#about to read 5, iclass 7, count 0 2006.285.14:12:42.65#ibcon#read 5, iclass 7, count 0 2006.285.14:12:42.65#ibcon#about to read 6, iclass 7, count 0 2006.285.14:12:42.65#ibcon#read 6, iclass 7, count 0 2006.285.14:12:42.65#ibcon#end of sib2, iclass 7, count 0 2006.285.14:12:42.65#ibcon#*after write, iclass 7, count 0 2006.285.14:12:42.65#ibcon#*before return 0, iclass 7, count 0 2006.285.14:12:42.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:12:42.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:12:42.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.14:12:42.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.14:12:42.66$vck44/vb=5,4 2006.285.14:12:42.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.14:12:42.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.14:12:42.66#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:42.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:12:42.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:12:42.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:12:42.70#ibcon#enter wrdev, iclass 11, count 2 2006.285.14:12:42.70#ibcon#first serial, iclass 11, count 2 2006.285.14:12:42.70#ibcon#enter sib2, iclass 11, count 2 2006.285.14:12:42.70#ibcon#flushed, iclass 11, count 2 2006.285.14:12:42.70#ibcon#about to write, iclass 11, count 2 2006.285.14:12:42.70#ibcon#wrote, iclass 11, count 2 2006.285.14:12:42.70#ibcon#about to read 3, iclass 11, count 2 2006.285.14:12:42.72#ibcon#read 3, iclass 11, count 2 2006.285.14:12:42.72#ibcon#about to read 4, iclass 11, count 2 2006.285.14:12:42.72#ibcon#read 4, iclass 11, count 2 2006.285.14:12:42.72#ibcon#about to read 5, iclass 11, count 2 2006.285.14:12:42.72#ibcon#read 5, iclass 11, count 2 2006.285.14:12:42.72#ibcon#about to read 6, iclass 11, count 2 2006.285.14:12:42.72#ibcon#read 6, iclass 11, count 2 2006.285.14:12:42.72#ibcon#end of sib2, iclass 11, count 2 2006.285.14:12:42.72#ibcon#*mode == 0, iclass 11, count 2 2006.285.14:12:42.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.14:12:42.72#ibcon#[27=AT05-04\r\n] 2006.285.14:12:42.72#ibcon#*before write, iclass 11, count 2 2006.285.14:12:42.72#ibcon#enter sib2, iclass 11, count 2 2006.285.14:12:42.72#ibcon#flushed, iclass 11, count 2 2006.285.14:12:42.72#ibcon#about to write, iclass 11, count 2 2006.285.14:12:42.72#ibcon#wrote, iclass 11, count 2 2006.285.14:12:42.72#ibcon#about to read 3, iclass 11, count 2 2006.285.14:12:42.75#ibcon#read 3, iclass 11, count 2 2006.285.14:12:42.75#ibcon#about to read 4, iclass 11, count 2 2006.285.14:12:42.75#ibcon#read 4, iclass 11, count 2 2006.285.14:12:42.75#ibcon#about to read 5, iclass 11, count 2 2006.285.14:12:42.75#ibcon#read 5, iclass 11, count 2 2006.285.14:12:42.75#ibcon#about to read 6, iclass 11, count 2 2006.285.14:12:42.75#ibcon#read 6, iclass 11, count 2 2006.285.14:12:42.75#ibcon#end of sib2, iclass 11, count 2 2006.285.14:12:42.75#ibcon#*after write, iclass 11, count 2 2006.285.14:12:42.75#ibcon#*before return 0, iclass 11, count 2 2006.285.14:12:42.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:12:42.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:12:42.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.14:12:42.75#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:42.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:12:42.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:12:42.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:12:42.87#ibcon#enter wrdev, iclass 11, count 0 2006.285.14:12:42.87#ibcon#first serial, iclass 11, count 0 2006.285.14:12:42.87#ibcon#enter sib2, iclass 11, count 0 2006.285.14:12:42.87#ibcon#flushed, iclass 11, count 0 2006.285.14:12:42.87#ibcon#about to write, iclass 11, count 0 2006.285.14:12:42.87#ibcon#wrote, iclass 11, count 0 2006.285.14:12:42.87#ibcon#about to read 3, iclass 11, count 0 2006.285.14:12:42.89#ibcon#read 3, iclass 11, count 0 2006.285.14:12:42.89#ibcon#about to read 4, iclass 11, count 0 2006.285.14:12:42.89#ibcon#read 4, iclass 11, count 0 2006.285.14:12:42.89#ibcon#about to read 5, iclass 11, count 0 2006.285.14:12:42.89#ibcon#read 5, iclass 11, count 0 2006.285.14:12:42.89#ibcon#about to read 6, iclass 11, count 0 2006.285.14:12:42.89#ibcon#read 6, iclass 11, count 0 2006.285.14:12:42.89#ibcon#end of sib2, iclass 11, count 0 2006.285.14:12:42.89#ibcon#*mode == 0, iclass 11, count 0 2006.285.14:12:42.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.14:12:42.89#ibcon#[27=USB\r\n] 2006.285.14:12:42.89#ibcon#*before write, iclass 11, count 0 2006.285.14:12:42.89#ibcon#enter sib2, iclass 11, count 0 2006.285.14:12:42.89#ibcon#flushed, iclass 11, count 0 2006.285.14:12:42.89#ibcon#about to write, iclass 11, count 0 2006.285.14:12:42.89#ibcon#wrote, iclass 11, count 0 2006.285.14:12:42.89#ibcon#about to read 3, iclass 11, count 0 2006.285.14:12:42.92#ibcon#read 3, iclass 11, count 0 2006.285.14:12:42.92#ibcon#about to read 4, iclass 11, count 0 2006.285.14:12:42.92#ibcon#read 4, iclass 11, count 0 2006.285.14:12:42.92#ibcon#about to read 5, iclass 11, count 0 2006.285.14:12:42.92#ibcon#read 5, iclass 11, count 0 2006.285.14:12:42.92#ibcon#about to read 6, iclass 11, count 0 2006.285.14:12:42.92#ibcon#read 6, iclass 11, count 0 2006.285.14:12:42.92#ibcon#end of sib2, iclass 11, count 0 2006.285.14:12:42.92#ibcon#*after write, iclass 11, count 0 2006.285.14:12:42.92#ibcon#*before return 0, iclass 11, count 0 2006.285.14:12:42.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:12:42.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:12:42.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.14:12:42.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.14:12:42.93$vck44/vblo=6,719.99 2006.285.14:12:42.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.14:12:42.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.14:12:42.93#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:42.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:12:42.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:12:42.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:12:42.93#ibcon#enter wrdev, iclass 13, count 0 2006.285.14:12:42.93#ibcon#first serial, iclass 13, count 0 2006.285.14:12:42.93#ibcon#enter sib2, iclass 13, count 0 2006.285.14:12:42.93#ibcon#flushed, iclass 13, count 0 2006.285.14:12:42.93#ibcon#about to write, iclass 13, count 0 2006.285.14:12:42.93#ibcon#wrote, iclass 13, count 0 2006.285.14:12:42.93#ibcon#about to read 3, iclass 13, count 0 2006.285.14:12:42.94#ibcon#read 3, iclass 13, count 0 2006.285.14:12:42.94#ibcon#about to read 4, iclass 13, count 0 2006.285.14:12:42.94#ibcon#read 4, iclass 13, count 0 2006.285.14:12:42.94#ibcon#about to read 5, iclass 13, count 0 2006.285.14:12:42.94#ibcon#read 5, iclass 13, count 0 2006.285.14:12:42.94#ibcon#about to read 6, iclass 13, count 0 2006.285.14:12:42.94#ibcon#read 6, iclass 13, count 0 2006.285.14:12:42.94#ibcon#end of sib2, iclass 13, count 0 2006.285.14:12:42.94#ibcon#*mode == 0, iclass 13, count 0 2006.285.14:12:42.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.14:12:42.94#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.14:12:42.94#ibcon#*before write, iclass 13, count 0 2006.285.14:12:42.94#ibcon#enter sib2, iclass 13, count 0 2006.285.14:12:42.94#ibcon#flushed, iclass 13, count 0 2006.285.14:12:42.94#ibcon#about to write, iclass 13, count 0 2006.285.14:12:42.94#ibcon#wrote, iclass 13, count 0 2006.285.14:12:42.94#ibcon#about to read 3, iclass 13, count 0 2006.285.14:12:42.98#ibcon#read 3, iclass 13, count 0 2006.285.14:12:42.98#ibcon#about to read 4, iclass 13, count 0 2006.285.14:12:42.98#ibcon#read 4, iclass 13, count 0 2006.285.14:12:42.98#ibcon#about to read 5, iclass 13, count 0 2006.285.14:12:42.98#ibcon#read 5, iclass 13, count 0 2006.285.14:12:42.98#ibcon#about to read 6, iclass 13, count 0 2006.285.14:12:42.98#ibcon#read 6, iclass 13, count 0 2006.285.14:12:42.98#ibcon#end of sib2, iclass 13, count 0 2006.285.14:12:42.98#ibcon#*after write, iclass 13, count 0 2006.285.14:12:42.98#ibcon#*before return 0, iclass 13, count 0 2006.285.14:12:42.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:12:42.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:12:42.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.14:12:42.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.14:12:42.99$vck44/vb=6,3 2006.285.14:12:42.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.14:12:42.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.14:12:42.99#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:42.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:12:43.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:12:43.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:12:43.03#ibcon#enter wrdev, iclass 15, count 2 2006.285.14:12:43.03#ibcon#first serial, iclass 15, count 2 2006.285.14:12:43.03#ibcon#enter sib2, iclass 15, count 2 2006.285.14:12:43.03#ibcon#flushed, iclass 15, count 2 2006.285.14:12:43.03#ibcon#about to write, iclass 15, count 2 2006.285.14:12:43.03#ibcon#wrote, iclass 15, count 2 2006.285.14:12:43.03#ibcon#about to read 3, iclass 15, count 2 2006.285.14:12:43.05#ibcon#read 3, iclass 15, count 2 2006.285.14:12:43.05#ibcon#about to read 4, iclass 15, count 2 2006.285.14:12:43.05#ibcon#read 4, iclass 15, count 2 2006.285.14:12:43.05#ibcon#about to read 5, iclass 15, count 2 2006.285.14:12:43.05#ibcon#read 5, iclass 15, count 2 2006.285.14:12:43.05#ibcon#about to read 6, iclass 15, count 2 2006.285.14:12:43.05#ibcon#read 6, iclass 15, count 2 2006.285.14:12:43.05#ibcon#end of sib2, iclass 15, count 2 2006.285.14:12:43.05#ibcon#*mode == 0, iclass 15, count 2 2006.285.14:12:43.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.14:12:43.05#ibcon#[27=AT06-03\r\n] 2006.285.14:12:43.05#ibcon#*before write, iclass 15, count 2 2006.285.14:12:43.05#ibcon#enter sib2, iclass 15, count 2 2006.285.14:12:43.05#ibcon#flushed, iclass 15, count 2 2006.285.14:12:43.05#ibcon#about to write, iclass 15, count 2 2006.285.14:12:43.05#ibcon#wrote, iclass 15, count 2 2006.285.14:12:43.05#ibcon#about to read 3, iclass 15, count 2 2006.285.14:12:43.08#ibcon#read 3, iclass 15, count 2 2006.285.14:12:43.08#ibcon#about to read 4, iclass 15, count 2 2006.285.14:12:43.08#ibcon#read 4, iclass 15, count 2 2006.285.14:12:43.08#ibcon#about to read 5, iclass 15, count 2 2006.285.14:12:43.08#ibcon#read 5, iclass 15, count 2 2006.285.14:12:43.08#ibcon#about to read 6, iclass 15, count 2 2006.285.14:12:43.08#ibcon#read 6, iclass 15, count 2 2006.285.14:12:43.08#ibcon#end of sib2, iclass 15, count 2 2006.285.14:12:43.08#ibcon#*after write, iclass 15, count 2 2006.285.14:12:43.08#ibcon#*before return 0, iclass 15, count 2 2006.285.14:12:43.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:12:43.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:12:43.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.14:12:43.08#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:43.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:12:43.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:12:43.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:12:43.20#ibcon#enter wrdev, iclass 15, count 0 2006.285.14:12:43.20#ibcon#first serial, iclass 15, count 0 2006.285.14:12:43.20#ibcon#enter sib2, iclass 15, count 0 2006.285.14:12:43.20#ibcon#flushed, iclass 15, count 0 2006.285.14:12:43.20#ibcon#about to write, iclass 15, count 0 2006.285.14:12:43.20#ibcon#wrote, iclass 15, count 0 2006.285.14:12:43.20#ibcon#about to read 3, iclass 15, count 0 2006.285.14:12:43.22#ibcon#read 3, iclass 15, count 0 2006.285.14:12:43.22#ibcon#about to read 4, iclass 15, count 0 2006.285.14:12:43.22#ibcon#read 4, iclass 15, count 0 2006.285.14:12:43.22#ibcon#about to read 5, iclass 15, count 0 2006.285.14:12:43.22#ibcon#read 5, iclass 15, count 0 2006.285.14:12:43.22#ibcon#about to read 6, iclass 15, count 0 2006.285.14:12:43.22#ibcon#read 6, iclass 15, count 0 2006.285.14:12:43.22#ibcon#end of sib2, iclass 15, count 0 2006.285.14:12:43.22#ibcon#*mode == 0, iclass 15, count 0 2006.285.14:12:43.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.14:12:43.22#ibcon#[27=USB\r\n] 2006.285.14:12:43.22#ibcon#*before write, iclass 15, count 0 2006.285.14:12:43.22#ibcon#enter sib2, iclass 15, count 0 2006.285.14:12:43.22#ibcon#flushed, iclass 15, count 0 2006.285.14:12:43.22#ibcon#about to write, iclass 15, count 0 2006.285.14:12:43.22#ibcon#wrote, iclass 15, count 0 2006.285.14:12:43.22#ibcon#about to read 3, iclass 15, count 0 2006.285.14:12:43.25#ibcon#read 3, iclass 15, count 0 2006.285.14:12:43.25#ibcon#about to read 4, iclass 15, count 0 2006.285.14:12:43.25#ibcon#read 4, iclass 15, count 0 2006.285.14:12:43.25#ibcon#about to read 5, iclass 15, count 0 2006.285.14:12:43.25#ibcon#read 5, iclass 15, count 0 2006.285.14:12:43.25#ibcon#about to read 6, iclass 15, count 0 2006.285.14:12:43.25#ibcon#read 6, iclass 15, count 0 2006.285.14:12:43.25#ibcon#end of sib2, iclass 15, count 0 2006.285.14:12:43.25#ibcon#*after write, iclass 15, count 0 2006.285.14:12:43.25#ibcon#*before return 0, iclass 15, count 0 2006.285.14:12:43.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:12:43.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:12:43.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.14:12:43.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.14:12:43.26$vck44/vblo=7,734.99 2006.285.14:12:43.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.14:12:43.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.14:12:43.26#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:43.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:12:43.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:12:43.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:12:43.26#ibcon#enter wrdev, iclass 17, count 0 2006.285.14:12:43.26#ibcon#first serial, iclass 17, count 0 2006.285.14:12:43.26#ibcon#enter sib2, iclass 17, count 0 2006.285.14:12:43.26#ibcon#flushed, iclass 17, count 0 2006.285.14:12:43.26#ibcon#about to write, iclass 17, count 0 2006.285.14:12:43.26#ibcon#wrote, iclass 17, count 0 2006.285.14:12:43.26#ibcon#about to read 3, iclass 17, count 0 2006.285.14:12:43.27#ibcon#read 3, iclass 17, count 0 2006.285.14:12:43.27#ibcon#about to read 4, iclass 17, count 0 2006.285.14:12:43.27#ibcon#read 4, iclass 17, count 0 2006.285.14:12:43.27#ibcon#about to read 5, iclass 17, count 0 2006.285.14:12:43.27#ibcon#read 5, iclass 17, count 0 2006.285.14:12:43.27#ibcon#about to read 6, iclass 17, count 0 2006.285.14:12:43.27#ibcon#read 6, iclass 17, count 0 2006.285.14:12:43.27#ibcon#end of sib2, iclass 17, count 0 2006.285.14:12:43.27#ibcon#*mode == 0, iclass 17, count 0 2006.285.14:12:43.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.14:12:43.27#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.14:12:43.27#ibcon#*before write, iclass 17, count 0 2006.285.14:12:43.27#ibcon#enter sib2, iclass 17, count 0 2006.285.14:12:43.27#ibcon#flushed, iclass 17, count 0 2006.285.14:12:43.27#ibcon#about to write, iclass 17, count 0 2006.285.14:12:43.27#ibcon#wrote, iclass 17, count 0 2006.285.14:12:43.27#ibcon#about to read 3, iclass 17, count 0 2006.285.14:12:43.31#ibcon#read 3, iclass 17, count 0 2006.285.14:12:43.31#ibcon#about to read 4, iclass 17, count 0 2006.285.14:12:43.31#ibcon#read 4, iclass 17, count 0 2006.285.14:12:43.31#ibcon#about to read 5, iclass 17, count 0 2006.285.14:12:43.31#ibcon#read 5, iclass 17, count 0 2006.285.14:12:43.31#ibcon#about to read 6, iclass 17, count 0 2006.285.14:12:43.31#ibcon#read 6, iclass 17, count 0 2006.285.14:12:43.31#ibcon#end of sib2, iclass 17, count 0 2006.285.14:12:43.31#ibcon#*after write, iclass 17, count 0 2006.285.14:12:43.31#ibcon#*before return 0, iclass 17, count 0 2006.285.14:12:43.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:12:43.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:12:43.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.14:12:43.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.14:12:43.32$vck44/vb=7,4 2006.285.14:12:43.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.14:12:43.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.14:12:43.32#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:43.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:12:43.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:12:43.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:12:43.36#ibcon#enter wrdev, iclass 19, count 2 2006.285.14:12:43.36#ibcon#first serial, iclass 19, count 2 2006.285.14:12:43.36#ibcon#enter sib2, iclass 19, count 2 2006.285.14:12:43.36#ibcon#flushed, iclass 19, count 2 2006.285.14:12:43.36#ibcon#about to write, iclass 19, count 2 2006.285.14:12:43.36#ibcon#wrote, iclass 19, count 2 2006.285.14:12:43.36#ibcon#about to read 3, iclass 19, count 2 2006.285.14:12:43.38#ibcon#read 3, iclass 19, count 2 2006.285.14:12:43.38#ibcon#about to read 4, iclass 19, count 2 2006.285.14:12:43.38#ibcon#read 4, iclass 19, count 2 2006.285.14:12:43.38#ibcon#about to read 5, iclass 19, count 2 2006.285.14:12:43.38#ibcon#read 5, iclass 19, count 2 2006.285.14:12:43.38#ibcon#about to read 6, iclass 19, count 2 2006.285.14:12:43.38#ibcon#read 6, iclass 19, count 2 2006.285.14:12:43.38#ibcon#end of sib2, iclass 19, count 2 2006.285.14:12:43.38#ibcon#*mode == 0, iclass 19, count 2 2006.285.14:12:43.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.14:12:43.38#ibcon#[27=AT07-04\r\n] 2006.285.14:12:43.38#ibcon#*before write, iclass 19, count 2 2006.285.14:12:43.38#ibcon#enter sib2, iclass 19, count 2 2006.285.14:12:43.38#ibcon#flushed, iclass 19, count 2 2006.285.14:12:43.38#ibcon#about to write, iclass 19, count 2 2006.285.14:12:43.38#ibcon#wrote, iclass 19, count 2 2006.285.14:12:43.38#ibcon#about to read 3, iclass 19, count 2 2006.285.14:12:43.41#ibcon#read 3, iclass 19, count 2 2006.285.14:12:43.41#ibcon#about to read 4, iclass 19, count 2 2006.285.14:12:43.41#ibcon#read 4, iclass 19, count 2 2006.285.14:12:43.41#ibcon#about to read 5, iclass 19, count 2 2006.285.14:12:43.41#ibcon#read 5, iclass 19, count 2 2006.285.14:12:43.41#ibcon#about to read 6, iclass 19, count 2 2006.285.14:12:43.41#ibcon#read 6, iclass 19, count 2 2006.285.14:12:43.41#ibcon#end of sib2, iclass 19, count 2 2006.285.14:12:43.41#ibcon#*after write, iclass 19, count 2 2006.285.14:12:43.41#ibcon#*before return 0, iclass 19, count 2 2006.285.14:12:43.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:12:43.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:12:43.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.14:12:43.41#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:43.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:12:43.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:12:43.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:12:43.53#ibcon#enter wrdev, iclass 19, count 0 2006.285.14:12:43.53#ibcon#first serial, iclass 19, count 0 2006.285.14:12:43.53#ibcon#enter sib2, iclass 19, count 0 2006.285.14:12:43.53#ibcon#flushed, iclass 19, count 0 2006.285.14:12:43.53#ibcon#about to write, iclass 19, count 0 2006.285.14:12:43.53#ibcon#wrote, iclass 19, count 0 2006.285.14:12:43.53#ibcon#about to read 3, iclass 19, count 0 2006.285.14:12:43.55#ibcon#read 3, iclass 19, count 0 2006.285.14:12:43.55#ibcon#about to read 4, iclass 19, count 0 2006.285.14:12:43.55#ibcon#read 4, iclass 19, count 0 2006.285.14:12:43.55#ibcon#about to read 5, iclass 19, count 0 2006.285.14:12:43.55#ibcon#read 5, iclass 19, count 0 2006.285.14:12:43.55#ibcon#about to read 6, iclass 19, count 0 2006.285.14:12:43.55#ibcon#read 6, iclass 19, count 0 2006.285.14:12:43.61#ibcon#end of sib2, iclass 19, count 0 2006.285.14:12:43.61#ibcon#*mode == 0, iclass 19, count 0 2006.285.14:12:43.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.14:12:43.61#ibcon#[27=USB\r\n] 2006.285.14:12:43.61#ibcon#*before write, iclass 19, count 0 2006.285.14:12:43.61#ibcon#enter sib2, iclass 19, count 0 2006.285.14:12:43.61#ibcon#flushed, iclass 19, count 0 2006.285.14:12:43.61#ibcon#about to write, iclass 19, count 0 2006.285.14:12:43.61#ibcon#wrote, iclass 19, count 0 2006.285.14:12:43.61#ibcon#about to read 3, iclass 19, count 0 2006.285.14:12:43.63#ibcon#read 3, iclass 19, count 0 2006.285.14:12:43.63#ibcon#about to read 4, iclass 19, count 0 2006.285.14:12:43.63#ibcon#read 4, iclass 19, count 0 2006.285.14:12:43.63#ibcon#about to read 5, iclass 19, count 0 2006.285.14:12:43.63#ibcon#read 5, iclass 19, count 0 2006.285.14:12:43.63#ibcon#about to read 6, iclass 19, count 0 2006.285.14:12:43.63#ibcon#read 6, iclass 19, count 0 2006.285.14:12:43.63#ibcon#end of sib2, iclass 19, count 0 2006.285.14:12:43.63#ibcon#*after write, iclass 19, count 0 2006.285.14:12:43.63#ibcon#*before return 0, iclass 19, count 0 2006.285.14:12:43.63#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:12:43.63#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:12:43.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.14:12:43.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.14:12:43.64$vck44/vblo=8,744.99 2006.285.14:12:43.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.14:12:43.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.14:12:43.64#ibcon#ireg 17 cls_cnt 0 2006.285.14:12:43.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:12:43.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:12:43.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:12:43.64#ibcon#enter wrdev, iclass 21, count 0 2006.285.14:12:43.64#ibcon#first serial, iclass 21, count 0 2006.285.14:12:43.64#ibcon#enter sib2, iclass 21, count 0 2006.285.14:12:43.64#ibcon#flushed, iclass 21, count 0 2006.285.14:12:43.64#ibcon#about to write, iclass 21, count 0 2006.285.14:12:43.64#ibcon#wrote, iclass 21, count 0 2006.285.14:12:43.64#ibcon#about to read 3, iclass 21, count 0 2006.285.14:12:43.65#ibcon#read 3, iclass 21, count 0 2006.285.14:12:43.65#ibcon#about to read 4, iclass 21, count 0 2006.285.14:12:43.65#ibcon#read 4, iclass 21, count 0 2006.285.14:12:43.65#ibcon#about to read 5, iclass 21, count 0 2006.285.14:12:43.65#ibcon#read 5, iclass 21, count 0 2006.285.14:12:43.65#ibcon#about to read 6, iclass 21, count 0 2006.285.14:12:43.65#ibcon#read 6, iclass 21, count 0 2006.285.14:12:43.65#ibcon#end of sib2, iclass 21, count 0 2006.285.14:12:43.65#ibcon#*mode == 0, iclass 21, count 0 2006.285.14:12:43.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.14:12:43.65#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.14:12:43.65#ibcon#*before write, iclass 21, count 0 2006.285.14:12:43.65#ibcon#enter sib2, iclass 21, count 0 2006.285.14:12:43.65#ibcon#flushed, iclass 21, count 0 2006.285.14:12:43.65#ibcon#about to write, iclass 21, count 0 2006.285.14:12:43.65#ibcon#wrote, iclass 21, count 0 2006.285.14:12:43.65#ibcon#about to read 3, iclass 21, count 0 2006.285.14:12:43.69#ibcon#read 3, iclass 21, count 0 2006.285.14:12:43.69#ibcon#about to read 4, iclass 21, count 0 2006.285.14:12:43.69#ibcon#read 4, iclass 21, count 0 2006.285.14:12:43.69#ibcon#about to read 5, iclass 21, count 0 2006.285.14:12:43.69#ibcon#read 5, iclass 21, count 0 2006.285.14:12:43.69#ibcon#about to read 6, iclass 21, count 0 2006.285.14:12:43.69#ibcon#read 6, iclass 21, count 0 2006.285.14:12:43.69#ibcon#end of sib2, iclass 21, count 0 2006.285.14:12:43.69#ibcon#*after write, iclass 21, count 0 2006.285.14:12:43.69#ibcon#*before return 0, iclass 21, count 0 2006.285.14:12:43.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:12:43.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:12:43.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.14:12:43.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.14:12:43.70$vck44/vb=8,4 2006.285.14:12:43.70#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.14:12:43.70#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.14:12:43.70#ibcon#ireg 11 cls_cnt 2 2006.285.14:12:43.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:12:43.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:12:43.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:12:43.74#ibcon#enter wrdev, iclass 23, count 2 2006.285.14:12:43.74#ibcon#first serial, iclass 23, count 2 2006.285.14:12:43.74#ibcon#enter sib2, iclass 23, count 2 2006.285.14:12:43.74#ibcon#flushed, iclass 23, count 2 2006.285.14:12:43.74#ibcon#about to write, iclass 23, count 2 2006.285.14:12:43.74#ibcon#wrote, iclass 23, count 2 2006.285.14:12:43.74#ibcon#about to read 3, iclass 23, count 2 2006.285.14:12:43.76#ibcon#read 3, iclass 23, count 2 2006.285.14:12:43.76#ibcon#about to read 4, iclass 23, count 2 2006.285.14:12:43.76#ibcon#read 4, iclass 23, count 2 2006.285.14:12:43.76#ibcon#about to read 5, iclass 23, count 2 2006.285.14:12:43.76#ibcon#read 5, iclass 23, count 2 2006.285.14:12:43.76#ibcon#about to read 6, iclass 23, count 2 2006.285.14:12:43.76#ibcon#read 6, iclass 23, count 2 2006.285.14:12:43.76#ibcon#end of sib2, iclass 23, count 2 2006.285.14:12:43.76#ibcon#*mode == 0, iclass 23, count 2 2006.285.14:12:43.76#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.14:12:43.76#ibcon#[27=AT08-04\r\n] 2006.285.14:12:43.76#ibcon#*before write, iclass 23, count 2 2006.285.14:12:43.76#ibcon#enter sib2, iclass 23, count 2 2006.285.14:12:43.76#ibcon#flushed, iclass 23, count 2 2006.285.14:12:43.76#ibcon#about to write, iclass 23, count 2 2006.285.14:12:43.76#ibcon#wrote, iclass 23, count 2 2006.285.14:12:43.76#ibcon#about to read 3, iclass 23, count 2 2006.285.14:12:43.79#ibcon#read 3, iclass 23, count 2 2006.285.14:12:43.79#ibcon#about to read 4, iclass 23, count 2 2006.285.14:12:43.79#ibcon#read 4, iclass 23, count 2 2006.285.14:12:43.79#ibcon#about to read 5, iclass 23, count 2 2006.285.14:12:43.79#ibcon#read 5, iclass 23, count 2 2006.285.14:12:43.79#ibcon#about to read 6, iclass 23, count 2 2006.285.14:12:43.79#ibcon#read 6, iclass 23, count 2 2006.285.14:12:43.79#ibcon#end of sib2, iclass 23, count 2 2006.285.14:12:43.79#ibcon#*after write, iclass 23, count 2 2006.285.14:12:43.79#ibcon#*before return 0, iclass 23, count 2 2006.285.14:12:43.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:12:43.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:12:43.79#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.14:12:43.79#ibcon#ireg 7 cls_cnt 0 2006.285.14:12:43.79#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:12:43.91#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:12:43.91#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:12:43.91#ibcon#enter wrdev, iclass 23, count 0 2006.285.14:12:43.91#ibcon#first serial, iclass 23, count 0 2006.285.14:12:43.91#ibcon#enter sib2, iclass 23, count 0 2006.285.14:12:43.91#ibcon#flushed, iclass 23, count 0 2006.285.14:12:43.91#ibcon#about to write, iclass 23, count 0 2006.285.14:12:43.91#ibcon#wrote, iclass 23, count 0 2006.285.14:12:43.91#ibcon#about to read 3, iclass 23, count 0 2006.285.14:12:43.93#ibcon#read 3, iclass 23, count 0 2006.285.14:12:43.93#ibcon#about to read 4, iclass 23, count 0 2006.285.14:12:43.93#ibcon#read 4, iclass 23, count 0 2006.285.14:12:43.93#ibcon#about to read 5, iclass 23, count 0 2006.285.14:12:43.93#ibcon#read 5, iclass 23, count 0 2006.285.14:12:43.93#ibcon#about to read 6, iclass 23, count 0 2006.285.14:12:43.93#ibcon#read 6, iclass 23, count 0 2006.285.14:12:43.93#ibcon#end of sib2, iclass 23, count 0 2006.285.14:12:43.93#ibcon#*mode == 0, iclass 23, count 0 2006.285.14:12:43.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.14:12:43.93#ibcon#[27=USB\r\n] 2006.285.14:12:43.93#ibcon#*before write, iclass 23, count 0 2006.285.14:12:43.93#ibcon#enter sib2, iclass 23, count 0 2006.285.14:12:43.93#ibcon#flushed, iclass 23, count 0 2006.285.14:12:43.93#ibcon#about to write, iclass 23, count 0 2006.285.14:12:43.93#ibcon#wrote, iclass 23, count 0 2006.285.14:12:43.93#ibcon#about to read 3, iclass 23, count 0 2006.285.14:12:43.96#ibcon#read 3, iclass 23, count 0 2006.285.14:12:43.96#ibcon#about to read 4, iclass 23, count 0 2006.285.14:12:43.96#ibcon#read 4, iclass 23, count 0 2006.285.14:12:43.96#ibcon#about to read 5, iclass 23, count 0 2006.285.14:12:43.96#ibcon#read 5, iclass 23, count 0 2006.285.14:12:43.96#ibcon#about to read 6, iclass 23, count 0 2006.285.14:12:43.96#ibcon#read 6, iclass 23, count 0 2006.285.14:12:43.96#ibcon#end of sib2, iclass 23, count 0 2006.285.14:12:43.96#ibcon#*after write, iclass 23, count 0 2006.285.14:12:43.96#ibcon#*before return 0, iclass 23, count 0 2006.285.14:12:43.96#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:12:43.96#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:12:43.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.14:12:43.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.14:12:43.97$vck44/vabw=wide 2006.285.14:12:43.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.14:12:43.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.14:12:43.97#ibcon#ireg 8 cls_cnt 0 2006.285.14:12:43.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:12:43.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:12:43.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:12:43.97#ibcon#enter wrdev, iclass 25, count 0 2006.285.14:12:43.97#ibcon#first serial, iclass 25, count 0 2006.285.14:12:43.97#ibcon#enter sib2, iclass 25, count 0 2006.285.14:12:43.97#ibcon#flushed, iclass 25, count 0 2006.285.14:12:43.97#ibcon#about to write, iclass 25, count 0 2006.285.14:12:43.97#ibcon#wrote, iclass 25, count 0 2006.285.14:12:43.97#ibcon#about to read 3, iclass 25, count 0 2006.285.14:12:43.98#ibcon#read 3, iclass 25, count 0 2006.285.14:12:43.98#ibcon#about to read 4, iclass 25, count 0 2006.285.14:12:43.98#ibcon#read 4, iclass 25, count 0 2006.285.14:12:43.98#ibcon#about to read 5, iclass 25, count 0 2006.285.14:12:43.98#ibcon#read 5, iclass 25, count 0 2006.285.14:12:43.98#ibcon#about to read 6, iclass 25, count 0 2006.285.14:12:43.98#ibcon#read 6, iclass 25, count 0 2006.285.14:12:43.98#ibcon#end of sib2, iclass 25, count 0 2006.285.14:12:43.98#ibcon#*mode == 0, iclass 25, count 0 2006.285.14:12:43.98#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.14:12:43.98#ibcon#[25=BW32\r\n] 2006.285.14:12:43.98#ibcon#*before write, iclass 25, count 0 2006.285.14:12:43.98#ibcon#enter sib2, iclass 25, count 0 2006.285.14:12:43.98#ibcon#flushed, iclass 25, count 0 2006.285.14:12:43.98#ibcon#about to write, iclass 25, count 0 2006.285.14:12:43.98#ibcon#wrote, iclass 25, count 0 2006.285.14:12:43.98#ibcon#about to read 3, iclass 25, count 0 2006.285.14:12:44.01#ibcon#read 3, iclass 25, count 0 2006.285.14:12:44.01#ibcon#about to read 4, iclass 25, count 0 2006.285.14:12:44.01#ibcon#read 4, iclass 25, count 0 2006.285.14:12:44.01#ibcon#about to read 5, iclass 25, count 0 2006.285.14:12:44.01#ibcon#read 5, iclass 25, count 0 2006.285.14:12:44.01#ibcon#about to read 6, iclass 25, count 0 2006.285.14:12:44.01#ibcon#read 6, iclass 25, count 0 2006.285.14:12:44.01#ibcon#end of sib2, iclass 25, count 0 2006.285.14:12:44.01#ibcon#*after write, iclass 25, count 0 2006.285.14:12:44.01#ibcon#*before return 0, iclass 25, count 0 2006.285.14:12:44.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:12:44.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:12:44.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.14:12:44.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.14:12:44.02$vck44/vbbw=wide 2006.285.14:12:44.02#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.14:12:44.02#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.14:12:44.02#ibcon#ireg 8 cls_cnt 0 2006.285.14:12:44.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:12:44.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:12:44.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:12:44.07#ibcon#enter wrdev, iclass 27, count 0 2006.285.14:12:44.07#ibcon#first serial, iclass 27, count 0 2006.285.14:12:44.07#ibcon#enter sib2, iclass 27, count 0 2006.285.14:12:44.07#ibcon#flushed, iclass 27, count 0 2006.285.14:12:44.07#ibcon#about to write, iclass 27, count 0 2006.285.14:12:44.07#ibcon#wrote, iclass 27, count 0 2006.285.14:12:44.07#ibcon#about to read 3, iclass 27, count 0 2006.285.14:12:44.09#ibcon#read 3, iclass 27, count 0 2006.285.14:12:44.09#ibcon#about to read 4, iclass 27, count 0 2006.285.14:12:44.09#ibcon#read 4, iclass 27, count 0 2006.285.14:12:44.09#ibcon#about to read 5, iclass 27, count 0 2006.285.14:12:44.09#ibcon#read 5, iclass 27, count 0 2006.285.14:12:44.09#ibcon#about to read 6, iclass 27, count 0 2006.285.14:12:44.09#ibcon#read 6, iclass 27, count 0 2006.285.14:12:44.09#ibcon#end of sib2, iclass 27, count 0 2006.285.14:12:44.09#ibcon#*mode == 0, iclass 27, count 0 2006.285.14:12:44.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.14:12:44.09#ibcon#[27=BW32\r\n] 2006.285.14:12:44.09#ibcon#*before write, iclass 27, count 0 2006.285.14:12:44.09#ibcon#enter sib2, iclass 27, count 0 2006.285.14:12:44.09#ibcon#flushed, iclass 27, count 0 2006.285.14:12:44.09#ibcon#about to write, iclass 27, count 0 2006.285.14:12:44.09#ibcon#wrote, iclass 27, count 0 2006.285.14:12:44.09#ibcon#about to read 3, iclass 27, count 0 2006.285.14:12:44.12#ibcon#read 3, iclass 27, count 0 2006.285.14:12:44.12#ibcon#about to read 4, iclass 27, count 0 2006.285.14:12:44.12#ibcon#read 4, iclass 27, count 0 2006.285.14:12:44.12#ibcon#about to read 5, iclass 27, count 0 2006.285.14:12:44.12#ibcon#read 5, iclass 27, count 0 2006.285.14:12:44.12#ibcon#about to read 6, iclass 27, count 0 2006.285.14:12:44.12#ibcon#read 6, iclass 27, count 0 2006.285.14:12:44.12#ibcon#end of sib2, iclass 27, count 0 2006.285.14:12:44.12#ibcon#*after write, iclass 27, count 0 2006.285.14:12:44.12#ibcon#*before return 0, iclass 27, count 0 2006.285.14:12:44.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:12:44.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:12:44.12#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.14:12:44.12#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.14:12:44.13$setupk4/ifdk4 2006.285.14:12:44.13$ifdk4/lo= 2006.285.14:12:44.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.14:12:44.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.14:12:44.13$ifdk4/patch= 2006.285.14:12:44.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.14:12:44.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.14:12:44.13$setupk4/!*+20s 2006.285.14:12:49.14#trakl#Source acquired 2006.285.14:12:49.15#flagr#flagr/antenna,acquired 2006.285.14:12:49.99#abcon#<5=/04 1.9 3.8 19.17 961015.1\r\n> 2006.285.14:12:50.01#abcon#{5=INTERFACE CLEAR} 2006.285.14:12:50.07#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:12:57.41$setupk4/"tpicd 2006.285.14:12:57.41$setupk4/echo=off 2006.285.14:12:57.41$setupk4/xlog=off 2006.285.14:12:57.41:!2006.285.14:17:52 2006.285.14:17:52.00:preob 2006.285.14:17:53.14/onsource/TRACKING 2006.285.14:17:53.14:!2006.285.14:18:02 2006.285.14:18:02.00:"tape 2006.285.14:18:02.00:"st=record 2006.285.14:18:02.00:data_valid=on 2006.285.14:18:02.00:midob 2006.285.14:18:02.14/onsource/TRACKING 2006.285.14:18:02.14/wx/19.19,1015.1,96 2006.285.14:18:02.34/cable/+6.4990E-03 2006.285.14:18:03.43/va/01,07,usb,yes,33,35 2006.285.14:18:03.43/va/02,06,usb,yes,33,33 2006.285.14:18:03.43/va/03,07,usb,yes,32,34 2006.285.14:18:03.43/va/04,06,usb,yes,34,35 2006.285.14:18:03.43/va/05,03,usb,yes,33,34 2006.285.14:18:03.43/va/06,04,usb,yes,30,29 2006.285.14:18:03.43/va/07,04,usb,yes,30,31 2006.285.14:18:03.43/va/08,03,usb,yes,31,38 2006.285.14:18:03.66/valo/01,524.99,yes,locked 2006.285.14:18:03.66/valo/02,534.99,yes,locked 2006.285.14:18:03.66/valo/03,564.99,yes,locked 2006.285.14:18:03.66/valo/04,624.99,yes,locked 2006.285.14:18:03.66/valo/05,734.99,yes,locked 2006.285.14:18:03.66/valo/06,814.99,yes,locked 2006.285.14:18:03.66/valo/07,864.99,yes,locked 2006.285.14:18:03.66/valo/08,884.99,yes,locked 2006.285.14:18:04.75/vb/01,04,usb,yes,30,28 2006.285.14:18:04.75/vb/02,05,usb,yes,28,28 2006.285.14:18:04.75/vb/03,04,usb,yes,30,32 2006.285.14:18:04.75/vb/04,05,usb,yes,30,29 2006.285.14:18:04.75/vb/05,04,usb,yes,26,29 2006.285.14:18:04.75/vb/06,03,usb,yes,38,33 2006.285.14:18:04.75/vb/07,04,usb,yes,30,30 2006.285.14:18:04.75/vb/08,04,usb,yes,28,31 2006.285.14:18:04.99/vblo/01,629.99,yes,locked 2006.285.14:18:04.99/vblo/02,634.99,yes,locked 2006.285.14:18:04.99/vblo/03,649.99,yes,locked 2006.285.14:18:04.99/vblo/04,679.99,yes,locked 2006.285.14:18:04.99/vblo/05,709.99,yes,locked 2006.285.14:18:04.99/vblo/06,719.99,yes,locked 2006.285.14:18:04.99/vblo/07,734.99,yes,locked 2006.285.14:18:04.99/vblo/08,744.99,yes,locked 2006.285.14:18:05.14/vabw/8 2006.285.14:18:05.29/vbbw/8 2006.285.14:18:05.54/xfe/off,on,12.2 2006.285.14:18:05.91/ifatt/23,28,28,28 2006.285.14:18:06.07/fmout-gps/S +2.72E-07 2006.285.14:18:06.09:!2006.285.14:19:02 2006.285.14:19:02.01:data_valid=off 2006.285.14:19:02.01:"et 2006.285.14:19:02.01:!+3s 2006.285.14:19:05.02:"tape 2006.285.14:19:05.02:postob 2006.285.14:19:05.12/cable/+6.4992E-03 2006.285.14:19:05.12/wx/19.20,1015.1,96 2006.285.14:19:05.18/fmout-gps/S +2.73E-07 2006.285.14:19:05.18:scan_name=285-1420,jd0610,170 2006.285.14:19:05.18:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.285.14:19:06.13#flagr#flagr/antenna,new-source 2006.285.14:19:06.13:checkk5 2006.285.14:19:06.66/chk_autoobs//k5ts1/ autoobs is running! 2006.285.14:19:07.10/chk_autoobs//k5ts2/ autoobs is running! 2006.285.14:19:07.61/chk_autoobs//k5ts3/ autoobs is running! 2006.285.14:19:08.00/chk_autoobs//k5ts4/ autoobs is running! 2006.285.14:19:08.61/chk_obsdata//k5ts1/T2851418??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.14:19:08.95/chk_obsdata//k5ts2/T2851418??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.14:19:09.52/chk_obsdata//k5ts3/T2851418??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.14:19:09.99/chk_obsdata//k5ts4/T2851418??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.14:19:11.00/k5log//k5ts1_log_newline 2006.285.14:19:12.31/k5log//k5ts2_log_newline 2006.285.14:19:13.16/k5log//k5ts3_log_newline 2006.285.14:19:14.45/k5log//k5ts4_log_newline 2006.285.14:19:14.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.14:19:14.47:setupk4=1 2006.285.14:19:14.47$setupk4/echo=on 2006.285.14:19:14.47$setupk4/pcalon 2006.285.14:19:14.47$pcalon/"no phase cal control is implemented here 2006.285.14:19:14.47$setupk4/"tpicd=stop 2006.285.14:19:14.47$setupk4/"rec=synch_on 2006.285.14:19:14.47$setupk4/"rec_mode=128 2006.285.14:19:14.47$setupk4/!* 2006.285.14:19:14.47$setupk4/recpk4 2006.285.14:19:14.48$recpk4/recpatch= 2006.285.14:19:14.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.14:19:14.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.14:19:14.48$setupk4/vck44 2006.285.14:19:14.48$vck44/valo=1,524.99 2006.285.14:19:14.48#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.14:19:14.48#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.14:19:14.48#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:14.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:19:14.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:19:14.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:19:14.48#ibcon#enter wrdev, iclass 40, count 0 2006.285.14:19:14.48#ibcon#first serial, iclass 40, count 0 2006.285.14:19:14.48#ibcon#enter sib2, iclass 40, count 0 2006.285.14:19:14.48#ibcon#flushed, iclass 40, count 0 2006.285.14:19:14.48#ibcon#about to write, iclass 40, count 0 2006.285.14:19:14.48#ibcon#wrote, iclass 40, count 0 2006.285.14:19:14.48#ibcon#about to read 3, iclass 40, count 0 2006.285.14:19:14.49#ibcon#read 3, iclass 40, count 0 2006.285.14:19:14.49#ibcon#about to read 4, iclass 40, count 0 2006.285.14:19:14.49#ibcon#read 4, iclass 40, count 0 2006.285.14:19:14.49#ibcon#about to read 5, iclass 40, count 0 2006.285.14:19:14.49#ibcon#read 5, iclass 40, count 0 2006.285.14:19:14.49#ibcon#about to read 6, iclass 40, count 0 2006.285.14:19:14.49#ibcon#read 6, iclass 40, count 0 2006.285.14:19:14.49#ibcon#end of sib2, iclass 40, count 0 2006.285.14:19:14.49#ibcon#*mode == 0, iclass 40, count 0 2006.285.14:19:14.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.14:19:14.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.14:19:14.49#ibcon#*before write, iclass 40, count 0 2006.285.14:19:14.49#ibcon#enter sib2, iclass 40, count 0 2006.285.14:19:14.49#ibcon#flushed, iclass 40, count 0 2006.285.14:19:14.49#ibcon#about to write, iclass 40, count 0 2006.285.14:19:14.49#ibcon#wrote, iclass 40, count 0 2006.285.14:19:14.49#ibcon#about to read 3, iclass 40, count 0 2006.285.14:19:14.54#ibcon#read 3, iclass 40, count 0 2006.285.14:19:14.54#ibcon#about to read 4, iclass 40, count 0 2006.285.14:19:14.54#ibcon#read 4, iclass 40, count 0 2006.285.14:19:14.54#ibcon#about to read 5, iclass 40, count 0 2006.285.14:19:14.54#ibcon#read 5, iclass 40, count 0 2006.285.14:19:14.54#ibcon#about to read 6, iclass 40, count 0 2006.285.14:19:14.54#ibcon#read 6, iclass 40, count 0 2006.285.14:19:14.54#ibcon#end of sib2, iclass 40, count 0 2006.285.14:19:14.54#ibcon#*after write, iclass 40, count 0 2006.285.14:19:14.54#ibcon#*before return 0, iclass 40, count 0 2006.285.14:19:14.54#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:19:14.54#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:19:14.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.14:19:14.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.14:19:14.54$vck44/va=1,7 2006.285.14:19:14.54#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.14:19:14.54#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.14:19:14.54#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:14.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:19:14.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:19:14.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:19:14.54#ibcon#enter wrdev, iclass 4, count 2 2006.285.14:19:14.54#ibcon#first serial, iclass 4, count 2 2006.285.14:19:14.54#ibcon#enter sib2, iclass 4, count 2 2006.285.14:19:14.54#ibcon#flushed, iclass 4, count 2 2006.285.14:19:14.54#ibcon#about to write, iclass 4, count 2 2006.285.14:19:14.54#ibcon#wrote, iclass 4, count 2 2006.285.14:19:14.54#ibcon#about to read 3, iclass 4, count 2 2006.285.14:19:14.56#ibcon#read 3, iclass 4, count 2 2006.285.14:19:14.56#ibcon#about to read 4, iclass 4, count 2 2006.285.14:19:14.56#ibcon#read 4, iclass 4, count 2 2006.285.14:19:14.56#ibcon#about to read 5, iclass 4, count 2 2006.285.14:19:14.56#ibcon#read 5, iclass 4, count 2 2006.285.14:19:14.56#ibcon#about to read 6, iclass 4, count 2 2006.285.14:19:14.56#ibcon#read 6, iclass 4, count 2 2006.285.14:19:14.56#ibcon#end of sib2, iclass 4, count 2 2006.285.14:19:14.56#ibcon#*mode == 0, iclass 4, count 2 2006.285.14:19:14.56#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.14:19:14.56#ibcon#[25=AT01-07\r\n] 2006.285.14:19:14.56#ibcon#*before write, iclass 4, count 2 2006.285.14:19:14.56#ibcon#enter sib2, iclass 4, count 2 2006.285.14:19:14.56#ibcon#flushed, iclass 4, count 2 2006.285.14:19:14.56#ibcon#about to write, iclass 4, count 2 2006.285.14:19:14.56#ibcon#wrote, iclass 4, count 2 2006.285.14:19:14.56#ibcon#about to read 3, iclass 4, count 2 2006.285.14:19:14.59#ibcon#read 3, iclass 4, count 2 2006.285.14:19:14.59#ibcon#about to read 4, iclass 4, count 2 2006.285.14:19:14.59#ibcon#read 4, iclass 4, count 2 2006.285.14:19:14.59#ibcon#about to read 5, iclass 4, count 2 2006.285.14:19:14.59#ibcon#read 5, iclass 4, count 2 2006.285.14:19:14.59#ibcon#about to read 6, iclass 4, count 2 2006.285.14:19:14.59#ibcon#read 6, iclass 4, count 2 2006.285.14:19:14.59#ibcon#end of sib2, iclass 4, count 2 2006.285.14:19:14.59#ibcon#*after write, iclass 4, count 2 2006.285.14:19:14.59#ibcon#*before return 0, iclass 4, count 2 2006.285.14:19:14.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:19:14.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:19:14.59#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.14:19:14.59#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:14.59#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:19:14.71#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:19:14.71#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:19:14.71#ibcon#enter wrdev, iclass 4, count 0 2006.285.14:19:14.71#ibcon#first serial, iclass 4, count 0 2006.285.14:19:14.71#ibcon#enter sib2, iclass 4, count 0 2006.285.14:19:14.71#ibcon#flushed, iclass 4, count 0 2006.285.14:19:14.71#ibcon#about to write, iclass 4, count 0 2006.285.14:19:14.71#ibcon#wrote, iclass 4, count 0 2006.285.14:19:14.71#ibcon#about to read 3, iclass 4, count 0 2006.285.14:19:14.73#ibcon#read 3, iclass 4, count 0 2006.285.14:19:14.73#ibcon#about to read 4, iclass 4, count 0 2006.285.14:19:14.73#ibcon#read 4, iclass 4, count 0 2006.285.14:19:14.73#ibcon#about to read 5, iclass 4, count 0 2006.285.14:19:14.73#ibcon#read 5, iclass 4, count 0 2006.285.14:19:14.73#ibcon#about to read 6, iclass 4, count 0 2006.285.14:19:14.73#ibcon#read 6, iclass 4, count 0 2006.285.14:19:14.73#ibcon#end of sib2, iclass 4, count 0 2006.285.14:19:14.73#ibcon#*mode == 0, iclass 4, count 0 2006.285.14:19:14.73#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.14:19:14.73#ibcon#[25=USB\r\n] 2006.285.14:19:14.73#ibcon#*before write, iclass 4, count 0 2006.285.14:19:14.73#ibcon#enter sib2, iclass 4, count 0 2006.285.14:19:14.73#ibcon#flushed, iclass 4, count 0 2006.285.14:19:14.73#ibcon#about to write, iclass 4, count 0 2006.285.14:19:14.73#ibcon#wrote, iclass 4, count 0 2006.285.14:19:14.73#ibcon#about to read 3, iclass 4, count 0 2006.285.14:19:14.76#ibcon#read 3, iclass 4, count 0 2006.285.14:19:14.76#ibcon#about to read 4, iclass 4, count 0 2006.285.14:19:14.76#ibcon#read 4, iclass 4, count 0 2006.285.14:19:14.76#ibcon#about to read 5, iclass 4, count 0 2006.285.14:19:14.76#ibcon#read 5, iclass 4, count 0 2006.285.14:19:14.76#ibcon#about to read 6, iclass 4, count 0 2006.285.14:19:14.76#ibcon#read 6, iclass 4, count 0 2006.285.14:19:14.76#ibcon#end of sib2, iclass 4, count 0 2006.285.14:19:14.76#ibcon#*after write, iclass 4, count 0 2006.285.14:19:14.76#ibcon#*before return 0, iclass 4, count 0 2006.285.14:19:14.76#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:19:14.76#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:19:14.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.14:19:14.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.14:19:14.76$vck44/valo=2,534.99 2006.285.14:19:14.76#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.14:19:14.76#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.14:19:14.76#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:14.76#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:19:14.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:19:14.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:19:14.76#ibcon#enter wrdev, iclass 6, count 0 2006.285.14:19:14.76#ibcon#first serial, iclass 6, count 0 2006.285.14:19:14.76#ibcon#enter sib2, iclass 6, count 0 2006.285.14:19:14.76#ibcon#flushed, iclass 6, count 0 2006.285.14:19:14.76#ibcon#about to write, iclass 6, count 0 2006.285.14:19:14.76#ibcon#wrote, iclass 6, count 0 2006.285.14:19:14.76#ibcon#about to read 3, iclass 6, count 0 2006.285.14:19:14.78#ibcon#read 3, iclass 6, count 0 2006.285.14:19:14.78#ibcon#about to read 4, iclass 6, count 0 2006.285.14:19:14.78#ibcon#read 4, iclass 6, count 0 2006.285.14:19:14.78#ibcon#about to read 5, iclass 6, count 0 2006.285.14:19:14.78#ibcon#read 5, iclass 6, count 0 2006.285.14:19:14.78#ibcon#about to read 6, iclass 6, count 0 2006.285.14:19:14.78#ibcon#read 6, iclass 6, count 0 2006.285.14:19:14.78#ibcon#end of sib2, iclass 6, count 0 2006.285.14:19:14.78#ibcon#*mode == 0, iclass 6, count 0 2006.285.14:19:14.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.14:19:14.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.14:19:14.78#ibcon#*before write, iclass 6, count 0 2006.285.14:19:14.78#ibcon#enter sib2, iclass 6, count 0 2006.285.14:19:14.78#ibcon#flushed, iclass 6, count 0 2006.285.14:19:14.78#ibcon#about to write, iclass 6, count 0 2006.285.14:19:14.78#ibcon#wrote, iclass 6, count 0 2006.285.14:19:14.78#ibcon#about to read 3, iclass 6, count 0 2006.285.14:19:14.82#ibcon#read 3, iclass 6, count 0 2006.285.14:19:14.82#ibcon#about to read 4, iclass 6, count 0 2006.285.14:19:14.82#ibcon#read 4, iclass 6, count 0 2006.285.14:19:14.82#ibcon#about to read 5, iclass 6, count 0 2006.285.14:19:14.82#ibcon#read 5, iclass 6, count 0 2006.285.14:19:14.82#ibcon#about to read 6, iclass 6, count 0 2006.285.14:19:14.82#ibcon#read 6, iclass 6, count 0 2006.285.14:19:14.82#ibcon#end of sib2, iclass 6, count 0 2006.285.14:19:14.82#ibcon#*after write, iclass 6, count 0 2006.285.14:19:14.82#ibcon#*before return 0, iclass 6, count 0 2006.285.14:19:14.82#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:19:14.82#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:19:14.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.14:19:14.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.14:19:14.82$vck44/va=2,6 2006.285.14:19:14.82#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.14:19:14.82#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.14:19:14.82#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:14.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:19:14.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:19:14.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:19:14.88#ibcon#enter wrdev, iclass 10, count 2 2006.285.14:19:14.88#ibcon#first serial, iclass 10, count 2 2006.285.14:19:14.88#ibcon#enter sib2, iclass 10, count 2 2006.285.14:19:14.88#ibcon#flushed, iclass 10, count 2 2006.285.14:19:14.88#ibcon#about to write, iclass 10, count 2 2006.285.14:19:14.88#ibcon#wrote, iclass 10, count 2 2006.285.14:19:14.88#ibcon#about to read 3, iclass 10, count 2 2006.285.14:19:14.90#ibcon#read 3, iclass 10, count 2 2006.285.14:19:14.90#ibcon#about to read 4, iclass 10, count 2 2006.285.14:19:14.90#ibcon#read 4, iclass 10, count 2 2006.285.14:19:14.90#ibcon#about to read 5, iclass 10, count 2 2006.285.14:19:14.90#ibcon#read 5, iclass 10, count 2 2006.285.14:19:14.90#ibcon#about to read 6, iclass 10, count 2 2006.285.14:19:14.90#ibcon#read 6, iclass 10, count 2 2006.285.14:19:14.90#ibcon#end of sib2, iclass 10, count 2 2006.285.14:19:14.90#ibcon#*mode == 0, iclass 10, count 2 2006.285.14:19:14.90#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.14:19:14.90#ibcon#[25=AT02-06\r\n] 2006.285.14:19:14.90#ibcon#*before write, iclass 10, count 2 2006.285.14:19:14.90#ibcon#enter sib2, iclass 10, count 2 2006.285.14:19:14.90#ibcon#flushed, iclass 10, count 2 2006.285.14:19:14.90#ibcon#about to write, iclass 10, count 2 2006.285.14:19:14.90#ibcon#wrote, iclass 10, count 2 2006.285.14:19:14.90#ibcon#about to read 3, iclass 10, count 2 2006.285.14:19:14.93#ibcon#read 3, iclass 10, count 2 2006.285.14:19:14.93#ibcon#about to read 4, iclass 10, count 2 2006.285.14:19:14.93#ibcon#read 4, iclass 10, count 2 2006.285.14:19:14.93#ibcon#about to read 5, iclass 10, count 2 2006.285.14:19:14.93#ibcon#read 5, iclass 10, count 2 2006.285.14:19:14.93#ibcon#about to read 6, iclass 10, count 2 2006.285.14:19:14.93#ibcon#read 6, iclass 10, count 2 2006.285.14:19:14.93#ibcon#end of sib2, iclass 10, count 2 2006.285.14:19:14.93#ibcon#*after write, iclass 10, count 2 2006.285.14:19:14.93#ibcon#*before return 0, iclass 10, count 2 2006.285.14:19:14.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:19:14.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:19:14.93#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.14:19:14.93#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:14.93#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:19:15.05#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:19:15.05#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:19:15.05#ibcon#enter wrdev, iclass 10, count 0 2006.285.14:19:15.05#ibcon#first serial, iclass 10, count 0 2006.285.14:19:15.05#ibcon#enter sib2, iclass 10, count 0 2006.285.14:19:15.05#ibcon#flushed, iclass 10, count 0 2006.285.14:19:15.05#ibcon#about to write, iclass 10, count 0 2006.285.14:19:15.05#ibcon#wrote, iclass 10, count 0 2006.285.14:19:15.05#ibcon#about to read 3, iclass 10, count 0 2006.285.14:19:15.07#ibcon#read 3, iclass 10, count 0 2006.285.14:19:15.07#ibcon#about to read 4, iclass 10, count 0 2006.285.14:19:15.07#ibcon#read 4, iclass 10, count 0 2006.285.14:19:15.07#ibcon#about to read 5, iclass 10, count 0 2006.285.14:19:15.07#ibcon#read 5, iclass 10, count 0 2006.285.14:19:15.07#ibcon#about to read 6, iclass 10, count 0 2006.285.14:19:15.07#ibcon#read 6, iclass 10, count 0 2006.285.14:19:15.07#ibcon#end of sib2, iclass 10, count 0 2006.285.14:19:15.07#ibcon#*mode == 0, iclass 10, count 0 2006.285.14:19:15.07#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.14:19:15.07#ibcon#[25=USB\r\n] 2006.285.14:19:15.07#ibcon#*before write, iclass 10, count 0 2006.285.14:19:15.07#ibcon#enter sib2, iclass 10, count 0 2006.285.14:19:15.07#ibcon#flushed, iclass 10, count 0 2006.285.14:19:15.07#ibcon#about to write, iclass 10, count 0 2006.285.14:19:15.07#ibcon#wrote, iclass 10, count 0 2006.285.14:19:15.07#ibcon#about to read 3, iclass 10, count 0 2006.285.14:19:15.10#ibcon#read 3, iclass 10, count 0 2006.285.14:19:15.10#ibcon#about to read 4, iclass 10, count 0 2006.285.14:19:15.10#ibcon#read 4, iclass 10, count 0 2006.285.14:19:15.10#ibcon#about to read 5, iclass 10, count 0 2006.285.14:19:15.10#ibcon#read 5, iclass 10, count 0 2006.285.14:19:15.10#ibcon#about to read 6, iclass 10, count 0 2006.285.14:19:15.10#ibcon#read 6, iclass 10, count 0 2006.285.14:19:15.10#ibcon#end of sib2, iclass 10, count 0 2006.285.14:19:15.10#ibcon#*after write, iclass 10, count 0 2006.285.14:19:15.10#ibcon#*before return 0, iclass 10, count 0 2006.285.14:19:15.10#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:19:15.10#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:19:15.10#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.14:19:15.10#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.14:19:15.10$vck44/valo=3,564.99 2006.285.14:19:15.10#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.14:19:15.10#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.14:19:15.10#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:15.10#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:19:15.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:19:15.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:19:15.10#ibcon#enter wrdev, iclass 12, count 0 2006.285.14:19:15.10#ibcon#first serial, iclass 12, count 0 2006.285.14:19:15.10#ibcon#enter sib2, iclass 12, count 0 2006.285.14:19:15.10#ibcon#flushed, iclass 12, count 0 2006.285.14:19:15.10#ibcon#about to write, iclass 12, count 0 2006.285.14:19:15.10#ibcon#wrote, iclass 12, count 0 2006.285.14:19:15.10#ibcon#about to read 3, iclass 12, count 0 2006.285.14:19:15.12#ibcon#read 3, iclass 12, count 0 2006.285.14:19:15.12#ibcon#about to read 4, iclass 12, count 0 2006.285.14:19:15.12#ibcon#read 4, iclass 12, count 0 2006.285.14:19:15.12#ibcon#about to read 5, iclass 12, count 0 2006.285.14:19:15.12#ibcon#read 5, iclass 12, count 0 2006.285.14:19:15.12#ibcon#about to read 6, iclass 12, count 0 2006.285.14:19:15.12#ibcon#read 6, iclass 12, count 0 2006.285.14:19:15.12#ibcon#end of sib2, iclass 12, count 0 2006.285.14:19:15.12#ibcon#*mode == 0, iclass 12, count 0 2006.285.14:19:15.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.14:19:15.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.14:19:15.12#ibcon#*before write, iclass 12, count 0 2006.285.14:19:15.12#ibcon#enter sib2, iclass 12, count 0 2006.285.14:19:15.12#ibcon#flushed, iclass 12, count 0 2006.285.14:19:15.12#ibcon#about to write, iclass 12, count 0 2006.285.14:19:15.12#ibcon#wrote, iclass 12, count 0 2006.285.14:19:15.12#ibcon#about to read 3, iclass 12, count 0 2006.285.14:19:15.16#ibcon#read 3, iclass 12, count 0 2006.285.14:19:15.16#ibcon#about to read 4, iclass 12, count 0 2006.285.14:19:15.16#ibcon#read 4, iclass 12, count 0 2006.285.14:19:15.16#ibcon#about to read 5, iclass 12, count 0 2006.285.14:19:15.16#ibcon#read 5, iclass 12, count 0 2006.285.14:19:15.16#ibcon#about to read 6, iclass 12, count 0 2006.285.14:19:15.16#ibcon#read 6, iclass 12, count 0 2006.285.14:19:15.16#ibcon#end of sib2, iclass 12, count 0 2006.285.14:19:15.16#ibcon#*after write, iclass 12, count 0 2006.285.14:19:15.16#ibcon#*before return 0, iclass 12, count 0 2006.285.14:19:15.16#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:19:15.16#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:19:15.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.14:19:15.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.14:19:15.16$vck44/va=3,7 2006.285.14:19:15.16#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.14:19:15.16#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.14:19:15.16#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:15.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:19:15.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:19:15.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:19:15.22#ibcon#enter wrdev, iclass 14, count 2 2006.285.14:19:15.22#ibcon#first serial, iclass 14, count 2 2006.285.14:19:15.22#ibcon#enter sib2, iclass 14, count 2 2006.285.14:19:15.22#ibcon#flushed, iclass 14, count 2 2006.285.14:19:15.22#ibcon#about to write, iclass 14, count 2 2006.285.14:19:15.22#ibcon#wrote, iclass 14, count 2 2006.285.14:19:15.22#ibcon#about to read 3, iclass 14, count 2 2006.285.14:19:15.24#ibcon#read 3, iclass 14, count 2 2006.285.14:19:15.24#ibcon#about to read 4, iclass 14, count 2 2006.285.14:19:15.24#ibcon#read 4, iclass 14, count 2 2006.285.14:19:15.24#ibcon#about to read 5, iclass 14, count 2 2006.285.14:19:15.24#ibcon#read 5, iclass 14, count 2 2006.285.14:19:15.24#ibcon#about to read 6, iclass 14, count 2 2006.285.14:19:15.24#ibcon#read 6, iclass 14, count 2 2006.285.14:19:15.24#ibcon#end of sib2, iclass 14, count 2 2006.285.14:19:15.24#ibcon#*mode == 0, iclass 14, count 2 2006.285.14:19:15.24#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.14:19:15.24#ibcon#[25=AT03-07\r\n] 2006.285.14:19:15.24#ibcon#*before write, iclass 14, count 2 2006.285.14:19:15.24#ibcon#enter sib2, iclass 14, count 2 2006.285.14:19:15.24#ibcon#flushed, iclass 14, count 2 2006.285.14:19:15.24#ibcon#about to write, iclass 14, count 2 2006.285.14:19:15.24#ibcon#wrote, iclass 14, count 2 2006.285.14:19:15.24#ibcon#about to read 3, iclass 14, count 2 2006.285.14:19:15.27#ibcon#read 3, iclass 14, count 2 2006.285.14:19:15.27#ibcon#about to read 4, iclass 14, count 2 2006.285.14:19:15.27#ibcon#read 4, iclass 14, count 2 2006.285.14:19:15.27#ibcon#about to read 5, iclass 14, count 2 2006.285.14:19:15.27#ibcon#read 5, iclass 14, count 2 2006.285.14:19:15.27#ibcon#about to read 6, iclass 14, count 2 2006.285.14:19:15.27#ibcon#read 6, iclass 14, count 2 2006.285.14:19:15.27#ibcon#end of sib2, iclass 14, count 2 2006.285.14:19:15.27#ibcon#*after write, iclass 14, count 2 2006.285.14:19:15.27#ibcon#*before return 0, iclass 14, count 2 2006.285.14:19:15.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:19:15.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:19:15.27#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.14:19:15.27#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:15.27#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:19:15.39#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:19:15.39#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:19:15.39#ibcon#enter wrdev, iclass 14, count 0 2006.285.14:19:15.39#ibcon#first serial, iclass 14, count 0 2006.285.14:19:15.39#ibcon#enter sib2, iclass 14, count 0 2006.285.14:19:15.39#ibcon#flushed, iclass 14, count 0 2006.285.14:19:15.39#ibcon#about to write, iclass 14, count 0 2006.285.14:19:15.39#ibcon#wrote, iclass 14, count 0 2006.285.14:19:15.39#ibcon#about to read 3, iclass 14, count 0 2006.285.14:19:15.41#ibcon#read 3, iclass 14, count 0 2006.285.14:19:15.41#ibcon#about to read 4, iclass 14, count 0 2006.285.14:19:15.41#ibcon#read 4, iclass 14, count 0 2006.285.14:19:15.41#ibcon#about to read 5, iclass 14, count 0 2006.285.14:19:15.41#ibcon#read 5, iclass 14, count 0 2006.285.14:19:15.41#ibcon#about to read 6, iclass 14, count 0 2006.285.14:19:15.41#ibcon#read 6, iclass 14, count 0 2006.285.14:19:15.41#ibcon#end of sib2, iclass 14, count 0 2006.285.14:19:15.41#ibcon#*mode == 0, iclass 14, count 0 2006.285.14:19:15.41#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.14:19:15.41#ibcon#[25=USB\r\n] 2006.285.14:19:15.41#ibcon#*before write, iclass 14, count 0 2006.285.14:19:15.41#ibcon#enter sib2, iclass 14, count 0 2006.285.14:19:15.41#ibcon#flushed, iclass 14, count 0 2006.285.14:19:15.41#ibcon#about to write, iclass 14, count 0 2006.285.14:19:15.41#ibcon#wrote, iclass 14, count 0 2006.285.14:19:15.41#ibcon#about to read 3, iclass 14, count 0 2006.285.14:19:15.44#ibcon#read 3, iclass 14, count 0 2006.285.14:19:15.44#ibcon#about to read 4, iclass 14, count 0 2006.285.14:19:15.82#ibcon#read 4, iclass 14, count 0 2006.285.14:19:15.82#ibcon#about to read 5, iclass 14, count 0 2006.285.14:19:15.82#ibcon#read 5, iclass 14, count 0 2006.285.14:19:15.82#ibcon#about to read 6, iclass 14, count 0 2006.285.14:19:15.82#ibcon#read 6, iclass 14, count 0 2006.285.14:19:15.82#ibcon#end of sib2, iclass 14, count 0 2006.285.14:19:15.82#ibcon#*after write, iclass 14, count 0 2006.285.14:19:15.82#ibcon#*before return 0, iclass 14, count 0 2006.285.14:19:15.82#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:19:15.82#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:19:15.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.14:19:15.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.14:19:15.82$vck44/valo=4,624.99 2006.285.14:19:15.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.14:19:15.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.14:19:15.82#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:15.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:19:15.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:19:15.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:19:15.82#ibcon#enter wrdev, iclass 16, count 0 2006.285.14:19:15.82#ibcon#first serial, iclass 16, count 0 2006.285.14:19:15.82#ibcon#enter sib2, iclass 16, count 0 2006.285.14:19:15.82#ibcon#flushed, iclass 16, count 0 2006.285.14:19:15.82#ibcon#about to write, iclass 16, count 0 2006.285.14:19:15.82#ibcon#wrote, iclass 16, count 0 2006.285.14:19:15.82#ibcon#about to read 3, iclass 16, count 0 2006.285.14:19:15.83#ibcon#read 3, iclass 16, count 0 2006.285.14:19:15.83#ibcon#about to read 4, iclass 16, count 0 2006.285.14:19:15.83#ibcon#read 4, iclass 16, count 0 2006.285.14:19:15.83#ibcon#about to read 5, iclass 16, count 0 2006.285.14:19:15.83#ibcon#read 5, iclass 16, count 0 2006.285.14:19:15.83#ibcon#about to read 6, iclass 16, count 0 2006.285.14:19:15.83#ibcon#read 6, iclass 16, count 0 2006.285.14:19:15.83#ibcon#end of sib2, iclass 16, count 0 2006.285.14:19:15.83#ibcon#*mode == 0, iclass 16, count 0 2006.285.14:19:15.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.14:19:15.83#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.14:19:15.83#ibcon#*before write, iclass 16, count 0 2006.285.14:19:15.83#ibcon#enter sib2, iclass 16, count 0 2006.285.14:19:15.83#ibcon#flushed, iclass 16, count 0 2006.285.14:19:15.83#ibcon#about to write, iclass 16, count 0 2006.285.14:19:15.83#ibcon#wrote, iclass 16, count 0 2006.285.14:19:15.83#ibcon#about to read 3, iclass 16, count 0 2006.285.14:19:15.87#ibcon#read 3, iclass 16, count 0 2006.285.14:19:15.87#ibcon#about to read 4, iclass 16, count 0 2006.285.14:19:15.87#ibcon#read 4, iclass 16, count 0 2006.285.14:19:15.87#ibcon#about to read 5, iclass 16, count 0 2006.285.14:19:15.87#ibcon#read 5, iclass 16, count 0 2006.285.14:19:15.87#ibcon#about to read 6, iclass 16, count 0 2006.285.14:19:15.87#ibcon#read 6, iclass 16, count 0 2006.285.14:19:15.87#ibcon#end of sib2, iclass 16, count 0 2006.285.14:19:15.87#ibcon#*after write, iclass 16, count 0 2006.285.14:19:15.87#ibcon#*before return 0, iclass 16, count 0 2006.285.14:19:15.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:19:15.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:19:15.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.14:19:15.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.14:19:15.87$vck44/va=4,6 2006.285.14:19:15.87#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.14:19:15.87#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.14:19:15.87#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:15.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:19:15.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:19:15.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:19:15.94#ibcon#enter wrdev, iclass 18, count 2 2006.285.14:19:15.94#ibcon#first serial, iclass 18, count 2 2006.285.14:19:15.94#ibcon#enter sib2, iclass 18, count 2 2006.285.14:19:15.94#ibcon#flushed, iclass 18, count 2 2006.285.14:19:15.94#ibcon#about to write, iclass 18, count 2 2006.285.14:19:15.94#ibcon#wrote, iclass 18, count 2 2006.285.14:19:15.94#ibcon#about to read 3, iclass 18, count 2 2006.285.14:19:15.96#ibcon#read 3, iclass 18, count 2 2006.285.14:19:15.96#ibcon#about to read 4, iclass 18, count 2 2006.285.14:19:15.96#ibcon#read 4, iclass 18, count 2 2006.285.14:19:15.96#ibcon#about to read 5, iclass 18, count 2 2006.285.14:19:15.96#ibcon#read 5, iclass 18, count 2 2006.285.14:19:15.96#ibcon#about to read 6, iclass 18, count 2 2006.285.14:19:15.96#ibcon#read 6, iclass 18, count 2 2006.285.14:19:15.96#ibcon#end of sib2, iclass 18, count 2 2006.285.14:19:15.96#ibcon#*mode == 0, iclass 18, count 2 2006.285.14:19:15.96#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.14:19:15.96#ibcon#[25=AT04-06\r\n] 2006.285.14:19:15.96#ibcon#*before write, iclass 18, count 2 2006.285.14:19:15.96#ibcon#enter sib2, iclass 18, count 2 2006.285.14:19:15.96#ibcon#flushed, iclass 18, count 2 2006.285.14:19:15.96#ibcon#about to write, iclass 18, count 2 2006.285.14:19:15.96#ibcon#wrote, iclass 18, count 2 2006.285.14:19:15.96#ibcon#about to read 3, iclass 18, count 2 2006.285.14:19:15.99#ibcon#read 3, iclass 18, count 2 2006.285.14:19:15.99#ibcon#about to read 4, iclass 18, count 2 2006.285.14:19:15.99#ibcon#read 4, iclass 18, count 2 2006.285.14:19:15.99#ibcon#about to read 5, iclass 18, count 2 2006.285.14:19:15.99#ibcon#read 5, iclass 18, count 2 2006.285.14:19:15.99#ibcon#about to read 6, iclass 18, count 2 2006.285.14:19:15.99#ibcon#read 6, iclass 18, count 2 2006.285.14:19:15.99#ibcon#end of sib2, iclass 18, count 2 2006.285.14:19:15.99#ibcon#*after write, iclass 18, count 2 2006.285.14:19:15.99#ibcon#*before return 0, iclass 18, count 2 2006.285.14:19:15.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:19:15.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:19:15.99#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.14:19:15.99#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:15.99#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:19:16.11#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:19:16.11#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:19:16.11#ibcon#enter wrdev, iclass 18, count 0 2006.285.14:19:16.11#ibcon#first serial, iclass 18, count 0 2006.285.14:19:16.11#ibcon#enter sib2, iclass 18, count 0 2006.285.14:19:16.11#ibcon#flushed, iclass 18, count 0 2006.285.14:19:16.11#ibcon#about to write, iclass 18, count 0 2006.285.14:19:16.11#ibcon#wrote, iclass 18, count 0 2006.285.14:19:16.11#ibcon#about to read 3, iclass 18, count 0 2006.285.14:19:16.13#ibcon#read 3, iclass 18, count 0 2006.285.14:19:16.13#ibcon#about to read 4, iclass 18, count 0 2006.285.14:19:16.13#ibcon#read 4, iclass 18, count 0 2006.285.14:19:16.13#ibcon#about to read 5, iclass 18, count 0 2006.285.14:19:16.13#ibcon#read 5, iclass 18, count 0 2006.285.14:19:16.13#ibcon#about to read 6, iclass 18, count 0 2006.285.14:19:16.13#ibcon#read 6, iclass 18, count 0 2006.285.14:19:16.13#ibcon#end of sib2, iclass 18, count 0 2006.285.14:19:16.13#ibcon#*mode == 0, iclass 18, count 0 2006.285.14:19:16.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.14:19:16.13#ibcon#[25=USB\r\n] 2006.285.14:19:16.13#ibcon#*before write, iclass 18, count 0 2006.285.14:19:16.13#ibcon#enter sib2, iclass 18, count 0 2006.285.14:19:16.13#ibcon#flushed, iclass 18, count 0 2006.285.14:19:16.13#ibcon#about to write, iclass 18, count 0 2006.285.14:19:16.13#ibcon#wrote, iclass 18, count 0 2006.285.14:19:16.13#ibcon#about to read 3, iclass 18, count 0 2006.285.14:19:16.16#ibcon#read 3, iclass 18, count 0 2006.285.14:19:16.16#ibcon#about to read 4, iclass 18, count 0 2006.285.14:19:16.16#ibcon#read 4, iclass 18, count 0 2006.285.14:19:16.16#ibcon#about to read 5, iclass 18, count 0 2006.285.14:19:16.16#ibcon#read 5, iclass 18, count 0 2006.285.14:19:16.16#ibcon#about to read 6, iclass 18, count 0 2006.285.14:19:16.16#ibcon#read 6, iclass 18, count 0 2006.285.14:19:16.16#ibcon#end of sib2, iclass 18, count 0 2006.285.14:19:16.16#ibcon#*after write, iclass 18, count 0 2006.285.14:19:16.16#ibcon#*before return 0, iclass 18, count 0 2006.285.14:19:16.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:19:16.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:19:16.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.14:19:16.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.14:19:16.16$vck44/valo=5,734.99 2006.285.14:19:16.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.14:19:16.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.14:19:16.16#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:16.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:19:16.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:19:16.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:19:16.16#ibcon#enter wrdev, iclass 20, count 0 2006.285.14:19:16.16#ibcon#first serial, iclass 20, count 0 2006.285.14:19:16.16#ibcon#enter sib2, iclass 20, count 0 2006.285.14:19:16.16#ibcon#flushed, iclass 20, count 0 2006.285.14:19:16.16#ibcon#about to write, iclass 20, count 0 2006.285.14:19:16.34#ibcon#wrote, iclass 20, count 0 2006.285.14:19:16.34#ibcon#about to read 3, iclass 20, count 0 2006.285.14:19:16.35#ibcon#read 3, iclass 20, count 0 2006.285.14:19:16.35#ibcon#about to read 4, iclass 20, count 0 2006.285.14:19:16.35#ibcon#read 4, iclass 20, count 0 2006.285.14:19:16.35#ibcon#about to read 5, iclass 20, count 0 2006.285.14:19:16.35#ibcon#read 5, iclass 20, count 0 2006.285.14:19:16.35#ibcon#about to read 6, iclass 20, count 0 2006.285.14:19:16.35#ibcon#read 6, iclass 20, count 0 2006.285.14:19:16.35#ibcon#end of sib2, iclass 20, count 0 2006.285.14:19:16.35#ibcon#*mode == 0, iclass 20, count 0 2006.285.14:19:16.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.14:19:16.35#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.14:19:16.35#ibcon#*before write, iclass 20, count 0 2006.285.14:19:16.35#ibcon#enter sib2, iclass 20, count 0 2006.285.14:19:16.35#ibcon#flushed, iclass 20, count 0 2006.285.14:19:16.35#ibcon#about to write, iclass 20, count 0 2006.285.14:19:16.35#ibcon#wrote, iclass 20, count 0 2006.285.14:19:16.35#ibcon#about to read 3, iclass 20, count 0 2006.285.14:19:16.39#ibcon#read 3, iclass 20, count 0 2006.285.14:19:16.39#ibcon#about to read 4, iclass 20, count 0 2006.285.14:19:16.39#ibcon#read 4, iclass 20, count 0 2006.285.14:19:16.39#ibcon#about to read 5, iclass 20, count 0 2006.285.14:19:16.39#ibcon#read 5, iclass 20, count 0 2006.285.14:19:16.39#ibcon#about to read 6, iclass 20, count 0 2006.285.14:19:16.39#ibcon#read 6, iclass 20, count 0 2006.285.14:19:16.39#ibcon#end of sib2, iclass 20, count 0 2006.285.14:19:16.39#ibcon#*after write, iclass 20, count 0 2006.285.14:19:16.39#ibcon#*before return 0, iclass 20, count 0 2006.285.14:19:16.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:19:16.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:19:16.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.14:19:16.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.14:19:16.39$vck44/va=5,3 2006.285.14:19:16.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.14:19:16.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.14:19:16.39#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:16.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:19:16.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:19:16.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:19:16.39#ibcon#enter wrdev, iclass 22, count 2 2006.285.14:19:16.39#ibcon#first serial, iclass 22, count 2 2006.285.14:19:16.39#ibcon#enter sib2, iclass 22, count 2 2006.285.14:19:16.39#ibcon#flushed, iclass 22, count 2 2006.285.14:19:16.39#ibcon#about to write, iclass 22, count 2 2006.285.14:19:16.39#ibcon#wrote, iclass 22, count 2 2006.285.14:19:16.39#ibcon#about to read 3, iclass 22, count 2 2006.285.14:19:16.41#ibcon#read 3, iclass 22, count 2 2006.285.14:19:16.41#ibcon#about to read 4, iclass 22, count 2 2006.285.14:19:16.41#ibcon#read 4, iclass 22, count 2 2006.285.14:19:16.41#ibcon#about to read 5, iclass 22, count 2 2006.285.14:19:16.41#ibcon#read 5, iclass 22, count 2 2006.285.14:19:16.41#ibcon#about to read 6, iclass 22, count 2 2006.285.14:19:16.41#ibcon#read 6, iclass 22, count 2 2006.285.14:19:16.41#ibcon#end of sib2, iclass 22, count 2 2006.285.14:19:16.41#ibcon#*mode == 0, iclass 22, count 2 2006.285.14:19:16.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.14:19:16.41#ibcon#[25=AT05-03\r\n] 2006.285.14:19:16.41#ibcon#*before write, iclass 22, count 2 2006.285.14:19:16.41#ibcon#enter sib2, iclass 22, count 2 2006.285.14:19:16.41#ibcon#flushed, iclass 22, count 2 2006.285.14:19:16.41#ibcon#about to write, iclass 22, count 2 2006.285.14:19:16.41#ibcon#wrote, iclass 22, count 2 2006.285.14:19:16.41#ibcon#about to read 3, iclass 22, count 2 2006.285.14:19:16.44#ibcon#read 3, iclass 22, count 2 2006.285.14:19:16.44#ibcon#about to read 4, iclass 22, count 2 2006.285.14:19:16.44#ibcon#read 4, iclass 22, count 2 2006.285.14:19:16.44#ibcon#about to read 5, iclass 22, count 2 2006.285.14:19:16.44#ibcon#read 5, iclass 22, count 2 2006.285.14:19:16.44#ibcon#about to read 6, iclass 22, count 2 2006.285.14:19:16.44#ibcon#read 6, iclass 22, count 2 2006.285.14:19:16.44#ibcon#end of sib2, iclass 22, count 2 2006.285.14:19:16.44#ibcon#*after write, iclass 22, count 2 2006.285.14:19:16.44#ibcon#*before return 0, iclass 22, count 2 2006.285.14:19:16.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:19:16.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:19:16.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.14:19:16.44#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:16.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:19:16.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:19:16.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:19:16.56#ibcon#enter wrdev, iclass 22, count 0 2006.285.14:19:16.56#ibcon#first serial, iclass 22, count 0 2006.285.14:19:16.56#ibcon#enter sib2, iclass 22, count 0 2006.285.14:19:16.56#ibcon#flushed, iclass 22, count 0 2006.285.14:19:16.56#ibcon#about to write, iclass 22, count 0 2006.285.14:19:16.56#ibcon#wrote, iclass 22, count 0 2006.285.14:19:16.56#ibcon#about to read 3, iclass 22, count 0 2006.285.14:19:16.58#ibcon#read 3, iclass 22, count 0 2006.285.14:19:16.58#ibcon#about to read 4, iclass 22, count 0 2006.285.14:19:16.58#ibcon#read 4, iclass 22, count 0 2006.285.14:19:16.58#ibcon#about to read 5, iclass 22, count 0 2006.285.14:19:16.58#ibcon#read 5, iclass 22, count 0 2006.285.14:19:16.58#ibcon#about to read 6, iclass 22, count 0 2006.285.14:19:16.58#ibcon#read 6, iclass 22, count 0 2006.285.14:19:16.58#ibcon#end of sib2, iclass 22, count 0 2006.285.14:19:16.58#ibcon#*mode == 0, iclass 22, count 0 2006.285.14:19:16.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.14:19:16.58#ibcon#[25=USB\r\n] 2006.285.14:19:16.58#ibcon#*before write, iclass 22, count 0 2006.285.14:19:16.58#ibcon#enter sib2, iclass 22, count 0 2006.285.14:19:16.58#ibcon#flushed, iclass 22, count 0 2006.285.14:19:16.58#ibcon#about to write, iclass 22, count 0 2006.285.14:19:16.58#ibcon#wrote, iclass 22, count 0 2006.285.14:19:16.58#ibcon#about to read 3, iclass 22, count 0 2006.285.14:19:16.61#ibcon#read 3, iclass 22, count 0 2006.285.14:19:16.61#ibcon#about to read 4, iclass 22, count 0 2006.285.14:19:16.61#ibcon#read 4, iclass 22, count 0 2006.285.14:19:16.61#ibcon#about to read 5, iclass 22, count 0 2006.285.14:19:16.61#ibcon#read 5, iclass 22, count 0 2006.285.14:19:16.61#ibcon#about to read 6, iclass 22, count 0 2006.285.14:19:16.61#ibcon#read 6, iclass 22, count 0 2006.285.14:19:16.61#ibcon#end of sib2, iclass 22, count 0 2006.285.14:19:16.61#ibcon#*after write, iclass 22, count 0 2006.285.14:19:16.61#ibcon#*before return 0, iclass 22, count 0 2006.285.14:19:16.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:19:16.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:19:16.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.14:19:16.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.14:19:16.61$vck44/valo=6,814.99 2006.285.14:19:16.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.14:19:16.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.14:19:16.61#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:16.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:19:16.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:19:16.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:19:16.61#ibcon#enter wrdev, iclass 24, count 0 2006.285.14:19:16.61#ibcon#first serial, iclass 24, count 0 2006.285.14:19:16.61#ibcon#enter sib2, iclass 24, count 0 2006.285.14:19:16.61#ibcon#flushed, iclass 24, count 0 2006.285.14:19:16.61#ibcon#about to write, iclass 24, count 0 2006.285.14:19:16.61#ibcon#wrote, iclass 24, count 0 2006.285.14:19:16.61#ibcon#about to read 3, iclass 24, count 0 2006.285.14:19:16.63#ibcon#read 3, iclass 24, count 0 2006.285.14:19:16.63#ibcon#about to read 4, iclass 24, count 0 2006.285.14:19:16.63#ibcon#read 4, iclass 24, count 0 2006.285.14:19:16.63#ibcon#about to read 5, iclass 24, count 0 2006.285.14:19:16.63#ibcon#read 5, iclass 24, count 0 2006.285.14:19:16.63#ibcon#about to read 6, iclass 24, count 0 2006.285.14:19:16.63#ibcon#read 6, iclass 24, count 0 2006.285.14:19:16.63#ibcon#end of sib2, iclass 24, count 0 2006.285.14:19:16.63#ibcon#*mode == 0, iclass 24, count 0 2006.285.14:19:16.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.14:19:16.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.14:19:16.63#ibcon#*before write, iclass 24, count 0 2006.285.14:19:16.63#ibcon#enter sib2, iclass 24, count 0 2006.285.14:19:16.63#ibcon#flushed, iclass 24, count 0 2006.285.14:19:16.63#ibcon#about to write, iclass 24, count 0 2006.285.14:19:16.63#ibcon#wrote, iclass 24, count 0 2006.285.14:19:16.63#ibcon#about to read 3, iclass 24, count 0 2006.285.14:19:16.67#ibcon#read 3, iclass 24, count 0 2006.285.14:19:16.67#ibcon#about to read 4, iclass 24, count 0 2006.285.14:19:16.67#ibcon#read 4, iclass 24, count 0 2006.285.14:19:16.67#ibcon#about to read 5, iclass 24, count 0 2006.285.14:19:16.67#ibcon#read 5, iclass 24, count 0 2006.285.14:19:16.67#ibcon#about to read 6, iclass 24, count 0 2006.285.14:19:16.67#ibcon#read 6, iclass 24, count 0 2006.285.14:19:16.67#ibcon#end of sib2, iclass 24, count 0 2006.285.14:19:16.67#ibcon#*after write, iclass 24, count 0 2006.285.14:19:16.67#ibcon#*before return 0, iclass 24, count 0 2006.285.14:19:16.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:19:16.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:19:16.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.14:19:16.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.14:19:16.67$vck44/va=6,4 2006.285.14:19:16.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.14:19:16.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.14:19:16.67#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:16.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:19:16.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:19:16.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:19:16.73#ibcon#enter wrdev, iclass 26, count 2 2006.285.14:19:16.73#ibcon#first serial, iclass 26, count 2 2006.285.14:19:16.73#ibcon#enter sib2, iclass 26, count 2 2006.285.14:19:16.73#ibcon#flushed, iclass 26, count 2 2006.285.14:19:16.73#ibcon#about to write, iclass 26, count 2 2006.285.14:19:16.73#ibcon#wrote, iclass 26, count 2 2006.285.14:19:16.73#ibcon#about to read 3, iclass 26, count 2 2006.285.14:19:16.75#ibcon#read 3, iclass 26, count 2 2006.285.14:19:16.75#ibcon#about to read 4, iclass 26, count 2 2006.285.14:19:16.75#ibcon#read 4, iclass 26, count 2 2006.285.14:19:16.75#ibcon#about to read 5, iclass 26, count 2 2006.285.14:19:16.75#ibcon#read 5, iclass 26, count 2 2006.285.14:19:16.75#ibcon#about to read 6, iclass 26, count 2 2006.285.14:19:16.75#ibcon#read 6, iclass 26, count 2 2006.285.14:19:16.75#ibcon#end of sib2, iclass 26, count 2 2006.285.14:19:16.75#ibcon#*mode == 0, iclass 26, count 2 2006.285.14:19:16.75#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.14:19:16.75#ibcon#[25=AT06-04\r\n] 2006.285.14:19:16.75#ibcon#*before write, iclass 26, count 2 2006.285.14:19:16.75#ibcon#enter sib2, iclass 26, count 2 2006.285.14:19:16.75#ibcon#flushed, iclass 26, count 2 2006.285.14:19:16.75#ibcon#about to write, iclass 26, count 2 2006.285.14:19:16.75#ibcon#wrote, iclass 26, count 2 2006.285.14:19:16.75#ibcon#about to read 3, iclass 26, count 2 2006.285.14:19:16.78#ibcon#read 3, iclass 26, count 2 2006.285.14:19:16.78#ibcon#about to read 4, iclass 26, count 2 2006.285.14:19:16.78#ibcon#read 4, iclass 26, count 2 2006.285.14:19:16.78#ibcon#about to read 5, iclass 26, count 2 2006.285.14:19:16.78#ibcon#read 5, iclass 26, count 2 2006.285.14:19:16.78#ibcon#about to read 6, iclass 26, count 2 2006.285.14:19:16.78#ibcon#read 6, iclass 26, count 2 2006.285.14:19:16.78#ibcon#end of sib2, iclass 26, count 2 2006.285.14:19:16.78#ibcon#*after write, iclass 26, count 2 2006.285.14:19:16.78#ibcon#*before return 0, iclass 26, count 2 2006.285.14:19:16.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:19:16.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:19:16.78#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.14:19:16.78#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:16.78#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:19:16.90#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:19:16.90#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:19:16.90#ibcon#enter wrdev, iclass 26, count 0 2006.285.14:19:16.90#ibcon#first serial, iclass 26, count 0 2006.285.14:19:16.90#ibcon#enter sib2, iclass 26, count 0 2006.285.14:19:16.90#ibcon#flushed, iclass 26, count 0 2006.285.14:19:16.90#ibcon#about to write, iclass 26, count 0 2006.285.14:19:16.90#ibcon#wrote, iclass 26, count 0 2006.285.14:19:16.90#ibcon#about to read 3, iclass 26, count 0 2006.285.14:19:16.92#ibcon#read 3, iclass 26, count 0 2006.285.14:19:16.92#ibcon#about to read 4, iclass 26, count 0 2006.285.14:19:16.92#ibcon#read 4, iclass 26, count 0 2006.285.14:19:16.92#ibcon#about to read 5, iclass 26, count 0 2006.285.14:19:16.92#ibcon#read 5, iclass 26, count 0 2006.285.14:19:16.92#ibcon#about to read 6, iclass 26, count 0 2006.285.14:19:16.92#ibcon#read 6, iclass 26, count 0 2006.285.14:19:16.92#ibcon#end of sib2, iclass 26, count 0 2006.285.14:19:16.92#ibcon#*mode == 0, iclass 26, count 0 2006.285.14:19:16.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.14:19:16.92#ibcon#[25=USB\r\n] 2006.285.14:19:16.92#ibcon#*before write, iclass 26, count 0 2006.285.14:19:16.92#ibcon#enter sib2, iclass 26, count 0 2006.285.14:19:16.92#ibcon#flushed, iclass 26, count 0 2006.285.14:19:16.92#ibcon#about to write, iclass 26, count 0 2006.285.14:19:16.92#ibcon#wrote, iclass 26, count 0 2006.285.14:19:16.92#ibcon#about to read 3, iclass 26, count 0 2006.285.14:19:16.95#ibcon#read 3, iclass 26, count 0 2006.285.14:19:16.95#ibcon#about to read 4, iclass 26, count 0 2006.285.14:19:16.95#ibcon#read 4, iclass 26, count 0 2006.285.14:19:16.95#ibcon#about to read 5, iclass 26, count 0 2006.285.14:19:16.95#ibcon#read 5, iclass 26, count 0 2006.285.14:19:16.95#ibcon#about to read 6, iclass 26, count 0 2006.285.14:19:16.95#ibcon#read 6, iclass 26, count 0 2006.285.14:19:16.95#ibcon#end of sib2, iclass 26, count 0 2006.285.14:19:16.95#ibcon#*after write, iclass 26, count 0 2006.285.14:19:16.95#ibcon#*before return 0, iclass 26, count 0 2006.285.14:19:16.95#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:19:16.95#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:19:16.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.14:19:16.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.14:19:16.95$vck44/valo=7,864.99 2006.285.14:19:16.95#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.14:19:16.95#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.14:19:16.95#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:16.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:19:16.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:19:16.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:19:16.95#ibcon#enter wrdev, iclass 28, count 0 2006.285.14:19:16.95#ibcon#first serial, iclass 28, count 0 2006.285.14:19:16.95#ibcon#enter sib2, iclass 28, count 0 2006.285.14:19:16.95#ibcon#flushed, iclass 28, count 0 2006.285.14:19:16.95#ibcon#about to write, iclass 28, count 0 2006.285.14:19:16.95#ibcon#wrote, iclass 28, count 0 2006.285.14:19:16.95#ibcon#about to read 3, iclass 28, count 0 2006.285.14:19:16.97#ibcon#read 3, iclass 28, count 0 2006.285.14:19:16.97#ibcon#about to read 4, iclass 28, count 0 2006.285.14:19:16.97#ibcon#read 4, iclass 28, count 0 2006.285.14:19:16.97#ibcon#about to read 5, iclass 28, count 0 2006.285.14:19:16.97#ibcon#read 5, iclass 28, count 0 2006.285.14:19:16.97#ibcon#about to read 6, iclass 28, count 0 2006.285.14:19:16.97#ibcon#read 6, iclass 28, count 0 2006.285.14:19:16.97#ibcon#end of sib2, iclass 28, count 0 2006.285.14:19:16.97#ibcon#*mode == 0, iclass 28, count 0 2006.285.14:19:16.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.14:19:16.97#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.14:19:16.97#ibcon#*before write, iclass 28, count 0 2006.285.14:19:16.97#ibcon#enter sib2, iclass 28, count 0 2006.285.14:19:16.97#ibcon#flushed, iclass 28, count 0 2006.285.14:19:16.97#ibcon#about to write, iclass 28, count 0 2006.285.14:19:16.97#ibcon#wrote, iclass 28, count 0 2006.285.14:19:16.97#ibcon#about to read 3, iclass 28, count 0 2006.285.14:19:17.01#ibcon#read 3, iclass 28, count 0 2006.285.14:19:17.01#ibcon#about to read 4, iclass 28, count 0 2006.285.14:19:17.01#ibcon#read 4, iclass 28, count 0 2006.285.14:19:17.01#ibcon#about to read 5, iclass 28, count 0 2006.285.14:19:17.01#ibcon#read 5, iclass 28, count 0 2006.285.14:19:17.01#ibcon#about to read 6, iclass 28, count 0 2006.285.14:19:17.01#ibcon#read 6, iclass 28, count 0 2006.285.14:19:17.01#ibcon#end of sib2, iclass 28, count 0 2006.285.14:19:17.01#ibcon#*after write, iclass 28, count 0 2006.285.14:19:17.01#ibcon#*before return 0, iclass 28, count 0 2006.285.14:19:17.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:19:17.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:19:17.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.14:19:17.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.14:19:17.01$vck44/va=7,4 2006.285.14:19:17.01#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.14:19:17.01#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.14:19:17.01#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:17.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:19:17.04#abcon#<5=/04 2.0 3.5 19.20 961015.1\r\n> 2006.285.14:19:17.06#abcon#{5=INTERFACE CLEAR} 2006.285.14:19:17.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:19:17.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:19:17.07#ibcon#enter wrdev, iclass 31, count 2 2006.285.14:19:17.07#ibcon#first serial, iclass 31, count 2 2006.285.14:19:17.07#ibcon#enter sib2, iclass 31, count 2 2006.285.14:19:17.07#ibcon#flushed, iclass 31, count 2 2006.285.14:19:17.07#ibcon#about to write, iclass 31, count 2 2006.285.14:19:17.07#ibcon#wrote, iclass 31, count 2 2006.285.14:19:17.07#ibcon#about to read 3, iclass 31, count 2 2006.285.14:19:17.09#ibcon#read 3, iclass 31, count 2 2006.285.14:19:17.09#ibcon#about to read 4, iclass 31, count 2 2006.285.14:19:17.09#ibcon#read 4, iclass 31, count 2 2006.285.14:19:17.09#ibcon#about to read 5, iclass 31, count 2 2006.285.14:19:17.09#ibcon#read 5, iclass 31, count 2 2006.285.14:19:17.09#ibcon#about to read 6, iclass 31, count 2 2006.285.14:19:17.09#ibcon#read 6, iclass 31, count 2 2006.285.14:19:17.09#ibcon#end of sib2, iclass 31, count 2 2006.285.14:19:17.09#ibcon#*mode == 0, iclass 31, count 2 2006.285.14:19:17.09#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.14:19:17.09#ibcon#[25=AT07-04\r\n] 2006.285.14:19:17.09#ibcon#*before write, iclass 31, count 2 2006.285.14:19:17.09#ibcon#enter sib2, iclass 31, count 2 2006.285.14:19:17.09#ibcon#flushed, iclass 31, count 2 2006.285.14:19:17.09#ibcon#about to write, iclass 31, count 2 2006.285.14:19:17.09#ibcon#wrote, iclass 31, count 2 2006.285.14:19:17.09#ibcon#about to read 3, iclass 31, count 2 2006.285.14:19:17.12#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:19:17.12#ibcon#read 3, iclass 31, count 2 2006.285.14:19:17.12#ibcon#about to read 4, iclass 31, count 2 2006.285.14:19:17.12#ibcon#read 4, iclass 31, count 2 2006.285.14:19:17.12#ibcon#about to read 5, iclass 31, count 2 2006.285.14:19:17.12#ibcon#read 5, iclass 31, count 2 2006.285.14:19:17.12#ibcon#about to read 6, iclass 31, count 2 2006.285.14:19:17.12#ibcon#read 6, iclass 31, count 2 2006.285.14:19:17.12#ibcon#end of sib2, iclass 31, count 2 2006.285.14:19:17.12#ibcon#*after write, iclass 31, count 2 2006.285.14:19:17.12#ibcon#*before return 0, iclass 31, count 2 2006.285.14:19:17.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:19:17.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:19:17.12#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.14:19:17.12#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:17.12#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:19:17.24#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:19:17.24#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:19:17.24#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:19:17.24#ibcon#first serial, iclass 31, count 0 2006.285.14:19:17.24#ibcon#enter sib2, iclass 31, count 0 2006.285.14:19:17.24#ibcon#flushed, iclass 31, count 0 2006.285.14:19:17.24#ibcon#about to write, iclass 31, count 0 2006.285.14:19:17.24#ibcon#wrote, iclass 31, count 0 2006.285.14:19:17.24#ibcon#about to read 3, iclass 31, count 0 2006.285.14:19:17.26#ibcon#read 3, iclass 31, count 0 2006.285.14:19:17.26#ibcon#about to read 4, iclass 31, count 0 2006.285.14:19:17.26#ibcon#read 4, iclass 31, count 0 2006.285.14:19:17.26#ibcon#about to read 5, iclass 31, count 0 2006.285.14:19:17.26#ibcon#read 5, iclass 31, count 0 2006.285.14:19:17.26#ibcon#about to read 6, iclass 31, count 0 2006.285.14:19:17.26#ibcon#read 6, iclass 31, count 0 2006.285.14:19:17.26#ibcon#end of sib2, iclass 31, count 0 2006.285.14:19:17.26#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:19:17.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:19:17.26#ibcon#[25=USB\r\n] 2006.285.14:19:17.26#ibcon#*before write, iclass 31, count 0 2006.285.14:19:17.26#ibcon#enter sib2, iclass 31, count 0 2006.285.14:19:17.26#ibcon#flushed, iclass 31, count 0 2006.285.14:19:17.26#ibcon#about to write, iclass 31, count 0 2006.285.14:19:17.26#ibcon#wrote, iclass 31, count 0 2006.285.14:19:17.26#ibcon#about to read 3, iclass 31, count 0 2006.285.14:19:17.29#ibcon#read 3, iclass 31, count 0 2006.285.14:19:17.29#ibcon#about to read 4, iclass 31, count 0 2006.285.14:19:17.29#ibcon#read 4, iclass 31, count 0 2006.285.14:19:17.29#ibcon#about to read 5, iclass 31, count 0 2006.285.14:19:17.29#ibcon#read 5, iclass 31, count 0 2006.285.14:19:17.29#ibcon#about to read 6, iclass 31, count 0 2006.285.14:19:17.29#ibcon#read 6, iclass 31, count 0 2006.285.14:19:17.29#ibcon#end of sib2, iclass 31, count 0 2006.285.14:19:17.29#ibcon#*after write, iclass 31, count 0 2006.285.14:19:17.29#ibcon#*before return 0, iclass 31, count 0 2006.285.14:19:17.29#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:19:17.29#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:19:17.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:19:17.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:19:17.29$vck44/valo=8,884.99 2006.285.14:19:17.29#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.14:19:17.29#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.14:19:17.29#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:17.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:19:17.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:19:17.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:19:17.29#ibcon#enter wrdev, iclass 36, count 0 2006.285.14:19:17.29#ibcon#first serial, iclass 36, count 0 2006.285.14:19:17.29#ibcon#enter sib2, iclass 36, count 0 2006.285.14:19:17.29#ibcon#flushed, iclass 36, count 0 2006.285.14:19:17.29#ibcon#about to write, iclass 36, count 0 2006.285.14:19:17.29#ibcon#wrote, iclass 36, count 0 2006.285.14:19:17.29#ibcon#about to read 3, iclass 36, count 0 2006.285.14:19:17.31#ibcon#read 3, iclass 36, count 0 2006.285.14:19:17.31#ibcon#about to read 4, iclass 36, count 0 2006.285.14:19:17.31#ibcon#read 4, iclass 36, count 0 2006.285.14:19:17.31#ibcon#about to read 5, iclass 36, count 0 2006.285.14:19:17.31#ibcon#read 5, iclass 36, count 0 2006.285.14:19:17.31#ibcon#about to read 6, iclass 36, count 0 2006.285.14:19:17.31#ibcon#read 6, iclass 36, count 0 2006.285.14:19:17.31#ibcon#end of sib2, iclass 36, count 0 2006.285.14:19:17.31#ibcon#*mode == 0, iclass 36, count 0 2006.285.14:19:17.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.14:19:17.31#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.14:19:17.31#ibcon#*before write, iclass 36, count 0 2006.285.14:19:17.31#ibcon#enter sib2, iclass 36, count 0 2006.285.14:19:17.31#ibcon#flushed, iclass 36, count 0 2006.285.14:19:17.31#ibcon#about to write, iclass 36, count 0 2006.285.14:19:17.31#ibcon#wrote, iclass 36, count 0 2006.285.14:19:17.31#ibcon#about to read 3, iclass 36, count 0 2006.285.14:19:17.35#ibcon#read 3, iclass 36, count 0 2006.285.14:19:17.35#ibcon#about to read 4, iclass 36, count 0 2006.285.14:19:17.35#ibcon#read 4, iclass 36, count 0 2006.285.14:19:17.35#ibcon#about to read 5, iclass 36, count 0 2006.285.14:19:17.35#ibcon#read 5, iclass 36, count 0 2006.285.14:19:17.35#ibcon#about to read 6, iclass 36, count 0 2006.285.14:19:17.35#ibcon#read 6, iclass 36, count 0 2006.285.14:19:17.35#ibcon#end of sib2, iclass 36, count 0 2006.285.14:19:17.35#ibcon#*after write, iclass 36, count 0 2006.285.14:19:17.35#ibcon#*before return 0, iclass 36, count 0 2006.285.14:19:17.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:19:17.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:19:17.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.14:19:17.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.14:19:17.35$vck44/va=8,3 2006.285.14:19:17.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.14:19:17.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.14:19:17.68#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:17.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:19:17.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:19:17.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:19:17.68#ibcon#enter wrdev, iclass 38, count 2 2006.285.14:19:17.68#ibcon#first serial, iclass 38, count 2 2006.285.14:19:17.68#ibcon#enter sib2, iclass 38, count 2 2006.285.14:19:17.68#ibcon#flushed, iclass 38, count 2 2006.285.14:19:17.68#ibcon#about to write, iclass 38, count 2 2006.285.14:19:17.68#ibcon#wrote, iclass 38, count 2 2006.285.14:19:17.68#ibcon#about to read 3, iclass 38, count 2 2006.285.14:19:17.70#ibcon#read 3, iclass 38, count 2 2006.285.14:19:17.70#ibcon#about to read 4, iclass 38, count 2 2006.285.14:19:17.70#ibcon#read 4, iclass 38, count 2 2006.285.14:19:17.70#ibcon#about to read 5, iclass 38, count 2 2006.285.14:19:17.70#ibcon#read 5, iclass 38, count 2 2006.285.14:19:17.70#ibcon#about to read 6, iclass 38, count 2 2006.285.14:19:17.70#ibcon#read 6, iclass 38, count 2 2006.285.14:19:17.70#ibcon#end of sib2, iclass 38, count 2 2006.285.14:19:17.70#ibcon#*mode == 0, iclass 38, count 2 2006.285.14:19:17.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.14:19:17.70#ibcon#[25=AT08-03\r\n] 2006.285.14:19:17.70#ibcon#*before write, iclass 38, count 2 2006.285.14:19:17.70#ibcon#enter sib2, iclass 38, count 2 2006.285.14:19:17.70#ibcon#flushed, iclass 38, count 2 2006.285.14:19:17.70#ibcon#about to write, iclass 38, count 2 2006.285.14:19:17.70#ibcon#wrote, iclass 38, count 2 2006.285.14:19:17.70#ibcon#about to read 3, iclass 38, count 2 2006.285.14:19:17.73#ibcon#read 3, iclass 38, count 2 2006.285.14:19:17.73#ibcon#about to read 4, iclass 38, count 2 2006.285.14:19:17.73#ibcon#read 4, iclass 38, count 2 2006.285.14:19:17.73#ibcon#about to read 5, iclass 38, count 2 2006.285.14:19:17.73#ibcon#read 5, iclass 38, count 2 2006.285.14:19:17.73#ibcon#about to read 6, iclass 38, count 2 2006.285.14:19:17.73#ibcon#read 6, iclass 38, count 2 2006.285.14:19:17.73#ibcon#end of sib2, iclass 38, count 2 2006.285.14:19:17.73#ibcon#*after write, iclass 38, count 2 2006.285.14:19:17.73#ibcon#*before return 0, iclass 38, count 2 2006.285.14:19:17.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:19:17.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:19:17.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.14:19:17.73#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:17.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:19:17.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:19:17.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:19:17.85#ibcon#enter wrdev, iclass 38, count 0 2006.285.14:19:17.85#ibcon#first serial, iclass 38, count 0 2006.285.14:19:17.85#ibcon#enter sib2, iclass 38, count 0 2006.285.14:19:17.85#ibcon#flushed, iclass 38, count 0 2006.285.14:19:17.85#ibcon#about to write, iclass 38, count 0 2006.285.14:19:17.85#ibcon#wrote, iclass 38, count 0 2006.285.14:19:17.85#ibcon#about to read 3, iclass 38, count 0 2006.285.14:19:17.87#ibcon#read 3, iclass 38, count 0 2006.285.14:19:17.87#ibcon#about to read 4, iclass 38, count 0 2006.285.14:19:17.87#ibcon#read 4, iclass 38, count 0 2006.285.14:19:17.87#ibcon#about to read 5, iclass 38, count 0 2006.285.14:19:17.87#ibcon#read 5, iclass 38, count 0 2006.285.14:19:17.87#ibcon#about to read 6, iclass 38, count 0 2006.285.14:19:17.87#ibcon#read 6, iclass 38, count 0 2006.285.14:19:17.87#ibcon#end of sib2, iclass 38, count 0 2006.285.14:19:17.87#ibcon#*mode == 0, iclass 38, count 0 2006.285.14:19:17.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.14:19:17.87#ibcon#[25=USB\r\n] 2006.285.14:19:17.87#ibcon#*before write, iclass 38, count 0 2006.285.14:19:17.87#ibcon#enter sib2, iclass 38, count 0 2006.285.14:19:17.87#ibcon#flushed, iclass 38, count 0 2006.285.14:19:17.87#ibcon#about to write, iclass 38, count 0 2006.285.14:19:17.87#ibcon#wrote, iclass 38, count 0 2006.285.14:19:17.87#ibcon#about to read 3, iclass 38, count 0 2006.285.14:19:17.90#ibcon#read 3, iclass 38, count 0 2006.285.14:19:17.90#ibcon#about to read 4, iclass 38, count 0 2006.285.14:19:17.90#ibcon#read 4, iclass 38, count 0 2006.285.14:19:17.90#ibcon#about to read 5, iclass 38, count 0 2006.285.14:19:17.90#ibcon#read 5, iclass 38, count 0 2006.285.14:19:17.90#ibcon#about to read 6, iclass 38, count 0 2006.285.14:19:17.90#ibcon#read 6, iclass 38, count 0 2006.285.14:19:17.90#ibcon#end of sib2, iclass 38, count 0 2006.285.14:19:17.90#ibcon#*after write, iclass 38, count 0 2006.285.14:19:17.90#ibcon#*before return 0, iclass 38, count 0 2006.285.14:19:17.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:19:17.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:19:17.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.14:19:17.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.14:19:17.90$vck44/vblo=1,629.99 2006.285.14:19:17.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.14:19:17.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.14:19:17.90#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:17.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:19:17.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:19:17.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:19:17.90#ibcon#enter wrdev, iclass 40, count 0 2006.285.14:19:17.90#ibcon#first serial, iclass 40, count 0 2006.285.14:19:17.90#ibcon#enter sib2, iclass 40, count 0 2006.285.14:19:17.90#ibcon#flushed, iclass 40, count 0 2006.285.14:19:17.90#ibcon#about to write, iclass 40, count 0 2006.285.14:19:17.90#ibcon#wrote, iclass 40, count 0 2006.285.14:19:17.90#ibcon#about to read 3, iclass 40, count 0 2006.285.14:19:17.92#ibcon#read 3, iclass 40, count 0 2006.285.14:19:17.92#ibcon#about to read 4, iclass 40, count 0 2006.285.14:19:17.92#ibcon#read 4, iclass 40, count 0 2006.285.14:19:17.92#ibcon#about to read 5, iclass 40, count 0 2006.285.14:19:17.92#ibcon#read 5, iclass 40, count 0 2006.285.14:19:17.92#ibcon#about to read 6, iclass 40, count 0 2006.285.14:19:17.92#ibcon#read 6, iclass 40, count 0 2006.285.14:19:17.92#ibcon#end of sib2, iclass 40, count 0 2006.285.14:19:17.92#ibcon#*mode == 0, iclass 40, count 0 2006.285.14:19:17.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.14:19:17.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.14:19:17.92#ibcon#*before write, iclass 40, count 0 2006.285.14:19:17.92#ibcon#enter sib2, iclass 40, count 0 2006.285.14:19:17.92#ibcon#flushed, iclass 40, count 0 2006.285.14:19:17.92#ibcon#about to write, iclass 40, count 0 2006.285.14:19:17.92#ibcon#wrote, iclass 40, count 0 2006.285.14:19:17.92#ibcon#about to read 3, iclass 40, count 0 2006.285.14:19:17.96#ibcon#read 3, iclass 40, count 0 2006.285.14:19:17.96#ibcon#about to read 4, iclass 40, count 0 2006.285.14:19:17.96#ibcon#read 4, iclass 40, count 0 2006.285.14:19:17.96#ibcon#about to read 5, iclass 40, count 0 2006.285.14:19:17.96#ibcon#read 5, iclass 40, count 0 2006.285.14:19:17.96#ibcon#about to read 6, iclass 40, count 0 2006.285.14:19:17.96#ibcon#read 6, iclass 40, count 0 2006.285.14:19:17.96#ibcon#end of sib2, iclass 40, count 0 2006.285.14:19:17.96#ibcon#*after write, iclass 40, count 0 2006.285.14:19:17.96#ibcon#*before return 0, iclass 40, count 0 2006.285.14:19:17.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:19:17.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:19:17.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.14:19:17.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.14:19:17.96$vck44/vb=1,4 2006.285.14:19:17.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.14:19:17.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.14:19:17.96#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:17.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:19:17.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:19:17.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:19:17.96#ibcon#enter wrdev, iclass 4, count 2 2006.285.14:19:17.96#ibcon#first serial, iclass 4, count 2 2006.285.14:19:17.96#ibcon#enter sib2, iclass 4, count 2 2006.285.14:19:17.96#ibcon#flushed, iclass 4, count 2 2006.285.14:19:17.96#ibcon#about to write, iclass 4, count 2 2006.285.14:19:17.96#ibcon#wrote, iclass 4, count 2 2006.285.14:19:17.96#ibcon#about to read 3, iclass 4, count 2 2006.285.14:19:17.98#ibcon#read 3, iclass 4, count 2 2006.285.14:19:17.98#ibcon#about to read 4, iclass 4, count 2 2006.285.14:19:17.98#ibcon#read 4, iclass 4, count 2 2006.285.14:19:17.98#ibcon#about to read 5, iclass 4, count 2 2006.285.14:19:17.98#ibcon#read 5, iclass 4, count 2 2006.285.14:19:17.98#ibcon#about to read 6, iclass 4, count 2 2006.285.14:19:17.98#ibcon#read 6, iclass 4, count 2 2006.285.14:19:17.98#ibcon#end of sib2, iclass 4, count 2 2006.285.14:19:17.98#ibcon#*mode == 0, iclass 4, count 2 2006.285.14:19:17.98#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.14:19:17.98#ibcon#[27=AT01-04\r\n] 2006.285.14:19:17.98#ibcon#*before write, iclass 4, count 2 2006.285.14:19:17.98#ibcon#enter sib2, iclass 4, count 2 2006.285.14:19:17.98#ibcon#flushed, iclass 4, count 2 2006.285.14:19:17.98#ibcon#about to write, iclass 4, count 2 2006.285.14:19:17.98#ibcon#wrote, iclass 4, count 2 2006.285.14:19:17.98#ibcon#about to read 3, iclass 4, count 2 2006.285.14:19:18.01#ibcon#read 3, iclass 4, count 2 2006.285.14:19:18.01#ibcon#about to read 4, iclass 4, count 2 2006.285.14:19:18.01#ibcon#read 4, iclass 4, count 2 2006.285.14:19:18.01#ibcon#about to read 5, iclass 4, count 2 2006.285.14:19:18.01#ibcon#read 5, iclass 4, count 2 2006.285.14:19:18.01#ibcon#about to read 6, iclass 4, count 2 2006.285.14:19:18.01#ibcon#read 6, iclass 4, count 2 2006.285.14:19:18.01#ibcon#end of sib2, iclass 4, count 2 2006.285.14:19:18.01#ibcon#*after write, iclass 4, count 2 2006.285.14:19:18.01#ibcon#*before return 0, iclass 4, count 2 2006.285.14:19:18.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:19:18.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:19:18.01#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.14:19:18.01#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:18.01#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:19:18.13#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:19:18.13#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:19:18.13#ibcon#enter wrdev, iclass 4, count 0 2006.285.14:19:18.13#ibcon#first serial, iclass 4, count 0 2006.285.14:19:18.13#ibcon#enter sib2, iclass 4, count 0 2006.285.14:19:18.13#ibcon#flushed, iclass 4, count 0 2006.285.14:19:18.13#ibcon#about to write, iclass 4, count 0 2006.285.14:19:18.13#ibcon#wrote, iclass 4, count 0 2006.285.14:19:18.13#ibcon#about to read 3, iclass 4, count 0 2006.285.14:19:18.15#ibcon#read 3, iclass 4, count 0 2006.285.14:19:18.15#ibcon#about to read 4, iclass 4, count 0 2006.285.14:19:18.15#ibcon#read 4, iclass 4, count 0 2006.285.14:19:18.15#ibcon#about to read 5, iclass 4, count 0 2006.285.14:19:18.15#ibcon#read 5, iclass 4, count 0 2006.285.14:19:18.15#ibcon#about to read 6, iclass 4, count 0 2006.285.14:19:18.15#ibcon#read 6, iclass 4, count 0 2006.285.14:19:18.15#ibcon#end of sib2, iclass 4, count 0 2006.285.14:19:18.15#ibcon#*mode == 0, iclass 4, count 0 2006.285.14:19:18.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.14:19:18.15#ibcon#[27=USB\r\n] 2006.285.14:19:18.15#ibcon#*before write, iclass 4, count 0 2006.285.14:19:18.15#ibcon#enter sib2, iclass 4, count 0 2006.285.14:19:18.15#ibcon#flushed, iclass 4, count 0 2006.285.14:19:18.15#ibcon#about to write, iclass 4, count 0 2006.285.14:19:18.15#ibcon#wrote, iclass 4, count 0 2006.285.14:19:18.15#ibcon#about to read 3, iclass 4, count 0 2006.285.14:19:18.18#ibcon#read 3, iclass 4, count 0 2006.285.14:19:18.18#ibcon#about to read 4, iclass 4, count 0 2006.285.14:19:18.18#ibcon#read 4, iclass 4, count 0 2006.285.14:19:18.18#ibcon#about to read 5, iclass 4, count 0 2006.285.14:19:18.18#ibcon#read 5, iclass 4, count 0 2006.285.14:19:18.18#ibcon#about to read 6, iclass 4, count 0 2006.285.14:19:18.18#ibcon#read 6, iclass 4, count 0 2006.285.14:19:18.18#ibcon#end of sib2, iclass 4, count 0 2006.285.14:19:18.18#ibcon#*after write, iclass 4, count 0 2006.285.14:19:18.18#ibcon#*before return 0, iclass 4, count 0 2006.285.14:19:18.18#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:19:18.18#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:19:18.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.14:19:18.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.14:19:18.18$vck44/vblo=2,634.99 2006.285.14:19:18.18#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.14:19:18.18#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.14:19:18.18#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:18.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:19:18.18#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:19:18.18#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:19:18.18#ibcon#enter wrdev, iclass 6, count 0 2006.285.14:19:18.18#ibcon#first serial, iclass 6, count 0 2006.285.14:19:18.18#ibcon#enter sib2, iclass 6, count 0 2006.285.14:19:18.18#ibcon#flushed, iclass 6, count 0 2006.285.14:19:18.18#ibcon#about to write, iclass 6, count 0 2006.285.14:19:18.18#ibcon#wrote, iclass 6, count 0 2006.285.14:19:18.18#ibcon#about to read 3, iclass 6, count 0 2006.285.14:19:18.20#ibcon#read 3, iclass 6, count 0 2006.285.14:19:18.20#ibcon#about to read 4, iclass 6, count 0 2006.285.14:19:18.20#ibcon#read 4, iclass 6, count 0 2006.285.14:19:18.20#ibcon#about to read 5, iclass 6, count 0 2006.285.14:19:18.20#ibcon#read 5, iclass 6, count 0 2006.285.14:19:18.20#ibcon#about to read 6, iclass 6, count 0 2006.285.14:19:18.20#ibcon#read 6, iclass 6, count 0 2006.285.14:19:18.20#ibcon#end of sib2, iclass 6, count 0 2006.285.14:19:18.20#ibcon#*mode == 0, iclass 6, count 0 2006.285.14:19:18.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.14:19:18.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.14:19:18.20#ibcon#*before write, iclass 6, count 0 2006.285.14:19:18.20#ibcon#enter sib2, iclass 6, count 0 2006.285.14:19:18.20#ibcon#flushed, iclass 6, count 0 2006.285.14:19:18.20#ibcon#about to write, iclass 6, count 0 2006.285.14:19:18.20#ibcon#wrote, iclass 6, count 0 2006.285.14:19:18.20#ibcon#about to read 3, iclass 6, count 0 2006.285.14:19:18.24#ibcon#read 3, iclass 6, count 0 2006.285.14:19:18.24#ibcon#about to read 4, iclass 6, count 0 2006.285.14:19:18.24#ibcon#read 4, iclass 6, count 0 2006.285.14:19:18.24#ibcon#about to read 5, iclass 6, count 0 2006.285.14:19:18.24#ibcon#read 5, iclass 6, count 0 2006.285.14:19:18.24#ibcon#about to read 6, iclass 6, count 0 2006.285.14:19:18.24#ibcon#read 6, iclass 6, count 0 2006.285.14:19:18.24#ibcon#end of sib2, iclass 6, count 0 2006.285.14:19:18.24#ibcon#*after write, iclass 6, count 0 2006.285.14:19:18.24#ibcon#*before return 0, iclass 6, count 0 2006.285.14:19:18.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:19:18.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:19:18.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.14:19:18.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.14:19:18.24$vck44/vb=2,5 2006.285.14:19:18.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.14:19:18.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.14:19:18.24#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:18.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:19:18.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:19:18.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:19:18.30#ibcon#enter wrdev, iclass 10, count 2 2006.285.14:19:18.30#ibcon#first serial, iclass 10, count 2 2006.285.14:19:18.30#ibcon#enter sib2, iclass 10, count 2 2006.285.14:19:18.30#ibcon#flushed, iclass 10, count 2 2006.285.14:19:18.30#ibcon#about to write, iclass 10, count 2 2006.285.14:19:18.30#ibcon#wrote, iclass 10, count 2 2006.285.14:19:18.30#ibcon#about to read 3, iclass 10, count 2 2006.285.14:19:18.32#ibcon#read 3, iclass 10, count 2 2006.285.14:19:18.32#ibcon#about to read 4, iclass 10, count 2 2006.285.14:19:18.32#ibcon#read 4, iclass 10, count 2 2006.285.14:19:18.32#ibcon#about to read 5, iclass 10, count 2 2006.285.14:19:18.32#ibcon#read 5, iclass 10, count 2 2006.285.14:19:18.32#ibcon#about to read 6, iclass 10, count 2 2006.285.14:19:18.32#ibcon#read 6, iclass 10, count 2 2006.285.14:19:18.32#ibcon#end of sib2, iclass 10, count 2 2006.285.14:19:18.32#ibcon#*mode == 0, iclass 10, count 2 2006.285.14:19:18.32#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.14:19:18.32#ibcon#[27=AT02-05\r\n] 2006.285.14:19:18.32#ibcon#*before write, iclass 10, count 2 2006.285.14:19:18.32#ibcon#enter sib2, iclass 10, count 2 2006.285.14:19:18.32#ibcon#flushed, iclass 10, count 2 2006.285.14:19:18.32#ibcon#about to write, iclass 10, count 2 2006.285.14:19:18.32#ibcon#wrote, iclass 10, count 2 2006.285.14:19:18.32#ibcon#about to read 3, iclass 10, count 2 2006.285.14:19:18.35#ibcon#read 3, iclass 10, count 2 2006.285.14:19:18.35#ibcon#about to read 4, iclass 10, count 2 2006.285.14:19:18.35#ibcon#read 4, iclass 10, count 2 2006.285.14:19:18.35#ibcon#about to read 5, iclass 10, count 2 2006.285.14:19:18.35#ibcon#read 5, iclass 10, count 2 2006.285.14:19:18.35#ibcon#about to read 6, iclass 10, count 2 2006.285.14:19:18.35#ibcon#read 6, iclass 10, count 2 2006.285.14:19:18.35#ibcon#end of sib2, iclass 10, count 2 2006.285.14:19:18.35#ibcon#*after write, iclass 10, count 2 2006.285.14:19:18.35#ibcon#*before return 0, iclass 10, count 2 2006.285.14:19:18.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:19:18.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:19:18.35#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.14:19:18.35#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:18.35#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:19:18.47#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:19:18.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:19:18.53#ibcon#enter wrdev, iclass 10, count 0 2006.285.14:19:18.53#ibcon#first serial, iclass 10, count 0 2006.285.14:19:18.53#ibcon#enter sib2, iclass 10, count 0 2006.285.14:19:18.53#ibcon#flushed, iclass 10, count 0 2006.285.14:19:18.53#ibcon#about to write, iclass 10, count 0 2006.285.14:19:18.53#ibcon#wrote, iclass 10, count 0 2006.285.14:19:18.53#ibcon#about to read 3, iclass 10, count 0 2006.285.14:19:18.54#ibcon#read 3, iclass 10, count 0 2006.285.14:19:18.54#ibcon#about to read 4, iclass 10, count 0 2006.285.14:19:18.54#ibcon#read 4, iclass 10, count 0 2006.285.14:19:18.54#ibcon#about to read 5, iclass 10, count 0 2006.285.14:19:18.54#ibcon#read 5, iclass 10, count 0 2006.285.14:19:18.54#ibcon#about to read 6, iclass 10, count 0 2006.285.14:19:18.54#ibcon#read 6, iclass 10, count 0 2006.285.14:19:18.54#ibcon#end of sib2, iclass 10, count 0 2006.285.14:19:18.54#ibcon#*mode == 0, iclass 10, count 0 2006.285.14:19:18.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.14:19:18.54#ibcon#[27=USB\r\n] 2006.285.14:19:18.54#ibcon#*before write, iclass 10, count 0 2006.285.14:19:18.54#ibcon#enter sib2, iclass 10, count 0 2006.285.14:19:18.54#ibcon#flushed, iclass 10, count 0 2006.285.14:19:18.54#ibcon#about to write, iclass 10, count 0 2006.285.14:19:18.54#ibcon#wrote, iclass 10, count 0 2006.285.14:19:18.54#ibcon#about to read 3, iclass 10, count 0 2006.285.14:19:18.57#ibcon#read 3, iclass 10, count 0 2006.285.14:19:18.57#ibcon#about to read 4, iclass 10, count 0 2006.285.14:19:18.57#ibcon#read 4, iclass 10, count 0 2006.285.14:19:18.57#ibcon#about to read 5, iclass 10, count 0 2006.285.14:19:18.57#ibcon#read 5, iclass 10, count 0 2006.285.14:19:18.57#ibcon#about to read 6, iclass 10, count 0 2006.285.14:19:18.57#ibcon#read 6, iclass 10, count 0 2006.285.14:19:18.57#ibcon#end of sib2, iclass 10, count 0 2006.285.14:19:18.57#ibcon#*after write, iclass 10, count 0 2006.285.14:19:18.57#ibcon#*before return 0, iclass 10, count 0 2006.285.14:19:18.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:19:18.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:19:18.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.14:19:18.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.14:19:18.57$vck44/vblo=3,649.99 2006.285.14:19:18.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.14:19:18.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.14:19:18.57#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:18.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:19:18.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:19:18.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:19:18.57#ibcon#enter wrdev, iclass 12, count 0 2006.285.14:19:18.57#ibcon#first serial, iclass 12, count 0 2006.285.14:19:18.57#ibcon#enter sib2, iclass 12, count 0 2006.285.14:19:18.57#ibcon#flushed, iclass 12, count 0 2006.285.14:19:18.57#ibcon#about to write, iclass 12, count 0 2006.285.14:19:18.57#ibcon#wrote, iclass 12, count 0 2006.285.14:19:18.57#ibcon#about to read 3, iclass 12, count 0 2006.285.14:19:18.59#ibcon#read 3, iclass 12, count 0 2006.285.14:19:18.59#ibcon#about to read 4, iclass 12, count 0 2006.285.14:19:18.59#ibcon#read 4, iclass 12, count 0 2006.285.14:19:18.59#ibcon#about to read 5, iclass 12, count 0 2006.285.14:19:18.59#ibcon#read 5, iclass 12, count 0 2006.285.14:19:18.59#ibcon#about to read 6, iclass 12, count 0 2006.285.14:19:18.59#ibcon#read 6, iclass 12, count 0 2006.285.14:19:18.59#ibcon#end of sib2, iclass 12, count 0 2006.285.14:19:18.59#ibcon#*mode == 0, iclass 12, count 0 2006.285.14:19:18.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.14:19:18.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.14:19:18.59#ibcon#*before write, iclass 12, count 0 2006.285.14:19:18.59#ibcon#enter sib2, iclass 12, count 0 2006.285.14:19:18.59#ibcon#flushed, iclass 12, count 0 2006.285.14:19:18.59#ibcon#about to write, iclass 12, count 0 2006.285.14:19:18.59#ibcon#wrote, iclass 12, count 0 2006.285.14:19:18.59#ibcon#about to read 3, iclass 12, count 0 2006.285.14:19:18.63#ibcon#read 3, iclass 12, count 0 2006.285.14:19:18.63#ibcon#about to read 4, iclass 12, count 0 2006.285.14:19:18.63#ibcon#read 4, iclass 12, count 0 2006.285.14:19:18.63#ibcon#about to read 5, iclass 12, count 0 2006.285.14:19:18.63#ibcon#read 5, iclass 12, count 0 2006.285.14:19:18.63#ibcon#about to read 6, iclass 12, count 0 2006.285.14:19:18.63#ibcon#read 6, iclass 12, count 0 2006.285.14:19:18.63#ibcon#end of sib2, iclass 12, count 0 2006.285.14:19:18.63#ibcon#*after write, iclass 12, count 0 2006.285.14:19:18.63#ibcon#*before return 0, iclass 12, count 0 2006.285.14:19:18.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:19:18.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:19:18.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.14:19:18.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.14:19:18.63$vck44/vb=3,4 2006.285.14:19:18.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.14:19:18.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.14:19:18.63#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:18.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:19:18.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:19:18.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:19:18.69#ibcon#enter wrdev, iclass 14, count 2 2006.285.14:19:18.69#ibcon#first serial, iclass 14, count 2 2006.285.14:19:18.69#ibcon#enter sib2, iclass 14, count 2 2006.285.14:19:18.69#ibcon#flushed, iclass 14, count 2 2006.285.14:19:18.69#ibcon#about to write, iclass 14, count 2 2006.285.14:19:18.69#ibcon#wrote, iclass 14, count 2 2006.285.14:19:18.69#ibcon#about to read 3, iclass 14, count 2 2006.285.14:19:18.71#ibcon#read 3, iclass 14, count 2 2006.285.14:19:18.71#ibcon#about to read 4, iclass 14, count 2 2006.285.14:19:18.71#ibcon#read 4, iclass 14, count 2 2006.285.14:19:18.71#ibcon#about to read 5, iclass 14, count 2 2006.285.14:19:18.71#ibcon#read 5, iclass 14, count 2 2006.285.14:19:18.71#ibcon#about to read 6, iclass 14, count 2 2006.285.14:19:18.71#ibcon#read 6, iclass 14, count 2 2006.285.14:19:18.71#ibcon#end of sib2, iclass 14, count 2 2006.285.14:19:18.71#ibcon#*mode == 0, iclass 14, count 2 2006.285.14:19:18.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.14:19:18.71#ibcon#[27=AT03-04\r\n] 2006.285.14:19:18.71#ibcon#*before write, iclass 14, count 2 2006.285.14:19:18.71#ibcon#enter sib2, iclass 14, count 2 2006.285.14:19:18.71#ibcon#flushed, iclass 14, count 2 2006.285.14:19:18.71#ibcon#about to write, iclass 14, count 2 2006.285.14:19:18.71#ibcon#wrote, iclass 14, count 2 2006.285.14:19:18.71#ibcon#about to read 3, iclass 14, count 2 2006.285.14:19:18.74#ibcon#read 3, iclass 14, count 2 2006.285.14:19:18.74#ibcon#about to read 4, iclass 14, count 2 2006.285.14:19:18.74#ibcon#read 4, iclass 14, count 2 2006.285.14:19:18.74#ibcon#about to read 5, iclass 14, count 2 2006.285.14:19:18.74#ibcon#read 5, iclass 14, count 2 2006.285.14:19:18.74#ibcon#about to read 6, iclass 14, count 2 2006.285.14:19:18.74#ibcon#read 6, iclass 14, count 2 2006.285.14:19:18.74#ibcon#end of sib2, iclass 14, count 2 2006.285.14:19:18.74#ibcon#*after write, iclass 14, count 2 2006.285.14:19:18.74#ibcon#*before return 0, iclass 14, count 2 2006.285.14:19:18.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:19:18.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:19:18.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.14:19:18.74#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:18.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:19:18.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:19:18.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:19:18.86#ibcon#enter wrdev, iclass 14, count 0 2006.285.14:19:18.86#ibcon#first serial, iclass 14, count 0 2006.285.14:19:18.86#ibcon#enter sib2, iclass 14, count 0 2006.285.14:19:18.86#ibcon#flushed, iclass 14, count 0 2006.285.14:19:18.86#ibcon#about to write, iclass 14, count 0 2006.285.14:19:18.86#ibcon#wrote, iclass 14, count 0 2006.285.14:19:18.86#ibcon#about to read 3, iclass 14, count 0 2006.285.14:19:18.88#ibcon#read 3, iclass 14, count 0 2006.285.14:19:18.88#ibcon#about to read 4, iclass 14, count 0 2006.285.14:19:18.88#ibcon#read 4, iclass 14, count 0 2006.285.14:19:18.88#ibcon#about to read 5, iclass 14, count 0 2006.285.14:19:18.88#ibcon#read 5, iclass 14, count 0 2006.285.14:19:18.88#ibcon#about to read 6, iclass 14, count 0 2006.285.14:19:18.88#ibcon#read 6, iclass 14, count 0 2006.285.14:19:18.88#ibcon#end of sib2, iclass 14, count 0 2006.285.14:19:18.88#ibcon#*mode == 0, iclass 14, count 0 2006.285.14:19:18.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.14:19:18.88#ibcon#[27=USB\r\n] 2006.285.14:19:18.88#ibcon#*before write, iclass 14, count 0 2006.285.14:19:18.88#ibcon#enter sib2, iclass 14, count 0 2006.285.14:19:18.88#ibcon#flushed, iclass 14, count 0 2006.285.14:19:18.88#ibcon#about to write, iclass 14, count 0 2006.285.14:19:18.88#ibcon#wrote, iclass 14, count 0 2006.285.14:19:18.88#ibcon#about to read 3, iclass 14, count 0 2006.285.14:19:18.91#ibcon#read 3, iclass 14, count 0 2006.285.14:19:18.91#ibcon#about to read 4, iclass 14, count 0 2006.285.14:19:18.91#ibcon#read 4, iclass 14, count 0 2006.285.14:19:18.91#ibcon#about to read 5, iclass 14, count 0 2006.285.14:19:18.91#ibcon#read 5, iclass 14, count 0 2006.285.14:19:18.91#ibcon#about to read 6, iclass 14, count 0 2006.285.14:19:18.91#ibcon#read 6, iclass 14, count 0 2006.285.14:19:18.91#ibcon#end of sib2, iclass 14, count 0 2006.285.14:19:18.91#ibcon#*after write, iclass 14, count 0 2006.285.14:19:18.91#ibcon#*before return 0, iclass 14, count 0 2006.285.14:19:18.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:19:18.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:19:18.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.14:19:18.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.14:19:18.91$vck44/vblo=4,679.99 2006.285.14:19:18.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.14:19:18.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.14:19:18.91#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:18.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:19:18.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:19:18.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:19:18.91#ibcon#enter wrdev, iclass 16, count 0 2006.285.14:19:18.91#ibcon#first serial, iclass 16, count 0 2006.285.14:19:18.91#ibcon#enter sib2, iclass 16, count 0 2006.285.14:19:18.91#ibcon#flushed, iclass 16, count 0 2006.285.14:19:18.91#ibcon#about to write, iclass 16, count 0 2006.285.14:19:18.91#ibcon#wrote, iclass 16, count 0 2006.285.14:19:18.91#ibcon#about to read 3, iclass 16, count 0 2006.285.14:19:18.93#ibcon#read 3, iclass 16, count 0 2006.285.14:19:18.93#ibcon#about to read 4, iclass 16, count 0 2006.285.14:19:18.93#ibcon#read 4, iclass 16, count 0 2006.285.14:19:18.93#ibcon#about to read 5, iclass 16, count 0 2006.285.14:19:18.93#ibcon#read 5, iclass 16, count 0 2006.285.14:19:18.93#ibcon#about to read 6, iclass 16, count 0 2006.285.14:19:18.93#ibcon#read 6, iclass 16, count 0 2006.285.14:19:18.93#ibcon#end of sib2, iclass 16, count 0 2006.285.14:19:18.93#ibcon#*mode == 0, iclass 16, count 0 2006.285.14:19:18.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.14:19:18.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.14:19:18.93#ibcon#*before write, iclass 16, count 0 2006.285.14:19:18.93#ibcon#enter sib2, iclass 16, count 0 2006.285.14:19:18.93#ibcon#flushed, iclass 16, count 0 2006.285.14:19:18.93#ibcon#about to write, iclass 16, count 0 2006.285.14:19:18.93#ibcon#wrote, iclass 16, count 0 2006.285.14:19:18.93#ibcon#about to read 3, iclass 16, count 0 2006.285.14:19:18.97#ibcon#read 3, iclass 16, count 0 2006.285.14:19:18.97#ibcon#about to read 4, iclass 16, count 0 2006.285.14:19:18.97#ibcon#read 4, iclass 16, count 0 2006.285.14:19:18.97#ibcon#about to read 5, iclass 16, count 0 2006.285.14:19:18.97#ibcon#read 5, iclass 16, count 0 2006.285.14:19:18.97#ibcon#about to read 6, iclass 16, count 0 2006.285.14:19:18.97#ibcon#read 6, iclass 16, count 0 2006.285.14:19:18.97#ibcon#end of sib2, iclass 16, count 0 2006.285.14:19:18.97#ibcon#*after write, iclass 16, count 0 2006.285.14:19:18.97#ibcon#*before return 0, iclass 16, count 0 2006.285.14:19:18.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:19:18.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:19:18.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.14:19:18.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.14:19:18.97$vck44/vb=4,5 2006.285.14:19:18.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.14:19:18.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.14:19:18.97#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:18.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:19:19.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:19:19.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:19:19.03#ibcon#enter wrdev, iclass 18, count 2 2006.285.14:19:19.03#ibcon#first serial, iclass 18, count 2 2006.285.14:19:19.03#ibcon#enter sib2, iclass 18, count 2 2006.285.14:19:19.03#ibcon#flushed, iclass 18, count 2 2006.285.14:19:19.03#ibcon#about to write, iclass 18, count 2 2006.285.14:19:19.03#ibcon#wrote, iclass 18, count 2 2006.285.14:19:19.03#ibcon#about to read 3, iclass 18, count 2 2006.285.14:19:19.05#ibcon#read 3, iclass 18, count 2 2006.285.14:19:19.05#ibcon#about to read 4, iclass 18, count 2 2006.285.14:19:19.05#ibcon#read 4, iclass 18, count 2 2006.285.14:19:19.05#ibcon#about to read 5, iclass 18, count 2 2006.285.14:19:19.05#ibcon#read 5, iclass 18, count 2 2006.285.14:19:19.05#ibcon#about to read 6, iclass 18, count 2 2006.285.14:19:19.05#ibcon#read 6, iclass 18, count 2 2006.285.14:19:19.05#ibcon#end of sib2, iclass 18, count 2 2006.285.14:19:19.05#ibcon#*mode == 0, iclass 18, count 2 2006.285.14:19:19.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.14:19:19.05#ibcon#[27=AT04-05\r\n] 2006.285.14:19:19.05#ibcon#*before write, iclass 18, count 2 2006.285.14:19:19.05#ibcon#enter sib2, iclass 18, count 2 2006.285.14:19:19.05#ibcon#flushed, iclass 18, count 2 2006.285.14:19:19.05#ibcon#about to write, iclass 18, count 2 2006.285.14:19:19.05#ibcon#wrote, iclass 18, count 2 2006.285.14:19:19.05#ibcon#about to read 3, iclass 18, count 2 2006.285.14:19:19.08#ibcon#read 3, iclass 18, count 2 2006.285.14:19:19.08#ibcon#about to read 4, iclass 18, count 2 2006.285.14:19:19.08#ibcon#read 4, iclass 18, count 2 2006.285.14:19:19.08#ibcon#about to read 5, iclass 18, count 2 2006.285.14:19:19.08#ibcon#read 5, iclass 18, count 2 2006.285.14:19:19.08#ibcon#about to read 6, iclass 18, count 2 2006.285.14:19:19.08#ibcon#read 6, iclass 18, count 2 2006.285.14:19:19.08#ibcon#end of sib2, iclass 18, count 2 2006.285.14:19:19.08#ibcon#*after write, iclass 18, count 2 2006.285.14:19:19.08#ibcon#*before return 0, iclass 18, count 2 2006.285.14:19:19.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:19:19.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:19:19.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.14:19:19.08#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:19.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:19:19.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:19:19.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:19:19.20#ibcon#enter wrdev, iclass 18, count 0 2006.285.14:19:19.20#ibcon#first serial, iclass 18, count 0 2006.285.14:19:19.20#ibcon#enter sib2, iclass 18, count 0 2006.285.14:19:19.20#ibcon#flushed, iclass 18, count 0 2006.285.14:19:19.20#ibcon#about to write, iclass 18, count 0 2006.285.14:19:19.20#ibcon#wrote, iclass 18, count 0 2006.285.14:19:19.20#ibcon#about to read 3, iclass 18, count 0 2006.285.14:19:19.22#ibcon#read 3, iclass 18, count 0 2006.285.14:19:19.22#ibcon#about to read 4, iclass 18, count 0 2006.285.14:19:19.22#ibcon#read 4, iclass 18, count 0 2006.285.14:19:19.22#ibcon#about to read 5, iclass 18, count 0 2006.285.14:19:19.22#ibcon#read 5, iclass 18, count 0 2006.285.14:19:19.22#ibcon#about to read 6, iclass 18, count 0 2006.285.14:19:19.22#ibcon#read 6, iclass 18, count 0 2006.285.14:19:19.22#ibcon#end of sib2, iclass 18, count 0 2006.285.14:19:19.22#ibcon#*mode == 0, iclass 18, count 0 2006.285.14:19:19.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.14:19:19.22#ibcon#[27=USB\r\n] 2006.285.14:19:19.22#ibcon#*before write, iclass 18, count 0 2006.285.14:19:19.22#ibcon#enter sib2, iclass 18, count 0 2006.285.14:19:19.22#ibcon#flushed, iclass 18, count 0 2006.285.14:19:19.22#ibcon#about to write, iclass 18, count 0 2006.285.14:19:19.22#ibcon#wrote, iclass 18, count 0 2006.285.14:19:19.22#ibcon#about to read 3, iclass 18, count 0 2006.285.14:19:19.25#ibcon#read 3, iclass 18, count 0 2006.285.14:19:19.25#ibcon#about to read 4, iclass 18, count 0 2006.285.14:19:19.25#ibcon#read 4, iclass 18, count 0 2006.285.14:19:19.25#ibcon#about to read 5, iclass 18, count 0 2006.285.14:19:19.25#ibcon#read 5, iclass 18, count 0 2006.285.14:19:19.25#ibcon#about to read 6, iclass 18, count 0 2006.285.14:19:19.25#ibcon#read 6, iclass 18, count 0 2006.285.14:19:19.25#ibcon#end of sib2, iclass 18, count 0 2006.285.14:19:19.25#ibcon#*after write, iclass 18, count 0 2006.285.14:19:19.25#ibcon#*before return 0, iclass 18, count 0 2006.285.14:19:19.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:19:19.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:19:19.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.14:19:19.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.14:19:19.25$vck44/vblo=5,709.99 2006.285.14:19:19.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.14:19:19.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.14:19:19.25#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:19.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:19:19.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:19:19.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:19:19.25#ibcon#enter wrdev, iclass 20, count 0 2006.285.14:19:19.25#ibcon#first serial, iclass 20, count 0 2006.285.14:19:19.25#ibcon#enter sib2, iclass 20, count 0 2006.285.14:19:19.25#ibcon#flushed, iclass 20, count 0 2006.285.14:19:19.25#ibcon#about to write, iclass 20, count 0 2006.285.14:19:19.25#ibcon#wrote, iclass 20, count 0 2006.285.14:19:19.25#ibcon#about to read 3, iclass 20, count 0 2006.285.14:19:19.27#ibcon#read 3, iclass 20, count 0 2006.285.14:19:19.27#ibcon#about to read 4, iclass 20, count 0 2006.285.14:19:19.27#ibcon#read 4, iclass 20, count 0 2006.285.14:19:19.27#ibcon#about to read 5, iclass 20, count 0 2006.285.14:19:19.27#ibcon#read 5, iclass 20, count 0 2006.285.14:19:19.27#ibcon#about to read 6, iclass 20, count 0 2006.285.14:19:19.27#ibcon#read 6, iclass 20, count 0 2006.285.14:19:19.27#ibcon#end of sib2, iclass 20, count 0 2006.285.14:19:19.27#ibcon#*mode == 0, iclass 20, count 0 2006.285.14:19:19.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.14:19:19.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.14:19:19.27#ibcon#*before write, iclass 20, count 0 2006.285.14:19:19.27#ibcon#enter sib2, iclass 20, count 0 2006.285.14:19:19.27#ibcon#flushed, iclass 20, count 0 2006.285.14:19:19.27#ibcon#about to write, iclass 20, count 0 2006.285.14:19:19.27#ibcon#wrote, iclass 20, count 0 2006.285.14:19:19.27#ibcon#about to read 3, iclass 20, count 0 2006.285.14:19:19.31#ibcon#read 3, iclass 20, count 0 2006.285.14:19:19.31#ibcon#about to read 4, iclass 20, count 0 2006.285.14:19:19.31#ibcon#read 4, iclass 20, count 0 2006.285.14:19:19.31#ibcon#about to read 5, iclass 20, count 0 2006.285.14:19:19.31#ibcon#read 5, iclass 20, count 0 2006.285.14:19:19.31#ibcon#about to read 6, iclass 20, count 0 2006.285.14:19:19.31#ibcon#read 6, iclass 20, count 0 2006.285.14:19:19.31#ibcon#end of sib2, iclass 20, count 0 2006.285.14:19:19.31#ibcon#*after write, iclass 20, count 0 2006.285.14:19:19.31#ibcon#*before return 0, iclass 20, count 0 2006.285.14:19:19.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:19:19.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:19:19.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.14:19:19.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.14:19:19.31$vck44/vb=5,4 2006.285.14:19:19.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.14:19:19.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.14:19:19.31#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:19.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:19:19.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:19:19.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:19:19.37#ibcon#enter wrdev, iclass 22, count 2 2006.285.14:19:19.37#ibcon#first serial, iclass 22, count 2 2006.285.14:19:19.37#ibcon#enter sib2, iclass 22, count 2 2006.285.14:19:19.37#ibcon#flushed, iclass 22, count 2 2006.285.14:19:19.37#ibcon#about to write, iclass 22, count 2 2006.285.14:19:19.37#ibcon#wrote, iclass 22, count 2 2006.285.14:19:19.37#ibcon#about to read 3, iclass 22, count 2 2006.285.14:19:19.39#ibcon#read 3, iclass 22, count 2 2006.285.14:19:19.39#ibcon#about to read 4, iclass 22, count 2 2006.285.14:19:19.39#ibcon#read 4, iclass 22, count 2 2006.285.14:19:19.39#ibcon#about to read 5, iclass 22, count 2 2006.285.14:19:19.39#ibcon#read 5, iclass 22, count 2 2006.285.14:19:19.39#ibcon#about to read 6, iclass 22, count 2 2006.285.14:19:19.39#ibcon#read 6, iclass 22, count 2 2006.285.14:19:19.39#ibcon#end of sib2, iclass 22, count 2 2006.285.14:19:19.39#ibcon#*mode == 0, iclass 22, count 2 2006.285.14:19:19.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.14:19:19.39#ibcon#[27=AT05-04\r\n] 2006.285.14:19:19.39#ibcon#*before write, iclass 22, count 2 2006.285.14:19:19.39#ibcon#enter sib2, iclass 22, count 2 2006.285.14:19:19.39#ibcon#flushed, iclass 22, count 2 2006.285.14:19:19.39#ibcon#about to write, iclass 22, count 2 2006.285.14:19:19.39#ibcon#wrote, iclass 22, count 2 2006.285.14:19:19.39#ibcon#about to read 3, iclass 22, count 2 2006.285.14:19:19.42#ibcon#read 3, iclass 22, count 2 2006.285.14:19:19.62#ibcon#about to read 4, iclass 22, count 2 2006.285.14:19:19.62#ibcon#read 4, iclass 22, count 2 2006.285.14:19:19.62#ibcon#about to read 5, iclass 22, count 2 2006.285.14:19:19.62#ibcon#read 5, iclass 22, count 2 2006.285.14:19:19.62#ibcon#about to read 6, iclass 22, count 2 2006.285.14:19:19.62#ibcon#read 6, iclass 22, count 2 2006.285.14:19:19.62#ibcon#end of sib2, iclass 22, count 2 2006.285.14:19:19.62#ibcon#*after write, iclass 22, count 2 2006.285.14:19:19.62#ibcon#*before return 0, iclass 22, count 2 2006.285.14:19:19.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:19:19.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:19:19.62#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.14:19:19.62#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:19.62#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:19:19.74#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:19:19.74#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:19:19.74#ibcon#enter wrdev, iclass 22, count 0 2006.285.14:19:19.74#ibcon#first serial, iclass 22, count 0 2006.285.14:19:19.74#ibcon#enter sib2, iclass 22, count 0 2006.285.14:19:19.74#ibcon#flushed, iclass 22, count 0 2006.285.14:19:19.74#ibcon#about to write, iclass 22, count 0 2006.285.14:19:19.74#ibcon#wrote, iclass 22, count 0 2006.285.14:19:19.74#ibcon#about to read 3, iclass 22, count 0 2006.285.14:19:19.76#ibcon#read 3, iclass 22, count 0 2006.285.14:19:19.76#ibcon#about to read 4, iclass 22, count 0 2006.285.14:19:19.76#ibcon#read 4, iclass 22, count 0 2006.285.14:19:19.76#ibcon#about to read 5, iclass 22, count 0 2006.285.14:19:19.76#ibcon#read 5, iclass 22, count 0 2006.285.14:19:19.76#ibcon#about to read 6, iclass 22, count 0 2006.285.14:19:19.76#ibcon#read 6, iclass 22, count 0 2006.285.14:19:19.76#ibcon#end of sib2, iclass 22, count 0 2006.285.14:19:19.76#ibcon#*mode == 0, iclass 22, count 0 2006.285.14:19:19.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.14:19:19.76#ibcon#[27=USB\r\n] 2006.285.14:19:19.76#ibcon#*before write, iclass 22, count 0 2006.285.14:19:19.76#ibcon#enter sib2, iclass 22, count 0 2006.285.14:19:19.76#ibcon#flushed, iclass 22, count 0 2006.285.14:19:19.76#ibcon#about to write, iclass 22, count 0 2006.285.14:19:19.76#ibcon#wrote, iclass 22, count 0 2006.285.14:19:19.76#ibcon#about to read 3, iclass 22, count 0 2006.285.14:19:19.79#ibcon#read 3, iclass 22, count 0 2006.285.14:19:19.79#ibcon#about to read 4, iclass 22, count 0 2006.285.14:19:19.79#ibcon#read 4, iclass 22, count 0 2006.285.14:19:19.79#ibcon#about to read 5, iclass 22, count 0 2006.285.14:19:19.79#ibcon#read 5, iclass 22, count 0 2006.285.14:19:19.79#ibcon#about to read 6, iclass 22, count 0 2006.285.14:19:19.79#ibcon#read 6, iclass 22, count 0 2006.285.14:19:19.79#ibcon#end of sib2, iclass 22, count 0 2006.285.14:19:19.79#ibcon#*after write, iclass 22, count 0 2006.285.14:19:19.79#ibcon#*before return 0, iclass 22, count 0 2006.285.14:19:19.79#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:19:19.79#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:19:19.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.14:19:19.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.14:19:19.79$vck44/vblo=6,719.99 2006.285.14:19:19.79#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.14:19:19.79#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.14:19:19.79#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:19.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:19:19.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:19:19.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:19:19.79#ibcon#enter wrdev, iclass 24, count 0 2006.285.14:19:19.79#ibcon#first serial, iclass 24, count 0 2006.285.14:19:19.79#ibcon#enter sib2, iclass 24, count 0 2006.285.14:19:19.79#ibcon#flushed, iclass 24, count 0 2006.285.14:19:19.79#ibcon#about to write, iclass 24, count 0 2006.285.14:19:19.79#ibcon#wrote, iclass 24, count 0 2006.285.14:19:19.79#ibcon#about to read 3, iclass 24, count 0 2006.285.14:19:19.81#ibcon#read 3, iclass 24, count 0 2006.285.14:19:19.81#ibcon#about to read 4, iclass 24, count 0 2006.285.14:19:19.81#ibcon#read 4, iclass 24, count 0 2006.285.14:19:19.81#ibcon#about to read 5, iclass 24, count 0 2006.285.14:19:19.81#ibcon#read 5, iclass 24, count 0 2006.285.14:19:19.81#ibcon#about to read 6, iclass 24, count 0 2006.285.14:19:19.81#ibcon#read 6, iclass 24, count 0 2006.285.14:19:19.81#ibcon#end of sib2, iclass 24, count 0 2006.285.14:19:19.81#ibcon#*mode == 0, iclass 24, count 0 2006.285.14:19:19.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.14:19:19.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.14:19:19.81#ibcon#*before write, iclass 24, count 0 2006.285.14:19:19.81#ibcon#enter sib2, iclass 24, count 0 2006.285.14:19:19.81#ibcon#flushed, iclass 24, count 0 2006.285.14:19:19.81#ibcon#about to write, iclass 24, count 0 2006.285.14:19:19.81#ibcon#wrote, iclass 24, count 0 2006.285.14:19:19.81#ibcon#about to read 3, iclass 24, count 0 2006.285.14:19:19.85#ibcon#read 3, iclass 24, count 0 2006.285.14:19:19.85#ibcon#about to read 4, iclass 24, count 0 2006.285.14:19:19.85#ibcon#read 4, iclass 24, count 0 2006.285.14:19:19.85#ibcon#about to read 5, iclass 24, count 0 2006.285.14:19:19.85#ibcon#read 5, iclass 24, count 0 2006.285.14:19:19.85#ibcon#about to read 6, iclass 24, count 0 2006.285.14:19:19.85#ibcon#read 6, iclass 24, count 0 2006.285.14:19:19.85#ibcon#end of sib2, iclass 24, count 0 2006.285.14:19:19.85#ibcon#*after write, iclass 24, count 0 2006.285.14:19:19.85#ibcon#*before return 0, iclass 24, count 0 2006.285.14:19:19.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:19:19.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:19:19.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.14:19:19.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.14:19:19.85$vck44/vb=6,3 2006.285.14:19:19.85#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.14:19:19.85#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.14:19:19.85#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:19.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:19:19.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:19:19.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:19:19.91#ibcon#enter wrdev, iclass 26, count 2 2006.285.14:19:19.91#ibcon#first serial, iclass 26, count 2 2006.285.14:19:19.91#ibcon#enter sib2, iclass 26, count 2 2006.285.14:19:19.91#ibcon#flushed, iclass 26, count 2 2006.285.14:19:19.91#ibcon#about to write, iclass 26, count 2 2006.285.14:19:19.91#ibcon#wrote, iclass 26, count 2 2006.285.14:19:19.91#ibcon#about to read 3, iclass 26, count 2 2006.285.14:19:19.93#ibcon#read 3, iclass 26, count 2 2006.285.14:19:19.93#ibcon#about to read 4, iclass 26, count 2 2006.285.14:19:19.93#ibcon#read 4, iclass 26, count 2 2006.285.14:19:19.93#ibcon#about to read 5, iclass 26, count 2 2006.285.14:19:19.93#ibcon#read 5, iclass 26, count 2 2006.285.14:19:19.93#ibcon#about to read 6, iclass 26, count 2 2006.285.14:19:19.93#ibcon#read 6, iclass 26, count 2 2006.285.14:19:19.93#ibcon#end of sib2, iclass 26, count 2 2006.285.14:19:19.93#ibcon#*mode == 0, iclass 26, count 2 2006.285.14:19:19.93#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.14:19:19.93#ibcon#[27=AT06-03\r\n] 2006.285.14:19:19.93#ibcon#*before write, iclass 26, count 2 2006.285.14:19:19.93#ibcon#enter sib2, iclass 26, count 2 2006.285.14:19:19.93#ibcon#flushed, iclass 26, count 2 2006.285.14:19:19.93#ibcon#about to write, iclass 26, count 2 2006.285.14:19:19.93#ibcon#wrote, iclass 26, count 2 2006.285.14:19:19.93#ibcon#about to read 3, iclass 26, count 2 2006.285.14:19:19.96#ibcon#read 3, iclass 26, count 2 2006.285.14:19:19.96#ibcon#about to read 4, iclass 26, count 2 2006.285.14:19:19.96#ibcon#read 4, iclass 26, count 2 2006.285.14:19:19.96#ibcon#about to read 5, iclass 26, count 2 2006.285.14:19:19.96#ibcon#read 5, iclass 26, count 2 2006.285.14:19:19.96#ibcon#about to read 6, iclass 26, count 2 2006.285.14:19:19.96#ibcon#read 6, iclass 26, count 2 2006.285.14:19:19.96#ibcon#end of sib2, iclass 26, count 2 2006.285.14:19:19.96#ibcon#*after write, iclass 26, count 2 2006.285.14:19:19.96#ibcon#*before return 0, iclass 26, count 2 2006.285.14:19:19.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:19:19.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:19:19.96#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.14:19:19.96#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:19.96#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:19:20.08#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:19:20.08#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:19:20.08#ibcon#enter wrdev, iclass 26, count 0 2006.285.14:19:20.08#ibcon#first serial, iclass 26, count 0 2006.285.14:19:20.08#ibcon#enter sib2, iclass 26, count 0 2006.285.14:19:20.08#ibcon#flushed, iclass 26, count 0 2006.285.14:19:20.08#ibcon#about to write, iclass 26, count 0 2006.285.14:19:20.08#ibcon#wrote, iclass 26, count 0 2006.285.14:19:20.08#ibcon#about to read 3, iclass 26, count 0 2006.285.14:19:20.10#ibcon#read 3, iclass 26, count 0 2006.285.14:19:20.10#ibcon#about to read 4, iclass 26, count 0 2006.285.14:19:20.10#ibcon#read 4, iclass 26, count 0 2006.285.14:19:20.10#ibcon#about to read 5, iclass 26, count 0 2006.285.14:19:20.10#ibcon#read 5, iclass 26, count 0 2006.285.14:19:20.10#ibcon#about to read 6, iclass 26, count 0 2006.285.14:19:20.10#ibcon#read 6, iclass 26, count 0 2006.285.14:19:20.10#ibcon#end of sib2, iclass 26, count 0 2006.285.14:19:20.10#ibcon#*mode == 0, iclass 26, count 0 2006.285.14:19:20.10#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.14:19:20.10#ibcon#[27=USB\r\n] 2006.285.14:19:20.10#ibcon#*before write, iclass 26, count 0 2006.285.14:19:20.10#ibcon#enter sib2, iclass 26, count 0 2006.285.14:19:20.10#ibcon#flushed, iclass 26, count 0 2006.285.14:19:20.10#ibcon#about to write, iclass 26, count 0 2006.285.14:19:20.10#ibcon#wrote, iclass 26, count 0 2006.285.14:19:20.10#ibcon#about to read 3, iclass 26, count 0 2006.285.14:19:20.13#ibcon#read 3, iclass 26, count 0 2006.285.14:19:20.13#ibcon#about to read 4, iclass 26, count 0 2006.285.14:19:20.13#ibcon#read 4, iclass 26, count 0 2006.285.14:19:20.13#ibcon#about to read 5, iclass 26, count 0 2006.285.14:19:20.13#ibcon#read 5, iclass 26, count 0 2006.285.14:19:20.13#ibcon#about to read 6, iclass 26, count 0 2006.285.14:19:20.13#ibcon#read 6, iclass 26, count 0 2006.285.14:19:20.13#ibcon#end of sib2, iclass 26, count 0 2006.285.14:19:20.13#ibcon#*after write, iclass 26, count 0 2006.285.14:19:20.13#ibcon#*before return 0, iclass 26, count 0 2006.285.14:19:20.13#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:19:20.13#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:19:20.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.14:19:20.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.14:19:20.13$vck44/vblo=7,734.99 2006.285.14:19:20.13#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.14:19:20.13#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.14:19:20.13#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:20.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:19:20.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:19:20.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:19:20.13#ibcon#enter wrdev, iclass 28, count 0 2006.285.14:19:20.13#ibcon#first serial, iclass 28, count 0 2006.285.14:19:20.13#ibcon#enter sib2, iclass 28, count 0 2006.285.14:19:20.13#ibcon#flushed, iclass 28, count 0 2006.285.14:19:20.13#ibcon#about to write, iclass 28, count 0 2006.285.14:19:20.13#ibcon#wrote, iclass 28, count 0 2006.285.14:19:20.13#ibcon#about to read 3, iclass 28, count 0 2006.285.14:19:20.15#ibcon#read 3, iclass 28, count 0 2006.285.14:19:20.15#ibcon#about to read 4, iclass 28, count 0 2006.285.14:19:20.15#ibcon#read 4, iclass 28, count 0 2006.285.14:19:20.15#ibcon#about to read 5, iclass 28, count 0 2006.285.14:19:20.15#ibcon#read 5, iclass 28, count 0 2006.285.14:19:20.15#ibcon#about to read 6, iclass 28, count 0 2006.285.14:19:20.15#ibcon#read 6, iclass 28, count 0 2006.285.14:19:20.15#ibcon#end of sib2, iclass 28, count 0 2006.285.14:19:20.15#ibcon#*mode == 0, iclass 28, count 0 2006.285.14:19:20.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.14:19:20.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.14:19:20.15#ibcon#*before write, iclass 28, count 0 2006.285.14:19:20.15#ibcon#enter sib2, iclass 28, count 0 2006.285.14:19:20.15#ibcon#flushed, iclass 28, count 0 2006.285.14:19:20.15#ibcon#about to write, iclass 28, count 0 2006.285.14:19:20.15#ibcon#wrote, iclass 28, count 0 2006.285.14:19:20.15#ibcon#about to read 3, iclass 28, count 0 2006.285.14:19:20.19#ibcon#read 3, iclass 28, count 0 2006.285.14:19:20.19#ibcon#about to read 4, iclass 28, count 0 2006.285.14:19:20.19#ibcon#read 4, iclass 28, count 0 2006.285.14:19:20.19#ibcon#about to read 5, iclass 28, count 0 2006.285.14:19:20.19#ibcon#read 5, iclass 28, count 0 2006.285.14:19:20.19#ibcon#about to read 6, iclass 28, count 0 2006.285.14:19:20.19#ibcon#read 6, iclass 28, count 0 2006.285.14:19:20.19#ibcon#end of sib2, iclass 28, count 0 2006.285.14:19:20.19#ibcon#*after write, iclass 28, count 0 2006.285.14:19:20.19#ibcon#*before return 0, iclass 28, count 0 2006.285.14:19:20.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:19:20.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:19:20.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.14:19:20.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.14:19:20.19$vck44/vb=7,4 2006.285.14:19:20.19#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.14:19:20.19#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.14:19:20.19#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:20.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:19:20.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:19:20.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:19:20.25#ibcon#enter wrdev, iclass 30, count 2 2006.285.14:19:20.25#ibcon#first serial, iclass 30, count 2 2006.285.14:19:20.25#ibcon#enter sib2, iclass 30, count 2 2006.285.14:19:20.25#ibcon#flushed, iclass 30, count 2 2006.285.14:19:20.25#ibcon#about to write, iclass 30, count 2 2006.285.14:19:20.25#ibcon#wrote, iclass 30, count 2 2006.285.14:19:20.25#ibcon#about to read 3, iclass 30, count 2 2006.285.14:19:20.27#ibcon#read 3, iclass 30, count 2 2006.285.14:19:20.27#ibcon#about to read 4, iclass 30, count 2 2006.285.14:19:20.27#ibcon#read 4, iclass 30, count 2 2006.285.14:19:20.27#ibcon#about to read 5, iclass 30, count 2 2006.285.14:19:20.27#ibcon#read 5, iclass 30, count 2 2006.285.14:19:20.27#ibcon#about to read 6, iclass 30, count 2 2006.285.14:19:20.27#ibcon#read 6, iclass 30, count 2 2006.285.14:19:20.27#ibcon#end of sib2, iclass 30, count 2 2006.285.14:19:20.27#ibcon#*mode == 0, iclass 30, count 2 2006.285.14:19:20.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.14:19:20.27#ibcon#[27=AT07-04\r\n] 2006.285.14:19:20.27#ibcon#*before write, iclass 30, count 2 2006.285.14:19:20.27#ibcon#enter sib2, iclass 30, count 2 2006.285.14:19:20.27#ibcon#flushed, iclass 30, count 2 2006.285.14:19:20.27#ibcon#about to write, iclass 30, count 2 2006.285.14:19:20.27#ibcon#wrote, iclass 30, count 2 2006.285.14:19:20.27#ibcon#about to read 3, iclass 30, count 2 2006.285.14:19:20.30#ibcon#read 3, iclass 30, count 2 2006.285.14:19:20.30#ibcon#about to read 4, iclass 30, count 2 2006.285.14:19:20.30#ibcon#read 4, iclass 30, count 2 2006.285.14:19:20.30#ibcon#about to read 5, iclass 30, count 2 2006.285.14:19:20.30#ibcon#read 5, iclass 30, count 2 2006.285.14:19:20.30#ibcon#about to read 6, iclass 30, count 2 2006.285.14:19:20.30#ibcon#read 6, iclass 30, count 2 2006.285.14:19:20.30#ibcon#end of sib2, iclass 30, count 2 2006.285.14:19:20.30#ibcon#*after write, iclass 30, count 2 2006.285.14:19:20.30#ibcon#*before return 0, iclass 30, count 2 2006.285.14:19:20.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:19:20.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:19:20.30#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.14:19:20.30#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:20.30#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:19:20.42#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:19:20.42#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:19:20.42#ibcon#enter wrdev, iclass 30, count 0 2006.285.14:19:20.42#ibcon#first serial, iclass 30, count 0 2006.285.14:19:20.42#ibcon#enter sib2, iclass 30, count 0 2006.285.14:19:20.42#ibcon#flushed, iclass 30, count 0 2006.285.14:19:20.42#ibcon#about to write, iclass 30, count 0 2006.285.14:19:20.42#ibcon#wrote, iclass 30, count 0 2006.285.14:19:20.42#ibcon#about to read 3, iclass 30, count 0 2006.285.14:19:20.44#ibcon#read 3, iclass 30, count 0 2006.285.14:19:20.44#ibcon#about to read 4, iclass 30, count 0 2006.285.14:19:20.44#ibcon#read 4, iclass 30, count 0 2006.285.14:19:20.44#ibcon#about to read 5, iclass 30, count 0 2006.285.14:19:20.44#ibcon#read 5, iclass 30, count 0 2006.285.14:19:20.44#ibcon#about to read 6, iclass 30, count 0 2006.285.14:19:20.44#ibcon#read 6, iclass 30, count 0 2006.285.14:19:20.44#ibcon#end of sib2, iclass 30, count 0 2006.285.14:19:20.44#ibcon#*mode == 0, iclass 30, count 0 2006.285.14:19:20.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.14:19:20.44#ibcon#[27=USB\r\n] 2006.285.14:19:20.44#ibcon#*before write, iclass 30, count 0 2006.285.14:19:20.44#ibcon#enter sib2, iclass 30, count 0 2006.285.14:19:20.44#ibcon#flushed, iclass 30, count 0 2006.285.14:19:20.44#ibcon#about to write, iclass 30, count 0 2006.285.14:19:20.44#ibcon#wrote, iclass 30, count 0 2006.285.14:19:20.44#ibcon#about to read 3, iclass 30, count 0 2006.285.14:19:20.47#ibcon#read 3, iclass 30, count 0 2006.285.14:19:20.47#ibcon#about to read 4, iclass 30, count 0 2006.285.14:19:20.47#ibcon#read 4, iclass 30, count 0 2006.285.14:19:20.47#ibcon#about to read 5, iclass 30, count 0 2006.285.14:19:20.47#ibcon#read 5, iclass 30, count 0 2006.285.14:19:20.47#ibcon#about to read 6, iclass 30, count 0 2006.285.14:19:20.47#ibcon#read 6, iclass 30, count 0 2006.285.14:19:20.47#ibcon#end of sib2, iclass 30, count 0 2006.285.14:19:20.47#ibcon#*after write, iclass 30, count 0 2006.285.14:19:20.47#ibcon#*before return 0, iclass 30, count 0 2006.285.14:19:20.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:19:20.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:19:20.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.14:19:20.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.14:19:20.47$vck44/vblo=8,744.99 2006.285.14:19:20.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.14:19:20.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.14:19:20.47#ibcon#ireg 17 cls_cnt 0 2006.285.14:19:20.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:19:20.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:19:20.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:19:20.47#ibcon#enter wrdev, iclass 32, count 0 2006.285.14:19:20.47#ibcon#first serial, iclass 32, count 0 2006.285.14:19:20.47#ibcon#enter sib2, iclass 32, count 0 2006.285.14:19:20.47#ibcon#flushed, iclass 32, count 0 2006.285.14:19:20.47#ibcon#about to write, iclass 32, count 0 2006.285.14:19:20.47#ibcon#wrote, iclass 32, count 0 2006.285.14:19:20.47#ibcon#about to read 3, iclass 32, count 0 2006.285.14:19:20.49#ibcon#read 3, iclass 32, count 0 2006.285.14:19:20.49#ibcon#about to read 4, iclass 32, count 0 2006.285.14:19:20.49#ibcon#read 4, iclass 32, count 0 2006.285.14:19:20.49#ibcon#about to read 5, iclass 32, count 0 2006.285.14:19:20.49#ibcon#read 5, iclass 32, count 0 2006.285.14:19:20.49#ibcon#about to read 6, iclass 32, count 0 2006.285.14:19:20.49#ibcon#read 6, iclass 32, count 0 2006.285.14:19:20.49#ibcon#end of sib2, iclass 32, count 0 2006.285.14:19:20.49#ibcon#*mode == 0, iclass 32, count 0 2006.285.14:19:20.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.14:19:20.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.14:19:20.49#ibcon#*before write, iclass 32, count 0 2006.285.14:19:20.49#ibcon#enter sib2, iclass 32, count 0 2006.285.14:19:20.49#ibcon#flushed, iclass 32, count 0 2006.285.14:19:20.49#ibcon#about to write, iclass 32, count 0 2006.285.14:19:20.49#ibcon#wrote, iclass 32, count 0 2006.285.14:19:20.49#ibcon#about to read 3, iclass 32, count 0 2006.285.14:19:20.53#ibcon#read 3, iclass 32, count 0 2006.285.14:19:20.53#ibcon#about to read 4, iclass 32, count 0 2006.285.14:19:20.53#ibcon#read 4, iclass 32, count 0 2006.285.14:19:20.53#ibcon#about to read 5, iclass 32, count 0 2006.285.14:19:20.53#ibcon#read 5, iclass 32, count 0 2006.285.14:19:20.53#ibcon#about to read 6, iclass 32, count 0 2006.285.14:19:20.53#ibcon#read 6, iclass 32, count 0 2006.285.14:19:20.53#ibcon#end of sib2, iclass 32, count 0 2006.285.14:19:20.53#ibcon#*after write, iclass 32, count 0 2006.285.14:19:20.53#ibcon#*before return 0, iclass 32, count 0 2006.285.14:19:20.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:19:20.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:19:20.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.14:19:20.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.14:19:20.53$vck44/vb=8,4 2006.285.14:19:20.53#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.14:19:20.53#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.14:19:20.53#ibcon#ireg 11 cls_cnt 2 2006.285.14:19:20.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:19:20.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:19:20.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:19:20.59#ibcon#enter wrdev, iclass 34, count 2 2006.285.14:19:20.59#ibcon#first serial, iclass 34, count 2 2006.285.14:19:20.59#ibcon#enter sib2, iclass 34, count 2 2006.285.14:19:20.59#ibcon#flushed, iclass 34, count 2 2006.285.14:19:20.59#ibcon#about to write, iclass 34, count 2 2006.285.14:19:20.59#ibcon#wrote, iclass 34, count 2 2006.285.14:19:20.59#ibcon#about to read 3, iclass 34, count 2 2006.285.14:19:20.61#ibcon#read 3, iclass 34, count 2 2006.285.14:19:20.61#ibcon#about to read 4, iclass 34, count 2 2006.285.14:19:20.61#ibcon#read 4, iclass 34, count 2 2006.285.14:19:20.61#ibcon#about to read 5, iclass 34, count 2 2006.285.14:19:20.61#ibcon#read 5, iclass 34, count 2 2006.285.14:19:20.61#ibcon#about to read 6, iclass 34, count 2 2006.285.14:19:20.61#ibcon#read 6, iclass 34, count 2 2006.285.14:19:20.61#ibcon#end of sib2, iclass 34, count 2 2006.285.14:19:20.61#ibcon#*mode == 0, iclass 34, count 2 2006.285.14:19:20.61#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.14:19:20.61#ibcon#[27=AT08-04\r\n] 2006.285.14:19:20.61#ibcon#*before write, iclass 34, count 2 2006.285.14:19:20.61#ibcon#enter sib2, iclass 34, count 2 2006.285.14:19:20.61#ibcon#flushed, iclass 34, count 2 2006.285.14:19:20.61#ibcon#about to write, iclass 34, count 2 2006.285.14:19:20.61#ibcon#wrote, iclass 34, count 2 2006.285.14:19:20.61#ibcon#about to read 3, iclass 34, count 2 2006.285.14:19:20.64#ibcon#read 3, iclass 34, count 2 2006.285.14:19:20.64#ibcon#about to read 4, iclass 34, count 2 2006.285.14:19:20.64#ibcon#read 4, iclass 34, count 2 2006.285.14:19:20.64#ibcon#about to read 5, iclass 34, count 2 2006.285.14:19:20.64#ibcon#read 5, iclass 34, count 2 2006.285.14:19:20.64#ibcon#about to read 6, iclass 34, count 2 2006.285.14:19:20.64#ibcon#read 6, iclass 34, count 2 2006.285.14:19:20.64#ibcon#end of sib2, iclass 34, count 2 2006.285.14:19:20.64#ibcon#*after write, iclass 34, count 2 2006.285.14:19:20.64#ibcon#*before return 0, iclass 34, count 2 2006.285.14:19:20.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:19:20.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:19:20.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.14:19:20.64#ibcon#ireg 7 cls_cnt 0 2006.285.14:19:20.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:19:20.76#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:19:20.76#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:19:20.76#ibcon#enter wrdev, iclass 34, count 0 2006.285.14:19:20.76#ibcon#first serial, iclass 34, count 0 2006.285.14:19:20.76#ibcon#enter sib2, iclass 34, count 0 2006.285.14:19:20.76#ibcon#flushed, iclass 34, count 0 2006.285.14:19:20.76#ibcon#about to write, iclass 34, count 0 2006.285.14:19:20.76#ibcon#wrote, iclass 34, count 0 2006.285.14:19:20.76#ibcon#about to read 3, iclass 34, count 0 2006.285.14:19:20.78#ibcon#read 3, iclass 34, count 0 2006.285.14:19:20.78#ibcon#about to read 4, iclass 34, count 0 2006.285.14:19:20.78#ibcon#read 4, iclass 34, count 0 2006.285.14:19:20.78#ibcon#about to read 5, iclass 34, count 0 2006.285.14:19:20.78#ibcon#read 5, iclass 34, count 0 2006.285.14:19:20.78#ibcon#about to read 6, iclass 34, count 0 2006.285.14:19:20.78#ibcon#read 6, iclass 34, count 0 2006.285.14:19:20.78#ibcon#end of sib2, iclass 34, count 0 2006.285.14:19:20.78#ibcon#*mode == 0, iclass 34, count 0 2006.285.14:19:20.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.14:19:20.78#ibcon#[27=USB\r\n] 2006.285.14:19:20.78#ibcon#*before write, iclass 34, count 0 2006.285.14:19:20.78#ibcon#enter sib2, iclass 34, count 0 2006.285.14:19:20.78#ibcon#flushed, iclass 34, count 0 2006.285.14:19:20.78#ibcon#about to write, iclass 34, count 0 2006.285.14:19:20.78#ibcon#wrote, iclass 34, count 0 2006.285.14:19:20.78#ibcon#about to read 3, iclass 34, count 0 2006.285.14:19:20.81#ibcon#read 3, iclass 34, count 0 2006.285.14:19:20.81#ibcon#about to read 4, iclass 34, count 0 2006.285.14:19:20.81#ibcon#read 4, iclass 34, count 0 2006.285.14:19:20.81#ibcon#about to read 5, iclass 34, count 0 2006.285.14:19:20.81#ibcon#read 5, iclass 34, count 0 2006.285.14:19:20.81#ibcon#about to read 6, iclass 34, count 0 2006.285.14:19:20.81#ibcon#read 6, iclass 34, count 0 2006.285.14:19:20.81#ibcon#end of sib2, iclass 34, count 0 2006.285.14:19:20.81#ibcon#*after write, iclass 34, count 0 2006.285.14:19:20.81#ibcon#*before return 0, iclass 34, count 0 2006.285.14:19:20.81#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:19:20.81#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:19:20.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.14:19:20.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.14:19:20.81$vck44/vabw=wide 2006.285.14:19:20.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.14:19:20.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.14:19:20.81#ibcon#ireg 8 cls_cnt 0 2006.285.14:19:20.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:19:20.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:19:20.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:19:20.81#ibcon#enter wrdev, iclass 36, count 0 2006.285.14:19:20.81#ibcon#first serial, iclass 36, count 0 2006.285.14:19:20.81#ibcon#enter sib2, iclass 36, count 0 2006.285.14:19:20.81#ibcon#flushed, iclass 36, count 0 2006.285.14:19:20.81#ibcon#about to write, iclass 36, count 0 2006.285.14:19:20.81#ibcon#wrote, iclass 36, count 0 2006.285.14:19:20.81#ibcon#about to read 3, iclass 36, count 0 2006.285.14:19:20.83#ibcon#read 3, iclass 36, count 0 2006.285.14:19:20.83#ibcon#about to read 4, iclass 36, count 0 2006.285.14:19:20.83#ibcon#read 4, iclass 36, count 0 2006.285.14:19:20.83#ibcon#about to read 5, iclass 36, count 0 2006.285.14:19:20.83#ibcon#read 5, iclass 36, count 0 2006.285.14:19:20.83#ibcon#about to read 6, iclass 36, count 0 2006.285.14:19:20.83#ibcon#read 6, iclass 36, count 0 2006.285.14:19:20.83#ibcon#end of sib2, iclass 36, count 0 2006.285.14:19:20.83#ibcon#*mode == 0, iclass 36, count 0 2006.285.14:19:20.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.14:19:20.83#ibcon#[25=BW32\r\n] 2006.285.14:19:20.83#ibcon#*before write, iclass 36, count 0 2006.285.14:19:20.83#ibcon#enter sib2, iclass 36, count 0 2006.285.14:19:20.83#ibcon#flushed, iclass 36, count 0 2006.285.14:19:20.83#ibcon#about to write, iclass 36, count 0 2006.285.14:19:20.83#ibcon#wrote, iclass 36, count 0 2006.285.14:19:20.83#ibcon#about to read 3, iclass 36, count 0 2006.285.14:19:20.86#ibcon#read 3, iclass 36, count 0 2006.285.14:19:20.86#ibcon#about to read 4, iclass 36, count 0 2006.285.14:19:20.86#ibcon#read 4, iclass 36, count 0 2006.285.14:19:20.86#ibcon#about to read 5, iclass 36, count 0 2006.285.14:19:20.86#ibcon#read 5, iclass 36, count 0 2006.285.14:19:20.86#ibcon#about to read 6, iclass 36, count 0 2006.285.14:19:20.86#ibcon#read 6, iclass 36, count 0 2006.285.14:19:20.86#ibcon#end of sib2, iclass 36, count 0 2006.285.14:19:20.86#ibcon#*after write, iclass 36, count 0 2006.285.14:19:20.86#ibcon#*before return 0, iclass 36, count 0 2006.285.14:19:20.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:19:20.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:19:20.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.14:19:20.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.14:19:20.86$vck44/vbbw=wide 2006.285.14:19:20.86#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.14:19:20.86#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.14:19:20.86#ibcon#ireg 8 cls_cnt 0 2006.285.14:19:20.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:19:20.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:19:20.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:19:20.93#ibcon#enter wrdev, iclass 38, count 0 2006.285.14:19:20.93#ibcon#first serial, iclass 38, count 0 2006.285.14:19:20.93#ibcon#enter sib2, iclass 38, count 0 2006.285.14:19:20.93#ibcon#flushed, iclass 38, count 0 2006.285.14:19:20.93#ibcon#about to write, iclass 38, count 0 2006.285.14:19:20.93#ibcon#wrote, iclass 38, count 0 2006.285.14:19:20.93#ibcon#about to read 3, iclass 38, count 0 2006.285.14:19:20.95#ibcon#read 3, iclass 38, count 0 2006.285.14:19:20.95#ibcon#about to read 4, iclass 38, count 0 2006.285.14:19:20.95#ibcon#read 4, iclass 38, count 0 2006.285.14:19:20.95#ibcon#about to read 5, iclass 38, count 0 2006.285.14:19:20.95#ibcon#read 5, iclass 38, count 0 2006.285.14:19:20.95#ibcon#about to read 6, iclass 38, count 0 2006.285.14:19:20.95#ibcon#read 6, iclass 38, count 0 2006.285.14:19:20.95#ibcon#end of sib2, iclass 38, count 0 2006.285.14:19:20.95#ibcon#*mode == 0, iclass 38, count 0 2006.285.14:19:20.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.14:19:20.95#ibcon#[27=BW32\r\n] 2006.285.14:19:20.95#ibcon#*before write, iclass 38, count 0 2006.285.14:19:20.95#ibcon#enter sib2, iclass 38, count 0 2006.285.14:19:20.95#ibcon#flushed, iclass 38, count 0 2006.285.14:19:20.95#ibcon#about to write, iclass 38, count 0 2006.285.14:19:20.95#ibcon#wrote, iclass 38, count 0 2006.285.14:19:20.95#ibcon#about to read 3, iclass 38, count 0 2006.285.14:19:20.98#ibcon#read 3, iclass 38, count 0 2006.285.14:19:20.98#ibcon#about to read 4, iclass 38, count 0 2006.285.14:19:20.98#ibcon#read 4, iclass 38, count 0 2006.285.14:19:20.98#ibcon#about to read 5, iclass 38, count 0 2006.285.14:19:20.98#ibcon#read 5, iclass 38, count 0 2006.285.14:19:20.98#ibcon#about to read 6, iclass 38, count 0 2006.285.14:19:20.98#ibcon#read 6, iclass 38, count 0 2006.285.14:19:20.98#ibcon#end of sib2, iclass 38, count 0 2006.285.14:19:20.98#ibcon#*after write, iclass 38, count 0 2006.285.14:19:20.98#ibcon#*before return 0, iclass 38, count 0 2006.285.14:19:20.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:19:20.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:19:20.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.14:19:20.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.14:19:20.98$setupk4/ifdk4 2006.285.14:19:20.98$ifdk4/lo= 2006.285.14:19:20.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.14:19:20.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.14:19:20.98$ifdk4/patch= 2006.285.14:19:20.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.14:19:20.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.14:19:20.99$setupk4/!*+20s 2006.285.14:19:22.13#trakl#Source acquired 2006.285.14:19:23.13#flagr#flagr/antenna,acquired 2006.285.14:19:27.21#abcon#<5=/04 1.9 3.5 19.20 961015.1\r\n> 2006.285.14:19:27.23#abcon#{5=INTERFACE CLEAR} 2006.285.14:19:27.29#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:19:34.49$setupk4/"tpicd 2006.285.14:19:34.49$setupk4/echo=off 2006.285.14:19:34.49$setupk4/xlog=off 2006.285.14:19:34.49:!2006.285.14:20:19 2006.285.14:20:19.00:preob 2006.285.14:20:19.13/onsource/TRACKING 2006.285.14:20:19.13:!2006.285.14:20:29 2006.285.14:20:29.00:"tape 2006.285.14:20:29.00:"st=record 2006.285.14:20:29.00:data_valid=on 2006.285.14:20:29.00:midob 2006.285.14:20:29.13/onsource/TRACKING 2006.285.14:20:29.13/wx/19.19,1015.1,96 2006.285.14:20:29.19/cable/+6.4999E-03 2006.285.14:20:30.28/va/01,07,usb,yes,33,35 2006.285.14:20:30.28/va/02,06,usb,yes,33,33 2006.285.14:20:30.28/va/03,07,usb,yes,32,34 2006.285.14:20:30.28/va/04,06,usb,yes,34,35 2006.285.14:20:30.28/va/05,03,usb,yes,33,34 2006.285.14:20:30.28/va/06,04,usb,yes,30,29 2006.285.14:20:30.28/va/07,04,usb,yes,30,31 2006.285.14:20:30.28/va/08,03,usb,yes,31,38 2006.285.14:20:30.51/valo/01,524.99,yes,locked 2006.285.14:20:30.51/valo/02,534.99,yes,locked 2006.285.14:20:30.51/valo/03,564.99,yes,locked 2006.285.14:20:30.51/valo/04,624.99,yes,locked 2006.285.14:20:30.51/valo/05,734.99,yes,locked 2006.285.14:20:30.51/valo/06,814.99,yes,locked 2006.285.14:20:30.51/valo/07,864.99,yes,locked 2006.285.14:20:30.51/valo/08,884.99,yes,locked 2006.285.14:20:31.60/vb/01,04,usb,yes,40,30 2006.285.14:20:31.60/vb/02,05,usb,yes,31,35 2006.285.14:20:31.60/vb/03,04,usb,yes,30,37 2006.285.14:20:31.60/vb/04,05,usb,yes,30,29 2006.285.14:20:31.60/vb/05,04,usb,yes,26,29 2006.285.14:20:31.60/vb/06,03,usb,yes,38,34 2006.285.14:20:31.60/vb/07,04,usb,yes,31,31 2006.285.14:20:31.60/vb/08,04,usb,yes,28,31 2006.285.14:20:31.84/vblo/01,629.99,yes,locked 2006.285.14:20:31.84/vblo/02,634.99,yes,locked 2006.285.14:20:31.84/vblo/03,649.99,yes,locked 2006.285.14:20:31.84/vblo/04,679.99,yes,locked 2006.285.14:20:31.84/vblo/05,709.99,yes,locked 2006.285.14:20:31.84/vblo/06,719.99,yes,locked 2006.285.14:20:31.84/vblo/07,734.99,yes,locked 2006.285.14:20:31.84/vblo/08,744.99,yes,locked 2006.285.14:20:31.99/vabw/8 2006.285.14:20:32.14/vbbw/8 2006.285.14:20:32.23/xfe/off,on,12.2 2006.285.14:20:32.60/ifatt/23,28,28,28 2006.285.14:20:33.07/fmout-gps/S +2.74E-07 2006.285.14:20:33.09:!2006.285.14:23:19 2006.285.14:23:19.01:data_valid=off 2006.285.14:23:19.01:"et 2006.285.14:23:19.01:!+3s 2006.285.14:23:22.02:"tape 2006.285.14:23:22.02:postob 2006.285.14:23:22.11/cable/+6.4991E-03 2006.285.14:23:22.11/wx/19.19,1015.1,96 2006.285.14:23:23.08/fmout-gps/S +2.75E-07 2006.285.14:23:23.08:scan_name=285-1425,jd0610,80 2006.285.14:23:23.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.285.14:23:24.14#flagr#flagr/antenna,new-source 2006.285.14:23:24.14:checkk5 2006.285.14:23:24.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.14:23:25.04/chk_autoobs//k5ts2/ autoobs is running! 2006.285.14:23:25.46/chk_autoobs//k5ts3/ autoobs is running! 2006.285.14:23:25.91/chk_autoobs//k5ts4/ autoobs is running! 2006.285.14:23:26.32/chk_obsdata//k5ts1/T2851420??a.dat file size is correct (nominal:680MB, actual:676MB). 2006.285.14:23:26.70/chk_obsdata//k5ts2/T2851420??b.dat file size is correct (nominal:680MB, actual:676MB). 2006.285.14:23:27.18/chk_obsdata//k5ts3/T2851420??c.dat file size is correct (nominal:680MB, actual:676MB). 2006.285.14:23:27.56/chk_obsdata//k5ts4/T2851420??d.dat file size is correct (nominal:680MB, actual:676MB). 2006.285.14:23:28.39/k5log//k5ts1_log_newline 2006.285.14:23:29.17/k5log//k5ts2_log_newline 2006.285.14:23:29.99/k5log//k5ts3_log_newline 2006.285.14:23:30.88/k5log//k5ts4_log_newline 2006.285.14:23:30.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.14:23:30.90:setupk4=1 2006.285.14:23:30.90$setupk4/echo=on 2006.285.14:23:30.90$setupk4/pcalon 2006.285.14:23:30.90$pcalon/"no phase cal control is implemented here 2006.285.14:23:30.90$setupk4/"tpicd=stop 2006.285.14:23:30.90$setupk4/"rec=synch_on 2006.285.14:23:30.90$setupk4/"rec_mode=128 2006.285.14:23:30.90$setupk4/!* 2006.285.14:23:30.91$setupk4/recpk4 2006.285.14:23:30.91$recpk4/recpatch= 2006.285.14:23:30.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.14:23:30.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.14:23:30.91$setupk4/vck44 2006.285.14:23:30.91$vck44/valo=1,524.99 2006.285.14:23:30.91#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.14:23:30.91#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.14:23:30.91#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:30.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:23:30.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:23:30.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:23:30.91#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:23:30.91#ibcon#first serial, iclass 31, count 0 2006.285.14:23:30.91#ibcon#enter sib2, iclass 31, count 0 2006.285.14:23:30.91#ibcon#flushed, iclass 31, count 0 2006.285.14:23:30.91#ibcon#about to write, iclass 31, count 0 2006.285.14:23:30.91#ibcon#wrote, iclass 31, count 0 2006.285.14:23:30.91#ibcon#about to read 3, iclass 31, count 0 2006.285.14:23:30.92#ibcon#read 3, iclass 31, count 0 2006.285.14:23:30.92#ibcon#about to read 4, iclass 31, count 0 2006.285.14:23:30.92#ibcon#read 4, iclass 31, count 0 2006.285.14:23:30.92#ibcon#about to read 5, iclass 31, count 0 2006.285.14:23:30.92#ibcon#read 5, iclass 31, count 0 2006.285.14:23:30.92#ibcon#about to read 6, iclass 31, count 0 2006.285.14:23:30.92#ibcon#read 6, iclass 31, count 0 2006.285.14:23:30.92#ibcon#end of sib2, iclass 31, count 0 2006.285.14:23:30.92#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:23:30.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:23:30.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.14:23:30.92#ibcon#*before write, iclass 31, count 0 2006.285.14:23:30.92#ibcon#enter sib2, iclass 31, count 0 2006.285.14:23:30.92#ibcon#flushed, iclass 31, count 0 2006.285.14:23:30.92#ibcon#about to write, iclass 31, count 0 2006.285.14:23:30.92#ibcon#wrote, iclass 31, count 0 2006.285.14:23:30.92#ibcon#about to read 3, iclass 31, count 0 2006.285.14:23:30.97#ibcon#read 3, iclass 31, count 0 2006.285.14:23:30.97#ibcon#about to read 4, iclass 31, count 0 2006.285.14:23:30.97#ibcon#read 4, iclass 31, count 0 2006.285.14:23:30.97#ibcon#about to read 5, iclass 31, count 0 2006.285.14:23:30.97#ibcon#read 5, iclass 31, count 0 2006.285.14:23:30.97#ibcon#about to read 6, iclass 31, count 0 2006.285.14:23:30.97#ibcon#read 6, iclass 31, count 0 2006.285.14:23:30.97#ibcon#end of sib2, iclass 31, count 0 2006.285.14:23:30.97#ibcon#*after write, iclass 31, count 0 2006.285.14:23:30.97#ibcon#*before return 0, iclass 31, count 0 2006.285.14:23:30.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:23:30.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:23:30.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:23:30.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:23:30.97$vck44/va=1,7 2006.285.14:23:30.97#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.14:23:30.97#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.14:23:30.97#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:30.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:23:30.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:23:30.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:23:30.97#ibcon#enter wrdev, iclass 33, count 2 2006.285.14:23:30.97#ibcon#first serial, iclass 33, count 2 2006.285.14:23:30.97#ibcon#enter sib2, iclass 33, count 2 2006.285.14:23:30.97#ibcon#flushed, iclass 33, count 2 2006.285.14:23:30.97#ibcon#about to write, iclass 33, count 2 2006.285.14:23:30.97#ibcon#wrote, iclass 33, count 2 2006.285.14:23:30.97#ibcon#about to read 3, iclass 33, count 2 2006.285.14:23:30.99#ibcon#read 3, iclass 33, count 2 2006.285.14:23:30.99#ibcon#about to read 4, iclass 33, count 2 2006.285.14:23:30.99#ibcon#read 4, iclass 33, count 2 2006.285.14:23:30.99#ibcon#about to read 5, iclass 33, count 2 2006.285.14:23:30.99#ibcon#read 5, iclass 33, count 2 2006.285.14:23:30.99#ibcon#about to read 6, iclass 33, count 2 2006.285.14:23:30.99#ibcon#read 6, iclass 33, count 2 2006.285.14:23:30.99#ibcon#end of sib2, iclass 33, count 2 2006.285.14:23:30.99#ibcon#*mode == 0, iclass 33, count 2 2006.285.14:23:30.99#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.14:23:30.99#ibcon#[25=AT01-07\r\n] 2006.285.14:23:30.99#ibcon#*before write, iclass 33, count 2 2006.285.14:23:30.99#ibcon#enter sib2, iclass 33, count 2 2006.285.14:23:30.99#ibcon#flushed, iclass 33, count 2 2006.285.14:23:30.99#ibcon#about to write, iclass 33, count 2 2006.285.14:23:30.99#ibcon#wrote, iclass 33, count 2 2006.285.14:23:30.99#ibcon#about to read 3, iclass 33, count 2 2006.285.14:23:31.02#ibcon#read 3, iclass 33, count 2 2006.285.14:23:31.02#ibcon#about to read 4, iclass 33, count 2 2006.285.14:23:31.02#ibcon#read 4, iclass 33, count 2 2006.285.14:23:31.02#ibcon#about to read 5, iclass 33, count 2 2006.285.14:23:31.02#ibcon#read 5, iclass 33, count 2 2006.285.14:23:31.02#ibcon#about to read 6, iclass 33, count 2 2006.285.14:23:31.02#ibcon#read 6, iclass 33, count 2 2006.285.14:23:31.02#ibcon#end of sib2, iclass 33, count 2 2006.285.14:23:31.02#ibcon#*after write, iclass 33, count 2 2006.285.14:23:31.02#ibcon#*before return 0, iclass 33, count 2 2006.285.14:23:31.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:23:31.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:23:31.02#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.14:23:31.02#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:31.02#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:23:31.14#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:23:31.14#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:23:31.14#ibcon#enter wrdev, iclass 33, count 0 2006.285.14:23:31.14#ibcon#first serial, iclass 33, count 0 2006.285.14:23:31.14#ibcon#enter sib2, iclass 33, count 0 2006.285.14:23:31.14#ibcon#flushed, iclass 33, count 0 2006.285.14:23:31.14#ibcon#about to write, iclass 33, count 0 2006.285.14:23:31.14#ibcon#wrote, iclass 33, count 0 2006.285.14:23:31.14#ibcon#about to read 3, iclass 33, count 0 2006.285.14:23:31.16#ibcon#read 3, iclass 33, count 0 2006.285.14:23:31.16#ibcon#about to read 4, iclass 33, count 0 2006.285.14:23:31.16#ibcon#read 4, iclass 33, count 0 2006.285.14:23:31.16#ibcon#about to read 5, iclass 33, count 0 2006.285.14:23:31.16#ibcon#read 5, iclass 33, count 0 2006.285.14:23:31.16#ibcon#about to read 6, iclass 33, count 0 2006.285.14:23:31.16#ibcon#read 6, iclass 33, count 0 2006.285.14:23:31.16#ibcon#end of sib2, iclass 33, count 0 2006.285.14:23:31.16#ibcon#*mode == 0, iclass 33, count 0 2006.285.14:23:31.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.14:23:31.16#ibcon#[25=USB\r\n] 2006.285.14:23:31.16#ibcon#*before write, iclass 33, count 0 2006.285.14:23:31.16#ibcon#enter sib2, iclass 33, count 0 2006.285.14:23:31.16#ibcon#flushed, iclass 33, count 0 2006.285.14:23:31.16#ibcon#about to write, iclass 33, count 0 2006.285.14:23:31.16#ibcon#wrote, iclass 33, count 0 2006.285.14:23:31.16#ibcon#about to read 3, iclass 33, count 0 2006.285.14:23:31.19#ibcon#read 3, iclass 33, count 0 2006.285.14:23:31.19#ibcon#about to read 4, iclass 33, count 0 2006.285.14:23:31.19#ibcon#read 4, iclass 33, count 0 2006.285.14:23:31.19#ibcon#about to read 5, iclass 33, count 0 2006.285.14:23:31.19#ibcon#read 5, iclass 33, count 0 2006.285.14:23:31.19#ibcon#about to read 6, iclass 33, count 0 2006.285.14:23:31.19#ibcon#read 6, iclass 33, count 0 2006.285.14:23:31.19#ibcon#end of sib2, iclass 33, count 0 2006.285.14:23:31.19#ibcon#*after write, iclass 33, count 0 2006.285.14:23:31.19#ibcon#*before return 0, iclass 33, count 0 2006.285.14:23:31.19#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:23:31.19#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:23:31.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.14:23:31.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.14:23:31.19$vck44/valo=2,534.99 2006.285.14:23:31.19#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.14:23:31.19#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.14:23:31.19#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:31.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:23:31.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:23:31.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:23:31.19#ibcon#enter wrdev, iclass 35, count 0 2006.285.14:23:31.19#ibcon#first serial, iclass 35, count 0 2006.285.14:23:31.19#ibcon#enter sib2, iclass 35, count 0 2006.285.14:23:31.19#ibcon#flushed, iclass 35, count 0 2006.285.14:23:31.19#ibcon#about to write, iclass 35, count 0 2006.285.14:23:31.19#ibcon#wrote, iclass 35, count 0 2006.285.14:23:31.19#ibcon#about to read 3, iclass 35, count 0 2006.285.14:23:31.21#ibcon#read 3, iclass 35, count 0 2006.285.14:23:31.21#ibcon#about to read 4, iclass 35, count 0 2006.285.14:23:31.21#ibcon#read 4, iclass 35, count 0 2006.285.14:23:31.21#ibcon#about to read 5, iclass 35, count 0 2006.285.14:23:31.21#ibcon#read 5, iclass 35, count 0 2006.285.14:23:31.21#ibcon#about to read 6, iclass 35, count 0 2006.285.14:23:31.21#ibcon#read 6, iclass 35, count 0 2006.285.14:23:31.21#ibcon#end of sib2, iclass 35, count 0 2006.285.14:23:31.21#ibcon#*mode == 0, iclass 35, count 0 2006.285.14:23:31.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.14:23:31.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.14:23:31.21#ibcon#*before write, iclass 35, count 0 2006.285.14:23:31.21#ibcon#enter sib2, iclass 35, count 0 2006.285.14:23:31.21#ibcon#flushed, iclass 35, count 0 2006.285.14:23:31.21#ibcon#about to write, iclass 35, count 0 2006.285.14:23:31.21#ibcon#wrote, iclass 35, count 0 2006.285.14:23:31.21#ibcon#about to read 3, iclass 35, count 0 2006.285.14:23:31.25#ibcon#read 3, iclass 35, count 0 2006.285.14:23:31.25#ibcon#about to read 4, iclass 35, count 0 2006.285.14:23:31.25#ibcon#read 4, iclass 35, count 0 2006.285.14:23:31.25#ibcon#about to read 5, iclass 35, count 0 2006.285.14:23:31.25#ibcon#read 5, iclass 35, count 0 2006.285.14:23:31.25#ibcon#about to read 6, iclass 35, count 0 2006.285.14:23:31.25#ibcon#read 6, iclass 35, count 0 2006.285.14:23:31.25#ibcon#end of sib2, iclass 35, count 0 2006.285.14:23:31.25#ibcon#*after write, iclass 35, count 0 2006.285.14:23:31.25#ibcon#*before return 0, iclass 35, count 0 2006.285.14:23:31.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:23:31.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:23:31.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.14:23:31.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.14:23:31.25$vck44/va=2,6 2006.285.14:23:31.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.14:23:31.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.14:23:31.25#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:31.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:23:31.29#abcon#<5=/04 1.9 4.1 19.19 961015.1\r\n> 2006.285.14:23:31.31#abcon#{5=INTERFACE CLEAR} 2006.285.14:23:31.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:23:31.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:23:31.31#ibcon#enter wrdev, iclass 38, count 2 2006.285.14:23:31.31#ibcon#first serial, iclass 38, count 2 2006.285.14:23:31.31#ibcon#enter sib2, iclass 38, count 2 2006.285.14:23:31.31#ibcon#flushed, iclass 38, count 2 2006.285.14:23:31.31#ibcon#about to write, iclass 38, count 2 2006.285.14:23:31.31#ibcon#wrote, iclass 38, count 2 2006.285.14:23:31.31#ibcon#about to read 3, iclass 38, count 2 2006.285.14:23:31.33#ibcon#read 3, iclass 38, count 2 2006.285.14:23:31.33#ibcon#about to read 4, iclass 38, count 2 2006.285.14:23:31.33#ibcon#read 4, iclass 38, count 2 2006.285.14:23:31.33#ibcon#about to read 5, iclass 38, count 2 2006.285.14:23:31.33#ibcon#read 5, iclass 38, count 2 2006.285.14:23:31.33#ibcon#about to read 6, iclass 38, count 2 2006.285.14:23:31.33#ibcon#read 6, iclass 38, count 2 2006.285.14:23:31.33#ibcon#end of sib2, iclass 38, count 2 2006.285.14:23:31.33#ibcon#*mode == 0, iclass 38, count 2 2006.285.14:23:31.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.14:23:31.33#ibcon#[25=AT02-06\r\n] 2006.285.14:23:31.33#ibcon#*before write, iclass 38, count 2 2006.285.14:23:31.33#ibcon#enter sib2, iclass 38, count 2 2006.285.14:23:31.33#ibcon#flushed, iclass 38, count 2 2006.285.14:23:31.33#ibcon#about to write, iclass 38, count 2 2006.285.14:23:31.33#ibcon#wrote, iclass 38, count 2 2006.285.14:23:31.33#ibcon#about to read 3, iclass 38, count 2 2006.285.14:23:31.36#ibcon#read 3, iclass 38, count 2 2006.285.14:23:31.36#ibcon#about to read 4, iclass 38, count 2 2006.285.14:23:31.36#ibcon#read 4, iclass 38, count 2 2006.285.14:23:31.36#ibcon#about to read 5, iclass 38, count 2 2006.285.14:23:31.36#ibcon#read 5, iclass 38, count 2 2006.285.14:23:31.36#ibcon#about to read 6, iclass 38, count 2 2006.285.14:23:31.36#ibcon#read 6, iclass 38, count 2 2006.285.14:23:31.36#ibcon#end of sib2, iclass 38, count 2 2006.285.14:23:31.36#ibcon#*after write, iclass 38, count 2 2006.285.14:23:31.36#ibcon#*before return 0, iclass 38, count 2 2006.285.14:23:31.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:23:31.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:23:31.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.14:23:31.36#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:31.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:23:31.37#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:23:31.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:23:31.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:23:31.48#ibcon#enter wrdev, iclass 38, count 0 2006.285.14:23:31.48#ibcon#first serial, iclass 38, count 0 2006.285.14:23:31.48#ibcon#enter sib2, iclass 38, count 0 2006.285.14:23:31.48#ibcon#flushed, iclass 38, count 0 2006.285.14:23:31.48#ibcon#about to write, iclass 38, count 0 2006.285.14:23:31.48#ibcon#wrote, iclass 38, count 0 2006.285.14:23:31.48#ibcon#about to read 3, iclass 38, count 0 2006.285.14:23:31.50#ibcon#read 3, iclass 38, count 0 2006.285.14:23:31.50#ibcon#about to read 4, iclass 38, count 0 2006.285.14:23:31.50#ibcon#read 4, iclass 38, count 0 2006.285.14:23:31.50#ibcon#about to read 5, iclass 38, count 0 2006.285.14:23:31.50#ibcon#read 5, iclass 38, count 0 2006.285.14:23:31.50#ibcon#about to read 6, iclass 38, count 0 2006.285.14:23:31.50#ibcon#read 6, iclass 38, count 0 2006.285.14:23:31.50#ibcon#end of sib2, iclass 38, count 0 2006.285.14:23:31.50#ibcon#*mode == 0, iclass 38, count 0 2006.285.14:23:31.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.14:23:31.50#ibcon#[25=USB\r\n] 2006.285.14:23:31.50#ibcon#*before write, iclass 38, count 0 2006.285.14:23:31.50#ibcon#enter sib2, iclass 38, count 0 2006.285.14:23:31.50#ibcon#flushed, iclass 38, count 0 2006.285.14:23:31.50#ibcon#about to write, iclass 38, count 0 2006.285.14:23:31.50#ibcon#wrote, iclass 38, count 0 2006.285.14:23:31.50#ibcon#about to read 3, iclass 38, count 0 2006.285.14:23:31.53#ibcon#read 3, iclass 38, count 0 2006.285.14:23:31.53#ibcon#about to read 4, iclass 38, count 0 2006.285.14:23:31.53#ibcon#read 4, iclass 38, count 0 2006.285.14:23:31.53#ibcon#about to read 5, iclass 38, count 0 2006.285.14:23:31.53#ibcon#read 5, iclass 38, count 0 2006.285.14:23:31.53#ibcon#about to read 6, iclass 38, count 0 2006.285.14:23:31.53#ibcon#read 6, iclass 38, count 0 2006.285.14:23:31.53#ibcon#end of sib2, iclass 38, count 0 2006.285.14:23:31.53#ibcon#*after write, iclass 38, count 0 2006.285.14:23:31.53#ibcon#*before return 0, iclass 38, count 0 2006.285.14:23:31.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:23:31.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:23:31.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.14:23:31.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.14:23:31.53$vck44/valo=3,564.99 2006.285.14:23:31.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.14:23:31.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.14:23:31.53#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:31.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:23:31.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:23:31.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:23:31.53#ibcon#enter wrdev, iclass 5, count 0 2006.285.14:23:31.53#ibcon#first serial, iclass 5, count 0 2006.285.14:23:31.53#ibcon#enter sib2, iclass 5, count 0 2006.285.14:23:31.53#ibcon#flushed, iclass 5, count 0 2006.285.14:23:31.53#ibcon#about to write, iclass 5, count 0 2006.285.14:23:31.53#ibcon#wrote, iclass 5, count 0 2006.285.14:23:31.53#ibcon#about to read 3, iclass 5, count 0 2006.285.14:23:31.55#ibcon#read 3, iclass 5, count 0 2006.285.14:23:31.55#ibcon#about to read 4, iclass 5, count 0 2006.285.14:23:31.55#ibcon#read 4, iclass 5, count 0 2006.285.14:23:31.55#ibcon#about to read 5, iclass 5, count 0 2006.285.14:23:31.55#ibcon#read 5, iclass 5, count 0 2006.285.14:23:31.55#ibcon#about to read 6, iclass 5, count 0 2006.285.14:23:31.55#ibcon#read 6, iclass 5, count 0 2006.285.14:23:31.55#ibcon#end of sib2, iclass 5, count 0 2006.285.14:23:31.55#ibcon#*mode == 0, iclass 5, count 0 2006.285.14:23:31.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.14:23:31.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.14:23:31.55#ibcon#*before write, iclass 5, count 0 2006.285.14:23:31.55#ibcon#enter sib2, iclass 5, count 0 2006.285.14:23:31.55#ibcon#flushed, iclass 5, count 0 2006.285.14:23:31.55#ibcon#about to write, iclass 5, count 0 2006.285.14:23:31.55#ibcon#wrote, iclass 5, count 0 2006.285.14:23:31.55#ibcon#about to read 3, iclass 5, count 0 2006.285.14:23:31.59#ibcon#read 3, iclass 5, count 0 2006.285.14:23:31.59#ibcon#about to read 4, iclass 5, count 0 2006.285.14:23:31.59#ibcon#read 4, iclass 5, count 0 2006.285.14:23:31.59#ibcon#about to read 5, iclass 5, count 0 2006.285.14:23:31.59#ibcon#read 5, iclass 5, count 0 2006.285.14:23:31.59#ibcon#about to read 6, iclass 5, count 0 2006.285.14:23:31.59#ibcon#read 6, iclass 5, count 0 2006.285.14:23:31.59#ibcon#end of sib2, iclass 5, count 0 2006.285.14:23:31.59#ibcon#*after write, iclass 5, count 0 2006.285.14:23:31.59#ibcon#*before return 0, iclass 5, count 0 2006.285.14:23:31.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:23:31.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:23:31.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.14:23:31.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.14:23:31.59$vck44/va=3,7 2006.285.14:23:31.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.14:23:31.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.14:23:31.59#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:31.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:23:31.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:23:31.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:23:31.65#ibcon#enter wrdev, iclass 7, count 2 2006.285.14:23:31.65#ibcon#first serial, iclass 7, count 2 2006.285.14:23:31.65#ibcon#enter sib2, iclass 7, count 2 2006.285.14:23:31.65#ibcon#flushed, iclass 7, count 2 2006.285.14:23:31.65#ibcon#about to write, iclass 7, count 2 2006.285.14:23:31.65#ibcon#wrote, iclass 7, count 2 2006.285.14:23:31.65#ibcon#about to read 3, iclass 7, count 2 2006.285.14:23:31.67#ibcon#read 3, iclass 7, count 2 2006.285.14:23:31.67#ibcon#about to read 4, iclass 7, count 2 2006.285.14:23:31.67#ibcon#read 4, iclass 7, count 2 2006.285.14:23:31.67#ibcon#about to read 5, iclass 7, count 2 2006.285.14:23:31.67#ibcon#read 5, iclass 7, count 2 2006.285.14:23:31.67#ibcon#about to read 6, iclass 7, count 2 2006.285.14:23:31.67#ibcon#read 6, iclass 7, count 2 2006.285.14:23:31.67#ibcon#end of sib2, iclass 7, count 2 2006.285.14:23:31.67#ibcon#*mode == 0, iclass 7, count 2 2006.285.14:23:31.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.14:23:31.67#ibcon#[25=AT03-07\r\n] 2006.285.14:23:31.67#ibcon#*before write, iclass 7, count 2 2006.285.14:23:31.67#ibcon#enter sib2, iclass 7, count 2 2006.285.14:23:31.67#ibcon#flushed, iclass 7, count 2 2006.285.14:23:31.67#ibcon#about to write, iclass 7, count 2 2006.285.14:23:31.67#ibcon#wrote, iclass 7, count 2 2006.285.14:23:31.67#ibcon#about to read 3, iclass 7, count 2 2006.285.14:23:31.70#ibcon#read 3, iclass 7, count 2 2006.285.14:23:31.70#ibcon#about to read 4, iclass 7, count 2 2006.285.14:23:31.70#ibcon#read 4, iclass 7, count 2 2006.285.14:23:31.70#ibcon#about to read 5, iclass 7, count 2 2006.285.14:23:31.70#ibcon#read 5, iclass 7, count 2 2006.285.14:23:31.70#ibcon#about to read 6, iclass 7, count 2 2006.285.14:23:31.70#ibcon#read 6, iclass 7, count 2 2006.285.14:23:31.70#ibcon#end of sib2, iclass 7, count 2 2006.285.14:23:31.70#ibcon#*after write, iclass 7, count 2 2006.285.14:23:31.70#ibcon#*before return 0, iclass 7, count 2 2006.285.14:23:31.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:23:31.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:23:31.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.14:23:31.70#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:31.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:23:31.82#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:23:31.82#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:23:31.82#ibcon#enter wrdev, iclass 7, count 0 2006.285.14:23:31.82#ibcon#first serial, iclass 7, count 0 2006.285.14:23:31.82#ibcon#enter sib2, iclass 7, count 0 2006.285.14:23:31.82#ibcon#flushed, iclass 7, count 0 2006.285.14:23:31.82#ibcon#about to write, iclass 7, count 0 2006.285.14:23:31.82#ibcon#wrote, iclass 7, count 0 2006.285.14:23:31.82#ibcon#about to read 3, iclass 7, count 0 2006.285.14:23:31.84#ibcon#read 3, iclass 7, count 0 2006.285.14:23:31.84#ibcon#about to read 4, iclass 7, count 0 2006.285.14:23:31.84#ibcon#read 4, iclass 7, count 0 2006.285.14:23:31.84#ibcon#about to read 5, iclass 7, count 0 2006.285.14:23:31.84#ibcon#read 5, iclass 7, count 0 2006.285.14:23:31.84#ibcon#about to read 6, iclass 7, count 0 2006.285.14:23:31.84#ibcon#read 6, iclass 7, count 0 2006.285.14:23:31.84#ibcon#end of sib2, iclass 7, count 0 2006.285.14:23:31.84#ibcon#*mode == 0, iclass 7, count 0 2006.285.14:23:31.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.14:23:31.84#ibcon#[25=USB\r\n] 2006.285.14:23:31.84#ibcon#*before write, iclass 7, count 0 2006.285.14:23:31.84#ibcon#enter sib2, iclass 7, count 0 2006.285.14:23:31.84#ibcon#flushed, iclass 7, count 0 2006.285.14:23:31.84#ibcon#about to write, iclass 7, count 0 2006.285.14:23:31.84#ibcon#wrote, iclass 7, count 0 2006.285.14:23:31.84#ibcon#about to read 3, iclass 7, count 0 2006.285.14:23:31.87#ibcon#read 3, iclass 7, count 0 2006.285.14:23:31.87#ibcon#about to read 4, iclass 7, count 0 2006.285.14:23:31.87#ibcon#read 4, iclass 7, count 0 2006.285.14:23:31.87#ibcon#about to read 5, iclass 7, count 0 2006.285.14:23:31.87#ibcon#read 5, iclass 7, count 0 2006.285.14:23:31.87#ibcon#about to read 6, iclass 7, count 0 2006.285.14:23:31.87#ibcon#read 6, iclass 7, count 0 2006.285.14:23:31.87#ibcon#end of sib2, iclass 7, count 0 2006.285.14:23:31.87#ibcon#*after write, iclass 7, count 0 2006.285.14:23:31.87#ibcon#*before return 0, iclass 7, count 0 2006.285.14:23:31.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:23:31.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:23:31.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.14:23:31.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.14:23:31.87$vck44/valo=4,624.99 2006.285.14:23:31.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.14:23:31.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.14:23:31.87#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:31.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:23:31.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:23:31.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:23:31.87#ibcon#enter wrdev, iclass 11, count 0 2006.285.14:23:31.87#ibcon#first serial, iclass 11, count 0 2006.285.14:23:31.87#ibcon#enter sib2, iclass 11, count 0 2006.285.14:23:31.87#ibcon#flushed, iclass 11, count 0 2006.285.14:23:31.87#ibcon#about to write, iclass 11, count 0 2006.285.14:23:31.87#ibcon#wrote, iclass 11, count 0 2006.285.14:23:31.87#ibcon#about to read 3, iclass 11, count 0 2006.285.14:23:31.89#ibcon#read 3, iclass 11, count 0 2006.285.14:23:32.41#ibcon#about to read 4, iclass 11, count 0 2006.285.14:23:32.41#ibcon#read 4, iclass 11, count 0 2006.285.14:23:32.41#ibcon#about to read 5, iclass 11, count 0 2006.285.14:23:32.41#ibcon#read 5, iclass 11, count 0 2006.285.14:23:32.41#ibcon#about to read 6, iclass 11, count 0 2006.285.14:23:32.41#ibcon#read 6, iclass 11, count 0 2006.285.14:23:32.41#ibcon#end of sib2, iclass 11, count 0 2006.285.14:23:32.41#ibcon#*mode == 0, iclass 11, count 0 2006.285.14:23:32.41#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.14:23:32.41#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.14:23:32.41#ibcon#*before write, iclass 11, count 0 2006.285.14:23:32.41#ibcon#enter sib2, iclass 11, count 0 2006.285.14:23:32.41#ibcon#flushed, iclass 11, count 0 2006.285.14:23:32.41#ibcon#about to write, iclass 11, count 0 2006.285.14:23:32.41#ibcon#wrote, iclass 11, count 0 2006.285.14:23:32.41#ibcon#about to read 3, iclass 11, count 0 2006.285.14:23:32.45#ibcon#read 3, iclass 11, count 0 2006.285.14:23:32.45#ibcon#about to read 4, iclass 11, count 0 2006.285.14:23:32.45#ibcon#read 4, iclass 11, count 0 2006.285.14:23:32.45#ibcon#about to read 5, iclass 11, count 0 2006.285.14:23:32.45#ibcon#read 5, iclass 11, count 0 2006.285.14:23:32.45#ibcon#about to read 6, iclass 11, count 0 2006.285.14:23:32.45#ibcon#read 6, iclass 11, count 0 2006.285.14:23:32.45#ibcon#end of sib2, iclass 11, count 0 2006.285.14:23:32.45#ibcon#*after write, iclass 11, count 0 2006.285.14:23:32.45#ibcon#*before return 0, iclass 11, count 0 2006.285.14:23:32.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:23:32.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:23:32.45#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.14:23:32.45#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.14:23:32.45$vck44/va=4,6 2006.285.14:23:32.45#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.14:23:32.45#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.14:23:32.45#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:32.45#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:23:32.45#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:23:32.45#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:23:32.45#ibcon#enter wrdev, iclass 13, count 2 2006.285.14:23:32.45#ibcon#first serial, iclass 13, count 2 2006.285.14:23:32.45#ibcon#enter sib2, iclass 13, count 2 2006.285.14:23:32.45#ibcon#flushed, iclass 13, count 2 2006.285.14:23:32.45#ibcon#about to write, iclass 13, count 2 2006.285.14:23:32.45#ibcon#wrote, iclass 13, count 2 2006.285.14:23:32.45#ibcon#about to read 3, iclass 13, count 2 2006.285.14:23:32.47#ibcon#read 3, iclass 13, count 2 2006.285.14:23:32.47#ibcon#about to read 4, iclass 13, count 2 2006.285.14:23:32.47#ibcon#read 4, iclass 13, count 2 2006.285.14:23:32.47#ibcon#about to read 5, iclass 13, count 2 2006.285.14:23:32.47#ibcon#read 5, iclass 13, count 2 2006.285.14:23:32.47#ibcon#about to read 6, iclass 13, count 2 2006.285.14:23:32.47#ibcon#read 6, iclass 13, count 2 2006.285.14:23:32.47#ibcon#end of sib2, iclass 13, count 2 2006.285.14:23:32.47#ibcon#*mode == 0, iclass 13, count 2 2006.285.14:23:32.47#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.14:23:32.47#ibcon#[25=AT04-06\r\n] 2006.285.14:23:32.47#ibcon#*before write, iclass 13, count 2 2006.285.14:23:32.47#ibcon#enter sib2, iclass 13, count 2 2006.285.14:23:32.47#ibcon#flushed, iclass 13, count 2 2006.285.14:23:32.47#ibcon#about to write, iclass 13, count 2 2006.285.14:23:32.47#ibcon#wrote, iclass 13, count 2 2006.285.14:23:32.47#ibcon#about to read 3, iclass 13, count 2 2006.285.14:23:32.50#ibcon#read 3, iclass 13, count 2 2006.285.14:23:32.50#ibcon#about to read 4, iclass 13, count 2 2006.285.14:23:32.50#ibcon#read 4, iclass 13, count 2 2006.285.14:23:32.50#ibcon#about to read 5, iclass 13, count 2 2006.285.14:23:32.50#ibcon#read 5, iclass 13, count 2 2006.285.14:23:32.50#ibcon#about to read 6, iclass 13, count 2 2006.285.14:23:32.50#ibcon#read 6, iclass 13, count 2 2006.285.14:23:32.50#ibcon#end of sib2, iclass 13, count 2 2006.285.14:23:32.50#ibcon#*after write, iclass 13, count 2 2006.285.14:23:32.50#ibcon#*before return 0, iclass 13, count 2 2006.285.14:23:32.50#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:23:32.50#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:23:32.50#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.14:23:32.50#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:32.50#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:23:32.62#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:23:32.62#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:23:32.62#ibcon#enter wrdev, iclass 13, count 0 2006.285.14:23:32.62#ibcon#first serial, iclass 13, count 0 2006.285.14:23:32.62#ibcon#enter sib2, iclass 13, count 0 2006.285.14:23:32.62#ibcon#flushed, iclass 13, count 0 2006.285.14:23:32.62#ibcon#about to write, iclass 13, count 0 2006.285.14:23:32.62#ibcon#wrote, iclass 13, count 0 2006.285.14:23:32.62#ibcon#about to read 3, iclass 13, count 0 2006.285.14:23:32.64#ibcon#read 3, iclass 13, count 0 2006.285.14:23:32.64#ibcon#about to read 4, iclass 13, count 0 2006.285.14:23:32.64#ibcon#read 4, iclass 13, count 0 2006.285.14:23:32.64#ibcon#about to read 5, iclass 13, count 0 2006.285.14:23:32.64#ibcon#read 5, iclass 13, count 0 2006.285.14:23:32.64#ibcon#about to read 6, iclass 13, count 0 2006.285.14:23:32.64#ibcon#read 6, iclass 13, count 0 2006.285.14:23:32.64#ibcon#end of sib2, iclass 13, count 0 2006.285.14:23:32.64#ibcon#*mode == 0, iclass 13, count 0 2006.285.14:23:32.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.14:23:32.64#ibcon#[25=USB\r\n] 2006.285.14:23:32.64#ibcon#*before write, iclass 13, count 0 2006.285.14:23:32.64#ibcon#enter sib2, iclass 13, count 0 2006.285.14:23:32.64#ibcon#flushed, iclass 13, count 0 2006.285.14:23:32.64#ibcon#about to write, iclass 13, count 0 2006.285.14:23:32.64#ibcon#wrote, iclass 13, count 0 2006.285.14:23:32.64#ibcon#about to read 3, iclass 13, count 0 2006.285.14:23:32.67#ibcon#read 3, iclass 13, count 0 2006.285.14:23:32.67#ibcon#about to read 4, iclass 13, count 0 2006.285.14:23:32.67#ibcon#read 4, iclass 13, count 0 2006.285.14:23:32.67#ibcon#about to read 5, iclass 13, count 0 2006.285.14:23:32.67#ibcon#read 5, iclass 13, count 0 2006.285.14:23:32.67#ibcon#about to read 6, iclass 13, count 0 2006.285.14:23:32.67#ibcon#read 6, iclass 13, count 0 2006.285.14:23:32.67#ibcon#end of sib2, iclass 13, count 0 2006.285.14:23:32.67#ibcon#*after write, iclass 13, count 0 2006.285.14:23:32.67#ibcon#*before return 0, iclass 13, count 0 2006.285.14:23:32.67#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:23:32.67#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:23:32.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.14:23:32.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.14:23:32.67$vck44/valo=5,734.99 2006.285.14:23:32.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.14:23:32.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.14:23:32.67#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:32.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:23:32.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:23:32.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:23:32.67#ibcon#enter wrdev, iclass 15, count 0 2006.285.14:23:32.67#ibcon#first serial, iclass 15, count 0 2006.285.14:23:32.67#ibcon#enter sib2, iclass 15, count 0 2006.285.14:23:32.67#ibcon#flushed, iclass 15, count 0 2006.285.14:23:32.67#ibcon#about to write, iclass 15, count 0 2006.285.14:23:32.67#ibcon#wrote, iclass 15, count 0 2006.285.14:23:32.67#ibcon#about to read 3, iclass 15, count 0 2006.285.14:23:32.69#ibcon#read 3, iclass 15, count 0 2006.285.14:23:32.96#ibcon#about to read 4, iclass 15, count 0 2006.285.14:23:32.96#ibcon#read 4, iclass 15, count 0 2006.285.14:23:32.96#ibcon#about to read 5, iclass 15, count 0 2006.285.14:23:32.96#ibcon#read 5, iclass 15, count 0 2006.285.14:23:32.96#ibcon#about to read 6, iclass 15, count 0 2006.285.14:23:32.96#ibcon#read 6, iclass 15, count 0 2006.285.14:23:32.96#ibcon#end of sib2, iclass 15, count 0 2006.285.14:23:32.96#ibcon#*mode == 0, iclass 15, count 0 2006.285.14:23:32.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.14:23:32.96#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.14:23:32.96#ibcon#*before write, iclass 15, count 0 2006.285.14:23:32.96#ibcon#enter sib2, iclass 15, count 0 2006.285.14:23:32.96#ibcon#flushed, iclass 15, count 0 2006.285.14:23:32.96#ibcon#about to write, iclass 15, count 0 2006.285.14:23:32.96#ibcon#wrote, iclass 15, count 0 2006.285.14:23:32.96#ibcon#about to read 3, iclass 15, count 0 2006.285.14:23:33.00#ibcon#read 3, iclass 15, count 0 2006.285.14:23:33.00#ibcon#about to read 4, iclass 15, count 0 2006.285.14:23:33.00#ibcon#read 4, iclass 15, count 0 2006.285.14:23:33.00#ibcon#about to read 5, iclass 15, count 0 2006.285.14:23:33.00#ibcon#read 5, iclass 15, count 0 2006.285.14:23:33.00#ibcon#about to read 6, iclass 15, count 0 2006.285.14:23:33.00#ibcon#read 6, iclass 15, count 0 2006.285.14:23:33.00#ibcon#end of sib2, iclass 15, count 0 2006.285.14:23:33.00#ibcon#*after write, iclass 15, count 0 2006.285.14:23:33.00#ibcon#*before return 0, iclass 15, count 0 2006.285.14:23:33.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:23:33.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:23:33.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.14:23:33.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.14:23:33.00$vck44/va=5,3 2006.285.14:23:33.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.14:23:33.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.14:23:33.00#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:33.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:23:33.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:23:33.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:23:33.00#ibcon#enter wrdev, iclass 17, count 2 2006.285.14:23:33.00#ibcon#first serial, iclass 17, count 2 2006.285.14:23:33.00#ibcon#enter sib2, iclass 17, count 2 2006.285.14:23:33.00#ibcon#flushed, iclass 17, count 2 2006.285.14:23:33.00#ibcon#about to write, iclass 17, count 2 2006.285.14:23:33.00#ibcon#wrote, iclass 17, count 2 2006.285.14:23:33.00#ibcon#about to read 3, iclass 17, count 2 2006.285.14:23:33.02#ibcon#read 3, iclass 17, count 2 2006.285.14:23:33.02#ibcon#about to read 4, iclass 17, count 2 2006.285.14:23:33.02#ibcon#read 4, iclass 17, count 2 2006.285.14:23:33.02#ibcon#about to read 5, iclass 17, count 2 2006.285.14:23:33.02#ibcon#read 5, iclass 17, count 2 2006.285.14:23:33.02#ibcon#about to read 6, iclass 17, count 2 2006.285.14:23:33.02#ibcon#read 6, iclass 17, count 2 2006.285.14:23:33.02#ibcon#end of sib2, iclass 17, count 2 2006.285.14:23:33.02#ibcon#*mode == 0, iclass 17, count 2 2006.285.14:23:33.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.14:23:33.02#ibcon#[25=AT05-03\r\n] 2006.285.14:23:33.02#ibcon#*before write, iclass 17, count 2 2006.285.14:23:33.02#ibcon#enter sib2, iclass 17, count 2 2006.285.14:23:33.02#ibcon#flushed, iclass 17, count 2 2006.285.14:23:33.02#ibcon#about to write, iclass 17, count 2 2006.285.14:23:33.02#ibcon#wrote, iclass 17, count 2 2006.285.14:23:33.02#ibcon#about to read 3, iclass 17, count 2 2006.285.14:23:33.05#ibcon#read 3, iclass 17, count 2 2006.285.14:23:33.05#ibcon#about to read 4, iclass 17, count 2 2006.285.14:23:33.05#ibcon#read 4, iclass 17, count 2 2006.285.14:23:33.05#ibcon#about to read 5, iclass 17, count 2 2006.285.14:23:33.05#ibcon#read 5, iclass 17, count 2 2006.285.14:23:33.05#ibcon#about to read 6, iclass 17, count 2 2006.285.14:23:33.05#ibcon#read 6, iclass 17, count 2 2006.285.14:23:33.05#ibcon#end of sib2, iclass 17, count 2 2006.285.14:23:33.05#ibcon#*after write, iclass 17, count 2 2006.285.14:23:33.05#ibcon#*before return 0, iclass 17, count 2 2006.285.14:23:33.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:23:33.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:23:33.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.14:23:33.05#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:33.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:23:33.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:23:33.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:23:33.17#ibcon#enter wrdev, iclass 17, count 0 2006.285.14:23:33.17#ibcon#first serial, iclass 17, count 0 2006.285.14:23:33.17#ibcon#enter sib2, iclass 17, count 0 2006.285.14:23:33.17#ibcon#flushed, iclass 17, count 0 2006.285.14:23:33.17#ibcon#about to write, iclass 17, count 0 2006.285.14:23:33.17#ibcon#wrote, iclass 17, count 0 2006.285.14:23:33.17#ibcon#about to read 3, iclass 17, count 0 2006.285.14:23:33.19#ibcon#read 3, iclass 17, count 0 2006.285.14:23:33.19#ibcon#about to read 4, iclass 17, count 0 2006.285.14:23:33.19#ibcon#read 4, iclass 17, count 0 2006.285.14:23:33.19#ibcon#about to read 5, iclass 17, count 0 2006.285.14:23:33.19#ibcon#read 5, iclass 17, count 0 2006.285.14:23:33.19#ibcon#about to read 6, iclass 17, count 0 2006.285.14:23:33.19#ibcon#read 6, iclass 17, count 0 2006.285.14:23:33.19#ibcon#end of sib2, iclass 17, count 0 2006.285.14:23:33.19#ibcon#*mode == 0, iclass 17, count 0 2006.285.14:23:33.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.14:23:33.19#ibcon#[25=USB\r\n] 2006.285.14:23:33.19#ibcon#*before write, iclass 17, count 0 2006.285.14:23:33.19#ibcon#enter sib2, iclass 17, count 0 2006.285.14:23:33.19#ibcon#flushed, iclass 17, count 0 2006.285.14:23:33.19#ibcon#about to write, iclass 17, count 0 2006.285.14:23:33.19#ibcon#wrote, iclass 17, count 0 2006.285.14:23:33.19#ibcon#about to read 3, iclass 17, count 0 2006.285.14:23:33.22#ibcon#read 3, iclass 17, count 0 2006.285.14:23:33.22#ibcon#about to read 4, iclass 17, count 0 2006.285.14:23:33.22#ibcon#read 4, iclass 17, count 0 2006.285.14:23:33.22#ibcon#about to read 5, iclass 17, count 0 2006.285.14:23:33.22#ibcon#read 5, iclass 17, count 0 2006.285.14:23:33.22#ibcon#about to read 6, iclass 17, count 0 2006.285.14:23:33.22#ibcon#read 6, iclass 17, count 0 2006.285.14:23:33.22#ibcon#end of sib2, iclass 17, count 0 2006.285.14:23:33.22#ibcon#*after write, iclass 17, count 0 2006.285.14:23:33.22#ibcon#*before return 0, iclass 17, count 0 2006.285.14:23:33.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:23:33.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:23:33.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.14:23:33.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.14:23:33.22$vck44/valo=6,814.99 2006.285.14:23:33.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.14:23:33.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.14:23:33.22#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:33.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:23:33.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:23:33.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:23:33.22#ibcon#enter wrdev, iclass 19, count 0 2006.285.14:23:33.22#ibcon#first serial, iclass 19, count 0 2006.285.14:23:33.22#ibcon#enter sib2, iclass 19, count 0 2006.285.14:23:33.22#ibcon#flushed, iclass 19, count 0 2006.285.14:23:33.22#ibcon#about to write, iclass 19, count 0 2006.285.14:23:33.22#ibcon#wrote, iclass 19, count 0 2006.285.14:23:33.22#ibcon#about to read 3, iclass 19, count 0 2006.285.14:23:33.24#ibcon#read 3, iclass 19, count 0 2006.285.14:23:33.24#ibcon#about to read 4, iclass 19, count 0 2006.285.14:23:33.24#ibcon#read 4, iclass 19, count 0 2006.285.14:23:33.24#ibcon#about to read 5, iclass 19, count 0 2006.285.14:23:33.24#ibcon#read 5, iclass 19, count 0 2006.285.14:23:33.24#ibcon#about to read 6, iclass 19, count 0 2006.285.14:23:33.24#ibcon#read 6, iclass 19, count 0 2006.285.14:23:33.24#ibcon#end of sib2, iclass 19, count 0 2006.285.14:23:33.24#ibcon#*mode == 0, iclass 19, count 0 2006.285.14:23:33.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.14:23:33.24#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.14:23:33.24#ibcon#*before write, iclass 19, count 0 2006.285.14:23:33.24#ibcon#enter sib2, iclass 19, count 0 2006.285.14:23:33.24#ibcon#flushed, iclass 19, count 0 2006.285.14:23:33.24#ibcon#about to write, iclass 19, count 0 2006.285.14:23:33.24#ibcon#wrote, iclass 19, count 0 2006.285.14:23:33.24#ibcon#about to read 3, iclass 19, count 0 2006.285.14:23:33.28#ibcon#read 3, iclass 19, count 0 2006.285.14:23:33.28#ibcon#about to read 4, iclass 19, count 0 2006.285.14:23:33.28#ibcon#read 4, iclass 19, count 0 2006.285.14:23:33.28#ibcon#about to read 5, iclass 19, count 0 2006.285.14:23:33.28#ibcon#read 5, iclass 19, count 0 2006.285.14:23:33.28#ibcon#about to read 6, iclass 19, count 0 2006.285.14:23:33.28#ibcon#read 6, iclass 19, count 0 2006.285.14:23:33.28#ibcon#end of sib2, iclass 19, count 0 2006.285.14:23:33.28#ibcon#*after write, iclass 19, count 0 2006.285.14:23:33.28#ibcon#*before return 0, iclass 19, count 0 2006.285.14:23:33.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:23:33.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:23:33.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.14:23:33.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.14:23:33.28$vck44/va=6,4 2006.285.14:23:33.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.14:23:33.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.14:23:33.28#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:33.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:23:33.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:23:33.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:23:33.34#ibcon#enter wrdev, iclass 21, count 2 2006.285.14:23:33.34#ibcon#first serial, iclass 21, count 2 2006.285.14:23:33.34#ibcon#enter sib2, iclass 21, count 2 2006.285.14:23:33.34#ibcon#flushed, iclass 21, count 2 2006.285.14:23:33.34#ibcon#about to write, iclass 21, count 2 2006.285.14:23:33.34#ibcon#wrote, iclass 21, count 2 2006.285.14:23:33.34#ibcon#about to read 3, iclass 21, count 2 2006.285.14:23:33.36#ibcon#read 3, iclass 21, count 2 2006.285.14:23:33.36#ibcon#about to read 4, iclass 21, count 2 2006.285.14:23:33.36#ibcon#read 4, iclass 21, count 2 2006.285.14:23:33.36#ibcon#about to read 5, iclass 21, count 2 2006.285.14:23:33.36#ibcon#read 5, iclass 21, count 2 2006.285.14:23:33.36#ibcon#about to read 6, iclass 21, count 2 2006.285.14:23:33.36#ibcon#read 6, iclass 21, count 2 2006.285.14:23:33.36#ibcon#end of sib2, iclass 21, count 2 2006.285.14:23:33.36#ibcon#*mode == 0, iclass 21, count 2 2006.285.14:23:33.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.14:23:33.36#ibcon#[25=AT06-04\r\n] 2006.285.14:23:33.36#ibcon#*before write, iclass 21, count 2 2006.285.14:23:33.36#ibcon#enter sib2, iclass 21, count 2 2006.285.14:23:33.36#ibcon#flushed, iclass 21, count 2 2006.285.14:23:33.36#ibcon#about to write, iclass 21, count 2 2006.285.14:23:33.36#ibcon#wrote, iclass 21, count 2 2006.285.14:23:33.36#ibcon#about to read 3, iclass 21, count 2 2006.285.14:23:33.39#ibcon#read 3, iclass 21, count 2 2006.285.14:23:33.39#ibcon#about to read 4, iclass 21, count 2 2006.285.14:23:33.39#ibcon#read 4, iclass 21, count 2 2006.285.14:23:33.39#ibcon#about to read 5, iclass 21, count 2 2006.285.14:23:33.39#ibcon#read 5, iclass 21, count 2 2006.285.14:23:33.39#ibcon#about to read 6, iclass 21, count 2 2006.285.14:23:33.39#ibcon#read 6, iclass 21, count 2 2006.285.14:23:33.39#ibcon#end of sib2, iclass 21, count 2 2006.285.14:23:33.39#ibcon#*after write, iclass 21, count 2 2006.285.14:23:33.39#ibcon#*before return 0, iclass 21, count 2 2006.285.14:23:33.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:23:33.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:23:33.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.14:23:33.39#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:33.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:23:33.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:23:33.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:23:33.51#ibcon#enter wrdev, iclass 21, count 0 2006.285.14:23:33.51#ibcon#first serial, iclass 21, count 0 2006.285.14:23:33.51#ibcon#enter sib2, iclass 21, count 0 2006.285.14:23:33.51#ibcon#flushed, iclass 21, count 0 2006.285.14:23:33.51#ibcon#about to write, iclass 21, count 0 2006.285.14:23:33.51#ibcon#wrote, iclass 21, count 0 2006.285.14:23:33.51#ibcon#about to read 3, iclass 21, count 0 2006.285.14:23:33.53#ibcon#read 3, iclass 21, count 0 2006.285.14:23:33.53#ibcon#about to read 4, iclass 21, count 0 2006.285.14:23:33.53#ibcon#read 4, iclass 21, count 0 2006.285.14:23:33.53#ibcon#about to read 5, iclass 21, count 0 2006.285.14:23:33.53#ibcon#read 5, iclass 21, count 0 2006.285.14:23:33.53#ibcon#about to read 6, iclass 21, count 0 2006.285.14:23:33.53#ibcon#read 6, iclass 21, count 0 2006.285.14:23:33.53#ibcon#end of sib2, iclass 21, count 0 2006.285.14:23:33.53#ibcon#*mode == 0, iclass 21, count 0 2006.285.14:23:33.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.14:23:33.53#ibcon#[25=USB\r\n] 2006.285.14:23:33.53#ibcon#*before write, iclass 21, count 0 2006.285.14:23:33.53#ibcon#enter sib2, iclass 21, count 0 2006.285.14:23:33.53#ibcon#flushed, iclass 21, count 0 2006.285.14:23:33.53#ibcon#about to write, iclass 21, count 0 2006.285.14:23:33.53#ibcon#wrote, iclass 21, count 0 2006.285.14:23:33.53#ibcon#about to read 3, iclass 21, count 0 2006.285.14:23:33.56#ibcon#read 3, iclass 21, count 0 2006.285.14:23:33.56#ibcon#about to read 4, iclass 21, count 0 2006.285.14:23:33.56#ibcon#read 4, iclass 21, count 0 2006.285.14:23:33.56#ibcon#about to read 5, iclass 21, count 0 2006.285.14:23:33.56#ibcon#read 5, iclass 21, count 0 2006.285.14:23:33.56#ibcon#about to read 6, iclass 21, count 0 2006.285.14:23:33.56#ibcon#read 6, iclass 21, count 0 2006.285.14:23:33.56#ibcon#end of sib2, iclass 21, count 0 2006.285.14:23:33.56#ibcon#*after write, iclass 21, count 0 2006.285.14:23:33.56#ibcon#*before return 0, iclass 21, count 0 2006.285.14:23:33.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:23:33.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:23:33.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.14:23:33.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.14:23:33.56$vck44/valo=7,864.99 2006.285.14:23:33.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.14:23:33.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.14:23:33.56#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:33.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:23:33.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:23:33.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:23:33.56#ibcon#enter wrdev, iclass 23, count 0 2006.285.14:23:33.56#ibcon#first serial, iclass 23, count 0 2006.285.14:23:33.56#ibcon#enter sib2, iclass 23, count 0 2006.285.14:23:33.56#ibcon#flushed, iclass 23, count 0 2006.285.14:23:33.56#ibcon#about to write, iclass 23, count 0 2006.285.14:23:33.56#ibcon#wrote, iclass 23, count 0 2006.285.14:23:33.56#ibcon#about to read 3, iclass 23, count 0 2006.285.14:23:33.58#ibcon#read 3, iclass 23, count 0 2006.285.14:23:33.58#ibcon#about to read 4, iclass 23, count 0 2006.285.14:23:33.58#ibcon#read 4, iclass 23, count 0 2006.285.14:23:33.58#ibcon#about to read 5, iclass 23, count 0 2006.285.14:23:33.58#ibcon#read 5, iclass 23, count 0 2006.285.14:23:33.58#ibcon#about to read 6, iclass 23, count 0 2006.285.14:23:33.58#ibcon#read 6, iclass 23, count 0 2006.285.14:23:33.58#ibcon#end of sib2, iclass 23, count 0 2006.285.14:23:33.58#ibcon#*mode == 0, iclass 23, count 0 2006.285.14:23:33.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.14:23:33.58#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.14:23:33.58#ibcon#*before write, iclass 23, count 0 2006.285.14:23:33.58#ibcon#enter sib2, iclass 23, count 0 2006.285.14:23:33.58#ibcon#flushed, iclass 23, count 0 2006.285.14:23:33.58#ibcon#about to write, iclass 23, count 0 2006.285.14:23:33.58#ibcon#wrote, iclass 23, count 0 2006.285.14:23:33.58#ibcon#about to read 3, iclass 23, count 0 2006.285.14:23:33.62#ibcon#read 3, iclass 23, count 0 2006.285.14:23:33.62#ibcon#about to read 4, iclass 23, count 0 2006.285.14:23:33.62#ibcon#read 4, iclass 23, count 0 2006.285.14:23:33.62#ibcon#about to read 5, iclass 23, count 0 2006.285.14:23:33.62#ibcon#read 5, iclass 23, count 0 2006.285.14:23:33.62#ibcon#about to read 6, iclass 23, count 0 2006.285.14:23:33.62#ibcon#read 6, iclass 23, count 0 2006.285.14:23:33.62#ibcon#end of sib2, iclass 23, count 0 2006.285.14:23:33.62#ibcon#*after write, iclass 23, count 0 2006.285.14:23:33.62#ibcon#*before return 0, iclass 23, count 0 2006.285.14:23:33.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:23:33.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:23:33.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.14:23:33.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.14:23:33.62$vck44/va=7,4 2006.285.14:23:33.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.14:23:33.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.14:23:33.62#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:33.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:23:33.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:23:33.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:23:33.68#ibcon#enter wrdev, iclass 25, count 2 2006.285.14:23:33.68#ibcon#first serial, iclass 25, count 2 2006.285.14:23:33.68#ibcon#enter sib2, iclass 25, count 2 2006.285.14:23:33.68#ibcon#flushed, iclass 25, count 2 2006.285.14:23:33.68#ibcon#about to write, iclass 25, count 2 2006.285.14:23:33.68#ibcon#wrote, iclass 25, count 2 2006.285.14:23:33.68#ibcon#about to read 3, iclass 25, count 2 2006.285.14:23:33.70#ibcon#read 3, iclass 25, count 2 2006.285.14:23:33.70#ibcon#about to read 4, iclass 25, count 2 2006.285.14:23:33.70#ibcon#read 4, iclass 25, count 2 2006.285.14:23:33.70#ibcon#about to read 5, iclass 25, count 2 2006.285.14:23:33.70#ibcon#read 5, iclass 25, count 2 2006.285.14:23:33.70#ibcon#about to read 6, iclass 25, count 2 2006.285.14:23:33.70#ibcon#read 6, iclass 25, count 2 2006.285.14:23:33.70#ibcon#end of sib2, iclass 25, count 2 2006.285.14:23:33.70#ibcon#*mode == 0, iclass 25, count 2 2006.285.14:23:33.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.14:23:33.70#ibcon#[25=AT07-04\r\n] 2006.285.14:23:33.70#ibcon#*before write, iclass 25, count 2 2006.285.14:23:33.70#ibcon#enter sib2, iclass 25, count 2 2006.285.14:23:33.70#ibcon#flushed, iclass 25, count 2 2006.285.14:23:33.70#ibcon#about to write, iclass 25, count 2 2006.285.14:23:33.70#ibcon#wrote, iclass 25, count 2 2006.285.14:23:33.70#ibcon#about to read 3, iclass 25, count 2 2006.285.14:23:33.73#ibcon#read 3, iclass 25, count 2 2006.285.14:23:33.73#ibcon#about to read 4, iclass 25, count 2 2006.285.14:23:33.73#ibcon#read 4, iclass 25, count 2 2006.285.14:23:33.73#ibcon#about to read 5, iclass 25, count 2 2006.285.14:23:33.73#ibcon#read 5, iclass 25, count 2 2006.285.14:23:33.73#ibcon#about to read 6, iclass 25, count 2 2006.285.14:23:33.73#ibcon#read 6, iclass 25, count 2 2006.285.14:23:33.73#ibcon#end of sib2, iclass 25, count 2 2006.285.14:23:33.73#ibcon#*after write, iclass 25, count 2 2006.285.14:23:33.73#ibcon#*before return 0, iclass 25, count 2 2006.285.14:23:33.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:23:33.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:23:33.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.14:23:33.73#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:33.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:23:33.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:23:33.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:23:33.85#ibcon#enter wrdev, iclass 25, count 0 2006.285.14:23:33.85#ibcon#first serial, iclass 25, count 0 2006.285.14:23:33.85#ibcon#enter sib2, iclass 25, count 0 2006.285.14:23:33.85#ibcon#flushed, iclass 25, count 0 2006.285.14:23:33.85#ibcon#about to write, iclass 25, count 0 2006.285.14:23:33.85#ibcon#wrote, iclass 25, count 0 2006.285.14:23:33.85#ibcon#about to read 3, iclass 25, count 0 2006.285.14:23:33.87#ibcon#read 3, iclass 25, count 0 2006.285.14:23:33.87#ibcon#about to read 4, iclass 25, count 0 2006.285.14:23:33.87#ibcon#read 4, iclass 25, count 0 2006.285.14:23:33.87#ibcon#about to read 5, iclass 25, count 0 2006.285.14:23:33.87#ibcon#read 5, iclass 25, count 0 2006.285.14:23:33.87#ibcon#about to read 6, iclass 25, count 0 2006.285.14:23:33.87#ibcon#read 6, iclass 25, count 0 2006.285.14:23:33.87#ibcon#end of sib2, iclass 25, count 0 2006.285.14:23:33.87#ibcon#*mode == 0, iclass 25, count 0 2006.285.14:23:33.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.14:23:33.87#ibcon#[25=USB\r\n] 2006.285.14:23:33.87#ibcon#*before write, iclass 25, count 0 2006.285.14:23:33.87#ibcon#enter sib2, iclass 25, count 0 2006.285.14:23:33.87#ibcon#flushed, iclass 25, count 0 2006.285.14:23:33.87#ibcon#about to write, iclass 25, count 0 2006.285.14:23:33.87#ibcon#wrote, iclass 25, count 0 2006.285.14:23:33.87#ibcon#about to read 3, iclass 25, count 0 2006.285.14:23:33.90#ibcon#read 3, iclass 25, count 0 2006.285.14:23:33.90#ibcon#about to read 4, iclass 25, count 0 2006.285.14:23:33.90#ibcon#read 4, iclass 25, count 0 2006.285.14:23:33.90#ibcon#about to read 5, iclass 25, count 0 2006.285.14:23:33.90#ibcon#read 5, iclass 25, count 0 2006.285.14:23:33.90#ibcon#about to read 6, iclass 25, count 0 2006.285.14:23:33.90#ibcon#read 6, iclass 25, count 0 2006.285.14:23:33.90#ibcon#end of sib2, iclass 25, count 0 2006.285.14:23:33.90#ibcon#*after write, iclass 25, count 0 2006.285.14:23:33.90#ibcon#*before return 0, iclass 25, count 0 2006.285.14:23:33.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:23:33.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:23:33.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.14:23:33.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.14:23:33.90$vck44/valo=8,884.99 2006.285.14:23:33.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.14:23:33.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.14:23:33.90#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:33.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:23:33.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:23:33.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:23:33.90#ibcon#enter wrdev, iclass 27, count 0 2006.285.14:23:33.90#ibcon#first serial, iclass 27, count 0 2006.285.14:23:33.90#ibcon#enter sib2, iclass 27, count 0 2006.285.14:23:33.90#ibcon#flushed, iclass 27, count 0 2006.285.14:23:33.90#ibcon#about to write, iclass 27, count 0 2006.285.14:23:33.90#ibcon#wrote, iclass 27, count 0 2006.285.14:23:33.90#ibcon#about to read 3, iclass 27, count 0 2006.285.14:23:33.92#ibcon#read 3, iclass 27, count 0 2006.285.14:23:34.00#ibcon#about to read 4, iclass 27, count 0 2006.285.14:23:34.00#ibcon#read 4, iclass 27, count 0 2006.285.14:23:34.00#ibcon#about to read 5, iclass 27, count 0 2006.285.14:23:34.00#ibcon#read 5, iclass 27, count 0 2006.285.14:23:34.00#ibcon#about to read 6, iclass 27, count 0 2006.285.14:23:34.00#ibcon#read 6, iclass 27, count 0 2006.285.14:23:34.00#ibcon#end of sib2, iclass 27, count 0 2006.285.14:23:34.00#ibcon#*mode == 0, iclass 27, count 0 2006.285.14:23:34.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.14:23:34.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.14:23:34.00#ibcon#*before write, iclass 27, count 0 2006.285.14:23:34.00#ibcon#enter sib2, iclass 27, count 0 2006.285.14:23:34.00#ibcon#flushed, iclass 27, count 0 2006.285.14:23:34.00#ibcon#about to write, iclass 27, count 0 2006.285.14:23:34.00#ibcon#wrote, iclass 27, count 0 2006.285.14:23:34.00#ibcon#about to read 3, iclass 27, count 0 2006.285.14:23:34.04#ibcon#read 3, iclass 27, count 0 2006.285.14:23:34.04#ibcon#about to read 4, iclass 27, count 0 2006.285.14:23:34.04#ibcon#read 4, iclass 27, count 0 2006.285.14:23:34.04#ibcon#about to read 5, iclass 27, count 0 2006.285.14:23:34.04#ibcon#read 5, iclass 27, count 0 2006.285.14:23:34.04#ibcon#about to read 6, iclass 27, count 0 2006.285.14:23:34.04#ibcon#read 6, iclass 27, count 0 2006.285.14:23:34.04#ibcon#end of sib2, iclass 27, count 0 2006.285.14:23:34.04#ibcon#*after write, iclass 27, count 0 2006.285.14:23:34.04#ibcon#*before return 0, iclass 27, count 0 2006.285.14:23:34.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:23:34.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:23:34.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.14:23:34.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.14:23:34.04$vck44/va=8,3 2006.285.14:23:34.04#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.14:23:34.04#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.14:23:34.04#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:34.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:23:34.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:23:34.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:23:34.04#ibcon#enter wrdev, iclass 29, count 2 2006.285.14:23:34.04#ibcon#first serial, iclass 29, count 2 2006.285.14:23:34.04#ibcon#enter sib2, iclass 29, count 2 2006.285.14:23:34.04#ibcon#flushed, iclass 29, count 2 2006.285.14:23:34.04#ibcon#about to write, iclass 29, count 2 2006.285.14:23:34.04#ibcon#wrote, iclass 29, count 2 2006.285.14:23:34.04#ibcon#about to read 3, iclass 29, count 2 2006.285.14:23:34.06#ibcon#read 3, iclass 29, count 2 2006.285.14:23:34.06#ibcon#about to read 4, iclass 29, count 2 2006.285.14:23:34.06#ibcon#read 4, iclass 29, count 2 2006.285.14:23:34.06#ibcon#about to read 5, iclass 29, count 2 2006.285.14:23:34.06#ibcon#read 5, iclass 29, count 2 2006.285.14:23:34.06#ibcon#about to read 6, iclass 29, count 2 2006.285.14:23:34.06#ibcon#read 6, iclass 29, count 2 2006.285.14:23:34.06#ibcon#end of sib2, iclass 29, count 2 2006.285.14:23:34.06#ibcon#*mode == 0, iclass 29, count 2 2006.285.14:23:34.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.14:23:34.06#ibcon#[25=AT08-03\r\n] 2006.285.14:23:34.06#ibcon#*before write, iclass 29, count 2 2006.285.14:23:34.06#ibcon#enter sib2, iclass 29, count 2 2006.285.14:23:34.06#ibcon#flushed, iclass 29, count 2 2006.285.14:23:34.06#ibcon#about to write, iclass 29, count 2 2006.285.14:23:34.06#ibcon#wrote, iclass 29, count 2 2006.285.14:23:34.06#ibcon#about to read 3, iclass 29, count 2 2006.285.14:23:34.09#ibcon#read 3, iclass 29, count 2 2006.285.14:23:34.09#ibcon#about to read 4, iclass 29, count 2 2006.285.14:23:34.09#ibcon#read 4, iclass 29, count 2 2006.285.14:23:34.09#ibcon#about to read 5, iclass 29, count 2 2006.285.14:23:34.09#ibcon#read 5, iclass 29, count 2 2006.285.14:23:34.09#ibcon#about to read 6, iclass 29, count 2 2006.285.14:23:34.09#ibcon#read 6, iclass 29, count 2 2006.285.14:23:34.09#ibcon#end of sib2, iclass 29, count 2 2006.285.14:23:34.09#ibcon#*after write, iclass 29, count 2 2006.285.14:23:34.09#ibcon#*before return 0, iclass 29, count 2 2006.285.14:23:34.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:23:34.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:23:34.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.14:23:34.09#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:34.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:23:34.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:23:34.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:23:34.21#ibcon#enter wrdev, iclass 29, count 0 2006.285.14:23:34.21#ibcon#first serial, iclass 29, count 0 2006.285.14:23:34.21#ibcon#enter sib2, iclass 29, count 0 2006.285.14:23:34.21#ibcon#flushed, iclass 29, count 0 2006.285.14:23:34.21#ibcon#about to write, iclass 29, count 0 2006.285.14:23:34.21#ibcon#wrote, iclass 29, count 0 2006.285.14:23:34.21#ibcon#about to read 3, iclass 29, count 0 2006.285.14:23:34.23#ibcon#read 3, iclass 29, count 0 2006.285.14:23:34.23#ibcon#about to read 4, iclass 29, count 0 2006.285.14:23:34.23#ibcon#read 4, iclass 29, count 0 2006.285.14:23:34.23#ibcon#about to read 5, iclass 29, count 0 2006.285.14:23:34.23#ibcon#read 5, iclass 29, count 0 2006.285.14:23:34.23#ibcon#about to read 6, iclass 29, count 0 2006.285.14:23:34.23#ibcon#read 6, iclass 29, count 0 2006.285.14:23:34.23#ibcon#end of sib2, iclass 29, count 0 2006.285.14:23:34.23#ibcon#*mode == 0, iclass 29, count 0 2006.285.14:23:34.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.14:23:34.23#ibcon#[25=USB\r\n] 2006.285.14:23:34.23#ibcon#*before write, iclass 29, count 0 2006.285.14:23:34.23#ibcon#enter sib2, iclass 29, count 0 2006.285.14:23:34.23#ibcon#flushed, iclass 29, count 0 2006.285.14:23:34.23#ibcon#about to write, iclass 29, count 0 2006.285.14:23:34.23#ibcon#wrote, iclass 29, count 0 2006.285.14:23:34.23#ibcon#about to read 3, iclass 29, count 0 2006.285.14:23:34.26#ibcon#read 3, iclass 29, count 0 2006.285.14:23:34.26#ibcon#about to read 4, iclass 29, count 0 2006.285.14:23:34.26#ibcon#read 4, iclass 29, count 0 2006.285.14:23:34.26#ibcon#about to read 5, iclass 29, count 0 2006.285.14:23:34.26#ibcon#read 5, iclass 29, count 0 2006.285.14:23:34.26#ibcon#about to read 6, iclass 29, count 0 2006.285.14:23:34.26#ibcon#read 6, iclass 29, count 0 2006.285.14:23:34.26#ibcon#end of sib2, iclass 29, count 0 2006.285.14:23:34.26#ibcon#*after write, iclass 29, count 0 2006.285.14:23:34.26#ibcon#*before return 0, iclass 29, count 0 2006.285.14:23:34.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:23:34.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:23:34.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.14:23:34.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.14:23:34.26$vck44/vblo=1,629.99 2006.285.14:23:34.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.14:23:34.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.14:23:34.26#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:34.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:23:34.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:23:34.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:23:34.26#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:23:34.26#ibcon#first serial, iclass 31, count 0 2006.285.14:23:34.26#ibcon#enter sib2, iclass 31, count 0 2006.285.14:23:34.26#ibcon#flushed, iclass 31, count 0 2006.285.14:23:34.26#ibcon#about to write, iclass 31, count 0 2006.285.14:23:34.26#ibcon#wrote, iclass 31, count 0 2006.285.14:23:34.26#ibcon#about to read 3, iclass 31, count 0 2006.285.14:23:34.28#ibcon#read 3, iclass 31, count 0 2006.285.14:23:34.28#ibcon#about to read 4, iclass 31, count 0 2006.285.14:23:34.28#ibcon#read 4, iclass 31, count 0 2006.285.14:23:34.28#ibcon#about to read 5, iclass 31, count 0 2006.285.14:23:34.28#ibcon#read 5, iclass 31, count 0 2006.285.14:23:34.28#ibcon#about to read 6, iclass 31, count 0 2006.285.14:23:34.28#ibcon#read 6, iclass 31, count 0 2006.285.14:23:34.28#ibcon#end of sib2, iclass 31, count 0 2006.285.14:23:34.28#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:23:34.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:23:34.28#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.14:23:34.28#ibcon#*before write, iclass 31, count 0 2006.285.14:23:34.28#ibcon#enter sib2, iclass 31, count 0 2006.285.14:23:34.28#ibcon#flushed, iclass 31, count 0 2006.285.14:23:34.28#ibcon#about to write, iclass 31, count 0 2006.285.14:23:34.28#ibcon#wrote, iclass 31, count 0 2006.285.14:23:34.28#ibcon#about to read 3, iclass 31, count 0 2006.285.14:23:34.32#ibcon#read 3, iclass 31, count 0 2006.285.14:23:34.32#ibcon#about to read 4, iclass 31, count 0 2006.285.14:23:34.32#ibcon#read 4, iclass 31, count 0 2006.285.14:23:34.32#ibcon#about to read 5, iclass 31, count 0 2006.285.14:23:34.32#ibcon#read 5, iclass 31, count 0 2006.285.14:23:34.32#ibcon#about to read 6, iclass 31, count 0 2006.285.14:23:34.32#ibcon#read 6, iclass 31, count 0 2006.285.14:23:34.32#ibcon#end of sib2, iclass 31, count 0 2006.285.14:23:34.32#ibcon#*after write, iclass 31, count 0 2006.285.14:23:34.32#ibcon#*before return 0, iclass 31, count 0 2006.285.14:23:34.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:23:34.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:23:34.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:23:34.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:23:34.32$vck44/vb=1,4 2006.285.14:23:34.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.14:23:34.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.14:23:34.32#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:34.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:23:34.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:23:34.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:23:34.32#ibcon#enter wrdev, iclass 33, count 2 2006.285.14:23:34.32#ibcon#first serial, iclass 33, count 2 2006.285.14:23:34.32#ibcon#enter sib2, iclass 33, count 2 2006.285.14:23:34.32#ibcon#flushed, iclass 33, count 2 2006.285.14:23:34.32#ibcon#about to write, iclass 33, count 2 2006.285.14:23:34.32#ibcon#wrote, iclass 33, count 2 2006.285.14:23:34.32#ibcon#about to read 3, iclass 33, count 2 2006.285.14:23:34.34#ibcon#read 3, iclass 33, count 2 2006.285.14:23:34.34#ibcon#about to read 4, iclass 33, count 2 2006.285.14:23:34.34#ibcon#read 4, iclass 33, count 2 2006.285.14:23:34.34#ibcon#about to read 5, iclass 33, count 2 2006.285.14:23:34.34#ibcon#read 5, iclass 33, count 2 2006.285.14:23:34.34#ibcon#about to read 6, iclass 33, count 2 2006.285.14:23:34.34#ibcon#read 6, iclass 33, count 2 2006.285.14:23:34.34#ibcon#end of sib2, iclass 33, count 2 2006.285.14:23:34.34#ibcon#*mode == 0, iclass 33, count 2 2006.285.14:23:34.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.14:23:34.34#ibcon#[27=AT01-04\r\n] 2006.285.14:23:34.34#ibcon#*before write, iclass 33, count 2 2006.285.14:23:34.34#ibcon#enter sib2, iclass 33, count 2 2006.285.14:23:34.34#ibcon#flushed, iclass 33, count 2 2006.285.14:23:34.34#ibcon#about to write, iclass 33, count 2 2006.285.14:23:34.34#ibcon#wrote, iclass 33, count 2 2006.285.14:23:34.34#ibcon#about to read 3, iclass 33, count 2 2006.285.14:23:34.37#ibcon#read 3, iclass 33, count 2 2006.285.14:23:34.37#ibcon#about to read 4, iclass 33, count 2 2006.285.14:23:34.37#ibcon#read 4, iclass 33, count 2 2006.285.14:23:34.37#ibcon#about to read 5, iclass 33, count 2 2006.285.14:23:34.37#ibcon#read 5, iclass 33, count 2 2006.285.14:23:34.37#ibcon#about to read 6, iclass 33, count 2 2006.285.14:23:34.37#ibcon#read 6, iclass 33, count 2 2006.285.14:23:34.37#ibcon#end of sib2, iclass 33, count 2 2006.285.14:23:34.37#ibcon#*after write, iclass 33, count 2 2006.285.14:23:34.37#ibcon#*before return 0, iclass 33, count 2 2006.285.14:23:34.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:23:34.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:23:34.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.14:23:34.37#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:34.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:23:34.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:23:34.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:23:34.49#ibcon#enter wrdev, iclass 33, count 0 2006.285.14:23:34.49#ibcon#first serial, iclass 33, count 0 2006.285.14:23:34.49#ibcon#enter sib2, iclass 33, count 0 2006.285.14:23:34.49#ibcon#flushed, iclass 33, count 0 2006.285.14:23:34.49#ibcon#about to write, iclass 33, count 0 2006.285.14:23:34.49#ibcon#wrote, iclass 33, count 0 2006.285.14:23:34.49#ibcon#about to read 3, iclass 33, count 0 2006.285.14:23:34.51#ibcon#read 3, iclass 33, count 0 2006.285.14:23:34.51#ibcon#about to read 4, iclass 33, count 0 2006.285.14:23:34.51#ibcon#read 4, iclass 33, count 0 2006.285.14:23:34.51#ibcon#about to read 5, iclass 33, count 0 2006.285.14:23:34.51#ibcon#read 5, iclass 33, count 0 2006.285.14:23:34.51#ibcon#about to read 6, iclass 33, count 0 2006.285.14:23:34.51#ibcon#read 6, iclass 33, count 0 2006.285.14:23:34.51#ibcon#end of sib2, iclass 33, count 0 2006.285.14:23:34.51#ibcon#*mode == 0, iclass 33, count 0 2006.285.14:23:34.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.14:23:34.51#ibcon#[27=USB\r\n] 2006.285.14:23:34.51#ibcon#*before write, iclass 33, count 0 2006.285.14:23:34.51#ibcon#enter sib2, iclass 33, count 0 2006.285.14:23:34.51#ibcon#flushed, iclass 33, count 0 2006.285.14:23:34.51#ibcon#about to write, iclass 33, count 0 2006.285.14:23:34.51#ibcon#wrote, iclass 33, count 0 2006.285.14:23:34.51#ibcon#about to read 3, iclass 33, count 0 2006.285.14:23:34.54#ibcon#read 3, iclass 33, count 0 2006.285.14:23:34.54#ibcon#about to read 4, iclass 33, count 0 2006.285.14:23:34.54#ibcon#read 4, iclass 33, count 0 2006.285.14:23:34.54#ibcon#about to read 5, iclass 33, count 0 2006.285.14:23:34.54#ibcon#read 5, iclass 33, count 0 2006.285.14:23:34.54#ibcon#about to read 6, iclass 33, count 0 2006.285.14:23:34.54#ibcon#read 6, iclass 33, count 0 2006.285.14:23:34.54#ibcon#end of sib2, iclass 33, count 0 2006.285.14:23:34.54#ibcon#*after write, iclass 33, count 0 2006.285.14:23:34.54#ibcon#*before return 0, iclass 33, count 0 2006.285.14:23:34.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:23:34.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:23:34.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.14:23:34.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.14:23:34.54$vck44/vblo=2,634.99 2006.285.14:23:34.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.14:23:34.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.14:23:34.54#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:34.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:23:34.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:23:34.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:23:34.54#ibcon#enter wrdev, iclass 35, count 0 2006.285.14:23:34.54#ibcon#first serial, iclass 35, count 0 2006.285.14:23:34.54#ibcon#enter sib2, iclass 35, count 0 2006.285.14:23:34.54#ibcon#flushed, iclass 35, count 0 2006.285.14:23:34.54#ibcon#about to write, iclass 35, count 0 2006.285.14:23:34.54#ibcon#wrote, iclass 35, count 0 2006.285.14:23:34.54#ibcon#about to read 3, iclass 35, count 0 2006.285.14:23:34.56#ibcon#read 3, iclass 35, count 0 2006.285.14:23:34.56#ibcon#about to read 4, iclass 35, count 0 2006.285.14:23:34.56#ibcon#read 4, iclass 35, count 0 2006.285.14:23:34.56#ibcon#about to read 5, iclass 35, count 0 2006.285.14:23:34.56#ibcon#read 5, iclass 35, count 0 2006.285.14:23:34.56#ibcon#about to read 6, iclass 35, count 0 2006.285.14:23:34.56#ibcon#read 6, iclass 35, count 0 2006.285.14:23:34.56#ibcon#end of sib2, iclass 35, count 0 2006.285.14:23:34.56#ibcon#*mode == 0, iclass 35, count 0 2006.285.14:23:34.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.14:23:34.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.14:23:34.56#ibcon#*before write, iclass 35, count 0 2006.285.14:23:34.56#ibcon#enter sib2, iclass 35, count 0 2006.285.14:23:34.56#ibcon#flushed, iclass 35, count 0 2006.285.14:23:34.56#ibcon#about to write, iclass 35, count 0 2006.285.14:23:34.56#ibcon#wrote, iclass 35, count 0 2006.285.14:23:34.56#ibcon#about to read 3, iclass 35, count 0 2006.285.14:23:34.60#ibcon#read 3, iclass 35, count 0 2006.285.14:23:34.60#ibcon#about to read 4, iclass 35, count 0 2006.285.14:23:34.60#ibcon#read 4, iclass 35, count 0 2006.285.14:23:34.60#ibcon#about to read 5, iclass 35, count 0 2006.285.14:23:34.60#ibcon#read 5, iclass 35, count 0 2006.285.14:23:34.60#ibcon#about to read 6, iclass 35, count 0 2006.285.14:23:34.60#ibcon#read 6, iclass 35, count 0 2006.285.14:23:34.60#ibcon#end of sib2, iclass 35, count 0 2006.285.14:23:34.60#ibcon#*after write, iclass 35, count 0 2006.285.14:23:34.60#ibcon#*before return 0, iclass 35, count 0 2006.285.14:23:34.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:23:34.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:23:34.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.14:23:34.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.14:23:34.60$vck44/vb=2,5 2006.285.14:23:34.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.14:23:34.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.14:23:34.60#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:34.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:23:34.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:23:34.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:23:34.66#ibcon#enter wrdev, iclass 37, count 2 2006.285.14:23:34.66#ibcon#first serial, iclass 37, count 2 2006.285.14:23:34.66#ibcon#enter sib2, iclass 37, count 2 2006.285.14:23:34.66#ibcon#flushed, iclass 37, count 2 2006.285.14:23:34.66#ibcon#about to write, iclass 37, count 2 2006.285.14:23:34.66#ibcon#wrote, iclass 37, count 2 2006.285.14:23:34.66#ibcon#about to read 3, iclass 37, count 2 2006.285.14:23:34.68#ibcon#read 3, iclass 37, count 2 2006.285.14:23:34.68#ibcon#about to read 4, iclass 37, count 2 2006.285.14:23:34.68#ibcon#read 4, iclass 37, count 2 2006.285.14:23:34.68#ibcon#about to read 5, iclass 37, count 2 2006.285.14:23:34.68#ibcon#read 5, iclass 37, count 2 2006.285.14:23:34.68#ibcon#about to read 6, iclass 37, count 2 2006.285.14:23:34.68#ibcon#read 6, iclass 37, count 2 2006.285.14:23:34.68#ibcon#end of sib2, iclass 37, count 2 2006.285.14:23:34.68#ibcon#*mode == 0, iclass 37, count 2 2006.285.14:23:34.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.14:23:34.68#ibcon#[27=AT02-05\r\n] 2006.285.14:23:34.68#ibcon#*before write, iclass 37, count 2 2006.285.14:23:34.68#ibcon#enter sib2, iclass 37, count 2 2006.285.14:23:34.68#ibcon#flushed, iclass 37, count 2 2006.285.14:23:34.68#ibcon#about to write, iclass 37, count 2 2006.285.14:23:34.68#ibcon#wrote, iclass 37, count 2 2006.285.14:23:34.68#ibcon#about to read 3, iclass 37, count 2 2006.285.14:23:34.71#ibcon#read 3, iclass 37, count 2 2006.285.14:23:34.71#ibcon#about to read 4, iclass 37, count 2 2006.285.14:23:34.71#ibcon#read 4, iclass 37, count 2 2006.285.14:23:34.71#ibcon#about to read 5, iclass 37, count 2 2006.285.14:23:34.71#ibcon#read 5, iclass 37, count 2 2006.285.14:23:34.71#ibcon#about to read 6, iclass 37, count 2 2006.285.14:23:34.71#ibcon#read 6, iclass 37, count 2 2006.285.14:23:34.71#ibcon#end of sib2, iclass 37, count 2 2006.285.14:23:34.71#ibcon#*after write, iclass 37, count 2 2006.285.14:23:34.71#ibcon#*before return 0, iclass 37, count 2 2006.285.14:23:34.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:23:34.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:23:34.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.14:23:34.71#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:34.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:23:34.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:23:34.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:23:34.83#ibcon#enter wrdev, iclass 37, count 0 2006.285.14:23:34.83#ibcon#first serial, iclass 37, count 0 2006.285.14:23:34.83#ibcon#enter sib2, iclass 37, count 0 2006.285.14:23:34.83#ibcon#flushed, iclass 37, count 0 2006.285.14:23:34.83#ibcon#about to write, iclass 37, count 0 2006.285.14:23:34.83#ibcon#wrote, iclass 37, count 0 2006.285.14:23:34.83#ibcon#about to read 3, iclass 37, count 0 2006.285.14:23:34.85#ibcon#read 3, iclass 37, count 0 2006.285.14:23:34.85#ibcon#about to read 4, iclass 37, count 0 2006.285.14:23:34.85#ibcon#read 4, iclass 37, count 0 2006.285.14:23:34.85#ibcon#about to read 5, iclass 37, count 0 2006.285.14:23:34.85#ibcon#read 5, iclass 37, count 0 2006.285.14:23:34.85#ibcon#about to read 6, iclass 37, count 0 2006.285.14:23:34.85#ibcon#read 6, iclass 37, count 0 2006.285.14:23:34.85#ibcon#end of sib2, iclass 37, count 0 2006.285.14:23:34.85#ibcon#*mode == 0, iclass 37, count 0 2006.285.14:23:34.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.14:23:34.85#ibcon#[27=USB\r\n] 2006.285.14:23:34.85#ibcon#*before write, iclass 37, count 0 2006.285.14:23:34.85#ibcon#enter sib2, iclass 37, count 0 2006.285.14:23:34.85#ibcon#flushed, iclass 37, count 0 2006.285.14:23:34.85#ibcon#about to write, iclass 37, count 0 2006.285.14:23:34.85#ibcon#wrote, iclass 37, count 0 2006.285.14:23:34.85#ibcon#about to read 3, iclass 37, count 0 2006.285.14:23:34.88#ibcon#read 3, iclass 37, count 0 2006.285.14:23:34.88#ibcon#about to read 4, iclass 37, count 0 2006.285.14:23:34.88#ibcon#read 4, iclass 37, count 0 2006.285.14:23:34.88#ibcon#about to read 5, iclass 37, count 0 2006.285.14:23:34.88#ibcon#read 5, iclass 37, count 0 2006.285.14:23:34.88#ibcon#about to read 6, iclass 37, count 0 2006.285.14:23:34.88#ibcon#read 6, iclass 37, count 0 2006.285.14:23:34.88#ibcon#end of sib2, iclass 37, count 0 2006.285.14:23:34.88#ibcon#*after write, iclass 37, count 0 2006.285.14:23:34.88#ibcon#*before return 0, iclass 37, count 0 2006.285.14:23:34.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:23:34.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:23:34.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.14:23:34.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.14:23:34.88$vck44/vblo=3,649.99 2006.285.14:23:34.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.14:23:34.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.14:23:34.88#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:34.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:23:34.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:23:34.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:23:34.88#ibcon#enter wrdev, iclass 39, count 0 2006.285.14:23:34.88#ibcon#first serial, iclass 39, count 0 2006.285.14:23:34.88#ibcon#enter sib2, iclass 39, count 0 2006.285.14:23:34.88#ibcon#flushed, iclass 39, count 0 2006.285.14:23:34.88#ibcon#about to write, iclass 39, count 0 2006.285.14:23:34.88#ibcon#wrote, iclass 39, count 0 2006.285.14:23:34.88#ibcon#about to read 3, iclass 39, count 0 2006.285.14:23:34.90#ibcon#read 3, iclass 39, count 0 2006.285.14:23:35.03#ibcon#about to read 4, iclass 39, count 0 2006.285.14:23:35.03#ibcon#read 4, iclass 39, count 0 2006.285.14:23:35.03#ibcon#about to read 5, iclass 39, count 0 2006.285.14:23:35.03#ibcon#read 5, iclass 39, count 0 2006.285.14:23:35.03#ibcon#about to read 6, iclass 39, count 0 2006.285.14:23:35.03#ibcon#read 6, iclass 39, count 0 2006.285.14:23:35.03#ibcon#end of sib2, iclass 39, count 0 2006.285.14:23:35.03#ibcon#*mode == 0, iclass 39, count 0 2006.285.14:23:35.03#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.14:23:35.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.14:23:35.03#ibcon#*before write, iclass 39, count 0 2006.285.14:23:35.03#ibcon#enter sib2, iclass 39, count 0 2006.285.14:23:35.03#ibcon#flushed, iclass 39, count 0 2006.285.14:23:35.03#ibcon#about to write, iclass 39, count 0 2006.285.14:23:35.03#ibcon#wrote, iclass 39, count 0 2006.285.14:23:35.03#ibcon#about to read 3, iclass 39, count 0 2006.285.14:23:35.07#ibcon#read 3, iclass 39, count 0 2006.285.14:23:35.07#ibcon#about to read 4, iclass 39, count 0 2006.285.14:23:35.07#ibcon#read 4, iclass 39, count 0 2006.285.14:23:35.07#ibcon#about to read 5, iclass 39, count 0 2006.285.14:23:35.07#ibcon#read 5, iclass 39, count 0 2006.285.14:23:35.07#ibcon#about to read 6, iclass 39, count 0 2006.285.14:23:35.07#ibcon#read 6, iclass 39, count 0 2006.285.14:23:35.07#ibcon#end of sib2, iclass 39, count 0 2006.285.14:23:35.07#ibcon#*after write, iclass 39, count 0 2006.285.14:23:35.07#ibcon#*before return 0, iclass 39, count 0 2006.285.14:23:35.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:23:35.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:23:35.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.14:23:35.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.14:23:35.07$vck44/vb=3,4 2006.285.14:23:35.07#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.14:23:35.07#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.14:23:35.07#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:35.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:23:35.07#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:23:35.07#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:23:35.07#ibcon#enter wrdev, iclass 3, count 2 2006.285.14:23:35.07#ibcon#first serial, iclass 3, count 2 2006.285.14:23:35.07#ibcon#enter sib2, iclass 3, count 2 2006.285.14:23:35.07#ibcon#flushed, iclass 3, count 2 2006.285.14:23:35.07#ibcon#about to write, iclass 3, count 2 2006.285.14:23:35.07#ibcon#wrote, iclass 3, count 2 2006.285.14:23:35.07#ibcon#about to read 3, iclass 3, count 2 2006.285.14:23:35.09#ibcon#read 3, iclass 3, count 2 2006.285.14:23:35.09#ibcon#about to read 4, iclass 3, count 2 2006.285.14:23:35.09#ibcon#read 4, iclass 3, count 2 2006.285.14:23:35.09#ibcon#about to read 5, iclass 3, count 2 2006.285.14:23:35.09#ibcon#read 5, iclass 3, count 2 2006.285.14:23:35.09#ibcon#about to read 6, iclass 3, count 2 2006.285.14:23:35.09#ibcon#read 6, iclass 3, count 2 2006.285.14:23:35.09#ibcon#end of sib2, iclass 3, count 2 2006.285.14:23:35.09#ibcon#*mode == 0, iclass 3, count 2 2006.285.14:23:35.09#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.14:23:35.09#ibcon#[27=AT03-04\r\n] 2006.285.14:23:35.09#ibcon#*before write, iclass 3, count 2 2006.285.14:23:35.09#ibcon#enter sib2, iclass 3, count 2 2006.285.14:23:35.09#ibcon#flushed, iclass 3, count 2 2006.285.14:23:35.09#ibcon#about to write, iclass 3, count 2 2006.285.14:23:35.09#ibcon#wrote, iclass 3, count 2 2006.285.14:23:35.09#ibcon#about to read 3, iclass 3, count 2 2006.285.14:23:35.12#ibcon#read 3, iclass 3, count 2 2006.285.14:23:35.12#ibcon#about to read 4, iclass 3, count 2 2006.285.14:23:35.12#ibcon#read 4, iclass 3, count 2 2006.285.14:23:35.12#ibcon#about to read 5, iclass 3, count 2 2006.285.14:23:35.12#ibcon#read 5, iclass 3, count 2 2006.285.14:23:35.12#ibcon#about to read 6, iclass 3, count 2 2006.285.14:23:35.12#ibcon#read 6, iclass 3, count 2 2006.285.14:23:35.12#ibcon#end of sib2, iclass 3, count 2 2006.285.14:23:35.12#ibcon#*after write, iclass 3, count 2 2006.285.14:23:35.12#ibcon#*before return 0, iclass 3, count 2 2006.285.14:23:35.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:23:35.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:23:35.12#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.14:23:35.12#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:35.12#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:23:35.24#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:23:35.24#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:23:35.24#ibcon#enter wrdev, iclass 3, count 0 2006.285.14:23:35.24#ibcon#first serial, iclass 3, count 0 2006.285.14:23:35.24#ibcon#enter sib2, iclass 3, count 0 2006.285.14:23:35.24#ibcon#flushed, iclass 3, count 0 2006.285.14:23:35.24#ibcon#about to write, iclass 3, count 0 2006.285.14:23:35.24#ibcon#wrote, iclass 3, count 0 2006.285.14:23:35.24#ibcon#about to read 3, iclass 3, count 0 2006.285.14:23:35.26#ibcon#read 3, iclass 3, count 0 2006.285.14:23:35.26#ibcon#about to read 4, iclass 3, count 0 2006.285.14:23:35.26#ibcon#read 4, iclass 3, count 0 2006.285.14:23:35.26#ibcon#about to read 5, iclass 3, count 0 2006.285.14:23:35.26#ibcon#read 5, iclass 3, count 0 2006.285.14:23:35.26#ibcon#about to read 6, iclass 3, count 0 2006.285.14:23:35.26#ibcon#read 6, iclass 3, count 0 2006.285.14:23:35.26#ibcon#end of sib2, iclass 3, count 0 2006.285.14:23:35.26#ibcon#*mode == 0, iclass 3, count 0 2006.285.14:23:35.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.14:23:35.26#ibcon#[27=USB\r\n] 2006.285.14:23:35.26#ibcon#*before write, iclass 3, count 0 2006.285.14:23:35.26#ibcon#enter sib2, iclass 3, count 0 2006.285.14:23:35.26#ibcon#flushed, iclass 3, count 0 2006.285.14:23:35.26#ibcon#about to write, iclass 3, count 0 2006.285.14:23:35.26#ibcon#wrote, iclass 3, count 0 2006.285.14:23:35.26#ibcon#about to read 3, iclass 3, count 0 2006.285.14:23:35.29#ibcon#read 3, iclass 3, count 0 2006.285.14:23:35.29#ibcon#about to read 4, iclass 3, count 0 2006.285.14:23:35.29#ibcon#read 4, iclass 3, count 0 2006.285.14:23:35.29#ibcon#about to read 5, iclass 3, count 0 2006.285.14:23:35.29#ibcon#read 5, iclass 3, count 0 2006.285.14:23:35.29#ibcon#about to read 6, iclass 3, count 0 2006.285.14:23:35.29#ibcon#read 6, iclass 3, count 0 2006.285.14:23:35.29#ibcon#end of sib2, iclass 3, count 0 2006.285.14:23:35.29#ibcon#*after write, iclass 3, count 0 2006.285.14:23:35.29#ibcon#*before return 0, iclass 3, count 0 2006.285.14:23:35.29#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:23:35.29#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:23:35.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.14:23:35.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.14:23:35.29$vck44/vblo=4,679.99 2006.285.14:23:35.29#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.14:23:35.29#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.14:23:35.29#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:35.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:23:35.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:23:35.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:23:35.29#ibcon#enter wrdev, iclass 5, count 0 2006.285.14:23:35.29#ibcon#first serial, iclass 5, count 0 2006.285.14:23:35.29#ibcon#enter sib2, iclass 5, count 0 2006.285.14:23:35.29#ibcon#flushed, iclass 5, count 0 2006.285.14:23:35.29#ibcon#about to write, iclass 5, count 0 2006.285.14:23:35.29#ibcon#wrote, iclass 5, count 0 2006.285.14:23:35.29#ibcon#about to read 3, iclass 5, count 0 2006.285.14:23:35.31#ibcon#read 3, iclass 5, count 0 2006.285.14:23:35.31#ibcon#about to read 4, iclass 5, count 0 2006.285.14:23:35.31#ibcon#read 4, iclass 5, count 0 2006.285.14:23:35.31#ibcon#about to read 5, iclass 5, count 0 2006.285.14:23:35.31#ibcon#read 5, iclass 5, count 0 2006.285.14:23:35.31#ibcon#about to read 6, iclass 5, count 0 2006.285.14:23:35.31#ibcon#read 6, iclass 5, count 0 2006.285.14:23:35.31#ibcon#end of sib2, iclass 5, count 0 2006.285.14:23:35.31#ibcon#*mode == 0, iclass 5, count 0 2006.285.14:23:35.31#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.14:23:35.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.14:23:35.31#ibcon#*before write, iclass 5, count 0 2006.285.14:23:35.31#ibcon#enter sib2, iclass 5, count 0 2006.285.14:23:35.31#ibcon#flushed, iclass 5, count 0 2006.285.14:23:35.31#ibcon#about to write, iclass 5, count 0 2006.285.14:23:35.31#ibcon#wrote, iclass 5, count 0 2006.285.14:23:35.31#ibcon#about to read 3, iclass 5, count 0 2006.285.14:23:35.35#ibcon#read 3, iclass 5, count 0 2006.285.14:23:35.35#ibcon#about to read 4, iclass 5, count 0 2006.285.14:23:35.35#ibcon#read 4, iclass 5, count 0 2006.285.14:23:35.35#ibcon#about to read 5, iclass 5, count 0 2006.285.14:23:35.35#ibcon#read 5, iclass 5, count 0 2006.285.14:23:35.35#ibcon#about to read 6, iclass 5, count 0 2006.285.14:23:35.35#ibcon#read 6, iclass 5, count 0 2006.285.14:23:35.35#ibcon#end of sib2, iclass 5, count 0 2006.285.14:23:35.35#ibcon#*after write, iclass 5, count 0 2006.285.14:23:35.35#ibcon#*before return 0, iclass 5, count 0 2006.285.14:23:35.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:23:35.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:23:35.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.14:23:35.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.14:23:35.35$vck44/vb=4,5 2006.285.14:23:35.35#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.14:23:35.35#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.14:23:35.35#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:35.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:23:35.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:23:35.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:23:35.41#ibcon#enter wrdev, iclass 7, count 2 2006.285.14:23:35.41#ibcon#first serial, iclass 7, count 2 2006.285.14:23:35.41#ibcon#enter sib2, iclass 7, count 2 2006.285.14:23:35.41#ibcon#flushed, iclass 7, count 2 2006.285.14:23:35.41#ibcon#about to write, iclass 7, count 2 2006.285.14:23:35.41#ibcon#wrote, iclass 7, count 2 2006.285.14:23:35.41#ibcon#about to read 3, iclass 7, count 2 2006.285.14:23:35.43#ibcon#read 3, iclass 7, count 2 2006.285.14:23:35.43#ibcon#about to read 4, iclass 7, count 2 2006.285.14:23:35.43#ibcon#read 4, iclass 7, count 2 2006.285.14:23:35.43#ibcon#about to read 5, iclass 7, count 2 2006.285.14:23:35.43#ibcon#read 5, iclass 7, count 2 2006.285.14:23:35.43#ibcon#about to read 6, iclass 7, count 2 2006.285.14:23:35.43#ibcon#read 6, iclass 7, count 2 2006.285.14:23:35.43#ibcon#end of sib2, iclass 7, count 2 2006.285.14:23:35.43#ibcon#*mode == 0, iclass 7, count 2 2006.285.14:23:35.43#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.14:23:35.43#ibcon#[27=AT04-05\r\n] 2006.285.14:23:35.43#ibcon#*before write, iclass 7, count 2 2006.285.14:23:35.43#ibcon#enter sib2, iclass 7, count 2 2006.285.14:23:35.43#ibcon#flushed, iclass 7, count 2 2006.285.14:23:35.43#ibcon#about to write, iclass 7, count 2 2006.285.14:23:35.43#ibcon#wrote, iclass 7, count 2 2006.285.14:23:35.43#ibcon#about to read 3, iclass 7, count 2 2006.285.14:23:35.46#ibcon#read 3, iclass 7, count 2 2006.285.14:23:35.46#ibcon#about to read 4, iclass 7, count 2 2006.285.14:23:35.46#ibcon#read 4, iclass 7, count 2 2006.285.14:23:35.46#ibcon#about to read 5, iclass 7, count 2 2006.285.14:23:35.46#ibcon#read 5, iclass 7, count 2 2006.285.14:23:35.46#ibcon#about to read 6, iclass 7, count 2 2006.285.14:23:35.46#ibcon#read 6, iclass 7, count 2 2006.285.14:23:35.46#ibcon#end of sib2, iclass 7, count 2 2006.285.14:23:35.46#ibcon#*after write, iclass 7, count 2 2006.285.14:23:35.46#ibcon#*before return 0, iclass 7, count 2 2006.285.14:23:35.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:23:35.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:23:35.46#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.14:23:35.46#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:35.46#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:23:35.58#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:23:35.58#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:23:35.58#ibcon#enter wrdev, iclass 7, count 0 2006.285.14:23:35.58#ibcon#first serial, iclass 7, count 0 2006.285.14:23:35.58#ibcon#enter sib2, iclass 7, count 0 2006.285.14:23:35.58#ibcon#flushed, iclass 7, count 0 2006.285.14:23:35.58#ibcon#about to write, iclass 7, count 0 2006.285.14:23:35.58#ibcon#wrote, iclass 7, count 0 2006.285.14:23:35.58#ibcon#about to read 3, iclass 7, count 0 2006.285.14:23:35.60#ibcon#read 3, iclass 7, count 0 2006.285.14:23:35.60#ibcon#about to read 4, iclass 7, count 0 2006.285.14:23:35.60#ibcon#read 4, iclass 7, count 0 2006.285.14:23:35.60#ibcon#about to read 5, iclass 7, count 0 2006.285.14:23:35.60#ibcon#read 5, iclass 7, count 0 2006.285.14:23:35.60#ibcon#about to read 6, iclass 7, count 0 2006.285.14:23:35.60#ibcon#read 6, iclass 7, count 0 2006.285.14:23:35.60#ibcon#end of sib2, iclass 7, count 0 2006.285.14:23:35.60#ibcon#*mode == 0, iclass 7, count 0 2006.285.14:23:35.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.14:23:35.60#ibcon#[27=USB\r\n] 2006.285.14:23:35.60#ibcon#*before write, iclass 7, count 0 2006.285.14:23:35.60#ibcon#enter sib2, iclass 7, count 0 2006.285.14:23:35.60#ibcon#flushed, iclass 7, count 0 2006.285.14:23:35.60#ibcon#about to write, iclass 7, count 0 2006.285.14:23:35.60#ibcon#wrote, iclass 7, count 0 2006.285.14:23:35.60#ibcon#about to read 3, iclass 7, count 0 2006.285.14:23:35.63#ibcon#read 3, iclass 7, count 0 2006.285.14:23:35.63#ibcon#about to read 4, iclass 7, count 0 2006.285.14:23:35.63#ibcon#read 4, iclass 7, count 0 2006.285.14:23:35.63#ibcon#about to read 5, iclass 7, count 0 2006.285.14:23:35.63#ibcon#read 5, iclass 7, count 0 2006.285.14:23:35.63#ibcon#about to read 6, iclass 7, count 0 2006.285.14:23:35.63#ibcon#read 6, iclass 7, count 0 2006.285.14:23:35.63#ibcon#end of sib2, iclass 7, count 0 2006.285.14:23:35.63#ibcon#*after write, iclass 7, count 0 2006.285.14:23:35.63#ibcon#*before return 0, iclass 7, count 0 2006.285.14:23:35.63#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:23:35.63#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:23:35.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.14:23:35.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.14:23:35.63$vck44/vblo=5,709.99 2006.285.14:23:35.63#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.14:23:35.63#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.14:23:35.63#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:35.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:23:35.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:23:35.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:23:35.63#ibcon#enter wrdev, iclass 11, count 0 2006.285.14:23:35.63#ibcon#first serial, iclass 11, count 0 2006.285.14:23:35.63#ibcon#enter sib2, iclass 11, count 0 2006.285.14:23:35.63#ibcon#flushed, iclass 11, count 0 2006.285.14:23:35.63#ibcon#about to write, iclass 11, count 0 2006.285.14:23:35.63#ibcon#wrote, iclass 11, count 0 2006.285.14:23:35.63#ibcon#about to read 3, iclass 11, count 0 2006.285.14:23:35.65#ibcon#read 3, iclass 11, count 0 2006.285.14:23:35.65#ibcon#about to read 4, iclass 11, count 0 2006.285.14:23:35.65#ibcon#read 4, iclass 11, count 0 2006.285.14:23:35.65#ibcon#about to read 5, iclass 11, count 0 2006.285.14:23:35.65#ibcon#read 5, iclass 11, count 0 2006.285.14:23:35.65#ibcon#about to read 6, iclass 11, count 0 2006.285.14:23:35.65#ibcon#read 6, iclass 11, count 0 2006.285.14:23:35.65#ibcon#end of sib2, iclass 11, count 0 2006.285.14:23:35.65#ibcon#*mode == 0, iclass 11, count 0 2006.285.14:23:35.65#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.14:23:35.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.14:23:35.65#ibcon#*before write, iclass 11, count 0 2006.285.14:23:35.65#ibcon#enter sib2, iclass 11, count 0 2006.285.14:23:35.65#ibcon#flushed, iclass 11, count 0 2006.285.14:23:35.65#ibcon#about to write, iclass 11, count 0 2006.285.14:23:35.65#ibcon#wrote, iclass 11, count 0 2006.285.14:23:35.65#ibcon#about to read 3, iclass 11, count 0 2006.285.14:23:35.69#ibcon#read 3, iclass 11, count 0 2006.285.14:23:35.69#ibcon#about to read 4, iclass 11, count 0 2006.285.14:23:35.69#ibcon#read 4, iclass 11, count 0 2006.285.14:23:35.69#ibcon#about to read 5, iclass 11, count 0 2006.285.14:23:35.69#ibcon#read 5, iclass 11, count 0 2006.285.14:23:35.69#ibcon#about to read 6, iclass 11, count 0 2006.285.14:23:35.69#ibcon#read 6, iclass 11, count 0 2006.285.14:23:35.69#ibcon#end of sib2, iclass 11, count 0 2006.285.14:23:35.69#ibcon#*after write, iclass 11, count 0 2006.285.14:23:35.69#ibcon#*before return 0, iclass 11, count 0 2006.285.14:23:35.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:23:35.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:23:35.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.14:23:35.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.14:23:35.69$vck44/vb=5,4 2006.285.14:23:35.69#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.14:23:35.69#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.14:23:35.69#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:35.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:23:35.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:23:35.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:23:35.75#ibcon#enter wrdev, iclass 13, count 2 2006.285.14:23:35.75#ibcon#first serial, iclass 13, count 2 2006.285.14:23:35.75#ibcon#enter sib2, iclass 13, count 2 2006.285.14:23:35.75#ibcon#flushed, iclass 13, count 2 2006.285.14:23:35.75#ibcon#about to write, iclass 13, count 2 2006.285.14:23:35.75#ibcon#wrote, iclass 13, count 2 2006.285.14:23:35.75#ibcon#about to read 3, iclass 13, count 2 2006.285.14:23:35.77#ibcon#read 3, iclass 13, count 2 2006.285.14:23:35.77#ibcon#about to read 4, iclass 13, count 2 2006.285.14:23:35.77#ibcon#read 4, iclass 13, count 2 2006.285.14:23:35.77#ibcon#about to read 5, iclass 13, count 2 2006.285.14:23:35.77#ibcon#read 5, iclass 13, count 2 2006.285.14:23:35.77#ibcon#about to read 6, iclass 13, count 2 2006.285.14:23:35.77#ibcon#read 6, iclass 13, count 2 2006.285.14:23:35.77#ibcon#end of sib2, iclass 13, count 2 2006.285.14:23:35.77#ibcon#*mode == 0, iclass 13, count 2 2006.285.14:23:35.77#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.14:23:35.77#ibcon#[27=AT05-04\r\n] 2006.285.14:23:35.77#ibcon#*before write, iclass 13, count 2 2006.285.14:23:35.77#ibcon#enter sib2, iclass 13, count 2 2006.285.14:23:35.77#ibcon#flushed, iclass 13, count 2 2006.285.14:23:35.77#ibcon#about to write, iclass 13, count 2 2006.285.14:23:35.77#ibcon#wrote, iclass 13, count 2 2006.285.14:23:35.77#ibcon#about to read 3, iclass 13, count 2 2006.285.14:23:35.80#ibcon#read 3, iclass 13, count 2 2006.285.14:23:35.80#ibcon#about to read 4, iclass 13, count 2 2006.285.14:23:35.80#ibcon#read 4, iclass 13, count 2 2006.285.14:23:35.80#ibcon#about to read 5, iclass 13, count 2 2006.285.14:23:35.80#ibcon#read 5, iclass 13, count 2 2006.285.14:23:35.80#ibcon#about to read 6, iclass 13, count 2 2006.285.14:23:35.80#ibcon#read 6, iclass 13, count 2 2006.285.14:23:35.80#ibcon#end of sib2, iclass 13, count 2 2006.285.14:23:35.80#ibcon#*after write, iclass 13, count 2 2006.285.14:23:35.80#ibcon#*before return 0, iclass 13, count 2 2006.285.14:23:35.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:23:35.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:23:35.80#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.14:23:35.80#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:35.80#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:23:35.92#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:23:35.92#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:23:35.92#ibcon#enter wrdev, iclass 13, count 0 2006.285.14:23:35.92#ibcon#first serial, iclass 13, count 0 2006.285.14:23:35.92#ibcon#enter sib2, iclass 13, count 0 2006.285.14:23:35.92#ibcon#flushed, iclass 13, count 0 2006.285.14:23:35.92#ibcon#about to write, iclass 13, count 0 2006.285.14:23:35.92#ibcon#wrote, iclass 13, count 0 2006.285.14:23:35.92#ibcon#about to read 3, iclass 13, count 0 2006.285.14:23:35.94#ibcon#read 3, iclass 13, count 0 2006.285.14:23:35.94#ibcon#about to read 4, iclass 13, count 0 2006.285.14:23:35.94#ibcon#read 4, iclass 13, count 0 2006.285.14:23:35.94#ibcon#about to read 5, iclass 13, count 0 2006.285.14:23:35.94#ibcon#read 5, iclass 13, count 0 2006.285.14:23:35.94#ibcon#about to read 6, iclass 13, count 0 2006.285.14:23:35.94#ibcon#read 6, iclass 13, count 0 2006.285.14:23:35.94#ibcon#end of sib2, iclass 13, count 0 2006.285.14:23:35.94#ibcon#*mode == 0, iclass 13, count 0 2006.285.14:23:35.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.14:23:35.94#ibcon#[27=USB\r\n] 2006.285.14:23:35.94#ibcon#*before write, iclass 13, count 0 2006.285.14:23:35.94#ibcon#enter sib2, iclass 13, count 0 2006.285.14:23:35.94#ibcon#flushed, iclass 13, count 0 2006.285.14:23:35.94#ibcon#about to write, iclass 13, count 0 2006.285.14:23:35.94#ibcon#wrote, iclass 13, count 0 2006.285.14:23:35.94#ibcon#about to read 3, iclass 13, count 0 2006.285.14:23:35.97#ibcon#read 3, iclass 13, count 0 2006.285.14:23:35.97#ibcon#about to read 4, iclass 13, count 0 2006.285.14:23:35.97#ibcon#read 4, iclass 13, count 0 2006.285.14:23:35.97#ibcon#about to read 5, iclass 13, count 0 2006.285.14:23:35.97#ibcon#read 5, iclass 13, count 0 2006.285.14:23:35.97#ibcon#about to read 6, iclass 13, count 0 2006.285.14:23:35.97#ibcon#read 6, iclass 13, count 0 2006.285.14:23:35.97#ibcon#end of sib2, iclass 13, count 0 2006.285.14:23:35.97#ibcon#*after write, iclass 13, count 0 2006.285.14:23:35.97#ibcon#*before return 0, iclass 13, count 0 2006.285.14:23:35.97#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:23:35.97#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:23:35.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.14:23:35.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.14:23:35.97$vck44/vblo=6,719.99 2006.285.14:23:35.97#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.14:23:35.97#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.14:23:35.97#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:35.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:23:35.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:23:35.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:23:35.97#ibcon#enter wrdev, iclass 15, count 0 2006.285.14:23:35.97#ibcon#first serial, iclass 15, count 0 2006.285.14:23:35.97#ibcon#enter sib2, iclass 15, count 0 2006.285.14:23:35.97#ibcon#flushed, iclass 15, count 0 2006.285.14:23:35.97#ibcon#about to write, iclass 15, count 0 2006.285.14:23:35.97#ibcon#wrote, iclass 15, count 0 2006.285.14:23:35.97#ibcon#about to read 3, iclass 15, count 0 2006.285.14:23:35.99#ibcon#read 3, iclass 15, count 0 2006.285.14:23:36.08#ibcon#about to read 4, iclass 15, count 0 2006.285.14:23:36.08#ibcon#read 4, iclass 15, count 0 2006.285.14:23:36.08#ibcon#about to read 5, iclass 15, count 0 2006.285.14:23:36.08#ibcon#read 5, iclass 15, count 0 2006.285.14:23:36.08#ibcon#about to read 6, iclass 15, count 0 2006.285.14:23:36.08#ibcon#read 6, iclass 15, count 0 2006.285.14:23:36.08#ibcon#end of sib2, iclass 15, count 0 2006.285.14:23:36.08#ibcon#*mode == 0, iclass 15, count 0 2006.285.14:23:36.08#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.14:23:36.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.14:23:36.08#ibcon#*before write, iclass 15, count 0 2006.285.14:23:36.08#ibcon#enter sib2, iclass 15, count 0 2006.285.14:23:36.08#ibcon#flushed, iclass 15, count 0 2006.285.14:23:36.08#ibcon#about to write, iclass 15, count 0 2006.285.14:23:36.08#ibcon#wrote, iclass 15, count 0 2006.285.14:23:36.08#ibcon#about to read 3, iclass 15, count 0 2006.285.14:23:36.11#ibcon#read 3, iclass 15, count 0 2006.285.14:23:36.11#ibcon#about to read 4, iclass 15, count 0 2006.285.14:23:36.11#ibcon#read 4, iclass 15, count 0 2006.285.14:23:36.11#ibcon#about to read 5, iclass 15, count 0 2006.285.14:23:36.11#ibcon#read 5, iclass 15, count 0 2006.285.14:23:36.11#ibcon#about to read 6, iclass 15, count 0 2006.285.14:23:36.11#ibcon#read 6, iclass 15, count 0 2006.285.14:23:36.11#ibcon#end of sib2, iclass 15, count 0 2006.285.14:23:36.11#ibcon#*after write, iclass 15, count 0 2006.285.14:23:36.11#ibcon#*before return 0, iclass 15, count 0 2006.285.14:23:36.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:23:36.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:23:36.11#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.14:23:36.11#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.14:23:36.11$vck44/vb=6,3 2006.285.14:23:36.11#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.14:23:36.11#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.14:23:36.11#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:36.11#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:23:36.11#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:23:36.11#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:23:36.11#ibcon#enter wrdev, iclass 17, count 2 2006.285.14:23:36.11#ibcon#first serial, iclass 17, count 2 2006.285.14:23:36.11#ibcon#enter sib2, iclass 17, count 2 2006.285.14:23:36.11#ibcon#flushed, iclass 17, count 2 2006.285.14:23:36.11#ibcon#about to write, iclass 17, count 2 2006.285.14:23:36.11#ibcon#wrote, iclass 17, count 2 2006.285.14:23:36.11#ibcon#about to read 3, iclass 17, count 2 2006.285.14:23:36.13#ibcon#read 3, iclass 17, count 2 2006.285.14:23:36.13#ibcon#about to read 4, iclass 17, count 2 2006.285.14:23:36.13#ibcon#read 4, iclass 17, count 2 2006.285.14:23:36.13#ibcon#about to read 5, iclass 17, count 2 2006.285.14:23:36.13#ibcon#read 5, iclass 17, count 2 2006.285.14:23:36.13#ibcon#about to read 6, iclass 17, count 2 2006.285.14:23:36.13#ibcon#read 6, iclass 17, count 2 2006.285.14:23:36.13#ibcon#end of sib2, iclass 17, count 2 2006.285.14:23:36.13#ibcon#*mode == 0, iclass 17, count 2 2006.285.14:23:36.13#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.14:23:36.13#ibcon#[27=AT06-03\r\n] 2006.285.14:23:36.13#ibcon#*before write, iclass 17, count 2 2006.285.14:23:36.13#ibcon#enter sib2, iclass 17, count 2 2006.285.14:23:36.13#ibcon#flushed, iclass 17, count 2 2006.285.14:23:36.13#ibcon#about to write, iclass 17, count 2 2006.285.14:23:36.13#ibcon#wrote, iclass 17, count 2 2006.285.14:23:36.13#ibcon#about to read 3, iclass 17, count 2 2006.285.14:23:36.16#ibcon#read 3, iclass 17, count 2 2006.285.14:23:36.16#ibcon#about to read 4, iclass 17, count 2 2006.285.14:23:36.16#ibcon#read 4, iclass 17, count 2 2006.285.14:23:36.16#ibcon#about to read 5, iclass 17, count 2 2006.285.14:23:36.16#ibcon#read 5, iclass 17, count 2 2006.285.14:23:36.16#ibcon#about to read 6, iclass 17, count 2 2006.285.14:23:36.16#ibcon#read 6, iclass 17, count 2 2006.285.14:23:36.16#ibcon#end of sib2, iclass 17, count 2 2006.285.14:23:36.16#ibcon#*after write, iclass 17, count 2 2006.285.14:23:36.16#ibcon#*before return 0, iclass 17, count 2 2006.285.14:23:36.16#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:23:36.16#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:23:36.16#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.14:23:36.16#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:36.16#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:23:36.28#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:23:36.28#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:23:36.28#ibcon#enter wrdev, iclass 17, count 0 2006.285.14:23:36.28#ibcon#first serial, iclass 17, count 0 2006.285.14:23:36.28#ibcon#enter sib2, iclass 17, count 0 2006.285.14:23:36.28#ibcon#flushed, iclass 17, count 0 2006.285.14:23:36.28#ibcon#about to write, iclass 17, count 0 2006.285.14:23:36.28#ibcon#wrote, iclass 17, count 0 2006.285.14:23:36.28#ibcon#about to read 3, iclass 17, count 0 2006.285.14:23:36.30#ibcon#read 3, iclass 17, count 0 2006.285.14:23:36.30#ibcon#about to read 4, iclass 17, count 0 2006.285.14:23:36.30#ibcon#read 4, iclass 17, count 0 2006.285.14:23:36.30#ibcon#about to read 5, iclass 17, count 0 2006.285.14:23:36.30#ibcon#read 5, iclass 17, count 0 2006.285.14:23:36.30#ibcon#about to read 6, iclass 17, count 0 2006.285.14:23:36.30#ibcon#read 6, iclass 17, count 0 2006.285.14:23:36.30#ibcon#end of sib2, iclass 17, count 0 2006.285.14:23:36.30#ibcon#*mode == 0, iclass 17, count 0 2006.285.14:23:36.30#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.14:23:36.30#ibcon#[27=USB\r\n] 2006.285.14:23:36.30#ibcon#*before write, iclass 17, count 0 2006.285.14:23:36.30#ibcon#enter sib2, iclass 17, count 0 2006.285.14:23:36.30#ibcon#flushed, iclass 17, count 0 2006.285.14:23:36.30#ibcon#about to write, iclass 17, count 0 2006.285.14:23:36.30#ibcon#wrote, iclass 17, count 0 2006.285.14:23:36.30#ibcon#about to read 3, iclass 17, count 0 2006.285.14:23:36.33#ibcon#read 3, iclass 17, count 0 2006.285.14:23:36.33#ibcon#about to read 4, iclass 17, count 0 2006.285.14:23:36.33#ibcon#read 4, iclass 17, count 0 2006.285.14:23:36.33#ibcon#about to read 5, iclass 17, count 0 2006.285.14:23:36.33#ibcon#read 5, iclass 17, count 0 2006.285.14:23:36.33#ibcon#about to read 6, iclass 17, count 0 2006.285.14:23:36.33#ibcon#read 6, iclass 17, count 0 2006.285.14:23:36.33#ibcon#end of sib2, iclass 17, count 0 2006.285.14:23:36.33#ibcon#*after write, iclass 17, count 0 2006.285.14:23:36.33#ibcon#*before return 0, iclass 17, count 0 2006.285.14:23:36.33#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:23:36.33#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:23:36.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.14:23:36.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.14:23:36.33$vck44/vblo=7,734.99 2006.285.14:23:36.33#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.14:23:36.33#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.14:23:36.33#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:36.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:23:36.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:23:36.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:23:36.33#ibcon#enter wrdev, iclass 19, count 0 2006.285.14:23:36.33#ibcon#first serial, iclass 19, count 0 2006.285.14:23:36.33#ibcon#enter sib2, iclass 19, count 0 2006.285.14:23:36.33#ibcon#flushed, iclass 19, count 0 2006.285.14:23:36.33#ibcon#about to write, iclass 19, count 0 2006.285.14:23:36.33#ibcon#wrote, iclass 19, count 0 2006.285.14:23:36.33#ibcon#about to read 3, iclass 19, count 0 2006.285.14:23:36.35#ibcon#read 3, iclass 19, count 0 2006.285.14:23:36.35#ibcon#about to read 4, iclass 19, count 0 2006.285.14:23:36.35#ibcon#read 4, iclass 19, count 0 2006.285.14:23:36.35#ibcon#about to read 5, iclass 19, count 0 2006.285.14:23:36.35#ibcon#read 5, iclass 19, count 0 2006.285.14:23:36.35#ibcon#about to read 6, iclass 19, count 0 2006.285.14:23:36.35#ibcon#read 6, iclass 19, count 0 2006.285.14:23:36.35#ibcon#end of sib2, iclass 19, count 0 2006.285.14:23:36.35#ibcon#*mode == 0, iclass 19, count 0 2006.285.14:23:36.35#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.14:23:36.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.14:23:36.35#ibcon#*before write, iclass 19, count 0 2006.285.14:23:36.35#ibcon#enter sib2, iclass 19, count 0 2006.285.14:23:36.35#ibcon#flushed, iclass 19, count 0 2006.285.14:23:36.35#ibcon#about to write, iclass 19, count 0 2006.285.14:23:36.35#ibcon#wrote, iclass 19, count 0 2006.285.14:23:36.35#ibcon#about to read 3, iclass 19, count 0 2006.285.14:23:36.39#ibcon#read 3, iclass 19, count 0 2006.285.14:23:36.39#ibcon#about to read 4, iclass 19, count 0 2006.285.14:23:36.39#ibcon#read 4, iclass 19, count 0 2006.285.14:23:36.39#ibcon#about to read 5, iclass 19, count 0 2006.285.14:23:36.39#ibcon#read 5, iclass 19, count 0 2006.285.14:23:36.39#ibcon#about to read 6, iclass 19, count 0 2006.285.14:23:36.39#ibcon#read 6, iclass 19, count 0 2006.285.14:23:36.39#ibcon#end of sib2, iclass 19, count 0 2006.285.14:23:36.39#ibcon#*after write, iclass 19, count 0 2006.285.14:23:36.39#ibcon#*before return 0, iclass 19, count 0 2006.285.14:23:36.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:23:36.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:23:36.39#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.14:23:36.39#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.14:23:36.39$vck44/vb=7,4 2006.285.14:23:36.39#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.14:23:36.39#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.14:23:36.39#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:36.39#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:23:36.45#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:23:36.45#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:23:36.45#ibcon#enter wrdev, iclass 21, count 2 2006.285.14:23:36.45#ibcon#first serial, iclass 21, count 2 2006.285.14:23:36.45#ibcon#enter sib2, iclass 21, count 2 2006.285.14:23:36.45#ibcon#flushed, iclass 21, count 2 2006.285.14:23:36.45#ibcon#about to write, iclass 21, count 2 2006.285.14:23:36.45#ibcon#wrote, iclass 21, count 2 2006.285.14:23:36.45#ibcon#about to read 3, iclass 21, count 2 2006.285.14:23:36.47#ibcon#read 3, iclass 21, count 2 2006.285.14:23:36.47#ibcon#about to read 4, iclass 21, count 2 2006.285.14:23:36.47#ibcon#read 4, iclass 21, count 2 2006.285.14:23:36.47#ibcon#about to read 5, iclass 21, count 2 2006.285.14:23:36.47#ibcon#read 5, iclass 21, count 2 2006.285.14:23:36.47#ibcon#about to read 6, iclass 21, count 2 2006.285.14:23:36.47#ibcon#read 6, iclass 21, count 2 2006.285.14:23:36.47#ibcon#end of sib2, iclass 21, count 2 2006.285.14:23:36.47#ibcon#*mode == 0, iclass 21, count 2 2006.285.14:23:36.47#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.14:23:36.47#ibcon#[27=AT07-04\r\n] 2006.285.14:23:36.47#ibcon#*before write, iclass 21, count 2 2006.285.14:23:36.47#ibcon#enter sib2, iclass 21, count 2 2006.285.14:23:36.47#ibcon#flushed, iclass 21, count 2 2006.285.14:23:36.47#ibcon#about to write, iclass 21, count 2 2006.285.14:23:36.47#ibcon#wrote, iclass 21, count 2 2006.285.14:23:36.47#ibcon#about to read 3, iclass 21, count 2 2006.285.14:23:36.50#ibcon#read 3, iclass 21, count 2 2006.285.14:23:36.50#ibcon#about to read 4, iclass 21, count 2 2006.285.14:23:36.50#ibcon#read 4, iclass 21, count 2 2006.285.14:23:36.50#ibcon#about to read 5, iclass 21, count 2 2006.285.14:23:36.50#ibcon#read 5, iclass 21, count 2 2006.285.14:23:36.50#ibcon#about to read 6, iclass 21, count 2 2006.285.14:23:36.50#ibcon#read 6, iclass 21, count 2 2006.285.14:23:36.50#ibcon#end of sib2, iclass 21, count 2 2006.285.14:23:36.50#ibcon#*after write, iclass 21, count 2 2006.285.14:23:36.50#ibcon#*before return 0, iclass 21, count 2 2006.285.14:23:36.50#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:23:36.50#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:23:36.50#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.14:23:36.50#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:36.50#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:23:36.62#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:23:36.62#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:23:36.62#ibcon#enter wrdev, iclass 21, count 0 2006.285.14:23:36.62#ibcon#first serial, iclass 21, count 0 2006.285.14:23:36.62#ibcon#enter sib2, iclass 21, count 0 2006.285.14:23:36.62#ibcon#flushed, iclass 21, count 0 2006.285.14:23:36.62#ibcon#about to write, iclass 21, count 0 2006.285.14:23:36.62#ibcon#wrote, iclass 21, count 0 2006.285.14:23:36.62#ibcon#about to read 3, iclass 21, count 0 2006.285.14:23:36.64#ibcon#read 3, iclass 21, count 0 2006.285.14:23:36.64#ibcon#about to read 4, iclass 21, count 0 2006.285.14:23:36.64#ibcon#read 4, iclass 21, count 0 2006.285.14:23:36.64#ibcon#about to read 5, iclass 21, count 0 2006.285.14:23:36.64#ibcon#read 5, iclass 21, count 0 2006.285.14:23:36.64#ibcon#about to read 6, iclass 21, count 0 2006.285.14:23:36.64#ibcon#read 6, iclass 21, count 0 2006.285.14:23:36.64#ibcon#end of sib2, iclass 21, count 0 2006.285.14:23:36.64#ibcon#*mode == 0, iclass 21, count 0 2006.285.14:23:36.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.14:23:36.64#ibcon#[27=USB\r\n] 2006.285.14:23:36.64#ibcon#*before write, iclass 21, count 0 2006.285.14:23:36.64#ibcon#enter sib2, iclass 21, count 0 2006.285.14:23:36.64#ibcon#flushed, iclass 21, count 0 2006.285.14:23:36.64#ibcon#about to write, iclass 21, count 0 2006.285.14:23:36.64#ibcon#wrote, iclass 21, count 0 2006.285.14:23:36.64#ibcon#about to read 3, iclass 21, count 0 2006.285.14:23:36.67#ibcon#read 3, iclass 21, count 0 2006.285.14:23:36.67#ibcon#about to read 4, iclass 21, count 0 2006.285.14:23:36.67#ibcon#read 4, iclass 21, count 0 2006.285.14:23:36.67#ibcon#about to read 5, iclass 21, count 0 2006.285.14:23:36.67#ibcon#read 5, iclass 21, count 0 2006.285.14:23:36.67#ibcon#about to read 6, iclass 21, count 0 2006.285.14:23:36.67#ibcon#read 6, iclass 21, count 0 2006.285.14:23:36.67#ibcon#end of sib2, iclass 21, count 0 2006.285.14:23:36.67#ibcon#*after write, iclass 21, count 0 2006.285.14:23:36.67#ibcon#*before return 0, iclass 21, count 0 2006.285.14:23:36.67#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:23:36.67#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:23:36.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.14:23:36.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.14:23:36.67$vck44/vblo=8,744.99 2006.285.14:23:36.67#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.14:23:36.67#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.14:23:36.67#ibcon#ireg 17 cls_cnt 0 2006.285.14:23:36.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:23:36.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:23:36.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:23:36.67#ibcon#enter wrdev, iclass 23, count 0 2006.285.14:23:36.67#ibcon#first serial, iclass 23, count 0 2006.285.14:23:36.67#ibcon#enter sib2, iclass 23, count 0 2006.285.14:23:36.67#ibcon#flushed, iclass 23, count 0 2006.285.14:23:36.67#ibcon#about to write, iclass 23, count 0 2006.285.14:23:36.67#ibcon#wrote, iclass 23, count 0 2006.285.14:23:36.67#ibcon#about to read 3, iclass 23, count 0 2006.285.14:23:36.69#ibcon#read 3, iclass 23, count 0 2006.285.14:23:36.69#ibcon#about to read 4, iclass 23, count 0 2006.285.14:23:36.69#ibcon#read 4, iclass 23, count 0 2006.285.14:23:36.69#ibcon#about to read 5, iclass 23, count 0 2006.285.14:23:36.69#ibcon#read 5, iclass 23, count 0 2006.285.14:23:36.69#ibcon#about to read 6, iclass 23, count 0 2006.285.14:23:36.69#ibcon#read 6, iclass 23, count 0 2006.285.14:23:36.69#ibcon#end of sib2, iclass 23, count 0 2006.285.14:23:36.69#ibcon#*mode == 0, iclass 23, count 0 2006.285.14:23:36.69#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.14:23:36.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.14:23:36.69#ibcon#*before write, iclass 23, count 0 2006.285.14:23:36.69#ibcon#enter sib2, iclass 23, count 0 2006.285.14:23:36.69#ibcon#flushed, iclass 23, count 0 2006.285.14:23:36.69#ibcon#about to write, iclass 23, count 0 2006.285.14:23:36.69#ibcon#wrote, iclass 23, count 0 2006.285.14:23:36.69#ibcon#about to read 3, iclass 23, count 0 2006.285.14:23:36.73#ibcon#read 3, iclass 23, count 0 2006.285.14:23:36.73#ibcon#about to read 4, iclass 23, count 0 2006.285.14:23:36.73#ibcon#read 4, iclass 23, count 0 2006.285.14:23:36.73#ibcon#about to read 5, iclass 23, count 0 2006.285.14:23:36.73#ibcon#read 5, iclass 23, count 0 2006.285.14:23:36.73#ibcon#about to read 6, iclass 23, count 0 2006.285.14:23:36.73#ibcon#read 6, iclass 23, count 0 2006.285.14:23:36.73#ibcon#end of sib2, iclass 23, count 0 2006.285.14:23:36.73#ibcon#*after write, iclass 23, count 0 2006.285.14:23:36.73#ibcon#*before return 0, iclass 23, count 0 2006.285.14:23:36.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:23:36.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:23:36.73#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.14:23:36.73#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.14:23:36.73$vck44/vb=8,4 2006.285.14:23:36.73#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.14:23:36.73#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.14:23:36.73#ibcon#ireg 11 cls_cnt 2 2006.285.14:23:36.73#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:23:36.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:23:36.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:23:36.79#ibcon#enter wrdev, iclass 25, count 2 2006.285.14:23:36.79#ibcon#first serial, iclass 25, count 2 2006.285.14:23:36.79#ibcon#enter sib2, iclass 25, count 2 2006.285.14:23:36.79#ibcon#flushed, iclass 25, count 2 2006.285.14:23:36.79#ibcon#about to write, iclass 25, count 2 2006.285.14:23:36.79#ibcon#wrote, iclass 25, count 2 2006.285.14:23:36.79#ibcon#about to read 3, iclass 25, count 2 2006.285.14:23:36.81#ibcon#read 3, iclass 25, count 2 2006.285.14:23:36.81#ibcon#about to read 4, iclass 25, count 2 2006.285.14:23:36.81#ibcon#read 4, iclass 25, count 2 2006.285.14:23:36.81#ibcon#about to read 5, iclass 25, count 2 2006.285.14:23:36.81#ibcon#read 5, iclass 25, count 2 2006.285.14:23:36.81#ibcon#about to read 6, iclass 25, count 2 2006.285.14:23:36.81#ibcon#read 6, iclass 25, count 2 2006.285.14:23:36.81#ibcon#end of sib2, iclass 25, count 2 2006.285.14:23:36.81#ibcon#*mode == 0, iclass 25, count 2 2006.285.14:23:36.81#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.14:23:36.81#ibcon#[27=AT08-04\r\n] 2006.285.14:23:36.81#ibcon#*before write, iclass 25, count 2 2006.285.14:23:36.81#ibcon#enter sib2, iclass 25, count 2 2006.285.14:23:36.81#ibcon#flushed, iclass 25, count 2 2006.285.14:23:36.81#ibcon#about to write, iclass 25, count 2 2006.285.14:23:36.81#ibcon#wrote, iclass 25, count 2 2006.285.14:23:36.81#ibcon#about to read 3, iclass 25, count 2 2006.285.14:23:36.84#ibcon#read 3, iclass 25, count 2 2006.285.14:23:36.84#ibcon#about to read 4, iclass 25, count 2 2006.285.14:23:36.84#ibcon#read 4, iclass 25, count 2 2006.285.14:23:36.84#ibcon#about to read 5, iclass 25, count 2 2006.285.14:23:36.84#ibcon#read 5, iclass 25, count 2 2006.285.14:23:36.84#ibcon#about to read 6, iclass 25, count 2 2006.285.14:23:36.84#ibcon#read 6, iclass 25, count 2 2006.285.14:23:36.84#ibcon#end of sib2, iclass 25, count 2 2006.285.14:23:36.84#ibcon#*after write, iclass 25, count 2 2006.285.14:23:36.84#ibcon#*before return 0, iclass 25, count 2 2006.285.14:23:36.84#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:23:36.84#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:23:36.84#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.14:23:36.84#ibcon#ireg 7 cls_cnt 0 2006.285.14:23:36.84#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:23:36.96#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:23:36.96#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:23:36.96#ibcon#enter wrdev, iclass 25, count 0 2006.285.14:23:36.96#ibcon#first serial, iclass 25, count 0 2006.285.14:23:36.96#ibcon#enter sib2, iclass 25, count 0 2006.285.14:23:36.96#ibcon#flushed, iclass 25, count 0 2006.285.14:23:36.96#ibcon#about to write, iclass 25, count 0 2006.285.14:23:36.96#ibcon#wrote, iclass 25, count 0 2006.285.14:23:36.96#ibcon#about to read 3, iclass 25, count 0 2006.285.14:23:36.98#ibcon#read 3, iclass 25, count 0 2006.285.14:23:36.98#ibcon#about to read 4, iclass 25, count 0 2006.285.14:23:36.98#ibcon#read 4, iclass 25, count 0 2006.285.14:23:36.98#ibcon#about to read 5, iclass 25, count 0 2006.285.14:23:36.98#ibcon#read 5, iclass 25, count 0 2006.285.14:23:36.98#ibcon#about to read 6, iclass 25, count 0 2006.285.14:23:36.98#ibcon#read 6, iclass 25, count 0 2006.285.14:23:36.98#ibcon#end of sib2, iclass 25, count 0 2006.285.14:23:36.98#ibcon#*mode == 0, iclass 25, count 0 2006.285.14:23:36.98#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.14:23:36.98#ibcon#[27=USB\r\n] 2006.285.14:23:36.98#ibcon#*before write, iclass 25, count 0 2006.285.14:23:36.98#ibcon#enter sib2, iclass 25, count 0 2006.285.14:23:36.98#ibcon#flushed, iclass 25, count 0 2006.285.14:23:36.98#ibcon#about to write, iclass 25, count 0 2006.285.14:23:36.98#ibcon#wrote, iclass 25, count 0 2006.285.14:23:36.98#ibcon#about to read 3, iclass 25, count 0 2006.285.14:23:37.01#ibcon#read 3, iclass 25, count 0 2006.285.14:23:37.01#ibcon#about to read 4, iclass 25, count 0 2006.285.14:23:37.06#ibcon#read 4, iclass 25, count 0 2006.285.14:23:37.06#ibcon#about to read 5, iclass 25, count 0 2006.285.14:23:37.06#ibcon#read 5, iclass 25, count 0 2006.285.14:23:37.06#ibcon#about to read 6, iclass 25, count 0 2006.285.14:23:37.06#ibcon#read 6, iclass 25, count 0 2006.285.14:23:37.06#ibcon#end of sib2, iclass 25, count 0 2006.285.14:23:37.06#ibcon#*after write, iclass 25, count 0 2006.285.14:23:37.06#ibcon#*before return 0, iclass 25, count 0 2006.285.14:23:37.06#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:23:37.06#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:23:37.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.14:23:37.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.14:23:37.06$vck44/vabw=wide 2006.285.14:23:37.06#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.14:23:37.06#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.14:23:37.06#ibcon#ireg 8 cls_cnt 0 2006.285.14:23:37.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:23:37.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:23:37.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:23:37.06#ibcon#enter wrdev, iclass 27, count 0 2006.285.14:23:37.06#ibcon#first serial, iclass 27, count 0 2006.285.14:23:37.06#ibcon#enter sib2, iclass 27, count 0 2006.285.14:23:37.06#ibcon#flushed, iclass 27, count 0 2006.285.14:23:37.06#ibcon#about to write, iclass 27, count 0 2006.285.14:23:37.06#ibcon#wrote, iclass 27, count 0 2006.285.14:23:37.06#ibcon#about to read 3, iclass 27, count 0 2006.285.14:23:37.07#ibcon#read 3, iclass 27, count 0 2006.285.14:23:37.07#ibcon#about to read 4, iclass 27, count 0 2006.285.14:23:37.07#ibcon#read 4, iclass 27, count 0 2006.285.14:23:37.07#ibcon#about to read 5, iclass 27, count 0 2006.285.14:23:37.07#ibcon#read 5, iclass 27, count 0 2006.285.14:23:37.07#ibcon#about to read 6, iclass 27, count 0 2006.285.14:23:37.07#ibcon#read 6, iclass 27, count 0 2006.285.14:23:37.07#ibcon#end of sib2, iclass 27, count 0 2006.285.14:23:37.07#ibcon#*mode == 0, iclass 27, count 0 2006.285.14:23:37.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.14:23:37.07#ibcon#[25=BW32\r\n] 2006.285.14:23:37.07#ibcon#*before write, iclass 27, count 0 2006.285.14:23:37.07#ibcon#enter sib2, iclass 27, count 0 2006.285.14:23:37.07#ibcon#flushed, iclass 27, count 0 2006.285.14:23:37.07#ibcon#about to write, iclass 27, count 0 2006.285.14:23:37.07#ibcon#wrote, iclass 27, count 0 2006.285.14:23:37.07#ibcon#about to read 3, iclass 27, count 0 2006.285.14:23:37.10#ibcon#read 3, iclass 27, count 0 2006.285.14:23:37.10#ibcon#about to read 4, iclass 27, count 0 2006.285.14:23:37.10#ibcon#read 4, iclass 27, count 0 2006.285.14:23:37.10#ibcon#about to read 5, iclass 27, count 0 2006.285.14:23:37.10#ibcon#read 5, iclass 27, count 0 2006.285.14:23:37.10#ibcon#about to read 6, iclass 27, count 0 2006.285.14:23:37.10#ibcon#read 6, iclass 27, count 0 2006.285.14:23:37.10#ibcon#end of sib2, iclass 27, count 0 2006.285.14:23:37.10#ibcon#*after write, iclass 27, count 0 2006.285.14:23:37.10#ibcon#*before return 0, iclass 27, count 0 2006.285.14:23:37.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:23:37.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:23:37.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.14:23:37.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.14:23:37.10$vck44/vbbw=wide 2006.285.14:23:37.10#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.14:23:37.10#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.14:23:37.10#ibcon#ireg 8 cls_cnt 0 2006.285.14:23:37.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:23:37.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:23:37.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:23:37.18#ibcon#enter wrdev, iclass 29, count 0 2006.285.14:23:37.18#ibcon#first serial, iclass 29, count 0 2006.285.14:23:37.18#ibcon#enter sib2, iclass 29, count 0 2006.285.14:23:37.18#ibcon#flushed, iclass 29, count 0 2006.285.14:23:37.18#ibcon#about to write, iclass 29, count 0 2006.285.14:23:37.18#ibcon#wrote, iclass 29, count 0 2006.285.14:23:37.18#ibcon#about to read 3, iclass 29, count 0 2006.285.14:23:37.20#ibcon#read 3, iclass 29, count 0 2006.285.14:23:37.20#ibcon#about to read 4, iclass 29, count 0 2006.285.14:23:37.20#ibcon#read 4, iclass 29, count 0 2006.285.14:23:37.20#ibcon#about to read 5, iclass 29, count 0 2006.285.14:23:37.20#ibcon#read 5, iclass 29, count 0 2006.285.14:23:37.20#ibcon#about to read 6, iclass 29, count 0 2006.285.14:23:37.20#ibcon#read 6, iclass 29, count 0 2006.285.14:23:37.20#ibcon#end of sib2, iclass 29, count 0 2006.285.14:23:37.20#ibcon#*mode == 0, iclass 29, count 0 2006.285.14:23:37.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.14:23:37.20#ibcon#[27=BW32\r\n] 2006.285.14:23:37.20#ibcon#*before write, iclass 29, count 0 2006.285.14:23:37.20#ibcon#enter sib2, iclass 29, count 0 2006.285.14:23:37.20#ibcon#flushed, iclass 29, count 0 2006.285.14:23:37.20#ibcon#about to write, iclass 29, count 0 2006.285.14:23:37.20#ibcon#wrote, iclass 29, count 0 2006.285.14:23:37.20#ibcon#about to read 3, iclass 29, count 0 2006.285.14:23:37.23#ibcon#read 3, iclass 29, count 0 2006.285.14:23:37.23#ibcon#about to read 4, iclass 29, count 0 2006.285.14:23:37.23#ibcon#read 4, iclass 29, count 0 2006.285.14:23:37.23#ibcon#about to read 5, iclass 29, count 0 2006.285.14:23:37.23#ibcon#read 5, iclass 29, count 0 2006.285.14:23:37.23#ibcon#about to read 6, iclass 29, count 0 2006.285.14:23:37.23#ibcon#read 6, iclass 29, count 0 2006.285.14:23:37.23#ibcon#end of sib2, iclass 29, count 0 2006.285.14:23:37.23#ibcon#*after write, iclass 29, count 0 2006.285.14:23:37.23#ibcon#*before return 0, iclass 29, count 0 2006.285.14:23:37.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:23:37.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:23:37.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.14:23:37.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.14:23:37.23$setupk4/ifdk4 2006.285.14:23:37.23$ifdk4/lo= 2006.285.14:23:37.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.14:23:37.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.14:23:37.23$ifdk4/patch= 2006.285.14:23:37.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.14:23:37.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.14:23:37.23$setupk4/!*+20s 2006.285.14:23:41.46#abcon#<5=/03 1.9 4.1 19.19 961015.1\r\n> 2006.285.14:23:41.48#abcon#{5=INTERFACE CLEAR} 2006.285.14:23:41.54#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:23:42.14#trakl#Source acquired 2006.285.14:23:44.14#flagr#flagr/antenna,acquired 2006.285.14:23:50.91$setupk4/"tpicd 2006.285.14:23:50.91$setupk4/echo=off 2006.285.14:23:50.91$setupk4/xlog=off 2006.285.14:23:50.91:!2006.285.14:25:36 2006.285.14:25:36.00:preob 2006.285.14:25:36.14/onsource/TRACKING 2006.285.14:25:36.14:!2006.285.14:25:46 2006.285.14:25:46.00:"tape 2006.285.14:25:46.00:"st=record 2006.285.14:25:46.00:data_valid=on 2006.285.14:25:46.00:midob 2006.285.14:25:47.14/onsource/TRACKING 2006.285.14:25:47.14/wx/19.19,1015.1,96 2006.285.14:25:47.27/cable/+6.4996E-03 2006.285.14:25:48.36/va/01,07,usb,yes,32,35 2006.285.14:25:48.36/va/02,06,usb,yes,32,33 2006.285.14:25:48.36/va/03,07,usb,yes,32,34 2006.285.14:25:48.36/va/04,06,usb,yes,33,35 2006.285.14:25:48.36/va/05,03,usb,yes,33,33 2006.285.14:25:48.36/va/06,04,usb,yes,29,29 2006.285.14:25:48.36/va/07,04,usb,yes,30,31 2006.285.14:25:48.36/va/08,03,usb,yes,31,37 2006.285.14:25:48.59/valo/01,524.99,yes,locked 2006.285.14:25:48.59/valo/02,534.99,yes,locked 2006.285.14:25:48.59/valo/03,564.99,yes,locked 2006.285.14:25:48.59/valo/04,624.99,yes,locked 2006.285.14:25:48.59/valo/05,734.99,yes,locked 2006.285.14:25:48.59/valo/06,814.99,yes,locked 2006.285.14:25:48.59/valo/07,864.99,yes,locked 2006.285.14:25:48.59/valo/08,884.99,yes,locked 2006.285.14:25:49.68/vb/01,04,usb,yes,30,28 2006.285.14:25:49.68/vb/02,05,usb,yes,28,28 2006.285.14:25:49.68/vb/03,04,usb,yes,29,32 2006.285.14:25:49.68/vb/04,05,usb,yes,30,29 2006.285.14:25:49.68/vb/05,04,usb,yes,26,29 2006.285.14:25:49.68/vb/06,03,usb,yes,38,34 2006.285.14:25:49.68/vb/07,04,usb,yes,30,30 2006.285.14:25:49.68/vb/08,04,usb,yes,28,31 2006.285.14:25:49.91/vblo/01,629.99,yes,locked 2006.285.14:25:49.91/vblo/02,634.99,yes,locked 2006.285.14:25:49.91/vblo/03,649.99,yes,locked 2006.285.14:25:49.91/vblo/04,679.99,yes,locked 2006.285.14:25:49.91/vblo/05,709.99,yes,locked 2006.285.14:25:49.91/vblo/06,719.99,yes,locked 2006.285.14:25:49.91/vblo/07,734.99,yes,locked 2006.285.14:25:49.91/vblo/08,744.99,yes,locked 2006.285.14:25:50.06/vabw/8 2006.285.14:25:50.21/vbbw/8 2006.285.14:25:50.30/xfe/off,on,12.2 2006.285.14:25:50.68/ifatt/23,28,28,28 2006.285.14:25:51.08/fmout-gps/S +2.82E-07 2006.285.14:25:51.10:!2006.285.14:27:06 2006.285.14:27:06.00:data_valid=off 2006.285.14:27:06.00:"et 2006.285.14:27:06.00:!+3s 2006.285.14:27:09.01:"tape 2006.285.14:27:09.01:postob 2006.285.14:27:09.11/cable/+6.5009E-03 2006.285.14:27:09.11/wx/19.19,1015.1,95 2006.285.14:27:10.07/fmout-gps/S +2.83E-07 2006.285.14:27:10.07:scan_name=285-1431,jd0610,80 2006.285.14:27:10.07:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.285.14:27:11.14#flagr#flagr/antenna,new-source 2006.285.14:27:11.14:checkk5 2006.285.14:27:11.83/chk_autoobs//k5ts1/ autoobs is running! 2006.285.14:27:12.31/chk_autoobs//k5ts2/ autoobs is running! 2006.285.14:27:12.70/chk_autoobs//k5ts3/ autoobs is running! 2006.285.14:27:13.26/chk_autoobs//k5ts4/ autoobs is running! 2006.285.14:27:13.84/chk_obsdata//k5ts1/T2851425??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.14:27:14.32/chk_obsdata//k5ts2/T2851425??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.14:27:14.73/chk_obsdata//k5ts3/T2851425??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.14:27:15.58/chk_obsdata//k5ts4/T2851425??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.14:27:16.61/k5log//k5ts1_log_newline 2006.285.14:27:17.38/k5log//k5ts2_log_newline 2006.285.14:27:18.58/k5log//k5ts3_log_newline 2006.285.14:27:19.61/k5log//k5ts4_log_newline 2006.285.14:27:19.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.14:27:19.63:setupk4=1 2006.285.14:27:19.63$setupk4/echo=on 2006.285.14:27:19.63$setupk4/pcalon 2006.285.14:27:19.63$pcalon/"no phase cal control is implemented here 2006.285.14:27:19.63$setupk4/"tpicd=stop 2006.285.14:27:19.63$setupk4/"rec=synch_on 2006.285.14:27:19.63$setupk4/"rec_mode=128 2006.285.14:27:19.63$setupk4/!* 2006.285.14:27:19.63$setupk4/recpk4 2006.285.14:27:19.63$recpk4/recpatch= 2006.285.14:27:19.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.14:27:19.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.14:27:19.64$setupk4/vck44 2006.285.14:27:19.64$vck44/valo=1,524.99 2006.285.14:27:19.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.14:27:19.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.14:27:19.64#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:19.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:27:19.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:27:19.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:27:19.64#ibcon#enter wrdev, iclass 14, count 0 2006.285.14:27:19.64#ibcon#first serial, iclass 14, count 0 2006.285.14:27:19.64#ibcon#enter sib2, iclass 14, count 0 2006.285.14:27:19.64#ibcon#flushed, iclass 14, count 0 2006.285.14:27:19.64#ibcon#about to write, iclass 14, count 0 2006.285.14:27:19.64#ibcon#wrote, iclass 14, count 0 2006.285.14:27:19.64#ibcon#about to read 3, iclass 14, count 0 2006.285.14:27:19.65#ibcon#read 3, iclass 14, count 0 2006.285.14:27:19.65#ibcon#about to read 4, iclass 14, count 0 2006.285.14:27:19.65#ibcon#read 4, iclass 14, count 0 2006.285.14:27:19.65#ibcon#about to read 5, iclass 14, count 0 2006.285.14:27:19.65#ibcon#read 5, iclass 14, count 0 2006.285.14:27:19.65#ibcon#about to read 6, iclass 14, count 0 2006.285.14:27:19.65#ibcon#read 6, iclass 14, count 0 2006.285.14:27:19.65#ibcon#end of sib2, iclass 14, count 0 2006.285.14:27:19.65#ibcon#*mode == 0, iclass 14, count 0 2006.285.14:27:19.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.14:27:19.65#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.14:27:19.65#ibcon#*before write, iclass 14, count 0 2006.285.14:27:19.65#ibcon#enter sib2, iclass 14, count 0 2006.285.14:27:19.65#ibcon#flushed, iclass 14, count 0 2006.285.14:27:19.65#ibcon#about to write, iclass 14, count 0 2006.285.14:27:19.65#ibcon#wrote, iclass 14, count 0 2006.285.14:27:19.65#ibcon#about to read 3, iclass 14, count 0 2006.285.14:27:19.70#ibcon#read 3, iclass 14, count 0 2006.285.14:27:19.70#ibcon#about to read 4, iclass 14, count 0 2006.285.14:27:19.70#ibcon#read 4, iclass 14, count 0 2006.285.14:27:19.70#ibcon#about to read 5, iclass 14, count 0 2006.285.14:27:19.70#ibcon#read 5, iclass 14, count 0 2006.285.14:27:19.70#ibcon#about to read 6, iclass 14, count 0 2006.285.14:27:19.70#ibcon#read 6, iclass 14, count 0 2006.285.14:27:19.70#ibcon#end of sib2, iclass 14, count 0 2006.285.14:27:19.70#ibcon#*after write, iclass 14, count 0 2006.285.14:27:19.70#ibcon#*before return 0, iclass 14, count 0 2006.285.14:27:19.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:27:19.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:27:19.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.14:27:19.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.14:27:19.70$vck44/va=1,7 2006.285.14:27:19.70#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.14:27:19.70#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.14:27:19.70#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:19.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:27:19.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:27:19.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:27:19.70#ibcon#enter wrdev, iclass 16, count 2 2006.285.14:27:19.70#ibcon#first serial, iclass 16, count 2 2006.285.14:27:19.70#ibcon#enter sib2, iclass 16, count 2 2006.285.14:27:19.70#ibcon#flushed, iclass 16, count 2 2006.285.14:27:19.70#ibcon#about to write, iclass 16, count 2 2006.285.14:27:19.70#ibcon#wrote, iclass 16, count 2 2006.285.14:27:19.70#ibcon#about to read 3, iclass 16, count 2 2006.285.14:27:19.72#ibcon#read 3, iclass 16, count 2 2006.285.14:27:19.72#ibcon#about to read 4, iclass 16, count 2 2006.285.14:27:19.72#ibcon#read 4, iclass 16, count 2 2006.285.14:27:19.72#ibcon#about to read 5, iclass 16, count 2 2006.285.14:27:19.72#ibcon#read 5, iclass 16, count 2 2006.285.14:27:19.72#ibcon#about to read 6, iclass 16, count 2 2006.285.14:27:19.72#ibcon#read 6, iclass 16, count 2 2006.285.14:27:19.72#ibcon#end of sib2, iclass 16, count 2 2006.285.14:27:19.72#ibcon#*mode == 0, iclass 16, count 2 2006.285.14:27:19.72#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.14:27:19.72#ibcon#[25=AT01-07\r\n] 2006.285.14:27:19.72#ibcon#*before write, iclass 16, count 2 2006.285.14:27:19.72#ibcon#enter sib2, iclass 16, count 2 2006.285.14:27:19.72#ibcon#flushed, iclass 16, count 2 2006.285.14:27:19.72#ibcon#about to write, iclass 16, count 2 2006.285.14:27:19.72#ibcon#wrote, iclass 16, count 2 2006.285.14:27:19.72#ibcon#about to read 3, iclass 16, count 2 2006.285.14:27:19.75#ibcon#read 3, iclass 16, count 2 2006.285.14:27:19.75#ibcon#about to read 4, iclass 16, count 2 2006.285.14:27:19.75#ibcon#read 4, iclass 16, count 2 2006.285.14:27:19.75#ibcon#about to read 5, iclass 16, count 2 2006.285.14:27:19.75#ibcon#read 5, iclass 16, count 2 2006.285.14:27:19.75#ibcon#about to read 6, iclass 16, count 2 2006.285.14:27:19.75#ibcon#read 6, iclass 16, count 2 2006.285.14:27:19.75#ibcon#end of sib2, iclass 16, count 2 2006.285.14:27:19.75#ibcon#*after write, iclass 16, count 2 2006.285.14:27:19.75#ibcon#*before return 0, iclass 16, count 2 2006.285.14:27:19.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:27:19.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:27:19.75#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.14:27:19.75#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:19.75#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:27:19.87#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:27:19.87#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:27:19.87#ibcon#enter wrdev, iclass 16, count 0 2006.285.14:27:19.87#ibcon#first serial, iclass 16, count 0 2006.285.14:27:19.87#ibcon#enter sib2, iclass 16, count 0 2006.285.14:27:19.87#ibcon#flushed, iclass 16, count 0 2006.285.14:27:19.87#ibcon#about to write, iclass 16, count 0 2006.285.14:27:19.87#ibcon#wrote, iclass 16, count 0 2006.285.14:27:19.87#ibcon#about to read 3, iclass 16, count 0 2006.285.14:27:19.89#ibcon#read 3, iclass 16, count 0 2006.285.14:27:19.89#ibcon#about to read 4, iclass 16, count 0 2006.285.14:27:19.89#ibcon#read 4, iclass 16, count 0 2006.285.14:27:19.89#ibcon#about to read 5, iclass 16, count 0 2006.285.14:27:19.89#ibcon#read 5, iclass 16, count 0 2006.285.14:27:19.89#ibcon#about to read 6, iclass 16, count 0 2006.285.14:27:19.89#ibcon#read 6, iclass 16, count 0 2006.285.14:27:19.89#ibcon#end of sib2, iclass 16, count 0 2006.285.14:27:19.89#ibcon#*mode == 0, iclass 16, count 0 2006.285.14:27:19.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.14:27:19.89#ibcon#[25=USB\r\n] 2006.285.14:27:19.89#ibcon#*before write, iclass 16, count 0 2006.285.14:27:19.89#ibcon#enter sib2, iclass 16, count 0 2006.285.14:27:19.89#ibcon#flushed, iclass 16, count 0 2006.285.14:27:19.89#ibcon#about to write, iclass 16, count 0 2006.285.14:27:19.89#ibcon#wrote, iclass 16, count 0 2006.285.14:27:19.89#ibcon#about to read 3, iclass 16, count 0 2006.285.14:27:19.92#ibcon#read 3, iclass 16, count 0 2006.285.14:27:19.92#ibcon#about to read 4, iclass 16, count 0 2006.285.14:27:19.92#ibcon#read 4, iclass 16, count 0 2006.285.14:27:19.92#ibcon#about to read 5, iclass 16, count 0 2006.285.14:27:19.92#ibcon#read 5, iclass 16, count 0 2006.285.14:27:19.92#ibcon#about to read 6, iclass 16, count 0 2006.285.14:27:19.92#ibcon#read 6, iclass 16, count 0 2006.285.14:27:19.92#ibcon#end of sib2, iclass 16, count 0 2006.285.14:27:19.92#ibcon#*after write, iclass 16, count 0 2006.285.14:27:19.92#ibcon#*before return 0, iclass 16, count 0 2006.285.14:27:19.92#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:27:19.92#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:27:19.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.14:27:19.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.14:27:19.92$vck44/valo=2,534.99 2006.285.14:27:19.92#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.14:27:19.92#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.14:27:19.92#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:19.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:27:19.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:27:19.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:27:19.92#ibcon#enter wrdev, iclass 18, count 0 2006.285.14:27:19.92#ibcon#first serial, iclass 18, count 0 2006.285.14:27:19.92#ibcon#enter sib2, iclass 18, count 0 2006.285.14:27:19.92#ibcon#flushed, iclass 18, count 0 2006.285.14:27:19.92#ibcon#about to write, iclass 18, count 0 2006.285.14:27:19.92#ibcon#wrote, iclass 18, count 0 2006.285.14:27:19.92#ibcon#about to read 3, iclass 18, count 0 2006.285.14:27:19.94#ibcon#read 3, iclass 18, count 0 2006.285.14:27:19.94#ibcon#about to read 4, iclass 18, count 0 2006.285.14:27:19.94#ibcon#read 4, iclass 18, count 0 2006.285.14:27:19.94#ibcon#about to read 5, iclass 18, count 0 2006.285.14:27:19.94#ibcon#read 5, iclass 18, count 0 2006.285.14:27:19.94#ibcon#about to read 6, iclass 18, count 0 2006.285.14:27:19.94#ibcon#read 6, iclass 18, count 0 2006.285.14:27:19.94#ibcon#end of sib2, iclass 18, count 0 2006.285.14:27:19.94#ibcon#*mode == 0, iclass 18, count 0 2006.285.14:27:19.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.14:27:19.94#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.14:27:19.94#ibcon#*before write, iclass 18, count 0 2006.285.14:27:19.94#ibcon#enter sib2, iclass 18, count 0 2006.285.14:27:19.94#ibcon#flushed, iclass 18, count 0 2006.285.14:27:19.94#ibcon#about to write, iclass 18, count 0 2006.285.14:27:19.94#ibcon#wrote, iclass 18, count 0 2006.285.14:27:19.94#ibcon#about to read 3, iclass 18, count 0 2006.285.14:27:19.98#ibcon#read 3, iclass 18, count 0 2006.285.14:27:19.98#ibcon#about to read 4, iclass 18, count 0 2006.285.14:27:19.98#ibcon#read 4, iclass 18, count 0 2006.285.14:27:19.98#ibcon#about to read 5, iclass 18, count 0 2006.285.14:27:19.98#ibcon#read 5, iclass 18, count 0 2006.285.14:27:19.98#ibcon#about to read 6, iclass 18, count 0 2006.285.14:27:19.98#ibcon#read 6, iclass 18, count 0 2006.285.14:27:19.98#ibcon#end of sib2, iclass 18, count 0 2006.285.14:27:19.98#ibcon#*after write, iclass 18, count 0 2006.285.14:27:19.98#ibcon#*before return 0, iclass 18, count 0 2006.285.14:27:19.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:27:19.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:27:19.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.14:27:19.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.14:27:19.98$vck44/va=2,6 2006.285.14:27:19.98#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.14:27:19.98#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.14:27:19.98#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:19.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:27:20.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:27:20.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:27:20.04#ibcon#enter wrdev, iclass 20, count 2 2006.285.14:27:20.04#ibcon#first serial, iclass 20, count 2 2006.285.14:27:20.04#ibcon#enter sib2, iclass 20, count 2 2006.285.14:27:20.04#ibcon#flushed, iclass 20, count 2 2006.285.14:27:20.04#ibcon#about to write, iclass 20, count 2 2006.285.14:27:20.04#ibcon#wrote, iclass 20, count 2 2006.285.14:27:20.04#ibcon#about to read 3, iclass 20, count 2 2006.285.14:27:20.06#ibcon#read 3, iclass 20, count 2 2006.285.14:27:20.06#ibcon#about to read 4, iclass 20, count 2 2006.285.14:27:20.06#ibcon#read 4, iclass 20, count 2 2006.285.14:27:20.06#ibcon#about to read 5, iclass 20, count 2 2006.285.14:27:20.06#ibcon#read 5, iclass 20, count 2 2006.285.14:27:20.06#ibcon#about to read 6, iclass 20, count 2 2006.285.14:27:20.06#ibcon#read 6, iclass 20, count 2 2006.285.14:27:20.06#ibcon#end of sib2, iclass 20, count 2 2006.285.14:27:20.06#ibcon#*mode == 0, iclass 20, count 2 2006.285.14:27:20.06#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.14:27:20.06#ibcon#[25=AT02-06\r\n] 2006.285.14:27:20.06#ibcon#*before write, iclass 20, count 2 2006.285.14:27:20.06#ibcon#enter sib2, iclass 20, count 2 2006.285.14:27:20.06#ibcon#flushed, iclass 20, count 2 2006.285.14:27:20.06#ibcon#about to write, iclass 20, count 2 2006.285.14:27:20.06#ibcon#wrote, iclass 20, count 2 2006.285.14:27:20.06#ibcon#about to read 3, iclass 20, count 2 2006.285.14:27:20.09#ibcon#read 3, iclass 20, count 2 2006.285.14:27:20.09#ibcon#about to read 4, iclass 20, count 2 2006.285.14:27:20.09#ibcon#read 4, iclass 20, count 2 2006.285.14:27:20.09#ibcon#about to read 5, iclass 20, count 2 2006.285.14:27:20.09#ibcon#read 5, iclass 20, count 2 2006.285.14:27:20.09#ibcon#about to read 6, iclass 20, count 2 2006.285.14:27:20.09#ibcon#read 6, iclass 20, count 2 2006.285.14:27:20.09#ibcon#end of sib2, iclass 20, count 2 2006.285.14:27:20.09#ibcon#*after write, iclass 20, count 2 2006.285.14:27:20.09#ibcon#*before return 0, iclass 20, count 2 2006.285.14:27:20.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:27:20.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:27:20.09#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.14:27:20.09#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:20.09#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:27:20.21#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:27:20.21#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:27:20.21#ibcon#enter wrdev, iclass 20, count 0 2006.285.14:27:20.21#ibcon#first serial, iclass 20, count 0 2006.285.14:27:20.21#ibcon#enter sib2, iclass 20, count 0 2006.285.14:27:20.21#ibcon#flushed, iclass 20, count 0 2006.285.14:27:20.21#ibcon#about to write, iclass 20, count 0 2006.285.14:27:20.21#ibcon#wrote, iclass 20, count 0 2006.285.14:27:20.21#ibcon#about to read 3, iclass 20, count 0 2006.285.14:27:20.23#ibcon#read 3, iclass 20, count 0 2006.285.14:27:20.55#ibcon#about to read 4, iclass 20, count 0 2006.285.14:27:20.55#ibcon#read 4, iclass 20, count 0 2006.285.14:27:20.55#ibcon#about to read 5, iclass 20, count 0 2006.285.14:27:20.55#ibcon#read 5, iclass 20, count 0 2006.285.14:27:20.55#ibcon#about to read 6, iclass 20, count 0 2006.285.14:27:20.55#ibcon#read 6, iclass 20, count 0 2006.285.14:27:20.55#ibcon#end of sib2, iclass 20, count 0 2006.285.14:27:20.55#ibcon#*mode == 0, iclass 20, count 0 2006.285.14:27:20.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.14:27:20.55#ibcon#[25=USB\r\n] 2006.285.14:27:20.55#ibcon#*before write, iclass 20, count 0 2006.285.14:27:20.55#ibcon#enter sib2, iclass 20, count 0 2006.285.14:27:20.55#ibcon#flushed, iclass 20, count 0 2006.285.14:27:20.55#ibcon#about to write, iclass 20, count 0 2006.285.14:27:20.55#ibcon#wrote, iclass 20, count 0 2006.285.14:27:20.55#ibcon#about to read 3, iclass 20, count 0 2006.285.14:27:20.58#ibcon#read 3, iclass 20, count 0 2006.285.14:27:20.58#ibcon#about to read 4, iclass 20, count 0 2006.285.14:27:20.58#ibcon#read 4, iclass 20, count 0 2006.285.14:27:20.58#ibcon#about to read 5, iclass 20, count 0 2006.285.14:27:20.58#ibcon#read 5, iclass 20, count 0 2006.285.14:27:20.58#ibcon#about to read 6, iclass 20, count 0 2006.285.14:27:20.58#ibcon#read 6, iclass 20, count 0 2006.285.14:27:20.58#ibcon#end of sib2, iclass 20, count 0 2006.285.14:27:20.58#ibcon#*after write, iclass 20, count 0 2006.285.14:27:20.58#ibcon#*before return 0, iclass 20, count 0 2006.285.14:27:20.58#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:27:20.58#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:27:20.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.14:27:20.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.14:27:20.58$vck44/valo=3,564.99 2006.285.14:27:20.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.14:27:20.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.14:27:20.58#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:20.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:27:20.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:27:20.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:27:20.58#ibcon#enter wrdev, iclass 22, count 0 2006.285.14:27:20.58#ibcon#first serial, iclass 22, count 0 2006.285.14:27:20.58#ibcon#enter sib2, iclass 22, count 0 2006.285.14:27:20.58#ibcon#flushed, iclass 22, count 0 2006.285.14:27:20.58#ibcon#about to write, iclass 22, count 0 2006.285.14:27:20.58#ibcon#wrote, iclass 22, count 0 2006.285.14:27:20.58#ibcon#about to read 3, iclass 22, count 0 2006.285.14:27:20.60#ibcon#read 3, iclass 22, count 0 2006.285.14:27:20.60#ibcon#about to read 4, iclass 22, count 0 2006.285.14:27:20.60#ibcon#read 4, iclass 22, count 0 2006.285.14:27:20.60#ibcon#about to read 5, iclass 22, count 0 2006.285.14:27:20.60#ibcon#read 5, iclass 22, count 0 2006.285.14:27:20.60#ibcon#about to read 6, iclass 22, count 0 2006.285.14:27:20.60#ibcon#read 6, iclass 22, count 0 2006.285.14:27:20.60#ibcon#end of sib2, iclass 22, count 0 2006.285.14:27:20.60#ibcon#*mode == 0, iclass 22, count 0 2006.285.14:27:20.60#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.14:27:20.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.14:27:20.60#ibcon#*before write, iclass 22, count 0 2006.285.14:27:20.60#ibcon#enter sib2, iclass 22, count 0 2006.285.14:27:20.60#ibcon#flushed, iclass 22, count 0 2006.285.14:27:20.60#ibcon#about to write, iclass 22, count 0 2006.285.14:27:20.60#ibcon#wrote, iclass 22, count 0 2006.285.14:27:20.60#ibcon#about to read 3, iclass 22, count 0 2006.285.14:27:20.64#ibcon#read 3, iclass 22, count 0 2006.285.14:27:20.64#ibcon#about to read 4, iclass 22, count 0 2006.285.14:27:20.64#ibcon#read 4, iclass 22, count 0 2006.285.14:27:20.64#ibcon#about to read 5, iclass 22, count 0 2006.285.14:27:20.64#ibcon#read 5, iclass 22, count 0 2006.285.14:27:20.64#ibcon#about to read 6, iclass 22, count 0 2006.285.14:27:20.64#ibcon#read 6, iclass 22, count 0 2006.285.14:27:20.64#ibcon#end of sib2, iclass 22, count 0 2006.285.14:27:20.64#ibcon#*after write, iclass 22, count 0 2006.285.14:27:20.64#ibcon#*before return 0, iclass 22, count 0 2006.285.14:27:20.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:27:20.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:27:20.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.14:27:20.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.14:27:20.64$vck44/va=3,7 2006.285.14:27:20.64#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.14:27:20.64#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.14:27:20.64#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:20.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:27:20.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:27:20.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:27:20.70#ibcon#enter wrdev, iclass 24, count 2 2006.285.14:27:20.70#ibcon#first serial, iclass 24, count 2 2006.285.14:27:20.70#ibcon#enter sib2, iclass 24, count 2 2006.285.14:27:20.70#ibcon#flushed, iclass 24, count 2 2006.285.14:27:20.70#ibcon#about to write, iclass 24, count 2 2006.285.14:27:20.70#ibcon#wrote, iclass 24, count 2 2006.285.14:27:20.70#ibcon#about to read 3, iclass 24, count 2 2006.285.14:27:20.72#ibcon#read 3, iclass 24, count 2 2006.285.14:27:20.72#ibcon#about to read 4, iclass 24, count 2 2006.285.14:27:20.72#ibcon#read 4, iclass 24, count 2 2006.285.14:27:20.72#ibcon#about to read 5, iclass 24, count 2 2006.285.14:27:20.72#ibcon#read 5, iclass 24, count 2 2006.285.14:27:20.72#ibcon#about to read 6, iclass 24, count 2 2006.285.14:27:20.72#ibcon#read 6, iclass 24, count 2 2006.285.14:27:20.72#ibcon#end of sib2, iclass 24, count 2 2006.285.14:27:20.72#ibcon#*mode == 0, iclass 24, count 2 2006.285.14:27:20.72#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.14:27:20.72#ibcon#[25=AT03-07\r\n] 2006.285.14:27:20.72#ibcon#*before write, iclass 24, count 2 2006.285.14:27:20.72#ibcon#enter sib2, iclass 24, count 2 2006.285.14:27:20.72#ibcon#flushed, iclass 24, count 2 2006.285.14:27:20.72#ibcon#about to write, iclass 24, count 2 2006.285.14:27:20.72#ibcon#wrote, iclass 24, count 2 2006.285.14:27:20.72#ibcon#about to read 3, iclass 24, count 2 2006.285.14:27:20.75#ibcon#read 3, iclass 24, count 2 2006.285.14:27:20.75#ibcon#about to read 4, iclass 24, count 2 2006.285.14:27:20.75#ibcon#read 4, iclass 24, count 2 2006.285.14:27:20.75#ibcon#about to read 5, iclass 24, count 2 2006.285.14:27:20.75#ibcon#read 5, iclass 24, count 2 2006.285.14:27:20.75#ibcon#about to read 6, iclass 24, count 2 2006.285.14:27:20.75#ibcon#read 6, iclass 24, count 2 2006.285.14:27:20.75#ibcon#end of sib2, iclass 24, count 2 2006.285.14:27:20.75#ibcon#*after write, iclass 24, count 2 2006.285.14:27:20.75#ibcon#*before return 0, iclass 24, count 2 2006.285.14:27:20.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:27:20.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:27:20.75#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.14:27:20.75#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:20.75#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:27:20.87#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:27:21.11#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:27:21.11#ibcon#enter wrdev, iclass 24, count 0 2006.285.14:27:21.11#ibcon#first serial, iclass 24, count 0 2006.285.14:27:21.11#ibcon#enter sib2, iclass 24, count 0 2006.285.14:27:21.11#ibcon#flushed, iclass 24, count 0 2006.285.14:27:21.11#ibcon#about to write, iclass 24, count 0 2006.285.14:27:21.11#ibcon#wrote, iclass 24, count 0 2006.285.14:27:21.11#ibcon#about to read 3, iclass 24, count 0 2006.285.14:27:21.12#ibcon#read 3, iclass 24, count 0 2006.285.14:27:21.12#ibcon#about to read 4, iclass 24, count 0 2006.285.14:27:21.12#ibcon#read 4, iclass 24, count 0 2006.285.14:27:21.12#ibcon#about to read 5, iclass 24, count 0 2006.285.14:27:21.12#ibcon#read 5, iclass 24, count 0 2006.285.14:27:21.12#ibcon#about to read 6, iclass 24, count 0 2006.285.14:27:21.12#ibcon#read 6, iclass 24, count 0 2006.285.14:27:21.12#ibcon#end of sib2, iclass 24, count 0 2006.285.14:27:21.12#ibcon#*mode == 0, iclass 24, count 0 2006.285.14:27:21.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.14:27:21.12#ibcon#[25=USB\r\n] 2006.285.14:27:21.12#ibcon#*before write, iclass 24, count 0 2006.285.14:27:21.12#ibcon#enter sib2, iclass 24, count 0 2006.285.14:27:21.12#ibcon#flushed, iclass 24, count 0 2006.285.14:27:21.12#ibcon#about to write, iclass 24, count 0 2006.285.14:27:21.12#ibcon#wrote, iclass 24, count 0 2006.285.14:27:21.12#ibcon#about to read 3, iclass 24, count 0 2006.285.14:27:21.15#ibcon#read 3, iclass 24, count 0 2006.285.14:27:21.15#ibcon#about to read 4, iclass 24, count 0 2006.285.14:27:21.15#ibcon#read 4, iclass 24, count 0 2006.285.14:27:21.15#ibcon#about to read 5, iclass 24, count 0 2006.285.14:27:21.15#ibcon#read 5, iclass 24, count 0 2006.285.14:27:21.15#ibcon#about to read 6, iclass 24, count 0 2006.285.14:27:21.15#ibcon#read 6, iclass 24, count 0 2006.285.14:27:21.15#ibcon#end of sib2, iclass 24, count 0 2006.285.14:27:21.15#ibcon#*after write, iclass 24, count 0 2006.285.14:27:21.15#ibcon#*before return 0, iclass 24, count 0 2006.285.14:27:21.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:27:21.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:27:21.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.14:27:21.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.14:27:21.15$vck44/valo=4,624.99 2006.285.14:27:21.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.14:27:21.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.14:27:21.15#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:21.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:27:21.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:27:21.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:27:21.15#ibcon#enter wrdev, iclass 26, count 0 2006.285.14:27:21.15#ibcon#first serial, iclass 26, count 0 2006.285.14:27:21.15#ibcon#enter sib2, iclass 26, count 0 2006.285.14:27:21.15#ibcon#flushed, iclass 26, count 0 2006.285.14:27:21.15#ibcon#about to write, iclass 26, count 0 2006.285.14:27:21.15#ibcon#wrote, iclass 26, count 0 2006.285.14:27:21.15#ibcon#about to read 3, iclass 26, count 0 2006.285.14:27:21.17#ibcon#read 3, iclass 26, count 0 2006.285.14:27:21.17#ibcon#about to read 4, iclass 26, count 0 2006.285.14:27:21.17#ibcon#read 4, iclass 26, count 0 2006.285.14:27:21.17#ibcon#about to read 5, iclass 26, count 0 2006.285.14:27:21.17#ibcon#read 5, iclass 26, count 0 2006.285.14:27:21.17#ibcon#about to read 6, iclass 26, count 0 2006.285.14:27:21.17#ibcon#read 6, iclass 26, count 0 2006.285.14:27:21.17#ibcon#end of sib2, iclass 26, count 0 2006.285.14:27:21.17#ibcon#*mode == 0, iclass 26, count 0 2006.285.14:27:21.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.14:27:21.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.14:27:21.17#ibcon#*before write, iclass 26, count 0 2006.285.14:27:21.17#ibcon#enter sib2, iclass 26, count 0 2006.285.14:27:21.17#ibcon#flushed, iclass 26, count 0 2006.285.14:27:21.17#ibcon#about to write, iclass 26, count 0 2006.285.14:27:21.17#ibcon#wrote, iclass 26, count 0 2006.285.14:27:21.17#ibcon#about to read 3, iclass 26, count 0 2006.285.14:27:21.21#ibcon#read 3, iclass 26, count 0 2006.285.14:27:21.21#ibcon#about to read 4, iclass 26, count 0 2006.285.14:27:21.21#ibcon#read 4, iclass 26, count 0 2006.285.14:27:21.21#ibcon#about to read 5, iclass 26, count 0 2006.285.14:27:21.21#ibcon#read 5, iclass 26, count 0 2006.285.14:27:21.21#ibcon#about to read 6, iclass 26, count 0 2006.285.14:27:21.21#ibcon#read 6, iclass 26, count 0 2006.285.14:27:21.21#ibcon#end of sib2, iclass 26, count 0 2006.285.14:27:21.21#ibcon#*after write, iclass 26, count 0 2006.285.14:27:21.21#ibcon#*before return 0, iclass 26, count 0 2006.285.14:27:21.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:27:21.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:27:21.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.14:27:21.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.14:27:21.21$vck44/va=4,6 2006.285.14:27:21.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.14:27:21.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.14:27:21.21#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:21.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:27:21.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:27:21.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:27:21.27#ibcon#enter wrdev, iclass 28, count 2 2006.285.14:27:21.27#ibcon#first serial, iclass 28, count 2 2006.285.14:27:21.27#ibcon#enter sib2, iclass 28, count 2 2006.285.14:27:21.27#ibcon#flushed, iclass 28, count 2 2006.285.14:27:21.27#ibcon#about to write, iclass 28, count 2 2006.285.14:27:21.27#ibcon#wrote, iclass 28, count 2 2006.285.14:27:21.27#ibcon#about to read 3, iclass 28, count 2 2006.285.14:27:21.29#ibcon#read 3, iclass 28, count 2 2006.285.14:27:21.29#ibcon#about to read 4, iclass 28, count 2 2006.285.14:27:21.29#ibcon#read 4, iclass 28, count 2 2006.285.14:27:21.29#ibcon#about to read 5, iclass 28, count 2 2006.285.14:27:21.29#ibcon#read 5, iclass 28, count 2 2006.285.14:27:21.29#ibcon#about to read 6, iclass 28, count 2 2006.285.14:27:21.29#ibcon#read 6, iclass 28, count 2 2006.285.14:27:21.29#ibcon#end of sib2, iclass 28, count 2 2006.285.14:27:21.29#ibcon#*mode == 0, iclass 28, count 2 2006.285.14:27:21.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.14:27:21.29#ibcon#[25=AT04-06\r\n] 2006.285.14:27:21.29#ibcon#*before write, iclass 28, count 2 2006.285.14:27:21.29#ibcon#enter sib2, iclass 28, count 2 2006.285.14:27:21.29#ibcon#flushed, iclass 28, count 2 2006.285.14:27:21.29#ibcon#about to write, iclass 28, count 2 2006.285.14:27:21.29#ibcon#wrote, iclass 28, count 2 2006.285.14:27:21.29#ibcon#about to read 3, iclass 28, count 2 2006.285.14:27:21.32#ibcon#read 3, iclass 28, count 2 2006.285.14:27:21.32#ibcon#about to read 4, iclass 28, count 2 2006.285.14:27:21.32#ibcon#read 4, iclass 28, count 2 2006.285.14:27:21.32#ibcon#about to read 5, iclass 28, count 2 2006.285.14:27:21.32#ibcon#read 5, iclass 28, count 2 2006.285.14:27:21.32#ibcon#about to read 6, iclass 28, count 2 2006.285.14:27:21.32#ibcon#read 6, iclass 28, count 2 2006.285.14:27:21.32#ibcon#end of sib2, iclass 28, count 2 2006.285.14:27:21.32#ibcon#*after write, iclass 28, count 2 2006.285.14:27:21.32#ibcon#*before return 0, iclass 28, count 2 2006.285.14:27:21.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:27:21.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:27:21.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.14:27:21.32#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:21.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:27:21.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:27:21.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:27:21.44#ibcon#enter wrdev, iclass 28, count 0 2006.285.14:27:21.44#ibcon#first serial, iclass 28, count 0 2006.285.14:27:21.44#ibcon#enter sib2, iclass 28, count 0 2006.285.14:27:21.44#ibcon#flushed, iclass 28, count 0 2006.285.14:27:21.44#ibcon#about to write, iclass 28, count 0 2006.285.14:27:21.44#ibcon#wrote, iclass 28, count 0 2006.285.14:27:21.44#ibcon#about to read 3, iclass 28, count 0 2006.285.14:27:21.46#ibcon#read 3, iclass 28, count 0 2006.285.14:27:21.46#ibcon#about to read 4, iclass 28, count 0 2006.285.14:27:21.46#ibcon#read 4, iclass 28, count 0 2006.285.14:27:21.46#ibcon#about to read 5, iclass 28, count 0 2006.285.14:27:21.46#ibcon#read 5, iclass 28, count 0 2006.285.14:27:21.46#ibcon#about to read 6, iclass 28, count 0 2006.285.14:27:21.46#ibcon#read 6, iclass 28, count 0 2006.285.14:27:21.46#ibcon#end of sib2, iclass 28, count 0 2006.285.14:27:21.46#ibcon#*mode == 0, iclass 28, count 0 2006.285.14:27:21.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.14:27:21.46#ibcon#[25=USB\r\n] 2006.285.14:27:21.46#ibcon#*before write, iclass 28, count 0 2006.285.14:27:21.46#ibcon#enter sib2, iclass 28, count 0 2006.285.14:27:21.46#ibcon#flushed, iclass 28, count 0 2006.285.14:27:21.46#ibcon#about to write, iclass 28, count 0 2006.285.14:27:21.46#ibcon#wrote, iclass 28, count 0 2006.285.14:27:21.46#ibcon#about to read 3, iclass 28, count 0 2006.285.14:27:21.49#ibcon#read 3, iclass 28, count 0 2006.285.14:27:21.49#ibcon#about to read 4, iclass 28, count 0 2006.285.14:27:21.49#ibcon#read 4, iclass 28, count 0 2006.285.14:27:21.49#ibcon#about to read 5, iclass 28, count 0 2006.285.14:27:21.49#ibcon#read 5, iclass 28, count 0 2006.285.14:27:21.49#ibcon#about to read 6, iclass 28, count 0 2006.285.14:27:21.49#ibcon#read 6, iclass 28, count 0 2006.285.14:27:21.49#ibcon#end of sib2, iclass 28, count 0 2006.285.14:27:21.49#ibcon#*after write, iclass 28, count 0 2006.285.14:27:21.49#ibcon#*before return 0, iclass 28, count 0 2006.285.14:27:21.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:27:21.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:27:21.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.14:27:21.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.14:27:21.49$vck44/valo=5,734.99 2006.285.14:27:21.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.14:27:21.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.14:27:21.49#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:21.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:27:21.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:27:21.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:27:21.49#ibcon#enter wrdev, iclass 30, count 0 2006.285.14:27:21.49#ibcon#first serial, iclass 30, count 0 2006.285.14:27:21.49#ibcon#enter sib2, iclass 30, count 0 2006.285.14:27:21.49#ibcon#flushed, iclass 30, count 0 2006.285.14:27:21.49#ibcon#about to write, iclass 30, count 0 2006.285.14:27:21.49#ibcon#wrote, iclass 30, count 0 2006.285.14:27:21.49#ibcon#about to read 3, iclass 30, count 0 2006.285.14:27:21.51#ibcon#read 3, iclass 30, count 0 2006.285.14:27:21.51#ibcon#about to read 4, iclass 30, count 0 2006.285.14:27:21.51#ibcon#read 4, iclass 30, count 0 2006.285.14:27:21.51#ibcon#about to read 5, iclass 30, count 0 2006.285.14:27:21.51#ibcon#read 5, iclass 30, count 0 2006.285.14:27:21.51#ibcon#about to read 6, iclass 30, count 0 2006.285.14:27:21.51#ibcon#read 6, iclass 30, count 0 2006.285.14:27:21.51#ibcon#end of sib2, iclass 30, count 0 2006.285.14:27:21.51#ibcon#*mode == 0, iclass 30, count 0 2006.285.14:27:21.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.14:27:21.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.14:27:21.51#ibcon#*before write, iclass 30, count 0 2006.285.14:27:21.51#ibcon#enter sib2, iclass 30, count 0 2006.285.14:27:21.51#ibcon#flushed, iclass 30, count 0 2006.285.14:27:21.51#ibcon#about to write, iclass 30, count 0 2006.285.14:27:21.51#ibcon#wrote, iclass 30, count 0 2006.285.14:27:21.51#ibcon#about to read 3, iclass 30, count 0 2006.285.14:27:21.55#ibcon#read 3, iclass 30, count 0 2006.285.14:27:21.55#ibcon#about to read 4, iclass 30, count 0 2006.285.14:27:21.55#ibcon#read 4, iclass 30, count 0 2006.285.14:27:21.55#ibcon#about to read 5, iclass 30, count 0 2006.285.14:27:21.55#ibcon#read 5, iclass 30, count 0 2006.285.14:27:21.55#ibcon#about to read 6, iclass 30, count 0 2006.285.14:27:21.55#ibcon#read 6, iclass 30, count 0 2006.285.14:27:21.55#ibcon#end of sib2, iclass 30, count 0 2006.285.14:27:21.55#ibcon#*after write, iclass 30, count 0 2006.285.14:27:21.55#ibcon#*before return 0, iclass 30, count 0 2006.285.14:27:21.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:27:21.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:27:21.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.14:27:21.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.14:27:21.55$vck44/va=5,3 2006.285.14:27:21.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.14:27:21.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.14:27:21.55#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:21.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:27:21.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:27:21.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:27:21.61#ibcon#enter wrdev, iclass 32, count 2 2006.285.14:27:21.61#ibcon#first serial, iclass 32, count 2 2006.285.14:27:21.61#ibcon#enter sib2, iclass 32, count 2 2006.285.14:27:21.61#ibcon#flushed, iclass 32, count 2 2006.285.14:27:21.61#ibcon#about to write, iclass 32, count 2 2006.285.14:27:21.61#ibcon#wrote, iclass 32, count 2 2006.285.14:27:21.61#ibcon#about to read 3, iclass 32, count 2 2006.285.14:27:21.63#ibcon#read 3, iclass 32, count 2 2006.285.14:27:21.63#ibcon#about to read 4, iclass 32, count 2 2006.285.14:27:21.63#ibcon#read 4, iclass 32, count 2 2006.285.14:27:21.63#ibcon#about to read 5, iclass 32, count 2 2006.285.14:27:21.63#ibcon#read 5, iclass 32, count 2 2006.285.14:27:21.63#ibcon#about to read 6, iclass 32, count 2 2006.285.14:27:21.63#ibcon#read 6, iclass 32, count 2 2006.285.14:27:21.63#ibcon#end of sib2, iclass 32, count 2 2006.285.14:27:21.63#ibcon#*mode == 0, iclass 32, count 2 2006.285.14:27:21.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.14:27:21.63#ibcon#[25=AT05-03\r\n] 2006.285.14:27:21.63#ibcon#*before write, iclass 32, count 2 2006.285.14:27:21.63#ibcon#enter sib2, iclass 32, count 2 2006.285.14:27:21.63#ibcon#flushed, iclass 32, count 2 2006.285.14:27:21.63#ibcon#about to write, iclass 32, count 2 2006.285.14:27:21.63#ibcon#wrote, iclass 32, count 2 2006.285.14:27:21.63#ibcon#about to read 3, iclass 32, count 2 2006.285.14:27:21.66#ibcon#read 3, iclass 32, count 2 2006.285.14:27:21.66#ibcon#about to read 4, iclass 32, count 2 2006.285.14:27:21.66#ibcon#read 4, iclass 32, count 2 2006.285.14:27:21.66#ibcon#about to read 5, iclass 32, count 2 2006.285.14:27:21.66#ibcon#read 5, iclass 32, count 2 2006.285.14:27:21.66#ibcon#about to read 6, iclass 32, count 2 2006.285.14:27:21.66#ibcon#read 6, iclass 32, count 2 2006.285.14:27:21.66#ibcon#end of sib2, iclass 32, count 2 2006.285.14:27:21.66#ibcon#*after write, iclass 32, count 2 2006.285.14:27:21.66#ibcon#*before return 0, iclass 32, count 2 2006.285.14:27:21.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:27:21.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:27:21.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.14:27:21.66#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:21.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:27:21.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:27:21.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:27:21.78#ibcon#enter wrdev, iclass 32, count 0 2006.285.14:27:21.78#ibcon#first serial, iclass 32, count 0 2006.285.14:27:21.78#ibcon#enter sib2, iclass 32, count 0 2006.285.14:27:21.78#ibcon#flushed, iclass 32, count 0 2006.285.14:27:21.78#ibcon#about to write, iclass 32, count 0 2006.285.14:27:21.78#ibcon#wrote, iclass 32, count 0 2006.285.14:27:21.78#ibcon#about to read 3, iclass 32, count 0 2006.285.14:27:21.80#ibcon#read 3, iclass 32, count 0 2006.285.14:27:21.80#ibcon#about to read 4, iclass 32, count 0 2006.285.14:27:21.80#ibcon#read 4, iclass 32, count 0 2006.285.14:27:21.80#ibcon#about to read 5, iclass 32, count 0 2006.285.14:27:21.80#ibcon#read 5, iclass 32, count 0 2006.285.14:27:21.80#ibcon#about to read 6, iclass 32, count 0 2006.285.14:27:21.80#ibcon#read 6, iclass 32, count 0 2006.285.14:27:21.80#ibcon#end of sib2, iclass 32, count 0 2006.285.14:27:21.80#ibcon#*mode == 0, iclass 32, count 0 2006.285.14:27:21.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.14:27:21.80#ibcon#[25=USB\r\n] 2006.285.14:27:21.80#ibcon#*before write, iclass 32, count 0 2006.285.14:27:21.80#ibcon#enter sib2, iclass 32, count 0 2006.285.14:27:21.80#ibcon#flushed, iclass 32, count 0 2006.285.14:27:21.80#ibcon#about to write, iclass 32, count 0 2006.285.14:27:21.80#ibcon#wrote, iclass 32, count 0 2006.285.14:27:21.80#ibcon#about to read 3, iclass 32, count 0 2006.285.14:27:21.83#ibcon#read 3, iclass 32, count 0 2006.285.14:27:21.83#ibcon#about to read 4, iclass 32, count 0 2006.285.14:27:21.83#ibcon#read 4, iclass 32, count 0 2006.285.14:27:21.83#ibcon#about to read 5, iclass 32, count 0 2006.285.14:27:21.83#ibcon#read 5, iclass 32, count 0 2006.285.14:27:21.83#ibcon#about to read 6, iclass 32, count 0 2006.285.14:27:21.83#ibcon#read 6, iclass 32, count 0 2006.285.14:27:21.83#ibcon#end of sib2, iclass 32, count 0 2006.285.14:27:21.83#ibcon#*after write, iclass 32, count 0 2006.285.14:27:21.83#ibcon#*before return 0, iclass 32, count 0 2006.285.14:27:21.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:27:21.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:27:21.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.14:27:21.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.14:27:21.83$vck44/valo=6,814.99 2006.285.14:27:21.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.14:27:21.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.14:27:21.83#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:21.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:27:21.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:27:21.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:27:21.83#ibcon#enter wrdev, iclass 34, count 0 2006.285.14:27:21.83#ibcon#first serial, iclass 34, count 0 2006.285.14:27:21.83#ibcon#enter sib2, iclass 34, count 0 2006.285.14:27:21.83#ibcon#flushed, iclass 34, count 0 2006.285.14:27:21.83#ibcon#about to write, iclass 34, count 0 2006.285.14:27:21.83#ibcon#wrote, iclass 34, count 0 2006.285.14:27:21.83#ibcon#about to read 3, iclass 34, count 0 2006.285.14:27:21.85#ibcon#read 3, iclass 34, count 0 2006.285.14:27:21.85#ibcon#about to read 4, iclass 34, count 0 2006.285.14:27:21.85#ibcon#read 4, iclass 34, count 0 2006.285.14:27:21.85#ibcon#about to read 5, iclass 34, count 0 2006.285.14:27:21.85#ibcon#read 5, iclass 34, count 0 2006.285.14:27:21.85#ibcon#about to read 6, iclass 34, count 0 2006.285.14:27:21.85#ibcon#read 6, iclass 34, count 0 2006.285.14:27:21.85#ibcon#end of sib2, iclass 34, count 0 2006.285.14:27:21.85#ibcon#*mode == 0, iclass 34, count 0 2006.285.14:27:21.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.14:27:21.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.14:27:21.85#ibcon#*before write, iclass 34, count 0 2006.285.14:27:21.85#ibcon#enter sib2, iclass 34, count 0 2006.285.14:27:21.85#ibcon#flushed, iclass 34, count 0 2006.285.14:27:21.85#ibcon#about to write, iclass 34, count 0 2006.285.14:27:21.85#ibcon#wrote, iclass 34, count 0 2006.285.14:27:21.85#ibcon#about to read 3, iclass 34, count 0 2006.285.14:27:21.89#ibcon#read 3, iclass 34, count 0 2006.285.14:27:21.89#ibcon#about to read 4, iclass 34, count 0 2006.285.14:27:21.89#ibcon#read 4, iclass 34, count 0 2006.285.14:27:21.89#ibcon#about to read 5, iclass 34, count 0 2006.285.14:27:21.89#ibcon#read 5, iclass 34, count 0 2006.285.14:27:21.89#ibcon#about to read 6, iclass 34, count 0 2006.285.14:27:21.89#ibcon#read 6, iclass 34, count 0 2006.285.14:27:21.89#ibcon#end of sib2, iclass 34, count 0 2006.285.14:27:21.89#ibcon#*after write, iclass 34, count 0 2006.285.14:27:21.89#ibcon#*before return 0, iclass 34, count 0 2006.285.14:27:21.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:27:21.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:27:21.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.14:27:21.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.14:27:21.89$vck44/va=6,4 2006.285.14:27:21.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.14:27:21.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.14:27:21.89#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:21.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.14:27:21.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.14:27:21.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.14:27:21.95#ibcon#enter wrdev, iclass 36, count 2 2006.285.14:27:21.95#ibcon#first serial, iclass 36, count 2 2006.285.14:27:21.95#ibcon#enter sib2, iclass 36, count 2 2006.285.14:27:21.95#ibcon#flushed, iclass 36, count 2 2006.285.14:27:21.95#ibcon#about to write, iclass 36, count 2 2006.285.14:27:21.95#ibcon#wrote, iclass 36, count 2 2006.285.14:27:21.95#ibcon#about to read 3, iclass 36, count 2 2006.285.14:27:21.97#ibcon#read 3, iclass 36, count 2 2006.285.14:27:21.97#ibcon#about to read 4, iclass 36, count 2 2006.285.14:27:21.97#ibcon#read 4, iclass 36, count 2 2006.285.14:27:21.97#ibcon#about to read 5, iclass 36, count 2 2006.285.14:27:21.97#ibcon#read 5, iclass 36, count 2 2006.285.14:27:21.97#ibcon#about to read 6, iclass 36, count 2 2006.285.14:27:21.97#ibcon#read 6, iclass 36, count 2 2006.285.14:27:21.97#ibcon#end of sib2, iclass 36, count 2 2006.285.14:27:21.97#ibcon#*mode == 0, iclass 36, count 2 2006.285.14:27:21.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.14:27:21.97#ibcon#[25=AT06-04\r\n] 2006.285.14:27:21.97#ibcon#*before write, iclass 36, count 2 2006.285.14:27:21.97#ibcon#enter sib2, iclass 36, count 2 2006.285.14:27:21.97#ibcon#flushed, iclass 36, count 2 2006.285.14:27:21.97#ibcon#about to write, iclass 36, count 2 2006.285.14:27:21.97#ibcon#wrote, iclass 36, count 2 2006.285.14:27:21.97#ibcon#about to read 3, iclass 36, count 2 2006.285.14:27:22.00#ibcon#read 3, iclass 36, count 2 2006.285.14:27:22.00#ibcon#about to read 4, iclass 36, count 2 2006.285.14:27:22.00#ibcon#read 4, iclass 36, count 2 2006.285.14:27:22.00#ibcon#about to read 5, iclass 36, count 2 2006.285.14:27:22.00#ibcon#read 5, iclass 36, count 2 2006.285.14:27:22.00#ibcon#about to read 6, iclass 36, count 2 2006.285.14:27:22.00#ibcon#read 6, iclass 36, count 2 2006.285.14:27:22.00#ibcon#end of sib2, iclass 36, count 2 2006.285.14:27:22.00#ibcon#*after write, iclass 36, count 2 2006.285.14:27:22.00#ibcon#*before return 0, iclass 36, count 2 2006.285.14:27:22.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.14:27:22.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.14:27:22.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.14:27:22.00#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:22.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.14:27:22.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.14:27:22.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.14:27:22.12#ibcon#enter wrdev, iclass 36, count 0 2006.285.14:27:22.12#ibcon#first serial, iclass 36, count 0 2006.285.14:27:22.12#ibcon#enter sib2, iclass 36, count 0 2006.285.14:27:22.12#ibcon#flushed, iclass 36, count 0 2006.285.14:27:22.12#ibcon#about to write, iclass 36, count 0 2006.285.14:27:22.12#ibcon#wrote, iclass 36, count 0 2006.285.14:27:22.12#ibcon#about to read 3, iclass 36, count 0 2006.285.14:27:22.14#ibcon#read 3, iclass 36, count 0 2006.285.14:27:22.14#ibcon#about to read 4, iclass 36, count 0 2006.285.14:27:22.14#ibcon#read 4, iclass 36, count 0 2006.285.14:27:22.14#ibcon#about to read 5, iclass 36, count 0 2006.285.14:27:22.14#ibcon#read 5, iclass 36, count 0 2006.285.14:27:22.14#ibcon#about to read 6, iclass 36, count 0 2006.285.14:27:22.14#ibcon#read 6, iclass 36, count 0 2006.285.14:27:22.14#ibcon#end of sib2, iclass 36, count 0 2006.285.14:27:22.14#ibcon#*mode == 0, iclass 36, count 0 2006.285.14:27:22.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.14:27:22.14#ibcon#[25=USB\r\n] 2006.285.14:27:22.14#ibcon#*before write, iclass 36, count 0 2006.285.14:27:22.14#ibcon#enter sib2, iclass 36, count 0 2006.285.14:27:22.14#ibcon#flushed, iclass 36, count 0 2006.285.14:27:22.14#ibcon#about to write, iclass 36, count 0 2006.285.14:27:22.14#ibcon#wrote, iclass 36, count 0 2006.285.14:27:22.14#ibcon#about to read 3, iclass 36, count 0 2006.285.14:27:22.17#ibcon#read 3, iclass 36, count 0 2006.285.14:27:22.17#ibcon#about to read 4, iclass 36, count 0 2006.285.14:27:22.17#ibcon#read 4, iclass 36, count 0 2006.285.14:27:22.17#ibcon#about to read 5, iclass 36, count 0 2006.285.14:27:22.17#ibcon#read 5, iclass 36, count 0 2006.285.14:27:22.17#ibcon#about to read 6, iclass 36, count 0 2006.285.14:27:22.17#ibcon#read 6, iclass 36, count 0 2006.285.14:27:22.17#ibcon#end of sib2, iclass 36, count 0 2006.285.14:27:22.17#ibcon#*after write, iclass 36, count 0 2006.285.14:27:22.17#ibcon#*before return 0, iclass 36, count 0 2006.285.14:27:22.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.14:27:22.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.14:27:22.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.14:27:22.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.14:27:22.17$vck44/valo=7,864.99 2006.285.14:27:22.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.14:27:22.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.14:27:22.17#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:22.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:27:22.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:27:22.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:27:22.17#ibcon#enter wrdev, iclass 38, count 0 2006.285.14:27:22.17#ibcon#first serial, iclass 38, count 0 2006.285.14:27:22.17#ibcon#enter sib2, iclass 38, count 0 2006.285.14:27:22.17#ibcon#flushed, iclass 38, count 0 2006.285.14:27:22.17#ibcon#about to write, iclass 38, count 0 2006.285.14:27:22.17#ibcon#wrote, iclass 38, count 0 2006.285.14:27:22.17#ibcon#about to read 3, iclass 38, count 0 2006.285.14:27:22.19#ibcon#read 3, iclass 38, count 0 2006.285.14:27:22.54#ibcon#about to read 4, iclass 38, count 0 2006.285.14:27:22.54#ibcon#read 4, iclass 38, count 0 2006.285.14:27:22.54#ibcon#about to read 5, iclass 38, count 0 2006.285.14:27:22.54#ibcon#read 5, iclass 38, count 0 2006.285.14:27:22.54#ibcon#about to read 6, iclass 38, count 0 2006.285.14:27:22.54#ibcon#read 6, iclass 38, count 0 2006.285.14:27:22.54#ibcon#end of sib2, iclass 38, count 0 2006.285.14:27:22.54#ibcon#*mode == 0, iclass 38, count 0 2006.285.14:27:22.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.14:27:22.54#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.14:27:22.54#ibcon#*before write, iclass 38, count 0 2006.285.14:27:22.54#ibcon#enter sib2, iclass 38, count 0 2006.285.14:27:22.54#ibcon#flushed, iclass 38, count 0 2006.285.14:27:22.54#ibcon#about to write, iclass 38, count 0 2006.285.14:27:22.54#ibcon#wrote, iclass 38, count 0 2006.285.14:27:22.54#ibcon#about to read 3, iclass 38, count 0 2006.285.14:27:22.58#ibcon#read 3, iclass 38, count 0 2006.285.14:27:22.58#ibcon#about to read 4, iclass 38, count 0 2006.285.14:27:22.58#ibcon#read 4, iclass 38, count 0 2006.285.14:27:22.58#ibcon#about to read 5, iclass 38, count 0 2006.285.14:27:22.58#ibcon#read 5, iclass 38, count 0 2006.285.14:27:22.58#ibcon#about to read 6, iclass 38, count 0 2006.285.14:27:22.58#ibcon#read 6, iclass 38, count 0 2006.285.14:27:22.58#ibcon#end of sib2, iclass 38, count 0 2006.285.14:27:22.58#ibcon#*after write, iclass 38, count 0 2006.285.14:27:22.58#ibcon#*before return 0, iclass 38, count 0 2006.285.14:27:22.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:27:22.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:27:22.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.14:27:22.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.14:27:22.58$vck44/va=7,4 2006.285.14:27:22.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.14:27:22.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.14:27:22.58#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:22.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:27:22.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:27:22.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:27:22.58#ibcon#enter wrdev, iclass 40, count 2 2006.285.14:27:22.58#ibcon#first serial, iclass 40, count 2 2006.285.14:27:22.58#ibcon#enter sib2, iclass 40, count 2 2006.285.14:27:22.58#ibcon#flushed, iclass 40, count 2 2006.285.14:27:22.58#ibcon#about to write, iclass 40, count 2 2006.285.14:27:22.58#ibcon#wrote, iclass 40, count 2 2006.285.14:27:22.58#ibcon#about to read 3, iclass 40, count 2 2006.285.14:27:22.60#ibcon#read 3, iclass 40, count 2 2006.285.14:27:22.60#ibcon#about to read 4, iclass 40, count 2 2006.285.14:27:22.60#ibcon#read 4, iclass 40, count 2 2006.285.14:27:22.60#ibcon#about to read 5, iclass 40, count 2 2006.285.14:27:22.60#ibcon#read 5, iclass 40, count 2 2006.285.14:27:22.60#ibcon#about to read 6, iclass 40, count 2 2006.285.14:27:22.60#ibcon#read 6, iclass 40, count 2 2006.285.14:27:22.60#ibcon#end of sib2, iclass 40, count 2 2006.285.14:27:22.60#ibcon#*mode == 0, iclass 40, count 2 2006.285.14:27:22.60#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.14:27:22.60#ibcon#[25=AT07-04\r\n] 2006.285.14:27:22.60#ibcon#*before write, iclass 40, count 2 2006.285.14:27:22.60#ibcon#enter sib2, iclass 40, count 2 2006.285.14:27:22.60#ibcon#flushed, iclass 40, count 2 2006.285.14:27:22.60#ibcon#about to write, iclass 40, count 2 2006.285.14:27:22.60#ibcon#wrote, iclass 40, count 2 2006.285.14:27:22.60#ibcon#about to read 3, iclass 40, count 2 2006.285.14:27:22.63#ibcon#read 3, iclass 40, count 2 2006.285.14:27:22.63#ibcon#about to read 4, iclass 40, count 2 2006.285.14:27:22.63#ibcon#read 4, iclass 40, count 2 2006.285.14:27:22.63#ibcon#about to read 5, iclass 40, count 2 2006.285.14:27:22.63#ibcon#read 5, iclass 40, count 2 2006.285.14:27:22.63#ibcon#about to read 6, iclass 40, count 2 2006.285.14:27:22.63#ibcon#read 6, iclass 40, count 2 2006.285.14:27:22.63#ibcon#end of sib2, iclass 40, count 2 2006.285.14:27:22.63#ibcon#*after write, iclass 40, count 2 2006.285.14:27:22.63#ibcon#*before return 0, iclass 40, count 2 2006.285.14:27:22.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:27:22.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:27:22.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.14:27:22.63#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:22.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:27:22.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:27:22.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:27:22.75#ibcon#enter wrdev, iclass 40, count 0 2006.285.14:27:22.75#ibcon#first serial, iclass 40, count 0 2006.285.14:27:22.75#ibcon#enter sib2, iclass 40, count 0 2006.285.14:27:22.75#ibcon#flushed, iclass 40, count 0 2006.285.14:27:22.75#ibcon#about to write, iclass 40, count 0 2006.285.14:27:22.75#ibcon#wrote, iclass 40, count 0 2006.285.14:27:22.75#ibcon#about to read 3, iclass 40, count 0 2006.285.14:27:22.77#ibcon#read 3, iclass 40, count 0 2006.285.14:27:22.77#ibcon#about to read 4, iclass 40, count 0 2006.285.14:27:22.77#ibcon#read 4, iclass 40, count 0 2006.285.14:27:22.77#ibcon#about to read 5, iclass 40, count 0 2006.285.14:27:22.77#ibcon#read 5, iclass 40, count 0 2006.285.14:27:22.77#ibcon#about to read 6, iclass 40, count 0 2006.285.14:27:22.77#ibcon#read 6, iclass 40, count 0 2006.285.14:27:22.77#ibcon#end of sib2, iclass 40, count 0 2006.285.14:27:22.77#ibcon#*mode == 0, iclass 40, count 0 2006.285.14:27:22.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.14:27:22.77#ibcon#[25=USB\r\n] 2006.285.14:27:22.77#ibcon#*before write, iclass 40, count 0 2006.285.14:27:22.77#ibcon#enter sib2, iclass 40, count 0 2006.285.14:27:22.77#ibcon#flushed, iclass 40, count 0 2006.285.14:27:22.77#ibcon#about to write, iclass 40, count 0 2006.285.14:27:22.77#ibcon#wrote, iclass 40, count 0 2006.285.14:27:22.77#ibcon#about to read 3, iclass 40, count 0 2006.285.14:27:22.80#ibcon#read 3, iclass 40, count 0 2006.285.14:27:22.80#ibcon#about to read 4, iclass 40, count 0 2006.285.14:27:22.80#ibcon#read 4, iclass 40, count 0 2006.285.14:27:22.80#ibcon#about to read 5, iclass 40, count 0 2006.285.14:27:22.80#ibcon#read 5, iclass 40, count 0 2006.285.14:27:22.80#ibcon#about to read 6, iclass 40, count 0 2006.285.14:27:22.80#ibcon#read 6, iclass 40, count 0 2006.285.14:27:22.80#ibcon#end of sib2, iclass 40, count 0 2006.285.14:27:22.80#ibcon#*after write, iclass 40, count 0 2006.285.14:27:22.80#ibcon#*before return 0, iclass 40, count 0 2006.285.14:27:22.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:27:22.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:27:22.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.14:27:22.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.14:27:22.80$vck44/valo=8,884.99 2006.285.14:27:22.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.14:27:22.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.14:27:22.80#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:22.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:27:22.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:27:22.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:27:22.80#ibcon#enter wrdev, iclass 4, count 0 2006.285.14:27:22.80#ibcon#first serial, iclass 4, count 0 2006.285.14:27:22.80#ibcon#enter sib2, iclass 4, count 0 2006.285.14:27:22.80#ibcon#flushed, iclass 4, count 0 2006.285.14:27:22.80#ibcon#about to write, iclass 4, count 0 2006.285.14:27:22.80#ibcon#wrote, iclass 4, count 0 2006.285.14:27:22.80#ibcon#about to read 3, iclass 4, count 0 2006.285.14:27:22.82#ibcon#read 3, iclass 4, count 0 2006.285.14:27:22.82#ibcon#about to read 4, iclass 4, count 0 2006.285.14:27:22.82#ibcon#read 4, iclass 4, count 0 2006.285.14:27:22.82#ibcon#about to read 5, iclass 4, count 0 2006.285.14:27:22.82#ibcon#read 5, iclass 4, count 0 2006.285.14:27:22.82#ibcon#about to read 6, iclass 4, count 0 2006.285.14:27:22.82#ibcon#read 6, iclass 4, count 0 2006.285.14:27:22.82#ibcon#end of sib2, iclass 4, count 0 2006.285.14:27:22.82#ibcon#*mode == 0, iclass 4, count 0 2006.285.14:27:22.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.14:27:22.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.14:27:22.82#ibcon#*before write, iclass 4, count 0 2006.285.14:27:22.82#ibcon#enter sib2, iclass 4, count 0 2006.285.14:27:22.82#ibcon#flushed, iclass 4, count 0 2006.285.14:27:22.82#ibcon#about to write, iclass 4, count 0 2006.285.14:27:22.82#ibcon#wrote, iclass 4, count 0 2006.285.14:27:22.82#ibcon#about to read 3, iclass 4, count 0 2006.285.14:27:22.86#ibcon#read 3, iclass 4, count 0 2006.285.14:27:22.86#ibcon#about to read 4, iclass 4, count 0 2006.285.14:27:22.86#ibcon#read 4, iclass 4, count 0 2006.285.14:27:22.86#ibcon#about to read 5, iclass 4, count 0 2006.285.14:27:22.86#ibcon#read 5, iclass 4, count 0 2006.285.14:27:22.86#ibcon#about to read 6, iclass 4, count 0 2006.285.14:27:22.86#ibcon#read 6, iclass 4, count 0 2006.285.14:27:22.86#ibcon#end of sib2, iclass 4, count 0 2006.285.14:27:22.86#ibcon#*after write, iclass 4, count 0 2006.285.14:27:22.86#ibcon#*before return 0, iclass 4, count 0 2006.285.14:27:22.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:27:22.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:27:22.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.14:27:22.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.14:27:22.86$vck44/va=8,3 2006.285.14:27:22.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.14:27:22.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.14:27:22.86#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:22.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:27:22.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:27:22.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:27:22.92#ibcon#enter wrdev, iclass 6, count 2 2006.285.14:27:22.92#ibcon#first serial, iclass 6, count 2 2006.285.14:27:22.92#ibcon#enter sib2, iclass 6, count 2 2006.285.14:27:22.92#ibcon#flushed, iclass 6, count 2 2006.285.14:27:22.92#ibcon#about to write, iclass 6, count 2 2006.285.14:27:22.92#ibcon#wrote, iclass 6, count 2 2006.285.14:27:22.92#ibcon#about to read 3, iclass 6, count 2 2006.285.14:27:22.94#ibcon#read 3, iclass 6, count 2 2006.285.14:27:22.94#ibcon#about to read 4, iclass 6, count 2 2006.285.14:27:22.94#ibcon#read 4, iclass 6, count 2 2006.285.14:27:22.94#ibcon#about to read 5, iclass 6, count 2 2006.285.14:27:22.94#ibcon#read 5, iclass 6, count 2 2006.285.14:27:22.94#ibcon#about to read 6, iclass 6, count 2 2006.285.14:27:22.94#ibcon#read 6, iclass 6, count 2 2006.285.14:27:22.94#ibcon#end of sib2, iclass 6, count 2 2006.285.14:27:22.94#ibcon#*mode == 0, iclass 6, count 2 2006.285.14:27:22.94#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.14:27:22.94#ibcon#[25=AT08-03\r\n] 2006.285.14:27:22.94#ibcon#*before write, iclass 6, count 2 2006.285.14:27:22.94#ibcon#enter sib2, iclass 6, count 2 2006.285.14:27:22.94#ibcon#flushed, iclass 6, count 2 2006.285.14:27:22.94#ibcon#about to write, iclass 6, count 2 2006.285.14:27:22.94#ibcon#wrote, iclass 6, count 2 2006.285.14:27:22.94#ibcon#about to read 3, iclass 6, count 2 2006.285.14:27:22.97#ibcon#read 3, iclass 6, count 2 2006.285.14:27:22.97#ibcon#about to read 4, iclass 6, count 2 2006.285.14:27:22.97#ibcon#read 4, iclass 6, count 2 2006.285.14:27:22.97#ibcon#about to read 5, iclass 6, count 2 2006.285.14:27:22.97#ibcon#read 5, iclass 6, count 2 2006.285.14:27:22.97#ibcon#about to read 6, iclass 6, count 2 2006.285.14:27:22.97#ibcon#read 6, iclass 6, count 2 2006.285.14:27:22.97#ibcon#end of sib2, iclass 6, count 2 2006.285.14:27:22.97#ibcon#*after write, iclass 6, count 2 2006.285.14:27:22.97#ibcon#*before return 0, iclass 6, count 2 2006.285.14:27:22.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:27:22.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:27:22.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.14:27:22.97#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:22.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:27:23.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:27:23.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:27:23.09#ibcon#enter wrdev, iclass 6, count 0 2006.285.14:27:23.09#ibcon#first serial, iclass 6, count 0 2006.285.14:27:23.09#ibcon#enter sib2, iclass 6, count 0 2006.285.14:27:23.09#ibcon#flushed, iclass 6, count 0 2006.285.14:27:23.09#ibcon#about to write, iclass 6, count 0 2006.285.14:27:23.09#ibcon#wrote, iclass 6, count 0 2006.285.14:27:23.09#ibcon#about to read 3, iclass 6, count 0 2006.285.14:27:23.11#ibcon#read 3, iclass 6, count 0 2006.285.14:27:23.11#ibcon#about to read 4, iclass 6, count 0 2006.285.14:27:23.11#ibcon#read 4, iclass 6, count 0 2006.285.14:27:23.11#ibcon#about to read 5, iclass 6, count 0 2006.285.14:27:23.11#ibcon#read 5, iclass 6, count 0 2006.285.14:27:23.11#ibcon#about to read 6, iclass 6, count 0 2006.285.14:27:23.11#ibcon#read 6, iclass 6, count 0 2006.285.14:27:23.11#ibcon#end of sib2, iclass 6, count 0 2006.285.14:27:23.11#ibcon#*mode == 0, iclass 6, count 0 2006.285.14:27:23.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.14:27:23.11#ibcon#[25=USB\r\n] 2006.285.14:27:23.11#ibcon#*before write, iclass 6, count 0 2006.285.14:27:23.11#ibcon#enter sib2, iclass 6, count 0 2006.285.14:27:23.11#ibcon#flushed, iclass 6, count 0 2006.285.14:27:23.11#ibcon#about to write, iclass 6, count 0 2006.285.14:27:23.11#ibcon#wrote, iclass 6, count 0 2006.285.14:27:23.11#ibcon#about to read 3, iclass 6, count 0 2006.285.14:27:23.14#ibcon#read 3, iclass 6, count 0 2006.285.14:27:23.14#ibcon#about to read 4, iclass 6, count 0 2006.285.14:27:23.14#ibcon#read 4, iclass 6, count 0 2006.285.14:27:23.14#ibcon#about to read 5, iclass 6, count 0 2006.285.14:27:23.14#ibcon#read 5, iclass 6, count 0 2006.285.14:27:23.14#ibcon#about to read 6, iclass 6, count 0 2006.285.14:27:23.14#ibcon#read 6, iclass 6, count 0 2006.285.14:27:23.14#ibcon#end of sib2, iclass 6, count 0 2006.285.14:27:23.14#ibcon#*after write, iclass 6, count 0 2006.285.14:27:23.14#ibcon#*before return 0, iclass 6, count 0 2006.285.14:27:23.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:27:23.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:27:23.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.14:27:23.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.14:27:23.14$vck44/vblo=1,629.99 2006.285.14:27:23.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.14:27:23.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.14:27:23.14#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:23.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:27:23.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:27:23.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:27:23.14#ibcon#enter wrdev, iclass 10, count 0 2006.285.14:27:23.14#ibcon#first serial, iclass 10, count 0 2006.285.14:27:23.14#ibcon#enter sib2, iclass 10, count 0 2006.285.14:27:23.14#ibcon#flushed, iclass 10, count 0 2006.285.14:27:23.14#ibcon#about to write, iclass 10, count 0 2006.285.14:27:23.14#ibcon#wrote, iclass 10, count 0 2006.285.14:27:23.14#ibcon#about to read 3, iclass 10, count 0 2006.285.14:27:23.16#ibcon#read 3, iclass 10, count 0 2006.285.14:27:23.16#ibcon#about to read 4, iclass 10, count 0 2006.285.14:27:23.16#ibcon#read 4, iclass 10, count 0 2006.285.14:27:23.28#ibcon#about to read 5, iclass 10, count 0 2006.285.14:27:23.28#ibcon#read 5, iclass 10, count 0 2006.285.14:27:23.28#ibcon#about to read 6, iclass 10, count 0 2006.285.14:27:23.28#ibcon#read 6, iclass 10, count 0 2006.285.14:27:23.28#ibcon#end of sib2, iclass 10, count 0 2006.285.14:27:23.28#ibcon#*mode == 0, iclass 10, count 0 2006.285.14:27:23.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.14:27:23.28#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.14:27:23.28#ibcon#*before write, iclass 10, count 0 2006.285.14:27:23.28#ibcon#enter sib2, iclass 10, count 0 2006.285.14:27:23.28#ibcon#flushed, iclass 10, count 0 2006.285.14:27:23.28#ibcon#about to write, iclass 10, count 0 2006.285.14:27:23.28#ibcon#wrote, iclass 10, count 0 2006.285.14:27:23.28#ibcon#about to read 3, iclass 10, count 0 2006.285.14:27:23.32#ibcon#read 3, iclass 10, count 0 2006.285.14:27:23.32#ibcon#about to read 4, iclass 10, count 0 2006.285.14:27:23.32#ibcon#read 4, iclass 10, count 0 2006.285.14:27:23.32#ibcon#about to read 5, iclass 10, count 0 2006.285.14:27:23.32#ibcon#read 5, iclass 10, count 0 2006.285.14:27:23.32#ibcon#about to read 6, iclass 10, count 0 2006.285.14:27:23.32#ibcon#read 6, iclass 10, count 0 2006.285.14:27:23.32#ibcon#end of sib2, iclass 10, count 0 2006.285.14:27:23.32#ibcon#*after write, iclass 10, count 0 2006.285.14:27:23.32#ibcon#*before return 0, iclass 10, count 0 2006.285.14:27:23.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:27:23.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:27:23.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.14:27:23.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.14:27:23.32$vck44/vb=1,4 2006.285.14:27:23.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.14:27:23.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.14:27:23.32#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:23.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:27:23.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:27:23.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:27:23.32#ibcon#enter wrdev, iclass 12, count 2 2006.285.14:27:23.32#ibcon#first serial, iclass 12, count 2 2006.285.14:27:23.32#ibcon#enter sib2, iclass 12, count 2 2006.285.14:27:23.32#ibcon#flushed, iclass 12, count 2 2006.285.14:27:23.32#ibcon#about to write, iclass 12, count 2 2006.285.14:27:23.32#ibcon#wrote, iclass 12, count 2 2006.285.14:27:23.32#ibcon#about to read 3, iclass 12, count 2 2006.285.14:27:23.34#ibcon#read 3, iclass 12, count 2 2006.285.14:27:23.34#ibcon#about to read 4, iclass 12, count 2 2006.285.14:27:23.34#ibcon#read 4, iclass 12, count 2 2006.285.14:27:23.34#ibcon#about to read 5, iclass 12, count 2 2006.285.14:27:23.34#ibcon#read 5, iclass 12, count 2 2006.285.14:27:23.34#ibcon#about to read 6, iclass 12, count 2 2006.285.14:27:23.34#ibcon#read 6, iclass 12, count 2 2006.285.14:27:23.34#ibcon#end of sib2, iclass 12, count 2 2006.285.14:27:23.34#ibcon#*mode == 0, iclass 12, count 2 2006.285.14:27:23.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.14:27:23.34#ibcon#[27=AT01-04\r\n] 2006.285.14:27:23.34#ibcon#*before write, iclass 12, count 2 2006.285.14:27:23.34#ibcon#enter sib2, iclass 12, count 2 2006.285.14:27:23.34#ibcon#flushed, iclass 12, count 2 2006.285.14:27:23.34#ibcon#about to write, iclass 12, count 2 2006.285.14:27:23.34#ibcon#wrote, iclass 12, count 2 2006.285.14:27:23.34#ibcon#about to read 3, iclass 12, count 2 2006.285.14:27:23.37#ibcon#read 3, iclass 12, count 2 2006.285.14:27:23.37#ibcon#about to read 4, iclass 12, count 2 2006.285.14:27:23.37#ibcon#read 4, iclass 12, count 2 2006.285.14:27:23.37#ibcon#about to read 5, iclass 12, count 2 2006.285.14:27:23.37#ibcon#read 5, iclass 12, count 2 2006.285.14:27:23.37#ibcon#about to read 6, iclass 12, count 2 2006.285.14:27:23.37#ibcon#read 6, iclass 12, count 2 2006.285.14:27:23.37#ibcon#end of sib2, iclass 12, count 2 2006.285.14:27:23.37#ibcon#*after write, iclass 12, count 2 2006.285.14:27:23.37#ibcon#*before return 0, iclass 12, count 2 2006.285.14:27:23.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:27:23.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:27:23.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.14:27:23.37#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:23.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:27:23.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:27:23.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:27:23.49#ibcon#enter wrdev, iclass 12, count 0 2006.285.14:27:23.49#ibcon#first serial, iclass 12, count 0 2006.285.14:27:23.49#ibcon#enter sib2, iclass 12, count 0 2006.285.14:27:23.49#ibcon#flushed, iclass 12, count 0 2006.285.14:27:23.49#ibcon#about to write, iclass 12, count 0 2006.285.14:27:23.49#ibcon#wrote, iclass 12, count 0 2006.285.14:27:23.49#ibcon#about to read 3, iclass 12, count 0 2006.285.14:27:23.51#ibcon#read 3, iclass 12, count 0 2006.285.14:27:23.51#ibcon#about to read 4, iclass 12, count 0 2006.285.14:27:23.51#ibcon#read 4, iclass 12, count 0 2006.285.14:27:23.51#ibcon#about to read 5, iclass 12, count 0 2006.285.14:27:23.51#ibcon#read 5, iclass 12, count 0 2006.285.14:27:23.51#ibcon#about to read 6, iclass 12, count 0 2006.285.14:27:23.51#ibcon#read 6, iclass 12, count 0 2006.285.14:27:23.51#ibcon#end of sib2, iclass 12, count 0 2006.285.14:27:23.51#ibcon#*mode == 0, iclass 12, count 0 2006.285.14:27:23.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.14:27:23.51#ibcon#[27=USB\r\n] 2006.285.14:27:23.51#ibcon#*before write, iclass 12, count 0 2006.285.14:27:23.51#ibcon#enter sib2, iclass 12, count 0 2006.285.14:27:23.51#ibcon#flushed, iclass 12, count 0 2006.285.14:27:23.51#ibcon#about to write, iclass 12, count 0 2006.285.14:27:23.51#ibcon#wrote, iclass 12, count 0 2006.285.14:27:23.51#ibcon#about to read 3, iclass 12, count 0 2006.285.14:27:23.54#ibcon#read 3, iclass 12, count 0 2006.285.14:27:23.54#ibcon#about to read 4, iclass 12, count 0 2006.285.14:27:23.54#ibcon#read 4, iclass 12, count 0 2006.285.14:27:23.54#ibcon#about to read 5, iclass 12, count 0 2006.285.14:27:23.54#ibcon#read 5, iclass 12, count 0 2006.285.14:27:23.54#ibcon#about to read 6, iclass 12, count 0 2006.285.14:27:23.54#ibcon#read 6, iclass 12, count 0 2006.285.14:27:23.54#ibcon#end of sib2, iclass 12, count 0 2006.285.14:27:23.54#ibcon#*after write, iclass 12, count 0 2006.285.14:27:23.54#ibcon#*before return 0, iclass 12, count 0 2006.285.14:27:23.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:27:23.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:27:23.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.14:27:23.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.14:27:23.54$vck44/vblo=2,634.99 2006.285.14:27:23.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.14:27:23.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.14:27:23.54#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:23.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:27:23.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:27:23.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:27:23.54#ibcon#enter wrdev, iclass 14, count 0 2006.285.14:27:23.54#ibcon#first serial, iclass 14, count 0 2006.285.14:27:23.54#ibcon#enter sib2, iclass 14, count 0 2006.285.14:27:23.54#ibcon#flushed, iclass 14, count 0 2006.285.14:27:23.54#ibcon#about to write, iclass 14, count 0 2006.285.14:27:23.54#ibcon#wrote, iclass 14, count 0 2006.285.14:27:23.54#ibcon#about to read 3, iclass 14, count 0 2006.285.14:27:23.56#ibcon#read 3, iclass 14, count 0 2006.285.14:27:23.56#ibcon#about to read 4, iclass 14, count 0 2006.285.14:27:23.56#ibcon#read 4, iclass 14, count 0 2006.285.14:27:23.56#ibcon#about to read 5, iclass 14, count 0 2006.285.14:27:23.56#ibcon#read 5, iclass 14, count 0 2006.285.14:27:23.56#ibcon#about to read 6, iclass 14, count 0 2006.285.14:27:23.56#ibcon#read 6, iclass 14, count 0 2006.285.14:27:23.56#ibcon#end of sib2, iclass 14, count 0 2006.285.14:27:23.56#ibcon#*mode == 0, iclass 14, count 0 2006.285.14:27:23.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.14:27:23.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.14:27:23.56#ibcon#*before write, iclass 14, count 0 2006.285.14:27:23.56#ibcon#enter sib2, iclass 14, count 0 2006.285.14:27:23.56#ibcon#flushed, iclass 14, count 0 2006.285.14:27:23.56#ibcon#about to write, iclass 14, count 0 2006.285.14:27:23.56#ibcon#wrote, iclass 14, count 0 2006.285.14:27:23.56#ibcon#about to read 3, iclass 14, count 0 2006.285.14:27:23.60#ibcon#read 3, iclass 14, count 0 2006.285.14:27:23.60#ibcon#about to read 4, iclass 14, count 0 2006.285.14:27:23.60#ibcon#read 4, iclass 14, count 0 2006.285.14:27:23.60#ibcon#about to read 5, iclass 14, count 0 2006.285.14:27:23.60#ibcon#read 5, iclass 14, count 0 2006.285.14:27:23.60#ibcon#about to read 6, iclass 14, count 0 2006.285.14:27:23.60#ibcon#read 6, iclass 14, count 0 2006.285.14:27:23.60#ibcon#end of sib2, iclass 14, count 0 2006.285.14:27:23.60#ibcon#*after write, iclass 14, count 0 2006.285.14:27:23.60#ibcon#*before return 0, iclass 14, count 0 2006.285.14:27:23.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:27:23.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:27:23.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.14:27:23.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.14:27:23.60$vck44/vb=2,5 2006.285.14:27:23.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.14:27:23.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.14:27:23.60#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:23.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:27:23.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:27:23.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:27:23.66#ibcon#enter wrdev, iclass 16, count 2 2006.285.14:27:23.66#ibcon#first serial, iclass 16, count 2 2006.285.14:27:23.66#ibcon#enter sib2, iclass 16, count 2 2006.285.14:27:23.66#ibcon#flushed, iclass 16, count 2 2006.285.14:27:23.66#ibcon#about to write, iclass 16, count 2 2006.285.14:27:23.66#ibcon#wrote, iclass 16, count 2 2006.285.14:27:23.66#ibcon#about to read 3, iclass 16, count 2 2006.285.14:27:23.68#ibcon#read 3, iclass 16, count 2 2006.285.14:27:23.68#ibcon#about to read 4, iclass 16, count 2 2006.285.14:27:23.68#ibcon#read 4, iclass 16, count 2 2006.285.14:27:23.68#ibcon#about to read 5, iclass 16, count 2 2006.285.14:27:23.68#ibcon#read 5, iclass 16, count 2 2006.285.14:27:23.68#ibcon#about to read 6, iclass 16, count 2 2006.285.14:27:23.68#ibcon#read 6, iclass 16, count 2 2006.285.14:27:23.68#ibcon#end of sib2, iclass 16, count 2 2006.285.14:27:23.68#ibcon#*mode == 0, iclass 16, count 2 2006.285.14:27:23.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.14:27:23.68#ibcon#[27=AT02-05\r\n] 2006.285.14:27:23.68#ibcon#*before write, iclass 16, count 2 2006.285.14:27:23.68#ibcon#enter sib2, iclass 16, count 2 2006.285.14:27:23.68#ibcon#flushed, iclass 16, count 2 2006.285.14:27:23.68#ibcon#about to write, iclass 16, count 2 2006.285.14:27:23.68#ibcon#wrote, iclass 16, count 2 2006.285.14:27:23.68#ibcon#about to read 3, iclass 16, count 2 2006.285.14:27:23.71#ibcon#read 3, iclass 16, count 2 2006.285.14:27:23.71#ibcon#about to read 4, iclass 16, count 2 2006.285.14:27:23.71#ibcon#read 4, iclass 16, count 2 2006.285.14:27:23.71#ibcon#about to read 5, iclass 16, count 2 2006.285.14:27:23.71#ibcon#read 5, iclass 16, count 2 2006.285.14:27:23.71#ibcon#about to read 6, iclass 16, count 2 2006.285.14:27:23.71#ibcon#read 6, iclass 16, count 2 2006.285.14:27:23.71#ibcon#end of sib2, iclass 16, count 2 2006.285.14:27:23.71#ibcon#*after write, iclass 16, count 2 2006.285.14:27:23.71#ibcon#*before return 0, iclass 16, count 2 2006.285.14:27:23.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:27:23.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:27:23.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.14:27:23.71#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:23.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:27:23.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:27:23.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:27:23.83#ibcon#enter wrdev, iclass 16, count 0 2006.285.14:27:23.83#ibcon#first serial, iclass 16, count 0 2006.285.14:27:23.83#ibcon#enter sib2, iclass 16, count 0 2006.285.14:27:23.83#ibcon#flushed, iclass 16, count 0 2006.285.14:27:23.83#ibcon#about to write, iclass 16, count 0 2006.285.14:27:23.83#ibcon#wrote, iclass 16, count 0 2006.285.14:27:23.83#ibcon#about to read 3, iclass 16, count 0 2006.285.14:27:23.85#ibcon#read 3, iclass 16, count 0 2006.285.14:27:23.85#ibcon#about to read 4, iclass 16, count 0 2006.285.14:27:23.85#ibcon#read 4, iclass 16, count 0 2006.285.14:27:23.85#ibcon#about to read 5, iclass 16, count 0 2006.285.14:27:23.85#ibcon#read 5, iclass 16, count 0 2006.285.14:27:23.85#ibcon#about to read 6, iclass 16, count 0 2006.285.14:27:23.85#ibcon#read 6, iclass 16, count 0 2006.285.14:27:23.85#ibcon#end of sib2, iclass 16, count 0 2006.285.14:27:23.85#ibcon#*mode == 0, iclass 16, count 0 2006.285.14:27:23.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.14:27:23.85#ibcon#[27=USB\r\n] 2006.285.14:27:23.85#ibcon#*before write, iclass 16, count 0 2006.285.14:27:23.85#ibcon#enter sib2, iclass 16, count 0 2006.285.14:27:23.85#ibcon#flushed, iclass 16, count 0 2006.285.14:27:23.85#ibcon#about to write, iclass 16, count 0 2006.285.14:27:23.85#ibcon#wrote, iclass 16, count 0 2006.285.14:27:23.85#ibcon#about to read 3, iclass 16, count 0 2006.285.14:27:23.88#ibcon#read 3, iclass 16, count 0 2006.285.14:27:23.88#ibcon#about to read 4, iclass 16, count 0 2006.285.14:27:23.88#ibcon#read 4, iclass 16, count 0 2006.285.14:27:23.88#ibcon#about to read 5, iclass 16, count 0 2006.285.14:27:23.88#ibcon#read 5, iclass 16, count 0 2006.285.14:27:23.88#ibcon#about to read 6, iclass 16, count 0 2006.285.14:27:23.88#ibcon#read 6, iclass 16, count 0 2006.285.14:27:23.88#ibcon#end of sib2, iclass 16, count 0 2006.285.14:27:23.88#ibcon#*after write, iclass 16, count 0 2006.285.14:27:23.88#ibcon#*before return 0, iclass 16, count 0 2006.285.14:27:23.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:27:23.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:27:23.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.14:27:23.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.14:27:23.88$vck44/vblo=3,649.99 2006.285.14:27:23.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.14:27:23.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.14:27:23.88#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:23.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:27:23.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:27:23.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:27:23.88#ibcon#enter wrdev, iclass 18, count 0 2006.285.14:27:23.88#ibcon#first serial, iclass 18, count 0 2006.285.14:27:23.88#ibcon#enter sib2, iclass 18, count 0 2006.285.14:27:23.88#ibcon#flushed, iclass 18, count 0 2006.285.14:27:23.88#ibcon#about to write, iclass 18, count 0 2006.285.14:27:23.88#ibcon#wrote, iclass 18, count 0 2006.285.14:27:23.88#ibcon#about to read 3, iclass 18, count 0 2006.285.14:27:23.90#ibcon#read 3, iclass 18, count 0 2006.285.14:27:23.90#ibcon#about to read 4, iclass 18, count 0 2006.285.14:27:23.90#ibcon#read 4, iclass 18, count 0 2006.285.14:27:23.90#ibcon#about to read 5, iclass 18, count 0 2006.285.14:27:23.90#ibcon#read 5, iclass 18, count 0 2006.285.14:27:23.90#ibcon#about to read 6, iclass 18, count 0 2006.285.14:27:23.90#ibcon#read 6, iclass 18, count 0 2006.285.14:27:23.90#ibcon#end of sib2, iclass 18, count 0 2006.285.14:27:23.90#ibcon#*mode == 0, iclass 18, count 0 2006.285.14:27:23.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.14:27:23.90#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.14:27:23.90#ibcon#*before write, iclass 18, count 0 2006.285.14:27:23.90#ibcon#enter sib2, iclass 18, count 0 2006.285.14:27:23.90#ibcon#flushed, iclass 18, count 0 2006.285.14:27:23.90#ibcon#about to write, iclass 18, count 0 2006.285.14:27:23.90#ibcon#wrote, iclass 18, count 0 2006.285.14:27:23.90#ibcon#about to read 3, iclass 18, count 0 2006.285.14:27:23.94#ibcon#read 3, iclass 18, count 0 2006.285.14:27:23.94#ibcon#about to read 4, iclass 18, count 0 2006.285.14:27:23.94#ibcon#read 4, iclass 18, count 0 2006.285.14:27:23.94#ibcon#about to read 5, iclass 18, count 0 2006.285.14:27:23.94#ibcon#read 5, iclass 18, count 0 2006.285.14:27:23.94#ibcon#about to read 6, iclass 18, count 0 2006.285.14:27:23.94#ibcon#read 6, iclass 18, count 0 2006.285.14:27:23.94#ibcon#end of sib2, iclass 18, count 0 2006.285.14:27:23.94#ibcon#*after write, iclass 18, count 0 2006.285.14:27:23.94#ibcon#*before return 0, iclass 18, count 0 2006.285.14:27:23.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:27:23.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:27:23.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.14:27:23.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.14:27:23.94$vck44/vb=3,4 2006.285.14:27:23.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.14:27:23.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.14:27:23.94#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:23.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:27:24.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:27:24.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:27:24.00#ibcon#enter wrdev, iclass 20, count 2 2006.285.14:27:24.00#ibcon#first serial, iclass 20, count 2 2006.285.14:27:24.00#ibcon#enter sib2, iclass 20, count 2 2006.285.14:27:24.00#ibcon#flushed, iclass 20, count 2 2006.285.14:27:24.00#ibcon#about to write, iclass 20, count 2 2006.285.14:27:24.00#ibcon#wrote, iclass 20, count 2 2006.285.14:27:24.00#ibcon#about to read 3, iclass 20, count 2 2006.285.14:27:24.02#ibcon#read 3, iclass 20, count 2 2006.285.14:27:24.02#ibcon#about to read 4, iclass 20, count 2 2006.285.14:27:24.02#ibcon#read 4, iclass 20, count 2 2006.285.14:27:24.02#ibcon#about to read 5, iclass 20, count 2 2006.285.14:27:24.02#ibcon#read 5, iclass 20, count 2 2006.285.14:27:24.02#ibcon#about to read 6, iclass 20, count 2 2006.285.14:27:24.02#ibcon#read 6, iclass 20, count 2 2006.285.14:27:24.02#ibcon#end of sib2, iclass 20, count 2 2006.285.14:27:24.02#ibcon#*mode == 0, iclass 20, count 2 2006.285.14:27:24.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.14:27:24.02#ibcon#[27=AT03-04\r\n] 2006.285.14:27:24.02#ibcon#*before write, iclass 20, count 2 2006.285.14:27:24.02#ibcon#enter sib2, iclass 20, count 2 2006.285.14:27:24.02#ibcon#flushed, iclass 20, count 2 2006.285.14:27:24.02#ibcon#about to write, iclass 20, count 2 2006.285.14:27:24.02#ibcon#wrote, iclass 20, count 2 2006.285.14:27:24.02#ibcon#about to read 3, iclass 20, count 2 2006.285.14:27:24.05#ibcon#read 3, iclass 20, count 2 2006.285.14:27:24.05#ibcon#about to read 4, iclass 20, count 2 2006.285.14:27:24.05#ibcon#read 4, iclass 20, count 2 2006.285.14:27:24.05#ibcon#about to read 5, iclass 20, count 2 2006.285.14:27:24.05#ibcon#read 5, iclass 20, count 2 2006.285.14:27:24.05#ibcon#about to read 6, iclass 20, count 2 2006.285.14:27:24.05#ibcon#read 6, iclass 20, count 2 2006.285.14:27:24.05#ibcon#end of sib2, iclass 20, count 2 2006.285.14:27:24.05#ibcon#*after write, iclass 20, count 2 2006.285.14:27:24.05#ibcon#*before return 0, iclass 20, count 2 2006.285.14:27:24.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:27:24.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:27:24.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.14:27:24.05#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:24.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:27:24.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:27:24.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:27:24.17#ibcon#enter wrdev, iclass 20, count 0 2006.285.14:27:24.17#ibcon#first serial, iclass 20, count 0 2006.285.14:27:24.17#ibcon#enter sib2, iclass 20, count 0 2006.285.14:27:24.17#ibcon#flushed, iclass 20, count 0 2006.285.14:27:24.17#ibcon#about to write, iclass 20, count 0 2006.285.14:27:24.17#ibcon#wrote, iclass 20, count 0 2006.285.14:27:24.17#ibcon#about to read 3, iclass 20, count 0 2006.285.14:27:24.19#ibcon#read 3, iclass 20, count 0 2006.285.14:27:24.19#ibcon#about to read 4, iclass 20, count 0 2006.285.14:27:24.19#ibcon#read 4, iclass 20, count 0 2006.285.14:27:24.19#ibcon#about to read 5, iclass 20, count 0 2006.285.14:27:24.19#ibcon#read 5, iclass 20, count 0 2006.285.14:27:24.19#ibcon#about to read 6, iclass 20, count 0 2006.285.14:27:24.19#ibcon#read 6, iclass 20, count 0 2006.285.14:27:24.19#ibcon#end of sib2, iclass 20, count 0 2006.285.14:27:24.19#ibcon#*mode == 0, iclass 20, count 0 2006.285.14:27:24.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.14:27:24.19#ibcon#[27=USB\r\n] 2006.285.14:27:24.19#ibcon#*before write, iclass 20, count 0 2006.285.14:27:24.19#ibcon#enter sib2, iclass 20, count 0 2006.285.14:27:24.19#ibcon#flushed, iclass 20, count 0 2006.285.14:27:24.19#ibcon#about to write, iclass 20, count 0 2006.285.14:27:24.19#ibcon#wrote, iclass 20, count 0 2006.285.14:27:24.19#ibcon#about to read 3, iclass 20, count 0 2006.285.14:27:24.22#ibcon#read 3, iclass 20, count 0 2006.285.14:27:24.22#ibcon#about to read 4, iclass 20, count 0 2006.285.14:27:24.22#ibcon#read 4, iclass 20, count 0 2006.285.14:27:24.22#ibcon#about to read 5, iclass 20, count 0 2006.285.14:27:24.22#ibcon#read 5, iclass 20, count 0 2006.285.14:27:24.22#ibcon#about to read 6, iclass 20, count 0 2006.285.14:27:24.22#ibcon#read 6, iclass 20, count 0 2006.285.14:27:24.22#ibcon#end of sib2, iclass 20, count 0 2006.285.14:27:24.22#ibcon#*after write, iclass 20, count 0 2006.285.14:27:24.22#ibcon#*before return 0, iclass 20, count 0 2006.285.14:27:24.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:27:24.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:27:24.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.14:27:24.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.14:27:24.22$vck44/vblo=4,679.99 2006.285.14:27:24.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.14:27:24.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.14:27:24.22#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:24.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:27:24.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:27:24.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:27:24.22#ibcon#enter wrdev, iclass 22, count 0 2006.285.14:27:24.22#ibcon#first serial, iclass 22, count 0 2006.285.14:27:24.22#ibcon#enter sib2, iclass 22, count 0 2006.285.14:27:24.22#ibcon#flushed, iclass 22, count 0 2006.285.14:27:24.22#ibcon#about to write, iclass 22, count 0 2006.285.14:27:24.22#ibcon#wrote, iclass 22, count 0 2006.285.14:27:24.22#ibcon#about to read 3, iclass 22, count 0 2006.285.14:27:24.24#ibcon#read 3, iclass 22, count 0 2006.285.14:27:24.35#ibcon#about to read 4, iclass 22, count 0 2006.285.14:27:24.35#ibcon#read 4, iclass 22, count 0 2006.285.14:27:24.35#ibcon#about to read 5, iclass 22, count 0 2006.285.14:27:24.35#ibcon#read 5, iclass 22, count 0 2006.285.14:27:24.35#ibcon#about to read 6, iclass 22, count 0 2006.285.14:27:24.35#ibcon#read 6, iclass 22, count 0 2006.285.14:27:24.35#ibcon#end of sib2, iclass 22, count 0 2006.285.14:27:24.35#ibcon#*mode == 0, iclass 22, count 0 2006.285.14:27:24.35#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.14:27:24.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.14:27:24.35#ibcon#*before write, iclass 22, count 0 2006.285.14:27:24.35#ibcon#enter sib2, iclass 22, count 0 2006.285.14:27:24.35#ibcon#flushed, iclass 22, count 0 2006.285.14:27:24.35#ibcon#about to write, iclass 22, count 0 2006.285.14:27:24.35#ibcon#wrote, iclass 22, count 0 2006.285.14:27:24.35#ibcon#about to read 3, iclass 22, count 0 2006.285.14:27:24.39#ibcon#read 3, iclass 22, count 0 2006.285.14:27:24.39#ibcon#about to read 4, iclass 22, count 0 2006.285.14:27:24.39#ibcon#read 4, iclass 22, count 0 2006.285.14:27:24.39#ibcon#about to read 5, iclass 22, count 0 2006.285.14:27:24.39#ibcon#read 5, iclass 22, count 0 2006.285.14:27:24.39#ibcon#about to read 6, iclass 22, count 0 2006.285.14:27:24.39#ibcon#read 6, iclass 22, count 0 2006.285.14:27:24.39#ibcon#end of sib2, iclass 22, count 0 2006.285.14:27:24.39#ibcon#*after write, iclass 22, count 0 2006.285.14:27:24.39#ibcon#*before return 0, iclass 22, count 0 2006.285.14:27:24.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:27:24.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:27:24.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.14:27:24.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.14:27:24.39$vck44/vb=4,5 2006.285.14:27:24.39#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.14:27:24.39#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.14:27:24.39#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:24.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:27:24.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:27:24.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:27:24.39#ibcon#enter wrdev, iclass 24, count 2 2006.285.14:27:24.39#ibcon#first serial, iclass 24, count 2 2006.285.14:27:24.39#ibcon#enter sib2, iclass 24, count 2 2006.285.14:27:24.39#ibcon#flushed, iclass 24, count 2 2006.285.14:27:24.39#ibcon#about to write, iclass 24, count 2 2006.285.14:27:24.39#ibcon#wrote, iclass 24, count 2 2006.285.14:27:24.39#ibcon#about to read 3, iclass 24, count 2 2006.285.14:27:24.41#ibcon#read 3, iclass 24, count 2 2006.285.14:27:24.41#ibcon#about to read 4, iclass 24, count 2 2006.285.14:27:24.41#ibcon#read 4, iclass 24, count 2 2006.285.14:27:24.41#ibcon#about to read 5, iclass 24, count 2 2006.285.14:27:24.41#ibcon#read 5, iclass 24, count 2 2006.285.14:27:24.41#ibcon#about to read 6, iclass 24, count 2 2006.285.14:27:24.41#ibcon#read 6, iclass 24, count 2 2006.285.14:27:24.41#ibcon#end of sib2, iclass 24, count 2 2006.285.14:27:24.41#ibcon#*mode == 0, iclass 24, count 2 2006.285.14:27:24.41#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.14:27:24.41#ibcon#[27=AT04-05\r\n] 2006.285.14:27:24.41#ibcon#*before write, iclass 24, count 2 2006.285.14:27:24.41#ibcon#enter sib2, iclass 24, count 2 2006.285.14:27:24.41#ibcon#flushed, iclass 24, count 2 2006.285.14:27:24.41#ibcon#about to write, iclass 24, count 2 2006.285.14:27:24.41#ibcon#wrote, iclass 24, count 2 2006.285.14:27:24.41#ibcon#about to read 3, iclass 24, count 2 2006.285.14:27:24.44#ibcon#read 3, iclass 24, count 2 2006.285.14:27:24.44#ibcon#about to read 4, iclass 24, count 2 2006.285.14:27:24.44#ibcon#read 4, iclass 24, count 2 2006.285.14:27:24.44#ibcon#about to read 5, iclass 24, count 2 2006.285.14:27:24.44#ibcon#read 5, iclass 24, count 2 2006.285.14:27:24.44#ibcon#about to read 6, iclass 24, count 2 2006.285.14:27:24.44#ibcon#read 6, iclass 24, count 2 2006.285.14:27:24.44#ibcon#end of sib2, iclass 24, count 2 2006.285.14:27:24.44#ibcon#*after write, iclass 24, count 2 2006.285.14:27:24.44#ibcon#*before return 0, iclass 24, count 2 2006.285.14:27:24.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:27:24.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:27:24.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.14:27:24.44#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:24.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:27:24.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:27:24.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:27:24.56#ibcon#enter wrdev, iclass 24, count 0 2006.285.14:27:24.56#ibcon#first serial, iclass 24, count 0 2006.285.14:27:24.56#ibcon#enter sib2, iclass 24, count 0 2006.285.14:27:24.56#ibcon#flushed, iclass 24, count 0 2006.285.14:27:24.56#ibcon#about to write, iclass 24, count 0 2006.285.14:27:24.56#ibcon#wrote, iclass 24, count 0 2006.285.14:27:24.56#ibcon#about to read 3, iclass 24, count 0 2006.285.14:27:24.58#ibcon#read 3, iclass 24, count 0 2006.285.14:27:24.58#ibcon#about to read 4, iclass 24, count 0 2006.285.14:27:24.58#ibcon#read 4, iclass 24, count 0 2006.285.14:27:24.58#ibcon#about to read 5, iclass 24, count 0 2006.285.14:27:24.58#ibcon#read 5, iclass 24, count 0 2006.285.14:27:24.58#ibcon#about to read 6, iclass 24, count 0 2006.285.14:27:24.58#ibcon#read 6, iclass 24, count 0 2006.285.14:27:24.58#ibcon#end of sib2, iclass 24, count 0 2006.285.14:27:24.58#ibcon#*mode == 0, iclass 24, count 0 2006.285.14:27:24.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.14:27:24.58#ibcon#[27=USB\r\n] 2006.285.14:27:24.58#ibcon#*before write, iclass 24, count 0 2006.285.14:27:24.58#ibcon#enter sib2, iclass 24, count 0 2006.285.14:27:24.58#ibcon#flushed, iclass 24, count 0 2006.285.14:27:24.58#ibcon#about to write, iclass 24, count 0 2006.285.14:27:24.58#ibcon#wrote, iclass 24, count 0 2006.285.14:27:24.58#ibcon#about to read 3, iclass 24, count 0 2006.285.14:27:24.61#ibcon#read 3, iclass 24, count 0 2006.285.14:27:24.61#ibcon#about to read 4, iclass 24, count 0 2006.285.14:27:24.61#ibcon#read 4, iclass 24, count 0 2006.285.14:27:24.61#ibcon#about to read 5, iclass 24, count 0 2006.285.14:27:24.61#ibcon#read 5, iclass 24, count 0 2006.285.14:27:24.61#ibcon#about to read 6, iclass 24, count 0 2006.285.14:27:24.61#ibcon#read 6, iclass 24, count 0 2006.285.14:27:24.61#ibcon#end of sib2, iclass 24, count 0 2006.285.14:27:24.61#ibcon#*after write, iclass 24, count 0 2006.285.14:27:24.61#ibcon#*before return 0, iclass 24, count 0 2006.285.14:27:24.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:27:24.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:27:24.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.14:27:24.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.14:27:24.61$vck44/vblo=5,709.99 2006.285.14:27:24.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.14:27:24.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.14:27:24.61#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:24.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:27:24.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:27:24.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:27:24.61#ibcon#enter wrdev, iclass 26, count 0 2006.285.14:27:24.61#ibcon#first serial, iclass 26, count 0 2006.285.14:27:24.61#ibcon#enter sib2, iclass 26, count 0 2006.285.14:27:24.61#ibcon#flushed, iclass 26, count 0 2006.285.14:27:24.61#ibcon#about to write, iclass 26, count 0 2006.285.14:27:24.61#ibcon#wrote, iclass 26, count 0 2006.285.14:27:24.61#ibcon#about to read 3, iclass 26, count 0 2006.285.14:27:24.63#ibcon#read 3, iclass 26, count 0 2006.285.14:27:24.63#ibcon#about to read 4, iclass 26, count 0 2006.285.14:27:24.63#ibcon#read 4, iclass 26, count 0 2006.285.14:27:24.63#ibcon#about to read 5, iclass 26, count 0 2006.285.14:27:24.63#ibcon#read 5, iclass 26, count 0 2006.285.14:27:24.63#ibcon#about to read 6, iclass 26, count 0 2006.285.14:27:24.63#ibcon#read 6, iclass 26, count 0 2006.285.14:27:24.63#ibcon#end of sib2, iclass 26, count 0 2006.285.14:27:24.63#ibcon#*mode == 0, iclass 26, count 0 2006.285.14:27:24.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.14:27:24.63#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.14:27:24.63#ibcon#*before write, iclass 26, count 0 2006.285.14:27:24.63#ibcon#enter sib2, iclass 26, count 0 2006.285.14:27:24.63#ibcon#flushed, iclass 26, count 0 2006.285.14:27:24.63#ibcon#about to write, iclass 26, count 0 2006.285.14:27:24.63#ibcon#wrote, iclass 26, count 0 2006.285.14:27:24.63#ibcon#about to read 3, iclass 26, count 0 2006.285.14:27:24.67#ibcon#read 3, iclass 26, count 0 2006.285.14:27:24.67#ibcon#about to read 4, iclass 26, count 0 2006.285.14:27:24.67#ibcon#read 4, iclass 26, count 0 2006.285.14:27:24.67#ibcon#about to read 5, iclass 26, count 0 2006.285.14:27:24.67#ibcon#read 5, iclass 26, count 0 2006.285.14:27:24.67#ibcon#about to read 6, iclass 26, count 0 2006.285.14:27:24.67#ibcon#read 6, iclass 26, count 0 2006.285.14:27:24.67#ibcon#end of sib2, iclass 26, count 0 2006.285.14:27:24.67#ibcon#*after write, iclass 26, count 0 2006.285.14:27:24.67#ibcon#*before return 0, iclass 26, count 0 2006.285.14:27:24.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:27:24.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:27:24.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.14:27:24.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.14:27:24.67$vck44/vb=5,4 2006.285.14:27:24.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.14:27:24.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.14:27:24.67#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:24.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:27:24.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:27:24.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:27:24.73#ibcon#enter wrdev, iclass 28, count 2 2006.285.14:27:24.73#ibcon#first serial, iclass 28, count 2 2006.285.14:27:24.73#ibcon#enter sib2, iclass 28, count 2 2006.285.14:27:24.73#ibcon#flushed, iclass 28, count 2 2006.285.14:27:24.73#ibcon#about to write, iclass 28, count 2 2006.285.14:27:24.73#ibcon#wrote, iclass 28, count 2 2006.285.14:27:24.73#ibcon#about to read 3, iclass 28, count 2 2006.285.14:27:24.75#ibcon#read 3, iclass 28, count 2 2006.285.14:27:24.75#ibcon#about to read 4, iclass 28, count 2 2006.285.14:27:24.75#ibcon#read 4, iclass 28, count 2 2006.285.14:27:24.75#ibcon#about to read 5, iclass 28, count 2 2006.285.14:27:24.75#ibcon#read 5, iclass 28, count 2 2006.285.14:27:24.75#ibcon#about to read 6, iclass 28, count 2 2006.285.14:27:24.75#ibcon#read 6, iclass 28, count 2 2006.285.14:27:24.75#ibcon#end of sib2, iclass 28, count 2 2006.285.14:27:24.75#ibcon#*mode == 0, iclass 28, count 2 2006.285.14:27:24.75#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.14:27:24.75#ibcon#[27=AT05-04\r\n] 2006.285.14:27:24.75#ibcon#*before write, iclass 28, count 2 2006.285.14:27:24.75#ibcon#enter sib2, iclass 28, count 2 2006.285.14:27:24.75#ibcon#flushed, iclass 28, count 2 2006.285.14:27:24.75#ibcon#about to write, iclass 28, count 2 2006.285.14:27:24.75#ibcon#wrote, iclass 28, count 2 2006.285.14:27:24.75#ibcon#about to read 3, iclass 28, count 2 2006.285.14:27:24.78#ibcon#read 3, iclass 28, count 2 2006.285.14:27:24.78#ibcon#about to read 4, iclass 28, count 2 2006.285.14:27:24.78#ibcon#read 4, iclass 28, count 2 2006.285.14:27:24.78#ibcon#about to read 5, iclass 28, count 2 2006.285.14:27:24.78#ibcon#read 5, iclass 28, count 2 2006.285.14:27:24.78#ibcon#about to read 6, iclass 28, count 2 2006.285.14:27:24.78#ibcon#read 6, iclass 28, count 2 2006.285.14:27:24.78#ibcon#end of sib2, iclass 28, count 2 2006.285.14:27:24.78#ibcon#*after write, iclass 28, count 2 2006.285.14:27:24.78#ibcon#*before return 0, iclass 28, count 2 2006.285.14:27:24.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:27:24.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:27:24.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.14:27:24.78#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:24.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:27:24.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:27:24.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:27:24.90#ibcon#enter wrdev, iclass 28, count 0 2006.285.14:27:24.90#ibcon#first serial, iclass 28, count 0 2006.285.14:27:24.90#ibcon#enter sib2, iclass 28, count 0 2006.285.14:27:24.90#ibcon#flushed, iclass 28, count 0 2006.285.14:27:24.90#ibcon#about to write, iclass 28, count 0 2006.285.14:27:24.90#ibcon#wrote, iclass 28, count 0 2006.285.14:27:24.90#ibcon#about to read 3, iclass 28, count 0 2006.285.14:27:24.92#ibcon#read 3, iclass 28, count 0 2006.285.14:27:24.92#ibcon#about to read 4, iclass 28, count 0 2006.285.14:27:24.92#ibcon#read 4, iclass 28, count 0 2006.285.14:27:24.92#ibcon#about to read 5, iclass 28, count 0 2006.285.14:27:24.92#ibcon#read 5, iclass 28, count 0 2006.285.14:27:24.92#ibcon#about to read 6, iclass 28, count 0 2006.285.14:27:24.92#ibcon#read 6, iclass 28, count 0 2006.285.14:27:24.92#ibcon#end of sib2, iclass 28, count 0 2006.285.14:27:24.92#ibcon#*mode == 0, iclass 28, count 0 2006.285.14:27:24.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.14:27:24.92#ibcon#[27=USB\r\n] 2006.285.14:27:24.92#ibcon#*before write, iclass 28, count 0 2006.285.14:27:24.92#ibcon#enter sib2, iclass 28, count 0 2006.285.14:27:24.92#ibcon#flushed, iclass 28, count 0 2006.285.14:27:24.92#ibcon#about to write, iclass 28, count 0 2006.285.14:27:24.92#ibcon#wrote, iclass 28, count 0 2006.285.14:27:24.92#ibcon#about to read 3, iclass 28, count 0 2006.285.14:27:24.95#ibcon#read 3, iclass 28, count 0 2006.285.14:27:24.95#ibcon#about to read 4, iclass 28, count 0 2006.285.14:27:24.95#ibcon#read 4, iclass 28, count 0 2006.285.14:27:24.95#ibcon#about to read 5, iclass 28, count 0 2006.285.14:27:24.95#ibcon#read 5, iclass 28, count 0 2006.285.14:27:24.95#ibcon#about to read 6, iclass 28, count 0 2006.285.14:27:24.95#ibcon#read 6, iclass 28, count 0 2006.285.14:27:24.95#ibcon#end of sib2, iclass 28, count 0 2006.285.14:27:24.95#ibcon#*after write, iclass 28, count 0 2006.285.14:27:24.95#ibcon#*before return 0, iclass 28, count 0 2006.285.14:27:24.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:27:24.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:27:24.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.14:27:24.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.14:27:24.95$vck44/vblo=6,719.99 2006.285.14:27:24.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.14:27:24.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.14:27:24.95#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:24.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:27:24.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:27:24.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:27:24.95#ibcon#enter wrdev, iclass 30, count 0 2006.285.14:27:24.95#ibcon#first serial, iclass 30, count 0 2006.285.14:27:24.95#ibcon#enter sib2, iclass 30, count 0 2006.285.14:27:24.95#ibcon#flushed, iclass 30, count 0 2006.285.14:27:24.95#ibcon#about to write, iclass 30, count 0 2006.285.14:27:24.95#ibcon#wrote, iclass 30, count 0 2006.285.14:27:24.95#ibcon#about to read 3, iclass 30, count 0 2006.285.14:27:24.97#ibcon#read 3, iclass 30, count 0 2006.285.14:27:24.97#ibcon#about to read 4, iclass 30, count 0 2006.285.14:27:24.97#ibcon#read 4, iclass 30, count 0 2006.285.14:27:24.97#ibcon#about to read 5, iclass 30, count 0 2006.285.14:27:24.97#ibcon#read 5, iclass 30, count 0 2006.285.14:27:24.97#ibcon#about to read 6, iclass 30, count 0 2006.285.14:27:24.97#ibcon#read 6, iclass 30, count 0 2006.285.14:27:24.97#ibcon#end of sib2, iclass 30, count 0 2006.285.14:27:24.97#ibcon#*mode == 0, iclass 30, count 0 2006.285.14:27:24.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.14:27:24.97#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.14:27:24.97#ibcon#*before write, iclass 30, count 0 2006.285.14:27:24.97#ibcon#enter sib2, iclass 30, count 0 2006.285.14:27:24.97#ibcon#flushed, iclass 30, count 0 2006.285.14:27:24.97#ibcon#about to write, iclass 30, count 0 2006.285.14:27:24.97#ibcon#wrote, iclass 30, count 0 2006.285.14:27:24.97#ibcon#about to read 3, iclass 30, count 0 2006.285.14:27:25.01#ibcon#read 3, iclass 30, count 0 2006.285.14:27:25.01#ibcon#about to read 4, iclass 30, count 0 2006.285.14:27:25.01#ibcon#read 4, iclass 30, count 0 2006.285.14:27:25.01#ibcon#about to read 5, iclass 30, count 0 2006.285.14:27:25.01#ibcon#read 5, iclass 30, count 0 2006.285.14:27:25.01#ibcon#about to read 6, iclass 30, count 0 2006.285.14:27:25.01#ibcon#read 6, iclass 30, count 0 2006.285.14:27:25.01#ibcon#end of sib2, iclass 30, count 0 2006.285.14:27:25.01#ibcon#*after write, iclass 30, count 0 2006.285.14:27:25.01#ibcon#*before return 0, iclass 30, count 0 2006.285.14:27:25.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:27:25.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:27:25.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.14:27:25.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.14:27:25.01$vck44/vb=6,3 2006.285.14:27:25.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.14:27:25.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.14:27:25.01#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:25.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:27:25.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:27:25.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:27:25.07#ibcon#enter wrdev, iclass 32, count 2 2006.285.14:27:25.07#ibcon#first serial, iclass 32, count 2 2006.285.14:27:25.07#ibcon#enter sib2, iclass 32, count 2 2006.285.14:27:25.07#ibcon#flushed, iclass 32, count 2 2006.285.14:27:25.07#ibcon#about to write, iclass 32, count 2 2006.285.14:27:25.07#ibcon#wrote, iclass 32, count 2 2006.285.14:27:25.07#ibcon#about to read 3, iclass 32, count 2 2006.285.14:27:25.09#ibcon#read 3, iclass 32, count 2 2006.285.14:27:25.09#ibcon#about to read 4, iclass 32, count 2 2006.285.14:27:25.09#ibcon#read 4, iclass 32, count 2 2006.285.14:27:25.09#ibcon#about to read 5, iclass 32, count 2 2006.285.14:27:25.09#ibcon#read 5, iclass 32, count 2 2006.285.14:27:25.09#ibcon#about to read 6, iclass 32, count 2 2006.285.14:27:25.09#ibcon#read 6, iclass 32, count 2 2006.285.14:27:25.09#ibcon#end of sib2, iclass 32, count 2 2006.285.14:27:25.09#ibcon#*mode == 0, iclass 32, count 2 2006.285.14:27:25.09#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.14:27:25.09#ibcon#[27=AT06-03\r\n] 2006.285.14:27:25.09#ibcon#*before write, iclass 32, count 2 2006.285.14:27:25.09#ibcon#enter sib2, iclass 32, count 2 2006.285.14:27:25.09#ibcon#flushed, iclass 32, count 2 2006.285.14:27:25.09#ibcon#about to write, iclass 32, count 2 2006.285.14:27:25.09#ibcon#wrote, iclass 32, count 2 2006.285.14:27:25.09#ibcon#about to read 3, iclass 32, count 2 2006.285.14:27:25.12#ibcon#read 3, iclass 32, count 2 2006.285.14:27:25.12#ibcon#about to read 4, iclass 32, count 2 2006.285.14:27:25.12#ibcon#read 4, iclass 32, count 2 2006.285.14:27:25.12#ibcon#about to read 5, iclass 32, count 2 2006.285.14:27:25.12#ibcon#read 5, iclass 32, count 2 2006.285.14:27:25.12#ibcon#about to read 6, iclass 32, count 2 2006.285.14:27:25.12#ibcon#read 6, iclass 32, count 2 2006.285.14:27:25.12#ibcon#end of sib2, iclass 32, count 2 2006.285.14:27:25.12#ibcon#*after write, iclass 32, count 2 2006.285.14:27:25.12#ibcon#*before return 0, iclass 32, count 2 2006.285.14:27:25.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:27:25.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:27:25.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.14:27:25.12#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:25.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:27:25.20#abcon#<5=/04 1.7 4.1 19.19 951015.1\r\n> 2006.285.14:27:25.22#abcon#{5=INTERFACE CLEAR} 2006.285.14:27:25.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:27:25.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:27:25.24#ibcon#enter wrdev, iclass 32, count 0 2006.285.14:27:25.24#ibcon#first serial, iclass 32, count 0 2006.285.14:27:25.24#ibcon#enter sib2, iclass 32, count 0 2006.285.14:27:25.24#ibcon#flushed, iclass 32, count 0 2006.285.14:27:25.24#ibcon#about to write, iclass 32, count 0 2006.285.14:27:25.24#ibcon#wrote, iclass 32, count 0 2006.285.14:27:25.24#ibcon#about to read 3, iclass 32, count 0 2006.285.14:27:25.26#ibcon#read 3, iclass 32, count 0 2006.285.14:27:25.26#ibcon#about to read 4, iclass 32, count 0 2006.285.14:27:25.26#ibcon#read 4, iclass 32, count 0 2006.285.14:27:25.26#ibcon#about to read 5, iclass 32, count 0 2006.285.14:27:25.26#ibcon#read 5, iclass 32, count 0 2006.285.14:27:25.26#ibcon#about to read 6, iclass 32, count 0 2006.285.14:27:25.26#ibcon#read 6, iclass 32, count 0 2006.285.14:27:25.26#ibcon#end of sib2, iclass 32, count 0 2006.285.14:27:25.26#ibcon#*mode == 0, iclass 32, count 0 2006.285.14:27:25.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.14:27:25.26#ibcon#[27=USB\r\n] 2006.285.14:27:25.26#ibcon#*before write, iclass 32, count 0 2006.285.14:27:25.26#ibcon#enter sib2, iclass 32, count 0 2006.285.14:27:25.26#ibcon#flushed, iclass 32, count 0 2006.285.14:27:25.26#ibcon#about to write, iclass 32, count 0 2006.285.14:27:25.26#ibcon#wrote, iclass 32, count 0 2006.285.14:27:25.26#ibcon#about to read 3, iclass 32, count 0 2006.285.14:27:25.28#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:27:25.29#ibcon#read 3, iclass 32, count 0 2006.285.14:27:25.35#ibcon#about to read 4, iclass 32, count 0 2006.285.14:27:25.35#ibcon#read 4, iclass 32, count 0 2006.285.14:27:25.35#ibcon#about to read 5, iclass 32, count 0 2006.285.14:27:25.35#ibcon#read 5, iclass 32, count 0 2006.285.14:27:25.35#ibcon#about to read 6, iclass 32, count 0 2006.285.14:27:25.35#ibcon#read 6, iclass 32, count 0 2006.285.14:27:25.35#ibcon#end of sib2, iclass 32, count 0 2006.285.14:27:25.35#ibcon#*after write, iclass 32, count 0 2006.285.14:27:25.35#ibcon#*before return 0, iclass 32, count 0 2006.285.14:27:25.35#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:27:25.35#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:27:25.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.14:27:25.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.14:27:25.35$vck44/vblo=7,734.99 2006.285.14:27:25.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.14:27:25.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.14:27:25.35#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:25.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:27:25.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:27:25.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:27:25.35#ibcon#enter wrdev, iclass 38, count 0 2006.285.14:27:25.35#ibcon#first serial, iclass 38, count 0 2006.285.14:27:25.35#ibcon#enter sib2, iclass 38, count 0 2006.285.14:27:25.35#ibcon#flushed, iclass 38, count 0 2006.285.14:27:25.35#ibcon#about to write, iclass 38, count 0 2006.285.14:27:25.35#ibcon#wrote, iclass 38, count 0 2006.285.14:27:25.35#ibcon#about to read 3, iclass 38, count 0 2006.285.14:27:25.36#ibcon#read 3, iclass 38, count 0 2006.285.14:27:25.36#ibcon#about to read 4, iclass 38, count 0 2006.285.14:27:25.36#ibcon#read 4, iclass 38, count 0 2006.285.14:27:25.36#ibcon#about to read 5, iclass 38, count 0 2006.285.14:27:25.36#ibcon#read 5, iclass 38, count 0 2006.285.14:27:25.36#ibcon#about to read 6, iclass 38, count 0 2006.285.14:27:25.36#ibcon#read 6, iclass 38, count 0 2006.285.14:27:25.36#ibcon#end of sib2, iclass 38, count 0 2006.285.14:27:25.36#ibcon#*mode == 0, iclass 38, count 0 2006.285.14:27:25.36#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.14:27:25.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.14:27:25.36#ibcon#*before write, iclass 38, count 0 2006.285.14:27:25.36#ibcon#enter sib2, iclass 38, count 0 2006.285.14:27:25.36#ibcon#flushed, iclass 38, count 0 2006.285.14:27:25.36#ibcon#about to write, iclass 38, count 0 2006.285.14:27:25.36#ibcon#wrote, iclass 38, count 0 2006.285.14:27:25.36#ibcon#about to read 3, iclass 38, count 0 2006.285.14:27:25.40#ibcon#read 3, iclass 38, count 0 2006.285.14:27:25.40#ibcon#about to read 4, iclass 38, count 0 2006.285.14:27:25.40#ibcon#read 4, iclass 38, count 0 2006.285.14:27:25.40#ibcon#about to read 5, iclass 38, count 0 2006.285.14:27:25.40#ibcon#read 5, iclass 38, count 0 2006.285.14:27:25.40#ibcon#about to read 6, iclass 38, count 0 2006.285.14:27:25.40#ibcon#read 6, iclass 38, count 0 2006.285.14:27:25.40#ibcon#end of sib2, iclass 38, count 0 2006.285.14:27:25.40#ibcon#*after write, iclass 38, count 0 2006.285.14:27:25.40#ibcon#*before return 0, iclass 38, count 0 2006.285.14:27:25.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:27:25.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:27:25.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.14:27:25.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.14:27:25.40$vck44/vb=7,4 2006.285.14:27:25.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.14:27:25.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.14:27:25.40#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:25.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:27:25.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:27:25.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:27:25.47#ibcon#enter wrdev, iclass 40, count 2 2006.285.14:27:25.47#ibcon#first serial, iclass 40, count 2 2006.285.14:27:25.47#ibcon#enter sib2, iclass 40, count 2 2006.285.14:27:25.47#ibcon#flushed, iclass 40, count 2 2006.285.14:27:25.47#ibcon#about to write, iclass 40, count 2 2006.285.14:27:25.47#ibcon#wrote, iclass 40, count 2 2006.285.14:27:25.47#ibcon#about to read 3, iclass 40, count 2 2006.285.14:27:25.49#ibcon#read 3, iclass 40, count 2 2006.285.14:27:25.49#ibcon#about to read 4, iclass 40, count 2 2006.285.14:27:25.49#ibcon#read 4, iclass 40, count 2 2006.285.14:27:25.49#ibcon#about to read 5, iclass 40, count 2 2006.285.14:27:25.49#ibcon#read 5, iclass 40, count 2 2006.285.14:27:25.49#ibcon#about to read 6, iclass 40, count 2 2006.285.14:27:25.49#ibcon#read 6, iclass 40, count 2 2006.285.14:27:25.49#ibcon#end of sib2, iclass 40, count 2 2006.285.14:27:25.49#ibcon#*mode == 0, iclass 40, count 2 2006.285.14:27:25.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.14:27:25.49#ibcon#[27=AT07-04\r\n] 2006.285.14:27:25.49#ibcon#*before write, iclass 40, count 2 2006.285.14:27:25.49#ibcon#enter sib2, iclass 40, count 2 2006.285.14:27:25.49#ibcon#flushed, iclass 40, count 2 2006.285.14:27:25.49#ibcon#about to write, iclass 40, count 2 2006.285.14:27:25.49#ibcon#wrote, iclass 40, count 2 2006.285.14:27:25.49#ibcon#about to read 3, iclass 40, count 2 2006.285.14:27:25.52#ibcon#read 3, iclass 40, count 2 2006.285.14:27:25.52#ibcon#about to read 4, iclass 40, count 2 2006.285.14:27:25.52#ibcon#read 4, iclass 40, count 2 2006.285.14:27:25.52#ibcon#about to read 5, iclass 40, count 2 2006.285.14:27:25.52#ibcon#read 5, iclass 40, count 2 2006.285.14:27:25.52#ibcon#about to read 6, iclass 40, count 2 2006.285.14:27:25.52#ibcon#read 6, iclass 40, count 2 2006.285.14:27:25.52#ibcon#end of sib2, iclass 40, count 2 2006.285.14:27:25.52#ibcon#*after write, iclass 40, count 2 2006.285.14:27:25.52#ibcon#*before return 0, iclass 40, count 2 2006.285.14:27:25.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:27:25.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:27:25.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.14:27:25.52#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:25.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:27:25.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:27:25.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:27:25.64#ibcon#enter wrdev, iclass 40, count 0 2006.285.14:27:25.64#ibcon#first serial, iclass 40, count 0 2006.285.14:27:25.64#ibcon#enter sib2, iclass 40, count 0 2006.285.14:27:25.64#ibcon#flushed, iclass 40, count 0 2006.285.14:27:25.64#ibcon#about to write, iclass 40, count 0 2006.285.14:27:25.64#ibcon#wrote, iclass 40, count 0 2006.285.14:27:25.64#ibcon#about to read 3, iclass 40, count 0 2006.285.14:27:25.66#ibcon#read 3, iclass 40, count 0 2006.285.14:27:25.66#ibcon#about to read 4, iclass 40, count 0 2006.285.14:27:25.66#ibcon#read 4, iclass 40, count 0 2006.285.14:27:25.66#ibcon#about to read 5, iclass 40, count 0 2006.285.14:27:25.66#ibcon#read 5, iclass 40, count 0 2006.285.14:27:25.66#ibcon#about to read 6, iclass 40, count 0 2006.285.14:27:25.66#ibcon#read 6, iclass 40, count 0 2006.285.14:27:25.66#ibcon#end of sib2, iclass 40, count 0 2006.285.14:27:25.66#ibcon#*mode == 0, iclass 40, count 0 2006.285.14:27:25.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.14:27:25.66#ibcon#[27=USB\r\n] 2006.285.14:27:25.66#ibcon#*before write, iclass 40, count 0 2006.285.14:27:25.66#ibcon#enter sib2, iclass 40, count 0 2006.285.14:27:25.66#ibcon#flushed, iclass 40, count 0 2006.285.14:27:25.66#ibcon#about to write, iclass 40, count 0 2006.285.14:27:25.66#ibcon#wrote, iclass 40, count 0 2006.285.14:27:25.66#ibcon#about to read 3, iclass 40, count 0 2006.285.14:27:25.69#ibcon#read 3, iclass 40, count 0 2006.285.14:27:25.69#ibcon#about to read 4, iclass 40, count 0 2006.285.14:27:25.69#ibcon#read 4, iclass 40, count 0 2006.285.14:27:25.69#ibcon#about to read 5, iclass 40, count 0 2006.285.14:27:25.69#ibcon#read 5, iclass 40, count 0 2006.285.14:27:25.69#ibcon#about to read 6, iclass 40, count 0 2006.285.14:27:25.69#ibcon#read 6, iclass 40, count 0 2006.285.14:27:25.69#ibcon#end of sib2, iclass 40, count 0 2006.285.14:27:25.69#ibcon#*after write, iclass 40, count 0 2006.285.14:27:25.69#ibcon#*before return 0, iclass 40, count 0 2006.285.14:27:25.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:27:25.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:27:25.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.14:27:25.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.14:27:25.69$vck44/vblo=8,744.99 2006.285.14:27:25.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.14:27:25.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.14:27:25.69#ibcon#ireg 17 cls_cnt 0 2006.285.14:27:25.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:27:25.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:27:25.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:27:25.69#ibcon#enter wrdev, iclass 4, count 0 2006.285.14:27:25.69#ibcon#first serial, iclass 4, count 0 2006.285.14:27:25.69#ibcon#enter sib2, iclass 4, count 0 2006.285.14:27:25.69#ibcon#flushed, iclass 4, count 0 2006.285.14:27:25.69#ibcon#about to write, iclass 4, count 0 2006.285.14:27:25.69#ibcon#wrote, iclass 4, count 0 2006.285.14:27:25.69#ibcon#about to read 3, iclass 4, count 0 2006.285.14:27:25.71#ibcon#read 3, iclass 4, count 0 2006.285.14:27:25.71#ibcon#about to read 4, iclass 4, count 0 2006.285.14:27:25.71#ibcon#read 4, iclass 4, count 0 2006.285.14:27:25.71#ibcon#about to read 5, iclass 4, count 0 2006.285.14:27:25.71#ibcon#read 5, iclass 4, count 0 2006.285.14:27:25.71#ibcon#about to read 6, iclass 4, count 0 2006.285.14:27:25.71#ibcon#read 6, iclass 4, count 0 2006.285.14:27:25.71#ibcon#end of sib2, iclass 4, count 0 2006.285.14:27:25.71#ibcon#*mode == 0, iclass 4, count 0 2006.285.14:27:25.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.14:27:25.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.14:27:25.71#ibcon#*before write, iclass 4, count 0 2006.285.14:27:25.71#ibcon#enter sib2, iclass 4, count 0 2006.285.14:27:25.71#ibcon#flushed, iclass 4, count 0 2006.285.14:27:25.71#ibcon#about to write, iclass 4, count 0 2006.285.14:27:25.71#ibcon#wrote, iclass 4, count 0 2006.285.14:27:25.71#ibcon#about to read 3, iclass 4, count 0 2006.285.14:27:25.75#ibcon#read 3, iclass 4, count 0 2006.285.14:27:25.75#ibcon#about to read 4, iclass 4, count 0 2006.285.14:27:25.75#ibcon#read 4, iclass 4, count 0 2006.285.14:27:25.75#ibcon#about to read 5, iclass 4, count 0 2006.285.14:27:25.75#ibcon#read 5, iclass 4, count 0 2006.285.14:27:25.75#ibcon#about to read 6, iclass 4, count 0 2006.285.14:27:25.75#ibcon#read 6, iclass 4, count 0 2006.285.14:27:25.75#ibcon#end of sib2, iclass 4, count 0 2006.285.14:27:25.75#ibcon#*after write, iclass 4, count 0 2006.285.14:27:25.75#ibcon#*before return 0, iclass 4, count 0 2006.285.14:27:25.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:27:25.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:27:25.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.14:27:25.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.14:27:25.75$vck44/vb=8,4 2006.285.14:27:25.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.14:27:25.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.14:27:25.75#ibcon#ireg 11 cls_cnt 2 2006.285.14:27:25.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:27:25.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:27:25.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:27:25.81#ibcon#enter wrdev, iclass 6, count 2 2006.285.14:27:25.81#ibcon#first serial, iclass 6, count 2 2006.285.14:27:25.81#ibcon#enter sib2, iclass 6, count 2 2006.285.14:27:25.81#ibcon#flushed, iclass 6, count 2 2006.285.14:27:25.81#ibcon#about to write, iclass 6, count 2 2006.285.14:27:25.81#ibcon#wrote, iclass 6, count 2 2006.285.14:27:25.81#ibcon#about to read 3, iclass 6, count 2 2006.285.14:27:25.83#ibcon#read 3, iclass 6, count 2 2006.285.14:27:25.83#ibcon#about to read 4, iclass 6, count 2 2006.285.14:27:25.83#ibcon#read 4, iclass 6, count 2 2006.285.14:27:25.83#ibcon#about to read 5, iclass 6, count 2 2006.285.14:27:25.83#ibcon#read 5, iclass 6, count 2 2006.285.14:27:25.83#ibcon#about to read 6, iclass 6, count 2 2006.285.14:27:25.83#ibcon#read 6, iclass 6, count 2 2006.285.14:27:25.83#ibcon#end of sib2, iclass 6, count 2 2006.285.14:27:25.83#ibcon#*mode == 0, iclass 6, count 2 2006.285.14:27:25.83#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.14:27:25.83#ibcon#[27=AT08-04\r\n] 2006.285.14:27:25.83#ibcon#*before write, iclass 6, count 2 2006.285.14:27:25.83#ibcon#enter sib2, iclass 6, count 2 2006.285.14:27:25.83#ibcon#flushed, iclass 6, count 2 2006.285.14:27:25.83#ibcon#about to write, iclass 6, count 2 2006.285.14:27:25.83#ibcon#wrote, iclass 6, count 2 2006.285.14:27:25.83#ibcon#about to read 3, iclass 6, count 2 2006.285.14:27:25.86#ibcon#read 3, iclass 6, count 2 2006.285.14:27:25.86#ibcon#about to read 4, iclass 6, count 2 2006.285.14:27:25.86#ibcon#read 4, iclass 6, count 2 2006.285.14:27:25.86#ibcon#about to read 5, iclass 6, count 2 2006.285.14:27:25.86#ibcon#read 5, iclass 6, count 2 2006.285.14:27:25.86#ibcon#about to read 6, iclass 6, count 2 2006.285.14:27:25.86#ibcon#read 6, iclass 6, count 2 2006.285.14:27:25.86#ibcon#end of sib2, iclass 6, count 2 2006.285.14:27:25.86#ibcon#*after write, iclass 6, count 2 2006.285.14:27:25.86#ibcon#*before return 0, iclass 6, count 2 2006.285.14:27:25.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:27:25.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:27:25.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.14:27:25.86#ibcon#ireg 7 cls_cnt 0 2006.285.14:27:25.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:27:25.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:27:25.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:27:25.98#ibcon#enter wrdev, iclass 6, count 0 2006.285.14:27:25.98#ibcon#first serial, iclass 6, count 0 2006.285.14:27:25.98#ibcon#enter sib2, iclass 6, count 0 2006.285.14:27:25.98#ibcon#flushed, iclass 6, count 0 2006.285.14:27:25.98#ibcon#about to write, iclass 6, count 0 2006.285.14:27:25.98#ibcon#wrote, iclass 6, count 0 2006.285.14:27:25.98#ibcon#about to read 3, iclass 6, count 0 2006.285.14:27:26.00#ibcon#read 3, iclass 6, count 0 2006.285.14:27:26.00#ibcon#about to read 4, iclass 6, count 0 2006.285.14:27:26.00#ibcon#read 4, iclass 6, count 0 2006.285.14:27:26.00#ibcon#about to read 5, iclass 6, count 0 2006.285.14:27:26.00#ibcon#read 5, iclass 6, count 0 2006.285.14:27:26.00#ibcon#about to read 6, iclass 6, count 0 2006.285.14:27:26.00#ibcon#read 6, iclass 6, count 0 2006.285.14:27:26.00#ibcon#end of sib2, iclass 6, count 0 2006.285.14:27:26.00#ibcon#*mode == 0, iclass 6, count 0 2006.285.14:27:26.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.14:27:26.00#ibcon#[27=USB\r\n] 2006.285.14:27:26.00#ibcon#*before write, iclass 6, count 0 2006.285.14:27:26.00#ibcon#enter sib2, iclass 6, count 0 2006.285.14:27:26.00#ibcon#flushed, iclass 6, count 0 2006.285.14:27:26.00#ibcon#about to write, iclass 6, count 0 2006.285.14:27:26.00#ibcon#wrote, iclass 6, count 0 2006.285.14:27:26.00#ibcon#about to read 3, iclass 6, count 0 2006.285.14:27:26.03#ibcon#read 3, iclass 6, count 0 2006.285.14:27:26.03#ibcon#about to read 4, iclass 6, count 0 2006.285.14:27:26.03#ibcon#read 4, iclass 6, count 0 2006.285.14:27:26.03#ibcon#about to read 5, iclass 6, count 0 2006.285.14:27:26.03#ibcon#read 5, iclass 6, count 0 2006.285.14:27:26.03#ibcon#about to read 6, iclass 6, count 0 2006.285.14:27:26.03#ibcon#read 6, iclass 6, count 0 2006.285.14:27:26.03#ibcon#end of sib2, iclass 6, count 0 2006.285.14:27:26.03#ibcon#*after write, iclass 6, count 0 2006.285.14:27:26.03#ibcon#*before return 0, iclass 6, count 0 2006.285.14:27:26.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:27:26.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:27:26.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.14:27:26.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.14:27:26.03$vck44/vabw=wide 2006.285.14:27:26.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.14:27:26.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.14:27:26.03#ibcon#ireg 8 cls_cnt 0 2006.285.14:27:26.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:27:26.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:27:26.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:27:26.03#ibcon#enter wrdev, iclass 10, count 0 2006.285.14:27:26.03#ibcon#first serial, iclass 10, count 0 2006.285.14:27:26.03#ibcon#enter sib2, iclass 10, count 0 2006.285.14:27:26.03#ibcon#flushed, iclass 10, count 0 2006.285.14:27:26.03#ibcon#about to write, iclass 10, count 0 2006.285.14:27:26.03#ibcon#wrote, iclass 10, count 0 2006.285.14:27:26.03#ibcon#about to read 3, iclass 10, count 0 2006.285.14:27:26.05#ibcon#read 3, iclass 10, count 0 2006.285.14:27:26.05#ibcon#about to read 4, iclass 10, count 0 2006.285.14:27:26.05#ibcon#read 4, iclass 10, count 0 2006.285.14:27:26.05#ibcon#about to read 5, iclass 10, count 0 2006.285.14:27:26.05#ibcon#read 5, iclass 10, count 0 2006.285.14:27:26.05#ibcon#about to read 6, iclass 10, count 0 2006.285.14:27:26.05#ibcon#read 6, iclass 10, count 0 2006.285.14:27:26.05#ibcon#end of sib2, iclass 10, count 0 2006.285.14:27:26.05#ibcon#*mode == 0, iclass 10, count 0 2006.285.14:27:26.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.14:27:26.05#ibcon#[25=BW32\r\n] 2006.285.14:27:26.05#ibcon#*before write, iclass 10, count 0 2006.285.14:27:26.05#ibcon#enter sib2, iclass 10, count 0 2006.285.14:27:26.05#ibcon#flushed, iclass 10, count 0 2006.285.14:27:26.05#ibcon#about to write, iclass 10, count 0 2006.285.14:27:26.05#ibcon#wrote, iclass 10, count 0 2006.285.14:27:26.05#ibcon#about to read 3, iclass 10, count 0 2006.285.14:27:26.08#ibcon#read 3, iclass 10, count 0 2006.285.14:27:26.08#ibcon#about to read 4, iclass 10, count 0 2006.285.14:27:26.08#ibcon#read 4, iclass 10, count 0 2006.285.14:27:26.08#ibcon#about to read 5, iclass 10, count 0 2006.285.14:27:26.08#ibcon#read 5, iclass 10, count 0 2006.285.14:27:26.08#ibcon#about to read 6, iclass 10, count 0 2006.285.14:27:26.08#ibcon#read 6, iclass 10, count 0 2006.285.14:27:26.08#ibcon#end of sib2, iclass 10, count 0 2006.285.14:27:26.08#ibcon#*after write, iclass 10, count 0 2006.285.14:27:26.08#ibcon#*before return 0, iclass 10, count 0 2006.285.14:27:26.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:27:26.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:27:26.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.14:27:26.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.14:27:26.08$vck44/vbbw=wide 2006.285.14:27:26.08#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.14:27:26.08#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.14:27:26.08#ibcon#ireg 8 cls_cnt 0 2006.285.14:27:26.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:27:26.14#trakl#Source acquired 2006.285.14:27:26.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:27:26.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:27:26.15#ibcon#enter wrdev, iclass 12, count 0 2006.285.14:27:26.15#ibcon#first serial, iclass 12, count 0 2006.285.14:27:26.15#ibcon#enter sib2, iclass 12, count 0 2006.285.14:27:26.15#ibcon#flushed, iclass 12, count 0 2006.285.14:27:26.15#ibcon#about to write, iclass 12, count 0 2006.285.14:27:26.15#ibcon#wrote, iclass 12, count 0 2006.285.14:27:26.15#ibcon#about to read 3, iclass 12, count 0 2006.285.14:27:26.17#ibcon#read 3, iclass 12, count 0 2006.285.14:27:26.17#ibcon#about to read 4, iclass 12, count 0 2006.285.14:27:26.17#ibcon#read 4, iclass 12, count 0 2006.285.14:27:26.17#ibcon#about to read 5, iclass 12, count 0 2006.285.14:27:26.17#ibcon#read 5, iclass 12, count 0 2006.285.14:27:26.17#ibcon#about to read 6, iclass 12, count 0 2006.285.14:27:26.17#ibcon#read 6, iclass 12, count 0 2006.285.14:27:26.17#ibcon#end of sib2, iclass 12, count 0 2006.285.14:27:26.17#ibcon#*mode == 0, iclass 12, count 0 2006.285.14:27:26.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.14:27:26.17#ibcon#[27=BW32\r\n] 2006.285.14:27:26.17#ibcon#*before write, iclass 12, count 0 2006.285.14:27:26.17#ibcon#enter sib2, iclass 12, count 0 2006.285.14:27:26.17#ibcon#flushed, iclass 12, count 0 2006.285.14:27:26.17#ibcon#about to write, iclass 12, count 0 2006.285.14:27:26.17#ibcon#wrote, iclass 12, count 0 2006.285.14:27:26.17#ibcon#about to read 3, iclass 12, count 0 2006.285.14:27:26.20#ibcon#read 3, iclass 12, count 0 2006.285.14:27:26.20#ibcon#about to read 4, iclass 12, count 0 2006.285.14:27:26.20#ibcon#read 4, iclass 12, count 0 2006.285.14:27:26.20#ibcon#about to read 5, iclass 12, count 0 2006.285.14:27:26.20#ibcon#read 5, iclass 12, count 0 2006.285.14:27:26.20#ibcon#about to read 6, iclass 12, count 0 2006.285.14:27:26.20#ibcon#read 6, iclass 12, count 0 2006.285.14:27:26.20#ibcon#end of sib2, iclass 12, count 0 2006.285.14:27:26.20#ibcon#*after write, iclass 12, count 0 2006.285.14:27:26.20#ibcon#*before return 0, iclass 12, count 0 2006.285.14:27:26.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:27:26.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:27:26.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.14:27:26.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.14:27:26.20$setupk4/ifdk4 2006.285.14:27:26.45$ifdk4/lo= 2006.285.14:27:26.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.14:27:26.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.14:27:26.46$ifdk4/patch= 2006.285.14:27:26.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.14:27:26.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.14:27:26.46$setupk4/!*+20s 2006.285.14:27:28.14#flagr#flagr/antenna,acquired 2006.285.14:27:35.44#abcon#<5=/04 1.7 4.1 19.19 951015.1\r\n> 2006.285.14:27:35.46#abcon#{5=INTERFACE CLEAR} 2006.285.14:27:35.52#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:27:39.65$setupk4/"tpicd 2006.285.14:27:39.65$setupk4/echo=off 2006.285.14:27:39.65$setupk4/xlog=off 2006.285.14:27:39.65:!2006.285.14:31:33 2006.285.14:31:33.00:preob 2006.285.14:31:33.14/onsource/TRACKING 2006.285.14:31:33.14:!2006.285.14:31:43 2006.285.14:31:43.00:"tape 2006.285.14:31:43.00:"st=record 2006.285.14:31:43.00:data_valid=on 2006.285.14:31:43.00:midob 2006.285.14:31:43.14/onsource/TRACKING 2006.285.14:31:43.14/wx/19.18,1015.1,95 2006.285.14:31:43.28/cable/+6.4998E-03 2006.285.14:31:44.37/va/01,07,usb,yes,33,35 2006.285.14:31:44.37/va/02,06,usb,yes,33,33 2006.285.14:31:44.37/va/03,07,usb,yes,32,34 2006.285.14:31:44.37/va/04,06,usb,yes,34,35 2006.285.14:31:44.37/va/05,03,usb,yes,33,34 2006.285.14:31:44.37/va/06,04,usb,yes,30,29 2006.285.14:31:44.37/va/07,04,usb,yes,31,31 2006.285.14:31:44.37/va/08,03,usb,yes,31,38 2006.285.14:31:44.60/valo/01,524.99,yes,locked 2006.285.14:31:44.60/valo/02,534.99,yes,locked 2006.285.14:31:44.60/valo/03,564.99,yes,locked 2006.285.14:31:44.60/valo/04,624.99,yes,locked 2006.285.14:31:44.60/valo/05,734.99,yes,locked 2006.285.14:31:44.60/valo/06,814.99,yes,locked 2006.285.14:31:44.60/valo/07,864.99,yes,locked 2006.285.14:31:44.60/valo/08,884.99,yes,locked 2006.285.14:31:45.69/vb/01,04,usb,yes,31,29 2006.285.14:31:45.69/vb/02,05,usb,yes,29,29 2006.285.14:31:45.69/vb/03,04,usb,yes,30,33 2006.285.14:31:45.69/vb/04,05,usb,yes,30,29 2006.285.14:31:45.69/vb/05,04,usb,yes,27,29 2006.285.14:31:45.69/vb/06,03,usb,yes,38,34 2006.285.14:31:45.69/vb/07,04,usb,yes,31,31 2006.285.14:31:45.69/vb/08,04,usb,yes,28,32 2006.285.14:31:45.93/vblo/01,629.99,yes,locked 2006.285.14:31:45.93/vblo/02,634.99,yes,locked 2006.285.14:31:45.93/vblo/03,649.99,yes,locked 2006.285.14:31:45.93/vblo/04,679.99,yes,locked 2006.285.14:31:45.93/vblo/05,709.99,yes,locked 2006.285.14:31:45.93/vblo/06,719.99,yes,locked 2006.285.14:31:45.93/vblo/07,734.99,yes,locked 2006.285.14:31:45.93/vblo/08,744.99,yes,locked 2006.285.14:31:46.08/vabw/8 2006.285.14:31:46.23/vbbw/8 2006.285.14:31:46.32/xfe/off,on,12.2 2006.285.14:31:46.69/ifatt/23,28,28,28 2006.285.14:31:47.07/fmout-gps/S +2.95E-07 2006.285.14:31:47.09:!2006.285.14:33:03 2006.285.14:33:03.01:data_valid=off 2006.285.14:33:03.01:"et 2006.285.14:33:03.01:!+3s 2006.285.14:33:06.02:"tape 2006.285.14:33:06.02:postob 2006.285.14:33:06.15/cable/+6.4984E-03 2006.285.14:33:06.15/wx/19.18,1015.1,94 2006.285.14:33:06.21/fmout-gps/S +2.98E-07 2006.285.14:33:06.21:scan_name=285-1435,jd0610,110 2006.285.14:33:06.21:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.285.14:33:07.14#flagr#flagr/antenna,new-source 2006.285.14:33:07.14:checkk5 2006.285.14:33:07.60/chk_autoobs//k5ts1/ autoobs is running! 2006.285.14:33:08.06/chk_autoobs//k5ts2/ autoobs is running! 2006.285.14:33:08.50/chk_autoobs//k5ts3/ autoobs is running! 2006.285.14:33:09.04/chk_autoobs//k5ts4/ autoobs is running! 2006.285.14:33:09.45/chk_obsdata//k5ts1/T2851431??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.14:33:09.91/chk_obsdata//k5ts2/T2851431??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.14:33:10.29/chk_obsdata//k5ts3/T2851431??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.14:33:10.96/chk_obsdata//k5ts4/T2851431??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.285.14:33:11.85/k5log//k5ts1_log_newline 2006.285.14:33:12.63/k5log//k5ts2_log_newline 2006.285.14:33:13.36/k5log//k5ts3_log_newline 2006.285.14:33:14.65/k5log//k5ts4_log_newline 2006.285.14:33:14.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.14:33:14.68:setupk4=1 2006.285.14:33:14.68$setupk4/echo=on 2006.285.14:33:14.68$setupk4/pcalon 2006.285.14:33:14.68$pcalon/"no phase cal control is implemented here 2006.285.14:33:14.68$setupk4/"tpicd=stop 2006.285.14:33:14.68$setupk4/"rec=synch_on 2006.285.14:33:14.68$setupk4/"rec_mode=128 2006.285.14:33:14.68$setupk4/!* 2006.285.14:33:14.68$setupk4/recpk4 2006.285.14:33:14.68$recpk4/recpatch= 2006.285.14:33:14.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.14:33:14.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.14:33:14.68$setupk4/vck44 2006.285.14:33:14.68$vck44/valo=1,524.99 2006.285.14:33:14.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.14:33:14.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.14:33:14.68#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:14.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:33:14.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:33:14.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:33:14.68#ibcon#enter wrdev, iclass 7, count 0 2006.285.14:33:14.68#ibcon#first serial, iclass 7, count 0 2006.285.14:33:14.68#ibcon#enter sib2, iclass 7, count 0 2006.285.14:33:14.68#ibcon#flushed, iclass 7, count 0 2006.285.14:33:14.68#ibcon#about to write, iclass 7, count 0 2006.285.14:33:14.68#ibcon#wrote, iclass 7, count 0 2006.285.14:33:14.68#ibcon#about to read 3, iclass 7, count 0 2006.285.14:33:14.70#ibcon#read 3, iclass 7, count 0 2006.285.14:33:14.70#ibcon#about to read 4, iclass 7, count 0 2006.285.14:33:14.70#ibcon#read 4, iclass 7, count 0 2006.285.14:33:14.70#ibcon#about to read 5, iclass 7, count 0 2006.285.14:33:14.70#ibcon#read 5, iclass 7, count 0 2006.285.14:33:14.70#ibcon#about to read 6, iclass 7, count 0 2006.285.14:33:14.70#ibcon#read 6, iclass 7, count 0 2006.285.14:33:14.70#ibcon#end of sib2, iclass 7, count 0 2006.285.14:33:14.70#ibcon#*mode == 0, iclass 7, count 0 2006.285.14:33:14.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.14:33:14.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.14:33:14.70#ibcon#*before write, iclass 7, count 0 2006.285.14:33:14.70#ibcon#enter sib2, iclass 7, count 0 2006.285.14:33:14.70#ibcon#flushed, iclass 7, count 0 2006.285.14:33:14.70#ibcon#about to write, iclass 7, count 0 2006.285.14:33:14.70#ibcon#wrote, iclass 7, count 0 2006.285.14:33:14.70#ibcon#about to read 3, iclass 7, count 0 2006.285.14:33:14.75#ibcon#read 3, iclass 7, count 0 2006.285.14:33:14.75#ibcon#about to read 4, iclass 7, count 0 2006.285.14:33:14.75#ibcon#read 4, iclass 7, count 0 2006.285.14:33:14.75#ibcon#about to read 5, iclass 7, count 0 2006.285.14:33:14.75#ibcon#read 5, iclass 7, count 0 2006.285.14:33:14.75#ibcon#about to read 6, iclass 7, count 0 2006.285.14:33:14.75#ibcon#read 6, iclass 7, count 0 2006.285.14:33:14.75#ibcon#end of sib2, iclass 7, count 0 2006.285.14:33:14.75#ibcon#*after write, iclass 7, count 0 2006.285.14:33:14.75#ibcon#*before return 0, iclass 7, count 0 2006.285.14:33:14.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:33:14.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:33:14.75#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.14:33:14.75#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.14:33:14.75$vck44/va=1,7 2006.285.14:33:14.75#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.14:33:14.75#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.14:33:14.75#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:14.75#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:33:14.75#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:33:14.75#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:33:14.75#ibcon#enter wrdev, iclass 11, count 2 2006.285.14:33:14.75#ibcon#first serial, iclass 11, count 2 2006.285.14:33:14.75#ibcon#enter sib2, iclass 11, count 2 2006.285.14:33:14.75#ibcon#flushed, iclass 11, count 2 2006.285.14:33:14.75#ibcon#about to write, iclass 11, count 2 2006.285.14:33:14.75#ibcon#wrote, iclass 11, count 2 2006.285.14:33:14.75#ibcon#about to read 3, iclass 11, count 2 2006.285.14:33:14.77#ibcon#read 3, iclass 11, count 2 2006.285.14:33:14.77#ibcon#about to read 4, iclass 11, count 2 2006.285.14:33:14.77#ibcon#read 4, iclass 11, count 2 2006.285.14:33:14.77#ibcon#about to read 5, iclass 11, count 2 2006.285.14:33:14.77#ibcon#read 5, iclass 11, count 2 2006.285.14:33:14.77#ibcon#about to read 6, iclass 11, count 2 2006.285.14:33:14.77#ibcon#read 6, iclass 11, count 2 2006.285.14:33:14.77#ibcon#end of sib2, iclass 11, count 2 2006.285.14:33:14.77#ibcon#*mode == 0, iclass 11, count 2 2006.285.14:33:14.77#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.14:33:14.77#ibcon#[25=AT01-07\r\n] 2006.285.14:33:14.77#ibcon#*before write, iclass 11, count 2 2006.285.14:33:14.77#ibcon#enter sib2, iclass 11, count 2 2006.285.14:33:14.77#ibcon#flushed, iclass 11, count 2 2006.285.14:33:14.77#ibcon#about to write, iclass 11, count 2 2006.285.14:33:14.77#ibcon#wrote, iclass 11, count 2 2006.285.14:33:14.77#ibcon#about to read 3, iclass 11, count 2 2006.285.14:33:14.80#ibcon#read 3, iclass 11, count 2 2006.285.14:33:14.80#ibcon#about to read 4, iclass 11, count 2 2006.285.14:33:14.80#ibcon#read 4, iclass 11, count 2 2006.285.14:33:14.80#ibcon#about to read 5, iclass 11, count 2 2006.285.14:33:14.80#ibcon#read 5, iclass 11, count 2 2006.285.14:33:14.80#ibcon#about to read 6, iclass 11, count 2 2006.285.14:33:14.80#ibcon#read 6, iclass 11, count 2 2006.285.14:33:14.80#ibcon#end of sib2, iclass 11, count 2 2006.285.14:33:14.80#ibcon#*after write, iclass 11, count 2 2006.285.14:33:14.80#ibcon#*before return 0, iclass 11, count 2 2006.285.14:33:14.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:33:14.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:33:14.80#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.14:33:14.80#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:14.80#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:33:14.92#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:33:14.92#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:33:14.92#ibcon#enter wrdev, iclass 11, count 0 2006.285.14:33:14.92#ibcon#first serial, iclass 11, count 0 2006.285.14:33:14.92#ibcon#enter sib2, iclass 11, count 0 2006.285.14:33:14.92#ibcon#flushed, iclass 11, count 0 2006.285.14:33:14.92#ibcon#about to write, iclass 11, count 0 2006.285.14:33:14.92#ibcon#wrote, iclass 11, count 0 2006.285.14:33:14.92#ibcon#about to read 3, iclass 11, count 0 2006.285.14:33:14.94#ibcon#read 3, iclass 11, count 0 2006.285.14:33:14.94#ibcon#about to read 4, iclass 11, count 0 2006.285.14:33:14.94#ibcon#read 4, iclass 11, count 0 2006.285.14:33:14.94#ibcon#about to read 5, iclass 11, count 0 2006.285.14:33:14.94#ibcon#read 5, iclass 11, count 0 2006.285.14:33:14.94#ibcon#about to read 6, iclass 11, count 0 2006.285.14:33:14.94#ibcon#read 6, iclass 11, count 0 2006.285.14:33:14.94#ibcon#end of sib2, iclass 11, count 0 2006.285.14:33:14.94#ibcon#*mode == 0, iclass 11, count 0 2006.285.14:33:14.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.14:33:14.94#ibcon#[25=USB\r\n] 2006.285.14:33:14.94#ibcon#*before write, iclass 11, count 0 2006.285.14:33:14.94#ibcon#enter sib2, iclass 11, count 0 2006.285.14:33:14.94#ibcon#flushed, iclass 11, count 0 2006.285.14:33:14.94#ibcon#about to write, iclass 11, count 0 2006.285.14:33:14.94#ibcon#wrote, iclass 11, count 0 2006.285.14:33:14.94#ibcon#about to read 3, iclass 11, count 0 2006.285.14:33:14.97#ibcon#read 3, iclass 11, count 0 2006.285.14:33:14.97#ibcon#about to read 4, iclass 11, count 0 2006.285.14:33:14.97#ibcon#read 4, iclass 11, count 0 2006.285.14:33:14.97#ibcon#about to read 5, iclass 11, count 0 2006.285.14:33:14.97#ibcon#read 5, iclass 11, count 0 2006.285.14:33:14.97#ibcon#about to read 6, iclass 11, count 0 2006.285.14:33:14.97#ibcon#read 6, iclass 11, count 0 2006.285.14:33:14.97#ibcon#end of sib2, iclass 11, count 0 2006.285.14:33:14.97#ibcon#*after write, iclass 11, count 0 2006.285.14:33:14.97#ibcon#*before return 0, iclass 11, count 0 2006.285.14:33:14.97#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:33:14.97#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:33:14.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.14:33:14.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.14:33:14.97$vck44/valo=2,534.99 2006.285.14:33:14.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.14:33:14.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.14:33:14.97#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:14.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:33:14.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:33:14.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:33:14.97#ibcon#enter wrdev, iclass 13, count 0 2006.285.14:33:14.97#ibcon#first serial, iclass 13, count 0 2006.285.14:33:14.97#ibcon#enter sib2, iclass 13, count 0 2006.285.14:33:14.97#ibcon#flushed, iclass 13, count 0 2006.285.14:33:14.97#ibcon#about to write, iclass 13, count 0 2006.285.14:33:14.97#ibcon#wrote, iclass 13, count 0 2006.285.14:33:14.97#ibcon#about to read 3, iclass 13, count 0 2006.285.14:33:14.99#ibcon#read 3, iclass 13, count 0 2006.285.14:33:14.99#ibcon#about to read 4, iclass 13, count 0 2006.285.14:33:14.99#ibcon#read 4, iclass 13, count 0 2006.285.14:33:14.99#ibcon#about to read 5, iclass 13, count 0 2006.285.14:33:14.99#ibcon#read 5, iclass 13, count 0 2006.285.14:33:14.99#ibcon#about to read 6, iclass 13, count 0 2006.285.14:33:14.99#ibcon#read 6, iclass 13, count 0 2006.285.14:33:14.99#ibcon#end of sib2, iclass 13, count 0 2006.285.14:33:14.99#ibcon#*mode == 0, iclass 13, count 0 2006.285.14:33:14.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.14:33:14.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.14:33:14.99#ibcon#*before write, iclass 13, count 0 2006.285.14:33:14.99#ibcon#enter sib2, iclass 13, count 0 2006.285.14:33:14.99#ibcon#flushed, iclass 13, count 0 2006.285.14:33:14.99#ibcon#about to write, iclass 13, count 0 2006.285.14:33:14.99#ibcon#wrote, iclass 13, count 0 2006.285.14:33:14.99#ibcon#about to read 3, iclass 13, count 0 2006.285.14:33:15.03#ibcon#read 3, iclass 13, count 0 2006.285.14:33:15.03#ibcon#about to read 4, iclass 13, count 0 2006.285.14:33:15.03#ibcon#read 4, iclass 13, count 0 2006.285.14:33:15.03#ibcon#about to read 5, iclass 13, count 0 2006.285.14:33:15.03#ibcon#read 5, iclass 13, count 0 2006.285.14:33:15.03#ibcon#about to read 6, iclass 13, count 0 2006.285.14:33:15.03#ibcon#read 6, iclass 13, count 0 2006.285.14:33:15.03#ibcon#end of sib2, iclass 13, count 0 2006.285.14:33:15.03#ibcon#*after write, iclass 13, count 0 2006.285.14:33:15.03#ibcon#*before return 0, iclass 13, count 0 2006.285.14:33:15.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:33:15.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:33:15.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.14:33:15.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.14:33:15.03$vck44/va=2,6 2006.285.14:33:15.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.14:33:15.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.14:33:15.03#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:15.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:33:15.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:33:15.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:33:15.09#ibcon#enter wrdev, iclass 15, count 2 2006.285.14:33:15.09#ibcon#first serial, iclass 15, count 2 2006.285.14:33:15.09#ibcon#enter sib2, iclass 15, count 2 2006.285.14:33:15.09#ibcon#flushed, iclass 15, count 2 2006.285.14:33:15.09#ibcon#about to write, iclass 15, count 2 2006.285.14:33:15.09#ibcon#wrote, iclass 15, count 2 2006.285.14:33:15.09#ibcon#about to read 3, iclass 15, count 2 2006.285.14:33:15.11#ibcon#read 3, iclass 15, count 2 2006.285.14:33:15.11#ibcon#about to read 4, iclass 15, count 2 2006.285.14:33:15.11#ibcon#read 4, iclass 15, count 2 2006.285.14:33:15.11#ibcon#about to read 5, iclass 15, count 2 2006.285.14:33:15.11#ibcon#read 5, iclass 15, count 2 2006.285.14:33:15.11#ibcon#about to read 6, iclass 15, count 2 2006.285.14:33:15.11#ibcon#read 6, iclass 15, count 2 2006.285.14:33:15.11#ibcon#end of sib2, iclass 15, count 2 2006.285.14:33:15.11#ibcon#*mode == 0, iclass 15, count 2 2006.285.14:33:15.11#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.14:33:15.11#ibcon#[25=AT02-06\r\n] 2006.285.14:33:15.11#ibcon#*before write, iclass 15, count 2 2006.285.14:33:15.11#ibcon#enter sib2, iclass 15, count 2 2006.285.14:33:15.11#ibcon#flushed, iclass 15, count 2 2006.285.14:33:15.11#ibcon#about to write, iclass 15, count 2 2006.285.14:33:15.11#ibcon#wrote, iclass 15, count 2 2006.285.14:33:15.11#ibcon#about to read 3, iclass 15, count 2 2006.285.14:33:15.14#ibcon#read 3, iclass 15, count 2 2006.285.14:33:15.14#ibcon#about to read 4, iclass 15, count 2 2006.285.14:33:15.14#ibcon#read 4, iclass 15, count 2 2006.285.14:33:15.14#ibcon#about to read 5, iclass 15, count 2 2006.285.14:33:15.14#ibcon#read 5, iclass 15, count 2 2006.285.14:33:15.14#ibcon#about to read 6, iclass 15, count 2 2006.285.14:33:15.14#ibcon#read 6, iclass 15, count 2 2006.285.14:33:15.14#ibcon#end of sib2, iclass 15, count 2 2006.285.14:33:15.14#ibcon#*after write, iclass 15, count 2 2006.285.14:33:15.14#ibcon#*before return 0, iclass 15, count 2 2006.285.14:33:15.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:33:15.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:33:15.14#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.14:33:15.14#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:15.14#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:33:15.26#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:33:15.26#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:33:15.26#ibcon#enter wrdev, iclass 15, count 0 2006.285.14:33:15.26#ibcon#first serial, iclass 15, count 0 2006.285.14:33:15.26#ibcon#enter sib2, iclass 15, count 0 2006.285.14:33:15.26#ibcon#flushed, iclass 15, count 0 2006.285.14:33:15.26#ibcon#about to write, iclass 15, count 0 2006.285.14:33:15.26#ibcon#wrote, iclass 15, count 0 2006.285.14:33:15.26#ibcon#about to read 3, iclass 15, count 0 2006.285.14:33:15.28#ibcon#read 3, iclass 15, count 0 2006.285.14:33:15.28#ibcon#about to read 4, iclass 15, count 0 2006.285.14:33:15.28#ibcon#read 4, iclass 15, count 0 2006.285.14:33:15.28#ibcon#about to read 5, iclass 15, count 0 2006.285.14:33:15.28#ibcon#read 5, iclass 15, count 0 2006.285.14:33:15.28#ibcon#about to read 6, iclass 15, count 0 2006.285.14:33:15.28#ibcon#read 6, iclass 15, count 0 2006.285.14:33:15.28#ibcon#end of sib2, iclass 15, count 0 2006.285.14:33:15.28#ibcon#*mode == 0, iclass 15, count 0 2006.285.14:33:15.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.14:33:15.28#ibcon#[25=USB\r\n] 2006.285.14:33:15.28#ibcon#*before write, iclass 15, count 0 2006.285.14:33:15.28#ibcon#enter sib2, iclass 15, count 0 2006.285.14:33:15.28#ibcon#flushed, iclass 15, count 0 2006.285.14:33:15.28#ibcon#about to write, iclass 15, count 0 2006.285.14:33:15.28#ibcon#wrote, iclass 15, count 0 2006.285.14:33:15.28#ibcon#about to read 3, iclass 15, count 0 2006.285.14:33:15.31#ibcon#read 3, iclass 15, count 0 2006.285.14:33:15.31#ibcon#about to read 4, iclass 15, count 0 2006.285.14:33:15.31#ibcon#read 4, iclass 15, count 0 2006.285.14:33:15.31#ibcon#about to read 5, iclass 15, count 0 2006.285.14:33:15.31#ibcon#read 5, iclass 15, count 0 2006.285.14:33:15.31#ibcon#about to read 6, iclass 15, count 0 2006.285.14:33:15.31#ibcon#read 6, iclass 15, count 0 2006.285.14:33:15.31#ibcon#end of sib2, iclass 15, count 0 2006.285.14:33:15.31#ibcon#*after write, iclass 15, count 0 2006.285.14:33:15.31#ibcon#*before return 0, iclass 15, count 0 2006.285.14:33:15.31#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:33:15.31#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:33:15.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.14:33:15.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.14:33:15.31$vck44/valo=3,564.99 2006.285.14:33:15.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.14:33:15.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.14:33:15.31#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:15.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:33:15.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:33:15.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:33:15.31#ibcon#enter wrdev, iclass 17, count 0 2006.285.14:33:15.31#ibcon#first serial, iclass 17, count 0 2006.285.14:33:15.31#ibcon#enter sib2, iclass 17, count 0 2006.285.14:33:15.31#ibcon#flushed, iclass 17, count 0 2006.285.14:33:15.31#ibcon#about to write, iclass 17, count 0 2006.285.14:33:15.31#ibcon#wrote, iclass 17, count 0 2006.285.14:33:15.31#ibcon#about to read 3, iclass 17, count 0 2006.285.14:33:15.33#ibcon#read 3, iclass 17, count 0 2006.285.14:33:15.33#ibcon#about to read 4, iclass 17, count 0 2006.285.14:33:15.33#ibcon#read 4, iclass 17, count 0 2006.285.14:33:15.33#ibcon#about to read 5, iclass 17, count 0 2006.285.14:33:15.33#ibcon#read 5, iclass 17, count 0 2006.285.14:33:15.33#ibcon#about to read 6, iclass 17, count 0 2006.285.14:33:15.33#ibcon#read 6, iclass 17, count 0 2006.285.14:33:15.33#ibcon#end of sib2, iclass 17, count 0 2006.285.14:33:15.33#ibcon#*mode == 0, iclass 17, count 0 2006.285.14:33:15.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.14:33:15.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.14:33:15.33#ibcon#*before write, iclass 17, count 0 2006.285.14:33:15.33#ibcon#enter sib2, iclass 17, count 0 2006.285.14:33:15.33#ibcon#flushed, iclass 17, count 0 2006.285.14:33:15.33#ibcon#about to write, iclass 17, count 0 2006.285.14:33:15.33#ibcon#wrote, iclass 17, count 0 2006.285.14:33:15.33#ibcon#about to read 3, iclass 17, count 0 2006.285.14:33:15.37#ibcon#read 3, iclass 17, count 0 2006.285.14:33:15.37#ibcon#about to read 4, iclass 17, count 0 2006.285.14:33:15.37#ibcon#read 4, iclass 17, count 0 2006.285.14:33:15.37#ibcon#about to read 5, iclass 17, count 0 2006.285.14:33:15.37#ibcon#read 5, iclass 17, count 0 2006.285.14:33:15.37#ibcon#about to read 6, iclass 17, count 0 2006.285.14:33:15.37#ibcon#read 6, iclass 17, count 0 2006.285.14:33:15.37#ibcon#end of sib2, iclass 17, count 0 2006.285.14:33:15.37#ibcon#*after write, iclass 17, count 0 2006.285.14:33:15.37#ibcon#*before return 0, iclass 17, count 0 2006.285.14:33:15.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:33:15.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:33:15.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.14:33:15.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.14:33:15.37$vck44/va=3,7 2006.285.14:33:15.37#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.14:33:15.37#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.14:33:15.37#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:15.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:33:15.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:33:15.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:33:15.43#ibcon#enter wrdev, iclass 19, count 2 2006.285.14:33:15.43#ibcon#first serial, iclass 19, count 2 2006.285.14:33:15.43#ibcon#enter sib2, iclass 19, count 2 2006.285.14:33:15.43#ibcon#flushed, iclass 19, count 2 2006.285.14:33:15.43#ibcon#about to write, iclass 19, count 2 2006.285.14:33:15.43#ibcon#wrote, iclass 19, count 2 2006.285.14:33:15.43#ibcon#about to read 3, iclass 19, count 2 2006.285.14:33:15.45#ibcon#read 3, iclass 19, count 2 2006.285.14:33:15.45#ibcon#about to read 4, iclass 19, count 2 2006.285.14:33:15.45#ibcon#read 4, iclass 19, count 2 2006.285.14:33:15.45#ibcon#about to read 5, iclass 19, count 2 2006.285.14:33:15.45#ibcon#read 5, iclass 19, count 2 2006.285.14:33:15.45#ibcon#about to read 6, iclass 19, count 2 2006.285.14:33:15.45#ibcon#read 6, iclass 19, count 2 2006.285.14:33:15.45#ibcon#end of sib2, iclass 19, count 2 2006.285.14:33:15.45#ibcon#*mode == 0, iclass 19, count 2 2006.285.14:33:15.45#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.14:33:15.45#ibcon#[25=AT03-07\r\n] 2006.285.14:33:15.45#ibcon#*before write, iclass 19, count 2 2006.285.14:33:15.45#ibcon#enter sib2, iclass 19, count 2 2006.285.14:33:15.45#ibcon#flushed, iclass 19, count 2 2006.285.14:33:15.45#ibcon#about to write, iclass 19, count 2 2006.285.14:33:15.45#ibcon#wrote, iclass 19, count 2 2006.285.14:33:15.45#ibcon#about to read 3, iclass 19, count 2 2006.285.14:33:15.48#ibcon#read 3, iclass 19, count 2 2006.285.14:33:15.48#ibcon#about to read 4, iclass 19, count 2 2006.285.14:33:15.48#ibcon#read 4, iclass 19, count 2 2006.285.14:33:15.48#ibcon#about to read 5, iclass 19, count 2 2006.285.14:33:15.48#ibcon#read 5, iclass 19, count 2 2006.285.14:33:15.48#ibcon#about to read 6, iclass 19, count 2 2006.285.14:33:15.48#ibcon#read 6, iclass 19, count 2 2006.285.14:33:15.48#ibcon#end of sib2, iclass 19, count 2 2006.285.14:33:15.48#ibcon#*after write, iclass 19, count 2 2006.285.14:33:15.48#ibcon#*before return 0, iclass 19, count 2 2006.285.14:33:15.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:33:15.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:33:15.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.14:33:15.48#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:15.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:33:15.60#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:33:15.60#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:33:15.60#ibcon#enter wrdev, iclass 19, count 0 2006.285.14:33:15.60#ibcon#first serial, iclass 19, count 0 2006.285.14:33:15.60#ibcon#enter sib2, iclass 19, count 0 2006.285.14:33:15.60#ibcon#flushed, iclass 19, count 0 2006.285.14:33:15.60#ibcon#about to write, iclass 19, count 0 2006.285.14:33:15.60#ibcon#wrote, iclass 19, count 0 2006.285.14:33:15.60#ibcon#about to read 3, iclass 19, count 0 2006.285.14:33:15.62#ibcon#read 3, iclass 19, count 0 2006.285.14:33:15.62#ibcon#about to read 4, iclass 19, count 0 2006.285.14:33:15.62#ibcon#read 4, iclass 19, count 0 2006.285.14:33:15.62#ibcon#about to read 5, iclass 19, count 0 2006.285.14:33:15.62#ibcon#read 5, iclass 19, count 0 2006.285.14:33:15.62#ibcon#about to read 6, iclass 19, count 0 2006.285.14:33:15.62#ibcon#read 6, iclass 19, count 0 2006.285.14:33:15.62#ibcon#end of sib2, iclass 19, count 0 2006.285.14:33:15.62#ibcon#*mode == 0, iclass 19, count 0 2006.285.14:33:15.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.14:33:15.62#ibcon#[25=USB\r\n] 2006.285.14:33:15.62#ibcon#*before write, iclass 19, count 0 2006.285.14:33:15.62#ibcon#enter sib2, iclass 19, count 0 2006.285.14:33:15.62#ibcon#flushed, iclass 19, count 0 2006.285.14:33:15.62#ibcon#about to write, iclass 19, count 0 2006.285.14:33:15.62#ibcon#wrote, iclass 19, count 0 2006.285.14:33:15.62#ibcon#about to read 3, iclass 19, count 0 2006.285.14:33:15.65#ibcon#read 3, iclass 19, count 0 2006.285.14:33:15.65#ibcon#about to read 4, iclass 19, count 0 2006.285.14:33:15.65#ibcon#read 4, iclass 19, count 0 2006.285.14:33:15.65#ibcon#about to read 5, iclass 19, count 0 2006.285.14:33:15.65#ibcon#read 5, iclass 19, count 0 2006.285.14:33:15.65#ibcon#about to read 6, iclass 19, count 0 2006.285.14:33:15.65#ibcon#read 6, iclass 19, count 0 2006.285.14:33:15.65#ibcon#end of sib2, iclass 19, count 0 2006.285.14:33:15.65#ibcon#*after write, iclass 19, count 0 2006.285.14:33:15.65#ibcon#*before return 0, iclass 19, count 0 2006.285.14:33:15.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:33:15.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:33:15.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.14:33:15.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.14:33:15.65$vck44/valo=4,624.99 2006.285.14:33:15.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.14:33:15.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.14:33:15.65#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:15.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:33:15.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:33:15.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:33:15.65#ibcon#enter wrdev, iclass 21, count 0 2006.285.14:33:15.65#ibcon#first serial, iclass 21, count 0 2006.285.14:33:15.65#ibcon#enter sib2, iclass 21, count 0 2006.285.14:33:15.65#ibcon#flushed, iclass 21, count 0 2006.285.14:33:15.65#ibcon#about to write, iclass 21, count 0 2006.285.14:33:15.65#ibcon#wrote, iclass 21, count 0 2006.285.14:33:15.65#ibcon#about to read 3, iclass 21, count 0 2006.285.14:33:15.67#ibcon#read 3, iclass 21, count 0 2006.285.14:33:16.20#ibcon#about to read 4, iclass 21, count 0 2006.285.14:33:16.20#ibcon#read 4, iclass 21, count 0 2006.285.14:33:16.20#ibcon#about to read 5, iclass 21, count 0 2006.285.14:33:16.20#ibcon#read 5, iclass 21, count 0 2006.285.14:33:16.20#ibcon#about to read 6, iclass 21, count 0 2006.285.14:33:16.20#ibcon#read 6, iclass 21, count 0 2006.285.14:33:16.20#ibcon#end of sib2, iclass 21, count 0 2006.285.14:33:16.20#ibcon#*mode == 0, iclass 21, count 0 2006.285.14:33:16.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.14:33:16.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.14:33:16.20#ibcon#*before write, iclass 21, count 0 2006.285.14:33:16.20#ibcon#enter sib2, iclass 21, count 0 2006.285.14:33:16.20#ibcon#flushed, iclass 21, count 0 2006.285.14:33:16.20#ibcon#about to write, iclass 21, count 0 2006.285.14:33:16.20#ibcon#wrote, iclass 21, count 0 2006.285.14:33:16.20#ibcon#about to read 3, iclass 21, count 0 2006.285.14:33:16.25#ibcon#read 3, iclass 21, count 0 2006.285.14:33:16.25#ibcon#about to read 4, iclass 21, count 0 2006.285.14:33:16.25#ibcon#read 4, iclass 21, count 0 2006.285.14:33:16.25#ibcon#about to read 5, iclass 21, count 0 2006.285.14:33:16.25#ibcon#read 5, iclass 21, count 0 2006.285.14:33:16.25#ibcon#about to read 6, iclass 21, count 0 2006.285.14:33:16.25#ibcon#read 6, iclass 21, count 0 2006.285.14:33:16.25#ibcon#end of sib2, iclass 21, count 0 2006.285.14:33:16.25#ibcon#*after write, iclass 21, count 0 2006.285.14:33:16.25#ibcon#*before return 0, iclass 21, count 0 2006.285.14:33:16.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:33:16.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:33:16.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.14:33:16.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.14:33:16.25$vck44/va=4,6 2006.285.14:33:16.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.14:33:16.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.14:33:16.25#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:16.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:33:16.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:33:16.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:33:16.25#ibcon#enter wrdev, iclass 23, count 2 2006.285.14:33:16.25#ibcon#first serial, iclass 23, count 2 2006.285.14:33:16.25#ibcon#enter sib2, iclass 23, count 2 2006.285.14:33:16.25#ibcon#flushed, iclass 23, count 2 2006.285.14:33:16.25#ibcon#about to write, iclass 23, count 2 2006.285.14:33:16.25#ibcon#wrote, iclass 23, count 2 2006.285.14:33:16.25#ibcon#about to read 3, iclass 23, count 2 2006.285.14:33:16.27#ibcon#read 3, iclass 23, count 2 2006.285.14:33:16.27#ibcon#about to read 4, iclass 23, count 2 2006.285.14:33:16.27#ibcon#read 4, iclass 23, count 2 2006.285.14:33:16.27#ibcon#about to read 5, iclass 23, count 2 2006.285.14:33:16.27#ibcon#read 5, iclass 23, count 2 2006.285.14:33:16.27#ibcon#about to read 6, iclass 23, count 2 2006.285.14:33:16.27#ibcon#read 6, iclass 23, count 2 2006.285.14:33:16.27#ibcon#end of sib2, iclass 23, count 2 2006.285.14:33:16.27#ibcon#*mode == 0, iclass 23, count 2 2006.285.14:33:16.27#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.14:33:16.27#ibcon#[25=AT04-06\r\n] 2006.285.14:33:16.27#ibcon#*before write, iclass 23, count 2 2006.285.14:33:16.27#ibcon#enter sib2, iclass 23, count 2 2006.285.14:33:16.27#ibcon#flushed, iclass 23, count 2 2006.285.14:33:16.27#ibcon#about to write, iclass 23, count 2 2006.285.14:33:16.27#ibcon#wrote, iclass 23, count 2 2006.285.14:33:16.27#ibcon#about to read 3, iclass 23, count 2 2006.285.14:33:16.30#ibcon#read 3, iclass 23, count 2 2006.285.14:33:16.30#ibcon#about to read 4, iclass 23, count 2 2006.285.14:33:16.30#ibcon#read 4, iclass 23, count 2 2006.285.14:33:16.30#ibcon#about to read 5, iclass 23, count 2 2006.285.14:33:16.30#ibcon#read 5, iclass 23, count 2 2006.285.14:33:16.30#ibcon#about to read 6, iclass 23, count 2 2006.285.14:33:16.30#ibcon#read 6, iclass 23, count 2 2006.285.14:33:16.30#ibcon#end of sib2, iclass 23, count 2 2006.285.14:33:16.30#ibcon#*after write, iclass 23, count 2 2006.285.14:33:16.30#ibcon#*before return 0, iclass 23, count 2 2006.285.14:33:16.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:33:16.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:33:16.30#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.14:33:16.30#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:16.30#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:33:16.42#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:33:16.42#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:33:16.42#ibcon#enter wrdev, iclass 23, count 0 2006.285.14:33:16.42#ibcon#first serial, iclass 23, count 0 2006.285.14:33:16.42#ibcon#enter sib2, iclass 23, count 0 2006.285.14:33:16.42#ibcon#flushed, iclass 23, count 0 2006.285.14:33:16.42#ibcon#about to write, iclass 23, count 0 2006.285.14:33:16.42#ibcon#wrote, iclass 23, count 0 2006.285.14:33:16.42#ibcon#about to read 3, iclass 23, count 0 2006.285.14:33:16.44#ibcon#read 3, iclass 23, count 0 2006.285.14:33:16.44#ibcon#about to read 4, iclass 23, count 0 2006.285.14:33:16.44#ibcon#read 4, iclass 23, count 0 2006.285.14:33:16.44#ibcon#about to read 5, iclass 23, count 0 2006.285.14:33:16.44#ibcon#read 5, iclass 23, count 0 2006.285.14:33:16.44#ibcon#about to read 6, iclass 23, count 0 2006.285.14:33:16.44#ibcon#read 6, iclass 23, count 0 2006.285.14:33:16.44#ibcon#end of sib2, iclass 23, count 0 2006.285.14:33:16.44#ibcon#*mode == 0, iclass 23, count 0 2006.285.14:33:16.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.14:33:16.44#ibcon#[25=USB\r\n] 2006.285.14:33:16.44#ibcon#*before write, iclass 23, count 0 2006.285.14:33:16.44#ibcon#enter sib2, iclass 23, count 0 2006.285.14:33:16.44#ibcon#flushed, iclass 23, count 0 2006.285.14:33:16.44#ibcon#about to write, iclass 23, count 0 2006.285.14:33:16.44#ibcon#wrote, iclass 23, count 0 2006.285.14:33:16.44#ibcon#about to read 3, iclass 23, count 0 2006.285.14:33:16.47#ibcon#read 3, iclass 23, count 0 2006.285.14:33:16.47#ibcon#about to read 4, iclass 23, count 0 2006.285.14:33:16.47#ibcon#read 4, iclass 23, count 0 2006.285.14:33:16.47#ibcon#about to read 5, iclass 23, count 0 2006.285.14:33:16.47#ibcon#read 5, iclass 23, count 0 2006.285.14:33:16.47#ibcon#about to read 6, iclass 23, count 0 2006.285.14:33:16.47#ibcon#read 6, iclass 23, count 0 2006.285.14:33:16.47#ibcon#end of sib2, iclass 23, count 0 2006.285.14:33:16.47#ibcon#*after write, iclass 23, count 0 2006.285.14:33:16.47#ibcon#*before return 0, iclass 23, count 0 2006.285.14:33:16.47#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:33:16.47#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:33:16.47#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.14:33:16.47#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.14:33:16.47$vck44/valo=5,734.99 2006.285.14:33:16.47#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.14:33:16.47#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.14:33:16.47#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:16.47#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:33:16.47#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:33:16.47#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:33:16.47#ibcon#enter wrdev, iclass 25, count 0 2006.285.14:33:16.47#ibcon#first serial, iclass 25, count 0 2006.285.14:33:16.47#ibcon#enter sib2, iclass 25, count 0 2006.285.14:33:16.47#ibcon#flushed, iclass 25, count 0 2006.285.14:33:16.47#ibcon#about to write, iclass 25, count 0 2006.285.14:33:16.47#ibcon#wrote, iclass 25, count 0 2006.285.14:33:16.47#ibcon#about to read 3, iclass 25, count 0 2006.285.14:33:16.49#ibcon#read 3, iclass 25, count 0 2006.285.14:33:16.72#ibcon#about to read 4, iclass 25, count 0 2006.285.14:33:16.72#ibcon#read 4, iclass 25, count 0 2006.285.14:33:16.72#ibcon#about to read 5, iclass 25, count 0 2006.285.14:33:16.72#ibcon#read 5, iclass 25, count 0 2006.285.14:33:16.72#ibcon#about to read 6, iclass 25, count 0 2006.285.14:33:16.72#ibcon#read 6, iclass 25, count 0 2006.285.14:33:16.72#ibcon#end of sib2, iclass 25, count 0 2006.285.14:33:16.72#ibcon#*mode == 0, iclass 25, count 0 2006.285.14:33:16.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.14:33:16.72#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.14:33:16.72#ibcon#*before write, iclass 25, count 0 2006.285.14:33:16.72#ibcon#enter sib2, iclass 25, count 0 2006.285.14:33:16.72#ibcon#flushed, iclass 25, count 0 2006.285.14:33:16.72#ibcon#about to write, iclass 25, count 0 2006.285.14:33:16.72#ibcon#wrote, iclass 25, count 0 2006.285.14:33:16.72#ibcon#about to read 3, iclass 25, count 0 2006.285.14:33:16.77#ibcon#read 3, iclass 25, count 0 2006.285.14:33:16.77#ibcon#about to read 4, iclass 25, count 0 2006.285.14:33:16.77#ibcon#read 4, iclass 25, count 0 2006.285.14:33:16.77#ibcon#about to read 5, iclass 25, count 0 2006.285.14:33:16.77#ibcon#read 5, iclass 25, count 0 2006.285.14:33:16.77#ibcon#about to read 6, iclass 25, count 0 2006.285.14:33:16.77#ibcon#read 6, iclass 25, count 0 2006.285.14:33:16.77#ibcon#end of sib2, iclass 25, count 0 2006.285.14:33:16.77#ibcon#*after write, iclass 25, count 0 2006.285.14:33:16.77#ibcon#*before return 0, iclass 25, count 0 2006.285.14:33:16.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:33:16.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:33:16.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.14:33:16.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.14:33:16.77$vck44/va=5,3 2006.285.14:33:16.77#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.14:33:16.77#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.14:33:16.77#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:16.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:33:16.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:33:16.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:33:16.77#ibcon#enter wrdev, iclass 27, count 2 2006.285.14:33:16.77#ibcon#first serial, iclass 27, count 2 2006.285.14:33:16.77#ibcon#enter sib2, iclass 27, count 2 2006.285.14:33:16.77#ibcon#flushed, iclass 27, count 2 2006.285.14:33:16.77#ibcon#about to write, iclass 27, count 2 2006.285.14:33:16.77#ibcon#wrote, iclass 27, count 2 2006.285.14:33:16.77#ibcon#about to read 3, iclass 27, count 2 2006.285.14:33:16.79#ibcon#read 3, iclass 27, count 2 2006.285.14:33:16.79#ibcon#about to read 4, iclass 27, count 2 2006.285.14:33:16.79#ibcon#read 4, iclass 27, count 2 2006.285.14:33:16.79#ibcon#about to read 5, iclass 27, count 2 2006.285.14:33:16.79#ibcon#read 5, iclass 27, count 2 2006.285.14:33:16.79#ibcon#about to read 6, iclass 27, count 2 2006.285.14:33:16.79#ibcon#read 6, iclass 27, count 2 2006.285.14:33:16.79#ibcon#end of sib2, iclass 27, count 2 2006.285.14:33:16.79#ibcon#*mode == 0, iclass 27, count 2 2006.285.14:33:16.79#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.14:33:16.79#ibcon#[25=AT05-03\r\n] 2006.285.14:33:16.79#ibcon#*before write, iclass 27, count 2 2006.285.14:33:16.79#ibcon#enter sib2, iclass 27, count 2 2006.285.14:33:16.79#ibcon#flushed, iclass 27, count 2 2006.285.14:33:16.79#ibcon#about to write, iclass 27, count 2 2006.285.14:33:16.79#ibcon#wrote, iclass 27, count 2 2006.285.14:33:16.79#ibcon#about to read 3, iclass 27, count 2 2006.285.14:33:16.82#ibcon#read 3, iclass 27, count 2 2006.285.14:33:16.82#ibcon#about to read 4, iclass 27, count 2 2006.285.14:33:16.82#ibcon#read 4, iclass 27, count 2 2006.285.14:33:16.82#ibcon#about to read 5, iclass 27, count 2 2006.285.14:33:16.82#ibcon#read 5, iclass 27, count 2 2006.285.14:33:16.82#ibcon#about to read 6, iclass 27, count 2 2006.285.14:33:16.82#ibcon#read 6, iclass 27, count 2 2006.285.14:33:16.82#ibcon#end of sib2, iclass 27, count 2 2006.285.14:33:16.82#ibcon#*after write, iclass 27, count 2 2006.285.14:33:16.82#ibcon#*before return 0, iclass 27, count 2 2006.285.14:33:16.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:33:16.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:33:16.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.14:33:16.82#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:16.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:33:16.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:33:16.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:33:16.94#ibcon#enter wrdev, iclass 27, count 0 2006.285.14:33:16.94#ibcon#first serial, iclass 27, count 0 2006.285.14:33:16.94#ibcon#enter sib2, iclass 27, count 0 2006.285.14:33:16.94#ibcon#flushed, iclass 27, count 0 2006.285.14:33:16.94#ibcon#about to write, iclass 27, count 0 2006.285.14:33:16.94#ibcon#wrote, iclass 27, count 0 2006.285.14:33:16.94#ibcon#about to read 3, iclass 27, count 0 2006.285.14:33:16.96#ibcon#read 3, iclass 27, count 0 2006.285.14:33:16.96#ibcon#about to read 4, iclass 27, count 0 2006.285.14:33:16.96#ibcon#read 4, iclass 27, count 0 2006.285.14:33:16.96#ibcon#about to read 5, iclass 27, count 0 2006.285.14:33:16.96#ibcon#read 5, iclass 27, count 0 2006.285.14:33:16.96#ibcon#about to read 6, iclass 27, count 0 2006.285.14:33:16.96#ibcon#read 6, iclass 27, count 0 2006.285.14:33:16.96#ibcon#end of sib2, iclass 27, count 0 2006.285.14:33:16.96#ibcon#*mode == 0, iclass 27, count 0 2006.285.14:33:16.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.14:33:16.96#ibcon#[25=USB\r\n] 2006.285.14:33:16.96#ibcon#*before write, iclass 27, count 0 2006.285.14:33:16.96#ibcon#enter sib2, iclass 27, count 0 2006.285.14:33:16.96#ibcon#flushed, iclass 27, count 0 2006.285.14:33:16.96#ibcon#about to write, iclass 27, count 0 2006.285.14:33:16.96#ibcon#wrote, iclass 27, count 0 2006.285.14:33:16.96#ibcon#about to read 3, iclass 27, count 0 2006.285.14:33:16.99#ibcon#read 3, iclass 27, count 0 2006.285.14:33:16.99#ibcon#about to read 4, iclass 27, count 0 2006.285.14:33:16.99#ibcon#read 4, iclass 27, count 0 2006.285.14:33:16.99#ibcon#about to read 5, iclass 27, count 0 2006.285.14:33:16.99#ibcon#read 5, iclass 27, count 0 2006.285.14:33:16.99#ibcon#about to read 6, iclass 27, count 0 2006.285.14:33:16.99#ibcon#read 6, iclass 27, count 0 2006.285.14:33:16.99#ibcon#end of sib2, iclass 27, count 0 2006.285.14:33:16.99#ibcon#*after write, iclass 27, count 0 2006.285.14:33:16.99#ibcon#*before return 0, iclass 27, count 0 2006.285.14:33:16.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:33:16.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:33:16.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.14:33:16.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.14:33:16.99$vck44/valo=6,814.99 2006.285.14:33:16.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.14:33:16.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.14:33:16.99#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:16.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:33:16.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:33:16.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:33:16.99#ibcon#enter wrdev, iclass 29, count 0 2006.285.14:33:16.99#ibcon#first serial, iclass 29, count 0 2006.285.14:33:16.99#ibcon#enter sib2, iclass 29, count 0 2006.285.14:33:16.99#ibcon#flushed, iclass 29, count 0 2006.285.14:33:16.99#ibcon#about to write, iclass 29, count 0 2006.285.14:33:16.99#ibcon#wrote, iclass 29, count 0 2006.285.14:33:16.99#ibcon#about to read 3, iclass 29, count 0 2006.285.14:33:17.01#ibcon#read 3, iclass 29, count 0 2006.285.14:33:17.01#ibcon#about to read 4, iclass 29, count 0 2006.285.14:33:17.01#ibcon#read 4, iclass 29, count 0 2006.285.14:33:17.01#ibcon#about to read 5, iclass 29, count 0 2006.285.14:33:17.01#ibcon#read 5, iclass 29, count 0 2006.285.14:33:17.01#ibcon#about to read 6, iclass 29, count 0 2006.285.14:33:17.01#ibcon#read 6, iclass 29, count 0 2006.285.14:33:17.01#ibcon#end of sib2, iclass 29, count 0 2006.285.14:33:17.01#ibcon#*mode == 0, iclass 29, count 0 2006.285.14:33:17.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.14:33:17.01#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.14:33:17.01#ibcon#*before write, iclass 29, count 0 2006.285.14:33:17.01#ibcon#enter sib2, iclass 29, count 0 2006.285.14:33:17.01#ibcon#flushed, iclass 29, count 0 2006.285.14:33:17.01#ibcon#about to write, iclass 29, count 0 2006.285.14:33:17.01#ibcon#wrote, iclass 29, count 0 2006.285.14:33:17.01#ibcon#about to read 3, iclass 29, count 0 2006.285.14:33:17.05#ibcon#read 3, iclass 29, count 0 2006.285.14:33:17.05#ibcon#about to read 4, iclass 29, count 0 2006.285.14:33:17.05#ibcon#read 4, iclass 29, count 0 2006.285.14:33:17.05#ibcon#about to read 5, iclass 29, count 0 2006.285.14:33:17.05#ibcon#read 5, iclass 29, count 0 2006.285.14:33:17.05#ibcon#about to read 6, iclass 29, count 0 2006.285.14:33:17.05#ibcon#read 6, iclass 29, count 0 2006.285.14:33:17.05#ibcon#end of sib2, iclass 29, count 0 2006.285.14:33:17.05#ibcon#*after write, iclass 29, count 0 2006.285.14:33:17.05#ibcon#*before return 0, iclass 29, count 0 2006.285.14:33:17.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:33:17.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:33:17.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.14:33:17.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.14:33:17.05$vck44/va=6,4 2006.285.14:33:17.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.14:33:17.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.14:33:17.05#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:17.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:33:17.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:33:17.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:33:17.11#ibcon#enter wrdev, iclass 31, count 2 2006.285.14:33:17.11#ibcon#first serial, iclass 31, count 2 2006.285.14:33:17.11#ibcon#enter sib2, iclass 31, count 2 2006.285.14:33:17.11#ibcon#flushed, iclass 31, count 2 2006.285.14:33:17.11#ibcon#about to write, iclass 31, count 2 2006.285.14:33:17.11#ibcon#wrote, iclass 31, count 2 2006.285.14:33:17.11#ibcon#about to read 3, iclass 31, count 2 2006.285.14:33:17.13#ibcon#read 3, iclass 31, count 2 2006.285.14:33:17.13#ibcon#about to read 4, iclass 31, count 2 2006.285.14:33:17.13#ibcon#read 4, iclass 31, count 2 2006.285.14:33:17.13#ibcon#about to read 5, iclass 31, count 2 2006.285.14:33:17.13#ibcon#read 5, iclass 31, count 2 2006.285.14:33:17.13#ibcon#about to read 6, iclass 31, count 2 2006.285.14:33:17.13#ibcon#read 6, iclass 31, count 2 2006.285.14:33:17.13#ibcon#end of sib2, iclass 31, count 2 2006.285.14:33:17.13#ibcon#*mode == 0, iclass 31, count 2 2006.285.14:33:17.13#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.14:33:17.13#ibcon#[25=AT06-04\r\n] 2006.285.14:33:17.13#ibcon#*before write, iclass 31, count 2 2006.285.14:33:17.13#ibcon#enter sib2, iclass 31, count 2 2006.285.14:33:17.13#ibcon#flushed, iclass 31, count 2 2006.285.14:33:17.13#ibcon#about to write, iclass 31, count 2 2006.285.14:33:17.13#ibcon#wrote, iclass 31, count 2 2006.285.14:33:17.13#ibcon#about to read 3, iclass 31, count 2 2006.285.14:33:17.16#ibcon#read 3, iclass 31, count 2 2006.285.14:33:17.16#ibcon#about to read 4, iclass 31, count 2 2006.285.14:33:17.16#ibcon#read 4, iclass 31, count 2 2006.285.14:33:17.16#ibcon#about to read 5, iclass 31, count 2 2006.285.14:33:17.16#ibcon#read 5, iclass 31, count 2 2006.285.14:33:17.16#ibcon#about to read 6, iclass 31, count 2 2006.285.14:33:17.16#ibcon#read 6, iclass 31, count 2 2006.285.14:33:17.16#ibcon#end of sib2, iclass 31, count 2 2006.285.14:33:17.16#ibcon#*after write, iclass 31, count 2 2006.285.14:33:17.16#ibcon#*before return 0, iclass 31, count 2 2006.285.14:33:17.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:33:17.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:33:17.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.14:33:17.16#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:17.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:33:17.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:33:17.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:33:17.28#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:33:17.28#ibcon#first serial, iclass 31, count 0 2006.285.14:33:17.28#ibcon#enter sib2, iclass 31, count 0 2006.285.14:33:17.28#ibcon#flushed, iclass 31, count 0 2006.285.14:33:17.28#ibcon#about to write, iclass 31, count 0 2006.285.14:33:17.28#ibcon#wrote, iclass 31, count 0 2006.285.14:33:17.28#ibcon#about to read 3, iclass 31, count 0 2006.285.14:33:17.30#ibcon#read 3, iclass 31, count 0 2006.285.14:33:17.30#ibcon#about to read 4, iclass 31, count 0 2006.285.14:33:17.30#ibcon#read 4, iclass 31, count 0 2006.285.14:33:17.30#ibcon#about to read 5, iclass 31, count 0 2006.285.14:33:17.30#ibcon#read 5, iclass 31, count 0 2006.285.14:33:17.30#ibcon#about to read 6, iclass 31, count 0 2006.285.14:33:17.30#ibcon#read 6, iclass 31, count 0 2006.285.14:33:17.30#ibcon#end of sib2, iclass 31, count 0 2006.285.14:33:17.30#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:33:17.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:33:17.30#ibcon#[25=USB\r\n] 2006.285.14:33:17.30#ibcon#*before write, iclass 31, count 0 2006.285.14:33:17.30#ibcon#enter sib2, iclass 31, count 0 2006.285.14:33:17.30#ibcon#flushed, iclass 31, count 0 2006.285.14:33:17.30#ibcon#about to write, iclass 31, count 0 2006.285.14:33:17.30#ibcon#wrote, iclass 31, count 0 2006.285.14:33:17.30#ibcon#about to read 3, iclass 31, count 0 2006.285.14:33:17.33#ibcon#read 3, iclass 31, count 0 2006.285.14:33:17.33#ibcon#about to read 4, iclass 31, count 0 2006.285.14:33:17.33#ibcon#read 4, iclass 31, count 0 2006.285.14:33:17.33#ibcon#about to read 5, iclass 31, count 0 2006.285.14:33:17.33#ibcon#read 5, iclass 31, count 0 2006.285.14:33:17.33#ibcon#about to read 6, iclass 31, count 0 2006.285.14:33:17.33#ibcon#read 6, iclass 31, count 0 2006.285.14:33:17.33#ibcon#end of sib2, iclass 31, count 0 2006.285.14:33:17.33#ibcon#*after write, iclass 31, count 0 2006.285.14:33:17.33#ibcon#*before return 0, iclass 31, count 0 2006.285.14:33:17.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:33:17.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:33:17.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:33:17.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:33:17.33$vck44/valo=7,864.99 2006.285.14:33:17.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.14:33:17.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.14:33:17.33#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:17.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:33:17.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:33:17.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:33:17.33#ibcon#enter wrdev, iclass 33, count 0 2006.285.14:33:17.33#ibcon#first serial, iclass 33, count 0 2006.285.14:33:17.33#ibcon#enter sib2, iclass 33, count 0 2006.285.14:33:17.33#ibcon#flushed, iclass 33, count 0 2006.285.14:33:17.33#ibcon#about to write, iclass 33, count 0 2006.285.14:33:17.33#ibcon#wrote, iclass 33, count 0 2006.285.14:33:17.33#ibcon#about to read 3, iclass 33, count 0 2006.285.14:33:17.35#ibcon#read 3, iclass 33, count 0 2006.285.14:33:17.35#ibcon#about to read 4, iclass 33, count 0 2006.285.14:33:17.35#ibcon#read 4, iclass 33, count 0 2006.285.14:33:17.35#ibcon#about to read 5, iclass 33, count 0 2006.285.14:33:17.35#ibcon#read 5, iclass 33, count 0 2006.285.14:33:17.35#ibcon#about to read 6, iclass 33, count 0 2006.285.14:33:17.35#ibcon#read 6, iclass 33, count 0 2006.285.14:33:17.35#ibcon#end of sib2, iclass 33, count 0 2006.285.14:33:17.35#ibcon#*mode == 0, iclass 33, count 0 2006.285.14:33:17.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.14:33:17.35#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.14:33:17.35#ibcon#*before write, iclass 33, count 0 2006.285.14:33:17.35#ibcon#enter sib2, iclass 33, count 0 2006.285.14:33:17.35#ibcon#flushed, iclass 33, count 0 2006.285.14:33:17.35#ibcon#about to write, iclass 33, count 0 2006.285.14:33:17.35#ibcon#wrote, iclass 33, count 0 2006.285.14:33:17.35#ibcon#about to read 3, iclass 33, count 0 2006.285.14:33:17.39#ibcon#read 3, iclass 33, count 0 2006.285.14:33:17.39#ibcon#about to read 4, iclass 33, count 0 2006.285.14:33:17.39#ibcon#read 4, iclass 33, count 0 2006.285.14:33:17.39#ibcon#about to read 5, iclass 33, count 0 2006.285.14:33:17.39#ibcon#read 5, iclass 33, count 0 2006.285.14:33:17.39#ibcon#about to read 6, iclass 33, count 0 2006.285.14:33:17.39#ibcon#read 6, iclass 33, count 0 2006.285.14:33:17.39#ibcon#end of sib2, iclass 33, count 0 2006.285.14:33:17.39#ibcon#*after write, iclass 33, count 0 2006.285.14:33:17.39#ibcon#*before return 0, iclass 33, count 0 2006.285.14:33:17.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:33:17.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:33:17.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.14:33:17.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.14:33:17.39$vck44/va=7,4 2006.285.14:33:17.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.14:33:17.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.14:33:17.39#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:17.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:33:17.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:33:17.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:33:17.45#ibcon#enter wrdev, iclass 35, count 2 2006.285.14:33:17.45#ibcon#first serial, iclass 35, count 2 2006.285.14:33:17.45#ibcon#enter sib2, iclass 35, count 2 2006.285.14:33:17.45#ibcon#flushed, iclass 35, count 2 2006.285.14:33:17.45#ibcon#about to write, iclass 35, count 2 2006.285.14:33:17.45#ibcon#wrote, iclass 35, count 2 2006.285.14:33:17.45#ibcon#about to read 3, iclass 35, count 2 2006.285.14:33:17.47#ibcon#read 3, iclass 35, count 2 2006.285.14:33:17.47#ibcon#about to read 4, iclass 35, count 2 2006.285.14:33:17.47#ibcon#read 4, iclass 35, count 2 2006.285.14:33:17.47#ibcon#about to read 5, iclass 35, count 2 2006.285.14:33:17.47#ibcon#read 5, iclass 35, count 2 2006.285.14:33:17.47#ibcon#about to read 6, iclass 35, count 2 2006.285.14:33:17.47#ibcon#read 6, iclass 35, count 2 2006.285.14:33:17.47#ibcon#end of sib2, iclass 35, count 2 2006.285.14:33:17.47#ibcon#*mode == 0, iclass 35, count 2 2006.285.14:33:17.47#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.14:33:17.47#ibcon#[25=AT07-04\r\n] 2006.285.14:33:17.47#ibcon#*before write, iclass 35, count 2 2006.285.14:33:17.47#ibcon#enter sib2, iclass 35, count 2 2006.285.14:33:17.47#ibcon#flushed, iclass 35, count 2 2006.285.14:33:17.47#ibcon#about to write, iclass 35, count 2 2006.285.14:33:17.47#ibcon#wrote, iclass 35, count 2 2006.285.14:33:17.47#ibcon#about to read 3, iclass 35, count 2 2006.285.14:33:17.50#ibcon#read 3, iclass 35, count 2 2006.285.14:33:17.50#ibcon#about to read 4, iclass 35, count 2 2006.285.14:33:17.50#ibcon#read 4, iclass 35, count 2 2006.285.14:33:17.50#ibcon#about to read 5, iclass 35, count 2 2006.285.14:33:17.50#ibcon#read 5, iclass 35, count 2 2006.285.14:33:17.50#ibcon#about to read 6, iclass 35, count 2 2006.285.14:33:17.50#ibcon#read 6, iclass 35, count 2 2006.285.14:33:17.50#ibcon#end of sib2, iclass 35, count 2 2006.285.14:33:17.50#ibcon#*after write, iclass 35, count 2 2006.285.14:33:17.50#ibcon#*before return 0, iclass 35, count 2 2006.285.14:33:17.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:33:17.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:33:17.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.14:33:17.50#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:17.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:33:17.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:33:17.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:33:17.62#ibcon#enter wrdev, iclass 35, count 0 2006.285.14:33:17.62#ibcon#first serial, iclass 35, count 0 2006.285.14:33:17.62#ibcon#enter sib2, iclass 35, count 0 2006.285.14:33:17.62#ibcon#flushed, iclass 35, count 0 2006.285.14:33:17.62#ibcon#about to write, iclass 35, count 0 2006.285.14:33:17.62#ibcon#wrote, iclass 35, count 0 2006.285.14:33:17.62#ibcon#about to read 3, iclass 35, count 0 2006.285.14:33:17.64#ibcon#read 3, iclass 35, count 0 2006.285.14:33:17.64#ibcon#about to read 4, iclass 35, count 0 2006.285.14:33:17.64#ibcon#read 4, iclass 35, count 0 2006.285.14:33:17.64#ibcon#about to read 5, iclass 35, count 0 2006.285.14:33:17.64#ibcon#read 5, iclass 35, count 0 2006.285.14:33:17.64#ibcon#about to read 6, iclass 35, count 0 2006.285.14:33:17.64#ibcon#read 6, iclass 35, count 0 2006.285.14:33:17.64#ibcon#end of sib2, iclass 35, count 0 2006.285.14:33:17.64#ibcon#*mode == 0, iclass 35, count 0 2006.285.14:33:17.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.14:33:17.64#ibcon#[25=USB\r\n] 2006.285.14:33:17.64#ibcon#*before write, iclass 35, count 0 2006.285.14:33:17.64#ibcon#enter sib2, iclass 35, count 0 2006.285.14:33:17.64#ibcon#flushed, iclass 35, count 0 2006.285.14:33:17.64#ibcon#about to write, iclass 35, count 0 2006.285.14:33:17.64#ibcon#wrote, iclass 35, count 0 2006.285.14:33:17.64#ibcon#about to read 3, iclass 35, count 0 2006.285.14:33:17.67#ibcon#read 3, iclass 35, count 0 2006.285.14:33:17.67#ibcon#about to read 4, iclass 35, count 0 2006.285.14:33:17.67#ibcon#read 4, iclass 35, count 0 2006.285.14:33:17.67#ibcon#about to read 5, iclass 35, count 0 2006.285.14:33:17.67#ibcon#read 5, iclass 35, count 0 2006.285.14:33:17.67#ibcon#about to read 6, iclass 35, count 0 2006.285.14:33:17.67#ibcon#read 6, iclass 35, count 0 2006.285.14:33:17.67#ibcon#end of sib2, iclass 35, count 0 2006.285.14:33:17.67#ibcon#*after write, iclass 35, count 0 2006.285.14:33:17.67#ibcon#*before return 0, iclass 35, count 0 2006.285.14:33:17.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:33:17.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:33:17.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.14:33:17.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.14:33:17.67$vck44/valo=8,884.99 2006.285.14:33:17.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.14:33:17.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.14:33:17.67#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:17.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:33:17.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:33:17.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:33:17.67#ibcon#enter wrdev, iclass 37, count 0 2006.285.14:33:17.67#ibcon#first serial, iclass 37, count 0 2006.285.14:33:17.67#ibcon#enter sib2, iclass 37, count 0 2006.285.14:33:17.67#ibcon#flushed, iclass 37, count 0 2006.285.14:33:17.67#ibcon#about to write, iclass 37, count 0 2006.285.14:33:17.67#ibcon#wrote, iclass 37, count 0 2006.285.14:33:17.67#ibcon#about to read 3, iclass 37, count 0 2006.285.14:33:17.69#ibcon#read 3, iclass 37, count 0 2006.285.14:33:18.05#ibcon#about to read 4, iclass 37, count 0 2006.285.14:33:18.05#ibcon#read 4, iclass 37, count 0 2006.285.14:33:18.05#ibcon#about to read 5, iclass 37, count 0 2006.285.14:33:18.05#ibcon#read 5, iclass 37, count 0 2006.285.14:33:18.05#ibcon#about to read 6, iclass 37, count 0 2006.285.14:33:18.05#ibcon#read 6, iclass 37, count 0 2006.285.14:33:18.05#ibcon#end of sib2, iclass 37, count 0 2006.285.14:33:18.05#ibcon#*mode == 0, iclass 37, count 0 2006.285.14:33:18.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.14:33:18.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.14:33:18.05#ibcon#*before write, iclass 37, count 0 2006.285.14:33:18.05#ibcon#enter sib2, iclass 37, count 0 2006.285.14:33:18.05#ibcon#flushed, iclass 37, count 0 2006.285.14:33:18.05#ibcon#about to write, iclass 37, count 0 2006.285.14:33:18.05#ibcon#wrote, iclass 37, count 0 2006.285.14:33:18.05#ibcon#about to read 3, iclass 37, count 0 2006.285.14:33:18.09#ibcon#read 3, iclass 37, count 0 2006.285.14:33:18.09#ibcon#about to read 4, iclass 37, count 0 2006.285.14:33:18.09#ibcon#read 4, iclass 37, count 0 2006.285.14:33:18.09#ibcon#about to read 5, iclass 37, count 0 2006.285.14:33:18.09#ibcon#read 5, iclass 37, count 0 2006.285.14:33:18.09#ibcon#about to read 6, iclass 37, count 0 2006.285.14:33:18.09#ibcon#read 6, iclass 37, count 0 2006.285.14:33:18.09#ibcon#end of sib2, iclass 37, count 0 2006.285.14:33:18.09#ibcon#*after write, iclass 37, count 0 2006.285.14:33:18.09#ibcon#*before return 0, iclass 37, count 0 2006.285.14:33:18.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:33:18.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:33:18.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.14:33:18.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.14:33:18.09$vck44/va=8,3 2006.285.14:33:18.09#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.14:33:18.09#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.14:33:18.09#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:18.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:33:18.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:33:18.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:33:18.09#ibcon#enter wrdev, iclass 39, count 2 2006.285.14:33:18.09#ibcon#first serial, iclass 39, count 2 2006.285.14:33:18.09#ibcon#enter sib2, iclass 39, count 2 2006.285.14:33:18.09#ibcon#flushed, iclass 39, count 2 2006.285.14:33:18.09#ibcon#about to write, iclass 39, count 2 2006.285.14:33:18.09#ibcon#wrote, iclass 39, count 2 2006.285.14:33:18.09#ibcon#about to read 3, iclass 39, count 2 2006.285.14:33:18.11#ibcon#read 3, iclass 39, count 2 2006.285.14:33:18.11#ibcon#about to read 4, iclass 39, count 2 2006.285.14:33:18.11#ibcon#read 4, iclass 39, count 2 2006.285.14:33:18.11#ibcon#about to read 5, iclass 39, count 2 2006.285.14:33:18.11#ibcon#read 5, iclass 39, count 2 2006.285.14:33:18.11#ibcon#about to read 6, iclass 39, count 2 2006.285.14:33:18.11#ibcon#read 6, iclass 39, count 2 2006.285.14:33:18.11#ibcon#end of sib2, iclass 39, count 2 2006.285.14:33:18.11#ibcon#*mode == 0, iclass 39, count 2 2006.285.14:33:18.11#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.14:33:18.11#ibcon#[25=AT08-03\r\n] 2006.285.14:33:18.11#ibcon#*before write, iclass 39, count 2 2006.285.14:33:18.11#ibcon#enter sib2, iclass 39, count 2 2006.285.14:33:18.11#ibcon#flushed, iclass 39, count 2 2006.285.14:33:18.11#ibcon#about to write, iclass 39, count 2 2006.285.14:33:18.11#ibcon#wrote, iclass 39, count 2 2006.285.14:33:18.11#ibcon#about to read 3, iclass 39, count 2 2006.285.14:33:18.14#ibcon#read 3, iclass 39, count 2 2006.285.14:33:18.14#ibcon#about to read 4, iclass 39, count 2 2006.285.14:33:18.14#ibcon#read 4, iclass 39, count 2 2006.285.14:33:18.14#ibcon#about to read 5, iclass 39, count 2 2006.285.14:33:18.14#ibcon#read 5, iclass 39, count 2 2006.285.14:33:18.14#ibcon#about to read 6, iclass 39, count 2 2006.285.14:33:18.14#ibcon#read 6, iclass 39, count 2 2006.285.14:33:18.14#ibcon#end of sib2, iclass 39, count 2 2006.285.14:33:18.14#ibcon#*after write, iclass 39, count 2 2006.285.14:33:18.14#ibcon#*before return 0, iclass 39, count 2 2006.285.14:33:18.14#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:33:18.14#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:33:18.14#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.14:33:18.14#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:18.14#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:33:18.26#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:33:18.26#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:33:18.26#ibcon#enter wrdev, iclass 39, count 0 2006.285.14:33:18.26#ibcon#first serial, iclass 39, count 0 2006.285.14:33:18.26#ibcon#enter sib2, iclass 39, count 0 2006.285.14:33:18.26#ibcon#flushed, iclass 39, count 0 2006.285.14:33:18.26#ibcon#about to write, iclass 39, count 0 2006.285.14:33:18.26#ibcon#wrote, iclass 39, count 0 2006.285.14:33:18.26#ibcon#about to read 3, iclass 39, count 0 2006.285.14:33:18.28#ibcon#read 3, iclass 39, count 0 2006.285.14:33:18.28#ibcon#about to read 4, iclass 39, count 0 2006.285.14:33:18.28#ibcon#read 4, iclass 39, count 0 2006.285.14:33:18.28#ibcon#about to read 5, iclass 39, count 0 2006.285.14:33:18.28#ibcon#read 5, iclass 39, count 0 2006.285.14:33:18.28#ibcon#about to read 6, iclass 39, count 0 2006.285.14:33:18.28#ibcon#read 6, iclass 39, count 0 2006.285.14:33:18.28#ibcon#end of sib2, iclass 39, count 0 2006.285.14:33:18.28#ibcon#*mode == 0, iclass 39, count 0 2006.285.14:33:18.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.14:33:18.28#ibcon#[25=USB\r\n] 2006.285.14:33:18.28#ibcon#*before write, iclass 39, count 0 2006.285.14:33:18.28#ibcon#enter sib2, iclass 39, count 0 2006.285.14:33:18.28#ibcon#flushed, iclass 39, count 0 2006.285.14:33:18.28#ibcon#about to write, iclass 39, count 0 2006.285.14:33:18.28#ibcon#wrote, iclass 39, count 0 2006.285.14:33:18.28#ibcon#about to read 3, iclass 39, count 0 2006.285.14:33:18.31#ibcon#read 3, iclass 39, count 0 2006.285.14:33:18.31#ibcon#about to read 4, iclass 39, count 0 2006.285.14:33:18.31#ibcon#read 4, iclass 39, count 0 2006.285.14:33:18.31#ibcon#about to read 5, iclass 39, count 0 2006.285.14:33:18.31#ibcon#read 5, iclass 39, count 0 2006.285.14:33:18.31#ibcon#about to read 6, iclass 39, count 0 2006.285.14:33:18.31#ibcon#read 6, iclass 39, count 0 2006.285.14:33:18.31#ibcon#end of sib2, iclass 39, count 0 2006.285.14:33:18.31#ibcon#*after write, iclass 39, count 0 2006.285.14:33:18.31#ibcon#*before return 0, iclass 39, count 0 2006.285.14:33:18.31#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:33:18.31#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:33:18.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.14:33:18.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.14:33:18.31$vck44/vblo=1,629.99 2006.285.14:33:18.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.14:33:18.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.14:33:18.31#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:18.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:33:18.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:33:18.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:33:18.31#ibcon#enter wrdev, iclass 3, count 0 2006.285.14:33:18.31#ibcon#first serial, iclass 3, count 0 2006.285.14:33:18.31#ibcon#enter sib2, iclass 3, count 0 2006.285.14:33:18.31#ibcon#flushed, iclass 3, count 0 2006.285.14:33:18.31#ibcon#about to write, iclass 3, count 0 2006.285.14:33:18.31#ibcon#wrote, iclass 3, count 0 2006.285.14:33:18.31#ibcon#about to read 3, iclass 3, count 0 2006.285.14:33:18.33#ibcon#read 3, iclass 3, count 0 2006.285.14:33:18.33#ibcon#about to read 4, iclass 3, count 0 2006.285.14:33:18.33#ibcon#read 4, iclass 3, count 0 2006.285.14:33:18.33#ibcon#about to read 5, iclass 3, count 0 2006.285.14:33:18.33#ibcon#read 5, iclass 3, count 0 2006.285.14:33:18.33#ibcon#about to read 6, iclass 3, count 0 2006.285.14:33:18.33#ibcon#read 6, iclass 3, count 0 2006.285.14:33:18.33#ibcon#end of sib2, iclass 3, count 0 2006.285.14:33:18.33#ibcon#*mode == 0, iclass 3, count 0 2006.285.14:33:18.33#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.14:33:18.33#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.14:33:18.33#ibcon#*before write, iclass 3, count 0 2006.285.14:33:18.33#ibcon#enter sib2, iclass 3, count 0 2006.285.14:33:18.33#ibcon#flushed, iclass 3, count 0 2006.285.14:33:18.33#ibcon#about to write, iclass 3, count 0 2006.285.14:33:18.33#ibcon#wrote, iclass 3, count 0 2006.285.14:33:18.33#ibcon#about to read 3, iclass 3, count 0 2006.285.14:33:18.37#ibcon#read 3, iclass 3, count 0 2006.285.14:33:18.37#ibcon#about to read 4, iclass 3, count 0 2006.285.14:33:18.37#ibcon#read 4, iclass 3, count 0 2006.285.14:33:18.37#ibcon#about to read 5, iclass 3, count 0 2006.285.14:33:18.37#ibcon#read 5, iclass 3, count 0 2006.285.14:33:18.37#ibcon#about to read 6, iclass 3, count 0 2006.285.14:33:18.37#ibcon#read 6, iclass 3, count 0 2006.285.14:33:18.37#ibcon#end of sib2, iclass 3, count 0 2006.285.14:33:18.37#ibcon#*after write, iclass 3, count 0 2006.285.14:33:18.37#ibcon#*before return 0, iclass 3, count 0 2006.285.14:33:18.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:33:18.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:33:18.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.14:33:18.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.14:33:18.37$vck44/vb=1,4 2006.285.14:33:18.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.14:33:18.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.14:33:18.37#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:18.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:33:18.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:33:18.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:33:18.37#ibcon#enter wrdev, iclass 5, count 2 2006.285.14:33:18.37#ibcon#first serial, iclass 5, count 2 2006.285.14:33:18.37#ibcon#enter sib2, iclass 5, count 2 2006.285.14:33:18.37#ibcon#flushed, iclass 5, count 2 2006.285.14:33:18.37#ibcon#about to write, iclass 5, count 2 2006.285.14:33:18.37#ibcon#wrote, iclass 5, count 2 2006.285.14:33:18.37#ibcon#about to read 3, iclass 5, count 2 2006.285.14:33:18.39#ibcon#read 3, iclass 5, count 2 2006.285.14:33:18.39#ibcon#about to read 4, iclass 5, count 2 2006.285.14:33:18.39#ibcon#read 4, iclass 5, count 2 2006.285.14:33:18.39#ibcon#about to read 5, iclass 5, count 2 2006.285.14:33:18.39#ibcon#read 5, iclass 5, count 2 2006.285.14:33:18.39#ibcon#about to read 6, iclass 5, count 2 2006.285.14:33:18.39#ibcon#read 6, iclass 5, count 2 2006.285.14:33:18.39#ibcon#end of sib2, iclass 5, count 2 2006.285.14:33:18.39#ibcon#*mode == 0, iclass 5, count 2 2006.285.14:33:18.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.14:33:18.39#ibcon#[27=AT01-04\r\n] 2006.285.14:33:18.39#ibcon#*before write, iclass 5, count 2 2006.285.14:33:18.39#ibcon#enter sib2, iclass 5, count 2 2006.285.14:33:18.39#ibcon#flushed, iclass 5, count 2 2006.285.14:33:18.39#ibcon#about to write, iclass 5, count 2 2006.285.14:33:18.39#ibcon#wrote, iclass 5, count 2 2006.285.14:33:18.39#ibcon#about to read 3, iclass 5, count 2 2006.285.14:33:18.42#ibcon#read 3, iclass 5, count 2 2006.285.14:33:18.42#ibcon#about to read 4, iclass 5, count 2 2006.285.14:33:18.42#ibcon#read 4, iclass 5, count 2 2006.285.14:33:18.42#ibcon#about to read 5, iclass 5, count 2 2006.285.14:33:18.42#ibcon#read 5, iclass 5, count 2 2006.285.14:33:18.42#ibcon#about to read 6, iclass 5, count 2 2006.285.14:33:18.42#ibcon#read 6, iclass 5, count 2 2006.285.14:33:18.42#ibcon#end of sib2, iclass 5, count 2 2006.285.14:33:18.42#ibcon#*after write, iclass 5, count 2 2006.285.14:33:18.42#ibcon#*before return 0, iclass 5, count 2 2006.285.14:33:18.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:33:18.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:33:18.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.14:33:18.42#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:18.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:33:18.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:33:18.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:33:18.54#ibcon#enter wrdev, iclass 5, count 0 2006.285.14:33:18.54#ibcon#first serial, iclass 5, count 0 2006.285.14:33:18.54#ibcon#enter sib2, iclass 5, count 0 2006.285.14:33:18.54#ibcon#flushed, iclass 5, count 0 2006.285.14:33:18.54#ibcon#about to write, iclass 5, count 0 2006.285.14:33:18.54#ibcon#wrote, iclass 5, count 0 2006.285.14:33:18.54#ibcon#about to read 3, iclass 5, count 0 2006.285.14:33:18.56#ibcon#read 3, iclass 5, count 0 2006.285.14:33:18.56#ibcon#about to read 4, iclass 5, count 0 2006.285.14:33:18.56#ibcon#read 4, iclass 5, count 0 2006.285.14:33:18.56#ibcon#about to read 5, iclass 5, count 0 2006.285.14:33:18.56#ibcon#read 5, iclass 5, count 0 2006.285.14:33:18.56#ibcon#about to read 6, iclass 5, count 0 2006.285.14:33:18.56#ibcon#read 6, iclass 5, count 0 2006.285.14:33:18.56#ibcon#end of sib2, iclass 5, count 0 2006.285.14:33:18.56#ibcon#*mode == 0, iclass 5, count 0 2006.285.14:33:18.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.14:33:18.56#ibcon#[27=USB\r\n] 2006.285.14:33:18.56#ibcon#*before write, iclass 5, count 0 2006.285.14:33:18.56#ibcon#enter sib2, iclass 5, count 0 2006.285.14:33:18.56#ibcon#flushed, iclass 5, count 0 2006.285.14:33:18.56#ibcon#about to write, iclass 5, count 0 2006.285.14:33:18.56#ibcon#wrote, iclass 5, count 0 2006.285.14:33:18.56#ibcon#about to read 3, iclass 5, count 0 2006.285.14:33:18.59#ibcon#read 3, iclass 5, count 0 2006.285.14:33:18.59#ibcon#about to read 4, iclass 5, count 0 2006.285.14:33:18.59#ibcon#read 4, iclass 5, count 0 2006.285.14:33:18.59#ibcon#about to read 5, iclass 5, count 0 2006.285.14:33:18.59#ibcon#read 5, iclass 5, count 0 2006.285.14:33:18.59#ibcon#about to read 6, iclass 5, count 0 2006.285.14:33:18.59#ibcon#read 6, iclass 5, count 0 2006.285.14:33:18.59#ibcon#end of sib2, iclass 5, count 0 2006.285.14:33:18.59#ibcon#*after write, iclass 5, count 0 2006.285.14:33:18.59#ibcon#*before return 0, iclass 5, count 0 2006.285.14:33:18.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:33:18.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:33:18.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.14:33:18.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.14:33:18.59$vck44/vblo=2,634.99 2006.285.14:33:18.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.14:33:18.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.14:33:18.59#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:18.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:33:18.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:33:18.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:33:18.59#ibcon#enter wrdev, iclass 7, count 0 2006.285.14:33:18.59#ibcon#first serial, iclass 7, count 0 2006.285.14:33:18.59#ibcon#enter sib2, iclass 7, count 0 2006.285.14:33:18.59#ibcon#flushed, iclass 7, count 0 2006.285.14:33:18.59#ibcon#about to write, iclass 7, count 0 2006.285.14:33:18.59#ibcon#wrote, iclass 7, count 0 2006.285.14:33:18.59#ibcon#about to read 3, iclass 7, count 0 2006.285.14:33:18.61#ibcon#read 3, iclass 7, count 0 2006.285.14:33:18.61#ibcon#about to read 4, iclass 7, count 0 2006.285.14:33:18.61#ibcon#read 4, iclass 7, count 0 2006.285.14:33:18.61#ibcon#about to read 5, iclass 7, count 0 2006.285.14:33:18.61#ibcon#read 5, iclass 7, count 0 2006.285.14:33:18.61#ibcon#about to read 6, iclass 7, count 0 2006.285.14:33:18.61#ibcon#read 6, iclass 7, count 0 2006.285.14:33:18.61#ibcon#end of sib2, iclass 7, count 0 2006.285.14:33:18.61#ibcon#*mode == 0, iclass 7, count 0 2006.285.14:33:18.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.14:33:18.61#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.14:33:18.61#ibcon#*before write, iclass 7, count 0 2006.285.14:33:18.61#ibcon#enter sib2, iclass 7, count 0 2006.285.14:33:18.61#ibcon#flushed, iclass 7, count 0 2006.285.14:33:18.61#ibcon#about to write, iclass 7, count 0 2006.285.14:33:18.61#ibcon#wrote, iclass 7, count 0 2006.285.14:33:18.61#ibcon#about to read 3, iclass 7, count 0 2006.285.14:33:18.65#ibcon#read 3, iclass 7, count 0 2006.285.14:33:18.65#ibcon#about to read 4, iclass 7, count 0 2006.285.14:33:18.65#ibcon#read 4, iclass 7, count 0 2006.285.14:33:18.65#ibcon#about to read 5, iclass 7, count 0 2006.285.14:33:18.65#ibcon#read 5, iclass 7, count 0 2006.285.14:33:18.65#ibcon#about to read 6, iclass 7, count 0 2006.285.14:33:18.65#ibcon#read 6, iclass 7, count 0 2006.285.14:33:18.65#ibcon#end of sib2, iclass 7, count 0 2006.285.14:33:18.65#ibcon#*after write, iclass 7, count 0 2006.285.14:33:18.65#ibcon#*before return 0, iclass 7, count 0 2006.285.14:33:18.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:33:18.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:33:18.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.14:33:18.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.14:33:18.65$vck44/vb=2,5 2006.285.14:33:18.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.14:33:18.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.14:33:18.65#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:18.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:33:18.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:33:18.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:33:18.71#ibcon#enter wrdev, iclass 11, count 2 2006.285.14:33:18.71#ibcon#first serial, iclass 11, count 2 2006.285.14:33:18.71#ibcon#enter sib2, iclass 11, count 2 2006.285.14:33:18.71#ibcon#flushed, iclass 11, count 2 2006.285.14:33:18.71#ibcon#about to write, iclass 11, count 2 2006.285.14:33:18.71#ibcon#wrote, iclass 11, count 2 2006.285.14:33:18.71#ibcon#about to read 3, iclass 11, count 2 2006.285.14:33:18.73#ibcon#read 3, iclass 11, count 2 2006.285.14:33:18.73#ibcon#about to read 4, iclass 11, count 2 2006.285.14:33:18.73#ibcon#read 4, iclass 11, count 2 2006.285.14:33:18.73#ibcon#about to read 5, iclass 11, count 2 2006.285.14:33:18.73#ibcon#read 5, iclass 11, count 2 2006.285.14:33:18.73#ibcon#about to read 6, iclass 11, count 2 2006.285.14:33:18.73#ibcon#read 6, iclass 11, count 2 2006.285.14:33:18.73#ibcon#end of sib2, iclass 11, count 2 2006.285.14:33:18.73#ibcon#*mode == 0, iclass 11, count 2 2006.285.14:33:18.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.14:33:18.73#ibcon#[27=AT02-05\r\n] 2006.285.14:33:18.73#ibcon#*before write, iclass 11, count 2 2006.285.14:33:18.73#ibcon#enter sib2, iclass 11, count 2 2006.285.14:33:18.73#ibcon#flushed, iclass 11, count 2 2006.285.14:33:18.73#ibcon#about to write, iclass 11, count 2 2006.285.14:33:18.73#ibcon#wrote, iclass 11, count 2 2006.285.14:33:18.73#ibcon#about to read 3, iclass 11, count 2 2006.285.14:33:18.76#ibcon#read 3, iclass 11, count 2 2006.285.14:33:18.76#ibcon#about to read 4, iclass 11, count 2 2006.285.14:33:18.76#ibcon#read 4, iclass 11, count 2 2006.285.14:33:18.76#ibcon#about to read 5, iclass 11, count 2 2006.285.14:33:18.76#ibcon#read 5, iclass 11, count 2 2006.285.14:33:18.76#ibcon#about to read 6, iclass 11, count 2 2006.285.14:33:18.76#ibcon#read 6, iclass 11, count 2 2006.285.14:33:18.76#ibcon#end of sib2, iclass 11, count 2 2006.285.14:33:18.76#ibcon#*after write, iclass 11, count 2 2006.285.14:33:18.76#ibcon#*before return 0, iclass 11, count 2 2006.285.14:33:18.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:33:18.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:33:18.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.14:33:18.76#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:18.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:33:18.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:33:18.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:33:18.88#ibcon#enter wrdev, iclass 11, count 0 2006.285.14:33:18.88#ibcon#first serial, iclass 11, count 0 2006.285.14:33:18.88#ibcon#enter sib2, iclass 11, count 0 2006.285.14:33:18.88#ibcon#flushed, iclass 11, count 0 2006.285.14:33:18.88#ibcon#about to write, iclass 11, count 0 2006.285.14:33:18.88#ibcon#wrote, iclass 11, count 0 2006.285.14:33:18.88#ibcon#about to read 3, iclass 11, count 0 2006.285.14:33:18.90#ibcon#read 3, iclass 11, count 0 2006.285.14:33:18.90#ibcon#about to read 4, iclass 11, count 0 2006.285.14:33:18.90#ibcon#read 4, iclass 11, count 0 2006.285.14:33:18.90#ibcon#about to read 5, iclass 11, count 0 2006.285.14:33:18.90#ibcon#read 5, iclass 11, count 0 2006.285.14:33:18.90#ibcon#about to read 6, iclass 11, count 0 2006.285.14:33:18.90#ibcon#read 6, iclass 11, count 0 2006.285.14:33:18.90#ibcon#end of sib2, iclass 11, count 0 2006.285.14:33:18.90#ibcon#*mode == 0, iclass 11, count 0 2006.285.14:33:18.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.14:33:18.90#ibcon#[27=USB\r\n] 2006.285.14:33:18.90#ibcon#*before write, iclass 11, count 0 2006.285.14:33:18.90#ibcon#enter sib2, iclass 11, count 0 2006.285.14:33:18.90#ibcon#flushed, iclass 11, count 0 2006.285.14:33:18.90#ibcon#about to write, iclass 11, count 0 2006.285.14:33:18.90#ibcon#wrote, iclass 11, count 0 2006.285.14:33:18.90#ibcon#about to read 3, iclass 11, count 0 2006.285.14:33:18.93#ibcon#read 3, iclass 11, count 0 2006.285.14:33:18.93#ibcon#about to read 4, iclass 11, count 0 2006.285.14:33:18.93#ibcon#read 4, iclass 11, count 0 2006.285.14:33:18.93#ibcon#about to read 5, iclass 11, count 0 2006.285.14:33:18.93#ibcon#read 5, iclass 11, count 0 2006.285.14:33:18.93#ibcon#about to read 6, iclass 11, count 0 2006.285.14:33:18.93#ibcon#read 6, iclass 11, count 0 2006.285.14:33:18.93#ibcon#end of sib2, iclass 11, count 0 2006.285.14:33:18.93#ibcon#*after write, iclass 11, count 0 2006.285.14:33:18.93#ibcon#*before return 0, iclass 11, count 0 2006.285.14:33:18.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:33:18.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:33:18.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.14:33:18.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.14:33:18.93$vck44/vblo=3,649.99 2006.285.14:33:18.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.14:33:18.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.14:33:18.93#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:18.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:33:18.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:33:18.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:33:18.93#ibcon#enter wrdev, iclass 13, count 0 2006.285.14:33:18.93#ibcon#first serial, iclass 13, count 0 2006.285.14:33:18.93#ibcon#enter sib2, iclass 13, count 0 2006.285.14:33:18.93#ibcon#flushed, iclass 13, count 0 2006.285.14:33:18.93#ibcon#about to write, iclass 13, count 0 2006.285.14:33:18.93#ibcon#wrote, iclass 13, count 0 2006.285.14:33:18.93#ibcon#about to read 3, iclass 13, count 0 2006.285.14:33:18.95#ibcon#read 3, iclass 13, count 0 2006.285.14:33:18.95#ibcon#about to read 4, iclass 13, count 0 2006.285.14:33:18.95#ibcon#read 4, iclass 13, count 0 2006.285.14:33:18.95#ibcon#about to read 5, iclass 13, count 0 2006.285.14:33:18.95#ibcon#read 5, iclass 13, count 0 2006.285.14:33:18.95#ibcon#about to read 6, iclass 13, count 0 2006.285.14:33:18.95#ibcon#read 6, iclass 13, count 0 2006.285.14:33:18.95#ibcon#end of sib2, iclass 13, count 0 2006.285.14:33:18.95#ibcon#*mode == 0, iclass 13, count 0 2006.285.14:33:18.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.14:33:18.95#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.14:33:18.95#ibcon#*before write, iclass 13, count 0 2006.285.14:33:18.95#ibcon#enter sib2, iclass 13, count 0 2006.285.14:33:18.95#ibcon#flushed, iclass 13, count 0 2006.285.14:33:18.95#ibcon#about to write, iclass 13, count 0 2006.285.14:33:18.95#ibcon#wrote, iclass 13, count 0 2006.285.14:33:18.95#ibcon#about to read 3, iclass 13, count 0 2006.285.14:33:18.99#ibcon#read 3, iclass 13, count 0 2006.285.14:33:18.99#ibcon#about to read 4, iclass 13, count 0 2006.285.14:33:18.99#ibcon#read 4, iclass 13, count 0 2006.285.14:33:18.99#ibcon#about to read 5, iclass 13, count 0 2006.285.14:33:18.99#ibcon#read 5, iclass 13, count 0 2006.285.14:33:18.99#ibcon#about to read 6, iclass 13, count 0 2006.285.14:33:18.99#ibcon#read 6, iclass 13, count 0 2006.285.14:33:18.99#ibcon#end of sib2, iclass 13, count 0 2006.285.14:33:18.99#ibcon#*after write, iclass 13, count 0 2006.285.14:33:18.99#ibcon#*before return 0, iclass 13, count 0 2006.285.14:33:18.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:33:18.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:33:18.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.14:33:18.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.14:33:18.99$vck44/vb=3,4 2006.285.14:33:18.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.14:33:18.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.14:33:18.99#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:18.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:33:19.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:33:19.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:33:19.05#ibcon#enter wrdev, iclass 15, count 2 2006.285.14:33:19.05#ibcon#first serial, iclass 15, count 2 2006.285.14:33:19.05#ibcon#enter sib2, iclass 15, count 2 2006.285.14:33:19.05#ibcon#flushed, iclass 15, count 2 2006.285.14:33:19.05#ibcon#about to write, iclass 15, count 2 2006.285.14:33:19.05#ibcon#wrote, iclass 15, count 2 2006.285.14:33:19.05#ibcon#about to read 3, iclass 15, count 2 2006.285.14:33:19.07#ibcon#read 3, iclass 15, count 2 2006.285.14:33:19.07#ibcon#about to read 4, iclass 15, count 2 2006.285.14:33:19.07#ibcon#read 4, iclass 15, count 2 2006.285.14:33:19.07#ibcon#about to read 5, iclass 15, count 2 2006.285.14:33:19.07#ibcon#read 5, iclass 15, count 2 2006.285.14:33:19.07#ibcon#about to read 6, iclass 15, count 2 2006.285.14:33:19.07#ibcon#read 6, iclass 15, count 2 2006.285.14:33:19.07#ibcon#end of sib2, iclass 15, count 2 2006.285.14:33:19.07#ibcon#*mode == 0, iclass 15, count 2 2006.285.14:33:19.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.14:33:19.07#ibcon#[27=AT03-04\r\n] 2006.285.14:33:19.07#ibcon#*before write, iclass 15, count 2 2006.285.14:33:19.07#ibcon#enter sib2, iclass 15, count 2 2006.285.14:33:19.07#ibcon#flushed, iclass 15, count 2 2006.285.14:33:19.07#ibcon#about to write, iclass 15, count 2 2006.285.14:33:19.07#ibcon#wrote, iclass 15, count 2 2006.285.14:33:19.07#ibcon#about to read 3, iclass 15, count 2 2006.285.14:33:19.10#ibcon#read 3, iclass 15, count 2 2006.285.14:33:19.10#ibcon#about to read 4, iclass 15, count 2 2006.285.14:33:19.10#ibcon#read 4, iclass 15, count 2 2006.285.14:33:19.10#ibcon#about to read 5, iclass 15, count 2 2006.285.14:33:19.10#ibcon#read 5, iclass 15, count 2 2006.285.14:33:19.10#ibcon#about to read 6, iclass 15, count 2 2006.285.14:33:19.10#ibcon#read 6, iclass 15, count 2 2006.285.14:33:19.10#ibcon#end of sib2, iclass 15, count 2 2006.285.14:33:19.10#ibcon#*after write, iclass 15, count 2 2006.285.14:33:19.10#ibcon#*before return 0, iclass 15, count 2 2006.285.14:33:19.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:33:19.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:33:19.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.14:33:19.10#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:19.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:33:19.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:33:19.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:33:19.22#ibcon#enter wrdev, iclass 15, count 0 2006.285.14:33:19.22#ibcon#first serial, iclass 15, count 0 2006.285.14:33:19.22#ibcon#enter sib2, iclass 15, count 0 2006.285.14:33:19.22#ibcon#flushed, iclass 15, count 0 2006.285.14:33:19.22#ibcon#about to write, iclass 15, count 0 2006.285.14:33:19.22#ibcon#wrote, iclass 15, count 0 2006.285.14:33:19.22#ibcon#about to read 3, iclass 15, count 0 2006.285.14:33:19.24#ibcon#read 3, iclass 15, count 0 2006.285.14:33:19.24#ibcon#about to read 4, iclass 15, count 0 2006.285.14:33:19.24#ibcon#read 4, iclass 15, count 0 2006.285.14:33:19.24#ibcon#about to read 5, iclass 15, count 0 2006.285.14:33:19.24#ibcon#read 5, iclass 15, count 0 2006.285.14:33:19.24#ibcon#about to read 6, iclass 15, count 0 2006.285.14:33:19.24#ibcon#read 6, iclass 15, count 0 2006.285.14:33:19.24#ibcon#end of sib2, iclass 15, count 0 2006.285.14:33:19.24#ibcon#*mode == 0, iclass 15, count 0 2006.285.14:33:19.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.14:33:19.24#ibcon#[27=USB\r\n] 2006.285.14:33:19.24#ibcon#*before write, iclass 15, count 0 2006.285.14:33:19.24#ibcon#enter sib2, iclass 15, count 0 2006.285.14:33:19.24#ibcon#flushed, iclass 15, count 0 2006.285.14:33:19.24#ibcon#about to write, iclass 15, count 0 2006.285.14:33:19.24#ibcon#wrote, iclass 15, count 0 2006.285.14:33:19.24#ibcon#about to read 3, iclass 15, count 0 2006.285.14:33:19.27#ibcon#read 3, iclass 15, count 0 2006.285.14:33:19.27#ibcon#about to read 4, iclass 15, count 0 2006.285.14:33:19.27#ibcon#read 4, iclass 15, count 0 2006.285.14:33:19.27#ibcon#about to read 5, iclass 15, count 0 2006.285.14:33:19.27#ibcon#read 5, iclass 15, count 0 2006.285.14:33:19.27#ibcon#about to read 6, iclass 15, count 0 2006.285.14:33:19.27#ibcon#read 6, iclass 15, count 0 2006.285.14:33:19.27#ibcon#end of sib2, iclass 15, count 0 2006.285.14:33:19.27#ibcon#*after write, iclass 15, count 0 2006.285.14:33:19.27#ibcon#*before return 0, iclass 15, count 0 2006.285.14:33:19.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:33:19.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:33:19.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.14:33:19.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.14:33:19.27$vck44/vblo=4,679.99 2006.285.14:33:19.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.14:33:19.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.14:33:19.27#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:19.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:33:19.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:33:19.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:33:19.27#ibcon#enter wrdev, iclass 17, count 0 2006.285.14:33:19.27#ibcon#first serial, iclass 17, count 0 2006.285.14:33:19.27#ibcon#enter sib2, iclass 17, count 0 2006.285.14:33:19.27#ibcon#flushed, iclass 17, count 0 2006.285.14:33:19.27#ibcon#about to write, iclass 17, count 0 2006.285.14:33:19.27#ibcon#wrote, iclass 17, count 0 2006.285.14:33:19.27#ibcon#about to read 3, iclass 17, count 0 2006.285.14:33:19.29#ibcon#read 3, iclass 17, count 0 2006.285.14:33:19.29#ibcon#about to read 4, iclass 17, count 0 2006.285.14:33:19.29#ibcon#read 4, iclass 17, count 0 2006.285.14:33:19.29#ibcon#about to read 5, iclass 17, count 0 2006.285.14:33:19.29#ibcon#read 5, iclass 17, count 0 2006.285.14:33:19.29#ibcon#about to read 6, iclass 17, count 0 2006.285.14:33:19.29#ibcon#read 6, iclass 17, count 0 2006.285.14:33:19.29#ibcon#end of sib2, iclass 17, count 0 2006.285.14:33:19.29#ibcon#*mode == 0, iclass 17, count 0 2006.285.14:33:19.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.14:33:19.29#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.14:33:19.29#ibcon#*before write, iclass 17, count 0 2006.285.14:33:19.29#ibcon#enter sib2, iclass 17, count 0 2006.285.14:33:19.29#ibcon#flushed, iclass 17, count 0 2006.285.14:33:19.29#ibcon#about to write, iclass 17, count 0 2006.285.14:33:19.29#ibcon#wrote, iclass 17, count 0 2006.285.14:33:19.29#ibcon#about to read 3, iclass 17, count 0 2006.285.14:33:19.33#ibcon#read 3, iclass 17, count 0 2006.285.14:33:19.33#ibcon#about to read 4, iclass 17, count 0 2006.285.14:33:19.33#ibcon#read 4, iclass 17, count 0 2006.285.14:33:19.33#ibcon#about to read 5, iclass 17, count 0 2006.285.14:33:19.33#ibcon#read 5, iclass 17, count 0 2006.285.14:33:19.33#ibcon#about to read 6, iclass 17, count 0 2006.285.14:33:19.33#ibcon#read 6, iclass 17, count 0 2006.285.14:33:19.33#ibcon#end of sib2, iclass 17, count 0 2006.285.14:33:19.33#ibcon#*after write, iclass 17, count 0 2006.285.14:33:19.33#ibcon#*before return 0, iclass 17, count 0 2006.285.14:33:19.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:33:19.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:33:19.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.14:33:19.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.14:33:19.33$vck44/vb=4,5 2006.285.14:33:19.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.14:33:19.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.14:33:19.33#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:19.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:33:19.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:33:19.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:33:19.39#ibcon#enter wrdev, iclass 19, count 2 2006.285.14:33:19.39#ibcon#first serial, iclass 19, count 2 2006.285.14:33:19.39#ibcon#enter sib2, iclass 19, count 2 2006.285.14:33:19.39#ibcon#flushed, iclass 19, count 2 2006.285.14:33:19.39#ibcon#about to write, iclass 19, count 2 2006.285.14:33:19.39#ibcon#wrote, iclass 19, count 2 2006.285.14:33:19.39#ibcon#about to read 3, iclass 19, count 2 2006.285.14:33:19.41#ibcon#read 3, iclass 19, count 2 2006.285.14:33:19.41#ibcon#about to read 4, iclass 19, count 2 2006.285.14:33:19.41#ibcon#read 4, iclass 19, count 2 2006.285.14:33:19.41#ibcon#about to read 5, iclass 19, count 2 2006.285.14:33:19.41#ibcon#read 5, iclass 19, count 2 2006.285.14:33:19.41#ibcon#about to read 6, iclass 19, count 2 2006.285.14:33:19.41#ibcon#read 6, iclass 19, count 2 2006.285.14:33:19.41#ibcon#end of sib2, iclass 19, count 2 2006.285.14:33:19.41#ibcon#*mode == 0, iclass 19, count 2 2006.285.14:33:19.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.14:33:19.41#ibcon#[27=AT04-05\r\n] 2006.285.14:33:19.41#ibcon#*before write, iclass 19, count 2 2006.285.14:33:19.41#ibcon#enter sib2, iclass 19, count 2 2006.285.14:33:19.41#ibcon#flushed, iclass 19, count 2 2006.285.14:33:19.41#ibcon#about to write, iclass 19, count 2 2006.285.14:33:19.41#ibcon#wrote, iclass 19, count 2 2006.285.14:33:19.41#ibcon#about to read 3, iclass 19, count 2 2006.285.14:33:19.44#ibcon#read 3, iclass 19, count 2 2006.285.14:33:19.44#ibcon#about to read 4, iclass 19, count 2 2006.285.14:33:19.44#ibcon#read 4, iclass 19, count 2 2006.285.14:33:19.44#ibcon#about to read 5, iclass 19, count 2 2006.285.14:33:19.44#ibcon#read 5, iclass 19, count 2 2006.285.14:33:19.44#ibcon#about to read 6, iclass 19, count 2 2006.285.14:33:19.44#ibcon#read 6, iclass 19, count 2 2006.285.14:33:19.44#ibcon#end of sib2, iclass 19, count 2 2006.285.14:33:19.44#ibcon#*after write, iclass 19, count 2 2006.285.14:33:19.44#ibcon#*before return 0, iclass 19, count 2 2006.285.14:33:19.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:33:19.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:33:19.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.14:33:19.44#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:19.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:33:19.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:33:19.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:33:19.56#ibcon#enter wrdev, iclass 19, count 0 2006.285.14:33:19.56#ibcon#first serial, iclass 19, count 0 2006.285.14:33:19.56#ibcon#enter sib2, iclass 19, count 0 2006.285.14:33:19.56#ibcon#flushed, iclass 19, count 0 2006.285.14:33:19.56#ibcon#about to write, iclass 19, count 0 2006.285.14:33:19.56#ibcon#wrote, iclass 19, count 0 2006.285.14:33:19.56#ibcon#about to read 3, iclass 19, count 0 2006.285.14:33:19.58#ibcon#read 3, iclass 19, count 0 2006.285.14:33:19.58#ibcon#about to read 4, iclass 19, count 0 2006.285.14:33:19.58#ibcon#read 4, iclass 19, count 0 2006.285.14:33:19.58#ibcon#about to read 5, iclass 19, count 0 2006.285.14:33:19.58#ibcon#read 5, iclass 19, count 0 2006.285.14:33:19.58#ibcon#about to read 6, iclass 19, count 0 2006.285.14:33:19.58#ibcon#read 6, iclass 19, count 0 2006.285.14:33:19.58#ibcon#end of sib2, iclass 19, count 0 2006.285.14:33:19.58#ibcon#*mode == 0, iclass 19, count 0 2006.285.14:33:19.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.14:33:19.58#ibcon#[27=USB\r\n] 2006.285.14:33:19.58#ibcon#*before write, iclass 19, count 0 2006.285.14:33:19.58#ibcon#enter sib2, iclass 19, count 0 2006.285.14:33:19.58#ibcon#flushed, iclass 19, count 0 2006.285.14:33:19.58#ibcon#about to write, iclass 19, count 0 2006.285.14:33:19.58#ibcon#wrote, iclass 19, count 0 2006.285.14:33:19.58#ibcon#about to read 3, iclass 19, count 0 2006.285.14:33:19.61#ibcon#read 3, iclass 19, count 0 2006.285.14:33:19.61#ibcon#about to read 4, iclass 19, count 0 2006.285.14:33:19.61#ibcon#read 4, iclass 19, count 0 2006.285.14:33:19.61#ibcon#about to read 5, iclass 19, count 0 2006.285.14:33:19.61#ibcon#read 5, iclass 19, count 0 2006.285.14:33:19.61#ibcon#about to read 6, iclass 19, count 0 2006.285.14:33:19.61#ibcon#read 6, iclass 19, count 0 2006.285.14:33:19.61#ibcon#end of sib2, iclass 19, count 0 2006.285.14:33:19.61#ibcon#*after write, iclass 19, count 0 2006.285.14:33:19.61#ibcon#*before return 0, iclass 19, count 0 2006.285.14:33:19.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:33:19.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:33:19.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.14:33:19.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.14:33:19.61$vck44/vblo=5,709.99 2006.285.14:33:19.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.14:33:19.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.14:33:19.61#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:19.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:33:19.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:33:19.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:33:19.61#ibcon#enter wrdev, iclass 21, count 0 2006.285.14:33:19.61#ibcon#first serial, iclass 21, count 0 2006.285.14:33:19.61#ibcon#enter sib2, iclass 21, count 0 2006.285.14:33:19.61#ibcon#flushed, iclass 21, count 0 2006.285.14:33:19.61#ibcon#about to write, iclass 21, count 0 2006.285.14:33:19.61#ibcon#wrote, iclass 21, count 0 2006.285.14:33:19.61#ibcon#about to read 3, iclass 21, count 0 2006.285.14:33:19.63#ibcon#read 3, iclass 21, count 0 2006.285.14:33:19.63#ibcon#about to read 4, iclass 21, count 0 2006.285.14:33:19.63#ibcon#read 4, iclass 21, count 0 2006.285.14:33:19.63#ibcon#about to read 5, iclass 21, count 0 2006.285.14:33:19.63#ibcon#read 5, iclass 21, count 0 2006.285.14:33:19.63#ibcon#about to read 6, iclass 21, count 0 2006.285.14:33:19.63#ibcon#read 6, iclass 21, count 0 2006.285.14:33:19.63#ibcon#end of sib2, iclass 21, count 0 2006.285.14:33:19.63#ibcon#*mode == 0, iclass 21, count 0 2006.285.14:33:19.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.14:33:19.63#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.14:33:19.63#ibcon#*before write, iclass 21, count 0 2006.285.14:33:19.63#ibcon#enter sib2, iclass 21, count 0 2006.285.14:33:19.63#ibcon#flushed, iclass 21, count 0 2006.285.14:33:19.63#ibcon#about to write, iclass 21, count 0 2006.285.14:33:19.63#ibcon#wrote, iclass 21, count 0 2006.285.14:33:19.63#ibcon#about to read 3, iclass 21, count 0 2006.285.14:33:19.67#ibcon#read 3, iclass 21, count 0 2006.285.14:33:19.67#ibcon#about to read 4, iclass 21, count 0 2006.285.14:33:19.67#ibcon#read 4, iclass 21, count 0 2006.285.14:33:19.67#ibcon#about to read 5, iclass 21, count 0 2006.285.14:33:19.67#ibcon#read 5, iclass 21, count 0 2006.285.14:33:19.67#ibcon#about to read 6, iclass 21, count 0 2006.285.14:33:19.67#ibcon#read 6, iclass 21, count 0 2006.285.14:33:19.67#ibcon#end of sib2, iclass 21, count 0 2006.285.14:33:19.67#ibcon#*after write, iclass 21, count 0 2006.285.14:33:19.67#ibcon#*before return 0, iclass 21, count 0 2006.285.14:33:19.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:33:19.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:33:19.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.14:33:19.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.14:33:19.67$vck44/vb=5,4 2006.285.14:33:19.67#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.14:33:19.67#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.14:33:19.67#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:19.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:33:19.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:33:19.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:33:19.73#ibcon#enter wrdev, iclass 23, count 2 2006.285.14:33:19.73#ibcon#first serial, iclass 23, count 2 2006.285.14:33:19.73#ibcon#enter sib2, iclass 23, count 2 2006.285.14:33:19.73#ibcon#flushed, iclass 23, count 2 2006.285.14:33:19.73#ibcon#about to write, iclass 23, count 2 2006.285.14:33:19.73#ibcon#wrote, iclass 23, count 2 2006.285.14:33:19.73#ibcon#about to read 3, iclass 23, count 2 2006.285.14:33:19.75#ibcon#read 3, iclass 23, count 2 2006.285.14:33:19.96#ibcon#about to read 4, iclass 23, count 2 2006.285.14:33:19.96#ibcon#read 4, iclass 23, count 2 2006.285.14:33:19.96#ibcon#about to read 5, iclass 23, count 2 2006.285.14:33:19.96#ibcon#read 5, iclass 23, count 2 2006.285.14:33:19.96#ibcon#about to read 6, iclass 23, count 2 2006.285.14:33:19.96#ibcon#read 6, iclass 23, count 2 2006.285.14:33:19.96#ibcon#end of sib2, iclass 23, count 2 2006.285.14:33:19.96#ibcon#*mode == 0, iclass 23, count 2 2006.285.14:33:19.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.14:33:19.96#ibcon#[27=AT05-04\r\n] 2006.285.14:33:19.96#ibcon#*before write, iclass 23, count 2 2006.285.14:33:19.96#ibcon#enter sib2, iclass 23, count 2 2006.285.14:33:19.96#ibcon#flushed, iclass 23, count 2 2006.285.14:33:19.96#ibcon#about to write, iclass 23, count 2 2006.285.14:33:19.96#ibcon#wrote, iclass 23, count 2 2006.285.14:33:19.96#ibcon#about to read 3, iclass 23, count 2 2006.285.14:33:20.00#ibcon#read 3, iclass 23, count 2 2006.285.14:33:20.00#ibcon#about to read 4, iclass 23, count 2 2006.285.14:33:20.00#ibcon#read 4, iclass 23, count 2 2006.285.14:33:20.00#ibcon#about to read 5, iclass 23, count 2 2006.285.14:33:20.00#ibcon#read 5, iclass 23, count 2 2006.285.14:33:20.00#ibcon#about to read 6, iclass 23, count 2 2006.285.14:33:20.00#ibcon#read 6, iclass 23, count 2 2006.285.14:33:20.00#ibcon#end of sib2, iclass 23, count 2 2006.285.14:33:20.00#ibcon#*after write, iclass 23, count 2 2006.285.14:33:20.00#ibcon#*before return 0, iclass 23, count 2 2006.285.14:33:20.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:33:20.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:33:20.00#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.14:33:20.00#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:20.00#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:33:20.12#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:33:20.12#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:33:20.12#ibcon#enter wrdev, iclass 23, count 0 2006.285.14:33:20.12#ibcon#first serial, iclass 23, count 0 2006.285.14:33:20.12#ibcon#enter sib2, iclass 23, count 0 2006.285.14:33:20.12#ibcon#flushed, iclass 23, count 0 2006.285.14:33:20.12#ibcon#about to write, iclass 23, count 0 2006.285.14:33:20.12#ibcon#wrote, iclass 23, count 0 2006.285.14:33:20.12#ibcon#about to read 3, iclass 23, count 0 2006.285.14:33:20.14#ibcon#read 3, iclass 23, count 0 2006.285.14:33:20.14#ibcon#about to read 4, iclass 23, count 0 2006.285.14:33:20.14#ibcon#read 4, iclass 23, count 0 2006.285.14:33:20.14#ibcon#about to read 5, iclass 23, count 0 2006.285.14:33:20.14#ibcon#read 5, iclass 23, count 0 2006.285.14:33:20.14#ibcon#about to read 6, iclass 23, count 0 2006.285.14:33:20.14#ibcon#read 6, iclass 23, count 0 2006.285.14:33:20.14#ibcon#end of sib2, iclass 23, count 0 2006.285.14:33:20.14#ibcon#*mode == 0, iclass 23, count 0 2006.285.14:33:20.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.14:33:20.14#ibcon#[27=USB\r\n] 2006.285.14:33:20.14#ibcon#*before write, iclass 23, count 0 2006.285.14:33:20.14#ibcon#enter sib2, iclass 23, count 0 2006.285.14:33:20.14#ibcon#flushed, iclass 23, count 0 2006.285.14:33:20.14#ibcon#about to write, iclass 23, count 0 2006.285.14:33:20.14#ibcon#wrote, iclass 23, count 0 2006.285.14:33:20.14#ibcon#about to read 3, iclass 23, count 0 2006.285.14:33:20.17#ibcon#read 3, iclass 23, count 0 2006.285.14:33:20.17#ibcon#about to read 4, iclass 23, count 0 2006.285.14:33:20.17#ibcon#read 4, iclass 23, count 0 2006.285.14:33:20.17#ibcon#about to read 5, iclass 23, count 0 2006.285.14:33:20.17#ibcon#read 5, iclass 23, count 0 2006.285.14:33:20.17#ibcon#about to read 6, iclass 23, count 0 2006.285.14:33:20.17#ibcon#read 6, iclass 23, count 0 2006.285.14:33:20.17#ibcon#end of sib2, iclass 23, count 0 2006.285.14:33:20.17#ibcon#*after write, iclass 23, count 0 2006.285.14:33:20.17#ibcon#*before return 0, iclass 23, count 0 2006.285.14:33:20.17#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:33:20.17#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:33:20.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.14:33:20.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.14:33:20.17$vck44/vblo=6,719.99 2006.285.14:33:20.17#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.14:33:20.17#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.14:33:20.17#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:20.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:33:20.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:33:20.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:33:20.17#ibcon#enter wrdev, iclass 25, count 0 2006.285.14:33:20.17#ibcon#first serial, iclass 25, count 0 2006.285.14:33:20.17#ibcon#enter sib2, iclass 25, count 0 2006.285.14:33:20.17#ibcon#flushed, iclass 25, count 0 2006.285.14:33:20.17#ibcon#about to write, iclass 25, count 0 2006.285.14:33:20.17#ibcon#wrote, iclass 25, count 0 2006.285.14:33:20.17#ibcon#about to read 3, iclass 25, count 0 2006.285.14:33:20.19#ibcon#read 3, iclass 25, count 0 2006.285.14:33:20.19#ibcon#about to read 4, iclass 25, count 0 2006.285.14:33:20.19#ibcon#read 4, iclass 25, count 0 2006.285.14:33:20.19#ibcon#about to read 5, iclass 25, count 0 2006.285.14:33:20.19#ibcon#read 5, iclass 25, count 0 2006.285.14:33:20.19#ibcon#about to read 6, iclass 25, count 0 2006.285.14:33:20.19#ibcon#read 6, iclass 25, count 0 2006.285.14:33:20.19#ibcon#end of sib2, iclass 25, count 0 2006.285.14:33:20.19#ibcon#*mode == 0, iclass 25, count 0 2006.285.14:33:20.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.14:33:20.19#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.14:33:20.19#ibcon#*before write, iclass 25, count 0 2006.285.14:33:20.19#ibcon#enter sib2, iclass 25, count 0 2006.285.14:33:20.19#ibcon#flushed, iclass 25, count 0 2006.285.14:33:20.19#ibcon#about to write, iclass 25, count 0 2006.285.14:33:20.19#ibcon#wrote, iclass 25, count 0 2006.285.14:33:20.19#ibcon#about to read 3, iclass 25, count 0 2006.285.14:33:20.23#ibcon#read 3, iclass 25, count 0 2006.285.14:33:20.23#ibcon#about to read 4, iclass 25, count 0 2006.285.14:33:20.23#ibcon#read 4, iclass 25, count 0 2006.285.14:33:20.23#ibcon#about to read 5, iclass 25, count 0 2006.285.14:33:20.23#ibcon#read 5, iclass 25, count 0 2006.285.14:33:20.23#ibcon#about to read 6, iclass 25, count 0 2006.285.14:33:20.23#ibcon#read 6, iclass 25, count 0 2006.285.14:33:20.23#ibcon#end of sib2, iclass 25, count 0 2006.285.14:33:20.23#ibcon#*after write, iclass 25, count 0 2006.285.14:33:20.23#ibcon#*before return 0, iclass 25, count 0 2006.285.14:33:20.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:33:20.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:33:20.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.14:33:20.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.14:33:20.23$vck44/vb=6,3 2006.285.14:33:20.23#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.14:33:20.23#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.14:33:20.23#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:20.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:33:20.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:33:20.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:33:20.29#ibcon#enter wrdev, iclass 27, count 2 2006.285.14:33:20.29#ibcon#first serial, iclass 27, count 2 2006.285.14:33:20.29#ibcon#enter sib2, iclass 27, count 2 2006.285.14:33:20.29#ibcon#flushed, iclass 27, count 2 2006.285.14:33:20.29#ibcon#about to write, iclass 27, count 2 2006.285.14:33:20.29#ibcon#wrote, iclass 27, count 2 2006.285.14:33:20.29#ibcon#about to read 3, iclass 27, count 2 2006.285.14:33:20.31#ibcon#read 3, iclass 27, count 2 2006.285.14:33:20.31#ibcon#about to read 4, iclass 27, count 2 2006.285.14:33:20.31#ibcon#read 4, iclass 27, count 2 2006.285.14:33:20.31#ibcon#about to read 5, iclass 27, count 2 2006.285.14:33:20.31#ibcon#read 5, iclass 27, count 2 2006.285.14:33:20.31#ibcon#about to read 6, iclass 27, count 2 2006.285.14:33:20.31#ibcon#read 6, iclass 27, count 2 2006.285.14:33:20.31#ibcon#end of sib2, iclass 27, count 2 2006.285.14:33:20.31#ibcon#*mode == 0, iclass 27, count 2 2006.285.14:33:20.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.14:33:20.31#ibcon#[27=AT06-03\r\n] 2006.285.14:33:20.31#ibcon#*before write, iclass 27, count 2 2006.285.14:33:20.31#ibcon#enter sib2, iclass 27, count 2 2006.285.14:33:20.31#ibcon#flushed, iclass 27, count 2 2006.285.14:33:20.31#ibcon#about to write, iclass 27, count 2 2006.285.14:33:20.31#ibcon#wrote, iclass 27, count 2 2006.285.14:33:20.31#ibcon#about to read 3, iclass 27, count 2 2006.285.14:33:20.34#ibcon#read 3, iclass 27, count 2 2006.285.14:33:20.34#ibcon#about to read 4, iclass 27, count 2 2006.285.14:33:20.34#ibcon#read 4, iclass 27, count 2 2006.285.14:33:20.34#ibcon#about to read 5, iclass 27, count 2 2006.285.14:33:20.34#ibcon#read 5, iclass 27, count 2 2006.285.14:33:20.34#ibcon#about to read 6, iclass 27, count 2 2006.285.14:33:20.34#ibcon#read 6, iclass 27, count 2 2006.285.14:33:20.34#ibcon#end of sib2, iclass 27, count 2 2006.285.14:33:20.34#ibcon#*after write, iclass 27, count 2 2006.285.14:33:20.34#ibcon#*before return 0, iclass 27, count 2 2006.285.14:33:20.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:33:20.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:33:20.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.14:33:20.34#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:20.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:33:20.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:33:20.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:33:20.46#ibcon#enter wrdev, iclass 27, count 0 2006.285.14:33:20.46#ibcon#first serial, iclass 27, count 0 2006.285.14:33:20.46#ibcon#enter sib2, iclass 27, count 0 2006.285.14:33:20.46#ibcon#flushed, iclass 27, count 0 2006.285.14:33:20.46#ibcon#about to write, iclass 27, count 0 2006.285.14:33:20.46#ibcon#wrote, iclass 27, count 0 2006.285.14:33:20.46#ibcon#about to read 3, iclass 27, count 0 2006.285.14:33:20.48#ibcon#read 3, iclass 27, count 0 2006.285.14:33:20.48#ibcon#about to read 4, iclass 27, count 0 2006.285.14:33:20.48#ibcon#read 4, iclass 27, count 0 2006.285.14:33:20.48#ibcon#about to read 5, iclass 27, count 0 2006.285.14:33:20.48#ibcon#read 5, iclass 27, count 0 2006.285.14:33:20.48#ibcon#about to read 6, iclass 27, count 0 2006.285.14:33:20.48#ibcon#read 6, iclass 27, count 0 2006.285.14:33:20.48#ibcon#end of sib2, iclass 27, count 0 2006.285.14:33:20.48#ibcon#*mode == 0, iclass 27, count 0 2006.285.14:33:20.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.14:33:20.48#ibcon#[27=USB\r\n] 2006.285.14:33:20.48#ibcon#*before write, iclass 27, count 0 2006.285.14:33:20.48#ibcon#enter sib2, iclass 27, count 0 2006.285.14:33:20.48#ibcon#flushed, iclass 27, count 0 2006.285.14:33:20.48#ibcon#about to write, iclass 27, count 0 2006.285.14:33:20.48#ibcon#wrote, iclass 27, count 0 2006.285.14:33:20.48#ibcon#about to read 3, iclass 27, count 0 2006.285.14:33:20.51#ibcon#read 3, iclass 27, count 0 2006.285.14:33:20.51#ibcon#about to read 4, iclass 27, count 0 2006.285.14:33:20.51#ibcon#read 4, iclass 27, count 0 2006.285.14:33:20.51#ibcon#about to read 5, iclass 27, count 0 2006.285.14:33:20.51#ibcon#read 5, iclass 27, count 0 2006.285.14:33:20.51#ibcon#about to read 6, iclass 27, count 0 2006.285.14:33:20.51#ibcon#read 6, iclass 27, count 0 2006.285.14:33:20.51#ibcon#end of sib2, iclass 27, count 0 2006.285.14:33:20.51#ibcon#*after write, iclass 27, count 0 2006.285.14:33:20.51#ibcon#*before return 0, iclass 27, count 0 2006.285.14:33:20.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:33:20.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:33:20.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.14:33:20.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.14:33:20.51$vck44/vblo=7,734.99 2006.285.14:33:20.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.14:33:20.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.14:33:20.51#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:20.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:33:20.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:33:20.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:33:20.51#ibcon#enter wrdev, iclass 29, count 0 2006.285.14:33:20.51#ibcon#first serial, iclass 29, count 0 2006.285.14:33:20.51#ibcon#enter sib2, iclass 29, count 0 2006.285.14:33:20.51#ibcon#flushed, iclass 29, count 0 2006.285.14:33:20.51#ibcon#about to write, iclass 29, count 0 2006.285.14:33:20.51#ibcon#wrote, iclass 29, count 0 2006.285.14:33:20.51#ibcon#about to read 3, iclass 29, count 0 2006.285.14:33:20.53#ibcon#read 3, iclass 29, count 0 2006.285.14:33:20.53#ibcon#about to read 4, iclass 29, count 0 2006.285.14:33:20.53#ibcon#read 4, iclass 29, count 0 2006.285.14:33:20.53#ibcon#about to read 5, iclass 29, count 0 2006.285.14:33:20.53#ibcon#read 5, iclass 29, count 0 2006.285.14:33:20.53#ibcon#about to read 6, iclass 29, count 0 2006.285.14:33:20.53#ibcon#read 6, iclass 29, count 0 2006.285.14:33:20.53#ibcon#end of sib2, iclass 29, count 0 2006.285.14:33:20.53#ibcon#*mode == 0, iclass 29, count 0 2006.285.14:33:20.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.14:33:20.53#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.14:33:20.53#ibcon#*before write, iclass 29, count 0 2006.285.14:33:20.53#ibcon#enter sib2, iclass 29, count 0 2006.285.14:33:20.53#ibcon#flushed, iclass 29, count 0 2006.285.14:33:20.53#ibcon#about to write, iclass 29, count 0 2006.285.14:33:20.53#ibcon#wrote, iclass 29, count 0 2006.285.14:33:20.53#ibcon#about to read 3, iclass 29, count 0 2006.285.14:33:20.57#ibcon#read 3, iclass 29, count 0 2006.285.14:33:20.57#ibcon#about to read 4, iclass 29, count 0 2006.285.14:33:20.57#ibcon#read 4, iclass 29, count 0 2006.285.14:33:20.57#ibcon#about to read 5, iclass 29, count 0 2006.285.14:33:20.57#ibcon#read 5, iclass 29, count 0 2006.285.14:33:20.57#ibcon#about to read 6, iclass 29, count 0 2006.285.14:33:20.57#ibcon#read 6, iclass 29, count 0 2006.285.14:33:20.57#ibcon#end of sib2, iclass 29, count 0 2006.285.14:33:20.57#ibcon#*after write, iclass 29, count 0 2006.285.14:33:20.57#ibcon#*before return 0, iclass 29, count 0 2006.285.14:33:20.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:33:20.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:33:20.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.14:33:20.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.14:33:20.57$vck44/vb=7,4 2006.285.14:33:20.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.14:33:20.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.14:33:20.57#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:20.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:33:20.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:33:20.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:33:20.63#ibcon#enter wrdev, iclass 31, count 2 2006.285.14:33:20.63#ibcon#first serial, iclass 31, count 2 2006.285.14:33:20.63#ibcon#enter sib2, iclass 31, count 2 2006.285.14:33:20.63#ibcon#flushed, iclass 31, count 2 2006.285.14:33:20.63#ibcon#about to write, iclass 31, count 2 2006.285.14:33:20.63#ibcon#wrote, iclass 31, count 2 2006.285.14:33:20.63#ibcon#about to read 3, iclass 31, count 2 2006.285.14:33:20.65#ibcon#read 3, iclass 31, count 2 2006.285.14:33:20.65#ibcon#about to read 4, iclass 31, count 2 2006.285.14:33:20.65#ibcon#read 4, iclass 31, count 2 2006.285.14:33:20.65#ibcon#about to read 5, iclass 31, count 2 2006.285.14:33:20.65#ibcon#read 5, iclass 31, count 2 2006.285.14:33:20.65#ibcon#about to read 6, iclass 31, count 2 2006.285.14:33:20.65#ibcon#read 6, iclass 31, count 2 2006.285.14:33:20.65#ibcon#end of sib2, iclass 31, count 2 2006.285.14:33:20.65#ibcon#*mode == 0, iclass 31, count 2 2006.285.14:33:20.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.14:33:20.65#ibcon#[27=AT07-04\r\n] 2006.285.14:33:20.65#ibcon#*before write, iclass 31, count 2 2006.285.14:33:20.65#ibcon#enter sib2, iclass 31, count 2 2006.285.14:33:20.65#ibcon#flushed, iclass 31, count 2 2006.285.14:33:20.65#ibcon#about to write, iclass 31, count 2 2006.285.14:33:20.65#ibcon#wrote, iclass 31, count 2 2006.285.14:33:20.65#ibcon#about to read 3, iclass 31, count 2 2006.285.14:33:20.68#ibcon#read 3, iclass 31, count 2 2006.285.14:33:20.68#ibcon#about to read 4, iclass 31, count 2 2006.285.14:33:20.68#ibcon#read 4, iclass 31, count 2 2006.285.14:33:20.68#ibcon#about to read 5, iclass 31, count 2 2006.285.14:33:20.68#ibcon#read 5, iclass 31, count 2 2006.285.14:33:20.68#ibcon#about to read 6, iclass 31, count 2 2006.285.14:33:20.68#ibcon#read 6, iclass 31, count 2 2006.285.14:33:20.68#ibcon#end of sib2, iclass 31, count 2 2006.285.14:33:20.68#ibcon#*after write, iclass 31, count 2 2006.285.14:33:20.68#ibcon#*before return 0, iclass 31, count 2 2006.285.14:33:20.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:33:20.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:33:20.68#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.14:33:20.68#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:20.68#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:33:20.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:33:20.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:33:20.80#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:33:20.80#ibcon#first serial, iclass 31, count 0 2006.285.14:33:20.80#ibcon#enter sib2, iclass 31, count 0 2006.285.14:33:20.80#ibcon#flushed, iclass 31, count 0 2006.285.14:33:20.80#ibcon#about to write, iclass 31, count 0 2006.285.14:33:20.80#ibcon#wrote, iclass 31, count 0 2006.285.14:33:20.80#ibcon#about to read 3, iclass 31, count 0 2006.285.14:33:20.82#ibcon#read 3, iclass 31, count 0 2006.285.14:33:20.82#ibcon#about to read 4, iclass 31, count 0 2006.285.14:33:20.82#ibcon#read 4, iclass 31, count 0 2006.285.14:33:20.82#ibcon#about to read 5, iclass 31, count 0 2006.285.14:33:20.82#ibcon#read 5, iclass 31, count 0 2006.285.14:33:20.82#ibcon#about to read 6, iclass 31, count 0 2006.285.14:33:20.82#ibcon#read 6, iclass 31, count 0 2006.285.14:33:20.85#ibcon#end of sib2, iclass 31, count 0 2006.285.14:33:20.85#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:33:20.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:33:20.85#ibcon#[27=USB\r\n] 2006.285.14:33:20.85#ibcon#*before write, iclass 31, count 0 2006.285.14:33:20.85#ibcon#enter sib2, iclass 31, count 0 2006.285.14:33:20.85#ibcon#flushed, iclass 31, count 0 2006.285.14:33:20.85#ibcon#about to write, iclass 31, count 0 2006.285.14:33:20.85#ibcon#wrote, iclass 31, count 0 2006.285.14:33:20.85#ibcon#about to read 3, iclass 31, count 0 2006.285.14:33:20.88#ibcon#read 3, iclass 31, count 0 2006.285.14:33:20.88#ibcon#about to read 4, iclass 31, count 0 2006.285.14:33:20.88#ibcon#read 4, iclass 31, count 0 2006.285.14:33:20.88#ibcon#about to read 5, iclass 31, count 0 2006.285.14:33:20.88#ibcon#read 5, iclass 31, count 0 2006.285.14:33:20.88#ibcon#about to read 6, iclass 31, count 0 2006.285.14:33:20.88#ibcon#read 6, iclass 31, count 0 2006.285.14:33:20.88#ibcon#end of sib2, iclass 31, count 0 2006.285.14:33:20.88#ibcon#*after write, iclass 31, count 0 2006.285.14:33:20.88#ibcon#*before return 0, iclass 31, count 0 2006.285.14:33:20.88#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:33:20.88#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:33:20.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:33:20.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:33:20.88$vck44/vblo=8,744.99 2006.285.14:33:20.88#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.14:33:20.88#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.14:33:20.88#ibcon#ireg 17 cls_cnt 0 2006.285.14:33:20.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:33:20.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:33:20.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:33:20.88#ibcon#enter wrdev, iclass 33, count 0 2006.285.14:33:20.88#ibcon#first serial, iclass 33, count 0 2006.285.14:33:20.88#ibcon#enter sib2, iclass 33, count 0 2006.285.14:33:20.88#ibcon#flushed, iclass 33, count 0 2006.285.14:33:20.88#ibcon#about to write, iclass 33, count 0 2006.285.14:33:20.88#ibcon#wrote, iclass 33, count 0 2006.285.14:33:20.88#ibcon#about to read 3, iclass 33, count 0 2006.285.14:33:20.90#ibcon#read 3, iclass 33, count 0 2006.285.14:33:20.90#ibcon#about to read 4, iclass 33, count 0 2006.285.14:33:20.90#ibcon#read 4, iclass 33, count 0 2006.285.14:33:20.90#ibcon#about to read 5, iclass 33, count 0 2006.285.14:33:20.90#ibcon#read 5, iclass 33, count 0 2006.285.14:33:20.90#ibcon#about to read 6, iclass 33, count 0 2006.285.14:33:20.90#ibcon#read 6, iclass 33, count 0 2006.285.14:33:20.90#ibcon#end of sib2, iclass 33, count 0 2006.285.14:33:20.90#ibcon#*mode == 0, iclass 33, count 0 2006.285.14:33:20.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.14:33:20.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.14:33:20.90#ibcon#*before write, iclass 33, count 0 2006.285.14:33:20.90#ibcon#enter sib2, iclass 33, count 0 2006.285.14:33:20.90#ibcon#flushed, iclass 33, count 0 2006.285.14:33:20.90#ibcon#about to write, iclass 33, count 0 2006.285.14:33:20.90#ibcon#wrote, iclass 33, count 0 2006.285.14:33:20.90#ibcon#about to read 3, iclass 33, count 0 2006.285.14:33:20.94#ibcon#read 3, iclass 33, count 0 2006.285.14:33:20.94#ibcon#about to read 4, iclass 33, count 0 2006.285.14:33:20.94#ibcon#read 4, iclass 33, count 0 2006.285.14:33:20.94#ibcon#about to read 5, iclass 33, count 0 2006.285.14:33:20.94#ibcon#read 5, iclass 33, count 0 2006.285.14:33:20.94#ibcon#about to read 6, iclass 33, count 0 2006.285.14:33:20.94#ibcon#read 6, iclass 33, count 0 2006.285.14:33:20.94#ibcon#end of sib2, iclass 33, count 0 2006.285.14:33:20.94#ibcon#*after write, iclass 33, count 0 2006.285.14:33:20.94#ibcon#*before return 0, iclass 33, count 0 2006.285.14:33:20.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:33:20.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:33:20.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.14:33:20.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.14:33:20.94$vck44/vb=8,4 2006.285.14:33:20.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.14:33:20.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.14:33:20.94#ibcon#ireg 11 cls_cnt 2 2006.285.14:33:20.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:33:21.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:33:21.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:33:21.00#ibcon#enter wrdev, iclass 35, count 2 2006.285.14:33:21.00#ibcon#first serial, iclass 35, count 2 2006.285.14:33:21.00#ibcon#enter sib2, iclass 35, count 2 2006.285.14:33:21.00#ibcon#flushed, iclass 35, count 2 2006.285.14:33:21.00#ibcon#about to write, iclass 35, count 2 2006.285.14:33:21.00#ibcon#wrote, iclass 35, count 2 2006.285.14:33:21.00#ibcon#about to read 3, iclass 35, count 2 2006.285.14:33:21.02#ibcon#read 3, iclass 35, count 2 2006.285.14:33:21.02#ibcon#about to read 4, iclass 35, count 2 2006.285.14:33:21.02#ibcon#read 4, iclass 35, count 2 2006.285.14:33:21.02#ibcon#about to read 5, iclass 35, count 2 2006.285.14:33:21.02#ibcon#read 5, iclass 35, count 2 2006.285.14:33:21.02#ibcon#about to read 6, iclass 35, count 2 2006.285.14:33:21.02#ibcon#read 6, iclass 35, count 2 2006.285.14:33:21.02#ibcon#end of sib2, iclass 35, count 2 2006.285.14:33:21.02#ibcon#*mode == 0, iclass 35, count 2 2006.285.14:33:21.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.14:33:21.02#ibcon#[27=AT08-04\r\n] 2006.285.14:33:21.02#ibcon#*before write, iclass 35, count 2 2006.285.14:33:21.02#ibcon#enter sib2, iclass 35, count 2 2006.285.14:33:21.02#ibcon#flushed, iclass 35, count 2 2006.285.14:33:21.02#ibcon#about to write, iclass 35, count 2 2006.285.14:33:21.02#ibcon#wrote, iclass 35, count 2 2006.285.14:33:21.02#ibcon#about to read 3, iclass 35, count 2 2006.285.14:33:21.05#ibcon#read 3, iclass 35, count 2 2006.285.14:33:21.05#ibcon#about to read 4, iclass 35, count 2 2006.285.14:33:21.05#ibcon#read 4, iclass 35, count 2 2006.285.14:33:21.05#ibcon#about to read 5, iclass 35, count 2 2006.285.14:33:21.05#ibcon#read 5, iclass 35, count 2 2006.285.14:33:21.05#ibcon#about to read 6, iclass 35, count 2 2006.285.14:33:21.05#ibcon#read 6, iclass 35, count 2 2006.285.14:33:21.05#ibcon#end of sib2, iclass 35, count 2 2006.285.14:33:21.05#ibcon#*after write, iclass 35, count 2 2006.285.14:33:21.05#ibcon#*before return 0, iclass 35, count 2 2006.285.14:33:21.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:33:21.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:33:21.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.14:33:21.05#ibcon#ireg 7 cls_cnt 0 2006.285.14:33:21.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:33:21.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:33:21.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:33:21.17#ibcon#enter wrdev, iclass 35, count 0 2006.285.14:33:21.17#ibcon#first serial, iclass 35, count 0 2006.285.14:33:21.17#ibcon#enter sib2, iclass 35, count 0 2006.285.14:33:21.17#ibcon#flushed, iclass 35, count 0 2006.285.14:33:21.17#ibcon#about to write, iclass 35, count 0 2006.285.14:33:21.17#ibcon#wrote, iclass 35, count 0 2006.285.14:33:21.17#ibcon#about to read 3, iclass 35, count 0 2006.285.14:33:21.19#ibcon#read 3, iclass 35, count 0 2006.285.14:33:21.19#ibcon#about to read 4, iclass 35, count 0 2006.285.14:33:21.19#ibcon#read 4, iclass 35, count 0 2006.285.14:33:21.19#ibcon#about to read 5, iclass 35, count 0 2006.285.14:33:21.19#ibcon#read 5, iclass 35, count 0 2006.285.14:33:21.19#ibcon#about to read 6, iclass 35, count 0 2006.285.14:33:21.19#ibcon#read 6, iclass 35, count 0 2006.285.14:33:21.19#ibcon#end of sib2, iclass 35, count 0 2006.285.14:33:21.19#ibcon#*mode == 0, iclass 35, count 0 2006.285.14:33:21.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.14:33:21.19#ibcon#[27=USB\r\n] 2006.285.14:33:21.19#ibcon#*before write, iclass 35, count 0 2006.285.14:33:21.19#ibcon#enter sib2, iclass 35, count 0 2006.285.14:33:21.19#ibcon#flushed, iclass 35, count 0 2006.285.14:33:21.19#ibcon#about to write, iclass 35, count 0 2006.285.14:33:21.19#ibcon#wrote, iclass 35, count 0 2006.285.14:33:21.19#ibcon#about to read 3, iclass 35, count 0 2006.285.14:33:21.22#abcon#<5=/04 1.8 4.5 19.18 941015.1\r\n> 2006.285.14:33:21.22#ibcon#read 3, iclass 35, count 0 2006.285.14:33:21.22#ibcon#about to read 4, iclass 35, count 0 2006.285.14:33:21.22#ibcon#read 4, iclass 35, count 0 2006.285.14:33:21.22#ibcon#about to read 5, iclass 35, count 0 2006.285.14:33:21.22#ibcon#read 5, iclass 35, count 0 2006.285.14:33:21.22#ibcon#about to read 6, iclass 35, count 0 2006.285.14:33:21.22#ibcon#read 6, iclass 35, count 0 2006.285.14:33:21.22#ibcon#end of sib2, iclass 35, count 0 2006.285.14:33:21.22#ibcon#*after write, iclass 35, count 0 2006.285.14:33:21.22#ibcon#*before return 0, iclass 35, count 0 2006.285.14:33:21.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:33:21.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:33:21.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.14:33:21.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.14:33:21.22$vck44/vabw=wide 2006.285.14:33:21.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.14:33:21.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.14:33:21.22#ibcon#ireg 8 cls_cnt 0 2006.285.14:33:21.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:33:21.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:33:21.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:33:21.22#ibcon#enter wrdev, iclass 40, count 0 2006.285.14:33:21.22#ibcon#first serial, iclass 40, count 0 2006.285.14:33:21.22#ibcon#enter sib2, iclass 40, count 0 2006.285.14:33:21.22#ibcon#flushed, iclass 40, count 0 2006.285.14:33:21.22#ibcon#about to write, iclass 40, count 0 2006.285.14:33:21.22#ibcon#wrote, iclass 40, count 0 2006.285.14:33:21.22#ibcon#about to read 3, iclass 40, count 0 2006.285.14:33:21.24#abcon#{5=INTERFACE CLEAR} 2006.285.14:33:21.24#ibcon#read 3, iclass 40, count 0 2006.285.14:33:21.24#ibcon#about to read 4, iclass 40, count 0 2006.285.14:33:21.24#ibcon#read 4, iclass 40, count 0 2006.285.14:33:21.24#ibcon#about to read 5, iclass 40, count 0 2006.285.14:33:21.24#ibcon#read 5, iclass 40, count 0 2006.285.14:33:21.24#ibcon#about to read 6, iclass 40, count 0 2006.285.14:33:21.24#ibcon#read 6, iclass 40, count 0 2006.285.14:33:21.24#ibcon#end of sib2, iclass 40, count 0 2006.285.14:33:21.24#ibcon#*mode == 0, iclass 40, count 0 2006.285.14:33:21.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.14:33:21.24#ibcon#[25=BW32\r\n] 2006.285.14:33:21.24#ibcon#*before write, iclass 40, count 0 2006.285.14:33:21.24#ibcon#enter sib2, iclass 40, count 0 2006.285.14:33:21.24#ibcon#flushed, iclass 40, count 0 2006.285.14:33:21.24#ibcon#about to write, iclass 40, count 0 2006.285.14:33:21.24#ibcon#wrote, iclass 40, count 0 2006.285.14:33:21.24#ibcon#about to read 3, iclass 40, count 0 2006.285.14:33:21.27#ibcon#read 3, iclass 40, count 0 2006.285.14:33:21.27#ibcon#about to read 4, iclass 40, count 0 2006.285.14:33:21.27#ibcon#read 4, iclass 40, count 0 2006.285.14:33:21.27#ibcon#about to read 5, iclass 40, count 0 2006.285.14:33:21.27#ibcon#read 5, iclass 40, count 0 2006.285.14:33:21.27#ibcon#about to read 6, iclass 40, count 0 2006.285.14:33:21.27#ibcon#read 6, iclass 40, count 0 2006.285.14:33:21.27#ibcon#end of sib2, iclass 40, count 0 2006.285.14:33:21.27#ibcon#*after write, iclass 40, count 0 2006.285.14:33:21.27#ibcon#*before return 0, iclass 40, count 0 2006.285.14:33:21.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:33:21.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:33:21.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.14:33:21.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.14:33:21.27$vck44/vbbw=wide 2006.285.14:33:21.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.14:33:21.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.14:33:21.27#ibcon#ireg 8 cls_cnt 0 2006.285.14:33:21.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:33:21.30#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:33:21.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:33:21.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:33:21.34#ibcon#enter wrdev, iclass 4, count 0 2006.285.14:33:21.34#ibcon#first serial, iclass 4, count 0 2006.285.14:33:21.34#ibcon#enter sib2, iclass 4, count 0 2006.285.14:33:21.34#ibcon#flushed, iclass 4, count 0 2006.285.14:33:21.34#ibcon#about to write, iclass 4, count 0 2006.285.14:33:21.34#ibcon#wrote, iclass 4, count 0 2006.285.14:33:21.34#ibcon#about to read 3, iclass 4, count 0 2006.285.14:33:21.36#ibcon#read 3, iclass 4, count 0 2006.285.14:33:21.36#ibcon#about to read 4, iclass 4, count 0 2006.285.14:33:21.36#ibcon#read 4, iclass 4, count 0 2006.285.14:33:21.36#ibcon#about to read 5, iclass 4, count 0 2006.285.14:33:21.36#ibcon#read 5, iclass 4, count 0 2006.285.14:33:21.36#ibcon#about to read 6, iclass 4, count 0 2006.285.14:33:21.36#ibcon#read 6, iclass 4, count 0 2006.285.14:33:21.36#ibcon#end of sib2, iclass 4, count 0 2006.285.14:33:21.36#ibcon#*mode == 0, iclass 4, count 0 2006.285.14:33:21.36#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.14:33:21.36#ibcon#[27=BW32\r\n] 2006.285.14:33:21.36#ibcon#*before write, iclass 4, count 0 2006.285.14:33:21.36#ibcon#enter sib2, iclass 4, count 0 2006.285.14:33:21.36#ibcon#flushed, iclass 4, count 0 2006.285.14:33:21.36#ibcon#about to write, iclass 4, count 0 2006.285.14:33:21.36#ibcon#wrote, iclass 4, count 0 2006.285.14:33:21.36#ibcon#about to read 3, iclass 4, count 0 2006.285.14:33:21.39#ibcon#read 3, iclass 4, count 0 2006.285.14:33:21.39#ibcon#about to read 4, iclass 4, count 0 2006.285.14:33:21.39#ibcon#read 4, iclass 4, count 0 2006.285.14:33:21.39#ibcon#about to read 5, iclass 4, count 0 2006.285.14:33:21.39#ibcon#read 5, iclass 4, count 0 2006.285.14:33:21.39#ibcon#about to read 6, iclass 4, count 0 2006.285.14:33:21.39#ibcon#read 6, iclass 4, count 0 2006.285.14:33:21.39#ibcon#end of sib2, iclass 4, count 0 2006.285.14:33:21.39#ibcon#*after write, iclass 4, count 0 2006.285.14:33:21.39#ibcon#*before return 0, iclass 4, count 0 2006.285.14:33:21.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:33:21.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:33:21.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.14:33:21.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.14:33:21.39$setupk4/ifdk4 2006.285.14:33:21.39$ifdk4/lo= 2006.285.14:33:21.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.14:33:21.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.14:33:21.39$ifdk4/patch= 2006.285.14:33:21.39$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.14:33:21.39$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.14:33:21.39$setupk4/!*+20s 2006.285.14:33:31.39#abcon#<5=/04 1.9 4.5 19.18 941015.0\r\n> 2006.285.14:33:31.41#abcon#{5=INTERFACE CLEAR} 2006.285.14:33:31.47#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:33:34.69$setupk4/"tpicd 2006.285.14:33:34.69$setupk4/echo=off 2006.285.14:33:34.69$setupk4/xlog=off 2006.285.14:33:34.69:!2006.285.14:34:58 2006.285.14:33:47.14#trakl#Source acquired 2006.285.14:33:47.14#flagr#flagr/antenna,acquired 2006.285.14:34:58.00:preob 2006.285.14:34:58.14/onsource/TRACKING 2006.285.14:34:58.14:!2006.285.14:35:08 2006.285.14:35:08.00:"tape 2006.285.14:35:08.00:"st=record 2006.285.14:35:08.00:data_valid=on 2006.285.14:35:08.00:midob 2006.285.14:35:08.14/onsource/TRACKING 2006.285.14:35:08.14/wx/19.18,1015.1,94 2006.285.14:35:08.23/cable/+6.5008E-03 2006.285.14:35:09.32/va/01,07,usb,yes,31,34 2006.285.14:35:09.32/va/02,06,usb,yes,32,32 2006.285.14:35:09.32/va/03,07,usb,yes,31,33 2006.285.14:35:09.32/va/04,06,usb,yes,33,34 2006.285.14:35:09.32/va/05,03,usb,yes,32,32 2006.285.14:35:09.32/va/06,04,usb,yes,29,28 2006.285.14:35:09.32/va/07,04,usb,yes,29,30 2006.285.14:35:09.32/va/08,03,usb,yes,30,37 2006.285.14:35:09.55/valo/01,524.99,yes,locked 2006.285.14:35:09.55/valo/02,534.99,yes,locked 2006.285.14:35:09.55/valo/03,564.99,yes,locked 2006.285.14:35:09.55/valo/04,624.99,yes,locked 2006.285.14:35:09.55/valo/05,734.99,yes,locked 2006.285.14:35:09.55/valo/06,814.99,yes,locked 2006.285.14:35:09.55/valo/07,864.99,yes,locked 2006.285.14:35:09.55/valo/08,884.99,yes,locked 2006.285.14:35:10.64/vb/01,04,usb,yes,30,28 2006.285.14:35:10.64/vb/02,05,usb,yes,28,28 2006.285.14:35:10.64/vb/03,04,usb,yes,29,32 2006.285.14:35:10.64/vb/04,05,usb,yes,29,28 2006.285.14:35:10.64/vb/05,04,usb,yes,26,28 2006.285.14:35:10.64/vb/06,03,usb,yes,37,33 2006.285.14:35:10.64/vb/07,04,usb,yes,30,30 2006.285.14:35:10.64/vb/08,04,usb,yes,27,31 2006.285.14:35:10.87/vblo/01,629.99,yes,locked 2006.285.14:35:10.87/vblo/02,634.99,yes,locked 2006.285.14:35:10.87/vblo/03,649.99,yes,locked 2006.285.14:35:10.87/vblo/04,679.99,yes,locked 2006.285.14:35:10.87/vblo/05,709.99,yes,locked 2006.285.14:35:10.87/vblo/06,719.99,yes,locked 2006.285.14:35:10.87/vblo/07,734.99,yes,locked 2006.285.14:35:10.87/vblo/08,744.99,yes,locked 2006.285.14:35:11.02/vabw/8 2006.285.14:35:11.17/vbbw/8 2006.285.14:35:11.26/xfe/off,on,12.2 2006.285.14:35:11.64/ifatt/23,28,28,28 2006.285.14:35:12.08/fmout-gps/S +2.99E-07 2006.285.14:35:12.10:!2006.285.14:36:58 2006.285.14:36:58.01:data_valid=off 2006.285.14:36:58.01:"et 2006.285.14:36:58.01:!+3s 2006.285.14:37:01.02:"tape 2006.285.14:37:01.02:postob 2006.285.14:37:01.15/cable/+6.4994E-03 2006.285.14:37:01.15/wx/19.19,1015.1,94 2006.285.14:37:02.08/fmout-gps/S +2.96E-07 2006.285.14:37:02.08:scan_name=285-1439,jd0610,230 2006.285.14:37:02.08:source=1044+719,104827.62,714335.9,2000.0,cw 2006.285.14:37:03.13#flagr#flagr/antenna,new-source 2006.285.14:37:03.13:checkk5 2006.285.14:37:03.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.14:37:03.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.14:37:04.40/chk_autoobs//k5ts3/ autoobs is running! 2006.285.14:37:04.76/chk_autoobs//k5ts4/ autoobs is running! 2006.285.14:37:05.21/chk_obsdata//k5ts1/T2851435??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.14:37:05.60/chk_obsdata//k5ts2/T2851435??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.14:37:06.07/chk_obsdata//k5ts3/T2851435??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.14:37:06.70/chk_obsdata//k5ts4/T2851435??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.14:37:07.56/k5log//k5ts1_log_newline 2006.285.14:37:08.35/k5log//k5ts2_log_newline 2006.285.14:37:09.20/k5log//k5ts3_log_newline 2006.285.14:37:09.97/k5log//k5ts4_log_newline 2006.285.14:37:09.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.14:37:09.99:setupk4=1 2006.285.14:37:09.99$setupk4/echo=on 2006.285.14:37:09.99$setupk4/pcalon 2006.285.14:37:09.99$pcalon/"no phase cal control is implemented here 2006.285.14:37:09.99$setupk4/"tpicd=stop 2006.285.14:37:09.99$setupk4/"rec=synch_on 2006.285.14:37:09.99$setupk4/"rec_mode=128 2006.285.14:37:09.99$setupk4/!* 2006.285.14:37:09.99$setupk4/recpk4 2006.285.14:37:10.00$recpk4/recpatch= 2006.285.14:37:10.00$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.14:37:10.00$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.14:37:10.00$setupk4/vck44 2006.285.14:37:10.00$vck44/valo=1,524.99 2006.285.14:37:10.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.14:37:10.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.14:37:10.00#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:10.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:37:10.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:37:10.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:37:10.00#ibcon#enter wrdev, iclass 28, count 0 2006.285.14:37:10.00#ibcon#first serial, iclass 28, count 0 2006.285.14:37:10.00#ibcon#enter sib2, iclass 28, count 0 2006.285.14:37:10.00#ibcon#flushed, iclass 28, count 0 2006.285.14:37:10.00#ibcon#about to write, iclass 28, count 0 2006.285.14:37:10.00#ibcon#wrote, iclass 28, count 0 2006.285.14:37:10.00#ibcon#about to read 3, iclass 28, count 0 2006.285.14:37:10.02#ibcon#read 3, iclass 28, count 0 2006.285.14:37:10.02#ibcon#about to read 4, iclass 28, count 0 2006.285.14:37:10.02#ibcon#read 4, iclass 28, count 0 2006.285.14:37:10.02#ibcon#about to read 5, iclass 28, count 0 2006.285.14:37:10.02#ibcon#read 5, iclass 28, count 0 2006.285.14:37:10.02#ibcon#about to read 6, iclass 28, count 0 2006.285.14:37:10.02#ibcon#read 6, iclass 28, count 0 2006.285.14:37:10.02#ibcon#end of sib2, iclass 28, count 0 2006.285.14:37:10.02#ibcon#*mode == 0, iclass 28, count 0 2006.285.14:37:10.02#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.14:37:10.02#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.14:37:10.02#ibcon#*before write, iclass 28, count 0 2006.285.14:37:10.02#ibcon#enter sib2, iclass 28, count 0 2006.285.14:37:10.02#ibcon#flushed, iclass 28, count 0 2006.285.14:37:10.02#ibcon#about to write, iclass 28, count 0 2006.285.14:37:10.02#ibcon#wrote, iclass 28, count 0 2006.285.14:37:10.02#ibcon#about to read 3, iclass 28, count 0 2006.285.14:37:10.07#ibcon#read 3, iclass 28, count 0 2006.285.14:37:10.07#ibcon#about to read 4, iclass 28, count 0 2006.285.14:37:10.07#ibcon#read 4, iclass 28, count 0 2006.285.14:37:10.07#ibcon#about to read 5, iclass 28, count 0 2006.285.14:37:10.07#ibcon#read 5, iclass 28, count 0 2006.285.14:37:10.07#ibcon#about to read 6, iclass 28, count 0 2006.285.14:37:10.07#ibcon#read 6, iclass 28, count 0 2006.285.14:37:10.07#ibcon#end of sib2, iclass 28, count 0 2006.285.14:37:10.07#ibcon#*after write, iclass 28, count 0 2006.285.14:37:10.07#ibcon#*before return 0, iclass 28, count 0 2006.285.14:37:10.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:37:10.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:37:10.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.14:37:10.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.14:37:10.07$vck44/va=1,7 2006.285.14:37:10.07#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.14:37:10.07#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.14:37:10.07#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:10.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:37:10.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:37:10.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:37:10.07#ibcon#enter wrdev, iclass 30, count 2 2006.285.14:37:10.07#ibcon#first serial, iclass 30, count 2 2006.285.14:37:10.07#ibcon#enter sib2, iclass 30, count 2 2006.285.14:37:10.07#ibcon#flushed, iclass 30, count 2 2006.285.14:37:10.07#ibcon#about to write, iclass 30, count 2 2006.285.14:37:10.07#ibcon#wrote, iclass 30, count 2 2006.285.14:37:10.07#ibcon#about to read 3, iclass 30, count 2 2006.285.14:37:10.09#ibcon#read 3, iclass 30, count 2 2006.285.14:37:10.09#ibcon#about to read 4, iclass 30, count 2 2006.285.14:37:10.09#ibcon#read 4, iclass 30, count 2 2006.285.14:37:10.09#ibcon#about to read 5, iclass 30, count 2 2006.285.14:37:10.09#ibcon#read 5, iclass 30, count 2 2006.285.14:37:10.09#ibcon#about to read 6, iclass 30, count 2 2006.285.14:37:10.09#ibcon#read 6, iclass 30, count 2 2006.285.14:37:10.09#ibcon#end of sib2, iclass 30, count 2 2006.285.14:37:10.09#ibcon#*mode == 0, iclass 30, count 2 2006.285.14:37:10.09#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.14:37:10.09#ibcon#[25=AT01-07\r\n] 2006.285.14:37:10.09#ibcon#*before write, iclass 30, count 2 2006.285.14:37:10.09#ibcon#enter sib2, iclass 30, count 2 2006.285.14:37:10.09#ibcon#flushed, iclass 30, count 2 2006.285.14:37:10.09#ibcon#about to write, iclass 30, count 2 2006.285.14:37:10.09#ibcon#wrote, iclass 30, count 2 2006.285.14:37:10.09#ibcon#about to read 3, iclass 30, count 2 2006.285.14:37:10.12#ibcon#read 3, iclass 30, count 2 2006.285.14:37:10.12#ibcon#about to read 4, iclass 30, count 2 2006.285.14:37:10.12#ibcon#read 4, iclass 30, count 2 2006.285.14:37:10.12#ibcon#about to read 5, iclass 30, count 2 2006.285.14:37:10.12#ibcon#read 5, iclass 30, count 2 2006.285.14:37:10.12#ibcon#about to read 6, iclass 30, count 2 2006.285.14:37:10.12#ibcon#read 6, iclass 30, count 2 2006.285.14:37:10.12#ibcon#end of sib2, iclass 30, count 2 2006.285.14:37:10.12#ibcon#*after write, iclass 30, count 2 2006.285.14:37:10.12#ibcon#*before return 0, iclass 30, count 2 2006.285.14:37:10.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:37:10.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:37:10.12#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.14:37:10.12#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:10.12#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:37:10.24#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:37:10.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:37:10.24#ibcon#enter wrdev, iclass 30, count 0 2006.285.14:37:10.24#ibcon#first serial, iclass 30, count 0 2006.285.14:37:10.24#ibcon#enter sib2, iclass 30, count 0 2006.285.14:37:10.24#ibcon#flushed, iclass 30, count 0 2006.285.14:37:10.24#ibcon#about to write, iclass 30, count 0 2006.285.14:37:10.24#ibcon#wrote, iclass 30, count 0 2006.285.14:37:10.24#ibcon#about to read 3, iclass 30, count 0 2006.285.14:37:10.26#ibcon#read 3, iclass 30, count 0 2006.285.14:37:10.26#ibcon#about to read 4, iclass 30, count 0 2006.285.14:37:10.26#ibcon#read 4, iclass 30, count 0 2006.285.14:37:10.26#ibcon#about to read 5, iclass 30, count 0 2006.285.14:37:10.26#ibcon#read 5, iclass 30, count 0 2006.285.14:37:10.26#ibcon#about to read 6, iclass 30, count 0 2006.285.14:37:10.26#ibcon#read 6, iclass 30, count 0 2006.285.14:37:10.26#ibcon#end of sib2, iclass 30, count 0 2006.285.14:37:10.26#ibcon#*mode == 0, iclass 30, count 0 2006.285.14:37:10.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.14:37:10.26#ibcon#[25=USB\r\n] 2006.285.14:37:10.26#ibcon#*before write, iclass 30, count 0 2006.285.14:37:10.26#ibcon#enter sib2, iclass 30, count 0 2006.285.14:37:10.26#ibcon#flushed, iclass 30, count 0 2006.285.14:37:10.26#ibcon#about to write, iclass 30, count 0 2006.285.14:37:10.26#ibcon#wrote, iclass 30, count 0 2006.285.14:37:10.26#ibcon#about to read 3, iclass 30, count 0 2006.285.14:37:10.29#ibcon#read 3, iclass 30, count 0 2006.285.14:37:10.29#ibcon#about to read 4, iclass 30, count 0 2006.285.14:37:10.29#ibcon#read 4, iclass 30, count 0 2006.285.14:37:10.29#ibcon#about to read 5, iclass 30, count 0 2006.285.14:37:10.29#ibcon#read 5, iclass 30, count 0 2006.285.14:37:10.29#ibcon#about to read 6, iclass 30, count 0 2006.285.14:37:10.29#ibcon#read 6, iclass 30, count 0 2006.285.14:37:10.29#ibcon#end of sib2, iclass 30, count 0 2006.285.14:37:10.29#ibcon#*after write, iclass 30, count 0 2006.285.14:37:10.29#ibcon#*before return 0, iclass 30, count 0 2006.285.14:37:10.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:37:10.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:37:10.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.14:37:10.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.14:37:10.29$vck44/valo=2,534.99 2006.285.14:37:10.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.14:37:10.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.14:37:10.29#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:10.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:37:10.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:37:10.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:37:10.29#ibcon#enter wrdev, iclass 32, count 0 2006.285.14:37:10.29#ibcon#first serial, iclass 32, count 0 2006.285.14:37:10.29#ibcon#enter sib2, iclass 32, count 0 2006.285.14:37:10.29#ibcon#flushed, iclass 32, count 0 2006.285.14:37:10.29#ibcon#about to write, iclass 32, count 0 2006.285.14:37:10.29#ibcon#wrote, iclass 32, count 0 2006.285.14:37:10.29#ibcon#about to read 3, iclass 32, count 0 2006.285.14:37:10.31#ibcon#read 3, iclass 32, count 0 2006.285.14:37:10.31#ibcon#about to read 4, iclass 32, count 0 2006.285.14:37:10.31#ibcon#read 4, iclass 32, count 0 2006.285.14:37:10.31#ibcon#about to read 5, iclass 32, count 0 2006.285.14:37:10.31#ibcon#read 5, iclass 32, count 0 2006.285.14:37:10.31#ibcon#about to read 6, iclass 32, count 0 2006.285.14:37:10.31#ibcon#read 6, iclass 32, count 0 2006.285.14:37:10.31#ibcon#end of sib2, iclass 32, count 0 2006.285.14:37:10.31#ibcon#*mode == 0, iclass 32, count 0 2006.285.14:37:10.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.14:37:10.31#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.14:37:10.31#ibcon#*before write, iclass 32, count 0 2006.285.14:37:10.31#ibcon#enter sib2, iclass 32, count 0 2006.285.14:37:10.31#ibcon#flushed, iclass 32, count 0 2006.285.14:37:10.31#ibcon#about to write, iclass 32, count 0 2006.285.14:37:10.31#ibcon#wrote, iclass 32, count 0 2006.285.14:37:10.31#ibcon#about to read 3, iclass 32, count 0 2006.285.14:37:10.35#ibcon#read 3, iclass 32, count 0 2006.285.14:37:10.35#ibcon#about to read 4, iclass 32, count 0 2006.285.14:37:10.35#ibcon#read 4, iclass 32, count 0 2006.285.14:37:10.35#ibcon#about to read 5, iclass 32, count 0 2006.285.14:37:10.35#ibcon#read 5, iclass 32, count 0 2006.285.14:37:10.35#ibcon#about to read 6, iclass 32, count 0 2006.285.14:37:10.35#ibcon#read 6, iclass 32, count 0 2006.285.14:37:10.35#ibcon#end of sib2, iclass 32, count 0 2006.285.14:37:10.35#ibcon#*after write, iclass 32, count 0 2006.285.14:37:10.35#ibcon#*before return 0, iclass 32, count 0 2006.285.14:37:10.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:37:10.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:37:10.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.14:37:10.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.14:37:10.35$vck44/va=2,6 2006.285.14:37:10.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.14:37:10.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.14:37:10.35#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:10.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:37:10.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:37:10.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:37:10.41#ibcon#enter wrdev, iclass 34, count 2 2006.285.14:37:10.41#ibcon#first serial, iclass 34, count 2 2006.285.14:37:10.41#ibcon#enter sib2, iclass 34, count 2 2006.285.14:37:10.41#ibcon#flushed, iclass 34, count 2 2006.285.14:37:10.41#ibcon#about to write, iclass 34, count 2 2006.285.14:37:10.41#ibcon#wrote, iclass 34, count 2 2006.285.14:37:10.41#ibcon#about to read 3, iclass 34, count 2 2006.285.14:37:10.43#ibcon#read 3, iclass 34, count 2 2006.285.14:37:10.43#ibcon#about to read 4, iclass 34, count 2 2006.285.14:37:10.43#ibcon#read 4, iclass 34, count 2 2006.285.14:37:10.43#ibcon#about to read 5, iclass 34, count 2 2006.285.14:37:10.43#ibcon#read 5, iclass 34, count 2 2006.285.14:37:10.43#ibcon#about to read 6, iclass 34, count 2 2006.285.14:37:10.43#ibcon#read 6, iclass 34, count 2 2006.285.14:37:10.43#ibcon#end of sib2, iclass 34, count 2 2006.285.14:37:10.43#ibcon#*mode == 0, iclass 34, count 2 2006.285.14:37:10.43#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.14:37:10.43#ibcon#[25=AT02-06\r\n] 2006.285.14:37:10.43#ibcon#*before write, iclass 34, count 2 2006.285.14:37:10.43#ibcon#enter sib2, iclass 34, count 2 2006.285.14:37:10.43#ibcon#flushed, iclass 34, count 2 2006.285.14:37:10.43#ibcon#about to write, iclass 34, count 2 2006.285.14:37:10.43#ibcon#wrote, iclass 34, count 2 2006.285.14:37:10.43#ibcon#about to read 3, iclass 34, count 2 2006.285.14:37:10.46#ibcon#read 3, iclass 34, count 2 2006.285.14:37:10.46#ibcon#about to read 4, iclass 34, count 2 2006.285.14:37:10.46#ibcon#read 4, iclass 34, count 2 2006.285.14:37:10.46#ibcon#about to read 5, iclass 34, count 2 2006.285.14:37:10.46#ibcon#read 5, iclass 34, count 2 2006.285.14:37:10.46#ibcon#about to read 6, iclass 34, count 2 2006.285.14:37:10.46#ibcon#read 6, iclass 34, count 2 2006.285.14:37:10.46#ibcon#end of sib2, iclass 34, count 2 2006.285.14:37:10.46#ibcon#*after write, iclass 34, count 2 2006.285.14:37:10.46#ibcon#*before return 0, iclass 34, count 2 2006.285.14:37:10.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:37:10.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:37:10.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.14:37:10.46#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:10.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:37:10.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:37:10.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:37:10.58#ibcon#enter wrdev, iclass 34, count 0 2006.285.14:37:10.58#ibcon#first serial, iclass 34, count 0 2006.285.14:37:10.58#ibcon#enter sib2, iclass 34, count 0 2006.285.14:37:10.58#ibcon#flushed, iclass 34, count 0 2006.285.14:37:10.58#ibcon#about to write, iclass 34, count 0 2006.285.14:37:10.58#ibcon#wrote, iclass 34, count 0 2006.285.14:37:10.58#ibcon#about to read 3, iclass 34, count 0 2006.285.14:37:10.60#ibcon#read 3, iclass 34, count 0 2006.285.14:37:10.60#ibcon#about to read 4, iclass 34, count 0 2006.285.14:37:10.60#ibcon#read 4, iclass 34, count 0 2006.285.14:37:10.60#ibcon#about to read 5, iclass 34, count 0 2006.285.14:37:10.60#ibcon#read 5, iclass 34, count 0 2006.285.14:37:10.60#ibcon#about to read 6, iclass 34, count 0 2006.285.14:37:10.60#ibcon#read 6, iclass 34, count 0 2006.285.14:37:10.60#ibcon#end of sib2, iclass 34, count 0 2006.285.14:37:10.60#ibcon#*mode == 0, iclass 34, count 0 2006.285.14:37:10.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.14:37:10.60#ibcon#[25=USB\r\n] 2006.285.14:37:10.60#ibcon#*before write, iclass 34, count 0 2006.285.14:37:10.60#ibcon#enter sib2, iclass 34, count 0 2006.285.14:37:10.60#ibcon#flushed, iclass 34, count 0 2006.285.14:37:10.60#ibcon#about to write, iclass 34, count 0 2006.285.14:37:10.60#ibcon#wrote, iclass 34, count 0 2006.285.14:37:10.60#ibcon#about to read 3, iclass 34, count 0 2006.285.14:37:10.63#ibcon#read 3, iclass 34, count 0 2006.285.14:37:10.63#ibcon#about to read 4, iclass 34, count 0 2006.285.14:37:10.63#ibcon#read 4, iclass 34, count 0 2006.285.14:37:10.63#ibcon#about to read 5, iclass 34, count 0 2006.285.14:37:10.63#ibcon#read 5, iclass 34, count 0 2006.285.14:37:10.63#ibcon#about to read 6, iclass 34, count 0 2006.285.14:37:10.63#ibcon#read 6, iclass 34, count 0 2006.285.14:37:10.63#ibcon#end of sib2, iclass 34, count 0 2006.285.14:37:10.63#ibcon#*after write, iclass 34, count 0 2006.285.14:37:10.63#ibcon#*before return 0, iclass 34, count 0 2006.285.14:37:10.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:37:10.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:37:10.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.14:37:10.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.14:37:10.63$vck44/valo=3,564.99 2006.285.14:37:10.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.14:37:10.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.14:37:10.63#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:10.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:37:10.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:37:10.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:37:10.63#ibcon#enter wrdev, iclass 36, count 0 2006.285.14:37:10.63#ibcon#first serial, iclass 36, count 0 2006.285.14:37:10.63#ibcon#enter sib2, iclass 36, count 0 2006.285.14:37:10.63#ibcon#flushed, iclass 36, count 0 2006.285.14:37:10.63#ibcon#about to write, iclass 36, count 0 2006.285.14:37:10.63#ibcon#wrote, iclass 36, count 0 2006.285.14:37:10.63#ibcon#about to read 3, iclass 36, count 0 2006.285.14:37:10.65#ibcon#read 3, iclass 36, count 0 2006.285.14:37:10.65#ibcon#about to read 4, iclass 36, count 0 2006.285.14:37:10.65#ibcon#read 4, iclass 36, count 0 2006.285.14:37:10.65#ibcon#about to read 5, iclass 36, count 0 2006.285.14:37:10.65#ibcon#read 5, iclass 36, count 0 2006.285.14:37:10.65#ibcon#about to read 6, iclass 36, count 0 2006.285.14:37:10.65#ibcon#read 6, iclass 36, count 0 2006.285.14:37:10.65#ibcon#end of sib2, iclass 36, count 0 2006.285.14:37:10.65#ibcon#*mode == 0, iclass 36, count 0 2006.285.14:37:10.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.14:37:10.65#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.14:37:10.65#ibcon#*before write, iclass 36, count 0 2006.285.14:37:10.65#ibcon#enter sib2, iclass 36, count 0 2006.285.14:37:10.65#ibcon#flushed, iclass 36, count 0 2006.285.14:37:10.65#ibcon#about to write, iclass 36, count 0 2006.285.14:37:10.65#ibcon#wrote, iclass 36, count 0 2006.285.14:37:10.65#ibcon#about to read 3, iclass 36, count 0 2006.285.14:37:10.69#ibcon#read 3, iclass 36, count 0 2006.285.14:37:10.69#ibcon#about to read 4, iclass 36, count 0 2006.285.14:37:10.69#ibcon#read 4, iclass 36, count 0 2006.285.14:37:10.69#ibcon#about to read 5, iclass 36, count 0 2006.285.14:37:10.69#ibcon#read 5, iclass 36, count 0 2006.285.14:37:10.69#ibcon#about to read 6, iclass 36, count 0 2006.285.14:37:10.69#ibcon#read 6, iclass 36, count 0 2006.285.14:37:10.69#ibcon#end of sib2, iclass 36, count 0 2006.285.14:37:10.69#ibcon#*after write, iclass 36, count 0 2006.285.14:37:10.69#ibcon#*before return 0, iclass 36, count 0 2006.285.14:37:10.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:37:10.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:37:10.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.14:37:10.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.14:37:10.69$vck44/va=3,7 2006.285.14:37:10.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.14:37:10.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.14:37:10.69#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:10.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:37:10.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:37:10.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:37:10.75#ibcon#enter wrdev, iclass 38, count 2 2006.285.14:37:10.75#ibcon#first serial, iclass 38, count 2 2006.285.14:37:10.75#ibcon#enter sib2, iclass 38, count 2 2006.285.14:37:10.75#ibcon#flushed, iclass 38, count 2 2006.285.14:37:10.75#ibcon#about to write, iclass 38, count 2 2006.285.14:37:10.75#ibcon#wrote, iclass 38, count 2 2006.285.14:37:10.75#ibcon#about to read 3, iclass 38, count 2 2006.285.14:37:10.77#ibcon#read 3, iclass 38, count 2 2006.285.14:37:10.77#ibcon#about to read 4, iclass 38, count 2 2006.285.14:37:10.77#ibcon#read 4, iclass 38, count 2 2006.285.14:37:10.77#ibcon#about to read 5, iclass 38, count 2 2006.285.14:37:10.77#ibcon#read 5, iclass 38, count 2 2006.285.14:37:10.77#ibcon#about to read 6, iclass 38, count 2 2006.285.14:37:10.77#ibcon#read 6, iclass 38, count 2 2006.285.14:37:10.77#ibcon#end of sib2, iclass 38, count 2 2006.285.14:37:10.77#ibcon#*mode == 0, iclass 38, count 2 2006.285.14:37:10.77#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.14:37:10.77#ibcon#[25=AT03-07\r\n] 2006.285.14:37:10.77#ibcon#*before write, iclass 38, count 2 2006.285.14:37:10.77#ibcon#enter sib2, iclass 38, count 2 2006.285.14:37:10.77#ibcon#flushed, iclass 38, count 2 2006.285.14:37:10.77#ibcon#about to write, iclass 38, count 2 2006.285.14:37:10.77#ibcon#wrote, iclass 38, count 2 2006.285.14:37:10.77#ibcon#about to read 3, iclass 38, count 2 2006.285.14:37:10.80#ibcon#read 3, iclass 38, count 2 2006.285.14:37:10.80#ibcon#about to read 4, iclass 38, count 2 2006.285.14:37:10.80#ibcon#read 4, iclass 38, count 2 2006.285.14:37:10.80#ibcon#about to read 5, iclass 38, count 2 2006.285.14:37:10.80#ibcon#read 5, iclass 38, count 2 2006.285.14:37:10.80#ibcon#about to read 6, iclass 38, count 2 2006.285.14:37:10.80#ibcon#read 6, iclass 38, count 2 2006.285.14:37:10.80#ibcon#end of sib2, iclass 38, count 2 2006.285.14:37:10.80#ibcon#*after write, iclass 38, count 2 2006.285.14:37:10.80#ibcon#*before return 0, iclass 38, count 2 2006.285.14:37:10.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:37:10.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:37:10.80#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.14:37:10.80#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:10.80#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:37:10.92#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:37:10.92#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:37:10.92#ibcon#enter wrdev, iclass 38, count 0 2006.285.14:37:10.92#ibcon#first serial, iclass 38, count 0 2006.285.14:37:10.92#ibcon#enter sib2, iclass 38, count 0 2006.285.14:37:10.92#ibcon#flushed, iclass 38, count 0 2006.285.14:37:10.92#ibcon#about to write, iclass 38, count 0 2006.285.14:37:10.92#ibcon#wrote, iclass 38, count 0 2006.285.14:37:10.92#ibcon#about to read 3, iclass 38, count 0 2006.285.14:37:10.94#ibcon#read 3, iclass 38, count 0 2006.285.14:37:10.94#ibcon#about to read 4, iclass 38, count 0 2006.285.14:37:10.94#ibcon#read 4, iclass 38, count 0 2006.285.14:37:10.94#ibcon#about to read 5, iclass 38, count 0 2006.285.14:37:10.94#ibcon#read 5, iclass 38, count 0 2006.285.14:37:10.94#ibcon#about to read 6, iclass 38, count 0 2006.285.14:37:10.94#ibcon#read 6, iclass 38, count 0 2006.285.14:37:10.94#ibcon#end of sib2, iclass 38, count 0 2006.285.14:37:10.94#ibcon#*mode == 0, iclass 38, count 0 2006.285.14:37:10.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.14:37:10.94#ibcon#[25=USB\r\n] 2006.285.14:37:10.94#ibcon#*before write, iclass 38, count 0 2006.285.14:37:10.94#ibcon#enter sib2, iclass 38, count 0 2006.285.14:37:10.94#ibcon#flushed, iclass 38, count 0 2006.285.14:37:10.94#ibcon#about to write, iclass 38, count 0 2006.285.14:37:10.94#ibcon#wrote, iclass 38, count 0 2006.285.14:37:10.94#ibcon#about to read 3, iclass 38, count 0 2006.285.14:37:10.97#ibcon#read 3, iclass 38, count 0 2006.285.14:37:10.97#ibcon#about to read 4, iclass 38, count 0 2006.285.14:37:10.97#ibcon#read 4, iclass 38, count 0 2006.285.14:37:10.97#ibcon#about to read 5, iclass 38, count 0 2006.285.14:37:10.97#ibcon#read 5, iclass 38, count 0 2006.285.14:37:10.97#ibcon#about to read 6, iclass 38, count 0 2006.285.14:37:10.97#ibcon#read 6, iclass 38, count 0 2006.285.14:37:10.97#ibcon#end of sib2, iclass 38, count 0 2006.285.14:37:10.97#ibcon#*after write, iclass 38, count 0 2006.285.14:37:10.97#ibcon#*before return 0, iclass 38, count 0 2006.285.14:37:10.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:37:10.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:37:10.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.14:37:10.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.14:37:10.97$vck44/valo=4,624.99 2006.285.14:37:10.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.14:37:10.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.14:37:10.97#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:10.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:37:10.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:37:10.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:37:10.97#ibcon#enter wrdev, iclass 40, count 0 2006.285.14:37:10.97#ibcon#first serial, iclass 40, count 0 2006.285.14:37:10.97#ibcon#enter sib2, iclass 40, count 0 2006.285.14:37:10.97#ibcon#flushed, iclass 40, count 0 2006.285.14:37:10.97#ibcon#about to write, iclass 40, count 0 2006.285.14:37:11.69#ibcon#wrote, iclass 40, count 0 2006.285.14:37:11.69#ibcon#about to read 3, iclass 40, count 0 2006.285.14:37:11.71#ibcon#read 3, iclass 40, count 0 2006.285.14:37:11.71#ibcon#about to read 4, iclass 40, count 0 2006.285.14:37:11.71#ibcon#read 4, iclass 40, count 0 2006.285.14:37:11.71#ibcon#about to read 5, iclass 40, count 0 2006.285.14:37:11.71#ibcon#read 5, iclass 40, count 0 2006.285.14:37:11.71#ibcon#about to read 6, iclass 40, count 0 2006.285.14:37:11.71#ibcon#read 6, iclass 40, count 0 2006.285.14:37:11.71#ibcon#end of sib2, iclass 40, count 0 2006.285.14:37:11.71#ibcon#*mode == 0, iclass 40, count 0 2006.285.14:37:11.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.14:37:11.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.14:37:11.71#ibcon#*before write, iclass 40, count 0 2006.285.14:37:11.71#ibcon#enter sib2, iclass 40, count 0 2006.285.14:37:11.71#ibcon#flushed, iclass 40, count 0 2006.285.14:37:11.71#ibcon#about to write, iclass 40, count 0 2006.285.14:37:11.71#ibcon#wrote, iclass 40, count 0 2006.285.14:37:11.71#ibcon#about to read 3, iclass 40, count 0 2006.285.14:37:11.75#ibcon#read 3, iclass 40, count 0 2006.285.14:37:11.75#ibcon#about to read 4, iclass 40, count 0 2006.285.14:37:11.75#ibcon#read 4, iclass 40, count 0 2006.285.14:37:11.75#ibcon#about to read 5, iclass 40, count 0 2006.285.14:37:11.75#ibcon#read 5, iclass 40, count 0 2006.285.14:37:11.75#ibcon#about to read 6, iclass 40, count 0 2006.285.14:37:11.75#ibcon#read 6, iclass 40, count 0 2006.285.14:37:11.75#ibcon#end of sib2, iclass 40, count 0 2006.285.14:37:11.75#ibcon#*after write, iclass 40, count 0 2006.285.14:37:11.75#ibcon#*before return 0, iclass 40, count 0 2006.285.14:37:11.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:37:11.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:37:11.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.14:37:11.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.14:37:11.75$vck44/va=4,6 2006.285.14:37:11.75#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.14:37:11.75#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.14:37:11.75#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:11.75#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:37:11.75#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:37:11.75#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:37:11.75#ibcon#enter wrdev, iclass 4, count 2 2006.285.14:37:11.75#ibcon#first serial, iclass 4, count 2 2006.285.14:37:11.75#ibcon#enter sib2, iclass 4, count 2 2006.285.14:37:11.75#ibcon#flushed, iclass 4, count 2 2006.285.14:37:11.75#ibcon#about to write, iclass 4, count 2 2006.285.14:37:11.75#ibcon#wrote, iclass 4, count 2 2006.285.14:37:11.75#ibcon#about to read 3, iclass 4, count 2 2006.285.14:37:11.77#ibcon#read 3, iclass 4, count 2 2006.285.14:37:11.77#ibcon#about to read 4, iclass 4, count 2 2006.285.14:37:11.77#ibcon#read 4, iclass 4, count 2 2006.285.14:37:11.77#ibcon#about to read 5, iclass 4, count 2 2006.285.14:37:11.77#ibcon#read 5, iclass 4, count 2 2006.285.14:37:11.77#ibcon#about to read 6, iclass 4, count 2 2006.285.14:37:11.77#ibcon#read 6, iclass 4, count 2 2006.285.14:37:11.77#ibcon#end of sib2, iclass 4, count 2 2006.285.14:37:11.77#ibcon#*mode == 0, iclass 4, count 2 2006.285.14:37:11.77#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.14:37:11.77#ibcon#[25=AT04-06\r\n] 2006.285.14:37:11.77#ibcon#*before write, iclass 4, count 2 2006.285.14:37:11.77#ibcon#enter sib2, iclass 4, count 2 2006.285.14:37:11.77#ibcon#flushed, iclass 4, count 2 2006.285.14:37:11.77#ibcon#about to write, iclass 4, count 2 2006.285.14:37:11.77#ibcon#wrote, iclass 4, count 2 2006.285.14:37:11.77#ibcon#about to read 3, iclass 4, count 2 2006.285.14:37:11.80#ibcon#read 3, iclass 4, count 2 2006.285.14:37:11.80#ibcon#about to read 4, iclass 4, count 2 2006.285.14:37:11.80#ibcon#read 4, iclass 4, count 2 2006.285.14:37:11.80#ibcon#about to read 5, iclass 4, count 2 2006.285.14:37:11.80#ibcon#read 5, iclass 4, count 2 2006.285.14:37:11.80#ibcon#about to read 6, iclass 4, count 2 2006.285.14:37:11.80#ibcon#read 6, iclass 4, count 2 2006.285.14:37:11.80#ibcon#end of sib2, iclass 4, count 2 2006.285.14:37:11.80#ibcon#*after write, iclass 4, count 2 2006.285.14:37:11.80#ibcon#*before return 0, iclass 4, count 2 2006.285.14:37:11.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:37:11.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:37:11.80#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.14:37:11.80#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:11.80#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:37:11.92#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:37:11.92#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:37:11.92#ibcon#enter wrdev, iclass 4, count 0 2006.285.14:37:11.92#ibcon#first serial, iclass 4, count 0 2006.285.14:37:11.92#ibcon#enter sib2, iclass 4, count 0 2006.285.14:37:11.92#ibcon#flushed, iclass 4, count 0 2006.285.14:37:11.92#ibcon#about to write, iclass 4, count 0 2006.285.14:37:11.92#ibcon#wrote, iclass 4, count 0 2006.285.14:37:11.92#ibcon#about to read 3, iclass 4, count 0 2006.285.14:37:11.94#ibcon#read 3, iclass 4, count 0 2006.285.14:37:11.94#ibcon#about to read 4, iclass 4, count 0 2006.285.14:37:11.94#ibcon#read 4, iclass 4, count 0 2006.285.14:37:11.94#ibcon#about to read 5, iclass 4, count 0 2006.285.14:37:11.94#ibcon#read 5, iclass 4, count 0 2006.285.14:37:11.94#ibcon#about to read 6, iclass 4, count 0 2006.285.14:37:11.94#ibcon#read 6, iclass 4, count 0 2006.285.14:37:11.94#ibcon#end of sib2, iclass 4, count 0 2006.285.14:37:11.94#ibcon#*mode == 0, iclass 4, count 0 2006.285.14:37:11.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.14:37:11.94#ibcon#[25=USB\r\n] 2006.285.14:37:11.94#ibcon#*before write, iclass 4, count 0 2006.285.14:37:11.94#ibcon#enter sib2, iclass 4, count 0 2006.285.14:37:11.94#ibcon#flushed, iclass 4, count 0 2006.285.14:37:11.94#ibcon#about to write, iclass 4, count 0 2006.285.14:37:11.94#ibcon#wrote, iclass 4, count 0 2006.285.14:37:11.94#ibcon#about to read 3, iclass 4, count 0 2006.285.14:37:11.97#ibcon#read 3, iclass 4, count 0 2006.285.14:37:11.97#ibcon#about to read 4, iclass 4, count 0 2006.285.14:37:11.97#ibcon#read 4, iclass 4, count 0 2006.285.14:37:11.97#ibcon#about to read 5, iclass 4, count 0 2006.285.14:37:11.97#ibcon#read 5, iclass 4, count 0 2006.285.14:37:11.97#ibcon#about to read 6, iclass 4, count 0 2006.285.14:37:11.97#ibcon#read 6, iclass 4, count 0 2006.285.14:37:11.97#ibcon#end of sib2, iclass 4, count 0 2006.285.14:37:11.97#ibcon#*after write, iclass 4, count 0 2006.285.14:37:11.97#ibcon#*before return 0, iclass 4, count 0 2006.285.14:37:11.97#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:37:11.97#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:37:11.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.14:37:11.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.14:37:11.97$vck44/valo=5,734.99 2006.285.14:37:11.97#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.14:37:11.97#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.14:37:11.97#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:11.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:37:11.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:37:11.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:37:11.97#ibcon#enter wrdev, iclass 6, count 0 2006.285.14:37:11.97#ibcon#first serial, iclass 6, count 0 2006.285.14:37:11.97#ibcon#enter sib2, iclass 6, count 0 2006.285.14:37:11.97#ibcon#flushed, iclass 6, count 0 2006.285.14:37:11.97#ibcon#about to write, iclass 6, count 0 2006.285.14:37:12.26#ibcon#wrote, iclass 6, count 0 2006.285.14:37:12.26#ibcon#about to read 3, iclass 6, count 0 2006.285.14:37:12.27#ibcon#read 3, iclass 6, count 0 2006.285.14:37:12.27#ibcon#about to read 4, iclass 6, count 0 2006.285.14:37:12.27#ibcon#read 4, iclass 6, count 0 2006.285.14:37:12.27#ibcon#about to read 5, iclass 6, count 0 2006.285.14:37:12.27#ibcon#read 5, iclass 6, count 0 2006.285.14:37:12.27#ibcon#about to read 6, iclass 6, count 0 2006.285.14:37:12.27#ibcon#read 6, iclass 6, count 0 2006.285.14:37:12.27#ibcon#end of sib2, iclass 6, count 0 2006.285.14:37:12.27#ibcon#*mode == 0, iclass 6, count 0 2006.285.14:37:12.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.14:37:12.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.14:37:12.27#ibcon#*before write, iclass 6, count 0 2006.285.14:37:12.27#ibcon#enter sib2, iclass 6, count 0 2006.285.14:37:12.27#ibcon#flushed, iclass 6, count 0 2006.285.14:37:12.27#ibcon#about to write, iclass 6, count 0 2006.285.14:37:12.27#ibcon#wrote, iclass 6, count 0 2006.285.14:37:12.27#ibcon#about to read 3, iclass 6, count 0 2006.285.14:37:12.31#ibcon#read 3, iclass 6, count 0 2006.285.14:37:12.31#ibcon#about to read 4, iclass 6, count 0 2006.285.14:37:12.31#ibcon#read 4, iclass 6, count 0 2006.285.14:37:12.31#ibcon#about to read 5, iclass 6, count 0 2006.285.14:37:12.31#ibcon#read 5, iclass 6, count 0 2006.285.14:37:12.31#ibcon#about to read 6, iclass 6, count 0 2006.285.14:37:12.31#ibcon#read 6, iclass 6, count 0 2006.285.14:37:12.31#ibcon#end of sib2, iclass 6, count 0 2006.285.14:37:12.31#ibcon#*after write, iclass 6, count 0 2006.285.14:37:12.31#ibcon#*before return 0, iclass 6, count 0 2006.285.14:37:12.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:37:12.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.14:37:12.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.14:37:12.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.14:37:12.31$vck44/va=5,3 2006.285.14:37:12.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.14:37:12.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.14:37:12.31#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:12.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:37:12.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:37:12.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:37:12.31#ibcon#enter wrdev, iclass 10, count 2 2006.285.14:37:12.31#ibcon#first serial, iclass 10, count 2 2006.285.14:37:12.31#ibcon#enter sib2, iclass 10, count 2 2006.285.14:37:12.31#ibcon#flushed, iclass 10, count 2 2006.285.14:37:12.31#ibcon#about to write, iclass 10, count 2 2006.285.14:37:12.31#ibcon#wrote, iclass 10, count 2 2006.285.14:37:12.31#ibcon#about to read 3, iclass 10, count 2 2006.285.14:37:12.33#ibcon#read 3, iclass 10, count 2 2006.285.14:37:12.33#ibcon#about to read 4, iclass 10, count 2 2006.285.14:37:12.33#ibcon#read 4, iclass 10, count 2 2006.285.14:37:12.33#ibcon#about to read 5, iclass 10, count 2 2006.285.14:37:12.33#ibcon#read 5, iclass 10, count 2 2006.285.14:37:12.33#ibcon#about to read 6, iclass 10, count 2 2006.285.14:37:12.33#ibcon#read 6, iclass 10, count 2 2006.285.14:37:12.33#ibcon#end of sib2, iclass 10, count 2 2006.285.14:37:12.33#ibcon#*mode == 0, iclass 10, count 2 2006.285.14:37:12.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.14:37:12.33#ibcon#[25=AT05-03\r\n] 2006.285.14:37:12.33#ibcon#*before write, iclass 10, count 2 2006.285.14:37:12.33#ibcon#enter sib2, iclass 10, count 2 2006.285.14:37:12.33#ibcon#flushed, iclass 10, count 2 2006.285.14:37:12.33#ibcon#about to write, iclass 10, count 2 2006.285.14:37:12.33#ibcon#wrote, iclass 10, count 2 2006.285.14:37:12.33#ibcon#about to read 3, iclass 10, count 2 2006.285.14:37:12.36#ibcon#read 3, iclass 10, count 2 2006.285.14:37:12.36#ibcon#about to read 4, iclass 10, count 2 2006.285.14:37:12.36#ibcon#read 4, iclass 10, count 2 2006.285.14:37:12.36#ibcon#about to read 5, iclass 10, count 2 2006.285.14:37:12.36#ibcon#read 5, iclass 10, count 2 2006.285.14:37:12.36#ibcon#about to read 6, iclass 10, count 2 2006.285.14:37:12.36#ibcon#read 6, iclass 10, count 2 2006.285.14:37:12.36#ibcon#end of sib2, iclass 10, count 2 2006.285.14:37:12.36#ibcon#*after write, iclass 10, count 2 2006.285.14:37:12.36#ibcon#*before return 0, iclass 10, count 2 2006.285.14:37:12.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:37:12.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.14:37:12.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.14:37:12.36#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:12.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:37:12.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:37:12.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:37:12.48#ibcon#enter wrdev, iclass 10, count 0 2006.285.14:37:12.48#ibcon#first serial, iclass 10, count 0 2006.285.14:37:12.48#ibcon#enter sib2, iclass 10, count 0 2006.285.14:37:12.48#ibcon#flushed, iclass 10, count 0 2006.285.14:37:12.48#ibcon#about to write, iclass 10, count 0 2006.285.14:37:12.48#ibcon#wrote, iclass 10, count 0 2006.285.14:37:12.48#ibcon#about to read 3, iclass 10, count 0 2006.285.14:37:12.50#ibcon#read 3, iclass 10, count 0 2006.285.14:37:12.50#ibcon#about to read 4, iclass 10, count 0 2006.285.14:37:12.50#ibcon#read 4, iclass 10, count 0 2006.285.14:37:12.50#ibcon#about to read 5, iclass 10, count 0 2006.285.14:37:12.50#ibcon#read 5, iclass 10, count 0 2006.285.14:37:12.50#ibcon#about to read 6, iclass 10, count 0 2006.285.14:37:12.50#ibcon#read 6, iclass 10, count 0 2006.285.14:37:12.50#ibcon#end of sib2, iclass 10, count 0 2006.285.14:37:12.50#ibcon#*mode == 0, iclass 10, count 0 2006.285.14:37:12.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.14:37:12.50#ibcon#[25=USB\r\n] 2006.285.14:37:12.50#ibcon#*before write, iclass 10, count 0 2006.285.14:37:12.50#ibcon#enter sib2, iclass 10, count 0 2006.285.14:37:12.50#ibcon#flushed, iclass 10, count 0 2006.285.14:37:12.50#ibcon#about to write, iclass 10, count 0 2006.285.14:37:12.50#ibcon#wrote, iclass 10, count 0 2006.285.14:37:12.50#ibcon#about to read 3, iclass 10, count 0 2006.285.14:37:12.53#ibcon#read 3, iclass 10, count 0 2006.285.14:37:12.53#ibcon#about to read 4, iclass 10, count 0 2006.285.14:37:12.53#ibcon#read 4, iclass 10, count 0 2006.285.14:37:12.53#ibcon#about to read 5, iclass 10, count 0 2006.285.14:37:12.53#ibcon#read 5, iclass 10, count 0 2006.285.14:37:12.53#ibcon#about to read 6, iclass 10, count 0 2006.285.14:37:12.53#ibcon#read 6, iclass 10, count 0 2006.285.14:37:12.53#ibcon#end of sib2, iclass 10, count 0 2006.285.14:37:12.53#ibcon#*after write, iclass 10, count 0 2006.285.14:37:12.53#ibcon#*before return 0, iclass 10, count 0 2006.285.14:37:12.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:37:12.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.14:37:12.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.14:37:12.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.14:37:12.53$vck44/valo=6,814.99 2006.285.14:37:12.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.14:37:12.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.14:37:12.53#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:12.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:37:12.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:37:12.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:37:12.53#ibcon#enter wrdev, iclass 12, count 0 2006.285.14:37:12.53#ibcon#first serial, iclass 12, count 0 2006.285.14:37:12.53#ibcon#enter sib2, iclass 12, count 0 2006.285.14:37:12.53#ibcon#flushed, iclass 12, count 0 2006.285.14:37:12.53#ibcon#about to write, iclass 12, count 0 2006.285.14:37:12.53#ibcon#wrote, iclass 12, count 0 2006.285.14:37:12.53#ibcon#about to read 3, iclass 12, count 0 2006.285.14:37:12.55#ibcon#read 3, iclass 12, count 0 2006.285.14:37:12.55#ibcon#about to read 4, iclass 12, count 0 2006.285.14:37:12.55#ibcon#read 4, iclass 12, count 0 2006.285.14:37:12.55#ibcon#about to read 5, iclass 12, count 0 2006.285.14:37:12.55#ibcon#read 5, iclass 12, count 0 2006.285.14:37:12.55#ibcon#about to read 6, iclass 12, count 0 2006.285.14:37:12.55#ibcon#read 6, iclass 12, count 0 2006.285.14:37:12.55#ibcon#end of sib2, iclass 12, count 0 2006.285.14:37:12.55#ibcon#*mode == 0, iclass 12, count 0 2006.285.14:37:12.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.14:37:12.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.14:37:12.55#ibcon#*before write, iclass 12, count 0 2006.285.14:37:12.55#ibcon#enter sib2, iclass 12, count 0 2006.285.14:37:12.55#ibcon#flushed, iclass 12, count 0 2006.285.14:37:12.55#ibcon#about to write, iclass 12, count 0 2006.285.14:37:12.55#ibcon#wrote, iclass 12, count 0 2006.285.14:37:12.55#ibcon#about to read 3, iclass 12, count 0 2006.285.14:37:12.59#ibcon#read 3, iclass 12, count 0 2006.285.14:37:12.59#ibcon#about to read 4, iclass 12, count 0 2006.285.14:37:12.59#ibcon#read 4, iclass 12, count 0 2006.285.14:37:12.59#ibcon#about to read 5, iclass 12, count 0 2006.285.14:37:12.59#ibcon#read 5, iclass 12, count 0 2006.285.14:37:12.59#ibcon#about to read 6, iclass 12, count 0 2006.285.14:37:12.59#ibcon#read 6, iclass 12, count 0 2006.285.14:37:12.59#ibcon#end of sib2, iclass 12, count 0 2006.285.14:37:12.59#ibcon#*after write, iclass 12, count 0 2006.285.14:37:12.59#ibcon#*before return 0, iclass 12, count 0 2006.285.14:37:12.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:37:12.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:37:12.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.14:37:12.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.14:37:12.59$vck44/va=6,4 2006.285.14:37:12.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.14:37:12.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.14:37:12.59#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:12.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:37:12.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:37:12.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:37:12.65#ibcon#enter wrdev, iclass 14, count 2 2006.285.14:37:12.65#ibcon#first serial, iclass 14, count 2 2006.285.14:37:12.65#ibcon#enter sib2, iclass 14, count 2 2006.285.14:37:12.65#ibcon#flushed, iclass 14, count 2 2006.285.14:37:12.65#ibcon#about to write, iclass 14, count 2 2006.285.14:37:12.65#ibcon#wrote, iclass 14, count 2 2006.285.14:37:12.65#ibcon#about to read 3, iclass 14, count 2 2006.285.14:37:12.67#ibcon#read 3, iclass 14, count 2 2006.285.14:37:12.67#ibcon#about to read 4, iclass 14, count 2 2006.285.14:37:12.67#ibcon#read 4, iclass 14, count 2 2006.285.14:37:12.67#ibcon#about to read 5, iclass 14, count 2 2006.285.14:37:12.67#ibcon#read 5, iclass 14, count 2 2006.285.14:37:12.67#ibcon#about to read 6, iclass 14, count 2 2006.285.14:37:12.67#ibcon#read 6, iclass 14, count 2 2006.285.14:37:12.67#ibcon#end of sib2, iclass 14, count 2 2006.285.14:37:12.67#ibcon#*mode == 0, iclass 14, count 2 2006.285.14:37:12.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.14:37:12.67#ibcon#[25=AT06-04\r\n] 2006.285.14:37:12.67#ibcon#*before write, iclass 14, count 2 2006.285.14:37:12.67#ibcon#enter sib2, iclass 14, count 2 2006.285.14:37:12.67#ibcon#flushed, iclass 14, count 2 2006.285.14:37:12.67#ibcon#about to write, iclass 14, count 2 2006.285.14:37:12.67#ibcon#wrote, iclass 14, count 2 2006.285.14:37:12.67#ibcon#about to read 3, iclass 14, count 2 2006.285.14:37:12.70#ibcon#read 3, iclass 14, count 2 2006.285.14:37:12.70#ibcon#about to read 4, iclass 14, count 2 2006.285.14:37:12.70#ibcon#read 4, iclass 14, count 2 2006.285.14:37:12.70#ibcon#about to read 5, iclass 14, count 2 2006.285.14:37:12.70#ibcon#read 5, iclass 14, count 2 2006.285.14:37:12.70#ibcon#about to read 6, iclass 14, count 2 2006.285.14:37:12.70#ibcon#read 6, iclass 14, count 2 2006.285.14:37:12.70#ibcon#end of sib2, iclass 14, count 2 2006.285.14:37:12.70#ibcon#*after write, iclass 14, count 2 2006.285.14:37:12.70#ibcon#*before return 0, iclass 14, count 2 2006.285.14:37:12.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:37:12.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:37:12.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.14:37:12.70#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:12.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:37:12.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:37:12.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:37:12.82#ibcon#enter wrdev, iclass 14, count 0 2006.285.14:37:12.82#ibcon#first serial, iclass 14, count 0 2006.285.14:37:12.82#ibcon#enter sib2, iclass 14, count 0 2006.285.14:37:12.82#ibcon#flushed, iclass 14, count 0 2006.285.14:37:12.82#ibcon#about to write, iclass 14, count 0 2006.285.14:37:12.82#ibcon#wrote, iclass 14, count 0 2006.285.14:37:12.82#ibcon#about to read 3, iclass 14, count 0 2006.285.14:37:12.84#ibcon#read 3, iclass 14, count 0 2006.285.14:37:12.84#ibcon#about to read 4, iclass 14, count 0 2006.285.14:37:12.84#ibcon#read 4, iclass 14, count 0 2006.285.14:37:12.84#ibcon#about to read 5, iclass 14, count 0 2006.285.14:37:12.84#ibcon#read 5, iclass 14, count 0 2006.285.14:37:12.84#ibcon#about to read 6, iclass 14, count 0 2006.285.14:37:12.84#ibcon#read 6, iclass 14, count 0 2006.285.14:37:12.84#ibcon#end of sib2, iclass 14, count 0 2006.285.14:37:12.84#ibcon#*mode == 0, iclass 14, count 0 2006.285.14:37:12.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.14:37:12.84#ibcon#[25=USB\r\n] 2006.285.14:37:12.84#ibcon#*before write, iclass 14, count 0 2006.285.14:37:12.84#ibcon#enter sib2, iclass 14, count 0 2006.285.14:37:12.84#ibcon#flushed, iclass 14, count 0 2006.285.14:37:12.84#ibcon#about to write, iclass 14, count 0 2006.285.14:37:12.84#ibcon#wrote, iclass 14, count 0 2006.285.14:37:12.84#ibcon#about to read 3, iclass 14, count 0 2006.285.14:37:12.87#ibcon#read 3, iclass 14, count 0 2006.285.14:37:12.87#ibcon#about to read 4, iclass 14, count 0 2006.285.14:37:12.87#ibcon#read 4, iclass 14, count 0 2006.285.14:37:12.87#ibcon#about to read 5, iclass 14, count 0 2006.285.14:37:12.87#ibcon#read 5, iclass 14, count 0 2006.285.14:37:12.87#ibcon#about to read 6, iclass 14, count 0 2006.285.14:37:12.87#ibcon#read 6, iclass 14, count 0 2006.285.14:37:12.87#ibcon#end of sib2, iclass 14, count 0 2006.285.14:37:12.87#ibcon#*after write, iclass 14, count 0 2006.285.14:37:12.87#ibcon#*before return 0, iclass 14, count 0 2006.285.14:37:12.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:37:12.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:37:12.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.14:37:12.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.14:37:12.87$vck44/valo=7,864.99 2006.285.14:37:12.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.14:37:12.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.14:37:12.87#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:12.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:37:12.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:37:12.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:37:12.87#ibcon#enter wrdev, iclass 16, count 0 2006.285.14:37:12.87#ibcon#first serial, iclass 16, count 0 2006.285.14:37:12.87#ibcon#enter sib2, iclass 16, count 0 2006.285.14:37:12.87#ibcon#flushed, iclass 16, count 0 2006.285.14:37:12.87#ibcon#about to write, iclass 16, count 0 2006.285.14:37:12.87#ibcon#wrote, iclass 16, count 0 2006.285.14:37:12.87#ibcon#about to read 3, iclass 16, count 0 2006.285.14:37:12.89#ibcon#read 3, iclass 16, count 0 2006.285.14:37:12.89#ibcon#about to read 4, iclass 16, count 0 2006.285.14:37:12.89#ibcon#read 4, iclass 16, count 0 2006.285.14:37:12.89#ibcon#about to read 5, iclass 16, count 0 2006.285.14:37:12.89#ibcon#read 5, iclass 16, count 0 2006.285.14:37:12.89#ibcon#about to read 6, iclass 16, count 0 2006.285.14:37:12.89#ibcon#read 6, iclass 16, count 0 2006.285.14:37:12.89#ibcon#end of sib2, iclass 16, count 0 2006.285.14:37:12.89#ibcon#*mode == 0, iclass 16, count 0 2006.285.14:37:12.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.14:37:12.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.14:37:12.89#ibcon#*before write, iclass 16, count 0 2006.285.14:37:12.89#ibcon#enter sib2, iclass 16, count 0 2006.285.14:37:12.89#ibcon#flushed, iclass 16, count 0 2006.285.14:37:12.89#ibcon#about to write, iclass 16, count 0 2006.285.14:37:12.89#ibcon#wrote, iclass 16, count 0 2006.285.14:37:12.89#ibcon#about to read 3, iclass 16, count 0 2006.285.14:37:12.93#ibcon#read 3, iclass 16, count 0 2006.285.14:37:12.93#ibcon#about to read 4, iclass 16, count 0 2006.285.14:37:12.93#ibcon#read 4, iclass 16, count 0 2006.285.14:37:12.93#ibcon#about to read 5, iclass 16, count 0 2006.285.14:37:12.93#ibcon#read 5, iclass 16, count 0 2006.285.14:37:12.93#ibcon#about to read 6, iclass 16, count 0 2006.285.14:37:12.93#ibcon#read 6, iclass 16, count 0 2006.285.14:37:12.93#ibcon#end of sib2, iclass 16, count 0 2006.285.14:37:12.93#ibcon#*after write, iclass 16, count 0 2006.285.14:37:12.93#ibcon#*before return 0, iclass 16, count 0 2006.285.14:37:12.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:37:12.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:37:12.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.14:37:12.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.14:37:12.93$vck44/va=7,4 2006.285.14:37:12.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.14:37:12.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.14:37:12.93#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:12.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:37:12.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:37:12.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:37:12.99#ibcon#enter wrdev, iclass 18, count 2 2006.285.14:37:12.99#ibcon#first serial, iclass 18, count 2 2006.285.14:37:12.99#ibcon#enter sib2, iclass 18, count 2 2006.285.14:37:12.99#ibcon#flushed, iclass 18, count 2 2006.285.14:37:12.99#ibcon#about to write, iclass 18, count 2 2006.285.14:37:12.99#ibcon#wrote, iclass 18, count 2 2006.285.14:37:12.99#ibcon#about to read 3, iclass 18, count 2 2006.285.14:37:13.01#ibcon#read 3, iclass 18, count 2 2006.285.14:37:13.01#ibcon#about to read 4, iclass 18, count 2 2006.285.14:37:13.01#ibcon#read 4, iclass 18, count 2 2006.285.14:37:13.01#ibcon#about to read 5, iclass 18, count 2 2006.285.14:37:13.01#ibcon#read 5, iclass 18, count 2 2006.285.14:37:13.01#ibcon#about to read 6, iclass 18, count 2 2006.285.14:37:13.01#ibcon#read 6, iclass 18, count 2 2006.285.14:37:13.01#ibcon#end of sib2, iclass 18, count 2 2006.285.14:37:13.01#ibcon#*mode == 0, iclass 18, count 2 2006.285.14:37:13.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.14:37:13.01#ibcon#[25=AT07-04\r\n] 2006.285.14:37:13.01#ibcon#*before write, iclass 18, count 2 2006.285.14:37:13.01#ibcon#enter sib2, iclass 18, count 2 2006.285.14:37:13.01#ibcon#flushed, iclass 18, count 2 2006.285.14:37:13.01#ibcon#about to write, iclass 18, count 2 2006.285.14:37:13.01#ibcon#wrote, iclass 18, count 2 2006.285.14:37:13.01#ibcon#about to read 3, iclass 18, count 2 2006.285.14:37:13.04#ibcon#read 3, iclass 18, count 2 2006.285.14:37:13.04#ibcon#about to read 4, iclass 18, count 2 2006.285.14:37:13.04#ibcon#read 4, iclass 18, count 2 2006.285.14:37:13.04#ibcon#about to read 5, iclass 18, count 2 2006.285.14:37:13.04#ibcon#read 5, iclass 18, count 2 2006.285.14:37:13.04#ibcon#about to read 6, iclass 18, count 2 2006.285.14:37:13.04#ibcon#read 6, iclass 18, count 2 2006.285.14:37:13.04#ibcon#end of sib2, iclass 18, count 2 2006.285.14:37:13.04#ibcon#*after write, iclass 18, count 2 2006.285.14:37:13.04#ibcon#*before return 0, iclass 18, count 2 2006.285.14:37:13.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:37:13.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:37:13.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.14:37:13.04#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:13.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:37:13.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:37:13.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:37:13.16#ibcon#enter wrdev, iclass 18, count 0 2006.285.14:37:13.16#ibcon#first serial, iclass 18, count 0 2006.285.14:37:13.16#ibcon#enter sib2, iclass 18, count 0 2006.285.14:37:13.16#ibcon#flushed, iclass 18, count 0 2006.285.14:37:13.16#ibcon#about to write, iclass 18, count 0 2006.285.14:37:13.16#ibcon#wrote, iclass 18, count 0 2006.285.14:37:13.16#ibcon#about to read 3, iclass 18, count 0 2006.285.14:37:13.18#ibcon#read 3, iclass 18, count 0 2006.285.14:37:13.18#ibcon#about to read 4, iclass 18, count 0 2006.285.14:37:13.18#ibcon#read 4, iclass 18, count 0 2006.285.14:37:13.18#ibcon#about to read 5, iclass 18, count 0 2006.285.14:37:13.18#ibcon#read 5, iclass 18, count 0 2006.285.14:37:13.18#ibcon#about to read 6, iclass 18, count 0 2006.285.14:37:13.18#ibcon#read 6, iclass 18, count 0 2006.285.14:37:13.18#ibcon#end of sib2, iclass 18, count 0 2006.285.14:37:13.18#ibcon#*mode == 0, iclass 18, count 0 2006.285.14:37:13.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.14:37:13.18#ibcon#[25=USB\r\n] 2006.285.14:37:13.18#ibcon#*before write, iclass 18, count 0 2006.285.14:37:13.18#ibcon#enter sib2, iclass 18, count 0 2006.285.14:37:13.18#ibcon#flushed, iclass 18, count 0 2006.285.14:37:13.18#ibcon#about to write, iclass 18, count 0 2006.285.14:37:13.18#ibcon#wrote, iclass 18, count 0 2006.285.14:37:13.18#ibcon#about to read 3, iclass 18, count 0 2006.285.14:37:13.21#ibcon#read 3, iclass 18, count 0 2006.285.14:37:13.21#ibcon#about to read 4, iclass 18, count 0 2006.285.14:37:13.21#ibcon#read 4, iclass 18, count 0 2006.285.14:37:13.21#ibcon#about to read 5, iclass 18, count 0 2006.285.14:37:13.21#ibcon#read 5, iclass 18, count 0 2006.285.14:37:13.21#ibcon#about to read 6, iclass 18, count 0 2006.285.14:37:13.21#ibcon#read 6, iclass 18, count 0 2006.285.14:37:13.21#ibcon#end of sib2, iclass 18, count 0 2006.285.14:37:13.21#ibcon#*after write, iclass 18, count 0 2006.285.14:37:13.21#ibcon#*before return 0, iclass 18, count 0 2006.285.14:37:13.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:37:13.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:37:13.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.14:37:13.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.14:37:13.21$vck44/valo=8,884.99 2006.285.14:37:13.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.14:37:13.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.14:37:13.21#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:13.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:37:13.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:37:13.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:37:13.21#ibcon#enter wrdev, iclass 20, count 0 2006.285.14:37:13.21#ibcon#first serial, iclass 20, count 0 2006.285.14:37:13.21#ibcon#enter sib2, iclass 20, count 0 2006.285.14:37:13.21#ibcon#flushed, iclass 20, count 0 2006.285.14:37:13.21#ibcon#about to write, iclass 20, count 0 2006.285.14:37:13.21#ibcon#wrote, iclass 20, count 0 2006.285.14:37:13.21#ibcon#about to read 3, iclass 20, count 0 2006.285.14:37:13.23#ibcon#read 3, iclass 20, count 0 2006.285.14:37:13.23#ibcon#about to read 4, iclass 20, count 0 2006.285.14:37:13.23#ibcon#read 4, iclass 20, count 0 2006.285.14:37:13.23#ibcon#about to read 5, iclass 20, count 0 2006.285.14:37:13.23#ibcon#read 5, iclass 20, count 0 2006.285.14:37:13.23#ibcon#about to read 6, iclass 20, count 0 2006.285.14:37:13.23#ibcon#read 6, iclass 20, count 0 2006.285.14:37:13.23#ibcon#end of sib2, iclass 20, count 0 2006.285.14:37:13.23#ibcon#*mode == 0, iclass 20, count 0 2006.285.14:37:13.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.14:37:13.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.14:37:13.23#ibcon#*before write, iclass 20, count 0 2006.285.14:37:13.23#ibcon#enter sib2, iclass 20, count 0 2006.285.14:37:13.23#ibcon#flushed, iclass 20, count 0 2006.285.14:37:13.23#ibcon#about to write, iclass 20, count 0 2006.285.14:37:13.23#ibcon#wrote, iclass 20, count 0 2006.285.14:37:13.23#ibcon#about to read 3, iclass 20, count 0 2006.285.14:37:13.27#ibcon#read 3, iclass 20, count 0 2006.285.14:37:13.27#ibcon#about to read 4, iclass 20, count 0 2006.285.14:37:13.27#ibcon#read 4, iclass 20, count 0 2006.285.14:37:13.27#ibcon#about to read 5, iclass 20, count 0 2006.285.14:37:13.27#ibcon#read 5, iclass 20, count 0 2006.285.14:37:13.27#ibcon#about to read 6, iclass 20, count 0 2006.285.14:37:13.27#ibcon#read 6, iclass 20, count 0 2006.285.14:37:13.27#ibcon#end of sib2, iclass 20, count 0 2006.285.14:37:13.27#ibcon#*after write, iclass 20, count 0 2006.285.14:37:13.27#ibcon#*before return 0, iclass 20, count 0 2006.285.14:37:13.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:37:13.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:37:13.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.14:37:13.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.14:37:13.27$vck44/va=8,3 2006.285.14:37:13.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.14:37:13.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.14:37:13.27#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:13.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:37:13.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:37:13.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:37:13.33#ibcon#enter wrdev, iclass 22, count 2 2006.285.14:37:13.33#ibcon#first serial, iclass 22, count 2 2006.285.14:37:13.33#ibcon#enter sib2, iclass 22, count 2 2006.285.14:37:13.33#ibcon#flushed, iclass 22, count 2 2006.285.14:37:13.33#ibcon#about to write, iclass 22, count 2 2006.285.14:37:13.33#ibcon#wrote, iclass 22, count 2 2006.285.14:37:13.33#ibcon#about to read 3, iclass 22, count 2 2006.285.14:37:13.35#ibcon#read 3, iclass 22, count 2 2006.285.14:37:13.35#ibcon#about to read 4, iclass 22, count 2 2006.285.14:37:13.35#ibcon#read 4, iclass 22, count 2 2006.285.14:37:13.35#ibcon#about to read 5, iclass 22, count 2 2006.285.14:37:13.35#ibcon#read 5, iclass 22, count 2 2006.285.14:37:13.35#ibcon#about to read 6, iclass 22, count 2 2006.285.14:37:13.35#ibcon#read 6, iclass 22, count 2 2006.285.14:37:13.35#ibcon#end of sib2, iclass 22, count 2 2006.285.14:37:13.35#ibcon#*mode == 0, iclass 22, count 2 2006.285.14:37:13.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.14:37:13.35#ibcon#[25=AT08-03\r\n] 2006.285.14:37:13.35#ibcon#*before write, iclass 22, count 2 2006.285.14:37:13.35#ibcon#enter sib2, iclass 22, count 2 2006.285.14:37:13.35#ibcon#flushed, iclass 22, count 2 2006.285.14:37:13.35#ibcon#about to write, iclass 22, count 2 2006.285.14:37:13.35#ibcon#wrote, iclass 22, count 2 2006.285.14:37:13.35#ibcon#about to read 3, iclass 22, count 2 2006.285.14:37:13.38#ibcon#read 3, iclass 22, count 2 2006.285.14:37:13.38#ibcon#about to read 4, iclass 22, count 2 2006.285.14:37:13.38#ibcon#read 4, iclass 22, count 2 2006.285.14:37:13.38#ibcon#about to read 5, iclass 22, count 2 2006.285.14:37:13.38#ibcon#read 5, iclass 22, count 2 2006.285.14:37:13.38#ibcon#about to read 6, iclass 22, count 2 2006.285.14:37:13.38#ibcon#read 6, iclass 22, count 2 2006.285.14:37:13.38#ibcon#end of sib2, iclass 22, count 2 2006.285.14:37:13.38#ibcon#*after write, iclass 22, count 2 2006.285.14:37:13.38#ibcon#*before return 0, iclass 22, count 2 2006.285.14:37:13.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:37:13.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:37:13.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.14:37:13.38#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:13.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:37:13.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:37:13.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:37:13.50#ibcon#enter wrdev, iclass 22, count 0 2006.285.14:37:13.50#ibcon#first serial, iclass 22, count 0 2006.285.14:37:13.50#ibcon#enter sib2, iclass 22, count 0 2006.285.14:37:13.50#ibcon#flushed, iclass 22, count 0 2006.285.14:37:13.50#ibcon#about to write, iclass 22, count 0 2006.285.14:37:13.50#ibcon#wrote, iclass 22, count 0 2006.285.14:37:13.50#ibcon#about to read 3, iclass 22, count 0 2006.285.14:37:13.52#ibcon#read 3, iclass 22, count 0 2006.285.14:37:13.52#ibcon#about to read 4, iclass 22, count 0 2006.285.14:37:13.52#ibcon#read 4, iclass 22, count 0 2006.285.14:37:13.52#ibcon#about to read 5, iclass 22, count 0 2006.285.14:37:13.52#ibcon#read 5, iclass 22, count 0 2006.285.14:37:13.52#ibcon#about to read 6, iclass 22, count 0 2006.285.14:37:13.52#ibcon#read 6, iclass 22, count 0 2006.285.14:37:13.52#ibcon#end of sib2, iclass 22, count 0 2006.285.14:37:13.52#ibcon#*mode == 0, iclass 22, count 0 2006.285.14:37:13.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.14:37:13.52#ibcon#[25=USB\r\n] 2006.285.14:37:13.52#ibcon#*before write, iclass 22, count 0 2006.285.14:37:13.52#ibcon#enter sib2, iclass 22, count 0 2006.285.14:37:13.52#ibcon#flushed, iclass 22, count 0 2006.285.14:37:13.52#ibcon#about to write, iclass 22, count 0 2006.285.14:37:13.52#ibcon#wrote, iclass 22, count 0 2006.285.14:37:13.52#ibcon#about to read 3, iclass 22, count 0 2006.285.14:37:13.55#ibcon#read 3, iclass 22, count 0 2006.285.14:37:13.55#ibcon#about to read 4, iclass 22, count 0 2006.285.14:37:13.55#ibcon#read 4, iclass 22, count 0 2006.285.14:37:13.55#ibcon#about to read 5, iclass 22, count 0 2006.285.14:37:13.55#ibcon#read 5, iclass 22, count 0 2006.285.14:37:13.55#ibcon#about to read 6, iclass 22, count 0 2006.285.14:37:13.55#ibcon#read 6, iclass 22, count 0 2006.285.14:37:13.55#ibcon#end of sib2, iclass 22, count 0 2006.285.14:37:13.55#ibcon#*after write, iclass 22, count 0 2006.285.14:37:13.55#ibcon#*before return 0, iclass 22, count 0 2006.285.14:37:13.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:37:13.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:37:13.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.14:37:13.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.14:37:13.55$vck44/vblo=1,629.99 2006.285.14:37:13.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.14:37:13.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.14:37:13.55#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:13.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:37:13.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:37:13.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:37:13.55#ibcon#enter wrdev, iclass 24, count 0 2006.285.14:37:13.55#ibcon#first serial, iclass 24, count 0 2006.285.14:37:13.55#ibcon#enter sib2, iclass 24, count 0 2006.285.14:37:13.55#ibcon#flushed, iclass 24, count 0 2006.285.14:37:13.55#ibcon#about to write, iclass 24, count 0 2006.285.14:37:13.55#ibcon#wrote, iclass 24, count 0 2006.285.14:37:13.55#ibcon#about to read 3, iclass 24, count 0 2006.285.14:37:13.57#ibcon#read 3, iclass 24, count 0 2006.285.14:37:13.57#ibcon#about to read 4, iclass 24, count 0 2006.285.14:37:13.57#ibcon#read 4, iclass 24, count 0 2006.285.14:37:13.57#ibcon#about to read 5, iclass 24, count 0 2006.285.14:37:13.57#ibcon#read 5, iclass 24, count 0 2006.285.14:37:13.57#ibcon#about to read 6, iclass 24, count 0 2006.285.14:37:13.57#ibcon#read 6, iclass 24, count 0 2006.285.14:37:13.57#ibcon#end of sib2, iclass 24, count 0 2006.285.14:37:13.57#ibcon#*mode == 0, iclass 24, count 0 2006.285.14:37:13.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.14:37:13.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.14:37:13.57#ibcon#*before write, iclass 24, count 0 2006.285.14:37:13.57#ibcon#enter sib2, iclass 24, count 0 2006.285.14:37:13.57#ibcon#flushed, iclass 24, count 0 2006.285.14:37:13.57#ibcon#about to write, iclass 24, count 0 2006.285.14:37:13.57#ibcon#wrote, iclass 24, count 0 2006.285.14:37:13.57#ibcon#about to read 3, iclass 24, count 0 2006.285.14:37:13.61#ibcon#read 3, iclass 24, count 0 2006.285.14:37:13.61#ibcon#about to read 4, iclass 24, count 0 2006.285.14:37:13.61#ibcon#read 4, iclass 24, count 0 2006.285.14:37:13.61#ibcon#about to read 5, iclass 24, count 0 2006.285.14:37:13.61#ibcon#read 5, iclass 24, count 0 2006.285.14:37:13.61#ibcon#about to read 6, iclass 24, count 0 2006.285.14:37:13.61#ibcon#read 6, iclass 24, count 0 2006.285.14:37:13.61#ibcon#end of sib2, iclass 24, count 0 2006.285.14:37:13.61#ibcon#*after write, iclass 24, count 0 2006.285.14:37:13.61#ibcon#*before return 0, iclass 24, count 0 2006.285.14:37:13.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:37:13.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:37:13.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.14:37:13.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.14:37:13.61$vck44/vb=1,4 2006.285.14:37:13.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.14:37:13.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.14:37:13.61#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:13.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:37:13.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:37:13.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:37:13.61#ibcon#enter wrdev, iclass 26, count 2 2006.285.14:37:13.61#ibcon#first serial, iclass 26, count 2 2006.285.14:37:13.61#ibcon#enter sib2, iclass 26, count 2 2006.285.14:37:13.61#ibcon#flushed, iclass 26, count 2 2006.285.14:37:13.61#ibcon#about to write, iclass 26, count 2 2006.285.14:37:13.61#ibcon#wrote, iclass 26, count 2 2006.285.14:37:13.61#ibcon#about to read 3, iclass 26, count 2 2006.285.14:37:13.63#ibcon#read 3, iclass 26, count 2 2006.285.14:37:13.63#ibcon#about to read 4, iclass 26, count 2 2006.285.14:37:13.63#ibcon#read 4, iclass 26, count 2 2006.285.14:37:13.63#ibcon#about to read 5, iclass 26, count 2 2006.285.14:37:13.63#ibcon#read 5, iclass 26, count 2 2006.285.14:37:13.63#ibcon#about to read 6, iclass 26, count 2 2006.285.14:37:13.63#ibcon#read 6, iclass 26, count 2 2006.285.14:37:13.63#ibcon#end of sib2, iclass 26, count 2 2006.285.14:37:13.63#ibcon#*mode == 0, iclass 26, count 2 2006.285.14:37:13.63#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.14:37:13.63#ibcon#[27=AT01-04\r\n] 2006.285.14:37:13.63#ibcon#*before write, iclass 26, count 2 2006.285.14:37:13.63#ibcon#enter sib2, iclass 26, count 2 2006.285.14:37:13.63#ibcon#flushed, iclass 26, count 2 2006.285.14:37:13.63#ibcon#about to write, iclass 26, count 2 2006.285.14:37:13.63#ibcon#wrote, iclass 26, count 2 2006.285.14:37:13.63#ibcon#about to read 3, iclass 26, count 2 2006.285.14:37:13.66#ibcon#read 3, iclass 26, count 2 2006.285.14:37:13.66#ibcon#about to read 4, iclass 26, count 2 2006.285.14:37:13.66#ibcon#read 4, iclass 26, count 2 2006.285.14:37:13.66#ibcon#about to read 5, iclass 26, count 2 2006.285.14:37:13.66#ibcon#read 5, iclass 26, count 2 2006.285.14:37:13.66#ibcon#about to read 6, iclass 26, count 2 2006.285.14:37:13.66#ibcon#read 6, iclass 26, count 2 2006.285.14:37:13.66#ibcon#end of sib2, iclass 26, count 2 2006.285.14:37:13.66#ibcon#*after write, iclass 26, count 2 2006.285.14:37:13.66#ibcon#*before return 0, iclass 26, count 2 2006.285.14:37:13.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:37:13.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:37:13.66#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.14:37:13.66#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:13.66#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:37:13.78#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:37:13.78#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:37:13.78#ibcon#enter wrdev, iclass 26, count 0 2006.285.14:37:13.78#ibcon#first serial, iclass 26, count 0 2006.285.14:37:13.78#ibcon#enter sib2, iclass 26, count 0 2006.285.14:37:13.78#ibcon#flushed, iclass 26, count 0 2006.285.14:37:13.78#ibcon#about to write, iclass 26, count 0 2006.285.14:37:13.78#ibcon#wrote, iclass 26, count 0 2006.285.14:37:13.78#ibcon#about to read 3, iclass 26, count 0 2006.285.14:37:13.80#ibcon#read 3, iclass 26, count 0 2006.285.14:37:13.80#ibcon#about to read 4, iclass 26, count 0 2006.285.14:37:13.80#ibcon#read 4, iclass 26, count 0 2006.285.14:37:13.80#ibcon#about to read 5, iclass 26, count 0 2006.285.14:37:13.80#ibcon#read 5, iclass 26, count 0 2006.285.14:37:13.80#ibcon#about to read 6, iclass 26, count 0 2006.285.14:37:13.80#ibcon#read 6, iclass 26, count 0 2006.285.14:37:13.80#ibcon#end of sib2, iclass 26, count 0 2006.285.14:37:13.80#ibcon#*mode == 0, iclass 26, count 0 2006.285.14:37:13.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.14:37:13.80#ibcon#[27=USB\r\n] 2006.285.14:37:13.80#ibcon#*before write, iclass 26, count 0 2006.285.14:37:13.80#ibcon#enter sib2, iclass 26, count 0 2006.285.14:37:13.80#ibcon#flushed, iclass 26, count 0 2006.285.14:37:13.80#ibcon#about to write, iclass 26, count 0 2006.285.14:37:13.80#ibcon#wrote, iclass 26, count 0 2006.285.14:37:13.80#ibcon#about to read 3, iclass 26, count 0 2006.285.14:37:13.83#ibcon#read 3, iclass 26, count 0 2006.285.14:37:13.83#ibcon#about to read 4, iclass 26, count 0 2006.285.14:37:13.83#ibcon#read 4, iclass 26, count 0 2006.285.14:37:13.83#ibcon#about to read 5, iclass 26, count 0 2006.285.14:37:13.83#ibcon#read 5, iclass 26, count 0 2006.285.14:37:13.83#ibcon#about to read 6, iclass 26, count 0 2006.285.14:37:13.83#ibcon#read 6, iclass 26, count 0 2006.285.14:37:13.83#ibcon#end of sib2, iclass 26, count 0 2006.285.14:37:13.83#ibcon#*after write, iclass 26, count 0 2006.285.14:37:13.83#ibcon#*before return 0, iclass 26, count 0 2006.285.14:37:13.83#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:37:13.83#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:37:13.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.14:37:13.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.14:37:13.83$vck44/vblo=2,634.99 2006.285.14:37:13.83#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.14:37:13.83#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.14:37:13.83#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:13.83#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:37:13.83#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:37:13.83#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:37:13.83#ibcon#enter wrdev, iclass 28, count 0 2006.285.14:37:13.83#ibcon#first serial, iclass 28, count 0 2006.285.14:37:13.83#ibcon#enter sib2, iclass 28, count 0 2006.285.14:37:13.83#ibcon#flushed, iclass 28, count 0 2006.285.14:37:13.83#ibcon#about to write, iclass 28, count 0 2006.285.14:37:13.83#ibcon#wrote, iclass 28, count 0 2006.285.14:37:13.83#ibcon#about to read 3, iclass 28, count 0 2006.285.14:37:13.85#ibcon#read 3, iclass 28, count 0 2006.285.14:37:13.85#ibcon#about to read 4, iclass 28, count 0 2006.285.14:37:13.85#ibcon#read 4, iclass 28, count 0 2006.285.14:37:13.85#ibcon#about to read 5, iclass 28, count 0 2006.285.14:37:13.85#ibcon#read 5, iclass 28, count 0 2006.285.14:37:13.85#ibcon#about to read 6, iclass 28, count 0 2006.285.14:37:13.85#ibcon#read 6, iclass 28, count 0 2006.285.14:37:13.85#ibcon#end of sib2, iclass 28, count 0 2006.285.14:37:13.85#ibcon#*mode == 0, iclass 28, count 0 2006.285.14:37:13.85#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.14:37:13.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.14:37:13.85#ibcon#*before write, iclass 28, count 0 2006.285.14:37:13.85#ibcon#enter sib2, iclass 28, count 0 2006.285.14:37:13.85#ibcon#flushed, iclass 28, count 0 2006.285.14:37:13.85#ibcon#about to write, iclass 28, count 0 2006.285.14:37:13.85#ibcon#wrote, iclass 28, count 0 2006.285.14:37:13.85#ibcon#about to read 3, iclass 28, count 0 2006.285.14:37:13.89#ibcon#read 3, iclass 28, count 0 2006.285.14:37:13.89#ibcon#about to read 4, iclass 28, count 0 2006.285.14:37:13.89#ibcon#read 4, iclass 28, count 0 2006.285.14:37:13.89#ibcon#about to read 5, iclass 28, count 0 2006.285.14:37:13.89#ibcon#read 5, iclass 28, count 0 2006.285.14:37:13.89#ibcon#about to read 6, iclass 28, count 0 2006.285.14:37:13.89#ibcon#read 6, iclass 28, count 0 2006.285.14:37:13.89#ibcon#end of sib2, iclass 28, count 0 2006.285.14:37:13.89#ibcon#*after write, iclass 28, count 0 2006.285.14:37:13.89#ibcon#*before return 0, iclass 28, count 0 2006.285.14:37:13.89#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:37:13.89#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.14:37:13.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.14:37:13.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.14:37:13.89$vck44/vb=2,5 2006.285.14:37:13.89#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.14:37:13.89#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.14:37:13.89#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:13.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:37:13.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:37:13.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:37:13.95#ibcon#enter wrdev, iclass 30, count 2 2006.285.14:37:13.95#ibcon#first serial, iclass 30, count 2 2006.285.14:37:13.95#ibcon#enter sib2, iclass 30, count 2 2006.285.14:37:13.95#ibcon#flushed, iclass 30, count 2 2006.285.14:37:13.95#ibcon#about to write, iclass 30, count 2 2006.285.14:37:13.95#ibcon#wrote, iclass 30, count 2 2006.285.14:37:13.95#ibcon#about to read 3, iclass 30, count 2 2006.285.14:37:13.97#ibcon#read 3, iclass 30, count 2 2006.285.14:37:13.97#ibcon#about to read 4, iclass 30, count 2 2006.285.14:37:13.97#ibcon#read 4, iclass 30, count 2 2006.285.14:37:13.97#ibcon#about to read 5, iclass 30, count 2 2006.285.14:37:13.97#ibcon#read 5, iclass 30, count 2 2006.285.14:37:13.97#ibcon#about to read 6, iclass 30, count 2 2006.285.14:37:13.97#ibcon#read 6, iclass 30, count 2 2006.285.14:37:13.97#ibcon#end of sib2, iclass 30, count 2 2006.285.14:37:13.97#ibcon#*mode == 0, iclass 30, count 2 2006.285.14:37:13.97#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.14:37:13.97#ibcon#[27=AT02-05\r\n] 2006.285.14:37:13.97#ibcon#*before write, iclass 30, count 2 2006.285.14:37:13.97#ibcon#enter sib2, iclass 30, count 2 2006.285.14:37:13.97#ibcon#flushed, iclass 30, count 2 2006.285.14:37:13.97#ibcon#about to write, iclass 30, count 2 2006.285.14:37:13.97#ibcon#wrote, iclass 30, count 2 2006.285.14:37:13.97#ibcon#about to read 3, iclass 30, count 2 2006.285.14:37:14.00#ibcon#read 3, iclass 30, count 2 2006.285.14:37:14.00#ibcon#about to read 4, iclass 30, count 2 2006.285.14:37:14.00#ibcon#read 4, iclass 30, count 2 2006.285.14:37:14.00#ibcon#about to read 5, iclass 30, count 2 2006.285.14:37:14.00#ibcon#read 5, iclass 30, count 2 2006.285.14:37:14.00#ibcon#about to read 6, iclass 30, count 2 2006.285.14:37:14.00#ibcon#read 6, iclass 30, count 2 2006.285.14:37:14.00#ibcon#end of sib2, iclass 30, count 2 2006.285.14:37:14.00#ibcon#*after write, iclass 30, count 2 2006.285.14:37:14.00#ibcon#*before return 0, iclass 30, count 2 2006.285.14:37:14.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:37:14.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.14:37:14.00#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.14:37:14.00#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:14.00#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:37:14.12#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:37:14.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:37:14.24#ibcon#enter wrdev, iclass 30, count 0 2006.285.14:37:14.24#ibcon#first serial, iclass 30, count 0 2006.285.14:37:14.24#ibcon#enter sib2, iclass 30, count 0 2006.285.14:37:14.24#ibcon#flushed, iclass 30, count 0 2006.285.14:37:14.24#ibcon#about to write, iclass 30, count 0 2006.285.14:37:14.24#ibcon#wrote, iclass 30, count 0 2006.285.14:37:14.24#ibcon#about to read 3, iclass 30, count 0 2006.285.14:37:14.25#ibcon#read 3, iclass 30, count 0 2006.285.14:37:14.25#ibcon#about to read 4, iclass 30, count 0 2006.285.14:37:14.25#ibcon#read 4, iclass 30, count 0 2006.285.14:37:14.25#ibcon#about to read 5, iclass 30, count 0 2006.285.14:37:14.25#ibcon#read 5, iclass 30, count 0 2006.285.14:37:14.25#ibcon#about to read 6, iclass 30, count 0 2006.285.14:37:14.25#ibcon#read 6, iclass 30, count 0 2006.285.14:37:14.25#ibcon#end of sib2, iclass 30, count 0 2006.285.14:37:14.25#ibcon#*mode == 0, iclass 30, count 0 2006.285.14:37:14.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.14:37:14.25#ibcon#[27=USB\r\n] 2006.285.14:37:14.25#ibcon#*before write, iclass 30, count 0 2006.285.14:37:14.25#ibcon#enter sib2, iclass 30, count 0 2006.285.14:37:14.25#ibcon#flushed, iclass 30, count 0 2006.285.14:37:14.25#ibcon#about to write, iclass 30, count 0 2006.285.14:37:14.25#ibcon#wrote, iclass 30, count 0 2006.285.14:37:14.25#ibcon#about to read 3, iclass 30, count 0 2006.285.14:37:14.28#ibcon#read 3, iclass 30, count 0 2006.285.14:37:14.28#ibcon#about to read 4, iclass 30, count 0 2006.285.14:37:14.28#ibcon#read 4, iclass 30, count 0 2006.285.14:37:14.28#ibcon#about to read 5, iclass 30, count 0 2006.285.14:37:14.28#ibcon#read 5, iclass 30, count 0 2006.285.14:37:14.28#ibcon#about to read 6, iclass 30, count 0 2006.285.14:37:14.28#ibcon#read 6, iclass 30, count 0 2006.285.14:37:14.28#ibcon#end of sib2, iclass 30, count 0 2006.285.14:37:14.28#ibcon#*after write, iclass 30, count 0 2006.285.14:37:14.28#ibcon#*before return 0, iclass 30, count 0 2006.285.14:37:14.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:37:14.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.14:37:14.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.14:37:14.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.14:37:14.28$vck44/vblo=3,649.99 2006.285.14:37:14.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.14:37:14.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.14:37:14.28#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:14.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:37:14.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:37:14.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:37:14.28#ibcon#enter wrdev, iclass 32, count 0 2006.285.14:37:14.28#ibcon#first serial, iclass 32, count 0 2006.285.14:37:14.28#ibcon#enter sib2, iclass 32, count 0 2006.285.14:37:14.28#ibcon#flushed, iclass 32, count 0 2006.285.14:37:14.28#ibcon#about to write, iclass 32, count 0 2006.285.14:37:14.28#ibcon#wrote, iclass 32, count 0 2006.285.14:37:14.28#ibcon#about to read 3, iclass 32, count 0 2006.285.14:37:14.30#ibcon#read 3, iclass 32, count 0 2006.285.14:37:14.30#ibcon#about to read 4, iclass 32, count 0 2006.285.14:37:14.30#ibcon#read 4, iclass 32, count 0 2006.285.14:37:14.30#ibcon#about to read 5, iclass 32, count 0 2006.285.14:37:14.30#ibcon#read 5, iclass 32, count 0 2006.285.14:37:14.30#ibcon#about to read 6, iclass 32, count 0 2006.285.14:37:14.30#ibcon#read 6, iclass 32, count 0 2006.285.14:37:14.30#ibcon#end of sib2, iclass 32, count 0 2006.285.14:37:14.30#ibcon#*mode == 0, iclass 32, count 0 2006.285.14:37:14.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.14:37:14.30#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.14:37:14.30#ibcon#*before write, iclass 32, count 0 2006.285.14:37:14.30#ibcon#enter sib2, iclass 32, count 0 2006.285.14:37:14.30#ibcon#flushed, iclass 32, count 0 2006.285.14:37:14.30#ibcon#about to write, iclass 32, count 0 2006.285.14:37:14.30#ibcon#wrote, iclass 32, count 0 2006.285.14:37:14.30#ibcon#about to read 3, iclass 32, count 0 2006.285.14:37:14.34#ibcon#read 3, iclass 32, count 0 2006.285.14:37:14.34#ibcon#about to read 4, iclass 32, count 0 2006.285.14:37:14.34#ibcon#read 4, iclass 32, count 0 2006.285.14:37:14.34#ibcon#about to read 5, iclass 32, count 0 2006.285.14:37:14.34#ibcon#read 5, iclass 32, count 0 2006.285.14:37:14.34#ibcon#about to read 6, iclass 32, count 0 2006.285.14:37:14.34#ibcon#read 6, iclass 32, count 0 2006.285.14:37:14.34#ibcon#end of sib2, iclass 32, count 0 2006.285.14:37:14.34#ibcon#*after write, iclass 32, count 0 2006.285.14:37:14.34#ibcon#*before return 0, iclass 32, count 0 2006.285.14:37:14.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:37:14.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:37:14.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.14:37:14.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.14:37:14.34$vck44/vb=3,4 2006.285.14:37:14.34#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.14:37:14.34#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.14:37:14.34#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:14.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:37:14.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:37:14.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:37:14.40#ibcon#enter wrdev, iclass 34, count 2 2006.285.14:37:14.40#ibcon#first serial, iclass 34, count 2 2006.285.14:37:14.40#ibcon#enter sib2, iclass 34, count 2 2006.285.14:37:14.40#ibcon#flushed, iclass 34, count 2 2006.285.14:37:14.40#ibcon#about to write, iclass 34, count 2 2006.285.14:37:14.40#ibcon#wrote, iclass 34, count 2 2006.285.14:37:14.40#ibcon#about to read 3, iclass 34, count 2 2006.285.14:37:14.42#ibcon#read 3, iclass 34, count 2 2006.285.14:37:14.42#ibcon#about to read 4, iclass 34, count 2 2006.285.14:37:14.42#ibcon#read 4, iclass 34, count 2 2006.285.14:37:14.42#ibcon#about to read 5, iclass 34, count 2 2006.285.14:37:14.42#ibcon#read 5, iclass 34, count 2 2006.285.14:37:14.42#ibcon#about to read 6, iclass 34, count 2 2006.285.14:37:14.42#ibcon#read 6, iclass 34, count 2 2006.285.14:37:14.42#ibcon#end of sib2, iclass 34, count 2 2006.285.14:37:14.42#ibcon#*mode == 0, iclass 34, count 2 2006.285.14:37:14.42#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.14:37:14.42#ibcon#[27=AT03-04\r\n] 2006.285.14:37:14.42#ibcon#*before write, iclass 34, count 2 2006.285.14:37:14.42#ibcon#enter sib2, iclass 34, count 2 2006.285.14:37:14.42#ibcon#flushed, iclass 34, count 2 2006.285.14:37:14.42#ibcon#about to write, iclass 34, count 2 2006.285.14:37:14.42#ibcon#wrote, iclass 34, count 2 2006.285.14:37:14.42#ibcon#about to read 3, iclass 34, count 2 2006.285.14:37:14.45#ibcon#read 3, iclass 34, count 2 2006.285.14:37:14.45#ibcon#about to read 4, iclass 34, count 2 2006.285.14:37:14.45#ibcon#read 4, iclass 34, count 2 2006.285.14:37:14.45#ibcon#about to read 5, iclass 34, count 2 2006.285.14:37:14.45#ibcon#read 5, iclass 34, count 2 2006.285.14:37:14.45#ibcon#about to read 6, iclass 34, count 2 2006.285.14:37:14.45#ibcon#read 6, iclass 34, count 2 2006.285.14:37:14.45#ibcon#end of sib2, iclass 34, count 2 2006.285.14:37:14.45#ibcon#*after write, iclass 34, count 2 2006.285.14:37:14.45#ibcon#*before return 0, iclass 34, count 2 2006.285.14:37:14.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:37:14.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.14:37:14.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.14:37:14.45#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:14.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:37:14.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:37:14.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:37:14.57#ibcon#enter wrdev, iclass 34, count 0 2006.285.14:37:14.57#ibcon#first serial, iclass 34, count 0 2006.285.14:37:14.57#ibcon#enter sib2, iclass 34, count 0 2006.285.14:37:14.57#ibcon#flushed, iclass 34, count 0 2006.285.14:37:14.57#ibcon#about to write, iclass 34, count 0 2006.285.14:37:14.57#ibcon#wrote, iclass 34, count 0 2006.285.14:37:14.57#ibcon#about to read 3, iclass 34, count 0 2006.285.14:37:14.59#ibcon#read 3, iclass 34, count 0 2006.285.14:37:14.59#ibcon#about to read 4, iclass 34, count 0 2006.285.14:37:14.59#ibcon#read 4, iclass 34, count 0 2006.285.14:37:14.59#ibcon#about to read 5, iclass 34, count 0 2006.285.14:37:14.59#ibcon#read 5, iclass 34, count 0 2006.285.14:37:14.59#ibcon#about to read 6, iclass 34, count 0 2006.285.14:37:14.59#ibcon#read 6, iclass 34, count 0 2006.285.14:37:14.59#ibcon#end of sib2, iclass 34, count 0 2006.285.14:37:14.59#ibcon#*mode == 0, iclass 34, count 0 2006.285.14:37:14.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.14:37:14.59#ibcon#[27=USB\r\n] 2006.285.14:37:14.59#ibcon#*before write, iclass 34, count 0 2006.285.14:37:14.59#ibcon#enter sib2, iclass 34, count 0 2006.285.14:37:14.59#ibcon#flushed, iclass 34, count 0 2006.285.14:37:14.59#ibcon#about to write, iclass 34, count 0 2006.285.14:37:14.59#ibcon#wrote, iclass 34, count 0 2006.285.14:37:14.59#ibcon#about to read 3, iclass 34, count 0 2006.285.14:37:14.62#ibcon#read 3, iclass 34, count 0 2006.285.14:37:14.62#ibcon#about to read 4, iclass 34, count 0 2006.285.14:37:14.62#ibcon#read 4, iclass 34, count 0 2006.285.14:37:14.62#ibcon#about to read 5, iclass 34, count 0 2006.285.14:37:14.62#ibcon#read 5, iclass 34, count 0 2006.285.14:37:14.62#ibcon#about to read 6, iclass 34, count 0 2006.285.14:37:14.62#ibcon#read 6, iclass 34, count 0 2006.285.14:37:14.62#ibcon#end of sib2, iclass 34, count 0 2006.285.14:37:14.62#ibcon#*after write, iclass 34, count 0 2006.285.14:37:14.62#ibcon#*before return 0, iclass 34, count 0 2006.285.14:37:14.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:37:14.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.14:37:14.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.14:37:14.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.14:37:14.62$vck44/vblo=4,679.99 2006.285.14:37:14.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.14:37:14.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.14:37:14.62#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:14.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:37:14.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:37:14.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:37:14.62#ibcon#enter wrdev, iclass 36, count 0 2006.285.14:37:14.62#ibcon#first serial, iclass 36, count 0 2006.285.14:37:14.62#ibcon#enter sib2, iclass 36, count 0 2006.285.14:37:14.62#ibcon#flushed, iclass 36, count 0 2006.285.14:37:14.62#ibcon#about to write, iclass 36, count 0 2006.285.14:37:14.62#ibcon#wrote, iclass 36, count 0 2006.285.14:37:14.62#ibcon#about to read 3, iclass 36, count 0 2006.285.14:37:14.64#ibcon#read 3, iclass 36, count 0 2006.285.14:37:14.64#ibcon#about to read 4, iclass 36, count 0 2006.285.14:37:14.64#ibcon#read 4, iclass 36, count 0 2006.285.14:37:14.64#ibcon#about to read 5, iclass 36, count 0 2006.285.14:37:14.64#ibcon#read 5, iclass 36, count 0 2006.285.14:37:14.64#ibcon#about to read 6, iclass 36, count 0 2006.285.14:37:14.64#ibcon#read 6, iclass 36, count 0 2006.285.14:37:14.64#ibcon#end of sib2, iclass 36, count 0 2006.285.14:37:14.64#ibcon#*mode == 0, iclass 36, count 0 2006.285.14:37:14.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.14:37:14.64#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.14:37:14.64#ibcon#*before write, iclass 36, count 0 2006.285.14:37:14.64#ibcon#enter sib2, iclass 36, count 0 2006.285.14:37:14.64#ibcon#flushed, iclass 36, count 0 2006.285.14:37:14.64#ibcon#about to write, iclass 36, count 0 2006.285.14:37:14.64#ibcon#wrote, iclass 36, count 0 2006.285.14:37:14.64#ibcon#about to read 3, iclass 36, count 0 2006.285.14:37:14.68#ibcon#read 3, iclass 36, count 0 2006.285.14:37:14.68#ibcon#about to read 4, iclass 36, count 0 2006.285.14:37:14.68#ibcon#read 4, iclass 36, count 0 2006.285.14:37:14.68#ibcon#about to read 5, iclass 36, count 0 2006.285.14:37:14.68#ibcon#read 5, iclass 36, count 0 2006.285.14:37:14.68#ibcon#about to read 6, iclass 36, count 0 2006.285.14:37:14.68#ibcon#read 6, iclass 36, count 0 2006.285.14:37:14.68#ibcon#end of sib2, iclass 36, count 0 2006.285.14:37:14.68#ibcon#*after write, iclass 36, count 0 2006.285.14:37:14.68#ibcon#*before return 0, iclass 36, count 0 2006.285.14:37:14.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:37:14.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.14:37:14.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.14:37:14.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.14:37:14.68$vck44/vb=4,5 2006.285.14:37:14.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.14:37:14.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.14:37:14.68#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:14.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:37:14.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:37:14.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:37:14.74#ibcon#enter wrdev, iclass 38, count 2 2006.285.14:37:14.74#ibcon#first serial, iclass 38, count 2 2006.285.14:37:14.74#ibcon#enter sib2, iclass 38, count 2 2006.285.14:37:14.74#ibcon#flushed, iclass 38, count 2 2006.285.14:37:14.74#ibcon#about to write, iclass 38, count 2 2006.285.14:37:14.74#ibcon#wrote, iclass 38, count 2 2006.285.14:37:14.74#ibcon#about to read 3, iclass 38, count 2 2006.285.14:37:14.76#ibcon#read 3, iclass 38, count 2 2006.285.14:37:14.76#ibcon#about to read 4, iclass 38, count 2 2006.285.14:37:14.76#ibcon#read 4, iclass 38, count 2 2006.285.14:37:14.76#ibcon#about to read 5, iclass 38, count 2 2006.285.14:37:14.76#ibcon#read 5, iclass 38, count 2 2006.285.14:37:14.76#ibcon#about to read 6, iclass 38, count 2 2006.285.14:37:14.76#ibcon#read 6, iclass 38, count 2 2006.285.14:37:14.76#ibcon#end of sib2, iclass 38, count 2 2006.285.14:37:14.76#ibcon#*mode == 0, iclass 38, count 2 2006.285.14:37:14.76#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.14:37:14.76#ibcon#[27=AT04-05\r\n] 2006.285.14:37:14.76#ibcon#*before write, iclass 38, count 2 2006.285.14:37:14.76#ibcon#enter sib2, iclass 38, count 2 2006.285.14:37:14.76#ibcon#flushed, iclass 38, count 2 2006.285.14:37:14.76#ibcon#about to write, iclass 38, count 2 2006.285.14:37:14.76#ibcon#wrote, iclass 38, count 2 2006.285.14:37:14.76#ibcon#about to read 3, iclass 38, count 2 2006.285.14:37:14.79#ibcon#read 3, iclass 38, count 2 2006.285.14:37:14.79#ibcon#about to read 4, iclass 38, count 2 2006.285.14:37:14.79#ibcon#read 4, iclass 38, count 2 2006.285.14:37:14.79#ibcon#about to read 5, iclass 38, count 2 2006.285.14:37:14.79#ibcon#read 5, iclass 38, count 2 2006.285.14:37:14.79#ibcon#about to read 6, iclass 38, count 2 2006.285.14:37:14.79#ibcon#read 6, iclass 38, count 2 2006.285.14:37:14.79#ibcon#end of sib2, iclass 38, count 2 2006.285.14:37:14.79#ibcon#*after write, iclass 38, count 2 2006.285.14:37:14.79#ibcon#*before return 0, iclass 38, count 2 2006.285.14:37:14.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:37:14.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.14:37:14.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.14:37:14.79#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:14.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:37:14.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:37:14.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:37:14.91#ibcon#enter wrdev, iclass 38, count 0 2006.285.14:37:14.91#ibcon#first serial, iclass 38, count 0 2006.285.14:37:14.91#ibcon#enter sib2, iclass 38, count 0 2006.285.14:37:14.91#ibcon#flushed, iclass 38, count 0 2006.285.14:37:14.91#ibcon#about to write, iclass 38, count 0 2006.285.14:37:14.91#ibcon#wrote, iclass 38, count 0 2006.285.14:37:14.91#ibcon#about to read 3, iclass 38, count 0 2006.285.14:37:14.93#ibcon#read 3, iclass 38, count 0 2006.285.14:37:14.93#ibcon#about to read 4, iclass 38, count 0 2006.285.14:37:14.93#ibcon#read 4, iclass 38, count 0 2006.285.14:37:14.93#ibcon#about to read 5, iclass 38, count 0 2006.285.14:37:14.93#ibcon#read 5, iclass 38, count 0 2006.285.14:37:14.93#ibcon#about to read 6, iclass 38, count 0 2006.285.14:37:14.93#ibcon#read 6, iclass 38, count 0 2006.285.14:37:14.93#ibcon#end of sib2, iclass 38, count 0 2006.285.14:37:14.93#ibcon#*mode == 0, iclass 38, count 0 2006.285.14:37:14.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.14:37:14.93#ibcon#[27=USB\r\n] 2006.285.14:37:14.93#ibcon#*before write, iclass 38, count 0 2006.285.14:37:14.93#ibcon#enter sib2, iclass 38, count 0 2006.285.14:37:14.93#ibcon#flushed, iclass 38, count 0 2006.285.14:37:14.93#ibcon#about to write, iclass 38, count 0 2006.285.14:37:14.93#ibcon#wrote, iclass 38, count 0 2006.285.14:37:14.93#ibcon#about to read 3, iclass 38, count 0 2006.285.14:37:14.96#ibcon#read 3, iclass 38, count 0 2006.285.14:37:14.96#ibcon#about to read 4, iclass 38, count 0 2006.285.14:37:14.96#ibcon#read 4, iclass 38, count 0 2006.285.14:37:14.96#ibcon#about to read 5, iclass 38, count 0 2006.285.14:37:14.96#ibcon#read 5, iclass 38, count 0 2006.285.14:37:14.96#ibcon#about to read 6, iclass 38, count 0 2006.285.14:37:14.96#ibcon#read 6, iclass 38, count 0 2006.285.14:37:14.96#ibcon#end of sib2, iclass 38, count 0 2006.285.14:37:14.96#ibcon#*after write, iclass 38, count 0 2006.285.14:37:14.96#ibcon#*before return 0, iclass 38, count 0 2006.285.14:37:14.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:37:14.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.14:37:14.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.14:37:14.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.14:37:14.96$vck44/vblo=5,709.99 2006.285.14:37:14.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.14:37:14.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.14:37:14.96#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:14.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:37:14.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:37:14.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:37:14.96#ibcon#enter wrdev, iclass 40, count 0 2006.285.14:37:14.96#ibcon#first serial, iclass 40, count 0 2006.285.14:37:14.96#ibcon#enter sib2, iclass 40, count 0 2006.285.14:37:14.96#ibcon#flushed, iclass 40, count 0 2006.285.14:37:14.96#ibcon#about to write, iclass 40, count 0 2006.285.14:37:14.96#ibcon#wrote, iclass 40, count 0 2006.285.14:37:14.96#ibcon#about to read 3, iclass 40, count 0 2006.285.14:37:14.98#ibcon#read 3, iclass 40, count 0 2006.285.14:37:14.98#ibcon#about to read 4, iclass 40, count 0 2006.285.14:37:14.98#ibcon#read 4, iclass 40, count 0 2006.285.14:37:14.98#ibcon#about to read 5, iclass 40, count 0 2006.285.14:37:14.98#ibcon#read 5, iclass 40, count 0 2006.285.14:37:14.98#ibcon#about to read 6, iclass 40, count 0 2006.285.14:37:14.98#ibcon#read 6, iclass 40, count 0 2006.285.14:37:14.98#ibcon#end of sib2, iclass 40, count 0 2006.285.14:37:14.98#ibcon#*mode == 0, iclass 40, count 0 2006.285.14:37:14.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.14:37:14.98#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.14:37:14.98#ibcon#*before write, iclass 40, count 0 2006.285.14:37:14.98#ibcon#enter sib2, iclass 40, count 0 2006.285.14:37:14.98#ibcon#flushed, iclass 40, count 0 2006.285.14:37:14.98#ibcon#about to write, iclass 40, count 0 2006.285.14:37:14.98#ibcon#wrote, iclass 40, count 0 2006.285.14:37:14.98#ibcon#about to read 3, iclass 40, count 0 2006.285.14:37:15.02#ibcon#read 3, iclass 40, count 0 2006.285.14:37:15.02#ibcon#about to read 4, iclass 40, count 0 2006.285.14:37:15.02#ibcon#read 4, iclass 40, count 0 2006.285.14:37:15.02#ibcon#about to read 5, iclass 40, count 0 2006.285.14:37:15.02#ibcon#read 5, iclass 40, count 0 2006.285.14:37:15.02#ibcon#about to read 6, iclass 40, count 0 2006.285.14:37:15.02#ibcon#read 6, iclass 40, count 0 2006.285.14:37:15.02#ibcon#end of sib2, iclass 40, count 0 2006.285.14:37:15.02#ibcon#*after write, iclass 40, count 0 2006.285.14:37:15.02#ibcon#*before return 0, iclass 40, count 0 2006.285.14:37:15.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:37:15.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.14:37:15.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.14:37:15.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.14:37:15.02$vck44/vb=5,4 2006.285.14:37:15.07#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.14:37:15.07#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.14:37:15.07#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:15.07#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:37:15.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:37:15.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:37:15.07#ibcon#enter wrdev, iclass 4, count 2 2006.285.14:37:15.07#ibcon#first serial, iclass 4, count 2 2006.285.14:37:15.07#ibcon#enter sib2, iclass 4, count 2 2006.285.14:37:15.07#ibcon#flushed, iclass 4, count 2 2006.285.14:37:15.07#ibcon#about to write, iclass 4, count 2 2006.285.14:37:15.07#ibcon#wrote, iclass 4, count 2 2006.285.14:37:15.07#ibcon#about to read 3, iclass 4, count 2 2006.285.14:37:15.09#ibcon#read 3, iclass 4, count 2 2006.285.14:37:15.09#ibcon#about to read 4, iclass 4, count 2 2006.285.14:37:15.09#ibcon#read 4, iclass 4, count 2 2006.285.14:37:15.09#ibcon#about to read 5, iclass 4, count 2 2006.285.14:37:15.09#ibcon#read 5, iclass 4, count 2 2006.285.14:37:15.09#ibcon#about to read 6, iclass 4, count 2 2006.285.14:37:15.09#ibcon#read 6, iclass 4, count 2 2006.285.14:37:15.09#ibcon#end of sib2, iclass 4, count 2 2006.285.14:37:15.09#ibcon#*mode == 0, iclass 4, count 2 2006.285.14:37:15.09#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.14:37:15.09#ibcon#[27=AT05-04\r\n] 2006.285.14:37:15.09#ibcon#*before write, iclass 4, count 2 2006.285.14:37:15.09#ibcon#enter sib2, iclass 4, count 2 2006.285.14:37:15.09#ibcon#flushed, iclass 4, count 2 2006.285.14:37:15.09#ibcon#about to write, iclass 4, count 2 2006.285.14:37:15.09#ibcon#wrote, iclass 4, count 2 2006.285.14:37:15.09#ibcon#about to read 3, iclass 4, count 2 2006.285.14:37:15.12#ibcon#read 3, iclass 4, count 2 2006.285.14:37:15.12#ibcon#about to read 4, iclass 4, count 2 2006.285.14:37:15.12#ibcon#read 4, iclass 4, count 2 2006.285.14:37:15.12#ibcon#about to read 5, iclass 4, count 2 2006.285.14:37:15.12#ibcon#read 5, iclass 4, count 2 2006.285.14:37:15.12#ibcon#about to read 6, iclass 4, count 2 2006.285.14:37:15.12#ibcon#read 6, iclass 4, count 2 2006.285.14:37:15.12#ibcon#end of sib2, iclass 4, count 2 2006.285.14:37:15.12#ibcon#*after write, iclass 4, count 2 2006.285.14:37:15.12#ibcon#*before return 0, iclass 4, count 2 2006.285.14:37:15.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:37:15.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.14:37:15.12#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.14:37:15.12#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:15.12#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:37:15.13#abcon#<5=/04 1.9 4.5 19.19 941015.1\r\n> 2006.285.14:37:15.15#abcon#{5=INTERFACE CLEAR} 2006.285.14:37:15.21#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:37:15.24#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:37:15.24#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:37:15.24#ibcon#enter wrdev, iclass 4, count 0 2006.285.14:37:15.24#ibcon#first serial, iclass 4, count 0 2006.285.14:37:15.24#ibcon#enter sib2, iclass 4, count 0 2006.285.14:37:15.24#ibcon#flushed, iclass 4, count 0 2006.285.14:37:15.24#ibcon#about to write, iclass 4, count 0 2006.285.14:37:15.24#ibcon#wrote, iclass 4, count 0 2006.285.14:37:15.24#ibcon#about to read 3, iclass 4, count 0 2006.285.14:37:15.26#ibcon#read 3, iclass 4, count 0 2006.285.14:37:15.26#ibcon#about to read 4, iclass 4, count 0 2006.285.14:37:15.26#ibcon#read 4, iclass 4, count 0 2006.285.14:37:15.26#ibcon#about to read 5, iclass 4, count 0 2006.285.14:37:15.26#ibcon#read 5, iclass 4, count 0 2006.285.14:37:15.26#ibcon#about to read 6, iclass 4, count 0 2006.285.14:37:15.26#ibcon#read 6, iclass 4, count 0 2006.285.14:37:15.26#ibcon#end of sib2, iclass 4, count 0 2006.285.14:37:15.26#ibcon#*mode == 0, iclass 4, count 0 2006.285.14:37:15.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.14:37:15.26#ibcon#[27=USB\r\n] 2006.285.14:37:15.26#ibcon#*before write, iclass 4, count 0 2006.285.14:37:15.26#ibcon#enter sib2, iclass 4, count 0 2006.285.14:37:15.26#ibcon#flushed, iclass 4, count 0 2006.285.14:37:15.26#ibcon#about to write, iclass 4, count 0 2006.285.14:37:15.26#ibcon#wrote, iclass 4, count 0 2006.285.14:37:15.26#ibcon#about to read 3, iclass 4, count 0 2006.285.14:37:15.29#ibcon#read 3, iclass 4, count 0 2006.285.14:37:15.29#ibcon#about to read 4, iclass 4, count 0 2006.285.14:37:15.29#ibcon#read 4, iclass 4, count 0 2006.285.14:37:15.29#ibcon#about to read 5, iclass 4, count 0 2006.285.14:37:15.29#ibcon#read 5, iclass 4, count 0 2006.285.14:37:15.29#ibcon#about to read 6, iclass 4, count 0 2006.285.14:37:15.29#ibcon#read 6, iclass 4, count 0 2006.285.14:37:15.29#ibcon#end of sib2, iclass 4, count 0 2006.285.14:37:15.29#ibcon#*after write, iclass 4, count 0 2006.285.14:37:15.29#ibcon#*before return 0, iclass 4, count 0 2006.285.14:37:15.29#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:37:15.29#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.14:37:15.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.14:37:15.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.14:37:15.29$vck44/vblo=6,719.99 2006.285.14:37:15.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.14:37:15.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.14:37:15.29#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:15.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:37:15.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:37:15.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:37:15.29#ibcon#enter wrdev, iclass 12, count 0 2006.285.14:37:15.29#ibcon#first serial, iclass 12, count 0 2006.285.14:37:15.29#ibcon#enter sib2, iclass 12, count 0 2006.285.14:37:15.29#ibcon#flushed, iclass 12, count 0 2006.285.14:37:15.29#ibcon#about to write, iclass 12, count 0 2006.285.14:37:15.29#ibcon#wrote, iclass 12, count 0 2006.285.14:37:15.29#ibcon#about to read 3, iclass 12, count 0 2006.285.14:37:15.31#ibcon#read 3, iclass 12, count 0 2006.285.14:37:15.31#ibcon#about to read 4, iclass 12, count 0 2006.285.14:37:15.31#ibcon#read 4, iclass 12, count 0 2006.285.14:37:15.31#ibcon#about to read 5, iclass 12, count 0 2006.285.14:37:15.31#ibcon#read 5, iclass 12, count 0 2006.285.14:37:15.31#ibcon#about to read 6, iclass 12, count 0 2006.285.14:37:15.31#ibcon#read 6, iclass 12, count 0 2006.285.14:37:15.31#ibcon#end of sib2, iclass 12, count 0 2006.285.14:37:15.31#ibcon#*mode == 0, iclass 12, count 0 2006.285.14:37:15.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.14:37:15.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.14:37:15.31#ibcon#*before write, iclass 12, count 0 2006.285.14:37:15.31#ibcon#enter sib2, iclass 12, count 0 2006.285.14:37:15.31#ibcon#flushed, iclass 12, count 0 2006.285.14:37:15.31#ibcon#about to write, iclass 12, count 0 2006.285.14:37:15.31#ibcon#wrote, iclass 12, count 0 2006.285.14:37:15.31#ibcon#about to read 3, iclass 12, count 0 2006.285.14:37:15.35#ibcon#read 3, iclass 12, count 0 2006.285.14:37:15.35#ibcon#about to read 4, iclass 12, count 0 2006.285.14:37:15.35#ibcon#read 4, iclass 12, count 0 2006.285.14:37:15.35#ibcon#about to read 5, iclass 12, count 0 2006.285.14:37:15.35#ibcon#read 5, iclass 12, count 0 2006.285.14:37:15.35#ibcon#about to read 6, iclass 12, count 0 2006.285.14:37:15.35#ibcon#read 6, iclass 12, count 0 2006.285.14:37:15.35#ibcon#end of sib2, iclass 12, count 0 2006.285.14:37:15.35#ibcon#*after write, iclass 12, count 0 2006.285.14:37:15.35#ibcon#*before return 0, iclass 12, count 0 2006.285.14:37:15.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:37:15.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.14:37:15.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.14:37:15.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.14:37:15.35$vck44/vb=6,3 2006.285.14:37:15.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.14:37:15.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.14:37:15.35#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:15.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:37:15.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:37:15.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:37:15.41#ibcon#enter wrdev, iclass 14, count 2 2006.285.14:37:15.41#ibcon#first serial, iclass 14, count 2 2006.285.14:37:15.41#ibcon#enter sib2, iclass 14, count 2 2006.285.14:37:15.41#ibcon#flushed, iclass 14, count 2 2006.285.14:37:15.41#ibcon#about to write, iclass 14, count 2 2006.285.14:37:15.41#ibcon#wrote, iclass 14, count 2 2006.285.14:37:15.41#ibcon#about to read 3, iclass 14, count 2 2006.285.14:37:15.43#ibcon#read 3, iclass 14, count 2 2006.285.14:37:15.43#ibcon#about to read 4, iclass 14, count 2 2006.285.14:37:15.43#ibcon#read 4, iclass 14, count 2 2006.285.14:37:15.43#ibcon#about to read 5, iclass 14, count 2 2006.285.14:37:15.43#ibcon#read 5, iclass 14, count 2 2006.285.14:37:15.43#ibcon#about to read 6, iclass 14, count 2 2006.285.14:37:15.43#ibcon#read 6, iclass 14, count 2 2006.285.14:37:15.43#ibcon#end of sib2, iclass 14, count 2 2006.285.14:37:15.43#ibcon#*mode == 0, iclass 14, count 2 2006.285.14:37:15.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.14:37:15.43#ibcon#[27=AT06-03\r\n] 2006.285.14:37:15.43#ibcon#*before write, iclass 14, count 2 2006.285.14:37:15.43#ibcon#enter sib2, iclass 14, count 2 2006.285.14:37:15.43#ibcon#flushed, iclass 14, count 2 2006.285.14:37:15.43#ibcon#about to write, iclass 14, count 2 2006.285.14:37:15.43#ibcon#wrote, iclass 14, count 2 2006.285.14:37:15.43#ibcon#about to read 3, iclass 14, count 2 2006.285.14:37:15.46#ibcon#read 3, iclass 14, count 2 2006.285.14:37:15.46#ibcon#about to read 4, iclass 14, count 2 2006.285.14:37:15.46#ibcon#read 4, iclass 14, count 2 2006.285.14:37:15.46#ibcon#about to read 5, iclass 14, count 2 2006.285.14:37:15.46#ibcon#read 5, iclass 14, count 2 2006.285.14:37:15.46#ibcon#about to read 6, iclass 14, count 2 2006.285.14:37:15.46#ibcon#read 6, iclass 14, count 2 2006.285.14:37:15.46#ibcon#end of sib2, iclass 14, count 2 2006.285.14:37:15.46#ibcon#*after write, iclass 14, count 2 2006.285.14:37:15.46#ibcon#*before return 0, iclass 14, count 2 2006.285.14:37:15.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:37:15.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.14:37:15.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.14:37:15.46#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:15.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:37:15.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:37:15.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:37:15.58#ibcon#enter wrdev, iclass 14, count 0 2006.285.14:37:15.58#ibcon#first serial, iclass 14, count 0 2006.285.14:37:15.58#ibcon#enter sib2, iclass 14, count 0 2006.285.14:37:15.58#ibcon#flushed, iclass 14, count 0 2006.285.14:37:15.58#ibcon#about to write, iclass 14, count 0 2006.285.14:37:15.58#ibcon#wrote, iclass 14, count 0 2006.285.14:37:15.58#ibcon#about to read 3, iclass 14, count 0 2006.285.14:37:15.60#ibcon#read 3, iclass 14, count 0 2006.285.14:37:15.60#ibcon#about to read 4, iclass 14, count 0 2006.285.14:37:15.60#ibcon#read 4, iclass 14, count 0 2006.285.14:37:15.60#ibcon#about to read 5, iclass 14, count 0 2006.285.14:37:15.60#ibcon#read 5, iclass 14, count 0 2006.285.14:37:15.60#ibcon#about to read 6, iclass 14, count 0 2006.285.14:37:15.60#ibcon#read 6, iclass 14, count 0 2006.285.14:37:15.60#ibcon#end of sib2, iclass 14, count 0 2006.285.14:37:15.60#ibcon#*mode == 0, iclass 14, count 0 2006.285.14:37:15.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.14:37:15.60#ibcon#[27=USB\r\n] 2006.285.14:37:15.60#ibcon#*before write, iclass 14, count 0 2006.285.14:37:15.60#ibcon#enter sib2, iclass 14, count 0 2006.285.14:37:15.60#ibcon#flushed, iclass 14, count 0 2006.285.14:37:15.60#ibcon#about to write, iclass 14, count 0 2006.285.14:37:15.60#ibcon#wrote, iclass 14, count 0 2006.285.14:37:15.60#ibcon#about to read 3, iclass 14, count 0 2006.285.14:37:15.63#ibcon#read 3, iclass 14, count 0 2006.285.14:37:15.63#ibcon#about to read 4, iclass 14, count 0 2006.285.14:37:15.63#ibcon#read 4, iclass 14, count 0 2006.285.14:37:15.63#ibcon#about to read 5, iclass 14, count 0 2006.285.14:37:15.63#ibcon#read 5, iclass 14, count 0 2006.285.14:37:15.63#ibcon#about to read 6, iclass 14, count 0 2006.285.14:37:15.63#ibcon#read 6, iclass 14, count 0 2006.285.14:37:15.63#ibcon#end of sib2, iclass 14, count 0 2006.285.14:37:15.63#ibcon#*after write, iclass 14, count 0 2006.285.14:37:15.63#ibcon#*before return 0, iclass 14, count 0 2006.285.14:37:15.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:37:15.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.14:37:15.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.14:37:15.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.14:37:15.63$vck44/vblo=7,734.99 2006.285.14:37:15.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.14:37:15.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.14:37:15.63#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:15.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:37:15.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:37:15.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:37:15.63#ibcon#enter wrdev, iclass 16, count 0 2006.285.14:37:15.63#ibcon#first serial, iclass 16, count 0 2006.285.14:37:15.63#ibcon#enter sib2, iclass 16, count 0 2006.285.14:37:15.63#ibcon#flushed, iclass 16, count 0 2006.285.14:37:15.63#ibcon#about to write, iclass 16, count 0 2006.285.14:37:15.63#ibcon#wrote, iclass 16, count 0 2006.285.14:37:15.63#ibcon#about to read 3, iclass 16, count 0 2006.285.14:37:15.65#ibcon#read 3, iclass 16, count 0 2006.285.14:37:15.65#ibcon#about to read 4, iclass 16, count 0 2006.285.14:37:15.65#ibcon#read 4, iclass 16, count 0 2006.285.14:37:15.65#ibcon#about to read 5, iclass 16, count 0 2006.285.14:37:15.65#ibcon#read 5, iclass 16, count 0 2006.285.14:37:15.65#ibcon#about to read 6, iclass 16, count 0 2006.285.14:37:15.65#ibcon#read 6, iclass 16, count 0 2006.285.14:37:15.65#ibcon#end of sib2, iclass 16, count 0 2006.285.14:37:15.65#ibcon#*mode == 0, iclass 16, count 0 2006.285.14:37:15.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.14:37:15.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.14:37:15.65#ibcon#*before write, iclass 16, count 0 2006.285.14:37:15.65#ibcon#enter sib2, iclass 16, count 0 2006.285.14:37:15.65#ibcon#flushed, iclass 16, count 0 2006.285.14:37:15.65#ibcon#about to write, iclass 16, count 0 2006.285.14:37:15.65#ibcon#wrote, iclass 16, count 0 2006.285.14:37:15.65#ibcon#about to read 3, iclass 16, count 0 2006.285.14:37:15.69#ibcon#read 3, iclass 16, count 0 2006.285.14:37:15.69#ibcon#about to read 4, iclass 16, count 0 2006.285.14:37:15.69#ibcon#read 4, iclass 16, count 0 2006.285.14:37:15.69#ibcon#about to read 5, iclass 16, count 0 2006.285.14:37:15.69#ibcon#read 5, iclass 16, count 0 2006.285.14:37:15.69#ibcon#about to read 6, iclass 16, count 0 2006.285.14:37:15.69#ibcon#read 6, iclass 16, count 0 2006.285.14:37:15.69#ibcon#end of sib2, iclass 16, count 0 2006.285.14:37:15.69#ibcon#*after write, iclass 16, count 0 2006.285.14:37:15.69#ibcon#*before return 0, iclass 16, count 0 2006.285.14:37:15.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:37:15.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.14:37:15.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.14:37:15.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.14:37:15.69$vck44/vb=7,4 2006.285.14:37:15.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.14:37:15.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.14:37:15.69#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:15.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:37:15.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:37:15.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:37:15.75#ibcon#enter wrdev, iclass 18, count 2 2006.285.14:37:15.75#ibcon#first serial, iclass 18, count 2 2006.285.14:37:15.75#ibcon#enter sib2, iclass 18, count 2 2006.285.14:37:15.75#ibcon#flushed, iclass 18, count 2 2006.285.14:37:15.75#ibcon#about to write, iclass 18, count 2 2006.285.14:37:15.75#ibcon#wrote, iclass 18, count 2 2006.285.14:37:15.75#ibcon#about to read 3, iclass 18, count 2 2006.285.14:37:15.77#ibcon#read 3, iclass 18, count 2 2006.285.14:37:15.77#ibcon#about to read 4, iclass 18, count 2 2006.285.14:37:15.77#ibcon#read 4, iclass 18, count 2 2006.285.14:37:15.77#ibcon#about to read 5, iclass 18, count 2 2006.285.14:37:15.77#ibcon#read 5, iclass 18, count 2 2006.285.14:37:15.77#ibcon#about to read 6, iclass 18, count 2 2006.285.14:37:15.77#ibcon#read 6, iclass 18, count 2 2006.285.14:37:15.77#ibcon#end of sib2, iclass 18, count 2 2006.285.14:37:15.77#ibcon#*mode == 0, iclass 18, count 2 2006.285.14:37:15.77#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.14:37:15.77#ibcon#[27=AT07-04\r\n] 2006.285.14:37:15.77#ibcon#*before write, iclass 18, count 2 2006.285.14:37:15.77#ibcon#enter sib2, iclass 18, count 2 2006.285.14:37:15.77#ibcon#flushed, iclass 18, count 2 2006.285.14:37:15.77#ibcon#about to write, iclass 18, count 2 2006.285.14:37:15.77#ibcon#wrote, iclass 18, count 2 2006.285.14:37:15.77#ibcon#about to read 3, iclass 18, count 2 2006.285.14:37:15.80#ibcon#read 3, iclass 18, count 2 2006.285.14:37:15.80#ibcon#about to read 4, iclass 18, count 2 2006.285.14:37:15.80#ibcon#read 4, iclass 18, count 2 2006.285.14:37:15.80#ibcon#about to read 5, iclass 18, count 2 2006.285.14:37:15.80#ibcon#read 5, iclass 18, count 2 2006.285.14:37:15.80#ibcon#about to read 6, iclass 18, count 2 2006.285.14:37:15.80#ibcon#read 6, iclass 18, count 2 2006.285.14:37:15.80#ibcon#end of sib2, iclass 18, count 2 2006.285.14:37:15.80#ibcon#*after write, iclass 18, count 2 2006.285.14:37:15.80#ibcon#*before return 0, iclass 18, count 2 2006.285.14:37:15.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:37:15.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.14:37:15.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.14:37:15.80#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:15.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:37:15.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:37:15.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:37:15.92#ibcon#enter wrdev, iclass 18, count 0 2006.285.14:37:15.92#ibcon#first serial, iclass 18, count 0 2006.285.14:37:15.92#ibcon#enter sib2, iclass 18, count 0 2006.285.14:37:15.92#ibcon#flushed, iclass 18, count 0 2006.285.14:37:15.92#ibcon#about to write, iclass 18, count 0 2006.285.14:37:15.92#ibcon#wrote, iclass 18, count 0 2006.285.14:37:15.92#ibcon#about to read 3, iclass 18, count 0 2006.285.14:37:15.94#ibcon#read 3, iclass 18, count 0 2006.285.14:37:15.94#ibcon#about to read 4, iclass 18, count 0 2006.285.14:37:15.94#ibcon#read 4, iclass 18, count 0 2006.285.14:37:15.94#ibcon#about to read 5, iclass 18, count 0 2006.285.14:37:15.94#ibcon#read 5, iclass 18, count 0 2006.285.14:37:15.94#ibcon#about to read 6, iclass 18, count 0 2006.285.14:37:15.94#ibcon#read 6, iclass 18, count 0 2006.285.14:37:15.94#ibcon#end of sib2, iclass 18, count 0 2006.285.14:37:15.94#ibcon#*mode == 0, iclass 18, count 0 2006.285.14:37:15.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.14:37:15.94#ibcon#[27=USB\r\n] 2006.285.14:37:15.94#ibcon#*before write, iclass 18, count 0 2006.285.14:37:15.94#ibcon#enter sib2, iclass 18, count 0 2006.285.14:37:15.94#ibcon#flushed, iclass 18, count 0 2006.285.14:37:15.94#ibcon#about to write, iclass 18, count 0 2006.285.14:37:15.94#ibcon#wrote, iclass 18, count 0 2006.285.14:37:15.94#ibcon#about to read 3, iclass 18, count 0 2006.285.14:37:15.97#ibcon#read 3, iclass 18, count 0 2006.285.14:37:15.97#ibcon#about to read 4, iclass 18, count 0 2006.285.14:37:15.97#ibcon#read 4, iclass 18, count 0 2006.285.14:37:15.97#ibcon#about to read 5, iclass 18, count 0 2006.285.14:37:15.97#ibcon#read 5, iclass 18, count 0 2006.285.14:37:15.97#ibcon#about to read 6, iclass 18, count 0 2006.285.14:37:15.97#ibcon#read 6, iclass 18, count 0 2006.285.14:37:15.97#ibcon#end of sib2, iclass 18, count 0 2006.285.14:37:15.97#ibcon#*after write, iclass 18, count 0 2006.285.14:37:15.97#ibcon#*before return 0, iclass 18, count 0 2006.285.14:37:15.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:37:15.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.14:37:15.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.14:37:15.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.14:37:15.97$vck44/vblo=8,744.99 2006.285.14:37:15.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.14:37:15.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.14:37:15.97#ibcon#ireg 17 cls_cnt 0 2006.285.14:37:15.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:37:15.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:37:15.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:37:15.97#ibcon#enter wrdev, iclass 20, count 0 2006.285.14:37:15.97#ibcon#first serial, iclass 20, count 0 2006.285.14:37:15.97#ibcon#enter sib2, iclass 20, count 0 2006.285.14:37:15.97#ibcon#flushed, iclass 20, count 0 2006.285.14:37:15.97#ibcon#about to write, iclass 20, count 0 2006.285.14:37:15.97#ibcon#wrote, iclass 20, count 0 2006.285.14:37:15.97#ibcon#about to read 3, iclass 20, count 0 2006.285.14:37:15.99#ibcon#read 3, iclass 20, count 0 2006.285.14:37:15.99#ibcon#about to read 4, iclass 20, count 0 2006.285.14:37:15.99#ibcon#read 4, iclass 20, count 0 2006.285.14:37:15.99#ibcon#about to read 5, iclass 20, count 0 2006.285.14:37:15.99#ibcon#read 5, iclass 20, count 0 2006.285.14:37:15.99#ibcon#about to read 6, iclass 20, count 0 2006.285.14:37:15.99#ibcon#read 6, iclass 20, count 0 2006.285.14:37:15.99#ibcon#end of sib2, iclass 20, count 0 2006.285.14:37:15.99#ibcon#*mode == 0, iclass 20, count 0 2006.285.14:37:15.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.14:37:15.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.14:37:15.99#ibcon#*before write, iclass 20, count 0 2006.285.14:37:15.99#ibcon#enter sib2, iclass 20, count 0 2006.285.14:37:15.99#ibcon#flushed, iclass 20, count 0 2006.285.14:37:15.99#ibcon#about to write, iclass 20, count 0 2006.285.14:37:15.99#ibcon#wrote, iclass 20, count 0 2006.285.14:37:15.99#ibcon#about to read 3, iclass 20, count 0 2006.285.14:37:16.03#ibcon#read 3, iclass 20, count 0 2006.285.14:37:16.03#ibcon#about to read 4, iclass 20, count 0 2006.285.14:37:16.03#ibcon#read 4, iclass 20, count 0 2006.285.14:37:16.03#ibcon#about to read 5, iclass 20, count 0 2006.285.14:37:16.03#ibcon#read 5, iclass 20, count 0 2006.285.14:37:16.03#ibcon#about to read 6, iclass 20, count 0 2006.285.14:37:16.03#ibcon#read 6, iclass 20, count 0 2006.285.14:37:16.03#ibcon#end of sib2, iclass 20, count 0 2006.285.14:37:16.03#ibcon#*after write, iclass 20, count 0 2006.285.14:37:16.03#ibcon#*before return 0, iclass 20, count 0 2006.285.14:37:16.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:37:16.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.14:37:16.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.14:37:16.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.14:37:16.03$vck44/vb=8,4 2006.285.14:37:16.48#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.14:37:16.48#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.14:37:16.48#ibcon#ireg 11 cls_cnt 2 2006.285.14:37:16.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:37:16.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:37:16.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:37:16.48#ibcon#enter wrdev, iclass 22, count 2 2006.285.14:37:16.48#ibcon#first serial, iclass 22, count 2 2006.285.14:37:16.48#ibcon#enter sib2, iclass 22, count 2 2006.285.14:37:16.48#ibcon#flushed, iclass 22, count 2 2006.285.14:37:16.48#ibcon#about to write, iclass 22, count 2 2006.285.14:37:16.48#ibcon#wrote, iclass 22, count 2 2006.285.14:37:16.48#ibcon#about to read 3, iclass 22, count 2 2006.285.14:37:16.49#ibcon#read 3, iclass 22, count 2 2006.285.14:37:16.49#ibcon#about to read 4, iclass 22, count 2 2006.285.14:37:16.49#ibcon#read 4, iclass 22, count 2 2006.285.14:37:16.49#ibcon#about to read 5, iclass 22, count 2 2006.285.14:37:16.49#ibcon#read 5, iclass 22, count 2 2006.285.14:37:16.49#ibcon#about to read 6, iclass 22, count 2 2006.285.14:37:16.49#ibcon#read 6, iclass 22, count 2 2006.285.14:37:16.49#ibcon#end of sib2, iclass 22, count 2 2006.285.14:37:16.49#ibcon#*mode == 0, iclass 22, count 2 2006.285.14:37:16.49#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.14:37:16.49#ibcon#[27=AT08-04\r\n] 2006.285.14:37:16.49#ibcon#*before write, iclass 22, count 2 2006.285.14:37:16.49#ibcon#enter sib2, iclass 22, count 2 2006.285.14:37:16.49#ibcon#flushed, iclass 22, count 2 2006.285.14:37:16.49#ibcon#about to write, iclass 22, count 2 2006.285.14:37:16.49#ibcon#wrote, iclass 22, count 2 2006.285.14:37:16.49#ibcon#about to read 3, iclass 22, count 2 2006.285.14:37:16.52#ibcon#read 3, iclass 22, count 2 2006.285.14:37:16.52#ibcon#about to read 4, iclass 22, count 2 2006.285.14:37:16.52#ibcon#read 4, iclass 22, count 2 2006.285.14:37:16.52#ibcon#about to read 5, iclass 22, count 2 2006.285.14:37:16.52#ibcon#read 5, iclass 22, count 2 2006.285.14:37:16.52#ibcon#about to read 6, iclass 22, count 2 2006.285.14:37:16.52#ibcon#read 6, iclass 22, count 2 2006.285.14:37:16.52#ibcon#end of sib2, iclass 22, count 2 2006.285.14:37:16.52#ibcon#*after write, iclass 22, count 2 2006.285.14:37:16.52#ibcon#*before return 0, iclass 22, count 2 2006.285.14:37:16.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:37:16.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.14:37:16.52#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.14:37:16.52#ibcon#ireg 7 cls_cnt 0 2006.285.14:37:16.52#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:37:16.64#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:37:16.64#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:37:16.64#ibcon#enter wrdev, iclass 22, count 0 2006.285.14:37:16.64#ibcon#first serial, iclass 22, count 0 2006.285.14:37:16.64#ibcon#enter sib2, iclass 22, count 0 2006.285.14:37:16.64#ibcon#flushed, iclass 22, count 0 2006.285.14:37:16.64#ibcon#about to write, iclass 22, count 0 2006.285.14:37:16.64#ibcon#wrote, iclass 22, count 0 2006.285.14:37:16.64#ibcon#about to read 3, iclass 22, count 0 2006.285.14:37:16.66#ibcon#read 3, iclass 22, count 0 2006.285.14:37:16.66#ibcon#about to read 4, iclass 22, count 0 2006.285.14:37:16.66#ibcon#read 4, iclass 22, count 0 2006.285.14:37:16.66#ibcon#about to read 5, iclass 22, count 0 2006.285.14:37:16.66#ibcon#read 5, iclass 22, count 0 2006.285.14:37:16.66#ibcon#about to read 6, iclass 22, count 0 2006.285.14:37:16.66#ibcon#read 6, iclass 22, count 0 2006.285.14:37:16.66#ibcon#end of sib2, iclass 22, count 0 2006.285.14:37:16.66#ibcon#*mode == 0, iclass 22, count 0 2006.285.14:37:16.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.14:37:16.66#ibcon#[27=USB\r\n] 2006.285.14:37:16.66#ibcon#*before write, iclass 22, count 0 2006.285.14:37:16.66#ibcon#enter sib2, iclass 22, count 0 2006.285.14:37:16.66#ibcon#flushed, iclass 22, count 0 2006.285.14:37:16.66#ibcon#about to write, iclass 22, count 0 2006.285.14:37:16.66#ibcon#wrote, iclass 22, count 0 2006.285.14:37:16.66#ibcon#about to read 3, iclass 22, count 0 2006.285.14:37:16.69#ibcon#read 3, iclass 22, count 0 2006.285.14:37:16.69#ibcon#about to read 4, iclass 22, count 0 2006.285.14:37:16.69#ibcon#read 4, iclass 22, count 0 2006.285.14:37:16.69#ibcon#about to read 5, iclass 22, count 0 2006.285.14:37:16.69#ibcon#read 5, iclass 22, count 0 2006.285.14:37:16.69#ibcon#about to read 6, iclass 22, count 0 2006.285.14:37:16.69#ibcon#read 6, iclass 22, count 0 2006.285.14:37:16.69#ibcon#end of sib2, iclass 22, count 0 2006.285.14:37:16.69#ibcon#*after write, iclass 22, count 0 2006.285.14:37:16.69#ibcon#*before return 0, iclass 22, count 0 2006.285.14:37:16.69#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:37:16.69#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.14:37:16.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.14:37:16.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.14:37:16.69$vck44/vabw=wide 2006.285.14:37:16.69#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.14:37:16.69#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.14:37:16.69#ibcon#ireg 8 cls_cnt 0 2006.285.14:37:16.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:37:16.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:37:16.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:37:16.69#ibcon#enter wrdev, iclass 24, count 0 2006.285.14:37:16.69#ibcon#first serial, iclass 24, count 0 2006.285.14:37:16.69#ibcon#enter sib2, iclass 24, count 0 2006.285.14:37:16.69#ibcon#flushed, iclass 24, count 0 2006.285.14:37:16.69#ibcon#about to write, iclass 24, count 0 2006.285.14:37:16.69#ibcon#wrote, iclass 24, count 0 2006.285.14:37:16.69#ibcon#about to read 3, iclass 24, count 0 2006.285.14:37:16.71#ibcon#read 3, iclass 24, count 0 2006.285.14:37:16.71#ibcon#about to read 4, iclass 24, count 0 2006.285.14:37:16.71#ibcon#read 4, iclass 24, count 0 2006.285.14:37:16.71#ibcon#about to read 5, iclass 24, count 0 2006.285.14:37:16.71#ibcon#read 5, iclass 24, count 0 2006.285.14:37:16.71#ibcon#about to read 6, iclass 24, count 0 2006.285.14:37:16.71#ibcon#read 6, iclass 24, count 0 2006.285.14:37:16.71#ibcon#end of sib2, iclass 24, count 0 2006.285.14:37:16.71#ibcon#*mode == 0, iclass 24, count 0 2006.285.14:37:16.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.14:37:16.71#ibcon#[25=BW32\r\n] 2006.285.14:37:16.71#ibcon#*before write, iclass 24, count 0 2006.285.14:37:16.71#ibcon#enter sib2, iclass 24, count 0 2006.285.14:37:16.71#ibcon#flushed, iclass 24, count 0 2006.285.14:37:16.71#ibcon#about to write, iclass 24, count 0 2006.285.14:37:16.71#ibcon#wrote, iclass 24, count 0 2006.285.14:37:16.71#ibcon#about to read 3, iclass 24, count 0 2006.285.14:37:16.74#ibcon#read 3, iclass 24, count 0 2006.285.14:37:16.74#ibcon#about to read 4, iclass 24, count 0 2006.285.14:37:16.74#ibcon#read 4, iclass 24, count 0 2006.285.14:37:16.74#ibcon#about to read 5, iclass 24, count 0 2006.285.14:37:16.74#ibcon#read 5, iclass 24, count 0 2006.285.14:37:16.74#ibcon#about to read 6, iclass 24, count 0 2006.285.14:37:16.74#ibcon#read 6, iclass 24, count 0 2006.285.14:37:16.74#ibcon#end of sib2, iclass 24, count 0 2006.285.14:37:16.74#ibcon#*after write, iclass 24, count 0 2006.285.14:37:16.74#ibcon#*before return 0, iclass 24, count 0 2006.285.14:37:16.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:37:16.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.14:37:16.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.14:37:16.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.14:37:16.74$vck44/vbbw=wide 2006.285.14:37:16.74#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.14:37:16.74#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.14:37:16.74#ibcon#ireg 8 cls_cnt 0 2006.285.14:37:16.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:37:16.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:37:16.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:37:16.81#ibcon#enter wrdev, iclass 26, count 0 2006.285.14:37:16.81#ibcon#first serial, iclass 26, count 0 2006.285.14:37:16.81#ibcon#enter sib2, iclass 26, count 0 2006.285.14:37:16.81#ibcon#flushed, iclass 26, count 0 2006.285.14:37:16.81#ibcon#about to write, iclass 26, count 0 2006.285.14:37:16.81#ibcon#wrote, iclass 26, count 0 2006.285.14:37:16.81#ibcon#about to read 3, iclass 26, count 0 2006.285.14:37:16.83#ibcon#read 3, iclass 26, count 0 2006.285.14:37:16.83#ibcon#about to read 4, iclass 26, count 0 2006.285.14:37:16.83#ibcon#read 4, iclass 26, count 0 2006.285.14:37:16.83#ibcon#about to read 5, iclass 26, count 0 2006.285.14:37:16.83#ibcon#read 5, iclass 26, count 0 2006.285.14:37:16.83#ibcon#about to read 6, iclass 26, count 0 2006.285.14:37:16.83#ibcon#read 6, iclass 26, count 0 2006.285.14:37:16.83#ibcon#end of sib2, iclass 26, count 0 2006.285.14:37:16.83#ibcon#*mode == 0, iclass 26, count 0 2006.285.14:37:16.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.14:37:16.83#ibcon#[27=BW32\r\n] 2006.285.14:37:16.83#ibcon#*before write, iclass 26, count 0 2006.285.14:37:16.83#ibcon#enter sib2, iclass 26, count 0 2006.285.14:37:16.83#ibcon#flushed, iclass 26, count 0 2006.285.14:37:16.83#ibcon#about to write, iclass 26, count 0 2006.285.14:37:16.83#ibcon#wrote, iclass 26, count 0 2006.285.14:37:16.83#ibcon#about to read 3, iclass 26, count 0 2006.285.14:37:16.86#ibcon#read 3, iclass 26, count 0 2006.285.14:37:16.86#ibcon#about to read 4, iclass 26, count 0 2006.285.14:37:16.86#ibcon#read 4, iclass 26, count 0 2006.285.14:37:16.86#ibcon#about to read 5, iclass 26, count 0 2006.285.14:37:16.86#ibcon#read 5, iclass 26, count 0 2006.285.14:37:16.86#ibcon#about to read 6, iclass 26, count 0 2006.285.14:37:16.86#ibcon#read 6, iclass 26, count 0 2006.285.14:37:16.86#ibcon#end of sib2, iclass 26, count 0 2006.285.14:37:16.86#ibcon#*after write, iclass 26, count 0 2006.285.14:37:16.86#ibcon#*before return 0, iclass 26, count 0 2006.285.14:37:16.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:37:16.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:37:16.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.14:37:16.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.14:37:16.86$setupk4/ifdk4 2006.285.14:37:16.86$ifdk4/lo= 2006.285.14:37:16.86$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.14:37:16.86$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.14:37:16.86$ifdk4/patch= 2006.285.14:37:16.86$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.14:37:16.86$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.14:37:16.86$setupk4/!*+20s 2006.285.14:37:25.43#abcon#<5=/04 2.0 4.5 19.19 941015.1\r\n> 2006.285.14:37:25.45#abcon#{5=INTERFACE CLEAR} 2006.285.14:37:25.51#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:37:30.00$setupk4/"tpicd 2006.285.14:37:30.00$setupk4/echo=off 2006.285.14:37:30.00$setupk4/xlog=off 2006.285.14:37:30.00:!2006.285.14:39:25 2006.285.14:37:30.13#trakl#Source acquired 2006.285.14:37:32.13#flagr#flagr/antenna,acquired 2006.285.14:39:25.00:preob 2006.285.14:39:25.14/onsource/TRACKING 2006.285.14:39:25.14:!2006.285.14:39:35 2006.285.14:39:35.00:"tape 2006.285.14:39:35.00:"st=record 2006.285.14:39:35.00:data_valid=on 2006.285.14:39:35.00:midob 2006.285.14:39:35.14/onsource/TRACKING 2006.285.14:39:35.14/wx/19.19,1015.1,94 2006.285.14:39:35.27/cable/+6.4991E-03 2006.285.14:39:36.36/va/01,07,usb,yes,33,36 2006.285.14:39:36.36/va/02,06,usb,yes,34,34 2006.285.14:39:36.36/va/03,07,usb,yes,33,35 2006.285.14:39:36.36/va/04,06,usb,yes,35,36 2006.285.14:39:36.36/va/05,03,usb,yes,34,35 2006.285.14:39:36.36/va/06,04,usb,yes,31,30 2006.285.14:39:36.36/va/07,04,usb,yes,31,32 2006.285.14:39:36.36/va/08,03,usb,yes,32,39 2006.285.14:39:36.59/valo/01,524.99,yes,locked 2006.285.14:39:36.59/valo/02,534.99,yes,locked 2006.285.14:39:36.59/valo/03,564.99,yes,locked 2006.285.14:39:36.59/valo/04,624.99,yes,locked 2006.285.14:39:36.59/valo/05,734.99,yes,locked 2006.285.14:39:36.59/valo/06,814.99,yes,locked 2006.285.14:39:36.59/valo/07,864.99,yes,locked 2006.285.14:39:36.59/valo/08,884.99,yes,locked 2006.285.14:39:37.68/vb/01,04,usb,yes,31,29 2006.285.14:39:37.68/vb/02,05,usb,yes,29,29 2006.285.14:39:37.68/vb/03,04,usb,yes,30,33 2006.285.14:39:37.68/vb/04,05,usb,yes,30,29 2006.285.14:39:37.68/vb/05,04,usb,yes,27,29 2006.285.14:39:37.68/vb/06,03,usb,yes,39,35 2006.285.14:39:37.68/vb/07,04,usb,yes,31,31 2006.285.14:39:37.68/vb/08,04,usb,yes,28,32 2006.285.14:39:37.91/vblo/01,629.99,yes,locked 2006.285.14:39:37.91/vblo/02,634.99,yes,locked 2006.285.14:39:37.91/vblo/03,649.99,yes,locked 2006.285.14:39:37.91/vblo/04,679.99,yes,locked 2006.285.14:39:37.91/vblo/05,709.99,yes,locked 2006.285.14:39:37.91/vblo/06,719.99,yes,locked 2006.285.14:39:37.91/vblo/07,734.99,yes,locked 2006.285.14:39:37.91/vblo/08,744.99,yes,locked 2006.285.14:39:38.06/vabw/8 2006.285.14:39:38.21/vbbw/8 2006.285.14:39:38.30/xfe/off,on,12.0 2006.285.14:39:38.67/ifatt/23,28,28,28 2006.285.14:39:39.08/fmout-gps/S +2.91E-07 2006.285.14:39:39.10:!2006.285.14:43:25 2006.285.14:43:25.00:data_valid=off 2006.285.14:43:25.00:"et 2006.285.14:43:25.00:!+3s 2006.285.14:43:28.01:"tape 2006.285.14:43:28.01:postob 2006.285.14:43:28.20/cable/+6.5001E-03 2006.285.14:43:28.20/wx/19.18,1015.0,94 2006.285.14:43:29.08/fmout-gps/S +2.86E-07 2006.285.14:43:29.08:scan_name=285-1448,jd0610,50 2006.285.14:43:29.08:source=0552+398,055530.81,394849.2,2000.0,cw 2006.285.14:43:30.14#flagr#flagr/antenna,new-source 2006.285.14:43:30.14:checkk5 2006.285.14:43:30.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.14:43:31.03/chk_autoobs//k5ts2/ autoobs is running! 2006.285.14:43:31.44/chk_autoobs//k5ts3/ autoobs is running! 2006.285.14:43:31.94/chk_autoobs//k5ts4/ autoobs is running! 2006.285.14:43:32.39/chk_obsdata//k5ts1/T2851439??a.dat file size is correct (nominal:920MB, actual:920MB). 2006.285.14:43:32.82/chk_obsdata//k5ts2/T2851439??b.dat file size is correct (nominal:920MB, actual:920MB). 2006.285.14:43:33.27/chk_obsdata//k5ts3/T2851439??c.dat file size is correct (nominal:920MB, actual:920MB). 2006.285.14:43:33.65/chk_obsdata//k5ts4/T2851439??d.dat file size is correct (nominal:920MB, actual:920MB). 2006.285.14:43:34.47/k5log//k5ts1_log_newline 2006.285.14:43:35.59/k5log//k5ts2_log_newline 2006.285.14:43:36.75/k5log//k5ts3_log_newline 2006.285.14:43:37.50/k5log//k5ts4_log_newline 2006.285.14:43:37.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.14:43:37.52:setupk4=1 2006.285.14:43:37.52$setupk4/echo=on 2006.285.14:43:37.52$setupk4/pcalon 2006.285.14:43:37.52$pcalon/"no phase cal control is implemented here 2006.285.14:43:37.52$setupk4/"tpicd=stop 2006.285.14:43:37.52$setupk4/"rec=synch_on 2006.285.14:43:37.52$setupk4/"rec_mode=128 2006.285.14:43:37.52$setupk4/!* 2006.285.14:43:37.52$setupk4/recpk4 2006.285.14:43:37.52$recpk4/recpatch= 2006.285.14:43:37.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.14:43:37.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.14:43:37.53$setupk4/vck44 2006.285.14:43:37.53$vck44/valo=1,524.99 2006.285.14:43:37.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.14:43:37.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.14:43:37.53#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:37.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:43:37.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:43:37.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:43:37.53#ibcon#enter wrdev, iclass 35, count 0 2006.285.14:43:37.53#ibcon#first serial, iclass 35, count 0 2006.285.14:43:37.53#ibcon#enter sib2, iclass 35, count 0 2006.285.14:43:37.53#ibcon#flushed, iclass 35, count 0 2006.285.14:43:37.53#ibcon#about to write, iclass 35, count 0 2006.285.14:43:37.53#ibcon#wrote, iclass 35, count 0 2006.285.14:43:37.53#ibcon#about to read 3, iclass 35, count 0 2006.285.14:43:37.54#ibcon#read 3, iclass 35, count 0 2006.285.14:43:37.54#ibcon#about to read 4, iclass 35, count 0 2006.285.14:43:37.54#ibcon#read 4, iclass 35, count 0 2006.285.14:43:37.55#ibcon#about to read 5, iclass 35, count 0 2006.285.14:43:37.55#ibcon#read 5, iclass 35, count 0 2006.285.14:43:37.55#ibcon#about to read 6, iclass 35, count 0 2006.285.14:43:37.55#ibcon#read 6, iclass 35, count 0 2006.285.14:43:37.55#ibcon#end of sib2, iclass 35, count 0 2006.285.14:43:37.55#ibcon#*mode == 0, iclass 35, count 0 2006.285.14:43:37.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.14:43:37.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.14:43:37.55#ibcon#*before write, iclass 35, count 0 2006.285.14:43:37.55#ibcon#enter sib2, iclass 35, count 0 2006.285.14:43:37.55#ibcon#flushed, iclass 35, count 0 2006.285.14:43:37.55#ibcon#about to write, iclass 35, count 0 2006.285.14:43:37.55#ibcon#wrote, iclass 35, count 0 2006.285.14:43:37.55#ibcon#about to read 3, iclass 35, count 0 2006.285.14:43:37.59#ibcon#read 3, iclass 35, count 0 2006.285.14:43:37.59#ibcon#about to read 4, iclass 35, count 0 2006.285.14:43:37.59#ibcon#read 4, iclass 35, count 0 2006.285.14:43:37.60#ibcon#about to read 5, iclass 35, count 0 2006.285.14:43:37.60#ibcon#read 5, iclass 35, count 0 2006.285.14:43:37.60#ibcon#about to read 6, iclass 35, count 0 2006.285.14:43:37.60#ibcon#read 6, iclass 35, count 0 2006.285.14:43:37.60#ibcon#end of sib2, iclass 35, count 0 2006.285.14:43:37.60#ibcon#*after write, iclass 35, count 0 2006.285.14:43:37.60#ibcon#*before return 0, iclass 35, count 0 2006.285.14:43:37.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:43:37.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:43:37.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.14:43:37.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.14:43:37.60$vck44/va=1,7 2006.285.14:43:37.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.14:43:37.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.14:43:37.60#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:37.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:43:37.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:43:37.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:43:37.60#ibcon#enter wrdev, iclass 37, count 2 2006.285.14:43:37.60#ibcon#first serial, iclass 37, count 2 2006.285.14:43:37.60#ibcon#enter sib2, iclass 37, count 2 2006.285.14:43:37.60#ibcon#flushed, iclass 37, count 2 2006.285.14:43:37.60#ibcon#about to write, iclass 37, count 2 2006.285.14:43:37.60#ibcon#wrote, iclass 37, count 2 2006.285.14:43:37.60#ibcon#about to read 3, iclass 37, count 2 2006.285.14:43:37.61#ibcon#read 3, iclass 37, count 2 2006.285.14:43:37.61#ibcon#about to read 4, iclass 37, count 2 2006.285.14:43:37.62#ibcon#read 4, iclass 37, count 2 2006.285.14:43:37.62#ibcon#about to read 5, iclass 37, count 2 2006.285.14:43:37.62#ibcon#read 5, iclass 37, count 2 2006.285.14:43:37.62#ibcon#about to read 6, iclass 37, count 2 2006.285.14:43:37.62#ibcon#read 6, iclass 37, count 2 2006.285.14:43:37.62#ibcon#end of sib2, iclass 37, count 2 2006.285.14:43:37.62#ibcon#*mode == 0, iclass 37, count 2 2006.285.14:43:37.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.14:43:37.62#ibcon#[25=AT01-07\r\n] 2006.285.14:43:37.62#ibcon#*before write, iclass 37, count 2 2006.285.14:43:37.62#ibcon#enter sib2, iclass 37, count 2 2006.285.14:43:37.62#ibcon#flushed, iclass 37, count 2 2006.285.14:43:37.62#ibcon#about to write, iclass 37, count 2 2006.285.14:43:37.62#ibcon#wrote, iclass 37, count 2 2006.285.14:43:37.62#ibcon#about to read 3, iclass 37, count 2 2006.285.14:43:37.64#ibcon#read 3, iclass 37, count 2 2006.285.14:43:37.64#ibcon#about to read 4, iclass 37, count 2 2006.285.14:43:37.64#ibcon#read 4, iclass 37, count 2 2006.285.14:43:37.65#ibcon#about to read 5, iclass 37, count 2 2006.285.14:43:37.65#ibcon#read 5, iclass 37, count 2 2006.285.14:43:37.65#ibcon#about to read 6, iclass 37, count 2 2006.285.14:43:37.65#ibcon#read 6, iclass 37, count 2 2006.285.14:43:37.65#ibcon#end of sib2, iclass 37, count 2 2006.285.14:43:37.65#ibcon#*after write, iclass 37, count 2 2006.285.14:43:37.65#ibcon#*before return 0, iclass 37, count 2 2006.285.14:43:37.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:43:37.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:43:37.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.14:43:37.65#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:37.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:43:37.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:43:37.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:43:37.77#ibcon#enter wrdev, iclass 37, count 0 2006.285.14:43:37.77#ibcon#first serial, iclass 37, count 0 2006.285.14:43:37.77#ibcon#enter sib2, iclass 37, count 0 2006.285.14:43:37.77#ibcon#flushed, iclass 37, count 0 2006.285.14:43:37.77#ibcon#about to write, iclass 37, count 0 2006.285.14:43:37.77#ibcon#wrote, iclass 37, count 0 2006.285.14:43:37.77#ibcon#about to read 3, iclass 37, count 0 2006.285.14:43:37.78#ibcon#read 3, iclass 37, count 0 2006.285.14:43:37.79#ibcon#about to read 4, iclass 37, count 0 2006.285.14:43:37.79#ibcon#read 4, iclass 37, count 0 2006.285.14:43:37.79#ibcon#about to read 5, iclass 37, count 0 2006.285.14:43:37.79#ibcon#read 5, iclass 37, count 0 2006.285.14:43:37.79#ibcon#about to read 6, iclass 37, count 0 2006.285.14:43:37.79#ibcon#read 6, iclass 37, count 0 2006.285.14:43:37.79#ibcon#end of sib2, iclass 37, count 0 2006.285.14:43:37.79#ibcon#*mode == 0, iclass 37, count 0 2006.285.14:43:37.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.14:43:37.79#ibcon#[25=USB\r\n] 2006.285.14:43:37.79#ibcon#*before write, iclass 37, count 0 2006.285.14:43:37.79#ibcon#enter sib2, iclass 37, count 0 2006.285.14:43:37.79#ibcon#flushed, iclass 37, count 0 2006.285.14:43:37.79#ibcon#about to write, iclass 37, count 0 2006.285.14:43:37.79#ibcon#wrote, iclass 37, count 0 2006.285.14:43:37.79#ibcon#about to read 3, iclass 37, count 0 2006.285.14:43:37.81#ibcon#read 3, iclass 37, count 0 2006.285.14:43:37.82#ibcon#about to read 4, iclass 37, count 0 2006.285.14:43:37.82#ibcon#read 4, iclass 37, count 0 2006.285.14:43:37.82#ibcon#about to read 5, iclass 37, count 0 2006.285.14:43:37.82#ibcon#read 5, iclass 37, count 0 2006.285.14:43:37.82#ibcon#about to read 6, iclass 37, count 0 2006.285.14:43:37.82#ibcon#read 6, iclass 37, count 0 2006.285.14:43:37.82#ibcon#end of sib2, iclass 37, count 0 2006.285.14:43:37.82#ibcon#*after write, iclass 37, count 0 2006.285.14:43:37.82#ibcon#*before return 0, iclass 37, count 0 2006.285.14:43:37.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:43:37.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:43:37.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.14:43:37.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.14:43:37.82$vck44/valo=2,534.99 2006.285.14:43:37.82#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.14:43:37.82#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.14:43:37.82#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:37.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:43:37.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:43:37.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:43:37.82#ibcon#enter wrdev, iclass 39, count 0 2006.285.14:43:37.82#ibcon#first serial, iclass 39, count 0 2006.285.14:43:37.82#ibcon#enter sib2, iclass 39, count 0 2006.285.14:43:37.82#ibcon#flushed, iclass 39, count 0 2006.285.14:43:37.82#ibcon#about to write, iclass 39, count 0 2006.285.14:43:37.82#ibcon#wrote, iclass 39, count 0 2006.285.14:43:37.82#ibcon#about to read 3, iclass 39, count 0 2006.285.14:43:37.83#ibcon#read 3, iclass 39, count 0 2006.285.14:43:38.38#ibcon#about to read 4, iclass 39, count 0 2006.285.14:43:38.38#ibcon#read 4, iclass 39, count 0 2006.285.14:43:38.38#ibcon#about to read 5, iclass 39, count 0 2006.285.14:43:38.38#ibcon#read 5, iclass 39, count 0 2006.285.14:43:38.38#ibcon#about to read 6, iclass 39, count 0 2006.285.14:43:38.38#ibcon#read 6, iclass 39, count 0 2006.285.14:43:38.38#ibcon#end of sib2, iclass 39, count 0 2006.285.14:43:38.38#ibcon#*mode == 0, iclass 39, count 0 2006.285.14:43:38.38#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.14:43:38.38#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.14:43:38.38#ibcon#*before write, iclass 39, count 0 2006.285.14:43:38.38#ibcon#enter sib2, iclass 39, count 0 2006.285.14:43:38.38#ibcon#flushed, iclass 39, count 0 2006.285.14:43:38.38#ibcon#about to write, iclass 39, count 0 2006.285.14:43:38.38#ibcon#wrote, iclass 39, count 0 2006.285.14:43:38.38#ibcon#about to read 3, iclass 39, count 0 2006.285.14:43:38.41#ibcon#read 3, iclass 39, count 0 2006.285.14:43:38.41#ibcon#about to read 4, iclass 39, count 0 2006.285.14:43:38.42#ibcon#read 4, iclass 39, count 0 2006.285.14:43:38.42#ibcon#about to read 5, iclass 39, count 0 2006.285.14:43:38.42#ibcon#read 5, iclass 39, count 0 2006.285.14:43:38.42#ibcon#about to read 6, iclass 39, count 0 2006.285.14:43:38.42#ibcon#read 6, iclass 39, count 0 2006.285.14:43:38.42#ibcon#end of sib2, iclass 39, count 0 2006.285.14:43:38.42#ibcon#*after write, iclass 39, count 0 2006.285.14:43:38.42#ibcon#*before return 0, iclass 39, count 0 2006.285.14:43:38.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:43:38.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:43:38.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.14:43:38.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.14:43:38.42$vck44/va=2,6 2006.285.14:43:38.42#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.14:43:38.42#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.14:43:38.42#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:38.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:43:38.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:43:38.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:43:38.42#ibcon#enter wrdev, iclass 3, count 2 2006.285.14:43:38.42#ibcon#first serial, iclass 3, count 2 2006.285.14:43:38.42#ibcon#enter sib2, iclass 3, count 2 2006.285.14:43:38.42#ibcon#flushed, iclass 3, count 2 2006.285.14:43:38.42#ibcon#about to write, iclass 3, count 2 2006.285.14:43:38.42#ibcon#wrote, iclass 3, count 2 2006.285.14:43:38.42#ibcon#about to read 3, iclass 3, count 2 2006.285.14:43:38.43#ibcon#read 3, iclass 3, count 2 2006.285.14:43:38.43#ibcon#about to read 4, iclass 3, count 2 2006.285.14:43:38.44#ibcon#read 4, iclass 3, count 2 2006.285.14:43:38.44#ibcon#about to read 5, iclass 3, count 2 2006.285.14:43:38.44#ibcon#read 5, iclass 3, count 2 2006.285.14:43:38.44#ibcon#about to read 6, iclass 3, count 2 2006.285.14:43:38.44#ibcon#read 6, iclass 3, count 2 2006.285.14:43:38.44#ibcon#end of sib2, iclass 3, count 2 2006.285.14:43:38.44#ibcon#*mode == 0, iclass 3, count 2 2006.285.14:43:38.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.14:43:38.44#ibcon#[25=AT02-06\r\n] 2006.285.14:43:38.44#ibcon#*before write, iclass 3, count 2 2006.285.14:43:38.44#ibcon#enter sib2, iclass 3, count 2 2006.285.14:43:38.44#ibcon#flushed, iclass 3, count 2 2006.285.14:43:38.44#ibcon#about to write, iclass 3, count 2 2006.285.14:43:38.44#ibcon#wrote, iclass 3, count 2 2006.285.14:43:38.44#ibcon#about to read 3, iclass 3, count 2 2006.285.14:43:38.46#ibcon#read 3, iclass 3, count 2 2006.285.14:43:38.46#ibcon#about to read 4, iclass 3, count 2 2006.285.14:43:38.47#ibcon#read 4, iclass 3, count 2 2006.285.14:43:38.47#ibcon#about to read 5, iclass 3, count 2 2006.285.14:43:38.47#ibcon#read 5, iclass 3, count 2 2006.285.14:43:38.47#ibcon#about to read 6, iclass 3, count 2 2006.285.14:43:38.47#ibcon#read 6, iclass 3, count 2 2006.285.14:43:38.47#ibcon#end of sib2, iclass 3, count 2 2006.285.14:43:38.47#ibcon#*after write, iclass 3, count 2 2006.285.14:43:38.47#ibcon#*before return 0, iclass 3, count 2 2006.285.14:43:38.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:43:38.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:43:38.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.14:43:38.47#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:38.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:43:38.58#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:43:38.58#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:43:38.59#ibcon#enter wrdev, iclass 3, count 0 2006.285.14:43:38.59#ibcon#first serial, iclass 3, count 0 2006.285.14:43:38.59#ibcon#enter sib2, iclass 3, count 0 2006.285.14:43:38.59#ibcon#flushed, iclass 3, count 0 2006.285.14:43:38.59#ibcon#about to write, iclass 3, count 0 2006.285.14:43:38.59#ibcon#wrote, iclass 3, count 0 2006.285.14:43:38.59#ibcon#about to read 3, iclass 3, count 0 2006.285.14:43:38.60#ibcon#read 3, iclass 3, count 0 2006.285.14:43:38.60#ibcon#about to read 4, iclass 3, count 0 2006.285.14:43:38.61#ibcon#read 4, iclass 3, count 0 2006.285.14:43:38.61#ibcon#about to read 5, iclass 3, count 0 2006.285.14:43:38.61#ibcon#read 5, iclass 3, count 0 2006.285.14:43:38.61#ibcon#about to read 6, iclass 3, count 0 2006.285.14:43:38.61#ibcon#read 6, iclass 3, count 0 2006.285.14:43:38.61#ibcon#end of sib2, iclass 3, count 0 2006.285.14:43:38.61#ibcon#*mode == 0, iclass 3, count 0 2006.285.14:43:38.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.14:43:38.61#ibcon#[25=USB\r\n] 2006.285.14:43:38.61#ibcon#*before write, iclass 3, count 0 2006.285.14:43:38.61#ibcon#enter sib2, iclass 3, count 0 2006.285.14:43:38.61#ibcon#flushed, iclass 3, count 0 2006.285.14:43:38.61#ibcon#about to write, iclass 3, count 0 2006.285.14:43:38.61#ibcon#wrote, iclass 3, count 0 2006.285.14:43:38.61#ibcon#about to read 3, iclass 3, count 0 2006.285.14:43:38.63#ibcon#read 3, iclass 3, count 0 2006.285.14:43:38.64#ibcon#about to read 4, iclass 3, count 0 2006.285.14:43:38.64#ibcon#read 4, iclass 3, count 0 2006.285.14:43:38.64#ibcon#about to read 5, iclass 3, count 0 2006.285.14:43:38.64#ibcon#read 5, iclass 3, count 0 2006.285.14:43:38.64#ibcon#about to read 6, iclass 3, count 0 2006.285.14:43:38.64#ibcon#read 6, iclass 3, count 0 2006.285.14:43:38.64#ibcon#end of sib2, iclass 3, count 0 2006.285.14:43:38.64#ibcon#*after write, iclass 3, count 0 2006.285.14:43:38.64#ibcon#*before return 0, iclass 3, count 0 2006.285.14:43:38.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:43:38.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:43:38.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.14:43:38.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.14:43:38.64$vck44/valo=3,564.99 2006.285.14:43:38.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.14:43:38.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.14:43:38.64#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:38.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:43:38.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:43:38.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:43:38.64#ibcon#enter wrdev, iclass 5, count 0 2006.285.14:43:38.64#ibcon#first serial, iclass 5, count 0 2006.285.14:43:38.64#ibcon#enter sib2, iclass 5, count 0 2006.285.14:43:38.64#ibcon#flushed, iclass 5, count 0 2006.285.14:43:38.64#ibcon#about to write, iclass 5, count 0 2006.285.14:43:38.64#ibcon#wrote, iclass 5, count 0 2006.285.14:43:38.64#ibcon#about to read 3, iclass 5, count 0 2006.285.14:43:38.65#ibcon#read 3, iclass 5, count 0 2006.285.14:43:38.69#ibcon#about to read 4, iclass 5, count 0 2006.285.14:43:38.69#ibcon#read 4, iclass 5, count 0 2006.285.14:43:38.69#ibcon#about to read 5, iclass 5, count 0 2006.285.14:43:38.69#ibcon#read 5, iclass 5, count 0 2006.285.14:43:38.69#ibcon#about to read 6, iclass 5, count 0 2006.285.14:43:38.69#ibcon#read 6, iclass 5, count 0 2006.285.14:43:38.69#ibcon#end of sib2, iclass 5, count 0 2006.285.14:43:38.69#ibcon#*mode == 0, iclass 5, count 0 2006.285.14:43:38.69#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.14:43:38.69#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.14:43:38.69#ibcon#*before write, iclass 5, count 0 2006.285.14:43:38.69#ibcon#enter sib2, iclass 5, count 0 2006.285.14:43:38.69#ibcon#flushed, iclass 5, count 0 2006.285.14:43:38.69#ibcon#about to write, iclass 5, count 0 2006.285.14:43:38.69#ibcon#wrote, iclass 5, count 0 2006.285.14:43:38.69#ibcon#about to read 3, iclass 5, count 0 2006.285.14:43:38.73#ibcon#read 3, iclass 5, count 0 2006.285.14:43:38.74#ibcon#about to read 4, iclass 5, count 0 2006.285.14:43:38.74#ibcon#read 4, iclass 5, count 0 2006.285.14:43:38.74#ibcon#about to read 5, iclass 5, count 0 2006.285.14:43:38.74#ibcon#read 5, iclass 5, count 0 2006.285.14:43:38.74#ibcon#about to read 6, iclass 5, count 0 2006.285.14:43:38.74#ibcon#read 6, iclass 5, count 0 2006.285.14:43:38.74#ibcon#end of sib2, iclass 5, count 0 2006.285.14:43:38.74#ibcon#*after write, iclass 5, count 0 2006.285.14:43:38.74#ibcon#*before return 0, iclass 5, count 0 2006.285.14:43:38.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:43:38.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.14:43:38.74#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.14:43:38.74#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.14:43:38.74$vck44/va=3,7 2006.285.14:43:38.74#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.14:43:38.74#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.14:43:38.74#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:38.74#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:43:38.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:43:38.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:43:38.76#ibcon#enter wrdev, iclass 7, count 2 2006.285.14:43:38.76#ibcon#first serial, iclass 7, count 2 2006.285.14:43:38.76#ibcon#enter sib2, iclass 7, count 2 2006.285.14:43:38.76#ibcon#flushed, iclass 7, count 2 2006.285.14:43:38.76#ibcon#about to write, iclass 7, count 2 2006.285.14:43:38.76#ibcon#wrote, iclass 7, count 2 2006.285.14:43:38.76#ibcon#about to read 3, iclass 7, count 2 2006.285.14:43:38.77#ibcon#read 3, iclass 7, count 2 2006.285.14:43:38.77#ibcon#about to read 4, iclass 7, count 2 2006.285.14:43:38.78#ibcon#read 4, iclass 7, count 2 2006.285.14:43:38.78#ibcon#about to read 5, iclass 7, count 2 2006.285.14:43:38.78#ibcon#read 5, iclass 7, count 2 2006.285.14:43:38.78#ibcon#about to read 6, iclass 7, count 2 2006.285.14:43:38.78#ibcon#read 6, iclass 7, count 2 2006.285.14:43:38.78#ibcon#end of sib2, iclass 7, count 2 2006.285.14:43:38.78#ibcon#*mode == 0, iclass 7, count 2 2006.285.14:43:38.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.14:43:38.78#ibcon#[25=AT03-07\r\n] 2006.285.14:43:38.78#ibcon#*before write, iclass 7, count 2 2006.285.14:43:38.78#ibcon#enter sib2, iclass 7, count 2 2006.285.14:43:38.78#ibcon#flushed, iclass 7, count 2 2006.285.14:43:38.78#ibcon#about to write, iclass 7, count 2 2006.285.14:43:38.78#ibcon#wrote, iclass 7, count 2 2006.285.14:43:38.78#ibcon#about to read 3, iclass 7, count 2 2006.285.14:43:38.80#ibcon#read 3, iclass 7, count 2 2006.285.14:43:38.80#ibcon#about to read 4, iclass 7, count 2 2006.285.14:43:38.81#ibcon#read 4, iclass 7, count 2 2006.285.14:43:38.81#ibcon#about to read 5, iclass 7, count 2 2006.285.14:43:38.81#ibcon#read 5, iclass 7, count 2 2006.285.14:43:38.81#ibcon#about to read 6, iclass 7, count 2 2006.285.14:43:38.81#ibcon#read 6, iclass 7, count 2 2006.285.14:43:38.81#ibcon#end of sib2, iclass 7, count 2 2006.285.14:43:38.81#ibcon#*after write, iclass 7, count 2 2006.285.14:43:38.81#ibcon#*before return 0, iclass 7, count 2 2006.285.14:43:38.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:43:38.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.14:43:38.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.14:43:38.81#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:38.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:43:38.92#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:43:38.92#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:43:38.93#ibcon#enter wrdev, iclass 7, count 0 2006.285.14:43:38.93#ibcon#first serial, iclass 7, count 0 2006.285.14:43:38.93#ibcon#enter sib2, iclass 7, count 0 2006.285.14:43:38.93#ibcon#flushed, iclass 7, count 0 2006.285.14:43:38.93#ibcon#about to write, iclass 7, count 0 2006.285.14:43:38.93#ibcon#wrote, iclass 7, count 0 2006.285.14:43:38.93#ibcon#about to read 3, iclass 7, count 0 2006.285.14:43:38.94#ibcon#read 3, iclass 7, count 0 2006.285.14:43:38.94#ibcon#about to read 4, iclass 7, count 0 2006.285.14:43:38.95#ibcon#read 4, iclass 7, count 0 2006.285.14:43:38.95#ibcon#about to read 5, iclass 7, count 0 2006.285.14:43:38.95#ibcon#read 5, iclass 7, count 0 2006.285.14:43:38.95#ibcon#about to read 6, iclass 7, count 0 2006.285.14:43:38.95#ibcon#read 6, iclass 7, count 0 2006.285.14:43:38.95#ibcon#end of sib2, iclass 7, count 0 2006.285.14:43:38.95#ibcon#*mode == 0, iclass 7, count 0 2006.285.14:43:38.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.14:43:38.95#ibcon#[25=USB\r\n] 2006.285.14:43:38.95#ibcon#*before write, iclass 7, count 0 2006.285.14:43:38.95#ibcon#enter sib2, iclass 7, count 0 2006.285.14:43:38.95#ibcon#flushed, iclass 7, count 0 2006.285.14:43:38.95#ibcon#about to write, iclass 7, count 0 2006.285.14:43:38.95#ibcon#wrote, iclass 7, count 0 2006.285.14:43:38.95#ibcon#about to read 3, iclass 7, count 0 2006.285.14:43:38.97#ibcon#read 3, iclass 7, count 0 2006.285.14:43:38.97#ibcon#about to read 4, iclass 7, count 0 2006.285.14:43:38.98#ibcon#read 4, iclass 7, count 0 2006.285.14:43:38.98#ibcon#about to read 5, iclass 7, count 0 2006.285.14:43:38.98#ibcon#read 5, iclass 7, count 0 2006.285.14:43:38.98#ibcon#about to read 6, iclass 7, count 0 2006.285.14:43:38.98#ibcon#read 6, iclass 7, count 0 2006.285.14:43:38.98#ibcon#end of sib2, iclass 7, count 0 2006.285.14:43:38.98#ibcon#*after write, iclass 7, count 0 2006.285.14:43:38.98#ibcon#*before return 0, iclass 7, count 0 2006.285.14:43:38.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:43:38.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.14:43:38.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.14:43:38.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.14:43:38.98$vck44/valo=4,624.99 2006.285.14:43:38.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.14:43:38.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.14:43:38.98#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:38.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:43:38.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:43:38.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:43:38.98#ibcon#enter wrdev, iclass 11, count 0 2006.285.14:43:38.98#ibcon#first serial, iclass 11, count 0 2006.285.14:43:38.98#ibcon#enter sib2, iclass 11, count 0 2006.285.14:43:38.98#ibcon#flushed, iclass 11, count 0 2006.285.14:43:38.98#ibcon#about to write, iclass 11, count 0 2006.285.14:43:38.98#ibcon#wrote, iclass 11, count 0 2006.285.14:43:38.98#ibcon#about to read 3, iclass 11, count 0 2006.285.14:43:38.99#ibcon#read 3, iclass 11, count 0 2006.285.14:43:38.99#ibcon#about to read 4, iclass 11, count 0 2006.285.14:43:39.00#ibcon#read 4, iclass 11, count 0 2006.285.14:43:39.00#ibcon#about to read 5, iclass 11, count 0 2006.285.14:43:39.00#ibcon#read 5, iclass 11, count 0 2006.285.14:43:39.00#ibcon#about to read 6, iclass 11, count 0 2006.285.14:43:39.00#ibcon#read 6, iclass 11, count 0 2006.285.14:43:39.00#ibcon#end of sib2, iclass 11, count 0 2006.285.14:43:39.00#ibcon#*mode == 0, iclass 11, count 0 2006.285.14:43:39.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.14:43:39.00#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.14:43:39.00#ibcon#*before write, iclass 11, count 0 2006.285.14:43:39.00#ibcon#enter sib2, iclass 11, count 0 2006.285.14:43:39.00#ibcon#flushed, iclass 11, count 0 2006.285.14:43:39.00#ibcon#about to write, iclass 11, count 0 2006.285.14:43:39.00#ibcon#wrote, iclass 11, count 0 2006.285.14:43:39.00#ibcon#about to read 3, iclass 11, count 0 2006.285.14:43:39.03#ibcon#read 3, iclass 11, count 0 2006.285.14:43:39.03#ibcon#about to read 4, iclass 11, count 0 2006.285.14:43:39.04#ibcon#read 4, iclass 11, count 0 2006.285.14:43:39.04#ibcon#about to read 5, iclass 11, count 0 2006.285.14:43:39.04#ibcon#read 5, iclass 11, count 0 2006.285.14:43:39.04#ibcon#about to read 6, iclass 11, count 0 2006.285.14:43:39.04#ibcon#read 6, iclass 11, count 0 2006.285.14:43:39.04#ibcon#end of sib2, iclass 11, count 0 2006.285.14:43:39.04#ibcon#*after write, iclass 11, count 0 2006.285.14:43:39.04#ibcon#*before return 0, iclass 11, count 0 2006.285.14:43:39.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:43:39.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:43:39.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.14:43:39.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.14:43:39.04$vck44/va=4,6 2006.285.14:43:39.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.14:43:39.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.14:43:39.04#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:39.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:43:39.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:43:39.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:43:39.09#ibcon#enter wrdev, iclass 13, count 2 2006.285.14:43:39.10#ibcon#first serial, iclass 13, count 2 2006.285.14:43:39.10#ibcon#enter sib2, iclass 13, count 2 2006.285.14:43:39.10#ibcon#flushed, iclass 13, count 2 2006.285.14:43:39.10#ibcon#about to write, iclass 13, count 2 2006.285.14:43:39.10#ibcon#wrote, iclass 13, count 2 2006.285.14:43:39.10#ibcon#about to read 3, iclass 13, count 2 2006.285.14:43:39.11#ibcon#read 3, iclass 13, count 2 2006.285.14:43:39.11#ibcon#about to read 4, iclass 13, count 2 2006.285.14:43:39.11#ibcon#read 4, iclass 13, count 2 2006.285.14:43:39.11#ibcon#about to read 5, iclass 13, count 2 2006.285.14:43:39.12#ibcon#read 5, iclass 13, count 2 2006.285.14:43:39.12#ibcon#about to read 6, iclass 13, count 2 2006.285.14:43:39.12#ibcon#read 6, iclass 13, count 2 2006.285.14:43:39.12#ibcon#end of sib2, iclass 13, count 2 2006.285.14:43:39.12#ibcon#*mode == 0, iclass 13, count 2 2006.285.14:43:39.12#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.14:43:39.12#ibcon#[25=AT04-06\r\n] 2006.285.14:43:39.12#ibcon#*before write, iclass 13, count 2 2006.285.14:43:39.12#ibcon#enter sib2, iclass 13, count 2 2006.285.14:43:39.12#ibcon#flushed, iclass 13, count 2 2006.285.14:43:39.12#ibcon#about to write, iclass 13, count 2 2006.285.14:43:39.12#ibcon#wrote, iclass 13, count 2 2006.285.14:43:39.12#ibcon#about to read 3, iclass 13, count 2 2006.285.14:43:39.14#ibcon#read 3, iclass 13, count 2 2006.285.14:43:39.14#ibcon#about to read 4, iclass 13, count 2 2006.285.14:43:39.14#ibcon#read 4, iclass 13, count 2 2006.285.14:43:39.15#ibcon#about to read 5, iclass 13, count 2 2006.285.14:43:39.15#ibcon#read 5, iclass 13, count 2 2006.285.14:43:39.15#ibcon#about to read 6, iclass 13, count 2 2006.285.14:43:39.15#ibcon#read 6, iclass 13, count 2 2006.285.14:43:39.15#ibcon#end of sib2, iclass 13, count 2 2006.285.14:43:39.15#ibcon#*after write, iclass 13, count 2 2006.285.14:43:39.15#ibcon#*before return 0, iclass 13, count 2 2006.285.14:43:39.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:43:39.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:43:39.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.14:43:39.15#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:39.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:43:39.26#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:43:39.26#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:43:39.26#ibcon#enter wrdev, iclass 13, count 0 2006.285.14:43:39.27#ibcon#first serial, iclass 13, count 0 2006.285.14:43:39.27#ibcon#enter sib2, iclass 13, count 0 2006.285.14:43:39.27#ibcon#flushed, iclass 13, count 0 2006.285.14:43:39.27#ibcon#about to write, iclass 13, count 0 2006.285.14:43:39.27#ibcon#wrote, iclass 13, count 0 2006.285.14:43:39.27#ibcon#about to read 3, iclass 13, count 0 2006.285.14:43:39.28#ibcon#read 3, iclass 13, count 0 2006.285.14:43:39.28#ibcon#about to read 4, iclass 13, count 0 2006.285.14:43:39.28#ibcon#read 4, iclass 13, count 0 2006.285.14:43:39.28#ibcon#about to read 5, iclass 13, count 0 2006.285.14:43:39.29#ibcon#read 5, iclass 13, count 0 2006.285.14:43:39.29#ibcon#about to read 6, iclass 13, count 0 2006.285.14:43:39.29#ibcon#read 6, iclass 13, count 0 2006.285.14:43:39.29#ibcon#end of sib2, iclass 13, count 0 2006.285.14:43:39.29#ibcon#*mode == 0, iclass 13, count 0 2006.285.14:43:39.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.14:43:39.29#ibcon#[25=USB\r\n] 2006.285.14:43:39.29#ibcon#*before write, iclass 13, count 0 2006.285.14:43:39.29#ibcon#enter sib2, iclass 13, count 0 2006.285.14:43:39.29#ibcon#flushed, iclass 13, count 0 2006.285.14:43:39.29#ibcon#about to write, iclass 13, count 0 2006.285.14:43:39.29#ibcon#wrote, iclass 13, count 0 2006.285.14:43:39.29#ibcon#about to read 3, iclass 13, count 0 2006.285.14:43:39.31#ibcon#read 3, iclass 13, count 0 2006.285.14:43:39.31#ibcon#about to read 4, iclass 13, count 0 2006.285.14:43:39.31#ibcon#read 4, iclass 13, count 0 2006.285.14:43:39.31#ibcon#about to read 5, iclass 13, count 0 2006.285.14:43:39.32#ibcon#read 5, iclass 13, count 0 2006.285.14:43:39.32#ibcon#about to read 6, iclass 13, count 0 2006.285.14:43:39.32#ibcon#read 6, iclass 13, count 0 2006.285.14:43:39.32#ibcon#end of sib2, iclass 13, count 0 2006.285.14:43:39.32#ibcon#*after write, iclass 13, count 0 2006.285.14:43:39.32#ibcon#*before return 0, iclass 13, count 0 2006.285.14:43:39.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:43:39.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:43:39.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.14:43:39.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.14:43:39.32$vck44/valo=5,734.99 2006.285.14:43:39.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.14:43:39.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.14:43:39.32#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:39.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:43:39.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:43:39.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:43:39.32#ibcon#enter wrdev, iclass 15, count 0 2006.285.14:43:39.32#ibcon#first serial, iclass 15, count 0 2006.285.14:43:39.32#ibcon#enter sib2, iclass 15, count 0 2006.285.14:43:39.32#ibcon#flushed, iclass 15, count 0 2006.285.14:43:39.32#ibcon#about to write, iclass 15, count 0 2006.285.14:43:39.32#ibcon#wrote, iclass 15, count 0 2006.285.14:43:39.32#ibcon#about to read 3, iclass 15, count 0 2006.285.14:43:39.33#ibcon#read 3, iclass 15, count 0 2006.285.14:43:39.33#ibcon#about to read 4, iclass 15, count 0 2006.285.14:43:39.33#ibcon#read 4, iclass 15, count 0 2006.285.14:43:39.34#ibcon#about to read 5, iclass 15, count 0 2006.285.14:43:39.34#ibcon#read 5, iclass 15, count 0 2006.285.14:43:39.34#ibcon#about to read 6, iclass 15, count 0 2006.285.14:43:39.34#ibcon#read 6, iclass 15, count 0 2006.285.14:43:39.34#ibcon#end of sib2, iclass 15, count 0 2006.285.14:43:39.34#ibcon#*mode == 0, iclass 15, count 0 2006.285.14:43:39.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.14:43:39.34#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.14:43:39.34#ibcon#*before write, iclass 15, count 0 2006.285.14:43:39.34#ibcon#enter sib2, iclass 15, count 0 2006.285.14:43:39.34#ibcon#flushed, iclass 15, count 0 2006.285.14:43:39.34#ibcon#about to write, iclass 15, count 0 2006.285.14:43:39.34#ibcon#wrote, iclass 15, count 0 2006.285.14:43:39.34#ibcon#about to read 3, iclass 15, count 0 2006.285.14:43:39.37#ibcon#read 3, iclass 15, count 0 2006.285.14:43:39.37#ibcon#about to read 4, iclass 15, count 0 2006.285.14:43:39.37#ibcon#read 4, iclass 15, count 0 2006.285.14:43:39.37#ibcon#about to read 5, iclass 15, count 0 2006.285.14:43:39.38#ibcon#read 5, iclass 15, count 0 2006.285.14:43:39.38#ibcon#about to read 6, iclass 15, count 0 2006.285.14:43:39.38#ibcon#read 6, iclass 15, count 0 2006.285.14:43:39.38#ibcon#end of sib2, iclass 15, count 0 2006.285.14:43:39.38#ibcon#*after write, iclass 15, count 0 2006.285.14:43:39.38#ibcon#*before return 0, iclass 15, count 0 2006.285.14:43:39.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:43:39.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:43:39.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.14:43:39.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.14:43:39.38$vck44/va=5,3 2006.285.14:43:39.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.14:43:39.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.14:43:39.38#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:39.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:43:39.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:43:39.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:43:39.43#ibcon#enter wrdev, iclass 17, count 2 2006.285.14:43:39.43#ibcon#first serial, iclass 17, count 2 2006.285.14:43:39.44#ibcon#enter sib2, iclass 17, count 2 2006.285.14:43:39.44#ibcon#flushed, iclass 17, count 2 2006.285.14:43:39.44#ibcon#about to write, iclass 17, count 2 2006.285.14:43:39.44#ibcon#wrote, iclass 17, count 2 2006.285.14:43:39.44#ibcon#about to read 3, iclass 17, count 2 2006.285.14:43:39.45#ibcon#read 3, iclass 17, count 2 2006.285.14:43:39.45#ibcon#about to read 4, iclass 17, count 2 2006.285.14:43:39.45#ibcon#read 4, iclass 17, count 2 2006.285.14:43:39.45#ibcon#about to read 5, iclass 17, count 2 2006.285.14:43:39.46#ibcon#read 5, iclass 17, count 2 2006.285.14:43:39.46#ibcon#about to read 6, iclass 17, count 2 2006.285.14:43:39.46#ibcon#read 6, iclass 17, count 2 2006.285.14:43:39.46#ibcon#end of sib2, iclass 17, count 2 2006.285.14:43:39.46#ibcon#*mode == 0, iclass 17, count 2 2006.285.14:43:39.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.14:43:39.46#ibcon#[25=AT05-03\r\n] 2006.285.14:43:39.46#ibcon#*before write, iclass 17, count 2 2006.285.14:43:39.46#ibcon#enter sib2, iclass 17, count 2 2006.285.14:43:39.46#ibcon#flushed, iclass 17, count 2 2006.285.14:43:39.46#ibcon#about to write, iclass 17, count 2 2006.285.14:43:39.46#ibcon#wrote, iclass 17, count 2 2006.285.14:43:39.46#ibcon#about to read 3, iclass 17, count 2 2006.285.14:43:39.48#ibcon#read 3, iclass 17, count 2 2006.285.14:43:39.48#ibcon#about to read 4, iclass 17, count 2 2006.285.14:43:39.48#ibcon#read 4, iclass 17, count 2 2006.285.14:43:39.48#ibcon#about to read 5, iclass 17, count 2 2006.285.14:43:39.49#ibcon#read 5, iclass 17, count 2 2006.285.14:43:39.49#ibcon#about to read 6, iclass 17, count 2 2006.285.14:43:39.49#ibcon#read 6, iclass 17, count 2 2006.285.14:43:39.49#ibcon#end of sib2, iclass 17, count 2 2006.285.14:43:39.49#ibcon#*after write, iclass 17, count 2 2006.285.14:43:39.49#ibcon#*before return 0, iclass 17, count 2 2006.285.14:43:39.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:43:39.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:43:39.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.14:43:39.49#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:39.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:43:39.60#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:43:39.60#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:43:39.60#ibcon#enter wrdev, iclass 17, count 0 2006.285.14:43:39.60#ibcon#first serial, iclass 17, count 0 2006.285.14:43:39.61#ibcon#enter sib2, iclass 17, count 0 2006.285.14:43:39.61#ibcon#flushed, iclass 17, count 0 2006.285.14:43:39.61#ibcon#about to write, iclass 17, count 0 2006.285.14:43:39.61#ibcon#wrote, iclass 17, count 0 2006.285.14:43:39.61#ibcon#about to read 3, iclass 17, count 0 2006.285.14:43:39.62#ibcon#read 3, iclass 17, count 0 2006.285.14:43:39.62#ibcon#about to read 4, iclass 17, count 0 2006.285.14:43:39.62#ibcon#read 4, iclass 17, count 0 2006.285.14:43:39.62#ibcon#about to read 5, iclass 17, count 0 2006.285.14:43:39.63#ibcon#read 5, iclass 17, count 0 2006.285.14:43:39.63#ibcon#about to read 6, iclass 17, count 0 2006.285.14:43:39.63#ibcon#read 6, iclass 17, count 0 2006.285.14:43:39.63#ibcon#end of sib2, iclass 17, count 0 2006.285.14:43:39.63#ibcon#*mode == 0, iclass 17, count 0 2006.285.14:43:39.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.14:43:39.63#ibcon#[25=USB\r\n] 2006.285.14:43:39.63#ibcon#*before write, iclass 17, count 0 2006.285.14:43:39.63#ibcon#enter sib2, iclass 17, count 0 2006.285.14:43:39.63#ibcon#flushed, iclass 17, count 0 2006.285.14:43:39.63#ibcon#about to write, iclass 17, count 0 2006.285.14:43:39.63#ibcon#wrote, iclass 17, count 0 2006.285.14:43:39.63#ibcon#about to read 3, iclass 17, count 0 2006.285.14:43:39.65#ibcon#read 3, iclass 17, count 0 2006.285.14:43:39.65#ibcon#about to read 4, iclass 17, count 0 2006.285.14:43:39.65#ibcon#read 4, iclass 17, count 0 2006.285.14:43:39.65#ibcon#about to read 5, iclass 17, count 0 2006.285.14:43:39.66#ibcon#read 5, iclass 17, count 0 2006.285.14:43:39.66#ibcon#about to read 6, iclass 17, count 0 2006.285.14:43:39.66#ibcon#read 6, iclass 17, count 0 2006.285.14:43:39.66#ibcon#end of sib2, iclass 17, count 0 2006.285.14:43:39.66#ibcon#*after write, iclass 17, count 0 2006.285.14:43:39.66#ibcon#*before return 0, iclass 17, count 0 2006.285.14:43:39.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:43:39.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:43:39.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.14:43:39.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.14:43:39.66$vck44/valo=6,814.99 2006.285.14:43:39.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.14:43:39.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.14:43:39.66#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:39.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:43:39.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:43:39.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:43:39.66#ibcon#enter wrdev, iclass 19, count 0 2006.285.14:43:39.66#ibcon#first serial, iclass 19, count 0 2006.285.14:43:39.66#ibcon#enter sib2, iclass 19, count 0 2006.285.14:43:39.66#ibcon#flushed, iclass 19, count 0 2006.285.14:43:39.66#ibcon#about to write, iclass 19, count 0 2006.285.14:43:39.66#ibcon#wrote, iclass 19, count 0 2006.285.14:43:39.66#ibcon#about to read 3, iclass 19, count 0 2006.285.14:43:39.67#ibcon#read 3, iclass 19, count 0 2006.285.14:43:39.67#ibcon#about to read 4, iclass 19, count 0 2006.285.14:43:39.67#ibcon#read 4, iclass 19, count 0 2006.285.14:43:39.68#ibcon#about to read 5, iclass 19, count 0 2006.285.14:43:39.68#ibcon#read 5, iclass 19, count 0 2006.285.14:43:39.68#ibcon#about to read 6, iclass 19, count 0 2006.285.14:43:39.68#ibcon#read 6, iclass 19, count 0 2006.285.14:43:39.68#ibcon#end of sib2, iclass 19, count 0 2006.285.14:43:39.68#ibcon#*mode == 0, iclass 19, count 0 2006.285.14:43:39.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.14:43:39.68#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.14:43:39.68#ibcon#*before write, iclass 19, count 0 2006.285.14:43:39.68#ibcon#enter sib2, iclass 19, count 0 2006.285.14:43:39.68#ibcon#flushed, iclass 19, count 0 2006.285.14:43:39.68#ibcon#about to write, iclass 19, count 0 2006.285.14:43:39.68#ibcon#wrote, iclass 19, count 0 2006.285.14:43:39.68#ibcon#about to read 3, iclass 19, count 0 2006.285.14:43:39.71#ibcon#read 3, iclass 19, count 0 2006.285.14:43:39.71#ibcon#about to read 4, iclass 19, count 0 2006.285.14:43:39.71#ibcon#read 4, iclass 19, count 0 2006.285.14:43:39.71#ibcon#about to read 5, iclass 19, count 0 2006.285.14:43:39.72#ibcon#read 5, iclass 19, count 0 2006.285.14:43:39.72#ibcon#about to read 6, iclass 19, count 0 2006.285.14:43:39.72#ibcon#read 6, iclass 19, count 0 2006.285.14:43:39.72#ibcon#end of sib2, iclass 19, count 0 2006.285.14:43:39.72#ibcon#*after write, iclass 19, count 0 2006.285.14:43:39.72#ibcon#*before return 0, iclass 19, count 0 2006.285.14:43:39.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:43:39.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:43:39.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.14:43:39.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.14:43:39.72$vck44/va=6,4 2006.285.14:43:39.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.14:43:39.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.14:43:39.72#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:39.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:43:39.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:43:39.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:43:39.78#ibcon#enter wrdev, iclass 21, count 2 2006.285.14:43:39.78#ibcon#first serial, iclass 21, count 2 2006.285.14:43:39.78#ibcon#enter sib2, iclass 21, count 2 2006.285.14:43:39.78#ibcon#flushed, iclass 21, count 2 2006.285.14:43:39.78#ibcon#about to write, iclass 21, count 2 2006.285.14:43:39.78#ibcon#wrote, iclass 21, count 2 2006.285.14:43:39.78#ibcon#about to read 3, iclass 21, count 2 2006.285.14:43:39.79#ibcon#read 3, iclass 21, count 2 2006.285.14:43:39.79#ibcon#about to read 4, iclass 21, count 2 2006.285.14:43:39.80#ibcon#read 4, iclass 21, count 2 2006.285.14:43:39.80#ibcon#about to read 5, iclass 21, count 2 2006.285.14:43:39.80#ibcon#read 5, iclass 21, count 2 2006.285.14:43:39.80#ibcon#about to read 6, iclass 21, count 2 2006.285.14:43:39.80#ibcon#read 6, iclass 21, count 2 2006.285.14:43:39.80#ibcon#end of sib2, iclass 21, count 2 2006.285.14:43:39.80#ibcon#*mode == 0, iclass 21, count 2 2006.285.14:43:39.80#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.14:43:39.80#ibcon#[25=AT06-04\r\n] 2006.285.14:43:39.80#ibcon#*before write, iclass 21, count 2 2006.285.14:43:39.80#ibcon#enter sib2, iclass 21, count 2 2006.285.14:43:39.80#ibcon#flushed, iclass 21, count 2 2006.285.14:43:39.80#ibcon#about to write, iclass 21, count 2 2006.285.14:43:39.80#ibcon#wrote, iclass 21, count 2 2006.285.14:43:39.80#ibcon#about to read 3, iclass 21, count 2 2006.285.14:43:39.82#ibcon#read 3, iclass 21, count 2 2006.285.14:43:39.83#ibcon#about to read 4, iclass 21, count 2 2006.285.14:43:39.83#ibcon#read 4, iclass 21, count 2 2006.285.14:43:39.83#ibcon#about to read 5, iclass 21, count 2 2006.285.14:43:39.83#ibcon#read 5, iclass 21, count 2 2006.285.14:43:39.83#ibcon#about to read 6, iclass 21, count 2 2006.285.14:43:39.83#ibcon#read 6, iclass 21, count 2 2006.285.14:43:39.83#ibcon#end of sib2, iclass 21, count 2 2006.285.14:43:39.83#ibcon#*after write, iclass 21, count 2 2006.285.14:43:39.83#ibcon#*before return 0, iclass 21, count 2 2006.285.14:43:39.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:43:39.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:43:39.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.14:43:39.83#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:39.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:43:39.94#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:43:40.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:43:40.14#ibcon#enter wrdev, iclass 21, count 0 2006.285.14:43:40.14#ibcon#first serial, iclass 21, count 0 2006.285.14:43:40.14#ibcon#enter sib2, iclass 21, count 0 2006.285.14:43:40.14#ibcon#flushed, iclass 21, count 0 2006.285.14:43:40.14#ibcon#about to write, iclass 21, count 0 2006.285.14:43:40.14#ibcon#wrote, iclass 21, count 0 2006.285.14:43:40.14#ibcon#about to read 3, iclass 21, count 0 2006.285.14:43:40.15#ibcon#read 3, iclass 21, count 0 2006.285.14:43:40.16#ibcon#about to read 4, iclass 21, count 0 2006.285.14:43:40.16#ibcon#read 4, iclass 21, count 0 2006.285.14:43:40.16#ibcon#about to read 5, iclass 21, count 0 2006.285.14:43:40.16#ibcon#read 5, iclass 21, count 0 2006.285.14:43:40.16#ibcon#about to read 6, iclass 21, count 0 2006.285.14:43:40.16#ibcon#read 6, iclass 21, count 0 2006.285.14:43:40.16#ibcon#end of sib2, iclass 21, count 0 2006.285.14:43:40.16#ibcon#*mode == 0, iclass 21, count 0 2006.285.14:43:40.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.14:43:40.16#ibcon#[25=USB\r\n] 2006.285.14:43:40.16#ibcon#*before write, iclass 21, count 0 2006.285.14:43:40.16#ibcon#enter sib2, iclass 21, count 0 2006.285.14:43:40.16#ibcon#flushed, iclass 21, count 0 2006.285.14:43:40.16#ibcon#about to write, iclass 21, count 0 2006.285.14:43:40.16#ibcon#wrote, iclass 21, count 0 2006.285.14:43:40.16#ibcon#about to read 3, iclass 21, count 0 2006.285.14:43:40.18#ibcon#read 3, iclass 21, count 0 2006.285.14:43:40.18#ibcon#about to read 4, iclass 21, count 0 2006.285.14:43:40.19#ibcon#read 4, iclass 21, count 0 2006.285.14:43:40.19#ibcon#about to read 5, iclass 21, count 0 2006.285.14:43:40.19#ibcon#read 5, iclass 21, count 0 2006.285.14:43:40.19#ibcon#about to read 6, iclass 21, count 0 2006.285.14:43:40.19#ibcon#read 6, iclass 21, count 0 2006.285.14:43:40.19#ibcon#end of sib2, iclass 21, count 0 2006.285.14:43:40.19#ibcon#*after write, iclass 21, count 0 2006.285.14:43:40.19#ibcon#*before return 0, iclass 21, count 0 2006.285.14:43:40.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:43:40.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:43:40.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.14:43:40.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.14:43:40.19$vck44/valo=7,864.99 2006.285.14:43:40.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.14:43:40.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.14:43:40.19#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:40.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:43:40.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:43:40.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:43:40.19#ibcon#enter wrdev, iclass 23, count 0 2006.285.14:43:40.19#ibcon#first serial, iclass 23, count 0 2006.285.14:43:40.19#ibcon#enter sib2, iclass 23, count 0 2006.285.14:43:40.19#ibcon#flushed, iclass 23, count 0 2006.285.14:43:40.19#ibcon#about to write, iclass 23, count 0 2006.285.14:43:40.19#ibcon#wrote, iclass 23, count 0 2006.285.14:43:40.19#ibcon#about to read 3, iclass 23, count 0 2006.285.14:43:40.20#ibcon#read 3, iclass 23, count 0 2006.285.14:43:40.20#ibcon#about to read 4, iclass 23, count 0 2006.285.14:43:40.21#ibcon#read 4, iclass 23, count 0 2006.285.14:43:40.21#ibcon#about to read 5, iclass 23, count 0 2006.285.14:43:40.21#ibcon#read 5, iclass 23, count 0 2006.285.14:43:40.21#ibcon#about to read 6, iclass 23, count 0 2006.285.14:43:40.21#ibcon#read 6, iclass 23, count 0 2006.285.14:43:40.21#ibcon#end of sib2, iclass 23, count 0 2006.285.14:43:40.21#ibcon#*mode == 0, iclass 23, count 0 2006.285.14:43:40.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.14:43:40.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.14:43:40.21#ibcon#*before write, iclass 23, count 0 2006.285.14:43:40.21#ibcon#enter sib2, iclass 23, count 0 2006.285.14:43:40.21#ibcon#flushed, iclass 23, count 0 2006.285.14:43:40.21#ibcon#about to write, iclass 23, count 0 2006.285.14:43:40.21#ibcon#wrote, iclass 23, count 0 2006.285.14:43:40.21#ibcon#about to read 3, iclass 23, count 0 2006.285.14:43:40.24#ibcon#read 3, iclass 23, count 0 2006.285.14:43:40.24#ibcon#about to read 4, iclass 23, count 0 2006.285.14:43:40.25#ibcon#read 4, iclass 23, count 0 2006.285.14:43:40.25#ibcon#about to read 5, iclass 23, count 0 2006.285.14:43:40.25#ibcon#read 5, iclass 23, count 0 2006.285.14:43:40.25#ibcon#about to read 6, iclass 23, count 0 2006.285.14:43:40.25#ibcon#read 6, iclass 23, count 0 2006.285.14:43:40.25#ibcon#end of sib2, iclass 23, count 0 2006.285.14:43:40.25#ibcon#*after write, iclass 23, count 0 2006.285.14:43:40.25#ibcon#*before return 0, iclass 23, count 0 2006.285.14:43:40.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:43:40.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:43:40.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.14:43:40.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.14:43:40.25$vck44/va=7,4 2006.285.14:43:40.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.14:43:40.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.14:43:40.25#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:40.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:43:40.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:43:40.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:43:40.30#ibcon#enter wrdev, iclass 25, count 2 2006.285.14:43:40.31#ibcon#first serial, iclass 25, count 2 2006.285.14:43:40.31#ibcon#enter sib2, iclass 25, count 2 2006.285.14:43:40.31#ibcon#flushed, iclass 25, count 2 2006.285.14:43:40.31#ibcon#about to write, iclass 25, count 2 2006.285.14:43:40.31#ibcon#wrote, iclass 25, count 2 2006.285.14:43:40.31#ibcon#about to read 3, iclass 25, count 2 2006.285.14:43:40.32#ibcon#read 3, iclass 25, count 2 2006.285.14:43:40.32#ibcon#about to read 4, iclass 25, count 2 2006.285.14:43:40.33#ibcon#read 4, iclass 25, count 2 2006.285.14:43:40.33#ibcon#about to read 5, iclass 25, count 2 2006.285.14:43:40.33#ibcon#read 5, iclass 25, count 2 2006.285.14:43:40.33#ibcon#about to read 6, iclass 25, count 2 2006.285.14:43:40.33#ibcon#read 6, iclass 25, count 2 2006.285.14:43:40.33#ibcon#end of sib2, iclass 25, count 2 2006.285.14:43:40.33#ibcon#*mode == 0, iclass 25, count 2 2006.285.14:43:40.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.14:43:40.33#ibcon#[25=AT07-04\r\n] 2006.285.14:43:40.33#ibcon#*before write, iclass 25, count 2 2006.285.14:43:40.33#ibcon#enter sib2, iclass 25, count 2 2006.285.14:43:40.33#ibcon#flushed, iclass 25, count 2 2006.285.14:43:40.33#ibcon#about to write, iclass 25, count 2 2006.285.14:43:40.33#ibcon#wrote, iclass 25, count 2 2006.285.14:43:40.33#ibcon#about to read 3, iclass 25, count 2 2006.285.14:43:40.35#ibcon#read 3, iclass 25, count 2 2006.285.14:43:40.35#ibcon#about to read 4, iclass 25, count 2 2006.285.14:43:40.35#ibcon#read 4, iclass 25, count 2 2006.285.14:43:40.36#ibcon#about to read 5, iclass 25, count 2 2006.285.14:43:40.36#ibcon#read 5, iclass 25, count 2 2006.285.14:43:40.36#ibcon#about to read 6, iclass 25, count 2 2006.285.14:43:40.36#ibcon#read 6, iclass 25, count 2 2006.285.14:43:40.36#ibcon#end of sib2, iclass 25, count 2 2006.285.14:43:40.36#ibcon#*after write, iclass 25, count 2 2006.285.14:43:40.36#ibcon#*before return 0, iclass 25, count 2 2006.285.14:43:40.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:43:40.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:43:40.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.14:43:40.36#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:40.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:43:40.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:43:40.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:43:40.47#ibcon#enter wrdev, iclass 25, count 0 2006.285.14:43:40.48#ibcon#first serial, iclass 25, count 0 2006.285.14:43:40.48#ibcon#enter sib2, iclass 25, count 0 2006.285.14:43:40.48#ibcon#flushed, iclass 25, count 0 2006.285.14:43:40.48#ibcon#about to write, iclass 25, count 0 2006.285.14:43:40.48#ibcon#wrote, iclass 25, count 0 2006.285.14:43:40.48#ibcon#about to read 3, iclass 25, count 0 2006.285.14:43:40.49#ibcon#read 3, iclass 25, count 0 2006.285.14:43:40.49#ibcon#about to read 4, iclass 25, count 0 2006.285.14:43:40.49#ibcon#read 4, iclass 25, count 0 2006.285.14:43:40.49#ibcon#about to read 5, iclass 25, count 0 2006.285.14:43:40.50#ibcon#read 5, iclass 25, count 0 2006.285.14:43:40.50#ibcon#about to read 6, iclass 25, count 0 2006.285.14:43:40.50#ibcon#read 6, iclass 25, count 0 2006.285.14:43:40.50#ibcon#end of sib2, iclass 25, count 0 2006.285.14:43:40.50#ibcon#*mode == 0, iclass 25, count 0 2006.285.14:43:40.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.14:43:40.50#ibcon#[25=USB\r\n] 2006.285.14:43:40.50#ibcon#*before write, iclass 25, count 0 2006.285.14:43:40.50#ibcon#enter sib2, iclass 25, count 0 2006.285.14:43:40.50#ibcon#flushed, iclass 25, count 0 2006.285.14:43:40.50#ibcon#about to write, iclass 25, count 0 2006.285.14:43:40.50#ibcon#wrote, iclass 25, count 0 2006.285.14:43:40.50#ibcon#about to read 3, iclass 25, count 0 2006.285.14:43:40.52#ibcon#read 3, iclass 25, count 0 2006.285.14:43:40.52#ibcon#about to read 4, iclass 25, count 0 2006.285.14:43:40.52#ibcon#read 4, iclass 25, count 0 2006.285.14:43:40.52#ibcon#about to read 5, iclass 25, count 0 2006.285.14:43:40.53#ibcon#read 5, iclass 25, count 0 2006.285.14:43:40.53#ibcon#about to read 6, iclass 25, count 0 2006.285.14:43:40.53#ibcon#read 6, iclass 25, count 0 2006.285.14:43:40.53#ibcon#end of sib2, iclass 25, count 0 2006.285.14:43:40.53#ibcon#*after write, iclass 25, count 0 2006.285.14:43:40.53#ibcon#*before return 0, iclass 25, count 0 2006.285.14:43:40.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:43:40.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:43:40.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.14:43:40.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.14:43:40.53$vck44/valo=8,884.99 2006.285.14:43:40.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.14:43:40.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.14:43:40.53#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:40.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:43:40.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:43:40.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:43:40.53#ibcon#enter wrdev, iclass 27, count 0 2006.285.14:43:40.53#ibcon#first serial, iclass 27, count 0 2006.285.14:43:40.53#ibcon#enter sib2, iclass 27, count 0 2006.285.14:43:40.53#ibcon#flushed, iclass 27, count 0 2006.285.14:43:40.53#ibcon#about to write, iclass 27, count 0 2006.285.14:43:40.53#ibcon#wrote, iclass 27, count 0 2006.285.14:43:40.53#ibcon#about to read 3, iclass 27, count 0 2006.285.14:43:40.54#ibcon#read 3, iclass 27, count 0 2006.285.14:43:40.54#ibcon#about to read 4, iclass 27, count 0 2006.285.14:43:40.54#ibcon#read 4, iclass 27, count 0 2006.285.14:43:40.55#ibcon#about to read 5, iclass 27, count 0 2006.285.14:43:40.55#ibcon#read 5, iclass 27, count 0 2006.285.14:43:40.55#ibcon#about to read 6, iclass 27, count 0 2006.285.14:43:40.55#ibcon#read 6, iclass 27, count 0 2006.285.14:43:40.55#ibcon#end of sib2, iclass 27, count 0 2006.285.14:43:40.55#ibcon#*mode == 0, iclass 27, count 0 2006.285.14:43:40.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.14:43:40.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.14:43:40.55#ibcon#*before write, iclass 27, count 0 2006.285.14:43:40.55#ibcon#enter sib2, iclass 27, count 0 2006.285.14:43:40.55#ibcon#flushed, iclass 27, count 0 2006.285.14:43:40.55#ibcon#about to write, iclass 27, count 0 2006.285.14:43:40.55#ibcon#wrote, iclass 27, count 0 2006.285.14:43:40.55#ibcon#about to read 3, iclass 27, count 0 2006.285.14:43:40.58#ibcon#read 3, iclass 27, count 0 2006.285.14:43:40.58#ibcon#about to read 4, iclass 27, count 0 2006.285.14:43:40.58#ibcon#read 4, iclass 27, count 0 2006.285.14:43:40.58#ibcon#about to read 5, iclass 27, count 0 2006.285.14:43:40.59#ibcon#read 5, iclass 27, count 0 2006.285.14:43:40.59#ibcon#about to read 6, iclass 27, count 0 2006.285.14:43:40.59#ibcon#read 6, iclass 27, count 0 2006.285.14:43:40.59#ibcon#end of sib2, iclass 27, count 0 2006.285.14:43:40.59#ibcon#*after write, iclass 27, count 0 2006.285.14:43:40.59#ibcon#*before return 0, iclass 27, count 0 2006.285.14:43:40.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:43:40.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:43:40.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.14:43:40.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.14:43:40.59$vck44/va=8,3 2006.285.14:43:40.59#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.14:43:40.59#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.14:43:40.59#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:40.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:43:40.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:43:40.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:43:40.64#ibcon#enter wrdev, iclass 29, count 2 2006.285.14:43:40.64#ibcon#first serial, iclass 29, count 2 2006.285.14:43:40.65#ibcon#enter sib2, iclass 29, count 2 2006.285.14:43:40.65#ibcon#flushed, iclass 29, count 2 2006.285.14:43:40.65#ibcon#about to write, iclass 29, count 2 2006.285.14:43:40.65#ibcon#wrote, iclass 29, count 2 2006.285.14:43:40.65#ibcon#about to read 3, iclass 29, count 2 2006.285.14:43:40.66#ibcon#read 3, iclass 29, count 2 2006.285.14:43:40.66#ibcon#about to read 4, iclass 29, count 2 2006.285.14:43:40.66#ibcon#read 4, iclass 29, count 2 2006.285.14:43:40.66#ibcon#about to read 5, iclass 29, count 2 2006.285.14:43:40.67#ibcon#read 5, iclass 29, count 2 2006.285.14:43:40.67#ibcon#about to read 6, iclass 29, count 2 2006.285.14:43:40.67#ibcon#read 6, iclass 29, count 2 2006.285.14:43:40.67#ibcon#end of sib2, iclass 29, count 2 2006.285.14:43:40.67#ibcon#*mode == 0, iclass 29, count 2 2006.285.14:43:40.67#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.14:43:40.67#ibcon#[25=AT08-03\r\n] 2006.285.14:43:40.67#ibcon#*before write, iclass 29, count 2 2006.285.14:43:40.67#ibcon#enter sib2, iclass 29, count 2 2006.285.14:43:40.67#ibcon#flushed, iclass 29, count 2 2006.285.14:43:40.67#ibcon#about to write, iclass 29, count 2 2006.285.14:43:40.67#ibcon#wrote, iclass 29, count 2 2006.285.14:43:40.67#ibcon#about to read 3, iclass 29, count 2 2006.285.14:43:40.69#ibcon#read 3, iclass 29, count 2 2006.285.14:43:40.69#ibcon#about to read 4, iclass 29, count 2 2006.285.14:43:40.69#ibcon#read 4, iclass 29, count 2 2006.285.14:43:40.69#ibcon#about to read 5, iclass 29, count 2 2006.285.14:43:40.70#ibcon#read 5, iclass 29, count 2 2006.285.14:43:40.70#ibcon#about to read 6, iclass 29, count 2 2006.285.14:43:40.70#ibcon#read 6, iclass 29, count 2 2006.285.14:43:40.70#ibcon#end of sib2, iclass 29, count 2 2006.285.14:43:40.70#ibcon#*after write, iclass 29, count 2 2006.285.14:43:40.70#ibcon#*before return 0, iclass 29, count 2 2006.285.14:43:40.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:43:40.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:43:40.70#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.14:43:40.70#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:40.70#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:43:40.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:43:40.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:43:40.82#ibcon#enter wrdev, iclass 29, count 0 2006.285.14:43:40.82#ibcon#first serial, iclass 29, count 0 2006.285.14:43:40.82#ibcon#enter sib2, iclass 29, count 0 2006.285.14:43:40.82#ibcon#flushed, iclass 29, count 0 2006.285.14:43:40.82#ibcon#about to write, iclass 29, count 0 2006.285.14:43:40.82#ibcon#wrote, iclass 29, count 0 2006.285.14:43:40.82#ibcon#about to read 3, iclass 29, count 0 2006.285.14:43:40.83#ibcon#read 3, iclass 29, count 0 2006.285.14:43:40.83#ibcon#about to read 4, iclass 29, count 0 2006.285.14:43:40.84#ibcon#read 4, iclass 29, count 0 2006.285.14:43:40.84#ibcon#about to read 5, iclass 29, count 0 2006.285.14:43:40.84#ibcon#read 5, iclass 29, count 0 2006.285.14:43:40.84#ibcon#about to read 6, iclass 29, count 0 2006.285.14:43:40.84#ibcon#read 6, iclass 29, count 0 2006.285.14:43:40.84#ibcon#end of sib2, iclass 29, count 0 2006.285.14:43:40.84#ibcon#*mode == 0, iclass 29, count 0 2006.285.14:43:40.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.14:43:40.84#ibcon#[25=USB\r\n] 2006.285.14:43:40.84#ibcon#*before write, iclass 29, count 0 2006.285.14:43:40.84#ibcon#enter sib2, iclass 29, count 0 2006.285.14:43:40.84#ibcon#flushed, iclass 29, count 0 2006.285.14:43:40.84#ibcon#about to write, iclass 29, count 0 2006.285.14:43:40.84#ibcon#wrote, iclass 29, count 0 2006.285.14:43:40.84#ibcon#about to read 3, iclass 29, count 0 2006.285.14:43:40.86#ibcon#read 3, iclass 29, count 0 2006.285.14:43:40.86#ibcon#about to read 4, iclass 29, count 0 2006.285.14:43:40.86#ibcon#read 4, iclass 29, count 0 2006.285.14:43:40.87#ibcon#about to read 5, iclass 29, count 0 2006.285.14:43:40.87#ibcon#read 5, iclass 29, count 0 2006.285.14:43:40.87#ibcon#about to read 6, iclass 29, count 0 2006.285.14:43:40.87#ibcon#read 6, iclass 29, count 0 2006.285.14:43:40.87#ibcon#end of sib2, iclass 29, count 0 2006.285.14:43:40.87#ibcon#*after write, iclass 29, count 0 2006.285.14:43:40.87#ibcon#*before return 0, iclass 29, count 0 2006.285.14:43:40.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:43:40.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:43:40.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.14:43:40.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.14:43:40.87$vck44/vblo=1,629.99 2006.285.14:43:40.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.14:43:40.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.14:43:40.87#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:40.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:43:40.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:43:40.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:43:40.87#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:43:40.87#ibcon#first serial, iclass 31, count 0 2006.285.14:43:40.87#ibcon#enter sib2, iclass 31, count 0 2006.285.14:43:40.87#ibcon#flushed, iclass 31, count 0 2006.285.14:43:40.87#ibcon#about to write, iclass 31, count 0 2006.285.14:43:40.87#ibcon#wrote, iclass 31, count 0 2006.285.14:43:40.87#ibcon#about to read 3, iclass 31, count 0 2006.285.14:43:40.88#ibcon#read 3, iclass 31, count 0 2006.285.14:43:40.91#ibcon#about to read 4, iclass 31, count 0 2006.285.14:43:40.91#ibcon#read 4, iclass 31, count 0 2006.285.14:43:40.91#ibcon#about to read 5, iclass 31, count 0 2006.285.14:43:40.91#ibcon#read 5, iclass 31, count 0 2006.285.14:43:40.91#ibcon#about to read 6, iclass 31, count 0 2006.285.14:43:40.91#ibcon#read 6, iclass 31, count 0 2006.285.14:43:40.91#ibcon#end of sib2, iclass 31, count 0 2006.285.14:43:40.91#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:43:40.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:43:40.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.14:43:40.91#ibcon#*before write, iclass 31, count 0 2006.285.14:43:40.91#ibcon#enter sib2, iclass 31, count 0 2006.285.14:43:40.91#ibcon#flushed, iclass 31, count 0 2006.285.14:43:40.91#ibcon#about to write, iclass 31, count 0 2006.285.14:43:40.91#ibcon#wrote, iclass 31, count 0 2006.285.14:43:40.91#ibcon#about to read 3, iclass 31, count 0 2006.285.14:43:40.95#ibcon#read 3, iclass 31, count 0 2006.285.14:43:40.95#ibcon#about to read 4, iclass 31, count 0 2006.285.14:43:40.96#ibcon#read 4, iclass 31, count 0 2006.285.14:43:40.96#ibcon#about to read 5, iclass 31, count 0 2006.285.14:43:40.96#ibcon#read 5, iclass 31, count 0 2006.285.14:43:40.96#ibcon#about to read 6, iclass 31, count 0 2006.285.14:43:40.96#ibcon#read 6, iclass 31, count 0 2006.285.14:43:40.96#ibcon#end of sib2, iclass 31, count 0 2006.285.14:43:40.96#ibcon#*after write, iclass 31, count 0 2006.285.14:43:40.96#ibcon#*before return 0, iclass 31, count 0 2006.285.14:43:40.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:43:40.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:43:40.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:43:40.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:43:40.96$vck44/vb=1,4 2006.285.14:43:40.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.14:43:40.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.14:43:40.96#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:40.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:43:40.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:43:40.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:43:40.96#ibcon#enter wrdev, iclass 33, count 2 2006.285.14:43:40.96#ibcon#first serial, iclass 33, count 2 2006.285.14:43:40.96#ibcon#enter sib2, iclass 33, count 2 2006.285.14:43:40.96#ibcon#flushed, iclass 33, count 2 2006.285.14:43:40.96#ibcon#about to write, iclass 33, count 2 2006.285.14:43:40.96#ibcon#wrote, iclass 33, count 2 2006.285.14:43:40.96#ibcon#about to read 3, iclass 33, count 2 2006.285.14:43:40.97#ibcon#read 3, iclass 33, count 2 2006.285.14:43:40.97#ibcon#about to read 4, iclass 33, count 2 2006.285.14:43:40.97#ibcon#read 4, iclass 33, count 2 2006.285.14:43:40.98#ibcon#about to read 5, iclass 33, count 2 2006.285.14:43:40.98#ibcon#read 5, iclass 33, count 2 2006.285.14:43:40.98#ibcon#about to read 6, iclass 33, count 2 2006.285.14:43:40.98#ibcon#read 6, iclass 33, count 2 2006.285.14:43:40.98#ibcon#end of sib2, iclass 33, count 2 2006.285.14:43:40.98#ibcon#*mode == 0, iclass 33, count 2 2006.285.14:43:40.98#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.14:43:40.98#ibcon#[27=AT01-04\r\n] 2006.285.14:43:40.98#ibcon#*before write, iclass 33, count 2 2006.285.14:43:40.98#ibcon#enter sib2, iclass 33, count 2 2006.285.14:43:40.98#ibcon#flushed, iclass 33, count 2 2006.285.14:43:40.98#ibcon#about to write, iclass 33, count 2 2006.285.14:43:40.98#ibcon#wrote, iclass 33, count 2 2006.285.14:43:40.98#ibcon#about to read 3, iclass 33, count 2 2006.285.14:43:41.00#ibcon#read 3, iclass 33, count 2 2006.285.14:43:41.00#ibcon#about to read 4, iclass 33, count 2 2006.285.14:43:41.00#ibcon#read 4, iclass 33, count 2 2006.285.14:43:41.00#ibcon#about to read 5, iclass 33, count 2 2006.285.14:43:41.01#ibcon#read 5, iclass 33, count 2 2006.285.14:43:41.01#ibcon#about to read 6, iclass 33, count 2 2006.285.14:43:41.01#ibcon#read 6, iclass 33, count 2 2006.285.14:43:41.01#ibcon#end of sib2, iclass 33, count 2 2006.285.14:43:41.01#ibcon#*after write, iclass 33, count 2 2006.285.14:43:41.01#ibcon#*before return 0, iclass 33, count 2 2006.285.14:43:41.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:43:41.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.14:43:41.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.14:43:41.01#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:41.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:43:41.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:43:41.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:43:41.12#ibcon#enter wrdev, iclass 33, count 0 2006.285.14:43:41.13#ibcon#first serial, iclass 33, count 0 2006.285.14:43:41.13#ibcon#enter sib2, iclass 33, count 0 2006.285.14:43:41.13#ibcon#flushed, iclass 33, count 0 2006.285.14:43:41.13#ibcon#about to write, iclass 33, count 0 2006.285.14:43:41.13#ibcon#wrote, iclass 33, count 0 2006.285.14:43:41.13#ibcon#about to read 3, iclass 33, count 0 2006.285.14:43:41.14#ibcon#read 3, iclass 33, count 0 2006.285.14:43:41.14#ibcon#about to read 4, iclass 33, count 0 2006.285.14:43:41.15#ibcon#read 4, iclass 33, count 0 2006.285.14:43:41.15#ibcon#about to read 5, iclass 33, count 0 2006.285.14:43:41.15#ibcon#read 5, iclass 33, count 0 2006.285.14:43:41.15#ibcon#about to read 6, iclass 33, count 0 2006.285.14:43:41.15#ibcon#read 6, iclass 33, count 0 2006.285.14:43:41.15#ibcon#end of sib2, iclass 33, count 0 2006.285.14:43:41.15#ibcon#*mode == 0, iclass 33, count 0 2006.285.14:43:41.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.14:43:41.15#ibcon#[27=USB\r\n] 2006.285.14:43:41.15#ibcon#*before write, iclass 33, count 0 2006.285.14:43:41.15#ibcon#enter sib2, iclass 33, count 0 2006.285.14:43:41.15#ibcon#flushed, iclass 33, count 0 2006.285.14:43:41.15#ibcon#about to write, iclass 33, count 0 2006.285.14:43:41.15#ibcon#wrote, iclass 33, count 0 2006.285.14:43:41.15#ibcon#about to read 3, iclass 33, count 0 2006.285.14:43:41.17#ibcon#read 3, iclass 33, count 0 2006.285.14:43:41.17#ibcon#about to read 4, iclass 33, count 0 2006.285.14:43:41.18#ibcon#read 4, iclass 33, count 0 2006.285.14:43:41.18#ibcon#about to read 5, iclass 33, count 0 2006.285.14:43:41.18#ibcon#read 5, iclass 33, count 0 2006.285.14:43:41.18#ibcon#about to read 6, iclass 33, count 0 2006.285.14:43:41.18#ibcon#read 6, iclass 33, count 0 2006.285.14:43:41.18#ibcon#end of sib2, iclass 33, count 0 2006.285.14:43:41.18#ibcon#*after write, iclass 33, count 0 2006.285.14:43:41.18#ibcon#*before return 0, iclass 33, count 0 2006.285.14:43:41.18#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:43:41.18#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.14:43:41.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.14:43:41.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.14:43:41.18$vck44/vblo=2,634.99 2006.285.14:43:41.18#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.14:43:41.18#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.14:43:41.18#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:41.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:43:41.18#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:43:41.18#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:43:41.18#ibcon#enter wrdev, iclass 35, count 0 2006.285.14:43:41.18#ibcon#first serial, iclass 35, count 0 2006.285.14:43:41.18#ibcon#enter sib2, iclass 35, count 0 2006.285.14:43:41.18#ibcon#flushed, iclass 35, count 0 2006.285.14:43:41.18#ibcon#about to write, iclass 35, count 0 2006.285.14:43:41.18#ibcon#wrote, iclass 35, count 0 2006.285.14:43:41.18#ibcon#about to read 3, iclass 35, count 0 2006.285.14:43:41.19#ibcon#read 3, iclass 35, count 0 2006.285.14:43:41.19#ibcon#about to read 4, iclass 35, count 0 2006.285.14:43:41.19#ibcon#read 4, iclass 35, count 0 2006.285.14:43:41.20#ibcon#about to read 5, iclass 35, count 0 2006.285.14:43:41.20#ibcon#read 5, iclass 35, count 0 2006.285.14:43:41.20#ibcon#about to read 6, iclass 35, count 0 2006.285.14:43:41.20#ibcon#read 6, iclass 35, count 0 2006.285.14:43:41.20#ibcon#end of sib2, iclass 35, count 0 2006.285.14:43:41.20#ibcon#*mode == 0, iclass 35, count 0 2006.285.14:43:41.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.14:43:41.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.14:43:41.20#ibcon#*before write, iclass 35, count 0 2006.285.14:43:41.20#ibcon#enter sib2, iclass 35, count 0 2006.285.14:43:41.20#ibcon#flushed, iclass 35, count 0 2006.285.14:43:41.20#ibcon#about to write, iclass 35, count 0 2006.285.14:43:41.20#ibcon#wrote, iclass 35, count 0 2006.285.14:43:41.20#ibcon#about to read 3, iclass 35, count 0 2006.285.14:43:41.23#ibcon#read 3, iclass 35, count 0 2006.285.14:43:41.23#ibcon#about to read 4, iclass 35, count 0 2006.285.14:43:41.23#ibcon#read 4, iclass 35, count 0 2006.285.14:43:41.24#ibcon#about to read 5, iclass 35, count 0 2006.285.14:43:41.24#ibcon#read 5, iclass 35, count 0 2006.285.14:43:41.24#ibcon#about to read 6, iclass 35, count 0 2006.285.14:43:41.24#ibcon#read 6, iclass 35, count 0 2006.285.14:43:41.24#ibcon#end of sib2, iclass 35, count 0 2006.285.14:43:41.24#ibcon#*after write, iclass 35, count 0 2006.285.14:43:41.24#ibcon#*before return 0, iclass 35, count 0 2006.285.14:43:41.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:43:41.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:43:41.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.14:43:41.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.14:43:41.24$vck44/vb=2,5 2006.285.14:43:41.24#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.14:43:41.24#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.14:43:41.24#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:41.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:43:41.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:43:41.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:43:41.29#ibcon#enter wrdev, iclass 37, count 2 2006.285.14:43:41.29#ibcon#first serial, iclass 37, count 2 2006.285.14:43:41.30#ibcon#enter sib2, iclass 37, count 2 2006.285.14:43:41.30#ibcon#flushed, iclass 37, count 2 2006.285.14:43:41.30#ibcon#about to write, iclass 37, count 2 2006.285.14:43:41.30#ibcon#wrote, iclass 37, count 2 2006.285.14:43:41.30#ibcon#about to read 3, iclass 37, count 2 2006.285.14:43:41.31#ibcon#read 3, iclass 37, count 2 2006.285.14:43:41.31#ibcon#about to read 4, iclass 37, count 2 2006.285.14:43:41.31#ibcon#read 4, iclass 37, count 2 2006.285.14:43:41.31#ibcon#about to read 5, iclass 37, count 2 2006.285.14:43:41.32#ibcon#read 5, iclass 37, count 2 2006.285.14:43:41.32#ibcon#about to read 6, iclass 37, count 2 2006.285.14:43:41.32#ibcon#read 6, iclass 37, count 2 2006.285.14:43:41.32#ibcon#end of sib2, iclass 37, count 2 2006.285.14:43:41.32#ibcon#*mode == 0, iclass 37, count 2 2006.285.14:43:41.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.14:43:41.32#ibcon#[27=AT02-05\r\n] 2006.285.14:43:41.32#ibcon#*before write, iclass 37, count 2 2006.285.14:43:41.32#ibcon#enter sib2, iclass 37, count 2 2006.285.14:43:41.32#ibcon#flushed, iclass 37, count 2 2006.285.14:43:41.32#ibcon#about to write, iclass 37, count 2 2006.285.14:43:41.32#ibcon#wrote, iclass 37, count 2 2006.285.14:43:41.32#ibcon#about to read 3, iclass 37, count 2 2006.285.14:43:41.34#ibcon#read 3, iclass 37, count 2 2006.285.14:43:41.34#ibcon#about to read 4, iclass 37, count 2 2006.285.14:43:41.34#ibcon#read 4, iclass 37, count 2 2006.285.14:43:41.34#ibcon#about to read 5, iclass 37, count 2 2006.285.14:43:41.35#ibcon#read 5, iclass 37, count 2 2006.285.14:43:41.35#ibcon#about to read 6, iclass 37, count 2 2006.285.14:43:41.35#ibcon#read 6, iclass 37, count 2 2006.285.14:43:41.35#ibcon#end of sib2, iclass 37, count 2 2006.285.14:43:41.35#ibcon#*after write, iclass 37, count 2 2006.285.14:43:41.35#ibcon#*before return 0, iclass 37, count 2 2006.285.14:43:41.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:43:41.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.14:43:41.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.14:43:41.35#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:41.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:43:41.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:43:41.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:43:41.46#ibcon#enter wrdev, iclass 37, count 0 2006.285.14:43:41.46#ibcon#first serial, iclass 37, count 0 2006.285.14:43:41.46#ibcon#enter sib2, iclass 37, count 0 2006.285.14:43:41.47#ibcon#flushed, iclass 37, count 0 2006.285.14:43:41.47#ibcon#about to write, iclass 37, count 0 2006.285.14:43:41.47#ibcon#wrote, iclass 37, count 0 2006.285.14:43:41.47#ibcon#about to read 3, iclass 37, count 0 2006.285.14:43:41.48#ibcon#read 3, iclass 37, count 0 2006.285.14:43:41.48#ibcon#about to read 4, iclass 37, count 0 2006.285.14:43:41.48#ibcon#read 4, iclass 37, count 0 2006.285.14:43:41.48#ibcon#about to read 5, iclass 37, count 0 2006.285.14:43:41.49#ibcon#read 5, iclass 37, count 0 2006.285.14:43:41.49#ibcon#about to read 6, iclass 37, count 0 2006.285.14:43:41.49#ibcon#read 6, iclass 37, count 0 2006.285.14:43:41.49#ibcon#end of sib2, iclass 37, count 0 2006.285.14:43:41.49#ibcon#*mode == 0, iclass 37, count 0 2006.285.14:43:41.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.14:43:41.49#ibcon#[27=USB\r\n] 2006.285.14:43:41.49#ibcon#*before write, iclass 37, count 0 2006.285.14:43:41.49#ibcon#enter sib2, iclass 37, count 0 2006.285.14:43:41.49#ibcon#flushed, iclass 37, count 0 2006.285.14:43:41.49#ibcon#about to write, iclass 37, count 0 2006.285.14:43:41.49#ibcon#wrote, iclass 37, count 0 2006.285.14:43:41.49#ibcon#about to read 3, iclass 37, count 0 2006.285.14:43:41.51#ibcon#read 3, iclass 37, count 0 2006.285.14:43:41.51#ibcon#about to read 4, iclass 37, count 0 2006.285.14:43:41.51#ibcon#read 4, iclass 37, count 0 2006.285.14:43:41.51#ibcon#about to read 5, iclass 37, count 0 2006.285.14:43:41.52#ibcon#read 5, iclass 37, count 0 2006.285.14:43:41.52#ibcon#about to read 6, iclass 37, count 0 2006.285.14:43:41.52#ibcon#read 6, iclass 37, count 0 2006.285.14:43:41.52#ibcon#end of sib2, iclass 37, count 0 2006.285.14:43:41.52#ibcon#*after write, iclass 37, count 0 2006.285.14:43:41.52#ibcon#*before return 0, iclass 37, count 0 2006.285.14:43:41.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:43:41.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.14:43:41.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.14:43:41.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.14:43:41.52$vck44/vblo=3,649.99 2006.285.14:43:41.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.14:43:41.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.14:43:41.52#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:41.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:43:41.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:43:41.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:43:41.52#ibcon#enter wrdev, iclass 39, count 0 2006.285.14:43:41.52#ibcon#first serial, iclass 39, count 0 2006.285.14:43:41.52#ibcon#enter sib2, iclass 39, count 0 2006.285.14:43:41.52#ibcon#flushed, iclass 39, count 0 2006.285.14:43:41.52#ibcon#about to write, iclass 39, count 0 2006.285.14:43:41.52#ibcon#wrote, iclass 39, count 0 2006.285.14:43:41.52#ibcon#about to read 3, iclass 39, count 0 2006.285.14:43:41.53#ibcon#read 3, iclass 39, count 0 2006.285.14:43:41.53#ibcon#about to read 4, iclass 39, count 0 2006.285.14:43:41.53#ibcon#read 4, iclass 39, count 0 2006.285.14:43:41.54#ibcon#about to read 5, iclass 39, count 0 2006.285.14:43:41.54#ibcon#read 5, iclass 39, count 0 2006.285.14:43:41.54#ibcon#about to read 6, iclass 39, count 0 2006.285.14:43:41.54#ibcon#read 6, iclass 39, count 0 2006.285.14:43:41.54#ibcon#end of sib2, iclass 39, count 0 2006.285.14:43:41.54#ibcon#*mode == 0, iclass 39, count 0 2006.285.14:43:41.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.14:43:41.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.14:43:41.54#ibcon#*before write, iclass 39, count 0 2006.285.14:43:41.54#ibcon#enter sib2, iclass 39, count 0 2006.285.14:43:41.54#ibcon#flushed, iclass 39, count 0 2006.285.14:43:41.54#ibcon#about to write, iclass 39, count 0 2006.285.14:43:41.54#ibcon#wrote, iclass 39, count 0 2006.285.14:43:41.54#ibcon#about to read 3, iclass 39, count 0 2006.285.14:43:41.57#ibcon#read 3, iclass 39, count 0 2006.285.14:43:41.57#ibcon#about to read 4, iclass 39, count 0 2006.285.14:43:41.57#ibcon#read 4, iclass 39, count 0 2006.285.14:43:41.57#ibcon#about to read 5, iclass 39, count 0 2006.285.14:43:41.58#ibcon#read 5, iclass 39, count 0 2006.285.14:43:41.58#ibcon#about to read 6, iclass 39, count 0 2006.285.14:43:41.58#ibcon#read 6, iclass 39, count 0 2006.285.14:43:41.58#ibcon#end of sib2, iclass 39, count 0 2006.285.14:43:41.58#ibcon#*after write, iclass 39, count 0 2006.285.14:43:41.58#ibcon#*before return 0, iclass 39, count 0 2006.285.14:43:41.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:43:41.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.14:43:41.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.14:43:41.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.14:43:41.58$vck44/vb=3,4 2006.285.14:43:41.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.14:43:41.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.14:43:41.58#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:41.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:43:41.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:43:41.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:43:41.63#ibcon#enter wrdev, iclass 3, count 2 2006.285.14:43:41.63#ibcon#first serial, iclass 3, count 2 2006.285.14:43:41.64#ibcon#enter sib2, iclass 3, count 2 2006.285.14:43:41.64#ibcon#flushed, iclass 3, count 2 2006.285.14:43:41.64#ibcon#about to write, iclass 3, count 2 2006.285.14:43:41.64#ibcon#wrote, iclass 3, count 2 2006.285.14:43:41.64#ibcon#about to read 3, iclass 3, count 2 2006.285.14:43:41.65#ibcon#read 3, iclass 3, count 2 2006.285.14:43:41.65#ibcon#about to read 4, iclass 3, count 2 2006.285.14:43:41.65#ibcon#read 4, iclass 3, count 2 2006.285.14:43:41.65#ibcon#about to read 5, iclass 3, count 2 2006.285.14:43:41.65#ibcon#read 5, iclass 3, count 2 2006.285.14:43:41.66#ibcon#about to read 6, iclass 3, count 2 2006.285.14:43:41.66#ibcon#read 6, iclass 3, count 2 2006.285.14:43:41.66#ibcon#end of sib2, iclass 3, count 2 2006.285.14:43:41.66#ibcon#*mode == 0, iclass 3, count 2 2006.285.14:43:41.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.14:43:41.66#ibcon#[27=AT03-04\r\n] 2006.285.14:43:41.66#ibcon#*before write, iclass 3, count 2 2006.285.14:43:41.66#ibcon#enter sib2, iclass 3, count 2 2006.285.14:43:41.66#ibcon#flushed, iclass 3, count 2 2006.285.14:43:41.66#ibcon#about to write, iclass 3, count 2 2006.285.14:43:41.66#ibcon#wrote, iclass 3, count 2 2006.285.14:43:41.66#ibcon#about to read 3, iclass 3, count 2 2006.285.14:43:41.68#ibcon#read 3, iclass 3, count 2 2006.285.14:43:41.69#ibcon#about to read 4, iclass 3, count 2 2006.285.14:43:41.69#ibcon#read 4, iclass 3, count 2 2006.285.14:43:41.69#ibcon#about to read 5, iclass 3, count 2 2006.285.14:43:41.69#ibcon#read 5, iclass 3, count 2 2006.285.14:43:41.69#ibcon#about to read 6, iclass 3, count 2 2006.285.14:43:41.69#ibcon#read 6, iclass 3, count 2 2006.285.14:43:41.69#ibcon#end of sib2, iclass 3, count 2 2006.285.14:43:41.69#ibcon#*after write, iclass 3, count 2 2006.285.14:43:41.69#ibcon#*before return 0, iclass 3, count 2 2006.285.14:43:41.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:43:41.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.14:43:41.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.14:43:41.69#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:41.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:43:41.71#abcon#<5=/04 2.1 4.3 19.18 941015.0\r\n> 2006.285.14:43:41.73#abcon#{5=INTERFACE CLEAR} 2006.285.14:43:41.79#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:43:41.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:43:41.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:43:41.80#ibcon#enter wrdev, iclass 3, count 0 2006.285.14:43:41.81#ibcon#first serial, iclass 3, count 0 2006.285.14:43:41.81#ibcon#enter sib2, iclass 3, count 0 2006.285.14:43:41.81#ibcon#flushed, iclass 3, count 0 2006.285.14:43:41.81#ibcon#about to write, iclass 3, count 0 2006.285.14:43:41.81#ibcon#wrote, iclass 3, count 0 2006.285.14:43:41.81#ibcon#about to read 3, iclass 3, count 0 2006.285.14:43:41.82#ibcon#read 3, iclass 3, count 0 2006.285.14:43:41.82#ibcon#about to read 4, iclass 3, count 0 2006.285.14:43:41.82#ibcon#read 4, iclass 3, count 0 2006.285.14:43:41.82#ibcon#about to read 5, iclass 3, count 0 2006.285.14:43:41.83#ibcon#read 5, iclass 3, count 0 2006.285.14:43:41.83#ibcon#about to read 6, iclass 3, count 0 2006.285.14:43:41.83#ibcon#read 6, iclass 3, count 0 2006.285.14:43:41.83#ibcon#end of sib2, iclass 3, count 0 2006.285.14:43:41.83#ibcon#*mode == 0, iclass 3, count 0 2006.285.14:43:41.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.14:43:41.83#ibcon#[27=USB\r\n] 2006.285.14:43:41.83#ibcon#*before write, iclass 3, count 0 2006.285.14:43:41.83#ibcon#enter sib2, iclass 3, count 0 2006.285.14:43:41.83#ibcon#flushed, iclass 3, count 0 2006.285.14:43:41.83#ibcon#about to write, iclass 3, count 0 2006.285.14:43:41.83#ibcon#wrote, iclass 3, count 0 2006.285.14:43:41.83#ibcon#about to read 3, iclass 3, count 0 2006.285.14:43:41.85#ibcon#read 3, iclass 3, count 0 2006.285.14:43:41.85#ibcon#about to read 4, iclass 3, count 0 2006.285.14:43:41.86#ibcon#read 4, iclass 3, count 0 2006.285.14:43:41.86#ibcon#about to read 5, iclass 3, count 0 2006.285.14:43:41.86#ibcon#read 5, iclass 3, count 0 2006.285.14:43:41.86#ibcon#about to read 6, iclass 3, count 0 2006.285.14:43:41.86#ibcon#read 6, iclass 3, count 0 2006.285.14:43:41.86#ibcon#end of sib2, iclass 3, count 0 2006.285.14:43:41.86#ibcon#*after write, iclass 3, count 0 2006.285.14:43:41.86#ibcon#*before return 0, iclass 3, count 0 2006.285.14:43:41.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:43:41.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.14:43:41.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.14:43:41.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.14:43:41.86$vck44/vblo=4,679.99 2006.285.14:43:41.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.14:43:41.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.14:43:42.00#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:42.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:43:42.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:43:42.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:43:42.00#ibcon#enter wrdev, iclass 11, count 0 2006.285.14:43:42.00#ibcon#first serial, iclass 11, count 0 2006.285.14:43:42.00#ibcon#enter sib2, iclass 11, count 0 2006.285.14:43:42.00#ibcon#flushed, iclass 11, count 0 2006.285.14:43:42.00#ibcon#about to write, iclass 11, count 0 2006.285.14:43:42.00#ibcon#wrote, iclass 11, count 0 2006.285.14:43:42.00#ibcon#about to read 3, iclass 11, count 0 2006.285.14:43:42.01#ibcon#read 3, iclass 11, count 0 2006.285.14:43:42.02#ibcon#about to read 4, iclass 11, count 0 2006.285.14:43:42.02#ibcon#read 4, iclass 11, count 0 2006.285.14:43:42.02#ibcon#about to read 5, iclass 11, count 0 2006.285.14:43:42.02#ibcon#read 5, iclass 11, count 0 2006.285.14:43:42.02#ibcon#about to read 6, iclass 11, count 0 2006.285.14:43:42.02#ibcon#read 6, iclass 11, count 0 2006.285.14:43:42.02#ibcon#end of sib2, iclass 11, count 0 2006.285.14:43:42.02#ibcon#*mode == 0, iclass 11, count 0 2006.285.14:43:42.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.14:43:42.02#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.14:43:42.02#ibcon#*before write, iclass 11, count 0 2006.285.14:43:42.02#ibcon#enter sib2, iclass 11, count 0 2006.285.14:43:42.02#ibcon#flushed, iclass 11, count 0 2006.285.14:43:42.02#ibcon#about to write, iclass 11, count 0 2006.285.14:43:42.02#ibcon#wrote, iclass 11, count 0 2006.285.14:43:42.02#ibcon#about to read 3, iclass 11, count 0 2006.285.14:43:42.05#ibcon#read 3, iclass 11, count 0 2006.285.14:43:42.05#ibcon#about to read 4, iclass 11, count 0 2006.285.14:43:42.06#ibcon#read 4, iclass 11, count 0 2006.285.14:43:42.06#ibcon#about to read 5, iclass 11, count 0 2006.285.14:43:42.06#ibcon#read 5, iclass 11, count 0 2006.285.14:43:42.06#ibcon#about to read 6, iclass 11, count 0 2006.285.14:43:42.06#ibcon#read 6, iclass 11, count 0 2006.285.14:43:42.06#ibcon#end of sib2, iclass 11, count 0 2006.285.14:43:42.06#ibcon#*after write, iclass 11, count 0 2006.285.14:43:42.06#ibcon#*before return 0, iclass 11, count 0 2006.285.14:43:42.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:43:42.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.14:43:42.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.14:43:42.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.14:43:42.06$vck44/vb=4,5 2006.285.14:43:42.06#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.14:43:42.06#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.14:43:42.06#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:42.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:43:42.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:43:42.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:43:42.06#ibcon#enter wrdev, iclass 13, count 2 2006.285.14:43:42.06#ibcon#first serial, iclass 13, count 2 2006.285.14:43:42.06#ibcon#enter sib2, iclass 13, count 2 2006.285.14:43:42.06#ibcon#flushed, iclass 13, count 2 2006.285.14:43:42.06#ibcon#about to write, iclass 13, count 2 2006.285.14:43:42.06#ibcon#wrote, iclass 13, count 2 2006.285.14:43:42.06#ibcon#about to read 3, iclass 13, count 2 2006.285.14:43:42.07#ibcon#read 3, iclass 13, count 2 2006.285.14:43:42.07#ibcon#about to read 4, iclass 13, count 2 2006.285.14:43:42.08#ibcon#read 4, iclass 13, count 2 2006.285.14:43:42.08#ibcon#about to read 5, iclass 13, count 2 2006.285.14:43:42.08#ibcon#read 5, iclass 13, count 2 2006.285.14:43:42.08#ibcon#about to read 6, iclass 13, count 2 2006.285.14:43:42.08#ibcon#read 6, iclass 13, count 2 2006.285.14:43:42.08#ibcon#end of sib2, iclass 13, count 2 2006.285.14:43:42.08#ibcon#*mode == 0, iclass 13, count 2 2006.285.14:43:42.08#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.14:43:42.08#ibcon#[27=AT04-05\r\n] 2006.285.14:43:42.08#ibcon#*before write, iclass 13, count 2 2006.285.14:43:42.08#ibcon#enter sib2, iclass 13, count 2 2006.285.14:43:42.08#ibcon#flushed, iclass 13, count 2 2006.285.14:43:42.08#ibcon#about to write, iclass 13, count 2 2006.285.14:43:42.08#ibcon#wrote, iclass 13, count 2 2006.285.14:43:42.08#ibcon#about to read 3, iclass 13, count 2 2006.285.14:43:42.10#ibcon#read 3, iclass 13, count 2 2006.285.14:43:42.10#ibcon#about to read 4, iclass 13, count 2 2006.285.14:43:42.10#ibcon#read 4, iclass 13, count 2 2006.285.14:43:42.11#ibcon#about to read 5, iclass 13, count 2 2006.285.14:43:42.11#ibcon#read 5, iclass 13, count 2 2006.285.14:43:42.11#ibcon#about to read 6, iclass 13, count 2 2006.285.14:43:42.11#ibcon#read 6, iclass 13, count 2 2006.285.14:43:42.11#ibcon#end of sib2, iclass 13, count 2 2006.285.14:43:42.11#ibcon#*after write, iclass 13, count 2 2006.285.14:43:42.11#ibcon#*before return 0, iclass 13, count 2 2006.285.14:43:42.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:43:42.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.14:43:42.11#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.14:43:42.11#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:42.11#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:43:42.22#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:43:42.22#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:43:42.22#ibcon#enter wrdev, iclass 13, count 0 2006.285.14:43:42.23#ibcon#first serial, iclass 13, count 0 2006.285.14:43:42.23#ibcon#enter sib2, iclass 13, count 0 2006.285.14:43:42.23#ibcon#flushed, iclass 13, count 0 2006.285.14:43:42.23#ibcon#about to write, iclass 13, count 0 2006.285.14:43:42.23#ibcon#wrote, iclass 13, count 0 2006.285.14:43:42.23#ibcon#about to read 3, iclass 13, count 0 2006.285.14:43:42.24#ibcon#read 3, iclass 13, count 0 2006.285.14:43:42.24#ibcon#about to read 4, iclass 13, count 0 2006.285.14:43:42.24#ibcon#read 4, iclass 13, count 0 2006.285.14:43:42.24#ibcon#about to read 5, iclass 13, count 0 2006.285.14:43:42.25#ibcon#read 5, iclass 13, count 0 2006.285.14:43:42.25#ibcon#about to read 6, iclass 13, count 0 2006.285.14:43:42.25#ibcon#read 6, iclass 13, count 0 2006.285.14:43:42.25#ibcon#end of sib2, iclass 13, count 0 2006.285.14:43:42.25#ibcon#*mode == 0, iclass 13, count 0 2006.285.14:43:42.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.14:43:42.25#ibcon#[27=USB\r\n] 2006.285.14:43:42.25#ibcon#*before write, iclass 13, count 0 2006.285.14:43:42.25#ibcon#enter sib2, iclass 13, count 0 2006.285.14:43:42.25#ibcon#flushed, iclass 13, count 0 2006.285.14:43:42.25#ibcon#about to write, iclass 13, count 0 2006.285.14:43:42.25#ibcon#wrote, iclass 13, count 0 2006.285.14:43:42.25#ibcon#about to read 3, iclass 13, count 0 2006.285.14:43:42.27#ibcon#read 3, iclass 13, count 0 2006.285.14:43:42.27#ibcon#about to read 4, iclass 13, count 0 2006.285.14:43:42.27#ibcon#read 4, iclass 13, count 0 2006.285.14:43:42.27#ibcon#about to read 5, iclass 13, count 0 2006.285.14:43:42.28#ibcon#read 5, iclass 13, count 0 2006.285.14:43:42.28#ibcon#about to read 6, iclass 13, count 0 2006.285.14:43:42.28#ibcon#read 6, iclass 13, count 0 2006.285.14:43:42.28#ibcon#end of sib2, iclass 13, count 0 2006.285.14:43:42.28#ibcon#*after write, iclass 13, count 0 2006.285.14:43:42.28#ibcon#*before return 0, iclass 13, count 0 2006.285.14:43:42.28#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:43:42.28#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.14:43:42.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.14:43:42.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.14:43:42.28$vck44/vblo=5,709.99 2006.285.14:43:42.28#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.14:43:42.28#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.14:43:42.28#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:42.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:43:42.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:43:42.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:43:42.28#ibcon#enter wrdev, iclass 15, count 0 2006.285.14:43:42.28#ibcon#first serial, iclass 15, count 0 2006.285.14:43:42.28#ibcon#enter sib2, iclass 15, count 0 2006.285.14:43:42.28#ibcon#flushed, iclass 15, count 0 2006.285.14:43:42.28#ibcon#about to write, iclass 15, count 0 2006.285.14:43:42.28#ibcon#wrote, iclass 15, count 0 2006.285.14:43:42.28#ibcon#about to read 3, iclass 15, count 0 2006.285.14:43:42.29#ibcon#read 3, iclass 15, count 0 2006.285.14:43:42.29#ibcon#about to read 4, iclass 15, count 0 2006.285.14:43:42.29#ibcon#read 4, iclass 15, count 0 2006.285.14:43:42.29#ibcon#about to read 5, iclass 15, count 0 2006.285.14:43:42.30#ibcon#read 5, iclass 15, count 0 2006.285.14:43:42.30#ibcon#about to read 6, iclass 15, count 0 2006.285.14:43:42.30#ibcon#read 6, iclass 15, count 0 2006.285.14:43:42.30#ibcon#end of sib2, iclass 15, count 0 2006.285.14:43:42.30#ibcon#*mode == 0, iclass 15, count 0 2006.285.14:43:42.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.14:43:42.30#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.14:43:42.30#ibcon#*before write, iclass 15, count 0 2006.285.14:43:42.30#ibcon#enter sib2, iclass 15, count 0 2006.285.14:43:42.30#ibcon#flushed, iclass 15, count 0 2006.285.14:43:42.30#ibcon#about to write, iclass 15, count 0 2006.285.14:43:42.30#ibcon#wrote, iclass 15, count 0 2006.285.14:43:42.30#ibcon#about to read 3, iclass 15, count 0 2006.285.14:43:42.33#ibcon#read 3, iclass 15, count 0 2006.285.14:43:42.33#ibcon#about to read 4, iclass 15, count 0 2006.285.14:43:42.33#ibcon#read 4, iclass 15, count 0 2006.285.14:43:42.33#ibcon#about to read 5, iclass 15, count 0 2006.285.14:43:42.34#ibcon#read 5, iclass 15, count 0 2006.285.14:43:42.34#ibcon#about to read 6, iclass 15, count 0 2006.285.14:43:42.34#ibcon#read 6, iclass 15, count 0 2006.285.14:43:42.34#ibcon#end of sib2, iclass 15, count 0 2006.285.14:43:42.34#ibcon#*after write, iclass 15, count 0 2006.285.14:43:42.34#ibcon#*before return 0, iclass 15, count 0 2006.285.14:43:42.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:43:42.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.14:43:42.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.14:43:42.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.14:43:42.34$vck44/vb=5,4 2006.285.14:43:42.34#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.14:43:42.34#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.14:43:42.34#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:42.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:43:42.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:43:42.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:43:42.39#ibcon#enter wrdev, iclass 17, count 2 2006.285.14:43:42.39#ibcon#first serial, iclass 17, count 2 2006.285.14:43:42.39#ibcon#enter sib2, iclass 17, count 2 2006.285.14:43:42.40#ibcon#flushed, iclass 17, count 2 2006.285.14:43:42.40#ibcon#about to write, iclass 17, count 2 2006.285.14:43:42.40#ibcon#wrote, iclass 17, count 2 2006.285.14:43:42.40#ibcon#about to read 3, iclass 17, count 2 2006.285.14:43:42.41#ibcon#read 3, iclass 17, count 2 2006.285.14:43:42.41#ibcon#about to read 4, iclass 17, count 2 2006.285.14:43:42.41#ibcon#read 4, iclass 17, count 2 2006.285.14:43:42.41#ibcon#about to read 5, iclass 17, count 2 2006.285.14:43:42.41#ibcon#read 5, iclass 17, count 2 2006.285.14:43:42.42#ibcon#about to read 6, iclass 17, count 2 2006.285.14:43:42.42#ibcon#read 6, iclass 17, count 2 2006.285.14:43:42.42#ibcon#end of sib2, iclass 17, count 2 2006.285.14:43:42.42#ibcon#*mode == 0, iclass 17, count 2 2006.285.14:43:42.42#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.14:43:42.42#ibcon#[27=AT05-04\r\n] 2006.285.14:43:42.42#ibcon#*before write, iclass 17, count 2 2006.285.14:43:42.42#ibcon#enter sib2, iclass 17, count 2 2006.285.14:43:42.42#ibcon#flushed, iclass 17, count 2 2006.285.14:43:42.42#ibcon#about to write, iclass 17, count 2 2006.285.14:43:42.42#ibcon#wrote, iclass 17, count 2 2006.285.14:43:42.42#ibcon#about to read 3, iclass 17, count 2 2006.285.14:43:42.44#ibcon#read 3, iclass 17, count 2 2006.285.14:43:42.44#ibcon#about to read 4, iclass 17, count 2 2006.285.14:43:42.44#ibcon#read 4, iclass 17, count 2 2006.285.14:43:42.44#ibcon#about to read 5, iclass 17, count 2 2006.285.14:43:42.45#ibcon#read 5, iclass 17, count 2 2006.285.14:43:42.45#ibcon#about to read 6, iclass 17, count 2 2006.285.14:43:42.45#ibcon#read 6, iclass 17, count 2 2006.285.14:43:42.45#ibcon#end of sib2, iclass 17, count 2 2006.285.14:43:42.45#ibcon#*after write, iclass 17, count 2 2006.285.14:43:42.45#ibcon#*before return 0, iclass 17, count 2 2006.285.14:43:42.45#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:43:42.45#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.14:43:42.45#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.14:43:42.45#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:42.45#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:43:42.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:43:42.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:43:42.56#ibcon#enter wrdev, iclass 17, count 0 2006.285.14:43:42.56#ibcon#first serial, iclass 17, count 0 2006.285.14:43:42.56#ibcon#enter sib2, iclass 17, count 0 2006.285.14:43:42.57#ibcon#flushed, iclass 17, count 0 2006.285.14:43:42.57#ibcon#about to write, iclass 17, count 0 2006.285.14:43:42.57#ibcon#wrote, iclass 17, count 0 2006.285.14:43:42.57#ibcon#about to read 3, iclass 17, count 0 2006.285.14:43:42.58#ibcon#read 3, iclass 17, count 0 2006.285.14:43:42.58#ibcon#about to read 4, iclass 17, count 0 2006.285.14:43:42.58#ibcon#read 4, iclass 17, count 0 2006.285.14:43:42.58#ibcon#about to read 5, iclass 17, count 0 2006.285.14:43:42.58#ibcon#read 5, iclass 17, count 0 2006.285.14:43:42.59#ibcon#about to read 6, iclass 17, count 0 2006.285.14:43:42.59#ibcon#read 6, iclass 17, count 0 2006.285.14:43:42.59#ibcon#end of sib2, iclass 17, count 0 2006.285.14:43:42.59#ibcon#*mode == 0, iclass 17, count 0 2006.285.14:43:42.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.14:43:42.59#ibcon#[27=USB\r\n] 2006.285.14:43:42.59#ibcon#*before write, iclass 17, count 0 2006.285.14:43:42.59#ibcon#enter sib2, iclass 17, count 0 2006.285.14:43:42.59#ibcon#flushed, iclass 17, count 0 2006.285.14:43:42.59#ibcon#about to write, iclass 17, count 0 2006.285.14:43:42.59#ibcon#wrote, iclass 17, count 0 2006.285.14:43:42.59#ibcon#about to read 3, iclass 17, count 0 2006.285.14:43:42.61#ibcon#read 3, iclass 17, count 0 2006.285.14:43:42.61#ibcon#about to read 4, iclass 17, count 0 2006.285.14:43:42.61#ibcon#read 4, iclass 17, count 0 2006.285.14:43:42.61#ibcon#about to read 5, iclass 17, count 0 2006.285.14:43:42.61#ibcon#read 5, iclass 17, count 0 2006.285.14:43:42.62#ibcon#about to read 6, iclass 17, count 0 2006.285.14:43:42.62#ibcon#read 6, iclass 17, count 0 2006.285.14:43:42.62#ibcon#end of sib2, iclass 17, count 0 2006.285.14:43:42.62#ibcon#*after write, iclass 17, count 0 2006.285.14:43:42.62#ibcon#*before return 0, iclass 17, count 0 2006.285.14:43:42.62#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:43:42.62#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.14:43:42.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.14:43:42.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.14:43:42.62$vck44/vblo=6,719.99 2006.285.14:43:42.62#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.14:43:42.62#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.14:43:42.62#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:42.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:43:42.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:43:42.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:43:42.62#ibcon#enter wrdev, iclass 19, count 0 2006.285.14:43:42.62#ibcon#first serial, iclass 19, count 0 2006.285.14:43:42.62#ibcon#enter sib2, iclass 19, count 0 2006.285.14:43:42.62#ibcon#flushed, iclass 19, count 0 2006.285.14:43:42.62#ibcon#about to write, iclass 19, count 0 2006.285.14:43:42.62#ibcon#wrote, iclass 19, count 0 2006.285.14:43:42.62#ibcon#about to read 3, iclass 19, count 0 2006.285.14:43:42.63#ibcon#read 3, iclass 19, count 0 2006.285.14:43:42.63#ibcon#about to read 4, iclass 19, count 0 2006.285.14:43:42.63#ibcon#read 4, iclass 19, count 0 2006.285.14:43:42.63#ibcon#about to read 5, iclass 19, count 0 2006.285.14:43:42.64#ibcon#read 5, iclass 19, count 0 2006.285.14:43:42.64#ibcon#about to read 6, iclass 19, count 0 2006.285.14:43:42.64#ibcon#read 6, iclass 19, count 0 2006.285.14:43:42.64#ibcon#end of sib2, iclass 19, count 0 2006.285.14:43:42.64#ibcon#*mode == 0, iclass 19, count 0 2006.285.14:43:42.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.14:43:42.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.14:43:42.64#ibcon#*before write, iclass 19, count 0 2006.285.14:43:42.64#ibcon#enter sib2, iclass 19, count 0 2006.285.14:43:42.64#ibcon#flushed, iclass 19, count 0 2006.285.14:43:42.64#ibcon#about to write, iclass 19, count 0 2006.285.14:43:42.64#ibcon#wrote, iclass 19, count 0 2006.285.14:43:42.64#ibcon#about to read 3, iclass 19, count 0 2006.285.14:43:42.67#ibcon#read 3, iclass 19, count 0 2006.285.14:43:42.67#ibcon#about to read 4, iclass 19, count 0 2006.285.14:43:42.67#ibcon#read 4, iclass 19, count 0 2006.285.14:43:42.67#ibcon#about to read 5, iclass 19, count 0 2006.285.14:43:42.67#ibcon#read 5, iclass 19, count 0 2006.285.14:43:42.68#ibcon#about to read 6, iclass 19, count 0 2006.285.14:43:42.68#ibcon#read 6, iclass 19, count 0 2006.285.14:43:42.68#ibcon#end of sib2, iclass 19, count 0 2006.285.14:43:42.68#ibcon#*after write, iclass 19, count 0 2006.285.14:43:42.68#ibcon#*before return 0, iclass 19, count 0 2006.285.14:43:42.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:43:42.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.14:43:42.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.14:43:42.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.14:43:42.68$vck44/vb=6,3 2006.285.14:43:42.68#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.14:43:42.68#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.14:43:42.68#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:42.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:43:42.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:43:42.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:43:42.73#ibcon#enter wrdev, iclass 21, count 2 2006.285.14:43:42.73#ibcon#first serial, iclass 21, count 2 2006.285.14:43:42.73#ibcon#enter sib2, iclass 21, count 2 2006.285.14:43:42.74#ibcon#flushed, iclass 21, count 2 2006.285.14:43:42.74#ibcon#about to write, iclass 21, count 2 2006.285.14:43:42.74#ibcon#wrote, iclass 21, count 2 2006.285.14:43:42.74#ibcon#about to read 3, iclass 21, count 2 2006.285.14:43:42.75#ibcon#read 3, iclass 21, count 2 2006.285.14:43:42.75#ibcon#about to read 4, iclass 21, count 2 2006.285.14:43:42.75#ibcon#read 4, iclass 21, count 2 2006.285.14:43:42.75#ibcon#about to read 5, iclass 21, count 2 2006.285.14:43:42.75#ibcon#read 5, iclass 21, count 2 2006.285.14:43:42.76#ibcon#about to read 6, iclass 21, count 2 2006.285.14:43:42.76#ibcon#read 6, iclass 21, count 2 2006.285.14:43:42.76#ibcon#end of sib2, iclass 21, count 2 2006.285.14:43:42.76#ibcon#*mode == 0, iclass 21, count 2 2006.285.14:43:42.76#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.14:43:42.76#ibcon#[27=AT06-03\r\n] 2006.285.14:43:42.76#ibcon#*before write, iclass 21, count 2 2006.285.14:43:42.76#ibcon#enter sib2, iclass 21, count 2 2006.285.14:43:42.76#ibcon#flushed, iclass 21, count 2 2006.285.14:43:42.76#ibcon#about to write, iclass 21, count 2 2006.285.14:43:42.76#ibcon#wrote, iclass 21, count 2 2006.285.14:43:42.76#ibcon#about to read 3, iclass 21, count 2 2006.285.14:43:42.78#ibcon#read 3, iclass 21, count 2 2006.285.14:43:42.78#ibcon#about to read 4, iclass 21, count 2 2006.285.14:43:42.79#ibcon#read 4, iclass 21, count 2 2006.285.14:43:42.79#ibcon#about to read 5, iclass 21, count 2 2006.285.14:43:42.79#ibcon#read 5, iclass 21, count 2 2006.285.14:43:42.79#ibcon#about to read 6, iclass 21, count 2 2006.285.14:43:42.79#ibcon#read 6, iclass 21, count 2 2006.285.14:43:42.79#ibcon#end of sib2, iclass 21, count 2 2006.285.14:43:42.79#ibcon#*after write, iclass 21, count 2 2006.285.14:43:42.79#ibcon#*before return 0, iclass 21, count 2 2006.285.14:43:42.79#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:43:42.79#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.14:43:42.79#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.14:43:42.79#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:42.79#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:43:42.90#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:43:42.90#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:43:42.90#ibcon#enter wrdev, iclass 21, count 0 2006.285.14:43:42.91#ibcon#first serial, iclass 21, count 0 2006.285.14:43:42.91#ibcon#enter sib2, iclass 21, count 0 2006.285.14:43:42.91#ibcon#flushed, iclass 21, count 0 2006.285.14:43:42.91#ibcon#about to write, iclass 21, count 0 2006.285.14:43:42.91#ibcon#wrote, iclass 21, count 0 2006.285.14:43:42.91#ibcon#about to read 3, iclass 21, count 0 2006.285.14:43:42.92#ibcon#read 3, iclass 21, count 0 2006.285.14:43:42.92#ibcon#about to read 4, iclass 21, count 0 2006.285.14:43:42.92#ibcon#read 4, iclass 21, count 0 2006.285.14:43:42.93#ibcon#about to read 5, iclass 21, count 0 2006.285.14:43:42.93#ibcon#read 5, iclass 21, count 0 2006.285.14:43:42.93#ibcon#about to read 6, iclass 21, count 0 2006.285.14:43:42.93#ibcon#read 6, iclass 21, count 0 2006.285.14:43:42.93#ibcon#end of sib2, iclass 21, count 0 2006.285.14:43:42.93#ibcon#*mode == 0, iclass 21, count 0 2006.285.14:43:42.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.14:43:42.93#ibcon#[27=USB\r\n] 2006.285.14:43:42.93#ibcon#*before write, iclass 21, count 0 2006.285.14:43:42.93#ibcon#enter sib2, iclass 21, count 0 2006.285.14:43:42.93#ibcon#flushed, iclass 21, count 0 2006.285.14:43:42.93#ibcon#about to write, iclass 21, count 0 2006.285.14:43:42.93#ibcon#wrote, iclass 21, count 0 2006.285.14:43:42.93#ibcon#about to read 3, iclass 21, count 0 2006.285.14:43:42.95#ibcon#read 3, iclass 21, count 0 2006.285.14:43:42.95#ibcon#about to read 4, iclass 21, count 0 2006.285.14:43:42.95#ibcon#read 4, iclass 21, count 0 2006.285.14:43:42.96#ibcon#about to read 5, iclass 21, count 0 2006.285.14:43:42.96#ibcon#read 5, iclass 21, count 0 2006.285.14:43:42.96#ibcon#about to read 6, iclass 21, count 0 2006.285.14:43:42.96#ibcon#read 6, iclass 21, count 0 2006.285.14:43:42.96#ibcon#end of sib2, iclass 21, count 0 2006.285.14:43:42.96#ibcon#*after write, iclass 21, count 0 2006.285.14:43:42.96#ibcon#*before return 0, iclass 21, count 0 2006.285.14:43:42.96#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:43:42.96#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.14:43:42.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.14:43:42.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.14:43:42.96$vck44/vblo=7,734.99 2006.285.14:43:42.96#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.14:43:42.96#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.14:43:42.96#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:42.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:43:42.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:43:42.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:43:42.96#ibcon#enter wrdev, iclass 23, count 0 2006.285.14:43:42.96#ibcon#first serial, iclass 23, count 0 2006.285.14:43:42.96#ibcon#enter sib2, iclass 23, count 0 2006.285.14:43:42.96#ibcon#flushed, iclass 23, count 0 2006.285.14:43:42.96#ibcon#about to write, iclass 23, count 0 2006.285.14:43:42.96#ibcon#wrote, iclass 23, count 0 2006.285.14:43:42.96#ibcon#about to read 3, iclass 23, count 0 2006.285.14:43:42.97#ibcon#read 3, iclass 23, count 0 2006.285.14:43:43.07#ibcon#about to read 4, iclass 23, count 0 2006.285.14:43:43.07#ibcon#read 4, iclass 23, count 0 2006.285.14:43:43.07#ibcon#about to read 5, iclass 23, count 0 2006.285.14:43:43.07#ibcon#read 5, iclass 23, count 0 2006.285.14:43:43.07#ibcon#about to read 6, iclass 23, count 0 2006.285.14:43:43.07#ibcon#read 6, iclass 23, count 0 2006.285.14:43:43.07#ibcon#end of sib2, iclass 23, count 0 2006.285.14:43:43.07#ibcon#*mode == 0, iclass 23, count 0 2006.285.14:43:43.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.14:43:43.07#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.14:43:43.07#ibcon#*before write, iclass 23, count 0 2006.285.14:43:43.07#ibcon#enter sib2, iclass 23, count 0 2006.285.14:43:43.07#ibcon#flushed, iclass 23, count 0 2006.285.14:43:43.07#ibcon#about to write, iclass 23, count 0 2006.285.14:43:43.07#ibcon#wrote, iclass 23, count 0 2006.285.14:43:43.07#ibcon#about to read 3, iclass 23, count 0 2006.285.14:43:43.10#ibcon#read 3, iclass 23, count 0 2006.285.14:43:43.10#ibcon#about to read 4, iclass 23, count 0 2006.285.14:43:43.10#ibcon#read 4, iclass 23, count 0 2006.285.14:43:43.10#ibcon#about to read 5, iclass 23, count 0 2006.285.14:43:43.11#ibcon#read 5, iclass 23, count 0 2006.285.14:43:43.11#ibcon#about to read 6, iclass 23, count 0 2006.285.14:43:43.11#ibcon#read 6, iclass 23, count 0 2006.285.14:43:43.11#ibcon#end of sib2, iclass 23, count 0 2006.285.14:43:43.11#ibcon#*after write, iclass 23, count 0 2006.285.14:43:43.11#ibcon#*before return 0, iclass 23, count 0 2006.285.14:43:43.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:43:43.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.14:43:43.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.14:43:43.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.14:43:43.11$vck44/vb=7,4 2006.285.14:43:43.11#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.14:43:43.11#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.14:43:43.11#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:43.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:43:43.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:43:43.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:43:43.11#ibcon#enter wrdev, iclass 25, count 2 2006.285.14:43:43.11#ibcon#first serial, iclass 25, count 2 2006.285.14:43:43.11#ibcon#enter sib2, iclass 25, count 2 2006.285.14:43:43.11#ibcon#flushed, iclass 25, count 2 2006.285.14:43:43.11#ibcon#about to write, iclass 25, count 2 2006.285.14:43:43.11#ibcon#wrote, iclass 25, count 2 2006.285.14:43:43.11#ibcon#about to read 3, iclass 25, count 2 2006.285.14:43:43.12#ibcon#read 3, iclass 25, count 2 2006.285.14:43:43.12#ibcon#about to read 4, iclass 25, count 2 2006.285.14:43:43.12#ibcon#read 4, iclass 25, count 2 2006.285.14:43:43.12#ibcon#about to read 5, iclass 25, count 2 2006.285.14:43:43.13#ibcon#read 5, iclass 25, count 2 2006.285.14:43:43.13#ibcon#about to read 6, iclass 25, count 2 2006.285.14:43:43.13#ibcon#read 6, iclass 25, count 2 2006.285.14:43:43.13#ibcon#end of sib2, iclass 25, count 2 2006.285.14:43:43.13#ibcon#*mode == 0, iclass 25, count 2 2006.285.14:43:43.13#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.14:43:43.13#ibcon#[27=AT07-04\r\n] 2006.285.14:43:43.13#ibcon#*before write, iclass 25, count 2 2006.285.14:43:43.13#ibcon#enter sib2, iclass 25, count 2 2006.285.14:43:43.13#ibcon#flushed, iclass 25, count 2 2006.285.14:43:43.13#ibcon#about to write, iclass 25, count 2 2006.285.14:43:43.13#ibcon#wrote, iclass 25, count 2 2006.285.14:43:43.13#ibcon#about to read 3, iclass 25, count 2 2006.285.14:43:43.15#ibcon#read 3, iclass 25, count 2 2006.285.14:43:43.15#ibcon#about to read 4, iclass 25, count 2 2006.285.14:43:43.15#ibcon#read 4, iclass 25, count 2 2006.285.14:43:43.15#ibcon#about to read 5, iclass 25, count 2 2006.285.14:43:43.16#ibcon#read 5, iclass 25, count 2 2006.285.14:43:43.16#ibcon#about to read 6, iclass 25, count 2 2006.285.14:43:43.16#ibcon#read 6, iclass 25, count 2 2006.285.14:43:43.16#ibcon#end of sib2, iclass 25, count 2 2006.285.14:43:43.16#ibcon#*after write, iclass 25, count 2 2006.285.14:43:43.16#ibcon#*before return 0, iclass 25, count 2 2006.285.14:43:43.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:43:43.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.14:43:43.16#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.14:43:43.16#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:43.16#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:43:43.27#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:43:43.27#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:43:43.27#ibcon#enter wrdev, iclass 25, count 0 2006.285.14:43:43.28#ibcon#first serial, iclass 25, count 0 2006.285.14:43:43.28#ibcon#enter sib2, iclass 25, count 0 2006.285.14:43:43.28#ibcon#flushed, iclass 25, count 0 2006.285.14:43:43.28#ibcon#about to write, iclass 25, count 0 2006.285.14:43:43.28#ibcon#wrote, iclass 25, count 0 2006.285.14:43:43.28#ibcon#about to read 3, iclass 25, count 0 2006.285.14:43:43.29#ibcon#read 3, iclass 25, count 0 2006.285.14:43:43.29#ibcon#about to read 4, iclass 25, count 0 2006.285.14:43:43.29#ibcon#read 4, iclass 25, count 0 2006.285.14:43:43.30#ibcon#about to read 5, iclass 25, count 0 2006.285.14:43:43.30#ibcon#read 5, iclass 25, count 0 2006.285.14:43:43.30#ibcon#about to read 6, iclass 25, count 0 2006.285.14:43:43.30#ibcon#read 6, iclass 25, count 0 2006.285.14:43:43.30#ibcon#end of sib2, iclass 25, count 0 2006.285.14:43:43.30#ibcon#*mode == 0, iclass 25, count 0 2006.285.14:43:43.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.14:43:43.30#ibcon#[27=USB\r\n] 2006.285.14:43:43.30#ibcon#*before write, iclass 25, count 0 2006.285.14:43:43.30#ibcon#enter sib2, iclass 25, count 0 2006.285.14:43:43.30#ibcon#flushed, iclass 25, count 0 2006.285.14:43:43.30#ibcon#about to write, iclass 25, count 0 2006.285.14:43:43.30#ibcon#wrote, iclass 25, count 0 2006.285.14:43:43.30#ibcon#about to read 3, iclass 25, count 0 2006.285.14:43:43.32#ibcon#read 3, iclass 25, count 0 2006.285.14:43:43.32#ibcon#about to read 4, iclass 25, count 0 2006.285.14:43:43.33#ibcon#read 4, iclass 25, count 0 2006.285.14:43:43.33#ibcon#about to read 5, iclass 25, count 0 2006.285.14:43:43.33#ibcon#read 5, iclass 25, count 0 2006.285.14:43:43.33#ibcon#about to read 6, iclass 25, count 0 2006.285.14:43:43.33#ibcon#read 6, iclass 25, count 0 2006.285.14:43:43.33#ibcon#end of sib2, iclass 25, count 0 2006.285.14:43:43.33#ibcon#*after write, iclass 25, count 0 2006.285.14:43:43.33#ibcon#*before return 0, iclass 25, count 0 2006.285.14:43:43.33#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:43:43.33#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.14:43:43.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.14:43:43.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.14:43:43.33$vck44/vblo=8,744.99 2006.285.14:43:43.33#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.14:43:43.33#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.14:43:43.33#ibcon#ireg 17 cls_cnt 0 2006.285.14:43:43.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:43:43.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:43:43.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:43:43.33#ibcon#enter wrdev, iclass 27, count 0 2006.285.14:43:43.33#ibcon#first serial, iclass 27, count 0 2006.285.14:43:43.33#ibcon#enter sib2, iclass 27, count 0 2006.285.14:43:43.33#ibcon#flushed, iclass 27, count 0 2006.285.14:43:43.33#ibcon#about to write, iclass 27, count 0 2006.285.14:43:43.33#ibcon#wrote, iclass 27, count 0 2006.285.14:43:43.33#ibcon#about to read 3, iclass 27, count 0 2006.285.14:43:43.34#ibcon#read 3, iclass 27, count 0 2006.285.14:43:43.34#ibcon#about to read 4, iclass 27, count 0 2006.285.14:43:43.34#ibcon#read 4, iclass 27, count 0 2006.285.14:43:43.35#ibcon#about to read 5, iclass 27, count 0 2006.285.14:43:43.35#ibcon#read 5, iclass 27, count 0 2006.285.14:43:43.35#ibcon#about to read 6, iclass 27, count 0 2006.285.14:43:43.35#ibcon#read 6, iclass 27, count 0 2006.285.14:43:43.35#ibcon#end of sib2, iclass 27, count 0 2006.285.14:43:43.35#ibcon#*mode == 0, iclass 27, count 0 2006.285.14:43:43.35#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.14:43:43.35#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.14:43:43.35#ibcon#*before write, iclass 27, count 0 2006.285.14:43:43.35#ibcon#enter sib2, iclass 27, count 0 2006.285.14:43:43.35#ibcon#flushed, iclass 27, count 0 2006.285.14:43:43.35#ibcon#about to write, iclass 27, count 0 2006.285.14:43:43.35#ibcon#wrote, iclass 27, count 0 2006.285.14:43:43.35#ibcon#about to read 3, iclass 27, count 0 2006.285.14:43:43.38#ibcon#read 3, iclass 27, count 0 2006.285.14:43:43.38#ibcon#about to read 4, iclass 27, count 0 2006.285.14:43:43.38#ibcon#read 4, iclass 27, count 0 2006.285.14:43:43.38#ibcon#about to read 5, iclass 27, count 0 2006.285.14:43:43.39#ibcon#read 5, iclass 27, count 0 2006.285.14:43:43.39#ibcon#about to read 6, iclass 27, count 0 2006.285.14:43:43.39#ibcon#read 6, iclass 27, count 0 2006.285.14:43:43.39#ibcon#end of sib2, iclass 27, count 0 2006.285.14:43:43.39#ibcon#*after write, iclass 27, count 0 2006.285.14:43:43.39#ibcon#*before return 0, iclass 27, count 0 2006.285.14:43:43.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:43:43.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.14:43:43.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.14:43:43.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.14:43:43.39$vck44/vb=8,4 2006.285.14:43:43.39#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.14:43:43.39#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.14:43:43.39#ibcon#ireg 11 cls_cnt 2 2006.285.14:43:43.39#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:43:43.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:43:43.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:43:43.44#ibcon#enter wrdev, iclass 29, count 2 2006.285.14:43:43.44#ibcon#first serial, iclass 29, count 2 2006.285.14:43:43.44#ibcon#enter sib2, iclass 29, count 2 2006.285.14:43:43.45#ibcon#flushed, iclass 29, count 2 2006.285.14:43:43.45#ibcon#about to write, iclass 29, count 2 2006.285.14:43:43.45#ibcon#wrote, iclass 29, count 2 2006.285.14:43:43.45#ibcon#about to read 3, iclass 29, count 2 2006.285.14:43:43.46#ibcon#read 3, iclass 29, count 2 2006.285.14:43:43.46#ibcon#about to read 4, iclass 29, count 2 2006.285.14:43:43.46#ibcon#read 4, iclass 29, count 2 2006.285.14:43:43.46#ibcon#about to read 5, iclass 29, count 2 2006.285.14:43:43.46#ibcon#read 5, iclass 29, count 2 2006.285.14:43:43.47#ibcon#about to read 6, iclass 29, count 2 2006.285.14:43:43.47#ibcon#read 6, iclass 29, count 2 2006.285.14:43:43.47#ibcon#end of sib2, iclass 29, count 2 2006.285.14:43:43.47#ibcon#*mode == 0, iclass 29, count 2 2006.285.14:43:43.47#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.14:43:43.47#ibcon#[27=AT08-04\r\n] 2006.285.14:43:43.47#ibcon#*before write, iclass 29, count 2 2006.285.14:43:43.47#ibcon#enter sib2, iclass 29, count 2 2006.285.14:43:43.47#ibcon#flushed, iclass 29, count 2 2006.285.14:43:43.47#ibcon#about to write, iclass 29, count 2 2006.285.14:43:43.47#ibcon#wrote, iclass 29, count 2 2006.285.14:43:43.47#ibcon#about to read 3, iclass 29, count 2 2006.285.14:43:43.49#ibcon#read 3, iclass 29, count 2 2006.285.14:43:43.49#ibcon#about to read 4, iclass 29, count 2 2006.285.14:43:43.49#ibcon#read 4, iclass 29, count 2 2006.285.14:43:43.49#ibcon#about to read 5, iclass 29, count 2 2006.285.14:43:43.49#ibcon#read 5, iclass 29, count 2 2006.285.14:43:43.50#ibcon#about to read 6, iclass 29, count 2 2006.285.14:43:43.50#ibcon#read 6, iclass 29, count 2 2006.285.14:43:43.50#ibcon#end of sib2, iclass 29, count 2 2006.285.14:43:43.50#ibcon#*after write, iclass 29, count 2 2006.285.14:43:43.50#ibcon#*before return 0, iclass 29, count 2 2006.285.14:43:43.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:43:43.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.14:43:43.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.14:43:43.50#ibcon#ireg 7 cls_cnt 0 2006.285.14:43:43.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:43:43.61#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:43:43.61#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:43:43.61#ibcon#enter wrdev, iclass 29, count 0 2006.285.14:43:43.61#ibcon#first serial, iclass 29, count 0 2006.285.14:43:43.61#ibcon#enter sib2, iclass 29, count 0 2006.285.14:43:43.62#ibcon#flushed, iclass 29, count 0 2006.285.14:43:43.62#ibcon#about to write, iclass 29, count 0 2006.285.14:43:43.62#ibcon#wrote, iclass 29, count 0 2006.285.14:43:43.62#ibcon#about to read 3, iclass 29, count 0 2006.285.14:43:43.63#ibcon#read 3, iclass 29, count 0 2006.285.14:43:43.63#ibcon#about to read 4, iclass 29, count 0 2006.285.14:43:43.63#ibcon#read 4, iclass 29, count 0 2006.285.14:43:43.63#ibcon#about to read 5, iclass 29, count 0 2006.285.14:43:43.63#ibcon#read 5, iclass 29, count 0 2006.285.14:43:43.64#ibcon#about to read 6, iclass 29, count 0 2006.285.14:43:43.64#ibcon#read 6, iclass 29, count 0 2006.285.14:43:43.64#ibcon#end of sib2, iclass 29, count 0 2006.285.14:43:43.64#ibcon#*mode == 0, iclass 29, count 0 2006.285.14:43:43.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.14:43:43.64#ibcon#[27=USB\r\n] 2006.285.14:43:43.64#ibcon#*before write, iclass 29, count 0 2006.285.14:43:43.64#ibcon#enter sib2, iclass 29, count 0 2006.285.14:43:43.64#ibcon#flushed, iclass 29, count 0 2006.285.14:43:43.64#ibcon#about to write, iclass 29, count 0 2006.285.14:43:43.64#ibcon#wrote, iclass 29, count 0 2006.285.14:43:43.64#ibcon#about to read 3, iclass 29, count 0 2006.285.14:43:43.66#ibcon#read 3, iclass 29, count 0 2006.285.14:43:43.66#ibcon#about to read 4, iclass 29, count 0 2006.285.14:43:43.66#ibcon#read 4, iclass 29, count 0 2006.285.14:43:43.66#ibcon#about to read 5, iclass 29, count 0 2006.285.14:43:43.66#ibcon#read 5, iclass 29, count 0 2006.285.14:43:43.67#ibcon#about to read 6, iclass 29, count 0 2006.285.14:43:43.67#ibcon#read 6, iclass 29, count 0 2006.285.14:43:43.67#ibcon#end of sib2, iclass 29, count 0 2006.285.14:43:43.67#ibcon#*after write, iclass 29, count 0 2006.285.14:43:43.67#ibcon#*before return 0, iclass 29, count 0 2006.285.14:43:43.67#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:43:43.67#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.14:43:43.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.14:43:43.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.14:43:43.67$vck44/vabw=wide 2006.285.14:43:43.67#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.14:43:43.67#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.14:43:43.67#ibcon#ireg 8 cls_cnt 0 2006.285.14:43:43.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:43:43.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:43:43.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:43:43.67#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:43:43.67#ibcon#first serial, iclass 31, count 0 2006.285.14:43:43.67#ibcon#enter sib2, iclass 31, count 0 2006.285.14:43:43.67#ibcon#flushed, iclass 31, count 0 2006.285.14:43:43.67#ibcon#about to write, iclass 31, count 0 2006.285.14:43:43.67#ibcon#wrote, iclass 31, count 0 2006.285.14:43:43.67#ibcon#about to read 3, iclass 31, count 0 2006.285.14:43:43.68#ibcon#read 3, iclass 31, count 0 2006.285.14:43:43.68#ibcon#about to read 4, iclass 31, count 0 2006.285.14:43:43.68#ibcon#read 4, iclass 31, count 0 2006.285.14:43:43.68#ibcon#about to read 5, iclass 31, count 0 2006.285.14:43:43.69#ibcon#read 5, iclass 31, count 0 2006.285.14:43:43.69#ibcon#about to read 6, iclass 31, count 0 2006.285.14:43:43.69#ibcon#read 6, iclass 31, count 0 2006.285.14:43:43.69#ibcon#end of sib2, iclass 31, count 0 2006.285.14:43:43.69#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:43:43.69#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:43:43.69#ibcon#[25=BW32\r\n] 2006.285.14:43:43.69#ibcon#*before write, iclass 31, count 0 2006.285.14:43:43.69#ibcon#enter sib2, iclass 31, count 0 2006.285.14:43:43.69#ibcon#flushed, iclass 31, count 0 2006.285.14:43:43.69#ibcon#about to write, iclass 31, count 0 2006.285.14:43:43.69#ibcon#wrote, iclass 31, count 0 2006.285.14:43:43.69#ibcon#about to read 3, iclass 31, count 0 2006.285.14:43:43.71#ibcon#read 3, iclass 31, count 0 2006.285.14:43:43.71#ibcon#about to read 4, iclass 31, count 0 2006.285.14:43:43.71#ibcon#read 4, iclass 31, count 0 2006.285.14:43:43.71#ibcon#about to read 5, iclass 31, count 0 2006.285.14:43:43.71#ibcon#read 5, iclass 31, count 0 2006.285.14:43:43.72#ibcon#about to read 6, iclass 31, count 0 2006.285.14:43:43.72#ibcon#read 6, iclass 31, count 0 2006.285.14:43:43.72#ibcon#end of sib2, iclass 31, count 0 2006.285.14:43:43.72#ibcon#*after write, iclass 31, count 0 2006.285.14:43:43.72#ibcon#*before return 0, iclass 31, count 0 2006.285.14:43:43.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:43:43.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.14:43:43.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:43:43.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:43:43.72$vck44/vbbw=wide 2006.285.14:43:43.72#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.14:43:43.72#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.14:43:43.72#ibcon#ireg 8 cls_cnt 0 2006.285.14:43:43.72#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:43:43.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:43:43.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:43:43.78#ibcon#enter wrdev, iclass 33, count 0 2006.285.14:43:43.79#ibcon#first serial, iclass 33, count 0 2006.285.14:43:43.79#ibcon#enter sib2, iclass 33, count 0 2006.285.14:43:43.79#ibcon#flushed, iclass 33, count 0 2006.285.14:43:43.79#ibcon#about to write, iclass 33, count 0 2006.285.14:43:43.79#ibcon#wrote, iclass 33, count 0 2006.285.14:43:43.79#ibcon#about to read 3, iclass 33, count 0 2006.285.14:43:43.80#ibcon#read 3, iclass 33, count 0 2006.285.14:43:43.80#ibcon#about to read 4, iclass 33, count 0 2006.285.14:43:43.80#ibcon#read 4, iclass 33, count 0 2006.285.14:43:43.80#ibcon#about to read 5, iclass 33, count 0 2006.285.14:43:43.80#ibcon#read 5, iclass 33, count 0 2006.285.14:43:43.81#ibcon#about to read 6, iclass 33, count 0 2006.285.14:43:43.81#ibcon#read 6, iclass 33, count 0 2006.285.14:43:43.81#ibcon#end of sib2, iclass 33, count 0 2006.285.14:43:43.81#ibcon#*mode == 0, iclass 33, count 0 2006.285.14:43:43.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.14:43:43.81#ibcon#[27=BW32\r\n] 2006.285.14:43:43.81#ibcon#*before write, iclass 33, count 0 2006.285.14:43:43.81#ibcon#enter sib2, iclass 33, count 0 2006.285.14:43:43.81#ibcon#flushed, iclass 33, count 0 2006.285.14:43:43.81#ibcon#about to write, iclass 33, count 0 2006.285.14:43:43.81#ibcon#wrote, iclass 33, count 0 2006.285.14:43:43.81#ibcon#about to read 3, iclass 33, count 0 2006.285.14:43:43.83#ibcon#read 3, iclass 33, count 0 2006.285.14:43:43.83#ibcon#about to read 4, iclass 33, count 0 2006.285.14:43:43.84#ibcon#read 4, iclass 33, count 0 2006.285.14:43:43.84#ibcon#about to read 5, iclass 33, count 0 2006.285.14:43:43.84#ibcon#read 5, iclass 33, count 0 2006.285.14:43:43.84#ibcon#about to read 6, iclass 33, count 0 2006.285.14:43:43.84#ibcon#read 6, iclass 33, count 0 2006.285.14:43:43.84#ibcon#end of sib2, iclass 33, count 0 2006.285.14:43:43.84#ibcon#*after write, iclass 33, count 0 2006.285.14:43:43.84#ibcon#*before return 0, iclass 33, count 0 2006.285.14:43:43.84#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:43:43.84#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:43:43.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.14:43:43.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.14:43:43.84$setupk4/ifdk4 2006.285.14:43:43.84$ifdk4/lo= 2006.285.14:43:43.84$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.14:43:43.84$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.14:43:43.84$ifdk4/patch= 2006.285.14:43:43.84$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.14:43:43.84$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.14:43:43.84$setupk4/!*+20s 2006.285.14:43:51.88#abcon#<5=/04 2.1 4.3 19.17 941015.0\r\n> 2006.285.14:43:51.90#abcon#{5=INTERFACE CLEAR} 2006.285.14:43:51.96#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:43:56.14#trakl#Source acquired 2006.285.14:43:56.15#flagr#flagr/antenna,acquired 2006.285.14:43:57.54$setupk4/"tpicd 2006.285.14:43:57.55$setupk4/echo=off 2006.285.14:43:57.55$setupk4/xlog=off 2006.285.14:43:57.55:!2006.285.14:48:32 2006.285.14:48:32.01:preob 2006.285.14:48:33.14/onsource/TRACKING 2006.285.14:48:33.14:!2006.285.14:48:42 2006.285.14:48:42.00:"tape 2006.285.14:48:42.00:"st=record 2006.285.14:48:42.00:data_valid=on 2006.285.14:48:42.00:midob 2006.285.14:48:42.14/onsource/TRACKING 2006.285.14:48:42.15/wx/19.16,1015.0,93 2006.285.14:48:42.35/cable/+6.4995E-03 2006.285.14:48:43.44/va/01,07,usb,yes,32,35 2006.285.14:48:43.44/va/02,06,usb,yes,32,33 2006.285.14:48:43.44/va/03,07,usb,yes,32,34 2006.285.14:48:43.44/va/04,06,usb,yes,33,35 2006.285.14:48:43.44/va/05,03,usb,yes,33,33 2006.285.14:48:43.44/va/06,04,usb,yes,29,29 2006.285.14:48:43.44/va/07,04,usb,yes,30,31 2006.285.14:48:43.44/va/08,03,usb,yes,31,37 2006.285.14:48:43.67/valo/01,524.99,yes,locked 2006.285.14:48:43.67/valo/02,534.99,yes,locked 2006.285.14:48:43.67/valo/03,564.99,yes,locked 2006.285.14:48:43.67/valo/04,624.99,yes,locked 2006.285.14:48:43.67/valo/05,734.99,yes,locked 2006.285.14:48:43.67/valo/06,814.99,yes,locked 2006.285.14:48:43.67/valo/07,864.99,yes,locked 2006.285.14:48:43.67/valo/08,884.99,yes,locked 2006.285.14:48:44.76/vb/01,04,usb,yes,30,28 2006.285.14:48:44.76/vb/02,05,usb,yes,29,29 2006.285.14:48:44.76/vb/03,04,usb,yes,30,33 2006.285.14:48:44.76/vb/04,05,usb,yes,30,29 2006.285.14:48:44.76/vb/05,04,usb,yes,26,29 2006.285.14:48:44.76/vb/06,03,usb,yes,38,34 2006.285.14:48:44.76/vb/07,04,usb,yes,31,31 2006.285.14:48:44.76/vb/08,04,usb,yes,28,31 2006.285.14:48:44.99/vblo/01,629.99,yes,locked 2006.285.14:48:44.99/vblo/02,634.99,yes,locked 2006.285.14:48:44.99/vblo/03,649.99,yes,locked 2006.285.14:48:44.99/vblo/04,679.99,yes,locked 2006.285.14:48:44.99/vblo/05,709.99,yes,locked 2006.285.14:48:44.99/vblo/06,719.99,yes,locked 2006.285.14:48:44.99/vblo/07,734.99,yes,locked 2006.285.14:48:44.99/vblo/08,744.99,yes,locked 2006.285.14:48:45.14/vabw/8 2006.285.14:48:45.29/vbbw/8 2006.285.14:48:45.38/xfe/off,on,12.0 2006.285.14:48:45.79/ifatt/23,28,28,28 2006.285.14:48:46.07/fmout-gps/S +2.76E-07 2006.285.14:48:46.09:!2006.285.14:49:32 2006.285.14:49:32.00:data_valid=off 2006.285.14:49:32.00:"et 2006.285.14:49:32.00:!+3s 2006.285.14:49:35.01:"tape 2006.285.14:49:35.01:postob 2006.285.14:49:35.24/cable/+6.4988E-03 2006.285.14:49:35.24/wx/19.15,1015.0,93 2006.285.14:49:36.07/fmout-gps/S +2.77E-07 2006.285.14:49:36.07:scan_name=285-1452,jd0610,110 2006.285.14:49:36.07:source=0528+134,053056.42,133155.1,2000.0,cw 2006.285.14:49:37.14#flagr#flagr/antenna,new-source 2006.285.14:49:37.14:checkk5 2006.285.14:49:37.78/chk_autoobs//k5ts1/ autoobs is running! 2006.285.14:49:38.18/chk_autoobs//k5ts2/ autoobs is running! 2006.285.14:49:38.67/chk_autoobs//k5ts3/ autoobs is running! 2006.285.14:49:39.24/chk_autoobs//k5ts4/ autoobs is running! 2006.285.14:49:39.77/chk_obsdata//k5ts1/T2851448??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.14:49:40.22/chk_obsdata//k5ts2/T2851448??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.14:49:40.66/chk_obsdata//k5ts3/T2851448??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.14:49:41.04/chk_obsdata//k5ts4/T2851448??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.14:49:42.03/k5log//k5ts1_log_newline 2006.285.14:49:42.82/k5log//k5ts2_log_newline 2006.285.14:49:43.77/k5log//k5ts3_log_newline 2006.285.14:49:44.52/k5log//k5ts4_log_newline 2006.285.14:49:44.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.14:49:44.54:setupk4=1 2006.285.14:49:44.54$setupk4/echo=on 2006.285.14:49:44.54$setupk4/pcalon 2006.285.14:49:44.54$pcalon/"no phase cal control is implemented here 2006.285.14:49:44.54$setupk4/"tpicd=stop 2006.285.14:49:44.54$setupk4/"rec=synch_on 2006.285.14:49:44.54$setupk4/"rec_mode=128 2006.285.14:49:44.54$setupk4/!* 2006.285.14:49:44.54$setupk4/recpk4 2006.285.14:49:44.54$recpk4/recpatch= 2006.285.14:49:44.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.14:49:44.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.14:49:44.55$setupk4/vck44 2006.285.14:49:44.55$vck44/valo=1,524.99 2006.285.14:49:44.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.14:49:44.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.14:49:44.55#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:44.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:49:44.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:49:44.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:49:44.55#ibcon#enter wrdev, iclass 34, count 0 2006.285.14:49:44.55#ibcon#first serial, iclass 34, count 0 2006.285.14:49:44.55#ibcon#enter sib2, iclass 34, count 0 2006.285.14:49:44.55#ibcon#flushed, iclass 34, count 0 2006.285.14:49:44.55#ibcon#about to write, iclass 34, count 0 2006.285.14:49:44.55#ibcon#wrote, iclass 34, count 0 2006.285.14:49:44.55#ibcon#about to read 3, iclass 34, count 0 2006.285.14:49:44.56#ibcon#read 3, iclass 34, count 0 2006.285.14:49:44.56#ibcon#about to read 4, iclass 34, count 0 2006.285.14:49:44.56#ibcon#read 4, iclass 34, count 0 2006.285.14:49:44.56#ibcon#about to read 5, iclass 34, count 0 2006.285.14:49:44.56#ibcon#read 5, iclass 34, count 0 2006.285.14:49:44.56#ibcon#about to read 6, iclass 34, count 0 2006.285.14:49:44.56#ibcon#read 6, iclass 34, count 0 2006.285.14:49:44.56#ibcon#end of sib2, iclass 34, count 0 2006.285.14:49:44.56#ibcon#*mode == 0, iclass 34, count 0 2006.285.14:49:44.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.14:49:44.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.14:49:44.56#ibcon#*before write, iclass 34, count 0 2006.285.14:49:44.56#ibcon#enter sib2, iclass 34, count 0 2006.285.14:49:44.56#ibcon#flushed, iclass 34, count 0 2006.285.14:49:44.56#ibcon#about to write, iclass 34, count 0 2006.285.14:49:44.56#ibcon#wrote, iclass 34, count 0 2006.285.14:49:44.56#ibcon#about to read 3, iclass 34, count 0 2006.285.14:49:44.61#ibcon#read 3, iclass 34, count 0 2006.285.14:49:44.61#ibcon#about to read 4, iclass 34, count 0 2006.285.14:49:44.61#ibcon#read 4, iclass 34, count 0 2006.285.14:49:44.61#ibcon#about to read 5, iclass 34, count 0 2006.285.14:49:44.61#ibcon#read 5, iclass 34, count 0 2006.285.14:49:44.61#ibcon#about to read 6, iclass 34, count 0 2006.285.14:49:44.61#ibcon#read 6, iclass 34, count 0 2006.285.14:49:44.61#ibcon#end of sib2, iclass 34, count 0 2006.285.14:49:44.61#ibcon#*after write, iclass 34, count 0 2006.285.14:49:44.61#ibcon#*before return 0, iclass 34, count 0 2006.285.14:49:44.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:49:44.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:49:44.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.14:49:44.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.14:49:44.62$vck44/va=1,7 2006.285.14:49:44.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.14:49:44.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.14:49:44.62#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:44.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.14:49:44.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.14:49:44.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.14:49:44.62#ibcon#enter wrdev, iclass 36, count 2 2006.285.14:49:44.62#ibcon#first serial, iclass 36, count 2 2006.285.14:49:44.62#ibcon#enter sib2, iclass 36, count 2 2006.285.14:49:44.62#ibcon#flushed, iclass 36, count 2 2006.285.14:49:44.62#ibcon#about to write, iclass 36, count 2 2006.285.14:49:44.62#ibcon#wrote, iclass 36, count 2 2006.285.14:49:44.62#ibcon#about to read 3, iclass 36, count 2 2006.285.14:49:44.63#ibcon#read 3, iclass 36, count 2 2006.285.14:49:44.63#ibcon#about to read 4, iclass 36, count 2 2006.285.14:49:44.63#ibcon#read 4, iclass 36, count 2 2006.285.14:49:44.63#ibcon#about to read 5, iclass 36, count 2 2006.285.14:49:44.63#ibcon#read 5, iclass 36, count 2 2006.285.14:49:44.63#ibcon#about to read 6, iclass 36, count 2 2006.285.14:49:44.63#ibcon#read 6, iclass 36, count 2 2006.285.14:49:44.63#ibcon#end of sib2, iclass 36, count 2 2006.285.14:49:44.63#ibcon#*mode == 0, iclass 36, count 2 2006.285.14:49:44.63#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.14:49:44.63#ibcon#[25=AT01-07\r\n] 2006.285.14:49:44.63#ibcon#*before write, iclass 36, count 2 2006.285.14:49:44.63#ibcon#enter sib2, iclass 36, count 2 2006.285.14:49:44.63#ibcon#flushed, iclass 36, count 2 2006.285.14:49:44.63#ibcon#about to write, iclass 36, count 2 2006.285.14:49:44.63#ibcon#wrote, iclass 36, count 2 2006.285.14:49:44.63#ibcon#about to read 3, iclass 36, count 2 2006.285.14:49:44.66#ibcon#read 3, iclass 36, count 2 2006.285.14:49:44.66#ibcon#about to read 4, iclass 36, count 2 2006.285.14:49:44.66#ibcon#read 4, iclass 36, count 2 2006.285.14:49:44.66#ibcon#about to read 5, iclass 36, count 2 2006.285.14:49:44.66#ibcon#read 5, iclass 36, count 2 2006.285.14:49:44.66#ibcon#about to read 6, iclass 36, count 2 2006.285.14:49:44.66#ibcon#read 6, iclass 36, count 2 2006.285.14:49:44.66#ibcon#end of sib2, iclass 36, count 2 2006.285.14:49:44.66#ibcon#*after write, iclass 36, count 2 2006.285.14:49:44.66#ibcon#*before return 0, iclass 36, count 2 2006.285.14:49:44.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.14:49:44.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.14:49:44.66#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.14:49:44.66#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:44.66#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.14:49:44.78#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.14:49:44.78#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.14:49:44.78#ibcon#enter wrdev, iclass 36, count 0 2006.285.14:49:44.78#ibcon#first serial, iclass 36, count 0 2006.285.14:49:44.78#ibcon#enter sib2, iclass 36, count 0 2006.285.14:49:44.78#ibcon#flushed, iclass 36, count 0 2006.285.14:49:44.78#ibcon#about to write, iclass 36, count 0 2006.285.14:49:44.78#ibcon#wrote, iclass 36, count 0 2006.285.14:49:44.78#ibcon#about to read 3, iclass 36, count 0 2006.285.14:49:44.80#ibcon#read 3, iclass 36, count 0 2006.285.14:49:44.80#ibcon#about to read 4, iclass 36, count 0 2006.285.14:49:44.80#ibcon#read 4, iclass 36, count 0 2006.285.14:49:44.80#ibcon#about to read 5, iclass 36, count 0 2006.285.14:49:44.80#ibcon#read 5, iclass 36, count 0 2006.285.14:49:44.80#ibcon#about to read 6, iclass 36, count 0 2006.285.14:49:44.80#ibcon#read 6, iclass 36, count 0 2006.285.14:49:44.80#ibcon#end of sib2, iclass 36, count 0 2006.285.14:49:44.80#ibcon#*mode == 0, iclass 36, count 0 2006.285.14:49:44.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.14:49:44.80#ibcon#[25=USB\r\n] 2006.285.14:49:44.80#ibcon#*before write, iclass 36, count 0 2006.285.14:49:44.80#ibcon#enter sib2, iclass 36, count 0 2006.285.14:49:44.80#ibcon#flushed, iclass 36, count 0 2006.285.14:49:44.80#ibcon#about to write, iclass 36, count 0 2006.285.14:49:44.80#ibcon#wrote, iclass 36, count 0 2006.285.14:49:44.80#ibcon#about to read 3, iclass 36, count 0 2006.285.14:49:44.83#ibcon#read 3, iclass 36, count 0 2006.285.14:49:44.83#ibcon#about to read 4, iclass 36, count 0 2006.285.14:49:44.83#ibcon#read 4, iclass 36, count 0 2006.285.14:49:44.83#ibcon#about to read 5, iclass 36, count 0 2006.285.14:49:44.83#ibcon#read 5, iclass 36, count 0 2006.285.14:49:44.83#ibcon#about to read 6, iclass 36, count 0 2006.285.14:49:44.83#ibcon#read 6, iclass 36, count 0 2006.285.14:49:44.83#ibcon#end of sib2, iclass 36, count 0 2006.285.14:49:44.83#ibcon#*after write, iclass 36, count 0 2006.285.14:49:44.83#ibcon#*before return 0, iclass 36, count 0 2006.285.14:49:44.83#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.14:49:44.83#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.14:49:44.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.14:49:44.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.14:49:44.84$vck44/valo=2,534.99 2006.285.14:49:44.84#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.14:49:44.84#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.14:49:44.84#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:44.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:49:44.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:49:44.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:49:44.84#ibcon#enter wrdev, iclass 38, count 0 2006.285.14:49:44.84#ibcon#first serial, iclass 38, count 0 2006.285.14:49:44.84#ibcon#enter sib2, iclass 38, count 0 2006.285.14:49:44.84#ibcon#flushed, iclass 38, count 0 2006.285.14:49:44.84#ibcon#about to write, iclass 38, count 0 2006.285.14:49:44.84#ibcon#wrote, iclass 38, count 0 2006.285.14:49:44.84#ibcon#about to read 3, iclass 38, count 0 2006.285.14:49:44.85#ibcon#read 3, iclass 38, count 0 2006.285.14:49:44.85#ibcon#about to read 4, iclass 38, count 0 2006.285.14:49:44.85#ibcon#read 4, iclass 38, count 0 2006.285.14:49:44.85#ibcon#about to read 5, iclass 38, count 0 2006.285.14:49:44.85#ibcon#read 5, iclass 38, count 0 2006.285.14:49:44.85#ibcon#about to read 6, iclass 38, count 0 2006.285.14:49:44.85#ibcon#read 6, iclass 38, count 0 2006.285.14:49:44.85#ibcon#end of sib2, iclass 38, count 0 2006.285.14:49:44.85#ibcon#*mode == 0, iclass 38, count 0 2006.285.14:49:44.85#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.14:49:44.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.14:49:44.85#ibcon#*before write, iclass 38, count 0 2006.285.14:49:44.85#ibcon#enter sib2, iclass 38, count 0 2006.285.14:49:44.85#ibcon#flushed, iclass 38, count 0 2006.285.14:49:44.85#ibcon#about to write, iclass 38, count 0 2006.285.14:49:44.85#ibcon#wrote, iclass 38, count 0 2006.285.14:49:44.85#ibcon#about to read 3, iclass 38, count 0 2006.285.14:49:44.89#ibcon#read 3, iclass 38, count 0 2006.285.14:49:44.89#ibcon#about to read 4, iclass 38, count 0 2006.285.14:49:44.89#ibcon#read 4, iclass 38, count 0 2006.285.14:49:44.89#ibcon#about to read 5, iclass 38, count 0 2006.285.14:49:44.89#ibcon#read 5, iclass 38, count 0 2006.285.14:49:44.89#ibcon#about to read 6, iclass 38, count 0 2006.285.14:49:44.89#ibcon#read 6, iclass 38, count 0 2006.285.14:49:44.89#ibcon#end of sib2, iclass 38, count 0 2006.285.14:49:44.89#ibcon#*after write, iclass 38, count 0 2006.285.14:49:44.89#ibcon#*before return 0, iclass 38, count 0 2006.285.14:49:44.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:49:44.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.14:49:44.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.14:49:44.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.14:49:44.90$vck44/va=2,6 2006.285.14:49:44.90#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.14:49:44.90#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.14:49:44.90#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:44.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:49:44.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:49:44.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:49:44.94#ibcon#enter wrdev, iclass 40, count 2 2006.285.14:49:44.94#ibcon#first serial, iclass 40, count 2 2006.285.14:49:44.94#ibcon#enter sib2, iclass 40, count 2 2006.285.14:49:44.94#ibcon#flushed, iclass 40, count 2 2006.285.14:49:44.94#ibcon#about to write, iclass 40, count 2 2006.285.14:49:44.94#ibcon#wrote, iclass 40, count 2 2006.285.14:49:44.94#ibcon#about to read 3, iclass 40, count 2 2006.285.14:49:44.96#ibcon#read 3, iclass 40, count 2 2006.285.14:49:44.96#ibcon#about to read 4, iclass 40, count 2 2006.285.14:49:44.96#ibcon#read 4, iclass 40, count 2 2006.285.14:49:44.96#ibcon#about to read 5, iclass 40, count 2 2006.285.14:49:44.96#ibcon#read 5, iclass 40, count 2 2006.285.14:49:44.96#ibcon#about to read 6, iclass 40, count 2 2006.285.14:49:44.96#ibcon#read 6, iclass 40, count 2 2006.285.14:49:44.96#ibcon#end of sib2, iclass 40, count 2 2006.285.14:49:44.96#ibcon#*mode == 0, iclass 40, count 2 2006.285.14:49:44.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.14:49:44.96#ibcon#[25=AT02-06\r\n] 2006.285.14:49:44.96#ibcon#*before write, iclass 40, count 2 2006.285.14:49:44.96#ibcon#enter sib2, iclass 40, count 2 2006.285.14:49:44.96#ibcon#flushed, iclass 40, count 2 2006.285.14:49:44.96#ibcon#about to write, iclass 40, count 2 2006.285.14:49:44.96#ibcon#wrote, iclass 40, count 2 2006.285.14:49:44.96#ibcon#about to read 3, iclass 40, count 2 2006.285.14:49:44.99#ibcon#read 3, iclass 40, count 2 2006.285.14:49:44.99#ibcon#about to read 4, iclass 40, count 2 2006.285.14:49:44.99#ibcon#read 4, iclass 40, count 2 2006.285.14:49:44.99#ibcon#about to read 5, iclass 40, count 2 2006.285.14:49:44.99#ibcon#read 5, iclass 40, count 2 2006.285.14:49:44.99#ibcon#about to read 6, iclass 40, count 2 2006.285.14:49:44.99#ibcon#read 6, iclass 40, count 2 2006.285.14:49:44.99#ibcon#end of sib2, iclass 40, count 2 2006.285.14:49:44.99#ibcon#*after write, iclass 40, count 2 2006.285.14:49:44.99#ibcon#*before return 0, iclass 40, count 2 2006.285.14:49:44.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:49:44.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.14:49:44.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.14:49:44.99#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:44.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:49:45.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:49:45.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:49:45.11#ibcon#enter wrdev, iclass 40, count 0 2006.285.14:49:45.11#ibcon#first serial, iclass 40, count 0 2006.285.14:49:45.11#ibcon#enter sib2, iclass 40, count 0 2006.285.14:49:45.11#ibcon#flushed, iclass 40, count 0 2006.285.14:49:45.11#ibcon#about to write, iclass 40, count 0 2006.285.14:49:45.11#ibcon#wrote, iclass 40, count 0 2006.285.14:49:45.11#ibcon#about to read 3, iclass 40, count 0 2006.285.14:49:45.13#ibcon#read 3, iclass 40, count 0 2006.285.14:49:45.13#ibcon#about to read 4, iclass 40, count 0 2006.285.14:49:45.13#ibcon#read 4, iclass 40, count 0 2006.285.14:49:45.13#ibcon#about to read 5, iclass 40, count 0 2006.285.14:49:45.13#ibcon#read 5, iclass 40, count 0 2006.285.14:49:45.13#ibcon#about to read 6, iclass 40, count 0 2006.285.14:49:45.13#ibcon#read 6, iclass 40, count 0 2006.285.14:49:45.13#ibcon#end of sib2, iclass 40, count 0 2006.285.14:49:45.13#ibcon#*mode == 0, iclass 40, count 0 2006.285.14:49:45.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.14:49:45.13#ibcon#[25=USB\r\n] 2006.285.14:49:45.13#ibcon#*before write, iclass 40, count 0 2006.285.14:49:45.13#ibcon#enter sib2, iclass 40, count 0 2006.285.14:49:45.13#ibcon#flushed, iclass 40, count 0 2006.285.14:49:45.13#ibcon#about to write, iclass 40, count 0 2006.285.14:49:45.13#ibcon#wrote, iclass 40, count 0 2006.285.14:49:45.13#ibcon#about to read 3, iclass 40, count 0 2006.285.14:49:45.16#ibcon#read 3, iclass 40, count 0 2006.285.14:49:45.16#ibcon#about to read 4, iclass 40, count 0 2006.285.14:49:45.16#ibcon#read 4, iclass 40, count 0 2006.285.14:49:45.16#ibcon#about to read 5, iclass 40, count 0 2006.285.14:49:45.16#ibcon#read 5, iclass 40, count 0 2006.285.14:49:45.16#ibcon#about to read 6, iclass 40, count 0 2006.285.14:49:45.16#ibcon#read 6, iclass 40, count 0 2006.285.14:49:45.16#ibcon#end of sib2, iclass 40, count 0 2006.285.14:49:45.16#ibcon#*after write, iclass 40, count 0 2006.285.14:49:45.16#ibcon#*before return 0, iclass 40, count 0 2006.285.14:49:45.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:49:45.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.14:49:45.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.14:49:45.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.14:49:45.17$vck44/valo=3,564.99 2006.285.14:49:45.17#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.14:49:45.17#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.14:49:45.17#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:45.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:49:45.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:49:45.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:49:45.17#ibcon#enter wrdev, iclass 4, count 0 2006.285.14:49:45.17#ibcon#first serial, iclass 4, count 0 2006.285.14:49:45.17#ibcon#enter sib2, iclass 4, count 0 2006.285.14:49:45.17#ibcon#flushed, iclass 4, count 0 2006.285.14:49:45.17#ibcon#about to write, iclass 4, count 0 2006.285.14:49:45.17#ibcon#wrote, iclass 4, count 0 2006.285.14:49:45.17#ibcon#about to read 3, iclass 4, count 0 2006.285.14:49:45.18#ibcon#read 3, iclass 4, count 0 2006.285.14:49:45.18#ibcon#about to read 4, iclass 4, count 0 2006.285.14:49:45.18#ibcon#read 4, iclass 4, count 0 2006.285.14:49:45.18#ibcon#about to read 5, iclass 4, count 0 2006.285.14:49:45.18#ibcon#read 5, iclass 4, count 0 2006.285.14:49:45.18#ibcon#about to read 6, iclass 4, count 0 2006.285.14:49:45.18#ibcon#read 6, iclass 4, count 0 2006.285.14:49:45.18#ibcon#end of sib2, iclass 4, count 0 2006.285.14:49:45.18#ibcon#*mode == 0, iclass 4, count 0 2006.285.14:49:45.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.14:49:45.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.14:49:45.18#ibcon#*before write, iclass 4, count 0 2006.285.14:49:45.18#ibcon#enter sib2, iclass 4, count 0 2006.285.14:49:45.18#ibcon#flushed, iclass 4, count 0 2006.285.14:49:45.18#ibcon#about to write, iclass 4, count 0 2006.285.14:49:45.18#ibcon#wrote, iclass 4, count 0 2006.285.14:49:45.18#ibcon#about to read 3, iclass 4, count 0 2006.285.14:49:45.22#ibcon#read 3, iclass 4, count 0 2006.285.14:49:45.22#ibcon#about to read 4, iclass 4, count 0 2006.285.14:49:45.22#ibcon#read 4, iclass 4, count 0 2006.285.14:49:45.22#ibcon#about to read 5, iclass 4, count 0 2006.285.14:49:45.22#ibcon#read 5, iclass 4, count 0 2006.285.14:49:45.22#ibcon#about to read 6, iclass 4, count 0 2006.285.14:49:45.22#ibcon#read 6, iclass 4, count 0 2006.285.14:49:45.22#ibcon#end of sib2, iclass 4, count 0 2006.285.14:49:45.22#ibcon#*after write, iclass 4, count 0 2006.285.14:49:45.22#ibcon#*before return 0, iclass 4, count 0 2006.285.14:49:45.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:49:45.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:49:45.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.14:49:45.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.14:49:45.23$vck44/va=3,7 2006.285.14:49:45.23#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.14:49:45.23#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.14:49:45.23#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:45.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:49:45.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:49:45.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:49:45.27#ibcon#enter wrdev, iclass 6, count 2 2006.285.14:49:45.27#ibcon#first serial, iclass 6, count 2 2006.285.14:49:45.27#ibcon#enter sib2, iclass 6, count 2 2006.285.14:49:45.27#ibcon#flushed, iclass 6, count 2 2006.285.14:49:45.27#ibcon#about to write, iclass 6, count 2 2006.285.14:49:45.27#ibcon#wrote, iclass 6, count 2 2006.285.14:49:45.27#ibcon#about to read 3, iclass 6, count 2 2006.285.14:49:45.29#ibcon#read 3, iclass 6, count 2 2006.285.14:49:45.29#ibcon#about to read 4, iclass 6, count 2 2006.285.14:49:45.29#ibcon#read 4, iclass 6, count 2 2006.285.14:49:45.29#ibcon#about to read 5, iclass 6, count 2 2006.285.14:49:45.29#ibcon#read 5, iclass 6, count 2 2006.285.14:49:45.29#ibcon#about to read 6, iclass 6, count 2 2006.285.14:49:45.29#ibcon#read 6, iclass 6, count 2 2006.285.14:49:45.29#ibcon#end of sib2, iclass 6, count 2 2006.285.14:49:45.29#ibcon#*mode == 0, iclass 6, count 2 2006.285.14:49:45.29#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.14:49:45.29#ibcon#[25=AT03-07\r\n] 2006.285.14:49:45.29#ibcon#*before write, iclass 6, count 2 2006.285.14:49:45.29#ibcon#enter sib2, iclass 6, count 2 2006.285.14:49:45.29#ibcon#flushed, iclass 6, count 2 2006.285.14:49:45.29#ibcon#about to write, iclass 6, count 2 2006.285.14:49:45.29#ibcon#wrote, iclass 6, count 2 2006.285.14:49:45.29#ibcon#about to read 3, iclass 6, count 2 2006.285.14:49:45.32#ibcon#read 3, iclass 6, count 2 2006.285.14:49:45.32#ibcon#about to read 4, iclass 6, count 2 2006.285.14:49:45.32#ibcon#read 4, iclass 6, count 2 2006.285.14:49:45.32#ibcon#about to read 5, iclass 6, count 2 2006.285.14:49:45.32#ibcon#read 5, iclass 6, count 2 2006.285.14:49:45.32#ibcon#about to read 6, iclass 6, count 2 2006.285.14:49:45.32#ibcon#read 6, iclass 6, count 2 2006.285.14:49:45.32#ibcon#end of sib2, iclass 6, count 2 2006.285.14:49:45.32#ibcon#*after write, iclass 6, count 2 2006.285.14:49:45.32#ibcon#*before return 0, iclass 6, count 2 2006.285.14:49:45.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:49:45.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:49:45.32#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.14:49:45.32#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:45.32#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:49:45.44#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:49:45.44#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:49:45.44#ibcon#enter wrdev, iclass 6, count 0 2006.285.14:49:45.44#ibcon#first serial, iclass 6, count 0 2006.285.14:49:45.44#ibcon#enter sib2, iclass 6, count 0 2006.285.14:49:45.44#ibcon#flushed, iclass 6, count 0 2006.285.14:49:45.44#ibcon#about to write, iclass 6, count 0 2006.285.14:49:45.44#ibcon#wrote, iclass 6, count 0 2006.285.14:49:45.44#ibcon#about to read 3, iclass 6, count 0 2006.285.14:49:45.46#ibcon#read 3, iclass 6, count 0 2006.285.14:49:45.46#ibcon#about to read 4, iclass 6, count 0 2006.285.14:49:45.46#ibcon#read 4, iclass 6, count 0 2006.285.14:49:45.46#ibcon#about to read 5, iclass 6, count 0 2006.285.14:49:45.46#ibcon#read 5, iclass 6, count 0 2006.285.14:49:45.46#ibcon#about to read 6, iclass 6, count 0 2006.285.14:49:45.46#ibcon#read 6, iclass 6, count 0 2006.285.14:49:45.46#ibcon#end of sib2, iclass 6, count 0 2006.285.14:49:45.46#ibcon#*mode == 0, iclass 6, count 0 2006.285.14:49:45.46#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.14:49:45.46#ibcon#[25=USB\r\n] 2006.285.14:49:45.46#ibcon#*before write, iclass 6, count 0 2006.285.14:49:45.46#ibcon#enter sib2, iclass 6, count 0 2006.285.14:49:45.46#ibcon#flushed, iclass 6, count 0 2006.285.14:49:45.46#ibcon#about to write, iclass 6, count 0 2006.285.14:49:45.46#ibcon#wrote, iclass 6, count 0 2006.285.14:49:45.46#ibcon#about to read 3, iclass 6, count 0 2006.285.14:49:45.49#ibcon#read 3, iclass 6, count 0 2006.285.14:49:45.49#ibcon#about to read 4, iclass 6, count 0 2006.285.14:49:45.49#ibcon#read 4, iclass 6, count 0 2006.285.14:49:45.49#ibcon#about to read 5, iclass 6, count 0 2006.285.14:49:45.49#ibcon#read 5, iclass 6, count 0 2006.285.14:49:45.49#ibcon#about to read 6, iclass 6, count 0 2006.285.14:49:45.49#ibcon#read 6, iclass 6, count 0 2006.285.14:49:45.49#ibcon#end of sib2, iclass 6, count 0 2006.285.14:49:45.49#ibcon#*after write, iclass 6, count 0 2006.285.14:49:45.49#ibcon#*before return 0, iclass 6, count 0 2006.285.14:49:45.49#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:49:45.49#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:49:45.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.14:49:45.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.14:49:45.49$vck44/valo=4,624.99 2006.285.14:49:45.49#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.14:49:45.49#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.14:49:45.49#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:45.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:49:45.49#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:49:45.49#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:49:45.49#ibcon#enter wrdev, iclass 10, count 0 2006.285.14:49:45.49#ibcon#first serial, iclass 10, count 0 2006.285.14:49:45.49#ibcon#enter sib2, iclass 10, count 0 2006.285.14:49:45.49#ibcon#flushed, iclass 10, count 0 2006.285.14:49:45.49#ibcon#about to write, iclass 10, count 0 2006.285.14:49:45.49#ibcon#wrote, iclass 10, count 0 2006.285.14:49:45.49#ibcon#about to read 3, iclass 10, count 0 2006.285.14:49:45.89#ibcon#read 3, iclass 10, count 0 2006.285.14:49:45.89#ibcon#about to read 4, iclass 10, count 0 2006.285.14:49:45.89#ibcon#read 4, iclass 10, count 0 2006.285.14:49:45.89#ibcon#about to read 5, iclass 10, count 0 2006.285.14:49:45.89#ibcon#read 5, iclass 10, count 0 2006.285.14:49:45.89#ibcon#about to read 6, iclass 10, count 0 2006.285.14:49:45.89#ibcon#read 6, iclass 10, count 0 2006.285.14:49:45.89#ibcon#end of sib2, iclass 10, count 0 2006.285.14:49:45.89#ibcon#*mode == 0, iclass 10, count 0 2006.285.14:49:45.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.14:49:45.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.14:49:45.89#ibcon#*before write, iclass 10, count 0 2006.285.14:49:45.89#ibcon#enter sib2, iclass 10, count 0 2006.285.14:49:45.89#ibcon#flushed, iclass 10, count 0 2006.285.14:49:45.89#ibcon#about to write, iclass 10, count 0 2006.285.14:49:45.89#ibcon#wrote, iclass 10, count 0 2006.285.14:49:45.89#ibcon#about to read 3, iclass 10, count 0 2006.285.14:49:45.93#ibcon#read 3, iclass 10, count 0 2006.285.14:49:45.93#ibcon#about to read 4, iclass 10, count 0 2006.285.14:49:45.93#ibcon#read 4, iclass 10, count 0 2006.285.14:49:45.93#ibcon#about to read 5, iclass 10, count 0 2006.285.14:49:45.93#ibcon#read 5, iclass 10, count 0 2006.285.14:49:45.93#ibcon#about to read 6, iclass 10, count 0 2006.285.14:49:45.93#ibcon#read 6, iclass 10, count 0 2006.285.14:49:45.93#ibcon#end of sib2, iclass 10, count 0 2006.285.14:49:45.93#ibcon#*after write, iclass 10, count 0 2006.285.14:49:45.93#ibcon#*before return 0, iclass 10, count 0 2006.285.14:49:45.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:49:45.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:49:45.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.14:49:45.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.14:49:45.93$vck44/va=4,6 2006.285.14:49:45.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.14:49:45.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.14:49:45.93#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:45.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:49:45.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:49:45.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:49:45.93#ibcon#enter wrdev, iclass 12, count 2 2006.285.14:49:45.93#ibcon#first serial, iclass 12, count 2 2006.285.14:49:45.93#ibcon#enter sib2, iclass 12, count 2 2006.285.14:49:45.93#ibcon#flushed, iclass 12, count 2 2006.285.14:49:45.93#ibcon#about to write, iclass 12, count 2 2006.285.14:49:45.93#ibcon#wrote, iclass 12, count 2 2006.285.14:49:45.93#ibcon#about to read 3, iclass 12, count 2 2006.285.14:49:45.95#ibcon#read 3, iclass 12, count 2 2006.285.14:49:45.95#ibcon#about to read 4, iclass 12, count 2 2006.285.14:49:45.95#ibcon#read 4, iclass 12, count 2 2006.285.14:49:45.95#ibcon#about to read 5, iclass 12, count 2 2006.285.14:49:45.95#ibcon#read 5, iclass 12, count 2 2006.285.14:49:45.95#ibcon#about to read 6, iclass 12, count 2 2006.285.14:49:45.95#ibcon#read 6, iclass 12, count 2 2006.285.14:49:45.95#ibcon#end of sib2, iclass 12, count 2 2006.285.14:49:45.95#ibcon#*mode == 0, iclass 12, count 2 2006.285.14:49:45.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.14:49:45.95#ibcon#[25=AT04-06\r\n] 2006.285.14:49:45.95#ibcon#*before write, iclass 12, count 2 2006.285.14:49:45.95#ibcon#enter sib2, iclass 12, count 2 2006.285.14:49:45.95#ibcon#flushed, iclass 12, count 2 2006.285.14:49:45.95#ibcon#about to write, iclass 12, count 2 2006.285.14:49:45.95#ibcon#wrote, iclass 12, count 2 2006.285.14:49:45.95#ibcon#about to read 3, iclass 12, count 2 2006.285.14:49:45.98#ibcon#read 3, iclass 12, count 2 2006.285.14:49:45.98#ibcon#about to read 4, iclass 12, count 2 2006.285.14:49:45.98#ibcon#read 4, iclass 12, count 2 2006.285.14:49:45.98#ibcon#about to read 5, iclass 12, count 2 2006.285.14:49:45.98#ibcon#read 5, iclass 12, count 2 2006.285.14:49:45.98#ibcon#about to read 6, iclass 12, count 2 2006.285.14:49:45.98#ibcon#read 6, iclass 12, count 2 2006.285.14:49:45.98#ibcon#end of sib2, iclass 12, count 2 2006.285.14:49:45.98#ibcon#*after write, iclass 12, count 2 2006.285.14:49:45.98#ibcon#*before return 0, iclass 12, count 2 2006.285.14:49:45.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:49:45.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:49:45.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.14:49:45.98#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:45.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:49:46.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:49:46.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:49:46.10#ibcon#enter wrdev, iclass 12, count 0 2006.285.14:49:46.10#ibcon#first serial, iclass 12, count 0 2006.285.14:49:46.10#ibcon#enter sib2, iclass 12, count 0 2006.285.14:49:46.10#ibcon#flushed, iclass 12, count 0 2006.285.14:49:46.10#ibcon#about to write, iclass 12, count 0 2006.285.14:49:46.10#ibcon#wrote, iclass 12, count 0 2006.285.14:49:46.10#ibcon#about to read 3, iclass 12, count 0 2006.285.14:49:46.12#ibcon#read 3, iclass 12, count 0 2006.285.14:49:46.12#ibcon#about to read 4, iclass 12, count 0 2006.285.14:49:46.12#ibcon#read 4, iclass 12, count 0 2006.285.14:49:46.12#ibcon#about to read 5, iclass 12, count 0 2006.285.14:49:46.12#ibcon#read 5, iclass 12, count 0 2006.285.14:49:46.12#ibcon#about to read 6, iclass 12, count 0 2006.285.14:49:46.12#ibcon#read 6, iclass 12, count 0 2006.285.14:49:46.12#ibcon#end of sib2, iclass 12, count 0 2006.285.14:49:46.12#ibcon#*mode == 0, iclass 12, count 0 2006.285.14:49:46.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.14:49:46.12#ibcon#[25=USB\r\n] 2006.285.14:49:46.12#ibcon#*before write, iclass 12, count 0 2006.285.14:49:46.12#ibcon#enter sib2, iclass 12, count 0 2006.285.14:49:46.12#ibcon#flushed, iclass 12, count 0 2006.285.14:49:46.12#ibcon#about to write, iclass 12, count 0 2006.285.14:49:46.12#ibcon#wrote, iclass 12, count 0 2006.285.14:49:46.12#ibcon#about to read 3, iclass 12, count 0 2006.285.14:49:46.15#ibcon#read 3, iclass 12, count 0 2006.285.14:49:46.15#ibcon#about to read 4, iclass 12, count 0 2006.285.14:49:46.15#ibcon#read 4, iclass 12, count 0 2006.285.14:49:46.15#ibcon#about to read 5, iclass 12, count 0 2006.285.14:49:46.15#ibcon#read 5, iclass 12, count 0 2006.285.14:49:46.15#ibcon#about to read 6, iclass 12, count 0 2006.285.14:49:46.15#ibcon#read 6, iclass 12, count 0 2006.285.14:49:46.15#ibcon#end of sib2, iclass 12, count 0 2006.285.14:49:46.15#ibcon#*after write, iclass 12, count 0 2006.285.14:49:46.15#ibcon#*before return 0, iclass 12, count 0 2006.285.14:49:46.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:49:46.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:49:46.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.14:49:46.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.14:49:46.15$vck44/valo=5,734.99 2006.285.14:49:46.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.14:49:46.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.14:49:46.15#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:46.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:49:46.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:49:46.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:49:46.15#ibcon#enter wrdev, iclass 14, count 0 2006.285.14:49:46.15#ibcon#first serial, iclass 14, count 0 2006.285.14:49:46.15#ibcon#enter sib2, iclass 14, count 0 2006.285.14:49:46.15#ibcon#flushed, iclass 14, count 0 2006.285.14:49:46.15#ibcon#about to write, iclass 14, count 0 2006.285.14:49:46.15#ibcon#wrote, iclass 14, count 0 2006.285.14:49:46.15#ibcon#about to read 3, iclass 14, count 0 2006.285.14:49:46.17#ibcon#read 3, iclass 14, count 0 2006.285.14:49:46.17#ibcon#about to read 4, iclass 14, count 0 2006.285.14:49:46.17#ibcon#read 4, iclass 14, count 0 2006.285.14:49:46.17#ibcon#about to read 5, iclass 14, count 0 2006.285.14:49:46.17#ibcon#read 5, iclass 14, count 0 2006.285.14:49:46.17#ibcon#about to read 6, iclass 14, count 0 2006.285.14:49:46.17#ibcon#read 6, iclass 14, count 0 2006.285.14:49:46.17#ibcon#end of sib2, iclass 14, count 0 2006.285.14:49:46.17#ibcon#*mode == 0, iclass 14, count 0 2006.285.14:49:46.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.14:49:46.17#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.14:49:46.17#ibcon#*before write, iclass 14, count 0 2006.285.14:49:46.17#ibcon#enter sib2, iclass 14, count 0 2006.285.14:49:46.17#ibcon#flushed, iclass 14, count 0 2006.285.14:49:46.17#ibcon#about to write, iclass 14, count 0 2006.285.14:49:46.17#ibcon#wrote, iclass 14, count 0 2006.285.14:49:46.17#ibcon#about to read 3, iclass 14, count 0 2006.285.14:49:46.21#ibcon#read 3, iclass 14, count 0 2006.285.14:49:46.21#ibcon#about to read 4, iclass 14, count 0 2006.285.14:49:46.21#ibcon#read 4, iclass 14, count 0 2006.285.14:49:46.21#ibcon#about to read 5, iclass 14, count 0 2006.285.14:49:46.21#ibcon#read 5, iclass 14, count 0 2006.285.14:49:46.21#ibcon#about to read 6, iclass 14, count 0 2006.285.14:49:46.21#ibcon#read 6, iclass 14, count 0 2006.285.14:49:46.21#ibcon#end of sib2, iclass 14, count 0 2006.285.14:49:46.21#ibcon#*after write, iclass 14, count 0 2006.285.14:49:46.21#ibcon#*before return 0, iclass 14, count 0 2006.285.14:49:46.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:49:46.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:49:46.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.14:49:46.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.14:49:46.21$vck44/va=5,3 2006.285.14:49:46.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.14:49:46.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.14:49:46.21#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:46.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:49:46.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:49:46.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:49:46.27#ibcon#enter wrdev, iclass 16, count 2 2006.285.14:49:46.27#ibcon#first serial, iclass 16, count 2 2006.285.14:49:46.27#ibcon#enter sib2, iclass 16, count 2 2006.285.14:49:46.27#ibcon#flushed, iclass 16, count 2 2006.285.14:49:46.27#ibcon#about to write, iclass 16, count 2 2006.285.14:49:46.27#ibcon#wrote, iclass 16, count 2 2006.285.14:49:46.27#ibcon#about to read 3, iclass 16, count 2 2006.285.14:49:46.29#ibcon#read 3, iclass 16, count 2 2006.285.14:49:46.29#ibcon#about to read 4, iclass 16, count 2 2006.285.14:49:46.29#ibcon#read 4, iclass 16, count 2 2006.285.14:49:46.29#ibcon#about to read 5, iclass 16, count 2 2006.285.14:49:46.29#ibcon#read 5, iclass 16, count 2 2006.285.14:49:46.29#ibcon#about to read 6, iclass 16, count 2 2006.285.14:49:46.29#ibcon#read 6, iclass 16, count 2 2006.285.14:49:46.29#ibcon#end of sib2, iclass 16, count 2 2006.285.14:49:46.29#ibcon#*mode == 0, iclass 16, count 2 2006.285.14:49:46.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.14:49:46.29#ibcon#[25=AT05-03\r\n] 2006.285.14:49:46.29#ibcon#*before write, iclass 16, count 2 2006.285.14:49:46.29#ibcon#enter sib2, iclass 16, count 2 2006.285.14:49:46.29#ibcon#flushed, iclass 16, count 2 2006.285.14:49:46.29#ibcon#about to write, iclass 16, count 2 2006.285.14:49:46.29#ibcon#wrote, iclass 16, count 2 2006.285.14:49:46.29#ibcon#about to read 3, iclass 16, count 2 2006.285.14:49:46.32#ibcon#read 3, iclass 16, count 2 2006.285.14:49:46.32#ibcon#about to read 4, iclass 16, count 2 2006.285.14:49:46.32#ibcon#read 4, iclass 16, count 2 2006.285.14:49:46.32#ibcon#about to read 5, iclass 16, count 2 2006.285.14:49:46.32#ibcon#read 5, iclass 16, count 2 2006.285.14:49:46.32#ibcon#about to read 6, iclass 16, count 2 2006.285.14:49:46.32#ibcon#read 6, iclass 16, count 2 2006.285.14:49:46.32#ibcon#end of sib2, iclass 16, count 2 2006.285.14:49:46.32#ibcon#*after write, iclass 16, count 2 2006.285.14:49:46.32#ibcon#*before return 0, iclass 16, count 2 2006.285.14:49:46.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:49:46.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:49:46.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.14:49:46.32#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:46.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:49:46.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:49:46.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:49:46.52#ibcon#enter wrdev, iclass 16, count 0 2006.285.14:49:46.52#ibcon#first serial, iclass 16, count 0 2006.285.14:49:46.52#ibcon#enter sib2, iclass 16, count 0 2006.285.14:49:46.52#ibcon#flushed, iclass 16, count 0 2006.285.14:49:46.52#ibcon#about to write, iclass 16, count 0 2006.285.14:49:46.52#ibcon#wrote, iclass 16, count 0 2006.285.14:49:46.52#ibcon#about to read 3, iclass 16, count 0 2006.285.14:49:46.53#ibcon#read 3, iclass 16, count 0 2006.285.14:49:46.53#ibcon#about to read 4, iclass 16, count 0 2006.285.14:49:46.53#ibcon#read 4, iclass 16, count 0 2006.285.14:49:46.53#ibcon#about to read 5, iclass 16, count 0 2006.285.14:49:46.53#ibcon#read 5, iclass 16, count 0 2006.285.14:49:46.53#ibcon#about to read 6, iclass 16, count 0 2006.285.14:49:46.53#ibcon#read 6, iclass 16, count 0 2006.285.14:49:46.53#ibcon#end of sib2, iclass 16, count 0 2006.285.14:49:46.53#ibcon#*mode == 0, iclass 16, count 0 2006.285.14:49:46.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.14:49:46.53#ibcon#[25=USB\r\n] 2006.285.14:49:46.53#ibcon#*before write, iclass 16, count 0 2006.285.14:49:46.53#ibcon#enter sib2, iclass 16, count 0 2006.285.14:49:46.53#ibcon#flushed, iclass 16, count 0 2006.285.14:49:46.53#ibcon#about to write, iclass 16, count 0 2006.285.14:49:46.53#ibcon#wrote, iclass 16, count 0 2006.285.14:49:46.53#ibcon#about to read 3, iclass 16, count 0 2006.285.14:49:46.56#ibcon#read 3, iclass 16, count 0 2006.285.14:49:46.56#ibcon#about to read 4, iclass 16, count 0 2006.285.14:49:46.56#ibcon#read 4, iclass 16, count 0 2006.285.14:49:46.56#ibcon#about to read 5, iclass 16, count 0 2006.285.14:49:46.56#ibcon#read 5, iclass 16, count 0 2006.285.14:49:46.56#ibcon#about to read 6, iclass 16, count 0 2006.285.14:49:46.56#ibcon#read 6, iclass 16, count 0 2006.285.14:49:46.56#ibcon#end of sib2, iclass 16, count 0 2006.285.14:49:46.56#ibcon#*after write, iclass 16, count 0 2006.285.14:49:46.56#ibcon#*before return 0, iclass 16, count 0 2006.285.14:49:46.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:49:46.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:49:46.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.14:49:46.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.14:49:46.56$vck44/valo=6,814.99 2006.285.14:49:46.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.14:49:46.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.14:49:46.56#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:46.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:49:46.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:49:46.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:49:46.56#ibcon#enter wrdev, iclass 18, count 0 2006.285.14:49:46.56#ibcon#first serial, iclass 18, count 0 2006.285.14:49:46.56#ibcon#enter sib2, iclass 18, count 0 2006.285.14:49:46.56#ibcon#flushed, iclass 18, count 0 2006.285.14:49:46.56#ibcon#about to write, iclass 18, count 0 2006.285.14:49:46.56#ibcon#wrote, iclass 18, count 0 2006.285.14:49:46.56#ibcon#about to read 3, iclass 18, count 0 2006.285.14:49:46.58#ibcon#read 3, iclass 18, count 0 2006.285.14:49:46.58#ibcon#about to read 4, iclass 18, count 0 2006.285.14:49:46.58#ibcon#read 4, iclass 18, count 0 2006.285.14:49:46.58#ibcon#about to read 5, iclass 18, count 0 2006.285.14:49:46.58#ibcon#read 5, iclass 18, count 0 2006.285.14:49:46.58#ibcon#about to read 6, iclass 18, count 0 2006.285.14:49:46.58#ibcon#read 6, iclass 18, count 0 2006.285.14:49:46.58#ibcon#end of sib2, iclass 18, count 0 2006.285.14:49:46.58#ibcon#*mode == 0, iclass 18, count 0 2006.285.14:49:46.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.14:49:46.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.14:49:46.58#ibcon#*before write, iclass 18, count 0 2006.285.14:49:46.58#ibcon#enter sib2, iclass 18, count 0 2006.285.14:49:46.58#ibcon#flushed, iclass 18, count 0 2006.285.14:49:46.58#ibcon#about to write, iclass 18, count 0 2006.285.14:49:46.58#ibcon#wrote, iclass 18, count 0 2006.285.14:49:46.58#ibcon#about to read 3, iclass 18, count 0 2006.285.14:49:46.62#ibcon#read 3, iclass 18, count 0 2006.285.14:49:46.62#ibcon#about to read 4, iclass 18, count 0 2006.285.14:49:46.62#ibcon#read 4, iclass 18, count 0 2006.285.14:49:46.62#ibcon#about to read 5, iclass 18, count 0 2006.285.14:49:46.62#ibcon#read 5, iclass 18, count 0 2006.285.14:49:46.62#ibcon#about to read 6, iclass 18, count 0 2006.285.14:49:46.62#ibcon#read 6, iclass 18, count 0 2006.285.14:49:46.62#ibcon#end of sib2, iclass 18, count 0 2006.285.14:49:46.62#ibcon#*after write, iclass 18, count 0 2006.285.14:49:46.62#ibcon#*before return 0, iclass 18, count 0 2006.285.14:49:46.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:49:46.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:49:46.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.14:49:46.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.14:49:46.62$vck44/va=6,4 2006.285.14:49:46.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.14:49:46.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.14:49:46.62#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:46.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:49:46.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:49:46.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:49:46.68#ibcon#enter wrdev, iclass 20, count 2 2006.285.14:49:46.68#ibcon#first serial, iclass 20, count 2 2006.285.14:49:46.68#ibcon#enter sib2, iclass 20, count 2 2006.285.14:49:46.68#ibcon#flushed, iclass 20, count 2 2006.285.14:49:46.68#ibcon#about to write, iclass 20, count 2 2006.285.14:49:46.68#ibcon#wrote, iclass 20, count 2 2006.285.14:49:46.68#ibcon#about to read 3, iclass 20, count 2 2006.285.14:49:46.70#ibcon#read 3, iclass 20, count 2 2006.285.14:49:46.70#ibcon#about to read 4, iclass 20, count 2 2006.285.14:49:46.70#ibcon#read 4, iclass 20, count 2 2006.285.14:49:46.70#ibcon#about to read 5, iclass 20, count 2 2006.285.14:49:46.70#ibcon#read 5, iclass 20, count 2 2006.285.14:49:46.70#ibcon#about to read 6, iclass 20, count 2 2006.285.14:49:46.70#ibcon#read 6, iclass 20, count 2 2006.285.14:49:46.70#ibcon#end of sib2, iclass 20, count 2 2006.285.14:49:46.70#ibcon#*mode == 0, iclass 20, count 2 2006.285.14:49:46.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.14:49:46.70#ibcon#[25=AT06-04\r\n] 2006.285.14:49:46.70#ibcon#*before write, iclass 20, count 2 2006.285.14:49:46.70#ibcon#enter sib2, iclass 20, count 2 2006.285.14:49:46.70#ibcon#flushed, iclass 20, count 2 2006.285.14:49:46.70#ibcon#about to write, iclass 20, count 2 2006.285.14:49:46.70#ibcon#wrote, iclass 20, count 2 2006.285.14:49:46.70#ibcon#about to read 3, iclass 20, count 2 2006.285.14:49:46.73#ibcon#read 3, iclass 20, count 2 2006.285.14:49:46.73#ibcon#about to read 4, iclass 20, count 2 2006.285.14:49:46.73#ibcon#read 4, iclass 20, count 2 2006.285.14:49:46.73#ibcon#about to read 5, iclass 20, count 2 2006.285.14:49:46.73#ibcon#read 5, iclass 20, count 2 2006.285.14:49:46.73#ibcon#about to read 6, iclass 20, count 2 2006.285.14:49:46.73#ibcon#read 6, iclass 20, count 2 2006.285.14:49:46.73#ibcon#end of sib2, iclass 20, count 2 2006.285.14:49:46.73#ibcon#*after write, iclass 20, count 2 2006.285.14:49:46.73#ibcon#*before return 0, iclass 20, count 2 2006.285.14:49:46.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:49:46.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:49:46.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.14:49:46.73#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:46.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:49:46.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:49:46.93#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:49:46.93#ibcon#enter wrdev, iclass 20, count 0 2006.285.14:49:46.93#ibcon#first serial, iclass 20, count 0 2006.285.14:49:46.93#ibcon#enter sib2, iclass 20, count 0 2006.285.14:49:46.93#ibcon#flushed, iclass 20, count 0 2006.285.14:49:46.93#ibcon#about to write, iclass 20, count 0 2006.285.14:49:46.93#ibcon#wrote, iclass 20, count 0 2006.285.14:49:46.93#ibcon#about to read 3, iclass 20, count 0 2006.285.14:49:46.94#ibcon#read 3, iclass 20, count 0 2006.285.14:49:46.94#ibcon#about to read 4, iclass 20, count 0 2006.285.14:49:46.94#ibcon#read 4, iclass 20, count 0 2006.285.14:49:46.94#ibcon#about to read 5, iclass 20, count 0 2006.285.14:49:46.94#ibcon#read 5, iclass 20, count 0 2006.285.14:49:46.94#ibcon#about to read 6, iclass 20, count 0 2006.285.14:49:46.94#ibcon#read 6, iclass 20, count 0 2006.285.14:49:46.94#ibcon#end of sib2, iclass 20, count 0 2006.285.14:49:46.94#ibcon#*mode == 0, iclass 20, count 0 2006.285.14:49:46.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.14:49:46.94#ibcon#[25=USB\r\n] 2006.285.14:49:46.94#ibcon#*before write, iclass 20, count 0 2006.285.14:49:46.94#ibcon#enter sib2, iclass 20, count 0 2006.285.14:49:46.94#ibcon#flushed, iclass 20, count 0 2006.285.14:49:46.94#ibcon#about to write, iclass 20, count 0 2006.285.14:49:46.94#ibcon#wrote, iclass 20, count 0 2006.285.14:49:46.94#ibcon#about to read 3, iclass 20, count 0 2006.285.14:49:46.97#ibcon#read 3, iclass 20, count 0 2006.285.14:49:46.97#ibcon#about to read 4, iclass 20, count 0 2006.285.14:49:46.97#ibcon#read 4, iclass 20, count 0 2006.285.14:49:46.97#ibcon#about to read 5, iclass 20, count 0 2006.285.14:49:46.97#ibcon#read 5, iclass 20, count 0 2006.285.14:49:46.97#ibcon#about to read 6, iclass 20, count 0 2006.285.14:49:46.97#ibcon#read 6, iclass 20, count 0 2006.285.14:49:46.97#ibcon#end of sib2, iclass 20, count 0 2006.285.14:49:46.97#ibcon#*after write, iclass 20, count 0 2006.285.14:49:46.97#ibcon#*before return 0, iclass 20, count 0 2006.285.14:49:46.97#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:49:46.97#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:49:46.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.14:49:46.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.14:49:46.97$vck44/valo=7,864.99 2006.285.14:49:46.97#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.14:49:46.97#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.14:49:46.97#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:46.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:49:46.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:49:46.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:49:46.97#ibcon#enter wrdev, iclass 22, count 0 2006.285.14:49:46.97#ibcon#first serial, iclass 22, count 0 2006.285.14:49:46.97#ibcon#enter sib2, iclass 22, count 0 2006.285.14:49:46.97#ibcon#flushed, iclass 22, count 0 2006.285.14:49:46.97#ibcon#about to write, iclass 22, count 0 2006.285.14:49:46.97#ibcon#wrote, iclass 22, count 0 2006.285.14:49:46.97#ibcon#about to read 3, iclass 22, count 0 2006.285.14:49:46.99#ibcon#read 3, iclass 22, count 0 2006.285.14:49:46.99#ibcon#about to read 4, iclass 22, count 0 2006.285.14:49:46.99#ibcon#read 4, iclass 22, count 0 2006.285.14:49:46.99#ibcon#about to read 5, iclass 22, count 0 2006.285.14:49:46.99#ibcon#read 5, iclass 22, count 0 2006.285.14:49:46.99#ibcon#about to read 6, iclass 22, count 0 2006.285.14:49:46.99#ibcon#read 6, iclass 22, count 0 2006.285.14:49:46.99#ibcon#end of sib2, iclass 22, count 0 2006.285.14:49:46.99#ibcon#*mode == 0, iclass 22, count 0 2006.285.14:49:46.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.14:49:46.99#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.14:49:46.99#ibcon#*before write, iclass 22, count 0 2006.285.14:49:46.99#ibcon#enter sib2, iclass 22, count 0 2006.285.14:49:46.99#ibcon#flushed, iclass 22, count 0 2006.285.14:49:46.99#ibcon#about to write, iclass 22, count 0 2006.285.14:49:46.99#ibcon#wrote, iclass 22, count 0 2006.285.14:49:46.99#ibcon#about to read 3, iclass 22, count 0 2006.285.14:49:47.03#ibcon#read 3, iclass 22, count 0 2006.285.14:49:47.03#ibcon#about to read 4, iclass 22, count 0 2006.285.14:49:47.03#ibcon#read 4, iclass 22, count 0 2006.285.14:49:47.03#ibcon#about to read 5, iclass 22, count 0 2006.285.14:49:47.03#ibcon#read 5, iclass 22, count 0 2006.285.14:49:47.03#ibcon#about to read 6, iclass 22, count 0 2006.285.14:49:47.03#ibcon#read 6, iclass 22, count 0 2006.285.14:49:47.03#ibcon#end of sib2, iclass 22, count 0 2006.285.14:49:47.03#ibcon#*after write, iclass 22, count 0 2006.285.14:49:47.03#ibcon#*before return 0, iclass 22, count 0 2006.285.14:49:47.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:49:47.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:49:47.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.14:49:47.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.14:49:47.03$vck44/va=7,4 2006.285.14:49:47.03#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.14:49:47.03#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.14:49:47.03#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:47.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:49:47.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:49:47.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:49:47.09#ibcon#enter wrdev, iclass 24, count 2 2006.285.14:49:47.09#ibcon#first serial, iclass 24, count 2 2006.285.14:49:47.09#ibcon#enter sib2, iclass 24, count 2 2006.285.14:49:47.09#ibcon#flushed, iclass 24, count 2 2006.285.14:49:47.09#ibcon#about to write, iclass 24, count 2 2006.285.14:49:47.09#ibcon#wrote, iclass 24, count 2 2006.285.14:49:47.09#ibcon#about to read 3, iclass 24, count 2 2006.285.14:49:47.11#ibcon#read 3, iclass 24, count 2 2006.285.14:49:47.11#ibcon#about to read 4, iclass 24, count 2 2006.285.14:49:47.11#ibcon#read 4, iclass 24, count 2 2006.285.14:49:47.11#ibcon#about to read 5, iclass 24, count 2 2006.285.14:49:47.11#ibcon#read 5, iclass 24, count 2 2006.285.14:49:47.11#ibcon#about to read 6, iclass 24, count 2 2006.285.14:49:47.11#ibcon#read 6, iclass 24, count 2 2006.285.14:49:47.11#ibcon#end of sib2, iclass 24, count 2 2006.285.14:49:47.11#ibcon#*mode == 0, iclass 24, count 2 2006.285.14:49:47.11#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.14:49:47.11#ibcon#[25=AT07-04\r\n] 2006.285.14:49:47.11#ibcon#*before write, iclass 24, count 2 2006.285.14:49:47.11#ibcon#enter sib2, iclass 24, count 2 2006.285.14:49:47.11#ibcon#flushed, iclass 24, count 2 2006.285.14:49:47.11#ibcon#about to write, iclass 24, count 2 2006.285.14:49:47.11#ibcon#wrote, iclass 24, count 2 2006.285.14:49:47.11#ibcon#about to read 3, iclass 24, count 2 2006.285.14:49:47.14#ibcon#read 3, iclass 24, count 2 2006.285.14:49:47.14#ibcon#about to read 4, iclass 24, count 2 2006.285.14:49:47.14#ibcon#read 4, iclass 24, count 2 2006.285.14:49:47.14#ibcon#about to read 5, iclass 24, count 2 2006.285.14:49:47.14#ibcon#read 5, iclass 24, count 2 2006.285.14:49:47.14#ibcon#about to read 6, iclass 24, count 2 2006.285.14:49:47.14#ibcon#read 6, iclass 24, count 2 2006.285.14:49:47.14#ibcon#end of sib2, iclass 24, count 2 2006.285.14:49:47.14#ibcon#*after write, iclass 24, count 2 2006.285.14:49:47.14#ibcon#*before return 0, iclass 24, count 2 2006.285.14:49:47.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:49:47.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:49:47.14#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.14:49:47.14#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:47.14#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:49:47.26#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:49:47.26#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:49:47.26#ibcon#enter wrdev, iclass 24, count 0 2006.285.14:49:47.26#ibcon#first serial, iclass 24, count 0 2006.285.14:49:47.26#ibcon#enter sib2, iclass 24, count 0 2006.285.14:49:47.26#ibcon#flushed, iclass 24, count 0 2006.285.14:49:47.26#ibcon#about to write, iclass 24, count 0 2006.285.14:49:47.26#ibcon#wrote, iclass 24, count 0 2006.285.14:49:47.26#ibcon#about to read 3, iclass 24, count 0 2006.285.14:49:47.28#ibcon#read 3, iclass 24, count 0 2006.285.14:49:47.28#ibcon#about to read 4, iclass 24, count 0 2006.285.14:49:47.28#ibcon#read 4, iclass 24, count 0 2006.285.14:49:47.28#ibcon#about to read 5, iclass 24, count 0 2006.285.14:49:47.28#ibcon#read 5, iclass 24, count 0 2006.285.14:49:47.28#ibcon#about to read 6, iclass 24, count 0 2006.285.14:49:47.28#ibcon#read 6, iclass 24, count 0 2006.285.14:49:47.28#ibcon#end of sib2, iclass 24, count 0 2006.285.14:49:47.28#ibcon#*mode == 0, iclass 24, count 0 2006.285.14:49:47.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.14:49:47.28#ibcon#[25=USB\r\n] 2006.285.14:49:47.28#ibcon#*before write, iclass 24, count 0 2006.285.14:49:47.28#ibcon#enter sib2, iclass 24, count 0 2006.285.14:49:47.28#ibcon#flushed, iclass 24, count 0 2006.285.14:49:47.28#ibcon#about to write, iclass 24, count 0 2006.285.14:49:47.28#ibcon#wrote, iclass 24, count 0 2006.285.14:49:47.28#ibcon#about to read 3, iclass 24, count 0 2006.285.14:49:47.31#ibcon#read 3, iclass 24, count 0 2006.285.14:49:47.31#ibcon#about to read 4, iclass 24, count 0 2006.285.14:49:47.31#ibcon#read 4, iclass 24, count 0 2006.285.14:49:47.31#ibcon#about to read 5, iclass 24, count 0 2006.285.14:49:47.31#ibcon#read 5, iclass 24, count 0 2006.285.14:49:47.31#ibcon#about to read 6, iclass 24, count 0 2006.285.14:49:47.31#ibcon#read 6, iclass 24, count 0 2006.285.14:49:47.31#ibcon#end of sib2, iclass 24, count 0 2006.285.14:49:47.31#ibcon#*after write, iclass 24, count 0 2006.285.14:49:47.31#ibcon#*before return 0, iclass 24, count 0 2006.285.14:49:47.31#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:49:47.31#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:49:47.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.14:49:47.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.14:49:47.31$vck44/valo=8,884.99 2006.285.14:49:47.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.14:49:47.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.14:49:47.31#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:47.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:49:47.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:49:47.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:49:47.31#ibcon#enter wrdev, iclass 26, count 0 2006.285.14:49:47.31#ibcon#first serial, iclass 26, count 0 2006.285.14:49:47.31#ibcon#enter sib2, iclass 26, count 0 2006.285.14:49:47.31#ibcon#flushed, iclass 26, count 0 2006.285.14:49:47.31#ibcon#about to write, iclass 26, count 0 2006.285.14:49:47.31#ibcon#wrote, iclass 26, count 0 2006.285.14:49:47.31#ibcon#about to read 3, iclass 26, count 0 2006.285.14:49:47.33#ibcon#read 3, iclass 26, count 0 2006.285.14:49:47.33#ibcon#about to read 4, iclass 26, count 0 2006.285.14:49:47.33#ibcon#read 4, iclass 26, count 0 2006.285.14:49:47.33#ibcon#about to read 5, iclass 26, count 0 2006.285.14:49:47.33#ibcon#read 5, iclass 26, count 0 2006.285.14:49:47.33#ibcon#about to read 6, iclass 26, count 0 2006.285.14:49:47.33#ibcon#read 6, iclass 26, count 0 2006.285.14:49:47.33#ibcon#end of sib2, iclass 26, count 0 2006.285.14:49:47.33#ibcon#*mode == 0, iclass 26, count 0 2006.285.14:49:47.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.14:49:47.33#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.14:49:47.33#ibcon#*before write, iclass 26, count 0 2006.285.14:49:47.33#ibcon#enter sib2, iclass 26, count 0 2006.285.14:49:47.33#ibcon#flushed, iclass 26, count 0 2006.285.14:49:47.33#ibcon#about to write, iclass 26, count 0 2006.285.14:49:47.33#ibcon#wrote, iclass 26, count 0 2006.285.14:49:47.33#ibcon#about to read 3, iclass 26, count 0 2006.285.14:49:47.37#ibcon#read 3, iclass 26, count 0 2006.285.14:49:47.37#ibcon#about to read 4, iclass 26, count 0 2006.285.14:49:47.37#ibcon#read 4, iclass 26, count 0 2006.285.14:49:47.37#ibcon#about to read 5, iclass 26, count 0 2006.285.14:49:47.37#ibcon#read 5, iclass 26, count 0 2006.285.14:49:47.37#ibcon#about to read 6, iclass 26, count 0 2006.285.14:49:47.37#ibcon#read 6, iclass 26, count 0 2006.285.14:49:47.37#ibcon#end of sib2, iclass 26, count 0 2006.285.14:49:47.37#ibcon#*after write, iclass 26, count 0 2006.285.14:49:47.37#ibcon#*before return 0, iclass 26, count 0 2006.285.14:49:47.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:49:47.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:49:47.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.14:49:47.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.14:49:47.37$vck44/va=8,3 2006.285.14:49:47.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.14:49:47.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.14:49:47.37#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:47.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:49:47.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:49:47.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:49:47.43#ibcon#enter wrdev, iclass 28, count 2 2006.285.14:49:47.43#ibcon#first serial, iclass 28, count 2 2006.285.14:49:47.43#ibcon#enter sib2, iclass 28, count 2 2006.285.14:49:47.43#ibcon#flushed, iclass 28, count 2 2006.285.14:49:47.43#ibcon#about to write, iclass 28, count 2 2006.285.14:49:47.43#ibcon#wrote, iclass 28, count 2 2006.285.14:49:47.43#ibcon#about to read 3, iclass 28, count 2 2006.285.14:49:47.45#ibcon#read 3, iclass 28, count 2 2006.285.14:49:47.45#ibcon#about to read 4, iclass 28, count 2 2006.285.14:49:47.45#ibcon#read 4, iclass 28, count 2 2006.285.14:49:47.45#ibcon#about to read 5, iclass 28, count 2 2006.285.14:49:47.45#ibcon#read 5, iclass 28, count 2 2006.285.14:49:47.45#ibcon#about to read 6, iclass 28, count 2 2006.285.14:49:47.45#ibcon#read 6, iclass 28, count 2 2006.285.14:49:47.45#ibcon#end of sib2, iclass 28, count 2 2006.285.14:49:47.45#ibcon#*mode == 0, iclass 28, count 2 2006.285.14:49:47.45#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.14:49:47.45#ibcon#[25=AT08-03\r\n] 2006.285.14:49:47.45#ibcon#*before write, iclass 28, count 2 2006.285.14:49:47.45#ibcon#enter sib2, iclass 28, count 2 2006.285.14:49:47.45#ibcon#flushed, iclass 28, count 2 2006.285.14:49:47.45#ibcon#about to write, iclass 28, count 2 2006.285.14:49:47.45#ibcon#wrote, iclass 28, count 2 2006.285.14:49:47.45#ibcon#about to read 3, iclass 28, count 2 2006.285.14:49:47.48#ibcon#read 3, iclass 28, count 2 2006.285.14:49:47.48#ibcon#about to read 4, iclass 28, count 2 2006.285.14:49:47.48#ibcon#read 4, iclass 28, count 2 2006.285.14:49:47.48#ibcon#about to read 5, iclass 28, count 2 2006.285.14:49:47.48#ibcon#read 5, iclass 28, count 2 2006.285.14:49:47.48#ibcon#about to read 6, iclass 28, count 2 2006.285.14:49:47.48#ibcon#read 6, iclass 28, count 2 2006.285.14:49:47.48#ibcon#end of sib2, iclass 28, count 2 2006.285.14:49:47.48#ibcon#*after write, iclass 28, count 2 2006.285.14:49:47.48#ibcon#*before return 0, iclass 28, count 2 2006.285.14:49:47.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:49:47.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:49:47.48#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.14:49:47.48#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:47.48#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:49:47.60#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:49:47.60#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:49:47.60#ibcon#enter wrdev, iclass 28, count 0 2006.285.14:49:47.60#ibcon#first serial, iclass 28, count 0 2006.285.14:49:47.60#ibcon#enter sib2, iclass 28, count 0 2006.285.14:49:47.60#ibcon#flushed, iclass 28, count 0 2006.285.14:49:47.60#ibcon#about to write, iclass 28, count 0 2006.285.14:49:47.60#ibcon#wrote, iclass 28, count 0 2006.285.14:49:47.60#ibcon#about to read 3, iclass 28, count 0 2006.285.14:49:47.62#ibcon#read 3, iclass 28, count 0 2006.285.14:49:47.62#ibcon#about to read 4, iclass 28, count 0 2006.285.14:49:47.62#ibcon#read 4, iclass 28, count 0 2006.285.14:49:47.62#ibcon#about to read 5, iclass 28, count 0 2006.285.14:49:47.62#ibcon#read 5, iclass 28, count 0 2006.285.14:49:47.62#ibcon#about to read 6, iclass 28, count 0 2006.285.14:49:47.62#ibcon#read 6, iclass 28, count 0 2006.285.14:49:47.62#ibcon#end of sib2, iclass 28, count 0 2006.285.14:49:47.62#ibcon#*mode == 0, iclass 28, count 0 2006.285.14:49:47.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.14:49:47.62#ibcon#[25=USB\r\n] 2006.285.14:49:47.62#ibcon#*before write, iclass 28, count 0 2006.285.14:49:47.62#ibcon#enter sib2, iclass 28, count 0 2006.285.14:49:47.62#ibcon#flushed, iclass 28, count 0 2006.285.14:49:47.62#ibcon#about to write, iclass 28, count 0 2006.285.14:49:47.62#ibcon#wrote, iclass 28, count 0 2006.285.14:49:47.62#ibcon#about to read 3, iclass 28, count 0 2006.285.14:49:47.65#ibcon#read 3, iclass 28, count 0 2006.285.14:49:47.65#ibcon#about to read 4, iclass 28, count 0 2006.285.14:49:47.65#ibcon#read 4, iclass 28, count 0 2006.285.14:49:47.65#ibcon#about to read 5, iclass 28, count 0 2006.285.14:49:47.65#ibcon#read 5, iclass 28, count 0 2006.285.14:49:47.65#ibcon#about to read 6, iclass 28, count 0 2006.285.14:49:47.65#ibcon#read 6, iclass 28, count 0 2006.285.14:49:47.65#ibcon#end of sib2, iclass 28, count 0 2006.285.14:49:47.65#ibcon#*after write, iclass 28, count 0 2006.285.14:49:47.65#ibcon#*before return 0, iclass 28, count 0 2006.285.14:49:47.65#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:49:47.65#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:49:47.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.14:49:47.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.14:49:47.65$vck44/vblo=1,629.99 2006.285.14:49:47.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.14:49:47.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.14:49:47.65#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:47.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:49:47.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:49:47.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:49:47.65#ibcon#enter wrdev, iclass 30, count 0 2006.285.14:49:47.65#ibcon#first serial, iclass 30, count 0 2006.285.14:49:47.65#ibcon#enter sib2, iclass 30, count 0 2006.285.14:49:47.65#ibcon#flushed, iclass 30, count 0 2006.285.14:49:47.65#ibcon#about to write, iclass 30, count 0 2006.285.14:49:47.65#ibcon#wrote, iclass 30, count 0 2006.285.14:49:47.65#ibcon#about to read 3, iclass 30, count 0 2006.285.14:49:47.67#ibcon#read 3, iclass 30, count 0 2006.285.14:49:47.67#ibcon#about to read 4, iclass 30, count 0 2006.285.14:49:47.67#ibcon#read 4, iclass 30, count 0 2006.285.14:49:47.67#ibcon#about to read 5, iclass 30, count 0 2006.285.14:49:47.67#ibcon#read 5, iclass 30, count 0 2006.285.14:49:47.67#ibcon#about to read 6, iclass 30, count 0 2006.285.14:49:47.67#ibcon#read 6, iclass 30, count 0 2006.285.14:49:47.67#ibcon#end of sib2, iclass 30, count 0 2006.285.14:49:47.67#ibcon#*mode == 0, iclass 30, count 0 2006.285.14:49:47.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.14:49:47.67#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.14:49:47.67#ibcon#*before write, iclass 30, count 0 2006.285.14:49:47.67#ibcon#enter sib2, iclass 30, count 0 2006.285.14:49:47.67#ibcon#flushed, iclass 30, count 0 2006.285.14:49:47.67#ibcon#about to write, iclass 30, count 0 2006.285.14:49:47.67#ibcon#wrote, iclass 30, count 0 2006.285.14:49:47.67#ibcon#about to read 3, iclass 30, count 0 2006.285.14:49:47.71#ibcon#read 3, iclass 30, count 0 2006.285.14:49:47.71#ibcon#about to read 4, iclass 30, count 0 2006.285.14:49:47.71#ibcon#read 4, iclass 30, count 0 2006.285.14:49:47.71#ibcon#about to read 5, iclass 30, count 0 2006.285.14:49:47.71#ibcon#read 5, iclass 30, count 0 2006.285.14:49:47.71#ibcon#about to read 6, iclass 30, count 0 2006.285.14:49:47.71#ibcon#read 6, iclass 30, count 0 2006.285.14:49:47.71#ibcon#end of sib2, iclass 30, count 0 2006.285.14:49:47.71#ibcon#*after write, iclass 30, count 0 2006.285.14:49:47.71#ibcon#*before return 0, iclass 30, count 0 2006.285.14:49:47.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:49:47.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:49:47.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.14:49:47.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.14:49:47.71$vck44/vb=1,4 2006.285.14:49:47.71#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.14:49:47.71#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.14:49:47.71#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:47.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:49:47.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:49:47.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:49:47.71#ibcon#enter wrdev, iclass 32, count 2 2006.285.14:49:47.71#ibcon#first serial, iclass 32, count 2 2006.285.14:49:47.71#ibcon#enter sib2, iclass 32, count 2 2006.285.14:49:47.71#ibcon#flushed, iclass 32, count 2 2006.285.14:49:47.71#ibcon#about to write, iclass 32, count 2 2006.285.14:49:47.71#ibcon#wrote, iclass 32, count 2 2006.285.14:49:47.71#ibcon#about to read 3, iclass 32, count 2 2006.285.14:49:47.73#ibcon#read 3, iclass 32, count 2 2006.285.14:49:47.73#ibcon#about to read 4, iclass 32, count 2 2006.285.14:49:47.73#ibcon#read 4, iclass 32, count 2 2006.285.14:49:47.73#ibcon#about to read 5, iclass 32, count 2 2006.285.14:49:47.73#ibcon#read 5, iclass 32, count 2 2006.285.14:49:47.73#ibcon#about to read 6, iclass 32, count 2 2006.285.14:49:47.73#ibcon#read 6, iclass 32, count 2 2006.285.14:49:47.73#ibcon#end of sib2, iclass 32, count 2 2006.285.14:49:47.73#ibcon#*mode == 0, iclass 32, count 2 2006.285.14:49:47.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.14:49:47.73#ibcon#[27=AT01-04\r\n] 2006.285.14:49:47.73#ibcon#*before write, iclass 32, count 2 2006.285.14:49:47.73#ibcon#enter sib2, iclass 32, count 2 2006.285.14:49:47.73#ibcon#flushed, iclass 32, count 2 2006.285.14:49:47.73#ibcon#about to write, iclass 32, count 2 2006.285.14:49:47.73#ibcon#wrote, iclass 32, count 2 2006.285.14:49:47.73#ibcon#about to read 3, iclass 32, count 2 2006.285.14:49:47.76#ibcon#read 3, iclass 32, count 2 2006.285.14:49:47.76#ibcon#about to read 4, iclass 32, count 2 2006.285.14:49:47.76#ibcon#read 4, iclass 32, count 2 2006.285.14:49:47.76#ibcon#about to read 5, iclass 32, count 2 2006.285.14:49:47.76#ibcon#read 5, iclass 32, count 2 2006.285.14:49:47.76#ibcon#about to read 6, iclass 32, count 2 2006.285.14:49:47.76#ibcon#read 6, iclass 32, count 2 2006.285.14:49:47.76#ibcon#end of sib2, iclass 32, count 2 2006.285.14:49:47.76#ibcon#*after write, iclass 32, count 2 2006.285.14:49:47.76#ibcon#*before return 0, iclass 32, count 2 2006.285.14:49:47.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:49:47.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.14:49:47.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.14:49:47.76#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:47.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:49:47.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:49:47.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:49:47.88#ibcon#enter wrdev, iclass 32, count 0 2006.285.14:49:47.88#ibcon#first serial, iclass 32, count 0 2006.285.14:49:47.88#ibcon#enter sib2, iclass 32, count 0 2006.285.14:49:47.88#ibcon#flushed, iclass 32, count 0 2006.285.14:49:47.88#ibcon#about to write, iclass 32, count 0 2006.285.14:49:47.88#ibcon#wrote, iclass 32, count 0 2006.285.14:49:47.88#ibcon#about to read 3, iclass 32, count 0 2006.285.14:49:47.90#ibcon#read 3, iclass 32, count 0 2006.285.14:49:47.90#ibcon#about to read 4, iclass 32, count 0 2006.285.14:49:47.90#ibcon#read 4, iclass 32, count 0 2006.285.14:49:47.90#ibcon#about to read 5, iclass 32, count 0 2006.285.14:49:47.90#ibcon#read 5, iclass 32, count 0 2006.285.14:49:47.90#ibcon#about to read 6, iclass 32, count 0 2006.285.14:49:47.90#ibcon#read 6, iclass 32, count 0 2006.285.14:49:47.90#ibcon#end of sib2, iclass 32, count 0 2006.285.14:49:47.90#ibcon#*mode == 0, iclass 32, count 0 2006.285.14:49:47.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.14:49:47.90#ibcon#[27=USB\r\n] 2006.285.14:49:47.90#ibcon#*before write, iclass 32, count 0 2006.285.14:49:47.90#ibcon#enter sib2, iclass 32, count 0 2006.285.14:49:47.90#ibcon#flushed, iclass 32, count 0 2006.285.14:49:47.90#ibcon#about to write, iclass 32, count 0 2006.285.14:49:47.90#ibcon#wrote, iclass 32, count 0 2006.285.14:49:47.90#ibcon#about to read 3, iclass 32, count 0 2006.285.14:49:47.93#ibcon#read 3, iclass 32, count 0 2006.285.14:49:47.93#ibcon#about to read 4, iclass 32, count 0 2006.285.14:49:47.93#ibcon#read 4, iclass 32, count 0 2006.285.14:49:47.93#ibcon#about to read 5, iclass 32, count 0 2006.285.14:49:47.93#ibcon#read 5, iclass 32, count 0 2006.285.14:49:47.93#ibcon#about to read 6, iclass 32, count 0 2006.285.14:49:47.93#ibcon#read 6, iclass 32, count 0 2006.285.14:49:47.93#ibcon#end of sib2, iclass 32, count 0 2006.285.14:49:47.93#ibcon#*after write, iclass 32, count 0 2006.285.14:49:47.93#ibcon#*before return 0, iclass 32, count 0 2006.285.14:49:47.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:49:47.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.14:49:47.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.14:49:47.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.14:49:47.93$vck44/vblo=2,634.99 2006.285.14:49:47.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.14:49:47.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.14:49:47.93#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:47.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:49:47.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:49:47.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:49:47.93#ibcon#enter wrdev, iclass 34, count 0 2006.285.14:49:47.93#ibcon#first serial, iclass 34, count 0 2006.285.14:49:47.93#ibcon#enter sib2, iclass 34, count 0 2006.285.14:49:47.93#ibcon#flushed, iclass 34, count 0 2006.285.14:49:47.93#ibcon#about to write, iclass 34, count 0 2006.285.14:49:47.93#ibcon#wrote, iclass 34, count 0 2006.285.14:49:47.93#ibcon#about to read 3, iclass 34, count 0 2006.285.14:49:47.95#ibcon#read 3, iclass 34, count 0 2006.285.14:49:47.95#ibcon#about to read 4, iclass 34, count 0 2006.285.14:49:47.95#ibcon#read 4, iclass 34, count 0 2006.285.14:49:47.95#ibcon#about to read 5, iclass 34, count 0 2006.285.14:49:47.95#ibcon#read 5, iclass 34, count 0 2006.285.14:49:47.95#ibcon#about to read 6, iclass 34, count 0 2006.285.14:49:47.95#ibcon#read 6, iclass 34, count 0 2006.285.14:49:47.95#ibcon#end of sib2, iclass 34, count 0 2006.285.14:49:47.95#ibcon#*mode == 0, iclass 34, count 0 2006.285.14:49:47.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.14:49:47.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.14:49:47.95#ibcon#*before write, iclass 34, count 0 2006.285.14:49:47.95#ibcon#enter sib2, iclass 34, count 0 2006.285.14:49:47.95#ibcon#flushed, iclass 34, count 0 2006.285.14:49:47.95#ibcon#about to write, iclass 34, count 0 2006.285.14:49:47.95#ibcon#wrote, iclass 34, count 0 2006.285.14:49:47.95#ibcon#about to read 3, iclass 34, count 0 2006.285.14:49:47.99#abcon#<5=/03 2.0 5.0 19.15 931015.0\r\n> 2006.285.14:49:47.99#ibcon#read 3, iclass 34, count 0 2006.285.14:49:47.99#ibcon#about to read 4, iclass 34, count 0 2006.285.14:49:47.99#ibcon#read 4, iclass 34, count 0 2006.285.14:49:47.99#ibcon#about to read 5, iclass 34, count 0 2006.285.14:49:47.99#ibcon#read 5, iclass 34, count 0 2006.285.14:49:47.99#ibcon#about to read 6, iclass 34, count 0 2006.285.14:49:47.99#ibcon#read 6, iclass 34, count 0 2006.285.14:49:47.99#ibcon#end of sib2, iclass 34, count 0 2006.285.14:49:47.99#ibcon#*after write, iclass 34, count 0 2006.285.14:49:47.99#ibcon#*before return 0, iclass 34, count 0 2006.285.14:49:47.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:49:47.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.14:49:47.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.14:49:47.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.14:49:47.99$vck44/vb=2,5 2006.285.14:49:47.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.14:49:47.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.14:49:47.99#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:47.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:49:48.01#abcon#{5=INTERFACE CLEAR} 2006.285.14:49:48.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:49:48.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:49:48.05#ibcon#enter wrdev, iclass 39, count 2 2006.285.14:49:48.05#ibcon#first serial, iclass 39, count 2 2006.285.14:49:48.05#ibcon#enter sib2, iclass 39, count 2 2006.285.14:49:48.05#ibcon#flushed, iclass 39, count 2 2006.285.14:49:48.05#ibcon#about to write, iclass 39, count 2 2006.285.14:49:48.05#ibcon#wrote, iclass 39, count 2 2006.285.14:49:48.05#ibcon#about to read 3, iclass 39, count 2 2006.285.14:49:48.07#ibcon#read 3, iclass 39, count 2 2006.285.14:49:48.07#ibcon#about to read 4, iclass 39, count 2 2006.285.14:49:48.07#ibcon#read 4, iclass 39, count 2 2006.285.14:49:48.07#ibcon#about to read 5, iclass 39, count 2 2006.285.14:49:48.07#ibcon#read 5, iclass 39, count 2 2006.285.14:49:48.07#ibcon#about to read 6, iclass 39, count 2 2006.285.14:49:48.07#ibcon#read 6, iclass 39, count 2 2006.285.14:49:48.07#ibcon#end of sib2, iclass 39, count 2 2006.285.14:49:48.07#ibcon#*mode == 0, iclass 39, count 2 2006.285.14:49:48.07#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.14:49:48.07#ibcon#[27=AT02-05\r\n] 2006.285.14:49:48.07#ibcon#*before write, iclass 39, count 2 2006.285.14:49:48.07#ibcon#enter sib2, iclass 39, count 2 2006.285.14:49:48.07#ibcon#flushed, iclass 39, count 2 2006.285.14:49:48.07#ibcon#about to write, iclass 39, count 2 2006.285.14:49:48.07#ibcon#wrote, iclass 39, count 2 2006.285.14:49:48.07#ibcon#about to read 3, iclass 39, count 2 2006.285.14:49:48.07#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:49:48.10#ibcon#read 3, iclass 39, count 2 2006.285.14:49:48.10#ibcon#about to read 4, iclass 39, count 2 2006.285.14:49:48.10#ibcon#read 4, iclass 39, count 2 2006.285.14:49:48.10#ibcon#about to read 5, iclass 39, count 2 2006.285.14:49:48.10#ibcon#read 5, iclass 39, count 2 2006.285.14:49:48.10#ibcon#about to read 6, iclass 39, count 2 2006.285.14:49:48.10#ibcon#read 6, iclass 39, count 2 2006.285.14:49:48.10#ibcon#end of sib2, iclass 39, count 2 2006.285.14:49:48.10#ibcon#*after write, iclass 39, count 2 2006.285.14:49:48.10#ibcon#*before return 0, iclass 39, count 2 2006.285.14:49:48.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:49:48.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:49:48.10#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.14:49:48.10#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:48.10#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:49:48.22#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:49:48.22#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:49:48.22#ibcon#enter wrdev, iclass 39, count 0 2006.285.14:49:48.22#ibcon#first serial, iclass 39, count 0 2006.285.14:49:48.22#ibcon#enter sib2, iclass 39, count 0 2006.285.14:49:48.22#ibcon#flushed, iclass 39, count 0 2006.285.14:49:48.22#ibcon#about to write, iclass 39, count 0 2006.285.14:49:48.22#ibcon#wrote, iclass 39, count 0 2006.285.14:49:48.22#ibcon#about to read 3, iclass 39, count 0 2006.285.14:49:48.24#ibcon#read 3, iclass 39, count 0 2006.285.14:49:48.24#ibcon#about to read 4, iclass 39, count 0 2006.285.14:49:48.24#ibcon#read 4, iclass 39, count 0 2006.285.14:49:48.24#ibcon#about to read 5, iclass 39, count 0 2006.285.14:49:48.24#ibcon#read 5, iclass 39, count 0 2006.285.14:49:48.24#ibcon#about to read 6, iclass 39, count 0 2006.285.14:49:48.24#ibcon#read 6, iclass 39, count 0 2006.285.14:49:48.24#ibcon#end of sib2, iclass 39, count 0 2006.285.14:49:48.24#ibcon#*mode == 0, iclass 39, count 0 2006.285.14:49:48.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.14:49:48.24#ibcon#[27=USB\r\n] 2006.285.14:49:48.24#ibcon#*before write, iclass 39, count 0 2006.285.14:49:48.24#ibcon#enter sib2, iclass 39, count 0 2006.285.14:49:48.24#ibcon#flushed, iclass 39, count 0 2006.285.14:49:48.24#ibcon#about to write, iclass 39, count 0 2006.285.14:49:48.24#ibcon#wrote, iclass 39, count 0 2006.285.14:49:48.24#ibcon#about to read 3, iclass 39, count 0 2006.285.14:49:48.27#ibcon#read 3, iclass 39, count 0 2006.285.14:49:48.27#ibcon#about to read 4, iclass 39, count 0 2006.285.14:49:48.27#ibcon#read 4, iclass 39, count 0 2006.285.14:49:48.27#ibcon#about to read 5, iclass 39, count 0 2006.285.14:49:48.27#ibcon#read 5, iclass 39, count 0 2006.285.14:49:48.27#ibcon#about to read 6, iclass 39, count 0 2006.285.14:49:48.27#ibcon#read 6, iclass 39, count 0 2006.285.14:49:48.27#ibcon#end of sib2, iclass 39, count 0 2006.285.14:49:48.27#ibcon#*after write, iclass 39, count 0 2006.285.14:49:48.27#ibcon#*before return 0, iclass 39, count 0 2006.285.14:49:48.27#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:49:48.27#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:49:48.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.14:49:48.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.14:49:48.27$vck44/vblo=3,649.99 2006.285.14:49:48.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.14:49:48.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.14:49:48.27#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:48.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:49:48.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:49:48.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:49:48.27#ibcon#enter wrdev, iclass 4, count 0 2006.285.14:49:48.27#ibcon#first serial, iclass 4, count 0 2006.285.14:49:48.27#ibcon#enter sib2, iclass 4, count 0 2006.285.14:49:48.27#ibcon#flushed, iclass 4, count 0 2006.285.14:49:48.27#ibcon#about to write, iclass 4, count 0 2006.285.14:49:48.27#ibcon#wrote, iclass 4, count 0 2006.285.14:49:48.27#ibcon#about to read 3, iclass 4, count 0 2006.285.14:49:48.29#ibcon#read 3, iclass 4, count 0 2006.285.14:49:48.29#ibcon#about to read 4, iclass 4, count 0 2006.285.14:49:48.29#ibcon#read 4, iclass 4, count 0 2006.285.14:49:48.29#ibcon#about to read 5, iclass 4, count 0 2006.285.14:49:48.29#ibcon#read 5, iclass 4, count 0 2006.285.14:49:48.29#ibcon#about to read 6, iclass 4, count 0 2006.285.14:49:48.29#ibcon#read 6, iclass 4, count 0 2006.285.14:49:48.29#ibcon#end of sib2, iclass 4, count 0 2006.285.14:49:48.29#ibcon#*mode == 0, iclass 4, count 0 2006.285.14:49:48.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.14:49:48.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.14:49:48.29#ibcon#*before write, iclass 4, count 0 2006.285.14:49:48.29#ibcon#enter sib2, iclass 4, count 0 2006.285.14:49:48.29#ibcon#flushed, iclass 4, count 0 2006.285.14:49:48.29#ibcon#about to write, iclass 4, count 0 2006.285.14:49:48.29#ibcon#wrote, iclass 4, count 0 2006.285.14:49:48.29#ibcon#about to read 3, iclass 4, count 0 2006.285.14:49:48.33#ibcon#read 3, iclass 4, count 0 2006.285.14:49:48.33#ibcon#about to read 4, iclass 4, count 0 2006.285.14:49:48.33#ibcon#read 4, iclass 4, count 0 2006.285.14:49:48.33#ibcon#about to read 5, iclass 4, count 0 2006.285.14:49:48.33#ibcon#read 5, iclass 4, count 0 2006.285.14:49:48.33#ibcon#about to read 6, iclass 4, count 0 2006.285.14:49:48.33#ibcon#read 6, iclass 4, count 0 2006.285.14:49:48.33#ibcon#end of sib2, iclass 4, count 0 2006.285.14:49:48.33#ibcon#*after write, iclass 4, count 0 2006.285.14:49:48.33#ibcon#*before return 0, iclass 4, count 0 2006.285.14:49:48.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:49:48.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.14:49:48.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.14:49:48.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.14:49:48.33$vck44/vb=3,4 2006.285.14:49:48.33#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.14:49:48.33#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.14:49:48.33#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:48.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:49:48.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:49:48.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:49:48.39#ibcon#enter wrdev, iclass 6, count 2 2006.285.14:49:48.39#ibcon#first serial, iclass 6, count 2 2006.285.14:49:48.39#ibcon#enter sib2, iclass 6, count 2 2006.285.14:49:48.39#ibcon#flushed, iclass 6, count 2 2006.285.14:49:48.39#ibcon#about to write, iclass 6, count 2 2006.285.14:49:48.39#ibcon#wrote, iclass 6, count 2 2006.285.14:49:48.39#ibcon#about to read 3, iclass 6, count 2 2006.285.14:49:48.41#ibcon#read 3, iclass 6, count 2 2006.285.14:49:48.41#ibcon#about to read 4, iclass 6, count 2 2006.285.14:49:48.41#ibcon#read 4, iclass 6, count 2 2006.285.14:49:48.41#ibcon#about to read 5, iclass 6, count 2 2006.285.14:49:48.41#ibcon#read 5, iclass 6, count 2 2006.285.14:49:48.41#ibcon#about to read 6, iclass 6, count 2 2006.285.14:49:48.41#ibcon#read 6, iclass 6, count 2 2006.285.14:49:48.41#ibcon#end of sib2, iclass 6, count 2 2006.285.14:49:48.41#ibcon#*mode == 0, iclass 6, count 2 2006.285.14:49:48.41#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.14:49:48.41#ibcon#[27=AT03-04\r\n] 2006.285.14:49:48.41#ibcon#*before write, iclass 6, count 2 2006.285.14:49:48.41#ibcon#enter sib2, iclass 6, count 2 2006.285.14:49:48.41#ibcon#flushed, iclass 6, count 2 2006.285.14:49:48.41#ibcon#about to write, iclass 6, count 2 2006.285.14:49:48.41#ibcon#wrote, iclass 6, count 2 2006.285.14:49:48.41#ibcon#about to read 3, iclass 6, count 2 2006.285.14:49:48.44#ibcon#read 3, iclass 6, count 2 2006.285.14:49:48.44#ibcon#about to read 4, iclass 6, count 2 2006.285.14:49:48.44#ibcon#read 4, iclass 6, count 2 2006.285.14:49:48.44#ibcon#about to read 5, iclass 6, count 2 2006.285.14:49:48.44#ibcon#read 5, iclass 6, count 2 2006.285.14:49:48.44#ibcon#about to read 6, iclass 6, count 2 2006.285.14:49:48.44#ibcon#read 6, iclass 6, count 2 2006.285.14:49:48.44#ibcon#end of sib2, iclass 6, count 2 2006.285.14:49:48.44#ibcon#*after write, iclass 6, count 2 2006.285.14:49:48.44#ibcon#*before return 0, iclass 6, count 2 2006.285.14:49:48.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:49:48.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.14:49:48.44#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.14:49:48.44#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:48.44#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:49:48.56#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:49:48.56#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:49:48.56#ibcon#enter wrdev, iclass 6, count 0 2006.285.14:49:48.56#ibcon#first serial, iclass 6, count 0 2006.285.14:49:48.56#ibcon#enter sib2, iclass 6, count 0 2006.285.14:49:48.56#ibcon#flushed, iclass 6, count 0 2006.285.14:49:48.56#ibcon#about to write, iclass 6, count 0 2006.285.14:49:48.56#ibcon#wrote, iclass 6, count 0 2006.285.14:49:48.56#ibcon#about to read 3, iclass 6, count 0 2006.285.14:49:48.58#ibcon#read 3, iclass 6, count 0 2006.285.14:49:48.58#ibcon#about to read 4, iclass 6, count 0 2006.285.14:49:48.58#ibcon#read 4, iclass 6, count 0 2006.285.14:49:48.58#ibcon#about to read 5, iclass 6, count 0 2006.285.14:49:48.58#ibcon#read 5, iclass 6, count 0 2006.285.14:49:48.58#ibcon#about to read 6, iclass 6, count 0 2006.285.14:49:48.58#ibcon#read 6, iclass 6, count 0 2006.285.14:49:48.58#ibcon#end of sib2, iclass 6, count 0 2006.285.14:49:48.58#ibcon#*mode == 0, iclass 6, count 0 2006.285.14:49:48.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.14:49:48.58#ibcon#[27=USB\r\n] 2006.285.14:49:48.58#ibcon#*before write, iclass 6, count 0 2006.285.14:49:48.58#ibcon#enter sib2, iclass 6, count 0 2006.285.14:49:48.58#ibcon#flushed, iclass 6, count 0 2006.285.14:49:48.58#ibcon#about to write, iclass 6, count 0 2006.285.14:49:48.58#ibcon#wrote, iclass 6, count 0 2006.285.14:49:48.58#ibcon#about to read 3, iclass 6, count 0 2006.285.14:49:48.61#ibcon#read 3, iclass 6, count 0 2006.285.14:49:48.61#ibcon#about to read 4, iclass 6, count 0 2006.285.14:49:48.61#ibcon#read 4, iclass 6, count 0 2006.285.14:49:48.61#ibcon#about to read 5, iclass 6, count 0 2006.285.14:49:48.61#ibcon#read 5, iclass 6, count 0 2006.285.14:49:48.61#ibcon#about to read 6, iclass 6, count 0 2006.285.14:49:48.61#ibcon#read 6, iclass 6, count 0 2006.285.14:49:48.61#ibcon#end of sib2, iclass 6, count 0 2006.285.14:49:48.61#ibcon#*after write, iclass 6, count 0 2006.285.14:49:48.61#ibcon#*before return 0, iclass 6, count 0 2006.285.14:49:48.61#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:49:48.61#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.14:49:48.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.14:49:48.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.14:49:48.61$vck44/vblo=4,679.99 2006.285.14:49:48.73#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.14:49:48.73#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.14:49:48.73#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:48.73#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:49:48.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:49:48.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:49:48.73#ibcon#enter wrdev, iclass 10, count 0 2006.285.14:49:48.73#ibcon#first serial, iclass 10, count 0 2006.285.14:49:48.73#ibcon#enter sib2, iclass 10, count 0 2006.285.14:49:48.73#ibcon#flushed, iclass 10, count 0 2006.285.14:49:48.73#ibcon#about to write, iclass 10, count 0 2006.285.14:49:48.73#ibcon#wrote, iclass 10, count 0 2006.285.14:49:48.73#ibcon#about to read 3, iclass 10, count 0 2006.285.14:49:48.74#ibcon#read 3, iclass 10, count 0 2006.285.14:49:48.74#ibcon#about to read 4, iclass 10, count 0 2006.285.14:49:48.74#ibcon#read 4, iclass 10, count 0 2006.285.14:49:48.74#ibcon#about to read 5, iclass 10, count 0 2006.285.14:49:48.74#ibcon#read 5, iclass 10, count 0 2006.285.14:49:48.74#ibcon#about to read 6, iclass 10, count 0 2006.285.14:49:48.74#ibcon#read 6, iclass 10, count 0 2006.285.14:49:48.74#ibcon#end of sib2, iclass 10, count 0 2006.285.14:49:48.74#ibcon#*mode == 0, iclass 10, count 0 2006.285.14:49:48.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.14:49:48.74#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.14:49:48.74#ibcon#*before write, iclass 10, count 0 2006.285.14:49:48.74#ibcon#enter sib2, iclass 10, count 0 2006.285.14:49:48.74#ibcon#flushed, iclass 10, count 0 2006.285.14:49:48.74#ibcon#about to write, iclass 10, count 0 2006.285.14:49:48.74#ibcon#wrote, iclass 10, count 0 2006.285.14:49:48.74#ibcon#about to read 3, iclass 10, count 0 2006.285.14:49:48.78#ibcon#read 3, iclass 10, count 0 2006.285.14:49:48.78#ibcon#about to read 4, iclass 10, count 0 2006.285.14:49:48.78#ibcon#read 4, iclass 10, count 0 2006.285.14:49:48.78#ibcon#about to read 5, iclass 10, count 0 2006.285.14:49:48.78#ibcon#read 5, iclass 10, count 0 2006.285.14:49:48.78#ibcon#about to read 6, iclass 10, count 0 2006.285.14:49:48.78#ibcon#read 6, iclass 10, count 0 2006.285.14:49:48.78#ibcon#end of sib2, iclass 10, count 0 2006.285.14:49:48.78#ibcon#*after write, iclass 10, count 0 2006.285.14:49:48.78#ibcon#*before return 0, iclass 10, count 0 2006.285.14:49:48.78#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:49:48.78#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.14:49:48.78#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.14:49:48.78#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.14:49:48.78$vck44/vb=4,5 2006.285.14:49:48.78#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.14:49:48.78#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.14:49:48.78#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:48.78#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:49:48.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:49:48.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:49:48.78#ibcon#enter wrdev, iclass 12, count 2 2006.285.14:49:48.78#ibcon#first serial, iclass 12, count 2 2006.285.14:49:48.78#ibcon#enter sib2, iclass 12, count 2 2006.285.14:49:48.78#ibcon#flushed, iclass 12, count 2 2006.285.14:49:48.78#ibcon#about to write, iclass 12, count 2 2006.285.14:49:48.78#ibcon#wrote, iclass 12, count 2 2006.285.14:49:48.78#ibcon#about to read 3, iclass 12, count 2 2006.285.14:49:48.80#ibcon#read 3, iclass 12, count 2 2006.285.14:49:48.80#ibcon#about to read 4, iclass 12, count 2 2006.285.14:49:48.80#ibcon#read 4, iclass 12, count 2 2006.285.14:49:48.80#ibcon#about to read 5, iclass 12, count 2 2006.285.14:49:48.80#ibcon#read 5, iclass 12, count 2 2006.285.14:49:48.80#ibcon#about to read 6, iclass 12, count 2 2006.285.14:49:48.80#ibcon#read 6, iclass 12, count 2 2006.285.14:49:48.80#ibcon#end of sib2, iclass 12, count 2 2006.285.14:49:48.80#ibcon#*mode == 0, iclass 12, count 2 2006.285.14:49:48.80#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.14:49:48.80#ibcon#[27=AT04-05\r\n] 2006.285.14:49:48.80#ibcon#*before write, iclass 12, count 2 2006.285.14:49:48.80#ibcon#enter sib2, iclass 12, count 2 2006.285.14:49:48.80#ibcon#flushed, iclass 12, count 2 2006.285.14:49:48.80#ibcon#about to write, iclass 12, count 2 2006.285.14:49:48.80#ibcon#wrote, iclass 12, count 2 2006.285.14:49:48.80#ibcon#about to read 3, iclass 12, count 2 2006.285.14:49:48.83#ibcon#read 3, iclass 12, count 2 2006.285.14:49:48.83#ibcon#about to read 4, iclass 12, count 2 2006.285.14:49:48.83#ibcon#read 4, iclass 12, count 2 2006.285.14:49:48.83#ibcon#about to read 5, iclass 12, count 2 2006.285.14:49:48.83#ibcon#read 5, iclass 12, count 2 2006.285.14:49:48.83#ibcon#about to read 6, iclass 12, count 2 2006.285.14:49:48.83#ibcon#read 6, iclass 12, count 2 2006.285.14:49:48.83#ibcon#end of sib2, iclass 12, count 2 2006.285.14:49:48.83#ibcon#*after write, iclass 12, count 2 2006.285.14:49:48.83#ibcon#*before return 0, iclass 12, count 2 2006.285.14:49:48.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:49:48.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.14:49:48.83#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.14:49:48.83#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:48.83#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:49:48.95#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:49:48.95#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:49:48.95#ibcon#enter wrdev, iclass 12, count 0 2006.285.14:49:48.95#ibcon#first serial, iclass 12, count 0 2006.285.14:49:48.95#ibcon#enter sib2, iclass 12, count 0 2006.285.14:49:48.95#ibcon#flushed, iclass 12, count 0 2006.285.14:49:48.95#ibcon#about to write, iclass 12, count 0 2006.285.14:49:48.95#ibcon#wrote, iclass 12, count 0 2006.285.14:49:48.95#ibcon#about to read 3, iclass 12, count 0 2006.285.14:49:48.97#ibcon#read 3, iclass 12, count 0 2006.285.14:49:48.97#ibcon#about to read 4, iclass 12, count 0 2006.285.14:49:48.97#ibcon#read 4, iclass 12, count 0 2006.285.14:49:48.97#ibcon#about to read 5, iclass 12, count 0 2006.285.14:49:48.97#ibcon#read 5, iclass 12, count 0 2006.285.14:49:48.97#ibcon#about to read 6, iclass 12, count 0 2006.285.14:49:48.97#ibcon#read 6, iclass 12, count 0 2006.285.14:49:48.97#ibcon#end of sib2, iclass 12, count 0 2006.285.14:49:48.97#ibcon#*mode == 0, iclass 12, count 0 2006.285.14:49:48.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.14:49:48.97#ibcon#[27=USB\r\n] 2006.285.14:49:48.97#ibcon#*before write, iclass 12, count 0 2006.285.14:49:48.97#ibcon#enter sib2, iclass 12, count 0 2006.285.14:49:48.97#ibcon#flushed, iclass 12, count 0 2006.285.14:49:48.97#ibcon#about to write, iclass 12, count 0 2006.285.14:49:48.97#ibcon#wrote, iclass 12, count 0 2006.285.14:49:48.97#ibcon#about to read 3, iclass 12, count 0 2006.285.14:49:49.00#ibcon#read 3, iclass 12, count 0 2006.285.14:49:49.00#ibcon#about to read 4, iclass 12, count 0 2006.285.14:49:49.00#ibcon#read 4, iclass 12, count 0 2006.285.14:49:49.00#ibcon#about to read 5, iclass 12, count 0 2006.285.14:49:49.00#ibcon#read 5, iclass 12, count 0 2006.285.14:49:49.00#ibcon#about to read 6, iclass 12, count 0 2006.285.14:49:49.00#ibcon#read 6, iclass 12, count 0 2006.285.14:49:49.00#ibcon#end of sib2, iclass 12, count 0 2006.285.14:49:49.00#ibcon#*after write, iclass 12, count 0 2006.285.14:49:49.00#ibcon#*before return 0, iclass 12, count 0 2006.285.14:49:49.00#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:49:49.00#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.14:49:49.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.14:49:49.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.14:49:49.00$vck44/vblo=5,709.99 2006.285.14:49:49.00#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.14:49:49.00#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.14:49:49.00#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:49.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:49:49.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:49:49.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:49:49.00#ibcon#enter wrdev, iclass 14, count 0 2006.285.14:49:49.00#ibcon#first serial, iclass 14, count 0 2006.285.14:49:49.00#ibcon#enter sib2, iclass 14, count 0 2006.285.14:49:49.00#ibcon#flushed, iclass 14, count 0 2006.285.14:49:49.00#ibcon#about to write, iclass 14, count 0 2006.285.14:49:49.00#ibcon#wrote, iclass 14, count 0 2006.285.14:49:49.00#ibcon#about to read 3, iclass 14, count 0 2006.285.14:49:49.02#ibcon#read 3, iclass 14, count 0 2006.285.14:49:49.02#ibcon#about to read 4, iclass 14, count 0 2006.285.14:49:49.02#ibcon#read 4, iclass 14, count 0 2006.285.14:49:49.02#ibcon#about to read 5, iclass 14, count 0 2006.285.14:49:49.02#ibcon#read 5, iclass 14, count 0 2006.285.14:49:49.02#ibcon#about to read 6, iclass 14, count 0 2006.285.14:49:49.02#ibcon#read 6, iclass 14, count 0 2006.285.14:49:49.02#ibcon#end of sib2, iclass 14, count 0 2006.285.14:49:49.02#ibcon#*mode == 0, iclass 14, count 0 2006.285.14:49:49.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.14:49:49.02#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.14:49:49.02#ibcon#*before write, iclass 14, count 0 2006.285.14:49:49.02#ibcon#enter sib2, iclass 14, count 0 2006.285.14:49:49.02#ibcon#flushed, iclass 14, count 0 2006.285.14:49:49.02#ibcon#about to write, iclass 14, count 0 2006.285.14:49:49.02#ibcon#wrote, iclass 14, count 0 2006.285.14:49:49.02#ibcon#about to read 3, iclass 14, count 0 2006.285.14:49:49.06#ibcon#read 3, iclass 14, count 0 2006.285.14:49:49.06#ibcon#about to read 4, iclass 14, count 0 2006.285.14:49:49.06#ibcon#read 4, iclass 14, count 0 2006.285.14:49:49.06#ibcon#about to read 5, iclass 14, count 0 2006.285.14:49:49.06#ibcon#read 5, iclass 14, count 0 2006.285.14:49:49.06#ibcon#about to read 6, iclass 14, count 0 2006.285.14:49:49.06#ibcon#read 6, iclass 14, count 0 2006.285.14:49:49.06#ibcon#end of sib2, iclass 14, count 0 2006.285.14:49:49.06#ibcon#*after write, iclass 14, count 0 2006.285.14:49:49.06#ibcon#*before return 0, iclass 14, count 0 2006.285.14:49:49.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:49:49.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.14:49:49.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.14:49:49.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.14:49:49.06$vck44/vb=5,4 2006.285.14:49:49.06#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.14:49:49.06#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.14:49:49.06#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:49.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:49:49.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:49:49.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:49:49.12#ibcon#enter wrdev, iclass 16, count 2 2006.285.14:49:49.12#ibcon#first serial, iclass 16, count 2 2006.285.14:49:49.12#ibcon#enter sib2, iclass 16, count 2 2006.285.14:49:49.12#ibcon#flushed, iclass 16, count 2 2006.285.14:49:49.12#ibcon#about to write, iclass 16, count 2 2006.285.14:49:49.12#ibcon#wrote, iclass 16, count 2 2006.285.14:49:49.12#ibcon#about to read 3, iclass 16, count 2 2006.285.14:49:49.14#ibcon#read 3, iclass 16, count 2 2006.285.14:49:49.14#ibcon#about to read 4, iclass 16, count 2 2006.285.14:49:49.14#ibcon#read 4, iclass 16, count 2 2006.285.14:49:49.14#ibcon#about to read 5, iclass 16, count 2 2006.285.14:49:49.14#ibcon#read 5, iclass 16, count 2 2006.285.14:49:49.14#ibcon#about to read 6, iclass 16, count 2 2006.285.14:49:49.14#ibcon#read 6, iclass 16, count 2 2006.285.14:49:49.14#ibcon#end of sib2, iclass 16, count 2 2006.285.14:49:49.14#ibcon#*mode == 0, iclass 16, count 2 2006.285.14:49:49.14#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.14:49:49.14#ibcon#[27=AT05-04\r\n] 2006.285.14:49:49.14#ibcon#*before write, iclass 16, count 2 2006.285.14:49:49.14#ibcon#enter sib2, iclass 16, count 2 2006.285.14:49:49.14#ibcon#flushed, iclass 16, count 2 2006.285.14:49:49.14#ibcon#about to write, iclass 16, count 2 2006.285.14:49:49.14#ibcon#wrote, iclass 16, count 2 2006.285.14:49:49.14#ibcon#about to read 3, iclass 16, count 2 2006.285.14:49:49.17#ibcon#read 3, iclass 16, count 2 2006.285.14:49:49.17#ibcon#about to read 4, iclass 16, count 2 2006.285.14:49:49.17#ibcon#read 4, iclass 16, count 2 2006.285.14:49:49.17#ibcon#about to read 5, iclass 16, count 2 2006.285.14:49:49.17#ibcon#read 5, iclass 16, count 2 2006.285.14:49:49.17#ibcon#about to read 6, iclass 16, count 2 2006.285.14:49:49.17#ibcon#read 6, iclass 16, count 2 2006.285.14:49:49.17#ibcon#end of sib2, iclass 16, count 2 2006.285.14:49:49.17#ibcon#*after write, iclass 16, count 2 2006.285.14:49:49.17#ibcon#*before return 0, iclass 16, count 2 2006.285.14:49:49.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:49:49.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.14:49:49.17#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.14:49:49.17#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:49.17#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:49:49.29#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:49:49.29#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:49:49.29#ibcon#enter wrdev, iclass 16, count 0 2006.285.14:49:49.29#ibcon#first serial, iclass 16, count 0 2006.285.14:49:49.29#ibcon#enter sib2, iclass 16, count 0 2006.285.14:49:49.29#ibcon#flushed, iclass 16, count 0 2006.285.14:49:49.29#ibcon#about to write, iclass 16, count 0 2006.285.14:49:49.29#ibcon#wrote, iclass 16, count 0 2006.285.14:49:49.29#ibcon#about to read 3, iclass 16, count 0 2006.285.14:49:49.31#ibcon#read 3, iclass 16, count 0 2006.285.14:49:49.31#ibcon#about to read 4, iclass 16, count 0 2006.285.14:49:49.31#ibcon#read 4, iclass 16, count 0 2006.285.14:49:49.31#ibcon#about to read 5, iclass 16, count 0 2006.285.14:49:49.31#ibcon#read 5, iclass 16, count 0 2006.285.14:49:49.31#ibcon#about to read 6, iclass 16, count 0 2006.285.14:49:49.31#ibcon#read 6, iclass 16, count 0 2006.285.14:49:49.31#ibcon#end of sib2, iclass 16, count 0 2006.285.14:49:49.31#ibcon#*mode == 0, iclass 16, count 0 2006.285.14:49:49.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.14:49:49.31#ibcon#[27=USB\r\n] 2006.285.14:49:49.31#ibcon#*before write, iclass 16, count 0 2006.285.14:49:49.31#ibcon#enter sib2, iclass 16, count 0 2006.285.14:49:49.31#ibcon#flushed, iclass 16, count 0 2006.285.14:49:49.31#ibcon#about to write, iclass 16, count 0 2006.285.14:49:49.31#ibcon#wrote, iclass 16, count 0 2006.285.14:49:49.31#ibcon#about to read 3, iclass 16, count 0 2006.285.14:49:49.34#ibcon#read 3, iclass 16, count 0 2006.285.14:49:49.34#ibcon#about to read 4, iclass 16, count 0 2006.285.14:49:49.34#ibcon#read 4, iclass 16, count 0 2006.285.14:49:49.34#ibcon#about to read 5, iclass 16, count 0 2006.285.14:49:49.34#ibcon#read 5, iclass 16, count 0 2006.285.14:49:49.34#ibcon#about to read 6, iclass 16, count 0 2006.285.14:49:49.34#ibcon#read 6, iclass 16, count 0 2006.285.14:49:49.34#ibcon#end of sib2, iclass 16, count 0 2006.285.14:49:49.34#ibcon#*after write, iclass 16, count 0 2006.285.14:49:49.34#ibcon#*before return 0, iclass 16, count 0 2006.285.14:49:49.34#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:49:49.34#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.14:49:49.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.14:49:49.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.14:49:49.34$vck44/vblo=6,719.99 2006.285.14:49:49.34#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.14:49:49.34#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.14:49:49.34#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:49.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:49:49.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:49:49.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:49:49.34#ibcon#enter wrdev, iclass 18, count 0 2006.285.14:49:49.34#ibcon#first serial, iclass 18, count 0 2006.285.14:49:49.34#ibcon#enter sib2, iclass 18, count 0 2006.285.14:49:49.34#ibcon#flushed, iclass 18, count 0 2006.285.14:49:49.34#ibcon#about to write, iclass 18, count 0 2006.285.14:49:49.34#ibcon#wrote, iclass 18, count 0 2006.285.14:49:49.34#ibcon#about to read 3, iclass 18, count 0 2006.285.14:49:49.36#ibcon#read 3, iclass 18, count 0 2006.285.14:49:49.36#ibcon#about to read 4, iclass 18, count 0 2006.285.14:49:49.36#ibcon#read 4, iclass 18, count 0 2006.285.14:49:49.36#ibcon#about to read 5, iclass 18, count 0 2006.285.14:49:49.36#ibcon#read 5, iclass 18, count 0 2006.285.14:49:49.36#ibcon#about to read 6, iclass 18, count 0 2006.285.14:49:49.36#ibcon#read 6, iclass 18, count 0 2006.285.14:49:49.36#ibcon#end of sib2, iclass 18, count 0 2006.285.14:49:49.36#ibcon#*mode == 0, iclass 18, count 0 2006.285.14:49:49.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.14:49:49.36#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.14:49:49.36#ibcon#*before write, iclass 18, count 0 2006.285.14:49:49.36#ibcon#enter sib2, iclass 18, count 0 2006.285.14:49:49.36#ibcon#flushed, iclass 18, count 0 2006.285.14:49:49.36#ibcon#about to write, iclass 18, count 0 2006.285.14:49:49.36#ibcon#wrote, iclass 18, count 0 2006.285.14:49:49.36#ibcon#about to read 3, iclass 18, count 0 2006.285.14:49:49.40#ibcon#read 3, iclass 18, count 0 2006.285.14:49:49.40#ibcon#about to read 4, iclass 18, count 0 2006.285.14:49:49.40#ibcon#read 4, iclass 18, count 0 2006.285.14:49:49.40#ibcon#about to read 5, iclass 18, count 0 2006.285.14:49:49.40#ibcon#read 5, iclass 18, count 0 2006.285.14:49:49.40#ibcon#about to read 6, iclass 18, count 0 2006.285.14:49:49.40#ibcon#read 6, iclass 18, count 0 2006.285.14:49:49.40#ibcon#end of sib2, iclass 18, count 0 2006.285.14:49:49.40#ibcon#*after write, iclass 18, count 0 2006.285.14:49:49.40#ibcon#*before return 0, iclass 18, count 0 2006.285.14:49:49.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:49:49.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.14:49:49.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.14:49:49.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.14:49:49.40$vck44/vb=6,3 2006.285.14:49:49.40#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.14:49:49.40#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.14:49:49.40#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:49.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:49:49.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:49:49.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:49:49.46#ibcon#enter wrdev, iclass 20, count 2 2006.285.14:49:49.46#ibcon#first serial, iclass 20, count 2 2006.285.14:49:49.46#ibcon#enter sib2, iclass 20, count 2 2006.285.14:49:49.46#ibcon#flushed, iclass 20, count 2 2006.285.14:49:49.46#ibcon#about to write, iclass 20, count 2 2006.285.14:49:49.46#ibcon#wrote, iclass 20, count 2 2006.285.14:49:49.46#ibcon#about to read 3, iclass 20, count 2 2006.285.14:49:49.48#ibcon#read 3, iclass 20, count 2 2006.285.14:49:49.48#ibcon#about to read 4, iclass 20, count 2 2006.285.14:49:49.48#ibcon#read 4, iclass 20, count 2 2006.285.14:49:49.48#ibcon#about to read 5, iclass 20, count 2 2006.285.14:49:49.48#ibcon#read 5, iclass 20, count 2 2006.285.14:49:49.48#ibcon#about to read 6, iclass 20, count 2 2006.285.14:49:49.48#ibcon#read 6, iclass 20, count 2 2006.285.14:49:49.48#ibcon#end of sib2, iclass 20, count 2 2006.285.14:49:49.48#ibcon#*mode == 0, iclass 20, count 2 2006.285.14:49:49.48#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.14:49:49.48#ibcon#[27=AT06-03\r\n] 2006.285.14:49:49.48#ibcon#*before write, iclass 20, count 2 2006.285.14:49:49.48#ibcon#enter sib2, iclass 20, count 2 2006.285.14:49:49.48#ibcon#flushed, iclass 20, count 2 2006.285.14:49:49.48#ibcon#about to write, iclass 20, count 2 2006.285.14:49:49.48#ibcon#wrote, iclass 20, count 2 2006.285.14:49:49.48#ibcon#about to read 3, iclass 20, count 2 2006.285.14:49:49.51#ibcon#read 3, iclass 20, count 2 2006.285.14:49:49.51#ibcon#about to read 4, iclass 20, count 2 2006.285.14:49:49.51#ibcon#read 4, iclass 20, count 2 2006.285.14:49:49.51#ibcon#about to read 5, iclass 20, count 2 2006.285.14:49:49.51#ibcon#read 5, iclass 20, count 2 2006.285.14:49:49.51#ibcon#about to read 6, iclass 20, count 2 2006.285.14:49:49.51#ibcon#read 6, iclass 20, count 2 2006.285.14:49:49.51#ibcon#end of sib2, iclass 20, count 2 2006.285.14:49:49.51#ibcon#*after write, iclass 20, count 2 2006.285.14:49:49.51#ibcon#*before return 0, iclass 20, count 2 2006.285.14:49:49.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:49:49.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.14:49:49.51#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.14:49:49.51#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:49.51#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:49:49.63#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:49:49.63#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:49:49.63#ibcon#enter wrdev, iclass 20, count 0 2006.285.14:49:49.63#ibcon#first serial, iclass 20, count 0 2006.285.14:49:49.63#ibcon#enter sib2, iclass 20, count 0 2006.285.14:49:49.63#ibcon#flushed, iclass 20, count 0 2006.285.14:49:49.63#ibcon#about to write, iclass 20, count 0 2006.285.14:49:49.63#ibcon#wrote, iclass 20, count 0 2006.285.14:49:49.63#ibcon#about to read 3, iclass 20, count 0 2006.285.14:49:49.65#ibcon#read 3, iclass 20, count 0 2006.285.14:49:49.65#ibcon#about to read 4, iclass 20, count 0 2006.285.14:49:49.65#ibcon#read 4, iclass 20, count 0 2006.285.14:49:49.65#ibcon#about to read 5, iclass 20, count 0 2006.285.14:49:49.65#ibcon#read 5, iclass 20, count 0 2006.285.14:49:49.65#ibcon#about to read 6, iclass 20, count 0 2006.285.14:49:49.65#ibcon#read 6, iclass 20, count 0 2006.285.14:49:49.65#ibcon#end of sib2, iclass 20, count 0 2006.285.14:49:49.65#ibcon#*mode == 0, iclass 20, count 0 2006.285.14:49:49.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.14:49:49.65#ibcon#[27=USB\r\n] 2006.285.14:49:49.65#ibcon#*before write, iclass 20, count 0 2006.285.14:49:49.65#ibcon#enter sib2, iclass 20, count 0 2006.285.14:49:49.65#ibcon#flushed, iclass 20, count 0 2006.285.14:49:49.65#ibcon#about to write, iclass 20, count 0 2006.285.14:49:49.65#ibcon#wrote, iclass 20, count 0 2006.285.14:49:49.65#ibcon#about to read 3, iclass 20, count 0 2006.285.14:49:49.68#ibcon#read 3, iclass 20, count 0 2006.285.14:49:49.68#ibcon#about to read 4, iclass 20, count 0 2006.285.14:49:49.68#ibcon#read 4, iclass 20, count 0 2006.285.14:49:49.68#ibcon#about to read 5, iclass 20, count 0 2006.285.14:49:49.68#ibcon#read 5, iclass 20, count 0 2006.285.14:49:49.68#ibcon#about to read 6, iclass 20, count 0 2006.285.14:49:49.68#ibcon#read 6, iclass 20, count 0 2006.285.14:49:49.68#ibcon#end of sib2, iclass 20, count 0 2006.285.14:49:49.68#ibcon#*after write, iclass 20, count 0 2006.285.14:49:49.68#ibcon#*before return 0, iclass 20, count 0 2006.285.14:49:49.68#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:49:49.68#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.14:49:49.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.14:49:49.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.14:49:49.68$vck44/vblo=7,734.99 2006.285.14:49:49.68#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.14:49:49.68#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.14:49:49.68#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:49.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:49:49.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:49:49.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:49:49.68#ibcon#enter wrdev, iclass 22, count 0 2006.285.14:49:49.68#ibcon#first serial, iclass 22, count 0 2006.285.14:49:49.68#ibcon#enter sib2, iclass 22, count 0 2006.285.14:49:49.68#ibcon#flushed, iclass 22, count 0 2006.285.14:49:49.68#ibcon#about to write, iclass 22, count 0 2006.285.14:49:49.68#ibcon#wrote, iclass 22, count 0 2006.285.14:49:49.68#ibcon#about to read 3, iclass 22, count 0 2006.285.14:49:49.70#ibcon#read 3, iclass 22, count 0 2006.285.14:49:49.70#ibcon#about to read 4, iclass 22, count 0 2006.285.14:49:49.70#ibcon#read 4, iclass 22, count 0 2006.285.14:49:49.70#ibcon#about to read 5, iclass 22, count 0 2006.285.14:49:49.70#ibcon#read 5, iclass 22, count 0 2006.285.14:49:49.70#ibcon#about to read 6, iclass 22, count 0 2006.285.14:49:49.70#ibcon#read 6, iclass 22, count 0 2006.285.14:49:49.70#ibcon#end of sib2, iclass 22, count 0 2006.285.14:49:49.70#ibcon#*mode == 0, iclass 22, count 0 2006.285.14:49:49.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.14:49:49.70#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.14:49:49.70#ibcon#*before write, iclass 22, count 0 2006.285.14:49:49.70#ibcon#enter sib2, iclass 22, count 0 2006.285.14:49:49.70#ibcon#flushed, iclass 22, count 0 2006.285.14:49:49.70#ibcon#about to write, iclass 22, count 0 2006.285.14:49:49.70#ibcon#wrote, iclass 22, count 0 2006.285.14:49:49.70#ibcon#about to read 3, iclass 22, count 0 2006.285.14:49:49.74#ibcon#read 3, iclass 22, count 0 2006.285.14:49:49.74#ibcon#about to read 4, iclass 22, count 0 2006.285.14:49:49.74#ibcon#read 4, iclass 22, count 0 2006.285.14:49:49.74#ibcon#about to read 5, iclass 22, count 0 2006.285.14:49:49.74#ibcon#read 5, iclass 22, count 0 2006.285.14:49:49.74#ibcon#about to read 6, iclass 22, count 0 2006.285.14:49:49.74#ibcon#read 6, iclass 22, count 0 2006.285.14:49:49.74#ibcon#end of sib2, iclass 22, count 0 2006.285.14:49:49.74#ibcon#*after write, iclass 22, count 0 2006.285.14:49:49.74#ibcon#*before return 0, iclass 22, count 0 2006.285.14:49:49.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:49:49.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:49:49.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.14:49:49.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.14:49:49.74$vck44/vb=7,4 2006.285.14:49:49.74#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.14:49:49.74#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.14:49:49.74#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:49.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:49:49.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:49:49.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:49:49.80#ibcon#enter wrdev, iclass 24, count 2 2006.285.14:49:49.80#ibcon#first serial, iclass 24, count 2 2006.285.14:49:49.80#ibcon#enter sib2, iclass 24, count 2 2006.285.14:49:49.80#ibcon#flushed, iclass 24, count 2 2006.285.14:49:49.80#ibcon#about to write, iclass 24, count 2 2006.285.14:49:49.80#ibcon#wrote, iclass 24, count 2 2006.285.14:49:49.80#ibcon#about to read 3, iclass 24, count 2 2006.285.14:49:49.82#ibcon#read 3, iclass 24, count 2 2006.285.14:49:49.82#ibcon#about to read 4, iclass 24, count 2 2006.285.14:49:49.82#ibcon#read 4, iclass 24, count 2 2006.285.14:49:49.82#ibcon#about to read 5, iclass 24, count 2 2006.285.14:49:49.82#ibcon#read 5, iclass 24, count 2 2006.285.14:49:49.82#ibcon#about to read 6, iclass 24, count 2 2006.285.14:49:49.82#ibcon#read 6, iclass 24, count 2 2006.285.14:49:49.82#ibcon#end of sib2, iclass 24, count 2 2006.285.14:49:49.82#ibcon#*mode == 0, iclass 24, count 2 2006.285.14:49:49.82#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.14:49:49.82#ibcon#[27=AT07-04\r\n] 2006.285.14:49:49.82#ibcon#*before write, iclass 24, count 2 2006.285.14:49:49.82#ibcon#enter sib2, iclass 24, count 2 2006.285.14:49:49.82#ibcon#flushed, iclass 24, count 2 2006.285.14:49:49.82#ibcon#about to write, iclass 24, count 2 2006.285.14:49:49.82#ibcon#wrote, iclass 24, count 2 2006.285.14:49:49.82#ibcon#about to read 3, iclass 24, count 2 2006.285.14:49:49.85#ibcon#read 3, iclass 24, count 2 2006.285.14:49:49.85#ibcon#about to read 4, iclass 24, count 2 2006.285.14:49:49.85#ibcon#read 4, iclass 24, count 2 2006.285.14:49:49.85#ibcon#about to read 5, iclass 24, count 2 2006.285.14:49:49.85#ibcon#read 5, iclass 24, count 2 2006.285.14:49:49.85#ibcon#about to read 6, iclass 24, count 2 2006.285.14:49:49.85#ibcon#read 6, iclass 24, count 2 2006.285.14:49:49.85#ibcon#end of sib2, iclass 24, count 2 2006.285.14:49:49.85#ibcon#*after write, iclass 24, count 2 2006.285.14:49:49.85#ibcon#*before return 0, iclass 24, count 2 2006.285.14:49:49.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:49:49.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.14:49:49.85#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.14:49:49.85#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:49.85#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:49:49.97#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:49:49.97#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:49:49.97#ibcon#enter wrdev, iclass 24, count 0 2006.285.14:49:49.97#ibcon#first serial, iclass 24, count 0 2006.285.14:49:49.97#ibcon#enter sib2, iclass 24, count 0 2006.285.14:49:49.97#ibcon#flushed, iclass 24, count 0 2006.285.14:49:49.97#ibcon#about to write, iclass 24, count 0 2006.285.14:49:49.97#ibcon#wrote, iclass 24, count 0 2006.285.14:49:49.97#ibcon#about to read 3, iclass 24, count 0 2006.285.14:49:49.99#ibcon#read 3, iclass 24, count 0 2006.285.14:49:49.99#ibcon#about to read 4, iclass 24, count 0 2006.285.14:49:49.99#ibcon#read 4, iclass 24, count 0 2006.285.14:49:49.99#ibcon#about to read 5, iclass 24, count 0 2006.285.14:49:49.99#ibcon#read 5, iclass 24, count 0 2006.285.14:49:49.99#ibcon#about to read 6, iclass 24, count 0 2006.285.14:49:49.99#ibcon#read 6, iclass 24, count 0 2006.285.14:49:49.99#ibcon#end of sib2, iclass 24, count 0 2006.285.14:49:49.99#ibcon#*mode == 0, iclass 24, count 0 2006.285.14:49:49.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.14:49:49.99#ibcon#[27=USB\r\n] 2006.285.14:49:49.99#ibcon#*before write, iclass 24, count 0 2006.285.14:49:49.99#ibcon#enter sib2, iclass 24, count 0 2006.285.14:49:49.99#ibcon#flushed, iclass 24, count 0 2006.285.14:49:49.99#ibcon#about to write, iclass 24, count 0 2006.285.14:49:49.99#ibcon#wrote, iclass 24, count 0 2006.285.14:49:49.99#ibcon#about to read 3, iclass 24, count 0 2006.285.14:49:50.02#ibcon#read 3, iclass 24, count 0 2006.285.14:49:50.02#ibcon#about to read 4, iclass 24, count 0 2006.285.14:49:50.02#ibcon#read 4, iclass 24, count 0 2006.285.14:49:50.02#ibcon#about to read 5, iclass 24, count 0 2006.285.14:49:50.02#ibcon#read 5, iclass 24, count 0 2006.285.14:49:50.02#ibcon#about to read 6, iclass 24, count 0 2006.285.14:49:50.02#ibcon#read 6, iclass 24, count 0 2006.285.14:49:50.02#ibcon#end of sib2, iclass 24, count 0 2006.285.14:49:50.02#ibcon#*after write, iclass 24, count 0 2006.285.14:49:50.02#ibcon#*before return 0, iclass 24, count 0 2006.285.14:49:50.02#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:49:50.02#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.14:49:50.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.14:49:50.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.14:49:50.02$vck44/vblo=8,744.99 2006.285.14:49:50.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.14:49:50.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.14:49:50.02#ibcon#ireg 17 cls_cnt 0 2006.285.14:49:50.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:49:50.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:49:50.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:49:50.02#ibcon#enter wrdev, iclass 26, count 0 2006.285.14:49:50.02#ibcon#first serial, iclass 26, count 0 2006.285.14:49:50.02#ibcon#enter sib2, iclass 26, count 0 2006.285.14:49:50.02#ibcon#flushed, iclass 26, count 0 2006.285.14:49:50.02#ibcon#about to write, iclass 26, count 0 2006.285.14:49:50.02#ibcon#wrote, iclass 26, count 0 2006.285.14:49:50.02#ibcon#about to read 3, iclass 26, count 0 2006.285.14:49:50.04#ibcon#read 3, iclass 26, count 0 2006.285.14:49:50.04#ibcon#about to read 4, iclass 26, count 0 2006.285.14:49:50.04#ibcon#read 4, iclass 26, count 0 2006.285.14:49:50.04#ibcon#about to read 5, iclass 26, count 0 2006.285.14:49:50.04#ibcon#read 5, iclass 26, count 0 2006.285.14:49:50.04#ibcon#about to read 6, iclass 26, count 0 2006.285.14:49:50.04#ibcon#read 6, iclass 26, count 0 2006.285.14:49:50.04#ibcon#end of sib2, iclass 26, count 0 2006.285.14:49:50.04#ibcon#*mode == 0, iclass 26, count 0 2006.285.14:49:50.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.14:49:50.04#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.14:49:50.04#ibcon#*before write, iclass 26, count 0 2006.285.14:49:50.04#ibcon#enter sib2, iclass 26, count 0 2006.285.14:49:50.04#ibcon#flushed, iclass 26, count 0 2006.285.14:49:50.04#ibcon#about to write, iclass 26, count 0 2006.285.14:49:50.04#ibcon#wrote, iclass 26, count 0 2006.285.14:49:50.04#ibcon#about to read 3, iclass 26, count 0 2006.285.14:49:50.08#ibcon#read 3, iclass 26, count 0 2006.285.14:49:50.08#ibcon#about to read 4, iclass 26, count 0 2006.285.14:49:50.08#ibcon#read 4, iclass 26, count 0 2006.285.14:49:50.08#ibcon#about to read 5, iclass 26, count 0 2006.285.14:49:50.08#ibcon#read 5, iclass 26, count 0 2006.285.14:49:50.08#ibcon#about to read 6, iclass 26, count 0 2006.285.14:49:50.08#ibcon#read 6, iclass 26, count 0 2006.285.14:49:50.08#ibcon#end of sib2, iclass 26, count 0 2006.285.14:49:50.08#ibcon#*after write, iclass 26, count 0 2006.285.14:49:50.08#ibcon#*before return 0, iclass 26, count 0 2006.285.14:49:50.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:49:50.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.14:49:50.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.14:49:50.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.14:49:50.08$vck44/vb=8,4 2006.285.14:49:50.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.14:49:50.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.14:49:50.08#ibcon#ireg 11 cls_cnt 2 2006.285.14:49:50.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:49:50.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:49:50.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:49:50.14#ibcon#enter wrdev, iclass 28, count 2 2006.285.14:49:50.14#ibcon#first serial, iclass 28, count 2 2006.285.14:49:50.14#ibcon#enter sib2, iclass 28, count 2 2006.285.14:49:50.14#ibcon#flushed, iclass 28, count 2 2006.285.14:49:50.14#ibcon#about to write, iclass 28, count 2 2006.285.14:49:50.14#ibcon#wrote, iclass 28, count 2 2006.285.14:49:50.14#ibcon#about to read 3, iclass 28, count 2 2006.285.14:49:50.16#ibcon#read 3, iclass 28, count 2 2006.285.14:49:50.16#ibcon#about to read 4, iclass 28, count 2 2006.285.14:49:50.16#ibcon#read 4, iclass 28, count 2 2006.285.14:49:50.16#ibcon#about to read 5, iclass 28, count 2 2006.285.14:49:50.16#ibcon#read 5, iclass 28, count 2 2006.285.14:49:50.16#ibcon#about to read 6, iclass 28, count 2 2006.285.14:49:50.16#ibcon#read 6, iclass 28, count 2 2006.285.14:49:50.16#ibcon#end of sib2, iclass 28, count 2 2006.285.14:49:50.16#ibcon#*mode == 0, iclass 28, count 2 2006.285.14:49:50.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.14:49:50.16#ibcon#[27=AT08-04\r\n] 2006.285.14:49:50.16#ibcon#*before write, iclass 28, count 2 2006.285.14:49:50.16#ibcon#enter sib2, iclass 28, count 2 2006.285.14:49:50.16#ibcon#flushed, iclass 28, count 2 2006.285.14:49:50.16#ibcon#about to write, iclass 28, count 2 2006.285.14:49:50.16#ibcon#wrote, iclass 28, count 2 2006.285.14:49:50.16#ibcon#about to read 3, iclass 28, count 2 2006.285.14:49:50.19#ibcon#read 3, iclass 28, count 2 2006.285.14:49:50.19#ibcon#about to read 4, iclass 28, count 2 2006.285.14:49:50.19#ibcon#read 4, iclass 28, count 2 2006.285.14:49:50.19#ibcon#about to read 5, iclass 28, count 2 2006.285.14:49:50.19#ibcon#read 5, iclass 28, count 2 2006.285.14:49:50.19#ibcon#about to read 6, iclass 28, count 2 2006.285.14:49:50.19#ibcon#read 6, iclass 28, count 2 2006.285.14:49:50.19#ibcon#end of sib2, iclass 28, count 2 2006.285.14:49:50.19#ibcon#*after write, iclass 28, count 2 2006.285.14:49:50.19#ibcon#*before return 0, iclass 28, count 2 2006.285.14:49:50.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:49:50.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.14:49:50.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.14:49:50.19#ibcon#ireg 7 cls_cnt 0 2006.285.14:49:50.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:49:50.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:49:50.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:49:50.31#ibcon#enter wrdev, iclass 28, count 0 2006.285.14:49:50.31#ibcon#first serial, iclass 28, count 0 2006.285.14:49:50.31#ibcon#enter sib2, iclass 28, count 0 2006.285.14:49:50.31#ibcon#flushed, iclass 28, count 0 2006.285.14:49:50.31#ibcon#about to write, iclass 28, count 0 2006.285.14:49:50.31#ibcon#wrote, iclass 28, count 0 2006.285.14:49:50.31#ibcon#about to read 3, iclass 28, count 0 2006.285.14:49:50.33#ibcon#read 3, iclass 28, count 0 2006.285.14:49:50.33#ibcon#about to read 4, iclass 28, count 0 2006.285.14:49:50.33#ibcon#read 4, iclass 28, count 0 2006.285.14:49:50.33#ibcon#about to read 5, iclass 28, count 0 2006.285.14:49:50.33#ibcon#read 5, iclass 28, count 0 2006.285.14:49:50.33#ibcon#about to read 6, iclass 28, count 0 2006.285.14:49:50.33#ibcon#read 6, iclass 28, count 0 2006.285.14:49:50.33#ibcon#end of sib2, iclass 28, count 0 2006.285.14:49:50.33#ibcon#*mode == 0, iclass 28, count 0 2006.285.14:49:50.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.14:49:50.33#ibcon#[27=USB\r\n] 2006.285.14:49:50.33#ibcon#*before write, iclass 28, count 0 2006.285.14:49:50.33#ibcon#enter sib2, iclass 28, count 0 2006.285.14:49:50.33#ibcon#flushed, iclass 28, count 0 2006.285.14:49:50.33#ibcon#about to write, iclass 28, count 0 2006.285.14:49:50.33#ibcon#wrote, iclass 28, count 0 2006.285.14:49:50.33#ibcon#about to read 3, iclass 28, count 0 2006.285.14:49:50.36#ibcon#read 3, iclass 28, count 0 2006.285.14:49:50.36#ibcon#about to read 4, iclass 28, count 0 2006.285.14:49:50.36#ibcon#read 4, iclass 28, count 0 2006.285.14:49:50.36#ibcon#about to read 5, iclass 28, count 0 2006.285.14:49:50.36#ibcon#read 5, iclass 28, count 0 2006.285.14:49:50.36#ibcon#about to read 6, iclass 28, count 0 2006.285.14:49:50.36#ibcon#read 6, iclass 28, count 0 2006.285.14:49:50.36#ibcon#end of sib2, iclass 28, count 0 2006.285.14:49:50.36#ibcon#*after write, iclass 28, count 0 2006.285.14:49:50.36#ibcon#*before return 0, iclass 28, count 0 2006.285.14:49:50.36#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:49:50.36#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.14:49:50.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.14:49:50.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.14:49:50.36$vck44/vabw=wide 2006.285.14:49:50.36#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.14:49:50.36#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.14:49:50.36#ibcon#ireg 8 cls_cnt 0 2006.285.14:49:50.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:49:50.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:49:50.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:49:50.36#ibcon#enter wrdev, iclass 30, count 0 2006.285.14:49:50.36#ibcon#first serial, iclass 30, count 0 2006.285.14:49:50.36#ibcon#enter sib2, iclass 30, count 0 2006.285.14:49:50.36#ibcon#flushed, iclass 30, count 0 2006.285.14:49:50.36#ibcon#about to write, iclass 30, count 0 2006.285.14:49:50.36#ibcon#wrote, iclass 30, count 0 2006.285.14:49:50.36#ibcon#about to read 3, iclass 30, count 0 2006.285.14:49:50.38#ibcon#read 3, iclass 30, count 0 2006.285.14:49:50.38#ibcon#about to read 4, iclass 30, count 0 2006.285.14:49:50.38#ibcon#read 4, iclass 30, count 0 2006.285.14:49:50.38#ibcon#about to read 5, iclass 30, count 0 2006.285.14:49:50.38#ibcon#read 5, iclass 30, count 0 2006.285.14:49:50.38#ibcon#about to read 6, iclass 30, count 0 2006.285.14:49:50.38#ibcon#read 6, iclass 30, count 0 2006.285.14:49:50.38#ibcon#end of sib2, iclass 30, count 0 2006.285.14:49:50.38#ibcon#*mode == 0, iclass 30, count 0 2006.285.14:49:50.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.14:49:50.38#ibcon#[25=BW32\r\n] 2006.285.14:49:50.38#ibcon#*before write, iclass 30, count 0 2006.285.14:49:50.38#ibcon#enter sib2, iclass 30, count 0 2006.285.14:49:50.38#ibcon#flushed, iclass 30, count 0 2006.285.14:49:50.38#ibcon#about to write, iclass 30, count 0 2006.285.14:49:50.38#ibcon#wrote, iclass 30, count 0 2006.285.14:49:50.38#ibcon#about to read 3, iclass 30, count 0 2006.285.14:49:50.41#ibcon#read 3, iclass 30, count 0 2006.285.14:49:50.41#ibcon#about to read 4, iclass 30, count 0 2006.285.14:49:50.41#ibcon#read 4, iclass 30, count 0 2006.285.14:49:50.41#ibcon#about to read 5, iclass 30, count 0 2006.285.14:49:50.41#ibcon#read 5, iclass 30, count 0 2006.285.14:49:50.41#ibcon#about to read 6, iclass 30, count 0 2006.285.14:49:50.41#ibcon#read 6, iclass 30, count 0 2006.285.14:49:50.41#ibcon#end of sib2, iclass 30, count 0 2006.285.14:49:50.41#ibcon#*after write, iclass 30, count 0 2006.285.14:49:50.41#ibcon#*before return 0, iclass 30, count 0 2006.285.14:49:50.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:49:50.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.14:49:50.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.14:49:50.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.14:49:50.41$vck44/vbbw=wide 2006.285.14:49:50.41#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.14:49:50.41#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.14:49:50.41#ibcon#ireg 8 cls_cnt 0 2006.285.14:49:50.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:49:50.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:49:50.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:49:50.48#ibcon#enter wrdev, iclass 32, count 0 2006.285.14:49:50.48#ibcon#first serial, iclass 32, count 0 2006.285.14:49:50.48#ibcon#enter sib2, iclass 32, count 0 2006.285.14:49:50.48#ibcon#flushed, iclass 32, count 0 2006.285.14:49:50.48#ibcon#about to write, iclass 32, count 0 2006.285.14:49:50.48#ibcon#wrote, iclass 32, count 0 2006.285.14:49:50.48#ibcon#about to read 3, iclass 32, count 0 2006.285.14:49:50.50#ibcon#read 3, iclass 32, count 0 2006.285.14:49:50.50#ibcon#about to read 4, iclass 32, count 0 2006.285.14:49:50.50#ibcon#read 4, iclass 32, count 0 2006.285.14:49:50.50#ibcon#about to read 5, iclass 32, count 0 2006.285.14:49:50.50#ibcon#read 5, iclass 32, count 0 2006.285.14:49:50.50#ibcon#about to read 6, iclass 32, count 0 2006.285.14:49:50.50#ibcon#read 6, iclass 32, count 0 2006.285.14:49:50.50#ibcon#end of sib2, iclass 32, count 0 2006.285.14:49:50.50#ibcon#*mode == 0, iclass 32, count 0 2006.285.14:49:50.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.14:49:50.50#ibcon#[27=BW32\r\n] 2006.285.14:49:50.50#ibcon#*before write, iclass 32, count 0 2006.285.14:49:50.50#ibcon#enter sib2, iclass 32, count 0 2006.285.14:49:50.50#ibcon#flushed, iclass 32, count 0 2006.285.14:49:50.50#ibcon#about to write, iclass 32, count 0 2006.285.14:49:50.50#ibcon#wrote, iclass 32, count 0 2006.285.14:49:50.50#ibcon#about to read 3, iclass 32, count 0 2006.285.14:49:50.53#ibcon#read 3, iclass 32, count 0 2006.285.14:49:50.53#ibcon#about to read 4, iclass 32, count 0 2006.285.14:49:50.53#ibcon#read 4, iclass 32, count 0 2006.285.14:49:50.53#ibcon#about to read 5, iclass 32, count 0 2006.285.14:49:50.53#ibcon#read 5, iclass 32, count 0 2006.285.14:49:50.53#ibcon#about to read 6, iclass 32, count 0 2006.285.14:49:50.53#ibcon#read 6, iclass 32, count 0 2006.285.14:49:50.53#ibcon#end of sib2, iclass 32, count 0 2006.285.14:49:50.53#ibcon#*after write, iclass 32, count 0 2006.285.14:49:50.53#ibcon#*before return 0, iclass 32, count 0 2006.285.14:49:50.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:49:50.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.14:49:50.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.14:49:50.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.14:49:50.53$setupk4/ifdk4 2006.285.14:49:50.53$ifdk4/lo= 2006.285.14:49:50.53$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.14:49:50.53$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.14:49:50.65$ifdk4/patch= 2006.285.14:49:50.65$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.14:49:50.65$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.14:49:50.65$setupk4/!*+20s 2006.285.14:49:57.14#trakl#Source acquired 2006.285.14:49:57.14#flagr#flagr/antenna,acquired 2006.285.14:49:58.16#abcon#<5=/03 2.0 5.0 19.15 931015.0\r\n> 2006.285.14:49:58.18#abcon#{5=INTERFACE CLEAR} 2006.285.14:49:58.24#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:50:04.56$setupk4/"tpicd 2006.285.14:50:04.56$setupk4/echo=off 2006.285.14:50:04.56$setupk4/xlog=off 2006.285.14:50:04.56:!2006.285.14:52:19 2006.285.14:52:19.00:preob 2006.285.14:52:19.14/onsource/TRACKING 2006.285.14:52:19.14:!2006.285.14:52:29 2006.285.14:52:29.00:"tape 2006.285.14:52:29.00:"st=record 2006.285.14:52:29.00:data_valid=on 2006.285.14:52:29.00:midob 2006.285.14:52:30.14/onsource/TRACKING 2006.285.14:52:30.14/wx/19.16,1015.0,93 2006.285.14:52:30.30/cable/+6.4981E-03 2006.285.14:52:31.39/va/01,07,usb,yes,32,35 2006.285.14:52:31.39/va/02,06,usb,yes,33,33 2006.285.14:52:31.39/va/03,07,usb,yes,32,34 2006.285.14:52:31.39/va/04,06,usb,yes,34,35 2006.285.14:52:31.39/va/05,03,usb,yes,33,33 2006.285.14:52:31.39/va/06,04,usb,yes,30,29 2006.285.14:52:31.39/va/07,04,usb,yes,30,31 2006.285.14:52:31.39/va/08,03,usb,yes,31,38 2006.285.14:52:31.62/valo/01,524.99,yes,locked 2006.285.14:52:31.62/valo/02,534.99,yes,locked 2006.285.14:52:31.62/valo/03,564.99,yes,locked 2006.285.14:52:31.62/valo/04,624.99,yes,locked 2006.285.14:52:31.62/valo/05,734.99,yes,locked 2006.285.14:52:31.62/valo/06,814.99,yes,locked 2006.285.14:52:31.62/valo/07,864.99,yes,locked 2006.285.14:52:31.62/valo/08,884.99,yes,locked 2006.285.14:52:32.71/vb/01,04,usb,yes,30,28 2006.285.14:52:32.71/vb/02,05,usb,yes,29,28 2006.285.14:52:32.71/vb/03,04,usb,yes,30,33 2006.285.14:52:32.71/vb/04,05,usb,yes,30,29 2006.285.14:52:32.71/vb/05,04,usb,yes,26,29 2006.285.14:52:32.71/vb/06,03,usb,yes,38,34 2006.285.14:52:32.71/vb/07,04,usb,yes,30,30 2006.285.14:52:32.71/vb/08,04,usb,yes,28,31 2006.285.14:52:32.94/vblo/01,629.99,yes,locked 2006.285.14:52:32.94/vblo/02,634.99,yes,locked 2006.285.14:52:32.94/vblo/03,649.99,yes,locked 2006.285.14:52:32.94/vblo/04,679.99,yes,locked 2006.285.14:52:32.94/vblo/05,709.99,yes,locked 2006.285.14:52:32.94/vblo/06,719.99,yes,locked 2006.285.14:52:32.94/vblo/07,734.99,yes,locked 2006.285.14:52:32.94/vblo/08,744.99,yes,locked 2006.285.14:52:33.09/vabw/8 2006.285.14:52:33.24/vbbw/8 2006.285.14:52:33.33/xfe/off,on,12.0 2006.285.14:52:33.70/ifatt/23,28,28,28 2006.285.14:52:34.07/fmout-gps/S +2.72E-07 2006.285.14:52:34.09:!2006.285.14:54:19 2006.285.14:54:19.01:data_valid=off 2006.285.14:54:19.01:"et 2006.285.14:54:19.01:!+3s 2006.285.14:54:22.02:"tape 2006.285.14:54:22.02:postob 2006.285.14:54:22.15/cable/+6.4998E-03 2006.285.14:54:22.15/wx/19.16,1015.0,92 2006.285.14:54:22.21/fmout-gps/S +2.73E-07 2006.285.14:54:22.21:scan_name=285-1456,jd0610,310 2006.285.14:54:22.21:source=nrao150,035929.75,505750.2,2000.0,cw 2006.285.14:54:23.13#flagr#flagr/antenna,new-source 2006.285.14:54:23.13:checkk5 2006.285.14:54:23.78/chk_autoobs//k5ts1/ autoobs is running! 2006.285.14:54:24.22/chk_autoobs//k5ts2/ autoobs is running! 2006.285.14:54:24.76/chk_autoobs//k5ts3/ autoobs is running! 2006.285.14:54:25.47/chk_autoobs//k5ts4/ autoobs is running! 2006.285.14:54:25.85/chk_obsdata//k5ts1/T2851452??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.14:54:26.21/chk_obsdata//k5ts2/T2851452??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.14:54:26.61/chk_obsdata//k5ts3/T2851452??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.14:54:26.97/chk_obsdata//k5ts4/T2851452??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.14:54:27.97/k5log//k5ts1_log_newline 2006.285.14:54:28.84/k5log//k5ts2_log_newline 2006.285.14:54:29.70/k5log//k5ts3_log_newline 2006.285.14:54:30.62/k5log//k5ts4_log_newline 2006.285.14:54:30.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.14:54:30.64:setupk4=1 2006.285.14:54:30.64$setupk4/echo=on 2006.285.14:54:30.64$setupk4/pcalon 2006.285.14:54:30.64$pcalon/"no phase cal control is implemented here 2006.285.14:54:30.64$setupk4/"tpicd=stop 2006.285.14:54:30.64$setupk4/"rec=synch_on 2006.285.14:54:30.64$setupk4/"rec_mode=128 2006.285.14:54:30.64$setupk4/!* 2006.285.14:54:30.64$setupk4/recpk4 2006.285.14:54:30.64$recpk4/recpatch= 2006.285.14:54:30.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.14:54:30.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.14:54:30.64$setupk4/vck44 2006.285.14:54:30.64$vck44/valo=1,524.99 2006.285.14:54:30.64#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.14:54:30.64#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.14:54:30.64#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:30.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:54:30.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:54:30.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:54:30.64#ibcon#enter wrdev, iclass 37, count 0 2006.285.14:54:30.64#ibcon#first serial, iclass 37, count 0 2006.285.14:54:30.64#ibcon#enter sib2, iclass 37, count 0 2006.285.14:54:30.64#ibcon#flushed, iclass 37, count 0 2006.285.14:54:30.64#ibcon#about to write, iclass 37, count 0 2006.285.14:54:30.64#ibcon#wrote, iclass 37, count 0 2006.285.14:54:30.64#ibcon#about to read 3, iclass 37, count 0 2006.285.14:54:30.66#ibcon#read 3, iclass 37, count 0 2006.285.14:54:30.66#ibcon#about to read 4, iclass 37, count 0 2006.285.14:54:30.66#ibcon#read 4, iclass 37, count 0 2006.285.14:54:30.66#ibcon#about to read 5, iclass 37, count 0 2006.285.14:54:30.66#ibcon#read 5, iclass 37, count 0 2006.285.14:54:30.66#ibcon#about to read 6, iclass 37, count 0 2006.285.14:54:30.66#ibcon#read 6, iclass 37, count 0 2006.285.14:54:30.66#ibcon#end of sib2, iclass 37, count 0 2006.285.14:54:30.66#ibcon#*mode == 0, iclass 37, count 0 2006.285.14:54:30.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.14:54:30.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.14:54:30.66#ibcon#*before write, iclass 37, count 0 2006.285.14:54:30.66#ibcon#enter sib2, iclass 37, count 0 2006.285.14:54:30.66#ibcon#flushed, iclass 37, count 0 2006.285.14:54:30.66#ibcon#about to write, iclass 37, count 0 2006.285.14:54:30.66#ibcon#wrote, iclass 37, count 0 2006.285.14:54:30.66#ibcon#about to read 3, iclass 37, count 0 2006.285.14:54:30.71#ibcon#read 3, iclass 37, count 0 2006.285.14:54:30.71#ibcon#about to read 4, iclass 37, count 0 2006.285.14:54:30.71#ibcon#read 4, iclass 37, count 0 2006.285.14:54:30.71#ibcon#about to read 5, iclass 37, count 0 2006.285.14:54:30.71#ibcon#read 5, iclass 37, count 0 2006.285.14:54:30.71#ibcon#about to read 6, iclass 37, count 0 2006.285.14:54:30.71#ibcon#read 6, iclass 37, count 0 2006.285.14:54:30.71#ibcon#end of sib2, iclass 37, count 0 2006.285.14:54:30.71#ibcon#*after write, iclass 37, count 0 2006.285.14:54:30.71#ibcon#*before return 0, iclass 37, count 0 2006.285.14:54:30.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:54:30.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:54:30.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.14:54:30.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.14:54:30.71$vck44/va=1,7 2006.285.14:54:30.71#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.14:54:30.71#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.14:54:30.71#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:30.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:54:30.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:54:30.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:54:30.71#ibcon#enter wrdev, iclass 39, count 2 2006.285.14:54:30.71#ibcon#first serial, iclass 39, count 2 2006.285.14:54:30.71#ibcon#enter sib2, iclass 39, count 2 2006.285.14:54:30.71#ibcon#flushed, iclass 39, count 2 2006.285.14:54:30.71#ibcon#about to write, iclass 39, count 2 2006.285.14:54:30.71#ibcon#wrote, iclass 39, count 2 2006.285.14:54:30.71#ibcon#about to read 3, iclass 39, count 2 2006.285.14:54:30.73#ibcon#read 3, iclass 39, count 2 2006.285.14:54:30.73#ibcon#about to read 4, iclass 39, count 2 2006.285.14:54:30.73#ibcon#read 4, iclass 39, count 2 2006.285.14:54:30.73#ibcon#about to read 5, iclass 39, count 2 2006.285.14:54:30.73#ibcon#read 5, iclass 39, count 2 2006.285.14:54:30.73#ibcon#about to read 6, iclass 39, count 2 2006.285.14:54:30.73#ibcon#read 6, iclass 39, count 2 2006.285.14:54:30.73#ibcon#end of sib2, iclass 39, count 2 2006.285.14:54:30.73#ibcon#*mode == 0, iclass 39, count 2 2006.285.14:54:30.73#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.14:54:30.73#ibcon#[25=AT01-07\r\n] 2006.285.14:54:30.73#ibcon#*before write, iclass 39, count 2 2006.285.14:54:30.73#ibcon#enter sib2, iclass 39, count 2 2006.285.14:54:30.73#ibcon#flushed, iclass 39, count 2 2006.285.14:54:30.73#ibcon#about to write, iclass 39, count 2 2006.285.14:54:30.73#ibcon#wrote, iclass 39, count 2 2006.285.14:54:30.73#ibcon#about to read 3, iclass 39, count 2 2006.285.14:54:30.76#ibcon#read 3, iclass 39, count 2 2006.285.14:54:30.76#ibcon#about to read 4, iclass 39, count 2 2006.285.14:54:30.76#ibcon#read 4, iclass 39, count 2 2006.285.14:54:30.76#ibcon#about to read 5, iclass 39, count 2 2006.285.14:54:30.76#ibcon#read 5, iclass 39, count 2 2006.285.14:54:30.76#ibcon#about to read 6, iclass 39, count 2 2006.285.14:54:30.76#ibcon#read 6, iclass 39, count 2 2006.285.14:54:30.76#ibcon#end of sib2, iclass 39, count 2 2006.285.14:54:30.76#ibcon#*after write, iclass 39, count 2 2006.285.14:54:30.76#ibcon#*before return 0, iclass 39, count 2 2006.285.14:54:30.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:54:30.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:54:30.76#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.14:54:30.76#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:30.76#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:54:30.88#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:54:30.88#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:54:30.88#ibcon#enter wrdev, iclass 39, count 0 2006.285.14:54:30.88#ibcon#first serial, iclass 39, count 0 2006.285.14:54:30.88#ibcon#enter sib2, iclass 39, count 0 2006.285.14:54:30.88#ibcon#flushed, iclass 39, count 0 2006.285.14:54:30.88#ibcon#about to write, iclass 39, count 0 2006.285.14:54:30.88#ibcon#wrote, iclass 39, count 0 2006.285.14:54:30.88#ibcon#about to read 3, iclass 39, count 0 2006.285.14:54:30.90#ibcon#read 3, iclass 39, count 0 2006.285.14:54:30.90#ibcon#about to read 4, iclass 39, count 0 2006.285.14:54:30.90#ibcon#read 4, iclass 39, count 0 2006.285.14:54:30.90#ibcon#about to read 5, iclass 39, count 0 2006.285.14:54:30.90#ibcon#read 5, iclass 39, count 0 2006.285.14:54:30.90#ibcon#about to read 6, iclass 39, count 0 2006.285.14:54:30.90#ibcon#read 6, iclass 39, count 0 2006.285.14:54:30.90#ibcon#end of sib2, iclass 39, count 0 2006.285.14:54:30.90#ibcon#*mode == 0, iclass 39, count 0 2006.285.14:54:30.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.14:54:30.90#ibcon#[25=USB\r\n] 2006.285.14:54:30.90#ibcon#*before write, iclass 39, count 0 2006.285.14:54:30.90#ibcon#enter sib2, iclass 39, count 0 2006.285.14:54:30.90#ibcon#flushed, iclass 39, count 0 2006.285.14:54:30.90#ibcon#about to write, iclass 39, count 0 2006.285.14:54:30.90#ibcon#wrote, iclass 39, count 0 2006.285.14:54:30.90#ibcon#about to read 3, iclass 39, count 0 2006.285.14:54:30.93#ibcon#read 3, iclass 39, count 0 2006.285.14:54:30.93#ibcon#about to read 4, iclass 39, count 0 2006.285.14:54:30.93#ibcon#read 4, iclass 39, count 0 2006.285.14:54:30.93#ibcon#about to read 5, iclass 39, count 0 2006.285.14:54:30.93#ibcon#read 5, iclass 39, count 0 2006.285.14:54:30.93#ibcon#about to read 6, iclass 39, count 0 2006.285.14:54:30.93#ibcon#read 6, iclass 39, count 0 2006.285.14:54:30.93#ibcon#end of sib2, iclass 39, count 0 2006.285.14:54:30.93#ibcon#*after write, iclass 39, count 0 2006.285.14:54:30.93#ibcon#*before return 0, iclass 39, count 0 2006.285.14:54:30.93#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:54:30.93#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:54:30.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.14:54:30.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.14:54:30.93$vck44/valo=2,534.99 2006.285.14:54:30.93#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.14:54:30.93#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.14:54:30.93#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:30.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:54:30.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:54:30.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:54:30.93#ibcon#enter wrdev, iclass 3, count 0 2006.285.14:54:30.93#ibcon#first serial, iclass 3, count 0 2006.285.14:54:30.93#ibcon#enter sib2, iclass 3, count 0 2006.285.14:54:30.93#ibcon#flushed, iclass 3, count 0 2006.285.14:54:30.93#ibcon#about to write, iclass 3, count 0 2006.285.14:54:30.93#ibcon#wrote, iclass 3, count 0 2006.285.14:54:30.93#ibcon#about to read 3, iclass 3, count 0 2006.285.14:54:30.95#ibcon#read 3, iclass 3, count 0 2006.285.14:54:30.95#ibcon#about to read 4, iclass 3, count 0 2006.285.14:54:30.95#ibcon#read 4, iclass 3, count 0 2006.285.14:54:30.95#ibcon#about to read 5, iclass 3, count 0 2006.285.14:54:30.95#ibcon#read 5, iclass 3, count 0 2006.285.14:54:30.95#ibcon#about to read 6, iclass 3, count 0 2006.285.14:54:30.95#ibcon#read 6, iclass 3, count 0 2006.285.14:54:30.95#ibcon#end of sib2, iclass 3, count 0 2006.285.14:54:30.95#ibcon#*mode == 0, iclass 3, count 0 2006.285.14:54:30.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.14:54:30.95#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.14:54:30.95#ibcon#*before write, iclass 3, count 0 2006.285.14:54:30.95#ibcon#enter sib2, iclass 3, count 0 2006.285.14:54:30.95#ibcon#flushed, iclass 3, count 0 2006.285.14:54:30.95#ibcon#about to write, iclass 3, count 0 2006.285.14:54:30.95#ibcon#wrote, iclass 3, count 0 2006.285.14:54:30.95#ibcon#about to read 3, iclass 3, count 0 2006.285.14:54:30.99#ibcon#read 3, iclass 3, count 0 2006.285.14:54:30.99#ibcon#about to read 4, iclass 3, count 0 2006.285.14:54:30.99#ibcon#read 4, iclass 3, count 0 2006.285.14:54:30.99#ibcon#about to read 5, iclass 3, count 0 2006.285.14:54:30.99#ibcon#read 5, iclass 3, count 0 2006.285.14:54:30.99#ibcon#about to read 6, iclass 3, count 0 2006.285.14:54:30.99#ibcon#read 6, iclass 3, count 0 2006.285.14:54:30.99#ibcon#end of sib2, iclass 3, count 0 2006.285.14:54:30.99#ibcon#*after write, iclass 3, count 0 2006.285.14:54:30.99#ibcon#*before return 0, iclass 3, count 0 2006.285.14:54:30.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:54:30.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:54:30.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.14:54:30.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.14:54:30.99$vck44/va=2,6 2006.285.14:54:30.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.14:54:30.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.14:54:30.99#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:30.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:54:31.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:54:31.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:54:31.05#ibcon#enter wrdev, iclass 5, count 2 2006.285.14:54:31.05#ibcon#first serial, iclass 5, count 2 2006.285.14:54:31.05#ibcon#enter sib2, iclass 5, count 2 2006.285.14:54:31.05#ibcon#flushed, iclass 5, count 2 2006.285.14:54:31.05#ibcon#about to write, iclass 5, count 2 2006.285.14:54:31.05#ibcon#wrote, iclass 5, count 2 2006.285.14:54:31.05#ibcon#about to read 3, iclass 5, count 2 2006.285.14:54:31.07#ibcon#read 3, iclass 5, count 2 2006.285.14:54:31.07#ibcon#about to read 4, iclass 5, count 2 2006.285.14:54:31.07#ibcon#read 4, iclass 5, count 2 2006.285.14:54:31.07#ibcon#about to read 5, iclass 5, count 2 2006.285.14:54:31.07#ibcon#read 5, iclass 5, count 2 2006.285.14:54:31.07#ibcon#about to read 6, iclass 5, count 2 2006.285.14:54:31.07#ibcon#read 6, iclass 5, count 2 2006.285.14:54:31.07#ibcon#end of sib2, iclass 5, count 2 2006.285.14:54:31.07#ibcon#*mode == 0, iclass 5, count 2 2006.285.14:54:31.07#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.14:54:31.07#ibcon#[25=AT02-06\r\n] 2006.285.14:54:31.07#ibcon#*before write, iclass 5, count 2 2006.285.14:54:31.07#ibcon#enter sib2, iclass 5, count 2 2006.285.14:54:31.07#ibcon#flushed, iclass 5, count 2 2006.285.14:54:31.07#ibcon#about to write, iclass 5, count 2 2006.285.14:54:31.07#ibcon#wrote, iclass 5, count 2 2006.285.14:54:31.07#ibcon#about to read 3, iclass 5, count 2 2006.285.14:54:31.10#ibcon#read 3, iclass 5, count 2 2006.285.14:54:31.10#ibcon#about to read 4, iclass 5, count 2 2006.285.14:54:31.10#ibcon#read 4, iclass 5, count 2 2006.285.14:54:31.10#ibcon#about to read 5, iclass 5, count 2 2006.285.14:54:31.10#ibcon#read 5, iclass 5, count 2 2006.285.14:54:31.10#ibcon#about to read 6, iclass 5, count 2 2006.285.14:54:31.10#ibcon#read 6, iclass 5, count 2 2006.285.14:54:31.10#ibcon#end of sib2, iclass 5, count 2 2006.285.14:54:31.10#ibcon#*after write, iclass 5, count 2 2006.285.14:54:31.10#ibcon#*before return 0, iclass 5, count 2 2006.285.14:54:31.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:54:31.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:54:31.10#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.14:54:31.10#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:31.10#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:54:31.22#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:54:31.22#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:54:31.22#ibcon#enter wrdev, iclass 5, count 0 2006.285.14:54:31.22#ibcon#first serial, iclass 5, count 0 2006.285.14:54:31.22#ibcon#enter sib2, iclass 5, count 0 2006.285.14:54:31.22#ibcon#flushed, iclass 5, count 0 2006.285.14:54:31.22#ibcon#about to write, iclass 5, count 0 2006.285.14:54:31.22#ibcon#wrote, iclass 5, count 0 2006.285.14:54:31.22#ibcon#about to read 3, iclass 5, count 0 2006.285.14:54:31.24#ibcon#read 3, iclass 5, count 0 2006.285.14:54:31.24#ibcon#about to read 4, iclass 5, count 0 2006.285.14:54:31.24#ibcon#read 4, iclass 5, count 0 2006.285.14:54:31.24#ibcon#about to read 5, iclass 5, count 0 2006.285.14:54:31.24#ibcon#read 5, iclass 5, count 0 2006.285.14:54:31.24#ibcon#about to read 6, iclass 5, count 0 2006.285.14:54:31.24#ibcon#read 6, iclass 5, count 0 2006.285.14:54:31.24#ibcon#end of sib2, iclass 5, count 0 2006.285.14:54:31.24#ibcon#*mode == 0, iclass 5, count 0 2006.285.14:54:31.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.14:54:31.24#ibcon#[25=USB\r\n] 2006.285.14:54:31.24#ibcon#*before write, iclass 5, count 0 2006.285.14:54:31.24#ibcon#enter sib2, iclass 5, count 0 2006.285.14:54:31.24#ibcon#flushed, iclass 5, count 0 2006.285.14:54:31.24#ibcon#about to write, iclass 5, count 0 2006.285.14:54:31.24#ibcon#wrote, iclass 5, count 0 2006.285.14:54:31.24#ibcon#about to read 3, iclass 5, count 0 2006.285.14:54:31.27#ibcon#read 3, iclass 5, count 0 2006.285.14:54:31.27#ibcon#about to read 4, iclass 5, count 0 2006.285.14:54:31.27#ibcon#read 4, iclass 5, count 0 2006.285.14:54:31.27#ibcon#about to read 5, iclass 5, count 0 2006.285.14:54:31.27#ibcon#read 5, iclass 5, count 0 2006.285.14:54:31.27#ibcon#about to read 6, iclass 5, count 0 2006.285.14:54:31.27#ibcon#read 6, iclass 5, count 0 2006.285.14:54:31.27#ibcon#end of sib2, iclass 5, count 0 2006.285.14:54:31.27#ibcon#*after write, iclass 5, count 0 2006.285.14:54:31.27#ibcon#*before return 0, iclass 5, count 0 2006.285.14:54:31.27#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:54:31.27#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:54:31.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.14:54:31.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.14:54:31.27$vck44/valo=3,564.99 2006.285.14:54:31.27#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.14:54:31.27#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.14:54:31.27#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:31.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:54:31.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:54:31.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:54:31.27#ibcon#enter wrdev, iclass 7, count 0 2006.285.14:54:31.27#ibcon#first serial, iclass 7, count 0 2006.285.14:54:31.27#ibcon#enter sib2, iclass 7, count 0 2006.285.14:54:31.27#ibcon#flushed, iclass 7, count 0 2006.285.14:54:31.27#ibcon#about to write, iclass 7, count 0 2006.285.14:54:31.27#ibcon#wrote, iclass 7, count 0 2006.285.14:54:31.27#ibcon#about to read 3, iclass 7, count 0 2006.285.14:54:31.29#ibcon#read 3, iclass 7, count 0 2006.285.14:54:31.29#ibcon#about to read 4, iclass 7, count 0 2006.285.14:54:31.74#ibcon#read 4, iclass 7, count 0 2006.285.14:54:31.74#ibcon#about to read 5, iclass 7, count 0 2006.285.14:54:31.74#ibcon#read 5, iclass 7, count 0 2006.285.14:54:31.74#ibcon#about to read 6, iclass 7, count 0 2006.285.14:54:31.74#ibcon#read 6, iclass 7, count 0 2006.285.14:54:31.74#ibcon#end of sib2, iclass 7, count 0 2006.285.14:54:31.74#ibcon#*mode == 0, iclass 7, count 0 2006.285.14:54:31.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.14:54:31.74#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.14:54:31.74#ibcon#*before write, iclass 7, count 0 2006.285.14:54:31.74#ibcon#enter sib2, iclass 7, count 0 2006.285.14:54:31.74#ibcon#flushed, iclass 7, count 0 2006.285.14:54:31.74#ibcon#about to write, iclass 7, count 0 2006.285.14:54:31.74#ibcon#wrote, iclass 7, count 0 2006.285.14:54:31.74#ibcon#about to read 3, iclass 7, count 0 2006.285.14:54:31.77#ibcon#read 3, iclass 7, count 0 2006.285.14:54:31.77#ibcon#about to read 4, iclass 7, count 0 2006.285.14:54:31.77#ibcon#read 4, iclass 7, count 0 2006.285.14:54:31.77#ibcon#about to read 5, iclass 7, count 0 2006.285.14:54:31.77#ibcon#read 5, iclass 7, count 0 2006.285.14:54:31.77#ibcon#about to read 6, iclass 7, count 0 2006.285.14:54:31.77#ibcon#read 6, iclass 7, count 0 2006.285.14:54:31.77#ibcon#end of sib2, iclass 7, count 0 2006.285.14:54:31.77#ibcon#*after write, iclass 7, count 0 2006.285.14:54:31.77#ibcon#*before return 0, iclass 7, count 0 2006.285.14:54:31.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:54:31.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:54:31.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.14:54:31.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.14:54:31.77$vck44/va=3,7 2006.285.14:54:31.77#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.14:54:31.77#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.14:54:31.77#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:31.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:54:31.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:54:31.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:54:31.77#ibcon#enter wrdev, iclass 11, count 2 2006.285.14:54:31.77#ibcon#first serial, iclass 11, count 2 2006.285.14:54:31.77#ibcon#enter sib2, iclass 11, count 2 2006.285.14:54:31.77#ibcon#flushed, iclass 11, count 2 2006.285.14:54:31.77#ibcon#about to write, iclass 11, count 2 2006.285.14:54:31.77#ibcon#wrote, iclass 11, count 2 2006.285.14:54:31.77#ibcon#about to read 3, iclass 11, count 2 2006.285.14:54:31.79#ibcon#read 3, iclass 11, count 2 2006.285.14:54:31.79#ibcon#about to read 4, iclass 11, count 2 2006.285.14:54:31.79#ibcon#read 4, iclass 11, count 2 2006.285.14:54:31.79#ibcon#about to read 5, iclass 11, count 2 2006.285.14:54:31.79#ibcon#read 5, iclass 11, count 2 2006.285.14:54:31.79#ibcon#about to read 6, iclass 11, count 2 2006.285.14:54:31.79#ibcon#read 6, iclass 11, count 2 2006.285.14:54:31.79#ibcon#end of sib2, iclass 11, count 2 2006.285.14:54:31.79#ibcon#*mode == 0, iclass 11, count 2 2006.285.14:54:31.79#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.14:54:31.79#ibcon#[25=AT03-07\r\n] 2006.285.14:54:31.79#ibcon#*before write, iclass 11, count 2 2006.285.14:54:31.79#ibcon#enter sib2, iclass 11, count 2 2006.285.14:54:31.79#ibcon#flushed, iclass 11, count 2 2006.285.14:54:31.79#ibcon#about to write, iclass 11, count 2 2006.285.14:54:31.79#ibcon#wrote, iclass 11, count 2 2006.285.14:54:31.79#ibcon#about to read 3, iclass 11, count 2 2006.285.14:54:31.82#ibcon#read 3, iclass 11, count 2 2006.285.14:54:31.82#ibcon#about to read 4, iclass 11, count 2 2006.285.14:54:31.82#ibcon#read 4, iclass 11, count 2 2006.285.14:54:31.82#ibcon#about to read 5, iclass 11, count 2 2006.285.14:54:31.82#ibcon#read 5, iclass 11, count 2 2006.285.14:54:31.82#ibcon#about to read 6, iclass 11, count 2 2006.285.14:54:31.82#ibcon#read 6, iclass 11, count 2 2006.285.14:54:31.82#ibcon#end of sib2, iclass 11, count 2 2006.285.14:54:31.82#ibcon#*after write, iclass 11, count 2 2006.285.14:54:31.82#ibcon#*before return 0, iclass 11, count 2 2006.285.14:54:31.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:54:31.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:54:31.82#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.14:54:31.82#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:31.82#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:54:31.94#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:54:31.94#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:54:31.94#ibcon#enter wrdev, iclass 11, count 0 2006.285.14:54:31.94#ibcon#first serial, iclass 11, count 0 2006.285.14:54:31.94#ibcon#enter sib2, iclass 11, count 0 2006.285.14:54:31.94#ibcon#flushed, iclass 11, count 0 2006.285.14:54:31.94#ibcon#about to write, iclass 11, count 0 2006.285.14:54:31.94#ibcon#wrote, iclass 11, count 0 2006.285.14:54:31.94#ibcon#about to read 3, iclass 11, count 0 2006.285.14:54:31.96#ibcon#read 3, iclass 11, count 0 2006.285.14:54:31.96#ibcon#about to read 4, iclass 11, count 0 2006.285.14:54:31.96#ibcon#read 4, iclass 11, count 0 2006.285.14:54:31.96#ibcon#about to read 5, iclass 11, count 0 2006.285.14:54:31.96#ibcon#read 5, iclass 11, count 0 2006.285.14:54:31.96#ibcon#about to read 6, iclass 11, count 0 2006.285.14:54:31.96#ibcon#read 6, iclass 11, count 0 2006.285.14:54:31.96#ibcon#end of sib2, iclass 11, count 0 2006.285.14:54:31.96#ibcon#*mode == 0, iclass 11, count 0 2006.285.14:54:31.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.14:54:31.96#ibcon#[25=USB\r\n] 2006.285.14:54:31.96#ibcon#*before write, iclass 11, count 0 2006.285.14:54:31.96#ibcon#enter sib2, iclass 11, count 0 2006.285.14:54:31.96#ibcon#flushed, iclass 11, count 0 2006.285.14:54:31.96#ibcon#about to write, iclass 11, count 0 2006.285.14:54:31.96#ibcon#wrote, iclass 11, count 0 2006.285.14:54:31.96#ibcon#about to read 3, iclass 11, count 0 2006.285.14:54:31.99#ibcon#read 3, iclass 11, count 0 2006.285.14:54:31.99#ibcon#about to read 4, iclass 11, count 0 2006.285.14:54:31.99#ibcon#read 4, iclass 11, count 0 2006.285.14:54:31.99#ibcon#about to read 5, iclass 11, count 0 2006.285.14:54:31.99#ibcon#read 5, iclass 11, count 0 2006.285.14:54:31.99#ibcon#about to read 6, iclass 11, count 0 2006.285.14:54:31.99#ibcon#read 6, iclass 11, count 0 2006.285.14:54:31.99#ibcon#end of sib2, iclass 11, count 0 2006.285.14:54:31.99#ibcon#*after write, iclass 11, count 0 2006.285.14:54:31.99#ibcon#*before return 0, iclass 11, count 0 2006.285.14:54:31.99#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:54:31.99#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:54:31.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.14:54:31.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.14:54:31.99$vck44/valo=4,624.99 2006.285.14:54:31.99#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.14:54:31.99#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.14:54:31.99#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:31.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:54:31.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:54:31.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:54:31.99#ibcon#enter wrdev, iclass 13, count 0 2006.285.14:54:31.99#ibcon#first serial, iclass 13, count 0 2006.285.14:54:31.99#ibcon#enter sib2, iclass 13, count 0 2006.285.14:54:31.99#ibcon#flushed, iclass 13, count 0 2006.285.14:54:31.99#ibcon#about to write, iclass 13, count 0 2006.285.14:54:31.99#ibcon#wrote, iclass 13, count 0 2006.285.14:54:31.99#ibcon#about to read 3, iclass 13, count 0 2006.285.14:54:32.01#ibcon#read 3, iclass 13, count 0 2006.285.14:54:32.01#ibcon#about to read 4, iclass 13, count 0 2006.285.14:54:32.01#ibcon#read 4, iclass 13, count 0 2006.285.14:54:32.01#ibcon#about to read 5, iclass 13, count 0 2006.285.14:54:32.01#ibcon#read 5, iclass 13, count 0 2006.285.14:54:32.01#ibcon#about to read 6, iclass 13, count 0 2006.285.14:54:32.01#ibcon#read 6, iclass 13, count 0 2006.285.14:54:32.01#ibcon#end of sib2, iclass 13, count 0 2006.285.14:54:32.01#ibcon#*mode == 0, iclass 13, count 0 2006.285.14:54:32.01#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.14:54:32.01#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.14:54:32.01#ibcon#*before write, iclass 13, count 0 2006.285.14:54:32.01#ibcon#enter sib2, iclass 13, count 0 2006.285.14:54:32.01#ibcon#flushed, iclass 13, count 0 2006.285.14:54:32.01#ibcon#about to write, iclass 13, count 0 2006.285.14:54:32.01#ibcon#wrote, iclass 13, count 0 2006.285.14:54:32.01#ibcon#about to read 3, iclass 13, count 0 2006.285.14:54:32.05#ibcon#read 3, iclass 13, count 0 2006.285.14:54:32.05#ibcon#about to read 4, iclass 13, count 0 2006.285.14:54:32.05#ibcon#read 4, iclass 13, count 0 2006.285.14:54:32.05#ibcon#about to read 5, iclass 13, count 0 2006.285.14:54:32.05#ibcon#read 5, iclass 13, count 0 2006.285.14:54:32.05#ibcon#about to read 6, iclass 13, count 0 2006.285.14:54:32.05#ibcon#read 6, iclass 13, count 0 2006.285.14:54:32.05#ibcon#end of sib2, iclass 13, count 0 2006.285.14:54:32.05#ibcon#*after write, iclass 13, count 0 2006.285.14:54:32.05#ibcon#*before return 0, iclass 13, count 0 2006.285.14:54:32.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:54:32.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:54:32.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.14:54:32.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.14:54:32.05$vck44/va=4,6 2006.285.14:54:32.05#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.14:54:32.05#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.14:54:32.05#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:32.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:54:32.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:54:32.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:54:32.11#ibcon#enter wrdev, iclass 15, count 2 2006.285.14:54:32.11#ibcon#first serial, iclass 15, count 2 2006.285.14:54:32.11#ibcon#enter sib2, iclass 15, count 2 2006.285.14:54:32.11#ibcon#flushed, iclass 15, count 2 2006.285.14:54:32.11#ibcon#about to write, iclass 15, count 2 2006.285.14:54:32.11#ibcon#wrote, iclass 15, count 2 2006.285.14:54:32.11#ibcon#about to read 3, iclass 15, count 2 2006.285.14:54:32.13#ibcon#read 3, iclass 15, count 2 2006.285.14:54:32.13#ibcon#about to read 4, iclass 15, count 2 2006.285.14:54:32.13#ibcon#read 4, iclass 15, count 2 2006.285.14:54:32.13#ibcon#about to read 5, iclass 15, count 2 2006.285.14:54:32.13#ibcon#read 5, iclass 15, count 2 2006.285.14:54:32.13#ibcon#about to read 6, iclass 15, count 2 2006.285.14:54:32.13#ibcon#read 6, iclass 15, count 2 2006.285.14:54:32.13#ibcon#end of sib2, iclass 15, count 2 2006.285.14:54:32.13#ibcon#*mode == 0, iclass 15, count 2 2006.285.14:54:32.13#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.14:54:32.13#ibcon#[25=AT04-06\r\n] 2006.285.14:54:32.13#ibcon#*before write, iclass 15, count 2 2006.285.14:54:32.13#ibcon#enter sib2, iclass 15, count 2 2006.285.14:54:32.13#ibcon#flushed, iclass 15, count 2 2006.285.14:54:32.13#ibcon#about to write, iclass 15, count 2 2006.285.14:54:32.13#ibcon#wrote, iclass 15, count 2 2006.285.14:54:32.13#ibcon#about to read 3, iclass 15, count 2 2006.285.14:54:32.16#ibcon#read 3, iclass 15, count 2 2006.285.14:54:32.26#ibcon#about to read 4, iclass 15, count 2 2006.285.14:54:32.26#ibcon#read 4, iclass 15, count 2 2006.285.14:54:32.26#ibcon#about to read 5, iclass 15, count 2 2006.285.14:54:32.26#ibcon#read 5, iclass 15, count 2 2006.285.14:54:32.26#ibcon#about to read 6, iclass 15, count 2 2006.285.14:54:32.26#ibcon#read 6, iclass 15, count 2 2006.285.14:54:32.26#ibcon#end of sib2, iclass 15, count 2 2006.285.14:54:32.26#ibcon#*after write, iclass 15, count 2 2006.285.14:54:32.26#ibcon#*before return 0, iclass 15, count 2 2006.285.14:54:32.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:54:32.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:54:32.26#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.14:54:32.26#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:32.26#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:54:32.37#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:54:32.37#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:54:32.37#ibcon#enter wrdev, iclass 15, count 0 2006.285.14:54:32.37#ibcon#first serial, iclass 15, count 0 2006.285.14:54:32.37#ibcon#enter sib2, iclass 15, count 0 2006.285.14:54:32.37#ibcon#flushed, iclass 15, count 0 2006.285.14:54:32.37#ibcon#about to write, iclass 15, count 0 2006.285.14:54:32.37#ibcon#wrote, iclass 15, count 0 2006.285.14:54:32.37#ibcon#about to read 3, iclass 15, count 0 2006.285.14:54:32.39#ibcon#read 3, iclass 15, count 0 2006.285.14:54:32.39#ibcon#about to read 4, iclass 15, count 0 2006.285.14:54:32.39#ibcon#read 4, iclass 15, count 0 2006.285.14:54:32.39#ibcon#about to read 5, iclass 15, count 0 2006.285.14:54:32.39#ibcon#read 5, iclass 15, count 0 2006.285.14:54:32.39#ibcon#about to read 6, iclass 15, count 0 2006.285.14:54:32.39#ibcon#read 6, iclass 15, count 0 2006.285.14:54:32.39#ibcon#end of sib2, iclass 15, count 0 2006.285.14:54:32.39#ibcon#*mode == 0, iclass 15, count 0 2006.285.14:54:32.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.14:54:32.39#ibcon#[25=USB\r\n] 2006.285.14:54:32.39#ibcon#*before write, iclass 15, count 0 2006.285.14:54:32.39#ibcon#enter sib2, iclass 15, count 0 2006.285.14:54:32.39#ibcon#flushed, iclass 15, count 0 2006.285.14:54:32.39#ibcon#about to write, iclass 15, count 0 2006.285.14:54:32.39#ibcon#wrote, iclass 15, count 0 2006.285.14:54:32.39#ibcon#about to read 3, iclass 15, count 0 2006.285.14:54:32.42#ibcon#read 3, iclass 15, count 0 2006.285.14:54:32.42#ibcon#about to read 4, iclass 15, count 0 2006.285.14:54:32.42#ibcon#read 4, iclass 15, count 0 2006.285.14:54:32.42#ibcon#about to read 5, iclass 15, count 0 2006.285.14:54:32.42#ibcon#read 5, iclass 15, count 0 2006.285.14:54:32.42#ibcon#about to read 6, iclass 15, count 0 2006.285.14:54:32.42#ibcon#read 6, iclass 15, count 0 2006.285.14:54:32.42#ibcon#end of sib2, iclass 15, count 0 2006.285.14:54:32.42#ibcon#*after write, iclass 15, count 0 2006.285.14:54:32.42#ibcon#*before return 0, iclass 15, count 0 2006.285.14:54:32.42#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:54:32.42#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:54:32.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.14:54:32.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.14:54:32.42$vck44/valo=5,734.99 2006.285.14:54:32.42#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.14:54:32.42#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.14:54:32.42#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:32.42#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:54:32.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:54:32.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:54:32.42#ibcon#enter wrdev, iclass 17, count 0 2006.285.14:54:32.42#ibcon#first serial, iclass 17, count 0 2006.285.14:54:32.42#ibcon#enter sib2, iclass 17, count 0 2006.285.14:54:32.42#ibcon#flushed, iclass 17, count 0 2006.285.14:54:32.42#ibcon#about to write, iclass 17, count 0 2006.285.14:54:32.42#ibcon#wrote, iclass 17, count 0 2006.285.14:54:32.42#ibcon#about to read 3, iclass 17, count 0 2006.285.14:54:32.44#ibcon#read 3, iclass 17, count 0 2006.285.14:54:32.54#ibcon#about to read 4, iclass 17, count 0 2006.285.14:54:32.54#ibcon#read 4, iclass 17, count 0 2006.285.14:54:32.54#ibcon#about to read 5, iclass 17, count 0 2006.285.14:54:32.54#ibcon#read 5, iclass 17, count 0 2006.285.14:54:32.54#ibcon#about to read 6, iclass 17, count 0 2006.285.14:54:32.54#ibcon#read 6, iclass 17, count 0 2006.285.14:54:32.54#ibcon#end of sib2, iclass 17, count 0 2006.285.14:54:32.54#ibcon#*mode == 0, iclass 17, count 0 2006.285.14:54:32.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.14:54:32.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.14:54:32.54#ibcon#*before write, iclass 17, count 0 2006.285.14:54:32.54#ibcon#enter sib2, iclass 17, count 0 2006.285.14:54:32.54#ibcon#flushed, iclass 17, count 0 2006.285.14:54:32.54#ibcon#about to write, iclass 17, count 0 2006.285.14:54:32.54#ibcon#wrote, iclass 17, count 0 2006.285.14:54:32.54#ibcon#about to read 3, iclass 17, count 0 2006.285.14:54:32.58#ibcon#read 3, iclass 17, count 0 2006.285.14:54:32.58#ibcon#about to read 4, iclass 17, count 0 2006.285.14:54:32.58#ibcon#read 4, iclass 17, count 0 2006.285.14:54:32.58#ibcon#about to read 5, iclass 17, count 0 2006.285.14:54:32.58#ibcon#read 5, iclass 17, count 0 2006.285.14:54:32.58#ibcon#about to read 6, iclass 17, count 0 2006.285.14:54:32.58#ibcon#read 6, iclass 17, count 0 2006.285.14:54:32.58#ibcon#end of sib2, iclass 17, count 0 2006.285.14:54:32.58#ibcon#*after write, iclass 17, count 0 2006.285.14:54:32.58#ibcon#*before return 0, iclass 17, count 0 2006.285.14:54:32.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:54:32.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:54:32.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.14:54:32.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.14:54:32.58$vck44/va=5,3 2006.285.14:54:32.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.14:54:32.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.14:54:32.58#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:32.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:54:32.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:54:32.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:54:32.58#ibcon#enter wrdev, iclass 19, count 2 2006.285.14:54:32.58#ibcon#first serial, iclass 19, count 2 2006.285.14:54:32.58#ibcon#enter sib2, iclass 19, count 2 2006.285.14:54:32.58#ibcon#flushed, iclass 19, count 2 2006.285.14:54:32.58#ibcon#about to write, iclass 19, count 2 2006.285.14:54:32.58#ibcon#wrote, iclass 19, count 2 2006.285.14:54:32.58#ibcon#about to read 3, iclass 19, count 2 2006.285.14:54:32.60#ibcon#read 3, iclass 19, count 2 2006.285.14:54:32.60#ibcon#about to read 4, iclass 19, count 2 2006.285.14:54:32.60#ibcon#read 4, iclass 19, count 2 2006.285.14:54:32.60#ibcon#about to read 5, iclass 19, count 2 2006.285.14:54:32.60#ibcon#read 5, iclass 19, count 2 2006.285.14:54:32.60#ibcon#about to read 6, iclass 19, count 2 2006.285.14:54:32.60#ibcon#read 6, iclass 19, count 2 2006.285.14:54:32.60#ibcon#end of sib2, iclass 19, count 2 2006.285.14:54:32.60#ibcon#*mode == 0, iclass 19, count 2 2006.285.14:54:32.60#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.14:54:32.60#ibcon#[25=AT05-03\r\n] 2006.285.14:54:32.60#ibcon#*before write, iclass 19, count 2 2006.285.14:54:32.60#ibcon#enter sib2, iclass 19, count 2 2006.285.14:54:32.60#ibcon#flushed, iclass 19, count 2 2006.285.14:54:32.60#ibcon#about to write, iclass 19, count 2 2006.285.14:54:32.60#ibcon#wrote, iclass 19, count 2 2006.285.14:54:32.60#ibcon#about to read 3, iclass 19, count 2 2006.285.14:54:32.63#ibcon#read 3, iclass 19, count 2 2006.285.14:54:32.63#ibcon#about to read 4, iclass 19, count 2 2006.285.14:54:32.63#ibcon#read 4, iclass 19, count 2 2006.285.14:54:32.63#ibcon#about to read 5, iclass 19, count 2 2006.285.14:54:32.63#ibcon#read 5, iclass 19, count 2 2006.285.14:54:32.63#ibcon#about to read 6, iclass 19, count 2 2006.285.14:54:32.63#ibcon#read 6, iclass 19, count 2 2006.285.14:54:32.63#ibcon#end of sib2, iclass 19, count 2 2006.285.14:54:32.63#ibcon#*after write, iclass 19, count 2 2006.285.14:54:32.63#ibcon#*before return 0, iclass 19, count 2 2006.285.14:54:32.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:54:32.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:54:32.63#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.14:54:32.63#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:32.63#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:54:32.75#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:54:32.75#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:54:32.75#ibcon#enter wrdev, iclass 19, count 0 2006.285.14:54:32.75#ibcon#first serial, iclass 19, count 0 2006.285.14:54:32.75#ibcon#enter sib2, iclass 19, count 0 2006.285.14:54:32.75#ibcon#flushed, iclass 19, count 0 2006.285.14:54:32.75#ibcon#about to write, iclass 19, count 0 2006.285.14:54:32.75#ibcon#wrote, iclass 19, count 0 2006.285.14:54:32.75#ibcon#about to read 3, iclass 19, count 0 2006.285.14:54:32.77#ibcon#read 3, iclass 19, count 0 2006.285.14:54:32.77#ibcon#about to read 4, iclass 19, count 0 2006.285.14:54:32.77#ibcon#read 4, iclass 19, count 0 2006.285.14:54:32.77#ibcon#about to read 5, iclass 19, count 0 2006.285.14:54:32.77#ibcon#read 5, iclass 19, count 0 2006.285.14:54:32.77#ibcon#about to read 6, iclass 19, count 0 2006.285.14:54:32.77#ibcon#read 6, iclass 19, count 0 2006.285.14:54:32.77#ibcon#end of sib2, iclass 19, count 0 2006.285.14:54:32.77#ibcon#*mode == 0, iclass 19, count 0 2006.285.14:54:32.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.14:54:32.77#ibcon#[25=USB\r\n] 2006.285.14:54:32.77#ibcon#*before write, iclass 19, count 0 2006.285.14:54:32.77#ibcon#enter sib2, iclass 19, count 0 2006.285.14:54:32.77#ibcon#flushed, iclass 19, count 0 2006.285.14:54:32.77#ibcon#about to write, iclass 19, count 0 2006.285.14:54:32.77#ibcon#wrote, iclass 19, count 0 2006.285.14:54:32.77#ibcon#about to read 3, iclass 19, count 0 2006.285.14:54:32.80#ibcon#read 3, iclass 19, count 0 2006.285.14:54:32.80#ibcon#about to read 4, iclass 19, count 0 2006.285.14:54:32.80#ibcon#read 4, iclass 19, count 0 2006.285.14:54:32.80#ibcon#about to read 5, iclass 19, count 0 2006.285.14:54:32.80#ibcon#read 5, iclass 19, count 0 2006.285.14:54:32.80#ibcon#about to read 6, iclass 19, count 0 2006.285.14:54:32.80#ibcon#read 6, iclass 19, count 0 2006.285.14:54:32.80#ibcon#end of sib2, iclass 19, count 0 2006.285.14:54:32.80#ibcon#*after write, iclass 19, count 0 2006.285.14:54:32.80#ibcon#*before return 0, iclass 19, count 0 2006.285.14:54:32.80#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:54:32.80#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:54:32.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.14:54:32.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.14:54:32.80$vck44/valo=6,814.99 2006.285.14:54:32.80#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.14:54:32.80#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.14:54:32.80#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:32.80#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:54:32.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:54:32.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:54:32.80#ibcon#enter wrdev, iclass 22, count 0 2006.285.14:54:32.80#ibcon#first serial, iclass 22, count 0 2006.285.14:54:32.80#ibcon#enter sib2, iclass 22, count 0 2006.285.14:54:32.80#ibcon#flushed, iclass 22, count 0 2006.285.14:54:32.80#ibcon#about to write, iclass 22, count 0 2006.285.14:54:32.80#ibcon#wrote, iclass 22, count 0 2006.285.14:54:32.80#ibcon#about to read 3, iclass 22, count 0 2006.285.14:54:32.82#ibcon#read 3, iclass 22, count 0 2006.285.14:54:32.82#ibcon#about to read 4, iclass 22, count 0 2006.285.14:54:32.82#ibcon#read 4, iclass 22, count 0 2006.285.14:54:32.82#ibcon#about to read 5, iclass 22, count 0 2006.285.14:54:32.82#ibcon#read 5, iclass 22, count 0 2006.285.14:54:32.82#ibcon#about to read 6, iclass 22, count 0 2006.285.14:54:32.82#ibcon#read 6, iclass 22, count 0 2006.285.14:54:32.82#ibcon#end of sib2, iclass 22, count 0 2006.285.14:54:32.82#ibcon#*mode == 0, iclass 22, count 0 2006.285.14:54:32.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.14:54:32.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.14:54:32.82#ibcon#*before write, iclass 22, count 0 2006.285.14:54:32.82#ibcon#enter sib2, iclass 22, count 0 2006.285.14:54:32.82#ibcon#flushed, iclass 22, count 0 2006.285.14:54:32.82#ibcon#about to write, iclass 22, count 0 2006.285.14:54:32.82#ibcon#wrote, iclass 22, count 0 2006.285.14:54:32.82#ibcon#about to read 3, iclass 22, count 0 2006.285.14:54:32.84#abcon#<5=/03 1.9 5.0 19.15 921015.0\r\n> 2006.285.14:54:32.86#abcon#{5=INTERFACE CLEAR} 2006.285.14:54:32.86#ibcon#read 3, iclass 22, count 0 2006.285.14:54:32.86#ibcon#about to read 4, iclass 22, count 0 2006.285.14:54:32.86#ibcon#read 4, iclass 22, count 0 2006.285.14:54:32.86#ibcon#about to read 5, iclass 22, count 0 2006.285.14:54:32.86#ibcon#read 5, iclass 22, count 0 2006.285.14:54:32.86#ibcon#about to read 6, iclass 22, count 0 2006.285.14:54:32.86#ibcon#read 6, iclass 22, count 0 2006.285.14:54:32.86#ibcon#end of sib2, iclass 22, count 0 2006.285.14:54:32.86#ibcon#*after write, iclass 22, count 0 2006.285.14:54:32.86#ibcon#*before return 0, iclass 22, count 0 2006.285.14:54:32.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:54:32.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.14:54:32.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.14:54:32.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.14:54:32.86$vck44/va=6,4 2006.285.14:54:32.86#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.14:54:32.86#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.14:54:32.86#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:32.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:54:32.92#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:54:32.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:54:32.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:54:32.92#ibcon#enter wrdev, iclass 26, count 2 2006.285.14:54:32.92#ibcon#first serial, iclass 26, count 2 2006.285.14:54:32.92#ibcon#enter sib2, iclass 26, count 2 2006.285.14:54:32.92#ibcon#flushed, iclass 26, count 2 2006.285.14:54:32.92#ibcon#about to write, iclass 26, count 2 2006.285.14:54:32.92#ibcon#wrote, iclass 26, count 2 2006.285.14:54:32.92#ibcon#about to read 3, iclass 26, count 2 2006.285.14:54:32.94#ibcon#read 3, iclass 26, count 2 2006.285.14:54:32.94#ibcon#about to read 4, iclass 26, count 2 2006.285.14:54:32.94#ibcon#read 4, iclass 26, count 2 2006.285.14:54:32.94#ibcon#about to read 5, iclass 26, count 2 2006.285.14:54:32.94#ibcon#read 5, iclass 26, count 2 2006.285.14:54:32.94#ibcon#about to read 6, iclass 26, count 2 2006.285.14:54:32.94#ibcon#read 6, iclass 26, count 2 2006.285.14:54:32.94#ibcon#end of sib2, iclass 26, count 2 2006.285.14:54:32.94#ibcon#*mode == 0, iclass 26, count 2 2006.285.14:54:32.94#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.14:54:32.94#ibcon#[25=AT06-04\r\n] 2006.285.14:54:32.94#ibcon#*before write, iclass 26, count 2 2006.285.14:54:32.94#ibcon#enter sib2, iclass 26, count 2 2006.285.14:54:32.94#ibcon#flushed, iclass 26, count 2 2006.285.14:54:32.94#ibcon#about to write, iclass 26, count 2 2006.285.14:54:32.94#ibcon#wrote, iclass 26, count 2 2006.285.14:54:32.94#ibcon#about to read 3, iclass 26, count 2 2006.285.14:54:32.97#ibcon#read 3, iclass 26, count 2 2006.285.14:54:32.97#ibcon#about to read 4, iclass 26, count 2 2006.285.14:54:32.97#ibcon#read 4, iclass 26, count 2 2006.285.14:54:32.97#ibcon#about to read 5, iclass 26, count 2 2006.285.14:54:32.97#ibcon#read 5, iclass 26, count 2 2006.285.14:54:32.97#ibcon#about to read 6, iclass 26, count 2 2006.285.14:54:32.97#ibcon#read 6, iclass 26, count 2 2006.285.14:54:32.97#ibcon#end of sib2, iclass 26, count 2 2006.285.14:54:32.97#ibcon#*after write, iclass 26, count 2 2006.285.14:54:32.97#ibcon#*before return 0, iclass 26, count 2 2006.285.14:54:32.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:54:32.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.14:54:32.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.14:54:32.97#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:32.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:54:33.09#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:54:33.09#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:54:33.09#ibcon#enter wrdev, iclass 26, count 0 2006.285.14:54:33.09#ibcon#first serial, iclass 26, count 0 2006.285.14:54:33.09#ibcon#enter sib2, iclass 26, count 0 2006.285.14:54:33.09#ibcon#flushed, iclass 26, count 0 2006.285.14:54:33.09#ibcon#about to write, iclass 26, count 0 2006.285.14:54:33.09#ibcon#wrote, iclass 26, count 0 2006.285.14:54:33.09#ibcon#about to read 3, iclass 26, count 0 2006.285.14:54:33.11#ibcon#read 3, iclass 26, count 0 2006.285.14:54:33.11#ibcon#about to read 4, iclass 26, count 0 2006.285.14:54:33.11#ibcon#read 4, iclass 26, count 0 2006.285.14:54:33.11#ibcon#about to read 5, iclass 26, count 0 2006.285.14:54:33.11#ibcon#read 5, iclass 26, count 0 2006.285.14:54:33.11#ibcon#about to read 6, iclass 26, count 0 2006.285.14:54:33.11#ibcon#read 6, iclass 26, count 0 2006.285.14:54:33.11#ibcon#end of sib2, iclass 26, count 0 2006.285.14:54:33.11#ibcon#*mode == 0, iclass 26, count 0 2006.285.14:54:33.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.14:54:33.11#ibcon#[25=USB\r\n] 2006.285.14:54:33.11#ibcon#*before write, iclass 26, count 0 2006.285.14:54:33.11#ibcon#enter sib2, iclass 26, count 0 2006.285.14:54:33.11#ibcon#flushed, iclass 26, count 0 2006.285.14:54:33.11#ibcon#about to write, iclass 26, count 0 2006.285.14:54:33.11#ibcon#wrote, iclass 26, count 0 2006.285.14:54:33.11#ibcon#about to read 3, iclass 26, count 0 2006.285.14:54:33.14#ibcon#read 3, iclass 26, count 0 2006.285.14:54:33.14#ibcon#about to read 4, iclass 26, count 0 2006.285.14:54:33.14#ibcon#read 4, iclass 26, count 0 2006.285.14:54:33.14#ibcon#about to read 5, iclass 26, count 0 2006.285.14:54:33.14#ibcon#read 5, iclass 26, count 0 2006.285.14:54:33.14#ibcon#about to read 6, iclass 26, count 0 2006.285.14:54:33.14#ibcon#read 6, iclass 26, count 0 2006.285.14:54:33.14#ibcon#end of sib2, iclass 26, count 0 2006.285.14:54:33.14#ibcon#*after write, iclass 26, count 0 2006.285.14:54:33.14#ibcon#*before return 0, iclass 26, count 0 2006.285.14:54:33.14#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:54:33.14#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.14:54:33.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.14:54:33.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.14:54:33.14$vck44/valo=7,864.99 2006.285.14:54:33.14#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.14:54:33.14#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.14:54:33.14#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:33.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:54:33.14#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:54:33.14#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:54:33.14#ibcon#enter wrdev, iclass 29, count 0 2006.285.14:54:33.14#ibcon#first serial, iclass 29, count 0 2006.285.14:54:33.14#ibcon#enter sib2, iclass 29, count 0 2006.285.14:54:33.14#ibcon#flushed, iclass 29, count 0 2006.285.14:54:33.14#ibcon#about to write, iclass 29, count 0 2006.285.14:54:33.14#ibcon#wrote, iclass 29, count 0 2006.285.14:54:33.14#ibcon#about to read 3, iclass 29, count 0 2006.285.14:54:33.16#ibcon#read 3, iclass 29, count 0 2006.285.14:54:33.16#ibcon#about to read 4, iclass 29, count 0 2006.285.14:54:33.16#ibcon#read 4, iclass 29, count 0 2006.285.14:54:33.16#ibcon#about to read 5, iclass 29, count 0 2006.285.14:54:33.16#ibcon#read 5, iclass 29, count 0 2006.285.14:54:33.16#ibcon#about to read 6, iclass 29, count 0 2006.285.14:54:33.16#ibcon#read 6, iclass 29, count 0 2006.285.14:54:33.16#ibcon#end of sib2, iclass 29, count 0 2006.285.14:54:33.16#ibcon#*mode == 0, iclass 29, count 0 2006.285.14:54:33.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.14:54:33.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.14:54:33.16#ibcon#*before write, iclass 29, count 0 2006.285.14:54:33.16#ibcon#enter sib2, iclass 29, count 0 2006.285.14:54:33.16#ibcon#flushed, iclass 29, count 0 2006.285.14:54:33.16#ibcon#about to write, iclass 29, count 0 2006.285.14:54:33.16#ibcon#wrote, iclass 29, count 0 2006.285.14:54:33.16#ibcon#about to read 3, iclass 29, count 0 2006.285.14:54:33.20#ibcon#read 3, iclass 29, count 0 2006.285.14:54:33.20#ibcon#about to read 4, iclass 29, count 0 2006.285.14:54:33.20#ibcon#read 4, iclass 29, count 0 2006.285.14:54:33.20#ibcon#about to read 5, iclass 29, count 0 2006.285.14:54:33.20#ibcon#read 5, iclass 29, count 0 2006.285.14:54:33.20#ibcon#about to read 6, iclass 29, count 0 2006.285.14:54:33.20#ibcon#read 6, iclass 29, count 0 2006.285.14:54:33.20#ibcon#end of sib2, iclass 29, count 0 2006.285.14:54:33.20#ibcon#*after write, iclass 29, count 0 2006.285.14:54:33.20#ibcon#*before return 0, iclass 29, count 0 2006.285.14:54:33.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:54:33.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:54:33.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.14:54:33.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.14:54:33.20$vck44/va=7,4 2006.285.14:54:33.20#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.14:54:33.20#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.14:54:33.20#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:33.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:54:33.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:54:33.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:54:33.26#ibcon#enter wrdev, iclass 31, count 2 2006.285.14:54:33.26#ibcon#first serial, iclass 31, count 2 2006.285.14:54:33.26#ibcon#enter sib2, iclass 31, count 2 2006.285.14:54:33.26#ibcon#flushed, iclass 31, count 2 2006.285.14:54:33.26#ibcon#about to write, iclass 31, count 2 2006.285.14:54:33.26#ibcon#wrote, iclass 31, count 2 2006.285.14:54:33.26#ibcon#about to read 3, iclass 31, count 2 2006.285.14:54:33.28#ibcon#read 3, iclass 31, count 2 2006.285.14:54:33.28#ibcon#about to read 4, iclass 31, count 2 2006.285.14:54:33.28#ibcon#read 4, iclass 31, count 2 2006.285.14:54:33.28#ibcon#about to read 5, iclass 31, count 2 2006.285.14:54:33.28#ibcon#read 5, iclass 31, count 2 2006.285.14:54:33.28#ibcon#about to read 6, iclass 31, count 2 2006.285.14:54:33.28#ibcon#read 6, iclass 31, count 2 2006.285.14:54:33.28#ibcon#end of sib2, iclass 31, count 2 2006.285.14:54:33.28#ibcon#*mode == 0, iclass 31, count 2 2006.285.14:54:33.28#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.14:54:33.28#ibcon#[25=AT07-04\r\n] 2006.285.14:54:33.28#ibcon#*before write, iclass 31, count 2 2006.285.14:54:33.28#ibcon#enter sib2, iclass 31, count 2 2006.285.14:54:33.28#ibcon#flushed, iclass 31, count 2 2006.285.14:54:33.28#ibcon#about to write, iclass 31, count 2 2006.285.14:54:33.28#ibcon#wrote, iclass 31, count 2 2006.285.14:54:33.28#ibcon#about to read 3, iclass 31, count 2 2006.285.14:54:33.31#ibcon#read 3, iclass 31, count 2 2006.285.14:54:33.31#ibcon#about to read 4, iclass 31, count 2 2006.285.14:54:33.31#ibcon#read 4, iclass 31, count 2 2006.285.14:54:33.31#ibcon#about to read 5, iclass 31, count 2 2006.285.14:54:33.31#ibcon#read 5, iclass 31, count 2 2006.285.14:54:33.31#ibcon#about to read 6, iclass 31, count 2 2006.285.14:54:33.31#ibcon#read 6, iclass 31, count 2 2006.285.14:54:33.31#ibcon#end of sib2, iclass 31, count 2 2006.285.14:54:33.31#ibcon#*after write, iclass 31, count 2 2006.285.14:54:33.31#ibcon#*before return 0, iclass 31, count 2 2006.285.14:54:33.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:54:33.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:54:33.31#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.14:54:33.31#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:33.31#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:54:33.43#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:54:33.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:54:33.49#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:54:33.49#ibcon#first serial, iclass 31, count 0 2006.285.14:54:33.49#ibcon#enter sib2, iclass 31, count 0 2006.285.14:54:33.49#ibcon#flushed, iclass 31, count 0 2006.285.14:54:33.49#ibcon#about to write, iclass 31, count 0 2006.285.14:54:33.49#ibcon#wrote, iclass 31, count 0 2006.285.14:54:33.49#ibcon#about to read 3, iclass 31, count 0 2006.285.14:54:33.50#ibcon#read 3, iclass 31, count 0 2006.285.14:54:33.50#ibcon#about to read 4, iclass 31, count 0 2006.285.14:54:33.50#ibcon#read 4, iclass 31, count 0 2006.285.14:54:33.50#ibcon#about to read 5, iclass 31, count 0 2006.285.14:54:33.50#ibcon#read 5, iclass 31, count 0 2006.285.14:54:33.50#ibcon#about to read 6, iclass 31, count 0 2006.285.14:54:33.50#ibcon#read 6, iclass 31, count 0 2006.285.14:54:33.50#ibcon#end of sib2, iclass 31, count 0 2006.285.14:54:33.50#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:54:33.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:54:33.50#ibcon#[25=USB\r\n] 2006.285.14:54:33.50#ibcon#*before write, iclass 31, count 0 2006.285.14:54:33.50#ibcon#enter sib2, iclass 31, count 0 2006.285.14:54:33.50#ibcon#flushed, iclass 31, count 0 2006.285.14:54:33.50#ibcon#about to write, iclass 31, count 0 2006.285.14:54:33.50#ibcon#wrote, iclass 31, count 0 2006.285.14:54:33.50#ibcon#about to read 3, iclass 31, count 0 2006.285.14:54:33.53#ibcon#read 3, iclass 31, count 0 2006.285.14:54:33.53#ibcon#about to read 4, iclass 31, count 0 2006.285.14:54:33.53#ibcon#read 4, iclass 31, count 0 2006.285.14:54:33.53#ibcon#about to read 5, iclass 31, count 0 2006.285.14:54:33.53#ibcon#read 5, iclass 31, count 0 2006.285.14:54:33.53#ibcon#about to read 6, iclass 31, count 0 2006.285.14:54:33.53#ibcon#read 6, iclass 31, count 0 2006.285.14:54:33.53#ibcon#end of sib2, iclass 31, count 0 2006.285.14:54:33.53#ibcon#*after write, iclass 31, count 0 2006.285.14:54:33.53#ibcon#*before return 0, iclass 31, count 0 2006.285.14:54:33.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:54:33.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:54:33.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:54:33.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:54:33.53$vck44/valo=8,884.99 2006.285.14:54:33.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.14:54:33.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.14:54:33.53#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:33.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:54:33.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:54:33.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:54:33.53#ibcon#enter wrdev, iclass 33, count 0 2006.285.14:54:33.53#ibcon#first serial, iclass 33, count 0 2006.285.14:54:33.53#ibcon#enter sib2, iclass 33, count 0 2006.285.14:54:33.53#ibcon#flushed, iclass 33, count 0 2006.285.14:54:33.53#ibcon#about to write, iclass 33, count 0 2006.285.14:54:33.53#ibcon#wrote, iclass 33, count 0 2006.285.14:54:33.53#ibcon#about to read 3, iclass 33, count 0 2006.285.14:54:33.55#ibcon#read 3, iclass 33, count 0 2006.285.14:54:33.55#ibcon#about to read 4, iclass 33, count 0 2006.285.14:54:33.55#ibcon#read 4, iclass 33, count 0 2006.285.14:54:33.55#ibcon#about to read 5, iclass 33, count 0 2006.285.14:54:33.55#ibcon#read 5, iclass 33, count 0 2006.285.14:54:33.55#ibcon#about to read 6, iclass 33, count 0 2006.285.14:54:33.55#ibcon#read 6, iclass 33, count 0 2006.285.14:54:33.55#ibcon#end of sib2, iclass 33, count 0 2006.285.14:54:33.55#ibcon#*mode == 0, iclass 33, count 0 2006.285.14:54:33.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.14:54:33.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.14:54:33.55#ibcon#*before write, iclass 33, count 0 2006.285.14:54:33.55#ibcon#enter sib2, iclass 33, count 0 2006.285.14:54:33.55#ibcon#flushed, iclass 33, count 0 2006.285.14:54:33.55#ibcon#about to write, iclass 33, count 0 2006.285.14:54:33.55#ibcon#wrote, iclass 33, count 0 2006.285.14:54:33.55#ibcon#about to read 3, iclass 33, count 0 2006.285.14:54:33.59#ibcon#read 3, iclass 33, count 0 2006.285.14:54:33.59#ibcon#about to read 4, iclass 33, count 0 2006.285.14:54:33.59#ibcon#read 4, iclass 33, count 0 2006.285.14:54:33.59#ibcon#about to read 5, iclass 33, count 0 2006.285.14:54:33.59#ibcon#read 5, iclass 33, count 0 2006.285.14:54:33.59#ibcon#about to read 6, iclass 33, count 0 2006.285.14:54:33.59#ibcon#read 6, iclass 33, count 0 2006.285.14:54:33.59#ibcon#end of sib2, iclass 33, count 0 2006.285.14:54:33.59#ibcon#*after write, iclass 33, count 0 2006.285.14:54:33.59#ibcon#*before return 0, iclass 33, count 0 2006.285.14:54:33.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:54:33.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:54:33.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.14:54:33.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.14:54:33.59$vck44/va=8,3 2006.285.14:54:33.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.14:54:33.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.14:54:33.59#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:33.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:54:33.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:54:33.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:54:33.65#ibcon#enter wrdev, iclass 35, count 2 2006.285.14:54:33.65#ibcon#first serial, iclass 35, count 2 2006.285.14:54:33.65#ibcon#enter sib2, iclass 35, count 2 2006.285.14:54:33.65#ibcon#flushed, iclass 35, count 2 2006.285.14:54:33.65#ibcon#about to write, iclass 35, count 2 2006.285.14:54:33.65#ibcon#wrote, iclass 35, count 2 2006.285.14:54:33.65#ibcon#about to read 3, iclass 35, count 2 2006.285.14:54:33.67#ibcon#read 3, iclass 35, count 2 2006.285.14:54:33.67#ibcon#about to read 4, iclass 35, count 2 2006.285.14:54:33.67#ibcon#read 4, iclass 35, count 2 2006.285.14:54:33.67#ibcon#about to read 5, iclass 35, count 2 2006.285.14:54:33.67#ibcon#read 5, iclass 35, count 2 2006.285.14:54:33.67#ibcon#about to read 6, iclass 35, count 2 2006.285.14:54:33.67#ibcon#read 6, iclass 35, count 2 2006.285.14:54:33.67#ibcon#end of sib2, iclass 35, count 2 2006.285.14:54:33.67#ibcon#*mode == 0, iclass 35, count 2 2006.285.14:54:33.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.14:54:33.67#ibcon#[25=AT08-03\r\n] 2006.285.14:54:33.67#ibcon#*before write, iclass 35, count 2 2006.285.14:54:33.67#ibcon#enter sib2, iclass 35, count 2 2006.285.14:54:33.67#ibcon#flushed, iclass 35, count 2 2006.285.14:54:33.67#ibcon#about to write, iclass 35, count 2 2006.285.14:54:33.67#ibcon#wrote, iclass 35, count 2 2006.285.14:54:33.67#ibcon#about to read 3, iclass 35, count 2 2006.285.14:54:33.70#ibcon#read 3, iclass 35, count 2 2006.285.14:54:33.70#ibcon#about to read 4, iclass 35, count 2 2006.285.14:54:33.70#ibcon#read 4, iclass 35, count 2 2006.285.14:54:33.70#ibcon#about to read 5, iclass 35, count 2 2006.285.14:54:33.70#ibcon#read 5, iclass 35, count 2 2006.285.14:54:33.70#ibcon#about to read 6, iclass 35, count 2 2006.285.14:54:33.70#ibcon#read 6, iclass 35, count 2 2006.285.14:54:33.70#ibcon#end of sib2, iclass 35, count 2 2006.285.14:54:33.70#ibcon#*after write, iclass 35, count 2 2006.285.14:54:33.70#ibcon#*before return 0, iclass 35, count 2 2006.285.14:54:33.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:54:33.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.14:54:33.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.14:54:33.70#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:33.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:54:33.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:54:33.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:54:33.82#ibcon#enter wrdev, iclass 35, count 0 2006.285.14:54:33.82#ibcon#first serial, iclass 35, count 0 2006.285.14:54:33.82#ibcon#enter sib2, iclass 35, count 0 2006.285.14:54:33.82#ibcon#flushed, iclass 35, count 0 2006.285.14:54:33.82#ibcon#about to write, iclass 35, count 0 2006.285.14:54:33.82#ibcon#wrote, iclass 35, count 0 2006.285.14:54:33.82#ibcon#about to read 3, iclass 35, count 0 2006.285.14:54:33.84#ibcon#read 3, iclass 35, count 0 2006.285.14:54:33.84#ibcon#about to read 4, iclass 35, count 0 2006.285.14:54:33.84#ibcon#read 4, iclass 35, count 0 2006.285.14:54:33.84#ibcon#about to read 5, iclass 35, count 0 2006.285.14:54:33.84#ibcon#read 5, iclass 35, count 0 2006.285.14:54:33.84#ibcon#about to read 6, iclass 35, count 0 2006.285.14:54:33.84#ibcon#read 6, iclass 35, count 0 2006.285.14:54:33.84#ibcon#end of sib2, iclass 35, count 0 2006.285.14:54:33.84#ibcon#*mode == 0, iclass 35, count 0 2006.285.14:54:33.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.14:54:33.84#ibcon#[25=USB\r\n] 2006.285.14:54:33.84#ibcon#*before write, iclass 35, count 0 2006.285.14:54:33.84#ibcon#enter sib2, iclass 35, count 0 2006.285.14:54:33.84#ibcon#flushed, iclass 35, count 0 2006.285.14:54:33.84#ibcon#about to write, iclass 35, count 0 2006.285.14:54:33.84#ibcon#wrote, iclass 35, count 0 2006.285.14:54:33.84#ibcon#about to read 3, iclass 35, count 0 2006.285.14:54:33.87#ibcon#read 3, iclass 35, count 0 2006.285.14:54:33.87#ibcon#about to read 4, iclass 35, count 0 2006.285.14:54:33.87#ibcon#read 4, iclass 35, count 0 2006.285.14:54:33.87#ibcon#about to read 5, iclass 35, count 0 2006.285.14:54:33.87#ibcon#read 5, iclass 35, count 0 2006.285.14:54:33.87#ibcon#about to read 6, iclass 35, count 0 2006.285.14:54:33.87#ibcon#read 6, iclass 35, count 0 2006.285.14:54:33.87#ibcon#end of sib2, iclass 35, count 0 2006.285.14:54:33.87#ibcon#*after write, iclass 35, count 0 2006.285.14:54:33.87#ibcon#*before return 0, iclass 35, count 0 2006.285.14:54:33.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:54:33.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.14:54:33.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.14:54:33.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.14:54:33.87$vck44/vblo=1,629.99 2006.285.14:54:33.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.14:54:33.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.14:54:33.87#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:33.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:54:33.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:54:33.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:54:33.87#ibcon#enter wrdev, iclass 37, count 0 2006.285.14:54:33.87#ibcon#first serial, iclass 37, count 0 2006.285.14:54:33.87#ibcon#enter sib2, iclass 37, count 0 2006.285.14:54:33.87#ibcon#flushed, iclass 37, count 0 2006.285.14:54:33.87#ibcon#about to write, iclass 37, count 0 2006.285.14:54:33.87#ibcon#wrote, iclass 37, count 0 2006.285.14:54:33.87#ibcon#about to read 3, iclass 37, count 0 2006.285.14:54:33.89#ibcon#read 3, iclass 37, count 0 2006.285.14:54:33.89#ibcon#about to read 4, iclass 37, count 0 2006.285.14:54:33.89#ibcon#read 4, iclass 37, count 0 2006.285.14:54:33.89#ibcon#about to read 5, iclass 37, count 0 2006.285.14:54:33.89#ibcon#read 5, iclass 37, count 0 2006.285.14:54:33.89#ibcon#about to read 6, iclass 37, count 0 2006.285.14:54:33.89#ibcon#read 6, iclass 37, count 0 2006.285.14:54:33.89#ibcon#end of sib2, iclass 37, count 0 2006.285.14:54:33.89#ibcon#*mode == 0, iclass 37, count 0 2006.285.14:54:33.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.14:54:33.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.14:54:33.89#ibcon#*before write, iclass 37, count 0 2006.285.14:54:33.89#ibcon#enter sib2, iclass 37, count 0 2006.285.14:54:33.89#ibcon#flushed, iclass 37, count 0 2006.285.14:54:33.89#ibcon#about to write, iclass 37, count 0 2006.285.14:54:33.89#ibcon#wrote, iclass 37, count 0 2006.285.14:54:33.89#ibcon#about to read 3, iclass 37, count 0 2006.285.14:54:33.93#ibcon#read 3, iclass 37, count 0 2006.285.14:54:33.93#ibcon#about to read 4, iclass 37, count 0 2006.285.14:54:33.93#ibcon#read 4, iclass 37, count 0 2006.285.14:54:33.93#ibcon#about to read 5, iclass 37, count 0 2006.285.14:54:33.93#ibcon#read 5, iclass 37, count 0 2006.285.14:54:33.93#ibcon#about to read 6, iclass 37, count 0 2006.285.14:54:33.93#ibcon#read 6, iclass 37, count 0 2006.285.14:54:33.93#ibcon#end of sib2, iclass 37, count 0 2006.285.14:54:33.93#ibcon#*after write, iclass 37, count 0 2006.285.14:54:33.93#ibcon#*before return 0, iclass 37, count 0 2006.285.14:54:33.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:54:33.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.14:54:33.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.14:54:33.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.14:54:33.93$vck44/vb=1,4 2006.285.14:54:33.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.14:54:33.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.14:54:33.93#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:33.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:54:33.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:54:33.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:54:33.93#ibcon#enter wrdev, iclass 39, count 2 2006.285.14:54:33.93#ibcon#first serial, iclass 39, count 2 2006.285.14:54:33.93#ibcon#enter sib2, iclass 39, count 2 2006.285.14:54:33.93#ibcon#flushed, iclass 39, count 2 2006.285.14:54:33.93#ibcon#about to write, iclass 39, count 2 2006.285.14:54:33.93#ibcon#wrote, iclass 39, count 2 2006.285.14:54:33.93#ibcon#about to read 3, iclass 39, count 2 2006.285.14:54:33.95#ibcon#read 3, iclass 39, count 2 2006.285.14:54:33.95#ibcon#about to read 4, iclass 39, count 2 2006.285.14:54:33.95#ibcon#read 4, iclass 39, count 2 2006.285.14:54:33.95#ibcon#about to read 5, iclass 39, count 2 2006.285.14:54:33.95#ibcon#read 5, iclass 39, count 2 2006.285.14:54:33.95#ibcon#about to read 6, iclass 39, count 2 2006.285.14:54:33.95#ibcon#read 6, iclass 39, count 2 2006.285.14:54:33.95#ibcon#end of sib2, iclass 39, count 2 2006.285.14:54:33.95#ibcon#*mode == 0, iclass 39, count 2 2006.285.14:54:33.95#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.14:54:33.95#ibcon#[27=AT01-04\r\n] 2006.285.14:54:33.95#ibcon#*before write, iclass 39, count 2 2006.285.14:54:33.95#ibcon#enter sib2, iclass 39, count 2 2006.285.14:54:33.95#ibcon#flushed, iclass 39, count 2 2006.285.14:54:33.95#ibcon#about to write, iclass 39, count 2 2006.285.14:54:33.95#ibcon#wrote, iclass 39, count 2 2006.285.14:54:33.95#ibcon#about to read 3, iclass 39, count 2 2006.285.14:54:33.98#ibcon#read 3, iclass 39, count 2 2006.285.14:54:33.98#ibcon#about to read 4, iclass 39, count 2 2006.285.14:54:33.98#ibcon#read 4, iclass 39, count 2 2006.285.14:54:33.98#ibcon#about to read 5, iclass 39, count 2 2006.285.14:54:33.98#ibcon#read 5, iclass 39, count 2 2006.285.14:54:33.98#ibcon#about to read 6, iclass 39, count 2 2006.285.14:54:33.98#ibcon#read 6, iclass 39, count 2 2006.285.14:54:33.98#ibcon#end of sib2, iclass 39, count 2 2006.285.14:54:33.98#ibcon#*after write, iclass 39, count 2 2006.285.14:54:33.98#ibcon#*before return 0, iclass 39, count 2 2006.285.14:54:33.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:54:33.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.14:54:33.98#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.14:54:33.98#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:33.98#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:54:34.10#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:54:34.10#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:54:34.10#ibcon#enter wrdev, iclass 39, count 0 2006.285.14:54:34.10#ibcon#first serial, iclass 39, count 0 2006.285.14:54:34.10#ibcon#enter sib2, iclass 39, count 0 2006.285.14:54:34.10#ibcon#flushed, iclass 39, count 0 2006.285.14:54:34.10#ibcon#about to write, iclass 39, count 0 2006.285.14:54:34.10#ibcon#wrote, iclass 39, count 0 2006.285.14:54:34.10#ibcon#about to read 3, iclass 39, count 0 2006.285.14:54:34.12#ibcon#read 3, iclass 39, count 0 2006.285.14:54:34.12#ibcon#about to read 4, iclass 39, count 0 2006.285.14:54:34.12#ibcon#read 4, iclass 39, count 0 2006.285.14:54:34.12#ibcon#about to read 5, iclass 39, count 0 2006.285.14:54:34.12#ibcon#read 5, iclass 39, count 0 2006.285.14:54:34.12#ibcon#about to read 6, iclass 39, count 0 2006.285.14:54:34.12#ibcon#read 6, iclass 39, count 0 2006.285.14:54:34.12#ibcon#end of sib2, iclass 39, count 0 2006.285.14:54:34.12#ibcon#*mode == 0, iclass 39, count 0 2006.285.14:54:34.12#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.14:54:34.12#ibcon#[27=USB\r\n] 2006.285.14:54:34.12#ibcon#*before write, iclass 39, count 0 2006.285.14:54:34.12#ibcon#enter sib2, iclass 39, count 0 2006.285.14:54:34.12#ibcon#flushed, iclass 39, count 0 2006.285.14:54:34.12#ibcon#about to write, iclass 39, count 0 2006.285.14:54:34.12#ibcon#wrote, iclass 39, count 0 2006.285.14:54:34.12#ibcon#about to read 3, iclass 39, count 0 2006.285.14:54:34.15#ibcon#read 3, iclass 39, count 0 2006.285.14:54:34.15#ibcon#about to read 4, iclass 39, count 0 2006.285.14:54:34.15#ibcon#read 4, iclass 39, count 0 2006.285.14:54:34.15#ibcon#about to read 5, iclass 39, count 0 2006.285.14:54:34.15#ibcon#read 5, iclass 39, count 0 2006.285.14:54:34.15#ibcon#about to read 6, iclass 39, count 0 2006.285.14:54:34.15#ibcon#read 6, iclass 39, count 0 2006.285.14:54:34.15#ibcon#end of sib2, iclass 39, count 0 2006.285.14:54:34.15#ibcon#*after write, iclass 39, count 0 2006.285.14:54:34.15#ibcon#*before return 0, iclass 39, count 0 2006.285.14:54:34.15#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:54:34.15#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.14:54:34.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.14:54:34.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.14:54:34.15$vck44/vblo=2,634.99 2006.285.14:54:34.15#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.14:54:34.15#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.14:54:34.15#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:34.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:54:34.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:54:34.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:54:34.15#ibcon#enter wrdev, iclass 3, count 0 2006.285.14:54:34.15#ibcon#first serial, iclass 3, count 0 2006.285.14:54:34.15#ibcon#enter sib2, iclass 3, count 0 2006.285.14:54:34.15#ibcon#flushed, iclass 3, count 0 2006.285.14:54:34.15#ibcon#about to write, iclass 3, count 0 2006.285.14:54:34.15#ibcon#wrote, iclass 3, count 0 2006.285.14:54:34.15#ibcon#about to read 3, iclass 3, count 0 2006.285.14:54:34.17#ibcon#read 3, iclass 3, count 0 2006.285.14:54:34.17#ibcon#about to read 4, iclass 3, count 0 2006.285.14:54:34.17#ibcon#read 4, iclass 3, count 0 2006.285.14:54:34.17#ibcon#about to read 5, iclass 3, count 0 2006.285.14:54:34.17#ibcon#read 5, iclass 3, count 0 2006.285.14:54:34.17#ibcon#about to read 6, iclass 3, count 0 2006.285.14:54:34.17#ibcon#read 6, iclass 3, count 0 2006.285.14:54:34.17#ibcon#end of sib2, iclass 3, count 0 2006.285.14:54:34.17#ibcon#*mode == 0, iclass 3, count 0 2006.285.14:54:34.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.14:54:34.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.14:54:34.17#ibcon#*before write, iclass 3, count 0 2006.285.14:54:34.17#ibcon#enter sib2, iclass 3, count 0 2006.285.14:54:34.17#ibcon#flushed, iclass 3, count 0 2006.285.14:54:34.17#ibcon#about to write, iclass 3, count 0 2006.285.14:54:34.17#ibcon#wrote, iclass 3, count 0 2006.285.14:54:34.17#ibcon#about to read 3, iclass 3, count 0 2006.285.14:54:34.21#ibcon#read 3, iclass 3, count 0 2006.285.14:54:34.21#ibcon#about to read 4, iclass 3, count 0 2006.285.14:54:34.21#ibcon#read 4, iclass 3, count 0 2006.285.14:54:34.21#ibcon#about to read 5, iclass 3, count 0 2006.285.14:54:34.21#ibcon#read 5, iclass 3, count 0 2006.285.14:54:34.21#ibcon#about to read 6, iclass 3, count 0 2006.285.14:54:34.21#ibcon#read 6, iclass 3, count 0 2006.285.14:54:34.21#ibcon#end of sib2, iclass 3, count 0 2006.285.14:54:34.21#ibcon#*after write, iclass 3, count 0 2006.285.14:54:34.21#ibcon#*before return 0, iclass 3, count 0 2006.285.14:54:34.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:54:34.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.14:54:34.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.14:54:34.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.14:54:34.21$vck44/vb=2,5 2006.285.14:54:34.21#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.14:54:34.21#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.14:54:34.21#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:34.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:54:34.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:54:34.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:54:34.27#ibcon#enter wrdev, iclass 5, count 2 2006.285.14:54:34.27#ibcon#first serial, iclass 5, count 2 2006.285.14:54:34.27#ibcon#enter sib2, iclass 5, count 2 2006.285.14:54:34.27#ibcon#flushed, iclass 5, count 2 2006.285.14:54:34.27#ibcon#about to write, iclass 5, count 2 2006.285.14:54:34.27#ibcon#wrote, iclass 5, count 2 2006.285.14:54:34.27#ibcon#about to read 3, iclass 5, count 2 2006.285.14:54:34.29#ibcon#read 3, iclass 5, count 2 2006.285.14:54:34.29#ibcon#about to read 4, iclass 5, count 2 2006.285.14:54:34.29#ibcon#read 4, iclass 5, count 2 2006.285.14:54:34.29#ibcon#about to read 5, iclass 5, count 2 2006.285.14:54:34.29#ibcon#read 5, iclass 5, count 2 2006.285.14:54:34.29#ibcon#about to read 6, iclass 5, count 2 2006.285.14:54:34.29#ibcon#read 6, iclass 5, count 2 2006.285.14:54:34.29#ibcon#end of sib2, iclass 5, count 2 2006.285.14:54:34.29#ibcon#*mode == 0, iclass 5, count 2 2006.285.14:54:34.29#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.14:54:34.29#ibcon#[27=AT02-05\r\n] 2006.285.14:54:34.29#ibcon#*before write, iclass 5, count 2 2006.285.14:54:34.29#ibcon#enter sib2, iclass 5, count 2 2006.285.14:54:34.29#ibcon#flushed, iclass 5, count 2 2006.285.14:54:34.29#ibcon#about to write, iclass 5, count 2 2006.285.14:54:34.29#ibcon#wrote, iclass 5, count 2 2006.285.14:54:34.29#ibcon#about to read 3, iclass 5, count 2 2006.285.14:54:34.32#ibcon#read 3, iclass 5, count 2 2006.285.14:54:34.32#ibcon#about to read 4, iclass 5, count 2 2006.285.14:54:34.32#ibcon#read 4, iclass 5, count 2 2006.285.14:54:34.32#ibcon#about to read 5, iclass 5, count 2 2006.285.14:54:34.32#ibcon#read 5, iclass 5, count 2 2006.285.14:54:34.32#ibcon#about to read 6, iclass 5, count 2 2006.285.14:54:34.32#ibcon#read 6, iclass 5, count 2 2006.285.14:54:34.32#ibcon#end of sib2, iclass 5, count 2 2006.285.14:54:34.32#ibcon#*after write, iclass 5, count 2 2006.285.14:54:34.32#ibcon#*before return 0, iclass 5, count 2 2006.285.14:54:34.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:54:34.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.14:54:34.32#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.14:54:34.32#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:34.32#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:54:34.44#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:54:34.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:54:34.53#ibcon#enter wrdev, iclass 5, count 0 2006.285.14:54:34.53#ibcon#first serial, iclass 5, count 0 2006.285.14:54:34.53#ibcon#enter sib2, iclass 5, count 0 2006.285.14:54:34.53#ibcon#flushed, iclass 5, count 0 2006.285.14:54:34.53#ibcon#about to write, iclass 5, count 0 2006.285.14:54:34.53#ibcon#wrote, iclass 5, count 0 2006.285.14:54:34.53#ibcon#about to read 3, iclass 5, count 0 2006.285.14:54:34.54#ibcon#read 3, iclass 5, count 0 2006.285.14:54:34.54#ibcon#about to read 4, iclass 5, count 0 2006.285.14:54:34.54#ibcon#read 4, iclass 5, count 0 2006.285.14:54:34.54#ibcon#about to read 5, iclass 5, count 0 2006.285.14:54:34.54#ibcon#read 5, iclass 5, count 0 2006.285.14:54:34.54#ibcon#about to read 6, iclass 5, count 0 2006.285.14:54:34.54#ibcon#read 6, iclass 5, count 0 2006.285.14:54:34.54#ibcon#end of sib2, iclass 5, count 0 2006.285.14:54:34.54#ibcon#*mode == 0, iclass 5, count 0 2006.285.14:54:34.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.14:54:34.54#ibcon#[27=USB\r\n] 2006.285.14:54:34.54#ibcon#*before write, iclass 5, count 0 2006.285.14:54:34.54#ibcon#enter sib2, iclass 5, count 0 2006.285.14:54:34.54#ibcon#flushed, iclass 5, count 0 2006.285.14:54:34.54#ibcon#about to write, iclass 5, count 0 2006.285.14:54:34.54#ibcon#wrote, iclass 5, count 0 2006.285.14:54:34.54#ibcon#about to read 3, iclass 5, count 0 2006.285.14:54:34.57#ibcon#read 3, iclass 5, count 0 2006.285.14:54:34.57#ibcon#about to read 4, iclass 5, count 0 2006.285.14:54:34.57#ibcon#read 4, iclass 5, count 0 2006.285.14:54:34.57#ibcon#about to read 5, iclass 5, count 0 2006.285.14:54:34.57#ibcon#read 5, iclass 5, count 0 2006.285.14:54:34.57#ibcon#about to read 6, iclass 5, count 0 2006.285.14:54:34.57#ibcon#read 6, iclass 5, count 0 2006.285.14:54:34.57#ibcon#end of sib2, iclass 5, count 0 2006.285.14:54:34.57#ibcon#*after write, iclass 5, count 0 2006.285.14:54:34.57#ibcon#*before return 0, iclass 5, count 0 2006.285.14:54:34.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:54:34.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.14:54:34.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.14:54:34.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.14:54:34.57$vck44/vblo=3,649.99 2006.285.14:54:34.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.14:54:34.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.14:54:34.57#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:34.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:54:34.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:54:34.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:54:34.57#ibcon#enter wrdev, iclass 7, count 0 2006.285.14:54:34.57#ibcon#first serial, iclass 7, count 0 2006.285.14:54:34.57#ibcon#enter sib2, iclass 7, count 0 2006.285.14:54:34.57#ibcon#flushed, iclass 7, count 0 2006.285.14:54:34.57#ibcon#about to write, iclass 7, count 0 2006.285.14:54:34.57#ibcon#wrote, iclass 7, count 0 2006.285.14:54:34.57#ibcon#about to read 3, iclass 7, count 0 2006.285.14:54:34.59#ibcon#read 3, iclass 7, count 0 2006.285.14:54:34.59#ibcon#about to read 4, iclass 7, count 0 2006.285.14:54:34.59#ibcon#read 4, iclass 7, count 0 2006.285.14:54:34.59#ibcon#about to read 5, iclass 7, count 0 2006.285.14:54:34.59#ibcon#read 5, iclass 7, count 0 2006.285.14:54:34.59#ibcon#about to read 6, iclass 7, count 0 2006.285.14:54:34.59#ibcon#read 6, iclass 7, count 0 2006.285.14:54:34.59#ibcon#end of sib2, iclass 7, count 0 2006.285.14:54:34.59#ibcon#*mode == 0, iclass 7, count 0 2006.285.14:54:34.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.14:54:34.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.14:54:34.59#ibcon#*before write, iclass 7, count 0 2006.285.14:54:34.59#ibcon#enter sib2, iclass 7, count 0 2006.285.14:54:34.59#ibcon#flushed, iclass 7, count 0 2006.285.14:54:34.59#ibcon#about to write, iclass 7, count 0 2006.285.14:54:34.59#ibcon#wrote, iclass 7, count 0 2006.285.14:54:34.59#ibcon#about to read 3, iclass 7, count 0 2006.285.14:54:34.63#ibcon#read 3, iclass 7, count 0 2006.285.14:54:34.63#ibcon#about to read 4, iclass 7, count 0 2006.285.14:54:34.63#ibcon#read 4, iclass 7, count 0 2006.285.14:54:34.63#ibcon#about to read 5, iclass 7, count 0 2006.285.14:54:34.63#ibcon#read 5, iclass 7, count 0 2006.285.14:54:34.63#ibcon#about to read 6, iclass 7, count 0 2006.285.14:54:34.63#ibcon#read 6, iclass 7, count 0 2006.285.14:54:34.63#ibcon#end of sib2, iclass 7, count 0 2006.285.14:54:34.63#ibcon#*after write, iclass 7, count 0 2006.285.14:54:34.63#ibcon#*before return 0, iclass 7, count 0 2006.285.14:54:34.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:54:34.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.14:54:34.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.14:54:34.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.14:54:34.63$vck44/vb=3,4 2006.285.14:54:34.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.14:54:34.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.14:54:34.63#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:34.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:54:34.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:54:34.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:54:34.69#ibcon#enter wrdev, iclass 11, count 2 2006.285.14:54:34.69#ibcon#first serial, iclass 11, count 2 2006.285.14:54:34.69#ibcon#enter sib2, iclass 11, count 2 2006.285.14:54:34.69#ibcon#flushed, iclass 11, count 2 2006.285.14:54:34.69#ibcon#about to write, iclass 11, count 2 2006.285.14:54:34.69#ibcon#wrote, iclass 11, count 2 2006.285.14:54:34.69#ibcon#about to read 3, iclass 11, count 2 2006.285.14:54:34.71#ibcon#read 3, iclass 11, count 2 2006.285.14:54:34.71#ibcon#about to read 4, iclass 11, count 2 2006.285.14:54:34.71#ibcon#read 4, iclass 11, count 2 2006.285.14:54:34.71#ibcon#about to read 5, iclass 11, count 2 2006.285.14:54:34.71#ibcon#read 5, iclass 11, count 2 2006.285.14:54:34.71#ibcon#about to read 6, iclass 11, count 2 2006.285.14:54:34.71#ibcon#read 6, iclass 11, count 2 2006.285.14:54:34.71#ibcon#end of sib2, iclass 11, count 2 2006.285.14:54:34.71#ibcon#*mode == 0, iclass 11, count 2 2006.285.14:54:34.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.14:54:34.71#ibcon#[27=AT03-04\r\n] 2006.285.14:54:34.71#ibcon#*before write, iclass 11, count 2 2006.285.14:54:34.71#ibcon#enter sib2, iclass 11, count 2 2006.285.14:54:34.71#ibcon#flushed, iclass 11, count 2 2006.285.14:54:34.71#ibcon#about to write, iclass 11, count 2 2006.285.14:54:34.71#ibcon#wrote, iclass 11, count 2 2006.285.14:54:34.71#ibcon#about to read 3, iclass 11, count 2 2006.285.14:54:34.74#ibcon#read 3, iclass 11, count 2 2006.285.14:54:34.74#ibcon#about to read 4, iclass 11, count 2 2006.285.14:54:34.74#ibcon#read 4, iclass 11, count 2 2006.285.14:54:34.74#ibcon#about to read 5, iclass 11, count 2 2006.285.14:54:34.74#ibcon#read 5, iclass 11, count 2 2006.285.14:54:34.74#ibcon#about to read 6, iclass 11, count 2 2006.285.14:54:34.74#ibcon#read 6, iclass 11, count 2 2006.285.14:54:34.74#ibcon#end of sib2, iclass 11, count 2 2006.285.14:54:34.74#ibcon#*after write, iclass 11, count 2 2006.285.14:54:34.74#ibcon#*before return 0, iclass 11, count 2 2006.285.14:54:34.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:54:34.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.14:54:34.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.14:54:34.74#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:34.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:54:34.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:54:34.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:54:34.86#ibcon#enter wrdev, iclass 11, count 0 2006.285.14:54:34.86#ibcon#first serial, iclass 11, count 0 2006.285.14:54:34.86#ibcon#enter sib2, iclass 11, count 0 2006.285.14:54:34.86#ibcon#flushed, iclass 11, count 0 2006.285.14:54:34.86#ibcon#about to write, iclass 11, count 0 2006.285.14:54:34.86#ibcon#wrote, iclass 11, count 0 2006.285.14:54:34.86#ibcon#about to read 3, iclass 11, count 0 2006.285.14:54:34.88#ibcon#read 3, iclass 11, count 0 2006.285.14:54:34.88#ibcon#about to read 4, iclass 11, count 0 2006.285.14:54:34.88#ibcon#read 4, iclass 11, count 0 2006.285.14:54:34.88#ibcon#about to read 5, iclass 11, count 0 2006.285.14:54:34.88#ibcon#read 5, iclass 11, count 0 2006.285.14:54:34.88#ibcon#about to read 6, iclass 11, count 0 2006.285.14:54:34.88#ibcon#read 6, iclass 11, count 0 2006.285.14:54:34.88#ibcon#end of sib2, iclass 11, count 0 2006.285.14:54:34.88#ibcon#*mode == 0, iclass 11, count 0 2006.285.14:54:34.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.14:54:34.88#ibcon#[27=USB\r\n] 2006.285.14:54:34.88#ibcon#*before write, iclass 11, count 0 2006.285.14:54:34.88#ibcon#enter sib2, iclass 11, count 0 2006.285.14:54:34.88#ibcon#flushed, iclass 11, count 0 2006.285.14:54:34.88#ibcon#about to write, iclass 11, count 0 2006.285.14:54:34.88#ibcon#wrote, iclass 11, count 0 2006.285.14:54:34.88#ibcon#about to read 3, iclass 11, count 0 2006.285.14:54:34.91#ibcon#read 3, iclass 11, count 0 2006.285.14:54:34.91#ibcon#about to read 4, iclass 11, count 0 2006.285.14:54:34.91#ibcon#read 4, iclass 11, count 0 2006.285.14:54:34.91#ibcon#about to read 5, iclass 11, count 0 2006.285.14:54:34.91#ibcon#read 5, iclass 11, count 0 2006.285.14:54:34.91#ibcon#about to read 6, iclass 11, count 0 2006.285.14:54:34.91#ibcon#read 6, iclass 11, count 0 2006.285.14:54:34.91#ibcon#end of sib2, iclass 11, count 0 2006.285.14:54:34.91#ibcon#*after write, iclass 11, count 0 2006.285.14:54:34.91#ibcon#*before return 0, iclass 11, count 0 2006.285.14:54:34.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:54:34.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.14:54:34.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.14:54:34.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.14:54:34.91$vck44/vblo=4,679.99 2006.285.14:54:34.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.14:54:34.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.14:54:34.91#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:34.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:54:34.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:54:34.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:54:34.91#ibcon#enter wrdev, iclass 13, count 0 2006.285.14:54:34.91#ibcon#first serial, iclass 13, count 0 2006.285.14:54:34.91#ibcon#enter sib2, iclass 13, count 0 2006.285.14:54:34.91#ibcon#flushed, iclass 13, count 0 2006.285.14:54:34.91#ibcon#about to write, iclass 13, count 0 2006.285.14:54:34.91#ibcon#wrote, iclass 13, count 0 2006.285.14:54:34.91#ibcon#about to read 3, iclass 13, count 0 2006.285.14:54:34.93#ibcon#read 3, iclass 13, count 0 2006.285.14:54:34.93#ibcon#about to read 4, iclass 13, count 0 2006.285.14:54:34.93#ibcon#read 4, iclass 13, count 0 2006.285.14:54:34.93#ibcon#about to read 5, iclass 13, count 0 2006.285.14:54:34.93#ibcon#read 5, iclass 13, count 0 2006.285.14:54:34.93#ibcon#about to read 6, iclass 13, count 0 2006.285.14:54:34.93#ibcon#read 6, iclass 13, count 0 2006.285.14:54:34.93#ibcon#end of sib2, iclass 13, count 0 2006.285.14:54:34.93#ibcon#*mode == 0, iclass 13, count 0 2006.285.14:54:34.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.14:54:34.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.14:54:34.93#ibcon#*before write, iclass 13, count 0 2006.285.14:54:34.93#ibcon#enter sib2, iclass 13, count 0 2006.285.14:54:34.93#ibcon#flushed, iclass 13, count 0 2006.285.14:54:34.93#ibcon#about to write, iclass 13, count 0 2006.285.14:54:34.93#ibcon#wrote, iclass 13, count 0 2006.285.14:54:34.93#ibcon#about to read 3, iclass 13, count 0 2006.285.14:54:34.97#ibcon#read 3, iclass 13, count 0 2006.285.14:54:34.97#ibcon#about to read 4, iclass 13, count 0 2006.285.14:54:34.97#ibcon#read 4, iclass 13, count 0 2006.285.14:54:34.97#ibcon#about to read 5, iclass 13, count 0 2006.285.14:54:34.97#ibcon#read 5, iclass 13, count 0 2006.285.14:54:34.97#ibcon#about to read 6, iclass 13, count 0 2006.285.14:54:34.97#ibcon#read 6, iclass 13, count 0 2006.285.14:54:34.97#ibcon#end of sib2, iclass 13, count 0 2006.285.14:54:34.97#ibcon#*after write, iclass 13, count 0 2006.285.14:54:34.97#ibcon#*before return 0, iclass 13, count 0 2006.285.14:54:34.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:54:34.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.14:54:34.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.14:54:34.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.14:54:34.97$vck44/vb=4,5 2006.285.14:54:34.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.14:54:34.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.14:54:34.97#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:34.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:54:35.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:54:35.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:54:35.03#ibcon#enter wrdev, iclass 15, count 2 2006.285.14:54:35.03#ibcon#first serial, iclass 15, count 2 2006.285.14:54:35.03#ibcon#enter sib2, iclass 15, count 2 2006.285.14:54:35.03#ibcon#flushed, iclass 15, count 2 2006.285.14:54:35.03#ibcon#about to write, iclass 15, count 2 2006.285.14:54:35.03#ibcon#wrote, iclass 15, count 2 2006.285.14:54:35.03#ibcon#about to read 3, iclass 15, count 2 2006.285.14:54:35.05#ibcon#read 3, iclass 15, count 2 2006.285.14:54:35.05#ibcon#about to read 4, iclass 15, count 2 2006.285.14:54:35.05#ibcon#read 4, iclass 15, count 2 2006.285.14:54:35.05#ibcon#about to read 5, iclass 15, count 2 2006.285.14:54:35.05#ibcon#read 5, iclass 15, count 2 2006.285.14:54:35.05#ibcon#about to read 6, iclass 15, count 2 2006.285.14:54:35.05#ibcon#read 6, iclass 15, count 2 2006.285.14:54:35.05#ibcon#end of sib2, iclass 15, count 2 2006.285.14:54:35.05#ibcon#*mode == 0, iclass 15, count 2 2006.285.14:54:35.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.14:54:35.05#ibcon#[27=AT04-05\r\n] 2006.285.14:54:35.05#ibcon#*before write, iclass 15, count 2 2006.285.14:54:35.05#ibcon#enter sib2, iclass 15, count 2 2006.285.14:54:35.05#ibcon#flushed, iclass 15, count 2 2006.285.14:54:35.05#ibcon#about to write, iclass 15, count 2 2006.285.14:54:35.05#ibcon#wrote, iclass 15, count 2 2006.285.14:54:35.05#ibcon#about to read 3, iclass 15, count 2 2006.285.14:54:35.08#ibcon#read 3, iclass 15, count 2 2006.285.14:54:35.08#ibcon#about to read 4, iclass 15, count 2 2006.285.14:54:35.08#ibcon#read 4, iclass 15, count 2 2006.285.14:54:35.08#ibcon#about to read 5, iclass 15, count 2 2006.285.14:54:35.08#ibcon#read 5, iclass 15, count 2 2006.285.14:54:35.08#ibcon#about to read 6, iclass 15, count 2 2006.285.14:54:35.08#ibcon#read 6, iclass 15, count 2 2006.285.14:54:35.08#ibcon#end of sib2, iclass 15, count 2 2006.285.14:54:35.08#ibcon#*after write, iclass 15, count 2 2006.285.14:54:35.08#ibcon#*before return 0, iclass 15, count 2 2006.285.14:54:35.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:54:35.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.14:54:35.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.14:54:35.08#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:35.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:54:35.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:54:35.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:54:35.20#ibcon#enter wrdev, iclass 15, count 0 2006.285.14:54:35.20#ibcon#first serial, iclass 15, count 0 2006.285.14:54:35.20#ibcon#enter sib2, iclass 15, count 0 2006.285.14:54:35.20#ibcon#flushed, iclass 15, count 0 2006.285.14:54:35.20#ibcon#about to write, iclass 15, count 0 2006.285.14:54:35.20#ibcon#wrote, iclass 15, count 0 2006.285.14:54:35.20#ibcon#about to read 3, iclass 15, count 0 2006.285.14:54:35.22#ibcon#read 3, iclass 15, count 0 2006.285.14:54:35.22#ibcon#about to read 4, iclass 15, count 0 2006.285.14:54:35.22#ibcon#read 4, iclass 15, count 0 2006.285.14:54:35.22#ibcon#about to read 5, iclass 15, count 0 2006.285.14:54:35.22#ibcon#read 5, iclass 15, count 0 2006.285.14:54:35.22#ibcon#about to read 6, iclass 15, count 0 2006.285.14:54:35.22#ibcon#read 6, iclass 15, count 0 2006.285.14:54:35.22#ibcon#end of sib2, iclass 15, count 0 2006.285.14:54:35.22#ibcon#*mode == 0, iclass 15, count 0 2006.285.14:54:35.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.14:54:35.22#ibcon#[27=USB\r\n] 2006.285.14:54:35.22#ibcon#*before write, iclass 15, count 0 2006.285.14:54:35.22#ibcon#enter sib2, iclass 15, count 0 2006.285.14:54:35.22#ibcon#flushed, iclass 15, count 0 2006.285.14:54:35.22#ibcon#about to write, iclass 15, count 0 2006.285.14:54:35.22#ibcon#wrote, iclass 15, count 0 2006.285.14:54:35.22#ibcon#about to read 3, iclass 15, count 0 2006.285.14:54:35.25#ibcon#read 3, iclass 15, count 0 2006.285.14:54:35.25#ibcon#about to read 4, iclass 15, count 0 2006.285.14:54:35.25#ibcon#read 4, iclass 15, count 0 2006.285.14:54:35.25#ibcon#about to read 5, iclass 15, count 0 2006.285.14:54:35.25#ibcon#read 5, iclass 15, count 0 2006.285.14:54:35.25#ibcon#about to read 6, iclass 15, count 0 2006.285.14:54:35.25#ibcon#read 6, iclass 15, count 0 2006.285.14:54:35.25#ibcon#end of sib2, iclass 15, count 0 2006.285.14:54:35.25#ibcon#*after write, iclass 15, count 0 2006.285.14:54:35.25#ibcon#*before return 0, iclass 15, count 0 2006.285.14:54:35.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:54:35.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.14:54:35.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.14:54:35.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.14:54:35.25$vck44/vblo=5,709.99 2006.285.14:54:35.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.14:54:35.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.14:54:35.25#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:35.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:54:35.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:54:35.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:54:35.25#ibcon#enter wrdev, iclass 17, count 0 2006.285.14:54:35.25#ibcon#first serial, iclass 17, count 0 2006.285.14:54:35.25#ibcon#enter sib2, iclass 17, count 0 2006.285.14:54:35.25#ibcon#flushed, iclass 17, count 0 2006.285.14:54:35.25#ibcon#about to write, iclass 17, count 0 2006.285.14:54:35.25#ibcon#wrote, iclass 17, count 0 2006.285.14:54:35.25#ibcon#about to read 3, iclass 17, count 0 2006.285.14:54:35.27#ibcon#read 3, iclass 17, count 0 2006.285.14:54:35.27#ibcon#about to read 4, iclass 17, count 0 2006.285.14:54:35.27#ibcon#read 4, iclass 17, count 0 2006.285.14:54:35.27#ibcon#about to read 5, iclass 17, count 0 2006.285.14:54:35.27#ibcon#read 5, iclass 17, count 0 2006.285.14:54:35.27#ibcon#about to read 6, iclass 17, count 0 2006.285.14:54:35.27#ibcon#read 6, iclass 17, count 0 2006.285.14:54:35.27#ibcon#end of sib2, iclass 17, count 0 2006.285.14:54:35.27#ibcon#*mode == 0, iclass 17, count 0 2006.285.14:54:35.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.14:54:35.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.14:54:35.27#ibcon#*before write, iclass 17, count 0 2006.285.14:54:35.27#ibcon#enter sib2, iclass 17, count 0 2006.285.14:54:35.27#ibcon#flushed, iclass 17, count 0 2006.285.14:54:35.27#ibcon#about to write, iclass 17, count 0 2006.285.14:54:35.27#ibcon#wrote, iclass 17, count 0 2006.285.14:54:35.27#ibcon#about to read 3, iclass 17, count 0 2006.285.14:54:35.31#ibcon#read 3, iclass 17, count 0 2006.285.14:54:35.31#ibcon#about to read 4, iclass 17, count 0 2006.285.14:54:35.31#ibcon#read 4, iclass 17, count 0 2006.285.14:54:35.31#ibcon#about to read 5, iclass 17, count 0 2006.285.14:54:35.31#ibcon#read 5, iclass 17, count 0 2006.285.14:54:35.31#ibcon#about to read 6, iclass 17, count 0 2006.285.14:54:35.31#ibcon#read 6, iclass 17, count 0 2006.285.14:54:35.31#ibcon#end of sib2, iclass 17, count 0 2006.285.14:54:35.31#ibcon#*after write, iclass 17, count 0 2006.285.14:54:35.31#ibcon#*before return 0, iclass 17, count 0 2006.285.14:54:35.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:54:35.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.14:54:35.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.14:54:35.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.14:54:35.31$vck44/vb=5,4 2006.285.14:54:35.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.14:54:35.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.14:54:35.31#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:35.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:54:35.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:54:35.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:54:35.37#ibcon#enter wrdev, iclass 19, count 2 2006.285.14:54:35.37#ibcon#first serial, iclass 19, count 2 2006.285.14:54:35.37#ibcon#enter sib2, iclass 19, count 2 2006.285.14:54:35.37#ibcon#flushed, iclass 19, count 2 2006.285.14:54:35.37#ibcon#about to write, iclass 19, count 2 2006.285.14:54:35.37#ibcon#wrote, iclass 19, count 2 2006.285.14:54:35.37#ibcon#about to read 3, iclass 19, count 2 2006.285.14:54:35.39#ibcon#read 3, iclass 19, count 2 2006.285.14:54:35.45#ibcon#about to read 4, iclass 19, count 2 2006.285.14:54:35.45#ibcon#read 4, iclass 19, count 2 2006.285.14:54:35.45#ibcon#about to read 5, iclass 19, count 2 2006.285.14:54:35.45#ibcon#read 5, iclass 19, count 2 2006.285.14:54:35.45#ibcon#about to read 6, iclass 19, count 2 2006.285.14:54:35.45#ibcon#read 6, iclass 19, count 2 2006.285.14:54:35.45#ibcon#end of sib2, iclass 19, count 2 2006.285.14:54:35.45#ibcon#*mode == 0, iclass 19, count 2 2006.285.14:54:35.45#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.14:54:35.45#ibcon#[27=AT05-04\r\n] 2006.285.14:54:35.45#ibcon#*before write, iclass 19, count 2 2006.285.14:54:35.45#ibcon#enter sib2, iclass 19, count 2 2006.285.14:54:35.45#ibcon#flushed, iclass 19, count 2 2006.285.14:54:35.45#ibcon#about to write, iclass 19, count 2 2006.285.14:54:35.45#ibcon#wrote, iclass 19, count 2 2006.285.14:54:35.45#ibcon#about to read 3, iclass 19, count 2 2006.285.14:54:35.48#ibcon#read 3, iclass 19, count 2 2006.285.14:54:35.48#ibcon#about to read 4, iclass 19, count 2 2006.285.14:54:35.48#ibcon#read 4, iclass 19, count 2 2006.285.14:54:35.48#ibcon#about to read 5, iclass 19, count 2 2006.285.14:54:35.48#ibcon#read 5, iclass 19, count 2 2006.285.14:54:35.48#ibcon#about to read 6, iclass 19, count 2 2006.285.14:54:35.48#ibcon#read 6, iclass 19, count 2 2006.285.14:54:35.48#ibcon#end of sib2, iclass 19, count 2 2006.285.14:54:35.48#ibcon#*after write, iclass 19, count 2 2006.285.14:54:35.48#ibcon#*before return 0, iclass 19, count 2 2006.285.14:54:35.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:54:35.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.14:54:35.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.14:54:35.48#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:35.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:54:35.60#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:54:35.60#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:54:35.60#ibcon#enter wrdev, iclass 19, count 0 2006.285.14:54:35.60#ibcon#first serial, iclass 19, count 0 2006.285.14:54:35.60#ibcon#enter sib2, iclass 19, count 0 2006.285.14:54:35.60#ibcon#flushed, iclass 19, count 0 2006.285.14:54:35.60#ibcon#about to write, iclass 19, count 0 2006.285.14:54:35.60#ibcon#wrote, iclass 19, count 0 2006.285.14:54:35.60#ibcon#about to read 3, iclass 19, count 0 2006.285.14:54:35.62#ibcon#read 3, iclass 19, count 0 2006.285.14:54:35.62#ibcon#about to read 4, iclass 19, count 0 2006.285.14:54:35.62#ibcon#read 4, iclass 19, count 0 2006.285.14:54:35.62#ibcon#about to read 5, iclass 19, count 0 2006.285.14:54:35.62#ibcon#read 5, iclass 19, count 0 2006.285.14:54:35.62#ibcon#about to read 6, iclass 19, count 0 2006.285.14:54:35.62#ibcon#read 6, iclass 19, count 0 2006.285.14:54:35.62#ibcon#end of sib2, iclass 19, count 0 2006.285.14:54:35.62#ibcon#*mode == 0, iclass 19, count 0 2006.285.14:54:35.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.14:54:35.62#ibcon#[27=USB\r\n] 2006.285.14:54:35.62#ibcon#*before write, iclass 19, count 0 2006.285.14:54:35.62#ibcon#enter sib2, iclass 19, count 0 2006.285.14:54:35.62#ibcon#flushed, iclass 19, count 0 2006.285.14:54:35.62#ibcon#about to write, iclass 19, count 0 2006.285.14:54:35.62#ibcon#wrote, iclass 19, count 0 2006.285.14:54:35.62#ibcon#about to read 3, iclass 19, count 0 2006.285.14:54:35.65#ibcon#read 3, iclass 19, count 0 2006.285.14:54:35.65#ibcon#about to read 4, iclass 19, count 0 2006.285.14:54:35.65#ibcon#read 4, iclass 19, count 0 2006.285.14:54:35.65#ibcon#about to read 5, iclass 19, count 0 2006.285.14:54:35.65#ibcon#read 5, iclass 19, count 0 2006.285.14:54:35.65#ibcon#about to read 6, iclass 19, count 0 2006.285.14:54:35.65#ibcon#read 6, iclass 19, count 0 2006.285.14:54:35.65#ibcon#end of sib2, iclass 19, count 0 2006.285.14:54:35.65#ibcon#*after write, iclass 19, count 0 2006.285.14:54:35.65#ibcon#*before return 0, iclass 19, count 0 2006.285.14:54:35.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:54:35.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.14:54:35.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.14:54:35.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.14:54:35.65$vck44/vblo=6,719.99 2006.285.14:54:35.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.14:54:35.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.14:54:35.65#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:35.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:54:35.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:54:35.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:54:35.65#ibcon#enter wrdev, iclass 21, count 0 2006.285.14:54:35.65#ibcon#first serial, iclass 21, count 0 2006.285.14:54:35.65#ibcon#enter sib2, iclass 21, count 0 2006.285.14:54:35.65#ibcon#flushed, iclass 21, count 0 2006.285.14:54:35.65#ibcon#about to write, iclass 21, count 0 2006.285.14:54:35.65#ibcon#wrote, iclass 21, count 0 2006.285.14:54:35.65#ibcon#about to read 3, iclass 21, count 0 2006.285.14:54:35.67#ibcon#read 3, iclass 21, count 0 2006.285.14:54:35.67#ibcon#about to read 4, iclass 21, count 0 2006.285.14:54:35.67#ibcon#read 4, iclass 21, count 0 2006.285.14:54:35.67#ibcon#about to read 5, iclass 21, count 0 2006.285.14:54:35.67#ibcon#read 5, iclass 21, count 0 2006.285.14:54:35.67#ibcon#about to read 6, iclass 21, count 0 2006.285.14:54:35.67#ibcon#read 6, iclass 21, count 0 2006.285.14:54:35.67#ibcon#end of sib2, iclass 21, count 0 2006.285.14:54:35.67#ibcon#*mode == 0, iclass 21, count 0 2006.285.14:54:35.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.14:54:35.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.14:54:35.67#ibcon#*before write, iclass 21, count 0 2006.285.14:54:35.67#ibcon#enter sib2, iclass 21, count 0 2006.285.14:54:35.67#ibcon#flushed, iclass 21, count 0 2006.285.14:54:35.67#ibcon#about to write, iclass 21, count 0 2006.285.14:54:35.67#ibcon#wrote, iclass 21, count 0 2006.285.14:54:35.67#ibcon#about to read 3, iclass 21, count 0 2006.285.14:54:35.71#ibcon#read 3, iclass 21, count 0 2006.285.14:54:35.71#ibcon#about to read 4, iclass 21, count 0 2006.285.14:54:35.71#ibcon#read 4, iclass 21, count 0 2006.285.14:54:35.71#ibcon#about to read 5, iclass 21, count 0 2006.285.14:54:35.71#ibcon#read 5, iclass 21, count 0 2006.285.14:54:35.71#ibcon#about to read 6, iclass 21, count 0 2006.285.14:54:35.71#ibcon#read 6, iclass 21, count 0 2006.285.14:54:35.71#ibcon#end of sib2, iclass 21, count 0 2006.285.14:54:35.71#ibcon#*after write, iclass 21, count 0 2006.285.14:54:35.71#ibcon#*before return 0, iclass 21, count 0 2006.285.14:54:35.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:54:35.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.14:54:35.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.14:54:35.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.14:54:35.71$vck44/vb=6,3 2006.285.14:54:35.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.14:54:35.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.14:54:35.71#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:35.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:54:35.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:54:35.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:54:35.77#ibcon#enter wrdev, iclass 23, count 2 2006.285.14:54:35.77#ibcon#first serial, iclass 23, count 2 2006.285.14:54:35.77#ibcon#enter sib2, iclass 23, count 2 2006.285.14:54:35.77#ibcon#flushed, iclass 23, count 2 2006.285.14:54:35.77#ibcon#about to write, iclass 23, count 2 2006.285.14:54:35.77#ibcon#wrote, iclass 23, count 2 2006.285.14:54:35.77#ibcon#about to read 3, iclass 23, count 2 2006.285.14:54:35.79#ibcon#read 3, iclass 23, count 2 2006.285.14:54:35.79#ibcon#about to read 4, iclass 23, count 2 2006.285.14:54:35.79#ibcon#read 4, iclass 23, count 2 2006.285.14:54:35.79#ibcon#about to read 5, iclass 23, count 2 2006.285.14:54:35.79#ibcon#read 5, iclass 23, count 2 2006.285.14:54:35.79#ibcon#about to read 6, iclass 23, count 2 2006.285.14:54:35.79#ibcon#read 6, iclass 23, count 2 2006.285.14:54:35.79#ibcon#end of sib2, iclass 23, count 2 2006.285.14:54:35.79#ibcon#*mode == 0, iclass 23, count 2 2006.285.14:54:35.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.14:54:35.79#ibcon#[27=AT06-03\r\n] 2006.285.14:54:35.79#ibcon#*before write, iclass 23, count 2 2006.285.14:54:35.79#ibcon#enter sib2, iclass 23, count 2 2006.285.14:54:35.79#ibcon#flushed, iclass 23, count 2 2006.285.14:54:35.79#ibcon#about to write, iclass 23, count 2 2006.285.14:54:35.79#ibcon#wrote, iclass 23, count 2 2006.285.14:54:35.79#ibcon#about to read 3, iclass 23, count 2 2006.285.14:54:35.82#ibcon#read 3, iclass 23, count 2 2006.285.14:54:35.82#ibcon#about to read 4, iclass 23, count 2 2006.285.14:54:35.82#ibcon#read 4, iclass 23, count 2 2006.285.14:54:35.82#ibcon#about to read 5, iclass 23, count 2 2006.285.14:54:35.82#ibcon#read 5, iclass 23, count 2 2006.285.14:54:35.82#ibcon#about to read 6, iclass 23, count 2 2006.285.14:54:35.82#ibcon#read 6, iclass 23, count 2 2006.285.14:54:35.82#ibcon#end of sib2, iclass 23, count 2 2006.285.14:54:35.82#ibcon#*after write, iclass 23, count 2 2006.285.14:54:35.82#ibcon#*before return 0, iclass 23, count 2 2006.285.14:54:35.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:54:35.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.14:54:35.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.14:54:35.82#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:35.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:54:35.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:54:35.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:54:35.94#ibcon#enter wrdev, iclass 23, count 0 2006.285.14:54:35.94#ibcon#first serial, iclass 23, count 0 2006.285.14:54:35.94#ibcon#enter sib2, iclass 23, count 0 2006.285.14:54:35.94#ibcon#flushed, iclass 23, count 0 2006.285.14:54:35.94#ibcon#about to write, iclass 23, count 0 2006.285.14:54:35.94#ibcon#wrote, iclass 23, count 0 2006.285.14:54:35.94#ibcon#about to read 3, iclass 23, count 0 2006.285.14:54:35.96#ibcon#read 3, iclass 23, count 0 2006.285.14:54:35.96#ibcon#about to read 4, iclass 23, count 0 2006.285.14:54:35.96#ibcon#read 4, iclass 23, count 0 2006.285.14:54:35.96#ibcon#about to read 5, iclass 23, count 0 2006.285.14:54:35.96#ibcon#read 5, iclass 23, count 0 2006.285.14:54:35.96#ibcon#about to read 6, iclass 23, count 0 2006.285.14:54:35.96#ibcon#read 6, iclass 23, count 0 2006.285.14:54:35.96#ibcon#end of sib2, iclass 23, count 0 2006.285.14:54:35.96#ibcon#*mode == 0, iclass 23, count 0 2006.285.14:54:35.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.14:54:35.96#ibcon#[27=USB\r\n] 2006.285.14:54:35.96#ibcon#*before write, iclass 23, count 0 2006.285.14:54:35.96#ibcon#enter sib2, iclass 23, count 0 2006.285.14:54:35.96#ibcon#flushed, iclass 23, count 0 2006.285.14:54:35.96#ibcon#about to write, iclass 23, count 0 2006.285.14:54:35.96#ibcon#wrote, iclass 23, count 0 2006.285.14:54:35.96#ibcon#about to read 3, iclass 23, count 0 2006.285.14:54:35.99#ibcon#read 3, iclass 23, count 0 2006.285.14:54:35.99#ibcon#about to read 4, iclass 23, count 0 2006.285.14:54:35.99#ibcon#read 4, iclass 23, count 0 2006.285.14:54:35.99#ibcon#about to read 5, iclass 23, count 0 2006.285.14:54:35.99#ibcon#read 5, iclass 23, count 0 2006.285.14:54:35.99#ibcon#about to read 6, iclass 23, count 0 2006.285.14:54:35.99#ibcon#read 6, iclass 23, count 0 2006.285.14:54:35.99#ibcon#end of sib2, iclass 23, count 0 2006.285.14:54:35.99#ibcon#*after write, iclass 23, count 0 2006.285.14:54:35.99#ibcon#*before return 0, iclass 23, count 0 2006.285.14:54:35.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:54:35.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.14:54:35.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.14:54:35.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.14:54:35.99$vck44/vblo=7,734.99 2006.285.14:54:35.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.14:54:35.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.14:54:35.99#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:35.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:54:35.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:54:35.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:54:35.99#ibcon#enter wrdev, iclass 25, count 0 2006.285.14:54:35.99#ibcon#first serial, iclass 25, count 0 2006.285.14:54:35.99#ibcon#enter sib2, iclass 25, count 0 2006.285.14:54:35.99#ibcon#flushed, iclass 25, count 0 2006.285.14:54:35.99#ibcon#about to write, iclass 25, count 0 2006.285.14:54:35.99#ibcon#wrote, iclass 25, count 0 2006.285.14:54:35.99#ibcon#about to read 3, iclass 25, count 0 2006.285.14:54:36.01#ibcon#read 3, iclass 25, count 0 2006.285.14:54:36.01#ibcon#about to read 4, iclass 25, count 0 2006.285.14:54:36.01#ibcon#read 4, iclass 25, count 0 2006.285.14:54:36.01#ibcon#about to read 5, iclass 25, count 0 2006.285.14:54:36.01#ibcon#read 5, iclass 25, count 0 2006.285.14:54:36.01#ibcon#about to read 6, iclass 25, count 0 2006.285.14:54:36.01#ibcon#read 6, iclass 25, count 0 2006.285.14:54:36.01#ibcon#end of sib2, iclass 25, count 0 2006.285.14:54:36.01#ibcon#*mode == 0, iclass 25, count 0 2006.285.14:54:36.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.14:54:36.01#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.14:54:36.01#ibcon#*before write, iclass 25, count 0 2006.285.14:54:36.01#ibcon#enter sib2, iclass 25, count 0 2006.285.14:54:36.01#ibcon#flushed, iclass 25, count 0 2006.285.14:54:36.01#ibcon#about to write, iclass 25, count 0 2006.285.14:54:36.01#ibcon#wrote, iclass 25, count 0 2006.285.14:54:36.01#ibcon#about to read 3, iclass 25, count 0 2006.285.14:54:36.05#ibcon#read 3, iclass 25, count 0 2006.285.14:54:36.05#ibcon#about to read 4, iclass 25, count 0 2006.285.14:54:36.05#ibcon#read 4, iclass 25, count 0 2006.285.14:54:36.05#ibcon#about to read 5, iclass 25, count 0 2006.285.14:54:36.05#ibcon#read 5, iclass 25, count 0 2006.285.14:54:36.05#ibcon#about to read 6, iclass 25, count 0 2006.285.14:54:36.05#ibcon#read 6, iclass 25, count 0 2006.285.14:54:36.05#ibcon#end of sib2, iclass 25, count 0 2006.285.14:54:36.05#ibcon#*after write, iclass 25, count 0 2006.285.14:54:36.05#ibcon#*before return 0, iclass 25, count 0 2006.285.14:54:36.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:54:36.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.14:54:36.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.14:54:36.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.14:54:36.05$vck44/vb=7,4 2006.285.14:54:36.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.14:54:36.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.14:54:36.05#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:36.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:54:36.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:54:36.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:54:36.11#ibcon#enter wrdev, iclass 27, count 2 2006.285.14:54:36.11#ibcon#first serial, iclass 27, count 2 2006.285.14:54:36.11#ibcon#enter sib2, iclass 27, count 2 2006.285.14:54:36.11#ibcon#flushed, iclass 27, count 2 2006.285.14:54:36.11#ibcon#about to write, iclass 27, count 2 2006.285.14:54:36.11#ibcon#wrote, iclass 27, count 2 2006.285.14:54:36.11#ibcon#about to read 3, iclass 27, count 2 2006.285.14:54:36.13#ibcon#read 3, iclass 27, count 2 2006.285.14:54:36.13#ibcon#about to read 4, iclass 27, count 2 2006.285.14:54:36.13#ibcon#read 4, iclass 27, count 2 2006.285.14:54:36.13#ibcon#about to read 5, iclass 27, count 2 2006.285.14:54:36.13#ibcon#read 5, iclass 27, count 2 2006.285.14:54:36.13#ibcon#about to read 6, iclass 27, count 2 2006.285.14:54:36.13#ibcon#read 6, iclass 27, count 2 2006.285.14:54:36.13#ibcon#end of sib2, iclass 27, count 2 2006.285.14:54:36.13#ibcon#*mode == 0, iclass 27, count 2 2006.285.14:54:36.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.14:54:36.13#ibcon#[27=AT07-04\r\n] 2006.285.14:54:36.13#ibcon#*before write, iclass 27, count 2 2006.285.14:54:36.13#ibcon#enter sib2, iclass 27, count 2 2006.285.14:54:36.13#ibcon#flushed, iclass 27, count 2 2006.285.14:54:36.13#ibcon#about to write, iclass 27, count 2 2006.285.14:54:36.13#ibcon#wrote, iclass 27, count 2 2006.285.14:54:36.13#ibcon#about to read 3, iclass 27, count 2 2006.285.14:54:36.16#ibcon#read 3, iclass 27, count 2 2006.285.14:54:36.16#ibcon#about to read 4, iclass 27, count 2 2006.285.14:54:36.16#ibcon#read 4, iclass 27, count 2 2006.285.14:54:36.16#ibcon#about to read 5, iclass 27, count 2 2006.285.14:54:36.16#ibcon#read 5, iclass 27, count 2 2006.285.14:54:36.16#ibcon#about to read 6, iclass 27, count 2 2006.285.14:54:36.16#ibcon#read 6, iclass 27, count 2 2006.285.14:54:36.16#ibcon#end of sib2, iclass 27, count 2 2006.285.14:54:36.16#ibcon#*after write, iclass 27, count 2 2006.285.14:54:36.16#ibcon#*before return 0, iclass 27, count 2 2006.285.14:54:36.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:54:36.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.14:54:36.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.14:54:36.16#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:36.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:54:36.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:54:36.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:54:36.28#ibcon#enter wrdev, iclass 27, count 0 2006.285.14:54:36.28#ibcon#first serial, iclass 27, count 0 2006.285.14:54:36.28#ibcon#enter sib2, iclass 27, count 0 2006.285.14:54:36.28#ibcon#flushed, iclass 27, count 0 2006.285.14:54:36.28#ibcon#about to write, iclass 27, count 0 2006.285.14:54:36.28#ibcon#wrote, iclass 27, count 0 2006.285.14:54:36.28#ibcon#about to read 3, iclass 27, count 0 2006.285.14:54:36.30#ibcon#read 3, iclass 27, count 0 2006.285.14:54:36.30#ibcon#about to read 4, iclass 27, count 0 2006.285.14:54:36.30#ibcon#read 4, iclass 27, count 0 2006.285.14:54:36.30#ibcon#about to read 5, iclass 27, count 0 2006.285.14:54:36.30#ibcon#read 5, iclass 27, count 0 2006.285.14:54:36.30#ibcon#about to read 6, iclass 27, count 0 2006.285.14:54:36.30#ibcon#read 6, iclass 27, count 0 2006.285.14:54:36.30#ibcon#end of sib2, iclass 27, count 0 2006.285.14:54:36.30#ibcon#*mode == 0, iclass 27, count 0 2006.285.14:54:36.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.14:54:36.30#ibcon#[27=USB\r\n] 2006.285.14:54:36.30#ibcon#*before write, iclass 27, count 0 2006.285.14:54:36.30#ibcon#enter sib2, iclass 27, count 0 2006.285.14:54:36.30#ibcon#flushed, iclass 27, count 0 2006.285.14:54:36.30#ibcon#about to write, iclass 27, count 0 2006.285.14:54:36.30#ibcon#wrote, iclass 27, count 0 2006.285.14:54:36.30#ibcon#about to read 3, iclass 27, count 0 2006.285.14:54:36.33#ibcon#read 3, iclass 27, count 0 2006.285.14:54:36.33#ibcon#about to read 4, iclass 27, count 0 2006.285.14:54:36.33#ibcon#read 4, iclass 27, count 0 2006.285.14:54:36.33#ibcon#about to read 5, iclass 27, count 0 2006.285.14:54:36.33#ibcon#read 5, iclass 27, count 0 2006.285.14:54:36.33#ibcon#about to read 6, iclass 27, count 0 2006.285.14:54:36.33#ibcon#read 6, iclass 27, count 0 2006.285.14:54:36.33#ibcon#end of sib2, iclass 27, count 0 2006.285.14:54:36.33#ibcon#*after write, iclass 27, count 0 2006.285.14:54:36.33#ibcon#*before return 0, iclass 27, count 0 2006.285.14:54:36.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:54:36.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.14:54:36.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.14:54:36.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.14:54:36.33$vck44/vblo=8,744.99 2006.285.14:54:36.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.14:54:36.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.14:54:36.33#ibcon#ireg 17 cls_cnt 0 2006.285.14:54:36.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:54:36.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:54:36.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:54:36.33#ibcon#enter wrdev, iclass 29, count 0 2006.285.14:54:36.33#ibcon#first serial, iclass 29, count 0 2006.285.14:54:36.33#ibcon#enter sib2, iclass 29, count 0 2006.285.14:54:36.33#ibcon#flushed, iclass 29, count 0 2006.285.14:54:36.33#ibcon#about to write, iclass 29, count 0 2006.285.14:54:36.33#ibcon#wrote, iclass 29, count 0 2006.285.14:54:36.33#ibcon#about to read 3, iclass 29, count 0 2006.285.14:54:36.35#ibcon#read 3, iclass 29, count 0 2006.285.14:54:36.57#ibcon#about to read 4, iclass 29, count 0 2006.285.14:54:36.57#ibcon#read 4, iclass 29, count 0 2006.285.14:54:36.57#ibcon#about to read 5, iclass 29, count 0 2006.285.14:54:36.57#ibcon#read 5, iclass 29, count 0 2006.285.14:54:36.57#ibcon#about to read 6, iclass 29, count 0 2006.285.14:54:36.57#ibcon#read 6, iclass 29, count 0 2006.285.14:54:36.57#ibcon#end of sib2, iclass 29, count 0 2006.285.14:54:36.57#ibcon#*mode == 0, iclass 29, count 0 2006.285.14:54:36.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.14:54:36.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.14:54:36.57#ibcon#*before write, iclass 29, count 0 2006.285.14:54:36.57#ibcon#enter sib2, iclass 29, count 0 2006.285.14:54:36.57#ibcon#flushed, iclass 29, count 0 2006.285.14:54:36.57#ibcon#about to write, iclass 29, count 0 2006.285.14:54:36.57#ibcon#wrote, iclass 29, count 0 2006.285.14:54:36.57#ibcon#about to read 3, iclass 29, count 0 2006.285.14:54:36.61#ibcon#read 3, iclass 29, count 0 2006.285.14:54:36.61#ibcon#about to read 4, iclass 29, count 0 2006.285.14:54:36.61#ibcon#read 4, iclass 29, count 0 2006.285.14:54:36.61#ibcon#about to read 5, iclass 29, count 0 2006.285.14:54:36.61#ibcon#read 5, iclass 29, count 0 2006.285.14:54:36.61#ibcon#about to read 6, iclass 29, count 0 2006.285.14:54:36.61#ibcon#read 6, iclass 29, count 0 2006.285.14:54:36.61#ibcon#end of sib2, iclass 29, count 0 2006.285.14:54:36.61#ibcon#*after write, iclass 29, count 0 2006.285.14:54:36.61#ibcon#*before return 0, iclass 29, count 0 2006.285.14:54:36.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:54:36.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.14:54:36.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.14:54:36.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.14:54:36.61$vck44/vb=8,4 2006.285.14:54:36.61#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.14:54:36.61#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.14:54:36.61#ibcon#ireg 11 cls_cnt 2 2006.285.14:54:36.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:54:36.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:54:36.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:54:36.61#ibcon#enter wrdev, iclass 31, count 2 2006.285.14:54:36.61#ibcon#first serial, iclass 31, count 2 2006.285.14:54:36.61#ibcon#enter sib2, iclass 31, count 2 2006.285.14:54:36.61#ibcon#flushed, iclass 31, count 2 2006.285.14:54:36.61#ibcon#about to write, iclass 31, count 2 2006.285.14:54:36.61#ibcon#wrote, iclass 31, count 2 2006.285.14:54:36.61#ibcon#about to read 3, iclass 31, count 2 2006.285.14:54:36.63#ibcon#read 3, iclass 31, count 2 2006.285.14:54:36.63#ibcon#about to read 4, iclass 31, count 2 2006.285.14:54:36.63#ibcon#read 4, iclass 31, count 2 2006.285.14:54:36.63#ibcon#about to read 5, iclass 31, count 2 2006.285.14:54:36.63#ibcon#read 5, iclass 31, count 2 2006.285.14:54:36.63#ibcon#about to read 6, iclass 31, count 2 2006.285.14:54:36.63#ibcon#read 6, iclass 31, count 2 2006.285.14:54:36.63#ibcon#end of sib2, iclass 31, count 2 2006.285.14:54:36.63#ibcon#*mode == 0, iclass 31, count 2 2006.285.14:54:36.63#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.14:54:36.63#ibcon#[27=AT08-04\r\n] 2006.285.14:54:36.63#ibcon#*before write, iclass 31, count 2 2006.285.14:54:36.63#ibcon#enter sib2, iclass 31, count 2 2006.285.14:54:36.63#ibcon#flushed, iclass 31, count 2 2006.285.14:54:36.63#ibcon#about to write, iclass 31, count 2 2006.285.14:54:36.63#ibcon#wrote, iclass 31, count 2 2006.285.14:54:36.63#ibcon#about to read 3, iclass 31, count 2 2006.285.14:54:36.66#ibcon#read 3, iclass 31, count 2 2006.285.14:54:36.66#ibcon#about to read 4, iclass 31, count 2 2006.285.14:54:36.66#ibcon#read 4, iclass 31, count 2 2006.285.14:54:36.66#ibcon#about to read 5, iclass 31, count 2 2006.285.14:54:36.66#ibcon#read 5, iclass 31, count 2 2006.285.14:54:36.66#ibcon#about to read 6, iclass 31, count 2 2006.285.14:54:36.66#ibcon#read 6, iclass 31, count 2 2006.285.14:54:36.66#ibcon#end of sib2, iclass 31, count 2 2006.285.14:54:36.66#ibcon#*after write, iclass 31, count 2 2006.285.14:54:36.66#ibcon#*before return 0, iclass 31, count 2 2006.285.14:54:36.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:54:36.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.14:54:36.66#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.14:54:36.66#ibcon#ireg 7 cls_cnt 0 2006.285.14:54:36.66#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:54:36.78#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:54:36.78#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:54:36.78#ibcon#enter wrdev, iclass 31, count 0 2006.285.14:54:36.78#ibcon#first serial, iclass 31, count 0 2006.285.14:54:36.78#ibcon#enter sib2, iclass 31, count 0 2006.285.14:54:36.78#ibcon#flushed, iclass 31, count 0 2006.285.14:54:36.78#ibcon#about to write, iclass 31, count 0 2006.285.14:54:36.78#ibcon#wrote, iclass 31, count 0 2006.285.14:54:36.78#ibcon#about to read 3, iclass 31, count 0 2006.285.14:54:36.80#ibcon#read 3, iclass 31, count 0 2006.285.14:54:36.80#ibcon#about to read 4, iclass 31, count 0 2006.285.14:54:36.80#ibcon#read 4, iclass 31, count 0 2006.285.14:54:36.80#ibcon#about to read 5, iclass 31, count 0 2006.285.14:54:36.80#ibcon#read 5, iclass 31, count 0 2006.285.14:54:36.80#ibcon#about to read 6, iclass 31, count 0 2006.285.14:54:36.80#ibcon#read 6, iclass 31, count 0 2006.285.14:54:36.80#ibcon#end of sib2, iclass 31, count 0 2006.285.14:54:36.80#ibcon#*mode == 0, iclass 31, count 0 2006.285.14:54:36.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.14:54:36.80#ibcon#[27=USB\r\n] 2006.285.14:54:36.80#ibcon#*before write, iclass 31, count 0 2006.285.14:54:36.80#ibcon#enter sib2, iclass 31, count 0 2006.285.14:54:36.80#ibcon#flushed, iclass 31, count 0 2006.285.14:54:36.80#ibcon#about to write, iclass 31, count 0 2006.285.14:54:36.80#ibcon#wrote, iclass 31, count 0 2006.285.14:54:36.80#ibcon#about to read 3, iclass 31, count 0 2006.285.14:54:36.83#ibcon#read 3, iclass 31, count 0 2006.285.14:54:36.83#ibcon#about to read 4, iclass 31, count 0 2006.285.14:54:36.83#ibcon#read 4, iclass 31, count 0 2006.285.14:54:36.83#ibcon#about to read 5, iclass 31, count 0 2006.285.14:54:36.83#ibcon#read 5, iclass 31, count 0 2006.285.14:54:36.83#ibcon#about to read 6, iclass 31, count 0 2006.285.14:54:36.83#ibcon#read 6, iclass 31, count 0 2006.285.14:54:36.83#ibcon#end of sib2, iclass 31, count 0 2006.285.14:54:36.83#ibcon#*after write, iclass 31, count 0 2006.285.14:54:36.83#ibcon#*before return 0, iclass 31, count 0 2006.285.14:54:36.83#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:54:36.83#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.14:54:36.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.14:54:36.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.14:54:36.83$vck44/vabw=wide 2006.285.14:54:36.83#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.14:54:36.83#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.14:54:36.83#ibcon#ireg 8 cls_cnt 0 2006.285.14:54:36.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:54:36.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:54:36.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:54:36.83#ibcon#enter wrdev, iclass 33, count 0 2006.285.14:54:36.83#ibcon#first serial, iclass 33, count 0 2006.285.14:54:36.83#ibcon#enter sib2, iclass 33, count 0 2006.285.14:54:36.83#ibcon#flushed, iclass 33, count 0 2006.285.14:54:36.83#ibcon#about to write, iclass 33, count 0 2006.285.14:54:36.83#ibcon#wrote, iclass 33, count 0 2006.285.14:54:36.83#ibcon#about to read 3, iclass 33, count 0 2006.285.14:54:36.85#ibcon#read 3, iclass 33, count 0 2006.285.14:54:36.85#ibcon#about to read 4, iclass 33, count 0 2006.285.14:54:36.85#ibcon#read 4, iclass 33, count 0 2006.285.14:54:36.85#ibcon#about to read 5, iclass 33, count 0 2006.285.14:54:36.85#ibcon#read 5, iclass 33, count 0 2006.285.14:54:36.85#ibcon#about to read 6, iclass 33, count 0 2006.285.14:54:36.85#ibcon#read 6, iclass 33, count 0 2006.285.14:54:36.85#ibcon#end of sib2, iclass 33, count 0 2006.285.14:54:36.85#ibcon#*mode == 0, iclass 33, count 0 2006.285.14:54:36.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.14:54:36.85#ibcon#[25=BW32\r\n] 2006.285.14:54:36.85#ibcon#*before write, iclass 33, count 0 2006.285.14:54:36.85#ibcon#enter sib2, iclass 33, count 0 2006.285.14:54:36.85#ibcon#flushed, iclass 33, count 0 2006.285.14:54:36.85#ibcon#about to write, iclass 33, count 0 2006.285.14:54:36.85#ibcon#wrote, iclass 33, count 0 2006.285.14:54:36.85#ibcon#about to read 3, iclass 33, count 0 2006.285.14:54:36.88#ibcon#read 3, iclass 33, count 0 2006.285.14:54:36.88#ibcon#about to read 4, iclass 33, count 0 2006.285.14:54:36.88#ibcon#read 4, iclass 33, count 0 2006.285.14:54:36.88#ibcon#about to read 5, iclass 33, count 0 2006.285.14:54:36.88#ibcon#read 5, iclass 33, count 0 2006.285.14:54:36.88#ibcon#about to read 6, iclass 33, count 0 2006.285.14:54:36.88#ibcon#read 6, iclass 33, count 0 2006.285.14:54:36.88#ibcon#end of sib2, iclass 33, count 0 2006.285.14:54:36.88#ibcon#*after write, iclass 33, count 0 2006.285.14:54:36.88#ibcon#*before return 0, iclass 33, count 0 2006.285.14:54:36.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:54:36.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.14:54:36.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.14:54:36.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.14:54:36.88$vck44/vbbw=wide 2006.285.14:54:36.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.14:54:36.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.14:54:36.88#ibcon#ireg 8 cls_cnt 0 2006.285.14:54:36.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:54:36.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:54:36.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:54:36.95#ibcon#enter wrdev, iclass 35, count 0 2006.285.14:54:36.95#ibcon#first serial, iclass 35, count 0 2006.285.14:54:36.95#ibcon#enter sib2, iclass 35, count 0 2006.285.14:54:36.95#ibcon#flushed, iclass 35, count 0 2006.285.14:54:36.95#ibcon#about to write, iclass 35, count 0 2006.285.14:54:36.95#ibcon#wrote, iclass 35, count 0 2006.285.14:54:36.95#ibcon#about to read 3, iclass 35, count 0 2006.285.14:54:36.97#ibcon#read 3, iclass 35, count 0 2006.285.14:54:36.97#ibcon#about to read 4, iclass 35, count 0 2006.285.14:54:36.97#ibcon#read 4, iclass 35, count 0 2006.285.14:54:36.97#ibcon#about to read 5, iclass 35, count 0 2006.285.14:54:36.97#ibcon#read 5, iclass 35, count 0 2006.285.14:54:36.97#ibcon#about to read 6, iclass 35, count 0 2006.285.14:54:36.97#ibcon#read 6, iclass 35, count 0 2006.285.14:54:36.97#ibcon#end of sib2, iclass 35, count 0 2006.285.14:54:36.97#ibcon#*mode == 0, iclass 35, count 0 2006.285.14:54:36.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.14:54:36.97#ibcon#[27=BW32\r\n] 2006.285.14:54:36.97#ibcon#*before write, iclass 35, count 0 2006.285.14:54:36.97#ibcon#enter sib2, iclass 35, count 0 2006.285.14:54:36.97#ibcon#flushed, iclass 35, count 0 2006.285.14:54:36.97#ibcon#about to write, iclass 35, count 0 2006.285.14:54:36.97#ibcon#wrote, iclass 35, count 0 2006.285.14:54:36.97#ibcon#about to read 3, iclass 35, count 0 2006.285.14:54:37.00#ibcon#read 3, iclass 35, count 0 2006.285.14:54:37.00#ibcon#about to read 4, iclass 35, count 0 2006.285.14:54:37.00#ibcon#read 4, iclass 35, count 0 2006.285.14:54:37.00#ibcon#about to read 5, iclass 35, count 0 2006.285.14:54:37.00#ibcon#read 5, iclass 35, count 0 2006.285.14:54:37.00#ibcon#about to read 6, iclass 35, count 0 2006.285.14:54:37.00#ibcon#read 6, iclass 35, count 0 2006.285.14:54:37.00#ibcon#end of sib2, iclass 35, count 0 2006.285.14:54:37.00#ibcon#*after write, iclass 35, count 0 2006.285.14:54:37.00#ibcon#*before return 0, iclass 35, count 0 2006.285.14:54:37.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:54:37.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.14:54:37.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.14:54:37.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.14:54:37.00$setupk4/ifdk4 2006.285.14:54:37.00$ifdk4/lo= 2006.285.14:54:37.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.14:54:37.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.14:54:37.00$ifdk4/patch= 2006.285.14:54:37.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.14:54:37.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.14:54:37.00$setupk4/!*+20s 2006.285.14:54:43.01#abcon#<5=/03 1.9 5.0 19.15 921015.0\r\n> 2006.285.14:54:43.03#abcon#{5=INTERFACE CLEAR} 2006.285.14:54:43.09#abcon#[5=S1D000X0/0*\r\n] 2006.285.14:54:48.13#trakl#Source acquired 2006.285.14:54:48.13#flagr#flagr/antenna,acquired 2006.285.14:54:50.65$setupk4/"tpicd 2006.285.14:54:50.65$setupk4/echo=off 2006.285.14:54:50.65$setupk4/xlog=off 2006.285.14:54:50.65:!2006.285.14:56:26 2006.285.14:56:26.00:preob 2006.285.14:56:26.14/onsource/TRACKING 2006.285.14:56:26.14:!2006.285.14:56:36 2006.285.14:56:36.00:"tape 2006.285.14:56:36.00:"st=record 2006.285.14:56:36.00:data_valid=on 2006.285.14:56:36.00:midob 2006.285.14:56:36.14/onsource/TRACKING 2006.285.14:56:36.14/wx/19.16,1015.0,92 2006.285.14:56:36.35/cable/+6.5008E-03 2006.285.14:56:37.44/va/01,07,usb,yes,32,34 2006.285.14:56:37.44/va/02,06,usb,yes,32,32 2006.285.14:56:37.44/va/03,07,usb,yes,31,33 2006.285.14:56:37.44/va/04,06,usb,yes,33,34 2006.285.14:56:37.44/va/05,03,usb,yes,32,33 2006.285.14:56:37.44/va/06,04,usb,yes,29,29 2006.285.14:56:37.44/va/07,04,usb,yes,30,30 2006.285.14:56:37.44/va/08,03,usb,yes,30,37 2006.285.14:56:37.67/valo/01,524.99,yes,locked 2006.285.14:56:37.67/valo/02,534.99,yes,locked 2006.285.14:56:37.67/valo/03,564.99,yes,locked 2006.285.14:56:37.67/valo/04,624.99,yes,locked 2006.285.14:56:37.67/valo/05,734.99,yes,locked 2006.285.14:56:37.67/valo/06,814.99,yes,locked 2006.285.14:56:37.67/valo/07,864.99,yes,locked 2006.285.14:56:37.67/valo/08,884.99,yes,locked 2006.285.14:56:38.76/vb/01,04,usb,yes,30,28 2006.285.14:56:38.76/vb/02,05,usb,yes,28,28 2006.285.14:56:38.76/vb/03,04,usb,yes,29,32 2006.285.14:56:38.76/vb/04,05,usb,yes,29,28 2006.285.14:56:38.76/vb/05,04,usb,yes,26,28 2006.285.14:56:38.76/vb/06,03,usb,yes,37,33 2006.285.14:56:38.76/vb/07,04,usb,yes,30,30 2006.285.14:56:38.76/vb/08,04,usb,yes,27,31 2006.285.14:56:39.00/vblo/01,629.99,yes,locked 2006.285.14:56:39.00/vblo/02,634.99,yes,locked 2006.285.14:56:39.00/vblo/03,649.99,yes,locked 2006.285.14:56:39.00/vblo/04,679.99,yes,locked 2006.285.14:56:39.00/vblo/05,709.99,yes,locked 2006.285.14:56:39.00/vblo/06,719.99,yes,locked 2006.285.14:56:39.00/vblo/07,734.99,yes,locked 2006.285.14:56:39.00/vblo/08,744.99,yes,locked 2006.285.14:56:39.15/vabw/8 2006.285.14:56:39.30/vbbw/8 2006.285.14:56:39.39/xfe/off,on,12.0 2006.285.14:56:39.78/ifatt/23,28,28,28 2006.285.14:56:40.07/fmout-gps/S +2.71E-07 2006.285.14:56:40.09:!2006.285.15:01:46 2006.285.15:01:46.00:data_valid=off 2006.285.15:01:46.00:"et 2006.285.15:01:46.00:!+3s 2006.285.15:01:49.01:"tape 2006.285.15:01:49.01:postob 2006.285.15:01:49.07/cable/+6.4995E-03 2006.285.15:01:49.07/wx/19.15,1014.9,93 2006.285.15:01:50.07/fmout-gps/S +2.66E-07 2006.285.15:01:50.07:scan_name=285-1506,jd0610,250 2006.285.15:01:50.07:source=1803+784,180045.68,782804.0,2000.0,ccw 2006.285.15:01:51.13#flagr#flagr/antenna,new-source 2006.285.15:01:51.13:checkk5 2006.285.15:01:51.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.15:01:52.27/chk_autoobs//k5ts2/ autoobs is running! 2006.285.15:01:52.77/chk_autoobs//k5ts3/ autoobs is running! 2006.285.15:01:53.26/chk_autoobs//k5ts4/ autoobs is running! 2006.285.15:01:53.67/chk_obsdata//k5ts1/T2851456??a.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.285.15:01:54.06/chk_obsdata//k5ts2/T2851456??b.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.285.15:01:54.39/chk_obsdata//k5ts3/T2851456??c.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.285.15:01:54.87/chk_obsdata//k5ts4/T2851456??d.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.285.15:01:55.77/k5log//k5ts1_log_newline 2006.285.15:01:56.65/k5log//k5ts2_log_newline 2006.285.15:01:57.50/k5log//k5ts3_log_newline 2006.285.15:01:58.22/k5log//k5ts4_log_newline 2006.285.15:01:58.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.15:01:58.24:setupk4=1 2006.285.15:01:58.24$setupk4/echo=on 2006.285.15:01:58.24$setupk4/pcalon 2006.285.15:01:58.24$pcalon/"no phase cal control is implemented here 2006.285.15:01:58.24$setupk4/"tpicd=stop 2006.285.15:01:58.24$setupk4/"rec=synch_on 2006.285.15:01:58.24$setupk4/"rec_mode=128 2006.285.15:01:58.24$setupk4/!* 2006.285.15:01:58.24$setupk4/recpk4 2006.285.15:01:58.24$recpk4/recpatch= 2006.285.15:01:58.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.15:01:58.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.15:01:58.24$setupk4/vck44 2006.285.15:01:58.24$vck44/valo=1,524.99 2006.285.15:01:58.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.15:01:58.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.15:01:58.24#ibcon#ireg 17 cls_cnt 0 2006.285.15:01:58.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:01:58.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:01:58.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:01:58.24#ibcon#enter wrdev, iclass 32, count 0 2006.285.15:01:58.24#ibcon#first serial, iclass 32, count 0 2006.285.15:01:58.24#ibcon#enter sib2, iclass 32, count 0 2006.285.15:01:58.24#ibcon#flushed, iclass 32, count 0 2006.285.15:01:58.24#ibcon#about to write, iclass 32, count 0 2006.285.15:01:58.24#ibcon#wrote, iclass 32, count 0 2006.285.15:01:58.24#ibcon#about to read 3, iclass 32, count 0 2006.285.15:01:58.26#ibcon#read 3, iclass 32, count 0 2006.285.15:01:58.26#ibcon#about to read 4, iclass 32, count 0 2006.285.15:01:58.26#ibcon#read 4, iclass 32, count 0 2006.285.15:01:58.26#ibcon#about to read 5, iclass 32, count 0 2006.285.15:01:58.26#ibcon#read 5, iclass 32, count 0 2006.285.15:01:58.26#ibcon#about to read 6, iclass 32, count 0 2006.285.15:01:58.26#ibcon#read 6, iclass 32, count 0 2006.285.15:01:58.26#ibcon#end of sib2, iclass 32, count 0 2006.285.15:01:58.26#ibcon#*mode == 0, iclass 32, count 0 2006.285.15:01:58.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.15:01:58.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.15:01:58.26#ibcon#*before write, iclass 32, count 0 2006.285.15:01:58.26#ibcon#enter sib2, iclass 32, count 0 2006.285.15:01:58.26#ibcon#flushed, iclass 32, count 0 2006.285.15:01:58.26#ibcon#about to write, iclass 32, count 0 2006.285.15:01:58.26#ibcon#wrote, iclass 32, count 0 2006.285.15:01:58.26#ibcon#about to read 3, iclass 32, count 0 2006.285.15:01:58.31#ibcon#read 3, iclass 32, count 0 2006.285.15:01:58.31#ibcon#about to read 4, iclass 32, count 0 2006.285.15:01:58.31#ibcon#read 4, iclass 32, count 0 2006.285.15:01:58.31#ibcon#about to read 5, iclass 32, count 0 2006.285.15:01:58.31#ibcon#read 5, iclass 32, count 0 2006.285.15:01:58.31#ibcon#about to read 6, iclass 32, count 0 2006.285.15:01:58.31#ibcon#read 6, iclass 32, count 0 2006.285.15:01:58.31#ibcon#end of sib2, iclass 32, count 0 2006.285.15:01:58.31#ibcon#*after write, iclass 32, count 0 2006.285.15:01:58.31#ibcon#*before return 0, iclass 32, count 0 2006.285.15:01:58.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:01:58.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:01:58.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.15:01:58.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.15:01:58.31$vck44/va=1,7 2006.285.15:01:58.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.15:01:58.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.15:01:58.31#ibcon#ireg 11 cls_cnt 2 2006.285.15:01:58.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:01:58.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:01:58.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:01:58.31#ibcon#enter wrdev, iclass 34, count 2 2006.285.15:01:58.31#ibcon#first serial, iclass 34, count 2 2006.285.15:01:58.31#ibcon#enter sib2, iclass 34, count 2 2006.285.15:01:58.31#ibcon#flushed, iclass 34, count 2 2006.285.15:01:58.31#ibcon#about to write, iclass 34, count 2 2006.285.15:01:58.31#ibcon#wrote, iclass 34, count 2 2006.285.15:01:58.31#ibcon#about to read 3, iclass 34, count 2 2006.285.15:01:58.33#ibcon#read 3, iclass 34, count 2 2006.285.15:01:58.33#ibcon#about to read 4, iclass 34, count 2 2006.285.15:01:58.33#ibcon#read 4, iclass 34, count 2 2006.285.15:01:58.33#ibcon#about to read 5, iclass 34, count 2 2006.285.15:01:58.33#ibcon#read 5, iclass 34, count 2 2006.285.15:01:58.33#ibcon#about to read 6, iclass 34, count 2 2006.285.15:01:58.33#ibcon#read 6, iclass 34, count 2 2006.285.15:01:58.33#ibcon#end of sib2, iclass 34, count 2 2006.285.15:01:58.33#ibcon#*mode == 0, iclass 34, count 2 2006.285.15:01:58.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.15:01:58.33#ibcon#[25=AT01-07\r\n] 2006.285.15:01:58.33#ibcon#*before write, iclass 34, count 2 2006.285.15:01:58.33#ibcon#enter sib2, iclass 34, count 2 2006.285.15:01:58.33#ibcon#flushed, iclass 34, count 2 2006.285.15:01:58.33#ibcon#about to write, iclass 34, count 2 2006.285.15:01:58.33#ibcon#wrote, iclass 34, count 2 2006.285.15:01:58.33#ibcon#about to read 3, iclass 34, count 2 2006.285.15:01:58.36#ibcon#read 3, iclass 34, count 2 2006.285.15:01:58.36#ibcon#about to read 4, iclass 34, count 2 2006.285.15:01:58.36#ibcon#read 4, iclass 34, count 2 2006.285.15:01:58.36#ibcon#about to read 5, iclass 34, count 2 2006.285.15:01:58.36#ibcon#read 5, iclass 34, count 2 2006.285.15:01:58.36#ibcon#about to read 6, iclass 34, count 2 2006.285.15:01:58.36#ibcon#read 6, iclass 34, count 2 2006.285.15:01:58.36#ibcon#end of sib2, iclass 34, count 2 2006.285.15:01:58.36#ibcon#*after write, iclass 34, count 2 2006.285.15:01:58.36#ibcon#*before return 0, iclass 34, count 2 2006.285.15:01:58.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:01:58.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:01:58.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.15:01:58.36#ibcon#ireg 7 cls_cnt 0 2006.285.15:01:58.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:01:58.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:01:58.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:01:58.48#ibcon#enter wrdev, iclass 34, count 0 2006.285.15:01:58.48#ibcon#first serial, iclass 34, count 0 2006.285.15:01:58.48#ibcon#enter sib2, iclass 34, count 0 2006.285.15:01:58.48#ibcon#flushed, iclass 34, count 0 2006.285.15:01:58.48#ibcon#about to write, iclass 34, count 0 2006.285.15:01:58.48#ibcon#wrote, iclass 34, count 0 2006.285.15:01:58.48#ibcon#about to read 3, iclass 34, count 0 2006.285.15:01:58.50#ibcon#read 3, iclass 34, count 0 2006.285.15:01:58.50#ibcon#about to read 4, iclass 34, count 0 2006.285.15:01:58.50#ibcon#read 4, iclass 34, count 0 2006.285.15:01:58.50#ibcon#about to read 5, iclass 34, count 0 2006.285.15:01:58.50#ibcon#read 5, iclass 34, count 0 2006.285.15:01:58.50#ibcon#about to read 6, iclass 34, count 0 2006.285.15:01:58.50#ibcon#read 6, iclass 34, count 0 2006.285.15:01:58.50#ibcon#end of sib2, iclass 34, count 0 2006.285.15:01:58.50#ibcon#*mode == 0, iclass 34, count 0 2006.285.15:01:58.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.15:01:58.50#ibcon#[25=USB\r\n] 2006.285.15:01:58.50#ibcon#*before write, iclass 34, count 0 2006.285.15:01:58.50#ibcon#enter sib2, iclass 34, count 0 2006.285.15:01:58.50#ibcon#flushed, iclass 34, count 0 2006.285.15:01:58.50#ibcon#about to write, iclass 34, count 0 2006.285.15:01:58.50#ibcon#wrote, iclass 34, count 0 2006.285.15:01:58.50#ibcon#about to read 3, iclass 34, count 0 2006.285.15:01:58.53#ibcon#read 3, iclass 34, count 0 2006.285.15:01:58.53#ibcon#about to read 4, iclass 34, count 0 2006.285.15:01:58.53#ibcon#read 4, iclass 34, count 0 2006.285.15:01:58.53#ibcon#about to read 5, iclass 34, count 0 2006.285.15:01:58.53#ibcon#read 5, iclass 34, count 0 2006.285.15:01:58.53#ibcon#about to read 6, iclass 34, count 0 2006.285.15:01:58.53#ibcon#read 6, iclass 34, count 0 2006.285.15:01:58.53#ibcon#end of sib2, iclass 34, count 0 2006.285.15:01:58.53#ibcon#*after write, iclass 34, count 0 2006.285.15:01:58.53#ibcon#*before return 0, iclass 34, count 0 2006.285.15:01:58.53#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:01:58.53#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:01:58.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.15:01:58.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.15:01:58.53$vck44/valo=2,534.99 2006.285.15:01:58.53#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.15:01:58.53#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.15:01:58.53#ibcon#ireg 17 cls_cnt 0 2006.285.15:01:58.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:01:58.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:01:58.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:01:58.53#ibcon#enter wrdev, iclass 36, count 0 2006.285.15:01:58.53#ibcon#first serial, iclass 36, count 0 2006.285.15:01:58.53#ibcon#enter sib2, iclass 36, count 0 2006.285.15:01:58.53#ibcon#flushed, iclass 36, count 0 2006.285.15:01:58.53#ibcon#about to write, iclass 36, count 0 2006.285.15:01:58.53#ibcon#wrote, iclass 36, count 0 2006.285.15:01:58.53#ibcon#about to read 3, iclass 36, count 0 2006.285.15:01:58.55#ibcon#read 3, iclass 36, count 0 2006.285.15:01:58.55#ibcon#about to read 4, iclass 36, count 0 2006.285.15:01:58.55#ibcon#read 4, iclass 36, count 0 2006.285.15:01:58.55#ibcon#about to read 5, iclass 36, count 0 2006.285.15:01:58.55#ibcon#read 5, iclass 36, count 0 2006.285.15:01:58.55#ibcon#about to read 6, iclass 36, count 0 2006.285.15:01:58.55#ibcon#read 6, iclass 36, count 0 2006.285.15:01:58.55#ibcon#end of sib2, iclass 36, count 0 2006.285.15:01:58.55#ibcon#*mode == 0, iclass 36, count 0 2006.285.15:01:58.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.15:01:58.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.15:01:58.55#ibcon#*before write, iclass 36, count 0 2006.285.15:01:58.55#ibcon#enter sib2, iclass 36, count 0 2006.285.15:01:58.55#ibcon#flushed, iclass 36, count 0 2006.285.15:01:58.55#ibcon#about to write, iclass 36, count 0 2006.285.15:01:58.55#ibcon#wrote, iclass 36, count 0 2006.285.15:01:58.55#ibcon#about to read 3, iclass 36, count 0 2006.285.15:01:58.59#ibcon#read 3, iclass 36, count 0 2006.285.15:01:58.59#ibcon#about to read 4, iclass 36, count 0 2006.285.15:01:58.59#ibcon#read 4, iclass 36, count 0 2006.285.15:01:58.59#ibcon#about to read 5, iclass 36, count 0 2006.285.15:01:58.59#ibcon#read 5, iclass 36, count 0 2006.285.15:01:58.59#ibcon#about to read 6, iclass 36, count 0 2006.285.15:01:58.59#ibcon#read 6, iclass 36, count 0 2006.285.15:01:58.59#ibcon#end of sib2, iclass 36, count 0 2006.285.15:01:58.59#ibcon#*after write, iclass 36, count 0 2006.285.15:01:58.59#ibcon#*before return 0, iclass 36, count 0 2006.285.15:01:58.59#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:01:58.59#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:01:58.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.15:01:58.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.15:01:58.59$vck44/va=2,6 2006.285.15:01:58.59#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.15:01:58.59#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.15:01:58.59#ibcon#ireg 11 cls_cnt 2 2006.285.15:01:58.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:01:58.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:01:58.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:01:58.65#ibcon#enter wrdev, iclass 38, count 2 2006.285.15:01:58.65#ibcon#first serial, iclass 38, count 2 2006.285.15:01:58.65#ibcon#enter sib2, iclass 38, count 2 2006.285.15:01:58.65#ibcon#flushed, iclass 38, count 2 2006.285.15:01:58.65#ibcon#about to write, iclass 38, count 2 2006.285.15:01:58.65#ibcon#wrote, iclass 38, count 2 2006.285.15:01:58.65#ibcon#about to read 3, iclass 38, count 2 2006.285.15:01:58.67#ibcon#read 3, iclass 38, count 2 2006.285.15:01:58.67#ibcon#about to read 4, iclass 38, count 2 2006.285.15:01:58.67#ibcon#read 4, iclass 38, count 2 2006.285.15:01:58.67#ibcon#about to read 5, iclass 38, count 2 2006.285.15:01:58.67#ibcon#read 5, iclass 38, count 2 2006.285.15:01:58.67#ibcon#about to read 6, iclass 38, count 2 2006.285.15:01:58.67#ibcon#read 6, iclass 38, count 2 2006.285.15:01:58.67#ibcon#end of sib2, iclass 38, count 2 2006.285.15:01:58.67#ibcon#*mode == 0, iclass 38, count 2 2006.285.15:01:58.67#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.15:01:58.67#ibcon#[25=AT02-06\r\n] 2006.285.15:01:58.67#ibcon#*before write, iclass 38, count 2 2006.285.15:01:58.67#ibcon#enter sib2, iclass 38, count 2 2006.285.15:01:58.67#ibcon#flushed, iclass 38, count 2 2006.285.15:01:58.67#ibcon#about to write, iclass 38, count 2 2006.285.15:01:58.67#ibcon#wrote, iclass 38, count 2 2006.285.15:01:58.67#ibcon#about to read 3, iclass 38, count 2 2006.285.15:01:58.70#ibcon#read 3, iclass 38, count 2 2006.285.15:01:58.70#ibcon#about to read 4, iclass 38, count 2 2006.285.15:01:58.70#ibcon#read 4, iclass 38, count 2 2006.285.15:01:58.70#ibcon#about to read 5, iclass 38, count 2 2006.285.15:01:58.70#ibcon#read 5, iclass 38, count 2 2006.285.15:01:58.70#ibcon#about to read 6, iclass 38, count 2 2006.285.15:01:58.70#ibcon#read 6, iclass 38, count 2 2006.285.15:01:58.70#ibcon#end of sib2, iclass 38, count 2 2006.285.15:01:58.70#ibcon#*after write, iclass 38, count 2 2006.285.15:01:58.70#ibcon#*before return 0, iclass 38, count 2 2006.285.15:01:58.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:01:58.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:01:58.70#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.15:01:58.70#ibcon#ireg 7 cls_cnt 0 2006.285.15:01:58.70#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:01:58.82#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:01:58.82#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:01:58.82#ibcon#enter wrdev, iclass 38, count 0 2006.285.15:01:58.82#ibcon#first serial, iclass 38, count 0 2006.285.15:01:58.82#ibcon#enter sib2, iclass 38, count 0 2006.285.15:01:58.82#ibcon#flushed, iclass 38, count 0 2006.285.15:01:58.82#ibcon#about to write, iclass 38, count 0 2006.285.15:01:58.82#ibcon#wrote, iclass 38, count 0 2006.285.15:01:58.82#ibcon#about to read 3, iclass 38, count 0 2006.285.15:01:58.84#ibcon#read 3, iclass 38, count 0 2006.285.15:01:59.20#ibcon#about to read 4, iclass 38, count 0 2006.285.15:01:59.20#ibcon#read 4, iclass 38, count 0 2006.285.15:01:59.20#ibcon#about to read 5, iclass 38, count 0 2006.285.15:01:59.20#ibcon#read 5, iclass 38, count 0 2006.285.15:01:59.20#ibcon#about to read 6, iclass 38, count 0 2006.285.15:01:59.20#ibcon#read 6, iclass 38, count 0 2006.285.15:01:59.20#ibcon#end of sib2, iclass 38, count 0 2006.285.15:01:59.20#ibcon#*mode == 0, iclass 38, count 0 2006.285.15:01:59.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.15:01:59.21#ibcon#[25=USB\r\n] 2006.285.15:01:59.21#ibcon#*before write, iclass 38, count 0 2006.285.15:01:59.21#ibcon#enter sib2, iclass 38, count 0 2006.285.15:01:59.21#ibcon#flushed, iclass 38, count 0 2006.285.15:01:59.21#ibcon#about to write, iclass 38, count 0 2006.285.15:01:59.21#ibcon#wrote, iclass 38, count 0 2006.285.15:01:59.21#ibcon#about to read 3, iclass 38, count 0 2006.285.15:01:59.23#ibcon#read 3, iclass 38, count 0 2006.285.15:01:59.23#ibcon#about to read 4, iclass 38, count 0 2006.285.15:01:59.23#ibcon#read 4, iclass 38, count 0 2006.285.15:01:59.23#ibcon#about to read 5, iclass 38, count 0 2006.285.15:01:59.23#ibcon#read 5, iclass 38, count 0 2006.285.15:01:59.23#ibcon#about to read 6, iclass 38, count 0 2006.285.15:01:59.23#ibcon#read 6, iclass 38, count 0 2006.285.15:01:59.23#ibcon#end of sib2, iclass 38, count 0 2006.285.15:01:59.23#ibcon#*after write, iclass 38, count 0 2006.285.15:01:59.23#ibcon#*before return 0, iclass 38, count 0 2006.285.15:01:59.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:01:59.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:01:59.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.15:01:59.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.15:01:59.23$vck44/valo=3,564.99 2006.285.15:01:59.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.15:01:59.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.15:01:59.23#ibcon#ireg 17 cls_cnt 0 2006.285.15:01:59.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:01:59.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:01:59.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:01:59.23#ibcon#enter wrdev, iclass 40, count 0 2006.285.15:01:59.23#ibcon#first serial, iclass 40, count 0 2006.285.15:01:59.23#ibcon#enter sib2, iclass 40, count 0 2006.285.15:01:59.23#ibcon#flushed, iclass 40, count 0 2006.285.15:01:59.23#ibcon#about to write, iclass 40, count 0 2006.285.15:01:59.23#ibcon#wrote, iclass 40, count 0 2006.285.15:01:59.23#ibcon#about to read 3, iclass 40, count 0 2006.285.15:01:59.25#ibcon#read 3, iclass 40, count 0 2006.285.15:01:59.25#ibcon#about to read 4, iclass 40, count 0 2006.285.15:01:59.25#ibcon#read 4, iclass 40, count 0 2006.285.15:01:59.25#ibcon#about to read 5, iclass 40, count 0 2006.285.15:01:59.25#ibcon#read 5, iclass 40, count 0 2006.285.15:01:59.25#ibcon#about to read 6, iclass 40, count 0 2006.285.15:01:59.25#ibcon#read 6, iclass 40, count 0 2006.285.15:01:59.25#ibcon#end of sib2, iclass 40, count 0 2006.285.15:01:59.25#ibcon#*mode == 0, iclass 40, count 0 2006.285.15:01:59.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.15:01:59.25#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.15:01:59.25#ibcon#*before write, iclass 40, count 0 2006.285.15:01:59.25#ibcon#enter sib2, iclass 40, count 0 2006.285.15:01:59.25#ibcon#flushed, iclass 40, count 0 2006.285.15:01:59.25#ibcon#about to write, iclass 40, count 0 2006.285.15:01:59.25#ibcon#wrote, iclass 40, count 0 2006.285.15:01:59.25#ibcon#about to read 3, iclass 40, count 0 2006.285.15:01:59.29#ibcon#read 3, iclass 40, count 0 2006.285.15:01:59.29#ibcon#about to read 4, iclass 40, count 0 2006.285.15:01:59.29#ibcon#read 4, iclass 40, count 0 2006.285.15:01:59.29#ibcon#about to read 5, iclass 40, count 0 2006.285.15:01:59.29#ibcon#read 5, iclass 40, count 0 2006.285.15:01:59.29#ibcon#about to read 6, iclass 40, count 0 2006.285.15:01:59.29#ibcon#read 6, iclass 40, count 0 2006.285.15:01:59.29#ibcon#end of sib2, iclass 40, count 0 2006.285.15:01:59.29#ibcon#*after write, iclass 40, count 0 2006.285.15:01:59.29#ibcon#*before return 0, iclass 40, count 0 2006.285.15:01:59.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:01:59.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:01:59.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.15:01:59.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.15:01:59.29$vck44/va=3,7 2006.285.15:01:59.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.15:01:59.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.15:01:59.29#ibcon#ireg 11 cls_cnt 2 2006.285.15:01:59.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:01:59.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:01:59.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:01:59.35#ibcon#enter wrdev, iclass 4, count 2 2006.285.15:01:59.35#ibcon#first serial, iclass 4, count 2 2006.285.15:01:59.35#ibcon#enter sib2, iclass 4, count 2 2006.285.15:01:59.35#ibcon#flushed, iclass 4, count 2 2006.285.15:01:59.35#ibcon#about to write, iclass 4, count 2 2006.285.15:01:59.35#ibcon#wrote, iclass 4, count 2 2006.285.15:01:59.35#ibcon#about to read 3, iclass 4, count 2 2006.285.15:01:59.37#ibcon#read 3, iclass 4, count 2 2006.285.15:01:59.37#ibcon#about to read 4, iclass 4, count 2 2006.285.15:01:59.37#ibcon#read 4, iclass 4, count 2 2006.285.15:01:59.37#ibcon#about to read 5, iclass 4, count 2 2006.285.15:01:59.37#ibcon#read 5, iclass 4, count 2 2006.285.15:01:59.37#ibcon#about to read 6, iclass 4, count 2 2006.285.15:01:59.37#ibcon#read 6, iclass 4, count 2 2006.285.15:01:59.37#ibcon#end of sib2, iclass 4, count 2 2006.285.15:01:59.37#ibcon#*mode == 0, iclass 4, count 2 2006.285.15:01:59.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.15:01:59.37#ibcon#[25=AT03-07\r\n] 2006.285.15:01:59.37#ibcon#*before write, iclass 4, count 2 2006.285.15:01:59.37#ibcon#enter sib2, iclass 4, count 2 2006.285.15:01:59.37#ibcon#flushed, iclass 4, count 2 2006.285.15:01:59.37#ibcon#about to write, iclass 4, count 2 2006.285.15:01:59.37#ibcon#wrote, iclass 4, count 2 2006.285.15:01:59.37#ibcon#about to read 3, iclass 4, count 2 2006.285.15:01:59.40#ibcon#read 3, iclass 4, count 2 2006.285.15:01:59.40#ibcon#about to read 4, iclass 4, count 2 2006.285.15:01:59.40#ibcon#read 4, iclass 4, count 2 2006.285.15:01:59.40#ibcon#about to read 5, iclass 4, count 2 2006.285.15:01:59.40#ibcon#read 5, iclass 4, count 2 2006.285.15:01:59.40#ibcon#about to read 6, iclass 4, count 2 2006.285.15:01:59.40#ibcon#read 6, iclass 4, count 2 2006.285.15:01:59.40#ibcon#end of sib2, iclass 4, count 2 2006.285.15:01:59.40#ibcon#*after write, iclass 4, count 2 2006.285.15:01:59.40#ibcon#*before return 0, iclass 4, count 2 2006.285.15:01:59.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:01:59.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:01:59.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.15:01:59.40#ibcon#ireg 7 cls_cnt 0 2006.285.15:01:59.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:01:59.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:01:59.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:01:59.52#ibcon#enter wrdev, iclass 4, count 0 2006.285.15:01:59.52#ibcon#first serial, iclass 4, count 0 2006.285.15:01:59.52#ibcon#enter sib2, iclass 4, count 0 2006.285.15:01:59.52#ibcon#flushed, iclass 4, count 0 2006.285.15:01:59.52#ibcon#about to write, iclass 4, count 0 2006.285.15:01:59.52#ibcon#wrote, iclass 4, count 0 2006.285.15:01:59.52#ibcon#about to read 3, iclass 4, count 0 2006.285.15:01:59.54#ibcon#read 3, iclass 4, count 0 2006.285.15:01:59.54#ibcon#about to read 4, iclass 4, count 0 2006.285.15:01:59.54#ibcon#read 4, iclass 4, count 0 2006.285.15:01:59.54#ibcon#about to read 5, iclass 4, count 0 2006.285.15:01:59.54#ibcon#read 5, iclass 4, count 0 2006.285.15:01:59.54#ibcon#about to read 6, iclass 4, count 0 2006.285.15:01:59.54#ibcon#read 6, iclass 4, count 0 2006.285.15:01:59.54#ibcon#end of sib2, iclass 4, count 0 2006.285.15:01:59.54#ibcon#*mode == 0, iclass 4, count 0 2006.285.15:01:59.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.15:01:59.54#ibcon#[25=USB\r\n] 2006.285.15:01:59.54#ibcon#*before write, iclass 4, count 0 2006.285.15:01:59.54#ibcon#enter sib2, iclass 4, count 0 2006.285.15:01:59.54#ibcon#flushed, iclass 4, count 0 2006.285.15:01:59.54#ibcon#about to write, iclass 4, count 0 2006.285.15:01:59.54#ibcon#wrote, iclass 4, count 0 2006.285.15:01:59.54#ibcon#about to read 3, iclass 4, count 0 2006.285.15:01:59.57#ibcon#read 3, iclass 4, count 0 2006.285.15:01:59.57#ibcon#about to read 4, iclass 4, count 0 2006.285.15:01:59.57#ibcon#read 4, iclass 4, count 0 2006.285.15:01:59.57#ibcon#about to read 5, iclass 4, count 0 2006.285.15:01:59.57#ibcon#read 5, iclass 4, count 0 2006.285.15:01:59.57#ibcon#about to read 6, iclass 4, count 0 2006.285.15:01:59.57#ibcon#read 6, iclass 4, count 0 2006.285.15:01:59.57#ibcon#end of sib2, iclass 4, count 0 2006.285.15:01:59.57#ibcon#*after write, iclass 4, count 0 2006.285.15:01:59.57#ibcon#*before return 0, iclass 4, count 0 2006.285.15:01:59.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:01:59.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:01:59.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.15:01:59.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.15:01:59.57$vck44/valo=4,624.99 2006.285.15:01:59.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.15:01:59.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.15:01:59.57#ibcon#ireg 17 cls_cnt 0 2006.285.15:01:59.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:01:59.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:01:59.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:01:59.57#ibcon#enter wrdev, iclass 6, count 0 2006.285.15:01:59.57#ibcon#first serial, iclass 6, count 0 2006.285.15:01:59.57#ibcon#enter sib2, iclass 6, count 0 2006.285.15:01:59.57#ibcon#flushed, iclass 6, count 0 2006.285.15:01:59.57#ibcon#about to write, iclass 6, count 0 2006.285.15:01:59.57#ibcon#wrote, iclass 6, count 0 2006.285.15:01:59.57#ibcon#about to read 3, iclass 6, count 0 2006.285.15:01:59.59#ibcon#read 3, iclass 6, count 0 2006.285.15:01:59.81#ibcon#about to read 4, iclass 6, count 0 2006.285.15:01:59.81#ibcon#read 4, iclass 6, count 0 2006.285.15:01:59.81#ibcon#about to read 5, iclass 6, count 0 2006.285.15:01:59.81#ibcon#read 5, iclass 6, count 0 2006.285.15:01:59.81#ibcon#about to read 6, iclass 6, count 0 2006.285.15:01:59.81#ibcon#read 6, iclass 6, count 0 2006.285.15:01:59.81#ibcon#end of sib2, iclass 6, count 0 2006.285.15:01:59.81#ibcon#*mode == 0, iclass 6, count 0 2006.285.15:01:59.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.15:01:59.81#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.15:01:59.81#ibcon#*before write, iclass 6, count 0 2006.285.15:01:59.81#ibcon#enter sib2, iclass 6, count 0 2006.285.15:01:59.81#ibcon#flushed, iclass 6, count 0 2006.285.15:01:59.81#ibcon#about to write, iclass 6, count 0 2006.285.15:01:59.81#ibcon#wrote, iclass 6, count 0 2006.285.15:01:59.81#ibcon#about to read 3, iclass 6, count 0 2006.285.15:01:59.85#ibcon#read 3, iclass 6, count 0 2006.285.15:01:59.85#ibcon#about to read 4, iclass 6, count 0 2006.285.15:01:59.85#ibcon#read 4, iclass 6, count 0 2006.285.15:01:59.85#ibcon#about to read 5, iclass 6, count 0 2006.285.15:01:59.85#ibcon#read 5, iclass 6, count 0 2006.285.15:01:59.85#ibcon#about to read 6, iclass 6, count 0 2006.285.15:01:59.85#ibcon#read 6, iclass 6, count 0 2006.285.15:01:59.85#ibcon#end of sib2, iclass 6, count 0 2006.285.15:01:59.85#ibcon#*after write, iclass 6, count 0 2006.285.15:01:59.85#ibcon#*before return 0, iclass 6, count 0 2006.285.15:01:59.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:01:59.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:01:59.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.15:01:59.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.15:01:59.85$vck44/va=4,6 2006.285.15:01:59.85#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.15:01:59.85#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.15:01:59.85#ibcon#ireg 11 cls_cnt 2 2006.285.15:01:59.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:01:59.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:01:59.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:01:59.85#ibcon#enter wrdev, iclass 10, count 2 2006.285.15:01:59.85#ibcon#first serial, iclass 10, count 2 2006.285.15:01:59.85#ibcon#enter sib2, iclass 10, count 2 2006.285.15:01:59.85#ibcon#flushed, iclass 10, count 2 2006.285.15:01:59.85#ibcon#about to write, iclass 10, count 2 2006.285.15:01:59.85#ibcon#wrote, iclass 10, count 2 2006.285.15:01:59.85#ibcon#about to read 3, iclass 10, count 2 2006.285.15:01:59.87#ibcon#read 3, iclass 10, count 2 2006.285.15:01:59.87#ibcon#about to read 4, iclass 10, count 2 2006.285.15:01:59.87#ibcon#read 4, iclass 10, count 2 2006.285.15:01:59.87#ibcon#about to read 5, iclass 10, count 2 2006.285.15:01:59.87#ibcon#read 5, iclass 10, count 2 2006.285.15:01:59.87#ibcon#about to read 6, iclass 10, count 2 2006.285.15:01:59.87#ibcon#read 6, iclass 10, count 2 2006.285.15:01:59.87#ibcon#end of sib2, iclass 10, count 2 2006.285.15:01:59.87#ibcon#*mode == 0, iclass 10, count 2 2006.285.15:01:59.87#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.15:01:59.87#ibcon#[25=AT04-06\r\n] 2006.285.15:01:59.87#ibcon#*before write, iclass 10, count 2 2006.285.15:01:59.87#ibcon#enter sib2, iclass 10, count 2 2006.285.15:01:59.87#ibcon#flushed, iclass 10, count 2 2006.285.15:01:59.87#ibcon#about to write, iclass 10, count 2 2006.285.15:01:59.87#ibcon#wrote, iclass 10, count 2 2006.285.15:01:59.87#ibcon#about to read 3, iclass 10, count 2 2006.285.15:01:59.90#ibcon#read 3, iclass 10, count 2 2006.285.15:01:59.90#ibcon#about to read 4, iclass 10, count 2 2006.285.15:01:59.90#ibcon#read 4, iclass 10, count 2 2006.285.15:01:59.90#ibcon#about to read 5, iclass 10, count 2 2006.285.15:01:59.90#ibcon#read 5, iclass 10, count 2 2006.285.15:01:59.90#ibcon#about to read 6, iclass 10, count 2 2006.285.15:01:59.90#ibcon#read 6, iclass 10, count 2 2006.285.15:01:59.90#ibcon#end of sib2, iclass 10, count 2 2006.285.15:01:59.90#ibcon#*after write, iclass 10, count 2 2006.285.15:01:59.90#ibcon#*before return 0, iclass 10, count 2 2006.285.15:01:59.90#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:01:59.90#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:01:59.90#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.15:01:59.90#ibcon#ireg 7 cls_cnt 0 2006.285.15:01:59.90#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:02:00.02#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:02:00.02#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:02:00.02#ibcon#enter wrdev, iclass 10, count 0 2006.285.15:02:00.02#ibcon#first serial, iclass 10, count 0 2006.285.15:02:00.02#ibcon#enter sib2, iclass 10, count 0 2006.285.15:02:00.02#ibcon#flushed, iclass 10, count 0 2006.285.15:02:00.02#ibcon#about to write, iclass 10, count 0 2006.285.15:02:00.02#ibcon#wrote, iclass 10, count 0 2006.285.15:02:00.02#ibcon#about to read 3, iclass 10, count 0 2006.285.15:02:00.04#ibcon#read 3, iclass 10, count 0 2006.285.15:02:00.04#ibcon#about to read 4, iclass 10, count 0 2006.285.15:02:00.04#ibcon#read 4, iclass 10, count 0 2006.285.15:02:00.04#ibcon#about to read 5, iclass 10, count 0 2006.285.15:02:00.04#ibcon#read 5, iclass 10, count 0 2006.285.15:02:00.04#ibcon#about to read 6, iclass 10, count 0 2006.285.15:02:00.04#ibcon#read 6, iclass 10, count 0 2006.285.15:02:00.04#ibcon#end of sib2, iclass 10, count 0 2006.285.15:02:00.04#ibcon#*mode == 0, iclass 10, count 0 2006.285.15:02:00.04#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.15:02:00.04#ibcon#[25=USB\r\n] 2006.285.15:02:00.04#ibcon#*before write, iclass 10, count 0 2006.285.15:02:00.04#ibcon#enter sib2, iclass 10, count 0 2006.285.15:02:00.04#ibcon#flushed, iclass 10, count 0 2006.285.15:02:00.04#ibcon#about to write, iclass 10, count 0 2006.285.15:02:00.04#ibcon#wrote, iclass 10, count 0 2006.285.15:02:00.04#ibcon#about to read 3, iclass 10, count 0 2006.285.15:02:00.07#ibcon#read 3, iclass 10, count 0 2006.285.15:02:00.07#ibcon#about to read 4, iclass 10, count 0 2006.285.15:02:00.07#ibcon#read 4, iclass 10, count 0 2006.285.15:02:00.07#ibcon#about to read 5, iclass 10, count 0 2006.285.15:02:00.07#ibcon#read 5, iclass 10, count 0 2006.285.15:02:00.07#ibcon#about to read 6, iclass 10, count 0 2006.285.15:02:00.07#ibcon#read 6, iclass 10, count 0 2006.285.15:02:00.07#ibcon#end of sib2, iclass 10, count 0 2006.285.15:02:00.07#ibcon#*after write, iclass 10, count 0 2006.285.15:02:00.07#ibcon#*before return 0, iclass 10, count 0 2006.285.15:02:00.07#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:02:00.07#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:02:00.07#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.15:02:00.07#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.15:02:00.07$vck44/valo=5,734.99 2006.285.15:02:00.07#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.15:02:00.07#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.15:02:00.07#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:00.07#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:02:00.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:02:00.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:02:00.07#ibcon#enter wrdev, iclass 12, count 0 2006.285.15:02:00.07#ibcon#first serial, iclass 12, count 0 2006.285.15:02:00.07#ibcon#enter sib2, iclass 12, count 0 2006.285.15:02:00.07#ibcon#flushed, iclass 12, count 0 2006.285.15:02:00.07#ibcon#about to write, iclass 12, count 0 2006.285.15:02:00.07#ibcon#wrote, iclass 12, count 0 2006.285.15:02:00.07#ibcon#about to read 3, iclass 12, count 0 2006.285.15:02:00.09#ibcon#read 3, iclass 12, count 0 2006.285.15:02:00.09#ibcon#about to read 4, iclass 12, count 0 2006.285.15:02:00.09#ibcon#read 4, iclass 12, count 0 2006.285.15:02:00.09#ibcon#about to read 5, iclass 12, count 0 2006.285.15:02:00.09#ibcon#read 5, iclass 12, count 0 2006.285.15:02:00.09#ibcon#about to read 6, iclass 12, count 0 2006.285.15:02:00.09#ibcon#read 6, iclass 12, count 0 2006.285.15:02:00.09#ibcon#end of sib2, iclass 12, count 0 2006.285.15:02:00.09#ibcon#*mode == 0, iclass 12, count 0 2006.285.15:02:00.09#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.15:02:00.09#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.15:02:00.09#ibcon#*before write, iclass 12, count 0 2006.285.15:02:00.09#ibcon#enter sib2, iclass 12, count 0 2006.285.15:02:00.09#ibcon#flushed, iclass 12, count 0 2006.285.15:02:00.09#ibcon#about to write, iclass 12, count 0 2006.285.15:02:00.09#ibcon#wrote, iclass 12, count 0 2006.285.15:02:00.09#ibcon#about to read 3, iclass 12, count 0 2006.285.15:02:00.13#ibcon#read 3, iclass 12, count 0 2006.285.15:02:00.13#ibcon#about to read 4, iclass 12, count 0 2006.285.15:02:00.13#ibcon#read 4, iclass 12, count 0 2006.285.15:02:00.13#ibcon#about to read 5, iclass 12, count 0 2006.285.15:02:00.13#ibcon#read 5, iclass 12, count 0 2006.285.15:02:00.13#ibcon#about to read 6, iclass 12, count 0 2006.285.15:02:00.13#ibcon#read 6, iclass 12, count 0 2006.285.15:02:00.13#ibcon#end of sib2, iclass 12, count 0 2006.285.15:02:00.13#ibcon#*after write, iclass 12, count 0 2006.285.15:02:00.13#ibcon#*before return 0, iclass 12, count 0 2006.285.15:02:00.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:02:00.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:02:00.13#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.15:02:00.13#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.15:02:00.13$vck44/va=5,3 2006.285.15:02:00.13#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.15:02:00.13#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.15:02:00.13#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:00.13#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:02:00.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:02:00.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:02:00.19#ibcon#enter wrdev, iclass 14, count 2 2006.285.15:02:00.19#ibcon#first serial, iclass 14, count 2 2006.285.15:02:00.19#ibcon#enter sib2, iclass 14, count 2 2006.285.15:02:00.19#ibcon#flushed, iclass 14, count 2 2006.285.15:02:00.19#ibcon#about to write, iclass 14, count 2 2006.285.15:02:00.19#ibcon#wrote, iclass 14, count 2 2006.285.15:02:00.19#ibcon#about to read 3, iclass 14, count 2 2006.285.15:02:00.21#ibcon#read 3, iclass 14, count 2 2006.285.15:02:00.21#ibcon#about to read 4, iclass 14, count 2 2006.285.15:02:00.21#ibcon#read 4, iclass 14, count 2 2006.285.15:02:00.21#ibcon#about to read 5, iclass 14, count 2 2006.285.15:02:00.21#ibcon#read 5, iclass 14, count 2 2006.285.15:02:00.21#ibcon#about to read 6, iclass 14, count 2 2006.285.15:02:00.21#ibcon#read 6, iclass 14, count 2 2006.285.15:02:00.21#ibcon#end of sib2, iclass 14, count 2 2006.285.15:02:00.21#ibcon#*mode == 0, iclass 14, count 2 2006.285.15:02:00.21#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.15:02:00.21#ibcon#[25=AT05-03\r\n] 2006.285.15:02:00.21#ibcon#*before write, iclass 14, count 2 2006.285.15:02:00.21#ibcon#enter sib2, iclass 14, count 2 2006.285.15:02:00.21#ibcon#flushed, iclass 14, count 2 2006.285.15:02:00.21#ibcon#about to write, iclass 14, count 2 2006.285.15:02:00.21#ibcon#wrote, iclass 14, count 2 2006.285.15:02:00.21#ibcon#about to read 3, iclass 14, count 2 2006.285.15:02:00.24#ibcon#read 3, iclass 14, count 2 2006.285.15:02:00.24#ibcon#about to read 4, iclass 14, count 2 2006.285.15:02:00.24#ibcon#read 4, iclass 14, count 2 2006.285.15:02:00.24#ibcon#about to read 5, iclass 14, count 2 2006.285.15:02:00.24#ibcon#read 5, iclass 14, count 2 2006.285.15:02:00.24#ibcon#about to read 6, iclass 14, count 2 2006.285.15:02:00.24#ibcon#read 6, iclass 14, count 2 2006.285.15:02:00.24#ibcon#end of sib2, iclass 14, count 2 2006.285.15:02:00.24#ibcon#*after write, iclass 14, count 2 2006.285.15:02:00.24#ibcon#*before return 0, iclass 14, count 2 2006.285.15:02:00.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:02:00.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:02:00.24#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.15:02:00.24#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:00.24#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:02:00.36#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:02:00.36#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:02:00.36#ibcon#enter wrdev, iclass 14, count 0 2006.285.15:02:00.36#ibcon#first serial, iclass 14, count 0 2006.285.15:02:00.36#ibcon#enter sib2, iclass 14, count 0 2006.285.15:02:00.36#ibcon#flushed, iclass 14, count 0 2006.285.15:02:00.36#ibcon#about to write, iclass 14, count 0 2006.285.15:02:00.36#ibcon#wrote, iclass 14, count 0 2006.285.15:02:00.36#ibcon#about to read 3, iclass 14, count 0 2006.285.15:02:00.38#ibcon#read 3, iclass 14, count 0 2006.285.15:02:00.38#ibcon#about to read 4, iclass 14, count 0 2006.285.15:02:00.38#ibcon#read 4, iclass 14, count 0 2006.285.15:02:00.38#ibcon#about to read 5, iclass 14, count 0 2006.285.15:02:00.38#ibcon#read 5, iclass 14, count 0 2006.285.15:02:00.38#ibcon#about to read 6, iclass 14, count 0 2006.285.15:02:00.38#ibcon#read 6, iclass 14, count 0 2006.285.15:02:00.38#ibcon#end of sib2, iclass 14, count 0 2006.285.15:02:00.38#ibcon#*mode == 0, iclass 14, count 0 2006.285.15:02:00.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.15:02:00.38#ibcon#[25=USB\r\n] 2006.285.15:02:00.38#ibcon#*before write, iclass 14, count 0 2006.285.15:02:00.38#ibcon#enter sib2, iclass 14, count 0 2006.285.15:02:00.38#ibcon#flushed, iclass 14, count 0 2006.285.15:02:00.38#ibcon#about to write, iclass 14, count 0 2006.285.15:02:00.38#ibcon#wrote, iclass 14, count 0 2006.285.15:02:00.38#ibcon#about to read 3, iclass 14, count 0 2006.285.15:02:00.41#ibcon#read 3, iclass 14, count 0 2006.285.15:02:00.41#ibcon#about to read 4, iclass 14, count 0 2006.285.15:02:00.41#ibcon#read 4, iclass 14, count 0 2006.285.15:02:00.41#ibcon#about to read 5, iclass 14, count 0 2006.285.15:02:00.41#ibcon#read 5, iclass 14, count 0 2006.285.15:02:00.41#ibcon#about to read 6, iclass 14, count 0 2006.285.15:02:00.41#ibcon#read 6, iclass 14, count 0 2006.285.15:02:00.41#ibcon#end of sib2, iclass 14, count 0 2006.285.15:02:00.41#ibcon#*after write, iclass 14, count 0 2006.285.15:02:00.41#ibcon#*before return 0, iclass 14, count 0 2006.285.15:02:00.41#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:02:00.41#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:02:00.41#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.15:02:00.41#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.15:02:00.41$vck44/valo=6,814.99 2006.285.15:02:00.41#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.15:02:00.41#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.15:02:00.41#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:00.41#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:02:00.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:02:00.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:02:00.41#ibcon#enter wrdev, iclass 16, count 0 2006.285.15:02:00.41#ibcon#first serial, iclass 16, count 0 2006.285.15:02:00.41#ibcon#enter sib2, iclass 16, count 0 2006.285.15:02:00.41#ibcon#flushed, iclass 16, count 0 2006.285.15:02:00.41#ibcon#about to write, iclass 16, count 0 2006.285.15:02:00.41#ibcon#wrote, iclass 16, count 0 2006.285.15:02:00.41#ibcon#about to read 3, iclass 16, count 0 2006.285.15:02:00.43#ibcon#read 3, iclass 16, count 0 2006.285.15:02:00.43#ibcon#about to read 4, iclass 16, count 0 2006.285.15:02:00.43#ibcon#read 4, iclass 16, count 0 2006.285.15:02:00.43#ibcon#about to read 5, iclass 16, count 0 2006.285.15:02:00.43#ibcon#read 5, iclass 16, count 0 2006.285.15:02:00.43#ibcon#about to read 6, iclass 16, count 0 2006.285.15:02:00.43#ibcon#read 6, iclass 16, count 0 2006.285.15:02:00.43#ibcon#end of sib2, iclass 16, count 0 2006.285.15:02:00.43#ibcon#*mode == 0, iclass 16, count 0 2006.285.15:02:00.43#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.15:02:00.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.15:02:00.43#ibcon#*before write, iclass 16, count 0 2006.285.15:02:00.43#ibcon#enter sib2, iclass 16, count 0 2006.285.15:02:00.43#ibcon#flushed, iclass 16, count 0 2006.285.15:02:00.43#ibcon#about to write, iclass 16, count 0 2006.285.15:02:00.43#ibcon#wrote, iclass 16, count 0 2006.285.15:02:00.43#ibcon#about to read 3, iclass 16, count 0 2006.285.15:02:00.47#ibcon#read 3, iclass 16, count 0 2006.285.15:02:00.47#ibcon#about to read 4, iclass 16, count 0 2006.285.15:02:00.47#ibcon#read 4, iclass 16, count 0 2006.285.15:02:00.47#ibcon#about to read 5, iclass 16, count 0 2006.285.15:02:00.47#ibcon#read 5, iclass 16, count 0 2006.285.15:02:00.47#ibcon#about to read 6, iclass 16, count 0 2006.285.15:02:00.47#ibcon#read 6, iclass 16, count 0 2006.285.15:02:00.47#ibcon#end of sib2, iclass 16, count 0 2006.285.15:02:00.47#ibcon#*after write, iclass 16, count 0 2006.285.15:02:00.47#ibcon#*before return 0, iclass 16, count 0 2006.285.15:02:00.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:02:00.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:02:00.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.15:02:00.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.15:02:00.47$vck44/va=6,4 2006.285.15:02:00.47#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.15:02:00.47#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.15:02:00.47#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:00.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:02:00.52#abcon#<5=/03 2.0 3.6 19.15 931014.9\r\n> 2006.285.15:02:00.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:02:00.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:02:00.53#ibcon#enter wrdev, iclass 18, count 2 2006.285.15:02:00.53#ibcon#first serial, iclass 18, count 2 2006.285.15:02:00.53#ibcon#enter sib2, iclass 18, count 2 2006.285.15:02:00.53#ibcon#flushed, iclass 18, count 2 2006.285.15:02:00.53#ibcon#about to write, iclass 18, count 2 2006.285.15:02:00.53#ibcon#wrote, iclass 18, count 2 2006.285.15:02:00.53#ibcon#about to read 3, iclass 18, count 2 2006.285.15:02:00.54#abcon#{5=INTERFACE CLEAR} 2006.285.15:02:00.55#ibcon#read 3, iclass 18, count 2 2006.285.15:02:00.55#ibcon#about to read 4, iclass 18, count 2 2006.285.15:02:00.55#ibcon#read 4, iclass 18, count 2 2006.285.15:02:00.55#ibcon#about to read 5, iclass 18, count 2 2006.285.15:02:00.55#ibcon#read 5, iclass 18, count 2 2006.285.15:02:00.55#ibcon#about to read 6, iclass 18, count 2 2006.285.15:02:00.55#ibcon#read 6, iclass 18, count 2 2006.285.15:02:00.55#ibcon#end of sib2, iclass 18, count 2 2006.285.15:02:00.55#ibcon#*mode == 0, iclass 18, count 2 2006.285.15:02:00.55#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.15:02:00.55#ibcon#[25=AT06-04\r\n] 2006.285.15:02:00.55#ibcon#*before write, iclass 18, count 2 2006.285.15:02:00.55#ibcon#enter sib2, iclass 18, count 2 2006.285.15:02:00.55#ibcon#flushed, iclass 18, count 2 2006.285.15:02:00.55#ibcon#about to write, iclass 18, count 2 2006.285.15:02:00.55#ibcon#wrote, iclass 18, count 2 2006.285.15:02:00.55#ibcon#about to read 3, iclass 18, count 2 2006.285.15:02:00.58#ibcon#read 3, iclass 18, count 2 2006.285.15:02:00.58#ibcon#about to read 4, iclass 18, count 2 2006.285.15:02:00.58#ibcon#read 4, iclass 18, count 2 2006.285.15:02:00.58#ibcon#about to read 5, iclass 18, count 2 2006.285.15:02:00.58#ibcon#read 5, iclass 18, count 2 2006.285.15:02:00.58#ibcon#about to read 6, iclass 18, count 2 2006.285.15:02:00.58#ibcon#read 6, iclass 18, count 2 2006.285.15:02:00.58#ibcon#end of sib2, iclass 18, count 2 2006.285.15:02:00.58#ibcon#*after write, iclass 18, count 2 2006.285.15:02:00.58#ibcon#*before return 0, iclass 18, count 2 2006.285.15:02:00.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:02:00.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:02:00.58#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.15:02:00.58#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:00.58#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:02:00.60#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:02:00.70#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:02:00.70#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:02:00.70#ibcon#enter wrdev, iclass 18, count 0 2006.285.15:02:00.70#ibcon#first serial, iclass 18, count 0 2006.285.15:02:00.70#ibcon#enter sib2, iclass 18, count 0 2006.285.15:02:00.70#ibcon#flushed, iclass 18, count 0 2006.285.15:02:00.70#ibcon#about to write, iclass 18, count 0 2006.285.15:02:00.70#ibcon#wrote, iclass 18, count 0 2006.285.15:02:00.70#ibcon#about to read 3, iclass 18, count 0 2006.285.15:02:00.72#ibcon#read 3, iclass 18, count 0 2006.285.15:02:00.72#ibcon#about to read 4, iclass 18, count 0 2006.285.15:02:00.72#ibcon#read 4, iclass 18, count 0 2006.285.15:02:00.72#ibcon#about to read 5, iclass 18, count 0 2006.285.15:02:00.72#ibcon#read 5, iclass 18, count 0 2006.285.15:02:00.72#ibcon#about to read 6, iclass 18, count 0 2006.285.15:02:00.72#ibcon#read 6, iclass 18, count 0 2006.285.15:02:00.72#ibcon#end of sib2, iclass 18, count 0 2006.285.15:02:00.72#ibcon#*mode == 0, iclass 18, count 0 2006.285.15:02:00.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.15:02:00.72#ibcon#[25=USB\r\n] 2006.285.15:02:00.72#ibcon#*before write, iclass 18, count 0 2006.285.15:02:00.72#ibcon#enter sib2, iclass 18, count 0 2006.285.15:02:00.72#ibcon#flushed, iclass 18, count 0 2006.285.15:02:00.72#ibcon#about to write, iclass 18, count 0 2006.285.15:02:00.72#ibcon#wrote, iclass 18, count 0 2006.285.15:02:00.72#ibcon#about to read 3, iclass 18, count 0 2006.285.15:02:00.75#ibcon#read 3, iclass 18, count 0 2006.285.15:02:00.75#ibcon#about to read 4, iclass 18, count 0 2006.285.15:02:00.75#ibcon#read 4, iclass 18, count 0 2006.285.15:02:00.75#ibcon#about to read 5, iclass 18, count 0 2006.285.15:02:00.75#ibcon#read 5, iclass 18, count 0 2006.285.15:02:00.75#ibcon#about to read 6, iclass 18, count 0 2006.285.15:02:00.75#ibcon#read 6, iclass 18, count 0 2006.285.15:02:00.75#ibcon#end of sib2, iclass 18, count 0 2006.285.15:02:00.75#ibcon#*after write, iclass 18, count 0 2006.285.15:02:00.75#ibcon#*before return 0, iclass 18, count 0 2006.285.15:02:00.75#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:02:00.75#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:02:00.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.15:02:00.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.15:02:00.75$vck44/valo=7,864.99 2006.285.15:02:00.75#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.15:02:00.75#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.15:02:00.75#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:00.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:02:00.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:02:00.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:02:00.75#ibcon#enter wrdev, iclass 24, count 0 2006.285.15:02:00.75#ibcon#first serial, iclass 24, count 0 2006.285.15:02:00.75#ibcon#enter sib2, iclass 24, count 0 2006.285.15:02:00.75#ibcon#flushed, iclass 24, count 0 2006.285.15:02:00.75#ibcon#about to write, iclass 24, count 0 2006.285.15:02:00.75#ibcon#wrote, iclass 24, count 0 2006.285.15:02:00.75#ibcon#about to read 3, iclass 24, count 0 2006.285.15:02:00.77#ibcon#read 3, iclass 24, count 0 2006.285.15:02:01.01#ibcon#about to read 4, iclass 24, count 0 2006.285.15:02:01.01#ibcon#read 4, iclass 24, count 0 2006.285.15:02:01.01#ibcon#about to read 5, iclass 24, count 0 2006.285.15:02:01.01#ibcon#read 5, iclass 24, count 0 2006.285.15:02:01.01#ibcon#about to read 6, iclass 24, count 0 2006.285.15:02:01.01#ibcon#read 6, iclass 24, count 0 2006.285.15:02:01.01#ibcon#end of sib2, iclass 24, count 0 2006.285.15:02:01.01#ibcon#*mode == 0, iclass 24, count 0 2006.285.15:02:01.01#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.15:02:01.01#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.15:02:01.01#ibcon#*before write, iclass 24, count 0 2006.285.15:02:01.01#ibcon#enter sib2, iclass 24, count 0 2006.285.15:02:01.01#ibcon#flushed, iclass 24, count 0 2006.285.15:02:01.01#ibcon#about to write, iclass 24, count 0 2006.285.15:02:01.01#ibcon#wrote, iclass 24, count 0 2006.285.15:02:01.01#ibcon#about to read 3, iclass 24, count 0 2006.285.15:02:01.05#ibcon#read 3, iclass 24, count 0 2006.285.15:02:01.05#ibcon#about to read 4, iclass 24, count 0 2006.285.15:02:01.05#ibcon#read 4, iclass 24, count 0 2006.285.15:02:01.05#ibcon#about to read 5, iclass 24, count 0 2006.285.15:02:01.05#ibcon#read 5, iclass 24, count 0 2006.285.15:02:01.05#ibcon#about to read 6, iclass 24, count 0 2006.285.15:02:01.05#ibcon#read 6, iclass 24, count 0 2006.285.15:02:01.05#ibcon#end of sib2, iclass 24, count 0 2006.285.15:02:01.05#ibcon#*after write, iclass 24, count 0 2006.285.15:02:01.05#ibcon#*before return 0, iclass 24, count 0 2006.285.15:02:01.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:02:01.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:02:01.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.15:02:01.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.15:02:01.05$vck44/va=7,4 2006.285.15:02:01.05#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.15:02:01.05#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.15:02:01.05#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:01.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:02:01.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:02:01.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:02:01.05#ibcon#enter wrdev, iclass 26, count 2 2006.285.15:02:01.05#ibcon#first serial, iclass 26, count 2 2006.285.15:02:01.05#ibcon#enter sib2, iclass 26, count 2 2006.285.15:02:01.05#ibcon#flushed, iclass 26, count 2 2006.285.15:02:01.05#ibcon#about to write, iclass 26, count 2 2006.285.15:02:01.05#ibcon#wrote, iclass 26, count 2 2006.285.15:02:01.05#ibcon#about to read 3, iclass 26, count 2 2006.285.15:02:01.07#ibcon#read 3, iclass 26, count 2 2006.285.15:02:01.07#ibcon#about to read 4, iclass 26, count 2 2006.285.15:02:01.07#ibcon#read 4, iclass 26, count 2 2006.285.15:02:01.07#ibcon#about to read 5, iclass 26, count 2 2006.285.15:02:01.07#ibcon#read 5, iclass 26, count 2 2006.285.15:02:01.07#ibcon#about to read 6, iclass 26, count 2 2006.285.15:02:01.07#ibcon#read 6, iclass 26, count 2 2006.285.15:02:01.07#ibcon#end of sib2, iclass 26, count 2 2006.285.15:02:01.07#ibcon#*mode == 0, iclass 26, count 2 2006.285.15:02:01.07#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.15:02:01.07#ibcon#[25=AT07-04\r\n] 2006.285.15:02:01.07#ibcon#*before write, iclass 26, count 2 2006.285.15:02:01.07#ibcon#enter sib2, iclass 26, count 2 2006.285.15:02:01.07#ibcon#flushed, iclass 26, count 2 2006.285.15:02:01.07#ibcon#about to write, iclass 26, count 2 2006.285.15:02:01.07#ibcon#wrote, iclass 26, count 2 2006.285.15:02:01.07#ibcon#about to read 3, iclass 26, count 2 2006.285.15:02:01.10#ibcon#read 3, iclass 26, count 2 2006.285.15:02:01.10#ibcon#about to read 4, iclass 26, count 2 2006.285.15:02:01.10#ibcon#read 4, iclass 26, count 2 2006.285.15:02:01.10#ibcon#about to read 5, iclass 26, count 2 2006.285.15:02:01.10#ibcon#read 5, iclass 26, count 2 2006.285.15:02:01.10#ibcon#about to read 6, iclass 26, count 2 2006.285.15:02:01.10#ibcon#read 6, iclass 26, count 2 2006.285.15:02:01.10#ibcon#end of sib2, iclass 26, count 2 2006.285.15:02:01.10#ibcon#*after write, iclass 26, count 2 2006.285.15:02:01.10#ibcon#*before return 0, iclass 26, count 2 2006.285.15:02:01.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:02:01.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:02:01.10#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.15:02:01.10#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:01.10#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:02:01.22#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:02:01.22#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:02:01.22#ibcon#enter wrdev, iclass 26, count 0 2006.285.15:02:01.22#ibcon#first serial, iclass 26, count 0 2006.285.15:02:01.22#ibcon#enter sib2, iclass 26, count 0 2006.285.15:02:01.22#ibcon#flushed, iclass 26, count 0 2006.285.15:02:01.22#ibcon#about to write, iclass 26, count 0 2006.285.15:02:01.22#ibcon#wrote, iclass 26, count 0 2006.285.15:02:01.22#ibcon#about to read 3, iclass 26, count 0 2006.285.15:02:01.24#ibcon#read 3, iclass 26, count 0 2006.285.15:02:01.24#ibcon#about to read 4, iclass 26, count 0 2006.285.15:02:01.24#ibcon#read 4, iclass 26, count 0 2006.285.15:02:01.24#ibcon#about to read 5, iclass 26, count 0 2006.285.15:02:01.24#ibcon#read 5, iclass 26, count 0 2006.285.15:02:01.24#ibcon#about to read 6, iclass 26, count 0 2006.285.15:02:01.24#ibcon#read 6, iclass 26, count 0 2006.285.15:02:01.24#ibcon#end of sib2, iclass 26, count 0 2006.285.15:02:01.24#ibcon#*mode == 0, iclass 26, count 0 2006.285.15:02:01.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.15:02:01.24#ibcon#[25=USB\r\n] 2006.285.15:02:01.24#ibcon#*before write, iclass 26, count 0 2006.285.15:02:01.24#ibcon#enter sib2, iclass 26, count 0 2006.285.15:02:01.24#ibcon#flushed, iclass 26, count 0 2006.285.15:02:01.24#ibcon#about to write, iclass 26, count 0 2006.285.15:02:01.24#ibcon#wrote, iclass 26, count 0 2006.285.15:02:01.24#ibcon#about to read 3, iclass 26, count 0 2006.285.15:02:01.27#ibcon#read 3, iclass 26, count 0 2006.285.15:02:01.27#ibcon#about to read 4, iclass 26, count 0 2006.285.15:02:01.27#ibcon#read 4, iclass 26, count 0 2006.285.15:02:01.27#ibcon#about to read 5, iclass 26, count 0 2006.285.15:02:01.27#ibcon#read 5, iclass 26, count 0 2006.285.15:02:01.27#ibcon#about to read 6, iclass 26, count 0 2006.285.15:02:01.27#ibcon#read 6, iclass 26, count 0 2006.285.15:02:01.27#ibcon#end of sib2, iclass 26, count 0 2006.285.15:02:01.27#ibcon#*after write, iclass 26, count 0 2006.285.15:02:01.27#ibcon#*before return 0, iclass 26, count 0 2006.285.15:02:01.27#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:02:01.27#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:02:01.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.15:02:01.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.15:02:01.27$vck44/valo=8,884.99 2006.285.15:02:01.27#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.15:02:01.27#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.15:02:01.27#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:01.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:02:01.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:02:01.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:02:01.27#ibcon#enter wrdev, iclass 28, count 0 2006.285.15:02:01.27#ibcon#first serial, iclass 28, count 0 2006.285.15:02:01.27#ibcon#enter sib2, iclass 28, count 0 2006.285.15:02:01.27#ibcon#flushed, iclass 28, count 0 2006.285.15:02:01.27#ibcon#about to write, iclass 28, count 0 2006.285.15:02:01.27#ibcon#wrote, iclass 28, count 0 2006.285.15:02:01.27#ibcon#about to read 3, iclass 28, count 0 2006.285.15:02:01.29#ibcon#read 3, iclass 28, count 0 2006.285.15:02:01.29#ibcon#about to read 4, iclass 28, count 0 2006.285.15:02:01.29#ibcon#read 4, iclass 28, count 0 2006.285.15:02:01.29#ibcon#about to read 5, iclass 28, count 0 2006.285.15:02:01.29#ibcon#read 5, iclass 28, count 0 2006.285.15:02:01.29#ibcon#about to read 6, iclass 28, count 0 2006.285.15:02:01.29#ibcon#read 6, iclass 28, count 0 2006.285.15:02:01.29#ibcon#end of sib2, iclass 28, count 0 2006.285.15:02:01.29#ibcon#*mode == 0, iclass 28, count 0 2006.285.15:02:01.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.15:02:01.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.15:02:01.29#ibcon#*before write, iclass 28, count 0 2006.285.15:02:01.29#ibcon#enter sib2, iclass 28, count 0 2006.285.15:02:01.29#ibcon#flushed, iclass 28, count 0 2006.285.15:02:01.29#ibcon#about to write, iclass 28, count 0 2006.285.15:02:01.29#ibcon#wrote, iclass 28, count 0 2006.285.15:02:01.29#ibcon#about to read 3, iclass 28, count 0 2006.285.15:02:01.33#ibcon#read 3, iclass 28, count 0 2006.285.15:02:01.33#ibcon#about to read 4, iclass 28, count 0 2006.285.15:02:01.33#ibcon#read 4, iclass 28, count 0 2006.285.15:02:01.33#ibcon#about to read 5, iclass 28, count 0 2006.285.15:02:01.33#ibcon#read 5, iclass 28, count 0 2006.285.15:02:01.33#ibcon#about to read 6, iclass 28, count 0 2006.285.15:02:01.33#ibcon#read 6, iclass 28, count 0 2006.285.15:02:01.33#ibcon#end of sib2, iclass 28, count 0 2006.285.15:02:01.33#ibcon#*after write, iclass 28, count 0 2006.285.15:02:01.33#ibcon#*before return 0, iclass 28, count 0 2006.285.15:02:01.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:02:01.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:02:01.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.15:02:01.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.15:02:01.33$vck44/va=8,3 2006.285.15:02:01.33#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.15:02:01.33#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.15:02:01.33#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:01.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:02:01.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:02:01.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:02:01.39#ibcon#enter wrdev, iclass 30, count 2 2006.285.15:02:01.39#ibcon#first serial, iclass 30, count 2 2006.285.15:02:01.39#ibcon#enter sib2, iclass 30, count 2 2006.285.15:02:01.39#ibcon#flushed, iclass 30, count 2 2006.285.15:02:01.39#ibcon#about to write, iclass 30, count 2 2006.285.15:02:01.39#ibcon#wrote, iclass 30, count 2 2006.285.15:02:01.39#ibcon#about to read 3, iclass 30, count 2 2006.285.15:02:01.41#ibcon#read 3, iclass 30, count 2 2006.285.15:02:01.41#ibcon#about to read 4, iclass 30, count 2 2006.285.15:02:01.41#ibcon#read 4, iclass 30, count 2 2006.285.15:02:01.41#ibcon#about to read 5, iclass 30, count 2 2006.285.15:02:01.41#ibcon#read 5, iclass 30, count 2 2006.285.15:02:01.41#ibcon#about to read 6, iclass 30, count 2 2006.285.15:02:01.41#ibcon#read 6, iclass 30, count 2 2006.285.15:02:01.41#ibcon#end of sib2, iclass 30, count 2 2006.285.15:02:01.41#ibcon#*mode == 0, iclass 30, count 2 2006.285.15:02:01.41#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.15:02:01.41#ibcon#[25=AT08-03\r\n] 2006.285.15:02:01.41#ibcon#*before write, iclass 30, count 2 2006.285.15:02:01.41#ibcon#enter sib2, iclass 30, count 2 2006.285.15:02:01.41#ibcon#flushed, iclass 30, count 2 2006.285.15:02:01.41#ibcon#about to write, iclass 30, count 2 2006.285.15:02:01.41#ibcon#wrote, iclass 30, count 2 2006.285.15:02:01.41#ibcon#about to read 3, iclass 30, count 2 2006.285.15:02:01.44#ibcon#read 3, iclass 30, count 2 2006.285.15:02:01.44#ibcon#about to read 4, iclass 30, count 2 2006.285.15:02:01.44#ibcon#read 4, iclass 30, count 2 2006.285.15:02:01.44#ibcon#about to read 5, iclass 30, count 2 2006.285.15:02:01.44#ibcon#read 5, iclass 30, count 2 2006.285.15:02:01.44#ibcon#about to read 6, iclass 30, count 2 2006.285.15:02:01.44#ibcon#read 6, iclass 30, count 2 2006.285.15:02:01.44#ibcon#end of sib2, iclass 30, count 2 2006.285.15:02:01.44#ibcon#*after write, iclass 30, count 2 2006.285.15:02:01.44#ibcon#*before return 0, iclass 30, count 2 2006.285.15:02:01.44#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:02:01.44#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:02:01.44#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.15:02:01.44#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:01.44#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:02:01.56#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:02:01.56#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:02:01.56#ibcon#enter wrdev, iclass 30, count 0 2006.285.15:02:01.56#ibcon#first serial, iclass 30, count 0 2006.285.15:02:01.56#ibcon#enter sib2, iclass 30, count 0 2006.285.15:02:01.56#ibcon#flushed, iclass 30, count 0 2006.285.15:02:01.56#ibcon#about to write, iclass 30, count 0 2006.285.15:02:01.56#ibcon#wrote, iclass 30, count 0 2006.285.15:02:01.56#ibcon#about to read 3, iclass 30, count 0 2006.285.15:02:01.58#ibcon#read 3, iclass 30, count 0 2006.285.15:02:01.58#ibcon#about to read 4, iclass 30, count 0 2006.285.15:02:01.58#ibcon#read 4, iclass 30, count 0 2006.285.15:02:01.58#ibcon#about to read 5, iclass 30, count 0 2006.285.15:02:01.58#ibcon#read 5, iclass 30, count 0 2006.285.15:02:01.58#ibcon#about to read 6, iclass 30, count 0 2006.285.15:02:01.58#ibcon#read 6, iclass 30, count 0 2006.285.15:02:01.58#ibcon#end of sib2, iclass 30, count 0 2006.285.15:02:01.58#ibcon#*mode == 0, iclass 30, count 0 2006.285.15:02:01.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.15:02:01.58#ibcon#[25=USB\r\n] 2006.285.15:02:01.58#ibcon#*before write, iclass 30, count 0 2006.285.15:02:01.58#ibcon#enter sib2, iclass 30, count 0 2006.285.15:02:01.58#ibcon#flushed, iclass 30, count 0 2006.285.15:02:01.58#ibcon#about to write, iclass 30, count 0 2006.285.15:02:01.58#ibcon#wrote, iclass 30, count 0 2006.285.15:02:01.58#ibcon#about to read 3, iclass 30, count 0 2006.285.15:02:01.61#ibcon#read 3, iclass 30, count 0 2006.285.15:02:01.61#ibcon#about to read 4, iclass 30, count 0 2006.285.15:02:01.61#ibcon#read 4, iclass 30, count 0 2006.285.15:02:01.61#ibcon#about to read 5, iclass 30, count 0 2006.285.15:02:01.61#ibcon#read 5, iclass 30, count 0 2006.285.15:02:01.61#ibcon#about to read 6, iclass 30, count 0 2006.285.15:02:01.61#ibcon#read 6, iclass 30, count 0 2006.285.15:02:01.61#ibcon#end of sib2, iclass 30, count 0 2006.285.15:02:01.61#ibcon#*after write, iclass 30, count 0 2006.285.15:02:01.61#ibcon#*before return 0, iclass 30, count 0 2006.285.15:02:01.61#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:02:01.61#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:02:01.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.15:02:01.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.15:02:01.61$vck44/vblo=1,629.99 2006.285.15:02:01.61#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.15:02:01.61#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.15:02:01.61#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:01.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:02:01.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:02:01.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:02:01.61#ibcon#enter wrdev, iclass 32, count 0 2006.285.15:02:01.61#ibcon#first serial, iclass 32, count 0 2006.285.15:02:01.61#ibcon#enter sib2, iclass 32, count 0 2006.285.15:02:01.61#ibcon#flushed, iclass 32, count 0 2006.285.15:02:01.61#ibcon#about to write, iclass 32, count 0 2006.285.15:02:01.61#ibcon#wrote, iclass 32, count 0 2006.285.15:02:01.61#ibcon#about to read 3, iclass 32, count 0 2006.285.15:02:01.63#ibcon#read 3, iclass 32, count 0 2006.285.15:02:01.63#ibcon#about to read 4, iclass 32, count 0 2006.285.15:02:01.63#ibcon#read 4, iclass 32, count 0 2006.285.15:02:01.63#ibcon#about to read 5, iclass 32, count 0 2006.285.15:02:01.63#ibcon#read 5, iclass 32, count 0 2006.285.15:02:01.63#ibcon#about to read 6, iclass 32, count 0 2006.285.15:02:01.63#ibcon#read 6, iclass 32, count 0 2006.285.15:02:01.63#ibcon#end of sib2, iclass 32, count 0 2006.285.15:02:01.63#ibcon#*mode == 0, iclass 32, count 0 2006.285.15:02:01.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.15:02:01.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.15:02:01.63#ibcon#*before write, iclass 32, count 0 2006.285.15:02:01.63#ibcon#enter sib2, iclass 32, count 0 2006.285.15:02:01.63#ibcon#flushed, iclass 32, count 0 2006.285.15:02:01.63#ibcon#about to write, iclass 32, count 0 2006.285.15:02:01.63#ibcon#wrote, iclass 32, count 0 2006.285.15:02:01.63#ibcon#about to read 3, iclass 32, count 0 2006.285.15:02:01.67#ibcon#read 3, iclass 32, count 0 2006.285.15:02:01.67#ibcon#about to read 4, iclass 32, count 0 2006.285.15:02:01.67#ibcon#read 4, iclass 32, count 0 2006.285.15:02:01.67#ibcon#about to read 5, iclass 32, count 0 2006.285.15:02:01.67#ibcon#read 5, iclass 32, count 0 2006.285.15:02:01.67#ibcon#about to read 6, iclass 32, count 0 2006.285.15:02:01.67#ibcon#read 6, iclass 32, count 0 2006.285.15:02:01.67#ibcon#end of sib2, iclass 32, count 0 2006.285.15:02:01.67#ibcon#*after write, iclass 32, count 0 2006.285.15:02:01.67#ibcon#*before return 0, iclass 32, count 0 2006.285.15:02:01.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:02:01.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:02:01.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.15:02:01.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.15:02:01.67$vck44/vb=1,4 2006.285.15:02:01.67#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.15:02:01.67#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.15:02:01.67#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:01.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:02:01.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:02:01.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:02:01.67#ibcon#enter wrdev, iclass 34, count 2 2006.285.15:02:01.67#ibcon#first serial, iclass 34, count 2 2006.285.15:02:01.67#ibcon#enter sib2, iclass 34, count 2 2006.285.15:02:01.67#ibcon#flushed, iclass 34, count 2 2006.285.15:02:01.67#ibcon#about to write, iclass 34, count 2 2006.285.15:02:01.67#ibcon#wrote, iclass 34, count 2 2006.285.15:02:01.67#ibcon#about to read 3, iclass 34, count 2 2006.285.15:02:01.69#ibcon#read 3, iclass 34, count 2 2006.285.15:02:01.69#ibcon#about to read 4, iclass 34, count 2 2006.285.15:02:01.69#ibcon#read 4, iclass 34, count 2 2006.285.15:02:01.69#ibcon#about to read 5, iclass 34, count 2 2006.285.15:02:01.69#ibcon#read 5, iclass 34, count 2 2006.285.15:02:01.69#ibcon#about to read 6, iclass 34, count 2 2006.285.15:02:01.69#ibcon#read 6, iclass 34, count 2 2006.285.15:02:01.69#ibcon#end of sib2, iclass 34, count 2 2006.285.15:02:01.69#ibcon#*mode == 0, iclass 34, count 2 2006.285.15:02:01.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.15:02:01.69#ibcon#[27=AT01-04\r\n] 2006.285.15:02:01.69#ibcon#*before write, iclass 34, count 2 2006.285.15:02:01.69#ibcon#enter sib2, iclass 34, count 2 2006.285.15:02:01.69#ibcon#flushed, iclass 34, count 2 2006.285.15:02:01.69#ibcon#about to write, iclass 34, count 2 2006.285.15:02:01.69#ibcon#wrote, iclass 34, count 2 2006.285.15:02:01.69#ibcon#about to read 3, iclass 34, count 2 2006.285.15:02:01.72#ibcon#read 3, iclass 34, count 2 2006.285.15:02:01.72#ibcon#about to read 4, iclass 34, count 2 2006.285.15:02:01.72#ibcon#read 4, iclass 34, count 2 2006.285.15:02:01.72#ibcon#about to read 5, iclass 34, count 2 2006.285.15:02:01.72#ibcon#read 5, iclass 34, count 2 2006.285.15:02:01.72#ibcon#about to read 6, iclass 34, count 2 2006.285.15:02:01.72#ibcon#read 6, iclass 34, count 2 2006.285.15:02:01.72#ibcon#end of sib2, iclass 34, count 2 2006.285.15:02:01.72#ibcon#*after write, iclass 34, count 2 2006.285.15:02:01.72#ibcon#*before return 0, iclass 34, count 2 2006.285.15:02:01.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:02:01.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:02:01.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.15:02:01.72#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:01.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:02:01.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:02:01.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:02:01.84#ibcon#enter wrdev, iclass 34, count 0 2006.285.15:02:01.84#ibcon#first serial, iclass 34, count 0 2006.285.15:02:01.84#ibcon#enter sib2, iclass 34, count 0 2006.285.15:02:01.84#ibcon#flushed, iclass 34, count 0 2006.285.15:02:01.84#ibcon#about to write, iclass 34, count 0 2006.285.15:02:01.84#ibcon#wrote, iclass 34, count 0 2006.285.15:02:01.84#ibcon#about to read 3, iclass 34, count 0 2006.285.15:02:01.86#ibcon#read 3, iclass 34, count 0 2006.285.15:02:01.86#ibcon#about to read 4, iclass 34, count 0 2006.285.15:02:01.86#ibcon#read 4, iclass 34, count 0 2006.285.15:02:01.86#ibcon#about to read 5, iclass 34, count 0 2006.285.15:02:01.86#ibcon#read 5, iclass 34, count 0 2006.285.15:02:01.86#ibcon#about to read 6, iclass 34, count 0 2006.285.15:02:01.86#ibcon#read 6, iclass 34, count 0 2006.285.15:02:01.86#ibcon#end of sib2, iclass 34, count 0 2006.285.15:02:01.86#ibcon#*mode == 0, iclass 34, count 0 2006.285.15:02:01.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.15:02:01.86#ibcon#[27=USB\r\n] 2006.285.15:02:01.86#ibcon#*before write, iclass 34, count 0 2006.285.15:02:01.86#ibcon#enter sib2, iclass 34, count 0 2006.285.15:02:01.86#ibcon#flushed, iclass 34, count 0 2006.285.15:02:01.86#ibcon#about to write, iclass 34, count 0 2006.285.15:02:01.86#ibcon#wrote, iclass 34, count 0 2006.285.15:02:01.86#ibcon#about to read 3, iclass 34, count 0 2006.285.15:02:01.89#ibcon#read 3, iclass 34, count 0 2006.285.15:02:01.89#ibcon#about to read 4, iclass 34, count 0 2006.285.15:02:01.89#ibcon#read 4, iclass 34, count 0 2006.285.15:02:01.89#ibcon#about to read 5, iclass 34, count 0 2006.285.15:02:01.89#ibcon#read 5, iclass 34, count 0 2006.285.15:02:01.89#ibcon#about to read 6, iclass 34, count 0 2006.285.15:02:01.89#ibcon#read 6, iclass 34, count 0 2006.285.15:02:01.89#ibcon#end of sib2, iclass 34, count 0 2006.285.15:02:01.89#ibcon#*after write, iclass 34, count 0 2006.285.15:02:01.89#ibcon#*before return 0, iclass 34, count 0 2006.285.15:02:01.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:02:01.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:02:01.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.15:02:01.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.15:02:01.89$vck44/vblo=2,634.99 2006.285.15:02:01.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.15:02:01.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.15:02:01.89#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:01.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:02:01.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:02:01.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:02:01.89#ibcon#enter wrdev, iclass 36, count 0 2006.285.15:02:01.89#ibcon#first serial, iclass 36, count 0 2006.285.15:02:01.89#ibcon#enter sib2, iclass 36, count 0 2006.285.15:02:01.89#ibcon#flushed, iclass 36, count 0 2006.285.15:02:01.89#ibcon#about to write, iclass 36, count 0 2006.285.15:02:01.89#ibcon#wrote, iclass 36, count 0 2006.285.15:02:01.89#ibcon#about to read 3, iclass 36, count 0 2006.285.15:02:01.91#ibcon#read 3, iclass 36, count 0 2006.285.15:02:01.91#ibcon#about to read 4, iclass 36, count 0 2006.285.15:02:01.91#ibcon#read 4, iclass 36, count 0 2006.285.15:02:01.91#ibcon#about to read 5, iclass 36, count 0 2006.285.15:02:01.91#ibcon#read 5, iclass 36, count 0 2006.285.15:02:01.91#ibcon#about to read 6, iclass 36, count 0 2006.285.15:02:01.91#ibcon#read 6, iclass 36, count 0 2006.285.15:02:01.91#ibcon#end of sib2, iclass 36, count 0 2006.285.15:02:01.91#ibcon#*mode == 0, iclass 36, count 0 2006.285.15:02:01.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.15:02:01.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.15:02:01.91#ibcon#*before write, iclass 36, count 0 2006.285.15:02:01.91#ibcon#enter sib2, iclass 36, count 0 2006.285.15:02:01.91#ibcon#flushed, iclass 36, count 0 2006.285.15:02:01.91#ibcon#about to write, iclass 36, count 0 2006.285.15:02:01.91#ibcon#wrote, iclass 36, count 0 2006.285.15:02:01.91#ibcon#about to read 3, iclass 36, count 0 2006.285.15:02:01.95#ibcon#read 3, iclass 36, count 0 2006.285.15:02:01.95#ibcon#about to read 4, iclass 36, count 0 2006.285.15:02:01.95#ibcon#read 4, iclass 36, count 0 2006.285.15:02:01.95#ibcon#about to read 5, iclass 36, count 0 2006.285.15:02:01.95#ibcon#read 5, iclass 36, count 0 2006.285.15:02:01.95#ibcon#about to read 6, iclass 36, count 0 2006.285.15:02:01.95#ibcon#read 6, iclass 36, count 0 2006.285.15:02:01.95#ibcon#end of sib2, iclass 36, count 0 2006.285.15:02:01.95#ibcon#*after write, iclass 36, count 0 2006.285.15:02:01.95#ibcon#*before return 0, iclass 36, count 0 2006.285.15:02:01.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:02:01.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:02:01.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.15:02:01.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.15:02:01.95$vck44/vb=2,5 2006.285.15:02:01.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.15:02:01.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.15:02:01.95#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:01.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:02:02.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:02:02.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:02:02.01#ibcon#enter wrdev, iclass 38, count 2 2006.285.15:02:02.01#ibcon#first serial, iclass 38, count 2 2006.285.15:02:02.01#ibcon#enter sib2, iclass 38, count 2 2006.285.15:02:02.01#ibcon#flushed, iclass 38, count 2 2006.285.15:02:02.01#ibcon#about to write, iclass 38, count 2 2006.285.15:02:02.01#ibcon#wrote, iclass 38, count 2 2006.285.15:02:02.01#ibcon#about to read 3, iclass 38, count 2 2006.285.15:02:02.03#ibcon#read 3, iclass 38, count 2 2006.285.15:02:02.03#ibcon#about to read 4, iclass 38, count 2 2006.285.15:02:02.03#ibcon#read 4, iclass 38, count 2 2006.285.15:02:02.03#ibcon#about to read 5, iclass 38, count 2 2006.285.15:02:02.03#ibcon#read 5, iclass 38, count 2 2006.285.15:02:02.03#ibcon#about to read 6, iclass 38, count 2 2006.285.15:02:02.03#ibcon#read 6, iclass 38, count 2 2006.285.15:02:02.03#ibcon#end of sib2, iclass 38, count 2 2006.285.15:02:02.03#ibcon#*mode == 0, iclass 38, count 2 2006.285.15:02:02.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.15:02:02.03#ibcon#[27=AT02-05\r\n] 2006.285.15:02:02.03#ibcon#*before write, iclass 38, count 2 2006.285.15:02:02.03#ibcon#enter sib2, iclass 38, count 2 2006.285.15:02:02.03#ibcon#flushed, iclass 38, count 2 2006.285.15:02:02.03#ibcon#about to write, iclass 38, count 2 2006.285.15:02:02.03#ibcon#wrote, iclass 38, count 2 2006.285.15:02:02.03#ibcon#about to read 3, iclass 38, count 2 2006.285.15:02:02.06#ibcon#read 3, iclass 38, count 2 2006.285.15:02:02.06#ibcon#about to read 4, iclass 38, count 2 2006.285.15:02:02.06#ibcon#read 4, iclass 38, count 2 2006.285.15:02:02.06#ibcon#about to read 5, iclass 38, count 2 2006.285.15:02:02.06#ibcon#read 5, iclass 38, count 2 2006.285.15:02:02.06#ibcon#about to read 6, iclass 38, count 2 2006.285.15:02:02.06#ibcon#read 6, iclass 38, count 2 2006.285.15:02:02.06#ibcon#end of sib2, iclass 38, count 2 2006.285.15:02:02.06#ibcon#*after write, iclass 38, count 2 2006.285.15:02:02.06#ibcon#*before return 0, iclass 38, count 2 2006.285.15:02:02.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:02:02.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:02:02.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.15:02:02.06#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:02.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:02:02.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:02:02.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:02:02.18#ibcon#enter wrdev, iclass 38, count 0 2006.285.15:02:02.18#ibcon#first serial, iclass 38, count 0 2006.285.15:02:02.18#ibcon#enter sib2, iclass 38, count 0 2006.285.15:02:02.18#ibcon#flushed, iclass 38, count 0 2006.285.15:02:02.18#ibcon#about to write, iclass 38, count 0 2006.285.15:02:02.18#ibcon#wrote, iclass 38, count 0 2006.285.15:02:02.18#ibcon#about to read 3, iclass 38, count 0 2006.285.15:02:02.20#ibcon#read 3, iclass 38, count 0 2006.285.15:02:02.20#ibcon#about to read 4, iclass 38, count 0 2006.285.15:02:02.20#ibcon#read 4, iclass 38, count 0 2006.285.15:02:02.20#ibcon#about to read 5, iclass 38, count 0 2006.285.15:02:02.20#ibcon#read 5, iclass 38, count 0 2006.285.15:02:02.20#ibcon#about to read 6, iclass 38, count 0 2006.285.15:02:02.20#ibcon#read 6, iclass 38, count 0 2006.285.15:02:02.20#ibcon#end of sib2, iclass 38, count 0 2006.285.15:02:02.20#ibcon#*mode == 0, iclass 38, count 0 2006.285.15:02:02.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.15:02:02.20#ibcon#[27=USB\r\n] 2006.285.15:02:02.20#ibcon#*before write, iclass 38, count 0 2006.285.15:02:02.20#ibcon#enter sib2, iclass 38, count 0 2006.285.15:02:02.20#ibcon#flushed, iclass 38, count 0 2006.285.15:02:02.20#ibcon#about to write, iclass 38, count 0 2006.285.15:02:02.20#ibcon#wrote, iclass 38, count 0 2006.285.15:02:02.20#ibcon#about to read 3, iclass 38, count 0 2006.285.15:02:02.23#ibcon#read 3, iclass 38, count 0 2006.285.15:02:02.23#ibcon#about to read 4, iclass 38, count 0 2006.285.15:02:02.23#ibcon#read 4, iclass 38, count 0 2006.285.15:02:02.23#ibcon#about to read 5, iclass 38, count 0 2006.285.15:02:02.23#ibcon#read 5, iclass 38, count 0 2006.285.15:02:02.23#ibcon#about to read 6, iclass 38, count 0 2006.285.15:02:02.23#ibcon#read 6, iclass 38, count 0 2006.285.15:02:02.23#ibcon#end of sib2, iclass 38, count 0 2006.285.15:02:02.23#ibcon#*after write, iclass 38, count 0 2006.285.15:02:02.23#ibcon#*before return 0, iclass 38, count 0 2006.285.15:02:02.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:02:02.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:02:02.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.15:02:02.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.15:02:02.23$vck44/vblo=3,649.99 2006.285.15:02:02.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.15:02:02.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.15:02:02.23#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:02.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:02:02.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:02:02.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:02:02.23#ibcon#enter wrdev, iclass 40, count 0 2006.285.15:02:02.23#ibcon#first serial, iclass 40, count 0 2006.285.15:02:02.23#ibcon#enter sib2, iclass 40, count 0 2006.285.15:02:02.23#ibcon#flushed, iclass 40, count 0 2006.285.15:02:02.23#ibcon#about to write, iclass 40, count 0 2006.285.15:02:02.23#ibcon#wrote, iclass 40, count 0 2006.285.15:02:02.23#ibcon#about to read 3, iclass 40, count 0 2006.285.15:02:02.25#ibcon#read 3, iclass 40, count 0 2006.285.15:02:02.25#ibcon#about to read 4, iclass 40, count 0 2006.285.15:02:02.25#ibcon#read 4, iclass 40, count 0 2006.285.15:02:02.25#ibcon#about to read 5, iclass 40, count 0 2006.285.15:02:02.25#ibcon#read 5, iclass 40, count 0 2006.285.15:02:02.25#ibcon#about to read 6, iclass 40, count 0 2006.285.15:02:02.25#ibcon#read 6, iclass 40, count 0 2006.285.15:02:02.25#ibcon#end of sib2, iclass 40, count 0 2006.285.15:02:02.25#ibcon#*mode == 0, iclass 40, count 0 2006.285.15:02:02.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.15:02:02.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.15:02:02.25#ibcon#*before write, iclass 40, count 0 2006.285.15:02:02.25#ibcon#enter sib2, iclass 40, count 0 2006.285.15:02:02.25#ibcon#flushed, iclass 40, count 0 2006.285.15:02:02.25#ibcon#about to write, iclass 40, count 0 2006.285.15:02:02.25#ibcon#wrote, iclass 40, count 0 2006.285.15:02:02.25#ibcon#about to read 3, iclass 40, count 0 2006.285.15:02:02.29#ibcon#read 3, iclass 40, count 0 2006.285.15:02:02.29#ibcon#about to read 4, iclass 40, count 0 2006.285.15:02:02.29#ibcon#read 4, iclass 40, count 0 2006.285.15:02:02.29#ibcon#about to read 5, iclass 40, count 0 2006.285.15:02:02.29#ibcon#read 5, iclass 40, count 0 2006.285.15:02:02.29#ibcon#about to read 6, iclass 40, count 0 2006.285.15:02:02.29#ibcon#read 6, iclass 40, count 0 2006.285.15:02:02.29#ibcon#end of sib2, iclass 40, count 0 2006.285.15:02:02.29#ibcon#*after write, iclass 40, count 0 2006.285.15:02:02.29#ibcon#*before return 0, iclass 40, count 0 2006.285.15:02:02.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:02:02.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:02:02.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.15:02:02.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.15:02:02.29$vck44/vb=3,4 2006.285.15:02:02.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.15:02:02.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.15:02:02.29#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:02.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:02:02.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:02:02.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:02:02.35#ibcon#enter wrdev, iclass 4, count 2 2006.285.15:02:02.35#ibcon#first serial, iclass 4, count 2 2006.285.15:02:02.35#ibcon#enter sib2, iclass 4, count 2 2006.285.15:02:02.35#ibcon#flushed, iclass 4, count 2 2006.285.15:02:02.35#ibcon#about to write, iclass 4, count 2 2006.285.15:02:02.35#ibcon#wrote, iclass 4, count 2 2006.285.15:02:02.35#ibcon#about to read 3, iclass 4, count 2 2006.285.15:02:02.37#ibcon#read 3, iclass 4, count 2 2006.285.15:02:02.37#ibcon#about to read 4, iclass 4, count 2 2006.285.15:02:02.37#ibcon#read 4, iclass 4, count 2 2006.285.15:02:02.37#ibcon#about to read 5, iclass 4, count 2 2006.285.15:02:02.37#ibcon#read 5, iclass 4, count 2 2006.285.15:02:02.37#ibcon#about to read 6, iclass 4, count 2 2006.285.15:02:02.37#ibcon#read 6, iclass 4, count 2 2006.285.15:02:02.37#ibcon#end of sib2, iclass 4, count 2 2006.285.15:02:02.37#ibcon#*mode == 0, iclass 4, count 2 2006.285.15:02:02.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.15:02:02.37#ibcon#[27=AT03-04\r\n] 2006.285.15:02:02.37#ibcon#*before write, iclass 4, count 2 2006.285.15:02:02.37#ibcon#enter sib2, iclass 4, count 2 2006.285.15:02:02.37#ibcon#flushed, iclass 4, count 2 2006.285.15:02:02.37#ibcon#about to write, iclass 4, count 2 2006.285.15:02:02.37#ibcon#wrote, iclass 4, count 2 2006.285.15:02:02.37#ibcon#about to read 3, iclass 4, count 2 2006.285.15:02:02.40#ibcon#read 3, iclass 4, count 2 2006.285.15:02:02.40#ibcon#about to read 4, iclass 4, count 2 2006.285.15:02:02.40#ibcon#read 4, iclass 4, count 2 2006.285.15:02:02.40#ibcon#about to read 5, iclass 4, count 2 2006.285.15:02:02.40#ibcon#read 5, iclass 4, count 2 2006.285.15:02:02.40#ibcon#about to read 6, iclass 4, count 2 2006.285.15:02:02.40#ibcon#read 6, iclass 4, count 2 2006.285.15:02:02.40#ibcon#end of sib2, iclass 4, count 2 2006.285.15:02:02.40#ibcon#*after write, iclass 4, count 2 2006.285.15:02:02.40#ibcon#*before return 0, iclass 4, count 2 2006.285.15:02:02.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:02:02.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:02:02.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.15:02:02.40#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:02.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:02:02.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:02:02.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:02:02.52#ibcon#enter wrdev, iclass 4, count 0 2006.285.15:02:02.52#ibcon#first serial, iclass 4, count 0 2006.285.15:02:02.52#ibcon#enter sib2, iclass 4, count 0 2006.285.15:02:02.52#ibcon#flushed, iclass 4, count 0 2006.285.15:02:02.52#ibcon#about to write, iclass 4, count 0 2006.285.15:02:02.52#ibcon#wrote, iclass 4, count 0 2006.285.15:02:02.52#ibcon#about to read 3, iclass 4, count 0 2006.285.15:02:02.54#ibcon#read 3, iclass 4, count 0 2006.285.15:02:02.54#ibcon#about to read 4, iclass 4, count 0 2006.285.15:02:02.54#ibcon#read 4, iclass 4, count 0 2006.285.15:02:02.54#ibcon#about to read 5, iclass 4, count 0 2006.285.15:02:02.54#ibcon#read 5, iclass 4, count 0 2006.285.15:02:02.54#ibcon#about to read 6, iclass 4, count 0 2006.285.15:02:02.54#ibcon#read 6, iclass 4, count 0 2006.285.15:02:02.54#ibcon#end of sib2, iclass 4, count 0 2006.285.15:02:02.54#ibcon#*mode == 0, iclass 4, count 0 2006.285.15:02:02.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.15:02:02.54#ibcon#[27=USB\r\n] 2006.285.15:02:02.54#ibcon#*before write, iclass 4, count 0 2006.285.15:02:02.54#ibcon#enter sib2, iclass 4, count 0 2006.285.15:02:02.54#ibcon#flushed, iclass 4, count 0 2006.285.15:02:02.54#ibcon#about to write, iclass 4, count 0 2006.285.15:02:02.54#ibcon#wrote, iclass 4, count 0 2006.285.15:02:02.54#ibcon#about to read 3, iclass 4, count 0 2006.285.15:02:02.57#ibcon#read 3, iclass 4, count 0 2006.285.15:02:02.57#ibcon#about to read 4, iclass 4, count 0 2006.285.15:02:02.57#ibcon#read 4, iclass 4, count 0 2006.285.15:02:02.57#ibcon#about to read 5, iclass 4, count 0 2006.285.15:02:02.57#ibcon#read 5, iclass 4, count 0 2006.285.15:02:02.57#ibcon#about to read 6, iclass 4, count 0 2006.285.15:02:02.57#ibcon#read 6, iclass 4, count 0 2006.285.15:02:02.57#ibcon#end of sib2, iclass 4, count 0 2006.285.15:02:02.57#ibcon#*after write, iclass 4, count 0 2006.285.15:02:02.57#ibcon#*before return 0, iclass 4, count 0 2006.285.15:02:02.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:02:02.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:02:02.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.15:02:02.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.15:02:02.57$vck44/vblo=4,679.99 2006.285.15:02:02.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.15:02:02.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.15:02:02.57#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:02.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:02:02.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:02:02.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:02:02.57#ibcon#enter wrdev, iclass 6, count 0 2006.285.15:02:02.57#ibcon#first serial, iclass 6, count 0 2006.285.15:02:02.57#ibcon#enter sib2, iclass 6, count 0 2006.285.15:02:02.57#ibcon#flushed, iclass 6, count 0 2006.285.15:02:02.57#ibcon#about to write, iclass 6, count 0 2006.285.15:02:02.57#ibcon#wrote, iclass 6, count 0 2006.285.15:02:02.57#ibcon#about to read 3, iclass 6, count 0 2006.285.15:02:02.59#ibcon#read 3, iclass 6, count 0 2006.285.15:02:02.59#ibcon#about to read 4, iclass 6, count 0 2006.285.15:02:02.59#ibcon#read 4, iclass 6, count 0 2006.285.15:02:02.59#ibcon#about to read 5, iclass 6, count 0 2006.285.15:02:02.59#ibcon#read 5, iclass 6, count 0 2006.285.15:02:02.59#ibcon#about to read 6, iclass 6, count 0 2006.285.15:02:02.59#ibcon#read 6, iclass 6, count 0 2006.285.15:02:02.59#ibcon#end of sib2, iclass 6, count 0 2006.285.15:02:02.59#ibcon#*mode == 0, iclass 6, count 0 2006.285.15:02:02.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.15:02:02.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.15:02:02.59#ibcon#*before write, iclass 6, count 0 2006.285.15:02:02.59#ibcon#enter sib2, iclass 6, count 0 2006.285.15:02:02.59#ibcon#flushed, iclass 6, count 0 2006.285.15:02:02.59#ibcon#about to write, iclass 6, count 0 2006.285.15:02:02.59#ibcon#wrote, iclass 6, count 0 2006.285.15:02:02.59#ibcon#about to read 3, iclass 6, count 0 2006.285.15:02:02.63#ibcon#read 3, iclass 6, count 0 2006.285.15:02:02.63#ibcon#about to read 4, iclass 6, count 0 2006.285.15:02:02.63#ibcon#read 4, iclass 6, count 0 2006.285.15:02:02.63#ibcon#about to read 5, iclass 6, count 0 2006.285.15:02:02.63#ibcon#read 5, iclass 6, count 0 2006.285.15:02:02.63#ibcon#about to read 6, iclass 6, count 0 2006.285.15:02:02.63#ibcon#read 6, iclass 6, count 0 2006.285.15:02:02.63#ibcon#end of sib2, iclass 6, count 0 2006.285.15:02:02.63#ibcon#*after write, iclass 6, count 0 2006.285.15:02:02.63#ibcon#*before return 0, iclass 6, count 0 2006.285.15:02:02.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:02:02.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:02:02.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.15:02:02.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.15:02:02.63$vck44/vb=4,5 2006.285.15:02:02.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.15:02:02.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.15:02:02.63#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:02.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:02:02.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:02:02.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:02:02.69#ibcon#enter wrdev, iclass 10, count 2 2006.285.15:02:02.69#ibcon#first serial, iclass 10, count 2 2006.285.15:02:02.69#ibcon#enter sib2, iclass 10, count 2 2006.285.15:02:02.69#ibcon#flushed, iclass 10, count 2 2006.285.15:02:02.69#ibcon#about to write, iclass 10, count 2 2006.285.15:02:02.69#ibcon#wrote, iclass 10, count 2 2006.285.15:02:02.69#ibcon#about to read 3, iclass 10, count 2 2006.285.15:02:02.71#ibcon#read 3, iclass 10, count 2 2006.285.15:02:02.71#ibcon#about to read 4, iclass 10, count 2 2006.285.15:02:02.71#ibcon#read 4, iclass 10, count 2 2006.285.15:02:02.71#ibcon#about to read 5, iclass 10, count 2 2006.285.15:02:02.71#ibcon#read 5, iclass 10, count 2 2006.285.15:02:02.71#ibcon#about to read 6, iclass 10, count 2 2006.285.15:02:02.71#ibcon#read 6, iclass 10, count 2 2006.285.15:02:02.71#ibcon#end of sib2, iclass 10, count 2 2006.285.15:02:02.71#ibcon#*mode == 0, iclass 10, count 2 2006.285.15:02:02.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.15:02:02.71#ibcon#[27=AT04-05\r\n] 2006.285.15:02:02.71#ibcon#*before write, iclass 10, count 2 2006.285.15:02:02.71#ibcon#enter sib2, iclass 10, count 2 2006.285.15:02:02.71#ibcon#flushed, iclass 10, count 2 2006.285.15:02:02.71#ibcon#about to write, iclass 10, count 2 2006.285.15:02:02.71#ibcon#wrote, iclass 10, count 2 2006.285.15:02:02.71#ibcon#about to read 3, iclass 10, count 2 2006.285.15:02:02.74#ibcon#read 3, iclass 10, count 2 2006.285.15:02:02.74#ibcon#about to read 4, iclass 10, count 2 2006.285.15:02:02.74#ibcon#read 4, iclass 10, count 2 2006.285.15:02:02.74#ibcon#about to read 5, iclass 10, count 2 2006.285.15:02:02.74#ibcon#read 5, iclass 10, count 2 2006.285.15:02:02.74#ibcon#about to read 6, iclass 10, count 2 2006.285.15:02:02.74#ibcon#read 6, iclass 10, count 2 2006.285.15:02:02.74#ibcon#end of sib2, iclass 10, count 2 2006.285.15:02:02.74#ibcon#*after write, iclass 10, count 2 2006.285.15:02:02.74#ibcon#*before return 0, iclass 10, count 2 2006.285.15:02:02.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:02:02.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:02:02.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.15:02:02.74#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:02.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:02:02.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:02:02.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:02:02.86#ibcon#enter wrdev, iclass 10, count 0 2006.285.15:02:02.86#ibcon#first serial, iclass 10, count 0 2006.285.15:02:02.86#ibcon#enter sib2, iclass 10, count 0 2006.285.15:02:02.86#ibcon#flushed, iclass 10, count 0 2006.285.15:02:02.86#ibcon#about to write, iclass 10, count 0 2006.285.15:02:02.86#ibcon#wrote, iclass 10, count 0 2006.285.15:02:02.86#ibcon#about to read 3, iclass 10, count 0 2006.285.15:02:02.88#ibcon#read 3, iclass 10, count 0 2006.285.15:02:02.88#ibcon#about to read 4, iclass 10, count 0 2006.285.15:02:02.88#ibcon#read 4, iclass 10, count 0 2006.285.15:02:02.88#ibcon#about to read 5, iclass 10, count 0 2006.285.15:02:02.88#ibcon#read 5, iclass 10, count 0 2006.285.15:02:02.88#ibcon#about to read 6, iclass 10, count 0 2006.285.15:02:02.88#ibcon#read 6, iclass 10, count 0 2006.285.15:02:02.88#ibcon#end of sib2, iclass 10, count 0 2006.285.15:02:02.88#ibcon#*mode == 0, iclass 10, count 0 2006.285.15:02:02.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.15:02:02.97#ibcon#[27=USB\r\n] 2006.285.15:02:02.97#ibcon#*before write, iclass 10, count 0 2006.285.15:02:02.97#ibcon#enter sib2, iclass 10, count 0 2006.285.15:02:02.97#ibcon#flushed, iclass 10, count 0 2006.285.15:02:02.97#ibcon#about to write, iclass 10, count 0 2006.285.15:02:02.97#ibcon#wrote, iclass 10, count 0 2006.285.15:02:02.97#ibcon#about to read 3, iclass 10, count 0 2006.285.15:02:03.00#ibcon#read 3, iclass 10, count 0 2006.285.15:02:03.00#ibcon#about to read 4, iclass 10, count 0 2006.285.15:02:03.00#ibcon#read 4, iclass 10, count 0 2006.285.15:02:03.00#ibcon#about to read 5, iclass 10, count 0 2006.285.15:02:03.00#ibcon#read 5, iclass 10, count 0 2006.285.15:02:03.00#ibcon#about to read 6, iclass 10, count 0 2006.285.15:02:03.00#ibcon#read 6, iclass 10, count 0 2006.285.15:02:03.00#ibcon#end of sib2, iclass 10, count 0 2006.285.15:02:03.00#ibcon#*after write, iclass 10, count 0 2006.285.15:02:03.00#ibcon#*before return 0, iclass 10, count 0 2006.285.15:02:03.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:02:03.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:02:03.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.15:02:03.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.15:02:03.00$vck44/vblo=5,709.99 2006.285.15:02:03.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.15:02:03.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.15:02:03.00#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:03.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:02:03.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:02:03.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:02:03.00#ibcon#enter wrdev, iclass 12, count 0 2006.285.15:02:03.00#ibcon#first serial, iclass 12, count 0 2006.285.15:02:03.00#ibcon#enter sib2, iclass 12, count 0 2006.285.15:02:03.00#ibcon#flushed, iclass 12, count 0 2006.285.15:02:03.00#ibcon#about to write, iclass 12, count 0 2006.285.15:02:03.00#ibcon#wrote, iclass 12, count 0 2006.285.15:02:03.00#ibcon#about to read 3, iclass 12, count 0 2006.285.15:02:03.02#ibcon#read 3, iclass 12, count 0 2006.285.15:02:03.02#ibcon#about to read 4, iclass 12, count 0 2006.285.15:02:03.02#ibcon#read 4, iclass 12, count 0 2006.285.15:02:03.02#ibcon#about to read 5, iclass 12, count 0 2006.285.15:02:03.02#ibcon#read 5, iclass 12, count 0 2006.285.15:02:03.02#ibcon#about to read 6, iclass 12, count 0 2006.285.15:02:03.02#ibcon#read 6, iclass 12, count 0 2006.285.15:02:03.02#ibcon#end of sib2, iclass 12, count 0 2006.285.15:02:03.02#ibcon#*mode == 0, iclass 12, count 0 2006.285.15:02:03.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.15:02:03.02#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.15:02:03.02#ibcon#*before write, iclass 12, count 0 2006.285.15:02:03.02#ibcon#enter sib2, iclass 12, count 0 2006.285.15:02:03.02#ibcon#flushed, iclass 12, count 0 2006.285.15:02:03.02#ibcon#about to write, iclass 12, count 0 2006.285.15:02:03.02#ibcon#wrote, iclass 12, count 0 2006.285.15:02:03.02#ibcon#about to read 3, iclass 12, count 0 2006.285.15:02:03.06#ibcon#read 3, iclass 12, count 0 2006.285.15:02:03.06#ibcon#about to read 4, iclass 12, count 0 2006.285.15:02:03.06#ibcon#read 4, iclass 12, count 0 2006.285.15:02:03.06#ibcon#about to read 5, iclass 12, count 0 2006.285.15:02:03.06#ibcon#read 5, iclass 12, count 0 2006.285.15:02:03.06#ibcon#about to read 6, iclass 12, count 0 2006.285.15:02:03.06#ibcon#read 6, iclass 12, count 0 2006.285.15:02:03.06#ibcon#end of sib2, iclass 12, count 0 2006.285.15:02:03.06#ibcon#*after write, iclass 12, count 0 2006.285.15:02:03.06#ibcon#*before return 0, iclass 12, count 0 2006.285.15:02:03.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:02:03.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:02:03.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.15:02:03.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.15:02:03.06$vck44/vb=5,4 2006.285.15:02:03.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.15:02:03.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.15:02:03.06#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:03.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:02:03.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:02:03.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:02:03.12#ibcon#enter wrdev, iclass 14, count 2 2006.285.15:02:03.12#ibcon#first serial, iclass 14, count 2 2006.285.15:02:03.12#ibcon#enter sib2, iclass 14, count 2 2006.285.15:02:03.12#ibcon#flushed, iclass 14, count 2 2006.285.15:02:03.12#ibcon#about to write, iclass 14, count 2 2006.285.15:02:03.12#ibcon#wrote, iclass 14, count 2 2006.285.15:02:03.12#ibcon#about to read 3, iclass 14, count 2 2006.285.15:02:03.14#ibcon#read 3, iclass 14, count 2 2006.285.15:02:03.14#ibcon#about to read 4, iclass 14, count 2 2006.285.15:02:03.14#ibcon#read 4, iclass 14, count 2 2006.285.15:02:03.14#ibcon#about to read 5, iclass 14, count 2 2006.285.15:02:03.14#ibcon#read 5, iclass 14, count 2 2006.285.15:02:03.14#ibcon#about to read 6, iclass 14, count 2 2006.285.15:02:03.14#ibcon#read 6, iclass 14, count 2 2006.285.15:02:03.14#ibcon#end of sib2, iclass 14, count 2 2006.285.15:02:03.14#ibcon#*mode == 0, iclass 14, count 2 2006.285.15:02:03.14#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.15:02:03.14#ibcon#[27=AT05-04\r\n] 2006.285.15:02:03.14#ibcon#*before write, iclass 14, count 2 2006.285.15:02:03.14#ibcon#enter sib2, iclass 14, count 2 2006.285.15:02:03.14#ibcon#flushed, iclass 14, count 2 2006.285.15:02:03.14#ibcon#about to write, iclass 14, count 2 2006.285.15:02:03.14#ibcon#wrote, iclass 14, count 2 2006.285.15:02:03.14#ibcon#about to read 3, iclass 14, count 2 2006.285.15:02:03.17#ibcon#read 3, iclass 14, count 2 2006.285.15:02:03.17#ibcon#about to read 4, iclass 14, count 2 2006.285.15:02:03.17#ibcon#read 4, iclass 14, count 2 2006.285.15:02:03.17#ibcon#about to read 5, iclass 14, count 2 2006.285.15:02:03.17#ibcon#read 5, iclass 14, count 2 2006.285.15:02:03.17#ibcon#about to read 6, iclass 14, count 2 2006.285.15:02:03.17#ibcon#read 6, iclass 14, count 2 2006.285.15:02:03.17#ibcon#end of sib2, iclass 14, count 2 2006.285.15:02:03.17#ibcon#*after write, iclass 14, count 2 2006.285.15:02:03.17#ibcon#*before return 0, iclass 14, count 2 2006.285.15:02:03.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:02:03.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:02:03.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.15:02:03.17#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:03.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:02:03.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:02:03.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:02:03.29#ibcon#enter wrdev, iclass 14, count 0 2006.285.15:02:03.29#ibcon#first serial, iclass 14, count 0 2006.285.15:02:03.29#ibcon#enter sib2, iclass 14, count 0 2006.285.15:02:03.29#ibcon#flushed, iclass 14, count 0 2006.285.15:02:03.29#ibcon#about to write, iclass 14, count 0 2006.285.15:02:03.29#ibcon#wrote, iclass 14, count 0 2006.285.15:02:03.29#ibcon#about to read 3, iclass 14, count 0 2006.285.15:02:03.31#ibcon#read 3, iclass 14, count 0 2006.285.15:02:03.31#ibcon#about to read 4, iclass 14, count 0 2006.285.15:02:03.31#ibcon#read 4, iclass 14, count 0 2006.285.15:02:03.31#ibcon#about to read 5, iclass 14, count 0 2006.285.15:02:03.31#ibcon#read 5, iclass 14, count 0 2006.285.15:02:03.31#ibcon#about to read 6, iclass 14, count 0 2006.285.15:02:03.31#ibcon#read 6, iclass 14, count 0 2006.285.15:02:03.31#ibcon#end of sib2, iclass 14, count 0 2006.285.15:02:03.31#ibcon#*mode == 0, iclass 14, count 0 2006.285.15:02:03.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.15:02:03.31#ibcon#[27=USB\r\n] 2006.285.15:02:03.31#ibcon#*before write, iclass 14, count 0 2006.285.15:02:03.31#ibcon#enter sib2, iclass 14, count 0 2006.285.15:02:03.31#ibcon#flushed, iclass 14, count 0 2006.285.15:02:03.31#ibcon#about to write, iclass 14, count 0 2006.285.15:02:03.31#ibcon#wrote, iclass 14, count 0 2006.285.15:02:03.31#ibcon#about to read 3, iclass 14, count 0 2006.285.15:02:03.34#ibcon#read 3, iclass 14, count 0 2006.285.15:02:03.34#ibcon#about to read 4, iclass 14, count 0 2006.285.15:02:03.34#ibcon#read 4, iclass 14, count 0 2006.285.15:02:03.34#ibcon#about to read 5, iclass 14, count 0 2006.285.15:02:03.34#ibcon#read 5, iclass 14, count 0 2006.285.15:02:03.34#ibcon#about to read 6, iclass 14, count 0 2006.285.15:02:03.34#ibcon#read 6, iclass 14, count 0 2006.285.15:02:03.34#ibcon#end of sib2, iclass 14, count 0 2006.285.15:02:03.34#ibcon#*after write, iclass 14, count 0 2006.285.15:02:03.34#ibcon#*before return 0, iclass 14, count 0 2006.285.15:02:03.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:02:03.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:02:03.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.15:02:03.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.15:02:03.34$vck44/vblo=6,719.99 2006.285.15:02:03.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.15:02:03.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.15:02:03.34#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:03.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:02:03.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:02:03.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:02:03.34#ibcon#enter wrdev, iclass 16, count 0 2006.285.15:02:03.34#ibcon#first serial, iclass 16, count 0 2006.285.15:02:03.34#ibcon#enter sib2, iclass 16, count 0 2006.285.15:02:03.34#ibcon#flushed, iclass 16, count 0 2006.285.15:02:03.34#ibcon#about to write, iclass 16, count 0 2006.285.15:02:03.34#ibcon#wrote, iclass 16, count 0 2006.285.15:02:03.34#ibcon#about to read 3, iclass 16, count 0 2006.285.15:02:03.36#ibcon#read 3, iclass 16, count 0 2006.285.15:02:03.36#ibcon#about to read 4, iclass 16, count 0 2006.285.15:02:03.36#ibcon#read 4, iclass 16, count 0 2006.285.15:02:03.36#ibcon#about to read 5, iclass 16, count 0 2006.285.15:02:03.36#ibcon#read 5, iclass 16, count 0 2006.285.15:02:03.36#ibcon#about to read 6, iclass 16, count 0 2006.285.15:02:03.36#ibcon#read 6, iclass 16, count 0 2006.285.15:02:03.36#ibcon#end of sib2, iclass 16, count 0 2006.285.15:02:03.36#ibcon#*mode == 0, iclass 16, count 0 2006.285.15:02:03.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.15:02:03.36#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.15:02:03.36#ibcon#*before write, iclass 16, count 0 2006.285.15:02:03.36#ibcon#enter sib2, iclass 16, count 0 2006.285.15:02:03.36#ibcon#flushed, iclass 16, count 0 2006.285.15:02:03.36#ibcon#about to write, iclass 16, count 0 2006.285.15:02:03.36#ibcon#wrote, iclass 16, count 0 2006.285.15:02:03.36#ibcon#about to read 3, iclass 16, count 0 2006.285.15:02:03.40#ibcon#read 3, iclass 16, count 0 2006.285.15:02:03.40#ibcon#about to read 4, iclass 16, count 0 2006.285.15:02:03.40#ibcon#read 4, iclass 16, count 0 2006.285.15:02:03.40#ibcon#about to read 5, iclass 16, count 0 2006.285.15:02:03.40#ibcon#read 5, iclass 16, count 0 2006.285.15:02:03.40#ibcon#about to read 6, iclass 16, count 0 2006.285.15:02:03.40#ibcon#read 6, iclass 16, count 0 2006.285.15:02:03.40#ibcon#end of sib2, iclass 16, count 0 2006.285.15:02:03.40#ibcon#*after write, iclass 16, count 0 2006.285.15:02:03.40#ibcon#*before return 0, iclass 16, count 0 2006.285.15:02:03.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:02:03.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:02:03.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.15:02:03.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.15:02:03.40$vck44/vb=6,3 2006.285.15:02:03.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.15:02:03.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.15:02:03.40#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:03.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:02:03.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:02:03.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:02:03.46#ibcon#enter wrdev, iclass 18, count 2 2006.285.15:02:03.46#ibcon#first serial, iclass 18, count 2 2006.285.15:02:03.46#ibcon#enter sib2, iclass 18, count 2 2006.285.15:02:03.46#ibcon#flushed, iclass 18, count 2 2006.285.15:02:03.46#ibcon#about to write, iclass 18, count 2 2006.285.15:02:03.46#ibcon#wrote, iclass 18, count 2 2006.285.15:02:03.46#ibcon#about to read 3, iclass 18, count 2 2006.285.15:02:03.48#ibcon#read 3, iclass 18, count 2 2006.285.15:02:03.48#ibcon#about to read 4, iclass 18, count 2 2006.285.15:02:03.48#ibcon#read 4, iclass 18, count 2 2006.285.15:02:03.48#ibcon#about to read 5, iclass 18, count 2 2006.285.15:02:03.48#ibcon#read 5, iclass 18, count 2 2006.285.15:02:03.48#ibcon#about to read 6, iclass 18, count 2 2006.285.15:02:03.48#ibcon#read 6, iclass 18, count 2 2006.285.15:02:03.48#ibcon#end of sib2, iclass 18, count 2 2006.285.15:02:03.48#ibcon#*mode == 0, iclass 18, count 2 2006.285.15:02:03.48#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.15:02:03.48#ibcon#[27=AT06-03\r\n] 2006.285.15:02:03.48#ibcon#*before write, iclass 18, count 2 2006.285.15:02:03.48#ibcon#enter sib2, iclass 18, count 2 2006.285.15:02:03.48#ibcon#flushed, iclass 18, count 2 2006.285.15:02:03.48#ibcon#about to write, iclass 18, count 2 2006.285.15:02:03.48#ibcon#wrote, iclass 18, count 2 2006.285.15:02:03.48#ibcon#about to read 3, iclass 18, count 2 2006.285.15:02:03.51#ibcon#read 3, iclass 18, count 2 2006.285.15:02:03.51#ibcon#about to read 4, iclass 18, count 2 2006.285.15:02:03.51#ibcon#read 4, iclass 18, count 2 2006.285.15:02:03.51#ibcon#about to read 5, iclass 18, count 2 2006.285.15:02:03.51#ibcon#read 5, iclass 18, count 2 2006.285.15:02:03.51#ibcon#about to read 6, iclass 18, count 2 2006.285.15:02:03.51#ibcon#read 6, iclass 18, count 2 2006.285.15:02:03.51#ibcon#end of sib2, iclass 18, count 2 2006.285.15:02:03.51#ibcon#*after write, iclass 18, count 2 2006.285.15:02:03.51#ibcon#*before return 0, iclass 18, count 2 2006.285.15:02:03.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:02:03.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:02:03.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.15:02:03.51#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:03.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:02:03.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:02:03.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:02:03.63#ibcon#enter wrdev, iclass 18, count 0 2006.285.15:02:03.63#ibcon#first serial, iclass 18, count 0 2006.285.15:02:03.63#ibcon#enter sib2, iclass 18, count 0 2006.285.15:02:03.63#ibcon#flushed, iclass 18, count 0 2006.285.15:02:03.63#ibcon#about to write, iclass 18, count 0 2006.285.15:02:03.63#ibcon#wrote, iclass 18, count 0 2006.285.15:02:03.63#ibcon#about to read 3, iclass 18, count 0 2006.285.15:02:03.65#ibcon#read 3, iclass 18, count 0 2006.285.15:02:03.65#ibcon#about to read 4, iclass 18, count 0 2006.285.15:02:03.65#ibcon#read 4, iclass 18, count 0 2006.285.15:02:03.65#ibcon#about to read 5, iclass 18, count 0 2006.285.15:02:03.65#ibcon#read 5, iclass 18, count 0 2006.285.15:02:03.65#ibcon#about to read 6, iclass 18, count 0 2006.285.15:02:03.65#ibcon#read 6, iclass 18, count 0 2006.285.15:02:03.65#ibcon#end of sib2, iclass 18, count 0 2006.285.15:02:03.65#ibcon#*mode == 0, iclass 18, count 0 2006.285.15:02:03.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.15:02:03.65#ibcon#[27=USB\r\n] 2006.285.15:02:03.65#ibcon#*before write, iclass 18, count 0 2006.285.15:02:03.65#ibcon#enter sib2, iclass 18, count 0 2006.285.15:02:03.65#ibcon#flushed, iclass 18, count 0 2006.285.15:02:03.65#ibcon#about to write, iclass 18, count 0 2006.285.15:02:03.65#ibcon#wrote, iclass 18, count 0 2006.285.15:02:03.65#ibcon#about to read 3, iclass 18, count 0 2006.285.15:02:03.68#ibcon#read 3, iclass 18, count 0 2006.285.15:02:03.68#ibcon#about to read 4, iclass 18, count 0 2006.285.15:02:03.68#ibcon#read 4, iclass 18, count 0 2006.285.15:02:03.68#ibcon#about to read 5, iclass 18, count 0 2006.285.15:02:03.68#ibcon#read 5, iclass 18, count 0 2006.285.15:02:03.68#ibcon#about to read 6, iclass 18, count 0 2006.285.15:02:03.68#ibcon#read 6, iclass 18, count 0 2006.285.15:02:03.68#ibcon#end of sib2, iclass 18, count 0 2006.285.15:02:03.68#ibcon#*after write, iclass 18, count 0 2006.285.15:02:03.68#ibcon#*before return 0, iclass 18, count 0 2006.285.15:02:03.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:02:03.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:02:03.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.15:02:03.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.15:02:03.68$vck44/vblo=7,734.99 2006.285.15:02:03.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.15:02:03.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.15:02:03.68#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:03.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.15:02:03.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.15:02:03.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.15:02:03.68#ibcon#enter wrdev, iclass 20, count 0 2006.285.15:02:03.68#ibcon#first serial, iclass 20, count 0 2006.285.15:02:03.68#ibcon#enter sib2, iclass 20, count 0 2006.285.15:02:03.68#ibcon#flushed, iclass 20, count 0 2006.285.15:02:03.68#ibcon#about to write, iclass 20, count 0 2006.285.15:02:03.68#ibcon#wrote, iclass 20, count 0 2006.285.15:02:03.68#ibcon#about to read 3, iclass 20, count 0 2006.285.15:02:03.70#ibcon#read 3, iclass 20, count 0 2006.285.15:02:03.70#ibcon#about to read 4, iclass 20, count 0 2006.285.15:02:03.70#ibcon#read 4, iclass 20, count 0 2006.285.15:02:03.70#ibcon#about to read 5, iclass 20, count 0 2006.285.15:02:03.70#ibcon#read 5, iclass 20, count 0 2006.285.15:02:03.70#ibcon#about to read 6, iclass 20, count 0 2006.285.15:02:03.70#ibcon#read 6, iclass 20, count 0 2006.285.15:02:03.70#ibcon#end of sib2, iclass 20, count 0 2006.285.15:02:03.70#ibcon#*mode == 0, iclass 20, count 0 2006.285.15:02:03.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.15:02:03.70#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.15:02:03.70#ibcon#*before write, iclass 20, count 0 2006.285.15:02:03.70#ibcon#enter sib2, iclass 20, count 0 2006.285.15:02:03.70#ibcon#flushed, iclass 20, count 0 2006.285.15:02:03.70#ibcon#about to write, iclass 20, count 0 2006.285.15:02:03.70#ibcon#wrote, iclass 20, count 0 2006.285.15:02:03.70#ibcon#about to read 3, iclass 20, count 0 2006.285.15:02:03.74#ibcon#read 3, iclass 20, count 0 2006.285.15:02:03.74#ibcon#about to read 4, iclass 20, count 0 2006.285.15:02:03.74#ibcon#read 4, iclass 20, count 0 2006.285.15:02:03.74#ibcon#about to read 5, iclass 20, count 0 2006.285.15:02:03.74#ibcon#read 5, iclass 20, count 0 2006.285.15:02:03.74#ibcon#about to read 6, iclass 20, count 0 2006.285.15:02:03.74#ibcon#read 6, iclass 20, count 0 2006.285.15:02:03.74#ibcon#end of sib2, iclass 20, count 0 2006.285.15:02:03.74#ibcon#*after write, iclass 20, count 0 2006.285.15:02:03.74#ibcon#*before return 0, iclass 20, count 0 2006.285.15:02:03.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.15:02:03.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.15:02:03.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.15:02:03.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.15:02:03.74$vck44/vb=7,4 2006.285.15:02:03.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.15:02:03.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.15:02:03.74#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:03.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.15:02:03.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.15:02:03.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.15:02:03.80#ibcon#enter wrdev, iclass 22, count 2 2006.285.15:02:03.80#ibcon#first serial, iclass 22, count 2 2006.285.15:02:03.80#ibcon#enter sib2, iclass 22, count 2 2006.285.15:02:03.80#ibcon#flushed, iclass 22, count 2 2006.285.15:02:03.80#ibcon#about to write, iclass 22, count 2 2006.285.15:02:03.80#ibcon#wrote, iclass 22, count 2 2006.285.15:02:03.80#ibcon#about to read 3, iclass 22, count 2 2006.285.15:02:03.82#ibcon#read 3, iclass 22, count 2 2006.285.15:02:03.82#ibcon#about to read 4, iclass 22, count 2 2006.285.15:02:03.82#ibcon#read 4, iclass 22, count 2 2006.285.15:02:03.82#ibcon#about to read 5, iclass 22, count 2 2006.285.15:02:03.82#ibcon#read 5, iclass 22, count 2 2006.285.15:02:03.82#ibcon#about to read 6, iclass 22, count 2 2006.285.15:02:03.82#ibcon#read 6, iclass 22, count 2 2006.285.15:02:03.82#ibcon#end of sib2, iclass 22, count 2 2006.285.15:02:03.82#ibcon#*mode == 0, iclass 22, count 2 2006.285.15:02:03.82#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.15:02:03.82#ibcon#[27=AT07-04\r\n] 2006.285.15:02:03.82#ibcon#*before write, iclass 22, count 2 2006.285.15:02:03.82#ibcon#enter sib2, iclass 22, count 2 2006.285.15:02:03.82#ibcon#flushed, iclass 22, count 2 2006.285.15:02:03.82#ibcon#about to write, iclass 22, count 2 2006.285.15:02:03.82#ibcon#wrote, iclass 22, count 2 2006.285.15:02:03.82#ibcon#about to read 3, iclass 22, count 2 2006.285.15:02:03.85#ibcon#read 3, iclass 22, count 2 2006.285.15:02:03.85#ibcon#about to read 4, iclass 22, count 2 2006.285.15:02:03.85#ibcon#read 4, iclass 22, count 2 2006.285.15:02:03.85#ibcon#about to read 5, iclass 22, count 2 2006.285.15:02:03.85#ibcon#read 5, iclass 22, count 2 2006.285.15:02:03.85#ibcon#about to read 6, iclass 22, count 2 2006.285.15:02:03.85#ibcon#read 6, iclass 22, count 2 2006.285.15:02:03.85#ibcon#end of sib2, iclass 22, count 2 2006.285.15:02:03.85#ibcon#*after write, iclass 22, count 2 2006.285.15:02:03.85#ibcon#*before return 0, iclass 22, count 2 2006.285.15:02:03.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.15:02:03.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.15:02:03.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.15:02:03.85#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:03.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.15:02:03.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.15:02:03.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.15:02:03.97#ibcon#enter wrdev, iclass 22, count 0 2006.285.15:02:03.97#ibcon#first serial, iclass 22, count 0 2006.285.15:02:03.97#ibcon#enter sib2, iclass 22, count 0 2006.285.15:02:03.97#ibcon#flushed, iclass 22, count 0 2006.285.15:02:03.97#ibcon#about to write, iclass 22, count 0 2006.285.15:02:03.97#ibcon#wrote, iclass 22, count 0 2006.285.15:02:03.97#ibcon#about to read 3, iclass 22, count 0 2006.285.15:02:03.99#ibcon#read 3, iclass 22, count 0 2006.285.15:02:03.99#ibcon#about to read 4, iclass 22, count 0 2006.285.15:02:03.99#ibcon#read 4, iclass 22, count 0 2006.285.15:02:03.99#ibcon#about to read 5, iclass 22, count 0 2006.285.15:02:03.99#ibcon#read 5, iclass 22, count 0 2006.285.15:02:03.99#ibcon#about to read 6, iclass 22, count 0 2006.285.15:02:03.99#ibcon#read 6, iclass 22, count 0 2006.285.15:02:03.99#ibcon#end of sib2, iclass 22, count 0 2006.285.15:02:03.99#ibcon#*mode == 0, iclass 22, count 0 2006.285.15:02:03.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.15:02:03.99#ibcon#[27=USB\r\n] 2006.285.15:02:03.99#ibcon#*before write, iclass 22, count 0 2006.285.15:02:03.99#ibcon#enter sib2, iclass 22, count 0 2006.285.15:02:03.99#ibcon#flushed, iclass 22, count 0 2006.285.15:02:03.99#ibcon#about to write, iclass 22, count 0 2006.285.15:02:03.99#ibcon#wrote, iclass 22, count 0 2006.285.15:02:03.99#ibcon#about to read 3, iclass 22, count 0 2006.285.15:02:04.02#ibcon#read 3, iclass 22, count 0 2006.285.15:02:04.02#ibcon#about to read 4, iclass 22, count 0 2006.285.15:02:04.02#ibcon#read 4, iclass 22, count 0 2006.285.15:02:04.02#ibcon#about to read 5, iclass 22, count 0 2006.285.15:02:04.02#ibcon#read 5, iclass 22, count 0 2006.285.15:02:04.02#ibcon#about to read 6, iclass 22, count 0 2006.285.15:02:04.02#ibcon#read 6, iclass 22, count 0 2006.285.15:02:04.02#ibcon#end of sib2, iclass 22, count 0 2006.285.15:02:04.02#ibcon#*after write, iclass 22, count 0 2006.285.15:02:04.02#ibcon#*before return 0, iclass 22, count 0 2006.285.15:02:04.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.15:02:04.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.15:02:04.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.15:02:04.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.15:02:04.02$vck44/vblo=8,744.99 2006.285.15:02:04.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.15:02:04.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.15:02:04.02#ibcon#ireg 17 cls_cnt 0 2006.285.15:02:04.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:02:04.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:02:04.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:02:04.02#ibcon#enter wrdev, iclass 24, count 0 2006.285.15:02:04.02#ibcon#first serial, iclass 24, count 0 2006.285.15:02:04.02#ibcon#enter sib2, iclass 24, count 0 2006.285.15:02:04.02#ibcon#flushed, iclass 24, count 0 2006.285.15:02:04.02#ibcon#about to write, iclass 24, count 0 2006.285.15:02:04.02#ibcon#wrote, iclass 24, count 0 2006.285.15:02:04.02#ibcon#about to read 3, iclass 24, count 0 2006.285.15:02:04.04#ibcon#read 3, iclass 24, count 0 2006.285.15:02:04.04#ibcon#about to read 4, iclass 24, count 0 2006.285.15:02:04.04#ibcon#read 4, iclass 24, count 0 2006.285.15:02:04.04#ibcon#about to read 5, iclass 24, count 0 2006.285.15:02:04.04#ibcon#read 5, iclass 24, count 0 2006.285.15:02:04.04#ibcon#about to read 6, iclass 24, count 0 2006.285.15:02:04.04#ibcon#read 6, iclass 24, count 0 2006.285.15:02:04.04#ibcon#end of sib2, iclass 24, count 0 2006.285.15:02:04.04#ibcon#*mode == 0, iclass 24, count 0 2006.285.15:02:04.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.15:02:04.04#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.15:02:04.04#ibcon#*before write, iclass 24, count 0 2006.285.15:02:04.04#ibcon#enter sib2, iclass 24, count 0 2006.285.15:02:04.04#ibcon#flushed, iclass 24, count 0 2006.285.15:02:04.04#ibcon#about to write, iclass 24, count 0 2006.285.15:02:04.04#ibcon#wrote, iclass 24, count 0 2006.285.15:02:04.04#ibcon#about to read 3, iclass 24, count 0 2006.285.15:02:04.08#ibcon#read 3, iclass 24, count 0 2006.285.15:02:04.08#ibcon#about to read 4, iclass 24, count 0 2006.285.15:02:04.08#ibcon#read 4, iclass 24, count 0 2006.285.15:02:04.08#ibcon#about to read 5, iclass 24, count 0 2006.285.15:02:04.08#ibcon#read 5, iclass 24, count 0 2006.285.15:02:04.08#ibcon#about to read 6, iclass 24, count 0 2006.285.15:02:04.08#ibcon#read 6, iclass 24, count 0 2006.285.15:02:04.08#ibcon#end of sib2, iclass 24, count 0 2006.285.15:02:04.08#ibcon#*after write, iclass 24, count 0 2006.285.15:02:04.08#ibcon#*before return 0, iclass 24, count 0 2006.285.15:02:04.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:02:04.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:02:04.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.15:02:04.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.15:02:04.08$vck44/vb=8,4 2006.285.15:02:04.08#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.15:02:04.08#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.15:02:04.08#ibcon#ireg 11 cls_cnt 2 2006.285.15:02:04.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:02:04.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:02:04.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:02:04.14#ibcon#enter wrdev, iclass 26, count 2 2006.285.15:02:04.14#ibcon#first serial, iclass 26, count 2 2006.285.15:02:04.14#ibcon#enter sib2, iclass 26, count 2 2006.285.15:02:04.14#ibcon#flushed, iclass 26, count 2 2006.285.15:02:04.14#ibcon#about to write, iclass 26, count 2 2006.285.15:02:04.14#ibcon#wrote, iclass 26, count 2 2006.285.15:02:04.14#ibcon#about to read 3, iclass 26, count 2 2006.285.15:02:04.16#ibcon#read 3, iclass 26, count 2 2006.285.15:02:04.16#ibcon#about to read 4, iclass 26, count 2 2006.285.15:02:04.16#ibcon#read 4, iclass 26, count 2 2006.285.15:02:04.16#ibcon#about to read 5, iclass 26, count 2 2006.285.15:02:04.16#ibcon#read 5, iclass 26, count 2 2006.285.15:02:04.16#ibcon#about to read 6, iclass 26, count 2 2006.285.15:02:04.16#ibcon#read 6, iclass 26, count 2 2006.285.15:02:04.16#ibcon#end of sib2, iclass 26, count 2 2006.285.15:02:04.16#ibcon#*mode == 0, iclass 26, count 2 2006.285.15:02:04.16#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.15:02:04.16#ibcon#[27=AT08-04\r\n] 2006.285.15:02:04.16#ibcon#*before write, iclass 26, count 2 2006.285.15:02:04.16#ibcon#enter sib2, iclass 26, count 2 2006.285.15:02:04.16#ibcon#flushed, iclass 26, count 2 2006.285.15:02:04.16#ibcon#about to write, iclass 26, count 2 2006.285.15:02:04.16#ibcon#wrote, iclass 26, count 2 2006.285.15:02:04.16#ibcon#about to read 3, iclass 26, count 2 2006.285.15:02:04.19#ibcon#read 3, iclass 26, count 2 2006.285.15:02:04.19#ibcon#about to read 4, iclass 26, count 2 2006.285.15:02:04.19#ibcon#read 4, iclass 26, count 2 2006.285.15:02:04.19#ibcon#about to read 5, iclass 26, count 2 2006.285.15:02:04.19#ibcon#read 5, iclass 26, count 2 2006.285.15:02:04.19#ibcon#about to read 6, iclass 26, count 2 2006.285.15:02:04.19#ibcon#read 6, iclass 26, count 2 2006.285.15:02:04.19#ibcon#end of sib2, iclass 26, count 2 2006.285.15:02:04.19#ibcon#*after write, iclass 26, count 2 2006.285.15:02:04.19#ibcon#*before return 0, iclass 26, count 2 2006.285.15:02:04.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:02:04.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:02:04.19#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.15:02:04.19#ibcon#ireg 7 cls_cnt 0 2006.285.15:02:04.19#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:02:04.31#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:02:04.31#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:02:04.31#ibcon#enter wrdev, iclass 26, count 0 2006.285.15:02:04.31#ibcon#first serial, iclass 26, count 0 2006.285.15:02:04.31#ibcon#enter sib2, iclass 26, count 0 2006.285.15:02:04.31#ibcon#flushed, iclass 26, count 0 2006.285.15:02:04.31#ibcon#about to write, iclass 26, count 0 2006.285.15:02:04.31#ibcon#wrote, iclass 26, count 0 2006.285.15:02:04.31#ibcon#about to read 3, iclass 26, count 0 2006.285.15:02:04.33#ibcon#read 3, iclass 26, count 0 2006.285.15:02:04.33#ibcon#about to read 4, iclass 26, count 0 2006.285.15:02:04.33#ibcon#read 4, iclass 26, count 0 2006.285.15:02:04.33#ibcon#about to read 5, iclass 26, count 0 2006.285.15:02:04.33#ibcon#read 5, iclass 26, count 0 2006.285.15:02:04.33#ibcon#about to read 6, iclass 26, count 0 2006.285.15:02:04.33#ibcon#read 6, iclass 26, count 0 2006.285.15:02:04.33#ibcon#end of sib2, iclass 26, count 0 2006.285.15:02:04.33#ibcon#*mode == 0, iclass 26, count 0 2006.285.15:02:04.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.15:02:04.33#ibcon#[27=USB\r\n] 2006.285.15:02:04.33#ibcon#*before write, iclass 26, count 0 2006.285.15:02:04.33#ibcon#enter sib2, iclass 26, count 0 2006.285.15:02:04.33#ibcon#flushed, iclass 26, count 0 2006.285.15:02:04.33#ibcon#about to write, iclass 26, count 0 2006.285.15:02:04.33#ibcon#wrote, iclass 26, count 0 2006.285.15:02:04.33#ibcon#about to read 3, iclass 26, count 0 2006.285.15:02:04.36#ibcon#read 3, iclass 26, count 0 2006.285.15:02:04.36#ibcon#about to read 4, iclass 26, count 0 2006.285.15:02:04.36#ibcon#read 4, iclass 26, count 0 2006.285.15:02:04.36#ibcon#about to read 5, iclass 26, count 0 2006.285.15:02:04.36#ibcon#read 5, iclass 26, count 0 2006.285.15:02:04.36#ibcon#about to read 6, iclass 26, count 0 2006.285.15:02:04.36#ibcon#read 6, iclass 26, count 0 2006.285.15:02:04.36#ibcon#end of sib2, iclass 26, count 0 2006.285.15:02:04.36#ibcon#*after write, iclass 26, count 0 2006.285.15:02:04.36#ibcon#*before return 0, iclass 26, count 0 2006.285.15:02:04.36#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:02:04.36#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:02:04.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.15:02:04.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.15:02:04.36$vck44/vabw=wide 2006.285.15:02:04.36#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.15:02:04.36#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.15:02:04.36#ibcon#ireg 8 cls_cnt 0 2006.285.15:02:04.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:02:04.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:02:04.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:02:04.36#ibcon#enter wrdev, iclass 28, count 0 2006.285.15:02:04.36#ibcon#first serial, iclass 28, count 0 2006.285.15:02:04.36#ibcon#enter sib2, iclass 28, count 0 2006.285.15:02:04.36#ibcon#flushed, iclass 28, count 0 2006.285.15:02:04.36#ibcon#about to write, iclass 28, count 0 2006.285.15:02:04.36#ibcon#wrote, iclass 28, count 0 2006.285.15:02:04.36#ibcon#about to read 3, iclass 28, count 0 2006.285.15:02:04.38#ibcon#read 3, iclass 28, count 0 2006.285.15:02:04.38#ibcon#about to read 4, iclass 28, count 0 2006.285.15:02:04.38#ibcon#read 4, iclass 28, count 0 2006.285.15:02:04.38#ibcon#about to read 5, iclass 28, count 0 2006.285.15:02:04.38#ibcon#read 5, iclass 28, count 0 2006.285.15:02:04.38#ibcon#about to read 6, iclass 28, count 0 2006.285.15:02:04.38#ibcon#read 6, iclass 28, count 0 2006.285.15:02:04.38#ibcon#end of sib2, iclass 28, count 0 2006.285.15:02:04.38#ibcon#*mode == 0, iclass 28, count 0 2006.285.15:02:04.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.15:02:04.38#ibcon#[25=BW32\r\n] 2006.285.15:02:04.38#ibcon#*before write, iclass 28, count 0 2006.285.15:02:04.38#ibcon#enter sib2, iclass 28, count 0 2006.285.15:02:04.38#ibcon#flushed, iclass 28, count 0 2006.285.15:02:04.38#ibcon#about to write, iclass 28, count 0 2006.285.15:02:04.38#ibcon#wrote, iclass 28, count 0 2006.285.15:02:04.38#ibcon#about to read 3, iclass 28, count 0 2006.285.15:02:04.41#ibcon#read 3, iclass 28, count 0 2006.285.15:02:04.41#ibcon#about to read 4, iclass 28, count 0 2006.285.15:02:04.41#ibcon#read 4, iclass 28, count 0 2006.285.15:02:04.41#ibcon#about to read 5, iclass 28, count 0 2006.285.15:02:04.41#ibcon#read 5, iclass 28, count 0 2006.285.15:02:04.41#ibcon#about to read 6, iclass 28, count 0 2006.285.15:02:04.41#ibcon#read 6, iclass 28, count 0 2006.285.15:02:04.41#ibcon#end of sib2, iclass 28, count 0 2006.285.15:02:04.41#ibcon#*after write, iclass 28, count 0 2006.285.15:02:04.41#ibcon#*before return 0, iclass 28, count 0 2006.285.15:02:04.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:02:04.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:02:04.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.15:02:04.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.15:02:04.41$vck44/vbbw=wide 2006.285.15:02:04.41#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.15:02:04.41#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.15:02:04.41#ibcon#ireg 8 cls_cnt 0 2006.285.15:02:04.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:02:04.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:02:04.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:02:04.48#ibcon#enter wrdev, iclass 30, count 0 2006.285.15:02:04.48#ibcon#first serial, iclass 30, count 0 2006.285.15:02:04.48#ibcon#enter sib2, iclass 30, count 0 2006.285.15:02:04.48#ibcon#flushed, iclass 30, count 0 2006.285.15:02:04.48#ibcon#about to write, iclass 30, count 0 2006.285.15:02:04.48#ibcon#wrote, iclass 30, count 0 2006.285.15:02:04.48#ibcon#about to read 3, iclass 30, count 0 2006.285.15:02:04.50#ibcon#read 3, iclass 30, count 0 2006.285.15:02:04.50#ibcon#about to read 4, iclass 30, count 0 2006.285.15:02:04.50#ibcon#read 4, iclass 30, count 0 2006.285.15:02:04.50#ibcon#about to read 5, iclass 30, count 0 2006.285.15:02:04.50#ibcon#read 5, iclass 30, count 0 2006.285.15:02:04.50#ibcon#about to read 6, iclass 30, count 0 2006.285.15:02:04.50#ibcon#read 6, iclass 30, count 0 2006.285.15:02:04.50#ibcon#end of sib2, iclass 30, count 0 2006.285.15:02:04.50#ibcon#*mode == 0, iclass 30, count 0 2006.285.15:02:04.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.15:02:04.50#ibcon#[27=BW32\r\n] 2006.285.15:02:04.50#ibcon#*before write, iclass 30, count 0 2006.285.15:02:04.50#ibcon#enter sib2, iclass 30, count 0 2006.285.15:02:04.50#ibcon#flushed, iclass 30, count 0 2006.285.15:02:04.50#ibcon#about to write, iclass 30, count 0 2006.285.15:02:04.50#ibcon#wrote, iclass 30, count 0 2006.285.15:02:04.50#ibcon#about to read 3, iclass 30, count 0 2006.285.15:02:04.53#ibcon#read 3, iclass 30, count 0 2006.285.15:02:04.53#ibcon#about to read 4, iclass 30, count 0 2006.285.15:02:04.53#ibcon#read 4, iclass 30, count 0 2006.285.15:02:04.53#ibcon#about to read 5, iclass 30, count 0 2006.285.15:02:04.53#ibcon#read 5, iclass 30, count 0 2006.285.15:02:04.53#ibcon#about to read 6, iclass 30, count 0 2006.285.15:02:04.53#ibcon#read 6, iclass 30, count 0 2006.285.15:02:04.53#ibcon#end of sib2, iclass 30, count 0 2006.285.15:02:04.53#ibcon#*after write, iclass 30, count 0 2006.285.15:02:04.53#ibcon#*before return 0, iclass 30, count 0 2006.285.15:02:04.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:02:04.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:02:04.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.15:02:04.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.15:02:04.53$setupk4/ifdk4 2006.285.15:02:04.53$ifdk4/lo= 2006.285.15:02:04.53$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.15:02:04.53$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.15:02:04.53$ifdk4/patch= 2006.285.15:02:04.53$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.15:02:04.53$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.15:02:04.53$setupk4/!*+20s 2006.285.15:02:10.69#abcon#<5=/03 2.0 3.6 19.15 931014.9\r\n> 2006.285.15:02:10.71#abcon#{5=INTERFACE CLEAR} 2006.285.15:02:10.77#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:02:18.25$setupk4/"tpicd 2006.285.15:02:18.25$setupk4/echo=off 2006.285.15:02:18.25$setupk4/xlog=off 2006.285.15:02:18.25:!2006.285.15:06:13 2006.285.15:02:19.13#trakl#Source acquired 2006.285.15:02:19.13#flagr#flagr/antenna,acquired 2006.285.15:06:13.00:preob 2006.285.15:06:14.14/onsource/TRACKING 2006.285.15:06:14.14:!2006.285.15:06:23 2006.285.15:06:23.00:"tape 2006.285.15:06:23.00:"st=record 2006.285.15:06:23.00:data_valid=on 2006.285.15:06:23.00:midob 2006.285.15:06:23.14/onsource/TRACKING 2006.285.15:06:23.14/wx/19.15,1015.0,93 2006.285.15:06:23.35/cable/+6.5008E-03 2006.285.15:06:24.44/va/01,07,usb,yes,33,35 2006.285.15:06:24.44/va/02,06,usb,yes,33,33 2006.285.15:06:24.44/va/03,07,usb,yes,32,34 2006.285.15:06:24.44/va/04,06,usb,yes,34,35 2006.285.15:06:24.44/va/05,03,usb,yes,33,34 2006.285.15:06:24.44/va/06,04,usb,yes,30,29 2006.285.15:06:24.44/va/07,04,usb,yes,30,31 2006.285.15:06:24.44/va/08,03,usb,yes,31,38 2006.285.15:06:24.67/valo/01,524.99,yes,locked 2006.285.15:06:24.67/valo/02,534.99,yes,locked 2006.285.15:06:24.67/valo/03,564.99,yes,locked 2006.285.15:06:24.67/valo/04,624.99,yes,locked 2006.285.15:06:24.67/valo/05,734.99,yes,locked 2006.285.15:06:24.67/valo/06,814.99,yes,locked 2006.285.15:06:24.67/valo/07,864.99,yes,locked 2006.285.15:06:24.67/valo/08,884.99,yes,locked 2006.285.15:06:25.76/vb/01,04,usb,yes,31,29 2006.285.15:06:25.76/vb/02,05,usb,yes,29,29 2006.285.15:06:25.76/vb/03,04,usb,yes,30,33 2006.285.15:06:25.76/vb/04,05,usb,yes,30,29 2006.285.15:06:25.76/vb/05,04,usb,yes,27,29 2006.285.15:06:25.76/vb/06,03,usb,yes,39,34 2006.285.15:06:25.76/vb/07,04,usb,yes,31,31 2006.285.15:06:25.76/vb/08,04,usb,yes,28,32 2006.285.15:06:26.00/vblo/01,629.99,yes,locked 2006.285.15:06:26.00/vblo/02,634.99,yes,locked 2006.285.15:06:26.00/vblo/03,649.99,yes,locked 2006.285.15:06:26.00/vblo/04,679.99,yes,locked 2006.285.15:06:26.00/vblo/05,709.99,yes,locked 2006.285.15:06:26.00/vblo/06,719.99,yes,locked 2006.285.15:06:26.00/vblo/07,734.99,yes,locked 2006.285.15:06:26.00/vblo/08,744.99,yes,locked 2006.285.15:06:26.15/vabw/8 2006.285.15:06:26.30/vbbw/8 2006.285.15:06:26.40/xfe/off,on,12.0 2006.285.15:06:26.78/ifatt/23,28,28,28 2006.285.15:06:27.08/fmout-gps/S +2.75E-07 2006.285.15:06:27.10:!2006.285.15:10:33 2006.285.15:10:33.01:data_valid=off 2006.285.15:10:33.01:"et 2006.285.15:10:33.01:!+3s 2006.285.15:10:36.02:"tape 2006.285.15:10:36.02:postob 2006.285.15:10:36.18/cable/+6.5007E-03 2006.285.15:10:36.18/wx/19.16,1014.9,92 2006.285.15:10:37.08/fmout-gps/S +2.83E-07 2006.285.15:10:37.08:scan_name=285-1520,jd0610,170 2006.285.15:10:37.08:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.285.15:10:38.13#flagr#flagr/antenna,new-source 2006.285.15:10:38.13:checkk5 2006.285.15:10:38.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.15:10:39.23/chk_autoobs//k5ts2/ autoobs is running! 2006.285.15:10:39.78/chk_autoobs//k5ts3/ autoobs is running! 2006.285.15:10:40.23/chk_autoobs//k5ts4/ autoobs is running! 2006.285.15:10:40.57/chk_obsdata//k5ts1/T2851506??a.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.285.15:10:41.02/chk_obsdata//k5ts2/T2851506??b.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.285.15:10:41.70/chk_obsdata//k5ts3/T2851506??c.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.285.15:10:42.28/chk_obsdata//k5ts4/T2851506??d.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.285.15:10:43.14/k5log//k5ts1_log_newline 2006.285.15:10:43.92/k5log//k5ts2_log_newline 2006.285.15:10:44.71/k5log//k5ts3_log_newline 2006.285.15:10:45.54/k5log//k5ts4_log_newline 2006.285.15:10:45.56/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.15:10:45.57:setupk4=1 2006.285.15:10:45.57$setupk4/echo=on 2006.285.15:10:45.57$setupk4/pcalon 2006.285.15:10:45.57$pcalon/"no phase cal control is implemented here 2006.285.15:10:45.57$setupk4/"tpicd=stop 2006.285.15:10:45.57$setupk4/"rec=synch_on 2006.285.15:10:45.57$setupk4/"rec_mode=128 2006.285.15:10:45.57$setupk4/!* 2006.285.15:10:45.57$setupk4/recpk4 2006.285.15:10:45.57$recpk4/recpatch= 2006.285.15:10:45.57$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.15:10:45.57$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.15:10:45.57$setupk4/vck44 2006.285.15:10:45.57$vck44/valo=1,524.99 2006.285.15:10:45.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.15:10:45.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.15:10:45.57#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:45.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:10:45.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:10:45.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:10:45.57#ibcon#enter wrdev, iclass 23, count 0 2006.285.15:10:45.57#ibcon#first serial, iclass 23, count 0 2006.285.15:10:45.57#ibcon#enter sib2, iclass 23, count 0 2006.285.15:10:45.57#ibcon#flushed, iclass 23, count 0 2006.285.15:10:45.57#ibcon#about to write, iclass 23, count 0 2006.285.15:10:45.57#ibcon#wrote, iclass 23, count 0 2006.285.15:10:45.57#ibcon#about to read 3, iclass 23, count 0 2006.285.15:10:45.59#ibcon#read 3, iclass 23, count 0 2006.285.15:10:45.59#ibcon#about to read 4, iclass 23, count 0 2006.285.15:10:45.59#ibcon#read 4, iclass 23, count 0 2006.285.15:10:45.59#ibcon#about to read 5, iclass 23, count 0 2006.285.15:10:45.59#ibcon#read 5, iclass 23, count 0 2006.285.15:10:45.59#ibcon#about to read 6, iclass 23, count 0 2006.285.15:10:45.59#ibcon#read 6, iclass 23, count 0 2006.285.15:10:45.59#ibcon#end of sib2, iclass 23, count 0 2006.285.15:10:45.59#ibcon#*mode == 0, iclass 23, count 0 2006.285.15:10:45.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.15:10:45.59#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.15:10:45.59#ibcon#*before write, iclass 23, count 0 2006.285.15:10:45.59#ibcon#enter sib2, iclass 23, count 0 2006.285.15:10:45.59#ibcon#flushed, iclass 23, count 0 2006.285.15:10:45.59#ibcon#about to write, iclass 23, count 0 2006.285.15:10:45.59#ibcon#wrote, iclass 23, count 0 2006.285.15:10:45.59#ibcon#about to read 3, iclass 23, count 0 2006.285.15:10:45.64#ibcon#read 3, iclass 23, count 0 2006.285.15:10:45.64#ibcon#about to read 4, iclass 23, count 0 2006.285.15:10:45.64#ibcon#read 4, iclass 23, count 0 2006.285.15:10:45.64#ibcon#about to read 5, iclass 23, count 0 2006.285.15:10:45.64#ibcon#read 5, iclass 23, count 0 2006.285.15:10:45.64#ibcon#about to read 6, iclass 23, count 0 2006.285.15:10:45.64#ibcon#read 6, iclass 23, count 0 2006.285.15:10:45.64#ibcon#end of sib2, iclass 23, count 0 2006.285.15:10:45.64#ibcon#*after write, iclass 23, count 0 2006.285.15:10:45.64#ibcon#*before return 0, iclass 23, count 0 2006.285.15:10:45.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:10:45.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:10:45.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.15:10:45.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.15:10:45.64$vck44/va=1,7 2006.285.15:10:45.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.15:10:45.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.15:10:45.64#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:45.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:10:45.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:10:45.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:10:45.64#ibcon#enter wrdev, iclass 25, count 2 2006.285.15:10:45.64#ibcon#first serial, iclass 25, count 2 2006.285.15:10:45.64#ibcon#enter sib2, iclass 25, count 2 2006.285.15:10:45.64#ibcon#flushed, iclass 25, count 2 2006.285.15:10:45.64#ibcon#about to write, iclass 25, count 2 2006.285.15:10:45.64#ibcon#wrote, iclass 25, count 2 2006.285.15:10:45.64#ibcon#about to read 3, iclass 25, count 2 2006.285.15:10:45.66#ibcon#read 3, iclass 25, count 2 2006.285.15:10:45.66#ibcon#about to read 4, iclass 25, count 2 2006.285.15:10:45.66#ibcon#read 4, iclass 25, count 2 2006.285.15:10:45.66#ibcon#about to read 5, iclass 25, count 2 2006.285.15:10:45.66#ibcon#read 5, iclass 25, count 2 2006.285.15:10:45.66#ibcon#about to read 6, iclass 25, count 2 2006.285.15:10:45.66#ibcon#read 6, iclass 25, count 2 2006.285.15:10:45.66#ibcon#end of sib2, iclass 25, count 2 2006.285.15:10:45.66#ibcon#*mode == 0, iclass 25, count 2 2006.285.15:10:45.66#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.15:10:45.66#ibcon#[25=AT01-07\r\n] 2006.285.15:10:45.66#ibcon#*before write, iclass 25, count 2 2006.285.15:10:45.66#ibcon#enter sib2, iclass 25, count 2 2006.285.15:10:45.66#ibcon#flushed, iclass 25, count 2 2006.285.15:10:45.66#ibcon#about to write, iclass 25, count 2 2006.285.15:10:45.66#ibcon#wrote, iclass 25, count 2 2006.285.15:10:45.66#ibcon#about to read 3, iclass 25, count 2 2006.285.15:10:45.69#ibcon#read 3, iclass 25, count 2 2006.285.15:10:45.69#ibcon#about to read 4, iclass 25, count 2 2006.285.15:10:45.69#ibcon#read 4, iclass 25, count 2 2006.285.15:10:45.69#ibcon#about to read 5, iclass 25, count 2 2006.285.15:10:45.69#ibcon#read 5, iclass 25, count 2 2006.285.15:10:45.69#ibcon#about to read 6, iclass 25, count 2 2006.285.15:10:45.69#ibcon#read 6, iclass 25, count 2 2006.285.15:10:45.69#ibcon#end of sib2, iclass 25, count 2 2006.285.15:10:45.69#ibcon#*after write, iclass 25, count 2 2006.285.15:10:45.69#ibcon#*before return 0, iclass 25, count 2 2006.285.15:10:45.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:10:45.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:10:45.69#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.15:10:45.69#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:45.69#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:10:45.81#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:10:45.81#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:10:45.81#ibcon#enter wrdev, iclass 25, count 0 2006.285.15:10:45.81#ibcon#first serial, iclass 25, count 0 2006.285.15:10:45.81#ibcon#enter sib2, iclass 25, count 0 2006.285.15:10:45.81#ibcon#flushed, iclass 25, count 0 2006.285.15:10:45.81#ibcon#about to write, iclass 25, count 0 2006.285.15:10:45.81#ibcon#wrote, iclass 25, count 0 2006.285.15:10:45.81#ibcon#about to read 3, iclass 25, count 0 2006.285.15:10:45.83#ibcon#read 3, iclass 25, count 0 2006.285.15:10:45.83#ibcon#about to read 4, iclass 25, count 0 2006.285.15:10:45.83#ibcon#read 4, iclass 25, count 0 2006.285.15:10:45.83#ibcon#about to read 5, iclass 25, count 0 2006.285.15:10:45.83#ibcon#read 5, iclass 25, count 0 2006.285.15:10:45.83#ibcon#about to read 6, iclass 25, count 0 2006.285.15:10:45.83#ibcon#read 6, iclass 25, count 0 2006.285.15:10:45.83#ibcon#end of sib2, iclass 25, count 0 2006.285.15:10:45.83#ibcon#*mode == 0, iclass 25, count 0 2006.285.15:10:45.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.15:10:45.83#ibcon#[25=USB\r\n] 2006.285.15:10:45.83#ibcon#*before write, iclass 25, count 0 2006.285.15:10:45.83#ibcon#enter sib2, iclass 25, count 0 2006.285.15:10:45.83#ibcon#flushed, iclass 25, count 0 2006.285.15:10:45.83#ibcon#about to write, iclass 25, count 0 2006.285.15:10:45.83#ibcon#wrote, iclass 25, count 0 2006.285.15:10:45.83#ibcon#about to read 3, iclass 25, count 0 2006.285.15:10:45.86#ibcon#read 3, iclass 25, count 0 2006.285.15:10:45.86#ibcon#about to read 4, iclass 25, count 0 2006.285.15:10:45.86#ibcon#read 4, iclass 25, count 0 2006.285.15:10:45.86#ibcon#about to read 5, iclass 25, count 0 2006.285.15:10:45.86#ibcon#read 5, iclass 25, count 0 2006.285.15:10:45.86#ibcon#about to read 6, iclass 25, count 0 2006.285.15:10:45.86#ibcon#read 6, iclass 25, count 0 2006.285.15:10:45.86#ibcon#end of sib2, iclass 25, count 0 2006.285.15:10:45.86#ibcon#*after write, iclass 25, count 0 2006.285.15:10:45.86#ibcon#*before return 0, iclass 25, count 0 2006.285.15:10:45.86#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:10:45.86#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:10:45.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.15:10:45.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.15:10:45.86$vck44/valo=2,534.99 2006.285.15:10:45.86#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.15:10:45.86#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.15:10:45.86#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:45.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:10:45.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:10:45.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:10:45.86#ibcon#enter wrdev, iclass 27, count 0 2006.285.15:10:45.86#ibcon#first serial, iclass 27, count 0 2006.285.15:10:45.86#ibcon#enter sib2, iclass 27, count 0 2006.285.15:10:45.86#ibcon#flushed, iclass 27, count 0 2006.285.15:10:45.86#ibcon#about to write, iclass 27, count 0 2006.285.15:10:45.86#ibcon#wrote, iclass 27, count 0 2006.285.15:10:45.86#ibcon#about to read 3, iclass 27, count 0 2006.285.15:10:45.88#ibcon#read 3, iclass 27, count 0 2006.285.15:10:45.88#ibcon#about to read 4, iclass 27, count 0 2006.285.15:10:45.88#ibcon#read 4, iclass 27, count 0 2006.285.15:10:45.88#ibcon#about to read 5, iclass 27, count 0 2006.285.15:10:45.88#ibcon#read 5, iclass 27, count 0 2006.285.15:10:45.88#ibcon#about to read 6, iclass 27, count 0 2006.285.15:10:45.88#ibcon#read 6, iclass 27, count 0 2006.285.15:10:45.88#ibcon#end of sib2, iclass 27, count 0 2006.285.15:10:45.88#ibcon#*mode == 0, iclass 27, count 0 2006.285.15:10:45.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.15:10:45.88#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.15:10:45.88#ibcon#*before write, iclass 27, count 0 2006.285.15:10:45.88#ibcon#enter sib2, iclass 27, count 0 2006.285.15:10:45.88#ibcon#flushed, iclass 27, count 0 2006.285.15:10:45.88#ibcon#about to write, iclass 27, count 0 2006.285.15:10:45.88#ibcon#wrote, iclass 27, count 0 2006.285.15:10:45.88#ibcon#about to read 3, iclass 27, count 0 2006.285.15:10:45.92#ibcon#read 3, iclass 27, count 0 2006.285.15:10:45.92#ibcon#about to read 4, iclass 27, count 0 2006.285.15:10:45.92#ibcon#read 4, iclass 27, count 0 2006.285.15:10:45.92#ibcon#about to read 5, iclass 27, count 0 2006.285.15:10:45.92#ibcon#read 5, iclass 27, count 0 2006.285.15:10:45.92#ibcon#about to read 6, iclass 27, count 0 2006.285.15:10:45.92#ibcon#read 6, iclass 27, count 0 2006.285.15:10:45.92#ibcon#end of sib2, iclass 27, count 0 2006.285.15:10:45.92#ibcon#*after write, iclass 27, count 0 2006.285.15:10:45.92#ibcon#*before return 0, iclass 27, count 0 2006.285.15:10:45.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:10:45.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:10:45.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.15:10:45.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.15:10:45.92$vck44/va=2,6 2006.285.15:10:45.92#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.15:10:45.92#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.15:10:45.92#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:45.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:10:45.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:10:45.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:10:45.98#ibcon#enter wrdev, iclass 29, count 2 2006.285.15:10:45.98#ibcon#first serial, iclass 29, count 2 2006.285.15:10:45.98#ibcon#enter sib2, iclass 29, count 2 2006.285.15:10:45.98#ibcon#flushed, iclass 29, count 2 2006.285.15:10:45.98#ibcon#about to write, iclass 29, count 2 2006.285.15:10:45.98#ibcon#wrote, iclass 29, count 2 2006.285.15:10:45.98#ibcon#about to read 3, iclass 29, count 2 2006.285.15:10:46.00#ibcon#read 3, iclass 29, count 2 2006.285.15:10:46.37#ibcon#about to read 4, iclass 29, count 2 2006.285.15:10:46.37#ibcon#read 4, iclass 29, count 2 2006.285.15:10:46.37#ibcon#about to read 5, iclass 29, count 2 2006.285.15:10:46.37#ibcon#read 5, iclass 29, count 2 2006.285.15:10:46.37#ibcon#about to read 6, iclass 29, count 2 2006.285.15:10:46.37#ibcon#read 6, iclass 29, count 2 2006.285.15:10:46.37#ibcon#end of sib2, iclass 29, count 2 2006.285.15:10:46.37#ibcon#*mode == 0, iclass 29, count 2 2006.285.15:10:46.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.15:10:46.37#ibcon#[25=AT02-06\r\n] 2006.285.15:10:46.37#ibcon#*before write, iclass 29, count 2 2006.285.15:10:46.37#ibcon#enter sib2, iclass 29, count 2 2006.285.15:10:46.37#ibcon#flushed, iclass 29, count 2 2006.285.15:10:46.37#ibcon#about to write, iclass 29, count 2 2006.285.15:10:46.37#ibcon#wrote, iclass 29, count 2 2006.285.15:10:46.37#ibcon#about to read 3, iclass 29, count 2 2006.285.15:10:46.40#ibcon#read 3, iclass 29, count 2 2006.285.15:10:46.40#ibcon#about to read 4, iclass 29, count 2 2006.285.15:10:46.40#ibcon#read 4, iclass 29, count 2 2006.285.15:10:46.40#ibcon#about to read 5, iclass 29, count 2 2006.285.15:10:46.40#ibcon#read 5, iclass 29, count 2 2006.285.15:10:46.40#ibcon#about to read 6, iclass 29, count 2 2006.285.15:10:46.40#ibcon#read 6, iclass 29, count 2 2006.285.15:10:46.40#ibcon#end of sib2, iclass 29, count 2 2006.285.15:10:46.40#ibcon#*after write, iclass 29, count 2 2006.285.15:10:46.40#ibcon#*before return 0, iclass 29, count 2 2006.285.15:10:46.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:10:46.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:10:46.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.15:10:46.40#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:46.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:10:46.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:10:46.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:10:46.52#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:10:46.52#ibcon#first serial, iclass 29, count 0 2006.285.15:10:46.52#ibcon#enter sib2, iclass 29, count 0 2006.285.15:10:46.52#ibcon#flushed, iclass 29, count 0 2006.285.15:10:46.52#ibcon#about to write, iclass 29, count 0 2006.285.15:10:46.52#ibcon#wrote, iclass 29, count 0 2006.285.15:10:46.52#ibcon#about to read 3, iclass 29, count 0 2006.285.15:10:46.54#ibcon#read 3, iclass 29, count 0 2006.285.15:10:46.54#ibcon#about to read 4, iclass 29, count 0 2006.285.15:10:46.54#ibcon#read 4, iclass 29, count 0 2006.285.15:10:46.54#ibcon#about to read 5, iclass 29, count 0 2006.285.15:10:46.54#ibcon#read 5, iclass 29, count 0 2006.285.15:10:46.54#ibcon#about to read 6, iclass 29, count 0 2006.285.15:10:46.54#ibcon#read 6, iclass 29, count 0 2006.285.15:10:46.54#ibcon#end of sib2, iclass 29, count 0 2006.285.15:10:46.54#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:10:46.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:10:46.54#ibcon#[25=USB\r\n] 2006.285.15:10:46.54#ibcon#*before write, iclass 29, count 0 2006.285.15:10:46.54#ibcon#enter sib2, iclass 29, count 0 2006.285.15:10:46.54#ibcon#flushed, iclass 29, count 0 2006.285.15:10:46.54#ibcon#about to write, iclass 29, count 0 2006.285.15:10:46.54#ibcon#wrote, iclass 29, count 0 2006.285.15:10:46.54#ibcon#about to read 3, iclass 29, count 0 2006.285.15:10:46.57#ibcon#read 3, iclass 29, count 0 2006.285.15:10:46.57#ibcon#about to read 4, iclass 29, count 0 2006.285.15:10:46.57#ibcon#read 4, iclass 29, count 0 2006.285.15:10:46.57#ibcon#about to read 5, iclass 29, count 0 2006.285.15:10:46.57#ibcon#read 5, iclass 29, count 0 2006.285.15:10:46.57#ibcon#about to read 6, iclass 29, count 0 2006.285.15:10:46.57#ibcon#read 6, iclass 29, count 0 2006.285.15:10:46.57#ibcon#end of sib2, iclass 29, count 0 2006.285.15:10:46.57#ibcon#*after write, iclass 29, count 0 2006.285.15:10:46.57#ibcon#*before return 0, iclass 29, count 0 2006.285.15:10:46.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:10:46.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:10:46.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:10:46.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:10:46.57$vck44/valo=3,564.99 2006.285.15:10:46.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.15:10:46.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.15:10:46.57#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:46.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:10:46.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:10:46.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:10:46.57#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:10:46.57#ibcon#first serial, iclass 31, count 0 2006.285.15:10:46.57#ibcon#enter sib2, iclass 31, count 0 2006.285.15:10:46.57#ibcon#flushed, iclass 31, count 0 2006.285.15:10:46.57#ibcon#about to write, iclass 31, count 0 2006.285.15:10:46.57#ibcon#wrote, iclass 31, count 0 2006.285.15:10:46.57#ibcon#about to read 3, iclass 31, count 0 2006.285.15:10:46.59#ibcon#read 3, iclass 31, count 0 2006.285.15:10:46.59#ibcon#about to read 4, iclass 31, count 0 2006.285.15:10:46.59#ibcon#read 4, iclass 31, count 0 2006.285.15:10:46.59#ibcon#about to read 5, iclass 31, count 0 2006.285.15:10:46.59#ibcon#read 5, iclass 31, count 0 2006.285.15:10:46.59#ibcon#about to read 6, iclass 31, count 0 2006.285.15:10:46.59#ibcon#read 6, iclass 31, count 0 2006.285.15:10:46.59#ibcon#end of sib2, iclass 31, count 0 2006.285.15:10:46.59#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:10:46.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:10:46.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.15:10:46.59#ibcon#*before write, iclass 31, count 0 2006.285.15:10:46.59#ibcon#enter sib2, iclass 31, count 0 2006.285.15:10:46.59#ibcon#flushed, iclass 31, count 0 2006.285.15:10:46.59#ibcon#about to write, iclass 31, count 0 2006.285.15:10:46.59#ibcon#wrote, iclass 31, count 0 2006.285.15:10:46.59#ibcon#about to read 3, iclass 31, count 0 2006.285.15:10:46.63#ibcon#read 3, iclass 31, count 0 2006.285.15:10:46.63#ibcon#about to read 4, iclass 31, count 0 2006.285.15:10:46.63#ibcon#read 4, iclass 31, count 0 2006.285.15:10:46.63#ibcon#about to read 5, iclass 31, count 0 2006.285.15:10:46.63#ibcon#read 5, iclass 31, count 0 2006.285.15:10:46.63#ibcon#about to read 6, iclass 31, count 0 2006.285.15:10:46.63#ibcon#read 6, iclass 31, count 0 2006.285.15:10:46.63#ibcon#end of sib2, iclass 31, count 0 2006.285.15:10:46.63#ibcon#*after write, iclass 31, count 0 2006.285.15:10:46.63#ibcon#*before return 0, iclass 31, count 0 2006.285.15:10:46.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:10:46.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:10:46.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:10:46.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:10:46.63$vck44/va=3,7 2006.285.15:10:46.90#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.15:10:46.90#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.15:10:46.90#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:46.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:10:46.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:10:46.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:10:46.90#ibcon#enter wrdev, iclass 33, count 2 2006.285.15:10:46.90#ibcon#first serial, iclass 33, count 2 2006.285.15:10:46.90#ibcon#enter sib2, iclass 33, count 2 2006.285.15:10:46.90#ibcon#flushed, iclass 33, count 2 2006.285.15:10:46.90#ibcon#about to write, iclass 33, count 2 2006.285.15:10:46.90#ibcon#wrote, iclass 33, count 2 2006.285.15:10:46.90#ibcon#about to read 3, iclass 33, count 2 2006.285.15:10:46.92#ibcon#read 3, iclass 33, count 2 2006.285.15:10:46.92#ibcon#about to read 4, iclass 33, count 2 2006.285.15:10:46.92#ibcon#read 4, iclass 33, count 2 2006.285.15:10:46.92#ibcon#about to read 5, iclass 33, count 2 2006.285.15:10:46.92#ibcon#read 5, iclass 33, count 2 2006.285.15:10:46.92#ibcon#about to read 6, iclass 33, count 2 2006.285.15:10:46.92#ibcon#read 6, iclass 33, count 2 2006.285.15:10:46.92#ibcon#end of sib2, iclass 33, count 2 2006.285.15:10:46.92#ibcon#*mode == 0, iclass 33, count 2 2006.285.15:10:46.92#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.15:10:46.92#ibcon#[25=AT03-07\r\n] 2006.285.15:10:46.92#ibcon#*before write, iclass 33, count 2 2006.285.15:10:46.92#ibcon#enter sib2, iclass 33, count 2 2006.285.15:10:46.92#ibcon#flushed, iclass 33, count 2 2006.285.15:10:46.92#ibcon#about to write, iclass 33, count 2 2006.285.15:10:46.92#ibcon#wrote, iclass 33, count 2 2006.285.15:10:46.92#ibcon#about to read 3, iclass 33, count 2 2006.285.15:10:46.95#ibcon#read 3, iclass 33, count 2 2006.285.15:10:46.95#ibcon#about to read 4, iclass 33, count 2 2006.285.15:10:46.95#ibcon#read 4, iclass 33, count 2 2006.285.15:10:46.95#ibcon#about to read 5, iclass 33, count 2 2006.285.15:10:46.95#ibcon#read 5, iclass 33, count 2 2006.285.15:10:46.95#ibcon#about to read 6, iclass 33, count 2 2006.285.15:10:46.95#ibcon#read 6, iclass 33, count 2 2006.285.15:10:46.95#ibcon#end of sib2, iclass 33, count 2 2006.285.15:10:46.95#ibcon#*after write, iclass 33, count 2 2006.285.15:10:46.95#ibcon#*before return 0, iclass 33, count 2 2006.285.15:10:46.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:10:46.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:10:46.95#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.15:10:46.95#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:46.95#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:10:47.07#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:10:47.07#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:10:47.07#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:10:47.07#ibcon#first serial, iclass 33, count 0 2006.285.15:10:47.07#ibcon#enter sib2, iclass 33, count 0 2006.285.15:10:47.07#ibcon#flushed, iclass 33, count 0 2006.285.15:10:47.07#ibcon#about to write, iclass 33, count 0 2006.285.15:10:47.07#ibcon#wrote, iclass 33, count 0 2006.285.15:10:47.07#ibcon#about to read 3, iclass 33, count 0 2006.285.15:10:47.09#ibcon#read 3, iclass 33, count 0 2006.285.15:10:47.09#ibcon#about to read 4, iclass 33, count 0 2006.285.15:10:47.09#ibcon#read 4, iclass 33, count 0 2006.285.15:10:47.09#ibcon#about to read 5, iclass 33, count 0 2006.285.15:10:47.09#ibcon#read 5, iclass 33, count 0 2006.285.15:10:47.09#ibcon#about to read 6, iclass 33, count 0 2006.285.15:10:47.09#ibcon#read 6, iclass 33, count 0 2006.285.15:10:47.09#ibcon#end of sib2, iclass 33, count 0 2006.285.15:10:47.09#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:10:47.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:10:47.09#ibcon#[25=USB\r\n] 2006.285.15:10:47.09#ibcon#*before write, iclass 33, count 0 2006.285.15:10:47.09#ibcon#enter sib2, iclass 33, count 0 2006.285.15:10:47.09#ibcon#flushed, iclass 33, count 0 2006.285.15:10:47.09#ibcon#about to write, iclass 33, count 0 2006.285.15:10:47.09#ibcon#wrote, iclass 33, count 0 2006.285.15:10:47.09#ibcon#about to read 3, iclass 33, count 0 2006.285.15:10:47.12#ibcon#read 3, iclass 33, count 0 2006.285.15:10:47.12#ibcon#about to read 4, iclass 33, count 0 2006.285.15:10:47.12#ibcon#read 4, iclass 33, count 0 2006.285.15:10:47.12#ibcon#about to read 5, iclass 33, count 0 2006.285.15:10:47.12#ibcon#read 5, iclass 33, count 0 2006.285.15:10:47.12#ibcon#about to read 6, iclass 33, count 0 2006.285.15:10:47.12#ibcon#read 6, iclass 33, count 0 2006.285.15:10:47.12#ibcon#end of sib2, iclass 33, count 0 2006.285.15:10:47.12#ibcon#*after write, iclass 33, count 0 2006.285.15:10:47.12#ibcon#*before return 0, iclass 33, count 0 2006.285.15:10:47.12#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:10:47.12#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:10:47.12#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:10:47.12#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:10:47.12$vck44/valo=4,624.99 2006.285.15:10:47.12#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.15:10:47.12#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.15:10:47.12#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:47.12#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:10:47.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:10:47.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:10:47.12#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:10:47.12#ibcon#first serial, iclass 35, count 0 2006.285.15:10:47.12#ibcon#enter sib2, iclass 35, count 0 2006.285.15:10:47.12#ibcon#flushed, iclass 35, count 0 2006.285.15:10:47.12#ibcon#about to write, iclass 35, count 0 2006.285.15:10:47.12#ibcon#wrote, iclass 35, count 0 2006.285.15:10:47.12#ibcon#about to read 3, iclass 35, count 0 2006.285.15:10:47.14#ibcon#read 3, iclass 35, count 0 2006.285.15:10:47.14#ibcon#about to read 4, iclass 35, count 0 2006.285.15:10:47.14#ibcon#read 4, iclass 35, count 0 2006.285.15:10:47.14#ibcon#about to read 5, iclass 35, count 0 2006.285.15:10:47.14#ibcon#read 5, iclass 35, count 0 2006.285.15:10:47.14#ibcon#about to read 6, iclass 35, count 0 2006.285.15:10:47.14#ibcon#read 6, iclass 35, count 0 2006.285.15:10:47.14#ibcon#end of sib2, iclass 35, count 0 2006.285.15:10:47.14#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:10:47.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:10:47.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.15:10:47.14#ibcon#*before write, iclass 35, count 0 2006.285.15:10:47.14#ibcon#enter sib2, iclass 35, count 0 2006.285.15:10:47.14#ibcon#flushed, iclass 35, count 0 2006.285.15:10:47.14#ibcon#about to write, iclass 35, count 0 2006.285.15:10:47.14#ibcon#wrote, iclass 35, count 0 2006.285.15:10:47.14#ibcon#about to read 3, iclass 35, count 0 2006.285.15:10:47.18#ibcon#read 3, iclass 35, count 0 2006.285.15:10:47.18#ibcon#about to read 4, iclass 35, count 0 2006.285.15:10:47.18#ibcon#read 4, iclass 35, count 0 2006.285.15:10:47.18#ibcon#about to read 5, iclass 35, count 0 2006.285.15:10:47.18#ibcon#read 5, iclass 35, count 0 2006.285.15:10:47.18#ibcon#about to read 6, iclass 35, count 0 2006.285.15:10:47.18#ibcon#read 6, iclass 35, count 0 2006.285.15:10:47.18#ibcon#end of sib2, iclass 35, count 0 2006.285.15:10:47.18#ibcon#*after write, iclass 35, count 0 2006.285.15:10:47.18#ibcon#*before return 0, iclass 35, count 0 2006.285.15:10:47.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:10:47.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:10:47.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:10:47.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:10:47.18$vck44/va=4,6 2006.285.15:10:47.18#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.15:10:47.18#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.15:10:47.18#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:47.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:10:47.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:10:47.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:10:47.24#ibcon#enter wrdev, iclass 37, count 2 2006.285.15:10:47.24#ibcon#first serial, iclass 37, count 2 2006.285.15:10:47.24#ibcon#enter sib2, iclass 37, count 2 2006.285.15:10:47.24#ibcon#flushed, iclass 37, count 2 2006.285.15:10:47.24#ibcon#about to write, iclass 37, count 2 2006.285.15:10:47.24#ibcon#wrote, iclass 37, count 2 2006.285.15:10:47.24#ibcon#about to read 3, iclass 37, count 2 2006.285.15:10:47.26#ibcon#read 3, iclass 37, count 2 2006.285.15:10:47.26#ibcon#about to read 4, iclass 37, count 2 2006.285.15:10:47.26#ibcon#read 4, iclass 37, count 2 2006.285.15:10:47.26#ibcon#about to read 5, iclass 37, count 2 2006.285.15:10:47.26#ibcon#read 5, iclass 37, count 2 2006.285.15:10:47.26#ibcon#about to read 6, iclass 37, count 2 2006.285.15:10:47.26#ibcon#read 6, iclass 37, count 2 2006.285.15:10:47.26#ibcon#end of sib2, iclass 37, count 2 2006.285.15:10:47.26#ibcon#*mode == 0, iclass 37, count 2 2006.285.15:10:47.26#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.15:10:47.26#ibcon#[25=AT04-06\r\n] 2006.285.15:10:47.26#ibcon#*before write, iclass 37, count 2 2006.285.15:10:47.26#ibcon#enter sib2, iclass 37, count 2 2006.285.15:10:47.26#ibcon#flushed, iclass 37, count 2 2006.285.15:10:47.26#ibcon#about to write, iclass 37, count 2 2006.285.15:10:47.26#ibcon#wrote, iclass 37, count 2 2006.285.15:10:47.26#ibcon#about to read 3, iclass 37, count 2 2006.285.15:10:47.29#ibcon#read 3, iclass 37, count 2 2006.285.15:10:47.29#ibcon#about to read 4, iclass 37, count 2 2006.285.15:10:47.29#ibcon#read 4, iclass 37, count 2 2006.285.15:10:47.29#ibcon#about to read 5, iclass 37, count 2 2006.285.15:10:47.29#ibcon#read 5, iclass 37, count 2 2006.285.15:10:47.29#ibcon#about to read 6, iclass 37, count 2 2006.285.15:10:47.29#ibcon#read 6, iclass 37, count 2 2006.285.15:10:47.29#ibcon#end of sib2, iclass 37, count 2 2006.285.15:10:47.29#ibcon#*after write, iclass 37, count 2 2006.285.15:10:47.29#ibcon#*before return 0, iclass 37, count 2 2006.285.15:10:47.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:10:47.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:10:47.29#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.15:10:47.29#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:47.29#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:10:47.41#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:10:47.41#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:10:47.41#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:10:47.41#ibcon#first serial, iclass 37, count 0 2006.285.15:10:47.41#ibcon#enter sib2, iclass 37, count 0 2006.285.15:10:47.41#ibcon#flushed, iclass 37, count 0 2006.285.15:10:47.41#ibcon#about to write, iclass 37, count 0 2006.285.15:10:47.41#ibcon#wrote, iclass 37, count 0 2006.285.15:10:47.41#ibcon#about to read 3, iclass 37, count 0 2006.285.15:10:47.43#ibcon#read 3, iclass 37, count 0 2006.285.15:10:47.43#ibcon#about to read 4, iclass 37, count 0 2006.285.15:10:47.43#ibcon#read 4, iclass 37, count 0 2006.285.15:10:47.43#ibcon#about to read 5, iclass 37, count 0 2006.285.15:10:47.43#ibcon#read 5, iclass 37, count 0 2006.285.15:10:47.43#ibcon#about to read 6, iclass 37, count 0 2006.285.15:10:47.43#ibcon#read 6, iclass 37, count 0 2006.285.15:10:47.43#ibcon#end of sib2, iclass 37, count 0 2006.285.15:10:47.43#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:10:47.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:10:47.43#ibcon#[25=USB\r\n] 2006.285.15:10:47.43#ibcon#*before write, iclass 37, count 0 2006.285.15:10:47.43#ibcon#enter sib2, iclass 37, count 0 2006.285.15:10:47.43#ibcon#flushed, iclass 37, count 0 2006.285.15:10:47.43#ibcon#about to write, iclass 37, count 0 2006.285.15:10:47.43#ibcon#wrote, iclass 37, count 0 2006.285.15:10:47.43#ibcon#about to read 3, iclass 37, count 0 2006.285.15:10:47.46#ibcon#read 3, iclass 37, count 0 2006.285.15:10:47.46#ibcon#about to read 4, iclass 37, count 0 2006.285.15:10:47.46#ibcon#read 4, iclass 37, count 0 2006.285.15:10:47.46#ibcon#about to read 5, iclass 37, count 0 2006.285.15:10:47.46#ibcon#read 5, iclass 37, count 0 2006.285.15:10:47.46#ibcon#about to read 6, iclass 37, count 0 2006.285.15:10:47.46#ibcon#read 6, iclass 37, count 0 2006.285.15:10:47.46#ibcon#end of sib2, iclass 37, count 0 2006.285.15:10:47.46#ibcon#*after write, iclass 37, count 0 2006.285.15:10:47.46#ibcon#*before return 0, iclass 37, count 0 2006.285.15:10:47.46#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:10:47.46#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:10:47.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:10:47.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:10:47.46$vck44/valo=5,734.99 2006.285.15:10:47.46#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.15:10:47.46#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.15:10:47.46#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:47.46#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:10:47.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:10:47.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:10:47.46#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:10:47.46#ibcon#first serial, iclass 39, count 0 2006.285.15:10:47.46#ibcon#enter sib2, iclass 39, count 0 2006.285.15:10:47.46#ibcon#flushed, iclass 39, count 0 2006.285.15:10:47.46#ibcon#about to write, iclass 39, count 0 2006.285.15:10:47.46#ibcon#wrote, iclass 39, count 0 2006.285.15:10:47.46#ibcon#about to read 3, iclass 39, count 0 2006.285.15:10:47.48#ibcon#read 3, iclass 39, count 0 2006.285.15:10:47.48#ibcon#about to read 4, iclass 39, count 0 2006.285.15:10:47.48#ibcon#read 4, iclass 39, count 0 2006.285.15:10:47.48#ibcon#about to read 5, iclass 39, count 0 2006.285.15:10:47.48#ibcon#read 5, iclass 39, count 0 2006.285.15:10:47.48#ibcon#about to read 6, iclass 39, count 0 2006.285.15:10:47.48#ibcon#read 6, iclass 39, count 0 2006.285.15:10:47.48#ibcon#end of sib2, iclass 39, count 0 2006.285.15:10:47.48#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:10:47.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:10:47.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.15:10:47.48#ibcon#*before write, iclass 39, count 0 2006.285.15:10:47.48#ibcon#enter sib2, iclass 39, count 0 2006.285.15:10:47.48#ibcon#flushed, iclass 39, count 0 2006.285.15:10:47.48#ibcon#about to write, iclass 39, count 0 2006.285.15:10:47.48#ibcon#wrote, iclass 39, count 0 2006.285.15:10:47.48#ibcon#about to read 3, iclass 39, count 0 2006.285.15:10:47.52#ibcon#read 3, iclass 39, count 0 2006.285.15:10:47.52#ibcon#about to read 4, iclass 39, count 0 2006.285.15:10:47.52#ibcon#read 4, iclass 39, count 0 2006.285.15:10:47.52#ibcon#about to read 5, iclass 39, count 0 2006.285.15:10:47.52#ibcon#read 5, iclass 39, count 0 2006.285.15:10:47.52#ibcon#about to read 6, iclass 39, count 0 2006.285.15:10:47.52#ibcon#read 6, iclass 39, count 0 2006.285.15:10:47.52#ibcon#end of sib2, iclass 39, count 0 2006.285.15:10:47.52#ibcon#*after write, iclass 39, count 0 2006.285.15:10:47.52#ibcon#*before return 0, iclass 39, count 0 2006.285.15:10:47.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:10:47.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:10:47.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:10:47.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:10:47.52$vck44/va=5,3 2006.285.15:10:47.52#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.15:10:47.52#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.15:10:47.52#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:47.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:10:47.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:10:47.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:10:47.58#ibcon#enter wrdev, iclass 3, count 2 2006.285.15:10:47.58#ibcon#first serial, iclass 3, count 2 2006.285.15:10:47.58#ibcon#enter sib2, iclass 3, count 2 2006.285.15:10:47.58#ibcon#flushed, iclass 3, count 2 2006.285.15:10:47.58#ibcon#about to write, iclass 3, count 2 2006.285.15:10:47.58#ibcon#wrote, iclass 3, count 2 2006.285.15:10:47.58#ibcon#about to read 3, iclass 3, count 2 2006.285.15:10:47.60#ibcon#read 3, iclass 3, count 2 2006.285.15:10:47.60#ibcon#about to read 4, iclass 3, count 2 2006.285.15:10:47.60#ibcon#read 4, iclass 3, count 2 2006.285.15:10:47.60#ibcon#about to read 5, iclass 3, count 2 2006.285.15:10:47.60#ibcon#read 5, iclass 3, count 2 2006.285.15:10:47.60#ibcon#about to read 6, iclass 3, count 2 2006.285.15:10:47.60#ibcon#read 6, iclass 3, count 2 2006.285.15:10:47.60#ibcon#end of sib2, iclass 3, count 2 2006.285.15:10:47.60#ibcon#*mode == 0, iclass 3, count 2 2006.285.15:10:47.60#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.15:10:47.60#ibcon#[25=AT05-03\r\n] 2006.285.15:10:47.60#ibcon#*before write, iclass 3, count 2 2006.285.15:10:47.60#ibcon#enter sib2, iclass 3, count 2 2006.285.15:10:47.60#ibcon#flushed, iclass 3, count 2 2006.285.15:10:47.60#ibcon#about to write, iclass 3, count 2 2006.285.15:10:47.60#ibcon#wrote, iclass 3, count 2 2006.285.15:10:47.60#ibcon#about to read 3, iclass 3, count 2 2006.285.15:10:47.63#ibcon#read 3, iclass 3, count 2 2006.285.15:10:47.63#ibcon#about to read 4, iclass 3, count 2 2006.285.15:10:47.63#ibcon#read 4, iclass 3, count 2 2006.285.15:10:47.63#ibcon#about to read 5, iclass 3, count 2 2006.285.15:10:47.63#ibcon#read 5, iclass 3, count 2 2006.285.15:10:47.63#ibcon#about to read 6, iclass 3, count 2 2006.285.15:10:47.63#ibcon#read 6, iclass 3, count 2 2006.285.15:10:47.63#ibcon#end of sib2, iclass 3, count 2 2006.285.15:10:47.63#ibcon#*after write, iclass 3, count 2 2006.285.15:10:47.63#ibcon#*before return 0, iclass 3, count 2 2006.285.15:10:47.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:10:47.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:10:47.63#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.15:10:47.63#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:47.63#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:10:47.75#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:10:47.75#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:10:47.75#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:10:47.75#ibcon#first serial, iclass 3, count 0 2006.285.15:10:47.75#ibcon#enter sib2, iclass 3, count 0 2006.285.15:10:47.75#ibcon#flushed, iclass 3, count 0 2006.285.15:10:47.75#ibcon#about to write, iclass 3, count 0 2006.285.15:10:47.75#ibcon#wrote, iclass 3, count 0 2006.285.15:10:47.75#ibcon#about to read 3, iclass 3, count 0 2006.285.15:10:47.77#ibcon#read 3, iclass 3, count 0 2006.285.15:10:47.77#ibcon#about to read 4, iclass 3, count 0 2006.285.15:10:47.77#ibcon#read 4, iclass 3, count 0 2006.285.15:10:47.77#ibcon#about to read 5, iclass 3, count 0 2006.285.15:10:47.77#ibcon#read 5, iclass 3, count 0 2006.285.15:10:47.77#ibcon#about to read 6, iclass 3, count 0 2006.285.15:10:47.77#ibcon#read 6, iclass 3, count 0 2006.285.15:10:47.77#ibcon#end of sib2, iclass 3, count 0 2006.285.15:10:47.77#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:10:47.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:10:47.77#ibcon#[25=USB\r\n] 2006.285.15:10:47.77#ibcon#*before write, iclass 3, count 0 2006.285.15:10:47.77#ibcon#enter sib2, iclass 3, count 0 2006.285.15:10:47.77#ibcon#flushed, iclass 3, count 0 2006.285.15:10:47.77#ibcon#about to write, iclass 3, count 0 2006.285.15:10:47.77#ibcon#wrote, iclass 3, count 0 2006.285.15:10:47.77#ibcon#about to read 3, iclass 3, count 0 2006.285.15:10:47.80#ibcon#read 3, iclass 3, count 0 2006.285.15:10:47.80#ibcon#about to read 4, iclass 3, count 0 2006.285.15:10:47.80#ibcon#read 4, iclass 3, count 0 2006.285.15:10:47.80#ibcon#about to read 5, iclass 3, count 0 2006.285.15:10:47.80#ibcon#read 5, iclass 3, count 0 2006.285.15:10:47.80#ibcon#about to read 6, iclass 3, count 0 2006.285.15:10:47.80#ibcon#read 6, iclass 3, count 0 2006.285.15:10:47.80#ibcon#end of sib2, iclass 3, count 0 2006.285.15:10:47.80#ibcon#*after write, iclass 3, count 0 2006.285.15:10:47.80#ibcon#*before return 0, iclass 3, count 0 2006.285.15:10:47.80#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:10:47.80#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:10:47.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:10:47.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:10:47.80$vck44/valo=6,814.99 2006.285.15:10:47.80#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.15:10:47.80#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.15:10:47.80#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:47.80#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:10:47.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:10:47.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:10:47.80#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:10:47.80#ibcon#first serial, iclass 5, count 0 2006.285.15:10:47.80#ibcon#enter sib2, iclass 5, count 0 2006.285.15:10:47.80#ibcon#flushed, iclass 5, count 0 2006.285.15:10:47.80#ibcon#about to write, iclass 5, count 0 2006.285.15:10:47.80#ibcon#wrote, iclass 5, count 0 2006.285.15:10:47.80#ibcon#about to read 3, iclass 5, count 0 2006.285.15:10:47.82#ibcon#read 3, iclass 5, count 0 2006.285.15:10:47.82#ibcon#about to read 4, iclass 5, count 0 2006.285.15:10:47.82#ibcon#read 4, iclass 5, count 0 2006.285.15:10:47.82#ibcon#about to read 5, iclass 5, count 0 2006.285.15:10:47.82#ibcon#read 5, iclass 5, count 0 2006.285.15:10:47.82#ibcon#about to read 6, iclass 5, count 0 2006.285.15:10:47.82#ibcon#read 6, iclass 5, count 0 2006.285.15:10:47.82#ibcon#end of sib2, iclass 5, count 0 2006.285.15:10:47.82#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:10:47.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:10:47.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.15:10:47.82#ibcon#*before write, iclass 5, count 0 2006.285.15:10:47.82#ibcon#enter sib2, iclass 5, count 0 2006.285.15:10:47.82#ibcon#flushed, iclass 5, count 0 2006.285.15:10:47.82#ibcon#about to write, iclass 5, count 0 2006.285.15:10:47.82#ibcon#wrote, iclass 5, count 0 2006.285.15:10:47.82#ibcon#about to read 3, iclass 5, count 0 2006.285.15:10:47.86#ibcon#read 3, iclass 5, count 0 2006.285.15:10:47.86#ibcon#about to read 4, iclass 5, count 0 2006.285.15:10:47.86#ibcon#read 4, iclass 5, count 0 2006.285.15:10:47.86#ibcon#about to read 5, iclass 5, count 0 2006.285.15:10:47.86#ibcon#read 5, iclass 5, count 0 2006.285.15:10:47.86#ibcon#about to read 6, iclass 5, count 0 2006.285.15:10:47.86#ibcon#read 6, iclass 5, count 0 2006.285.15:10:47.86#ibcon#end of sib2, iclass 5, count 0 2006.285.15:10:47.86#ibcon#*after write, iclass 5, count 0 2006.285.15:10:47.86#ibcon#*before return 0, iclass 5, count 0 2006.285.15:10:47.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:10:47.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:10:47.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:10:47.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:10:47.86$vck44/va=6,4 2006.285.15:10:47.86#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.15:10:47.86#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.15:10:47.86#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:47.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:10:47.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:10:47.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:10:47.92#ibcon#enter wrdev, iclass 7, count 2 2006.285.15:10:47.92#ibcon#first serial, iclass 7, count 2 2006.285.15:10:47.92#ibcon#enter sib2, iclass 7, count 2 2006.285.15:10:47.92#ibcon#flushed, iclass 7, count 2 2006.285.15:10:47.92#ibcon#about to write, iclass 7, count 2 2006.285.15:10:47.92#ibcon#wrote, iclass 7, count 2 2006.285.15:10:47.92#ibcon#about to read 3, iclass 7, count 2 2006.285.15:10:47.94#ibcon#read 3, iclass 7, count 2 2006.285.15:10:47.94#ibcon#about to read 4, iclass 7, count 2 2006.285.15:10:47.94#ibcon#read 4, iclass 7, count 2 2006.285.15:10:47.94#ibcon#about to read 5, iclass 7, count 2 2006.285.15:10:47.94#ibcon#read 5, iclass 7, count 2 2006.285.15:10:47.94#ibcon#about to read 6, iclass 7, count 2 2006.285.15:10:47.94#ibcon#read 6, iclass 7, count 2 2006.285.15:10:47.94#ibcon#end of sib2, iclass 7, count 2 2006.285.15:10:47.94#ibcon#*mode == 0, iclass 7, count 2 2006.285.15:10:47.94#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.15:10:47.94#ibcon#[25=AT06-04\r\n] 2006.285.15:10:47.94#ibcon#*before write, iclass 7, count 2 2006.285.15:10:47.94#ibcon#enter sib2, iclass 7, count 2 2006.285.15:10:47.94#ibcon#flushed, iclass 7, count 2 2006.285.15:10:47.94#ibcon#about to write, iclass 7, count 2 2006.285.15:10:47.94#ibcon#wrote, iclass 7, count 2 2006.285.15:10:47.94#ibcon#about to read 3, iclass 7, count 2 2006.285.15:10:47.97#ibcon#read 3, iclass 7, count 2 2006.285.15:10:47.97#ibcon#about to read 4, iclass 7, count 2 2006.285.15:10:47.97#ibcon#read 4, iclass 7, count 2 2006.285.15:10:47.97#ibcon#about to read 5, iclass 7, count 2 2006.285.15:10:47.97#ibcon#read 5, iclass 7, count 2 2006.285.15:10:47.97#ibcon#about to read 6, iclass 7, count 2 2006.285.15:10:47.97#ibcon#read 6, iclass 7, count 2 2006.285.15:10:47.97#ibcon#end of sib2, iclass 7, count 2 2006.285.15:10:47.97#ibcon#*after write, iclass 7, count 2 2006.285.15:10:47.97#ibcon#*before return 0, iclass 7, count 2 2006.285.15:10:47.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:10:47.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:10:47.97#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.15:10:47.97#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:47.97#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:10:48.09#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:10:48.25#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:10:48.25#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:10:48.25#ibcon#first serial, iclass 7, count 0 2006.285.15:10:48.25#ibcon#enter sib2, iclass 7, count 0 2006.285.15:10:48.25#ibcon#flushed, iclass 7, count 0 2006.285.15:10:48.25#ibcon#about to write, iclass 7, count 0 2006.285.15:10:48.25#ibcon#wrote, iclass 7, count 0 2006.285.15:10:48.25#ibcon#about to read 3, iclass 7, count 0 2006.285.15:10:48.27#ibcon#read 3, iclass 7, count 0 2006.285.15:10:48.27#ibcon#about to read 4, iclass 7, count 0 2006.285.15:10:48.27#ibcon#read 4, iclass 7, count 0 2006.285.15:10:48.27#ibcon#about to read 5, iclass 7, count 0 2006.285.15:10:48.27#ibcon#read 5, iclass 7, count 0 2006.285.15:10:48.27#ibcon#about to read 6, iclass 7, count 0 2006.285.15:10:48.27#ibcon#read 6, iclass 7, count 0 2006.285.15:10:48.27#ibcon#end of sib2, iclass 7, count 0 2006.285.15:10:48.27#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:10:48.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:10:48.27#ibcon#[25=USB\r\n] 2006.285.15:10:48.27#ibcon#*before write, iclass 7, count 0 2006.285.15:10:48.27#ibcon#enter sib2, iclass 7, count 0 2006.285.15:10:48.27#ibcon#flushed, iclass 7, count 0 2006.285.15:10:48.27#ibcon#about to write, iclass 7, count 0 2006.285.15:10:48.27#ibcon#wrote, iclass 7, count 0 2006.285.15:10:48.27#ibcon#about to read 3, iclass 7, count 0 2006.285.15:10:48.30#ibcon#read 3, iclass 7, count 0 2006.285.15:10:48.30#ibcon#about to read 4, iclass 7, count 0 2006.285.15:10:48.30#ibcon#read 4, iclass 7, count 0 2006.285.15:10:48.30#ibcon#about to read 5, iclass 7, count 0 2006.285.15:10:48.30#ibcon#read 5, iclass 7, count 0 2006.285.15:10:48.30#ibcon#about to read 6, iclass 7, count 0 2006.285.15:10:48.30#ibcon#read 6, iclass 7, count 0 2006.285.15:10:48.30#ibcon#end of sib2, iclass 7, count 0 2006.285.15:10:48.30#ibcon#*after write, iclass 7, count 0 2006.285.15:10:48.30#ibcon#*before return 0, iclass 7, count 0 2006.285.15:10:48.30#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:10:48.30#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:10:48.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:10:48.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:10:48.30$vck44/valo=7,864.99 2006.285.15:10:48.30#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.15:10:48.30#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.15:10:48.30#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:48.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:10:48.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:10:48.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:10:48.30#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:10:48.30#ibcon#first serial, iclass 11, count 0 2006.285.15:10:48.30#ibcon#enter sib2, iclass 11, count 0 2006.285.15:10:48.30#ibcon#flushed, iclass 11, count 0 2006.285.15:10:48.30#ibcon#about to write, iclass 11, count 0 2006.285.15:10:48.30#ibcon#wrote, iclass 11, count 0 2006.285.15:10:48.30#ibcon#about to read 3, iclass 11, count 0 2006.285.15:10:48.32#ibcon#read 3, iclass 11, count 0 2006.285.15:10:48.32#ibcon#about to read 4, iclass 11, count 0 2006.285.15:10:48.32#ibcon#read 4, iclass 11, count 0 2006.285.15:10:48.32#ibcon#about to read 5, iclass 11, count 0 2006.285.15:10:48.32#ibcon#read 5, iclass 11, count 0 2006.285.15:10:48.32#ibcon#about to read 6, iclass 11, count 0 2006.285.15:10:48.32#ibcon#read 6, iclass 11, count 0 2006.285.15:10:48.32#ibcon#end of sib2, iclass 11, count 0 2006.285.15:10:48.32#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:10:48.32#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:10:48.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.15:10:48.32#ibcon#*before write, iclass 11, count 0 2006.285.15:10:48.32#ibcon#enter sib2, iclass 11, count 0 2006.285.15:10:48.32#ibcon#flushed, iclass 11, count 0 2006.285.15:10:48.32#ibcon#about to write, iclass 11, count 0 2006.285.15:10:48.32#ibcon#wrote, iclass 11, count 0 2006.285.15:10:48.32#ibcon#about to read 3, iclass 11, count 0 2006.285.15:10:48.36#ibcon#read 3, iclass 11, count 0 2006.285.15:10:48.36#ibcon#about to read 4, iclass 11, count 0 2006.285.15:10:48.36#ibcon#read 4, iclass 11, count 0 2006.285.15:10:48.36#ibcon#about to read 5, iclass 11, count 0 2006.285.15:10:48.36#ibcon#read 5, iclass 11, count 0 2006.285.15:10:48.36#ibcon#about to read 6, iclass 11, count 0 2006.285.15:10:48.36#ibcon#read 6, iclass 11, count 0 2006.285.15:10:48.36#ibcon#end of sib2, iclass 11, count 0 2006.285.15:10:48.36#ibcon#*after write, iclass 11, count 0 2006.285.15:10:48.36#ibcon#*before return 0, iclass 11, count 0 2006.285.15:10:48.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:10:48.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:10:48.36#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:10:48.36#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:10:48.36$vck44/va=7,4 2006.285.15:10:48.36#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.15:10:48.36#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.15:10:48.36#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:48.36#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:10:48.42#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:10:48.42#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:10:48.42#ibcon#enter wrdev, iclass 13, count 2 2006.285.15:10:48.42#ibcon#first serial, iclass 13, count 2 2006.285.15:10:48.42#ibcon#enter sib2, iclass 13, count 2 2006.285.15:10:48.42#ibcon#flushed, iclass 13, count 2 2006.285.15:10:48.42#ibcon#about to write, iclass 13, count 2 2006.285.15:10:48.42#ibcon#wrote, iclass 13, count 2 2006.285.15:10:48.42#ibcon#about to read 3, iclass 13, count 2 2006.285.15:10:48.44#ibcon#read 3, iclass 13, count 2 2006.285.15:10:48.44#ibcon#about to read 4, iclass 13, count 2 2006.285.15:10:48.44#ibcon#read 4, iclass 13, count 2 2006.285.15:10:48.44#ibcon#about to read 5, iclass 13, count 2 2006.285.15:10:48.44#ibcon#read 5, iclass 13, count 2 2006.285.15:10:48.44#ibcon#about to read 6, iclass 13, count 2 2006.285.15:10:48.44#ibcon#read 6, iclass 13, count 2 2006.285.15:10:48.44#ibcon#end of sib2, iclass 13, count 2 2006.285.15:10:48.44#ibcon#*mode == 0, iclass 13, count 2 2006.285.15:10:48.44#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.15:10:48.44#ibcon#[25=AT07-04\r\n] 2006.285.15:10:48.44#ibcon#*before write, iclass 13, count 2 2006.285.15:10:48.44#ibcon#enter sib2, iclass 13, count 2 2006.285.15:10:48.44#ibcon#flushed, iclass 13, count 2 2006.285.15:10:48.44#ibcon#about to write, iclass 13, count 2 2006.285.15:10:48.44#ibcon#wrote, iclass 13, count 2 2006.285.15:10:48.44#ibcon#about to read 3, iclass 13, count 2 2006.285.15:10:48.47#ibcon#read 3, iclass 13, count 2 2006.285.15:10:48.47#ibcon#about to read 4, iclass 13, count 2 2006.285.15:10:48.47#ibcon#read 4, iclass 13, count 2 2006.285.15:10:48.47#ibcon#about to read 5, iclass 13, count 2 2006.285.15:10:48.47#ibcon#read 5, iclass 13, count 2 2006.285.15:10:48.47#ibcon#about to read 6, iclass 13, count 2 2006.285.15:10:48.47#ibcon#read 6, iclass 13, count 2 2006.285.15:10:48.47#ibcon#end of sib2, iclass 13, count 2 2006.285.15:10:48.47#ibcon#*after write, iclass 13, count 2 2006.285.15:10:48.47#ibcon#*before return 0, iclass 13, count 2 2006.285.15:10:48.47#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:10:48.47#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:10:48.47#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.15:10:48.47#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:48.47#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:10:48.59#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:10:48.59#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:10:48.59#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:10:48.59#ibcon#first serial, iclass 13, count 0 2006.285.15:10:48.59#ibcon#enter sib2, iclass 13, count 0 2006.285.15:10:48.59#ibcon#flushed, iclass 13, count 0 2006.285.15:10:48.59#ibcon#about to write, iclass 13, count 0 2006.285.15:10:48.59#ibcon#wrote, iclass 13, count 0 2006.285.15:10:48.59#ibcon#about to read 3, iclass 13, count 0 2006.285.15:10:48.61#ibcon#read 3, iclass 13, count 0 2006.285.15:10:48.61#ibcon#about to read 4, iclass 13, count 0 2006.285.15:10:48.61#ibcon#read 4, iclass 13, count 0 2006.285.15:10:48.61#ibcon#about to read 5, iclass 13, count 0 2006.285.15:10:48.61#ibcon#read 5, iclass 13, count 0 2006.285.15:10:48.61#ibcon#about to read 6, iclass 13, count 0 2006.285.15:10:48.61#ibcon#read 6, iclass 13, count 0 2006.285.15:10:48.61#ibcon#end of sib2, iclass 13, count 0 2006.285.15:10:48.61#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:10:48.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:10:48.61#ibcon#[25=USB\r\n] 2006.285.15:10:48.61#ibcon#*before write, iclass 13, count 0 2006.285.15:10:48.61#ibcon#enter sib2, iclass 13, count 0 2006.285.15:10:48.61#ibcon#flushed, iclass 13, count 0 2006.285.15:10:48.61#ibcon#about to write, iclass 13, count 0 2006.285.15:10:48.61#ibcon#wrote, iclass 13, count 0 2006.285.15:10:48.61#ibcon#about to read 3, iclass 13, count 0 2006.285.15:10:48.64#ibcon#read 3, iclass 13, count 0 2006.285.15:10:48.64#ibcon#about to read 4, iclass 13, count 0 2006.285.15:10:48.64#ibcon#read 4, iclass 13, count 0 2006.285.15:10:48.64#ibcon#about to read 5, iclass 13, count 0 2006.285.15:10:48.64#ibcon#read 5, iclass 13, count 0 2006.285.15:10:48.64#ibcon#about to read 6, iclass 13, count 0 2006.285.15:10:48.64#ibcon#read 6, iclass 13, count 0 2006.285.15:10:48.64#ibcon#end of sib2, iclass 13, count 0 2006.285.15:10:48.64#ibcon#*after write, iclass 13, count 0 2006.285.15:10:48.64#ibcon#*before return 0, iclass 13, count 0 2006.285.15:10:48.64#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:10:48.64#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:10:48.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:10:48.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:10:48.64$vck44/valo=8,884.99 2006.285.15:10:48.64#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.15:10:48.64#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.15:10:48.64#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:48.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:10:48.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:10:48.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:10:48.64#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:10:48.64#ibcon#first serial, iclass 15, count 0 2006.285.15:10:48.64#ibcon#enter sib2, iclass 15, count 0 2006.285.15:10:48.64#ibcon#flushed, iclass 15, count 0 2006.285.15:10:48.64#ibcon#about to write, iclass 15, count 0 2006.285.15:10:48.64#ibcon#wrote, iclass 15, count 0 2006.285.15:10:48.64#ibcon#about to read 3, iclass 15, count 0 2006.285.15:10:48.66#ibcon#read 3, iclass 15, count 0 2006.285.15:10:48.66#ibcon#about to read 4, iclass 15, count 0 2006.285.15:10:48.66#ibcon#read 4, iclass 15, count 0 2006.285.15:10:48.66#ibcon#about to read 5, iclass 15, count 0 2006.285.15:10:48.66#ibcon#read 5, iclass 15, count 0 2006.285.15:10:48.66#ibcon#about to read 6, iclass 15, count 0 2006.285.15:10:48.66#ibcon#read 6, iclass 15, count 0 2006.285.15:10:48.66#ibcon#end of sib2, iclass 15, count 0 2006.285.15:10:48.66#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:10:48.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:10:48.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.15:10:48.66#ibcon#*before write, iclass 15, count 0 2006.285.15:10:48.66#ibcon#enter sib2, iclass 15, count 0 2006.285.15:10:48.66#ibcon#flushed, iclass 15, count 0 2006.285.15:10:48.66#ibcon#about to write, iclass 15, count 0 2006.285.15:10:48.66#ibcon#wrote, iclass 15, count 0 2006.285.15:10:48.66#ibcon#about to read 3, iclass 15, count 0 2006.285.15:10:48.70#ibcon#read 3, iclass 15, count 0 2006.285.15:10:48.70#ibcon#about to read 4, iclass 15, count 0 2006.285.15:10:48.70#ibcon#read 4, iclass 15, count 0 2006.285.15:10:48.70#ibcon#about to read 5, iclass 15, count 0 2006.285.15:10:48.70#ibcon#read 5, iclass 15, count 0 2006.285.15:10:48.70#ibcon#about to read 6, iclass 15, count 0 2006.285.15:10:48.70#ibcon#read 6, iclass 15, count 0 2006.285.15:10:48.70#ibcon#end of sib2, iclass 15, count 0 2006.285.15:10:48.70#ibcon#*after write, iclass 15, count 0 2006.285.15:10:48.70#ibcon#*before return 0, iclass 15, count 0 2006.285.15:10:48.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:10:48.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:10:48.70#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:10:48.70#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:10:48.70$vck44/va=8,3 2006.285.15:10:48.70#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.15:10:48.70#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.15:10:48.70#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:48.70#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:10:48.76#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:10:48.76#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:10:48.76#ibcon#enter wrdev, iclass 17, count 2 2006.285.15:10:48.76#ibcon#first serial, iclass 17, count 2 2006.285.15:10:48.76#ibcon#enter sib2, iclass 17, count 2 2006.285.15:10:48.76#ibcon#flushed, iclass 17, count 2 2006.285.15:10:48.76#ibcon#about to write, iclass 17, count 2 2006.285.15:10:48.76#ibcon#wrote, iclass 17, count 2 2006.285.15:10:48.76#ibcon#about to read 3, iclass 17, count 2 2006.285.15:10:48.78#ibcon#read 3, iclass 17, count 2 2006.285.15:10:48.78#ibcon#about to read 4, iclass 17, count 2 2006.285.15:10:48.78#ibcon#read 4, iclass 17, count 2 2006.285.15:10:48.78#ibcon#about to read 5, iclass 17, count 2 2006.285.15:10:48.78#ibcon#read 5, iclass 17, count 2 2006.285.15:10:48.78#ibcon#about to read 6, iclass 17, count 2 2006.285.15:10:48.78#ibcon#read 6, iclass 17, count 2 2006.285.15:10:48.78#ibcon#end of sib2, iclass 17, count 2 2006.285.15:10:48.78#ibcon#*mode == 0, iclass 17, count 2 2006.285.15:10:48.78#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.15:10:48.78#ibcon#[25=AT08-03\r\n] 2006.285.15:10:48.78#ibcon#*before write, iclass 17, count 2 2006.285.15:10:48.78#ibcon#enter sib2, iclass 17, count 2 2006.285.15:10:48.78#ibcon#flushed, iclass 17, count 2 2006.285.15:10:48.78#ibcon#about to write, iclass 17, count 2 2006.285.15:10:48.78#ibcon#wrote, iclass 17, count 2 2006.285.15:10:48.78#ibcon#about to read 3, iclass 17, count 2 2006.285.15:10:48.81#ibcon#read 3, iclass 17, count 2 2006.285.15:10:48.81#ibcon#about to read 4, iclass 17, count 2 2006.285.15:10:48.81#ibcon#read 4, iclass 17, count 2 2006.285.15:10:48.81#ibcon#about to read 5, iclass 17, count 2 2006.285.15:10:48.81#ibcon#read 5, iclass 17, count 2 2006.285.15:10:48.81#ibcon#about to read 6, iclass 17, count 2 2006.285.15:10:48.81#ibcon#read 6, iclass 17, count 2 2006.285.15:10:48.81#ibcon#end of sib2, iclass 17, count 2 2006.285.15:10:48.81#ibcon#*after write, iclass 17, count 2 2006.285.15:10:48.81#ibcon#*before return 0, iclass 17, count 2 2006.285.15:10:48.81#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:10:48.81#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:10:48.81#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.15:10:48.81#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:48.81#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:10:48.93#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:10:48.93#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:10:48.93#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:10:48.93#ibcon#first serial, iclass 17, count 0 2006.285.15:10:48.93#ibcon#enter sib2, iclass 17, count 0 2006.285.15:10:48.93#ibcon#flushed, iclass 17, count 0 2006.285.15:10:48.93#ibcon#about to write, iclass 17, count 0 2006.285.15:10:48.93#ibcon#wrote, iclass 17, count 0 2006.285.15:10:48.93#ibcon#about to read 3, iclass 17, count 0 2006.285.15:10:48.95#ibcon#read 3, iclass 17, count 0 2006.285.15:10:48.95#ibcon#about to read 4, iclass 17, count 0 2006.285.15:10:48.95#ibcon#read 4, iclass 17, count 0 2006.285.15:10:48.95#ibcon#about to read 5, iclass 17, count 0 2006.285.15:10:48.95#ibcon#read 5, iclass 17, count 0 2006.285.15:10:48.95#ibcon#about to read 6, iclass 17, count 0 2006.285.15:10:48.95#ibcon#read 6, iclass 17, count 0 2006.285.15:10:48.95#ibcon#end of sib2, iclass 17, count 0 2006.285.15:10:48.95#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:10:48.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:10:48.95#ibcon#[25=USB\r\n] 2006.285.15:10:48.95#ibcon#*before write, iclass 17, count 0 2006.285.15:10:48.95#ibcon#enter sib2, iclass 17, count 0 2006.285.15:10:48.95#ibcon#flushed, iclass 17, count 0 2006.285.15:10:48.95#ibcon#about to write, iclass 17, count 0 2006.285.15:10:48.95#ibcon#wrote, iclass 17, count 0 2006.285.15:10:48.95#ibcon#about to read 3, iclass 17, count 0 2006.285.15:10:48.98#ibcon#read 3, iclass 17, count 0 2006.285.15:10:48.98#ibcon#about to read 4, iclass 17, count 0 2006.285.15:10:48.98#ibcon#read 4, iclass 17, count 0 2006.285.15:10:48.98#ibcon#about to read 5, iclass 17, count 0 2006.285.15:10:48.98#ibcon#read 5, iclass 17, count 0 2006.285.15:10:48.98#ibcon#about to read 6, iclass 17, count 0 2006.285.15:10:48.98#ibcon#read 6, iclass 17, count 0 2006.285.15:10:48.98#ibcon#end of sib2, iclass 17, count 0 2006.285.15:10:48.98#ibcon#*after write, iclass 17, count 0 2006.285.15:10:48.98#ibcon#*before return 0, iclass 17, count 0 2006.285.15:10:48.98#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:10:48.98#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:10:48.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:10:48.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:10:48.98$vck44/vblo=1,629.99 2006.285.15:10:48.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.15:10:48.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.15:10:48.98#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:48.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:10:48.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:10:48.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:10:48.98#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:10:48.98#ibcon#first serial, iclass 19, count 0 2006.285.15:10:48.98#ibcon#enter sib2, iclass 19, count 0 2006.285.15:10:48.98#ibcon#flushed, iclass 19, count 0 2006.285.15:10:48.98#ibcon#about to write, iclass 19, count 0 2006.285.15:10:48.98#ibcon#wrote, iclass 19, count 0 2006.285.15:10:48.98#ibcon#about to read 3, iclass 19, count 0 2006.285.15:10:49.00#ibcon#read 3, iclass 19, count 0 2006.285.15:10:49.06#ibcon#about to read 4, iclass 19, count 0 2006.285.15:10:49.06#ibcon#read 4, iclass 19, count 0 2006.285.15:10:49.06#ibcon#about to read 5, iclass 19, count 0 2006.285.15:10:49.06#ibcon#read 5, iclass 19, count 0 2006.285.15:10:49.06#ibcon#about to read 6, iclass 19, count 0 2006.285.15:10:49.06#ibcon#read 6, iclass 19, count 0 2006.285.15:10:49.06#ibcon#end of sib2, iclass 19, count 0 2006.285.15:10:49.06#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:10:49.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:10:49.06#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.15:10:49.06#ibcon#*before write, iclass 19, count 0 2006.285.15:10:49.06#ibcon#enter sib2, iclass 19, count 0 2006.285.15:10:49.06#ibcon#flushed, iclass 19, count 0 2006.285.15:10:49.06#ibcon#about to write, iclass 19, count 0 2006.285.15:10:49.06#ibcon#wrote, iclass 19, count 0 2006.285.15:10:49.06#ibcon#about to read 3, iclass 19, count 0 2006.285.15:10:49.10#ibcon#read 3, iclass 19, count 0 2006.285.15:10:49.10#ibcon#about to read 4, iclass 19, count 0 2006.285.15:10:49.10#ibcon#read 4, iclass 19, count 0 2006.285.15:10:49.10#ibcon#about to read 5, iclass 19, count 0 2006.285.15:10:49.10#ibcon#read 5, iclass 19, count 0 2006.285.15:10:49.10#ibcon#about to read 6, iclass 19, count 0 2006.285.15:10:49.10#ibcon#read 6, iclass 19, count 0 2006.285.15:10:49.10#ibcon#end of sib2, iclass 19, count 0 2006.285.15:10:49.10#ibcon#*after write, iclass 19, count 0 2006.285.15:10:49.10#ibcon#*before return 0, iclass 19, count 0 2006.285.15:10:49.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:10:49.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:10:49.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:10:49.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:10:49.10$vck44/vb=1,4 2006.285.15:10:49.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.15:10:49.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.15:10:49.10#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:49.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:10:49.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:10:49.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:10:49.10#ibcon#enter wrdev, iclass 21, count 2 2006.285.15:10:49.10#ibcon#first serial, iclass 21, count 2 2006.285.15:10:49.10#ibcon#enter sib2, iclass 21, count 2 2006.285.15:10:49.10#ibcon#flushed, iclass 21, count 2 2006.285.15:10:49.10#ibcon#about to write, iclass 21, count 2 2006.285.15:10:49.10#ibcon#wrote, iclass 21, count 2 2006.285.15:10:49.10#ibcon#about to read 3, iclass 21, count 2 2006.285.15:10:49.12#ibcon#read 3, iclass 21, count 2 2006.285.15:10:49.12#ibcon#about to read 4, iclass 21, count 2 2006.285.15:10:49.12#ibcon#read 4, iclass 21, count 2 2006.285.15:10:49.12#ibcon#about to read 5, iclass 21, count 2 2006.285.15:10:49.12#ibcon#read 5, iclass 21, count 2 2006.285.15:10:49.12#ibcon#about to read 6, iclass 21, count 2 2006.285.15:10:49.12#ibcon#read 6, iclass 21, count 2 2006.285.15:10:49.12#ibcon#end of sib2, iclass 21, count 2 2006.285.15:10:49.12#ibcon#*mode == 0, iclass 21, count 2 2006.285.15:10:49.12#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.15:10:49.12#ibcon#[27=AT01-04\r\n] 2006.285.15:10:49.12#ibcon#*before write, iclass 21, count 2 2006.285.15:10:49.12#ibcon#enter sib2, iclass 21, count 2 2006.285.15:10:49.12#ibcon#flushed, iclass 21, count 2 2006.285.15:10:49.12#ibcon#about to write, iclass 21, count 2 2006.285.15:10:49.12#ibcon#wrote, iclass 21, count 2 2006.285.15:10:49.12#ibcon#about to read 3, iclass 21, count 2 2006.285.15:10:49.15#ibcon#read 3, iclass 21, count 2 2006.285.15:10:49.15#ibcon#about to read 4, iclass 21, count 2 2006.285.15:10:49.15#ibcon#read 4, iclass 21, count 2 2006.285.15:10:49.15#ibcon#about to read 5, iclass 21, count 2 2006.285.15:10:49.15#ibcon#read 5, iclass 21, count 2 2006.285.15:10:49.15#ibcon#about to read 6, iclass 21, count 2 2006.285.15:10:49.15#ibcon#read 6, iclass 21, count 2 2006.285.15:10:49.15#ibcon#end of sib2, iclass 21, count 2 2006.285.15:10:49.15#ibcon#*after write, iclass 21, count 2 2006.285.15:10:49.15#ibcon#*before return 0, iclass 21, count 2 2006.285.15:10:49.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:10:49.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:10:49.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.15:10:49.15#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:49.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:10:49.27#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:10:49.27#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:10:49.27#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:10:49.27#ibcon#first serial, iclass 21, count 0 2006.285.15:10:49.27#ibcon#enter sib2, iclass 21, count 0 2006.285.15:10:49.27#ibcon#flushed, iclass 21, count 0 2006.285.15:10:49.27#ibcon#about to write, iclass 21, count 0 2006.285.15:10:49.27#ibcon#wrote, iclass 21, count 0 2006.285.15:10:49.27#ibcon#about to read 3, iclass 21, count 0 2006.285.15:10:49.29#ibcon#read 3, iclass 21, count 0 2006.285.15:10:49.29#ibcon#about to read 4, iclass 21, count 0 2006.285.15:10:49.29#ibcon#read 4, iclass 21, count 0 2006.285.15:10:49.29#ibcon#about to read 5, iclass 21, count 0 2006.285.15:10:49.29#ibcon#read 5, iclass 21, count 0 2006.285.15:10:49.29#ibcon#about to read 6, iclass 21, count 0 2006.285.15:10:49.29#ibcon#read 6, iclass 21, count 0 2006.285.15:10:49.29#ibcon#end of sib2, iclass 21, count 0 2006.285.15:10:49.29#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:10:49.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:10:49.29#ibcon#[27=USB\r\n] 2006.285.15:10:49.29#ibcon#*before write, iclass 21, count 0 2006.285.15:10:49.29#ibcon#enter sib2, iclass 21, count 0 2006.285.15:10:49.29#ibcon#flushed, iclass 21, count 0 2006.285.15:10:49.29#ibcon#about to write, iclass 21, count 0 2006.285.15:10:49.29#ibcon#wrote, iclass 21, count 0 2006.285.15:10:49.29#ibcon#about to read 3, iclass 21, count 0 2006.285.15:10:49.32#ibcon#read 3, iclass 21, count 0 2006.285.15:10:49.32#ibcon#about to read 4, iclass 21, count 0 2006.285.15:10:49.32#ibcon#read 4, iclass 21, count 0 2006.285.15:10:49.32#ibcon#about to read 5, iclass 21, count 0 2006.285.15:10:49.32#ibcon#read 5, iclass 21, count 0 2006.285.15:10:49.32#ibcon#about to read 6, iclass 21, count 0 2006.285.15:10:49.32#ibcon#read 6, iclass 21, count 0 2006.285.15:10:49.32#ibcon#end of sib2, iclass 21, count 0 2006.285.15:10:49.32#ibcon#*after write, iclass 21, count 0 2006.285.15:10:49.32#ibcon#*before return 0, iclass 21, count 0 2006.285.15:10:49.32#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:10:49.32#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:10:49.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:10:49.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:10:49.32$vck44/vblo=2,634.99 2006.285.15:10:49.32#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.15:10:49.32#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.15:10:49.32#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:49.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:10:49.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:10:49.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:10:49.32#ibcon#enter wrdev, iclass 23, count 0 2006.285.15:10:49.32#ibcon#first serial, iclass 23, count 0 2006.285.15:10:49.32#ibcon#enter sib2, iclass 23, count 0 2006.285.15:10:49.32#ibcon#flushed, iclass 23, count 0 2006.285.15:10:49.32#ibcon#about to write, iclass 23, count 0 2006.285.15:10:49.32#ibcon#wrote, iclass 23, count 0 2006.285.15:10:49.32#ibcon#about to read 3, iclass 23, count 0 2006.285.15:10:49.34#ibcon#read 3, iclass 23, count 0 2006.285.15:10:49.34#ibcon#about to read 4, iclass 23, count 0 2006.285.15:10:49.34#ibcon#read 4, iclass 23, count 0 2006.285.15:10:49.34#ibcon#about to read 5, iclass 23, count 0 2006.285.15:10:49.34#ibcon#read 5, iclass 23, count 0 2006.285.15:10:49.34#ibcon#about to read 6, iclass 23, count 0 2006.285.15:10:49.34#ibcon#read 6, iclass 23, count 0 2006.285.15:10:49.34#ibcon#end of sib2, iclass 23, count 0 2006.285.15:10:49.34#ibcon#*mode == 0, iclass 23, count 0 2006.285.15:10:49.34#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.15:10:49.34#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.15:10:49.34#ibcon#*before write, iclass 23, count 0 2006.285.15:10:49.34#ibcon#enter sib2, iclass 23, count 0 2006.285.15:10:49.34#ibcon#flushed, iclass 23, count 0 2006.285.15:10:49.34#ibcon#about to write, iclass 23, count 0 2006.285.15:10:49.34#ibcon#wrote, iclass 23, count 0 2006.285.15:10:49.34#ibcon#about to read 3, iclass 23, count 0 2006.285.15:10:49.38#ibcon#read 3, iclass 23, count 0 2006.285.15:10:49.38#ibcon#about to read 4, iclass 23, count 0 2006.285.15:10:49.38#ibcon#read 4, iclass 23, count 0 2006.285.15:10:49.38#ibcon#about to read 5, iclass 23, count 0 2006.285.15:10:49.38#ibcon#read 5, iclass 23, count 0 2006.285.15:10:49.38#ibcon#about to read 6, iclass 23, count 0 2006.285.15:10:49.38#ibcon#read 6, iclass 23, count 0 2006.285.15:10:49.38#ibcon#end of sib2, iclass 23, count 0 2006.285.15:10:49.38#ibcon#*after write, iclass 23, count 0 2006.285.15:10:49.38#ibcon#*before return 0, iclass 23, count 0 2006.285.15:10:49.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:10:49.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:10:49.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.15:10:49.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.15:10:49.38$vck44/vb=2,5 2006.285.15:10:49.38#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.15:10:49.38#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.15:10:49.38#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:49.38#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:10:49.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:10:49.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:10:49.44#ibcon#enter wrdev, iclass 25, count 2 2006.285.15:10:49.44#ibcon#first serial, iclass 25, count 2 2006.285.15:10:49.44#ibcon#enter sib2, iclass 25, count 2 2006.285.15:10:49.44#ibcon#flushed, iclass 25, count 2 2006.285.15:10:49.44#ibcon#about to write, iclass 25, count 2 2006.285.15:10:49.44#ibcon#wrote, iclass 25, count 2 2006.285.15:10:49.44#ibcon#about to read 3, iclass 25, count 2 2006.285.15:10:49.46#ibcon#read 3, iclass 25, count 2 2006.285.15:10:49.46#ibcon#about to read 4, iclass 25, count 2 2006.285.15:10:49.46#ibcon#read 4, iclass 25, count 2 2006.285.15:10:49.46#ibcon#about to read 5, iclass 25, count 2 2006.285.15:10:49.46#ibcon#read 5, iclass 25, count 2 2006.285.15:10:49.46#ibcon#about to read 6, iclass 25, count 2 2006.285.15:10:49.46#ibcon#read 6, iclass 25, count 2 2006.285.15:10:49.46#ibcon#end of sib2, iclass 25, count 2 2006.285.15:10:49.46#ibcon#*mode == 0, iclass 25, count 2 2006.285.15:10:49.46#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.15:10:49.46#ibcon#[27=AT02-05\r\n] 2006.285.15:10:49.46#ibcon#*before write, iclass 25, count 2 2006.285.15:10:49.46#ibcon#enter sib2, iclass 25, count 2 2006.285.15:10:49.46#ibcon#flushed, iclass 25, count 2 2006.285.15:10:49.46#ibcon#about to write, iclass 25, count 2 2006.285.15:10:49.46#ibcon#wrote, iclass 25, count 2 2006.285.15:10:49.46#ibcon#about to read 3, iclass 25, count 2 2006.285.15:10:49.49#ibcon#read 3, iclass 25, count 2 2006.285.15:10:49.49#ibcon#about to read 4, iclass 25, count 2 2006.285.15:10:49.49#ibcon#read 4, iclass 25, count 2 2006.285.15:10:49.49#ibcon#about to read 5, iclass 25, count 2 2006.285.15:10:49.49#ibcon#read 5, iclass 25, count 2 2006.285.15:10:49.49#ibcon#about to read 6, iclass 25, count 2 2006.285.15:10:49.49#ibcon#read 6, iclass 25, count 2 2006.285.15:10:49.49#ibcon#end of sib2, iclass 25, count 2 2006.285.15:10:49.49#ibcon#*after write, iclass 25, count 2 2006.285.15:10:49.49#ibcon#*before return 0, iclass 25, count 2 2006.285.15:10:49.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:10:49.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:10:49.49#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.15:10:49.49#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:49.49#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:10:49.51#abcon#<5=/03 1.9 3.7 19.16 921014.9\r\n> 2006.285.15:10:49.53#abcon#{5=INTERFACE CLEAR} 2006.285.15:10:49.59#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:10:49.61#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:10:49.61#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:10:49.61#ibcon#enter wrdev, iclass 25, count 0 2006.285.15:10:49.61#ibcon#first serial, iclass 25, count 0 2006.285.15:10:49.61#ibcon#enter sib2, iclass 25, count 0 2006.285.15:10:49.61#ibcon#flushed, iclass 25, count 0 2006.285.15:10:49.61#ibcon#about to write, iclass 25, count 0 2006.285.15:10:49.61#ibcon#wrote, iclass 25, count 0 2006.285.15:10:49.61#ibcon#about to read 3, iclass 25, count 0 2006.285.15:10:49.63#ibcon#read 3, iclass 25, count 0 2006.285.15:10:49.63#ibcon#about to read 4, iclass 25, count 0 2006.285.15:10:49.63#ibcon#read 4, iclass 25, count 0 2006.285.15:10:49.63#ibcon#about to read 5, iclass 25, count 0 2006.285.15:10:49.63#ibcon#read 5, iclass 25, count 0 2006.285.15:10:49.63#ibcon#about to read 6, iclass 25, count 0 2006.285.15:10:49.63#ibcon#read 6, iclass 25, count 0 2006.285.15:10:49.63#ibcon#end of sib2, iclass 25, count 0 2006.285.15:10:49.63#ibcon#*mode == 0, iclass 25, count 0 2006.285.15:10:49.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.15:10:49.63#ibcon#[27=USB\r\n] 2006.285.15:10:49.63#ibcon#*before write, iclass 25, count 0 2006.285.15:10:49.63#ibcon#enter sib2, iclass 25, count 0 2006.285.15:10:49.63#ibcon#flushed, iclass 25, count 0 2006.285.15:10:49.63#ibcon#about to write, iclass 25, count 0 2006.285.15:10:49.63#ibcon#wrote, iclass 25, count 0 2006.285.15:10:49.63#ibcon#about to read 3, iclass 25, count 0 2006.285.15:10:49.66#ibcon#read 3, iclass 25, count 0 2006.285.15:10:49.66#ibcon#about to read 4, iclass 25, count 0 2006.285.15:10:49.66#ibcon#read 4, iclass 25, count 0 2006.285.15:10:49.66#ibcon#about to read 5, iclass 25, count 0 2006.285.15:10:49.66#ibcon#read 5, iclass 25, count 0 2006.285.15:10:49.66#ibcon#about to read 6, iclass 25, count 0 2006.285.15:10:49.66#ibcon#read 6, iclass 25, count 0 2006.285.15:10:49.66#ibcon#end of sib2, iclass 25, count 0 2006.285.15:10:49.66#ibcon#*after write, iclass 25, count 0 2006.285.15:10:49.66#ibcon#*before return 0, iclass 25, count 0 2006.285.15:10:49.66#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:10:49.66#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:10:49.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.15:10:49.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.15:10:49.66$vck44/vblo=3,649.99 2006.285.15:10:49.66#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.15:10:49.66#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.15:10:49.66#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:49.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:10:49.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:10:49.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:10:49.66#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:10:49.66#ibcon#first serial, iclass 31, count 0 2006.285.15:10:49.66#ibcon#enter sib2, iclass 31, count 0 2006.285.15:10:49.66#ibcon#flushed, iclass 31, count 0 2006.285.15:10:49.66#ibcon#about to write, iclass 31, count 0 2006.285.15:10:49.66#ibcon#wrote, iclass 31, count 0 2006.285.15:10:49.66#ibcon#about to read 3, iclass 31, count 0 2006.285.15:10:49.68#ibcon#read 3, iclass 31, count 0 2006.285.15:10:49.68#ibcon#about to read 4, iclass 31, count 0 2006.285.15:10:49.68#ibcon#read 4, iclass 31, count 0 2006.285.15:10:49.68#ibcon#about to read 5, iclass 31, count 0 2006.285.15:10:49.68#ibcon#read 5, iclass 31, count 0 2006.285.15:10:49.68#ibcon#about to read 6, iclass 31, count 0 2006.285.15:10:49.68#ibcon#read 6, iclass 31, count 0 2006.285.15:10:49.68#ibcon#end of sib2, iclass 31, count 0 2006.285.15:10:49.68#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:10:49.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:10:49.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.15:10:49.68#ibcon#*before write, iclass 31, count 0 2006.285.15:10:49.68#ibcon#enter sib2, iclass 31, count 0 2006.285.15:10:49.68#ibcon#flushed, iclass 31, count 0 2006.285.15:10:49.68#ibcon#about to write, iclass 31, count 0 2006.285.15:10:49.68#ibcon#wrote, iclass 31, count 0 2006.285.15:10:49.68#ibcon#about to read 3, iclass 31, count 0 2006.285.15:10:49.72#ibcon#read 3, iclass 31, count 0 2006.285.15:10:49.72#ibcon#about to read 4, iclass 31, count 0 2006.285.15:10:49.72#ibcon#read 4, iclass 31, count 0 2006.285.15:10:49.72#ibcon#about to read 5, iclass 31, count 0 2006.285.15:10:49.72#ibcon#read 5, iclass 31, count 0 2006.285.15:10:49.72#ibcon#about to read 6, iclass 31, count 0 2006.285.15:10:49.72#ibcon#read 6, iclass 31, count 0 2006.285.15:10:49.72#ibcon#end of sib2, iclass 31, count 0 2006.285.15:10:49.72#ibcon#*after write, iclass 31, count 0 2006.285.15:10:49.72#ibcon#*before return 0, iclass 31, count 0 2006.285.15:10:49.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:10:49.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:10:49.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:10:49.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:10:49.72$vck44/vb=3,4 2006.285.15:10:49.72#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.15:10:49.72#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.15:10:49.72#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:49.72#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:10:49.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:10:49.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:10:49.78#ibcon#enter wrdev, iclass 33, count 2 2006.285.15:10:49.78#ibcon#first serial, iclass 33, count 2 2006.285.15:10:49.78#ibcon#enter sib2, iclass 33, count 2 2006.285.15:10:49.78#ibcon#flushed, iclass 33, count 2 2006.285.15:10:49.78#ibcon#about to write, iclass 33, count 2 2006.285.15:10:49.78#ibcon#wrote, iclass 33, count 2 2006.285.15:10:49.78#ibcon#about to read 3, iclass 33, count 2 2006.285.15:10:49.80#ibcon#read 3, iclass 33, count 2 2006.285.15:10:49.80#ibcon#about to read 4, iclass 33, count 2 2006.285.15:10:49.80#ibcon#read 4, iclass 33, count 2 2006.285.15:10:49.80#ibcon#about to read 5, iclass 33, count 2 2006.285.15:10:49.80#ibcon#read 5, iclass 33, count 2 2006.285.15:10:49.80#ibcon#about to read 6, iclass 33, count 2 2006.285.15:10:49.80#ibcon#read 6, iclass 33, count 2 2006.285.15:10:49.80#ibcon#end of sib2, iclass 33, count 2 2006.285.15:10:49.80#ibcon#*mode == 0, iclass 33, count 2 2006.285.15:10:49.80#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.15:10:49.80#ibcon#[27=AT03-04\r\n] 2006.285.15:10:49.80#ibcon#*before write, iclass 33, count 2 2006.285.15:10:49.80#ibcon#enter sib2, iclass 33, count 2 2006.285.15:10:49.80#ibcon#flushed, iclass 33, count 2 2006.285.15:10:49.80#ibcon#about to write, iclass 33, count 2 2006.285.15:10:49.80#ibcon#wrote, iclass 33, count 2 2006.285.15:10:49.80#ibcon#about to read 3, iclass 33, count 2 2006.285.15:10:49.83#ibcon#read 3, iclass 33, count 2 2006.285.15:10:49.83#ibcon#about to read 4, iclass 33, count 2 2006.285.15:10:49.83#ibcon#read 4, iclass 33, count 2 2006.285.15:10:49.83#ibcon#about to read 5, iclass 33, count 2 2006.285.15:10:49.83#ibcon#read 5, iclass 33, count 2 2006.285.15:10:49.83#ibcon#about to read 6, iclass 33, count 2 2006.285.15:10:49.83#ibcon#read 6, iclass 33, count 2 2006.285.15:10:49.83#ibcon#end of sib2, iclass 33, count 2 2006.285.15:10:49.83#ibcon#*after write, iclass 33, count 2 2006.285.15:10:49.83#ibcon#*before return 0, iclass 33, count 2 2006.285.15:10:49.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:10:49.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:10:49.83#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.15:10:49.83#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:49.83#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:10:49.95#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:10:49.95#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:10:49.95#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:10:49.95#ibcon#first serial, iclass 33, count 0 2006.285.15:10:49.95#ibcon#enter sib2, iclass 33, count 0 2006.285.15:10:49.95#ibcon#flushed, iclass 33, count 0 2006.285.15:10:49.95#ibcon#about to write, iclass 33, count 0 2006.285.15:10:49.95#ibcon#wrote, iclass 33, count 0 2006.285.15:10:49.95#ibcon#about to read 3, iclass 33, count 0 2006.285.15:10:49.97#ibcon#read 3, iclass 33, count 0 2006.285.15:10:49.97#ibcon#about to read 4, iclass 33, count 0 2006.285.15:10:49.97#ibcon#read 4, iclass 33, count 0 2006.285.15:10:49.97#ibcon#about to read 5, iclass 33, count 0 2006.285.15:10:49.97#ibcon#read 5, iclass 33, count 0 2006.285.15:10:49.97#ibcon#about to read 6, iclass 33, count 0 2006.285.15:10:49.97#ibcon#read 6, iclass 33, count 0 2006.285.15:10:49.97#ibcon#end of sib2, iclass 33, count 0 2006.285.15:10:49.97#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:10:49.97#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:10:49.97#ibcon#[27=USB\r\n] 2006.285.15:10:49.97#ibcon#*before write, iclass 33, count 0 2006.285.15:10:49.97#ibcon#enter sib2, iclass 33, count 0 2006.285.15:10:49.97#ibcon#flushed, iclass 33, count 0 2006.285.15:10:49.97#ibcon#about to write, iclass 33, count 0 2006.285.15:10:49.97#ibcon#wrote, iclass 33, count 0 2006.285.15:10:49.97#ibcon#about to read 3, iclass 33, count 0 2006.285.15:10:50.00#ibcon#read 3, iclass 33, count 0 2006.285.15:10:50.00#ibcon#about to read 4, iclass 33, count 0 2006.285.15:10:50.00#ibcon#read 4, iclass 33, count 0 2006.285.15:10:50.00#ibcon#about to read 5, iclass 33, count 0 2006.285.15:10:50.00#ibcon#read 5, iclass 33, count 0 2006.285.15:10:50.00#ibcon#about to read 6, iclass 33, count 0 2006.285.15:10:50.00#ibcon#read 6, iclass 33, count 0 2006.285.15:10:50.00#ibcon#end of sib2, iclass 33, count 0 2006.285.15:10:50.00#ibcon#*after write, iclass 33, count 0 2006.285.15:10:50.00#ibcon#*before return 0, iclass 33, count 0 2006.285.15:10:50.00#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:10:50.00#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:10:50.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:10:50.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:10:50.00$vck44/vblo=4,679.99 2006.285.15:10:50.00#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.15:10:50.00#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.15:10:50.00#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:50.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:10:50.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:10:50.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:10:50.00#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:10:50.00#ibcon#first serial, iclass 35, count 0 2006.285.15:10:50.00#ibcon#enter sib2, iclass 35, count 0 2006.285.15:10:50.00#ibcon#flushed, iclass 35, count 0 2006.285.15:10:50.00#ibcon#about to write, iclass 35, count 0 2006.285.15:10:50.00#ibcon#wrote, iclass 35, count 0 2006.285.15:10:50.00#ibcon#about to read 3, iclass 35, count 0 2006.285.15:10:50.02#ibcon#read 3, iclass 35, count 0 2006.285.15:10:50.23#ibcon#about to read 4, iclass 35, count 0 2006.285.15:10:50.23#ibcon#read 4, iclass 35, count 0 2006.285.15:10:50.23#ibcon#about to read 5, iclass 35, count 0 2006.285.15:10:50.23#ibcon#read 5, iclass 35, count 0 2006.285.15:10:50.23#ibcon#about to read 6, iclass 35, count 0 2006.285.15:10:50.23#ibcon#read 6, iclass 35, count 0 2006.285.15:10:50.23#ibcon#end of sib2, iclass 35, count 0 2006.285.15:10:50.23#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:10:50.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:10:50.23#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.15:10:50.23#ibcon#*before write, iclass 35, count 0 2006.285.15:10:50.23#ibcon#enter sib2, iclass 35, count 0 2006.285.15:10:50.23#ibcon#flushed, iclass 35, count 0 2006.285.15:10:50.23#ibcon#about to write, iclass 35, count 0 2006.285.15:10:50.23#ibcon#wrote, iclass 35, count 0 2006.285.15:10:50.23#ibcon#about to read 3, iclass 35, count 0 2006.285.15:10:50.28#ibcon#read 3, iclass 35, count 0 2006.285.15:10:50.28#ibcon#about to read 4, iclass 35, count 0 2006.285.15:10:50.28#ibcon#read 4, iclass 35, count 0 2006.285.15:10:50.28#ibcon#about to read 5, iclass 35, count 0 2006.285.15:10:50.28#ibcon#read 5, iclass 35, count 0 2006.285.15:10:50.28#ibcon#about to read 6, iclass 35, count 0 2006.285.15:10:50.28#ibcon#read 6, iclass 35, count 0 2006.285.15:10:50.28#ibcon#end of sib2, iclass 35, count 0 2006.285.15:10:50.28#ibcon#*after write, iclass 35, count 0 2006.285.15:10:50.28#ibcon#*before return 0, iclass 35, count 0 2006.285.15:10:50.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:10:50.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:10:50.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:10:50.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:10:50.28$vck44/vb=4,5 2006.285.15:10:50.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.15:10:50.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.15:10:50.28#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:50.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:10:50.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:10:50.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:10:50.28#ibcon#enter wrdev, iclass 37, count 2 2006.285.15:10:50.28#ibcon#first serial, iclass 37, count 2 2006.285.15:10:50.28#ibcon#enter sib2, iclass 37, count 2 2006.285.15:10:50.28#ibcon#flushed, iclass 37, count 2 2006.285.15:10:50.28#ibcon#about to write, iclass 37, count 2 2006.285.15:10:50.28#ibcon#wrote, iclass 37, count 2 2006.285.15:10:50.28#ibcon#about to read 3, iclass 37, count 2 2006.285.15:10:50.30#ibcon#read 3, iclass 37, count 2 2006.285.15:10:50.30#ibcon#about to read 4, iclass 37, count 2 2006.285.15:10:50.30#ibcon#read 4, iclass 37, count 2 2006.285.15:10:50.30#ibcon#about to read 5, iclass 37, count 2 2006.285.15:10:50.30#ibcon#read 5, iclass 37, count 2 2006.285.15:10:50.30#ibcon#about to read 6, iclass 37, count 2 2006.285.15:10:50.30#ibcon#read 6, iclass 37, count 2 2006.285.15:10:50.30#ibcon#end of sib2, iclass 37, count 2 2006.285.15:10:50.30#ibcon#*mode == 0, iclass 37, count 2 2006.285.15:10:50.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.15:10:50.30#ibcon#[27=AT04-05\r\n] 2006.285.15:10:50.30#ibcon#*before write, iclass 37, count 2 2006.285.15:10:50.30#ibcon#enter sib2, iclass 37, count 2 2006.285.15:10:50.30#ibcon#flushed, iclass 37, count 2 2006.285.15:10:50.30#ibcon#about to write, iclass 37, count 2 2006.285.15:10:50.30#ibcon#wrote, iclass 37, count 2 2006.285.15:10:50.30#ibcon#about to read 3, iclass 37, count 2 2006.285.15:10:50.33#ibcon#read 3, iclass 37, count 2 2006.285.15:10:50.33#ibcon#about to read 4, iclass 37, count 2 2006.285.15:10:50.33#ibcon#read 4, iclass 37, count 2 2006.285.15:10:50.33#ibcon#about to read 5, iclass 37, count 2 2006.285.15:10:50.33#ibcon#read 5, iclass 37, count 2 2006.285.15:10:50.33#ibcon#about to read 6, iclass 37, count 2 2006.285.15:10:50.33#ibcon#read 6, iclass 37, count 2 2006.285.15:10:50.33#ibcon#end of sib2, iclass 37, count 2 2006.285.15:10:50.33#ibcon#*after write, iclass 37, count 2 2006.285.15:10:50.33#ibcon#*before return 0, iclass 37, count 2 2006.285.15:10:50.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:10:50.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:10:50.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.15:10:50.33#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:50.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:10:50.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:10:50.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:10:50.45#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:10:50.45#ibcon#first serial, iclass 37, count 0 2006.285.15:10:50.45#ibcon#enter sib2, iclass 37, count 0 2006.285.15:10:50.45#ibcon#flushed, iclass 37, count 0 2006.285.15:10:50.45#ibcon#about to write, iclass 37, count 0 2006.285.15:10:50.45#ibcon#wrote, iclass 37, count 0 2006.285.15:10:50.45#ibcon#about to read 3, iclass 37, count 0 2006.285.15:10:50.47#ibcon#read 3, iclass 37, count 0 2006.285.15:10:50.47#ibcon#about to read 4, iclass 37, count 0 2006.285.15:10:50.47#ibcon#read 4, iclass 37, count 0 2006.285.15:10:50.47#ibcon#about to read 5, iclass 37, count 0 2006.285.15:10:50.47#ibcon#read 5, iclass 37, count 0 2006.285.15:10:50.47#ibcon#about to read 6, iclass 37, count 0 2006.285.15:10:50.47#ibcon#read 6, iclass 37, count 0 2006.285.15:10:50.47#ibcon#end of sib2, iclass 37, count 0 2006.285.15:10:50.47#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:10:50.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:10:50.47#ibcon#[27=USB\r\n] 2006.285.15:10:50.47#ibcon#*before write, iclass 37, count 0 2006.285.15:10:50.47#ibcon#enter sib2, iclass 37, count 0 2006.285.15:10:50.47#ibcon#flushed, iclass 37, count 0 2006.285.15:10:50.47#ibcon#about to write, iclass 37, count 0 2006.285.15:10:50.47#ibcon#wrote, iclass 37, count 0 2006.285.15:10:50.47#ibcon#about to read 3, iclass 37, count 0 2006.285.15:10:50.50#ibcon#read 3, iclass 37, count 0 2006.285.15:10:50.50#ibcon#about to read 4, iclass 37, count 0 2006.285.15:10:50.50#ibcon#read 4, iclass 37, count 0 2006.285.15:10:50.50#ibcon#about to read 5, iclass 37, count 0 2006.285.15:10:50.50#ibcon#read 5, iclass 37, count 0 2006.285.15:10:50.50#ibcon#about to read 6, iclass 37, count 0 2006.285.15:10:50.50#ibcon#read 6, iclass 37, count 0 2006.285.15:10:50.50#ibcon#end of sib2, iclass 37, count 0 2006.285.15:10:50.50#ibcon#*after write, iclass 37, count 0 2006.285.15:10:50.50#ibcon#*before return 0, iclass 37, count 0 2006.285.15:10:50.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:10:50.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:10:50.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:10:50.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:10:50.50$vck44/vblo=5,709.99 2006.285.15:10:50.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.15:10:50.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.15:10:50.50#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:50.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:10:50.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:10:50.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:10:50.50#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:10:50.50#ibcon#first serial, iclass 39, count 0 2006.285.15:10:50.50#ibcon#enter sib2, iclass 39, count 0 2006.285.15:10:50.50#ibcon#flushed, iclass 39, count 0 2006.285.15:10:50.50#ibcon#about to write, iclass 39, count 0 2006.285.15:10:50.50#ibcon#wrote, iclass 39, count 0 2006.285.15:10:50.50#ibcon#about to read 3, iclass 39, count 0 2006.285.15:10:50.52#ibcon#read 3, iclass 39, count 0 2006.285.15:10:50.52#ibcon#about to read 4, iclass 39, count 0 2006.285.15:10:50.52#ibcon#read 4, iclass 39, count 0 2006.285.15:10:50.52#ibcon#about to read 5, iclass 39, count 0 2006.285.15:10:50.52#ibcon#read 5, iclass 39, count 0 2006.285.15:10:50.52#ibcon#about to read 6, iclass 39, count 0 2006.285.15:10:50.52#ibcon#read 6, iclass 39, count 0 2006.285.15:10:50.52#ibcon#end of sib2, iclass 39, count 0 2006.285.15:10:50.52#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:10:50.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:10:50.52#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.15:10:50.52#ibcon#*before write, iclass 39, count 0 2006.285.15:10:50.52#ibcon#enter sib2, iclass 39, count 0 2006.285.15:10:50.52#ibcon#flushed, iclass 39, count 0 2006.285.15:10:50.52#ibcon#about to write, iclass 39, count 0 2006.285.15:10:50.52#ibcon#wrote, iclass 39, count 0 2006.285.15:10:50.52#ibcon#about to read 3, iclass 39, count 0 2006.285.15:10:50.56#ibcon#read 3, iclass 39, count 0 2006.285.15:10:50.56#ibcon#about to read 4, iclass 39, count 0 2006.285.15:10:50.56#ibcon#read 4, iclass 39, count 0 2006.285.15:10:50.56#ibcon#about to read 5, iclass 39, count 0 2006.285.15:10:50.56#ibcon#read 5, iclass 39, count 0 2006.285.15:10:50.56#ibcon#about to read 6, iclass 39, count 0 2006.285.15:10:50.56#ibcon#read 6, iclass 39, count 0 2006.285.15:10:50.56#ibcon#end of sib2, iclass 39, count 0 2006.285.15:10:50.56#ibcon#*after write, iclass 39, count 0 2006.285.15:10:50.56#ibcon#*before return 0, iclass 39, count 0 2006.285.15:10:50.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:10:50.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:10:50.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:10:50.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:10:50.56$vck44/vb=5,4 2006.285.15:10:50.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.15:10:50.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.15:10:50.56#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:50.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:10:50.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:10:50.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:10:50.62#ibcon#enter wrdev, iclass 3, count 2 2006.285.15:10:50.62#ibcon#first serial, iclass 3, count 2 2006.285.15:10:50.62#ibcon#enter sib2, iclass 3, count 2 2006.285.15:10:50.62#ibcon#flushed, iclass 3, count 2 2006.285.15:10:50.62#ibcon#about to write, iclass 3, count 2 2006.285.15:10:50.62#ibcon#wrote, iclass 3, count 2 2006.285.15:10:50.62#ibcon#about to read 3, iclass 3, count 2 2006.285.15:10:50.64#ibcon#read 3, iclass 3, count 2 2006.285.15:10:50.64#ibcon#about to read 4, iclass 3, count 2 2006.285.15:10:50.64#ibcon#read 4, iclass 3, count 2 2006.285.15:10:50.64#ibcon#about to read 5, iclass 3, count 2 2006.285.15:10:50.64#ibcon#read 5, iclass 3, count 2 2006.285.15:10:50.64#ibcon#about to read 6, iclass 3, count 2 2006.285.15:10:50.64#ibcon#read 6, iclass 3, count 2 2006.285.15:10:50.64#ibcon#end of sib2, iclass 3, count 2 2006.285.15:10:50.64#ibcon#*mode == 0, iclass 3, count 2 2006.285.15:10:50.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.15:10:50.64#ibcon#[27=AT05-04\r\n] 2006.285.15:10:50.64#ibcon#*before write, iclass 3, count 2 2006.285.15:10:50.64#ibcon#enter sib2, iclass 3, count 2 2006.285.15:10:50.64#ibcon#flushed, iclass 3, count 2 2006.285.15:10:50.64#ibcon#about to write, iclass 3, count 2 2006.285.15:10:50.64#ibcon#wrote, iclass 3, count 2 2006.285.15:10:50.64#ibcon#about to read 3, iclass 3, count 2 2006.285.15:10:50.67#ibcon#read 3, iclass 3, count 2 2006.285.15:10:50.67#ibcon#about to read 4, iclass 3, count 2 2006.285.15:10:50.67#ibcon#read 4, iclass 3, count 2 2006.285.15:10:50.67#ibcon#about to read 5, iclass 3, count 2 2006.285.15:10:50.67#ibcon#read 5, iclass 3, count 2 2006.285.15:10:50.67#ibcon#about to read 6, iclass 3, count 2 2006.285.15:10:50.67#ibcon#read 6, iclass 3, count 2 2006.285.15:10:50.67#ibcon#end of sib2, iclass 3, count 2 2006.285.15:10:50.67#ibcon#*after write, iclass 3, count 2 2006.285.15:10:50.67#ibcon#*before return 0, iclass 3, count 2 2006.285.15:10:50.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:10:50.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:10:50.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.15:10:50.67#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:50.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:10:50.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:10:50.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:10:50.79#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:10:50.79#ibcon#first serial, iclass 3, count 0 2006.285.15:10:50.79#ibcon#enter sib2, iclass 3, count 0 2006.285.15:10:50.79#ibcon#flushed, iclass 3, count 0 2006.285.15:10:50.79#ibcon#about to write, iclass 3, count 0 2006.285.15:10:50.79#ibcon#wrote, iclass 3, count 0 2006.285.15:10:50.79#ibcon#about to read 3, iclass 3, count 0 2006.285.15:10:50.81#ibcon#read 3, iclass 3, count 0 2006.285.15:10:50.81#ibcon#about to read 4, iclass 3, count 0 2006.285.15:10:50.81#ibcon#read 4, iclass 3, count 0 2006.285.15:10:50.81#ibcon#about to read 5, iclass 3, count 0 2006.285.15:10:50.81#ibcon#read 5, iclass 3, count 0 2006.285.15:10:50.81#ibcon#about to read 6, iclass 3, count 0 2006.285.15:10:50.81#ibcon#read 6, iclass 3, count 0 2006.285.15:10:50.81#ibcon#end of sib2, iclass 3, count 0 2006.285.15:10:50.81#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:10:50.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:10:50.81#ibcon#[27=USB\r\n] 2006.285.15:10:50.81#ibcon#*before write, iclass 3, count 0 2006.285.15:10:50.81#ibcon#enter sib2, iclass 3, count 0 2006.285.15:10:50.81#ibcon#flushed, iclass 3, count 0 2006.285.15:10:50.81#ibcon#about to write, iclass 3, count 0 2006.285.15:10:50.81#ibcon#wrote, iclass 3, count 0 2006.285.15:10:50.81#ibcon#about to read 3, iclass 3, count 0 2006.285.15:10:50.84#ibcon#read 3, iclass 3, count 0 2006.285.15:10:50.84#ibcon#about to read 4, iclass 3, count 0 2006.285.15:10:50.84#ibcon#read 4, iclass 3, count 0 2006.285.15:10:50.84#ibcon#about to read 5, iclass 3, count 0 2006.285.15:10:50.84#ibcon#read 5, iclass 3, count 0 2006.285.15:10:50.84#ibcon#about to read 6, iclass 3, count 0 2006.285.15:10:50.84#ibcon#read 6, iclass 3, count 0 2006.285.15:10:50.84#ibcon#end of sib2, iclass 3, count 0 2006.285.15:10:50.84#ibcon#*after write, iclass 3, count 0 2006.285.15:10:50.84#ibcon#*before return 0, iclass 3, count 0 2006.285.15:10:50.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:10:50.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:10:50.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:10:50.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:10:50.84$vck44/vblo=6,719.99 2006.285.15:10:50.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.15:10:50.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.15:10:50.84#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:50.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:10:50.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:10:50.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:10:50.84#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:10:50.84#ibcon#first serial, iclass 5, count 0 2006.285.15:10:50.84#ibcon#enter sib2, iclass 5, count 0 2006.285.15:10:50.84#ibcon#flushed, iclass 5, count 0 2006.285.15:10:50.84#ibcon#about to write, iclass 5, count 0 2006.285.15:10:50.84#ibcon#wrote, iclass 5, count 0 2006.285.15:10:50.84#ibcon#about to read 3, iclass 5, count 0 2006.285.15:10:50.86#ibcon#read 3, iclass 5, count 0 2006.285.15:10:50.86#ibcon#about to read 4, iclass 5, count 0 2006.285.15:10:50.86#ibcon#read 4, iclass 5, count 0 2006.285.15:10:50.86#ibcon#about to read 5, iclass 5, count 0 2006.285.15:10:50.86#ibcon#read 5, iclass 5, count 0 2006.285.15:10:50.86#ibcon#about to read 6, iclass 5, count 0 2006.285.15:10:50.86#ibcon#read 6, iclass 5, count 0 2006.285.15:10:50.86#ibcon#end of sib2, iclass 5, count 0 2006.285.15:10:50.86#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:10:50.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:10:50.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.15:10:50.86#ibcon#*before write, iclass 5, count 0 2006.285.15:10:50.86#ibcon#enter sib2, iclass 5, count 0 2006.285.15:10:50.86#ibcon#flushed, iclass 5, count 0 2006.285.15:10:50.86#ibcon#about to write, iclass 5, count 0 2006.285.15:10:50.86#ibcon#wrote, iclass 5, count 0 2006.285.15:10:50.86#ibcon#about to read 3, iclass 5, count 0 2006.285.15:10:50.90#ibcon#read 3, iclass 5, count 0 2006.285.15:10:50.90#ibcon#about to read 4, iclass 5, count 0 2006.285.15:10:50.90#ibcon#read 4, iclass 5, count 0 2006.285.15:10:50.90#ibcon#about to read 5, iclass 5, count 0 2006.285.15:10:50.90#ibcon#read 5, iclass 5, count 0 2006.285.15:10:50.90#ibcon#about to read 6, iclass 5, count 0 2006.285.15:10:50.90#ibcon#read 6, iclass 5, count 0 2006.285.15:10:50.90#ibcon#end of sib2, iclass 5, count 0 2006.285.15:10:50.90#ibcon#*after write, iclass 5, count 0 2006.285.15:10:50.90#ibcon#*before return 0, iclass 5, count 0 2006.285.15:10:50.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:10:50.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:10:50.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:10:50.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:10:50.90$vck44/vb=6,3 2006.285.15:10:50.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.15:10:50.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.15:10:50.90#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:50.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:10:50.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:10:50.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:10:50.96#ibcon#enter wrdev, iclass 7, count 2 2006.285.15:10:50.96#ibcon#first serial, iclass 7, count 2 2006.285.15:10:50.96#ibcon#enter sib2, iclass 7, count 2 2006.285.15:10:50.96#ibcon#flushed, iclass 7, count 2 2006.285.15:10:50.96#ibcon#about to write, iclass 7, count 2 2006.285.15:10:50.96#ibcon#wrote, iclass 7, count 2 2006.285.15:10:50.96#ibcon#about to read 3, iclass 7, count 2 2006.285.15:10:50.98#ibcon#read 3, iclass 7, count 2 2006.285.15:10:50.98#ibcon#about to read 4, iclass 7, count 2 2006.285.15:10:50.98#ibcon#read 4, iclass 7, count 2 2006.285.15:10:50.98#ibcon#about to read 5, iclass 7, count 2 2006.285.15:10:50.98#ibcon#read 5, iclass 7, count 2 2006.285.15:10:50.98#ibcon#about to read 6, iclass 7, count 2 2006.285.15:10:50.98#ibcon#read 6, iclass 7, count 2 2006.285.15:10:50.98#ibcon#end of sib2, iclass 7, count 2 2006.285.15:10:50.98#ibcon#*mode == 0, iclass 7, count 2 2006.285.15:10:50.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.15:10:50.98#ibcon#[27=AT06-03\r\n] 2006.285.15:10:50.98#ibcon#*before write, iclass 7, count 2 2006.285.15:10:50.98#ibcon#enter sib2, iclass 7, count 2 2006.285.15:10:50.98#ibcon#flushed, iclass 7, count 2 2006.285.15:10:50.98#ibcon#about to write, iclass 7, count 2 2006.285.15:10:50.98#ibcon#wrote, iclass 7, count 2 2006.285.15:10:50.98#ibcon#about to read 3, iclass 7, count 2 2006.285.15:10:51.01#ibcon#read 3, iclass 7, count 2 2006.285.15:10:51.01#ibcon#about to read 4, iclass 7, count 2 2006.285.15:10:51.01#ibcon#read 4, iclass 7, count 2 2006.285.15:10:51.01#ibcon#about to read 5, iclass 7, count 2 2006.285.15:10:51.01#ibcon#read 5, iclass 7, count 2 2006.285.15:10:51.01#ibcon#about to read 6, iclass 7, count 2 2006.285.15:10:51.01#ibcon#read 6, iclass 7, count 2 2006.285.15:10:51.01#ibcon#end of sib2, iclass 7, count 2 2006.285.15:10:51.01#ibcon#*after write, iclass 7, count 2 2006.285.15:10:51.01#ibcon#*before return 0, iclass 7, count 2 2006.285.15:10:51.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:10:51.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:10:51.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.15:10:51.01#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:51.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:10:51.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:10:51.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:10:51.13#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:10:51.13#ibcon#first serial, iclass 7, count 0 2006.285.15:10:51.13#ibcon#enter sib2, iclass 7, count 0 2006.285.15:10:51.13#ibcon#flushed, iclass 7, count 0 2006.285.15:10:51.13#ibcon#about to write, iclass 7, count 0 2006.285.15:10:51.13#ibcon#wrote, iclass 7, count 0 2006.285.15:10:51.13#ibcon#about to read 3, iclass 7, count 0 2006.285.15:10:51.15#ibcon#read 3, iclass 7, count 0 2006.285.15:10:51.15#ibcon#about to read 4, iclass 7, count 0 2006.285.15:10:51.15#ibcon#read 4, iclass 7, count 0 2006.285.15:10:51.15#ibcon#about to read 5, iclass 7, count 0 2006.285.15:10:51.15#ibcon#read 5, iclass 7, count 0 2006.285.15:10:51.15#ibcon#about to read 6, iclass 7, count 0 2006.285.15:10:51.15#ibcon#read 6, iclass 7, count 0 2006.285.15:10:51.15#ibcon#end of sib2, iclass 7, count 0 2006.285.15:10:51.15#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:10:51.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:10:51.15#ibcon#[27=USB\r\n] 2006.285.15:10:51.15#ibcon#*before write, iclass 7, count 0 2006.285.15:10:51.15#ibcon#enter sib2, iclass 7, count 0 2006.285.15:10:51.15#ibcon#flushed, iclass 7, count 0 2006.285.15:10:51.15#ibcon#about to write, iclass 7, count 0 2006.285.15:10:51.15#ibcon#wrote, iclass 7, count 0 2006.285.15:10:51.15#ibcon#about to read 3, iclass 7, count 0 2006.285.15:10:51.18#ibcon#read 3, iclass 7, count 0 2006.285.15:10:51.18#ibcon#about to read 4, iclass 7, count 0 2006.285.15:10:51.18#ibcon#read 4, iclass 7, count 0 2006.285.15:10:51.18#ibcon#about to read 5, iclass 7, count 0 2006.285.15:10:51.18#ibcon#read 5, iclass 7, count 0 2006.285.15:10:51.18#ibcon#about to read 6, iclass 7, count 0 2006.285.15:10:51.18#ibcon#read 6, iclass 7, count 0 2006.285.15:10:51.18#ibcon#end of sib2, iclass 7, count 0 2006.285.15:10:51.18#ibcon#*after write, iclass 7, count 0 2006.285.15:10:51.18#ibcon#*before return 0, iclass 7, count 0 2006.285.15:10:51.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:10:51.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:10:51.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:10:51.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:10:51.18$vck44/vblo=7,734.99 2006.285.15:10:51.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.15:10:51.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.15:10:51.18#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:51.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:10:51.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:10:51.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:10:51.18#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:10:51.18#ibcon#first serial, iclass 11, count 0 2006.285.15:10:51.18#ibcon#enter sib2, iclass 11, count 0 2006.285.15:10:51.18#ibcon#flushed, iclass 11, count 0 2006.285.15:10:51.18#ibcon#about to write, iclass 11, count 0 2006.285.15:10:51.18#ibcon#wrote, iclass 11, count 0 2006.285.15:10:51.18#ibcon#about to read 3, iclass 11, count 0 2006.285.15:10:51.20#ibcon#read 3, iclass 11, count 0 2006.285.15:10:51.20#ibcon#about to read 4, iclass 11, count 0 2006.285.15:10:51.20#ibcon#read 4, iclass 11, count 0 2006.285.15:10:51.20#ibcon#about to read 5, iclass 11, count 0 2006.285.15:10:51.20#ibcon#read 5, iclass 11, count 0 2006.285.15:10:51.20#ibcon#about to read 6, iclass 11, count 0 2006.285.15:10:51.20#ibcon#read 6, iclass 11, count 0 2006.285.15:10:51.20#ibcon#end of sib2, iclass 11, count 0 2006.285.15:10:51.20#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:10:51.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:10:51.20#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.15:10:51.20#ibcon#*before write, iclass 11, count 0 2006.285.15:10:51.20#ibcon#enter sib2, iclass 11, count 0 2006.285.15:10:51.20#ibcon#flushed, iclass 11, count 0 2006.285.15:10:51.20#ibcon#about to write, iclass 11, count 0 2006.285.15:10:51.20#ibcon#wrote, iclass 11, count 0 2006.285.15:10:51.20#ibcon#about to read 3, iclass 11, count 0 2006.285.15:10:51.24#ibcon#read 3, iclass 11, count 0 2006.285.15:10:51.24#ibcon#about to read 4, iclass 11, count 0 2006.285.15:10:51.24#ibcon#read 4, iclass 11, count 0 2006.285.15:10:51.24#ibcon#about to read 5, iclass 11, count 0 2006.285.15:10:51.24#ibcon#read 5, iclass 11, count 0 2006.285.15:10:51.24#ibcon#about to read 6, iclass 11, count 0 2006.285.15:10:51.24#ibcon#read 6, iclass 11, count 0 2006.285.15:10:51.24#ibcon#end of sib2, iclass 11, count 0 2006.285.15:10:51.24#ibcon#*after write, iclass 11, count 0 2006.285.15:10:51.24#ibcon#*before return 0, iclass 11, count 0 2006.285.15:10:51.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:10:51.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:10:51.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:10:51.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:10:51.24$vck44/vb=7,4 2006.285.15:10:51.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.15:10:51.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.15:10:51.24#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:51.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:10:51.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:10:51.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:10:51.30#ibcon#enter wrdev, iclass 13, count 2 2006.285.15:10:51.30#ibcon#first serial, iclass 13, count 2 2006.285.15:10:51.30#ibcon#enter sib2, iclass 13, count 2 2006.285.15:10:51.30#ibcon#flushed, iclass 13, count 2 2006.285.15:10:51.30#ibcon#about to write, iclass 13, count 2 2006.285.15:10:51.30#ibcon#wrote, iclass 13, count 2 2006.285.15:10:51.30#ibcon#about to read 3, iclass 13, count 2 2006.285.15:10:51.32#ibcon#read 3, iclass 13, count 2 2006.285.15:10:51.32#ibcon#about to read 4, iclass 13, count 2 2006.285.15:10:51.32#ibcon#read 4, iclass 13, count 2 2006.285.15:10:51.32#ibcon#about to read 5, iclass 13, count 2 2006.285.15:10:51.32#ibcon#read 5, iclass 13, count 2 2006.285.15:10:51.32#ibcon#about to read 6, iclass 13, count 2 2006.285.15:10:51.32#ibcon#read 6, iclass 13, count 2 2006.285.15:10:51.32#ibcon#end of sib2, iclass 13, count 2 2006.285.15:10:51.32#ibcon#*mode == 0, iclass 13, count 2 2006.285.15:10:51.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.15:10:51.32#ibcon#[27=AT07-04\r\n] 2006.285.15:10:51.32#ibcon#*before write, iclass 13, count 2 2006.285.15:10:51.32#ibcon#enter sib2, iclass 13, count 2 2006.285.15:10:51.32#ibcon#flushed, iclass 13, count 2 2006.285.15:10:51.32#ibcon#about to write, iclass 13, count 2 2006.285.15:10:51.32#ibcon#wrote, iclass 13, count 2 2006.285.15:10:51.32#ibcon#about to read 3, iclass 13, count 2 2006.285.15:10:51.35#ibcon#read 3, iclass 13, count 2 2006.285.15:10:51.35#ibcon#about to read 4, iclass 13, count 2 2006.285.15:10:51.35#ibcon#read 4, iclass 13, count 2 2006.285.15:10:51.35#ibcon#about to read 5, iclass 13, count 2 2006.285.15:10:51.35#ibcon#read 5, iclass 13, count 2 2006.285.15:10:51.35#ibcon#about to read 6, iclass 13, count 2 2006.285.15:10:51.35#ibcon#read 6, iclass 13, count 2 2006.285.15:10:51.35#ibcon#end of sib2, iclass 13, count 2 2006.285.15:10:51.35#ibcon#*after write, iclass 13, count 2 2006.285.15:10:51.35#ibcon#*before return 0, iclass 13, count 2 2006.285.15:10:51.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:10:51.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:10:51.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.15:10:51.35#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:51.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:10:51.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:10:51.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:10:51.47#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:10:51.47#ibcon#first serial, iclass 13, count 0 2006.285.15:10:51.47#ibcon#enter sib2, iclass 13, count 0 2006.285.15:10:51.47#ibcon#flushed, iclass 13, count 0 2006.285.15:10:51.47#ibcon#about to write, iclass 13, count 0 2006.285.15:10:51.47#ibcon#wrote, iclass 13, count 0 2006.285.15:10:51.47#ibcon#about to read 3, iclass 13, count 0 2006.285.15:10:51.49#ibcon#read 3, iclass 13, count 0 2006.285.15:10:51.49#ibcon#about to read 4, iclass 13, count 0 2006.285.15:10:51.49#ibcon#read 4, iclass 13, count 0 2006.285.15:10:51.49#ibcon#about to read 5, iclass 13, count 0 2006.285.15:10:51.49#ibcon#read 5, iclass 13, count 0 2006.285.15:10:51.49#ibcon#about to read 6, iclass 13, count 0 2006.285.15:10:51.49#ibcon#read 6, iclass 13, count 0 2006.285.15:10:51.49#ibcon#end of sib2, iclass 13, count 0 2006.285.15:10:51.49#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:10:51.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:10:51.49#ibcon#[27=USB\r\n] 2006.285.15:10:51.49#ibcon#*before write, iclass 13, count 0 2006.285.15:10:51.49#ibcon#enter sib2, iclass 13, count 0 2006.285.15:10:51.49#ibcon#flushed, iclass 13, count 0 2006.285.15:10:51.49#ibcon#about to write, iclass 13, count 0 2006.285.15:10:51.49#ibcon#wrote, iclass 13, count 0 2006.285.15:10:51.49#ibcon#about to read 3, iclass 13, count 0 2006.285.15:10:51.52#ibcon#read 3, iclass 13, count 0 2006.285.15:10:51.52#ibcon#about to read 4, iclass 13, count 0 2006.285.15:10:51.52#ibcon#read 4, iclass 13, count 0 2006.285.15:10:51.52#ibcon#about to read 5, iclass 13, count 0 2006.285.15:10:51.52#ibcon#read 5, iclass 13, count 0 2006.285.15:10:51.52#ibcon#about to read 6, iclass 13, count 0 2006.285.15:10:51.52#ibcon#read 6, iclass 13, count 0 2006.285.15:10:51.52#ibcon#end of sib2, iclass 13, count 0 2006.285.15:10:51.52#ibcon#*after write, iclass 13, count 0 2006.285.15:10:51.52#ibcon#*before return 0, iclass 13, count 0 2006.285.15:10:51.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:10:51.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:10:51.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:10:51.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:10:51.52$vck44/vblo=8,744.99 2006.285.15:10:51.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.15:10:51.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.15:10:51.52#ibcon#ireg 17 cls_cnt 0 2006.285.15:10:51.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:10:51.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:10:51.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:10:51.52#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:10:51.52#ibcon#first serial, iclass 15, count 0 2006.285.15:10:51.52#ibcon#enter sib2, iclass 15, count 0 2006.285.15:10:51.52#ibcon#flushed, iclass 15, count 0 2006.285.15:10:51.52#ibcon#about to write, iclass 15, count 0 2006.285.15:10:51.52#ibcon#wrote, iclass 15, count 0 2006.285.15:10:51.52#ibcon#about to read 3, iclass 15, count 0 2006.285.15:10:51.54#ibcon#read 3, iclass 15, count 0 2006.285.15:10:51.54#ibcon#about to read 4, iclass 15, count 0 2006.285.15:10:51.54#ibcon#read 4, iclass 15, count 0 2006.285.15:10:51.54#ibcon#about to read 5, iclass 15, count 0 2006.285.15:10:51.54#ibcon#read 5, iclass 15, count 0 2006.285.15:10:51.54#ibcon#about to read 6, iclass 15, count 0 2006.285.15:10:51.54#ibcon#read 6, iclass 15, count 0 2006.285.15:10:51.54#ibcon#end of sib2, iclass 15, count 0 2006.285.15:10:51.54#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:10:51.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:10:51.54#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.15:10:51.54#ibcon#*before write, iclass 15, count 0 2006.285.15:10:51.54#ibcon#enter sib2, iclass 15, count 0 2006.285.15:10:51.54#ibcon#flushed, iclass 15, count 0 2006.285.15:10:51.54#ibcon#about to write, iclass 15, count 0 2006.285.15:10:51.54#ibcon#wrote, iclass 15, count 0 2006.285.15:10:51.54#ibcon#about to read 3, iclass 15, count 0 2006.285.15:10:51.58#ibcon#read 3, iclass 15, count 0 2006.285.15:10:51.58#ibcon#about to read 4, iclass 15, count 0 2006.285.15:10:51.58#ibcon#read 4, iclass 15, count 0 2006.285.15:10:51.58#ibcon#about to read 5, iclass 15, count 0 2006.285.15:10:51.58#ibcon#read 5, iclass 15, count 0 2006.285.15:10:51.58#ibcon#about to read 6, iclass 15, count 0 2006.285.15:10:51.58#ibcon#read 6, iclass 15, count 0 2006.285.15:10:51.58#ibcon#end of sib2, iclass 15, count 0 2006.285.15:10:51.58#ibcon#*after write, iclass 15, count 0 2006.285.15:10:51.58#ibcon#*before return 0, iclass 15, count 0 2006.285.15:10:51.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:10:51.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:10:51.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:10:51.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:10:51.58$vck44/vb=8,4 2006.285.15:10:51.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.15:10:51.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.15:10:51.58#ibcon#ireg 11 cls_cnt 2 2006.285.15:10:51.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:10:51.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:10:51.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:10:51.64#ibcon#enter wrdev, iclass 17, count 2 2006.285.15:10:51.64#ibcon#first serial, iclass 17, count 2 2006.285.15:10:51.64#ibcon#enter sib2, iclass 17, count 2 2006.285.15:10:51.64#ibcon#flushed, iclass 17, count 2 2006.285.15:10:51.64#ibcon#about to write, iclass 17, count 2 2006.285.15:10:51.64#ibcon#wrote, iclass 17, count 2 2006.285.15:10:51.64#ibcon#about to read 3, iclass 17, count 2 2006.285.15:10:51.66#ibcon#read 3, iclass 17, count 2 2006.285.15:10:51.66#ibcon#about to read 4, iclass 17, count 2 2006.285.15:10:51.66#ibcon#read 4, iclass 17, count 2 2006.285.15:10:51.66#ibcon#about to read 5, iclass 17, count 2 2006.285.15:10:51.66#ibcon#read 5, iclass 17, count 2 2006.285.15:10:51.66#ibcon#about to read 6, iclass 17, count 2 2006.285.15:10:51.66#ibcon#read 6, iclass 17, count 2 2006.285.15:10:51.66#ibcon#end of sib2, iclass 17, count 2 2006.285.15:10:51.66#ibcon#*mode == 0, iclass 17, count 2 2006.285.15:10:51.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.15:10:51.66#ibcon#[27=AT08-04\r\n] 2006.285.15:10:51.66#ibcon#*before write, iclass 17, count 2 2006.285.15:10:51.66#ibcon#enter sib2, iclass 17, count 2 2006.285.15:10:51.66#ibcon#flushed, iclass 17, count 2 2006.285.15:10:51.66#ibcon#about to write, iclass 17, count 2 2006.285.15:10:51.66#ibcon#wrote, iclass 17, count 2 2006.285.15:10:51.66#ibcon#about to read 3, iclass 17, count 2 2006.285.15:10:51.69#ibcon#read 3, iclass 17, count 2 2006.285.15:10:51.69#ibcon#about to read 4, iclass 17, count 2 2006.285.15:10:51.69#ibcon#read 4, iclass 17, count 2 2006.285.15:10:51.69#ibcon#about to read 5, iclass 17, count 2 2006.285.15:10:51.69#ibcon#read 5, iclass 17, count 2 2006.285.15:10:51.69#ibcon#about to read 6, iclass 17, count 2 2006.285.15:10:51.69#ibcon#read 6, iclass 17, count 2 2006.285.15:10:51.69#ibcon#end of sib2, iclass 17, count 2 2006.285.15:10:51.69#ibcon#*after write, iclass 17, count 2 2006.285.15:10:51.69#ibcon#*before return 0, iclass 17, count 2 2006.285.15:10:51.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:10:51.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:10:51.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.15:10:51.69#ibcon#ireg 7 cls_cnt 0 2006.285.15:10:51.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:10:51.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:10:51.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:10:51.81#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:10:51.81#ibcon#first serial, iclass 17, count 0 2006.285.15:10:51.81#ibcon#enter sib2, iclass 17, count 0 2006.285.15:10:51.81#ibcon#flushed, iclass 17, count 0 2006.285.15:10:51.81#ibcon#about to write, iclass 17, count 0 2006.285.15:10:51.81#ibcon#wrote, iclass 17, count 0 2006.285.15:10:51.81#ibcon#about to read 3, iclass 17, count 0 2006.285.15:10:51.83#ibcon#read 3, iclass 17, count 0 2006.285.15:10:51.83#ibcon#about to read 4, iclass 17, count 0 2006.285.15:10:51.83#ibcon#read 4, iclass 17, count 0 2006.285.15:10:51.83#ibcon#about to read 5, iclass 17, count 0 2006.285.15:10:51.83#ibcon#read 5, iclass 17, count 0 2006.285.15:10:51.83#ibcon#about to read 6, iclass 17, count 0 2006.285.15:10:51.83#ibcon#read 6, iclass 17, count 0 2006.285.15:10:51.83#ibcon#end of sib2, iclass 17, count 0 2006.285.15:10:51.83#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:10:51.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:10:51.83#ibcon#[27=USB\r\n] 2006.285.15:10:51.83#ibcon#*before write, iclass 17, count 0 2006.285.15:10:51.83#ibcon#enter sib2, iclass 17, count 0 2006.285.15:10:51.83#ibcon#flushed, iclass 17, count 0 2006.285.15:10:51.83#ibcon#about to write, iclass 17, count 0 2006.285.15:10:51.83#ibcon#wrote, iclass 17, count 0 2006.285.15:10:51.83#ibcon#about to read 3, iclass 17, count 0 2006.285.15:10:51.86#ibcon#read 3, iclass 17, count 0 2006.285.15:10:51.86#ibcon#about to read 4, iclass 17, count 0 2006.285.15:10:51.86#ibcon#read 4, iclass 17, count 0 2006.285.15:10:51.86#ibcon#about to read 5, iclass 17, count 0 2006.285.15:10:51.86#ibcon#read 5, iclass 17, count 0 2006.285.15:10:51.86#ibcon#about to read 6, iclass 17, count 0 2006.285.15:10:51.86#ibcon#read 6, iclass 17, count 0 2006.285.15:10:51.86#ibcon#end of sib2, iclass 17, count 0 2006.285.15:10:51.86#ibcon#*after write, iclass 17, count 0 2006.285.15:10:51.86#ibcon#*before return 0, iclass 17, count 0 2006.285.15:10:51.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:10:51.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:10:51.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:10:51.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:10:51.86$vck44/vabw=wide 2006.285.15:10:51.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.15:10:51.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.15:10:51.86#ibcon#ireg 8 cls_cnt 0 2006.285.15:10:51.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:10:51.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:10:51.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:10:51.86#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:10:51.86#ibcon#first serial, iclass 19, count 0 2006.285.15:10:51.86#ibcon#enter sib2, iclass 19, count 0 2006.285.15:10:51.86#ibcon#flushed, iclass 19, count 0 2006.285.15:10:51.86#ibcon#about to write, iclass 19, count 0 2006.285.15:10:51.86#ibcon#wrote, iclass 19, count 0 2006.285.15:10:51.86#ibcon#about to read 3, iclass 19, count 0 2006.285.15:10:51.88#ibcon#read 3, iclass 19, count 0 2006.285.15:10:51.88#ibcon#about to read 4, iclass 19, count 0 2006.285.15:10:51.88#ibcon#read 4, iclass 19, count 0 2006.285.15:10:51.88#ibcon#about to read 5, iclass 19, count 0 2006.285.15:10:51.88#ibcon#read 5, iclass 19, count 0 2006.285.15:10:51.88#ibcon#about to read 6, iclass 19, count 0 2006.285.15:10:51.88#ibcon#read 6, iclass 19, count 0 2006.285.15:10:51.88#ibcon#end of sib2, iclass 19, count 0 2006.285.15:10:51.88#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:10:51.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:10:51.88#ibcon#[25=BW32\r\n] 2006.285.15:10:51.88#ibcon#*before write, iclass 19, count 0 2006.285.15:10:51.88#ibcon#enter sib2, iclass 19, count 0 2006.285.15:10:51.88#ibcon#flushed, iclass 19, count 0 2006.285.15:10:51.88#ibcon#about to write, iclass 19, count 0 2006.285.15:10:51.88#ibcon#wrote, iclass 19, count 0 2006.285.15:10:51.88#ibcon#about to read 3, iclass 19, count 0 2006.285.15:10:51.91#ibcon#read 3, iclass 19, count 0 2006.285.15:10:51.91#ibcon#about to read 4, iclass 19, count 0 2006.285.15:10:51.91#ibcon#read 4, iclass 19, count 0 2006.285.15:10:51.91#ibcon#about to read 5, iclass 19, count 0 2006.285.15:10:51.91#ibcon#read 5, iclass 19, count 0 2006.285.15:10:51.91#ibcon#about to read 6, iclass 19, count 0 2006.285.15:10:51.91#ibcon#read 6, iclass 19, count 0 2006.285.15:10:51.91#ibcon#end of sib2, iclass 19, count 0 2006.285.15:10:51.91#ibcon#*after write, iclass 19, count 0 2006.285.15:10:51.91#ibcon#*before return 0, iclass 19, count 0 2006.285.15:10:51.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:10:51.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:10:51.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:10:51.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:10:51.91$vck44/vbbw=wide 2006.285.15:10:51.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.15:10:51.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.15:10:51.91#ibcon#ireg 8 cls_cnt 0 2006.285.15:10:51.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:10:51.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:10:51.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:10:51.98#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:10:51.98#ibcon#first serial, iclass 21, count 0 2006.285.15:10:51.98#ibcon#enter sib2, iclass 21, count 0 2006.285.15:10:51.98#ibcon#flushed, iclass 21, count 0 2006.285.15:10:51.98#ibcon#about to write, iclass 21, count 0 2006.285.15:10:51.98#ibcon#wrote, iclass 21, count 0 2006.285.15:10:51.98#ibcon#about to read 3, iclass 21, count 0 2006.285.15:10:52.00#ibcon#read 3, iclass 21, count 0 2006.285.15:10:52.00#ibcon#about to read 4, iclass 21, count 0 2006.285.15:10:52.00#ibcon#read 4, iclass 21, count 0 2006.285.15:10:52.00#ibcon#about to read 5, iclass 21, count 0 2006.285.15:10:52.00#ibcon#read 5, iclass 21, count 0 2006.285.15:10:52.00#ibcon#about to read 6, iclass 21, count 0 2006.285.15:10:52.00#ibcon#read 6, iclass 21, count 0 2006.285.15:10:52.00#ibcon#end of sib2, iclass 21, count 0 2006.285.15:10:52.00#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:10:52.00#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:10:52.00#ibcon#[27=BW32\r\n] 2006.285.15:10:52.00#ibcon#*before write, iclass 21, count 0 2006.285.15:10:52.00#ibcon#enter sib2, iclass 21, count 0 2006.285.15:10:52.00#ibcon#flushed, iclass 21, count 0 2006.285.15:10:52.00#ibcon#about to write, iclass 21, count 0 2006.285.15:10:52.00#ibcon#wrote, iclass 21, count 0 2006.285.15:10:52.00#ibcon#about to read 3, iclass 21, count 0 2006.285.15:10:52.03#ibcon#read 3, iclass 21, count 0 2006.285.15:10:52.03#ibcon#about to read 4, iclass 21, count 0 2006.285.15:10:52.03#ibcon#read 4, iclass 21, count 0 2006.285.15:10:52.03#ibcon#about to read 5, iclass 21, count 0 2006.285.15:10:52.03#ibcon#read 5, iclass 21, count 0 2006.285.15:10:52.03#ibcon#about to read 6, iclass 21, count 0 2006.285.15:10:52.03#ibcon#read 6, iclass 21, count 0 2006.285.15:10:52.03#ibcon#end of sib2, iclass 21, count 0 2006.285.15:10:52.03#ibcon#*after write, iclass 21, count 0 2006.285.15:10:52.03#ibcon#*before return 0, iclass 21, count 0 2006.285.15:10:52.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:10:52.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:10:52.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:10:52.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:10:52.03$setupk4/ifdk4 2006.285.15:10:52.03$ifdk4/lo= 2006.285.15:10:52.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.15:10:52.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.15:10:52.03$ifdk4/patch= 2006.285.15:10:52.27$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.15:10:52.27$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.15:10:52.27$setupk4/!*+20s 2006.285.15:10:59.68#abcon#<5=/03 1.9 3.7 19.16 921015.0\r\n> 2006.285.15:10:59.70#abcon#{5=INTERFACE CLEAR} 2006.285.15:10:59.76#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:11:05.58$setupk4/"tpicd 2006.285.15:11:05.58$setupk4/echo=off 2006.285.15:11:05.58$setupk4/xlog=off 2006.285.15:11:05.58:!2006.285.15:20:05 2006.285.15:11:08.13#trakl#Source acquired 2006.285.15:11:09.13#flagr#flagr/antenna,acquired 2006.285.15:20:05.02:preob 2006.285.15:20:06.14/onsource/TRACKING 2006.285.15:20:06.14:!2006.285.15:20:15 2006.285.15:20:15.01:"tape 2006.285.15:20:15.02:"st=record 2006.285.15:20:15.02:data_valid=on 2006.285.15:20:15.02:midob 2006.285.15:20:16.14/onsource/TRACKING 2006.285.15:20:16.14/wx/19.12,1015.0,92 2006.285.15:20:16.19/cable/+6.4998E-03 2006.285.15:20:17.28/va/01,07,usb,yes,32,35 2006.285.15:20:17.28/va/02,06,usb,yes,32,32 2006.285.15:20:17.28/va/03,07,usb,yes,31,33 2006.285.15:20:17.28/va/04,06,usb,yes,33,34 2006.285.15:20:17.28/va/05,03,usb,yes,33,33 2006.285.15:20:17.28/va/06,04,usb,yes,29,29 2006.285.15:20:17.28/va/07,04,usb,yes,30,30 2006.285.15:20:17.28/va/08,03,usb,yes,31,37 2006.285.15:20:17.51/valo/01,524.99,yes,locked 2006.285.15:20:17.51/valo/02,534.99,yes,locked 2006.285.15:20:17.51/valo/03,564.99,yes,locked 2006.285.15:20:17.51/valo/04,624.99,yes,locked 2006.285.15:20:17.51/valo/05,734.99,yes,locked 2006.285.15:20:17.51/valo/06,814.99,yes,locked 2006.285.15:20:17.52/valo/07,864.99,yes,locked 2006.285.15:20:17.52/valo/08,884.99,yes,locked 2006.285.15:20:18.60/vb/01,04,usb,yes,31,28 2006.285.15:20:18.60/vb/02,05,usb,yes,29,29 2006.285.15:20:18.60/vb/03,04,usb,yes,30,33 2006.285.15:20:18.60/vb/04,05,usb,yes,30,29 2006.285.15:20:18.60/vb/05,04,usb,yes,26,29 2006.285.15:20:18.60/vb/06,03,usb,yes,38,34 2006.285.15:20:18.60/vb/07,04,usb,yes,31,31 2006.285.15:20:18.60/vb/08,04,usb,yes,28,32 2006.285.15:20:18.83/vblo/01,629.99,yes,locked 2006.285.15:20:18.83/vblo/02,634.99,yes,locked 2006.285.15:20:18.83/vblo/03,649.99,yes,locked 2006.285.15:20:18.83/vblo/04,679.99,yes,locked 2006.285.15:20:18.83/vblo/05,709.99,yes,locked 2006.285.15:20:18.83/vblo/06,719.99,yes,locked 2006.285.15:20:18.83/vblo/07,734.99,yes,locked 2006.285.15:20:18.83/vblo/08,744.99,yes,locked 2006.285.15:20:18.98/vabw/8 2006.285.15:20:19.13/vbbw/8 2006.285.15:20:19.27/xfe/off,on,12.2 2006.285.15:20:19.65/ifatt/23,28,28,28 2006.285.15:20:20.07/fmout-gps/S +2.81E-07 2006.285.15:20:20.09:!2006.285.15:23:05 2006.285.15:23:05.01:data_valid=off 2006.285.15:23:05.02:"et 2006.285.15:23:05.02:!+3s 2006.285.15:23:08.04:"tape 2006.285.15:23:08.04:postob 2006.285.15:23:08.11/cable/+6.5012E-03 2006.285.15:23:08.11/wx/19.10,1015.0,92 2006.285.15:23:08.17/fmout-gps/S +2.82E-07 2006.285.15:23:08.17:scan_name=285-1529,jd0610,70 2006.285.15:23:08.17:source=2145+067,214805.46,065738.6,2000.0,ccw 2006.285.15:23:10.14#flagr#flagr/antenna,new-source 2006.285.15:23:10.15:checkk5 2006.285.15:23:10.67/chk_autoobs//k5ts1/ autoobs is running! 2006.285.15:23:11.03/chk_autoobs//k5ts2/ autoobs is running! 2006.285.15:23:11.69/chk_autoobs//k5ts3/ autoobs is running! 2006.285.15:23:12.06/chk_autoobs//k5ts4/ autoobs is running! 2006.285.15:23:12.54/chk_obsdata//k5ts1/T2851520??a.dat file size is correct (nominal:680MB, actual:676MB). 2006.285.15:23:12.91/chk_obsdata//k5ts2/T2851520??b.dat file size is correct (nominal:680MB, actual:676MB). 2006.285.15:23:13.37/chk_obsdata//k5ts3/T2851520??c.dat file size is correct (nominal:680MB, actual:676MB). 2006.285.15:23:13.81/chk_obsdata//k5ts4/T2851520??d.dat file size is correct (nominal:680MB, actual:676MB). 2006.285.15:23:14.66/k5log//k5ts1_log_newline 2006.285.15:23:15.39/k5log//k5ts2_log_newline 2006.285.15:23:16.14/k5log//k5ts3_log_newline 2006.285.15:23:16.88/k5log//k5ts4_log_newline 2006.285.15:23:16.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.15:23:16.90:setupk4=1 2006.285.15:23:16.90$setupk4/echo=on 2006.285.15:23:16.90$setupk4/pcalon 2006.285.15:23:16.90$pcalon/"no phase cal control is implemented here 2006.285.15:23:16.90$setupk4/"tpicd=stop 2006.285.15:23:16.90$setupk4/"rec=synch_on 2006.285.15:23:16.90$setupk4/"rec_mode=128 2006.285.15:23:16.90$setupk4/!* 2006.285.15:23:16.90$setupk4/recpk4 2006.285.15:23:16.90$recpk4/recpatch= 2006.285.15:23:16.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.15:23:16.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.15:23:16.90$setupk4/vck44 2006.285.15:23:16.90$vck44/valo=1,524.99 2006.285.15:23:16.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.15:23:16.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.15:23:16.90#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:16.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:23:16.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:23:16.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:23:16.90#ibcon#enter wrdev, iclass 25, count 0 2006.285.15:23:16.90#ibcon#first serial, iclass 25, count 0 2006.285.15:23:16.90#ibcon#enter sib2, iclass 25, count 0 2006.285.15:23:16.90#ibcon#flushed, iclass 25, count 0 2006.285.15:23:16.90#ibcon#about to write, iclass 25, count 0 2006.285.15:23:16.90#ibcon#wrote, iclass 25, count 0 2006.285.15:23:16.90#ibcon#about to read 3, iclass 25, count 0 2006.285.15:23:16.92#ibcon#read 3, iclass 25, count 0 2006.285.15:23:16.92#ibcon#about to read 4, iclass 25, count 0 2006.285.15:23:16.92#ibcon#read 4, iclass 25, count 0 2006.285.15:23:16.92#ibcon#about to read 5, iclass 25, count 0 2006.285.15:23:16.92#ibcon#read 5, iclass 25, count 0 2006.285.15:23:16.92#ibcon#about to read 6, iclass 25, count 0 2006.285.15:23:16.92#ibcon#read 6, iclass 25, count 0 2006.285.15:23:16.92#ibcon#end of sib2, iclass 25, count 0 2006.285.15:23:16.92#ibcon#*mode == 0, iclass 25, count 0 2006.285.15:23:16.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.15:23:16.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.15:23:16.92#ibcon#*before write, iclass 25, count 0 2006.285.15:23:16.92#ibcon#enter sib2, iclass 25, count 0 2006.285.15:23:16.92#ibcon#flushed, iclass 25, count 0 2006.285.15:23:16.92#ibcon#about to write, iclass 25, count 0 2006.285.15:23:16.92#ibcon#wrote, iclass 25, count 0 2006.285.15:23:16.92#ibcon#about to read 3, iclass 25, count 0 2006.285.15:23:16.97#ibcon#read 3, iclass 25, count 0 2006.285.15:23:16.97#ibcon#about to read 4, iclass 25, count 0 2006.285.15:23:16.97#ibcon#read 4, iclass 25, count 0 2006.285.15:23:16.97#ibcon#about to read 5, iclass 25, count 0 2006.285.15:23:16.97#ibcon#read 5, iclass 25, count 0 2006.285.15:23:16.97#ibcon#about to read 6, iclass 25, count 0 2006.285.15:23:16.97#ibcon#read 6, iclass 25, count 0 2006.285.15:23:16.97#ibcon#end of sib2, iclass 25, count 0 2006.285.15:23:16.97#ibcon#*after write, iclass 25, count 0 2006.285.15:23:16.97#ibcon#*before return 0, iclass 25, count 0 2006.285.15:23:16.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:23:16.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:23:16.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.15:23:16.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.15:23:16.97$vck44/va=1,7 2006.285.15:23:16.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.15:23:16.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.15:23:16.98#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:16.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:23:16.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:23:16.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:23:16.98#ibcon#enter wrdev, iclass 27, count 2 2006.285.15:23:16.98#ibcon#first serial, iclass 27, count 2 2006.285.15:23:16.98#ibcon#enter sib2, iclass 27, count 2 2006.285.15:23:16.98#ibcon#flushed, iclass 27, count 2 2006.285.15:23:16.98#ibcon#about to write, iclass 27, count 2 2006.285.15:23:16.98#ibcon#wrote, iclass 27, count 2 2006.285.15:23:16.98#ibcon#about to read 3, iclass 27, count 2 2006.285.15:23:16.99#ibcon#read 3, iclass 27, count 2 2006.285.15:23:16.99#ibcon#about to read 4, iclass 27, count 2 2006.285.15:23:16.99#ibcon#read 4, iclass 27, count 2 2006.285.15:23:16.99#ibcon#about to read 5, iclass 27, count 2 2006.285.15:23:16.99#ibcon#read 5, iclass 27, count 2 2006.285.15:23:16.99#ibcon#about to read 6, iclass 27, count 2 2006.285.15:23:16.99#ibcon#read 6, iclass 27, count 2 2006.285.15:23:16.99#ibcon#end of sib2, iclass 27, count 2 2006.285.15:23:16.99#ibcon#*mode == 0, iclass 27, count 2 2006.285.15:23:16.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.15:23:16.99#ibcon#[25=AT01-07\r\n] 2006.285.15:23:16.99#ibcon#*before write, iclass 27, count 2 2006.285.15:23:16.99#ibcon#enter sib2, iclass 27, count 2 2006.285.15:23:16.99#ibcon#flushed, iclass 27, count 2 2006.285.15:23:16.99#ibcon#about to write, iclass 27, count 2 2006.285.15:23:16.99#ibcon#wrote, iclass 27, count 2 2006.285.15:23:16.99#ibcon#about to read 3, iclass 27, count 2 2006.285.15:23:17.02#ibcon#read 3, iclass 27, count 2 2006.285.15:23:17.02#ibcon#about to read 4, iclass 27, count 2 2006.285.15:23:17.02#ibcon#read 4, iclass 27, count 2 2006.285.15:23:17.02#ibcon#about to read 5, iclass 27, count 2 2006.285.15:23:17.02#ibcon#read 5, iclass 27, count 2 2006.285.15:23:17.02#ibcon#about to read 6, iclass 27, count 2 2006.285.15:23:17.02#ibcon#read 6, iclass 27, count 2 2006.285.15:23:17.02#ibcon#end of sib2, iclass 27, count 2 2006.285.15:23:17.02#ibcon#*after write, iclass 27, count 2 2006.285.15:23:17.02#ibcon#*before return 0, iclass 27, count 2 2006.285.15:23:17.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:23:17.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:23:17.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.15:23:17.02#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:17.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:23:17.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:23:17.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:23:17.15#ibcon#enter wrdev, iclass 27, count 0 2006.285.15:23:17.15#ibcon#first serial, iclass 27, count 0 2006.285.15:23:17.15#ibcon#enter sib2, iclass 27, count 0 2006.285.15:23:17.15#ibcon#flushed, iclass 27, count 0 2006.285.15:23:17.15#ibcon#about to write, iclass 27, count 0 2006.285.15:23:17.15#ibcon#wrote, iclass 27, count 0 2006.285.15:23:17.15#ibcon#about to read 3, iclass 27, count 0 2006.285.15:23:17.16#ibcon#read 3, iclass 27, count 0 2006.285.15:23:17.16#ibcon#about to read 4, iclass 27, count 0 2006.285.15:23:17.16#ibcon#read 4, iclass 27, count 0 2006.285.15:23:17.16#ibcon#about to read 5, iclass 27, count 0 2006.285.15:23:17.16#ibcon#read 5, iclass 27, count 0 2006.285.15:23:17.16#ibcon#about to read 6, iclass 27, count 0 2006.285.15:23:17.16#ibcon#read 6, iclass 27, count 0 2006.285.15:23:17.16#ibcon#end of sib2, iclass 27, count 0 2006.285.15:23:17.16#ibcon#*mode == 0, iclass 27, count 0 2006.285.15:23:17.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.15:23:17.16#ibcon#[25=USB\r\n] 2006.285.15:23:17.16#ibcon#*before write, iclass 27, count 0 2006.285.15:23:17.16#ibcon#enter sib2, iclass 27, count 0 2006.285.15:23:17.16#ibcon#flushed, iclass 27, count 0 2006.285.15:23:17.16#ibcon#about to write, iclass 27, count 0 2006.285.15:23:17.16#ibcon#wrote, iclass 27, count 0 2006.285.15:23:17.16#ibcon#about to read 3, iclass 27, count 0 2006.285.15:23:17.19#ibcon#read 3, iclass 27, count 0 2006.285.15:23:17.19#ibcon#about to read 4, iclass 27, count 0 2006.285.15:23:17.19#ibcon#read 4, iclass 27, count 0 2006.285.15:23:17.19#ibcon#about to read 5, iclass 27, count 0 2006.285.15:23:17.19#ibcon#read 5, iclass 27, count 0 2006.285.15:23:17.19#ibcon#about to read 6, iclass 27, count 0 2006.285.15:23:17.20#ibcon#read 6, iclass 27, count 0 2006.285.15:23:17.20#ibcon#end of sib2, iclass 27, count 0 2006.285.15:23:17.20#ibcon#*after write, iclass 27, count 0 2006.285.15:23:17.20#ibcon#*before return 0, iclass 27, count 0 2006.285.15:23:17.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:23:17.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:23:17.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.15:23:17.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.15:23:17.20$vck44/valo=2,534.99 2006.285.15:23:17.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.15:23:17.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.15:23:17.20#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:17.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:23:17.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:23:17.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:23:17.20#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:23:17.20#ibcon#first serial, iclass 29, count 0 2006.285.15:23:17.20#ibcon#enter sib2, iclass 29, count 0 2006.285.15:23:17.20#ibcon#flushed, iclass 29, count 0 2006.285.15:23:17.20#ibcon#about to write, iclass 29, count 0 2006.285.15:23:17.20#ibcon#wrote, iclass 29, count 0 2006.285.15:23:17.20#ibcon#about to read 3, iclass 29, count 0 2006.285.15:23:17.21#ibcon#read 3, iclass 29, count 0 2006.285.15:23:17.21#ibcon#about to read 4, iclass 29, count 0 2006.285.15:23:17.21#ibcon#read 4, iclass 29, count 0 2006.285.15:23:17.21#ibcon#about to read 5, iclass 29, count 0 2006.285.15:23:17.21#ibcon#read 5, iclass 29, count 0 2006.285.15:23:17.21#ibcon#about to read 6, iclass 29, count 0 2006.285.15:23:17.21#ibcon#read 6, iclass 29, count 0 2006.285.15:23:17.21#ibcon#end of sib2, iclass 29, count 0 2006.285.15:23:17.21#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:23:17.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:23:17.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.15:23:17.21#ibcon#*before write, iclass 29, count 0 2006.285.15:23:17.21#ibcon#enter sib2, iclass 29, count 0 2006.285.15:23:17.21#ibcon#flushed, iclass 29, count 0 2006.285.15:23:17.21#ibcon#about to write, iclass 29, count 0 2006.285.15:23:17.21#ibcon#wrote, iclass 29, count 0 2006.285.15:23:17.21#ibcon#about to read 3, iclass 29, count 0 2006.285.15:23:17.25#ibcon#read 3, iclass 29, count 0 2006.285.15:23:17.25#ibcon#about to read 4, iclass 29, count 0 2006.285.15:23:17.25#ibcon#read 4, iclass 29, count 0 2006.285.15:23:17.25#ibcon#about to read 5, iclass 29, count 0 2006.285.15:23:17.25#ibcon#read 5, iclass 29, count 0 2006.285.15:23:17.25#ibcon#about to read 6, iclass 29, count 0 2006.285.15:23:17.25#ibcon#read 6, iclass 29, count 0 2006.285.15:23:17.25#ibcon#end of sib2, iclass 29, count 0 2006.285.15:23:17.25#ibcon#*after write, iclass 29, count 0 2006.285.15:23:17.25#ibcon#*before return 0, iclass 29, count 0 2006.285.15:23:17.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:23:17.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:23:17.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:23:17.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:23:17.25$vck44/va=2,6 2006.285.15:23:17.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.15:23:17.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.15:23:17.26#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:17.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:23:17.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:23:17.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:23:17.31#ibcon#enter wrdev, iclass 31, count 2 2006.285.15:23:17.31#ibcon#first serial, iclass 31, count 2 2006.285.15:23:17.31#ibcon#enter sib2, iclass 31, count 2 2006.285.15:23:17.31#ibcon#flushed, iclass 31, count 2 2006.285.15:23:17.31#ibcon#about to write, iclass 31, count 2 2006.285.15:23:17.31#ibcon#wrote, iclass 31, count 2 2006.285.15:23:17.31#ibcon#about to read 3, iclass 31, count 2 2006.285.15:23:17.33#ibcon#read 3, iclass 31, count 2 2006.285.15:23:17.33#ibcon#about to read 4, iclass 31, count 2 2006.285.15:23:17.33#ibcon#read 4, iclass 31, count 2 2006.285.15:23:17.33#ibcon#about to read 5, iclass 31, count 2 2006.285.15:23:17.33#ibcon#read 5, iclass 31, count 2 2006.285.15:23:17.33#ibcon#about to read 6, iclass 31, count 2 2006.285.15:23:17.33#ibcon#read 6, iclass 31, count 2 2006.285.15:23:17.33#ibcon#end of sib2, iclass 31, count 2 2006.285.15:23:17.33#ibcon#*mode == 0, iclass 31, count 2 2006.285.15:23:17.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.15:23:17.33#ibcon#[25=AT02-06\r\n] 2006.285.15:23:17.33#ibcon#*before write, iclass 31, count 2 2006.285.15:23:17.33#ibcon#enter sib2, iclass 31, count 2 2006.285.15:23:17.33#ibcon#flushed, iclass 31, count 2 2006.285.15:23:17.33#ibcon#about to write, iclass 31, count 2 2006.285.15:23:17.33#ibcon#wrote, iclass 31, count 2 2006.285.15:23:17.33#ibcon#about to read 3, iclass 31, count 2 2006.285.15:23:17.36#ibcon#read 3, iclass 31, count 2 2006.285.15:23:17.36#ibcon#about to read 4, iclass 31, count 2 2006.285.15:23:17.36#ibcon#read 4, iclass 31, count 2 2006.285.15:23:17.36#ibcon#about to read 5, iclass 31, count 2 2006.285.15:23:17.36#ibcon#read 5, iclass 31, count 2 2006.285.15:23:17.36#ibcon#about to read 6, iclass 31, count 2 2006.285.15:23:17.36#ibcon#read 6, iclass 31, count 2 2006.285.15:23:17.36#ibcon#end of sib2, iclass 31, count 2 2006.285.15:23:17.36#ibcon#*after write, iclass 31, count 2 2006.285.15:23:17.36#ibcon#*before return 0, iclass 31, count 2 2006.285.15:23:17.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:23:17.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:23:17.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.15:23:17.36#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:17.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:23:17.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:23:17.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:23:17.48#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:23:17.48#ibcon#first serial, iclass 31, count 0 2006.285.15:23:17.48#ibcon#enter sib2, iclass 31, count 0 2006.285.15:23:17.48#ibcon#flushed, iclass 31, count 0 2006.285.15:23:17.48#ibcon#about to write, iclass 31, count 0 2006.285.15:23:17.48#ibcon#wrote, iclass 31, count 0 2006.285.15:23:17.48#ibcon#about to read 3, iclass 31, count 0 2006.285.15:23:17.50#ibcon#read 3, iclass 31, count 0 2006.285.15:23:17.78#ibcon#about to read 4, iclass 31, count 0 2006.285.15:23:17.78#ibcon#read 4, iclass 31, count 0 2006.285.15:23:17.78#ibcon#about to read 5, iclass 31, count 0 2006.285.15:23:17.78#ibcon#read 5, iclass 31, count 0 2006.285.15:23:17.78#ibcon#about to read 6, iclass 31, count 0 2006.285.15:23:17.78#ibcon#read 6, iclass 31, count 0 2006.285.15:23:17.78#ibcon#end of sib2, iclass 31, count 0 2006.285.15:23:17.78#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:23:17.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:23:17.78#ibcon#[25=USB\r\n] 2006.285.15:23:17.78#ibcon#*before write, iclass 31, count 0 2006.285.15:23:17.78#ibcon#enter sib2, iclass 31, count 0 2006.285.15:23:17.78#ibcon#flushed, iclass 31, count 0 2006.285.15:23:17.78#ibcon#about to write, iclass 31, count 0 2006.285.15:23:17.78#ibcon#wrote, iclass 31, count 0 2006.285.15:23:17.78#ibcon#about to read 3, iclass 31, count 0 2006.285.15:23:17.81#ibcon#read 3, iclass 31, count 0 2006.285.15:23:17.81#ibcon#about to read 4, iclass 31, count 0 2006.285.15:23:17.81#ibcon#read 4, iclass 31, count 0 2006.285.15:23:17.81#ibcon#about to read 5, iclass 31, count 0 2006.285.15:23:17.81#ibcon#read 5, iclass 31, count 0 2006.285.15:23:17.81#ibcon#about to read 6, iclass 31, count 0 2006.285.15:23:17.81#ibcon#read 6, iclass 31, count 0 2006.285.15:23:17.81#ibcon#end of sib2, iclass 31, count 0 2006.285.15:23:17.81#ibcon#*after write, iclass 31, count 0 2006.285.15:23:17.81#ibcon#*before return 0, iclass 31, count 0 2006.285.15:23:17.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:23:17.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:23:17.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:23:17.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:23:17.81$vck44/valo=3,564.99 2006.285.15:23:17.82#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.15:23:17.82#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.15:23:17.82#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:17.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:23:17.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:23:17.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:23:17.82#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:23:17.82#ibcon#first serial, iclass 33, count 0 2006.285.15:23:17.82#ibcon#enter sib2, iclass 33, count 0 2006.285.15:23:17.82#ibcon#flushed, iclass 33, count 0 2006.285.15:23:17.82#ibcon#about to write, iclass 33, count 0 2006.285.15:23:17.82#ibcon#wrote, iclass 33, count 0 2006.285.15:23:17.82#ibcon#about to read 3, iclass 33, count 0 2006.285.15:23:17.83#ibcon#read 3, iclass 33, count 0 2006.285.15:23:17.83#ibcon#about to read 4, iclass 33, count 0 2006.285.15:23:17.83#ibcon#read 4, iclass 33, count 0 2006.285.15:23:17.83#ibcon#about to read 5, iclass 33, count 0 2006.285.15:23:17.83#ibcon#read 5, iclass 33, count 0 2006.285.15:23:17.83#ibcon#about to read 6, iclass 33, count 0 2006.285.15:23:17.83#ibcon#read 6, iclass 33, count 0 2006.285.15:23:17.83#ibcon#end of sib2, iclass 33, count 0 2006.285.15:23:17.83#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:23:17.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:23:17.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.15:23:17.83#ibcon#*before write, iclass 33, count 0 2006.285.15:23:17.83#ibcon#enter sib2, iclass 33, count 0 2006.285.15:23:17.83#ibcon#flushed, iclass 33, count 0 2006.285.15:23:17.83#ibcon#about to write, iclass 33, count 0 2006.285.15:23:17.83#ibcon#wrote, iclass 33, count 0 2006.285.15:23:17.83#ibcon#about to read 3, iclass 33, count 0 2006.285.15:23:17.87#ibcon#read 3, iclass 33, count 0 2006.285.15:23:17.87#ibcon#about to read 4, iclass 33, count 0 2006.285.15:23:17.87#ibcon#read 4, iclass 33, count 0 2006.285.15:23:17.87#ibcon#about to read 5, iclass 33, count 0 2006.285.15:23:17.87#ibcon#read 5, iclass 33, count 0 2006.285.15:23:17.87#ibcon#about to read 6, iclass 33, count 0 2006.285.15:23:17.87#ibcon#read 6, iclass 33, count 0 2006.285.15:23:17.87#ibcon#end of sib2, iclass 33, count 0 2006.285.15:23:17.87#ibcon#*after write, iclass 33, count 0 2006.285.15:23:17.87#ibcon#*before return 0, iclass 33, count 0 2006.285.15:23:17.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:23:17.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:23:17.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:23:17.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:23:17.87$vck44/va=3,7 2006.285.15:23:17.88#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.15:23:17.88#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.15:23:17.88#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:17.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:23:17.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:23:17.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:23:17.92#ibcon#enter wrdev, iclass 35, count 2 2006.285.15:23:17.92#ibcon#first serial, iclass 35, count 2 2006.285.15:23:17.92#ibcon#enter sib2, iclass 35, count 2 2006.285.15:23:17.92#ibcon#flushed, iclass 35, count 2 2006.285.15:23:17.92#ibcon#about to write, iclass 35, count 2 2006.285.15:23:17.92#ibcon#wrote, iclass 35, count 2 2006.285.15:23:17.92#ibcon#about to read 3, iclass 35, count 2 2006.285.15:23:17.94#ibcon#read 3, iclass 35, count 2 2006.285.15:23:17.94#ibcon#about to read 4, iclass 35, count 2 2006.285.15:23:17.94#ibcon#read 4, iclass 35, count 2 2006.285.15:23:17.94#ibcon#about to read 5, iclass 35, count 2 2006.285.15:23:17.94#ibcon#read 5, iclass 35, count 2 2006.285.15:23:17.94#ibcon#about to read 6, iclass 35, count 2 2006.285.15:23:17.94#ibcon#read 6, iclass 35, count 2 2006.285.15:23:17.94#ibcon#end of sib2, iclass 35, count 2 2006.285.15:23:17.94#ibcon#*mode == 0, iclass 35, count 2 2006.285.15:23:17.94#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.15:23:17.94#ibcon#[25=AT03-07\r\n] 2006.285.15:23:17.94#ibcon#*before write, iclass 35, count 2 2006.285.15:23:17.94#ibcon#enter sib2, iclass 35, count 2 2006.285.15:23:17.94#ibcon#flushed, iclass 35, count 2 2006.285.15:23:17.94#ibcon#about to write, iclass 35, count 2 2006.285.15:23:17.94#ibcon#wrote, iclass 35, count 2 2006.285.15:23:17.94#ibcon#about to read 3, iclass 35, count 2 2006.285.15:23:17.97#ibcon#read 3, iclass 35, count 2 2006.285.15:23:17.97#ibcon#about to read 4, iclass 35, count 2 2006.285.15:23:17.97#ibcon#read 4, iclass 35, count 2 2006.285.15:23:17.97#ibcon#about to read 5, iclass 35, count 2 2006.285.15:23:17.97#ibcon#read 5, iclass 35, count 2 2006.285.15:23:17.97#ibcon#about to read 6, iclass 35, count 2 2006.285.15:23:17.97#ibcon#read 6, iclass 35, count 2 2006.285.15:23:17.97#ibcon#end of sib2, iclass 35, count 2 2006.285.15:23:17.97#ibcon#*after write, iclass 35, count 2 2006.285.15:23:17.97#ibcon#*before return 0, iclass 35, count 2 2006.285.15:23:17.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:23:17.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:23:17.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.15:23:17.97#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:17.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:23:18.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:23:18.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:23:18.09#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:23:18.09#ibcon#first serial, iclass 35, count 0 2006.285.15:23:18.09#ibcon#enter sib2, iclass 35, count 0 2006.285.15:23:18.09#ibcon#flushed, iclass 35, count 0 2006.285.15:23:18.09#ibcon#about to write, iclass 35, count 0 2006.285.15:23:18.09#ibcon#wrote, iclass 35, count 0 2006.285.15:23:18.09#ibcon#about to read 3, iclass 35, count 0 2006.285.15:23:18.11#ibcon#read 3, iclass 35, count 0 2006.285.15:23:18.11#ibcon#about to read 4, iclass 35, count 0 2006.285.15:23:18.11#ibcon#read 4, iclass 35, count 0 2006.285.15:23:18.11#ibcon#about to read 5, iclass 35, count 0 2006.285.15:23:18.11#ibcon#read 5, iclass 35, count 0 2006.285.15:23:18.11#ibcon#about to read 6, iclass 35, count 0 2006.285.15:23:18.11#ibcon#read 6, iclass 35, count 0 2006.285.15:23:18.11#ibcon#end of sib2, iclass 35, count 0 2006.285.15:23:18.11#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:23:18.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:23:18.11#ibcon#[25=USB\r\n] 2006.285.15:23:18.11#ibcon#*before write, iclass 35, count 0 2006.285.15:23:18.11#ibcon#enter sib2, iclass 35, count 0 2006.285.15:23:18.11#ibcon#flushed, iclass 35, count 0 2006.285.15:23:18.11#ibcon#about to write, iclass 35, count 0 2006.285.15:23:18.11#ibcon#wrote, iclass 35, count 0 2006.285.15:23:18.11#ibcon#about to read 3, iclass 35, count 0 2006.285.15:23:18.14#ibcon#read 3, iclass 35, count 0 2006.285.15:23:18.14#ibcon#about to read 4, iclass 35, count 0 2006.285.15:23:18.54#ibcon#read 4, iclass 35, count 0 2006.285.15:23:18.54#ibcon#about to read 5, iclass 35, count 0 2006.285.15:23:18.54#ibcon#read 5, iclass 35, count 0 2006.285.15:23:18.54#ibcon#about to read 6, iclass 35, count 0 2006.285.15:23:18.54#ibcon#read 6, iclass 35, count 0 2006.285.15:23:18.54#ibcon#end of sib2, iclass 35, count 0 2006.285.15:23:18.54#ibcon#*after write, iclass 35, count 0 2006.285.15:23:18.54#ibcon#*before return 0, iclass 35, count 0 2006.285.15:23:18.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:23:18.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:23:18.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:23:18.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:23:18.54$vck44/valo=4,624.99 2006.285.15:23:18.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.15:23:18.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.15:23:18.54#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:18.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:23:18.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:23:18.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:23:18.54#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:23:18.54#ibcon#first serial, iclass 37, count 0 2006.285.15:23:18.54#ibcon#enter sib2, iclass 37, count 0 2006.285.15:23:18.54#ibcon#flushed, iclass 37, count 0 2006.285.15:23:18.54#ibcon#about to write, iclass 37, count 0 2006.285.15:23:18.54#ibcon#wrote, iclass 37, count 0 2006.285.15:23:18.54#ibcon#about to read 3, iclass 37, count 0 2006.285.15:23:18.55#ibcon#read 3, iclass 37, count 0 2006.285.15:23:18.55#ibcon#about to read 4, iclass 37, count 0 2006.285.15:23:18.55#ibcon#read 4, iclass 37, count 0 2006.285.15:23:18.55#ibcon#about to read 5, iclass 37, count 0 2006.285.15:23:18.55#ibcon#read 5, iclass 37, count 0 2006.285.15:23:18.55#ibcon#about to read 6, iclass 37, count 0 2006.285.15:23:18.55#ibcon#read 6, iclass 37, count 0 2006.285.15:23:18.55#ibcon#end of sib2, iclass 37, count 0 2006.285.15:23:18.55#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:23:18.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:23:18.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.15:23:18.55#ibcon#*before write, iclass 37, count 0 2006.285.15:23:18.55#ibcon#enter sib2, iclass 37, count 0 2006.285.15:23:18.55#ibcon#flushed, iclass 37, count 0 2006.285.15:23:18.55#ibcon#about to write, iclass 37, count 0 2006.285.15:23:18.55#ibcon#wrote, iclass 37, count 0 2006.285.15:23:18.55#ibcon#about to read 3, iclass 37, count 0 2006.285.15:23:18.59#ibcon#read 3, iclass 37, count 0 2006.285.15:23:18.59#ibcon#about to read 4, iclass 37, count 0 2006.285.15:23:18.59#ibcon#read 4, iclass 37, count 0 2006.285.15:23:18.59#ibcon#about to read 5, iclass 37, count 0 2006.285.15:23:18.59#ibcon#read 5, iclass 37, count 0 2006.285.15:23:18.59#ibcon#about to read 6, iclass 37, count 0 2006.285.15:23:18.59#ibcon#read 6, iclass 37, count 0 2006.285.15:23:18.59#ibcon#end of sib2, iclass 37, count 0 2006.285.15:23:18.59#ibcon#*after write, iclass 37, count 0 2006.285.15:23:18.59#ibcon#*before return 0, iclass 37, count 0 2006.285.15:23:18.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:23:18.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:23:18.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:23:18.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:23:18.59$vck44/va=4,6 2006.285.15:23:18.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.15:23:18.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.15:23:18.60#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:18.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:23:18.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:23:18.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:23:18.65#ibcon#enter wrdev, iclass 39, count 2 2006.285.15:23:18.65#ibcon#first serial, iclass 39, count 2 2006.285.15:23:18.65#ibcon#enter sib2, iclass 39, count 2 2006.285.15:23:18.65#ibcon#flushed, iclass 39, count 2 2006.285.15:23:18.65#ibcon#about to write, iclass 39, count 2 2006.285.15:23:18.65#ibcon#wrote, iclass 39, count 2 2006.285.15:23:18.65#ibcon#about to read 3, iclass 39, count 2 2006.285.15:23:18.67#ibcon#read 3, iclass 39, count 2 2006.285.15:23:18.67#ibcon#about to read 4, iclass 39, count 2 2006.285.15:23:18.67#ibcon#read 4, iclass 39, count 2 2006.285.15:23:18.67#ibcon#about to read 5, iclass 39, count 2 2006.285.15:23:18.67#ibcon#read 5, iclass 39, count 2 2006.285.15:23:18.67#ibcon#about to read 6, iclass 39, count 2 2006.285.15:23:18.67#ibcon#read 6, iclass 39, count 2 2006.285.15:23:18.67#ibcon#end of sib2, iclass 39, count 2 2006.285.15:23:18.67#ibcon#*mode == 0, iclass 39, count 2 2006.285.15:23:18.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.15:23:18.67#ibcon#[25=AT04-06\r\n] 2006.285.15:23:18.67#ibcon#*before write, iclass 39, count 2 2006.285.15:23:18.67#ibcon#enter sib2, iclass 39, count 2 2006.285.15:23:18.67#ibcon#flushed, iclass 39, count 2 2006.285.15:23:18.67#ibcon#about to write, iclass 39, count 2 2006.285.15:23:18.67#ibcon#wrote, iclass 39, count 2 2006.285.15:23:18.67#ibcon#about to read 3, iclass 39, count 2 2006.285.15:23:18.70#ibcon#read 3, iclass 39, count 2 2006.285.15:23:18.70#ibcon#about to read 4, iclass 39, count 2 2006.285.15:23:18.70#ibcon#read 4, iclass 39, count 2 2006.285.15:23:18.70#ibcon#about to read 5, iclass 39, count 2 2006.285.15:23:18.70#ibcon#read 5, iclass 39, count 2 2006.285.15:23:18.70#ibcon#about to read 6, iclass 39, count 2 2006.285.15:23:18.70#ibcon#read 6, iclass 39, count 2 2006.285.15:23:18.70#ibcon#end of sib2, iclass 39, count 2 2006.285.15:23:18.70#ibcon#*after write, iclass 39, count 2 2006.285.15:23:18.70#ibcon#*before return 0, iclass 39, count 2 2006.285.15:23:18.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:23:18.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:23:18.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.15:23:18.70#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:18.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:23:18.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:23:18.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:23:18.82#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:23:18.82#ibcon#first serial, iclass 39, count 0 2006.285.15:23:18.82#ibcon#enter sib2, iclass 39, count 0 2006.285.15:23:18.82#ibcon#flushed, iclass 39, count 0 2006.285.15:23:18.82#ibcon#about to write, iclass 39, count 0 2006.285.15:23:18.82#ibcon#wrote, iclass 39, count 0 2006.285.15:23:18.82#ibcon#about to read 3, iclass 39, count 0 2006.285.15:23:18.84#ibcon#read 3, iclass 39, count 0 2006.285.15:23:18.84#ibcon#about to read 4, iclass 39, count 0 2006.285.15:23:18.84#ibcon#read 4, iclass 39, count 0 2006.285.15:23:18.84#ibcon#about to read 5, iclass 39, count 0 2006.285.15:23:18.84#ibcon#read 5, iclass 39, count 0 2006.285.15:23:18.84#ibcon#about to read 6, iclass 39, count 0 2006.285.15:23:18.84#ibcon#read 6, iclass 39, count 0 2006.285.15:23:18.84#ibcon#end of sib2, iclass 39, count 0 2006.285.15:23:18.84#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:23:18.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:23:18.84#ibcon#[25=USB\r\n] 2006.285.15:23:18.84#ibcon#*before write, iclass 39, count 0 2006.285.15:23:18.84#ibcon#enter sib2, iclass 39, count 0 2006.285.15:23:18.84#ibcon#flushed, iclass 39, count 0 2006.285.15:23:18.84#ibcon#about to write, iclass 39, count 0 2006.285.15:23:18.84#ibcon#wrote, iclass 39, count 0 2006.285.15:23:18.84#ibcon#about to read 3, iclass 39, count 0 2006.285.15:23:18.87#ibcon#read 3, iclass 39, count 0 2006.285.15:23:18.87#ibcon#about to read 4, iclass 39, count 0 2006.285.15:23:18.87#ibcon#read 4, iclass 39, count 0 2006.285.15:23:18.87#ibcon#about to read 5, iclass 39, count 0 2006.285.15:23:18.87#ibcon#read 5, iclass 39, count 0 2006.285.15:23:18.87#ibcon#about to read 6, iclass 39, count 0 2006.285.15:23:18.87#ibcon#read 6, iclass 39, count 0 2006.285.15:23:18.87#ibcon#end of sib2, iclass 39, count 0 2006.285.15:23:18.87#ibcon#*after write, iclass 39, count 0 2006.285.15:23:18.87#ibcon#*before return 0, iclass 39, count 0 2006.285.15:23:18.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:23:18.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:23:18.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:23:18.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:23:18.87$vck44/valo=5,734.99 2006.285.15:23:18.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.15:23:18.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.15:23:18.88#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:18.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:23:18.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:23:18.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:23:18.88#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:23:18.88#ibcon#first serial, iclass 3, count 0 2006.285.15:23:18.88#ibcon#enter sib2, iclass 3, count 0 2006.285.15:23:18.88#ibcon#flushed, iclass 3, count 0 2006.285.15:23:18.88#ibcon#about to write, iclass 3, count 0 2006.285.15:23:18.88#ibcon#wrote, iclass 3, count 0 2006.285.15:23:18.88#ibcon#about to read 3, iclass 3, count 0 2006.285.15:23:18.89#ibcon#read 3, iclass 3, count 0 2006.285.15:23:18.89#ibcon#about to read 4, iclass 3, count 0 2006.285.15:23:18.89#ibcon#read 4, iclass 3, count 0 2006.285.15:23:18.89#ibcon#about to read 5, iclass 3, count 0 2006.285.15:23:18.89#ibcon#read 5, iclass 3, count 0 2006.285.15:23:18.89#ibcon#about to read 6, iclass 3, count 0 2006.285.15:23:18.89#ibcon#read 6, iclass 3, count 0 2006.285.15:23:18.89#ibcon#end of sib2, iclass 3, count 0 2006.285.15:23:18.89#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:23:18.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:23:18.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.15:23:18.89#ibcon#*before write, iclass 3, count 0 2006.285.15:23:18.89#ibcon#enter sib2, iclass 3, count 0 2006.285.15:23:18.89#ibcon#flushed, iclass 3, count 0 2006.285.15:23:18.89#ibcon#about to write, iclass 3, count 0 2006.285.15:23:18.89#ibcon#wrote, iclass 3, count 0 2006.285.15:23:18.89#ibcon#about to read 3, iclass 3, count 0 2006.285.15:23:18.93#ibcon#read 3, iclass 3, count 0 2006.285.15:23:18.93#ibcon#about to read 4, iclass 3, count 0 2006.285.15:23:18.93#ibcon#read 4, iclass 3, count 0 2006.285.15:23:18.93#ibcon#about to read 5, iclass 3, count 0 2006.285.15:23:18.93#ibcon#read 5, iclass 3, count 0 2006.285.15:23:18.93#ibcon#about to read 6, iclass 3, count 0 2006.285.15:23:18.93#ibcon#read 6, iclass 3, count 0 2006.285.15:23:18.93#ibcon#end of sib2, iclass 3, count 0 2006.285.15:23:18.93#ibcon#*after write, iclass 3, count 0 2006.285.15:23:18.93#ibcon#*before return 0, iclass 3, count 0 2006.285.15:23:18.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:23:18.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:23:18.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:23:18.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:23:18.93$vck44/va=5,3 2006.285.15:23:18.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.15:23:18.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.15:23:18.94#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:18.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:23:18.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:23:18.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:23:18.98#ibcon#enter wrdev, iclass 5, count 2 2006.285.15:23:18.98#ibcon#first serial, iclass 5, count 2 2006.285.15:23:18.98#ibcon#enter sib2, iclass 5, count 2 2006.285.15:23:18.98#ibcon#flushed, iclass 5, count 2 2006.285.15:23:18.98#ibcon#about to write, iclass 5, count 2 2006.285.15:23:18.98#ibcon#wrote, iclass 5, count 2 2006.285.15:23:18.98#ibcon#about to read 3, iclass 5, count 2 2006.285.15:23:19.00#ibcon#read 3, iclass 5, count 2 2006.285.15:23:19.00#ibcon#about to read 4, iclass 5, count 2 2006.285.15:23:19.00#ibcon#read 4, iclass 5, count 2 2006.285.15:23:19.00#ibcon#about to read 5, iclass 5, count 2 2006.285.15:23:19.00#ibcon#read 5, iclass 5, count 2 2006.285.15:23:19.00#ibcon#about to read 6, iclass 5, count 2 2006.285.15:23:19.00#ibcon#read 6, iclass 5, count 2 2006.285.15:23:19.00#ibcon#end of sib2, iclass 5, count 2 2006.285.15:23:19.00#ibcon#*mode == 0, iclass 5, count 2 2006.285.15:23:19.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.15:23:19.00#ibcon#[25=AT05-03\r\n] 2006.285.15:23:19.00#ibcon#*before write, iclass 5, count 2 2006.285.15:23:19.00#ibcon#enter sib2, iclass 5, count 2 2006.285.15:23:19.00#ibcon#flushed, iclass 5, count 2 2006.285.15:23:19.00#ibcon#about to write, iclass 5, count 2 2006.285.15:23:19.00#ibcon#wrote, iclass 5, count 2 2006.285.15:23:19.00#ibcon#about to read 3, iclass 5, count 2 2006.285.15:23:19.03#ibcon#read 3, iclass 5, count 2 2006.285.15:23:19.03#ibcon#about to read 4, iclass 5, count 2 2006.285.15:23:19.03#ibcon#read 4, iclass 5, count 2 2006.285.15:23:19.03#ibcon#about to read 5, iclass 5, count 2 2006.285.15:23:19.03#ibcon#read 5, iclass 5, count 2 2006.285.15:23:19.03#ibcon#about to read 6, iclass 5, count 2 2006.285.15:23:19.03#ibcon#read 6, iclass 5, count 2 2006.285.15:23:19.03#ibcon#end of sib2, iclass 5, count 2 2006.285.15:23:19.03#ibcon#*after write, iclass 5, count 2 2006.285.15:23:19.03#ibcon#*before return 0, iclass 5, count 2 2006.285.15:23:19.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:23:19.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:23:19.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.15:23:19.03#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:19.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:23:19.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:23:19.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:23:19.15#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:23:19.15#ibcon#first serial, iclass 5, count 0 2006.285.15:23:19.15#ibcon#enter sib2, iclass 5, count 0 2006.285.15:23:19.15#ibcon#flushed, iclass 5, count 0 2006.285.15:23:19.15#ibcon#about to write, iclass 5, count 0 2006.285.15:23:19.15#ibcon#wrote, iclass 5, count 0 2006.285.15:23:19.15#ibcon#about to read 3, iclass 5, count 0 2006.285.15:23:19.17#ibcon#read 3, iclass 5, count 0 2006.285.15:23:19.17#ibcon#about to read 4, iclass 5, count 0 2006.285.15:23:19.17#ibcon#read 4, iclass 5, count 0 2006.285.15:23:19.17#ibcon#about to read 5, iclass 5, count 0 2006.285.15:23:19.17#ibcon#read 5, iclass 5, count 0 2006.285.15:23:19.17#ibcon#about to read 6, iclass 5, count 0 2006.285.15:23:19.17#ibcon#read 6, iclass 5, count 0 2006.285.15:23:19.17#ibcon#end of sib2, iclass 5, count 0 2006.285.15:23:19.17#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:23:19.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:23:19.17#ibcon#[25=USB\r\n] 2006.285.15:23:19.17#ibcon#*before write, iclass 5, count 0 2006.285.15:23:19.17#ibcon#enter sib2, iclass 5, count 0 2006.285.15:23:19.17#ibcon#flushed, iclass 5, count 0 2006.285.15:23:19.17#ibcon#about to write, iclass 5, count 0 2006.285.15:23:19.17#ibcon#wrote, iclass 5, count 0 2006.285.15:23:19.17#ibcon#about to read 3, iclass 5, count 0 2006.285.15:23:19.20#ibcon#read 3, iclass 5, count 0 2006.285.15:23:19.20#ibcon#about to read 4, iclass 5, count 0 2006.285.15:23:19.20#ibcon#read 4, iclass 5, count 0 2006.285.15:23:19.20#ibcon#about to read 5, iclass 5, count 0 2006.285.15:23:19.20#ibcon#read 5, iclass 5, count 0 2006.285.15:23:19.20#ibcon#about to read 6, iclass 5, count 0 2006.285.15:23:19.20#ibcon#read 6, iclass 5, count 0 2006.285.15:23:19.20#ibcon#end of sib2, iclass 5, count 0 2006.285.15:23:19.20#ibcon#*after write, iclass 5, count 0 2006.285.15:23:19.20#ibcon#*before return 0, iclass 5, count 0 2006.285.15:23:19.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:23:19.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:23:19.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:23:19.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:23:19.20$vck44/valo=6,814.99 2006.285.15:23:19.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.15:23:19.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.15:23:19.21#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:19.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:23:19.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:23:19.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:23:19.21#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:23:19.21#ibcon#first serial, iclass 7, count 0 2006.285.15:23:19.21#ibcon#enter sib2, iclass 7, count 0 2006.285.15:23:19.21#ibcon#flushed, iclass 7, count 0 2006.285.15:23:19.21#ibcon#about to write, iclass 7, count 0 2006.285.15:23:19.21#ibcon#wrote, iclass 7, count 0 2006.285.15:23:19.21#ibcon#about to read 3, iclass 7, count 0 2006.285.15:23:19.22#ibcon#read 3, iclass 7, count 0 2006.285.15:23:19.22#ibcon#about to read 4, iclass 7, count 0 2006.285.15:23:19.22#ibcon#read 4, iclass 7, count 0 2006.285.15:23:19.22#ibcon#about to read 5, iclass 7, count 0 2006.285.15:23:19.22#ibcon#read 5, iclass 7, count 0 2006.285.15:23:19.22#ibcon#about to read 6, iclass 7, count 0 2006.285.15:23:19.22#ibcon#read 6, iclass 7, count 0 2006.285.15:23:19.22#ibcon#end of sib2, iclass 7, count 0 2006.285.15:23:19.22#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:23:19.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:23:19.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.15:23:19.22#ibcon#*before write, iclass 7, count 0 2006.285.15:23:19.22#ibcon#enter sib2, iclass 7, count 0 2006.285.15:23:19.22#ibcon#flushed, iclass 7, count 0 2006.285.15:23:19.22#ibcon#about to write, iclass 7, count 0 2006.285.15:23:19.22#ibcon#wrote, iclass 7, count 0 2006.285.15:23:19.22#ibcon#about to read 3, iclass 7, count 0 2006.285.15:23:19.26#ibcon#read 3, iclass 7, count 0 2006.285.15:23:19.26#ibcon#about to read 4, iclass 7, count 0 2006.285.15:23:19.26#ibcon#read 4, iclass 7, count 0 2006.285.15:23:19.26#ibcon#about to read 5, iclass 7, count 0 2006.285.15:23:19.26#ibcon#read 5, iclass 7, count 0 2006.285.15:23:19.26#ibcon#about to read 6, iclass 7, count 0 2006.285.15:23:19.26#ibcon#read 6, iclass 7, count 0 2006.285.15:23:19.26#ibcon#end of sib2, iclass 7, count 0 2006.285.15:23:19.26#ibcon#*after write, iclass 7, count 0 2006.285.15:23:19.26#ibcon#*before return 0, iclass 7, count 0 2006.285.15:23:19.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:23:19.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:23:19.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:23:19.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:23:19.26$vck44/va=6,4 2006.285.15:23:19.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.15:23:19.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.15:23:19.27#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:19.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:23:19.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:23:19.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:23:19.31#ibcon#enter wrdev, iclass 11, count 2 2006.285.15:23:19.31#ibcon#first serial, iclass 11, count 2 2006.285.15:23:19.31#ibcon#enter sib2, iclass 11, count 2 2006.285.15:23:19.31#ibcon#flushed, iclass 11, count 2 2006.285.15:23:19.31#ibcon#about to write, iclass 11, count 2 2006.285.15:23:19.31#ibcon#wrote, iclass 11, count 2 2006.285.15:23:19.31#ibcon#about to read 3, iclass 11, count 2 2006.285.15:23:19.33#ibcon#read 3, iclass 11, count 2 2006.285.15:23:19.33#ibcon#about to read 4, iclass 11, count 2 2006.285.15:23:19.33#ibcon#read 4, iclass 11, count 2 2006.285.15:23:19.33#ibcon#about to read 5, iclass 11, count 2 2006.285.15:23:19.33#ibcon#read 5, iclass 11, count 2 2006.285.15:23:19.33#ibcon#about to read 6, iclass 11, count 2 2006.285.15:23:19.33#ibcon#read 6, iclass 11, count 2 2006.285.15:23:19.33#ibcon#end of sib2, iclass 11, count 2 2006.285.15:23:19.33#ibcon#*mode == 0, iclass 11, count 2 2006.285.15:23:19.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.15:23:19.33#ibcon#[25=AT06-04\r\n] 2006.285.15:23:19.33#ibcon#*before write, iclass 11, count 2 2006.285.15:23:19.33#ibcon#enter sib2, iclass 11, count 2 2006.285.15:23:19.33#ibcon#flushed, iclass 11, count 2 2006.285.15:23:19.33#ibcon#about to write, iclass 11, count 2 2006.285.15:23:19.33#ibcon#wrote, iclass 11, count 2 2006.285.15:23:19.33#ibcon#about to read 3, iclass 11, count 2 2006.285.15:23:19.36#ibcon#read 3, iclass 11, count 2 2006.285.15:23:19.36#ibcon#about to read 4, iclass 11, count 2 2006.285.15:23:19.36#ibcon#read 4, iclass 11, count 2 2006.285.15:23:19.36#ibcon#about to read 5, iclass 11, count 2 2006.285.15:23:19.36#ibcon#read 5, iclass 11, count 2 2006.285.15:23:19.36#ibcon#about to read 6, iclass 11, count 2 2006.285.15:23:19.36#ibcon#read 6, iclass 11, count 2 2006.285.15:23:19.36#ibcon#end of sib2, iclass 11, count 2 2006.285.15:23:19.36#ibcon#*after write, iclass 11, count 2 2006.285.15:23:19.36#ibcon#*before return 0, iclass 11, count 2 2006.285.15:23:19.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:23:19.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:23:19.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.15:23:19.36#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:19.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:23:19.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:23:19.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:23:19.48#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:23:19.48#ibcon#first serial, iclass 11, count 0 2006.285.15:23:19.48#ibcon#enter sib2, iclass 11, count 0 2006.285.15:23:19.48#ibcon#flushed, iclass 11, count 0 2006.285.15:23:19.48#ibcon#about to write, iclass 11, count 0 2006.285.15:23:19.48#ibcon#wrote, iclass 11, count 0 2006.285.15:23:19.48#ibcon#about to read 3, iclass 11, count 0 2006.285.15:23:19.50#ibcon#read 3, iclass 11, count 0 2006.285.15:23:19.50#ibcon#about to read 4, iclass 11, count 0 2006.285.15:23:19.50#ibcon#read 4, iclass 11, count 0 2006.285.15:23:19.50#ibcon#about to read 5, iclass 11, count 0 2006.285.15:23:19.50#ibcon#read 5, iclass 11, count 0 2006.285.15:23:19.50#ibcon#about to read 6, iclass 11, count 0 2006.285.15:23:19.50#ibcon#read 6, iclass 11, count 0 2006.285.15:23:19.50#ibcon#end of sib2, iclass 11, count 0 2006.285.15:23:19.50#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:23:19.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:23:19.50#ibcon#[25=USB\r\n] 2006.285.15:23:19.50#ibcon#*before write, iclass 11, count 0 2006.285.15:23:19.50#ibcon#enter sib2, iclass 11, count 0 2006.285.15:23:19.50#ibcon#flushed, iclass 11, count 0 2006.285.15:23:19.50#ibcon#about to write, iclass 11, count 0 2006.285.15:23:19.50#ibcon#wrote, iclass 11, count 0 2006.285.15:23:19.50#ibcon#about to read 3, iclass 11, count 0 2006.285.15:23:19.53#ibcon#read 3, iclass 11, count 0 2006.285.15:23:19.56#ibcon#about to read 4, iclass 11, count 0 2006.285.15:23:19.56#ibcon#read 4, iclass 11, count 0 2006.285.15:23:19.56#ibcon#about to read 5, iclass 11, count 0 2006.285.15:23:19.56#ibcon#read 5, iclass 11, count 0 2006.285.15:23:19.56#ibcon#about to read 6, iclass 11, count 0 2006.285.15:23:19.56#ibcon#read 6, iclass 11, count 0 2006.285.15:23:19.56#ibcon#end of sib2, iclass 11, count 0 2006.285.15:23:19.56#ibcon#*after write, iclass 11, count 0 2006.285.15:23:19.56#ibcon#*before return 0, iclass 11, count 0 2006.285.15:23:19.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:23:19.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:23:19.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:23:19.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:23:19.56$vck44/valo=7,864.99 2006.285.15:23:19.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.15:23:19.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.15:23:19.56#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:19.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:23:19.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:23:19.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:23:19.56#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:23:19.56#ibcon#first serial, iclass 13, count 0 2006.285.15:23:19.56#ibcon#enter sib2, iclass 13, count 0 2006.285.15:23:19.56#ibcon#flushed, iclass 13, count 0 2006.285.15:23:19.56#ibcon#about to write, iclass 13, count 0 2006.285.15:23:19.56#ibcon#wrote, iclass 13, count 0 2006.285.15:23:19.56#ibcon#about to read 3, iclass 13, count 0 2006.285.15:23:19.57#ibcon#read 3, iclass 13, count 0 2006.285.15:23:19.57#ibcon#about to read 4, iclass 13, count 0 2006.285.15:23:19.57#ibcon#read 4, iclass 13, count 0 2006.285.15:23:19.57#ibcon#about to read 5, iclass 13, count 0 2006.285.15:23:19.57#ibcon#read 5, iclass 13, count 0 2006.285.15:23:19.57#ibcon#about to read 6, iclass 13, count 0 2006.285.15:23:19.57#ibcon#read 6, iclass 13, count 0 2006.285.15:23:19.57#ibcon#end of sib2, iclass 13, count 0 2006.285.15:23:19.57#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:23:19.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:23:19.57#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.15:23:19.57#ibcon#*before write, iclass 13, count 0 2006.285.15:23:19.57#ibcon#enter sib2, iclass 13, count 0 2006.285.15:23:19.57#ibcon#flushed, iclass 13, count 0 2006.285.15:23:19.57#ibcon#about to write, iclass 13, count 0 2006.285.15:23:19.57#ibcon#wrote, iclass 13, count 0 2006.285.15:23:19.57#ibcon#about to read 3, iclass 13, count 0 2006.285.15:23:19.61#ibcon#read 3, iclass 13, count 0 2006.285.15:23:19.61#ibcon#about to read 4, iclass 13, count 0 2006.285.15:23:19.61#ibcon#read 4, iclass 13, count 0 2006.285.15:23:19.61#ibcon#about to read 5, iclass 13, count 0 2006.285.15:23:19.61#ibcon#read 5, iclass 13, count 0 2006.285.15:23:19.61#ibcon#about to read 6, iclass 13, count 0 2006.285.15:23:19.61#ibcon#read 6, iclass 13, count 0 2006.285.15:23:19.61#ibcon#end of sib2, iclass 13, count 0 2006.285.15:23:19.61#ibcon#*after write, iclass 13, count 0 2006.285.15:23:19.61#ibcon#*before return 0, iclass 13, count 0 2006.285.15:23:19.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:23:19.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:23:19.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:23:19.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:23:19.61$vck44/va=7,4 2006.285.15:23:19.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.15:23:19.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.15:23:19.61#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:19.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:23:19.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:23:19.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:23:19.68#ibcon#enter wrdev, iclass 15, count 2 2006.285.15:23:19.68#ibcon#first serial, iclass 15, count 2 2006.285.15:23:19.68#ibcon#enter sib2, iclass 15, count 2 2006.285.15:23:19.68#ibcon#flushed, iclass 15, count 2 2006.285.15:23:19.68#ibcon#about to write, iclass 15, count 2 2006.285.15:23:19.68#ibcon#wrote, iclass 15, count 2 2006.285.15:23:19.68#ibcon#about to read 3, iclass 15, count 2 2006.285.15:23:19.70#ibcon#read 3, iclass 15, count 2 2006.285.15:23:19.70#ibcon#about to read 4, iclass 15, count 2 2006.285.15:23:19.70#ibcon#read 4, iclass 15, count 2 2006.285.15:23:19.70#ibcon#about to read 5, iclass 15, count 2 2006.285.15:23:19.70#ibcon#read 5, iclass 15, count 2 2006.285.15:23:19.70#ibcon#about to read 6, iclass 15, count 2 2006.285.15:23:19.70#ibcon#read 6, iclass 15, count 2 2006.285.15:23:19.70#ibcon#end of sib2, iclass 15, count 2 2006.285.15:23:19.70#ibcon#*mode == 0, iclass 15, count 2 2006.285.15:23:19.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.15:23:19.70#ibcon#[25=AT07-04\r\n] 2006.285.15:23:19.70#ibcon#*before write, iclass 15, count 2 2006.285.15:23:19.70#ibcon#enter sib2, iclass 15, count 2 2006.285.15:23:19.70#ibcon#flushed, iclass 15, count 2 2006.285.15:23:19.70#ibcon#about to write, iclass 15, count 2 2006.285.15:23:19.70#ibcon#wrote, iclass 15, count 2 2006.285.15:23:19.70#ibcon#about to read 3, iclass 15, count 2 2006.285.15:23:19.73#ibcon#read 3, iclass 15, count 2 2006.285.15:23:19.73#ibcon#about to read 4, iclass 15, count 2 2006.285.15:23:19.73#ibcon#read 4, iclass 15, count 2 2006.285.15:23:19.73#ibcon#about to read 5, iclass 15, count 2 2006.285.15:23:19.73#ibcon#read 5, iclass 15, count 2 2006.285.15:23:19.73#ibcon#about to read 6, iclass 15, count 2 2006.285.15:23:19.73#ibcon#read 6, iclass 15, count 2 2006.285.15:23:19.73#ibcon#end of sib2, iclass 15, count 2 2006.285.15:23:19.73#ibcon#*after write, iclass 15, count 2 2006.285.15:23:19.73#ibcon#*before return 0, iclass 15, count 2 2006.285.15:23:19.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:23:19.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:23:19.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.15:23:19.73#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:19.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:23:19.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:23:19.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:23:19.85#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:23:19.85#ibcon#first serial, iclass 15, count 0 2006.285.15:23:19.85#ibcon#enter sib2, iclass 15, count 0 2006.285.15:23:19.85#ibcon#flushed, iclass 15, count 0 2006.285.15:23:19.85#ibcon#about to write, iclass 15, count 0 2006.285.15:23:19.85#ibcon#wrote, iclass 15, count 0 2006.285.15:23:19.85#ibcon#about to read 3, iclass 15, count 0 2006.285.15:23:19.87#ibcon#read 3, iclass 15, count 0 2006.285.15:23:19.87#ibcon#about to read 4, iclass 15, count 0 2006.285.15:23:19.87#ibcon#read 4, iclass 15, count 0 2006.285.15:23:19.87#ibcon#about to read 5, iclass 15, count 0 2006.285.15:23:19.87#ibcon#read 5, iclass 15, count 0 2006.285.15:23:19.87#ibcon#about to read 6, iclass 15, count 0 2006.285.15:23:19.87#ibcon#read 6, iclass 15, count 0 2006.285.15:23:19.87#ibcon#end of sib2, iclass 15, count 0 2006.285.15:23:19.87#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:23:19.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:23:19.87#ibcon#[25=USB\r\n] 2006.285.15:23:19.87#ibcon#*before write, iclass 15, count 0 2006.285.15:23:19.87#ibcon#enter sib2, iclass 15, count 0 2006.285.15:23:19.87#ibcon#flushed, iclass 15, count 0 2006.285.15:23:19.87#ibcon#about to write, iclass 15, count 0 2006.285.15:23:19.87#ibcon#wrote, iclass 15, count 0 2006.285.15:23:19.87#ibcon#about to read 3, iclass 15, count 0 2006.285.15:23:19.90#ibcon#read 3, iclass 15, count 0 2006.285.15:23:19.90#ibcon#about to read 4, iclass 15, count 0 2006.285.15:23:19.90#ibcon#read 4, iclass 15, count 0 2006.285.15:23:19.90#ibcon#about to read 5, iclass 15, count 0 2006.285.15:23:19.90#ibcon#read 5, iclass 15, count 0 2006.285.15:23:19.90#ibcon#about to read 6, iclass 15, count 0 2006.285.15:23:19.90#ibcon#read 6, iclass 15, count 0 2006.285.15:23:19.90#ibcon#end of sib2, iclass 15, count 0 2006.285.15:23:19.90#ibcon#*after write, iclass 15, count 0 2006.285.15:23:19.90#ibcon#*before return 0, iclass 15, count 0 2006.285.15:23:19.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:23:19.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:23:19.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:23:19.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:23:19.90$vck44/valo=8,884.99 2006.285.15:23:19.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.15:23:19.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.15:23:19.90#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:19.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:23:19.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:23:19.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:23:19.90#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:23:19.90#ibcon#first serial, iclass 17, count 0 2006.285.15:23:19.90#ibcon#enter sib2, iclass 17, count 0 2006.285.15:23:19.90#ibcon#flushed, iclass 17, count 0 2006.285.15:23:19.90#ibcon#about to write, iclass 17, count 0 2006.285.15:23:19.90#ibcon#wrote, iclass 17, count 0 2006.285.15:23:19.91#ibcon#about to read 3, iclass 17, count 0 2006.285.15:23:19.92#ibcon#read 3, iclass 17, count 0 2006.285.15:23:19.92#ibcon#about to read 4, iclass 17, count 0 2006.285.15:23:19.92#ibcon#read 4, iclass 17, count 0 2006.285.15:23:19.92#ibcon#about to read 5, iclass 17, count 0 2006.285.15:23:19.92#ibcon#read 5, iclass 17, count 0 2006.285.15:23:19.92#ibcon#about to read 6, iclass 17, count 0 2006.285.15:23:19.92#ibcon#read 6, iclass 17, count 0 2006.285.15:23:19.92#ibcon#end of sib2, iclass 17, count 0 2006.285.15:23:19.92#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:23:19.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:23:19.92#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.15:23:19.92#ibcon#*before write, iclass 17, count 0 2006.285.15:23:19.92#ibcon#enter sib2, iclass 17, count 0 2006.285.15:23:19.92#ibcon#flushed, iclass 17, count 0 2006.285.15:23:19.92#ibcon#about to write, iclass 17, count 0 2006.285.15:23:19.92#ibcon#wrote, iclass 17, count 0 2006.285.15:23:19.92#ibcon#about to read 3, iclass 17, count 0 2006.285.15:23:19.96#ibcon#read 3, iclass 17, count 0 2006.285.15:23:19.96#ibcon#about to read 4, iclass 17, count 0 2006.285.15:23:19.96#ibcon#read 4, iclass 17, count 0 2006.285.15:23:19.96#ibcon#about to read 5, iclass 17, count 0 2006.285.15:23:19.96#ibcon#read 5, iclass 17, count 0 2006.285.15:23:19.96#ibcon#about to read 6, iclass 17, count 0 2006.285.15:23:19.96#ibcon#read 6, iclass 17, count 0 2006.285.15:23:19.96#ibcon#end of sib2, iclass 17, count 0 2006.285.15:23:19.96#ibcon#*after write, iclass 17, count 0 2006.285.15:23:19.96#ibcon#*before return 0, iclass 17, count 0 2006.285.15:23:19.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:23:19.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:23:19.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:23:19.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:23:19.96$vck44/va=8,3 2006.285.15:23:19.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.15:23:19.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.15:23:19.96#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:19.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:23:20.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:23:20.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:23:20.02#ibcon#enter wrdev, iclass 19, count 2 2006.285.15:23:20.02#ibcon#first serial, iclass 19, count 2 2006.285.15:23:20.02#ibcon#enter sib2, iclass 19, count 2 2006.285.15:23:20.02#ibcon#flushed, iclass 19, count 2 2006.285.15:23:20.02#ibcon#about to write, iclass 19, count 2 2006.285.15:23:20.02#ibcon#wrote, iclass 19, count 2 2006.285.15:23:20.02#ibcon#about to read 3, iclass 19, count 2 2006.285.15:23:20.04#ibcon#read 3, iclass 19, count 2 2006.285.15:23:20.04#ibcon#about to read 4, iclass 19, count 2 2006.285.15:23:20.04#ibcon#read 4, iclass 19, count 2 2006.285.15:23:20.04#ibcon#about to read 5, iclass 19, count 2 2006.285.15:23:20.04#ibcon#read 5, iclass 19, count 2 2006.285.15:23:20.04#ibcon#about to read 6, iclass 19, count 2 2006.285.15:23:20.04#ibcon#read 6, iclass 19, count 2 2006.285.15:23:20.04#ibcon#end of sib2, iclass 19, count 2 2006.285.15:23:20.04#ibcon#*mode == 0, iclass 19, count 2 2006.285.15:23:20.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.15:23:20.04#ibcon#[25=AT08-03\r\n] 2006.285.15:23:20.04#ibcon#*before write, iclass 19, count 2 2006.285.15:23:20.04#ibcon#enter sib2, iclass 19, count 2 2006.285.15:23:20.04#ibcon#flushed, iclass 19, count 2 2006.285.15:23:20.04#ibcon#about to write, iclass 19, count 2 2006.285.15:23:20.04#ibcon#wrote, iclass 19, count 2 2006.285.15:23:20.04#ibcon#about to read 3, iclass 19, count 2 2006.285.15:23:20.07#ibcon#read 3, iclass 19, count 2 2006.285.15:23:20.07#ibcon#about to read 4, iclass 19, count 2 2006.285.15:23:20.07#ibcon#read 4, iclass 19, count 2 2006.285.15:23:20.07#ibcon#about to read 5, iclass 19, count 2 2006.285.15:23:20.07#ibcon#read 5, iclass 19, count 2 2006.285.15:23:20.07#ibcon#about to read 6, iclass 19, count 2 2006.285.15:23:20.07#ibcon#read 6, iclass 19, count 2 2006.285.15:23:20.07#ibcon#end of sib2, iclass 19, count 2 2006.285.15:23:20.07#ibcon#*after write, iclass 19, count 2 2006.285.15:23:20.07#ibcon#*before return 0, iclass 19, count 2 2006.285.15:23:20.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:23:20.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:23:20.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.15:23:20.07#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:20.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:23:20.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:23:20.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:23:20.19#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:23:20.19#ibcon#first serial, iclass 19, count 0 2006.285.15:23:20.19#ibcon#enter sib2, iclass 19, count 0 2006.285.15:23:20.19#ibcon#flushed, iclass 19, count 0 2006.285.15:23:20.19#ibcon#about to write, iclass 19, count 0 2006.285.15:23:20.19#ibcon#wrote, iclass 19, count 0 2006.285.15:23:20.19#ibcon#about to read 3, iclass 19, count 0 2006.285.15:23:20.21#ibcon#read 3, iclass 19, count 0 2006.285.15:23:20.21#ibcon#about to read 4, iclass 19, count 0 2006.285.15:23:20.21#ibcon#read 4, iclass 19, count 0 2006.285.15:23:20.21#ibcon#about to read 5, iclass 19, count 0 2006.285.15:23:20.21#ibcon#read 5, iclass 19, count 0 2006.285.15:23:20.21#ibcon#about to read 6, iclass 19, count 0 2006.285.15:23:20.21#ibcon#read 6, iclass 19, count 0 2006.285.15:23:20.21#ibcon#end of sib2, iclass 19, count 0 2006.285.15:23:20.21#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:23:20.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:23:20.21#ibcon#[25=USB\r\n] 2006.285.15:23:20.21#ibcon#*before write, iclass 19, count 0 2006.285.15:23:20.21#ibcon#enter sib2, iclass 19, count 0 2006.285.15:23:20.21#ibcon#flushed, iclass 19, count 0 2006.285.15:23:20.21#ibcon#about to write, iclass 19, count 0 2006.285.15:23:20.21#ibcon#wrote, iclass 19, count 0 2006.285.15:23:20.21#ibcon#about to read 3, iclass 19, count 0 2006.285.15:23:20.24#ibcon#read 3, iclass 19, count 0 2006.285.15:23:20.24#ibcon#about to read 4, iclass 19, count 0 2006.285.15:23:20.24#ibcon#read 4, iclass 19, count 0 2006.285.15:23:20.24#ibcon#about to read 5, iclass 19, count 0 2006.285.15:23:20.24#ibcon#read 5, iclass 19, count 0 2006.285.15:23:20.24#ibcon#about to read 6, iclass 19, count 0 2006.285.15:23:20.24#ibcon#read 6, iclass 19, count 0 2006.285.15:23:20.24#ibcon#end of sib2, iclass 19, count 0 2006.285.15:23:20.24#ibcon#*after write, iclass 19, count 0 2006.285.15:23:20.24#ibcon#*before return 0, iclass 19, count 0 2006.285.15:23:20.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:23:20.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:23:20.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:23:20.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:23:20.24$vck44/vblo=1,629.99 2006.285.15:23:20.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.15:23:20.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.15:23:20.24#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:20.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:23:20.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:23:20.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:23:20.24#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:23:20.24#ibcon#first serial, iclass 21, count 0 2006.285.15:23:20.24#ibcon#enter sib2, iclass 21, count 0 2006.285.15:23:20.24#ibcon#flushed, iclass 21, count 0 2006.285.15:23:20.24#ibcon#about to write, iclass 21, count 0 2006.285.15:23:20.25#ibcon#wrote, iclass 21, count 0 2006.285.15:23:20.25#ibcon#about to read 3, iclass 21, count 0 2006.285.15:23:20.26#ibcon#read 3, iclass 21, count 0 2006.285.15:23:20.26#ibcon#about to read 4, iclass 21, count 0 2006.285.15:23:20.26#ibcon#read 4, iclass 21, count 0 2006.285.15:23:20.26#ibcon#about to read 5, iclass 21, count 0 2006.285.15:23:20.26#ibcon#read 5, iclass 21, count 0 2006.285.15:23:20.26#ibcon#about to read 6, iclass 21, count 0 2006.285.15:23:20.26#ibcon#read 6, iclass 21, count 0 2006.285.15:23:20.26#ibcon#end of sib2, iclass 21, count 0 2006.285.15:23:20.26#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:23:20.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:23:20.26#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.15:23:20.26#ibcon#*before write, iclass 21, count 0 2006.285.15:23:20.26#ibcon#enter sib2, iclass 21, count 0 2006.285.15:23:20.26#ibcon#flushed, iclass 21, count 0 2006.285.15:23:20.26#ibcon#about to write, iclass 21, count 0 2006.285.15:23:20.26#ibcon#wrote, iclass 21, count 0 2006.285.15:23:20.26#ibcon#about to read 3, iclass 21, count 0 2006.285.15:23:20.30#ibcon#read 3, iclass 21, count 0 2006.285.15:23:20.30#ibcon#about to read 4, iclass 21, count 0 2006.285.15:23:20.30#ibcon#read 4, iclass 21, count 0 2006.285.15:23:20.30#ibcon#about to read 5, iclass 21, count 0 2006.285.15:23:20.30#ibcon#read 5, iclass 21, count 0 2006.285.15:23:20.30#ibcon#about to read 6, iclass 21, count 0 2006.285.15:23:20.30#ibcon#read 6, iclass 21, count 0 2006.285.15:23:20.30#ibcon#end of sib2, iclass 21, count 0 2006.285.15:23:20.30#ibcon#*after write, iclass 21, count 0 2006.285.15:23:20.30#ibcon#*before return 0, iclass 21, count 0 2006.285.15:23:20.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:23:20.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:23:20.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:23:20.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:23:20.30$vck44/vb=1,4 2006.285.15:23:20.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.15:23:20.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.15:23:20.30#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:20.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:23:20.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:23:20.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:23:20.30#ibcon#enter wrdev, iclass 23, count 2 2006.285.15:23:20.30#ibcon#first serial, iclass 23, count 2 2006.285.15:23:20.30#ibcon#enter sib2, iclass 23, count 2 2006.285.15:23:20.30#ibcon#flushed, iclass 23, count 2 2006.285.15:23:20.30#ibcon#about to write, iclass 23, count 2 2006.285.15:23:20.30#ibcon#wrote, iclass 23, count 2 2006.285.15:23:20.30#ibcon#about to read 3, iclass 23, count 2 2006.285.15:23:20.32#ibcon#read 3, iclass 23, count 2 2006.285.15:23:20.32#ibcon#about to read 4, iclass 23, count 2 2006.285.15:23:20.32#ibcon#read 4, iclass 23, count 2 2006.285.15:23:20.32#ibcon#about to read 5, iclass 23, count 2 2006.285.15:23:20.32#ibcon#read 5, iclass 23, count 2 2006.285.15:23:20.32#ibcon#about to read 6, iclass 23, count 2 2006.285.15:23:20.32#ibcon#read 6, iclass 23, count 2 2006.285.15:23:20.32#ibcon#end of sib2, iclass 23, count 2 2006.285.15:23:20.32#ibcon#*mode == 0, iclass 23, count 2 2006.285.15:23:20.32#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.15:23:20.32#ibcon#[27=AT01-04\r\n] 2006.285.15:23:20.32#ibcon#*before write, iclass 23, count 2 2006.285.15:23:20.32#ibcon#enter sib2, iclass 23, count 2 2006.285.15:23:20.32#ibcon#flushed, iclass 23, count 2 2006.285.15:23:20.32#ibcon#about to write, iclass 23, count 2 2006.285.15:23:20.32#ibcon#wrote, iclass 23, count 2 2006.285.15:23:20.32#ibcon#about to read 3, iclass 23, count 2 2006.285.15:23:20.35#ibcon#read 3, iclass 23, count 2 2006.285.15:23:20.35#ibcon#about to read 4, iclass 23, count 2 2006.285.15:23:20.35#ibcon#read 4, iclass 23, count 2 2006.285.15:23:20.35#ibcon#about to read 5, iclass 23, count 2 2006.285.15:23:20.35#ibcon#read 5, iclass 23, count 2 2006.285.15:23:20.35#ibcon#about to read 6, iclass 23, count 2 2006.285.15:23:20.35#ibcon#read 6, iclass 23, count 2 2006.285.15:23:20.35#ibcon#end of sib2, iclass 23, count 2 2006.285.15:23:20.35#ibcon#*after write, iclass 23, count 2 2006.285.15:23:20.35#ibcon#*before return 0, iclass 23, count 2 2006.285.15:23:20.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:23:20.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:23:20.35#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.15:23:20.35#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:20.35#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:23:20.47#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:23:20.47#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:23:20.47#ibcon#enter wrdev, iclass 23, count 0 2006.285.15:23:20.47#ibcon#first serial, iclass 23, count 0 2006.285.15:23:20.47#ibcon#enter sib2, iclass 23, count 0 2006.285.15:23:20.47#ibcon#flushed, iclass 23, count 0 2006.285.15:23:20.47#ibcon#about to write, iclass 23, count 0 2006.285.15:23:20.47#ibcon#wrote, iclass 23, count 0 2006.285.15:23:20.47#ibcon#about to read 3, iclass 23, count 0 2006.285.15:23:20.49#ibcon#read 3, iclass 23, count 0 2006.285.15:23:20.49#ibcon#about to read 4, iclass 23, count 0 2006.285.15:23:20.49#ibcon#read 4, iclass 23, count 0 2006.285.15:23:20.49#ibcon#about to read 5, iclass 23, count 0 2006.285.15:23:20.49#ibcon#read 5, iclass 23, count 0 2006.285.15:23:20.49#ibcon#about to read 6, iclass 23, count 0 2006.285.15:23:20.49#ibcon#read 6, iclass 23, count 0 2006.285.15:23:20.49#ibcon#end of sib2, iclass 23, count 0 2006.285.15:23:20.49#ibcon#*mode == 0, iclass 23, count 0 2006.285.15:23:20.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.15:23:20.49#ibcon#[27=USB\r\n] 2006.285.15:23:20.49#ibcon#*before write, iclass 23, count 0 2006.285.15:23:20.49#ibcon#enter sib2, iclass 23, count 0 2006.285.15:23:20.49#ibcon#flushed, iclass 23, count 0 2006.285.15:23:20.49#ibcon#about to write, iclass 23, count 0 2006.285.15:23:20.49#ibcon#wrote, iclass 23, count 0 2006.285.15:23:20.49#ibcon#about to read 3, iclass 23, count 0 2006.285.15:23:20.52#ibcon#read 3, iclass 23, count 0 2006.285.15:23:20.52#ibcon#about to read 4, iclass 23, count 0 2006.285.15:23:20.52#ibcon#read 4, iclass 23, count 0 2006.285.15:23:20.52#ibcon#about to read 5, iclass 23, count 0 2006.285.15:23:20.52#ibcon#read 5, iclass 23, count 0 2006.285.15:23:20.52#ibcon#about to read 6, iclass 23, count 0 2006.285.15:23:20.52#ibcon#read 6, iclass 23, count 0 2006.285.15:23:20.52#ibcon#end of sib2, iclass 23, count 0 2006.285.15:23:20.52#ibcon#*after write, iclass 23, count 0 2006.285.15:23:20.52#ibcon#*before return 0, iclass 23, count 0 2006.285.15:23:20.52#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:23:20.52#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:23:20.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.15:23:20.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.15:23:20.52$vck44/vblo=2,634.99 2006.285.15:23:20.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.15:23:20.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.15:23:20.54#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:20.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:23:20.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:23:20.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:23:20.54#ibcon#enter wrdev, iclass 25, count 0 2006.285.15:23:20.54#ibcon#first serial, iclass 25, count 0 2006.285.15:23:20.54#ibcon#enter sib2, iclass 25, count 0 2006.285.15:23:20.54#ibcon#flushed, iclass 25, count 0 2006.285.15:23:20.54#ibcon#about to write, iclass 25, count 0 2006.285.15:23:20.54#ibcon#wrote, iclass 25, count 0 2006.285.15:23:20.54#ibcon#about to read 3, iclass 25, count 0 2006.285.15:23:20.56#ibcon#read 3, iclass 25, count 0 2006.285.15:23:20.56#ibcon#about to read 4, iclass 25, count 0 2006.285.15:23:20.56#ibcon#read 4, iclass 25, count 0 2006.285.15:23:20.56#ibcon#about to read 5, iclass 25, count 0 2006.285.15:23:20.56#ibcon#read 5, iclass 25, count 0 2006.285.15:23:20.56#ibcon#about to read 6, iclass 25, count 0 2006.285.15:23:20.56#ibcon#read 6, iclass 25, count 0 2006.285.15:23:20.56#ibcon#end of sib2, iclass 25, count 0 2006.285.15:23:20.56#ibcon#*mode == 0, iclass 25, count 0 2006.285.15:23:20.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.15:23:20.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.15:23:20.56#ibcon#*before write, iclass 25, count 0 2006.285.15:23:20.56#ibcon#enter sib2, iclass 25, count 0 2006.285.15:23:20.56#ibcon#flushed, iclass 25, count 0 2006.285.15:23:20.56#ibcon#about to write, iclass 25, count 0 2006.285.15:23:20.56#ibcon#wrote, iclass 25, count 0 2006.285.15:23:20.56#ibcon#about to read 3, iclass 25, count 0 2006.285.15:23:20.60#ibcon#read 3, iclass 25, count 0 2006.285.15:23:20.60#ibcon#about to read 4, iclass 25, count 0 2006.285.15:23:20.60#ibcon#read 4, iclass 25, count 0 2006.285.15:23:20.60#ibcon#about to read 5, iclass 25, count 0 2006.285.15:23:20.60#ibcon#read 5, iclass 25, count 0 2006.285.15:23:20.60#ibcon#about to read 6, iclass 25, count 0 2006.285.15:23:20.60#ibcon#read 6, iclass 25, count 0 2006.285.15:23:20.60#ibcon#end of sib2, iclass 25, count 0 2006.285.15:23:20.60#ibcon#*after write, iclass 25, count 0 2006.285.15:23:20.60#ibcon#*before return 0, iclass 25, count 0 2006.285.15:23:20.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:23:20.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:23:20.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.15:23:20.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.15:23:20.60$vck44/vb=2,5 2006.285.15:23:20.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.15:23:20.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.15:23:20.60#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:20.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:23:20.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:23:20.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:23:20.64#ibcon#enter wrdev, iclass 27, count 2 2006.285.15:23:20.64#ibcon#first serial, iclass 27, count 2 2006.285.15:23:20.64#ibcon#enter sib2, iclass 27, count 2 2006.285.15:23:20.64#ibcon#flushed, iclass 27, count 2 2006.285.15:23:20.64#ibcon#about to write, iclass 27, count 2 2006.285.15:23:20.64#ibcon#wrote, iclass 27, count 2 2006.285.15:23:20.64#ibcon#about to read 3, iclass 27, count 2 2006.285.15:23:20.66#ibcon#read 3, iclass 27, count 2 2006.285.15:23:20.66#ibcon#about to read 4, iclass 27, count 2 2006.285.15:23:20.66#ibcon#read 4, iclass 27, count 2 2006.285.15:23:20.66#ibcon#about to read 5, iclass 27, count 2 2006.285.15:23:20.66#ibcon#read 5, iclass 27, count 2 2006.285.15:23:20.66#ibcon#about to read 6, iclass 27, count 2 2006.285.15:23:20.66#ibcon#read 6, iclass 27, count 2 2006.285.15:23:20.66#ibcon#end of sib2, iclass 27, count 2 2006.285.15:23:20.66#ibcon#*mode == 0, iclass 27, count 2 2006.285.15:23:20.66#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.15:23:20.66#ibcon#[27=AT02-05\r\n] 2006.285.15:23:20.66#ibcon#*before write, iclass 27, count 2 2006.285.15:23:20.66#ibcon#enter sib2, iclass 27, count 2 2006.285.15:23:20.66#ibcon#flushed, iclass 27, count 2 2006.285.15:23:20.66#ibcon#about to write, iclass 27, count 2 2006.285.15:23:20.66#ibcon#wrote, iclass 27, count 2 2006.285.15:23:20.66#ibcon#about to read 3, iclass 27, count 2 2006.285.15:23:20.69#ibcon#read 3, iclass 27, count 2 2006.285.15:23:20.69#ibcon#about to read 4, iclass 27, count 2 2006.285.15:23:20.69#ibcon#read 4, iclass 27, count 2 2006.285.15:23:20.69#ibcon#about to read 5, iclass 27, count 2 2006.285.15:23:20.69#ibcon#read 5, iclass 27, count 2 2006.285.15:23:20.69#ibcon#about to read 6, iclass 27, count 2 2006.285.15:23:20.69#ibcon#read 6, iclass 27, count 2 2006.285.15:23:20.69#ibcon#end of sib2, iclass 27, count 2 2006.285.15:23:20.69#ibcon#*after write, iclass 27, count 2 2006.285.15:23:20.69#ibcon#*before return 0, iclass 27, count 2 2006.285.15:23:20.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:23:20.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:23:20.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.15:23:20.69#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:20.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:23:20.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:23:20.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:23:20.81#ibcon#enter wrdev, iclass 27, count 0 2006.285.15:23:20.81#ibcon#first serial, iclass 27, count 0 2006.285.15:23:20.81#ibcon#enter sib2, iclass 27, count 0 2006.285.15:23:20.81#ibcon#flushed, iclass 27, count 0 2006.285.15:23:20.81#ibcon#about to write, iclass 27, count 0 2006.285.15:23:20.81#ibcon#wrote, iclass 27, count 0 2006.285.15:23:20.81#ibcon#about to read 3, iclass 27, count 0 2006.285.15:23:20.83#ibcon#read 3, iclass 27, count 0 2006.285.15:23:20.83#ibcon#about to read 4, iclass 27, count 0 2006.285.15:23:20.83#ibcon#read 4, iclass 27, count 0 2006.285.15:23:20.83#ibcon#about to read 5, iclass 27, count 0 2006.285.15:23:20.83#ibcon#read 5, iclass 27, count 0 2006.285.15:23:20.83#ibcon#about to read 6, iclass 27, count 0 2006.285.15:23:20.83#ibcon#read 6, iclass 27, count 0 2006.285.15:23:20.83#ibcon#end of sib2, iclass 27, count 0 2006.285.15:23:20.83#ibcon#*mode == 0, iclass 27, count 0 2006.285.15:23:20.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.15:23:20.83#ibcon#[27=USB\r\n] 2006.285.15:23:20.83#ibcon#*before write, iclass 27, count 0 2006.285.15:23:20.83#ibcon#enter sib2, iclass 27, count 0 2006.285.15:23:20.83#ibcon#flushed, iclass 27, count 0 2006.285.15:23:20.83#ibcon#about to write, iclass 27, count 0 2006.285.15:23:20.83#ibcon#wrote, iclass 27, count 0 2006.285.15:23:20.83#ibcon#about to read 3, iclass 27, count 0 2006.285.15:23:20.86#ibcon#read 3, iclass 27, count 0 2006.285.15:23:20.86#ibcon#about to read 4, iclass 27, count 0 2006.285.15:23:20.86#ibcon#read 4, iclass 27, count 0 2006.285.15:23:20.86#ibcon#about to read 5, iclass 27, count 0 2006.285.15:23:20.86#ibcon#read 5, iclass 27, count 0 2006.285.15:23:20.86#ibcon#about to read 6, iclass 27, count 0 2006.285.15:23:20.86#ibcon#read 6, iclass 27, count 0 2006.285.15:23:20.86#ibcon#end of sib2, iclass 27, count 0 2006.285.15:23:20.86#ibcon#*after write, iclass 27, count 0 2006.285.15:23:20.86#ibcon#*before return 0, iclass 27, count 0 2006.285.15:23:20.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:23:20.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:23:20.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.15:23:20.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.15:23:20.86$vck44/vblo=3,649.99 2006.285.15:23:20.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.15:23:20.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.15:23:20.86#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:20.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:23:20.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:23:20.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:23:20.86#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:23:20.86#ibcon#first serial, iclass 29, count 0 2006.285.15:23:20.86#ibcon#enter sib2, iclass 29, count 0 2006.285.15:23:20.86#ibcon#flushed, iclass 29, count 0 2006.285.15:23:20.86#ibcon#about to write, iclass 29, count 0 2006.285.15:23:20.86#ibcon#wrote, iclass 29, count 0 2006.285.15:23:20.87#ibcon#about to read 3, iclass 29, count 0 2006.285.15:23:20.88#ibcon#read 3, iclass 29, count 0 2006.285.15:23:20.88#ibcon#about to read 4, iclass 29, count 0 2006.285.15:23:20.88#ibcon#read 4, iclass 29, count 0 2006.285.15:23:20.88#ibcon#about to read 5, iclass 29, count 0 2006.285.15:23:20.88#ibcon#read 5, iclass 29, count 0 2006.285.15:23:20.88#ibcon#about to read 6, iclass 29, count 0 2006.285.15:23:20.88#ibcon#read 6, iclass 29, count 0 2006.285.15:23:20.88#ibcon#end of sib2, iclass 29, count 0 2006.285.15:23:20.88#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:23:20.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:23:20.88#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.15:23:20.88#ibcon#*before write, iclass 29, count 0 2006.285.15:23:20.88#ibcon#enter sib2, iclass 29, count 0 2006.285.15:23:20.88#ibcon#flushed, iclass 29, count 0 2006.285.15:23:20.88#ibcon#about to write, iclass 29, count 0 2006.285.15:23:20.88#ibcon#wrote, iclass 29, count 0 2006.285.15:23:20.88#ibcon#about to read 3, iclass 29, count 0 2006.285.15:23:20.92#ibcon#read 3, iclass 29, count 0 2006.285.15:23:20.92#ibcon#about to read 4, iclass 29, count 0 2006.285.15:23:20.92#ibcon#read 4, iclass 29, count 0 2006.285.15:23:20.92#ibcon#about to read 5, iclass 29, count 0 2006.285.15:23:20.92#ibcon#read 5, iclass 29, count 0 2006.285.15:23:20.92#ibcon#about to read 6, iclass 29, count 0 2006.285.15:23:20.92#ibcon#read 6, iclass 29, count 0 2006.285.15:23:20.92#ibcon#end of sib2, iclass 29, count 0 2006.285.15:23:20.92#ibcon#*after write, iclass 29, count 0 2006.285.15:23:20.92#ibcon#*before return 0, iclass 29, count 0 2006.285.15:23:20.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:23:20.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:23:20.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:23:20.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:23:20.92$vck44/vb=3,4 2006.285.15:23:20.92#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.15:23:20.92#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.15:23:20.92#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:20.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:23:20.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:23:20.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:23:20.98#ibcon#enter wrdev, iclass 31, count 2 2006.285.15:23:20.98#ibcon#first serial, iclass 31, count 2 2006.285.15:23:20.98#ibcon#enter sib2, iclass 31, count 2 2006.285.15:23:20.98#ibcon#flushed, iclass 31, count 2 2006.285.15:23:20.98#ibcon#about to write, iclass 31, count 2 2006.285.15:23:20.98#ibcon#wrote, iclass 31, count 2 2006.285.15:23:20.98#ibcon#about to read 3, iclass 31, count 2 2006.285.15:23:21.00#ibcon#read 3, iclass 31, count 2 2006.285.15:23:21.00#ibcon#about to read 4, iclass 31, count 2 2006.285.15:23:21.00#ibcon#read 4, iclass 31, count 2 2006.285.15:23:21.00#ibcon#about to read 5, iclass 31, count 2 2006.285.15:23:21.00#ibcon#read 5, iclass 31, count 2 2006.285.15:23:21.00#ibcon#about to read 6, iclass 31, count 2 2006.285.15:23:21.00#ibcon#read 6, iclass 31, count 2 2006.285.15:23:21.00#ibcon#end of sib2, iclass 31, count 2 2006.285.15:23:21.00#ibcon#*mode == 0, iclass 31, count 2 2006.285.15:23:21.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.15:23:21.00#ibcon#[27=AT03-04\r\n] 2006.285.15:23:21.00#ibcon#*before write, iclass 31, count 2 2006.285.15:23:21.00#ibcon#enter sib2, iclass 31, count 2 2006.285.15:23:21.00#ibcon#flushed, iclass 31, count 2 2006.285.15:23:21.00#ibcon#about to write, iclass 31, count 2 2006.285.15:23:21.00#ibcon#wrote, iclass 31, count 2 2006.285.15:23:21.00#ibcon#about to read 3, iclass 31, count 2 2006.285.15:23:21.03#ibcon#read 3, iclass 31, count 2 2006.285.15:23:21.03#ibcon#about to read 4, iclass 31, count 2 2006.285.15:23:21.03#ibcon#read 4, iclass 31, count 2 2006.285.15:23:21.03#ibcon#about to read 5, iclass 31, count 2 2006.285.15:23:21.03#ibcon#read 5, iclass 31, count 2 2006.285.15:23:21.03#ibcon#about to read 6, iclass 31, count 2 2006.285.15:23:21.03#ibcon#read 6, iclass 31, count 2 2006.285.15:23:21.03#ibcon#end of sib2, iclass 31, count 2 2006.285.15:23:21.03#ibcon#*after write, iclass 31, count 2 2006.285.15:23:21.03#ibcon#*before return 0, iclass 31, count 2 2006.285.15:23:21.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:23:21.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:23:21.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.15:23:21.03#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:21.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:23:21.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:23:21.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:23:21.15#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:23:21.15#ibcon#first serial, iclass 31, count 0 2006.285.15:23:21.15#ibcon#enter sib2, iclass 31, count 0 2006.285.15:23:21.15#ibcon#flushed, iclass 31, count 0 2006.285.15:23:21.15#ibcon#about to write, iclass 31, count 0 2006.285.15:23:21.15#ibcon#wrote, iclass 31, count 0 2006.285.15:23:21.15#ibcon#about to read 3, iclass 31, count 0 2006.285.15:23:21.17#ibcon#read 3, iclass 31, count 0 2006.285.15:23:21.17#ibcon#about to read 4, iclass 31, count 0 2006.285.15:23:21.17#ibcon#read 4, iclass 31, count 0 2006.285.15:23:21.17#ibcon#about to read 5, iclass 31, count 0 2006.285.15:23:21.17#ibcon#read 5, iclass 31, count 0 2006.285.15:23:21.17#ibcon#about to read 6, iclass 31, count 0 2006.285.15:23:21.17#ibcon#read 6, iclass 31, count 0 2006.285.15:23:21.17#ibcon#end of sib2, iclass 31, count 0 2006.285.15:23:21.17#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:23:21.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:23:21.17#ibcon#[27=USB\r\n] 2006.285.15:23:21.17#ibcon#*before write, iclass 31, count 0 2006.285.15:23:21.17#ibcon#enter sib2, iclass 31, count 0 2006.285.15:23:21.17#ibcon#flushed, iclass 31, count 0 2006.285.15:23:21.17#ibcon#about to write, iclass 31, count 0 2006.285.15:23:21.17#ibcon#wrote, iclass 31, count 0 2006.285.15:23:21.17#ibcon#about to read 3, iclass 31, count 0 2006.285.15:23:21.20#ibcon#read 3, iclass 31, count 0 2006.285.15:23:21.20#ibcon#about to read 4, iclass 31, count 0 2006.285.15:23:21.20#ibcon#read 4, iclass 31, count 0 2006.285.15:23:21.20#ibcon#about to read 5, iclass 31, count 0 2006.285.15:23:21.20#ibcon#read 5, iclass 31, count 0 2006.285.15:23:21.20#ibcon#about to read 6, iclass 31, count 0 2006.285.15:23:21.20#ibcon#read 6, iclass 31, count 0 2006.285.15:23:21.20#ibcon#end of sib2, iclass 31, count 0 2006.285.15:23:21.20#ibcon#*after write, iclass 31, count 0 2006.285.15:23:21.20#ibcon#*before return 0, iclass 31, count 0 2006.285.15:23:21.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:23:21.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:23:21.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:23:21.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:23:21.20$vck44/vblo=4,679.99 2006.285.15:23:21.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.15:23:21.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.15:23:21.20#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:21.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:23:21.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:23:21.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:23:21.20#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:23:21.21#ibcon#first serial, iclass 33, count 0 2006.285.15:23:21.21#ibcon#enter sib2, iclass 33, count 0 2006.285.15:23:21.21#ibcon#flushed, iclass 33, count 0 2006.285.15:23:21.21#ibcon#about to write, iclass 33, count 0 2006.285.15:23:21.21#ibcon#wrote, iclass 33, count 0 2006.285.15:23:21.21#ibcon#about to read 3, iclass 33, count 0 2006.285.15:23:21.22#ibcon#read 3, iclass 33, count 0 2006.285.15:23:21.22#ibcon#about to read 4, iclass 33, count 0 2006.285.15:23:21.22#ibcon#read 4, iclass 33, count 0 2006.285.15:23:21.22#ibcon#about to read 5, iclass 33, count 0 2006.285.15:23:21.22#ibcon#read 5, iclass 33, count 0 2006.285.15:23:21.22#ibcon#about to read 6, iclass 33, count 0 2006.285.15:23:21.22#ibcon#read 6, iclass 33, count 0 2006.285.15:23:21.22#ibcon#end of sib2, iclass 33, count 0 2006.285.15:23:21.22#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:23:21.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:23:21.22#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.15:23:21.22#ibcon#*before write, iclass 33, count 0 2006.285.15:23:21.22#ibcon#enter sib2, iclass 33, count 0 2006.285.15:23:21.22#ibcon#flushed, iclass 33, count 0 2006.285.15:23:21.22#ibcon#about to write, iclass 33, count 0 2006.285.15:23:21.22#ibcon#wrote, iclass 33, count 0 2006.285.15:23:21.22#ibcon#about to read 3, iclass 33, count 0 2006.285.15:23:21.26#ibcon#read 3, iclass 33, count 0 2006.285.15:23:21.26#ibcon#about to read 4, iclass 33, count 0 2006.285.15:23:21.26#ibcon#read 4, iclass 33, count 0 2006.285.15:23:21.26#ibcon#about to read 5, iclass 33, count 0 2006.285.15:23:21.26#ibcon#read 5, iclass 33, count 0 2006.285.15:23:21.26#ibcon#about to read 6, iclass 33, count 0 2006.285.15:23:21.26#ibcon#read 6, iclass 33, count 0 2006.285.15:23:21.26#ibcon#end of sib2, iclass 33, count 0 2006.285.15:23:21.26#ibcon#*after write, iclass 33, count 0 2006.285.15:23:21.26#ibcon#*before return 0, iclass 33, count 0 2006.285.15:23:21.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:23:21.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:23:21.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:23:21.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:23:21.26$vck44/vb=4,5 2006.285.15:23:21.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.15:23:21.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.15:23:21.26#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:21.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:23:21.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:23:21.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:23:21.32#ibcon#enter wrdev, iclass 35, count 2 2006.285.15:23:21.32#ibcon#first serial, iclass 35, count 2 2006.285.15:23:21.32#ibcon#enter sib2, iclass 35, count 2 2006.285.15:23:21.32#ibcon#flushed, iclass 35, count 2 2006.285.15:23:21.32#ibcon#about to write, iclass 35, count 2 2006.285.15:23:21.32#ibcon#wrote, iclass 35, count 2 2006.285.15:23:21.32#ibcon#about to read 3, iclass 35, count 2 2006.285.15:23:21.34#ibcon#read 3, iclass 35, count 2 2006.285.15:23:21.34#ibcon#about to read 4, iclass 35, count 2 2006.285.15:23:21.34#ibcon#read 4, iclass 35, count 2 2006.285.15:23:21.34#ibcon#about to read 5, iclass 35, count 2 2006.285.15:23:21.34#ibcon#read 5, iclass 35, count 2 2006.285.15:23:21.34#ibcon#about to read 6, iclass 35, count 2 2006.285.15:23:21.34#ibcon#read 6, iclass 35, count 2 2006.285.15:23:21.34#ibcon#end of sib2, iclass 35, count 2 2006.285.15:23:21.34#ibcon#*mode == 0, iclass 35, count 2 2006.285.15:23:21.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.15:23:21.34#ibcon#[27=AT04-05\r\n] 2006.285.15:23:21.34#ibcon#*before write, iclass 35, count 2 2006.285.15:23:21.34#ibcon#enter sib2, iclass 35, count 2 2006.285.15:23:21.34#ibcon#flushed, iclass 35, count 2 2006.285.15:23:21.34#ibcon#about to write, iclass 35, count 2 2006.285.15:23:21.34#ibcon#wrote, iclass 35, count 2 2006.285.15:23:21.34#ibcon#about to read 3, iclass 35, count 2 2006.285.15:23:21.37#ibcon#read 3, iclass 35, count 2 2006.285.15:23:21.37#ibcon#about to read 4, iclass 35, count 2 2006.285.15:23:21.37#ibcon#read 4, iclass 35, count 2 2006.285.15:23:21.37#ibcon#about to read 5, iclass 35, count 2 2006.285.15:23:21.37#ibcon#read 5, iclass 35, count 2 2006.285.15:23:21.37#ibcon#about to read 6, iclass 35, count 2 2006.285.15:23:21.37#ibcon#read 6, iclass 35, count 2 2006.285.15:23:21.37#ibcon#end of sib2, iclass 35, count 2 2006.285.15:23:21.37#ibcon#*after write, iclass 35, count 2 2006.285.15:23:21.37#ibcon#*before return 0, iclass 35, count 2 2006.285.15:23:21.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:23:21.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:23:21.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.15:23:21.37#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:21.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:23:21.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:23:21.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:23:21.49#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:23:21.49#ibcon#first serial, iclass 35, count 0 2006.285.15:23:21.49#ibcon#enter sib2, iclass 35, count 0 2006.285.15:23:21.49#ibcon#flushed, iclass 35, count 0 2006.285.15:23:21.49#ibcon#about to write, iclass 35, count 0 2006.285.15:23:21.49#ibcon#wrote, iclass 35, count 0 2006.285.15:23:21.49#ibcon#about to read 3, iclass 35, count 0 2006.285.15:23:21.51#ibcon#read 3, iclass 35, count 0 2006.285.15:23:21.51#ibcon#about to read 4, iclass 35, count 0 2006.285.15:23:21.51#ibcon#read 4, iclass 35, count 0 2006.285.15:23:21.51#ibcon#about to read 5, iclass 35, count 0 2006.285.15:23:21.51#ibcon#read 5, iclass 35, count 0 2006.285.15:23:21.51#ibcon#about to read 6, iclass 35, count 0 2006.285.15:23:21.51#ibcon#read 6, iclass 35, count 0 2006.285.15:23:21.51#ibcon#end of sib2, iclass 35, count 0 2006.285.15:23:21.51#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:23:21.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:23:21.51#ibcon#[27=USB\r\n] 2006.285.15:23:21.51#ibcon#*before write, iclass 35, count 0 2006.285.15:23:21.51#ibcon#enter sib2, iclass 35, count 0 2006.285.15:23:21.51#ibcon#flushed, iclass 35, count 0 2006.285.15:23:21.51#ibcon#about to write, iclass 35, count 0 2006.285.15:23:21.51#ibcon#wrote, iclass 35, count 0 2006.285.15:23:21.51#ibcon#about to read 3, iclass 35, count 0 2006.285.15:23:21.54#ibcon#read 3, iclass 35, count 0 2006.285.15:23:21.54#ibcon#about to read 4, iclass 35, count 0 2006.285.15:23:21.54#ibcon#read 4, iclass 35, count 0 2006.285.15:23:21.54#ibcon#about to read 5, iclass 35, count 0 2006.285.15:23:21.54#ibcon#read 5, iclass 35, count 0 2006.285.15:23:21.54#ibcon#about to read 6, iclass 35, count 0 2006.285.15:23:21.54#ibcon#read 6, iclass 35, count 0 2006.285.15:23:21.54#ibcon#end of sib2, iclass 35, count 0 2006.285.15:23:21.54#ibcon#*after write, iclass 35, count 0 2006.285.15:23:21.54#ibcon#*before return 0, iclass 35, count 0 2006.285.15:23:21.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:23:21.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:23:21.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:23:21.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:23:21.54$vck44/vblo=5,709.99 2006.285.15:23:21.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.15:23:21.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.15:23:21.59#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:21.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:23:21.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:23:21.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:23:21.59#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:23:21.59#ibcon#first serial, iclass 37, count 0 2006.285.15:23:21.59#ibcon#enter sib2, iclass 37, count 0 2006.285.15:23:21.59#ibcon#flushed, iclass 37, count 0 2006.285.15:23:21.59#ibcon#about to write, iclass 37, count 0 2006.285.15:23:21.59#ibcon#wrote, iclass 37, count 0 2006.285.15:23:21.59#ibcon#about to read 3, iclass 37, count 0 2006.285.15:23:21.60#ibcon#read 3, iclass 37, count 0 2006.285.15:23:21.60#ibcon#about to read 4, iclass 37, count 0 2006.285.15:23:21.60#ibcon#read 4, iclass 37, count 0 2006.285.15:23:21.60#ibcon#about to read 5, iclass 37, count 0 2006.285.15:23:21.60#ibcon#read 5, iclass 37, count 0 2006.285.15:23:21.60#ibcon#about to read 6, iclass 37, count 0 2006.285.15:23:21.60#ibcon#read 6, iclass 37, count 0 2006.285.15:23:21.60#ibcon#end of sib2, iclass 37, count 0 2006.285.15:23:21.60#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:23:21.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:23:21.60#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.15:23:21.60#ibcon#*before write, iclass 37, count 0 2006.285.15:23:21.60#ibcon#enter sib2, iclass 37, count 0 2006.285.15:23:21.60#ibcon#flushed, iclass 37, count 0 2006.285.15:23:21.60#ibcon#about to write, iclass 37, count 0 2006.285.15:23:21.60#ibcon#wrote, iclass 37, count 0 2006.285.15:23:21.60#ibcon#about to read 3, iclass 37, count 0 2006.285.15:23:21.64#ibcon#read 3, iclass 37, count 0 2006.285.15:23:21.64#ibcon#about to read 4, iclass 37, count 0 2006.285.15:23:21.64#ibcon#read 4, iclass 37, count 0 2006.285.15:23:21.64#ibcon#about to read 5, iclass 37, count 0 2006.285.15:23:21.64#ibcon#read 5, iclass 37, count 0 2006.285.15:23:21.64#ibcon#about to read 6, iclass 37, count 0 2006.285.15:23:21.64#ibcon#read 6, iclass 37, count 0 2006.285.15:23:21.64#ibcon#end of sib2, iclass 37, count 0 2006.285.15:23:21.64#ibcon#*after write, iclass 37, count 0 2006.285.15:23:21.64#ibcon#*before return 0, iclass 37, count 0 2006.285.15:23:21.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:23:21.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:23:21.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:23:21.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:23:21.64$vck44/vb=5,4 2006.285.15:23:21.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.15:23:21.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.15:23:21.64#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:21.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:23:21.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:23:21.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:23:21.66#ibcon#enter wrdev, iclass 39, count 2 2006.285.15:23:21.66#ibcon#first serial, iclass 39, count 2 2006.285.15:23:21.66#ibcon#enter sib2, iclass 39, count 2 2006.285.15:23:21.66#ibcon#flushed, iclass 39, count 2 2006.285.15:23:21.66#ibcon#about to write, iclass 39, count 2 2006.285.15:23:21.66#ibcon#wrote, iclass 39, count 2 2006.285.15:23:21.66#ibcon#about to read 3, iclass 39, count 2 2006.285.15:23:21.68#ibcon#read 3, iclass 39, count 2 2006.285.15:23:21.68#ibcon#about to read 4, iclass 39, count 2 2006.285.15:23:21.68#ibcon#read 4, iclass 39, count 2 2006.285.15:23:21.68#ibcon#about to read 5, iclass 39, count 2 2006.285.15:23:21.68#ibcon#read 5, iclass 39, count 2 2006.285.15:23:21.68#ibcon#about to read 6, iclass 39, count 2 2006.285.15:23:21.68#ibcon#read 6, iclass 39, count 2 2006.285.15:23:21.68#ibcon#end of sib2, iclass 39, count 2 2006.285.15:23:21.68#ibcon#*mode == 0, iclass 39, count 2 2006.285.15:23:21.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.15:23:21.68#ibcon#[27=AT05-04\r\n] 2006.285.15:23:21.68#ibcon#*before write, iclass 39, count 2 2006.285.15:23:21.68#ibcon#enter sib2, iclass 39, count 2 2006.285.15:23:21.68#ibcon#flushed, iclass 39, count 2 2006.285.15:23:21.68#ibcon#about to write, iclass 39, count 2 2006.285.15:23:21.68#ibcon#wrote, iclass 39, count 2 2006.285.15:23:21.68#ibcon#about to read 3, iclass 39, count 2 2006.285.15:23:21.71#ibcon#read 3, iclass 39, count 2 2006.285.15:23:21.71#ibcon#about to read 4, iclass 39, count 2 2006.285.15:23:21.71#ibcon#read 4, iclass 39, count 2 2006.285.15:23:21.71#ibcon#about to read 5, iclass 39, count 2 2006.285.15:23:21.71#ibcon#read 5, iclass 39, count 2 2006.285.15:23:21.71#ibcon#about to read 6, iclass 39, count 2 2006.285.15:23:21.71#ibcon#read 6, iclass 39, count 2 2006.285.15:23:21.71#ibcon#end of sib2, iclass 39, count 2 2006.285.15:23:21.71#ibcon#*after write, iclass 39, count 2 2006.285.15:23:21.71#ibcon#*before return 0, iclass 39, count 2 2006.285.15:23:21.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:23:21.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:23:21.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.15:23:21.71#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:21.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:23:21.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:23:21.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:23:21.83#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:23:21.83#ibcon#first serial, iclass 39, count 0 2006.285.15:23:21.83#ibcon#enter sib2, iclass 39, count 0 2006.285.15:23:21.83#ibcon#flushed, iclass 39, count 0 2006.285.15:23:21.83#ibcon#about to write, iclass 39, count 0 2006.285.15:23:21.83#ibcon#wrote, iclass 39, count 0 2006.285.15:23:21.83#ibcon#about to read 3, iclass 39, count 0 2006.285.15:23:21.85#ibcon#read 3, iclass 39, count 0 2006.285.15:23:21.85#ibcon#about to read 4, iclass 39, count 0 2006.285.15:23:21.85#ibcon#read 4, iclass 39, count 0 2006.285.15:23:21.85#ibcon#about to read 5, iclass 39, count 0 2006.285.15:23:21.85#ibcon#read 5, iclass 39, count 0 2006.285.15:23:21.85#ibcon#about to read 6, iclass 39, count 0 2006.285.15:23:21.85#ibcon#read 6, iclass 39, count 0 2006.285.15:23:21.85#ibcon#end of sib2, iclass 39, count 0 2006.285.15:23:21.85#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:23:21.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:23:21.85#ibcon#[27=USB\r\n] 2006.285.15:23:21.85#ibcon#*before write, iclass 39, count 0 2006.285.15:23:21.85#ibcon#enter sib2, iclass 39, count 0 2006.285.15:23:21.85#ibcon#flushed, iclass 39, count 0 2006.285.15:23:21.85#ibcon#about to write, iclass 39, count 0 2006.285.15:23:21.85#ibcon#wrote, iclass 39, count 0 2006.285.15:23:21.85#ibcon#about to read 3, iclass 39, count 0 2006.285.15:23:21.88#ibcon#read 3, iclass 39, count 0 2006.285.15:23:21.88#ibcon#about to read 4, iclass 39, count 0 2006.285.15:23:21.88#ibcon#read 4, iclass 39, count 0 2006.285.15:23:21.88#ibcon#about to read 5, iclass 39, count 0 2006.285.15:23:21.88#ibcon#read 5, iclass 39, count 0 2006.285.15:23:21.88#ibcon#about to read 6, iclass 39, count 0 2006.285.15:23:21.88#ibcon#read 6, iclass 39, count 0 2006.285.15:23:21.88#ibcon#end of sib2, iclass 39, count 0 2006.285.15:23:21.88#ibcon#*after write, iclass 39, count 0 2006.285.15:23:21.88#ibcon#*before return 0, iclass 39, count 0 2006.285.15:23:21.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:23:21.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:23:21.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:23:21.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:23:21.88$vck44/vblo=6,719.99 2006.285.15:23:21.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.15:23:21.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.15:23:21.88#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:21.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:23:21.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:23:21.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:23:21.88#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:23:21.88#ibcon#first serial, iclass 3, count 0 2006.285.15:23:21.88#ibcon#enter sib2, iclass 3, count 0 2006.285.15:23:21.88#ibcon#flushed, iclass 3, count 0 2006.285.15:23:21.88#ibcon#about to write, iclass 3, count 0 2006.285.15:23:21.88#ibcon#wrote, iclass 3, count 0 2006.285.15:23:21.89#ibcon#about to read 3, iclass 3, count 0 2006.285.15:23:21.90#ibcon#read 3, iclass 3, count 0 2006.285.15:23:21.90#ibcon#about to read 4, iclass 3, count 0 2006.285.15:23:21.90#ibcon#read 4, iclass 3, count 0 2006.285.15:23:21.90#ibcon#about to read 5, iclass 3, count 0 2006.285.15:23:21.90#ibcon#read 5, iclass 3, count 0 2006.285.15:23:21.90#ibcon#about to read 6, iclass 3, count 0 2006.285.15:23:21.90#ibcon#read 6, iclass 3, count 0 2006.285.15:23:21.90#ibcon#end of sib2, iclass 3, count 0 2006.285.15:23:21.90#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:23:21.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:23:21.90#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.15:23:21.90#ibcon#*before write, iclass 3, count 0 2006.285.15:23:21.90#ibcon#enter sib2, iclass 3, count 0 2006.285.15:23:21.90#ibcon#flushed, iclass 3, count 0 2006.285.15:23:21.90#ibcon#about to write, iclass 3, count 0 2006.285.15:23:21.90#ibcon#wrote, iclass 3, count 0 2006.285.15:23:21.90#ibcon#about to read 3, iclass 3, count 0 2006.285.15:23:21.94#ibcon#read 3, iclass 3, count 0 2006.285.15:23:21.94#ibcon#about to read 4, iclass 3, count 0 2006.285.15:23:21.94#ibcon#read 4, iclass 3, count 0 2006.285.15:23:21.94#ibcon#about to read 5, iclass 3, count 0 2006.285.15:23:21.94#ibcon#read 5, iclass 3, count 0 2006.285.15:23:21.94#ibcon#about to read 6, iclass 3, count 0 2006.285.15:23:21.94#ibcon#read 6, iclass 3, count 0 2006.285.15:23:21.94#ibcon#end of sib2, iclass 3, count 0 2006.285.15:23:21.94#ibcon#*after write, iclass 3, count 0 2006.285.15:23:21.94#ibcon#*before return 0, iclass 3, count 0 2006.285.15:23:21.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:23:21.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:23:21.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:23:21.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:23:21.94$vck44/vb=6,3 2006.285.15:23:21.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.15:23:21.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.15:23:21.94#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:21.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:23:22.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:23:22.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:23:22.00#ibcon#enter wrdev, iclass 5, count 2 2006.285.15:23:22.00#ibcon#first serial, iclass 5, count 2 2006.285.15:23:22.00#ibcon#enter sib2, iclass 5, count 2 2006.285.15:23:22.00#ibcon#flushed, iclass 5, count 2 2006.285.15:23:22.00#ibcon#about to write, iclass 5, count 2 2006.285.15:23:22.00#ibcon#wrote, iclass 5, count 2 2006.285.15:23:22.00#ibcon#about to read 3, iclass 5, count 2 2006.285.15:23:22.02#ibcon#read 3, iclass 5, count 2 2006.285.15:23:22.02#ibcon#about to read 4, iclass 5, count 2 2006.285.15:23:22.02#ibcon#read 4, iclass 5, count 2 2006.285.15:23:22.02#ibcon#about to read 5, iclass 5, count 2 2006.285.15:23:22.02#ibcon#read 5, iclass 5, count 2 2006.285.15:23:22.02#ibcon#about to read 6, iclass 5, count 2 2006.285.15:23:22.02#ibcon#read 6, iclass 5, count 2 2006.285.15:23:22.02#ibcon#end of sib2, iclass 5, count 2 2006.285.15:23:22.02#ibcon#*mode == 0, iclass 5, count 2 2006.285.15:23:22.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.15:23:22.02#ibcon#[27=AT06-03\r\n] 2006.285.15:23:22.02#ibcon#*before write, iclass 5, count 2 2006.285.15:23:22.02#ibcon#enter sib2, iclass 5, count 2 2006.285.15:23:22.02#ibcon#flushed, iclass 5, count 2 2006.285.15:23:22.02#ibcon#about to write, iclass 5, count 2 2006.285.15:23:22.02#ibcon#wrote, iclass 5, count 2 2006.285.15:23:22.02#ibcon#about to read 3, iclass 5, count 2 2006.285.15:23:22.05#ibcon#read 3, iclass 5, count 2 2006.285.15:23:22.05#ibcon#about to read 4, iclass 5, count 2 2006.285.15:23:22.05#ibcon#read 4, iclass 5, count 2 2006.285.15:23:22.05#ibcon#about to read 5, iclass 5, count 2 2006.285.15:23:22.05#ibcon#read 5, iclass 5, count 2 2006.285.15:23:22.05#ibcon#about to read 6, iclass 5, count 2 2006.285.15:23:22.05#ibcon#read 6, iclass 5, count 2 2006.285.15:23:22.05#ibcon#end of sib2, iclass 5, count 2 2006.285.15:23:22.05#ibcon#*after write, iclass 5, count 2 2006.285.15:23:22.05#ibcon#*before return 0, iclass 5, count 2 2006.285.15:23:22.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:23:22.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:23:22.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.15:23:22.05#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:22.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:23:22.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:23:22.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:23:22.17#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:23:22.17#ibcon#first serial, iclass 5, count 0 2006.285.15:23:22.17#ibcon#enter sib2, iclass 5, count 0 2006.285.15:23:22.17#ibcon#flushed, iclass 5, count 0 2006.285.15:23:22.17#ibcon#about to write, iclass 5, count 0 2006.285.15:23:22.17#ibcon#wrote, iclass 5, count 0 2006.285.15:23:22.17#ibcon#about to read 3, iclass 5, count 0 2006.285.15:23:22.19#ibcon#read 3, iclass 5, count 0 2006.285.15:23:22.19#ibcon#about to read 4, iclass 5, count 0 2006.285.15:23:22.19#ibcon#read 4, iclass 5, count 0 2006.285.15:23:22.19#ibcon#about to read 5, iclass 5, count 0 2006.285.15:23:22.19#ibcon#read 5, iclass 5, count 0 2006.285.15:23:22.19#ibcon#about to read 6, iclass 5, count 0 2006.285.15:23:22.19#ibcon#read 6, iclass 5, count 0 2006.285.15:23:22.19#ibcon#end of sib2, iclass 5, count 0 2006.285.15:23:22.19#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:23:22.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:23:22.19#ibcon#[27=USB\r\n] 2006.285.15:23:22.19#ibcon#*before write, iclass 5, count 0 2006.285.15:23:22.19#ibcon#enter sib2, iclass 5, count 0 2006.285.15:23:22.19#ibcon#flushed, iclass 5, count 0 2006.285.15:23:22.19#ibcon#about to write, iclass 5, count 0 2006.285.15:23:22.19#ibcon#wrote, iclass 5, count 0 2006.285.15:23:22.19#ibcon#about to read 3, iclass 5, count 0 2006.285.15:23:22.22#ibcon#read 3, iclass 5, count 0 2006.285.15:23:22.22#ibcon#about to read 4, iclass 5, count 0 2006.285.15:23:22.22#ibcon#read 4, iclass 5, count 0 2006.285.15:23:22.22#ibcon#about to read 5, iclass 5, count 0 2006.285.15:23:22.22#ibcon#read 5, iclass 5, count 0 2006.285.15:23:22.22#ibcon#about to read 6, iclass 5, count 0 2006.285.15:23:22.22#ibcon#read 6, iclass 5, count 0 2006.285.15:23:22.22#ibcon#end of sib2, iclass 5, count 0 2006.285.15:23:22.22#ibcon#*after write, iclass 5, count 0 2006.285.15:23:22.22#ibcon#*before return 0, iclass 5, count 0 2006.285.15:23:22.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:23:22.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:23:22.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:23:22.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:23:22.22$vck44/vblo=7,734.99 2006.285.15:23:22.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.15:23:22.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.15:23:22.22#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:22.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:23:22.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:23:22.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:23:22.22#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:23:22.22#ibcon#first serial, iclass 7, count 0 2006.285.15:23:22.22#ibcon#enter sib2, iclass 7, count 0 2006.285.15:23:22.23#ibcon#flushed, iclass 7, count 0 2006.285.15:23:22.23#ibcon#about to write, iclass 7, count 0 2006.285.15:23:22.23#ibcon#wrote, iclass 7, count 0 2006.285.15:23:22.23#ibcon#about to read 3, iclass 7, count 0 2006.285.15:23:22.24#ibcon#read 3, iclass 7, count 0 2006.285.15:23:22.24#ibcon#about to read 4, iclass 7, count 0 2006.285.15:23:22.24#ibcon#read 4, iclass 7, count 0 2006.285.15:23:22.24#ibcon#about to read 5, iclass 7, count 0 2006.285.15:23:22.24#ibcon#read 5, iclass 7, count 0 2006.285.15:23:22.24#ibcon#about to read 6, iclass 7, count 0 2006.285.15:23:22.24#ibcon#read 6, iclass 7, count 0 2006.285.15:23:22.24#ibcon#end of sib2, iclass 7, count 0 2006.285.15:23:22.24#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:23:22.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:23:22.24#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.15:23:22.24#ibcon#*before write, iclass 7, count 0 2006.285.15:23:22.24#ibcon#enter sib2, iclass 7, count 0 2006.285.15:23:22.24#ibcon#flushed, iclass 7, count 0 2006.285.15:23:22.24#ibcon#about to write, iclass 7, count 0 2006.285.15:23:22.24#ibcon#wrote, iclass 7, count 0 2006.285.15:23:22.24#ibcon#about to read 3, iclass 7, count 0 2006.285.15:23:22.28#ibcon#read 3, iclass 7, count 0 2006.285.15:23:22.28#ibcon#about to read 4, iclass 7, count 0 2006.285.15:23:22.28#ibcon#read 4, iclass 7, count 0 2006.285.15:23:22.28#ibcon#about to read 5, iclass 7, count 0 2006.285.15:23:22.28#ibcon#read 5, iclass 7, count 0 2006.285.15:23:22.28#ibcon#about to read 6, iclass 7, count 0 2006.285.15:23:22.28#ibcon#read 6, iclass 7, count 0 2006.285.15:23:22.28#ibcon#end of sib2, iclass 7, count 0 2006.285.15:23:22.28#ibcon#*after write, iclass 7, count 0 2006.285.15:23:22.28#ibcon#*before return 0, iclass 7, count 0 2006.285.15:23:22.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:23:22.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:23:22.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:23:22.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:23:22.28$vck44/vb=7,4 2006.285.15:23:22.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.15:23:22.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.15:23:22.28#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:22.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:23:22.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:23:22.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:23:22.34#ibcon#enter wrdev, iclass 11, count 2 2006.285.15:23:22.34#ibcon#first serial, iclass 11, count 2 2006.285.15:23:22.34#ibcon#enter sib2, iclass 11, count 2 2006.285.15:23:22.34#ibcon#flushed, iclass 11, count 2 2006.285.15:23:22.34#ibcon#about to write, iclass 11, count 2 2006.285.15:23:22.34#ibcon#wrote, iclass 11, count 2 2006.285.15:23:22.34#ibcon#about to read 3, iclass 11, count 2 2006.285.15:23:22.36#ibcon#read 3, iclass 11, count 2 2006.285.15:23:22.36#ibcon#about to read 4, iclass 11, count 2 2006.285.15:23:22.36#ibcon#read 4, iclass 11, count 2 2006.285.15:23:22.36#ibcon#about to read 5, iclass 11, count 2 2006.285.15:23:22.36#ibcon#read 5, iclass 11, count 2 2006.285.15:23:22.36#ibcon#about to read 6, iclass 11, count 2 2006.285.15:23:22.36#ibcon#read 6, iclass 11, count 2 2006.285.15:23:22.36#ibcon#end of sib2, iclass 11, count 2 2006.285.15:23:22.36#ibcon#*mode == 0, iclass 11, count 2 2006.285.15:23:22.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.15:23:22.36#ibcon#[27=AT07-04\r\n] 2006.285.15:23:22.36#ibcon#*before write, iclass 11, count 2 2006.285.15:23:22.36#ibcon#enter sib2, iclass 11, count 2 2006.285.15:23:22.36#ibcon#flushed, iclass 11, count 2 2006.285.15:23:22.36#ibcon#about to write, iclass 11, count 2 2006.285.15:23:22.36#ibcon#wrote, iclass 11, count 2 2006.285.15:23:22.36#ibcon#about to read 3, iclass 11, count 2 2006.285.15:23:22.39#ibcon#read 3, iclass 11, count 2 2006.285.15:23:22.39#ibcon#about to read 4, iclass 11, count 2 2006.285.15:23:22.39#ibcon#read 4, iclass 11, count 2 2006.285.15:23:22.39#ibcon#about to read 5, iclass 11, count 2 2006.285.15:23:22.39#ibcon#read 5, iclass 11, count 2 2006.285.15:23:22.39#ibcon#about to read 6, iclass 11, count 2 2006.285.15:23:22.39#ibcon#read 6, iclass 11, count 2 2006.285.15:23:22.39#ibcon#end of sib2, iclass 11, count 2 2006.285.15:23:22.39#ibcon#*after write, iclass 11, count 2 2006.285.15:23:22.39#ibcon#*before return 0, iclass 11, count 2 2006.285.15:23:22.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:23:22.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:23:22.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.15:23:22.39#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:22.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:23:22.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:23:22.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:23:22.51#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:23:22.51#ibcon#first serial, iclass 11, count 0 2006.285.15:23:22.51#ibcon#enter sib2, iclass 11, count 0 2006.285.15:23:22.51#ibcon#flushed, iclass 11, count 0 2006.285.15:23:22.51#ibcon#about to write, iclass 11, count 0 2006.285.15:23:22.51#ibcon#wrote, iclass 11, count 0 2006.285.15:23:22.51#ibcon#about to read 3, iclass 11, count 0 2006.285.15:23:22.53#ibcon#read 3, iclass 11, count 0 2006.285.15:23:22.53#ibcon#about to read 4, iclass 11, count 0 2006.285.15:23:22.53#ibcon#read 4, iclass 11, count 0 2006.285.15:23:22.53#ibcon#about to read 5, iclass 11, count 0 2006.285.15:23:22.53#ibcon#read 5, iclass 11, count 0 2006.285.15:23:22.53#ibcon#about to read 6, iclass 11, count 0 2006.285.15:23:22.53#ibcon#read 6, iclass 11, count 0 2006.285.15:23:22.53#ibcon#end of sib2, iclass 11, count 0 2006.285.15:23:22.53#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:23:22.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:23:22.53#ibcon#[27=USB\r\n] 2006.285.15:23:22.53#ibcon#*before write, iclass 11, count 0 2006.285.15:23:22.53#ibcon#enter sib2, iclass 11, count 0 2006.285.15:23:22.53#ibcon#flushed, iclass 11, count 0 2006.285.15:23:22.53#ibcon#about to write, iclass 11, count 0 2006.285.15:23:22.53#ibcon#wrote, iclass 11, count 0 2006.285.15:23:22.53#ibcon#about to read 3, iclass 11, count 0 2006.285.15:23:22.56#ibcon#read 3, iclass 11, count 0 2006.285.15:23:22.56#ibcon#about to read 4, iclass 11, count 0 2006.285.15:23:22.56#ibcon#read 4, iclass 11, count 0 2006.285.15:23:22.56#ibcon#about to read 5, iclass 11, count 0 2006.285.15:23:22.56#ibcon#read 5, iclass 11, count 0 2006.285.15:23:22.56#ibcon#about to read 6, iclass 11, count 0 2006.285.15:23:22.56#ibcon#read 6, iclass 11, count 0 2006.285.15:23:22.56#ibcon#end of sib2, iclass 11, count 0 2006.285.15:23:22.56#ibcon#*after write, iclass 11, count 0 2006.285.15:23:22.56#ibcon#*before return 0, iclass 11, count 0 2006.285.15:23:22.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:23:22.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:23:22.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:23:22.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:23:22.56$vck44/vblo=8,744.99 2006.285.15:23:22.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.15:23:22.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.15:23:22.65#ibcon#ireg 17 cls_cnt 0 2006.285.15:23:22.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:23:22.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:23:22.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:23:22.65#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:23:22.65#ibcon#first serial, iclass 13, count 0 2006.285.15:23:22.65#ibcon#enter sib2, iclass 13, count 0 2006.285.15:23:22.65#ibcon#flushed, iclass 13, count 0 2006.285.15:23:22.65#ibcon#about to write, iclass 13, count 0 2006.285.15:23:22.65#ibcon#wrote, iclass 13, count 0 2006.285.15:23:22.65#ibcon#about to read 3, iclass 13, count 0 2006.285.15:23:22.66#ibcon#read 3, iclass 13, count 0 2006.285.15:23:22.66#ibcon#about to read 4, iclass 13, count 0 2006.285.15:23:22.66#ibcon#read 4, iclass 13, count 0 2006.285.15:23:22.66#ibcon#about to read 5, iclass 13, count 0 2006.285.15:23:22.66#ibcon#read 5, iclass 13, count 0 2006.285.15:23:22.66#ibcon#about to read 6, iclass 13, count 0 2006.285.15:23:22.66#ibcon#read 6, iclass 13, count 0 2006.285.15:23:22.66#ibcon#end of sib2, iclass 13, count 0 2006.285.15:23:22.66#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:23:22.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:23:22.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.15:23:22.66#ibcon#*before write, iclass 13, count 0 2006.285.15:23:22.66#ibcon#enter sib2, iclass 13, count 0 2006.285.15:23:22.66#ibcon#flushed, iclass 13, count 0 2006.285.15:23:22.66#ibcon#about to write, iclass 13, count 0 2006.285.15:23:22.66#ibcon#wrote, iclass 13, count 0 2006.285.15:23:22.66#ibcon#about to read 3, iclass 13, count 0 2006.285.15:23:22.70#ibcon#read 3, iclass 13, count 0 2006.285.15:23:22.70#ibcon#about to read 4, iclass 13, count 0 2006.285.15:23:22.70#ibcon#read 4, iclass 13, count 0 2006.285.15:23:22.70#ibcon#about to read 5, iclass 13, count 0 2006.285.15:23:22.70#ibcon#read 5, iclass 13, count 0 2006.285.15:23:22.70#ibcon#about to read 6, iclass 13, count 0 2006.285.15:23:22.70#ibcon#read 6, iclass 13, count 0 2006.285.15:23:22.70#ibcon#end of sib2, iclass 13, count 0 2006.285.15:23:22.70#ibcon#*after write, iclass 13, count 0 2006.285.15:23:22.70#ibcon#*before return 0, iclass 13, count 0 2006.285.15:23:22.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:23:22.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:23:22.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:23:22.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:23:22.70$vck44/vb=8,4 2006.285.15:23:22.70#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.15:23:22.70#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.15:23:22.70#ibcon#ireg 11 cls_cnt 2 2006.285.15:23:22.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:23:22.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:23:22.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:23:22.70#ibcon#enter wrdev, iclass 15, count 2 2006.285.15:23:22.70#ibcon#first serial, iclass 15, count 2 2006.285.15:23:22.70#ibcon#enter sib2, iclass 15, count 2 2006.285.15:23:22.71#ibcon#flushed, iclass 15, count 2 2006.285.15:23:22.71#ibcon#about to write, iclass 15, count 2 2006.285.15:23:22.71#ibcon#wrote, iclass 15, count 2 2006.285.15:23:22.71#ibcon#about to read 3, iclass 15, count 2 2006.285.15:23:22.72#ibcon#read 3, iclass 15, count 2 2006.285.15:23:22.72#ibcon#about to read 4, iclass 15, count 2 2006.285.15:23:22.72#ibcon#read 4, iclass 15, count 2 2006.285.15:23:22.72#ibcon#about to read 5, iclass 15, count 2 2006.285.15:23:22.72#ibcon#read 5, iclass 15, count 2 2006.285.15:23:22.72#ibcon#about to read 6, iclass 15, count 2 2006.285.15:23:22.72#ibcon#read 6, iclass 15, count 2 2006.285.15:23:22.72#ibcon#end of sib2, iclass 15, count 2 2006.285.15:23:22.72#ibcon#*mode == 0, iclass 15, count 2 2006.285.15:23:22.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.15:23:22.72#ibcon#[27=AT08-04\r\n] 2006.285.15:23:22.72#ibcon#*before write, iclass 15, count 2 2006.285.15:23:22.72#ibcon#enter sib2, iclass 15, count 2 2006.285.15:23:22.72#ibcon#flushed, iclass 15, count 2 2006.285.15:23:22.72#ibcon#about to write, iclass 15, count 2 2006.285.15:23:22.72#ibcon#wrote, iclass 15, count 2 2006.285.15:23:22.72#ibcon#about to read 3, iclass 15, count 2 2006.285.15:23:22.75#ibcon#read 3, iclass 15, count 2 2006.285.15:23:22.75#ibcon#about to read 4, iclass 15, count 2 2006.285.15:23:22.75#ibcon#read 4, iclass 15, count 2 2006.285.15:23:22.75#ibcon#about to read 5, iclass 15, count 2 2006.285.15:23:22.75#ibcon#read 5, iclass 15, count 2 2006.285.15:23:22.75#ibcon#about to read 6, iclass 15, count 2 2006.285.15:23:22.75#ibcon#read 6, iclass 15, count 2 2006.285.15:23:22.75#ibcon#end of sib2, iclass 15, count 2 2006.285.15:23:22.75#ibcon#*after write, iclass 15, count 2 2006.285.15:23:22.75#ibcon#*before return 0, iclass 15, count 2 2006.285.15:23:22.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:23:22.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:23:22.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.15:23:22.75#ibcon#ireg 7 cls_cnt 0 2006.285.15:23:22.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:23:22.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:23:22.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:23:22.87#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:23:22.87#ibcon#first serial, iclass 15, count 0 2006.285.15:23:22.87#ibcon#enter sib2, iclass 15, count 0 2006.285.15:23:22.87#ibcon#flushed, iclass 15, count 0 2006.285.15:23:22.87#ibcon#about to write, iclass 15, count 0 2006.285.15:23:22.87#ibcon#wrote, iclass 15, count 0 2006.285.15:23:22.87#ibcon#about to read 3, iclass 15, count 0 2006.285.15:23:22.89#ibcon#read 3, iclass 15, count 0 2006.285.15:23:22.89#ibcon#about to read 4, iclass 15, count 0 2006.285.15:23:22.89#ibcon#read 4, iclass 15, count 0 2006.285.15:23:22.89#ibcon#about to read 5, iclass 15, count 0 2006.285.15:23:22.89#ibcon#read 5, iclass 15, count 0 2006.285.15:23:22.89#ibcon#about to read 6, iclass 15, count 0 2006.285.15:23:22.89#ibcon#read 6, iclass 15, count 0 2006.285.15:23:22.89#ibcon#end of sib2, iclass 15, count 0 2006.285.15:23:22.89#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:23:22.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:23:22.89#ibcon#[27=USB\r\n] 2006.285.15:23:22.89#ibcon#*before write, iclass 15, count 0 2006.285.15:23:22.89#ibcon#enter sib2, iclass 15, count 0 2006.285.15:23:22.89#ibcon#flushed, iclass 15, count 0 2006.285.15:23:22.89#ibcon#about to write, iclass 15, count 0 2006.285.15:23:22.89#ibcon#wrote, iclass 15, count 0 2006.285.15:23:22.89#ibcon#about to read 3, iclass 15, count 0 2006.285.15:23:22.92#ibcon#read 3, iclass 15, count 0 2006.285.15:23:22.92#ibcon#about to read 4, iclass 15, count 0 2006.285.15:23:22.92#ibcon#read 4, iclass 15, count 0 2006.285.15:23:22.92#ibcon#about to read 5, iclass 15, count 0 2006.285.15:23:22.92#ibcon#read 5, iclass 15, count 0 2006.285.15:23:22.92#ibcon#about to read 6, iclass 15, count 0 2006.285.15:23:22.92#ibcon#read 6, iclass 15, count 0 2006.285.15:23:22.92#ibcon#end of sib2, iclass 15, count 0 2006.285.15:23:22.92#ibcon#*after write, iclass 15, count 0 2006.285.15:23:22.92#ibcon#*before return 0, iclass 15, count 0 2006.285.15:23:22.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:23:22.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:23:22.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:23:22.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:23:22.92$vck44/vabw=wide 2006.285.15:23:22.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.15:23:22.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.15:23:22.92#ibcon#ireg 8 cls_cnt 0 2006.285.15:23:22.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:23:22.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:23:22.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:23:22.92#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:23:22.92#ibcon#first serial, iclass 17, count 0 2006.285.15:23:22.92#ibcon#enter sib2, iclass 17, count 0 2006.285.15:23:22.92#ibcon#flushed, iclass 17, count 0 2006.285.15:23:22.92#ibcon#about to write, iclass 17, count 0 2006.285.15:23:22.92#ibcon#wrote, iclass 17, count 0 2006.285.15:23:22.92#ibcon#about to read 3, iclass 17, count 0 2006.285.15:23:22.94#ibcon#read 3, iclass 17, count 0 2006.285.15:23:22.94#ibcon#about to read 4, iclass 17, count 0 2006.285.15:23:22.94#ibcon#read 4, iclass 17, count 0 2006.285.15:23:22.94#ibcon#about to read 5, iclass 17, count 0 2006.285.15:23:22.94#ibcon#read 5, iclass 17, count 0 2006.285.15:23:22.94#ibcon#about to read 6, iclass 17, count 0 2006.285.15:23:22.94#ibcon#read 6, iclass 17, count 0 2006.285.15:23:22.94#ibcon#end of sib2, iclass 17, count 0 2006.285.15:23:22.94#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:23:22.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:23:22.94#ibcon#[25=BW32\r\n] 2006.285.15:23:22.94#ibcon#*before write, iclass 17, count 0 2006.285.15:23:22.94#ibcon#enter sib2, iclass 17, count 0 2006.285.15:23:22.94#ibcon#flushed, iclass 17, count 0 2006.285.15:23:22.94#ibcon#about to write, iclass 17, count 0 2006.285.15:23:22.94#ibcon#wrote, iclass 17, count 0 2006.285.15:23:22.94#ibcon#about to read 3, iclass 17, count 0 2006.285.15:23:22.97#ibcon#read 3, iclass 17, count 0 2006.285.15:23:22.97#ibcon#about to read 4, iclass 17, count 0 2006.285.15:23:22.97#ibcon#read 4, iclass 17, count 0 2006.285.15:23:22.97#ibcon#about to read 5, iclass 17, count 0 2006.285.15:23:22.97#ibcon#read 5, iclass 17, count 0 2006.285.15:23:22.97#ibcon#about to read 6, iclass 17, count 0 2006.285.15:23:22.97#ibcon#read 6, iclass 17, count 0 2006.285.15:23:22.97#ibcon#end of sib2, iclass 17, count 0 2006.285.15:23:22.97#ibcon#*after write, iclass 17, count 0 2006.285.15:23:22.97#ibcon#*before return 0, iclass 17, count 0 2006.285.15:23:22.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:23:22.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:23:22.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:23:22.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:23:22.97$vck44/vbbw=wide 2006.285.15:23:22.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.15:23:22.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.15:23:22.97#ibcon#ireg 8 cls_cnt 0 2006.285.15:23:22.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:23:23.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:23:23.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:23:23.04#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:23:23.04#ibcon#first serial, iclass 19, count 0 2006.285.15:23:23.04#ibcon#enter sib2, iclass 19, count 0 2006.285.15:23:23.04#ibcon#flushed, iclass 19, count 0 2006.285.15:23:23.04#ibcon#about to write, iclass 19, count 0 2006.285.15:23:23.04#ibcon#wrote, iclass 19, count 0 2006.285.15:23:23.04#ibcon#about to read 3, iclass 19, count 0 2006.285.15:23:23.06#ibcon#read 3, iclass 19, count 0 2006.285.15:23:23.06#ibcon#about to read 4, iclass 19, count 0 2006.285.15:23:23.06#ibcon#read 4, iclass 19, count 0 2006.285.15:23:23.06#ibcon#about to read 5, iclass 19, count 0 2006.285.15:23:23.06#ibcon#read 5, iclass 19, count 0 2006.285.15:23:23.06#ibcon#about to read 6, iclass 19, count 0 2006.285.15:23:23.06#ibcon#read 6, iclass 19, count 0 2006.285.15:23:23.06#ibcon#end of sib2, iclass 19, count 0 2006.285.15:23:23.06#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:23:23.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:23:23.06#ibcon#[27=BW32\r\n] 2006.285.15:23:23.06#ibcon#*before write, iclass 19, count 0 2006.285.15:23:23.06#ibcon#enter sib2, iclass 19, count 0 2006.285.15:23:23.06#ibcon#flushed, iclass 19, count 0 2006.285.15:23:23.06#ibcon#about to write, iclass 19, count 0 2006.285.15:23:23.06#ibcon#wrote, iclass 19, count 0 2006.285.15:23:23.06#ibcon#about to read 3, iclass 19, count 0 2006.285.15:23:23.09#ibcon#read 3, iclass 19, count 0 2006.285.15:23:23.09#ibcon#about to read 4, iclass 19, count 0 2006.285.15:23:23.09#ibcon#read 4, iclass 19, count 0 2006.285.15:23:23.09#ibcon#about to read 5, iclass 19, count 0 2006.285.15:23:23.09#ibcon#read 5, iclass 19, count 0 2006.285.15:23:23.09#ibcon#about to read 6, iclass 19, count 0 2006.285.15:23:23.09#ibcon#read 6, iclass 19, count 0 2006.285.15:23:23.09#ibcon#end of sib2, iclass 19, count 0 2006.285.15:23:23.09#ibcon#*after write, iclass 19, count 0 2006.285.15:23:23.09#ibcon#*before return 0, iclass 19, count 0 2006.285.15:23:23.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:23:23.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:23:23.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:23:23.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:23:23.09$setupk4/ifdk4 2006.285.15:23:23.09$ifdk4/lo= 2006.285.15:23:23.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.15:23:23.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.15:23:23.10$ifdk4/patch= 2006.285.15:23:23.10$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.15:23:23.10$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.15:23:23.10$setupk4/!*+20s 2006.285.15:23:25.00#abcon#<5=/03 1.1 2.7 19.10 921014.9\r\n> 2006.285.15:23:25.02#abcon#{5=INTERFACE CLEAR} 2006.285.15:23:25.08#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:23:27.14#trakl#Source acquired 2006.285.15:23:29.14#flagr#flagr/antenna,acquired 2006.285.15:23:35.17#abcon#<5=/03 1.1 2.7 19.10 921014.9\r\n> 2006.285.15:23:35.19#abcon#{5=INTERFACE CLEAR} 2006.285.15:23:35.25#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:23:36.92$setupk4/"tpicd 2006.285.15:23:36.92$setupk4/echo=off 2006.285.15:23:36.92$setupk4/xlog=off 2006.285.15:23:36.92:!2006.285.15:28:52 2006.285.15:28:52.00:preob 2006.285.15:28:52.13/onsource/TRACKING 2006.285.15:28:52.13:!2006.285.15:29:02 2006.285.15:29:02.00:"tape 2006.285.15:29:02.00:"st=record 2006.285.15:29:02.00:data_valid=on 2006.285.15:29:02.00:midob 2006.285.15:29:02.13/onsource/TRACKING 2006.285.15:29:02.13/wx/19.07,1014.9,92 2006.285.15:29:02.26/cable/+6.4985E-03 2006.285.15:29:03.35/va/01,07,usb,yes,34,36 2006.285.15:29:03.35/va/02,06,usb,yes,34,34 2006.285.15:29:03.35/va/03,07,usb,yes,33,35 2006.285.15:29:03.35/va/04,06,usb,yes,35,36 2006.285.15:29:03.35/va/05,03,usb,yes,34,35 2006.285.15:29:03.35/va/06,04,usb,yes,31,30 2006.285.15:29:03.35/va/07,04,usb,yes,31,32 2006.285.15:29:03.35/va/08,03,usb,yes,32,39 2006.285.15:29:03.58/valo/01,524.99,yes,locked 2006.285.15:29:03.58/valo/02,534.99,yes,locked 2006.285.15:29:03.58/valo/03,564.99,yes,locked 2006.285.15:29:03.58/valo/04,624.99,yes,locked 2006.285.15:29:03.58/valo/05,734.99,yes,locked 2006.285.15:29:03.58/valo/06,814.99,yes,locked 2006.285.15:29:03.58/valo/07,864.99,yes,locked 2006.285.15:29:03.58/valo/08,884.99,yes,locked 2006.285.15:29:04.67/vb/01,04,usb,yes,31,29 2006.285.15:29:04.67/vb/02,05,usb,yes,29,29 2006.285.15:29:04.67/vb/03,04,usb,yes,30,33 2006.285.15:29:04.67/vb/04,05,usb,yes,31,29 2006.285.15:29:04.67/vb/05,04,usb,yes,27,30 2006.285.15:29:04.67/vb/06,03,usb,yes,39,35 2006.285.15:29:04.67/vb/07,04,usb,yes,31,31 2006.285.15:29:04.67/vb/08,04,usb,yes,28,32 2006.285.15:29:04.90/vblo/01,629.99,yes,locked 2006.285.15:29:04.90/vblo/02,634.99,yes,locked 2006.285.15:29:04.90/vblo/03,649.99,yes,locked 2006.285.15:29:04.90/vblo/04,679.99,yes,locked 2006.285.15:29:04.90/vblo/05,709.99,yes,locked 2006.285.15:29:04.90/vblo/06,719.99,yes,locked 2006.285.15:29:04.90/vblo/07,734.99,yes,locked 2006.285.15:29:04.90/vblo/08,744.99,yes,locked 2006.285.15:29:05.05/vabw/8 2006.285.15:29:05.20/vbbw/8 2006.285.15:29:05.29/xfe/off,on,12.2 2006.285.15:29:05.67/ifatt/23,28,28,28 2006.285.15:29:06.07/fmout-gps/S +2.78E-07 2006.285.15:29:06.09:!2006.285.15:30:12 2006.285.15:30:12.00:data_valid=off 2006.285.15:30:12.00:"et 2006.285.15:30:12.00:!+3s 2006.285.15:30:15.01:"tape 2006.285.15:30:15.01:postob 2006.285.15:30:15.14/cable/+6.5011E-03 2006.285.15:30:15.14/wx/19.06,1014.9,92 2006.285.15:30:16.07/fmout-gps/S +2.77E-07 2006.285.15:30:16.07:scan_name=285-1531,jd0610,190 2006.285.15:30:16.07:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.285.15:30:17.14#flagr#flagr/antenna,new-source 2006.285.15:30:17.14:checkk5 2006.285.15:30:17.69/chk_autoobs//k5ts1/ autoobs is running! 2006.285.15:30:18.15/chk_autoobs//k5ts2/ autoobs is running! 2006.285.15:30:18.82/chk_autoobs//k5ts3/ autoobs is running! 2006.285.15:30:19.18/chk_autoobs//k5ts4/ autoobs is running! 2006.285.15:30:19.66/chk_obsdata//k5ts1/T2851529??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.15:30:20.04/chk_obsdata//k5ts2/T2851529??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.15:30:20.43/chk_obsdata//k5ts3/T2851529??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.15:30:21.05/chk_obsdata//k5ts4/T2851529??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.15:30:21.93/k5log//k5ts1_log_newline 2006.285.15:30:22.99/k5log//k5ts2_log_newline 2006.285.15:30:23.79/k5log//k5ts3_log_newline 2006.285.15:30:24.67/k5log//k5ts4_log_newline 2006.285.15:30:24.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.15:30:24.69:setupk4=1 2006.285.15:30:24.69$setupk4/echo=on 2006.285.15:30:24.69$setupk4/pcalon 2006.285.15:30:24.69$pcalon/"no phase cal control is implemented here 2006.285.15:30:24.69$setupk4/"tpicd=stop 2006.285.15:30:24.69$setupk4/"rec=synch_on 2006.285.15:30:24.69$setupk4/"rec_mode=128 2006.285.15:30:24.69$setupk4/!* 2006.285.15:30:24.69$setupk4/recpk4 2006.285.15:30:24.69$recpk4/recpatch= 2006.285.15:30:24.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.15:30:24.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.15:30:24.69$setupk4/vck44 2006.285.15:30:24.69$vck44/valo=1,524.99 2006.285.15:30:24.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.15:30:24.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.15:30:24.69#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:24.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:30:24.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:30:24.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:30:24.69#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:30:24.69#ibcon#first serial, iclass 39, count 0 2006.285.15:30:24.69#ibcon#enter sib2, iclass 39, count 0 2006.285.15:30:24.69#ibcon#flushed, iclass 39, count 0 2006.285.15:30:24.69#ibcon#about to write, iclass 39, count 0 2006.285.15:30:24.69#ibcon#wrote, iclass 39, count 0 2006.285.15:30:24.69#ibcon#about to read 3, iclass 39, count 0 2006.285.15:30:24.71#ibcon#read 3, iclass 39, count 0 2006.285.15:30:24.71#ibcon#about to read 4, iclass 39, count 0 2006.285.15:30:24.71#ibcon#read 4, iclass 39, count 0 2006.285.15:30:24.71#ibcon#about to read 5, iclass 39, count 0 2006.285.15:30:24.71#ibcon#read 5, iclass 39, count 0 2006.285.15:30:24.71#ibcon#about to read 6, iclass 39, count 0 2006.285.15:30:24.71#ibcon#read 6, iclass 39, count 0 2006.285.15:30:24.71#ibcon#end of sib2, iclass 39, count 0 2006.285.15:30:24.71#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:30:24.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:30:24.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.15:30:24.71#ibcon#*before write, iclass 39, count 0 2006.285.15:30:24.71#ibcon#enter sib2, iclass 39, count 0 2006.285.15:30:24.71#ibcon#flushed, iclass 39, count 0 2006.285.15:30:24.71#ibcon#about to write, iclass 39, count 0 2006.285.15:30:24.71#ibcon#wrote, iclass 39, count 0 2006.285.15:30:24.71#ibcon#about to read 3, iclass 39, count 0 2006.285.15:30:24.76#ibcon#read 3, iclass 39, count 0 2006.285.15:30:24.76#ibcon#about to read 4, iclass 39, count 0 2006.285.15:30:24.76#ibcon#read 4, iclass 39, count 0 2006.285.15:30:24.76#ibcon#about to read 5, iclass 39, count 0 2006.285.15:30:24.76#ibcon#read 5, iclass 39, count 0 2006.285.15:30:24.76#ibcon#about to read 6, iclass 39, count 0 2006.285.15:30:24.76#ibcon#read 6, iclass 39, count 0 2006.285.15:30:24.76#ibcon#end of sib2, iclass 39, count 0 2006.285.15:30:24.76#ibcon#*after write, iclass 39, count 0 2006.285.15:30:24.76#ibcon#*before return 0, iclass 39, count 0 2006.285.15:30:24.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:30:24.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:30:24.76#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:30:24.76#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:30:24.76$vck44/va=1,7 2006.285.15:30:24.76#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.15:30:24.76#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.15:30:24.76#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:24.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:30:24.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:30:24.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:30:24.76#ibcon#enter wrdev, iclass 4, count 2 2006.285.15:30:24.76#ibcon#first serial, iclass 4, count 2 2006.285.15:30:24.76#ibcon#enter sib2, iclass 4, count 2 2006.285.15:30:24.76#ibcon#flushed, iclass 4, count 2 2006.285.15:30:24.76#ibcon#about to write, iclass 4, count 2 2006.285.15:30:24.76#ibcon#wrote, iclass 4, count 2 2006.285.15:30:24.76#ibcon#about to read 3, iclass 4, count 2 2006.285.15:30:24.78#ibcon#read 3, iclass 4, count 2 2006.285.15:30:24.78#ibcon#about to read 4, iclass 4, count 2 2006.285.15:30:24.78#ibcon#read 4, iclass 4, count 2 2006.285.15:30:24.78#ibcon#about to read 5, iclass 4, count 2 2006.285.15:30:24.78#ibcon#read 5, iclass 4, count 2 2006.285.15:30:24.78#ibcon#about to read 6, iclass 4, count 2 2006.285.15:30:24.78#ibcon#read 6, iclass 4, count 2 2006.285.15:30:24.78#ibcon#end of sib2, iclass 4, count 2 2006.285.15:30:24.78#ibcon#*mode == 0, iclass 4, count 2 2006.285.15:30:24.78#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.15:30:24.78#ibcon#[25=AT01-07\r\n] 2006.285.15:30:24.78#ibcon#*before write, iclass 4, count 2 2006.285.15:30:24.78#ibcon#enter sib2, iclass 4, count 2 2006.285.15:30:24.78#ibcon#flushed, iclass 4, count 2 2006.285.15:30:24.78#ibcon#about to write, iclass 4, count 2 2006.285.15:30:24.78#ibcon#wrote, iclass 4, count 2 2006.285.15:30:24.78#ibcon#about to read 3, iclass 4, count 2 2006.285.15:30:24.80#abcon#<5=/02 1.0 3.5 19.05 921015.0\r\n> 2006.285.15:30:24.81#ibcon#read 3, iclass 4, count 2 2006.285.15:30:24.81#ibcon#about to read 4, iclass 4, count 2 2006.285.15:30:24.81#ibcon#read 4, iclass 4, count 2 2006.285.15:30:24.81#ibcon#about to read 5, iclass 4, count 2 2006.285.15:30:24.81#ibcon#read 5, iclass 4, count 2 2006.285.15:30:24.81#ibcon#about to read 6, iclass 4, count 2 2006.285.15:30:24.81#ibcon#read 6, iclass 4, count 2 2006.285.15:30:24.81#ibcon#end of sib2, iclass 4, count 2 2006.285.15:30:24.81#ibcon#*after write, iclass 4, count 2 2006.285.15:30:24.81#ibcon#*before return 0, iclass 4, count 2 2006.285.15:30:24.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:30:24.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:30:24.81#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.15:30:24.81#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:24.81#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:30:24.82#abcon#{5=INTERFACE CLEAR} 2006.285.15:30:24.88#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:30:24.93#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:30:24.93#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:30:24.93#ibcon#enter wrdev, iclass 4, count 0 2006.285.15:30:24.93#ibcon#first serial, iclass 4, count 0 2006.285.15:30:24.93#ibcon#enter sib2, iclass 4, count 0 2006.285.15:30:24.93#ibcon#flushed, iclass 4, count 0 2006.285.15:30:24.93#ibcon#about to write, iclass 4, count 0 2006.285.15:30:24.93#ibcon#wrote, iclass 4, count 0 2006.285.15:30:24.93#ibcon#about to read 3, iclass 4, count 0 2006.285.15:30:24.95#ibcon#read 3, iclass 4, count 0 2006.285.15:30:24.95#ibcon#about to read 4, iclass 4, count 0 2006.285.15:30:24.95#ibcon#read 4, iclass 4, count 0 2006.285.15:30:24.95#ibcon#about to read 5, iclass 4, count 0 2006.285.15:30:24.95#ibcon#read 5, iclass 4, count 0 2006.285.15:30:24.95#ibcon#about to read 6, iclass 4, count 0 2006.285.15:30:24.95#ibcon#read 6, iclass 4, count 0 2006.285.15:30:24.95#ibcon#end of sib2, iclass 4, count 0 2006.285.15:30:24.95#ibcon#*mode == 0, iclass 4, count 0 2006.285.15:30:24.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.15:30:24.95#ibcon#[25=USB\r\n] 2006.285.15:30:24.95#ibcon#*before write, iclass 4, count 0 2006.285.15:30:24.95#ibcon#enter sib2, iclass 4, count 0 2006.285.15:30:24.95#ibcon#flushed, iclass 4, count 0 2006.285.15:30:24.95#ibcon#about to write, iclass 4, count 0 2006.285.15:30:24.95#ibcon#wrote, iclass 4, count 0 2006.285.15:30:24.95#ibcon#about to read 3, iclass 4, count 0 2006.285.15:30:24.98#ibcon#read 3, iclass 4, count 0 2006.285.15:30:24.98#ibcon#about to read 4, iclass 4, count 0 2006.285.15:30:24.98#ibcon#read 4, iclass 4, count 0 2006.285.15:30:24.98#ibcon#about to read 5, iclass 4, count 0 2006.285.15:30:24.98#ibcon#read 5, iclass 4, count 0 2006.285.15:30:24.98#ibcon#about to read 6, iclass 4, count 0 2006.285.15:30:24.98#ibcon#read 6, iclass 4, count 0 2006.285.15:30:24.98#ibcon#end of sib2, iclass 4, count 0 2006.285.15:30:24.98#ibcon#*after write, iclass 4, count 0 2006.285.15:30:24.98#ibcon#*before return 0, iclass 4, count 0 2006.285.15:30:24.98#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:30:24.98#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:30:24.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.15:30:24.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.15:30:24.98$vck44/valo=2,534.99 2006.285.15:30:24.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.15:30:24.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.15:30:24.98#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:24.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:30:24.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:30:24.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:30:24.98#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:30:24.98#ibcon#first serial, iclass 11, count 0 2006.285.15:30:24.98#ibcon#enter sib2, iclass 11, count 0 2006.285.15:30:24.98#ibcon#flushed, iclass 11, count 0 2006.285.15:30:24.98#ibcon#about to write, iclass 11, count 0 2006.285.15:30:24.98#ibcon#wrote, iclass 11, count 0 2006.285.15:30:24.98#ibcon#about to read 3, iclass 11, count 0 2006.285.15:30:25.00#ibcon#read 3, iclass 11, count 0 2006.285.15:30:25.00#ibcon#about to read 4, iclass 11, count 0 2006.285.15:30:25.00#ibcon#read 4, iclass 11, count 0 2006.285.15:30:25.00#ibcon#about to read 5, iclass 11, count 0 2006.285.15:30:25.00#ibcon#read 5, iclass 11, count 0 2006.285.15:30:25.00#ibcon#about to read 6, iclass 11, count 0 2006.285.15:30:25.00#ibcon#read 6, iclass 11, count 0 2006.285.15:30:25.00#ibcon#end of sib2, iclass 11, count 0 2006.285.15:30:25.00#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:30:25.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:30:25.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.15:30:25.00#ibcon#*before write, iclass 11, count 0 2006.285.15:30:25.00#ibcon#enter sib2, iclass 11, count 0 2006.285.15:30:25.00#ibcon#flushed, iclass 11, count 0 2006.285.15:30:25.00#ibcon#about to write, iclass 11, count 0 2006.285.15:30:25.00#ibcon#wrote, iclass 11, count 0 2006.285.15:30:25.00#ibcon#about to read 3, iclass 11, count 0 2006.285.15:30:25.04#ibcon#read 3, iclass 11, count 0 2006.285.15:30:25.04#ibcon#about to read 4, iclass 11, count 0 2006.285.15:30:25.04#ibcon#read 4, iclass 11, count 0 2006.285.15:30:25.04#ibcon#about to read 5, iclass 11, count 0 2006.285.15:30:25.04#ibcon#read 5, iclass 11, count 0 2006.285.15:30:25.04#ibcon#about to read 6, iclass 11, count 0 2006.285.15:30:25.04#ibcon#read 6, iclass 11, count 0 2006.285.15:30:25.04#ibcon#end of sib2, iclass 11, count 0 2006.285.15:30:25.04#ibcon#*after write, iclass 11, count 0 2006.285.15:30:25.04#ibcon#*before return 0, iclass 11, count 0 2006.285.15:30:25.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:30:25.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:30:25.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:30:25.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:30:25.04$vck44/va=2,6 2006.285.15:30:25.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.15:30:25.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.15:30:25.04#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:25.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:30:25.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:30:25.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:30:25.10#ibcon#enter wrdev, iclass 13, count 2 2006.285.15:30:25.10#ibcon#first serial, iclass 13, count 2 2006.285.15:30:25.10#ibcon#enter sib2, iclass 13, count 2 2006.285.15:30:25.10#ibcon#flushed, iclass 13, count 2 2006.285.15:30:25.10#ibcon#about to write, iclass 13, count 2 2006.285.15:30:25.10#ibcon#wrote, iclass 13, count 2 2006.285.15:30:25.10#ibcon#about to read 3, iclass 13, count 2 2006.285.15:30:25.12#ibcon#read 3, iclass 13, count 2 2006.285.15:30:25.12#ibcon#about to read 4, iclass 13, count 2 2006.285.15:30:25.12#ibcon#read 4, iclass 13, count 2 2006.285.15:30:25.12#ibcon#about to read 5, iclass 13, count 2 2006.285.15:30:25.12#ibcon#read 5, iclass 13, count 2 2006.285.15:30:25.12#ibcon#about to read 6, iclass 13, count 2 2006.285.15:30:25.12#ibcon#read 6, iclass 13, count 2 2006.285.15:30:25.12#ibcon#end of sib2, iclass 13, count 2 2006.285.15:30:25.12#ibcon#*mode == 0, iclass 13, count 2 2006.285.15:30:25.12#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.15:30:25.12#ibcon#[25=AT02-06\r\n] 2006.285.15:30:25.12#ibcon#*before write, iclass 13, count 2 2006.285.15:30:25.12#ibcon#enter sib2, iclass 13, count 2 2006.285.15:30:25.12#ibcon#flushed, iclass 13, count 2 2006.285.15:30:25.12#ibcon#about to write, iclass 13, count 2 2006.285.15:30:25.12#ibcon#wrote, iclass 13, count 2 2006.285.15:30:25.12#ibcon#about to read 3, iclass 13, count 2 2006.285.15:30:25.15#ibcon#read 3, iclass 13, count 2 2006.285.15:30:25.15#ibcon#about to read 4, iclass 13, count 2 2006.285.15:30:25.15#ibcon#read 4, iclass 13, count 2 2006.285.15:30:25.15#ibcon#about to read 5, iclass 13, count 2 2006.285.15:30:25.15#ibcon#read 5, iclass 13, count 2 2006.285.15:30:25.15#ibcon#about to read 6, iclass 13, count 2 2006.285.15:30:25.15#ibcon#read 6, iclass 13, count 2 2006.285.15:30:25.15#ibcon#end of sib2, iclass 13, count 2 2006.285.15:30:25.15#ibcon#*after write, iclass 13, count 2 2006.285.15:30:25.15#ibcon#*before return 0, iclass 13, count 2 2006.285.15:30:25.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:30:25.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:30:25.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.15:30:25.15#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:25.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:30:25.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:30:25.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:30:25.27#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:30:25.27#ibcon#first serial, iclass 13, count 0 2006.285.15:30:25.27#ibcon#enter sib2, iclass 13, count 0 2006.285.15:30:25.27#ibcon#flushed, iclass 13, count 0 2006.285.15:30:25.27#ibcon#about to write, iclass 13, count 0 2006.285.15:30:25.27#ibcon#wrote, iclass 13, count 0 2006.285.15:30:25.27#ibcon#about to read 3, iclass 13, count 0 2006.285.15:30:25.29#ibcon#read 3, iclass 13, count 0 2006.285.15:30:25.29#ibcon#about to read 4, iclass 13, count 0 2006.285.15:30:25.29#ibcon#read 4, iclass 13, count 0 2006.285.15:30:25.29#ibcon#about to read 5, iclass 13, count 0 2006.285.15:30:25.29#ibcon#read 5, iclass 13, count 0 2006.285.15:30:25.29#ibcon#about to read 6, iclass 13, count 0 2006.285.15:30:25.29#ibcon#read 6, iclass 13, count 0 2006.285.15:30:25.29#ibcon#end of sib2, iclass 13, count 0 2006.285.15:30:25.29#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:30:25.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:30:25.29#ibcon#[25=USB\r\n] 2006.285.15:30:25.29#ibcon#*before write, iclass 13, count 0 2006.285.15:30:25.29#ibcon#enter sib2, iclass 13, count 0 2006.285.15:30:25.29#ibcon#flushed, iclass 13, count 0 2006.285.15:30:25.29#ibcon#about to write, iclass 13, count 0 2006.285.15:30:25.29#ibcon#wrote, iclass 13, count 0 2006.285.15:30:25.29#ibcon#about to read 3, iclass 13, count 0 2006.285.15:30:25.32#ibcon#read 3, iclass 13, count 0 2006.285.15:30:25.32#ibcon#about to read 4, iclass 13, count 0 2006.285.15:30:25.32#ibcon#read 4, iclass 13, count 0 2006.285.15:30:25.32#ibcon#about to read 5, iclass 13, count 0 2006.285.15:30:25.32#ibcon#read 5, iclass 13, count 0 2006.285.15:30:25.32#ibcon#about to read 6, iclass 13, count 0 2006.285.15:30:25.32#ibcon#read 6, iclass 13, count 0 2006.285.15:30:25.32#ibcon#end of sib2, iclass 13, count 0 2006.285.15:30:25.32#ibcon#*after write, iclass 13, count 0 2006.285.15:30:25.32#ibcon#*before return 0, iclass 13, count 0 2006.285.15:30:25.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:30:25.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:30:25.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:30:25.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:30:25.32$vck44/valo=3,564.99 2006.285.15:30:25.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.15:30:25.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.15:30:25.32#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:25.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:30:25.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:30:25.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:30:25.32#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:30:25.32#ibcon#first serial, iclass 15, count 0 2006.285.15:30:25.32#ibcon#enter sib2, iclass 15, count 0 2006.285.15:30:25.32#ibcon#flushed, iclass 15, count 0 2006.285.15:30:25.32#ibcon#about to write, iclass 15, count 0 2006.285.15:30:25.32#ibcon#wrote, iclass 15, count 0 2006.285.15:30:25.32#ibcon#about to read 3, iclass 15, count 0 2006.285.15:30:25.34#ibcon#read 3, iclass 15, count 0 2006.285.15:30:25.34#ibcon#about to read 4, iclass 15, count 0 2006.285.15:30:25.34#ibcon#read 4, iclass 15, count 0 2006.285.15:30:25.34#ibcon#about to read 5, iclass 15, count 0 2006.285.15:30:25.34#ibcon#read 5, iclass 15, count 0 2006.285.15:30:25.34#ibcon#about to read 6, iclass 15, count 0 2006.285.15:30:25.34#ibcon#read 6, iclass 15, count 0 2006.285.15:30:25.34#ibcon#end of sib2, iclass 15, count 0 2006.285.15:30:25.34#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:30:25.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:30:25.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.15:30:25.34#ibcon#*before write, iclass 15, count 0 2006.285.15:30:25.34#ibcon#enter sib2, iclass 15, count 0 2006.285.15:30:25.34#ibcon#flushed, iclass 15, count 0 2006.285.15:30:25.34#ibcon#about to write, iclass 15, count 0 2006.285.15:30:25.34#ibcon#wrote, iclass 15, count 0 2006.285.15:30:25.34#ibcon#about to read 3, iclass 15, count 0 2006.285.15:30:25.38#ibcon#read 3, iclass 15, count 0 2006.285.15:30:25.38#ibcon#about to read 4, iclass 15, count 0 2006.285.15:30:25.38#ibcon#read 4, iclass 15, count 0 2006.285.15:30:25.38#ibcon#about to read 5, iclass 15, count 0 2006.285.15:30:25.38#ibcon#read 5, iclass 15, count 0 2006.285.15:30:25.38#ibcon#about to read 6, iclass 15, count 0 2006.285.15:30:25.38#ibcon#read 6, iclass 15, count 0 2006.285.15:30:25.38#ibcon#end of sib2, iclass 15, count 0 2006.285.15:30:25.38#ibcon#*after write, iclass 15, count 0 2006.285.15:30:25.38#ibcon#*before return 0, iclass 15, count 0 2006.285.15:30:25.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:30:25.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:30:25.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:30:25.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:30:25.38$vck44/va=3,7 2006.285.15:30:25.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.15:30:25.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.15:30:25.38#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:25.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:30:25.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:30:25.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:30:25.44#ibcon#enter wrdev, iclass 17, count 2 2006.285.15:30:25.44#ibcon#first serial, iclass 17, count 2 2006.285.15:30:25.44#ibcon#enter sib2, iclass 17, count 2 2006.285.15:30:25.44#ibcon#flushed, iclass 17, count 2 2006.285.15:30:25.44#ibcon#about to write, iclass 17, count 2 2006.285.15:30:25.44#ibcon#wrote, iclass 17, count 2 2006.285.15:30:25.44#ibcon#about to read 3, iclass 17, count 2 2006.285.15:30:25.46#ibcon#read 3, iclass 17, count 2 2006.285.15:30:25.46#ibcon#about to read 4, iclass 17, count 2 2006.285.15:30:25.46#ibcon#read 4, iclass 17, count 2 2006.285.15:30:25.46#ibcon#about to read 5, iclass 17, count 2 2006.285.15:30:25.46#ibcon#read 5, iclass 17, count 2 2006.285.15:30:25.46#ibcon#about to read 6, iclass 17, count 2 2006.285.15:30:25.46#ibcon#read 6, iclass 17, count 2 2006.285.15:30:25.46#ibcon#end of sib2, iclass 17, count 2 2006.285.15:30:25.46#ibcon#*mode == 0, iclass 17, count 2 2006.285.15:30:25.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.15:30:25.46#ibcon#[25=AT03-07\r\n] 2006.285.15:30:25.46#ibcon#*before write, iclass 17, count 2 2006.285.15:30:25.46#ibcon#enter sib2, iclass 17, count 2 2006.285.15:30:25.46#ibcon#flushed, iclass 17, count 2 2006.285.15:30:25.46#ibcon#about to write, iclass 17, count 2 2006.285.15:30:25.46#ibcon#wrote, iclass 17, count 2 2006.285.15:30:25.46#ibcon#about to read 3, iclass 17, count 2 2006.285.15:30:25.49#ibcon#read 3, iclass 17, count 2 2006.285.15:30:25.49#ibcon#about to read 4, iclass 17, count 2 2006.285.15:30:25.49#ibcon#read 4, iclass 17, count 2 2006.285.15:30:25.49#ibcon#about to read 5, iclass 17, count 2 2006.285.15:30:25.49#ibcon#read 5, iclass 17, count 2 2006.285.15:30:25.49#ibcon#about to read 6, iclass 17, count 2 2006.285.15:30:25.49#ibcon#read 6, iclass 17, count 2 2006.285.15:30:25.49#ibcon#end of sib2, iclass 17, count 2 2006.285.15:30:25.49#ibcon#*after write, iclass 17, count 2 2006.285.15:30:25.49#ibcon#*before return 0, iclass 17, count 2 2006.285.15:30:25.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:30:25.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:30:25.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.15:30:25.49#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:25.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:30:25.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:30:25.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:30:25.61#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:30:25.61#ibcon#first serial, iclass 17, count 0 2006.285.15:30:25.61#ibcon#enter sib2, iclass 17, count 0 2006.285.15:30:25.61#ibcon#flushed, iclass 17, count 0 2006.285.15:30:25.61#ibcon#about to write, iclass 17, count 0 2006.285.15:30:25.61#ibcon#wrote, iclass 17, count 0 2006.285.15:30:25.61#ibcon#about to read 3, iclass 17, count 0 2006.285.15:30:25.63#ibcon#read 3, iclass 17, count 0 2006.285.15:30:25.63#ibcon#about to read 4, iclass 17, count 0 2006.285.15:30:25.63#ibcon#read 4, iclass 17, count 0 2006.285.15:30:25.63#ibcon#about to read 5, iclass 17, count 0 2006.285.15:30:25.63#ibcon#read 5, iclass 17, count 0 2006.285.15:30:25.63#ibcon#about to read 6, iclass 17, count 0 2006.285.15:30:25.63#ibcon#read 6, iclass 17, count 0 2006.285.15:30:25.63#ibcon#end of sib2, iclass 17, count 0 2006.285.15:30:25.63#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:30:25.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:30:25.63#ibcon#[25=USB\r\n] 2006.285.15:30:25.63#ibcon#*before write, iclass 17, count 0 2006.285.15:30:25.63#ibcon#enter sib2, iclass 17, count 0 2006.285.15:30:25.63#ibcon#flushed, iclass 17, count 0 2006.285.15:30:25.63#ibcon#about to write, iclass 17, count 0 2006.285.15:30:25.63#ibcon#wrote, iclass 17, count 0 2006.285.15:30:25.63#ibcon#about to read 3, iclass 17, count 0 2006.285.15:30:25.66#ibcon#read 3, iclass 17, count 0 2006.285.15:30:25.66#ibcon#about to read 4, iclass 17, count 0 2006.285.15:30:25.66#ibcon#read 4, iclass 17, count 0 2006.285.15:30:25.66#ibcon#about to read 5, iclass 17, count 0 2006.285.15:30:25.66#ibcon#read 5, iclass 17, count 0 2006.285.15:30:25.66#ibcon#about to read 6, iclass 17, count 0 2006.285.15:30:25.66#ibcon#read 6, iclass 17, count 0 2006.285.15:30:25.66#ibcon#end of sib2, iclass 17, count 0 2006.285.15:30:25.66#ibcon#*after write, iclass 17, count 0 2006.285.15:30:25.66#ibcon#*before return 0, iclass 17, count 0 2006.285.15:30:25.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:30:25.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:30:25.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:30:25.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:30:25.66$vck44/valo=4,624.99 2006.285.15:30:25.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.15:30:25.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.15:30:25.66#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:25.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:30:25.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:30:25.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:30:25.66#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:30:25.66#ibcon#first serial, iclass 19, count 0 2006.285.15:30:25.66#ibcon#enter sib2, iclass 19, count 0 2006.285.15:30:25.66#ibcon#flushed, iclass 19, count 0 2006.285.15:30:25.66#ibcon#about to write, iclass 19, count 0 2006.285.15:30:25.66#ibcon#wrote, iclass 19, count 0 2006.285.15:30:25.66#ibcon#about to read 3, iclass 19, count 0 2006.285.15:30:26.19#ibcon#read 3, iclass 19, count 0 2006.285.15:30:26.19#ibcon#about to read 4, iclass 19, count 0 2006.285.15:30:26.19#ibcon#read 4, iclass 19, count 0 2006.285.15:30:26.19#ibcon#about to read 5, iclass 19, count 0 2006.285.15:30:26.19#ibcon#read 5, iclass 19, count 0 2006.285.15:30:26.19#ibcon#about to read 6, iclass 19, count 0 2006.285.15:30:26.19#ibcon#read 6, iclass 19, count 0 2006.285.15:30:26.19#ibcon#end of sib2, iclass 19, count 0 2006.285.15:30:26.19#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:30:26.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:30:26.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.15:30:26.19#ibcon#*before write, iclass 19, count 0 2006.285.15:30:26.19#ibcon#enter sib2, iclass 19, count 0 2006.285.15:30:26.19#ibcon#flushed, iclass 19, count 0 2006.285.15:30:26.19#ibcon#about to write, iclass 19, count 0 2006.285.15:30:26.19#ibcon#wrote, iclass 19, count 0 2006.285.15:30:26.19#ibcon#about to read 3, iclass 19, count 0 2006.285.15:30:26.23#ibcon#read 3, iclass 19, count 0 2006.285.15:30:26.23#ibcon#about to read 4, iclass 19, count 0 2006.285.15:30:26.23#ibcon#read 4, iclass 19, count 0 2006.285.15:30:26.23#ibcon#about to read 5, iclass 19, count 0 2006.285.15:30:26.23#ibcon#read 5, iclass 19, count 0 2006.285.15:30:26.23#ibcon#about to read 6, iclass 19, count 0 2006.285.15:30:26.23#ibcon#read 6, iclass 19, count 0 2006.285.15:30:26.23#ibcon#end of sib2, iclass 19, count 0 2006.285.15:30:26.23#ibcon#*after write, iclass 19, count 0 2006.285.15:30:26.23#ibcon#*before return 0, iclass 19, count 0 2006.285.15:30:26.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:30:26.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:30:26.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:30:26.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:30:26.23$vck44/va=4,6 2006.285.15:30:26.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.15:30:26.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.15:30:26.23#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:26.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:30:26.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:30:26.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:30:26.23#ibcon#enter wrdev, iclass 21, count 2 2006.285.15:30:26.23#ibcon#first serial, iclass 21, count 2 2006.285.15:30:26.23#ibcon#enter sib2, iclass 21, count 2 2006.285.15:30:26.23#ibcon#flushed, iclass 21, count 2 2006.285.15:30:26.23#ibcon#about to write, iclass 21, count 2 2006.285.15:30:26.23#ibcon#wrote, iclass 21, count 2 2006.285.15:30:26.23#ibcon#about to read 3, iclass 21, count 2 2006.285.15:30:26.25#ibcon#read 3, iclass 21, count 2 2006.285.15:30:26.25#ibcon#about to read 4, iclass 21, count 2 2006.285.15:30:26.25#ibcon#read 4, iclass 21, count 2 2006.285.15:30:26.25#ibcon#about to read 5, iclass 21, count 2 2006.285.15:30:26.25#ibcon#read 5, iclass 21, count 2 2006.285.15:30:26.25#ibcon#about to read 6, iclass 21, count 2 2006.285.15:30:26.25#ibcon#read 6, iclass 21, count 2 2006.285.15:30:26.25#ibcon#end of sib2, iclass 21, count 2 2006.285.15:30:26.25#ibcon#*mode == 0, iclass 21, count 2 2006.285.15:30:26.25#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.15:30:26.25#ibcon#[25=AT04-06\r\n] 2006.285.15:30:26.25#ibcon#*before write, iclass 21, count 2 2006.285.15:30:26.25#ibcon#enter sib2, iclass 21, count 2 2006.285.15:30:26.25#ibcon#flushed, iclass 21, count 2 2006.285.15:30:26.25#ibcon#about to write, iclass 21, count 2 2006.285.15:30:26.25#ibcon#wrote, iclass 21, count 2 2006.285.15:30:26.25#ibcon#about to read 3, iclass 21, count 2 2006.285.15:30:26.28#ibcon#read 3, iclass 21, count 2 2006.285.15:30:26.28#ibcon#about to read 4, iclass 21, count 2 2006.285.15:30:26.28#ibcon#read 4, iclass 21, count 2 2006.285.15:30:26.28#ibcon#about to read 5, iclass 21, count 2 2006.285.15:30:26.28#ibcon#read 5, iclass 21, count 2 2006.285.15:30:26.28#ibcon#about to read 6, iclass 21, count 2 2006.285.15:30:26.28#ibcon#read 6, iclass 21, count 2 2006.285.15:30:26.28#ibcon#end of sib2, iclass 21, count 2 2006.285.15:30:26.28#ibcon#*after write, iclass 21, count 2 2006.285.15:30:26.28#ibcon#*before return 0, iclass 21, count 2 2006.285.15:30:26.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:30:26.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:30:26.28#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.15:30:26.28#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:26.28#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:30:26.40#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:30:26.40#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:30:26.40#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:30:26.40#ibcon#first serial, iclass 21, count 0 2006.285.15:30:26.40#ibcon#enter sib2, iclass 21, count 0 2006.285.15:30:26.40#ibcon#flushed, iclass 21, count 0 2006.285.15:30:26.40#ibcon#about to write, iclass 21, count 0 2006.285.15:30:26.40#ibcon#wrote, iclass 21, count 0 2006.285.15:30:26.40#ibcon#about to read 3, iclass 21, count 0 2006.285.15:30:26.42#ibcon#read 3, iclass 21, count 0 2006.285.15:30:26.42#ibcon#about to read 4, iclass 21, count 0 2006.285.15:30:26.42#ibcon#read 4, iclass 21, count 0 2006.285.15:30:26.42#ibcon#about to read 5, iclass 21, count 0 2006.285.15:30:26.42#ibcon#read 5, iclass 21, count 0 2006.285.15:30:26.42#ibcon#about to read 6, iclass 21, count 0 2006.285.15:30:26.42#ibcon#read 6, iclass 21, count 0 2006.285.15:30:26.42#ibcon#end of sib2, iclass 21, count 0 2006.285.15:30:26.42#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:30:26.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:30:26.42#ibcon#[25=USB\r\n] 2006.285.15:30:26.42#ibcon#*before write, iclass 21, count 0 2006.285.15:30:26.42#ibcon#enter sib2, iclass 21, count 0 2006.285.15:30:26.42#ibcon#flushed, iclass 21, count 0 2006.285.15:30:26.42#ibcon#about to write, iclass 21, count 0 2006.285.15:30:26.42#ibcon#wrote, iclass 21, count 0 2006.285.15:30:26.42#ibcon#about to read 3, iclass 21, count 0 2006.285.15:30:26.45#ibcon#read 3, iclass 21, count 0 2006.285.15:30:26.45#ibcon#about to read 4, iclass 21, count 0 2006.285.15:30:26.45#ibcon#read 4, iclass 21, count 0 2006.285.15:30:26.45#ibcon#about to read 5, iclass 21, count 0 2006.285.15:30:26.45#ibcon#read 5, iclass 21, count 0 2006.285.15:30:26.45#ibcon#about to read 6, iclass 21, count 0 2006.285.15:30:26.45#ibcon#read 6, iclass 21, count 0 2006.285.15:30:26.45#ibcon#end of sib2, iclass 21, count 0 2006.285.15:30:26.45#ibcon#*after write, iclass 21, count 0 2006.285.15:30:26.45#ibcon#*before return 0, iclass 21, count 0 2006.285.15:30:26.45#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:30:26.45#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:30:26.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:30:26.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:30:26.45$vck44/valo=5,734.99 2006.285.15:30:26.45#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.15:30:26.45#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.15:30:26.45#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:26.45#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:30:26.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:30:26.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:30:26.45#ibcon#enter wrdev, iclass 23, count 0 2006.285.15:30:26.45#ibcon#first serial, iclass 23, count 0 2006.285.15:30:26.45#ibcon#enter sib2, iclass 23, count 0 2006.285.15:30:26.45#ibcon#flushed, iclass 23, count 0 2006.285.15:30:26.45#ibcon#about to write, iclass 23, count 0 2006.285.15:30:26.45#ibcon#wrote, iclass 23, count 0 2006.285.15:30:26.45#ibcon#about to read 3, iclass 23, count 0 2006.285.15:30:26.97#ibcon#read 3, iclass 23, count 0 2006.285.15:30:26.97#ibcon#about to read 4, iclass 23, count 0 2006.285.15:30:26.97#ibcon#read 4, iclass 23, count 0 2006.285.15:30:26.97#ibcon#about to read 5, iclass 23, count 0 2006.285.15:30:26.97#ibcon#read 5, iclass 23, count 0 2006.285.15:30:26.97#ibcon#about to read 6, iclass 23, count 0 2006.285.15:30:26.97#ibcon#read 6, iclass 23, count 0 2006.285.15:30:26.97#ibcon#end of sib2, iclass 23, count 0 2006.285.15:30:26.97#ibcon#*mode == 0, iclass 23, count 0 2006.285.15:30:26.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.15:30:26.97#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.15:30:26.97#ibcon#*before write, iclass 23, count 0 2006.285.15:30:26.97#ibcon#enter sib2, iclass 23, count 0 2006.285.15:30:26.97#ibcon#flushed, iclass 23, count 0 2006.285.15:30:26.97#ibcon#about to write, iclass 23, count 0 2006.285.15:30:26.97#ibcon#wrote, iclass 23, count 0 2006.285.15:30:26.97#ibcon#about to read 3, iclass 23, count 0 2006.285.15:30:27.01#ibcon#read 3, iclass 23, count 0 2006.285.15:30:27.01#ibcon#about to read 4, iclass 23, count 0 2006.285.15:30:27.01#ibcon#read 4, iclass 23, count 0 2006.285.15:30:27.01#ibcon#about to read 5, iclass 23, count 0 2006.285.15:30:27.01#ibcon#read 5, iclass 23, count 0 2006.285.15:30:27.01#ibcon#about to read 6, iclass 23, count 0 2006.285.15:30:27.01#ibcon#read 6, iclass 23, count 0 2006.285.15:30:27.01#ibcon#end of sib2, iclass 23, count 0 2006.285.15:30:27.01#ibcon#*after write, iclass 23, count 0 2006.285.15:30:27.01#ibcon#*before return 0, iclass 23, count 0 2006.285.15:30:27.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:30:27.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:30:27.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.15:30:27.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.15:30:27.01$vck44/va=5,3 2006.285.15:30:27.01#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.15:30:27.01#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.15:30:27.01#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:27.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:30:27.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:30:27.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:30:27.01#ibcon#enter wrdev, iclass 25, count 2 2006.285.15:30:27.01#ibcon#first serial, iclass 25, count 2 2006.285.15:30:27.01#ibcon#enter sib2, iclass 25, count 2 2006.285.15:30:27.01#ibcon#flushed, iclass 25, count 2 2006.285.15:30:27.01#ibcon#about to write, iclass 25, count 2 2006.285.15:30:27.01#ibcon#wrote, iclass 25, count 2 2006.285.15:30:27.01#ibcon#about to read 3, iclass 25, count 2 2006.285.15:30:27.03#ibcon#read 3, iclass 25, count 2 2006.285.15:30:27.03#ibcon#about to read 4, iclass 25, count 2 2006.285.15:30:27.03#ibcon#read 4, iclass 25, count 2 2006.285.15:30:27.03#ibcon#about to read 5, iclass 25, count 2 2006.285.15:30:27.03#ibcon#read 5, iclass 25, count 2 2006.285.15:30:27.03#ibcon#about to read 6, iclass 25, count 2 2006.285.15:30:27.03#ibcon#read 6, iclass 25, count 2 2006.285.15:30:27.03#ibcon#end of sib2, iclass 25, count 2 2006.285.15:30:27.03#ibcon#*mode == 0, iclass 25, count 2 2006.285.15:30:27.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.15:30:27.03#ibcon#[25=AT05-03\r\n] 2006.285.15:30:27.03#ibcon#*before write, iclass 25, count 2 2006.285.15:30:27.03#ibcon#enter sib2, iclass 25, count 2 2006.285.15:30:27.03#ibcon#flushed, iclass 25, count 2 2006.285.15:30:27.03#ibcon#about to write, iclass 25, count 2 2006.285.15:30:27.03#ibcon#wrote, iclass 25, count 2 2006.285.15:30:27.03#ibcon#about to read 3, iclass 25, count 2 2006.285.15:30:27.06#ibcon#read 3, iclass 25, count 2 2006.285.15:30:27.06#ibcon#about to read 4, iclass 25, count 2 2006.285.15:30:27.06#ibcon#read 4, iclass 25, count 2 2006.285.15:30:27.06#ibcon#about to read 5, iclass 25, count 2 2006.285.15:30:27.06#ibcon#read 5, iclass 25, count 2 2006.285.15:30:27.06#ibcon#about to read 6, iclass 25, count 2 2006.285.15:30:27.06#ibcon#read 6, iclass 25, count 2 2006.285.15:30:27.06#ibcon#end of sib2, iclass 25, count 2 2006.285.15:30:27.06#ibcon#*after write, iclass 25, count 2 2006.285.15:30:27.06#ibcon#*before return 0, iclass 25, count 2 2006.285.15:30:27.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:30:27.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:30:27.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.15:30:27.06#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:27.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:30:27.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:30:27.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:30:27.18#ibcon#enter wrdev, iclass 25, count 0 2006.285.15:30:27.18#ibcon#first serial, iclass 25, count 0 2006.285.15:30:27.18#ibcon#enter sib2, iclass 25, count 0 2006.285.15:30:27.18#ibcon#flushed, iclass 25, count 0 2006.285.15:30:27.18#ibcon#about to write, iclass 25, count 0 2006.285.15:30:27.18#ibcon#wrote, iclass 25, count 0 2006.285.15:30:27.18#ibcon#about to read 3, iclass 25, count 0 2006.285.15:30:27.20#ibcon#read 3, iclass 25, count 0 2006.285.15:30:27.20#ibcon#about to read 4, iclass 25, count 0 2006.285.15:30:27.20#ibcon#read 4, iclass 25, count 0 2006.285.15:30:27.20#ibcon#about to read 5, iclass 25, count 0 2006.285.15:30:27.20#ibcon#read 5, iclass 25, count 0 2006.285.15:30:27.20#ibcon#about to read 6, iclass 25, count 0 2006.285.15:30:27.20#ibcon#read 6, iclass 25, count 0 2006.285.15:30:27.20#ibcon#end of sib2, iclass 25, count 0 2006.285.15:30:27.20#ibcon#*mode == 0, iclass 25, count 0 2006.285.15:30:27.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.15:30:27.20#ibcon#[25=USB\r\n] 2006.285.15:30:27.20#ibcon#*before write, iclass 25, count 0 2006.285.15:30:27.20#ibcon#enter sib2, iclass 25, count 0 2006.285.15:30:27.20#ibcon#flushed, iclass 25, count 0 2006.285.15:30:27.20#ibcon#about to write, iclass 25, count 0 2006.285.15:30:27.20#ibcon#wrote, iclass 25, count 0 2006.285.15:30:27.20#ibcon#about to read 3, iclass 25, count 0 2006.285.15:30:27.23#ibcon#read 3, iclass 25, count 0 2006.285.15:30:27.23#ibcon#about to read 4, iclass 25, count 0 2006.285.15:30:27.23#ibcon#read 4, iclass 25, count 0 2006.285.15:30:27.23#ibcon#about to read 5, iclass 25, count 0 2006.285.15:30:27.23#ibcon#read 5, iclass 25, count 0 2006.285.15:30:27.23#ibcon#about to read 6, iclass 25, count 0 2006.285.15:30:27.23#ibcon#read 6, iclass 25, count 0 2006.285.15:30:27.23#ibcon#end of sib2, iclass 25, count 0 2006.285.15:30:27.23#ibcon#*after write, iclass 25, count 0 2006.285.15:30:27.23#ibcon#*before return 0, iclass 25, count 0 2006.285.15:30:27.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:30:27.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:30:27.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.15:30:27.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.15:30:27.23$vck44/valo=6,814.99 2006.285.15:30:27.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.15:30:27.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.15:30:27.23#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:27.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:30:27.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:30:27.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:30:27.23#ibcon#enter wrdev, iclass 27, count 0 2006.285.15:30:27.23#ibcon#first serial, iclass 27, count 0 2006.285.15:30:27.23#ibcon#enter sib2, iclass 27, count 0 2006.285.15:30:27.23#ibcon#flushed, iclass 27, count 0 2006.285.15:30:27.23#ibcon#about to write, iclass 27, count 0 2006.285.15:30:27.23#ibcon#wrote, iclass 27, count 0 2006.285.15:30:27.23#ibcon#about to read 3, iclass 27, count 0 2006.285.15:30:27.25#ibcon#read 3, iclass 27, count 0 2006.285.15:30:27.25#ibcon#about to read 4, iclass 27, count 0 2006.285.15:30:27.25#ibcon#read 4, iclass 27, count 0 2006.285.15:30:27.25#ibcon#about to read 5, iclass 27, count 0 2006.285.15:30:27.25#ibcon#read 5, iclass 27, count 0 2006.285.15:30:27.25#ibcon#about to read 6, iclass 27, count 0 2006.285.15:30:27.25#ibcon#read 6, iclass 27, count 0 2006.285.15:30:27.25#ibcon#end of sib2, iclass 27, count 0 2006.285.15:30:27.25#ibcon#*mode == 0, iclass 27, count 0 2006.285.15:30:27.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.15:30:27.25#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.15:30:27.25#ibcon#*before write, iclass 27, count 0 2006.285.15:30:27.25#ibcon#enter sib2, iclass 27, count 0 2006.285.15:30:27.25#ibcon#flushed, iclass 27, count 0 2006.285.15:30:27.25#ibcon#about to write, iclass 27, count 0 2006.285.15:30:27.25#ibcon#wrote, iclass 27, count 0 2006.285.15:30:27.25#ibcon#about to read 3, iclass 27, count 0 2006.285.15:30:27.29#ibcon#read 3, iclass 27, count 0 2006.285.15:30:27.29#ibcon#about to read 4, iclass 27, count 0 2006.285.15:30:27.29#ibcon#read 4, iclass 27, count 0 2006.285.15:30:27.29#ibcon#about to read 5, iclass 27, count 0 2006.285.15:30:27.29#ibcon#read 5, iclass 27, count 0 2006.285.15:30:27.29#ibcon#about to read 6, iclass 27, count 0 2006.285.15:30:27.29#ibcon#read 6, iclass 27, count 0 2006.285.15:30:27.29#ibcon#end of sib2, iclass 27, count 0 2006.285.15:30:27.29#ibcon#*after write, iclass 27, count 0 2006.285.15:30:27.29#ibcon#*before return 0, iclass 27, count 0 2006.285.15:30:27.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:30:27.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:30:27.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.15:30:27.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.15:30:27.29$vck44/va=6,4 2006.285.15:30:27.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.15:30:27.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.15:30:27.29#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:27.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:30:27.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:30:27.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:30:27.35#ibcon#enter wrdev, iclass 29, count 2 2006.285.15:30:27.35#ibcon#first serial, iclass 29, count 2 2006.285.15:30:27.35#ibcon#enter sib2, iclass 29, count 2 2006.285.15:30:27.35#ibcon#flushed, iclass 29, count 2 2006.285.15:30:27.35#ibcon#about to write, iclass 29, count 2 2006.285.15:30:27.35#ibcon#wrote, iclass 29, count 2 2006.285.15:30:27.35#ibcon#about to read 3, iclass 29, count 2 2006.285.15:30:27.37#ibcon#read 3, iclass 29, count 2 2006.285.15:30:27.37#ibcon#about to read 4, iclass 29, count 2 2006.285.15:30:27.37#ibcon#read 4, iclass 29, count 2 2006.285.15:30:27.37#ibcon#about to read 5, iclass 29, count 2 2006.285.15:30:27.37#ibcon#read 5, iclass 29, count 2 2006.285.15:30:27.37#ibcon#about to read 6, iclass 29, count 2 2006.285.15:30:27.37#ibcon#read 6, iclass 29, count 2 2006.285.15:30:27.37#ibcon#end of sib2, iclass 29, count 2 2006.285.15:30:27.37#ibcon#*mode == 0, iclass 29, count 2 2006.285.15:30:27.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.15:30:27.37#ibcon#[25=AT06-04\r\n] 2006.285.15:30:27.37#ibcon#*before write, iclass 29, count 2 2006.285.15:30:27.37#ibcon#enter sib2, iclass 29, count 2 2006.285.15:30:27.37#ibcon#flushed, iclass 29, count 2 2006.285.15:30:27.37#ibcon#about to write, iclass 29, count 2 2006.285.15:30:27.37#ibcon#wrote, iclass 29, count 2 2006.285.15:30:27.37#ibcon#about to read 3, iclass 29, count 2 2006.285.15:30:27.40#ibcon#read 3, iclass 29, count 2 2006.285.15:30:27.40#ibcon#about to read 4, iclass 29, count 2 2006.285.15:30:27.40#ibcon#read 4, iclass 29, count 2 2006.285.15:30:27.40#ibcon#about to read 5, iclass 29, count 2 2006.285.15:30:27.40#ibcon#read 5, iclass 29, count 2 2006.285.15:30:27.40#ibcon#about to read 6, iclass 29, count 2 2006.285.15:30:27.40#ibcon#read 6, iclass 29, count 2 2006.285.15:30:27.40#ibcon#end of sib2, iclass 29, count 2 2006.285.15:30:27.40#ibcon#*after write, iclass 29, count 2 2006.285.15:30:27.40#ibcon#*before return 0, iclass 29, count 2 2006.285.15:30:27.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:30:27.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:30:27.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.15:30:27.40#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:27.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:30:27.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:30:27.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:30:27.52#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:30:27.52#ibcon#first serial, iclass 29, count 0 2006.285.15:30:27.52#ibcon#enter sib2, iclass 29, count 0 2006.285.15:30:27.52#ibcon#flushed, iclass 29, count 0 2006.285.15:30:27.52#ibcon#about to write, iclass 29, count 0 2006.285.15:30:27.52#ibcon#wrote, iclass 29, count 0 2006.285.15:30:27.52#ibcon#about to read 3, iclass 29, count 0 2006.285.15:30:27.54#ibcon#read 3, iclass 29, count 0 2006.285.15:30:27.54#ibcon#about to read 4, iclass 29, count 0 2006.285.15:30:27.54#ibcon#read 4, iclass 29, count 0 2006.285.15:30:27.54#ibcon#about to read 5, iclass 29, count 0 2006.285.15:30:27.54#ibcon#read 5, iclass 29, count 0 2006.285.15:30:27.54#ibcon#about to read 6, iclass 29, count 0 2006.285.15:30:27.54#ibcon#read 6, iclass 29, count 0 2006.285.15:30:27.54#ibcon#end of sib2, iclass 29, count 0 2006.285.15:30:27.54#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:30:27.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:30:27.54#ibcon#[25=USB\r\n] 2006.285.15:30:27.54#ibcon#*before write, iclass 29, count 0 2006.285.15:30:27.54#ibcon#enter sib2, iclass 29, count 0 2006.285.15:30:27.54#ibcon#flushed, iclass 29, count 0 2006.285.15:30:27.54#ibcon#about to write, iclass 29, count 0 2006.285.15:30:27.54#ibcon#wrote, iclass 29, count 0 2006.285.15:30:27.54#ibcon#about to read 3, iclass 29, count 0 2006.285.15:30:27.57#ibcon#read 3, iclass 29, count 0 2006.285.15:30:27.57#ibcon#about to read 4, iclass 29, count 0 2006.285.15:30:27.57#ibcon#read 4, iclass 29, count 0 2006.285.15:30:27.57#ibcon#about to read 5, iclass 29, count 0 2006.285.15:30:27.57#ibcon#read 5, iclass 29, count 0 2006.285.15:30:27.57#ibcon#about to read 6, iclass 29, count 0 2006.285.15:30:27.57#ibcon#read 6, iclass 29, count 0 2006.285.15:30:27.57#ibcon#end of sib2, iclass 29, count 0 2006.285.15:30:27.57#ibcon#*after write, iclass 29, count 0 2006.285.15:30:27.57#ibcon#*before return 0, iclass 29, count 0 2006.285.15:30:27.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:30:27.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:30:27.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:30:27.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:30:27.57$vck44/valo=7,864.99 2006.285.15:30:27.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.15:30:27.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.15:30:27.57#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:27.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:30:27.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:30:27.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:30:27.57#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:30:27.57#ibcon#first serial, iclass 31, count 0 2006.285.15:30:27.57#ibcon#enter sib2, iclass 31, count 0 2006.285.15:30:27.57#ibcon#flushed, iclass 31, count 0 2006.285.15:30:27.57#ibcon#about to write, iclass 31, count 0 2006.285.15:30:27.57#ibcon#wrote, iclass 31, count 0 2006.285.15:30:27.57#ibcon#about to read 3, iclass 31, count 0 2006.285.15:30:27.59#ibcon#read 3, iclass 31, count 0 2006.285.15:30:27.59#ibcon#about to read 4, iclass 31, count 0 2006.285.15:30:27.59#ibcon#read 4, iclass 31, count 0 2006.285.15:30:27.59#ibcon#about to read 5, iclass 31, count 0 2006.285.15:30:27.59#ibcon#read 5, iclass 31, count 0 2006.285.15:30:27.59#ibcon#about to read 6, iclass 31, count 0 2006.285.15:30:27.59#ibcon#read 6, iclass 31, count 0 2006.285.15:30:27.59#ibcon#end of sib2, iclass 31, count 0 2006.285.15:30:27.59#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:30:27.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:30:27.59#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.15:30:27.59#ibcon#*before write, iclass 31, count 0 2006.285.15:30:27.59#ibcon#enter sib2, iclass 31, count 0 2006.285.15:30:27.59#ibcon#flushed, iclass 31, count 0 2006.285.15:30:27.59#ibcon#about to write, iclass 31, count 0 2006.285.15:30:27.59#ibcon#wrote, iclass 31, count 0 2006.285.15:30:27.59#ibcon#about to read 3, iclass 31, count 0 2006.285.15:30:27.63#ibcon#read 3, iclass 31, count 0 2006.285.15:30:27.63#ibcon#about to read 4, iclass 31, count 0 2006.285.15:30:27.63#ibcon#read 4, iclass 31, count 0 2006.285.15:30:27.63#ibcon#about to read 5, iclass 31, count 0 2006.285.15:30:27.63#ibcon#read 5, iclass 31, count 0 2006.285.15:30:27.63#ibcon#about to read 6, iclass 31, count 0 2006.285.15:30:27.63#ibcon#read 6, iclass 31, count 0 2006.285.15:30:27.63#ibcon#end of sib2, iclass 31, count 0 2006.285.15:30:27.63#ibcon#*after write, iclass 31, count 0 2006.285.15:30:27.63#ibcon#*before return 0, iclass 31, count 0 2006.285.15:30:27.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:30:27.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:30:27.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:30:27.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:30:27.63$vck44/va=7,4 2006.285.15:30:27.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.15:30:27.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.15:30:27.63#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:27.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:30:27.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:30:27.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:30:27.69#ibcon#enter wrdev, iclass 33, count 2 2006.285.15:30:27.69#ibcon#first serial, iclass 33, count 2 2006.285.15:30:27.69#ibcon#enter sib2, iclass 33, count 2 2006.285.15:30:27.69#ibcon#flushed, iclass 33, count 2 2006.285.15:30:27.69#ibcon#about to write, iclass 33, count 2 2006.285.15:30:27.69#ibcon#wrote, iclass 33, count 2 2006.285.15:30:27.69#ibcon#about to read 3, iclass 33, count 2 2006.285.15:30:27.71#ibcon#read 3, iclass 33, count 2 2006.285.15:30:28.05#ibcon#about to read 4, iclass 33, count 2 2006.285.15:30:28.05#ibcon#read 4, iclass 33, count 2 2006.285.15:30:28.05#ibcon#about to read 5, iclass 33, count 2 2006.285.15:30:28.05#ibcon#read 5, iclass 33, count 2 2006.285.15:30:28.05#ibcon#about to read 6, iclass 33, count 2 2006.285.15:30:28.05#ibcon#read 6, iclass 33, count 2 2006.285.15:30:28.05#ibcon#end of sib2, iclass 33, count 2 2006.285.15:30:28.05#ibcon#*mode == 0, iclass 33, count 2 2006.285.15:30:28.05#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.15:30:28.05#ibcon#[25=AT07-04\r\n] 2006.285.15:30:28.05#ibcon#*before write, iclass 33, count 2 2006.285.15:30:28.05#ibcon#enter sib2, iclass 33, count 2 2006.285.15:30:28.05#ibcon#flushed, iclass 33, count 2 2006.285.15:30:28.05#ibcon#about to write, iclass 33, count 2 2006.285.15:30:28.05#ibcon#wrote, iclass 33, count 2 2006.285.15:30:28.05#ibcon#about to read 3, iclass 33, count 2 2006.285.15:30:28.08#ibcon#read 3, iclass 33, count 2 2006.285.15:30:28.08#ibcon#about to read 4, iclass 33, count 2 2006.285.15:30:28.08#ibcon#read 4, iclass 33, count 2 2006.285.15:30:28.08#ibcon#about to read 5, iclass 33, count 2 2006.285.15:30:28.08#ibcon#read 5, iclass 33, count 2 2006.285.15:30:28.08#ibcon#about to read 6, iclass 33, count 2 2006.285.15:30:28.08#ibcon#read 6, iclass 33, count 2 2006.285.15:30:28.08#ibcon#end of sib2, iclass 33, count 2 2006.285.15:30:28.08#ibcon#*after write, iclass 33, count 2 2006.285.15:30:28.08#ibcon#*before return 0, iclass 33, count 2 2006.285.15:30:28.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:30:28.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:30:28.08#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.15:30:28.08#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:28.08#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:30:28.20#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:30:28.20#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:30:28.20#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:30:28.20#ibcon#first serial, iclass 33, count 0 2006.285.15:30:28.20#ibcon#enter sib2, iclass 33, count 0 2006.285.15:30:28.20#ibcon#flushed, iclass 33, count 0 2006.285.15:30:28.20#ibcon#about to write, iclass 33, count 0 2006.285.15:30:28.20#ibcon#wrote, iclass 33, count 0 2006.285.15:30:28.20#ibcon#about to read 3, iclass 33, count 0 2006.285.15:30:28.22#ibcon#read 3, iclass 33, count 0 2006.285.15:30:28.22#ibcon#about to read 4, iclass 33, count 0 2006.285.15:30:28.22#ibcon#read 4, iclass 33, count 0 2006.285.15:30:28.22#ibcon#about to read 5, iclass 33, count 0 2006.285.15:30:28.22#ibcon#read 5, iclass 33, count 0 2006.285.15:30:28.22#ibcon#about to read 6, iclass 33, count 0 2006.285.15:30:28.22#ibcon#read 6, iclass 33, count 0 2006.285.15:30:28.22#ibcon#end of sib2, iclass 33, count 0 2006.285.15:30:28.22#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:30:28.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:30:28.22#ibcon#[25=USB\r\n] 2006.285.15:30:28.22#ibcon#*before write, iclass 33, count 0 2006.285.15:30:28.22#ibcon#enter sib2, iclass 33, count 0 2006.285.15:30:28.22#ibcon#flushed, iclass 33, count 0 2006.285.15:30:28.22#ibcon#about to write, iclass 33, count 0 2006.285.15:30:28.22#ibcon#wrote, iclass 33, count 0 2006.285.15:30:28.22#ibcon#about to read 3, iclass 33, count 0 2006.285.15:30:28.25#ibcon#read 3, iclass 33, count 0 2006.285.15:30:28.25#ibcon#about to read 4, iclass 33, count 0 2006.285.15:30:28.25#ibcon#read 4, iclass 33, count 0 2006.285.15:30:28.25#ibcon#about to read 5, iclass 33, count 0 2006.285.15:30:28.25#ibcon#read 5, iclass 33, count 0 2006.285.15:30:28.25#ibcon#about to read 6, iclass 33, count 0 2006.285.15:30:28.25#ibcon#read 6, iclass 33, count 0 2006.285.15:30:28.25#ibcon#end of sib2, iclass 33, count 0 2006.285.15:30:28.25#ibcon#*after write, iclass 33, count 0 2006.285.15:30:28.25#ibcon#*before return 0, iclass 33, count 0 2006.285.15:30:28.25#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:30:28.25#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:30:28.25#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:30:28.25#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:30:28.25$vck44/valo=8,884.99 2006.285.15:30:28.25#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.15:30:28.25#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.15:30:28.25#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:28.25#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:30:28.25#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:30:28.25#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:30:28.25#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:30:28.25#ibcon#first serial, iclass 35, count 0 2006.285.15:30:28.25#ibcon#enter sib2, iclass 35, count 0 2006.285.15:30:28.25#ibcon#flushed, iclass 35, count 0 2006.285.15:30:28.25#ibcon#about to write, iclass 35, count 0 2006.285.15:30:28.25#ibcon#wrote, iclass 35, count 0 2006.285.15:30:28.25#ibcon#about to read 3, iclass 35, count 0 2006.285.15:30:28.27#ibcon#read 3, iclass 35, count 0 2006.285.15:30:28.27#ibcon#about to read 4, iclass 35, count 0 2006.285.15:30:28.27#ibcon#read 4, iclass 35, count 0 2006.285.15:30:28.27#ibcon#about to read 5, iclass 35, count 0 2006.285.15:30:28.27#ibcon#read 5, iclass 35, count 0 2006.285.15:30:28.27#ibcon#about to read 6, iclass 35, count 0 2006.285.15:30:28.27#ibcon#read 6, iclass 35, count 0 2006.285.15:30:28.27#ibcon#end of sib2, iclass 35, count 0 2006.285.15:30:28.27#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:30:28.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:30:28.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.15:30:28.27#ibcon#*before write, iclass 35, count 0 2006.285.15:30:28.27#ibcon#enter sib2, iclass 35, count 0 2006.285.15:30:28.27#ibcon#flushed, iclass 35, count 0 2006.285.15:30:28.27#ibcon#about to write, iclass 35, count 0 2006.285.15:30:28.27#ibcon#wrote, iclass 35, count 0 2006.285.15:30:28.27#ibcon#about to read 3, iclass 35, count 0 2006.285.15:30:28.31#ibcon#read 3, iclass 35, count 0 2006.285.15:30:28.31#ibcon#about to read 4, iclass 35, count 0 2006.285.15:30:28.31#ibcon#read 4, iclass 35, count 0 2006.285.15:30:28.31#ibcon#about to read 5, iclass 35, count 0 2006.285.15:30:28.31#ibcon#read 5, iclass 35, count 0 2006.285.15:30:28.31#ibcon#about to read 6, iclass 35, count 0 2006.285.15:30:28.31#ibcon#read 6, iclass 35, count 0 2006.285.15:30:28.31#ibcon#end of sib2, iclass 35, count 0 2006.285.15:30:28.31#ibcon#*after write, iclass 35, count 0 2006.285.15:30:28.31#ibcon#*before return 0, iclass 35, count 0 2006.285.15:30:28.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:30:28.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:30:28.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:30:28.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:30:28.31$vck44/va=8,3 2006.285.15:30:28.31#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.15:30:28.31#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.15:30:28.31#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:28.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:30:28.37#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:30:28.37#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:30:28.37#ibcon#enter wrdev, iclass 37, count 2 2006.285.15:30:28.37#ibcon#first serial, iclass 37, count 2 2006.285.15:30:28.37#ibcon#enter sib2, iclass 37, count 2 2006.285.15:30:28.37#ibcon#flushed, iclass 37, count 2 2006.285.15:30:28.37#ibcon#about to write, iclass 37, count 2 2006.285.15:30:28.37#ibcon#wrote, iclass 37, count 2 2006.285.15:30:28.37#ibcon#about to read 3, iclass 37, count 2 2006.285.15:30:28.39#ibcon#read 3, iclass 37, count 2 2006.285.15:30:28.39#ibcon#about to read 4, iclass 37, count 2 2006.285.15:30:28.39#ibcon#read 4, iclass 37, count 2 2006.285.15:30:28.39#ibcon#about to read 5, iclass 37, count 2 2006.285.15:30:28.39#ibcon#read 5, iclass 37, count 2 2006.285.15:30:28.39#ibcon#about to read 6, iclass 37, count 2 2006.285.15:30:28.39#ibcon#read 6, iclass 37, count 2 2006.285.15:30:28.39#ibcon#end of sib2, iclass 37, count 2 2006.285.15:30:28.39#ibcon#*mode == 0, iclass 37, count 2 2006.285.15:30:28.39#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.15:30:28.39#ibcon#[25=AT08-03\r\n] 2006.285.15:30:28.39#ibcon#*before write, iclass 37, count 2 2006.285.15:30:28.39#ibcon#enter sib2, iclass 37, count 2 2006.285.15:30:28.39#ibcon#flushed, iclass 37, count 2 2006.285.15:30:28.39#ibcon#about to write, iclass 37, count 2 2006.285.15:30:28.39#ibcon#wrote, iclass 37, count 2 2006.285.15:30:28.39#ibcon#about to read 3, iclass 37, count 2 2006.285.15:30:28.42#ibcon#read 3, iclass 37, count 2 2006.285.15:30:28.42#ibcon#about to read 4, iclass 37, count 2 2006.285.15:30:28.42#ibcon#read 4, iclass 37, count 2 2006.285.15:30:28.42#ibcon#about to read 5, iclass 37, count 2 2006.285.15:30:28.42#ibcon#read 5, iclass 37, count 2 2006.285.15:30:28.42#ibcon#about to read 6, iclass 37, count 2 2006.285.15:30:28.42#ibcon#read 6, iclass 37, count 2 2006.285.15:30:28.42#ibcon#end of sib2, iclass 37, count 2 2006.285.15:30:28.42#ibcon#*after write, iclass 37, count 2 2006.285.15:30:28.42#ibcon#*before return 0, iclass 37, count 2 2006.285.15:30:28.42#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:30:28.42#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:30:28.42#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.15:30:28.42#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:28.42#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:30:28.54#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:30:28.54#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:30:28.54#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:30:28.54#ibcon#first serial, iclass 37, count 0 2006.285.15:30:28.54#ibcon#enter sib2, iclass 37, count 0 2006.285.15:30:28.54#ibcon#flushed, iclass 37, count 0 2006.285.15:30:28.54#ibcon#about to write, iclass 37, count 0 2006.285.15:30:28.54#ibcon#wrote, iclass 37, count 0 2006.285.15:30:28.54#ibcon#about to read 3, iclass 37, count 0 2006.285.15:30:28.56#ibcon#read 3, iclass 37, count 0 2006.285.15:30:28.56#ibcon#about to read 4, iclass 37, count 0 2006.285.15:30:28.56#ibcon#read 4, iclass 37, count 0 2006.285.15:30:28.56#ibcon#about to read 5, iclass 37, count 0 2006.285.15:30:28.56#ibcon#read 5, iclass 37, count 0 2006.285.15:30:28.56#ibcon#about to read 6, iclass 37, count 0 2006.285.15:30:28.56#ibcon#read 6, iclass 37, count 0 2006.285.15:30:28.56#ibcon#end of sib2, iclass 37, count 0 2006.285.15:30:28.56#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:30:28.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:30:28.56#ibcon#[25=USB\r\n] 2006.285.15:30:28.56#ibcon#*before write, iclass 37, count 0 2006.285.15:30:28.56#ibcon#enter sib2, iclass 37, count 0 2006.285.15:30:28.56#ibcon#flushed, iclass 37, count 0 2006.285.15:30:28.56#ibcon#about to write, iclass 37, count 0 2006.285.15:30:28.56#ibcon#wrote, iclass 37, count 0 2006.285.15:30:28.56#ibcon#about to read 3, iclass 37, count 0 2006.285.15:30:28.59#ibcon#read 3, iclass 37, count 0 2006.285.15:30:28.59#ibcon#about to read 4, iclass 37, count 0 2006.285.15:30:28.59#ibcon#read 4, iclass 37, count 0 2006.285.15:30:28.59#ibcon#about to read 5, iclass 37, count 0 2006.285.15:30:28.59#ibcon#read 5, iclass 37, count 0 2006.285.15:30:28.59#ibcon#about to read 6, iclass 37, count 0 2006.285.15:30:28.59#ibcon#read 6, iclass 37, count 0 2006.285.15:30:28.59#ibcon#end of sib2, iclass 37, count 0 2006.285.15:30:28.59#ibcon#*after write, iclass 37, count 0 2006.285.15:30:28.59#ibcon#*before return 0, iclass 37, count 0 2006.285.15:30:28.59#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:30:28.59#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:30:28.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:30:28.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:30:28.59$vck44/vblo=1,629.99 2006.285.15:30:28.59#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.15:30:28.59#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.15:30:28.59#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:28.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:30:28.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:30:28.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:30:28.59#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:30:28.59#ibcon#first serial, iclass 39, count 0 2006.285.15:30:28.59#ibcon#enter sib2, iclass 39, count 0 2006.285.15:30:28.59#ibcon#flushed, iclass 39, count 0 2006.285.15:30:28.59#ibcon#about to write, iclass 39, count 0 2006.285.15:30:28.59#ibcon#wrote, iclass 39, count 0 2006.285.15:30:28.59#ibcon#about to read 3, iclass 39, count 0 2006.285.15:30:28.61#ibcon#read 3, iclass 39, count 0 2006.285.15:30:28.61#ibcon#about to read 4, iclass 39, count 0 2006.285.15:30:28.61#ibcon#read 4, iclass 39, count 0 2006.285.15:30:28.61#ibcon#about to read 5, iclass 39, count 0 2006.285.15:30:28.61#ibcon#read 5, iclass 39, count 0 2006.285.15:30:28.61#ibcon#about to read 6, iclass 39, count 0 2006.285.15:30:28.61#ibcon#read 6, iclass 39, count 0 2006.285.15:30:28.61#ibcon#end of sib2, iclass 39, count 0 2006.285.15:30:28.61#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:30:28.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:30:28.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.15:30:28.61#ibcon#*before write, iclass 39, count 0 2006.285.15:30:28.61#ibcon#enter sib2, iclass 39, count 0 2006.285.15:30:28.61#ibcon#flushed, iclass 39, count 0 2006.285.15:30:28.61#ibcon#about to write, iclass 39, count 0 2006.285.15:30:28.61#ibcon#wrote, iclass 39, count 0 2006.285.15:30:28.61#ibcon#about to read 3, iclass 39, count 0 2006.285.15:30:28.65#ibcon#read 3, iclass 39, count 0 2006.285.15:30:28.65#ibcon#about to read 4, iclass 39, count 0 2006.285.15:30:28.65#ibcon#read 4, iclass 39, count 0 2006.285.15:30:28.65#ibcon#about to read 5, iclass 39, count 0 2006.285.15:30:28.65#ibcon#read 5, iclass 39, count 0 2006.285.15:30:28.65#ibcon#about to read 6, iclass 39, count 0 2006.285.15:30:28.65#ibcon#read 6, iclass 39, count 0 2006.285.15:30:28.65#ibcon#end of sib2, iclass 39, count 0 2006.285.15:30:28.65#ibcon#*after write, iclass 39, count 0 2006.285.15:30:28.65#ibcon#*before return 0, iclass 39, count 0 2006.285.15:30:28.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:30:28.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:30:28.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:30:28.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:30:28.65$vck44/vb=1,4 2006.285.15:30:28.65#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.15:30:28.65#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.15:30:28.65#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:28.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:30:28.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:30:28.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:30:28.65#ibcon#enter wrdev, iclass 3, count 2 2006.285.15:30:28.65#ibcon#first serial, iclass 3, count 2 2006.285.15:30:28.65#ibcon#enter sib2, iclass 3, count 2 2006.285.15:30:28.65#ibcon#flushed, iclass 3, count 2 2006.285.15:30:28.65#ibcon#about to write, iclass 3, count 2 2006.285.15:30:28.65#ibcon#wrote, iclass 3, count 2 2006.285.15:30:28.65#ibcon#about to read 3, iclass 3, count 2 2006.285.15:30:28.67#ibcon#read 3, iclass 3, count 2 2006.285.15:30:28.67#ibcon#about to read 4, iclass 3, count 2 2006.285.15:30:28.67#ibcon#read 4, iclass 3, count 2 2006.285.15:30:28.86#ibcon#about to read 5, iclass 3, count 2 2006.285.15:30:28.86#ibcon#read 5, iclass 3, count 2 2006.285.15:30:28.86#ibcon#about to read 6, iclass 3, count 2 2006.285.15:30:28.86#ibcon#read 6, iclass 3, count 2 2006.285.15:30:28.86#ibcon#end of sib2, iclass 3, count 2 2006.285.15:30:28.86#ibcon#*mode == 0, iclass 3, count 2 2006.285.15:30:28.86#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.15:30:28.86#ibcon#[27=AT01-04\r\n] 2006.285.15:30:28.86#ibcon#*before write, iclass 3, count 2 2006.285.15:30:28.86#ibcon#enter sib2, iclass 3, count 2 2006.285.15:30:28.86#ibcon#flushed, iclass 3, count 2 2006.285.15:30:28.86#ibcon#about to write, iclass 3, count 2 2006.285.15:30:28.86#ibcon#wrote, iclass 3, count 2 2006.285.15:30:28.86#ibcon#about to read 3, iclass 3, count 2 2006.285.15:30:28.89#ibcon#read 3, iclass 3, count 2 2006.285.15:30:28.89#ibcon#about to read 4, iclass 3, count 2 2006.285.15:30:28.89#ibcon#read 4, iclass 3, count 2 2006.285.15:30:28.89#ibcon#about to read 5, iclass 3, count 2 2006.285.15:30:28.89#ibcon#read 5, iclass 3, count 2 2006.285.15:30:28.89#ibcon#about to read 6, iclass 3, count 2 2006.285.15:30:28.89#ibcon#read 6, iclass 3, count 2 2006.285.15:30:28.89#ibcon#end of sib2, iclass 3, count 2 2006.285.15:30:28.89#ibcon#*after write, iclass 3, count 2 2006.285.15:30:28.89#ibcon#*before return 0, iclass 3, count 2 2006.285.15:30:28.89#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:30:28.89#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:30:28.89#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.15:30:28.89#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:28.89#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:30:29.01#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:30:29.01#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:30:29.01#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:30:29.01#ibcon#first serial, iclass 3, count 0 2006.285.15:30:29.01#ibcon#enter sib2, iclass 3, count 0 2006.285.15:30:29.01#ibcon#flushed, iclass 3, count 0 2006.285.15:30:29.01#ibcon#about to write, iclass 3, count 0 2006.285.15:30:29.01#ibcon#wrote, iclass 3, count 0 2006.285.15:30:29.01#ibcon#about to read 3, iclass 3, count 0 2006.285.15:30:29.03#ibcon#read 3, iclass 3, count 0 2006.285.15:30:29.03#ibcon#about to read 4, iclass 3, count 0 2006.285.15:30:29.03#ibcon#read 4, iclass 3, count 0 2006.285.15:30:29.03#ibcon#about to read 5, iclass 3, count 0 2006.285.15:30:29.03#ibcon#read 5, iclass 3, count 0 2006.285.15:30:29.03#ibcon#about to read 6, iclass 3, count 0 2006.285.15:30:29.03#ibcon#read 6, iclass 3, count 0 2006.285.15:30:29.03#ibcon#end of sib2, iclass 3, count 0 2006.285.15:30:29.03#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:30:29.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:30:29.03#ibcon#[27=USB\r\n] 2006.285.15:30:29.03#ibcon#*before write, iclass 3, count 0 2006.285.15:30:29.03#ibcon#enter sib2, iclass 3, count 0 2006.285.15:30:29.03#ibcon#flushed, iclass 3, count 0 2006.285.15:30:29.03#ibcon#about to write, iclass 3, count 0 2006.285.15:30:29.03#ibcon#wrote, iclass 3, count 0 2006.285.15:30:29.03#ibcon#about to read 3, iclass 3, count 0 2006.285.15:30:29.06#ibcon#read 3, iclass 3, count 0 2006.285.15:30:29.06#ibcon#about to read 4, iclass 3, count 0 2006.285.15:30:29.06#ibcon#read 4, iclass 3, count 0 2006.285.15:30:29.06#ibcon#about to read 5, iclass 3, count 0 2006.285.15:30:29.06#ibcon#read 5, iclass 3, count 0 2006.285.15:30:29.06#ibcon#about to read 6, iclass 3, count 0 2006.285.15:30:29.06#ibcon#read 6, iclass 3, count 0 2006.285.15:30:29.06#ibcon#end of sib2, iclass 3, count 0 2006.285.15:30:29.06#ibcon#*after write, iclass 3, count 0 2006.285.15:30:29.06#ibcon#*before return 0, iclass 3, count 0 2006.285.15:30:29.06#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:30:29.06#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:30:29.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:30:29.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:30:29.06$vck44/vblo=2,634.99 2006.285.15:30:29.06#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.15:30:29.06#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.15:30:29.06#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:29.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:30:29.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:30:29.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:30:29.06#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:30:29.06#ibcon#first serial, iclass 5, count 0 2006.285.15:30:29.06#ibcon#enter sib2, iclass 5, count 0 2006.285.15:30:29.06#ibcon#flushed, iclass 5, count 0 2006.285.15:30:29.06#ibcon#about to write, iclass 5, count 0 2006.285.15:30:29.06#ibcon#wrote, iclass 5, count 0 2006.285.15:30:29.06#ibcon#about to read 3, iclass 5, count 0 2006.285.15:30:29.08#ibcon#read 3, iclass 5, count 0 2006.285.15:30:29.08#ibcon#about to read 4, iclass 5, count 0 2006.285.15:30:29.08#ibcon#read 4, iclass 5, count 0 2006.285.15:30:29.08#ibcon#about to read 5, iclass 5, count 0 2006.285.15:30:29.08#ibcon#read 5, iclass 5, count 0 2006.285.15:30:29.08#ibcon#about to read 6, iclass 5, count 0 2006.285.15:30:29.08#ibcon#read 6, iclass 5, count 0 2006.285.15:30:29.08#ibcon#end of sib2, iclass 5, count 0 2006.285.15:30:29.08#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:30:29.08#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:30:29.08#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.15:30:29.08#ibcon#*before write, iclass 5, count 0 2006.285.15:30:29.08#ibcon#enter sib2, iclass 5, count 0 2006.285.15:30:29.08#ibcon#flushed, iclass 5, count 0 2006.285.15:30:29.08#ibcon#about to write, iclass 5, count 0 2006.285.15:30:29.08#ibcon#wrote, iclass 5, count 0 2006.285.15:30:29.08#ibcon#about to read 3, iclass 5, count 0 2006.285.15:30:29.12#ibcon#read 3, iclass 5, count 0 2006.285.15:30:29.12#ibcon#about to read 4, iclass 5, count 0 2006.285.15:30:29.12#ibcon#read 4, iclass 5, count 0 2006.285.15:30:29.12#ibcon#about to read 5, iclass 5, count 0 2006.285.15:30:29.12#ibcon#read 5, iclass 5, count 0 2006.285.15:30:29.12#ibcon#about to read 6, iclass 5, count 0 2006.285.15:30:29.12#ibcon#read 6, iclass 5, count 0 2006.285.15:30:29.12#ibcon#end of sib2, iclass 5, count 0 2006.285.15:30:29.12#ibcon#*after write, iclass 5, count 0 2006.285.15:30:29.12#ibcon#*before return 0, iclass 5, count 0 2006.285.15:30:29.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:30:29.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:30:29.12#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:30:29.12#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:30:29.12$vck44/vb=2,5 2006.285.15:30:29.12#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.15:30:29.12#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.15:30:29.12#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:29.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:30:29.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:30:29.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:30:29.18#ibcon#enter wrdev, iclass 7, count 2 2006.285.15:30:29.18#ibcon#first serial, iclass 7, count 2 2006.285.15:30:29.18#ibcon#enter sib2, iclass 7, count 2 2006.285.15:30:29.18#ibcon#flushed, iclass 7, count 2 2006.285.15:30:29.18#ibcon#about to write, iclass 7, count 2 2006.285.15:30:29.18#ibcon#wrote, iclass 7, count 2 2006.285.15:30:29.18#ibcon#about to read 3, iclass 7, count 2 2006.285.15:30:29.20#ibcon#read 3, iclass 7, count 2 2006.285.15:30:29.20#ibcon#about to read 4, iclass 7, count 2 2006.285.15:30:29.20#ibcon#read 4, iclass 7, count 2 2006.285.15:30:29.20#ibcon#about to read 5, iclass 7, count 2 2006.285.15:30:29.20#ibcon#read 5, iclass 7, count 2 2006.285.15:30:29.20#ibcon#about to read 6, iclass 7, count 2 2006.285.15:30:29.20#ibcon#read 6, iclass 7, count 2 2006.285.15:30:29.20#ibcon#end of sib2, iclass 7, count 2 2006.285.15:30:29.20#ibcon#*mode == 0, iclass 7, count 2 2006.285.15:30:29.20#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.15:30:29.20#ibcon#[27=AT02-05\r\n] 2006.285.15:30:29.20#ibcon#*before write, iclass 7, count 2 2006.285.15:30:29.20#ibcon#enter sib2, iclass 7, count 2 2006.285.15:30:29.20#ibcon#flushed, iclass 7, count 2 2006.285.15:30:29.20#ibcon#about to write, iclass 7, count 2 2006.285.15:30:29.20#ibcon#wrote, iclass 7, count 2 2006.285.15:30:29.20#ibcon#about to read 3, iclass 7, count 2 2006.285.15:30:29.23#ibcon#read 3, iclass 7, count 2 2006.285.15:30:29.23#ibcon#about to read 4, iclass 7, count 2 2006.285.15:30:29.23#ibcon#read 4, iclass 7, count 2 2006.285.15:30:29.23#ibcon#about to read 5, iclass 7, count 2 2006.285.15:30:29.23#ibcon#read 5, iclass 7, count 2 2006.285.15:30:29.23#ibcon#about to read 6, iclass 7, count 2 2006.285.15:30:29.23#ibcon#read 6, iclass 7, count 2 2006.285.15:30:29.23#ibcon#end of sib2, iclass 7, count 2 2006.285.15:30:29.23#ibcon#*after write, iclass 7, count 2 2006.285.15:30:29.23#ibcon#*before return 0, iclass 7, count 2 2006.285.15:30:29.23#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:30:29.23#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:30:29.23#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.15:30:29.23#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:29.23#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:30:29.35#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:30:29.35#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:30:29.35#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:30:29.35#ibcon#first serial, iclass 7, count 0 2006.285.15:30:29.35#ibcon#enter sib2, iclass 7, count 0 2006.285.15:30:29.35#ibcon#flushed, iclass 7, count 0 2006.285.15:30:29.35#ibcon#about to write, iclass 7, count 0 2006.285.15:30:29.35#ibcon#wrote, iclass 7, count 0 2006.285.15:30:29.35#ibcon#about to read 3, iclass 7, count 0 2006.285.15:30:29.37#ibcon#read 3, iclass 7, count 0 2006.285.15:30:29.37#ibcon#about to read 4, iclass 7, count 0 2006.285.15:30:29.37#ibcon#read 4, iclass 7, count 0 2006.285.15:30:29.37#ibcon#about to read 5, iclass 7, count 0 2006.285.15:30:29.37#ibcon#read 5, iclass 7, count 0 2006.285.15:30:29.37#ibcon#about to read 6, iclass 7, count 0 2006.285.15:30:29.37#ibcon#read 6, iclass 7, count 0 2006.285.15:30:29.37#ibcon#end of sib2, iclass 7, count 0 2006.285.15:30:29.37#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:30:29.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:30:29.37#ibcon#[27=USB\r\n] 2006.285.15:30:29.37#ibcon#*before write, iclass 7, count 0 2006.285.15:30:29.37#ibcon#enter sib2, iclass 7, count 0 2006.285.15:30:29.37#ibcon#flushed, iclass 7, count 0 2006.285.15:30:29.37#ibcon#about to write, iclass 7, count 0 2006.285.15:30:29.37#ibcon#wrote, iclass 7, count 0 2006.285.15:30:29.37#ibcon#about to read 3, iclass 7, count 0 2006.285.15:30:29.40#ibcon#read 3, iclass 7, count 0 2006.285.15:30:29.40#ibcon#about to read 4, iclass 7, count 0 2006.285.15:30:29.40#ibcon#read 4, iclass 7, count 0 2006.285.15:30:29.40#ibcon#about to read 5, iclass 7, count 0 2006.285.15:30:29.40#ibcon#read 5, iclass 7, count 0 2006.285.15:30:29.40#ibcon#about to read 6, iclass 7, count 0 2006.285.15:30:29.40#ibcon#read 6, iclass 7, count 0 2006.285.15:30:29.40#ibcon#end of sib2, iclass 7, count 0 2006.285.15:30:29.40#ibcon#*after write, iclass 7, count 0 2006.285.15:30:29.40#ibcon#*before return 0, iclass 7, count 0 2006.285.15:30:29.40#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:30:29.40#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:30:29.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:30:29.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:30:29.40$vck44/vblo=3,649.99 2006.285.15:30:29.40#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.15:30:29.40#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.15:30:29.40#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:29.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:30:29.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:30:29.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:30:29.40#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:30:29.40#ibcon#first serial, iclass 11, count 0 2006.285.15:30:29.40#ibcon#enter sib2, iclass 11, count 0 2006.285.15:30:29.40#ibcon#flushed, iclass 11, count 0 2006.285.15:30:29.40#ibcon#about to write, iclass 11, count 0 2006.285.15:30:29.40#ibcon#wrote, iclass 11, count 0 2006.285.15:30:29.40#ibcon#about to read 3, iclass 11, count 0 2006.285.15:30:29.42#ibcon#read 3, iclass 11, count 0 2006.285.15:30:29.42#ibcon#about to read 4, iclass 11, count 0 2006.285.15:30:29.42#ibcon#read 4, iclass 11, count 0 2006.285.15:30:29.42#ibcon#about to read 5, iclass 11, count 0 2006.285.15:30:29.42#ibcon#read 5, iclass 11, count 0 2006.285.15:30:29.42#ibcon#about to read 6, iclass 11, count 0 2006.285.15:30:29.42#ibcon#read 6, iclass 11, count 0 2006.285.15:30:29.42#ibcon#end of sib2, iclass 11, count 0 2006.285.15:30:29.42#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:30:29.42#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:30:29.42#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.15:30:29.42#ibcon#*before write, iclass 11, count 0 2006.285.15:30:29.42#ibcon#enter sib2, iclass 11, count 0 2006.285.15:30:29.42#ibcon#flushed, iclass 11, count 0 2006.285.15:30:29.42#ibcon#about to write, iclass 11, count 0 2006.285.15:30:29.42#ibcon#wrote, iclass 11, count 0 2006.285.15:30:29.42#ibcon#about to read 3, iclass 11, count 0 2006.285.15:30:29.46#ibcon#read 3, iclass 11, count 0 2006.285.15:30:29.46#ibcon#about to read 4, iclass 11, count 0 2006.285.15:30:29.46#ibcon#read 4, iclass 11, count 0 2006.285.15:30:29.46#ibcon#about to read 5, iclass 11, count 0 2006.285.15:30:29.46#ibcon#read 5, iclass 11, count 0 2006.285.15:30:29.46#ibcon#about to read 6, iclass 11, count 0 2006.285.15:30:29.46#ibcon#read 6, iclass 11, count 0 2006.285.15:30:29.46#ibcon#end of sib2, iclass 11, count 0 2006.285.15:30:29.46#ibcon#*after write, iclass 11, count 0 2006.285.15:30:29.46#ibcon#*before return 0, iclass 11, count 0 2006.285.15:30:29.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:30:29.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:30:29.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:30:29.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:30:29.46$vck44/vb=3,4 2006.285.15:30:29.46#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.15:30:29.46#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.15:30:29.46#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:29.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:30:29.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:30:29.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:30:29.52#ibcon#enter wrdev, iclass 13, count 2 2006.285.15:30:29.52#ibcon#first serial, iclass 13, count 2 2006.285.15:30:29.52#ibcon#enter sib2, iclass 13, count 2 2006.285.15:30:29.52#ibcon#flushed, iclass 13, count 2 2006.285.15:30:29.52#ibcon#about to write, iclass 13, count 2 2006.285.15:30:29.52#ibcon#wrote, iclass 13, count 2 2006.285.15:30:29.52#ibcon#about to read 3, iclass 13, count 2 2006.285.15:30:29.54#ibcon#read 3, iclass 13, count 2 2006.285.15:30:29.54#ibcon#about to read 4, iclass 13, count 2 2006.285.15:30:29.54#ibcon#read 4, iclass 13, count 2 2006.285.15:30:29.54#ibcon#about to read 5, iclass 13, count 2 2006.285.15:30:29.54#ibcon#read 5, iclass 13, count 2 2006.285.15:30:29.54#ibcon#about to read 6, iclass 13, count 2 2006.285.15:30:29.54#ibcon#read 6, iclass 13, count 2 2006.285.15:30:29.54#ibcon#end of sib2, iclass 13, count 2 2006.285.15:30:29.54#ibcon#*mode == 0, iclass 13, count 2 2006.285.15:30:29.54#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.15:30:29.54#ibcon#[27=AT03-04\r\n] 2006.285.15:30:29.54#ibcon#*before write, iclass 13, count 2 2006.285.15:30:29.54#ibcon#enter sib2, iclass 13, count 2 2006.285.15:30:29.54#ibcon#flushed, iclass 13, count 2 2006.285.15:30:29.54#ibcon#about to write, iclass 13, count 2 2006.285.15:30:29.54#ibcon#wrote, iclass 13, count 2 2006.285.15:30:29.54#ibcon#about to read 3, iclass 13, count 2 2006.285.15:30:29.57#ibcon#read 3, iclass 13, count 2 2006.285.15:30:29.57#ibcon#about to read 4, iclass 13, count 2 2006.285.15:30:29.57#ibcon#read 4, iclass 13, count 2 2006.285.15:30:29.57#ibcon#about to read 5, iclass 13, count 2 2006.285.15:30:29.57#ibcon#read 5, iclass 13, count 2 2006.285.15:30:29.57#ibcon#about to read 6, iclass 13, count 2 2006.285.15:30:29.57#ibcon#read 6, iclass 13, count 2 2006.285.15:30:29.57#ibcon#end of sib2, iclass 13, count 2 2006.285.15:30:29.57#ibcon#*after write, iclass 13, count 2 2006.285.15:30:29.57#ibcon#*before return 0, iclass 13, count 2 2006.285.15:30:29.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:30:29.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:30:29.57#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.15:30:29.57#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:29.57#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:30:29.69#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:30:29.69#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:30:29.69#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:30:29.69#ibcon#first serial, iclass 13, count 0 2006.285.15:30:29.69#ibcon#enter sib2, iclass 13, count 0 2006.285.15:30:29.69#ibcon#flushed, iclass 13, count 0 2006.285.15:30:29.69#ibcon#about to write, iclass 13, count 0 2006.285.15:30:29.69#ibcon#wrote, iclass 13, count 0 2006.285.15:30:29.69#ibcon#about to read 3, iclass 13, count 0 2006.285.15:30:29.71#ibcon#read 3, iclass 13, count 0 2006.285.15:30:29.71#ibcon#about to read 4, iclass 13, count 0 2006.285.15:30:29.71#ibcon#read 4, iclass 13, count 0 2006.285.15:30:29.71#ibcon#about to read 5, iclass 13, count 0 2006.285.15:30:29.71#ibcon#read 5, iclass 13, count 0 2006.285.15:30:29.71#ibcon#about to read 6, iclass 13, count 0 2006.285.15:30:29.71#ibcon#read 6, iclass 13, count 0 2006.285.15:30:29.71#ibcon#end of sib2, iclass 13, count 0 2006.285.15:30:29.71#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:30:29.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:30:29.71#ibcon#[27=USB\r\n] 2006.285.15:30:29.71#ibcon#*before write, iclass 13, count 0 2006.285.15:30:29.71#ibcon#enter sib2, iclass 13, count 0 2006.285.15:30:29.71#ibcon#flushed, iclass 13, count 0 2006.285.15:30:29.71#ibcon#about to write, iclass 13, count 0 2006.285.15:30:29.71#ibcon#wrote, iclass 13, count 0 2006.285.15:30:29.71#ibcon#about to read 3, iclass 13, count 0 2006.285.15:30:29.74#ibcon#read 3, iclass 13, count 0 2006.285.15:30:29.74#ibcon#about to read 4, iclass 13, count 0 2006.285.15:30:29.74#ibcon#read 4, iclass 13, count 0 2006.285.15:30:29.74#ibcon#about to read 5, iclass 13, count 0 2006.285.15:30:29.74#ibcon#read 5, iclass 13, count 0 2006.285.15:30:29.74#ibcon#about to read 6, iclass 13, count 0 2006.285.15:30:29.74#ibcon#read 6, iclass 13, count 0 2006.285.15:30:29.74#ibcon#end of sib2, iclass 13, count 0 2006.285.15:30:29.74#ibcon#*after write, iclass 13, count 0 2006.285.15:30:29.74#ibcon#*before return 0, iclass 13, count 0 2006.285.15:30:29.74#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:30:29.74#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:30:29.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:30:29.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:30:29.74$vck44/vblo=4,679.99 2006.285.15:30:29.74#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.15:30:29.74#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.15:30:29.74#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:29.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:30:29.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:30:29.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:30:29.74#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:30:29.74#ibcon#first serial, iclass 15, count 0 2006.285.15:30:29.74#ibcon#enter sib2, iclass 15, count 0 2006.285.15:30:29.74#ibcon#flushed, iclass 15, count 0 2006.285.15:30:29.74#ibcon#about to write, iclass 15, count 0 2006.285.15:30:29.74#ibcon#wrote, iclass 15, count 0 2006.285.15:30:29.74#ibcon#about to read 3, iclass 15, count 0 2006.285.15:30:29.76#ibcon#read 3, iclass 15, count 0 2006.285.15:30:29.80#ibcon#about to read 4, iclass 15, count 0 2006.285.15:30:29.80#ibcon#read 4, iclass 15, count 0 2006.285.15:30:29.80#ibcon#about to read 5, iclass 15, count 0 2006.285.15:30:29.80#ibcon#read 5, iclass 15, count 0 2006.285.15:30:29.80#ibcon#about to read 6, iclass 15, count 0 2006.285.15:30:29.80#ibcon#read 6, iclass 15, count 0 2006.285.15:30:29.80#ibcon#end of sib2, iclass 15, count 0 2006.285.15:30:29.80#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:30:29.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:30:29.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.15:30:29.80#ibcon#*before write, iclass 15, count 0 2006.285.15:30:29.80#ibcon#enter sib2, iclass 15, count 0 2006.285.15:30:29.80#ibcon#flushed, iclass 15, count 0 2006.285.15:30:29.80#ibcon#about to write, iclass 15, count 0 2006.285.15:30:29.80#ibcon#wrote, iclass 15, count 0 2006.285.15:30:29.80#ibcon#about to read 3, iclass 15, count 0 2006.285.15:30:29.84#ibcon#read 3, iclass 15, count 0 2006.285.15:30:29.84#ibcon#about to read 4, iclass 15, count 0 2006.285.15:30:29.84#ibcon#read 4, iclass 15, count 0 2006.285.15:30:29.84#ibcon#about to read 5, iclass 15, count 0 2006.285.15:30:29.84#ibcon#read 5, iclass 15, count 0 2006.285.15:30:29.84#ibcon#about to read 6, iclass 15, count 0 2006.285.15:30:29.84#ibcon#read 6, iclass 15, count 0 2006.285.15:30:29.84#ibcon#end of sib2, iclass 15, count 0 2006.285.15:30:29.84#ibcon#*after write, iclass 15, count 0 2006.285.15:30:29.84#ibcon#*before return 0, iclass 15, count 0 2006.285.15:30:29.84#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:30:29.84#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:30:29.84#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:30:29.84#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:30:29.84$vck44/vb=4,5 2006.285.15:30:29.84#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.15:30:29.84#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.15:30:29.84#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:29.84#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:30:29.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:30:29.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:30:29.86#ibcon#enter wrdev, iclass 17, count 2 2006.285.15:30:29.86#ibcon#first serial, iclass 17, count 2 2006.285.15:30:29.86#ibcon#enter sib2, iclass 17, count 2 2006.285.15:30:29.86#ibcon#flushed, iclass 17, count 2 2006.285.15:30:29.86#ibcon#about to write, iclass 17, count 2 2006.285.15:30:29.86#ibcon#wrote, iclass 17, count 2 2006.285.15:30:29.86#ibcon#about to read 3, iclass 17, count 2 2006.285.15:30:29.88#ibcon#read 3, iclass 17, count 2 2006.285.15:30:29.88#ibcon#about to read 4, iclass 17, count 2 2006.285.15:30:29.88#ibcon#read 4, iclass 17, count 2 2006.285.15:30:29.88#ibcon#about to read 5, iclass 17, count 2 2006.285.15:30:29.88#ibcon#read 5, iclass 17, count 2 2006.285.15:30:29.88#ibcon#about to read 6, iclass 17, count 2 2006.285.15:30:29.88#ibcon#read 6, iclass 17, count 2 2006.285.15:30:29.88#ibcon#end of sib2, iclass 17, count 2 2006.285.15:30:29.88#ibcon#*mode == 0, iclass 17, count 2 2006.285.15:30:29.88#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.15:30:29.88#ibcon#[27=AT04-05\r\n] 2006.285.15:30:29.88#ibcon#*before write, iclass 17, count 2 2006.285.15:30:29.88#ibcon#enter sib2, iclass 17, count 2 2006.285.15:30:29.88#ibcon#flushed, iclass 17, count 2 2006.285.15:30:29.88#ibcon#about to write, iclass 17, count 2 2006.285.15:30:29.88#ibcon#wrote, iclass 17, count 2 2006.285.15:30:29.88#ibcon#about to read 3, iclass 17, count 2 2006.285.15:30:29.91#ibcon#read 3, iclass 17, count 2 2006.285.15:30:29.91#ibcon#about to read 4, iclass 17, count 2 2006.285.15:30:29.91#ibcon#read 4, iclass 17, count 2 2006.285.15:30:29.91#ibcon#about to read 5, iclass 17, count 2 2006.285.15:30:29.91#ibcon#read 5, iclass 17, count 2 2006.285.15:30:29.91#ibcon#about to read 6, iclass 17, count 2 2006.285.15:30:29.91#ibcon#read 6, iclass 17, count 2 2006.285.15:30:29.91#ibcon#end of sib2, iclass 17, count 2 2006.285.15:30:29.91#ibcon#*after write, iclass 17, count 2 2006.285.15:30:29.91#ibcon#*before return 0, iclass 17, count 2 2006.285.15:30:29.91#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:30:29.91#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:30:29.91#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.15:30:29.91#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:29.91#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:30:30.03#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:30:30.03#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:30:30.03#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:30:30.03#ibcon#first serial, iclass 17, count 0 2006.285.15:30:30.03#ibcon#enter sib2, iclass 17, count 0 2006.285.15:30:30.03#ibcon#flushed, iclass 17, count 0 2006.285.15:30:30.03#ibcon#about to write, iclass 17, count 0 2006.285.15:30:30.03#ibcon#wrote, iclass 17, count 0 2006.285.15:30:30.03#ibcon#about to read 3, iclass 17, count 0 2006.285.15:30:30.05#ibcon#read 3, iclass 17, count 0 2006.285.15:30:30.05#ibcon#about to read 4, iclass 17, count 0 2006.285.15:30:30.05#ibcon#read 4, iclass 17, count 0 2006.285.15:30:30.05#ibcon#about to read 5, iclass 17, count 0 2006.285.15:30:30.05#ibcon#read 5, iclass 17, count 0 2006.285.15:30:30.05#ibcon#about to read 6, iclass 17, count 0 2006.285.15:30:30.05#ibcon#read 6, iclass 17, count 0 2006.285.15:30:30.05#ibcon#end of sib2, iclass 17, count 0 2006.285.15:30:30.05#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:30:30.05#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:30:30.05#ibcon#[27=USB\r\n] 2006.285.15:30:30.05#ibcon#*before write, iclass 17, count 0 2006.285.15:30:30.05#ibcon#enter sib2, iclass 17, count 0 2006.285.15:30:30.05#ibcon#flushed, iclass 17, count 0 2006.285.15:30:30.05#ibcon#about to write, iclass 17, count 0 2006.285.15:30:30.05#ibcon#wrote, iclass 17, count 0 2006.285.15:30:30.05#ibcon#about to read 3, iclass 17, count 0 2006.285.15:30:30.08#ibcon#read 3, iclass 17, count 0 2006.285.15:30:30.08#ibcon#about to read 4, iclass 17, count 0 2006.285.15:30:30.08#ibcon#read 4, iclass 17, count 0 2006.285.15:30:30.08#ibcon#about to read 5, iclass 17, count 0 2006.285.15:30:30.08#ibcon#read 5, iclass 17, count 0 2006.285.15:30:30.08#ibcon#about to read 6, iclass 17, count 0 2006.285.15:30:30.08#ibcon#read 6, iclass 17, count 0 2006.285.15:30:30.08#ibcon#end of sib2, iclass 17, count 0 2006.285.15:30:30.08#ibcon#*after write, iclass 17, count 0 2006.285.15:30:30.08#ibcon#*before return 0, iclass 17, count 0 2006.285.15:30:30.08#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:30:30.08#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:30:30.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:30:30.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:30:30.08$vck44/vblo=5,709.99 2006.285.15:30:30.08#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.15:30:30.08#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.15:30:30.08#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:30.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:30:30.08#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:30:30.08#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:30:30.08#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:30:30.08#ibcon#first serial, iclass 19, count 0 2006.285.15:30:30.08#ibcon#enter sib2, iclass 19, count 0 2006.285.15:30:30.08#ibcon#flushed, iclass 19, count 0 2006.285.15:30:30.08#ibcon#about to write, iclass 19, count 0 2006.285.15:30:30.08#ibcon#wrote, iclass 19, count 0 2006.285.15:30:30.08#ibcon#about to read 3, iclass 19, count 0 2006.285.15:30:30.10#ibcon#read 3, iclass 19, count 0 2006.285.15:30:30.10#ibcon#about to read 4, iclass 19, count 0 2006.285.15:30:30.10#ibcon#read 4, iclass 19, count 0 2006.285.15:30:30.10#ibcon#about to read 5, iclass 19, count 0 2006.285.15:30:30.10#ibcon#read 5, iclass 19, count 0 2006.285.15:30:30.10#ibcon#about to read 6, iclass 19, count 0 2006.285.15:30:30.10#ibcon#read 6, iclass 19, count 0 2006.285.15:30:30.10#ibcon#end of sib2, iclass 19, count 0 2006.285.15:30:30.10#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:30:30.10#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:30:30.10#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.15:30:30.10#ibcon#*before write, iclass 19, count 0 2006.285.15:30:30.10#ibcon#enter sib2, iclass 19, count 0 2006.285.15:30:30.10#ibcon#flushed, iclass 19, count 0 2006.285.15:30:30.10#ibcon#about to write, iclass 19, count 0 2006.285.15:30:30.10#ibcon#wrote, iclass 19, count 0 2006.285.15:30:30.10#ibcon#about to read 3, iclass 19, count 0 2006.285.15:30:30.14#ibcon#read 3, iclass 19, count 0 2006.285.15:30:30.14#ibcon#about to read 4, iclass 19, count 0 2006.285.15:30:30.14#ibcon#read 4, iclass 19, count 0 2006.285.15:30:30.14#ibcon#about to read 5, iclass 19, count 0 2006.285.15:30:30.14#ibcon#read 5, iclass 19, count 0 2006.285.15:30:30.14#ibcon#about to read 6, iclass 19, count 0 2006.285.15:30:30.14#ibcon#read 6, iclass 19, count 0 2006.285.15:30:30.14#ibcon#end of sib2, iclass 19, count 0 2006.285.15:30:30.14#ibcon#*after write, iclass 19, count 0 2006.285.15:30:30.14#ibcon#*before return 0, iclass 19, count 0 2006.285.15:30:30.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:30:30.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:30:30.14#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:30:30.14#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:30:30.14$vck44/vb=5,4 2006.285.15:30:30.14#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.15:30:30.14#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.15:30:30.14#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:30.14#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:30:30.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:30:30.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:30:30.20#ibcon#enter wrdev, iclass 21, count 2 2006.285.15:30:30.20#ibcon#first serial, iclass 21, count 2 2006.285.15:30:30.20#ibcon#enter sib2, iclass 21, count 2 2006.285.15:30:30.20#ibcon#flushed, iclass 21, count 2 2006.285.15:30:30.20#ibcon#about to write, iclass 21, count 2 2006.285.15:30:30.20#ibcon#wrote, iclass 21, count 2 2006.285.15:30:30.20#ibcon#about to read 3, iclass 21, count 2 2006.285.15:30:30.22#ibcon#read 3, iclass 21, count 2 2006.285.15:30:30.22#ibcon#about to read 4, iclass 21, count 2 2006.285.15:30:30.22#ibcon#read 4, iclass 21, count 2 2006.285.15:30:30.22#ibcon#about to read 5, iclass 21, count 2 2006.285.15:30:30.22#ibcon#read 5, iclass 21, count 2 2006.285.15:30:30.22#ibcon#about to read 6, iclass 21, count 2 2006.285.15:30:30.22#ibcon#read 6, iclass 21, count 2 2006.285.15:30:30.22#ibcon#end of sib2, iclass 21, count 2 2006.285.15:30:30.22#ibcon#*mode == 0, iclass 21, count 2 2006.285.15:30:30.22#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.15:30:30.22#ibcon#[27=AT05-04\r\n] 2006.285.15:30:30.22#ibcon#*before write, iclass 21, count 2 2006.285.15:30:30.22#ibcon#enter sib2, iclass 21, count 2 2006.285.15:30:30.22#ibcon#flushed, iclass 21, count 2 2006.285.15:30:30.22#ibcon#about to write, iclass 21, count 2 2006.285.15:30:30.22#ibcon#wrote, iclass 21, count 2 2006.285.15:30:30.22#ibcon#about to read 3, iclass 21, count 2 2006.285.15:30:30.25#ibcon#read 3, iclass 21, count 2 2006.285.15:30:30.25#ibcon#about to read 4, iclass 21, count 2 2006.285.15:30:30.25#ibcon#read 4, iclass 21, count 2 2006.285.15:30:30.25#ibcon#about to read 5, iclass 21, count 2 2006.285.15:30:30.25#ibcon#read 5, iclass 21, count 2 2006.285.15:30:30.25#ibcon#about to read 6, iclass 21, count 2 2006.285.15:30:30.25#ibcon#read 6, iclass 21, count 2 2006.285.15:30:30.25#ibcon#end of sib2, iclass 21, count 2 2006.285.15:30:30.25#ibcon#*after write, iclass 21, count 2 2006.285.15:30:30.25#ibcon#*before return 0, iclass 21, count 2 2006.285.15:30:30.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:30:30.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:30:30.25#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.15:30:30.25#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:30.25#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:30:30.37#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:30:30.37#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:30:30.37#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:30:30.37#ibcon#first serial, iclass 21, count 0 2006.285.15:30:30.37#ibcon#enter sib2, iclass 21, count 0 2006.285.15:30:30.37#ibcon#flushed, iclass 21, count 0 2006.285.15:30:30.37#ibcon#about to write, iclass 21, count 0 2006.285.15:30:30.37#ibcon#wrote, iclass 21, count 0 2006.285.15:30:30.37#ibcon#about to read 3, iclass 21, count 0 2006.285.15:30:30.39#ibcon#read 3, iclass 21, count 0 2006.285.15:30:30.39#ibcon#about to read 4, iclass 21, count 0 2006.285.15:30:30.39#ibcon#read 4, iclass 21, count 0 2006.285.15:30:30.39#ibcon#about to read 5, iclass 21, count 0 2006.285.15:30:30.39#ibcon#read 5, iclass 21, count 0 2006.285.15:30:30.39#ibcon#about to read 6, iclass 21, count 0 2006.285.15:30:30.39#ibcon#read 6, iclass 21, count 0 2006.285.15:30:30.39#ibcon#end of sib2, iclass 21, count 0 2006.285.15:30:30.39#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:30:30.39#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:30:30.39#ibcon#[27=USB\r\n] 2006.285.15:30:30.39#ibcon#*before write, iclass 21, count 0 2006.285.15:30:30.39#ibcon#enter sib2, iclass 21, count 0 2006.285.15:30:30.39#ibcon#flushed, iclass 21, count 0 2006.285.15:30:30.39#ibcon#about to write, iclass 21, count 0 2006.285.15:30:30.39#ibcon#wrote, iclass 21, count 0 2006.285.15:30:30.39#ibcon#about to read 3, iclass 21, count 0 2006.285.15:30:30.42#ibcon#read 3, iclass 21, count 0 2006.285.15:30:30.42#ibcon#about to read 4, iclass 21, count 0 2006.285.15:30:30.42#ibcon#read 4, iclass 21, count 0 2006.285.15:30:30.42#ibcon#about to read 5, iclass 21, count 0 2006.285.15:30:30.42#ibcon#read 5, iclass 21, count 0 2006.285.15:30:30.42#ibcon#about to read 6, iclass 21, count 0 2006.285.15:30:30.42#ibcon#read 6, iclass 21, count 0 2006.285.15:30:30.42#ibcon#end of sib2, iclass 21, count 0 2006.285.15:30:30.42#ibcon#*after write, iclass 21, count 0 2006.285.15:30:30.42#ibcon#*before return 0, iclass 21, count 0 2006.285.15:30:30.42#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:30:30.42#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:30:30.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:30:30.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:30:30.42$vck44/vblo=6,719.99 2006.285.15:30:30.42#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.15:30:30.42#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.15:30:30.42#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:30.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:30:30.42#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:30:30.42#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:30:30.42#ibcon#enter wrdev, iclass 23, count 0 2006.285.15:30:30.42#ibcon#first serial, iclass 23, count 0 2006.285.15:30:30.42#ibcon#enter sib2, iclass 23, count 0 2006.285.15:30:30.42#ibcon#flushed, iclass 23, count 0 2006.285.15:30:30.42#ibcon#about to write, iclass 23, count 0 2006.285.15:30:30.42#ibcon#wrote, iclass 23, count 0 2006.285.15:30:30.42#ibcon#about to read 3, iclass 23, count 0 2006.285.15:30:30.44#ibcon#read 3, iclass 23, count 0 2006.285.15:30:30.44#ibcon#about to read 4, iclass 23, count 0 2006.285.15:30:30.44#ibcon#read 4, iclass 23, count 0 2006.285.15:30:30.44#ibcon#about to read 5, iclass 23, count 0 2006.285.15:30:30.44#ibcon#read 5, iclass 23, count 0 2006.285.15:30:30.44#ibcon#about to read 6, iclass 23, count 0 2006.285.15:30:30.44#ibcon#read 6, iclass 23, count 0 2006.285.15:30:30.44#ibcon#end of sib2, iclass 23, count 0 2006.285.15:30:30.44#ibcon#*mode == 0, iclass 23, count 0 2006.285.15:30:30.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.15:30:30.44#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.15:30:30.44#ibcon#*before write, iclass 23, count 0 2006.285.15:30:30.44#ibcon#enter sib2, iclass 23, count 0 2006.285.15:30:30.44#ibcon#flushed, iclass 23, count 0 2006.285.15:30:30.44#ibcon#about to write, iclass 23, count 0 2006.285.15:30:30.44#ibcon#wrote, iclass 23, count 0 2006.285.15:30:30.44#ibcon#about to read 3, iclass 23, count 0 2006.285.15:30:30.48#ibcon#read 3, iclass 23, count 0 2006.285.15:30:30.48#ibcon#about to read 4, iclass 23, count 0 2006.285.15:30:30.48#ibcon#read 4, iclass 23, count 0 2006.285.15:30:30.48#ibcon#about to read 5, iclass 23, count 0 2006.285.15:30:30.48#ibcon#read 5, iclass 23, count 0 2006.285.15:30:30.48#ibcon#about to read 6, iclass 23, count 0 2006.285.15:30:30.48#ibcon#read 6, iclass 23, count 0 2006.285.15:30:30.48#ibcon#end of sib2, iclass 23, count 0 2006.285.15:30:30.48#ibcon#*after write, iclass 23, count 0 2006.285.15:30:30.48#ibcon#*before return 0, iclass 23, count 0 2006.285.15:30:30.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:30:30.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:30:30.48#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.15:30:30.48#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.15:30:30.48$vck44/vb=6,3 2006.285.15:30:30.48#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.15:30:30.48#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.15:30:30.48#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:30.48#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:30:30.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:30:30.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:30:30.54#ibcon#enter wrdev, iclass 25, count 2 2006.285.15:30:30.54#ibcon#first serial, iclass 25, count 2 2006.285.15:30:30.54#ibcon#enter sib2, iclass 25, count 2 2006.285.15:30:30.54#ibcon#flushed, iclass 25, count 2 2006.285.15:30:30.54#ibcon#about to write, iclass 25, count 2 2006.285.15:30:30.54#ibcon#wrote, iclass 25, count 2 2006.285.15:30:30.54#ibcon#about to read 3, iclass 25, count 2 2006.285.15:30:30.56#ibcon#read 3, iclass 25, count 2 2006.285.15:30:30.56#ibcon#about to read 4, iclass 25, count 2 2006.285.15:30:30.56#ibcon#read 4, iclass 25, count 2 2006.285.15:30:30.56#ibcon#about to read 5, iclass 25, count 2 2006.285.15:30:30.56#ibcon#read 5, iclass 25, count 2 2006.285.15:30:30.56#ibcon#about to read 6, iclass 25, count 2 2006.285.15:30:30.56#ibcon#read 6, iclass 25, count 2 2006.285.15:30:30.56#ibcon#end of sib2, iclass 25, count 2 2006.285.15:30:30.56#ibcon#*mode == 0, iclass 25, count 2 2006.285.15:30:30.56#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.15:30:30.56#ibcon#[27=AT06-03\r\n] 2006.285.15:30:30.56#ibcon#*before write, iclass 25, count 2 2006.285.15:30:30.56#ibcon#enter sib2, iclass 25, count 2 2006.285.15:30:30.56#ibcon#flushed, iclass 25, count 2 2006.285.15:30:30.56#ibcon#about to write, iclass 25, count 2 2006.285.15:30:30.56#ibcon#wrote, iclass 25, count 2 2006.285.15:30:30.56#ibcon#about to read 3, iclass 25, count 2 2006.285.15:30:30.59#ibcon#read 3, iclass 25, count 2 2006.285.15:30:30.59#ibcon#about to read 4, iclass 25, count 2 2006.285.15:30:30.59#ibcon#read 4, iclass 25, count 2 2006.285.15:30:30.59#ibcon#about to read 5, iclass 25, count 2 2006.285.15:30:30.59#ibcon#read 5, iclass 25, count 2 2006.285.15:30:30.59#ibcon#about to read 6, iclass 25, count 2 2006.285.15:30:30.59#ibcon#read 6, iclass 25, count 2 2006.285.15:30:30.59#ibcon#end of sib2, iclass 25, count 2 2006.285.15:30:30.59#ibcon#*after write, iclass 25, count 2 2006.285.15:30:30.59#ibcon#*before return 0, iclass 25, count 2 2006.285.15:30:30.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:30:30.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:30:30.59#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.15:30:30.59#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:30.59#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:30:30.71#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:30:30.71#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:30:30.71#ibcon#enter wrdev, iclass 25, count 0 2006.285.15:30:30.71#ibcon#first serial, iclass 25, count 0 2006.285.15:30:30.71#ibcon#enter sib2, iclass 25, count 0 2006.285.15:30:30.71#ibcon#flushed, iclass 25, count 0 2006.285.15:30:30.71#ibcon#about to write, iclass 25, count 0 2006.285.15:30:30.71#ibcon#wrote, iclass 25, count 0 2006.285.15:30:30.71#ibcon#about to read 3, iclass 25, count 0 2006.285.15:30:30.73#ibcon#read 3, iclass 25, count 0 2006.285.15:30:30.73#ibcon#about to read 4, iclass 25, count 0 2006.285.15:30:30.73#ibcon#read 4, iclass 25, count 0 2006.285.15:30:30.73#ibcon#about to read 5, iclass 25, count 0 2006.285.15:30:30.73#ibcon#read 5, iclass 25, count 0 2006.285.15:30:30.73#ibcon#about to read 6, iclass 25, count 0 2006.285.15:30:30.73#ibcon#read 6, iclass 25, count 0 2006.285.15:30:30.73#ibcon#end of sib2, iclass 25, count 0 2006.285.15:30:30.73#ibcon#*mode == 0, iclass 25, count 0 2006.285.15:30:30.73#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.15:30:30.73#ibcon#[27=USB\r\n] 2006.285.15:30:30.73#ibcon#*before write, iclass 25, count 0 2006.285.15:30:30.73#ibcon#enter sib2, iclass 25, count 0 2006.285.15:30:30.73#ibcon#flushed, iclass 25, count 0 2006.285.15:30:30.73#ibcon#about to write, iclass 25, count 0 2006.285.15:30:30.73#ibcon#wrote, iclass 25, count 0 2006.285.15:30:30.73#ibcon#about to read 3, iclass 25, count 0 2006.285.15:30:30.76#ibcon#read 3, iclass 25, count 0 2006.285.15:30:30.76#ibcon#about to read 4, iclass 25, count 0 2006.285.15:30:30.76#ibcon#read 4, iclass 25, count 0 2006.285.15:30:30.76#ibcon#about to read 5, iclass 25, count 0 2006.285.15:30:30.76#ibcon#read 5, iclass 25, count 0 2006.285.15:30:30.76#ibcon#about to read 6, iclass 25, count 0 2006.285.15:30:30.76#ibcon#read 6, iclass 25, count 0 2006.285.15:30:30.76#ibcon#end of sib2, iclass 25, count 0 2006.285.15:30:30.76#ibcon#*after write, iclass 25, count 0 2006.285.15:30:30.76#ibcon#*before return 0, iclass 25, count 0 2006.285.15:30:30.76#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:30:30.76#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:30:30.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.15:30:30.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.15:30:30.76$vck44/vblo=7,734.99 2006.285.15:30:30.76#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.15:30:30.76#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.15:30:30.76#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:30.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:30:30.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:30:30.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:30:30.76#ibcon#enter wrdev, iclass 27, count 0 2006.285.15:30:30.76#ibcon#first serial, iclass 27, count 0 2006.285.15:30:30.76#ibcon#enter sib2, iclass 27, count 0 2006.285.15:30:30.76#ibcon#flushed, iclass 27, count 0 2006.285.15:30:30.76#ibcon#about to write, iclass 27, count 0 2006.285.15:30:30.76#ibcon#wrote, iclass 27, count 0 2006.285.15:30:30.76#ibcon#about to read 3, iclass 27, count 0 2006.285.15:30:30.78#ibcon#read 3, iclass 27, count 0 2006.285.15:30:30.82#ibcon#about to read 4, iclass 27, count 0 2006.285.15:30:30.82#ibcon#read 4, iclass 27, count 0 2006.285.15:30:30.82#ibcon#about to read 5, iclass 27, count 0 2006.285.15:30:30.82#ibcon#read 5, iclass 27, count 0 2006.285.15:30:30.82#ibcon#about to read 6, iclass 27, count 0 2006.285.15:30:30.82#ibcon#read 6, iclass 27, count 0 2006.285.15:30:30.82#ibcon#end of sib2, iclass 27, count 0 2006.285.15:30:30.82#ibcon#*mode == 0, iclass 27, count 0 2006.285.15:30:30.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.15:30:30.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.15:30:30.82#ibcon#*before write, iclass 27, count 0 2006.285.15:30:30.82#ibcon#enter sib2, iclass 27, count 0 2006.285.15:30:30.82#ibcon#flushed, iclass 27, count 0 2006.285.15:30:30.82#ibcon#about to write, iclass 27, count 0 2006.285.15:30:30.82#ibcon#wrote, iclass 27, count 0 2006.285.15:30:30.82#ibcon#about to read 3, iclass 27, count 0 2006.285.15:30:30.85#ibcon#read 3, iclass 27, count 0 2006.285.15:30:30.85#ibcon#about to read 4, iclass 27, count 0 2006.285.15:30:30.85#ibcon#read 4, iclass 27, count 0 2006.285.15:30:30.85#ibcon#about to read 5, iclass 27, count 0 2006.285.15:30:30.85#ibcon#read 5, iclass 27, count 0 2006.285.15:30:30.85#ibcon#about to read 6, iclass 27, count 0 2006.285.15:30:30.85#ibcon#read 6, iclass 27, count 0 2006.285.15:30:30.85#ibcon#end of sib2, iclass 27, count 0 2006.285.15:30:30.85#ibcon#*after write, iclass 27, count 0 2006.285.15:30:30.85#ibcon#*before return 0, iclass 27, count 0 2006.285.15:30:30.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:30:30.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:30:30.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.15:30:30.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.15:30:30.85$vck44/vb=7,4 2006.285.15:30:30.85#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.15:30:30.85#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.15:30:30.85#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:30.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:30:30.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:30:30.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:30:30.88#ibcon#enter wrdev, iclass 29, count 2 2006.285.15:30:30.88#ibcon#first serial, iclass 29, count 2 2006.285.15:30:30.88#ibcon#enter sib2, iclass 29, count 2 2006.285.15:30:30.88#ibcon#flushed, iclass 29, count 2 2006.285.15:30:30.88#ibcon#about to write, iclass 29, count 2 2006.285.15:30:30.88#ibcon#wrote, iclass 29, count 2 2006.285.15:30:30.88#ibcon#about to read 3, iclass 29, count 2 2006.285.15:30:30.90#ibcon#read 3, iclass 29, count 2 2006.285.15:30:30.90#ibcon#about to read 4, iclass 29, count 2 2006.285.15:30:30.90#ibcon#read 4, iclass 29, count 2 2006.285.15:30:30.90#ibcon#about to read 5, iclass 29, count 2 2006.285.15:30:30.90#ibcon#read 5, iclass 29, count 2 2006.285.15:30:30.90#ibcon#about to read 6, iclass 29, count 2 2006.285.15:30:30.90#ibcon#read 6, iclass 29, count 2 2006.285.15:30:30.90#ibcon#end of sib2, iclass 29, count 2 2006.285.15:30:30.90#ibcon#*mode == 0, iclass 29, count 2 2006.285.15:30:30.90#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.15:30:30.90#ibcon#[27=AT07-04\r\n] 2006.285.15:30:30.90#ibcon#*before write, iclass 29, count 2 2006.285.15:30:30.90#ibcon#enter sib2, iclass 29, count 2 2006.285.15:30:30.90#ibcon#flushed, iclass 29, count 2 2006.285.15:30:30.90#ibcon#about to write, iclass 29, count 2 2006.285.15:30:30.90#ibcon#wrote, iclass 29, count 2 2006.285.15:30:30.90#ibcon#about to read 3, iclass 29, count 2 2006.285.15:30:30.93#ibcon#read 3, iclass 29, count 2 2006.285.15:30:30.93#ibcon#about to read 4, iclass 29, count 2 2006.285.15:30:30.93#ibcon#read 4, iclass 29, count 2 2006.285.15:30:30.93#ibcon#about to read 5, iclass 29, count 2 2006.285.15:30:30.93#ibcon#read 5, iclass 29, count 2 2006.285.15:30:30.93#ibcon#about to read 6, iclass 29, count 2 2006.285.15:30:30.93#ibcon#read 6, iclass 29, count 2 2006.285.15:30:30.93#ibcon#end of sib2, iclass 29, count 2 2006.285.15:30:30.93#ibcon#*after write, iclass 29, count 2 2006.285.15:30:30.93#ibcon#*before return 0, iclass 29, count 2 2006.285.15:30:30.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:30:30.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:30:30.93#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.15:30:30.93#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:30.93#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:30:31.05#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:30:31.05#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:30:31.05#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:30:31.05#ibcon#first serial, iclass 29, count 0 2006.285.15:30:31.05#ibcon#enter sib2, iclass 29, count 0 2006.285.15:30:31.05#ibcon#flushed, iclass 29, count 0 2006.285.15:30:31.05#ibcon#about to write, iclass 29, count 0 2006.285.15:30:31.05#ibcon#wrote, iclass 29, count 0 2006.285.15:30:31.05#ibcon#about to read 3, iclass 29, count 0 2006.285.15:30:31.07#ibcon#read 3, iclass 29, count 0 2006.285.15:30:31.07#ibcon#about to read 4, iclass 29, count 0 2006.285.15:30:31.07#ibcon#read 4, iclass 29, count 0 2006.285.15:30:31.07#ibcon#about to read 5, iclass 29, count 0 2006.285.15:30:31.07#ibcon#read 5, iclass 29, count 0 2006.285.15:30:31.07#ibcon#about to read 6, iclass 29, count 0 2006.285.15:30:31.07#ibcon#read 6, iclass 29, count 0 2006.285.15:30:31.07#ibcon#end of sib2, iclass 29, count 0 2006.285.15:30:31.07#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:30:31.07#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:30:31.07#ibcon#[27=USB\r\n] 2006.285.15:30:31.07#ibcon#*before write, iclass 29, count 0 2006.285.15:30:31.07#ibcon#enter sib2, iclass 29, count 0 2006.285.15:30:31.07#ibcon#flushed, iclass 29, count 0 2006.285.15:30:31.07#ibcon#about to write, iclass 29, count 0 2006.285.15:30:31.07#ibcon#wrote, iclass 29, count 0 2006.285.15:30:31.07#ibcon#about to read 3, iclass 29, count 0 2006.285.15:30:31.10#ibcon#read 3, iclass 29, count 0 2006.285.15:30:31.10#ibcon#about to read 4, iclass 29, count 0 2006.285.15:30:31.10#ibcon#read 4, iclass 29, count 0 2006.285.15:30:31.10#ibcon#about to read 5, iclass 29, count 0 2006.285.15:30:31.10#ibcon#read 5, iclass 29, count 0 2006.285.15:30:31.10#ibcon#about to read 6, iclass 29, count 0 2006.285.15:30:31.10#ibcon#read 6, iclass 29, count 0 2006.285.15:30:31.10#ibcon#end of sib2, iclass 29, count 0 2006.285.15:30:31.10#ibcon#*after write, iclass 29, count 0 2006.285.15:30:31.10#ibcon#*before return 0, iclass 29, count 0 2006.285.15:30:31.10#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:30:31.10#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:30:31.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:30:31.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:30:31.10$vck44/vblo=8,744.99 2006.285.15:30:31.10#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.15:30:31.10#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.15:30:31.10#ibcon#ireg 17 cls_cnt 0 2006.285.15:30:31.10#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:30:31.10#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:30:31.10#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:30:31.10#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:30:31.10#ibcon#first serial, iclass 31, count 0 2006.285.15:30:31.10#ibcon#enter sib2, iclass 31, count 0 2006.285.15:30:31.10#ibcon#flushed, iclass 31, count 0 2006.285.15:30:31.10#ibcon#about to write, iclass 31, count 0 2006.285.15:30:31.10#ibcon#wrote, iclass 31, count 0 2006.285.15:30:31.10#ibcon#about to read 3, iclass 31, count 0 2006.285.15:30:31.12#ibcon#read 3, iclass 31, count 0 2006.285.15:30:31.12#ibcon#about to read 4, iclass 31, count 0 2006.285.15:30:31.12#ibcon#read 4, iclass 31, count 0 2006.285.15:30:31.12#ibcon#about to read 5, iclass 31, count 0 2006.285.15:30:31.12#ibcon#read 5, iclass 31, count 0 2006.285.15:30:31.12#ibcon#about to read 6, iclass 31, count 0 2006.285.15:30:31.12#ibcon#read 6, iclass 31, count 0 2006.285.15:30:31.12#ibcon#end of sib2, iclass 31, count 0 2006.285.15:30:31.12#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:30:31.12#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:30:31.12#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.15:30:31.12#ibcon#*before write, iclass 31, count 0 2006.285.15:30:31.12#ibcon#enter sib2, iclass 31, count 0 2006.285.15:30:31.12#ibcon#flushed, iclass 31, count 0 2006.285.15:30:31.12#ibcon#about to write, iclass 31, count 0 2006.285.15:30:31.12#ibcon#wrote, iclass 31, count 0 2006.285.15:30:31.12#ibcon#about to read 3, iclass 31, count 0 2006.285.15:30:31.16#ibcon#read 3, iclass 31, count 0 2006.285.15:30:31.16#ibcon#about to read 4, iclass 31, count 0 2006.285.15:30:31.16#ibcon#read 4, iclass 31, count 0 2006.285.15:30:31.16#ibcon#about to read 5, iclass 31, count 0 2006.285.15:30:31.16#ibcon#read 5, iclass 31, count 0 2006.285.15:30:31.16#ibcon#about to read 6, iclass 31, count 0 2006.285.15:30:31.16#ibcon#read 6, iclass 31, count 0 2006.285.15:30:31.16#ibcon#end of sib2, iclass 31, count 0 2006.285.15:30:31.16#ibcon#*after write, iclass 31, count 0 2006.285.15:30:31.16#ibcon#*before return 0, iclass 31, count 0 2006.285.15:30:31.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:30:31.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:30:31.16#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:30:31.16#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:30:31.16$vck44/vb=8,4 2006.285.15:30:31.16#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.15:30:31.16#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.15:30:31.16#ibcon#ireg 11 cls_cnt 2 2006.285.15:30:31.16#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:30:31.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:30:31.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:30:31.22#ibcon#enter wrdev, iclass 33, count 2 2006.285.15:30:31.22#ibcon#first serial, iclass 33, count 2 2006.285.15:30:31.22#ibcon#enter sib2, iclass 33, count 2 2006.285.15:30:31.22#ibcon#flushed, iclass 33, count 2 2006.285.15:30:31.22#ibcon#about to write, iclass 33, count 2 2006.285.15:30:31.22#ibcon#wrote, iclass 33, count 2 2006.285.15:30:31.22#ibcon#about to read 3, iclass 33, count 2 2006.285.15:30:31.24#ibcon#read 3, iclass 33, count 2 2006.285.15:30:31.24#ibcon#about to read 4, iclass 33, count 2 2006.285.15:30:31.24#ibcon#read 4, iclass 33, count 2 2006.285.15:30:31.24#ibcon#about to read 5, iclass 33, count 2 2006.285.15:30:31.24#ibcon#read 5, iclass 33, count 2 2006.285.15:30:31.24#ibcon#about to read 6, iclass 33, count 2 2006.285.15:30:31.24#ibcon#read 6, iclass 33, count 2 2006.285.15:30:31.24#ibcon#end of sib2, iclass 33, count 2 2006.285.15:30:31.24#ibcon#*mode == 0, iclass 33, count 2 2006.285.15:30:31.24#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.15:30:31.24#ibcon#[27=AT08-04\r\n] 2006.285.15:30:31.24#ibcon#*before write, iclass 33, count 2 2006.285.15:30:31.24#ibcon#enter sib2, iclass 33, count 2 2006.285.15:30:31.24#ibcon#flushed, iclass 33, count 2 2006.285.15:30:31.24#ibcon#about to write, iclass 33, count 2 2006.285.15:30:31.24#ibcon#wrote, iclass 33, count 2 2006.285.15:30:31.24#ibcon#about to read 3, iclass 33, count 2 2006.285.15:30:31.27#ibcon#read 3, iclass 33, count 2 2006.285.15:30:31.27#ibcon#about to read 4, iclass 33, count 2 2006.285.15:30:31.27#ibcon#read 4, iclass 33, count 2 2006.285.15:30:31.27#ibcon#about to read 5, iclass 33, count 2 2006.285.15:30:31.27#ibcon#read 5, iclass 33, count 2 2006.285.15:30:31.27#ibcon#about to read 6, iclass 33, count 2 2006.285.15:30:31.27#ibcon#read 6, iclass 33, count 2 2006.285.15:30:31.27#ibcon#end of sib2, iclass 33, count 2 2006.285.15:30:31.27#ibcon#*after write, iclass 33, count 2 2006.285.15:30:31.27#ibcon#*before return 0, iclass 33, count 2 2006.285.15:30:31.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:30:31.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:30:31.27#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.15:30:31.27#ibcon#ireg 7 cls_cnt 0 2006.285.15:30:31.27#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:30:31.39#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:30:31.39#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:30:31.39#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:30:31.39#ibcon#first serial, iclass 33, count 0 2006.285.15:30:31.39#ibcon#enter sib2, iclass 33, count 0 2006.285.15:30:31.39#ibcon#flushed, iclass 33, count 0 2006.285.15:30:31.39#ibcon#about to write, iclass 33, count 0 2006.285.15:30:31.39#ibcon#wrote, iclass 33, count 0 2006.285.15:30:31.39#ibcon#about to read 3, iclass 33, count 0 2006.285.15:30:31.41#ibcon#read 3, iclass 33, count 0 2006.285.15:30:31.41#ibcon#about to read 4, iclass 33, count 0 2006.285.15:30:31.41#ibcon#read 4, iclass 33, count 0 2006.285.15:30:31.41#ibcon#about to read 5, iclass 33, count 0 2006.285.15:30:31.41#ibcon#read 5, iclass 33, count 0 2006.285.15:30:31.41#ibcon#about to read 6, iclass 33, count 0 2006.285.15:30:31.41#ibcon#read 6, iclass 33, count 0 2006.285.15:30:31.41#ibcon#end of sib2, iclass 33, count 0 2006.285.15:30:31.41#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:30:31.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:30:31.41#ibcon#[27=USB\r\n] 2006.285.15:30:31.41#ibcon#*before write, iclass 33, count 0 2006.285.15:30:31.41#ibcon#enter sib2, iclass 33, count 0 2006.285.15:30:31.41#ibcon#flushed, iclass 33, count 0 2006.285.15:30:31.41#ibcon#about to write, iclass 33, count 0 2006.285.15:30:31.41#ibcon#wrote, iclass 33, count 0 2006.285.15:30:31.41#ibcon#about to read 3, iclass 33, count 0 2006.285.15:30:31.44#ibcon#read 3, iclass 33, count 0 2006.285.15:30:31.44#ibcon#about to read 4, iclass 33, count 0 2006.285.15:30:31.44#ibcon#read 4, iclass 33, count 0 2006.285.15:30:31.44#ibcon#about to read 5, iclass 33, count 0 2006.285.15:30:31.44#ibcon#read 5, iclass 33, count 0 2006.285.15:30:31.44#ibcon#about to read 6, iclass 33, count 0 2006.285.15:30:31.44#ibcon#read 6, iclass 33, count 0 2006.285.15:30:31.44#ibcon#end of sib2, iclass 33, count 0 2006.285.15:30:31.44#ibcon#*after write, iclass 33, count 0 2006.285.15:30:31.44#ibcon#*before return 0, iclass 33, count 0 2006.285.15:30:31.44#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:30:31.44#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:30:31.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:30:31.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:30:31.44$vck44/vabw=wide 2006.285.15:30:31.44#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.15:30:31.44#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.15:30:31.44#ibcon#ireg 8 cls_cnt 0 2006.285.15:30:31.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:30:31.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:30:31.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:30:31.44#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:30:31.44#ibcon#first serial, iclass 35, count 0 2006.285.15:30:31.44#ibcon#enter sib2, iclass 35, count 0 2006.285.15:30:31.44#ibcon#flushed, iclass 35, count 0 2006.285.15:30:31.44#ibcon#about to write, iclass 35, count 0 2006.285.15:30:31.44#ibcon#wrote, iclass 35, count 0 2006.285.15:30:31.44#ibcon#about to read 3, iclass 35, count 0 2006.285.15:30:31.46#ibcon#read 3, iclass 35, count 0 2006.285.15:30:31.46#ibcon#about to read 4, iclass 35, count 0 2006.285.15:30:31.46#ibcon#read 4, iclass 35, count 0 2006.285.15:30:31.46#ibcon#about to read 5, iclass 35, count 0 2006.285.15:30:31.46#ibcon#read 5, iclass 35, count 0 2006.285.15:30:31.46#ibcon#about to read 6, iclass 35, count 0 2006.285.15:30:31.46#ibcon#read 6, iclass 35, count 0 2006.285.15:30:31.46#ibcon#end of sib2, iclass 35, count 0 2006.285.15:30:31.46#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:30:31.46#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:30:31.46#ibcon#[25=BW32\r\n] 2006.285.15:30:31.46#ibcon#*before write, iclass 35, count 0 2006.285.15:30:31.46#ibcon#enter sib2, iclass 35, count 0 2006.285.15:30:31.46#ibcon#flushed, iclass 35, count 0 2006.285.15:30:31.46#ibcon#about to write, iclass 35, count 0 2006.285.15:30:31.46#ibcon#wrote, iclass 35, count 0 2006.285.15:30:31.46#ibcon#about to read 3, iclass 35, count 0 2006.285.15:30:31.49#ibcon#read 3, iclass 35, count 0 2006.285.15:30:31.49#ibcon#about to read 4, iclass 35, count 0 2006.285.15:30:31.49#ibcon#read 4, iclass 35, count 0 2006.285.15:30:31.49#ibcon#about to read 5, iclass 35, count 0 2006.285.15:30:31.49#ibcon#read 5, iclass 35, count 0 2006.285.15:30:31.49#ibcon#about to read 6, iclass 35, count 0 2006.285.15:30:31.49#ibcon#read 6, iclass 35, count 0 2006.285.15:30:31.49#ibcon#end of sib2, iclass 35, count 0 2006.285.15:30:31.49#ibcon#*after write, iclass 35, count 0 2006.285.15:30:31.49#ibcon#*before return 0, iclass 35, count 0 2006.285.15:30:31.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:30:31.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:30:31.49#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:30:31.49#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:30:31.49$vck44/vbbw=wide 2006.285.15:30:31.49#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.15:30:31.49#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.15:30:31.49#ibcon#ireg 8 cls_cnt 0 2006.285.15:30:31.49#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:30:31.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:30:31.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:30:31.56#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:30:31.56#ibcon#first serial, iclass 37, count 0 2006.285.15:30:31.56#ibcon#enter sib2, iclass 37, count 0 2006.285.15:30:31.56#ibcon#flushed, iclass 37, count 0 2006.285.15:30:31.56#ibcon#about to write, iclass 37, count 0 2006.285.15:30:31.56#ibcon#wrote, iclass 37, count 0 2006.285.15:30:31.56#ibcon#about to read 3, iclass 37, count 0 2006.285.15:30:31.58#ibcon#read 3, iclass 37, count 0 2006.285.15:30:31.58#ibcon#about to read 4, iclass 37, count 0 2006.285.15:30:31.58#ibcon#read 4, iclass 37, count 0 2006.285.15:30:31.58#ibcon#about to read 5, iclass 37, count 0 2006.285.15:30:31.58#ibcon#read 5, iclass 37, count 0 2006.285.15:30:31.58#ibcon#about to read 6, iclass 37, count 0 2006.285.15:30:31.58#ibcon#read 6, iclass 37, count 0 2006.285.15:30:31.58#ibcon#end of sib2, iclass 37, count 0 2006.285.15:30:31.58#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:30:31.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:30:31.58#ibcon#[27=BW32\r\n] 2006.285.15:30:31.58#ibcon#*before write, iclass 37, count 0 2006.285.15:30:31.58#ibcon#enter sib2, iclass 37, count 0 2006.285.15:30:31.58#ibcon#flushed, iclass 37, count 0 2006.285.15:30:31.58#ibcon#about to write, iclass 37, count 0 2006.285.15:30:31.58#ibcon#wrote, iclass 37, count 0 2006.285.15:30:31.58#ibcon#about to read 3, iclass 37, count 0 2006.285.15:30:31.61#ibcon#read 3, iclass 37, count 0 2006.285.15:30:31.61#ibcon#about to read 4, iclass 37, count 0 2006.285.15:30:31.61#ibcon#read 4, iclass 37, count 0 2006.285.15:30:31.61#ibcon#about to read 5, iclass 37, count 0 2006.285.15:30:31.61#ibcon#read 5, iclass 37, count 0 2006.285.15:30:31.61#ibcon#about to read 6, iclass 37, count 0 2006.285.15:30:31.61#ibcon#read 6, iclass 37, count 0 2006.285.15:30:31.61#ibcon#end of sib2, iclass 37, count 0 2006.285.15:30:31.61#ibcon#*after write, iclass 37, count 0 2006.285.15:30:31.61#ibcon#*before return 0, iclass 37, count 0 2006.285.15:30:31.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:30:31.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:30:31.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:30:31.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:30:31.61$setupk4/ifdk4 2006.285.15:30:31.61$ifdk4/lo= 2006.285.15:30:31.61$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.15:30:31.61$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.15:30:31.61$ifdk4/patch= 2006.285.15:30:31.61$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.15:30:31.62$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.15:30:31.62$setupk4/!*+20s 2006.285.15:30:34.14#trakl#Source acquired 2006.285.15:30:34.97#abcon#<5=/02 1.1 3.5 19.05 921014.9\r\n> 2006.285.15:30:34.99#abcon#{5=INTERFACE CLEAR} 2006.285.15:30:35.05#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:30:36.14#flagr#flagr/antenna,acquired 2006.285.15:30:44.71$setupk4/"tpicd 2006.285.15:30:44.71$setupk4/echo=off 2006.285.15:30:44.71$setupk4/xlog=off 2006.285.15:30:44.71:!2006.285.15:31:29 2006.285.15:31:29.00:preob 2006.285.15:31:29.14/onsource/TRACKING 2006.285.15:31:29.14:!2006.285.15:31:39 2006.285.15:31:39.00:"tape 2006.285.15:31:39.00:"st=record 2006.285.15:31:39.00:data_valid=on 2006.285.15:31:39.00:midob 2006.285.15:31:39.14/onsource/TRACKING 2006.285.15:31:39.14/wx/19.04,1014.9,92 2006.285.15:31:39.31/cable/+6.5012E-03 2006.285.15:31:40.40/va/01,07,usb,yes,34,36 2006.285.15:31:40.40/va/02,06,usb,yes,34,34 2006.285.15:31:40.40/va/03,07,usb,yes,33,35 2006.285.15:31:40.40/va/04,06,usb,yes,35,36 2006.285.15:31:40.40/va/05,03,usb,yes,34,35 2006.285.15:31:40.40/va/06,04,usb,yes,31,30 2006.285.15:31:40.40/va/07,04,usb,yes,32,32 2006.285.15:31:40.40/va/08,03,usb,yes,32,39 2006.285.15:31:40.63/valo/01,524.99,yes,locked 2006.285.15:31:40.63/valo/02,534.99,yes,locked 2006.285.15:31:40.63/valo/03,564.99,yes,locked 2006.285.15:31:40.63/valo/04,624.99,yes,locked 2006.285.15:31:40.63/valo/05,734.99,yes,locked 2006.285.15:31:40.63/valo/06,814.99,yes,locked 2006.285.15:31:40.63/valo/07,864.99,yes,locked 2006.285.15:31:40.63/valo/08,884.99,yes,locked 2006.285.15:31:41.72/vb/01,04,usb,yes,31,29 2006.285.15:31:41.72/vb/02,05,usb,yes,29,29 2006.285.15:31:41.72/vb/03,04,usb,yes,30,33 2006.285.15:31:41.72/vb/04,05,usb,yes,31,29 2006.285.15:31:41.72/vb/05,04,usb,yes,27,29 2006.285.15:31:41.72/vb/06,03,usb,yes,39,34 2006.285.15:31:41.72/vb/07,04,usb,yes,31,31 2006.285.15:31:41.72/vb/08,04,usb,yes,28,32 2006.285.15:31:41.96/vblo/01,629.99,yes,locked 2006.285.15:31:41.96/vblo/02,634.99,yes,locked 2006.285.15:31:41.96/vblo/03,649.99,yes,locked 2006.285.15:31:41.96/vblo/04,679.99,yes,locked 2006.285.15:31:41.96/vblo/05,709.99,yes,locked 2006.285.15:31:41.96/vblo/06,719.99,yes,locked 2006.285.15:31:41.96/vblo/07,734.99,yes,locked 2006.285.15:31:41.96/vblo/08,744.99,yes,locked 2006.285.15:31:42.11/vabw/8 2006.285.15:31:42.26/vbbw/8 2006.285.15:31:42.35/xfe/off,on,12.2 2006.285.15:31:42.73/ifatt/23,28,28,28 2006.285.15:31:43.07/fmout-gps/S +2.76E-07 2006.285.15:31:43.09:!2006.285.15:34:49 2006.285.15:34:49.00:data_valid=off 2006.285.15:34:49.00:"et 2006.285.15:34:49.00:!+3s 2006.285.15:34:52.01:"tape 2006.285.15:34:52.01:postob 2006.285.15:34:52.20/cable/+6.5007E-03 2006.285.15:34:52.20/wx/19.01,1014.9,92 2006.285.15:34:53.08/fmout-gps/S +2.69E-07 2006.285.15:34:53.08:scan_name=285-1537,jd0610,100 2006.285.15:34:53.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.285.15:34:54.14#flagr#flagr/antenna,new-source 2006.285.15:34:54.14:checkk5 2006.285.15:34:54.59/chk_autoobs//k5ts1/ autoobs is running! 2006.285.15:34:54.98/chk_autoobs//k5ts2/ autoobs is running! 2006.285.15:34:55.46/chk_autoobs//k5ts3/ autoobs is running! 2006.285.15:34:55.84/chk_autoobs//k5ts4/ autoobs is running! 2006.285.15:34:56.46/chk_obsdata//k5ts1/T2851531??a.dat file size is correct (nominal:760MB, actual:760MB). 2006.285.15:34:56.82/chk_obsdata//k5ts2/T2851531??b.dat file size is correct (nominal:760MB, actual:760MB). 2006.285.15:34:57.20/chk_obsdata//k5ts3/T2851531??c.dat file size is correct (nominal:760MB, actual:760MB). 2006.285.15:34:57.95/chk_obsdata//k5ts4/T2851531??d.dat file size is correct (nominal:760MB, actual:760MB). 2006.285.15:34:58.74/k5log//k5ts1_log_newline 2006.285.15:34:59.71/k5log//k5ts2_log_newline 2006.285.15:35:00.74/k5log//k5ts3_log_newline 2006.285.15:35:01.52/k5log//k5ts4_log_newline 2006.285.15:35:01.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.15:35:01.54:setupk4=1 2006.285.15:35:01.54$setupk4/echo=on 2006.285.15:35:01.54$setupk4/pcalon 2006.285.15:35:01.54$pcalon/"no phase cal control is implemented here 2006.285.15:35:01.54$setupk4/"tpicd=stop 2006.285.15:35:01.54$setupk4/"rec=synch_on 2006.285.15:35:01.54$setupk4/"rec_mode=128 2006.285.15:35:01.54$setupk4/!* 2006.285.15:35:01.54$setupk4/recpk4 2006.285.15:35:01.54$recpk4/recpatch= 2006.285.15:35:01.54$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.15:35:01.54$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.15:35:01.54$setupk4/vck44 2006.285.15:35:01.54$vck44/valo=1,524.99 2006.285.15:35:01.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.15:35:01.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.15:35:01.54#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:01.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:35:01.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:35:01.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:35:01.54#ibcon#enter wrdev, iclass 4, count 0 2006.285.15:35:01.54#ibcon#first serial, iclass 4, count 0 2006.285.15:35:01.54#ibcon#enter sib2, iclass 4, count 0 2006.285.15:35:01.54#ibcon#flushed, iclass 4, count 0 2006.285.15:35:01.54#ibcon#about to write, iclass 4, count 0 2006.285.15:35:01.54#ibcon#wrote, iclass 4, count 0 2006.285.15:35:01.54#ibcon#about to read 3, iclass 4, count 0 2006.285.15:35:01.56#ibcon#read 3, iclass 4, count 0 2006.285.15:35:01.56#ibcon#about to read 4, iclass 4, count 0 2006.285.15:35:01.56#ibcon#read 4, iclass 4, count 0 2006.285.15:35:01.56#ibcon#about to read 5, iclass 4, count 0 2006.285.15:35:01.56#ibcon#read 5, iclass 4, count 0 2006.285.15:35:01.56#ibcon#about to read 6, iclass 4, count 0 2006.285.15:35:01.56#ibcon#read 6, iclass 4, count 0 2006.285.15:35:01.56#ibcon#end of sib2, iclass 4, count 0 2006.285.15:35:01.56#ibcon#*mode == 0, iclass 4, count 0 2006.285.15:35:01.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.15:35:01.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.15:35:01.56#ibcon#*before write, iclass 4, count 0 2006.285.15:35:01.56#ibcon#enter sib2, iclass 4, count 0 2006.285.15:35:01.56#ibcon#flushed, iclass 4, count 0 2006.285.15:35:01.56#ibcon#about to write, iclass 4, count 0 2006.285.15:35:01.56#ibcon#wrote, iclass 4, count 0 2006.285.15:35:01.56#ibcon#about to read 3, iclass 4, count 0 2006.285.15:35:01.61#ibcon#read 3, iclass 4, count 0 2006.285.15:35:01.61#ibcon#about to read 4, iclass 4, count 0 2006.285.15:35:01.61#ibcon#read 4, iclass 4, count 0 2006.285.15:35:01.61#ibcon#about to read 5, iclass 4, count 0 2006.285.15:35:01.61#ibcon#read 5, iclass 4, count 0 2006.285.15:35:01.61#ibcon#about to read 6, iclass 4, count 0 2006.285.15:35:01.61#ibcon#read 6, iclass 4, count 0 2006.285.15:35:01.61#ibcon#end of sib2, iclass 4, count 0 2006.285.15:35:01.61#ibcon#*after write, iclass 4, count 0 2006.285.15:35:01.61#ibcon#*before return 0, iclass 4, count 0 2006.285.15:35:01.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:35:01.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:35:01.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.15:35:01.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.15:35:01.61$vck44/va=1,7 2006.285.15:35:01.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.15:35:01.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.15:35:01.61#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:01.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:35:01.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:35:01.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:35:01.61#ibcon#enter wrdev, iclass 6, count 2 2006.285.15:35:01.61#ibcon#first serial, iclass 6, count 2 2006.285.15:35:01.61#ibcon#enter sib2, iclass 6, count 2 2006.285.15:35:01.61#ibcon#flushed, iclass 6, count 2 2006.285.15:35:01.61#ibcon#about to write, iclass 6, count 2 2006.285.15:35:01.61#ibcon#wrote, iclass 6, count 2 2006.285.15:35:01.61#ibcon#about to read 3, iclass 6, count 2 2006.285.15:35:01.63#ibcon#read 3, iclass 6, count 2 2006.285.15:35:01.63#ibcon#about to read 4, iclass 6, count 2 2006.285.15:35:01.63#ibcon#read 4, iclass 6, count 2 2006.285.15:35:01.63#ibcon#about to read 5, iclass 6, count 2 2006.285.15:35:01.63#ibcon#read 5, iclass 6, count 2 2006.285.15:35:01.63#ibcon#about to read 6, iclass 6, count 2 2006.285.15:35:01.63#ibcon#read 6, iclass 6, count 2 2006.285.15:35:01.63#ibcon#end of sib2, iclass 6, count 2 2006.285.15:35:01.63#ibcon#*mode == 0, iclass 6, count 2 2006.285.15:35:01.63#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.15:35:01.63#ibcon#[25=AT01-07\r\n] 2006.285.15:35:01.63#ibcon#*before write, iclass 6, count 2 2006.285.15:35:01.63#ibcon#enter sib2, iclass 6, count 2 2006.285.15:35:01.63#ibcon#flushed, iclass 6, count 2 2006.285.15:35:01.63#ibcon#about to write, iclass 6, count 2 2006.285.15:35:01.63#ibcon#wrote, iclass 6, count 2 2006.285.15:35:01.63#ibcon#about to read 3, iclass 6, count 2 2006.285.15:35:01.66#ibcon#read 3, iclass 6, count 2 2006.285.15:35:01.66#ibcon#about to read 4, iclass 6, count 2 2006.285.15:35:01.66#ibcon#read 4, iclass 6, count 2 2006.285.15:35:01.66#ibcon#about to read 5, iclass 6, count 2 2006.285.15:35:01.66#ibcon#read 5, iclass 6, count 2 2006.285.15:35:01.66#ibcon#about to read 6, iclass 6, count 2 2006.285.15:35:01.66#ibcon#read 6, iclass 6, count 2 2006.285.15:35:01.66#ibcon#end of sib2, iclass 6, count 2 2006.285.15:35:01.66#ibcon#*after write, iclass 6, count 2 2006.285.15:35:01.66#ibcon#*before return 0, iclass 6, count 2 2006.285.15:35:01.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:35:01.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:35:01.66#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.15:35:01.66#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:01.66#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:35:01.78#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:35:01.78#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:35:01.78#ibcon#enter wrdev, iclass 6, count 0 2006.285.15:35:01.78#ibcon#first serial, iclass 6, count 0 2006.285.15:35:01.78#ibcon#enter sib2, iclass 6, count 0 2006.285.15:35:01.78#ibcon#flushed, iclass 6, count 0 2006.285.15:35:01.78#ibcon#about to write, iclass 6, count 0 2006.285.15:35:01.78#ibcon#wrote, iclass 6, count 0 2006.285.15:35:01.78#ibcon#about to read 3, iclass 6, count 0 2006.285.15:35:01.80#ibcon#read 3, iclass 6, count 0 2006.285.15:35:01.80#ibcon#about to read 4, iclass 6, count 0 2006.285.15:35:01.80#ibcon#read 4, iclass 6, count 0 2006.285.15:35:01.80#ibcon#about to read 5, iclass 6, count 0 2006.285.15:35:01.80#ibcon#read 5, iclass 6, count 0 2006.285.15:35:01.80#ibcon#about to read 6, iclass 6, count 0 2006.285.15:35:01.80#ibcon#read 6, iclass 6, count 0 2006.285.15:35:01.80#ibcon#end of sib2, iclass 6, count 0 2006.285.15:35:01.80#ibcon#*mode == 0, iclass 6, count 0 2006.285.15:35:01.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.15:35:01.80#ibcon#[25=USB\r\n] 2006.285.15:35:01.80#ibcon#*before write, iclass 6, count 0 2006.285.15:35:01.80#ibcon#enter sib2, iclass 6, count 0 2006.285.15:35:01.80#ibcon#flushed, iclass 6, count 0 2006.285.15:35:01.80#ibcon#about to write, iclass 6, count 0 2006.285.15:35:01.80#ibcon#wrote, iclass 6, count 0 2006.285.15:35:01.80#ibcon#about to read 3, iclass 6, count 0 2006.285.15:35:01.83#ibcon#read 3, iclass 6, count 0 2006.285.15:35:01.83#ibcon#about to read 4, iclass 6, count 0 2006.285.15:35:01.83#ibcon#read 4, iclass 6, count 0 2006.285.15:35:01.83#ibcon#about to read 5, iclass 6, count 0 2006.285.15:35:01.83#ibcon#read 5, iclass 6, count 0 2006.285.15:35:01.83#ibcon#about to read 6, iclass 6, count 0 2006.285.15:35:01.83#ibcon#read 6, iclass 6, count 0 2006.285.15:35:01.83#ibcon#end of sib2, iclass 6, count 0 2006.285.15:35:01.83#ibcon#*after write, iclass 6, count 0 2006.285.15:35:01.83#ibcon#*before return 0, iclass 6, count 0 2006.285.15:35:01.83#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:35:01.83#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:35:01.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.15:35:01.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.15:35:01.83$vck44/valo=2,534.99 2006.285.15:35:01.83#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.15:35:01.83#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.15:35:01.83#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:01.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:35:01.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:35:01.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:35:01.83#ibcon#enter wrdev, iclass 10, count 0 2006.285.15:35:01.83#ibcon#first serial, iclass 10, count 0 2006.285.15:35:01.83#ibcon#enter sib2, iclass 10, count 0 2006.285.15:35:01.83#ibcon#flushed, iclass 10, count 0 2006.285.15:35:01.83#ibcon#about to write, iclass 10, count 0 2006.285.15:35:01.83#ibcon#wrote, iclass 10, count 0 2006.285.15:35:01.83#ibcon#about to read 3, iclass 10, count 0 2006.285.15:35:01.85#ibcon#read 3, iclass 10, count 0 2006.285.15:35:01.85#ibcon#about to read 4, iclass 10, count 0 2006.285.15:35:01.85#ibcon#read 4, iclass 10, count 0 2006.285.15:35:01.85#ibcon#about to read 5, iclass 10, count 0 2006.285.15:35:01.85#ibcon#read 5, iclass 10, count 0 2006.285.15:35:01.85#ibcon#about to read 6, iclass 10, count 0 2006.285.15:35:01.85#ibcon#read 6, iclass 10, count 0 2006.285.15:35:01.85#ibcon#end of sib2, iclass 10, count 0 2006.285.15:35:01.85#ibcon#*mode == 0, iclass 10, count 0 2006.285.15:35:01.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.15:35:01.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.15:35:01.85#ibcon#*before write, iclass 10, count 0 2006.285.15:35:01.85#ibcon#enter sib2, iclass 10, count 0 2006.285.15:35:01.85#ibcon#flushed, iclass 10, count 0 2006.285.15:35:01.85#ibcon#about to write, iclass 10, count 0 2006.285.15:35:01.85#ibcon#wrote, iclass 10, count 0 2006.285.15:35:01.85#ibcon#about to read 3, iclass 10, count 0 2006.285.15:35:01.89#ibcon#read 3, iclass 10, count 0 2006.285.15:35:01.89#ibcon#about to read 4, iclass 10, count 0 2006.285.15:35:01.89#ibcon#read 4, iclass 10, count 0 2006.285.15:35:01.89#ibcon#about to read 5, iclass 10, count 0 2006.285.15:35:01.89#ibcon#read 5, iclass 10, count 0 2006.285.15:35:01.89#ibcon#about to read 6, iclass 10, count 0 2006.285.15:35:01.89#ibcon#read 6, iclass 10, count 0 2006.285.15:35:01.89#ibcon#end of sib2, iclass 10, count 0 2006.285.15:35:01.89#ibcon#*after write, iclass 10, count 0 2006.285.15:35:01.89#ibcon#*before return 0, iclass 10, count 0 2006.285.15:35:01.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:35:01.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:35:01.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.15:35:01.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.15:35:01.89$vck44/va=2,6 2006.285.15:35:01.89#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.15:35:01.89#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.15:35:01.89#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:01.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:35:01.95#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:35:01.95#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:35:01.95#ibcon#enter wrdev, iclass 12, count 2 2006.285.15:35:01.95#ibcon#first serial, iclass 12, count 2 2006.285.15:35:01.95#ibcon#enter sib2, iclass 12, count 2 2006.285.15:35:01.95#ibcon#flushed, iclass 12, count 2 2006.285.15:35:01.95#ibcon#about to write, iclass 12, count 2 2006.285.15:35:01.95#ibcon#wrote, iclass 12, count 2 2006.285.15:35:01.95#ibcon#about to read 3, iclass 12, count 2 2006.285.15:35:01.97#ibcon#read 3, iclass 12, count 2 2006.285.15:35:01.97#ibcon#about to read 4, iclass 12, count 2 2006.285.15:35:01.97#ibcon#read 4, iclass 12, count 2 2006.285.15:35:01.97#ibcon#about to read 5, iclass 12, count 2 2006.285.15:35:01.97#ibcon#read 5, iclass 12, count 2 2006.285.15:35:01.97#ibcon#about to read 6, iclass 12, count 2 2006.285.15:35:01.97#ibcon#read 6, iclass 12, count 2 2006.285.15:35:01.97#ibcon#end of sib2, iclass 12, count 2 2006.285.15:35:01.97#ibcon#*mode == 0, iclass 12, count 2 2006.285.15:35:01.97#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.15:35:01.97#ibcon#[25=AT02-06\r\n] 2006.285.15:35:01.97#ibcon#*before write, iclass 12, count 2 2006.285.15:35:01.97#ibcon#enter sib2, iclass 12, count 2 2006.285.15:35:01.97#ibcon#flushed, iclass 12, count 2 2006.285.15:35:01.97#ibcon#about to write, iclass 12, count 2 2006.285.15:35:01.97#ibcon#wrote, iclass 12, count 2 2006.285.15:35:01.97#ibcon#about to read 3, iclass 12, count 2 2006.285.15:35:02.00#ibcon#read 3, iclass 12, count 2 2006.285.15:35:02.00#ibcon#about to read 4, iclass 12, count 2 2006.285.15:35:02.00#ibcon#read 4, iclass 12, count 2 2006.285.15:35:02.00#ibcon#about to read 5, iclass 12, count 2 2006.285.15:35:02.00#ibcon#read 5, iclass 12, count 2 2006.285.15:35:02.00#ibcon#about to read 6, iclass 12, count 2 2006.285.15:35:02.00#ibcon#read 6, iclass 12, count 2 2006.285.15:35:02.00#ibcon#end of sib2, iclass 12, count 2 2006.285.15:35:02.00#ibcon#*after write, iclass 12, count 2 2006.285.15:35:02.00#ibcon#*before return 0, iclass 12, count 2 2006.285.15:35:02.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:35:02.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:35:02.00#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.15:35:02.00#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:02.00#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:35:02.12#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:35:02.12#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:35:02.12#ibcon#enter wrdev, iclass 12, count 0 2006.285.15:35:02.12#ibcon#first serial, iclass 12, count 0 2006.285.15:35:02.12#ibcon#enter sib2, iclass 12, count 0 2006.285.15:35:02.12#ibcon#flushed, iclass 12, count 0 2006.285.15:35:02.12#ibcon#about to write, iclass 12, count 0 2006.285.15:35:02.12#ibcon#wrote, iclass 12, count 0 2006.285.15:35:02.12#ibcon#about to read 3, iclass 12, count 0 2006.285.15:35:02.14#ibcon#read 3, iclass 12, count 0 2006.285.15:35:02.14#ibcon#about to read 4, iclass 12, count 0 2006.285.15:35:02.14#ibcon#read 4, iclass 12, count 0 2006.285.15:35:02.14#ibcon#about to read 5, iclass 12, count 0 2006.285.15:35:02.14#ibcon#read 5, iclass 12, count 0 2006.285.15:35:02.14#ibcon#about to read 6, iclass 12, count 0 2006.285.15:35:02.14#ibcon#read 6, iclass 12, count 0 2006.285.15:35:02.14#ibcon#end of sib2, iclass 12, count 0 2006.285.15:35:02.14#ibcon#*mode == 0, iclass 12, count 0 2006.285.15:35:02.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.15:35:02.14#ibcon#[25=USB\r\n] 2006.285.15:35:02.14#ibcon#*before write, iclass 12, count 0 2006.285.15:35:02.14#ibcon#enter sib2, iclass 12, count 0 2006.285.15:35:02.14#ibcon#flushed, iclass 12, count 0 2006.285.15:35:02.14#ibcon#about to write, iclass 12, count 0 2006.285.15:35:02.14#ibcon#wrote, iclass 12, count 0 2006.285.15:35:02.14#ibcon#about to read 3, iclass 12, count 0 2006.285.15:35:02.17#ibcon#read 3, iclass 12, count 0 2006.285.15:35:02.17#ibcon#about to read 4, iclass 12, count 0 2006.285.15:35:02.17#ibcon#read 4, iclass 12, count 0 2006.285.15:35:02.17#ibcon#about to read 5, iclass 12, count 0 2006.285.15:35:02.17#ibcon#read 5, iclass 12, count 0 2006.285.15:35:02.17#ibcon#about to read 6, iclass 12, count 0 2006.285.15:35:02.17#ibcon#read 6, iclass 12, count 0 2006.285.15:35:02.17#ibcon#end of sib2, iclass 12, count 0 2006.285.15:35:02.17#ibcon#*after write, iclass 12, count 0 2006.285.15:35:02.17#ibcon#*before return 0, iclass 12, count 0 2006.285.15:35:02.17#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:35:02.17#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:35:02.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.15:35:02.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.15:35:02.17$vck44/valo=3,564.99 2006.285.15:35:02.17#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.15:35:02.17#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.15:35:02.17#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:02.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:35:02.17#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:35:02.17#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:35:02.17#ibcon#enter wrdev, iclass 14, count 0 2006.285.15:35:02.17#ibcon#first serial, iclass 14, count 0 2006.285.15:35:02.17#ibcon#enter sib2, iclass 14, count 0 2006.285.15:35:02.17#ibcon#flushed, iclass 14, count 0 2006.285.15:35:02.17#ibcon#about to write, iclass 14, count 0 2006.285.15:35:02.17#ibcon#wrote, iclass 14, count 0 2006.285.15:35:02.17#ibcon#about to read 3, iclass 14, count 0 2006.285.15:35:02.19#ibcon#read 3, iclass 14, count 0 2006.285.15:35:02.19#ibcon#about to read 4, iclass 14, count 0 2006.285.15:35:02.19#ibcon#read 4, iclass 14, count 0 2006.285.15:35:02.19#ibcon#about to read 5, iclass 14, count 0 2006.285.15:35:02.19#ibcon#read 5, iclass 14, count 0 2006.285.15:35:02.19#ibcon#about to read 6, iclass 14, count 0 2006.285.15:35:02.19#ibcon#read 6, iclass 14, count 0 2006.285.15:35:02.19#ibcon#end of sib2, iclass 14, count 0 2006.285.15:35:02.19#ibcon#*mode == 0, iclass 14, count 0 2006.285.15:35:02.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.15:35:02.19#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.15:35:02.19#ibcon#*before write, iclass 14, count 0 2006.285.15:35:02.19#ibcon#enter sib2, iclass 14, count 0 2006.285.15:35:02.19#ibcon#flushed, iclass 14, count 0 2006.285.15:35:02.19#ibcon#about to write, iclass 14, count 0 2006.285.15:35:02.19#ibcon#wrote, iclass 14, count 0 2006.285.15:35:02.19#ibcon#about to read 3, iclass 14, count 0 2006.285.15:35:02.23#ibcon#read 3, iclass 14, count 0 2006.285.15:35:02.23#ibcon#about to read 4, iclass 14, count 0 2006.285.15:35:02.23#ibcon#read 4, iclass 14, count 0 2006.285.15:35:02.23#ibcon#about to read 5, iclass 14, count 0 2006.285.15:35:02.23#ibcon#read 5, iclass 14, count 0 2006.285.15:35:02.23#ibcon#about to read 6, iclass 14, count 0 2006.285.15:35:02.23#ibcon#read 6, iclass 14, count 0 2006.285.15:35:02.23#ibcon#end of sib2, iclass 14, count 0 2006.285.15:35:02.23#ibcon#*after write, iclass 14, count 0 2006.285.15:35:02.23#ibcon#*before return 0, iclass 14, count 0 2006.285.15:35:02.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:35:02.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:35:02.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.15:35:02.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.15:35:02.23$vck44/va=3,7 2006.285.15:35:02.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.15:35:02.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.15:35:02.23#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:02.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:35:02.29#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:35:02.29#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:35:02.29#ibcon#enter wrdev, iclass 16, count 2 2006.285.15:35:02.29#ibcon#first serial, iclass 16, count 2 2006.285.15:35:02.29#ibcon#enter sib2, iclass 16, count 2 2006.285.15:35:02.29#ibcon#flushed, iclass 16, count 2 2006.285.15:35:02.29#ibcon#about to write, iclass 16, count 2 2006.285.15:35:02.29#ibcon#wrote, iclass 16, count 2 2006.285.15:35:02.29#ibcon#about to read 3, iclass 16, count 2 2006.285.15:35:02.31#ibcon#read 3, iclass 16, count 2 2006.285.15:35:02.31#ibcon#about to read 4, iclass 16, count 2 2006.285.15:35:02.31#ibcon#read 4, iclass 16, count 2 2006.285.15:35:02.31#ibcon#about to read 5, iclass 16, count 2 2006.285.15:35:02.31#ibcon#read 5, iclass 16, count 2 2006.285.15:35:02.31#ibcon#about to read 6, iclass 16, count 2 2006.285.15:35:02.31#ibcon#read 6, iclass 16, count 2 2006.285.15:35:02.31#ibcon#end of sib2, iclass 16, count 2 2006.285.15:35:02.31#ibcon#*mode == 0, iclass 16, count 2 2006.285.15:35:02.31#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.15:35:02.31#ibcon#[25=AT03-07\r\n] 2006.285.15:35:02.31#ibcon#*before write, iclass 16, count 2 2006.285.15:35:02.31#ibcon#enter sib2, iclass 16, count 2 2006.285.15:35:02.31#ibcon#flushed, iclass 16, count 2 2006.285.15:35:02.31#ibcon#about to write, iclass 16, count 2 2006.285.15:35:02.31#ibcon#wrote, iclass 16, count 2 2006.285.15:35:02.31#ibcon#about to read 3, iclass 16, count 2 2006.285.15:35:02.34#ibcon#read 3, iclass 16, count 2 2006.285.15:35:02.34#ibcon#about to read 4, iclass 16, count 2 2006.285.15:35:02.34#ibcon#read 4, iclass 16, count 2 2006.285.15:35:02.34#ibcon#about to read 5, iclass 16, count 2 2006.285.15:35:02.34#ibcon#read 5, iclass 16, count 2 2006.285.15:35:02.34#ibcon#about to read 6, iclass 16, count 2 2006.285.15:35:02.34#ibcon#read 6, iclass 16, count 2 2006.285.15:35:02.34#ibcon#end of sib2, iclass 16, count 2 2006.285.15:35:02.34#ibcon#*after write, iclass 16, count 2 2006.285.15:35:02.34#ibcon#*before return 0, iclass 16, count 2 2006.285.15:35:02.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:35:02.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:35:02.34#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.15:35:02.34#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:02.34#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:35:02.46#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:35:02.46#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:35:02.46#ibcon#enter wrdev, iclass 16, count 0 2006.285.15:35:02.46#ibcon#first serial, iclass 16, count 0 2006.285.15:35:02.46#ibcon#enter sib2, iclass 16, count 0 2006.285.15:35:02.46#ibcon#flushed, iclass 16, count 0 2006.285.15:35:02.46#ibcon#about to write, iclass 16, count 0 2006.285.15:35:02.46#ibcon#wrote, iclass 16, count 0 2006.285.15:35:02.46#ibcon#about to read 3, iclass 16, count 0 2006.285.15:35:02.48#ibcon#read 3, iclass 16, count 0 2006.285.15:35:02.80#ibcon#about to read 4, iclass 16, count 0 2006.285.15:35:02.80#ibcon#read 4, iclass 16, count 0 2006.285.15:35:02.80#ibcon#about to read 5, iclass 16, count 0 2006.285.15:35:02.80#ibcon#read 5, iclass 16, count 0 2006.285.15:35:02.80#ibcon#about to read 6, iclass 16, count 0 2006.285.15:35:02.80#ibcon#read 6, iclass 16, count 0 2006.285.15:35:02.80#ibcon#end of sib2, iclass 16, count 0 2006.285.15:35:02.80#ibcon#*mode == 0, iclass 16, count 0 2006.285.15:35:02.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.15:35:02.80#ibcon#[25=USB\r\n] 2006.285.15:35:02.80#ibcon#*before write, iclass 16, count 0 2006.285.15:35:02.80#ibcon#enter sib2, iclass 16, count 0 2006.285.15:35:02.80#ibcon#flushed, iclass 16, count 0 2006.285.15:35:02.80#ibcon#about to write, iclass 16, count 0 2006.285.15:35:02.80#ibcon#wrote, iclass 16, count 0 2006.285.15:35:02.80#ibcon#about to read 3, iclass 16, count 0 2006.285.15:35:02.83#ibcon#read 3, iclass 16, count 0 2006.285.15:35:02.83#ibcon#about to read 4, iclass 16, count 0 2006.285.15:35:02.83#ibcon#read 4, iclass 16, count 0 2006.285.15:35:02.83#ibcon#about to read 5, iclass 16, count 0 2006.285.15:35:02.83#ibcon#read 5, iclass 16, count 0 2006.285.15:35:02.83#ibcon#about to read 6, iclass 16, count 0 2006.285.15:35:02.83#ibcon#read 6, iclass 16, count 0 2006.285.15:35:02.83#ibcon#end of sib2, iclass 16, count 0 2006.285.15:35:02.83#ibcon#*after write, iclass 16, count 0 2006.285.15:35:02.83#ibcon#*before return 0, iclass 16, count 0 2006.285.15:35:02.83#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:35:02.83#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:35:02.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.15:35:02.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.15:35:02.83$vck44/valo=4,624.99 2006.285.15:35:02.83#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.15:35:02.83#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.15:35:02.83#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:02.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:35:02.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:35:02.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:35:02.83#ibcon#enter wrdev, iclass 18, count 0 2006.285.15:35:02.83#ibcon#first serial, iclass 18, count 0 2006.285.15:35:02.83#ibcon#enter sib2, iclass 18, count 0 2006.285.15:35:02.83#ibcon#flushed, iclass 18, count 0 2006.285.15:35:02.83#ibcon#about to write, iclass 18, count 0 2006.285.15:35:02.83#ibcon#wrote, iclass 18, count 0 2006.285.15:35:02.83#ibcon#about to read 3, iclass 18, count 0 2006.285.15:35:02.85#ibcon#read 3, iclass 18, count 0 2006.285.15:35:02.85#ibcon#about to read 4, iclass 18, count 0 2006.285.15:35:02.85#ibcon#read 4, iclass 18, count 0 2006.285.15:35:02.85#ibcon#about to read 5, iclass 18, count 0 2006.285.15:35:02.85#ibcon#read 5, iclass 18, count 0 2006.285.15:35:02.85#ibcon#about to read 6, iclass 18, count 0 2006.285.15:35:02.85#ibcon#read 6, iclass 18, count 0 2006.285.15:35:02.85#ibcon#end of sib2, iclass 18, count 0 2006.285.15:35:02.85#ibcon#*mode == 0, iclass 18, count 0 2006.285.15:35:02.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.15:35:02.85#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.15:35:02.85#ibcon#*before write, iclass 18, count 0 2006.285.15:35:02.85#ibcon#enter sib2, iclass 18, count 0 2006.285.15:35:02.85#ibcon#flushed, iclass 18, count 0 2006.285.15:35:02.85#ibcon#about to write, iclass 18, count 0 2006.285.15:35:02.85#ibcon#wrote, iclass 18, count 0 2006.285.15:35:02.85#ibcon#about to read 3, iclass 18, count 0 2006.285.15:35:02.89#ibcon#read 3, iclass 18, count 0 2006.285.15:35:02.89#ibcon#about to read 4, iclass 18, count 0 2006.285.15:35:02.89#ibcon#read 4, iclass 18, count 0 2006.285.15:35:02.89#ibcon#about to read 5, iclass 18, count 0 2006.285.15:35:02.89#ibcon#read 5, iclass 18, count 0 2006.285.15:35:02.89#ibcon#about to read 6, iclass 18, count 0 2006.285.15:35:02.89#ibcon#read 6, iclass 18, count 0 2006.285.15:35:02.89#ibcon#end of sib2, iclass 18, count 0 2006.285.15:35:02.89#ibcon#*after write, iclass 18, count 0 2006.285.15:35:02.89#ibcon#*before return 0, iclass 18, count 0 2006.285.15:35:02.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:35:02.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:35:02.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.15:35:02.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.15:35:02.89$vck44/va=4,6 2006.285.15:35:02.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.15:35:02.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.15:35:02.89#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:02.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:35:02.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:35:02.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:35:02.95#ibcon#enter wrdev, iclass 20, count 2 2006.285.15:35:02.95#ibcon#first serial, iclass 20, count 2 2006.285.15:35:02.95#ibcon#enter sib2, iclass 20, count 2 2006.285.15:35:02.95#ibcon#flushed, iclass 20, count 2 2006.285.15:35:02.95#ibcon#about to write, iclass 20, count 2 2006.285.15:35:02.95#ibcon#wrote, iclass 20, count 2 2006.285.15:35:02.95#ibcon#about to read 3, iclass 20, count 2 2006.285.15:35:02.97#ibcon#read 3, iclass 20, count 2 2006.285.15:35:02.97#ibcon#about to read 4, iclass 20, count 2 2006.285.15:35:02.97#ibcon#read 4, iclass 20, count 2 2006.285.15:35:02.97#ibcon#about to read 5, iclass 20, count 2 2006.285.15:35:02.97#ibcon#read 5, iclass 20, count 2 2006.285.15:35:02.97#ibcon#about to read 6, iclass 20, count 2 2006.285.15:35:02.97#ibcon#read 6, iclass 20, count 2 2006.285.15:35:02.97#ibcon#end of sib2, iclass 20, count 2 2006.285.15:35:02.97#ibcon#*mode == 0, iclass 20, count 2 2006.285.15:35:02.97#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.15:35:02.97#ibcon#[25=AT04-06\r\n] 2006.285.15:35:02.97#ibcon#*before write, iclass 20, count 2 2006.285.15:35:02.97#ibcon#enter sib2, iclass 20, count 2 2006.285.15:35:02.97#ibcon#flushed, iclass 20, count 2 2006.285.15:35:02.97#ibcon#about to write, iclass 20, count 2 2006.285.15:35:02.97#ibcon#wrote, iclass 20, count 2 2006.285.15:35:02.97#ibcon#about to read 3, iclass 20, count 2 2006.285.15:35:03.00#ibcon#read 3, iclass 20, count 2 2006.285.15:35:03.00#ibcon#about to read 4, iclass 20, count 2 2006.285.15:35:03.00#ibcon#read 4, iclass 20, count 2 2006.285.15:35:03.00#ibcon#about to read 5, iclass 20, count 2 2006.285.15:35:03.00#ibcon#read 5, iclass 20, count 2 2006.285.15:35:03.00#ibcon#about to read 6, iclass 20, count 2 2006.285.15:35:03.00#ibcon#read 6, iclass 20, count 2 2006.285.15:35:03.00#ibcon#end of sib2, iclass 20, count 2 2006.285.15:35:03.00#ibcon#*after write, iclass 20, count 2 2006.285.15:35:03.00#ibcon#*before return 0, iclass 20, count 2 2006.285.15:35:03.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:35:03.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:35:03.00#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.15:35:03.00#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:03.00#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:35:03.12#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:35:03.12#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:35:03.12#ibcon#enter wrdev, iclass 20, count 0 2006.285.15:35:03.12#ibcon#first serial, iclass 20, count 0 2006.285.15:35:03.12#ibcon#enter sib2, iclass 20, count 0 2006.285.15:35:03.12#ibcon#flushed, iclass 20, count 0 2006.285.15:35:03.12#ibcon#about to write, iclass 20, count 0 2006.285.15:35:03.12#ibcon#wrote, iclass 20, count 0 2006.285.15:35:03.12#ibcon#about to read 3, iclass 20, count 0 2006.285.15:35:03.14#ibcon#read 3, iclass 20, count 0 2006.285.15:35:03.14#ibcon#about to read 4, iclass 20, count 0 2006.285.15:35:03.14#ibcon#read 4, iclass 20, count 0 2006.285.15:35:03.14#ibcon#about to read 5, iclass 20, count 0 2006.285.15:35:03.14#ibcon#read 5, iclass 20, count 0 2006.285.15:35:03.14#ibcon#about to read 6, iclass 20, count 0 2006.285.15:35:03.14#ibcon#read 6, iclass 20, count 0 2006.285.15:35:03.14#ibcon#end of sib2, iclass 20, count 0 2006.285.15:35:03.14#ibcon#*mode == 0, iclass 20, count 0 2006.285.15:35:03.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.15:35:03.14#ibcon#[25=USB\r\n] 2006.285.15:35:03.14#ibcon#*before write, iclass 20, count 0 2006.285.15:35:03.14#ibcon#enter sib2, iclass 20, count 0 2006.285.15:35:03.14#ibcon#flushed, iclass 20, count 0 2006.285.15:35:03.14#ibcon#about to write, iclass 20, count 0 2006.285.15:35:03.14#ibcon#wrote, iclass 20, count 0 2006.285.15:35:03.14#ibcon#about to read 3, iclass 20, count 0 2006.285.15:35:03.17#ibcon#read 3, iclass 20, count 0 2006.285.15:35:03.17#ibcon#about to read 4, iclass 20, count 0 2006.285.15:35:03.17#ibcon#read 4, iclass 20, count 0 2006.285.15:35:03.17#ibcon#about to read 5, iclass 20, count 0 2006.285.15:35:03.17#ibcon#read 5, iclass 20, count 0 2006.285.15:35:03.17#ibcon#about to read 6, iclass 20, count 0 2006.285.15:35:03.17#ibcon#read 6, iclass 20, count 0 2006.285.15:35:03.17#ibcon#end of sib2, iclass 20, count 0 2006.285.15:35:03.17#ibcon#*after write, iclass 20, count 0 2006.285.15:35:03.17#ibcon#*before return 0, iclass 20, count 0 2006.285.15:35:03.17#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:35:03.17#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:35:03.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.15:35:03.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.15:35:03.17$vck44/valo=5,734.99 2006.285.15:35:03.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.15:35:03.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.15:35:03.17#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:03.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:35:03.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:35:03.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:35:03.17#ibcon#enter wrdev, iclass 22, count 0 2006.285.15:35:03.17#ibcon#first serial, iclass 22, count 0 2006.285.15:35:03.17#ibcon#enter sib2, iclass 22, count 0 2006.285.15:35:03.17#ibcon#flushed, iclass 22, count 0 2006.285.15:35:03.17#ibcon#about to write, iclass 22, count 0 2006.285.15:35:03.17#ibcon#wrote, iclass 22, count 0 2006.285.15:35:03.43#ibcon#about to read 3, iclass 22, count 0 2006.285.15:35:03.43#ibcon#read 3, iclass 22, count 0 2006.285.15:35:03.43#ibcon#about to read 4, iclass 22, count 0 2006.285.15:35:03.43#ibcon#read 4, iclass 22, count 0 2006.285.15:35:03.43#ibcon#about to read 5, iclass 22, count 0 2006.285.15:35:03.43#ibcon#read 5, iclass 22, count 0 2006.285.15:35:03.43#ibcon#about to read 6, iclass 22, count 0 2006.285.15:35:03.43#ibcon#read 6, iclass 22, count 0 2006.285.15:35:03.43#ibcon#end of sib2, iclass 22, count 0 2006.285.15:35:03.43#ibcon#*mode == 0, iclass 22, count 0 2006.285.15:35:03.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.15:35:03.43#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.15:35:03.43#ibcon#*before write, iclass 22, count 0 2006.285.15:35:03.43#ibcon#enter sib2, iclass 22, count 0 2006.285.15:35:03.43#ibcon#flushed, iclass 22, count 0 2006.285.15:35:03.43#ibcon#about to write, iclass 22, count 0 2006.285.15:35:03.43#ibcon#wrote, iclass 22, count 0 2006.285.15:35:03.43#ibcon#about to read 3, iclass 22, count 0 2006.285.15:35:03.47#ibcon#read 3, iclass 22, count 0 2006.285.15:35:03.47#ibcon#about to read 4, iclass 22, count 0 2006.285.15:35:03.47#ibcon#read 4, iclass 22, count 0 2006.285.15:35:03.47#ibcon#about to read 5, iclass 22, count 0 2006.285.15:35:03.47#ibcon#read 5, iclass 22, count 0 2006.285.15:35:03.47#ibcon#about to read 6, iclass 22, count 0 2006.285.15:35:03.47#ibcon#read 6, iclass 22, count 0 2006.285.15:35:03.47#ibcon#end of sib2, iclass 22, count 0 2006.285.15:35:03.47#ibcon#*after write, iclass 22, count 0 2006.285.15:35:03.47#ibcon#*before return 0, iclass 22, count 0 2006.285.15:35:03.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:35:03.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:35:03.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.15:35:03.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.15:35:03.47$vck44/va=5,3 2006.285.15:35:03.47#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.15:35:03.47#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.15:35:03.47#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:03.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:35:03.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:35:03.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:35:03.47#ibcon#enter wrdev, iclass 24, count 2 2006.285.15:35:03.47#ibcon#first serial, iclass 24, count 2 2006.285.15:35:03.47#ibcon#enter sib2, iclass 24, count 2 2006.285.15:35:03.47#ibcon#flushed, iclass 24, count 2 2006.285.15:35:03.47#ibcon#about to write, iclass 24, count 2 2006.285.15:35:03.47#ibcon#wrote, iclass 24, count 2 2006.285.15:35:03.47#ibcon#about to read 3, iclass 24, count 2 2006.285.15:35:03.49#ibcon#read 3, iclass 24, count 2 2006.285.15:35:03.49#ibcon#about to read 4, iclass 24, count 2 2006.285.15:35:03.49#ibcon#read 4, iclass 24, count 2 2006.285.15:35:03.49#ibcon#about to read 5, iclass 24, count 2 2006.285.15:35:03.49#ibcon#read 5, iclass 24, count 2 2006.285.15:35:03.49#ibcon#about to read 6, iclass 24, count 2 2006.285.15:35:03.49#ibcon#read 6, iclass 24, count 2 2006.285.15:35:03.49#ibcon#end of sib2, iclass 24, count 2 2006.285.15:35:03.49#ibcon#*mode == 0, iclass 24, count 2 2006.285.15:35:03.49#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.15:35:03.49#ibcon#[25=AT05-03\r\n] 2006.285.15:35:03.49#ibcon#*before write, iclass 24, count 2 2006.285.15:35:03.49#ibcon#enter sib2, iclass 24, count 2 2006.285.15:35:03.49#ibcon#flushed, iclass 24, count 2 2006.285.15:35:03.49#ibcon#about to write, iclass 24, count 2 2006.285.15:35:03.49#ibcon#wrote, iclass 24, count 2 2006.285.15:35:03.49#ibcon#about to read 3, iclass 24, count 2 2006.285.15:35:03.52#ibcon#read 3, iclass 24, count 2 2006.285.15:35:03.52#ibcon#about to read 4, iclass 24, count 2 2006.285.15:35:03.52#ibcon#read 4, iclass 24, count 2 2006.285.15:35:03.52#ibcon#about to read 5, iclass 24, count 2 2006.285.15:35:03.52#ibcon#read 5, iclass 24, count 2 2006.285.15:35:03.52#ibcon#about to read 6, iclass 24, count 2 2006.285.15:35:03.52#ibcon#read 6, iclass 24, count 2 2006.285.15:35:03.52#ibcon#end of sib2, iclass 24, count 2 2006.285.15:35:03.52#ibcon#*after write, iclass 24, count 2 2006.285.15:35:03.52#ibcon#*before return 0, iclass 24, count 2 2006.285.15:35:03.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:35:03.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:35:03.52#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.15:35:03.52#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:03.52#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:35:03.64#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:35:03.64#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:35:03.64#ibcon#enter wrdev, iclass 24, count 0 2006.285.15:35:03.64#ibcon#first serial, iclass 24, count 0 2006.285.15:35:03.64#ibcon#enter sib2, iclass 24, count 0 2006.285.15:35:03.64#ibcon#flushed, iclass 24, count 0 2006.285.15:35:03.64#ibcon#about to write, iclass 24, count 0 2006.285.15:35:03.64#ibcon#wrote, iclass 24, count 0 2006.285.15:35:03.64#ibcon#about to read 3, iclass 24, count 0 2006.285.15:35:03.66#ibcon#read 3, iclass 24, count 0 2006.285.15:35:03.66#ibcon#about to read 4, iclass 24, count 0 2006.285.15:35:03.66#ibcon#read 4, iclass 24, count 0 2006.285.15:35:03.66#ibcon#about to read 5, iclass 24, count 0 2006.285.15:35:03.66#ibcon#read 5, iclass 24, count 0 2006.285.15:35:03.66#ibcon#about to read 6, iclass 24, count 0 2006.285.15:35:03.66#ibcon#read 6, iclass 24, count 0 2006.285.15:35:03.66#ibcon#end of sib2, iclass 24, count 0 2006.285.15:35:03.66#ibcon#*mode == 0, iclass 24, count 0 2006.285.15:35:03.66#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.15:35:03.66#ibcon#[25=USB\r\n] 2006.285.15:35:03.66#ibcon#*before write, iclass 24, count 0 2006.285.15:35:03.66#ibcon#enter sib2, iclass 24, count 0 2006.285.15:35:03.66#ibcon#flushed, iclass 24, count 0 2006.285.15:35:03.66#ibcon#about to write, iclass 24, count 0 2006.285.15:35:03.66#ibcon#wrote, iclass 24, count 0 2006.285.15:35:03.66#ibcon#about to read 3, iclass 24, count 0 2006.285.15:35:03.69#ibcon#read 3, iclass 24, count 0 2006.285.15:35:03.69#ibcon#about to read 4, iclass 24, count 0 2006.285.15:35:03.69#ibcon#read 4, iclass 24, count 0 2006.285.15:35:03.69#ibcon#about to read 5, iclass 24, count 0 2006.285.15:35:03.69#ibcon#read 5, iclass 24, count 0 2006.285.15:35:03.69#ibcon#about to read 6, iclass 24, count 0 2006.285.15:35:03.69#ibcon#read 6, iclass 24, count 0 2006.285.15:35:03.69#ibcon#end of sib2, iclass 24, count 0 2006.285.15:35:03.69#ibcon#*after write, iclass 24, count 0 2006.285.15:35:03.69#ibcon#*before return 0, iclass 24, count 0 2006.285.15:35:03.69#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:35:03.69#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:35:03.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.15:35:03.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.15:35:03.69$vck44/valo=6,814.99 2006.285.15:35:03.69#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.15:35:03.69#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.15:35:03.69#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:03.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:35:03.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:35:03.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:35:03.69#ibcon#enter wrdev, iclass 26, count 0 2006.285.15:35:03.69#ibcon#first serial, iclass 26, count 0 2006.285.15:35:03.69#ibcon#enter sib2, iclass 26, count 0 2006.285.15:35:03.69#ibcon#flushed, iclass 26, count 0 2006.285.15:35:03.69#ibcon#about to write, iclass 26, count 0 2006.285.15:35:03.69#ibcon#wrote, iclass 26, count 0 2006.285.15:35:03.69#ibcon#about to read 3, iclass 26, count 0 2006.285.15:35:03.71#ibcon#read 3, iclass 26, count 0 2006.285.15:35:03.71#ibcon#about to read 4, iclass 26, count 0 2006.285.15:35:03.71#ibcon#read 4, iclass 26, count 0 2006.285.15:35:03.71#ibcon#about to read 5, iclass 26, count 0 2006.285.15:35:03.71#ibcon#read 5, iclass 26, count 0 2006.285.15:35:03.71#ibcon#about to read 6, iclass 26, count 0 2006.285.15:35:03.71#ibcon#read 6, iclass 26, count 0 2006.285.15:35:03.71#ibcon#end of sib2, iclass 26, count 0 2006.285.15:35:03.71#ibcon#*mode == 0, iclass 26, count 0 2006.285.15:35:03.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.15:35:03.71#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.15:35:03.71#ibcon#*before write, iclass 26, count 0 2006.285.15:35:03.71#ibcon#enter sib2, iclass 26, count 0 2006.285.15:35:03.71#ibcon#flushed, iclass 26, count 0 2006.285.15:35:03.71#ibcon#about to write, iclass 26, count 0 2006.285.15:35:03.71#ibcon#wrote, iclass 26, count 0 2006.285.15:35:03.71#ibcon#about to read 3, iclass 26, count 0 2006.285.15:35:03.75#ibcon#read 3, iclass 26, count 0 2006.285.15:35:03.75#ibcon#about to read 4, iclass 26, count 0 2006.285.15:35:03.75#ibcon#read 4, iclass 26, count 0 2006.285.15:35:03.75#ibcon#about to read 5, iclass 26, count 0 2006.285.15:35:03.75#ibcon#read 5, iclass 26, count 0 2006.285.15:35:03.75#ibcon#about to read 6, iclass 26, count 0 2006.285.15:35:03.75#ibcon#read 6, iclass 26, count 0 2006.285.15:35:03.75#ibcon#end of sib2, iclass 26, count 0 2006.285.15:35:03.75#ibcon#*after write, iclass 26, count 0 2006.285.15:35:03.75#ibcon#*before return 0, iclass 26, count 0 2006.285.15:35:03.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:35:03.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:35:03.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.15:35:03.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.15:35:03.75$vck44/va=6,4 2006.285.15:35:03.75#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.15:35:03.75#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.15:35:03.75#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:03.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:35:03.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:35:03.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:35:03.81#ibcon#enter wrdev, iclass 28, count 2 2006.285.15:35:03.81#ibcon#first serial, iclass 28, count 2 2006.285.15:35:03.81#ibcon#enter sib2, iclass 28, count 2 2006.285.15:35:03.81#ibcon#flushed, iclass 28, count 2 2006.285.15:35:03.81#ibcon#about to write, iclass 28, count 2 2006.285.15:35:03.81#ibcon#wrote, iclass 28, count 2 2006.285.15:35:03.81#ibcon#about to read 3, iclass 28, count 2 2006.285.15:35:03.83#ibcon#read 3, iclass 28, count 2 2006.285.15:35:03.83#ibcon#about to read 4, iclass 28, count 2 2006.285.15:35:03.83#ibcon#read 4, iclass 28, count 2 2006.285.15:35:03.83#ibcon#about to read 5, iclass 28, count 2 2006.285.15:35:03.83#ibcon#read 5, iclass 28, count 2 2006.285.15:35:03.83#ibcon#about to read 6, iclass 28, count 2 2006.285.15:35:03.83#ibcon#read 6, iclass 28, count 2 2006.285.15:35:03.83#ibcon#end of sib2, iclass 28, count 2 2006.285.15:35:03.83#ibcon#*mode == 0, iclass 28, count 2 2006.285.15:35:03.83#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.15:35:03.83#ibcon#[25=AT06-04\r\n] 2006.285.15:35:03.83#ibcon#*before write, iclass 28, count 2 2006.285.15:35:03.83#ibcon#enter sib2, iclass 28, count 2 2006.285.15:35:03.83#ibcon#flushed, iclass 28, count 2 2006.285.15:35:03.83#ibcon#about to write, iclass 28, count 2 2006.285.15:35:03.83#ibcon#wrote, iclass 28, count 2 2006.285.15:35:03.83#ibcon#about to read 3, iclass 28, count 2 2006.285.15:35:03.86#ibcon#read 3, iclass 28, count 2 2006.285.15:35:03.86#ibcon#about to read 4, iclass 28, count 2 2006.285.15:35:03.86#ibcon#read 4, iclass 28, count 2 2006.285.15:35:03.86#ibcon#about to read 5, iclass 28, count 2 2006.285.15:35:03.86#ibcon#read 5, iclass 28, count 2 2006.285.15:35:03.86#ibcon#about to read 6, iclass 28, count 2 2006.285.15:35:03.86#ibcon#read 6, iclass 28, count 2 2006.285.15:35:03.86#ibcon#end of sib2, iclass 28, count 2 2006.285.15:35:03.86#ibcon#*after write, iclass 28, count 2 2006.285.15:35:03.86#ibcon#*before return 0, iclass 28, count 2 2006.285.15:35:03.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:35:03.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:35:03.86#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.15:35:03.86#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:03.86#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:35:03.98#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:35:03.98#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:35:03.98#ibcon#enter wrdev, iclass 28, count 0 2006.285.15:35:03.98#ibcon#first serial, iclass 28, count 0 2006.285.15:35:03.98#ibcon#enter sib2, iclass 28, count 0 2006.285.15:35:03.98#ibcon#flushed, iclass 28, count 0 2006.285.15:35:03.98#ibcon#about to write, iclass 28, count 0 2006.285.15:35:03.98#ibcon#wrote, iclass 28, count 0 2006.285.15:35:03.98#ibcon#about to read 3, iclass 28, count 0 2006.285.15:35:04.00#ibcon#read 3, iclass 28, count 0 2006.285.15:35:04.00#ibcon#about to read 4, iclass 28, count 0 2006.285.15:35:04.00#ibcon#read 4, iclass 28, count 0 2006.285.15:35:04.00#ibcon#about to read 5, iclass 28, count 0 2006.285.15:35:04.00#ibcon#read 5, iclass 28, count 0 2006.285.15:35:04.00#ibcon#about to read 6, iclass 28, count 0 2006.285.15:35:04.00#ibcon#read 6, iclass 28, count 0 2006.285.15:35:04.00#ibcon#end of sib2, iclass 28, count 0 2006.285.15:35:04.00#ibcon#*mode == 0, iclass 28, count 0 2006.285.15:35:04.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.15:35:04.00#ibcon#[25=USB\r\n] 2006.285.15:35:04.00#ibcon#*before write, iclass 28, count 0 2006.285.15:35:04.00#ibcon#enter sib2, iclass 28, count 0 2006.285.15:35:04.00#ibcon#flushed, iclass 28, count 0 2006.285.15:35:04.00#ibcon#about to write, iclass 28, count 0 2006.285.15:35:04.00#ibcon#wrote, iclass 28, count 0 2006.285.15:35:04.00#ibcon#about to read 3, iclass 28, count 0 2006.285.15:35:04.03#ibcon#read 3, iclass 28, count 0 2006.285.15:35:04.03#ibcon#about to read 4, iclass 28, count 0 2006.285.15:35:04.03#ibcon#read 4, iclass 28, count 0 2006.285.15:35:04.03#ibcon#about to read 5, iclass 28, count 0 2006.285.15:35:04.03#ibcon#read 5, iclass 28, count 0 2006.285.15:35:04.03#ibcon#about to read 6, iclass 28, count 0 2006.285.15:35:04.03#ibcon#read 6, iclass 28, count 0 2006.285.15:35:04.03#ibcon#end of sib2, iclass 28, count 0 2006.285.15:35:04.03#ibcon#*after write, iclass 28, count 0 2006.285.15:35:04.03#ibcon#*before return 0, iclass 28, count 0 2006.285.15:35:04.03#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:35:04.03#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:35:04.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.15:35:04.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.15:35:04.03$vck44/valo=7,864.99 2006.285.15:35:04.03#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.15:35:04.03#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.15:35:04.03#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:04.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:35:04.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:35:04.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:35:04.03#ibcon#enter wrdev, iclass 30, count 0 2006.285.15:35:04.03#ibcon#first serial, iclass 30, count 0 2006.285.15:35:04.03#ibcon#enter sib2, iclass 30, count 0 2006.285.15:35:04.03#ibcon#flushed, iclass 30, count 0 2006.285.15:35:04.03#ibcon#about to write, iclass 30, count 0 2006.285.15:35:04.03#ibcon#wrote, iclass 30, count 0 2006.285.15:35:04.03#ibcon#about to read 3, iclass 30, count 0 2006.285.15:35:04.05#ibcon#read 3, iclass 30, count 0 2006.285.15:35:04.05#ibcon#about to read 4, iclass 30, count 0 2006.285.15:35:04.05#ibcon#read 4, iclass 30, count 0 2006.285.15:35:04.05#ibcon#about to read 5, iclass 30, count 0 2006.285.15:35:04.05#ibcon#read 5, iclass 30, count 0 2006.285.15:35:04.05#ibcon#about to read 6, iclass 30, count 0 2006.285.15:35:04.05#ibcon#read 6, iclass 30, count 0 2006.285.15:35:04.05#ibcon#end of sib2, iclass 30, count 0 2006.285.15:35:04.05#ibcon#*mode == 0, iclass 30, count 0 2006.285.15:35:04.05#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.15:35:04.05#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.15:35:04.05#ibcon#*before write, iclass 30, count 0 2006.285.15:35:04.05#ibcon#enter sib2, iclass 30, count 0 2006.285.15:35:04.05#ibcon#flushed, iclass 30, count 0 2006.285.15:35:04.05#ibcon#about to write, iclass 30, count 0 2006.285.15:35:04.05#ibcon#wrote, iclass 30, count 0 2006.285.15:35:04.05#ibcon#about to read 3, iclass 30, count 0 2006.285.15:35:04.09#ibcon#read 3, iclass 30, count 0 2006.285.15:35:04.09#ibcon#about to read 4, iclass 30, count 0 2006.285.15:35:04.09#ibcon#read 4, iclass 30, count 0 2006.285.15:35:04.09#ibcon#about to read 5, iclass 30, count 0 2006.285.15:35:04.09#ibcon#read 5, iclass 30, count 0 2006.285.15:35:04.09#ibcon#about to read 6, iclass 30, count 0 2006.285.15:35:04.09#ibcon#read 6, iclass 30, count 0 2006.285.15:35:04.09#ibcon#end of sib2, iclass 30, count 0 2006.285.15:35:04.09#ibcon#*after write, iclass 30, count 0 2006.285.15:35:04.09#ibcon#*before return 0, iclass 30, count 0 2006.285.15:35:04.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:35:04.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:35:04.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.15:35:04.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.15:35:04.09$vck44/va=7,4 2006.285.15:35:04.09#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.15:35:04.09#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.15:35:04.09#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:04.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:35:04.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:35:04.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:35:04.15#ibcon#enter wrdev, iclass 32, count 2 2006.285.15:35:04.15#ibcon#first serial, iclass 32, count 2 2006.285.15:35:04.15#ibcon#enter sib2, iclass 32, count 2 2006.285.15:35:04.15#ibcon#flushed, iclass 32, count 2 2006.285.15:35:04.15#ibcon#about to write, iclass 32, count 2 2006.285.15:35:04.15#ibcon#wrote, iclass 32, count 2 2006.285.15:35:04.15#ibcon#about to read 3, iclass 32, count 2 2006.285.15:35:04.17#ibcon#read 3, iclass 32, count 2 2006.285.15:35:04.17#ibcon#about to read 4, iclass 32, count 2 2006.285.15:35:04.17#ibcon#read 4, iclass 32, count 2 2006.285.15:35:04.17#ibcon#about to read 5, iclass 32, count 2 2006.285.15:35:04.17#ibcon#read 5, iclass 32, count 2 2006.285.15:35:04.17#ibcon#about to read 6, iclass 32, count 2 2006.285.15:35:04.17#ibcon#read 6, iclass 32, count 2 2006.285.15:35:04.17#ibcon#end of sib2, iclass 32, count 2 2006.285.15:35:04.17#ibcon#*mode == 0, iclass 32, count 2 2006.285.15:35:04.17#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.15:35:04.17#ibcon#[25=AT07-04\r\n] 2006.285.15:35:04.17#ibcon#*before write, iclass 32, count 2 2006.285.15:35:04.17#ibcon#enter sib2, iclass 32, count 2 2006.285.15:35:04.17#ibcon#flushed, iclass 32, count 2 2006.285.15:35:04.17#ibcon#about to write, iclass 32, count 2 2006.285.15:35:04.17#ibcon#wrote, iclass 32, count 2 2006.285.15:35:04.17#ibcon#about to read 3, iclass 32, count 2 2006.285.15:35:04.20#ibcon#read 3, iclass 32, count 2 2006.285.15:35:04.20#ibcon#about to read 4, iclass 32, count 2 2006.285.15:35:04.20#ibcon#read 4, iclass 32, count 2 2006.285.15:35:04.20#ibcon#about to read 5, iclass 32, count 2 2006.285.15:35:04.20#ibcon#read 5, iclass 32, count 2 2006.285.15:35:04.20#ibcon#about to read 6, iclass 32, count 2 2006.285.15:35:04.20#ibcon#read 6, iclass 32, count 2 2006.285.15:35:04.20#ibcon#end of sib2, iclass 32, count 2 2006.285.15:35:04.20#ibcon#*after write, iclass 32, count 2 2006.285.15:35:04.20#ibcon#*before return 0, iclass 32, count 2 2006.285.15:35:04.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:35:04.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:35:04.20#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.15:35:04.20#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:04.20#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:35:04.32#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:35:04.32#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:35:04.32#ibcon#enter wrdev, iclass 32, count 0 2006.285.15:35:04.32#ibcon#first serial, iclass 32, count 0 2006.285.15:35:04.32#ibcon#enter sib2, iclass 32, count 0 2006.285.15:35:04.32#ibcon#flushed, iclass 32, count 0 2006.285.15:35:04.32#ibcon#about to write, iclass 32, count 0 2006.285.15:35:04.32#ibcon#wrote, iclass 32, count 0 2006.285.15:35:04.32#ibcon#about to read 3, iclass 32, count 0 2006.285.15:35:04.34#ibcon#read 3, iclass 32, count 0 2006.285.15:35:04.34#ibcon#about to read 4, iclass 32, count 0 2006.285.15:35:04.34#ibcon#read 4, iclass 32, count 0 2006.285.15:35:04.34#ibcon#about to read 5, iclass 32, count 0 2006.285.15:35:04.34#ibcon#read 5, iclass 32, count 0 2006.285.15:35:04.34#ibcon#about to read 6, iclass 32, count 0 2006.285.15:35:04.34#ibcon#read 6, iclass 32, count 0 2006.285.15:35:04.34#ibcon#end of sib2, iclass 32, count 0 2006.285.15:35:04.34#ibcon#*mode == 0, iclass 32, count 0 2006.285.15:35:04.34#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.15:35:04.34#ibcon#[25=USB\r\n] 2006.285.15:35:04.34#ibcon#*before write, iclass 32, count 0 2006.285.15:35:04.34#ibcon#enter sib2, iclass 32, count 0 2006.285.15:35:04.34#ibcon#flushed, iclass 32, count 0 2006.285.15:35:04.34#ibcon#about to write, iclass 32, count 0 2006.285.15:35:04.34#ibcon#wrote, iclass 32, count 0 2006.285.15:35:04.34#ibcon#about to read 3, iclass 32, count 0 2006.285.15:35:04.37#ibcon#read 3, iclass 32, count 0 2006.285.15:35:04.37#ibcon#about to read 4, iclass 32, count 0 2006.285.15:35:04.37#ibcon#read 4, iclass 32, count 0 2006.285.15:35:04.37#ibcon#about to read 5, iclass 32, count 0 2006.285.15:35:04.37#ibcon#read 5, iclass 32, count 0 2006.285.15:35:04.37#ibcon#about to read 6, iclass 32, count 0 2006.285.15:35:04.37#ibcon#read 6, iclass 32, count 0 2006.285.15:35:04.37#ibcon#end of sib2, iclass 32, count 0 2006.285.15:35:04.37#ibcon#*after write, iclass 32, count 0 2006.285.15:35:04.37#ibcon#*before return 0, iclass 32, count 0 2006.285.15:35:04.37#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:35:04.37#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:35:04.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.15:35:04.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.15:35:04.37$vck44/valo=8,884.99 2006.285.15:35:04.37#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.15:35:04.37#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.15:35:04.37#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:04.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:35:04.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:35:04.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:35:04.37#ibcon#enter wrdev, iclass 34, count 0 2006.285.15:35:04.37#ibcon#first serial, iclass 34, count 0 2006.285.15:35:04.37#ibcon#enter sib2, iclass 34, count 0 2006.285.15:35:04.37#ibcon#flushed, iclass 34, count 0 2006.285.15:35:04.37#ibcon#about to write, iclass 34, count 0 2006.285.15:35:04.37#ibcon#wrote, iclass 34, count 0 2006.285.15:35:04.37#ibcon#about to read 3, iclass 34, count 0 2006.285.15:35:04.39#ibcon#read 3, iclass 34, count 0 2006.285.15:35:04.54#ibcon#about to read 4, iclass 34, count 0 2006.285.15:35:04.54#ibcon#read 4, iclass 34, count 0 2006.285.15:35:04.54#ibcon#about to read 5, iclass 34, count 0 2006.285.15:35:04.54#ibcon#read 5, iclass 34, count 0 2006.285.15:35:04.54#ibcon#about to read 6, iclass 34, count 0 2006.285.15:35:04.54#ibcon#read 6, iclass 34, count 0 2006.285.15:35:04.54#ibcon#end of sib2, iclass 34, count 0 2006.285.15:35:04.54#ibcon#*mode == 0, iclass 34, count 0 2006.285.15:35:04.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.15:35:04.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.15:35:04.54#ibcon#*before write, iclass 34, count 0 2006.285.15:35:04.54#ibcon#enter sib2, iclass 34, count 0 2006.285.15:35:04.54#ibcon#flushed, iclass 34, count 0 2006.285.15:35:04.54#ibcon#about to write, iclass 34, count 0 2006.285.15:35:04.54#ibcon#wrote, iclass 34, count 0 2006.285.15:35:04.54#ibcon#about to read 3, iclass 34, count 0 2006.285.15:35:04.58#ibcon#read 3, iclass 34, count 0 2006.285.15:35:04.58#ibcon#about to read 4, iclass 34, count 0 2006.285.15:35:04.58#ibcon#read 4, iclass 34, count 0 2006.285.15:35:04.58#ibcon#about to read 5, iclass 34, count 0 2006.285.15:35:04.58#ibcon#read 5, iclass 34, count 0 2006.285.15:35:04.58#ibcon#about to read 6, iclass 34, count 0 2006.285.15:35:04.58#ibcon#read 6, iclass 34, count 0 2006.285.15:35:04.58#ibcon#end of sib2, iclass 34, count 0 2006.285.15:35:04.58#ibcon#*after write, iclass 34, count 0 2006.285.15:35:04.58#ibcon#*before return 0, iclass 34, count 0 2006.285.15:35:04.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:35:04.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:35:04.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.15:35:04.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.15:35:04.58$vck44/va=8,3 2006.285.15:35:04.58#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.15:35:04.58#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.15:35:04.58#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:04.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:35:04.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:35:04.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:35:04.58#ibcon#enter wrdev, iclass 36, count 2 2006.285.15:35:04.58#ibcon#first serial, iclass 36, count 2 2006.285.15:35:04.58#ibcon#enter sib2, iclass 36, count 2 2006.285.15:35:04.58#ibcon#flushed, iclass 36, count 2 2006.285.15:35:04.58#ibcon#about to write, iclass 36, count 2 2006.285.15:35:04.58#ibcon#wrote, iclass 36, count 2 2006.285.15:35:04.58#ibcon#about to read 3, iclass 36, count 2 2006.285.15:35:04.60#ibcon#read 3, iclass 36, count 2 2006.285.15:35:04.60#ibcon#about to read 4, iclass 36, count 2 2006.285.15:35:04.60#ibcon#read 4, iclass 36, count 2 2006.285.15:35:04.60#ibcon#about to read 5, iclass 36, count 2 2006.285.15:35:04.60#ibcon#read 5, iclass 36, count 2 2006.285.15:35:04.60#ibcon#about to read 6, iclass 36, count 2 2006.285.15:35:04.60#ibcon#read 6, iclass 36, count 2 2006.285.15:35:04.60#ibcon#end of sib2, iclass 36, count 2 2006.285.15:35:04.60#ibcon#*mode == 0, iclass 36, count 2 2006.285.15:35:04.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.15:35:04.60#ibcon#[25=AT08-03\r\n] 2006.285.15:35:04.60#ibcon#*before write, iclass 36, count 2 2006.285.15:35:04.60#ibcon#enter sib2, iclass 36, count 2 2006.285.15:35:04.60#ibcon#flushed, iclass 36, count 2 2006.285.15:35:04.60#ibcon#about to write, iclass 36, count 2 2006.285.15:35:04.60#ibcon#wrote, iclass 36, count 2 2006.285.15:35:04.60#ibcon#about to read 3, iclass 36, count 2 2006.285.15:35:04.63#ibcon#read 3, iclass 36, count 2 2006.285.15:35:04.63#ibcon#about to read 4, iclass 36, count 2 2006.285.15:35:04.63#ibcon#read 4, iclass 36, count 2 2006.285.15:35:04.63#ibcon#about to read 5, iclass 36, count 2 2006.285.15:35:04.63#ibcon#read 5, iclass 36, count 2 2006.285.15:35:04.63#ibcon#about to read 6, iclass 36, count 2 2006.285.15:35:04.63#ibcon#read 6, iclass 36, count 2 2006.285.15:35:04.63#ibcon#end of sib2, iclass 36, count 2 2006.285.15:35:04.63#ibcon#*after write, iclass 36, count 2 2006.285.15:35:04.63#ibcon#*before return 0, iclass 36, count 2 2006.285.15:35:04.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:35:04.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:35:04.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.15:35:04.63#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:04.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:35:04.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:35:04.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:35:04.75#ibcon#enter wrdev, iclass 36, count 0 2006.285.15:35:04.75#ibcon#first serial, iclass 36, count 0 2006.285.15:35:04.75#ibcon#enter sib2, iclass 36, count 0 2006.285.15:35:04.75#ibcon#flushed, iclass 36, count 0 2006.285.15:35:04.75#ibcon#about to write, iclass 36, count 0 2006.285.15:35:04.75#ibcon#wrote, iclass 36, count 0 2006.285.15:35:04.75#ibcon#about to read 3, iclass 36, count 0 2006.285.15:35:04.77#ibcon#read 3, iclass 36, count 0 2006.285.15:35:04.77#ibcon#about to read 4, iclass 36, count 0 2006.285.15:35:04.77#ibcon#read 4, iclass 36, count 0 2006.285.15:35:04.77#ibcon#about to read 5, iclass 36, count 0 2006.285.15:35:04.77#ibcon#read 5, iclass 36, count 0 2006.285.15:35:04.77#ibcon#about to read 6, iclass 36, count 0 2006.285.15:35:04.77#ibcon#read 6, iclass 36, count 0 2006.285.15:35:04.77#ibcon#end of sib2, iclass 36, count 0 2006.285.15:35:04.77#ibcon#*mode == 0, iclass 36, count 0 2006.285.15:35:04.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.15:35:04.77#ibcon#[25=USB\r\n] 2006.285.15:35:04.77#ibcon#*before write, iclass 36, count 0 2006.285.15:35:04.77#ibcon#enter sib2, iclass 36, count 0 2006.285.15:35:04.77#ibcon#flushed, iclass 36, count 0 2006.285.15:35:04.77#ibcon#about to write, iclass 36, count 0 2006.285.15:35:04.77#ibcon#wrote, iclass 36, count 0 2006.285.15:35:04.77#ibcon#about to read 3, iclass 36, count 0 2006.285.15:35:04.80#ibcon#read 3, iclass 36, count 0 2006.285.15:35:04.80#ibcon#about to read 4, iclass 36, count 0 2006.285.15:35:04.80#ibcon#read 4, iclass 36, count 0 2006.285.15:35:04.80#ibcon#about to read 5, iclass 36, count 0 2006.285.15:35:04.80#ibcon#read 5, iclass 36, count 0 2006.285.15:35:04.80#ibcon#about to read 6, iclass 36, count 0 2006.285.15:35:04.80#ibcon#read 6, iclass 36, count 0 2006.285.15:35:04.80#ibcon#end of sib2, iclass 36, count 0 2006.285.15:35:04.80#ibcon#*after write, iclass 36, count 0 2006.285.15:35:04.80#ibcon#*before return 0, iclass 36, count 0 2006.285.15:35:04.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:35:04.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:35:04.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.15:35:04.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.15:35:04.80$vck44/vblo=1,629.99 2006.285.15:35:04.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.15:35:04.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.15:35:04.80#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:04.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:35:04.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:35:04.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:35:04.80#ibcon#enter wrdev, iclass 38, count 0 2006.285.15:35:04.80#ibcon#first serial, iclass 38, count 0 2006.285.15:35:04.80#ibcon#enter sib2, iclass 38, count 0 2006.285.15:35:04.80#ibcon#flushed, iclass 38, count 0 2006.285.15:35:04.80#ibcon#about to write, iclass 38, count 0 2006.285.15:35:04.80#ibcon#wrote, iclass 38, count 0 2006.285.15:35:04.80#ibcon#about to read 3, iclass 38, count 0 2006.285.15:35:04.82#ibcon#read 3, iclass 38, count 0 2006.285.15:35:04.82#ibcon#about to read 4, iclass 38, count 0 2006.285.15:35:04.82#ibcon#read 4, iclass 38, count 0 2006.285.15:35:04.82#ibcon#about to read 5, iclass 38, count 0 2006.285.15:35:04.82#ibcon#read 5, iclass 38, count 0 2006.285.15:35:04.82#ibcon#about to read 6, iclass 38, count 0 2006.285.15:35:04.82#ibcon#read 6, iclass 38, count 0 2006.285.15:35:04.82#ibcon#end of sib2, iclass 38, count 0 2006.285.15:35:04.82#ibcon#*mode == 0, iclass 38, count 0 2006.285.15:35:04.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.15:35:04.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.15:35:04.82#ibcon#*before write, iclass 38, count 0 2006.285.15:35:04.82#ibcon#enter sib2, iclass 38, count 0 2006.285.15:35:04.82#ibcon#flushed, iclass 38, count 0 2006.285.15:35:04.82#ibcon#about to write, iclass 38, count 0 2006.285.15:35:04.82#ibcon#wrote, iclass 38, count 0 2006.285.15:35:04.82#ibcon#about to read 3, iclass 38, count 0 2006.285.15:35:04.86#ibcon#read 3, iclass 38, count 0 2006.285.15:35:04.86#ibcon#about to read 4, iclass 38, count 0 2006.285.15:35:04.86#ibcon#read 4, iclass 38, count 0 2006.285.15:35:04.86#ibcon#about to read 5, iclass 38, count 0 2006.285.15:35:04.86#ibcon#read 5, iclass 38, count 0 2006.285.15:35:04.86#ibcon#about to read 6, iclass 38, count 0 2006.285.15:35:04.86#ibcon#read 6, iclass 38, count 0 2006.285.15:35:04.86#ibcon#end of sib2, iclass 38, count 0 2006.285.15:35:04.86#ibcon#*after write, iclass 38, count 0 2006.285.15:35:04.86#ibcon#*before return 0, iclass 38, count 0 2006.285.15:35:04.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:35:04.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:35:04.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.15:35:04.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.15:35:04.86$vck44/vb=1,4 2006.285.15:35:04.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.15:35:04.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.15:35:04.86#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:04.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:35:04.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:35:04.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:35:04.86#ibcon#enter wrdev, iclass 40, count 2 2006.285.15:35:04.86#ibcon#first serial, iclass 40, count 2 2006.285.15:35:04.86#ibcon#enter sib2, iclass 40, count 2 2006.285.15:35:04.86#ibcon#flushed, iclass 40, count 2 2006.285.15:35:04.86#ibcon#about to write, iclass 40, count 2 2006.285.15:35:04.86#ibcon#wrote, iclass 40, count 2 2006.285.15:35:04.86#ibcon#about to read 3, iclass 40, count 2 2006.285.15:35:04.88#ibcon#read 3, iclass 40, count 2 2006.285.15:35:04.88#ibcon#about to read 4, iclass 40, count 2 2006.285.15:35:04.88#ibcon#read 4, iclass 40, count 2 2006.285.15:35:04.88#ibcon#about to read 5, iclass 40, count 2 2006.285.15:35:04.88#ibcon#read 5, iclass 40, count 2 2006.285.15:35:04.88#ibcon#about to read 6, iclass 40, count 2 2006.285.15:35:04.88#ibcon#read 6, iclass 40, count 2 2006.285.15:35:04.88#ibcon#end of sib2, iclass 40, count 2 2006.285.15:35:04.88#ibcon#*mode == 0, iclass 40, count 2 2006.285.15:35:04.88#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.15:35:04.88#ibcon#[27=AT01-04\r\n] 2006.285.15:35:04.88#ibcon#*before write, iclass 40, count 2 2006.285.15:35:04.88#ibcon#enter sib2, iclass 40, count 2 2006.285.15:35:04.88#ibcon#flushed, iclass 40, count 2 2006.285.15:35:04.88#ibcon#about to write, iclass 40, count 2 2006.285.15:35:04.88#ibcon#wrote, iclass 40, count 2 2006.285.15:35:04.88#ibcon#about to read 3, iclass 40, count 2 2006.285.15:35:04.91#ibcon#read 3, iclass 40, count 2 2006.285.15:35:04.91#ibcon#about to read 4, iclass 40, count 2 2006.285.15:35:04.91#ibcon#read 4, iclass 40, count 2 2006.285.15:35:04.91#ibcon#about to read 5, iclass 40, count 2 2006.285.15:35:04.91#ibcon#read 5, iclass 40, count 2 2006.285.15:35:04.91#ibcon#about to read 6, iclass 40, count 2 2006.285.15:35:04.91#ibcon#read 6, iclass 40, count 2 2006.285.15:35:04.91#ibcon#end of sib2, iclass 40, count 2 2006.285.15:35:04.91#ibcon#*after write, iclass 40, count 2 2006.285.15:35:04.91#ibcon#*before return 0, iclass 40, count 2 2006.285.15:35:04.91#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:35:04.91#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:35:04.91#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.15:35:04.91#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:04.91#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:35:05.03#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:35:05.03#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:35:05.03#ibcon#enter wrdev, iclass 40, count 0 2006.285.15:35:05.03#ibcon#first serial, iclass 40, count 0 2006.285.15:35:05.03#ibcon#enter sib2, iclass 40, count 0 2006.285.15:35:05.03#ibcon#flushed, iclass 40, count 0 2006.285.15:35:05.03#ibcon#about to write, iclass 40, count 0 2006.285.15:35:05.03#ibcon#wrote, iclass 40, count 0 2006.285.15:35:05.03#ibcon#about to read 3, iclass 40, count 0 2006.285.15:35:05.05#ibcon#read 3, iclass 40, count 0 2006.285.15:35:05.05#ibcon#about to read 4, iclass 40, count 0 2006.285.15:35:05.05#ibcon#read 4, iclass 40, count 0 2006.285.15:35:05.05#ibcon#about to read 5, iclass 40, count 0 2006.285.15:35:05.05#ibcon#read 5, iclass 40, count 0 2006.285.15:35:05.05#ibcon#about to read 6, iclass 40, count 0 2006.285.15:35:05.05#ibcon#read 6, iclass 40, count 0 2006.285.15:35:05.05#ibcon#end of sib2, iclass 40, count 0 2006.285.15:35:05.05#ibcon#*mode == 0, iclass 40, count 0 2006.285.15:35:05.05#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.15:35:05.05#ibcon#[27=USB\r\n] 2006.285.15:35:05.05#ibcon#*before write, iclass 40, count 0 2006.285.15:35:05.05#ibcon#enter sib2, iclass 40, count 0 2006.285.15:35:05.05#ibcon#flushed, iclass 40, count 0 2006.285.15:35:05.05#ibcon#about to write, iclass 40, count 0 2006.285.15:35:05.05#ibcon#wrote, iclass 40, count 0 2006.285.15:35:05.05#ibcon#about to read 3, iclass 40, count 0 2006.285.15:35:05.08#ibcon#read 3, iclass 40, count 0 2006.285.15:35:05.08#ibcon#about to read 4, iclass 40, count 0 2006.285.15:35:05.08#ibcon#read 4, iclass 40, count 0 2006.285.15:35:05.08#ibcon#about to read 5, iclass 40, count 0 2006.285.15:35:05.08#ibcon#read 5, iclass 40, count 0 2006.285.15:35:05.08#ibcon#about to read 6, iclass 40, count 0 2006.285.15:35:05.08#ibcon#read 6, iclass 40, count 0 2006.285.15:35:05.08#ibcon#end of sib2, iclass 40, count 0 2006.285.15:35:05.08#ibcon#*after write, iclass 40, count 0 2006.285.15:35:05.08#ibcon#*before return 0, iclass 40, count 0 2006.285.15:35:05.08#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:35:05.08#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:35:05.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.15:35:05.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.15:35:05.08$vck44/vblo=2,634.99 2006.285.15:35:05.08#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.15:35:05.08#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.15:35:05.08#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:05.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:35:05.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:35:05.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:35:05.08#ibcon#enter wrdev, iclass 4, count 0 2006.285.15:35:05.08#ibcon#first serial, iclass 4, count 0 2006.285.15:35:05.08#ibcon#enter sib2, iclass 4, count 0 2006.285.15:35:05.08#ibcon#flushed, iclass 4, count 0 2006.285.15:35:05.08#ibcon#about to write, iclass 4, count 0 2006.285.15:35:05.08#ibcon#wrote, iclass 4, count 0 2006.285.15:35:05.08#ibcon#about to read 3, iclass 4, count 0 2006.285.15:35:05.10#ibcon#read 3, iclass 4, count 0 2006.285.15:35:05.10#ibcon#about to read 4, iclass 4, count 0 2006.285.15:35:05.10#ibcon#read 4, iclass 4, count 0 2006.285.15:35:05.10#ibcon#about to read 5, iclass 4, count 0 2006.285.15:35:05.10#ibcon#read 5, iclass 4, count 0 2006.285.15:35:05.10#ibcon#about to read 6, iclass 4, count 0 2006.285.15:35:05.10#ibcon#read 6, iclass 4, count 0 2006.285.15:35:05.10#ibcon#end of sib2, iclass 4, count 0 2006.285.15:35:05.10#ibcon#*mode == 0, iclass 4, count 0 2006.285.15:35:05.10#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.15:35:05.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.15:35:05.10#ibcon#*before write, iclass 4, count 0 2006.285.15:35:05.10#ibcon#enter sib2, iclass 4, count 0 2006.285.15:35:05.10#ibcon#flushed, iclass 4, count 0 2006.285.15:35:05.10#ibcon#about to write, iclass 4, count 0 2006.285.15:35:05.10#ibcon#wrote, iclass 4, count 0 2006.285.15:35:05.10#ibcon#about to read 3, iclass 4, count 0 2006.285.15:35:05.14#ibcon#read 3, iclass 4, count 0 2006.285.15:35:05.14#ibcon#about to read 4, iclass 4, count 0 2006.285.15:35:05.14#ibcon#read 4, iclass 4, count 0 2006.285.15:35:05.14#ibcon#about to read 5, iclass 4, count 0 2006.285.15:35:05.14#ibcon#read 5, iclass 4, count 0 2006.285.15:35:05.14#ibcon#about to read 6, iclass 4, count 0 2006.285.15:35:05.14#ibcon#read 6, iclass 4, count 0 2006.285.15:35:05.14#ibcon#end of sib2, iclass 4, count 0 2006.285.15:35:05.14#ibcon#*after write, iclass 4, count 0 2006.285.15:35:05.14#ibcon#*before return 0, iclass 4, count 0 2006.285.15:35:05.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:35:05.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:35:05.14#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.15:35:05.14#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.15:35:05.14$vck44/vb=2,5 2006.285.15:35:05.14#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.15:35:05.14#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.15:35:05.14#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:05.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:35:05.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:35:05.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:35:05.20#ibcon#enter wrdev, iclass 6, count 2 2006.285.15:35:05.20#ibcon#first serial, iclass 6, count 2 2006.285.15:35:05.20#ibcon#enter sib2, iclass 6, count 2 2006.285.15:35:05.20#ibcon#flushed, iclass 6, count 2 2006.285.15:35:05.20#ibcon#about to write, iclass 6, count 2 2006.285.15:35:05.20#ibcon#wrote, iclass 6, count 2 2006.285.15:35:05.20#ibcon#about to read 3, iclass 6, count 2 2006.285.15:35:05.22#ibcon#read 3, iclass 6, count 2 2006.285.15:35:05.22#ibcon#about to read 4, iclass 6, count 2 2006.285.15:35:05.22#ibcon#read 4, iclass 6, count 2 2006.285.15:35:05.22#ibcon#about to read 5, iclass 6, count 2 2006.285.15:35:05.22#ibcon#read 5, iclass 6, count 2 2006.285.15:35:05.22#ibcon#about to read 6, iclass 6, count 2 2006.285.15:35:05.22#ibcon#read 6, iclass 6, count 2 2006.285.15:35:05.22#ibcon#end of sib2, iclass 6, count 2 2006.285.15:35:05.22#ibcon#*mode == 0, iclass 6, count 2 2006.285.15:35:05.22#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.15:35:05.22#ibcon#[27=AT02-05\r\n] 2006.285.15:35:05.22#ibcon#*before write, iclass 6, count 2 2006.285.15:35:05.22#ibcon#enter sib2, iclass 6, count 2 2006.285.15:35:05.22#ibcon#flushed, iclass 6, count 2 2006.285.15:35:05.22#ibcon#about to write, iclass 6, count 2 2006.285.15:35:05.22#ibcon#wrote, iclass 6, count 2 2006.285.15:35:05.22#ibcon#about to read 3, iclass 6, count 2 2006.285.15:35:05.25#ibcon#read 3, iclass 6, count 2 2006.285.15:35:05.25#ibcon#about to read 4, iclass 6, count 2 2006.285.15:35:05.25#ibcon#read 4, iclass 6, count 2 2006.285.15:35:05.25#ibcon#about to read 5, iclass 6, count 2 2006.285.15:35:05.25#ibcon#read 5, iclass 6, count 2 2006.285.15:35:05.25#ibcon#about to read 6, iclass 6, count 2 2006.285.15:35:05.25#ibcon#read 6, iclass 6, count 2 2006.285.15:35:05.25#ibcon#end of sib2, iclass 6, count 2 2006.285.15:35:05.25#ibcon#*after write, iclass 6, count 2 2006.285.15:35:05.25#ibcon#*before return 0, iclass 6, count 2 2006.285.15:35:05.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:35:05.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:35:05.25#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.15:35:05.25#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:05.25#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:35:05.37#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:35:05.37#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:35:05.37#ibcon#enter wrdev, iclass 6, count 0 2006.285.15:35:05.37#ibcon#first serial, iclass 6, count 0 2006.285.15:35:05.37#ibcon#enter sib2, iclass 6, count 0 2006.285.15:35:05.37#ibcon#flushed, iclass 6, count 0 2006.285.15:35:05.37#ibcon#about to write, iclass 6, count 0 2006.285.15:35:05.37#ibcon#wrote, iclass 6, count 0 2006.285.15:35:05.37#ibcon#about to read 3, iclass 6, count 0 2006.285.15:35:05.39#ibcon#read 3, iclass 6, count 0 2006.285.15:35:05.39#ibcon#about to read 4, iclass 6, count 0 2006.285.15:35:05.39#ibcon#read 4, iclass 6, count 0 2006.285.15:35:05.39#ibcon#about to read 5, iclass 6, count 0 2006.285.15:35:05.39#ibcon#read 5, iclass 6, count 0 2006.285.15:35:05.39#ibcon#about to read 6, iclass 6, count 0 2006.285.15:35:05.39#ibcon#read 6, iclass 6, count 0 2006.285.15:35:05.39#ibcon#end of sib2, iclass 6, count 0 2006.285.15:35:05.39#ibcon#*mode == 0, iclass 6, count 0 2006.285.15:35:05.39#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.15:35:05.39#ibcon#[27=USB\r\n] 2006.285.15:35:05.39#ibcon#*before write, iclass 6, count 0 2006.285.15:35:05.39#ibcon#enter sib2, iclass 6, count 0 2006.285.15:35:05.39#ibcon#flushed, iclass 6, count 0 2006.285.15:35:05.39#ibcon#about to write, iclass 6, count 0 2006.285.15:35:05.39#ibcon#wrote, iclass 6, count 0 2006.285.15:35:05.39#ibcon#about to read 3, iclass 6, count 0 2006.285.15:35:05.42#ibcon#read 3, iclass 6, count 0 2006.285.15:35:05.42#ibcon#about to read 4, iclass 6, count 0 2006.285.15:35:05.42#ibcon#read 4, iclass 6, count 0 2006.285.15:35:05.42#ibcon#about to read 5, iclass 6, count 0 2006.285.15:35:05.42#ibcon#read 5, iclass 6, count 0 2006.285.15:35:05.42#ibcon#about to read 6, iclass 6, count 0 2006.285.15:35:05.42#ibcon#read 6, iclass 6, count 0 2006.285.15:35:05.42#ibcon#end of sib2, iclass 6, count 0 2006.285.15:35:05.42#ibcon#*after write, iclass 6, count 0 2006.285.15:35:05.42#ibcon#*before return 0, iclass 6, count 0 2006.285.15:35:05.42#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:35:05.42#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:35:05.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.15:35:05.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.15:35:05.42$vck44/vblo=3,649.99 2006.285.15:35:05.42#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.15:35:05.42#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.15:35:05.42#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:05.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:35:05.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:35:05.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:35:05.42#ibcon#enter wrdev, iclass 10, count 0 2006.285.15:35:05.42#ibcon#first serial, iclass 10, count 0 2006.285.15:35:05.42#ibcon#enter sib2, iclass 10, count 0 2006.285.15:35:05.42#ibcon#flushed, iclass 10, count 0 2006.285.15:35:05.42#ibcon#about to write, iclass 10, count 0 2006.285.15:35:05.42#ibcon#wrote, iclass 10, count 0 2006.285.15:35:05.67#ibcon#about to read 3, iclass 10, count 0 2006.285.15:35:05.67#ibcon#read 3, iclass 10, count 0 2006.285.15:35:05.67#ibcon#about to read 4, iclass 10, count 0 2006.285.15:35:05.67#ibcon#read 4, iclass 10, count 0 2006.285.15:35:05.67#ibcon#about to read 5, iclass 10, count 0 2006.285.15:35:05.67#ibcon#read 5, iclass 10, count 0 2006.285.15:35:05.67#ibcon#about to read 6, iclass 10, count 0 2006.285.15:35:05.67#ibcon#read 6, iclass 10, count 0 2006.285.15:35:05.67#ibcon#end of sib2, iclass 10, count 0 2006.285.15:35:05.67#ibcon#*mode == 0, iclass 10, count 0 2006.285.15:35:05.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.15:35:05.67#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.15:35:05.67#ibcon#*before write, iclass 10, count 0 2006.285.15:35:05.67#ibcon#enter sib2, iclass 10, count 0 2006.285.15:35:05.67#ibcon#flushed, iclass 10, count 0 2006.285.15:35:05.67#ibcon#about to write, iclass 10, count 0 2006.285.15:35:05.67#ibcon#wrote, iclass 10, count 0 2006.285.15:35:05.67#ibcon#about to read 3, iclass 10, count 0 2006.285.15:35:05.71#ibcon#read 3, iclass 10, count 0 2006.285.15:35:05.71#ibcon#about to read 4, iclass 10, count 0 2006.285.15:35:05.71#ibcon#read 4, iclass 10, count 0 2006.285.15:35:05.71#ibcon#about to read 5, iclass 10, count 0 2006.285.15:35:05.71#ibcon#read 5, iclass 10, count 0 2006.285.15:35:05.71#ibcon#about to read 6, iclass 10, count 0 2006.285.15:35:05.71#ibcon#read 6, iclass 10, count 0 2006.285.15:35:05.71#ibcon#end of sib2, iclass 10, count 0 2006.285.15:35:05.71#ibcon#*after write, iclass 10, count 0 2006.285.15:35:05.71#ibcon#*before return 0, iclass 10, count 0 2006.285.15:35:05.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:35:05.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:35:05.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.15:35:05.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.15:35:05.71$vck44/vb=3,4 2006.285.15:35:05.71#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.15:35:05.71#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.15:35:05.71#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:05.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:35:05.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:35:05.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:35:05.71#ibcon#enter wrdev, iclass 12, count 2 2006.285.15:35:05.71#ibcon#first serial, iclass 12, count 2 2006.285.15:35:05.71#ibcon#enter sib2, iclass 12, count 2 2006.285.15:35:05.71#ibcon#flushed, iclass 12, count 2 2006.285.15:35:05.71#ibcon#about to write, iclass 12, count 2 2006.285.15:35:05.71#ibcon#wrote, iclass 12, count 2 2006.285.15:35:05.71#ibcon#about to read 3, iclass 12, count 2 2006.285.15:35:05.73#ibcon#read 3, iclass 12, count 2 2006.285.15:35:05.73#ibcon#about to read 4, iclass 12, count 2 2006.285.15:35:05.73#ibcon#read 4, iclass 12, count 2 2006.285.15:35:05.73#ibcon#about to read 5, iclass 12, count 2 2006.285.15:35:05.73#ibcon#read 5, iclass 12, count 2 2006.285.15:35:05.73#ibcon#about to read 6, iclass 12, count 2 2006.285.15:35:05.73#ibcon#read 6, iclass 12, count 2 2006.285.15:35:05.73#ibcon#end of sib2, iclass 12, count 2 2006.285.15:35:05.73#ibcon#*mode == 0, iclass 12, count 2 2006.285.15:35:05.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.15:35:05.73#ibcon#[27=AT03-04\r\n] 2006.285.15:35:05.73#ibcon#*before write, iclass 12, count 2 2006.285.15:35:05.73#ibcon#enter sib2, iclass 12, count 2 2006.285.15:35:05.73#ibcon#flushed, iclass 12, count 2 2006.285.15:35:05.73#ibcon#about to write, iclass 12, count 2 2006.285.15:35:05.73#ibcon#wrote, iclass 12, count 2 2006.285.15:35:05.73#ibcon#about to read 3, iclass 12, count 2 2006.285.15:35:05.76#ibcon#read 3, iclass 12, count 2 2006.285.15:35:05.76#ibcon#about to read 4, iclass 12, count 2 2006.285.15:35:05.76#ibcon#read 4, iclass 12, count 2 2006.285.15:35:05.76#ibcon#about to read 5, iclass 12, count 2 2006.285.15:35:05.76#ibcon#read 5, iclass 12, count 2 2006.285.15:35:05.76#ibcon#about to read 6, iclass 12, count 2 2006.285.15:35:05.76#ibcon#read 6, iclass 12, count 2 2006.285.15:35:05.76#ibcon#end of sib2, iclass 12, count 2 2006.285.15:35:05.76#ibcon#*after write, iclass 12, count 2 2006.285.15:35:05.76#ibcon#*before return 0, iclass 12, count 2 2006.285.15:35:05.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:35:05.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:35:05.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.15:35:05.76#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:05.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:35:05.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:35:05.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:35:05.88#ibcon#enter wrdev, iclass 12, count 0 2006.285.15:35:05.88#ibcon#first serial, iclass 12, count 0 2006.285.15:35:05.88#ibcon#enter sib2, iclass 12, count 0 2006.285.15:35:05.88#ibcon#flushed, iclass 12, count 0 2006.285.15:35:05.88#ibcon#about to write, iclass 12, count 0 2006.285.15:35:05.88#ibcon#wrote, iclass 12, count 0 2006.285.15:35:05.88#ibcon#about to read 3, iclass 12, count 0 2006.285.15:35:05.90#ibcon#read 3, iclass 12, count 0 2006.285.15:35:05.90#ibcon#about to read 4, iclass 12, count 0 2006.285.15:35:05.90#ibcon#read 4, iclass 12, count 0 2006.285.15:35:05.90#ibcon#about to read 5, iclass 12, count 0 2006.285.15:35:05.90#ibcon#read 5, iclass 12, count 0 2006.285.15:35:05.90#ibcon#about to read 6, iclass 12, count 0 2006.285.15:35:05.90#ibcon#read 6, iclass 12, count 0 2006.285.15:35:05.90#ibcon#end of sib2, iclass 12, count 0 2006.285.15:35:05.90#ibcon#*mode == 0, iclass 12, count 0 2006.285.15:35:05.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.15:35:05.90#ibcon#[27=USB\r\n] 2006.285.15:35:05.90#ibcon#*before write, iclass 12, count 0 2006.285.15:35:05.90#ibcon#enter sib2, iclass 12, count 0 2006.285.15:35:05.90#ibcon#flushed, iclass 12, count 0 2006.285.15:35:05.90#ibcon#about to write, iclass 12, count 0 2006.285.15:35:05.90#ibcon#wrote, iclass 12, count 0 2006.285.15:35:05.90#ibcon#about to read 3, iclass 12, count 0 2006.285.15:35:05.93#ibcon#read 3, iclass 12, count 0 2006.285.15:35:05.93#ibcon#about to read 4, iclass 12, count 0 2006.285.15:35:05.93#ibcon#read 4, iclass 12, count 0 2006.285.15:35:05.93#ibcon#about to read 5, iclass 12, count 0 2006.285.15:35:05.93#ibcon#read 5, iclass 12, count 0 2006.285.15:35:05.93#ibcon#about to read 6, iclass 12, count 0 2006.285.15:35:05.93#ibcon#read 6, iclass 12, count 0 2006.285.15:35:05.93#ibcon#end of sib2, iclass 12, count 0 2006.285.15:35:05.93#ibcon#*after write, iclass 12, count 0 2006.285.15:35:05.93#ibcon#*before return 0, iclass 12, count 0 2006.285.15:35:05.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:35:05.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:35:05.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.15:35:05.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.15:35:05.93$vck44/vblo=4,679.99 2006.285.15:35:05.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.15:35:05.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.15:35:05.93#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:05.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:35:05.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:35:05.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:35:05.93#ibcon#enter wrdev, iclass 14, count 0 2006.285.15:35:05.93#ibcon#first serial, iclass 14, count 0 2006.285.15:35:05.93#ibcon#enter sib2, iclass 14, count 0 2006.285.15:35:05.93#ibcon#flushed, iclass 14, count 0 2006.285.15:35:05.93#ibcon#about to write, iclass 14, count 0 2006.285.15:35:05.93#ibcon#wrote, iclass 14, count 0 2006.285.15:35:05.93#ibcon#about to read 3, iclass 14, count 0 2006.285.15:35:05.95#ibcon#read 3, iclass 14, count 0 2006.285.15:35:05.95#ibcon#about to read 4, iclass 14, count 0 2006.285.15:35:05.95#ibcon#read 4, iclass 14, count 0 2006.285.15:35:05.95#ibcon#about to read 5, iclass 14, count 0 2006.285.15:35:05.95#ibcon#read 5, iclass 14, count 0 2006.285.15:35:05.95#ibcon#about to read 6, iclass 14, count 0 2006.285.15:35:05.95#ibcon#read 6, iclass 14, count 0 2006.285.15:35:05.95#ibcon#end of sib2, iclass 14, count 0 2006.285.15:35:05.95#ibcon#*mode == 0, iclass 14, count 0 2006.285.15:35:05.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.15:35:05.95#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.15:35:05.95#ibcon#*before write, iclass 14, count 0 2006.285.15:35:05.95#ibcon#enter sib2, iclass 14, count 0 2006.285.15:35:05.95#ibcon#flushed, iclass 14, count 0 2006.285.15:35:05.95#ibcon#about to write, iclass 14, count 0 2006.285.15:35:05.95#ibcon#wrote, iclass 14, count 0 2006.285.15:35:05.95#ibcon#about to read 3, iclass 14, count 0 2006.285.15:35:05.99#ibcon#read 3, iclass 14, count 0 2006.285.15:35:05.99#ibcon#about to read 4, iclass 14, count 0 2006.285.15:35:05.99#ibcon#read 4, iclass 14, count 0 2006.285.15:35:05.99#ibcon#about to read 5, iclass 14, count 0 2006.285.15:35:05.99#ibcon#read 5, iclass 14, count 0 2006.285.15:35:05.99#ibcon#about to read 6, iclass 14, count 0 2006.285.15:35:05.99#ibcon#read 6, iclass 14, count 0 2006.285.15:35:05.99#ibcon#end of sib2, iclass 14, count 0 2006.285.15:35:05.99#ibcon#*after write, iclass 14, count 0 2006.285.15:35:05.99#ibcon#*before return 0, iclass 14, count 0 2006.285.15:35:05.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:35:05.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:35:05.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.15:35:05.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.15:35:05.99$vck44/vb=4,5 2006.285.15:35:05.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.15:35:05.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.15:35:05.99#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:05.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:35:06.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:35:06.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:35:06.05#ibcon#enter wrdev, iclass 16, count 2 2006.285.15:35:06.05#ibcon#first serial, iclass 16, count 2 2006.285.15:35:06.05#ibcon#enter sib2, iclass 16, count 2 2006.285.15:35:06.05#ibcon#flushed, iclass 16, count 2 2006.285.15:35:06.05#ibcon#about to write, iclass 16, count 2 2006.285.15:35:06.05#ibcon#wrote, iclass 16, count 2 2006.285.15:35:06.05#ibcon#about to read 3, iclass 16, count 2 2006.285.15:35:06.07#ibcon#read 3, iclass 16, count 2 2006.285.15:35:06.07#ibcon#about to read 4, iclass 16, count 2 2006.285.15:35:06.07#ibcon#read 4, iclass 16, count 2 2006.285.15:35:06.07#ibcon#about to read 5, iclass 16, count 2 2006.285.15:35:06.07#ibcon#read 5, iclass 16, count 2 2006.285.15:35:06.07#ibcon#about to read 6, iclass 16, count 2 2006.285.15:35:06.07#ibcon#read 6, iclass 16, count 2 2006.285.15:35:06.07#ibcon#end of sib2, iclass 16, count 2 2006.285.15:35:06.07#ibcon#*mode == 0, iclass 16, count 2 2006.285.15:35:06.07#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.15:35:06.07#ibcon#[27=AT04-05\r\n] 2006.285.15:35:06.07#ibcon#*before write, iclass 16, count 2 2006.285.15:35:06.07#ibcon#enter sib2, iclass 16, count 2 2006.285.15:35:06.07#ibcon#flushed, iclass 16, count 2 2006.285.15:35:06.07#ibcon#about to write, iclass 16, count 2 2006.285.15:35:06.07#ibcon#wrote, iclass 16, count 2 2006.285.15:35:06.07#ibcon#about to read 3, iclass 16, count 2 2006.285.15:35:06.10#ibcon#read 3, iclass 16, count 2 2006.285.15:35:06.10#ibcon#about to read 4, iclass 16, count 2 2006.285.15:35:06.10#ibcon#read 4, iclass 16, count 2 2006.285.15:35:06.10#ibcon#about to read 5, iclass 16, count 2 2006.285.15:35:06.10#ibcon#read 5, iclass 16, count 2 2006.285.15:35:06.10#ibcon#about to read 6, iclass 16, count 2 2006.285.15:35:06.10#ibcon#read 6, iclass 16, count 2 2006.285.15:35:06.10#ibcon#end of sib2, iclass 16, count 2 2006.285.15:35:06.10#ibcon#*after write, iclass 16, count 2 2006.285.15:35:06.10#ibcon#*before return 0, iclass 16, count 2 2006.285.15:35:06.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:35:06.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:35:06.10#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.15:35:06.10#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:06.10#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:35:06.22#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:35:06.22#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:35:06.22#ibcon#enter wrdev, iclass 16, count 0 2006.285.15:35:06.22#ibcon#first serial, iclass 16, count 0 2006.285.15:35:06.22#ibcon#enter sib2, iclass 16, count 0 2006.285.15:35:06.22#ibcon#flushed, iclass 16, count 0 2006.285.15:35:06.22#ibcon#about to write, iclass 16, count 0 2006.285.15:35:06.22#ibcon#wrote, iclass 16, count 0 2006.285.15:35:06.22#ibcon#about to read 3, iclass 16, count 0 2006.285.15:35:06.24#ibcon#read 3, iclass 16, count 0 2006.285.15:35:06.24#ibcon#about to read 4, iclass 16, count 0 2006.285.15:35:06.24#ibcon#read 4, iclass 16, count 0 2006.285.15:35:06.24#ibcon#about to read 5, iclass 16, count 0 2006.285.15:35:06.24#ibcon#read 5, iclass 16, count 0 2006.285.15:35:06.24#ibcon#about to read 6, iclass 16, count 0 2006.285.15:35:06.24#ibcon#read 6, iclass 16, count 0 2006.285.15:35:06.24#ibcon#end of sib2, iclass 16, count 0 2006.285.15:35:06.24#ibcon#*mode == 0, iclass 16, count 0 2006.285.15:35:06.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.15:35:06.24#ibcon#[27=USB\r\n] 2006.285.15:35:06.24#ibcon#*before write, iclass 16, count 0 2006.285.15:35:06.24#ibcon#enter sib2, iclass 16, count 0 2006.285.15:35:06.24#ibcon#flushed, iclass 16, count 0 2006.285.15:35:06.24#ibcon#about to write, iclass 16, count 0 2006.285.15:35:06.24#ibcon#wrote, iclass 16, count 0 2006.285.15:35:06.24#ibcon#about to read 3, iclass 16, count 0 2006.285.15:35:06.27#ibcon#read 3, iclass 16, count 0 2006.285.15:35:06.27#ibcon#about to read 4, iclass 16, count 0 2006.285.15:35:06.27#ibcon#read 4, iclass 16, count 0 2006.285.15:35:06.27#ibcon#about to read 5, iclass 16, count 0 2006.285.15:35:06.27#ibcon#read 5, iclass 16, count 0 2006.285.15:35:06.27#ibcon#about to read 6, iclass 16, count 0 2006.285.15:35:06.27#ibcon#read 6, iclass 16, count 0 2006.285.15:35:06.27#ibcon#end of sib2, iclass 16, count 0 2006.285.15:35:06.27#ibcon#*after write, iclass 16, count 0 2006.285.15:35:06.27#ibcon#*before return 0, iclass 16, count 0 2006.285.15:35:06.27#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:35:06.27#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:35:06.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.15:35:06.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.15:35:06.27$vck44/vblo=5,709.99 2006.285.15:35:06.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.15:35:06.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.15:35:06.27#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:06.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:35:06.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:35:06.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:35:06.27#ibcon#enter wrdev, iclass 18, count 0 2006.285.15:35:06.27#ibcon#first serial, iclass 18, count 0 2006.285.15:35:06.27#ibcon#enter sib2, iclass 18, count 0 2006.285.15:35:06.27#ibcon#flushed, iclass 18, count 0 2006.285.15:35:06.27#ibcon#about to write, iclass 18, count 0 2006.285.15:35:06.27#ibcon#wrote, iclass 18, count 0 2006.285.15:35:06.27#ibcon#about to read 3, iclass 18, count 0 2006.285.15:35:06.29#ibcon#read 3, iclass 18, count 0 2006.285.15:35:06.29#ibcon#about to read 4, iclass 18, count 0 2006.285.15:35:06.29#ibcon#read 4, iclass 18, count 0 2006.285.15:35:06.29#ibcon#about to read 5, iclass 18, count 0 2006.285.15:35:06.29#ibcon#read 5, iclass 18, count 0 2006.285.15:35:06.29#ibcon#about to read 6, iclass 18, count 0 2006.285.15:35:06.29#ibcon#read 6, iclass 18, count 0 2006.285.15:35:06.29#ibcon#end of sib2, iclass 18, count 0 2006.285.15:35:06.29#ibcon#*mode == 0, iclass 18, count 0 2006.285.15:35:06.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.15:35:06.29#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.15:35:06.29#ibcon#*before write, iclass 18, count 0 2006.285.15:35:06.29#ibcon#enter sib2, iclass 18, count 0 2006.285.15:35:06.29#ibcon#flushed, iclass 18, count 0 2006.285.15:35:06.29#ibcon#about to write, iclass 18, count 0 2006.285.15:35:06.29#ibcon#wrote, iclass 18, count 0 2006.285.15:35:06.29#ibcon#about to read 3, iclass 18, count 0 2006.285.15:35:06.33#ibcon#read 3, iclass 18, count 0 2006.285.15:35:06.33#ibcon#about to read 4, iclass 18, count 0 2006.285.15:35:06.33#ibcon#read 4, iclass 18, count 0 2006.285.15:35:06.33#ibcon#about to read 5, iclass 18, count 0 2006.285.15:35:06.33#ibcon#read 5, iclass 18, count 0 2006.285.15:35:06.33#ibcon#about to read 6, iclass 18, count 0 2006.285.15:35:06.33#ibcon#read 6, iclass 18, count 0 2006.285.15:35:06.33#ibcon#end of sib2, iclass 18, count 0 2006.285.15:35:06.33#ibcon#*after write, iclass 18, count 0 2006.285.15:35:06.33#ibcon#*before return 0, iclass 18, count 0 2006.285.15:35:06.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:35:06.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:35:06.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.15:35:06.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.15:35:06.33$vck44/vb=5,4 2006.285.15:35:06.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.15:35:06.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.15:35:06.33#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:06.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:35:06.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:35:06.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:35:06.39#ibcon#enter wrdev, iclass 20, count 2 2006.285.15:35:06.39#ibcon#first serial, iclass 20, count 2 2006.285.15:35:06.39#ibcon#enter sib2, iclass 20, count 2 2006.285.15:35:06.39#ibcon#flushed, iclass 20, count 2 2006.285.15:35:06.39#ibcon#about to write, iclass 20, count 2 2006.285.15:35:06.39#ibcon#wrote, iclass 20, count 2 2006.285.15:35:06.39#ibcon#about to read 3, iclass 20, count 2 2006.285.15:35:06.41#ibcon#read 3, iclass 20, count 2 2006.285.15:35:06.41#ibcon#about to read 4, iclass 20, count 2 2006.285.15:35:06.41#ibcon#read 4, iclass 20, count 2 2006.285.15:35:06.41#ibcon#about to read 5, iclass 20, count 2 2006.285.15:35:06.41#ibcon#read 5, iclass 20, count 2 2006.285.15:35:06.41#ibcon#about to read 6, iclass 20, count 2 2006.285.15:35:06.41#ibcon#read 6, iclass 20, count 2 2006.285.15:35:06.41#ibcon#end of sib2, iclass 20, count 2 2006.285.15:35:06.41#ibcon#*mode == 0, iclass 20, count 2 2006.285.15:35:06.41#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.15:35:06.41#ibcon#[27=AT05-04\r\n] 2006.285.15:35:06.41#ibcon#*before write, iclass 20, count 2 2006.285.15:35:06.41#ibcon#enter sib2, iclass 20, count 2 2006.285.15:35:06.41#ibcon#flushed, iclass 20, count 2 2006.285.15:35:06.41#ibcon#about to write, iclass 20, count 2 2006.285.15:35:06.41#ibcon#wrote, iclass 20, count 2 2006.285.15:35:06.41#ibcon#about to read 3, iclass 20, count 2 2006.285.15:35:06.44#ibcon#read 3, iclass 20, count 2 2006.285.15:35:06.44#ibcon#about to read 4, iclass 20, count 2 2006.285.15:35:06.44#ibcon#read 4, iclass 20, count 2 2006.285.15:35:06.44#ibcon#about to read 5, iclass 20, count 2 2006.285.15:35:06.44#ibcon#read 5, iclass 20, count 2 2006.285.15:35:06.44#ibcon#about to read 6, iclass 20, count 2 2006.285.15:35:06.44#ibcon#read 6, iclass 20, count 2 2006.285.15:35:06.44#ibcon#end of sib2, iclass 20, count 2 2006.285.15:35:06.44#ibcon#*after write, iclass 20, count 2 2006.285.15:35:06.44#ibcon#*before return 0, iclass 20, count 2 2006.285.15:35:06.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:35:06.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:35:06.44#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.15:35:06.44#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:06.44#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:35:06.56#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:35:06.56#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:35:06.56#ibcon#enter wrdev, iclass 20, count 0 2006.285.15:35:06.56#ibcon#first serial, iclass 20, count 0 2006.285.15:35:06.56#ibcon#enter sib2, iclass 20, count 0 2006.285.15:35:06.56#ibcon#flushed, iclass 20, count 0 2006.285.15:35:06.56#ibcon#about to write, iclass 20, count 0 2006.285.15:35:06.56#ibcon#wrote, iclass 20, count 0 2006.285.15:35:06.56#ibcon#about to read 3, iclass 20, count 0 2006.285.15:35:06.58#ibcon#read 3, iclass 20, count 0 2006.285.15:35:06.58#ibcon#about to read 4, iclass 20, count 0 2006.285.15:35:06.58#ibcon#read 4, iclass 20, count 0 2006.285.15:35:06.58#ibcon#about to read 5, iclass 20, count 0 2006.285.15:35:06.58#ibcon#read 5, iclass 20, count 0 2006.285.15:35:06.58#ibcon#about to read 6, iclass 20, count 0 2006.285.15:35:06.58#ibcon#read 6, iclass 20, count 0 2006.285.15:35:06.58#ibcon#end of sib2, iclass 20, count 0 2006.285.15:35:06.58#ibcon#*mode == 0, iclass 20, count 0 2006.285.15:35:06.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.15:35:06.58#ibcon#[27=USB\r\n] 2006.285.15:35:06.58#ibcon#*before write, iclass 20, count 0 2006.285.15:35:06.58#ibcon#enter sib2, iclass 20, count 0 2006.285.15:35:06.58#ibcon#flushed, iclass 20, count 0 2006.285.15:35:06.58#ibcon#about to write, iclass 20, count 0 2006.285.15:35:06.58#ibcon#wrote, iclass 20, count 0 2006.285.15:35:06.58#ibcon#about to read 3, iclass 20, count 0 2006.285.15:35:06.61#ibcon#read 3, iclass 20, count 0 2006.285.15:35:06.61#ibcon#about to read 4, iclass 20, count 0 2006.285.15:35:06.61#ibcon#read 4, iclass 20, count 0 2006.285.15:35:06.61#ibcon#about to read 5, iclass 20, count 0 2006.285.15:35:06.61#ibcon#read 5, iclass 20, count 0 2006.285.15:35:06.61#ibcon#about to read 6, iclass 20, count 0 2006.285.15:35:06.61#ibcon#read 6, iclass 20, count 0 2006.285.15:35:06.61#ibcon#end of sib2, iclass 20, count 0 2006.285.15:35:06.61#ibcon#*after write, iclass 20, count 0 2006.285.15:35:06.61#ibcon#*before return 0, iclass 20, count 0 2006.285.15:35:06.61#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:35:06.61#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:35:06.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.15:35:06.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.15:35:06.61$vck44/vblo=6,719.99 2006.285.15:35:06.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.15:35:06.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.15:35:06.61#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:06.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:35:06.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:35:06.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:35:06.61#ibcon#enter wrdev, iclass 22, count 0 2006.285.15:35:06.61#ibcon#first serial, iclass 22, count 0 2006.285.15:35:06.61#ibcon#enter sib2, iclass 22, count 0 2006.285.15:35:06.61#ibcon#flushed, iclass 22, count 0 2006.285.15:35:06.61#ibcon#about to write, iclass 22, count 0 2006.285.15:35:06.61#ibcon#wrote, iclass 22, count 0 2006.285.15:35:06.61#ibcon#about to read 3, iclass 22, count 0 2006.285.15:35:06.63#ibcon#read 3, iclass 22, count 0 2006.285.15:35:06.63#ibcon#about to read 4, iclass 22, count 0 2006.285.15:35:06.63#ibcon#read 4, iclass 22, count 0 2006.285.15:35:06.63#ibcon#about to read 5, iclass 22, count 0 2006.285.15:35:06.63#ibcon#read 5, iclass 22, count 0 2006.285.15:35:06.63#ibcon#about to read 6, iclass 22, count 0 2006.285.15:35:06.63#ibcon#read 6, iclass 22, count 0 2006.285.15:35:06.63#ibcon#end of sib2, iclass 22, count 0 2006.285.15:35:06.63#ibcon#*mode == 0, iclass 22, count 0 2006.285.15:35:06.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.15:35:06.63#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.15:35:06.63#ibcon#*before write, iclass 22, count 0 2006.285.15:35:06.63#ibcon#enter sib2, iclass 22, count 0 2006.285.15:35:06.63#ibcon#flushed, iclass 22, count 0 2006.285.15:35:06.63#ibcon#about to write, iclass 22, count 0 2006.285.15:35:06.63#ibcon#wrote, iclass 22, count 0 2006.285.15:35:06.63#ibcon#about to read 3, iclass 22, count 0 2006.285.15:35:06.67#ibcon#read 3, iclass 22, count 0 2006.285.15:35:06.67#ibcon#about to read 4, iclass 22, count 0 2006.285.15:35:06.67#ibcon#read 4, iclass 22, count 0 2006.285.15:35:06.67#ibcon#about to read 5, iclass 22, count 0 2006.285.15:35:06.67#ibcon#read 5, iclass 22, count 0 2006.285.15:35:06.67#ibcon#about to read 6, iclass 22, count 0 2006.285.15:35:06.67#ibcon#read 6, iclass 22, count 0 2006.285.15:35:06.67#ibcon#end of sib2, iclass 22, count 0 2006.285.15:35:06.67#ibcon#*after write, iclass 22, count 0 2006.285.15:35:06.67#ibcon#*before return 0, iclass 22, count 0 2006.285.15:35:06.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:35:06.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:35:06.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.15:35:06.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.15:35:06.67$vck44/vb=6,3 2006.285.15:35:06.67#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.15:35:06.67#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.15:35:06.67#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:06.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:35:06.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:35:06.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:35:06.73#ibcon#enter wrdev, iclass 24, count 2 2006.285.15:35:06.73#ibcon#first serial, iclass 24, count 2 2006.285.15:35:06.73#ibcon#enter sib2, iclass 24, count 2 2006.285.15:35:06.73#ibcon#flushed, iclass 24, count 2 2006.285.15:35:06.73#ibcon#about to write, iclass 24, count 2 2006.285.15:35:06.73#ibcon#wrote, iclass 24, count 2 2006.285.15:35:06.73#ibcon#about to read 3, iclass 24, count 2 2006.285.15:35:06.75#ibcon#read 3, iclass 24, count 2 2006.285.15:35:06.75#ibcon#about to read 4, iclass 24, count 2 2006.285.15:35:06.75#ibcon#read 4, iclass 24, count 2 2006.285.15:35:06.75#ibcon#about to read 5, iclass 24, count 2 2006.285.15:35:06.75#ibcon#read 5, iclass 24, count 2 2006.285.15:35:06.75#ibcon#about to read 6, iclass 24, count 2 2006.285.15:35:06.75#ibcon#read 6, iclass 24, count 2 2006.285.15:35:06.75#ibcon#end of sib2, iclass 24, count 2 2006.285.15:35:06.75#ibcon#*mode == 0, iclass 24, count 2 2006.285.15:35:06.75#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.15:35:06.75#ibcon#[27=AT06-03\r\n] 2006.285.15:35:06.75#ibcon#*before write, iclass 24, count 2 2006.285.15:35:06.75#ibcon#enter sib2, iclass 24, count 2 2006.285.15:35:06.75#ibcon#flushed, iclass 24, count 2 2006.285.15:35:06.75#ibcon#about to write, iclass 24, count 2 2006.285.15:35:06.75#ibcon#wrote, iclass 24, count 2 2006.285.15:35:06.75#ibcon#about to read 3, iclass 24, count 2 2006.285.15:35:06.78#ibcon#read 3, iclass 24, count 2 2006.285.15:35:06.78#ibcon#about to read 4, iclass 24, count 2 2006.285.15:35:06.78#ibcon#read 4, iclass 24, count 2 2006.285.15:35:06.78#ibcon#about to read 5, iclass 24, count 2 2006.285.15:35:06.78#ibcon#read 5, iclass 24, count 2 2006.285.15:35:06.78#ibcon#about to read 6, iclass 24, count 2 2006.285.15:35:06.78#ibcon#read 6, iclass 24, count 2 2006.285.15:35:06.78#ibcon#end of sib2, iclass 24, count 2 2006.285.15:35:06.78#ibcon#*after write, iclass 24, count 2 2006.285.15:35:06.78#ibcon#*before return 0, iclass 24, count 2 2006.285.15:35:06.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:35:06.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:35:06.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.15:35:06.78#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:06.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:35:06.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:35:06.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:35:06.90#ibcon#enter wrdev, iclass 24, count 0 2006.285.15:35:06.90#ibcon#first serial, iclass 24, count 0 2006.285.15:35:06.90#ibcon#enter sib2, iclass 24, count 0 2006.285.15:35:06.90#ibcon#flushed, iclass 24, count 0 2006.285.15:35:06.90#ibcon#about to write, iclass 24, count 0 2006.285.15:35:06.90#ibcon#wrote, iclass 24, count 0 2006.285.15:35:06.90#ibcon#about to read 3, iclass 24, count 0 2006.285.15:35:06.92#ibcon#read 3, iclass 24, count 0 2006.285.15:35:06.92#ibcon#about to read 4, iclass 24, count 0 2006.285.15:35:06.92#ibcon#read 4, iclass 24, count 0 2006.285.15:35:06.92#ibcon#about to read 5, iclass 24, count 0 2006.285.15:35:06.92#ibcon#read 5, iclass 24, count 0 2006.285.15:35:06.92#ibcon#about to read 6, iclass 24, count 0 2006.285.15:35:06.92#ibcon#read 6, iclass 24, count 0 2006.285.15:35:06.92#ibcon#end of sib2, iclass 24, count 0 2006.285.15:35:06.92#ibcon#*mode == 0, iclass 24, count 0 2006.285.15:35:06.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.15:35:06.92#ibcon#[27=USB\r\n] 2006.285.15:35:06.92#ibcon#*before write, iclass 24, count 0 2006.285.15:35:06.92#ibcon#enter sib2, iclass 24, count 0 2006.285.15:35:06.92#ibcon#flushed, iclass 24, count 0 2006.285.15:35:06.92#ibcon#about to write, iclass 24, count 0 2006.285.15:35:06.92#ibcon#wrote, iclass 24, count 0 2006.285.15:35:06.92#ibcon#about to read 3, iclass 24, count 0 2006.285.15:35:06.95#ibcon#read 3, iclass 24, count 0 2006.285.15:35:06.95#ibcon#about to read 4, iclass 24, count 0 2006.285.15:35:06.95#ibcon#read 4, iclass 24, count 0 2006.285.15:35:06.95#ibcon#about to read 5, iclass 24, count 0 2006.285.15:35:06.95#ibcon#read 5, iclass 24, count 0 2006.285.15:35:06.95#ibcon#about to read 6, iclass 24, count 0 2006.285.15:35:06.95#ibcon#read 6, iclass 24, count 0 2006.285.15:35:06.95#ibcon#end of sib2, iclass 24, count 0 2006.285.15:35:06.95#ibcon#*after write, iclass 24, count 0 2006.285.15:35:06.95#ibcon#*before return 0, iclass 24, count 0 2006.285.15:35:06.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:35:06.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:35:06.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.15:35:06.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.15:35:06.95$vck44/vblo=7,734.99 2006.285.15:35:06.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.15:35:06.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.15:35:06.95#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:06.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:35:06.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:35:06.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:35:06.95#ibcon#enter wrdev, iclass 26, count 0 2006.285.15:35:06.95#ibcon#first serial, iclass 26, count 0 2006.285.15:35:06.95#ibcon#enter sib2, iclass 26, count 0 2006.285.15:35:06.95#ibcon#flushed, iclass 26, count 0 2006.285.15:35:06.95#ibcon#about to write, iclass 26, count 0 2006.285.15:35:06.95#ibcon#wrote, iclass 26, count 0 2006.285.15:35:06.95#ibcon#about to read 3, iclass 26, count 0 2006.285.15:35:06.97#ibcon#read 3, iclass 26, count 0 2006.285.15:35:06.97#ibcon#about to read 4, iclass 26, count 0 2006.285.15:35:06.97#ibcon#read 4, iclass 26, count 0 2006.285.15:35:06.97#ibcon#about to read 5, iclass 26, count 0 2006.285.15:35:06.97#ibcon#read 5, iclass 26, count 0 2006.285.15:35:06.97#ibcon#about to read 6, iclass 26, count 0 2006.285.15:35:06.97#ibcon#read 6, iclass 26, count 0 2006.285.15:35:06.97#ibcon#end of sib2, iclass 26, count 0 2006.285.15:35:06.97#ibcon#*mode == 0, iclass 26, count 0 2006.285.15:35:06.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.15:35:06.97#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.15:35:06.97#ibcon#*before write, iclass 26, count 0 2006.285.15:35:06.97#ibcon#enter sib2, iclass 26, count 0 2006.285.15:35:06.97#ibcon#flushed, iclass 26, count 0 2006.285.15:35:06.97#ibcon#about to write, iclass 26, count 0 2006.285.15:35:06.97#ibcon#wrote, iclass 26, count 0 2006.285.15:35:06.97#ibcon#about to read 3, iclass 26, count 0 2006.285.15:35:07.01#ibcon#read 3, iclass 26, count 0 2006.285.15:35:07.01#ibcon#about to read 4, iclass 26, count 0 2006.285.15:35:07.01#ibcon#read 4, iclass 26, count 0 2006.285.15:35:07.01#ibcon#about to read 5, iclass 26, count 0 2006.285.15:35:07.01#ibcon#read 5, iclass 26, count 0 2006.285.15:35:07.01#ibcon#about to read 6, iclass 26, count 0 2006.285.15:35:07.01#ibcon#read 6, iclass 26, count 0 2006.285.15:35:07.01#ibcon#end of sib2, iclass 26, count 0 2006.285.15:35:07.01#ibcon#*after write, iclass 26, count 0 2006.285.15:35:07.01#ibcon#*before return 0, iclass 26, count 0 2006.285.15:35:07.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:35:07.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:35:07.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.15:35:07.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.15:35:07.01$vck44/vb=7,4 2006.285.15:35:07.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.15:35:07.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.15:35:07.01#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:07.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:35:07.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:35:07.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:35:07.07#ibcon#enter wrdev, iclass 28, count 2 2006.285.15:35:07.07#ibcon#first serial, iclass 28, count 2 2006.285.15:35:07.07#ibcon#enter sib2, iclass 28, count 2 2006.285.15:35:07.07#ibcon#flushed, iclass 28, count 2 2006.285.15:35:07.07#ibcon#about to write, iclass 28, count 2 2006.285.15:35:07.07#ibcon#wrote, iclass 28, count 2 2006.285.15:35:07.07#ibcon#about to read 3, iclass 28, count 2 2006.285.15:35:07.09#ibcon#read 3, iclass 28, count 2 2006.285.15:35:07.09#ibcon#about to read 4, iclass 28, count 2 2006.285.15:35:07.09#ibcon#read 4, iclass 28, count 2 2006.285.15:35:07.09#ibcon#about to read 5, iclass 28, count 2 2006.285.15:35:07.09#ibcon#read 5, iclass 28, count 2 2006.285.15:35:07.09#ibcon#about to read 6, iclass 28, count 2 2006.285.15:35:07.09#ibcon#read 6, iclass 28, count 2 2006.285.15:35:07.09#ibcon#end of sib2, iclass 28, count 2 2006.285.15:35:07.09#ibcon#*mode == 0, iclass 28, count 2 2006.285.15:35:07.09#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.15:35:07.09#ibcon#[27=AT07-04\r\n] 2006.285.15:35:07.09#ibcon#*before write, iclass 28, count 2 2006.285.15:35:07.09#ibcon#enter sib2, iclass 28, count 2 2006.285.15:35:07.09#ibcon#flushed, iclass 28, count 2 2006.285.15:35:07.09#ibcon#about to write, iclass 28, count 2 2006.285.15:35:07.09#ibcon#wrote, iclass 28, count 2 2006.285.15:35:07.09#ibcon#about to read 3, iclass 28, count 2 2006.285.15:35:07.12#ibcon#read 3, iclass 28, count 2 2006.285.15:35:07.12#ibcon#about to read 4, iclass 28, count 2 2006.285.15:35:07.12#ibcon#read 4, iclass 28, count 2 2006.285.15:35:07.12#ibcon#about to read 5, iclass 28, count 2 2006.285.15:35:07.12#ibcon#read 5, iclass 28, count 2 2006.285.15:35:07.12#ibcon#about to read 6, iclass 28, count 2 2006.285.15:35:07.12#ibcon#read 6, iclass 28, count 2 2006.285.15:35:07.12#ibcon#end of sib2, iclass 28, count 2 2006.285.15:35:07.12#ibcon#*after write, iclass 28, count 2 2006.285.15:35:07.12#ibcon#*before return 0, iclass 28, count 2 2006.285.15:35:07.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:35:07.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:35:07.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.15:35:07.12#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:07.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:35:07.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:35:07.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:35:07.24#ibcon#enter wrdev, iclass 28, count 0 2006.285.15:35:07.24#ibcon#first serial, iclass 28, count 0 2006.285.15:35:07.24#ibcon#enter sib2, iclass 28, count 0 2006.285.15:35:07.24#ibcon#flushed, iclass 28, count 0 2006.285.15:35:07.24#ibcon#about to write, iclass 28, count 0 2006.285.15:35:07.24#ibcon#wrote, iclass 28, count 0 2006.285.15:35:07.24#ibcon#about to read 3, iclass 28, count 0 2006.285.15:35:07.26#ibcon#read 3, iclass 28, count 0 2006.285.15:35:07.26#ibcon#about to read 4, iclass 28, count 0 2006.285.15:35:07.26#ibcon#read 4, iclass 28, count 0 2006.285.15:35:07.26#ibcon#about to read 5, iclass 28, count 0 2006.285.15:35:07.26#ibcon#read 5, iclass 28, count 0 2006.285.15:35:07.26#ibcon#about to read 6, iclass 28, count 0 2006.285.15:35:07.26#ibcon#read 6, iclass 28, count 0 2006.285.15:35:07.26#ibcon#end of sib2, iclass 28, count 0 2006.285.15:35:07.26#ibcon#*mode == 0, iclass 28, count 0 2006.285.15:35:07.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.15:35:07.26#ibcon#[27=USB\r\n] 2006.285.15:35:07.26#ibcon#*before write, iclass 28, count 0 2006.285.15:35:07.26#ibcon#enter sib2, iclass 28, count 0 2006.285.15:35:07.26#ibcon#flushed, iclass 28, count 0 2006.285.15:35:07.26#ibcon#about to write, iclass 28, count 0 2006.285.15:35:07.26#ibcon#wrote, iclass 28, count 0 2006.285.15:35:07.26#ibcon#about to read 3, iclass 28, count 0 2006.285.15:35:07.29#ibcon#read 3, iclass 28, count 0 2006.285.15:35:07.29#ibcon#about to read 4, iclass 28, count 0 2006.285.15:35:07.29#ibcon#read 4, iclass 28, count 0 2006.285.15:35:07.29#ibcon#about to read 5, iclass 28, count 0 2006.285.15:35:07.29#ibcon#read 5, iclass 28, count 0 2006.285.15:35:07.29#ibcon#about to read 6, iclass 28, count 0 2006.285.15:35:07.29#ibcon#read 6, iclass 28, count 0 2006.285.15:35:07.29#ibcon#end of sib2, iclass 28, count 0 2006.285.15:35:07.29#ibcon#*after write, iclass 28, count 0 2006.285.15:35:07.29#ibcon#*before return 0, iclass 28, count 0 2006.285.15:35:07.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:35:07.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:35:07.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.15:35:07.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.15:35:07.29$vck44/vblo=8,744.99 2006.285.15:35:07.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.15:35:07.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.15:35:07.29#ibcon#ireg 17 cls_cnt 0 2006.285.15:35:07.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:35:07.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:35:07.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:35:07.29#ibcon#enter wrdev, iclass 30, count 0 2006.285.15:35:07.29#ibcon#first serial, iclass 30, count 0 2006.285.15:35:07.29#ibcon#enter sib2, iclass 30, count 0 2006.285.15:35:07.29#ibcon#flushed, iclass 30, count 0 2006.285.15:35:07.29#ibcon#about to write, iclass 30, count 0 2006.285.15:35:07.29#ibcon#wrote, iclass 30, count 0 2006.285.15:35:07.29#ibcon#about to read 3, iclass 30, count 0 2006.285.15:35:07.31#ibcon#read 3, iclass 30, count 0 2006.285.15:35:07.31#ibcon#about to read 4, iclass 30, count 0 2006.285.15:35:07.31#ibcon#read 4, iclass 30, count 0 2006.285.15:35:07.31#ibcon#about to read 5, iclass 30, count 0 2006.285.15:35:07.31#ibcon#read 5, iclass 30, count 0 2006.285.15:35:07.31#ibcon#about to read 6, iclass 30, count 0 2006.285.15:35:07.31#ibcon#read 6, iclass 30, count 0 2006.285.15:35:07.31#ibcon#end of sib2, iclass 30, count 0 2006.285.15:35:07.31#ibcon#*mode == 0, iclass 30, count 0 2006.285.15:35:07.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.15:35:07.31#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.15:35:07.31#ibcon#*before write, iclass 30, count 0 2006.285.15:35:07.31#ibcon#enter sib2, iclass 30, count 0 2006.285.15:35:07.31#ibcon#flushed, iclass 30, count 0 2006.285.15:35:07.31#ibcon#about to write, iclass 30, count 0 2006.285.15:35:07.31#ibcon#wrote, iclass 30, count 0 2006.285.15:35:07.31#ibcon#about to read 3, iclass 30, count 0 2006.285.15:35:07.35#ibcon#read 3, iclass 30, count 0 2006.285.15:35:07.35#ibcon#about to read 4, iclass 30, count 0 2006.285.15:35:07.35#ibcon#read 4, iclass 30, count 0 2006.285.15:35:07.35#ibcon#about to read 5, iclass 30, count 0 2006.285.15:35:07.35#ibcon#read 5, iclass 30, count 0 2006.285.15:35:07.35#ibcon#about to read 6, iclass 30, count 0 2006.285.15:35:07.35#ibcon#read 6, iclass 30, count 0 2006.285.15:35:07.35#ibcon#end of sib2, iclass 30, count 0 2006.285.15:35:07.35#ibcon#*after write, iclass 30, count 0 2006.285.15:35:07.35#ibcon#*before return 0, iclass 30, count 0 2006.285.15:35:07.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:35:07.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:35:07.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.15:35:07.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.15:35:07.35$vck44/vb=8,4 2006.285.15:35:07.35#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.15:35:07.35#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.15:35:07.35#ibcon#ireg 11 cls_cnt 2 2006.285.15:35:07.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:35:07.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:35:07.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:35:07.41#ibcon#enter wrdev, iclass 32, count 2 2006.285.15:35:07.41#ibcon#first serial, iclass 32, count 2 2006.285.15:35:07.41#ibcon#enter sib2, iclass 32, count 2 2006.285.15:35:07.41#ibcon#flushed, iclass 32, count 2 2006.285.15:35:07.41#ibcon#about to write, iclass 32, count 2 2006.285.15:35:07.41#ibcon#wrote, iclass 32, count 2 2006.285.15:35:07.41#ibcon#about to read 3, iclass 32, count 2 2006.285.15:35:07.43#ibcon#read 3, iclass 32, count 2 2006.285.15:35:07.43#ibcon#about to read 4, iclass 32, count 2 2006.285.15:35:07.43#ibcon#read 4, iclass 32, count 2 2006.285.15:35:07.43#ibcon#about to read 5, iclass 32, count 2 2006.285.15:35:07.43#ibcon#read 5, iclass 32, count 2 2006.285.15:35:07.43#ibcon#about to read 6, iclass 32, count 2 2006.285.15:35:07.43#ibcon#read 6, iclass 32, count 2 2006.285.15:35:07.43#ibcon#end of sib2, iclass 32, count 2 2006.285.15:35:07.43#ibcon#*mode == 0, iclass 32, count 2 2006.285.15:35:07.43#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.15:35:07.43#ibcon#[27=AT08-04\r\n] 2006.285.15:35:07.43#ibcon#*before write, iclass 32, count 2 2006.285.15:35:07.43#ibcon#enter sib2, iclass 32, count 2 2006.285.15:35:07.43#ibcon#flushed, iclass 32, count 2 2006.285.15:35:07.43#ibcon#about to write, iclass 32, count 2 2006.285.15:35:07.43#ibcon#wrote, iclass 32, count 2 2006.285.15:35:07.43#ibcon#about to read 3, iclass 32, count 2 2006.285.15:35:07.46#ibcon#read 3, iclass 32, count 2 2006.285.15:35:07.46#ibcon#about to read 4, iclass 32, count 2 2006.285.15:35:07.46#ibcon#read 4, iclass 32, count 2 2006.285.15:35:07.46#ibcon#about to read 5, iclass 32, count 2 2006.285.15:35:07.46#ibcon#read 5, iclass 32, count 2 2006.285.15:35:07.46#ibcon#about to read 6, iclass 32, count 2 2006.285.15:35:07.46#ibcon#read 6, iclass 32, count 2 2006.285.15:35:07.46#ibcon#end of sib2, iclass 32, count 2 2006.285.15:35:07.46#ibcon#*after write, iclass 32, count 2 2006.285.15:35:07.46#ibcon#*before return 0, iclass 32, count 2 2006.285.15:35:07.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:35:07.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:35:07.46#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.15:35:07.46#ibcon#ireg 7 cls_cnt 0 2006.285.15:35:07.46#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:35:07.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:35:07.62#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:35:07.62#ibcon#enter wrdev, iclass 32, count 0 2006.285.15:35:07.62#ibcon#first serial, iclass 32, count 0 2006.285.15:35:07.62#ibcon#enter sib2, iclass 32, count 0 2006.285.15:35:07.62#ibcon#flushed, iclass 32, count 0 2006.285.15:35:07.62#ibcon#about to write, iclass 32, count 0 2006.285.15:35:07.62#ibcon#wrote, iclass 32, count 0 2006.285.15:35:07.62#ibcon#about to read 3, iclass 32, count 0 2006.285.15:35:07.63#ibcon#read 3, iclass 32, count 0 2006.285.15:35:07.63#ibcon#about to read 4, iclass 32, count 0 2006.285.15:35:07.63#ibcon#read 4, iclass 32, count 0 2006.285.15:35:07.63#ibcon#about to read 5, iclass 32, count 0 2006.285.15:35:07.63#ibcon#read 5, iclass 32, count 0 2006.285.15:35:07.63#ibcon#about to read 6, iclass 32, count 0 2006.285.15:35:07.63#ibcon#read 6, iclass 32, count 0 2006.285.15:35:07.63#ibcon#end of sib2, iclass 32, count 0 2006.285.15:35:07.63#ibcon#*mode == 0, iclass 32, count 0 2006.285.15:35:07.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.15:35:07.63#ibcon#[27=USB\r\n] 2006.285.15:35:07.63#ibcon#*before write, iclass 32, count 0 2006.285.15:35:07.63#ibcon#enter sib2, iclass 32, count 0 2006.285.15:35:07.63#ibcon#flushed, iclass 32, count 0 2006.285.15:35:07.63#ibcon#about to write, iclass 32, count 0 2006.285.15:35:07.63#ibcon#wrote, iclass 32, count 0 2006.285.15:35:07.63#ibcon#about to read 3, iclass 32, count 0 2006.285.15:35:07.66#ibcon#read 3, iclass 32, count 0 2006.285.15:35:07.66#ibcon#about to read 4, iclass 32, count 0 2006.285.15:35:07.66#ibcon#read 4, iclass 32, count 0 2006.285.15:35:07.66#ibcon#about to read 5, iclass 32, count 0 2006.285.15:35:07.66#ibcon#read 5, iclass 32, count 0 2006.285.15:35:07.66#ibcon#about to read 6, iclass 32, count 0 2006.285.15:35:07.66#ibcon#read 6, iclass 32, count 0 2006.285.15:35:07.66#ibcon#end of sib2, iclass 32, count 0 2006.285.15:35:07.66#ibcon#*after write, iclass 32, count 0 2006.285.15:35:07.66#ibcon#*before return 0, iclass 32, count 0 2006.285.15:35:07.66#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:35:07.66#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:35:07.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.15:35:07.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.15:35:07.66$vck44/vabw=wide 2006.285.15:35:07.66#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.15:35:07.66#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.15:35:07.66#ibcon#ireg 8 cls_cnt 0 2006.285.15:35:07.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:35:07.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:35:07.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:35:07.66#ibcon#enter wrdev, iclass 34, count 0 2006.285.15:35:07.66#ibcon#first serial, iclass 34, count 0 2006.285.15:35:07.66#ibcon#enter sib2, iclass 34, count 0 2006.285.15:35:07.66#ibcon#flushed, iclass 34, count 0 2006.285.15:35:07.66#ibcon#about to write, iclass 34, count 0 2006.285.15:35:07.66#ibcon#wrote, iclass 34, count 0 2006.285.15:35:07.66#ibcon#about to read 3, iclass 34, count 0 2006.285.15:35:07.68#ibcon#read 3, iclass 34, count 0 2006.285.15:35:07.68#ibcon#about to read 4, iclass 34, count 0 2006.285.15:35:07.68#ibcon#read 4, iclass 34, count 0 2006.285.15:35:07.68#ibcon#about to read 5, iclass 34, count 0 2006.285.15:35:07.68#ibcon#read 5, iclass 34, count 0 2006.285.15:35:07.68#ibcon#about to read 6, iclass 34, count 0 2006.285.15:35:07.68#ibcon#read 6, iclass 34, count 0 2006.285.15:35:07.68#ibcon#end of sib2, iclass 34, count 0 2006.285.15:35:07.68#ibcon#*mode == 0, iclass 34, count 0 2006.285.15:35:07.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.15:35:07.68#ibcon#[25=BW32\r\n] 2006.285.15:35:07.68#ibcon#*before write, iclass 34, count 0 2006.285.15:35:07.68#ibcon#enter sib2, iclass 34, count 0 2006.285.15:35:07.68#ibcon#flushed, iclass 34, count 0 2006.285.15:35:07.68#ibcon#about to write, iclass 34, count 0 2006.285.15:35:07.68#ibcon#wrote, iclass 34, count 0 2006.285.15:35:07.68#ibcon#about to read 3, iclass 34, count 0 2006.285.15:35:07.71#ibcon#read 3, iclass 34, count 0 2006.285.15:35:07.71#ibcon#about to read 4, iclass 34, count 0 2006.285.15:35:07.71#ibcon#read 4, iclass 34, count 0 2006.285.15:35:07.71#ibcon#about to read 5, iclass 34, count 0 2006.285.15:35:07.71#ibcon#read 5, iclass 34, count 0 2006.285.15:35:07.71#ibcon#about to read 6, iclass 34, count 0 2006.285.15:35:07.71#ibcon#read 6, iclass 34, count 0 2006.285.15:35:07.71#ibcon#end of sib2, iclass 34, count 0 2006.285.15:35:07.71#ibcon#*after write, iclass 34, count 0 2006.285.15:35:07.71#ibcon#*before return 0, iclass 34, count 0 2006.285.15:35:07.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:35:07.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:35:07.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.15:35:07.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.15:35:07.71$vck44/vbbw=wide 2006.285.15:35:07.71#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.15:35:07.71#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.15:35:07.71#ibcon#ireg 8 cls_cnt 0 2006.285.15:35:07.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:35:07.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:35:07.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:35:07.78#ibcon#enter wrdev, iclass 36, count 0 2006.285.15:35:07.78#ibcon#first serial, iclass 36, count 0 2006.285.15:35:07.78#ibcon#enter sib2, iclass 36, count 0 2006.285.15:35:07.78#ibcon#flushed, iclass 36, count 0 2006.285.15:35:07.78#ibcon#about to write, iclass 36, count 0 2006.285.15:35:07.78#ibcon#wrote, iclass 36, count 0 2006.285.15:35:07.78#ibcon#about to read 3, iclass 36, count 0 2006.285.15:35:07.80#ibcon#read 3, iclass 36, count 0 2006.285.15:35:07.80#ibcon#about to read 4, iclass 36, count 0 2006.285.15:35:07.80#ibcon#read 4, iclass 36, count 0 2006.285.15:35:07.80#ibcon#about to read 5, iclass 36, count 0 2006.285.15:35:07.80#ibcon#read 5, iclass 36, count 0 2006.285.15:35:07.80#ibcon#about to read 6, iclass 36, count 0 2006.285.15:35:07.80#ibcon#read 6, iclass 36, count 0 2006.285.15:35:07.80#ibcon#end of sib2, iclass 36, count 0 2006.285.15:35:07.80#ibcon#*mode == 0, iclass 36, count 0 2006.285.15:35:07.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.15:35:07.80#ibcon#[27=BW32\r\n] 2006.285.15:35:07.80#ibcon#*before write, iclass 36, count 0 2006.285.15:35:07.80#ibcon#enter sib2, iclass 36, count 0 2006.285.15:35:07.80#ibcon#flushed, iclass 36, count 0 2006.285.15:35:07.80#ibcon#about to write, iclass 36, count 0 2006.285.15:35:07.80#ibcon#wrote, iclass 36, count 0 2006.285.15:35:07.80#ibcon#about to read 3, iclass 36, count 0 2006.285.15:35:07.83#ibcon#read 3, iclass 36, count 0 2006.285.15:35:07.83#ibcon#about to read 4, iclass 36, count 0 2006.285.15:35:07.83#ibcon#read 4, iclass 36, count 0 2006.285.15:35:07.83#ibcon#about to read 5, iclass 36, count 0 2006.285.15:35:07.83#ibcon#read 5, iclass 36, count 0 2006.285.15:35:07.83#ibcon#about to read 6, iclass 36, count 0 2006.285.15:35:07.83#ibcon#read 6, iclass 36, count 0 2006.285.15:35:07.83#ibcon#end of sib2, iclass 36, count 0 2006.285.15:35:07.83#ibcon#*after write, iclass 36, count 0 2006.285.15:35:07.83#ibcon#*before return 0, iclass 36, count 0 2006.285.15:35:07.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:35:07.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:35:07.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.15:35:07.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.15:35:07.83$setupk4/ifdk4 2006.285.15:35:07.83$ifdk4/lo= 2006.285.15:35:07.83$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.15:35:07.83$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.15:35:07.83$ifdk4/patch= 2006.285.15:35:07.83$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.15:35:07.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.15:35:07.83$setupk4/!*+20s 2006.285.15:35:09.86#abcon#<5=/02 1.0 3.9 19.01 921014.9\r\n> 2006.285.15:35:09.88#abcon#{5=INTERFACE CLEAR} 2006.285.15:35:09.94#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:35:11.14#trakl#Source acquired 2006.285.15:35:13.14#flagr#flagr/antenna,acquired 2006.285.15:35:20.03#abcon#<5=/02 1.0 3.9 19.01 921014.9\r\n> 2006.285.15:35:20.05#abcon#{5=INTERFACE CLEAR} 2006.285.15:35:20.11#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:35:21.55$setupk4/"tpicd 2006.285.15:35:21.55$setupk4/echo=off 2006.285.15:35:21.55$setupk4/xlog=off 2006.285.15:35:21.55:!2006.285.15:37:06 2006.285.15:37:06.00:preob 2006.285.15:37:06.13/onsource/TRACKING 2006.285.15:37:06.13:!2006.285.15:37:16 2006.285.15:37:16.00:"tape 2006.285.15:37:16.00:"st=record 2006.285.15:37:16.00:data_valid=on 2006.285.15:37:16.00:midob 2006.285.15:37:16.13/onsource/TRACKING 2006.285.15:37:16.13/wx/19.00,1015.0,91 2006.285.15:37:16.19/cable/+6.5013E-03 2006.285.15:37:17.28/va/01,07,usb,yes,33,36 2006.285.15:37:17.28/va/02,06,usb,yes,33,34 2006.285.15:37:17.28/va/03,07,usb,yes,33,35 2006.285.15:37:17.28/va/04,06,usb,yes,34,36 2006.285.15:37:17.28/va/05,03,usb,yes,34,34 2006.285.15:37:17.28/va/06,04,usb,yes,30,30 2006.285.15:37:17.28/va/07,04,usb,yes,31,32 2006.285.15:37:17.28/va/08,03,usb,yes,32,39 2006.285.15:37:17.51/valo/01,524.99,yes,locked 2006.285.15:37:17.51/valo/02,534.99,yes,locked 2006.285.15:37:17.51/valo/03,564.99,yes,locked 2006.285.15:37:17.51/valo/04,624.99,yes,locked 2006.285.15:37:17.51/valo/05,734.99,yes,locked 2006.285.15:37:17.51/valo/06,814.99,yes,locked 2006.285.15:37:17.51/valo/07,864.99,yes,locked 2006.285.15:37:17.51/valo/08,884.99,yes,locked 2006.285.15:37:18.60/vb/01,04,usb,yes,31,29 2006.285.15:37:18.60/vb/02,05,usb,yes,29,29 2006.285.15:37:18.60/vb/03,04,usb,yes,30,33 2006.285.15:37:18.60/vb/04,05,usb,yes,30,29 2006.285.15:37:18.60/vb/05,04,usb,yes,27,29 2006.285.15:37:18.60/vb/06,03,usb,yes,38,34 2006.285.15:37:18.60/vb/07,04,usb,yes,31,31 2006.285.15:37:18.60/vb/08,04,usb,yes,28,32 2006.285.15:37:18.84/vblo/01,629.99,yes,locked 2006.285.15:37:18.84/vblo/02,634.99,yes,locked 2006.285.15:37:18.84/vblo/03,649.99,yes,locked 2006.285.15:37:18.84/vblo/04,679.99,yes,locked 2006.285.15:37:18.84/vblo/05,709.99,yes,locked 2006.285.15:37:18.84/vblo/06,719.99,yes,locked 2006.285.15:37:18.84/vblo/07,734.99,yes,locked 2006.285.15:37:18.84/vblo/08,744.99,yes,locked 2006.285.15:37:18.99/vabw/8 2006.285.15:37:19.14/vbbw/8 2006.285.15:37:19.23/xfe/off,on,12.2 2006.285.15:37:19.60/ifatt/23,28,28,28 2006.285.15:37:20.07/fmout-gps/S +2.58E-07 2006.285.15:37:20.09:!2006.285.15:38:56 2006.285.15:38:56.01:data_valid=off 2006.285.15:38:56.01:"et 2006.285.15:38:56.01:!+3s 2006.285.15:38:59.02:"tape 2006.285.15:38:59.02:postob 2006.285.15:38:59.23/cable/+6.5009E-03 2006.285.15:38:59.23/wx/19.01,1015.0,91 2006.285.15:38:59.29/fmout-gps/S +2.54E-07 2006.285.15:38:59.29:scan_name=285-1543,jd0610,100 2006.285.15:38:59.29:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.285.15:39:01.14#flagr#flagr/antenna,new-source 2006.285.15:39:01.14:checkk5 2006.285.15:39:01.68/chk_autoobs//k5ts1/ autoobs is running! 2006.285.15:39:02.17/chk_autoobs//k5ts2/ autoobs is running! 2006.285.15:39:02.57/chk_autoobs//k5ts3/ autoobs is running! 2006.285.15:39:03.05/chk_autoobs//k5ts4/ autoobs is running! 2006.285.15:39:03.43/chk_obsdata//k5ts1/T2851537??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.15:39:03.94/chk_obsdata//k5ts2/T2851537??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.15:39:04.38/chk_obsdata//k5ts3/T2851537??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.15:39:04.82/chk_obsdata//k5ts4/T2851537??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.15:39:05.63/k5log//k5ts1_log_newline 2006.285.15:39:06.46/k5log//k5ts2_log_newline 2006.285.15:39:07.46/k5log//k5ts3_log_newline 2006.285.15:39:08.33/k5log//k5ts4_log_newline 2006.285.15:39:08.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.15:39:08.36:setupk4=1 2006.285.15:39:08.36$setupk4/echo=on 2006.285.15:39:08.36$setupk4/pcalon 2006.285.15:39:08.36$pcalon/"no phase cal control is implemented here 2006.285.15:39:08.36$setupk4/"tpicd=stop 2006.285.15:39:08.36$setupk4/"rec=synch_on 2006.285.15:39:08.36$setupk4/"rec_mode=128 2006.285.15:39:08.36$setupk4/!* 2006.285.15:39:08.36$setupk4/recpk4 2006.285.15:39:08.36$recpk4/recpatch= 2006.285.15:39:08.36$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.15:39:08.36$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.15:39:08.36$setupk4/vck44 2006.285.15:39:08.36$vck44/valo=1,524.99 2006.285.15:39:08.36#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.15:39:08.36#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.15:39:08.36#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:08.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:39:08.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:39:08.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:39:08.36#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:39:08.36#ibcon#first serial, iclass 29, count 0 2006.285.15:39:08.36#ibcon#enter sib2, iclass 29, count 0 2006.285.15:39:08.36#ibcon#flushed, iclass 29, count 0 2006.285.15:39:08.36#ibcon#about to write, iclass 29, count 0 2006.285.15:39:08.36#ibcon#wrote, iclass 29, count 0 2006.285.15:39:08.36#ibcon#about to read 3, iclass 29, count 0 2006.285.15:39:08.38#ibcon#read 3, iclass 29, count 0 2006.285.15:39:08.38#ibcon#about to read 4, iclass 29, count 0 2006.285.15:39:08.38#ibcon#read 4, iclass 29, count 0 2006.285.15:39:08.38#ibcon#about to read 5, iclass 29, count 0 2006.285.15:39:08.38#ibcon#read 5, iclass 29, count 0 2006.285.15:39:08.38#ibcon#about to read 6, iclass 29, count 0 2006.285.15:39:08.38#ibcon#read 6, iclass 29, count 0 2006.285.15:39:08.38#ibcon#end of sib2, iclass 29, count 0 2006.285.15:39:08.38#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:39:08.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:39:08.38#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.15:39:08.38#ibcon#*before write, iclass 29, count 0 2006.285.15:39:08.38#ibcon#enter sib2, iclass 29, count 0 2006.285.15:39:08.38#ibcon#flushed, iclass 29, count 0 2006.285.15:39:08.38#ibcon#about to write, iclass 29, count 0 2006.285.15:39:08.38#ibcon#wrote, iclass 29, count 0 2006.285.15:39:08.38#ibcon#about to read 3, iclass 29, count 0 2006.285.15:39:08.43#ibcon#read 3, iclass 29, count 0 2006.285.15:39:08.43#ibcon#about to read 4, iclass 29, count 0 2006.285.15:39:08.43#ibcon#read 4, iclass 29, count 0 2006.285.15:39:08.43#ibcon#about to read 5, iclass 29, count 0 2006.285.15:39:08.43#ibcon#read 5, iclass 29, count 0 2006.285.15:39:08.43#ibcon#about to read 6, iclass 29, count 0 2006.285.15:39:08.43#ibcon#read 6, iclass 29, count 0 2006.285.15:39:08.43#ibcon#end of sib2, iclass 29, count 0 2006.285.15:39:08.43#ibcon#*after write, iclass 29, count 0 2006.285.15:39:08.43#ibcon#*before return 0, iclass 29, count 0 2006.285.15:39:08.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:39:08.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:39:08.43#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:39:08.43#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:39:08.43$vck44/va=1,7 2006.285.15:39:08.43#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.15:39:08.43#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.15:39:08.43#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:08.43#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:39:08.43#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:39:08.43#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:39:08.43#ibcon#enter wrdev, iclass 31, count 2 2006.285.15:39:08.43#ibcon#first serial, iclass 31, count 2 2006.285.15:39:08.43#ibcon#enter sib2, iclass 31, count 2 2006.285.15:39:08.43#ibcon#flushed, iclass 31, count 2 2006.285.15:39:08.43#ibcon#about to write, iclass 31, count 2 2006.285.15:39:08.43#ibcon#wrote, iclass 31, count 2 2006.285.15:39:08.43#ibcon#about to read 3, iclass 31, count 2 2006.285.15:39:08.45#ibcon#read 3, iclass 31, count 2 2006.285.15:39:08.45#ibcon#about to read 4, iclass 31, count 2 2006.285.15:39:08.45#ibcon#read 4, iclass 31, count 2 2006.285.15:39:08.45#ibcon#about to read 5, iclass 31, count 2 2006.285.15:39:08.45#ibcon#read 5, iclass 31, count 2 2006.285.15:39:08.45#ibcon#about to read 6, iclass 31, count 2 2006.285.15:39:08.45#ibcon#read 6, iclass 31, count 2 2006.285.15:39:08.45#ibcon#end of sib2, iclass 31, count 2 2006.285.15:39:08.45#ibcon#*mode == 0, iclass 31, count 2 2006.285.15:39:08.45#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.15:39:08.45#ibcon#[25=AT01-07\r\n] 2006.285.15:39:08.45#ibcon#*before write, iclass 31, count 2 2006.285.15:39:08.45#ibcon#enter sib2, iclass 31, count 2 2006.285.15:39:08.45#ibcon#flushed, iclass 31, count 2 2006.285.15:39:08.45#ibcon#about to write, iclass 31, count 2 2006.285.15:39:08.45#ibcon#wrote, iclass 31, count 2 2006.285.15:39:08.45#ibcon#about to read 3, iclass 31, count 2 2006.285.15:39:08.48#ibcon#read 3, iclass 31, count 2 2006.285.15:39:08.48#ibcon#about to read 4, iclass 31, count 2 2006.285.15:39:08.48#ibcon#read 4, iclass 31, count 2 2006.285.15:39:08.48#ibcon#about to read 5, iclass 31, count 2 2006.285.15:39:08.48#ibcon#read 5, iclass 31, count 2 2006.285.15:39:08.48#ibcon#about to read 6, iclass 31, count 2 2006.285.15:39:08.48#ibcon#read 6, iclass 31, count 2 2006.285.15:39:08.48#ibcon#end of sib2, iclass 31, count 2 2006.285.15:39:08.48#ibcon#*after write, iclass 31, count 2 2006.285.15:39:08.48#ibcon#*before return 0, iclass 31, count 2 2006.285.15:39:08.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:39:08.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:39:08.48#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.15:39:08.48#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:08.48#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:39:08.60#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:39:08.60#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:39:08.60#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:39:08.60#ibcon#first serial, iclass 31, count 0 2006.285.15:39:08.60#ibcon#enter sib2, iclass 31, count 0 2006.285.15:39:08.60#ibcon#flushed, iclass 31, count 0 2006.285.15:39:08.60#ibcon#about to write, iclass 31, count 0 2006.285.15:39:08.60#ibcon#wrote, iclass 31, count 0 2006.285.15:39:08.60#ibcon#about to read 3, iclass 31, count 0 2006.285.15:39:08.62#ibcon#read 3, iclass 31, count 0 2006.285.15:39:08.62#ibcon#about to read 4, iclass 31, count 0 2006.285.15:39:08.62#ibcon#read 4, iclass 31, count 0 2006.285.15:39:08.62#ibcon#about to read 5, iclass 31, count 0 2006.285.15:39:08.62#ibcon#read 5, iclass 31, count 0 2006.285.15:39:08.62#ibcon#about to read 6, iclass 31, count 0 2006.285.15:39:08.62#ibcon#read 6, iclass 31, count 0 2006.285.15:39:08.62#ibcon#end of sib2, iclass 31, count 0 2006.285.15:39:08.62#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:39:08.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:39:08.62#ibcon#[25=USB\r\n] 2006.285.15:39:08.62#ibcon#*before write, iclass 31, count 0 2006.285.15:39:08.62#ibcon#enter sib2, iclass 31, count 0 2006.285.15:39:08.62#ibcon#flushed, iclass 31, count 0 2006.285.15:39:08.62#ibcon#about to write, iclass 31, count 0 2006.285.15:39:08.62#ibcon#wrote, iclass 31, count 0 2006.285.15:39:08.62#ibcon#about to read 3, iclass 31, count 0 2006.285.15:39:08.65#ibcon#read 3, iclass 31, count 0 2006.285.15:39:08.65#ibcon#about to read 4, iclass 31, count 0 2006.285.15:39:08.65#ibcon#read 4, iclass 31, count 0 2006.285.15:39:08.65#ibcon#about to read 5, iclass 31, count 0 2006.285.15:39:08.65#ibcon#read 5, iclass 31, count 0 2006.285.15:39:08.65#ibcon#about to read 6, iclass 31, count 0 2006.285.15:39:08.65#ibcon#read 6, iclass 31, count 0 2006.285.15:39:08.65#ibcon#end of sib2, iclass 31, count 0 2006.285.15:39:08.65#ibcon#*after write, iclass 31, count 0 2006.285.15:39:08.65#ibcon#*before return 0, iclass 31, count 0 2006.285.15:39:08.65#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:39:08.65#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:39:08.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:39:08.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:39:08.65$vck44/valo=2,534.99 2006.285.15:39:08.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.15:39:08.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.15:39:08.65#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:08.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:39:08.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:39:08.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:39:08.65#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:39:08.65#ibcon#first serial, iclass 33, count 0 2006.285.15:39:08.65#ibcon#enter sib2, iclass 33, count 0 2006.285.15:39:08.65#ibcon#flushed, iclass 33, count 0 2006.285.15:39:08.65#ibcon#about to write, iclass 33, count 0 2006.285.15:39:08.65#ibcon#wrote, iclass 33, count 0 2006.285.15:39:08.65#ibcon#about to read 3, iclass 33, count 0 2006.285.15:39:08.67#ibcon#read 3, iclass 33, count 0 2006.285.15:39:08.67#ibcon#about to read 4, iclass 33, count 0 2006.285.15:39:08.67#ibcon#read 4, iclass 33, count 0 2006.285.15:39:08.67#ibcon#about to read 5, iclass 33, count 0 2006.285.15:39:08.67#ibcon#read 5, iclass 33, count 0 2006.285.15:39:08.67#ibcon#about to read 6, iclass 33, count 0 2006.285.15:39:08.67#ibcon#read 6, iclass 33, count 0 2006.285.15:39:08.67#ibcon#end of sib2, iclass 33, count 0 2006.285.15:39:08.67#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:39:08.67#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:39:08.67#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.15:39:08.67#ibcon#*before write, iclass 33, count 0 2006.285.15:39:08.67#ibcon#enter sib2, iclass 33, count 0 2006.285.15:39:08.67#ibcon#flushed, iclass 33, count 0 2006.285.15:39:08.67#ibcon#about to write, iclass 33, count 0 2006.285.15:39:08.67#ibcon#wrote, iclass 33, count 0 2006.285.15:39:08.67#ibcon#about to read 3, iclass 33, count 0 2006.285.15:39:08.71#ibcon#read 3, iclass 33, count 0 2006.285.15:39:08.71#ibcon#about to read 4, iclass 33, count 0 2006.285.15:39:08.71#ibcon#read 4, iclass 33, count 0 2006.285.15:39:08.71#ibcon#about to read 5, iclass 33, count 0 2006.285.15:39:08.71#ibcon#read 5, iclass 33, count 0 2006.285.15:39:08.71#ibcon#about to read 6, iclass 33, count 0 2006.285.15:39:08.71#ibcon#read 6, iclass 33, count 0 2006.285.15:39:08.71#ibcon#end of sib2, iclass 33, count 0 2006.285.15:39:08.71#ibcon#*after write, iclass 33, count 0 2006.285.15:39:08.71#ibcon#*before return 0, iclass 33, count 0 2006.285.15:39:08.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:39:08.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:39:08.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:39:08.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:39:08.71$vck44/va=2,6 2006.285.15:39:08.71#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.15:39:08.71#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.15:39:08.71#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:08.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:39:08.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:39:08.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:39:08.77#ibcon#enter wrdev, iclass 35, count 2 2006.285.15:39:08.77#ibcon#first serial, iclass 35, count 2 2006.285.15:39:08.77#ibcon#enter sib2, iclass 35, count 2 2006.285.15:39:08.77#ibcon#flushed, iclass 35, count 2 2006.285.15:39:08.77#ibcon#about to write, iclass 35, count 2 2006.285.15:39:08.77#ibcon#wrote, iclass 35, count 2 2006.285.15:39:08.77#ibcon#about to read 3, iclass 35, count 2 2006.285.15:39:08.79#ibcon#read 3, iclass 35, count 2 2006.285.15:39:08.79#ibcon#about to read 4, iclass 35, count 2 2006.285.15:39:08.79#ibcon#read 4, iclass 35, count 2 2006.285.15:39:08.79#ibcon#about to read 5, iclass 35, count 2 2006.285.15:39:08.79#ibcon#read 5, iclass 35, count 2 2006.285.15:39:08.79#ibcon#about to read 6, iclass 35, count 2 2006.285.15:39:08.79#ibcon#read 6, iclass 35, count 2 2006.285.15:39:08.79#ibcon#end of sib2, iclass 35, count 2 2006.285.15:39:08.79#ibcon#*mode == 0, iclass 35, count 2 2006.285.15:39:08.79#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.15:39:08.79#ibcon#[25=AT02-06\r\n] 2006.285.15:39:08.79#ibcon#*before write, iclass 35, count 2 2006.285.15:39:08.79#ibcon#enter sib2, iclass 35, count 2 2006.285.15:39:08.79#ibcon#flushed, iclass 35, count 2 2006.285.15:39:08.79#ibcon#about to write, iclass 35, count 2 2006.285.15:39:08.79#ibcon#wrote, iclass 35, count 2 2006.285.15:39:08.79#ibcon#about to read 3, iclass 35, count 2 2006.285.15:39:08.82#ibcon#read 3, iclass 35, count 2 2006.285.15:39:08.82#ibcon#about to read 4, iclass 35, count 2 2006.285.15:39:08.82#ibcon#read 4, iclass 35, count 2 2006.285.15:39:08.82#ibcon#about to read 5, iclass 35, count 2 2006.285.15:39:08.82#ibcon#read 5, iclass 35, count 2 2006.285.15:39:08.82#ibcon#about to read 6, iclass 35, count 2 2006.285.15:39:08.82#ibcon#read 6, iclass 35, count 2 2006.285.15:39:08.82#ibcon#end of sib2, iclass 35, count 2 2006.285.15:39:08.82#ibcon#*after write, iclass 35, count 2 2006.285.15:39:08.82#ibcon#*before return 0, iclass 35, count 2 2006.285.15:39:08.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:39:08.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:39:08.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.15:39:08.82#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:08.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:39:08.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:39:09.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:39:09.49#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:39:09.49#ibcon#first serial, iclass 35, count 0 2006.285.15:39:09.49#ibcon#enter sib2, iclass 35, count 0 2006.285.15:39:09.49#ibcon#flushed, iclass 35, count 0 2006.285.15:39:09.49#ibcon#about to write, iclass 35, count 0 2006.285.15:39:09.49#ibcon#wrote, iclass 35, count 0 2006.285.15:39:09.49#ibcon#about to read 3, iclass 35, count 0 2006.285.15:39:09.50#ibcon#read 3, iclass 35, count 0 2006.285.15:39:09.50#ibcon#about to read 4, iclass 35, count 0 2006.285.15:39:09.50#ibcon#read 4, iclass 35, count 0 2006.285.15:39:09.50#ibcon#about to read 5, iclass 35, count 0 2006.285.15:39:09.50#ibcon#read 5, iclass 35, count 0 2006.285.15:39:09.50#ibcon#about to read 6, iclass 35, count 0 2006.285.15:39:09.50#ibcon#read 6, iclass 35, count 0 2006.285.15:39:09.50#ibcon#end of sib2, iclass 35, count 0 2006.285.15:39:09.50#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:39:09.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:39:09.50#ibcon#[25=USB\r\n] 2006.285.15:39:09.50#ibcon#*before write, iclass 35, count 0 2006.285.15:39:09.50#ibcon#enter sib2, iclass 35, count 0 2006.285.15:39:09.50#ibcon#flushed, iclass 35, count 0 2006.285.15:39:09.50#ibcon#about to write, iclass 35, count 0 2006.285.15:39:09.50#ibcon#wrote, iclass 35, count 0 2006.285.15:39:09.50#ibcon#about to read 3, iclass 35, count 0 2006.285.15:39:09.53#ibcon#read 3, iclass 35, count 0 2006.285.15:39:09.53#ibcon#about to read 4, iclass 35, count 0 2006.285.15:39:09.53#ibcon#read 4, iclass 35, count 0 2006.285.15:39:09.53#ibcon#about to read 5, iclass 35, count 0 2006.285.15:39:09.53#ibcon#read 5, iclass 35, count 0 2006.285.15:39:09.53#ibcon#about to read 6, iclass 35, count 0 2006.285.15:39:09.53#ibcon#read 6, iclass 35, count 0 2006.285.15:39:09.53#ibcon#end of sib2, iclass 35, count 0 2006.285.15:39:09.53#ibcon#*after write, iclass 35, count 0 2006.285.15:39:09.53#ibcon#*before return 0, iclass 35, count 0 2006.285.15:39:09.53#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:39:09.53#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:39:09.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:39:09.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:39:09.53$vck44/valo=3,564.99 2006.285.15:39:09.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.15:39:09.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.15:39:09.53#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:09.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:39:09.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:39:09.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:39:09.53#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:39:09.53#ibcon#first serial, iclass 37, count 0 2006.285.15:39:09.53#ibcon#enter sib2, iclass 37, count 0 2006.285.15:39:09.53#ibcon#flushed, iclass 37, count 0 2006.285.15:39:09.53#ibcon#about to write, iclass 37, count 0 2006.285.15:39:09.53#ibcon#wrote, iclass 37, count 0 2006.285.15:39:09.53#ibcon#about to read 3, iclass 37, count 0 2006.285.15:39:09.55#ibcon#read 3, iclass 37, count 0 2006.285.15:39:09.55#ibcon#about to read 4, iclass 37, count 0 2006.285.15:39:09.55#ibcon#read 4, iclass 37, count 0 2006.285.15:39:09.55#ibcon#about to read 5, iclass 37, count 0 2006.285.15:39:09.55#ibcon#read 5, iclass 37, count 0 2006.285.15:39:09.55#ibcon#about to read 6, iclass 37, count 0 2006.285.15:39:09.55#ibcon#read 6, iclass 37, count 0 2006.285.15:39:09.55#ibcon#end of sib2, iclass 37, count 0 2006.285.15:39:09.55#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:39:09.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:39:09.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.15:39:09.55#ibcon#*before write, iclass 37, count 0 2006.285.15:39:09.55#ibcon#enter sib2, iclass 37, count 0 2006.285.15:39:09.55#ibcon#flushed, iclass 37, count 0 2006.285.15:39:09.55#ibcon#about to write, iclass 37, count 0 2006.285.15:39:09.55#ibcon#wrote, iclass 37, count 0 2006.285.15:39:09.55#ibcon#about to read 3, iclass 37, count 0 2006.285.15:39:09.59#ibcon#read 3, iclass 37, count 0 2006.285.15:39:09.59#ibcon#about to read 4, iclass 37, count 0 2006.285.15:39:09.59#ibcon#read 4, iclass 37, count 0 2006.285.15:39:09.59#ibcon#about to read 5, iclass 37, count 0 2006.285.15:39:09.59#ibcon#read 5, iclass 37, count 0 2006.285.15:39:09.59#ibcon#about to read 6, iclass 37, count 0 2006.285.15:39:09.59#ibcon#read 6, iclass 37, count 0 2006.285.15:39:09.59#ibcon#end of sib2, iclass 37, count 0 2006.285.15:39:09.59#ibcon#*after write, iclass 37, count 0 2006.285.15:39:09.59#ibcon#*before return 0, iclass 37, count 0 2006.285.15:39:09.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:39:09.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:39:09.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:39:09.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:39:09.59$vck44/va=3,7 2006.285.15:39:09.59#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.15:39:09.59#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.15:39:09.59#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:09.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:39:09.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:39:09.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:39:09.65#ibcon#enter wrdev, iclass 39, count 2 2006.285.15:39:09.65#ibcon#first serial, iclass 39, count 2 2006.285.15:39:09.65#ibcon#enter sib2, iclass 39, count 2 2006.285.15:39:09.65#ibcon#flushed, iclass 39, count 2 2006.285.15:39:09.65#ibcon#about to write, iclass 39, count 2 2006.285.15:39:09.65#ibcon#wrote, iclass 39, count 2 2006.285.15:39:09.65#ibcon#about to read 3, iclass 39, count 2 2006.285.15:39:09.67#ibcon#read 3, iclass 39, count 2 2006.285.15:39:09.67#ibcon#about to read 4, iclass 39, count 2 2006.285.15:39:09.67#ibcon#read 4, iclass 39, count 2 2006.285.15:39:09.67#ibcon#about to read 5, iclass 39, count 2 2006.285.15:39:09.67#ibcon#read 5, iclass 39, count 2 2006.285.15:39:09.67#ibcon#about to read 6, iclass 39, count 2 2006.285.15:39:09.67#ibcon#read 6, iclass 39, count 2 2006.285.15:39:09.67#ibcon#end of sib2, iclass 39, count 2 2006.285.15:39:09.67#ibcon#*mode == 0, iclass 39, count 2 2006.285.15:39:09.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.15:39:09.67#ibcon#[25=AT03-07\r\n] 2006.285.15:39:09.67#ibcon#*before write, iclass 39, count 2 2006.285.15:39:09.67#ibcon#enter sib2, iclass 39, count 2 2006.285.15:39:09.67#ibcon#flushed, iclass 39, count 2 2006.285.15:39:09.67#ibcon#about to write, iclass 39, count 2 2006.285.15:39:09.67#ibcon#wrote, iclass 39, count 2 2006.285.15:39:09.67#ibcon#about to read 3, iclass 39, count 2 2006.285.15:39:09.70#ibcon#read 3, iclass 39, count 2 2006.285.15:39:09.70#ibcon#about to read 4, iclass 39, count 2 2006.285.15:39:09.70#ibcon#read 4, iclass 39, count 2 2006.285.15:39:09.70#ibcon#about to read 5, iclass 39, count 2 2006.285.15:39:09.70#ibcon#read 5, iclass 39, count 2 2006.285.15:39:09.70#ibcon#about to read 6, iclass 39, count 2 2006.285.15:39:09.70#ibcon#read 6, iclass 39, count 2 2006.285.15:39:09.70#ibcon#end of sib2, iclass 39, count 2 2006.285.15:39:09.70#ibcon#*after write, iclass 39, count 2 2006.285.15:39:09.70#ibcon#*before return 0, iclass 39, count 2 2006.285.15:39:09.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:39:09.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:39:09.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.15:39:09.70#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:09.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:39:09.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:39:09.95#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:39:09.95#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:39:09.95#ibcon#first serial, iclass 39, count 0 2006.285.15:39:09.95#ibcon#enter sib2, iclass 39, count 0 2006.285.15:39:09.95#ibcon#flushed, iclass 39, count 0 2006.285.15:39:09.95#ibcon#about to write, iclass 39, count 0 2006.285.15:39:09.95#ibcon#wrote, iclass 39, count 0 2006.285.15:39:09.95#ibcon#about to read 3, iclass 39, count 0 2006.285.15:39:09.97#ibcon#read 3, iclass 39, count 0 2006.285.15:39:09.97#ibcon#about to read 4, iclass 39, count 0 2006.285.15:39:09.97#ibcon#read 4, iclass 39, count 0 2006.285.15:39:09.97#ibcon#about to read 5, iclass 39, count 0 2006.285.15:39:09.97#ibcon#read 5, iclass 39, count 0 2006.285.15:39:09.97#ibcon#about to read 6, iclass 39, count 0 2006.285.15:39:09.97#ibcon#read 6, iclass 39, count 0 2006.285.15:39:09.97#ibcon#end of sib2, iclass 39, count 0 2006.285.15:39:09.97#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:39:09.97#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:39:09.97#ibcon#[25=USB\r\n] 2006.285.15:39:09.97#ibcon#*before write, iclass 39, count 0 2006.285.15:39:09.97#ibcon#enter sib2, iclass 39, count 0 2006.285.15:39:09.97#ibcon#flushed, iclass 39, count 0 2006.285.15:39:09.97#ibcon#about to write, iclass 39, count 0 2006.285.15:39:09.97#ibcon#wrote, iclass 39, count 0 2006.285.15:39:09.97#ibcon#about to read 3, iclass 39, count 0 2006.285.15:39:10.00#ibcon#read 3, iclass 39, count 0 2006.285.15:39:10.00#ibcon#about to read 4, iclass 39, count 0 2006.285.15:39:10.00#ibcon#read 4, iclass 39, count 0 2006.285.15:39:10.00#ibcon#about to read 5, iclass 39, count 0 2006.285.15:39:10.00#ibcon#read 5, iclass 39, count 0 2006.285.15:39:10.00#ibcon#about to read 6, iclass 39, count 0 2006.285.15:39:10.00#ibcon#read 6, iclass 39, count 0 2006.285.15:39:10.00#ibcon#end of sib2, iclass 39, count 0 2006.285.15:39:10.00#ibcon#*after write, iclass 39, count 0 2006.285.15:39:10.00#ibcon#*before return 0, iclass 39, count 0 2006.285.15:39:10.00#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:39:10.00#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:39:10.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:39:10.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:39:10.00$vck44/valo=4,624.99 2006.285.15:39:10.00#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.15:39:10.00#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.15:39:10.00#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:10.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:39:10.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:39:10.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:39:10.00#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:39:10.00#ibcon#first serial, iclass 3, count 0 2006.285.15:39:10.00#ibcon#enter sib2, iclass 3, count 0 2006.285.15:39:10.00#ibcon#flushed, iclass 3, count 0 2006.285.15:39:10.00#ibcon#about to write, iclass 3, count 0 2006.285.15:39:10.00#ibcon#wrote, iclass 3, count 0 2006.285.15:39:10.00#ibcon#about to read 3, iclass 3, count 0 2006.285.15:39:10.02#ibcon#read 3, iclass 3, count 0 2006.285.15:39:10.02#ibcon#about to read 4, iclass 3, count 0 2006.285.15:39:10.02#ibcon#read 4, iclass 3, count 0 2006.285.15:39:10.02#ibcon#about to read 5, iclass 3, count 0 2006.285.15:39:10.02#ibcon#read 5, iclass 3, count 0 2006.285.15:39:10.02#ibcon#about to read 6, iclass 3, count 0 2006.285.15:39:10.02#ibcon#read 6, iclass 3, count 0 2006.285.15:39:10.02#ibcon#end of sib2, iclass 3, count 0 2006.285.15:39:10.02#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:39:10.02#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:39:10.02#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.15:39:10.02#ibcon#*before write, iclass 3, count 0 2006.285.15:39:10.02#ibcon#enter sib2, iclass 3, count 0 2006.285.15:39:10.02#ibcon#flushed, iclass 3, count 0 2006.285.15:39:10.02#ibcon#about to write, iclass 3, count 0 2006.285.15:39:10.02#ibcon#wrote, iclass 3, count 0 2006.285.15:39:10.02#ibcon#about to read 3, iclass 3, count 0 2006.285.15:39:10.06#ibcon#read 3, iclass 3, count 0 2006.285.15:39:10.06#ibcon#about to read 4, iclass 3, count 0 2006.285.15:39:10.06#ibcon#read 4, iclass 3, count 0 2006.285.15:39:10.06#ibcon#about to read 5, iclass 3, count 0 2006.285.15:39:10.06#ibcon#read 5, iclass 3, count 0 2006.285.15:39:10.06#ibcon#about to read 6, iclass 3, count 0 2006.285.15:39:10.06#ibcon#read 6, iclass 3, count 0 2006.285.15:39:10.06#ibcon#end of sib2, iclass 3, count 0 2006.285.15:39:10.06#ibcon#*after write, iclass 3, count 0 2006.285.15:39:10.06#ibcon#*before return 0, iclass 3, count 0 2006.285.15:39:10.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:39:10.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:39:10.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:39:10.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:39:10.06$vck44/va=4,6 2006.285.15:39:10.06#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.15:39:10.06#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.15:39:10.06#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:10.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:39:10.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:39:10.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:39:10.12#ibcon#enter wrdev, iclass 5, count 2 2006.285.15:39:10.12#ibcon#first serial, iclass 5, count 2 2006.285.15:39:10.12#ibcon#enter sib2, iclass 5, count 2 2006.285.15:39:10.12#ibcon#flushed, iclass 5, count 2 2006.285.15:39:10.12#ibcon#about to write, iclass 5, count 2 2006.285.15:39:10.12#ibcon#wrote, iclass 5, count 2 2006.285.15:39:10.12#ibcon#about to read 3, iclass 5, count 2 2006.285.15:39:10.14#ibcon#read 3, iclass 5, count 2 2006.285.15:39:10.14#ibcon#about to read 4, iclass 5, count 2 2006.285.15:39:10.14#ibcon#read 4, iclass 5, count 2 2006.285.15:39:10.14#ibcon#about to read 5, iclass 5, count 2 2006.285.15:39:10.14#ibcon#read 5, iclass 5, count 2 2006.285.15:39:10.14#ibcon#about to read 6, iclass 5, count 2 2006.285.15:39:10.14#ibcon#read 6, iclass 5, count 2 2006.285.15:39:10.14#ibcon#end of sib2, iclass 5, count 2 2006.285.15:39:10.14#ibcon#*mode == 0, iclass 5, count 2 2006.285.15:39:10.14#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.15:39:10.14#ibcon#[25=AT04-06\r\n] 2006.285.15:39:10.14#ibcon#*before write, iclass 5, count 2 2006.285.15:39:10.14#ibcon#enter sib2, iclass 5, count 2 2006.285.15:39:10.14#ibcon#flushed, iclass 5, count 2 2006.285.15:39:10.14#ibcon#about to write, iclass 5, count 2 2006.285.15:39:10.14#ibcon#wrote, iclass 5, count 2 2006.285.15:39:10.14#ibcon#about to read 3, iclass 5, count 2 2006.285.15:39:10.17#ibcon#read 3, iclass 5, count 2 2006.285.15:39:10.19#ibcon#about to read 4, iclass 5, count 2 2006.285.15:39:10.19#ibcon#read 4, iclass 5, count 2 2006.285.15:39:10.19#ibcon#about to read 5, iclass 5, count 2 2006.285.15:39:10.19#ibcon#read 5, iclass 5, count 2 2006.285.15:39:10.19#ibcon#about to read 6, iclass 5, count 2 2006.285.15:39:10.19#ibcon#read 6, iclass 5, count 2 2006.285.15:39:10.19#ibcon#end of sib2, iclass 5, count 2 2006.285.15:39:10.19#ibcon#*after write, iclass 5, count 2 2006.285.15:39:10.19#ibcon#*before return 0, iclass 5, count 2 2006.285.15:39:10.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:39:10.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:39:10.19#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.15:39:10.19#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:10.19#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:39:10.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:39:10.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:39:10.30#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:39:10.30#ibcon#first serial, iclass 5, count 0 2006.285.15:39:10.30#ibcon#enter sib2, iclass 5, count 0 2006.285.15:39:10.30#ibcon#flushed, iclass 5, count 0 2006.285.15:39:10.30#ibcon#about to write, iclass 5, count 0 2006.285.15:39:10.30#ibcon#wrote, iclass 5, count 0 2006.285.15:39:10.30#ibcon#about to read 3, iclass 5, count 0 2006.285.15:39:10.32#ibcon#read 3, iclass 5, count 0 2006.285.15:39:10.32#ibcon#about to read 4, iclass 5, count 0 2006.285.15:39:10.32#ibcon#read 4, iclass 5, count 0 2006.285.15:39:10.32#ibcon#about to read 5, iclass 5, count 0 2006.285.15:39:10.32#ibcon#read 5, iclass 5, count 0 2006.285.15:39:10.32#ibcon#about to read 6, iclass 5, count 0 2006.285.15:39:10.32#ibcon#read 6, iclass 5, count 0 2006.285.15:39:10.32#ibcon#end of sib2, iclass 5, count 0 2006.285.15:39:10.32#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:39:10.32#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:39:10.32#ibcon#[25=USB\r\n] 2006.285.15:39:10.32#ibcon#*before write, iclass 5, count 0 2006.285.15:39:10.32#ibcon#enter sib2, iclass 5, count 0 2006.285.15:39:10.32#ibcon#flushed, iclass 5, count 0 2006.285.15:39:10.32#ibcon#about to write, iclass 5, count 0 2006.285.15:39:10.32#ibcon#wrote, iclass 5, count 0 2006.285.15:39:10.32#ibcon#about to read 3, iclass 5, count 0 2006.285.15:39:10.35#ibcon#read 3, iclass 5, count 0 2006.285.15:39:10.35#ibcon#about to read 4, iclass 5, count 0 2006.285.15:39:10.35#ibcon#read 4, iclass 5, count 0 2006.285.15:39:10.35#ibcon#about to read 5, iclass 5, count 0 2006.285.15:39:10.35#ibcon#read 5, iclass 5, count 0 2006.285.15:39:10.35#ibcon#about to read 6, iclass 5, count 0 2006.285.15:39:10.35#ibcon#read 6, iclass 5, count 0 2006.285.15:39:10.35#ibcon#end of sib2, iclass 5, count 0 2006.285.15:39:10.35#ibcon#*after write, iclass 5, count 0 2006.285.15:39:10.35#ibcon#*before return 0, iclass 5, count 0 2006.285.15:39:10.35#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:39:10.35#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:39:10.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:39:10.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:39:10.35$vck44/valo=5,734.99 2006.285.15:39:10.35#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.15:39:10.35#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.15:39:10.35#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:10.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:39:10.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:39:10.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:39:10.35#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:39:10.35#ibcon#first serial, iclass 7, count 0 2006.285.15:39:10.35#ibcon#enter sib2, iclass 7, count 0 2006.285.15:39:10.35#ibcon#flushed, iclass 7, count 0 2006.285.15:39:10.35#ibcon#about to write, iclass 7, count 0 2006.285.15:39:10.35#ibcon#wrote, iclass 7, count 0 2006.285.15:39:10.35#ibcon#about to read 3, iclass 7, count 0 2006.285.15:39:10.37#ibcon#read 3, iclass 7, count 0 2006.285.15:39:10.37#ibcon#about to read 4, iclass 7, count 0 2006.285.15:39:10.37#ibcon#read 4, iclass 7, count 0 2006.285.15:39:10.37#ibcon#about to read 5, iclass 7, count 0 2006.285.15:39:10.37#ibcon#read 5, iclass 7, count 0 2006.285.15:39:10.37#ibcon#about to read 6, iclass 7, count 0 2006.285.15:39:10.37#ibcon#read 6, iclass 7, count 0 2006.285.15:39:10.37#ibcon#end of sib2, iclass 7, count 0 2006.285.15:39:10.37#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:39:10.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:39:10.37#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.15:39:10.37#ibcon#*before write, iclass 7, count 0 2006.285.15:39:10.37#ibcon#enter sib2, iclass 7, count 0 2006.285.15:39:10.37#ibcon#flushed, iclass 7, count 0 2006.285.15:39:10.37#ibcon#about to write, iclass 7, count 0 2006.285.15:39:10.37#ibcon#wrote, iclass 7, count 0 2006.285.15:39:10.37#ibcon#about to read 3, iclass 7, count 0 2006.285.15:39:10.41#ibcon#read 3, iclass 7, count 0 2006.285.15:39:10.41#ibcon#about to read 4, iclass 7, count 0 2006.285.15:39:10.41#ibcon#read 4, iclass 7, count 0 2006.285.15:39:10.41#ibcon#about to read 5, iclass 7, count 0 2006.285.15:39:10.41#ibcon#read 5, iclass 7, count 0 2006.285.15:39:10.41#ibcon#about to read 6, iclass 7, count 0 2006.285.15:39:10.41#ibcon#read 6, iclass 7, count 0 2006.285.15:39:10.41#ibcon#end of sib2, iclass 7, count 0 2006.285.15:39:10.41#ibcon#*after write, iclass 7, count 0 2006.285.15:39:10.41#ibcon#*before return 0, iclass 7, count 0 2006.285.15:39:10.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:39:10.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:39:10.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:39:10.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:39:10.41$vck44/va=5,3 2006.285.15:39:10.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.15:39:10.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.15:39:10.41#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:10.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:39:10.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:39:10.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:39:10.47#ibcon#enter wrdev, iclass 11, count 2 2006.285.15:39:10.47#ibcon#first serial, iclass 11, count 2 2006.285.15:39:10.47#ibcon#enter sib2, iclass 11, count 2 2006.285.15:39:10.47#ibcon#flushed, iclass 11, count 2 2006.285.15:39:10.47#ibcon#about to write, iclass 11, count 2 2006.285.15:39:10.47#ibcon#wrote, iclass 11, count 2 2006.285.15:39:10.47#ibcon#about to read 3, iclass 11, count 2 2006.285.15:39:10.49#ibcon#read 3, iclass 11, count 2 2006.285.15:39:10.49#ibcon#about to read 4, iclass 11, count 2 2006.285.15:39:10.49#ibcon#read 4, iclass 11, count 2 2006.285.15:39:10.49#ibcon#about to read 5, iclass 11, count 2 2006.285.15:39:10.49#ibcon#read 5, iclass 11, count 2 2006.285.15:39:10.49#ibcon#about to read 6, iclass 11, count 2 2006.285.15:39:10.49#ibcon#read 6, iclass 11, count 2 2006.285.15:39:10.49#ibcon#end of sib2, iclass 11, count 2 2006.285.15:39:10.49#ibcon#*mode == 0, iclass 11, count 2 2006.285.15:39:10.49#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.15:39:10.49#ibcon#[25=AT05-03\r\n] 2006.285.15:39:10.49#ibcon#*before write, iclass 11, count 2 2006.285.15:39:10.49#ibcon#enter sib2, iclass 11, count 2 2006.285.15:39:10.49#ibcon#flushed, iclass 11, count 2 2006.285.15:39:10.49#ibcon#about to write, iclass 11, count 2 2006.285.15:39:10.49#ibcon#wrote, iclass 11, count 2 2006.285.15:39:10.49#ibcon#about to read 3, iclass 11, count 2 2006.285.15:39:10.52#ibcon#read 3, iclass 11, count 2 2006.285.15:39:10.52#ibcon#about to read 4, iclass 11, count 2 2006.285.15:39:10.52#ibcon#read 4, iclass 11, count 2 2006.285.15:39:10.52#ibcon#about to read 5, iclass 11, count 2 2006.285.15:39:10.52#ibcon#read 5, iclass 11, count 2 2006.285.15:39:10.52#ibcon#about to read 6, iclass 11, count 2 2006.285.15:39:10.52#ibcon#read 6, iclass 11, count 2 2006.285.15:39:10.52#ibcon#end of sib2, iclass 11, count 2 2006.285.15:39:10.52#ibcon#*after write, iclass 11, count 2 2006.285.15:39:10.52#ibcon#*before return 0, iclass 11, count 2 2006.285.15:39:10.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:39:10.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:39:10.52#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.15:39:10.52#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:10.52#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:39:10.64#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:39:10.64#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:39:10.64#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:39:10.64#ibcon#first serial, iclass 11, count 0 2006.285.15:39:10.64#ibcon#enter sib2, iclass 11, count 0 2006.285.15:39:10.64#ibcon#flushed, iclass 11, count 0 2006.285.15:39:10.64#ibcon#about to write, iclass 11, count 0 2006.285.15:39:10.64#ibcon#wrote, iclass 11, count 0 2006.285.15:39:10.64#ibcon#about to read 3, iclass 11, count 0 2006.285.15:39:10.66#ibcon#read 3, iclass 11, count 0 2006.285.15:39:10.66#ibcon#about to read 4, iclass 11, count 0 2006.285.15:39:10.66#ibcon#read 4, iclass 11, count 0 2006.285.15:39:10.66#ibcon#about to read 5, iclass 11, count 0 2006.285.15:39:10.66#ibcon#read 5, iclass 11, count 0 2006.285.15:39:10.66#ibcon#about to read 6, iclass 11, count 0 2006.285.15:39:10.66#ibcon#read 6, iclass 11, count 0 2006.285.15:39:10.66#ibcon#end of sib2, iclass 11, count 0 2006.285.15:39:10.66#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:39:10.66#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:39:10.66#ibcon#[25=USB\r\n] 2006.285.15:39:10.66#ibcon#*before write, iclass 11, count 0 2006.285.15:39:10.66#ibcon#enter sib2, iclass 11, count 0 2006.285.15:39:10.66#ibcon#flushed, iclass 11, count 0 2006.285.15:39:10.66#ibcon#about to write, iclass 11, count 0 2006.285.15:39:10.66#ibcon#wrote, iclass 11, count 0 2006.285.15:39:10.66#ibcon#about to read 3, iclass 11, count 0 2006.285.15:39:10.69#ibcon#read 3, iclass 11, count 0 2006.285.15:39:10.69#ibcon#about to read 4, iclass 11, count 0 2006.285.15:39:10.69#ibcon#read 4, iclass 11, count 0 2006.285.15:39:10.69#ibcon#about to read 5, iclass 11, count 0 2006.285.15:39:10.69#ibcon#read 5, iclass 11, count 0 2006.285.15:39:10.69#ibcon#about to read 6, iclass 11, count 0 2006.285.15:39:10.69#ibcon#read 6, iclass 11, count 0 2006.285.15:39:10.69#ibcon#end of sib2, iclass 11, count 0 2006.285.15:39:10.69#ibcon#*after write, iclass 11, count 0 2006.285.15:39:10.69#ibcon#*before return 0, iclass 11, count 0 2006.285.15:39:10.69#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:39:10.69#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:39:10.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:39:10.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:39:10.69$vck44/valo=6,814.99 2006.285.15:39:10.69#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.15:39:10.69#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.15:39:10.69#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:10.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:39:10.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:39:10.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:39:10.69#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:39:10.69#ibcon#first serial, iclass 13, count 0 2006.285.15:39:10.69#ibcon#enter sib2, iclass 13, count 0 2006.285.15:39:10.69#ibcon#flushed, iclass 13, count 0 2006.285.15:39:10.69#ibcon#about to write, iclass 13, count 0 2006.285.15:39:10.69#ibcon#wrote, iclass 13, count 0 2006.285.15:39:10.69#ibcon#about to read 3, iclass 13, count 0 2006.285.15:39:10.71#ibcon#read 3, iclass 13, count 0 2006.285.15:39:10.71#ibcon#about to read 4, iclass 13, count 0 2006.285.15:39:10.71#ibcon#read 4, iclass 13, count 0 2006.285.15:39:10.71#ibcon#about to read 5, iclass 13, count 0 2006.285.15:39:10.71#ibcon#read 5, iclass 13, count 0 2006.285.15:39:10.71#ibcon#about to read 6, iclass 13, count 0 2006.285.15:39:10.71#ibcon#read 6, iclass 13, count 0 2006.285.15:39:10.71#ibcon#end of sib2, iclass 13, count 0 2006.285.15:39:10.71#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:39:10.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:39:10.71#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.15:39:10.71#ibcon#*before write, iclass 13, count 0 2006.285.15:39:10.71#ibcon#enter sib2, iclass 13, count 0 2006.285.15:39:10.71#ibcon#flushed, iclass 13, count 0 2006.285.15:39:10.71#ibcon#about to write, iclass 13, count 0 2006.285.15:39:10.71#ibcon#wrote, iclass 13, count 0 2006.285.15:39:10.71#ibcon#about to read 3, iclass 13, count 0 2006.285.15:39:10.75#ibcon#read 3, iclass 13, count 0 2006.285.15:39:10.75#ibcon#about to read 4, iclass 13, count 0 2006.285.15:39:10.75#ibcon#read 4, iclass 13, count 0 2006.285.15:39:10.75#ibcon#about to read 5, iclass 13, count 0 2006.285.15:39:10.75#ibcon#read 5, iclass 13, count 0 2006.285.15:39:10.75#ibcon#about to read 6, iclass 13, count 0 2006.285.15:39:10.75#ibcon#read 6, iclass 13, count 0 2006.285.15:39:10.75#ibcon#end of sib2, iclass 13, count 0 2006.285.15:39:10.75#ibcon#*after write, iclass 13, count 0 2006.285.15:39:10.75#ibcon#*before return 0, iclass 13, count 0 2006.285.15:39:10.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:39:10.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:39:10.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:39:10.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:39:10.75$vck44/va=6,4 2006.285.15:39:10.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.15:39:10.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.15:39:10.75#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:10.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:39:10.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:39:10.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:39:10.81#ibcon#enter wrdev, iclass 15, count 2 2006.285.15:39:10.81#ibcon#first serial, iclass 15, count 2 2006.285.15:39:10.81#ibcon#enter sib2, iclass 15, count 2 2006.285.15:39:10.81#ibcon#flushed, iclass 15, count 2 2006.285.15:39:10.81#ibcon#about to write, iclass 15, count 2 2006.285.15:39:10.81#ibcon#wrote, iclass 15, count 2 2006.285.15:39:10.81#ibcon#about to read 3, iclass 15, count 2 2006.285.15:39:10.83#ibcon#read 3, iclass 15, count 2 2006.285.15:39:10.83#ibcon#about to read 4, iclass 15, count 2 2006.285.15:39:10.83#ibcon#read 4, iclass 15, count 2 2006.285.15:39:10.83#ibcon#about to read 5, iclass 15, count 2 2006.285.15:39:10.83#ibcon#read 5, iclass 15, count 2 2006.285.15:39:10.83#ibcon#about to read 6, iclass 15, count 2 2006.285.15:39:10.83#ibcon#read 6, iclass 15, count 2 2006.285.15:39:10.83#ibcon#end of sib2, iclass 15, count 2 2006.285.15:39:10.83#ibcon#*mode == 0, iclass 15, count 2 2006.285.15:39:10.83#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.15:39:10.83#ibcon#[25=AT06-04\r\n] 2006.285.15:39:10.83#ibcon#*before write, iclass 15, count 2 2006.285.15:39:10.83#ibcon#enter sib2, iclass 15, count 2 2006.285.15:39:10.83#ibcon#flushed, iclass 15, count 2 2006.285.15:39:10.83#ibcon#about to write, iclass 15, count 2 2006.285.15:39:10.83#ibcon#wrote, iclass 15, count 2 2006.285.15:39:10.83#ibcon#about to read 3, iclass 15, count 2 2006.285.15:39:10.86#ibcon#read 3, iclass 15, count 2 2006.285.15:39:10.86#ibcon#about to read 4, iclass 15, count 2 2006.285.15:39:10.86#ibcon#read 4, iclass 15, count 2 2006.285.15:39:10.86#ibcon#about to read 5, iclass 15, count 2 2006.285.15:39:10.86#ibcon#read 5, iclass 15, count 2 2006.285.15:39:10.86#ibcon#about to read 6, iclass 15, count 2 2006.285.15:39:10.86#ibcon#read 6, iclass 15, count 2 2006.285.15:39:10.86#ibcon#end of sib2, iclass 15, count 2 2006.285.15:39:10.86#ibcon#*after write, iclass 15, count 2 2006.285.15:39:10.86#ibcon#*before return 0, iclass 15, count 2 2006.285.15:39:10.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:39:10.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:39:10.86#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.15:39:10.86#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:10.86#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:39:10.98#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:39:10.98#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:39:10.98#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:39:10.98#ibcon#first serial, iclass 15, count 0 2006.285.15:39:10.98#ibcon#enter sib2, iclass 15, count 0 2006.285.15:39:10.98#ibcon#flushed, iclass 15, count 0 2006.285.15:39:10.98#ibcon#about to write, iclass 15, count 0 2006.285.15:39:10.98#ibcon#wrote, iclass 15, count 0 2006.285.15:39:10.98#ibcon#about to read 3, iclass 15, count 0 2006.285.15:39:11.00#ibcon#read 3, iclass 15, count 0 2006.285.15:39:11.00#ibcon#about to read 4, iclass 15, count 0 2006.285.15:39:11.00#ibcon#read 4, iclass 15, count 0 2006.285.15:39:11.00#ibcon#about to read 5, iclass 15, count 0 2006.285.15:39:11.00#ibcon#read 5, iclass 15, count 0 2006.285.15:39:11.00#ibcon#about to read 6, iclass 15, count 0 2006.285.15:39:11.00#ibcon#read 6, iclass 15, count 0 2006.285.15:39:11.00#ibcon#end of sib2, iclass 15, count 0 2006.285.15:39:11.00#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:39:11.00#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:39:11.00#ibcon#[25=USB\r\n] 2006.285.15:39:11.00#ibcon#*before write, iclass 15, count 0 2006.285.15:39:11.00#ibcon#enter sib2, iclass 15, count 0 2006.285.15:39:11.00#ibcon#flushed, iclass 15, count 0 2006.285.15:39:11.00#ibcon#about to write, iclass 15, count 0 2006.285.15:39:11.00#ibcon#wrote, iclass 15, count 0 2006.285.15:39:11.00#ibcon#about to read 3, iclass 15, count 0 2006.285.15:39:11.03#ibcon#read 3, iclass 15, count 0 2006.285.15:39:11.03#ibcon#about to read 4, iclass 15, count 0 2006.285.15:39:11.03#ibcon#read 4, iclass 15, count 0 2006.285.15:39:11.03#ibcon#about to read 5, iclass 15, count 0 2006.285.15:39:11.03#ibcon#read 5, iclass 15, count 0 2006.285.15:39:11.03#ibcon#about to read 6, iclass 15, count 0 2006.285.15:39:11.03#ibcon#read 6, iclass 15, count 0 2006.285.15:39:11.03#ibcon#end of sib2, iclass 15, count 0 2006.285.15:39:11.03#ibcon#*after write, iclass 15, count 0 2006.285.15:39:11.03#ibcon#*before return 0, iclass 15, count 0 2006.285.15:39:11.03#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:39:11.03#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:39:11.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:39:11.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:39:11.03$vck44/valo=7,864.99 2006.285.15:39:11.03#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.15:39:11.03#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.15:39:11.03#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:11.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:39:11.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:39:11.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:39:11.03#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:39:11.03#ibcon#first serial, iclass 17, count 0 2006.285.15:39:11.03#ibcon#enter sib2, iclass 17, count 0 2006.285.15:39:11.03#ibcon#flushed, iclass 17, count 0 2006.285.15:39:11.03#ibcon#about to write, iclass 17, count 0 2006.285.15:39:11.03#ibcon#wrote, iclass 17, count 0 2006.285.15:39:11.03#ibcon#about to read 3, iclass 17, count 0 2006.285.15:39:11.05#ibcon#read 3, iclass 17, count 0 2006.285.15:39:11.05#ibcon#about to read 4, iclass 17, count 0 2006.285.15:39:11.05#ibcon#read 4, iclass 17, count 0 2006.285.15:39:11.05#ibcon#about to read 5, iclass 17, count 0 2006.285.15:39:11.05#ibcon#read 5, iclass 17, count 0 2006.285.15:39:11.05#ibcon#about to read 6, iclass 17, count 0 2006.285.15:39:11.05#ibcon#read 6, iclass 17, count 0 2006.285.15:39:11.05#ibcon#end of sib2, iclass 17, count 0 2006.285.15:39:11.05#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:39:11.05#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:39:11.05#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.15:39:11.05#ibcon#*before write, iclass 17, count 0 2006.285.15:39:11.05#ibcon#enter sib2, iclass 17, count 0 2006.285.15:39:11.05#ibcon#flushed, iclass 17, count 0 2006.285.15:39:11.05#ibcon#about to write, iclass 17, count 0 2006.285.15:39:11.05#ibcon#wrote, iclass 17, count 0 2006.285.15:39:11.05#ibcon#about to read 3, iclass 17, count 0 2006.285.15:39:11.09#ibcon#read 3, iclass 17, count 0 2006.285.15:39:11.09#ibcon#about to read 4, iclass 17, count 0 2006.285.15:39:11.09#ibcon#read 4, iclass 17, count 0 2006.285.15:39:11.09#ibcon#about to read 5, iclass 17, count 0 2006.285.15:39:11.09#ibcon#read 5, iclass 17, count 0 2006.285.15:39:11.09#ibcon#about to read 6, iclass 17, count 0 2006.285.15:39:11.09#ibcon#read 6, iclass 17, count 0 2006.285.15:39:11.09#ibcon#end of sib2, iclass 17, count 0 2006.285.15:39:11.09#ibcon#*after write, iclass 17, count 0 2006.285.15:39:11.09#ibcon#*before return 0, iclass 17, count 0 2006.285.15:39:11.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:39:11.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:39:11.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:39:11.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:39:11.09$vck44/va=7,4 2006.285.15:39:11.09#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.15:39:11.09#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.15:39:11.09#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:11.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:39:11.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:39:11.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:39:11.15#ibcon#enter wrdev, iclass 19, count 2 2006.285.15:39:11.15#ibcon#first serial, iclass 19, count 2 2006.285.15:39:11.15#ibcon#enter sib2, iclass 19, count 2 2006.285.15:39:11.15#ibcon#flushed, iclass 19, count 2 2006.285.15:39:11.15#ibcon#about to write, iclass 19, count 2 2006.285.15:39:11.15#ibcon#wrote, iclass 19, count 2 2006.285.15:39:11.15#ibcon#about to read 3, iclass 19, count 2 2006.285.15:39:11.17#ibcon#read 3, iclass 19, count 2 2006.285.15:39:11.17#ibcon#about to read 4, iclass 19, count 2 2006.285.15:39:11.17#ibcon#read 4, iclass 19, count 2 2006.285.15:39:11.17#ibcon#about to read 5, iclass 19, count 2 2006.285.15:39:11.17#ibcon#read 5, iclass 19, count 2 2006.285.15:39:11.17#ibcon#about to read 6, iclass 19, count 2 2006.285.15:39:11.17#ibcon#read 6, iclass 19, count 2 2006.285.15:39:11.17#ibcon#end of sib2, iclass 19, count 2 2006.285.15:39:11.17#ibcon#*mode == 0, iclass 19, count 2 2006.285.15:39:11.17#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.15:39:11.17#ibcon#[25=AT07-04\r\n] 2006.285.15:39:11.17#ibcon#*before write, iclass 19, count 2 2006.285.15:39:11.17#ibcon#enter sib2, iclass 19, count 2 2006.285.15:39:11.17#ibcon#flushed, iclass 19, count 2 2006.285.15:39:11.17#ibcon#about to write, iclass 19, count 2 2006.285.15:39:11.17#ibcon#wrote, iclass 19, count 2 2006.285.15:39:11.17#ibcon#about to read 3, iclass 19, count 2 2006.285.15:39:11.20#ibcon#read 3, iclass 19, count 2 2006.285.15:39:11.20#ibcon#about to read 4, iclass 19, count 2 2006.285.15:39:11.20#ibcon#read 4, iclass 19, count 2 2006.285.15:39:11.20#ibcon#about to read 5, iclass 19, count 2 2006.285.15:39:11.20#ibcon#read 5, iclass 19, count 2 2006.285.15:39:11.20#ibcon#about to read 6, iclass 19, count 2 2006.285.15:39:11.20#ibcon#read 6, iclass 19, count 2 2006.285.15:39:11.20#ibcon#end of sib2, iclass 19, count 2 2006.285.15:39:11.20#ibcon#*after write, iclass 19, count 2 2006.285.15:39:11.20#ibcon#*before return 0, iclass 19, count 2 2006.285.15:39:11.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:39:11.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:39:11.20#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.15:39:11.20#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:11.20#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:39:11.32#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:39:11.32#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:39:11.32#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:39:11.32#ibcon#first serial, iclass 19, count 0 2006.285.15:39:11.32#ibcon#enter sib2, iclass 19, count 0 2006.285.15:39:11.32#ibcon#flushed, iclass 19, count 0 2006.285.15:39:11.32#ibcon#about to write, iclass 19, count 0 2006.285.15:39:11.32#ibcon#wrote, iclass 19, count 0 2006.285.15:39:11.32#ibcon#about to read 3, iclass 19, count 0 2006.285.15:39:11.34#ibcon#read 3, iclass 19, count 0 2006.285.15:39:11.34#ibcon#about to read 4, iclass 19, count 0 2006.285.15:39:11.34#ibcon#read 4, iclass 19, count 0 2006.285.15:39:11.34#ibcon#about to read 5, iclass 19, count 0 2006.285.15:39:11.34#ibcon#read 5, iclass 19, count 0 2006.285.15:39:11.34#ibcon#about to read 6, iclass 19, count 0 2006.285.15:39:11.34#ibcon#read 6, iclass 19, count 0 2006.285.15:39:11.34#ibcon#end of sib2, iclass 19, count 0 2006.285.15:39:11.34#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:39:11.34#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:39:11.34#ibcon#[25=USB\r\n] 2006.285.15:39:11.34#ibcon#*before write, iclass 19, count 0 2006.285.15:39:11.34#ibcon#enter sib2, iclass 19, count 0 2006.285.15:39:11.34#ibcon#flushed, iclass 19, count 0 2006.285.15:39:11.34#ibcon#about to write, iclass 19, count 0 2006.285.15:39:11.34#ibcon#wrote, iclass 19, count 0 2006.285.15:39:11.34#ibcon#about to read 3, iclass 19, count 0 2006.285.15:39:11.37#ibcon#read 3, iclass 19, count 0 2006.285.15:39:11.37#ibcon#about to read 4, iclass 19, count 0 2006.285.15:39:11.37#ibcon#read 4, iclass 19, count 0 2006.285.15:39:11.37#ibcon#about to read 5, iclass 19, count 0 2006.285.15:39:11.37#ibcon#read 5, iclass 19, count 0 2006.285.15:39:11.37#ibcon#about to read 6, iclass 19, count 0 2006.285.15:39:11.37#ibcon#read 6, iclass 19, count 0 2006.285.15:39:11.37#ibcon#end of sib2, iclass 19, count 0 2006.285.15:39:11.37#ibcon#*after write, iclass 19, count 0 2006.285.15:39:11.37#ibcon#*before return 0, iclass 19, count 0 2006.285.15:39:11.37#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:39:11.37#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:39:11.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:39:11.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:39:11.37$vck44/valo=8,884.99 2006.285.15:39:11.37#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.15:39:11.37#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.15:39:11.37#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:11.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:39:11.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:39:11.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:39:11.37#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:39:11.37#ibcon#first serial, iclass 21, count 0 2006.285.15:39:11.37#ibcon#enter sib2, iclass 21, count 0 2006.285.15:39:11.37#ibcon#flushed, iclass 21, count 0 2006.285.15:39:11.37#ibcon#about to write, iclass 21, count 0 2006.285.15:39:11.37#ibcon#wrote, iclass 21, count 0 2006.285.15:39:11.37#ibcon#about to read 3, iclass 21, count 0 2006.285.15:39:11.39#ibcon#read 3, iclass 21, count 0 2006.285.15:39:11.39#ibcon#about to read 4, iclass 21, count 0 2006.285.15:39:11.39#ibcon#read 4, iclass 21, count 0 2006.285.15:39:11.39#ibcon#about to read 5, iclass 21, count 0 2006.285.15:39:11.39#ibcon#read 5, iclass 21, count 0 2006.285.15:39:11.39#ibcon#about to read 6, iclass 21, count 0 2006.285.15:39:11.39#ibcon#read 6, iclass 21, count 0 2006.285.15:39:11.39#ibcon#end of sib2, iclass 21, count 0 2006.285.15:39:11.39#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:39:11.39#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:39:11.39#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.15:39:11.39#ibcon#*before write, iclass 21, count 0 2006.285.15:39:11.39#ibcon#enter sib2, iclass 21, count 0 2006.285.15:39:11.39#ibcon#flushed, iclass 21, count 0 2006.285.15:39:11.39#ibcon#about to write, iclass 21, count 0 2006.285.15:39:11.39#ibcon#wrote, iclass 21, count 0 2006.285.15:39:11.39#ibcon#about to read 3, iclass 21, count 0 2006.285.15:39:11.43#ibcon#read 3, iclass 21, count 0 2006.285.15:39:11.43#ibcon#about to read 4, iclass 21, count 0 2006.285.15:39:11.43#ibcon#read 4, iclass 21, count 0 2006.285.15:39:11.43#ibcon#about to read 5, iclass 21, count 0 2006.285.15:39:11.43#ibcon#read 5, iclass 21, count 0 2006.285.15:39:11.43#ibcon#about to read 6, iclass 21, count 0 2006.285.15:39:11.43#ibcon#read 6, iclass 21, count 0 2006.285.15:39:11.43#ibcon#end of sib2, iclass 21, count 0 2006.285.15:39:11.43#ibcon#*after write, iclass 21, count 0 2006.285.15:39:11.43#ibcon#*before return 0, iclass 21, count 0 2006.285.15:39:11.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:39:11.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:39:11.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:39:11.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:39:11.43$vck44/va=8,3 2006.285.15:39:11.43#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.15:39:11.43#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.15:39:11.43#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:11.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:39:11.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:39:11.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:39:11.49#ibcon#enter wrdev, iclass 23, count 2 2006.285.15:39:11.49#ibcon#first serial, iclass 23, count 2 2006.285.15:39:11.49#ibcon#enter sib2, iclass 23, count 2 2006.285.15:39:11.49#ibcon#flushed, iclass 23, count 2 2006.285.15:39:11.49#ibcon#about to write, iclass 23, count 2 2006.285.15:39:11.49#ibcon#wrote, iclass 23, count 2 2006.285.15:39:11.49#ibcon#about to read 3, iclass 23, count 2 2006.285.15:39:11.51#ibcon#read 3, iclass 23, count 2 2006.285.15:39:11.51#ibcon#about to read 4, iclass 23, count 2 2006.285.15:39:11.51#ibcon#read 4, iclass 23, count 2 2006.285.15:39:11.51#ibcon#about to read 5, iclass 23, count 2 2006.285.15:39:11.51#ibcon#read 5, iclass 23, count 2 2006.285.15:39:11.51#ibcon#about to read 6, iclass 23, count 2 2006.285.15:39:11.51#ibcon#read 6, iclass 23, count 2 2006.285.15:39:11.51#ibcon#end of sib2, iclass 23, count 2 2006.285.15:39:11.51#ibcon#*mode == 0, iclass 23, count 2 2006.285.15:39:11.51#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.15:39:11.51#ibcon#[25=AT08-03\r\n] 2006.285.15:39:11.51#ibcon#*before write, iclass 23, count 2 2006.285.15:39:11.51#ibcon#enter sib2, iclass 23, count 2 2006.285.15:39:11.51#ibcon#flushed, iclass 23, count 2 2006.285.15:39:11.51#ibcon#about to write, iclass 23, count 2 2006.285.15:39:11.51#ibcon#wrote, iclass 23, count 2 2006.285.15:39:11.51#ibcon#about to read 3, iclass 23, count 2 2006.285.15:39:11.54#ibcon#read 3, iclass 23, count 2 2006.285.15:39:11.54#ibcon#about to read 4, iclass 23, count 2 2006.285.15:39:11.54#ibcon#read 4, iclass 23, count 2 2006.285.15:39:11.54#ibcon#about to read 5, iclass 23, count 2 2006.285.15:39:11.54#ibcon#read 5, iclass 23, count 2 2006.285.15:39:11.54#ibcon#about to read 6, iclass 23, count 2 2006.285.15:39:11.54#ibcon#read 6, iclass 23, count 2 2006.285.15:39:11.54#ibcon#end of sib2, iclass 23, count 2 2006.285.15:39:11.54#ibcon#*after write, iclass 23, count 2 2006.285.15:39:11.54#ibcon#*before return 0, iclass 23, count 2 2006.285.15:39:11.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:39:11.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:39:11.54#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.15:39:11.54#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:11.54#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:39:11.66#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:39:11.66#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:39:11.66#ibcon#enter wrdev, iclass 23, count 0 2006.285.15:39:11.66#ibcon#first serial, iclass 23, count 0 2006.285.15:39:11.66#ibcon#enter sib2, iclass 23, count 0 2006.285.15:39:11.66#ibcon#flushed, iclass 23, count 0 2006.285.15:39:11.66#ibcon#about to write, iclass 23, count 0 2006.285.15:39:11.66#ibcon#wrote, iclass 23, count 0 2006.285.15:39:11.66#ibcon#about to read 3, iclass 23, count 0 2006.285.15:39:11.68#ibcon#read 3, iclass 23, count 0 2006.285.15:39:11.68#ibcon#about to read 4, iclass 23, count 0 2006.285.15:39:11.68#ibcon#read 4, iclass 23, count 0 2006.285.15:39:11.68#ibcon#about to read 5, iclass 23, count 0 2006.285.15:39:11.68#ibcon#read 5, iclass 23, count 0 2006.285.15:39:11.68#ibcon#about to read 6, iclass 23, count 0 2006.285.15:39:11.68#ibcon#read 6, iclass 23, count 0 2006.285.15:39:11.68#ibcon#end of sib2, iclass 23, count 0 2006.285.15:39:11.68#ibcon#*mode == 0, iclass 23, count 0 2006.285.15:39:11.68#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.15:39:11.68#ibcon#[25=USB\r\n] 2006.285.15:39:11.68#ibcon#*before write, iclass 23, count 0 2006.285.15:39:11.68#ibcon#enter sib2, iclass 23, count 0 2006.285.15:39:11.68#ibcon#flushed, iclass 23, count 0 2006.285.15:39:11.68#ibcon#about to write, iclass 23, count 0 2006.285.15:39:11.68#ibcon#wrote, iclass 23, count 0 2006.285.15:39:11.68#ibcon#about to read 3, iclass 23, count 0 2006.285.15:39:11.71#ibcon#read 3, iclass 23, count 0 2006.285.15:39:11.71#ibcon#about to read 4, iclass 23, count 0 2006.285.15:39:11.71#ibcon#read 4, iclass 23, count 0 2006.285.15:39:11.71#ibcon#about to read 5, iclass 23, count 0 2006.285.15:39:11.71#ibcon#read 5, iclass 23, count 0 2006.285.15:39:11.71#ibcon#about to read 6, iclass 23, count 0 2006.285.15:39:11.71#ibcon#read 6, iclass 23, count 0 2006.285.15:39:11.71#ibcon#end of sib2, iclass 23, count 0 2006.285.15:39:11.71#ibcon#*after write, iclass 23, count 0 2006.285.15:39:11.71#ibcon#*before return 0, iclass 23, count 0 2006.285.15:39:11.71#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:39:11.71#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:39:11.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.15:39:11.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.15:39:11.71$vck44/vblo=1,629.99 2006.285.15:39:11.71#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.15:39:11.71#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.15:39:11.71#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:11.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:39:11.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:39:11.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:39:11.71#ibcon#enter wrdev, iclass 25, count 0 2006.285.15:39:11.71#ibcon#first serial, iclass 25, count 0 2006.285.15:39:11.71#ibcon#enter sib2, iclass 25, count 0 2006.285.15:39:11.71#ibcon#flushed, iclass 25, count 0 2006.285.15:39:11.71#ibcon#about to write, iclass 25, count 0 2006.285.15:39:11.71#ibcon#wrote, iclass 25, count 0 2006.285.15:39:11.71#ibcon#about to read 3, iclass 25, count 0 2006.285.15:39:11.73#ibcon#read 3, iclass 25, count 0 2006.285.15:39:11.73#ibcon#about to read 4, iclass 25, count 0 2006.285.15:39:11.73#ibcon#read 4, iclass 25, count 0 2006.285.15:39:11.73#ibcon#about to read 5, iclass 25, count 0 2006.285.15:39:11.73#ibcon#read 5, iclass 25, count 0 2006.285.15:39:11.73#ibcon#about to read 6, iclass 25, count 0 2006.285.15:39:11.73#ibcon#read 6, iclass 25, count 0 2006.285.15:39:11.73#ibcon#end of sib2, iclass 25, count 0 2006.285.15:39:11.73#ibcon#*mode == 0, iclass 25, count 0 2006.285.15:39:11.73#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.15:39:11.73#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.15:39:11.73#ibcon#*before write, iclass 25, count 0 2006.285.15:39:11.73#ibcon#enter sib2, iclass 25, count 0 2006.285.15:39:11.73#ibcon#flushed, iclass 25, count 0 2006.285.15:39:11.73#ibcon#about to write, iclass 25, count 0 2006.285.15:39:11.73#ibcon#wrote, iclass 25, count 0 2006.285.15:39:11.73#ibcon#about to read 3, iclass 25, count 0 2006.285.15:39:11.77#ibcon#read 3, iclass 25, count 0 2006.285.15:39:11.77#ibcon#about to read 4, iclass 25, count 0 2006.285.15:39:11.77#ibcon#read 4, iclass 25, count 0 2006.285.15:39:11.77#ibcon#about to read 5, iclass 25, count 0 2006.285.15:39:11.77#ibcon#read 5, iclass 25, count 0 2006.285.15:39:11.77#ibcon#about to read 6, iclass 25, count 0 2006.285.15:39:11.77#ibcon#read 6, iclass 25, count 0 2006.285.15:39:11.77#ibcon#end of sib2, iclass 25, count 0 2006.285.15:39:11.77#ibcon#*after write, iclass 25, count 0 2006.285.15:39:11.77#ibcon#*before return 0, iclass 25, count 0 2006.285.15:39:11.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:39:11.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:39:11.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.15:39:11.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.15:39:11.77$vck44/vb=1,4 2006.285.15:39:11.77#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.15:39:11.77#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.15:39:11.77#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:11.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:39:11.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:39:11.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:39:11.77#ibcon#enter wrdev, iclass 27, count 2 2006.285.15:39:11.77#ibcon#first serial, iclass 27, count 2 2006.285.15:39:11.77#ibcon#enter sib2, iclass 27, count 2 2006.285.15:39:11.77#ibcon#flushed, iclass 27, count 2 2006.285.15:39:11.77#ibcon#about to write, iclass 27, count 2 2006.285.15:39:11.77#ibcon#wrote, iclass 27, count 2 2006.285.15:39:11.77#ibcon#about to read 3, iclass 27, count 2 2006.285.15:39:11.79#ibcon#read 3, iclass 27, count 2 2006.285.15:39:11.79#ibcon#about to read 4, iclass 27, count 2 2006.285.15:39:11.79#ibcon#read 4, iclass 27, count 2 2006.285.15:39:11.79#ibcon#about to read 5, iclass 27, count 2 2006.285.15:39:11.79#ibcon#read 5, iclass 27, count 2 2006.285.15:39:11.79#ibcon#about to read 6, iclass 27, count 2 2006.285.15:39:11.79#ibcon#read 6, iclass 27, count 2 2006.285.15:39:11.79#ibcon#end of sib2, iclass 27, count 2 2006.285.15:39:11.79#ibcon#*mode == 0, iclass 27, count 2 2006.285.15:39:11.79#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.15:39:11.79#ibcon#[27=AT01-04\r\n] 2006.285.15:39:11.79#ibcon#*before write, iclass 27, count 2 2006.285.15:39:11.79#ibcon#enter sib2, iclass 27, count 2 2006.285.15:39:11.79#ibcon#flushed, iclass 27, count 2 2006.285.15:39:11.79#ibcon#about to write, iclass 27, count 2 2006.285.15:39:11.79#ibcon#wrote, iclass 27, count 2 2006.285.15:39:11.79#ibcon#about to read 3, iclass 27, count 2 2006.285.15:39:11.82#ibcon#read 3, iclass 27, count 2 2006.285.15:39:11.82#ibcon#about to read 4, iclass 27, count 2 2006.285.15:39:11.82#ibcon#read 4, iclass 27, count 2 2006.285.15:39:11.82#ibcon#about to read 5, iclass 27, count 2 2006.285.15:39:11.82#ibcon#read 5, iclass 27, count 2 2006.285.15:39:11.82#ibcon#about to read 6, iclass 27, count 2 2006.285.15:39:11.82#ibcon#read 6, iclass 27, count 2 2006.285.15:39:11.82#ibcon#end of sib2, iclass 27, count 2 2006.285.15:39:11.82#ibcon#*after write, iclass 27, count 2 2006.285.15:39:11.82#ibcon#*before return 0, iclass 27, count 2 2006.285.15:39:11.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:39:11.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:39:11.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.15:39:11.82#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:11.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:39:11.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:39:11.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:39:11.94#ibcon#enter wrdev, iclass 27, count 0 2006.285.15:39:11.94#ibcon#first serial, iclass 27, count 0 2006.285.15:39:11.94#ibcon#enter sib2, iclass 27, count 0 2006.285.15:39:11.94#ibcon#flushed, iclass 27, count 0 2006.285.15:39:11.94#ibcon#about to write, iclass 27, count 0 2006.285.15:39:11.94#ibcon#wrote, iclass 27, count 0 2006.285.15:39:11.94#ibcon#about to read 3, iclass 27, count 0 2006.285.15:39:11.96#ibcon#read 3, iclass 27, count 0 2006.285.15:39:11.96#ibcon#about to read 4, iclass 27, count 0 2006.285.15:39:11.96#ibcon#read 4, iclass 27, count 0 2006.285.15:39:11.96#ibcon#about to read 5, iclass 27, count 0 2006.285.15:39:11.96#ibcon#read 5, iclass 27, count 0 2006.285.15:39:11.96#ibcon#about to read 6, iclass 27, count 0 2006.285.15:39:11.96#ibcon#read 6, iclass 27, count 0 2006.285.15:39:11.96#ibcon#end of sib2, iclass 27, count 0 2006.285.15:39:11.96#ibcon#*mode == 0, iclass 27, count 0 2006.285.15:39:11.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.15:39:11.96#ibcon#[27=USB\r\n] 2006.285.15:39:11.96#ibcon#*before write, iclass 27, count 0 2006.285.15:39:11.96#ibcon#enter sib2, iclass 27, count 0 2006.285.15:39:11.96#ibcon#flushed, iclass 27, count 0 2006.285.15:39:11.96#ibcon#about to write, iclass 27, count 0 2006.285.15:39:11.96#ibcon#wrote, iclass 27, count 0 2006.285.15:39:11.96#ibcon#about to read 3, iclass 27, count 0 2006.285.15:39:11.99#ibcon#read 3, iclass 27, count 0 2006.285.15:39:12.03#ibcon#about to read 4, iclass 27, count 0 2006.285.15:39:12.03#ibcon#read 4, iclass 27, count 0 2006.285.15:39:12.03#ibcon#about to read 5, iclass 27, count 0 2006.285.15:39:12.03#ibcon#read 5, iclass 27, count 0 2006.285.15:39:12.03#ibcon#about to read 6, iclass 27, count 0 2006.285.15:39:12.03#ibcon#read 6, iclass 27, count 0 2006.285.15:39:12.03#ibcon#end of sib2, iclass 27, count 0 2006.285.15:39:12.03#ibcon#*after write, iclass 27, count 0 2006.285.15:39:12.03#ibcon#*before return 0, iclass 27, count 0 2006.285.15:39:12.03#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:39:12.03#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:39:12.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.15:39:12.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.15:39:12.04$vck44/vblo=2,634.99 2006.285.15:39:12.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.15:39:12.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.15:39:12.04#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:12.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:39:12.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:39:12.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:39:12.04#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:39:12.04#ibcon#first serial, iclass 29, count 0 2006.285.15:39:12.04#ibcon#enter sib2, iclass 29, count 0 2006.285.15:39:12.04#ibcon#flushed, iclass 29, count 0 2006.285.15:39:12.04#ibcon#about to write, iclass 29, count 0 2006.285.15:39:12.04#ibcon#wrote, iclass 29, count 0 2006.285.15:39:12.04#ibcon#about to read 3, iclass 29, count 0 2006.285.15:39:12.05#ibcon#read 3, iclass 29, count 0 2006.285.15:39:12.05#ibcon#about to read 4, iclass 29, count 0 2006.285.15:39:12.05#ibcon#read 4, iclass 29, count 0 2006.285.15:39:12.05#ibcon#about to read 5, iclass 29, count 0 2006.285.15:39:12.05#ibcon#read 5, iclass 29, count 0 2006.285.15:39:12.05#ibcon#about to read 6, iclass 29, count 0 2006.285.15:39:12.05#ibcon#read 6, iclass 29, count 0 2006.285.15:39:12.05#ibcon#end of sib2, iclass 29, count 0 2006.285.15:39:12.05#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:39:12.05#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:39:12.05#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.15:39:12.05#ibcon#*before write, iclass 29, count 0 2006.285.15:39:12.05#ibcon#enter sib2, iclass 29, count 0 2006.285.15:39:12.05#ibcon#flushed, iclass 29, count 0 2006.285.15:39:12.05#ibcon#about to write, iclass 29, count 0 2006.285.15:39:12.05#ibcon#wrote, iclass 29, count 0 2006.285.15:39:12.05#ibcon#about to read 3, iclass 29, count 0 2006.285.15:39:12.09#ibcon#read 3, iclass 29, count 0 2006.285.15:39:12.09#ibcon#about to read 4, iclass 29, count 0 2006.285.15:39:12.09#ibcon#read 4, iclass 29, count 0 2006.285.15:39:12.09#ibcon#about to read 5, iclass 29, count 0 2006.285.15:39:12.09#ibcon#read 5, iclass 29, count 0 2006.285.15:39:12.09#ibcon#about to read 6, iclass 29, count 0 2006.285.15:39:12.09#ibcon#read 6, iclass 29, count 0 2006.285.15:39:12.09#ibcon#end of sib2, iclass 29, count 0 2006.285.15:39:12.09#ibcon#*after write, iclass 29, count 0 2006.285.15:39:12.09#ibcon#*before return 0, iclass 29, count 0 2006.285.15:39:12.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:39:12.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:39:12.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:39:12.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:39:12.09$vck44/vb=2,5 2006.285.15:39:12.09#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.15:39:12.09#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.15:39:12.09#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:12.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:39:12.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:39:12.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:39:12.15#ibcon#enter wrdev, iclass 31, count 2 2006.285.15:39:12.15#ibcon#first serial, iclass 31, count 2 2006.285.15:39:12.15#ibcon#enter sib2, iclass 31, count 2 2006.285.15:39:12.15#ibcon#flushed, iclass 31, count 2 2006.285.15:39:12.15#ibcon#about to write, iclass 31, count 2 2006.285.15:39:12.15#ibcon#wrote, iclass 31, count 2 2006.285.15:39:12.15#ibcon#about to read 3, iclass 31, count 2 2006.285.15:39:12.17#ibcon#read 3, iclass 31, count 2 2006.285.15:39:12.17#ibcon#about to read 4, iclass 31, count 2 2006.285.15:39:12.17#ibcon#read 4, iclass 31, count 2 2006.285.15:39:12.17#ibcon#about to read 5, iclass 31, count 2 2006.285.15:39:12.17#ibcon#read 5, iclass 31, count 2 2006.285.15:39:12.17#ibcon#about to read 6, iclass 31, count 2 2006.285.15:39:12.17#ibcon#read 6, iclass 31, count 2 2006.285.15:39:12.17#ibcon#end of sib2, iclass 31, count 2 2006.285.15:39:12.17#ibcon#*mode == 0, iclass 31, count 2 2006.285.15:39:12.17#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.15:39:12.17#ibcon#[27=AT02-05\r\n] 2006.285.15:39:12.17#ibcon#*before write, iclass 31, count 2 2006.285.15:39:12.17#ibcon#enter sib2, iclass 31, count 2 2006.285.15:39:12.17#ibcon#flushed, iclass 31, count 2 2006.285.15:39:12.17#ibcon#about to write, iclass 31, count 2 2006.285.15:39:12.17#ibcon#wrote, iclass 31, count 2 2006.285.15:39:12.17#ibcon#about to read 3, iclass 31, count 2 2006.285.15:39:12.20#ibcon#read 3, iclass 31, count 2 2006.285.15:39:12.20#ibcon#about to read 4, iclass 31, count 2 2006.285.15:39:12.20#ibcon#read 4, iclass 31, count 2 2006.285.15:39:12.20#ibcon#about to read 5, iclass 31, count 2 2006.285.15:39:12.20#ibcon#read 5, iclass 31, count 2 2006.285.15:39:12.20#ibcon#about to read 6, iclass 31, count 2 2006.285.15:39:12.20#ibcon#read 6, iclass 31, count 2 2006.285.15:39:12.20#ibcon#end of sib2, iclass 31, count 2 2006.285.15:39:12.20#ibcon#*after write, iclass 31, count 2 2006.285.15:39:12.20#ibcon#*before return 0, iclass 31, count 2 2006.285.15:39:12.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:39:12.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:39:12.20#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.15:39:12.20#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:12.20#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:39:12.32#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:39:12.32#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:39:12.32#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:39:12.32#ibcon#first serial, iclass 31, count 0 2006.285.15:39:12.32#ibcon#enter sib2, iclass 31, count 0 2006.285.15:39:12.32#ibcon#flushed, iclass 31, count 0 2006.285.15:39:12.32#ibcon#about to write, iclass 31, count 0 2006.285.15:39:12.32#ibcon#wrote, iclass 31, count 0 2006.285.15:39:12.32#ibcon#about to read 3, iclass 31, count 0 2006.285.15:39:12.34#ibcon#read 3, iclass 31, count 0 2006.285.15:39:12.34#ibcon#about to read 4, iclass 31, count 0 2006.285.15:39:12.34#ibcon#read 4, iclass 31, count 0 2006.285.15:39:12.34#ibcon#about to read 5, iclass 31, count 0 2006.285.15:39:12.34#ibcon#read 5, iclass 31, count 0 2006.285.15:39:12.34#ibcon#about to read 6, iclass 31, count 0 2006.285.15:39:12.34#ibcon#read 6, iclass 31, count 0 2006.285.15:39:12.34#ibcon#end of sib2, iclass 31, count 0 2006.285.15:39:12.34#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:39:12.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:39:12.34#ibcon#[27=USB\r\n] 2006.285.15:39:12.34#ibcon#*before write, iclass 31, count 0 2006.285.15:39:12.34#ibcon#enter sib2, iclass 31, count 0 2006.285.15:39:12.34#ibcon#flushed, iclass 31, count 0 2006.285.15:39:12.34#ibcon#about to write, iclass 31, count 0 2006.285.15:39:12.34#ibcon#wrote, iclass 31, count 0 2006.285.15:39:12.34#ibcon#about to read 3, iclass 31, count 0 2006.285.15:39:12.37#ibcon#read 3, iclass 31, count 0 2006.285.15:39:12.37#ibcon#about to read 4, iclass 31, count 0 2006.285.15:39:12.37#ibcon#read 4, iclass 31, count 0 2006.285.15:39:12.37#ibcon#about to read 5, iclass 31, count 0 2006.285.15:39:12.37#ibcon#read 5, iclass 31, count 0 2006.285.15:39:12.37#ibcon#about to read 6, iclass 31, count 0 2006.285.15:39:12.37#ibcon#read 6, iclass 31, count 0 2006.285.15:39:12.37#ibcon#end of sib2, iclass 31, count 0 2006.285.15:39:12.37#ibcon#*after write, iclass 31, count 0 2006.285.15:39:12.37#ibcon#*before return 0, iclass 31, count 0 2006.285.15:39:12.37#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:39:12.37#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:39:12.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:39:12.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:39:12.37$vck44/vblo=3,649.99 2006.285.15:39:12.37#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.15:39:12.37#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.15:39:12.37#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:12.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:39:12.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:39:12.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:39:12.37#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:39:12.37#ibcon#first serial, iclass 33, count 0 2006.285.15:39:12.37#ibcon#enter sib2, iclass 33, count 0 2006.285.15:39:12.37#ibcon#flushed, iclass 33, count 0 2006.285.15:39:12.37#ibcon#about to write, iclass 33, count 0 2006.285.15:39:12.37#ibcon#wrote, iclass 33, count 0 2006.285.15:39:12.37#ibcon#about to read 3, iclass 33, count 0 2006.285.15:39:12.39#ibcon#read 3, iclass 33, count 0 2006.285.15:39:12.39#ibcon#about to read 4, iclass 33, count 0 2006.285.15:39:12.39#ibcon#read 4, iclass 33, count 0 2006.285.15:39:12.39#ibcon#about to read 5, iclass 33, count 0 2006.285.15:39:12.39#ibcon#read 5, iclass 33, count 0 2006.285.15:39:12.39#ibcon#about to read 6, iclass 33, count 0 2006.285.15:39:12.39#ibcon#read 6, iclass 33, count 0 2006.285.15:39:12.39#ibcon#end of sib2, iclass 33, count 0 2006.285.15:39:12.39#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:39:12.39#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:39:12.39#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.15:39:12.39#ibcon#*before write, iclass 33, count 0 2006.285.15:39:12.39#ibcon#enter sib2, iclass 33, count 0 2006.285.15:39:12.39#ibcon#flushed, iclass 33, count 0 2006.285.15:39:12.39#ibcon#about to write, iclass 33, count 0 2006.285.15:39:12.39#ibcon#wrote, iclass 33, count 0 2006.285.15:39:12.39#ibcon#about to read 3, iclass 33, count 0 2006.285.15:39:12.43#ibcon#read 3, iclass 33, count 0 2006.285.15:39:12.43#ibcon#about to read 4, iclass 33, count 0 2006.285.15:39:12.43#ibcon#read 4, iclass 33, count 0 2006.285.15:39:12.43#ibcon#about to read 5, iclass 33, count 0 2006.285.15:39:12.43#ibcon#read 5, iclass 33, count 0 2006.285.15:39:12.43#ibcon#about to read 6, iclass 33, count 0 2006.285.15:39:12.43#ibcon#read 6, iclass 33, count 0 2006.285.15:39:12.43#ibcon#end of sib2, iclass 33, count 0 2006.285.15:39:12.43#ibcon#*after write, iclass 33, count 0 2006.285.15:39:12.43#ibcon#*before return 0, iclass 33, count 0 2006.285.15:39:12.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:39:12.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:39:12.43#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:39:12.43#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:39:12.43$vck44/vb=3,4 2006.285.15:39:12.43#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.15:39:12.43#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.15:39:12.43#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:12.43#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:39:12.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:39:12.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:39:12.49#ibcon#enter wrdev, iclass 35, count 2 2006.285.15:39:12.49#ibcon#first serial, iclass 35, count 2 2006.285.15:39:12.49#ibcon#enter sib2, iclass 35, count 2 2006.285.15:39:12.49#ibcon#flushed, iclass 35, count 2 2006.285.15:39:12.49#ibcon#about to write, iclass 35, count 2 2006.285.15:39:12.49#ibcon#wrote, iclass 35, count 2 2006.285.15:39:12.49#ibcon#about to read 3, iclass 35, count 2 2006.285.15:39:12.51#ibcon#read 3, iclass 35, count 2 2006.285.15:39:12.51#ibcon#about to read 4, iclass 35, count 2 2006.285.15:39:12.51#ibcon#read 4, iclass 35, count 2 2006.285.15:39:12.51#ibcon#about to read 5, iclass 35, count 2 2006.285.15:39:12.51#ibcon#read 5, iclass 35, count 2 2006.285.15:39:12.51#ibcon#about to read 6, iclass 35, count 2 2006.285.15:39:12.51#ibcon#read 6, iclass 35, count 2 2006.285.15:39:12.51#ibcon#end of sib2, iclass 35, count 2 2006.285.15:39:12.51#ibcon#*mode == 0, iclass 35, count 2 2006.285.15:39:12.51#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.15:39:12.51#ibcon#[27=AT03-04\r\n] 2006.285.15:39:12.51#ibcon#*before write, iclass 35, count 2 2006.285.15:39:12.51#ibcon#enter sib2, iclass 35, count 2 2006.285.15:39:12.51#ibcon#flushed, iclass 35, count 2 2006.285.15:39:12.51#ibcon#about to write, iclass 35, count 2 2006.285.15:39:12.51#ibcon#wrote, iclass 35, count 2 2006.285.15:39:12.51#ibcon#about to read 3, iclass 35, count 2 2006.285.15:39:12.54#ibcon#read 3, iclass 35, count 2 2006.285.15:39:12.54#ibcon#about to read 4, iclass 35, count 2 2006.285.15:39:12.54#ibcon#read 4, iclass 35, count 2 2006.285.15:39:12.54#ibcon#about to read 5, iclass 35, count 2 2006.285.15:39:12.54#ibcon#read 5, iclass 35, count 2 2006.285.15:39:12.54#ibcon#about to read 6, iclass 35, count 2 2006.285.15:39:12.54#ibcon#read 6, iclass 35, count 2 2006.285.15:39:12.54#ibcon#end of sib2, iclass 35, count 2 2006.285.15:39:12.54#ibcon#*after write, iclass 35, count 2 2006.285.15:39:12.54#ibcon#*before return 0, iclass 35, count 2 2006.285.15:39:12.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:39:12.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:39:12.54#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.15:39:12.54#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:12.54#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:39:12.66#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:39:12.66#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:39:12.66#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:39:12.66#ibcon#first serial, iclass 35, count 0 2006.285.15:39:12.66#ibcon#enter sib2, iclass 35, count 0 2006.285.15:39:12.66#ibcon#flushed, iclass 35, count 0 2006.285.15:39:12.66#ibcon#about to write, iclass 35, count 0 2006.285.15:39:12.66#ibcon#wrote, iclass 35, count 0 2006.285.15:39:12.66#ibcon#about to read 3, iclass 35, count 0 2006.285.15:39:12.68#ibcon#read 3, iclass 35, count 0 2006.285.15:39:12.68#ibcon#about to read 4, iclass 35, count 0 2006.285.15:39:12.68#ibcon#read 4, iclass 35, count 0 2006.285.15:39:12.68#ibcon#about to read 5, iclass 35, count 0 2006.285.15:39:12.68#ibcon#read 5, iclass 35, count 0 2006.285.15:39:12.68#ibcon#about to read 6, iclass 35, count 0 2006.285.15:39:12.68#ibcon#read 6, iclass 35, count 0 2006.285.15:39:12.68#ibcon#end of sib2, iclass 35, count 0 2006.285.15:39:12.68#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:39:12.68#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:39:12.68#ibcon#[27=USB\r\n] 2006.285.15:39:12.68#ibcon#*before write, iclass 35, count 0 2006.285.15:39:12.68#ibcon#enter sib2, iclass 35, count 0 2006.285.15:39:12.68#ibcon#flushed, iclass 35, count 0 2006.285.15:39:12.68#ibcon#about to write, iclass 35, count 0 2006.285.15:39:12.68#ibcon#wrote, iclass 35, count 0 2006.285.15:39:12.68#ibcon#about to read 3, iclass 35, count 0 2006.285.15:39:12.71#ibcon#read 3, iclass 35, count 0 2006.285.15:39:12.71#ibcon#about to read 4, iclass 35, count 0 2006.285.15:39:12.71#ibcon#read 4, iclass 35, count 0 2006.285.15:39:12.71#ibcon#about to read 5, iclass 35, count 0 2006.285.15:39:12.71#ibcon#read 5, iclass 35, count 0 2006.285.15:39:12.71#ibcon#about to read 6, iclass 35, count 0 2006.285.15:39:12.71#ibcon#read 6, iclass 35, count 0 2006.285.15:39:12.71#ibcon#end of sib2, iclass 35, count 0 2006.285.15:39:12.71#ibcon#*after write, iclass 35, count 0 2006.285.15:39:12.71#ibcon#*before return 0, iclass 35, count 0 2006.285.15:39:12.71#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:39:12.71#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:39:12.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:39:12.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:39:12.71$vck44/vblo=4,679.99 2006.285.15:39:12.71#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.15:39:12.71#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.15:39:12.71#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:12.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:39:12.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:39:12.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:39:12.71#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:39:12.71#ibcon#first serial, iclass 37, count 0 2006.285.15:39:12.71#ibcon#enter sib2, iclass 37, count 0 2006.285.15:39:12.71#ibcon#flushed, iclass 37, count 0 2006.285.15:39:12.71#ibcon#about to write, iclass 37, count 0 2006.285.15:39:12.71#ibcon#wrote, iclass 37, count 0 2006.285.15:39:12.71#ibcon#about to read 3, iclass 37, count 0 2006.285.15:39:12.73#ibcon#read 3, iclass 37, count 0 2006.285.15:39:12.73#ibcon#about to read 4, iclass 37, count 0 2006.285.15:39:12.73#ibcon#read 4, iclass 37, count 0 2006.285.15:39:12.73#ibcon#about to read 5, iclass 37, count 0 2006.285.15:39:12.73#ibcon#read 5, iclass 37, count 0 2006.285.15:39:12.73#ibcon#about to read 6, iclass 37, count 0 2006.285.15:39:12.73#ibcon#read 6, iclass 37, count 0 2006.285.15:39:12.73#ibcon#end of sib2, iclass 37, count 0 2006.285.15:39:12.73#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:39:12.73#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:39:12.73#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.15:39:12.73#ibcon#*before write, iclass 37, count 0 2006.285.15:39:12.73#ibcon#enter sib2, iclass 37, count 0 2006.285.15:39:12.73#ibcon#flushed, iclass 37, count 0 2006.285.15:39:12.73#ibcon#about to write, iclass 37, count 0 2006.285.15:39:12.73#ibcon#wrote, iclass 37, count 0 2006.285.15:39:12.73#ibcon#about to read 3, iclass 37, count 0 2006.285.15:39:12.77#ibcon#read 3, iclass 37, count 0 2006.285.15:39:12.77#ibcon#about to read 4, iclass 37, count 0 2006.285.15:39:12.77#ibcon#read 4, iclass 37, count 0 2006.285.15:39:12.77#ibcon#about to read 5, iclass 37, count 0 2006.285.15:39:12.77#ibcon#read 5, iclass 37, count 0 2006.285.15:39:12.77#ibcon#about to read 6, iclass 37, count 0 2006.285.15:39:12.77#ibcon#read 6, iclass 37, count 0 2006.285.15:39:12.77#ibcon#end of sib2, iclass 37, count 0 2006.285.15:39:12.77#ibcon#*after write, iclass 37, count 0 2006.285.15:39:12.77#ibcon#*before return 0, iclass 37, count 0 2006.285.15:39:12.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:39:12.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:39:12.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:39:12.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:39:12.77$vck44/vb=4,5 2006.285.15:39:12.77#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.15:39:12.77#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.15:39:12.77#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:12.77#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:39:12.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:39:12.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:39:12.83#ibcon#enter wrdev, iclass 39, count 2 2006.285.15:39:12.83#ibcon#first serial, iclass 39, count 2 2006.285.15:39:12.83#ibcon#enter sib2, iclass 39, count 2 2006.285.15:39:12.83#ibcon#flushed, iclass 39, count 2 2006.285.15:39:12.83#ibcon#about to write, iclass 39, count 2 2006.285.15:39:12.83#ibcon#wrote, iclass 39, count 2 2006.285.15:39:12.83#ibcon#about to read 3, iclass 39, count 2 2006.285.15:39:12.85#ibcon#read 3, iclass 39, count 2 2006.285.15:39:12.85#ibcon#about to read 4, iclass 39, count 2 2006.285.15:39:12.85#ibcon#read 4, iclass 39, count 2 2006.285.15:39:12.85#ibcon#about to read 5, iclass 39, count 2 2006.285.15:39:12.85#ibcon#read 5, iclass 39, count 2 2006.285.15:39:12.85#ibcon#about to read 6, iclass 39, count 2 2006.285.15:39:12.85#ibcon#read 6, iclass 39, count 2 2006.285.15:39:12.85#ibcon#end of sib2, iclass 39, count 2 2006.285.15:39:12.85#ibcon#*mode == 0, iclass 39, count 2 2006.285.15:39:12.85#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.15:39:12.85#ibcon#[27=AT04-05\r\n] 2006.285.15:39:12.85#ibcon#*before write, iclass 39, count 2 2006.285.15:39:12.85#ibcon#enter sib2, iclass 39, count 2 2006.285.15:39:12.85#ibcon#flushed, iclass 39, count 2 2006.285.15:39:12.85#ibcon#about to write, iclass 39, count 2 2006.285.15:39:12.85#ibcon#wrote, iclass 39, count 2 2006.285.15:39:12.85#ibcon#about to read 3, iclass 39, count 2 2006.285.15:39:12.88#ibcon#read 3, iclass 39, count 2 2006.285.15:39:12.88#ibcon#about to read 4, iclass 39, count 2 2006.285.15:39:12.88#ibcon#read 4, iclass 39, count 2 2006.285.15:39:12.88#ibcon#about to read 5, iclass 39, count 2 2006.285.15:39:12.88#ibcon#read 5, iclass 39, count 2 2006.285.15:39:12.88#ibcon#about to read 6, iclass 39, count 2 2006.285.15:39:12.88#ibcon#read 6, iclass 39, count 2 2006.285.15:39:12.88#ibcon#end of sib2, iclass 39, count 2 2006.285.15:39:12.88#ibcon#*after write, iclass 39, count 2 2006.285.15:39:12.88#ibcon#*before return 0, iclass 39, count 2 2006.285.15:39:12.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:39:12.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:39:12.88#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.15:39:12.88#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:12.88#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:39:13.00#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:39:13.09#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:39:13.09#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:39:13.09#ibcon#first serial, iclass 39, count 0 2006.285.15:39:13.09#ibcon#enter sib2, iclass 39, count 0 2006.285.15:39:13.09#ibcon#flushed, iclass 39, count 0 2006.285.15:39:13.09#ibcon#about to write, iclass 39, count 0 2006.285.15:39:13.09#ibcon#wrote, iclass 39, count 0 2006.285.15:39:13.09#ibcon#about to read 3, iclass 39, count 0 2006.285.15:39:13.10#ibcon#read 3, iclass 39, count 0 2006.285.15:39:13.10#ibcon#about to read 4, iclass 39, count 0 2006.285.15:39:13.10#ibcon#read 4, iclass 39, count 0 2006.285.15:39:13.10#ibcon#about to read 5, iclass 39, count 0 2006.285.15:39:13.10#ibcon#read 5, iclass 39, count 0 2006.285.15:39:13.10#ibcon#about to read 6, iclass 39, count 0 2006.285.15:39:13.10#ibcon#read 6, iclass 39, count 0 2006.285.15:39:13.10#ibcon#end of sib2, iclass 39, count 0 2006.285.15:39:13.10#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:39:13.10#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:39:13.10#ibcon#[27=USB\r\n] 2006.285.15:39:13.10#ibcon#*before write, iclass 39, count 0 2006.285.15:39:13.10#ibcon#enter sib2, iclass 39, count 0 2006.285.15:39:13.10#ibcon#flushed, iclass 39, count 0 2006.285.15:39:13.10#ibcon#about to write, iclass 39, count 0 2006.285.15:39:13.10#ibcon#wrote, iclass 39, count 0 2006.285.15:39:13.10#ibcon#about to read 3, iclass 39, count 0 2006.285.15:39:13.13#ibcon#read 3, iclass 39, count 0 2006.285.15:39:13.13#ibcon#about to read 4, iclass 39, count 0 2006.285.15:39:13.13#ibcon#read 4, iclass 39, count 0 2006.285.15:39:13.13#ibcon#about to read 5, iclass 39, count 0 2006.285.15:39:13.13#ibcon#read 5, iclass 39, count 0 2006.285.15:39:13.13#ibcon#about to read 6, iclass 39, count 0 2006.285.15:39:13.13#ibcon#read 6, iclass 39, count 0 2006.285.15:39:13.13#ibcon#end of sib2, iclass 39, count 0 2006.285.15:39:13.13#ibcon#*after write, iclass 39, count 0 2006.285.15:39:13.13#ibcon#*before return 0, iclass 39, count 0 2006.285.15:39:13.13#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:39:13.13#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:39:13.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:39:13.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:39:13.13$vck44/vblo=5,709.99 2006.285.15:39:13.13#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.15:39:13.13#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.15:39:13.13#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:13.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:39:13.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:39:13.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:39:13.13#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:39:13.13#ibcon#first serial, iclass 3, count 0 2006.285.15:39:13.13#ibcon#enter sib2, iclass 3, count 0 2006.285.15:39:13.13#ibcon#flushed, iclass 3, count 0 2006.285.15:39:13.13#ibcon#about to write, iclass 3, count 0 2006.285.15:39:13.13#ibcon#wrote, iclass 3, count 0 2006.285.15:39:13.13#ibcon#about to read 3, iclass 3, count 0 2006.285.15:39:13.15#ibcon#read 3, iclass 3, count 0 2006.285.15:39:13.15#ibcon#about to read 4, iclass 3, count 0 2006.285.15:39:13.15#ibcon#read 4, iclass 3, count 0 2006.285.15:39:13.15#ibcon#about to read 5, iclass 3, count 0 2006.285.15:39:13.15#ibcon#read 5, iclass 3, count 0 2006.285.15:39:13.15#ibcon#about to read 6, iclass 3, count 0 2006.285.15:39:13.15#ibcon#read 6, iclass 3, count 0 2006.285.15:39:13.15#ibcon#end of sib2, iclass 3, count 0 2006.285.15:39:13.15#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:39:13.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:39:13.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.15:39:13.15#ibcon#*before write, iclass 3, count 0 2006.285.15:39:13.15#ibcon#enter sib2, iclass 3, count 0 2006.285.15:39:13.15#ibcon#flushed, iclass 3, count 0 2006.285.15:39:13.15#ibcon#about to write, iclass 3, count 0 2006.285.15:39:13.15#ibcon#wrote, iclass 3, count 0 2006.285.15:39:13.15#ibcon#about to read 3, iclass 3, count 0 2006.285.15:39:13.19#ibcon#read 3, iclass 3, count 0 2006.285.15:39:13.19#ibcon#about to read 4, iclass 3, count 0 2006.285.15:39:13.19#ibcon#read 4, iclass 3, count 0 2006.285.15:39:13.19#ibcon#about to read 5, iclass 3, count 0 2006.285.15:39:13.19#ibcon#read 5, iclass 3, count 0 2006.285.15:39:13.19#ibcon#about to read 6, iclass 3, count 0 2006.285.15:39:13.19#ibcon#read 6, iclass 3, count 0 2006.285.15:39:13.19#ibcon#end of sib2, iclass 3, count 0 2006.285.15:39:13.19#ibcon#*after write, iclass 3, count 0 2006.285.15:39:13.19#ibcon#*before return 0, iclass 3, count 0 2006.285.15:39:13.19#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:39:13.19#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:39:13.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:39:13.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:39:13.19$vck44/vb=5,4 2006.285.15:39:13.19#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.15:39:13.19#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.15:39:13.19#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:13.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:39:13.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:39:13.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:39:13.25#ibcon#enter wrdev, iclass 5, count 2 2006.285.15:39:13.25#ibcon#first serial, iclass 5, count 2 2006.285.15:39:13.25#ibcon#enter sib2, iclass 5, count 2 2006.285.15:39:13.25#ibcon#flushed, iclass 5, count 2 2006.285.15:39:13.25#ibcon#about to write, iclass 5, count 2 2006.285.15:39:13.25#ibcon#wrote, iclass 5, count 2 2006.285.15:39:13.25#ibcon#about to read 3, iclass 5, count 2 2006.285.15:39:13.27#ibcon#read 3, iclass 5, count 2 2006.285.15:39:13.27#ibcon#about to read 4, iclass 5, count 2 2006.285.15:39:13.27#ibcon#read 4, iclass 5, count 2 2006.285.15:39:13.27#ibcon#about to read 5, iclass 5, count 2 2006.285.15:39:13.27#ibcon#read 5, iclass 5, count 2 2006.285.15:39:13.27#ibcon#about to read 6, iclass 5, count 2 2006.285.15:39:13.27#ibcon#read 6, iclass 5, count 2 2006.285.15:39:13.27#ibcon#end of sib2, iclass 5, count 2 2006.285.15:39:13.27#ibcon#*mode == 0, iclass 5, count 2 2006.285.15:39:13.27#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.15:39:13.27#ibcon#[27=AT05-04\r\n] 2006.285.15:39:13.27#ibcon#*before write, iclass 5, count 2 2006.285.15:39:13.27#ibcon#enter sib2, iclass 5, count 2 2006.285.15:39:13.27#ibcon#flushed, iclass 5, count 2 2006.285.15:39:13.27#ibcon#about to write, iclass 5, count 2 2006.285.15:39:13.27#ibcon#wrote, iclass 5, count 2 2006.285.15:39:13.27#ibcon#about to read 3, iclass 5, count 2 2006.285.15:39:13.30#ibcon#read 3, iclass 5, count 2 2006.285.15:39:13.30#ibcon#about to read 4, iclass 5, count 2 2006.285.15:39:13.30#ibcon#read 4, iclass 5, count 2 2006.285.15:39:13.30#ibcon#about to read 5, iclass 5, count 2 2006.285.15:39:13.30#ibcon#read 5, iclass 5, count 2 2006.285.15:39:13.30#ibcon#about to read 6, iclass 5, count 2 2006.285.15:39:13.30#ibcon#read 6, iclass 5, count 2 2006.285.15:39:13.30#ibcon#end of sib2, iclass 5, count 2 2006.285.15:39:13.30#ibcon#*after write, iclass 5, count 2 2006.285.15:39:13.30#ibcon#*before return 0, iclass 5, count 2 2006.285.15:39:13.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:39:13.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:39:13.30#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.15:39:13.30#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:13.30#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:39:13.42#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:39:13.42#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:39:13.42#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:39:13.42#ibcon#first serial, iclass 5, count 0 2006.285.15:39:13.42#ibcon#enter sib2, iclass 5, count 0 2006.285.15:39:13.42#ibcon#flushed, iclass 5, count 0 2006.285.15:39:13.42#ibcon#about to write, iclass 5, count 0 2006.285.15:39:13.42#ibcon#wrote, iclass 5, count 0 2006.285.15:39:13.42#ibcon#about to read 3, iclass 5, count 0 2006.285.15:39:13.44#ibcon#read 3, iclass 5, count 0 2006.285.15:39:13.44#ibcon#about to read 4, iclass 5, count 0 2006.285.15:39:13.44#ibcon#read 4, iclass 5, count 0 2006.285.15:39:13.44#ibcon#about to read 5, iclass 5, count 0 2006.285.15:39:13.44#ibcon#read 5, iclass 5, count 0 2006.285.15:39:13.44#ibcon#about to read 6, iclass 5, count 0 2006.285.15:39:13.44#ibcon#read 6, iclass 5, count 0 2006.285.15:39:13.44#ibcon#end of sib2, iclass 5, count 0 2006.285.15:39:13.44#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:39:13.44#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:39:13.44#ibcon#[27=USB\r\n] 2006.285.15:39:13.44#ibcon#*before write, iclass 5, count 0 2006.285.15:39:13.44#ibcon#enter sib2, iclass 5, count 0 2006.285.15:39:13.44#ibcon#flushed, iclass 5, count 0 2006.285.15:39:13.44#ibcon#about to write, iclass 5, count 0 2006.285.15:39:13.44#ibcon#wrote, iclass 5, count 0 2006.285.15:39:13.44#ibcon#about to read 3, iclass 5, count 0 2006.285.15:39:13.47#ibcon#read 3, iclass 5, count 0 2006.285.15:39:13.47#ibcon#about to read 4, iclass 5, count 0 2006.285.15:39:13.47#ibcon#read 4, iclass 5, count 0 2006.285.15:39:13.47#ibcon#about to read 5, iclass 5, count 0 2006.285.15:39:13.47#ibcon#read 5, iclass 5, count 0 2006.285.15:39:13.47#ibcon#about to read 6, iclass 5, count 0 2006.285.15:39:13.47#ibcon#read 6, iclass 5, count 0 2006.285.15:39:13.47#ibcon#end of sib2, iclass 5, count 0 2006.285.15:39:13.47#ibcon#*after write, iclass 5, count 0 2006.285.15:39:13.47#ibcon#*before return 0, iclass 5, count 0 2006.285.15:39:13.47#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:39:13.47#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:39:13.47#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:39:13.47#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:39:13.47$vck44/vblo=6,719.99 2006.285.15:39:13.47#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.15:39:13.47#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.15:39:13.47#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:13.47#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:39:13.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:39:13.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:39:13.47#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:39:13.47#ibcon#first serial, iclass 7, count 0 2006.285.15:39:13.47#ibcon#enter sib2, iclass 7, count 0 2006.285.15:39:13.47#ibcon#flushed, iclass 7, count 0 2006.285.15:39:13.47#ibcon#about to write, iclass 7, count 0 2006.285.15:39:13.47#ibcon#wrote, iclass 7, count 0 2006.285.15:39:13.47#ibcon#about to read 3, iclass 7, count 0 2006.285.15:39:13.49#ibcon#read 3, iclass 7, count 0 2006.285.15:39:13.49#ibcon#about to read 4, iclass 7, count 0 2006.285.15:39:13.49#ibcon#read 4, iclass 7, count 0 2006.285.15:39:13.49#ibcon#about to read 5, iclass 7, count 0 2006.285.15:39:13.49#ibcon#read 5, iclass 7, count 0 2006.285.15:39:13.49#ibcon#about to read 6, iclass 7, count 0 2006.285.15:39:13.49#ibcon#read 6, iclass 7, count 0 2006.285.15:39:13.49#ibcon#end of sib2, iclass 7, count 0 2006.285.15:39:13.49#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:39:13.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:39:13.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.15:39:13.49#ibcon#*before write, iclass 7, count 0 2006.285.15:39:13.49#ibcon#enter sib2, iclass 7, count 0 2006.285.15:39:13.49#ibcon#flushed, iclass 7, count 0 2006.285.15:39:13.49#ibcon#about to write, iclass 7, count 0 2006.285.15:39:13.49#ibcon#wrote, iclass 7, count 0 2006.285.15:39:13.49#ibcon#about to read 3, iclass 7, count 0 2006.285.15:39:13.53#ibcon#read 3, iclass 7, count 0 2006.285.15:39:13.53#ibcon#about to read 4, iclass 7, count 0 2006.285.15:39:13.53#ibcon#read 4, iclass 7, count 0 2006.285.15:39:13.53#ibcon#about to read 5, iclass 7, count 0 2006.285.15:39:13.53#ibcon#read 5, iclass 7, count 0 2006.285.15:39:13.53#ibcon#about to read 6, iclass 7, count 0 2006.285.15:39:13.53#ibcon#read 6, iclass 7, count 0 2006.285.15:39:13.53#ibcon#end of sib2, iclass 7, count 0 2006.285.15:39:13.53#ibcon#*after write, iclass 7, count 0 2006.285.15:39:13.53#ibcon#*before return 0, iclass 7, count 0 2006.285.15:39:13.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:39:13.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:39:13.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:39:13.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:39:13.53$vck44/vb=6,3 2006.285.15:39:13.53#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.15:39:13.53#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.15:39:13.53#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:13.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:39:13.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:39:13.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:39:13.59#ibcon#enter wrdev, iclass 11, count 2 2006.285.15:39:13.59#ibcon#first serial, iclass 11, count 2 2006.285.15:39:13.59#ibcon#enter sib2, iclass 11, count 2 2006.285.15:39:13.59#ibcon#flushed, iclass 11, count 2 2006.285.15:39:13.59#ibcon#about to write, iclass 11, count 2 2006.285.15:39:13.59#ibcon#wrote, iclass 11, count 2 2006.285.15:39:13.59#ibcon#about to read 3, iclass 11, count 2 2006.285.15:39:13.61#ibcon#read 3, iclass 11, count 2 2006.285.15:39:13.61#ibcon#about to read 4, iclass 11, count 2 2006.285.15:39:13.61#ibcon#read 4, iclass 11, count 2 2006.285.15:39:13.61#ibcon#about to read 5, iclass 11, count 2 2006.285.15:39:13.61#ibcon#read 5, iclass 11, count 2 2006.285.15:39:13.61#ibcon#about to read 6, iclass 11, count 2 2006.285.15:39:13.61#ibcon#read 6, iclass 11, count 2 2006.285.15:39:13.61#ibcon#end of sib2, iclass 11, count 2 2006.285.15:39:13.61#ibcon#*mode == 0, iclass 11, count 2 2006.285.15:39:13.61#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.15:39:13.61#ibcon#[27=AT06-03\r\n] 2006.285.15:39:13.61#ibcon#*before write, iclass 11, count 2 2006.285.15:39:13.61#ibcon#enter sib2, iclass 11, count 2 2006.285.15:39:13.61#ibcon#flushed, iclass 11, count 2 2006.285.15:39:13.61#ibcon#about to write, iclass 11, count 2 2006.285.15:39:13.61#ibcon#wrote, iclass 11, count 2 2006.285.15:39:13.61#ibcon#about to read 3, iclass 11, count 2 2006.285.15:39:13.64#ibcon#read 3, iclass 11, count 2 2006.285.15:39:13.64#ibcon#about to read 4, iclass 11, count 2 2006.285.15:39:13.64#ibcon#read 4, iclass 11, count 2 2006.285.15:39:13.64#ibcon#about to read 5, iclass 11, count 2 2006.285.15:39:13.64#ibcon#read 5, iclass 11, count 2 2006.285.15:39:13.64#ibcon#about to read 6, iclass 11, count 2 2006.285.15:39:13.64#ibcon#read 6, iclass 11, count 2 2006.285.15:39:13.64#ibcon#end of sib2, iclass 11, count 2 2006.285.15:39:13.64#ibcon#*after write, iclass 11, count 2 2006.285.15:39:13.64#ibcon#*before return 0, iclass 11, count 2 2006.285.15:39:13.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:39:13.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:39:13.64#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.15:39:13.64#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:13.64#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:39:13.76#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:39:13.76#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:39:13.76#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:39:13.76#ibcon#first serial, iclass 11, count 0 2006.285.15:39:13.76#ibcon#enter sib2, iclass 11, count 0 2006.285.15:39:13.76#ibcon#flushed, iclass 11, count 0 2006.285.15:39:13.76#ibcon#about to write, iclass 11, count 0 2006.285.15:39:13.76#ibcon#wrote, iclass 11, count 0 2006.285.15:39:13.76#ibcon#about to read 3, iclass 11, count 0 2006.285.15:39:13.78#ibcon#read 3, iclass 11, count 0 2006.285.15:39:13.78#ibcon#about to read 4, iclass 11, count 0 2006.285.15:39:13.78#ibcon#read 4, iclass 11, count 0 2006.285.15:39:13.78#ibcon#about to read 5, iclass 11, count 0 2006.285.15:39:13.78#ibcon#read 5, iclass 11, count 0 2006.285.15:39:13.78#ibcon#about to read 6, iclass 11, count 0 2006.285.15:39:13.78#ibcon#read 6, iclass 11, count 0 2006.285.15:39:13.78#ibcon#end of sib2, iclass 11, count 0 2006.285.15:39:13.78#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:39:13.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:39:13.78#ibcon#[27=USB\r\n] 2006.285.15:39:13.78#ibcon#*before write, iclass 11, count 0 2006.285.15:39:13.78#ibcon#enter sib2, iclass 11, count 0 2006.285.15:39:13.78#ibcon#flushed, iclass 11, count 0 2006.285.15:39:13.78#ibcon#about to write, iclass 11, count 0 2006.285.15:39:13.78#ibcon#wrote, iclass 11, count 0 2006.285.15:39:13.78#ibcon#about to read 3, iclass 11, count 0 2006.285.15:39:13.81#ibcon#read 3, iclass 11, count 0 2006.285.15:39:13.81#ibcon#about to read 4, iclass 11, count 0 2006.285.15:39:13.81#ibcon#read 4, iclass 11, count 0 2006.285.15:39:13.81#ibcon#about to read 5, iclass 11, count 0 2006.285.15:39:13.81#ibcon#read 5, iclass 11, count 0 2006.285.15:39:13.81#ibcon#about to read 6, iclass 11, count 0 2006.285.15:39:13.81#ibcon#read 6, iclass 11, count 0 2006.285.15:39:13.81#ibcon#end of sib2, iclass 11, count 0 2006.285.15:39:13.81#ibcon#*after write, iclass 11, count 0 2006.285.15:39:13.81#ibcon#*before return 0, iclass 11, count 0 2006.285.15:39:13.81#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:39:13.81#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:39:13.81#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:39:13.81#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:39:13.81$vck44/vblo=7,734.99 2006.285.15:39:13.81#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.15:39:13.81#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.15:39:13.81#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:13.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:39:13.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:39:13.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:39:13.81#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:39:13.81#ibcon#first serial, iclass 13, count 0 2006.285.15:39:13.81#ibcon#enter sib2, iclass 13, count 0 2006.285.15:39:13.81#ibcon#flushed, iclass 13, count 0 2006.285.15:39:13.81#ibcon#about to write, iclass 13, count 0 2006.285.15:39:13.81#ibcon#wrote, iclass 13, count 0 2006.285.15:39:13.81#ibcon#about to read 3, iclass 13, count 0 2006.285.15:39:13.83#ibcon#read 3, iclass 13, count 0 2006.285.15:39:13.83#ibcon#about to read 4, iclass 13, count 0 2006.285.15:39:13.83#ibcon#read 4, iclass 13, count 0 2006.285.15:39:13.83#ibcon#about to read 5, iclass 13, count 0 2006.285.15:39:13.83#ibcon#read 5, iclass 13, count 0 2006.285.15:39:13.83#ibcon#about to read 6, iclass 13, count 0 2006.285.15:39:13.83#ibcon#read 6, iclass 13, count 0 2006.285.15:39:13.83#ibcon#end of sib2, iclass 13, count 0 2006.285.15:39:13.83#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:39:13.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:39:13.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.15:39:13.83#ibcon#*before write, iclass 13, count 0 2006.285.15:39:13.83#ibcon#enter sib2, iclass 13, count 0 2006.285.15:39:13.83#ibcon#flushed, iclass 13, count 0 2006.285.15:39:13.83#ibcon#about to write, iclass 13, count 0 2006.285.15:39:13.83#ibcon#wrote, iclass 13, count 0 2006.285.15:39:13.83#ibcon#about to read 3, iclass 13, count 0 2006.285.15:39:13.87#ibcon#read 3, iclass 13, count 0 2006.285.15:39:13.87#ibcon#about to read 4, iclass 13, count 0 2006.285.15:39:13.87#ibcon#read 4, iclass 13, count 0 2006.285.15:39:13.87#ibcon#about to read 5, iclass 13, count 0 2006.285.15:39:13.87#ibcon#read 5, iclass 13, count 0 2006.285.15:39:13.87#ibcon#about to read 6, iclass 13, count 0 2006.285.15:39:13.87#ibcon#read 6, iclass 13, count 0 2006.285.15:39:13.87#ibcon#end of sib2, iclass 13, count 0 2006.285.15:39:13.87#ibcon#*after write, iclass 13, count 0 2006.285.15:39:13.87#ibcon#*before return 0, iclass 13, count 0 2006.285.15:39:13.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:39:13.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:39:13.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:39:13.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:39:13.87$vck44/vb=7,4 2006.285.15:39:13.87#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.15:39:13.87#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.15:39:13.87#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:13.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:39:13.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:39:13.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:39:13.93#ibcon#enter wrdev, iclass 15, count 2 2006.285.15:39:13.93#ibcon#first serial, iclass 15, count 2 2006.285.15:39:13.93#ibcon#enter sib2, iclass 15, count 2 2006.285.15:39:13.93#ibcon#flushed, iclass 15, count 2 2006.285.15:39:13.93#ibcon#about to write, iclass 15, count 2 2006.285.15:39:13.93#ibcon#wrote, iclass 15, count 2 2006.285.15:39:13.93#ibcon#about to read 3, iclass 15, count 2 2006.285.15:39:13.94#abcon#<5=/03 1.1 3.9 19.01 911015.0\r\n> 2006.285.15:39:13.95#ibcon#read 3, iclass 15, count 2 2006.285.15:39:14.00#ibcon#about to read 4, iclass 15, count 2 2006.285.15:39:14.00#ibcon#read 4, iclass 15, count 2 2006.285.15:39:14.00#ibcon#about to read 5, iclass 15, count 2 2006.285.15:39:14.00#ibcon#read 5, iclass 15, count 2 2006.285.15:39:14.00#ibcon#about to read 6, iclass 15, count 2 2006.285.15:39:14.00#ibcon#read 6, iclass 15, count 2 2006.285.15:39:14.00#ibcon#end of sib2, iclass 15, count 2 2006.285.15:39:14.00#ibcon#*mode == 0, iclass 15, count 2 2006.285.15:39:14.00#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.15:39:14.00#ibcon#[27=AT07-04\r\n] 2006.285.15:39:14.00#ibcon#*before write, iclass 15, count 2 2006.285.15:39:14.00#ibcon#enter sib2, iclass 15, count 2 2006.285.15:39:14.00#ibcon#flushed, iclass 15, count 2 2006.285.15:39:14.00#ibcon#about to write, iclass 15, count 2 2006.285.15:39:14.00#ibcon#wrote, iclass 15, count 2 2006.285.15:39:14.00#ibcon#about to read 3, iclass 15, count 2 2006.285.15:39:14.01#abcon#{5=INTERFACE CLEAR} 2006.285.15:39:14.03#ibcon#read 3, iclass 15, count 2 2006.285.15:39:14.03#ibcon#about to read 4, iclass 15, count 2 2006.285.15:39:14.03#ibcon#read 4, iclass 15, count 2 2006.285.15:39:14.03#ibcon#about to read 5, iclass 15, count 2 2006.285.15:39:14.03#ibcon#read 5, iclass 15, count 2 2006.285.15:39:14.03#ibcon#about to read 6, iclass 15, count 2 2006.285.15:39:14.03#ibcon#read 6, iclass 15, count 2 2006.285.15:39:14.03#ibcon#end of sib2, iclass 15, count 2 2006.285.15:39:14.03#ibcon#*after write, iclass 15, count 2 2006.285.15:39:14.03#ibcon#*before return 0, iclass 15, count 2 2006.285.15:39:14.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:39:14.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:39:14.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.15:39:14.03#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:14.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:39:14.07#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:39:14.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:39:14.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:39:14.15#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:39:14.15#ibcon#first serial, iclass 15, count 0 2006.285.15:39:14.15#ibcon#enter sib2, iclass 15, count 0 2006.285.15:39:14.15#ibcon#flushed, iclass 15, count 0 2006.285.15:39:14.15#ibcon#about to write, iclass 15, count 0 2006.285.15:39:14.15#ibcon#wrote, iclass 15, count 0 2006.285.15:39:14.15#ibcon#about to read 3, iclass 15, count 0 2006.285.15:39:14.17#ibcon#read 3, iclass 15, count 0 2006.285.15:39:14.17#ibcon#about to read 4, iclass 15, count 0 2006.285.15:39:14.17#ibcon#read 4, iclass 15, count 0 2006.285.15:39:14.17#ibcon#about to read 5, iclass 15, count 0 2006.285.15:39:14.17#ibcon#read 5, iclass 15, count 0 2006.285.15:39:14.17#ibcon#about to read 6, iclass 15, count 0 2006.285.15:39:14.17#ibcon#read 6, iclass 15, count 0 2006.285.15:39:14.17#ibcon#end of sib2, iclass 15, count 0 2006.285.15:39:14.17#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:39:14.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:39:14.17#ibcon#[27=USB\r\n] 2006.285.15:39:14.17#ibcon#*before write, iclass 15, count 0 2006.285.15:39:14.17#ibcon#enter sib2, iclass 15, count 0 2006.285.15:39:14.17#ibcon#flushed, iclass 15, count 0 2006.285.15:39:14.17#ibcon#about to write, iclass 15, count 0 2006.285.15:39:14.17#ibcon#wrote, iclass 15, count 0 2006.285.15:39:14.17#ibcon#about to read 3, iclass 15, count 0 2006.285.15:39:14.20#ibcon#read 3, iclass 15, count 0 2006.285.15:39:14.20#ibcon#about to read 4, iclass 15, count 0 2006.285.15:39:14.20#ibcon#read 4, iclass 15, count 0 2006.285.15:39:14.20#ibcon#about to read 5, iclass 15, count 0 2006.285.15:39:14.20#ibcon#read 5, iclass 15, count 0 2006.285.15:39:14.20#ibcon#about to read 6, iclass 15, count 0 2006.285.15:39:14.20#ibcon#read 6, iclass 15, count 0 2006.285.15:39:14.20#ibcon#end of sib2, iclass 15, count 0 2006.285.15:39:14.20#ibcon#*after write, iclass 15, count 0 2006.285.15:39:14.20#ibcon#*before return 0, iclass 15, count 0 2006.285.15:39:14.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:39:14.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:39:14.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:39:14.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:39:14.20$vck44/vblo=8,744.99 2006.285.15:39:14.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.15:39:14.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.15:39:14.20#ibcon#ireg 17 cls_cnt 0 2006.285.15:39:14.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:39:14.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:39:14.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:39:14.20#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:39:14.20#ibcon#first serial, iclass 21, count 0 2006.285.15:39:14.20#ibcon#enter sib2, iclass 21, count 0 2006.285.15:39:14.20#ibcon#flushed, iclass 21, count 0 2006.285.15:39:14.20#ibcon#about to write, iclass 21, count 0 2006.285.15:39:14.20#ibcon#wrote, iclass 21, count 0 2006.285.15:39:14.20#ibcon#about to read 3, iclass 21, count 0 2006.285.15:39:14.22#ibcon#read 3, iclass 21, count 0 2006.285.15:39:14.22#ibcon#about to read 4, iclass 21, count 0 2006.285.15:39:14.22#ibcon#read 4, iclass 21, count 0 2006.285.15:39:14.22#ibcon#about to read 5, iclass 21, count 0 2006.285.15:39:14.22#ibcon#read 5, iclass 21, count 0 2006.285.15:39:14.22#ibcon#about to read 6, iclass 21, count 0 2006.285.15:39:14.22#ibcon#read 6, iclass 21, count 0 2006.285.15:39:14.22#ibcon#end of sib2, iclass 21, count 0 2006.285.15:39:14.22#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:39:14.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:39:14.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.15:39:14.22#ibcon#*before write, iclass 21, count 0 2006.285.15:39:14.22#ibcon#enter sib2, iclass 21, count 0 2006.285.15:39:14.22#ibcon#flushed, iclass 21, count 0 2006.285.15:39:14.22#ibcon#about to write, iclass 21, count 0 2006.285.15:39:14.22#ibcon#wrote, iclass 21, count 0 2006.285.15:39:14.22#ibcon#about to read 3, iclass 21, count 0 2006.285.15:39:14.26#ibcon#read 3, iclass 21, count 0 2006.285.15:39:14.26#ibcon#about to read 4, iclass 21, count 0 2006.285.15:39:14.26#ibcon#read 4, iclass 21, count 0 2006.285.15:39:14.26#ibcon#about to read 5, iclass 21, count 0 2006.285.15:39:14.26#ibcon#read 5, iclass 21, count 0 2006.285.15:39:14.26#ibcon#about to read 6, iclass 21, count 0 2006.285.15:39:14.26#ibcon#read 6, iclass 21, count 0 2006.285.15:39:14.26#ibcon#end of sib2, iclass 21, count 0 2006.285.15:39:14.26#ibcon#*after write, iclass 21, count 0 2006.285.15:39:14.26#ibcon#*before return 0, iclass 21, count 0 2006.285.15:39:14.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:39:14.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:39:14.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:39:14.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:39:14.26$vck44/vb=8,4 2006.285.15:39:14.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.15:39:14.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.15:39:14.26#ibcon#ireg 11 cls_cnt 2 2006.285.15:39:14.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:39:14.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:39:14.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:39:14.32#ibcon#enter wrdev, iclass 23, count 2 2006.285.15:39:14.32#ibcon#first serial, iclass 23, count 2 2006.285.15:39:14.32#ibcon#enter sib2, iclass 23, count 2 2006.285.15:39:14.32#ibcon#flushed, iclass 23, count 2 2006.285.15:39:14.32#ibcon#about to write, iclass 23, count 2 2006.285.15:39:14.32#ibcon#wrote, iclass 23, count 2 2006.285.15:39:14.32#ibcon#about to read 3, iclass 23, count 2 2006.285.15:39:14.34#ibcon#read 3, iclass 23, count 2 2006.285.15:39:14.34#ibcon#about to read 4, iclass 23, count 2 2006.285.15:39:14.34#ibcon#read 4, iclass 23, count 2 2006.285.15:39:14.34#ibcon#about to read 5, iclass 23, count 2 2006.285.15:39:14.34#ibcon#read 5, iclass 23, count 2 2006.285.15:39:14.34#ibcon#about to read 6, iclass 23, count 2 2006.285.15:39:14.34#ibcon#read 6, iclass 23, count 2 2006.285.15:39:14.34#ibcon#end of sib2, iclass 23, count 2 2006.285.15:39:14.34#ibcon#*mode == 0, iclass 23, count 2 2006.285.15:39:14.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.15:39:14.34#ibcon#[27=AT08-04\r\n] 2006.285.15:39:14.34#ibcon#*before write, iclass 23, count 2 2006.285.15:39:14.34#ibcon#enter sib2, iclass 23, count 2 2006.285.15:39:14.34#ibcon#flushed, iclass 23, count 2 2006.285.15:39:14.34#ibcon#about to write, iclass 23, count 2 2006.285.15:39:14.34#ibcon#wrote, iclass 23, count 2 2006.285.15:39:14.34#ibcon#about to read 3, iclass 23, count 2 2006.285.15:39:14.37#ibcon#read 3, iclass 23, count 2 2006.285.15:39:14.37#ibcon#about to read 4, iclass 23, count 2 2006.285.15:39:14.37#ibcon#read 4, iclass 23, count 2 2006.285.15:39:14.37#ibcon#about to read 5, iclass 23, count 2 2006.285.15:39:14.37#ibcon#read 5, iclass 23, count 2 2006.285.15:39:14.37#ibcon#about to read 6, iclass 23, count 2 2006.285.15:39:14.37#ibcon#read 6, iclass 23, count 2 2006.285.15:39:14.37#ibcon#end of sib2, iclass 23, count 2 2006.285.15:39:14.37#ibcon#*after write, iclass 23, count 2 2006.285.15:39:14.37#ibcon#*before return 0, iclass 23, count 2 2006.285.15:39:14.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:39:14.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:39:14.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.15:39:14.37#ibcon#ireg 7 cls_cnt 0 2006.285.15:39:14.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:39:14.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:39:14.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:39:14.49#ibcon#enter wrdev, iclass 23, count 0 2006.285.15:39:14.49#ibcon#first serial, iclass 23, count 0 2006.285.15:39:14.49#ibcon#enter sib2, iclass 23, count 0 2006.285.15:39:14.49#ibcon#flushed, iclass 23, count 0 2006.285.15:39:14.49#ibcon#about to write, iclass 23, count 0 2006.285.15:39:14.49#ibcon#wrote, iclass 23, count 0 2006.285.15:39:14.49#ibcon#about to read 3, iclass 23, count 0 2006.285.15:39:14.51#ibcon#read 3, iclass 23, count 0 2006.285.15:39:14.51#ibcon#about to read 4, iclass 23, count 0 2006.285.15:39:14.51#ibcon#read 4, iclass 23, count 0 2006.285.15:39:14.51#ibcon#about to read 5, iclass 23, count 0 2006.285.15:39:14.51#ibcon#read 5, iclass 23, count 0 2006.285.15:39:14.51#ibcon#about to read 6, iclass 23, count 0 2006.285.15:39:14.51#ibcon#read 6, iclass 23, count 0 2006.285.15:39:14.51#ibcon#end of sib2, iclass 23, count 0 2006.285.15:39:14.51#ibcon#*mode == 0, iclass 23, count 0 2006.285.15:39:14.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.15:39:14.51#ibcon#[27=USB\r\n] 2006.285.15:39:14.51#ibcon#*before write, iclass 23, count 0 2006.285.15:39:14.51#ibcon#enter sib2, iclass 23, count 0 2006.285.15:39:14.51#ibcon#flushed, iclass 23, count 0 2006.285.15:39:14.51#ibcon#about to write, iclass 23, count 0 2006.285.15:39:14.51#ibcon#wrote, iclass 23, count 0 2006.285.15:39:14.51#ibcon#about to read 3, iclass 23, count 0 2006.285.15:39:14.54#ibcon#read 3, iclass 23, count 0 2006.285.15:39:14.54#ibcon#about to read 4, iclass 23, count 0 2006.285.15:39:14.54#ibcon#read 4, iclass 23, count 0 2006.285.15:39:14.54#ibcon#about to read 5, iclass 23, count 0 2006.285.15:39:14.54#ibcon#read 5, iclass 23, count 0 2006.285.15:39:14.54#ibcon#about to read 6, iclass 23, count 0 2006.285.15:39:14.54#ibcon#read 6, iclass 23, count 0 2006.285.15:39:14.54#ibcon#end of sib2, iclass 23, count 0 2006.285.15:39:14.54#ibcon#*after write, iclass 23, count 0 2006.285.15:39:14.54#ibcon#*before return 0, iclass 23, count 0 2006.285.15:39:14.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:39:14.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:39:14.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.15:39:14.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.15:39:14.54$vck44/vabw=wide 2006.285.15:39:14.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.15:39:14.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.15:39:14.54#ibcon#ireg 8 cls_cnt 0 2006.285.15:39:14.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:39:14.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:39:14.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:39:14.54#ibcon#enter wrdev, iclass 25, count 0 2006.285.15:39:14.54#ibcon#first serial, iclass 25, count 0 2006.285.15:39:14.54#ibcon#enter sib2, iclass 25, count 0 2006.285.15:39:14.54#ibcon#flushed, iclass 25, count 0 2006.285.15:39:14.54#ibcon#about to write, iclass 25, count 0 2006.285.15:39:14.54#ibcon#wrote, iclass 25, count 0 2006.285.15:39:14.54#ibcon#about to read 3, iclass 25, count 0 2006.285.15:39:14.56#ibcon#read 3, iclass 25, count 0 2006.285.15:39:14.56#ibcon#about to read 4, iclass 25, count 0 2006.285.15:39:14.56#ibcon#read 4, iclass 25, count 0 2006.285.15:39:14.56#ibcon#about to read 5, iclass 25, count 0 2006.285.15:39:14.56#ibcon#read 5, iclass 25, count 0 2006.285.15:39:14.56#ibcon#about to read 6, iclass 25, count 0 2006.285.15:39:14.56#ibcon#read 6, iclass 25, count 0 2006.285.15:39:14.56#ibcon#end of sib2, iclass 25, count 0 2006.285.15:39:14.56#ibcon#*mode == 0, iclass 25, count 0 2006.285.15:39:14.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.15:39:14.56#ibcon#[25=BW32\r\n] 2006.285.15:39:14.56#ibcon#*before write, iclass 25, count 0 2006.285.15:39:14.56#ibcon#enter sib2, iclass 25, count 0 2006.285.15:39:14.56#ibcon#flushed, iclass 25, count 0 2006.285.15:39:14.56#ibcon#about to write, iclass 25, count 0 2006.285.15:39:14.56#ibcon#wrote, iclass 25, count 0 2006.285.15:39:14.56#ibcon#about to read 3, iclass 25, count 0 2006.285.15:39:14.59#ibcon#read 3, iclass 25, count 0 2006.285.15:39:14.59#ibcon#about to read 4, iclass 25, count 0 2006.285.15:39:14.59#ibcon#read 4, iclass 25, count 0 2006.285.15:39:14.59#ibcon#about to read 5, iclass 25, count 0 2006.285.15:39:14.59#ibcon#read 5, iclass 25, count 0 2006.285.15:39:14.59#ibcon#about to read 6, iclass 25, count 0 2006.285.15:39:14.59#ibcon#read 6, iclass 25, count 0 2006.285.15:39:14.59#ibcon#end of sib2, iclass 25, count 0 2006.285.15:39:14.59#ibcon#*after write, iclass 25, count 0 2006.285.15:39:14.59#ibcon#*before return 0, iclass 25, count 0 2006.285.15:39:14.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:39:14.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:39:14.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.15:39:14.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.15:39:14.59$vck44/vbbw=wide 2006.285.15:39:14.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.15:39:14.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.15:39:14.59#ibcon#ireg 8 cls_cnt 0 2006.285.15:39:14.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:39:14.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:39:14.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:39:14.66#ibcon#enter wrdev, iclass 27, count 0 2006.285.15:39:14.66#ibcon#first serial, iclass 27, count 0 2006.285.15:39:14.66#ibcon#enter sib2, iclass 27, count 0 2006.285.15:39:14.66#ibcon#flushed, iclass 27, count 0 2006.285.15:39:14.66#ibcon#about to write, iclass 27, count 0 2006.285.15:39:14.66#ibcon#wrote, iclass 27, count 0 2006.285.15:39:14.66#ibcon#about to read 3, iclass 27, count 0 2006.285.15:39:14.68#ibcon#read 3, iclass 27, count 0 2006.285.15:39:14.68#ibcon#about to read 4, iclass 27, count 0 2006.285.15:39:14.68#ibcon#read 4, iclass 27, count 0 2006.285.15:39:14.68#ibcon#about to read 5, iclass 27, count 0 2006.285.15:39:14.68#ibcon#read 5, iclass 27, count 0 2006.285.15:39:14.68#ibcon#about to read 6, iclass 27, count 0 2006.285.15:39:14.68#ibcon#read 6, iclass 27, count 0 2006.285.15:39:14.68#ibcon#end of sib2, iclass 27, count 0 2006.285.15:39:14.68#ibcon#*mode == 0, iclass 27, count 0 2006.285.15:39:14.68#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.15:39:14.68#ibcon#[27=BW32\r\n] 2006.285.15:39:14.68#ibcon#*before write, iclass 27, count 0 2006.285.15:39:14.68#ibcon#enter sib2, iclass 27, count 0 2006.285.15:39:14.68#ibcon#flushed, iclass 27, count 0 2006.285.15:39:14.68#ibcon#about to write, iclass 27, count 0 2006.285.15:39:14.68#ibcon#wrote, iclass 27, count 0 2006.285.15:39:14.68#ibcon#about to read 3, iclass 27, count 0 2006.285.15:39:14.71#ibcon#read 3, iclass 27, count 0 2006.285.15:39:14.71#ibcon#about to read 4, iclass 27, count 0 2006.285.15:39:14.71#ibcon#read 4, iclass 27, count 0 2006.285.15:39:14.71#ibcon#about to read 5, iclass 27, count 0 2006.285.15:39:14.71#ibcon#read 5, iclass 27, count 0 2006.285.15:39:14.71#ibcon#about to read 6, iclass 27, count 0 2006.285.15:39:14.71#ibcon#read 6, iclass 27, count 0 2006.285.15:39:14.71#ibcon#end of sib2, iclass 27, count 0 2006.285.15:39:14.71#ibcon#*after write, iclass 27, count 0 2006.285.15:39:14.71#ibcon#*before return 0, iclass 27, count 0 2006.285.15:39:14.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:39:14.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:39:14.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.15:39:14.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.15:39:14.71$setupk4/ifdk4 2006.285.15:39:14.71$ifdk4/lo= 2006.285.15:39:14.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.15:39:14.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.15:39:14.71$ifdk4/patch= 2006.285.15:39:14.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.15:39:14.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.15:39:14.71$setupk4/!*+20s 2006.285.15:39:16.14#trakl#Source acquired 2006.285.15:39:17.14#flagr#flagr/antenna,acquired 2006.285.15:39:24.16#abcon#<5=/03 1.1 3.9 19.01 911015.0\r\n> 2006.285.15:39:24.18#abcon#{5=INTERFACE CLEAR} 2006.285.15:39:24.24#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:39:28.37$setupk4/"tpicd 2006.285.15:39:28.37$setupk4/echo=off 2006.285.15:39:28.37$setupk4/xlog=off 2006.285.15:39:28.37:!2006.285.15:43:23 2006.285.15:43:23.00:preob 2006.285.15:43:24.14/onsource/TRACKING 2006.285.15:43:24.14:!2006.285.15:43:33 2006.285.15:43:33.00:"tape 2006.285.15:43:33.00:"st=record 2006.285.15:43:33.00:data_valid=on 2006.285.15:43:33.00:midob 2006.285.15:43:33.14/onsource/TRACKING 2006.285.15:43:33.14/wx/18.97,1015.0,91 2006.285.15:43:33.31/cable/+6.5022E-03 2006.285.15:43:34.40/va/01,07,usb,yes,35,38 2006.285.15:43:34.40/va/02,06,usb,yes,35,36 2006.285.15:43:34.40/va/03,07,usb,yes,35,37 2006.285.15:43:34.40/va/04,06,usb,yes,36,38 2006.285.15:43:34.40/va/05,03,usb,yes,36,36 2006.285.15:43:34.40/va/06,04,usb,yes,32,32 2006.285.15:43:34.40/va/07,04,usb,yes,33,34 2006.285.15:43:34.40/va/08,03,usb,yes,34,41 2006.285.15:43:34.63/valo/01,524.99,yes,locked 2006.285.15:43:34.63/valo/02,534.99,yes,locked 2006.285.15:43:34.63/valo/03,564.99,yes,locked 2006.285.15:43:34.63/valo/04,624.99,yes,locked 2006.285.15:43:34.63/valo/05,734.99,yes,locked 2006.285.15:43:34.63/valo/06,814.99,yes,locked 2006.285.15:43:34.63/valo/07,864.99,yes,locked 2006.285.15:43:34.63/valo/08,884.99,yes,locked 2006.285.15:43:35.72/vb/01,04,usb,yes,30,28 2006.285.15:43:35.72/vb/02,05,usb,yes,28,28 2006.285.15:43:35.72/vb/03,04,usb,yes,29,32 2006.285.15:43:35.72/vb/04,05,usb,yes,29,28 2006.285.15:43:35.72/vb/05,04,usb,yes,26,28 2006.285.15:43:35.72/vb/06,03,usb,yes,37,33 2006.285.15:43:35.72/vb/07,04,usb,yes,30,30 2006.285.15:43:35.72/vb/08,04,usb,yes,27,31 2006.285.15:43:35.95/vblo/01,629.99,yes,locked 2006.285.15:43:35.95/vblo/02,634.99,yes,locked 2006.285.15:43:35.95/vblo/03,649.99,yes,locked 2006.285.15:43:35.95/vblo/04,679.99,yes,locked 2006.285.15:43:35.95/vblo/05,709.99,yes,locked 2006.285.15:43:35.95/vblo/06,719.99,yes,locked 2006.285.15:43:35.95/vblo/07,734.99,yes,locked 2006.285.15:43:35.95/vblo/08,744.99,yes,locked 2006.285.15:43:36.10/vabw/8 2006.285.15:43:36.25/vbbw/8 2006.285.15:43:36.34/xfe/off,on,12.2 2006.285.15:43:36.71/ifatt/23,28,28,28 2006.285.15:43:37.07/fmout-gps/S +2.54E-07 2006.285.15:43:37.09:!2006.285.15:45:13 2006.285.15:45:13.01:data_valid=off 2006.285.15:45:13.01:"et 2006.285.15:45:13.01:!+3s 2006.285.15:45:16.02:"tape 2006.285.15:45:16.02:postob 2006.285.15:45:16.10/cable/+6.5011E-03 2006.285.15:45:16.10/wx/18.94,1015.0,92 2006.285.15:45:17.08/fmout-gps/S +2.55E-07 2006.285.15:45:17.08:scan_name=285-1547,jd0610,110 2006.285.15:45:17.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.285.15:45:18.13#flagr#flagr/antenna,new-source 2006.285.15:45:18.13:checkk5 2006.285.15:45:18.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.15:45:19.16/chk_autoobs//k5ts2/ autoobs is running! 2006.285.15:45:19.63/chk_autoobs//k5ts3/ autoobs is running! 2006.285.15:45:20.02/chk_autoobs//k5ts4/ autoobs is running! 2006.285.15:45:20.93/chk_obsdata//k5ts1/T2851543??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.15:45:21.34/chk_obsdata//k5ts2/T2851543??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.15:45:21.84/chk_obsdata//k5ts3/T2851543??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.15:45:22.23/chk_obsdata//k5ts4/T2851543??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.15:45:23.30/k5log//k5ts1_log_newline 2006.285.15:45:24.45/k5log//k5ts2_log_newline 2006.285.15:45:25.23/k5log//k5ts3_log_newline 2006.285.15:45:26.54/k5log//k5ts4_log_newline 2006.285.15:45:26.56/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.15:45:26.56:setupk4=1 2006.285.15:45:26.56$setupk4/echo=on 2006.285.15:45:26.56$setupk4/pcalon 2006.285.15:45:26.56$pcalon/"no phase cal control is implemented here 2006.285.15:45:26.56$setupk4/"tpicd=stop 2006.285.15:45:26.56$setupk4/"rec=synch_on 2006.285.15:45:26.56$setupk4/"rec_mode=128 2006.285.15:45:26.56$setupk4/!* 2006.285.15:45:26.56$setupk4/recpk4 2006.285.15:45:26.56$recpk4/recpatch= 2006.285.15:45:26.57$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.15:45:26.57$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.15:45:26.57$setupk4/vck44 2006.285.15:45:26.57$vck44/valo=1,524.99 2006.285.15:45:26.57#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.15:45:26.57#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.15:45:26.57#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:26.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:45:26.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:45:26.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:45:26.57#ibcon#enter wrdev, iclass 27, count 0 2006.285.15:45:26.57#ibcon#first serial, iclass 27, count 0 2006.285.15:45:26.57#ibcon#enter sib2, iclass 27, count 0 2006.285.15:45:26.57#ibcon#flushed, iclass 27, count 0 2006.285.15:45:26.57#ibcon#about to write, iclass 27, count 0 2006.285.15:45:26.57#ibcon#wrote, iclass 27, count 0 2006.285.15:45:26.57#ibcon#about to read 3, iclass 27, count 0 2006.285.15:45:26.59#ibcon#read 3, iclass 27, count 0 2006.285.15:45:26.59#ibcon#about to read 4, iclass 27, count 0 2006.285.15:45:26.59#ibcon#read 4, iclass 27, count 0 2006.285.15:45:26.59#ibcon#about to read 5, iclass 27, count 0 2006.285.15:45:26.59#ibcon#read 5, iclass 27, count 0 2006.285.15:45:26.59#ibcon#about to read 6, iclass 27, count 0 2006.285.15:45:26.59#ibcon#read 6, iclass 27, count 0 2006.285.15:45:26.59#ibcon#end of sib2, iclass 27, count 0 2006.285.15:45:26.59#ibcon#*mode == 0, iclass 27, count 0 2006.285.15:45:26.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.15:45:26.59#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.15:45:26.59#ibcon#*before write, iclass 27, count 0 2006.285.15:45:26.59#ibcon#enter sib2, iclass 27, count 0 2006.285.15:45:26.59#ibcon#flushed, iclass 27, count 0 2006.285.15:45:26.59#ibcon#about to write, iclass 27, count 0 2006.285.15:45:26.59#ibcon#wrote, iclass 27, count 0 2006.285.15:45:26.59#ibcon#about to read 3, iclass 27, count 0 2006.285.15:45:26.64#ibcon#read 3, iclass 27, count 0 2006.285.15:45:26.64#ibcon#about to read 4, iclass 27, count 0 2006.285.15:45:26.64#ibcon#read 4, iclass 27, count 0 2006.285.15:45:26.64#ibcon#about to read 5, iclass 27, count 0 2006.285.15:45:26.64#ibcon#read 5, iclass 27, count 0 2006.285.15:45:26.64#ibcon#about to read 6, iclass 27, count 0 2006.285.15:45:26.64#ibcon#read 6, iclass 27, count 0 2006.285.15:45:26.64#ibcon#end of sib2, iclass 27, count 0 2006.285.15:45:26.64#ibcon#*after write, iclass 27, count 0 2006.285.15:45:26.64#ibcon#*before return 0, iclass 27, count 0 2006.285.15:45:26.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:45:26.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:45:26.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.15:45:26.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.15:45:26.64$vck44/va=1,7 2006.285.15:45:26.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.15:45:26.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.15:45:26.64#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:26.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:45:26.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:45:26.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:45:26.64#ibcon#enter wrdev, iclass 29, count 2 2006.285.15:45:26.64#ibcon#first serial, iclass 29, count 2 2006.285.15:45:26.64#ibcon#enter sib2, iclass 29, count 2 2006.285.15:45:26.64#ibcon#flushed, iclass 29, count 2 2006.285.15:45:26.64#ibcon#about to write, iclass 29, count 2 2006.285.15:45:26.64#ibcon#wrote, iclass 29, count 2 2006.285.15:45:26.64#ibcon#about to read 3, iclass 29, count 2 2006.285.15:45:26.66#ibcon#read 3, iclass 29, count 2 2006.285.15:45:26.66#ibcon#about to read 4, iclass 29, count 2 2006.285.15:45:26.66#ibcon#read 4, iclass 29, count 2 2006.285.15:45:26.66#ibcon#about to read 5, iclass 29, count 2 2006.285.15:45:26.66#ibcon#read 5, iclass 29, count 2 2006.285.15:45:26.66#ibcon#about to read 6, iclass 29, count 2 2006.285.15:45:26.66#ibcon#read 6, iclass 29, count 2 2006.285.15:45:26.66#ibcon#end of sib2, iclass 29, count 2 2006.285.15:45:26.66#ibcon#*mode == 0, iclass 29, count 2 2006.285.15:45:26.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.15:45:26.66#ibcon#[25=AT01-07\r\n] 2006.285.15:45:26.66#ibcon#*before write, iclass 29, count 2 2006.285.15:45:26.66#ibcon#enter sib2, iclass 29, count 2 2006.285.15:45:26.66#ibcon#flushed, iclass 29, count 2 2006.285.15:45:26.66#ibcon#about to write, iclass 29, count 2 2006.285.15:45:26.66#ibcon#wrote, iclass 29, count 2 2006.285.15:45:26.66#ibcon#about to read 3, iclass 29, count 2 2006.285.15:45:26.69#ibcon#read 3, iclass 29, count 2 2006.285.15:45:26.69#ibcon#about to read 4, iclass 29, count 2 2006.285.15:45:26.69#ibcon#read 4, iclass 29, count 2 2006.285.15:45:26.69#ibcon#about to read 5, iclass 29, count 2 2006.285.15:45:26.69#ibcon#read 5, iclass 29, count 2 2006.285.15:45:26.69#ibcon#about to read 6, iclass 29, count 2 2006.285.15:45:26.69#ibcon#read 6, iclass 29, count 2 2006.285.15:45:26.69#ibcon#end of sib2, iclass 29, count 2 2006.285.15:45:26.69#ibcon#*after write, iclass 29, count 2 2006.285.15:45:26.69#ibcon#*before return 0, iclass 29, count 2 2006.285.15:45:26.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:45:26.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:45:26.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.15:45:26.69#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:26.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:45:26.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:45:26.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:45:26.81#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:45:26.81#ibcon#first serial, iclass 29, count 0 2006.285.15:45:26.81#ibcon#enter sib2, iclass 29, count 0 2006.285.15:45:26.81#ibcon#flushed, iclass 29, count 0 2006.285.15:45:26.81#ibcon#about to write, iclass 29, count 0 2006.285.15:45:26.81#ibcon#wrote, iclass 29, count 0 2006.285.15:45:26.81#ibcon#about to read 3, iclass 29, count 0 2006.285.15:45:26.83#ibcon#read 3, iclass 29, count 0 2006.285.15:45:26.83#ibcon#about to read 4, iclass 29, count 0 2006.285.15:45:26.83#ibcon#read 4, iclass 29, count 0 2006.285.15:45:26.83#ibcon#about to read 5, iclass 29, count 0 2006.285.15:45:26.83#ibcon#read 5, iclass 29, count 0 2006.285.15:45:26.83#ibcon#about to read 6, iclass 29, count 0 2006.285.15:45:26.83#ibcon#read 6, iclass 29, count 0 2006.285.15:45:26.83#ibcon#end of sib2, iclass 29, count 0 2006.285.15:45:26.83#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:45:26.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:45:26.83#ibcon#[25=USB\r\n] 2006.285.15:45:26.83#ibcon#*before write, iclass 29, count 0 2006.285.15:45:26.83#ibcon#enter sib2, iclass 29, count 0 2006.285.15:45:26.83#ibcon#flushed, iclass 29, count 0 2006.285.15:45:26.83#ibcon#about to write, iclass 29, count 0 2006.285.15:45:26.83#ibcon#wrote, iclass 29, count 0 2006.285.15:45:26.83#ibcon#about to read 3, iclass 29, count 0 2006.285.15:45:26.86#ibcon#read 3, iclass 29, count 0 2006.285.15:45:26.86#ibcon#about to read 4, iclass 29, count 0 2006.285.15:45:26.86#ibcon#read 4, iclass 29, count 0 2006.285.15:45:26.86#ibcon#about to read 5, iclass 29, count 0 2006.285.15:45:26.86#ibcon#read 5, iclass 29, count 0 2006.285.15:45:26.86#ibcon#about to read 6, iclass 29, count 0 2006.285.15:45:26.86#ibcon#read 6, iclass 29, count 0 2006.285.15:45:26.86#ibcon#end of sib2, iclass 29, count 0 2006.285.15:45:26.86#ibcon#*after write, iclass 29, count 0 2006.285.15:45:26.86#ibcon#*before return 0, iclass 29, count 0 2006.285.15:45:26.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:45:26.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:45:26.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:45:26.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:45:26.86$vck44/valo=2,534.99 2006.285.15:45:26.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.15:45:26.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.15:45:26.86#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:26.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:45:26.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:45:26.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:45:26.86#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:45:26.86#ibcon#first serial, iclass 31, count 0 2006.285.15:45:26.86#ibcon#enter sib2, iclass 31, count 0 2006.285.15:45:26.86#ibcon#flushed, iclass 31, count 0 2006.285.15:45:26.86#ibcon#about to write, iclass 31, count 0 2006.285.15:45:26.86#ibcon#wrote, iclass 31, count 0 2006.285.15:45:26.86#ibcon#about to read 3, iclass 31, count 0 2006.285.15:45:26.88#ibcon#read 3, iclass 31, count 0 2006.285.15:45:26.88#ibcon#about to read 4, iclass 31, count 0 2006.285.15:45:26.88#ibcon#read 4, iclass 31, count 0 2006.285.15:45:26.88#ibcon#about to read 5, iclass 31, count 0 2006.285.15:45:26.88#ibcon#read 5, iclass 31, count 0 2006.285.15:45:26.88#ibcon#about to read 6, iclass 31, count 0 2006.285.15:45:26.88#ibcon#read 6, iclass 31, count 0 2006.285.15:45:26.88#ibcon#end of sib2, iclass 31, count 0 2006.285.15:45:26.88#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:45:26.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:45:26.88#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.15:45:26.88#ibcon#*before write, iclass 31, count 0 2006.285.15:45:26.88#ibcon#enter sib2, iclass 31, count 0 2006.285.15:45:26.88#ibcon#flushed, iclass 31, count 0 2006.285.15:45:26.88#ibcon#about to write, iclass 31, count 0 2006.285.15:45:26.88#ibcon#wrote, iclass 31, count 0 2006.285.15:45:26.88#ibcon#about to read 3, iclass 31, count 0 2006.285.15:45:26.92#ibcon#read 3, iclass 31, count 0 2006.285.15:45:26.92#ibcon#about to read 4, iclass 31, count 0 2006.285.15:45:26.92#ibcon#read 4, iclass 31, count 0 2006.285.15:45:26.92#ibcon#about to read 5, iclass 31, count 0 2006.285.15:45:26.92#ibcon#read 5, iclass 31, count 0 2006.285.15:45:26.92#ibcon#about to read 6, iclass 31, count 0 2006.285.15:45:26.92#ibcon#read 6, iclass 31, count 0 2006.285.15:45:26.92#ibcon#end of sib2, iclass 31, count 0 2006.285.15:45:26.92#ibcon#*after write, iclass 31, count 0 2006.285.15:45:26.92#ibcon#*before return 0, iclass 31, count 0 2006.285.15:45:26.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:45:26.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:45:26.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:45:26.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:45:26.92$vck44/va=2,6 2006.285.15:45:26.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.15:45:26.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.15:45:26.92#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:26.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:45:26.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:45:26.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:45:26.98#ibcon#enter wrdev, iclass 33, count 2 2006.285.15:45:26.98#ibcon#first serial, iclass 33, count 2 2006.285.15:45:26.98#ibcon#enter sib2, iclass 33, count 2 2006.285.15:45:26.98#ibcon#flushed, iclass 33, count 2 2006.285.15:45:26.98#ibcon#about to write, iclass 33, count 2 2006.285.15:45:26.98#ibcon#wrote, iclass 33, count 2 2006.285.15:45:26.98#ibcon#about to read 3, iclass 33, count 2 2006.285.15:45:27.00#ibcon#read 3, iclass 33, count 2 2006.285.15:45:27.00#ibcon#about to read 4, iclass 33, count 2 2006.285.15:45:27.00#ibcon#read 4, iclass 33, count 2 2006.285.15:45:27.00#ibcon#about to read 5, iclass 33, count 2 2006.285.15:45:27.00#ibcon#read 5, iclass 33, count 2 2006.285.15:45:27.00#ibcon#about to read 6, iclass 33, count 2 2006.285.15:45:27.00#ibcon#read 6, iclass 33, count 2 2006.285.15:45:27.00#ibcon#end of sib2, iclass 33, count 2 2006.285.15:45:27.00#ibcon#*mode == 0, iclass 33, count 2 2006.285.15:45:27.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.15:45:27.00#ibcon#[25=AT02-06\r\n] 2006.285.15:45:27.00#ibcon#*before write, iclass 33, count 2 2006.285.15:45:27.00#ibcon#enter sib2, iclass 33, count 2 2006.285.15:45:27.00#ibcon#flushed, iclass 33, count 2 2006.285.15:45:27.00#ibcon#about to write, iclass 33, count 2 2006.285.15:45:27.00#ibcon#wrote, iclass 33, count 2 2006.285.15:45:27.00#ibcon#about to read 3, iclass 33, count 2 2006.285.15:45:27.03#ibcon#read 3, iclass 33, count 2 2006.285.15:45:27.03#ibcon#about to read 4, iclass 33, count 2 2006.285.15:45:27.03#ibcon#read 4, iclass 33, count 2 2006.285.15:45:27.03#ibcon#about to read 5, iclass 33, count 2 2006.285.15:45:27.03#ibcon#read 5, iclass 33, count 2 2006.285.15:45:27.03#ibcon#about to read 6, iclass 33, count 2 2006.285.15:45:27.03#ibcon#read 6, iclass 33, count 2 2006.285.15:45:27.03#ibcon#end of sib2, iclass 33, count 2 2006.285.15:45:27.03#ibcon#*after write, iclass 33, count 2 2006.285.15:45:27.03#ibcon#*before return 0, iclass 33, count 2 2006.285.15:45:27.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:45:27.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:45:27.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.15:45:27.03#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:27.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:45:27.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:45:27.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:45:27.15#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:45:27.15#ibcon#first serial, iclass 33, count 0 2006.285.15:45:27.15#ibcon#enter sib2, iclass 33, count 0 2006.285.15:45:27.15#ibcon#flushed, iclass 33, count 0 2006.285.15:45:27.15#ibcon#about to write, iclass 33, count 0 2006.285.15:45:27.15#ibcon#wrote, iclass 33, count 0 2006.285.15:45:27.15#ibcon#about to read 3, iclass 33, count 0 2006.285.15:45:27.17#ibcon#read 3, iclass 33, count 0 2006.285.15:45:27.17#ibcon#about to read 4, iclass 33, count 0 2006.285.15:45:27.17#ibcon#read 4, iclass 33, count 0 2006.285.15:45:27.17#ibcon#about to read 5, iclass 33, count 0 2006.285.15:45:27.17#ibcon#read 5, iclass 33, count 0 2006.285.15:45:27.17#ibcon#about to read 6, iclass 33, count 0 2006.285.15:45:27.17#ibcon#read 6, iclass 33, count 0 2006.285.15:45:27.17#ibcon#end of sib2, iclass 33, count 0 2006.285.15:45:27.17#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:45:27.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:45:27.17#ibcon#[25=USB\r\n] 2006.285.15:45:27.17#ibcon#*before write, iclass 33, count 0 2006.285.15:45:27.17#ibcon#enter sib2, iclass 33, count 0 2006.285.15:45:27.17#ibcon#flushed, iclass 33, count 0 2006.285.15:45:27.17#ibcon#about to write, iclass 33, count 0 2006.285.15:45:27.17#ibcon#wrote, iclass 33, count 0 2006.285.15:45:27.17#ibcon#about to read 3, iclass 33, count 0 2006.285.15:45:27.20#ibcon#read 3, iclass 33, count 0 2006.285.15:45:27.20#ibcon#about to read 4, iclass 33, count 0 2006.285.15:45:27.20#ibcon#read 4, iclass 33, count 0 2006.285.15:45:27.20#ibcon#about to read 5, iclass 33, count 0 2006.285.15:45:27.20#ibcon#read 5, iclass 33, count 0 2006.285.15:45:27.20#ibcon#about to read 6, iclass 33, count 0 2006.285.15:45:27.20#ibcon#read 6, iclass 33, count 0 2006.285.15:45:27.20#ibcon#end of sib2, iclass 33, count 0 2006.285.15:45:27.20#ibcon#*after write, iclass 33, count 0 2006.285.15:45:27.20#ibcon#*before return 0, iclass 33, count 0 2006.285.15:45:27.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:45:27.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:45:27.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:45:27.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:45:27.20$vck44/valo=3,564.99 2006.285.15:45:27.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.15:45:27.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.15:45:27.20#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:27.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:45:27.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:45:27.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:45:27.20#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:45:27.20#ibcon#first serial, iclass 35, count 0 2006.285.15:45:27.20#ibcon#enter sib2, iclass 35, count 0 2006.285.15:45:27.20#ibcon#flushed, iclass 35, count 0 2006.285.15:45:27.20#ibcon#about to write, iclass 35, count 0 2006.285.15:45:27.20#ibcon#wrote, iclass 35, count 0 2006.285.15:45:27.20#ibcon#about to read 3, iclass 35, count 0 2006.285.15:45:27.22#ibcon#read 3, iclass 35, count 0 2006.285.15:45:27.22#ibcon#about to read 4, iclass 35, count 0 2006.285.15:45:27.22#ibcon#read 4, iclass 35, count 0 2006.285.15:45:27.22#ibcon#about to read 5, iclass 35, count 0 2006.285.15:45:27.22#ibcon#read 5, iclass 35, count 0 2006.285.15:45:27.22#ibcon#about to read 6, iclass 35, count 0 2006.285.15:45:27.22#ibcon#read 6, iclass 35, count 0 2006.285.15:45:27.22#ibcon#end of sib2, iclass 35, count 0 2006.285.15:45:27.22#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:45:27.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:45:27.22#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.15:45:27.22#ibcon#*before write, iclass 35, count 0 2006.285.15:45:27.22#ibcon#enter sib2, iclass 35, count 0 2006.285.15:45:27.22#ibcon#flushed, iclass 35, count 0 2006.285.15:45:27.22#ibcon#about to write, iclass 35, count 0 2006.285.15:45:27.22#ibcon#wrote, iclass 35, count 0 2006.285.15:45:27.22#ibcon#about to read 3, iclass 35, count 0 2006.285.15:45:27.26#ibcon#read 3, iclass 35, count 0 2006.285.15:45:27.26#ibcon#about to read 4, iclass 35, count 0 2006.285.15:45:27.26#ibcon#read 4, iclass 35, count 0 2006.285.15:45:27.26#ibcon#about to read 5, iclass 35, count 0 2006.285.15:45:27.26#ibcon#read 5, iclass 35, count 0 2006.285.15:45:27.26#ibcon#about to read 6, iclass 35, count 0 2006.285.15:45:27.26#ibcon#read 6, iclass 35, count 0 2006.285.15:45:27.26#ibcon#end of sib2, iclass 35, count 0 2006.285.15:45:27.26#ibcon#*after write, iclass 35, count 0 2006.285.15:45:27.26#ibcon#*before return 0, iclass 35, count 0 2006.285.15:45:27.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:45:27.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:45:27.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:45:27.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:45:27.26$vck44/va=3,7 2006.285.15:45:27.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.15:45:27.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.15:45:27.26#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:27.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:45:27.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:45:27.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:45:27.32#ibcon#enter wrdev, iclass 37, count 2 2006.285.15:45:27.32#ibcon#first serial, iclass 37, count 2 2006.285.15:45:27.32#ibcon#enter sib2, iclass 37, count 2 2006.285.15:45:27.32#ibcon#flushed, iclass 37, count 2 2006.285.15:45:27.32#ibcon#about to write, iclass 37, count 2 2006.285.15:45:27.32#ibcon#wrote, iclass 37, count 2 2006.285.15:45:27.32#ibcon#about to read 3, iclass 37, count 2 2006.285.15:45:27.34#ibcon#read 3, iclass 37, count 2 2006.285.15:45:27.34#ibcon#about to read 4, iclass 37, count 2 2006.285.15:45:27.34#ibcon#read 4, iclass 37, count 2 2006.285.15:45:27.34#ibcon#about to read 5, iclass 37, count 2 2006.285.15:45:27.34#ibcon#read 5, iclass 37, count 2 2006.285.15:45:27.34#ibcon#about to read 6, iclass 37, count 2 2006.285.15:45:27.34#ibcon#read 6, iclass 37, count 2 2006.285.15:45:27.34#ibcon#end of sib2, iclass 37, count 2 2006.285.15:45:27.34#ibcon#*mode == 0, iclass 37, count 2 2006.285.15:45:27.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.15:45:27.34#ibcon#[25=AT03-07\r\n] 2006.285.15:45:27.34#ibcon#*before write, iclass 37, count 2 2006.285.15:45:27.34#ibcon#enter sib2, iclass 37, count 2 2006.285.15:45:27.34#ibcon#flushed, iclass 37, count 2 2006.285.15:45:27.34#ibcon#about to write, iclass 37, count 2 2006.285.15:45:27.34#ibcon#wrote, iclass 37, count 2 2006.285.15:45:27.34#ibcon#about to read 3, iclass 37, count 2 2006.285.15:45:27.37#ibcon#read 3, iclass 37, count 2 2006.285.15:45:27.37#ibcon#about to read 4, iclass 37, count 2 2006.285.15:45:27.37#ibcon#read 4, iclass 37, count 2 2006.285.15:45:27.37#ibcon#about to read 5, iclass 37, count 2 2006.285.15:45:27.37#ibcon#read 5, iclass 37, count 2 2006.285.15:45:27.37#ibcon#about to read 6, iclass 37, count 2 2006.285.15:45:27.37#ibcon#read 6, iclass 37, count 2 2006.285.15:45:27.37#ibcon#end of sib2, iclass 37, count 2 2006.285.15:45:27.37#ibcon#*after write, iclass 37, count 2 2006.285.15:45:27.37#ibcon#*before return 0, iclass 37, count 2 2006.285.15:45:27.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:45:27.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:45:27.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.15:45:27.37#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:27.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:45:27.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:45:27.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:45:27.49#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:45:27.49#ibcon#first serial, iclass 37, count 0 2006.285.15:45:27.49#ibcon#enter sib2, iclass 37, count 0 2006.285.15:45:27.49#ibcon#flushed, iclass 37, count 0 2006.285.15:45:27.49#ibcon#about to write, iclass 37, count 0 2006.285.15:45:27.49#ibcon#wrote, iclass 37, count 0 2006.285.15:45:27.49#ibcon#about to read 3, iclass 37, count 0 2006.285.15:45:27.51#ibcon#read 3, iclass 37, count 0 2006.285.15:45:27.51#ibcon#about to read 4, iclass 37, count 0 2006.285.15:45:27.51#ibcon#read 4, iclass 37, count 0 2006.285.15:45:27.51#ibcon#about to read 5, iclass 37, count 0 2006.285.15:45:27.51#ibcon#read 5, iclass 37, count 0 2006.285.15:45:27.51#ibcon#about to read 6, iclass 37, count 0 2006.285.15:45:27.51#ibcon#read 6, iclass 37, count 0 2006.285.15:45:27.51#ibcon#end of sib2, iclass 37, count 0 2006.285.15:45:27.51#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:45:27.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:45:27.51#ibcon#[25=USB\r\n] 2006.285.15:45:27.51#ibcon#*before write, iclass 37, count 0 2006.285.15:45:27.51#ibcon#enter sib2, iclass 37, count 0 2006.285.15:45:27.51#ibcon#flushed, iclass 37, count 0 2006.285.15:45:27.51#ibcon#about to write, iclass 37, count 0 2006.285.15:45:27.51#ibcon#wrote, iclass 37, count 0 2006.285.15:45:27.51#ibcon#about to read 3, iclass 37, count 0 2006.285.15:45:27.54#ibcon#read 3, iclass 37, count 0 2006.285.15:45:27.54#ibcon#about to read 4, iclass 37, count 0 2006.285.15:45:27.54#ibcon#read 4, iclass 37, count 0 2006.285.15:45:27.54#ibcon#about to read 5, iclass 37, count 0 2006.285.15:45:27.54#ibcon#read 5, iclass 37, count 0 2006.285.15:45:27.54#ibcon#about to read 6, iclass 37, count 0 2006.285.15:45:27.54#ibcon#read 6, iclass 37, count 0 2006.285.15:45:27.54#ibcon#end of sib2, iclass 37, count 0 2006.285.15:45:27.54#ibcon#*after write, iclass 37, count 0 2006.285.15:45:27.54#ibcon#*before return 0, iclass 37, count 0 2006.285.15:45:27.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:45:27.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:45:27.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:45:27.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:45:27.54$vck44/valo=4,624.99 2006.285.15:45:27.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.15:45:27.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.15:45:27.54#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:27.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:45:27.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:45:27.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:45:27.54#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:45:27.54#ibcon#first serial, iclass 39, count 0 2006.285.15:45:27.54#ibcon#enter sib2, iclass 39, count 0 2006.285.15:45:27.54#ibcon#flushed, iclass 39, count 0 2006.285.15:45:27.54#ibcon#about to write, iclass 39, count 0 2006.285.15:45:27.54#ibcon#wrote, iclass 39, count 0 2006.285.15:45:27.54#ibcon#about to read 3, iclass 39, count 0 2006.285.15:45:27.56#ibcon#read 3, iclass 39, count 0 2006.285.15:45:27.56#ibcon#about to read 4, iclass 39, count 0 2006.285.15:45:27.56#ibcon#read 4, iclass 39, count 0 2006.285.15:45:27.56#ibcon#about to read 5, iclass 39, count 0 2006.285.15:45:27.56#ibcon#read 5, iclass 39, count 0 2006.285.15:45:27.56#ibcon#about to read 6, iclass 39, count 0 2006.285.15:45:27.56#ibcon#read 6, iclass 39, count 0 2006.285.15:45:27.56#ibcon#end of sib2, iclass 39, count 0 2006.285.15:45:27.56#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:45:27.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:45:27.56#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.15:45:27.56#ibcon#*before write, iclass 39, count 0 2006.285.15:45:27.56#ibcon#enter sib2, iclass 39, count 0 2006.285.15:45:27.56#ibcon#flushed, iclass 39, count 0 2006.285.15:45:27.56#ibcon#about to write, iclass 39, count 0 2006.285.15:45:27.56#ibcon#wrote, iclass 39, count 0 2006.285.15:45:27.56#ibcon#about to read 3, iclass 39, count 0 2006.285.15:45:27.60#ibcon#read 3, iclass 39, count 0 2006.285.15:45:27.60#ibcon#about to read 4, iclass 39, count 0 2006.285.15:45:27.60#ibcon#read 4, iclass 39, count 0 2006.285.15:45:27.60#ibcon#about to read 5, iclass 39, count 0 2006.285.15:45:27.60#ibcon#read 5, iclass 39, count 0 2006.285.15:45:27.60#ibcon#about to read 6, iclass 39, count 0 2006.285.15:45:27.60#ibcon#read 6, iclass 39, count 0 2006.285.15:45:27.60#ibcon#end of sib2, iclass 39, count 0 2006.285.15:45:27.60#ibcon#*after write, iclass 39, count 0 2006.285.15:45:27.60#ibcon#*before return 0, iclass 39, count 0 2006.285.15:45:27.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:45:27.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:45:27.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:45:27.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:45:27.60$vck44/va=4,6 2006.285.15:45:28.03#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.15:45:28.03#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.15:45:28.03#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:28.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:45:28.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:45:28.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:45:28.03#ibcon#enter wrdev, iclass 3, count 2 2006.285.15:45:28.03#ibcon#first serial, iclass 3, count 2 2006.285.15:45:28.03#ibcon#enter sib2, iclass 3, count 2 2006.285.15:45:28.03#ibcon#flushed, iclass 3, count 2 2006.285.15:45:28.03#ibcon#about to write, iclass 3, count 2 2006.285.15:45:28.03#ibcon#wrote, iclass 3, count 2 2006.285.15:45:28.03#ibcon#about to read 3, iclass 3, count 2 2006.285.15:45:28.05#ibcon#read 3, iclass 3, count 2 2006.285.15:45:28.05#ibcon#about to read 4, iclass 3, count 2 2006.285.15:45:28.05#ibcon#read 4, iclass 3, count 2 2006.285.15:45:28.05#ibcon#about to read 5, iclass 3, count 2 2006.285.15:45:28.05#ibcon#read 5, iclass 3, count 2 2006.285.15:45:28.05#ibcon#about to read 6, iclass 3, count 2 2006.285.15:45:28.05#ibcon#read 6, iclass 3, count 2 2006.285.15:45:28.05#ibcon#end of sib2, iclass 3, count 2 2006.285.15:45:28.05#ibcon#*mode == 0, iclass 3, count 2 2006.285.15:45:28.05#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.15:45:28.05#ibcon#[25=AT04-06\r\n] 2006.285.15:45:28.05#ibcon#*before write, iclass 3, count 2 2006.285.15:45:28.05#ibcon#enter sib2, iclass 3, count 2 2006.285.15:45:28.05#ibcon#flushed, iclass 3, count 2 2006.285.15:45:28.05#ibcon#about to write, iclass 3, count 2 2006.285.15:45:28.05#ibcon#wrote, iclass 3, count 2 2006.285.15:45:28.05#ibcon#about to read 3, iclass 3, count 2 2006.285.15:45:28.08#ibcon#read 3, iclass 3, count 2 2006.285.15:45:28.08#ibcon#about to read 4, iclass 3, count 2 2006.285.15:45:28.08#ibcon#read 4, iclass 3, count 2 2006.285.15:45:28.08#ibcon#about to read 5, iclass 3, count 2 2006.285.15:45:28.08#ibcon#read 5, iclass 3, count 2 2006.285.15:45:28.08#ibcon#about to read 6, iclass 3, count 2 2006.285.15:45:28.08#ibcon#read 6, iclass 3, count 2 2006.285.15:45:28.08#ibcon#end of sib2, iclass 3, count 2 2006.285.15:45:28.08#ibcon#*after write, iclass 3, count 2 2006.285.15:45:28.08#ibcon#*before return 0, iclass 3, count 2 2006.285.15:45:28.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:45:28.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:45:28.08#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.15:45:28.08#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:28.08#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:45:28.20#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:45:28.20#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:45:28.20#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:45:28.20#ibcon#first serial, iclass 3, count 0 2006.285.15:45:28.20#ibcon#enter sib2, iclass 3, count 0 2006.285.15:45:28.20#ibcon#flushed, iclass 3, count 0 2006.285.15:45:28.20#ibcon#about to write, iclass 3, count 0 2006.285.15:45:28.20#ibcon#wrote, iclass 3, count 0 2006.285.15:45:28.20#ibcon#about to read 3, iclass 3, count 0 2006.285.15:45:28.22#ibcon#read 3, iclass 3, count 0 2006.285.15:45:28.22#ibcon#about to read 4, iclass 3, count 0 2006.285.15:45:28.22#ibcon#read 4, iclass 3, count 0 2006.285.15:45:28.22#ibcon#about to read 5, iclass 3, count 0 2006.285.15:45:28.22#ibcon#read 5, iclass 3, count 0 2006.285.15:45:28.22#ibcon#about to read 6, iclass 3, count 0 2006.285.15:45:28.22#ibcon#read 6, iclass 3, count 0 2006.285.15:45:28.22#ibcon#end of sib2, iclass 3, count 0 2006.285.15:45:28.22#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:45:28.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:45:28.22#ibcon#[25=USB\r\n] 2006.285.15:45:28.22#ibcon#*before write, iclass 3, count 0 2006.285.15:45:28.22#ibcon#enter sib2, iclass 3, count 0 2006.285.15:45:28.22#ibcon#flushed, iclass 3, count 0 2006.285.15:45:28.22#ibcon#about to write, iclass 3, count 0 2006.285.15:45:28.22#ibcon#wrote, iclass 3, count 0 2006.285.15:45:28.22#ibcon#about to read 3, iclass 3, count 0 2006.285.15:45:28.25#ibcon#read 3, iclass 3, count 0 2006.285.15:45:28.25#ibcon#about to read 4, iclass 3, count 0 2006.285.15:45:28.25#ibcon#read 4, iclass 3, count 0 2006.285.15:45:28.25#ibcon#about to read 5, iclass 3, count 0 2006.285.15:45:28.25#ibcon#read 5, iclass 3, count 0 2006.285.15:45:28.25#ibcon#about to read 6, iclass 3, count 0 2006.285.15:45:28.25#ibcon#read 6, iclass 3, count 0 2006.285.15:45:28.25#ibcon#end of sib2, iclass 3, count 0 2006.285.15:45:28.25#ibcon#*after write, iclass 3, count 0 2006.285.15:45:28.25#ibcon#*before return 0, iclass 3, count 0 2006.285.15:45:28.25#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:45:28.25#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:45:28.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:45:28.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:45:28.25$vck44/valo=5,734.99 2006.285.15:45:28.25#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.15:45:28.25#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.15:45:28.25#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:28.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:45:28.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:45:28.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:45:28.25#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:45:28.25#ibcon#first serial, iclass 5, count 0 2006.285.15:45:28.25#ibcon#enter sib2, iclass 5, count 0 2006.285.15:45:28.25#ibcon#flushed, iclass 5, count 0 2006.285.15:45:28.25#ibcon#about to write, iclass 5, count 0 2006.285.15:45:28.25#ibcon#wrote, iclass 5, count 0 2006.285.15:45:28.25#ibcon#about to read 3, iclass 5, count 0 2006.285.15:45:28.27#ibcon#read 3, iclass 5, count 0 2006.285.15:45:28.27#ibcon#about to read 4, iclass 5, count 0 2006.285.15:45:28.27#ibcon#read 4, iclass 5, count 0 2006.285.15:45:28.27#ibcon#about to read 5, iclass 5, count 0 2006.285.15:45:28.27#ibcon#read 5, iclass 5, count 0 2006.285.15:45:28.27#ibcon#about to read 6, iclass 5, count 0 2006.285.15:45:28.27#ibcon#read 6, iclass 5, count 0 2006.285.15:45:28.27#ibcon#end of sib2, iclass 5, count 0 2006.285.15:45:28.27#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:45:28.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:45:28.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.15:45:28.27#ibcon#*before write, iclass 5, count 0 2006.285.15:45:28.27#ibcon#enter sib2, iclass 5, count 0 2006.285.15:45:28.27#ibcon#flushed, iclass 5, count 0 2006.285.15:45:28.27#ibcon#about to write, iclass 5, count 0 2006.285.15:45:28.27#ibcon#wrote, iclass 5, count 0 2006.285.15:45:28.27#ibcon#about to read 3, iclass 5, count 0 2006.285.15:45:28.31#ibcon#read 3, iclass 5, count 0 2006.285.15:45:28.31#ibcon#about to read 4, iclass 5, count 0 2006.285.15:45:28.31#ibcon#read 4, iclass 5, count 0 2006.285.15:45:28.31#ibcon#about to read 5, iclass 5, count 0 2006.285.15:45:28.31#ibcon#read 5, iclass 5, count 0 2006.285.15:45:28.31#ibcon#about to read 6, iclass 5, count 0 2006.285.15:45:28.31#ibcon#read 6, iclass 5, count 0 2006.285.15:45:28.31#ibcon#end of sib2, iclass 5, count 0 2006.285.15:45:28.31#ibcon#*after write, iclass 5, count 0 2006.285.15:45:28.31#ibcon#*before return 0, iclass 5, count 0 2006.285.15:45:28.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:45:28.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:45:28.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:45:28.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:45:28.31$vck44/va=5,3 2006.285.15:45:28.56#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.15:45:28.56#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.15:45:28.56#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:28.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:45:28.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:45:28.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:45:28.56#ibcon#enter wrdev, iclass 7, count 2 2006.285.15:45:28.56#ibcon#first serial, iclass 7, count 2 2006.285.15:45:28.56#ibcon#enter sib2, iclass 7, count 2 2006.285.15:45:28.56#ibcon#flushed, iclass 7, count 2 2006.285.15:45:28.56#ibcon#about to write, iclass 7, count 2 2006.285.15:45:28.56#ibcon#wrote, iclass 7, count 2 2006.285.15:45:28.56#ibcon#about to read 3, iclass 7, count 2 2006.285.15:45:28.58#ibcon#read 3, iclass 7, count 2 2006.285.15:45:28.58#ibcon#about to read 4, iclass 7, count 2 2006.285.15:45:28.58#ibcon#read 4, iclass 7, count 2 2006.285.15:45:28.58#ibcon#about to read 5, iclass 7, count 2 2006.285.15:45:28.58#ibcon#read 5, iclass 7, count 2 2006.285.15:45:28.58#ibcon#about to read 6, iclass 7, count 2 2006.285.15:45:28.58#ibcon#read 6, iclass 7, count 2 2006.285.15:45:28.58#ibcon#end of sib2, iclass 7, count 2 2006.285.15:45:28.58#ibcon#*mode == 0, iclass 7, count 2 2006.285.15:45:28.58#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.15:45:28.58#ibcon#[25=AT05-03\r\n] 2006.285.15:45:28.58#ibcon#*before write, iclass 7, count 2 2006.285.15:45:28.58#ibcon#enter sib2, iclass 7, count 2 2006.285.15:45:28.58#ibcon#flushed, iclass 7, count 2 2006.285.15:45:28.58#ibcon#about to write, iclass 7, count 2 2006.285.15:45:28.58#ibcon#wrote, iclass 7, count 2 2006.285.15:45:28.58#ibcon#about to read 3, iclass 7, count 2 2006.285.15:45:28.61#ibcon#read 3, iclass 7, count 2 2006.285.15:45:28.61#ibcon#about to read 4, iclass 7, count 2 2006.285.15:45:28.61#ibcon#read 4, iclass 7, count 2 2006.285.15:45:28.61#ibcon#about to read 5, iclass 7, count 2 2006.285.15:45:28.61#ibcon#read 5, iclass 7, count 2 2006.285.15:45:28.61#ibcon#about to read 6, iclass 7, count 2 2006.285.15:45:28.61#ibcon#read 6, iclass 7, count 2 2006.285.15:45:28.61#ibcon#end of sib2, iclass 7, count 2 2006.285.15:45:28.61#ibcon#*after write, iclass 7, count 2 2006.285.15:45:28.61#ibcon#*before return 0, iclass 7, count 2 2006.285.15:45:28.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:45:28.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:45:28.61#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.15:45:28.61#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:28.61#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:45:28.73#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:45:28.73#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:45:28.73#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:45:28.73#ibcon#first serial, iclass 7, count 0 2006.285.15:45:28.73#ibcon#enter sib2, iclass 7, count 0 2006.285.15:45:28.73#ibcon#flushed, iclass 7, count 0 2006.285.15:45:28.73#ibcon#about to write, iclass 7, count 0 2006.285.15:45:28.73#ibcon#wrote, iclass 7, count 0 2006.285.15:45:28.73#ibcon#about to read 3, iclass 7, count 0 2006.285.15:45:28.75#ibcon#read 3, iclass 7, count 0 2006.285.15:45:28.75#ibcon#about to read 4, iclass 7, count 0 2006.285.15:45:28.75#ibcon#read 4, iclass 7, count 0 2006.285.15:45:28.75#ibcon#about to read 5, iclass 7, count 0 2006.285.15:45:28.75#ibcon#read 5, iclass 7, count 0 2006.285.15:45:28.75#ibcon#about to read 6, iclass 7, count 0 2006.285.15:45:28.75#ibcon#read 6, iclass 7, count 0 2006.285.15:45:28.75#ibcon#end of sib2, iclass 7, count 0 2006.285.15:45:28.75#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:45:28.75#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:45:28.75#ibcon#[25=USB\r\n] 2006.285.15:45:28.75#ibcon#*before write, iclass 7, count 0 2006.285.15:45:28.75#ibcon#enter sib2, iclass 7, count 0 2006.285.15:45:28.75#ibcon#flushed, iclass 7, count 0 2006.285.15:45:28.75#ibcon#about to write, iclass 7, count 0 2006.285.15:45:28.75#ibcon#wrote, iclass 7, count 0 2006.285.15:45:28.75#ibcon#about to read 3, iclass 7, count 0 2006.285.15:45:28.78#ibcon#read 3, iclass 7, count 0 2006.285.15:45:28.78#ibcon#about to read 4, iclass 7, count 0 2006.285.15:45:28.78#ibcon#read 4, iclass 7, count 0 2006.285.15:45:28.78#ibcon#about to read 5, iclass 7, count 0 2006.285.15:45:28.78#ibcon#read 5, iclass 7, count 0 2006.285.15:45:28.78#ibcon#about to read 6, iclass 7, count 0 2006.285.15:45:28.78#ibcon#read 6, iclass 7, count 0 2006.285.15:45:28.78#ibcon#end of sib2, iclass 7, count 0 2006.285.15:45:28.78#ibcon#*after write, iclass 7, count 0 2006.285.15:45:28.78#ibcon#*before return 0, iclass 7, count 0 2006.285.15:45:28.78#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:45:28.78#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:45:28.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:45:28.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:45:28.78$vck44/valo=6,814.99 2006.285.15:45:28.78#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.15:45:28.78#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.15:45:28.78#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:28.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:45:28.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:45:28.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:45:28.78#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:45:28.78#ibcon#first serial, iclass 11, count 0 2006.285.15:45:28.78#ibcon#enter sib2, iclass 11, count 0 2006.285.15:45:28.78#ibcon#flushed, iclass 11, count 0 2006.285.15:45:28.78#ibcon#about to write, iclass 11, count 0 2006.285.15:45:28.78#ibcon#wrote, iclass 11, count 0 2006.285.15:45:28.78#ibcon#about to read 3, iclass 11, count 0 2006.285.15:45:28.80#ibcon#read 3, iclass 11, count 0 2006.285.15:45:28.80#ibcon#about to read 4, iclass 11, count 0 2006.285.15:45:28.80#ibcon#read 4, iclass 11, count 0 2006.285.15:45:28.80#ibcon#about to read 5, iclass 11, count 0 2006.285.15:45:28.80#ibcon#read 5, iclass 11, count 0 2006.285.15:45:28.80#ibcon#about to read 6, iclass 11, count 0 2006.285.15:45:28.80#ibcon#read 6, iclass 11, count 0 2006.285.15:45:28.80#ibcon#end of sib2, iclass 11, count 0 2006.285.15:45:28.80#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:45:28.80#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:45:28.80#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.15:45:28.80#ibcon#*before write, iclass 11, count 0 2006.285.15:45:28.80#ibcon#enter sib2, iclass 11, count 0 2006.285.15:45:28.80#ibcon#flushed, iclass 11, count 0 2006.285.15:45:28.80#ibcon#about to write, iclass 11, count 0 2006.285.15:45:28.80#ibcon#wrote, iclass 11, count 0 2006.285.15:45:28.80#ibcon#about to read 3, iclass 11, count 0 2006.285.15:45:28.84#ibcon#read 3, iclass 11, count 0 2006.285.15:45:28.84#ibcon#about to read 4, iclass 11, count 0 2006.285.15:45:28.84#ibcon#read 4, iclass 11, count 0 2006.285.15:45:28.84#ibcon#about to read 5, iclass 11, count 0 2006.285.15:45:28.84#ibcon#read 5, iclass 11, count 0 2006.285.15:45:28.84#ibcon#about to read 6, iclass 11, count 0 2006.285.15:45:28.84#ibcon#read 6, iclass 11, count 0 2006.285.15:45:28.84#ibcon#end of sib2, iclass 11, count 0 2006.285.15:45:28.84#ibcon#*after write, iclass 11, count 0 2006.285.15:45:28.84#ibcon#*before return 0, iclass 11, count 0 2006.285.15:45:28.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:45:28.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:45:28.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:45:28.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:45:28.84$vck44/va=6,4 2006.285.15:45:28.84#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.15:45:28.84#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.15:45:28.84#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:28.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:45:28.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:45:28.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:45:28.90#ibcon#enter wrdev, iclass 13, count 2 2006.285.15:45:28.90#ibcon#first serial, iclass 13, count 2 2006.285.15:45:28.90#ibcon#enter sib2, iclass 13, count 2 2006.285.15:45:28.90#ibcon#flushed, iclass 13, count 2 2006.285.15:45:28.90#ibcon#about to write, iclass 13, count 2 2006.285.15:45:28.90#ibcon#wrote, iclass 13, count 2 2006.285.15:45:28.90#ibcon#about to read 3, iclass 13, count 2 2006.285.15:45:28.92#ibcon#read 3, iclass 13, count 2 2006.285.15:45:28.92#ibcon#about to read 4, iclass 13, count 2 2006.285.15:45:28.92#ibcon#read 4, iclass 13, count 2 2006.285.15:45:28.92#ibcon#about to read 5, iclass 13, count 2 2006.285.15:45:28.92#ibcon#read 5, iclass 13, count 2 2006.285.15:45:28.92#ibcon#about to read 6, iclass 13, count 2 2006.285.15:45:28.92#ibcon#read 6, iclass 13, count 2 2006.285.15:45:28.92#ibcon#end of sib2, iclass 13, count 2 2006.285.15:45:28.92#ibcon#*mode == 0, iclass 13, count 2 2006.285.15:45:28.92#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.15:45:28.92#ibcon#[25=AT06-04\r\n] 2006.285.15:45:28.92#ibcon#*before write, iclass 13, count 2 2006.285.15:45:28.92#ibcon#enter sib2, iclass 13, count 2 2006.285.15:45:28.92#ibcon#flushed, iclass 13, count 2 2006.285.15:45:28.92#ibcon#about to write, iclass 13, count 2 2006.285.15:45:28.92#ibcon#wrote, iclass 13, count 2 2006.285.15:45:28.92#ibcon#about to read 3, iclass 13, count 2 2006.285.15:45:28.95#ibcon#read 3, iclass 13, count 2 2006.285.15:45:28.95#ibcon#about to read 4, iclass 13, count 2 2006.285.15:45:28.95#ibcon#read 4, iclass 13, count 2 2006.285.15:45:28.95#ibcon#about to read 5, iclass 13, count 2 2006.285.15:45:28.95#ibcon#read 5, iclass 13, count 2 2006.285.15:45:28.95#ibcon#about to read 6, iclass 13, count 2 2006.285.15:45:28.95#ibcon#read 6, iclass 13, count 2 2006.285.15:45:28.95#ibcon#end of sib2, iclass 13, count 2 2006.285.15:45:28.95#ibcon#*after write, iclass 13, count 2 2006.285.15:45:28.95#ibcon#*before return 0, iclass 13, count 2 2006.285.15:45:28.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:45:28.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:45:28.95#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.15:45:28.95#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:28.95#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:45:29.07#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:45:29.07#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:45:29.07#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:45:29.07#ibcon#first serial, iclass 13, count 0 2006.285.15:45:29.07#ibcon#enter sib2, iclass 13, count 0 2006.285.15:45:29.07#ibcon#flushed, iclass 13, count 0 2006.285.15:45:29.07#ibcon#about to write, iclass 13, count 0 2006.285.15:45:29.07#ibcon#wrote, iclass 13, count 0 2006.285.15:45:29.07#ibcon#about to read 3, iclass 13, count 0 2006.285.15:45:29.09#ibcon#read 3, iclass 13, count 0 2006.285.15:45:29.09#ibcon#about to read 4, iclass 13, count 0 2006.285.15:45:29.09#ibcon#read 4, iclass 13, count 0 2006.285.15:45:29.09#ibcon#about to read 5, iclass 13, count 0 2006.285.15:45:29.09#ibcon#read 5, iclass 13, count 0 2006.285.15:45:29.09#ibcon#about to read 6, iclass 13, count 0 2006.285.15:45:29.09#ibcon#read 6, iclass 13, count 0 2006.285.15:45:29.09#ibcon#end of sib2, iclass 13, count 0 2006.285.15:45:29.09#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:45:29.09#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:45:29.09#ibcon#[25=USB\r\n] 2006.285.15:45:29.09#ibcon#*before write, iclass 13, count 0 2006.285.15:45:29.09#ibcon#enter sib2, iclass 13, count 0 2006.285.15:45:29.09#ibcon#flushed, iclass 13, count 0 2006.285.15:45:29.09#ibcon#about to write, iclass 13, count 0 2006.285.15:45:29.09#ibcon#wrote, iclass 13, count 0 2006.285.15:45:29.09#ibcon#about to read 3, iclass 13, count 0 2006.285.15:45:29.12#ibcon#read 3, iclass 13, count 0 2006.285.15:45:29.12#ibcon#about to read 4, iclass 13, count 0 2006.285.15:45:29.12#ibcon#read 4, iclass 13, count 0 2006.285.15:45:29.12#ibcon#about to read 5, iclass 13, count 0 2006.285.15:45:29.12#ibcon#read 5, iclass 13, count 0 2006.285.15:45:29.12#ibcon#about to read 6, iclass 13, count 0 2006.285.15:45:29.12#ibcon#read 6, iclass 13, count 0 2006.285.15:45:29.12#ibcon#end of sib2, iclass 13, count 0 2006.285.15:45:29.12#ibcon#*after write, iclass 13, count 0 2006.285.15:45:29.12#ibcon#*before return 0, iclass 13, count 0 2006.285.15:45:29.12#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:45:29.12#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:45:29.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:45:29.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:45:29.12$vck44/valo=7,864.99 2006.285.15:45:29.12#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.15:45:29.12#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.15:45:29.12#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:29.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:45:29.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:45:29.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:45:29.12#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:45:29.12#ibcon#first serial, iclass 15, count 0 2006.285.15:45:29.12#ibcon#enter sib2, iclass 15, count 0 2006.285.15:45:29.12#ibcon#flushed, iclass 15, count 0 2006.285.15:45:29.12#ibcon#about to write, iclass 15, count 0 2006.285.15:45:29.12#ibcon#wrote, iclass 15, count 0 2006.285.15:45:29.12#ibcon#about to read 3, iclass 15, count 0 2006.285.15:45:29.14#ibcon#read 3, iclass 15, count 0 2006.285.15:45:29.14#ibcon#about to read 4, iclass 15, count 0 2006.285.15:45:29.14#ibcon#read 4, iclass 15, count 0 2006.285.15:45:29.14#ibcon#about to read 5, iclass 15, count 0 2006.285.15:45:29.14#ibcon#read 5, iclass 15, count 0 2006.285.15:45:29.14#ibcon#about to read 6, iclass 15, count 0 2006.285.15:45:29.14#ibcon#read 6, iclass 15, count 0 2006.285.15:45:29.14#ibcon#end of sib2, iclass 15, count 0 2006.285.15:45:29.14#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:45:29.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:45:29.14#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.15:45:29.14#ibcon#*before write, iclass 15, count 0 2006.285.15:45:29.14#ibcon#enter sib2, iclass 15, count 0 2006.285.15:45:29.14#ibcon#flushed, iclass 15, count 0 2006.285.15:45:29.14#ibcon#about to write, iclass 15, count 0 2006.285.15:45:29.14#ibcon#wrote, iclass 15, count 0 2006.285.15:45:29.14#ibcon#about to read 3, iclass 15, count 0 2006.285.15:45:29.18#ibcon#read 3, iclass 15, count 0 2006.285.15:45:29.18#ibcon#about to read 4, iclass 15, count 0 2006.285.15:45:29.18#ibcon#read 4, iclass 15, count 0 2006.285.15:45:29.18#ibcon#about to read 5, iclass 15, count 0 2006.285.15:45:29.18#ibcon#read 5, iclass 15, count 0 2006.285.15:45:29.18#ibcon#about to read 6, iclass 15, count 0 2006.285.15:45:29.18#ibcon#read 6, iclass 15, count 0 2006.285.15:45:29.18#ibcon#end of sib2, iclass 15, count 0 2006.285.15:45:29.18#ibcon#*after write, iclass 15, count 0 2006.285.15:45:29.18#ibcon#*before return 0, iclass 15, count 0 2006.285.15:45:29.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:45:29.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:45:29.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:45:29.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:45:29.18$vck44/va=7,4 2006.285.15:45:29.18#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.15:45:29.18#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.15:45:29.18#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:29.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:45:29.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:45:29.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:45:29.24#ibcon#enter wrdev, iclass 17, count 2 2006.285.15:45:29.24#ibcon#first serial, iclass 17, count 2 2006.285.15:45:29.24#ibcon#enter sib2, iclass 17, count 2 2006.285.15:45:29.24#ibcon#flushed, iclass 17, count 2 2006.285.15:45:29.24#ibcon#about to write, iclass 17, count 2 2006.285.15:45:29.24#ibcon#wrote, iclass 17, count 2 2006.285.15:45:29.24#ibcon#about to read 3, iclass 17, count 2 2006.285.15:45:29.26#ibcon#read 3, iclass 17, count 2 2006.285.15:45:29.26#ibcon#about to read 4, iclass 17, count 2 2006.285.15:45:29.26#ibcon#read 4, iclass 17, count 2 2006.285.15:45:29.26#ibcon#about to read 5, iclass 17, count 2 2006.285.15:45:29.26#ibcon#read 5, iclass 17, count 2 2006.285.15:45:29.26#ibcon#about to read 6, iclass 17, count 2 2006.285.15:45:29.26#ibcon#read 6, iclass 17, count 2 2006.285.15:45:29.26#ibcon#end of sib2, iclass 17, count 2 2006.285.15:45:29.26#ibcon#*mode == 0, iclass 17, count 2 2006.285.15:45:29.26#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.15:45:29.26#ibcon#[25=AT07-04\r\n] 2006.285.15:45:29.26#ibcon#*before write, iclass 17, count 2 2006.285.15:45:29.26#ibcon#enter sib2, iclass 17, count 2 2006.285.15:45:29.26#ibcon#flushed, iclass 17, count 2 2006.285.15:45:29.26#ibcon#about to write, iclass 17, count 2 2006.285.15:45:29.26#ibcon#wrote, iclass 17, count 2 2006.285.15:45:29.26#ibcon#about to read 3, iclass 17, count 2 2006.285.15:45:29.29#ibcon#read 3, iclass 17, count 2 2006.285.15:45:29.29#ibcon#about to read 4, iclass 17, count 2 2006.285.15:45:29.29#ibcon#read 4, iclass 17, count 2 2006.285.15:45:29.29#ibcon#about to read 5, iclass 17, count 2 2006.285.15:45:29.29#ibcon#read 5, iclass 17, count 2 2006.285.15:45:29.29#ibcon#about to read 6, iclass 17, count 2 2006.285.15:45:29.29#ibcon#read 6, iclass 17, count 2 2006.285.15:45:29.29#ibcon#end of sib2, iclass 17, count 2 2006.285.15:45:29.29#ibcon#*after write, iclass 17, count 2 2006.285.15:45:29.29#ibcon#*before return 0, iclass 17, count 2 2006.285.15:45:29.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:45:29.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:45:29.29#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.15:45:29.29#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:29.29#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:45:29.41#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:45:29.41#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:45:29.41#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:45:29.41#ibcon#first serial, iclass 17, count 0 2006.285.15:45:29.41#ibcon#enter sib2, iclass 17, count 0 2006.285.15:45:29.41#ibcon#flushed, iclass 17, count 0 2006.285.15:45:29.41#ibcon#about to write, iclass 17, count 0 2006.285.15:45:29.41#ibcon#wrote, iclass 17, count 0 2006.285.15:45:29.41#ibcon#about to read 3, iclass 17, count 0 2006.285.15:45:29.43#ibcon#read 3, iclass 17, count 0 2006.285.15:45:29.43#ibcon#about to read 4, iclass 17, count 0 2006.285.15:45:29.43#ibcon#read 4, iclass 17, count 0 2006.285.15:45:29.43#ibcon#about to read 5, iclass 17, count 0 2006.285.15:45:29.43#ibcon#read 5, iclass 17, count 0 2006.285.15:45:29.43#ibcon#about to read 6, iclass 17, count 0 2006.285.15:45:29.43#ibcon#read 6, iclass 17, count 0 2006.285.15:45:29.43#ibcon#end of sib2, iclass 17, count 0 2006.285.15:45:29.43#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:45:29.43#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:45:29.43#ibcon#[25=USB\r\n] 2006.285.15:45:29.43#ibcon#*before write, iclass 17, count 0 2006.285.15:45:29.43#ibcon#enter sib2, iclass 17, count 0 2006.285.15:45:29.43#ibcon#flushed, iclass 17, count 0 2006.285.15:45:29.43#ibcon#about to write, iclass 17, count 0 2006.285.15:45:29.43#ibcon#wrote, iclass 17, count 0 2006.285.15:45:29.43#ibcon#about to read 3, iclass 17, count 0 2006.285.15:45:29.46#ibcon#read 3, iclass 17, count 0 2006.285.15:45:29.46#ibcon#about to read 4, iclass 17, count 0 2006.285.15:45:29.46#ibcon#read 4, iclass 17, count 0 2006.285.15:45:29.46#ibcon#about to read 5, iclass 17, count 0 2006.285.15:45:29.46#ibcon#read 5, iclass 17, count 0 2006.285.15:45:29.46#ibcon#about to read 6, iclass 17, count 0 2006.285.15:45:29.46#ibcon#read 6, iclass 17, count 0 2006.285.15:45:29.46#ibcon#end of sib2, iclass 17, count 0 2006.285.15:45:29.46#ibcon#*after write, iclass 17, count 0 2006.285.15:45:29.46#ibcon#*before return 0, iclass 17, count 0 2006.285.15:45:29.46#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:45:29.46#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:45:29.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:45:29.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:45:29.46$vck44/valo=8,884.99 2006.285.15:45:29.46#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.15:45:29.46#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.15:45:29.46#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:29.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:45:29.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:45:29.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:45:29.46#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:45:29.46#ibcon#first serial, iclass 19, count 0 2006.285.15:45:29.46#ibcon#enter sib2, iclass 19, count 0 2006.285.15:45:29.46#ibcon#flushed, iclass 19, count 0 2006.285.15:45:29.46#ibcon#about to write, iclass 19, count 0 2006.285.15:45:29.46#ibcon#wrote, iclass 19, count 0 2006.285.15:45:29.46#ibcon#about to read 3, iclass 19, count 0 2006.285.15:45:29.48#ibcon#read 3, iclass 19, count 0 2006.285.15:45:29.48#ibcon#about to read 4, iclass 19, count 0 2006.285.15:45:29.48#ibcon#read 4, iclass 19, count 0 2006.285.15:45:29.48#ibcon#about to read 5, iclass 19, count 0 2006.285.15:45:29.48#ibcon#read 5, iclass 19, count 0 2006.285.15:45:29.48#ibcon#about to read 6, iclass 19, count 0 2006.285.15:45:29.48#ibcon#read 6, iclass 19, count 0 2006.285.15:45:29.48#ibcon#end of sib2, iclass 19, count 0 2006.285.15:45:29.48#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:45:29.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:45:29.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.15:45:29.48#ibcon#*before write, iclass 19, count 0 2006.285.15:45:29.48#ibcon#enter sib2, iclass 19, count 0 2006.285.15:45:29.48#ibcon#flushed, iclass 19, count 0 2006.285.15:45:29.48#ibcon#about to write, iclass 19, count 0 2006.285.15:45:29.48#ibcon#wrote, iclass 19, count 0 2006.285.15:45:29.48#ibcon#about to read 3, iclass 19, count 0 2006.285.15:45:29.52#ibcon#read 3, iclass 19, count 0 2006.285.15:45:29.52#ibcon#about to read 4, iclass 19, count 0 2006.285.15:45:29.52#ibcon#read 4, iclass 19, count 0 2006.285.15:45:29.52#ibcon#about to read 5, iclass 19, count 0 2006.285.15:45:29.52#ibcon#read 5, iclass 19, count 0 2006.285.15:45:29.52#ibcon#about to read 6, iclass 19, count 0 2006.285.15:45:29.52#ibcon#read 6, iclass 19, count 0 2006.285.15:45:29.52#ibcon#end of sib2, iclass 19, count 0 2006.285.15:45:29.52#ibcon#*after write, iclass 19, count 0 2006.285.15:45:29.52#ibcon#*before return 0, iclass 19, count 0 2006.285.15:45:29.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:45:29.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:45:29.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:45:29.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:45:29.52$vck44/va=8,3 2006.285.15:45:29.52#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.15:45:29.52#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.15:45:29.52#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:29.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:45:29.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:45:29.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:45:29.58#ibcon#enter wrdev, iclass 21, count 2 2006.285.15:45:29.58#ibcon#first serial, iclass 21, count 2 2006.285.15:45:29.58#ibcon#enter sib2, iclass 21, count 2 2006.285.15:45:29.58#ibcon#flushed, iclass 21, count 2 2006.285.15:45:29.58#ibcon#about to write, iclass 21, count 2 2006.285.15:45:29.58#ibcon#wrote, iclass 21, count 2 2006.285.15:45:29.58#ibcon#about to read 3, iclass 21, count 2 2006.285.15:45:29.60#ibcon#read 3, iclass 21, count 2 2006.285.15:45:29.60#ibcon#about to read 4, iclass 21, count 2 2006.285.15:45:29.60#ibcon#read 4, iclass 21, count 2 2006.285.15:45:29.60#ibcon#about to read 5, iclass 21, count 2 2006.285.15:45:29.60#ibcon#read 5, iclass 21, count 2 2006.285.15:45:29.60#ibcon#about to read 6, iclass 21, count 2 2006.285.15:45:29.60#ibcon#read 6, iclass 21, count 2 2006.285.15:45:29.60#ibcon#end of sib2, iclass 21, count 2 2006.285.15:45:29.60#ibcon#*mode == 0, iclass 21, count 2 2006.285.15:45:29.60#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.15:45:29.60#ibcon#[25=AT08-03\r\n] 2006.285.15:45:29.60#ibcon#*before write, iclass 21, count 2 2006.285.15:45:29.60#ibcon#enter sib2, iclass 21, count 2 2006.285.15:45:29.60#ibcon#flushed, iclass 21, count 2 2006.285.15:45:29.60#ibcon#about to write, iclass 21, count 2 2006.285.15:45:29.60#ibcon#wrote, iclass 21, count 2 2006.285.15:45:29.60#ibcon#about to read 3, iclass 21, count 2 2006.285.15:45:29.63#ibcon#read 3, iclass 21, count 2 2006.285.15:45:29.63#ibcon#about to read 4, iclass 21, count 2 2006.285.15:45:29.63#ibcon#read 4, iclass 21, count 2 2006.285.15:45:29.63#ibcon#about to read 5, iclass 21, count 2 2006.285.15:45:29.63#ibcon#read 5, iclass 21, count 2 2006.285.15:45:29.63#ibcon#about to read 6, iclass 21, count 2 2006.285.15:45:29.63#ibcon#read 6, iclass 21, count 2 2006.285.15:45:29.63#ibcon#end of sib2, iclass 21, count 2 2006.285.15:45:29.63#ibcon#*after write, iclass 21, count 2 2006.285.15:45:29.63#ibcon#*before return 0, iclass 21, count 2 2006.285.15:45:29.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:45:29.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:45:29.63#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.15:45:29.63#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:29.63#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:45:29.75#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:45:29.75#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:45:29.75#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:45:29.75#ibcon#first serial, iclass 21, count 0 2006.285.15:45:29.75#ibcon#enter sib2, iclass 21, count 0 2006.285.15:45:29.75#ibcon#flushed, iclass 21, count 0 2006.285.15:45:29.75#ibcon#about to write, iclass 21, count 0 2006.285.15:45:29.75#ibcon#wrote, iclass 21, count 0 2006.285.15:45:29.75#ibcon#about to read 3, iclass 21, count 0 2006.285.15:45:29.77#ibcon#read 3, iclass 21, count 0 2006.285.15:45:29.77#ibcon#about to read 4, iclass 21, count 0 2006.285.15:45:29.77#ibcon#read 4, iclass 21, count 0 2006.285.15:45:29.77#ibcon#about to read 5, iclass 21, count 0 2006.285.15:45:29.77#ibcon#read 5, iclass 21, count 0 2006.285.15:45:29.77#ibcon#about to read 6, iclass 21, count 0 2006.285.15:45:29.77#ibcon#read 6, iclass 21, count 0 2006.285.15:45:29.77#ibcon#end of sib2, iclass 21, count 0 2006.285.15:45:29.77#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:45:29.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:45:29.77#ibcon#[25=USB\r\n] 2006.285.15:45:29.77#ibcon#*before write, iclass 21, count 0 2006.285.15:45:29.77#ibcon#enter sib2, iclass 21, count 0 2006.285.15:45:29.77#ibcon#flushed, iclass 21, count 0 2006.285.15:45:29.77#ibcon#about to write, iclass 21, count 0 2006.285.15:45:29.77#ibcon#wrote, iclass 21, count 0 2006.285.15:45:29.77#ibcon#about to read 3, iclass 21, count 0 2006.285.15:45:29.80#ibcon#read 3, iclass 21, count 0 2006.285.15:45:29.80#ibcon#about to read 4, iclass 21, count 0 2006.285.15:45:29.80#ibcon#read 4, iclass 21, count 0 2006.285.15:45:29.80#ibcon#about to read 5, iclass 21, count 0 2006.285.15:45:29.80#ibcon#read 5, iclass 21, count 0 2006.285.15:45:29.80#ibcon#about to read 6, iclass 21, count 0 2006.285.15:45:29.80#ibcon#read 6, iclass 21, count 0 2006.285.15:45:29.80#ibcon#end of sib2, iclass 21, count 0 2006.285.15:45:29.80#ibcon#*after write, iclass 21, count 0 2006.285.15:45:29.80#ibcon#*before return 0, iclass 21, count 0 2006.285.15:45:29.80#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:45:29.80#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:45:29.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:45:29.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:45:29.80$vck44/vblo=1,629.99 2006.285.15:45:29.80#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.15:45:29.80#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.15:45:29.80#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:29.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:45:29.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:45:29.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:45:29.80#ibcon#enter wrdev, iclass 23, count 0 2006.285.15:45:29.80#ibcon#first serial, iclass 23, count 0 2006.285.15:45:29.80#ibcon#enter sib2, iclass 23, count 0 2006.285.15:45:29.80#ibcon#flushed, iclass 23, count 0 2006.285.15:45:29.80#ibcon#about to write, iclass 23, count 0 2006.285.15:45:29.80#ibcon#wrote, iclass 23, count 0 2006.285.15:45:29.80#ibcon#about to read 3, iclass 23, count 0 2006.285.15:45:29.82#ibcon#read 3, iclass 23, count 0 2006.285.15:45:29.82#ibcon#about to read 4, iclass 23, count 0 2006.285.15:45:29.82#ibcon#read 4, iclass 23, count 0 2006.285.15:45:29.82#ibcon#about to read 5, iclass 23, count 0 2006.285.15:45:29.82#ibcon#read 5, iclass 23, count 0 2006.285.15:45:29.82#ibcon#about to read 6, iclass 23, count 0 2006.285.15:45:29.82#ibcon#read 6, iclass 23, count 0 2006.285.15:45:29.82#ibcon#end of sib2, iclass 23, count 0 2006.285.15:45:29.82#ibcon#*mode == 0, iclass 23, count 0 2006.285.15:45:29.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.15:45:29.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.15:45:29.82#ibcon#*before write, iclass 23, count 0 2006.285.15:45:29.82#ibcon#enter sib2, iclass 23, count 0 2006.285.15:45:29.82#ibcon#flushed, iclass 23, count 0 2006.285.15:45:29.82#ibcon#about to write, iclass 23, count 0 2006.285.15:45:29.82#ibcon#wrote, iclass 23, count 0 2006.285.15:45:29.82#ibcon#about to read 3, iclass 23, count 0 2006.285.15:45:29.86#ibcon#read 3, iclass 23, count 0 2006.285.15:45:29.86#ibcon#about to read 4, iclass 23, count 0 2006.285.15:45:29.86#ibcon#read 4, iclass 23, count 0 2006.285.15:45:29.86#ibcon#about to read 5, iclass 23, count 0 2006.285.15:45:29.86#ibcon#read 5, iclass 23, count 0 2006.285.15:45:29.86#ibcon#about to read 6, iclass 23, count 0 2006.285.15:45:29.86#ibcon#read 6, iclass 23, count 0 2006.285.15:45:29.86#ibcon#end of sib2, iclass 23, count 0 2006.285.15:45:29.86#ibcon#*after write, iclass 23, count 0 2006.285.15:45:29.86#ibcon#*before return 0, iclass 23, count 0 2006.285.15:45:29.86#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:45:29.86#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:45:29.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.15:45:29.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.15:45:29.86$vck44/vb=1,4 2006.285.15:45:29.86#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.15:45:29.86#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.15:45:29.86#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:29.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:45:29.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:45:29.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:45:29.86#ibcon#enter wrdev, iclass 25, count 2 2006.285.15:45:29.86#ibcon#first serial, iclass 25, count 2 2006.285.15:45:29.86#ibcon#enter sib2, iclass 25, count 2 2006.285.15:45:29.86#ibcon#flushed, iclass 25, count 2 2006.285.15:45:29.86#ibcon#about to write, iclass 25, count 2 2006.285.15:45:29.86#ibcon#wrote, iclass 25, count 2 2006.285.15:45:29.86#ibcon#about to read 3, iclass 25, count 2 2006.285.15:45:29.88#ibcon#read 3, iclass 25, count 2 2006.285.15:45:29.88#ibcon#about to read 4, iclass 25, count 2 2006.285.15:45:29.88#ibcon#read 4, iclass 25, count 2 2006.285.15:45:29.88#ibcon#about to read 5, iclass 25, count 2 2006.285.15:45:29.88#ibcon#read 5, iclass 25, count 2 2006.285.15:45:29.88#ibcon#about to read 6, iclass 25, count 2 2006.285.15:45:29.88#ibcon#read 6, iclass 25, count 2 2006.285.15:45:29.88#ibcon#end of sib2, iclass 25, count 2 2006.285.15:45:29.88#ibcon#*mode == 0, iclass 25, count 2 2006.285.15:45:29.88#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.15:45:29.88#ibcon#[27=AT01-04\r\n] 2006.285.15:45:29.88#ibcon#*before write, iclass 25, count 2 2006.285.15:45:29.88#ibcon#enter sib2, iclass 25, count 2 2006.285.15:45:29.88#ibcon#flushed, iclass 25, count 2 2006.285.15:45:29.88#ibcon#about to write, iclass 25, count 2 2006.285.15:45:29.88#ibcon#wrote, iclass 25, count 2 2006.285.15:45:29.88#ibcon#about to read 3, iclass 25, count 2 2006.285.15:45:29.91#ibcon#read 3, iclass 25, count 2 2006.285.15:45:29.91#ibcon#about to read 4, iclass 25, count 2 2006.285.15:45:29.91#ibcon#read 4, iclass 25, count 2 2006.285.15:45:29.91#ibcon#about to read 5, iclass 25, count 2 2006.285.15:45:29.91#ibcon#read 5, iclass 25, count 2 2006.285.15:45:29.91#ibcon#about to read 6, iclass 25, count 2 2006.285.15:45:29.91#ibcon#read 6, iclass 25, count 2 2006.285.15:45:29.91#ibcon#end of sib2, iclass 25, count 2 2006.285.15:45:29.91#ibcon#*after write, iclass 25, count 2 2006.285.15:45:29.91#ibcon#*before return 0, iclass 25, count 2 2006.285.15:45:29.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:45:29.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.15:45:29.91#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.15:45:29.91#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:29.91#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:45:30.03#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:45:30.03#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:45:30.03#ibcon#enter wrdev, iclass 25, count 0 2006.285.15:45:30.03#ibcon#first serial, iclass 25, count 0 2006.285.15:45:30.03#ibcon#enter sib2, iclass 25, count 0 2006.285.15:45:30.03#ibcon#flushed, iclass 25, count 0 2006.285.15:45:30.03#ibcon#about to write, iclass 25, count 0 2006.285.15:45:30.03#ibcon#wrote, iclass 25, count 0 2006.285.15:45:30.03#ibcon#about to read 3, iclass 25, count 0 2006.285.15:45:30.05#ibcon#read 3, iclass 25, count 0 2006.285.15:45:30.05#ibcon#about to read 4, iclass 25, count 0 2006.285.15:45:30.05#ibcon#read 4, iclass 25, count 0 2006.285.15:45:30.05#ibcon#about to read 5, iclass 25, count 0 2006.285.15:45:30.05#ibcon#read 5, iclass 25, count 0 2006.285.15:45:30.05#ibcon#about to read 6, iclass 25, count 0 2006.285.15:45:30.05#ibcon#read 6, iclass 25, count 0 2006.285.15:45:30.05#ibcon#end of sib2, iclass 25, count 0 2006.285.15:45:30.05#ibcon#*mode == 0, iclass 25, count 0 2006.285.15:45:30.05#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.15:45:30.05#ibcon#[27=USB\r\n] 2006.285.15:45:30.05#ibcon#*before write, iclass 25, count 0 2006.285.15:45:30.05#ibcon#enter sib2, iclass 25, count 0 2006.285.15:45:30.05#ibcon#flushed, iclass 25, count 0 2006.285.15:45:30.05#ibcon#about to write, iclass 25, count 0 2006.285.15:45:30.05#ibcon#wrote, iclass 25, count 0 2006.285.15:45:30.05#ibcon#about to read 3, iclass 25, count 0 2006.285.15:45:30.08#ibcon#read 3, iclass 25, count 0 2006.285.15:45:30.08#ibcon#about to read 4, iclass 25, count 0 2006.285.15:45:30.08#ibcon#read 4, iclass 25, count 0 2006.285.15:45:30.08#ibcon#about to read 5, iclass 25, count 0 2006.285.15:45:30.08#ibcon#read 5, iclass 25, count 0 2006.285.15:45:30.08#ibcon#about to read 6, iclass 25, count 0 2006.285.15:45:30.08#ibcon#read 6, iclass 25, count 0 2006.285.15:45:30.08#ibcon#end of sib2, iclass 25, count 0 2006.285.15:45:30.08#ibcon#*after write, iclass 25, count 0 2006.285.15:45:30.08#ibcon#*before return 0, iclass 25, count 0 2006.285.15:45:30.08#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:45:30.08#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.15:45:30.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.15:45:30.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.15:45:30.08$vck44/vblo=2,634.99 2006.285.15:45:30.08#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.15:45:30.08#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.15:45:30.08#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:30.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:45:30.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:45:30.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:45:30.08#ibcon#enter wrdev, iclass 27, count 0 2006.285.15:45:30.08#ibcon#first serial, iclass 27, count 0 2006.285.15:45:30.08#ibcon#enter sib2, iclass 27, count 0 2006.285.15:45:30.08#ibcon#flushed, iclass 27, count 0 2006.285.15:45:30.08#ibcon#about to write, iclass 27, count 0 2006.285.15:45:30.08#ibcon#wrote, iclass 27, count 0 2006.285.15:45:30.08#ibcon#about to read 3, iclass 27, count 0 2006.285.15:45:30.10#ibcon#read 3, iclass 27, count 0 2006.285.15:45:30.10#ibcon#about to read 4, iclass 27, count 0 2006.285.15:45:30.10#ibcon#read 4, iclass 27, count 0 2006.285.15:45:30.10#ibcon#about to read 5, iclass 27, count 0 2006.285.15:45:30.10#ibcon#read 5, iclass 27, count 0 2006.285.15:45:30.10#ibcon#about to read 6, iclass 27, count 0 2006.285.15:45:30.10#ibcon#read 6, iclass 27, count 0 2006.285.15:45:30.10#ibcon#end of sib2, iclass 27, count 0 2006.285.15:45:30.10#ibcon#*mode == 0, iclass 27, count 0 2006.285.15:45:30.10#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.15:45:30.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.15:45:30.10#ibcon#*before write, iclass 27, count 0 2006.285.15:45:30.10#ibcon#enter sib2, iclass 27, count 0 2006.285.15:45:30.10#ibcon#flushed, iclass 27, count 0 2006.285.15:45:30.10#ibcon#about to write, iclass 27, count 0 2006.285.15:45:30.10#ibcon#wrote, iclass 27, count 0 2006.285.15:45:30.10#ibcon#about to read 3, iclass 27, count 0 2006.285.15:45:30.14#ibcon#read 3, iclass 27, count 0 2006.285.15:45:30.14#ibcon#about to read 4, iclass 27, count 0 2006.285.15:45:30.14#ibcon#read 4, iclass 27, count 0 2006.285.15:45:30.14#ibcon#about to read 5, iclass 27, count 0 2006.285.15:45:30.14#ibcon#read 5, iclass 27, count 0 2006.285.15:45:30.14#ibcon#about to read 6, iclass 27, count 0 2006.285.15:45:30.14#ibcon#read 6, iclass 27, count 0 2006.285.15:45:30.14#ibcon#end of sib2, iclass 27, count 0 2006.285.15:45:30.14#ibcon#*after write, iclass 27, count 0 2006.285.15:45:30.14#ibcon#*before return 0, iclass 27, count 0 2006.285.15:45:30.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:45:30.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.15:45:30.14#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.15:45:30.14#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.15:45:30.14$vck44/vb=2,5 2006.285.15:45:30.14#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.15:45:30.14#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.15:45:30.14#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:30.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:45:30.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:45:30.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:45:30.20#ibcon#enter wrdev, iclass 29, count 2 2006.285.15:45:30.20#ibcon#first serial, iclass 29, count 2 2006.285.15:45:30.20#ibcon#enter sib2, iclass 29, count 2 2006.285.15:45:30.20#ibcon#flushed, iclass 29, count 2 2006.285.15:45:30.20#ibcon#about to write, iclass 29, count 2 2006.285.15:45:30.20#ibcon#wrote, iclass 29, count 2 2006.285.15:45:30.20#ibcon#about to read 3, iclass 29, count 2 2006.285.15:45:30.22#ibcon#read 3, iclass 29, count 2 2006.285.15:45:30.22#ibcon#about to read 4, iclass 29, count 2 2006.285.15:45:30.22#ibcon#read 4, iclass 29, count 2 2006.285.15:45:30.22#ibcon#about to read 5, iclass 29, count 2 2006.285.15:45:30.22#ibcon#read 5, iclass 29, count 2 2006.285.15:45:30.22#ibcon#about to read 6, iclass 29, count 2 2006.285.15:45:30.22#ibcon#read 6, iclass 29, count 2 2006.285.15:45:30.22#ibcon#end of sib2, iclass 29, count 2 2006.285.15:45:30.22#ibcon#*mode == 0, iclass 29, count 2 2006.285.15:45:30.22#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.15:45:30.22#ibcon#[27=AT02-05\r\n] 2006.285.15:45:30.22#ibcon#*before write, iclass 29, count 2 2006.285.15:45:30.22#ibcon#enter sib2, iclass 29, count 2 2006.285.15:45:30.22#ibcon#flushed, iclass 29, count 2 2006.285.15:45:30.22#ibcon#about to write, iclass 29, count 2 2006.285.15:45:30.22#ibcon#wrote, iclass 29, count 2 2006.285.15:45:30.22#ibcon#about to read 3, iclass 29, count 2 2006.285.15:45:30.25#ibcon#read 3, iclass 29, count 2 2006.285.15:45:30.25#ibcon#about to read 4, iclass 29, count 2 2006.285.15:45:30.25#ibcon#read 4, iclass 29, count 2 2006.285.15:45:30.25#ibcon#about to read 5, iclass 29, count 2 2006.285.15:45:30.25#ibcon#read 5, iclass 29, count 2 2006.285.15:45:30.25#ibcon#about to read 6, iclass 29, count 2 2006.285.15:45:30.25#ibcon#read 6, iclass 29, count 2 2006.285.15:45:30.25#ibcon#end of sib2, iclass 29, count 2 2006.285.15:45:30.25#ibcon#*after write, iclass 29, count 2 2006.285.15:45:30.25#ibcon#*before return 0, iclass 29, count 2 2006.285.15:45:30.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:45:30.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.15:45:30.25#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.15:45:30.25#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:30.25#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:45:30.37#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:45:30.37#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:45:30.37#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:45:30.37#ibcon#first serial, iclass 29, count 0 2006.285.15:45:30.37#ibcon#enter sib2, iclass 29, count 0 2006.285.15:45:30.37#ibcon#flushed, iclass 29, count 0 2006.285.15:45:30.37#ibcon#about to write, iclass 29, count 0 2006.285.15:45:30.37#ibcon#wrote, iclass 29, count 0 2006.285.15:45:30.37#ibcon#about to read 3, iclass 29, count 0 2006.285.15:45:30.39#ibcon#read 3, iclass 29, count 0 2006.285.15:45:30.39#ibcon#about to read 4, iclass 29, count 0 2006.285.15:45:30.39#ibcon#read 4, iclass 29, count 0 2006.285.15:45:30.39#ibcon#about to read 5, iclass 29, count 0 2006.285.15:45:30.39#ibcon#read 5, iclass 29, count 0 2006.285.15:45:30.39#ibcon#about to read 6, iclass 29, count 0 2006.285.15:45:30.39#ibcon#read 6, iclass 29, count 0 2006.285.15:45:30.39#ibcon#end of sib2, iclass 29, count 0 2006.285.15:45:30.39#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:45:30.39#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:45:30.39#ibcon#[27=USB\r\n] 2006.285.15:45:30.39#ibcon#*before write, iclass 29, count 0 2006.285.15:45:30.39#ibcon#enter sib2, iclass 29, count 0 2006.285.15:45:30.39#ibcon#flushed, iclass 29, count 0 2006.285.15:45:30.39#ibcon#about to write, iclass 29, count 0 2006.285.15:45:30.39#ibcon#wrote, iclass 29, count 0 2006.285.15:45:30.39#ibcon#about to read 3, iclass 29, count 0 2006.285.15:45:30.42#ibcon#read 3, iclass 29, count 0 2006.285.15:45:30.42#ibcon#about to read 4, iclass 29, count 0 2006.285.15:45:30.42#ibcon#read 4, iclass 29, count 0 2006.285.15:45:30.42#ibcon#about to read 5, iclass 29, count 0 2006.285.15:45:30.42#ibcon#read 5, iclass 29, count 0 2006.285.15:45:30.42#ibcon#about to read 6, iclass 29, count 0 2006.285.15:45:30.42#ibcon#read 6, iclass 29, count 0 2006.285.15:45:30.42#ibcon#end of sib2, iclass 29, count 0 2006.285.15:45:30.42#ibcon#*after write, iclass 29, count 0 2006.285.15:45:30.42#ibcon#*before return 0, iclass 29, count 0 2006.285.15:45:30.42#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:45:30.42#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.15:45:30.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:45:30.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:45:30.42$vck44/vblo=3,649.99 2006.285.15:45:30.42#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.15:45:30.42#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.15:45:30.42#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:30.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:45:30.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:45:30.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:45:30.42#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:45:30.42#ibcon#first serial, iclass 31, count 0 2006.285.15:45:30.42#ibcon#enter sib2, iclass 31, count 0 2006.285.15:45:30.42#ibcon#flushed, iclass 31, count 0 2006.285.15:45:30.42#ibcon#about to write, iclass 31, count 0 2006.285.15:45:30.42#ibcon#wrote, iclass 31, count 0 2006.285.15:45:30.42#ibcon#about to read 3, iclass 31, count 0 2006.285.15:45:30.44#ibcon#read 3, iclass 31, count 0 2006.285.15:45:30.44#ibcon#about to read 4, iclass 31, count 0 2006.285.15:45:30.44#ibcon#read 4, iclass 31, count 0 2006.285.15:45:30.44#ibcon#about to read 5, iclass 31, count 0 2006.285.15:45:30.44#ibcon#read 5, iclass 31, count 0 2006.285.15:45:30.44#ibcon#about to read 6, iclass 31, count 0 2006.285.15:45:30.44#ibcon#read 6, iclass 31, count 0 2006.285.15:45:30.44#ibcon#end of sib2, iclass 31, count 0 2006.285.15:45:30.44#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:45:30.44#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:45:30.44#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.15:45:30.44#ibcon#*before write, iclass 31, count 0 2006.285.15:45:30.44#ibcon#enter sib2, iclass 31, count 0 2006.285.15:45:30.44#ibcon#flushed, iclass 31, count 0 2006.285.15:45:30.44#ibcon#about to write, iclass 31, count 0 2006.285.15:45:30.44#ibcon#wrote, iclass 31, count 0 2006.285.15:45:30.44#ibcon#about to read 3, iclass 31, count 0 2006.285.15:45:30.48#ibcon#read 3, iclass 31, count 0 2006.285.15:45:30.48#ibcon#about to read 4, iclass 31, count 0 2006.285.15:45:30.48#ibcon#read 4, iclass 31, count 0 2006.285.15:45:30.48#ibcon#about to read 5, iclass 31, count 0 2006.285.15:45:30.48#ibcon#read 5, iclass 31, count 0 2006.285.15:45:30.48#ibcon#about to read 6, iclass 31, count 0 2006.285.15:45:30.48#ibcon#read 6, iclass 31, count 0 2006.285.15:45:30.48#ibcon#end of sib2, iclass 31, count 0 2006.285.15:45:30.48#ibcon#*after write, iclass 31, count 0 2006.285.15:45:30.48#ibcon#*before return 0, iclass 31, count 0 2006.285.15:45:30.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:45:30.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.15:45:30.48#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:45:30.48#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:45:30.48$vck44/vb=3,4 2006.285.15:45:30.48#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.15:45:30.48#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.15:45:30.48#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:30.48#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:45:30.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:45:30.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:45:30.54#ibcon#enter wrdev, iclass 33, count 2 2006.285.15:45:30.54#ibcon#first serial, iclass 33, count 2 2006.285.15:45:30.54#ibcon#enter sib2, iclass 33, count 2 2006.285.15:45:30.54#ibcon#flushed, iclass 33, count 2 2006.285.15:45:30.54#ibcon#about to write, iclass 33, count 2 2006.285.15:45:30.54#ibcon#wrote, iclass 33, count 2 2006.285.15:45:30.54#ibcon#about to read 3, iclass 33, count 2 2006.285.15:45:30.56#ibcon#read 3, iclass 33, count 2 2006.285.15:45:30.56#ibcon#about to read 4, iclass 33, count 2 2006.285.15:45:30.56#ibcon#read 4, iclass 33, count 2 2006.285.15:45:30.56#ibcon#about to read 5, iclass 33, count 2 2006.285.15:45:30.56#ibcon#read 5, iclass 33, count 2 2006.285.15:45:30.56#ibcon#about to read 6, iclass 33, count 2 2006.285.15:45:30.56#ibcon#read 6, iclass 33, count 2 2006.285.15:45:30.56#ibcon#end of sib2, iclass 33, count 2 2006.285.15:45:30.56#ibcon#*mode == 0, iclass 33, count 2 2006.285.15:45:30.56#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.15:45:30.56#ibcon#[27=AT03-04\r\n] 2006.285.15:45:30.56#ibcon#*before write, iclass 33, count 2 2006.285.15:45:30.56#ibcon#enter sib2, iclass 33, count 2 2006.285.15:45:30.56#ibcon#flushed, iclass 33, count 2 2006.285.15:45:30.56#ibcon#about to write, iclass 33, count 2 2006.285.15:45:30.56#ibcon#wrote, iclass 33, count 2 2006.285.15:45:30.56#ibcon#about to read 3, iclass 33, count 2 2006.285.15:45:30.59#ibcon#read 3, iclass 33, count 2 2006.285.15:45:30.59#ibcon#about to read 4, iclass 33, count 2 2006.285.15:45:30.59#ibcon#read 4, iclass 33, count 2 2006.285.15:45:30.59#ibcon#about to read 5, iclass 33, count 2 2006.285.15:45:30.59#ibcon#read 5, iclass 33, count 2 2006.285.15:45:30.59#ibcon#about to read 6, iclass 33, count 2 2006.285.15:45:30.59#ibcon#read 6, iclass 33, count 2 2006.285.15:45:30.59#ibcon#end of sib2, iclass 33, count 2 2006.285.15:45:30.59#ibcon#*after write, iclass 33, count 2 2006.285.15:45:30.59#ibcon#*before return 0, iclass 33, count 2 2006.285.15:45:30.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:45:30.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.15:45:30.59#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.15:45:30.59#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:30.59#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:45:30.71#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:45:30.71#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:45:30.71#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:45:30.71#ibcon#first serial, iclass 33, count 0 2006.285.15:45:30.71#ibcon#enter sib2, iclass 33, count 0 2006.285.15:45:30.71#ibcon#flushed, iclass 33, count 0 2006.285.15:45:30.71#ibcon#about to write, iclass 33, count 0 2006.285.15:45:30.71#ibcon#wrote, iclass 33, count 0 2006.285.15:45:30.71#ibcon#about to read 3, iclass 33, count 0 2006.285.15:45:30.73#ibcon#read 3, iclass 33, count 0 2006.285.15:45:30.73#ibcon#about to read 4, iclass 33, count 0 2006.285.15:45:30.73#ibcon#read 4, iclass 33, count 0 2006.285.15:45:30.73#ibcon#about to read 5, iclass 33, count 0 2006.285.15:45:30.73#ibcon#read 5, iclass 33, count 0 2006.285.15:45:30.73#ibcon#about to read 6, iclass 33, count 0 2006.285.15:45:30.86#ibcon#read 6, iclass 33, count 0 2006.285.15:45:30.86#ibcon#end of sib2, iclass 33, count 0 2006.285.15:45:30.86#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:45:30.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:45:30.86#ibcon#[27=USB\r\n] 2006.285.15:45:30.86#ibcon#*before write, iclass 33, count 0 2006.285.15:45:30.86#ibcon#enter sib2, iclass 33, count 0 2006.285.15:45:30.86#ibcon#flushed, iclass 33, count 0 2006.285.15:45:30.86#ibcon#about to write, iclass 33, count 0 2006.285.15:45:30.86#ibcon#wrote, iclass 33, count 0 2006.285.15:45:30.86#ibcon#about to read 3, iclass 33, count 0 2006.285.15:45:30.89#ibcon#read 3, iclass 33, count 0 2006.285.15:45:30.89#ibcon#about to read 4, iclass 33, count 0 2006.285.15:45:30.89#ibcon#read 4, iclass 33, count 0 2006.285.15:45:30.89#ibcon#about to read 5, iclass 33, count 0 2006.285.15:45:30.89#ibcon#read 5, iclass 33, count 0 2006.285.15:45:30.89#ibcon#about to read 6, iclass 33, count 0 2006.285.15:45:30.89#ibcon#read 6, iclass 33, count 0 2006.285.15:45:30.89#ibcon#end of sib2, iclass 33, count 0 2006.285.15:45:30.89#ibcon#*after write, iclass 33, count 0 2006.285.15:45:30.89#ibcon#*before return 0, iclass 33, count 0 2006.285.15:45:30.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:45:30.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.15:45:30.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:45:30.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:45:30.89$vck44/vblo=4,679.99 2006.285.15:45:30.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.15:45:30.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.15:45:30.89#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:30.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:45:30.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:45:30.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:45:30.89#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:45:30.89#ibcon#first serial, iclass 35, count 0 2006.285.15:45:30.89#ibcon#enter sib2, iclass 35, count 0 2006.285.15:45:30.89#ibcon#flushed, iclass 35, count 0 2006.285.15:45:30.89#ibcon#about to write, iclass 35, count 0 2006.285.15:45:30.89#ibcon#wrote, iclass 35, count 0 2006.285.15:45:30.89#ibcon#about to read 3, iclass 35, count 0 2006.285.15:45:30.91#ibcon#read 3, iclass 35, count 0 2006.285.15:45:30.91#ibcon#about to read 4, iclass 35, count 0 2006.285.15:45:30.91#ibcon#read 4, iclass 35, count 0 2006.285.15:45:30.91#ibcon#about to read 5, iclass 35, count 0 2006.285.15:45:30.91#ibcon#read 5, iclass 35, count 0 2006.285.15:45:30.91#ibcon#about to read 6, iclass 35, count 0 2006.285.15:45:30.91#ibcon#read 6, iclass 35, count 0 2006.285.15:45:30.91#ibcon#end of sib2, iclass 35, count 0 2006.285.15:45:30.91#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:45:30.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:45:30.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.15:45:30.91#ibcon#*before write, iclass 35, count 0 2006.285.15:45:30.91#ibcon#enter sib2, iclass 35, count 0 2006.285.15:45:30.91#ibcon#flushed, iclass 35, count 0 2006.285.15:45:30.91#ibcon#about to write, iclass 35, count 0 2006.285.15:45:30.91#ibcon#wrote, iclass 35, count 0 2006.285.15:45:30.91#ibcon#about to read 3, iclass 35, count 0 2006.285.15:45:30.95#ibcon#read 3, iclass 35, count 0 2006.285.15:45:30.95#ibcon#about to read 4, iclass 35, count 0 2006.285.15:45:30.95#ibcon#read 4, iclass 35, count 0 2006.285.15:45:30.95#ibcon#about to read 5, iclass 35, count 0 2006.285.15:45:30.95#ibcon#read 5, iclass 35, count 0 2006.285.15:45:30.95#ibcon#about to read 6, iclass 35, count 0 2006.285.15:45:30.95#ibcon#read 6, iclass 35, count 0 2006.285.15:45:30.95#ibcon#end of sib2, iclass 35, count 0 2006.285.15:45:30.95#ibcon#*after write, iclass 35, count 0 2006.285.15:45:30.95#ibcon#*before return 0, iclass 35, count 0 2006.285.15:45:30.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:45:30.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.15:45:30.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:45:30.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:45:30.95$vck44/vb=4,5 2006.285.15:45:30.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.15:45:30.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.15:45:30.95#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:30.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:45:31.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:45:31.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:45:31.01#ibcon#enter wrdev, iclass 37, count 2 2006.285.15:45:31.01#ibcon#first serial, iclass 37, count 2 2006.285.15:45:31.01#ibcon#enter sib2, iclass 37, count 2 2006.285.15:45:31.01#ibcon#flushed, iclass 37, count 2 2006.285.15:45:31.01#ibcon#about to write, iclass 37, count 2 2006.285.15:45:31.01#ibcon#wrote, iclass 37, count 2 2006.285.15:45:31.01#ibcon#about to read 3, iclass 37, count 2 2006.285.15:45:31.03#ibcon#read 3, iclass 37, count 2 2006.285.15:45:31.03#ibcon#about to read 4, iclass 37, count 2 2006.285.15:45:31.03#ibcon#read 4, iclass 37, count 2 2006.285.15:45:31.03#ibcon#about to read 5, iclass 37, count 2 2006.285.15:45:31.03#ibcon#read 5, iclass 37, count 2 2006.285.15:45:31.03#ibcon#about to read 6, iclass 37, count 2 2006.285.15:45:31.03#ibcon#read 6, iclass 37, count 2 2006.285.15:45:31.03#ibcon#end of sib2, iclass 37, count 2 2006.285.15:45:31.03#ibcon#*mode == 0, iclass 37, count 2 2006.285.15:45:31.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.15:45:31.03#ibcon#[27=AT04-05\r\n] 2006.285.15:45:31.03#ibcon#*before write, iclass 37, count 2 2006.285.15:45:31.03#ibcon#enter sib2, iclass 37, count 2 2006.285.15:45:31.03#ibcon#flushed, iclass 37, count 2 2006.285.15:45:31.03#ibcon#about to write, iclass 37, count 2 2006.285.15:45:31.03#ibcon#wrote, iclass 37, count 2 2006.285.15:45:31.03#ibcon#about to read 3, iclass 37, count 2 2006.285.15:45:31.06#ibcon#read 3, iclass 37, count 2 2006.285.15:45:31.06#ibcon#about to read 4, iclass 37, count 2 2006.285.15:45:31.06#ibcon#read 4, iclass 37, count 2 2006.285.15:45:31.06#ibcon#about to read 5, iclass 37, count 2 2006.285.15:45:31.06#ibcon#read 5, iclass 37, count 2 2006.285.15:45:31.06#ibcon#about to read 6, iclass 37, count 2 2006.285.15:45:31.06#ibcon#read 6, iclass 37, count 2 2006.285.15:45:31.06#ibcon#end of sib2, iclass 37, count 2 2006.285.15:45:31.06#ibcon#*after write, iclass 37, count 2 2006.285.15:45:31.06#ibcon#*before return 0, iclass 37, count 2 2006.285.15:45:31.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:45:31.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.15:45:31.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.15:45:31.06#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:31.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:45:31.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:45:31.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:45:31.18#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:45:31.18#ibcon#first serial, iclass 37, count 0 2006.285.15:45:31.18#ibcon#enter sib2, iclass 37, count 0 2006.285.15:45:31.18#ibcon#flushed, iclass 37, count 0 2006.285.15:45:31.18#ibcon#about to write, iclass 37, count 0 2006.285.15:45:31.18#ibcon#wrote, iclass 37, count 0 2006.285.15:45:31.18#ibcon#about to read 3, iclass 37, count 0 2006.285.15:45:31.20#ibcon#read 3, iclass 37, count 0 2006.285.15:45:31.20#ibcon#about to read 4, iclass 37, count 0 2006.285.15:45:31.20#ibcon#read 4, iclass 37, count 0 2006.285.15:45:31.20#ibcon#about to read 5, iclass 37, count 0 2006.285.15:45:31.20#ibcon#read 5, iclass 37, count 0 2006.285.15:45:31.20#ibcon#about to read 6, iclass 37, count 0 2006.285.15:45:31.20#ibcon#read 6, iclass 37, count 0 2006.285.15:45:31.20#ibcon#end of sib2, iclass 37, count 0 2006.285.15:45:31.20#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:45:31.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:45:31.20#ibcon#[27=USB\r\n] 2006.285.15:45:31.20#ibcon#*before write, iclass 37, count 0 2006.285.15:45:31.20#ibcon#enter sib2, iclass 37, count 0 2006.285.15:45:31.20#ibcon#flushed, iclass 37, count 0 2006.285.15:45:31.20#ibcon#about to write, iclass 37, count 0 2006.285.15:45:31.20#ibcon#wrote, iclass 37, count 0 2006.285.15:45:31.20#ibcon#about to read 3, iclass 37, count 0 2006.285.15:45:31.23#ibcon#read 3, iclass 37, count 0 2006.285.15:45:31.23#ibcon#about to read 4, iclass 37, count 0 2006.285.15:45:31.23#ibcon#read 4, iclass 37, count 0 2006.285.15:45:31.23#ibcon#about to read 5, iclass 37, count 0 2006.285.15:45:31.23#ibcon#read 5, iclass 37, count 0 2006.285.15:45:31.23#ibcon#about to read 6, iclass 37, count 0 2006.285.15:45:31.23#ibcon#read 6, iclass 37, count 0 2006.285.15:45:31.23#ibcon#end of sib2, iclass 37, count 0 2006.285.15:45:31.23#ibcon#*after write, iclass 37, count 0 2006.285.15:45:31.23#ibcon#*before return 0, iclass 37, count 0 2006.285.15:45:31.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:45:31.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.15:45:31.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:45:31.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:45:31.23$vck44/vblo=5,709.99 2006.285.15:45:31.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.15:45:31.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.15:45:31.23#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:31.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:45:31.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:45:31.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:45:31.23#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:45:31.23#ibcon#first serial, iclass 39, count 0 2006.285.15:45:31.23#ibcon#enter sib2, iclass 39, count 0 2006.285.15:45:31.23#ibcon#flushed, iclass 39, count 0 2006.285.15:45:31.23#ibcon#about to write, iclass 39, count 0 2006.285.15:45:31.23#ibcon#wrote, iclass 39, count 0 2006.285.15:45:31.23#ibcon#about to read 3, iclass 39, count 0 2006.285.15:45:31.25#ibcon#read 3, iclass 39, count 0 2006.285.15:45:31.25#ibcon#about to read 4, iclass 39, count 0 2006.285.15:45:31.25#ibcon#read 4, iclass 39, count 0 2006.285.15:45:31.25#ibcon#about to read 5, iclass 39, count 0 2006.285.15:45:31.25#ibcon#read 5, iclass 39, count 0 2006.285.15:45:31.25#ibcon#about to read 6, iclass 39, count 0 2006.285.15:45:31.25#ibcon#read 6, iclass 39, count 0 2006.285.15:45:31.25#ibcon#end of sib2, iclass 39, count 0 2006.285.15:45:31.25#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:45:31.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:45:31.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.15:45:31.25#ibcon#*before write, iclass 39, count 0 2006.285.15:45:31.25#ibcon#enter sib2, iclass 39, count 0 2006.285.15:45:31.25#ibcon#flushed, iclass 39, count 0 2006.285.15:45:31.25#ibcon#about to write, iclass 39, count 0 2006.285.15:45:31.25#ibcon#wrote, iclass 39, count 0 2006.285.15:45:31.25#ibcon#about to read 3, iclass 39, count 0 2006.285.15:45:31.29#ibcon#read 3, iclass 39, count 0 2006.285.15:45:31.29#ibcon#about to read 4, iclass 39, count 0 2006.285.15:45:31.29#ibcon#read 4, iclass 39, count 0 2006.285.15:45:31.29#ibcon#about to read 5, iclass 39, count 0 2006.285.15:45:31.29#ibcon#read 5, iclass 39, count 0 2006.285.15:45:31.29#ibcon#about to read 6, iclass 39, count 0 2006.285.15:45:31.29#ibcon#read 6, iclass 39, count 0 2006.285.15:45:31.29#ibcon#end of sib2, iclass 39, count 0 2006.285.15:45:31.29#ibcon#*after write, iclass 39, count 0 2006.285.15:45:31.29#ibcon#*before return 0, iclass 39, count 0 2006.285.15:45:31.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:45:31.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.15:45:31.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:45:31.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:45:31.29$vck44/vb=5,4 2006.285.15:45:31.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.15:45:31.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.15:45:31.29#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:31.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:45:31.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:45:31.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:45:31.35#ibcon#enter wrdev, iclass 3, count 2 2006.285.15:45:31.35#ibcon#first serial, iclass 3, count 2 2006.285.15:45:31.35#ibcon#enter sib2, iclass 3, count 2 2006.285.15:45:31.35#ibcon#flushed, iclass 3, count 2 2006.285.15:45:31.35#ibcon#about to write, iclass 3, count 2 2006.285.15:45:31.35#ibcon#wrote, iclass 3, count 2 2006.285.15:45:31.35#ibcon#about to read 3, iclass 3, count 2 2006.285.15:45:31.37#ibcon#read 3, iclass 3, count 2 2006.285.15:45:31.37#ibcon#about to read 4, iclass 3, count 2 2006.285.15:45:31.37#ibcon#read 4, iclass 3, count 2 2006.285.15:45:31.37#ibcon#about to read 5, iclass 3, count 2 2006.285.15:45:31.37#ibcon#read 5, iclass 3, count 2 2006.285.15:45:31.37#ibcon#about to read 6, iclass 3, count 2 2006.285.15:45:31.37#ibcon#read 6, iclass 3, count 2 2006.285.15:45:31.37#ibcon#end of sib2, iclass 3, count 2 2006.285.15:45:31.37#ibcon#*mode == 0, iclass 3, count 2 2006.285.15:45:31.37#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.15:45:31.37#ibcon#[27=AT05-04\r\n] 2006.285.15:45:31.37#ibcon#*before write, iclass 3, count 2 2006.285.15:45:31.37#ibcon#enter sib2, iclass 3, count 2 2006.285.15:45:31.37#ibcon#flushed, iclass 3, count 2 2006.285.15:45:31.37#ibcon#about to write, iclass 3, count 2 2006.285.15:45:31.37#ibcon#wrote, iclass 3, count 2 2006.285.15:45:31.37#ibcon#about to read 3, iclass 3, count 2 2006.285.15:45:31.40#ibcon#read 3, iclass 3, count 2 2006.285.15:45:31.40#ibcon#about to read 4, iclass 3, count 2 2006.285.15:45:31.40#ibcon#read 4, iclass 3, count 2 2006.285.15:45:31.40#ibcon#about to read 5, iclass 3, count 2 2006.285.15:45:31.40#ibcon#read 5, iclass 3, count 2 2006.285.15:45:31.40#ibcon#about to read 6, iclass 3, count 2 2006.285.15:45:31.40#ibcon#read 6, iclass 3, count 2 2006.285.15:45:31.40#ibcon#end of sib2, iclass 3, count 2 2006.285.15:45:31.40#ibcon#*after write, iclass 3, count 2 2006.285.15:45:31.40#ibcon#*before return 0, iclass 3, count 2 2006.285.15:45:31.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:45:31.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.15:45:31.40#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.15:45:31.40#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:31.40#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:45:31.52#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:45:31.52#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:45:31.52#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:45:31.52#ibcon#first serial, iclass 3, count 0 2006.285.15:45:31.52#ibcon#enter sib2, iclass 3, count 0 2006.285.15:45:31.52#ibcon#flushed, iclass 3, count 0 2006.285.15:45:31.52#ibcon#about to write, iclass 3, count 0 2006.285.15:45:31.52#ibcon#wrote, iclass 3, count 0 2006.285.15:45:31.52#ibcon#about to read 3, iclass 3, count 0 2006.285.15:45:31.54#ibcon#read 3, iclass 3, count 0 2006.285.15:45:31.54#ibcon#about to read 4, iclass 3, count 0 2006.285.15:45:31.54#ibcon#read 4, iclass 3, count 0 2006.285.15:45:31.54#ibcon#about to read 5, iclass 3, count 0 2006.285.15:45:31.54#ibcon#read 5, iclass 3, count 0 2006.285.15:45:31.54#ibcon#about to read 6, iclass 3, count 0 2006.285.15:45:31.54#ibcon#read 6, iclass 3, count 0 2006.285.15:45:31.54#ibcon#end of sib2, iclass 3, count 0 2006.285.15:45:31.54#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:45:31.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:45:31.54#ibcon#[27=USB\r\n] 2006.285.15:45:31.54#ibcon#*before write, iclass 3, count 0 2006.285.15:45:31.54#ibcon#enter sib2, iclass 3, count 0 2006.285.15:45:31.54#ibcon#flushed, iclass 3, count 0 2006.285.15:45:31.54#ibcon#about to write, iclass 3, count 0 2006.285.15:45:31.54#ibcon#wrote, iclass 3, count 0 2006.285.15:45:31.54#ibcon#about to read 3, iclass 3, count 0 2006.285.15:45:31.57#ibcon#read 3, iclass 3, count 0 2006.285.15:45:31.57#ibcon#about to read 4, iclass 3, count 0 2006.285.15:45:31.57#ibcon#read 4, iclass 3, count 0 2006.285.15:45:31.57#ibcon#about to read 5, iclass 3, count 0 2006.285.15:45:31.57#ibcon#read 5, iclass 3, count 0 2006.285.15:45:31.57#ibcon#about to read 6, iclass 3, count 0 2006.285.15:45:31.57#ibcon#read 6, iclass 3, count 0 2006.285.15:45:31.57#ibcon#end of sib2, iclass 3, count 0 2006.285.15:45:31.57#ibcon#*after write, iclass 3, count 0 2006.285.15:45:31.57#ibcon#*before return 0, iclass 3, count 0 2006.285.15:45:31.57#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:45:31.57#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.15:45:31.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:45:31.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:45:31.57$vck44/vblo=6,719.99 2006.285.15:45:31.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.15:45:31.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.15:45:31.57#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:31.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:45:31.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:45:31.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:45:31.57#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:45:31.57#ibcon#first serial, iclass 5, count 0 2006.285.15:45:31.57#ibcon#enter sib2, iclass 5, count 0 2006.285.15:45:31.57#ibcon#flushed, iclass 5, count 0 2006.285.15:45:31.57#ibcon#about to write, iclass 5, count 0 2006.285.15:45:31.57#ibcon#wrote, iclass 5, count 0 2006.285.15:45:31.57#ibcon#about to read 3, iclass 5, count 0 2006.285.15:45:31.59#ibcon#read 3, iclass 5, count 0 2006.285.15:45:31.59#ibcon#about to read 4, iclass 5, count 0 2006.285.15:45:31.59#ibcon#read 4, iclass 5, count 0 2006.285.15:45:31.59#ibcon#about to read 5, iclass 5, count 0 2006.285.15:45:31.59#ibcon#read 5, iclass 5, count 0 2006.285.15:45:31.59#ibcon#about to read 6, iclass 5, count 0 2006.285.15:45:31.59#ibcon#read 6, iclass 5, count 0 2006.285.15:45:31.59#ibcon#end of sib2, iclass 5, count 0 2006.285.15:45:31.59#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:45:31.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:45:31.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.15:45:31.59#ibcon#*before write, iclass 5, count 0 2006.285.15:45:31.59#ibcon#enter sib2, iclass 5, count 0 2006.285.15:45:31.59#ibcon#flushed, iclass 5, count 0 2006.285.15:45:31.59#ibcon#about to write, iclass 5, count 0 2006.285.15:45:31.59#ibcon#wrote, iclass 5, count 0 2006.285.15:45:31.59#ibcon#about to read 3, iclass 5, count 0 2006.285.15:45:31.63#ibcon#read 3, iclass 5, count 0 2006.285.15:45:31.63#ibcon#about to read 4, iclass 5, count 0 2006.285.15:45:31.63#ibcon#read 4, iclass 5, count 0 2006.285.15:45:31.63#ibcon#about to read 5, iclass 5, count 0 2006.285.15:45:31.63#ibcon#read 5, iclass 5, count 0 2006.285.15:45:31.63#ibcon#about to read 6, iclass 5, count 0 2006.285.15:45:31.63#ibcon#read 6, iclass 5, count 0 2006.285.15:45:31.63#ibcon#end of sib2, iclass 5, count 0 2006.285.15:45:31.63#ibcon#*after write, iclass 5, count 0 2006.285.15:45:31.63#ibcon#*before return 0, iclass 5, count 0 2006.285.15:45:31.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:45:31.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.15:45:31.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:45:31.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:45:31.63$vck44/vb=6,3 2006.285.15:45:31.69#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.15:45:31.69#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.15:45:31.69#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:31.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:45:31.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:45:31.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:45:31.69#ibcon#enter wrdev, iclass 7, count 2 2006.285.15:45:31.69#ibcon#first serial, iclass 7, count 2 2006.285.15:45:31.69#ibcon#enter sib2, iclass 7, count 2 2006.285.15:45:31.69#ibcon#flushed, iclass 7, count 2 2006.285.15:45:31.69#ibcon#about to write, iclass 7, count 2 2006.285.15:45:31.69#ibcon#wrote, iclass 7, count 2 2006.285.15:45:31.69#ibcon#about to read 3, iclass 7, count 2 2006.285.15:45:31.71#ibcon#read 3, iclass 7, count 2 2006.285.15:45:31.71#ibcon#about to read 4, iclass 7, count 2 2006.285.15:45:31.71#ibcon#read 4, iclass 7, count 2 2006.285.15:45:31.71#ibcon#about to read 5, iclass 7, count 2 2006.285.15:45:31.71#ibcon#read 5, iclass 7, count 2 2006.285.15:45:31.71#ibcon#about to read 6, iclass 7, count 2 2006.285.15:45:31.71#ibcon#read 6, iclass 7, count 2 2006.285.15:45:31.71#ibcon#end of sib2, iclass 7, count 2 2006.285.15:45:31.71#ibcon#*mode == 0, iclass 7, count 2 2006.285.15:45:31.71#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.15:45:31.71#ibcon#[27=AT06-03\r\n] 2006.285.15:45:31.71#ibcon#*before write, iclass 7, count 2 2006.285.15:45:31.71#ibcon#enter sib2, iclass 7, count 2 2006.285.15:45:31.71#ibcon#flushed, iclass 7, count 2 2006.285.15:45:31.71#ibcon#about to write, iclass 7, count 2 2006.285.15:45:31.71#ibcon#wrote, iclass 7, count 2 2006.285.15:45:31.71#ibcon#about to read 3, iclass 7, count 2 2006.285.15:45:31.74#ibcon#read 3, iclass 7, count 2 2006.285.15:45:31.74#ibcon#about to read 4, iclass 7, count 2 2006.285.15:45:31.74#ibcon#read 4, iclass 7, count 2 2006.285.15:45:31.74#ibcon#about to read 5, iclass 7, count 2 2006.285.15:45:31.74#ibcon#read 5, iclass 7, count 2 2006.285.15:45:31.74#ibcon#about to read 6, iclass 7, count 2 2006.285.15:45:31.74#ibcon#read 6, iclass 7, count 2 2006.285.15:45:31.74#ibcon#end of sib2, iclass 7, count 2 2006.285.15:45:31.74#ibcon#*after write, iclass 7, count 2 2006.285.15:45:31.74#ibcon#*before return 0, iclass 7, count 2 2006.285.15:45:31.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:45:31.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.15:45:31.74#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.15:45:31.74#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:31.74#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:45:31.86#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:45:31.86#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:45:31.86#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:45:31.86#ibcon#first serial, iclass 7, count 0 2006.285.15:45:31.86#ibcon#enter sib2, iclass 7, count 0 2006.285.15:45:31.86#ibcon#flushed, iclass 7, count 0 2006.285.15:45:31.86#ibcon#about to write, iclass 7, count 0 2006.285.15:45:31.86#ibcon#wrote, iclass 7, count 0 2006.285.15:45:31.86#ibcon#about to read 3, iclass 7, count 0 2006.285.15:45:31.88#ibcon#read 3, iclass 7, count 0 2006.285.15:45:31.88#ibcon#about to read 4, iclass 7, count 0 2006.285.15:45:31.88#ibcon#read 4, iclass 7, count 0 2006.285.15:45:31.88#ibcon#about to read 5, iclass 7, count 0 2006.285.15:45:31.88#ibcon#read 5, iclass 7, count 0 2006.285.15:45:31.88#ibcon#about to read 6, iclass 7, count 0 2006.285.15:45:31.88#ibcon#read 6, iclass 7, count 0 2006.285.15:45:31.88#ibcon#end of sib2, iclass 7, count 0 2006.285.15:45:31.88#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:45:31.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:45:31.88#ibcon#[27=USB\r\n] 2006.285.15:45:31.88#ibcon#*before write, iclass 7, count 0 2006.285.15:45:31.88#ibcon#enter sib2, iclass 7, count 0 2006.285.15:45:31.88#ibcon#flushed, iclass 7, count 0 2006.285.15:45:31.88#ibcon#about to write, iclass 7, count 0 2006.285.15:45:31.88#ibcon#wrote, iclass 7, count 0 2006.285.15:45:31.88#ibcon#about to read 3, iclass 7, count 0 2006.285.15:45:31.91#ibcon#read 3, iclass 7, count 0 2006.285.15:45:31.91#ibcon#about to read 4, iclass 7, count 0 2006.285.15:45:31.91#ibcon#read 4, iclass 7, count 0 2006.285.15:45:31.91#ibcon#about to read 5, iclass 7, count 0 2006.285.15:45:31.91#ibcon#read 5, iclass 7, count 0 2006.285.15:45:31.91#ibcon#about to read 6, iclass 7, count 0 2006.285.15:45:31.91#ibcon#read 6, iclass 7, count 0 2006.285.15:45:31.91#ibcon#end of sib2, iclass 7, count 0 2006.285.15:45:31.91#ibcon#*after write, iclass 7, count 0 2006.285.15:45:31.91#ibcon#*before return 0, iclass 7, count 0 2006.285.15:45:31.91#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:45:31.91#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.15:45:31.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:45:31.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:45:31.91$vck44/vblo=7,734.99 2006.285.15:45:31.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.15:45:31.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.15:45:31.91#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:31.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:45:31.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:45:31.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:45:31.91#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:45:31.91#ibcon#first serial, iclass 11, count 0 2006.285.15:45:31.91#ibcon#enter sib2, iclass 11, count 0 2006.285.15:45:31.91#ibcon#flushed, iclass 11, count 0 2006.285.15:45:31.91#ibcon#about to write, iclass 11, count 0 2006.285.15:45:31.91#ibcon#wrote, iclass 11, count 0 2006.285.15:45:31.91#ibcon#about to read 3, iclass 11, count 0 2006.285.15:45:31.93#ibcon#read 3, iclass 11, count 0 2006.285.15:45:31.93#ibcon#about to read 4, iclass 11, count 0 2006.285.15:45:31.93#ibcon#read 4, iclass 11, count 0 2006.285.15:45:31.93#ibcon#about to read 5, iclass 11, count 0 2006.285.15:45:31.93#ibcon#read 5, iclass 11, count 0 2006.285.15:45:31.93#ibcon#about to read 6, iclass 11, count 0 2006.285.15:45:31.93#ibcon#read 6, iclass 11, count 0 2006.285.15:45:31.93#ibcon#end of sib2, iclass 11, count 0 2006.285.15:45:31.93#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:45:31.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:45:31.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.15:45:31.93#ibcon#*before write, iclass 11, count 0 2006.285.15:45:31.93#ibcon#enter sib2, iclass 11, count 0 2006.285.15:45:31.93#ibcon#flushed, iclass 11, count 0 2006.285.15:45:31.93#ibcon#about to write, iclass 11, count 0 2006.285.15:45:31.93#ibcon#wrote, iclass 11, count 0 2006.285.15:45:31.93#ibcon#about to read 3, iclass 11, count 0 2006.285.15:45:31.97#ibcon#read 3, iclass 11, count 0 2006.285.15:45:31.97#ibcon#about to read 4, iclass 11, count 0 2006.285.15:45:31.97#ibcon#read 4, iclass 11, count 0 2006.285.15:45:31.97#ibcon#about to read 5, iclass 11, count 0 2006.285.15:45:31.97#ibcon#read 5, iclass 11, count 0 2006.285.15:45:31.97#ibcon#about to read 6, iclass 11, count 0 2006.285.15:45:31.97#ibcon#read 6, iclass 11, count 0 2006.285.15:45:31.97#ibcon#end of sib2, iclass 11, count 0 2006.285.15:45:31.97#ibcon#*after write, iclass 11, count 0 2006.285.15:45:31.97#ibcon#*before return 0, iclass 11, count 0 2006.285.15:45:31.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:45:31.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.15:45:31.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:45:31.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:45:31.97$vck44/vb=7,4 2006.285.15:45:31.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.15:45:31.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.15:45:31.97#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:31.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:45:32.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:45:32.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:45:32.03#ibcon#enter wrdev, iclass 13, count 2 2006.285.15:45:32.03#ibcon#first serial, iclass 13, count 2 2006.285.15:45:32.03#ibcon#enter sib2, iclass 13, count 2 2006.285.15:45:32.03#ibcon#flushed, iclass 13, count 2 2006.285.15:45:32.03#ibcon#about to write, iclass 13, count 2 2006.285.15:45:32.03#ibcon#wrote, iclass 13, count 2 2006.285.15:45:32.03#ibcon#about to read 3, iclass 13, count 2 2006.285.15:45:32.05#ibcon#read 3, iclass 13, count 2 2006.285.15:45:32.05#ibcon#about to read 4, iclass 13, count 2 2006.285.15:45:32.05#ibcon#read 4, iclass 13, count 2 2006.285.15:45:32.05#ibcon#about to read 5, iclass 13, count 2 2006.285.15:45:32.05#ibcon#read 5, iclass 13, count 2 2006.285.15:45:32.05#ibcon#about to read 6, iclass 13, count 2 2006.285.15:45:32.05#ibcon#read 6, iclass 13, count 2 2006.285.15:45:32.05#ibcon#end of sib2, iclass 13, count 2 2006.285.15:45:32.05#ibcon#*mode == 0, iclass 13, count 2 2006.285.15:45:32.05#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.15:45:32.05#ibcon#[27=AT07-04\r\n] 2006.285.15:45:32.05#ibcon#*before write, iclass 13, count 2 2006.285.15:45:32.05#ibcon#enter sib2, iclass 13, count 2 2006.285.15:45:32.05#ibcon#flushed, iclass 13, count 2 2006.285.15:45:32.05#ibcon#about to write, iclass 13, count 2 2006.285.15:45:32.05#ibcon#wrote, iclass 13, count 2 2006.285.15:45:32.05#ibcon#about to read 3, iclass 13, count 2 2006.285.15:45:32.08#ibcon#read 3, iclass 13, count 2 2006.285.15:45:32.08#ibcon#about to read 4, iclass 13, count 2 2006.285.15:45:32.08#ibcon#read 4, iclass 13, count 2 2006.285.15:45:32.08#ibcon#about to read 5, iclass 13, count 2 2006.285.15:45:32.08#ibcon#read 5, iclass 13, count 2 2006.285.15:45:32.08#ibcon#about to read 6, iclass 13, count 2 2006.285.15:45:32.08#ibcon#read 6, iclass 13, count 2 2006.285.15:45:32.08#ibcon#end of sib2, iclass 13, count 2 2006.285.15:45:32.08#ibcon#*after write, iclass 13, count 2 2006.285.15:45:32.08#ibcon#*before return 0, iclass 13, count 2 2006.285.15:45:32.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:45:32.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.15:45:32.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.15:45:32.08#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:32.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:45:32.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:45:32.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:45:32.20#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:45:32.20#ibcon#first serial, iclass 13, count 0 2006.285.15:45:32.20#ibcon#enter sib2, iclass 13, count 0 2006.285.15:45:32.20#ibcon#flushed, iclass 13, count 0 2006.285.15:45:32.20#ibcon#about to write, iclass 13, count 0 2006.285.15:45:32.20#ibcon#wrote, iclass 13, count 0 2006.285.15:45:32.20#ibcon#about to read 3, iclass 13, count 0 2006.285.15:45:32.22#ibcon#read 3, iclass 13, count 0 2006.285.15:45:32.22#ibcon#about to read 4, iclass 13, count 0 2006.285.15:45:32.22#ibcon#read 4, iclass 13, count 0 2006.285.15:45:32.22#ibcon#about to read 5, iclass 13, count 0 2006.285.15:45:32.22#ibcon#read 5, iclass 13, count 0 2006.285.15:45:32.22#ibcon#about to read 6, iclass 13, count 0 2006.285.15:45:32.22#ibcon#read 6, iclass 13, count 0 2006.285.15:45:32.22#ibcon#end of sib2, iclass 13, count 0 2006.285.15:45:32.22#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:45:32.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:45:32.22#ibcon#[27=USB\r\n] 2006.285.15:45:32.22#ibcon#*before write, iclass 13, count 0 2006.285.15:45:32.22#ibcon#enter sib2, iclass 13, count 0 2006.285.15:45:32.22#ibcon#flushed, iclass 13, count 0 2006.285.15:45:32.22#ibcon#about to write, iclass 13, count 0 2006.285.15:45:32.22#ibcon#wrote, iclass 13, count 0 2006.285.15:45:32.22#ibcon#about to read 3, iclass 13, count 0 2006.285.15:45:32.25#ibcon#read 3, iclass 13, count 0 2006.285.15:45:32.25#ibcon#about to read 4, iclass 13, count 0 2006.285.15:45:32.25#ibcon#read 4, iclass 13, count 0 2006.285.15:45:32.25#ibcon#about to read 5, iclass 13, count 0 2006.285.15:45:32.25#ibcon#read 5, iclass 13, count 0 2006.285.15:45:32.25#ibcon#about to read 6, iclass 13, count 0 2006.285.15:45:32.25#ibcon#read 6, iclass 13, count 0 2006.285.15:45:32.25#ibcon#end of sib2, iclass 13, count 0 2006.285.15:45:32.25#ibcon#*after write, iclass 13, count 0 2006.285.15:45:32.25#ibcon#*before return 0, iclass 13, count 0 2006.285.15:45:32.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:45:32.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.15:45:32.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:45:32.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:45:32.25$vck44/vblo=8,744.99 2006.285.15:45:32.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.15:45:32.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.15:45:32.25#ibcon#ireg 17 cls_cnt 0 2006.285.15:45:32.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:45:32.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:45:32.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:45:32.25#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:45:32.25#ibcon#first serial, iclass 15, count 0 2006.285.15:45:32.25#ibcon#enter sib2, iclass 15, count 0 2006.285.15:45:32.25#ibcon#flushed, iclass 15, count 0 2006.285.15:45:32.25#ibcon#about to write, iclass 15, count 0 2006.285.15:45:32.25#ibcon#wrote, iclass 15, count 0 2006.285.15:45:32.25#ibcon#about to read 3, iclass 15, count 0 2006.285.15:45:32.27#ibcon#read 3, iclass 15, count 0 2006.285.15:45:32.27#ibcon#about to read 4, iclass 15, count 0 2006.285.15:45:32.27#ibcon#read 4, iclass 15, count 0 2006.285.15:45:32.27#ibcon#about to read 5, iclass 15, count 0 2006.285.15:45:32.27#ibcon#read 5, iclass 15, count 0 2006.285.15:45:32.27#ibcon#about to read 6, iclass 15, count 0 2006.285.15:45:32.27#ibcon#read 6, iclass 15, count 0 2006.285.15:45:32.27#ibcon#end of sib2, iclass 15, count 0 2006.285.15:45:32.27#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:45:32.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:45:32.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.15:45:32.27#ibcon#*before write, iclass 15, count 0 2006.285.15:45:32.27#ibcon#enter sib2, iclass 15, count 0 2006.285.15:45:32.27#ibcon#flushed, iclass 15, count 0 2006.285.15:45:32.27#ibcon#about to write, iclass 15, count 0 2006.285.15:45:32.27#ibcon#wrote, iclass 15, count 0 2006.285.15:45:32.27#ibcon#about to read 3, iclass 15, count 0 2006.285.15:45:32.31#ibcon#read 3, iclass 15, count 0 2006.285.15:45:32.31#ibcon#about to read 4, iclass 15, count 0 2006.285.15:45:32.31#ibcon#read 4, iclass 15, count 0 2006.285.15:45:32.31#ibcon#about to read 5, iclass 15, count 0 2006.285.15:45:32.31#ibcon#read 5, iclass 15, count 0 2006.285.15:45:32.31#ibcon#about to read 6, iclass 15, count 0 2006.285.15:45:32.31#ibcon#read 6, iclass 15, count 0 2006.285.15:45:32.31#ibcon#end of sib2, iclass 15, count 0 2006.285.15:45:32.31#ibcon#*after write, iclass 15, count 0 2006.285.15:45:32.31#ibcon#*before return 0, iclass 15, count 0 2006.285.15:45:32.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:45:32.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.15:45:32.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:45:32.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:45:32.31$vck44/vb=8,4 2006.285.15:45:32.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.15:45:32.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.15:45:32.31#ibcon#ireg 11 cls_cnt 2 2006.285.15:45:32.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:45:32.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:45:32.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:45:32.37#ibcon#enter wrdev, iclass 17, count 2 2006.285.15:45:32.37#ibcon#first serial, iclass 17, count 2 2006.285.15:45:32.37#ibcon#enter sib2, iclass 17, count 2 2006.285.15:45:32.37#ibcon#flushed, iclass 17, count 2 2006.285.15:45:32.37#ibcon#about to write, iclass 17, count 2 2006.285.15:45:32.37#ibcon#wrote, iclass 17, count 2 2006.285.15:45:32.37#ibcon#about to read 3, iclass 17, count 2 2006.285.15:45:32.39#ibcon#read 3, iclass 17, count 2 2006.285.15:45:32.39#ibcon#about to read 4, iclass 17, count 2 2006.285.15:45:32.39#ibcon#read 4, iclass 17, count 2 2006.285.15:45:32.39#ibcon#about to read 5, iclass 17, count 2 2006.285.15:45:32.39#ibcon#read 5, iclass 17, count 2 2006.285.15:45:32.39#ibcon#about to read 6, iclass 17, count 2 2006.285.15:45:32.39#ibcon#read 6, iclass 17, count 2 2006.285.15:45:32.39#ibcon#end of sib2, iclass 17, count 2 2006.285.15:45:32.39#ibcon#*mode == 0, iclass 17, count 2 2006.285.15:45:32.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.15:45:32.39#ibcon#[27=AT08-04\r\n] 2006.285.15:45:32.39#ibcon#*before write, iclass 17, count 2 2006.285.15:45:32.39#ibcon#enter sib2, iclass 17, count 2 2006.285.15:45:32.39#ibcon#flushed, iclass 17, count 2 2006.285.15:45:32.39#ibcon#about to write, iclass 17, count 2 2006.285.15:45:32.39#ibcon#wrote, iclass 17, count 2 2006.285.15:45:32.39#ibcon#about to read 3, iclass 17, count 2 2006.285.15:45:32.42#ibcon#read 3, iclass 17, count 2 2006.285.15:45:32.42#ibcon#about to read 4, iclass 17, count 2 2006.285.15:45:32.42#ibcon#read 4, iclass 17, count 2 2006.285.15:45:32.42#ibcon#about to read 5, iclass 17, count 2 2006.285.15:45:32.42#ibcon#read 5, iclass 17, count 2 2006.285.15:45:32.42#ibcon#about to read 6, iclass 17, count 2 2006.285.15:45:32.42#ibcon#read 6, iclass 17, count 2 2006.285.15:45:32.42#ibcon#end of sib2, iclass 17, count 2 2006.285.15:45:32.42#ibcon#*after write, iclass 17, count 2 2006.285.15:45:32.42#ibcon#*before return 0, iclass 17, count 2 2006.285.15:45:32.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:45:32.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.15:45:32.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.15:45:32.42#ibcon#ireg 7 cls_cnt 0 2006.285.15:45:32.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:45:32.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:45:32.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:45:32.54#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:45:32.54#ibcon#first serial, iclass 17, count 0 2006.285.15:45:32.54#ibcon#enter sib2, iclass 17, count 0 2006.285.15:45:32.54#ibcon#flushed, iclass 17, count 0 2006.285.15:45:32.54#ibcon#about to write, iclass 17, count 0 2006.285.15:45:32.54#ibcon#wrote, iclass 17, count 0 2006.285.15:45:32.54#ibcon#about to read 3, iclass 17, count 0 2006.285.15:45:32.56#ibcon#read 3, iclass 17, count 0 2006.285.15:45:32.56#ibcon#about to read 4, iclass 17, count 0 2006.285.15:45:32.56#ibcon#read 4, iclass 17, count 0 2006.285.15:45:32.56#ibcon#about to read 5, iclass 17, count 0 2006.285.15:45:32.56#ibcon#read 5, iclass 17, count 0 2006.285.15:45:32.56#ibcon#about to read 6, iclass 17, count 0 2006.285.15:45:32.56#ibcon#read 6, iclass 17, count 0 2006.285.15:45:32.56#ibcon#end of sib2, iclass 17, count 0 2006.285.15:45:32.56#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:45:32.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:45:32.56#ibcon#[27=USB\r\n] 2006.285.15:45:32.56#ibcon#*before write, iclass 17, count 0 2006.285.15:45:32.56#ibcon#enter sib2, iclass 17, count 0 2006.285.15:45:32.56#ibcon#flushed, iclass 17, count 0 2006.285.15:45:32.56#ibcon#about to write, iclass 17, count 0 2006.285.15:45:32.56#ibcon#wrote, iclass 17, count 0 2006.285.15:45:32.56#ibcon#about to read 3, iclass 17, count 0 2006.285.15:45:32.59#ibcon#read 3, iclass 17, count 0 2006.285.15:45:32.59#ibcon#about to read 4, iclass 17, count 0 2006.285.15:45:32.59#ibcon#read 4, iclass 17, count 0 2006.285.15:45:32.59#ibcon#about to read 5, iclass 17, count 0 2006.285.15:45:32.59#ibcon#read 5, iclass 17, count 0 2006.285.15:45:32.59#ibcon#about to read 6, iclass 17, count 0 2006.285.15:45:32.59#ibcon#read 6, iclass 17, count 0 2006.285.15:45:32.59#ibcon#end of sib2, iclass 17, count 0 2006.285.15:45:32.59#ibcon#*after write, iclass 17, count 0 2006.285.15:45:32.59#ibcon#*before return 0, iclass 17, count 0 2006.285.15:45:32.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:45:32.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.15:45:32.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:45:32.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:45:32.59$vck44/vabw=wide 2006.285.15:45:32.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.15:45:32.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.15:45:32.59#ibcon#ireg 8 cls_cnt 0 2006.285.15:45:32.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:45:32.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:45:32.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:45:32.59#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:45:32.59#ibcon#first serial, iclass 19, count 0 2006.285.15:45:32.59#ibcon#enter sib2, iclass 19, count 0 2006.285.15:45:32.59#ibcon#flushed, iclass 19, count 0 2006.285.15:45:32.59#ibcon#about to write, iclass 19, count 0 2006.285.15:45:32.59#ibcon#wrote, iclass 19, count 0 2006.285.15:45:32.59#ibcon#about to read 3, iclass 19, count 0 2006.285.15:45:32.61#ibcon#read 3, iclass 19, count 0 2006.285.15:45:32.61#ibcon#about to read 4, iclass 19, count 0 2006.285.15:45:32.61#ibcon#read 4, iclass 19, count 0 2006.285.15:45:32.61#ibcon#about to read 5, iclass 19, count 0 2006.285.15:45:32.61#ibcon#read 5, iclass 19, count 0 2006.285.15:45:32.61#ibcon#about to read 6, iclass 19, count 0 2006.285.15:45:32.61#ibcon#read 6, iclass 19, count 0 2006.285.15:45:32.61#ibcon#end of sib2, iclass 19, count 0 2006.285.15:45:32.61#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:45:32.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:45:32.61#ibcon#[25=BW32\r\n] 2006.285.15:45:32.61#ibcon#*before write, iclass 19, count 0 2006.285.15:45:32.61#ibcon#enter sib2, iclass 19, count 0 2006.285.15:45:32.61#ibcon#flushed, iclass 19, count 0 2006.285.15:45:32.61#ibcon#about to write, iclass 19, count 0 2006.285.15:45:32.61#ibcon#wrote, iclass 19, count 0 2006.285.15:45:32.61#ibcon#about to read 3, iclass 19, count 0 2006.285.15:45:32.64#ibcon#read 3, iclass 19, count 0 2006.285.15:45:32.64#ibcon#about to read 4, iclass 19, count 0 2006.285.15:45:32.64#ibcon#read 4, iclass 19, count 0 2006.285.15:45:32.64#ibcon#about to read 5, iclass 19, count 0 2006.285.15:45:32.64#ibcon#read 5, iclass 19, count 0 2006.285.15:45:32.64#ibcon#about to read 6, iclass 19, count 0 2006.285.15:45:32.64#ibcon#read 6, iclass 19, count 0 2006.285.15:45:32.64#ibcon#end of sib2, iclass 19, count 0 2006.285.15:45:32.64#ibcon#*after write, iclass 19, count 0 2006.285.15:45:32.64#ibcon#*before return 0, iclass 19, count 0 2006.285.15:45:32.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:45:32.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:45:32.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:45:32.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:45:32.64$vck44/vbbw=wide 2006.285.15:45:32.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.15:45:32.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.15:45:32.79#ibcon#ireg 8 cls_cnt 0 2006.285.15:45:32.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:45:32.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:45:32.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:45:32.79#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:45:32.79#ibcon#first serial, iclass 21, count 0 2006.285.15:45:32.79#ibcon#enter sib2, iclass 21, count 0 2006.285.15:45:32.79#ibcon#flushed, iclass 21, count 0 2006.285.15:45:32.79#ibcon#about to write, iclass 21, count 0 2006.285.15:45:32.79#ibcon#wrote, iclass 21, count 0 2006.285.15:45:32.79#ibcon#about to read 3, iclass 21, count 0 2006.285.15:45:32.81#ibcon#read 3, iclass 21, count 0 2006.285.15:45:32.81#ibcon#about to read 4, iclass 21, count 0 2006.285.15:45:32.81#ibcon#read 4, iclass 21, count 0 2006.285.15:45:32.81#ibcon#about to read 5, iclass 21, count 0 2006.285.15:45:32.81#ibcon#read 5, iclass 21, count 0 2006.285.15:45:32.81#ibcon#about to read 6, iclass 21, count 0 2006.285.15:45:32.81#ibcon#read 6, iclass 21, count 0 2006.285.15:45:32.81#ibcon#end of sib2, iclass 21, count 0 2006.285.15:45:32.81#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:45:32.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:45:32.81#ibcon#[27=BW32\r\n] 2006.285.15:45:32.81#ibcon#*before write, iclass 21, count 0 2006.285.15:45:32.81#ibcon#enter sib2, iclass 21, count 0 2006.285.15:45:32.81#ibcon#flushed, iclass 21, count 0 2006.285.15:45:32.81#ibcon#about to write, iclass 21, count 0 2006.285.15:45:32.81#ibcon#wrote, iclass 21, count 0 2006.285.15:45:32.81#ibcon#about to read 3, iclass 21, count 0 2006.285.15:45:32.84#ibcon#read 3, iclass 21, count 0 2006.285.15:45:32.84#ibcon#about to read 4, iclass 21, count 0 2006.285.15:45:32.84#ibcon#read 4, iclass 21, count 0 2006.285.15:45:32.84#ibcon#about to read 5, iclass 21, count 0 2006.285.15:45:32.84#ibcon#read 5, iclass 21, count 0 2006.285.15:45:32.84#ibcon#about to read 6, iclass 21, count 0 2006.285.15:45:32.84#ibcon#read 6, iclass 21, count 0 2006.285.15:45:32.84#ibcon#end of sib2, iclass 21, count 0 2006.285.15:45:32.84#ibcon#*after write, iclass 21, count 0 2006.285.15:45:32.84#ibcon#*before return 0, iclass 21, count 0 2006.285.15:45:32.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:45:32.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:45:32.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:45:32.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:45:32.84$setupk4/ifdk4 2006.285.15:45:32.84$ifdk4/lo= 2006.285.15:45:32.84$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.15:45:32.84$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.15:45:32.84$ifdk4/patch= 2006.285.15:45:32.84$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.15:45:32.84$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.15:45:32.84$setupk4/!*+20s 2006.285.15:45:33.11#abcon#<5=/02 1.0 3.1 18.93 921015.0\r\n> 2006.285.15:45:33.13#abcon#{5=INTERFACE CLEAR} 2006.285.15:45:33.19#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:45:43.28#abcon#<5=/02 1.0 3.0 18.93 921015.0\r\n> 2006.285.15:45:43.30#abcon#{5=INTERFACE CLEAR} 2006.285.15:45:43.36#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:45:46.57$setupk4/"tpicd 2006.285.15:45:46.57$setupk4/echo=off 2006.285.15:45:46.57$setupk4/xlog=off 2006.285.15:45:46.57:!2006.285.15:47:27 2006.285.15:45:48.13#trakl#Source acquired 2006.285.15:45:49.13#flagr#flagr/antenna,acquired 2006.285.15:47:27.00:preob 2006.285.15:47:27.14/onsource/TRACKING 2006.285.15:47:27.14:!2006.285.15:47:37 2006.285.15:47:37.00:"tape 2006.285.15:47:37.00:"st=record 2006.285.15:47:37.00:data_valid=on 2006.285.15:47:37.00:midob 2006.285.15:47:37.14/onsource/TRACKING 2006.285.15:47:37.14/wx/18.87,1015.0,92 2006.285.15:47:37.27/cable/+6.4999E-03 2006.285.15:47:38.36/va/01,07,usb,yes,32,35 2006.285.15:47:38.36/va/02,06,usb,yes,32,33 2006.285.15:47:38.36/va/03,07,usb,yes,32,34 2006.285.15:47:38.36/va/04,06,usb,yes,33,35 2006.285.15:47:38.36/va/05,03,usb,yes,33,33 2006.285.15:47:38.36/va/06,04,usb,yes,29,29 2006.285.15:47:38.36/va/07,04,usb,yes,30,31 2006.285.15:47:38.36/va/08,03,usb,yes,31,37 2006.285.15:47:38.59/valo/01,524.99,yes,locked 2006.285.15:47:38.59/valo/02,534.99,yes,locked 2006.285.15:47:38.59/valo/03,564.99,yes,locked 2006.285.15:47:38.59/valo/04,624.99,yes,locked 2006.285.15:47:38.59/valo/05,734.99,yes,locked 2006.285.15:47:38.59/valo/06,814.99,yes,locked 2006.285.15:47:38.59/valo/07,864.99,yes,locked 2006.285.15:47:38.59/valo/08,884.99,yes,locked 2006.285.15:47:39.68/vb/01,04,usb,yes,30,28 2006.285.15:47:39.68/vb/02,05,usb,yes,28,28 2006.285.15:47:39.68/vb/03,04,usb,yes,29,32 2006.285.15:47:39.68/vb/04,05,usb,yes,29,28 2006.285.15:47:39.68/vb/05,04,usb,yes,26,28 2006.285.15:47:39.68/vb/06,03,usb,yes,37,33 2006.285.15:47:39.68/vb/07,04,usb,yes,30,30 2006.285.15:47:39.68/vb/08,04,usb,yes,27,31 2006.285.15:47:39.92/vblo/01,629.99,yes,locked 2006.285.15:47:39.92/vblo/02,634.99,yes,locked 2006.285.15:47:39.92/vblo/03,649.99,yes,locked 2006.285.15:47:39.92/vblo/04,679.99,yes,locked 2006.285.15:47:39.92/vblo/05,709.99,yes,locked 2006.285.15:47:39.92/vblo/06,719.99,yes,locked 2006.285.15:47:39.92/vblo/07,734.99,yes,locked 2006.285.15:47:39.92/vblo/08,744.99,yes,locked 2006.285.15:47:40.07/vabw/8 2006.285.15:47:40.22/vbbw/8 2006.285.15:47:40.31/xfe/off,on,12.2 2006.285.15:47:40.68/ifatt/23,28,28,28 2006.285.15:47:41.08/fmout-gps/S +2.56E-07 2006.285.15:47:41.10:!2006.285.15:49:27 2006.285.15:49:27.01:data_valid=off 2006.285.15:49:27.01:"et 2006.285.15:49:27.01:!+3s 2006.285.15:49:30.02:"tape 2006.285.15:49:30.02:postob 2006.285.15:49:30.11/cable/+6.5000E-03 2006.285.15:49:30.11/wx/18.82,1015.0,92 2006.285.15:49:31.08/fmout-gps/S +2.57E-07 2006.285.15:49:31.08:scan_name=285-1552,jd0610,50 2006.285.15:49:31.08:source=0552+398,055530.81,394849.2,2000.0,cw 2006.285.15:49:32.14#flagr#flagr/antenna,new-source 2006.285.15:49:32.14:checkk5 2006.285.15:49:32.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.15:49:33.39/chk_autoobs//k5ts2/ autoobs is running! 2006.285.15:49:33.79/chk_autoobs//k5ts3/ autoobs is running! 2006.285.15:49:34.23/chk_autoobs//k5ts4/ autoobs is running! 2006.285.15:49:35.01/chk_obsdata//k5ts1/T2851547??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.15:49:35.46/chk_obsdata//k5ts2/T2851547??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.15:49:36.18/chk_obsdata//k5ts3/T2851547??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.15:49:36.68/chk_obsdata//k5ts4/T2851547??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.15:49:37.52/k5log//k5ts1_log_newline 2006.285.15:49:38.56/k5log//k5ts2_log_newline 2006.285.15:49:39.71/k5log//k5ts3_log_newline 2006.285.15:49:40.51/k5log//k5ts4_log_newline 2006.285.15:49:40.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.15:49:40.53:setupk4=1 2006.285.15:49:40.53$setupk4/echo=on 2006.285.15:49:40.53$setupk4/pcalon 2006.285.15:49:40.53$pcalon/"no phase cal control is implemented here 2006.285.15:49:40.53$setupk4/"tpicd=stop 2006.285.15:49:40.53$setupk4/"rec=synch_on 2006.285.15:49:40.53$setupk4/"rec_mode=128 2006.285.15:49:40.53$setupk4/!* 2006.285.15:49:40.53$setupk4/recpk4 2006.285.15:49:40.53$recpk4/recpatch= 2006.285.15:49:40.54$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.15:49:40.54$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.15:49:40.54$setupk4/vck44 2006.285.15:49:40.54$vck44/valo=1,524.99 2006.285.15:49:40.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.15:49:40.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.15:49:40.54#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:40.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:49:40.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:49:40.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:49:40.54#ibcon#enter wrdev, iclass 18, count 0 2006.285.15:49:40.54#ibcon#first serial, iclass 18, count 0 2006.285.15:49:40.54#ibcon#enter sib2, iclass 18, count 0 2006.285.15:49:40.54#ibcon#flushed, iclass 18, count 0 2006.285.15:49:40.54#ibcon#about to write, iclass 18, count 0 2006.285.15:49:40.54#ibcon#wrote, iclass 18, count 0 2006.285.15:49:40.54#ibcon#about to read 3, iclass 18, count 0 2006.285.15:49:40.56#ibcon#read 3, iclass 18, count 0 2006.285.15:49:40.56#ibcon#about to read 4, iclass 18, count 0 2006.285.15:49:40.56#ibcon#read 4, iclass 18, count 0 2006.285.15:49:40.56#ibcon#about to read 5, iclass 18, count 0 2006.285.15:49:40.56#ibcon#read 5, iclass 18, count 0 2006.285.15:49:40.56#ibcon#about to read 6, iclass 18, count 0 2006.285.15:49:40.56#ibcon#read 6, iclass 18, count 0 2006.285.15:49:40.56#ibcon#end of sib2, iclass 18, count 0 2006.285.15:49:40.56#ibcon#*mode == 0, iclass 18, count 0 2006.285.15:49:40.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.15:49:40.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.15:49:40.56#ibcon#*before write, iclass 18, count 0 2006.285.15:49:40.56#ibcon#enter sib2, iclass 18, count 0 2006.285.15:49:40.56#ibcon#flushed, iclass 18, count 0 2006.285.15:49:40.56#ibcon#about to write, iclass 18, count 0 2006.285.15:49:40.56#ibcon#wrote, iclass 18, count 0 2006.285.15:49:40.56#ibcon#about to read 3, iclass 18, count 0 2006.285.15:49:40.61#ibcon#read 3, iclass 18, count 0 2006.285.15:49:40.61#ibcon#about to read 4, iclass 18, count 0 2006.285.15:49:40.61#ibcon#read 4, iclass 18, count 0 2006.285.15:49:40.61#ibcon#about to read 5, iclass 18, count 0 2006.285.15:49:40.61#ibcon#read 5, iclass 18, count 0 2006.285.15:49:40.61#ibcon#about to read 6, iclass 18, count 0 2006.285.15:49:40.61#ibcon#read 6, iclass 18, count 0 2006.285.15:49:40.61#ibcon#end of sib2, iclass 18, count 0 2006.285.15:49:40.61#ibcon#*after write, iclass 18, count 0 2006.285.15:49:40.61#ibcon#*before return 0, iclass 18, count 0 2006.285.15:49:40.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:49:40.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:49:40.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.15:49:40.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.15:49:40.61$vck44/va=1,7 2006.285.15:49:40.61#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.15:49:40.61#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.15:49:40.61#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:40.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:49:40.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:49:40.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:49:40.61#ibcon#enter wrdev, iclass 20, count 2 2006.285.15:49:40.61#ibcon#first serial, iclass 20, count 2 2006.285.15:49:40.61#ibcon#enter sib2, iclass 20, count 2 2006.285.15:49:40.61#ibcon#flushed, iclass 20, count 2 2006.285.15:49:40.61#ibcon#about to write, iclass 20, count 2 2006.285.15:49:40.61#ibcon#wrote, iclass 20, count 2 2006.285.15:49:40.61#ibcon#about to read 3, iclass 20, count 2 2006.285.15:49:40.63#ibcon#read 3, iclass 20, count 2 2006.285.15:49:40.63#ibcon#about to read 4, iclass 20, count 2 2006.285.15:49:40.63#ibcon#read 4, iclass 20, count 2 2006.285.15:49:40.63#ibcon#about to read 5, iclass 20, count 2 2006.285.15:49:40.63#ibcon#read 5, iclass 20, count 2 2006.285.15:49:40.63#ibcon#about to read 6, iclass 20, count 2 2006.285.15:49:40.63#ibcon#read 6, iclass 20, count 2 2006.285.15:49:40.63#ibcon#end of sib2, iclass 20, count 2 2006.285.15:49:40.63#ibcon#*mode == 0, iclass 20, count 2 2006.285.15:49:40.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.15:49:40.63#ibcon#[25=AT01-07\r\n] 2006.285.15:49:40.63#ibcon#*before write, iclass 20, count 2 2006.285.15:49:40.63#ibcon#enter sib2, iclass 20, count 2 2006.285.15:49:40.63#ibcon#flushed, iclass 20, count 2 2006.285.15:49:40.63#ibcon#about to write, iclass 20, count 2 2006.285.15:49:40.63#ibcon#wrote, iclass 20, count 2 2006.285.15:49:40.63#ibcon#about to read 3, iclass 20, count 2 2006.285.15:49:40.66#ibcon#read 3, iclass 20, count 2 2006.285.15:49:40.66#ibcon#about to read 4, iclass 20, count 2 2006.285.15:49:40.66#ibcon#read 4, iclass 20, count 2 2006.285.15:49:40.66#ibcon#about to read 5, iclass 20, count 2 2006.285.15:49:40.66#ibcon#read 5, iclass 20, count 2 2006.285.15:49:40.66#ibcon#about to read 6, iclass 20, count 2 2006.285.15:49:40.66#ibcon#read 6, iclass 20, count 2 2006.285.15:49:40.66#ibcon#end of sib2, iclass 20, count 2 2006.285.15:49:40.66#ibcon#*after write, iclass 20, count 2 2006.285.15:49:40.66#ibcon#*before return 0, iclass 20, count 2 2006.285.15:49:40.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:49:40.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:49:40.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.15:49:40.66#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:40.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:49:40.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:49:40.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:49:40.78#ibcon#enter wrdev, iclass 20, count 0 2006.285.15:49:40.78#ibcon#first serial, iclass 20, count 0 2006.285.15:49:40.78#ibcon#enter sib2, iclass 20, count 0 2006.285.15:49:40.78#ibcon#flushed, iclass 20, count 0 2006.285.15:49:40.78#ibcon#about to write, iclass 20, count 0 2006.285.15:49:40.78#ibcon#wrote, iclass 20, count 0 2006.285.15:49:40.78#ibcon#about to read 3, iclass 20, count 0 2006.285.15:49:40.80#ibcon#read 3, iclass 20, count 0 2006.285.15:49:40.80#ibcon#about to read 4, iclass 20, count 0 2006.285.15:49:40.80#ibcon#read 4, iclass 20, count 0 2006.285.15:49:40.80#ibcon#about to read 5, iclass 20, count 0 2006.285.15:49:40.80#ibcon#read 5, iclass 20, count 0 2006.285.15:49:40.80#ibcon#about to read 6, iclass 20, count 0 2006.285.15:49:40.80#ibcon#read 6, iclass 20, count 0 2006.285.15:49:40.80#ibcon#end of sib2, iclass 20, count 0 2006.285.15:49:40.80#ibcon#*mode == 0, iclass 20, count 0 2006.285.15:49:40.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.15:49:40.80#ibcon#[25=USB\r\n] 2006.285.15:49:40.80#ibcon#*before write, iclass 20, count 0 2006.285.15:49:40.80#ibcon#enter sib2, iclass 20, count 0 2006.285.15:49:40.80#ibcon#flushed, iclass 20, count 0 2006.285.15:49:40.80#ibcon#about to write, iclass 20, count 0 2006.285.15:49:40.80#ibcon#wrote, iclass 20, count 0 2006.285.15:49:40.80#ibcon#about to read 3, iclass 20, count 0 2006.285.15:49:40.83#ibcon#read 3, iclass 20, count 0 2006.285.15:49:40.83#ibcon#about to read 4, iclass 20, count 0 2006.285.15:49:40.83#ibcon#read 4, iclass 20, count 0 2006.285.15:49:40.83#ibcon#about to read 5, iclass 20, count 0 2006.285.15:49:40.83#ibcon#read 5, iclass 20, count 0 2006.285.15:49:40.83#ibcon#about to read 6, iclass 20, count 0 2006.285.15:49:40.83#ibcon#read 6, iclass 20, count 0 2006.285.15:49:40.83#ibcon#end of sib2, iclass 20, count 0 2006.285.15:49:40.83#ibcon#*after write, iclass 20, count 0 2006.285.15:49:40.83#ibcon#*before return 0, iclass 20, count 0 2006.285.15:49:40.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:49:40.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:49:40.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.15:49:40.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.15:49:40.83$vck44/valo=2,534.99 2006.285.15:49:40.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.15:49:40.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.15:49:40.83#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:40.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:49:40.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:49:40.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:49:40.83#ibcon#enter wrdev, iclass 22, count 0 2006.285.15:49:40.83#ibcon#first serial, iclass 22, count 0 2006.285.15:49:40.83#ibcon#enter sib2, iclass 22, count 0 2006.285.15:49:40.83#ibcon#flushed, iclass 22, count 0 2006.285.15:49:40.83#ibcon#about to write, iclass 22, count 0 2006.285.15:49:40.83#ibcon#wrote, iclass 22, count 0 2006.285.15:49:40.83#ibcon#about to read 3, iclass 22, count 0 2006.285.15:49:40.85#ibcon#read 3, iclass 22, count 0 2006.285.15:49:40.85#ibcon#about to read 4, iclass 22, count 0 2006.285.15:49:40.85#ibcon#read 4, iclass 22, count 0 2006.285.15:49:40.85#ibcon#about to read 5, iclass 22, count 0 2006.285.15:49:40.85#ibcon#read 5, iclass 22, count 0 2006.285.15:49:40.85#ibcon#about to read 6, iclass 22, count 0 2006.285.15:49:40.85#ibcon#read 6, iclass 22, count 0 2006.285.15:49:40.85#ibcon#end of sib2, iclass 22, count 0 2006.285.15:49:40.85#ibcon#*mode == 0, iclass 22, count 0 2006.285.15:49:40.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.15:49:40.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.15:49:40.85#ibcon#*before write, iclass 22, count 0 2006.285.15:49:40.85#ibcon#enter sib2, iclass 22, count 0 2006.285.15:49:40.85#ibcon#flushed, iclass 22, count 0 2006.285.15:49:40.85#ibcon#about to write, iclass 22, count 0 2006.285.15:49:40.85#ibcon#wrote, iclass 22, count 0 2006.285.15:49:40.85#ibcon#about to read 3, iclass 22, count 0 2006.285.15:49:40.89#ibcon#read 3, iclass 22, count 0 2006.285.15:49:40.89#ibcon#about to read 4, iclass 22, count 0 2006.285.15:49:40.89#ibcon#read 4, iclass 22, count 0 2006.285.15:49:40.89#ibcon#about to read 5, iclass 22, count 0 2006.285.15:49:40.89#ibcon#read 5, iclass 22, count 0 2006.285.15:49:40.89#ibcon#about to read 6, iclass 22, count 0 2006.285.15:49:40.89#ibcon#read 6, iclass 22, count 0 2006.285.15:49:40.89#ibcon#end of sib2, iclass 22, count 0 2006.285.15:49:40.89#ibcon#*after write, iclass 22, count 0 2006.285.15:49:40.89#ibcon#*before return 0, iclass 22, count 0 2006.285.15:49:40.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:49:40.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:49:40.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.15:49:40.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.15:49:40.89$vck44/va=2,6 2006.285.15:49:40.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.15:49:40.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.15:49:40.89#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:40.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:49:40.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:49:40.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:49:40.95#ibcon#enter wrdev, iclass 24, count 2 2006.285.15:49:40.95#ibcon#first serial, iclass 24, count 2 2006.285.15:49:40.95#ibcon#enter sib2, iclass 24, count 2 2006.285.15:49:40.95#ibcon#flushed, iclass 24, count 2 2006.285.15:49:40.95#ibcon#about to write, iclass 24, count 2 2006.285.15:49:40.95#ibcon#wrote, iclass 24, count 2 2006.285.15:49:40.95#ibcon#about to read 3, iclass 24, count 2 2006.285.15:49:40.97#ibcon#read 3, iclass 24, count 2 2006.285.15:49:40.97#ibcon#about to read 4, iclass 24, count 2 2006.285.15:49:40.97#ibcon#read 4, iclass 24, count 2 2006.285.15:49:40.97#ibcon#about to read 5, iclass 24, count 2 2006.285.15:49:40.97#ibcon#read 5, iclass 24, count 2 2006.285.15:49:40.97#ibcon#about to read 6, iclass 24, count 2 2006.285.15:49:40.97#ibcon#read 6, iclass 24, count 2 2006.285.15:49:40.97#ibcon#end of sib2, iclass 24, count 2 2006.285.15:49:40.97#ibcon#*mode == 0, iclass 24, count 2 2006.285.15:49:40.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.15:49:40.97#ibcon#[25=AT02-06\r\n] 2006.285.15:49:40.97#ibcon#*before write, iclass 24, count 2 2006.285.15:49:40.97#ibcon#enter sib2, iclass 24, count 2 2006.285.15:49:40.97#ibcon#flushed, iclass 24, count 2 2006.285.15:49:40.97#ibcon#about to write, iclass 24, count 2 2006.285.15:49:40.97#ibcon#wrote, iclass 24, count 2 2006.285.15:49:40.97#ibcon#about to read 3, iclass 24, count 2 2006.285.15:49:41.00#ibcon#read 3, iclass 24, count 2 2006.285.15:49:41.00#ibcon#about to read 4, iclass 24, count 2 2006.285.15:49:41.00#ibcon#read 4, iclass 24, count 2 2006.285.15:49:41.00#ibcon#about to read 5, iclass 24, count 2 2006.285.15:49:41.00#ibcon#read 5, iclass 24, count 2 2006.285.15:49:41.00#ibcon#about to read 6, iclass 24, count 2 2006.285.15:49:41.00#ibcon#read 6, iclass 24, count 2 2006.285.15:49:41.00#ibcon#end of sib2, iclass 24, count 2 2006.285.15:49:41.00#ibcon#*after write, iclass 24, count 2 2006.285.15:49:41.00#ibcon#*before return 0, iclass 24, count 2 2006.285.15:49:41.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:49:41.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:49:41.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.15:49:41.00#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:41.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:49:41.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:49:41.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:49:41.12#ibcon#enter wrdev, iclass 24, count 0 2006.285.15:49:41.12#ibcon#first serial, iclass 24, count 0 2006.285.15:49:41.12#ibcon#enter sib2, iclass 24, count 0 2006.285.15:49:41.12#ibcon#flushed, iclass 24, count 0 2006.285.15:49:41.12#ibcon#about to write, iclass 24, count 0 2006.285.15:49:41.12#ibcon#wrote, iclass 24, count 0 2006.285.15:49:41.12#ibcon#about to read 3, iclass 24, count 0 2006.285.15:49:41.14#ibcon#read 3, iclass 24, count 0 2006.285.15:49:41.14#ibcon#about to read 4, iclass 24, count 0 2006.285.15:49:41.14#ibcon#read 4, iclass 24, count 0 2006.285.15:49:41.14#ibcon#about to read 5, iclass 24, count 0 2006.285.15:49:41.14#ibcon#read 5, iclass 24, count 0 2006.285.15:49:41.14#ibcon#about to read 6, iclass 24, count 0 2006.285.15:49:41.14#ibcon#read 6, iclass 24, count 0 2006.285.15:49:41.14#ibcon#end of sib2, iclass 24, count 0 2006.285.15:49:41.14#ibcon#*mode == 0, iclass 24, count 0 2006.285.15:49:41.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.15:49:41.14#ibcon#[25=USB\r\n] 2006.285.15:49:41.14#ibcon#*before write, iclass 24, count 0 2006.285.15:49:41.14#ibcon#enter sib2, iclass 24, count 0 2006.285.15:49:41.14#ibcon#flushed, iclass 24, count 0 2006.285.15:49:41.14#ibcon#about to write, iclass 24, count 0 2006.285.15:49:41.14#ibcon#wrote, iclass 24, count 0 2006.285.15:49:41.14#ibcon#about to read 3, iclass 24, count 0 2006.285.15:49:41.17#ibcon#read 3, iclass 24, count 0 2006.285.15:49:41.17#ibcon#about to read 4, iclass 24, count 0 2006.285.15:49:41.17#ibcon#read 4, iclass 24, count 0 2006.285.15:49:41.17#ibcon#about to read 5, iclass 24, count 0 2006.285.15:49:41.17#ibcon#read 5, iclass 24, count 0 2006.285.15:49:41.17#ibcon#about to read 6, iclass 24, count 0 2006.285.15:49:41.17#ibcon#read 6, iclass 24, count 0 2006.285.15:49:41.17#ibcon#end of sib2, iclass 24, count 0 2006.285.15:49:41.17#ibcon#*after write, iclass 24, count 0 2006.285.15:49:41.17#ibcon#*before return 0, iclass 24, count 0 2006.285.15:49:41.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:49:41.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:49:41.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.15:49:41.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.15:49:41.17$vck44/valo=3,564.99 2006.285.15:49:41.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.15:49:41.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.15:49:41.17#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:41.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:49:41.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:49:41.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:49:41.17#ibcon#enter wrdev, iclass 26, count 0 2006.285.15:49:41.17#ibcon#first serial, iclass 26, count 0 2006.285.15:49:41.17#ibcon#enter sib2, iclass 26, count 0 2006.285.15:49:41.17#ibcon#flushed, iclass 26, count 0 2006.285.15:49:41.17#ibcon#about to write, iclass 26, count 0 2006.285.15:49:41.17#ibcon#wrote, iclass 26, count 0 2006.285.15:49:41.17#ibcon#about to read 3, iclass 26, count 0 2006.285.15:49:41.66#ibcon#read 3, iclass 26, count 0 2006.285.15:49:41.66#ibcon#about to read 4, iclass 26, count 0 2006.285.15:49:41.66#ibcon#read 4, iclass 26, count 0 2006.285.15:49:41.66#ibcon#about to read 5, iclass 26, count 0 2006.285.15:49:41.66#ibcon#read 5, iclass 26, count 0 2006.285.15:49:41.66#ibcon#about to read 6, iclass 26, count 0 2006.285.15:49:41.66#ibcon#read 6, iclass 26, count 0 2006.285.15:49:41.66#ibcon#end of sib2, iclass 26, count 0 2006.285.15:49:41.66#ibcon#*mode == 0, iclass 26, count 0 2006.285.15:49:41.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.15:49:41.66#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.15:49:41.66#ibcon#*before write, iclass 26, count 0 2006.285.15:49:41.66#ibcon#enter sib2, iclass 26, count 0 2006.285.15:49:41.66#ibcon#flushed, iclass 26, count 0 2006.285.15:49:41.66#ibcon#about to write, iclass 26, count 0 2006.285.15:49:41.66#ibcon#wrote, iclass 26, count 0 2006.285.15:49:41.66#ibcon#about to read 3, iclass 26, count 0 2006.285.15:49:41.71#ibcon#read 3, iclass 26, count 0 2006.285.15:49:41.71#ibcon#about to read 4, iclass 26, count 0 2006.285.15:49:41.71#ibcon#read 4, iclass 26, count 0 2006.285.15:49:41.71#ibcon#about to read 5, iclass 26, count 0 2006.285.15:49:41.71#ibcon#read 5, iclass 26, count 0 2006.285.15:49:41.71#ibcon#about to read 6, iclass 26, count 0 2006.285.15:49:41.71#ibcon#read 6, iclass 26, count 0 2006.285.15:49:41.71#ibcon#end of sib2, iclass 26, count 0 2006.285.15:49:41.71#ibcon#*after write, iclass 26, count 0 2006.285.15:49:41.71#ibcon#*before return 0, iclass 26, count 0 2006.285.15:49:41.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:49:41.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:49:41.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.15:49:41.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.15:49:41.71$vck44/va=3,7 2006.285.15:49:41.71#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.15:49:41.71#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.15:49:41.71#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:41.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:49:41.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:49:41.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:49:41.71#ibcon#enter wrdev, iclass 28, count 2 2006.285.15:49:41.71#ibcon#first serial, iclass 28, count 2 2006.285.15:49:41.71#ibcon#enter sib2, iclass 28, count 2 2006.285.15:49:41.71#ibcon#flushed, iclass 28, count 2 2006.285.15:49:41.71#ibcon#about to write, iclass 28, count 2 2006.285.15:49:41.71#ibcon#wrote, iclass 28, count 2 2006.285.15:49:41.71#ibcon#about to read 3, iclass 28, count 2 2006.285.15:49:41.73#ibcon#read 3, iclass 28, count 2 2006.285.15:49:41.73#ibcon#about to read 4, iclass 28, count 2 2006.285.15:49:41.73#ibcon#read 4, iclass 28, count 2 2006.285.15:49:41.73#ibcon#about to read 5, iclass 28, count 2 2006.285.15:49:41.73#ibcon#read 5, iclass 28, count 2 2006.285.15:49:41.73#ibcon#about to read 6, iclass 28, count 2 2006.285.15:49:41.73#ibcon#read 6, iclass 28, count 2 2006.285.15:49:41.73#ibcon#end of sib2, iclass 28, count 2 2006.285.15:49:41.73#ibcon#*mode == 0, iclass 28, count 2 2006.285.15:49:41.73#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.15:49:41.73#ibcon#[25=AT03-07\r\n] 2006.285.15:49:41.73#ibcon#*before write, iclass 28, count 2 2006.285.15:49:41.73#ibcon#enter sib2, iclass 28, count 2 2006.285.15:49:41.73#ibcon#flushed, iclass 28, count 2 2006.285.15:49:41.73#ibcon#about to write, iclass 28, count 2 2006.285.15:49:41.73#ibcon#wrote, iclass 28, count 2 2006.285.15:49:41.73#ibcon#about to read 3, iclass 28, count 2 2006.285.15:49:41.76#ibcon#read 3, iclass 28, count 2 2006.285.15:49:41.76#ibcon#about to read 4, iclass 28, count 2 2006.285.15:49:41.76#ibcon#read 4, iclass 28, count 2 2006.285.15:49:41.76#ibcon#about to read 5, iclass 28, count 2 2006.285.15:49:41.76#ibcon#read 5, iclass 28, count 2 2006.285.15:49:41.76#ibcon#about to read 6, iclass 28, count 2 2006.285.15:49:41.76#ibcon#read 6, iclass 28, count 2 2006.285.15:49:41.76#ibcon#end of sib2, iclass 28, count 2 2006.285.15:49:41.76#ibcon#*after write, iclass 28, count 2 2006.285.15:49:41.76#ibcon#*before return 0, iclass 28, count 2 2006.285.15:49:41.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:49:41.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:49:41.76#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.15:49:41.76#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:41.76#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:49:41.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:49:41.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:49:41.88#ibcon#enter wrdev, iclass 28, count 0 2006.285.15:49:41.88#ibcon#first serial, iclass 28, count 0 2006.285.15:49:41.88#ibcon#enter sib2, iclass 28, count 0 2006.285.15:49:41.88#ibcon#flushed, iclass 28, count 0 2006.285.15:49:41.88#ibcon#about to write, iclass 28, count 0 2006.285.15:49:41.88#ibcon#wrote, iclass 28, count 0 2006.285.15:49:41.88#ibcon#about to read 3, iclass 28, count 0 2006.285.15:49:41.90#ibcon#read 3, iclass 28, count 0 2006.285.15:49:41.90#ibcon#about to read 4, iclass 28, count 0 2006.285.15:49:41.90#ibcon#read 4, iclass 28, count 0 2006.285.15:49:41.90#ibcon#about to read 5, iclass 28, count 0 2006.285.15:49:41.90#ibcon#read 5, iclass 28, count 0 2006.285.15:49:41.90#ibcon#about to read 6, iclass 28, count 0 2006.285.15:49:41.90#ibcon#read 6, iclass 28, count 0 2006.285.15:49:41.90#ibcon#end of sib2, iclass 28, count 0 2006.285.15:49:41.90#ibcon#*mode == 0, iclass 28, count 0 2006.285.15:49:41.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.15:49:41.90#ibcon#[25=USB\r\n] 2006.285.15:49:41.90#ibcon#*before write, iclass 28, count 0 2006.285.15:49:41.90#ibcon#enter sib2, iclass 28, count 0 2006.285.15:49:41.90#ibcon#flushed, iclass 28, count 0 2006.285.15:49:41.90#ibcon#about to write, iclass 28, count 0 2006.285.15:49:41.90#ibcon#wrote, iclass 28, count 0 2006.285.15:49:41.90#ibcon#about to read 3, iclass 28, count 0 2006.285.15:49:41.93#ibcon#read 3, iclass 28, count 0 2006.285.15:49:41.93#ibcon#about to read 4, iclass 28, count 0 2006.285.15:49:41.93#ibcon#read 4, iclass 28, count 0 2006.285.15:49:41.93#ibcon#about to read 5, iclass 28, count 0 2006.285.15:49:41.93#ibcon#read 5, iclass 28, count 0 2006.285.15:49:41.93#ibcon#about to read 6, iclass 28, count 0 2006.285.15:49:41.93#ibcon#read 6, iclass 28, count 0 2006.285.15:49:41.93#ibcon#end of sib2, iclass 28, count 0 2006.285.15:49:41.93#ibcon#*after write, iclass 28, count 0 2006.285.15:49:41.93#ibcon#*before return 0, iclass 28, count 0 2006.285.15:49:41.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:49:41.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:49:41.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.15:49:41.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.15:49:41.93$vck44/valo=4,624.99 2006.285.15:49:41.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.15:49:41.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.15:49:41.93#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:41.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:49:41.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:49:41.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:49:41.93#ibcon#enter wrdev, iclass 30, count 0 2006.285.15:49:41.93#ibcon#first serial, iclass 30, count 0 2006.285.15:49:41.93#ibcon#enter sib2, iclass 30, count 0 2006.285.15:49:41.93#ibcon#flushed, iclass 30, count 0 2006.285.15:49:41.93#ibcon#about to write, iclass 30, count 0 2006.285.15:49:41.93#ibcon#wrote, iclass 30, count 0 2006.285.15:49:41.93#ibcon#about to read 3, iclass 30, count 0 2006.285.15:49:41.95#ibcon#read 3, iclass 30, count 0 2006.285.15:49:42.20#ibcon#about to read 4, iclass 30, count 0 2006.285.15:49:42.20#ibcon#read 4, iclass 30, count 0 2006.285.15:49:42.20#ibcon#about to read 5, iclass 30, count 0 2006.285.15:49:42.20#ibcon#read 5, iclass 30, count 0 2006.285.15:49:42.20#ibcon#about to read 6, iclass 30, count 0 2006.285.15:49:42.20#ibcon#read 6, iclass 30, count 0 2006.285.15:49:42.20#ibcon#end of sib2, iclass 30, count 0 2006.285.15:49:42.20#ibcon#*mode == 0, iclass 30, count 0 2006.285.15:49:42.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.15:49:42.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.15:49:42.20#ibcon#*before write, iclass 30, count 0 2006.285.15:49:42.20#ibcon#enter sib2, iclass 30, count 0 2006.285.15:49:42.20#ibcon#flushed, iclass 30, count 0 2006.285.15:49:42.20#ibcon#about to write, iclass 30, count 0 2006.285.15:49:42.20#ibcon#wrote, iclass 30, count 0 2006.285.15:49:42.20#ibcon#about to read 3, iclass 30, count 0 2006.285.15:49:42.25#ibcon#read 3, iclass 30, count 0 2006.285.15:49:42.25#ibcon#about to read 4, iclass 30, count 0 2006.285.15:49:42.25#ibcon#read 4, iclass 30, count 0 2006.285.15:49:42.25#ibcon#about to read 5, iclass 30, count 0 2006.285.15:49:42.25#ibcon#read 5, iclass 30, count 0 2006.285.15:49:42.25#ibcon#about to read 6, iclass 30, count 0 2006.285.15:49:42.25#ibcon#read 6, iclass 30, count 0 2006.285.15:49:42.25#ibcon#end of sib2, iclass 30, count 0 2006.285.15:49:42.25#ibcon#*after write, iclass 30, count 0 2006.285.15:49:42.25#ibcon#*before return 0, iclass 30, count 0 2006.285.15:49:42.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:49:42.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:49:42.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.15:49:42.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.15:49:42.25$vck44/va=4,6 2006.285.15:49:42.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.15:49:42.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.15:49:42.25#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:42.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:49:42.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:49:42.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:49:42.25#ibcon#enter wrdev, iclass 32, count 2 2006.285.15:49:42.25#ibcon#first serial, iclass 32, count 2 2006.285.15:49:42.25#ibcon#enter sib2, iclass 32, count 2 2006.285.15:49:42.25#ibcon#flushed, iclass 32, count 2 2006.285.15:49:42.25#ibcon#about to write, iclass 32, count 2 2006.285.15:49:42.25#ibcon#wrote, iclass 32, count 2 2006.285.15:49:42.25#ibcon#about to read 3, iclass 32, count 2 2006.285.15:49:42.27#ibcon#read 3, iclass 32, count 2 2006.285.15:49:42.27#ibcon#about to read 4, iclass 32, count 2 2006.285.15:49:42.27#ibcon#read 4, iclass 32, count 2 2006.285.15:49:42.27#ibcon#about to read 5, iclass 32, count 2 2006.285.15:49:42.27#ibcon#read 5, iclass 32, count 2 2006.285.15:49:42.27#ibcon#about to read 6, iclass 32, count 2 2006.285.15:49:42.27#ibcon#read 6, iclass 32, count 2 2006.285.15:49:42.27#ibcon#end of sib2, iclass 32, count 2 2006.285.15:49:42.27#ibcon#*mode == 0, iclass 32, count 2 2006.285.15:49:42.27#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.15:49:42.27#ibcon#[25=AT04-06\r\n] 2006.285.15:49:42.27#ibcon#*before write, iclass 32, count 2 2006.285.15:49:42.27#ibcon#enter sib2, iclass 32, count 2 2006.285.15:49:42.27#ibcon#flushed, iclass 32, count 2 2006.285.15:49:42.27#ibcon#about to write, iclass 32, count 2 2006.285.15:49:42.27#ibcon#wrote, iclass 32, count 2 2006.285.15:49:42.27#ibcon#about to read 3, iclass 32, count 2 2006.285.15:49:42.30#ibcon#read 3, iclass 32, count 2 2006.285.15:49:42.30#ibcon#about to read 4, iclass 32, count 2 2006.285.15:49:42.30#ibcon#read 4, iclass 32, count 2 2006.285.15:49:42.30#ibcon#about to read 5, iclass 32, count 2 2006.285.15:49:42.30#ibcon#read 5, iclass 32, count 2 2006.285.15:49:42.30#ibcon#about to read 6, iclass 32, count 2 2006.285.15:49:42.30#ibcon#read 6, iclass 32, count 2 2006.285.15:49:42.30#ibcon#end of sib2, iclass 32, count 2 2006.285.15:49:42.30#ibcon#*after write, iclass 32, count 2 2006.285.15:49:42.30#ibcon#*before return 0, iclass 32, count 2 2006.285.15:49:42.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:49:42.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:49:42.30#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.15:49:42.30#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:42.30#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:49:42.42#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:49:42.42#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:49:42.42#ibcon#enter wrdev, iclass 32, count 0 2006.285.15:49:42.42#ibcon#first serial, iclass 32, count 0 2006.285.15:49:42.42#ibcon#enter sib2, iclass 32, count 0 2006.285.15:49:42.42#ibcon#flushed, iclass 32, count 0 2006.285.15:49:42.42#ibcon#about to write, iclass 32, count 0 2006.285.15:49:42.42#ibcon#wrote, iclass 32, count 0 2006.285.15:49:42.42#ibcon#about to read 3, iclass 32, count 0 2006.285.15:49:42.44#ibcon#read 3, iclass 32, count 0 2006.285.15:49:42.44#ibcon#about to read 4, iclass 32, count 0 2006.285.15:49:42.44#ibcon#read 4, iclass 32, count 0 2006.285.15:49:42.44#ibcon#about to read 5, iclass 32, count 0 2006.285.15:49:42.44#ibcon#read 5, iclass 32, count 0 2006.285.15:49:42.44#ibcon#about to read 6, iclass 32, count 0 2006.285.15:49:42.44#ibcon#read 6, iclass 32, count 0 2006.285.15:49:42.44#ibcon#end of sib2, iclass 32, count 0 2006.285.15:49:42.44#ibcon#*mode == 0, iclass 32, count 0 2006.285.15:49:42.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.15:49:42.44#ibcon#[25=USB\r\n] 2006.285.15:49:42.44#ibcon#*before write, iclass 32, count 0 2006.285.15:49:42.44#ibcon#enter sib2, iclass 32, count 0 2006.285.15:49:42.44#ibcon#flushed, iclass 32, count 0 2006.285.15:49:42.44#ibcon#about to write, iclass 32, count 0 2006.285.15:49:42.44#ibcon#wrote, iclass 32, count 0 2006.285.15:49:42.44#ibcon#about to read 3, iclass 32, count 0 2006.285.15:49:42.47#ibcon#read 3, iclass 32, count 0 2006.285.15:49:42.47#ibcon#about to read 4, iclass 32, count 0 2006.285.15:49:42.47#ibcon#read 4, iclass 32, count 0 2006.285.15:49:42.47#ibcon#about to read 5, iclass 32, count 0 2006.285.15:49:42.47#ibcon#read 5, iclass 32, count 0 2006.285.15:49:42.47#ibcon#about to read 6, iclass 32, count 0 2006.285.15:49:42.47#ibcon#read 6, iclass 32, count 0 2006.285.15:49:42.47#ibcon#end of sib2, iclass 32, count 0 2006.285.15:49:42.47#ibcon#*after write, iclass 32, count 0 2006.285.15:49:42.47#ibcon#*before return 0, iclass 32, count 0 2006.285.15:49:42.47#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:49:42.47#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:49:42.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.15:49:42.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.15:49:42.47$vck44/valo=5,734.99 2006.285.15:49:42.47#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.15:49:42.47#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.15:49:42.47#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:42.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:49:42.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:49:42.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:49:42.47#ibcon#enter wrdev, iclass 34, count 0 2006.285.15:49:42.47#ibcon#first serial, iclass 34, count 0 2006.285.15:49:42.47#ibcon#enter sib2, iclass 34, count 0 2006.285.15:49:42.47#ibcon#flushed, iclass 34, count 0 2006.285.15:49:42.47#ibcon#about to write, iclass 34, count 0 2006.285.15:49:42.47#ibcon#wrote, iclass 34, count 0 2006.285.15:49:42.47#ibcon#about to read 3, iclass 34, count 0 2006.285.15:49:42.49#ibcon#read 3, iclass 34, count 0 2006.285.15:49:42.49#ibcon#about to read 4, iclass 34, count 0 2006.285.15:49:42.49#ibcon#read 4, iclass 34, count 0 2006.285.15:49:42.49#ibcon#about to read 5, iclass 34, count 0 2006.285.15:49:42.49#ibcon#read 5, iclass 34, count 0 2006.285.15:49:42.49#ibcon#about to read 6, iclass 34, count 0 2006.285.15:49:42.49#ibcon#read 6, iclass 34, count 0 2006.285.15:49:42.49#ibcon#end of sib2, iclass 34, count 0 2006.285.15:49:42.49#ibcon#*mode == 0, iclass 34, count 0 2006.285.15:49:42.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.15:49:42.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.15:49:42.49#ibcon#*before write, iclass 34, count 0 2006.285.15:49:42.49#ibcon#enter sib2, iclass 34, count 0 2006.285.15:49:42.49#ibcon#flushed, iclass 34, count 0 2006.285.15:49:42.49#ibcon#about to write, iclass 34, count 0 2006.285.15:49:42.49#ibcon#wrote, iclass 34, count 0 2006.285.15:49:42.49#ibcon#about to read 3, iclass 34, count 0 2006.285.15:49:42.53#ibcon#read 3, iclass 34, count 0 2006.285.15:49:42.53#ibcon#about to read 4, iclass 34, count 0 2006.285.15:49:42.53#ibcon#read 4, iclass 34, count 0 2006.285.15:49:42.53#ibcon#about to read 5, iclass 34, count 0 2006.285.15:49:42.53#ibcon#read 5, iclass 34, count 0 2006.285.15:49:42.53#ibcon#about to read 6, iclass 34, count 0 2006.285.15:49:42.53#ibcon#read 6, iclass 34, count 0 2006.285.15:49:42.53#ibcon#end of sib2, iclass 34, count 0 2006.285.15:49:42.53#ibcon#*after write, iclass 34, count 0 2006.285.15:49:42.53#ibcon#*before return 0, iclass 34, count 0 2006.285.15:49:42.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:49:42.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:49:42.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.15:49:42.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.15:49:42.53$vck44/va=5,3 2006.285.15:49:42.53#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.15:49:42.53#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.15:49:42.53#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:42.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:49:42.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:49:42.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:49:42.59#ibcon#enter wrdev, iclass 36, count 2 2006.285.15:49:42.59#ibcon#first serial, iclass 36, count 2 2006.285.15:49:42.59#ibcon#enter sib2, iclass 36, count 2 2006.285.15:49:42.59#ibcon#flushed, iclass 36, count 2 2006.285.15:49:42.59#ibcon#about to write, iclass 36, count 2 2006.285.15:49:42.59#ibcon#wrote, iclass 36, count 2 2006.285.15:49:42.59#ibcon#about to read 3, iclass 36, count 2 2006.285.15:49:42.61#ibcon#read 3, iclass 36, count 2 2006.285.15:49:42.61#ibcon#about to read 4, iclass 36, count 2 2006.285.15:49:42.61#ibcon#read 4, iclass 36, count 2 2006.285.15:49:42.61#ibcon#about to read 5, iclass 36, count 2 2006.285.15:49:42.61#ibcon#read 5, iclass 36, count 2 2006.285.15:49:42.61#ibcon#about to read 6, iclass 36, count 2 2006.285.15:49:42.61#ibcon#read 6, iclass 36, count 2 2006.285.15:49:42.61#ibcon#end of sib2, iclass 36, count 2 2006.285.15:49:42.61#ibcon#*mode == 0, iclass 36, count 2 2006.285.15:49:42.61#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.15:49:42.61#ibcon#[25=AT05-03\r\n] 2006.285.15:49:42.61#ibcon#*before write, iclass 36, count 2 2006.285.15:49:42.61#ibcon#enter sib2, iclass 36, count 2 2006.285.15:49:42.61#ibcon#flushed, iclass 36, count 2 2006.285.15:49:42.61#ibcon#about to write, iclass 36, count 2 2006.285.15:49:42.61#ibcon#wrote, iclass 36, count 2 2006.285.15:49:42.61#ibcon#about to read 3, iclass 36, count 2 2006.285.15:49:42.64#ibcon#read 3, iclass 36, count 2 2006.285.15:49:42.64#ibcon#about to read 4, iclass 36, count 2 2006.285.15:49:42.64#ibcon#read 4, iclass 36, count 2 2006.285.15:49:42.64#ibcon#about to read 5, iclass 36, count 2 2006.285.15:49:42.64#ibcon#read 5, iclass 36, count 2 2006.285.15:49:42.64#ibcon#about to read 6, iclass 36, count 2 2006.285.15:49:42.64#ibcon#read 6, iclass 36, count 2 2006.285.15:49:42.64#ibcon#end of sib2, iclass 36, count 2 2006.285.15:49:42.64#ibcon#*after write, iclass 36, count 2 2006.285.15:49:42.64#ibcon#*before return 0, iclass 36, count 2 2006.285.15:49:42.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:49:42.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:49:42.64#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.15:49:42.64#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:42.64#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:49:42.76#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:49:42.76#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:49:42.76#ibcon#enter wrdev, iclass 36, count 0 2006.285.15:49:42.76#ibcon#first serial, iclass 36, count 0 2006.285.15:49:42.76#ibcon#enter sib2, iclass 36, count 0 2006.285.15:49:42.76#ibcon#flushed, iclass 36, count 0 2006.285.15:49:42.76#ibcon#about to write, iclass 36, count 0 2006.285.15:49:42.76#ibcon#wrote, iclass 36, count 0 2006.285.15:49:42.76#ibcon#about to read 3, iclass 36, count 0 2006.285.15:49:42.78#ibcon#read 3, iclass 36, count 0 2006.285.15:49:42.78#ibcon#about to read 4, iclass 36, count 0 2006.285.15:49:42.78#ibcon#read 4, iclass 36, count 0 2006.285.15:49:42.78#ibcon#about to read 5, iclass 36, count 0 2006.285.15:49:42.78#ibcon#read 5, iclass 36, count 0 2006.285.15:49:42.78#ibcon#about to read 6, iclass 36, count 0 2006.285.15:49:42.78#ibcon#read 6, iclass 36, count 0 2006.285.15:49:42.78#ibcon#end of sib2, iclass 36, count 0 2006.285.15:49:42.78#ibcon#*mode == 0, iclass 36, count 0 2006.285.15:49:42.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.15:49:42.78#ibcon#[25=USB\r\n] 2006.285.15:49:42.78#ibcon#*before write, iclass 36, count 0 2006.285.15:49:42.78#ibcon#enter sib2, iclass 36, count 0 2006.285.15:49:42.78#ibcon#flushed, iclass 36, count 0 2006.285.15:49:42.78#ibcon#about to write, iclass 36, count 0 2006.285.15:49:42.78#ibcon#wrote, iclass 36, count 0 2006.285.15:49:42.78#ibcon#about to read 3, iclass 36, count 0 2006.285.15:49:42.81#ibcon#read 3, iclass 36, count 0 2006.285.15:49:42.81#ibcon#about to read 4, iclass 36, count 0 2006.285.15:49:42.81#ibcon#read 4, iclass 36, count 0 2006.285.15:49:42.81#ibcon#about to read 5, iclass 36, count 0 2006.285.15:49:42.81#ibcon#read 5, iclass 36, count 0 2006.285.15:49:42.81#ibcon#about to read 6, iclass 36, count 0 2006.285.15:49:42.81#ibcon#read 6, iclass 36, count 0 2006.285.15:49:42.81#ibcon#end of sib2, iclass 36, count 0 2006.285.15:49:42.81#ibcon#*after write, iclass 36, count 0 2006.285.15:49:42.81#ibcon#*before return 0, iclass 36, count 0 2006.285.15:49:42.81#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:49:42.81#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:49:42.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.15:49:42.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.15:49:42.81$vck44/valo=6,814.99 2006.285.15:49:42.81#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.15:49:42.81#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.15:49:42.81#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:42.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:49:42.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:49:42.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:49:42.81#ibcon#enter wrdev, iclass 38, count 0 2006.285.15:49:42.81#ibcon#first serial, iclass 38, count 0 2006.285.15:49:42.81#ibcon#enter sib2, iclass 38, count 0 2006.285.15:49:42.81#ibcon#flushed, iclass 38, count 0 2006.285.15:49:42.81#ibcon#about to write, iclass 38, count 0 2006.285.15:49:42.81#ibcon#wrote, iclass 38, count 0 2006.285.15:49:42.81#ibcon#about to read 3, iclass 38, count 0 2006.285.15:49:42.83#ibcon#read 3, iclass 38, count 0 2006.285.15:49:42.83#ibcon#about to read 4, iclass 38, count 0 2006.285.15:49:42.83#ibcon#read 4, iclass 38, count 0 2006.285.15:49:42.83#ibcon#about to read 5, iclass 38, count 0 2006.285.15:49:42.83#ibcon#read 5, iclass 38, count 0 2006.285.15:49:42.83#ibcon#about to read 6, iclass 38, count 0 2006.285.15:49:42.83#ibcon#read 6, iclass 38, count 0 2006.285.15:49:42.83#ibcon#end of sib2, iclass 38, count 0 2006.285.15:49:42.83#ibcon#*mode == 0, iclass 38, count 0 2006.285.15:49:42.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.15:49:42.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.15:49:42.83#ibcon#*before write, iclass 38, count 0 2006.285.15:49:42.83#ibcon#enter sib2, iclass 38, count 0 2006.285.15:49:42.83#ibcon#flushed, iclass 38, count 0 2006.285.15:49:42.83#ibcon#about to write, iclass 38, count 0 2006.285.15:49:42.83#ibcon#wrote, iclass 38, count 0 2006.285.15:49:42.83#ibcon#about to read 3, iclass 38, count 0 2006.285.15:49:42.87#ibcon#read 3, iclass 38, count 0 2006.285.15:49:42.87#ibcon#about to read 4, iclass 38, count 0 2006.285.15:49:42.87#ibcon#read 4, iclass 38, count 0 2006.285.15:49:42.87#ibcon#about to read 5, iclass 38, count 0 2006.285.15:49:42.87#ibcon#read 5, iclass 38, count 0 2006.285.15:49:42.87#ibcon#about to read 6, iclass 38, count 0 2006.285.15:49:42.87#ibcon#read 6, iclass 38, count 0 2006.285.15:49:42.87#ibcon#end of sib2, iclass 38, count 0 2006.285.15:49:42.87#ibcon#*after write, iclass 38, count 0 2006.285.15:49:42.87#ibcon#*before return 0, iclass 38, count 0 2006.285.15:49:42.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:49:42.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:49:42.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.15:49:42.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.15:49:42.87$vck44/va=6,4 2006.285.15:49:42.87#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.15:49:42.87#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.15:49:42.87#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:42.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:49:42.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:49:42.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:49:42.93#ibcon#enter wrdev, iclass 40, count 2 2006.285.15:49:42.93#ibcon#first serial, iclass 40, count 2 2006.285.15:49:42.93#ibcon#enter sib2, iclass 40, count 2 2006.285.15:49:42.93#ibcon#flushed, iclass 40, count 2 2006.285.15:49:42.93#ibcon#about to write, iclass 40, count 2 2006.285.15:49:42.93#ibcon#wrote, iclass 40, count 2 2006.285.15:49:42.93#ibcon#about to read 3, iclass 40, count 2 2006.285.15:49:42.95#ibcon#read 3, iclass 40, count 2 2006.285.15:49:42.95#ibcon#about to read 4, iclass 40, count 2 2006.285.15:49:42.95#ibcon#read 4, iclass 40, count 2 2006.285.15:49:42.95#ibcon#about to read 5, iclass 40, count 2 2006.285.15:49:42.95#ibcon#read 5, iclass 40, count 2 2006.285.15:49:42.95#ibcon#about to read 6, iclass 40, count 2 2006.285.15:49:42.95#ibcon#read 6, iclass 40, count 2 2006.285.15:49:42.95#ibcon#end of sib2, iclass 40, count 2 2006.285.15:49:42.95#ibcon#*mode == 0, iclass 40, count 2 2006.285.15:49:42.95#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.15:49:42.95#ibcon#[25=AT06-04\r\n] 2006.285.15:49:42.95#ibcon#*before write, iclass 40, count 2 2006.285.15:49:42.95#ibcon#enter sib2, iclass 40, count 2 2006.285.15:49:42.95#ibcon#flushed, iclass 40, count 2 2006.285.15:49:42.95#ibcon#about to write, iclass 40, count 2 2006.285.15:49:42.95#ibcon#wrote, iclass 40, count 2 2006.285.15:49:42.95#ibcon#about to read 3, iclass 40, count 2 2006.285.15:49:42.98#ibcon#read 3, iclass 40, count 2 2006.285.15:49:42.98#ibcon#about to read 4, iclass 40, count 2 2006.285.15:49:42.98#ibcon#read 4, iclass 40, count 2 2006.285.15:49:42.98#ibcon#about to read 5, iclass 40, count 2 2006.285.15:49:42.98#ibcon#read 5, iclass 40, count 2 2006.285.15:49:42.98#ibcon#about to read 6, iclass 40, count 2 2006.285.15:49:42.98#ibcon#read 6, iclass 40, count 2 2006.285.15:49:42.98#ibcon#end of sib2, iclass 40, count 2 2006.285.15:49:42.98#ibcon#*after write, iclass 40, count 2 2006.285.15:49:42.98#ibcon#*before return 0, iclass 40, count 2 2006.285.15:49:42.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:49:42.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:49:42.98#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.15:49:42.98#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:42.98#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:49:43.10#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:49:43.10#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:49:43.10#ibcon#enter wrdev, iclass 40, count 0 2006.285.15:49:43.10#ibcon#first serial, iclass 40, count 0 2006.285.15:49:43.10#ibcon#enter sib2, iclass 40, count 0 2006.285.15:49:43.10#ibcon#flushed, iclass 40, count 0 2006.285.15:49:43.10#ibcon#about to write, iclass 40, count 0 2006.285.15:49:43.10#ibcon#wrote, iclass 40, count 0 2006.285.15:49:43.10#ibcon#about to read 3, iclass 40, count 0 2006.285.15:49:43.12#ibcon#read 3, iclass 40, count 0 2006.285.15:49:43.12#ibcon#about to read 4, iclass 40, count 0 2006.285.15:49:43.12#ibcon#read 4, iclass 40, count 0 2006.285.15:49:43.12#ibcon#about to read 5, iclass 40, count 0 2006.285.15:49:43.12#ibcon#read 5, iclass 40, count 0 2006.285.15:49:43.12#ibcon#about to read 6, iclass 40, count 0 2006.285.15:49:43.12#ibcon#read 6, iclass 40, count 0 2006.285.15:49:43.12#ibcon#end of sib2, iclass 40, count 0 2006.285.15:49:43.12#ibcon#*mode == 0, iclass 40, count 0 2006.285.15:49:43.12#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.15:49:43.12#ibcon#[25=USB\r\n] 2006.285.15:49:43.12#ibcon#*before write, iclass 40, count 0 2006.285.15:49:43.12#ibcon#enter sib2, iclass 40, count 0 2006.285.15:49:43.12#ibcon#flushed, iclass 40, count 0 2006.285.15:49:43.12#ibcon#about to write, iclass 40, count 0 2006.285.15:49:43.12#ibcon#wrote, iclass 40, count 0 2006.285.15:49:43.12#ibcon#about to read 3, iclass 40, count 0 2006.285.15:49:43.15#ibcon#read 3, iclass 40, count 0 2006.285.15:49:43.15#ibcon#about to read 4, iclass 40, count 0 2006.285.15:49:43.15#ibcon#read 4, iclass 40, count 0 2006.285.15:49:43.15#ibcon#about to read 5, iclass 40, count 0 2006.285.15:49:43.15#ibcon#read 5, iclass 40, count 0 2006.285.15:49:43.15#ibcon#about to read 6, iclass 40, count 0 2006.285.15:49:43.15#ibcon#read 6, iclass 40, count 0 2006.285.15:49:43.15#ibcon#end of sib2, iclass 40, count 0 2006.285.15:49:43.15#ibcon#*after write, iclass 40, count 0 2006.285.15:49:43.15#ibcon#*before return 0, iclass 40, count 0 2006.285.15:49:43.15#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:49:43.15#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:49:43.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.15:49:43.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.15:49:43.15$vck44/valo=7,864.99 2006.285.15:49:43.15#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.15:49:43.15#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.15:49:43.15#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:43.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:49:43.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:49:43.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:49:43.15#ibcon#enter wrdev, iclass 4, count 0 2006.285.15:49:43.15#ibcon#first serial, iclass 4, count 0 2006.285.15:49:43.15#ibcon#enter sib2, iclass 4, count 0 2006.285.15:49:43.31#ibcon#flushed, iclass 4, count 0 2006.285.15:49:43.31#ibcon#about to write, iclass 4, count 0 2006.285.15:49:43.31#ibcon#wrote, iclass 4, count 0 2006.285.15:49:43.31#ibcon#about to read 3, iclass 4, count 0 2006.285.15:49:43.33#ibcon#read 3, iclass 4, count 0 2006.285.15:49:43.33#ibcon#about to read 4, iclass 4, count 0 2006.285.15:49:43.33#ibcon#read 4, iclass 4, count 0 2006.285.15:49:43.33#ibcon#about to read 5, iclass 4, count 0 2006.285.15:49:43.33#ibcon#read 5, iclass 4, count 0 2006.285.15:49:43.33#ibcon#about to read 6, iclass 4, count 0 2006.285.15:49:43.33#ibcon#read 6, iclass 4, count 0 2006.285.15:49:43.33#ibcon#end of sib2, iclass 4, count 0 2006.285.15:49:43.33#ibcon#*mode == 0, iclass 4, count 0 2006.285.15:49:43.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.15:49:43.33#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.15:49:43.33#ibcon#*before write, iclass 4, count 0 2006.285.15:49:43.33#ibcon#enter sib2, iclass 4, count 0 2006.285.15:49:43.33#ibcon#flushed, iclass 4, count 0 2006.285.15:49:43.33#ibcon#about to write, iclass 4, count 0 2006.285.15:49:43.33#ibcon#wrote, iclass 4, count 0 2006.285.15:49:43.33#ibcon#about to read 3, iclass 4, count 0 2006.285.15:49:43.37#ibcon#read 3, iclass 4, count 0 2006.285.15:49:43.37#ibcon#about to read 4, iclass 4, count 0 2006.285.15:49:43.37#ibcon#read 4, iclass 4, count 0 2006.285.15:49:43.37#ibcon#about to read 5, iclass 4, count 0 2006.285.15:49:43.37#ibcon#read 5, iclass 4, count 0 2006.285.15:49:43.37#ibcon#about to read 6, iclass 4, count 0 2006.285.15:49:43.37#ibcon#read 6, iclass 4, count 0 2006.285.15:49:43.37#ibcon#end of sib2, iclass 4, count 0 2006.285.15:49:43.37#ibcon#*after write, iclass 4, count 0 2006.285.15:49:43.37#ibcon#*before return 0, iclass 4, count 0 2006.285.15:49:43.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:49:43.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:49:43.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.15:49:43.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.15:49:43.37$vck44/va=7,4 2006.285.15:49:43.37#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.15:49:43.37#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.15:49:43.37#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:43.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:49:43.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:49:43.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:49:43.37#ibcon#enter wrdev, iclass 6, count 2 2006.285.15:49:43.37#ibcon#first serial, iclass 6, count 2 2006.285.15:49:43.37#ibcon#enter sib2, iclass 6, count 2 2006.285.15:49:43.37#ibcon#flushed, iclass 6, count 2 2006.285.15:49:43.37#ibcon#about to write, iclass 6, count 2 2006.285.15:49:43.37#ibcon#wrote, iclass 6, count 2 2006.285.15:49:43.37#ibcon#about to read 3, iclass 6, count 2 2006.285.15:49:43.39#ibcon#read 3, iclass 6, count 2 2006.285.15:49:43.39#ibcon#about to read 4, iclass 6, count 2 2006.285.15:49:43.39#ibcon#read 4, iclass 6, count 2 2006.285.15:49:43.39#ibcon#about to read 5, iclass 6, count 2 2006.285.15:49:43.39#ibcon#read 5, iclass 6, count 2 2006.285.15:49:43.39#ibcon#about to read 6, iclass 6, count 2 2006.285.15:49:43.39#ibcon#read 6, iclass 6, count 2 2006.285.15:49:43.39#ibcon#end of sib2, iclass 6, count 2 2006.285.15:49:43.39#ibcon#*mode == 0, iclass 6, count 2 2006.285.15:49:43.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.15:49:43.39#ibcon#[25=AT07-04\r\n] 2006.285.15:49:43.39#ibcon#*before write, iclass 6, count 2 2006.285.15:49:43.39#ibcon#enter sib2, iclass 6, count 2 2006.285.15:49:43.39#ibcon#flushed, iclass 6, count 2 2006.285.15:49:43.39#ibcon#about to write, iclass 6, count 2 2006.285.15:49:43.39#ibcon#wrote, iclass 6, count 2 2006.285.15:49:43.39#ibcon#about to read 3, iclass 6, count 2 2006.285.15:49:43.42#ibcon#read 3, iclass 6, count 2 2006.285.15:49:43.42#ibcon#about to read 4, iclass 6, count 2 2006.285.15:49:43.42#ibcon#read 4, iclass 6, count 2 2006.285.15:49:43.42#ibcon#about to read 5, iclass 6, count 2 2006.285.15:49:43.42#ibcon#read 5, iclass 6, count 2 2006.285.15:49:43.42#ibcon#about to read 6, iclass 6, count 2 2006.285.15:49:43.42#ibcon#read 6, iclass 6, count 2 2006.285.15:49:43.42#ibcon#end of sib2, iclass 6, count 2 2006.285.15:49:43.42#ibcon#*after write, iclass 6, count 2 2006.285.15:49:43.42#ibcon#*before return 0, iclass 6, count 2 2006.285.15:49:43.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:49:43.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:49:43.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.15:49:43.42#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:43.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:49:43.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:49:43.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:49:43.54#ibcon#enter wrdev, iclass 6, count 0 2006.285.15:49:43.54#ibcon#first serial, iclass 6, count 0 2006.285.15:49:43.54#ibcon#enter sib2, iclass 6, count 0 2006.285.15:49:43.54#ibcon#flushed, iclass 6, count 0 2006.285.15:49:43.54#ibcon#about to write, iclass 6, count 0 2006.285.15:49:43.54#ibcon#wrote, iclass 6, count 0 2006.285.15:49:43.54#ibcon#about to read 3, iclass 6, count 0 2006.285.15:49:43.56#ibcon#read 3, iclass 6, count 0 2006.285.15:49:43.56#ibcon#about to read 4, iclass 6, count 0 2006.285.15:49:43.56#ibcon#read 4, iclass 6, count 0 2006.285.15:49:43.56#ibcon#about to read 5, iclass 6, count 0 2006.285.15:49:43.56#ibcon#read 5, iclass 6, count 0 2006.285.15:49:43.56#ibcon#about to read 6, iclass 6, count 0 2006.285.15:49:43.56#ibcon#read 6, iclass 6, count 0 2006.285.15:49:43.56#ibcon#end of sib2, iclass 6, count 0 2006.285.15:49:43.56#ibcon#*mode == 0, iclass 6, count 0 2006.285.15:49:43.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.15:49:43.56#ibcon#[25=USB\r\n] 2006.285.15:49:43.56#ibcon#*before write, iclass 6, count 0 2006.285.15:49:43.56#ibcon#enter sib2, iclass 6, count 0 2006.285.15:49:43.56#ibcon#flushed, iclass 6, count 0 2006.285.15:49:43.56#ibcon#about to write, iclass 6, count 0 2006.285.15:49:43.56#ibcon#wrote, iclass 6, count 0 2006.285.15:49:43.56#ibcon#about to read 3, iclass 6, count 0 2006.285.15:49:43.59#ibcon#read 3, iclass 6, count 0 2006.285.15:49:43.59#ibcon#about to read 4, iclass 6, count 0 2006.285.15:49:43.59#ibcon#read 4, iclass 6, count 0 2006.285.15:49:43.59#ibcon#about to read 5, iclass 6, count 0 2006.285.15:49:43.59#ibcon#read 5, iclass 6, count 0 2006.285.15:49:43.59#ibcon#about to read 6, iclass 6, count 0 2006.285.15:49:43.59#ibcon#read 6, iclass 6, count 0 2006.285.15:49:43.59#ibcon#end of sib2, iclass 6, count 0 2006.285.15:49:43.59#ibcon#*after write, iclass 6, count 0 2006.285.15:49:43.59#ibcon#*before return 0, iclass 6, count 0 2006.285.15:49:43.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:49:43.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:49:43.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.15:49:43.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.15:49:43.59$vck44/valo=8,884.99 2006.285.15:49:43.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.15:49:43.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.15:49:43.59#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:43.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:49:43.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:49:43.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:49:43.59#ibcon#enter wrdev, iclass 10, count 0 2006.285.15:49:43.59#ibcon#first serial, iclass 10, count 0 2006.285.15:49:43.59#ibcon#enter sib2, iclass 10, count 0 2006.285.15:49:43.59#ibcon#flushed, iclass 10, count 0 2006.285.15:49:43.59#ibcon#about to write, iclass 10, count 0 2006.285.15:49:43.59#ibcon#wrote, iclass 10, count 0 2006.285.15:49:43.59#ibcon#about to read 3, iclass 10, count 0 2006.285.15:49:43.61#ibcon#read 3, iclass 10, count 0 2006.285.15:49:43.61#ibcon#about to read 4, iclass 10, count 0 2006.285.15:49:43.61#ibcon#read 4, iclass 10, count 0 2006.285.15:49:43.61#ibcon#about to read 5, iclass 10, count 0 2006.285.15:49:43.61#ibcon#read 5, iclass 10, count 0 2006.285.15:49:43.61#ibcon#about to read 6, iclass 10, count 0 2006.285.15:49:43.61#ibcon#read 6, iclass 10, count 0 2006.285.15:49:43.61#ibcon#end of sib2, iclass 10, count 0 2006.285.15:49:43.61#ibcon#*mode == 0, iclass 10, count 0 2006.285.15:49:43.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.15:49:43.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.15:49:43.61#ibcon#*before write, iclass 10, count 0 2006.285.15:49:43.61#ibcon#enter sib2, iclass 10, count 0 2006.285.15:49:43.61#ibcon#flushed, iclass 10, count 0 2006.285.15:49:43.61#ibcon#about to write, iclass 10, count 0 2006.285.15:49:43.61#ibcon#wrote, iclass 10, count 0 2006.285.15:49:43.61#ibcon#about to read 3, iclass 10, count 0 2006.285.15:49:43.65#ibcon#read 3, iclass 10, count 0 2006.285.15:49:43.65#ibcon#about to read 4, iclass 10, count 0 2006.285.15:49:43.65#ibcon#read 4, iclass 10, count 0 2006.285.15:49:43.65#ibcon#about to read 5, iclass 10, count 0 2006.285.15:49:43.65#ibcon#read 5, iclass 10, count 0 2006.285.15:49:43.65#ibcon#about to read 6, iclass 10, count 0 2006.285.15:49:43.65#ibcon#read 6, iclass 10, count 0 2006.285.15:49:43.65#ibcon#end of sib2, iclass 10, count 0 2006.285.15:49:43.65#ibcon#*after write, iclass 10, count 0 2006.285.15:49:43.65#ibcon#*before return 0, iclass 10, count 0 2006.285.15:49:43.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:49:43.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:49:43.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.15:49:43.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.15:49:43.65$vck44/va=8,3 2006.285.15:49:43.65#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.15:49:43.65#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.15:49:43.65#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:43.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:49:43.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:49:43.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:49:43.71#ibcon#enter wrdev, iclass 12, count 2 2006.285.15:49:43.71#ibcon#first serial, iclass 12, count 2 2006.285.15:49:43.71#ibcon#enter sib2, iclass 12, count 2 2006.285.15:49:43.71#ibcon#flushed, iclass 12, count 2 2006.285.15:49:43.71#ibcon#about to write, iclass 12, count 2 2006.285.15:49:43.71#ibcon#wrote, iclass 12, count 2 2006.285.15:49:43.71#ibcon#about to read 3, iclass 12, count 2 2006.285.15:49:43.73#ibcon#read 3, iclass 12, count 2 2006.285.15:49:43.73#ibcon#about to read 4, iclass 12, count 2 2006.285.15:49:43.73#ibcon#read 4, iclass 12, count 2 2006.285.15:49:43.73#ibcon#about to read 5, iclass 12, count 2 2006.285.15:49:43.73#ibcon#read 5, iclass 12, count 2 2006.285.15:49:43.73#ibcon#about to read 6, iclass 12, count 2 2006.285.15:49:43.73#ibcon#read 6, iclass 12, count 2 2006.285.15:49:43.73#ibcon#end of sib2, iclass 12, count 2 2006.285.15:49:43.73#ibcon#*mode == 0, iclass 12, count 2 2006.285.15:49:43.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.15:49:43.73#ibcon#[25=AT08-03\r\n] 2006.285.15:49:43.73#ibcon#*before write, iclass 12, count 2 2006.285.15:49:43.73#ibcon#enter sib2, iclass 12, count 2 2006.285.15:49:43.73#ibcon#flushed, iclass 12, count 2 2006.285.15:49:43.73#ibcon#about to write, iclass 12, count 2 2006.285.15:49:43.73#ibcon#wrote, iclass 12, count 2 2006.285.15:49:43.73#ibcon#about to read 3, iclass 12, count 2 2006.285.15:49:43.76#ibcon#read 3, iclass 12, count 2 2006.285.15:49:43.76#ibcon#about to read 4, iclass 12, count 2 2006.285.15:49:43.76#ibcon#read 4, iclass 12, count 2 2006.285.15:49:43.76#ibcon#about to read 5, iclass 12, count 2 2006.285.15:49:43.76#ibcon#read 5, iclass 12, count 2 2006.285.15:49:43.76#ibcon#about to read 6, iclass 12, count 2 2006.285.15:49:43.76#ibcon#read 6, iclass 12, count 2 2006.285.15:49:43.76#ibcon#end of sib2, iclass 12, count 2 2006.285.15:49:43.76#ibcon#*after write, iclass 12, count 2 2006.285.15:49:43.76#ibcon#*before return 0, iclass 12, count 2 2006.285.15:49:43.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:49:43.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.15:49:43.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.15:49:43.76#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:43.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:49:43.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:49:43.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:49:43.88#ibcon#enter wrdev, iclass 12, count 0 2006.285.15:49:43.88#ibcon#first serial, iclass 12, count 0 2006.285.15:49:43.88#ibcon#enter sib2, iclass 12, count 0 2006.285.15:49:43.88#ibcon#flushed, iclass 12, count 0 2006.285.15:49:43.88#ibcon#about to write, iclass 12, count 0 2006.285.15:49:43.88#ibcon#wrote, iclass 12, count 0 2006.285.15:49:43.88#ibcon#about to read 3, iclass 12, count 0 2006.285.15:49:43.90#ibcon#read 3, iclass 12, count 0 2006.285.15:49:43.90#ibcon#about to read 4, iclass 12, count 0 2006.285.15:49:43.90#ibcon#read 4, iclass 12, count 0 2006.285.15:49:43.90#ibcon#about to read 5, iclass 12, count 0 2006.285.15:49:43.90#ibcon#read 5, iclass 12, count 0 2006.285.15:49:43.90#ibcon#about to read 6, iclass 12, count 0 2006.285.15:49:43.90#ibcon#read 6, iclass 12, count 0 2006.285.15:49:43.90#ibcon#end of sib2, iclass 12, count 0 2006.285.15:49:43.90#ibcon#*mode == 0, iclass 12, count 0 2006.285.15:49:43.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.15:49:43.90#ibcon#[25=USB\r\n] 2006.285.15:49:43.90#ibcon#*before write, iclass 12, count 0 2006.285.15:49:43.90#ibcon#enter sib2, iclass 12, count 0 2006.285.15:49:43.90#ibcon#flushed, iclass 12, count 0 2006.285.15:49:43.90#ibcon#about to write, iclass 12, count 0 2006.285.15:49:43.90#ibcon#wrote, iclass 12, count 0 2006.285.15:49:43.90#ibcon#about to read 3, iclass 12, count 0 2006.285.15:49:43.93#ibcon#read 3, iclass 12, count 0 2006.285.15:49:43.93#ibcon#about to read 4, iclass 12, count 0 2006.285.15:49:43.93#ibcon#read 4, iclass 12, count 0 2006.285.15:49:43.93#ibcon#about to read 5, iclass 12, count 0 2006.285.15:49:43.93#ibcon#read 5, iclass 12, count 0 2006.285.15:49:43.93#ibcon#about to read 6, iclass 12, count 0 2006.285.15:49:43.93#ibcon#read 6, iclass 12, count 0 2006.285.15:49:43.93#ibcon#end of sib2, iclass 12, count 0 2006.285.15:49:43.93#ibcon#*after write, iclass 12, count 0 2006.285.15:49:43.93#ibcon#*before return 0, iclass 12, count 0 2006.285.15:49:43.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:49:43.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.15:49:43.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.15:49:43.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.15:49:43.93$vck44/vblo=1,629.99 2006.285.15:49:43.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.15:49:43.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.15:49:43.93#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:43.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:49:43.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:49:43.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:49:43.93#ibcon#enter wrdev, iclass 14, count 0 2006.285.15:49:43.93#ibcon#first serial, iclass 14, count 0 2006.285.15:49:43.93#ibcon#enter sib2, iclass 14, count 0 2006.285.15:49:43.93#ibcon#flushed, iclass 14, count 0 2006.285.15:49:43.93#ibcon#about to write, iclass 14, count 0 2006.285.15:49:43.93#ibcon#wrote, iclass 14, count 0 2006.285.15:49:43.93#ibcon#about to read 3, iclass 14, count 0 2006.285.15:49:43.95#ibcon#read 3, iclass 14, count 0 2006.285.15:49:43.95#ibcon#about to read 4, iclass 14, count 0 2006.285.15:49:43.95#ibcon#read 4, iclass 14, count 0 2006.285.15:49:43.95#ibcon#about to read 5, iclass 14, count 0 2006.285.15:49:43.95#ibcon#read 5, iclass 14, count 0 2006.285.15:49:43.95#ibcon#about to read 6, iclass 14, count 0 2006.285.15:49:43.95#ibcon#read 6, iclass 14, count 0 2006.285.15:49:43.95#ibcon#end of sib2, iclass 14, count 0 2006.285.15:49:43.95#ibcon#*mode == 0, iclass 14, count 0 2006.285.15:49:43.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.15:49:43.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.15:49:43.95#ibcon#*before write, iclass 14, count 0 2006.285.15:49:43.95#ibcon#enter sib2, iclass 14, count 0 2006.285.15:49:43.95#ibcon#flushed, iclass 14, count 0 2006.285.15:49:43.95#ibcon#about to write, iclass 14, count 0 2006.285.15:49:43.95#ibcon#wrote, iclass 14, count 0 2006.285.15:49:43.95#ibcon#about to read 3, iclass 14, count 0 2006.285.15:49:43.99#ibcon#read 3, iclass 14, count 0 2006.285.15:49:43.99#ibcon#about to read 4, iclass 14, count 0 2006.285.15:49:43.99#ibcon#read 4, iclass 14, count 0 2006.285.15:49:43.99#ibcon#about to read 5, iclass 14, count 0 2006.285.15:49:43.99#ibcon#read 5, iclass 14, count 0 2006.285.15:49:43.99#ibcon#about to read 6, iclass 14, count 0 2006.285.15:49:43.99#ibcon#read 6, iclass 14, count 0 2006.285.15:49:43.99#ibcon#end of sib2, iclass 14, count 0 2006.285.15:49:43.99#ibcon#*after write, iclass 14, count 0 2006.285.15:49:43.99#ibcon#*before return 0, iclass 14, count 0 2006.285.15:49:43.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:49:43.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.15:49:43.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.15:49:43.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.15:49:43.99$vck44/vb=1,4 2006.285.15:49:43.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.15:49:43.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.15:49:43.99#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:43.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:49:43.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:49:43.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:49:43.99#ibcon#enter wrdev, iclass 16, count 2 2006.285.15:49:43.99#ibcon#first serial, iclass 16, count 2 2006.285.15:49:43.99#ibcon#enter sib2, iclass 16, count 2 2006.285.15:49:43.99#ibcon#flushed, iclass 16, count 2 2006.285.15:49:43.99#ibcon#about to write, iclass 16, count 2 2006.285.15:49:43.99#ibcon#wrote, iclass 16, count 2 2006.285.15:49:43.99#ibcon#about to read 3, iclass 16, count 2 2006.285.15:49:44.01#ibcon#read 3, iclass 16, count 2 2006.285.15:49:44.01#ibcon#about to read 4, iclass 16, count 2 2006.285.15:49:44.01#ibcon#read 4, iclass 16, count 2 2006.285.15:49:44.01#ibcon#about to read 5, iclass 16, count 2 2006.285.15:49:44.01#ibcon#read 5, iclass 16, count 2 2006.285.15:49:44.01#ibcon#about to read 6, iclass 16, count 2 2006.285.15:49:44.01#ibcon#read 6, iclass 16, count 2 2006.285.15:49:44.01#ibcon#end of sib2, iclass 16, count 2 2006.285.15:49:44.01#ibcon#*mode == 0, iclass 16, count 2 2006.285.15:49:44.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.15:49:44.01#ibcon#[27=AT01-04\r\n] 2006.285.15:49:44.01#ibcon#*before write, iclass 16, count 2 2006.285.15:49:44.01#ibcon#enter sib2, iclass 16, count 2 2006.285.15:49:44.01#ibcon#flushed, iclass 16, count 2 2006.285.15:49:44.01#ibcon#about to write, iclass 16, count 2 2006.285.15:49:44.01#ibcon#wrote, iclass 16, count 2 2006.285.15:49:44.01#ibcon#about to read 3, iclass 16, count 2 2006.285.15:49:44.04#ibcon#read 3, iclass 16, count 2 2006.285.15:49:44.04#ibcon#about to read 4, iclass 16, count 2 2006.285.15:49:44.04#ibcon#read 4, iclass 16, count 2 2006.285.15:49:44.04#ibcon#about to read 5, iclass 16, count 2 2006.285.15:49:44.04#ibcon#read 5, iclass 16, count 2 2006.285.15:49:44.04#ibcon#about to read 6, iclass 16, count 2 2006.285.15:49:44.04#ibcon#read 6, iclass 16, count 2 2006.285.15:49:44.04#ibcon#end of sib2, iclass 16, count 2 2006.285.15:49:44.04#ibcon#*after write, iclass 16, count 2 2006.285.15:49:44.04#ibcon#*before return 0, iclass 16, count 2 2006.285.15:49:44.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:49:44.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.15:49:44.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.15:49:44.04#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:44.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:49:44.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:49:44.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:49:44.16#ibcon#enter wrdev, iclass 16, count 0 2006.285.15:49:44.16#ibcon#first serial, iclass 16, count 0 2006.285.15:49:44.16#ibcon#enter sib2, iclass 16, count 0 2006.285.15:49:44.16#ibcon#flushed, iclass 16, count 0 2006.285.15:49:44.16#ibcon#about to write, iclass 16, count 0 2006.285.15:49:44.16#ibcon#wrote, iclass 16, count 0 2006.285.15:49:44.16#ibcon#about to read 3, iclass 16, count 0 2006.285.15:49:44.18#ibcon#read 3, iclass 16, count 0 2006.285.15:49:44.18#ibcon#about to read 4, iclass 16, count 0 2006.285.15:49:44.18#ibcon#read 4, iclass 16, count 0 2006.285.15:49:44.18#ibcon#about to read 5, iclass 16, count 0 2006.285.15:49:44.18#ibcon#read 5, iclass 16, count 0 2006.285.15:49:44.18#ibcon#about to read 6, iclass 16, count 0 2006.285.15:49:44.18#ibcon#read 6, iclass 16, count 0 2006.285.15:49:44.18#ibcon#end of sib2, iclass 16, count 0 2006.285.15:49:44.18#ibcon#*mode == 0, iclass 16, count 0 2006.285.15:49:44.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.15:49:44.18#ibcon#[27=USB\r\n] 2006.285.15:49:44.18#ibcon#*before write, iclass 16, count 0 2006.285.15:49:44.18#ibcon#enter sib2, iclass 16, count 0 2006.285.15:49:44.18#ibcon#flushed, iclass 16, count 0 2006.285.15:49:44.18#ibcon#about to write, iclass 16, count 0 2006.285.15:49:44.18#ibcon#wrote, iclass 16, count 0 2006.285.15:49:44.18#ibcon#about to read 3, iclass 16, count 0 2006.285.15:49:44.21#ibcon#read 3, iclass 16, count 0 2006.285.15:49:44.21#ibcon#about to read 4, iclass 16, count 0 2006.285.15:49:44.21#ibcon#read 4, iclass 16, count 0 2006.285.15:49:44.21#ibcon#about to read 5, iclass 16, count 0 2006.285.15:49:44.21#ibcon#read 5, iclass 16, count 0 2006.285.15:49:44.21#ibcon#about to read 6, iclass 16, count 0 2006.285.15:49:44.21#ibcon#read 6, iclass 16, count 0 2006.285.15:49:44.21#ibcon#end of sib2, iclass 16, count 0 2006.285.15:49:44.21#ibcon#*after write, iclass 16, count 0 2006.285.15:49:44.21#ibcon#*before return 0, iclass 16, count 0 2006.285.15:49:44.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:49:44.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.15:49:44.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.15:49:44.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.15:49:44.21$vck44/vblo=2,634.99 2006.285.15:49:44.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.15:49:44.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.15:49:44.21#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:44.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:49:44.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:49:44.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:49:44.21#ibcon#enter wrdev, iclass 18, count 0 2006.285.15:49:44.21#ibcon#first serial, iclass 18, count 0 2006.285.15:49:44.21#ibcon#enter sib2, iclass 18, count 0 2006.285.15:49:44.21#ibcon#flushed, iclass 18, count 0 2006.285.15:49:44.21#ibcon#about to write, iclass 18, count 0 2006.285.15:49:44.26#ibcon#wrote, iclass 18, count 0 2006.285.15:49:44.26#ibcon#about to read 3, iclass 18, count 0 2006.285.15:49:44.28#ibcon#read 3, iclass 18, count 0 2006.285.15:49:44.28#ibcon#about to read 4, iclass 18, count 0 2006.285.15:49:44.28#ibcon#read 4, iclass 18, count 0 2006.285.15:49:44.28#ibcon#about to read 5, iclass 18, count 0 2006.285.15:49:44.28#ibcon#read 5, iclass 18, count 0 2006.285.15:49:44.28#ibcon#about to read 6, iclass 18, count 0 2006.285.15:49:44.28#ibcon#read 6, iclass 18, count 0 2006.285.15:49:44.28#ibcon#end of sib2, iclass 18, count 0 2006.285.15:49:44.28#ibcon#*mode == 0, iclass 18, count 0 2006.285.15:49:44.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.15:49:44.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.15:49:44.28#ibcon#*before write, iclass 18, count 0 2006.285.15:49:44.28#ibcon#enter sib2, iclass 18, count 0 2006.285.15:49:44.28#ibcon#flushed, iclass 18, count 0 2006.285.15:49:44.28#ibcon#about to write, iclass 18, count 0 2006.285.15:49:44.28#ibcon#wrote, iclass 18, count 0 2006.285.15:49:44.28#ibcon#about to read 3, iclass 18, count 0 2006.285.15:49:44.32#ibcon#read 3, iclass 18, count 0 2006.285.15:49:44.32#ibcon#about to read 4, iclass 18, count 0 2006.285.15:49:44.32#ibcon#read 4, iclass 18, count 0 2006.285.15:49:44.32#ibcon#about to read 5, iclass 18, count 0 2006.285.15:49:44.32#ibcon#read 5, iclass 18, count 0 2006.285.15:49:44.32#ibcon#about to read 6, iclass 18, count 0 2006.285.15:49:44.32#ibcon#read 6, iclass 18, count 0 2006.285.15:49:44.32#ibcon#end of sib2, iclass 18, count 0 2006.285.15:49:44.32#ibcon#*after write, iclass 18, count 0 2006.285.15:49:44.32#ibcon#*before return 0, iclass 18, count 0 2006.285.15:49:44.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:49:44.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.15:49:44.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.15:49:44.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.15:49:44.32$vck44/vb=2,5 2006.285.15:49:44.32#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.15:49:44.32#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.15:49:44.32#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:44.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:49:44.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:49:44.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:49:44.32#ibcon#enter wrdev, iclass 20, count 2 2006.285.15:49:44.32#ibcon#first serial, iclass 20, count 2 2006.285.15:49:44.32#ibcon#enter sib2, iclass 20, count 2 2006.285.15:49:44.32#ibcon#flushed, iclass 20, count 2 2006.285.15:49:44.32#ibcon#about to write, iclass 20, count 2 2006.285.15:49:44.32#ibcon#wrote, iclass 20, count 2 2006.285.15:49:44.32#ibcon#about to read 3, iclass 20, count 2 2006.285.15:49:44.34#ibcon#read 3, iclass 20, count 2 2006.285.15:49:44.34#ibcon#about to read 4, iclass 20, count 2 2006.285.15:49:44.34#ibcon#read 4, iclass 20, count 2 2006.285.15:49:44.34#ibcon#about to read 5, iclass 20, count 2 2006.285.15:49:44.34#ibcon#read 5, iclass 20, count 2 2006.285.15:49:44.34#ibcon#about to read 6, iclass 20, count 2 2006.285.15:49:44.34#ibcon#read 6, iclass 20, count 2 2006.285.15:49:44.34#ibcon#end of sib2, iclass 20, count 2 2006.285.15:49:44.34#ibcon#*mode == 0, iclass 20, count 2 2006.285.15:49:44.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.15:49:44.34#ibcon#[27=AT02-05\r\n] 2006.285.15:49:44.34#ibcon#*before write, iclass 20, count 2 2006.285.15:49:44.34#ibcon#enter sib2, iclass 20, count 2 2006.285.15:49:44.34#ibcon#flushed, iclass 20, count 2 2006.285.15:49:44.34#ibcon#about to write, iclass 20, count 2 2006.285.15:49:44.34#ibcon#wrote, iclass 20, count 2 2006.285.15:49:44.34#ibcon#about to read 3, iclass 20, count 2 2006.285.15:49:44.37#ibcon#read 3, iclass 20, count 2 2006.285.15:49:44.37#ibcon#about to read 4, iclass 20, count 2 2006.285.15:49:44.37#ibcon#read 4, iclass 20, count 2 2006.285.15:49:44.37#ibcon#about to read 5, iclass 20, count 2 2006.285.15:49:44.37#ibcon#read 5, iclass 20, count 2 2006.285.15:49:44.37#ibcon#about to read 6, iclass 20, count 2 2006.285.15:49:44.37#ibcon#read 6, iclass 20, count 2 2006.285.15:49:44.37#ibcon#end of sib2, iclass 20, count 2 2006.285.15:49:44.37#ibcon#*after write, iclass 20, count 2 2006.285.15:49:44.37#ibcon#*before return 0, iclass 20, count 2 2006.285.15:49:44.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:49:44.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.15:49:44.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.15:49:44.37#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:44.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:49:44.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:49:44.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:49:44.49#ibcon#enter wrdev, iclass 20, count 0 2006.285.15:49:44.49#ibcon#first serial, iclass 20, count 0 2006.285.15:49:44.49#ibcon#enter sib2, iclass 20, count 0 2006.285.15:49:44.49#ibcon#flushed, iclass 20, count 0 2006.285.15:49:44.49#ibcon#about to write, iclass 20, count 0 2006.285.15:49:44.49#ibcon#wrote, iclass 20, count 0 2006.285.15:49:44.49#ibcon#about to read 3, iclass 20, count 0 2006.285.15:49:44.51#ibcon#read 3, iclass 20, count 0 2006.285.15:49:44.51#ibcon#about to read 4, iclass 20, count 0 2006.285.15:49:44.51#ibcon#read 4, iclass 20, count 0 2006.285.15:49:44.51#ibcon#about to read 5, iclass 20, count 0 2006.285.15:49:44.51#ibcon#read 5, iclass 20, count 0 2006.285.15:49:44.51#ibcon#about to read 6, iclass 20, count 0 2006.285.15:49:44.51#ibcon#read 6, iclass 20, count 0 2006.285.15:49:44.51#ibcon#end of sib2, iclass 20, count 0 2006.285.15:49:44.51#ibcon#*mode == 0, iclass 20, count 0 2006.285.15:49:44.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.15:49:44.51#ibcon#[27=USB\r\n] 2006.285.15:49:44.51#ibcon#*before write, iclass 20, count 0 2006.285.15:49:44.51#ibcon#enter sib2, iclass 20, count 0 2006.285.15:49:44.51#ibcon#flushed, iclass 20, count 0 2006.285.15:49:44.51#ibcon#about to write, iclass 20, count 0 2006.285.15:49:44.51#ibcon#wrote, iclass 20, count 0 2006.285.15:49:44.51#ibcon#about to read 3, iclass 20, count 0 2006.285.15:49:44.54#ibcon#read 3, iclass 20, count 0 2006.285.15:49:44.54#ibcon#about to read 4, iclass 20, count 0 2006.285.15:49:44.54#ibcon#read 4, iclass 20, count 0 2006.285.15:49:44.54#ibcon#about to read 5, iclass 20, count 0 2006.285.15:49:44.54#ibcon#read 5, iclass 20, count 0 2006.285.15:49:44.54#ibcon#about to read 6, iclass 20, count 0 2006.285.15:49:44.54#ibcon#read 6, iclass 20, count 0 2006.285.15:49:44.54#ibcon#end of sib2, iclass 20, count 0 2006.285.15:49:44.54#ibcon#*after write, iclass 20, count 0 2006.285.15:49:44.54#ibcon#*before return 0, iclass 20, count 0 2006.285.15:49:44.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:49:44.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.15:49:44.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.15:49:44.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.15:49:44.54$vck44/vblo=3,649.99 2006.285.15:49:44.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.15:49:44.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.15:49:44.54#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:44.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:49:44.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:49:44.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:49:44.54#ibcon#enter wrdev, iclass 22, count 0 2006.285.15:49:44.54#ibcon#first serial, iclass 22, count 0 2006.285.15:49:44.54#ibcon#enter sib2, iclass 22, count 0 2006.285.15:49:44.54#ibcon#flushed, iclass 22, count 0 2006.285.15:49:44.54#ibcon#about to write, iclass 22, count 0 2006.285.15:49:44.54#ibcon#wrote, iclass 22, count 0 2006.285.15:49:44.54#ibcon#about to read 3, iclass 22, count 0 2006.285.15:49:44.56#ibcon#read 3, iclass 22, count 0 2006.285.15:49:44.56#ibcon#about to read 4, iclass 22, count 0 2006.285.15:49:44.56#ibcon#read 4, iclass 22, count 0 2006.285.15:49:44.56#ibcon#about to read 5, iclass 22, count 0 2006.285.15:49:44.56#ibcon#read 5, iclass 22, count 0 2006.285.15:49:44.56#ibcon#about to read 6, iclass 22, count 0 2006.285.15:49:44.56#ibcon#read 6, iclass 22, count 0 2006.285.15:49:44.56#ibcon#end of sib2, iclass 22, count 0 2006.285.15:49:44.56#ibcon#*mode == 0, iclass 22, count 0 2006.285.15:49:44.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.15:49:44.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.15:49:44.56#ibcon#*before write, iclass 22, count 0 2006.285.15:49:44.56#ibcon#enter sib2, iclass 22, count 0 2006.285.15:49:44.56#ibcon#flushed, iclass 22, count 0 2006.285.15:49:44.56#ibcon#about to write, iclass 22, count 0 2006.285.15:49:44.56#ibcon#wrote, iclass 22, count 0 2006.285.15:49:44.56#ibcon#about to read 3, iclass 22, count 0 2006.285.15:49:44.60#ibcon#read 3, iclass 22, count 0 2006.285.15:49:44.60#ibcon#about to read 4, iclass 22, count 0 2006.285.15:49:44.60#ibcon#read 4, iclass 22, count 0 2006.285.15:49:44.60#ibcon#about to read 5, iclass 22, count 0 2006.285.15:49:44.60#ibcon#read 5, iclass 22, count 0 2006.285.15:49:44.60#ibcon#about to read 6, iclass 22, count 0 2006.285.15:49:44.60#ibcon#read 6, iclass 22, count 0 2006.285.15:49:44.60#ibcon#end of sib2, iclass 22, count 0 2006.285.15:49:44.60#ibcon#*after write, iclass 22, count 0 2006.285.15:49:44.60#ibcon#*before return 0, iclass 22, count 0 2006.285.15:49:44.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:49:44.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.15:49:44.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.15:49:44.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.15:49:44.60$vck44/vb=3,4 2006.285.15:49:44.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.15:49:44.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.15:49:44.60#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:44.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:49:44.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:49:44.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:49:44.66#ibcon#enter wrdev, iclass 24, count 2 2006.285.15:49:44.66#ibcon#first serial, iclass 24, count 2 2006.285.15:49:44.66#ibcon#enter sib2, iclass 24, count 2 2006.285.15:49:44.66#ibcon#flushed, iclass 24, count 2 2006.285.15:49:44.66#ibcon#about to write, iclass 24, count 2 2006.285.15:49:44.66#ibcon#wrote, iclass 24, count 2 2006.285.15:49:44.66#ibcon#about to read 3, iclass 24, count 2 2006.285.15:49:44.68#ibcon#read 3, iclass 24, count 2 2006.285.15:49:44.68#ibcon#about to read 4, iclass 24, count 2 2006.285.15:49:44.68#ibcon#read 4, iclass 24, count 2 2006.285.15:49:44.68#ibcon#about to read 5, iclass 24, count 2 2006.285.15:49:44.68#ibcon#read 5, iclass 24, count 2 2006.285.15:49:44.68#ibcon#about to read 6, iclass 24, count 2 2006.285.15:49:44.68#ibcon#read 6, iclass 24, count 2 2006.285.15:49:44.68#ibcon#end of sib2, iclass 24, count 2 2006.285.15:49:44.68#ibcon#*mode == 0, iclass 24, count 2 2006.285.15:49:44.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.15:49:44.68#ibcon#[27=AT03-04\r\n] 2006.285.15:49:44.68#ibcon#*before write, iclass 24, count 2 2006.285.15:49:44.68#ibcon#enter sib2, iclass 24, count 2 2006.285.15:49:44.68#ibcon#flushed, iclass 24, count 2 2006.285.15:49:44.68#ibcon#about to write, iclass 24, count 2 2006.285.15:49:44.68#ibcon#wrote, iclass 24, count 2 2006.285.15:49:44.68#ibcon#about to read 3, iclass 24, count 2 2006.285.15:49:44.71#ibcon#read 3, iclass 24, count 2 2006.285.15:49:44.71#ibcon#about to read 4, iclass 24, count 2 2006.285.15:49:44.71#ibcon#read 4, iclass 24, count 2 2006.285.15:49:44.71#ibcon#about to read 5, iclass 24, count 2 2006.285.15:49:44.71#ibcon#read 5, iclass 24, count 2 2006.285.15:49:44.71#ibcon#about to read 6, iclass 24, count 2 2006.285.15:49:44.71#ibcon#read 6, iclass 24, count 2 2006.285.15:49:44.71#ibcon#end of sib2, iclass 24, count 2 2006.285.15:49:44.71#ibcon#*after write, iclass 24, count 2 2006.285.15:49:44.71#ibcon#*before return 0, iclass 24, count 2 2006.285.15:49:44.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:49:44.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.15:49:44.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.15:49:44.71#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:44.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:49:44.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:49:44.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:49:44.83#ibcon#enter wrdev, iclass 24, count 0 2006.285.15:49:44.83#ibcon#first serial, iclass 24, count 0 2006.285.15:49:44.83#ibcon#enter sib2, iclass 24, count 0 2006.285.15:49:44.83#ibcon#flushed, iclass 24, count 0 2006.285.15:49:44.83#ibcon#about to write, iclass 24, count 0 2006.285.15:49:44.83#ibcon#wrote, iclass 24, count 0 2006.285.15:49:44.83#ibcon#about to read 3, iclass 24, count 0 2006.285.15:49:44.85#ibcon#read 3, iclass 24, count 0 2006.285.15:49:44.85#ibcon#about to read 4, iclass 24, count 0 2006.285.15:49:44.85#ibcon#read 4, iclass 24, count 0 2006.285.15:49:44.85#ibcon#about to read 5, iclass 24, count 0 2006.285.15:49:44.85#ibcon#read 5, iclass 24, count 0 2006.285.15:49:44.85#ibcon#about to read 6, iclass 24, count 0 2006.285.15:49:44.85#ibcon#read 6, iclass 24, count 0 2006.285.15:49:44.85#ibcon#end of sib2, iclass 24, count 0 2006.285.15:49:44.85#ibcon#*mode == 0, iclass 24, count 0 2006.285.15:49:44.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.15:49:44.85#ibcon#[27=USB\r\n] 2006.285.15:49:44.85#ibcon#*before write, iclass 24, count 0 2006.285.15:49:44.85#ibcon#enter sib2, iclass 24, count 0 2006.285.15:49:44.85#ibcon#flushed, iclass 24, count 0 2006.285.15:49:44.85#ibcon#about to write, iclass 24, count 0 2006.285.15:49:44.85#ibcon#wrote, iclass 24, count 0 2006.285.15:49:44.85#ibcon#about to read 3, iclass 24, count 0 2006.285.15:49:44.88#ibcon#read 3, iclass 24, count 0 2006.285.15:49:44.88#ibcon#about to read 4, iclass 24, count 0 2006.285.15:49:44.88#ibcon#read 4, iclass 24, count 0 2006.285.15:49:44.88#ibcon#about to read 5, iclass 24, count 0 2006.285.15:49:44.88#ibcon#read 5, iclass 24, count 0 2006.285.15:49:44.88#ibcon#about to read 6, iclass 24, count 0 2006.285.15:49:44.88#ibcon#read 6, iclass 24, count 0 2006.285.15:49:44.88#ibcon#end of sib2, iclass 24, count 0 2006.285.15:49:44.88#ibcon#*after write, iclass 24, count 0 2006.285.15:49:44.88#ibcon#*before return 0, iclass 24, count 0 2006.285.15:49:44.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:49:44.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.15:49:44.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.15:49:44.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.15:49:44.88$vck44/vblo=4,679.99 2006.285.15:49:44.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.15:49:44.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.15:49:44.88#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:44.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:49:44.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:49:44.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:49:44.88#ibcon#enter wrdev, iclass 26, count 0 2006.285.15:49:44.88#ibcon#first serial, iclass 26, count 0 2006.285.15:49:44.88#ibcon#enter sib2, iclass 26, count 0 2006.285.15:49:44.88#ibcon#flushed, iclass 26, count 0 2006.285.15:49:44.88#ibcon#about to write, iclass 26, count 0 2006.285.15:49:44.88#ibcon#wrote, iclass 26, count 0 2006.285.15:49:44.88#ibcon#about to read 3, iclass 26, count 0 2006.285.15:49:44.90#ibcon#read 3, iclass 26, count 0 2006.285.15:49:44.90#ibcon#about to read 4, iclass 26, count 0 2006.285.15:49:44.90#ibcon#read 4, iclass 26, count 0 2006.285.15:49:44.90#ibcon#about to read 5, iclass 26, count 0 2006.285.15:49:44.90#ibcon#read 5, iclass 26, count 0 2006.285.15:49:44.90#ibcon#about to read 6, iclass 26, count 0 2006.285.15:49:44.90#ibcon#read 6, iclass 26, count 0 2006.285.15:49:44.90#ibcon#end of sib2, iclass 26, count 0 2006.285.15:49:44.90#ibcon#*mode == 0, iclass 26, count 0 2006.285.15:49:44.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.15:49:44.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.15:49:44.90#ibcon#*before write, iclass 26, count 0 2006.285.15:49:44.90#ibcon#enter sib2, iclass 26, count 0 2006.285.15:49:44.90#ibcon#flushed, iclass 26, count 0 2006.285.15:49:44.90#ibcon#about to write, iclass 26, count 0 2006.285.15:49:44.90#ibcon#wrote, iclass 26, count 0 2006.285.15:49:44.90#ibcon#about to read 3, iclass 26, count 0 2006.285.15:49:44.94#ibcon#read 3, iclass 26, count 0 2006.285.15:49:44.94#ibcon#about to read 4, iclass 26, count 0 2006.285.15:49:44.94#ibcon#read 4, iclass 26, count 0 2006.285.15:49:44.94#ibcon#about to read 5, iclass 26, count 0 2006.285.15:49:44.94#ibcon#read 5, iclass 26, count 0 2006.285.15:49:44.94#ibcon#about to read 6, iclass 26, count 0 2006.285.15:49:44.94#ibcon#read 6, iclass 26, count 0 2006.285.15:49:44.94#ibcon#end of sib2, iclass 26, count 0 2006.285.15:49:44.94#ibcon#*after write, iclass 26, count 0 2006.285.15:49:44.94#ibcon#*before return 0, iclass 26, count 0 2006.285.15:49:44.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:49:44.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:49:44.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.15:49:44.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.15:49:44.94$vck44/vb=4,5 2006.285.15:49:44.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.15:49:44.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.15:49:44.94#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:44.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:49:45.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:49:45.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:49:45.00#ibcon#enter wrdev, iclass 28, count 2 2006.285.15:49:45.00#ibcon#first serial, iclass 28, count 2 2006.285.15:49:45.00#ibcon#enter sib2, iclass 28, count 2 2006.285.15:49:45.00#ibcon#flushed, iclass 28, count 2 2006.285.15:49:45.00#ibcon#about to write, iclass 28, count 2 2006.285.15:49:45.00#ibcon#wrote, iclass 28, count 2 2006.285.15:49:45.00#ibcon#about to read 3, iclass 28, count 2 2006.285.15:49:45.02#ibcon#read 3, iclass 28, count 2 2006.285.15:49:45.02#ibcon#about to read 4, iclass 28, count 2 2006.285.15:49:45.02#ibcon#read 4, iclass 28, count 2 2006.285.15:49:45.02#ibcon#about to read 5, iclass 28, count 2 2006.285.15:49:45.02#ibcon#read 5, iclass 28, count 2 2006.285.15:49:45.02#ibcon#about to read 6, iclass 28, count 2 2006.285.15:49:45.02#ibcon#read 6, iclass 28, count 2 2006.285.15:49:45.02#ibcon#end of sib2, iclass 28, count 2 2006.285.15:49:45.02#ibcon#*mode == 0, iclass 28, count 2 2006.285.15:49:45.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.15:49:45.02#ibcon#[27=AT04-05\r\n] 2006.285.15:49:45.02#ibcon#*before write, iclass 28, count 2 2006.285.15:49:45.02#ibcon#enter sib2, iclass 28, count 2 2006.285.15:49:45.02#ibcon#flushed, iclass 28, count 2 2006.285.15:49:45.02#ibcon#about to write, iclass 28, count 2 2006.285.15:49:45.02#ibcon#wrote, iclass 28, count 2 2006.285.15:49:45.02#ibcon#about to read 3, iclass 28, count 2 2006.285.15:49:45.05#ibcon#read 3, iclass 28, count 2 2006.285.15:49:45.05#ibcon#about to read 4, iclass 28, count 2 2006.285.15:49:45.05#ibcon#read 4, iclass 28, count 2 2006.285.15:49:45.05#ibcon#about to read 5, iclass 28, count 2 2006.285.15:49:45.05#ibcon#read 5, iclass 28, count 2 2006.285.15:49:45.05#ibcon#about to read 6, iclass 28, count 2 2006.285.15:49:45.05#ibcon#read 6, iclass 28, count 2 2006.285.15:49:45.05#ibcon#end of sib2, iclass 28, count 2 2006.285.15:49:45.05#ibcon#*after write, iclass 28, count 2 2006.285.15:49:45.05#ibcon#*before return 0, iclass 28, count 2 2006.285.15:49:45.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:49:45.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.15:49:45.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.15:49:45.05#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:45.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:49:45.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:49:45.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:49:45.17#ibcon#enter wrdev, iclass 28, count 0 2006.285.15:49:45.17#ibcon#first serial, iclass 28, count 0 2006.285.15:49:45.17#ibcon#enter sib2, iclass 28, count 0 2006.285.15:49:45.17#ibcon#flushed, iclass 28, count 0 2006.285.15:49:45.17#ibcon#about to write, iclass 28, count 0 2006.285.15:49:45.17#ibcon#wrote, iclass 28, count 0 2006.285.15:49:45.17#ibcon#about to read 3, iclass 28, count 0 2006.285.15:49:45.19#ibcon#read 3, iclass 28, count 0 2006.285.15:49:45.19#ibcon#about to read 4, iclass 28, count 0 2006.285.15:49:45.19#ibcon#read 4, iclass 28, count 0 2006.285.15:49:45.19#ibcon#about to read 5, iclass 28, count 0 2006.285.15:49:45.19#ibcon#read 5, iclass 28, count 0 2006.285.15:49:45.19#ibcon#about to read 6, iclass 28, count 0 2006.285.15:49:45.19#ibcon#read 6, iclass 28, count 0 2006.285.15:49:45.19#ibcon#end of sib2, iclass 28, count 0 2006.285.15:49:45.19#ibcon#*mode == 0, iclass 28, count 0 2006.285.15:49:45.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.15:49:45.19#ibcon#[27=USB\r\n] 2006.285.15:49:45.19#ibcon#*before write, iclass 28, count 0 2006.285.15:49:45.19#ibcon#enter sib2, iclass 28, count 0 2006.285.15:49:45.19#ibcon#flushed, iclass 28, count 0 2006.285.15:49:45.19#ibcon#about to write, iclass 28, count 0 2006.285.15:49:45.19#ibcon#wrote, iclass 28, count 0 2006.285.15:49:45.19#ibcon#about to read 3, iclass 28, count 0 2006.285.15:49:45.22#ibcon#read 3, iclass 28, count 0 2006.285.15:49:45.22#ibcon#about to read 4, iclass 28, count 0 2006.285.15:49:45.22#ibcon#read 4, iclass 28, count 0 2006.285.15:49:45.22#ibcon#about to read 5, iclass 28, count 0 2006.285.15:49:45.22#ibcon#read 5, iclass 28, count 0 2006.285.15:49:45.22#ibcon#about to read 6, iclass 28, count 0 2006.285.15:49:45.22#ibcon#read 6, iclass 28, count 0 2006.285.15:49:45.22#ibcon#end of sib2, iclass 28, count 0 2006.285.15:49:45.22#ibcon#*after write, iclass 28, count 0 2006.285.15:49:45.22#ibcon#*before return 0, iclass 28, count 0 2006.285.15:49:45.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:49:45.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.15:49:45.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.15:49:45.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.15:49:45.22$vck44/vblo=5,709.99 2006.285.15:49:45.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.15:49:45.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.15:49:45.22#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:45.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:49:45.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:49:45.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:49:45.22#ibcon#enter wrdev, iclass 30, count 0 2006.285.15:49:45.22#ibcon#first serial, iclass 30, count 0 2006.285.15:49:45.22#ibcon#enter sib2, iclass 30, count 0 2006.285.15:49:45.22#ibcon#flushed, iclass 30, count 0 2006.285.15:49:45.22#ibcon#about to write, iclass 30, count 0 2006.285.15:49:45.22#ibcon#wrote, iclass 30, count 0 2006.285.15:49:45.22#ibcon#about to read 3, iclass 30, count 0 2006.285.15:49:45.24#ibcon#read 3, iclass 30, count 0 2006.285.15:49:45.24#ibcon#about to read 4, iclass 30, count 0 2006.285.15:49:45.24#ibcon#read 4, iclass 30, count 0 2006.285.15:49:45.24#ibcon#about to read 5, iclass 30, count 0 2006.285.15:49:45.24#ibcon#read 5, iclass 30, count 0 2006.285.15:49:45.24#ibcon#about to read 6, iclass 30, count 0 2006.285.15:49:45.24#ibcon#read 6, iclass 30, count 0 2006.285.15:49:45.24#ibcon#end of sib2, iclass 30, count 0 2006.285.15:49:45.24#ibcon#*mode == 0, iclass 30, count 0 2006.285.15:49:45.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.15:49:45.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.15:49:45.24#ibcon#*before write, iclass 30, count 0 2006.285.15:49:45.24#ibcon#enter sib2, iclass 30, count 0 2006.285.15:49:45.24#ibcon#flushed, iclass 30, count 0 2006.285.15:49:45.24#ibcon#about to write, iclass 30, count 0 2006.285.15:49:45.24#ibcon#wrote, iclass 30, count 0 2006.285.15:49:45.24#ibcon#about to read 3, iclass 30, count 0 2006.285.15:49:45.28#ibcon#read 3, iclass 30, count 0 2006.285.15:49:45.28#ibcon#about to read 4, iclass 30, count 0 2006.285.15:49:45.28#ibcon#read 4, iclass 30, count 0 2006.285.15:49:45.28#ibcon#about to read 5, iclass 30, count 0 2006.285.15:49:45.28#ibcon#read 5, iclass 30, count 0 2006.285.15:49:45.28#ibcon#about to read 6, iclass 30, count 0 2006.285.15:49:45.28#ibcon#read 6, iclass 30, count 0 2006.285.15:49:45.28#ibcon#end of sib2, iclass 30, count 0 2006.285.15:49:45.28#ibcon#*after write, iclass 30, count 0 2006.285.15:49:45.28#ibcon#*before return 0, iclass 30, count 0 2006.285.15:49:45.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:49:45.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.15:49:45.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.15:49:45.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.15:49:45.28$vck44/vb=5,4 2006.285.15:49:45.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.15:49:45.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.15:49:45.28#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:45.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:49:45.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:49:45.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:49:45.34#ibcon#enter wrdev, iclass 32, count 2 2006.285.15:49:45.34#ibcon#first serial, iclass 32, count 2 2006.285.15:49:45.34#ibcon#enter sib2, iclass 32, count 2 2006.285.15:49:45.34#ibcon#flushed, iclass 32, count 2 2006.285.15:49:45.34#ibcon#about to write, iclass 32, count 2 2006.285.15:49:45.34#ibcon#wrote, iclass 32, count 2 2006.285.15:49:45.34#ibcon#about to read 3, iclass 32, count 2 2006.285.15:49:45.36#ibcon#read 3, iclass 32, count 2 2006.285.15:49:45.36#ibcon#about to read 4, iclass 32, count 2 2006.285.15:49:45.36#ibcon#read 4, iclass 32, count 2 2006.285.15:49:45.36#ibcon#about to read 5, iclass 32, count 2 2006.285.15:49:45.36#ibcon#read 5, iclass 32, count 2 2006.285.15:49:45.36#ibcon#about to read 6, iclass 32, count 2 2006.285.15:49:45.36#ibcon#read 6, iclass 32, count 2 2006.285.15:49:45.36#ibcon#end of sib2, iclass 32, count 2 2006.285.15:49:45.36#ibcon#*mode == 0, iclass 32, count 2 2006.285.15:49:45.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.15:49:45.36#ibcon#[27=AT05-04\r\n] 2006.285.15:49:45.36#ibcon#*before write, iclass 32, count 2 2006.285.15:49:45.36#ibcon#enter sib2, iclass 32, count 2 2006.285.15:49:45.36#ibcon#flushed, iclass 32, count 2 2006.285.15:49:45.36#ibcon#about to write, iclass 32, count 2 2006.285.15:49:45.36#ibcon#wrote, iclass 32, count 2 2006.285.15:49:45.36#ibcon#about to read 3, iclass 32, count 2 2006.285.15:49:45.39#ibcon#read 3, iclass 32, count 2 2006.285.15:49:45.39#ibcon#about to read 4, iclass 32, count 2 2006.285.15:49:45.39#ibcon#read 4, iclass 32, count 2 2006.285.15:49:45.39#ibcon#about to read 5, iclass 32, count 2 2006.285.15:49:45.39#ibcon#read 5, iclass 32, count 2 2006.285.15:49:45.39#ibcon#about to read 6, iclass 32, count 2 2006.285.15:49:45.39#ibcon#read 6, iclass 32, count 2 2006.285.15:49:45.39#ibcon#end of sib2, iclass 32, count 2 2006.285.15:49:45.39#ibcon#*after write, iclass 32, count 2 2006.285.15:49:45.39#ibcon#*before return 0, iclass 32, count 2 2006.285.15:49:45.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:49:45.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.15:49:45.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.15:49:45.39#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:45.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:49:45.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:49:45.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:49:45.51#ibcon#enter wrdev, iclass 32, count 0 2006.285.15:49:45.51#ibcon#first serial, iclass 32, count 0 2006.285.15:49:45.51#ibcon#enter sib2, iclass 32, count 0 2006.285.15:49:45.51#ibcon#flushed, iclass 32, count 0 2006.285.15:49:45.51#ibcon#about to write, iclass 32, count 0 2006.285.15:49:45.51#ibcon#wrote, iclass 32, count 0 2006.285.15:49:45.51#ibcon#about to read 3, iclass 32, count 0 2006.285.15:49:45.53#ibcon#read 3, iclass 32, count 0 2006.285.15:49:45.53#ibcon#about to read 4, iclass 32, count 0 2006.285.15:49:45.53#ibcon#read 4, iclass 32, count 0 2006.285.15:49:45.53#ibcon#about to read 5, iclass 32, count 0 2006.285.15:49:45.53#ibcon#read 5, iclass 32, count 0 2006.285.15:49:45.53#ibcon#about to read 6, iclass 32, count 0 2006.285.15:49:45.53#ibcon#read 6, iclass 32, count 0 2006.285.15:49:45.53#ibcon#end of sib2, iclass 32, count 0 2006.285.15:49:45.53#ibcon#*mode == 0, iclass 32, count 0 2006.285.15:49:45.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.15:49:45.53#ibcon#[27=USB\r\n] 2006.285.15:49:45.53#ibcon#*before write, iclass 32, count 0 2006.285.15:49:45.53#ibcon#enter sib2, iclass 32, count 0 2006.285.15:49:45.53#ibcon#flushed, iclass 32, count 0 2006.285.15:49:45.53#ibcon#about to write, iclass 32, count 0 2006.285.15:49:45.53#ibcon#wrote, iclass 32, count 0 2006.285.15:49:45.53#ibcon#about to read 3, iclass 32, count 0 2006.285.15:49:45.56#ibcon#read 3, iclass 32, count 0 2006.285.15:49:45.56#ibcon#about to read 4, iclass 32, count 0 2006.285.15:49:45.56#ibcon#read 4, iclass 32, count 0 2006.285.15:49:45.56#ibcon#about to read 5, iclass 32, count 0 2006.285.15:49:45.56#ibcon#read 5, iclass 32, count 0 2006.285.15:49:45.56#ibcon#about to read 6, iclass 32, count 0 2006.285.15:49:45.56#ibcon#read 6, iclass 32, count 0 2006.285.15:49:45.56#ibcon#end of sib2, iclass 32, count 0 2006.285.15:49:45.56#ibcon#*after write, iclass 32, count 0 2006.285.15:49:45.56#ibcon#*before return 0, iclass 32, count 0 2006.285.15:49:45.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:49:45.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.15:49:45.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.15:49:45.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.15:49:45.56$vck44/vblo=6,719.99 2006.285.15:49:45.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.15:49:45.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.15:49:45.56#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:45.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:49:45.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:49:45.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:49:45.56#ibcon#enter wrdev, iclass 34, count 0 2006.285.15:49:45.56#ibcon#first serial, iclass 34, count 0 2006.285.15:49:45.56#ibcon#enter sib2, iclass 34, count 0 2006.285.15:49:45.56#ibcon#flushed, iclass 34, count 0 2006.285.15:49:45.56#ibcon#about to write, iclass 34, count 0 2006.285.15:49:45.56#ibcon#wrote, iclass 34, count 0 2006.285.15:49:45.56#ibcon#about to read 3, iclass 34, count 0 2006.285.15:49:45.58#ibcon#read 3, iclass 34, count 0 2006.285.15:49:45.58#ibcon#about to read 4, iclass 34, count 0 2006.285.15:49:45.58#ibcon#read 4, iclass 34, count 0 2006.285.15:49:45.58#ibcon#about to read 5, iclass 34, count 0 2006.285.15:49:45.58#ibcon#read 5, iclass 34, count 0 2006.285.15:49:45.58#ibcon#about to read 6, iclass 34, count 0 2006.285.15:49:45.58#ibcon#read 6, iclass 34, count 0 2006.285.15:49:45.58#ibcon#end of sib2, iclass 34, count 0 2006.285.15:49:45.58#ibcon#*mode == 0, iclass 34, count 0 2006.285.15:49:45.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.15:49:45.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.15:49:45.58#ibcon#*before write, iclass 34, count 0 2006.285.15:49:45.58#ibcon#enter sib2, iclass 34, count 0 2006.285.15:49:45.58#ibcon#flushed, iclass 34, count 0 2006.285.15:49:45.58#ibcon#about to write, iclass 34, count 0 2006.285.15:49:45.58#ibcon#wrote, iclass 34, count 0 2006.285.15:49:45.58#ibcon#about to read 3, iclass 34, count 0 2006.285.15:49:45.62#ibcon#read 3, iclass 34, count 0 2006.285.15:49:45.62#ibcon#about to read 4, iclass 34, count 0 2006.285.15:49:45.62#ibcon#read 4, iclass 34, count 0 2006.285.15:49:45.62#ibcon#about to read 5, iclass 34, count 0 2006.285.15:49:45.62#ibcon#read 5, iclass 34, count 0 2006.285.15:49:45.62#ibcon#about to read 6, iclass 34, count 0 2006.285.15:49:45.62#ibcon#read 6, iclass 34, count 0 2006.285.15:49:45.62#ibcon#end of sib2, iclass 34, count 0 2006.285.15:49:45.62#ibcon#*after write, iclass 34, count 0 2006.285.15:49:45.62#ibcon#*before return 0, iclass 34, count 0 2006.285.15:49:45.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:49:45.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.15:49:45.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.15:49:45.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.15:49:45.62$vck44/vb=6,3 2006.285.15:49:45.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.15:49:45.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.15:49:45.62#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:45.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:49:45.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:49:45.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:49:45.68#ibcon#enter wrdev, iclass 36, count 2 2006.285.15:49:45.68#ibcon#first serial, iclass 36, count 2 2006.285.15:49:45.68#ibcon#enter sib2, iclass 36, count 2 2006.285.15:49:45.68#ibcon#flushed, iclass 36, count 2 2006.285.15:49:45.68#ibcon#about to write, iclass 36, count 2 2006.285.15:49:45.68#ibcon#wrote, iclass 36, count 2 2006.285.15:49:45.68#ibcon#about to read 3, iclass 36, count 2 2006.285.15:49:45.70#ibcon#read 3, iclass 36, count 2 2006.285.15:49:45.70#ibcon#about to read 4, iclass 36, count 2 2006.285.15:49:45.70#ibcon#read 4, iclass 36, count 2 2006.285.15:49:45.70#ibcon#about to read 5, iclass 36, count 2 2006.285.15:49:45.70#ibcon#read 5, iclass 36, count 2 2006.285.15:49:45.70#ibcon#about to read 6, iclass 36, count 2 2006.285.15:49:45.70#ibcon#read 6, iclass 36, count 2 2006.285.15:49:45.70#ibcon#end of sib2, iclass 36, count 2 2006.285.15:49:45.70#ibcon#*mode == 0, iclass 36, count 2 2006.285.15:49:45.70#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.15:49:45.70#ibcon#[27=AT06-03\r\n] 2006.285.15:49:45.70#ibcon#*before write, iclass 36, count 2 2006.285.15:49:45.70#ibcon#enter sib2, iclass 36, count 2 2006.285.15:49:45.70#ibcon#flushed, iclass 36, count 2 2006.285.15:49:45.70#ibcon#about to write, iclass 36, count 2 2006.285.15:49:45.70#ibcon#wrote, iclass 36, count 2 2006.285.15:49:45.70#ibcon#about to read 3, iclass 36, count 2 2006.285.15:49:45.73#ibcon#read 3, iclass 36, count 2 2006.285.15:49:45.73#ibcon#about to read 4, iclass 36, count 2 2006.285.15:49:45.73#ibcon#read 4, iclass 36, count 2 2006.285.15:49:45.73#ibcon#about to read 5, iclass 36, count 2 2006.285.15:49:45.73#ibcon#read 5, iclass 36, count 2 2006.285.15:49:45.73#ibcon#about to read 6, iclass 36, count 2 2006.285.15:49:45.73#ibcon#read 6, iclass 36, count 2 2006.285.15:49:45.73#ibcon#end of sib2, iclass 36, count 2 2006.285.15:49:45.73#ibcon#*after write, iclass 36, count 2 2006.285.15:49:45.73#ibcon#*before return 0, iclass 36, count 2 2006.285.15:49:45.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:49:45.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.15:49:45.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.15:49:45.73#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:45.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:49:45.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:49:45.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:49:45.85#ibcon#enter wrdev, iclass 36, count 0 2006.285.15:49:45.85#ibcon#first serial, iclass 36, count 0 2006.285.15:49:45.85#ibcon#enter sib2, iclass 36, count 0 2006.285.15:49:45.85#ibcon#flushed, iclass 36, count 0 2006.285.15:49:45.85#ibcon#about to write, iclass 36, count 0 2006.285.15:49:45.85#ibcon#wrote, iclass 36, count 0 2006.285.15:49:45.85#ibcon#about to read 3, iclass 36, count 0 2006.285.15:49:45.87#ibcon#read 3, iclass 36, count 0 2006.285.15:49:45.87#ibcon#about to read 4, iclass 36, count 0 2006.285.15:49:45.87#ibcon#read 4, iclass 36, count 0 2006.285.15:49:45.87#ibcon#about to read 5, iclass 36, count 0 2006.285.15:49:45.87#ibcon#read 5, iclass 36, count 0 2006.285.15:49:45.87#ibcon#about to read 6, iclass 36, count 0 2006.285.15:49:45.87#ibcon#read 6, iclass 36, count 0 2006.285.15:49:45.87#ibcon#end of sib2, iclass 36, count 0 2006.285.15:49:45.87#ibcon#*mode == 0, iclass 36, count 0 2006.285.15:49:45.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.15:49:45.87#ibcon#[27=USB\r\n] 2006.285.15:49:45.87#ibcon#*before write, iclass 36, count 0 2006.285.15:49:45.87#ibcon#enter sib2, iclass 36, count 0 2006.285.15:49:45.87#ibcon#flushed, iclass 36, count 0 2006.285.15:49:45.87#ibcon#about to write, iclass 36, count 0 2006.285.15:49:45.87#ibcon#wrote, iclass 36, count 0 2006.285.15:49:45.87#ibcon#about to read 3, iclass 36, count 0 2006.285.15:49:45.90#ibcon#read 3, iclass 36, count 0 2006.285.15:49:45.90#ibcon#about to read 4, iclass 36, count 0 2006.285.15:49:45.90#ibcon#read 4, iclass 36, count 0 2006.285.15:49:45.90#ibcon#about to read 5, iclass 36, count 0 2006.285.15:49:45.90#ibcon#read 5, iclass 36, count 0 2006.285.15:49:45.90#ibcon#about to read 6, iclass 36, count 0 2006.285.15:49:45.90#ibcon#read 6, iclass 36, count 0 2006.285.15:49:45.90#ibcon#end of sib2, iclass 36, count 0 2006.285.15:49:45.90#ibcon#*after write, iclass 36, count 0 2006.285.15:49:45.90#ibcon#*before return 0, iclass 36, count 0 2006.285.15:49:45.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:49:45.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.15:49:45.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.15:49:45.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.15:49:45.90$vck44/vblo=7,734.99 2006.285.15:49:45.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.15:49:45.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.15:49:45.90#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:45.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:49:45.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:49:45.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:49:45.90#ibcon#enter wrdev, iclass 38, count 0 2006.285.15:49:45.90#ibcon#first serial, iclass 38, count 0 2006.285.15:49:45.90#ibcon#enter sib2, iclass 38, count 0 2006.285.15:49:45.90#ibcon#flushed, iclass 38, count 0 2006.285.15:49:45.90#ibcon#about to write, iclass 38, count 0 2006.285.15:49:45.90#ibcon#wrote, iclass 38, count 0 2006.285.15:49:45.90#ibcon#about to read 3, iclass 38, count 0 2006.285.15:49:45.92#ibcon#read 3, iclass 38, count 0 2006.285.15:49:45.92#ibcon#about to read 4, iclass 38, count 0 2006.285.15:49:45.92#ibcon#read 4, iclass 38, count 0 2006.285.15:49:45.92#ibcon#about to read 5, iclass 38, count 0 2006.285.15:49:45.92#ibcon#read 5, iclass 38, count 0 2006.285.15:49:45.92#ibcon#about to read 6, iclass 38, count 0 2006.285.15:49:45.92#ibcon#read 6, iclass 38, count 0 2006.285.15:49:45.92#ibcon#end of sib2, iclass 38, count 0 2006.285.15:49:45.92#ibcon#*mode == 0, iclass 38, count 0 2006.285.15:49:45.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.15:49:45.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.15:49:45.92#ibcon#*before write, iclass 38, count 0 2006.285.15:49:45.92#ibcon#enter sib2, iclass 38, count 0 2006.285.15:49:45.92#ibcon#flushed, iclass 38, count 0 2006.285.15:49:45.92#ibcon#about to write, iclass 38, count 0 2006.285.15:49:45.92#ibcon#wrote, iclass 38, count 0 2006.285.15:49:45.92#ibcon#about to read 3, iclass 38, count 0 2006.285.15:49:45.96#ibcon#read 3, iclass 38, count 0 2006.285.15:49:45.96#ibcon#about to read 4, iclass 38, count 0 2006.285.15:49:45.96#ibcon#read 4, iclass 38, count 0 2006.285.15:49:45.96#ibcon#about to read 5, iclass 38, count 0 2006.285.15:49:45.96#ibcon#read 5, iclass 38, count 0 2006.285.15:49:45.96#ibcon#about to read 6, iclass 38, count 0 2006.285.15:49:45.96#ibcon#read 6, iclass 38, count 0 2006.285.15:49:45.96#ibcon#end of sib2, iclass 38, count 0 2006.285.15:49:45.96#ibcon#*after write, iclass 38, count 0 2006.285.15:49:45.96#ibcon#*before return 0, iclass 38, count 0 2006.285.15:49:45.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:49:45.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.15:49:45.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.15:49:45.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.15:49:45.96$vck44/vb=7,4 2006.285.15:49:45.96#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.15:49:45.96#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.15:49:45.96#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:45.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:49:46.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:49:46.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:49:46.02#ibcon#enter wrdev, iclass 40, count 2 2006.285.15:49:46.02#ibcon#first serial, iclass 40, count 2 2006.285.15:49:46.02#ibcon#enter sib2, iclass 40, count 2 2006.285.15:49:46.02#ibcon#flushed, iclass 40, count 2 2006.285.15:49:46.02#ibcon#about to write, iclass 40, count 2 2006.285.15:49:46.02#ibcon#wrote, iclass 40, count 2 2006.285.15:49:46.02#ibcon#about to read 3, iclass 40, count 2 2006.285.15:49:46.04#ibcon#read 3, iclass 40, count 2 2006.285.15:49:46.04#ibcon#about to read 4, iclass 40, count 2 2006.285.15:49:46.04#ibcon#read 4, iclass 40, count 2 2006.285.15:49:46.04#ibcon#about to read 5, iclass 40, count 2 2006.285.15:49:46.04#ibcon#read 5, iclass 40, count 2 2006.285.15:49:46.04#ibcon#about to read 6, iclass 40, count 2 2006.285.15:49:46.04#ibcon#read 6, iclass 40, count 2 2006.285.15:49:46.04#ibcon#end of sib2, iclass 40, count 2 2006.285.15:49:46.04#ibcon#*mode == 0, iclass 40, count 2 2006.285.15:49:46.04#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.15:49:46.04#ibcon#[27=AT07-04\r\n] 2006.285.15:49:46.04#ibcon#*before write, iclass 40, count 2 2006.285.15:49:46.04#ibcon#enter sib2, iclass 40, count 2 2006.285.15:49:46.04#ibcon#flushed, iclass 40, count 2 2006.285.15:49:46.04#ibcon#about to write, iclass 40, count 2 2006.285.15:49:46.04#ibcon#wrote, iclass 40, count 2 2006.285.15:49:46.04#ibcon#about to read 3, iclass 40, count 2 2006.285.15:49:46.07#ibcon#read 3, iclass 40, count 2 2006.285.15:49:46.07#ibcon#about to read 4, iclass 40, count 2 2006.285.15:49:46.07#ibcon#read 4, iclass 40, count 2 2006.285.15:49:46.07#ibcon#about to read 5, iclass 40, count 2 2006.285.15:49:46.07#ibcon#read 5, iclass 40, count 2 2006.285.15:49:46.07#ibcon#about to read 6, iclass 40, count 2 2006.285.15:49:46.07#ibcon#read 6, iclass 40, count 2 2006.285.15:49:46.07#ibcon#end of sib2, iclass 40, count 2 2006.285.15:49:46.07#ibcon#*after write, iclass 40, count 2 2006.285.15:49:46.07#ibcon#*before return 0, iclass 40, count 2 2006.285.15:49:46.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:49:46.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.15:49:46.07#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.15:49:46.07#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:46.07#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:49:46.19#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:49:46.19#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:49:46.19#ibcon#enter wrdev, iclass 40, count 0 2006.285.15:49:46.19#ibcon#first serial, iclass 40, count 0 2006.285.15:49:46.19#ibcon#enter sib2, iclass 40, count 0 2006.285.15:49:46.19#ibcon#flushed, iclass 40, count 0 2006.285.15:49:46.19#ibcon#about to write, iclass 40, count 0 2006.285.15:49:46.19#ibcon#wrote, iclass 40, count 0 2006.285.15:49:46.19#ibcon#about to read 3, iclass 40, count 0 2006.285.15:49:46.21#ibcon#read 3, iclass 40, count 0 2006.285.15:49:46.21#ibcon#about to read 4, iclass 40, count 0 2006.285.15:49:46.21#ibcon#read 4, iclass 40, count 0 2006.285.15:49:46.21#ibcon#about to read 5, iclass 40, count 0 2006.285.15:49:46.21#ibcon#read 5, iclass 40, count 0 2006.285.15:49:46.21#ibcon#about to read 6, iclass 40, count 0 2006.285.15:49:46.21#ibcon#read 6, iclass 40, count 0 2006.285.15:49:46.21#ibcon#end of sib2, iclass 40, count 0 2006.285.15:49:46.21#ibcon#*mode == 0, iclass 40, count 0 2006.285.15:49:46.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.15:49:46.21#ibcon#[27=USB\r\n] 2006.285.15:49:46.21#ibcon#*before write, iclass 40, count 0 2006.285.15:49:46.21#ibcon#enter sib2, iclass 40, count 0 2006.285.15:49:46.21#ibcon#flushed, iclass 40, count 0 2006.285.15:49:46.21#ibcon#about to write, iclass 40, count 0 2006.285.15:49:46.21#ibcon#wrote, iclass 40, count 0 2006.285.15:49:46.21#ibcon#about to read 3, iclass 40, count 0 2006.285.15:49:46.24#ibcon#read 3, iclass 40, count 0 2006.285.15:49:46.24#ibcon#about to read 4, iclass 40, count 0 2006.285.15:49:46.24#ibcon#read 4, iclass 40, count 0 2006.285.15:49:46.24#ibcon#about to read 5, iclass 40, count 0 2006.285.15:49:46.24#ibcon#read 5, iclass 40, count 0 2006.285.15:49:46.24#ibcon#about to read 6, iclass 40, count 0 2006.285.15:49:46.24#ibcon#read 6, iclass 40, count 0 2006.285.15:49:46.24#ibcon#end of sib2, iclass 40, count 0 2006.285.15:49:46.24#ibcon#*after write, iclass 40, count 0 2006.285.15:49:46.24#ibcon#*before return 0, iclass 40, count 0 2006.285.15:49:46.24#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:49:46.24#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.15:49:46.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.15:49:46.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.15:49:46.24$vck44/vblo=8,744.99 2006.285.15:49:46.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.15:49:46.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.15:49:46.24#ibcon#ireg 17 cls_cnt 0 2006.285.15:49:46.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:49:46.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:49:46.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:49:46.24#ibcon#enter wrdev, iclass 4, count 0 2006.285.15:49:46.24#ibcon#first serial, iclass 4, count 0 2006.285.15:49:46.24#ibcon#enter sib2, iclass 4, count 0 2006.285.15:49:46.24#ibcon#flushed, iclass 4, count 0 2006.285.15:49:46.24#ibcon#about to write, iclass 4, count 0 2006.285.15:49:46.40#ibcon#wrote, iclass 4, count 0 2006.285.15:49:46.40#ibcon#about to read 3, iclass 4, count 0 2006.285.15:49:46.42#ibcon#read 3, iclass 4, count 0 2006.285.15:49:46.42#ibcon#about to read 4, iclass 4, count 0 2006.285.15:49:46.42#ibcon#read 4, iclass 4, count 0 2006.285.15:49:46.42#ibcon#about to read 5, iclass 4, count 0 2006.285.15:49:46.42#ibcon#read 5, iclass 4, count 0 2006.285.15:49:46.42#ibcon#about to read 6, iclass 4, count 0 2006.285.15:49:46.42#ibcon#read 6, iclass 4, count 0 2006.285.15:49:46.42#ibcon#end of sib2, iclass 4, count 0 2006.285.15:49:46.42#ibcon#*mode == 0, iclass 4, count 0 2006.285.15:49:46.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.15:49:46.42#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.15:49:46.42#ibcon#*before write, iclass 4, count 0 2006.285.15:49:46.42#ibcon#enter sib2, iclass 4, count 0 2006.285.15:49:46.42#ibcon#flushed, iclass 4, count 0 2006.285.15:49:46.42#ibcon#about to write, iclass 4, count 0 2006.285.15:49:46.42#ibcon#wrote, iclass 4, count 0 2006.285.15:49:46.42#ibcon#about to read 3, iclass 4, count 0 2006.285.15:49:46.46#ibcon#read 3, iclass 4, count 0 2006.285.15:49:46.46#ibcon#about to read 4, iclass 4, count 0 2006.285.15:49:46.46#ibcon#read 4, iclass 4, count 0 2006.285.15:49:46.46#ibcon#about to read 5, iclass 4, count 0 2006.285.15:49:46.46#ibcon#read 5, iclass 4, count 0 2006.285.15:49:46.46#ibcon#about to read 6, iclass 4, count 0 2006.285.15:49:46.46#ibcon#read 6, iclass 4, count 0 2006.285.15:49:46.46#ibcon#end of sib2, iclass 4, count 0 2006.285.15:49:46.46#ibcon#*after write, iclass 4, count 0 2006.285.15:49:46.46#ibcon#*before return 0, iclass 4, count 0 2006.285.15:49:46.46#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:49:46.46#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.15:49:46.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.15:49:46.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.15:49:46.46$vck44/vb=8,4 2006.285.15:49:46.46#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.15:49:46.46#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.15:49:46.46#ibcon#ireg 11 cls_cnt 2 2006.285.15:49:46.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:49:46.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:49:46.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:49:46.46#ibcon#enter wrdev, iclass 6, count 2 2006.285.15:49:46.46#ibcon#first serial, iclass 6, count 2 2006.285.15:49:46.46#ibcon#enter sib2, iclass 6, count 2 2006.285.15:49:46.46#ibcon#flushed, iclass 6, count 2 2006.285.15:49:46.46#ibcon#about to write, iclass 6, count 2 2006.285.15:49:46.46#ibcon#wrote, iclass 6, count 2 2006.285.15:49:46.46#ibcon#about to read 3, iclass 6, count 2 2006.285.15:49:46.48#ibcon#read 3, iclass 6, count 2 2006.285.15:49:46.48#ibcon#about to read 4, iclass 6, count 2 2006.285.15:49:46.48#ibcon#read 4, iclass 6, count 2 2006.285.15:49:46.48#ibcon#about to read 5, iclass 6, count 2 2006.285.15:49:46.48#ibcon#read 5, iclass 6, count 2 2006.285.15:49:46.48#ibcon#about to read 6, iclass 6, count 2 2006.285.15:49:46.48#ibcon#read 6, iclass 6, count 2 2006.285.15:49:46.48#ibcon#end of sib2, iclass 6, count 2 2006.285.15:49:46.48#ibcon#*mode == 0, iclass 6, count 2 2006.285.15:49:46.48#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.15:49:46.48#ibcon#[27=AT08-04\r\n] 2006.285.15:49:46.48#ibcon#*before write, iclass 6, count 2 2006.285.15:49:46.48#ibcon#enter sib2, iclass 6, count 2 2006.285.15:49:46.48#ibcon#flushed, iclass 6, count 2 2006.285.15:49:46.48#ibcon#about to write, iclass 6, count 2 2006.285.15:49:46.48#ibcon#wrote, iclass 6, count 2 2006.285.15:49:46.48#ibcon#about to read 3, iclass 6, count 2 2006.285.15:49:46.51#ibcon#read 3, iclass 6, count 2 2006.285.15:49:46.51#ibcon#about to read 4, iclass 6, count 2 2006.285.15:49:46.51#ibcon#read 4, iclass 6, count 2 2006.285.15:49:46.51#ibcon#about to read 5, iclass 6, count 2 2006.285.15:49:46.51#ibcon#read 5, iclass 6, count 2 2006.285.15:49:46.51#ibcon#about to read 6, iclass 6, count 2 2006.285.15:49:46.51#ibcon#read 6, iclass 6, count 2 2006.285.15:49:46.51#ibcon#end of sib2, iclass 6, count 2 2006.285.15:49:46.51#ibcon#*after write, iclass 6, count 2 2006.285.15:49:46.51#ibcon#*before return 0, iclass 6, count 2 2006.285.15:49:46.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:49:46.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.15:49:46.51#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.15:49:46.51#ibcon#ireg 7 cls_cnt 0 2006.285.15:49:46.51#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:49:46.63#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:49:46.63#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:49:46.63#ibcon#enter wrdev, iclass 6, count 0 2006.285.15:49:46.63#ibcon#first serial, iclass 6, count 0 2006.285.15:49:46.63#ibcon#enter sib2, iclass 6, count 0 2006.285.15:49:46.63#ibcon#flushed, iclass 6, count 0 2006.285.15:49:46.63#ibcon#about to write, iclass 6, count 0 2006.285.15:49:46.63#ibcon#wrote, iclass 6, count 0 2006.285.15:49:46.63#ibcon#about to read 3, iclass 6, count 0 2006.285.15:49:46.65#ibcon#read 3, iclass 6, count 0 2006.285.15:49:46.65#ibcon#about to read 4, iclass 6, count 0 2006.285.15:49:46.65#ibcon#read 4, iclass 6, count 0 2006.285.15:49:46.65#ibcon#about to read 5, iclass 6, count 0 2006.285.15:49:46.65#ibcon#read 5, iclass 6, count 0 2006.285.15:49:46.65#ibcon#about to read 6, iclass 6, count 0 2006.285.15:49:46.65#ibcon#read 6, iclass 6, count 0 2006.285.15:49:46.65#ibcon#end of sib2, iclass 6, count 0 2006.285.15:49:46.65#ibcon#*mode == 0, iclass 6, count 0 2006.285.15:49:46.65#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.15:49:46.65#ibcon#[27=USB\r\n] 2006.285.15:49:46.65#ibcon#*before write, iclass 6, count 0 2006.285.15:49:46.65#ibcon#enter sib2, iclass 6, count 0 2006.285.15:49:46.65#ibcon#flushed, iclass 6, count 0 2006.285.15:49:46.65#ibcon#about to write, iclass 6, count 0 2006.285.15:49:46.65#ibcon#wrote, iclass 6, count 0 2006.285.15:49:46.65#ibcon#about to read 3, iclass 6, count 0 2006.285.15:49:46.68#ibcon#read 3, iclass 6, count 0 2006.285.15:49:46.68#ibcon#about to read 4, iclass 6, count 0 2006.285.15:49:46.68#ibcon#read 4, iclass 6, count 0 2006.285.15:49:46.68#ibcon#about to read 5, iclass 6, count 0 2006.285.15:49:46.68#ibcon#read 5, iclass 6, count 0 2006.285.15:49:46.68#ibcon#about to read 6, iclass 6, count 0 2006.285.15:49:46.68#ibcon#read 6, iclass 6, count 0 2006.285.15:49:46.68#ibcon#end of sib2, iclass 6, count 0 2006.285.15:49:46.68#ibcon#*after write, iclass 6, count 0 2006.285.15:49:46.68#ibcon#*before return 0, iclass 6, count 0 2006.285.15:49:46.68#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:49:46.68#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.15:49:46.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.15:49:46.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.15:49:46.68$vck44/vabw=wide 2006.285.15:49:46.68#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.15:49:46.68#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.15:49:46.68#ibcon#ireg 8 cls_cnt 0 2006.285.15:49:46.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:49:46.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:49:46.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:49:46.68#ibcon#enter wrdev, iclass 10, count 0 2006.285.15:49:46.68#ibcon#first serial, iclass 10, count 0 2006.285.15:49:46.68#ibcon#enter sib2, iclass 10, count 0 2006.285.15:49:46.68#ibcon#flushed, iclass 10, count 0 2006.285.15:49:46.68#ibcon#about to write, iclass 10, count 0 2006.285.15:49:46.68#ibcon#wrote, iclass 10, count 0 2006.285.15:49:46.68#ibcon#about to read 3, iclass 10, count 0 2006.285.15:49:46.70#ibcon#read 3, iclass 10, count 0 2006.285.15:49:46.70#ibcon#about to read 4, iclass 10, count 0 2006.285.15:49:46.70#ibcon#read 4, iclass 10, count 0 2006.285.15:49:46.70#ibcon#about to read 5, iclass 10, count 0 2006.285.15:49:46.70#ibcon#read 5, iclass 10, count 0 2006.285.15:49:46.70#ibcon#about to read 6, iclass 10, count 0 2006.285.15:49:46.70#ibcon#read 6, iclass 10, count 0 2006.285.15:49:46.70#ibcon#end of sib2, iclass 10, count 0 2006.285.15:49:46.70#ibcon#*mode == 0, iclass 10, count 0 2006.285.15:49:46.70#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.15:49:46.70#ibcon#[25=BW32\r\n] 2006.285.15:49:46.70#ibcon#*before write, iclass 10, count 0 2006.285.15:49:46.70#ibcon#enter sib2, iclass 10, count 0 2006.285.15:49:46.70#ibcon#flushed, iclass 10, count 0 2006.285.15:49:46.70#ibcon#about to write, iclass 10, count 0 2006.285.15:49:46.70#ibcon#wrote, iclass 10, count 0 2006.285.15:49:46.70#ibcon#about to read 3, iclass 10, count 0 2006.285.15:49:46.73#ibcon#read 3, iclass 10, count 0 2006.285.15:49:46.73#ibcon#about to read 4, iclass 10, count 0 2006.285.15:49:46.73#ibcon#read 4, iclass 10, count 0 2006.285.15:49:46.73#ibcon#about to read 5, iclass 10, count 0 2006.285.15:49:46.73#ibcon#read 5, iclass 10, count 0 2006.285.15:49:46.73#ibcon#about to read 6, iclass 10, count 0 2006.285.15:49:46.73#ibcon#read 6, iclass 10, count 0 2006.285.15:49:46.73#ibcon#end of sib2, iclass 10, count 0 2006.285.15:49:46.73#ibcon#*after write, iclass 10, count 0 2006.285.15:49:46.73#ibcon#*before return 0, iclass 10, count 0 2006.285.15:49:46.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:49:46.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.15:49:46.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.15:49:46.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.15:49:46.73$vck44/vbbw=wide 2006.285.15:49:46.73#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.15:49:46.73#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.15:49:46.73#ibcon#ireg 8 cls_cnt 0 2006.285.15:49:46.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:49:46.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:49:46.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:49:46.80#ibcon#enter wrdev, iclass 12, count 0 2006.285.15:49:46.80#ibcon#first serial, iclass 12, count 0 2006.285.15:49:46.80#ibcon#enter sib2, iclass 12, count 0 2006.285.15:49:46.80#ibcon#flushed, iclass 12, count 0 2006.285.15:49:46.80#ibcon#about to write, iclass 12, count 0 2006.285.15:49:46.80#ibcon#wrote, iclass 12, count 0 2006.285.15:49:46.80#ibcon#about to read 3, iclass 12, count 0 2006.285.15:49:46.82#ibcon#read 3, iclass 12, count 0 2006.285.15:49:46.82#ibcon#about to read 4, iclass 12, count 0 2006.285.15:49:46.82#ibcon#read 4, iclass 12, count 0 2006.285.15:49:46.82#ibcon#about to read 5, iclass 12, count 0 2006.285.15:49:46.82#ibcon#read 5, iclass 12, count 0 2006.285.15:49:46.82#ibcon#about to read 6, iclass 12, count 0 2006.285.15:49:46.82#ibcon#read 6, iclass 12, count 0 2006.285.15:49:46.82#ibcon#end of sib2, iclass 12, count 0 2006.285.15:49:46.82#ibcon#*mode == 0, iclass 12, count 0 2006.285.15:49:46.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.15:49:46.82#ibcon#[27=BW32\r\n] 2006.285.15:49:46.82#ibcon#*before write, iclass 12, count 0 2006.285.15:49:46.82#ibcon#enter sib2, iclass 12, count 0 2006.285.15:49:46.82#ibcon#flushed, iclass 12, count 0 2006.285.15:49:46.82#ibcon#about to write, iclass 12, count 0 2006.285.15:49:46.82#ibcon#wrote, iclass 12, count 0 2006.285.15:49:46.82#ibcon#about to read 3, iclass 12, count 0 2006.285.15:49:46.85#ibcon#read 3, iclass 12, count 0 2006.285.15:49:46.85#ibcon#about to read 4, iclass 12, count 0 2006.285.15:49:46.85#ibcon#read 4, iclass 12, count 0 2006.285.15:49:46.85#ibcon#about to read 5, iclass 12, count 0 2006.285.15:49:46.85#ibcon#read 5, iclass 12, count 0 2006.285.15:49:46.85#ibcon#about to read 6, iclass 12, count 0 2006.285.15:49:46.85#ibcon#read 6, iclass 12, count 0 2006.285.15:49:46.85#ibcon#end of sib2, iclass 12, count 0 2006.285.15:49:46.85#ibcon#*after write, iclass 12, count 0 2006.285.15:49:46.85#ibcon#*before return 0, iclass 12, count 0 2006.285.15:49:46.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:49:46.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:49:46.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.15:49:46.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.15:49:46.85$setupk4/ifdk4 2006.285.15:49:46.85$ifdk4/lo= 2006.285.15:49:46.85$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.15:49:46.85$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.15:49:46.85$ifdk4/patch= 2006.285.15:49:46.85$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.15:49:46.85$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.15:49:46.85$setupk4/!*+20s 2006.285.15:49:47.56#abcon#<5=/16 0.9 2.6 18.81 921015.0\r\n> 2006.285.15:49:47.58#abcon#{5=INTERFACE CLEAR} 2006.285.15:49:47.64#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:49:57.73#abcon#<5=/16 0.9 2.6 18.81 921015.0\r\n> 2006.285.15:49:57.75#abcon#{5=INTERFACE CLEAR} 2006.285.15:49:57.81#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:50:00.54$setupk4/"tpicd 2006.285.15:50:00.54$setupk4/echo=off 2006.285.15:50:00.54$setupk4/xlog=off 2006.285.15:50:00.54:!2006.285.15:52:01 2006.285.15:50:11.14#trakl#Source acquired 2006.285.15:50:13.14#flagr#flagr/antenna,acquired 2006.285.15:52:01.00:preob 2006.285.15:52:02.14/onsource/TRACKING 2006.285.15:52:02.14:!2006.285.15:52:11 2006.285.15:52:11.00:"tape 2006.285.15:52:11.00:"st=record 2006.285.15:52:11.00:data_valid=on 2006.285.15:52:11.00:midob 2006.285.15:52:11.14/onsource/TRACKING 2006.285.15:52:11.14/wx/18.76,1015.0,93 2006.285.15:52:11.23/cable/+6.4983E-03 2006.285.15:52:12.32/va/01,07,usb,yes,32,34 2006.285.15:52:12.32/va/02,06,usb,yes,32,32 2006.285.15:52:12.32/va/03,07,usb,yes,31,33 2006.285.15:52:12.32/va/04,06,usb,yes,33,34 2006.285.15:52:12.32/va/05,03,usb,yes,32,33 2006.285.15:52:12.32/va/06,04,usb,yes,29,29 2006.285.15:52:12.32/va/07,04,usb,yes,30,30 2006.285.15:52:12.32/va/08,03,usb,yes,30,37 2006.285.15:52:12.55/valo/01,524.99,yes,locked 2006.285.15:52:12.55/valo/02,534.99,yes,locked 2006.285.15:52:12.55/valo/03,564.99,yes,locked 2006.285.15:52:12.55/valo/04,624.99,yes,locked 2006.285.15:52:12.55/valo/05,734.99,yes,locked 2006.285.15:52:12.55/valo/06,814.99,yes,locked 2006.285.15:52:12.55/valo/07,864.99,yes,locked 2006.285.15:52:12.55/valo/08,884.99,yes,locked 2006.285.15:52:13.64/vb/01,04,usb,yes,30,28 2006.285.15:52:13.64/vb/02,05,usb,yes,28,28 2006.285.15:52:13.64/vb/03,04,usb,yes,29,32 2006.285.15:52:13.64/vb/04,05,usb,yes,30,29 2006.285.15:52:13.64/vb/05,04,usb,yes,26,28 2006.285.15:52:13.64/vb/06,03,usb,yes,37,33 2006.285.15:52:13.64/vb/07,04,usb,yes,30,30 2006.285.15:52:13.64/vb/08,04,usb,yes,28,31 2006.285.15:52:13.88/vblo/01,629.99,yes,locked 2006.285.15:52:13.88/vblo/02,634.99,yes,locked 2006.285.15:52:13.88/vblo/03,649.99,yes,locked 2006.285.15:52:13.88/vblo/04,679.99,yes,locked 2006.285.15:52:13.88/vblo/05,709.99,yes,locked 2006.285.15:52:13.88/vblo/06,719.99,yes,locked 2006.285.15:52:13.88/vblo/07,734.99,yes,locked 2006.285.15:52:13.88/vblo/08,744.99,yes,locked 2006.285.15:52:14.03/vabw/8 2006.285.15:52:14.18/vbbw/8 2006.285.15:52:14.27/xfe/off,on,12.0 2006.285.15:52:14.65/ifatt/23,28,28,28 2006.285.15:52:15.08/fmout-gps/S +2.58E-07 2006.285.15:52:15.10:!2006.285.15:53:01 2006.285.15:53:01.01:data_valid=off 2006.285.15:53:01.01:"et 2006.285.15:53:01.01:!+3s 2006.285.15:53:04.02:"tape 2006.285.15:53:04.02:postob 2006.285.15:53:04.19/cable/+6.5004E-03 2006.285.15:53:04.19/wx/18.74,1015.0,93 2006.285.15:53:05.08/fmout-gps/S +2.60E-07 2006.285.15:53:05.08:scan_name=285-1555,jd0610,110 2006.285.15:53:05.08:source=0528+134,053056.42,133155.1,2000.0,cw 2006.285.15:53:06.13#flagr#flagr/antenna,new-source 2006.285.15:53:06.13:checkk5 2006.285.15:53:06.89/chk_autoobs//k5ts1/ autoobs is running! 2006.285.15:53:07.34/chk_autoobs//k5ts2/ autoobs is running! 2006.285.15:53:07.74/chk_autoobs//k5ts3/ autoobs is running! 2006.285.15:53:08.12/chk_autoobs//k5ts4/ autoobs is running! 2006.285.15:53:08.52/chk_obsdata//k5ts1/T2851552??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.15:53:08.89/chk_obsdata//k5ts2/T2851552??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.15:53:09.33/chk_obsdata//k5ts3/T2851552??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.15:53:09.72/chk_obsdata//k5ts4/T2851552??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.15:53:10.87/k5log//k5ts1_log_newline 2006.285.15:53:12.37/k5log//k5ts2_log_newline 2006.285.15:53:13.17/k5log//k5ts3_log_newline 2006.285.15:53:13.93/k5log//k5ts4_log_newline 2006.285.15:53:13.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.15:53:13.95:setupk4=1 2006.285.15:53:13.95$setupk4/echo=on 2006.285.15:53:13.95$setupk4/pcalon 2006.285.15:53:13.95$pcalon/"no phase cal control is implemented here 2006.285.15:53:13.95$setupk4/"tpicd=stop 2006.285.15:53:13.95$setupk4/"rec=synch_on 2006.285.15:53:13.95$setupk4/"rec_mode=128 2006.285.15:53:13.95$setupk4/!* 2006.285.15:53:13.95$setupk4/recpk4 2006.285.15:53:13.95$recpk4/recpatch= 2006.285.15:53:13.96$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.15:53:13.96$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.15:53:13.96$setupk4/vck44 2006.285.15:53:13.96$vck44/valo=1,524.99 2006.285.15:53:13.96#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.15:53:13.96#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.15:53:13.96#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:13.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:53:13.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:53:13.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:53:13.96#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:53:13.96#ibcon#first serial, iclass 29, count 0 2006.285.15:53:13.96#ibcon#enter sib2, iclass 29, count 0 2006.285.15:53:13.96#ibcon#flushed, iclass 29, count 0 2006.285.15:53:13.96#ibcon#about to write, iclass 29, count 0 2006.285.15:53:13.96#ibcon#wrote, iclass 29, count 0 2006.285.15:53:13.96#ibcon#about to read 3, iclass 29, count 0 2006.285.15:53:13.98#ibcon#read 3, iclass 29, count 0 2006.285.15:53:13.98#ibcon#about to read 4, iclass 29, count 0 2006.285.15:53:13.98#ibcon#read 4, iclass 29, count 0 2006.285.15:53:13.98#ibcon#about to read 5, iclass 29, count 0 2006.285.15:53:13.98#ibcon#read 5, iclass 29, count 0 2006.285.15:53:13.98#ibcon#about to read 6, iclass 29, count 0 2006.285.15:53:13.98#ibcon#read 6, iclass 29, count 0 2006.285.15:53:13.98#ibcon#end of sib2, iclass 29, count 0 2006.285.15:53:13.98#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:53:13.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:53:13.98#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.15:53:13.98#ibcon#*before write, iclass 29, count 0 2006.285.15:53:13.98#ibcon#enter sib2, iclass 29, count 0 2006.285.15:53:13.98#ibcon#flushed, iclass 29, count 0 2006.285.15:53:13.98#ibcon#about to write, iclass 29, count 0 2006.285.15:53:13.98#ibcon#wrote, iclass 29, count 0 2006.285.15:53:13.98#ibcon#about to read 3, iclass 29, count 0 2006.285.15:53:14.03#ibcon#read 3, iclass 29, count 0 2006.285.15:53:14.03#ibcon#about to read 4, iclass 29, count 0 2006.285.15:53:14.03#ibcon#read 4, iclass 29, count 0 2006.285.15:53:14.03#ibcon#about to read 5, iclass 29, count 0 2006.285.15:53:14.03#ibcon#read 5, iclass 29, count 0 2006.285.15:53:14.03#ibcon#about to read 6, iclass 29, count 0 2006.285.15:53:14.03#ibcon#read 6, iclass 29, count 0 2006.285.15:53:14.03#ibcon#end of sib2, iclass 29, count 0 2006.285.15:53:14.03#ibcon#*after write, iclass 29, count 0 2006.285.15:53:14.03#ibcon#*before return 0, iclass 29, count 0 2006.285.15:53:14.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:53:14.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:53:14.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:53:14.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:53:14.03$vck44/va=1,7 2006.285.15:53:14.03#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.15:53:14.03#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.15:53:14.03#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:14.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:53:14.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:53:14.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:53:14.03#ibcon#enter wrdev, iclass 31, count 2 2006.285.15:53:14.03#ibcon#first serial, iclass 31, count 2 2006.285.15:53:14.03#ibcon#enter sib2, iclass 31, count 2 2006.285.15:53:14.03#ibcon#flushed, iclass 31, count 2 2006.285.15:53:14.03#ibcon#about to write, iclass 31, count 2 2006.285.15:53:14.03#ibcon#wrote, iclass 31, count 2 2006.285.15:53:14.03#ibcon#about to read 3, iclass 31, count 2 2006.285.15:53:14.05#ibcon#read 3, iclass 31, count 2 2006.285.15:53:14.05#ibcon#about to read 4, iclass 31, count 2 2006.285.15:53:14.05#ibcon#read 4, iclass 31, count 2 2006.285.15:53:14.05#ibcon#about to read 5, iclass 31, count 2 2006.285.15:53:14.05#ibcon#read 5, iclass 31, count 2 2006.285.15:53:14.05#ibcon#about to read 6, iclass 31, count 2 2006.285.15:53:14.05#ibcon#read 6, iclass 31, count 2 2006.285.15:53:14.05#ibcon#end of sib2, iclass 31, count 2 2006.285.15:53:14.05#ibcon#*mode == 0, iclass 31, count 2 2006.285.15:53:14.05#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.15:53:14.05#ibcon#[25=AT01-07\r\n] 2006.285.15:53:14.05#ibcon#*before write, iclass 31, count 2 2006.285.15:53:14.05#ibcon#enter sib2, iclass 31, count 2 2006.285.15:53:14.05#ibcon#flushed, iclass 31, count 2 2006.285.15:53:14.05#ibcon#about to write, iclass 31, count 2 2006.285.15:53:14.05#ibcon#wrote, iclass 31, count 2 2006.285.15:53:14.05#ibcon#about to read 3, iclass 31, count 2 2006.285.15:53:14.08#ibcon#read 3, iclass 31, count 2 2006.285.15:53:14.08#ibcon#about to read 4, iclass 31, count 2 2006.285.15:53:14.08#ibcon#read 4, iclass 31, count 2 2006.285.15:53:14.08#ibcon#about to read 5, iclass 31, count 2 2006.285.15:53:14.08#ibcon#read 5, iclass 31, count 2 2006.285.15:53:14.08#ibcon#about to read 6, iclass 31, count 2 2006.285.15:53:14.08#ibcon#read 6, iclass 31, count 2 2006.285.15:53:14.08#ibcon#end of sib2, iclass 31, count 2 2006.285.15:53:14.08#ibcon#*after write, iclass 31, count 2 2006.285.15:53:14.08#ibcon#*before return 0, iclass 31, count 2 2006.285.15:53:14.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:53:14.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:53:14.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.15:53:14.08#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:14.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:53:14.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:53:14.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:53:14.20#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:53:14.20#ibcon#first serial, iclass 31, count 0 2006.285.15:53:14.20#ibcon#enter sib2, iclass 31, count 0 2006.285.15:53:14.20#ibcon#flushed, iclass 31, count 0 2006.285.15:53:14.20#ibcon#about to write, iclass 31, count 0 2006.285.15:53:14.20#ibcon#wrote, iclass 31, count 0 2006.285.15:53:14.20#ibcon#about to read 3, iclass 31, count 0 2006.285.15:53:14.22#ibcon#read 3, iclass 31, count 0 2006.285.15:53:14.22#ibcon#about to read 4, iclass 31, count 0 2006.285.15:53:14.22#ibcon#read 4, iclass 31, count 0 2006.285.15:53:14.22#ibcon#about to read 5, iclass 31, count 0 2006.285.15:53:14.22#ibcon#read 5, iclass 31, count 0 2006.285.15:53:14.22#ibcon#about to read 6, iclass 31, count 0 2006.285.15:53:14.22#ibcon#read 6, iclass 31, count 0 2006.285.15:53:14.22#ibcon#end of sib2, iclass 31, count 0 2006.285.15:53:14.22#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:53:14.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:53:14.22#ibcon#[25=USB\r\n] 2006.285.15:53:14.22#ibcon#*before write, iclass 31, count 0 2006.285.15:53:14.22#ibcon#enter sib2, iclass 31, count 0 2006.285.15:53:14.22#ibcon#flushed, iclass 31, count 0 2006.285.15:53:14.22#ibcon#about to write, iclass 31, count 0 2006.285.15:53:14.22#ibcon#wrote, iclass 31, count 0 2006.285.15:53:14.22#ibcon#about to read 3, iclass 31, count 0 2006.285.15:53:14.25#ibcon#read 3, iclass 31, count 0 2006.285.15:53:14.25#ibcon#about to read 4, iclass 31, count 0 2006.285.15:53:14.25#ibcon#read 4, iclass 31, count 0 2006.285.15:53:14.25#ibcon#about to read 5, iclass 31, count 0 2006.285.15:53:14.25#ibcon#read 5, iclass 31, count 0 2006.285.15:53:14.25#ibcon#about to read 6, iclass 31, count 0 2006.285.15:53:14.25#ibcon#read 6, iclass 31, count 0 2006.285.15:53:14.25#ibcon#end of sib2, iclass 31, count 0 2006.285.15:53:14.25#ibcon#*after write, iclass 31, count 0 2006.285.15:53:14.25#ibcon#*before return 0, iclass 31, count 0 2006.285.15:53:14.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:53:14.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:53:14.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:53:14.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:53:14.25$vck44/valo=2,534.99 2006.285.15:53:14.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.15:53:14.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.15:53:14.25#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:14.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:53:14.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:53:14.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:53:14.25#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:53:14.25#ibcon#first serial, iclass 33, count 0 2006.285.15:53:14.25#ibcon#enter sib2, iclass 33, count 0 2006.285.15:53:14.25#ibcon#flushed, iclass 33, count 0 2006.285.15:53:14.25#ibcon#about to write, iclass 33, count 0 2006.285.15:53:14.25#ibcon#wrote, iclass 33, count 0 2006.285.15:53:14.25#ibcon#about to read 3, iclass 33, count 0 2006.285.15:53:14.73#ibcon#read 3, iclass 33, count 0 2006.285.15:53:14.73#ibcon#about to read 4, iclass 33, count 0 2006.285.15:53:14.73#ibcon#read 4, iclass 33, count 0 2006.285.15:53:14.73#ibcon#about to read 5, iclass 33, count 0 2006.285.15:53:14.73#ibcon#read 5, iclass 33, count 0 2006.285.15:53:14.73#ibcon#about to read 6, iclass 33, count 0 2006.285.15:53:14.73#ibcon#read 6, iclass 33, count 0 2006.285.15:53:14.73#ibcon#end of sib2, iclass 33, count 0 2006.285.15:53:14.73#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:53:14.73#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:53:14.73#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.15:53:14.73#ibcon#*before write, iclass 33, count 0 2006.285.15:53:14.73#ibcon#enter sib2, iclass 33, count 0 2006.285.15:53:14.73#ibcon#flushed, iclass 33, count 0 2006.285.15:53:14.73#ibcon#about to write, iclass 33, count 0 2006.285.15:53:14.73#ibcon#wrote, iclass 33, count 0 2006.285.15:53:14.73#ibcon#about to read 3, iclass 33, count 0 2006.285.15:53:14.77#ibcon#read 3, iclass 33, count 0 2006.285.15:53:14.77#ibcon#about to read 4, iclass 33, count 0 2006.285.15:53:14.77#ibcon#read 4, iclass 33, count 0 2006.285.15:53:14.77#ibcon#about to read 5, iclass 33, count 0 2006.285.15:53:14.77#ibcon#read 5, iclass 33, count 0 2006.285.15:53:14.77#ibcon#about to read 6, iclass 33, count 0 2006.285.15:53:14.77#ibcon#read 6, iclass 33, count 0 2006.285.15:53:14.77#ibcon#end of sib2, iclass 33, count 0 2006.285.15:53:14.77#ibcon#*after write, iclass 33, count 0 2006.285.15:53:14.77#ibcon#*before return 0, iclass 33, count 0 2006.285.15:53:14.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:53:14.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:53:14.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:53:14.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:53:14.77$vck44/va=2,6 2006.285.15:53:14.77#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.15:53:14.77#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.15:53:14.77#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:14.77#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:53:14.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:53:14.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:53:14.77#ibcon#enter wrdev, iclass 35, count 2 2006.285.15:53:14.77#ibcon#first serial, iclass 35, count 2 2006.285.15:53:14.77#ibcon#enter sib2, iclass 35, count 2 2006.285.15:53:14.77#ibcon#flushed, iclass 35, count 2 2006.285.15:53:14.77#ibcon#about to write, iclass 35, count 2 2006.285.15:53:14.77#ibcon#wrote, iclass 35, count 2 2006.285.15:53:14.77#ibcon#about to read 3, iclass 35, count 2 2006.285.15:53:14.79#ibcon#read 3, iclass 35, count 2 2006.285.15:53:14.79#ibcon#about to read 4, iclass 35, count 2 2006.285.15:53:14.79#ibcon#read 4, iclass 35, count 2 2006.285.15:53:14.79#ibcon#about to read 5, iclass 35, count 2 2006.285.15:53:14.79#ibcon#read 5, iclass 35, count 2 2006.285.15:53:14.79#ibcon#about to read 6, iclass 35, count 2 2006.285.15:53:14.79#ibcon#read 6, iclass 35, count 2 2006.285.15:53:14.79#ibcon#end of sib2, iclass 35, count 2 2006.285.15:53:14.79#ibcon#*mode == 0, iclass 35, count 2 2006.285.15:53:14.79#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.15:53:14.79#ibcon#[25=AT02-06\r\n] 2006.285.15:53:14.79#ibcon#*before write, iclass 35, count 2 2006.285.15:53:14.79#ibcon#enter sib2, iclass 35, count 2 2006.285.15:53:14.79#ibcon#flushed, iclass 35, count 2 2006.285.15:53:14.79#ibcon#about to write, iclass 35, count 2 2006.285.15:53:14.79#ibcon#wrote, iclass 35, count 2 2006.285.15:53:14.79#ibcon#about to read 3, iclass 35, count 2 2006.285.15:53:14.82#ibcon#read 3, iclass 35, count 2 2006.285.15:53:14.82#ibcon#about to read 4, iclass 35, count 2 2006.285.15:53:14.82#ibcon#read 4, iclass 35, count 2 2006.285.15:53:14.82#ibcon#about to read 5, iclass 35, count 2 2006.285.15:53:14.82#ibcon#read 5, iclass 35, count 2 2006.285.15:53:14.82#ibcon#about to read 6, iclass 35, count 2 2006.285.15:53:14.82#ibcon#read 6, iclass 35, count 2 2006.285.15:53:14.82#ibcon#end of sib2, iclass 35, count 2 2006.285.15:53:14.82#ibcon#*after write, iclass 35, count 2 2006.285.15:53:14.82#ibcon#*before return 0, iclass 35, count 2 2006.285.15:53:14.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:53:14.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:53:14.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.15:53:14.82#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:14.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:53:14.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:53:14.94#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:53:14.94#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:53:14.94#ibcon#first serial, iclass 35, count 0 2006.285.15:53:14.94#ibcon#enter sib2, iclass 35, count 0 2006.285.15:53:14.94#ibcon#flushed, iclass 35, count 0 2006.285.15:53:14.94#ibcon#about to write, iclass 35, count 0 2006.285.15:53:14.94#ibcon#wrote, iclass 35, count 0 2006.285.15:53:14.94#ibcon#about to read 3, iclass 35, count 0 2006.285.15:53:14.96#ibcon#read 3, iclass 35, count 0 2006.285.15:53:14.96#ibcon#about to read 4, iclass 35, count 0 2006.285.15:53:14.96#ibcon#read 4, iclass 35, count 0 2006.285.15:53:14.96#ibcon#about to read 5, iclass 35, count 0 2006.285.15:53:14.96#ibcon#read 5, iclass 35, count 0 2006.285.15:53:14.96#ibcon#about to read 6, iclass 35, count 0 2006.285.15:53:14.96#ibcon#read 6, iclass 35, count 0 2006.285.15:53:14.96#ibcon#end of sib2, iclass 35, count 0 2006.285.15:53:14.96#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:53:14.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:53:14.96#ibcon#[25=USB\r\n] 2006.285.15:53:14.96#ibcon#*before write, iclass 35, count 0 2006.285.15:53:14.96#ibcon#enter sib2, iclass 35, count 0 2006.285.15:53:14.96#ibcon#flushed, iclass 35, count 0 2006.285.15:53:14.96#ibcon#about to write, iclass 35, count 0 2006.285.15:53:14.96#ibcon#wrote, iclass 35, count 0 2006.285.15:53:14.96#ibcon#about to read 3, iclass 35, count 0 2006.285.15:53:14.99#ibcon#read 3, iclass 35, count 0 2006.285.15:53:14.99#ibcon#about to read 4, iclass 35, count 0 2006.285.15:53:14.99#ibcon#read 4, iclass 35, count 0 2006.285.15:53:14.99#ibcon#about to read 5, iclass 35, count 0 2006.285.15:53:14.99#ibcon#read 5, iclass 35, count 0 2006.285.15:53:14.99#ibcon#about to read 6, iclass 35, count 0 2006.285.15:53:14.99#ibcon#read 6, iclass 35, count 0 2006.285.15:53:14.99#ibcon#end of sib2, iclass 35, count 0 2006.285.15:53:14.99#ibcon#*after write, iclass 35, count 0 2006.285.15:53:14.99#ibcon#*before return 0, iclass 35, count 0 2006.285.15:53:14.99#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:53:14.99#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:53:14.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:53:14.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:53:14.99$vck44/valo=3,564.99 2006.285.15:53:14.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.15:53:14.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.15:53:14.99#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:14.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:53:14.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:53:14.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:53:14.99#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:53:14.99#ibcon#first serial, iclass 37, count 0 2006.285.15:53:14.99#ibcon#enter sib2, iclass 37, count 0 2006.285.15:53:14.99#ibcon#flushed, iclass 37, count 0 2006.285.15:53:14.99#ibcon#about to write, iclass 37, count 0 2006.285.15:53:14.99#ibcon#wrote, iclass 37, count 0 2006.285.15:53:14.99#ibcon#about to read 3, iclass 37, count 0 2006.285.15:53:15.06#ibcon#read 3, iclass 37, count 0 2006.285.15:53:15.06#ibcon#about to read 4, iclass 37, count 0 2006.285.15:53:15.06#ibcon#read 4, iclass 37, count 0 2006.285.15:53:15.06#ibcon#about to read 5, iclass 37, count 0 2006.285.15:53:15.06#ibcon#read 5, iclass 37, count 0 2006.285.15:53:15.06#ibcon#about to read 6, iclass 37, count 0 2006.285.15:53:15.06#ibcon#read 6, iclass 37, count 0 2006.285.15:53:15.06#ibcon#end of sib2, iclass 37, count 0 2006.285.15:53:15.06#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:53:15.06#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:53:15.06#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.15:53:15.06#ibcon#*before write, iclass 37, count 0 2006.285.15:53:15.06#ibcon#enter sib2, iclass 37, count 0 2006.285.15:53:15.06#ibcon#flushed, iclass 37, count 0 2006.285.15:53:15.06#ibcon#about to write, iclass 37, count 0 2006.285.15:53:15.06#ibcon#wrote, iclass 37, count 0 2006.285.15:53:15.06#ibcon#about to read 3, iclass 37, count 0 2006.285.15:53:15.10#ibcon#read 3, iclass 37, count 0 2006.285.15:53:15.10#ibcon#about to read 4, iclass 37, count 0 2006.285.15:53:15.10#ibcon#read 4, iclass 37, count 0 2006.285.15:53:15.10#ibcon#about to read 5, iclass 37, count 0 2006.285.15:53:15.10#ibcon#read 5, iclass 37, count 0 2006.285.15:53:15.10#ibcon#about to read 6, iclass 37, count 0 2006.285.15:53:15.10#ibcon#read 6, iclass 37, count 0 2006.285.15:53:15.10#ibcon#end of sib2, iclass 37, count 0 2006.285.15:53:15.10#ibcon#*after write, iclass 37, count 0 2006.285.15:53:15.10#ibcon#*before return 0, iclass 37, count 0 2006.285.15:53:15.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:53:15.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:53:15.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:53:15.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:53:15.10$vck44/va=3,7 2006.285.15:53:15.10#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.15:53:15.10#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.15:53:15.10#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:15.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:53:15.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:53:15.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:53:15.10#ibcon#enter wrdev, iclass 39, count 2 2006.285.15:53:15.10#ibcon#first serial, iclass 39, count 2 2006.285.15:53:15.10#ibcon#enter sib2, iclass 39, count 2 2006.285.15:53:15.10#ibcon#flushed, iclass 39, count 2 2006.285.15:53:15.10#ibcon#about to write, iclass 39, count 2 2006.285.15:53:15.10#ibcon#wrote, iclass 39, count 2 2006.285.15:53:15.10#ibcon#about to read 3, iclass 39, count 2 2006.285.15:53:15.12#ibcon#read 3, iclass 39, count 2 2006.285.15:53:15.12#ibcon#about to read 4, iclass 39, count 2 2006.285.15:53:15.12#ibcon#read 4, iclass 39, count 2 2006.285.15:53:15.12#ibcon#about to read 5, iclass 39, count 2 2006.285.15:53:15.12#ibcon#read 5, iclass 39, count 2 2006.285.15:53:15.12#ibcon#about to read 6, iclass 39, count 2 2006.285.15:53:15.12#ibcon#read 6, iclass 39, count 2 2006.285.15:53:15.12#ibcon#end of sib2, iclass 39, count 2 2006.285.15:53:15.12#ibcon#*mode == 0, iclass 39, count 2 2006.285.15:53:15.12#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.15:53:15.12#ibcon#[25=AT03-07\r\n] 2006.285.15:53:15.12#ibcon#*before write, iclass 39, count 2 2006.285.15:53:15.12#ibcon#enter sib2, iclass 39, count 2 2006.285.15:53:15.12#ibcon#flushed, iclass 39, count 2 2006.285.15:53:15.12#ibcon#about to write, iclass 39, count 2 2006.285.15:53:15.12#ibcon#wrote, iclass 39, count 2 2006.285.15:53:15.12#ibcon#about to read 3, iclass 39, count 2 2006.285.15:53:15.15#ibcon#read 3, iclass 39, count 2 2006.285.15:53:15.15#ibcon#about to read 4, iclass 39, count 2 2006.285.15:53:15.15#ibcon#read 4, iclass 39, count 2 2006.285.15:53:15.15#ibcon#about to read 5, iclass 39, count 2 2006.285.15:53:15.15#ibcon#read 5, iclass 39, count 2 2006.285.15:53:15.15#ibcon#about to read 6, iclass 39, count 2 2006.285.15:53:15.15#ibcon#read 6, iclass 39, count 2 2006.285.15:53:15.15#ibcon#end of sib2, iclass 39, count 2 2006.285.15:53:15.15#ibcon#*after write, iclass 39, count 2 2006.285.15:53:15.15#ibcon#*before return 0, iclass 39, count 2 2006.285.15:53:15.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:53:15.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:53:15.15#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.15:53:15.15#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:15.15#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:53:15.27#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:53:15.27#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:53:15.27#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:53:15.27#ibcon#first serial, iclass 39, count 0 2006.285.15:53:15.27#ibcon#enter sib2, iclass 39, count 0 2006.285.15:53:15.27#ibcon#flushed, iclass 39, count 0 2006.285.15:53:15.27#ibcon#about to write, iclass 39, count 0 2006.285.15:53:15.27#ibcon#wrote, iclass 39, count 0 2006.285.15:53:15.27#ibcon#about to read 3, iclass 39, count 0 2006.285.15:53:15.29#ibcon#read 3, iclass 39, count 0 2006.285.15:53:15.29#ibcon#about to read 4, iclass 39, count 0 2006.285.15:53:15.29#ibcon#read 4, iclass 39, count 0 2006.285.15:53:15.29#ibcon#about to read 5, iclass 39, count 0 2006.285.15:53:15.29#ibcon#read 5, iclass 39, count 0 2006.285.15:53:15.29#ibcon#about to read 6, iclass 39, count 0 2006.285.15:53:15.29#ibcon#read 6, iclass 39, count 0 2006.285.15:53:15.29#ibcon#end of sib2, iclass 39, count 0 2006.285.15:53:15.29#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:53:15.29#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:53:15.29#ibcon#[25=USB\r\n] 2006.285.15:53:15.29#ibcon#*before write, iclass 39, count 0 2006.285.15:53:15.29#ibcon#enter sib2, iclass 39, count 0 2006.285.15:53:15.29#ibcon#flushed, iclass 39, count 0 2006.285.15:53:15.29#ibcon#about to write, iclass 39, count 0 2006.285.15:53:15.29#ibcon#wrote, iclass 39, count 0 2006.285.15:53:15.29#ibcon#about to read 3, iclass 39, count 0 2006.285.15:53:15.32#ibcon#read 3, iclass 39, count 0 2006.285.15:53:15.32#ibcon#about to read 4, iclass 39, count 0 2006.285.15:53:15.32#ibcon#read 4, iclass 39, count 0 2006.285.15:53:15.32#ibcon#about to read 5, iclass 39, count 0 2006.285.15:53:15.32#ibcon#read 5, iclass 39, count 0 2006.285.15:53:15.32#ibcon#about to read 6, iclass 39, count 0 2006.285.15:53:15.32#ibcon#read 6, iclass 39, count 0 2006.285.15:53:15.32#ibcon#end of sib2, iclass 39, count 0 2006.285.15:53:15.32#ibcon#*after write, iclass 39, count 0 2006.285.15:53:15.32#ibcon#*before return 0, iclass 39, count 0 2006.285.15:53:15.32#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:53:15.32#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:53:15.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:53:15.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:53:15.32$vck44/valo=4,624.99 2006.285.15:53:15.32#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.15:53:15.32#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.15:53:15.32#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:15.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:53:15.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:53:15.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:53:15.32#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:53:15.32#ibcon#first serial, iclass 3, count 0 2006.285.15:53:15.32#ibcon#enter sib2, iclass 3, count 0 2006.285.15:53:15.32#ibcon#flushed, iclass 3, count 0 2006.285.15:53:15.32#ibcon#about to write, iclass 3, count 0 2006.285.15:53:15.32#ibcon#wrote, iclass 3, count 0 2006.285.15:53:15.32#ibcon#about to read 3, iclass 3, count 0 2006.285.15:53:15.34#ibcon#read 3, iclass 3, count 0 2006.285.15:53:15.34#ibcon#about to read 4, iclass 3, count 0 2006.285.15:53:15.34#ibcon#read 4, iclass 3, count 0 2006.285.15:53:15.34#ibcon#about to read 5, iclass 3, count 0 2006.285.15:53:15.34#ibcon#read 5, iclass 3, count 0 2006.285.15:53:15.34#ibcon#about to read 6, iclass 3, count 0 2006.285.15:53:15.34#ibcon#read 6, iclass 3, count 0 2006.285.15:53:15.34#ibcon#end of sib2, iclass 3, count 0 2006.285.15:53:15.34#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:53:15.34#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:53:15.34#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.15:53:15.34#ibcon#*before write, iclass 3, count 0 2006.285.15:53:15.34#ibcon#enter sib2, iclass 3, count 0 2006.285.15:53:15.34#ibcon#flushed, iclass 3, count 0 2006.285.15:53:15.34#ibcon#about to write, iclass 3, count 0 2006.285.15:53:15.34#ibcon#wrote, iclass 3, count 0 2006.285.15:53:15.34#ibcon#about to read 3, iclass 3, count 0 2006.285.15:53:15.38#ibcon#read 3, iclass 3, count 0 2006.285.15:53:15.38#ibcon#about to read 4, iclass 3, count 0 2006.285.15:53:15.38#ibcon#read 4, iclass 3, count 0 2006.285.15:53:15.38#ibcon#about to read 5, iclass 3, count 0 2006.285.15:53:15.38#ibcon#read 5, iclass 3, count 0 2006.285.15:53:15.38#ibcon#about to read 6, iclass 3, count 0 2006.285.15:53:15.38#ibcon#read 6, iclass 3, count 0 2006.285.15:53:15.38#ibcon#end of sib2, iclass 3, count 0 2006.285.15:53:15.38#ibcon#*after write, iclass 3, count 0 2006.285.15:53:15.38#ibcon#*before return 0, iclass 3, count 0 2006.285.15:53:15.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:53:15.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:53:15.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:53:15.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:53:15.38$vck44/va=4,6 2006.285.15:53:15.38#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.15:53:15.38#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.15:53:15.38#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:15.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:53:15.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:53:15.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:53:15.44#ibcon#enter wrdev, iclass 5, count 2 2006.285.15:53:15.44#ibcon#first serial, iclass 5, count 2 2006.285.15:53:15.44#ibcon#enter sib2, iclass 5, count 2 2006.285.15:53:15.44#ibcon#flushed, iclass 5, count 2 2006.285.15:53:15.44#ibcon#about to write, iclass 5, count 2 2006.285.15:53:15.44#ibcon#wrote, iclass 5, count 2 2006.285.15:53:15.44#ibcon#about to read 3, iclass 5, count 2 2006.285.15:53:15.46#ibcon#read 3, iclass 5, count 2 2006.285.15:53:15.46#ibcon#about to read 4, iclass 5, count 2 2006.285.15:53:15.46#ibcon#read 4, iclass 5, count 2 2006.285.15:53:15.46#ibcon#about to read 5, iclass 5, count 2 2006.285.15:53:15.46#ibcon#read 5, iclass 5, count 2 2006.285.15:53:15.46#ibcon#about to read 6, iclass 5, count 2 2006.285.15:53:15.46#ibcon#read 6, iclass 5, count 2 2006.285.15:53:15.46#ibcon#end of sib2, iclass 5, count 2 2006.285.15:53:15.46#ibcon#*mode == 0, iclass 5, count 2 2006.285.15:53:15.46#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.15:53:15.46#ibcon#[25=AT04-06\r\n] 2006.285.15:53:15.46#ibcon#*before write, iclass 5, count 2 2006.285.15:53:15.46#ibcon#enter sib2, iclass 5, count 2 2006.285.15:53:15.46#ibcon#flushed, iclass 5, count 2 2006.285.15:53:15.46#ibcon#about to write, iclass 5, count 2 2006.285.15:53:15.46#ibcon#wrote, iclass 5, count 2 2006.285.15:53:15.46#ibcon#about to read 3, iclass 5, count 2 2006.285.15:53:15.49#ibcon#read 3, iclass 5, count 2 2006.285.15:53:15.54#ibcon#about to read 4, iclass 5, count 2 2006.285.15:53:15.54#ibcon#read 4, iclass 5, count 2 2006.285.15:53:15.54#ibcon#about to read 5, iclass 5, count 2 2006.285.15:53:15.54#ibcon#read 5, iclass 5, count 2 2006.285.15:53:15.54#ibcon#about to read 6, iclass 5, count 2 2006.285.15:53:15.54#ibcon#read 6, iclass 5, count 2 2006.285.15:53:15.54#ibcon#end of sib2, iclass 5, count 2 2006.285.15:53:15.54#ibcon#*after write, iclass 5, count 2 2006.285.15:53:15.54#ibcon#*before return 0, iclass 5, count 2 2006.285.15:53:15.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:53:15.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:53:15.54#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.15:53:15.54#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:15.54#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:53:15.66#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:53:15.66#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:53:15.66#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:53:15.66#ibcon#first serial, iclass 5, count 0 2006.285.15:53:15.66#ibcon#enter sib2, iclass 5, count 0 2006.285.15:53:15.66#ibcon#flushed, iclass 5, count 0 2006.285.15:53:15.66#ibcon#about to write, iclass 5, count 0 2006.285.15:53:15.66#ibcon#wrote, iclass 5, count 0 2006.285.15:53:15.66#ibcon#about to read 3, iclass 5, count 0 2006.285.15:53:15.68#ibcon#read 3, iclass 5, count 0 2006.285.15:53:15.68#ibcon#about to read 4, iclass 5, count 0 2006.285.15:53:15.68#ibcon#read 4, iclass 5, count 0 2006.285.15:53:15.68#ibcon#about to read 5, iclass 5, count 0 2006.285.15:53:15.68#ibcon#read 5, iclass 5, count 0 2006.285.15:53:15.68#ibcon#about to read 6, iclass 5, count 0 2006.285.15:53:15.68#ibcon#read 6, iclass 5, count 0 2006.285.15:53:15.68#ibcon#end of sib2, iclass 5, count 0 2006.285.15:53:15.68#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:53:15.68#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:53:15.68#ibcon#[25=USB\r\n] 2006.285.15:53:15.68#ibcon#*before write, iclass 5, count 0 2006.285.15:53:15.68#ibcon#enter sib2, iclass 5, count 0 2006.285.15:53:15.68#ibcon#flushed, iclass 5, count 0 2006.285.15:53:15.68#ibcon#about to write, iclass 5, count 0 2006.285.15:53:15.68#ibcon#wrote, iclass 5, count 0 2006.285.15:53:15.68#ibcon#about to read 3, iclass 5, count 0 2006.285.15:53:15.71#ibcon#read 3, iclass 5, count 0 2006.285.15:53:15.71#ibcon#about to read 4, iclass 5, count 0 2006.285.15:53:15.71#ibcon#read 4, iclass 5, count 0 2006.285.15:53:15.71#ibcon#about to read 5, iclass 5, count 0 2006.285.15:53:15.71#ibcon#read 5, iclass 5, count 0 2006.285.15:53:15.71#ibcon#about to read 6, iclass 5, count 0 2006.285.15:53:15.71#ibcon#read 6, iclass 5, count 0 2006.285.15:53:15.71#ibcon#end of sib2, iclass 5, count 0 2006.285.15:53:15.71#ibcon#*after write, iclass 5, count 0 2006.285.15:53:15.71#ibcon#*before return 0, iclass 5, count 0 2006.285.15:53:15.71#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:53:15.71#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:53:15.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:53:15.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:53:15.71$vck44/valo=5,734.99 2006.285.15:53:15.71#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.15:53:15.71#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.15:53:15.71#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:15.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:53:15.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:53:15.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:53:15.71#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:53:15.71#ibcon#first serial, iclass 7, count 0 2006.285.15:53:15.71#ibcon#enter sib2, iclass 7, count 0 2006.285.15:53:15.71#ibcon#flushed, iclass 7, count 0 2006.285.15:53:15.71#ibcon#about to write, iclass 7, count 0 2006.285.15:53:15.71#ibcon#wrote, iclass 7, count 0 2006.285.15:53:15.71#ibcon#about to read 3, iclass 7, count 0 2006.285.15:53:15.73#ibcon#read 3, iclass 7, count 0 2006.285.15:53:15.73#ibcon#about to read 4, iclass 7, count 0 2006.285.15:53:15.73#ibcon#read 4, iclass 7, count 0 2006.285.15:53:15.73#ibcon#about to read 5, iclass 7, count 0 2006.285.15:53:15.73#ibcon#read 5, iclass 7, count 0 2006.285.15:53:15.73#ibcon#about to read 6, iclass 7, count 0 2006.285.15:53:15.73#ibcon#read 6, iclass 7, count 0 2006.285.15:53:15.73#ibcon#end of sib2, iclass 7, count 0 2006.285.15:53:15.73#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:53:15.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:53:15.73#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.15:53:15.73#ibcon#*before write, iclass 7, count 0 2006.285.15:53:15.73#ibcon#enter sib2, iclass 7, count 0 2006.285.15:53:15.73#ibcon#flushed, iclass 7, count 0 2006.285.15:53:15.73#ibcon#about to write, iclass 7, count 0 2006.285.15:53:15.73#ibcon#wrote, iclass 7, count 0 2006.285.15:53:15.73#ibcon#about to read 3, iclass 7, count 0 2006.285.15:53:15.77#ibcon#read 3, iclass 7, count 0 2006.285.15:53:15.77#ibcon#about to read 4, iclass 7, count 0 2006.285.15:53:15.77#ibcon#read 4, iclass 7, count 0 2006.285.15:53:15.77#ibcon#about to read 5, iclass 7, count 0 2006.285.15:53:15.77#ibcon#read 5, iclass 7, count 0 2006.285.15:53:15.77#ibcon#about to read 6, iclass 7, count 0 2006.285.15:53:15.77#ibcon#read 6, iclass 7, count 0 2006.285.15:53:15.77#ibcon#end of sib2, iclass 7, count 0 2006.285.15:53:15.77#ibcon#*after write, iclass 7, count 0 2006.285.15:53:15.77#ibcon#*before return 0, iclass 7, count 0 2006.285.15:53:15.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:53:15.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:53:15.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:53:15.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:53:15.77$vck44/va=5,3 2006.285.15:53:15.77#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.15:53:15.77#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.15:53:15.77#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:15.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:53:15.83#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:53:15.83#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:53:15.83#ibcon#enter wrdev, iclass 11, count 2 2006.285.15:53:15.83#ibcon#first serial, iclass 11, count 2 2006.285.15:53:15.83#ibcon#enter sib2, iclass 11, count 2 2006.285.15:53:15.83#ibcon#flushed, iclass 11, count 2 2006.285.15:53:15.83#ibcon#about to write, iclass 11, count 2 2006.285.15:53:15.83#ibcon#wrote, iclass 11, count 2 2006.285.15:53:15.83#ibcon#about to read 3, iclass 11, count 2 2006.285.15:53:15.85#ibcon#read 3, iclass 11, count 2 2006.285.15:53:15.85#ibcon#about to read 4, iclass 11, count 2 2006.285.15:53:15.85#ibcon#read 4, iclass 11, count 2 2006.285.15:53:15.85#ibcon#about to read 5, iclass 11, count 2 2006.285.15:53:15.85#ibcon#read 5, iclass 11, count 2 2006.285.15:53:15.85#ibcon#about to read 6, iclass 11, count 2 2006.285.15:53:15.85#ibcon#read 6, iclass 11, count 2 2006.285.15:53:15.85#ibcon#end of sib2, iclass 11, count 2 2006.285.15:53:15.85#ibcon#*mode == 0, iclass 11, count 2 2006.285.15:53:15.85#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.15:53:15.85#ibcon#[25=AT05-03\r\n] 2006.285.15:53:15.85#ibcon#*before write, iclass 11, count 2 2006.285.15:53:15.85#ibcon#enter sib2, iclass 11, count 2 2006.285.15:53:15.85#ibcon#flushed, iclass 11, count 2 2006.285.15:53:15.85#ibcon#about to write, iclass 11, count 2 2006.285.15:53:15.85#ibcon#wrote, iclass 11, count 2 2006.285.15:53:15.85#ibcon#about to read 3, iclass 11, count 2 2006.285.15:53:15.88#ibcon#read 3, iclass 11, count 2 2006.285.15:53:15.88#ibcon#about to read 4, iclass 11, count 2 2006.285.15:53:15.88#ibcon#read 4, iclass 11, count 2 2006.285.15:53:15.88#ibcon#about to read 5, iclass 11, count 2 2006.285.15:53:15.88#ibcon#read 5, iclass 11, count 2 2006.285.15:53:15.88#ibcon#about to read 6, iclass 11, count 2 2006.285.15:53:15.88#ibcon#read 6, iclass 11, count 2 2006.285.15:53:15.88#ibcon#end of sib2, iclass 11, count 2 2006.285.15:53:15.88#ibcon#*after write, iclass 11, count 2 2006.285.15:53:15.88#ibcon#*before return 0, iclass 11, count 2 2006.285.15:53:15.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:53:15.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:53:15.88#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.15:53:15.88#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:15.88#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:53:16.00#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:53:16.00#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:53:16.00#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:53:16.00#ibcon#first serial, iclass 11, count 0 2006.285.15:53:16.00#ibcon#enter sib2, iclass 11, count 0 2006.285.15:53:16.00#ibcon#flushed, iclass 11, count 0 2006.285.15:53:16.00#ibcon#about to write, iclass 11, count 0 2006.285.15:53:16.00#ibcon#wrote, iclass 11, count 0 2006.285.15:53:16.00#ibcon#about to read 3, iclass 11, count 0 2006.285.15:53:16.02#ibcon#read 3, iclass 11, count 0 2006.285.15:53:16.02#ibcon#about to read 4, iclass 11, count 0 2006.285.15:53:16.02#ibcon#read 4, iclass 11, count 0 2006.285.15:53:16.02#ibcon#about to read 5, iclass 11, count 0 2006.285.15:53:16.02#ibcon#read 5, iclass 11, count 0 2006.285.15:53:16.02#ibcon#about to read 6, iclass 11, count 0 2006.285.15:53:16.02#ibcon#read 6, iclass 11, count 0 2006.285.15:53:16.02#ibcon#end of sib2, iclass 11, count 0 2006.285.15:53:16.02#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:53:16.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:53:16.02#ibcon#[25=USB\r\n] 2006.285.15:53:16.02#ibcon#*before write, iclass 11, count 0 2006.285.15:53:16.02#ibcon#enter sib2, iclass 11, count 0 2006.285.15:53:16.02#ibcon#flushed, iclass 11, count 0 2006.285.15:53:16.02#ibcon#about to write, iclass 11, count 0 2006.285.15:53:16.02#ibcon#wrote, iclass 11, count 0 2006.285.15:53:16.02#ibcon#about to read 3, iclass 11, count 0 2006.285.15:53:16.05#ibcon#read 3, iclass 11, count 0 2006.285.15:53:16.05#ibcon#about to read 4, iclass 11, count 0 2006.285.15:53:16.05#ibcon#read 4, iclass 11, count 0 2006.285.15:53:16.05#ibcon#about to read 5, iclass 11, count 0 2006.285.15:53:16.05#ibcon#read 5, iclass 11, count 0 2006.285.15:53:16.05#ibcon#about to read 6, iclass 11, count 0 2006.285.15:53:16.05#ibcon#read 6, iclass 11, count 0 2006.285.15:53:16.05#ibcon#end of sib2, iclass 11, count 0 2006.285.15:53:16.05#ibcon#*after write, iclass 11, count 0 2006.285.15:53:16.05#ibcon#*before return 0, iclass 11, count 0 2006.285.15:53:16.05#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:53:16.05#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:53:16.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:53:16.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:53:16.05$vck44/valo=6,814.99 2006.285.15:53:16.05#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.15:53:16.05#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.15:53:16.05#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:16.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:53:16.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:53:16.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:53:16.05#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:53:16.05#ibcon#first serial, iclass 13, count 0 2006.285.15:53:16.05#ibcon#enter sib2, iclass 13, count 0 2006.285.15:53:16.05#ibcon#flushed, iclass 13, count 0 2006.285.15:53:16.05#ibcon#about to write, iclass 13, count 0 2006.285.15:53:16.05#ibcon#wrote, iclass 13, count 0 2006.285.15:53:16.05#ibcon#about to read 3, iclass 13, count 0 2006.285.15:53:16.07#ibcon#read 3, iclass 13, count 0 2006.285.15:53:16.07#ibcon#about to read 4, iclass 13, count 0 2006.285.15:53:16.07#ibcon#read 4, iclass 13, count 0 2006.285.15:53:16.07#ibcon#about to read 5, iclass 13, count 0 2006.285.15:53:16.07#ibcon#read 5, iclass 13, count 0 2006.285.15:53:16.07#ibcon#about to read 6, iclass 13, count 0 2006.285.15:53:16.07#ibcon#read 6, iclass 13, count 0 2006.285.15:53:16.07#ibcon#end of sib2, iclass 13, count 0 2006.285.15:53:16.07#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:53:16.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:53:16.07#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.15:53:16.07#ibcon#*before write, iclass 13, count 0 2006.285.15:53:16.07#ibcon#enter sib2, iclass 13, count 0 2006.285.15:53:16.07#ibcon#flushed, iclass 13, count 0 2006.285.15:53:16.07#ibcon#about to write, iclass 13, count 0 2006.285.15:53:16.07#ibcon#wrote, iclass 13, count 0 2006.285.15:53:16.07#ibcon#about to read 3, iclass 13, count 0 2006.285.15:53:16.11#ibcon#read 3, iclass 13, count 0 2006.285.15:53:16.11#ibcon#about to read 4, iclass 13, count 0 2006.285.15:53:16.11#ibcon#read 4, iclass 13, count 0 2006.285.15:53:16.11#ibcon#about to read 5, iclass 13, count 0 2006.285.15:53:16.11#ibcon#read 5, iclass 13, count 0 2006.285.15:53:16.11#ibcon#about to read 6, iclass 13, count 0 2006.285.15:53:16.11#ibcon#read 6, iclass 13, count 0 2006.285.15:53:16.11#ibcon#end of sib2, iclass 13, count 0 2006.285.15:53:16.11#ibcon#*after write, iclass 13, count 0 2006.285.15:53:16.11#ibcon#*before return 0, iclass 13, count 0 2006.285.15:53:16.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:53:16.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:53:16.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:53:16.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:53:16.11$vck44/va=6,4 2006.285.15:53:16.11#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.15:53:16.11#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.15:53:16.11#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:16.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:53:16.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:53:16.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:53:16.17#ibcon#enter wrdev, iclass 15, count 2 2006.285.15:53:16.17#ibcon#first serial, iclass 15, count 2 2006.285.15:53:16.17#ibcon#enter sib2, iclass 15, count 2 2006.285.15:53:16.17#ibcon#flushed, iclass 15, count 2 2006.285.15:53:16.17#ibcon#about to write, iclass 15, count 2 2006.285.15:53:16.17#ibcon#wrote, iclass 15, count 2 2006.285.15:53:16.17#ibcon#about to read 3, iclass 15, count 2 2006.285.15:53:16.19#ibcon#read 3, iclass 15, count 2 2006.285.15:53:16.19#ibcon#about to read 4, iclass 15, count 2 2006.285.15:53:16.19#ibcon#read 4, iclass 15, count 2 2006.285.15:53:16.19#ibcon#about to read 5, iclass 15, count 2 2006.285.15:53:16.19#ibcon#read 5, iclass 15, count 2 2006.285.15:53:16.19#ibcon#about to read 6, iclass 15, count 2 2006.285.15:53:16.19#ibcon#read 6, iclass 15, count 2 2006.285.15:53:16.19#ibcon#end of sib2, iclass 15, count 2 2006.285.15:53:16.19#ibcon#*mode == 0, iclass 15, count 2 2006.285.15:53:16.19#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.15:53:16.19#ibcon#[25=AT06-04\r\n] 2006.285.15:53:16.19#ibcon#*before write, iclass 15, count 2 2006.285.15:53:16.19#ibcon#enter sib2, iclass 15, count 2 2006.285.15:53:16.19#ibcon#flushed, iclass 15, count 2 2006.285.15:53:16.19#ibcon#about to write, iclass 15, count 2 2006.285.15:53:16.19#ibcon#wrote, iclass 15, count 2 2006.285.15:53:16.19#ibcon#about to read 3, iclass 15, count 2 2006.285.15:53:16.22#ibcon#read 3, iclass 15, count 2 2006.285.15:53:16.22#ibcon#about to read 4, iclass 15, count 2 2006.285.15:53:16.22#ibcon#read 4, iclass 15, count 2 2006.285.15:53:16.22#ibcon#about to read 5, iclass 15, count 2 2006.285.15:53:16.22#ibcon#read 5, iclass 15, count 2 2006.285.15:53:16.22#ibcon#about to read 6, iclass 15, count 2 2006.285.15:53:16.22#ibcon#read 6, iclass 15, count 2 2006.285.15:53:16.22#ibcon#end of sib2, iclass 15, count 2 2006.285.15:53:16.22#ibcon#*after write, iclass 15, count 2 2006.285.15:53:16.22#ibcon#*before return 0, iclass 15, count 2 2006.285.15:53:16.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:53:16.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:53:16.22#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.15:53:16.22#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:16.22#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:53:16.34#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:53:16.38#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:53:16.38#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:53:16.38#ibcon#first serial, iclass 15, count 0 2006.285.15:53:16.38#ibcon#enter sib2, iclass 15, count 0 2006.285.15:53:16.38#ibcon#flushed, iclass 15, count 0 2006.285.15:53:16.38#ibcon#about to write, iclass 15, count 0 2006.285.15:53:16.38#ibcon#wrote, iclass 15, count 0 2006.285.15:53:16.38#ibcon#about to read 3, iclass 15, count 0 2006.285.15:53:16.40#ibcon#read 3, iclass 15, count 0 2006.285.15:53:16.40#ibcon#about to read 4, iclass 15, count 0 2006.285.15:53:16.40#ibcon#read 4, iclass 15, count 0 2006.285.15:53:16.40#ibcon#about to read 5, iclass 15, count 0 2006.285.15:53:16.40#ibcon#read 5, iclass 15, count 0 2006.285.15:53:16.40#ibcon#about to read 6, iclass 15, count 0 2006.285.15:53:16.40#ibcon#read 6, iclass 15, count 0 2006.285.15:53:16.40#ibcon#end of sib2, iclass 15, count 0 2006.285.15:53:16.40#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:53:16.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:53:16.40#ibcon#[25=USB\r\n] 2006.285.15:53:16.40#ibcon#*before write, iclass 15, count 0 2006.285.15:53:16.40#ibcon#enter sib2, iclass 15, count 0 2006.285.15:53:16.40#ibcon#flushed, iclass 15, count 0 2006.285.15:53:16.40#ibcon#about to write, iclass 15, count 0 2006.285.15:53:16.40#ibcon#wrote, iclass 15, count 0 2006.285.15:53:16.40#ibcon#about to read 3, iclass 15, count 0 2006.285.15:53:16.43#ibcon#read 3, iclass 15, count 0 2006.285.15:53:16.43#ibcon#about to read 4, iclass 15, count 0 2006.285.15:53:16.43#ibcon#read 4, iclass 15, count 0 2006.285.15:53:16.43#ibcon#about to read 5, iclass 15, count 0 2006.285.15:53:16.43#ibcon#read 5, iclass 15, count 0 2006.285.15:53:16.43#ibcon#about to read 6, iclass 15, count 0 2006.285.15:53:16.43#ibcon#read 6, iclass 15, count 0 2006.285.15:53:16.43#ibcon#end of sib2, iclass 15, count 0 2006.285.15:53:16.43#ibcon#*after write, iclass 15, count 0 2006.285.15:53:16.43#ibcon#*before return 0, iclass 15, count 0 2006.285.15:53:16.43#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:53:16.43#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:53:16.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:53:16.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:53:16.43$vck44/valo=7,864.99 2006.285.15:53:16.43#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.15:53:16.43#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.15:53:16.43#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:16.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:53:16.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:53:16.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:53:16.43#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:53:16.43#ibcon#first serial, iclass 17, count 0 2006.285.15:53:16.43#ibcon#enter sib2, iclass 17, count 0 2006.285.15:53:16.43#ibcon#flushed, iclass 17, count 0 2006.285.15:53:16.43#ibcon#about to write, iclass 17, count 0 2006.285.15:53:16.43#ibcon#wrote, iclass 17, count 0 2006.285.15:53:16.43#ibcon#about to read 3, iclass 17, count 0 2006.285.15:53:16.45#ibcon#read 3, iclass 17, count 0 2006.285.15:53:16.45#ibcon#about to read 4, iclass 17, count 0 2006.285.15:53:16.45#ibcon#read 4, iclass 17, count 0 2006.285.15:53:16.45#ibcon#about to read 5, iclass 17, count 0 2006.285.15:53:16.45#ibcon#read 5, iclass 17, count 0 2006.285.15:53:16.45#ibcon#about to read 6, iclass 17, count 0 2006.285.15:53:16.45#ibcon#read 6, iclass 17, count 0 2006.285.15:53:16.45#ibcon#end of sib2, iclass 17, count 0 2006.285.15:53:16.45#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:53:16.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:53:16.45#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.15:53:16.45#ibcon#*before write, iclass 17, count 0 2006.285.15:53:16.45#ibcon#enter sib2, iclass 17, count 0 2006.285.15:53:16.45#ibcon#flushed, iclass 17, count 0 2006.285.15:53:16.45#ibcon#about to write, iclass 17, count 0 2006.285.15:53:16.45#ibcon#wrote, iclass 17, count 0 2006.285.15:53:16.45#ibcon#about to read 3, iclass 17, count 0 2006.285.15:53:16.49#ibcon#read 3, iclass 17, count 0 2006.285.15:53:16.49#ibcon#about to read 4, iclass 17, count 0 2006.285.15:53:16.49#ibcon#read 4, iclass 17, count 0 2006.285.15:53:16.49#ibcon#about to read 5, iclass 17, count 0 2006.285.15:53:16.49#ibcon#read 5, iclass 17, count 0 2006.285.15:53:16.49#ibcon#about to read 6, iclass 17, count 0 2006.285.15:53:16.49#ibcon#read 6, iclass 17, count 0 2006.285.15:53:16.49#ibcon#end of sib2, iclass 17, count 0 2006.285.15:53:16.49#ibcon#*after write, iclass 17, count 0 2006.285.15:53:16.49#ibcon#*before return 0, iclass 17, count 0 2006.285.15:53:16.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:53:16.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:53:16.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:53:16.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:53:16.49$vck44/va=7,4 2006.285.15:53:16.49#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.15:53:16.49#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.15:53:16.49#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:16.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:53:16.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:53:16.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:53:16.55#ibcon#enter wrdev, iclass 19, count 2 2006.285.15:53:16.55#ibcon#first serial, iclass 19, count 2 2006.285.15:53:16.55#ibcon#enter sib2, iclass 19, count 2 2006.285.15:53:16.55#ibcon#flushed, iclass 19, count 2 2006.285.15:53:16.55#ibcon#about to write, iclass 19, count 2 2006.285.15:53:16.55#ibcon#wrote, iclass 19, count 2 2006.285.15:53:16.55#ibcon#about to read 3, iclass 19, count 2 2006.285.15:53:16.57#ibcon#read 3, iclass 19, count 2 2006.285.15:53:16.57#ibcon#about to read 4, iclass 19, count 2 2006.285.15:53:16.57#ibcon#read 4, iclass 19, count 2 2006.285.15:53:16.57#ibcon#about to read 5, iclass 19, count 2 2006.285.15:53:16.57#ibcon#read 5, iclass 19, count 2 2006.285.15:53:16.57#ibcon#about to read 6, iclass 19, count 2 2006.285.15:53:16.57#ibcon#read 6, iclass 19, count 2 2006.285.15:53:16.57#ibcon#end of sib2, iclass 19, count 2 2006.285.15:53:16.57#ibcon#*mode == 0, iclass 19, count 2 2006.285.15:53:16.57#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.15:53:16.57#ibcon#[25=AT07-04\r\n] 2006.285.15:53:16.57#ibcon#*before write, iclass 19, count 2 2006.285.15:53:16.57#ibcon#enter sib2, iclass 19, count 2 2006.285.15:53:16.57#ibcon#flushed, iclass 19, count 2 2006.285.15:53:16.57#ibcon#about to write, iclass 19, count 2 2006.285.15:53:16.57#ibcon#wrote, iclass 19, count 2 2006.285.15:53:16.57#ibcon#about to read 3, iclass 19, count 2 2006.285.15:53:16.60#ibcon#read 3, iclass 19, count 2 2006.285.15:53:16.60#ibcon#about to read 4, iclass 19, count 2 2006.285.15:53:16.60#ibcon#read 4, iclass 19, count 2 2006.285.15:53:16.60#ibcon#about to read 5, iclass 19, count 2 2006.285.15:53:16.60#ibcon#read 5, iclass 19, count 2 2006.285.15:53:16.60#ibcon#about to read 6, iclass 19, count 2 2006.285.15:53:16.60#ibcon#read 6, iclass 19, count 2 2006.285.15:53:16.60#ibcon#end of sib2, iclass 19, count 2 2006.285.15:53:16.60#ibcon#*after write, iclass 19, count 2 2006.285.15:53:16.60#ibcon#*before return 0, iclass 19, count 2 2006.285.15:53:16.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:53:16.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:53:16.60#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.15:53:16.60#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:16.60#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:53:16.72#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:53:16.72#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:53:16.72#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:53:16.72#ibcon#first serial, iclass 19, count 0 2006.285.15:53:16.72#ibcon#enter sib2, iclass 19, count 0 2006.285.15:53:16.72#ibcon#flushed, iclass 19, count 0 2006.285.15:53:16.72#ibcon#about to write, iclass 19, count 0 2006.285.15:53:16.72#ibcon#wrote, iclass 19, count 0 2006.285.15:53:16.72#ibcon#about to read 3, iclass 19, count 0 2006.285.15:53:16.74#ibcon#read 3, iclass 19, count 0 2006.285.15:53:16.74#ibcon#about to read 4, iclass 19, count 0 2006.285.15:53:16.74#ibcon#read 4, iclass 19, count 0 2006.285.15:53:16.74#ibcon#about to read 5, iclass 19, count 0 2006.285.15:53:16.74#ibcon#read 5, iclass 19, count 0 2006.285.15:53:16.74#ibcon#about to read 6, iclass 19, count 0 2006.285.15:53:16.74#ibcon#read 6, iclass 19, count 0 2006.285.15:53:16.74#ibcon#end of sib2, iclass 19, count 0 2006.285.15:53:16.74#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:53:16.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:53:16.74#ibcon#[25=USB\r\n] 2006.285.15:53:16.74#ibcon#*before write, iclass 19, count 0 2006.285.15:53:16.74#ibcon#enter sib2, iclass 19, count 0 2006.285.15:53:16.74#ibcon#flushed, iclass 19, count 0 2006.285.15:53:16.74#ibcon#about to write, iclass 19, count 0 2006.285.15:53:16.74#ibcon#wrote, iclass 19, count 0 2006.285.15:53:16.74#ibcon#about to read 3, iclass 19, count 0 2006.285.15:53:16.77#ibcon#read 3, iclass 19, count 0 2006.285.15:53:16.77#ibcon#about to read 4, iclass 19, count 0 2006.285.15:53:16.77#ibcon#read 4, iclass 19, count 0 2006.285.15:53:16.77#ibcon#about to read 5, iclass 19, count 0 2006.285.15:53:16.77#ibcon#read 5, iclass 19, count 0 2006.285.15:53:16.77#ibcon#about to read 6, iclass 19, count 0 2006.285.15:53:16.77#ibcon#read 6, iclass 19, count 0 2006.285.15:53:16.77#ibcon#end of sib2, iclass 19, count 0 2006.285.15:53:16.77#ibcon#*after write, iclass 19, count 0 2006.285.15:53:16.77#ibcon#*before return 0, iclass 19, count 0 2006.285.15:53:16.77#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:53:16.77#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:53:16.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:53:16.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:53:16.77$vck44/valo=8,884.99 2006.285.15:53:16.77#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.15:53:16.77#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.15:53:16.77#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:16.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:53:16.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:53:16.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:53:16.77#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:53:16.77#ibcon#first serial, iclass 21, count 0 2006.285.15:53:16.77#ibcon#enter sib2, iclass 21, count 0 2006.285.15:53:16.77#ibcon#flushed, iclass 21, count 0 2006.285.15:53:16.77#ibcon#about to write, iclass 21, count 0 2006.285.15:53:16.77#ibcon#wrote, iclass 21, count 0 2006.285.15:53:16.77#ibcon#about to read 3, iclass 21, count 0 2006.285.15:53:16.79#ibcon#read 3, iclass 21, count 0 2006.285.15:53:16.79#ibcon#about to read 4, iclass 21, count 0 2006.285.15:53:16.79#ibcon#read 4, iclass 21, count 0 2006.285.15:53:16.79#ibcon#about to read 5, iclass 21, count 0 2006.285.15:53:16.79#ibcon#read 5, iclass 21, count 0 2006.285.15:53:16.79#ibcon#about to read 6, iclass 21, count 0 2006.285.15:53:16.79#ibcon#read 6, iclass 21, count 0 2006.285.15:53:16.79#ibcon#end of sib2, iclass 21, count 0 2006.285.15:53:16.79#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:53:16.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:53:16.79#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.15:53:16.79#ibcon#*before write, iclass 21, count 0 2006.285.15:53:16.79#ibcon#enter sib2, iclass 21, count 0 2006.285.15:53:16.79#ibcon#flushed, iclass 21, count 0 2006.285.15:53:16.79#ibcon#about to write, iclass 21, count 0 2006.285.15:53:16.79#ibcon#wrote, iclass 21, count 0 2006.285.15:53:16.79#ibcon#about to read 3, iclass 21, count 0 2006.285.15:53:16.83#ibcon#read 3, iclass 21, count 0 2006.285.15:53:16.83#ibcon#about to read 4, iclass 21, count 0 2006.285.15:53:16.83#ibcon#read 4, iclass 21, count 0 2006.285.15:53:16.83#ibcon#about to read 5, iclass 21, count 0 2006.285.15:53:16.83#ibcon#read 5, iclass 21, count 0 2006.285.15:53:16.83#ibcon#about to read 6, iclass 21, count 0 2006.285.15:53:16.83#ibcon#read 6, iclass 21, count 0 2006.285.15:53:16.83#ibcon#end of sib2, iclass 21, count 0 2006.285.15:53:16.83#ibcon#*after write, iclass 21, count 0 2006.285.15:53:16.83#ibcon#*before return 0, iclass 21, count 0 2006.285.15:53:16.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:53:16.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:53:16.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:53:16.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:53:16.83$vck44/va=8,3 2006.285.15:53:16.83#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.15:53:16.83#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.15:53:16.83#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:16.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:53:16.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:53:16.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:53:16.89#ibcon#enter wrdev, iclass 23, count 2 2006.285.15:53:16.89#ibcon#first serial, iclass 23, count 2 2006.285.15:53:16.89#ibcon#enter sib2, iclass 23, count 2 2006.285.15:53:16.89#ibcon#flushed, iclass 23, count 2 2006.285.15:53:16.89#ibcon#about to write, iclass 23, count 2 2006.285.15:53:16.89#ibcon#wrote, iclass 23, count 2 2006.285.15:53:16.89#ibcon#about to read 3, iclass 23, count 2 2006.285.15:53:16.91#ibcon#read 3, iclass 23, count 2 2006.285.15:53:16.91#ibcon#about to read 4, iclass 23, count 2 2006.285.15:53:16.91#ibcon#read 4, iclass 23, count 2 2006.285.15:53:16.91#ibcon#about to read 5, iclass 23, count 2 2006.285.15:53:16.91#ibcon#read 5, iclass 23, count 2 2006.285.15:53:16.91#ibcon#about to read 6, iclass 23, count 2 2006.285.15:53:16.91#ibcon#read 6, iclass 23, count 2 2006.285.15:53:16.91#ibcon#end of sib2, iclass 23, count 2 2006.285.15:53:16.91#ibcon#*mode == 0, iclass 23, count 2 2006.285.15:53:16.91#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.15:53:16.91#ibcon#[25=AT08-03\r\n] 2006.285.15:53:16.91#ibcon#*before write, iclass 23, count 2 2006.285.15:53:16.91#ibcon#enter sib2, iclass 23, count 2 2006.285.15:53:16.91#ibcon#flushed, iclass 23, count 2 2006.285.15:53:16.91#ibcon#about to write, iclass 23, count 2 2006.285.15:53:16.91#ibcon#wrote, iclass 23, count 2 2006.285.15:53:16.91#ibcon#about to read 3, iclass 23, count 2 2006.285.15:53:16.94#ibcon#read 3, iclass 23, count 2 2006.285.15:53:16.94#ibcon#about to read 4, iclass 23, count 2 2006.285.15:53:16.94#ibcon#read 4, iclass 23, count 2 2006.285.15:53:16.94#ibcon#about to read 5, iclass 23, count 2 2006.285.15:53:16.94#ibcon#read 5, iclass 23, count 2 2006.285.15:53:16.94#ibcon#about to read 6, iclass 23, count 2 2006.285.15:53:16.94#ibcon#read 6, iclass 23, count 2 2006.285.15:53:16.94#ibcon#end of sib2, iclass 23, count 2 2006.285.15:53:16.94#ibcon#*after write, iclass 23, count 2 2006.285.15:53:16.94#ibcon#*before return 0, iclass 23, count 2 2006.285.15:53:16.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:53:16.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.15:53:16.94#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.15:53:16.94#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:16.94#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:53:17.06#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:53:17.06#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:53:17.06#ibcon#enter wrdev, iclass 23, count 0 2006.285.15:53:17.06#ibcon#first serial, iclass 23, count 0 2006.285.15:53:17.06#ibcon#enter sib2, iclass 23, count 0 2006.285.15:53:17.06#ibcon#flushed, iclass 23, count 0 2006.285.15:53:17.06#ibcon#about to write, iclass 23, count 0 2006.285.15:53:17.06#ibcon#wrote, iclass 23, count 0 2006.285.15:53:17.06#ibcon#about to read 3, iclass 23, count 0 2006.285.15:53:17.08#ibcon#read 3, iclass 23, count 0 2006.285.15:53:17.08#ibcon#about to read 4, iclass 23, count 0 2006.285.15:53:17.08#ibcon#read 4, iclass 23, count 0 2006.285.15:53:17.08#ibcon#about to read 5, iclass 23, count 0 2006.285.15:53:17.08#ibcon#read 5, iclass 23, count 0 2006.285.15:53:17.08#ibcon#about to read 6, iclass 23, count 0 2006.285.15:53:17.08#ibcon#read 6, iclass 23, count 0 2006.285.15:53:17.08#ibcon#end of sib2, iclass 23, count 0 2006.285.15:53:17.08#ibcon#*mode == 0, iclass 23, count 0 2006.285.15:53:17.08#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.15:53:17.08#ibcon#[25=USB\r\n] 2006.285.15:53:17.08#ibcon#*before write, iclass 23, count 0 2006.285.15:53:17.08#ibcon#enter sib2, iclass 23, count 0 2006.285.15:53:17.08#ibcon#flushed, iclass 23, count 0 2006.285.15:53:17.08#ibcon#about to write, iclass 23, count 0 2006.285.15:53:17.08#ibcon#wrote, iclass 23, count 0 2006.285.15:53:17.08#ibcon#about to read 3, iclass 23, count 0 2006.285.15:53:17.11#ibcon#read 3, iclass 23, count 0 2006.285.15:53:17.11#ibcon#about to read 4, iclass 23, count 0 2006.285.15:53:17.11#ibcon#read 4, iclass 23, count 0 2006.285.15:53:17.11#ibcon#about to read 5, iclass 23, count 0 2006.285.15:53:17.11#ibcon#read 5, iclass 23, count 0 2006.285.15:53:17.11#ibcon#about to read 6, iclass 23, count 0 2006.285.15:53:17.11#ibcon#read 6, iclass 23, count 0 2006.285.15:53:17.11#ibcon#end of sib2, iclass 23, count 0 2006.285.15:53:17.11#ibcon#*after write, iclass 23, count 0 2006.285.15:53:17.11#ibcon#*before return 0, iclass 23, count 0 2006.285.15:53:17.11#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:53:17.11#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.15:53:17.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.15:53:17.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.15:53:17.11$vck44/vblo=1,629.99 2006.285.15:53:17.11#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.15:53:17.11#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.15:53:17.11#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:17.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:53:17.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:53:17.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:53:17.11#ibcon#enter wrdev, iclass 25, count 0 2006.285.15:53:17.11#ibcon#first serial, iclass 25, count 0 2006.285.15:53:17.11#ibcon#enter sib2, iclass 25, count 0 2006.285.15:53:17.11#ibcon#flushed, iclass 25, count 0 2006.285.15:53:17.11#ibcon#about to write, iclass 25, count 0 2006.285.15:53:17.11#ibcon#wrote, iclass 25, count 0 2006.285.15:53:17.11#ibcon#about to read 3, iclass 25, count 0 2006.285.15:53:17.13#ibcon#read 3, iclass 25, count 0 2006.285.15:53:17.13#ibcon#about to read 4, iclass 25, count 0 2006.285.15:53:17.13#ibcon#read 4, iclass 25, count 0 2006.285.15:53:17.13#ibcon#about to read 5, iclass 25, count 0 2006.285.15:53:17.13#ibcon#read 5, iclass 25, count 0 2006.285.15:53:17.13#ibcon#about to read 6, iclass 25, count 0 2006.285.15:53:17.13#ibcon#read 6, iclass 25, count 0 2006.285.15:53:17.13#ibcon#end of sib2, iclass 25, count 0 2006.285.15:53:17.13#ibcon#*mode == 0, iclass 25, count 0 2006.285.15:53:17.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.15:53:17.13#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.15:53:17.13#ibcon#*before write, iclass 25, count 0 2006.285.15:53:17.13#ibcon#enter sib2, iclass 25, count 0 2006.285.15:53:17.13#ibcon#flushed, iclass 25, count 0 2006.285.15:53:17.13#ibcon#about to write, iclass 25, count 0 2006.285.15:53:17.13#ibcon#wrote, iclass 25, count 0 2006.285.15:53:17.13#ibcon#about to read 3, iclass 25, count 0 2006.285.15:53:17.17#ibcon#read 3, iclass 25, count 0 2006.285.15:53:17.17#ibcon#about to read 4, iclass 25, count 0 2006.285.15:53:17.17#ibcon#read 4, iclass 25, count 0 2006.285.15:53:17.17#ibcon#about to read 5, iclass 25, count 0 2006.285.15:53:17.17#ibcon#read 5, iclass 25, count 0 2006.285.15:53:17.17#ibcon#about to read 6, iclass 25, count 0 2006.285.15:53:17.17#ibcon#read 6, iclass 25, count 0 2006.285.15:53:17.17#ibcon#end of sib2, iclass 25, count 0 2006.285.15:53:17.17#ibcon#*after write, iclass 25, count 0 2006.285.15:53:17.17#ibcon#*before return 0, iclass 25, count 0 2006.285.15:53:17.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:53:17.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.15:53:17.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.15:53:17.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.15:53:17.17$vck44/vb=1,4 2006.285.15:53:17.17#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.15:53:17.17#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.15:53:17.17#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:17.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:53:17.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:53:17.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:53:17.17#ibcon#enter wrdev, iclass 27, count 2 2006.285.15:53:17.17#ibcon#first serial, iclass 27, count 2 2006.285.15:53:17.17#ibcon#enter sib2, iclass 27, count 2 2006.285.15:53:17.17#ibcon#flushed, iclass 27, count 2 2006.285.15:53:17.17#ibcon#about to write, iclass 27, count 2 2006.285.15:53:17.17#ibcon#wrote, iclass 27, count 2 2006.285.15:53:17.17#ibcon#about to read 3, iclass 27, count 2 2006.285.15:53:17.19#ibcon#read 3, iclass 27, count 2 2006.285.15:53:17.19#ibcon#about to read 4, iclass 27, count 2 2006.285.15:53:17.19#ibcon#read 4, iclass 27, count 2 2006.285.15:53:17.19#ibcon#about to read 5, iclass 27, count 2 2006.285.15:53:17.19#ibcon#read 5, iclass 27, count 2 2006.285.15:53:17.19#ibcon#about to read 6, iclass 27, count 2 2006.285.15:53:17.19#ibcon#read 6, iclass 27, count 2 2006.285.15:53:17.19#ibcon#end of sib2, iclass 27, count 2 2006.285.15:53:17.19#ibcon#*mode == 0, iclass 27, count 2 2006.285.15:53:17.19#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.15:53:17.19#ibcon#[27=AT01-04\r\n] 2006.285.15:53:17.19#ibcon#*before write, iclass 27, count 2 2006.285.15:53:17.19#ibcon#enter sib2, iclass 27, count 2 2006.285.15:53:17.19#ibcon#flushed, iclass 27, count 2 2006.285.15:53:17.19#ibcon#about to write, iclass 27, count 2 2006.285.15:53:17.19#ibcon#wrote, iclass 27, count 2 2006.285.15:53:17.19#ibcon#about to read 3, iclass 27, count 2 2006.285.15:53:17.22#ibcon#read 3, iclass 27, count 2 2006.285.15:53:17.22#ibcon#about to read 4, iclass 27, count 2 2006.285.15:53:17.22#ibcon#read 4, iclass 27, count 2 2006.285.15:53:17.22#ibcon#about to read 5, iclass 27, count 2 2006.285.15:53:17.22#ibcon#read 5, iclass 27, count 2 2006.285.15:53:17.22#ibcon#about to read 6, iclass 27, count 2 2006.285.15:53:17.22#ibcon#read 6, iclass 27, count 2 2006.285.15:53:17.22#ibcon#end of sib2, iclass 27, count 2 2006.285.15:53:17.22#ibcon#*after write, iclass 27, count 2 2006.285.15:53:17.22#ibcon#*before return 0, iclass 27, count 2 2006.285.15:53:17.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:53:17.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.15:53:17.22#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.15:53:17.22#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:17.22#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:53:17.34#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:53:17.39#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:53:17.39#ibcon#enter wrdev, iclass 27, count 0 2006.285.15:53:17.39#ibcon#first serial, iclass 27, count 0 2006.285.15:53:17.39#ibcon#enter sib2, iclass 27, count 0 2006.285.15:53:17.39#ibcon#flushed, iclass 27, count 0 2006.285.15:53:17.39#ibcon#about to write, iclass 27, count 0 2006.285.15:53:17.39#ibcon#wrote, iclass 27, count 0 2006.285.15:53:17.39#ibcon#about to read 3, iclass 27, count 0 2006.285.15:53:17.41#ibcon#read 3, iclass 27, count 0 2006.285.15:53:17.41#ibcon#about to read 4, iclass 27, count 0 2006.285.15:53:17.41#ibcon#read 4, iclass 27, count 0 2006.285.15:53:17.41#ibcon#about to read 5, iclass 27, count 0 2006.285.15:53:17.41#ibcon#read 5, iclass 27, count 0 2006.285.15:53:17.41#ibcon#about to read 6, iclass 27, count 0 2006.285.15:53:17.41#ibcon#read 6, iclass 27, count 0 2006.285.15:53:17.41#ibcon#end of sib2, iclass 27, count 0 2006.285.15:53:17.41#ibcon#*mode == 0, iclass 27, count 0 2006.285.15:53:17.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.15:53:17.41#ibcon#[27=USB\r\n] 2006.285.15:53:17.41#ibcon#*before write, iclass 27, count 0 2006.285.15:53:17.41#ibcon#enter sib2, iclass 27, count 0 2006.285.15:53:17.41#ibcon#flushed, iclass 27, count 0 2006.285.15:53:17.41#ibcon#about to write, iclass 27, count 0 2006.285.15:53:17.41#ibcon#wrote, iclass 27, count 0 2006.285.15:53:17.41#ibcon#about to read 3, iclass 27, count 0 2006.285.15:53:17.44#ibcon#read 3, iclass 27, count 0 2006.285.15:53:17.44#ibcon#about to read 4, iclass 27, count 0 2006.285.15:53:17.44#ibcon#read 4, iclass 27, count 0 2006.285.15:53:17.44#ibcon#about to read 5, iclass 27, count 0 2006.285.15:53:17.44#ibcon#read 5, iclass 27, count 0 2006.285.15:53:17.44#ibcon#about to read 6, iclass 27, count 0 2006.285.15:53:17.44#ibcon#read 6, iclass 27, count 0 2006.285.15:53:17.44#ibcon#end of sib2, iclass 27, count 0 2006.285.15:53:17.44#ibcon#*after write, iclass 27, count 0 2006.285.15:53:17.44#ibcon#*before return 0, iclass 27, count 0 2006.285.15:53:17.44#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:53:17.44#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.15:53:17.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.15:53:17.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.15:53:17.44$vck44/vblo=2,634.99 2006.285.15:53:17.44#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.15:53:17.44#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.15:53:17.44#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:17.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:53:17.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:53:17.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:53:17.44#ibcon#enter wrdev, iclass 29, count 0 2006.285.15:53:17.44#ibcon#first serial, iclass 29, count 0 2006.285.15:53:17.44#ibcon#enter sib2, iclass 29, count 0 2006.285.15:53:17.44#ibcon#flushed, iclass 29, count 0 2006.285.15:53:17.44#ibcon#about to write, iclass 29, count 0 2006.285.15:53:17.44#ibcon#wrote, iclass 29, count 0 2006.285.15:53:17.44#ibcon#about to read 3, iclass 29, count 0 2006.285.15:53:17.46#ibcon#read 3, iclass 29, count 0 2006.285.15:53:17.46#ibcon#about to read 4, iclass 29, count 0 2006.285.15:53:17.46#ibcon#read 4, iclass 29, count 0 2006.285.15:53:17.46#ibcon#about to read 5, iclass 29, count 0 2006.285.15:53:17.46#ibcon#read 5, iclass 29, count 0 2006.285.15:53:17.46#ibcon#about to read 6, iclass 29, count 0 2006.285.15:53:17.46#ibcon#read 6, iclass 29, count 0 2006.285.15:53:17.46#ibcon#end of sib2, iclass 29, count 0 2006.285.15:53:17.46#ibcon#*mode == 0, iclass 29, count 0 2006.285.15:53:17.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.15:53:17.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.15:53:17.46#ibcon#*before write, iclass 29, count 0 2006.285.15:53:17.46#ibcon#enter sib2, iclass 29, count 0 2006.285.15:53:17.46#ibcon#flushed, iclass 29, count 0 2006.285.15:53:17.46#ibcon#about to write, iclass 29, count 0 2006.285.15:53:17.46#ibcon#wrote, iclass 29, count 0 2006.285.15:53:17.46#ibcon#about to read 3, iclass 29, count 0 2006.285.15:53:17.50#ibcon#read 3, iclass 29, count 0 2006.285.15:53:17.50#ibcon#about to read 4, iclass 29, count 0 2006.285.15:53:17.50#ibcon#read 4, iclass 29, count 0 2006.285.15:53:17.50#ibcon#about to read 5, iclass 29, count 0 2006.285.15:53:17.50#ibcon#read 5, iclass 29, count 0 2006.285.15:53:17.50#ibcon#about to read 6, iclass 29, count 0 2006.285.15:53:17.50#ibcon#read 6, iclass 29, count 0 2006.285.15:53:17.50#ibcon#end of sib2, iclass 29, count 0 2006.285.15:53:17.50#ibcon#*after write, iclass 29, count 0 2006.285.15:53:17.50#ibcon#*before return 0, iclass 29, count 0 2006.285.15:53:17.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:53:17.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.15:53:17.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.15:53:17.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.15:53:17.50$vck44/vb=2,5 2006.285.15:53:17.50#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.15:53:17.50#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.15:53:17.50#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:17.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:53:17.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:53:17.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:53:17.56#ibcon#enter wrdev, iclass 31, count 2 2006.285.15:53:17.56#ibcon#first serial, iclass 31, count 2 2006.285.15:53:17.56#ibcon#enter sib2, iclass 31, count 2 2006.285.15:53:17.56#ibcon#flushed, iclass 31, count 2 2006.285.15:53:17.56#ibcon#about to write, iclass 31, count 2 2006.285.15:53:17.56#ibcon#wrote, iclass 31, count 2 2006.285.15:53:17.56#ibcon#about to read 3, iclass 31, count 2 2006.285.15:53:17.58#ibcon#read 3, iclass 31, count 2 2006.285.15:53:17.58#ibcon#about to read 4, iclass 31, count 2 2006.285.15:53:17.58#ibcon#read 4, iclass 31, count 2 2006.285.15:53:17.58#ibcon#about to read 5, iclass 31, count 2 2006.285.15:53:17.58#ibcon#read 5, iclass 31, count 2 2006.285.15:53:17.58#ibcon#about to read 6, iclass 31, count 2 2006.285.15:53:17.58#ibcon#read 6, iclass 31, count 2 2006.285.15:53:17.58#ibcon#end of sib2, iclass 31, count 2 2006.285.15:53:17.58#ibcon#*mode == 0, iclass 31, count 2 2006.285.15:53:17.58#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.15:53:17.58#ibcon#[27=AT02-05\r\n] 2006.285.15:53:17.58#ibcon#*before write, iclass 31, count 2 2006.285.15:53:17.58#ibcon#enter sib2, iclass 31, count 2 2006.285.15:53:17.58#ibcon#flushed, iclass 31, count 2 2006.285.15:53:17.58#ibcon#about to write, iclass 31, count 2 2006.285.15:53:17.58#ibcon#wrote, iclass 31, count 2 2006.285.15:53:17.58#ibcon#about to read 3, iclass 31, count 2 2006.285.15:53:17.61#ibcon#read 3, iclass 31, count 2 2006.285.15:53:17.61#ibcon#about to read 4, iclass 31, count 2 2006.285.15:53:17.61#ibcon#read 4, iclass 31, count 2 2006.285.15:53:17.61#ibcon#about to read 5, iclass 31, count 2 2006.285.15:53:17.61#ibcon#read 5, iclass 31, count 2 2006.285.15:53:17.61#ibcon#about to read 6, iclass 31, count 2 2006.285.15:53:17.61#ibcon#read 6, iclass 31, count 2 2006.285.15:53:17.61#ibcon#end of sib2, iclass 31, count 2 2006.285.15:53:17.61#ibcon#*after write, iclass 31, count 2 2006.285.15:53:17.61#ibcon#*before return 0, iclass 31, count 2 2006.285.15:53:17.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:53:17.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.15:53:17.61#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.15:53:17.61#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:17.61#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:53:17.73#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:53:17.73#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:53:17.73#ibcon#enter wrdev, iclass 31, count 0 2006.285.15:53:17.73#ibcon#first serial, iclass 31, count 0 2006.285.15:53:17.73#ibcon#enter sib2, iclass 31, count 0 2006.285.15:53:17.73#ibcon#flushed, iclass 31, count 0 2006.285.15:53:17.73#ibcon#about to write, iclass 31, count 0 2006.285.15:53:17.73#ibcon#wrote, iclass 31, count 0 2006.285.15:53:17.73#ibcon#about to read 3, iclass 31, count 0 2006.285.15:53:17.75#ibcon#read 3, iclass 31, count 0 2006.285.15:53:17.75#ibcon#about to read 4, iclass 31, count 0 2006.285.15:53:17.75#ibcon#read 4, iclass 31, count 0 2006.285.15:53:17.75#ibcon#about to read 5, iclass 31, count 0 2006.285.15:53:17.75#ibcon#read 5, iclass 31, count 0 2006.285.15:53:17.75#ibcon#about to read 6, iclass 31, count 0 2006.285.15:53:17.75#ibcon#read 6, iclass 31, count 0 2006.285.15:53:17.75#ibcon#end of sib2, iclass 31, count 0 2006.285.15:53:17.75#ibcon#*mode == 0, iclass 31, count 0 2006.285.15:53:17.75#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.15:53:17.75#ibcon#[27=USB\r\n] 2006.285.15:53:17.75#ibcon#*before write, iclass 31, count 0 2006.285.15:53:17.75#ibcon#enter sib2, iclass 31, count 0 2006.285.15:53:17.75#ibcon#flushed, iclass 31, count 0 2006.285.15:53:17.75#ibcon#about to write, iclass 31, count 0 2006.285.15:53:17.75#ibcon#wrote, iclass 31, count 0 2006.285.15:53:17.75#ibcon#about to read 3, iclass 31, count 0 2006.285.15:53:17.78#ibcon#read 3, iclass 31, count 0 2006.285.15:53:17.78#ibcon#about to read 4, iclass 31, count 0 2006.285.15:53:17.78#ibcon#read 4, iclass 31, count 0 2006.285.15:53:17.78#ibcon#about to read 5, iclass 31, count 0 2006.285.15:53:17.78#ibcon#read 5, iclass 31, count 0 2006.285.15:53:17.78#ibcon#about to read 6, iclass 31, count 0 2006.285.15:53:17.78#ibcon#read 6, iclass 31, count 0 2006.285.15:53:17.78#ibcon#end of sib2, iclass 31, count 0 2006.285.15:53:17.78#ibcon#*after write, iclass 31, count 0 2006.285.15:53:17.78#ibcon#*before return 0, iclass 31, count 0 2006.285.15:53:17.78#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:53:17.78#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.15:53:17.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.15:53:17.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.15:53:17.78$vck44/vblo=3,649.99 2006.285.15:53:17.78#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.15:53:17.78#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.15:53:17.78#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:17.78#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:53:17.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:53:17.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:53:17.78#ibcon#enter wrdev, iclass 33, count 0 2006.285.15:53:17.78#ibcon#first serial, iclass 33, count 0 2006.285.15:53:17.78#ibcon#enter sib2, iclass 33, count 0 2006.285.15:53:17.78#ibcon#flushed, iclass 33, count 0 2006.285.15:53:17.78#ibcon#about to write, iclass 33, count 0 2006.285.15:53:17.78#ibcon#wrote, iclass 33, count 0 2006.285.15:53:17.78#ibcon#about to read 3, iclass 33, count 0 2006.285.15:53:17.80#ibcon#read 3, iclass 33, count 0 2006.285.15:53:17.80#ibcon#about to read 4, iclass 33, count 0 2006.285.15:53:17.80#ibcon#read 4, iclass 33, count 0 2006.285.15:53:17.80#ibcon#about to read 5, iclass 33, count 0 2006.285.15:53:17.80#ibcon#read 5, iclass 33, count 0 2006.285.15:53:17.80#ibcon#about to read 6, iclass 33, count 0 2006.285.15:53:17.80#ibcon#read 6, iclass 33, count 0 2006.285.15:53:17.80#ibcon#end of sib2, iclass 33, count 0 2006.285.15:53:17.80#ibcon#*mode == 0, iclass 33, count 0 2006.285.15:53:17.80#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.15:53:17.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.15:53:17.80#ibcon#*before write, iclass 33, count 0 2006.285.15:53:17.80#ibcon#enter sib2, iclass 33, count 0 2006.285.15:53:17.80#ibcon#flushed, iclass 33, count 0 2006.285.15:53:17.80#ibcon#about to write, iclass 33, count 0 2006.285.15:53:17.80#ibcon#wrote, iclass 33, count 0 2006.285.15:53:17.80#ibcon#about to read 3, iclass 33, count 0 2006.285.15:53:17.84#ibcon#read 3, iclass 33, count 0 2006.285.15:53:17.84#ibcon#about to read 4, iclass 33, count 0 2006.285.15:53:17.84#ibcon#read 4, iclass 33, count 0 2006.285.15:53:17.84#ibcon#about to read 5, iclass 33, count 0 2006.285.15:53:17.84#ibcon#read 5, iclass 33, count 0 2006.285.15:53:17.84#ibcon#about to read 6, iclass 33, count 0 2006.285.15:53:17.84#ibcon#read 6, iclass 33, count 0 2006.285.15:53:17.84#ibcon#end of sib2, iclass 33, count 0 2006.285.15:53:17.84#ibcon#*after write, iclass 33, count 0 2006.285.15:53:17.84#ibcon#*before return 0, iclass 33, count 0 2006.285.15:53:17.84#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:53:17.84#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.15:53:17.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.15:53:17.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.15:53:17.84$vck44/vb=3,4 2006.285.15:53:17.84#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.15:53:17.84#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.15:53:17.84#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:17.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:53:17.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:53:17.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:53:17.90#ibcon#enter wrdev, iclass 35, count 2 2006.285.15:53:17.90#ibcon#first serial, iclass 35, count 2 2006.285.15:53:17.90#ibcon#enter sib2, iclass 35, count 2 2006.285.15:53:17.90#ibcon#flushed, iclass 35, count 2 2006.285.15:53:17.90#ibcon#about to write, iclass 35, count 2 2006.285.15:53:17.90#ibcon#wrote, iclass 35, count 2 2006.285.15:53:17.90#ibcon#about to read 3, iclass 35, count 2 2006.285.15:53:17.92#ibcon#read 3, iclass 35, count 2 2006.285.15:53:17.92#ibcon#about to read 4, iclass 35, count 2 2006.285.15:53:17.92#ibcon#read 4, iclass 35, count 2 2006.285.15:53:17.92#ibcon#about to read 5, iclass 35, count 2 2006.285.15:53:17.92#ibcon#read 5, iclass 35, count 2 2006.285.15:53:17.92#ibcon#about to read 6, iclass 35, count 2 2006.285.15:53:17.92#ibcon#read 6, iclass 35, count 2 2006.285.15:53:17.92#ibcon#end of sib2, iclass 35, count 2 2006.285.15:53:17.92#ibcon#*mode == 0, iclass 35, count 2 2006.285.15:53:17.92#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.15:53:17.92#ibcon#[27=AT03-04\r\n] 2006.285.15:53:17.92#ibcon#*before write, iclass 35, count 2 2006.285.15:53:17.92#ibcon#enter sib2, iclass 35, count 2 2006.285.15:53:17.92#ibcon#flushed, iclass 35, count 2 2006.285.15:53:17.92#ibcon#about to write, iclass 35, count 2 2006.285.15:53:17.92#ibcon#wrote, iclass 35, count 2 2006.285.15:53:17.92#ibcon#about to read 3, iclass 35, count 2 2006.285.15:53:17.95#ibcon#read 3, iclass 35, count 2 2006.285.15:53:17.95#ibcon#about to read 4, iclass 35, count 2 2006.285.15:53:17.95#ibcon#read 4, iclass 35, count 2 2006.285.15:53:17.95#ibcon#about to read 5, iclass 35, count 2 2006.285.15:53:17.95#ibcon#read 5, iclass 35, count 2 2006.285.15:53:17.95#ibcon#about to read 6, iclass 35, count 2 2006.285.15:53:17.95#ibcon#read 6, iclass 35, count 2 2006.285.15:53:17.95#ibcon#end of sib2, iclass 35, count 2 2006.285.15:53:17.95#ibcon#*after write, iclass 35, count 2 2006.285.15:53:17.95#ibcon#*before return 0, iclass 35, count 2 2006.285.15:53:17.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:53:17.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.15:53:17.95#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.15:53:17.95#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:17.95#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:53:18.07#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:53:18.07#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:53:18.07#ibcon#enter wrdev, iclass 35, count 0 2006.285.15:53:18.07#ibcon#first serial, iclass 35, count 0 2006.285.15:53:18.07#ibcon#enter sib2, iclass 35, count 0 2006.285.15:53:18.07#ibcon#flushed, iclass 35, count 0 2006.285.15:53:18.07#ibcon#about to write, iclass 35, count 0 2006.285.15:53:18.07#ibcon#wrote, iclass 35, count 0 2006.285.15:53:18.07#ibcon#about to read 3, iclass 35, count 0 2006.285.15:53:18.09#ibcon#read 3, iclass 35, count 0 2006.285.15:53:18.09#ibcon#about to read 4, iclass 35, count 0 2006.285.15:53:18.09#ibcon#read 4, iclass 35, count 0 2006.285.15:53:18.09#ibcon#about to read 5, iclass 35, count 0 2006.285.15:53:18.09#ibcon#read 5, iclass 35, count 0 2006.285.15:53:18.09#ibcon#about to read 6, iclass 35, count 0 2006.285.15:53:18.09#ibcon#read 6, iclass 35, count 0 2006.285.15:53:18.09#ibcon#end of sib2, iclass 35, count 0 2006.285.15:53:18.09#ibcon#*mode == 0, iclass 35, count 0 2006.285.15:53:18.09#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.15:53:18.09#ibcon#[27=USB\r\n] 2006.285.15:53:18.09#ibcon#*before write, iclass 35, count 0 2006.285.15:53:18.09#ibcon#enter sib2, iclass 35, count 0 2006.285.15:53:18.09#ibcon#flushed, iclass 35, count 0 2006.285.15:53:18.09#ibcon#about to write, iclass 35, count 0 2006.285.15:53:18.09#ibcon#wrote, iclass 35, count 0 2006.285.15:53:18.09#ibcon#about to read 3, iclass 35, count 0 2006.285.15:53:18.12#ibcon#read 3, iclass 35, count 0 2006.285.15:53:18.12#ibcon#about to read 4, iclass 35, count 0 2006.285.15:53:18.12#ibcon#read 4, iclass 35, count 0 2006.285.15:53:18.12#ibcon#about to read 5, iclass 35, count 0 2006.285.15:53:18.12#ibcon#read 5, iclass 35, count 0 2006.285.15:53:18.12#ibcon#about to read 6, iclass 35, count 0 2006.285.15:53:18.12#ibcon#read 6, iclass 35, count 0 2006.285.15:53:18.12#ibcon#end of sib2, iclass 35, count 0 2006.285.15:53:18.12#ibcon#*after write, iclass 35, count 0 2006.285.15:53:18.12#ibcon#*before return 0, iclass 35, count 0 2006.285.15:53:18.12#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:53:18.12#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.15:53:18.12#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.15:53:18.12#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.15:53:18.12$vck44/vblo=4,679.99 2006.285.15:53:18.12#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.15:53:18.12#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.15:53:18.12#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:18.12#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:53:18.12#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:53:18.12#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:53:18.12#ibcon#enter wrdev, iclass 37, count 0 2006.285.15:53:18.12#ibcon#first serial, iclass 37, count 0 2006.285.15:53:18.12#ibcon#enter sib2, iclass 37, count 0 2006.285.15:53:18.12#ibcon#flushed, iclass 37, count 0 2006.285.15:53:18.12#ibcon#about to write, iclass 37, count 0 2006.285.15:53:18.12#ibcon#wrote, iclass 37, count 0 2006.285.15:53:18.12#ibcon#about to read 3, iclass 37, count 0 2006.285.15:53:18.14#ibcon#read 3, iclass 37, count 0 2006.285.15:53:18.14#ibcon#about to read 4, iclass 37, count 0 2006.285.15:53:18.14#ibcon#read 4, iclass 37, count 0 2006.285.15:53:18.14#ibcon#about to read 5, iclass 37, count 0 2006.285.15:53:18.14#ibcon#read 5, iclass 37, count 0 2006.285.15:53:18.14#ibcon#about to read 6, iclass 37, count 0 2006.285.15:53:18.14#ibcon#read 6, iclass 37, count 0 2006.285.15:53:18.14#ibcon#end of sib2, iclass 37, count 0 2006.285.15:53:18.14#ibcon#*mode == 0, iclass 37, count 0 2006.285.15:53:18.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.15:53:18.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.15:53:18.14#ibcon#*before write, iclass 37, count 0 2006.285.15:53:18.14#ibcon#enter sib2, iclass 37, count 0 2006.285.15:53:18.14#ibcon#flushed, iclass 37, count 0 2006.285.15:53:18.14#ibcon#about to write, iclass 37, count 0 2006.285.15:53:18.14#ibcon#wrote, iclass 37, count 0 2006.285.15:53:18.14#ibcon#about to read 3, iclass 37, count 0 2006.285.15:53:18.18#ibcon#read 3, iclass 37, count 0 2006.285.15:53:18.18#ibcon#about to read 4, iclass 37, count 0 2006.285.15:53:18.18#ibcon#read 4, iclass 37, count 0 2006.285.15:53:18.18#ibcon#about to read 5, iclass 37, count 0 2006.285.15:53:18.18#ibcon#read 5, iclass 37, count 0 2006.285.15:53:18.18#ibcon#about to read 6, iclass 37, count 0 2006.285.15:53:18.18#ibcon#read 6, iclass 37, count 0 2006.285.15:53:18.18#ibcon#end of sib2, iclass 37, count 0 2006.285.15:53:18.18#ibcon#*after write, iclass 37, count 0 2006.285.15:53:18.18#ibcon#*before return 0, iclass 37, count 0 2006.285.15:53:18.18#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:53:18.18#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.15:53:18.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.15:53:18.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.15:53:18.18$vck44/vb=4,5 2006.285.15:53:18.18#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.15:53:18.18#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.15:53:18.18#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:18.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:53:18.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:53:18.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:53:18.24#ibcon#enter wrdev, iclass 39, count 2 2006.285.15:53:18.24#ibcon#first serial, iclass 39, count 2 2006.285.15:53:18.24#ibcon#enter sib2, iclass 39, count 2 2006.285.15:53:18.24#ibcon#flushed, iclass 39, count 2 2006.285.15:53:18.24#ibcon#about to write, iclass 39, count 2 2006.285.15:53:18.24#ibcon#wrote, iclass 39, count 2 2006.285.15:53:18.24#ibcon#about to read 3, iclass 39, count 2 2006.285.15:53:18.26#ibcon#read 3, iclass 39, count 2 2006.285.15:53:18.26#ibcon#about to read 4, iclass 39, count 2 2006.285.15:53:18.26#ibcon#read 4, iclass 39, count 2 2006.285.15:53:18.26#ibcon#about to read 5, iclass 39, count 2 2006.285.15:53:18.26#ibcon#read 5, iclass 39, count 2 2006.285.15:53:18.26#ibcon#about to read 6, iclass 39, count 2 2006.285.15:53:18.26#ibcon#read 6, iclass 39, count 2 2006.285.15:53:18.26#ibcon#end of sib2, iclass 39, count 2 2006.285.15:53:18.26#ibcon#*mode == 0, iclass 39, count 2 2006.285.15:53:18.26#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.15:53:18.26#ibcon#[27=AT04-05\r\n] 2006.285.15:53:18.26#ibcon#*before write, iclass 39, count 2 2006.285.15:53:18.26#ibcon#enter sib2, iclass 39, count 2 2006.285.15:53:18.26#ibcon#flushed, iclass 39, count 2 2006.285.15:53:18.26#ibcon#about to write, iclass 39, count 2 2006.285.15:53:18.26#ibcon#wrote, iclass 39, count 2 2006.285.15:53:18.26#ibcon#about to read 3, iclass 39, count 2 2006.285.15:53:18.29#ibcon#read 3, iclass 39, count 2 2006.285.15:53:18.32#ibcon#about to read 4, iclass 39, count 2 2006.285.15:53:18.32#ibcon#read 4, iclass 39, count 2 2006.285.15:53:18.32#ibcon#about to read 5, iclass 39, count 2 2006.285.15:53:18.32#ibcon#read 5, iclass 39, count 2 2006.285.15:53:18.32#ibcon#about to read 6, iclass 39, count 2 2006.285.15:53:18.32#ibcon#read 6, iclass 39, count 2 2006.285.15:53:18.32#ibcon#end of sib2, iclass 39, count 2 2006.285.15:53:18.32#ibcon#*after write, iclass 39, count 2 2006.285.15:53:18.32#ibcon#*before return 0, iclass 39, count 2 2006.285.15:53:18.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:53:18.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.15:53:18.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.15:53:18.32#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:18.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:53:18.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:53:18.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:53:18.44#ibcon#enter wrdev, iclass 39, count 0 2006.285.15:53:18.44#ibcon#first serial, iclass 39, count 0 2006.285.15:53:18.44#ibcon#enter sib2, iclass 39, count 0 2006.285.15:53:18.44#ibcon#flushed, iclass 39, count 0 2006.285.15:53:18.44#ibcon#about to write, iclass 39, count 0 2006.285.15:53:18.44#ibcon#wrote, iclass 39, count 0 2006.285.15:53:18.44#ibcon#about to read 3, iclass 39, count 0 2006.285.15:53:18.46#ibcon#read 3, iclass 39, count 0 2006.285.15:53:18.46#ibcon#about to read 4, iclass 39, count 0 2006.285.15:53:18.46#ibcon#read 4, iclass 39, count 0 2006.285.15:53:18.46#ibcon#about to read 5, iclass 39, count 0 2006.285.15:53:18.46#ibcon#read 5, iclass 39, count 0 2006.285.15:53:18.46#ibcon#about to read 6, iclass 39, count 0 2006.285.15:53:18.46#ibcon#read 6, iclass 39, count 0 2006.285.15:53:18.46#ibcon#end of sib2, iclass 39, count 0 2006.285.15:53:18.46#ibcon#*mode == 0, iclass 39, count 0 2006.285.15:53:18.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.15:53:18.46#ibcon#[27=USB\r\n] 2006.285.15:53:18.46#ibcon#*before write, iclass 39, count 0 2006.285.15:53:18.46#ibcon#enter sib2, iclass 39, count 0 2006.285.15:53:18.46#ibcon#flushed, iclass 39, count 0 2006.285.15:53:18.46#ibcon#about to write, iclass 39, count 0 2006.285.15:53:18.46#ibcon#wrote, iclass 39, count 0 2006.285.15:53:18.46#ibcon#about to read 3, iclass 39, count 0 2006.285.15:53:18.49#ibcon#read 3, iclass 39, count 0 2006.285.15:53:18.49#ibcon#about to read 4, iclass 39, count 0 2006.285.15:53:18.49#ibcon#read 4, iclass 39, count 0 2006.285.15:53:18.49#ibcon#about to read 5, iclass 39, count 0 2006.285.15:53:18.49#ibcon#read 5, iclass 39, count 0 2006.285.15:53:18.49#ibcon#about to read 6, iclass 39, count 0 2006.285.15:53:18.49#ibcon#read 6, iclass 39, count 0 2006.285.15:53:18.49#ibcon#end of sib2, iclass 39, count 0 2006.285.15:53:18.49#ibcon#*after write, iclass 39, count 0 2006.285.15:53:18.49#ibcon#*before return 0, iclass 39, count 0 2006.285.15:53:18.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:53:18.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.15:53:18.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.15:53:18.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.15:53:18.49$vck44/vblo=5,709.99 2006.285.15:53:18.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.15:53:18.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.15:53:18.49#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:18.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:53:18.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:53:18.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:53:18.49#ibcon#enter wrdev, iclass 3, count 0 2006.285.15:53:18.49#ibcon#first serial, iclass 3, count 0 2006.285.15:53:18.49#ibcon#enter sib2, iclass 3, count 0 2006.285.15:53:18.49#ibcon#flushed, iclass 3, count 0 2006.285.15:53:18.49#ibcon#about to write, iclass 3, count 0 2006.285.15:53:18.49#ibcon#wrote, iclass 3, count 0 2006.285.15:53:18.49#ibcon#about to read 3, iclass 3, count 0 2006.285.15:53:18.51#ibcon#read 3, iclass 3, count 0 2006.285.15:53:18.51#ibcon#about to read 4, iclass 3, count 0 2006.285.15:53:18.51#ibcon#read 4, iclass 3, count 0 2006.285.15:53:18.51#ibcon#about to read 5, iclass 3, count 0 2006.285.15:53:18.51#ibcon#read 5, iclass 3, count 0 2006.285.15:53:18.51#ibcon#about to read 6, iclass 3, count 0 2006.285.15:53:18.51#ibcon#read 6, iclass 3, count 0 2006.285.15:53:18.51#ibcon#end of sib2, iclass 3, count 0 2006.285.15:53:18.51#ibcon#*mode == 0, iclass 3, count 0 2006.285.15:53:18.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.15:53:18.51#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.15:53:18.51#ibcon#*before write, iclass 3, count 0 2006.285.15:53:18.51#ibcon#enter sib2, iclass 3, count 0 2006.285.15:53:18.51#ibcon#flushed, iclass 3, count 0 2006.285.15:53:18.51#ibcon#about to write, iclass 3, count 0 2006.285.15:53:18.51#ibcon#wrote, iclass 3, count 0 2006.285.15:53:18.51#ibcon#about to read 3, iclass 3, count 0 2006.285.15:53:18.55#ibcon#read 3, iclass 3, count 0 2006.285.15:53:18.55#ibcon#about to read 4, iclass 3, count 0 2006.285.15:53:18.55#ibcon#read 4, iclass 3, count 0 2006.285.15:53:18.55#ibcon#about to read 5, iclass 3, count 0 2006.285.15:53:18.55#ibcon#read 5, iclass 3, count 0 2006.285.15:53:18.55#ibcon#about to read 6, iclass 3, count 0 2006.285.15:53:18.55#ibcon#read 6, iclass 3, count 0 2006.285.15:53:18.55#ibcon#end of sib2, iclass 3, count 0 2006.285.15:53:18.55#ibcon#*after write, iclass 3, count 0 2006.285.15:53:18.55#ibcon#*before return 0, iclass 3, count 0 2006.285.15:53:18.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:53:18.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.15:53:18.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.15:53:18.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.15:53:18.55$vck44/vb=5,4 2006.285.15:53:18.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.15:53:18.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.15:53:18.55#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:18.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:53:18.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:53:18.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:53:18.61#ibcon#enter wrdev, iclass 5, count 2 2006.285.15:53:18.61#ibcon#first serial, iclass 5, count 2 2006.285.15:53:18.61#ibcon#enter sib2, iclass 5, count 2 2006.285.15:53:18.61#ibcon#flushed, iclass 5, count 2 2006.285.15:53:18.61#ibcon#about to write, iclass 5, count 2 2006.285.15:53:18.61#ibcon#wrote, iclass 5, count 2 2006.285.15:53:18.61#ibcon#about to read 3, iclass 5, count 2 2006.285.15:53:18.63#ibcon#read 3, iclass 5, count 2 2006.285.15:53:18.63#ibcon#about to read 4, iclass 5, count 2 2006.285.15:53:18.63#ibcon#read 4, iclass 5, count 2 2006.285.15:53:18.63#ibcon#about to read 5, iclass 5, count 2 2006.285.15:53:18.63#ibcon#read 5, iclass 5, count 2 2006.285.15:53:18.63#ibcon#about to read 6, iclass 5, count 2 2006.285.15:53:18.63#ibcon#read 6, iclass 5, count 2 2006.285.15:53:18.63#ibcon#end of sib2, iclass 5, count 2 2006.285.15:53:18.63#ibcon#*mode == 0, iclass 5, count 2 2006.285.15:53:18.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.15:53:18.63#ibcon#[27=AT05-04\r\n] 2006.285.15:53:18.63#ibcon#*before write, iclass 5, count 2 2006.285.15:53:18.63#ibcon#enter sib2, iclass 5, count 2 2006.285.15:53:18.63#ibcon#flushed, iclass 5, count 2 2006.285.15:53:18.63#ibcon#about to write, iclass 5, count 2 2006.285.15:53:18.63#ibcon#wrote, iclass 5, count 2 2006.285.15:53:18.63#ibcon#about to read 3, iclass 5, count 2 2006.285.15:53:18.66#ibcon#read 3, iclass 5, count 2 2006.285.15:53:18.66#ibcon#about to read 4, iclass 5, count 2 2006.285.15:53:18.66#ibcon#read 4, iclass 5, count 2 2006.285.15:53:18.66#ibcon#about to read 5, iclass 5, count 2 2006.285.15:53:18.66#ibcon#read 5, iclass 5, count 2 2006.285.15:53:18.66#ibcon#about to read 6, iclass 5, count 2 2006.285.15:53:18.66#ibcon#read 6, iclass 5, count 2 2006.285.15:53:18.66#ibcon#end of sib2, iclass 5, count 2 2006.285.15:53:18.66#ibcon#*after write, iclass 5, count 2 2006.285.15:53:18.66#ibcon#*before return 0, iclass 5, count 2 2006.285.15:53:18.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:53:18.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.15:53:18.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.15:53:18.66#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:18.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:53:18.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:53:18.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:53:18.78#ibcon#enter wrdev, iclass 5, count 0 2006.285.15:53:18.78#ibcon#first serial, iclass 5, count 0 2006.285.15:53:18.78#ibcon#enter sib2, iclass 5, count 0 2006.285.15:53:18.78#ibcon#flushed, iclass 5, count 0 2006.285.15:53:18.78#ibcon#about to write, iclass 5, count 0 2006.285.15:53:18.78#ibcon#wrote, iclass 5, count 0 2006.285.15:53:18.78#ibcon#about to read 3, iclass 5, count 0 2006.285.15:53:18.80#ibcon#read 3, iclass 5, count 0 2006.285.15:53:18.80#ibcon#about to read 4, iclass 5, count 0 2006.285.15:53:18.80#ibcon#read 4, iclass 5, count 0 2006.285.15:53:18.80#ibcon#about to read 5, iclass 5, count 0 2006.285.15:53:18.80#ibcon#read 5, iclass 5, count 0 2006.285.15:53:18.80#ibcon#about to read 6, iclass 5, count 0 2006.285.15:53:18.80#ibcon#read 6, iclass 5, count 0 2006.285.15:53:18.80#ibcon#end of sib2, iclass 5, count 0 2006.285.15:53:18.80#ibcon#*mode == 0, iclass 5, count 0 2006.285.15:53:18.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.15:53:18.80#ibcon#[27=USB\r\n] 2006.285.15:53:18.80#ibcon#*before write, iclass 5, count 0 2006.285.15:53:18.80#ibcon#enter sib2, iclass 5, count 0 2006.285.15:53:18.80#ibcon#flushed, iclass 5, count 0 2006.285.15:53:18.80#ibcon#about to write, iclass 5, count 0 2006.285.15:53:18.80#ibcon#wrote, iclass 5, count 0 2006.285.15:53:18.80#ibcon#about to read 3, iclass 5, count 0 2006.285.15:53:18.83#ibcon#read 3, iclass 5, count 0 2006.285.15:53:18.83#ibcon#about to read 4, iclass 5, count 0 2006.285.15:53:18.83#ibcon#read 4, iclass 5, count 0 2006.285.15:53:18.83#ibcon#about to read 5, iclass 5, count 0 2006.285.15:53:18.83#ibcon#read 5, iclass 5, count 0 2006.285.15:53:18.83#ibcon#about to read 6, iclass 5, count 0 2006.285.15:53:18.83#ibcon#read 6, iclass 5, count 0 2006.285.15:53:18.83#ibcon#end of sib2, iclass 5, count 0 2006.285.15:53:18.83#ibcon#*after write, iclass 5, count 0 2006.285.15:53:18.83#ibcon#*before return 0, iclass 5, count 0 2006.285.15:53:18.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:53:18.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.15:53:18.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.15:53:18.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.15:53:18.83$vck44/vblo=6,719.99 2006.285.15:53:18.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.15:53:18.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.15:53:18.83#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:18.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:53:18.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:53:18.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:53:18.83#ibcon#enter wrdev, iclass 7, count 0 2006.285.15:53:18.83#ibcon#first serial, iclass 7, count 0 2006.285.15:53:18.83#ibcon#enter sib2, iclass 7, count 0 2006.285.15:53:18.83#ibcon#flushed, iclass 7, count 0 2006.285.15:53:18.83#ibcon#about to write, iclass 7, count 0 2006.285.15:53:18.83#ibcon#wrote, iclass 7, count 0 2006.285.15:53:18.83#ibcon#about to read 3, iclass 7, count 0 2006.285.15:53:18.85#ibcon#read 3, iclass 7, count 0 2006.285.15:53:18.85#ibcon#about to read 4, iclass 7, count 0 2006.285.15:53:18.85#ibcon#read 4, iclass 7, count 0 2006.285.15:53:18.85#ibcon#about to read 5, iclass 7, count 0 2006.285.15:53:18.85#ibcon#read 5, iclass 7, count 0 2006.285.15:53:18.85#ibcon#about to read 6, iclass 7, count 0 2006.285.15:53:18.85#ibcon#read 6, iclass 7, count 0 2006.285.15:53:18.85#ibcon#end of sib2, iclass 7, count 0 2006.285.15:53:18.85#ibcon#*mode == 0, iclass 7, count 0 2006.285.15:53:18.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.15:53:18.85#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.15:53:18.85#ibcon#*before write, iclass 7, count 0 2006.285.15:53:18.85#ibcon#enter sib2, iclass 7, count 0 2006.285.15:53:18.85#ibcon#flushed, iclass 7, count 0 2006.285.15:53:18.85#ibcon#about to write, iclass 7, count 0 2006.285.15:53:18.85#ibcon#wrote, iclass 7, count 0 2006.285.15:53:18.85#ibcon#about to read 3, iclass 7, count 0 2006.285.15:53:18.89#ibcon#read 3, iclass 7, count 0 2006.285.15:53:18.89#ibcon#about to read 4, iclass 7, count 0 2006.285.15:53:18.89#ibcon#read 4, iclass 7, count 0 2006.285.15:53:18.89#ibcon#about to read 5, iclass 7, count 0 2006.285.15:53:18.89#ibcon#read 5, iclass 7, count 0 2006.285.15:53:18.89#ibcon#about to read 6, iclass 7, count 0 2006.285.15:53:18.89#ibcon#read 6, iclass 7, count 0 2006.285.15:53:18.89#ibcon#end of sib2, iclass 7, count 0 2006.285.15:53:18.89#ibcon#*after write, iclass 7, count 0 2006.285.15:53:18.89#ibcon#*before return 0, iclass 7, count 0 2006.285.15:53:18.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:53:18.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.15:53:18.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.15:53:18.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.15:53:18.89$vck44/vb=6,3 2006.285.15:53:18.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.15:53:18.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.15:53:18.89#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:18.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:53:18.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:53:18.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:53:18.95#ibcon#enter wrdev, iclass 11, count 2 2006.285.15:53:18.95#ibcon#first serial, iclass 11, count 2 2006.285.15:53:18.95#ibcon#enter sib2, iclass 11, count 2 2006.285.15:53:18.95#ibcon#flushed, iclass 11, count 2 2006.285.15:53:18.95#ibcon#about to write, iclass 11, count 2 2006.285.15:53:18.95#ibcon#wrote, iclass 11, count 2 2006.285.15:53:18.95#ibcon#about to read 3, iclass 11, count 2 2006.285.15:53:18.97#ibcon#read 3, iclass 11, count 2 2006.285.15:53:18.97#ibcon#about to read 4, iclass 11, count 2 2006.285.15:53:18.97#ibcon#read 4, iclass 11, count 2 2006.285.15:53:18.97#ibcon#about to read 5, iclass 11, count 2 2006.285.15:53:18.97#ibcon#read 5, iclass 11, count 2 2006.285.15:53:18.97#ibcon#about to read 6, iclass 11, count 2 2006.285.15:53:18.97#ibcon#read 6, iclass 11, count 2 2006.285.15:53:18.97#ibcon#end of sib2, iclass 11, count 2 2006.285.15:53:18.97#ibcon#*mode == 0, iclass 11, count 2 2006.285.15:53:18.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.15:53:18.97#ibcon#[27=AT06-03\r\n] 2006.285.15:53:18.97#ibcon#*before write, iclass 11, count 2 2006.285.15:53:18.97#ibcon#enter sib2, iclass 11, count 2 2006.285.15:53:18.97#ibcon#flushed, iclass 11, count 2 2006.285.15:53:18.97#ibcon#about to write, iclass 11, count 2 2006.285.15:53:18.97#ibcon#wrote, iclass 11, count 2 2006.285.15:53:18.97#ibcon#about to read 3, iclass 11, count 2 2006.285.15:53:19.00#ibcon#read 3, iclass 11, count 2 2006.285.15:53:19.00#ibcon#about to read 4, iclass 11, count 2 2006.285.15:53:19.00#ibcon#read 4, iclass 11, count 2 2006.285.15:53:19.00#ibcon#about to read 5, iclass 11, count 2 2006.285.15:53:19.00#ibcon#read 5, iclass 11, count 2 2006.285.15:53:19.00#ibcon#about to read 6, iclass 11, count 2 2006.285.15:53:19.00#ibcon#read 6, iclass 11, count 2 2006.285.15:53:19.00#ibcon#end of sib2, iclass 11, count 2 2006.285.15:53:19.00#ibcon#*after write, iclass 11, count 2 2006.285.15:53:19.00#ibcon#*before return 0, iclass 11, count 2 2006.285.15:53:19.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:53:19.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.15:53:19.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.15:53:19.00#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:19.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:53:19.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:53:19.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:53:19.12#ibcon#enter wrdev, iclass 11, count 0 2006.285.15:53:19.12#ibcon#first serial, iclass 11, count 0 2006.285.15:53:19.12#ibcon#enter sib2, iclass 11, count 0 2006.285.15:53:19.12#ibcon#flushed, iclass 11, count 0 2006.285.15:53:19.12#ibcon#about to write, iclass 11, count 0 2006.285.15:53:19.12#ibcon#wrote, iclass 11, count 0 2006.285.15:53:19.12#ibcon#about to read 3, iclass 11, count 0 2006.285.15:53:19.14#ibcon#read 3, iclass 11, count 0 2006.285.15:53:19.14#ibcon#about to read 4, iclass 11, count 0 2006.285.15:53:19.14#ibcon#read 4, iclass 11, count 0 2006.285.15:53:19.14#ibcon#about to read 5, iclass 11, count 0 2006.285.15:53:19.14#ibcon#read 5, iclass 11, count 0 2006.285.15:53:19.14#ibcon#about to read 6, iclass 11, count 0 2006.285.15:53:19.14#ibcon#read 6, iclass 11, count 0 2006.285.15:53:19.14#ibcon#end of sib2, iclass 11, count 0 2006.285.15:53:19.14#ibcon#*mode == 0, iclass 11, count 0 2006.285.15:53:19.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.15:53:19.14#ibcon#[27=USB\r\n] 2006.285.15:53:19.14#ibcon#*before write, iclass 11, count 0 2006.285.15:53:19.14#ibcon#enter sib2, iclass 11, count 0 2006.285.15:53:19.14#ibcon#flushed, iclass 11, count 0 2006.285.15:53:19.14#ibcon#about to write, iclass 11, count 0 2006.285.15:53:19.14#ibcon#wrote, iclass 11, count 0 2006.285.15:53:19.14#ibcon#about to read 3, iclass 11, count 0 2006.285.15:53:19.17#ibcon#read 3, iclass 11, count 0 2006.285.15:53:19.17#ibcon#about to read 4, iclass 11, count 0 2006.285.15:53:19.17#ibcon#read 4, iclass 11, count 0 2006.285.15:53:19.17#ibcon#about to read 5, iclass 11, count 0 2006.285.15:53:19.17#ibcon#read 5, iclass 11, count 0 2006.285.15:53:19.17#ibcon#about to read 6, iclass 11, count 0 2006.285.15:53:19.17#ibcon#read 6, iclass 11, count 0 2006.285.15:53:19.17#ibcon#end of sib2, iclass 11, count 0 2006.285.15:53:19.17#ibcon#*after write, iclass 11, count 0 2006.285.15:53:19.17#ibcon#*before return 0, iclass 11, count 0 2006.285.15:53:19.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:53:19.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.15:53:19.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.15:53:19.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.15:53:19.17$vck44/vblo=7,734.99 2006.285.15:53:19.17#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.15:53:19.17#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.15:53:19.17#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:19.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:53:19.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:53:19.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:53:19.17#ibcon#enter wrdev, iclass 13, count 0 2006.285.15:53:19.17#ibcon#first serial, iclass 13, count 0 2006.285.15:53:19.17#ibcon#enter sib2, iclass 13, count 0 2006.285.15:53:19.17#ibcon#flushed, iclass 13, count 0 2006.285.15:53:19.17#ibcon#about to write, iclass 13, count 0 2006.285.15:53:19.17#ibcon#wrote, iclass 13, count 0 2006.285.15:53:19.17#ibcon#about to read 3, iclass 13, count 0 2006.285.15:53:19.19#ibcon#read 3, iclass 13, count 0 2006.285.15:53:19.19#ibcon#about to read 4, iclass 13, count 0 2006.285.15:53:19.19#ibcon#read 4, iclass 13, count 0 2006.285.15:53:19.19#ibcon#about to read 5, iclass 13, count 0 2006.285.15:53:19.19#ibcon#read 5, iclass 13, count 0 2006.285.15:53:19.19#ibcon#about to read 6, iclass 13, count 0 2006.285.15:53:19.19#ibcon#read 6, iclass 13, count 0 2006.285.15:53:19.19#ibcon#end of sib2, iclass 13, count 0 2006.285.15:53:19.19#ibcon#*mode == 0, iclass 13, count 0 2006.285.15:53:19.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.15:53:19.19#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.15:53:19.19#ibcon#*before write, iclass 13, count 0 2006.285.15:53:19.19#ibcon#enter sib2, iclass 13, count 0 2006.285.15:53:19.19#ibcon#flushed, iclass 13, count 0 2006.285.15:53:19.19#ibcon#about to write, iclass 13, count 0 2006.285.15:53:19.19#ibcon#wrote, iclass 13, count 0 2006.285.15:53:19.19#ibcon#about to read 3, iclass 13, count 0 2006.285.15:53:19.23#ibcon#read 3, iclass 13, count 0 2006.285.15:53:19.23#ibcon#about to read 4, iclass 13, count 0 2006.285.15:53:19.23#ibcon#read 4, iclass 13, count 0 2006.285.15:53:19.23#ibcon#about to read 5, iclass 13, count 0 2006.285.15:53:19.23#ibcon#read 5, iclass 13, count 0 2006.285.15:53:19.23#ibcon#about to read 6, iclass 13, count 0 2006.285.15:53:19.23#ibcon#read 6, iclass 13, count 0 2006.285.15:53:19.23#ibcon#end of sib2, iclass 13, count 0 2006.285.15:53:19.23#ibcon#*after write, iclass 13, count 0 2006.285.15:53:19.23#ibcon#*before return 0, iclass 13, count 0 2006.285.15:53:19.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:53:19.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.15:53:19.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.15:53:19.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.15:53:19.23$vck44/vb=7,4 2006.285.15:53:19.23#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.15:53:19.23#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.15:53:19.23#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:19.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:53:19.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:53:19.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:53:19.29#ibcon#enter wrdev, iclass 15, count 2 2006.285.15:53:19.29#ibcon#first serial, iclass 15, count 2 2006.285.15:53:19.29#ibcon#enter sib2, iclass 15, count 2 2006.285.15:53:19.29#ibcon#flushed, iclass 15, count 2 2006.285.15:53:19.29#ibcon#about to write, iclass 15, count 2 2006.285.15:53:19.29#ibcon#wrote, iclass 15, count 2 2006.285.15:53:19.29#ibcon#about to read 3, iclass 15, count 2 2006.285.15:53:19.31#ibcon#read 3, iclass 15, count 2 2006.285.15:53:19.31#ibcon#about to read 4, iclass 15, count 2 2006.285.15:53:19.31#ibcon#read 4, iclass 15, count 2 2006.285.15:53:19.31#ibcon#about to read 5, iclass 15, count 2 2006.285.15:53:19.31#ibcon#read 5, iclass 15, count 2 2006.285.15:53:19.31#ibcon#about to read 6, iclass 15, count 2 2006.285.15:53:19.31#ibcon#read 6, iclass 15, count 2 2006.285.15:53:19.31#ibcon#end of sib2, iclass 15, count 2 2006.285.15:53:19.31#ibcon#*mode == 0, iclass 15, count 2 2006.285.15:53:19.31#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.15:53:19.31#ibcon#[27=AT07-04\r\n] 2006.285.15:53:19.31#ibcon#*before write, iclass 15, count 2 2006.285.15:53:19.31#ibcon#enter sib2, iclass 15, count 2 2006.285.15:53:19.31#ibcon#flushed, iclass 15, count 2 2006.285.15:53:19.31#ibcon#about to write, iclass 15, count 2 2006.285.15:53:19.31#ibcon#wrote, iclass 15, count 2 2006.285.15:53:19.31#ibcon#about to read 3, iclass 15, count 2 2006.285.15:53:19.34#ibcon#read 3, iclass 15, count 2 2006.285.15:53:19.34#ibcon#about to read 4, iclass 15, count 2 2006.285.15:53:19.34#ibcon#read 4, iclass 15, count 2 2006.285.15:53:19.34#ibcon#about to read 5, iclass 15, count 2 2006.285.15:53:19.34#ibcon#read 5, iclass 15, count 2 2006.285.15:53:19.34#ibcon#about to read 6, iclass 15, count 2 2006.285.15:53:19.34#ibcon#read 6, iclass 15, count 2 2006.285.15:53:19.34#ibcon#end of sib2, iclass 15, count 2 2006.285.15:53:19.34#ibcon#*after write, iclass 15, count 2 2006.285.15:53:19.34#ibcon#*before return 0, iclass 15, count 2 2006.285.15:53:19.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:53:19.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.15:53:19.34#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.15:53:19.34#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:19.34#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:53:19.46#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:53:19.46#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:53:19.46#ibcon#enter wrdev, iclass 15, count 0 2006.285.15:53:19.46#ibcon#first serial, iclass 15, count 0 2006.285.15:53:19.46#ibcon#enter sib2, iclass 15, count 0 2006.285.15:53:19.46#ibcon#flushed, iclass 15, count 0 2006.285.15:53:19.46#ibcon#about to write, iclass 15, count 0 2006.285.15:53:19.46#ibcon#wrote, iclass 15, count 0 2006.285.15:53:19.46#ibcon#about to read 3, iclass 15, count 0 2006.285.15:53:19.48#ibcon#read 3, iclass 15, count 0 2006.285.15:53:19.48#ibcon#about to read 4, iclass 15, count 0 2006.285.15:53:19.48#ibcon#read 4, iclass 15, count 0 2006.285.15:53:19.48#ibcon#about to read 5, iclass 15, count 0 2006.285.15:53:19.48#ibcon#read 5, iclass 15, count 0 2006.285.15:53:19.48#ibcon#about to read 6, iclass 15, count 0 2006.285.15:53:19.48#ibcon#read 6, iclass 15, count 0 2006.285.15:53:19.48#ibcon#end of sib2, iclass 15, count 0 2006.285.15:53:19.48#ibcon#*mode == 0, iclass 15, count 0 2006.285.15:53:19.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.15:53:19.48#ibcon#[27=USB\r\n] 2006.285.15:53:19.48#ibcon#*before write, iclass 15, count 0 2006.285.15:53:19.48#ibcon#enter sib2, iclass 15, count 0 2006.285.15:53:19.48#ibcon#flushed, iclass 15, count 0 2006.285.15:53:19.48#ibcon#about to write, iclass 15, count 0 2006.285.15:53:19.48#ibcon#wrote, iclass 15, count 0 2006.285.15:53:19.48#ibcon#about to read 3, iclass 15, count 0 2006.285.15:53:19.51#ibcon#read 3, iclass 15, count 0 2006.285.15:53:19.51#ibcon#about to read 4, iclass 15, count 0 2006.285.15:53:19.51#ibcon#read 4, iclass 15, count 0 2006.285.15:53:19.51#ibcon#about to read 5, iclass 15, count 0 2006.285.15:53:19.51#ibcon#read 5, iclass 15, count 0 2006.285.15:53:19.51#ibcon#about to read 6, iclass 15, count 0 2006.285.15:53:19.51#ibcon#read 6, iclass 15, count 0 2006.285.15:53:19.51#ibcon#end of sib2, iclass 15, count 0 2006.285.15:53:19.51#ibcon#*after write, iclass 15, count 0 2006.285.15:53:19.51#ibcon#*before return 0, iclass 15, count 0 2006.285.15:53:19.51#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:53:19.51#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.15:53:19.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.15:53:19.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.15:53:19.51$vck44/vblo=8,744.99 2006.285.15:53:19.51#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.15:53:19.51#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.15:53:19.51#ibcon#ireg 17 cls_cnt 0 2006.285.15:53:19.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:53:19.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:53:19.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:53:19.51#ibcon#enter wrdev, iclass 17, count 0 2006.285.15:53:19.51#ibcon#first serial, iclass 17, count 0 2006.285.15:53:19.51#ibcon#enter sib2, iclass 17, count 0 2006.285.15:53:19.51#ibcon#flushed, iclass 17, count 0 2006.285.15:53:19.51#ibcon#about to write, iclass 17, count 0 2006.285.15:53:19.51#ibcon#wrote, iclass 17, count 0 2006.285.15:53:19.51#ibcon#about to read 3, iclass 17, count 0 2006.285.15:53:19.53#ibcon#read 3, iclass 17, count 0 2006.285.15:53:19.53#ibcon#about to read 4, iclass 17, count 0 2006.285.15:53:19.53#ibcon#read 4, iclass 17, count 0 2006.285.15:53:19.53#ibcon#about to read 5, iclass 17, count 0 2006.285.15:53:19.53#ibcon#read 5, iclass 17, count 0 2006.285.15:53:19.53#ibcon#about to read 6, iclass 17, count 0 2006.285.15:53:19.53#ibcon#read 6, iclass 17, count 0 2006.285.15:53:19.53#ibcon#end of sib2, iclass 17, count 0 2006.285.15:53:19.53#ibcon#*mode == 0, iclass 17, count 0 2006.285.15:53:19.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.15:53:19.53#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.15:53:19.53#ibcon#*before write, iclass 17, count 0 2006.285.15:53:19.53#ibcon#enter sib2, iclass 17, count 0 2006.285.15:53:19.53#ibcon#flushed, iclass 17, count 0 2006.285.15:53:19.53#ibcon#about to write, iclass 17, count 0 2006.285.15:53:19.53#ibcon#wrote, iclass 17, count 0 2006.285.15:53:19.53#ibcon#about to read 3, iclass 17, count 0 2006.285.15:53:19.57#ibcon#read 3, iclass 17, count 0 2006.285.15:53:19.57#ibcon#about to read 4, iclass 17, count 0 2006.285.15:53:19.57#ibcon#read 4, iclass 17, count 0 2006.285.15:53:19.57#ibcon#about to read 5, iclass 17, count 0 2006.285.15:53:19.57#ibcon#read 5, iclass 17, count 0 2006.285.15:53:19.57#ibcon#about to read 6, iclass 17, count 0 2006.285.15:53:19.57#ibcon#read 6, iclass 17, count 0 2006.285.15:53:19.57#ibcon#end of sib2, iclass 17, count 0 2006.285.15:53:19.57#ibcon#*after write, iclass 17, count 0 2006.285.15:53:19.57#ibcon#*before return 0, iclass 17, count 0 2006.285.15:53:19.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:53:19.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.15:53:19.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.15:53:19.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.15:53:19.57$vck44/vb=8,4 2006.285.15:53:19.57#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.15:53:19.57#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.15:53:19.57#ibcon#ireg 11 cls_cnt 2 2006.285.15:53:19.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:53:19.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:53:19.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:53:19.63#ibcon#enter wrdev, iclass 19, count 2 2006.285.15:53:19.63#ibcon#first serial, iclass 19, count 2 2006.285.15:53:19.63#ibcon#enter sib2, iclass 19, count 2 2006.285.15:53:19.63#ibcon#flushed, iclass 19, count 2 2006.285.15:53:19.63#ibcon#about to write, iclass 19, count 2 2006.285.15:53:19.63#ibcon#wrote, iclass 19, count 2 2006.285.15:53:19.63#ibcon#about to read 3, iclass 19, count 2 2006.285.15:53:19.65#ibcon#read 3, iclass 19, count 2 2006.285.15:53:19.65#ibcon#about to read 4, iclass 19, count 2 2006.285.15:53:19.65#ibcon#read 4, iclass 19, count 2 2006.285.15:53:19.65#ibcon#about to read 5, iclass 19, count 2 2006.285.15:53:19.65#ibcon#read 5, iclass 19, count 2 2006.285.15:53:19.65#ibcon#about to read 6, iclass 19, count 2 2006.285.15:53:19.65#ibcon#read 6, iclass 19, count 2 2006.285.15:53:19.65#ibcon#end of sib2, iclass 19, count 2 2006.285.15:53:19.65#ibcon#*mode == 0, iclass 19, count 2 2006.285.15:53:19.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.15:53:19.65#ibcon#[27=AT08-04\r\n] 2006.285.15:53:19.65#ibcon#*before write, iclass 19, count 2 2006.285.15:53:19.65#ibcon#enter sib2, iclass 19, count 2 2006.285.15:53:19.65#ibcon#flushed, iclass 19, count 2 2006.285.15:53:19.65#ibcon#about to write, iclass 19, count 2 2006.285.15:53:19.65#ibcon#wrote, iclass 19, count 2 2006.285.15:53:19.65#ibcon#about to read 3, iclass 19, count 2 2006.285.15:53:19.68#ibcon#read 3, iclass 19, count 2 2006.285.15:53:19.68#ibcon#about to read 4, iclass 19, count 2 2006.285.15:53:19.68#ibcon#read 4, iclass 19, count 2 2006.285.15:53:19.68#ibcon#about to read 5, iclass 19, count 2 2006.285.15:53:19.68#ibcon#read 5, iclass 19, count 2 2006.285.15:53:19.68#ibcon#about to read 6, iclass 19, count 2 2006.285.15:53:19.68#ibcon#read 6, iclass 19, count 2 2006.285.15:53:19.68#ibcon#end of sib2, iclass 19, count 2 2006.285.15:53:19.68#ibcon#*after write, iclass 19, count 2 2006.285.15:53:19.68#ibcon#*before return 0, iclass 19, count 2 2006.285.15:53:19.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:53:19.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.15:53:19.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.15:53:19.68#ibcon#ireg 7 cls_cnt 0 2006.285.15:53:19.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:53:19.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:53:19.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:53:19.80#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:53:19.80#ibcon#first serial, iclass 19, count 0 2006.285.15:53:19.80#ibcon#enter sib2, iclass 19, count 0 2006.285.15:53:19.80#ibcon#flushed, iclass 19, count 0 2006.285.15:53:19.80#ibcon#about to write, iclass 19, count 0 2006.285.15:53:19.80#ibcon#wrote, iclass 19, count 0 2006.285.15:53:19.80#ibcon#about to read 3, iclass 19, count 0 2006.285.15:53:19.82#ibcon#read 3, iclass 19, count 0 2006.285.15:53:19.82#ibcon#about to read 4, iclass 19, count 0 2006.285.15:53:19.82#ibcon#read 4, iclass 19, count 0 2006.285.15:53:19.82#ibcon#about to read 5, iclass 19, count 0 2006.285.15:53:19.82#ibcon#read 5, iclass 19, count 0 2006.285.15:53:19.82#ibcon#about to read 6, iclass 19, count 0 2006.285.15:53:19.82#ibcon#read 6, iclass 19, count 0 2006.285.15:53:19.82#ibcon#end of sib2, iclass 19, count 0 2006.285.15:53:19.82#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:53:19.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:53:19.82#ibcon#[27=USB\r\n] 2006.285.15:53:19.82#ibcon#*before write, iclass 19, count 0 2006.285.15:53:19.82#ibcon#enter sib2, iclass 19, count 0 2006.285.15:53:19.82#ibcon#flushed, iclass 19, count 0 2006.285.15:53:19.82#ibcon#about to write, iclass 19, count 0 2006.285.15:53:19.82#ibcon#wrote, iclass 19, count 0 2006.285.15:53:19.82#ibcon#about to read 3, iclass 19, count 0 2006.285.15:53:19.85#ibcon#read 3, iclass 19, count 0 2006.285.15:53:19.85#ibcon#about to read 4, iclass 19, count 0 2006.285.15:53:19.85#ibcon#read 4, iclass 19, count 0 2006.285.15:53:19.85#ibcon#about to read 5, iclass 19, count 0 2006.285.15:53:19.85#ibcon#read 5, iclass 19, count 0 2006.285.15:53:19.85#ibcon#about to read 6, iclass 19, count 0 2006.285.15:53:19.85#ibcon#read 6, iclass 19, count 0 2006.285.15:53:19.85#ibcon#end of sib2, iclass 19, count 0 2006.285.15:53:19.85#ibcon#*after write, iclass 19, count 0 2006.285.15:53:19.85#ibcon#*before return 0, iclass 19, count 0 2006.285.15:53:19.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:53:19.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.15:53:19.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:53:19.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:53:19.85$vck44/vabw=wide 2006.285.15:53:19.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.15:53:19.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.15:53:19.85#ibcon#ireg 8 cls_cnt 0 2006.285.15:53:19.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:53:19.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:53:19.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:53:19.85#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:53:19.85#ibcon#first serial, iclass 21, count 0 2006.285.15:53:19.85#ibcon#enter sib2, iclass 21, count 0 2006.285.15:53:19.85#ibcon#flushed, iclass 21, count 0 2006.285.15:53:19.85#ibcon#about to write, iclass 21, count 0 2006.285.15:53:19.85#ibcon#wrote, iclass 21, count 0 2006.285.15:53:19.85#ibcon#about to read 3, iclass 21, count 0 2006.285.15:53:19.87#ibcon#read 3, iclass 21, count 0 2006.285.15:53:19.87#ibcon#about to read 4, iclass 21, count 0 2006.285.15:53:19.87#ibcon#read 4, iclass 21, count 0 2006.285.15:53:19.87#ibcon#about to read 5, iclass 21, count 0 2006.285.15:53:19.87#ibcon#read 5, iclass 21, count 0 2006.285.15:53:19.87#ibcon#about to read 6, iclass 21, count 0 2006.285.15:53:19.87#ibcon#read 6, iclass 21, count 0 2006.285.15:53:19.87#ibcon#end of sib2, iclass 21, count 0 2006.285.15:53:19.87#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:53:19.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:53:19.87#ibcon#[25=BW32\r\n] 2006.285.15:53:19.87#ibcon#*before write, iclass 21, count 0 2006.285.15:53:19.87#ibcon#enter sib2, iclass 21, count 0 2006.285.15:53:19.87#ibcon#flushed, iclass 21, count 0 2006.285.15:53:19.87#ibcon#about to write, iclass 21, count 0 2006.285.15:53:19.87#ibcon#wrote, iclass 21, count 0 2006.285.15:53:19.87#ibcon#about to read 3, iclass 21, count 0 2006.285.15:53:19.90#ibcon#read 3, iclass 21, count 0 2006.285.15:53:19.90#ibcon#about to read 4, iclass 21, count 0 2006.285.15:53:19.90#ibcon#read 4, iclass 21, count 0 2006.285.15:53:19.90#ibcon#about to read 5, iclass 21, count 0 2006.285.15:53:19.90#ibcon#read 5, iclass 21, count 0 2006.285.15:53:19.90#ibcon#about to read 6, iclass 21, count 0 2006.285.15:53:19.90#ibcon#read 6, iclass 21, count 0 2006.285.15:53:19.90#ibcon#end of sib2, iclass 21, count 0 2006.285.15:53:19.90#ibcon#*after write, iclass 21, count 0 2006.285.15:53:19.90#ibcon#*before return 0, iclass 21, count 0 2006.285.15:53:19.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:53:19.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.15:53:19.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:53:19.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:53:19.90$vck44/vbbw=wide 2006.285.15:53:19.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.15:53:19.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.15:53:19.90#ibcon#ireg 8 cls_cnt 0 2006.285.15:53:19.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:53:19.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:53:19.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:53:19.97#ibcon#enter wrdev, iclass 23, count 0 2006.285.15:53:19.97#ibcon#first serial, iclass 23, count 0 2006.285.15:53:19.97#ibcon#enter sib2, iclass 23, count 0 2006.285.15:53:19.97#ibcon#flushed, iclass 23, count 0 2006.285.15:53:19.97#ibcon#about to write, iclass 23, count 0 2006.285.15:53:19.97#ibcon#wrote, iclass 23, count 0 2006.285.15:53:19.97#ibcon#about to read 3, iclass 23, count 0 2006.285.15:53:19.99#ibcon#read 3, iclass 23, count 0 2006.285.15:53:19.99#ibcon#about to read 4, iclass 23, count 0 2006.285.15:53:19.99#ibcon#read 4, iclass 23, count 0 2006.285.15:53:19.99#ibcon#about to read 5, iclass 23, count 0 2006.285.15:53:19.99#ibcon#read 5, iclass 23, count 0 2006.285.15:53:19.99#ibcon#about to read 6, iclass 23, count 0 2006.285.15:53:19.99#ibcon#read 6, iclass 23, count 0 2006.285.15:53:19.99#ibcon#end of sib2, iclass 23, count 0 2006.285.15:53:19.99#ibcon#*mode == 0, iclass 23, count 0 2006.285.15:53:19.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.15:53:19.99#ibcon#[27=BW32\r\n] 2006.285.15:53:19.99#ibcon#*before write, iclass 23, count 0 2006.285.15:53:19.99#ibcon#enter sib2, iclass 23, count 0 2006.285.15:53:19.99#ibcon#flushed, iclass 23, count 0 2006.285.15:53:19.99#ibcon#about to write, iclass 23, count 0 2006.285.15:53:19.99#ibcon#wrote, iclass 23, count 0 2006.285.15:53:19.99#ibcon#about to read 3, iclass 23, count 0 2006.285.15:53:20.02#ibcon#read 3, iclass 23, count 0 2006.285.15:53:20.02#ibcon#about to read 4, iclass 23, count 0 2006.285.15:53:20.02#ibcon#read 4, iclass 23, count 0 2006.285.15:53:20.02#ibcon#about to read 5, iclass 23, count 0 2006.285.15:53:20.02#ibcon#read 5, iclass 23, count 0 2006.285.15:53:20.02#ibcon#about to read 6, iclass 23, count 0 2006.285.15:53:20.02#ibcon#read 6, iclass 23, count 0 2006.285.15:53:20.02#ibcon#end of sib2, iclass 23, count 0 2006.285.15:53:20.02#ibcon#*after write, iclass 23, count 0 2006.285.15:53:20.02#ibcon#*before return 0, iclass 23, count 0 2006.285.15:53:20.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:53:20.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.15:53:20.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.15:53:20.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.15:53:20.02$setupk4/ifdk4 2006.285.15:53:20.02$ifdk4/lo= 2006.285.15:53:20.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.15:53:20.02$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.15:53:20.02$ifdk4/patch= 2006.285.15:53:20.02$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.15:53:20.02$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.15:53:20.02$setupk4/!*+20s 2006.285.15:53:21.13#abcon#<5=/16 0.9 2.0 18.73 931014.9\r\n> 2006.285.15:53:21.15#abcon#{5=INTERFACE CLEAR} 2006.285.15:53:21.21#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:53:28.13#trakl#Source acquired 2006.285.15:53:29.13#flagr#flagr/antenna,acquired 2006.285.15:53:31.30#abcon#<5=/16 0.9 2.0 18.73 931015.0\r\n> 2006.285.15:53:31.32#abcon#{5=INTERFACE CLEAR} 2006.285.15:53:31.38#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:53:33.96$setupk4/"tpicd 2006.285.15:53:33.96$setupk4/echo=off 2006.285.15:53:33.96$setupk4/xlog=off 2006.285.15:53:33.96:!2006.285.15:55:38 2006.285.15:55:38.00:preob 2006.285.15:55:39.14/onsource/TRACKING 2006.285.15:55:39.14:!2006.285.15:55:48 2006.285.15:55:48.00:"tape 2006.285.15:55:48.00:"st=record 2006.285.15:55:48.00:data_valid=on 2006.285.15:55:48.00:midob 2006.285.15:55:48.14/onsource/TRACKING 2006.285.15:55:48.14/wx/18.69,1014.9,93 2006.285.15:55:48.24/cable/+6.4994E-03 2006.285.15:55:49.33/va/01,07,usb,yes,32,34 2006.285.15:55:49.33/va/02,06,usb,yes,32,32 2006.285.15:55:49.33/va/03,07,usb,yes,31,33 2006.285.15:55:49.33/va/04,06,usb,yes,33,34 2006.285.15:55:49.33/va/05,03,usb,yes,32,33 2006.285.15:55:49.33/va/06,04,usb,yes,29,29 2006.285.15:55:49.33/va/07,04,usb,yes,30,30 2006.285.15:55:49.33/va/08,03,usb,yes,30,37 2006.285.15:55:49.56/valo/01,524.99,yes,locked 2006.285.15:55:49.56/valo/02,534.99,yes,locked 2006.285.15:55:49.56/valo/03,564.99,yes,locked 2006.285.15:55:49.56/valo/04,624.99,yes,locked 2006.285.15:55:49.56/valo/05,734.99,yes,locked 2006.285.15:55:49.56/valo/06,814.99,yes,locked 2006.285.15:55:49.56/valo/07,864.99,yes,locked 2006.285.15:55:49.56/valo/08,884.99,yes,locked 2006.285.15:55:50.65/vb/01,04,usb,yes,30,28 2006.285.15:55:50.65/vb/02,05,usb,yes,28,28 2006.285.15:55:50.65/vb/03,04,usb,yes,29,32 2006.285.15:55:50.65/vb/04,05,usb,yes,29,28 2006.285.15:55:50.65/vb/05,04,usb,yes,26,28 2006.285.15:55:50.65/vb/06,03,usb,yes,37,33 2006.285.15:55:50.65/vb/07,04,usb,yes,30,30 2006.285.15:55:50.65/vb/08,04,usb,yes,27,31 2006.285.15:55:50.88/vblo/01,629.99,yes,locked 2006.285.15:55:50.88/vblo/02,634.99,yes,locked 2006.285.15:55:50.88/vblo/03,649.99,yes,locked 2006.285.15:55:50.88/vblo/04,679.99,yes,locked 2006.285.15:55:50.88/vblo/05,709.99,yes,locked 2006.285.15:55:50.88/vblo/06,719.99,yes,locked 2006.285.15:55:50.88/vblo/07,734.99,yes,locked 2006.285.15:55:50.88/vblo/08,744.99,yes,locked 2006.285.15:55:51.03/vabw/8 2006.285.15:55:51.18/vbbw/8 2006.285.15:55:51.27/xfe/off,on,12.2 2006.285.15:55:51.64/ifatt/23,28,28,28 2006.285.15:55:52.08/fmout-gps/S +2.63E-07 2006.285.15:55:52.09:!2006.285.15:57:38 2006.285.15:57:38.01:data_valid=off 2006.285.15:57:38.02:"et 2006.285.15:57:38.02:!+3s 2006.285.15:57:41.04:"tape 2006.285.15:57:41.05:postob 2006.285.15:57:41.24/cable/+6.5014E-03 2006.285.15:57:41.24/wx/18.67,1014.9,93 2006.285.15:57:41.29/fmout-gps/S +2.66E-07 2006.285.15:57:41.30:scan_name=285-1559,jd0610,310 2006.285.15:57:41.30:source=nrao150,035929.75,505750.2,2000.0,cw 2006.285.15:57:42.15#flagr#flagr/antenna,new-source 2006.285.15:57:42.15:checkk5 2006.285.15:57:42.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.15:57:43.18/chk_autoobs//k5ts2/ autoobs is running! 2006.285.15:57:43.64/chk_autoobs//k5ts3/ autoobs is running! 2006.285.15:57:44.16/chk_autoobs//k5ts4/ autoobs is running! 2006.285.15:57:44.54/chk_obsdata//k5ts1/T2851555??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.15:57:44.96/chk_obsdata//k5ts2/T2851555??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.15:57:45.47/chk_obsdata//k5ts3/T2851555??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.15:57:45.84/chk_obsdata//k5ts4/T2851555??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.15:57:46.84/k5log//k5ts1_log_newline 2006.285.15:57:48.06/k5log//k5ts2_log_newline 2006.285.15:57:49.06/k5log//k5ts3_log_newline 2006.285.15:57:50.28/k5log//k5ts4_log_newline 2006.285.15:57:50.30/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.15:57:50.30:setupk4=1 2006.285.15:57:50.30$setupk4/echo=on 2006.285.15:57:50.30$setupk4/pcalon 2006.285.15:57:50.30$pcalon/"no phase cal control is implemented here 2006.285.15:57:50.30$setupk4/"tpicd=stop 2006.285.15:57:50.30$setupk4/"rec=synch_on 2006.285.15:57:50.30$setupk4/"rec_mode=128 2006.285.15:57:50.30$setupk4/!* 2006.285.15:57:50.30$setupk4/recpk4 2006.285.15:57:50.30$recpk4/recpatch= 2006.285.15:57:50.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.15:57:50.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.15:57:50.31$setupk4/vck44 2006.285.15:57:50.31$vck44/valo=1,524.99 2006.285.15:57:50.31#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.15:57:50.31#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.15:57:50.31#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:50.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:57:50.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:57:50.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:57:50.31#ibcon#enter wrdev, iclass 28, count 0 2006.285.15:57:50.31#ibcon#first serial, iclass 28, count 0 2006.285.15:57:50.31#ibcon#enter sib2, iclass 28, count 0 2006.285.15:57:50.31#ibcon#flushed, iclass 28, count 0 2006.285.15:57:50.31#ibcon#about to write, iclass 28, count 0 2006.285.15:57:50.31#ibcon#wrote, iclass 28, count 0 2006.285.15:57:50.31#ibcon#about to read 3, iclass 28, count 0 2006.285.15:57:50.32#ibcon#read 3, iclass 28, count 0 2006.285.15:57:50.32#ibcon#about to read 4, iclass 28, count 0 2006.285.15:57:50.32#ibcon#read 4, iclass 28, count 0 2006.285.15:57:50.32#ibcon#about to read 5, iclass 28, count 0 2006.285.15:57:50.32#ibcon#read 5, iclass 28, count 0 2006.285.15:57:50.32#ibcon#about to read 6, iclass 28, count 0 2006.285.15:57:50.32#ibcon#read 6, iclass 28, count 0 2006.285.15:57:50.32#ibcon#end of sib2, iclass 28, count 0 2006.285.15:57:50.32#ibcon#*mode == 0, iclass 28, count 0 2006.285.15:57:50.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.15:57:50.32#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.15:57:50.32#ibcon#*before write, iclass 28, count 0 2006.285.15:57:50.32#ibcon#enter sib2, iclass 28, count 0 2006.285.15:57:50.33#ibcon#flushed, iclass 28, count 0 2006.285.15:57:50.33#ibcon#about to write, iclass 28, count 0 2006.285.15:57:50.33#ibcon#wrote, iclass 28, count 0 2006.285.15:57:50.33#ibcon#about to read 3, iclass 28, count 0 2006.285.15:57:50.37#ibcon#read 3, iclass 28, count 0 2006.285.15:57:50.37#ibcon#about to read 4, iclass 28, count 0 2006.285.15:57:50.37#ibcon#read 4, iclass 28, count 0 2006.285.15:57:50.37#ibcon#about to read 5, iclass 28, count 0 2006.285.15:57:50.37#ibcon#read 5, iclass 28, count 0 2006.285.15:57:50.37#ibcon#about to read 6, iclass 28, count 0 2006.285.15:57:50.37#ibcon#read 6, iclass 28, count 0 2006.285.15:57:50.37#ibcon#end of sib2, iclass 28, count 0 2006.285.15:57:50.37#ibcon#*after write, iclass 28, count 0 2006.285.15:57:50.37#ibcon#*before return 0, iclass 28, count 0 2006.285.15:57:50.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:57:50.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:57:50.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.15:57:50.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.15:57:50.38$vck44/va=1,7 2006.285.15:57:50.38#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.15:57:50.38#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.15:57:50.38#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:50.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:57:50.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:57:50.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:57:50.38#ibcon#enter wrdev, iclass 30, count 2 2006.285.15:57:50.38#ibcon#first serial, iclass 30, count 2 2006.285.15:57:50.38#ibcon#enter sib2, iclass 30, count 2 2006.285.15:57:50.38#ibcon#flushed, iclass 30, count 2 2006.285.15:57:50.38#ibcon#about to write, iclass 30, count 2 2006.285.15:57:50.38#ibcon#wrote, iclass 30, count 2 2006.285.15:57:50.38#ibcon#about to read 3, iclass 30, count 2 2006.285.15:57:50.39#ibcon#read 3, iclass 30, count 2 2006.285.15:57:50.39#ibcon#about to read 4, iclass 30, count 2 2006.285.15:57:50.39#ibcon#read 4, iclass 30, count 2 2006.285.15:57:50.39#ibcon#about to read 5, iclass 30, count 2 2006.285.15:57:50.39#ibcon#read 5, iclass 30, count 2 2006.285.15:57:50.39#ibcon#about to read 6, iclass 30, count 2 2006.285.15:57:50.39#ibcon#read 6, iclass 30, count 2 2006.285.15:57:50.39#ibcon#end of sib2, iclass 30, count 2 2006.285.15:57:50.39#ibcon#*mode == 0, iclass 30, count 2 2006.285.15:57:50.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.15:57:50.39#ibcon#[25=AT01-07\r\n] 2006.285.15:57:50.39#ibcon#*before write, iclass 30, count 2 2006.285.15:57:50.39#ibcon#enter sib2, iclass 30, count 2 2006.285.15:57:50.40#ibcon#flushed, iclass 30, count 2 2006.285.15:57:50.40#ibcon#about to write, iclass 30, count 2 2006.285.15:57:50.40#ibcon#wrote, iclass 30, count 2 2006.285.15:57:50.40#ibcon#about to read 3, iclass 30, count 2 2006.285.15:57:50.42#ibcon#read 3, iclass 30, count 2 2006.285.15:57:50.42#ibcon#about to read 4, iclass 30, count 2 2006.285.15:57:50.42#ibcon#read 4, iclass 30, count 2 2006.285.15:57:50.42#ibcon#about to read 5, iclass 30, count 2 2006.285.15:57:50.42#ibcon#read 5, iclass 30, count 2 2006.285.15:57:50.42#ibcon#about to read 6, iclass 30, count 2 2006.285.15:57:50.42#ibcon#read 6, iclass 30, count 2 2006.285.15:57:50.42#ibcon#end of sib2, iclass 30, count 2 2006.285.15:57:50.42#ibcon#*after write, iclass 30, count 2 2006.285.15:57:50.42#ibcon#*before return 0, iclass 30, count 2 2006.285.15:57:50.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:57:50.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:57:50.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.15:57:50.43#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:50.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:57:50.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:57:50.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:57:50.53#ibcon#enter wrdev, iclass 30, count 0 2006.285.15:57:50.53#ibcon#first serial, iclass 30, count 0 2006.285.15:57:50.53#ibcon#enter sib2, iclass 30, count 0 2006.285.15:57:50.53#ibcon#flushed, iclass 30, count 0 2006.285.15:57:50.53#ibcon#about to write, iclass 30, count 0 2006.285.15:57:50.53#ibcon#wrote, iclass 30, count 0 2006.285.15:57:50.53#ibcon#about to read 3, iclass 30, count 0 2006.285.15:57:50.55#ibcon#read 3, iclass 30, count 0 2006.285.15:57:50.55#ibcon#about to read 4, iclass 30, count 0 2006.285.15:57:50.55#ibcon#read 4, iclass 30, count 0 2006.285.15:57:50.55#ibcon#about to read 5, iclass 30, count 0 2006.285.15:57:50.55#ibcon#read 5, iclass 30, count 0 2006.285.15:57:50.55#ibcon#about to read 6, iclass 30, count 0 2006.285.15:57:50.55#ibcon#read 6, iclass 30, count 0 2006.285.15:57:50.55#ibcon#end of sib2, iclass 30, count 0 2006.285.15:57:50.55#ibcon#*mode == 0, iclass 30, count 0 2006.285.15:57:50.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.15:57:50.55#ibcon#[25=USB\r\n] 2006.285.15:57:50.55#ibcon#*before write, iclass 30, count 0 2006.285.15:57:50.55#ibcon#enter sib2, iclass 30, count 0 2006.285.15:57:50.55#ibcon#flushed, iclass 30, count 0 2006.285.15:57:50.55#ibcon#about to write, iclass 30, count 0 2006.285.15:57:50.56#ibcon#wrote, iclass 30, count 0 2006.285.15:57:50.56#ibcon#about to read 3, iclass 30, count 0 2006.285.15:57:50.58#ibcon#read 3, iclass 30, count 0 2006.285.15:57:50.58#ibcon#about to read 4, iclass 30, count 0 2006.285.15:57:50.58#ibcon#read 4, iclass 30, count 0 2006.285.15:57:50.58#ibcon#about to read 5, iclass 30, count 0 2006.285.15:57:50.58#ibcon#read 5, iclass 30, count 0 2006.285.15:57:50.58#ibcon#about to read 6, iclass 30, count 0 2006.285.15:57:50.58#ibcon#read 6, iclass 30, count 0 2006.285.15:57:50.58#ibcon#end of sib2, iclass 30, count 0 2006.285.15:57:50.58#ibcon#*after write, iclass 30, count 0 2006.285.15:57:50.58#ibcon#*before return 0, iclass 30, count 0 2006.285.15:57:50.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:57:50.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:57:50.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.15:57:50.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.15:57:50.59$vck44/valo=2,534.99 2006.285.15:57:50.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.15:57:50.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.15:57:50.59#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:50.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:57:50.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:57:50.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:57:50.59#ibcon#enter wrdev, iclass 32, count 0 2006.285.15:57:50.59#ibcon#first serial, iclass 32, count 0 2006.285.15:57:50.59#ibcon#enter sib2, iclass 32, count 0 2006.285.15:57:50.59#ibcon#flushed, iclass 32, count 0 2006.285.15:57:50.59#ibcon#about to write, iclass 32, count 0 2006.285.15:57:50.59#ibcon#wrote, iclass 32, count 0 2006.285.15:57:50.59#ibcon#about to read 3, iclass 32, count 0 2006.285.15:57:50.60#ibcon#read 3, iclass 32, count 0 2006.285.15:57:50.60#ibcon#about to read 4, iclass 32, count 0 2006.285.15:57:50.60#ibcon#read 4, iclass 32, count 0 2006.285.15:57:50.60#ibcon#about to read 5, iclass 32, count 0 2006.285.15:57:50.60#ibcon#read 5, iclass 32, count 0 2006.285.15:57:50.60#ibcon#about to read 6, iclass 32, count 0 2006.285.15:57:50.60#ibcon#read 6, iclass 32, count 0 2006.285.15:57:50.60#ibcon#end of sib2, iclass 32, count 0 2006.285.15:57:50.60#ibcon#*mode == 0, iclass 32, count 0 2006.285.15:57:50.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.15:57:50.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.15:57:50.60#ibcon#*before write, iclass 32, count 0 2006.285.15:57:50.60#ibcon#enter sib2, iclass 32, count 0 2006.285.15:57:50.61#ibcon#flushed, iclass 32, count 0 2006.285.15:57:50.61#ibcon#about to write, iclass 32, count 0 2006.285.15:57:50.61#ibcon#wrote, iclass 32, count 0 2006.285.15:57:50.61#ibcon#about to read 3, iclass 32, count 0 2006.285.15:57:50.64#ibcon#read 3, iclass 32, count 0 2006.285.15:57:50.64#ibcon#about to read 4, iclass 32, count 0 2006.285.15:57:50.64#ibcon#read 4, iclass 32, count 0 2006.285.15:57:50.64#ibcon#about to read 5, iclass 32, count 0 2006.285.15:57:50.64#ibcon#read 5, iclass 32, count 0 2006.285.15:57:50.64#ibcon#about to read 6, iclass 32, count 0 2006.285.15:57:50.64#ibcon#read 6, iclass 32, count 0 2006.285.15:57:50.64#ibcon#end of sib2, iclass 32, count 0 2006.285.15:57:50.64#ibcon#*after write, iclass 32, count 0 2006.285.15:57:50.64#ibcon#*before return 0, iclass 32, count 0 2006.285.15:57:50.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:57:50.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:57:50.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.15:57:50.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.15:57:50.65$vck44/va=2,6 2006.285.15:57:50.65#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.15:57:50.65#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.15:57:50.65#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:50.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:57:50.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:57:50.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:57:50.69#ibcon#enter wrdev, iclass 34, count 2 2006.285.15:57:50.69#ibcon#first serial, iclass 34, count 2 2006.285.15:57:50.69#ibcon#enter sib2, iclass 34, count 2 2006.285.15:57:50.69#ibcon#flushed, iclass 34, count 2 2006.285.15:57:50.69#ibcon#about to write, iclass 34, count 2 2006.285.15:57:50.69#ibcon#wrote, iclass 34, count 2 2006.285.15:57:50.69#ibcon#about to read 3, iclass 34, count 2 2006.285.15:57:50.71#ibcon#read 3, iclass 34, count 2 2006.285.15:57:50.71#ibcon#about to read 4, iclass 34, count 2 2006.285.15:57:50.71#ibcon#read 4, iclass 34, count 2 2006.285.15:57:50.71#ibcon#about to read 5, iclass 34, count 2 2006.285.15:57:50.71#ibcon#read 5, iclass 34, count 2 2006.285.15:57:50.71#ibcon#about to read 6, iclass 34, count 2 2006.285.15:57:50.71#ibcon#read 6, iclass 34, count 2 2006.285.15:57:50.71#ibcon#end of sib2, iclass 34, count 2 2006.285.15:57:50.71#ibcon#*mode == 0, iclass 34, count 2 2006.285.15:57:50.71#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.15:57:50.71#ibcon#[25=AT02-06\r\n] 2006.285.15:57:50.71#ibcon#*before write, iclass 34, count 2 2006.285.15:57:50.71#ibcon#enter sib2, iclass 34, count 2 2006.285.15:57:50.71#ibcon#flushed, iclass 34, count 2 2006.285.15:57:50.71#ibcon#about to write, iclass 34, count 2 2006.285.15:57:50.72#ibcon#wrote, iclass 34, count 2 2006.285.15:57:50.72#ibcon#about to read 3, iclass 34, count 2 2006.285.15:57:50.74#ibcon#read 3, iclass 34, count 2 2006.285.15:57:50.74#ibcon#about to read 4, iclass 34, count 2 2006.285.15:57:50.74#ibcon#read 4, iclass 34, count 2 2006.285.15:57:50.74#ibcon#about to read 5, iclass 34, count 2 2006.285.15:57:50.74#ibcon#read 5, iclass 34, count 2 2006.285.15:57:50.74#ibcon#about to read 6, iclass 34, count 2 2006.285.15:57:50.74#ibcon#read 6, iclass 34, count 2 2006.285.15:57:50.74#ibcon#end of sib2, iclass 34, count 2 2006.285.15:57:50.74#ibcon#*after write, iclass 34, count 2 2006.285.15:57:50.74#ibcon#*before return 0, iclass 34, count 2 2006.285.15:57:50.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:57:50.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:57:50.74#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.15:57:50.75#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:50.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:57:50.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:57:50.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:57:50.85#ibcon#enter wrdev, iclass 34, count 0 2006.285.15:57:50.85#ibcon#first serial, iclass 34, count 0 2006.285.15:57:50.85#ibcon#enter sib2, iclass 34, count 0 2006.285.15:57:50.85#ibcon#flushed, iclass 34, count 0 2006.285.15:57:50.85#ibcon#about to write, iclass 34, count 0 2006.285.15:57:50.85#ibcon#wrote, iclass 34, count 0 2006.285.15:57:50.85#ibcon#about to read 3, iclass 34, count 0 2006.285.15:57:50.87#ibcon#read 3, iclass 34, count 0 2006.285.15:57:50.88#ibcon#about to read 4, iclass 34, count 0 2006.285.15:57:50.88#ibcon#read 4, iclass 34, count 0 2006.285.15:57:50.88#ibcon#about to read 5, iclass 34, count 0 2006.285.15:57:50.88#ibcon#read 5, iclass 34, count 0 2006.285.15:57:50.88#ibcon#about to read 6, iclass 34, count 0 2006.285.15:57:50.88#ibcon#read 6, iclass 34, count 0 2006.285.15:57:50.88#ibcon#end of sib2, iclass 34, count 0 2006.285.15:57:50.88#ibcon#*mode == 0, iclass 34, count 0 2006.285.15:57:50.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.15:57:50.88#ibcon#[25=USB\r\n] 2006.285.15:57:50.88#ibcon#*before write, iclass 34, count 0 2006.285.15:57:50.88#ibcon#enter sib2, iclass 34, count 0 2006.285.15:57:50.88#ibcon#flushed, iclass 34, count 0 2006.285.15:57:50.88#ibcon#about to write, iclass 34, count 0 2006.285.15:57:50.88#ibcon#wrote, iclass 34, count 0 2006.285.15:57:50.88#ibcon#about to read 3, iclass 34, count 0 2006.285.15:57:50.90#ibcon#read 3, iclass 34, count 0 2006.285.15:57:50.90#ibcon#about to read 4, iclass 34, count 0 2006.285.15:57:50.90#ibcon#read 4, iclass 34, count 0 2006.285.15:57:50.90#ibcon#about to read 5, iclass 34, count 0 2006.285.15:57:50.90#ibcon#read 5, iclass 34, count 0 2006.285.15:57:50.90#ibcon#about to read 6, iclass 34, count 0 2006.285.15:57:50.90#ibcon#read 6, iclass 34, count 0 2006.285.15:57:50.90#ibcon#end of sib2, iclass 34, count 0 2006.285.15:57:50.90#ibcon#*after write, iclass 34, count 0 2006.285.15:57:50.90#ibcon#*before return 0, iclass 34, count 0 2006.285.15:57:50.91#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:57:50.91#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:57:50.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.15:57:50.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.15:57:50.91$vck44/valo=3,564.99 2006.285.15:57:50.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.15:57:50.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.15:57:50.91#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:50.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:57:50.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:57:50.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:57:50.91#ibcon#enter wrdev, iclass 36, count 0 2006.285.15:57:50.91#ibcon#first serial, iclass 36, count 0 2006.285.15:57:50.91#ibcon#enter sib2, iclass 36, count 0 2006.285.15:57:50.91#ibcon#flushed, iclass 36, count 0 2006.285.15:57:50.91#ibcon#about to write, iclass 36, count 0 2006.285.15:57:50.91#ibcon#wrote, iclass 36, count 0 2006.285.15:57:50.91#ibcon#about to read 3, iclass 36, count 0 2006.285.15:57:50.92#ibcon#read 3, iclass 36, count 0 2006.285.15:57:50.92#ibcon#about to read 4, iclass 36, count 0 2006.285.15:57:50.92#ibcon#read 4, iclass 36, count 0 2006.285.15:57:50.92#ibcon#about to read 5, iclass 36, count 0 2006.285.15:57:50.92#ibcon#read 5, iclass 36, count 0 2006.285.15:57:50.92#ibcon#about to read 6, iclass 36, count 0 2006.285.15:57:50.92#ibcon#read 6, iclass 36, count 0 2006.285.15:57:50.92#ibcon#end of sib2, iclass 36, count 0 2006.285.15:57:50.92#ibcon#*mode == 0, iclass 36, count 0 2006.285.15:57:50.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.15:57:50.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.15:57:50.93#ibcon#*before write, iclass 36, count 0 2006.285.15:57:50.93#ibcon#enter sib2, iclass 36, count 0 2006.285.15:57:50.93#ibcon#flushed, iclass 36, count 0 2006.285.15:57:50.93#ibcon#about to write, iclass 36, count 0 2006.285.15:57:50.93#ibcon#wrote, iclass 36, count 0 2006.285.15:57:50.93#ibcon#about to read 3, iclass 36, count 0 2006.285.15:57:50.96#ibcon#read 3, iclass 36, count 0 2006.285.15:57:50.96#ibcon#about to read 4, iclass 36, count 0 2006.285.15:57:50.96#ibcon#read 4, iclass 36, count 0 2006.285.15:57:50.96#ibcon#about to read 5, iclass 36, count 0 2006.285.15:57:50.96#ibcon#read 5, iclass 36, count 0 2006.285.15:57:50.96#ibcon#about to read 6, iclass 36, count 0 2006.285.15:57:50.96#ibcon#read 6, iclass 36, count 0 2006.285.15:57:50.96#ibcon#end of sib2, iclass 36, count 0 2006.285.15:57:50.96#ibcon#*after write, iclass 36, count 0 2006.285.15:57:50.96#ibcon#*before return 0, iclass 36, count 0 2006.285.15:57:50.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:57:50.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:57:50.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.15:57:50.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.15:57:50.97$vck44/va=3,7 2006.285.15:57:51.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.15:57:51.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.15:57:51.50#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:51.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:57:51.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:57:51.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:57:51.50#ibcon#enter wrdev, iclass 38, count 2 2006.285.15:57:51.50#ibcon#first serial, iclass 38, count 2 2006.285.15:57:51.50#ibcon#enter sib2, iclass 38, count 2 2006.285.15:57:51.50#ibcon#flushed, iclass 38, count 2 2006.285.15:57:51.50#ibcon#about to write, iclass 38, count 2 2006.285.15:57:51.50#ibcon#wrote, iclass 38, count 2 2006.285.15:57:51.50#ibcon#about to read 3, iclass 38, count 2 2006.285.15:57:51.51#ibcon#read 3, iclass 38, count 2 2006.285.15:57:51.51#ibcon#about to read 4, iclass 38, count 2 2006.285.15:57:51.51#ibcon#read 4, iclass 38, count 2 2006.285.15:57:51.51#ibcon#about to read 5, iclass 38, count 2 2006.285.15:57:51.51#ibcon#read 5, iclass 38, count 2 2006.285.15:57:51.51#ibcon#about to read 6, iclass 38, count 2 2006.285.15:57:51.51#ibcon#read 6, iclass 38, count 2 2006.285.15:57:51.51#ibcon#end of sib2, iclass 38, count 2 2006.285.15:57:51.51#ibcon#*mode == 0, iclass 38, count 2 2006.285.15:57:51.51#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.15:57:51.52#ibcon#[25=AT03-07\r\n] 2006.285.15:57:51.52#ibcon#*before write, iclass 38, count 2 2006.285.15:57:51.52#ibcon#enter sib2, iclass 38, count 2 2006.285.15:57:51.52#ibcon#flushed, iclass 38, count 2 2006.285.15:57:51.52#ibcon#about to write, iclass 38, count 2 2006.285.15:57:51.52#ibcon#wrote, iclass 38, count 2 2006.285.15:57:51.52#ibcon#about to read 3, iclass 38, count 2 2006.285.15:57:51.54#ibcon#read 3, iclass 38, count 2 2006.285.15:57:51.54#ibcon#about to read 4, iclass 38, count 2 2006.285.15:57:51.54#ibcon#read 4, iclass 38, count 2 2006.285.15:57:51.54#ibcon#about to read 5, iclass 38, count 2 2006.285.15:57:51.54#ibcon#read 5, iclass 38, count 2 2006.285.15:57:51.54#ibcon#about to read 6, iclass 38, count 2 2006.285.15:57:51.54#ibcon#read 6, iclass 38, count 2 2006.285.15:57:51.54#ibcon#end of sib2, iclass 38, count 2 2006.285.15:57:51.54#ibcon#*after write, iclass 38, count 2 2006.285.15:57:51.54#ibcon#*before return 0, iclass 38, count 2 2006.285.15:57:51.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:57:51.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:57:51.55#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.15:57:51.55#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:51.55#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:57:51.66#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:57:51.66#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:57:51.66#ibcon#enter wrdev, iclass 38, count 0 2006.285.15:57:51.66#ibcon#first serial, iclass 38, count 0 2006.285.15:57:51.66#ibcon#enter sib2, iclass 38, count 0 2006.285.15:57:51.66#ibcon#flushed, iclass 38, count 0 2006.285.15:57:51.66#ibcon#about to write, iclass 38, count 0 2006.285.15:57:51.66#ibcon#wrote, iclass 38, count 0 2006.285.15:57:51.66#ibcon#about to read 3, iclass 38, count 0 2006.285.15:57:51.68#ibcon#read 3, iclass 38, count 0 2006.285.15:57:51.68#ibcon#about to read 4, iclass 38, count 0 2006.285.15:57:51.68#ibcon#read 4, iclass 38, count 0 2006.285.15:57:51.68#ibcon#about to read 5, iclass 38, count 0 2006.285.15:57:51.68#ibcon#read 5, iclass 38, count 0 2006.285.15:57:51.68#ibcon#about to read 6, iclass 38, count 0 2006.285.15:57:51.68#ibcon#read 6, iclass 38, count 0 2006.285.15:57:51.68#ibcon#end of sib2, iclass 38, count 0 2006.285.15:57:51.68#ibcon#*mode == 0, iclass 38, count 0 2006.285.15:57:51.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.15:57:51.68#ibcon#[25=USB\r\n] 2006.285.15:57:51.68#ibcon#*before write, iclass 38, count 0 2006.285.15:57:51.69#ibcon#enter sib2, iclass 38, count 0 2006.285.15:57:51.69#ibcon#flushed, iclass 38, count 0 2006.285.15:57:51.69#ibcon#about to write, iclass 38, count 0 2006.285.15:57:51.69#ibcon#wrote, iclass 38, count 0 2006.285.15:57:51.69#ibcon#about to read 3, iclass 38, count 0 2006.285.15:57:51.71#ibcon#read 3, iclass 38, count 0 2006.285.15:57:51.71#ibcon#about to read 4, iclass 38, count 0 2006.285.15:57:51.71#ibcon#read 4, iclass 38, count 0 2006.285.15:57:51.71#ibcon#about to read 5, iclass 38, count 0 2006.285.15:57:51.71#ibcon#read 5, iclass 38, count 0 2006.285.15:57:51.71#ibcon#about to read 6, iclass 38, count 0 2006.285.15:57:51.71#ibcon#read 6, iclass 38, count 0 2006.285.15:57:51.71#ibcon#end of sib2, iclass 38, count 0 2006.285.15:57:51.71#ibcon#*after write, iclass 38, count 0 2006.285.15:57:51.71#ibcon#*before return 0, iclass 38, count 0 2006.285.15:57:51.71#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:57:51.72#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:57:51.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.15:57:51.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.15:57:51.72$vck44/valo=4,624.99 2006.285.15:57:51.72#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.15:57:51.72#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.15:57:51.72#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:51.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:57:51.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:57:51.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:57:51.72#ibcon#enter wrdev, iclass 40, count 0 2006.285.15:57:51.72#ibcon#first serial, iclass 40, count 0 2006.285.15:57:51.72#ibcon#enter sib2, iclass 40, count 0 2006.285.15:57:51.72#ibcon#flushed, iclass 40, count 0 2006.285.15:57:51.72#ibcon#about to write, iclass 40, count 0 2006.285.15:57:51.72#ibcon#wrote, iclass 40, count 0 2006.285.15:57:51.72#ibcon#about to read 3, iclass 40, count 0 2006.285.15:57:51.73#ibcon#read 3, iclass 40, count 0 2006.285.15:57:51.73#ibcon#about to read 4, iclass 40, count 0 2006.285.15:57:51.73#ibcon#read 4, iclass 40, count 0 2006.285.15:57:51.73#ibcon#about to read 5, iclass 40, count 0 2006.285.15:57:51.73#ibcon#read 5, iclass 40, count 0 2006.285.15:57:51.73#ibcon#about to read 6, iclass 40, count 0 2006.285.15:57:51.73#ibcon#read 6, iclass 40, count 0 2006.285.15:57:51.73#ibcon#end of sib2, iclass 40, count 0 2006.285.15:57:51.73#ibcon#*mode == 0, iclass 40, count 0 2006.285.15:57:51.73#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.15:57:51.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.15:57:51.74#ibcon#*before write, iclass 40, count 0 2006.285.15:57:51.74#ibcon#enter sib2, iclass 40, count 0 2006.285.15:57:51.74#ibcon#flushed, iclass 40, count 0 2006.285.15:57:51.74#ibcon#about to write, iclass 40, count 0 2006.285.15:57:51.74#ibcon#wrote, iclass 40, count 0 2006.285.15:57:51.74#ibcon#about to read 3, iclass 40, count 0 2006.285.15:57:51.77#ibcon#read 3, iclass 40, count 0 2006.285.15:57:51.77#ibcon#about to read 4, iclass 40, count 0 2006.285.15:57:51.77#ibcon#read 4, iclass 40, count 0 2006.285.15:57:51.77#ibcon#about to read 5, iclass 40, count 0 2006.285.15:57:51.77#ibcon#read 5, iclass 40, count 0 2006.285.15:57:51.77#ibcon#about to read 6, iclass 40, count 0 2006.285.15:57:51.77#ibcon#read 6, iclass 40, count 0 2006.285.15:57:51.77#ibcon#end of sib2, iclass 40, count 0 2006.285.15:57:51.77#ibcon#*after write, iclass 40, count 0 2006.285.15:57:51.77#ibcon#*before return 0, iclass 40, count 0 2006.285.15:57:51.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:57:51.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:57:51.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.15:57:51.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.15:57:51.78$vck44/va=4,6 2006.285.15:57:51.94#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.15:57:51.94#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.15:57:51.94#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:51.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:57:51.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:57:51.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:57:51.94#ibcon#enter wrdev, iclass 4, count 2 2006.285.15:57:51.94#ibcon#first serial, iclass 4, count 2 2006.285.15:57:51.94#ibcon#enter sib2, iclass 4, count 2 2006.285.15:57:51.94#ibcon#flushed, iclass 4, count 2 2006.285.15:57:51.94#ibcon#about to write, iclass 4, count 2 2006.285.15:57:51.94#ibcon#wrote, iclass 4, count 2 2006.285.15:57:51.94#ibcon#about to read 3, iclass 4, count 2 2006.285.15:57:51.95#ibcon#read 3, iclass 4, count 2 2006.285.15:57:51.95#ibcon#about to read 4, iclass 4, count 2 2006.285.15:57:51.95#ibcon#read 4, iclass 4, count 2 2006.285.15:57:51.95#ibcon#about to read 5, iclass 4, count 2 2006.285.15:57:51.95#ibcon#read 5, iclass 4, count 2 2006.285.15:57:51.95#ibcon#about to read 6, iclass 4, count 2 2006.285.15:57:51.95#ibcon#read 6, iclass 4, count 2 2006.285.15:57:51.95#ibcon#end of sib2, iclass 4, count 2 2006.285.15:57:51.95#ibcon#*mode == 0, iclass 4, count 2 2006.285.15:57:51.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.15:57:51.95#ibcon#[25=AT04-06\r\n] 2006.285.15:57:51.96#ibcon#*before write, iclass 4, count 2 2006.285.15:57:51.96#ibcon#enter sib2, iclass 4, count 2 2006.285.15:57:51.96#ibcon#flushed, iclass 4, count 2 2006.285.15:57:51.96#ibcon#about to write, iclass 4, count 2 2006.285.15:57:51.96#ibcon#wrote, iclass 4, count 2 2006.285.15:57:51.96#ibcon#about to read 3, iclass 4, count 2 2006.285.15:57:51.98#ibcon#read 3, iclass 4, count 2 2006.285.15:57:51.98#ibcon#about to read 4, iclass 4, count 2 2006.285.15:57:51.98#ibcon#read 4, iclass 4, count 2 2006.285.15:57:51.98#ibcon#about to read 5, iclass 4, count 2 2006.285.15:57:51.98#ibcon#read 5, iclass 4, count 2 2006.285.15:57:51.98#ibcon#about to read 6, iclass 4, count 2 2006.285.15:57:51.98#ibcon#read 6, iclass 4, count 2 2006.285.15:57:51.98#ibcon#end of sib2, iclass 4, count 2 2006.285.15:57:51.98#ibcon#*after write, iclass 4, count 2 2006.285.15:57:51.98#ibcon#*before return 0, iclass 4, count 2 2006.285.15:57:51.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:57:51.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:57:51.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.15:57:51.99#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:51.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:57:52.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:57:52.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:57:52.10#ibcon#enter wrdev, iclass 4, count 0 2006.285.15:57:52.10#ibcon#first serial, iclass 4, count 0 2006.285.15:57:52.10#ibcon#enter sib2, iclass 4, count 0 2006.285.15:57:52.10#ibcon#flushed, iclass 4, count 0 2006.285.15:57:52.10#ibcon#about to write, iclass 4, count 0 2006.285.15:57:52.10#ibcon#wrote, iclass 4, count 0 2006.285.15:57:52.10#ibcon#about to read 3, iclass 4, count 0 2006.285.15:57:52.12#ibcon#read 3, iclass 4, count 0 2006.285.15:57:52.12#ibcon#about to read 4, iclass 4, count 0 2006.285.15:57:52.12#ibcon#read 4, iclass 4, count 0 2006.285.15:57:52.12#ibcon#about to read 5, iclass 4, count 0 2006.285.15:57:52.12#ibcon#read 5, iclass 4, count 0 2006.285.15:57:52.12#ibcon#about to read 6, iclass 4, count 0 2006.285.15:57:52.12#ibcon#read 6, iclass 4, count 0 2006.285.15:57:52.12#ibcon#end of sib2, iclass 4, count 0 2006.285.15:57:52.12#ibcon#*mode == 0, iclass 4, count 0 2006.285.15:57:52.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.15:57:52.12#ibcon#[25=USB\r\n] 2006.285.15:57:52.12#ibcon#*before write, iclass 4, count 0 2006.285.15:57:52.13#ibcon#enter sib2, iclass 4, count 0 2006.285.15:57:52.13#ibcon#flushed, iclass 4, count 0 2006.285.15:57:52.13#ibcon#about to write, iclass 4, count 0 2006.285.15:57:52.13#ibcon#wrote, iclass 4, count 0 2006.285.15:57:52.13#ibcon#about to read 3, iclass 4, count 0 2006.285.15:57:52.15#ibcon#read 3, iclass 4, count 0 2006.285.15:57:52.15#ibcon#about to read 4, iclass 4, count 0 2006.285.15:57:52.15#ibcon#read 4, iclass 4, count 0 2006.285.15:57:52.15#ibcon#about to read 5, iclass 4, count 0 2006.285.15:57:52.15#ibcon#read 5, iclass 4, count 0 2006.285.15:57:52.15#ibcon#about to read 6, iclass 4, count 0 2006.285.15:57:52.15#ibcon#read 6, iclass 4, count 0 2006.285.15:57:52.15#ibcon#end of sib2, iclass 4, count 0 2006.285.15:57:52.15#ibcon#*after write, iclass 4, count 0 2006.285.15:57:52.15#ibcon#*before return 0, iclass 4, count 0 2006.285.15:57:52.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:57:52.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:57:52.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.15:57:52.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.15:57:52.16$vck44/valo=5,734.99 2006.285.15:57:52.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.15:57:52.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.15:57:52.16#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:52.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:57:52.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:57:52.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:57:52.16#ibcon#enter wrdev, iclass 6, count 0 2006.285.15:57:52.16#ibcon#first serial, iclass 6, count 0 2006.285.15:57:52.16#ibcon#enter sib2, iclass 6, count 0 2006.285.15:57:52.16#ibcon#flushed, iclass 6, count 0 2006.285.15:57:52.16#ibcon#about to write, iclass 6, count 0 2006.285.15:57:52.16#ibcon#wrote, iclass 6, count 0 2006.285.15:57:52.16#ibcon#about to read 3, iclass 6, count 0 2006.285.15:57:52.17#ibcon#read 3, iclass 6, count 0 2006.285.15:57:52.17#ibcon#about to read 4, iclass 6, count 0 2006.285.15:57:52.17#ibcon#read 4, iclass 6, count 0 2006.285.15:57:52.17#ibcon#about to read 5, iclass 6, count 0 2006.285.15:57:52.17#ibcon#read 5, iclass 6, count 0 2006.285.15:57:52.17#ibcon#about to read 6, iclass 6, count 0 2006.285.15:57:52.17#ibcon#read 6, iclass 6, count 0 2006.285.15:57:52.17#ibcon#end of sib2, iclass 6, count 0 2006.285.15:57:52.17#ibcon#*mode == 0, iclass 6, count 0 2006.285.15:57:52.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.15:57:52.17#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.15:57:52.17#ibcon#*before write, iclass 6, count 0 2006.285.15:57:52.18#ibcon#enter sib2, iclass 6, count 0 2006.285.15:57:52.18#ibcon#flushed, iclass 6, count 0 2006.285.15:57:52.18#ibcon#about to write, iclass 6, count 0 2006.285.15:57:52.18#ibcon#wrote, iclass 6, count 0 2006.285.15:57:52.18#ibcon#about to read 3, iclass 6, count 0 2006.285.15:57:52.21#ibcon#read 3, iclass 6, count 0 2006.285.15:57:52.21#ibcon#about to read 4, iclass 6, count 0 2006.285.15:57:52.21#ibcon#read 4, iclass 6, count 0 2006.285.15:57:52.21#ibcon#about to read 5, iclass 6, count 0 2006.285.15:57:52.21#ibcon#read 5, iclass 6, count 0 2006.285.15:57:52.21#ibcon#about to read 6, iclass 6, count 0 2006.285.15:57:52.21#ibcon#read 6, iclass 6, count 0 2006.285.15:57:52.21#ibcon#end of sib2, iclass 6, count 0 2006.285.15:57:52.21#ibcon#*after write, iclass 6, count 0 2006.285.15:57:52.21#ibcon#*before return 0, iclass 6, count 0 2006.285.15:57:52.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:57:52.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:57:52.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.15:57:52.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.15:57:52.22$vck44/va=5,3 2006.285.15:57:52.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.15:57:52.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.15:57:52.22#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:52.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:57:52.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:57:52.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:57:52.26#ibcon#enter wrdev, iclass 10, count 2 2006.285.15:57:52.26#ibcon#first serial, iclass 10, count 2 2006.285.15:57:52.26#ibcon#enter sib2, iclass 10, count 2 2006.285.15:57:52.26#ibcon#flushed, iclass 10, count 2 2006.285.15:57:52.26#ibcon#about to write, iclass 10, count 2 2006.285.15:57:52.26#ibcon#wrote, iclass 10, count 2 2006.285.15:57:52.26#ibcon#about to read 3, iclass 10, count 2 2006.285.15:57:52.28#ibcon#read 3, iclass 10, count 2 2006.285.15:57:52.28#ibcon#about to read 4, iclass 10, count 2 2006.285.15:57:52.28#ibcon#read 4, iclass 10, count 2 2006.285.15:57:52.28#ibcon#about to read 5, iclass 10, count 2 2006.285.15:57:52.28#ibcon#read 5, iclass 10, count 2 2006.285.15:57:52.28#ibcon#about to read 6, iclass 10, count 2 2006.285.15:57:52.28#ibcon#read 6, iclass 10, count 2 2006.285.15:57:52.28#ibcon#end of sib2, iclass 10, count 2 2006.285.15:57:52.28#ibcon#*mode == 0, iclass 10, count 2 2006.285.15:57:52.28#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.15:57:52.28#ibcon#[25=AT05-03\r\n] 2006.285.15:57:52.28#ibcon#*before write, iclass 10, count 2 2006.285.15:57:52.28#ibcon#enter sib2, iclass 10, count 2 2006.285.15:57:52.28#ibcon#flushed, iclass 10, count 2 2006.285.15:57:52.28#ibcon#about to write, iclass 10, count 2 2006.285.15:57:52.29#ibcon#wrote, iclass 10, count 2 2006.285.15:57:52.29#ibcon#about to read 3, iclass 10, count 2 2006.285.15:57:52.31#ibcon#read 3, iclass 10, count 2 2006.285.15:57:52.31#ibcon#about to read 4, iclass 10, count 2 2006.285.15:57:52.31#ibcon#read 4, iclass 10, count 2 2006.285.15:57:52.31#ibcon#about to read 5, iclass 10, count 2 2006.285.15:57:52.31#ibcon#read 5, iclass 10, count 2 2006.285.15:57:52.31#ibcon#about to read 6, iclass 10, count 2 2006.285.15:57:52.31#ibcon#read 6, iclass 10, count 2 2006.285.15:57:52.31#ibcon#end of sib2, iclass 10, count 2 2006.285.15:57:52.31#ibcon#*after write, iclass 10, count 2 2006.285.15:57:52.31#ibcon#*before return 0, iclass 10, count 2 2006.285.15:57:52.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:57:52.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:57:52.31#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.15:57:52.32#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:52.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:57:52.42#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:57:52.42#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:57:52.42#ibcon#enter wrdev, iclass 10, count 0 2006.285.15:57:52.42#ibcon#first serial, iclass 10, count 0 2006.285.15:57:52.42#ibcon#enter sib2, iclass 10, count 0 2006.285.15:57:52.42#ibcon#flushed, iclass 10, count 0 2006.285.15:57:52.42#ibcon#about to write, iclass 10, count 0 2006.285.15:57:52.42#ibcon#wrote, iclass 10, count 0 2006.285.15:57:52.42#ibcon#about to read 3, iclass 10, count 0 2006.285.15:57:52.44#ibcon#read 3, iclass 10, count 0 2006.285.15:57:52.44#ibcon#about to read 4, iclass 10, count 0 2006.285.15:57:52.44#ibcon#read 4, iclass 10, count 0 2006.285.15:57:52.44#ibcon#about to read 5, iclass 10, count 0 2006.285.15:57:52.44#ibcon#read 5, iclass 10, count 0 2006.285.15:57:52.44#ibcon#about to read 6, iclass 10, count 0 2006.285.15:57:52.44#ibcon#read 6, iclass 10, count 0 2006.285.15:57:52.44#ibcon#end of sib2, iclass 10, count 0 2006.285.15:57:52.44#ibcon#*mode == 0, iclass 10, count 0 2006.285.15:57:52.44#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.15:57:52.44#ibcon#[25=USB\r\n] 2006.285.15:57:52.44#ibcon#*before write, iclass 10, count 0 2006.285.15:57:52.45#ibcon#enter sib2, iclass 10, count 0 2006.285.15:57:52.45#ibcon#flushed, iclass 10, count 0 2006.285.15:57:52.45#ibcon#about to write, iclass 10, count 0 2006.285.15:57:52.45#ibcon#wrote, iclass 10, count 0 2006.285.15:57:52.45#ibcon#about to read 3, iclass 10, count 0 2006.285.15:57:52.47#ibcon#read 3, iclass 10, count 0 2006.285.15:57:52.47#ibcon#about to read 4, iclass 10, count 0 2006.285.15:57:52.47#ibcon#read 4, iclass 10, count 0 2006.285.15:57:52.47#ibcon#about to read 5, iclass 10, count 0 2006.285.15:57:52.47#ibcon#read 5, iclass 10, count 0 2006.285.15:57:52.47#ibcon#about to read 6, iclass 10, count 0 2006.285.15:57:52.47#ibcon#read 6, iclass 10, count 0 2006.285.15:57:52.47#ibcon#end of sib2, iclass 10, count 0 2006.285.15:57:52.47#ibcon#*after write, iclass 10, count 0 2006.285.15:57:52.47#ibcon#*before return 0, iclass 10, count 0 2006.285.15:57:52.47#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:57:52.48#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:57:52.48#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.15:57:52.48#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.15:57:52.48$vck44/valo=6,814.99 2006.285.15:57:52.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.15:57:52.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.15:57:52.48#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:52.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:57:52.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:57:52.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:57:52.48#ibcon#enter wrdev, iclass 12, count 0 2006.285.15:57:52.48#ibcon#first serial, iclass 12, count 0 2006.285.15:57:52.48#ibcon#enter sib2, iclass 12, count 0 2006.285.15:57:52.48#ibcon#flushed, iclass 12, count 0 2006.285.15:57:52.48#ibcon#about to write, iclass 12, count 0 2006.285.15:57:52.48#ibcon#wrote, iclass 12, count 0 2006.285.15:57:52.48#ibcon#about to read 3, iclass 12, count 0 2006.285.15:57:52.49#ibcon#read 3, iclass 12, count 0 2006.285.15:57:52.49#ibcon#about to read 4, iclass 12, count 0 2006.285.15:57:52.49#ibcon#read 4, iclass 12, count 0 2006.285.15:57:52.49#ibcon#about to read 5, iclass 12, count 0 2006.285.15:57:52.49#ibcon#read 5, iclass 12, count 0 2006.285.15:57:52.49#ibcon#about to read 6, iclass 12, count 0 2006.285.15:57:52.49#ibcon#read 6, iclass 12, count 0 2006.285.15:57:52.49#ibcon#end of sib2, iclass 12, count 0 2006.285.15:57:52.49#ibcon#*mode == 0, iclass 12, count 0 2006.285.15:57:52.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.15:57:52.49#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.15:57:52.49#ibcon#*before write, iclass 12, count 0 2006.285.15:57:52.50#ibcon#enter sib2, iclass 12, count 0 2006.285.15:57:52.50#ibcon#flushed, iclass 12, count 0 2006.285.15:57:52.50#ibcon#about to write, iclass 12, count 0 2006.285.15:57:52.50#ibcon#wrote, iclass 12, count 0 2006.285.15:57:52.50#ibcon#about to read 3, iclass 12, count 0 2006.285.15:57:52.53#ibcon#read 3, iclass 12, count 0 2006.285.15:57:52.53#ibcon#about to read 4, iclass 12, count 0 2006.285.15:57:52.53#ibcon#read 4, iclass 12, count 0 2006.285.15:57:52.53#ibcon#about to read 5, iclass 12, count 0 2006.285.15:57:52.53#ibcon#read 5, iclass 12, count 0 2006.285.15:57:52.53#ibcon#about to read 6, iclass 12, count 0 2006.285.15:57:52.53#ibcon#read 6, iclass 12, count 0 2006.285.15:57:52.53#ibcon#end of sib2, iclass 12, count 0 2006.285.15:57:52.53#ibcon#*after write, iclass 12, count 0 2006.285.15:57:52.53#ibcon#*before return 0, iclass 12, count 0 2006.285.15:57:52.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:57:52.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:57:52.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.15:57:52.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.15:57:52.54$vck44/va=6,4 2006.285.15:57:52.54#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.15:57:52.54#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.15:57:52.54#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:52.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:57:52.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:57:52.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:57:52.58#ibcon#enter wrdev, iclass 14, count 2 2006.285.15:57:52.58#ibcon#first serial, iclass 14, count 2 2006.285.15:57:52.58#ibcon#enter sib2, iclass 14, count 2 2006.285.15:57:52.58#ibcon#flushed, iclass 14, count 2 2006.285.15:57:52.58#ibcon#about to write, iclass 14, count 2 2006.285.15:57:52.58#ibcon#wrote, iclass 14, count 2 2006.285.15:57:52.58#ibcon#about to read 3, iclass 14, count 2 2006.285.15:57:52.60#ibcon#read 3, iclass 14, count 2 2006.285.15:57:52.60#ibcon#about to read 4, iclass 14, count 2 2006.285.15:57:52.60#ibcon#read 4, iclass 14, count 2 2006.285.15:57:52.60#ibcon#about to read 5, iclass 14, count 2 2006.285.15:57:52.60#ibcon#read 5, iclass 14, count 2 2006.285.15:57:52.60#ibcon#about to read 6, iclass 14, count 2 2006.285.15:57:52.60#ibcon#read 6, iclass 14, count 2 2006.285.15:57:52.60#ibcon#end of sib2, iclass 14, count 2 2006.285.15:57:52.60#ibcon#*mode == 0, iclass 14, count 2 2006.285.15:57:52.60#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.15:57:52.60#ibcon#[25=AT06-04\r\n] 2006.285.15:57:52.60#ibcon#*before write, iclass 14, count 2 2006.285.15:57:52.60#ibcon#enter sib2, iclass 14, count 2 2006.285.15:57:52.60#ibcon#flushed, iclass 14, count 2 2006.285.15:57:52.60#ibcon#about to write, iclass 14, count 2 2006.285.15:57:52.61#ibcon#wrote, iclass 14, count 2 2006.285.15:57:52.61#ibcon#about to read 3, iclass 14, count 2 2006.285.15:57:52.63#ibcon#read 3, iclass 14, count 2 2006.285.15:57:52.63#ibcon#about to read 4, iclass 14, count 2 2006.285.15:57:52.63#ibcon#read 4, iclass 14, count 2 2006.285.15:57:52.63#ibcon#about to read 5, iclass 14, count 2 2006.285.15:57:52.63#ibcon#read 5, iclass 14, count 2 2006.285.15:57:52.63#ibcon#about to read 6, iclass 14, count 2 2006.285.15:57:52.63#ibcon#read 6, iclass 14, count 2 2006.285.15:57:52.63#ibcon#end of sib2, iclass 14, count 2 2006.285.15:57:52.63#ibcon#*after write, iclass 14, count 2 2006.285.15:57:52.63#ibcon#*before return 0, iclass 14, count 2 2006.285.15:57:52.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:57:52.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:57:52.63#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.15:57:52.63#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:52.64#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:57:52.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:57:52.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:57:52.74#ibcon#enter wrdev, iclass 14, count 0 2006.285.15:57:52.74#ibcon#first serial, iclass 14, count 0 2006.285.15:57:52.74#ibcon#enter sib2, iclass 14, count 0 2006.285.15:57:52.74#ibcon#flushed, iclass 14, count 0 2006.285.15:57:52.74#ibcon#about to write, iclass 14, count 0 2006.285.15:57:52.74#ibcon#wrote, iclass 14, count 0 2006.285.15:57:52.74#ibcon#about to read 3, iclass 14, count 0 2006.285.15:57:52.76#ibcon#read 3, iclass 14, count 0 2006.285.15:57:52.76#ibcon#about to read 4, iclass 14, count 0 2006.285.15:57:52.76#ibcon#read 4, iclass 14, count 0 2006.285.15:57:52.76#ibcon#about to read 5, iclass 14, count 0 2006.285.15:57:52.76#ibcon#read 5, iclass 14, count 0 2006.285.15:57:52.76#ibcon#about to read 6, iclass 14, count 0 2006.285.15:57:52.76#ibcon#read 6, iclass 14, count 0 2006.285.15:57:52.76#ibcon#end of sib2, iclass 14, count 0 2006.285.15:57:52.76#ibcon#*mode == 0, iclass 14, count 0 2006.285.15:57:52.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.15:57:52.76#ibcon#[25=USB\r\n] 2006.285.15:57:52.76#ibcon#*before write, iclass 14, count 0 2006.285.15:57:52.76#ibcon#enter sib2, iclass 14, count 0 2006.285.15:57:52.76#ibcon#flushed, iclass 14, count 0 2006.285.15:57:52.76#ibcon#about to write, iclass 14, count 0 2006.285.15:57:52.77#ibcon#wrote, iclass 14, count 0 2006.285.15:57:52.77#ibcon#about to read 3, iclass 14, count 0 2006.285.15:57:52.79#ibcon#read 3, iclass 14, count 0 2006.285.15:57:52.79#ibcon#about to read 4, iclass 14, count 0 2006.285.15:57:52.79#ibcon#read 4, iclass 14, count 0 2006.285.15:57:52.79#ibcon#about to read 5, iclass 14, count 0 2006.285.15:57:52.79#ibcon#read 5, iclass 14, count 0 2006.285.15:57:52.79#ibcon#about to read 6, iclass 14, count 0 2006.285.15:57:52.79#ibcon#read 6, iclass 14, count 0 2006.285.15:57:52.79#ibcon#end of sib2, iclass 14, count 0 2006.285.15:57:52.79#ibcon#*after write, iclass 14, count 0 2006.285.15:57:52.79#ibcon#*before return 0, iclass 14, count 0 2006.285.15:57:52.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:57:52.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:57:52.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.15:57:52.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.15:57:52.80$vck44/valo=7,864.99 2006.285.15:57:52.80#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.15:57:52.80#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.15:57:52.80#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:52.80#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:57:52.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:57:52.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:57:52.80#ibcon#enter wrdev, iclass 16, count 0 2006.285.15:57:52.80#ibcon#first serial, iclass 16, count 0 2006.285.15:57:52.80#ibcon#enter sib2, iclass 16, count 0 2006.285.15:57:52.80#ibcon#flushed, iclass 16, count 0 2006.285.15:57:52.80#ibcon#about to write, iclass 16, count 0 2006.285.15:57:52.80#ibcon#wrote, iclass 16, count 0 2006.285.15:57:52.80#ibcon#about to read 3, iclass 16, count 0 2006.285.15:57:52.81#ibcon#read 3, iclass 16, count 0 2006.285.15:57:52.81#ibcon#about to read 4, iclass 16, count 0 2006.285.15:57:52.81#ibcon#read 4, iclass 16, count 0 2006.285.15:57:52.81#ibcon#about to read 5, iclass 16, count 0 2006.285.15:57:52.81#ibcon#read 5, iclass 16, count 0 2006.285.15:57:52.81#ibcon#about to read 6, iclass 16, count 0 2006.285.15:57:52.81#ibcon#read 6, iclass 16, count 0 2006.285.15:57:52.81#ibcon#end of sib2, iclass 16, count 0 2006.285.15:57:52.81#ibcon#*mode == 0, iclass 16, count 0 2006.285.15:57:52.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.15:57:52.81#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.15:57:52.81#ibcon#*before write, iclass 16, count 0 2006.285.15:57:52.81#ibcon#enter sib2, iclass 16, count 0 2006.285.15:57:52.81#ibcon#flushed, iclass 16, count 0 2006.285.15:57:52.82#ibcon#about to write, iclass 16, count 0 2006.285.15:57:52.82#ibcon#wrote, iclass 16, count 0 2006.285.15:57:52.82#ibcon#about to read 3, iclass 16, count 0 2006.285.15:57:52.85#ibcon#read 3, iclass 16, count 0 2006.285.15:57:52.85#ibcon#about to read 4, iclass 16, count 0 2006.285.15:57:52.85#ibcon#read 4, iclass 16, count 0 2006.285.15:57:52.85#ibcon#about to read 5, iclass 16, count 0 2006.285.15:57:52.85#ibcon#read 5, iclass 16, count 0 2006.285.15:57:52.85#ibcon#about to read 6, iclass 16, count 0 2006.285.15:57:52.85#ibcon#read 6, iclass 16, count 0 2006.285.15:57:52.85#ibcon#end of sib2, iclass 16, count 0 2006.285.15:57:52.85#ibcon#*after write, iclass 16, count 0 2006.285.15:57:52.85#ibcon#*before return 0, iclass 16, count 0 2006.285.15:57:52.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:57:52.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.15:57:52.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.15:57:52.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.15:57:52.86$vck44/va=7,4 2006.285.15:57:52.86#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.15:57:52.86#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.15:57:52.86#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:52.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:57:52.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:57:52.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:57:52.90#ibcon#enter wrdev, iclass 18, count 2 2006.285.15:57:52.90#ibcon#first serial, iclass 18, count 2 2006.285.15:57:52.90#ibcon#enter sib2, iclass 18, count 2 2006.285.15:57:52.90#ibcon#flushed, iclass 18, count 2 2006.285.15:57:52.90#ibcon#about to write, iclass 18, count 2 2006.285.15:57:52.90#ibcon#wrote, iclass 18, count 2 2006.285.15:57:52.90#ibcon#about to read 3, iclass 18, count 2 2006.285.15:57:52.92#ibcon#read 3, iclass 18, count 2 2006.285.15:57:52.92#ibcon#about to read 4, iclass 18, count 2 2006.285.15:57:52.92#ibcon#read 4, iclass 18, count 2 2006.285.15:57:52.92#ibcon#about to read 5, iclass 18, count 2 2006.285.15:57:52.92#ibcon#read 5, iclass 18, count 2 2006.285.15:57:52.92#ibcon#about to read 6, iclass 18, count 2 2006.285.15:57:52.92#ibcon#read 6, iclass 18, count 2 2006.285.15:57:52.92#ibcon#end of sib2, iclass 18, count 2 2006.285.15:57:52.92#ibcon#*mode == 0, iclass 18, count 2 2006.285.15:57:52.92#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.15:57:52.92#ibcon#[25=AT07-04\r\n] 2006.285.15:57:52.93#ibcon#*before write, iclass 18, count 2 2006.285.15:57:52.93#ibcon#enter sib2, iclass 18, count 2 2006.285.15:57:52.93#ibcon#flushed, iclass 18, count 2 2006.285.15:57:52.93#ibcon#about to write, iclass 18, count 2 2006.285.15:57:52.93#ibcon#wrote, iclass 18, count 2 2006.285.15:57:52.93#ibcon#about to read 3, iclass 18, count 2 2006.285.15:57:52.95#ibcon#read 3, iclass 18, count 2 2006.285.15:57:52.95#ibcon#about to read 4, iclass 18, count 2 2006.285.15:57:52.95#ibcon#read 4, iclass 18, count 2 2006.285.15:57:52.95#ibcon#about to read 5, iclass 18, count 2 2006.285.15:57:52.95#ibcon#read 5, iclass 18, count 2 2006.285.15:57:52.95#ibcon#about to read 6, iclass 18, count 2 2006.285.15:57:52.95#ibcon#read 6, iclass 18, count 2 2006.285.15:57:52.95#ibcon#end of sib2, iclass 18, count 2 2006.285.15:57:52.95#ibcon#*after write, iclass 18, count 2 2006.285.15:57:52.95#ibcon#*before return 0, iclass 18, count 2 2006.285.15:57:52.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:57:52.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.15:57:52.96#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.15:57:52.96#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:52.96#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:57:53.07#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:57:53.07#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:57:53.07#ibcon#enter wrdev, iclass 18, count 0 2006.285.15:57:53.07#ibcon#first serial, iclass 18, count 0 2006.285.15:57:53.07#ibcon#enter sib2, iclass 18, count 0 2006.285.15:57:53.07#ibcon#flushed, iclass 18, count 0 2006.285.15:57:53.07#ibcon#about to write, iclass 18, count 0 2006.285.15:57:53.07#ibcon#wrote, iclass 18, count 0 2006.285.15:57:53.07#ibcon#about to read 3, iclass 18, count 0 2006.285.15:57:53.09#ibcon#read 3, iclass 18, count 0 2006.285.15:57:53.09#ibcon#about to read 4, iclass 18, count 0 2006.285.15:57:53.09#ibcon#read 4, iclass 18, count 0 2006.285.15:57:53.09#ibcon#about to read 5, iclass 18, count 0 2006.285.15:57:53.09#ibcon#read 5, iclass 18, count 0 2006.285.15:57:53.09#ibcon#about to read 6, iclass 18, count 0 2006.285.15:57:53.09#ibcon#read 6, iclass 18, count 0 2006.285.15:57:53.09#ibcon#end of sib2, iclass 18, count 0 2006.285.15:57:53.09#ibcon#*mode == 0, iclass 18, count 0 2006.285.15:57:53.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.15:57:53.09#ibcon#[25=USB\r\n] 2006.285.15:57:53.09#ibcon#*before write, iclass 18, count 0 2006.285.15:57:53.10#ibcon#enter sib2, iclass 18, count 0 2006.285.15:57:53.10#ibcon#flushed, iclass 18, count 0 2006.285.15:57:53.10#ibcon#about to write, iclass 18, count 0 2006.285.15:57:53.10#ibcon#wrote, iclass 18, count 0 2006.285.15:57:53.10#ibcon#about to read 3, iclass 18, count 0 2006.285.15:57:53.12#ibcon#read 3, iclass 18, count 0 2006.285.15:57:53.12#ibcon#about to read 4, iclass 18, count 0 2006.285.15:57:53.12#ibcon#read 4, iclass 18, count 0 2006.285.15:57:53.12#ibcon#about to read 5, iclass 18, count 0 2006.285.15:57:53.12#ibcon#read 5, iclass 18, count 0 2006.285.15:57:53.12#ibcon#about to read 6, iclass 18, count 0 2006.285.15:57:53.12#ibcon#read 6, iclass 18, count 0 2006.285.15:57:53.12#ibcon#end of sib2, iclass 18, count 0 2006.285.15:57:53.12#ibcon#*after write, iclass 18, count 0 2006.285.15:57:53.12#ibcon#*before return 0, iclass 18, count 0 2006.285.15:57:53.12#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:57:53.12#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.15:57:53.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.15:57:53.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.15:57:53.13$vck44/valo=8,884.99 2006.285.15:57:53.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.15:57:53.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.15:57:53.16#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:53.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.15:57:53.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.15:57:53.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.15:57:53.16#ibcon#enter wrdev, iclass 20, count 0 2006.285.15:57:53.16#ibcon#first serial, iclass 20, count 0 2006.285.15:57:53.16#ibcon#enter sib2, iclass 20, count 0 2006.285.15:57:53.16#ibcon#flushed, iclass 20, count 0 2006.285.15:57:53.16#ibcon#about to write, iclass 20, count 0 2006.285.15:57:53.16#ibcon#wrote, iclass 20, count 0 2006.285.15:57:53.16#ibcon#about to read 3, iclass 20, count 0 2006.285.15:57:53.17#ibcon#read 3, iclass 20, count 0 2006.285.15:57:53.17#ibcon#about to read 4, iclass 20, count 0 2006.285.15:57:53.17#ibcon#read 4, iclass 20, count 0 2006.285.15:57:53.17#ibcon#about to read 5, iclass 20, count 0 2006.285.15:57:53.17#ibcon#read 5, iclass 20, count 0 2006.285.15:57:53.17#ibcon#about to read 6, iclass 20, count 0 2006.285.15:57:53.17#ibcon#read 6, iclass 20, count 0 2006.285.15:57:53.17#ibcon#end of sib2, iclass 20, count 0 2006.285.15:57:53.17#ibcon#*mode == 0, iclass 20, count 0 2006.285.15:57:53.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.15:57:53.17#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.15:57:53.17#ibcon#*before write, iclass 20, count 0 2006.285.15:57:53.18#ibcon#enter sib2, iclass 20, count 0 2006.285.15:57:53.18#ibcon#flushed, iclass 20, count 0 2006.285.15:57:53.18#ibcon#about to write, iclass 20, count 0 2006.285.15:57:53.18#ibcon#wrote, iclass 20, count 0 2006.285.15:57:53.18#ibcon#about to read 3, iclass 20, count 0 2006.285.15:57:53.21#ibcon#read 3, iclass 20, count 0 2006.285.15:57:53.21#ibcon#about to read 4, iclass 20, count 0 2006.285.15:57:53.21#ibcon#read 4, iclass 20, count 0 2006.285.15:57:53.21#ibcon#about to read 5, iclass 20, count 0 2006.285.15:57:53.21#ibcon#read 5, iclass 20, count 0 2006.285.15:57:53.21#ibcon#about to read 6, iclass 20, count 0 2006.285.15:57:53.21#ibcon#read 6, iclass 20, count 0 2006.285.15:57:53.21#ibcon#end of sib2, iclass 20, count 0 2006.285.15:57:53.21#ibcon#*after write, iclass 20, count 0 2006.285.15:57:53.21#ibcon#*before return 0, iclass 20, count 0 2006.285.15:57:53.21#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.15:57:53.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.15:57:53.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.15:57:53.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.15:57:53.22$vck44/va=8,3 2006.285.15:57:53.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.15:57:53.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.15:57:53.22#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:53.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.15:57:53.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.15:57:53.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.15:57:53.23#ibcon#enter wrdev, iclass 22, count 2 2006.285.15:57:53.23#ibcon#first serial, iclass 22, count 2 2006.285.15:57:53.23#ibcon#enter sib2, iclass 22, count 2 2006.285.15:57:53.23#ibcon#flushed, iclass 22, count 2 2006.285.15:57:53.23#ibcon#about to write, iclass 22, count 2 2006.285.15:57:53.23#ibcon#wrote, iclass 22, count 2 2006.285.15:57:53.23#ibcon#about to read 3, iclass 22, count 2 2006.285.15:57:53.25#ibcon#read 3, iclass 22, count 2 2006.285.15:57:53.25#ibcon#about to read 4, iclass 22, count 2 2006.285.15:57:53.25#ibcon#read 4, iclass 22, count 2 2006.285.15:57:53.25#ibcon#about to read 5, iclass 22, count 2 2006.285.15:57:53.25#ibcon#read 5, iclass 22, count 2 2006.285.15:57:53.25#ibcon#about to read 6, iclass 22, count 2 2006.285.15:57:53.25#ibcon#read 6, iclass 22, count 2 2006.285.15:57:53.25#ibcon#end of sib2, iclass 22, count 2 2006.285.15:57:53.25#ibcon#*mode == 0, iclass 22, count 2 2006.285.15:57:53.25#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.15:57:53.25#ibcon#[25=AT08-03\r\n] 2006.285.15:57:53.25#ibcon#*before write, iclass 22, count 2 2006.285.15:57:53.25#ibcon#enter sib2, iclass 22, count 2 2006.285.15:57:53.26#ibcon#flushed, iclass 22, count 2 2006.285.15:57:53.26#ibcon#about to write, iclass 22, count 2 2006.285.15:57:53.26#ibcon#wrote, iclass 22, count 2 2006.285.15:57:53.26#ibcon#about to read 3, iclass 22, count 2 2006.285.15:57:53.28#ibcon#read 3, iclass 22, count 2 2006.285.15:57:53.28#ibcon#about to read 4, iclass 22, count 2 2006.285.15:57:53.28#ibcon#read 4, iclass 22, count 2 2006.285.15:57:53.28#ibcon#about to read 5, iclass 22, count 2 2006.285.15:57:53.28#ibcon#read 5, iclass 22, count 2 2006.285.15:57:53.28#ibcon#about to read 6, iclass 22, count 2 2006.285.15:57:53.28#ibcon#read 6, iclass 22, count 2 2006.285.15:57:53.28#ibcon#end of sib2, iclass 22, count 2 2006.285.15:57:53.28#ibcon#*after write, iclass 22, count 2 2006.285.15:57:53.28#ibcon#*before return 0, iclass 22, count 2 2006.285.15:57:53.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.15:57:53.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.15:57:53.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.15:57:53.29#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:53.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.15:57:53.39#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.15:57:53.39#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.15:57:53.39#ibcon#enter wrdev, iclass 22, count 0 2006.285.15:57:53.39#ibcon#first serial, iclass 22, count 0 2006.285.15:57:53.39#ibcon#enter sib2, iclass 22, count 0 2006.285.15:57:53.39#ibcon#flushed, iclass 22, count 0 2006.285.15:57:53.39#ibcon#about to write, iclass 22, count 0 2006.285.15:57:53.39#ibcon#wrote, iclass 22, count 0 2006.285.15:57:53.39#ibcon#about to read 3, iclass 22, count 0 2006.285.15:57:53.41#ibcon#read 3, iclass 22, count 0 2006.285.15:57:53.41#ibcon#about to read 4, iclass 22, count 0 2006.285.15:57:53.41#ibcon#read 4, iclass 22, count 0 2006.285.15:57:53.41#ibcon#about to read 5, iclass 22, count 0 2006.285.15:57:53.41#ibcon#read 5, iclass 22, count 0 2006.285.15:57:53.41#ibcon#about to read 6, iclass 22, count 0 2006.285.15:57:53.41#ibcon#read 6, iclass 22, count 0 2006.285.15:57:53.41#ibcon#end of sib2, iclass 22, count 0 2006.285.15:57:53.41#ibcon#*mode == 0, iclass 22, count 0 2006.285.15:57:53.41#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.15:57:53.41#ibcon#[25=USB\r\n] 2006.285.15:57:53.41#ibcon#*before write, iclass 22, count 0 2006.285.15:57:53.41#ibcon#enter sib2, iclass 22, count 0 2006.285.15:57:53.42#ibcon#flushed, iclass 22, count 0 2006.285.15:57:53.42#ibcon#about to write, iclass 22, count 0 2006.285.15:57:53.42#ibcon#wrote, iclass 22, count 0 2006.285.15:57:53.42#ibcon#about to read 3, iclass 22, count 0 2006.285.15:57:53.44#ibcon#read 3, iclass 22, count 0 2006.285.15:57:53.44#ibcon#about to read 4, iclass 22, count 0 2006.285.15:57:53.44#ibcon#read 4, iclass 22, count 0 2006.285.15:57:53.44#ibcon#about to read 5, iclass 22, count 0 2006.285.15:57:53.44#ibcon#read 5, iclass 22, count 0 2006.285.15:57:53.44#ibcon#about to read 6, iclass 22, count 0 2006.285.15:57:53.44#ibcon#read 6, iclass 22, count 0 2006.285.15:57:53.44#ibcon#end of sib2, iclass 22, count 0 2006.285.15:57:53.44#ibcon#*after write, iclass 22, count 0 2006.285.15:57:53.44#ibcon#*before return 0, iclass 22, count 0 2006.285.15:57:53.44#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.15:57:53.44#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.15:57:53.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.15:57:53.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.15:57:53.45$vck44/vblo=1,629.99 2006.285.15:57:53.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.15:57:53.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.15:57:53.45#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:53.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:57:53.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:57:53.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:57:53.45#ibcon#enter wrdev, iclass 24, count 0 2006.285.15:57:53.45#ibcon#first serial, iclass 24, count 0 2006.285.15:57:53.45#ibcon#enter sib2, iclass 24, count 0 2006.285.15:57:53.45#ibcon#flushed, iclass 24, count 0 2006.285.15:57:53.45#ibcon#about to write, iclass 24, count 0 2006.285.15:57:53.45#ibcon#wrote, iclass 24, count 0 2006.285.15:57:53.45#ibcon#about to read 3, iclass 24, count 0 2006.285.15:57:53.46#ibcon#read 3, iclass 24, count 0 2006.285.15:57:53.46#ibcon#about to read 4, iclass 24, count 0 2006.285.15:57:53.46#ibcon#read 4, iclass 24, count 0 2006.285.15:57:53.46#ibcon#about to read 5, iclass 24, count 0 2006.285.15:57:53.46#ibcon#read 5, iclass 24, count 0 2006.285.15:57:53.46#ibcon#about to read 6, iclass 24, count 0 2006.285.15:57:53.46#ibcon#read 6, iclass 24, count 0 2006.285.15:57:53.46#ibcon#end of sib2, iclass 24, count 0 2006.285.15:57:53.46#ibcon#*mode == 0, iclass 24, count 0 2006.285.15:57:53.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.15:57:53.46#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.15:57:53.46#ibcon#*before write, iclass 24, count 0 2006.285.15:57:53.46#ibcon#enter sib2, iclass 24, count 0 2006.285.15:57:53.47#ibcon#flushed, iclass 24, count 0 2006.285.15:57:53.47#ibcon#about to write, iclass 24, count 0 2006.285.15:57:53.47#ibcon#wrote, iclass 24, count 0 2006.285.15:57:53.47#ibcon#about to read 3, iclass 24, count 0 2006.285.15:57:53.50#ibcon#read 3, iclass 24, count 0 2006.285.15:57:53.50#ibcon#about to read 4, iclass 24, count 0 2006.285.15:57:53.50#ibcon#read 4, iclass 24, count 0 2006.285.15:57:53.50#ibcon#about to read 5, iclass 24, count 0 2006.285.15:57:53.50#ibcon#read 5, iclass 24, count 0 2006.285.15:57:53.50#ibcon#about to read 6, iclass 24, count 0 2006.285.15:57:53.50#ibcon#read 6, iclass 24, count 0 2006.285.15:57:53.50#ibcon#end of sib2, iclass 24, count 0 2006.285.15:57:53.50#ibcon#*after write, iclass 24, count 0 2006.285.15:57:53.50#ibcon#*before return 0, iclass 24, count 0 2006.285.15:57:53.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:57:53.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:57:53.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.15:57:53.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.15:57:53.51$vck44/vb=1,4 2006.285.15:57:53.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.15:57:53.51#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.15:57:53.51#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:53.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:57:53.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:57:53.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:57:53.51#ibcon#enter wrdev, iclass 26, count 2 2006.285.15:57:53.51#ibcon#first serial, iclass 26, count 2 2006.285.15:57:53.51#ibcon#enter sib2, iclass 26, count 2 2006.285.15:57:53.51#ibcon#flushed, iclass 26, count 2 2006.285.15:57:53.51#ibcon#about to write, iclass 26, count 2 2006.285.15:57:53.51#ibcon#wrote, iclass 26, count 2 2006.285.15:57:53.51#ibcon#about to read 3, iclass 26, count 2 2006.285.15:57:53.52#ibcon#read 3, iclass 26, count 2 2006.285.15:57:53.52#ibcon#about to read 4, iclass 26, count 2 2006.285.15:57:53.52#ibcon#read 4, iclass 26, count 2 2006.285.15:57:53.52#ibcon#about to read 5, iclass 26, count 2 2006.285.15:57:53.52#ibcon#read 5, iclass 26, count 2 2006.285.15:57:53.52#ibcon#about to read 6, iclass 26, count 2 2006.285.15:57:53.52#ibcon#read 6, iclass 26, count 2 2006.285.15:57:53.52#ibcon#end of sib2, iclass 26, count 2 2006.285.15:57:53.52#ibcon#*mode == 0, iclass 26, count 2 2006.285.15:57:53.52#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.15:57:53.52#ibcon#[27=AT01-04\r\n] 2006.285.15:57:53.52#ibcon#*before write, iclass 26, count 2 2006.285.15:57:53.52#ibcon#enter sib2, iclass 26, count 2 2006.285.15:57:53.52#ibcon#flushed, iclass 26, count 2 2006.285.15:57:53.53#ibcon#about to write, iclass 26, count 2 2006.285.15:57:53.53#ibcon#wrote, iclass 26, count 2 2006.285.15:57:53.53#ibcon#about to read 3, iclass 26, count 2 2006.285.15:57:53.55#ibcon#read 3, iclass 26, count 2 2006.285.15:57:53.55#ibcon#about to read 4, iclass 26, count 2 2006.285.15:57:53.55#ibcon#read 4, iclass 26, count 2 2006.285.15:57:53.55#ibcon#about to read 5, iclass 26, count 2 2006.285.15:57:53.55#ibcon#read 5, iclass 26, count 2 2006.285.15:57:53.55#ibcon#about to read 6, iclass 26, count 2 2006.285.15:57:53.55#ibcon#read 6, iclass 26, count 2 2006.285.15:57:53.55#ibcon#end of sib2, iclass 26, count 2 2006.285.15:57:53.55#ibcon#*after write, iclass 26, count 2 2006.285.15:57:53.55#ibcon#*before return 0, iclass 26, count 2 2006.285.15:57:53.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:57:53.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.15:57:53.55#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.15:57:53.56#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:53.56#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:57:53.66#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:57:53.66#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:57:53.66#ibcon#enter wrdev, iclass 26, count 0 2006.285.15:57:53.66#ibcon#first serial, iclass 26, count 0 2006.285.15:57:53.66#ibcon#enter sib2, iclass 26, count 0 2006.285.15:57:53.66#ibcon#flushed, iclass 26, count 0 2006.285.15:57:53.66#ibcon#about to write, iclass 26, count 0 2006.285.15:57:53.66#ibcon#wrote, iclass 26, count 0 2006.285.15:57:53.66#ibcon#about to read 3, iclass 26, count 0 2006.285.15:57:53.68#ibcon#read 3, iclass 26, count 0 2006.285.15:57:53.68#ibcon#about to read 4, iclass 26, count 0 2006.285.15:57:53.68#ibcon#read 4, iclass 26, count 0 2006.285.15:57:53.68#ibcon#about to read 5, iclass 26, count 0 2006.285.15:57:53.68#ibcon#read 5, iclass 26, count 0 2006.285.15:57:53.68#ibcon#about to read 6, iclass 26, count 0 2006.285.15:57:53.68#ibcon#read 6, iclass 26, count 0 2006.285.15:57:53.68#ibcon#end of sib2, iclass 26, count 0 2006.285.15:57:53.68#ibcon#*mode == 0, iclass 26, count 0 2006.285.15:57:53.68#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.15:57:53.68#ibcon#[27=USB\r\n] 2006.285.15:57:53.68#ibcon#*before write, iclass 26, count 0 2006.285.15:57:53.68#ibcon#enter sib2, iclass 26, count 0 2006.285.15:57:53.68#ibcon#flushed, iclass 26, count 0 2006.285.15:57:53.68#ibcon#about to write, iclass 26, count 0 2006.285.15:57:53.69#ibcon#wrote, iclass 26, count 0 2006.285.15:57:53.69#ibcon#about to read 3, iclass 26, count 0 2006.285.15:57:53.71#ibcon#read 3, iclass 26, count 0 2006.285.15:57:53.71#ibcon#about to read 4, iclass 26, count 0 2006.285.15:57:53.71#ibcon#read 4, iclass 26, count 0 2006.285.15:57:53.71#ibcon#about to read 5, iclass 26, count 0 2006.285.15:57:53.71#ibcon#read 5, iclass 26, count 0 2006.285.15:57:53.71#ibcon#about to read 6, iclass 26, count 0 2006.285.15:57:53.71#ibcon#read 6, iclass 26, count 0 2006.285.15:57:53.71#ibcon#end of sib2, iclass 26, count 0 2006.285.15:57:53.71#ibcon#*after write, iclass 26, count 0 2006.285.15:57:53.71#ibcon#*before return 0, iclass 26, count 0 2006.285.15:57:53.71#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:57:53.71#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.15:57:53.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.15:57:53.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.15:57:53.72$vck44/vblo=2,634.99 2006.285.15:57:53.72#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.15:57:53.72#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.15:57:53.72#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:53.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:57:53.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:57:53.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:57:53.72#ibcon#enter wrdev, iclass 28, count 0 2006.285.15:57:53.72#ibcon#first serial, iclass 28, count 0 2006.285.15:57:53.72#ibcon#enter sib2, iclass 28, count 0 2006.285.15:57:53.72#ibcon#flushed, iclass 28, count 0 2006.285.15:57:53.72#ibcon#about to write, iclass 28, count 0 2006.285.15:57:53.72#ibcon#wrote, iclass 28, count 0 2006.285.15:57:53.72#ibcon#about to read 3, iclass 28, count 0 2006.285.15:57:53.73#ibcon#read 3, iclass 28, count 0 2006.285.15:57:53.73#ibcon#about to read 4, iclass 28, count 0 2006.285.15:57:53.73#ibcon#read 4, iclass 28, count 0 2006.285.15:57:53.73#ibcon#about to read 5, iclass 28, count 0 2006.285.15:57:53.73#ibcon#read 5, iclass 28, count 0 2006.285.15:57:53.73#ibcon#about to read 6, iclass 28, count 0 2006.285.15:57:53.73#ibcon#read 6, iclass 28, count 0 2006.285.15:57:53.73#ibcon#end of sib2, iclass 28, count 0 2006.285.15:57:53.73#ibcon#*mode == 0, iclass 28, count 0 2006.285.15:57:53.73#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.15:57:53.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.15:57:53.73#ibcon#*before write, iclass 28, count 0 2006.285.15:57:53.73#ibcon#enter sib2, iclass 28, count 0 2006.285.15:57:53.73#ibcon#flushed, iclass 28, count 0 2006.285.15:57:53.74#ibcon#about to write, iclass 28, count 0 2006.285.15:57:53.74#ibcon#wrote, iclass 28, count 0 2006.285.15:57:53.74#ibcon#about to read 3, iclass 28, count 0 2006.285.15:57:53.77#ibcon#read 3, iclass 28, count 0 2006.285.15:57:53.77#ibcon#about to read 4, iclass 28, count 0 2006.285.15:57:53.77#ibcon#read 4, iclass 28, count 0 2006.285.15:57:53.77#ibcon#about to read 5, iclass 28, count 0 2006.285.15:57:53.77#ibcon#read 5, iclass 28, count 0 2006.285.15:57:53.77#ibcon#about to read 6, iclass 28, count 0 2006.285.15:57:53.77#ibcon#read 6, iclass 28, count 0 2006.285.15:57:53.77#ibcon#end of sib2, iclass 28, count 0 2006.285.15:57:53.77#ibcon#*after write, iclass 28, count 0 2006.285.15:57:53.77#ibcon#*before return 0, iclass 28, count 0 2006.285.15:57:53.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:57:53.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.15:57:53.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.15:57:53.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.15:57:53.78$vck44/vb=2,5 2006.285.15:57:53.78#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.15:57:53.78#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.15:57:53.78#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:53.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:57:53.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:57:53.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:57:53.82#ibcon#enter wrdev, iclass 30, count 2 2006.285.15:57:53.82#ibcon#first serial, iclass 30, count 2 2006.285.15:57:53.82#ibcon#enter sib2, iclass 30, count 2 2006.285.15:57:53.82#ibcon#flushed, iclass 30, count 2 2006.285.15:57:53.82#ibcon#about to write, iclass 30, count 2 2006.285.15:57:53.82#ibcon#wrote, iclass 30, count 2 2006.285.15:57:53.82#ibcon#about to read 3, iclass 30, count 2 2006.285.15:57:53.84#ibcon#read 3, iclass 30, count 2 2006.285.15:57:53.84#ibcon#about to read 4, iclass 30, count 2 2006.285.15:57:53.84#ibcon#read 4, iclass 30, count 2 2006.285.15:57:53.84#ibcon#about to read 5, iclass 30, count 2 2006.285.15:57:53.84#ibcon#read 5, iclass 30, count 2 2006.285.15:57:53.84#ibcon#about to read 6, iclass 30, count 2 2006.285.15:57:53.84#ibcon#read 6, iclass 30, count 2 2006.285.15:57:53.84#ibcon#end of sib2, iclass 30, count 2 2006.285.15:57:53.84#ibcon#*mode == 0, iclass 30, count 2 2006.285.15:57:53.84#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.15:57:53.84#ibcon#[27=AT02-05\r\n] 2006.285.15:57:53.84#ibcon#*before write, iclass 30, count 2 2006.285.15:57:53.84#ibcon#enter sib2, iclass 30, count 2 2006.285.15:57:53.84#ibcon#flushed, iclass 30, count 2 2006.285.15:57:53.84#ibcon#about to write, iclass 30, count 2 2006.285.15:57:53.85#ibcon#wrote, iclass 30, count 2 2006.285.15:57:53.85#ibcon#about to read 3, iclass 30, count 2 2006.285.15:57:53.87#ibcon#read 3, iclass 30, count 2 2006.285.15:57:53.87#ibcon#about to read 4, iclass 30, count 2 2006.285.15:57:53.87#ibcon#read 4, iclass 30, count 2 2006.285.15:57:53.87#ibcon#about to read 5, iclass 30, count 2 2006.285.15:57:53.87#ibcon#read 5, iclass 30, count 2 2006.285.15:57:53.87#ibcon#about to read 6, iclass 30, count 2 2006.285.15:57:53.87#ibcon#read 6, iclass 30, count 2 2006.285.15:57:53.87#ibcon#end of sib2, iclass 30, count 2 2006.285.15:57:53.87#ibcon#*after write, iclass 30, count 2 2006.285.15:57:53.87#ibcon#*before return 0, iclass 30, count 2 2006.285.15:57:53.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:57:53.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.15:57:53.87#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.15:57:53.87#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:53.88#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:57:53.98#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:57:53.98#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:57:53.98#ibcon#enter wrdev, iclass 30, count 0 2006.285.15:57:53.98#ibcon#first serial, iclass 30, count 0 2006.285.15:57:53.98#ibcon#enter sib2, iclass 30, count 0 2006.285.15:57:53.98#ibcon#flushed, iclass 30, count 0 2006.285.15:57:53.98#ibcon#about to write, iclass 30, count 0 2006.285.15:57:53.98#ibcon#wrote, iclass 30, count 0 2006.285.15:57:53.98#ibcon#about to read 3, iclass 30, count 0 2006.285.15:57:54.00#ibcon#read 3, iclass 30, count 0 2006.285.15:57:54.00#ibcon#about to read 4, iclass 30, count 0 2006.285.15:57:54.00#ibcon#read 4, iclass 30, count 0 2006.285.15:57:54.00#ibcon#about to read 5, iclass 30, count 0 2006.285.15:57:54.00#ibcon#read 5, iclass 30, count 0 2006.285.15:57:54.00#ibcon#about to read 6, iclass 30, count 0 2006.285.15:57:54.00#ibcon#read 6, iclass 30, count 0 2006.285.15:57:54.00#ibcon#end of sib2, iclass 30, count 0 2006.285.15:57:54.00#ibcon#*mode == 0, iclass 30, count 0 2006.285.15:57:54.00#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.15:57:54.00#ibcon#[27=USB\r\n] 2006.285.15:57:54.00#ibcon#*before write, iclass 30, count 0 2006.285.15:57:54.00#ibcon#enter sib2, iclass 30, count 0 2006.285.15:57:54.00#ibcon#flushed, iclass 30, count 0 2006.285.15:57:54.00#ibcon#about to write, iclass 30, count 0 2006.285.15:57:54.01#ibcon#wrote, iclass 30, count 0 2006.285.15:57:54.01#ibcon#about to read 3, iclass 30, count 0 2006.285.15:57:54.03#ibcon#read 3, iclass 30, count 0 2006.285.15:57:54.03#ibcon#about to read 4, iclass 30, count 0 2006.285.15:57:54.03#ibcon#read 4, iclass 30, count 0 2006.285.15:57:54.03#ibcon#about to read 5, iclass 30, count 0 2006.285.15:57:54.03#ibcon#read 5, iclass 30, count 0 2006.285.15:57:54.03#ibcon#about to read 6, iclass 30, count 0 2006.285.15:57:54.03#ibcon#read 6, iclass 30, count 0 2006.285.15:57:54.03#ibcon#end of sib2, iclass 30, count 0 2006.285.15:57:54.03#ibcon#*after write, iclass 30, count 0 2006.285.15:57:54.03#ibcon#*before return 0, iclass 30, count 0 2006.285.15:57:54.03#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:57:54.04#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.15:57:54.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.15:57:54.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.15:57:54.04$vck44/vblo=3,649.99 2006.285.15:57:54.04#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.15:57:54.04#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.15:57:54.04#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:54.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:57:54.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:57:54.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:57:54.04#ibcon#enter wrdev, iclass 32, count 0 2006.285.15:57:54.04#ibcon#first serial, iclass 32, count 0 2006.285.15:57:54.04#ibcon#enter sib2, iclass 32, count 0 2006.285.15:57:54.04#ibcon#flushed, iclass 32, count 0 2006.285.15:57:54.04#ibcon#about to write, iclass 32, count 0 2006.285.15:57:54.04#ibcon#wrote, iclass 32, count 0 2006.285.15:57:54.04#ibcon#about to read 3, iclass 32, count 0 2006.285.15:57:54.05#ibcon#read 3, iclass 32, count 0 2006.285.15:57:54.16#ibcon#about to read 4, iclass 32, count 0 2006.285.15:57:54.16#ibcon#read 4, iclass 32, count 0 2006.285.15:57:54.16#ibcon#about to read 5, iclass 32, count 0 2006.285.15:57:54.16#ibcon#read 5, iclass 32, count 0 2006.285.15:57:54.16#ibcon#about to read 6, iclass 32, count 0 2006.285.15:57:54.16#ibcon#read 6, iclass 32, count 0 2006.285.15:57:54.16#ibcon#end of sib2, iclass 32, count 0 2006.285.15:57:54.16#ibcon#*mode == 0, iclass 32, count 0 2006.285.15:57:54.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.15:57:54.16#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.15:57:54.16#ibcon#*before write, iclass 32, count 0 2006.285.15:57:54.16#ibcon#enter sib2, iclass 32, count 0 2006.285.15:57:54.16#ibcon#flushed, iclass 32, count 0 2006.285.15:57:54.16#ibcon#about to write, iclass 32, count 0 2006.285.15:57:54.16#ibcon#wrote, iclass 32, count 0 2006.285.15:57:54.16#ibcon#about to read 3, iclass 32, count 0 2006.285.15:57:54.19#ibcon#read 3, iclass 32, count 0 2006.285.15:57:54.19#ibcon#about to read 4, iclass 32, count 0 2006.285.15:57:54.19#ibcon#read 4, iclass 32, count 0 2006.285.15:57:54.19#ibcon#about to read 5, iclass 32, count 0 2006.285.15:57:54.19#ibcon#read 5, iclass 32, count 0 2006.285.15:57:54.19#ibcon#about to read 6, iclass 32, count 0 2006.285.15:57:54.19#ibcon#read 6, iclass 32, count 0 2006.285.15:57:54.19#ibcon#end of sib2, iclass 32, count 0 2006.285.15:57:54.19#ibcon#*after write, iclass 32, count 0 2006.285.15:57:54.19#ibcon#*before return 0, iclass 32, count 0 2006.285.15:57:54.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:57:54.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.15:57:54.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.15:57:54.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.15:57:54.20$vck44/vb=3,4 2006.285.15:57:54.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.15:57:54.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.15:57:54.20#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:54.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:57:54.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:57:54.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:57:54.20#ibcon#enter wrdev, iclass 34, count 2 2006.285.15:57:54.20#ibcon#first serial, iclass 34, count 2 2006.285.15:57:54.20#ibcon#enter sib2, iclass 34, count 2 2006.285.15:57:54.20#ibcon#flushed, iclass 34, count 2 2006.285.15:57:54.20#ibcon#about to write, iclass 34, count 2 2006.285.15:57:54.20#ibcon#wrote, iclass 34, count 2 2006.285.15:57:54.20#ibcon#about to read 3, iclass 34, count 2 2006.285.15:57:54.21#ibcon#read 3, iclass 34, count 2 2006.285.15:57:54.21#ibcon#about to read 4, iclass 34, count 2 2006.285.15:57:54.21#ibcon#read 4, iclass 34, count 2 2006.285.15:57:54.21#ibcon#about to read 5, iclass 34, count 2 2006.285.15:57:54.21#ibcon#read 5, iclass 34, count 2 2006.285.15:57:54.21#ibcon#about to read 6, iclass 34, count 2 2006.285.15:57:54.21#ibcon#read 6, iclass 34, count 2 2006.285.15:57:54.21#ibcon#end of sib2, iclass 34, count 2 2006.285.15:57:54.21#ibcon#*mode == 0, iclass 34, count 2 2006.285.15:57:54.21#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.15:57:54.21#ibcon#[27=AT03-04\r\n] 2006.285.15:57:54.21#ibcon#*before write, iclass 34, count 2 2006.285.15:57:54.22#ibcon#enter sib2, iclass 34, count 2 2006.285.15:57:54.22#ibcon#flushed, iclass 34, count 2 2006.285.15:57:54.22#ibcon#about to write, iclass 34, count 2 2006.285.15:57:54.22#ibcon#wrote, iclass 34, count 2 2006.285.15:57:54.22#ibcon#about to read 3, iclass 34, count 2 2006.285.15:57:54.24#ibcon#read 3, iclass 34, count 2 2006.285.15:57:54.24#ibcon#about to read 4, iclass 34, count 2 2006.285.15:57:54.24#ibcon#read 4, iclass 34, count 2 2006.285.15:57:54.24#ibcon#about to read 5, iclass 34, count 2 2006.285.15:57:54.24#ibcon#read 5, iclass 34, count 2 2006.285.15:57:54.24#ibcon#about to read 6, iclass 34, count 2 2006.285.15:57:54.24#ibcon#read 6, iclass 34, count 2 2006.285.15:57:54.24#ibcon#end of sib2, iclass 34, count 2 2006.285.15:57:54.24#ibcon#*after write, iclass 34, count 2 2006.285.15:57:54.24#ibcon#*before return 0, iclass 34, count 2 2006.285.15:57:54.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:57:54.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.15:57:54.25#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.15:57:54.25#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:54.25#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:57:54.35#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:57:54.35#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:57:54.35#ibcon#enter wrdev, iclass 34, count 0 2006.285.15:57:54.35#ibcon#first serial, iclass 34, count 0 2006.285.15:57:54.35#ibcon#enter sib2, iclass 34, count 0 2006.285.15:57:54.35#ibcon#flushed, iclass 34, count 0 2006.285.15:57:54.35#ibcon#about to write, iclass 34, count 0 2006.285.15:57:54.35#ibcon#wrote, iclass 34, count 0 2006.285.15:57:54.35#ibcon#about to read 3, iclass 34, count 0 2006.285.15:57:54.37#ibcon#read 3, iclass 34, count 0 2006.285.15:57:54.37#ibcon#about to read 4, iclass 34, count 0 2006.285.15:57:54.37#ibcon#read 4, iclass 34, count 0 2006.285.15:57:54.37#ibcon#about to read 5, iclass 34, count 0 2006.285.15:57:54.37#ibcon#read 5, iclass 34, count 0 2006.285.15:57:54.37#ibcon#about to read 6, iclass 34, count 0 2006.285.15:57:54.37#ibcon#read 6, iclass 34, count 0 2006.285.15:57:54.37#ibcon#end of sib2, iclass 34, count 0 2006.285.15:57:54.37#ibcon#*mode == 0, iclass 34, count 0 2006.285.15:57:54.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.15:57:54.37#ibcon#[27=USB\r\n] 2006.285.15:57:54.37#ibcon#*before write, iclass 34, count 0 2006.285.15:57:54.37#ibcon#enter sib2, iclass 34, count 0 2006.285.15:57:54.37#ibcon#flushed, iclass 34, count 0 2006.285.15:57:54.37#ibcon#about to write, iclass 34, count 0 2006.285.15:57:54.38#ibcon#wrote, iclass 34, count 0 2006.285.15:57:54.38#ibcon#about to read 3, iclass 34, count 0 2006.285.15:57:54.40#ibcon#read 3, iclass 34, count 0 2006.285.15:57:54.40#ibcon#about to read 4, iclass 34, count 0 2006.285.15:57:54.40#ibcon#read 4, iclass 34, count 0 2006.285.15:57:54.40#ibcon#about to read 5, iclass 34, count 0 2006.285.15:57:54.40#ibcon#read 5, iclass 34, count 0 2006.285.15:57:54.40#ibcon#about to read 6, iclass 34, count 0 2006.285.15:57:54.40#ibcon#read 6, iclass 34, count 0 2006.285.15:57:54.40#ibcon#end of sib2, iclass 34, count 0 2006.285.15:57:54.40#ibcon#*after write, iclass 34, count 0 2006.285.15:57:54.40#ibcon#*before return 0, iclass 34, count 0 2006.285.15:57:54.40#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:57:54.40#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.15:57:54.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.15:57:54.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.15:57:54.41$vck44/vblo=4,679.99 2006.285.15:57:54.41#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.15:57:54.41#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.15:57:54.41#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:54.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:57:54.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:57:54.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:57:54.41#ibcon#enter wrdev, iclass 36, count 0 2006.285.15:57:54.41#ibcon#first serial, iclass 36, count 0 2006.285.15:57:54.41#ibcon#enter sib2, iclass 36, count 0 2006.285.15:57:54.41#ibcon#flushed, iclass 36, count 0 2006.285.15:57:54.41#ibcon#about to write, iclass 36, count 0 2006.285.15:57:54.41#ibcon#wrote, iclass 36, count 0 2006.285.15:57:54.41#ibcon#about to read 3, iclass 36, count 0 2006.285.15:57:54.42#ibcon#read 3, iclass 36, count 0 2006.285.15:57:54.42#ibcon#about to read 4, iclass 36, count 0 2006.285.15:57:54.42#ibcon#read 4, iclass 36, count 0 2006.285.15:57:54.42#ibcon#about to read 5, iclass 36, count 0 2006.285.15:57:54.42#ibcon#read 5, iclass 36, count 0 2006.285.15:57:54.42#ibcon#about to read 6, iclass 36, count 0 2006.285.15:57:54.42#ibcon#read 6, iclass 36, count 0 2006.285.15:57:54.42#ibcon#end of sib2, iclass 36, count 0 2006.285.15:57:54.42#ibcon#*mode == 0, iclass 36, count 0 2006.285.15:57:54.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.15:57:54.42#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.15:57:54.42#ibcon#*before write, iclass 36, count 0 2006.285.15:57:54.42#ibcon#enter sib2, iclass 36, count 0 2006.285.15:57:54.42#ibcon#flushed, iclass 36, count 0 2006.285.15:57:54.43#ibcon#about to write, iclass 36, count 0 2006.285.15:57:54.43#ibcon#wrote, iclass 36, count 0 2006.285.15:57:54.43#ibcon#about to read 3, iclass 36, count 0 2006.285.15:57:54.46#ibcon#read 3, iclass 36, count 0 2006.285.15:57:54.46#ibcon#about to read 4, iclass 36, count 0 2006.285.15:57:54.46#ibcon#read 4, iclass 36, count 0 2006.285.15:57:54.46#ibcon#about to read 5, iclass 36, count 0 2006.285.15:57:54.46#ibcon#read 5, iclass 36, count 0 2006.285.15:57:54.46#ibcon#about to read 6, iclass 36, count 0 2006.285.15:57:54.46#ibcon#read 6, iclass 36, count 0 2006.285.15:57:54.46#ibcon#end of sib2, iclass 36, count 0 2006.285.15:57:54.46#ibcon#*after write, iclass 36, count 0 2006.285.15:57:54.46#ibcon#*before return 0, iclass 36, count 0 2006.285.15:57:54.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:57:54.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.15:57:54.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.15:57:54.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.15:57:54.47$vck44/vb=4,5 2006.285.15:57:54.47#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.15:57:54.47#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.15:57:54.47#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:54.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:57:54.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:57:54.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:57:54.51#ibcon#enter wrdev, iclass 38, count 2 2006.285.15:57:54.51#ibcon#first serial, iclass 38, count 2 2006.285.15:57:54.51#ibcon#enter sib2, iclass 38, count 2 2006.285.15:57:54.51#ibcon#flushed, iclass 38, count 2 2006.285.15:57:54.51#ibcon#about to write, iclass 38, count 2 2006.285.15:57:54.51#ibcon#wrote, iclass 38, count 2 2006.285.15:57:54.51#ibcon#about to read 3, iclass 38, count 2 2006.285.15:57:54.53#ibcon#read 3, iclass 38, count 2 2006.285.15:57:54.53#ibcon#about to read 4, iclass 38, count 2 2006.285.15:57:54.53#ibcon#read 4, iclass 38, count 2 2006.285.15:57:54.53#ibcon#about to read 5, iclass 38, count 2 2006.285.15:57:54.53#ibcon#read 5, iclass 38, count 2 2006.285.15:57:54.53#ibcon#about to read 6, iclass 38, count 2 2006.285.15:57:54.53#ibcon#read 6, iclass 38, count 2 2006.285.15:57:54.53#ibcon#end of sib2, iclass 38, count 2 2006.285.15:57:54.53#ibcon#*mode == 0, iclass 38, count 2 2006.285.15:57:54.53#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.15:57:54.53#ibcon#[27=AT04-05\r\n] 2006.285.15:57:54.53#ibcon#*before write, iclass 38, count 2 2006.285.15:57:54.53#ibcon#enter sib2, iclass 38, count 2 2006.285.15:57:54.53#ibcon#flushed, iclass 38, count 2 2006.285.15:57:54.53#ibcon#about to write, iclass 38, count 2 2006.285.15:57:54.54#ibcon#wrote, iclass 38, count 2 2006.285.15:57:54.54#ibcon#about to read 3, iclass 38, count 2 2006.285.15:57:54.56#ibcon#read 3, iclass 38, count 2 2006.285.15:57:54.56#ibcon#about to read 4, iclass 38, count 2 2006.285.15:57:54.56#ibcon#read 4, iclass 38, count 2 2006.285.15:57:54.56#ibcon#about to read 5, iclass 38, count 2 2006.285.15:57:54.56#ibcon#read 5, iclass 38, count 2 2006.285.15:57:54.56#ibcon#about to read 6, iclass 38, count 2 2006.285.15:57:54.56#ibcon#read 6, iclass 38, count 2 2006.285.15:57:54.56#ibcon#end of sib2, iclass 38, count 2 2006.285.15:57:54.56#ibcon#*after write, iclass 38, count 2 2006.285.15:57:54.56#ibcon#*before return 0, iclass 38, count 2 2006.285.15:57:54.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:57:54.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.15:57:54.56#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.15:57:54.57#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:54.57#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:57:54.67#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:57:54.67#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:57:54.67#ibcon#enter wrdev, iclass 38, count 0 2006.285.15:57:54.67#ibcon#first serial, iclass 38, count 0 2006.285.15:57:54.67#ibcon#enter sib2, iclass 38, count 0 2006.285.15:57:54.67#ibcon#flushed, iclass 38, count 0 2006.285.15:57:54.67#ibcon#about to write, iclass 38, count 0 2006.285.15:57:54.67#ibcon#wrote, iclass 38, count 0 2006.285.15:57:54.67#ibcon#about to read 3, iclass 38, count 0 2006.285.15:57:54.69#ibcon#read 3, iclass 38, count 0 2006.285.15:57:54.69#ibcon#about to read 4, iclass 38, count 0 2006.285.15:57:54.69#ibcon#read 4, iclass 38, count 0 2006.285.15:57:54.69#ibcon#about to read 5, iclass 38, count 0 2006.285.15:57:54.69#ibcon#read 5, iclass 38, count 0 2006.285.15:57:54.69#ibcon#about to read 6, iclass 38, count 0 2006.285.15:57:54.69#ibcon#read 6, iclass 38, count 0 2006.285.15:57:54.69#ibcon#end of sib2, iclass 38, count 0 2006.285.15:57:54.69#ibcon#*mode == 0, iclass 38, count 0 2006.285.15:57:54.69#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.15:57:54.69#ibcon#[27=USB\r\n] 2006.285.15:57:54.69#ibcon#*before write, iclass 38, count 0 2006.285.15:57:54.69#ibcon#enter sib2, iclass 38, count 0 2006.285.15:57:54.69#ibcon#flushed, iclass 38, count 0 2006.285.15:57:54.69#ibcon#about to write, iclass 38, count 0 2006.285.15:57:54.70#ibcon#wrote, iclass 38, count 0 2006.285.15:57:54.70#ibcon#about to read 3, iclass 38, count 0 2006.285.15:57:54.72#ibcon#read 3, iclass 38, count 0 2006.285.15:57:54.72#ibcon#about to read 4, iclass 38, count 0 2006.285.15:57:54.72#ibcon#read 4, iclass 38, count 0 2006.285.15:57:54.72#ibcon#about to read 5, iclass 38, count 0 2006.285.15:57:54.72#ibcon#read 5, iclass 38, count 0 2006.285.15:57:54.72#ibcon#about to read 6, iclass 38, count 0 2006.285.15:57:54.72#ibcon#read 6, iclass 38, count 0 2006.285.15:57:54.72#ibcon#end of sib2, iclass 38, count 0 2006.285.15:57:54.72#ibcon#*after write, iclass 38, count 0 2006.285.15:57:54.72#ibcon#*before return 0, iclass 38, count 0 2006.285.15:57:54.72#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:57:54.72#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.15:57:54.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.15:57:54.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.15:57:54.73$vck44/vblo=5,709.99 2006.285.15:57:54.73#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.15:57:54.73#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.15:57:54.73#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:54.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:57:54.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:57:54.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:57:54.73#ibcon#enter wrdev, iclass 40, count 0 2006.285.15:57:54.73#ibcon#first serial, iclass 40, count 0 2006.285.15:57:54.73#ibcon#enter sib2, iclass 40, count 0 2006.285.15:57:54.73#ibcon#flushed, iclass 40, count 0 2006.285.15:57:54.73#ibcon#about to write, iclass 40, count 0 2006.285.15:57:54.73#ibcon#wrote, iclass 40, count 0 2006.285.15:57:54.73#ibcon#about to read 3, iclass 40, count 0 2006.285.15:57:54.74#ibcon#read 3, iclass 40, count 0 2006.285.15:57:54.74#ibcon#about to read 4, iclass 40, count 0 2006.285.15:57:54.74#ibcon#read 4, iclass 40, count 0 2006.285.15:57:54.74#ibcon#about to read 5, iclass 40, count 0 2006.285.15:57:54.74#ibcon#read 5, iclass 40, count 0 2006.285.15:57:54.74#ibcon#about to read 6, iclass 40, count 0 2006.285.15:57:54.74#ibcon#read 6, iclass 40, count 0 2006.285.15:57:54.74#ibcon#end of sib2, iclass 40, count 0 2006.285.15:57:54.74#ibcon#*mode == 0, iclass 40, count 0 2006.285.15:57:54.74#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.15:57:54.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.15:57:54.74#ibcon#*before write, iclass 40, count 0 2006.285.15:57:54.74#ibcon#enter sib2, iclass 40, count 0 2006.285.15:57:54.74#ibcon#flushed, iclass 40, count 0 2006.285.15:57:54.75#ibcon#about to write, iclass 40, count 0 2006.285.15:57:54.75#ibcon#wrote, iclass 40, count 0 2006.285.15:57:54.75#ibcon#about to read 3, iclass 40, count 0 2006.285.15:57:54.78#ibcon#read 3, iclass 40, count 0 2006.285.15:57:54.78#ibcon#about to read 4, iclass 40, count 0 2006.285.15:57:54.78#ibcon#read 4, iclass 40, count 0 2006.285.15:57:54.78#ibcon#about to read 5, iclass 40, count 0 2006.285.15:57:54.78#ibcon#read 5, iclass 40, count 0 2006.285.15:57:54.78#ibcon#about to read 6, iclass 40, count 0 2006.285.15:57:54.78#ibcon#read 6, iclass 40, count 0 2006.285.15:57:54.78#ibcon#end of sib2, iclass 40, count 0 2006.285.15:57:54.78#ibcon#*after write, iclass 40, count 0 2006.285.15:57:54.78#ibcon#*before return 0, iclass 40, count 0 2006.285.15:57:54.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:57:54.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.15:57:54.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.15:57:54.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.15:57:54.79$vck44/vb=5,4 2006.285.15:57:54.79#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.15:57:54.79#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.15:57:54.79#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:54.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:57:54.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:57:54.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:57:54.83#ibcon#enter wrdev, iclass 4, count 2 2006.285.15:57:54.83#ibcon#first serial, iclass 4, count 2 2006.285.15:57:54.83#ibcon#enter sib2, iclass 4, count 2 2006.285.15:57:54.83#ibcon#flushed, iclass 4, count 2 2006.285.15:57:54.83#ibcon#about to write, iclass 4, count 2 2006.285.15:57:54.83#ibcon#wrote, iclass 4, count 2 2006.285.15:57:54.83#ibcon#about to read 3, iclass 4, count 2 2006.285.15:57:54.85#ibcon#read 3, iclass 4, count 2 2006.285.15:57:54.85#ibcon#about to read 4, iclass 4, count 2 2006.285.15:57:54.85#ibcon#read 4, iclass 4, count 2 2006.285.15:57:54.85#ibcon#about to read 5, iclass 4, count 2 2006.285.15:57:54.85#ibcon#read 5, iclass 4, count 2 2006.285.15:57:54.85#ibcon#about to read 6, iclass 4, count 2 2006.285.15:57:54.85#ibcon#read 6, iclass 4, count 2 2006.285.15:57:54.85#ibcon#end of sib2, iclass 4, count 2 2006.285.15:57:54.85#ibcon#*mode == 0, iclass 4, count 2 2006.285.15:57:54.85#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.15:57:54.85#ibcon#[27=AT05-04\r\n] 2006.285.15:57:54.85#ibcon#*before write, iclass 4, count 2 2006.285.15:57:54.85#ibcon#enter sib2, iclass 4, count 2 2006.285.15:57:54.85#ibcon#flushed, iclass 4, count 2 2006.285.15:57:54.85#ibcon#about to write, iclass 4, count 2 2006.285.15:57:54.86#ibcon#wrote, iclass 4, count 2 2006.285.15:57:54.86#ibcon#about to read 3, iclass 4, count 2 2006.285.15:57:54.88#ibcon#read 3, iclass 4, count 2 2006.285.15:57:54.88#ibcon#about to read 4, iclass 4, count 2 2006.285.15:57:54.88#ibcon#read 4, iclass 4, count 2 2006.285.15:57:54.88#ibcon#about to read 5, iclass 4, count 2 2006.285.15:57:54.88#ibcon#read 5, iclass 4, count 2 2006.285.15:57:54.88#ibcon#about to read 6, iclass 4, count 2 2006.285.15:57:54.88#ibcon#read 6, iclass 4, count 2 2006.285.15:57:54.88#ibcon#end of sib2, iclass 4, count 2 2006.285.15:57:54.88#ibcon#*after write, iclass 4, count 2 2006.285.15:57:54.88#ibcon#*before return 0, iclass 4, count 2 2006.285.15:57:54.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:57:54.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.15:57:54.88#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.15:57:54.88#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:54.89#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:57:54.99#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:57:54.99#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:57:54.99#ibcon#enter wrdev, iclass 4, count 0 2006.285.15:57:54.99#ibcon#first serial, iclass 4, count 0 2006.285.15:57:54.99#ibcon#enter sib2, iclass 4, count 0 2006.285.15:57:54.99#ibcon#flushed, iclass 4, count 0 2006.285.15:57:54.99#ibcon#about to write, iclass 4, count 0 2006.285.15:57:54.99#ibcon#wrote, iclass 4, count 0 2006.285.15:57:54.99#ibcon#about to read 3, iclass 4, count 0 2006.285.15:57:55.01#ibcon#read 3, iclass 4, count 0 2006.285.15:57:55.01#ibcon#about to read 4, iclass 4, count 0 2006.285.15:57:55.01#ibcon#read 4, iclass 4, count 0 2006.285.15:57:55.01#ibcon#about to read 5, iclass 4, count 0 2006.285.15:57:55.01#ibcon#read 5, iclass 4, count 0 2006.285.15:57:55.01#ibcon#about to read 6, iclass 4, count 0 2006.285.15:57:55.01#ibcon#read 6, iclass 4, count 0 2006.285.15:57:55.01#ibcon#end of sib2, iclass 4, count 0 2006.285.15:57:55.01#ibcon#*mode == 0, iclass 4, count 0 2006.285.15:57:55.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.15:57:55.01#ibcon#[27=USB\r\n] 2006.285.15:57:55.01#ibcon#*before write, iclass 4, count 0 2006.285.15:57:55.01#ibcon#enter sib2, iclass 4, count 0 2006.285.15:57:55.01#ibcon#flushed, iclass 4, count 0 2006.285.15:57:55.02#ibcon#about to write, iclass 4, count 0 2006.285.15:57:55.02#ibcon#wrote, iclass 4, count 0 2006.285.15:57:55.02#ibcon#about to read 3, iclass 4, count 0 2006.285.15:57:55.04#ibcon#read 3, iclass 4, count 0 2006.285.15:57:55.04#ibcon#about to read 4, iclass 4, count 0 2006.285.15:57:55.04#ibcon#read 4, iclass 4, count 0 2006.285.15:57:55.04#ibcon#about to read 5, iclass 4, count 0 2006.285.15:57:55.04#ibcon#read 5, iclass 4, count 0 2006.285.15:57:55.04#ibcon#about to read 6, iclass 4, count 0 2006.285.15:57:55.04#ibcon#read 6, iclass 4, count 0 2006.285.15:57:55.04#ibcon#end of sib2, iclass 4, count 0 2006.285.15:57:55.04#ibcon#*after write, iclass 4, count 0 2006.285.15:57:55.04#ibcon#*before return 0, iclass 4, count 0 2006.285.15:57:55.04#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:57:55.05#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.15:57:55.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.15:57:55.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.15:57:55.05$vck44/vblo=6,719.99 2006.285.15:57:55.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.15:57:55.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.15:57:55.05#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:55.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:57:55.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:57:55.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:57:55.05#ibcon#enter wrdev, iclass 6, count 0 2006.285.15:57:55.05#ibcon#first serial, iclass 6, count 0 2006.285.15:57:55.05#ibcon#enter sib2, iclass 6, count 0 2006.285.15:57:55.05#ibcon#flushed, iclass 6, count 0 2006.285.15:57:55.05#ibcon#about to write, iclass 6, count 0 2006.285.15:57:55.05#ibcon#wrote, iclass 6, count 0 2006.285.15:57:55.05#ibcon#about to read 3, iclass 6, count 0 2006.285.15:57:55.06#ibcon#read 3, iclass 6, count 0 2006.285.15:57:55.20#ibcon#about to read 4, iclass 6, count 0 2006.285.15:57:55.20#ibcon#read 4, iclass 6, count 0 2006.285.15:57:55.20#ibcon#about to read 5, iclass 6, count 0 2006.285.15:57:55.20#ibcon#read 5, iclass 6, count 0 2006.285.15:57:55.20#ibcon#about to read 6, iclass 6, count 0 2006.285.15:57:55.20#ibcon#read 6, iclass 6, count 0 2006.285.15:57:55.20#ibcon#end of sib2, iclass 6, count 0 2006.285.15:57:55.20#ibcon#*mode == 0, iclass 6, count 0 2006.285.15:57:55.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.15:57:55.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.15:57:55.20#ibcon#*before write, iclass 6, count 0 2006.285.15:57:55.20#ibcon#enter sib2, iclass 6, count 0 2006.285.15:57:55.20#ibcon#flushed, iclass 6, count 0 2006.285.15:57:55.20#ibcon#about to write, iclass 6, count 0 2006.285.15:57:55.20#ibcon#wrote, iclass 6, count 0 2006.285.15:57:55.20#ibcon#about to read 3, iclass 6, count 0 2006.285.15:57:55.23#ibcon#read 3, iclass 6, count 0 2006.285.15:57:55.23#ibcon#about to read 4, iclass 6, count 0 2006.285.15:57:55.23#ibcon#read 4, iclass 6, count 0 2006.285.15:57:55.23#ibcon#about to read 5, iclass 6, count 0 2006.285.15:57:55.23#ibcon#read 5, iclass 6, count 0 2006.285.15:57:55.23#ibcon#about to read 6, iclass 6, count 0 2006.285.15:57:55.23#ibcon#read 6, iclass 6, count 0 2006.285.15:57:55.23#ibcon#end of sib2, iclass 6, count 0 2006.285.15:57:55.23#ibcon#*after write, iclass 6, count 0 2006.285.15:57:55.23#ibcon#*before return 0, iclass 6, count 0 2006.285.15:57:55.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:57:55.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.15:57:55.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.15:57:55.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.15:57:55.24$vck44/vb=6,3 2006.285.15:57:55.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.15:57:55.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.15:57:55.24#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:55.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:57:55.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:57:55.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:57:55.24#ibcon#enter wrdev, iclass 10, count 2 2006.285.15:57:55.24#ibcon#first serial, iclass 10, count 2 2006.285.15:57:55.24#ibcon#enter sib2, iclass 10, count 2 2006.285.15:57:55.24#ibcon#flushed, iclass 10, count 2 2006.285.15:57:55.24#ibcon#about to write, iclass 10, count 2 2006.285.15:57:55.24#ibcon#wrote, iclass 10, count 2 2006.285.15:57:55.24#ibcon#about to read 3, iclass 10, count 2 2006.285.15:57:55.25#ibcon#read 3, iclass 10, count 2 2006.285.15:57:55.25#ibcon#about to read 4, iclass 10, count 2 2006.285.15:57:55.25#ibcon#read 4, iclass 10, count 2 2006.285.15:57:55.25#ibcon#about to read 5, iclass 10, count 2 2006.285.15:57:55.25#ibcon#read 5, iclass 10, count 2 2006.285.15:57:55.25#ibcon#about to read 6, iclass 10, count 2 2006.285.15:57:55.25#ibcon#read 6, iclass 10, count 2 2006.285.15:57:55.25#ibcon#end of sib2, iclass 10, count 2 2006.285.15:57:55.25#ibcon#*mode == 0, iclass 10, count 2 2006.285.15:57:55.25#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.15:57:55.25#ibcon#[27=AT06-03\r\n] 2006.285.15:57:55.25#ibcon#*before write, iclass 10, count 2 2006.285.15:57:55.25#ibcon#enter sib2, iclass 10, count 2 2006.285.15:57:55.26#ibcon#flushed, iclass 10, count 2 2006.285.15:57:55.26#ibcon#about to write, iclass 10, count 2 2006.285.15:57:55.26#ibcon#wrote, iclass 10, count 2 2006.285.15:57:55.26#ibcon#about to read 3, iclass 10, count 2 2006.285.15:57:55.28#ibcon#read 3, iclass 10, count 2 2006.285.15:57:55.28#ibcon#about to read 4, iclass 10, count 2 2006.285.15:57:55.28#ibcon#read 4, iclass 10, count 2 2006.285.15:57:55.28#ibcon#about to read 5, iclass 10, count 2 2006.285.15:57:55.28#ibcon#read 5, iclass 10, count 2 2006.285.15:57:55.28#ibcon#about to read 6, iclass 10, count 2 2006.285.15:57:55.28#ibcon#read 6, iclass 10, count 2 2006.285.15:57:55.28#ibcon#end of sib2, iclass 10, count 2 2006.285.15:57:55.28#ibcon#*after write, iclass 10, count 2 2006.285.15:57:55.28#ibcon#*before return 0, iclass 10, count 2 2006.285.15:57:55.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:57:55.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.15:57:55.29#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.15:57:55.29#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:55.29#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:57:55.39#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:57:55.39#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:57:55.39#ibcon#enter wrdev, iclass 10, count 0 2006.285.15:57:55.39#ibcon#first serial, iclass 10, count 0 2006.285.15:57:55.39#ibcon#enter sib2, iclass 10, count 0 2006.285.15:57:55.39#ibcon#flushed, iclass 10, count 0 2006.285.15:57:55.39#ibcon#about to write, iclass 10, count 0 2006.285.15:57:55.39#ibcon#wrote, iclass 10, count 0 2006.285.15:57:55.39#ibcon#about to read 3, iclass 10, count 0 2006.285.15:57:55.41#ibcon#read 3, iclass 10, count 0 2006.285.15:57:55.41#ibcon#about to read 4, iclass 10, count 0 2006.285.15:57:55.41#ibcon#read 4, iclass 10, count 0 2006.285.15:57:55.41#ibcon#about to read 5, iclass 10, count 0 2006.285.15:57:55.41#ibcon#read 5, iclass 10, count 0 2006.285.15:57:55.41#ibcon#about to read 6, iclass 10, count 0 2006.285.15:57:55.41#ibcon#read 6, iclass 10, count 0 2006.285.15:57:55.41#ibcon#end of sib2, iclass 10, count 0 2006.285.15:57:55.41#ibcon#*mode == 0, iclass 10, count 0 2006.285.15:57:55.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.15:57:55.41#ibcon#[27=USB\r\n] 2006.285.15:57:55.41#ibcon#*before write, iclass 10, count 0 2006.285.15:57:55.41#ibcon#enter sib2, iclass 10, count 0 2006.285.15:57:55.42#ibcon#flushed, iclass 10, count 0 2006.285.15:57:55.42#ibcon#about to write, iclass 10, count 0 2006.285.15:57:55.42#ibcon#wrote, iclass 10, count 0 2006.285.15:57:55.42#ibcon#about to read 3, iclass 10, count 0 2006.285.15:57:55.44#ibcon#read 3, iclass 10, count 0 2006.285.15:57:55.44#ibcon#about to read 4, iclass 10, count 0 2006.285.15:57:55.44#ibcon#read 4, iclass 10, count 0 2006.285.15:57:55.44#ibcon#about to read 5, iclass 10, count 0 2006.285.15:57:55.44#ibcon#read 5, iclass 10, count 0 2006.285.15:57:55.44#ibcon#about to read 6, iclass 10, count 0 2006.285.15:57:55.44#ibcon#read 6, iclass 10, count 0 2006.285.15:57:55.44#ibcon#end of sib2, iclass 10, count 0 2006.285.15:57:55.44#ibcon#*after write, iclass 10, count 0 2006.285.15:57:55.44#ibcon#*before return 0, iclass 10, count 0 2006.285.15:57:55.44#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:57:55.44#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.15:57:55.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.15:57:55.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.15:57:55.45$vck44/vblo=7,734.99 2006.285.15:57:55.45#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.15:57:55.45#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.15:57:55.45#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:55.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:57:55.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:57:55.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:57:55.45#ibcon#enter wrdev, iclass 12, count 0 2006.285.15:57:55.45#ibcon#first serial, iclass 12, count 0 2006.285.15:57:55.45#ibcon#enter sib2, iclass 12, count 0 2006.285.15:57:55.45#ibcon#flushed, iclass 12, count 0 2006.285.15:57:55.45#ibcon#about to write, iclass 12, count 0 2006.285.15:57:55.45#ibcon#wrote, iclass 12, count 0 2006.285.15:57:55.45#ibcon#about to read 3, iclass 12, count 0 2006.285.15:57:55.46#ibcon#read 3, iclass 12, count 0 2006.285.15:57:55.46#ibcon#about to read 4, iclass 12, count 0 2006.285.15:57:55.46#ibcon#read 4, iclass 12, count 0 2006.285.15:57:55.46#ibcon#about to read 5, iclass 12, count 0 2006.285.15:57:55.46#ibcon#read 5, iclass 12, count 0 2006.285.15:57:55.46#ibcon#about to read 6, iclass 12, count 0 2006.285.15:57:55.46#ibcon#read 6, iclass 12, count 0 2006.285.15:57:55.46#ibcon#end of sib2, iclass 12, count 0 2006.285.15:57:55.46#ibcon#*mode == 0, iclass 12, count 0 2006.285.15:57:55.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.15:57:55.46#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.15:57:55.46#ibcon#*before write, iclass 12, count 0 2006.285.15:57:55.46#ibcon#enter sib2, iclass 12, count 0 2006.285.15:57:55.46#ibcon#flushed, iclass 12, count 0 2006.285.15:57:55.46#ibcon#about to write, iclass 12, count 0 2006.285.15:57:55.47#ibcon#wrote, iclass 12, count 0 2006.285.15:57:55.47#ibcon#about to read 3, iclass 12, count 0 2006.285.15:57:55.50#ibcon#read 3, iclass 12, count 0 2006.285.15:57:55.50#ibcon#about to read 4, iclass 12, count 0 2006.285.15:57:55.50#ibcon#read 4, iclass 12, count 0 2006.285.15:57:55.50#ibcon#about to read 5, iclass 12, count 0 2006.285.15:57:55.50#ibcon#read 5, iclass 12, count 0 2006.285.15:57:55.50#ibcon#about to read 6, iclass 12, count 0 2006.285.15:57:55.50#ibcon#read 6, iclass 12, count 0 2006.285.15:57:55.50#ibcon#end of sib2, iclass 12, count 0 2006.285.15:57:55.50#ibcon#*after write, iclass 12, count 0 2006.285.15:57:55.50#ibcon#*before return 0, iclass 12, count 0 2006.285.15:57:55.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:57:55.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.15:57:55.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.15:57:55.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.15:57:55.51$vck44/vb=7,4 2006.285.15:57:55.51#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.15:57:55.51#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.15:57:55.51#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:55.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:57:55.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:57:55.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:57:55.55#ibcon#enter wrdev, iclass 14, count 2 2006.285.15:57:55.55#ibcon#first serial, iclass 14, count 2 2006.285.15:57:55.55#ibcon#enter sib2, iclass 14, count 2 2006.285.15:57:55.55#ibcon#flushed, iclass 14, count 2 2006.285.15:57:55.55#ibcon#about to write, iclass 14, count 2 2006.285.15:57:55.55#ibcon#wrote, iclass 14, count 2 2006.285.15:57:55.55#ibcon#about to read 3, iclass 14, count 2 2006.285.15:57:55.57#ibcon#read 3, iclass 14, count 2 2006.285.15:57:55.57#ibcon#about to read 4, iclass 14, count 2 2006.285.15:57:55.57#ibcon#read 4, iclass 14, count 2 2006.285.15:57:55.57#ibcon#about to read 5, iclass 14, count 2 2006.285.15:57:55.57#ibcon#read 5, iclass 14, count 2 2006.285.15:57:55.57#ibcon#about to read 6, iclass 14, count 2 2006.285.15:57:55.57#ibcon#read 6, iclass 14, count 2 2006.285.15:57:55.57#ibcon#end of sib2, iclass 14, count 2 2006.285.15:57:55.57#ibcon#*mode == 0, iclass 14, count 2 2006.285.15:57:55.57#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.15:57:55.57#ibcon#[27=AT07-04\r\n] 2006.285.15:57:55.57#ibcon#*before write, iclass 14, count 2 2006.285.15:57:55.57#ibcon#enter sib2, iclass 14, count 2 2006.285.15:57:55.57#ibcon#flushed, iclass 14, count 2 2006.285.15:57:55.57#ibcon#about to write, iclass 14, count 2 2006.285.15:57:55.58#ibcon#wrote, iclass 14, count 2 2006.285.15:57:55.58#ibcon#about to read 3, iclass 14, count 2 2006.285.15:57:55.60#ibcon#read 3, iclass 14, count 2 2006.285.15:57:55.60#ibcon#about to read 4, iclass 14, count 2 2006.285.15:57:55.60#ibcon#read 4, iclass 14, count 2 2006.285.15:57:55.60#ibcon#about to read 5, iclass 14, count 2 2006.285.15:57:55.60#ibcon#read 5, iclass 14, count 2 2006.285.15:57:55.60#ibcon#about to read 6, iclass 14, count 2 2006.285.15:57:55.60#ibcon#read 6, iclass 14, count 2 2006.285.15:57:55.60#ibcon#end of sib2, iclass 14, count 2 2006.285.15:57:55.60#ibcon#*after write, iclass 14, count 2 2006.285.15:57:55.60#ibcon#*before return 0, iclass 14, count 2 2006.285.15:57:55.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:57:55.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.15:57:55.60#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.15:57:55.60#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:55.61#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:57:55.71#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:57:55.71#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:57:55.72#ibcon#enter wrdev, iclass 14, count 0 2006.285.15:57:55.72#ibcon#first serial, iclass 14, count 0 2006.285.15:57:55.72#ibcon#enter sib2, iclass 14, count 0 2006.285.15:57:55.72#ibcon#flushed, iclass 14, count 0 2006.285.15:57:55.72#ibcon#about to write, iclass 14, count 0 2006.285.15:57:55.72#ibcon#wrote, iclass 14, count 0 2006.285.15:57:55.72#ibcon#about to read 3, iclass 14, count 0 2006.285.15:57:55.73#ibcon#read 3, iclass 14, count 0 2006.285.15:57:55.73#ibcon#about to read 4, iclass 14, count 0 2006.285.15:57:55.73#ibcon#read 4, iclass 14, count 0 2006.285.15:57:55.73#ibcon#about to read 5, iclass 14, count 0 2006.285.15:57:55.73#ibcon#read 5, iclass 14, count 0 2006.285.15:57:55.73#ibcon#about to read 6, iclass 14, count 0 2006.285.15:57:55.73#ibcon#read 6, iclass 14, count 0 2006.285.15:57:55.73#ibcon#end of sib2, iclass 14, count 0 2006.285.15:57:55.73#ibcon#*mode == 0, iclass 14, count 0 2006.285.15:57:55.73#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.15:57:55.73#ibcon#[27=USB\r\n] 2006.285.15:57:55.73#ibcon#*before write, iclass 14, count 0 2006.285.15:57:55.73#ibcon#enter sib2, iclass 14, count 0 2006.285.15:57:55.73#ibcon#flushed, iclass 14, count 0 2006.285.15:57:55.73#ibcon#about to write, iclass 14, count 0 2006.285.15:57:55.74#ibcon#wrote, iclass 14, count 0 2006.285.15:57:55.74#ibcon#about to read 3, iclass 14, count 0 2006.285.15:57:55.76#abcon#<5=/01 0.8 2.5 18.67 931014.9\r\n> 2006.285.15:57:55.77#ibcon#read 3, iclass 14, count 0 2006.285.15:57:55.77#ibcon#about to read 4, iclass 14, count 0 2006.285.15:57:55.77#ibcon#read 4, iclass 14, count 0 2006.285.15:57:55.77#ibcon#about to read 5, iclass 14, count 0 2006.285.15:57:55.77#ibcon#read 5, iclass 14, count 0 2006.285.15:57:55.77#ibcon#about to read 6, iclass 14, count 0 2006.285.15:57:55.77#ibcon#read 6, iclass 14, count 0 2006.285.15:57:55.77#ibcon#end of sib2, iclass 14, count 0 2006.285.15:57:55.77#ibcon#*after write, iclass 14, count 0 2006.285.15:57:55.77#ibcon#*before return 0, iclass 14, count 0 2006.285.15:57:55.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:57:55.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.15:57:55.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.15:57:55.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.15:57:55.77$vck44/vblo=8,744.99 2006.285.15:57:55.77#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.15:57:55.77#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.15:57:55.77#ibcon#ireg 17 cls_cnt 0 2006.285.15:57:55.77#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:57:55.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:57:55.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:57:55.77#ibcon#enter wrdev, iclass 19, count 0 2006.285.15:57:55.77#ibcon#first serial, iclass 19, count 0 2006.285.15:57:55.77#ibcon#enter sib2, iclass 19, count 0 2006.285.15:57:55.77#ibcon#flushed, iclass 19, count 0 2006.285.15:57:55.77#ibcon#about to write, iclass 19, count 0 2006.285.15:57:55.77#ibcon#wrote, iclass 19, count 0 2006.285.15:57:55.77#ibcon#about to read 3, iclass 19, count 0 2006.285.15:57:55.78#abcon#{5=INTERFACE CLEAR} 2006.285.15:57:55.79#ibcon#read 3, iclass 19, count 0 2006.285.15:57:55.79#ibcon#about to read 4, iclass 19, count 0 2006.285.15:57:55.79#ibcon#read 4, iclass 19, count 0 2006.285.15:57:55.79#ibcon#about to read 5, iclass 19, count 0 2006.285.15:57:55.79#ibcon#read 5, iclass 19, count 0 2006.285.15:57:55.79#ibcon#about to read 6, iclass 19, count 0 2006.285.15:57:55.79#ibcon#read 6, iclass 19, count 0 2006.285.15:57:55.79#ibcon#end of sib2, iclass 19, count 0 2006.285.15:57:55.79#ibcon#*mode == 0, iclass 19, count 0 2006.285.15:57:55.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.15:57:55.79#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.15:57:55.79#ibcon#*before write, iclass 19, count 0 2006.285.15:57:55.79#ibcon#enter sib2, iclass 19, count 0 2006.285.15:57:55.79#ibcon#flushed, iclass 19, count 0 2006.285.15:57:55.79#ibcon#about to write, iclass 19, count 0 2006.285.15:57:55.79#ibcon#wrote, iclass 19, count 0 2006.285.15:57:55.79#ibcon#about to read 3, iclass 19, count 0 2006.285.15:57:55.82#ibcon#read 3, iclass 19, count 0 2006.285.15:57:55.82#ibcon#about to read 4, iclass 19, count 0 2006.285.15:57:55.82#ibcon#read 4, iclass 19, count 0 2006.285.15:57:55.82#ibcon#about to read 5, iclass 19, count 0 2006.285.15:57:55.82#ibcon#read 5, iclass 19, count 0 2006.285.15:57:55.82#ibcon#about to read 6, iclass 19, count 0 2006.285.15:57:55.82#ibcon#read 6, iclass 19, count 0 2006.285.15:57:55.82#ibcon#end of sib2, iclass 19, count 0 2006.285.15:57:55.82#ibcon#*after write, iclass 19, count 0 2006.285.15:57:55.82#ibcon#*before return 0, iclass 19, count 0 2006.285.15:57:55.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:57:55.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.15:57:55.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.15:57:55.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.15:57:55.83$vck44/vb=8,4 2006.285.15:57:55.83#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.15:57:55.83#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.15:57:55.83#ibcon#ireg 11 cls_cnt 2 2006.285.15:57:55.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:57:55.84#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:57:55.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:57:55.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:57:55.88#ibcon#enter wrdev, iclass 21, count 2 2006.285.15:57:55.88#ibcon#first serial, iclass 21, count 2 2006.285.15:57:55.88#ibcon#enter sib2, iclass 21, count 2 2006.285.15:57:55.88#ibcon#flushed, iclass 21, count 2 2006.285.15:57:55.88#ibcon#about to write, iclass 21, count 2 2006.285.15:57:55.88#ibcon#wrote, iclass 21, count 2 2006.285.15:57:55.89#ibcon#about to read 3, iclass 21, count 2 2006.285.15:57:55.90#ibcon#read 3, iclass 21, count 2 2006.285.15:57:55.90#ibcon#about to read 4, iclass 21, count 2 2006.285.15:57:55.90#ibcon#read 4, iclass 21, count 2 2006.285.15:57:55.90#ibcon#about to read 5, iclass 21, count 2 2006.285.15:57:55.90#ibcon#read 5, iclass 21, count 2 2006.285.15:57:55.90#ibcon#about to read 6, iclass 21, count 2 2006.285.15:57:55.90#ibcon#read 6, iclass 21, count 2 2006.285.15:57:55.90#ibcon#end of sib2, iclass 21, count 2 2006.285.15:57:55.90#ibcon#*mode == 0, iclass 21, count 2 2006.285.15:57:55.90#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.15:57:55.90#ibcon#[27=AT08-04\r\n] 2006.285.15:57:55.90#ibcon#*before write, iclass 21, count 2 2006.285.15:57:55.90#ibcon#enter sib2, iclass 21, count 2 2006.285.15:57:55.90#ibcon#flushed, iclass 21, count 2 2006.285.15:57:55.90#ibcon#about to write, iclass 21, count 2 2006.285.15:57:55.91#ibcon#wrote, iclass 21, count 2 2006.285.15:57:55.91#ibcon#about to read 3, iclass 21, count 2 2006.285.15:57:55.93#ibcon#read 3, iclass 21, count 2 2006.285.15:57:55.93#ibcon#about to read 4, iclass 21, count 2 2006.285.15:57:55.93#ibcon#read 4, iclass 21, count 2 2006.285.15:57:55.93#ibcon#about to read 5, iclass 21, count 2 2006.285.15:57:55.93#ibcon#read 5, iclass 21, count 2 2006.285.15:57:55.93#ibcon#about to read 6, iclass 21, count 2 2006.285.15:57:55.93#ibcon#read 6, iclass 21, count 2 2006.285.15:57:55.93#ibcon#end of sib2, iclass 21, count 2 2006.285.15:57:55.93#ibcon#*after write, iclass 21, count 2 2006.285.15:57:55.93#ibcon#*before return 0, iclass 21, count 2 2006.285.15:57:55.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:57:55.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.15:57:55.94#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.15:57:55.94#ibcon#ireg 7 cls_cnt 0 2006.285.15:57:55.94#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:57:56.05#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:57:56.05#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:57:56.05#ibcon#enter wrdev, iclass 21, count 0 2006.285.15:57:56.05#ibcon#first serial, iclass 21, count 0 2006.285.15:57:56.05#ibcon#enter sib2, iclass 21, count 0 2006.285.15:57:56.05#ibcon#flushed, iclass 21, count 0 2006.285.15:57:56.05#ibcon#about to write, iclass 21, count 0 2006.285.15:57:56.05#ibcon#wrote, iclass 21, count 0 2006.285.15:57:56.05#ibcon#about to read 3, iclass 21, count 0 2006.285.15:57:56.07#ibcon#read 3, iclass 21, count 0 2006.285.15:57:56.07#ibcon#about to read 4, iclass 21, count 0 2006.285.15:57:56.07#ibcon#read 4, iclass 21, count 0 2006.285.15:57:56.07#ibcon#about to read 5, iclass 21, count 0 2006.285.15:57:56.07#ibcon#read 5, iclass 21, count 0 2006.285.15:57:56.07#ibcon#about to read 6, iclass 21, count 0 2006.285.15:57:56.07#ibcon#read 6, iclass 21, count 0 2006.285.15:57:56.07#ibcon#end of sib2, iclass 21, count 0 2006.285.15:57:56.07#ibcon#*mode == 0, iclass 21, count 0 2006.285.15:57:56.07#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.15:57:56.07#ibcon#[27=USB\r\n] 2006.285.15:57:56.07#ibcon#*before write, iclass 21, count 0 2006.285.15:57:56.07#ibcon#enter sib2, iclass 21, count 0 2006.285.15:57:56.08#ibcon#flushed, iclass 21, count 0 2006.285.15:57:56.08#ibcon#about to write, iclass 21, count 0 2006.285.15:57:56.08#ibcon#wrote, iclass 21, count 0 2006.285.15:57:56.08#ibcon#about to read 3, iclass 21, count 0 2006.285.15:57:56.10#ibcon#read 3, iclass 21, count 0 2006.285.15:57:56.10#ibcon#about to read 4, iclass 21, count 0 2006.285.15:57:56.10#ibcon#read 4, iclass 21, count 0 2006.285.15:57:56.10#ibcon#about to read 5, iclass 21, count 0 2006.285.15:57:56.10#ibcon#read 5, iclass 21, count 0 2006.285.15:57:56.10#ibcon#about to read 6, iclass 21, count 0 2006.285.15:57:56.10#ibcon#read 6, iclass 21, count 0 2006.285.15:57:56.10#ibcon#end of sib2, iclass 21, count 0 2006.285.15:57:56.10#ibcon#*after write, iclass 21, count 0 2006.285.15:57:56.10#ibcon#*before return 0, iclass 21, count 0 2006.285.15:57:56.10#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:57:56.10#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.15:57:56.11#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.15:57:56.11#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.15:57:56.11$vck44/vabw=wide 2006.285.15:57:56.11#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.15:57:56.11#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.15:57:56.11#ibcon#ireg 8 cls_cnt 0 2006.285.15:57:56.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:57:56.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:57:56.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:57:56.11#ibcon#enter wrdev, iclass 24, count 0 2006.285.15:57:56.11#ibcon#first serial, iclass 24, count 0 2006.285.15:57:56.11#ibcon#enter sib2, iclass 24, count 0 2006.285.15:57:56.11#ibcon#flushed, iclass 24, count 0 2006.285.15:57:56.11#ibcon#about to write, iclass 24, count 0 2006.285.15:57:56.11#ibcon#wrote, iclass 24, count 0 2006.285.15:57:56.11#ibcon#about to read 3, iclass 24, count 0 2006.285.15:57:56.12#ibcon#read 3, iclass 24, count 0 2006.285.15:57:56.49#ibcon#about to read 4, iclass 24, count 0 2006.285.15:57:56.49#ibcon#read 4, iclass 24, count 0 2006.285.15:57:56.49#ibcon#about to read 5, iclass 24, count 0 2006.285.15:57:56.49#ibcon#read 5, iclass 24, count 0 2006.285.15:57:56.49#ibcon#about to read 6, iclass 24, count 0 2006.285.15:57:56.49#ibcon#read 6, iclass 24, count 0 2006.285.15:57:56.49#ibcon#end of sib2, iclass 24, count 0 2006.285.15:57:56.49#ibcon#*mode == 0, iclass 24, count 0 2006.285.15:57:56.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.15:57:56.49#ibcon#[25=BW32\r\n] 2006.285.15:57:56.49#ibcon#*before write, iclass 24, count 0 2006.285.15:57:56.49#ibcon#enter sib2, iclass 24, count 0 2006.285.15:57:56.49#ibcon#flushed, iclass 24, count 0 2006.285.15:57:56.49#ibcon#about to write, iclass 24, count 0 2006.285.15:57:56.49#ibcon#wrote, iclass 24, count 0 2006.285.15:57:56.49#ibcon#about to read 3, iclass 24, count 0 2006.285.15:57:56.52#ibcon#read 3, iclass 24, count 0 2006.285.15:57:56.52#ibcon#about to read 4, iclass 24, count 0 2006.285.15:57:56.52#ibcon#read 4, iclass 24, count 0 2006.285.15:57:56.52#ibcon#about to read 5, iclass 24, count 0 2006.285.15:57:56.52#ibcon#read 5, iclass 24, count 0 2006.285.15:57:56.52#ibcon#about to read 6, iclass 24, count 0 2006.285.15:57:56.52#ibcon#read 6, iclass 24, count 0 2006.285.15:57:56.52#ibcon#end of sib2, iclass 24, count 0 2006.285.15:57:56.52#ibcon#*after write, iclass 24, count 0 2006.285.15:57:56.52#ibcon#*before return 0, iclass 24, count 0 2006.285.15:57:56.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:57:56.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.15:57:56.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.15:57:56.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.15:57:56.53$vck44/vbbw=wide 2006.285.15:57:56.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.15:57:56.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.15:57:56.53#ibcon#ireg 8 cls_cnt 0 2006.285.15:57:56.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:57:56.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:57:56.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:57:56.53#ibcon#enter wrdev, iclass 26, count 0 2006.285.15:57:56.53#ibcon#first serial, iclass 26, count 0 2006.285.15:57:56.53#ibcon#enter sib2, iclass 26, count 0 2006.285.15:57:56.53#ibcon#flushed, iclass 26, count 0 2006.285.15:57:56.53#ibcon#about to write, iclass 26, count 0 2006.285.15:57:56.53#ibcon#wrote, iclass 26, count 0 2006.285.15:57:56.53#ibcon#about to read 3, iclass 26, count 0 2006.285.15:57:56.54#ibcon#read 3, iclass 26, count 0 2006.285.15:57:56.54#ibcon#about to read 4, iclass 26, count 0 2006.285.15:57:56.54#ibcon#read 4, iclass 26, count 0 2006.285.15:57:56.54#ibcon#about to read 5, iclass 26, count 0 2006.285.15:57:56.54#ibcon#read 5, iclass 26, count 0 2006.285.15:57:56.54#ibcon#about to read 6, iclass 26, count 0 2006.285.15:57:56.54#ibcon#read 6, iclass 26, count 0 2006.285.15:57:56.54#ibcon#end of sib2, iclass 26, count 0 2006.285.15:57:56.54#ibcon#*mode == 0, iclass 26, count 0 2006.285.15:57:56.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.15:57:56.54#ibcon#[27=BW32\r\n] 2006.285.15:57:56.54#ibcon#*before write, iclass 26, count 0 2006.285.15:57:56.54#ibcon#enter sib2, iclass 26, count 0 2006.285.15:57:56.55#ibcon#flushed, iclass 26, count 0 2006.285.15:57:56.55#ibcon#about to write, iclass 26, count 0 2006.285.15:57:56.55#ibcon#wrote, iclass 26, count 0 2006.285.15:57:56.55#ibcon#about to read 3, iclass 26, count 0 2006.285.15:57:56.57#ibcon#read 3, iclass 26, count 0 2006.285.15:57:56.57#ibcon#about to read 4, iclass 26, count 0 2006.285.15:57:56.57#ibcon#read 4, iclass 26, count 0 2006.285.15:57:56.57#ibcon#about to read 5, iclass 26, count 0 2006.285.15:57:56.57#ibcon#read 5, iclass 26, count 0 2006.285.15:57:56.57#ibcon#about to read 6, iclass 26, count 0 2006.285.15:57:56.57#ibcon#read 6, iclass 26, count 0 2006.285.15:57:56.57#ibcon#end of sib2, iclass 26, count 0 2006.285.15:57:56.57#ibcon#*after write, iclass 26, count 0 2006.285.15:57:56.57#ibcon#*before return 0, iclass 26, count 0 2006.285.15:57:56.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:57:56.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.15:57:56.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.15:57:56.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.15:57:56.58$setupk4/ifdk4 2006.285.15:57:56.58$ifdk4/lo= 2006.285.15:57:56.58$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.15:57:56.58$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.15:57:56.58$ifdk4/patch= 2006.285.15:57:56.58$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.15:57:56.58$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.15:57:56.58$setupk4/!*+20s 2006.285.15:58:05.93#abcon#<5=/01 0.8 2.6 18.67 931014.9\r\n> 2006.285.15:58:05.95#abcon#{5=INTERFACE CLEAR} 2006.285.15:58:06.01#abcon#[5=S1D000X0/0*\r\n] 2006.285.15:58:10.32$setupk4/"tpicd 2006.285.15:58:10.32$setupk4/echo=off 2006.285.15:58:10.33$setupk4/xlog=off 2006.285.15:58:10.33:!2006.285.15:59:31 2006.285.15:58:14.14#trakl#Source acquired 2006.285.15:58:16.15#flagr#flagr/antenna,acquired 2006.285.15:59:31.02:preob 2006.285.15:59:32.15/onsource/TRACKING 2006.285.15:59:32.15:!2006.285.15:59:41 2006.285.15:59:41.01:"tape 2006.285.15:59:41.02:"st=record 2006.285.15:59:41.02:data_valid=on 2006.285.15:59:41.02:midob 2006.285.15:59:42.15/onsource/TRACKING 2006.285.15:59:42.15/wx/18.65,1014.9,92 2006.285.15:59:42.26/cable/+6.5002E-03 2006.285.15:59:43.35/va/01,07,usb,yes,32,34 2006.285.15:59:43.35/va/02,06,usb,yes,32,32 2006.285.15:59:43.35/va/03,07,usb,yes,31,33 2006.285.15:59:43.35/va/04,06,usb,yes,33,34 2006.285.15:59:43.35/va/05,03,usb,yes,32,33 2006.285.15:59:43.35/va/06,04,usb,yes,29,28 2006.285.15:59:43.35/va/07,04,usb,yes,29,30 2006.285.15:59:43.35/va/08,03,usb,yes,30,37 2006.285.15:59:43.58/valo/01,524.99,yes,locked 2006.285.15:59:43.58/valo/02,534.99,yes,locked 2006.285.15:59:43.58/valo/03,564.99,yes,locked 2006.285.15:59:43.58/valo/04,624.99,yes,locked 2006.285.15:59:43.58/valo/05,734.99,yes,locked 2006.285.15:59:43.58/valo/06,814.99,yes,locked 2006.285.15:59:43.58/valo/07,864.99,yes,locked 2006.285.15:59:43.58/valo/08,884.99,yes,locked 2006.285.15:59:44.67/vb/01,04,usb,yes,30,28 2006.285.15:59:44.67/vb/02,05,usb,yes,28,28 2006.285.15:59:44.67/vb/03,04,usb,yes,29,32 2006.285.15:59:44.67/vb/04,05,usb,yes,29,28 2006.285.15:59:44.67/vb/05,04,usb,yes,26,28 2006.285.15:59:44.67/vb/06,03,usb,yes,37,33 2006.285.15:59:44.67/vb/07,04,usb,yes,30,30 2006.285.15:59:44.67/vb/08,04,usb,yes,27,31 2006.285.15:59:44.90/vblo/01,629.99,yes,locked 2006.285.15:59:44.90/vblo/02,634.99,yes,locked 2006.285.15:59:44.90/vblo/03,649.99,yes,locked 2006.285.15:59:44.90/vblo/04,679.99,yes,locked 2006.285.15:59:44.90/vblo/05,709.99,yes,locked 2006.285.15:59:44.90/vblo/06,719.99,yes,locked 2006.285.15:59:44.90/vblo/07,734.99,yes,locked 2006.285.15:59:44.90/vblo/08,744.99,yes,locked 2006.285.15:59:45.05/vabw/8 2006.285.15:59:45.20/vbbw/8 2006.285.15:59:45.29/xfe/off,on,12.2 2006.285.15:59:45.68/ifatt/23,28,28,28 2006.285.15:59:46.07/fmout-gps/S +2.64E-07 2006.285.15:59:46.09:!2006.285.16:04:51 2006.285.16:04:51.00:data_valid=off 2006.285.16:04:51.00:"et 2006.285.16:04:51.00:!+3s 2006.285.16:04:54.01:"tape 2006.285.16:04:54.01:postob 2006.285.16:04:54.19/cable/+6.5003E-03 2006.285.16:04:54.19/wx/18.66,1014.9,91 2006.285.16:04:55.08/fmout-gps/S +2.74E-07 2006.285.16:04:55.08:scan_name=285-1609,jd0610,500 2006.285.16:04:55.08:source=0804+499,080839.67,495036.5,2000.0,cw 2006.285.16:04:55.14#flagr#flagr/antenna,new-source 2006.285.16:04:56.14:checkk5 2006.285.16:04:56.59/chk_autoobs//k5ts1/ autoobs is running! 2006.285.16:04:57.02/chk_autoobs//k5ts2/ autoobs is running! 2006.285.16:04:57.57/chk_autoobs//k5ts3/ autoobs is running! 2006.285.16:04:57.98/chk_autoobs//k5ts4/ autoobs is running! 2006.285.16:04:58.46/chk_obsdata//k5ts1/T2851559??a.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.285.16:04:58.84/chk_obsdata//k5ts2/T2851559??b.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.285.16:04:59.40/chk_obsdata//k5ts3/T2851559??c.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.285.16:04:59.87/chk_obsdata//k5ts4/T2851559??d.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.285.16:05:00.64/k5log//k5ts1_log_newline 2006.285.16:05:01.48/k5log//k5ts2_log_newline 2006.285.16:05:02.30/k5log//k5ts3_log_newline 2006.285.16:05:03.03/k5log//k5ts4_log_newline 2006.285.16:05:03.05/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.16:05:03.05:setupk4=1 2006.285.16:05:03.05$setupk4/echo=on 2006.285.16:05:03.05$setupk4/pcalon 2006.285.16:05:03.05$pcalon/"no phase cal control is implemented here 2006.285.16:05:03.05$setupk4/"tpicd=stop 2006.285.16:05:03.05$setupk4/"rec=synch_on 2006.285.16:05:03.05$setupk4/"rec_mode=128 2006.285.16:05:03.05$setupk4/!* 2006.285.16:05:03.05$setupk4/recpk4 2006.285.16:05:03.05$recpk4/recpatch= 2006.285.16:05:03.05$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.16:05:03.05$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.16:05:03.06$setupk4/vck44 2006.285.16:05:03.06$vck44/valo=1,524.99 2006.285.16:05:03.06#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.16:05:03.06#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.16:05:03.06#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:03.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:05:03.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:05:03.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:05:03.06#ibcon#enter wrdev, iclass 19, count 0 2006.285.16:05:03.06#ibcon#first serial, iclass 19, count 0 2006.285.16:05:03.06#ibcon#enter sib2, iclass 19, count 0 2006.285.16:05:03.06#ibcon#flushed, iclass 19, count 0 2006.285.16:05:03.06#ibcon#about to write, iclass 19, count 0 2006.285.16:05:03.06#ibcon#wrote, iclass 19, count 0 2006.285.16:05:03.06#ibcon#about to read 3, iclass 19, count 0 2006.285.16:05:03.07#ibcon#read 3, iclass 19, count 0 2006.285.16:05:03.07#ibcon#about to read 4, iclass 19, count 0 2006.285.16:05:03.07#ibcon#read 4, iclass 19, count 0 2006.285.16:05:03.07#ibcon#about to read 5, iclass 19, count 0 2006.285.16:05:03.07#ibcon#read 5, iclass 19, count 0 2006.285.16:05:03.07#ibcon#about to read 6, iclass 19, count 0 2006.285.16:05:03.07#ibcon#read 6, iclass 19, count 0 2006.285.16:05:03.07#ibcon#end of sib2, iclass 19, count 0 2006.285.16:05:03.07#ibcon#*mode == 0, iclass 19, count 0 2006.285.16:05:03.07#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.16:05:03.07#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.16:05:03.07#ibcon#*before write, iclass 19, count 0 2006.285.16:05:03.07#ibcon#enter sib2, iclass 19, count 0 2006.285.16:05:03.07#ibcon#flushed, iclass 19, count 0 2006.285.16:05:03.07#ibcon#about to write, iclass 19, count 0 2006.285.16:05:03.07#ibcon#wrote, iclass 19, count 0 2006.285.16:05:03.07#ibcon#about to read 3, iclass 19, count 0 2006.285.16:05:03.12#ibcon#read 3, iclass 19, count 0 2006.285.16:05:03.12#ibcon#about to read 4, iclass 19, count 0 2006.285.16:05:03.12#ibcon#read 4, iclass 19, count 0 2006.285.16:05:03.12#ibcon#about to read 5, iclass 19, count 0 2006.285.16:05:03.12#ibcon#read 5, iclass 19, count 0 2006.285.16:05:03.12#ibcon#about to read 6, iclass 19, count 0 2006.285.16:05:03.12#ibcon#read 6, iclass 19, count 0 2006.285.16:05:03.12#ibcon#end of sib2, iclass 19, count 0 2006.285.16:05:03.12#ibcon#*after write, iclass 19, count 0 2006.285.16:05:03.12#ibcon#*before return 0, iclass 19, count 0 2006.285.16:05:03.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:05:03.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:05:03.12#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.16:05:03.12#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.16:05:03.12$vck44/va=1,7 2006.285.16:05:03.12#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.16:05:03.12#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.16:05:03.12#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:03.12#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:05:03.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:05:03.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:05:03.12#ibcon#enter wrdev, iclass 21, count 2 2006.285.16:05:03.12#ibcon#first serial, iclass 21, count 2 2006.285.16:05:03.12#ibcon#enter sib2, iclass 21, count 2 2006.285.16:05:03.12#ibcon#flushed, iclass 21, count 2 2006.285.16:05:03.12#ibcon#about to write, iclass 21, count 2 2006.285.16:05:03.12#ibcon#wrote, iclass 21, count 2 2006.285.16:05:03.12#ibcon#about to read 3, iclass 21, count 2 2006.285.16:05:03.14#ibcon#read 3, iclass 21, count 2 2006.285.16:05:03.14#ibcon#about to read 4, iclass 21, count 2 2006.285.16:05:03.14#ibcon#read 4, iclass 21, count 2 2006.285.16:05:03.14#ibcon#about to read 5, iclass 21, count 2 2006.285.16:05:03.14#ibcon#read 5, iclass 21, count 2 2006.285.16:05:03.14#ibcon#about to read 6, iclass 21, count 2 2006.285.16:05:03.14#ibcon#read 6, iclass 21, count 2 2006.285.16:05:03.14#ibcon#end of sib2, iclass 21, count 2 2006.285.16:05:03.14#ibcon#*mode == 0, iclass 21, count 2 2006.285.16:05:03.14#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.16:05:03.14#ibcon#[25=AT01-07\r\n] 2006.285.16:05:03.14#ibcon#*before write, iclass 21, count 2 2006.285.16:05:03.14#ibcon#enter sib2, iclass 21, count 2 2006.285.16:05:03.14#ibcon#flushed, iclass 21, count 2 2006.285.16:05:03.14#ibcon#about to write, iclass 21, count 2 2006.285.16:05:03.14#ibcon#wrote, iclass 21, count 2 2006.285.16:05:03.14#ibcon#about to read 3, iclass 21, count 2 2006.285.16:05:03.17#ibcon#read 3, iclass 21, count 2 2006.285.16:05:03.17#ibcon#about to read 4, iclass 21, count 2 2006.285.16:05:03.17#ibcon#read 4, iclass 21, count 2 2006.285.16:05:03.17#ibcon#about to read 5, iclass 21, count 2 2006.285.16:05:03.17#ibcon#read 5, iclass 21, count 2 2006.285.16:05:03.17#ibcon#about to read 6, iclass 21, count 2 2006.285.16:05:03.17#ibcon#read 6, iclass 21, count 2 2006.285.16:05:03.17#ibcon#end of sib2, iclass 21, count 2 2006.285.16:05:03.17#ibcon#*after write, iclass 21, count 2 2006.285.16:05:03.17#ibcon#*before return 0, iclass 21, count 2 2006.285.16:05:03.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:05:03.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:05:03.17#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.16:05:03.17#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:03.17#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:05:03.29#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:05:03.29#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:05:03.29#ibcon#enter wrdev, iclass 21, count 0 2006.285.16:05:03.29#ibcon#first serial, iclass 21, count 0 2006.285.16:05:03.29#ibcon#enter sib2, iclass 21, count 0 2006.285.16:05:03.29#ibcon#flushed, iclass 21, count 0 2006.285.16:05:03.29#ibcon#about to write, iclass 21, count 0 2006.285.16:05:03.29#ibcon#wrote, iclass 21, count 0 2006.285.16:05:03.29#ibcon#about to read 3, iclass 21, count 0 2006.285.16:05:03.31#ibcon#read 3, iclass 21, count 0 2006.285.16:05:03.31#ibcon#about to read 4, iclass 21, count 0 2006.285.16:05:03.31#ibcon#read 4, iclass 21, count 0 2006.285.16:05:03.31#ibcon#about to read 5, iclass 21, count 0 2006.285.16:05:03.31#ibcon#read 5, iclass 21, count 0 2006.285.16:05:03.31#ibcon#about to read 6, iclass 21, count 0 2006.285.16:05:03.31#ibcon#read 6, iclass 21, count 0 2006.285.16:05:03.31#ibcon#end of sib2, iclass 21, count 0 2006.285.16:05:03.31#ibcon#*mode == 0, iclass 21, count 0 2006.285.16:05:03.31#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.16:05:03.31#ibcon#[25=USB\r\n] 2006.285.16:05:03.31#ibcon#*before write, iclass 21, count 0 2006.285.16:05:03.31#ibcon#enter sib2, iclass 21, count 0 2006.285.16:05:03.31#ibcon#flushed, iclass 21, count 0 2006.285.16:05:03.31#ibcon#about to write, iclass 21, count 0 2006.285.16:05:03.31#ibcon#wrote, iclass 21, count 0 2006.285.16:05:03.31#ibcon#about to read 3, iclass 21, count 0 2006.285.16:05:03.34#ibcon#read 3, iclass 21, count 0 2006.285.16:05:03.34#ibcon#about to read 4, iclass 21, count 0 2006.285.16:05:03.34#ibcon#read 4, iclass 21, count 0 2006.285.16:05:03.34#ibcon#about to read 5, iclass 21, count 0 2006.285.16:05:03.34#ibcon#read 5, iclass 21, count 0 2006.285.16:05:03.34#ibcon#about to read 6, iclass 21, count 0 2006.285.16:05:03.34#ibcon#read 6, iclass 21, count 0 2006.285.16:05:03.34#ibcon#end of sib2, iclass 21, count 0 2006.285.16:05:03.34#ibcon#*after write, iclass 21, count 0 2006.285.16:05:03.34#ibcon#*before return 0, iclass 21, count 0 2006.285.16:05:03.34#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:05:03.34#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:05:03.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.16:05:03.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.16:05:03.34$vck44/valo=2,534.99 2006.285.16:05:03.34#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.16:05:03.34#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.16:05:03.34#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:03.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:05:03.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:05:03.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:05:03.34#ibcon#enter wrdev, iclass 23, count 0 2006.285.16:05:03.34#ibcon#first serial, iclass 23, count 0 2006.285.16:05:03.34#ibcon#enter sib2, iclass 23, count 0 2006.285.16:05:03.34#ibcon#flushed, iclass 23, count 0 2006.285.16:05:03.34#ibcon#about to write, iclass 23, count 0 2006.285.16:05:03.34#ibcon#wrote, iclass 23, count 0 2006.285.16:05:03.34#ibcon#about to read 3, iclass 23, count 0 2006.285.16:05:03.36#ibcon#read 3, iclass 23, count 0 2006.285.16:05:03.65#ibcon#about to read 4, iclass 23, count 0 2006.285.16:05:03.65#ibcon#read 4, iclass 23, count 0 2006.285.16:05:03.65#ibcon#about to read 5, iclass 23, count 0 2006.285.16:05:03.65#ibcon#read 5, iclass 23, count 0 2006.285.16:05:03.65#ibcon#about to read 6, iclass 23, count 0 2006.285.16:05:03.65#ibcon#read 6, iclass 23, count 0 2006.285.16:05:03.65#ibcon#end of sib2, iclass 23, count 0 2006.285.16:05:03.65#ibcon#*mode == 0, iclass 23, count 0 2006.285.16:05:03.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.16:05:03.65#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.16:05:03.65#ibcon#*before write, iclass 23, count 0 2006.285.16:05:03.65#ibcon#enter sib2, iclass 23, count 0 2006.285.16:05:03.65#ibcon#flushed, iclass 23, count 0 2006.285.16:05:03.65#ibcon#about to write, iclass 23, count 0 2006.285.16:05:03.66#ibcon#wrote, iclass 23, count 0 2006.285.16:05:03.66#ibcon#about to read 3, iclass 23, count 0 2006.285.16:05:03.69#ibcon#read 3, iclass 23, count 0 2006.285.16:05:03.69#ibcon#about to read 4, iclass 23, count 0 2006.285.16:05:03.69#ibcon#read 4, iclass 23, count 0 2006.285.16:05:03.69#ibcon#about to read 5, iclass 23, count 0 2006.285.16:05:03.69#ibcon#read 5, iclass 23, count 0 2006.285.16:05:03.69#ibcon#about to read 6, iclass 23, count 0 2006.285.16:05:03.69#ibcon#read 6, iclass 23, count 0 2006.285.16:05:03.69#ibcon#end of sib2, iclass 23, count 0 2006.285.16:05:03.69#ibcon#*after write, iclass 23, count 0 2006.285.16:05:03.69#ibcon#*before return 0, iclass 23, count 0 2006.285.16:05:03.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:05:03.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:05:03.69#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.16:05:03.69#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.16:05:03.69$vck44/va=2,6 2006.285.16:05:03.69#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.16:05:03.69#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.16:05:03.69#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:03.69#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:05:03.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:05:03.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:05:03.69#ibcon#enter wrdev, iclass 25, count 2 2006.285.16:05:03.69#ibcon#first serial, iclass 25, count 2 2006.285.16:05:03.69#ibcon#enter sib2, iclass 25, count 2 2006.285.16:05:03.69#ibcon#flushed, iclass 25, count 2 2006.285.16:05:03.69#ibcon#about to write, iclass 25, count 2 2006.285.16:05:03.69#ibcon#wrote, iclass 25, count 2 2006.285.16:05:03.69#ibcon#about to read 3, iclass 25, count 2 2006.285.16:05:03.71#ibcon#read 3, iclass 25, count 2 2006.285.16:05:03.71#ibcon#about to read 4, iclass 25, count 2 2006.285.16:05:03.71#ibcon#read 4, iclass 25, count 2 2006.285.16:05:03.71#ibcon#about to read 5, iclass 25, count 2 2006.285.16:05:03.71#ibcon#read 5, iclass 25, count 2 2006.285.16:05:03.71#ibcon#about to read 6, iclass 25, count 2 2006.285.16:05:03.71#ibcon#read 6, iclass 25, count 2 2006.285.16:05:03.71#ibcon#end of sib2, iclass 25, count 2 2006.285.16:05:03.71#ibcon#*mode == 0, iclass 25, count 2 2006.285.16:05:03.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.16:05:03.71#ibcon#[25=AT02-06\r\n] 2006.285.16:05:03.71#ibcon#*before write, iclass 25, count 2 2006.285.16:05:03.71#ibcon#enter sib2, iclass 25, count 2 2006.285.16:05:03.71#ibcon#flushed, iclass 25, count 2 2006.285.16:05:03.71#ibcon#about to write, iclass 25, count 2 2006.285.16:05:03.71#ibcon#wrote, iclass 25, count 2 2006.285.16:05:03.71#ibcon#about to read 3, iclass 25, count 2 2006.285.16:05:03.74#ibcon#read 3, iclass 25, count 2 2006.285.16:05:03.74#ibcon#about to read 4, iclass 25, count 2 2006.285.16:05:03.74#ibcon#read 4, iclass 25, count 2 2006.285.16:05:03.74#ibcon#about to read 5, iclass 25, count 2 2006.285.16:05:03.74#ibcon#read 5, iclass 25, count 2 2006.285.16:05:03.74#ibcon#about to read 6, iclass 25, count 2 2006.285.16:05:03.74#ibcon#read 6, iclass 25, count 2 2006.285.16:05:03.74#ibcon#end of sib2, iclass 25, count 2 2006.285.16:05:03.74#ibcon#*after write, iclass 25, count 2 2006.285.16:05:03.74#ibcon#*before return 0, iclass 25, count 2 2006.285.16:05:03.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:05:03.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:05:03.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.16:05:03.74#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:03.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:05:03.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:05:03.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:05:03.86#ibcon#enter wrdev, iclass 25, count 0 2006.285.16:05:03.86#ibcon#first serial, iclass 25, count 0 2006.285.16:05:03.86#ibcon#enter sib2, iclass 25, count 0 2006.285.16:05:03.86#ibcon#flushed, iclass 25, count 0 2006.285.16:05:03.86#ibcon#about to write, iclass 25, count 0 2006.285.16:05:03.86#ibcon#wrote, iclass 25, count 0 2006.285.16:05:03.86#ibcon#about to read 3, iclass 25, count 0 2006.285.16:05:03.88#ibcon#read 3, iclass 25, count 0 2006.285.16:05:03.88#ibcon#about to read 4, iclass 25, count 0 2006.285.16:05:03.88#ibcon#read 4, iclass 25, count 0 2006.285.16:05:03.88#ibcon#about to read 5, iclass 25, count 0 2006.285.16:05:03.88#ibcon#read 5, iclass 25, count 0 2006.285.16:05:03.88#ibcon#about to read 6, iclass 25, count 0 2006.285.16:05:03.88#ibcon#read 6, iclass 25, count 0 2006.285.16:05:03.88#ibcon#end of sib2, iclass 25, count 0 2006.285.16:05:03.88#ibcon#*mode == 0, iclass 25, count 0 2006.285.16:05:03.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.16:05:03.88#ibcon#[25=USB\r\n] 2006.285.16:05:03.88#ibcon#*before write, iclass 25, count 0 2006.285.16:05:03.88#ibcon#enter sib2, iclass 25, count 0 2006.285.16:05:03.88#ibcon#flushed, iclass 25, count 0 2006.285.16:05:03.88#ibcon#about to write, iclass 25, count 0 2006.285.16:05:03.88#ibcon#wrote, iclass 25, count 0 2006.285.16:05:03.88#ibcon#about to read 3, iclass 25, count 0 2006.285.16:05:03.91#ibcon#read 3, iclass 25, count 0 2006.285.16:05:03.91#ibcon#about to read 4, iclass 25, count 0 2006.285.16:05:03.91#ibcon#read 4, iclass 25, count 0 2006.285.16:05:03.91#ibcon#about to read 5, iclass 25, count 0 2006.285.16:05:03.91#ibcon#read 5, iclass 25, count 0 2006.285.16:05:03.91#ibcon#about to read 6, iclass 25, count 0 2006.285.16:05:03.91#ibcon#read 6, iclass 25, count 0 2006.285.16:05:03.91#ibcon#end of sib2, iclass 25, count 0 2006.285.16:05:03.91#ibcon#*after write, iclass 25, count 0 2006.285.16:05:03.91#ibcon#*before return 0, iclass 25, count 0 2006.285.16:05:03.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:05:03.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:05:03.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.16:05:03.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.16:05:03.91$vck44/valo=3,564.99 2006.285.16:05:03.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.16:05:03.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.16:05:03.91#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:03.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:05:03.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:05:03.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:05:03.91#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:05:03.91#ibcon#first serial, iclass 27, count 0 2006.285.16:05:03.91#ibcon#enter sib2, iclass 27, count 0 2006.285.16:05:03.91#ibcon#flushed, iclass 27, count 0 2006.285.16:05:03.91#ibcon#about to write, iclass 27, count 0 2006.285.16:05:03.91#ibcon#wrote, iclass 27, count 0 2006.285.16:05:03.91#ibcon#about to read 3, iclass 27, count 0 2006.285.16:05:03.93#ibcon#read 3, iclass 27, count 0 2006.285.16:05:04.10#ibcon#about to read 4, iclass 27, count 0 2006.285.16:05:04.10#ibcon#read 4, iclass 27, count 0 2006.285.16:05:04.10#ibcon#about to read 5, iclass 27, count 0 2006.285.16:05:04.10#ibcon#read 5, iclass 27, count 0 2006.285.16:05:04.10#ibcon#about to read 6, iclass 27, count 0 2006.285.16:05:04.10#ibcon#read 6, iclass 27, count 0 2006.285.16:05:04.10#ibcon#end of sib2, iclass 27, count 0 2006.285.16:05:04.10#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:05:04.10#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:05:04.10#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.16:05:04.10#ibcon#*before write, iclass 27, count 0 2006.285.16:05:04.10#ibcon#enter sib2, iclass 27, count 0 2006.285.16:05:04.10#ibcon#flushed, iclass 27, count 0 2006.285.16:05:04.10#ibcon#about to write, iclass 27, count 0 2006.285.16:05:04.10#ibcon#wrote, iclass 27, count 0 2006.285.16:05:04.10#ibcon#about to read 3, iclass 27, count 0 2006.285.16:05:04.13#ibcon#read 3, iclass 27, count 0 2006.285.16:05:04.13#ibcon#about to read 4, iclass 27, count 0 2006.285.16:05:04.13#ibcon#read 4, iclass 27, count 0 2006.285.16:05:04.13#ibcon#about to read 5, iclass 27, count 0 2006.285.16:05:04.13#ibcon#read 5, iclass 27, count 0 2006.285.16:05:04.13#ibcon#about to read 6, iclass 27, count 0 2006.285.16:05:04.13#ibcon#read 6, iclass 27, count 0 2006.285.16:05:04.13#ibcon#end of sib2, iclass 27, count 0 2006.285.16:05:04.13#ibcon#*after write, iclass 27, count 0 2006.285.16:05:04.13#ibcon#*before return 0, iclass 27, count 0 2006.285.16:05:04.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:05:04.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:05:04.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:05:04.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:05:04.13$vck44/va=3,7 2006.285.16:05:04.13#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.16:05:04.13#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.16:05:04.13#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:04.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:05:04.13#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:05:04.13#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:05:04.13#ibcon#enter wrdev, iclass 29, count 2 2006.285.16:05:04.13#ibcon#first serial, iclass 29, count 2 2006.285.16:05:04.13#ibcon#enter sib2, iclass 29, count 2 2006.285.16:05:04.13#ibcon#flushed, iclass 29, count 2 2006.285.16:05:04.13#ibcon#about to write, iclass 29, count 2 2006.285.16:05:04.13#ibcon#wrote, iclass 29, count 2 2006.285.16:05:04.13#ibcon#about to read 3, iclass 29, count 2 2006.285.16:05:04.15#ibcon#read 3, iclass 29, count 2 2006.285.16:05:04.15#ibcon#about to read 4, iclass 29, count 2 2006.285.16:05:04.15#ibcon#read 4, iclass 29, count 2 2006.285.16:05:04.15#ibcon#about to read 5, iclass 29, count 2 2006.285.16:05:04.15#ibcon#read 5, iclass 29, count 2 2006.285.16:05:04.15#ibcon#about to read 6, iclass 29, count 2 2006.285.16:05:04.15#ibcon#read 6, iclass 29, count 2 2006.285.16:05:04.15#ibcon#end of sib2, iclass 29, count 2 2006.285.16:05:04.15#ibcon#*mode == 0, iclass 29, count 2 2006.285.16:05:04.15#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.16:05:04.15#ibcon#[25=AT03-07\r\n] 2006.285.16:05:04.15#ibcon#*before write, iclass 29, count 2 2006.285.16:05:04.15#ibcon#enter sib2, iclass 29, count 2 2006.285.16:05:04.15#ibcon#flushed, iclass 29, count 2 2006.285.16:05:04.15#ibcon#about to write, iclass 29, count 2 2006.285.16:05:04.15#ibcon#wrote, iclass 29, count 2 2006.285.16:05:04.15#ibcon#about to read 3, iclass 29, count 2 2006.285.16:05:04.18#ibcon#read 3, iclass 29, count 2 2006.285.16:05:04.18#ibcon#about to read 4, iclass 29, count 2 2006.285.16:05:04.18#ibcon#read 4, iclass 29, count 2 2006.285.16:05:04.18#ibcon#about to read 5, iclass 29, count 2 2006.285.16:05:04.18#ibcon#read 5, iclass 29, count 2 2006.285.16:05:04.18#ibcon#about to read 6, iclass 29, count 2 2006.285.16:05:04.18#ibcon#read 6, iclass 29, count 2 2006.285.16:05:04.18#ibcon#end of sib2, iclass 29, count 2 2006.285.16:05:04.18#ibcon#*after write, iclass 29, count 2 2006.285.16:05:04.18#ibcon#*before return 0, iclass 29, count 2 2006.285.16:05:04.18#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:05:04.18#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:05:04.18#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.16:05:04.18#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:04.18#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:05:04.30#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:05:04.30#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:05:04.30#ibcon#enter wrdev, iclass 29, count 0 2006.285.16:05:04.30#ibcon#first serial, iclass 29, count 0 2006.285.16:05:04.30#ibcon#enter sib2, iclass 29, count 0 2006.285.16:05:04.30#ibcon#flushed, iclass 29, count 0 2006.285.16:05:04.30#ibcon#about to write, iclass 29, count 0 2006.285.16:05:04.30#ibcon#wrote, iclass 29, count 0 2006.285.16:05:04.30#ibcon#about to read 3, iclass 29, count 0 2006.285.16:05:04.32#ibcon#read 3, iclass 29, count 0 2006.285.16:05:04.32#ibcon#about to read 4, iclass 29, count 0 2006.285.16:05:04.32#ibcon#read 4, iclass 29, count 0 2006.285.16:05:04.32#ibcon#about to read 5, iclass 29, count 0 2006.285.16:05:04.32#ibcon#read 5, iclass 29, count 0 2006.285.16:05:04.32#ibcon#about to read 6, iclass 29, count 0 2006.285.16:05:04.32#ibcon#read 6, iclass 29, count 0 2006.285.16:05:04.32#ibcon#end of sib2, iclass 29, count 0 2006.285.16:05:04.32#ibcon#*mode == 0, iclass 29, count 0 2006.285.16:05:04.32#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.16:05:04.32#ibcon#[25=USB\r\n] 2006.285.16:05:04.32#ibcon#*before write, iclass 29, count 0 2006.285.16:05:04.32#ibcon#enter sib2, iclass 29, count 0 2006.285.16:05:04.32#ibcon#flushed, iclass 29, count 0 2006.285.16:05:04.32#ibcon#about to write, iclass 29, count 0 2006.285.16:05:04.32#ibcon#wrote, iclass 29, count 0 2006.285.16:05:04.32#ibcon#about to read 3, iclass 29, count 0 2006.285.16:05:04.35#ibcon#read 3, iclass 29, count 0 2006.285.16:05:04.35#ibcon#about to read 4, iclass 29, count 0 2006.285.16:05:04.35#ibcon#read 4, iclass 29, count 0 2006.285.16:05:04.35#ibcon#about to read 5, iclass 29, count 0 2006.285.16:05:04.35#ibcon#read 5, iclass 29, count 0 2006.285.16:05:04.35#ibcon#about to read 6, iclass 29, count 0 2006.285.16:05:04.35#ibcon#read 6, iclass 29, count 0 2006.285.16:05:04.35#ibcon#end of sib2, iclass 29, count 0 2006.285.16:05:04.35#ibcon#*after write, iclass 29, count 0 2006.285.16:05:04.35#ibcon#*before return 0, iclass 29, count 0 2006.285.16:05:04.35#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:05:04.35#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:05:04.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.16:05:04.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.16:05:04.35$vck44/valo=4,624.99 2006.285.16:05:04.35#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.16:05:04.35#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.16:05:04.35#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:04.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:05:04.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:05:04.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:05:04.35#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:05:04.35#ibcon#first serial, iclass 31, count 0 2006.285.16:05:04.35#ibcon#enter sib2, iclass 31, count 0 2006.285.16:05:04.35#ibcon#flushed, iclass 31, count 0 2006.285.16:05:04.35#ibcon#about to write, iclass 31, count 0 2006.285.16:05:04.35#ibcon#wrote, iclass 31, count 0 2006.285.16:05:04.35#ibcon#about to read 3, iclass 31, count 0 2006.285.16:05:04.37#ibcon#read 3, iclass 31, count 0 2006.285.16:05:04.49#ibcon#about to read 4, iclass 31, count 0 2006.285.16:05:04.49#ibcon#read 4, iclass 31, count 0 2006.285.16:05:04.49#ibcon#about to read 5, iclass 31, count 0 2006.285.16:05:04.49#ibcon#read 5, iclass 31, count 0 2006.285.16:05:04.49#ibcon#about to read 6, iclass 31, count 0 2006.285.16:05:04.49#ibcon#read 6, iclass 31, count 0 2006.285.16:05:04.49#ibcon#end of sib2, iclass 31, count 0 2006.285.16:05:04.49#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:05:04.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:05:04.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.16:05:04.49#ibcon#*before write, iclass 31, count 0 2006.285.16:05:04.49#ibcon#enter sib2, iclass 31, count 0 2006.285.16:05:04.49#ibcon#flushed, iclass 31, count 0 2006.285.16:05:04.49#ibcon#about to write, iclass 31, count 0 2006.285.16:05:04.49#ibcon#wrote, iclass 31, count 0 2006.285.16:05:04.49#ibcon#about to read 3, iclass 31, count 0 2006.285.16:05:04.53#ibcon#read 3, iclass 31, count 0 2006.285.16:05:04.53#ibcon#about to read 4, iclass 31, count 0 2006.285.16:05:04.53#ibcon#read 4, iclass 31, count 0 2006.285.16:05:04.53#ibcon#about to read 5, iclass 31, count 0 2006.285.16:05:04.53#ibcon#read 5, iclass 31, count 0 2006.285.16:05:04.53#ibcon#about to read 6, iclass 31, count 0 2006.285.16:05:04.53#ibcon#read 6, iclass 31, count 0 2006.285.16:05:04.53#ibcon#end of sib2, iclass 31, count 0 2006.285.16:05:04.53#ibcon#*after write, iclass 31, count 0 2006.285.16:05:04.53#ibcon#*before return 0, iclass 31, count 0 2006.285.16:05:04.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:05:04.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:05:04.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:05:04.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:05:04.53$vck44/va=4,6 2006.285.16:05:04.53#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.16:05:04.53#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.16:05:04.53#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:04.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:05:04.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:05:04.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:05:04.53#ibcon#enter wrdev, iclass 33, count 2 2006.285.16:05:04.53#ibcon#first serial, iclass 33, count 2 2006.285.16:05:04.53#ibcon#enter sib2, iclass 33, count 2 2006.285.16:05:04.53#ibcon#flushed, iclass 33, count 2 2006.285.16:05:04.53#ibcon#about to write, iclass 33, count 2 2006.285.16:05:04.53#ibcon#wrote, iclass 33, count 2 2006.285.16:05:04.53#ibcon#about to read 3, iclass 33, count 2 2006.285.16:05:04.55#ibcon#read 3, iclass 33, count 2 2006.285.16:05:04.55#ibcon#about to read 4, iclass 33, count 2 2006.285.16:05:04.55#ibcon#read 4, iclass 33, count 2 2006.285.16:05:04.55#ibcon#about to read 5, iclass 33, count 2 2006.285.16:05:04.55#ibcon#read 5, iclass 33, count 2 2006.285.16:05:04.55#ibcon#about to read 6, iclass 33, count 2 2006.285.16:05:04.55#ibcon#read 6, iclass 33, count 2 2006.285.16:05:04.55#ibcon#end of sib2, iclass 33, count 2 2006.285.16:05:04.55#ibcon#*mode == 0, iclass 33, count 2 2006.285.16:05:04.55#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.16:05:04.55#ibcon#[25=AT04-06\r\n] 2006.285.16:05:04.55#ibcon#*before write, iclass 33, count 2 2006.285.16:05:04.55#ibcon#enter sib2, iclass 33, count 2 2006.285.16:05:04.55#ibcon#flushed, iclass 33, count 2 2006.285.16:05:04.55#ibcon#about to write, iclass 33, count 2 2006.285.16:05:04.55#ibcon#wrote, iclass 33, count 2 2006.285.16:05:04.55#ibcon#about to read 3, iclass 33, count 2 2006.285.16:05:04.58#ibcon#read 3, iclass 33, count 2 2006.285.16:05:04.58#ibcon#about to read 4, iclass 33, count 2 2006.285.16:05:04.58#ibcon#read 4, iclass 33, count 2 2006.285.16:05:04.58#ibcon#about to read 5, iclass 33, count 2 2006.285.16:05:04.58#ibcon#read 5, iclass 33, count 2 2006.285.16:05:04.58#ibcon#about to read 6, iclass 33, count 2 2006.285.16:05:04.58#ibcon#read 6, iclass 33, count 2 2006.285.16:05:04.58#ibcon#end of sib2, iclass 33, count 2 2006.285.16:05:04.58#ibcon#*after write, iclass 33, count 2 2006.285.16:05:04.58#ibcon#*before return 0, iclass 33, count 2 2006.285.16:05:04.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:05:04.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:05:04.58#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.16:05:04.58#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:04.58#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:05:04.70#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:05:04.70#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:05:04.70#ibcon#enter wrdev, iclass 33, count 0 2006.285.16:05:04.70#ibcon#first serial, iclass 33, count 0 2006.285.16:05:04.70#ibcon#enter sib2, iclass 33, count 0 2006.285.16:05:04.70#ibcon#flushed, iclass 33, count 0 2006.285.16:05:04.70#ibcon#about to write, iclass 33, count 0 2006.285.16:05:04.70#ibcon#wrote, iclass 33, count 0 2006.285.16:05:04.70#ibcon#about to read 3, iclass 33, count 0 2006.285.16:05:04.72#ibcon#read 3, iclass 33, count 0 2006.285.16:05:04.72#ibcon#about to read 4, iclass 33, count 0 2006.285.16:05:04.72#ibcon#read 4, iclass 33, count 0 2006.285.16:05:04.72#ibcon#about to read 5, iclass 33, count 0 2006.285.16:05:04.72#ibcon#read 5, iclass 33, count 0 2006.285.16:05:04.72#ibcon#about to read 6, iclass 33, count 0 2006.285.16:05:04.72#ibcon#read 6, iclass 33, count 0 2006.285.16:05:04.72#ibcon#end of sib2, iclass 33, count 0 2006.285.16:05:04.72#ibcon#*mode == 0, iclass 33, count 0 2006.285.16:05:04.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.16:05:04.72#ibcon#[25=USB\r\n] 2006.285.16:05:04.72#ibcon#*before write, iclass 33, count 0 2006.285.16:05:04.72#ibcon#enter sib2, iclass 33, count 0 2006.285.16:05:04.72#ibcon#flushed, iclass 33, count 0 2006.285.16:05:04.72#ibcon#about to write, iclass 33, count 0 2006.285.16:05:04.72#ibcon#wrote, iclass 33, count 0 2006.285.16:05:04.72#ibcon#about to read 3, iclass 33, count 0 2006.285.16:05:04.75#ibcon#read 3, iclass 33, count 0 2006.285.16:05:04.75#ibcon#about to read 4, iclass 33, count 0 2006.285.16:05:04.75#ibcon#read 4, iclass 33, count 0 2006.285.16:05:04.75#ibcon#about to read 5, iclass 33, count 0 2006.285.16:05:04.75#ibcon#read 5, iclass 33, count 0 2006.285.16:05:04.75#ibcon#about to read 6, iclass 33, count 0 2006.285.16:05:04.75#ibcon#read 6, iclass 33, count 0 2006.285.16:05:04.75#ibcon#end of sib2, iclass 33, count 0 2006.285.16:05:04.75#ibcon#*after write, iclass 33, count 0 2006.285.16:05:04.75#ibcon#*before return 0, iclass 33, count 0 2006.285.16:05:04.75#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:05:04.75#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:05:04.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.16:05:04.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.16:05:04.75$vck44/valo=5,734.99 2006.285.16:05:04.75#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.16:05:04.75#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.16:05:04.75#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:04.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:05:04.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:05:04.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:05:04.75#ibcon#enter wrdev, iclass 35, count 0 2006.285.16:05:04.75#ibcon#first serial, iclass 35, count 0 2006.285.16:05:04.75#ibcon#enter sib2, iclass 35, count 0 2006.285.16:05:04.75#ibcon#flushed, iclass 35, count 0 2006.285.16:05:04.75#ibcon#about to write, iclass 35, count 0 2006.285.16:05:04.75#ibcon#wrote, iclass 35, count 0 2006.285.16:05:04.75#ibcon#about to read 3, iclass 35, count 0 2006.285.16:05:04.77#ibcon#read 3, iclass 35, count 0 2006.285.16:05:04.77#ibcon#about to read 4, iclass 35, count 0 2006.285.16:05:04.77#ibcon#read 4, iclass 35, count 0 2006.285.16:05:04.77#ibcon#about to read 5, iclass 35, count 0 2006.285.16:05:04.77#ibcon#read 5, iclass 35, count 0 2006.285.16:05:04.77#ibcon#about to read 6, iclass 35, count 0 2006.285.16:05:04.77#ibcon#read 6, iclass 35, count 0 2006.285.16:05:04.77#ibcon#end of sib2, iclass 35, count 0 2006.285.16:05:04.77#ibcon#*mode == 0, iclass 35, count 0 2006.285.16:05:04.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.16:05:04.77#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.16:05:04.77#ibcon#*before write, iclass 35, count 0 2006.285.16:05:04.77#ibcon#enter sib2, iclass 35, count 0 2006.285.16:05:04.77#ibcon#flushed, iclass 35, count 0 2006.285.16:05:04.77#ibcon#about to write, iclass 35, count 0 2006.285.16:05:04.77#ibcon#wrote, iclass 35, count 0 2006.285.16:05:04.77#ibcon#about to read 3, iclass 35, count 0 2006.285.16:05:04.81#ibcon#read 3, iclass 35, count 0 2006.285.16:05:04.81#ibcon#about to read 4, iclass 35, count 0 2006.285.16:05:04.81#ibcon#read 4, iclass 35, count 0 2006.285.16:05:04.81#ibcon#about to read 5, iclass 35, count 0 2006.285.16:05:04.81#ibcon#read 5, iclass 35, count 0 2006.285.16:05:04.81#ibcon#about to read 6, iclass 35, count 0 2006.285.16:05:04.81#ibcon#read 6, iclass 35, count 0 2006.285.16:05:04.81#ibcon#end of sib2, iclass 35, count 0 2006.285.16:05:04.81#ibcon#*after write, iclass 35, count 0 2006.285.16:05:04.81#ibcon#*before return 0, iclass 35, count 0 2006.285.16:05:04.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:05:04.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:05:04.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.16:05:04.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.16:05:04.81$vck44/va=5,3 2006.285.16:05:04.81#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.16:05:04.81#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.16:05:04.81#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:04.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:05:04.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:05:04.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:05:04.87#ibcon#enter wrdev, iclass 37, count 2 2006.285.16:05:04.87#ibcon#first serial, iclass 37, count 2 2006.285.16:05:04.87#ibcon#enter sib2, iclass 37, count 2 2006.285.16:05:04.87#ibcon#flushed, iclass 37, count 2 2006.285.16:05:04.87#ibcon#about to write, iclass 37, count 2 2006.285.16:05:04.87#ibcon#wrote, iclass 37, count 2 2006.285.16:05:04.87#ibcon#about to read 3, iclass 37, count 2 2006.285.16:05:04.89#ibcon#read 3, iclass 37, count 2 2006.285.16:05:04.89#ibcon#about to read 4, iclass 37, count 2 2006.285.16:05:04.89#ibcon#read 4, iclass 37, count 2 2006.285.16:05:04.89#ibcon#about to read 5, iclass 37, count 2 2006.285.16:05:04.89#ibcon#read 5, iclass 37, count 2 2006.285.16:05:04.89#ibcon#about to read 6, iclass 37, count 2 2006.285.16:05:04.89#ibcon#read 6, iclass 37, count 2 2006.285.16:05:04.89#ibcon#end of sib2, iclass 37, count 2 2006.285.16:05:04.89#ibcon#*mode == 0, iclass 37, count 2 2006.285.16:05:04.89#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.16:05:04.89#ibcon#[25=AT05-03\r\n] 2006.285.16:05:04.89#ibcon#*before write, iclass 37, count 2 2006.285.16:05:04.89#ibcon#enter sib2, iclass 37, count 2 2006.285.16:05:04.89#ibcon#flushed, iclass 37, count 2 2006.285.16:05:04.89#ibcon#about to write, iclass 37, count 2 2006.285.16:05:04.89#ibcon#wrote, iclass 37, count 2 2006.285.16:05:04.89#ibcon#about to read 3, iclass 37, count 2 2006.285.16:05:04.92#ibcon#read 3, iclass 37, count 2 2006.285.16:05:04.92#ibcon#about to read 4, iclass 37, count 2 2006.285.16:05:04.92#ibcon#read 4, iclass 37, count 2 2006.285.16:05:04.92#ibcon#about to read 5, iclass 37, count 2 2006.285.16:05:04.92#ibcon#read 5, iclass 37, count 2 2006.285.16:05:04.92#ibcon#about to read 6, iclass 37, count 2 2006.285.16:05:04.92#ibcon#read 6, iclass 37, count 2 2006.285.16:05:04.92#ibcon#end of sib2, iclass 37, count 2 2006.285.16:05:04.92#ibcon#*after write, iclass 37, count 2 2006.285.16:05:04.92#ibcon#*before return 0, iclass 37, count 2 2006.285.16:05:04.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:05:04.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:05:04.92#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.16:05:04.92#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:04.92#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:05:05.04#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:05:05.04#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:05:05.04#ibcon#enter wrdev, iclass 37, count 0 2006.285.16:05:05.04#ibcon#first serial, iclass 37, count 0 2006.285.16:05:05.04#ibcon#enter sib2, iclass 37, count 0 2006.285.16:05:05.04#ibcon#flushed, iclass 37, count 0 2006.285.16:05:05.04#ibcon#about to write, iclass 37, count 0 2006.285.16:05:05.04#ibcon#wrote, iclass 37, count 0 2006.285.16:05:05.04#ibcon#about to read 3, iclass 37, count 0 2006.285.16:05:05.06#ibcon#read 3, iclass 37, count 0 2006.285.16:05:05.06#ibcon#about to read 4, iclass 37, count 0 2006.285.16:05:05.06#ibcon#read 4, iclass 37, count 0 2006.285.16:05:05.06#ibcon#about to read 5, iclass 37, count 0 2006.285.16:05:05.06#ibcon#read 5, iclass 37, count 0 2006.285.16:05:05.06#ibcon#about to read 6, iclass 37, count 0 2006.285.16:05:05.06#ibcon#read 6, iclass 37, count 0 2006.285.16:05:05.06#ibcon#end of sib2, iclass 37, count 0 2006.285.16:05:05.06#ibcon#*mode == 0, iclass 37, count 0 2006.285.16:05:05.06#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.16:05:05.06#ibcon#[25=USB\r\n] 2006.285.16:05:05.06#ibcon#*before write, iclass 37, count 0 2006.285.16:05:05.06#ibcon#enter sib2, iclass 37, count 0 2006.285.16:05:05.06#ibcon#flushed, iclass 37, count 0 2006.285.16:05:05.06#ibcon#about to write, iclass 37, count 0 2006.285.16:05:05.06#ibcon#wrote, iclass 37, count 0 2006.285.16:05:05.06#ibcon#about to read 3, iclass 37, count 0 2006.285.16:05:05.09#ibcon#read 3, iclass 37, count 0 2006.285.16:05:05.09#ibcon#about to read 4, iclass 37, count 0 2006.285.16:05:05.09#ibcon#read 4, iclass 37, count 0 2006.285.16:05:05.09#ibcon#about to read 5, iclass 37, count 0 2006.285.16:05:05.09#ibcon#read 5, iclass 37, count 0 2006.285.16:05:05.09#ibcon#about to read 6, iclass 37, count 0 2006.285.16:05:05.09#ibcon#read 6, iclass 37, count 0 2006.285.16:05:05.09#ibcon#end of sib2, iclass 37, count 0 2006.285.16:05:05.09#ibcon#*after write, iclass 37, count 0 2006.285.16:05:05.09#ibcon#*before return 0, iclass 37, count 0 2006.285.16:05:05.09#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:05:05.09#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:05:05.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.16:05:05.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.16:05:05.09$vck44/valo=6,814.99 2006.285.16:05:05.09#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.16:05:05.09#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.16:05:05.09#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:05.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:05:05.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:05:05.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:05:05.09#ibcon#enter wrdev, iclass 39, count 0 2006.285.16:05:05.09#ibcon#first serial, iclass 39, count 0 2006.285.16:05:05.09#ibcon#enter sib2, iclass 39, count 0 2006.285.16:05:05.09#ibcon#flushed, iclass 39, count 0 2006.285.16:05:05.09#ibcon#about to write, iclass 39, count 0 2006.285.16:05:05.09#ibcon#wrote, iclass 39, count 0 2006.285.16:05:05.09#ibcon#about to read 3, iclass 39, count 0 2006.285.16:05:05.11#ibcon#read 3, iclass 39, count 0 2006.285.16:05:05.11#ibcon#about to read 4, iclass 39, count 0 2006.285.16:05:05.11#ibcon#read 4, iclass 39, count 0 2006.285.16:05:05.11#ibcon#about to read 5, iclass 39, count 0 2006.285.16:05:05.11#ibcon#read 5, iclass 39, count 0 2006.285.16:05:05.11#ibcon#about to read 6, iclass 39, count 0 2006.285.16:05:05.11#ibcon#read 6, iclass 39, count 0 2006.285.16:05:05.11#ibcon#end of sib2, iclass 39, count 0 2006.285.16:05:05.11#ibcon#*mode == 0, iclass 39, count 0 2006.285.16:05:05.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.16:05:05.11#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.16:05:05.11#ibcon#*before write, iclass 39, count 0 2006.285.16:05:05.11#ibcon#enter sib2, iclass 39, count 0 2006.285.16:05:05.11#ibcon#flushed, iclass 39, count 0 2006.285.16:05:05.11#ibcon#about to write, iclass 39, count 0 2006.285.16:05:05.11#ibcon#wrote, iclass 39, count 0 2006.285.16:05:05.11#ibcon#about to read 3, iclass 39, count 0 2006.285.16:05:05.15#ibcon#read 3, iclass 39, count 0 2006.285.16:05:05.15#ibcon#about to read 4, iclass 39, count 0 2006.285.16:05:05.15#ibcon#read 4, iclass 39, count 0 2006.285.16:05:05.15#ibcon#about to read 5, iclass 39, count 0 2006.285.16:05:05.15#ibcon#read 5, iclass 39, count 0 2006.285.16:05:05.15#ibcon#about to read 6, iclass 39, count 0 2006.285.16:05:05.15#ibcon#read 6, iclass 39, count 0 2006.285.16:05:05.15#ibcon#end of sib2, iclass 39, count 0 2006.285.16:05:05.15#ibcon#*after write, iclass 39, count 0 2006.285.16:05:05.15#ibcon#*before return 0, iclass 39, count 0 2006.285.16:05:05.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:05:05.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:05:05.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.16:05:05.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.16:05:05.15$vck44/va=6,4 2006.285.16:05:05.15#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.16:05:05.15#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.16:05:05.15#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:05.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:05:05.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:05:05.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:05:05.21#ibcon#enter wrdev, iclass 3, count 2 2006.285.16:05:05.21#ibcon#first serial, iclass 3, count 2 2006.285.16:05:05.21#ibcon#enter sib2, iclass 3, count 2 2006.285.16:05:05.21#ibcon#flushed, iclass 3, count 2 2006.285.16:05:05.21#ibcon#about to write, iclass 3, count 2 2006.285.16:05:05.21#ibcon#wrote, iclass 3, count 2 2006.285.16:05:05.21#ibcon#about to read 3, iclass 3, count 2 2006.285.16:05:05.23#ibcon#read 3, iclass 3, count 2 2006.285.16:05:05.23#ibcon#about to read 4, iclass 3, count 2 2006.285.16:05:05.23#ibcon#read 4, iclass 3, count 2 2006.285.16:05:05.23#ibcon#about to read 5, iclass 3, count 2 2006.285.16:05:05.23#ibcon#read 5, iclass 3, count 2 2006.285.16:05:05.23#ibcon#about to read 6, iclass 3, count 2 2006.285.16:05:05.23#ibcon#read 6, iclass 3, count 2 2006.285.16:05:05.23#ibcon#end of sib2, iclass 3, count 2 2006.285.16:05:05.23#ibcon#*mode == 0, iclass 3, count 2 2006.285.16:05:05.23#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.16:05:05.23#ibcon#[25=AT06-04\r\n] 2006.285.16:05:05.23#ibcon#*before write, iclass 3, count 2 2006.285.16:05:05.23#ibcon#enter sib2, iclass 3, count 2 2006.285.16:05:05.23#ibcon#flushed, iclass 3, count 2 2006.285.16:05:05.23#ibcon#about to write, iclass 3, count 2 2006.285.16:05:05.23#ibcon#wrote, iclass 3, count 2 2006.285.16:05:05.23#ibcon#about to read 3, iclass 3, count 2 2006.285.16:05:05.26#ibcon#read 3, iclass 3, count 2 2006.285.16:05:05.26#ibcon#about to read 4, iclass 3, count 2 2006.285.16:05:05.26#ibcon#read 4, iclass 3, count 2 2006.285.16:05:05.26#ibcon#about to read 5, iclass 3, count 2 2006.285.16:05:05.26#ibcon#read 5, iclass 3, count 2 2006.285.16:05:05.26#ibcon#about to read 6, iclass 3, count 2 2006.285.16:05:05.26#ibcon#read 6, iclass 3, count 2 2006.285.16:05:05.26#ibcon#end of sib2, iclass 3, count 2 2006.285.16:05:05.26#ibcon#*after write, iclass 3, count 2 2006.285.16:05:05.26#ibcon#*before return 0, iclass 3, count 2 2006.285.16:05:05.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:05:05.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:05:05.26#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.16:05:05.26#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:05.26#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:05:05.38#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:05:05.38#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:05:05.38#ibcon#enter wrdev, iclass 3, count 0 2006.285.16:05:05.38#ibcon#first serial, iclass 3, count 0 2006.285.16:05:05.38#ibcon#enter sib2, iclass 3, count 0 2006.285.16:05:05.38#ibcon#flushed, iclass 3, count 0 2006.285.16:05:05.38#ibcon#about to write, iclass 3, count 0 2006.285.16:05:05.38#ibcon#wrote, iclass 3, count 0 2006.285.16:05:05.38#ibcon#about to read 3, iclass 3, count 0 2006.285.16:05:05.40#ibcon#read 3, iclass 3, count 0 2006.285.16:05:05.40#ibcon#about to read 4, iclass 3, count 0 2006.285.16:05:05.40#ibcon#read 4, iclass 3, count 0 2006.285.16:05:05.40#ibcon#about to read 5, iclass 3, count 0 2006.285.16:05:05.40#ibcon#read 5, iclass 3, count 0 2006.285.16:05:05.40#ibcon#about to read 6, iclass 3, count 0 2006.285.16:05:05.40#ibcon#read 6, iclass 3, count 0 2006.285.16:05:05.40#ibcon#end of sib2, iclass 3, count 0 2006.285.16:05:05.40#ibcon#*mode == 0, iclass 3, count 0 2006.285.16:05:05.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.16:05:05.40#ibcon#[25=USB\r\n] 2006.285.16:05:05.40#ibcon#*before write, iclass 3, count 0 2006.285.16:05:05.40#ibcon#enter sib2, iclass 3, count 0 2006.285.16:05:05.40#ibcon#flushed, iclass 3, count 0 2006.285.16:05:05.40#ibcon#about to write, iclass 3, count 0 2006.285.16:05:05.40#ibcon#wrote, iclass 3, count 0 2006.285.16:05:05.40#ibcon#about to read 3, iclass 3, count 0 2006.285.16:05:05.43#ibcon#read 3, iclass 3, count 0 2006.285.16:05:05.43#ibcon#about to read 4, iclass 3, count 0 2006.285.16:05:05.43#ibcon#read 4, iclass 3, count 0 2006.285.16:05:05.43#ibcon#about to read 5, iclass 3, count 0 2006.285.16:05:05.43#ibcon#read 5, iclass 3, count 0 2006.285.16:05:05.43#ibcon#about to read 6, iclass 3, count 0 2006.285.16:05:05.43#ibcon#read 6, iclass 3, count 0 2006.285.16:05:05.43#ibcon#end of sib2, iclass 3, count 0 2006.285.16:05:05.43#ibcon#*after write, iclass 3, count 0 2006.285.16:05:05.43#ibcon#*before return 0, iclass 3, count 0 2006.285.16:05:05.43#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:05:05.43#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:05:05.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.16:05:05.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.16:05:05.43$vck44/valo=7,864.99 2006.285.16:05:05.74#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.16:05:05.74#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.16:05:05.74#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:05.74#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:05:05.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:05:05.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:05:05.74#ibcon#enter wrdev, iclass 5, count 0 2006.285.16:05:05.74#ibcon#first serial, iclass 5, count 0 2006.285.16:05:05.74#ibcon#enter sib2, iclass 5, count 0 2006.285.16:05:05.74#ibcon#flushed, iclass 5, count 0 2006.285.16:05:05.74#ibcon#about to write, iclass 5, count 0 2006.285.16:05:05.74#ibcon#wrote, iclass 5, count 0 2006.285.16:05:05.74#ibcon#about to read 3, iclass 5, count 0 2006.285.16:05:05.75#ibcon#read 3, iclass 5, count 0 2006.285.16:05:05.75#ibcon#about to read 4, iclass 5, count 0 2006.285.16:05:05.75#ibcon#read 4, iclass 5, count 0 2006.285.16:05:05.75#ibcon#about to read 5, iclass 5, count 0 2006.285.16:05:05.75#ibcon#read 5, iclass 5, count 0 2006.285.16:05:05.75#ibcon#about to read 6, iclass 5, count 0 2006.285.16:05:05.75#ibcon#read 6, iclass 5, count 0 2006.285.16:05:05.75#ibcon#end of sib2, iclass 5, count 0 2006.285.16:05:05.75#ibcon#*mode == 0, iclass 5, count 0 2006.285.16:05:05.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.16:05:05.75#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.16:05:05.75#ibcon#*before write, iclass 5, count 0 2006.285.16:05:05.75#ibcon#enter sib2, iclass 5, count 0 2006.285.16:05:05.75#ibcon#flushed, iclass 5, count 0 2006.285.16:05:05.75#ibcon#about to write, iclass 5, count 0 2006.285.16:05:05.75#ibcon#wrote, iclass 5, count 0 2006.285.16:05:05.75#ibcon#about to read 3, iclass 5, count 0 2006.285.16:05:05.79#ibcon#read 3, iclass 5, count 0 2006.285.16:05:05.79#ibcon#about to read 4, iclass 5, count 0 2006.285.16:05:05.79#ibcon#read 4, iclass 5, count 0 2006.285.16:05:05.79#ibcon#about to read 5, iclass 5, count 0 2006.285.16:05:05.79#ibcon#read 5, iclass 5, count 0 2006.285.16:05:05.79#ibcon#about to read 6, iclass 5, count 0 2006.285.16:05:05.79#ibcon#read 6, iclass 5, count 0 2006.285.16:05:05.79#ibcon#end of sib2, iclass 5, count 0 2006.285.16:05:05.79#ibcon#*after write, iclass 5, count 0 2006.285.16:05:05.79#ibcon#*before return 0, iclass 5, count 0 2006.285.16:05:05.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:05:05.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:05:05.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.16:05:05.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.16:05:05.79$vck44/va=7,4 2006.285.16:05:05.79#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.16:05:05.79#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.16:05:05.79#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:05.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:05:05.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:05:05.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:05:05.79#ibcon#enter wrdev, iclass 7, count 2 2006.285.16:05:05.79#ibcon#first serial, iclass 7, count 2 2006.285.16:05:05.79#ibcon#enter sib2, iclass 7, count 2 2006.285.16:05:05.79#ibcon#flushed, iclass 7, count 2 2006.285.16:05:05.79#ibcon#about to write, iclass 7, count 2 2006.285.16:05:05.79#ibcon#wrote, iclass 7, count 2 2006.285.16:05:05.79#ibcon#about to read 3, iclass 7, count 2 2006.285.16:05:05.81#ibcon#read 3, iclass 7, count 2 2006.285.16:05:05.81#ibcon#about to read 4, iclass 7, count 2 2006.285.16:05:05.81#ibcon#read 4, iclass 7, count 2 2006.285.16:05:05.81#ibcon#about to read 5, iclass 7, count 2 2006.285.16:05:05.81#ibcon#read 5, iclass 7, count 2 2006.285.16:05:05.81#ibcon#about to read 6, iclass 7, count 2 2006.285.16:05:05.81#ibcon#read 6, iclass 7, count 2 2006.285.16:05:05.81#ibcon#end of sib2, iclass 7, count 2 2006.285.16:05:05.81#ibcon#*mode == 0, iclass 7, count 2 2006.285.16:05:05.81#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.16:05:05.81#ibcon#[25=AT07-04\r\n] 2006.285.16:05:05.81#ibcon#*before write, iclass 7, count 2 2006.285.16:05:05.81#ibcon#enter sib2, iclass 7, count 2 2006.285.16:05:05.81#ibcon#flushed, iclass 7, count 2 2006.285.16:05:05.81#ibcon#about to write, iclass 7, count 2 2006.285.16:05:05.81#ibcon#wrote, iclass 7, count 2 2006.285.16:05:05.81#ibcon#about to read 3, iclass 7, count 2 2006.285.16:05:05.84#ibcon#read 3, iclass 7, count 2 2006.285.16:05:05.84#ibcon#about to read 4, iclass 7, count 2 2006.285.16:05:05.84#ibcon#read 4, iclass 7, count 2 2006.285.16:05:05.84#ibcon#about to read 5, iclass 7, count 2 2006.285.16:05:05.84#ibcon#read 5, iclass 7, count 2 2006.285.16:05:05.84#ibcon#about to read 6, iclass 7, count 2 2006.285.16:05:05.84#ibcon#read 6, iclass 7, count 2 2006.285.16:05:05.84#ibcon#end of sib2, iclass 7, count 2 2006.285.16:05:05.84#ibcon#*after write, iclass 7, count 2 2006.285.16:05:05.84#ibcon#*before return 0, iclass 7, count 2 2006.285.16:05:05.84#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:05:05.84#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:05:05.84#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.16:05:05.84#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:05.84#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:05:05.96#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:05:05.96#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:05:05.96#ibcon#enter wrdev, iclass 7, count 0 2006.285.16:05:05.96#ibcon#first serial, iclass 7, count 0 2006.285.16:05:05.96#ibcon#enter sib2, iclass 7, count 0 2006.285.16:05:05.96#ibcon#flushed, iclass 7, count 0 2006.285.16:05:05.96#ibcon#about to write, iclass 7, count 0 2006.285.16:05:05.96#ibcon#wrote, iclass 7, count 0 2006.285.16:05:05.96#ibcon#about to read 3, iclass 7, count 0 2006.285.16:05:05.98#ibcon#read 3, iclass 7, count 0 2006.285.16:05:05.98#ibcon#about to read 4, iclass 7, count 0 2006.285.16:05:05.98#ibcon#read 4, iclass 7, count 0 2006.285.16:05:05.98#ibcon#about to read 5, iclass 7, count 0 2006.285.16:05:05.98#ibcon#read 5, iclass 7, count 0 2006.285.16:05:05.98#ibcon#about to read 6, iclass 7, count 0 2006.285.16:05:05.98#ibcon#read 6, iclass 7, count 0 2006.285.16:05:05.98#ibcon#end of sib2, iclass 7, count 0 2006.285.16:05:05.98#ibcon#*mode == 0, iclass 7, count 0 2006.285.16:05:05.98#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.16:05:05.98#ibcon#[25=USB\r\n] 2006.285.16:05:05.98#ibcon#*before write, iclass 7, count 0 2006.285.16:05:05.98#ibcon#enter sib2, iclass 7, count 0 2006.285.16:05:05.98#ibcon#flushed, iclass 7, count 0 2006.285.16:05:05.98#ibcon#about to write, iclass 7, count 0 2006.285.16:05:05.98#ibcon#wrote, iclass 7, count 0 2006.285.16:05:05.98#ibcon#about to read 3, iclass 7, count 0 2006.285.16:05:06.01#ibcon#read 3, iclass 7, count 0 2006.285.16:05:06.01#ibcon#about to read 4, iclass 7, count 0 2006.285.16:05:06.01#ibcon#read 4, iclass 7, count 0 2006.285.16:05:06.01#ibcon#about to read 5, iclass 7, count 0 2006.285.16:05:06.01#ibcon#read 5, iclass 7, count 0 2006.285.16:05:06.01#ibcon#about to read 6, iclass 7, count 0 2006.285.16:05:06.01#ibcon#read 6, iclass 7, count 0 2006.285.16:05:06.01#ibcon#end of sib2, iclass 7, count 0 2006.285.16:05:06.01#ibcon#*after write, iclass 7, count 0 2006.285.16:05:06.01#ibcon#*before return 0, iclass 7, count 0 2006.285.16:05:06.01#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:05:06.01#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:05:06.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.16:05:06.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.16:05:06.01$vck44/valo=8,884.99 2006.285.16:05:06.01#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.16:05:06.01#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.16:05:06.01#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:06.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:05:06.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:05:06.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:05:06.01#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:05:06.01#ibcon#first serial, iclass 11, count 0 2006.285.16:05:06.01#ibcon#enter sib2, iclass 11, count 0 2006.285.16:05:06.01#ibcon#flushed, iclass 11, count 0 2006.285.16:05:06.01#ibcon#about to write, iclass 11, count 0 2006.285.16:05:06.01#ibcon#wrote, iclass 11, count 0 2006.285.16:05:06.01#ibcon#about to read 3, iclass 11, count 0 2006.285.16:05:06.03#ibcon#read 3, iclass 11, count 0 2006.285.16:05:06.03#ibcon#about to read 4, iclass 11, count 0 2006.285.16:05:06.03#ibcon#read 4, iclass 11, count 0 2006.285.16:05:06.03#ibcon#about to read 5, iclass 11, count 0 2006.285.16:05:06.03#ibcon#read 5, iclass 11, count 0 2006.285.16:05:06.03#ibcon#about to read 6, iclass 11, count 0 2006.285.16:05:06.03#ibcon#read 6, iclass 11, count 0 2006.285.16:05:06.03#ibcon#end of sib2, iclass 11, count 0 2006.285.16:05:06.03#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:05:06.03#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:05:06.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.16:05:06.03#ibcon#*before write, iclass 11, count 0 2006.285.16:05:06.03#ibcon#enter sib2, iclass 11, count 0 2006.285.16:05:06.03#ibcon#flushed, iclass 11, count 0 2006.285.16:05:06.03#ibcon#about to write, iclass 11, count 0 2006.285.16:05:06.03#ibcon#wrote, iclass 11, count 0 2006.285.16:05:06.03#ibcon#about to read 3, iclass 11, count 0 2006.285.16:05:06.07#ibcon#read 3, iclass 11, count 0 2006.285.16:05:06.07#ibcon#about to read 4, iclass 11, count 0 2006.285.16:05:06.07#ibcon#read 4, iclass 11, count 0 2006.285.16:05:06.07#ibcon#about to read 5, iclass 11, count 0 2006.285.16:05:06.07#ibcon#read 5, iclass 11, count 0 2006.285.16:05:06.07#ibcon#about to read 6, iclass 11, count 0 2006.285.16:05:06.07#ibcon#read 6, iclass 11, count 0 2006.285.16:05:06.07#ibcon#end of sib2, iclass 11, count 0 2006.285.16:05:06.07#ibcon#*after write, iclass 11, count 0 2006.285.16:05:06.07#ibcon#*before return 0, iclass 11, count 0 2006.285.16:05:06.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:05:06.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:05:06.07#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:05:06.07#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:05:06.07$vck44/va=8,3 2006.285.16:05:06.07#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.16:05:06.07#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.16:05:06.07#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:06.07#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:05:06.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:05:06.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:05:06.13#ibcon#enter wrdev, iclass 13, count 2 2006.285.16:05:06.13#ibcon#first serial, iclass 13, count 2 2006.285.16:05:06.13#ibcon#enter sib2, iclass 13, count 2 2006.285.16:05:06.13#ibcon#flushed, iclass 13, count 2 2006.285.16:05:06.13#ibcon#about to write, iclass 13, count 2 2006.285.16:05:06.13#ibcon#wrote, iclass 13, count 2 2006.285.16:05:06.13#ibcon#about to read 3, iclass 13, count 2 2006.285.16:05:06.15#ibcon#read 3, iclass 13, count 2 2006.285.16:05:06.15#ibcon#about to read 4, iclass 13, count 2 2006.285.16:05:06.15#ibcon#read 4, iclass 13, count 2 2006.285.16:05:06.15#ibcon#about to read 5, iclass 13, count 2 2006.285.16:05:06.15#ibcon#read 5, iclass 13, count 2 2006.285.16:05:06.15#ibcon#about to read 6, iclass 13, count 2 2006.285.16:05:06.15#ibcon#read 6, iclass 13, count 2 2006.285.16:05:06.15#ibcon#end of sib2, iclass 13, count 2 2006.285.16:05:06.15#ibcon#*mode == 0, iclass 13, count 2 2006.285.16:05:06.15#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.16:05:06.15#ibcon#[25=AT08-03\r\n] 2006.285.16:05:06.15#ibcon#*before write, iclass 13, count 2 2006.285.16:05:06.15#ibcon#enter sib2, iclass 13, count 2 2006.285.16:05:06.15#ibcon#flushed, iclass 13, count 2 2006.285.16:05:06.15#ibcon#about to write, iclass 13, count 2 2006.285.16:05:06.15#ibcon#wrote, iclass 13, count 2 2006.285.16:05:06.15#ibcon#about to read 3, iclass 13, count 2 2006.285.16:05:06.18#ibcon#read 3, iclass 13, count 2 2006.285.16:05:06.18#ibcon#about to read 4, iclass 13, count 2 2006.285.16:05:06.18#ibcon#read 4, iclass 13, count 2 2006.285.16:05:06.18#ibcon#about to read 5, iclass 13, count 2 2006.285.16:05:06.18#ibcon#read 5, iclass 13, count 2 2006.285.16:05:06.18#ibcon#about to read 6, iclass 13, count 2 2006.285.16:05:06.18#ibcon#read 6, iclass 13, count 2 2006.285.16:05:06.18#ibcon#end of sib2, iclass 13, count 2 2006.285.16:05:06.18#ibcon#*after write, iclass 13, count 2 2006.285.16:05:06.18#ibcon#*before return 0, iclass 13, count 2 2006.285.16:05:06.18#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:05:06.18#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:05:06.18#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.16:05:06.18#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:06.18#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:05:06.30#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:05:06.30#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:05:06.30#ibcon#enter wrdev, iclass 13, count 0 2006.285.16:05:06.30#ibcon#first serial, iclass 13, count 0 2006.285.16:05:06.30#ibcon#enter sib2, iclass 13, count 0 2006.285.16:05:06.30#ibcon#flushed, iclass 13, count 0 2006.285.16:05:06.30#ibcon#about to write, iclass 13, count 0 2006.285.16:05:06.30#ibcon#wrote, iclass 13, count 0 2006.285.16:05:06.30#ibcon#about to read 3, iclass 13, count 0 2006.285.16:05:06.32#ibcon#read 3, iclass 13, count 0 2006.285.16:05:06.32#ibcon#about to read 4, iclass 13, count 0 2006.285.16:05:06.32#ibcon#read 4, iclass 13, count 0 2006.285.16:05:06.32#ibcon#about to read 5, iclass 13, count 0 2006.285.16:05:06.32#ibcon#read 5, iclass 13, count 0 2006.285.16:05:06.32#ibcon#about to read 6, iclass 13, count 0 2006.285.16:05:06.32#ibcon#read 6, iclass 13, count 0 2006.285.16:05:06.32#ibcon#end of sib2, iclass 13, count 0 2006.285.16:05:06.32#ibcon#*mode == 0, iclass 13, count 0 2006.285.16:05:06.32#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.16:05:06.32#ibcon#[25=USB\r\n] 2006.285.16:05:06.32#ibcon#*before write, iclass 13, count 0 2006.285.16:05:06.32#ibcon#enter sib2, iclass 13, count 0 2006.285.16:05:06.32#ibcon#flushed, iclass 13, count 0 2006.285.16:05:06.32#ibcon#about to write, iclass 13, count 0 2006.285.16:05:06.32#ibcon#wrote, iclass 13, count 0 2006.285.16:05:06.32#ibcon#about to read 3, iclass 13, count 0 2006.285.16:05:06.35#ibcon#read 3, iclass 13, count 0 2006.285.16:05:06.35#ibcon#about to read 4, iclass 13, count 0 2006.285.16:05:06.35#ibcon#read 4, iclass 13, count 0 2006.285.16:05:06.35#ibcon#about to read 5, iclass 13, count 0 2006.285.16:05:06.35#ibcon#read 5, iclass 13, count 0 2006.285.16:05:06.35#ibcon#about to read 6, iclass 13, count 0 2006.285.16:05:06.35#ibcon#read 6, iclass 13, count 0 2006.285.16:05:06.35#ibcon#end of sib2, iclass 13, count 0 2006.285.16:05:06.35#ibcon#*after write, iclass 13, count 0 2006.285.16:05:06.35#ibcon#*before return 0, iclass 13, count 0 2006.285.16:05:06.35#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:05:06.35#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:05:06.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.16:05:06.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.16:05:06.35$vck44/vblo=1,629.99 2006.285.16:05:06.35#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.16:05:06.35#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.16:05:06.35#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:06.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:05:06.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:05:06.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:05:06.35#ibcon#enter wrdev, iclass 15, count 0 2006.285.16:05:06.35#ibcon#first serial, iclass 15, count 0 2006.285.16:05:06.35#ibcon#enter sib2, iclass 15, count 0 2006.285.16:05:06.35#ibcon#flushed, iclass 15, count 0 2006.285.16:05:06.35#ibcon#about to write, iclass 15, count 0 2006.285.16:05:06.35#ibcon#wrote, iclass 15, count 0 2006.285.16:05:06.35#ibcon#about to read 3, iclass 15, count 0 2006.285.16:05:06.37#ibcon#read 3, iclass 15, count 0 2006.285.16:05:06.43#ibcon#about to read 4, iclass 15, count 0 2006.285.16:05:06.43#ibcon#read 4, iclass 15, count 0 2006.285.16:05:06.43#ibcon#about to read 5, iclass 15, count 0 2006.285.16:05:06.43#ibcon#read 5, iclass 15, count 0 2006.285.16:05:06.43#ibcon#about to read 6, iclass 15, count 0 2006.285.16:05:06.43#ibcon#read 6, iclass 15, count 0 2006.285.16:05:06.43#ibcon#end of sib2, iclass 15, count 0 2006.285.16:05:06.43#ibcon#*mode == 0, iclass 15, count 0 2006.285.16:05:06.43#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.16:05:06.43#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.16:05:06.43#ibcon#*before write, iclass 15, count 0 2006.285.16:05:06.43#ibcon#enter sib2, iclass 15, count 0 2006.285.16:05:06.43#ibcon#flushed, iclass 15, count 0 2006.285.16:05:06.43#ibcon#about to write, iclass 15, count 0 2006.285.16:05:06.43#ibcon#wrote, iclass 15, count 0 2006.285.16:05:06.43#ibcon#about to read 3, iclass 15, count 0 2006.285.16:05:06.47#ibcon#read 3, iclass 15, count 0 2006.285.16:05:06.47#ibcon#about to read 4, iclass 15, count 0 2006.285.16:05:06.47#ibcon#read 4, iclass 15, count 0 2006.285.16:05:06.47#ibcon#about to read 5, iclass 15, count 0 2006.285.16:05:06.47#ibcon#read 5, iclass 15, count 0 2006.285.16:05:06.47#ibcon#about to read 6, iclass 15, count 0 2006.285.16:05:06.47#ibcon#read 6, iclass 15, count 0 2006.285.16:05:06.47#ibcon#end of sib2, iclass 15, count 0 2006.285.16:05:06.47#ibcon#*after write, iclass 15, count 0 2006.285.16:05:06.47#ibcon#*before return 0, iclass 15, count 0 2006.285.16:05:06.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:05:06.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:05:06.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.16:05:06.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.16:05:06.47$vck44/vb=1,4 2006.285.16:05:06.47#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.16:05:06.47#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.16:05:06.47#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:06.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:05:06.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:05:06.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:05:06.47#ibcon#enter wrdev, iclass 17, count 2 2006.285.16:05:06.47#ibcon#first serial, iclass 17, count 2 2006.285.16:05:06.47#ibcon#enter sib2, iclass 17, count 2 2006.285.16:05:06.47#ibcon#flushed, iclass 17, count 2 2006.285.16:05:06.47#ibcon#about to write, iclass 17, count 2 2006.285.16:05:06.47#ibcon#wrote, iclass 17, count 2 2006.285.16:05:06.47#ibcon#about to read 3, iclass 17, count 2 2006.285.16:05:06.49#ibcon#read 3, iclass 17, count 2 2006.285.16:05:06.49#ibcon#about to read 4, iclass 17, count 2 2006.285.16:05:06.49#ibcon#read 4, iclass 17, count 2 2006.285.16:05:06.49#ibcon#about to read 5, iclass 17, count 2 2006.285.16:05:06.49#ibcon#read 5, iclass 17, count 2 2006.285.16:05:06.49#ibcon#about to read 6, iclass 17, count 2 2006.285.16:05:06.49#ibcon#read 6, iclass 17, count 2 2006.285.16:05:06.49#ibcon#end of sib2, iclass 17, count 2 2006.285.16:05:06.49#ibcon#*mode == 0, iclass 17, count 2 2006.285.16:05:06.49#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.16:05:06.49#ibcon#[27=AT01-04\r\n] 2006.285.16:05:06.49#ibcon#*before write, iclass 17, count 2 2006.285.16:05:06.49#ibcon#enter sib2, iclass 17, count 2 2006.285.16:05:06.49#ibcon#flushed, iclass 17, count 2 2006.285.16:05:06.49#ibcon#about to write, iclass 17, count 2 2006.285.16:05:06.49#ibcon#wrote, iclass 17, count 2 2006.285.16:05:06.49#ibcon#about to read 3, iclass 17, count 2 2006.285.16:05:06.52#ibcon#read 3, iclass 17, count 2 2006.285.16:05:06.52#ibcon#about to read 4, iclass 17, count 2 2006.285.16:05:06.52#ibcon#read 4, iclass 17, count 2 2006.285.16:05:06.52#ibcon#about to read 5, iclass 17, count 2 2006.285.16:05:06.52#ibcon#read 5, iclass 17, count 2 2006.285.16:05:06.52#ibcon#about to read 6, iclass 17, count 2 2006.285.16:05:06.52#ibcon#read 6, iclass 17, count 2 2006.285.16:05:06.52#ibcon#end of sib2, iclass 17, count 2 2006.285.16:05:06.52#ibcon#*after write, iclass 17, count 2 2006.285.16:05:06.52#ibcon#*before return 0, iclass 17, count 2 2006.285.16:05:06.52#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:05:06.52#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:05:06.52#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.16:05:06.52#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:06.52#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:05:06.64#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:05:06.64#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:05:06.64#ibcon#enter wrdev, iclass 17, count 0 2006.285.16:05:06.64#ibcon#first serial, iclass 17, count 0 2006.285.16:05:06.64#ibcon#enter sib2, iclass 17, count 0 2006.285.16:05:06.64#ibcon#flushed, iclass 17, count 0 2006.285.16:05:06.64#ibcon#about to write, iclass 17, count 0 2006.285.16:05:06.64#ibcon#wrote, iclass 17, count 0 2006.285.16:05:06.64#ibcon#about to read 3, iclass 17, count 0 2006.285.16:05:06.66#ibcon#read 3, iclass 17, count 0 2006.285.16:05:06.66#ibcon#about to read 4, iclass 17, count 0 2006.285.16:05:06.66#ibcon#read 4, iclass 17, count 0 2006.285.16:05:06.66#ibcon#about to read 5, iclass 17, count 0 2006.285.16:05:06.66#ibcon#read 5, iclass 17, count 0 2006.285.16:05:06.66#ibcon#about to read 6, iclass 17, count 0 2006.285.16:05:06.66#ibcon#read 6, iclass 17, count 0 2006.285.16:05:06.66#ibcon#end of sib2, iclass 17, count 0 2006.285.16:05:06.66#ibcon#*mode == 0, iclass 17, count 0 2006.285.16:05:06.66#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.16:05:06.66#ibcon#[27=USB\r\n] 2006.285.16:05:06.66#ibcon#*before write, iclass 17, count 0 2006.285.16:05:06.66#ibcon#enter sib2, iclass 17, count 0 2006.285.16:05:06.66#ibcon#flushed, iclass 17, count 0 2006.285.16:05:06.66#ibcon#about to write, iclass 17, count 0 2006.285.16:05:06.66#ibcon#wrote, iclass 17, count 0 2006.285.16:05:06.66#ibcon#about to read 3, iclass 17, count 0 2006.285.16:05:06.69#ibcon#read 3, iclass 17, count 0 2006.285.16:05:06.69#ibcon#about to read 4, iclass 17, count 0 2006.285.16:05:06.69#ibcon#read 4, iclass 17, count 0 2006.285.16:05:06.69#ibcon#about to read 5, iclass 17, count 0 2006.285.16:05:06.69#ibcon#read 5, iclass 17, count 0 2006.285.16:05:06.69#ibcon#about to read 6, iclass 17, count 0 2006.285.16:05:06.69#ibcon#read 6, iclass 17, count 0 2006.285.16:05:06.69#ibcon#end of sib2, iclass 17, count 0 2006.285.16:05:06.69#ibcon#*after write, iclass 17, count 0 2006.285.16:05:06.69#ibcon#*before return 0, iclass 17, count 0 2006.285.16:05:06.69#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:05:06.69#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:05:06.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.16:05:06.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.16:05:06.69$vck44/vblo=2,634.99 2006.285.16:05:06.69#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.16:05:06.69#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.16:05:06.69#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:06.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:05:06.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:05:06.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:05:06.69#ibcon#enter wrdev, iclass 19, count 0 2006.285.16:05:06.69#ibcon#first serial, iclass 19, count 0 2006.285.16:05:06.69#ibcon#enter sib2, iclass 19, count 0 2006.285.16:05:06.69#ibcon#flushed, iclass 19, count 0 2006.285.16:05:06.69#ibcon#about to write, iclass 19, count 0 2006.285.16:05:06.69#ibcon#wrote, iclass 19, count 0 2006.285.16:05:06.69#ibcon#about to read 3, iclass 19, count 0 2006.285.16:05:06.71#ibcon#read 3, iclass 19, count 0 2006.285.16:05:06.71#ibcon#about to read 4, iclass 19, count 0 2006.285.16:05:06.71#ibcon#read 4, iclass 19, count 0 2006.285.16:05:06.71#ibcon#about to read 5, iclass 19, count 0 2006.285.16:05:06.71#ibcon#read 5, iclass 19, count 0 2006.285.16:05:06.71#ibcon#about to read 6, iclass 19, count 0 2006.285.16:05:06.71#ibcon#read 6, iclass 19, count 0 2006.285.16:05:06.71#ibcon#end of sib2, iclass 19, count 0 2006.285.16:05:06.71#ibcon#*mode == 0, iclass 19, count 0 2006.285.16:05:06.71#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.16:05:06.71#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.16:05:06.71#ibcon#*before write, iclass 19, count 0 2006.285.16:05:06.71#ibcon#enter sib2, iclass 19, count 0 2006.285.16:05:06.71#ibcon#flushed, iclass 19, count 0 2006.285.16:05:06.71#ibcon#about to write, iclass 19, count 0 2006.285.16:05:06.71#ibcon#wrote, iclass 19, count 0 2006.285.16:05:06.71#ibcon#about to read 3, iclass 19, count 0 2006.285.16:05:06.75#ibcon#read 3, iclass 19, count 0 2006.285.16:05:06.75#ibcon#about to read 4, iclass 19, count 0 2006.285.16:05:06.75#ibcon#read 4, iclass 19, count 0 2006.285.16:05:06.75#ibcon#about to read 5, iclass 19, count 0 2006.285.16:05:06.75#ibcon#read 5, iclass 19, count 0 2006.285.16:05:06.75#ibcon#about to read 6, iclass 19, count 0 2006.285.16:05:06.75#ibcon#read 6, iclass 19, count 0 2006.285.16:05:06.75#ibcon#end of sib2, iclass 19, count 0 2006.285.16:05:06.75#ibcon#*after write, iclass 19, count 0 2006.285.16:05:06.75#ibcon#*before return 0, iclass 19, count 0 2006.285.16:05:06.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:05:06.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:05:06.75#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.16:05:06.75#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.16:05:06.75$vck44/vb=2,5 2006.285.16:05:06.75#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.16:05:06.75#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.16:05:06.75#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:06.75#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:05:06.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:05:06.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:05:06.81#ibcon#enter wrdev, iclass 21, count 2 2006.285.16:05:06.81#ibcon#first serial, iclass 21, count 2 2006.285.16:05:06.81#ibcon#enter sib2, iclass 21, count 2 2006.285.16:05:06.81#ibcon#flushed, iclass 21, count 2 2006.285.16:05:06.81#ibcon#about to write, iclass 21, count 2 2006.285.16:05:06.81#ibcon#wrote, iclass 21, count 2 2006.285.16:05:06.81#ibcon#about to read 3, iclass 21, count 2 2006.285.16:05:06.83#ibcon#read 3, iclass 21, count 2 2006.285.16:05:06.83#ibcon#about to read 4, iclass 21, count 2 2006.285.16:05:06.83#ibcon#read 4, iclass 21, count 2 2006.285.16:05:06.83#ibcon#about to read 5, iclass 21, count 2 2006.285.16:05:06.83#ibcon#read 5, iclass 21, count 2 2006.285.16:05:06.83#ibcon#about to read 6, iclass 21, count 2 2006.285.16:05:06.83#ibcon#read 6, iclass 21, count 2 2006.285.16:05:06.83#ibcon#end of sib2, iclass 21, count 2 2006.285.16:05:06.83#ibcon#*mode == 0, iclass 21, count 2 2006.285.16:05:06.83#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.16:05:06.83#ibcon#[27=AT02-05\r\n] 2006.285.16:05:06.83#ibcon#*before write, iclass 21, count 2 2006.285.16:05:06.83#ibcon#enter sib2, iclass 21, count 2 2006.285.16:05:06.83#ibcon#flushed, iclass 21, count 2 2006.285.16:05:06.83#ibcon#about to write, iclass 21, count 2 2006.285.16:05:06.83#ibcon#wrote, iclass 21, count 2 2006.285.16:05:06.83#ibcon#about to read 3, iclass 21, count 2 2006.285.16:05:06.86#ibcon#read 3, iclass 21, count 2 2006.285.16:05:06.86#ibcon#about to read 4, iclass 21, count 2 2006.285.16:05:06.86#ibcon#read 4, iclass 21, count 2 2006.285.16:05:06.86#ibcon#about to read 5, iclass 21, count 2 2006.285.16:05:06.86#ibcon#read 5, iclass 21, count 2 2006.285.16:05:06.86#ibcon#about to read 6, iclass 21, count 2 2006.285.16:05:06.86#ibcon#read 6, iclass 21, count 2 2006.285.16:05:06.86#ibcon#end of sib2, iclass 21, count 2 2006.285.16:05:06.86#ibcon#*after write, iclass 21, count 2 2006.285.16:05:06.86#ibcon#*before return 0, iclass 21, count 2 2006.285.16:05:06.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:05:06.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:05:06.86#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.16:05:06.86#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:06.86#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:05:06.98#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:05:06.98#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:05:06.98#ibcon#enter wrdev, iclass 21, count 0 2006.285.16:05:06.98#ibcon#first serial, iclass 21, count 0 2006.285.16:05:06.98#ibcon#enter sib2, iclass 21, count 0 2006.285.16:05:06.98#ibcon#flushed, iclass 21, count 0 2006.285.16:05:06.98#ibcon#about to write, iclass 21, count 0 2006.285.16:05:06.98#ibcon#wrote, iclass 21, count 0 2006.285.16:05:06.98#ibcon#about to read 3, iclass 21, count 0 2006.285.16:05:07.00#ibcon#read 3, iclass 21, count 0 2006.285.16:05:07.00#ibcon#about to read 4, iclass 21, count 0 2006.285.16:05:07.00#ibcon#read 4, iclass 21, count 0 2006.285.16:05:07.00#ibcon#about to read 5, iclass 21, count 0 2006.285.16:05:07.00#ibcon#read 5, iclass 21, count 0 2006.285.16:05:07.00#ibcon#about to read 6, iclass 21, count 0 2006.285.16:05:07.00#ibcon#read 6, iclass 21, count 0 2006.285.16:05:07.00#ibcon#end of sib2, iclass 21, count 0 2006.285.16:05:07.00#ibcon#*mode == 0, iclass 21, count 0 2006.285.16:05:07.00#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.16:05:07.00#ibcon#[27=USB\r\n] 2006.285.16:05:07.00#ibcon#*before write, iclass 21, count 0 2006.285.16:05:07.00#ibcon#enter sib2, iclass 21, count 0 2006.285.16:05:07.00#ibcon#flushed, iclass 21, count 0 2006.285.16:05:07.00#ibcon#about to write, iclass 21, count 0 2006.285.16:05:07.00#ibcon#wrote, iclass 21, count 0 2006.285.16:05:07.00#ibcon#about to read 3, iclass 21, count 0 2006.285.16:05:07.03#ibcon#read 3, iclass 21, count 0 2006.285.16:05:07.03#ibcon#about to read 4, iclass 21, count 0 2006.285.16:05:07.03#ibcon#read 4, iclass 21, count 0 2006.285.16:05:07.03#ibcon#about to read 5, iclass 21, count 0 2006.285.16:05:07.03#ibcon#read 5, iclass 21, count 0 2006.285.16:05:07.03#ibcon#about to read 6, iclass 21, count 0 2006.285.16:05:07.03#ibcon#read 6, iclass 21, count 0 2006.285.16:05:07.03#ibcon#end of sib2, iclass 21, count 0 2006.285.16:05:07.03#ibcon#*after write, iclass 21, count 0 2006.285.16:05:07.03#ibcon#*before return 0, iclass 21, count 0 2006.285.16:05:07.03#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:05:07.03#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:05:07.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.16:05:07.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.16:05:07.03$vck44/vblo=3,649.99 2006.285.16:05:07.03#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.16:05:07.03#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.16:05:07.03#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:07.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:05:07.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:05:07.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:05:07.03#ibcon#enter wrdev, iclass 23, count 0 2006.285.16:05:07.03#ibcon#first serial, iclass 23, count 0 2006.285.16:05:07.03#ibcon#enter sib2, iclass 23, count 0 2006.285.16:05:07.03#ibcon#flushed, iclass 23, count 0 2006.285.16:05:07.03#ibcon#about to write, iclass 23, count 0 2006.285.16:05:07.03#ibcon#wrote, iclass 23, count 0 2006.285.16:05:07.03#ibcon#about to read 3, iclass 23, count 0 2006.285.16:05:07.05#ibcon#read 3, iclass 23, count 0 2006.285.16:05:07.05#ibcon#about to read 4, iclass 23, count 0 2006.285.16:05:07.05#ibcon#read 4, iclass 23, count 0 2006.285.16:05:07.05#ibcon#about to read 5, iclass 23, count 0 2006.285.16:05:07.05#ibcon#read 5, iclass 23, count 0 2006.285.16:05:07.05#ibcon#about to read 6, iclass 23, count 0 2006.285.16:05:07.05#ibcon#read 6, iclass 23, count 0 2006.285.16:05:07.05#ibcon#end of sib2, iclass 23, count 0 2006.285.16:05:07.05#ibcon#*mode == 0, iclass 23, count 0 2006.285.16:05:07.05#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.16:05:07.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.16:05:07.05#ibcon#*before write, iclass 23, count 0 2006.285.16:05:07.05#ibcon#enter sib2, iclass 23, count 0 2006.285.16:05:07.05#ibcon#flushed, iclass 23, count 0 2006.285.16:05:07.05#ibcon#about to write, iclass 23, count 0 2006.285.16:05:07.05#ibcon#wrote, iclass 23, count 0 2006.285.16:05:07.05#ibcon#about to read 3, iclass 23, count 0 2006.285.16:05:07.09#ibcon#read 3, iclass 23, count 0 2006.285.16:05:07.09#ibcon#about to read 4, iclass 23, count 0 2006.285.16:05:07.09#ibcon#read 4, iclass 23, count 0 2006.285.16:05:07.09#ibcon#about to read 5, iclass 23, count 0 2006.285.16:05:07.09#ibcon#read 5, iclass 23, count 0 2006.285.16:05:07.09#ibcon#about to read 6, iclass 23, count 0 2006.285.16:05:07.09#ibcon#read 6, iclass 23, count 0 2006.285.16:05:07.09#ibcon#end of sib2, iclass 23, count 0 2006.285.16:05:07.09#ibcon#*after write, iclass 23, count 0 2006.285.16:05:07.09#ibcon#*before return 0, iclass 23, count 0 2006.285.16:05:07.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:05:07.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:05:07.09#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.16:05:07.09#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.16:05:07.09$vck44/vb=3,4 2006.285.16:05:07.09#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.16:05:07.09#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.16:05:07.09#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:07.09#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:05:07.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:05:07.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:05:07.15#ibcon#enter wrdev, iclass 25, count 2 2006.285.16:05:07.15#ibcon#first serial, iclass 25, count 2 2006.285.16:05:07.15#ibcon#enter sib2, iclass 25, count 2 2006.285.16:05:07.15#ibcon#flushed, iclass 25, count 2 2006.285.16:05:07.15#ibcon#about to write, iclass 25, count 2 2006.285.16:05:07.15#ibcon#wrote, iclass 25, count 2 2006.285.16:05:07.15#ibcon#about to read 3, iclass 25, count 2 2006.285.16:05:07.17#ibcon#read 3, iclass 25, count 2 2006.285.16:05:07.17#ibcon#about to read 4, iclass 25, count 2 2006.285.16:05:07.17#ibcon#read 4, iclass 25, count 2 2006.285.16:05:07.17#ibcon#about to read 5, iclass 25, count 2 2006.285.16:05:07.17#ibcon#read 5, iclass 25, count 2 2006.285.16:05:07.17#ibcon#about to read 6, iclass 25, count 2 2006.285.16:05:07.17#ibcon#read 6, iclass 25, count 2 2006.285.16:05:07.17#ibcon#end of sib2, iclass 25, count 2 2006.285.16:05:07.17#ibcon#*mode == 0, iclass 25, count 2 2006.285.16:05:07.17#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.16:05:07.17#ibcon#[27=AT03-04\r\n] 2006.285.16:05:07.17#ibcon#*before write, iclass 25, count 2 2006.285.16:05:07.17#ibcon#enter sib2, iclass 25, count 2 2006.285.16:05:07.17#ibcon#flushed, iclass 25, count 2 2006.285.16:05:07.17#ibcon#about to write, iclass 25, count 2 2006.285.16:05:07.17#ibcon#wrote, iclass 25, count 2 2006.285.16:05:07.17#ibcon#about to read 3, iclass 25, count 2 2006.285.16:05:07.20#ibcon#read 3, iclass 25, count 2 2006.285.16:05:07.20#ibcon#about to read 4, iclass 25, count 2 2006.285.16:05:07.20#ibcon#read 4, iclass 25, count 2 2006.285.16:05:07.20#ibcon#about to read 5, iclass 25, count 2 2006.285.16:05:07.20#ibcon#read 5, iclass 25, count 2 2006.285.16:05:07.20#ibcon#about to read 6, iclass 25, count 2 2006.285.16:05:07.20#ibcon#read 6, iclass 25, count 2 2006.285.16:05:07.20#ibcon#end of sib2, iclass 25, count 2 2006.285.16:05:07.20#ibcon#*after write, iclass 25, count 2 2006.285.16:05:07.20#ibcon#*before return 0, iclass 25, count 2 2006.285.16:05:07.20#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:05:07.20#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:05:07.20#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.16:05:07.20#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:07.20#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:05:07.32#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:05:07.32#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:05:07.32#ibcon#enter wrdev, iclass 25, count 0 2006.285.16:05:07.32#ibcon#first serial, iclass 25, count 0 2006.285.16:05:07.32#ibcon#enter sib2, iclass 25, count 0 2006.285.16:05:07.32#ibcon#flushed, iclass 25, count 0 2006.285.16:05:07.32#ibcon#about to write, iclass 25, count 0 2006.285.16:05:07.32#ibcon#wrote, iclass 25, count 0 2006.285.16:05:07.32#ibcon#about to read 3, iclass 25, count 0 2006.285.16:05:07.34#ibcon#read 3, iclass 25, count 0 2006.285.16:05:07.34#ibcon#about to read 4, iclass 25, count 0 2006.285.16:05:07.34#ibcon#read 4, iclass 25, count 0 2006.285.16:05:07.34#ibcon#about to read 5, iclass 25, count 0 2006.285.16:05:07.34#ibcon#read 5, iclass 25, count 0 2006.285.16:05:07.34#ibcon#about to read 6, iclass 25, count 0 2006.285.16:05:07.34#ibcon#read 6, iclass 25, count 0 2006.285.16:05:07.34#ibcon#end of sib2, iclass 25, count 0 2006.285.16:05:07.34#ibcon#*mode == 0, iclass 25, count 0 2006.285.16:05:07.34#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.16:05:07.34#ibcon#[27=USB\r\n] 2006.285.16:05:07.34#ibcon#*before write, iclass 25, count 0 2006.285.16:05:07.34#ibcon#enter sib2, iclass 25, count 0 2006.285.16:05:07.34#ibcon#flushed, iclass 25, count 0 2006.285.16:05:07.34#ibcon#about to write, iclass 25, count 0 2006.285.16:05:07.34#ibcon#wrote, iclass 25, count 0 2006.285.16:05:07.34#ibcon#about to read 3, iclass 25, count 0 2006.285.16:05:07.37#ibcon#read 3, iclass 25, count 0 2006.285.16:05:07.37#ibcon#about to read 4, iclass 25, count 0 2006.285.16:05:07.37#ibcon#read 4, iclass 25, count 0 2006.285.16:05:07.37#ibcon#about to read 5, iclass 25, count 0 2006.285.16:05:07.37#ibcon#read 5, iclass 25, count 0 2006.285.16:05:07.37#ibcon#about to read 6, iclass 25, count 0 2006.285.16:05:07.37#ibcon#read 6, iclass 25, count 0 2006.285.16:05:07.37#ibcon#end of sib2, iclass 25, count 0 2006.285.16:05:07.37#ibcon#*after write, iclass 25, count 0 2006.285.16:05:07.37#ibcon#*before return 0, iclass 25, count 0 2006.285.16:05:07.37#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:05:07.37#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:05:07.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.16:05:07.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.16:05:07.37$vck44/vblo=4,679.99 2006.285.16:05:07.37#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.16:05:07.37#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.16:05:07.37#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:07.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:05:07.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:05:07.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:05:07.37#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:05:07.37#ibcon#first serial, iclass 27, count 0 2006.285.16:05:07.37#ibcon#enter sib2, iclass 27, count 0 2006.285.16:05:07.37#ibcon#flushed, iclass 27, count 0 2006.285.16:05:07.37#ibcon#about to write, iclass 27, count 0 2006.285.16:05:07.37#ibcon#wrote, iclass 27, count 0 2006.285.16:05:07.37#ibcon#about to read 3, iclass 27, count 0 2006.285.16:05:07.39#ibcon#read 3, iclass 27, count 0 2006.285.16:05:07.44#ibcon#about to read 4, iclass 27, count 0 2006.285.16:05:07.44#ibcon#read 4, iclass 27, count 0 2006.285.16:05:07.44#ibcon#about to read 5, iclass 27, count 0 2006.285.16:05:07.44#ibcon#read 5, iclass 27, count 0 2006.285.16:05:07.44#ibcon#about to read 6, iclass 27, count 0 2006.285.16:05:07.44#ibcon#read 6, iclass 27, count 0 2006.285.16:05:07.44#ibcon#end of sib2, iclass 27, count 0 2006.285.16:05:07.44#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:05:07.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:05:07.44#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.16:05:07.44#ibcon#*before write, iclass 27, count 0 2006.285.16:05:07.44#ibcon#enter sib2, iclass 27, count 0 2006.285.16:05:07.44#ibcon#flushed, iclass 27, count 0 2006.285.16:05:07.44#ibcon#about to write, iclass 27, count 0 2006.285.16:05:07.44#ibcon#wrote, iclass 27, count 0 2006.285.16:05:07.44#ibcon#about to read 3, iclass 27, count 0 2006.285.16:05:07.48#ibcon#read 3, iclass 27, count 0 2006.285.16:05:07.48#ibcon#about to read 4, iclass 27, count 0 2006.285.16:05:07.48#ibcon#read 4, iclass 27, count 0 2006.285.16:05:07.48#ibcon#about to read 5, iclass 27, count 0 2006.285.16:05:07.48#ibcon#read 5, iclass 27, count 0 2006.285.16:05:07.48#ibcon#about to read 6, iclass 27, count 0 2006.285.16:05:07.48#ibcon#read 6, iclass 27, count 0 2006.285.16:05:07.48#ibcon#end of sib2, iclass 27, count 0 2006.285.16:05:07.48#ibcon#*after write, iclass 27, count 0 2006.285.16:05:07.48#ibcon#*before return 0, iclass 27, count 0 2006.285.16:05:07.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:05:07.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:05:07.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:05:07.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:05:07.48$vck44/vb=4,5 2006.285.16:05:07.48#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.16:05:07.48#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.16:05:07.48#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:07.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:05:07.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:05:07.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:05:07.48#ibcon#enter wrdev, iclass 29, count 2 2006.285.16:05:07.48#ibcon#first serial, iclass 29, count 2 2006.285.16:05:07.48#ibcon#enter sib2, iclass 29, count 2 2006.285.16:05:07.48#ibcon#flushed, iclass 29, count 2 2006.285.16:05:07.48#ibcon#about to write, iclass 29, count 2 2006.285.16:05:07.48#ibcon#wrote, iclass 29, count 2 2006.285.16:05:07.48#ibcon#about to read 3, iclass 29, count 2 2006.285.16:05:07.50#ibcon#read 3, iclass 29, count 2 2006.285.16:05:07.50#ibcon#about to read 4, iclass 29, count 2 2006.285.16:05:07.50#ibcon#read 4, iclass 29, count 2 2006.285.16:05:07.50#ibcon#about to read 5, iclass 29, count 2 2006.285.16:05:07.50#ibcon#read 5, iclass 29, count 2 2006.285.16:05:07.50#ibcon#about to read 6, iclass 29, count 2 2006.285.16:05:07.50#ibcon#read 6, iclass 29, count 2 2006.285.16:05:07.50#ibcon#end of sib2, iclass 29, count 2 2006.285.16:05:07.50#ibcon#*mode == 0, iclass 29, count 2 2006.285.16:05:07.50#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.16:05:07.50#ibcon#[27=AT04-05\r\n] 2006.285.16:05:07.50#ibcon#*before write, iclass 29, count 2 2006.285.16:05:07.50#ibcon#enter sib2, iclass 29, count 2 2006.285.16:05:07.50#ibcon#flushed, iclass 29, count 2 2006.285.16:05:07.50#ibcon#about to write, iclass 29, count 2 2006.285.16:05:07.50#ibcon#wrote, iclass 29, count 2 2006.285.16:05:07.50#ibcon#about to read 3, iclass 29, count 2 2006.285.16:05:07.53#ibcon#read 3, iclass 29, count 2 2006.285.16:05:07.53#ibcon#about to read 4, iclass 29, count 2 2006.285.16:05:07.53#ibcon#read 4, iclass 29, count 2 2006.285.16:05:07.53#ibcon#about to read 5, iclass 29, count 2 2006.285.16:05:07.53#ibcon#read 5, iclass 29, count 2 2006.285.16:05:07.53#ibcon#about to read 6, iclass 29, count 2 2006.285.16:05:07.53#ibcon#read 6, iclass 29, count 2 2006.285.16:05:07.53#ibcon#end of sib2, iclass 29, count 2 2006.285.16:05:07.53#ibcon#*after write, iclass 29, count 2 2006.285.16:05:07.53#ibcon#*before return 0, iclass 29, count 2 2006.285.16:05:07.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:05:07.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:05:07.53#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.16:05:07.53#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:07.53#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:05:07.65#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:05:07.65#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:05:07.65#ibcon#enter wrdev, iclass 29, count 0 2006.285.16:05:07.65#ibcon#first serial, iclass 29, count 0 2006.285.16:05:07.65#ibcon#enter sib2, iclass 29, count 0 2006.285.16:05:07.65#ibcon#flushed, iclass 29, count 0 2006.285.16:05:07.65#ibcon#about to write, iclass 29, count 0 2006.285.16:05:07.65#ibcon#wrote, iclass 29, count 0 2006.285.16:05:07.65#ibcon#about to read 3, iclass 29, count 0 2006.285.16:05:07.67#ibcon#read 3, iclass 29, count 0 2006.285.16:05:07.67#ibcon#about to read 4, iclass 29, count 0 2006.285.16:05:07.67#ibcon#read 4, iclass 29, count 0 2006.285.16:05:07.67#ibcon#about to read 5, iclass 29, count 0 2006.285.16:05:07.67#ibcon#read 5, iclass 29, count 0 2006.285.16:05:07.67#ibcon#about to read 6, iclass 29, count 0 2006.285.16:05:07.67#ibcon#read 6, iclass 29, count 0 2006.285.16:05:07.67#ibcon#end of sib2, iclass 29, count 0 2006.285.16:05:07.67#ibcon#*mode == 0, iclass 29, count 0 2006.285.16:05:07.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.16:05:07.67#ibcon#[27=USB\r\n] 2006.285.16:05:07.67#ibcon#*before write, iclass 29, count 0 2006.285.16:05:07.67#ibcon#enter sib2, iclass 29, count 0 2006.285.16:05:07.67#ibcon#flushed, iclass 29, count 0 2006.285.16:05:07.67#ibcon#about to write, iclass 29, count 0 2006.285.16:05:07.67#ibcon#wrote, iclass 29, count 0 2006.285.16:05:07.67#ibcon#about to read 3, iclass 29, count 0 2006.285.16:05:07.70#ibcon#read 3, iclass 29, count 0 2006.285.16:05:07.70#ibcon#about to read 4, iclass 29, count 0 2006.285.16:05:07.70#ibcon#read 4, iclass 29, count 0 2006.285.16:05:07.70#ibcon#about to read 5, iclass 29, count 0 2006.285.16:05:07.70#ibcon#read 5, iclass 29, count 0 2006.285.16:05:07.70#ibcon#about to read 6, iclass 29, count 0 2006.285.16:05:07.70#ibcon#read 6, iclass 29, count 0 2006.285.16:05:07.70#ibcon#end of sib2, iclass 29, count 0 2006.285.16:05:07.70#ibcon#*after write, iclass 29, count 0 2006.285.16:05:07.70#ibcon#*before return 0, iclass 29, count 0 2006.285.16:05:07.70#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:05:07.70#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:05:07.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.16:05:07.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.16:05:07.70$vck44/vblo=5,709.99 2006.285.16:05:07.70#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.16:05:07.70#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.16:05:07.70#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:07.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:05:07.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:05:07.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:05:07.70#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:05:07.70#ibcon#first serial, iclass 31, count 0 2006.285.16:05:07.70#ibcon#enter sib2, iclass 31, count 0 2006.285.16:05:07.70#ibcon#flushed, iclass 31, count 0 2006.285.16:05:07.70#ibcon#about to write, iclass 31, count 0 2006.285.16:05:07.70#ibcon#wrote, iclass 31, count 0 2006.285.16:05:07.70#ibcon#about to read 3, iclass 31, count 0 2006.285.16:05:07.72#ibcon#read 3, iclass 31, count 0 2006.285.16:05:07.72#ibcon#about to read 4, iclass 31, count 0 2006.285.16:05:07.72#ibcon#read 4, iclass 31, count 0 2006.285.16:05:07.72#ibcon#about to read 5, iclass 31, count 0 2006.285.16:05:07.72#ibcon#read 5, iclass 31, count 0 2006.285.16:05:07.72#ibcon#about to read 6, iclass 31, count 0 2006.285.16:05:07.72#ibcon#read 6, iclass 31, count 0 2006.285.16:05:07.72#ibcon#end of sib2, iclass 31, count 0 2006.285.16:05:07.72#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:05:07.72#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:05:07.72#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.16:05:07.72#ibcon#*before write, iclass 31, count 0 2006.285.16:05:07.72#ibcon#enter sib2, iclass 31, count 0 2006.285.16:05:07.72#ibcon#flushed, iclass 31, count 0 2006.285.16:05:07.72#ibcon#about to write, iclass 31, count 0 2006.285.16:05:07.72#ibcon#wrote, iclass 31, count 0 2006.285.16:05:07.72#ibcon#about to read 3, iclass 31, count 0 2006.285.16:05:07.76#ibcon#read 3, iclass 31, count 0 2006.285.16:05:07.76#ibcon#about to read 4, iclass 31, count 0 2006.285.16:05:07.76#ibcon#read 4, iclass 31, count 0 2006.285.16:05:07.76#ibcon#about to read 5, iclass 31, count 0 2006.285.16:05:07.76#ibcon#read 5, iclass 31, count 0 2006.285.16:05:07.76#ibcon#about to read 6, iclass 31, count 0 2006.285.16:05:07.76#ibcon#read 6, iclass 31, count 0 2006.285.16:05:07.76#ibcon#end of sib2, iclass 31, count 0 2006.285.16:05:07.76#ibcon#*after write, iclass 31, count 0 2006.285.16:05:07.76#ibcon#*before return 0, iclass 31, count 0 2006.285.16:05:07.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:05:07.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:05:07.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:05:07.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:05:07.76$vck44/vb=5,4 2006.285.16:05:07.76#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.16:05:07.76#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.16:05:07.76#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:07.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:05:07.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:05:07.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:05:07.82#ibcon#enter wrdev, iclass 33, count 2 2006.285.16:05:07.82#ibcon#first serial, iclass 33, count 2 2006.285.16:05:07.82#ibcon#enter sib2, iclass 33, count 2 2006.285.16:05:07.82#ibcon#flushed, iclass 33, count 2 2006.285.16:05:07.82#ibcon#about to write, iclass 33, count 2 2006.285.16:05:07.82#ibcon#wrote, iclass 33, count 2 2006.285.16:05:07.82#ibcon#about to read 3, iclass 33, count 2 2006.285.16:05:07.84#ibcon#read 3, iclass 33, count 2 2006.285.16:05:07.84#ibcon#about to read 4, iclass 33, count 2 2006.285.16:05:07.84#ibcon#read 4, iclass 33, count 2 2006.285.16:05:07.84#ibcon#about to read 5, iclass 33, count 2 2006.285.16:05:07.84#ibcon#read 5, iclass 33, count 2 2006.285.16:05:07.84#ibcon#about to read 6, iclass 33, count 2 2006.285.16:05:07.84#ibcon#read 6, iclass 33, count 2 2006.285.16:05:07.84#ibcon#end of sib2, iclass 33, count 2 2006.285.16:05:07.84#ibcon#*mode == 0, iclass 33, count 2 2006.285.16:05:07.84#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.16:05:07.84#ibcon#[27=AT05-04\r\n] 2006.285.16:05:07.84#ibcon#*before write, iclass 33, count 2 2006.285.16:05:07.84#ibcon#enter sib2, iclass 33, count 2 2006.285.16:05:07.84#ibcon#flushed, iclass 33, count 2 2006.285.16:05:07.84#ibcon#about to write, iclass 33, count 2 2006.285.16:05:07.84#ibcon#wrote, iclass 33, count 2 2006.285.16:05:07.84#ibcon#about to read 3, iclass 33, count 2 2006.285.16:05:07.87#ibcon#read 3, iclass 33, count 2 2006.285.16:05:07.87#ibcon#about to read 4, iclass 33, count 2 2006.285.16:05:07.87#ibcon#read 4, iclass 33, count 2 2006.285.16:05:07.87#ibcon#about to read 5, iclass 33, count 2 2006.285.16:05:07.87#ibcon#read 5, iclass 33, count 2 2006.285.16:05:07.87#ibcon#about to read 6, iclass 33, count 2 2006.285.16:05:07.87#ibcon#read 6, iclass 33, count 2 2006.285.16:05:07.87#ibcon#end of sib2, iclass 33, count 2 2006.285.16:05:07.87#ibcon#*after write, iclass 33, count 2 2006.285.16:05:07.87#ibcon#*before return 0, iclass 33, count 2 2006.285.16:05:07.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:05:07.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:05:07.87#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.16:05:07.87#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:07.87#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:05:07.99#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:05:07.99#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:05:07.99#ibcon#enter wrdev, iclass 33, count 0 2006.285.16:05:07.99#ibcon#first serial, iclass 33, count 0 2006.285.16:05:07.99#ibcon#enter sib2, iclass 33, count 0 2006.285.16:05:07.99#ibcon#flushed, iclass 33, count 0 2006.285.16:05:07.99#ibcon#about to write, iclass 33, count 0 2006.285.16:05:07.99#ibcon#wrote, iclass 33, count 0 2006.285.16:05:07.99#ibcon#about to read 3, iclass 33, count 0 2006.285.16:05:08.01#ibcon#read 3, iclass 33, count 0 2006.285.16:05:08.01#ibcon#about to read 4, iclass 33, count 0 2006.285.16:05:08.01#ibcon#read 4, iclass 33, count 0 2006.285.16:05:08.01#ibcon#about to read 5, iclass 33, count 0 2006.285.16:05:08.01#ibcon#read 5, iclass 33, count 0 2006.285.16:05:08.01#ibcon#about to read 6, iclass 33, count 0 2006.285.16:05:08.01#ibcon#read 6, iclass 33, count 0 2006.285.16:05:08.01#ibcon#end of sib2, iclass 33, count 0 2006.285.16:05:08.01#ibcon#*mode == 0, iclass 33, count 0 2006.285.16:05:08.01#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.16:05:08.01#ibcon#[27=USB\r\n] 2006.285.16:05:08.01#ibcon#*before write, iclass 33, count 0 2006.285.16:05:08.01#ibcon#enter sib2, iclass 33, count 0 2006.285.16:05:08.01#ibcon#flushed, iclass 33, count 0 2006.285.16:05:08.01#ibcon#about to write, iclass 33, count 0 2006.285.16:05:08.01#ibcon#wrote, iclass 33, count 0 2006.285.16:05:08.01#ibcon#about to read 3, iclass 33, count 0 2006.285.16:05:08.04#ibcon#read 3, iclass 33, count 0 2006.285.16:05:08.04#ibcon#about to read 4, iclass 33, count 0 2006.285.16:05:08.04#ibcon#read 4, iclass 33, count 0 2006.285.16:05:08.04#ibcon#about to read 5, iclass 33, count 0 2006.285.16:05:08.04#ibcon#read 5, iclass 33, count 0 2006.285.16:05:08.04#ibcon#about to read 6, iclass 33, count 0 2006.285.16:05:08.04#ibcon#read 6, iclass 33, count 0 2006.285.16:05:08.04#ibcon#end of sib2, iclass 33, count 0 2006.285.16:05:08.04#ibcon#*after write, iclass 33, count 0 2006.285.16:05:08.04#ibcon#*before return 0, iclass 33, count 0 2006.285.16:05:08.04#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:05:08.04#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:05:08.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.16:05:08.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.16:05:08.04$vck44/vblo=6,719.99 2006.285.16:05:08.04#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.16:05:08.04#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.16:05:08.04#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:08.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:05:08.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:05:08.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:05:08.04#ibcon#enter wrdev, iclass 35, count 0 2006.285.16:05:08.04#ibcon#first serial, iclass 35, count 0 2006.285.16:05:08.04#ibcon#enter sib2, iclass 35, count 0 2006.285.16:05:08.04#ibcon#flushed, iclass 35, count 0 2006.285.16:05:08.04#ibcon#about to write, iclass 35, count 0 2006.285.16:05:08.04#ibcon#wrote, iclass 35, count 0 2006.285.16:05:08.04#ibcon#about to read 3, iclass 35, count 0 2006.285.16:05:08.06#ibcon#read 3, iclass 35, count 0 2006.285.16:05:08.06#ibcon#about to read 4, iclass 35, count 0 2006.285.16:05:08.06#ibcon#read 4, iclass 35, count 0 2006.285.16:05:08.06#ibcon#about to read 5, iclass 35, count 0 2006.285.16:05:08.06#ibcon#read 5, iclass 35, count 0 2006.285.16:05:08.06#ibcon#about to read 6, iclass 35, count 0 2006.285.16:05:08.06#ibcon#read 6, iclass 35, count 0 2006.285.16:05:08.06#ibcon#end of sib2, iclass 35, count 0 2006.285.16:05:08.06#ibcon#*mode == 0, iclass 35, count 0 2006.285.16:05:08.06#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.16:05:08.06#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.16:05:08.06#ibcon#*before write, iclass 35, count 0 2006.285.16:05:08.06#ibcon#enter sib2, iclass 35, count 0 2006.285.16:05:08.06#ibcon#flushed, iclass 35, count 0 2006.285.16:05:08.06#ibcon#about to write, iclass 35, count 0 2006.285.16:05:08.06#ibcon#wrote, iclass 35, count 0 2006.285.16:05:08.06#ibcon#about to read 3, iclass 35, count 0 2006.285.16:05:08.10#ibcon#read 3, iclass 35, count 0 2006.285.16:05:08.10#ibcon#about to read 4, iclass 35, count 0 2006.285.16:05:08.10#ibcon#read 4, iclass 35, count 0 2006.285.16:05:08.10#ibcon#about to read 5, iclass 35, count 0 2006.285.16:05:08.10#ibcon#read 5, iclass 35, count 0 2006.285.16:05:08.10#ibcon#about to read 6, iclass 35, count 0 2006.285.16:05:08.10#ibcon#read 6, iclass 35, count 0 2006.285.16:05:08.10#ibcon#end of sib2, iclass 35, count 0 2006.285.16:05:08.10#ibcon#*after write, iclass 35, count 0 2006.285.16:05:08.10#ibcon#*before return 0, iclass 35, count 0 2006.285.16:05:08.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:05:08.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:05:08.10#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.16:05:08.10#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.16:05:08.10$vck44/vb=6,3 2006.285.16:05:08.10#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.16:05:08.10#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.16:05:08.10#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:08.10#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:05:08.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:05:08.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:05:08.16#ibcon#enter wrdev, iclass 37, count 2 2006.285.16:05:08.16#ibcon#first serial, iclass 37, count 2 2006.285.16:05:08.16#ibcon#enter sib2, iclass 37, count 2 2006.285.16:05:08.16#ibcon#flushed, iclass 37, count 2 2006.285.16:05:08.16#ibcon#about to write, iclass 37, count 2 2006.285.16:05:08.16#ibcon#wrote, iclass 37, count 2 2006.285.16:05:08.16#ibcon#about to read 3, iclass 37, count 2 2006.285.16:05:08.18#ibcon#read 3, iclass 37, count 2 2006.285.16:05:08.18#ibcon#about to read 4, iclass 37, count 2 2006.285.16:05:08.18#ibcon#read 4, iclass 37, count 2 2006.285.16:05:08.18#ibcon#about to read 5, iclass 37, count 2 2006.285.16:05:08.18#ibcon#read 5, iclass 37, count 2 2006.285.16:05:08.18#ibcon#about to read 6, iclass 37, count 2 2006.285.16:05:08.18#ibcon#read 6, iclass 37, count 2 2006.285.16:05:08.18#ibcon#end of sib2, iclass 37, count 2 2006.285.16:05:08.18#ibcon#*mode == 0, iclass 37, count 2 2006.285.16:05:08.18#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.16:05:08.18#ibcon#[27=AT06-03\r\n] 2006.285.16:05:08.18#ibcon#*before write, iclass 37, count 2 2006.285.16:05:08.18#ibcon#enter sib2, iclass 37, count 2 2006.285.16:05:08.18#ibcon#flushed, iclass 37, count 2 2006.285.16:05:08.18#ibcon#about to write, iclass 37, count 2 2006.285.16:05:08.18#ibcon#wrote, iclass 37, count 2 2006.285.16:05:08.18#ibcon#about to read 3, iclass 37, count 2 2006.285.16:05:08.21#ibcon#read 3, iclass 37, count 2 2006.285.16:05:08.21#ibcon#about to read 4, iclass 37, count 2 2006.285.16:05:08.21#ibcon#read 4, iclass 37, count 2 2006.285.16:05:08.21#ibcon#about to read 5, iclass 37, count 2 2006.285.16:05:08.21#ibcon#read 5, iclass 37, count 2 2006.285.16:05:08.21#ibcon#about to read 6, iclass 37, count 2 2006.285.16:05:08.21#ibcon#read 6, iclass 37, count 2 2006.285.16:05:08.21#ibcon#end of sib2, iclass 37, count 2 2006.285.16:05:08.21#ibcon#*after write, iclass 37, count 2 2006.285.16:05:08.21#ibcon#*before return 0, iclass 37, count 2 2006.285.16:05:08.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:05:08.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:05:08.21#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.16:05:08.21#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:08.21#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:05:08.33#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:05:08.33#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:05:08.33#ibcon#enter wrdev, iclass 37, count 0 2006.285.16:05:08.33#ibcon#first serial, iclass 37, count 0 2006.285.16:05:08.33#ibcon#enter sib2, iclass 37, count 0 2006.285.16:05:08.33#ibcon#flushed, iclass 37, count 0 2006.285.16:05:08.33#ibcon#about to write, iclass 37, count 0 2006.285.16:05:08.33#ibcon#wrote, iclass 37, count 0 2006.285.16:05:08.33#ibcon#about to read 3, iclass 37, count 0 2006.285.16:05:08.35#ibcon#read 3, iclass 37, count 0 2006.285.16:05:08.35#ibcon#about to read 4, iclass 37, count 0 2006.285.16:05:08.35#ibcon#read 4, iclass 37, count 0 2006.285.16:05:08.35#ibcon#about to read 5, iclass 37, count 0 2006.285.16:05:08.35#ibcon#read 5, iclass 37, count 0 2006.285.16:05:08.35#ibcon#about to read 6, iclass 37, count 0 2006.285.16:05:08.35#ibcon#read 6, iclass 37, count 0 2006.285.16:05:08.35#ibcon#end of sib2, iclass 37, count 0 2006.285.16:05:08.35#ibcon#*mode == 0, iclass 37, count 0 2006.285.16:05:08.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.16:05:08.35#ibcon#[27=USB\r\n] 2006.285.16:05:08.35#ibcon#*before write, iclass 37, count 0 2006.285.16:05:08.35#ibcon#enter sib2, iclass 37, count 0 2006.285.16:05:08.35#ibcon#flushed, iclass 37, count 0 2006.285.16:05:08.35#ibcon#about to write, iclass 37, count 0 2006.285.16:05:08.35#ibcon#wrote, iclass 37, count 0 2006.285.16:05:08.35#ibcon#about to read 3, iclass 37, count 0 2006.285.16:05:08.38#ibcon#read 3, iclass 37, count 0 2006.285.16:05:08.38#ibcon#about to read 4, iclass 37, count 0 2006.285.16:05:08.38#ibcon#read 4, iclass 37, count 0 2006.285.16:05:08.38#ibcon#about to read 5, iclass 37, count 0 2006.285.16:05:08.38#ibcon#read 5, iclass 37, count 0 2006.285.16:05:08.38#ibcon#about to read 6, iclass 37, count 0 2006.285.16:05:08.38#ibcon#read 6, iclass 37, count 0 2006.285.16:05:08.38#ibcon#end of sib2, iclass 37, count 0 2006.285.16:05:08.38#ibcon#*after write, iclass 37, count 0 2006.285.16:05:08.38#ibcon#*before return 0, iclass 37, count 0 2006.285.16:05:08.38#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:05:08.38#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:05:08.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.16:05:08.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.16:05:08.38$vck44/vblo=7,734.99 2006.285.16:05:08.38#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.16:05:08.38#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.16:05:08.38#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:08.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:05:08.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:05:08.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:05:08.38#ibcon#enter wrdev, iclass 39, count 0 2006.285.16:05:08.38#ibcon#first serial, iclass 39, count 0 2006.285.16:05:08.38#ibcon#enter sib2, iclass 39, count 0 2006.285.16:05:08.38#ibcon#flushed, iclass 39, count 0 2006.285.16:05:08.38#ibcon#about to write, iclass 39, count 0 2006.285.16:05:08.38#ibcon#wrote, iclass 39, count 0 2006.285.16:05:08.38#ibcon#about to read 3, iclass 39, count 0 2006.285.16:05:08.40#ibcon#read 3, iclass 39, count 0 2006.285.16:05:08.47#ibcon#about to read 4, iclass 39, count 0 2006.285.16:05:08.47#ibcon#read 4, iclass 39, count 0 2006.285.16:05:08.47#ibcon#about to read 5, iclass 39, count 0 2006.285.16:05:08.47#ibcon#read 5, iclass 39, count 0 2006.285.16:05:08.47#ibcon#about to read 6, iclass 39, count 0 2006.285.16:05:08.47#ibcon#read 6, iclass 39, count 0 2006.285.16:05:08.47#ibcon#end of sib2, iclass 39, count 0 2006.285.16:05:08.47#ibcon#*mode == 0, iclass 39, count 0 2006.285.16:05:08.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.16:05:08.47#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.16:05:08.47#ibcon#*before write, iclass 39, count 0 2006.285.16:05:08.47#ibcon#enter sib2, iclass 39, count 0 2006.285.16:05:08.47#ibcon#flushed, iclass 39, count 0 2006.285.16:05:08.47#ibcon#about to write, iclass 39, count 0 2006.285.16:05:08.47#ibcon#wrote, iclass 39, count 0 2006.285.16:05:08.47#ibcon#about to read 3, iclass 39, count 0 2006.285.16:05:08.51#ibcon#read 3, iclass 39, count 0 2006.285.16:05:08.51#ibcon#about to read 4, iclass 39, count 0 2006.285.16:05:08.51#ibcon#read 4, iclass 39, count 0 2006.285.16:05:08.51#ibcon#about to read 5, iclass 39, count 0 2006.285.16:05:08.51#ibcon#read 5, iclass 39, count 0 2006.285.16:05:08.51#ibcon#about to read 6, iclass 39, count 0 2006.285.16:05:08.51#ibcon#read 6, iclass 39, count 0 2006.285.16:05:08.51#ibcon#end of sib2, iclass 39, count 0 2006.285.16:05:08.51#ibcon#*after write, iclass 39, count 0 2006.285.16:05:08.51#ibcon#*before return 0, iclass 39, count 0 2006.285.16:05:08.51#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:05:08.51#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:05:08.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.16:05:08.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.16:05:08.51$vck44/vb=7,4 2006.285.16:05:08.51#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.16:05:08.51#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.16:05:08.51#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:08.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:05:08.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:05:08.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:05:08.51#ibcon#enter wrdev, iclass 3, count 2 2006.285.16:05:08.51#ibcon#first serial, iclass 3, count 2 2006.285.16:05:08.51#ibcon#enter sib2, iclass 3, count 2 2006.285.16:05:08.51#ibcon#flushed, iclass 3, count 2 2006.285.16:05:08.51#ibcon#about to write, iclass 3, count 2 2006.285.16:05:08.51#ibcon#wrote, iclass 3, count 2 2006.285.16:05:08.51#ibcon#about to read 3, iclass 3, count 2 2006.285.16:05:08.53#ibcon#read 3, iclass 3, count 2 2006.285.16:05:08.53#ibcon#about to read 4, iclass 3, count 2 2006.285.16:05:08.53#ibcon#read 4, iclass 3, count 2 2006.285.16:05:08.53#ibcon#about to read 5, iclass 3, count 2 2006.285.16:05:08.53#ibcon#read 5, iclass 3, count 2 2006.285.16:05:08.53#ibcon#about to read 6, iclass 3, count 2 2006.285.16:05:08.53#ibcon#read 6, iclass 3, count 2 2006.285.16:05:08.53#ibcon#end of sib2, iclass 3, count 2 2006.285.16:05:08.53#ibcon#*mode == 0, iclass 3, count 2 2006.285.16:05:08.53#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.16:05:08.53#ibcon#[27=AT07-04\r\n] 2006.285.16:05:08.53#ibcon#*before write, iclass 3, count 2 2006.285.16:05:08.53#ibcon#enter sib2, iclass 3, count 2 2006.285.16:05:08.53#ibcon#flushed, iclass 3, count 2 2006.285.16:05:08.53#ibcon#about to write, iclass 3, count 2 2006.285.16:05:08.53#ibcon#wrote, iclass 3, count 2 2006.285.16:05:08.53#ibcon#about to read 3, iclass 3, count 2 2006.285.16:05:08.56#ibcon#read 3, iclass 3, count 2 2006.285.16:05:08.56#ibcon#about to read 4, iclass 3, count 2 2006.285.16:05:08.56#ibcon#read 4, iclass 3, count 2 2006.285.16:05:08.56#ibcon#about to read 5, iclass 3, count 2 2006.285.16:05:08.56#ibcon#read 5, iclass 3, count 2 2006.285.16:05:08.56#ibcon#about to read 6, iclass 3, count 2 2006.285.16:05:08.56#ibcon#read 6, iclass 3, count 2 2006.285.16:05:08.56#ibcon#end of sib2, iclass 3, count 2 2006.285.16:05:08.56#ibcon#*after write, iclass 3, count 2 2006.285.16:05:08.56#ibcon#*before return 0, iclass 3, count 2 2006.285.16:05:08.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:05:08.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:05:08.56#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.16:05:08.56#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:08.56#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:05:08.68#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:05:08.68#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:05:08.68#ibcon#enter wrdev, iclass 3, count 0 2006.285.16:05:08.68#ibcon#first serial, iclass 3, count 0 2006.285.16:05:08.68#ibcon#enter sib2, iclass 3, count 0 2006.285.16:05:08.68#ibcon#flushed, iclass 3, count 0 2006.285.16:05:08.68#ibcon#about to write, iclass 3, count 0 2006.285.16:05:08.68#ibcon#wrote, iclass 3, count 0 2006.285.16:05:08.68#ibcon#about to read 3, iclass 3, count 0 2006.285.16:05:08.70#ibcon#read 3, iclass 3, count 0 2006.285.16:05:08.70#ibcon#about to read 4, iclass 3, count 0 2006.285.16:05:08.70#ibcon#read 4, iclass 3, count 0 2006.285.16:05:08.70#ibcon#about to read 5, iclass 3, count 0 2006.285.16:05:08.70#ibcon#read 5, iclass 3, count 0 2006.285.16:05:08.70#ibcon#about to read 6, iclass 3, count 0 2006.285.16:05:08.70#ibcon#read 6, iclass 3, count 0 2006.285.16:05:08.70#ibcon#end of sib2, iclass 3, count 0 2006.285.16:05:08.70#ibcon#*mode == 0, iclass 3, count 0 2006.285.16:05:08.70#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.16:05:08.70#ibcon#[27=USB\r\n] 2006.285.16:05:08.70#ibcon#*before write, iclass 3, count 0 2006.285.16:05:08.70#ibcon#enter sib2, iclass 3, count 0 2006.285.16:05:08.70#ibcon#flushed, iclass 3, count 0 2006.285.16:05:08.70#ibcon#about to write, iclass 3, count 0 2006.285.16:05:08.70#ibcon#wrote, iclass 3, count 0 2006.285.16:05:08.70#ibcon#about to read 3, iclass 3, count 0 2006.285.16:05:08.73#ibcon#read 3, iclass 3, count 0 2006.285.16:05:08.73#ibcon#about to read 4, iclass 3, count 0 2006.285.16:05:08.73#ibcon#read 4, iclass 3, count 0 2006.285.16:05:08.73#ibcon#about to read 5, iclass 3, count 0 2006.285.16:05:08.73#ibcon#read 5, iclass 3, count 0 2006.285.16:05:08.73#ibcon#about to read 6, iclass 3, count 0 2006.285.16:05:08.73#ibcon#read 6, iclass 3, count 0 2006.285.16:05:08.73#ibcon#end of sib2, iclass 3, count 0 2006.285.16:05:08.73#ibcon#*after write, iclass 3, count 0 2006.285.16:05:08.73#ibcon#*before return 0, iclass 3, count 0 2006.285.16:05:08.73#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:05:08.73#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:05:08.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.16:05:08.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.16:05:08.73$vck44/vblo=8,744.99 2006.285.16:05:08.73#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.16:05:08.73#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.16:05:08.73#ibcon#ireg 17 cls_cnt 0 2006.285.16:05:08.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:05:08.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:05:08.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:05:08.73#ibcon#enter wrdev, iclass 5, count 0 2006.285.16:05:08.73#ibcon#first serial, iclass 5, count 0 2006.285.16:05:08.73#ibcon#enter sib2, iclass 5, count 0 2006.285.16:05:08.73#ibcon#flushed, iclass 5, count 0 2006.285.16:05:08.73#ibcon#about to write, iclass 5, count 0 2006.285.16:05:08.73#ibcon#wrote, iclass 5, count 0 2006.285.16:05:08.73#ibcon#about to read 3, iclass 5, count 0 2006.285.16:05:08.75#ibcon#read 3, iclass 5, count 0 2006.285.16:05:08.75#ibcon#about to read 4, iclass 5, count 0 2006.285.16:05:08.75#ibcon#read 4, iclass 5, count 0 2006.285.16:05:08.75#ibcon#about to read 5, iclass 5, count 0 2006.285.16:05:08.75#ibcon#read 5, iclass 5, count 0 2006.285.16:05:08.75#ibcon#about to read 6, iclass 5, count 0 2006.285.16:05:08.75#ibcon#read 6, iclass 5, count 0 2006.285.16:05:08.75#ibcon#end of sib2, iclass 5, count 0 2006.285.16:05:08.75#ibcon#*mode == 0, iclass 5, count 0 2006.285.16:05:08.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.16:05:08.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.16:05:08.75#ibcon#*before write, iclass 5, count 0 2006.285.16:05:08.75#ibcon#enter sib2, iclass 5, count 0 2006.285.16:05:08.75#ibcon#flushed, iclass 5, count 0 2006.285.16:05:08.75#ibcon#about to write, iclass 5, count 0 2006.285.16:05:08.75#ibcon#wrote, iclass 5, count 0 2006.285.16:05:08.75#ibcon#about to read 3, iclass 5, count 0 2006.285.16:05:08.79#ibcon#read 3, iclass 5, count 0 2006.285.16:05:08.79#ibcon#about to read 4, iclass 5, count 0 2006.285.16:05:08.79#ibcon#read 4, iclass 5, count 0 2006.285.16:05:08.79#ibcon#about to read 5, iclass 5, count 0 2006.285.16:05:08.79#ibcon#read 5, iclass 5, count 0 2006.285.16:05:08.79#ibcon#about to read 6, iclass 5, count 0 2006.285.16:05:08.79#ibcon#read 6, iclass 5, count 0 2006.285.16:05:08.79#ibcon#end of sib2, iclass 5, count 0 2006.285.16:05:08.79#ibcon#*after write, iclass 5, count 0 2006.285.16:05:08.79#ibcon#*before return 0, iclass 5, count 0 2006.285.16:05:08.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:05:08.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:05:08.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.16:05:08.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.16:05:08.79$vck44/vb=8,4 2006.285.16:05:08.79#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.16:05:08.79#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.16:05:08.79#ibcon#ireg 11 cls_cnt 2 2006.285.16:05:08.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:05:08.85#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:05:08.85#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:05:08.85#ibcon#enter wrdev, iclass 7, count 2 2006.285.16:05:08.85#ibcon#first serial, iclass 7, count 2 2006.285.16:05:08.85#ibcon#enter sib2, iclass 7, count 2 2006.285.16:05:08.85#ibcon#flushed, iclass 7, count 2 2006.285.16:05:08.85#ibcon#about to write, iclass 7, count 2 2006.285.16:05:08.85#ibcon#wrote, iclass 7, count 2 2006.285.16:05:08.85#ibcon#about to read 3, iclass 7, count 2 2006.285.16:05:08.87#ibcon#read 3, iclass 7, count 2 2006.285.16:05:08.87#ibcon#about to read 4, iclass 7, count 2 2006.285.16:05:08.87#ibcon#read 4, iclass 7, count 2 2006.285.16:05:08.87#ibcon#about to read 5, iclass 7, count 2 2006.285.16:05:08.87#ibcon#read 5, iclass 7, count 2 2006.285.16:05:08.87#ibcon#about to read 6, iclass 7, count 2 2006.285.16:05:08.87#ibcon#read 6, iclass 7, count 2 2006.285.16:05:08.87#ibcon#end of sib2, iclass 7, count 2 2006.285.16:05:08.87#ibcon#*mode == 0, iclass 7, count 2 2006.285.16:05:08.87#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.16:05:08.87#ibcon#[27=AT08-04\r\n] 2006.285.16:05:08.87#ibcon#*before write, iclass 7, count 2 2006.285.16:05:08.87#ibcon#enter sib2, iclass 7, count 2 2006.285.16:05:08.87#ibcon#flushed, iclass 7, count 2 2006.285.16:05:08.87#ibcon#about to write, iclass 7, count 2 2006.285.16:05:08.87#ibcon#wrote, iclass 7, count 2 2006.285.16:05:08.87#ibcon#about to read 3, iclass 7, count 2 2006.285.16:05:08.90#ibcon#read 3, iclass 7, count 2 2006.285.16:05:08.90#ibcon#about to read 4, iclass 7, count 2 2006.285.16:05:08.90#ibcon#read 4, iclass 7, count 2 2006.285.16:05:08.90#ibcon#about to read 5, iclass 7, count 2 2006.285.16:05:08.90#ibcon#read 5, iclass 7, count 2 2006.285.16:05:08.90#ibcon#about to read 6, iclass 7, count 2 2006.285.16:05:08.90#ibcon#read 6, iclass 7, count 2 2006.285.16:05:08.90#ibcon#end of sib2, iclass 7, count 2 2006.285.16:05:08.90#ibcon#*after write, iclass 7, count 2 2006.285.16:05:08.90#ibcon#*before return 0, iclass 7, count 2 2006.285.16:05:08.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:05:08.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:05:08.90#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.16:05:08.90#ibcon#ireg 7 cls_cnt 0 2006.285.16:05:08.90#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:05:09.02#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:05:09.02#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:05:09.02#ibcon#enter wrdev, iclass 7, count 0 2006.285.16:05:09.02#ibcon#first serial, iclass 7, count 0 2006.285.16:05:09.02#ibcon#enter sib2, iclass 7, count 0 2006.285.16:05:09.02#ibcon#flushed, iclass 7, count 0 2006.285.16:05:09.02#ibcon#about to write, iclass 7, count 0 2006.285.16:05:09.02#ibcon#wrote, iclass 7, count 0 2006.285.16:05:09.02#ibcon#about to read 3, iclass 7, count 0 2006.285.16:05:09.04#ibcon#read 3, iclass 7, count 0 2006.285.16:05:09.04#ibcon#about to read 4, iclass 7, count 0 2006.285.16:05:09.04#ibcon#read 4, iclass 7, count 0 2006.285.16:05:09.04#ibcon#about to read 5, iclass 7, count 0 2006.285.16:05:09.04#ibcon#read 5, iclass 7, count 0 2006.285.16:05:09.04#ibcon#about to read 6, iclass 7, count 0 2006.285.16:05:09.04#ibcon#read 6, iclass 7, count 0 2006.285.16:05:09.04#ibcon#end of sib2, iclass 7, count 0 2006.285.16:05:09.04#ibcon#*mode == 0, iclass 7, count 0 2006.285.16:05:09.04#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.16:05:09.04#ibcon#[27=USB\r\n] 2006.285.16:05:09.04#ibcon#*before write, iclass 7, count 0 2006.285.16:05:09.04#ibcon#enter sib2, iclass 7, count 0 2006.285.16:05:09.04#ibcon#flushed, iclass 7, count 0 2006.285.16:05:09.04#ibcon#about to write, iclass 7, count 0 2006.285.16:05:09.04#ibcon#wrote, iclass 7, count 0 2006.285.16:05:09.04#ibcon#about to read 3, iclass 7, count 0 2006.285.16:05:09.07#ibcon#read 3, iclass 7, count 0 2006.285.16:05:09.07#ibcon#about to read 4, iclass 7, count 0 2006.285.16:05:09.07#ibcon#read 4, iclass 7, count 0 2006.285.16:05:09.07#ibcon#about to read 5, iclass 7, count 0 2006.285.16:05:09.07#ibcon#read 5, iclass 7, count 0 2006.285.16:05:09.07#ibcon#about to read 6, iclass 7, count 0 2006.285.16:05:09.07#ibcon#read 6, iclass 7, count 0 2006.285.16:05:09.07#ibcon#end of sib2, iclass 7, count 0 2006.285.16:05:09.07#ibcon#*after write, iclass 7, count 0 2006.285.16:05:09.07#ibcon#*before return 0, iclass 7, count 0 2006.285.16:05:09.07#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:05:09.07#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:05:09.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.16:05:09.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.16:05:09.07$vck44/vabw=wide 2006.285.16:05:09.07#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.16:05:09.07#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.16:05:09.07#ibcon#ireg 8 cls_cnt 0 2006.285.16:05:09.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:05:09.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:05:09.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:05:09.07#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:05:09.07#ibcon#first serial, iclass 11, count 0 2006.285.16:05:09.07#ibcon#enter sib2, iclass 11, count 0 2006.285.16:05:09.07#ibcon#flushed, iclass 11, count 0 2006.285.16:05:09.07#ibcon#about to write, iclass 11, count 0 2006.285.16:05:09.07#ibcon#wrote, iclass 11, count 0 2006.285.16:05:09.07#ibcon#about to read 3, iclass 11, count 0 2006.285.16:05:09.09#ibcon#read 3, iclass 11, count 0 2006.285.16:05:09.09#ibcon#about to read 4, iclass 11, count 0 2006.285.16:05:09.09#ibcon#read 4, iclass 11, count 0 2006.285.16:05:09.09#ibcon#about to read 5, iclass 11, count 0 2006.285.16:05:09.09#ibcon#read 5, iclass 11, count 0 2006.285.16:05:09.09#ibcon#about to read 6, iclass 11, count 0 2006.285.16:05:09.09#ibcon#read 6, iclass 11, count 0 2006.285.16:05:09.09#ibcon#end of sib2, iclass 11, count 0 2006.285.16:05:09.09#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:05:09.09#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:05:09.09#ibcon#[25=BW32\r\n] 2006.285.16:05:09.09#ibcon#*before write, iclass 11, count 0 2006.285.16:05:09.09#ibcon#enter sib2, iclass 11, count 0 2006.285.16:05:09.09#ibcon#flushed, iclass 11, count 0 2006.285.16:05:09.09#ibcon#about to write, iclass 11, count 0 2006.285.16:05:09.09#ibcon#wrote, iclass 11, count 0 2006.285.16:05:09.09#ibcon#about to read 3, iclass 11, count 0 2006.285.16:05:09.12#ibcon#read 3, iclass 11, count 0 2006.285.16:05:09.12#ibcon#about to read 4, iclass 11, count 0 2006.285.16:05:09.12#ibcon#read 4, iclass 11, count 0 2006.285.16:05:09.12#ibcon#about to read 5, iclass 11, count 0 2006.285.16:05:09.12#ibcon#read 5, iclass 11, count 0 2006.285.16:05:09.12#ibcon#about to read 6, iclass 11, count 0 2006.285.16:05:09.12#ibcon#read 6, iclass 11, count 0 2006.285.16:05:09.12#ibcon#end of sib2, iclass 11, count 0 2006.285.16:05:09.12#ibcon#*after write, iclass 11, count 0 2006.285.16:05:09.12#ibcon#*before return 0, iclass 11, count 0 2006.285.16:05:09.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:05:09.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:05:09.12#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:05:09.12#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:05:09.12$vck44/vbbw=wide 2006.285.16:05:09.12#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.16:05:09.12#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.16:05:09.12#ibcon#ireg 8 cls_cnt 0 2006.285.16:05:09.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:05:09.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:05:09.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:05:09.19#ibcon#enter wrdev, iclass 13, count 0 2006.285.16:05:09.19#ibcon#first serial, iclass 13, count 0 2006.285.16:05:09.19#ibcon#enter sib2, iclass 13, count 0 2006.285.16:05:09.19#ibcon#flushed, iclass 13, count 0 2006.285.16:05:09.19#ibcon#about to write, iclass 13, count 0 2006.285.16:05:09.19#ibcon#wrote, iclass 13, count 0 2006.285.16:05:09.19#ibcon#about to read 3, iclass 13, count 0 2006.285.16:05:09.21#ibcon#read 3, iclass 13, count 0 2006.285.16:05:09.21#ibcon#about to read 4, iclass 13, count 0 2006.285.16:05:09.21#ibcon#read 4, iclass 13, count 0 2006.285.16:05:09.21#ibcon#about to read 5, iclass 13, count 0 2006.285.16:05:09.21#ibcon#read 5, iclass 13, count 0 2006.285.16:05:09.21#ibcon#about to read 6, iclass 13, count 0 2006.285.16:05:09.21#ibcon#read 6, iclass 13, count 0 2006.285.16:05:09.21#ibcon#end of sib2, iclass 13, count 0 2006.285.16:05:09.21#ibcon#*mode == 0, iclass 13, count 0 2006.285.16:05:09.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.16:05:09.21#ibcon#[27=BW32\r\n] 2006.285.16:05:09.21#ibcon#*before write, iclass 13, count 0 2006.285.16:05:09.21#ibcon#enter sib2, iclass 13, count 0 2006.285.16:05:09.21#ibcon#flushed, iclass 13, count 0 2006.285.16:05:09.21#ibcon#about to write, iclass 13, count 0 2006.285.16:05:09.21#ibcon#wrote, iclass 13, count 0 2006.285.16:05:09.21#ibcon#about to read 3, iclass 13, count 0 2006.285.16:05:09.24#ibcon#read 3, iclass 13, count 0 2006.285.16:05:09.24#ibcon#about to read 4, iclass 13, count 0 2006.285.16:05:09.24#ibcon#read 4, iclass 13, count 0 2006.285.16:05:09.24#ibcon#about to read 5, iclass 13, count 0 2006.285.16:05:09.24#ibcon#read 5, iclass 13, count 0 2006.285.16:05:09.24#ibcon#about to read 6, iclass 13, count 0 2006.285.16:05:09.24#ibcon#read 6, iclass 13, count 0 2006.285.16:05:09.24#ibcon#end of sib2, iclass 13, count 0 2006.285.16:05:09.24#ibcon#*after write, iclass 13, count 0 2006.285.16:05:09.24#ibcon#*before return 0, iclass 13, count 0 2006.285.16:05:09.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:05:09.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:05:09.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.16:05:09.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.16:05:09.24$setupk4/ifdk4 2006.285.16:05:09.24$ifdk4/lo= 2006.285.16:05:09.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.16:05:09.24$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.16:05:09.24$ifdk4/patch= 2006.285.16:05:09.24$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.16:05:09.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.16:05:09.25$setupk4/!*+20s 2006.285.16:05:13.07#abcon#<5=/02 1.3 4.1 18.66 911014.9\r\n> 2006.285.16:05:13.09#abcon#{5=INTERFACE CLEAR} 2006.285.16:05:13.15#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:05:20.14#trakl#Source acquired 2006.285.16:05:22.14#flagr#flagr/antenna,acquired 2006.285.16:05:23.07$setupk4/"tpicd 2006.285.16:05:23.07$setupk4/echo=off 2006.285.16:05:23.07$setupk4/xlog=off 2006.285.16:05:23.07:!2006.285.16:09:18 2006.285.16:09:18.00:preob 2006.285.16:09:18.14/onsource/TRACKING 2006.285.16:09:18.14:!2006.285.16:09:28 2006.285.16:09:28.00:"tape 2006.285.16:09:28.00:"st=record 2006.285.16:09:28.00:data_valid=on 2006.285.16:09:28.00:midob 2006.285.16:09:28.14/onsource/TRACKING 2006.285.16:09:28.14/wx/18.68,1014.9,90 2006.285.16:09:28.35/cable/+6.5002E-03 2006.285.16:09:29.44/va/01,07,usb,yes,32,35 2006.285.16:09:29.44/va/02,06,usb,yes,32,33 2006.285.16:09:29.44/va/03,07,usb,yes,32,34 2006.285.16:09:29.44/va/04,06,usb,yes,33,35 2006.285.16:09:29.44/va/05,03,usb,yes,33,33 2006.285.16:09:29.44/va/06,04,usb,yes,29,29 2006.285.16:09:29.44/va/07,04,usb,yes,30,31 2006.285.16:09:29.44/va/08,03,usb,yes,31,37 2006.285.16:09:29.67/valo/01,524.99,yes,locked 2006.285.16:09:29.67/valo/02,534.99,yes,locked 2006.285.16:09:29.67/valo/03,564.99,yes,locked 2006.285.16:09:29.67/valo/04,624.99,yes,locked 2006.285.16:09:29.67/valo/05,734.99,yes,locked 2006.285.16:09:29.67/valo/06,814.99,yes,locked 2006.285.16:09:29.67/valo/07,864.99,yes,locked 2006.285.16:09:29.67/valo/08,884.99,yes,locked 2006.285.16:09:30.76/vb/01,04,usb,yes,30,28 2006.285.16:09:30.76/vb/02,05,usb,yes,29,29 2006.285.16:09:30.76/vb/03,04,usb,yes,30,33 2006.285.16:09:30.76/vb/04,05,usb,yes,30,29 2006.285.16:09:30.76/vb/05,04,usb,yes,26,29 2006.285.16:09:30.76/vb/06,03,usb,yes,38,34 2006.285.16:09:30.76/vb/07,04,usb,yes,31,31 2006.285.16:09:30.76/vb/08,04,usb,yes,28,31 2006.285.16:09:30.99/vblo/01,629.99,yes,locked 2006.285.16:09:30.99/vblo/02,634.99,yes,locked 2006.285.16:09:30.99/vblo/03,649.99,yes,locked 2006.285.16:09:30.99/vblo/04,679.99,yes,locked 2006.285.16:09:30.99/vblo/05,709.99,yes,locked 2006.285.16:09:30.99/vblo/06,719.99,yes,locked 2006.285.16:09:30.99/vblo/07,734.99,yes,locked 2006.285.16:09:30.99/vblo/08,744.99,yes,locked 2006.285.16:09:31.14/vabw/8 2006.285.16:09:31.29/vbbw/8 2006.285.16:09:31.38/xfe/off,on,12.0 2006.285.16:09:31.75/ifatt/23,28,28,28 2006.285.16:09:32.07/fmout-gps/S +2.74E-07 2006.285.16:09:32.09:!2006.285.16:17:48 2006.285.16:17:48.00:data_valid=off 2006.285.16:17:48.00:"et 2006.285.16:17:48.00:!+3s 2006.285.16:17:51.01:"tape 2006.285.16:17:51.01:postob 2006.285.16:17:51.11/cable/+6.5002E-03 2006.285.16:17:51.11/wx/18.67,1014.9,90 2006.285.16:17:52.07/fmout-gps/S +2.77E-07 2006.285.16:17:52.07:scan_name=285-1623,jd0610,40 2006.285.16:17:52.07:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.285.16:17:53.14#flagr#flagr/antenna,new-source 2006.285.16:17:53.14:checkk5 2006.285.16:17:53.51/chk_autoobs//k5ts1/ autoobs is running! 2006.285.16:17:54.13/chk_autoobs//k5ts2/ autoobs is running! 2006.285.16:17:54.57/chk_autoobs//k5ts3/ autoobs is running! 2006.285.16:17:54.98/chk_autoobs//k5ts4/ autoobs is running! 2006.285.16:17:55.63/chk_obsdata//k5ts1/T2851609??a.dat file size is correct (nominal:2000MB, actual:1996MB). 2006.285.16:17:56.07/chk_obsdata//k5ts2/T2851609??b.dat file size is correct (nominal:2000MB, actual:1996MB). 2006.285.16:17:56.44/chk_obsdata//k5ts3/T2851609??c.dat file size is correct (nominal:2000MB, actual:1996MB). 2006.285.16:17:56.83/chk_obsdata//k5ts4/T2851609??d.dat file size is correct (nominal:2000MB, actual:1996MB). 2006.285.16:17:57.74/k5log//k5ts1_log_newline 2006.285.16:17:58.61/k5log//k5ts2_log_newline 2006.285.16:17:59.63/k5log//k5ts3_log_newline 2006.285.16:18:00.40/k5log//k5ts4_log_newline 2006.285.16:18:00.42/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.16:18:00.42:setupk4=1 2006.285.16:18:00.42$setupk4/echo=on 2006.285.16:18:00.42$setupk4/pcalon 2006.285.16:18:00.42$pcalon/"no phase cal control is implemented here 2006.285.16:18:00.42$setupk4/"tpicd=stop 2006.285.16:18:00.42$setupk4/"rec=synch_on 2006.285.16:18:00.42$setupk4/"rec_mode=128 2006.285.16:18:00.42$setupk4/!* 2006.285.16:18:00.42$setupk4/recpk4 2006.285.16:18:00.42$recpk4/recpatch= 2006.285.16:18:00.43$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.16:18:00.43$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.16:18:00.43$setupk4/vck44 2006.285.16:18:00.43$vck44/valo=1,524.99 2006.285.16:18:00.43#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.16:18:00.43#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.16:18:00.43#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:00.43#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:18:00.43#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:18:00.43#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:18:00.43#ibcon#enter wrdev, iclass 34, count 0 2006.285.16:18:00.43#ibcon#first serial, iclass 34, count 0 2006.285.16:18:00.43#ibcon#enter sib2, iclass 34, count 0 2006.285.16:18:00.43#ibcon#flushed, iclass 34, count 0 2006.285.16:18:00.43#ibcon#about to write, iclass 34, count 0 2006.285.16:18:00.43#ibcon#wrote, iclass 34, count 0 2006.285.16:18:00.43#ibcon#about to read 3, iclass 34, count 0 2006.285.16:18:00.44#ibcon#read 3, iclass 34, count 0 2006.285.16:18:00.44#ibcon#about to read 4, iclass 34, count 0 2006.285.16:18:00.44#ibcon#read 4, iclass 34, count 0 2006.285.16:18:00.44#ibcon#about to read 5, iclass 34, count 0 2006.285.16:18:00.44#ibcon#read 5, iclass 34, count 0 2006.285.16:18:00.44#ibcon#about to read 6, iclass 34, count 0 2006.285.16:18:00.44#ibcon#read 6, iclass 34, count 0 2006.285.16:18:00.44#ibcon#end of sib2, iclass 34, count 0 2006.285.16:18:00.44#ibcon#*mode == 0, iclass 34, count 0 2006.285.16:18:00.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.16:18:00.44#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.16:18:00.44#ibcon#*before write, iclass 34, count 0 2006.285.16:18:00.44#ibcon#enter sib2, iclass 34, count 0 2006.285.16:18:00.44#ibcon#flushed, iclass 34, count 0 2006.285.16:18:00.44#ibcon#about to write, iclass 34, count 0 2006.285.16:18:00.44#ibcon#wrote, iclass 34, count 0 2006.285.16:18:00.44#ibcon#about to read 3, iclass 34, count 0 2006.285.16:18:00.49#ibcon#read 3, iclass 34, count 0 2006.285.16:18:00.49#ibcon#about to read 4, iclass 34, count 0 2006.285.16:18:00.49#ibcon#read 4, iclass 34, count 0 2006.285.16:18:00.49#ibcon#about to read 5, iclass 34, count 0 2006.285.16:18:00.49#ibcon#read 5, iclass 34, count 0 2006.285.16:18:00.49#ibcon#about to read 6, iclass 34, count 0 2006.285.16:18:00.49#ibcon#read 6, iclass 34, count 0 2006.285.16:18:00.49#ibcon#end of sib2, iclass 34, count 0 2006.285.16:18:00.49#ibcon#*after write, iclass 34, count 0 2006.285.16:18:00.49#ibcon#*before return 0, iclass 34, count 0 2006.285.16:18:00.49#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:18:00.49#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:18:00.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.16:18:00.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.16:18:00.49$vck44/va=1,7 2006.285.16:18:00.49#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.16:18:00.49#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.16:18:00.49#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:00.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:18:00.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:18:00.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:18:00.49#ibcon#enter wrdev, iclass 36, count 2 2006.285.16:18:00.49#ibcon#first serial, iclass 36, count 2 2006.285.16:18:00.49#ibcon#enter sib2, iclass 36, count 2 2006.285.16:18:00.49#ibcon#flushed, iclass 36, count 2 2006.285.16:18:00.49#ibcon#about to write, iclass 36, count 2 2006.285.16:18:00.49#ibcon#wrote, iclass 36, count 2 2006.285.16:18:00.49#ibcon#about to read 3, iclass 36, count 2 2006.285.16:18:00.51#ibcon#read 3, iclass 36, count 2 2006.285.16:18:00.51#ibcon#about to read 4, iclass 36, count 2 2006.285.16:18:00.51#ibcon#read 4, iclass 36, count 2 2006.285.16:18:00.51#ibcon#about to read 5, iclass 36, count 2 2006.285.16:18:00.51#ibcon#read 5, iclass 36, count 2 2006.285.16:18:00.51#ibcon#about to read 6, iclass 36, count 2 2006.285.16:18:00.51#ibcon#read 6, iclass 36, count 2 2006.285.16:18:00.51#ibcon#end of sib2, iclass 36, count 2 2006.285.16:18:00.51#ibcon#*mode == 0, iclass 36, count 2 2006.285.16:18:00.51#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.16:18:00.51#ibcon#[25=AT01-07\r\n] 2006.285.16:18:00.51#ibcon#*before write, iclass 36, count 2 2006.285.16:18:00.51#ibcon#enter sib2, iclass 36, count 2 2006.285.16:18:00.51#ibcon#flushed, iclass 36, count 2 2006.285.16:18:00.51#ibcon#about to write, iclass 36, count 2 2006.285.16:18:00.51#ibcon#wrote, iclass 36, count 2 2006.285.16:18:00.51#ibcon#about to read 3, iclass 36, count 2 2006.285.16:18:00.54#ibcon#read 3, iclass 36, count 2 2006.285.16:18:00.54#ibcon#about to read 4, iclass 36, count 2 2006.285.16:18:00.54#ibcon#read 4, iclass 36, count 2 2006.285.16:18:00.54#ibcon#about to read 5, iclass 36, count 2 2006.285.16:18:00.54#ibcon#read 5, iclass 36, count 2 2006.285.16:18:00.54#ibcon#about to read 6, iclass 36, count 2 2006.285.16:18:00.54#ibcon#read 6, iclass 36, count 2 2006.285.16:18:00.54#ibcon#end of sib2, iclass 36, count 2 2006.285.16:18:00.54#ibcon#*after write, iclass 36, count 2 2006.285.16:18:00.54#ibcon#*before return 0, iclass 36, count 2 2006.285.16:18:00.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:18:00.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:18:00.54#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.16:18:00.54#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:00.54#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:18:00.66#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:18:00.66#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:18:00.66#ibcon#enter wrdev, iclass 36, count 0 2006.285.16:18:00.66#ibcon#first serial, iclass 36, count 0 2006.285.16:18:00.66#ibcon#enter sib2, iclass 36, count 0 2006.285.16:18:00.66#ibcon#flushed, iclass 36, count 0 2006.285.16:18:00.66#ibcon#about to write, iclass 36, count 0 2006.285.16:18:00.66#ibcon#wrote, iclass 36, count 0 2006.285.16:18:00.66#ibcon#about to read 3, iclass 36, count 0 2006.285.16:18:00.68#ibcon#read 3, iclass 36, count 0 2006.285.16:18:00.68#ibcon#about to read 4, iclass 36, count 0 2006.285.16:18:00.68#ibcon#read 4, iclass 36, count 0 2006.285.16:18:00.68#ibcon#about to read 5, iclass 36, count 0 2006.285.16:18:00.68#ibcon#read 5, iclass 36, count 0 2006.285.16:18:00.68#ibcon#about to read 6, iclass 36, count 0 2006.285.16:18:00.68#ibcon#read 6, iclass 36, count 0 2006.285.16:18:00.68#ibcon#end of sib2, iclass 36, count 0 2006.285.16:18:00.68#ibcon#*mode == 0, iclass 36, count 0 2006.285.16:18:00.68#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.16:18:00.68#ibcon#[25=USB\r\n] 2006.285.16:18:00.68#ibcon#*before write, iclass 36, count 0 2006.285.16:18:00.68#ibcon#enter sib2, iclass 36, count 0 2006.285.16:18:00.68#ibcon#flushed, iclass 36, count 0 2006.285.16:18:00.68#ibcon#about to write, iclass 36, count 0 2006.285.16:18:00.68#ibcon#wrote, iclass 36, count 0 2006.285.16:18:00.68#ibcon#about to read 3, iclass 36, count 0 2006.285.16:18:00.71#ibcon#read 3, iclass 36, count 0 2006.285.16:18:00.71#ibcon#about to read 4, iclass 36, count 0 2006.285.16:18:00.71#ibcon#read 4, iclass 36, count 0 2006.285.16:18:00.71#ibcon#about to read 5, iclass 36, count 0 2006.285.16:18:00.71#ibcon#read 5, iclass 36, count 0 2006.285.16:18:00.71#ibcon#about to read 6, iclass 36, count 0 2006.285.16:18:00.71#ibcon#read 6, iclass 36, count 0 2006.285.16:18:00.71#ibcon#end of sib2, iclass 36, count 0 2006.285.16:18:00.71#ibcon#*after write, iclass 36, count 0 2006.285.16:18:00.71#ibcon#*before return 0, iclass 36, count 0 2006.285.16:18:00.71#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:18:00.71#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:18:00.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.16:18:00.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.16:18:00.71$vck44/valo=2,534.99 2006.285.16:18:00.71#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.16:18:00.71#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.16:18:00.71#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:00.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:18:00.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:18:00.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:18:00.71#ibcon#enter wrdev, iclass 38, count 0 2006.285.16:18:00.71#ibcon#first serial, iclass 38, count 0 2006.285.16:18:00.71#ibcon#enter sib2, iclass 38, count 0 2006.285.16:18:00.71#ibcon#flushed, iclass 38, count 0 2006.285.16:18:00.71#ibcon#about to write, iclass 38, count 0 2006.285.16:18:00.71#ibcon#wrote, iclass 38, count 0 2006.285.16:18:00.71#ibcon#about to read 3, iclass 38, count 0 2006.285.16:18:00.73#ibcon#read 3, iclass 38, count 0 2006.285.16:18:00.73#ibcon#about to read 4, iclass 38, count 0 2006.285.16:18:00.73#ibcon#read 4, iclass 38, count 0 2006.285.16:18:00.73#ibcon#about to read 5, iclass 38, count 0 2006.285.16:18:00.73#ibcon#read 5, iclass 38, count 0 2006.285.16:18:00.73#ibcon#about to read 6, iclass 38, count 0 2006.285.16:18:00.73#ibcon#read 6, iclass 38, count 0 2006.285.16:18:00.73#ibcon#end of sib2, iclass 38, count 0 2006.285.16:18:00.73#ibcon#*mode == 0, iclass 38, count 0 2006.285.16:18:00.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.16:18:00.73#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.16:18:00.73#ibcon#*before write, iclass 38, count 0 2006.285.16:18:00.73#ibcon#enter sib2, iclass 38, count 0 2006.285.16:18:00.73#ibcon#flushed, iclass 38, count 0 2006.285.16:18:00.73#ibcon#about to write, iclass 38, count 0 2006.285.16:18:00.73#ibcon#wrote, iclass 38, count 0 2006.285.16:18:00.73#ibcon#about to read 3, iclass 38, count 0 2006.285.16:18:00.77#ibcon#read 3, iclass 38, count 0 2006.285.16:18:00.77#ibcon#about to read 4, iclass 38, count 0 2006.285.16:18:00.77#ibcon#read 4, iclass 38, count 0 2006.285.16:18:00.77#ibcon#about to read 5, iclass 38, count 0 2006.285.16:18:00.77#ibcon#read 5, iclass 38, count 0 2006.285.16:18:00.77#ibcon#about to read 6, iclass 38, count 0 2006.285.16:18:00.77#ibcon#read 6, iclass 38, count 0 2006.285.16:18:00.77#ibcon#end of sib2, iclass 38, count 0 2006.285.16:18:00.77#ibcon#*after write, iclass 38, count 0 2006.285.16:18:00.77#ibcon#*before return 0, iclass 38, count 0 2006.285.16:18:00.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:18:00.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:18:00.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.16:18:00.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.16:18:00.77$vck44/va=2,6 2006.285.16:18:00.77#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.16:18:00.77#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.16:18:00.77#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:00.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:18:00.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:18:00.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:18:00.83#ibcon#enter wrdev, iclass 40, count 2 2006.285.16:18:00.83#ibcon#first serial, iclass 40, count 2 2006.285.16:18:00.83#ibcon#enter sib2, iclass 40, count 2 2006.285.16:18:00.83#ibcon#flushed, iclass 40, count 2 2006.285.16:18:00.83#ibcon#about to write, iclass 40, count 2 2006.285.16:18:00.83#ibcon#wrote, iclass 40, count 2 2006.285.16:18:00.83#ibcon#about to read 3, iclass 40, count 2 2006.285.16:18:00.85#ibcon#read 3, iclass 40, count 2 2006.285.16:18:00.85#ibcon#about to read 4, iclass 40, count 2 2006.285.16:18:00.85#ibcon#read 4, iclass 40, count 2 2006.285.16:18:00.85#ibcon#about to read 5, iclass 40, count 2 2006.285.16:18:00.85#ibcon#read 5, iclass 40, count 2 2006.285.16:18:00.85#ibcon#about to read 6, iclass 40, count 2 2006.285.16:18:00.85#ibcon#read 6, iclass 40, count 2 2006.285.16:18:00.85#ibcon#end of sib2, iclass 40, count 2 2006.285.16:18:00.85#ibcon#*mode == 0, iclass 40, count 2 2006.285.16:18:00.85#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.16:18:00.85#ibcon#[25=AT02-06\r\n] 2006.285.16:18:00.85#ibcon#*before write, iclass 40, count 2 2006.285.16:18:00.85#ibcon#enter sib2, iclass 40, count 2 2006.285.16:18:00.85#ibcon#flushed, iclass 40, count 2 2006.285.16:18:00.85#ibcon#about to write, iclass 40, count 2 2006.285.16:18:00.85#ibcon#wrote, iclass 40, count 2 2006.285.16:18:00.85#ibcon#about to read 3, iclass 40, count 2 2006.285.16:18:00.88#ibcon#read 3, iclass 40, count 2 2006.285.16:18:00.88#ibcon#about to read 4, iclass 40, count 2 2006.285.16:18:00.88#ibcon#read 4, iclass 40, count 2 2006.285.16:18:00.88#ibcon#about to read 5, iclass 40, count 2 2006.285.16:18:00.88#ibcon#read 5, iclass 40, count 2 2006.285.16:18:00.88#ibcon#about to read 6, iclass 40, count 2 2006.285.16:18:00.88#ibcon#read 6, iclass 40, count 2 2006.285.16:18:00.88#ibcon#end of sib2, iclass 40, count 2 2006.285.16:18:00.88#ibcon#*after write, iclass 40, count 2 2006.285.16:18:00.88#ibcon#*before return 0, iclass 40, count 2 2006.285.16:18:00.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:18:00.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:18:00.88#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.16:18:00.88#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:00.88#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:18:01.00#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:18:01.00#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:18:01.00#ibcon#enter wrdev, iclass 40, count 0 2006.285.16:18:01.00#ibcon#first serial, iclass 40, count 0 2006.285.16:18:01.00#ibcon#enter sib2, iclass 40, count 0 2006.285.16:18:01.00#ibcon#flushed, iclass 40, count 0 2006.285.16:18:01.00#ibcon#about to write, iclass 40, count 0 2006.285.16:18:01.00#ibcon#wrote, iclass 40, count 0 2006.285.16:18:01.00#ibcon#about to read 3, iclass 40, count 0 2006.285.16:18:01.02#ibcon#read 3, iclass 40, count 0 2006.285.16:18:01.02#ibcon#about to read 4, iclass 40, count 0 2006.285.16:18:01.02#ibcon#read 4, iclass 40, count 0 2006.285.16:18:01.02#ibcon#about to read 5, iclass 40, count 0 2006.285.16:18:01.02#ibcon#read 5, iclass 40, count 0 2006.285.16:18:01.02#ibcon#about to read 6, iclass 40, count 0 2006.285.16:18:01.02#ibcon#read 6, iclass 40, count 0 2006.285.16:18:01.02#ibcon#end of sib2, iclass 40, count 0 2006.285.16:18:01.02#ibcon#*mode == 0, iclass 40, count 0 2006.285.16:18:01.02#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.16:18:01.02#ibcon#[25=USB\r\n] 2006.285.16:18:01.02#ibcon#*before write, iclass 40, count 0 2006.285.16:18:01.02#ibcon#enter sib2, iclass 40, count 0 2006.285.16:18:01.02#ibcon#flushed, iclass 40, count 0 2006.285.16:18:01.02#ibcon#about to write, iclass 40, count 0 2006.285.16:18:01.02#ibcon#wrote, iclass 40, count 0 2006.285.16:18:01.02#ibcon#about to read 3, iclass 40, count 0 2006.285.16:18:01.05#ibcon#read 3, iclass 40, count 0 2006.285.16:18:01.05#ibcon#about to read 4, iclass 40, count 0 2006.285.16:18:01.05#ibcon#read 4, iclass 40, count 0 2006.285.16:18:01.05#ibcon#about to read 5, iclass 40, count 0 2006.285.16:18:01.05#ibcon#read 5, iclass 40, count 0 2006.285.16:18:01.05#ibcon#about to read 6, iclass 40, count 0 2006.285.16:18:01.05#ibcon#read 6, iclass 40, count 0 2006.285.16:18:01.05#ibcon#end of sib2, iclass 40, count 0 2006.285.16:18:01.05#ibcon#*after write, iclass 40, count 0 2006.285.16:18:01.05#ibcon#*before return 0, iclass 40, count 0 2006.285.16:18:01.05#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:18:01.05#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:18:01.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.16:18:01.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.16:18:01.05$vck44/valo=3,564.99 2006.285.16:18:01.05#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.16:18:01.05#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.16:18:01.05#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:01.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:18:01.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:18:01.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:18:01.05#ibcon#enter wrdev, iclass 4, count 0 2006.285.16:18:01.05#ibcon#first serial, iclass 4, count 0 2006.285.16:18:01.05#ibcon#enter sib2, iclass 4, count 0 2006.285.16:18:01.05#ibcon#flushed, iclass 4, count 0 2006.285.16:18:01.05#ibcon#about to write, iclass 4, count 0 2006.285.16:18:01.05#ibcon#wrote, iclass 4, count 0 2006.285.16:18:01.05#ibcon#about to read 3, iclass 4, count 0 2006.285.16:18:01.07#ibcon#read 3, iclass 4, count 0 2006.285.16:18:01.38#ibcon#about to read 4, iclass 4, count 0 2006.285.16:18:01.38#ibcon#read 4, iclass 4, count 0 2006.285.16:18:01.38#ibcon#about to read 5, iclass 4, count 0 2006.285.16:18:01.38#ibcon#read 5, iclass 4, count 0 2006.285.16:18:01.38#ibcon#about to read 6, iclass 4, count 0 2006.285.16:18:01.38#ibcon#read 6, iclass 4, count 0 2006.285.16:18:01.38#ibcon#end of sib2, iclass 4, count 0 2006.285.16:18:01.38#ibcon#*mode == 0, iclass 4, count 0 2006.285.16:18:01.38#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.16:18:01.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.16:18:01.38#ibcon#*before write, iclass 4, count 0 2006.285.16:18:01.38#ibcon#enter sib2, iclass 4, count 0 2006.285.16:18:01.38#ibcon#flushed, iclass 4, count 0 2006.285.16:18:01.38#ibcon#about to write, iclass 4, count 0 2006.285.16:18:01.38#ibcon#wrote, iclass 4, count 0 2006.285.16:18:01.38#ibcon#about to read 3, iclass 4, count 0 2006.285.16:18:01.42#ibcon#read 3, iclass 4, count 0 2006.285.16:18:01.42#ibcon#about to read 4, iclass 4, count 0 2006.285.16:18:01.42#ibcon#read 4, iclass 4, count 0 2006.285.16:18:01.42#ibcon#about to read 5, iclass 4, count 0 2006.285.16:18:01.42#ibcon#read 5, iclass 4, count 0 2006.285.16:18:01.42#ibcon#about to read 6, iclass 4, count 0 2006.285.16:18:01.42#ibcon#read 6, iclass 4, count 0 2006.285.16:18:01.42#ibcon#end of sib2, iclass 4, count 0 2006.285.16:18:01.42#ibcon#*after write, iclass 4, count 0 2006.285.16:18:01.42#ibcon#*before return 0, iclass 4, count 0 2006.285.16:18:01.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:18:01.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:18:01.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.16:18:01.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.16:18:01.42$vck44/va=3,7 2006.285.16:18:01.42#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.16:18:01.42#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.16:18:01.42#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:01.42#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:18:01.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:18:01.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:18:01.42#ibcon#enter wrdev, iclass 6, count 2 2006.285.16:18:01.42#ibcon#first serial, iclass 6, count 2 2006.285.16:18:01.42#ibcon#enter sib2, iclass 6, count 2 2006.285.16:18:01.42#ibcon#flushed, iclass 6, count 2 2006.285.16:18:01.42#ibcon#about to write, iclass 6, count 2 2006.285.16:18:01.42#ibcon#wrote, iclass 6, count 2 2006.285.16:18:01.42#ibcon#about to read 3, iclass 6, count 2 2006.285.16:18:01.44#ibcon#read 3, iclass 6, count 2 2006.285.16:18:01.44#ibcon#about to read 4, iclass 6, count 2 2006.285.16:18:01.44#ibcon#read 4, iclass 6, count 2 2006.285.16:18:01.44#ibcon#about to read 5, iclass 6, count 2 2006.285.16:18:01.44#ibcon#read 5, iclass 6, count 2 2006.285.16:18:01.44#ibcon#about to read 6, iclass 6, count 2 2006.285.16:18:01.44#ibcon#read 6, iclass 6, count 2 2006.285.16:18:01.44#ibcon#end of sib2, iclass 6, count 2 2006.285.16:18:01.44#ibcon#*mode == 0, iclass 6, count 2 2006.285.16:18:01.44#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.16:18:01.44#ibcon#[25=AT03-07\r\n] 2006.285.16:18:01.44#ibcon#*before write, iclass 6, count 2 2006.285.16:18:01.44#ibcon#enter sib2, iclass 6, count 2 2006.285.16:18:01.44#ibcon#flushed, iclass 6, count 2 2006.285.16:18:01.44#ibcon#about to write, iclass 6, count 2 2006.285.16:18:01.44#ibcon#wrote, iclass 6, count 2 2006.285.16:18:01.44#ibcon#about to read 3, iclass 6, count 2 2006.285.16:18:01.47#ibcon#read 3, iclass 6, count 2 2006.285.16:18:01.47#ibcon#about to read 4, iclass 6, count 2 2006.285.16:18:01.47#ibcon#read 4, iclass 6, count 2 2006.285.16:18:01.47#ibcon#about to read 5, iclass 6, count 2 2006.285.16:18:01.47#ibcon#read 5, iclass 6, count 2 2006.285.16:18:01.47#ibcon#about to read 6, iclass 6, count 2 2006.285.16:18:01.47#ibcon#read 6, iclass 6, count 2 2006.285.16:18:01.47#ibcon#end of sib2, iclass 6, count 2 2006.285.16:18:01.47#ibcon#*after write, iclass 6, count 2 2006.285.16:18:01.47#ibcon#*before return 0, iclass 6, count 2 2006.285.16:18:01.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:18:01.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:18:01.47#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.16:18:01.47#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:01.47#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:18:01.59#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:18:01.59#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:18:01.59#ibcon#enter wrdev, iclass 6, count 0 2006.285.16:18:01.59#ibcon#first serial, iclass 6, count 0 2006.285.16:18:01.59#ibcon#enter sib2, iclass 6, count 0 2006.285.16:18:01.59#ibcon#flushed, iclass 6, count 0 2006.285.16:18:01.59#ibcon#about to write, iclass 6, count 0 2006.285.16:18:01.59#ibcon#wrote, iclass 6, count 0 2006.285.16:18:01.59#ibcon#about to read 3, iclass 6, count 0 2006.285.16:18:01.61#ibcon#read 3, iclass 6, count 0 2006.285.16:18:01.61#ibcon#about to read 4, iclass 6, count 0 2006.285.16:18:01.61#ibcon#read 4, iclass 6, count 0 2006.285.16:18:01.61#ibcon#about to read 5, iclass 6, count 0 2006.285.16:18:01.61#ibcon#read 5, iclass 6, count 0 2006.285.16:18:01.61#ibcon#about to read 6, iclass 6, count 0 2006.285.16:18:01.61#ibcon#read 6, iclass 6, count 0 2006.285.16:18:01.61#ibcon#end of sib2, iclass 6, count 0 2006.285.16:18:01.61#ibcon#*mode == 0, iclass 6, count 0 2006.285.16:18:01.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.16:18:01.61#ibcon#[25=USB\r\n] 2006.285.16:18:01.61#ibcon#*before write, iclass 6, count 0 2006.285.16:18:01.61#ibcon#enter sib2, iclass 6, count 0 2006.285.16:18:01.61#ibcon#flushed, iclass 6, count 0 2006.285.16:18:01.61#ibcon#about to write, iclass 6, count 0 2006.285.16:18:01.61#ibcon#wrote, iclass 6, count 0 2006.285.16:18:01.61#ibcon#about to read 3, iclass 6, count 0 2006.285.16:18:01.64#ibcon#read 3, iclass 6, count 0 2006.285.16:18:01.64#ibcon#about to read 4, iclass 6, count 0 2006.285.16:18:01.64#ibcon#read 4, iclass 6, count 0 2006.285.16:18:01.64#ibcon#about to read 5, iclass 6, count 0 2006.285.16:18:01.64#ibcon#read 5, iclass 6, count 0 2006.285.16:18:01.64#ibcon#about to read 6, iclass 6, count 0 2006.285.16:18:01.64#ibcon#read 6, iclass 6, count 0 2006.285.16:18:01.64#ibcon#end of sib2, iclass 6, count 0 2006.285.16:18:01.64#ibcon#*after write, iclass 6, count 0 2006.285.16:18:01.64#ibcon#*before return 0, iclass 6, count 0 2006.285.16:18:01.64#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:18:01.64#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:18:01.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.16:18:01.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.16:18:01.64$vck44/valo=4,624.99 2006.285.16:18:01.64#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.16:18:01.64#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.16:18:01.64#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:01.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:18:01.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:18:01.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:18:01.64#ibcon#enter wrdev, iclass 10, count 0 2006.285.16:18:01.64#ibcon#first serial, iclass 10, count 0 2006.285.16:18:01.64#ibcon#enter sib2, iclass 10, count 0 2006.285.16:18:01.64#ibcon#flushed, iclass 10, count 0 2006.285.16:18:01.64#ibcon#about to write, iclass 10, count 0 2006.285.16:18:01.64#ibcon#wrote, iclass 10, count 0 2006.285.16:18:01.64#ibcon#about to read 3, iclass 10, count 0 2006.285.16:18:01.66#ibcon#read 3, iclass 10, count 0 2006.285.16:18:01.87#ibcon#about to read 4, iclass 10, count 0 2006.285.16:18:01.87#ibcon#read 4, iclass 10, count 0 2006.285.16:18:01.87#ibcon#about to read 5, iclass 10, count 0 2006.285.16:18:01.87#ibcon#read 5, iclass 10, count 0 2006.285.16:18:01.87#ibcon#about to read 6, iclass 10, count 0 2006.285.16:18:01.87#ibcon#read 6, iclass 10, count 0 2006.285.16:18:01.87#ibcon#end of sib2, iclass 10, count 0 2006.285.16:18:01.87#ibcon#*mode == 0, iclass 10, count 0 2006.285.16:18:01.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.16:18:01.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.16:18:01.87#ibcon#*before write, iclass 10, count 0 2006.285.16:18:01.87#ibcon#enter sib2, iclass 10, count 0 2006.285.16:18:01.87#ibcon#flushed, iclass 10, count 0 2006.285.16:18:01.87#ibcon#about to write, iclass 10, count 0 2006.285.16:18:01.87#ibcon#wrote, iclass 10, count 0 2006.285.16:18:01.87#ibcon#about to read 3, iclass 10, count 0 2006.285.16:18:01.91#ibcon#read 3, iclass 10, count 0 2006.285.16:18:01.91#ibcon#about to read 4, iclass 10, count 0 2006.285.16:18:01.91#ibcon#read 4, iclass 10, count 0 2006.285.16:18:01.91#ibcon#about to read 5, iclass 10, count 0 2006.285.16:18:01.91#ibcon#read 5, iclass 10, count 0 2006.285.16:18:01.91#ibcon#about to read 6, iclass 10, count 0 2006.285.16:18:01.91#ibcon#read 6, iclass 10, count 0 2006.285.16:18:01.91#ibcon#end of sib2, iclass 10, count 0 2006.285.16:18:01.91#ibcon#*after write, iclass 10, count 0 2006.285.16:18:01.91#ibcon#*before return 0, iclass 10, count 0 2006.285.16:18:01.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:18:01.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:18:01.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.16:18:01.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.16:18:01.91$vck44/va=4,6 2006.285.16:18:01.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.16:18:01.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.16:18:01.91#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:01.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:18:01.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:18:01.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:18:01.91#ibcon#enter wrdev, iclass 12, count 2 2006.285.16:18:01.91#ibcon#first serial, iclass 12, count 2 2006.285.16:18:01.91#ibcon#enter sib2, iclass 12, count 2 2006.285.16:18:01.91#ibcon#flushed, iclass 12, count 2 2006.285.16:18:01.91#ibcon#about to write, iclass 12, count 2 2006.285.16:18:01.91#ibcon#wrote, iclass 12, count 2 2006.285.16:18:01.91#ibcon#about to read 3, iclass 12, count 2 2006.285.16:18:01.93#ibcon#read 3, iclass 12, count 2 2006.285.16:18:01.93#ibcon#about to read 4, iclass 12, count 2 2006.285.16:18:01.93#ibcon#read 4, iclass 12, count 2 2006.285.16:18:01.93#ibcon#about to read 5, iclass 12, count 2 2006.285.16:18:01.93#ibcon#read 5, iclass 12, count 2 2006.285.16:18:01.93#ibcon#about to read 6, iclass 12, count 2 2006.285.16:18:01.93#ibcon#read 6, iclass 12, count 2 2006.285.16:18:01.93#ibcon#end of sib2, iclass 12, count 2 2006.285.16:18:01.93#ibcon#*mode == 0, iclass 12, count 2 2006.285.16:18:01.93#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.16:18:01.93#ibcon#[25=AT04-06\r\n] 2006.285.16:18:01.93#ibcon#*before write, iclass 12, count 2 2006.285.16:18:01.93#ibcon#enter sib2, iclass 12, count 2 2006.285.16:18:01.93#ibcon#flushed, iclass 12, count 2 2006.285.16:18:01.93#ibcon#about to write, iclass 12, count 2 2006.285.16:18:01.93#ibcon#wrote, iclass 12, count 2 2006.285.16:18:01.93#ibcon#about to read 3, iclass 12, count 2 2006.285.16:18:01.96#ibcon#read 3, iclass 12, count 2 2006.285.16:18:01.96#ibcon#about to read 4, iclass 12, count 2 2006.285.16:18:01.96#ibcon#read 4, iclass 12, count 2 2006.285.16:18:01.96#ibcon#about to read 5, iclass 12, count 2 2006.285.16:18:01.96#ibcon#read 5, iclass 12, count 2 2006.285.16:18:01.96#ibcon#about to read 6, iclass 12, count 2 2006.285.16:18:01.96#ibcon#read 6, iclass 12, count 2 2006.285.16:18:01.96#ibcon#end of sib2, iclass 12, count 2 2006.285.16:18:01.96#ibcon#*after write, iclass 12, count 2 2006.285.16:18:01.96#ibcon#*before return 0, iclass 12, count 2 2006.285.16:18:01.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:18:01.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:18:01.96#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.16:18:01.96#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:01.96#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:18:02.08#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:18:02.08#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:18:02.08#ibcon#enter wrdev, iclass 12, count 0 2006.285.16:18:02.08#ibcon#first serial, iclass 12, count 0 2006.285.16:18:02.08#ibcon#enter sib2, iclass 12, count 0 2006.285.16:18:02.08#ibcon#flushed, iclass 12, count 0 2006.285.16:18:02.08#ibcon#about to write, iclass 12, count 0 2006.285.16:18:02.08#ibcon#wrote, iclass 12, count 0 2006.285.16:18:02.08#ibcon#about to read 3, iclass 12, count 0 2006.285.16:18:02.10#ibcon#read 3, iclass 12, count 0 2006.285.16:18:02.10#ibcon#about to read 4, iclass 12, count 0 2006.285.16:18:02.10#ibcon#read 4, iclass 12, count 0 2006.285.16:18:02.10#ibcon#about to read 5, iclass 12, count 0 2006.285.16:18:02.10#ibcon#read 5, iclass 12, count 0 2006.285.16:18:02.10#ibcon#about to read 6, iclass 12, count 0 2006.285.16:18:02.10#ibcon#read 6, iclass 12, count 0 2006.285.16:18:02.10#ibcon#end of sib2, iclass 12, count 0 2006.285.16:18:02.10#ibcon#*mode == 0, iclass 12, count 0 2006.285.16:18:02.10#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.16:18:02.10#ibcon#[25=USB\r\n] 2006.285.16:18:02.10#ibcon#*before write, iclass 12, count 0 2006.285.16:18:02.10#ibcon#enter sib2, iclass 12, count 0 2006.285.16:18:02.10#ibcon#flushed, iclass 12, count 0 2006.285.16:18:02.10#ibcon#about to write, iclass 12, count 0 2006.285.16:18:02.10#ibcon#wrote, iclass 12, count 0 2006.285.16:18:02.10#ibcon#about to read 3, iclass 12, count 0 2006.285.16:18:02.13#ibcon#read 3, iclass 12, count 0 2006.285.16:18:02.13#ibcon#about to read 4, iclass 12, count 0 2006.285.16:18:02.13#ibcon#read 4, iclass 12, count 0 2006.285.16:18:02.13#ibcon#about to read 5, iclass 12, count 0 2006.285.16:18:02.13#ibcon#read 5, iclass 12, count 0 2006.285.16:18:02.13#ibcon#about to read 6, iclass 12, count 0 2006.285.16:18:02.13#ibcon#read 6, iclass 12, count 0 2006.285.16:18:02.13#ibcon#end of sib2, iclass 12, count 0 2006.285.16:18:02.13#ibcon#*after write, iclass 12, count 0 2006.285.16:18:02.13#ibcon#*before return 0, iclass 12, count 0 2006.285.16:18:02.13#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:18:02.13#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:18:02.13#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.16:18:02.13#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.16:18:02.13$vck44/valo=5,734.99 2006.285.16:18:02.13#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.16:18:02.13#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.16:18:02.13#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:02.13#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:18:02.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:18:02.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:18:02.13#ibcon#enter wrdev, iclass 14, count 0 2006.285.16:18:02.13#ibcon#first serial, iclass 14, count 0 2006.285.16:18:02.13#ibcon#enter sib2, iclass 14, count 0 2006.285.16:18:02.13#ibcon#flushed, iclass 14, count 0 2006.285.16:18:02.13#ibcon#about to write, iclass 14, count 0 2006.285.16:18:02.13#ibcon#wrote, iclass 14, count 0 2006.285.16:18:02.13#ibcon#about to read 3, iclass 14, count 0 2006.285.16:18:02.15#ibcon#read 3, iclass 14, count 0 2006.285.16:18:02.15#ibcon#about to read 4, iclass 14, count 0 2006.285.16:18:02.15#ibcon#read 4, iclass 14, count 0 2006.285.16:18:02.15#ibcon#about to read 5, iclass 14, count 0 2006.285.16:18:02.15#ibcon#read 5, iclass 14, count 0 2006.285.16:18:02.15#ibcon#about to read 6, iclass 14, count 0 2006.285.16:18:02.15#ibcon#read 6, iclass 14, count 0 2006.285.16:18:02.15#ibcon#end of sib2, iclass 14, count 0 2006.285.16:18:02.15#ibcon#*mode == 0, iclass 14, count 0 2006.285.16:18:02.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.16:18:02.15#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.16:18:02.15#ibcon#*before write, iclass 14, count 0 2006.285.16:18:02.15#ibcon#enter sib2, iclass 14, count 0 2006.285.16:18:02.15#ibcon#flushed, iclass 14, count 0 2006.285.16:18:02.15#ibcon#about to write, iclass 14, count 0 2006.285.16:18:02.15#ibcon#wrote, iclass 14, count 0 2006.285.16:18:02.15#ibcon#about to read 3, iclass 14, count 0 2006.285.16:18:02.19#ibcon#read 3, iclass 14, count 0 2006.285.16:18:02.19#ibcon#about to read 4, iclass 14, count 0 2006.285.16:18:02.19#ibcon#read 4, iclass 14, count 0 2006.285.16:18:02.19#ibcon#about to read 5, iclass 14, count 0 2006.285.16:18:02.19#ibcon#read 5, iclass 14, count 0 2006.285.16:18:02.19#ibcon#about to read 6, iclass 14, count 0 2006.285.16:18:02.19#ibcon#read 6, iclass 14, count 0 2006.285.16:18:02.19#ibcon#end of sib2, iclass 14, count 0 2006.285.16:18:02.19#ibcon#*after write, iclass 14, count 0 2006.285.16:18:02.19#ibcon#*before return 0, iclass 14, count 0 2006.285.16:18:02.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:18:02.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:18:02.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.16:18:02.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.16:18:02.19$vck44/va=5,3 2006.285.16:18:02.19#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.16:18:02.19#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.16:18:02.19#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:02.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:18:02.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:18:02.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:18:02.25#ibcon#enter wrdev, iclass 16, count 2 2006.285.16:18:02.25#ibcon#first serial, iclass 16, count 2 2006.285.16:18:02.25#ibcon#enter sib2, iclass 16, count 2 2006.285.16:18:02.25#ibcon#flushed, iclass 16, count 2 2006.285.16:18:02.25#ibcon#about to write, iclass 16, count 2 2006.285.16:18:02.25#ibcon#wrote, iclass 16, count 2 2006.285.16:18:02.25#ibcon#about to read 3, iclass 16, count 2 2006.285.16:18:02.27#ibcon#read 3, iclass 16, count 2 2006.285.16:18:02.27#ibcon#about to read 4, iclass 16, count 2 2006.285.16:18:02.27#ibcon#read 4, iclass 16, count 2 2006.285.16:18:02.27#ibcon#about to read 5, iclass 16, count 2 2006.285.16:18:02.27#ibcon#read 5, iclass 16, count 2 2006.285.16:18:02.27#ibcon#about to read 6, iclass 16, count 2 2006.285.16:18:02.27#ibcon#read 6, iclass 16, count 2 2006.285.16:18:02.27#ibcon#end of sib2, iclass 16, count 2 2006.285.16:18:02.27#ibcon#*mode == 0, iclass 16, count 2 2006.285.16:18:02.27#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.16:18:02.27#ibcon#[25=AT05-03\r\n] 2006.285.16:18:02.27#ibcon#*before write, iclass 16, count 2 2006.285.16:18:02.27#ibcon#enter sib2, iclass 16, count 2 2006.285.16:18:02.27#ibcon#flushed, iclass 16, count 2 2006.285.16:18:02.27#ibcon#about to write, iclass 16, count 2 2006.285.16:18:02.27#ibcon#wrote, iclass 16, count 2 2006.285.16:18:02.27#ibcon#about to read 3, iclass 16, count 2 2006.285.16:18:02.30#ibcon#read 3, iclass 16, count 2 2006.285.16:18:02.30#ibcon#about to read 4, iclass 16, count 2 2006.285.16:18:02.30#ibcon#read 4, iclass 16, count 2 2006.285.16:18:02.30#ibcon#about to read 5, iclass 16, count 2 2006.285.16:18:02.30#ibcon#read 5, iclass 16, count 2 2006.285.16:18:02.30#ibcon#about to read 6, iclass 16, count 2 2006.285.16:18:02.30#ibcon#read 6, iclass 16, count 2 2006.285.16:18:02.30#ibcon#end of sib2, iclass 16, count 2 2006.285.16:18:02.30#ibcon#*after write, iclass 16, count 2 2006.285.16:18:02.30#ibcon#*before return 0, iclass 16, count 2 2006.285.16:18:02.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:18:02.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:18:02.30#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.16:18:02.30#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:02.30#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:18:02.42#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:18:02.42#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:18:02.42#ibcon#enter wrdev, iclass 16, count 0 2006.285.16:18:02.42#ibcon#first serial, iclass 16, count 0 2006.285.16:18:02.42#ibcon#enter sib2, iclass 16, count 0 2006.285.16:18:02.42#ibcon#flushed, iclass 16, count 0 2006.285.16:18:02.42#ibcon#about to write, iclass 16, count 0 2006.285.16:18:02.42#ibcon#wrote, iclass 16, count 0 2006.285.16:18:02.42#ibcon#about to read 3, iclass 16, count 0 2006.285.16:18:02.44#ibcon#read 3, iclass 16, count 0 2006.285.16:18:02.44#ibcon#about to read 4, iclass 16, count 0 2006.285.16:18:02.44#ibcon#read 4, iclass 16, count 0 2006.285.16:18:02.44#ibcon#about to read 5, iclass 16, count 0 2006.285.16:18:02.44#ibcon#read 5, iclass 16, count 0 2006.285.16:18:02.44#ibcon#about to read 6, iclass 16, count 0 2006.285.16:18:02.44#ibcon#read 6, iclass 16, count 0 2006.285.16:18:02.44#ibcon#end of sib2, iclass 16, count 0 2006.285.16:18:02.44#ibcon#*mode == 0, iclass 16, count 0 2006.285.16:18:02.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.16:18:02.44#ibcon#[25=USB\r\n] 2006.285.16:18:02.44#ibcon#*before write, iclass 16, count 0 2006.285.16:18:02.44#ibcon#enter sib2, iclass 16, count 0 2006.285.16:18:02.44#ibcon#flushed, iclass 16, count 0 2006.285.16:18:02.44#ibcon#about to write, iclass 16, count 0 2006.285.16:18:02.44#ibcon#wrote, iclass 16, count 0 2006.285.16:18:02.44#ibcon#about to read 3, iclass 16, count 0 2006.285.16:18:02.47#ibcon#read 3, iclass 16, count 0 2006.285.16:18:02.47#ibcon#about to read 4, iclass 16, count 0 2006.285.16:18:02.47#ibcon#read 4, iclass 16, count 0 2006.285.16:18:02.47#ibcon#about to read 5, iclass 16, count 0 2006.285.16:18:02.47#ibcon#read 5, iclass 16, count 0 2006.285.16:18:02.47#ibcon#about to read 6, iclass 16, count 0 2006.285.16:18:02.47#ibcon#read 6, iclass 16, count 0 2006.285.16:18:02.47#ibcon#end of sib2, iclass 16, count 0 2006.285.16:18:02.47#ibcon#*after write, iclass 16, count 0 2006.285.16:18:02.47#ibcon#*before return 0, iclass 16, count 0 2006.285.16:18:02.47#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:18:02.47#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:18:02.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.16:18:02.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.16:18:02.47$vck44/valo=6,814.99 2006.285.16:18:02.47#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.16:18:02.47#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.16:18:02.47#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:02.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:18:02.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:18:02.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:18:02.47#ibcon#enter wrdev, iclass 18, count 0 2006.285.16:18:02.47#ibcon#first serial, iclass 18, count 0 2006.285.16:18:02.47#ibcon#enter sib2, iclass 18, count 0 2006.285.16:18:02.47#ibcon#flushed, iclass 18, count 0 2006.285.16:18:02.47#ibcon#about to write, iclass 18, count 0 2006.285.16:18:02.47#ibcon#wrote, iclass 18, count 0 2006.285.16:18:02.47#ibcon#about to read 3, iclass 18, count 0 2006.285.16:18:02.49#ibcon#read 3, iclass 18, count 0 2006.285.16:18:02.49#ibcon#about to read 4, iclass 18, count 0 2006.285.16:18:02.49#ibcon#read 4, iclass 18, count 0 2006.285.16:18:02.49#ibcon#about to read 5, iclass 18, count 0 2006.285.16:18:02.49#ibcon#read 5, iclass 18, count 0 2006.285.16:18:02.49#ibcon#about to read 6, iclass 18, count 0 2006.285.16:18:02.49#ibcon#read 6, iclass 18, count 0 2006.285.16:18:02.49#ibcon#end of sib2, iclass 18, count 0 2006.285.16:18:02.49#ibcon#*mode == 0, iclass 18, count 0 2006.285.16:18:02.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.16:18:02.49#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.16:18:02.49#ibcon#*before write, iclass 18, count 0 2006.285.16:18:02.49#ibcon#enter sib2, iclass 18, count 0 2006.285.16:18:02.49#ibcon#flushed, iclass 18, count 0 2006.285.16:18:02.49#ibcon#about to write, iclass 18, count 0 2006.285.16:18:02.49#ibcon#wrote, iclass 18, count 0 2006.285.16:18:02.49#ibcon#about to read 3, iclass 18, count 0 2006.285.16:18:02.53#ibcon#read 3, iclass 18, count 0 2006.285.16:18:02.53#ibcon#about to read 4, iclass 18, count 0 2006.285.16:18:02.53#ibcon#read 4, iclass 18, count 0 2006.285.16:18:02.53#ibcon#about to read 5, iclass 18, count 0 2006.285.16:18:02.53#ibcon#read 5, iclass 18, count 0 2006.285.16:18:02.53#ibcon#about to read 6, iclass 18, count 0 2006.285.16:18:02.53#ibcon#read 6, iclass 18, count 0 2006.285.16:18:02.53#ibcon#end of sib2, iclass 18, count 0 2006.285.16:18:02.53#ibcon#*after write, iclass 18, count 0 2006.285.16:18:02.53#ibcon#*before return 0, iclass 18, count 0 2006.285.16:18:02.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:18:02.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:18:02.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.16:18:02.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.16:18:02.53$vck44/va=6,4 2006.285.16:18:02.53#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.16:18:02.53#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.16:18:02.53#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:02.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:18:02.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:18:02.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:18:02.59#ibcon#enter wrdev, iclass 20, count 2 2006.285.16:18:02.59#ibcon#first serial, iclass 20, count 2 2006.285.16:18:02.59#ibcon#enter sib2, iclass 20, count 2 2006.285.16:18:02.59#ibcon#flushed, iclass 20, count 2 2006.285.16:18:02.59#ibcon#about to write, iclass 20, count 2 2006.285.16:18:02.59#ibcon#wrote, iclass 20, count 2 2006.285.16:18:02.59#ibcon#about to read 3, iclass 20, count 2 2006.285.16:18:02.61#ibcon#read 3, iclass 20, count 2 2006.285.16:18:02.61#ibcon#about to read 4, iclass 20, count 2 2006.285.16:18:02.61#ibcon#read 4, iclass 20, count 2 2006.285.16:18:02.61#ibcon#about to read 5, iclass 20, count 2 2006.285.16:18:02.61#ibcon#read 5, iclass 20, count 2 2006.285.16:18:02.61#ibcon#about to read 6, iclass 20, count 2 2006.285.16:18:02.61#ibcon#read 6, iclass 20, count 2 2006.285.16:18:02.61#ibcon#end of sib2, iclass 20, count 2 2006.285.16:18:02.61#ibcon#*mode == 0, iclass 20, count 2 2006.285.16:18:02.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.16:18:02.61#ibcon#[25=AT06-04\r\n] 2006.285.16:18:02.61#ibcon#*before write, iclass 20, count 2 2006.285.16:18:02.61#ibcon#enter sib2, iclass 20, count 2 2006.285.16:18:02.61#ibcon#flushed, iclass 20, count 2 2006.285.16:18:02.61#ibcon#about to write, iclass 20, count 2 2006.285.16:18:02.61#ibcon#wrote, iclass 20, count 2 2006.285.16:18:02.61#ibcon#about to read 3, iclass 20, count 2 2006.285.16:18:02.64#ibcon#read 3, iclass 20, count 2 2006.285.16:18:02.64#ibcon#about to read 4, iclass 20, count 2 2006.285.16:18:02.64#ibcon#read 4, iclass 20, count 2 2006.285.16:18:02.64#ibcon#about to read 5, iclass 20, count 2 2006.285.16:18:02.64#ibcon#read 5, iclass 20, count 2 2006.285.16:18:02.64#ibcon#about to read 6, iclass 20, count 2 2006.285.16:18:02.64#ibcon#read 6, iclass 20, count 2 2006.285.16:18:02.64#ibcon#end of sib2, iclass 20, count 2 2006.285.16:18:02.64#ibcon#*after write, iclass 20, count 2 2006.285.16:18:02.64#ibcon#*before return 0, iclass 20, count 2 2006.285.16:18:02.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:18:02.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:18:02.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.16:18:02.64#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:02.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:18:02.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:18:02.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:18:02.76#ibcon#enter wrdev, iclass 20, count 0 2006.285.16:18:02.76#ibcon#first serial, iclass 20, count 0 2006.285.16:18:02.76#ibcon#enter sib2, iclass 20, count 0 2006.285.16:18:02.76#ibcon#flushed, iclass 20, count 0 2006.285.16:18:02.76#ibcon#about to write, iclass 20, count 0 2006.285.16:18:02.76#ibcon#wrote, iclass 20, count 0 2006.285.16:18:02.76#ibcon#about to read 3, iclass 20, count 0 2006.285.16:18:02.78#ibcon#read 3, iclass 20, count 0 2006.285.16:18:02.78#ibcon#about to read 4, iclass 20, count 0 2006.285.16:18:02.78#ibcon#read 4, iclass 20, count 0 2006.285.16:18:02.78#ibcon#about to read 5, iclass 20, count 0 2006.285.16:18:02.78#ibcon#read 5, iclass 20, count 0 2006.285.16:18:02.78#ibcon#about to read 6, iclass 20, count 0 2006.285.16:18:02.78#ibcon#read 6, iclass 20, count 0 2006.285.16:18:02.78#ibcon#end of sib2, iclass 20, count 0 2006.285.16:18:02.78#ibcon#*mode == 0, iclass 20, count 0 2006.285.16:18:02.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.16:18:02.78#ibcon#[25=USB\r\n] 2006.285.16:18:02.78#ibcon#*before write, iclass 20, count 0 2006.285.16:18:02.78#ibcon#enter sib2, iclass 20, count 0 2006.285.16:18:02.78#ibcon#flushed, iclass 20, count 0 2006.285.16:18:02.78#ibcon#about to write, iclass 20, count 0 2006.285.16:18:02.78#ibcon#wrote, iclass 20, count 0 2006.285.16:18:02.78#ibcon#about to read 3, iclass 20, count 0 2006.285.16:18:02.81#ibcon#read 3, iclass 20, count 0 2006.285.16:18:02.81#ibcon#about to read 4, iclass 20, count 0 2006.285.16:18:02.81#ibcon#read 4, iclass 20, count 0 2006.285.16:18:02.81#ibcon#about to read 5, iclass 20, count 0 2006.285.16:18:02.81#ibcon#read 5, iclass 20, count 0 2006.285.16:18:02.81#ibcon#about to read 6, iclass 20, count 0 2006.285.16:18:02.81#ibcon#read 6, iclass 20, count 0 2006.285.16:18:02.81#ibcon#end of sib2, iclass 20, count 0 2006.285.16:18:02.81#ibcon#*after write, iclass 20, count 0 2006.285.16:18:02.81#ibcon#*before return 0, iclass 20, count 0 2006.285.16:18:02.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:18:02.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:18:02.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.16:18:02.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.16:18:02.81$vck44/valo=7,864.99 2006.285.16:18:02.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.16:18:02.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.16:18:02.81#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:02.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:18:02.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:18:02.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:18:02.81#ibcon#enter wrdev, iclass 22, count 0 2006.285.16:18:02.81#ibcon#first serial, iclass 22, count 0 2006.285.16:18:02.81#ibcon#enter sib2, iclass 22, count 0 2006.285.16:18:02.81#ibcon#flushed, iclass 22, count 0 2006.285.16:18:02.81#ibcon#about to write, iclass 22, count 0 2006.285.16:18:02.81#ibcon#wrote, iclass 22, count 0 2006.285.16:18:02.81#ibcon#about to read 3, iclass 22, count 0 2006.285.16:18:02.83#ibcon#read 3, iclass 22, count 0 2006.285.16:18:02.83#ibcon#about to read 4, iclass 22, count 0 2006.285.16:18:02.83#ibcon#read 4, iclass 22, count 0 2006.285.16:18:02.83#ibcon#about to read 5, iclass 22, count 0 2006.285.16:18:02.83#ibcon#read 5, iclass 22, count 0 2006.285.16:18:02.83#ibcon#about to read 6, iclass 22, count 0 2006.285.16:18:02.83#ibcon#read 6, iclass 22, count 0 2006.285.16:18:02.83#ibcon#end of sib2, iclass 22, count 0 2006.285.16:18:02.83#ibcon#*mode == 0, iclass 22, count 0 2006.285.16:18:02.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.16:18:02.83#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.16:18:02.83#ibcon#*before write, iclass 22, count 0 2006.285.16:18:02.83#ibcon#enter sib2, iclass 22, count 0 2006.285.16:18:02.83#ibcon#flushed, iclass 22, count 0 2006.285.16:18:02.83#ibcon#about to write, iclass 22, count 0 2006.285.16:18:02.83#ibcon#wrote, iclass 22, count 0 2006.285.16:18:02.83#ibcon#about to read 3, iclass 22, count 0 2006.285.16:18:02.87#ibcon#read 3, iclass 22, count 0 2006.285.16:18:02.87#ibcon#about to read 4, iclass 22, count 0 2006.285.16:18:02.87#ibcon#read 4, iclass 22, count 0 2006.285.16:18:02.87#ibcon#about to read 5, iclass 22, count 0 2006.285.16:18:02.87#ibcon#read 5, iclass 22, count 0 2006.285.16:18:02.87#ibcon#about to read 6, iclass 22, count 0 2006.285.16:18:02.87#ibcon#read 6, iclass 22, count 0 2006.285.16:18:02.87#ibcon#end of sib2, iclass 22, count 0 2006.285.16:18:02.87#ibcon#*after write, iclass 22, count 0 2006.285.16:18:02.87#ibcon#*before return 0, iclass 22, count 0 2006.285.16:18:02.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:18:02.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:18:02.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.16:18:02.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.16:18:02.87$vck44/va=7,4 2006.285.16:18:02.87#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.16:18:02.87#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.16:18:02.87#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:02.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:18:02.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:18:02.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:18:02.93#ibcon#enter wrdev, iclass 24, count 2 2006.285.16:18:02.93#ibcon#first serial, iclass 24, count 2 2006.285.16:18:02.93#ibcon#enter sib2, iclass 24, count 2 2006.285.16:18:02.93#ibcon#flushed, iclass 24, count 2 2006.285.16:18:02.93#ibcon#about to write, iclass 24, count 2 2006.285.16:18:02.93#ibcon#wrote, iclass 24, count 2 2006.285.16:18:02.93#ibcon#about to read 3, iclass 24, count 2 2006.285.16:18:02.95#ibcon#read 3, iclass 24, count 2 2006.285.16:18:02.95#ibcon#about to read 4, iclass 24, count 2 2006.285.16:18:02.95#ibcon#read 4, iclass 24, count 2 2006.285.16:18:02.95#ibcon#about to read 5, iclass 24, count 2 2006.285.16:18:02.95#ibcon#read 5, iclass 24, count 2 2006.285.16:18:02.95#ibcon#about to read 6, iclass 24, count 2 2006.285.16:18:02.95#ibcon#read 6, iclass 24, count 2 2006.285.16:18:02.95#ibcon#end of sib2, iclass 24, count 2 2006.285.16:18:02.95#ibcon#*mode == 0, iclass 24, count 2 2006.285.16:18:02.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.16:18:02.95#ibcon#[25=AT07-04\r\n] 2006.285.16:18:02.95#ibcon#*before write, iclass 24, count 2 2006.285.16:18:02.95#ibcon#enter sib2, iclass 24, count 2 2006.285.16:18:02.95#ibcon#flushed, iclass 24, count 2 2006.285.16:18:02.95#ibcon#about to write, iclass 24, count 2 2006.285.16:18:02.95#ibcon#wrote, iclass 24, count 2 2006.285.16:18:02.95#ibcon#about to read 3, iclass 24, count 2 2006.285.16:18:02.98#ibcon#read 3, iclass 24, count 2 2006.285.16:18:02.98#ibcon#about to read 4, iclass 24, count 2 2006.285.16:18:02.98#ibcon#read 4, iclass 24, count 2 2006.285.16:18:02.98#ibcon#about to read 5, iclass 24, count 2 2006.285.16:18:02.98#ibcon#read 5, iclass 24, count 2 2006.285.16:18:02.98#ibcon#about to read 6, iclass 24, count 2 2006.285.16:18:02.98#ibcon#read 6, iclass 24, count 2 2006.285.16:18:02.98#ibcon#end of sib2, iclass 24, count 2 2006.285.16:18:02.98#ibcon#*after write, iclass 24, count 2 2006.285.16:18:02.98#ibcon#*before return 0, iclass 24, count 2 2006.285.16:18:02.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:18:02.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:18:02.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.16:18:02.98#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:02.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:18:03.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:18:03.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:18:03.18#ibcon#enter wrdev, iclass 24, count 0 2006.285.16:18:03.18#ibcon#first serial, iclass 24, count 0 2006.285.16:18:03.18#ibcon#enter sib2, iclass 24, count 0 2006.285.16:18:03.18#ibcon#flushed, iclass 24, count 0 2006.285.16:18:03.18#ibcon#about to write, iclass 24, count 0 2006.285.16:18:03.18#ibcon#wrote, iclass 24, count 0 2006.285.16:18:03.18#ibcon#about to read 3, iclass 24, count 0 2006.285.16:18:03.19#ibcon#read 3, iclass 24, count 0 2006.285.16:18:03.19#ibcon#about to read 4, iclass 24, count 0 2006.285.16:18:03.19#ibcon#read 4, iclass 24, count 0 2006.285.16:18:03.19#ibcon#about to read 5, iclass 24, count 0 2006.285.16:18:03.19#ibcon#read 5, iclass 24, count 0 2006.285.16:18:03.19#ibcon#about to read 6, iclass 24, count 0 2006.285.16:18:03.19#ibcon#read 6, iclass 24, count 0 2006.285.16:18:03.19#ibcon#end of sib2, iclass 24, count 0 2006.285.16:18:03.19#ibcon#*mode == 0, iclass 24, count 0 2006.285.16:18:03.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.16:18:03.19#ibcon#[25=USB\r\n] 2006.285.16:18:03.19#ibcon#*before write, iclass 24, count 0 2006.285.16:18:03.19#ibcon#enter sib2, iclass 24, count 0 2006.285.16:18:03.19#ibcon#flushed, iclass 24, count 0 2006.285.16:18:03.19#ibcon#about to write, iclass 24, count 0 2006.285.16:18:03.19#ibcon#wrote, iclass 24, count 0 2006.285.16:18:03.19#ibcon#about to read 3, iclass 24, count 0 2006.285.16:18:03.22#ibcon#read 3, iclass 24, count 0 2006.285.16:18:03.22#ibcon#about to read 4, iclass 24, count 0 2006.285.16:18:03.22#ibcon#read 4, iclass 24, count 0 2006.285.16:18:03.22#ibcon#about to read 5, iclass 24, count 0 2006.285.16:18:03.22#ibcon#read 5, iclass 24, count 0 2006.285.16:18:03.22#ibcon#about to read 6, iclass 24, count 0 2006.285.16:18:03.22#ibcon#read 6, iclass 24, count 0 2006.285.16:18:03.22#ibcon#end of sib2, iclass 24, count 0 2006.285.16:18:03.22#ibcon#*after write, iclass 24, count 0 2006.285.16:18:03.22#ibcon#*before return 0, iclass 24, count 0 2006.285.16:18:03.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:18:03.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:18:03.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.16:18:03.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.16:18:03.22$vck44/valo=8,884.99 2006.285.16:18:03.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.16:18:03.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.16:18:03.22#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:03.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:18:03.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:18:03.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:18:03.22#ibcon#enter wrdev, iclass 26, count 0 2006.285.16:18:03.22#ibcon#first serial, iclass 26, count 0 2006.285.16:18:03.22#ibcon#enter sib2, iclass 26, count 0 2006.285.16:18:03.22#ibcon#flushed, iclass 26, count 0 2006.285.16:18:03.22#ibcon#about to write, iclass 26, count 0 2006.285.16:18:03.22#ibcon#wrote, iclass 26, count 0 2006.285.16:18:03.22#ibcon#about to read 3, iclass 26, count 0 2006.285.16:18:03.24#ibcon#read 3, iclass 26, count 0 2006.285.16:18:03.24#ibcon#about to read 4, iclass 26, count 0 2006.285.16:18:03.24#ibcon#read 4, iclass 26, count 0 2006.285.16:18:03.24#ibcon#about to read 5, iclass 26, count 0 2006.285.16:18:03.24#ibcon#read 5, iclass 26, count 0 2006.285.16:18:03.24#ibcon#about to read 6, iclass 26, count 0 2006.285.16:18:03.24#ibcon#read 6, iclass 26, count 0 2006.285.16:18:03.24#ibcon#end of sib2, iclass 26, count 0 2006.285.16:18:03.24#ibcon#*mode == 0, iclass 26, count 0 2006.285.16:18:03.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.16:18:03.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.16:18:03.24#ibcon#*before write, iclass 26, count 0 2006.285.16:18:03.24#ibcon#enter sib2, iclass 26, count 0 2006.285.16:18:03.24#ibcon#flushed, iclass 26, count 0 2006.285.16:18:03.24#ibcon#about to write, iclass 26, count 0 2006.285.16:18:03.24#ibcon#wrote, iclass 26, count 0 2006.285.16:18:03.24#ibcon#about to read 3, iclass 26, count 0 2006.285.16:18:03.28#ibcon#read 3, iclass 26, count 0 2006.285.16:18:03.28#ibcon#about to read 4, iclass 26, count 0 2006.285.16:18:03.28#ibcon#read 4, iclass 26, count 0 2006.285.16:18:03.28#ibcon#about to read 5, iclass 26, count 0 2006.285.16:18:03.28#ibcon#read 5, iclass 26, count 0 2006.285.16:18:03.28#ibcon#about to read 6, iclass 26, count 0 2006.285.16:18:03.28#ibcon#read 6, iclass 26, count 0 2006.285.16:18:03.28#ibcon#end of sib2, iclass 26, count 0 2006.285.16:18:03.28#ibcon#*after write, iclass 26, count 0 2006.285.16:18:03.28#ibcon#*before return 0, iclass 26, count 0 2006.285.16:18:03.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:18:03.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:18:03.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.16:18:03.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.16:18:03.28$vck44/va=8,3 2006.285.16:18:03.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.16:18:03.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.16:18:03.28#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:03.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:18:03.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:18:03.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:18:03.34#ibcon#enter wrdev, iclass 28, count 2 2006.285.16:18:03.34#ibcon#first serial, iclass 28, count 2 2006.285.16:18:03.34#ibcon#enter sib2, iclass 28, count 2 2006.285.16:18:03.34#ibcon#flushed, iclass 28, count 2 2006.285.16:18:03.34#ibcon#about to write, iclass 28, count 2 2006.285.16:18:03.34#ibcon#wrote, iclass 28, count 2 2006.285.16:18:03.34#ibcon#about to read 3, iclass 28, count 2 2006.285.16:18:03.36#ibcon#read 3, iclass 28, count 2 2006.285.16:18:03.36#ibcon#about to read 4, iclass 28, count 2 2006.285.16:18:03.36#ibcon#read 4, iclass 28, count 2 2006.285.16:18:03.36#ibcon#about to read 5, iclass 28, count 2 2006.285.16:18:03.36#ibcon#read 5, iclass 28, count 2 2006.285.16:18:03.36#ibcon#about to read 6, iclass 28, count 2 2006.285.16:18:03.36#ibcon#read 6, iclass 28, count 2 2006.285.16:18:03.36#ibcon#end of sib2, iclass 28, count 2 2006.285.16:18:03.36#ibcon#*mode == 0, iclass 28, count 2 2006.285.16:18:03.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.16:18:03.36#ibcon#[25=AT08-03\r\n] 2006.285.16:18:03.36#ibcon#*before write, iclass 28, count 2 2006.285.16:18:03.36#ibcon#enter sib2, iclass 28, count 2 2006.285.16:18:03.36#ibcon#flushed, iclass 28, count 2 2006.285.16:18:03.36#ibcon#about to write, iclass 28, count 2 2006.285.16:18:03.36#ibcon#wrote, iclass 28, count 2 2006.285.16:18:03.36#ibcon#about to read 3, iclass 28, count 2 2006.285.16:18:03.39#ibcon#read 3, iclass 28, count 2 2006.285.16:18:03.39#ibcon#about to read 4, iclass 28, count 2 2006.285.16:18:03.39#ibcon#read 4, iclass 28, count 2 2006.285.16:18:03.39#ibcon#about to read 5, iclass 28, count 2 2006.285.16:18:03.39#ibcon#read 5, iclass 28, count 2 2006.285.16:18:03.39#ibcon#about to read 6, iclass 28, count 2 2006.285.16:18:03.39#ibcon#read 6, iclass 28, count 2 2006.285.16:18:03.39#ibcon#end of sib2, iclass 28, count 2 2006.285.16:18:03.39#ibcon#*after write, iclass 28, count 2 2006.285.16:18:03.39#ibcon#*before return 0, iclass 28, count 2 2006.285.16:18:03.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:18:03.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:18:03.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.16:18:03.39#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:03.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:18:03.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:18:03.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:18:03.51#ibcon#enter wrdev, iclass 28, count 0 2006.285.16:18:03.51#ibcon#first serial, iclass 28, count 0 2006.285.16:18:03.51#ibcon#enter sib2, iclass 28, count 0 2006.285.16:18:03.51#ibcon#flushed, iclass 28, count 0 2006.285.16:18:03.51#ibcon#about to write, iclass 28, count 0 2006.285.16:18:03.51#ibcon#wrote, iclass 28, count 0 2006.285.16:18:03.51#ibcon#about to read 3, iclass 28, count 0 2006.285.16:18:03.53#ibcon#read 3, iclass 28, count 0 2006.285.16:18:03.53#ibcon#about to read 4, iclass 28, count 0 2006.285.16:18:03.53#ibcon#read 4, iclass 28, count 0 2006.285.16:18:03.53#ibcon#about to read 5, iclass 28, count 0 2006.285.16:18:03.53#ibcon#read 5, iclass 28, count 0 2006.285.16:18:03.53#ibcon#about to read 6, iclass 28, count 0 2006.285.16:18:03.53#ibcon#read 6, iclass 28, count 0 2006.285.16:18:03.53#ibcon#end of sib2, iclass 28, count 0 2006.285.16:18:03.53#ibcon#*mode == 0, iclass 28, count 0 2006.285.16:18:03.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.16:18:03.53#ibcon#[25=USB\r\n] 2006.285.16:18:03.53#ibcon#*before write, iclass 28, count 0 2006.285.16:18:03.53#ibcon#enter sib2, iclass 28, count 0 2006.285.16:18:03.53#ibcon#flushed, iclass 28, count 0 2006.285.16:18:03.53#ibcon#about to write, iclass 28, count 0 2006.285.16:18:03.53#ibcon#wrote, iclass 28, count 0 2006.285.16:18:03.53#ibcon#about to read 3, iclass 28, count 0 2006.285.16:18:03.56#ibcon#read 3, iclass 28, count 0 2006.285.16:18:03.56#ibcon#about to read 4, iclass 28, count 0 2006.285.16:18:03.56#ibcon#read 4, iclass 28, count 0 2006.285.16:18:03.56#ibcon#about to read 5, iclass 28, count 0 2006.285.16:18:03.56#ibcon#read 5, iclass 28, count 0 2006.285.16:18:03.56#ibcon#about to read 6, iclass 28, count 0 2006.285.16:18:03.56#ibcon#read 6, iclass 28, count 0 2006.285.16:18:03.56#ibcon#end of sib2, iclass 28, count 0 2006.285.16:18:03.56#ibcon#*after write, iclass 28, count 0 2006.285.16:18:03.56#ibcon#*before return 0, iclass 28, count 0 2006.285.16:18:03.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:18:03.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:18:03.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.16:18:03.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.16:18:03.56$vck44/vblo=1,629.99 2006.285.16:18:03.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.16:18:03.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.16:18:03.56#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:03.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:18:03.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:18:03.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:18:03.56#ibcon#enter wrdev, iclass 30, count 0 2006.285.16:18:03.56#ibcon#first serial, iclass 30, count 0 2006.285.16:18:03.56#ibcon#enter sib2, iclass 30, count 0 2006.285.16:18:03.56#ibcon#flushed, iclass 30, count 0 2006.285.16:18:03.56#ibcon#about to write, iclass 30, count 0 2006.285.16:18:03.56#ibcon#wrote, iclass 30, count 0 2006.285.16:18:03.56#ibcon#about to read 3, iclass 30, count 0 2006.285.16:18:03.58#ibcon#read 3, iclass 30, count 0 2006.285.16:18:03.58#ibcon#about to read 4, iclass 30, count 0 2006.285.16:18:03.58#ibcon#read 4, iclass 30, count 0 2006.285.16:18:03.58#ibcon#about to read 5, iclass 30, count 0 2006.285.16:18:03.58#ibcon#read 5, iclass 30, count 0 2006.285.16:18:03.58#ibcon#about to read 6, iclass 30, count 0 2006.285.16:18:03.58#ibcon#read 6, iclass 30, count 0 2006.285.16:18:03.58#ibcon#end of sib2, iclass 30, count 0 2006.285.16:18:03.58#ibcon#*mode == 0, iclass 30, count 0 2006.285.16:18:03.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.16:18:03.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.16:18:03.58#ibcon#*before write, iclass 30, count 0 2006.285.16:18:03.58#ibcon#enter sib2, iclass 30, count 0 2006.285.16:18:03.58#ibcon#flushed, iclass 30, count 0 2006.285.16:18:03.58#ibcon#about to write, iclass 30, count 0 2006.285.16:18:03.58#ibcon#wrote, iclass 30, count 0 2006.285.16:18:03.58#ibcon#about to read 3, iclass 30, count 0 2006.285.16:18:03.62#ibcon#read 3, iclass 30, count 0 2006.285.16:18:03.62#ibcon#about to read 4, iclass 30, count 0 2006.285.16:18:03.62#ibcon#read 4, iclass 30, count 0 2006.285.16:18:03.62#ibcon#about to read 5, iclass 30, count 0 2006.285.16:18:03.62#ibcon#read 5, iclass 30, count 0 2006.285.16:18:03.62#ibcon#about to read 6, iclass 30, count 0 2006.285.16:18:03.62#ibcon#read 6, iclass 30, count 0 2006.285.16:18:03.62#ibcon#end of sib2, iclass 30, count 0 2006.285.16:18:03.62#ibcon#*after write, iclass 30, count 0 2006.285.16:18:03.62#ibcon#*before return 0, iclass 30, count 0 2006.285.16:18:03.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:18:03.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:18:03.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.16:18:03.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.16:18:03.62$vck44/vb=1,4 2006.285.16:18:03.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.16:18:03.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.16:18:03.62#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:03.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:18:03.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:18:03.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:18:03.62#ibcon#enter wrdev, iclass 32, count 2 2006.285.16:18:03.62#ibcon#first serial, iclass 32, count 2 2006.285.16:18:03.62#ibcon#enter sib2, iclass 32, count 2 2006.285.16:18:03.62#ibcon#flushed, iclass 32, count 2 2006.285.16:18:03.62#ibcon#about to write, iclass 32, count 2 2006.285.16:18:03.62#ibcon#wrote, iclass 32, count 2 2006.285.16:18:03.62#ibcon#about to read 3, iclass 32, count 2 2006.285.16:18:03.64#ibcon#read 3, iclass 32, count 2 2006.285.16:18:03.64#ibcon#about to read 4, iclass 32, count 2 2006.285.16:18:03.64#ibcon#read 4, iclass 32, count 2 2006.285.16:18:03.64#ibcon#about to read 5, iclass 32, count 2 2006.285.16:18:03.64#ibcon#read 5, iclass 32, count 2 2006.285.16:18:03.64#ibcon#about to read 6, iclass 32, count 2 2006.285.16:18:03.64#ibcon#read 6, iclass 32, count 2 2006.285.16:18:03.64#ibcon#end of sib2, iclass 32, count 2 2006.285.16:18:03.64#ibcon#*mode == 0, iclass 32, count 2 2006.285.16:18:03.64#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.16:18:03.64#ibcon#[27=AT01-04\r\n] 2006.285.16:18:03.64#ibcon#*before write, iclass 32, count 2 2006.285.16:18:03.64#ibcon#enter sib2, iclass 32, count 2 2006.285.16:18:03.64#ibcon#flushed, iclass 32, count 2 2006.285.16:18:03.64#ibcon#about to write, iclass 32, count 2 2006.285.16:18:03.64#ibcon#wrote, iclass 32, count 2 2006.285.16:18:03.64#ibcon#about to read 3, iclass 32, count 2 2006.285.16:18:03.67#ibcon#read 3, iclass 32, count 2 2006.285.16:18:03.67#ibcon#about to read 4, iclass 32, count 2 2006.285.16:18:03.67#ibcon#read 4, iclass 32, count 2 2006.285.16:18:03.67#ibcon#about to read 5, iclass 32, count 2 2006.285.16:18:03.67#ibcon#read 5, iclass 32, count 2 2006.285.16:18:03.67#ibcon#about to read 6, iclass 32, count 2 2006.285.16:18:03.67#ibcon#read 6, iclass 32, count 2 2006.285.16:18:03.67#ibcon#end of sib2, iclass 32, count 2 2006.285.16:18:03.67#ibcon#*after write, iclass 32, count 2 2006.285.16:18:03.67#ibcon#*before return 0, iclass 32, count 2 2006.285.16:18:03.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:18:03.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:18:03.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.16:18:03.67#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:03.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:18:03.79#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:18:03.79#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:18:03.79#ibcon#enter wrdev, iclass 32, count 0 2006.285.16:18:03.79#ibcon#first serial, iclass 32, count 0 2006.285.16:18:03.79#ibcon#enter sib2, iclass 32, count 0 2006.285.16:18:03.79#ibcon#flushed, iclass 32, count 0 2006.285.16:18:03.79#ibcon#about to write, iclass 32, count 0 2006.285.16:18:03.79#ibcon#wrote, iclass 32, count 0 2006.285.16:18:03.79#ibcon#about to read 3, iclass 32, count 0 2006.285.16:18:03.81#ibcon#read 3, iclass 32, count 0 2006.285.16:18:03.81#ibcon#about to read 4, iclass 32, count 0 2006.285.16:18:03.81#ibcon#read 4, iclass 32, count 0 2006.285.16:18:03.81#ibcon#about to read 5, iclass 32, count 0 2006.285.16:18:03.81#ibcon#read 5, iclass 32, count 0 2006.285.16:18:03.81#ibcon#about to read 6, iclass 32, count 0 2006.285.16:18:03.81#ibcon#read 6, iclass 32, count 0 2006.285.16:18:03.81#ibcon#end of sib2, iclass 32, count 0 2006.285.16:18:03.81#ibcon#*mode == 0, iclass 32, count 0 2006.285.16:18:03.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.16:18:03.81#ibcon#[27=USB\r\n] 2006.285.16:18:03.81#ibcon#*before write, iclass 32, count 0 2006.285.16:18:03.81#ibcon#enter sib2, iclass 32, count 0 2006.285.16:18:03.81#ibcon#flushed, iclass 32, count 0 2006.285.16:18:03.81#ibcon#about to write, iclass 32, count 0 2006.285.16:18:03.81#ibcon#wrote, iclass 32, count 0 2006.285.16:18:03.81#ibcon#about to read 3, iclass 32, count 0 2006.285.16:18:03.84#ibcon#read 3, iclass 32, count 0 2006.285.16:18:03.84#ibcon#about to read 4, iclass 32, count 0 2006.285.16:18:03.84#ibcon#read 4, iclass 32, count 0 2006.285.16:18:03.84#ibcon#about to read 5, iclass 32, count 0 2006.285.16:18:03.84#ibcon#read 5, iclass 32, count 0 2006.285.16:18:03.84#ibcon#about to read 6, iclass 32, count 0 2006.285.16:18:03.84#ibcon#read 6, iclass 32, count 0 2006.285.16:18:03.84#ibcon#end of sib2, iclass 32, count 0 2006.285.16:18:03.84#ibcon#*after write, iclass 32, count 0 2006.285.16:18:03.84#ibcon#*before return 0, iclass 32, count 0 2006.285.16:18:03.84#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:18:03.84#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:18:03.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.16:18:03.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.16:18:03.84$vck44/vblo=2,634.99 2006.285.16:18:03.84#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.16:18:03.84#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.16:18:03.84#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:03.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:18:03.84#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:18:03.84#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:18:03.84#ibcon#enter wrdev, iclass 34, count 0 2006.285.16:18:03.84#ibcon#first serial, iclass 34, count 0 2006.285.16:18:03.84#ibcon#enter sib2, iclass 34, count 0 2006.285.16:18:03.84#ibcon#flushed, iclass 34, count 0 2006.285.16:18:03.84#ibcon#about to write, iclass 34, count 0 2006.285.16:18:03.84#ibcon#wrote, iclass 34, count 0 2006.285.16:18:03.84#ibcon#about to read 3, iclass 34, count 0 2006.285.16:18:03.86#ibcon#read 3, iclass 34, count 0 2006.285.16:18:03.86#ibcon#about to read 4, iclass 34, count 0 2006.285.16:18:03.86#ibcon#read 4, iclass 34, count 0 2006.285.16:18:03.86#ibcon#about to read 5, iclass 34, count 0 2006.285.16:18:03.86#ibcon#read 5, iclass 34, count 0 2006.285.16:18:03.86#ibcon#about to read 6, iclass 34, count 0 2006.285.16:18:03.86#ibcon#read 6, iclass 34, count 0 2006.285.16:18:03.86#ibcon#end of sib2, iclass 34, count 0 2006.285.16:18:03.86#ibcon#*mode == 0, iclass 34, count 0 2006.285.16:18:03.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.16:18:03.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.16:18:03.86#ibcon#*before write, iclass 34, count 0 2006.285.16:18:03.86#ibcon#enter sib2, iclass 34, count 0 2006.285.16:18:03.86#ibcon#flushed, iclass 34, count 0 2006.285.16:18:03.86#ibcon#about to write, iclass 34, count 0 2006.285.16:18:03.86#ibcon#wrote, iclass 34, count 0 2006.285.16:18:03.86#ibcon#about to read 3, iclass 34, count 0 2006.285.16:18:03.90#ibcon#read 3, iclass 34, count 0 2006.285.16:18:03.90#ibcon#about to read 4, iclass 34, count 0 2006.285.16:18:03.90#ibcon#read 4, iclass 34, count 0 2006.285.16:18:03.90#ibcon#about to read 5, iclass 34, count 0 2006.285.16:18:03.90#ibcon#read 5, iclass 34, count 0 2006.285.16:18:03.90#ibcon#about to read 6, iclass 34, count 0 2006.285.16:18:03.90#ibcon#read 6, iclass 34, count 0 2006.285.16:18:03.90#ibcon#end of sib2, iclass 34, count 0 2006.285.16:18:03.90#ibcon#*after write, iclass 34, count 0 2006.285.16:18:03.90#ibcon#*before return 0, iclass 34, count 0 2006.285.16:18:03.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:18:03.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:18:03.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.16:18:03.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.16:18:03.90$vck44/vb=2,5 2006.285.16:18:03.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.16:18:03.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.16:18:03.90#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:03.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:18:03.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:18:03.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:18:03.96#ibcon#enter wrdev, iclass 36, count 2 2006.285.16:18:03.96#ibcon#first serial, iclass 36, count 2 2006.285.16:18:03.96#ibcon#enter sib2, iclass 36, count 2 2006.285.16:18:03.96#ibcon#flushed, iclass 36, count 2 2006.285.16:18:03.96#ibcon#about to write, iclass 36, count 2 2006.285.16:18:03.96#ibcon#wrote, iclass 36, count 2 2006.285.16:18:03.96#ibcon#about to read 3, iclass 36, count 2 2006.285.16:18:03.98#ibcon#read 3, iclass 36, count 2 2006.285.16:18:03.98#ibcon#about to read 4, iclass 36, count 2 2006.285.16:18:03.98#ibcon#read 4, iclass 36, count 2 2006.285.16:18:03.98#ibcon#about to read 5, iclass 36, count 2 2006.285.16:18:03.98#ibcon#read 5, iclass 36, count 2 2006.285.16:18:03.98#ibcon#about to read 6, iclass 36, count 2 2006.285.16:18:03.98#ibcon#read 6, iclass 36, count 2 2006.285.16:18:03.98#ibcon#end of sib2, iclass 36, count 2 2006.285.16:18:03.98#ibcon#*mode == 0, iclass 36, count 2 2006.285.16:18:03.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.16:18:03.98#ibcon#[27=AT02-05\r\n] 2006.285.16:18:03.98#ibcon#*before write, iclass 36, count 2 2006.285.16:18:03.98#ibcon#enter sib2, iclass 36, count 2 2006.285.16:18:03.98#ibcon#flushed, iclass 36, count 2 2006.285.16:18:03.98#ibcon#about to write, iclass 36, count 2 2006.285.16:18:03.98#ibcon#wrote, iclass 36, count 2 2006.285.16:18:03.98#ibcon#about to read 3, iclass 36, count 2 2006.285.16:18:04.01#ibcon#read 3, iclass 36, count 2 2006.285.16:18:04.01#ibcon#about to read 4, iclass 36, count 2 2006.285.16:18:04.01#ibcon#read 4, iclass 36, count 2 2006.285.16:18:04.01#ibcon#about to read 5, iclass 36, count 2 2006.285.16:18:04.01#ibcon#read 5, iclass 36, count 2 2006.285.16:18:04.01#ibcon#about to read 6, iclass 36, count 2 2006.285.16:18:04.01#ibcon#read 6, iclass 36, count 2 2006.285.16:18:04.01#ibcon#end of sib2, iclass 36, count 2 2006.285.16:18:04.01#ibcon#*after write, iclass 36, count 2 2006.285.16:18:04.01#ibcon#*before return 0, iclass 36, count 2 2006.285.16:18:04.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:18:04.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:18:04.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.16:18:04.01#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:04.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:18:04.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:18:04.14#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:18:04.14#ibcon#enter wrdev, iclass 36, count 0 2006.285.16:18:04.14#ibcon#first serial, iclass 36, count 0 2006.285.16:18:04.14#ibcon#enter sib2, iclass 36, count 0 2006.285.16:18:04.14#ibcon#flushed, iclass 36, count 0 2006.285.16:18:04.14#ibcon#about to write, iclass 36, count 0 2006.285.16:18:04.14#ibcon#wrote, iclass 36, count 0 2006.285.16:18:04.14#ibcon#about to read 3, iclass 36, count 0 2006.285.16:18:04.16#ibcon#read 3, iclass 36, count 0 2006.285.16:18:04.16#ibcon#about to read 4, iclass 36, count 0 2006.285.16:18:04.16#ibcon#read 4, iclass 36, count 0 2006.285.16:18:04.16#ibcon#about to read 5, iclass 36, count 0 2006.285.16:18:04.16#ibcon#read 5, iclass 36, count 0 2006.285.16:18:04.16#ibcon#about to read 6, iclass 36, count 0 2006.285.16:18:04.16#ibcon#read 6, iclass 36, count 0 2006.285.16:18:04.16#ibcon#end of sib2, iclass 36, count 0 2006.285.16:18:04.16#ibcon#*mode == 0, iclass 36, count 0 2006.285.16:18:04.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.16:18:04.16#ibcon#[27=USB\r\n] 2006.285.16:18:04.16#ibcon#*before write, iclass 36, count 0 2006.285.16:18:04.16#ibcon#enter sib2, iclass 36, count 0 2006.285.16:18:04.16#ibcon#flushed, iclass 36, count 0 2006.285.16:18:04.16#ibcon#about to write, iclass 36, count 0 2006.285.16:18:04.16#ibcon#wrote, iclass 36, count 0 2006.285.16:18:04.16#ibcon#about to read 3, iclass 36, count 0 2006.285.16:18:04.19#ibcon#read 3, iclass 36, count 0 2006.285.16:18:04.19#ibcon#about to read 4, iclass 36, count 0 2006.285.16:18:04.19#ibcon#read 4, iclass 36, count 0 2006.285.16:18:04.19#ibcon#about to read 5, iclass 36, count 0 2006.285.16:18:04.19#ibcon#read 5, iclass 36, count 0 2006.285.16:18:04.19#ibcon#about to read 6, iclass 36, count 0 2006.285.16:18:04.19#ibcon#read 6, iclass 36, count 0 2006.285.16:18:04.19#ibcon#end of sib2, iclass 36, count 0 2006.285.16:18:04.19#ibcon#*after write, iclass 36, count 0 2006.285.16:18:04.19#ibcon#*before return 0, iclass 36, count 0 2006.285.16:18:04.19#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:18:04.19#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:18:04.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.16:18:04.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.16:18:04.19$vck44/vblo=3,649.99 2006.285.16:18:04.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.16:18:04.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.16:18:04.19#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:04.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:18:04.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:18:04.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:18:04.19#ibcon#enter wrdev, iclass 38, count 0 2006.285.16:18:04.19#ibcon#first serial, iclass 38, count 0 2006.285.16:18:04.19#ibcon#enter sib2, iclass 38, count 0 2006.285.16:18:04.19#ibcon#flushed, iclass 38, count 0 2006.285.16:18:04.19#ibcon#about to write, iclass 38, count 0 2006.285.16:18:04.19#ibcon#wrote, iclass 38, count 0 2006.285.16:18:04.19#ibcon#about to read 3, iclass 38, count 0 2006.285.16:18:04.21#ibcon#read 3, iclass 38, count 0 2006.285.16:18:04.21#ibcon#about to read 4, iclass 38, count 0 2006.285.16:18:04.21#ibcon#read 4, iclass 38, count 0 2006.285.16:18:04.21#ibcon#about to read 5, iclass 38, count 0 2006.285.16:18:04.21#ibcon#read 5, iclass 38, count 0 2006.285.16:18:04.21#ibcon#about to read 6, iclass 38, count 0 2006.285.16:18:04.21#ibcon#read 6, iclass 38, count 0 2006.285.16:18:04.21#ibcon#end of sib2, iclass 38, count 0 2006.285.16:18:04.21#ibcon#*mode == 0, iclass 38, count 0 2006.285.16:18:04.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.16:18:04.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.16:18:04.21#ibcon#*before write, iclass 38, count 0 2006.285.16:18:04.21#ibcon#enter sib2, iclass 38, count 0 2006.285.16:18:04.21#ibcon#flushed, iclass 38, count 0 2006.285.16:18:04.21#ibcon#about to write, iclass 38, count 0 2006.285.16:18:04.21#ibcon#wrote, iclass 38, count 0 2006.285.16:18:04.21#ibcon#about to read 3, iclass 38, count 0 2006.285.16:18:04.25#ibcon#read 3, iclass 38, count 0 2006.285.16:18:04.25#ibcon#about to read 4, iclass 38, count 0 2006.285.16:18:04.25#ibcon#read 4, iclass 38, count 0 2006.285.16:18:04.25#ibcon#about to read 5, iclass 38, count 0 2006.285.16:18:04.25#ibcon#read 5, iclass 38, count 0 2006.285.16:18:04.25#ibcon#about to read 6, iclass 38, count 0 2006.285.16:18:04.25#ibcon#read 6, iclass 38, count 0 2006.285.16:18:04.25#ibcon#end of sib2, iclass 38, count 0 2006.285.16:18:04.25#ibcon#*after write, iclass 38, count 0 2006.285.16:18:04.25#ibcon#*before return 0, iclass 38, count 0 2006.285.16:18:04.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:18:04.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:18:04.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.16:18:04.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.16:18:04.25$vck44/vb=3,4 2006.285.16:18:04.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.16:18:04.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.16:18:04.25#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:04.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:18:04.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:18:04.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:18:04.31#ibcon#enter wrdev, iclass 40, count 2 2006.285.16:18:04.31#ibcon#first serial, iclass 40, count 2 2006.285.16:18:04.31#ibcon#enter sib2, iclass 40, count 2 2006.285.16:18:04.31#ibcon#flushed, iclass 40, count 2 2006.285.16:18:04.31#ibcon#about to write, iclass 40, count 2 2006.285.16:18:04.31#ibcon#wrote, iclass 40, count 2 2006.285.16:18:04.31#ibcon#about to read 3, iclass 40, count 2 2006.285.16:18:04.33#ibcon#read 3, iclass 40, count 2 2006.285.16:18:04.33#ibcon#about to read 4, iclass 40, count 2 2006.285.16:18:04.33#ibcon#read 4, iclass 40, count 2 2006.285.16:18:04.33#ibcon#about to read 5, iclass 40, count 2 2006.285.16:18:04.33#ibcon#read 5, iclass 40, count 2 2006.285.16:18:04.33#ibcon#about to read 6, iclass 40, count 2 2006.285.16:18:04.33#ibcon#read 6, iclass 40, count 2 2006.285.16:18:04.33#ibcon#end of sib2, iclass 40, count 2 2006.285.16:18:04.33#ibcon#*mode == 0, iclass 40, count 2 2006.285.16:18:04.33#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.16:18:04.33#ibcon#[27=AT03-04\r\n] 2006.285.16:18:04.33#ibcon#*before write, iclass 40, count 2 2006.285.16:18:04.33#ibcon#enter sib2, iclass 40, count 2 2006.285.16:18:04.33#ibcon#flushed, iclass 40, count 2 2006.285.16:18:04.33#ibcon#about to write, iclass 40, count 2 2006.285.16:18:04.33#ibcon#wrote, iclass 40, count 2 2006.285.16:18:04.33#ibcon#about to read 3, iclass 40, count 2 2006.285.16:18:04.36#ibcon#read 3, iclass 40, count 2 2006.285.16:18:04.36#ibcon#about to read 4, iclass 40, count 2 2006.285.16:18:04.36#ibcon#read 4, iclass 40, count 2 2006.285.16:18:04.36#ibcon#about to read 5, iclass 40, count 2 2006.285.16:18:04.36#ibcon#read 5, iclass 40, count 2 2006.285.16:18:04.36#ibcon#about to read 6, iclass 40, count 2 2006.285.16:18:04.36#ibcon#read 6, iclass 40, count 2 2006.285.16:18:04.36#ibcon#end of sib2, iclass 40, count 2 2006.285.16:18:04.36#ibcon#*after write, iclass 40, count 2 2006.285.16:18:04.36#ibcon#*before return 0, iclass 40, count 2 2006.285.16:18:04.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:18:04.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:18:04.36#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.16:18:04.36#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:04.36#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:18:04.48#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:18:04.48#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:18:04.48#ibcon#enter wrdev, iclass 40, count 0 2006.285.16:18:04.48#ibcon#first serial, iclass 40, count 0 2006.285.16:18:04.48#ibcon#enter sib2, iclass 40, count 0 2006.285.16:18:04.48#ibcon#flushed, iclass 40, count 0 2006.285.16:18:04.48#ibcon#about to write, iclass 40, count 0 2006.285.16:18:04.48#ibcon#wrote, iclass 40, count 0 2006.285.16:18:04.48#ibcon#about to read 3, iclass 40, count 0 2006.285.16:18:04.50#ibcon#read 3, iclass 40, count 0 2006.285.16:18:04.50#ibcon#about to read 4, iclass 40, count 0 2006.285.16:18:04.50#ibcon#read 4, iclass 40, count 0 2006.285.16:18:04.50#ibcon#about to read 5, iclass 40, count 0 2006.285.16:18:04.50#ibcon#read 5, iclass 40, count 0 2006.285.16:18:04.50#ibcon#about to read 6, iclass 40, count 0 2006.285.16:18:04.50#ibcon#read 6, iclass 40, count 0 2006.285.16:18:04.50#ibcon#end of sib2, iclass 40, count 0 2006.285.16:18:04.50#ibcon#*mode == 0, iclass 40, count 0 2006.285.16:18:04.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.16:18:04.50#ibcon#[27=USB\r\n] 2006.285.16:18:04.50#ibcon#*before write, iclass 40, count 0 2006.285.16:18:04.50#ibcon#enter sib2, iclass 40, count 0 2006.285.16:18:04.50#ibcon#flushed, iclass 40, count 0 2006.285.16:18:04.50#ibcon#about to write, iclass 40, count 0 2006.285.16:18:04.50#ibcon#wrote, iclass 40, count 0 2006.285.16:18:04.50#ibcon#about to read 3, iclass 40, count 0 2006.285.16:18:04.53#ibcon#read 3, iclass 40, count 0 2006.285.16:18:04.53#ibcon#about to read 4, iclass 40, count 0 2006.285.16:18:04.53#ibcon#read 4, iclass 40, count 0 2006.285.16:18:04.53#ibcon#about to read 5, iclass 40, count 0 2006.285.16:18:04.53#ibcon#read 5, iclass 40, count 0 2006.285.16:18:04.53#ibcon#about to read 6, iclass 40, count 0 2006.285.16:18:04.53#ibcon#read 6, iclass 40, count 0 2006.285.16:18:04.53#ibcon#end of sib2, iclass 40, count 0 2006.285.16:18:04.53#ibcon#*after write, iclass 40, count 0 2006.285.16:18:04.53#ibcon#*before return 0, iclass 40, count 0 2006.285.16:18:04.53#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:18:04.53#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:18:04.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.16:18:04.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.16:18:04.53$vck44/vblo=4,679.99 2006.285.16:18:04.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.16:18:04.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.16:18:04.53#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:04.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:18:04.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:18:04.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:18:04.53#ibcon#enter wrdev, iclass 4, count 0 2006.285.16:18:04.53#ibcon#first serial, iclass 4, count 0 2006.285.16:18:04.53#ibcon#enter sib2, iclass 4, count 0 2006.285.16:18:04.53#ibcon#flushed, iclass 4, count 0 2006.285.16:18:04.53#ibcon#about to write, iclass 4, count 0 2006.285.16:18:04.53#ibcon#wrote, iclass 4, count 0 2006.285.16:18:04.53#ibcon#about to read 3, iclass 4, count 0 2006.285.16:18:04.55#ibcon#read 3, iclass 4, count 0 2006.285.16:18:04.55#ibcon#about to read 4, iclass 4, count 0 2006.285.16:18:04.55#ibcon#read 4, iclass 4, count 0 2006.285.16:18:04.55#ibcon#about to read 5, iclass 4, count 0 2006.285.16:18:04.55#ibcon#read 5, iclass 4, count 0 2006.285.16:18:04.55#ibcon#about to read 6, iclass 4, count 0 2006.285.16:18:04.55#ibcon#read 6, iclass 4, count 0 2006.285.16:18:04.55#ibcon#end of sib2, iclass 4, count 0 2006.285.16:18:04.55#ibcon#*mode == 0, iclass 4, count 0 2006.285.16:18:04.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.16:18:04.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.16:18:04.55#ibcon#*before write, iclass 4, count 0 2006.285.16:18:04.55#ibcon#enter sib2, iclass 4, count 0 2006.285.16:18:04.55#ibcon#flushed, iclass 4, count 0 2006.285.16:18:04.55#ibcon#about to write, iclass 4, count 0 2006.285.16:18:04.55#ibcon#wrote, iclass 4, count 0 2006.285.16:18:04.55#ibcon#about to read 3, iclass 4, count 0 2006.285.16:18:04.59#ibcon#read 3, iclass 4, count 0 2006.285.16:18:04.59#ibcon#about to read 4, iclass 4, count 0 2006.285.16:18:04.59#ibcon#read 4, iclass 4, count 0 2006.285.16:18:04.59#ibcon#about to read 5, iclass 4, count 0 2006.285.16:18:04.59#ibcon#read 5, iclass 4, count 0 2006.285.16:18:04.59#ibcon#about to read 6, iclass 4, count 0 2006.285.16:18:04.59#ibcon#read 6, iclass 4, count 0 2006.285.16:18:04.59#ibcon#end of sib2, iclass 4, count 0 2006.285.16:18:04.59#ibcon#*after write, iclass 4, count 0 2006.285.16:18:04.59#ibcon#*before return 0, iclass 4, count 0 2006.285.16:18:04.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:18:04.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:18:04.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.16:18:04.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.16:18:04.59$vck44/vb=4,5 2006.285.16:18:04.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.16:18:04.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.16:18:04.59#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:04.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:18:04.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:18:04.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:18:04.65#ibcon#enter wrdev, iclass 6, count 2 2006.285.16:18:04.65#ibcon#first serial, iclass 6, count 2 2006.285.16:18:04.65#ibcon#enter sib2, iclass 6, count 2 2006.285.16:18:04.65#ibcon#flushed, iclass 6, count 2 2006.285.16:18:04.65#ibcon#about to write, iclass 6, count 2 2006.285.16:18:04.65#ibcon#wrote, iclass 6, count 2 2006.285.16:18:04.65#ibcon#about to read 3, iclass 6, count 2 2006.285.16:18:04.67#ibcon#read 3, iclass 6, count 2 2006.285.16:18:04.67#ibcon#about to read 4, iclass 6, count 2 2006.285.16:18:04.67#ibcon#read 4, iclass 6, count 2 2006.285.16:18:04.67#ibcon#about to read 5, iclass 6, count 2 2006.285.16:18:04.67#ibcon#read 5, iclass 6, count 2 2006.285.16:18:04.67#ibcon#about to read 6, iclass 6, count 2 2006.285.16:18:04.67#ibcon#read 6, iclass 6, count 2 2006.285.16:18:04.67#ibcon#end of sib2, iclass 6, count 2 2006.285.16:18:04.67#ibcon#*mode == 0, iclass 6, count 2 2006.285.16:18:04.67#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.16:18:04.67#ibcon#[27=AT04-05\r\n] 2006.285.16:18:04.67#ibcon#*before write, iclass 6, count 2 2006.285.16:18:04.67#ibcon#enter sib2, iclass 6, count 2 2006.285.16:18:04.67#ibcon#flushed, iclass 6, count 2 2006.285.16:18:04.67#ibcon#about to write, iclass 6, count 2 2006.285.16:18:04.67#ibcon#wrote, iclass 6, count 2 2006.285.16:18:04.67#ibcon#about to read 3, iclass 6, count 2 2006.285.16:18:04.70#ibcon#read 3, iclass 6, count 2 2006.285.16:18:04.70#ibcon#about to read 4, iclass 6, count 2 2006.285.16:18:04.70#ibcon#read 4, iclass 6, count 2 2006.285.16:18:04.70#ibcon#about to read 5, iclass 6, count 2 2006.285.16:18:04.70#ibcon#read 5, iclass 6, count 2 2006.285.16:18:04.70#ibcon#about to read 6, iclass 6, count 2 2006.285.16:18:04.70#ibcon#read 6, iclass 6, count 2 2006.285.16:18:04.70#ibcon#end of sib2, iclass 6, count 2 2006.285.16:18:04.70#ibcon#*after write, iclass 6, count 2 2006.285.16:18:04.70#ibcon#*before return 0, iclass 6, count 2 2006.285.16:18:04.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:18:04.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:18:04.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.16:18:04.70#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:04.70#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:18:04.82#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:18:04.82#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:18:04.82#ibcon#enter wrdev, iclass 6, count 0 2006.285.16:18:04.82#ibcon#first serial, iclass 6, count 0 2006.285.16:18:04.82#ibcon#enter sib2, iclass 6, count 0 2006.285.16:18:04.82#ibcon#flushed, iclass 6, count 0 2006.285.16:18:04.82#ibcon#about to write, iclass 6, count 0 2006.285.16:18:04.82#ibcon#wrote, iclass 6, count 0 2006.285.16:18:04.82#ibcon#about to read 3, iclass 6, count 0 2006.285.16:18:04.84#ibcon#read 3, iclass 6, count 0 2006.285.16:18:04.84#ibcon#about to read 4, iclass 6, count 0 2006.285.16:18:04.84#ibcon#read 4, iclass 6, count 0 2006.285.16:18:04.84#ibcon#about to read 5, iclass 6, count 0 2006.285.16:18:04.84#ibcon#read 5, iclass 6, count 0 2006.285.16:18:04.84#ibcon#about to read 6, iclass 6, count 0 2006.285.16:18:04.84#ibcon#read 6, iclass 6, count 0 2006.285.16:18:04.84#ibcon#end of sib2, iclass 6, count 0 2006.285.16:18:04.84#ibcon#*mode == 0, iclass 6, count 0 2006.285.16:18:04.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.16:18:04.84#ibcon#[27=USB\r\n] 2006.285.16:18:04.84#ibcon#*before write, iclass 6, count 0 2006.285.16:18:04.84#ibcon#enter sib2, iclass 6, count 0 2006.285.16:18:04.84#ibcon#flushed, iclass 6, count 0 2006.285.16:18:04.84#ibcon#about to write, iclass 6, count 0 2006.285.16:18:04.84#ibcon#wrote, iclass 6, count 0 2006.285.16:18:04.84#ibcon#about to read 3, iclass 6, count 0 2006.285.16:18:04.87#ibcon#read 3, iclass 6, count 0 2006.285.16:18:04.87#ibcon#about to read 4, iclass 6, count 0 2006.285.16:18:04.87#ibcon#read 4, iclass 6, count 0 2006.285.16:18:04.87#ibcon#about to read 5, iclass 6, count 0 2006.285.16:18:04.87#ibcon#read 5, iclass 6, count 0 2006.285.16:18:04.87#ibcon#about to read 6, iclass 6, count 0 2006.285.16:18:04.87#ibcon#read 6, iclass 6, count 0 2006.285.16:18:04.87#ibcon#end of sib2, iclass 6, count 0 2006.285.16:18:04.87#ibcon#*after write, iclass 6, count 0 2006.285.16:18:04.87#ibcon#*before return 0, iclass 6, count 0 2006.285.16:18:04.87#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:18:04.87#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:18:04.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.16:18:04.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.16:18:04.87$vck44/vblo=5,709.99 2006.285.16:18:04.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.16:18:04.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.16:18:04.87#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:04.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:18:04.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:18:04.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:18:04.87#ibcon#enter wrdev, iclass 10, count 0 2006.285.16:18:04.87#ibcon#first serial, iclass 10, count 0 2006.285.16:18:04.87#ibcon#enter sib2, iclass 10, count 0 2006.285.16:18:04.87#ibcon#flushed, iclass 10, count 0 2006.285.16:18:04.87#ibcon#about to write, iclass 10, count 0 2006.285.16:18:04.87#ibcon#wrote, iclass 10, count 0 2006.285.16:18:04.87#ibcon#about to read 3, iclass 10, count 0 2006.285.16:18:04.89#ibcon#read 3, iclass 10, count 0 2006.285.16:18:04.89#ibcon#about to read 4, iclass 10, count 0 2006.285.16:18:04.89#ibcon#read 4, iclass 10, count 0 2006.285.16:18:04.89#ibcon#about to read 5, iclass 10, count 0 2006.285.16:18:04.89#ibcon#read 5, iclass 10, count 0 2006.285.16:18:04.89#ibcon#about to read 6, iclass 10, count 0 2006.285.16:18:04.89#ibcon#read 6, iclass 10, count 0 2006.285.16:18:04.89#ibcon#end of sib2, iclass 10, count 0 2006.285.16:18:04.89#ibcon#*mode == 0, iclass 10, count 0 2006.285.16:18:04.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.16:18:04.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.16:18:04.89#ibcon#*before write, iclass 10, count 0 2006.285.16:18:04.89#ibcon#enter sib2, iclass 10, count 0 2006.285.16:18:04.89#ibcon#flushed, iclass 10, count 0 2006.285.16:18:04.89#ibcon#about to write, iclass 10, count 0 2006.285.16:18:04.89#ibcon#wrote, iclass 10, count 0 2006.285.16:18:04.89#ibcon#about to read 3, iclass 10, count 0 2006.285.16:18:04.93#ibcon#read 3, iclass 10, count 0 2006.285.16:18:04.93#ibcon#about to read 4, iclass 10, count 0 2006.285.16:18:04.93#ibcon#read 4, iclass 10, count 0 2006.285.16:18:04.93#ibcon#about to read 5, iclass 10, count 0 2006.285.16:18:04.93#ibcon#read 5, iclass 10, count 0 2006.285.16:18:04.93#ibcon#about to read 6, iclass 10, count 0 2006.285.16:18:04.93#ibcon#read 6, iclass 10, count 0 2006.285.16:18:04.93#ibcon#end of sib2, iclass 10, count 0 2006.285.16:18:04.93#ibcon#*after write, iclass 10, count 0 2006.285.16:18:04.93#ibcon#*before return 0, iclass 10, count 0 2006.285.16:18:04.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:18:04.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:18:04.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.16:18:04.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.16:18:04.93$vck44/vb=5,4 2006.285.16:18:04.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.16:18:04.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.16:18:04.93#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:04.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:18:04.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:18:04.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:18:04.99#ibcon#enter wrdev, iclass 12, count 2 2006.285.16:18:04.99#ibcon#first serial, iclass 12, count 2 2006.285.16:18:04.99#ibcon#enter sib2, iclass 12, count 2 2006.285.16:18:04.99#ibcon#flushed, iclass 12, count 2 2006.285.16:18:04.99#ibcon#about to write, iclass 12, count 2 2006.285.16:18:04.99#ibcon#wrote, iclass 12, count 2 2006.285.16:18:04.99#ibcon#about to read 3, iclass 12, count 2 2006.285.16:18:05.01#ibcon#read 3, iclass 12, count 2 2006.285.16:18:05.01#ibcon#about to read 4, iclass 12, count 2 2006.285.16:18:05.01#ibcon#read 4, iclass 12, count 2 2006.285.16:18:05.01#ibcon#about to read 5, iclass 12, count 2 2006.285.16:18:05.01#ibcon#read 5, iclass 12, count 2 2006.285.16:18:05.01#ibcon#about to read 6, iclass 12, count 2 2006.285.16:18:05.01#ibcon#read 6, iclass 12, count 2 2006.285.16:18:05.01#ibcon#end of sib2, iclass 12, count 2 2006.285.16:18:05.01#ibcon#*mode == 0, iclass 12, count 2 2006.285.16:18:05.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.16:18:05.01#ibcon#[27=AT05-04\r\n] 2006.285.16:18:05.01#ibcon#*before write, iclass 12, count 2 2006.285.16:18:05.01#ibcon#enter sib2, iclass 12, count 2 2006.285.16:18:05.01#ibcon#flushed, iclass 12, count 2 2006.285.16:18:05.01#ibcon#about to write, iclass 12, count 2 2006.285.16:18:05.01#ibcon#wrote, iclass 12, count 2 2006.285.16:18:05.01#ibcon#about to read 3, iclass 12, count 2 2006.285.16:18:05.04#ibcon#read 3, iclass 12, count 2 2006.285.16:18:05.04#ibcon#about to read 4, iclass 12, count 2 2006.285.16:18:05.04#ibcon#read 4, iclass 12, count 2 2006.285.16:18:05.04#ibcon#about to read 5, iclass 12, count 2 2006.285.16:18:05.04#ibcon#read 5, iclass 12, count 2 2006.285.16:18:05.04#ibcon#about to read 6, iclass 12, count 2 2006.285.16:18:05.04#ibcon#read 6, iclass 12, count 2 2006.285.16:18:05.04#ibcon#end of sib2, iclass 12, count 2 2006.285.16:18:05.04#ibcon#*after write, iclass 12, count 2 2006.285.16:18:05.04#ibcon#*before return 0, iclass 12, count 2 2006.285.16:18:05.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:18:05.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:18:05.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.16:18:05.04#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:05.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:18:05.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:18:05.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:18:05.16#ibcon#enter wrdev, iclass 12, count 0 2006.285.16:18:05.16#ibcon#first serial, iclass 12, count 0 2006.285.16:18:05.16#ibcon#enter sib2, iclass 12, count 0 2006.285.16:18:05.16#ibcon#flushed, iclass 12, count 0 2006.285.16:18:05.16#ibcon#about to write, iclass 12, count 0 2006.285.16:18:05.16#ibcon#wrote, iclass 12, count 0 2006.285.16:18:05.16#ibcon#about to read 3, iclass 12, count 0 2006.285.16:18:05.18#ibcon#read 3, iclass 12, count 0 2006.285.16:18:05.18#ibcon#about to read 4, iclass 12, count 0 2006.285.16:18:05.18#ibcon#read 4, iclass 12, count 0 2006.285.16:18:05.18#ibcon#about to read 5, iclass 12, count 0 2006.285.16:18:05.18#ibcon#read 5, iclass 12, count 0 2006.285.16:18:05.18#ibcon#about to read 6, iclass 12, count 0 2006.285.16:18:05.18#ibcon#read 6, iclass 12, count 0 2006.285.16:18:05.18#ibcon#end of sib2, iclass 12, count 0 2006.285.16:18:05.18#ibcon#*mode == 0, iclass 12, count 0 2006.285.16:18:05.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.16:18:05.18#ibcon#[27=USB\r\n] 2006.285.16:18:05.18#ibcon#*before write, iclass 12, count 0 2006.285.16:18:05.18#ibcon#enter sib2, iclass 12, count 0 2006.285.16:18:05.18#ibcon#flushed, iclass 12, count 0 2006.285.16:18:05.18#ibcon#about to write, iclass 12, count 0 2006.285.16:18:05.18#ibcon#wrote, iclass 12, count 0 2006.285.16:18:05.18#ibcon#about to read 3, iclass 12, count 0 2006.285.16:18:05.21#ibcon#read 3, iclass 12, count 0 2006.285.16:18:05.21#ibcon#about to read 4, iclass 12, count 0 2006.285.16:18:05.21#ibcon#read 4, iclass 12, count 0 2006.285.16:18:05.21#ibcon#about to read 5, iclass 12, count 0 2006.285.16:18:05.21#ibcon#read 5, iclass 12, count 0 2006.285.16:18:05.21#ibcon#about to read 6, iclass 12, count 0 2006.285.16:18:05.21#ibcon#read 6, iclass 12, count 0 2006.285.16:18:05.21#ibcon#end of sib2, iclass 12, count 0 2006.285.16:18:05.21#ibcon#*after write, iclass 12, count 0 2006.285.16:18:05.21#ibcon#*before return 0, iclass 12, count 0 2006.285.16:18:05.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:18:05.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:18:05.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.16:18:05.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.16:18:05.21$vck44/vblo=6,719.99 2006.285.16:18:05.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.16:18:05.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.16:18:05.21#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:05.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:18:05.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:18:05.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:18:05.21#ibcon#enter wrdev, iclass 14, count 0 2006.285.16:18:05.21#ibcon#first serial, iclass 14, count 0 2006.285.16:18:05.21#ibcon#enter sib2, iclass 14, count 0 2006.285.16:18:05.21#ibcon#flushed, iclass 14, count 0 2006.285.16:18:05.21#ibcon#about to write, iclass 14, count 0 2006.285.16:18:05.21#ibcon#wrote, iclass 14, count 0 2006.285.16:18:05.21#ibcon#about to read 3, iclass 14, count 0 2006.285.16:18:05.23#ibcon#read 3, iclass 14, count 0 2006.285.16:18:05.23#ibcon#about to read 4, iclass 14, count 0 2006.285.16:18:05.23#ibcon#read 4, iclass 14, count 0 2006.285.16:18:05.23#ibcon#about to read 5, iclass 14, count 0 2006.285.16:18:05.23#ibcon#read 5, iclass 14, count 0 2006.285.16:18:05.23#ibcon#about to read 6, iclass 14, count 0 2006.285.16:18:05.23#ibcon#read 6, iclass 14, count 0 2006.285.16:18:05.23#ibcon#end of sib2, iclass 14, count 0 2006.285.16:18:05.23#ibcon#*mode == 0, iclass 14, count 0 2006.285.16:18:05.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.16:18:05.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.16:18:05.23#ibcon#*before write, iclass 14, count 0 2006.285.16:18:05.23#ibcon#enter sib2, iclass 14, count 0 2006.285.16:18:05.23#ibcon#flushed, iclass 14, count 0 2006.285.16:18:05.23#ibcon#about to write, iclass 14, count 0 2006.285.16:18:05.23#ibcon#wrote, iclass 14, count 0 2006.285.16:18:05.23#ibcon#about to read 3, iclass 14, count 0 2006.285.16:18:05.27#ibcon#read 3, iclass 14, count 0 2006.285.16:18:05.27#ibcon#about to read 4, iclass 14, count 0 2006.285.16:18:05.27#ibcon#read 4, iclass 14, count 0 2006.285.16:18:05.27#ibcon#about to read 5, iclass 14, count 0 2006.285.16:18:05.27#ibcon#read 5, iclass 14, count 0 2006.285.16:18:05.27#ibcon#about to read 6, iclass 14, count 0 2006.285.16:18:05.27#ibcon#read 6, iclass 14, count 0 2006.285.16:18:05.27#ibcon#end of sib2, iclass 14, count 0 2006.285.16:18:05.27#ibcon#*after write, iclass 14, count 0 2006.285.16:18:05.27#ibcon#*before return 0, iclass 14, count 0 2006.285.16:18:05.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:18:05.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:18:05.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.16:18:05.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.16:18:05.27$vck44/vb=6,3 2006.285.16:18:05.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.16:18:05.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.16:18:05.27#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:05.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:18:05.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:18:05.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:18:05.33#ibcon#enter wrdev, iclass 16, count 2 2006.285.16:18:05.33#ibcon#first serial, iclass 16, count 2 2006.285.16:18:05.33#ibcon#enter sib2, iclass 16, count 2 2006.285.16:18:05.33#ibcon#flushed, iclass 16, count 2 2006.285.16:18:05.33#ibcon#about to write, iclass 16, count 2 2006.285.16:18:05.33#ibcon#wrote, iclass 16, count 2 2006.285.16:18:05.33#ibcon#about to read 3, iclass 16, count 2 2006.285.16:18:05.35#ibcon#read 3, iclass 16, count 2 2006.285.16:18:05.35#ibcon#about to read 4, iclass 16, count 2 2006.285.16:18:05.35#ibcon#read 4, iclass 16, count 2 2006.285.16:18:05.35#ibcon#about to read 5, iclass 16, count 2 2006.285.16:18:05.35#ibcon#read 5, iclass 16, count 2 2006.285.16:18:05.35#ibcon#about to read 6, iclass 16, count 2 2006.285.16:18:05.35#ibcon#read 6, iclass 16, count 2 2006.285.16:18:05.35#ibcon#end of sib2, iclass 16, count 2 2006.285.16:18:05.35#ibcon#*mode == 0, iclass 16, count 2 2006.285.16:18:05.35#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.16:18:05.35#ibcon#[27=AT06-03\r\n] 2006.285.16:18:05.35#ibcon#*before write, iclass 16, count 2 2006.285.16:18:05.35#ibcon#enter sib2, iclass 16, count 2 2006.285.16:18:05.35#ibcon#flushed, iclass 16, count 2 2006.285.16:18:05.35#ibcon#about to write, iclass 16, count 2 2006.285.16:18:05.35#ibcon#wrote, iclass 16, count 2 2006.285.16:18:05.35#ibcon#about to read 3, iclass 16, count 2 2006.285.16:18:05.38#ibcon#read 3, iclass 16, count 2 2006.285.16:18:05.38#ibcon#about to read 4, iclass 16, count 2 2006.285.16:18:05.38#ibcon#read 4, iclass 16, count 2 2006.285.16:18:05.38#ibcon#about to read 5, iclass 16, count 2 2006.285.16:18:05.38#ibcon#read 5, iclass 16, count 2 2006.285.16:18:05.38#ibcon#about to read 6, iclass 16, count 2 2006.285.16:18:05.38#ibcon#read 6, iclass 16, count 2 2006.285.16:18:05.38#ibcon#end of sib2, iclass 16, count 2 2006.285.16:18:05.38#ibcon#*after write, iclass 16, count 2 2006.285.16:18:05.38#ibcon#*before return 0, iclass 16, count 2 2006.285.16:18:05.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:18:05.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:18:05.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.16:18:05.38#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:05.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:18:05.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:18:05.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:18:05.50#ibcon#enter wrdev, iclass 16, count 0 2006.285.16:18:05.50#ibcon#first serial, iclass 16, count 0 2006.285.16:18:05.50#ibcon#enter sib2, iclass 16, count 0 2006.285.16:18:05.50#ibcon#flushed, iclass 16, count 0 2006.285.16:18:05.50#ibcon#about to write, iclass 16, count 0 2006.285.16:18:05.50#ibcon#wrote, iclass 16, count 0 2006.285.16:18:05.50#ibcon#about to read 3, iclass 16, count 0 2006.285.16:18:05.52#ibcon#read 3, iclass 16, count 0 2006.285.16:18:05.52#ibcon#about to read 4, iclass 16, count 0 2006.285.16:18:05.52#ibcon#read 4, iclass 16, count 0 2006.285.16:18:05.52#ibcon#about to read 5, iclass 16, count 0 2006.285.16:18:05.52#ibcon#read 5, iclass 16, count 0 2006.285.16:18:05.52#ibcon#about to read 6, iclass 16, count 0 2006.285.16:18:05.52#ibcon#read 6, iclass 16, count 0 2006.285.16:18:05.52#ibcon#end of sib2, iclass 16, count 0 2006.285.16:18:05.52#ibcon#*mode == 0, iclass 16, count 0 2006.285.16:18:05.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.16:18:05.52#ibcon#[27=USB\r\n] 2006.285.16:18:05.52#ibcon#*before write, iclass 16, count 0 2006.285.16:18:05.52#ibcon#enter sib2, iclass 16, count 0 2006.285.16:18:05.52#ibcon#flushed, iclass 16, count 0 2006.285.16:18:05.52#ibcon#about to write, iclass 16, count 0 2006.285.16:18:05.52#ibcon#wrote, iclass 16, count 0 2006.285.16:18:05.52#ibcon#about to read 3, iclass 16, count 0 2006.285.16:18:05.55#ibcon#read 3, iclass 16, count 0 2006.285.16:18:05.55#ibcon#about to read 4, iclass 16, count 0 2006.285.16:18:05.55#ibcon#read 4, iclass 16, count 0 2006.285.16:18:05.55#ibcon#about to read 5, iclass 16, count 0 2006.285.16:18:05.55#ibcon#read 5, iclass 16, count 0 2006.285.16:18:05.55#ibcon#about to read 6, iclass 16, count 0 2006.285.16:18:05.55#ibcon#read 6, iclass 16, count 0 2006.285.16:18:05.55#ibcon#end of sib2, iclass 16, count 0 2006.285.16:18:05.55#ibcon#*after write, iclass 16, count 0 2006.285.16:18:05.55#ibcon#*before return 0, iclass 16, count 0 2006.285.16:18:05.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:18:05.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:18:05.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.16:18:05.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.16:18:05.55$vck44/vblo=7,734.99 2006.285.16:18:05.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.16:18:05.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.16:18:05.55#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:05.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:18:05.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:18:05.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:18:05.55#ibcon#enter wrdev, iclass 18, count 0 2006.285.16:18:05.55#ibcon#first serial, iclass 18, count 0 2006.285.16:18:05.55#ibcon#enter sib2, iclass 18, count 0 2006.285.16:18:05.55#ibcon#flushed, iclass 18, count 0 2006.285.16:18:05.55#ibcon#about to write, iclass 18, count 0 2006.285.16:18:05.55#ibcon#wrote, iclass 18, count 0 2006.285.16:18:05.55#ibcon#about to read 3, iclass 18, count 0 2006.285.16:18:05.57#ibcon#read 3, iclass 18, count 0 2006.285.16:18:05.57#ibcon#about to read 4, iclass 18, count 0 2006.285.16:18:05.57#ibcon#read 4, iclass 18, count 0 2006.285.16:18:05.57#ibcon#about to read 5, iclass 18, count 0 2006.285.16:18:05.57#ibcon#read 5, iclass 18, count 0 2006.285.16:18:05.57#ibcon#about to read 6, iclass 18, count 0 2006.285.16:18:05.57#ibcon#read 6, iclass 18, count 0 2006.285.16:18:05.57#ibcon#end of sib2, iclass 18, count 0 2006.285.16:18:05.57#ibcon#*mode == 0, iclass 18, count 0 2006.285.16:18:05.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.16:18:05.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.16:18:05.57#ibcon#*before write, iclass 18, count 0 2006.285.16:18:05.57#ibcon#enter sib2, iclass 18, count 0 2006.285.16:18:05.57#ibcon#flushed, iclass 18, count 0 2006.285.16:18:05.57#ibcon#about to write, iclass 18, count 0 2006.285.16:18:05.57#ibcon#wrote, iclass 18, count 0 2006.285.16:18:05.57#ibcon#about to read 3, iclass 18, count 0 2006.285.16:18:05.61#ibcon#read 3, iclass 18, count 0 2006.285.16:18:05.61#ibcon#about to read 4, iclass 18, count 0 2006.285.16:18:05.61#ibcon#read 4, iclass 18, count 0 2006.285.16:18:05.61#ibcon#about to read 5, iclass 18, count 0 2006.285.16:18:05.61#ibcon#read 5, iclass 18, count 0 2006.285.16:18:05.61#ibcon#about to read 6, iclass 18, count 0 2006.285.16:18:05.61#ibcon#read 6, iclass 18, count 0 2006.285.16:18:05.61#ibcon#end of sib2, iclass 18, count 0 2006.285.16:18:05.61#ibcon#*after write, iclass 18, count 0 2006.285.16:18:05.61#ibcon#*before return 0, iclass 18, count 0 2006.285.16:18:05.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:18:05.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:18:05.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.16:18:05.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.16:18:05.61$vck44/vb=7,4 2006.285.16:18:05.61#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.16:18:05.61#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.16:18:05.61#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:05.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:18:05.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:18:05.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:18:05.67#ibcon#enter wrdev, iclass 20, count 2 2006.285.16:18:05.67#ibcon#first serial, iclass 20, count 2 2006.285.16:18:05.67#ibcon#enter sib2, iclass 20, count 2 2006.285.16:18:05.67#ibcon#flushed, iclass 20, count 2 2006.285.16:18:05.67#ibcon#about to write, iclass 20, count 2 2006.285.16:18:05.67#ibcon#wrote, iclass 20, count 2 2006.285.16:18:05.67#ibcon#about to read 3, iclass 20, count 2 2006.285.16:18:05.69#ibcon#read 3, iclass 20, count 2 2006.285.16:18:05.69#ibcon#about to read 4, iclass 20, count 2 2006.285.16:18:05.69#ibcon#read 4, iclass 20, count 2 2006.285.16:18:05.69#ibcon#about to read 5, iclass 20, count 2 2006.285.16:18:05.69#ibcon#read 5, iclass 20, count 2 2006.285.16:18:05.69#ibcon#about to read 6, iclass 20, count 2 2006.285.16:18:05.69#ibcon#read 6, iclass 20, count 2 2006.285.16:18:05.69#ibcon#end of sib2, iclass 20, count 2 2006.285.16:18:05.69#ibcon#*mode == 0, iclass 20, count 2 2006.285.16:18:05.69#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.16:18:05.69#ibcon#[27=AT07-04\r\n] 2006.285.16:18:05.69#ibcon#*before write, iclass 20, count 2 2006.285.16:18:05.69#ibcon#enter sib2, iclass 20, count 2 2006.285.16:18:05.69#ibcon#flushed, iclass 20, count 2 2006.285.16:18:05.69#ibcon#about to write, iclass 20, count 2 2006.285.16:18:05.69#ibcon#wrote, iclass 20, count 2 2006.285.16:18:05.69#ibcon#about to read 3, iclass 20, count 2 2006.285.16:18:05.72#ibcon#read 3, iclass 20, count 2 2006.285.16:18:05.72#ibcon#about to read 4, iclass 20, count 2 2006.285.16:18:05.72#ibcon#read 4, iclass 20, count 2 2006.285.16:18:05.72#ibcon#about to read 5, iclass 20, count 2 2006.285.16:18:05.72#ibcon#read 5, iclass 20, count 2 2006.285.16:18:05.72#ibcon#about to read 6, iclass 20, count 2 2006.285.16:18:05.72#ibcon#read 6, iclass 20, count 2 2006.285.16:18:05.72#ibcon#end of sib2, iclass 20, count 2 2006.285.16:18:05.72#ibcon#*after write, iclass 20, count 2 2006.285.16:18:05.72#ibcon#*before return 0, iclass 20, count 2 2006.285.16:18:05.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:18:05.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:18:05.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.16:18:05.72#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:05.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:18:05.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:18:05.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:18:05.84#ibcon#enter wrdev, iclass 20, count 0 2006.285.16:18:05.84#ibcon#first serial, iclass 20, count 0 2006.285.16:18:05.84#ibcon#enter sib2, iclass 20, count 0 2006.285.16:18:05.84#ibcon#flushed, iclass 20, count 0 2006.285.16:18:05.84#ibcon#about to write, iclass 20, count 0 2006.285.16:18:05.84#ibcon#wrote, iclass 20, count 0 2006.285.16:18:05.84#ibcon#about to read 3, iclass 20, count 0 2006.285.16:18:05.86#ibcon#read 3, iclass 20, count 0 2006.285.16:18:05.86#ibcon#about to read 4, iclass 20, count 0 2006.285.16:18:05.86#ibcon#read 4, iclass 20, count 0 2006.285.16:18:05.86#ibcon#about to read 5, iclass 20, count 0 2006.285.16:18:05.86#ibcon#read 5, iclass 20, count 0 2006.285.16:18:05.86#ibcon#about to read 6, iclass 20, count 0 2006.285.16:18:05.86#ibcon#read 6, iclass 20, count 0 2006.285.16:18:05.86#ibcon#end of sib2, iclass 20, count 0 2006.285.16:18:05.86#ibcon#*mode == 0, iclass 20, count 0 2006.285.16:18:05.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.16:18:05.86#ibcon#[27=USB\r\n] 2006.285.16:18:05.86#ibcon#*before write, iclass 20, count 0 2006.285.16:18:05.86#ibcon#enter sib2, iclass 20, count 0 2006.285.16:18:05.86#ibcon#flushed, iclass 20, count 0 2006.285.16:18:05.86#ibcon#about to write, iclass 20, count 0 2006.285.16:18:05.86#ibcon#wrote, iclass 20, count 0 2006.285.16:18:05.86#ibcon#about to read 3, iclass 20, count 0 2006.285.16:18:05.89#ibcon#read 3, iclass 20, count 0 2006.285.16:18:05.89#ibcon#about to read 4, iclass 20, count 0 2006.285.16:18:05.89#ibcon#read 4, iclass 20, count 0 2006.285.16:18:05.89#ibcon#about to read 5, iclass 20, count 0 2006.285.16:18:05.89#ibcon#read 5, iclass 20, count 0 2006.285.16:18:05.89#ibcon#about to read 6, iclass 20, count 0 2006.285.16:18:05.89#ibcon#read 6, iclass 20, count 0 2006.285.16:18:05.89#ibcon#end of sib2, iclass 20, count 0 2006.285.16:18:05.89#ibcon#*after write, iclass 20, count 0 2006.285.16:18:05.89#ibcon#*before return 0, iclass 20, count 0 2006.285.16:18:05.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:18:05.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:18:05.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.16:18:05.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.16:18:05.89$vck44/vblo=8,744.99 2006.285.16:18:05.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.16:18:05.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.16:18:05.89#ibcon#ireg 17 cls_cnt 0 2006.285.16:18:05.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:18:05.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:18:05.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:18:05.89#ibcon#enter wrdev, iclass 22, count 0 2006.285.16:18:05.89#ibcon#first serial, iclass 22, count 0 2006.285.16:18:05.89#ibcon#enter sib2, iclass 22, count 0 2006.285.16:18:05.89#ibcon#flushed, iclass 22, count 0 2006.285.16:18:05.89#ibcon#about to write, iclass 22, count 0 2006.285.16:18:05.89#ibcon#wrote, iclass 22, count 0 2006.285.16:18:05.89#ibcon#about to read 3, iclass 22, count 0 2006.285.16:18:05.91#ibcon#read 3, iclass 22, count 0 2006.285.16:18:05.91#ibcon#about to read 4, iclass 22, count 0 2006.285.16:18:05.91#ibcon#read 4, iclass 22, count 0 2006.285.16:18:05.91#ibcon#about to read 5, iclass 22, count 0 2006.285.16:18:05.91#ibcon#read 5, iclass 22, count 0 2006.285.16:18:05.91#ibcon#about to read 6, iclass 22, count 0 2006.285.16:18:05.91#ibcon#read 6, iclass 22, count 0 2006.285.16:18:05.91#ibcon#end of sib2, iclass 22, count 0 2006.285.16:18:05.91#ibcon#*mode == 0, iclass 22, count 0 2006.285.16:18:05.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.16:18:05.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.16:18:05.91#ibcon#*before write, iclass 22, count 0 2006.285.16:18:05.91#ibcon#enter sib2, iclass 22, count 0 2006.285.16:18:05.91#ibcon#flushed, iclass 22, count 0 2006.285.16:18:05.91#ibcon#about to write, iclass 22, count 0 2006.285.16:18:05.91#ibcon#wrote, iclass 22, count 0 2006.285.16:18:05.91#ibcon#about to read 3, iclass 22, count 0 2006.285.16:18:05.95#ibcon#read 3, iclass 22, count 0 2006.285.16:18:05.95#ibcon#about to read 4, iclass 22, count 0 2006.285.16:18:05.95#ibcon#read 4, iclass 22, count 0 2006.285.16:18:05.95#ibcon#about to read 5, iclass 22, count 0 2006.285.16:18:05.95#ibcon#read 5, iclass 22, count 0 2006.285.16:18:05.95#ibcon#about to read 6, iclass 22, count 0 2006.285.16:18:05.95#ibcon#read 6, iclass 22, count 0 2006.285.16:18:05.95#ibcon#end of sib2, iclass 22, count 0 2006.285.16:18:05.95#ibcon#*after write, iclass 22, count 0 2006.285.16:18:05.95#ibcon#*before return 0, iclass 22, count 0 2006.285.16:18:05.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:18:05.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:18:05.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.16:18:05.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.16:18:05.95$vck44/vb=8,4 2006.285.16:18:05.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.16:18:05.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.16:18:05.95#ibcon#ireg 11 cls_cnt 2 2006.285.16:18:05.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:18:06.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:18:06.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:18:06.01#ibcon#enter wrdev, iclass 24, count 2 2006.285.16:18:06.01#ibcon#first serial, iclass 24, count 2 2006.285.16:18:06.01#ibcon#enter sib2, iclass 24, count 2 2006.285.16:18:06.01#ibcon#flushed, iclass 24, count 2 2006.285.16:18:06.01#ibcon#about to write, iclass 24, count 2 2006.285.16:18:06.01#ibcon#wrote, iclass 24, count 2 2006.285.16:18:06.01#ibcon#about to read 3, iclass 24, count 2 2006.285.16:18:06.03#ibcon#read 3, iclass 24, count 2 2006.285.16:18:06.03#ibcon#about to read 4, iclass 24, count 2 2006.285.16:18:06.03#ibcon#read 4, iclass 24, count 2 2006.285.16:18:06.03#ibcon#about to read 5, iclass 24, count 2 2006.285.16:18:06.03#ibcon#read 5, iclass 24, count 2 2006.285.16:18:06.03#ibcon#about to read 6, iclass 24, count 2 2006.285.16:18:06.03#ibcon#read 6, iclass 24, count 2 2006.285.16:18:06.03#ibcon#end of sib2, iclass 24, count 2 2006.285.16:18:06.03#ibcon#*mode == 0, iclass 24, count 2 2006.285.16:18:06.03#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.16:18:06.03#ibcon#[27=AT08-04\r\n] 2006.285.16:18:06.03#ibcon#*before write, iclass 24, count 2 2006.285.16:18:06.03#ibcon#enter sib2, iclass 24, count 2 2006.285.16:18:06.03#ibcon#flushed, iclass 24, count 2 2006.285.16:18:06.03#ibcon#about to write, iclass 24, count 2 2006.285.16:18:06.03#ibcon#wrote, iclass 24, count 2 2006.285.16:18:06.03#ibcon#about to read 3, iclass 24, count 2 2006.285.16:18:06.06#ibcon#read 3, iclass 24, count 2 2006.285.16:18:06.06#ibcon#about to read 4, iclass 24, count 2 2006.285.16:18:06.06#ibcon#read 4, iclass 24, count 2 2006.285.16:18:06.06#ibcon#about to read 5, iclass 24, count 2 2006.285.16:18:06.06#ibcon#read 5, iclass 24, count 2 2006.285.16:18:06.06#ibcon#about to read 6, iclass 24, count 2 2006.285.16:18:06.06#ibcon#read 6, iclass 24, count 2 2006.285.16:18:06.06#ibcon#end of sib2, iclass 24, count 2 2006.285.16:18:06.06#ibcon#*after write, iclass 24, count 2 2006.285.16:18:06.06#ibcon#*before return 0, iclass 24, count 2 2006.285.16:18:06.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:18:06.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:18:06.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.16:18:06.06#ibcon#ireg 7 cls_cnt 0 2006.285.16:18:06.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:18:06.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:18:06.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:18:06.18#ibcon#enter wrdev, iclass 24, count 0 2006.285.16:18:06.18#ibcon#first serial, iclass 24, count 0 2006.285.16:18:06.18#ibcon#enter sib2, iclass 24, count 0 2006.285.16:18:06.18#ibcon#flushed, iclass 24, count 0 2006.285.16:18:06.18#ibcon#about to write, iclass 24, count 0 2006.285.16:18:06.18#ibcon#wrote, iclass 24, count 0 2006.285.16:18:06.18#ibcon#about to read 3, iclass 24, count 0 2006.285.16:18:06.20#ibcon#read 3, iclass 24, count 0 2006.285.16:18:06.20#ibcon#about to read 4, iclass 24, count 0 2006.285.16:18:06.20#ibcon#read 4, iclass 24, count 0 2006.285.16:18:06.20#ibcon#about to read 5, iclass 24, count 0 2006.285.16:18:06.20#ibcon#read 5, iclass 24, count 0 2006.285.16:18:06.20#ibcon#about to read 6, iclass 24, count 0 2006.285.16:18:06.20#ibcon#read 6, iclass 24, count 0 2006.285.16:18:06.20#ibcon#end of sib2, iclass 24, count 0 2006.285.16:18:06.20#ibcon#*mode == 0, iclass 24, count 0 2006.285.16:18:06.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.16:18:06.20#ibcon#[27=USB\r\n] 2006.285.16:18:06.20#ibcon#*before write, iclass 24, count 0 2006.285.16:18:06.20#ibcon#enter sib2, iclass 24, count 0 2006.285.16:18:06.20#ibcon#flushed, iclass 24, count 0 2006.285.16:18:06.20#ibcon#about to write, iclass 24, count 0 2006.285.16:18:06.20#ibcon#wrote, iclass 24, count 0 2006.285.16:18:06.20#ibcon#about to read 3, iclass 24, count 0 2006.285.16:18:06.23#ibcon#read 3, iclass 24, count 0 2006.285.16:18:06.23#ibcon#about to read 4, iclass 24, count 0 2006.285.16:18:06.23#ibcon#read 4, iclass 24, count 0 2006.285.16:18:06.23#ibcon#about to read 5, iclass 24, count 0 2006.285.16:18:06.23#ibcon#read 5, iclass 24, count 0 2006.285.16:18:06.23#ibcon#about to read 6, iclass 24, count 0 2006.285.16:18:06.23#ibcon#read 6, iclass 24, count 0 2006.285.16:18:06.23#ibcon#end of sib2, iclass 24, count 0 2006.285.16:18:06.23#ibcon#*after write, iclass 24, count 0 2006.285.16:18:06.23#ibcon#*before return 0, iclass 24, count 0 2006.285.16:18:06.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:18:06.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:18:06.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.16:18:06.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.16:18:06.23$vck44/vabw=wide 2006.285.16:18:06.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.16:18:06.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.16:18:06.23#ibcon#ireg 8 cls_cnt 0 2006.285.16:18:06.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:18:06.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:18:06.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:18:06.23#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:18:06.23#ibcon#first serial, iclass 27, count 0 2006.285.16:18:06.23#ibcon#enter sib2, iclass 27, count 0 2006.285.16:18:06.23#ibcon#flushed, iclass 27, count 0 2006.285.16:18:06.23#ibcon#about to write, iclass 27, count 0 2006.285.16:18:06.23#ibcon#wrote, iclass 27, count 0 2006.285.16:18:06.23#ibcon#about to read 3, iclass 27, count 0 2006.285.16:18:06.25#ibcon#read 3, iclass 27, count 0 2006.285.16:18:06.25#ibcon#about to read 4, iclass 27, count 0 2006.285.16:18:06.25#ibcon#read 4, iclass 27, count 0 2006.285.16:18:06.25#ibcon#about to read 5, iclass 27, count 0 2006.285.16:18:06.25#ibcon#read 5, iclass 27, count 0 2006.285.16:18:06.25#ibcon#about to read 6, iclass 27, count 0 2006.285.16:18:06.25#ibcon#read 6, iclass 27, count 0 2006.285.16:18:06.25#ibcon#end of sib2, iclass 27, count 0 2006.285.16:18:06.25#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:18:06.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:18:06.25#ibcon#[25=BW32\r\n] 2006.285.16:18:06.25#ibcon#*before write, iclass 27, count 0 2006.285.16:18:06.25#ibcon#enter sib2, iclass 27, count 0 2006.285.16:18:06.25#ibcon#flushed, iclass 27, count 0 2006.285.16:18:06.25#ibcon#about to write, iclass 27, count 0 2006.285.16:18:06.25#ibcon#wrote, iclass 27, count 0 2006.285.16:18:06.25#ibcon#about to read 3, iclass 27, count 0 2006.285.16:18:06.27#abcon#<5=/01 1.1 3.5 18.67 901014.9\r\n> 2006.285.16:18:06.28#ibcon#read 3, iclass 27, count 0 2006.285.16:18:06.28#ibcon#about to read 4, iclass 27, count 0 2006.285.16:18:06.28#ibcon#read 4, iclass 27, count 0 2006.285.16:18:06.28#ibcon#about to read 5, iclass 27, count 0 2006.285.16:18:06.28#ibcon#read 5, iclass 27, count 0 2006.285.16:18:06.28#ibcon#about to read 6, iclass 27, count 0 2006.285.16:18:06.28#ibcon#read 6, iclass 27, count 0 2006.285.16:18:06.28#ibcon#end of sib2, iclass 27, count 0 2006.285.16:18:06.28#ibcon#*after write, iclass 27, count 0 2006.285.16:18:06.28#ibcon#*before return 0, iclass 27, count 0 2006.285.16:18:06.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:18:06.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:18:06.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:18:06.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:18:06.28$vck44/vbbw=wide 2006.285.16:18:06.28#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.16:18:06.28#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.16:18:06.28#ibcon#ireg 8 cls_cnt 0 2006.285.16:18:06.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:18:06.29#abcon#{5=INTERFACE CLEAR} 2006.285.16:18:06.35#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:18:06.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:18:06.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:18:06.35#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:18:06.35#ibcon#first serial, iclass 31, count 0 2006.285.16:18:06.35#ibcon#enter sib2, iclass 31, count 0 2006.285.16:18:06.35#ibcon#flushed, iclass 31, count 0 2006.285.16:18:06.35#ibcon#about to write, iclass 31, count 0 2006.285.16:18:06.35#ibcon#wrote, iclass 31, count 0 2006.285.16:18:06.35#ibcon#about to read 3, iclass 31, count 0 2006.285.16:18:06.37#ibcon#read 3, iclass 31, count 0 2006.285.16:18:06.37#ibcon#about to read 4, iclass 31, count 0 2006.285.16:18:06.37#ibcon#read 4, iclass 31, count 0 2006.285.16:18:06.37#ibcon#about to read 5, iclass 31, count 0 2006.285.16:18:06.37#ibcon#read 5, iclass 31, count 0 2006.285.16:18:06.37#ibcon#about to read 6, iclass 31, count 0 2006.285.16:18:06.37#ibcon#read 6, iclass 31, count 0 2006.285.16:18:06.37#ibcon#end of sib2, iclass 31, count 0 2006.285.16:18:06.37#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:18:06.37#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:18:06.37#ibcon#[27=BW32\r\n] 2006.285.16:18:06.37#ibcon#*before write, iclass 31, count 0 2006.285.16:18:06.37#ibcon#enter sib2, iclass 31, count 0 2006.285.16:18:06.37#ibcon#flushed, iclass 31, count 0 2006.285.16:18:06.37#ibcon#about to write, iclass 31, count 0 2006.285.16:18:06.37#ibcon#wrote, iclass 31, count 0 2006.285.16:18:06.37#ibcon#about to read 3, iclass 31, count 0 2006.285.16:18:06.40#ibcon#read 3, iclass 31, count 0 2006.285.16:18:06.40#ibcon#about to read 4, iclass 31, count 0 2006.285.16:18:06.40#ibcon#read 4, iclass 31, count 0 2006.285.16:18:06.40#ibcon#about to read 5, iclass 31, count 0 2006.285.16:18:06.40#ibcon#read 5, iclass 31, count 0 2006.285.16:18:06.40#ibcon#about to read 6, iclass 31, count 0 2006.285.16:18:06.40#ibcon#read 6, iclass 31, count 0 2006.285.16:18:06.40#ibcon#end of sib2, iclass 31, count 0 2006.285.16:18:06.40#ibcon#*after write, iclass 31, count 0 2006.285.16:18:06.40#ibcon#*before return 0, iclass 31, count 0 2006.285.16:18:06.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:18:06.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:18:06.40#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:18:06.40#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:18:06.40$setupk4/ifdk4 2006.285.16:18:06.40$ifdk4/lo= 2006.285.16:18:06.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.16:18:06.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.16:18:06.40$ifdk4/patch= 2006.285.16:18:06.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.16:18:06.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.16:18:06.40$setupk4/!*+20s 2006.285.16:18:16.44#abcon#<5=/01 1.1 3.5 18.66 901014.9\r\n> 2006.285.16:18:16.46#abcon#{5=INTERFACE CLEAR} 2006.285.16:18:16.52#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:18:20.43$setupk4/"tpicd 2006.285.16:18:20.43$setupk4/echo=off 2006.285.16:18:20.43$setupk4/xlog=off 2006.285.16:18:20.43:!2006.285.16:23:11 2006.285.16:18:23.13#trakl#Source acquired 2006.285.16:18:25.13#flagr#flagr/antenna,acquired 2006.285.16:23:11.00:preob 2006.285.16:23:11.14/onsource/TRACKING 2006.285.16:23:11.14:!2006.285.16:23:21 2006.285.16:23:21.00:"tape 2006.285.16:23:21.00:"st=record 2006.285.16:23:21.00:data_valid=on 2006.285.16:23:21.00:midob 2006.285.16:23:22.14/onsource/TRACKING 2006.285.16:23:22.14/wx/18.60,1015.0,90 2006.285.16:23:22.31/cable/+6.5006E-03 2006.285.16:23:23.40/va/01,07,usb,yes,36,39 2006.285.16:23:23.40/va/02,06,usb,yes,36,37 2006.285.16:23:23.40/va/03,07,usb,yes,36,38 2006.285.16:23:23.40/va/04,06,usb,yes,37,39 2006.285.16:23:23.40/va/05,03,usb,yes,37,37 2006.285.16:23:23.40/va/06,04,usb,yes,33,33 2006.285.16:23:23.40/va/07,04,usb,yes,34,35 2006.285.16:23:23.40/va/08,03,usb,yes,35,42 2006.285.16:23:23.63/valo/01,524.99,yes,locked 2006.285.16:23:23.63/valo/02,534.99,yes,locked 2006.285.16:23:23.63/valo/03,564.99,yes,locked 2006.285.16:23:23.63/valo/04,624.99,yes,locked 2006.285.16:23:23.63/valo/05,734.99,yes,locked 2006.285.16:23:23.63/valo/06,814.99,yes,locked 2006.285.16:23:23.63/valo/07,864.99,yes,locked 2006.285.16:23:23.63/valo/08,884.99,yes,locked 2006.285.16:23:24.72/vb/01,04,usb,yes,33,30 2006.285.16:23:24.72/vb/02,05,usb,yes,31,31 2006.285.16:23:24.72/vb/03,04,usb,yes,32,35 2006.285.16:23:24.72/vb/04,05,usb,yes,32,31 2006.285.16:23:24.72/vb/05,04,usb,yes,28,31 2006.285.16:23:24.72/vb/06,03,usb,yes,41,36 2006.285.16:23:24.72/vb/07,04,usb,yes,33,33 2006.285.16:23:24.72/vb/08,04,usb,yes,30,34 2006.285.16:23:24.96/vblo/01,629.99,yes,locked 2006.285.16:23:24.96/vblo/02,634.99,yes,locked 2006.285.16:23:24.96/vblo/03,649.99,yes,locked 2006.285.16:23:24.96/vblo/04,679.99,yes,locked 2006.285.16:23:24.96/vblo/05,709.99,yes,locked 2006.285.16:23:24.96/vblo/06,719.99,yes,locked 2006.285.16:23:24.96/vblo/07,734.99,yes,locked 2006.285.16:23:24.96/vblo/08,744.99,yes,locked 2006.285.16:23:25.11/vabw/8 2006.285.16:23:25.26/vbbw/8 2006.285.16:23:25.35/xfe/off,on,12.2 2006.285.16:23:25.72/ifatt/23,28,28,28 2006.285.16:23:26.08/fmout-gps/S +2.73E-07 2006.285.16:23:26.11:!2006.285.16:24:01 2006.285.16:24:01.00:data_valid=off 2006.285.16:24:01.00:"et 2006.285.16:24:01.00:!+3s 2006.285.16:24:04.01:"tape 2006.285.16:24:04.01:postob 2006.285.16:24:04.08/cable/+6.5001E-03 2006.285.16:24:04.08/wx/18.60,1014.9,91 2006.285.16:24:05.08/fmout-gps/S +2.71E-07 2006.285.16:24:05.08:scan_name=285-1630,jd0610,40 2006.285.16:24:05.08:source=3c446,222547.26,-045701.4,2000.0,cw 2006.285.16:24:06.14#flagr#flagr/antenna,new-source 2006.285.16:24:06.14:checkk5 2006.285.16:24:06.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.16:24:06.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.16:24:07.31/chk_autoobs//k5ts3/ autoobs is running! 2006.285.16:24:07.80/chk_autoobs//k5ts4/ autoobs is running! 2006.285.16:24:08.44/chk_obsdata//k5ts1/T2851623??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.16:24:08.85/chk_obsdata//k5ts2/T2851623??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.16:24:09.21/chk_obsdata//k5ts3/T2851623??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.16:24:09.60/chk_obsdata//k5ts4/T2851623??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.16:24:10.44/k5log//k5ts1_log_newline 2006.285.16:24:11.22/k5log//k5ts2_log_newline 2006.285.16:24:11.97/k5log//k5ts3_log_newline 2006.285.16:24:13.00/k5log//k5ts4_log_newline 2006.285.16:24:13.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.16:24:13.02:setupk4=1 2006.285.16:24:13.02$setupk4/echo=on 2006.285.16:24:13.02$setupk4/pcalon 2006.285.16:24:13.02$pcalon/"no phase cal control is implemented here 2006.285.16:24:13.02$setupk4/"tpicd=stop 2006.285.16:24:13.02$setupk4/"rec=synch_on 2006.285.16:24:13.02$setupk4/"rec_mode=128 2006.285.16:24:13.02$setupk4/!* 2006.285.16:24:13.02$setupk4/recpk4 2006.285.16:24:13.02$recpk4/recpatch= 2006.285.16:24:13.02$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.16:24:13.03$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.16:24:13.03$setupk4/vck44 2006.285.16:24:13.03$vck44/valo=1,524.99 2006.285.16:24:13.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.16:24:13.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.16:24:13.03#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:13.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:24:13.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:24:13.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:24:13.03#ibcon#enter wrdev, iclass 37, count 0 2006.285.16:24:13.03#ibcon#first serial, iclass 37, count 0 2006.285.16:24:13.03#ibcon#enter sib2, iclass 37, count 0 2006.285.16:24:13.03#ibcon#flushed, iclass 37, count 0 2006.285.16:24:13.03#ibcon#about to write, iclass 37, count 0 2006.285.16:24:13.03#ibcon#wrote, iclass 37, count 0 2006.285.16:24:13.03#ibcon#about to read 3, iclass 37, count 0 2006.285.16:24:13.05#ibcon#read 3, iclass 37, count 0 2006.285.16:24:13.05#ibcon#about to read 4, iclass 37, count 0 2006.285.16:24:13.05#ibcon#read 4, iclass 37, count 0 2006.285.16:24:13.05#ibcon#about to read 5, iclass 37, count 0 2006.285.16:24:13.05#ibcon#read 5, iclass 37, count 0 2006.285.16:24:13.05#ibcon#about to read 6, iclass 37, count 0 2006.285.16:24:13.05#ibcon#read 6, iclass 37, count 0 2006.285.16:24:13.05#ibcon#end of sib2, iclass 37, count 0 2006.285.16:24:13.05#ibcon#*mode == 0, iclass 37, count 0 2006.285.16:24:13.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.16:24:13.05#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.16:24:13.05#ibcon#*before write, iclass 37, count 0 2006.285.16:24:13.05#ibcon#enter sib2, iclass 37, count 0 2006.285.16:24:13.05#ibcon#flushed, iclass 37, count 0 2006.285.16:24:13.05#ibcon#about to write, iclass 37, count 0 2006.285.16:24:13.05#ibcon#wrote, iclass 37, count 0 2006.285.16:24:13.05#ibcon#about to read 3, iclass 37, count 0 2006.285.16:24:13.10#ibcon#read 3, iclass 37, count 0 2006.285.16:24:13.10#ibcon#about to read 4, iclass 37, count 0 2006.285.16:24:13.10#ibcon#read 4, iclass 37, count 0 2006.285.16:24:13.10#ibcon#about to read 5, iclass 37, count 0 2006.285.16:24:13.10#ibcon#read 5, iclass 37, count 0 2006.285.16:24:13.10#ibcon#about to read 6, iclass 37, count 0 2006.285.16:24:13.10#ibcon#read 6, iclass 37, count 0 2006.285.16:24:13.10#ibcon#end of sib2, iclass 37, count 0 2006.285.16:24:13.10#ibcon#*after write, iclass 37, count 0 2006.285.16:24:13.10#ibcon#*before return 0, iclass 37, count 0 2006.285.16:24:13.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:24:13.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:24:13.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.16:24:13.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.16:24:13.10$vck44/va=1,7 2006.285.16:24:13.10#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.16:24:13.10#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.16:24:13.10#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:13.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:24:13.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:24:13.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:24:13.10#ibcon#enter wrdev, iclass 39, count 2 2006.285.16:24:13.10#ibcon#first serial, iclass 39, count 2 2006.285.16:24:13.10#ibcon#enter sib2, iclass 39, count 2 2006.285.16:24:13.10#ibcon#flushed, iclass 39, count 2 2006.285.16:24:13.10#ibcon#about to write, iclass 39, count 2 2006.285.16:24:13.10#ibcon#wrote, iclass 39, count 2 2006.285.16:24:13.10#ibcon#about to read 3, iclass 39, count 2 2006.285.16:24:13.12#ibcon#read 3, iclass 39, count 2 2006.285.16:24:13.12#ibcon#about to read 4, iclass 39, count 2 2006.285.16:24:13.12#ibcon#read 4, iclass 39, count 2 2006.285.16:24:13.12#ibcon#about to read 5, iclass 39, count 2 2006.285.16:24:13.12#ibcon#read 5, iclass 39, count 2 2006.285.16:24:13.12#ibcon#about to read 6, iclass 39, count 2 2006.285.16:24:13.12#ibcon#read 6, iclass 39, count 2 2006.285.16:24:13.12#ibcon#end of sib2, iclass 39, count 2 2006.285.16:24:13.12#ibcon#*mode == 0, iclass 39, count 2 2006.285.16:24:13.12#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.16:24:13.12#ibcon#[25=AT01-07\r\n] 2006.285.16:24:13.12#ibcon#*before write, iclass 39, count 2 2006.285.16:24:13.12#ibcon#enter sib2, iclass 39, count 2 2006.285.16:24:13.12#ibcon#flushed, iclass 39, count 2 2006.285.16:24:13.12#ibcon#about to write, iclass 39, count 2 2006.285.16:24:13.12#ibcon#wrote, iclass 39, count 2 2006.285.16:24:13.12#ibcon#about to read 3, iclass 39, count 2 2006.285.16:24:13.15#ibcon#read 3, iclass 39, count 2 2006.285.16:24:13.15#ibcon#about to read 4, iclass 39, count 2 2006.285.16:24:13.15#ibcon#read 4, iclass 39, count 2 2006.285.16:24:13.15#ibcon#about to read 5, iclass 39, count 2 2006.285.16:24:13.15#ibcon#read 5, iclass 39, count 2 2006.285.16:24:13.15#ibcon#about to read 6, iclass 39, count 2 2006.285.16:24:13.15#ibcon#read 6, iclass 39, count 2 2006.285.16:24:13.15#ibcon#end of sib2, iclass 39, count 2 2006.285.16:24:13.15#ibcon#*after write, iclass 39, count 2 2006.285.16:24:13.15#ibcon#*before return 0, iclass 39, count 2 2006.285.16:24:13.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:24:13.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:24:13.15#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.16:24:13.15#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:13.15#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:24:13.27#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:24:13.27#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:24:13.27#ibcon#enter wrdev, iclass 39, count 0 2006.285.16:24:13.27#ibcon#first serial, iclass 39, count 0 2006.285.16:24:13.27#ibcon#enter sib2, iclass 39, count 0 2006.285.16:24:13.27#ibcon#flushed, iclass 39, count 0 2006.285.16:24:13.27#ibcon#about to write, iclass 39, count 0 2006.285.16:24:13.27#ibcon#wrote, iclass 39, count 0 2006.285.16:24:13.27#ibcon#about to read 3, iclass 39, count 0 2006.285.16:24:13.29#ibcon#read 3, iclass 39, count 0 2006.285.16:24:13.29#ibcon#about to read 4, iclass 39, count 0 2006.285.16:24:13.29#ibcon#read 4, iclass 39, count 0 2006.285.16:24:13.29#ibcon#about to read 5, iclass 39, count 0 2006.285.16:24:13.29#ibcon#read 5, iclass 39, count 0 2006.285.16:24:13.29#ibcon#about to read 6, iclass 39, count 0 2006.285.16:24:13.29#ibcon#read 6, iclass 39, count 0 2006.285.16:24:13.29#ibcon#end of sib2, iclass 39, count 0 2006.285.16:24:13.29#ibcon#*mode == 0, iclass 39, count 0 2006.285.16:24:13.29#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.16:24:13.29#ibcon#[25=USB\r\n] 2006.285.16:24:13.29#ibcon#*before write, iclass 39, count 0 2006.285.16:24:13.29#ibcon#enter sib2, iclass 39, count 0 2006.285.16:24:13.29#ibcon#flushed, iclass 39, count 0 2006.285.16:24:13.29#ibcon#about to write, iclass 39, count 0 2006.285.16:24:13.29#ibcon#wrote, iclass 39, count 0 2006.285.16:24:13.29#ibcon#about to read 3, iclass 39, count 0 2006.285.16:24:13.32#ibcon#read 3, iclass 39, count 0 2006.285.16:24:13.32#ibcon#about to read 4, iclass 39, count 0 2006.285.16:24:13.32#ibcon#read 4, iclass 39, count 0 2006.285.16:24:13.32#ibcon#about to read 5, iclass 39, count 0 2006.285.16:24:13.32#ibcon#read 5, iclass 39, count 0 2006.285.16:24:13.32#ibcon#about to read 6, iclass 39, count 0 2006.285.16:24:13.32#ibcon#read 6, iclass 39, count 0 2006.285.16:24:13.32#ibcon#end of sib2, iclass 39, count 0 2006.285.16:24:13.32#ibcon#*after write, iclass 39, count 0 2006.285.16:24:13.32#ibcon#*before return 0, iclass 39, count 0 2006.285.16:24:13.32#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:24:13.32#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:24:13.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.16:24:13.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.16:24:13.32$vck44/valo=2,534.99 2006.285.16:24:13.32#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.16:24:13.32#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.16:24:13.32#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:13.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:24:13.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:24:13.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:24:13.32#ibcon#enter wrdev, iclass 3, count 0 2006.285.16:24:13.32#ibcon#first serial, iclass 3, count 0 2006.285.16:24:13.32#ibcon#enter sib2, iclass 3, count 0 2006.285.16:24:13.32#ibcon#flushed, iclass 3, count 0 2006.285.16:24:13.32#ibcon#about to write, iclass 3, count 0 2006.285.16:24:13.32#ibcon#wrote, iclass 3, count 0 2006.285.16:24:13.32#ibcon#about to read 3, iclass 3, count 0 2006.285.16:24:13.34#ibcon#read 3, iclass 3, count 0 2006.285.16:24:13.34#ibcon#about to read 4, iclass 3, count 0 2006.285.16:24:13.34#ibcon#read 4, iclass 3, count 0 2006.285.16:24:13.34#ibcon#about to read 5, iclass 3, count 0 2006.285.16:24:13.34#ibcon#read 5, iclass 3, count 0 2006.285.16:24:13.34#ibcon#about to read 6, iclass 3, count 0 2006.285.16:24:13.34#ibcon#read 6, iclass 3, count 0 2006.285.16:24:13.34#ibcon#end of sib2, iclass 3, count 0 2006.285.16:24:13.34#ibcon#*mode == 0, iclass 3, count 0 2006.285.16:24:13.34#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.16:24:13.34#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.16:24:13.34#ibcon#*before write, iclass 3, count 0 2006.285.16:24:13.34#ibcon#enter sib2, iclass 3, count 0 2006.285.16:24:13.34#ibcon#flushed, iclass 3, count 0 2006.285.16:24:13.34#ibcon#about to write, iclass 3, count 0 2006.285.16:24:13.34#ibcon#wrote, iclass 3, count 0 2006.285.16:24:13.34#ibcon#about to read 3, iclass 3, count 0 2006.285.16:24:13.38#ibcon#read 3, iclass 3, count 0 2006.285.16:24:13.38#ibcon#about to read 4, iclass 3, count 0 2006.285.16:24:13.38#ibcon#read 4, iclass 3, count 0 2006.285.16:24:13.38#ibcon#about to read 5, iclass 3, count 0 2006.285.16:24:13.38#ibcon#read 5, iclass 3, count 0 2006.285.16:24:13.38#ibcon#about to read 6, iclass 3, count 0 2006.285.16:24:13.38#ibcon#read 6, iclass 3, count 0 2006.285.16:24:13.38#ibcon#end of sib2, iclass 3, count 0 2006.285.16:24:13.38#ibcon#*after write, iclass 3, count 0 2006.285.16:24:13.38#ibcon#*before return 0, iclass 3, count 0 2006.285.16:24:13.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:24:13.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:24:13.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.16:24:13.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.16:24:13.38$vck44/va=2,6 2006.285.16:24:13.38#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.16:24:13.38#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.16:24:13.38#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:13.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:24:13.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:24:13.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:24:13.44#ibcon#enter wrdev, iclass 5, count 2 2006.285.16:24:13.44#ibcon#first serial, iclass 5, count 2 2006.285.16:24:13.44#ibcon#enter sib2, iclass 5, count 2 2006.285.16:24:13.44#ibcon#flushed, iclass 5, count 2 2006.285.16:24:13.44#ibcon#about to write, iclass 5, count 2 2006.285.16:24:13.44#ibcon#wrote, iclass 5, count 2 2006.285.16:24:13.44#ibcon#about to read 3, iclass 5, count 2 2006.285.16:24:13.46#ibcon#read 3, iclass 5, count 2 2006.285.16:24:13.46#ibcon#about to read 4, iclass 5, count 2 2006.285.16:24:13.46#ibcon#read 4, iclass 5, count 2 2006.285.16:24:13.46#ibcon#about to read 5, iclass 5, count 2 2006.285.16:24:13.46#ibcon#read 5, iclass 5, count 2 2006.285.16:24:13.46#ibcon#about to read 6, iclass 5, count 2 2006.285.16:24:13.46#ibcon#read 6, iclass 5, count 2 2006.285.16:24:13.46#ibcon#end of sib2, iclass 5, count 2 2006.285.16:24:13.46#ibcon#*mode == 0, iclass 5, count 2 2006.285.16:24:13.46#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.16:24:13.46#ibcon#[25=AT02-06\r\n] 2006.285.16:24:13.46#ibcon#*before write, iclass 5, count 2 2006.285.16:24:13.46#ibcon#enter sib2, iclass 5, count 2 2006.285.16:24:13.46#ibcon#flushed, iclass 5, count 2 2006.285.16:24:13.46#ibcon#about to write, iclass 5, count 2 2006.285.16:24:13.46#ibcon#wrote, iclass 5, count 2 2006.285.16:24:13.46#ibcon#about to read 3, iclass 5, count 2 2006.285.16:24:13.49#ibcon#read 3, iclass 5, count 2 2006.285.16:24:13.49#ibcon#about to read 4, iclass 5, count 2 2006.285.16:24:13.49#ibcon#read 4, iclass 5, count 2 2006.285.16:24:13.49#ibcon#about to read 5, iclass 5, count 2 2006.285.16:24:13.49#ibcon#read 5, iclass 5, count 2 2006.285.16:24:13.49#ibcon#about to read 6, iclass 5, count 2 2006.285.16:24:13.49#ibcon#read 6, iclass 5, count 2 2006.285.16:24:13.49#ibcon#end of sib2, iclass 5, count 2 2006.285.16:24:13.49#ibcon#*after write, iclass 5, count 2 2006.285.16:24:13.49#ibcon#*before return 0, iclass 5, count 2 2006.285.16:24:13.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:24:13.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:24:13.49#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.16:24:13.49#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:13.49#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:24:13.61#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:24:13.61#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:24:13.61#ibcon#enter wrdev, iclass 5, count 0 2006.285.16:24:13.61#ibcon#first serial, iclass 5, count 0 2006.285.16:24:13.61#ibcon#enter sib2, iclass 5, count 0 2006.285.16:24:13.61#ibcon#flushed, iclass 5, count 0 2006.285.16:24:13.61#ibcon#about to write, iclass 5, count 0 2006.285.16:24:13.61#ibcon#wrote, iclass 5, count 0 2006.285.16:24:13.61#ibcon#about to read 3, iclass 5, count 0 2006.285.16:24:13.63#ibcon#read 3, iclass 5, count 0 2006.285.16:24:13.63#ibcon#about to read 4, iclass 5, count 0 2006.285.16:24:13.63#ibcon#read 4, iclass 5, count 0 2006.285.16:24:13.63#ibcon#about to read 5, iclass 5, count 0 2006.285.16:24:13.63#ibcon#read 5, iclass 5, count 0 2006.285.16:24:13.63#ibcon#about to read 6, iclass 5, count 0 2006.285.16:24:13.63#ibcon#read 6, iclass 5, count 0 2006.285.16:24:13.63#ibcon#end of sib2, iclass 5, count 0 2006.285.16:24:13.63#ibcon#*mode == 0, iclass 5, count 0 2006.285.16:24:13.63#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.16:24:13.63#ibcon#[25=USB\r\n] 2006.285.16:24:13.63#ibcon#*before write, iclass 5, count 0 2006.285.16:24:13.63#ibcon#enter sib2, iclass 5, count 0 2006.285.16:24:13.63#ibcon#flushed, iclass 5, count 0 2006.285.16:24:13.63#ibcon#about to write, iclass 5, count 0 2006.285.16:24:13.63#ibcon#wrote, iclass 5, count 0 2006.285.16:24:13.63#ibcon#about to read 3, iclass 5, count 0 2006.285.16:24:13.66#ibcon#read 3, iclass 5, count 0 2006.285.16:24:13.66#ibcon#about to read 4, iclass 5, count 0 2006.285.16:24:13.66#ibcon#read 4, iclass 5, count 0 2006.285.16:24:13.66#ibcon#about to read 5, iclass 5, count 0 2006.285.16:24:13.66#ibcon#read 5, iclass 5, count 0 2006.285.16:24:13.66#ibcon#about to read 6, iclass 5, count 0 2006.285.16:24:13.66#ibcon#read 6, iclass 5, count 0 2006.285.16:24:13.66#ibcon#end of sib2, iclass 5, count 0 2006.285.16:24:13.66#ibcon#*after write, iclass 5, count 0 2006.285.16:24:13.66#ibcon#*before return 0, iclass 5, count 0 2006.285.16:24:13.66#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:24:13.66#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:24:13.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.16:24:13.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.16:24:13.66$vck44/valo=3,564.99 2006.285.16:24:13.66#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.16:24:13.66#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.16:24:13.66#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:13.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:24:13.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:24:13.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:24:13.66#ibcon#enter wrdev, iclass 7, count 0 2006.285.16:24:13.66#ibcon#first serial, iclass 7, count 0 2006.285.16:24:13.66#ibcon#enter sib2, iclass 7, count 0 2006.285.16:24:13.66#ibcon#flushed, iclass 7, count 0 2006.285.16:24:13.66#ibcon#about to write, iclass 7, count 0 2006.285.16:24:13.66#ibcon#wrote, iclass 7, count 0 2006.285.16:24:13.66#ibcon#about to read 3, iclass 7, count 0 2006.285.16:24:14.37#ibcon#read 3, iclass 7, count 0 2006.285.16:24:14.37#ibcon#about to read 4, iclass 7, count 0 2006.285.16:24:14.37#ibcon#read 4, iclass 7, count 0 2006.285.16:24:14.37#ibcon#about to read 5, iclass 7, count 0 2006.285.16:24:14.37#ibcon#read 5, iclass 7, count 0 2006.285.16:24:14.37#ibcon#about to read 6, iclass 7, count 0 2006.285.16:24:14.37#ibcon#read 6, iclass 7, count 0 2006.285.16:24:14.37#ibcon#end of sib2, iclass 7, count 0 2006.285.16:24:14.37#ibcon#*mode == 0, iclass 7, count 0 2006.285.16:24:14.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.16:24:14.37#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.16:24:14.37#ibcon#*before write, iclass 7, count 0 2006.285.16:24:14.37#ibcon#enter sib2, iclass 7, count 0 2006.285.16:24:14.37#ibcon#flushed, iclass 7, count 0 2006.285.16:24:14.37#ibcon#about to write, iclass 7, count 0 2006.285.16:24:14.37#ibcon#wrote, iclass 7, count 0 2006.285.16:24:14.37#ibcon#about to read 3, iclass 7, count 0 2006.285.16:24:14.41#ibcon#read 3, iclass 7, count 0 2006.285.16:24:14.41#ibcon#about to read 4, iclass 7, count 0 2006.285.16:24:14.41#ibcon#read 4, iclass 7, count 0 2006.285.16:24:14.41#ibcon#about to read 5, iclass 7, count 0 2006.285.16:24:14.41#ibcon#read 5, iclass 7, count 0 2006.285.16:24:14.41#ibcon#about to read 6, iclass 7, count 0 2006.285.16:24:14.41#ibcon#read 6, iclass 7, count 0 2006.285.16:24:14.41#ibcon#end of sib2, iclass 7, count 0 2006.285.16:24:14.41#ibcon#*after write, iclass 7, count 0 2006.285.16:24:14.41#ibcon#*before return 0, iclass 7, count 0 2006.285.16:24:14.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:24:14.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:24:14.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.16:24:14.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.16:24:14.41$vck44/va=3,7 2006.285.16:24:14.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.16:24:14.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.16:24:14.41#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:14.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:24:14.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:24:14.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:24:14.41#ibcon#enter wrdev, iclass 11, count 2 2006.285.16:24:14.41#ibcon#first serial, iclass 11, count 2 2006.285.16:24:14.41#ibcon#enter sib2, iclass 11, count 2 2006.285.16:24:14.41#ibcon#flushed, iclass 11, count 2 2006.285.16:24:14.41#ibcon#about to write, iclass 11, count 2 2006.285.16:24:14.41#ibcon#wrote, iclass 11, count 2 2006.285.16:24:14.41#ibcon#about to read 3, iclass 11, count 2 2006.285.16:24:14.43#ibcon#read 3, iclass 11, count 2 2006.285.16:24:14.43#ibcon#about to read 4, iclass 11, count 2 2006.285.16:24:14.43#ibcon#read 4, iclass 11, count 2 2006.285.16:24:14.43#ibcon#about to read 5, iclass 11, count 2 2006.285.16:24:14.43#ibcon#read 5, iclass 11, count 2 2006.285.16:24:14.43#ibcon#about to read 6, iclass 11, count 2 2006.285.16:24:14.43#ibcon#read 6, iclass 11, count 2 2006.285.16:24:14.43#ibcon#end of sib2, iclass 11, count 2 2006.285.16:24:14.43#ibcon#*mode == 0, iclass 11, count 2 2006.285.16:24:14.43#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.16:24:14.43#ibcon#[25=AT03-07\r\n] 2006.285.16:24:14.43#ibcon#*before write, iclass 11, count 2 2006.285.16:24:14.43#ibcon#enter sib2, iclass 11, count 2 2006.285.16:24:14.43#ibcon#flushed, iclass 11, count 2 2006.285.16:24:14.43#ibcon#about to write, iclass 11, count 2 2006.285.16:24:14.43#ibcon#wrote, iclass 11, count 2 2006.285.16:24:14.43#ibcon#about to read 3, iclass 11, count 2 2006.285.16:24:14.46#ibcon#read 3, iclass 11, count 2 2006.285.16:24:14.46#ibcon#about to read 4, iclass 11, count 2 2006.285.16:24:14.46#ibcon#read 4, iclass 11, count 2 2006.285.16:24:14.46#ibcon#about to read 5, iclass 11, count 2 2006.285.16:24:14.46#ibcon#read 5, iclass 11, count 2 2006.285.16:24:14.46#ibcon#about to read 6, iclass 11, count 2 2006.285.16:24:14.46#ibcon#read 6, iclass 11, count 2 2006.285.16:24:14.46#ibcon#end of sib2, iclass 11, count 2 2006.285.16:24:14.46#ibcon#*after write, iclass 11, count 2 2006.285.16:24:14.46#ibcon#*before return 0, iclass 11, count 2 2006.285.16:24:14.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:24:14.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:24:14.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.16:24:14.46#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:14.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:24:14.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:24:14.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:24:14.58#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:24:14.58#ibcon#first serial, iclass 11, count 0 2006.285.16:24:14.58#ibcon#enter sib2, iclass 11, count 0 2006.285.16:24:14.58#ibcon#flushed, iclass 11, count 0 2006.285.16:24:14.58#ibcon#about to write, iclass 11, count 0 2006.285.16:24:14.58#ibcon#wrote, iclass 11, count 0 2006.285.16:24:14.58#ibcon#about to read 3, iclass 11, count 0 2006.285.16:24:14.60#ibcon#read 3, iclass 11, count 0 2006.285.16:24:14.60#ibcon#about to read 4, iclass 11, count 0 2006.285.16:24:14.60#ibcon#read 4, iclass 11, count 0 2006.285.16:24:14.60#ibcon#about to read 5, iclass 11, count 0 2006.285.16:24:14.60#ibcon#read 5, iclass 11, count 0 2006.285.16:24:14.60#ibcon#about to read 6, iclass 11, count 0 2006.285.16:24:14.60#ibcon#read 6, iclass 11, count 0 2006.285.16:24:14.60#ibcon#end of sib2, iclass 11, count 0 2006.285.16:24:14.60#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:24:14.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:24:14.60#ibcon#[25=USB\r\n] 2006.285.16:24:14.60#ibcon#*before write, iclass 11, count 0 2006.285.16:24:14.60#ibcon#enter sib2, iclass 11, count 0 2006.285.16:24:14.60#ibcon#flushed, iclass 11, count 0 2006.285.16:24:14.60#ibcon#about to write, iclass 11, count 0 2006.285.16:24:14.60#ibcon#wrote, iclass 11, count 0 2006.285.16:24:14.60#ibcon#about to read 3, iclass 11, count 0 2006.285.16:24:14.63#ibcon#read 3, iclass 11, count 0 2006.285.16:24:14.63#ibcon#about to read 4, iclass 11, count 0 2006.285.16:24:14.63#ibcon#read 4, iclass 11, count 0 2006.285.16:24:14.63#ibcon#about to read 5, iclass 11, count 0 2006.285.16:24:14.63#ibcon#read 5, iclass 11, count 0 2006.285.16:24:14.63#ibcon#about to read 6, iclass 11, count 0 2006.285.16:24:14.63#ibcon#read 6, iclass 11, count 0 2006.285.16:24:14.63#ibcon#end of sib2, iclass 11, count 0 2006.285.16:24:14.63#ibcon#*after write, iclass 11, count 0 2006.285.16:24:14.63#ibcon#*before return 0, iclass 11, count 0 2006.285.16:24:14.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:24:14.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:24:14.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:24:14.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:24:14.63$vck44/valo=4,624.99 2006.285.16:24:14.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.16:24:14.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.16:24:14.63#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:14.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:24:14.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:24:14.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:24:14.63#ibcon#enter wrdev, iclass 13, count 0 2006.285.16:24:14.63#ibcon#first serial, iclass 13, count 0 2006.285.16:24:14.63#ibcon#enter sib2, iclass 13, count 0 2006.285.16:24:14.63#ibcon#flushed, iclass 13, count 0 2006.285.16:24:14.63#ibcon#about to write, iclass 13, count 0 2006.285.16:24:14.63#ibcon#wrote, iclass 13, count 0 2006.285.16:24:14.63#ibcon#about to read 3, iclass 13, count 0 2006.285.16:24:14.80#ibcon#read 3, iclass 13, count 0 2006.285.16:24:14.80#ibcon#about to read 4, iclass 13, count 0 2006.285.16:24:14.80#ibcon#read 4, iclass 13, count 0 2006.285.16:24:14.80#ibcon#about to read 5, iclass 13, count 0 2006.285.16:24:14.80#ibcon#read 5, iclass 13, count 0 2006.285.16:24:14.80#ibcon#about to read 6, iclass 13, count 0 2006.285.16:24:14.80#ibcon#read 6, iclass 13, count 0 2006.285.16:24:14.80#ibcon#end of sib2, iclass 13, count 0 2006.285.16:24:14.80#ibcon#*mode == 0, iclass 13, count 0 2006.285.16:24:14.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.16:24:14.80#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.16:24:14.80#ibcon#*before write, iclass 13, count 0 2006.285.16:24:14.80#ibcon#enter sib2, iclass 13, count 0 2006.285.16:24:14.80#ibcon#flushed, iclass 13, count 0 2006.285.16:24:14.80#ibcon#about to write, iclass 13, count 0 2006.285.16:24:14.80#ibcon#wrote, iclass 13, count 0 2006.285.16:24:14.80#ibcon#about to read 3, iclass 13, count 0 2006.285.16:24:14.85#ibcon#read 3, iclass 13, count 0 2006.285.16:24:14.85#ibcon#about to read 4, iclass 13, count 0 2006.285.16:24:14.85#ibcon#read 4, iclass 13, count 0 2006.285.16:24:14.85#ibcon#about to read 5, iclass 13, count 0 2006.285.16:24:14.85#ibcon#read 5, iclass 13, count 0 2006.285.16:24:14.85#ibcon#about to read 6, iclass 13, count 0 2006.285.16:24:14.85#ibcon#read 6, iclass 13, count 0 2006.285.16:24:14.85#ibcon#end of sib2, iclass 13, count 0 2006.285.16:24:14.85#ibcon#*after write, iclass 13, count 0 2006.285.16:24:14.85#ibcon#*before return 0, iclass 13, count 0 2006.285.16:24:14.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:24:14.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:24:14.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.16:24:14.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.16:24:14.85$vck44/va=4,6 2006.285.16:24:14.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.16:24:14.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.16:24:14.85#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:14.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:24:14.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:24:14.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:24:14.85#ibcon#enter wrdev, iclass 15, count 2 2006.285.16:24:14.85#ibcon#first serial, iclass 15, count 2 2006.285.16:24:14.85#ibcon#enter sib2, iclass 15, count 2 2006.285.16:24:14.85#ibcon#flushed, iclass 15, count 2 2006.285.16:24:14.85#ibcon#about to write, iclass 15, count 2 2006.285.16:24:14.85#ibcon#wrote, iclass 15, count 2 2006.285.16:24:14.85#ibcon#about to read 3, iclass 15, count 2 2006.285.16:24:14.87#ibcon#read 3, iclass 15, count 2 2006.285.16:24:14.87#ibcon#about to read 4, iclass 15, count 2 2006.285.16:24:14.87#ibcon#read 4, iclass 15, count 2 2006.285.16:24:14.87#ibcon#about to read 5, iclass 15, count 2 2006.285.16:24:14.87#ibcon#read 5, iclass 15, count 2 2006.285.16:24:14.87#ibcon#about to read 6, iclass 15, count 2 2006.285.16:24:14.87#ibcon#read 6, iclass 15, count 2 2006.285.16:24:14.87#ibcon#end of sib2, iclass 15, count 2 2006.285.16:24:14.87#ibcon#*mode == 0, iclass 15, count 2 2006.285.16:24:14.87#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.16:24:14.87#ibcon#[25=AT04-06\r\n] 2006.285.16:24:14.87#ibcon#*before write, iclass 15, count 2 2006.285.16:24:14.87#ibcon#enter sib2, iclass 15, count 2 2006.285.16:24:14.87#ibcon#flushed, iclass 15, count 2 2006.285.16:24:14.87#ibcon#about to write, iclass 15, count 2 2006.285.16:24:14.87#ibcon#wrote, iclass 15, count 2 2006.285.16:24:14.87#ibcon#about to read 3, iclass 15, count 2 2006.285.16:24:14.90#ibcon#read 3, iclass 15, count 2 2006.285.16:24:14.90#ibcon#about to read 4, iclass 15, count 2 2006.285.16:24:14.90#ibcon#read 4, iclass 15, count 2 2006.285.16:24:14.90#ibcon#about to read 5, iclass 15, count 2 2006.285.16:24:14.90#ibcon#read 5, iclass 15, count 2 2006.285.16:24:14.90#ibcon#about to read 6, iclass 15, count 2 2006.285.16:24:14.90#ibcon#read 6, iclass 15, count 2 2006.285.16:24:14.90#ibcon#end of sib2, iclass 15, count 2 2006.285.16:24:14.90#ibcon#*after write, iclass 15, count 2 2006.285.16:24:14.90#ibcon#*before return 0, iclass 15, count 2 2006.285.16:24:14.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:24:14.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:24:14.90#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.16:24:14.90#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:14.90#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:24:15.02#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:24:15.02#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:24:15.02#ibcon#enter wrdev, iclass 15, count 0 2006.285.16:24:15.02#ibcon#first serial, iclass 15, count 0 2006.285.16:24:15.02#ibcon#enter sib2, iclass 15, count 0 2006.285.16:24:15.02#ibcon#flushed, iclass 15, count 0 2006.285.16:24:15.02#ibcon#about to write, iclass 15, count 0 2006.285.16:24:15.02#ibcon#wrote, iclass 15, count 0 2006.285.16:24:15.02#ibcon#about to read 3, iclass 15, count 0 2006.285.16:24:15.04#ibcon#read 3, iclass 15, count 0 2006.285.16:24:15.04#ibcon#about to read 4, iclass 15, count 0 2006.285.16:24:15.04#ibcon#read 4, iclass 15, count 0 2006.285.16:24:15.04#ibcon#about to read 5, iclass 15, count 0 2006.285.16:24:15.04#ibcon#read 5, iclass 15, count 0 2006.285.16:24:15.04#ibcon#about to read 6, iclass 15, count 0 2006.285.16:24:15.04#ibcon#read 6, iclass 15, count 0 2006.285.16:24:15.04#ibcon#end of sib2, iclass 15, count 0 2006.285.16:24:15.04#ibcon#*mode == 0, iclass 15, count 0 2006.285.16:24:15.04#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.16:24:15.04#ibcon#[25=USB\r\n] 2006.285.16:24:15.04#ibcon#*before write, iclass 15, count 0 2006.285.16:24:15.04#ibcon#enter sib2, iclass 15, count 0 2006.285.16:24:15.04#ibcon#flushed, iclass 15, count 0 2006.285.16:24:15.04#ibcon#about to write, iclass 15, count 0 2006.285.16:24:15.04#ibcon#wrote, iclass 15, count 0 2006.285.16:24:15.04#ibcon#about to read 3, iclass 15, count 0 2006.285.16:24:15.07#ibcon#read 3, iclass 15, count 0 2006.285.16:24:15.07#ibcon#about to read 4, iclass 15, count 0 2006.285.16:24:15.07#ibcon#read 4, iclass 15, count 0 2006.285.16:24:15.07#ibcon#about to read 5, iclass 15, count 0 2006.285.16:24:15.07#ibcon#read 5, iclass 15, count 0 2006.285.16:24:15.07#ibcon#about to read 6, iclass 15, count 0 2006.285.16:24:15.07#ibcon#read 6, iclass 15, count 0 2006.285.16:24:15.07#ibcon#end of sib2, iclass 15, count 0 2006.285.16:24:15.07#ibcon#*after write, iclass 15, count 0 2006.285.16:24:15.07#ibcon#*before return 0, iclass 15, count 0 2006.285.16:24:15.07#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:24:15.07#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:24:15.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.16:24:15.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.16:24:15.07$vck44/valo=5,734.99 2006.285.16:24:15.07#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.16:24:15.07#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.16:24:15.07#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:15.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:24:15.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:24:15.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:24:15.07#ibcon#enter wrdev, iclass 17, count 0 2006.285.16:24:15.07#ibcon#first serial, iclass 17, count 0 2006.285.16:24:15.07#ibcon#enter sib2, iclass 17, count 0 2006.285.16:24:15.07#ibcon#flushed, iclass 17, count 0 2006.285.16:24:15.07#ibcon#about to write, iclass 17, count 0 2006.285.16:24:15.07#ibcon#wrote, iclass 17, count 0 2006.285.16:24:15.07#ibcon#about to read 3, iclass 17, count 0 2006.285.16:24:15.09#ibcon#read 3, iclass 17, count 0 2006.285.16:24:15.09#ibcon#about to read 4, iclass 17, count 0 2006.285.16:24:15.09#ibcon#read 4, iclass 17, count 0 2006.285.16:24:15.09#ibcon#about to read 5, iclass 17, count 0 2006.285.16:24:15.09#ibcon#read 5, iclass 17, count 0 2006.285.16:24:15.09#ibcon#about to read 6, iclass 17, count 0 2006.285.16:24:15.09#ibcon#read 6, iclass 17, count 0 2006.285.16:24:15.09#ibcon#end of sib2, iclass 17, count 0 2006.285.16:24:15.09#ibcon#*mode == 0, iclass 17, count 0 2006.285.16:24:15.09#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.16:24:15.09#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.16:24:15.09#ibcon#*before write, iclass 17, count 0 2006.285.16:24:15.09#ibcon#enter sib2, iclass 17, count 0 2006.285.16:24:15.09#ibcon#flushed, iclass 17, count 0 2006.285.16:24:15.09#ibcon#about to write, iclass 17, count 0 2006.285.16:24:15.09#ibcon#wrote, iclass 17, count 0 2006.285.16:24:15.09#ibcon#about to read 3, iclass 17, count 0 2006.285.16:24:15.13#ibcon#read 3, iclass 17, count 0 2006.285.16:24:15.13#ibcon#about to read 4, iclass 17, count 0 2006.285.16:24:15.13#ibcon#read 4, iclass 17, count 0 2006.285.16:24:15.13#ibcon#about to read 5, iclass 17, count 0 2006.285.16:24:15.13#ibcon#read 5, iclass 17, count 0 2006.285.16:24:15.13#ibcon#about to read 6, iclass 17, count 0 2006.285.16:24:15.13#ibcon#read 6, iclass 17, count 0 2006.285.16:24:15.13#ibcon#end of sib2, iclass 17, count 0 2006.285.16:24:15.13#ibcon#*after write, iclass 17, count 0 2006.285.16:24:15.13#ibcon#*before return 0, iclass 17, count 0 2006.285.16:24:15.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:24:15.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:24:15.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.16:24:15.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.16:24:15.13$vck44/va=5,3 2006.285.16:24:15.13#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.16:24:15.13#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.16:24:15.13#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:15.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:24:15.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:24:15.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:24:15.19#ibcon#enter wrdev, iclass 19, count 2 2006.285.16:24:15.19#ibcon#first serial, iclass 19, count 2 2006.285.16:24:15.19#ibcon#enter sib2, iclass 19, count 2 2006.285.16:24:15.19#ibcon#flushed, iclass 19, count 2 2006.285.16:24:15.19#ibcon#about to write, iclass 19, count 2 2006.285.16:24:15.19#ibcon#wrote, iclass 19, count 2 2006.285.16:24:15.19#ibcon#about to read 3, iclass 19, count 2 2006.285.16:24:15.21#ibcon#read 3, iclass 19, count 2 2006.285.16:24:15.21#ibcon#about to read 4, iclass 19, count 2 2006.285.16:24:15.21#ibcon#read 4, iclass 19, count 2 2006.285.16:24:15.21#ibcon#about to read 5, iclass 19, count 2 2006.285.16:24:15.21#ibcon#read 5, iclass 19, count 2 2006.285.16:24:15.21#ibcon#about to read 6, iclass 19, count 2 2006.285.16:24:15.21#ibcon#read 6, iclass 19, count 2 2006.285.16:24:15.21#ibcon#end of sib2, iclass 19, count 2 2006.285.16:24:15.21#ibcon#*mode == 0, iclass 19, count 2 2006.285.16:24:15.21#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.16:24:15.21#ibcon#[25=AT05-03\r\n] 2006.285.16:24:15.21#ibcon#*before write, iclass 19, count 2 2006.285.16:24:15.21#ibcon#enter sib2, iclass 19, count 2 2006.285.16:24:15.21#ibcon#flushed, iclass 19, count 2 2006.285.16:24:15.21#ibcon#about to write, iclass 19, count 2 2006.285.16:24:15.21#ibcon#wrote, iclass 19, count 2 2006.285.16:24:15.21#ibcon#about to read 3, iclass 19, count 2 2006.285.16:24:15.24#ibcon#read 3, iclass 19, count 2 2006.285.16:24:15.24#ibcon#about to read 4, iclass 19, count 2 2006.285.16:24:15.24#ibcon#read 4, iclass 19, count 2 2006.285.16:24:15.24#ibcon#about to read 5, iclass 19, count 2 2006.285.16:24:15.24#ibcon#read 5, iclass 19, count 2 2006.285.16:24:15.24#ibcon#about to read 6, iclass 19, count 2 2006.285.16:24:15.24#ibcon#read 6, iclass 19, count 2 2006.285.16:24:15.24#ibcon#end of sib2, iclass 19, count 2 2006.285.16:24:15.24#ibcon#*after write, iclass 19, count 2 2006.285.16:24:15.24#ibcon#*before return 0, iclass 19, count 2 2006.285.16:24:15.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:24:15.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:24:15.24#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.16:24:15.24#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:15.24#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:24:15.36#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:24:15.36#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:24:15.36#ibcon#enter wrdev, iclass 19, count 0 2006.285.16:24:15.36#ibcon#first serial, iclass 19, count 0 2006.285.16:24:15.36#ibcon#enter sib2, iclass 19, count 0 2006.285.16:24:15.36#ibcon#flushed, iclass 19, count 0 2006.285.16:24:15.36#ibcon#about to write, iclass 19, count 0 2006.285.16:24:15.36#ibcon#wrote, iclass 19, count 0 2006.285.16:24:15.36#ibcon#about to read 3, iclass 19, count 0 2006.285.16:24:15.38#ibcon#read 3, iclass 19, count 0 2006.285.16:24:15.38#ibcon#about to read 4, iclass 19, count 0 2006.285.16:24:15.38#ibcon#read 4, iclass 19, count 0 2006.285.16:24:15.38#ibcon#about to read 5, iclass 19, count 0 2006.285.16:24:15.38#ibcon#read 5, iclass 19, count 0 2006.285.16:24:15.38#ibcon#about to read 6, iclass 19, count 0 2006.285.16:24:15.38#ibcon#read 6, iclass 19, count 0 2006.285.16:24:15.38#ibcon#end of sib2, iclass 19, count 0 2006.285.16:24:15.38#ibcon#*mode == 0, iclass 19, count 0 2006.285.16:24:15.38#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.16:24:15.38#ibcon#[25=USB\r\n] 2006.285.16:24:15.38#ibcon#*before write, iclass 19, count 0 2006.285.16:24:15.38#ibcon#enter sib2, iclass 19, count 0 2006.285.16:24:15.38#ibcon#flushed, iclass 19, count 0 2006.285.16:24:15.38#ibcon#about to write, iclass 19, count 0 2006.285.16:24:15.38#ibcon#wrote, iclass 19, count 0 2006.285.16:24:15.38#ibcon#about to read 3, iclass 19, count 0 2006.285.16:24:15.41#ibcon#read 3, iclass 19, count 0 2006.285.16:24:15.41#ibcon#about to read 4, iclass 19, count 0 2006.285.16:24:15.41#ibcon#read 4, iclass 19, count 0 2006.285.16:24:15.41#ibcon#about to read 5, iclass 19, count 0 2006.285.16:24:15.41#ibcon#read 5, iclass 19, count 0 2006.285.16:24:15.41#ibcon#about to read 6, iclass 19, count 0 2006.285.16:24:15.41#ibcon#read 6, iclass 19, count 0 2006.285.16:24:15.41#ibcon#end of sib2, iclass 19, count 0 2006.285.16:24:15.41#ibcon#*after write, iclass 19, count 0 2006.285.16:24:15.41#ibcon#*before return 0, iclass 19, count 0 2006.285.16:24:15.41#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:24:15.41#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:24:15.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.16:24:15.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.16:24:15.41$vck44/valo=6,814.99 2006.285.16:24:15.41#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.16:24:15.41#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.16:24:15.41#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:15.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:24:15.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:24:15.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:24:15.41#ibcon#enter wrdev, iclass 21, count 0 2006.285.16:24:15.41#ibcon#first serial, iclass 21, count 0 2006.285.16:24:15.41#ibcon#enter sib2, iclass 21, count 0 2006.285.16:24:15.41#ibcon#flushed, iclass 21, count 0 2006.285.16:24:15.41#ibcon#about to write, iclass 21, count 0 2006.285.16:24:15.41#ibcon#wrote, iclass 21, count 0 2006.285.16:24:15.41#ibcon#about to read 3, iclass 21, count 0 2006.285.16:24:15.43#ibcon#read 3, iclass 21, count 0 2006.285.16:24:15.43#ibcon#about to read 4, iclass 21, count 0 2006.285.16:24:15.43#ibcon#read 4, iclass 21, count 0 2006.285.16:24:15.43#ibcon#about to read 5, iclass 21, count 0 2006.285.16:24:15.43#ibcon#read 5, iclass 21, count 0 2006.285.16:24:15.43#ibcon#about to read 6, iclass 21, count 0 2006.285.16:24:15.43#ibcon#read 6, iclass 21, count 0 2006.285.16:24:15.43#ibcon#end of sib2, iclass 21, count 0 2006.285.16:24:15.43#ibcon#*mode == 0, iclass 21, count 0 2006.285.16:24:15.43#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.16:24:15.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.16:24:15.43#ibcon#*before write, iclass 21, count 0 2006.285.16:24:15.43#ibcon#enter sib2, iclass 21, count 0 2006.285.16:24:15.43#ibcon#flushed, iclass 21, count 0 2006.285.16:24:15.43#ibcon#about to write, iclass 21, count 0 2006.285.16:24:15.43#ibcon#wrote, iclass 21, count 0 2006.285.16:24:15.43#ibcon#about to read 3, iclass 21, count 0 2006.285.16:24:15.47#ibcon#read 3, iclass 21, count 0 2006.285.16:24:15.47#ibcon#about to read 4, iclass 21, count 0 2006.285.16:24:15.47#ibcon#read 4, iclass 21, count 0 2006.285.16:24:15.47#ibcon#about to read 5, iclass 21, count 0 2006.285.16:24:15.47#ibcon#read 5, iclass 21, count 0 2006.285.16:24:15.47#ibcon#about to read 6, iclass 21, count 0 2006.285.16:24:15.47#ibcon#read 6, iclass 21, count 0 2006.285.16:24:15.47#ibcon#end of sib2, iclass 21, count 0 2006.285.16:24:15.47#ibcon#*after write, iclass 21, count 0 2006.285.16:24:15.47#ibcon#*before return 0, iclass 21, count 0 2006.285.16:24:15.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:24:15.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:24:15.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.16:24:15.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.16:24:15.47$vck44/va=6,4 2006.285.16:24:15.47#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.16:24:15.47#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.16:24:15.47#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:15.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:24:15.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:24:15.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:24:15.53#ibcon#enter wrdev, iclass 23, count 2 2006.285.16:24:15.53#ibcon#first serial, iclass 23, count 2 2006.285.16:24:15.53#ibcon#enter sib2, iclass 23, count 2 2006.285.16:24:15.53#ibcon#flushed, iclass 23, count 2 2006.285.16:24:15.53#ibcon#about to write, iclass 23, count 2 2006.285.16:24:15.53#ibcon#wrote, iclass 23, count 2 2006.285.16:24:15.53#ibcon#about to read 3, iclass 23, count 2 2006.285.16:24:15.55#ibcon#read 3, iclass 23, count 2 2006.285.16:24:15.55#ibcon#about to read 4, iclass 23, count 2 2006.285.16:24:15.55#ibcon#read 4, iclass 23, count 2 2006.285.16:24:15.55#ibcon#about to read 5, iclass 23, count 2 2006.285.16:24:15.55#ibcon#read 5, iclass 23, count 2 2006.285.16:24:15.55#ibcon#about to read 6, iclass 23, count 2 2006.285.16:24:15.55#ibcon#read 6, iclass 23, count 2 2006.285.16:24:15.55#ibcon#end of sib2, iclass 23, count 2 2006.285.16:24:15.55#ibcon#*mode == 0, iclass 23, count 2 2006.285.16:24:15.55#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.16:24:15.55#ibcon#[25=AT06-04\r\n] 2006.285.16:24:15.55#ibcon#*before write, iclass 23, count 2 2006.285.16:24:15.55#ibcon#enter sib2, iclass 23, count 2 2006.285.16:24:15.55#ibcon#flushed, iclass 23, count 2 2006.285.16:24:15.55#ibcon#about to write, iclass 23, count 2 2006.285.16:24:15.55#ibcon#wrote, iclass 23, count 2 2006.285.16:24:15.55#ibcon#about to read 3, iclass 23, count 2 2006.285.16:24:15.58#ibcon#read 3, iclass 23, count 2 2006.285.16:24:15.58#ibcon#about to read 4, iclass 23, count 2 2006.285.16:24:15.58#ibcon#read 4, iclass 23, count 2 2006.285.16:24:15.58#ibcon#about to read 5, iclass 23, count 2 2006.285.16:24:15.58#ibcon#read 5, iclass 23, count 2 2006.285.16:24:15.58#ibcon#about to read 6, iclass 23, count 2 2006.285.16:24:15.58#ibcon#read 6, iclass 23, count 2 2006.285.16:24:15.58#ibcon#end of sib2, iclass 23, count 2 2006.285.16:24:15.58#ibcon#*after write, iclass 23, count 2 2006.285.16:24:15.58#ibcon#*before return 0, iclass 23, count 2 2006.285.16:24:15.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:24:15.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:24:15.58#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.16:24:15.58#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:15.58#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:24:15.70#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:24:15.70#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:24:15.70#ibcon#enter wrdev, iclass 23, count 0 2006.285.16:24:15.70#ibcon#first serial, iclass 23, count 0 2006.285.16:24:15.70#ibcon#enter sib2, iclass 23, count 0 2006.285.16:24:15.70#ibcon#flushed, iclass 23, count 0 2006.285.16:24:15.70#ibcon#about to write, iclass 23, count 0 2006.285.16:24:15.70#ibcon#wrote, iclass 23, count 0 2006.285.16:24:15.70#ibcon#about to read 3, iclass 23, count 0 2006.285.16:24:15.72#ibcon#read 3, iclass 23, count 0 2006.285.16:24:15.72#ibcon#about to read 4, iclass 23, count 0 2006.285.16:24:15.72#ibcon#read 4, iclass 23, count 0 2006.285.16:24:15.72#ibcon#about to read 5, iclass 23, count 0 2006.285.16:24:15.72#ibcon#read 5, iclass 23, count 0 2006.285.16:24:15.72#ibcon#about to read 6, iclass 23, count 0 2006.285.16:24:15.72#ibcon#read 6, iclass 23, count 0 2006.285.16:24:15.72#ibcon#end of sib2, iclass 23, count 0 2006.285.16:24:15.72#ibcon#*mode == 0, iclass 23, count 0 2006.285.16:24:15.72#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.16:24:15.72#ibcon#[25=USB\r\n] 2006.285.16:24:15.72#ibcon#*before write, iclass 23, count 0 2006.285.16:24:15.72#ibcon#enter sib2, iclass 23, count 0 2006.285.16:24:15.72#ibcon#flushed, iclass 23, count 0 2006.285.16:24:15.72#ibcon#about to write, iclass 23, count 0 2006.285.16:24:15.72#ibcon#wrote, iclass 23, count 0 2006.285.16:24:15.72#ibcon#about to read 3, iclass 23, count 0 2006.285.16:24:15.75#ibcon#read 3, iclass 23, count 0 2006.285.16:24:15.75#ibcon#about to read 4, iclass 23, count 0 2006.285.16:24:15.75#ibcon#read 4, iclass 23, count 0 2006.285.16:24:15.75#ibcon#about to read 5, iclass 23, count 0 2006.285.16:24:15.75#ibcon#read 5, iclass 23, count 0 2006.285.16:24:15.75#ibcon#about to read 6, iclass 23, count 0 2006.285.16:24:15.75#ibcon#read 6, iclass 23, count 0 2006.285.16:24:15.75#ibcon#end of sib2, iclass 23, count 0 2006.285.16:24:15.75#ibcon#*after write, iclass 23, count 0 2006.285.16:24:15.75#ibcon#*before return 0, iclass 23, count 0 2006.285.16:24:15.75#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:24:15.75#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:24:15.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.16:24:15.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.16:24:15.75$vck44/valo=7,864.99 2006.285.16:24:15.75#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.16:24:15.75#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.16:24:15.75#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:15.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:24:15.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:24:15.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:24:15.75#ibcon#enter wrdev, iclass 25, count 0 2006.285.16:24:15.75#ibcon#first serial, iclass 25, count 0 2006.285.16:24:15.75#ibcon#enter sib2, iclass 25, count 0 2006.285.16:24:15.75#ibcon#flushed, iclass 25, count 0 2006.285.16:24:15.75#ibcon#about to write, iclass 25, count 0 2006.285.16:24:15.75#ibcon#wrote, iclass 25, count 0 2006.285.16:24:15.75#ibcon#about to read 3, iclass 25, count 0 2006.285.16:24:15.77#ibcon#read 3, iclass 25, count 0 2006.285.16:24:15.92#ibcon#about to read 4, iclass 25, count 0 2006.285.16:24:15.92#ibcon#read 4, iclass 25, count 0 2006.285.16:24:15.92#ibcon#about to read 5, iclass 25, count 0 2006.285.16:24:15.92#ibcon#read 5, iclass 25, count 0 2006.285.16:24:15.92#ibcon#about to read 6, iclass 25, count 0 2006.285.16:24:15.92#ibcon#read 6, iclass 25, count 0 2006.285.16:24:15.92#ibcon#end of sib2, iclass 25, count 0 2006.285.16:24:15.92#ibcon#*mode == 0, iclass 25, count 0 2006.285.16:24:15.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.16:24:15.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.16:24:15.92#ibcon#*before write, iclass 25, count 0 2006.285.16:24:15.92#ibcon#enter sib2, iclass 25, count 0 2006.285.16:24:15.92#ibcon#flushed, iclass 25, count 0 2006.285.16:24:15.92#ibcon#about to write, iclass 25, count 0 2006.285.16:24:15.92#ibcon#wrote, iclass 25, count 0 2006.285.16:24:15.92#ibcon#about to read 3, iclass 25, count 0 2006.285.16:24:15.96#ibcon#read 3, iclass 25, count 0 2006.285.16:24:15.96#ibcon#about to read 4, iclass 25, count 0 2006.285.16:24:15.96#ibcon#read 4, iclass 25, count 0 2006.285.16:24:15.96#ibcon#about to read 5, iclass 25, count 0 2006.285.16:24:15.96#ibcon#read 5, iclass 25, count 0 2006.285.16:24:15.96#ibcon#about to read 6, iclass 25, count 0 2006.285.16:24:15.96#ibcon#read 6, iclass 25, count 0 2006.285.16:24:15.96#ibcon#end of sib2, iclass 25, count 0 2006.285.16:24:15.96#ibcon#*after write, iclass 25, count 0 2006.285.16:24:15.96#ibcon#*before return 0, iclass 25, count 0 2006.285.16:24:15.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:24:15.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:24:15.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.16:24:15.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.16:24:15.96$vck44/va=7,4 2006.285.16:24:15.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.16:24:15.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.16:24:15.96#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:15.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:24:15.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:24:15.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:24:15.96#ibcon#enter wrdev, iclass 27, count 2 2006.285.16:24:15.96#ibcon#first serial, iclass 27, count 2 2006.285.16:24:15.96#ibcon#enter sib2, iclass 27, count 2 2006.285.16:24:15.96#ibcon#flushed, iclass 27, count 2 2006.285.16:24:15.96#ibcon#about to write, iclass 27, count 2 2006.285.16:24:15.96#ibcon#wrote, iclass 27, count 2 2006.285.16:24:15.96#ibcon#about to read 3, iclass 27, count 2 2006.285.16:24:15.98#ibcon#read 3, iclass 27, count 2 2006.285.16:24:15.98#ibcon#about to read 4, iclass 27, count 2 2006.285.16:24:15.98#ibcon#read 4, iclass 27, count 2 2006.285.16:24:15.98#ibcon#about to read 5, iclass 27, count 2 2006.285.16:24:15.98#ibcon#read 5, iclass 27, count 2 2006.285.16:24:15.98#ibcon#about to read 6, iclass 27, count 2 2006.285.16:24:15.98#ibcon#read 6, iclass 27, count 2 2006.285.16:24:15.98#ibcon#end of sib2, iclass 27, count 2 2006.285.16:24:15.98#ibcon#*mode == 0, iclass 27, count 2 2006.285.16:24:15.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.16:24:15.98#ibcon#[25=AT07-04\r\n] 2006.285.16:24:15.98#ibcon#*before write, iclass 27, count 2 2006.285.16:24:15.98#ibcon#enter sib2, iclass 27, count 2 2006.285.16:24:15.98#ibcon#flushed, iclass 27, count 2 2006.285.16:24:15.98#ibcon#about to write, iclass 27, count 2 2006.285.16:24:15.98#ibcon#wrote, iclass 27, count 2 2006.285.16:24:15.98#ibcon#about to read 3, iclass 27, count 2 2006.285.16:24:16.01#ibcon#read 3, iclass 27, count 2 2006.285.16:24:16.01#ibcon#about to read 4, iclass 27, count 2 2006.285.16:24:16.01#ibcon#read 4, iclass 27, count 2 2006.285.16:24:16.01#ibcon#about to read 5, iclass 27, count 2 2006.285.16:24:16.01#ibcon#read 5, iclass 27, count 2 2006.285.16:24:16.01#ibcon#about to read 6, iclass 27, count 2 2006.285.16:24:16.01#ibcon#read 6, iclass 27, count 2 2006.285.16:24:16.01#ibcon#end of sib2, iclass 27, count 2 2006.285.16:24:16.01#ibcon#*after write, iclass 27, count 2 2006.285.16:24:16.01#ibcon#*before return 0, iclass 27, count 2 2006.285.16:24:16.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:24:16.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:24:16.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.16:24:16.01#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:16.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:24:16.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:24:16.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:24:16.13#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:24:16.13#ibcon#first serial, iclass 27, count 0 2006.285.16:24:16.13#ibcon#enter sib2, iclass 27, count 0 2006.285.16:24:16.13#ibcon#flushed, iclass 27, count 0 2006.285.16:24:16.13#ibcon#about to write, iclass 27, count 0 2006.285.16:24:16.13#ibcon#wrote, iclass 27, count 0 2006.285.16:24:16.13#ibcon#about to read 3, iclass 27, count 0 2006.285.16:24:16.15#ibcon#read 3, iclass 27, count 0 2006.285.16:24:16.15#ibcon#about to read 4, iclass 27, count 0 2006.285.16:24:16.15#ibcon#read 4, iclass 27, count 0 2006.285.16:24:16.15#ibcon#about to read 5, iclass 27, count 0 2006.285.16:24:16.15#ibcon#read 5, iclass 27, count 0 2006.285.16:24:16.15#ibcon#about to read 6, iclass 27, count 0 2006.285.16:24:16.15#ibcon#read 6, iclass 27, count 0 2006.285.16:24:16.15#ibcon#end of sib2, iclass 27, count 0 2006.285.16:24:16.15#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:24:16.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:24:16.15#ibcon#[25=USB\r\n] 2006.285.16:24:16.15#ibcon#*before write, iclass 27, count 0 2006.285.16:24:16.15#ibcon#enter sib2, iclass 27, count 0 2006.285.16:24:16.15#ibcon#flushed, iclass 27, count 0 2006.285.16:24:16.15#ibcon#about to write, iclass 27, count 0 2006.285.16:24:16.15#ibcon#wrote, iclass 27, count 0 2006.285.16:24:16.15#ibcon#about to read 3, iclass 27, count 0 2006.285.16:24:16.18#ibcon#read 3, iclass 27, count 0 2006.285.16:24:16.18#ibcon#about to read 4, iclass 27, count 0 2006.285.16:24:16.18#ibcon#read 4, iclass 27, count 0 2006.285.16:24:16.18#ibcon#about to read 5, iclass 27, count 0 2006.285.16:24:16.18#ibcon#read 5, iclass 27, count 0 2006.285.16:24:16.18#ibcon#about to read 6, iclass 27, count 0 2006.285.16:24:16.18#ibcon#read 6, iclass 27, count 0 2006.285.16:24:16.18#ibcon#end of sib2, iclass 27, count 0 2006.285.16:24:16.18#ibcon#*after write, iclass 27, count 0 2006.285.16:24:16.18#ibcon#*before return 0, iclass 27, count 0 2006.285.16:24:16.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:24:16.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:24:16.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:24:16.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:24:16.18$vck44/valo=8,884.99 2006.285.16:24:16.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.16:24:16.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.16:24:16.18#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:16.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:24:16.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:24:16.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:24:16.18#ibcon#enter wrdev, iclass 29, count 0 2006.285.16:24:16.18#ibcon#first serial, iclass 29, count 0 2006.285.16:24:16.18#ibcon#enter sib2, iclass 29, count 0 2006.285.16:24:16.18#ibcon#flushed, iclass 29, count 0 2006.285.16:24:16.18#ibcon#about to write, iclass 29, count 0 2006.285.16:24:16.18#ibcon#wrote, iclass 29, count 0 2006.285.16:24:16.18#ibcon#about to read 3, iclass 29, count 0 2006.285.16:24:16.20#ibcon#read 3, iclass 29, count 0 2006.285.16:24:16.20#ibcon#about to read 4, iclass 29, count 0 2006.285.16:24:16.20#ibcon#read 4, iclass 29, count 0 2006.285.16:24:16.20#ibcon#about to read 5, iclass 29, count 0 2006.285.16:24:16.20#ibcon#read 5, iclass 29, count 0 2006.285.16:24:16.20#ibcon#about to read 6, iclass 29, count 0 2006.285.16:24:16.20#ibcon#read 6, iclass 29, count 0 2006.285.16:24:16.20#ibcon#end of sib2, iclass 29, count 0 2006.285.16:24:16.20#ibcon#*mode == 0, iclass 29, count 0 2006.285.16:24:16.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.16:24:16.20#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.16:24:16.20#ibcon#*before write, iclass 29, count 0 2006.285.16:24:16.20#ibcon#enter sib2, iclass 29, count 0 2006.285.16:24:16.20#ibcon#flushed, iclass 29, count 0 2006.285.16:24:16.20#ibcon#about to write, iclass 29, count 0 2006.285.16:24:16.20#ibcon#wrote, iclass 29, count 0 2006.285.16:24:16.20#ibcon#about to read 3, iclass 29, count 0 2006.285.16:24:16.24#ibcon#read 3, iclass 29, count 0 2006.285.16:24:16.24#ibcon#about to read 4, iclass 29, count 0 2006.285.16:24:16.24#ibcon#read 4, iclass 29, count 0 2006.285.16:24:16.24#ibcon#about to read 5, iclass 29, count 0 2006.285.16:24:16.24#ibcon#read 5, iclass 29, count 0 2006.285.16:24:16.24#ibcon#about to read 6, iclass 29, count 0 2006.285.16:24:16.24#ibcon#read 6, iclass 29, count 0 2006.285.16:24:16.24#ibcon#end of sib2, iclass 29, count 0 2006.285.16:24:16.24#ibcon#*after write, iclass 29, count 0 2006.285.16:24:16.24#ibcon#*before return 0, iclass 29, count 0 2006.285.16:24:16.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:24:16.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:24:16.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.16:24:16.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.16:24:16.24$vck44/va=8,3 2006.285.16:24:16.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.16:24:16.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.16:24:16.24#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:16.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:24:16.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:24:16.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:24:16.30#ibcon#enter wrdev, iclass 31, count 2 2006.285.16:24:16.30#ibcon#first serial, iclass 31, count 2 2006.285.16:24:16.30#ibcon#enter sib2, iclass 31, count 2 2006.285.16:24:16.30#ibcon#flushed, iclass 31, count 2 2006.285.16:24:16.30#ibcon#about to write, iclass 31, count 2 2006.285.16:24:16.30#ibcon#wrote, iclass 31, count 2 2006.285.16:24:16.30#ibcon#about to read 3, iclass 31, count 2 2006.285.16:24:16.32#ibcon#read 3, iclass 31, count 2 2006.285.16:24:16.32#ibcon#about to read 4, iclass 31, count 2 2006.285.16:24:16.32#ibcon#read 4, iclass 31, count 2 2006.285.16:24:16.32#ibcon#about to read 5, iclass 31, count 2 2006.285.16:24:16.32#ibcon#read 5, iclass 31, count 2 2006.285.16:24:16.32#ibcon#about to read 6, iclass 31, count 2 2006.285.16:24:16.32#ibcon#read 6, iclass 31, count 2 2006.285.16:24:16.32#ibcon#end of sib2, iclass 31, count 2 2006.285.16:24:16.32#ibcon#*mode == 0, iclass 31, count 2 2006.285.16:24:16.32#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.16:24:16.32#ibcon#[25=AT08-03\r\n] 2006.285.16:24:16.32#ibcon#*before write, iclass 31, count 2 2006.285.16:24:16.32#ibcon#enter sib2, iclass 31, count 2 2006.285.16:24:16.32#ibcon#flushed, iclass 31, count 2 2006.285.16:24:16.32#ibcon#about to write, iclass 31, count 2 2006.285.16:24:16.32#ibcon#wrote, iclass 31, count 2 2006.285.16:24:16.32#ibcon#about to read 3, iclass 31, count 2 2006.285.16:24:16.35#ibcon#read 3, iclass 31, count 2 2006.285.16:24:16.35#ibcon#about to read 4, iclass 31, count 2 2006.285.16:24:16.35#ibcon#read 4, iclass 31, count 2 2006.285.16:24:16.35#ibcon#about to read 5, iclass 31, count 2 2006.285.16:24:16.35#ibcon#read 5, iclass 31, count 2 2006.285.16:24:16.35#ibcon#about to read 6, iclass 31, count 2 2006.285.16:24:16.35#ibcon#read 6, iclass 31, count 2 2006.285.16:24:16.35#ibcon#end of sib2, iclass 31, count 2 2006.285.16:24:16.35#ibcon#*after write, iclass 31, count 2 2006.285.16:24:16.35#ibcon#*before return 0, iclass 31, count 2 2006.285.16:24:16.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:24:16.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:24:16.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.16:24:16.35#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:16.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:24:16.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:24:16.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:24:16.47#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:24:16.47#ibcon#first serial, iclass 31, count 0 2006.285.16:24:16.47#ibcon#enter sib2, iclass 31, count 0 2006.285.16:24:16.47#ibcon#flushed, iclass 31, count 0 2006.285.16:24:16.47#ibcon#about to write, iclass 31, count 0 2006.285.16:24:16.47#ibcon#wrote, iclass 31, count 0 2006.285.16:24:16.47#ibcon#about to read 3, iclass 31, count 0 2006.285.16:24:16.49#ibcon#read 3, iclass 31, count 0 2006.285.16:24:16.49#ibcon#about to read 4, iclass 31, count 0 2006.285.16:24:16.49#ibcon#read 4, iclass 31, count 0 2006.285.16:24:16.49#ibcon#about to read 5, iclass 31, count 0 2006.285.16:24:16.49#ibcon#read 5, iclass 31, count 0 2006.285.16:24:16.49#ibcon#about to read 6, iclass 31, count 0 2006.285.16:24:16.49#ibcon#read 6, iclass 31, count 0 2006.285.16:24:16.49#ibcon#end of sib2, iclass 31, count 0 2006.285.16:24:16.49#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:24:16.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:24:16.49#ibcon#[25=USB\r\n] 2006.285.16:24:16.49#ibcon#*before write, iclass 31, count 0 2006.285.16:24:16.49#ibcon#enter sib2, iclass 31, count 0 2006.285.16:24:16.49#ibcon#flushed, iclass 31, count 0 2006.285.16:24:16.49#ibcon#about to write, iclass 31, count 0 2006.285.16:24:16.49#ibcon#wrote, iclass 31, count 0 2006.285.16:24:16.49#ibcon#about to read 3, iclass 31, count 0 2006.285.16:24:16.52#ibcon#read 3, iclass 31, count 0 2006.285.16:24:16.52#ibcon#about to read 4, iclass 31, count 0 2006.285.16:24:16.52#ibcon#read 4, iclass 31, count 0 2006.285.16:24:16.52#ibcon#about to read 5, iclass 31, count 0 2006.285.16:24:16.52#ibcon#read 5, iclass 31, count 0 2006.285.16:24:16.52#ibcon#about to read 6, iclass 31, count 0 2006.285.16:24:16.52#ibcon#read 6, iclass 31, count 0 2006.285.16:24:16.52#ibcon#end of sib2, iclass 31, count 0 2006.285.16:24:16.52#ibcon#*after write, iclass 31, count 0 2006.285.16:24:16.52#ibcon#*before return 0, iclass 31, count 0 2006.285.16:24:16.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:24:16.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:24:16.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:24:16.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:24:16.52$vck44/vblo=1,629.99 2006.285.16:24:16.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.16:24:16.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.16:24:16.52#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:16.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:24:16.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:24:16.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:24:16.52#ibcon#enter wrdev, iclass 33, count 0 2006.285.16:24:16.52#ibcon#first serial, iclass 33, count 0 2006.285.16:24:16.52#ibcon#enter sib2, iclass 33, count 0 2006.285.16:24:16.52#ibcon#flushed, iclass 33, count 0 2006.285.16:24:16.52#ibcon#about to write, iclass 33, count 0 2006.285.16:24:16.52#ibcon#wrote, iclass 33, count 0 2006.285.16:24:16.52#ibcon#about to read 3, iclass 33, count 0 2006.285.16:24:16.54#ibcon#read 3, iclass 33, count 0 2006.285.16:24:16.54#ibcon#about to read 4, iclass 33, count 0 2006.285.16:24:16.54#ibcon#read 4, iclass 33, count 0 2006.285.16:24:16.54#ibcon#about to read 5, iclass 33, count 0 2006.285.16:24:16.54#ibcon#read 5, iclass 33, count 0 2006.285.16:24:16.54#ibcon#about to read 6, iclass 33, count 0 2006.285.16:24:16.54#ibcon#read 6, iclass 33, count 0 2006.285.16:24:16.54#ibcon#end of sib2, iclass 33, count 0 2006.285.16:24:16.54#ibcon#*mode == 0, iclass 33, count 0 2006.285.16:24:16.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.16:24:16.54#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.16:24:16.54#ibcon#*before write, iclass 33, count 0 2006.285.16:24:16.54#ibcon#enter sib2, iclass 33, count 0 2006.285.16:24:16.54#ibcon#flushed, iclass 33, count 0 2006.285.16:24:16.54#ibcon#about to write, iclass 33, count 0 2006.285.16:24:16.54#ibcon#wrote, iclass 33, count 0 2006.285.16:24:16.54#ibcon#about to read 3, iclass 33, count 0 2006.285.16:24:16.58#ibcon#read 3, iclass 33, count 0 2006.285.16:24:16.58#ibcon#about to read 4, iclass 33, count 0 2006.285.16:24:16.58#ibcon#read 4, iclass 33, count 0 2006.285.16:24:16.58#ibcon#about to read 5, iclass 33, count 0 2006.285.16:24:16.58#ibcon#read 5, iclass 33, count 0 2006.285.16:24:16.58#ibcon#about to read 6, iclass 33, count 0 2006.285.16:24:16.58#ibcon#read 6, iclass 33, count 0 2006.285.16:24:16.58#ibcon#end of sib2, iclass 33, count 0 2006.285.16:24:16.58#ibcon#*after write, iclass 33, count 0 2006.285.16:24:16.58#ibcon#*before return 0, iclass 33, count 0 2006.285.16:24:16.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:24:16.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:24:16.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.16:24:16.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.16:24:16.58$vck44/vb=1,4 2006.285.16:24:16.58#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.16:24:16.58#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.16:24:16.58#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:16.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:24:16.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:24:16.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:24:16.58#ibcon#enter wrdev, iclass 35, count 2 2006.285.16:24:16.58#ibcon#first serial, iclass 35, count 2 2006.285.16:24:16.58#ibcon#enter sib2, iclass 35, count 2 2006.285.16:24:16.58#ibcon#flushed, iclass 35, count 2 2006.285.16:24:16.58#ibcon#about to write, iclass 35, count 2 2006.285.16:24:16.58#ibcon#wrote, iclass 35, count 2 2006.285.16:24:16.58#ibcon#about to read 3, iclass 35, count 2 2006.285.16:24:16.60#ibcon#read 3, iclass 35, count 2 2006.285.16:24:16.60#ibcon#about to read 4, iclass 35, count 2 2006.285.16:24:16.60#ibcon#read 4, iclass 35, count 2 2006.285.16:24:16.60#ibcon#about to read 5, iclass 35, count 2 2006.285.16:24:16.60#ibcon#read 5, iclass 35, count 2 2006.285.16:24:16.60#ibcon#about to read 6, iclass 35, count 2 2006.285.16:24:16.60#ibcon#read 6, iclass 35, count 2 2006.285.16:24:16.60#ibcon#end of sib2, iclass 35, count 2 2006.285.16:24:16.60#ibcon#*mode == 0, iclass 35, count 2 2006.285.16:24:16.60#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.16:24:16.60#ibcon#[27=AT01-04\r\n] 2006.285.16:24:16.60#ibcon#*before write, iclass 35, count 2 2006.285.16:24:16.60#ibcon#enter sib2, iclass 35, count 2 2006.285.16:24:16.60#ibcon#flushed, iclass 35, count 2 2006.285.16:24:16.60#ibcon#about to write, iclass 35, count 2 2006.285.16:24:16.60#ibcon#wrote, iclass 35, count 2 2006.285.16:24:16.60#ibcon#about to read 3, iclass 35, count 2 2006.285.16:24:16.63#ibcon#read 3, iclass 35, count 2 2006.285.16:24:16.63#ibcon#about to read 4, iclass 35, count 2 2006.285.16:24:16.63#ibcon#read 4, iclass 35, count 2 2006.285.16:24:16.63#ibcon#about to read 5, iclass 35, count 2 2006.285.16:24:16.63#ibcon#read 5, iclass 35, count 2 2006.285.16:24:16.63#ibcon#about to read 6, iclass 35, count 2 2006.285.16:24:16.63#ibcon#read 6, iclass 35, count 2 2006.285.16:24:16.63#ibcon#end of sib2, iclass 35, count 2 2006.285.16:24:16.63#ibcon#*after write, iclass 35, count 2 2006.285.16:24:16.63#ibcon#*before return 0, iclass 35, count 2 2006.285.16:24:16.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:24:16.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:24:16.63#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.16:24:16.63#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:16.63#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:24:16.75#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:24:16.75#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:24:16.75#ibcon#enter wrdev, iclass 35, count 0 2006.285.16:24:16.75#ibcon#first serial, iclass 35, count 0 2006.285.16:24:16.75#ibcon#enter sib2, iclass 35, count 0 2006.285.16:24:16.75#ibcon#flushed, iclass 35, count 0 2006.285.16:24:16.75#ibcon#about to write, iclass 35, count 0 2006.285.16:24:16.75#ibcon#wrote, iclass 35, count 0 2006.285.16:24:16.75#ibcon#about to read 3, iclass 35, count 0 2006.285.16:24:16.77#ibcon#read 3, iclass 35, count 0 2006.285.16:24:16.77#ibcon#about to read 4, iclass 35, count 0 2006.285.16:24:16.77#ibcon#read 4, iclass 35, count 0 2006.285.16:24:16.77#ibcon#about to read 5, iclass 35, count 0 2006.285.16:24:16.77#ibcon#read 5, iclass 35, count 0 2006.285.16:24:16.77#ibcon#about to read 6, iclass 35, count 0 2006.285.16:24:16.77#ibcon#read 6, iclass 35, count 0 2006.285.16:24:16.77#ibcon#end of sib2, iclass 35, count 0 2006.285.16:24:16.77#ibcon#*mode == 0, iclass 35, count 0 2006.285.16:24:16.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.16:24:16.77#ibcon#[27=USB\r\n] 2006.285.16:24:16.77#ibcon#*before write, iclass 35, count 0 2006.285.16:24:16.77#ibcon#enter sib2, iclass 35, count 0 2006.285.16:24:16.77#ibcon#flushed, iclass 35, count 0 2006.285.16:24:16.77#ibcon#about to write, iclass 35, count 0 2006.285.16:24:16.77#ibcon#wrote, iclass 35, count 0 2006.285.16:24:16.77#ibcon#about to read 3, iclass 35, count 0 2006.285.16:24:16.80#ibcon#read 3, iclass 35, count 0 2006.285.16:24:16.80#ibcon#about to read 4, iclass 35, count 0 2006.285.16:24:16.80#ibcon#read 4, iclass 35, count 0 2006.285.16:24:16.80#ibcon#about to read 5, iclass 35, count 0 2006.285.16:24:16.80#ibcon#read 5, iclass 35, count 0 2006.285.16:24:16.80#ibcon#about to read 6, iclass 35, count 0 2006.285.16:24:16.80#ibcon#read 6, iclass 35, count 0 2006.285.16:24:16.80#ibcon#end of sib2, iclass 35, count 0 2006.285.16:24:16.80#ibcon#*after write, iclass 35, count 0 2006.285.16:24:16.80#ibcon#*before return 0, iclass 35, count 0 2006.285.16:24:16.80#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:24:16.80#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:24:16.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.16:24:16.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.16:24:16.80$vck44/vblo=2,634.99 2006.285.16:24:16.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.16:24:16.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.16:24:16.80#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:16.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:24:16.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:24:16.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:24:16.80#ibcon#enter wrdev, iclass 37, count 0 2006.285.16:24:16.80#ibcon#first serial, iclass 37, count 0 2006.285.16:24:16.80#ibcon#enter sib2, iclass 37, count 0 2006.285.16:24:16.80#ibcon#flushed, iclass 37, count 0 2006.285.16:24:16.80#ibcon#about to write, iclass 37, count 0 2006.285.16:24:16.80#ibcon#wrote, iclass 37, count 0 2006.285.16:24:16.80#ibcon#about to read 3, iclass 37, count 0 2006.285.16:24:16.82#ibcon#read 3, iclass 37, count 0 2006.285.16:24:16.83#ibcon#about to read 4, iclass 37, count 0 2006.285.16:24:16.83#ibcon#read 4, iclass 37, count 0 2006.285.16:24:16.83#ibcon#about to read 5, iclass 37, count 0 2006.285.16:24:16.83#ibcon#read 5, iclass 37, count 0 2006.285.16:24:16.83#ibcon#about to read 6, iclass 37, count 0 2006.285.16:24:16.83#ibcon#read 6, iclass 37, count 0 2006.285.16:24:16.83#ibcon#end of sib2, iclass 37, count 0 2006.285.16:24:16.83#ibcon#*mode == 0, iclass 37, count 0 2006.285.16:24:16.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.16:24:16.83#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.16:24:16.83#ibcon#*before write, iclass 37, count 0 2006.285.16:24:16.83#ibcon#enter sib2, iclass 37, count 0 2006.285.16:24:16.83#ibcon#flushed, iclass 37, count 0 2006.285.16:24:16.83#ibcon#about to write, iclass 37, count 0 2006.285.16:24:16.83#ibcon#wrote, iclass 37, count 0 2006.285.16:24:16.83#ibcon#about to read 3, iclass 37, count 0 2006.285.16:24:16.88#ibcon#read 3, iclass 37, count 0 2006.285.16:24:16.88#ibcon#about to read 4, iclass 37, count 0 2006.285.16:24:16.88#ibcon#read 4, iclass 37, count 0 2006.285.16:24:16.88#ibcon#about to read 5, iclass 37, count 0 2006.285.16:24:16.88#ibcon#read 5, iclass 37, count 0 2006.285.16:24:16.88#ibcon#about to read 6, iclass 37, count 0 2006.285.16:24:16.88#ibcon#read 6, iclass 37, count 0 2006.285.16:24:16.88#ibcon#end of sib2, iclass 37, count 0 2006.285.16:24:16.88#ibcon#*after write, iclass 37, count 0 2006.285.16:24:16.88#ibcon#*before return 0, iclass 37, count 0 2006.285.16:24:16.88#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:24:16.88#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:24:16.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.16:24:16.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.16:24:16.88$vck44/vb=2,5 2006.285.16:24:16.88#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.16:24:16.88#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.16:24:16.88#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:16.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:24:16.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:24:16.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:24:16.92#ibcon#enter wrdev, iclass 39, count 2 2006.285.16:24:16.92#ibcon#first serial, iclass 39, count 2 2006.285.16:24:16.92#ibcon#enter sib2, iclass 39, count 2 2006.285.16:24:16.92#ibcon#flushed, iclass 39, count 2 2006.285.16:24:16.92#ibcon#about to write, iclass 39, count 2 2006.285.16:24:16.92#ibcon#wrote, iclass 39, count 2 2006.285.16:24:16.92#ibcon#about to read 3, iclass 39, count 2 2006.285.16:24:16.94#ibcon#read 3, iclass 39, count 2 2006.285.16:24:16.94#ibcon#about to read 4, iclass 39, count 2 2006.285.16:24:16.94#ibcon#read 4, iclass 39, count 2 2006.285.16:24:16.94#ibcon#about to read 5, iclass 39, count 2 2006.285.16:24:16.94#ibcon#read 5, iclass 39, count 2 2006.285.16:24:16.94#ibcon#about to read 6, iclass 39, count 2 2006.285.16:24:16.94#ibcon#read 6, iclass 39, count 2 2006.285.16:24:16.94#ibcon#end of sib2, iclass 39, count 2 2006.285.16:24:16.94#ibcon#*mode == 0, iclass 39, count 2 2006.285.16:24:16.94#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.16:24:16.94#ibcon#[27=AT02-05\r\n] 2006.285.16:24:16.94#ibcon#*before write, iclass 39, count 2 2006.285.16:24:16.94#ibcon#enter sib2, iclass 39, count 2 2006.285.16:24:16.94#ibcon#flushed, iclass 39, count 2 2006.285.16:24:16.94#ibcon#about to write, iclass 39, count 2 2006.285.16:24:16.94#ibcon#wrote, iclass 39, count 2 2006.285.16:24:16.94#ibcon#about to read 3, iclass 39, count 2 2006.285.16:24:16.97#ibcon#read 3, iclass 39, count 2 2006.285.16:24:16.97#ibcon#about to read 4, iclass 39, count 2 2006.285.16:24:16.97#ibcon#read 4, iclass 39, count 2 2006.285.16:24:16.97#ibcon#about to read 5, iclass 39, count 2 2006.285.16:24:16.97#ibcon#read 5, iclass 39, count 2 2006.285.16:24:16.97#ibcon#about to read 6, iclass 39, count 2 2006.285.16:24:16.97#ibcon#read 6, iclass 39, count 2 2006.285.16:24:16.97#ibcon#end of sib2, iclass 39, count 2 2006.285.16:24:16.97#ibcon#*after write, iclass 39, count 2 2006.285.16:24:16.97#ibcon#*before return 0, iclass 39, count 2 2006.285.16:24:16.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:24:16.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:24:16.97#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.16:24:16.97#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:16.97#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:24:17.09#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:24:17.09#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:24:17.09#ibcon#enter wrdev, iclass 39, count 0 2006.285.16:24:17.09#ibcon#first serial, iclass 39, count 0 2006.285.16:24:17.09#ibcon#enter sib2, iclass 39, count 0 2006.285.16:24:17.09#ibcon#flushed, iclass 39, count 0 2006.285.16:24:17.09#ibcon#about to write, iclass 39, count 0 2006.285.16:24:17.09#ibcon#wrote, iclass 39, count 0 2006.285.16:24:17.09#ibcon#about to read 3, iclass 39, count 0 2006.285.16:24:17.11#ibcon#read 3, iclass 39, count 0 2006.285.16:24:17.11#ibcon#about to read 4, iclass 39, count 0 2006.285.16:24:17.11#ibcon#read 4, iclass 39, count 0 2006.285.16:24:17.11#ibcon#about to read 5, iclass 39, count 0 2006.285.16:24:17.11#ibcon#read 5, iclass 39, count 0 2006.285.16:24:17.11#ibcon#about to read 6, iclass 39, count 0 2006.285.16:24:17.11#ibcon#read 6, iclass 39, count 0 2006.285.16:24:17.11#ibcon#end of sib2, iclass 39, count 0 2006.285.16:24:17.11#ibcon#*mode == 0, iclass 39, count 0 2006.285.16:24:17.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.16:24:17.11#ibcon#[27=USB\r\n] 2006.285.16:24:17.11#ibcon#*before write, iclass 39, count 0 2006.285.16:24:17.11#ibcon#enter sib2, iclass 39, count 0 2006.285.16:24:17.11#ibcon#flushed, iclass 39, count 0 2006.285.16:24:17.11#ibcon#about to write, iclass 39, count 0 2006.285.16:24:17.11#ibcon#wrote, iclass 39, count 0 2006.285.16:24:17.11#ibcon#about to read 3, iclass 39, count 0 2006.285.16:24:17.14#ibcon#read 3, iclass 39, count 0 2006.285.16:24:17.14#ibcon#about to read 4, iclass 39, count 0 2006.285.16:24:17.14#ibcon#read 4, iclass 39, count 0 2006.285.16:24:17.14#ibcon#about to read 5, iclass 39, count 0 2006.285.16:24:17.14#ibcon#read 5, iclass 39, count 0 2006.285.16:24:17.14#ibcon#about to read 6, iclass 39, count 0 2006.285.16:24:17.14#ibcon#read 6, iclass 39, count 0 2006.285.16:24:17.14#ibcon#end of sib2, iclass 39, count 0 2006.285.16:24:17.14#ibcon#*after write, iclass 39, count 0 2006.285.16:24:17.14#ibcon#*before return 0, iclass 39, count 0 2006.285.16:24:17.14#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:24:17.14#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:24:17.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.16:24:17.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.16:24:17.14$vck44/vblo=3,649.99 2006.285.16:24:17.14#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.16:24:17.14#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.16:24:17.14#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:17.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:24:17.14#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:24:17.14#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:24:17.14#ibcon#enter wrdev, iclass 3, count 0 2006.285.16:24:17.14#ibcon#first serial, iclass 3, count 0 2006.285.16:24:17.14#ibcon#enter sib2, iclass 3, count 0 2006.285.16:24:17.14#ibcon#flushed, iclass 3, count 0 2006.285.16:24:17.14#ibcon#about to write, iclass 3, count 0 2006.285.16:24:17.14#ibcon#wrote, iclass 3, count 0 2006.285.16:24:17.14#ibcon#about to read 3, iclass 3, count 0 2006.285.16:24:17.16#ibcon#read 3, iclass 3, count 0 2006.285.16:24:17.16#ibcon#about to read 4, iclass 3, count 0 2006.285.16:24:17.16#ibcon#read 4, iclass 3, count 0 2006.285.16:24:17.16#ibcon#about to read 5, iclass 3, count 0 2006.285.16:24:17.16#ibcon#read 5, iclass 3, count 0 2006.285.16:24:17.16#ibcon#about to read 6, iclass 3, count 0 2006.285.16:24:17.16#ibcon#read 6, iclass 3, count 0 2006.285.16:24:17.16#ibcon#end of sib2, iclass 3, count 0 2006.285.16:24:17.16#ibcon#*mode == 0, iclass 3, count 0 2006.285.16:24:17.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.16:24:17.16#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.16:24:17.16#ibcon#*before write, iclass 3, count 0 2006.285.16:24:17.16#ibcon#enter sib2, iclass 3, count 0 2006.285.16:24:17.16#ibcon#flushed, iclass 3, count 0 2006.285.16:24:17.16#ibcon#about to write, iclass 3, count 0 2006.285.16:24:17.16#ibcon#wrote, iclass 3, count 0 2006.285.16:24:17.16#ibcon#about to read 3, iclass 3, count 0 2006.285.16:24:17.20#ibcon#read 3, iclass 3, count 0 2006.285.16:24:17.20#ibcon#about to read 4, iclass 3, count 0 2006.285.16:24:17.20#ibcon#read 4, iclass 3, count 0 2006.285.16:24:17.20#ibcon#about to read 5, iclass 3, count 0 2006.285.16:24:17.20#ibcon#read 5, iclass 3, count 0 2006.285.16:24:17.20#ibcon#about to read 6, iclass 3, count 0 2006.285.16:24:17.20#ibcon#read 6, iclass 3, count 0 2006.285.16:24:17.20#ibcon#end of sib2, iclass 3, count 0 2006.285.16:24:17.20#ibcon#*after write, iclass 3, count 0 2006.285.16:24:17.20#ibcon#*before return 0, iclass 3, count 0 2006.285.16:24:17.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:24:17.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:24:17.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.16:24:17.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.16:24:17.20$vck44/vb=3,4 2006.285.16:24:17.20#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.16:24:17.20#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.16:24:17.20#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:17.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:24:17.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:24:17.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:24:17.26#ibcon#enter wrdev, iclass 5, count 2 2006.285.16:24:17.26#ibcon#first serial, iclass 5, count 2 2006.285.16:24:17.26#ibcon#enter sib2, iclass 5, count 2 2006.285.16:24:17.26#ibcon#flushed, iclass 5, count 2 2006.285.16:24:17.26#ibcon#about to write, iclass 5, count 2 2006.285.16:24:17.26#ibcon#wrote, iclass 5, count 2 2006.285.16:24:17.26#ibcon#about to read 3, iclass 5, count 2 2006.285.16:24:17.28#ibcon#read 3, iclass 5, count 2 2006.285.16:24:17.28#ibcon#about to read 4, iclass 5, count 2 2006.285.16:24:17.28#ibcon#read 4, iclass 5, count 2 2006.285.16:24:17.28#ibcon#about to read 5, iclass 5, count 2 2006.285.16:24:17.28#ibcon#read 5, iclass 5, count 2 2006.285.16:24:17.28#ibcon#about to read 6, iclass 5, count 2 2006.285.16:24:17.28#ibcon#read 6, iclass 5, count 2 2006.285.16:24:17.28#ibcon#end of sib2, iclass 5, count 2 2006.285.16:24:17.28#ibcon#*mode == 0, iclass 5, count 2 2006.285.16:24:17.28#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.16:24:17.28#ibcon#[27=AT03-04\r\n] 2006.285.16:24:17.28#ibcon#*before write, iclass 5, count 2 2006.285.16:24:17.28#ibcon#enter sib2, iclass 5, count 2 2006.285.16:24:17.28#ibcon#flushed, iclass 5, count 2 2006.285.16:24:17.28#ibcon#about to write, iclass 5, count 2 2006.285.16:24:17.28#ibcon#wrote, iclass 5, count 2 2006.285.16:24:17.28#ibcon#about to read 3, iclass 5, count 2 2006.285.16:24:17.31#ibcon#read 3, iclass 5, count 2 2006.285.16:24:17.31#ibcon#about to read 4, iclass 5, count 2 2006.285.16:24:17.31#ibcon#read 4, iclass 5, count 2 2006.285.16:24:17.31#ibcon#about to read 5, iclass 5, count 2 2006.285.16:24:17.31#ibcon#read 5, iclass 5, count 2 2006.285.16:24:17.31#ibcon#about to read 6, iclass 5, count 2 2006.285.16:24:17.31#ibcon#read 6, iclass 5, count 2 2006.285.16:24:17.31#ibcon#end of sib2, iclass 5, count 2 2006.285.16:24:17.31#ibcon#*after write, iclass 5, count 2 2006.285.16:24:17.31#ibcon#*before return 0, iclass 5, count 2 2006.285.16:24:17.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:24:17.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:24:17.31#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.16:24:17.31#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:17.31#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:24:17.43#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:24:17.43#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:24:17.43#ibcon#enter wrdev, iclass 5, count 0 2006.285.16:24:17.43#ibcon#first serial, iclass 5, count 0 2006.285.16:24:17.43#ibcon#enter sib2, iclass 5, count 0 2006.285.16:24:17.43#ibcon#flushed, iclass 5, count 0 2006.285.16:24:17.43#ibcon#about to write, iclass 5, count 0 2006.285.16:24:17.43#ibcon#wrote, iclass 5, count 0 2006.285.16:24:17.43#ibcon#about to read 3, iclass 5, count 0 2006.285.16:24:17.45#ibcon#read 3, iclass 5, count 0 2006.285.16:24:17.45#ibcon#about to read 4, iclass 5, count 0 2006.285.16:24:17.45#ibcon#read 4, iclass 5, count 0 2006.285.16:24:17.45#ibcon#about to read 5, iclass 5, count 0 2006.285.16:24:17.45#ibcon#read 5, iclass 5, count 0 2006.285.16:24:17.45#ibcon#about to read 6, iclass 5, count 0 2006.285.16:24:17.45#ibcon#read 6, iclass 5, count 0 2006.285.16:24:17.45#ibcon#end of sib2, iclass 5, count 0 2006.285.16:24:17.45#ibcon#*mode == 0, iclass 5, count 0 2006.285.16:24:17.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.16:24:17.45#ibcon#[27=USB\r\n] 2006.285.16:24:17.45#ibcon#*before write, iclass 5, count 0 2006.285.16:24:17.45#ibcon#enter sib2, iclass 5, count 0 2006.285.16:24:17.45#ibcon#flushed, iclass 5, count 0 2006.285.16:24:17.45#ibcon#about to write, iclass 5, count 0 2006.285.16:24:17.45#ibcon#wrote, iclass 5, count 0 2006.285.16:24:17.45#ibcon#about to read 3, iclass 5, count 0 2006.285.16:24:17.48#ibcon#read 3, iclass 5, count 0 2006.285.16:24:17.48#ibcon#about to read 4, iclass 5, count 0 2006.285.16:24:17.48#ibcon#read 4, iclass 5, count 0 2006.285.16:24:17.48#ibcon#about to read 5, iclass 5, count 0 2006.285.16:24:17.48#ibcon#read 5, iclass 5, count 0 2006.285.16:24:17.48#ibcon#about to read 6, iclass 5, count 0 2006.285.16:24:17.48#ibcon#read 6, iclass 5, count 0 2006.285.16:24:17.48#ibcon#end of sib2, iclass 5, count 0 2006.285.16:24:17.48#ibcon#*after write, iclass 5, count 0 2006.285.16:24:17.48#ibcon#*before return 0, iclass 5, count 0 2006.285.16:24:17.48#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:24:17.48#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:24:17.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.16:24:17.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.16:24:17.48$vck44/vblo=4,679.99 2006.285.16:24:17.48#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.16:24:17.48#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.16:24:17.48#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:17.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:24:17.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:24:17.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:24:17.48#ibcon#enter wrdev, iclass 7, count 0 2006.285.16:24:17.48#ibcon#first serial, iclass 7, count 0 2006.285.16:24:17.48#ibcon#enter sib2, iclass 7, count 0 2006.285.16:24:17.48#ibcon#flushed, iclass 7, count 0 2006.285.16:24:17.48#ibcon#about to write, iclass 7, count 0 2006.285.16:24:17.48#ibcon#wrote, iclass 7, count 0 2006.285.16:24:17.48#ibcon#about to read 3, iclass 7, count 0 2006.285.16:24:17.50#ibcon#read 3, iclass 7, count 0 2006.285.16:24:17.50#ibcon#about to read 4, iclass 7, count 0 2006.285.16:24:17.50#ibcon#read 4, iclass 7, count 0 2006.285.16:24:17.50#ibcon#about to read 5, iclass 7, count 0 2006.285.16:24:17.50#ibcon#read 5, iclass 7, count 0 2006.285.16:24:17.50#ibcon#about to read 6, iclass 7, count 0 2006.285.16:24:17.50#ibcon#read 6, iclass 7, count 0 2006.285.16:24:17.50#ibcon#end of sib2, iclass 7, count 0 2006.285.16:24:17.50#ibcon#*mode == 0, iclass 7, count 0 2006.285.16:24:17.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.16:24:17.50#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.16:24:17.50#ibcon#*before write, iclass 7, count 0 2006.285.16:24:17.50#ibcon#enter sib2, iclass 7, count 0 2006.285.16:24:17.50#ibcon#flushed, iclass 7, count 0 2006.285.16:24:17.50#ibcon#about to write, iclass 7, count 0 2006.285.16:24:17.50#ibcon#wrote, iclass 7, count 0 2006.285.16:24:17.50#ibcon#about to read 3, iclass 7, count 0 2006.285.16:24:17.54#ibcon#read 3, iclass 7, count 0 2006.285.16:24:17.54#ibcon#about to read 4, iclass 7, count 0 2006.285.16:24:17.54#ibcon#read 4, iclass 7, count 0 2006.285.16:24:17.54#ibcon#about to read 5, iclass 7, count 0 2006.285.16:24:17.54#ibcon#read 5, iclass 7, count 0 2006.285.16:24:17.54#ibcon#about to read 6, iclass 7, count 0 2006.285.16:24:17.54#ibcon#read 6, iclass 7, count 0 2006.285.16:24:17.54#ibcon#end of sib2, iclass 7, count 0 2006.285.16:24:17.54#ibcon#*after write, iclass 7, count 0 2006.285.16:24:17.54#ibcon#*before return 0, iclass 7, count 0 2006.285.16:24:17.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:24:17.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:24:17.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.16:24:17.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.16:24:17.54$vck44/vb=4,5 2006.285.16:24:17.54#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.16:24:17.54#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.16:24:17.54#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:17.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:24:17.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:24:17.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:24:17.60#ibcon#enter wrdev, iclass 11, count 2 2006.285.16:24:17.60#ibcon#first serial, iclass 11, count 2 2006.285.16:24:17.60#ibcon#enter sib2, iclass 11, count 2 2006.285.16:24:17.60#ibcon#flushed, iclass 11, count 2 2006.285.16:24:17.60#ibcon#about to write, iclass 11, count 2 2006.285.16:24:17.60#ibcon#wrote, iclass 11, count 2 2006.285.16:24:17.60#ibcon#about to read 3, iclass 11, count 2 2006.285.16:24:17.62#ibcon#read 3, iclass 11, count 2 2006.285.16:24:17.62#ibcon#about to read 4, iclass 11, count 2 2006.285.16:24:17.62#ibcon#read 4, iclass 11, count 2 2006.285.16:24:17.62#ibcon#about to read 5, iclass 11, count 2 2006.285.16:24:17.62#ibcon#read 5, iclass 11, count 2 2006.285.16:24:17.62#ibcon#about to read 6, iclass 11, count 2 2006.285.16:24:17.62#ibcon#read 6, iclass 11, count 2 2006.285.16:24:17.62#ibcon#end of sib2, iclass 11, count 2 2006.285.16:24:17.62#ibcon#*mode == 0, iclass 11, count 2 2006.285.16:24:17.62#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.16:24:17.62#ibcon#[27=AT04-05\r\n] 2006.285.16:24:17.62#ibcon#*before write, iclass 11, count 2 2006.285.16:24:17.62#ibcon#enter sib2, iclass 11, count 2 2006.285.16:24:17.62#ibcon#flushed, iclass 11, count 2 2006.285.16:24:17.62#ibcon#about to write, iclass 11, count 2 2006.285.16:24:17.62#ibcon#wrote, iclass 11, count 2 2006.285.16:24:17.62#ibcon#about to read 3, iclass 11, count 2 2006.285.16:24:17.65#ibcon#read 3, iclass 11, count 2 2006.285.16:24:17.65#ibcon#about to read 4, iclass 11, count 2 2006.285.16:24:17.65#ibcon#read 4, iclass 11, count 2 2006.285.16:24:17.65#ibcon#about to read 5, iclass 11, count 2 2006.285.16:24:17.65#ibcon#read 5, iclass 11, count 2 2006.285.16:24:17.65#ibcon#about to read 6, iclass 11, count 2 2006.285.16:24:17.65#ibcon#read 6, iclass 11, count 2 2006.285.16:24:17.65#ibcon#end of sib2, iclass 11, count 2 2006.285.16:24:17.65#ibcon#*after write, iclass 11, count 2 2006.285.16:24:17.65#ibcon#*before return 0, iclass 11, count 2 2006.285.16:24:17.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:24:17.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:24:17.65#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.16:24:17.65#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:17.65#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:24:17.77#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:24:17.77#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:24:17.77#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:24:17.77#ibcon#first serial, iclass 11, count 0 2006.285.16:24:17.77#ibcon#enter sib2, iclass 11, count 0 2006.285.16:24:17.77#ibcon#flushed, iclass 11, count 0 2006.285.16:24:17.77#ibcon#about to write, iclass 11, count 0 2006.285.16:24:17.77#ibcon#wrote, iclass 11, count 0 2006.285.16:24:17.77#ibcon#about to read 3, iclass 11, count 0 2006.285.16:24:17.79#ibcon#read 3, iclass 11, count 0 2006.285.16:24:17.79#ibcon#about to read 4, iclass 11, count 0 2006.285.16:24:17.79#ibcon#read 4, iclass 11, count 0 2006.285.16:24:17.79#ibcon#about to read 5, iclass 11, count 0 2006.285.16:24:17.79#ibcon#read 5, iclass 11, count 0 2006.285.16:24:17.79#ibcon#about to read 6, iclass 11, count 0 2006.285.16:24:17.79#ibcon#read 6, iclass 11, count 0 2006.285.16:24:17.79#ibcon#end of sib2, iclass 11, count 0 2006.285.16:24:17.79#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:24:17.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:24:17.79#ibcon#[27=USB\r\n] 2006.285.16:24:17.79#ibcon#*before write, iclass 11, count 0 2006.285.16:24:17.79#ibcon#enter sib2, iclass 11, count 0 2006.285.16:24:17.79#ibcon#flushed, iclass 11, count 0 2006.285.16:24:17.79#ibcon#about to write, iclass 11, count 0 2006.285.16:24:17.79#ibcon#wrote, iclass 11, count 0 2006.285.16:24:17.79#ibcon#about to read 3, iclass 11, count 0 2006.285.16:24:17.82#ibcon#read 3, iclass 11, count 0 2006.285.16:24:17.82#ibcon#about to read 4, iclass 11, count 0 2006.285.16:24:17.82#ibcon#read 4, iclass 11, count 0 2006.285.16:24:17.82#ibcon#about to read 5, iclass 11, count 0 2006.285.16:24:17.82#ibcon#read 5, iclass 11, count 0 2006.285.16:24:17.82#ibcon#about to read 6, iclass 11, count 0 2006.285.16:24:17.82#ibcon#read 6, iclass 11, count 0 2006.285.16:24:17.82#ibcon#end of sib2, iclass 11, count 0 2006.285.16:24:17.82#ibcon#*after write, iclass 11, count 0 2006.285.16:24:17.82#ibcon#*before return 0, iclass 11, count 0 2006.285.16:24:17.82#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:24:17.82#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:24:17.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:24:17.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:24:17.82$vck44/vblo=5,709.99 2006.285.16:24:17.84#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.16:24:17.84#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.16:24:17.84#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:17.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:24:17.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:24:17.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:24:17.84#ibcon#enter wrdev, iclass 13, count 0 2006.285.16:24:17.84#ibcon#first serial, iclass 13, count 0 2006.285.16:24:17.84#ibcon#enter sib2, iclass 13, count 0 2006.285.16:24:17.84#ibcon#flushed, iclass 13, count 0 2006.285.16:24:17.84#ibcon#about to write, iclass 13, count 0 2006.285.16:24:17.84#ibcon#wrote, iclass 13, count 0 2006.285.16:24:17.84#ibcon#about to read 3, iclass 13, count 0 2006.285.16:24:17.86#ibcon#read 3, iclass 13, count 0 2006.285.16:24:17.86#ibcon#about to read 4, iclass 13, count 0 2006.285.16:24:17.86#ibcon#read 4, iclass 13, count 0 2006.285.16:24:17.86#ibcon#about to read 5, iclass 13, count 0 2006.285.16:24:17.86#ibcon#read 5, iclass 13, count 0 2006.285.16:24:17.86#ibcon#about to read 6, iclass 13, count 0 2006.285.16:24:17.86#ibcon#read 6, iclass 13, count 0 2006.285.16:24:17.86#ibcon#end of sib2, iclass 13, count 0 2006.285.16:24:17.86#ibcon#*mode == 0, iclass 13, count 0 2006.285.16:24:17.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.16:24:17.86#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.16:24:17.86#ibcon#*before write, iclass 13, count 0 2006.285.16:24:17.86#ibcon#enter sib2, iclass 13, count 0 2006.285.16:24:17.86#ibcon#flushed, iclass 13, count 0 2006.285.16:24:17.86#ibcon#about to write, iclass 13, count 0 2006.285.16:24:17.86#ibcon#wrote, iclass 13, count 0 2006.285.16:24:17.86#ibcon#about to read 3, iclass 13, count 0 2006.285.16:24:17.90#ibcon#read 3, iclass 13, count 0 2006.285.16:24:17.90#ibcon#about to read 4, iclass 13, count 0 2006.285.16:24:17.90#ibcon#read 4, iclass 13, count 0 2006.285.16:24:17.90#ibcon#about to read 5, iclass 13, count 0 2006.285.16:24:17.90#ibcon#read 5, iclass 13, count 0 2006.285.16:24:17.90#ibcon#about to read 6, iclass 13, count 0 2006.285.16:24:17.90#ibcon#read 6, iclass 13, count 0 2006.285.16:24:17.90#ibcon#end of sib2, iclass 13, count 0 2006.285.16:24:17.90#ibcon#*after write, iclass 13, count 0 2006.285.16:24:17.90#ibcon#*before return 0, iclass 13, count 0 2006.285.16:24:17.90#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:24:17.90#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:24:17.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.16:24:17.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.16:24:17.90$vck44/vb=5,4 2006.285.16:24:17.90#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.16:24:17.90#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.16:24:17.90#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:17.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:24:17.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:24:17.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:24:17.94#ibcon#enter wrdev, iclass 15, count 2 2006.285.16:24:17.94#ibcon#first serial, iclass 15, count 2 2006.285.16:24:17.94#ibcon#enter sib2, iclass 15, count 2 2006.285.16:24:17.94#ibcon#flushed, iclass 15, count 2 2006.285.16:24:17.94#ibcon#about to write, iclass 15, count 2 2006.285.16:24:17.94#ibcon#wrote, iclass 15, count 2 2006.285.16:24:17.94#ibcon#about to read 3, iclass 15, count 2 2006.285.16:24:17.96#ibcon#read 3, iclass 15, count 2 2006.285.16:24:17.96#ibcon#about to read 4, iclass 15, count 2 2006.285.16:24:17.96#ibcon#read 4, iclass 15, count 2 2006.285.16:24:17.96#ibcon#about to read 5, iclass 15, count 2 2006.285.16:24:17.96#ibcon#read 5, iclass 15, count 2 2006.285.16:24:17.96#ibcon#about to read 6, iclass 15, count 2 2006.285.16:24:17.96#ibcon#read 6, iclass 15, count 2 2006.285.16:24:17.96#ibcon#end of sib2, iclass 15, count 2 2006.285.16:24:17.96#ibcon#*mode == 0, iclass 15, count 2 2006.285.16:24:17.96#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.16:24:17.96#ibcon#[27=AT05-04\r\n] 2006.285.16:24:17.96#ibcon#*before write, iclass 15, count 2 2006.285.16:24:17.96#ibcon#enter sib2, iclass 15, count 2 2006.285.16:24:17.96#ibcon#flushed, iclass 15, count 2 2006.285.16:24:17.96#ibcon#about to write, iclass 15, count 2 2006.285.16:24:17.96#ibcon#wrote, iclass 15, count 2 2006.285.16:24:17.96#ibcon#about to read 3, iclass 15, count 2 2006.285.16:24:17.99#ibcon#read 3, iclass 15, count 2 2006.285.16:24:17.99#ibcon#about to read 4, iclass 15, count 2 2006.285.16:24:17.99#ibcon#read 4, iclass 15, count 2 2006.285.16:24:17.99#ibcon#about to read 5, iclass 15, count 2 2006.285.16:24:17.99#ibcon#read 5, iclass 15, count 2 2006.285.16:24:17.99#ibcon#about to read 6, iclass 15, count 2 2006.285.16:24:17.99#ibcon#read 6, iclass 15, count 2 2006.285.16:24:17.99#ibcon#end of sib2, iclass 15, count 2 2006.285.16:24:17.99#ibcon#*after write, iclass 15, count 2 2006.285.16:24:17.99#ibcon#*before return 0, iclass 15, count 2 2006.285.16:24:17.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:24:17.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:24:17.99#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.16:24:17.99#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:17.99#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:24:18.11#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:24:18.11#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:24:18.11#ibcon#enter wrdev, iclass 15, count 0 2006.285.16:24:18.11#ibcon#first serial, iclass 15, count 0 2006.285.16:24:18.11#ibcon#enter sib2, iclass 15, count 0 2006.285.16:24:18.11#ibcon#flushed, iclass 15, count 0 2006.285.16:24:18.11#ibcon#about to write, iclass 15, count 0 2006.285.16:24:18.11#ibcon#wrote, iclass 15, count 0 2006.285.16:24:18.11#ibcon#about to read 3, iclass 15, count 0 2006.285.16:24:18.13#ibcon#read 3, iclass 15, count 0 2006.285.16:24:18.13#ibcon#about to read 4, iclass 15, count 0 2006.285.16:24:18.13#ibcon#read 4, iclass 15, count 0 2006.285.16:24:18.13#ibcon#about to read 5, iclass 15, count 0 2006.285.16:24:18.13#ibcon#read 5, iclass 15, count 0 2006.285.16:24:18.13#ibcon#about to read 6, iclass 15, count 0 2006.285.16:24:18.13#ibcon#read 6, iclass 15, count 0 2006.285.16:24:18.13#ibcon#end of sib2, iclass 15, count 0 2006.285.16:24:18.13#ibcon#*mode == 0, iclass 15, count 0 2006.285.16:24:18.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.16:24:18.13#ibcon#[27=USB\r\n] 2006.285.16:24:18.13#ibcon#*before write, iclass 15, count 0 2006.285.16:24:18.13#ibcon#enter sib2, iclass 15, count 0 2006.285.16:24:18.13#ibcon#flushed, iclass 15, count 0 2006.285.16:24:18.13#ibcon#about to write, iclass 15, count 0 2006.285.16:24:18.13#ibcon#wrote, iclass 15, count 0 2006.285.16:24:18.13#ibcon#about to read 3, iclass 15, count 0 2006.285.16:24:18.16#ibcon#read 3, iclass 15, count 0 2006.285.16:24:18.16#ibcon#about to read 4, iclass 15, count 0 2006.285.16:24:18.16#ibcon#read 4, iclass 15, count 0 2006.285.16:24:18.16#ibcon#about to read 5, iclass 15, count 0 2006.285.16:24:18.16#ibcon#read 5, iclass 15, count 0 2006.285.16:24:18.16#ibcon#about to read 6, iclass 15, count 0 2006.285.16:24:18.16#ibcon#read 6, iclass 15, count 0 2006.285.16:24:18.16#ibcon#end of sib2, iclass 15, count 0 2006.285.16:24:18.16#ibcon#*after write, iclass 15, count 0 2006.285.16:24:18.16#ibcon#*before return 0, iclass 15, count 0 2006.285.16:24:18.16#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:24:18.16#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:24:18.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.16:24:18.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.16:24:18.16$vck44/vblo=6,719.99 2006.285.16:24:18.16#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.16:24:18.16#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.16:24:18.16#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:18.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:24:18.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:24:18.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:24:18.16#ibcon#enter wrdev, iclass 17, count 0 2006.285.16:24:18.16#ibcon#first serial, iclass 17, count 0 2006.285.16:24:18.16#ibcon#enter sib2, iclass 17, count 0 2006.285.16:24:18.16#ibcon#flushed, iclass 17, count 0 2006.285.16:24:18.16#ibcon#about to write, iclass 17, count 0 2006.285.16:24:18.16#ibcon#wrote, iclass 17, count 0 2006.285.16:24:18.16#ibcon#about to read 3, iclass 17, count 0 2006.285.16:24:18.18#ibcon#read 3, iclass 17, count 0 2006.285.16:24:18.18#ibcon#about to read 4, iclass 17, count 0 2006.285.16:24:18.18#ibcon#read 4, iclass 17, count 0 2006.285.16:24:18.18#ibcon#about to read 5, iclass 17, count 0 2006.285.16:24:18.18#ibcon#read 5, iclass 17, count 0 2006.285.16:24:18.18#ibcon#about to read 6, iclass 17, count 0 2006.285.16:24:18.18#ibcon#read 6, iclass 17, count 0 2006.285.16:24:18.18#ibcon#end of sib2, iclass 17, count 0 2006.285.16:24:18.18#ibcon#*mode == 0, iclass 17, count 0 2006.285.16:24:18.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.16:24:18.18#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.16:24:18.18#ibcon#*before write, iclass 17, count 0 2006.285.16:24:18.18#ibcon#enter sib2, iclass 17, count 0 2006.285.16:24:18.18#ibcon#flushed, iclass 17, count 0 2006.285.16:24:18.18#ibcon#about to write, iclass 17, count 0 2006.285.16:24:18.18#ibcon#wrote, iclass 17, count 0 2006.285.16:24:18.18#ibcon#about to read 3, iclass 17, count 0 2006.285.16:24:18.22#ibcon#read 3, iclass 17, count 0 2006.285.16:24:18.22#ibcon#about to read 4, iclass 17, count 0 2006.285.16:24:18.22#ibcon#read 4, iclass 17, count 0 2006.285.16:24:18.22#ibcon#about to read 5, iclass 17, count 0 2006.285.16:24:18.22#ibcon#read 5, iclass 17, count 0 2006.285.16:24:18.22#ibcon#about to read 6, iclass 17, count 0 2006.285.16:24:18.22#ibcon#read 6, iclass 17, count 0 2006.285.16:24:18.22#ibcon#end of sib2, iclass 17, count 0 2006.285.16:24:18.22#ibcon#*after write, iclass 17, count 0 2006.285.16:24:18.22#ibcon#*before return 0, iclass 17, count 0 2006.285.16:24:18.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:24:18.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:24:18.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.16:24:18.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.16:24:18.22$vck44/vb=6,3 2006.285.16:24:18.22#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.16:24:18.22#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.16:24:18.22#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:18.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:24:18.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:24:18.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:24:18.28#ibcon#enter wrdev, iclass 19, count 2 2006.285.16:24:18.28#ibcon#first serial, iclass 19, count 2 2006.285.16:24:18.28#ibcon#enter sib2, iclass 19, count 2 2006.285.16:24:18.28#ibcon#flushed, iclass 19, count 2 2006.285.16:24:18.28#ibcon#about to write, iclass 19, count 2 2006.285.16:24:18.28#ibcon#wrote, iclass 19, count 2 2006.285.16:24:18.28#ibcon#about to read 3, iclass 19, count 2 2006.285.16:24:18.30#ibcon#read 3, iclass 19, count 2 2006.285.16:24:18.30#ibcon#about to read 4, iclass 19, count 2 2006.285.16:24:18.30#ibcon#read 4, iclass 19, count 2 2006.285.16:24:18.30#ibcon#about to read 5, iclass 19, count 2 2006.285.16:24:18.30#ibcon#read 5, iclass 19, count 2 2006.285.16:24:18.30#ibcon#about to read 6, iclass 19, count 2 2006.285.16:24:18.30#ibcon#read 6, iclass 19, count 2 2006.285.16:24:18.30#ibcon#end of sib2, iclass 19, count 2 2006.285.16:24:18.30#ibcon#*mode == 0, iclass 19, count 2 2006.285.16:24:18.30#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.16:24:18.30#ibcon#[27=AT06-03\r\n] 2006.285.16:24:18.30#ibcon#*before write, iclass 19, count 2 2006.285.16:24:18.30#ibcon#enter sib2, iclass 19, count 2 2006.285.16:24:18.30#ibcon#flushed, iclass 19, count 2 2006.285.16:24:18.30#ibcon#about to write, iclass 19, count 2 2006.285.16:24:18.30#ibcon#wrote, iclass 19, count 2 2006.285.16:24:18.30#ibcon#about to read 3, iclass 19, count 2 2006.285.16:24:18.33#ibcon#read 3, iclass 19, count 2 2006.285.16:24:18.33#ibcon#about to read 4, iclass 19, count 2 2006.285.16:24:18.33#ibcon#read 4, iclass 19, count 2 2006.285.16:24:18.33#ibcon#about to read 5, iclass 19, count 2 2006.285.16:24:18.33#ibcon#read 5, iclass 19, count 2 2006.285.16:24:18.33#ibcon#about to read 6, iclass 19, count 2 2006.285.16:24:18.33#ibcon#read 6, iclass 19, count 2 2006.285.16:24:18.33#ibcon#end of sib2, iclass 19, count 2 2006.285.16:24:18.33#ibcon#*after write, iclass 19, count 2 2006.285.16:24:18.33#ibcon#*before return 0, iclass 19, count 2 2006.285.16:24:18.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:24:18.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:24:18.33#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.16:24:18.33#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:18.33#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:24:18.45#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:24:18.45#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:24:18.45#ibcon#enter wrdev, iclass 19, count 0 2006.285.16:24:18.45#ibcon#first serial, iclass 19, count 0 2006.285.16:24:18.45#ibcon#enter sib2, iclass 19, count 0 2006.285.16:24:18.45#ibcon#flushed, iclass 19, count 0 2006.285.16:24:18.45#ibcon#about to write, iclass 19, count 0 2006.285.16:24:18.45#ibcon#wrote, iclass 19, count 0 2006.285.16:24:18.45#ibcon#about to read 3, iclass 19, count 0 2006.285.16:24:18.47#ibcon#read 3, iclass 19, count 0 2006.285.16:24:18.47#ibcon#about to read 4, iclass 19, count 0 2006.285.16:24:18.47#ibcon#read 4, iclass 19, count 0 2006.285.16:24:18.47#ibcon#about to read 5, iclass 19, count 0 2006.285.16:24:18.47#ibcon#read 5, iclass 19, count 0 2006.285.16:24:18.47#ibcon#about to read 6, iclass 19, count 0 2006.285.16:24:18.47#ibcon#read 6, iclass 19, count 0 2006.285.16:24:18.47#ibcon#end of sib2, iclass 19, count 0 2006.285.16:24:18.47#ibcon#*mode == 0, iclass 19, count 0 2006.285.16:24:18.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.16:24:18.47#ibcon#[27=USB\r\n] 2006.285.16:24:18.47#ibcon#*before write, iclass 19, count 0 2006.285.16:24:18.47#ibcon#enter sib2, iclass 19, count 0 2006.285.16:24:18.47#ibcon#flushed, iclass 19, count 0 2006.285.16:24:18.47#ibcon#about to write, iclass 19, count 0 2006.285.16:24:18.47#ibcon#wrote, iclass 19, count 0 2006.285.16:24:18.47#ibcon#about to read 3, iclass 19, count 0 2006.285.16:24:18.50#ibcon#read 3, iclass 19, count 0 2006.285.16:24:18.50#ibcon#about to read 4, iclass 19, count 0 2006.285.16:24:18.50#ibcon#read 4, iclass 19, count 0 2006.285.16:24:18.50#ibcon#about to read 5, iclass 19, count 0 2006.285.16:24:18.50#ibcon#read 5, iclass 19, count 0 2006.285.16:24:18.50#ibcon#about to read 6, iclass 19, count 0 2006.285.16:24:18.50#ibcon#read 6, iclass 19, count 0 2006.285.16:24:18.50#ibcon#end of sib2, iclass 19, count 0 2006.285.16:24:18.50#ibcon#*after write, iclass 19, count 0 2006.285.16:24:18.50#ibcon#*before return 0, iclass 19, count 0 2006.285.16:24:18.50#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:24:18.50#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:24:18.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.16:24:18.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.16:24:18.50$vck44/vblo=7,734.99 2006.285.16:24:18.50#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.16:24:18.50#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.16:24:18.50#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:18.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:24:18.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:24:18.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:24:18.50#ibcon#enter wrdev, iclass 21, count 0 2006.285.16:24:18.50#ibcon#first serial, iclass 21, count 0 2006.285.16:24:18.50#ibcon#enter sib2, iclass 21, count 0 2006.285.16:24:18.50#ibcon#flushed, iclass 21, count 0 2006.285.16:24:18.50#ibcon#about to write, iclass 21, count 0 2006.285.16:24:18.50#ibcon#wrote, iclass 21, count 0 2006.285.16:24:18.50#ibcon#about to read 3, iclass 21, count 0 2006.285.16:24:18.52#ibcon#read 3, iclass 21, count 0 2006.285.16:24:18.52#ibcon#about to read 4, iclass 21, count 0 2006.285.16:24:18.52#ibcon#read 4, iclass 21, count 0 2006.285.16:24:18.52#ibcon#about to read 5, iclass 21, count 0 2006.285.16:24:18.52#ibcon#read 5, iclass 21, count 0 2006.285.16:24:18.52#ibcon#about to read 6, iclass 21, count 0 2006.285.16:24:18.52#ibcon#read 6, iclass 21, count 0 2006.285.16:24:18.52#ibcon#end of sib2, iclass 21, count 0 2006.285.16:24:18.52#ibcon#*mode == 0, iclass 21, count 0 2006.285.16:24:18.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.16:24:18.52#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.16:24:18.52#ibcon#*before write, iclass 21, count 0 2006.285.16:24:18.52#ibcon#enter sib2, iclass 21, count 0 2006.285.16:24:18.52#ibcon#flushed, iclass 21, count 0 2006.285.16:24:18.52#ibcon#about to write, iclass 21, count 0 2006.285.16:24:18.52#ibcon#wrote, iclass 21, count 0 2006.285.16:24:18.52#ibcon#about to read 3, iclass 21, count 0 2006.285.16:24:18.56#ibcon#read 3, iclass 21, count 0 2006.285.16:24:18.56#ibcon#about to read 4, iclass 21, count 0 2006.285.16:24:18.56#ibcon#read 4, iclass 21, count 0 2006.285.16:24:18.56#ibcon#about to read 5, iclass 21, count 0 2006.285.16:24:18.56#ibcon#read 5, iclass 21, count 0 2006.285.16:24:18.56#ibcon#about to read 6, iclass 21, count 0 2006.285.16:24:18.56#ibcon#read 6, iclass 21, count 0 2006.285.16:24:18.56#ibcon#end of sib2, iclass 21, count 0 2006.285.16:24:18.56#ibcon#*after write, iclass 21, count 0 2006.285.16:24:18.56#ibcon#*before return 0, iclass 21, count 0 2006.285.16:24:18.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:24:18.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:24:18.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.16:24:18.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.16:24:18.56$vck44/vb=7,4 2006.285.16:24:18.56#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.16:24:18.56#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.16:24:18.56#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:18.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:24:18.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:24:18.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:24:18.62#ibcon#enter wrdev, iclass 23, count 2 2006.285.16:24:18.62#ibcon#first serial, iclass 23, count 2 2006.285.16:24:18.62#ibcon#enter sib2, iclass 23, count 2 2006.285.16:24:18.62#ibcon#flushed, iclass 23, count 2 2006.285.16:24:18.62#ibcon#about to write, iclass 23, count 2 2006.285.16:24:18.62#ibcon#wrote, iclass 23, count 2 2006.285.16:24:18.62#ibcon#about to read 3, iclass 23, count 2 2006.285.16:24:18.64#ibcon#read 3, iclass 23, count 2 2006.285.16:24:18.64#ibcon#about to read 4, iclass 23, count 2 2006.285.16:24:18.64#ibcon#read 4, iclass 23, count 2 2006.285.16:24:18.64#ibcon#about to read 5, iclass 23, count 2 2006.285.16:24:18.64#ibcon#read 5, iclass 23, count 2 2006.285.16:24:18.64#ibcon#about to read 6, iclass 23, count 2 2006.285.16:24:18.64#ibcon#read 6, iclass 23, count 2 2006.285.16:24:18.64#ibcon#end of sib2, iclass 23, count 2 2006.285.16:24:18.64#ibcon#*mode == 0, iclass 23, count 2 2006.285.16:24:18.64#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.16:24:18.64#ibcon#[27=AT07-04\r\n] 2006.285.16:24:18.64#ibcon#*before write, iclass 23, count 2 2006.285.16:24:18.64#ibcon#enter sib2, iclass 23, count 2 2006.285.16:24:18.64#ibcon#flushed, iclass 23, count 2 2006.285.16:24:18.64#ibcon#about to write, iclass 23, count 2 2006.285.16:24:18.64#ibcon#wrote, iclass 23, count 2 2006.285.16:24:18.64#ibcon#about to read 3, iclass 23, count 2 2006.285.16:24:18.67#ibcon#read 3, iclass 23, count 2 2006.285.16:24:18.67#ibcon#about to read 4, iclass 23, count 2 2006.285.16:24:18.67#ibcon#read 4, iclass 23, count 2 2006.285.16:24:18.67#ibcon#about to read 5, iclass 23, count 2 2006.285.16:24:18.67#ibcon#read 5, iclass 23, count 2 2006.285.16:24:18.67#ibcon#about to read 6, iclass 23, count 2 2006.285.16:24:18.67#ibcon#read 6, iclass 23, count 2 2006.285.16:24:18.67#ibcon#end of sib2, iclass 23, count 2 2006.285.16:24:18.67#ibcon#*after write, iclass 23, count 2 2006.285.16:24:18.67#ibcon#*before return 0, iclass 23, count 2 2006.285.16:24:18.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:24:18.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:24:18.67#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.16:24:18.67#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:18.67#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:24:18.79#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:24:18.79#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:24:18.79#ibcon#enter wrdev, iclass 23, count 0 2006.285.16:24:18.79#ibcon#first serial, iclass 23, count 0 2006.285.16:24:18.79#ibcon#enter sib2, iclass 23, count 0 2006.285.16:24:18.79#ibcon#flushed, iclass 23, count 0 2006.285.16:24:18.79#ibcon#about to write, iclass 23, count 0 2006.285.16:24:18.79#ibcon#wrote, iclass 23, count 0 2006.285.16:24:18.79#ibcon#about to read 3, iclass 23, count 0 2006.285.16:24:18.81#ibcon#read 3, iclass 23, count 0 2006.285.16:24:18.81#ibcon#about to read 4, iclass 23, count 0 2006.285.16:24:18.81#ibcon#read 4, iclass 23, count 0 2006.285.16:24:18.81#ibcon#about to read 5, iclass 23, count 0 2006.285.16:24:18.81#ibcon#read 5, iclass 23, count 0 2006.285.16:24:18.81#ibcon#about to read 6, iclass 23, count 0 2006.285.16:24:18.81#ibcon#read 6, iclass 23, count 0 2006.285.16:24:18.81#ibcon#end of sib2, iclass 23, count 0 2006.285.16:24:18.81#ibcon#*mode == 0, iclass 23, count 0 2006.285.16:24:18.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.16:24:18.81#ibcon#[27=USB\r\n] 2006.285.16:24:18.81#ibcon#*before write, iclass 23, count 0 2006.285.16:24:18.81#ibcon#enter sib2, iclass 23, count 0 2006.285.16:24:18.81#ibcon#flushed, iclass 23, count 0 2006.285.16:24:18.81#ibcon#about to write, iclass 23, count 0 2006.285.16:24:18.81#ibcon#wrote, iclass 23, count 0 2006.285.16:24:18.81#ibcon#about to read 3, iclass 23, count 0 2006.285.16:24:18.84#ibcon#read 3, iclass 23, count 0 2006.285.16:24:18.84#ibcon#about to read 4, iclass 23, count 0 2006.285.16:24:18.84#ibcon#read 4, iclass 23, count 0 2006.285.16:24:18.84#ibcon#about to read 5, iclass 23, count 0 2006.285.16:24:18.84#ibcon#read 5, iclass 23, count 0 2006.285.16:24:18.84#ibcon#about to read 6, iclass 23, count 0 2006.285.16:24:18.84#ibcon#read 6, iclass 23, count 0 2006.285.16:24:18.84#ibcon#end of sib2, iclass 23, count 0 2006.285.16:24:18.84#ibcon#*after write, iclass 23, count 0 2006.285.16:24:18.84#ibcon#*before return 0, iclass 23, count 0 2006.285.16:24:18.84#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:24:18.84#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:24:18.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.16:24:18.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.16:24:18.84$vck44/vblo=8,744.99 2006.285.16:24:18.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.16:24:18.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.16:24:18.87#ibcon#ireg 17 cls_cnt 0 2006.285.16:24:18.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:24:18.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:24:18.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:24:18.87#ibcon#enter wrdev, iclass 25, count 0 2006.285.16:24:18.87#ibcon#first serial, iclass 25, count 0 2006.285.16:24:18.87#ibcon#enter sib2, iclass 25, count 0 2006.285.16:24:18.87#ibcon#flushed, iclass 25, count 0 2006.285.16:24:18.87#ibcon#about to write, iclass 25, count 0 2006.285.16:24:18.87#ibcon#wrote, iclass 25, count 0 2006.285.16:24:18.87#ibcon#about to read 3, iclass 25, count 0 2006.285.16:24:18.89#ibcon#read 3, iclass 25, count 0 2006.285.16:24:18.89#ibcon#about to read 4, iclass 25, count 0 2006.285.16:24:18.89#ibcon#read 4, iclass 25, count 0 2006.285.16:24:18.89#ibcon#about to read 5, iclass 25, count 0 2006.285.16:24:18.89#ibcon#read 5, iclass 25, count 0 2006.285.16:24:18.89#ibcon#about to read 6, iclass 25, count 0 2006.285.16:24:18.89#ibcon#read 6, iclass 25, count 0 2006.285.16:24:18.89#ibcon#end of sib2, iclass 25, count 0 2006.285.16:24:18.89#ibcon#*mode == 0, iclass 25, count 0 2006.285.16:24:18.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.16:24:18.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.16:24:18.89#ibcon#*before write, iclass 25, count 0 2006.285.16:24:18.89#ibcon#enter sib2, iclass 25, count 0 2006.285.16:24:18.89#ibcon#flushed, iclass 25, count 0 2006.285.16:24:18.89#ibcon#about to write, iclass 25, count 0 2006.285.16:24:18.89#ibcon#wrote, iclass 25, count 0 2006.285.16:24:18.89#ibcon#about to read 3, iclass 25, count 0 2006.285.16:24:18.93#ibcon#read 3, iclass 25, count 0 2006.285.16:24:18.93#ibcon#about to read 4, iclass 25, count 0 2006.285.16:24:18.93#ibcon#read 4, iclass 25, count 0 2006.285.16:24:18.93#ibcon#about to read 5, iclass 25, count 0 2006.285.16:24:18.93#ibcon#read 5, iclass 25, count 0 2006.285.16:24:18.93#ibcon#about to read 6, iclass 25, count 0 2006.285.16:24:18.93#ibcon#read 6, iclass 25, count 0 2006.285.16:24:18.93#ibcon#end of sib2, iclass 25, count 0 2006.285.16:24:18.93#ibcon#*after write, iclass 25, count 0 2006.285.16:24:18.93#ibcon#*before return 0, iclass 25, count 0 2006.285.16:24:18.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:24:18.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:24:18.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.16:24:18.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.16:24:18.93$vck44/vb=8,4 2006.285.16:24:18.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.16:24:18.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.16:24:18.93#ibcon#ireg 11 cls_cnt 2 2006.285.16:24:18.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:24:18.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:24:18.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:24:18.96#ibcon#enter wrdev, iclass 27, count 2 2006.285.16:24:18.96#ibcon#first serial, iclass 27, count 2 2006.285.16:24:18.96#ibcon#enter sib2, iclass 27, count 2 2006.285.16:24:18.96#ibcon#flushed, iclass 27, count 2 2006.285.16:24:18.96#ibcon#about to write, iclass 27, count 2 2006.285.16:24:18.96#ibcon#wrote, iclass 27, count 2 2006.285.16:24:18.96#ibcon#about to read 3, iclass 27, count 2 2006.285.16:24:18.98#ibcon#read 3, iclass 27, count 2 2006.285.16:24:18.98#ibcon#about to read 4, iclass 27, count 2 2006.285.16:24:18.98#ibcon#read 4, iclass 27, count 2 2006.285.16:24:18.98#ibcon#about to read 5, iclass 27, count 2 2006.285.16:24:18.98#ibcon#read 5, iclass 27, count 2 2006.285.16:24:18.98#ibcon#about to read 6, iclass 27, count 2 2006.285.16:24:18.98#ibcon#read 6, iclass 27, count 2 2006.285.16:24:18.98#ibcon#end of sib2, iclass 27, count 2 2006.285.16:24:18.98#ibcon#*mode == 0, iclass 27, count 2 2006.285.16:24:18.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.16:24:18.98#ibcon#[27=AT08-04\r\n] 2006.285.16:24:18.98#ibcon#*before write, iclass 27, count 2 2006.285.16:24:18.98#ibcon#enter sib2, iclass 27, count 2 2006.285.16:24:18.98#ibcon#flushed, iclass 27, count 2 2006.285.16:24:18.98#ibcon#about to write, iclass 27, count 2 2006.285.16:24:18.98#ibcon#wrote, iclass 27, count 2 2006.285.16:24:18.98#ibcon#about to read 3, iclass 27, count 2 2006.285.16:24:19.01#ibcon#read 3, iclass 27, count 2 2006.285.16:24:19.01#ibcon#about to read 4, iclass 27, count 2 2006.285.16:24:19.01#ibcon#read 4, iclass 27, count 2 2006.285.16:24:19.01#ibcon#about to read 5, iclass 27, count 2 2006.285.16:24:19.01#ibcon#read 5, iclass 27, count 2 2006.285.16:24:19.01#ibcon#about to read 6, iclass 27, count 2 2006.285.16:24:19.01#ibcon#read 6, iclass 27, count 2 2006.285.16:24:19.01#ibcon#end of sib2, iclass 27, count 2 2006.285.16:24:19.01#ibcon#*after write, iclass 27, count 2 2006.285.16:24:19.01#ibcon#*before return 0, iclass 27, count 2 2006.285.16:24:19.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:24:19.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:24:19.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.16:24:19.01#ibcon#ireg 7 cls_cnt 0 2006.285.16:24:19.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:24:19.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:24:19.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:24:19.13#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:24:19.13#ibcon#first serial, iclass 27, count 0 2006.285.16:24:19.13#ibcon#enter sib2, iclass 27, count 0 2006.285.16:24:19.13#ibcon#flushed, iclass 27, count 0 2006.285.16:24:19.13#ibcon#about to write, iclass 27, count 0 2006.285.16:24:19.13#ibcon#wrote, iclass 27, count 0 2006.285.16:24:19.13#ibcon#about to read 3, iclass 27, count 0 2006.285.16:24:19.15#ibcon#read 3, iclass 27, count 0 2006.285.16:24:19.15#ibcon#about to read 4, iclass 27, count 0 2006.285.16:24:19.15#ibcon#read 4, iclass 27, count 0 2006.285.16:24:19.15#ibcon#about to read 5, iclass 27, count 0 2006.285.16:24:19.15#ibcon#read 5, iclass 27, count 0 2006.285.16:24:19.15#ibcon#about to read 6, iclass 27, count 0 2006.285.16:24:19.15#ibcon#read 6, iclass 27, count 0 2006.285.16:24:19.15#ibcon#end of sib2, iclass 27, count 0 2006.285.16:24:19.15#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:24:19.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:24:19.15#ibcon#[27=USB\r\n] 2006.285.16:24:19.15#ibcon#*before write, iclass 27, count 0 2006.285.16:24:19.15#ibcon#enter sib2, iclass 27, count 0 2006.285.16:24:19.15#ibcon#flushed, iclass 27, count 0 2006.285.16:24:19.15#ibcon#about to write, iclass 27, count 0 2006.285.16:24:19.15#ibcon#wrote, iclass 27, count 0 2006.285.16:24:19.15#ibcon#about to read 3, iclass 27, count 0 2006.285.16:24:19.18#ibcon#read 3, iclass 27, count 0 2006.285.16:24:19.18#ibcon#about to read 4, iclass 27, count 0 2006.285.16:24:19.18#ibcon#read 4, iclass 27, count 0 2006.285.16:24:19.18#ibcon#about to read 5, iclass 27, count 0 2006.285.16:24:19.18#ibcon#read 5, iclass 27, count 0 2006.285.16:24:19.18#ibcon#about to read 6, iclass 27, count 0 2006.285.16:24:19.18#ibcon#read 6, iclass 27, count 0 2006.285.16:24:19.18#ibcon#end of sib2, iclass 27, count 0 2006.285.16:24:19.18#ibcon#*after write, iclass 27, count 0 2006.285.16:24:19.18#ibcon#*before return 0, iclass 27, count 0 2006.285.16:24:19.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:24:19.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:24:19.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:24:19.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:24:19.18$vck44/vabw=wide 2006.285.16:24:19.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.16:24:19.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.16:24:19.18#ibcon#ireg 8 cls_cnt 0 2006.285.16:24:19.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:24:19.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:24:19.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:24:19.18#ibcon#enter wrdev, iclass 29, count 0 2006.285.16:24:19.18#ibcon#first serial, iclass 29, count 0 2006.285.16:24:19.18#ibcon#enter sib2, iclass 29, count 0 2006.285.16:24:19.18#ibcon#flushed, iclass 29, count 0 2006.285.16:24:19.18#ibcon#about to write, iclass 29, count 0 2006.285.16:24:19.18#ibcon#wrote, iclass 29, count 0 2006.285.16:24:19.18#ibcon#about to read 3, iclass 29, count 0 2006.285.16:24:19.20#ibcon#read 3, iclass 29, count 0 2006.285.16:24:19.20#ibcon#about to read 4, iclass 29, count 0 2006.285.16:24:19.20#ibcon#read 4, iclass 29, count 0 2006.285.16:24:19.20#ibcon#about to read 5, iclass 29, count 0 2006.285.16:24:19.20#ibcon#read 5, iclass 29, count 0 2006.285.16:24:19.20#ibcon#about to read 6, iclass 29, count 0 2006.285.16:24:19.20#ibcon#read 6, iclass 29, count 0 2006.285.16:24:19.20#ibcon#end of sib2, iclass 29, count 0 2006.285.16:24:19.20#ibcon#*mode == 0, iclass 29, count 0 2006.285.16:24:19.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.16:24:19.20#ibcon#[25=BW32\r\n] 2006.285.16:24:19.20#ibcon#*before write, iclass 29, count 0 2006.285.16:24:19.20#ibcon#enter sib2, iclass 29, count 0 2006.285.16:24:19.20#ibcon#flushed, iclass 29, count 0 2006.285.16:24:19.20#ibcon#about to write, iclass 29, count 0 2006.285.16:24:19.20#ibcon#wrote, iclass 29, count 0 2006.285.16:24:19.20#ibcon#about to read 3, iclass 29, count 0 2006.285.16:24:19.23#ibcon#read 3, iclass 29, count 0 2006.285.16:24:19.23#ibcon#about to read 4, iclass 29, count 0 2006.285.16:24:19.23#ibcon#read 4, iclass 29, count 0 2006.285.16:24:19.23#ibcon#about to read 5, iclass 29, count 0 2006.285.16:24:19.23#ibcon#read 5, iclass 29, count 0 2006.285.16:24:19.23#ibcon#about to read 6, iclass 29, count 0 2006.285.16:24:19.23#ibcon#read 6, iclass 29, count 0 2006.285.16:24:19.23#ibcon#end of sib2, iclass 29, count 0 2006.285.16:24:19.23#ibcon#*after write, iclass 29, count 0 2006.285.16:24:19.23#ibcon#*before return 0, iclass 29, count 0 2006.285.16:24:19.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:24:19.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:24:19.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.16:24:19.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.16:24:19.23$vck44/vbbw=wide 2006.285.16:24:19.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.16:24:19.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.16:24:19.23#ibcon#ireg 8 cls_cnt 0 2006.285.16:24:19.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:24:19.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:24:19.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:24:19.30#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:24:19.30#ibcon#first serial, iclass 31, count 0 2006.285.16:24:19.30#ibcon#enter sib2, iclass 31, count 0 2006.285.16:24:19.30#ibcon#flushed, iclass 31, count 0 2006.285.16:24:19.30#ibcon#about to write, iclass 31, count 0 2006.285.16:24:19.30#ibcon#wrote, iclass 31, count 0 2006.285.16:24:19.30#ibcon#about to read 3, iclass 31, count 0 2006.285.16:24:19.32#ibcon#read 3, iclass 31, count 0 2006.285.16:24:19.32#ibcon#about to read 4, iclass 31, count 0 2006.285.16:24:19.32#ibcon#read 4, iclass 31, count 0 2006.285.16:24:19.32#ibcon#about to read 5, iclass 31, count 0 2006.285.16:24:19.32#ibcon#read 5, iclass 31, count 0 2006.285.16:24:19.32#ibcon#about to read 6, iclass 31, count 0 2006.285.16:24:19.32#ibcon#read 6, iclass 31, count 0 2006.285.16:24:19.32#ibcon#end of sib2, iclass 31, count 0 2006.285.16:24:19.32#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:24:19.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:24:19.32#ibcon#[27=BW32\r\n] 2006.285.16:24:19.32#ibcon#*before write, iclass 31, count 0 2006.285.16:24:19.32#ibcon#enter sib2, iclass 31, count 0 2006.285.16:24:19.32#ibcon#flushed, iclass 31, count 0 2006.285.16:24:19.32#ibcon#about to write, iclass 31, count 0 2006.285.16:24:19.32#ibcon#wrote, iclass 31, count 0 2006.285.16:24:19.32#ibcon#about to read 3, iclass 31, count 0 2006.285.16:24:19.35#ibcon#read 3, iclass 31, count 0 2006.285.16:24:19.35#ibcon#about to read 4, iclass 31, count 0 2006.285.16:24:19.35#ibcon#read 4, iclass 31, count 0 2006.285.16:24:19.35#ibcon#about to read 5, iclass 31, count 0 2006.285.16:24:19.35#ibcon#read 5, iclass 31, count 0 2006.285.16:24:19.35#ibcon#about to read 6, iclass 31, count 0 2006.285.16:24:19.35#ibcon#read 6, iclass 31, count 0 2006.285.16:24:19.35#ibcon#end of sib2, iclass 31, count 0 2006.285.16:24:19.35#ibcon#*after write, iclass 31, count 0 2006.285.16:24:19.35#ibcon#*before return 0, iclass 31, count 0 2006.285.16:24:19.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:24:19.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:24:19.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:24:19.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:24:19.35$setupk4/ifdk4 2006.285.16:24:19.35$ifdk4/lo= 2006.285.16:24:19.35$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.16:24:19.35$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.16:24:19.35$ifdk4/patch= 2006.285.16:24:19.35$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.16:24:19.35$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.16:24:19.35$setupk4/!*+20s 2006.285.16:24:22.65#abcon#<5=/16 0.8 2.2 18.59 911014.9\r\n> 2006.285.16:24:22.67#abcon#{5=INTERFACE CLEAR} 2006.285.16:24:22.73#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:24:32.82#abcon#<5=/16 0.8 2.2 18.59 911014.9\r\n> 2006.285.16:24:32.84#abcon#{5=INTERFACE CLEAR} 2006.285.16:24:32.90#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:24:33.03$setupk4/"tpicd 2006.285.16:24:33.03$setupk4/echo=off 2006.285.16:24:33.03$setupk4/xlog=off 2006.285.16:24:33.03:!2006.285.16:30:06 2006.285.16:24:59.14#trakl#Source acquired 2006.285.16:25:01.14#flagr#flagr/antenna,acquired 2006.285.16:30:06.00:preob 2006.285.16:30:06.14/onsource/TRACKING 2006.285.16:30:06.14:!2006.285.16:30:16 2006.285.16:30:16.00:"tape 2006.285.16:30:16.00:"st=record 2006.285.16:30:16.00:data_valid=on 2006.285.16:30:16.00:midob 2006.285.16:30:16.14/onsource/TRACKING 2006.285.16:30:16.14/wx/18.55,1014.9,90 2006.285.16:30:16.30/cable/+6.5027E-03 2006.285.16:30:17.39/va/01,07,usb,yes,37,40 2006.285.16:30:17.39/va/02,06,usb,yes,37,38 2006.285.16:30:17.39/va/03,07,usb,yes,37,39 2006.285.16:30:17.39/va/04,06,usb,yes,38,40 2006.285.16:30:17.39/va/05,03,usb,yes,38,38 2006.285.16:30:17.39/va/06,04,usb,yes,34,34 2006.285.16:30:17.39/va/07,04,usb,yes,35,35 2006.285.16:30:17.39/va/08,03,usb,yes,36,43 2006.285.16:30:17.62/valo/01,524.99,yes,locked 2006.285.16:30:17.62/valo/02,534.99,yes,locked 2006.285.16:30:17.62/valo/03,564.99,yes,locked 2006.285.16:30:17.62/valo/04,624.99,yes,locked 2006.285.16:30:17.62/valo/05,734.99,yes,locked 2006.285.16:30:17.62/valo/06,814.99,yes,locked 2006.285.16:30:17.62/valo/07,864.99,yes,locked 2006.285.16:30:17.62/valo/08,884.99,yes,locked 2006.285.16:30:18.71/vb/01,04,usb,yes,32,29 2006.285.16:30:18.71/vb/02,05,usb,yes,30,30 2006.285.16:30:18.71/vb/03,04,usb,yes,31,34 2006.285.16:30:18.71/vb/04,05,usb,yes,31,30 2006.285.16:30:18.71/vb/05,04,usb,yes,28,30 2006.285.16:30:18.71/vb/06,03,usb,yes,40,35 2006.285.16:30:18.71/vb/07,04,usb,yes,32,32 2006.285.16:30:18.71/vb/08,04,usb,yes,29,33 2006.285.16:30:18.95/vblo/01,629.99,yes,locked 2006.285.16:30:18.95/vblo/02,634.99,yes,locked 2006.285.16:30:18.95/vblo/03,649.99,yes,locked 2006.285.16:30:18.95/vblo/04,679.99,yes,locked 2006.285.16:30:18.95/vblo/05,709.99,yes,locked 2006.285.16:30:18.95/vblo/06,719.99,yes,locked 2006.285.16:30:18.95/vblo/07,734.99,yes,locked 2006.285.16:30:18.95/vblo/08,744.99,yes,locked 2006.285.16:30:19.10/vabw/8 2006.285.16:30:19.25/vbbw/8 2006.285.16:30:19.37/xfe/off,on,12.2 2006.285.16:30:19.74/ifatt/23,28,28,28 2006.285.16:30:20.08/fmout-gps/S +2.66E-07 2006.285.16:30:20.10:!2006.285.16:30:56 2006.285.16:30:56.00:data_valid=off 2006.285.16:30:56.00:"et 2006.285.16:30:56.00:!+3s 2006.285.16:30:59.01:"tape 2006.285.16:30:59.01:postob 2006.285.16:30:59.20/cable/+6.5025E-03 2006.285.16:30:59.20/wx/18.55,1014.9,90 2006.285.16:31:00.08/fmout-gps/S +2.62E-07 2006.285.16:31:00.08:scan_name=285-1637,jd0610,100 2006.285.16:31:00.08:source=0528+134,053056.42,133155.1,2000.0,cw 2006.285.16:31:01.14#flagr#flagr/antenna,new-source 2006.285.16:31:01.14:checkk5 2006.285.16:31:01.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.16:31:01.99/chk_autoobs//k5ts2/ autoobs is running! 2006.285.16:31:02.37/chk_autoobs//k5ts3/ autoobs is running! 2006.285.16:31:03.05/chk_autoobs//k5ts4/ autoobs is running! 2006.285.16:31:03.48/chk_obsdata//k5ts1/T2851630??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.16:31:04.32/chk_obsdata//k5ts2/T2851630??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.16:31:04.68/chk_obsdata//k5ts3/T2851630??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.16:31:05.14/chk_obsdata//k5ts4/T2851630??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.16:31:06.03/k5log//k5ts1_log_newline 2006.285.16:31:06.81/k5log//k5ts2_log_newline 2006.285.16:31:12.62/k5log//k5ts3_log_newline 2006.285.16:31:13.70/k5log//k5ts4_log_newline 2006.285.16:31:13.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.16:31:13.72:setupk4=1 2006.285.16:31:13.72$setupk4/echo=on 2006.285.16:31:13.72$setupk4/pcalon 2006.285.16:31:13.72$pcalon/"no phase cal control is implemented here 2006.285.16:31:13.72$setupk4/"tpicd=stop 2006.285.16:31:13.72$setupk4/"rec=synch_on 2006.285.16:31:13.72$setupk4/"rec_mode=128 2006.285.16:31:13.72$setupk4/!* 2006.285.16:31:13.72$setupk4/recpk4 2006.285.16:31:13.72$recpk4/recpatch= 2006.285.16:31:13.72$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.16:31:13.72$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.16:31:13.73$setupk4/vck44 2006.285.16:31:13.73$vck44/valo=1,524.99 2006.285.16:31:13.73#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.16:31:13.73#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.16:31:13.73#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:13.73#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:31:13.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:31:13.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:31:13.73#ibcon#enter wrdev, iclass 20, count 0 2006.285.16:31:13.73#ibcon#first serial, iclass 20, count 0 2006.285.16:31:13.73#ibcon#enter sib2, iclass 20, count 0 2006.285.16:31:13.73#ibcon#flushed, iclass 20, count 0 2006.285.16:31:13.73#ibcon#about to write, iclass 20, count 0 2006.285.16:31:13.73#ibcon#wrote, iclass 20, count 0 2006.285.16:31:13.73#ibcon#about to read 3, iclass 20, count 0 2006.285.16:31:13.75#ibcon#read 3, iclass 20, count 0 2006.285.16:31:13.75#ibcon#about to read 4, iclass 20, count 0 2006.285.16:31:13.75#ibcon#read 4, iclass 20, count 0 2006.285.16:31:13.75#ibcon#about to read 5, iclass 20, count 0 2006.285.16:31:13.75#ibcon#read 5, iclass 20, count 0 2006.285.16:31:13.75#ibcon#about to read 6, iclass 20, count 0 2006.285.16:31:13.75#ibcon#read 6, iclass 20, count 0 2006.285.16:31:13.75#ibcon#end of sib2, iclass 20, count 0 2006.285.16:31:13.75#ibcon#*mode == 0, iclass 20, count 0 2006.285.16:31:13.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.16:31:13.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.16:31:13.75#ibcon#*before write, iclass 20, count 0 2006.285.16:31:13.75#ibcon#enter sib2, iclass 20, count 0 2006.285.16:31:13.75#ibcon#flushed, iclass 20, count 0 2006.285.16:31:13.75#ibcon#about to write, iclass 20, count 0 2006.285.16:31:13.75#ibcon#wrote, iclass 20, count 0 2006.285.16:31:13.75#ibcon#about to read 3, iclass 20, count 0 2006.285.16:31:13.80#ibcon#read 3, iclass 20, count 0 2006.285.16:31:13.80#ibcon#about to read 4, iclass 20, count 0 2006.285.16:31:13.80#ibcon#read 4, iclass 20, count 0 2006.285.16:31:13.80#ibcon#about to read 5, iclass 20, count 0 2006.285.16:31:13.80#ibcon#read 5, iclass 20, count 0 2006.285.16:31:13.80#ibcon#about to read 6, iclass 20, count 0 2006.285.16:31:13.80#ibcon#read 6, iclass 20, count 0 2006.285.16:31:13.80#ibcon#end of sib2, iclass 20, count 0 2006.285.16:31:13.80#ibcon#*after write, iclass 20, count 0 2006.285.16:31:13.80#ibcon#*before return 0, iclass 20, count 0 2006.285.16:31:13.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:31:13.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:31:13.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.16:31:13.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.16:31:13.80$vck44/va=1,7 2006.285.16:31:13.80#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.16:31:13.80#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.16:31:13.80#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:13.80#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:31:13.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:31:13.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:31:13.80#ibcon#enter wrdev, iclass 22, count 2 2006.285.16:31:13.80#ibcon#first serial, iclass 22, count 2 2006.285.16:31:13.80#ibcon#enter sib2, iclass 22, count 2 2006.285.16:31:13.80#ibcon#flushed, iclass 22, count 2 2006.285.16:31:13.80#ibcon#about to write, iclass 22, count 2 2006.285.16:31:13.80#ibcon#wrote, iclass 22, count 2 2006.285.16:31:13.80#ibcon#about to read 3, iclass 22, count 2 2006.285.16:31:13.82#ibcon#read 3, iclass 22, count 2 2006.285.16:31:13.82#ibcon#about to read 4, iclass 22, count 2 2006.285.16:31:13.82#ibcon#read 4, iclass 22, count 2 2006.285.16:31:13.82#ibcon#about to read 5, iclass 22, count 2 2006.285.16:31:13.82#ibcon#read 5, iclass 22, count 2 2006.285.16:31:13.82#ibcon#about to read 6, iclass 22, count 2 2006.285.16:31:13.82#ibcon#read 6, iclass 22, count 2 2006.285.16:31:13.82#ibcon#end of sib2, iclass 22, count 2 2006.285.16:31:13.82#ibcon#*mode == 0, iclass 22, count 2 2006.285.16:31:13.82#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.16:31:13.82#ibcon#[25=AT01-07\r\n] 2006.285.16:31:13.82#ibcon#*before write, iclass 22, count 2 2006.285.16:31:13.82#ibcon#enter sib2, iclass 22, count 2 2006.285.16:31:13.82#ibcon#flushed, iclass 22, count 2 2006.285.16:31:13.82#ibcon#about to write, iclass 22, count 2 2006.285.16:31:13.82#ibcon#wrote, iclass 22, count 2 2006.285.16:31:13.82#ibcon#about to read 3, iclass 22, count 2 2006.285.16:31:13.85#ibcon#read 3, iclass 22, count 2 2006.285.16:31:13.85#ibcon#about to read 4, iclass 22, count 2 2006.285.16:31:13.85#ibcon#read 4, iclass 22, count 2 2006.285.16:31:13.85#ibcon#about to read 5, iclass 22, count 2 2006.285.16:31:13.85#ibcon#read 5, iclass 22, count 2 2006.285.16:31:13.85#ibcon#about to read 6, iclass 22, count 2 2006.285.16:31:13.85#ibcon#read 6, iclass 22, count 2 2006.285.16:31:13.85#ibcon#end of sib2, iclass 22, count 2 2006.285.16:31:13.85#ibcon#*after write, iclass 22, count 2 2006.285.16:31:13.85#ibcon#*before return 0, iclass 22, count 2 2006.285.16:31:13.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:31:13.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:31:13.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.16:31:13.85#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:13.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:31:13.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:31:13.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:31:13.97#ibcon#enter wrdev, iclass 22, count 0 2006.285.16:31:13.97#ibcon#first serial, iclass 22, count 0 2006.285.16:31:13.97#ibcon#enter sib2, iclass 22, count 0 2006.285.16:31:13.97#ibcon#flushed, iclass 22, count 0 2006.285.16:31:13.97#ibcon#about to write, iclass 22, count 0 2006.285.16:31:13.97#ibcon#wrote, iclass 22, count 0 2006.285.16:31:13.97#ibcon#about to read 3, iclass 22, count 0 2006.285.16:31:13.99#ibcon#read 3, iclass 22, count 0 2006.285.16:31:13.99#ibcon#about to read 4, iclass 22, count 0 2006.285.16:31:13.99#ibcon#read 4, iclass 22, count 0 2006.285.16:31:13.99#ibcon#about to read 5, iclass 22, count 0 2006.285.16:31:13.99#ibcon#read 5, iclass 22, count 0 2006.285.16:31:13.99#ibcon#about to read 6, iclass 22, count 0 2006.285.16:31:13.99#ibcon#read 6, iclass 22, count 0 2006.285.16:31:13.99#ibcon#end of sib2, iclass 22, count 0 2006.285.16:31:13.99#ibcon#*mode == 0, iclass 22, count 0 2006.285.16:31:13.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.16:31:13.99#ibcon#[25=USB\r\n] 2006.285.16:31:13.99#ibcon#*before write, iclass 22, count 0 2006.285.16:31:13.99#ibcon#enter sib2, iclass 22, count 0 2006.285.16:31:13.99#ibcon#flushed, iclass 22, count 0 2006.285.16:31:13.99#ibcon#about to write, iclass 22, count 0 2006.285.16:31:13.99#ibcon#wrote, iclass 22, count 0 2006.285.16:31:13.99#ibcon#about to read 3, iclass 22, count 0 2006.285.16:31:14.02#ibcon#read 3, iclass 22, count 0 2006.285.16:31:14.02#ibcon#about to read 4, iclass 22, count 0 2006.285.16:31:14.02#ibcon#read 4, iclass 22, count 0 2006.285.16:31:14.02#ibcon#about to read 5, iclass 22, count 0 2006.285.16:31:14.02#ibcon#read 5, iclass 22, count 0 2006.285.16:31:14.02#ibcon#about to read 6, iclass 22, count 0 2006.285.16:31:14.02#ibcon#read 6, iclass 22, count 0 2006.285.16:31:14.02#ibcon#end of sib2, iclass 22, count 0 2006.285.16:31:14.02#ibcon#*after write, iclass 22, count 0 2006.285.16:31:14.02#ibcon#*before return 0, iclass 22, count 0 2006.285.16:31:14.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:31:14.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:31:14.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.16:31:14.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.16:31:14.02$vck44/valo=2,534.99 2006.285.16:31:14.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.16:31:14.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.16:31:14.02#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:14.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:31:14.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:31:14.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:31:14.02#ibcon#enter wrdev, iclass 24, count 0 2006.285.16:31:14.02#ibcon#first serial, iclass 24, count 0 2006.285.16:31:14.02#ibcon#enter sib2, iclass 24, count 0 2006.285.16:31:14.02#ibcon#flushed, iclass 24, count 0 2006.285.16:31:14.02#ibcon#about to write, iclass 24, count 0 2006.285.16:31:14.02#ibcon#wrote, iclass 24, count 0 2006.285.16:31:14.02#ibcon#about to read 3, iclass 24, count 0 2006.285.16:31:14.04#ibcon#read 3, iclass 24, count 0 2006.285.16:31:14.04#ibcon#about to read 4, iclass 24, count 0 2006.285.16:31:14.04#ibcon#read 4, iclass 24, count 0 2006.285.16:31:14.04#ibcon#about to read 5, iclass 24, count 0 2006.285.16:31:14.04#ibcon#read 5, iclass 24, count 0 2006.285.16:31:14.04#ibcon#about to read 6, iclass 24, count 0 2006.285.16:31:14.04#ibcon#read 6, iclass 24, count 0 2006.285.16:31:14.04#ibcon#end of sib2, iclass 24, count 0 2006.285.16:31:14.04#ibcon#*mode == 0, iclass 24, count 0 2006.285.16:31:14.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.16:31:14.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.16:31:14.04#ibcon#*before write, iclass 24, count 0 2006.285.16:31:14.04#ibcon#enter sib2, iclass 24, count 0 2006.285.16:31:14.04#ibcon#flushed, iclass 24, count 0 2006.285.16:31:14.04#ibcon#about to write, iclass 24, count 0 2006.285.16:31:14.04#ibcon#wrote, iclass 24, count 0 2006.285.16:31:14.04#ibcon#about to read 3, iclass 24, count 0 2006.285.16:31:14.08#ibcon#read 3, iclass 24, count 0 2006.285.16:31:14.08#ibcon#about to read 4, iclass 24, count 0 2006.285.16:31:14.08#ibcon#read 4, iclass 24, count 0 2006.285.16:31:14.08#ibcon#about to read 5, iclass 24, count 0 2006.285.16:31:14.08#ibcon#read 5, iclass 24, count 0 2006.285.16:31:14.08#ibcon#about to read 6, iclass 24, count 0 2006.285.16:31:14.08#ibcon#read 6, iclass 24, count 0 2006.285.16:31:14.08#ibcon#end of sib2, iclass 24, count 0 2006.285.16:31:14.08#ibcon#*after write, iclass 24, count 0 2006.285.16:31:14.08#ibcon#*before return 0, iclass 24, count 0 2006.285.16:31:14.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:31:14.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:31:14.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.16:31:14.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.16:31:14.08$vck44/va=2,6 2006.285.16:31:14.08#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.16:31:14.08#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.16:31:14.08#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:14.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:31:14.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:31:14.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:31:14.14#ibcon#enter wrdev, iclass 26, count 2 2006.285.16:31:14.14#ibcon#first serial, iclass 26, count 2 2006.285.16:31:14.14#ibcon#enter sib2, iclass 26, count 2 2006.285.16:31:14.14#ibcon#flushed, iclass 26, count 2 2006.285.16:31:14.14#ibcon#about to write, iclass 26, count 2 2006.285.16:31:14.14#ibcon#wrote, iclass 26, count 2 2006.285.16:31:14.14#ibcon#about to read 3, iclass 26, count 2 2006.285.16:31:14.16#ibcon#read 3, iclass 26, count 2 2006.285.16:31:14.16#ibcon#about to read 4, iclass 26, count 2 2006.285.16:31:14.16#ibcon#read 4, iclass 26, count 2 2006.285.16:31:14.16#ibcon#about to read 5, iclass 26, count 2 2006.285.16:31:14.16#ibcon#read 5, iclass 26, count 2 2006.285.16:31:14.16#ibcon#about to read 6, iclass 26, count 2 2006.285.16:31:14.16#ibcon#read 6, iclass 26, count 2 2006.285.16:31:14.16#ibcon#end of sib2, iclass 26, count 2 2006.285.16:31:14.16#ibcon#*mode == 0, iclass 26, count 2 2006.285.16:31:14.16#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.16:31:14.16#ibcon#[25=AT02-06\r\n] 2006.285.16:31:14.16#ibcon#*before write, iclass 26, count 2 2006.285.16:31:14.16#ibcon#enter sib2, iclass 26, count 2 2006.285.16:31:14.16#ibcon#flushed, iclass 26, count 2 2006.285.16:31:14.16#ibcon#about to write, iclass 26, count 2 2006.285.16:31:14.16#ibcon#wrote, iclass 26, count 2 2006.285.16:31:14.16#ibcon#about to read 3, iclass 26, count 2 2006.285.16:31:14.19#ibcon#read 3, iclass 26, count 2 2006.285.16:31:14.19#ibcon#about to read 4, iclass 26, count 2 2006.285.16:31:14.19#ibcon#read 4, iclass 26, count 2 2006.285.16:31:14.19#ibcon#about to read 5, iclass 26, count 2 2006.285.16:31:14.19#ibcon#read 5, iclass 26, count 2 2006.285.16:31:14.19#ibcon#about to read 6, iclass 26, count 2 2006.285.16:31:14.19#ibcon#read 6, iclass 26, count 2 2006.285.16:31:14.19#ibcon#end of sib2, iclass 26, count 2 2006.285.16:31:14.19#ibcon#*after write, iclass 26, count 2 2006.285.16:31:14.19#ibcon#*before return 0, iclass 26, count 2 2006.285.16:31:14.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:31:14.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:31:14.19#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.16:31:14.19#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:14.19#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:31:14.31#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:31:14.31#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:31:14.31#ibcon#enter wrdev, iclass 26, count 0 2006.285.16:31:14.31#ibcon#first serial, iclass 26, count 0 2006.285.16:31:14.31#ibcon#enter sib2, iclass 26, count 0 2006.285.16:31:14.31#ibcon#flushed, iclass 26, count 0 2006.285.16:31:14.31#ibcon#about to write, iclass 26, count 0 2006.285.16:31:14.31#ibcon#wrote, iclass 26, count 0 2006.285.16:31:14.31#ibcon#about to read 3, iclass 26, count 0 2006.285.16:31:14.33#ibcon#read 3, iclass 26, count 0 2006.285.16:31:14.33#ibcon#about to read 4, iclass 26, count 0 2006.285.16:31:14.33#ibcon#read 4, iclass 26, count 0 2006.285.16:31:14.33#ibcon#about to read 5, iclass 26, count 0 2006.285.16:31:14.33#ibcon#read 5, iclass 26, count 0 2006.285.16:31:14.33#ibcon#about to read 6, iclass 26, count 0 2006.285.16:31:14.33#ibcon#read 6, iclass 26, count 0 2006.285.16:31:14.33#ibcon#end of sib2, iclass 26, count 0 2006.285.16:31:14.33#ibcon#*mode == 0, iclass 26, count 0 2006.285.16:31:14.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.16:31:14.33#ibcon#[25=USB\r\n] 2006.285.16:31:14.33#ibcon#*before write, iclass 26, count 0 2006.285.16:31:14.33#ibcon#enter sib2, iclass 26, count 0 2006.285.16:31:14.33#ibcon#flushed, iclass 26, count 0 2006.285.16:31:14.33#ibcon#about to write, iclass 26, count 0 2006.285.16:31:14.33#ibcon#wrote, iclass 26, count 0 2006.285.16:31:14.33#ibcon#about to read 3, iclass 26, count 0 2006.285.16:31:14.36#ibcon#read 3, iclass 26, count 0 2006.285.16:31:14.36#ibcon#about to read 4, iclass 26, count 0 2006.285.16:31:14.36#ibcon#read 4, iclass 26, count 0 2006.285.16:31:14.36#ibcon#about to read 5, iclass 26, count 0 2006.285.16:31:14.36#ibcon#read 5, iclass 26, count 0 2006.285.16:31:14.36#ibcon#about to read 6, iclass 26, count 0 2006.285.16:31:14.36#ibcon#read 6, iclass 26, count 0 2006.285.16:31:14.36#ibcon#end of sib2, iclass 26, count 0 2006.285.16:31:14.36#ibcon#*after write, iclass 26, count 0 2006.285.16:31:14.36#ibcon#*before return 0, iclass 26, count 0 2006.285.16:31:14.36#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:31:14.36#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:31:14.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.16:31:14.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.16:31:14.36$vck44/valo=3,564.99 2006.285.16:31:14.36#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.16:31:14.36#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.16:31:14.36#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:14.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:31:14.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:31:14.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:31:14.36#ibcon#enter wrdev, iclass 28, count 0 2006.285.16:31:14.36#ibcon#first serial, iclass 28, count 0 2006.285.16:31:14.36#ibcon#enter sib2, iclass 28, count 0 2006.285.16:31:14.36#ibcon#flushed, iclass 28, count 0 2006.285.16:31:14.36#ibcon#about to write, iclass 28, count 0 2006.285.16:31:14.36#ibcon#wrote, iclass 28, count 0 2006.285.16:31:14.36#ibcon#about to read 3, iclass 28, count 0 2006.285.16:31:14.38#ibcon#read 3, iclass 28, count 0 2006.285.16:31:14.38#ibcon#about to read 4, iclass 28, count 0 2006.285.16:31:14.38#ibcon#read 4, iclass 28, count 0 2006.285.16:31:14.38#ibcon#about to read 5, iclass 28, count 0 2006.285.16:31:14.38#ibcon#read 5, iclass 28, count 0 2006.285.16:31:14.38#ibcon#about to read 6, iclass 28, count 0 2006.285.16:31:14.38#ibcon#read 6, iclass 28, count 0 2006.285.16:31:14.38#ibcon#end of sib2, iclass 28, count 0 2006.285.16:31:14.38#ibcon#*mode == 0, iclass 28, count 0 2006.285.16:31:14.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.16:31:14.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.16:31:14.38#ibcon#*before write, iclass 28, count 0 2006.285.16:31:14.38#ibcon#enter sib2, iclass 28, count 0 2006.285.16:31:14.38#ibcon#flushed, iclass 28, count 0 2006.285.16:31:14.38#ibcon#about to write, iclass 28, count 0 2006.285.16:31:14.38#ibcon#wrote, iclass 28, count 0 2006.285.16:31:14.38#ibcon#about to read 3, iclass 28, count 0 2006.285.16:31:14.42#ibcon#read 3, iclass 28, count 0 2006.285.16:31:14.42#ibcon#about to read 4, iclass 28, count 0 2006.285.16:31:14.42#ibcon#read 4, iclass 28, count 0 2006.285.16:31:14.42#ibcon#about to read 5, iclass 28, count 0 2006.285.16:31:14.42#ibcon#read 5, iclass 28, count 0 2006.285.16:31:14.42#ibcon#about to read 6, iclass 28, count 0 2006.285.16:31:14.42#ibcon#read 6, iclass 28, count 0 2006.285.16:31:14.42#ibcon#end of sib2, iclass 28, count 0 2006.285.16:31:14.42#ibcon#*after write, iclass 28, count 0 2006.285.16:31:14.42#ibcon#*before return 0, iclass 28, count 0 2006.285.16:31:14.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:31:14.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:31:14.42#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.16:31:14.42#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.16:31:14.42$vck44/va=3,7 2006.285.16:31:14.42#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.16:31:14.42#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.16:31:14.42#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:14.42#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:31:14.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:31:14.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:31:14.48#ibcon#enter wrdev, iclass 30, count 2 2006.285.16:31:14.48#ibcon#first serial, iclass 30, count 2 2006.285.16:31:14.48#ibcon#enter sib2, iclass 30, count 2 2006.285.16:31:14.48#ibcon#flushed, iclass 30, count 2 2006.285.16:31:14.48#ibcon#about to write, iclass 30, count 2 2006.285.16:31:14.48#ibcon#wrote, iclass 30, count 2 2006.285.16:31:14.48#ibcon#about to read 3, iclass 30, count 2 2006.285.16:31:14.50#ibcon#read 3, iclass 30, count 2 2006.285.16:31:14.50#ibcon#about to read 4, iclass 30, count 2 2006.285.16:31:14.50#ibcon#read 4, iclass 30, count 2 2006.285.16:31:14.50#ibcon#about to read 5, iclass 30, count 2 2006.285.16:31:14.50#ibcon#read 5, iclass 30, count 2 2006.285.16:31:14.50#ibcon#about to read 6, iclass 30, count 2 2006.285.16:31:14.50#ibcon#read 6, iclass 30, count 2 2006.285.16:31:14.50#ibcon#end of sib2, iclass 30, count 2 2006.285.16:31:14.50#ibcon#*mode == 0, iclass 30, count 2 2006.285.16:31:14.50#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.16:31:14.50#ibcon#[25=AT03-07\r\n] 2006.285.16:31:14.50#ibcon#*before write, iclass 30, count 2 2006.285.16:31:14.50#ibcon#enter sib2, iclass 30, count 2 2006.285.16:31:14.50#ibcon#flushed, iclass 30, count 2 2006.285.16:31:14.50#ibcon#about to write, iclass 30, count 2 2006.285.16:31:14.50#ibcon#wrote, iclass 30, count 2 2006.285.16:31:14.50#ibcon#about to read 3, iclass 30, count 2 2006.285.16:31:14.53#ibcon#read 3, iclass 30, count 2 2006.285.16:31:14.53#ibcon#about to read 4, iclass 30, count 2 2006.285.16:31:14.53#ibcon#read 4, iclass 30, count 2 2006.285.16:31:14.53#ibcon#about to read 5, iclass 30, count 2 2006.285.16:31:14.53#ibcon#read 5, iclass 30, count 2 2006.285.16:31:14.53#ibcon#about to read 6, iclass 30, count 2 2006.285.16:31:14.53#ibcon#read 6, iclass 30, count 2 2006.285.16:31:14.53#ibcon#end of sib2, iclass 30, count 2 2006.285.16:31:14.53#ibcon#*after write, iclass 30, count 2 2006.285.16:31:14.53#ibcon#*before return 0, iclass 30, count 2 2006.285.16:31:14.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:31:14.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:31:14.53#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.16:31:14.53#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:14.53#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:31:14.65#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:31:14.65#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:31:14.65#ibcon#enter wrdev, iclass 30, count 0 2006.285.16:31:14.65#ibcon#first serial, iclass 30, count 0 2006.285.16:31:14.65#ibcon#enter sib2, iclass 30, count 0 2006.285.16:31:14.65#ibcon#flushed, iclass 30, count 0 2006.285.16:31:14.65#ibcon#about to write, iclass 30, count 0 2006.285.16:31:14.65#ibcon#wrote, iclass 30, count 0 2006.285.16:31:14.65#ibcon#about to read 3, iclass 30, count 0 2006.285.16:31:14.67#ibcon#read 3, iclass 30, count 0 2006.285.16:31:14.67#ibcon#about to read 4, iclass 30, count 0 2006.285.16:31:14.67#ibcon#read 4, iclass 30, count 0 2006.285.16:31:14.67#ibcon#about to read 5, iclass 30, count 0 2006.285.16:31:14.67#ibcon#read 5, iclass 30, count 0 2006.285.16:31:14.67#ibcon#about to read 6, iclass 30, count 0 2006.285.16:31:14.67#ibcon#read 6, iclass 30, count 0 2006.285.16:31:14.67#ibcon#end of sib2, iclass 30, count 0 2006.285.16:31:14.67#ibcon#*mode == 0, iclass 30, count 0 2006.285.16:31:14.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.16:31:14.67#ibcon#[25=USB\r\n] 2006.285.16:31:14.67#ibcon#*before write, iclass 30, count 0 2006.285.16:31:14.67#ibcon#enter sib2, iclass 30, count 0 2006.285.16:31:14.67#ibcon#flushed, iclass 30, count 0 2006.285.16:31:14.67#ibcon#about to write, iclass 30, count 0 2006.285.16:31:14.67#ibcon#wrote, iclass 30, count 0 2006.285.16:31:14.67#ibcon#about to read 3, iclass 30, count 0 2006.285.16:31:14.70#ibcon#read 3, iclass 30, count 0 2006.285.16:31:14.70#ibcon#about to read 4, iclass 30, count 0 2006.285.16:31:14.70#ibcon#read 4, iclass 30, count 0 2006.285.16:31:14.70#ibcon#about to read 5, iclass 30, count 0 2006.285.16:31:14.70#ibcon#read 5, iclass 30, count 0 2006.285.16:31:14.70#ibcon#about to read 6, iclass 30, count 0 2006.285.16:31:14.70#ibcon#read 6, iclass 30, count 0 2006.285.16:31:14.70#ibcon#end of sib2, iclass 30, count 0 2006.285.16:31:14.70#ibcon#*after write, iclass 30, count 0 2006.285.16:31:14.70#ibcon#*before return 0, iclass 30, count 0 2006.285.16:31:14.70#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:31:14.70#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:31:14.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.16:31:14.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.16:31:14.70$vck44/valo=4,624.99 2006.285.16:31:14.70#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.16:31:14.70#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.16:31:14.70#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:14.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:31:14.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:31:14.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:31:14.70#ibcon#enter wrdev, iclass 32, count 0 2006.285.16:31:14.70#ibcon#first serial, iclass 32, count 0 2006.285.16:31:14.70#ibcon#enter sib2, iclass 32, count 0 2006.285.16:31:14.70#ibcon#flushed, iclass 32, count 0 2006.285.16:31:14.70#ibcon#about to write, iclass 32, count 0 2006.285.16:31:14.70#ibcon#wrote, iclass 32, count 0 2006.285.16:31:14.70#ibcon#about to read 3, iclass 32, count 0 2006.285.16:31:14.72#ibcon#read 3, iclass 32, count 0 2006.285.16:31:14.72#ibcon#about to read 4, iclass 32, count 0 2006.285.16:31:14.72#ibcon#read 4, iclass 32, count 0 2006.285.16:31:14.72#ibcon#about to read 5, iclass 32, count 0 2006.285.16:31:14.72#ibcon#read 5, iclass 32, count 0 2006.285.16:31:14.72#ibcon#about to read 6, iclass 32, count 0 2006.285.16:31:14.72#ibcon#read 6, iclass 32, count 0 2006.285.16:31:14.72#ibcon#end of sib2, iclass 32, count 0 2006.285.16:31:14.72#ibcon#*mode == 0, iclass 32, count 0 2006.285.16:31:14.72#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.16:31:14.72#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.16:31:14.72#ibcon#*before write, iclass 32, count 0 2006.285.16:31:14.72#ibcon#enter sib2, iclass 32, count 0 2006.285.16:31:14.72#ibcon#flushed, iclass 32, count 0 2006.285.16:31:14.72#ibcon#about to write, iclass 32, count 0 2006.285.16:31:14.72#ibcon#wrote, iclass 32, count 0 2006.285.16:31:14.72#ibcon#about to read 3, iclass 32, count 0 2006.285.16:31:14.76#ibcon#read 3, iclass 32, count 0 2006.285.16:31:14.76#ibcon#about to read 4, iclass 32, count 0 2006.285.16:31:14.76#ibcon#read 4, iclass 32, count 0 2006.285.16:31:14.76#ibcon#about to read 5, iclass 32, count 0 2006.285.16:31:14.76#ibcon#read 5, iclass 32, count 0 2006.285.16:31:14.76#ibcon#about to read 6, iclass 32, count 0 2006.285.16:31:14.76#ibcon#read 6, iclass 32, count 0 2006.285.16:31:14.76#ibcon#end of sib2, iclass 32, count 0 2006.285.16:31:14.76#ibcon#*after write, iclass 32, count 0 2006.285.16:31:14.76#ibcon#*before return 0, iclass 32, count 0 2006.285.16:31:14.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:31:14.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:31:14.76#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.16:31:14.76#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.16:31:14.76$vck44/va=4,6 2006.285.16:31:14.76#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.16:31:14.76#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.16:31:14.76#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:14.76#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:31:14.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:31:14.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:31:14.82#ibcon#enter wrdev, iclass 34, count 2 2006.285.16:31:14.82#ibcon#first serial, iclass 34, count 2 2006.285.16:31:14.82#ibcon#enter sib2, iclass 34, count 2 2006.285.16:31:14.82#ibcon#flushed, iclass 34, count 2 2006.285.16:31:14.82#ibcon#about to write, iclass 34, count 2 2006.285.16:31:14.82#ibcon#wrote, iclass 34, count 2 2006.285.16:31:14.82#ibcon#about to read 3, iclass 34, count 2 2006.285.16:31:14.84#ibcon#read 3, iclass 34, count 2 2006.285.16:31:14.84#ibcon#about to read 4, iclass 34, count 2 2006.285.16:31:14.84#ibcon#read 4, iclass 34, count 2 2006.285.16:31:14.84#ibcon#about to read 5, iclass 34, count 2 2006.285.16:31:14.84#ibcon#read 5, iclass 34, count 2 2006.285.16:31:14.84#ibcon#about to read 6, iclass 34, count 2 2006.285.16:31:14.84#ibcon#read 6, iclass 34, count 2 2006.285.16:31:14.84#ibcon#end of sib2, iclass 34, count 2 2006.285.16:31:14.84#ibcon#*mode == 0, iclass 34, count 2 2006.285.16:31:14.84#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.16:31:14.84#ibcon#[25=AT04-06\r\n] 2006.285.16:31:14.84#ibcon#*before write, iclass 34, count 2 2006.285.16:31:14.84#ibcon#enter sib2, iclass 34, count 2 2006.285.16:31:14.84#ibcon#flushed, iclass 34, count 2 2006.285.16:31:14.84#ibcon#about to write, iclass 34, count 2 2006.285.16:31:14.84#ibcon#wrote, iclass 34, count 2 2006.285.16:31:14.84#ibcon#about to read 3, iclass 34, count 2 2006.285.16:31:14.87#ibcon#read 3, iclass 34, count 2 2006.285.16:31:14.87#ibcon#about to read 4, iclass 34, count 2 2006.285.16:31:14.87#ibcon#read 4, iclass 34, count 2 2006.285.16:31:14.87#ibcon#about to read 5, iclass 34, count 2 2006.285.16:31:14.87#ibcon#read 5, iclass 34, count 2 2006.285.16:31:14.87#ibcon#about to read 6, iclass 34, count 2 2006.285.16:31:14.87#ibcon#read 6, iclass 34, count 2 2006.285.16:31:14.87#ibcon#end of sib2, iclass 34, count 2 2006.285.16:31:14.87#ibcon#*after write, iclass 34, count 2 2006.285.16:31:14.87#ibcon#*before return 0, iclass 34, count 2 2006.285.16:31:14.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:31:14.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:31:14.87#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.16:31:14.87#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:14.87#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:31:14.99#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:31:15.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:31:15.22#ibcon#enter wrdev, iclass 34, count 0 2006.285.16:31:15.22#ibcon#first serial, iclass 34, count 0 2006.285.16:31:15.22#ibcon#enter sib2, iclass 34, count 0 2006.285.16:31:15.22#ibcon#flushed, iclass 34, count 0 2006.285.16:31:15.22#ibcon#about to write, iclass 34, count 0 2006.285.16:31:15.22#ibcon#wrote, iclass 34, count 0 2006.285.16:31:15.22#ibcon#about to read 3, iclass 34, count 0 2006.285.16:31:15.24#ibcon#read 3, iclass 34, count 0 2006.285.16:31:15.24#ibcon#about to read 4, iclass 34, count 0 2006.285.16:31:15.24#ibcon#read 4, iclass 34, count 0 2006.285.16:31:15.24#ibcon#about to read 5, iclass 34, count 0 2006.285.16:31:15.24#ibcon#read 5, iclass 34, count 0 2006.285.16:31:15.24#ibcon#about to read 6, iclass 34, count 0 2006.285.16:31:15.24#ibcon#read 6, iclass 34, count 0 2006.285.16:31:15.24#ibcon#end of sib2, iclass 34, count 0 2006.285.16:31:15.24#ibcon#*mode == 0, iclass 34, count 0 2006.285.16:31:15.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.16:31:15.24#ibcon#[25=USB\r\n] 2006.285.16:31:15.24#ibcon#*before write, iclass 34, count 0 2006.285.16:31:15.24#ibcon#enter sib2, iclass 34, count 0 2006.285.16:31:15.24#ibcon#flushed, iclass 34, count 0 2006.285.16:31:15.24#ibcon#about to write, iclass 34, count 0 2006.285.16:31:15.24#ibcon#wrote, iclass 34, count 0 2006.285.16:31:15.24#ibcon#about to read 3, iclass 34, count 0 2006.285.16:31:15.27#ibcon#read 3, iclass 34, count 0 2006.285.16:31:15.27#ibcon#about to read 4, iclass 34, count 0 2006.285.16:31:15.27#ibcon#read 4, iclass 34, count 0 2006.285.16:31:15.27#ibcon#about to read 5, iclass 34, count 0 2006.285.16:31:15.27#ibcon#read 5, iclass 34, count 0 2006.285.16:31:15.27#ibcon#about to read 6, iclass 34, count 0 2006.285.16:31:15.27#ibcon#read 6, iclass 34, count 0 2006.285.16:31:15.27#ibcon#end of sib2, iclass 34, count 0 2006.285.16:31:15.27#ibcon#*after write, iclass 34, count 0 2006.285.16:31:15.27#ibcon#*before return 0, iclass 34, count 0 2006.285.16:31:15.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:31:15.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:31:15.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.16:31:15.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.16:31:15.27$vck44/valo=5,734.99 2006.285.16:31:15.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.16:31:15.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.16:31:15.27#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:15.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:31:15.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:31:15.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:31:15.27#ibcon#enter wrdev, iclass 36, count 0 2006.285.16:31:15.27#ibcon#first serial, iclass 36, count 0 2006.285.16:31:15.27#ibcon#enter sib2, iclass 36, count 0 2006.285.16:31:15.27#ibcon#flushed, iclass 36, count 0 2006.285.16:31:15.27#ibcon#about to write, iclass 36, count 0 2006.285.16:31:15.27#ibcon#wrote, iclass 36, count 0 2006.285.16:31:15.27#ibcon#about to read 3, iclass 36, count 0 2006.285.16:31:15.29#ibcon#read 3, iclass 36, count 0 2006.285.16:31:15.29#ibcon#about to read 4, iclass 36, count 0 2006.285.16:31:15.29#ibcon#read 4, iclass 36, count 0 2006.285.16:31:15.29#ibcon#about to read 5, iclass 36, count 0 2006.285.16:31:15.29#ibcon#read 5, iclass 36, count 0 2006.285.16:31:15.29#ibcon#about to read 6, iclass 36, count 0 2006.285.16:31:15.29#ibcon#read 6, iclass 36, count 0 2006.285.16:31:15.29#ibcon#end of sib2, iclass 36, count 0 2006.285.16:31:15.29#ibcon#*mode == 0, iclass 36, count 0 2006.285.16:31:15.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.16:31:15.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.16:31:15.29#ibcon#*before write, iclass 36, count 0 2006.285.16:31:15.29#ibcon#enter sib2, iclass 36, count 0 2006.285.16:31:15.29#ibcon#flushed, iclass 36, count 0 2006.285.16:31:15.29#ibcon#about to write, iclass 36, count 0 2006.285.16:31:15.29#ibcon#wrote, iclass 36, count 0 2006.285.16:31:15.29#ibcon#about to read 3, iclass 36, count 0 2006.285.16:31:15.33#ibcon#read 3, iclass 36, count 0 2006.285.16:31:15.33#ibcon#about to read 4, iclass 36, count 0 2006.285.16:31:15.33#ibcon#read 4, iclass 36, count 0 2006.285.16:31:15.33#ibcon#about to read 5, iclass 36, count 0 2006.285.16:31:15.33#ibcon#read 5, iclass 36, count 0 2006.285.16:31:15.33#ibcon#about to read 6, iclass 36, count 0 2006.285.16:31:15.33#ibcon#read 6, iclass 36, count 0 2006.285.16:31:15.33#ibcon#end of sib2, iclass 36, count 0 2006.285.16:31:15.33#ibcon#*after write, iclass 36, count 0 2006.285.16:31:15.33#ibcon#*before return 0, iclass 36, count 0 2006.285.16:31:15.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:31:15.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:31:15.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.16:31:15.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.16:31:15.33$vck44/va=5,3 2006.285.16:31:15.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.16:31:15.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.16:31:15.33#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:15.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:31:15.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:31:15.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:31:15.39#ibcon#enter wrdev, iclass 38, count 2 2006.285.16:31:15.39#ibcon#first serial, iclass 38, count 2 2006.285.16:31:15.39#ibcon#enter sib2, iclass 38, count 2 2006.285.16:31:15.39#ibcon#flushed, iclass 38, count 2 2006.285.16:31:15.39#ibcon#about to write, iclass 38, count 2 2006.285.16:31:15.39#ibcon#wrote, iclass 38, count 2 2006.285.16:31:15.39#ibcon#about to read 3, iclass 38, count 2 2006.285.16:31:15.41#ibcon#read 3, iclass 38, count 2 2006.285.16:31:15.41#ibcon#about to read 4, iclass 38, count 2 2006.285.16:31:15.41#ibcon#read 4, iclass 38, count 2 2006.285.16:31:15.41#ibcon#about to read 5, iclass 38, count 2 2006.285.16:31:15.41#ibcon#read 5, iclass 38, count 2 2006.285.16:31:15.41#ibcon#about to read 6, iclass 38, count 2 2006.285.16:31:15.41#ibcon#read 6, iclass 38, count 2 2006.285.16:31:15.41#ibcon#end of sib2, iclass 38, count 2 2006.285.16:31:15.41#ibcon#*mode == 0, iclass 38, count 2 2006.285.16:31:15.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.16:31:15.41#ibcon#[25=AT05-03\r\n] 2006.285.16:31:15.41#ibcon#*before write, iclass 38, count 2 2006.285.16:31:15.41#ibcon#enter sib2, iclass 38, count 2 2006.285.16:31:15.41#ibcon#flushed, iclass 38, count 2 2006.285.16:31:15.41#ibcon#about to write, iclass 38, count 2 2006.285.16:31:15.41#ibcon#wrote, iclass 38, count 2 2006.285.16:31:15.41#ibcon#about to read 3, iclass 38, count 2 2006.285.16:31:15.44#ibcon#read 3, iclass 38, count 2 2006.285.16:31:15.44#ibcon#about to read 4, iclass 38, count 2 2006.285.16:31:15.44#ibcon#read 4, iclass 38, count 2 2006.285.16:31:15.44#ibcon#about to read 5, iclass 38, count 2 2006.285.16:31:15.44#ibcon#read 5, iclass 38, count 2 2006.285.16:31:15.44#ibcon#about to read 6, iclass 38, count 2 2006.285.16:31:15.44#ibcon#read 6, iclass 38, count 2 2006.285.16:31:15.44#ibcon#end of sib2, iclass 38, count 2 2006.285.16:31:15.44#ibcon#*after write, iclass 38, count 2 2006.285.16:31:15.44#ibcon#*before return 0, iclass 38, count 2 2006.285.16:31:15.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:31:15.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:31:15.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.16:31:15.44#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:15.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:31:15.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:31:15.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:31:15.56#ibcon#enter wrdev, iclass 38, count 0 2006.285.16:31:15.56#ibcon#first serial, iclass 38, count 0 2006.285.16:31:15.56#ibcon#enter sib2, iclass 38, count 0 2006.285.16:31:15.56#ibcon#flushed, iclass 38, count 0 2006.285.16:31:15.56#ibcon#about to write, iclass 38, count 0 2006.285.16:31:15.56#ibcon#wrote, iclass 38, count 0 2006.285.16:31:15.56#ibcon#about to read 3, iclass 38, count 0 2006.285.16:31:15.58#ibcon#read 3, iclass 38, count 0 2006.285.16:31:15.58#ibcon#about to read 4, iclass 38, count 0 2006.285.16:31:15.58#ibcon#read 4, iclass 38, count 0 2006.285.16:31:15.58#ibcon#about to read 5, iclass 38, count 0 2006.285.16:31:15.58#ibcon#read 5, iclass 38, count 0 2006.285.16:31:15.58#ibcon#about to read 6, iclass 38, count 0 2006.285.16:31:15.58#ibcon#read 6, iclass 38, count 0 2006.285.16:31:15.73#ibcon#end of sib2, iclass 38, count 0 2006.285.16:31:15.73#ibcon#*mode == 0, iclass 38, count 0 2006.285.16:31:15.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.16:31:15.73#ibcon#[25=USB\r\n] 2006.285.16:31:15.73#ibcon#*before write, iclass 38, count 0 2006.285.16:31:15.73#ibcon#enter sib2, iclass 38, count 0 2006.285.16:31:15.73#ibcon#flushed, iclass 38, count 0 2006.285.16:31:15.73#ibcon#about to write, iclass 38, count 0 2006.285.16:31:15.73#ibcon#wrote, iclass 38, count 0 2006.285.16:31:15.73#ibcon#about to read 3, iclass 38, count 0 2006.285.16:31:15.77#ibcon#read 3, iclass 38, count 0 2006.285.16:31:15.77#ibcon#about to read 4, iclass 38, count 0 2006.285.16:31:15.77#ibcon#read 4, iclass 38, count 0 2006.285.16:31:15.77#ibcon#about to read 5, iclass 38, count 0 2006.285.16:31:15.77#ibcon#read 5, iclass 38, count 0 2006.285.16:31:15.77#ibcon#about to read 6, iclass 38, count 0 2006.285.16:31:15.77#ibcon#read 6, iclass 38, count 0 2006.285.16:31:15.77#ibcon#end of sib2, iclass 38, count 0 2006.285.16:31:15.77#ibcon#*after write, iclass 38, count 0 2006.285.16:31:15.77#ibcon#*before return 0, iclass 38, count 0 2006.285.16:31:15.77#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:31:15.77#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:31:15.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.16:31:15.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.16:31:15.77$vck44/valo=6,814.99 2006.285.16:31:15.77#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.16:31:15.77#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.16:31:15.77#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:15.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:31:15.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:31:15.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:31:15.77#ibcon#enter wrdev, iclass 40, count 0 2006.285.16:31:15.77#ibcon#first serial, iclass 40, count 0 2006.285.16:31:15.77#ibcon#enter sib2, iclass 40, count 0 2006.285.16:31:15.77#ibcon#flushed, iclass 40, count 0 2006.285.16:31:15.77#ibcon#about to write, iclass 40, count 0 2006.285.16:31:15.77#ibcon#wrote, iclass 40, count 0 2006.285.16:31:15.77#ibcon#about to read 3, iclass 40, count 0 2006.285.16:31:15.79#ibcon#read 3, iclass 40, count 0 2006.285.16:31:15.79#ibcon#about to read 4, iclass 40, count 0 2006.285.16:31:15.79#ibcon#read 4, iclass 40, count 0 2006.285.16:31:15.79#ibcon#about to read 5, iclass 40, count 0 2006.285.16:31:15.79#ibcon#read 5, iclass 40, count 0 2006.285.16:31:15.79#ibcon#about to read 6, iclass 40, count 0 2006.285.16:31:15.79#ibcon#read 6, iclass 40, count 0 2006.285.16:31:15.79#ibcon#end of sib2, iclass 40, count 0 2006.285.16:31:15.79#ibcon#*mode == 0, iclass 40, count 0 2006.285.16:31:15.79#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.16:31:15.79#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.16:31:15.79#ibcon#*before write, iclass 40, count 0 2006.285.16:31:15.79#ibcon#enter sib2, iclass 40, count 0 2006.285.16:31:15.79#ibcon#flushed, iclass 40, count 0 2006.285.16:31:15.79#ibcon#about to write, iclass 40, count 0 2006.285.16:31:15.79#ibcon#wrote, iclass 40, count 0 2006.285.16:31:15.79#ibcon#about to read 3, iclass 40, count 0 2006.285.16:31:15.83#ibcon#read 3, iclass 40, count 0 2006.285.16:31:15.83#ibcon#about to read 4, iclass 40, count 0 2006.285.16:31:15.83#ibcon#read 4, iclass 40, count 0 2006.285.16:31:15.83#ibcon#about to read 5, iclass 40, count 0 2006.285.16:31:15.83#ibcon#read 5, iclass 40, count 0 2006.285.16:31:15.83#ibcon#about to read 6, iclass 40, count 0 2006.285.16:31:15.83#ibcon#read 6, iclass 40, count 0 2006.285.16:31:15.83#ibcon#end of sib2, iclass 40, count 0 2006.285.16:31:15.83#ibcon#*after write, iclass 40, count 0 2006.285.16:31:15.83#ibcon#*before return 0, iclass 40, count 0 2006.285.16:31:15.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:31:15.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:31:15.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.16:31:15.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.16:31:15.83$vck44/va=6,4 2006.285.16:31:15.83#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.16:31:15.83#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.16:31:15.83#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:15.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:31:15.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:31:15.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:31:15.89#ibcon#enter wrdev, iclass 4, count 2 2006.285.16:31:15.89#ibcon#first serial, iclass 4, count 2 2006.285.16:31:15.89#ibcon#enter sib2, iclass 4, count 2 2006.285.16:31:15.89#ibcon#flushed, iclass 4, count 2 2006.285.16:31:15.89#ibcon#about to write, iclass 4, count 2 2006.285.16:31:15.89#ibcon#wrote, iclass 4, count 2 2006.285.16:31:15.89#ibcon#about to read 3, iclass 4, count 2 2006.285.16:31:15.91#ibcon#read 3, iclass 4, count 2 2006.285.16:31:15.91#ibcon#about to read 4, iclass 4, count 2 2006.285.16:31:15.91#ibcon#read 4, iclass 4, count 2 2006.285.16:31:15.91#ibcon#about to read 5, iclass 4, count 2 2006.285.16:31:15.91#ibcon#read 5, iclass 4, count 2 2006.285.16:31:15.91#ibcon#about to read 6, iclass 4, count 2 2006.285.16:31:15.91#ibcon#read 6, iclass 4, count 2 2006.285.16:31:15.91#ibcon#end of sib2, iclass 4, count 2 2006.285.16:31:15.91#ibcon#*mode == 0, iclass 4, count 2 2006.285.16:31:15.91#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.16:31:15.91#ibcon#[25=AT06-04\r\n] 2006.285.16:31:15.91#ibcon#*before write, iclass 4, count 2 2006.285.16:31:15.91#ibcon#enter sib2, iclass 4, count 2 2006.285.16:31:15.91#ibcon#flushed, iclass 4, count 2 2006.285.16:31:15.91#ibcon#about to write, iclass 4, count 2 2006.285.16:31:15.91#ibcon#wrote, iclass 4, count 2 2006.285.16:31:15.91#ibcon#about to read 3, iclass 4, count 2 2006.285.16:31:15.94#ibcon#read 3, iclass 4, count 2 2006.285.16:31:15.94#ibcon#about to read 4, iclass 4, count 2 2006.285.16:31:15.94#ibcon#read 4, iclass 4, count 2 2006.285.16:31:15.94#ibcon#about to read 5, iclass 4, count 2 2006.285.16:31:15.94#ibcon#read 5, iclass 4, count 2 2006.285.16:31:15.94#ibcon#about to read 6, iclass 4, count 2 2006.285.16:31:15.94#ibcon#read 6, iclass 4, count 2 2006.285.16:31:15.94#ibcon#end of sib2, iclass 4, count 2 2006.285.16:31:15.94#ibcon#*after write, iclass 4, count 2 2006.285.16:31:15.94#ibcon#*before return 0, iclass 4, count 2 2006.285.16:31:15.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:31:15.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:31:15.94#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.16:31:15.94#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:15.94#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:31:16.06#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:31:16.06#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:31:16.06#ibcon#enter wrdev, iclass 4, count 0 2006.285.16:31:16.06#ibcon#first serial, iclass 4, count 0 2006.285.16:31:16.06#ibcon#enter sib2, iclass 4, count 0 2006.285.16:31:16.06#ibcon#flushed, iclass 4, count 0 2006.285.16:31:16.06#ibcon#about to write, iclass 4, count 0 2006.285.16:31:16.06#ibcon#wrote, iclass 4, count 0 2006.285.16:31:16.06#ibcon#about to read 3, iclass 4, count 0 2006.285.16:31:16.08#ibcon#read 3, iclass 4, count 0 2006.285.16:31:16.08#ibcon#about to read 4, iclass 4, count 0 2006.285.16:31:16.08#ibcon#read 4, iclass 4, count 0 2006.285.16:31:16.08#ibcon#about to read 5, iclass 4, count 0 2006.285.16:31:16.08#ibcon#read 5, iclass 4, count 0 2006.285.16:31:16.08#ibcon#about to read 6, iclass 4, count 0 2006.285.16:31:16.08#ibcon#read 6, iclass 4, count 0 2006.285.16:31:16.08#ibcon#end of sib2, iclass 4, count 0 2006.285.16:31:16.08#ibcon#*mode == 0, iclass 4, count 0 2006.285.16:31:16.08#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.16:31:16.08#ibcon#[25=USB\r\n] 2006.285.16:31:16.08#ibcon#*before write, iclass 4, count 0 2006.285.16:31:16.08#ibcon#enter sib2, iclass 4, count 0 2006.285.16:31:16.08#ibcon#flushed, iclass 4, count 0 2006.285.16:31:16.08#ibcon#about to write, iclass 4, count 0 2006.285.16:31:16.08#ibcon#wrote, iclass 4, count 0 2006.285.16:31:16.08#ibcon#about to read 3, iclass 4, count 0 2006.285.16:31:16.11#ibcon#read 3, iclass 4, count 0 2006.285.16:31:16.11#ibcon#about to read 4, iclass 4, count 0 2006.285.16:31:16.11#ibcon#read 4, iclass 4, count 0 2006.285.16:31:16.11#ibcon#about to read 5, iclass 4, count 0 2006.285.16:31:16.11#ibcon#read 5, iclass 4, count 0 2006.285.16:31:16.11#ibcon#about to read 6, iclass 4, count 0 2006.285.16:31:16.11#ibcon#read 6, iclass 4, count 0 2006.285.16:31:16.11#ibcon#end of sib2, iclass 4, count 0 2006.285.16:31:16.11#ibcon#*after write, iclass 4, count 0 2006.285.16:31:16.11#ibcon#*before return 0, iclass 4, count 0 2006.285.16:31:16.11#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:31:16.11#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:31:16.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.16:31:16.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.16:31:16.11$vck44/valo=7,864.99 2006.285.16:31:16.11#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.16:31:16.11#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.16:31:16.11#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:16.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.16:31:16.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.16:31:16.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.16:31:16.11#ibcon#enter wrdev, iclass 6, count 0 2006.285.16:31:16.11#ibcon#first serial, iclass 6, count 0 2006.285.16:31:16.11#ibcon#enter sib2, iclass 6, count 0 2006.285.16:31:16.11#ibcon#flushed, iclass 6, count 0 2006.285.16:31:16.11#ibcon#about to write, iclass 6, count 0 2006.285.16:31:16.11#ibcon#wrote, iclass 6, count 0 2006.285.16:31:16.11#ibcon#about to read 3, iclass 6, count 0 2006.285.16:31:16.13#ibcon#read 3, iclass 6, count 0 2006.285.16:31:16.13#ibcon#about to read 4, iclass 6, count 0 2006.285.16:31:16.13#ibcon#read 4, iclass 6, count 0 2006.285.16:31:16.13#ibcon#about to read 5, iclass 6, count 0 2006.285.16:31:16.13#ibcon#read 5, iclass 6, count 0 2006.285.16:31:16.13#ibcon#about to read 6, iclass 6, count 0 2006.285.16:31:16.13#ibcon#read 6, iclass 6, count 0 2006.285.16:31:16.13#ibcon#end of sib2, iclass 6, count 0 2006.285.16:31:16.13#ibcon#*mode == 0, iclass 6, count 0 2006.285.16:31:16.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.16:31:16.13#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.16:31:16.13#ibcon#*before write, iclass 6, count 0 2006.285.16:31:16.13#ibcon#enter sib2, iclass 6, count 0 2006.285.16:31:16.13#ibcon#flushed, iclass 6, count 0 2006.285.16:31:16.13#ibcon#about to write, iclass 6, count 0 2006.285.16:31:16.13#ibcon#wrote, iclass 6, count 0 2006.285.16:31:16.13#ibcon#about to read 3, iclass 6, count 0 2006.285.16:31:16.17#ibcon#read 3, iclass 6, count 0 2006.285.16:31:16.17#ibcon#about to read 4, iclass 6, count 0 2006.285.16:31:16.17#ibcon#read 4, iclass 6, count 0 2006.285.16:31:16.17#ibcon#about to read 5, iclass 6, count 0 2006.285.16:31:16.17#ibcon#read 5, iclass 6, count 0 2006.285.16:31:16.17#ibcon#about to read 6, iclass 6, count 0 2006.285.16:31:16.17#ibcon#read 6, iclass 6, count 0 2006.285.16:31:16.17#ibcon#end of sib2, iclass 6, count 0 2006.285.16:31:16.17#ibcon#*after write, iclass 6, count 0 2006.285.16:31:16.17#ibcon#*before return 0, iclass 6, count 0 2006.285.16:31:16.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.16:31:16.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.16:31:16.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.16:31:16.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.16:31:16.17$vck44/va=7,4 2006.285.16:31:16.17#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.16:31:16.17#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.16:31:16.17#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:16.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.16:31:16.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.16:31:16.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.16:31:16.23#ibcon#enter wrdev, iclass 10, count 2 2006.285.16:31:16.23#ibcon#first serial, iclass 10, count 2 2006.285.16:31:16.23#ibcon#enter sib2, iclass 10, count 2 2006.285.16:31:16.23#ibcon#flushed, iclass 10, count 2 2006.285.16:31:16.23#ibcon#about to write, iclass 10, count 2 2006.285.16:31:16.23#ibcon#wrote, iclass 10, count 2 2006.285.16:31:16.23#ibcon#about to read 3, iclass 10, count 2 2006.285.16:31:16.25#ibcon#read 3, iclass 10, count 2 2006.285.16:31:16.25#ibcon#about to read 4, iclass 10, count 2 2006.285.16:31:16.25#ibcon#read 4, iclass 10, count 2 2006.285.16:31:16.25#ibcon#about to read 5, iclass 10, count 2 2006.285.16:31:16.25#ibcon#read 5, iclass 10, count 2 2006.285.16:31:16.25#ibcon#about to read 6, iclass 10, count 2 2006.285.16:31:16.25#ibcon#read 6, iclass 10, count 2 2006.285.16:31:16.25#ibcon#end of sib2, iclass 10, count 2 2006.285.16:31:16.25#ibcon#*mode == 0, iclass 10, count 2 2006.285.16:31:16.25#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.16:31:16.25#ibcon#[25=AT07-04\r\n] 2006.285.16:31:16.25#ibcon#*before write, iclass 10, count 2 2006.285.16:31:16.25#ibcon#enter sib2, iclass 10, count 2 2006.285.16:31:16.25#ibcon#flushed, iclass 10, count 2 2006.285.16:31:16.25#ibcon#about to write, iclass 10, count 2 2006.285.16:31:16.25#ibcon#wrote, iclass 10, count 2 2006.285.16:31:16.25#ibcon#about to read 3, iclass 10, count 2 2006.285.16:31:16.28#ibcon#read 3, iclass 10, count 2 2006.285.16:31:16.28#ibcon#about to read 4, iclass 10, count 2 2006.285.16:31:16.28#ibcon#read 4, iclass 10, count 2 2006.285.16:31:16.28#ibcon#about to read 5, iclass 10, count 2 2006.285.16:31:16.28#ibcon#read 5, iclass 10, count 2 2006.285.16:31:16.28#ibcon#about to read 6, iclass 10, count 2 2006.285.16:31:16.28#ibcon#read 6, iclass 10, count 2 2006.285.16:31:16.28#ibcon#end of sib2, iclass 10, count 2 2006.285.16:31:16.28#ibcon#*after write, iclass 10, count 2 2006.285.16:31:16.28#ibcon#*before return 0, iclass 10, count 2 2006.285.16:31:16.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.16:31:16.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.16:31:16.28#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.16:31:16.28#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:16.28#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.16:31:16.40#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.16:31:16.40#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.16:31:16.40#ibcon#enter wrdev, iclass 10, count 0 2006.285.16:31:16.40#ibcon#first serial, iclass 10, count 0 2006.285.16:31:16.40#ibcon#enter sib2, iclass 10, count 0 2006.285.16:31:16.40#ibcon#flushed, iclass 10, count 0 2006.285.16:31:16.40#ibcon#about to write, iclass 10, count 0 2006.285.16:31:16.40#ibcon#wrote, iclass 10, count 0 2006.285.16:31:16.40#ibcon#about to read 3, iclass 10, count 0 2006.285.16:31:16.42#ibcon#read 3, iclass 10, count 0 2006.285.16:31:16.42#ibcon#about to read 4, iclass 10, count 0 2006.285.16:31:16.42#ibcon#read 4, iclass 10, count 0 2006.285.16:31:16.42#ibcon#about to read 5, iclass 10, count 0 2006.285.16:31:16.42#ibcon#read 5, iclass 10, count 0 2006.285.16:31:16.42#ibcon#about to read 6, iclass 10, count 0 2006.285.16:31:16.42#ibcon#read 6, iclass 10, count 0 2006.285.16:31:16.42#ibcon#end of sib2, iclass 10, count 0 2006.285.16:31:16.42#ibcon#*mode == 0, iclass 10, count 0 2006.285.16:31:16.42#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.16:31:16.42#ibcon#[25=USB\r\n] 2006.285.16:31:16.42#ibcon#*before write, iclass 10, count 0 2006.285.16:31:16.42#ibcon#enter sib2, iclass 10, count 0 2006.285.16:31:16.42#ibcon#flushed, iclass 10, count 0 2006.285.16:31:16.42#ibcon#about to write, iclass 10, count 0 2006.285.16:31:16.42#ibcon#wrote, iclass 10, count 0 2006.285.16:31:16.42#ibcon#about to read 3, iclass 10, count 0 2006.285.16:31:16.45#ibcon#read 3, iclass 10, count 0 2006.285.16:31:16.45#ibcon#about to read 4, iclass 10, count 0 2006.285.16:31:16.45#ibcon#read 4, iclass 10, count 0 2006.285.16:31:16.45#ibcon#about to read 5, iclass 10, count 0 2006.285.16:31:16.45#ibcon#read 5, iclass 10, count 0 2006.285.16:31:16.45#ibcon#about to read 6, iclass 10, count 0 2006.285.16:31:16.45#ibcon#read 6, iclass 10, count 0 2006.285.16:31:16.45#ibcon#end of sib2, iclass 10, count 0 2006.285.16:31:16.45#ibcon#*after write, iclass 10, count 0 2006.285.16:31:16.45#ibcon#*before return 0, iclass 10, count 0 2006.285.16:31:16.45#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.16:31:16.45#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.16:31:16.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.16:31:16.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.16:31:16.45$vck44/valo=8,884.99 2006.285.16:31:16.45#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.16:31:16.45#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.16:31:16.45#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:16.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:31:16.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:31:16.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:31:16.45#ibcon#enter wrdev, iclass 12, count 0 2006.285.16:31:16.45#ibcon#first serial, iclass 12, count 0 2006.285.16:31:16.45#ibcon#enter sib2, iclass 12, count 0 2006.285.16:31:16.45#ibcon#flushed, iclass 12, count 0 2006.285.16:31:16.45#ibcon#about to write, iclass 12, count 0 2006.285.16:31:16.45#ibcon#wrote, iclass 12, count 0 2006.285.16:31:16.45#ibcon#about to read 3, iclass 12, count 0 2006.285.16:31:16.47#ibcon#read 3, iclass 12, count 0 2006.285.16:31:16.47#ibcon#about to read 4, iclass 12, count 0 2006.285.16:31:16.47#ibcon#read 4, iclass 12, count 0 2006.285.16:31:16.47#ibcon#about to read 5, iclass 12, count 0 2006.285.16:31:16.47#ibcon#read 5, iclass 12, count 0 2006.285.16:31:16.47#ibcon#about to read 6, iclass 12, count 0 2006.285.16:31:16.47#ibcon#read 6, iclass 12, count 0 2006.285.16:31:16.47#ibcon#end of sib2, iclass 12, count 0 2006.285.16:31:16.47#ibcon#*mode == 0, iclass 12, count 0 2006.285.16:31:16.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.16:31:16.47#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.16:31:16.47#ibcon#*before write, iclass 12, count 0 2006.285.16:31:16.47#ibcon#enter sib2, iclass 12, count 0 2006.285.16:31:16.47#ibcon#flushed, iclass 12, count 0 2006.285.16:31:16.47#ibcon#about to write, iclass 12, count 0 2006.285.16:31:16.47#ibcon#wrote, iclass 12, count 0 2006.285.16:31:16.47#ibcon#about to read 3, iclass 12, count 0 2006.285.16:31:16.51#ibcon#read 3, iclass 12, count 0 2006.285.16:31:16.51#ibcon#about to read 4, iclass 12, count 0 2006.285.16:31:16.51#ibcon#read 4, iclass 12, count 0 2006.285.16:31:16.51#ibcon#about to read 5, iclass 12, count 0 2006.285.16:31:16.51#ibcon#read 5, iclass 12, count 0 2006.285.16:31:16.51#ibcon#about to read 6, iclass 12, count 0 2006.285.16:31:16.51#ibcon#read 6, iclass 12, count 0 2006.285.16:31:16.51#ibcon#end of sib2, iclass 12, count 0 2006.285.16:31:16.51#ibcon#*after write, iclass 12, count 0 2006.285.16:31:16.51#ibcon#*before return 0, iclass 12, count 0 2006.285.16:31:16.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:31:16.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:31:16.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.16:31:16.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.16:31:16.51$vck44/va=8,3 2006.285.16:31:16.51#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.16:31:16.51#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.16:31:16.51#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:16.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:31:16.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:31:16.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:31:16.57#ibcon#enter wrdev, iclass 14, count 2 2006.285.16:31:16.57#ibcon#first serial, iclass 14, count 2 2006.285.16:31:16.57#ibcon#enter sib2, iclass 14, count 2 2006.285.16:31:16.57#ibcon#flushed, iclass 14, count 2 2006.285.16:31:16.57#ibcon#about to write, iclass 14, count 2 2006.285.16:31:16.57#ibcon#wrote, iclass 14, count 2 2006.285.16:31:16.57#ibcon#about to read 3, iclass 14, count 2 2006.285.16:31:16.59#ibcon#read 3, iclass 14, count 2 2006.285.16:31:16.59#ibcon#about to read 4, iclass 14, count 2 2006.285.16:31:16.59#ibcon#read 4, iclass 14, count 2 2006.285.16:31:16.59#ibcon#about to read 5, iclass 14, count 2 2006.285.16:31:16.59#ibcon#read 5, iclass 14, count 2 2006.285.16:31:16.59#ibcon#about to read 6, iclass 14, count 2 2006.285.16:31:16.59#ibcon#read 6, iclass 14, count 2 2006.285.16:31:16.59#ibcon#end of sib2, iclass 14, count 2 2006.285.16:31:16.59#ibcon#*mode == 0, iclass 14, count 2 2006.285.16:31:16.59#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.16:31:16.59#ibcon#[25=AT08-03\r\n] 2006.285.16:31:16.59#ibcon#*before write, iclass 14, count 2 2006.285.16:31:16.59#ibcon#enter sib2, iclass 14, count 2 2006.285.16:31:16.59#ibcon#flushed, iclass 14, count 2 2006.285.16:31:16.59#ibcon#about to write, iclass 14, count 2 2006.285.16:31:16.59#ibcon#wrote, iclass 14, count 2 2006.285.16:31:16.59#ibcon#about to read 3, iclass 14, count 2 2006.285.16:31:16.62#ibcon#read 3, iclass 14, count 2 2006.285.16:31:16.62#ibcon#about to read 4, iclass 14, count 2 2006.285.16:31:16.62#ibcon#read 4, iclass 14, count 2 2006.285.16:31:16.62#ibcon#about to read 5, iclass 14, count 2 2006.285.16:31:16.62#ibcon#read 5, iclass 14, count 2 2006.285.16:31:16.62#ibcon#about to read 6, iclass 14, count 2 2006.285.16:31:16.62#ibcon#read 6, iclass 14, count 2 2006.285.16:31:16.62#ibcon#end of sib2, iclass 14, count 2 2006.285.16:31:16.62#ibcon#*after write, iclass 14, count 2 2006.285.16:31:16.62#ibcon#*before return 0, iclass 14, count 2 2006.285.16:31:16.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:31:16.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:31:16.62#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.16:31:16.62#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:16.62#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:31:16.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:31:16.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:31:16.74#ibcon#enter wrdev, iclass 14, count 0 2006.285.16:31:16.74#ibcon#first serial, iclass 14, count 0 2006.285.16:31:16.74#ibcon#enter sib2, iclass 14, count 0 2006.285.16:31:16.74#ibcon#flushed, iclass 14, count 0 2006.285.16:31:16.74#ibcon#about to write, iclass 14, count 0 2006.285.16:31:16.74#ibcon#wrote, iclass 14, count 0 2006.285.16:31:16.74#ibcon#about to read 3, iclass 14, count 0 2006.285.16:31:16.76#ibcon#read 3, iclass 14, count 0 2006.285.16:31:16.76#ibcon#about to read 4, iclass 14, count 0 2006.285.16:31:16.76#ibcon#read 4, iclass 14, count 0 2006.285.16:31:16.76#ibcon#about to read 5, iclass 14, count 0 2006.285.16:31:16.76#ibcon#read 5, iclass 14, count 0 2006.285.16:31:16.76#ibcon#about to read 6, iclass 14, count 0 2006.285.16:31:16.76#ibcon#read 6, iclass 14, count 0 2006.285.16:31:16.76#ibcon#end of sib2, iclass 14, count 0 2006.285.16:31:16.76#ibcon#*mode == 0, iclass 14, count 0 2006.285.16:31:16.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.16:31:16.76#ibcon#[25=USB\r\n] 2006.285.16:31:16.76#ibcon#*before write, iclass 14, count 0 2006.285.16:31:16.76#ibcon#enter sib2, iclass 14, count 0 2006.285.16:31:16.76#ibcon#flushed, iclass 14, count 0 2006.285.16:31:16.76#ibcon#about to write, iclass 14, count 0 2006.285.16:31:16.76#ibcon#wrote, iclass 14, count 0 2006.285.16:31:16.76#ibcon#about to read 3, iclass 14, count 0 2006.285.16:31:16.79#ibcon#read 3, iclass 14, count 0 2006.285.16:31:16.79#ibcon#about to read 4, iclass 14, count 0 2006.285.16:31:16.79#ibcon#read 4, iclass 14, count 0 2006.285.16:31:16.79#ibcon#about to read 5, iclass 14, count 0 2006.285.16:31:16.79#ibcon#read 5, iclass 14, count 0 2006.285.16:31:16.79#ibcon#about to read 6, iclass 14, count 0 2006.285.16:31:16.79#ibcon#read 6, iclass 14, count 0 2006.285.16:31:16.79#ibcon#end of sib2, iclass 14, count 0 2006.285.16:31:16.79#ibcon#*after write, iclass 14, count 0 2006.285.16:31:16.79#ibcon#*before return 0, iclass 14, count 0 2006.285.16:31:16.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:31:16.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:31:16.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.16:31:16.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.16:31:16.79$vck44/vblo=1,629.99 2006.285.16:31:16.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.16:31:16.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.16:31:16.79#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:16.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:31:16.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:31:16.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:31:16.79#ibcon#enter wrdev, iclass 16, count 0 2006.285.16:31:16.79#ibcon#first serial, iclass 16, count 0 2006.285.16:31:16.79#ibcon#enter sib2, iclass 16, count 0 2006.285.16:31:16.79#ibcon#flushed, iclass 16, count 0 2006.285.16:31:16.79#ibcon#about to write, iclass 16, count 0 2006.285.16:31:16.79#ibcon#wrote, iclass 16, count 0 2006.285.16:31:16.79#ibcon#about to read 3, iclass 16, count 0 2006.285.16:31:16.81#ibcon#read 3, iclass 16, count 0 2006.285.16:31:16.81#ibcon#about to read 4, iclass 16, count 0 2006.285.16:31:16.81#ibcon#read 4, iclass 16, count 0 2006.285.16:31:16.81#ibcon#about to read 5, iclass 16, count 0 2006.285.16:31:16.81#ibcon#read 5, iclass 16, count 0 2006.285.16:31:16.81#ibcon#about to read 6, iclass 16, count 0 2006.285.16:31:16.81#ibcon#read 6, iclass 16, count 0 2006.285.16:31:16.81#ibcon#end of sib2, iclass 16, count 0 2006.285.16:31:16.81#ibcon#*mode == 0, iclass 16, count 0 2006.285.16:31:16.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.16:31:16.81#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.16:31:16.81#ibcon#*before write, iclass 16, count 0 2006.285.16:31:16.81#ibcon#enter sib2, iclass 16, count 0 2006.285.16:31:16.81#ibcon#flushed, iclass 16, count 0 2006.285.16:31:16.81#ibcon#about to write, iclass 16, count 0 2006.285.16:31:16.81#ibcon#wrote, iclass 16, count 0 2006.285.16:31:16.81#ibcon#about to read 3, iclass 16, count 0 2006.285.16:31:16.85#ibcon#read 3, iclass 16, count 0 2006.285.16:31:16.85#ibcon#about to read 4, iclass 16, count 0 2006.285.16:31:16.85#ibcon#read 4, iclass 16, count 0 2006.285.16:31:16.85#ibcon#about to read 5, iclass 16, count 0 2006.285.16:31:16.85#ibcon#read 5, iclass 16, count 0 2006.285.16:31:16.85#ibcon#about to read 6, iclass 16, count 0 2006.285.16:31:16.85#ibcon#read 6, iclass 16, count 0 2006.285.16:31:16.85#ibcon#end of sib2, iclass 16, count 0 2006.285.16:31:16.85#ibcon#*after write, iclass 16, count 0 2006.285.16:31:16.85#ibcon#*before return 0, iclass 16, count 0 2006.285.16:31:16.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:31:16.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:31:16.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.16:31:16.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.16:31:16.85$vck44/vb=1,4 2006.285.16:31:16.85#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.16:31:16.85#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.16:31:16.85#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:16.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:31:16.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:31:16.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:31:16.85#ibcon#enter wrdev, iclass 18, count 2 2006.285.16:31:16.85#ibcon#first serial, iclass 18, count 2 2006.285.16:31:16.85#ibcon#enter sib2, iclass 18, count 2 2006.285.16:31:16.85#ibcon#flushed, iclass 18, count 2 2006.285.16:31:16.85#ibcon#about to write, iclass 18, count 2 2006.285.16:31:16.85#ibcon#wrote, iclass 18, count 2 2006.285.16:31:16.85#ibcon#about to read 3, iclass 18, count 2 2006.285.16:31:16.87#ibcon#read 3, iclass 18, count 2 2006.285.16:31:16.87#ibcon#about to read 4, iclass 18, count 2 2006.285.16:31:16.87#ibcon#read 4, iclass 18, count 2 2006.285.16:31:17.41#ibcon#about to read 5, iclass 18, count 2 2006.285.16:31:17.41#ibcon#read 5, iclass 18, count 2 2006.285.16:31:17.41#ibcon#about to read 6, iclass 18, count 2 2006.285.16:31:17.41#ibcon#read 6, iclass 18, count 2 2006.285.16:31:17.41#ibcon#end of sib2, iclass 18, count 2 2006.285.16:31:17.41#ibcon#*mode == 0, iclass 18, count 2 2006.285.16:31:17.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.16:31:17.41#ibcon#[27=AT01-04\r\n] 2006.285.16:31:17.41#ibcon#*before write, iclass 18, count 2 2006.285.16:31:17.41#ibcon#enter sib2, iclass 18, count 2 2006.285.16:31:17.41#ibcon#flushed, iclass 18, count 2 2006.285.16:31:17.41#ibcon#about to write, iclass 18, count 2 2006.285.16:31:17.41#ibcon#wrote, iclass 18, count 2 2006.285.16:31:17.41#ibcon#about to read 3, iclass 18, count 2 2006.285.16:31:17.45#ibcon#read 3, iclass 18, count 2 2006.285.16:31:17.45#ibcon#about to read 4, iclass 18, count 2 2006.285.16:31:17.45#ibcon#read 4, iclass 18, count 2 2006.285.16:31:17.45#ibcon#about to read 5, iclass 18, count 2 2006.285.16:31:17.45#ibcon#read 5, iclass 18, count 2 2006.285.16:31:17.45#ibcon#about to read 6, iclass 18, count 2 2006.285.16:31:17.45#ibcon#read 6, iclass 18, count 2 2006.285.16:31:17.45#ibcon#end of sib2, iclass 18, count 2 2006.285.16:31:17.45#ibcon#*after write, iclass 18, count 2 2006.285.16:31:17.45#ibcon#*before return 0, iclass 18, count 2 2006.285.16:31:17.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:31:17.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:31:17.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.16:31:17.45#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:17.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:31:17.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:31:17.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:31:17.57#ibcon#enter wrdev, iclass 18, count 0 2006.285.16:31:17.57#ibcon#first serial, iclass 18, count 0 2006.285.16:31:17.57#ibcon#enter sib2, iclass 18, count 0 2006.285.16:31:17.57#ibcon#flushed, iclass 18, count 0 2006.285.16:31:17.57#ibcon#about to write, iclass 18, count 0 2006.285.16:31:17.57#ibcon#wrote, iclass 18, count 0 2006.285.16:31:17.57#ibcon#about to read 3, iclass 18, count 0 2006.285.16:31:17.59#ibcon#read 3, iclass 18, count 0 2006.285.16:31:17.59#ibcon#about to read 4, iclass 18, count 0 2006.285.16:31:17.59#ibcon#read 4, iclass 18, count 0 2006.285.16:31:17.59#ibcon#about to read 5, iclass 18, count 0 2006.285.16:31:17.59#ibcon#read 5, iclass 18, count 0 2006.285.16:31:17.59#ibcon#about to read 6, iclass 18, count 0 2006.285.16:31:17.59#ibcon#read 6, iclass 18, count 0 2006.285.16:31:17.59#ibcon#end of sib2, iclass 18, count 0 2006.285.16:31:17.59#ibcon#*mode == 0, iclass 18, count 0 2006.285.16:31:17.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.16:31:17.59#ibcon#[27=USB\r\n] 2006.285.16:31:17.59#ibcon#*before write, iclass 18, count 0 2006.285.16:31:17.59#ibcon#enter sib2, iclass 18, count 0 2006.285.16:31:17.59#ibcon#flushed, iclass 18, count 0 2006.285.16:31:17.59#ibcon#about to write, iclass 18, count 0 2006.285.16:31:17.59#ibcon#wrote, iclass 18, count 0 2006.285.16:31:17.59#ibcon#about to read 3, iclass 18, count 0 2006.285.16:31:17.62#ibcon#read 3, iclass 18, count 0 2006.285.16:31:17.62#ibcon#about to read 4, iclass 18, count 0 2006.285.16:31:17.62#ibcon#read 4, iclass 18, count 0 2006.285.16:31:17.62#ibcon#about to read 5, iclass 18, count 0 2006.285.16:31:17.62#ibcon#read 5, iclass 18, count 0 2006.285.16:31:17.62#ibcon#about to read 6, iclass 18, count 0 2006.285.16:31:17.62#ibcon#read 6, iclass 18, count 0 2006.285.16:31:17.62#ibcon#end of sib2, iclass 18, count 0 2006.285.16:31:17.62#ibcon#*after write, iclass 18, count 0 2006.285.16:31:17.62#ibcon#*before return 0, iclass 18, count 0 2006.285.16:31:17.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:31:17.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:31:17.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.16:31:17.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.16:31:17.62$vck44/vblo=2,634.99 2006.285.16:31:17.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.16:31:17.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.16:31:17.62#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:17.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:31:17.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:31:17.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:31:17.62#ibcon#enter wrdev, iclass 20, count 0 2006.285.16:31:17.62#ibcon#first serial, iclass 20, count 0 2006.285.16:31:17.62#ibcon#enter sib2, iclass 20, count 0 2006.285.16:31:17.62#ibcon#flushed, iclass 20, count 0 2006.285.16:31:17.62#ibcon#about to write, iclass 20, count 0 2006.285.16:31:17.62#ibcon#wrote, iclass 20, count 0 2006.285.16:31:17.62#ibcon#about to read 3, iclass 20, count 0 2006.285.16:31:17.64#ibcon#read 3, iclass 20, count 0 2006.285.16:31:17.64#ibcon#about to read 4, iclass 20, count 0 2006.285.16:31:17.64#ibcon#read 4, iclass 20, count 0 2006.285.16:31:17.64#ibcon#about to read 5, iclass 20, count 0 2006.285.16:31:17.64#ibcon#read 5, iclass 20, count 0 2006.285.16:31:17.64#ibcon#about to read 6, iclass 20, count 0 2006.285.16:31:17.64#ibcon#read 6, iclass 20, count 0 2006.285.16:31:17.64#ibcon#end of sib2, iclass 20, count 0 2006.285.16:31:17.64#ibcon#*mode == 0, iclass 20, count 0 2006.285.16:31:17.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.16:31:17.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.16:31:17.64#ibcon#*before write, iclass 20, count 0 2006.285.16:31:17.64#ibcon#enter sib2, iclass 20, count 0 2006.285.16:31:17.64#ibcon#flushed, iclass 20, count 0 2006.285.16:31:17.64#ibcon#about to write, iclass 20, count 0 2006.285.16:31:17.64#ibcon#wrote, iclass 20, count 0 2006.285.16:31:17.64#ibcon#about to read 3, iclass 20, count 0 2006.285.16:31:17.68#ibcon#read 3, iclass 20, count 0 2006.285.16:31:17.68#ibcon#about to read 4, iclass 20, count 0 2006.285.16:31:17.68#ibcon#read 4, iclass 20, count 0 2006.285.16:31:17.68#ibcon#about to read 5, iclass 20, count 0 2006.285.16:31:17.68#ibcon#read 5, iclass 20, count 0 2006.285.16:31:17.68#ibcon#about to read 6, iclass 20, count 0 2006.285.16:31:17.68#ibcon#read 6, iclass 20, count 0 2006.285.16:31:17.68#ibcon#end of sib2, iclass 20, count 0 2006.285.16:31:17.68#ibcon#*after write, iclass 20, count 0 2006.285.16:31:17.68#ibcon#*before return 0, iclass 20, count 0 2006.285.16:31:17.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:31:17.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:31:17.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.16:31:17.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.16:31:17.68$vck44/vb=2,5 2006.285.16:31:17.68#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.16:31:17.68#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.16:31:17.68#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:17.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:31:17.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:31:17.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:31:17.74#ibcon#enter wrdev, iclass 22, count 2 2006.285.16:31:17.74#ibcon#first serial, iclass 22, count 2 2006.285.16:31:17.74#ibcon#enter sib2, iclass 22, count 2 2006.285.16:31:17.74#ibcon#flushed, iclass 22, count 2 2006.285.16:31:17.74#ibcon#about to write, iclass 22, count 2 2006.285.16:31:17.74#ibcon#wrote, iclass 22, count 2 2006.285.16:31:17.74#ibcon#about to read 3, iclass 22, count 2 2006.285.16:31:17.76#ibcon#read 3, iclass 22, count 2 2006.285.16:31:17.76#ibcon#about to read 4, iclass 22, count 2 2006.285.16:31:17.76#ibcon#read 4, iclass 22, count 2 2006.285.16:31:17.76#ibcon#about to read 5, iclass 22, count 2 2006.285.16:31:17.76#ibcon#read 5, iclass 22, count 2 2006.285.16:31:17.76#ibcon#about to read 6, iclass 22, count 2 2006.285.16:31:17.76#ibcon#read 6, iclass 22, count 2 2006.285.16:31:17.76#ibcon#end of sib2, iclass 22, count 2 2006.285.16:31:17.76#ibcon#*mode == 0, iclass 22, count 2 2006.285.16:31:17.76#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.16:31:17.76#ibcon#[27=AT02-05\r\n] 2006.285.16:31:17.76#ibcon#*before write, iclass 22, count 2 2006.285.16:31:17.76#ibcon#enter sib2, iclass 22, count 2 2006.285.16:31:17.76#ibcon#flushed, iclass 22, count 2 2006.285.16:31:17.76#ibcon#about to write, iclass 22, count 2 2006.285.16:31:17.76#ibcon#wrote, iclass 22, count 2 2006.285.16:31:17.76#ibcon#about to read 3, iclass 22, count 2 2006.285.16:31:17.79#ibcon#read 3, iclass 22, count 2 2006.285.16:31:17.79#ibcon#about to read 4, iclass 22, count 2 2006.285.16:31:17.79#ibcon#read 4, iclass 22, count 2 2006.285.16:31:17.79#ibcon#about to read 5, iclass 22, count 2 2006.285.16:31:17.79#ibcon#read 5, iclass 22, count 2 2006.285.16:31:17.79#ibcon#about to read 6, iclass 22, count 2 2006.285.16:31:17.79#ibcon#read 6, iclass 22, count 2 2006.285.16:31:17.79#ibcon#end of sib2, iclass 22, count 2 2006.285.16:31:17.79#ibcon#*after write, iclass 22, count 2 2006.285.16:31:17.79#ibcon#*before return 0, iclass 22, count 2 2006.285.16:31:17.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:31:17.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:31:17.79#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.16:31:17.79#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:17.79#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:31:17.91#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:31:17.91#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:31:17.91#ibcon#enter wrdev, iclass 22, count 0 2006.285.16:31:17.91#ibcon#first serial, iclass 22, count 0 2006.285.16:31:17.91#ibcon#enter sib2, iclass 22, count 0 2006.285.16:31:17.91#ibcon#flushed, iclass 22, count 0 2006.285.16:31:17.91#ibcon#about to write, iclass 22, count 0 2006.285.16:31:17.91#ibcon#wrote, iclass 22, count 0 2006.285.16:31:17.91#ibcon#about to read 3, iclass 22, count 0 2006.285.16:31:17.93#ibcon#read 3, iclass 22, count 0 2006.285.16:31:17.93#ibcon#about to read 4, iclass 22, count 0 2006.285.16:31:17.93#ibcon#read 4, iclass 22, count 0 2006.285.16:31:17.93#ibcon#about to read 5, iclass 22, count 0 2006.285.16:31:17.93#ibcon#read 5, iclass 22, count 0 2006.285.16:31:17.93#ibcon#about to read 6, iclass 22, count 0 2006.285.16:31:17.93#ibcon#read 6, iclass 22, count 0 2006.285.16:31:17.93#ibcon#end of sib2, iclass 22, count 0 2006.285.16:31:17.93#ibcon#*mode == 0, iclass 22, count 0 2006.285.16:31:17.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.16:31:17.93#ibcon#[27=USB\r\n] 2006.285.16:31:17.93#ibcon#*before write, iclass 22, count 0 2006.285.16:31:17.93#ibcon#enter sib2, iclass 22, count 0 2006.285.16:31:17.93#ibcon#flushed, iclass 22, count 0 2006.285.16:31:17.93#ibcon#about to write, iclass 22, count 0 2006.285.16:31:17.93#ibcon#wrote, iclass 22, count 0 2006.285.16:31:17.93#ibcon#about to read 3, iclass 22, count 0 2006.285.16:31:17.96#ibcon#read 3, iclass 22, count 0 2006.285.16:31:17.96#ibcon#about to read 4, iclass 22, count 0 2006.285.16:31:17.96#ibcon#read 4, iclass 22, count 0 2006.285.16:31:17.96#ibcon#about to read 5, iclass 22, count 0 2006.285.16:31:17.96#ibcon#read 5, iclass 22, count 0 2006.285.16:31:17.96#ibcon#about to read 6, iclass 22, count 0 2006.285.16:31:17.96#ibcon#read 6, iclass 22, count 0 2006.285.16:31:17.96#ibcon#end of sib2, iclass 22, count 0 2006.285.16:31:17.96#ibcon#*after write, iclass 22, count 0 2006.285.16:31:17.96#ibcon#*before return 0, iclass 22, count 0 2006.285.16:31:17.96#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:31:17.96#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:31:17.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.16:31:17.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.16:31:17.96$vck44/vblo=3,649.99 2006.285.16:31:17.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.16:31:17.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.16:31:17.96#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:17.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:31:17.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:31:17.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:31:17.96#ibcon#enter wrdev, iclass 24, count 0 2006.285.16:31:17.96#ibcon#first serial, iclass 24, count 0 2006.285.16:31:17.96#ibcon#enter sib2, iclass 24, count 0 2006.285.16:31:17.96#ibcon#flushed, iclass 24, count 0 2006.285.16:31:17.96#ibcon#about to write, iclass 24, count 0 2006.285.16:31:17.96#ibcon#wrote, iclass 24, count 0 2006.285.16:31:17.96#ibcon#about to read 3, iclass 24, count 0 2006.285.16:31:17.98#ibcon#read 3, iclass 24, count 0 2006.285.16:31:17.98#ibcon#about to read 4, iclass 24, count 0 2006.285.16:31:17.98#ibcon#read 4, iclass 24, count 0 2006.285.16:31:17.98#ibcon#about to read 5, iclass 24, count 0 2006.285.16:31:17.98#ibcon#read 5, iclass 24, count 0 2006.285.16:31:17.98#ibcon#about to read 6, iclass 24, count 0 2006.285.16:31:17.98#ibcon#read 6, iclass 24, count 0 2006.285.16:31:17.98#ibcon#end of sib2, iclass 24, count 0 2006.285.16:31:17.98#ibcon#*mode == 0, iclass 24, count 0 2006.285.16:31:17.98#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.16:31:17.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.16:31:17.98#ibcon#*before write, iclass 24, count 0 2006.285.16:31:17.98#ibcon#enter sib2, iclass 24, count 0 2006.285.16:31:17.98#ibcon#flushed, iclass 24, count 0 2006.285.16:31:17.98#ibcon#about to write, iclass 24, count 0 2006.285.16:31:17.98#ibcon#wrote, iclass 24, count 0 2006.285.16:31:17.98#ibcon#about to read 3, iclass 24, count 0 2006.285.16:31:18.02#ibcon#read 3, iclass 24, count 0 2006.285.16:31:18.02#ibcon#about to read 4, iclass 24, count 0 2006.285.16:31:18.02#ibcon#read 4, iclass 24, count 0 2006.285.16:31:18.02#ibcon#about to read 5, iclass 24, count 0 2006.285.16:31:18.02#ibcon#read 5, iclass 24, count 0 2006.285.16:31:18.02#ibcon#about to read 6, iclass 24, count 0 2006.285.16:31:18.02#ibcon#read 6, iclass 24, count 0 2006.285.16:31:18.02#ibcon#end of sib2, iclass 24, count 0 2006.285.16:31:18.02#ibcon#*after write, iclass 24, count 0 2006.285.16:31:18.02#ibcon#*before return 0, iclass 24, count 0 2006.285.16:31:18.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:31:18.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:31:18.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.16:31:18.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.16:31:18.02$vck44/vb=3,4 2006.285.16:31:18.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.16:31:18.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.16:31:18.02#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:18.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:31:18.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:31:18.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:31:18.08#ibcon#enter wrdev, iclass 26, count 2 2006.285.16:31:18.08#ibcon#first serial, iclass 26, count 2 2006.285.16:31:18.08#ibcon#enter sib2, iclass 26, count 2 2006.285.16:31:18.08#ibcon#flushed, iclass 26, count 2 2006.285.16:31:18.08#ibcon#about to write, iclass 26, count 2 2006.285.16:31:18.08#ibcon#wrote, iclass 26, count 2 2006.285.16:31:18.08#ibcon#about to read 3, iclass 26, count 2 2006.285.16:31:18.10#ibcon#read 3, iclass 26, count 2 2006.285.16:31:18.10#ibcon#about to read 4, iclass 26, count 2 2006.285.16:31:18.10#ibcon#read 4, iclass 26, count 2 2006.285.16:31:18.10#ibcon#about to read 5, iclass 26, count 2 2006.285.16:31:18.10#ibcon#read 5, iclass 26, count 2 2006.285.16:31:18.10#ibcon#about to read 6, iclass 26, count 2 2006.285.16:31:18.10#ibcon#read 6, iclass 26, count 2 2006.285.16:31:18.10#ibcon#end of sib2, iclass 26, count 2 2006.285.16:31:18.10#ibcon#*mode == 0, iclass 26, count 2 2006.285.16:31:18.10#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.16:31:18.10#ibcon#[27=AT03-04\r\n] 2006.285.16:31:18.10#ibcon#*before write, iclass 26, count 2 2006.285.16:31:18.10#ibcon#enter sib2, iclass 26, count 2 2006.285.16:31:18.10#ibcon#flushed, iclass 26, count 2 2006.285.16:31:18.10#ibcon#about to write, iclass 26, count 2 2006.285.16:31:18.10#ibcon#wrote, iclass 26, count 2 2006.285.16:31:18.10#ibcon#about to read 3, iclass 26, count 2 2006.285.16:31:18.13#ibcon#read 3, iclass 26, count 2 2006.285.16:31:18.13#ibcon#about to read 4, iclass 26, count 2 2006.285.16:31:18.13#ibcon#read 4, iclass 26, count 2 2006.285.16:31:18.13#ibcon#about to read 5, iclass 26, count 2 2006.285.16:31:18.13#ibcon#read 5, iclass 26, count 2 2006.285.16:31:18.13#ibcon#about to read 6, iclass 26, count 2 2006.285.16:31:18.13#ibcon#read 6, iclass 26, count 2 2006.285.16:31:18.13#ibcon#end of sib2, iclass 26, count 2 2006.285.16:31:18.13#ibcon#*after write, iclass 26, count 2 2006.285.16:31:18.13#ibcon#*before return 0, iclass 26, count 2 2006.285.16:31:18.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:31:18.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:31:18.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.16:31:18.13#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:18.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:31:18.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:31:18.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:31:18.25#ibcon#enter wrdev, iclass 26, count 0 2006.285.16:31:18.25#ibcon#first serial, iclass 26, count 0 2006.285.16:31:18.25#ibcon#enter sib2, iclass 26, count 0 2006.285.16:31:18.25#ibcon#flushed, iclass 26, count 0 2006.285.16:31:18.25#ibcon#about to write, iclass 26, count 0 2006.285.16:31:18.25#ibcon#wrote, iclass 26, count 0 2006.285.16:31:18.25#ibcon#about to read 3, iclass 26, count 0 2006.285.16:31:18.27#ibcon#read 3, iclass 26, count 0 2006.285.16:31:18.27#ibcon#about to read 4, iclass 26, count 0 2006.285.16:31:18.27#ibcon#read 4, iclass 26, count 0 2006.285.16:31:18.27#ibcon#about to read 5, iclass 26, count 0 2006.285.16:31:18.27#ibcon#read 5, iclass 26, count 0 2006.285.16:31:18.27#ibcon#about to read 6, iclass 26, count 0 2006.285.16:31:18.27#ibcon#read 6, iclass 26, count 0 2006.285.16:31:18.27#ibcon#end of sib2, iclass 26, count 0 2006.285.16:31:18.27#ibcon#*mode == 0, iclass 26, count 0 2006.285.16:31:18.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.16:31:18.27#ibcon#[27=USB\r\n] 2006.285.16:31:18.27#ibcon#*before write, iclass 26, count 0 2006.285.16:31:18.27#ibcon#enter sib2, iclass 26, count 0 2006.285.16:31:18.27#ibcon#flushed, iclass 26, count 0 2006.285.16:31:18.27#ibcon#about to write, iclass 26, count 0 2006.285.16:31:18.27#ibcon#wrote, iclass 26, count 0 2006.285.16:31:18.27#ibcon#about to read 3, iclass 26, count 0 2006.285.16:31:18.30#ibcon#read 3, iclass 26, count 0 2006.285.16:31:18.30#ibcon#about to read 4, iclass 26, count 0 2006.285.16:31:18.30#ibcon#read 4, iclass 26, count 0 2006.285.16:31:18.30#ibcon#about to read 5, iclass 26, count 0 2006.285.16:31:18.30#ibcon#read 5, iclass 26, count 0 2006.285.16:31:18.30#ibcon#about to read 6, iclass 26, count 0 2006.285.16:31:18.30#ibcon#read 6, iclass 26, count 0 2006.285.16:31:18.30#ibcon#end of sib2, iclass 26, count 0 2006.285.16:31:18.30#ibcon#*after write, iclass 26, count 0 2006.285.16:31:18.30#ibcon#*before return 0, iclass 26, count 0 2006.285.16:31:18.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:31:18.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:31:18.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.16:31:18.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.16:31:18.30$vck44/vblo=4,679.99 2006.285.16:31:18.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.16:31:18.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.16:31:18.30#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:18.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:31:18.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:31:18.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:31:18.30#ibcon#enter wrdev, iclass 28, count 0 2006.285.16:31:18.30#ibcon#first serial, iclass 28, count 0 2006.285.16:31:18.30#ibcon#enter sib2, iclass 28, count 0 2006.285.16:31:18.30#ibcon#flushed, iclass 28, count 0 2006.285.16:31:18.30#ibcon#about to write, iclass 28, count 0 2006.285.16:31:18.30#ibcon#wrote, iclass 28, count 0 2006.285.16:31:18.30#ibcon#about to read 3, iclass 28, count 0 2006.285.16:31:18.32#ibcon#read 3, iclass 28, count 0 2006.285.16:31:18.32#ibcon#about to read 4, iclass 28, count 0 2006.285.16:31:18.32#ibcon#read 4, iclass 28, count 0 2006.285.16:31:18.32#ibcon#about to read 5, iclass 28, count 0 2006.285.16:31:18.32#ibcon#read 5, iclass 28, count 0 2006.285.16:31:18.32#ibcon#about to read 6, iclass 28, count 0 2006.285.16:31:18.32#ibcon#read 6, iclass 28, count 0 2006.285.16:31:18.32#ibcon#end of sib2, iclass 28, count 0 2006.285.16:31:18.32#ibcon#*mode == 0, iclass 28, count 0 2006.285.16:31:18.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.16:31:18.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.16:31:18.32#ibcon#*before write, iclass 28, count 0 2006.285.16:31:18.32#ibcon#enter sib2, iclass 28, count 0 2006.285.16:31:18.32#ibcon#flushed, iclass 28, count 0 2006.285.16:31:18.32#ibcon#about to write, iclass 28, count 0 2006.285.16:31:18.32#ibcon#wrote, iclass 28, count 0 2006.285.16:31:18.32#ibcon#about to read 3, iclass 28, count 0 2006.285.16:31:18.36#ibcon#read 3, iclass 28, count 0 2006.285.16:31:18.36#ibcon#about to read 4, iclass 28, count 0 2006.285.16:31:18.36#ibcon#read 4, iclass 28, count 0 2006.285.16:31:18.36#ibcon#about to read 5, iclass 28, count 0 2006.285.16:31:18.36#ibcon#read 5, iclass 28, count 0 2006.285.16:31:18.36#ibcon#about to read 6, iclass 28, count 0 2006.285.16:31:18.36#ibcon#read 6, iclass 28, count 0 2006.285.16:31:18.36#ibcon#end of sib2, iclass 28, count 0 2006.285.16:31:18.36#ibcon#*after write, iclass 28, count 0 2006.285.16:31:18.36#ibcon#*before return 0, iclass 28, count 0 2006.285.16:31:18.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:31:18.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:31:18.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.16:31:18.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.16:31:18.36$vck44/vb=4,5 2006.285.16:31:18.36#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.16:31:18.36#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.16:31:18.36#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:18.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:31:18.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:31:18.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:31:18.42#ibcon#enter wrdev, iclass 30, count 2 2006.285.16:31:18.42#ibcon#first serial, iclass 30, count 2 2006.285.16:31:18.42#ibcon#enter sib2, iclass 30, count 2 2006.285.16:31:18.42#ibcon#flushed, iclass 30, count 2 2006.285.16:31:18.42#ibcon#about to write, iclass 30, count 2 2006.285.16:31:18.42#ibcon#wrote, iclass 30, count 2 2006.285.16:31:18.42#ibcon#about to read 3, iclass 30, count 2 2006.285.16:31:18.44#ibcon#read 3, iclass 30, count 2 2006.285.16:31:18.44#ibcon#about to read 4, iclass 30, count 2 2006.285.16:31:18.44#ibcon#read 4, iclass 30, count 2 2006.285.16:31:18.44#ibcon#about to read 5, iclass 30, count 2 2006.285.16:31:18.44#ibcon#read 5, iclass 30, count 2 2006.285.16:31:18.44#ibcon#about to read 6, iclass 30, count 2 2006.285.16:31:18.44#ibcon#read 6, iclass 30, count 2 2006.285.16:31:18.44#ibcon#end of sib2, iclass 30, count 2 2006.285.16:31:18.44#ibcon#*mode == 0, iclass 30, count 2 2006.285.16:31:18.44#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.16:31:18.44#ibcon#[27=AT04-05\r\n] 2006.285.16:31:18.44#ibcon#*before write, iclass 30, count 2 2006.285.16:31:18.44#ibcon#enter sib2, iclass 30, count 2 2006.285.16:31:18.44#ibcon#flushed, iclass 30, count 2 2006.285.16:31:18.44#ibcon#about to write, iclass 30, count 2 2006.285.16:31:18.44#ibcon#wrote, iclass 30, count 2 2006.285.16:31:18.44#ibcon#about to read 3, iclass 30, count 2 2006.285.16:31:18.47#ibcon#read 3, iclass 30, count 2 2006.285.16:31:18.47#ibcon#about to read 4, iclass 30, count 2 2006.285.16:31:18.47#ibcon#read 4, iclass 30, count 2 2006.285.16:31:18.47#ibcon#about to read 5, iclass 30, count 2 2006.285.16:31:18.47#ibcon#read 5, iclass 30, count 2 2006.285.16:31:18.47#ibcon#about to read 6, iclass 30, count 2 2006.285.16:31:18.47#ibcon#read 6, iclass 30, count 2 2006.285.16:31:18.47#ibcon#end of sib2, iclass 30, count 2 2006.285.16:31:18.47#ibcon#*after write, iclass 30, count 2 2006.285.16:31:18.47#ibcon#*before return 0, iclass 30, count 2 2006.285.16:31:18.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:31:18.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:31:18.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.16:31:18.47#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:18.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:31:18.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:31:18.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:31:18.59#ibcon#enter wrdev, iclass 30, count 0 2006.285.16:31:18.59#ibcon#first serial, iclass 30, count 0 2006.285.16:31:18.59#ibcon#enter sib2, iclass 30, count 0 2006.285.16:31:18.59#ibcon#flushed, iclass 30, count 0 2006.285.16:31:18.59#ibcon#about to write, iclass 30, count 0 2006.285.16:31:18.59#ibcon#wrote, iclass 30, count 0 2006.285.16:31:18.59#ibcon#about to read 3, iclass 30, count 0 2006.285.16:31:18.61#ibcon#read 3, iclass 30, count 0 2006.285.16:31:18.61#ibcon#about to read 4, iclass 30, count 0 2006.285.16:31:18.61#ibcon#read 4, iclass 30, count 0 2006.285.16:31:18.61#ibcon#about to read 5, iclass 30, count 0 2006.285.16:31:18.61#ibcon#read 5, iclass 30, count 0 2006.285.16:31:18.61#ibcon#about to read 6, iclass 30, count 0 2006.285.16:31:18.61#ibcon#read 6, iclass 30, count 0 2006.285.16:31:18.61#ibcon#end of sib2, iclass 30, count 0 2006.285.16:31:18.61#ibcon#*mode == 0, iclass 30, count 0 2006.285.16:31:18.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.16:31:18.61#ibcon#[27=USB\r\n] 2006.285.16:31:18.61#ibcon#*before write, iclass 30, count 0 2006.285.16:31:18.61#ibcon#enter sib2, iclass 30, count 0 2006.285.16:31:18.61#ibcon#flushed, iclass 30, count 0 2006.285.16:31:18.61#ibcon#about to write, iclass 30, count 0 2006.285.16:31:18.61#ibcon#wrote, iclass 30, count 0 2006.285.16:31:18.61#ibcon#about to read 3, iclass 30, count 0 2006.285.16:31:18.64#ibcon#read 3, iclass 30, count 0 2006.285.16:31:18.64#ibcon#about to read 4, iclass 30, count 0 2006.285.16:31:18.64#ibcon#read 4, iclass 30, count 0 2006.285.16:31:18.64#ibcon#about to read 5, iclass 30, count 0 2006.285.16:31:18.64#ibcon#read 5, iclass 30, count 0 2006.285.16:31:18.64#ibcon#about to read 6, iclass 30, count 0 2006.285.16:31:18.64#ibcon#read 6, iclass 30, count 0 2006.285.16:31:18.64#ibcon#end of sib2, iclass 30, count 0 2006.285.16:31:18.64#ibcon#*after write, iclass 30, count 0 2006.285.16:31:18.64#ibcon#*before return 0, iclass 30, count 0 2006.285.16:31:18.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:31:18.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:31:18.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.16:31:18.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.16:31:18.64$vck44/vblo=5,709.99 2006.285.16:31:18.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.16:31:18.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.16:31:18.64#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:18.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:31:18.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:31:18.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:31:18.64#ibcon#enter wrdev, iclass 32, count 0 2006.285.16:31:18.64#ibcon#first serial, iclass 32, count 0 2006.285.16:31:18.64#ibcon#enter sib2, iclass 32, count 0 2006.285.16:31:18.64#ibcon#flushed, iclass 32, count 0 2006.285.16:31:18.64#ibcon#about to write, iclass 32, count 0 2006.285.16:31:18.64#ibcon#wrote, iclass 32, count 0 2006.285.16:31:18.64#ibcon#about to read 3, iclass 32, count 0 2006.285.16:31:18.66#ibcon#read 3, iclass 32, count 0 2006.285.16:31:18.66#ibcon#about to read 4, iclass 32, count 0 2006.285.16:31:18.66#ibcon#read 4, iclass 32, count 0 2006.285.16:31:18.66#ibcon#about to read 5, iclass 32, count 0 2006.285.16:31:18.66#ibcon#read 5, iclass 32, count 0 2006.285.16:31:18.66#ibcon#about to read 6, iclass 32, count 0 2006.285.16:31:18.66#ibcon#read 6, iclass 32, count 0 2006.285.16:31:18.66#ibcon#end of sib2, iclass 32, count 0 2006.285.16:31:18.66#ibcon#*mode == 0, iclass 32, count 0 2006.285.16:31:18.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.16:31:18.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.16:31:18.66#ibcon#*before write, iclass 32, count 0 2006.285.16:31:18.66#ibcon#enter sib2, iclass 32, count 0 2006.285.16:31:18.66#ibcon#flushed, iclass 32, count 0 2006.285.16:31:18.66#ibcon#about to write, iclass 32, count 0 2006.285.16:31:18.66#ibcon#wrote, iclass 32, count 0 2006.285.16:31:18.66#ibcon#about to read 3, iclass 32, count 0 2006.285.16:31:18.70#ibcon#read 3, iclass 32, count 0 2006.285.16:31:18.70#ibcon#about to read 4, iclass 32, count 0 2006.285.16:31:18.70#ibcon#read 4, iclass 32, count 0 2006.285.16:31:18.70#ibcon#about to read 5, iclass 32, count 0 2006.285.16:31:18.70#ibcon#read 5, iclass 32, count 0 2006.285.16:31:18.70#ibcon#about to read 6, iclass 32, count 0 2006.285.16:31:18.70#ibcon#read 6, iclass 32, count 0 2006.285.16:31:18.70#ibcon#end of sib2, iclass 32, count 0 2006.285.16:31:18.70#ibcon#*after write, iclass 32, count 0 2006.285.16:31:18.70#ibcon#*before return 0, iclass 32, count 0 2006.285.16:31:18.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:31:18.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:31:18.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.16:31:18.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.16:31:18.70$vck44/vb=5,4 2006.285.16:31:18.70#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.16:31:18.70#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.16:31:18.70#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:18.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:31:18.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:31:18.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:31:18.76#ibcon#enter wrdev, iclass 34, count 2 2006.285.16:31:18.76#ibcon#first serial, iclass 34, count 2 2006.285.16:31:18.76#ibcon#enter sib2, iclass 34, count 2 2006.285.16:31:18.76#ibcon#flushed, iclass 34, count 2 2006.285.16:31:18.76#ibcon#about to write, iclass 34, count 2 2006.285.16:31:18.76#ibcon#wrote, iclass 34, count 2 2006.285.16:31:18.76#ibcon#about to read 3, iclass 34, count 2 2006.285.16:31:18.78#ibcon#read 3, iclass 34, count 2 2006.285.16:31:18.78#ibcon#about to read 4, iclass 34, count 2 2006.285.16:31:18.78#ibcon#read 4, iclass 34, count 2 2006.285.16:31:18.78#ibcon#about to read 5, iclass 34, count 2 2006.285.16:31:18.78#ibcon#read 5, iclass 34, count 2 2006.285.16:31:18.78#ibcon#about to read 6, iclass 34, count 2 2006.285.16:31:18.78#ibcon#read 6, iclass 34, count 2 2006.285.16:31:18.78#ibcon#end of sib2, iclass 34, count 2 2006.285.16:31:18.78#ibcon#*mode == 0, iclass 34, count 2 2006.285.16:31:18.78#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.16:31:18.78#ibcon#[27=AT05-04\r\n] 2006.285.16:31:18.78#ibcon#*before write, iclass 34, count 2 2006.285.16:31:18.78#ibcon#enter sib2, iclass 34, count 2 2006.285.16:31:18.78#ibcon#flushed, iclass 34, count 2 2006.285.16:31:18.78#ibcon#about to write, iclass 34, count 2 2006.285.16:31:18.78#ibcon#wrote, iclass 34, count 2 2006.285.16:31:18.78#ibcon#about to read 3, iclass 34, count 2 2006.285.16:31:18.81#ibcon#read 3, iclass 34, count 2 2006.285.16:31:18.81#ibcon#about to read 4, iclass 34, count 2 2006.285.16:31:18.81#ibcon#read 4, iclass 34, count 2 2006.285.16:31:18.81#ibcon#about to read 5, iclass 34, count 2 2006.285.16:31:18.81#ibcon#read 5, iclass 34, count 2 2006.285.16:31:18.81#ibcon#about to read 6, iclass 34, count 2 2006.285.16:31:18.81#ibcon#read 6, iclass 34, count 2 2006.285.16:31:18.81#ibcon#end of sib2, iclass 34, count 2 2006.285.16:31:18.81#ibcon#*after write, iclass 34, count 2 2006.285.16:31:18.81#ibcon#*before return 0, iclass 34, count 2 2006.285.16:31:18.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:31:18.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:31:18.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.16:31:18.81#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:18.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:31:18.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:31:18.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:31:18.93#ibcon#enter wrdev, iclass 34, count 0 2006.285.16:31:18.93#ibcon#first serial, iclass 34, count 0 2006.285.16:31:18.93#ibcon#enter sib2, iclass 34, count 0 2006.285.16:31:18.93#ibcon#flushed, iclass 34, count 0 2006.285.16:31:18.93#ibcon#about to write, iclass 34, count 0 2006.285.16:31:18.93#ibcon#wrote, iclass 34, count 0 2006.285.16:31:18.93#ibcon#about to read 3, iclass 34, count 0 2006.285.16:31:18.95#ibcon#read 3, iclass 34, count 0 2006.285.16:31:18.95#ibcon#about to read 4, iclass 34, count 0 2006.285.16:31:18.95#ibcon#read 4, iclass 34, count 0 2006.285.16:31:18.95#ibcon#about to read 5, iclass 34, count 0 2006.285.16:31:18.95#ibcon#read 5, iclass 34, count 0 2006.285.16:31:18.95#ibcon#about to read 6, iclass 34, count 0 2006.285.16:31:18.95#ibcon#read 6, iclass 34, count 0 2006.285.16:31:18.95#ibcon#end of sib2, iclass 34, count 0 2006.285.16:31:18.95#ibcon#*mode == 0, iclass 34, count 0 2006.285.16:31:18.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.16:31:18.95#ibcon#[27=USB\r\n] 2006.285.16:31:18.95#ibcon#*before write, iclass 34, count 0 2006.285.16:31:18.95#ibcon#enter sib2, iclass 34, count 0 2006.285.16:31:18.95#ibcon#flushed, iclass 34, count 0 2006.285.16:31:18.95#ibcon#about to write, iclass 34, count 0 2006.285.16:31:18.95#ibcon#wrote, iclass 34, count 0 2006.285.16:31:18.95#ibcon#about to read 3, iclass 34, count 0 2006.285.16:31:18.98#ibcon#read 3, iclass 34, count 0 2006.285.16:31:18.98#ibcon#about to read 4, iclass 34, count 0 2006.285.16:31:18.98#ibcon#read 4, iclass 34, count 0 2006.285.16:31:18.98#ibcon#about to read 5, iclass 34, count 0 2006.285.16:31:18.98#ibcon#read 5, iclass 34, count 0 2006.285.16:31:18.98#ibcon#about to read 6, iclass 34, count 0 2006.285.16:31:18.98#ibcon#read 6, iclass 34, count 0 2006.285.16:31:18.98#ibcon#end of sib2, iclass 34, count 0 2006.285.16:31:18.98#ibcon#*after write, iclass 34, count 0 2006.285.16:31:18.98#ibcon#*before return 0, iclass 34, count 0 2006.285.16:31:18.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:31:18.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:31:18.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.16:31:18.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.16:31:18.98$vck44/vblo=6,719.99 2006.285.16:31:18.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.16:31:18.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.16:31:18.98#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:18.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:31:18.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:31:18.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:31:18.98#ibcon#enter wrdev, iclass 36, count 0 2006.285.16:31:18.98#ibcon#first serial, iclass 36, count 0 2006.285.16:31:18.98#ibcon#enter sib2, iclass 36, count 0 2006.285.16:31:18.98#ibcon#flushed, iclass 36, count 0 2006.285.16:31:18.98#ibcon#about to write, iclass 36, count 0 2006.285.16:31:18.98#ibcon#wrote, iclass 36, count 0 2006.285.16:31:18.98#ibcon#about to read 3, iclass 36, count 0 2006.285.16:31:19.00#ibcon#read 3, iclass 36, count 0 2006.285.16:31:19.08#ibcon#about to read 4, iclass 36, count 0 2006.285.16:31:19.08#ibcon#read 4, iclass 36, count 0 2006.285.16:31:19.08#ibcon#about to read 5, iclass 36, count 0 2006.285.16:31:19.08#ibcon#read 5, iclass 36, count 0 2006.285.16:31:19.08#ibcon#about to read 6, iclass 36, count 0 2006.285.16:31:19.08#ibcon#read 6, iclass 36, count 0 2006.285.16:31:19.08#ibcon#end of sib2, iclass 36, count 0 2006.285.16:31:19.08#ibcon#*mode == 0, iclass 36, count 0 2006.285.16:31:19.08#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.16:31:19.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.16:31:19.08#ibcon#*before write, iclass 36, count 0 2006.285.16:31:19.08#ibcon#enter sib2, iclass 36, count 0 2006.285.16:31:19.08#ibcon#flushed, iclass 36, count 0 2006.285.16:31:19.08#ibcon#about to write, iclass 36, count 0 2006.285.16:31:19.08#ibcon#wrote, iclass 36, count 0 2006.285.16:31:19.08#ibcon#about to read 3, iclass 36, count 0 2006.285.16:31:19.13#ibcon#read 3, iclass 36, count 0 2006.285.16:31:19.13#ibcon#about to read 4, iclass 36, count 0 2006.285.16:31:19.13#ibcon#read 4, iclass 36, count 0 2006.285.16:31:19.13#ibcon#about to read 5, iclass 36, count 0 2006.285.16:31:19.13#ibcon#read 5, iclass 36, count 0 2006.285.16:31:19.13#ibcon#about to read 6, iclass 36, count 0 2006.285.16:31:19.13#ibcon#read 6, iclass 36, count 0 2006.285.16:31:19.13#ibcon#end of sib2, iclass 36, count 0 2006.285.16:31:19.13#ibcon#*after write, iclass 36, count 0 2006.285.16:31:19.13#ibcon#*before return 0, iclass 36, count 0 2006.285.16:31:19.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:31:19.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:31:19.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.16:31:19.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.16:31:19.13$vck44/vb=6,3 2006.285.16:31:19.13#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.16:31:19.13#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.16:31:19.13#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:19.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:31:19.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:31:19.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:31:19.13#ibcon#enter wrdev, iclass 38, count 2 2006.285.16:31:19.13#ibcon#first serial, iclass 38, count 2 2006.285.16:31:19.13#ibcon#enter sib2, iclass 38, count 2 2006.285.16:31:19.13#ibcon#flushed, iclass 38, count 2 2006.285.16:31:19.13#ibcon#about to write, iclass 38, count 2 2006.285.16:31:19.13#ibcon#wrote, iclass 38, count 2 2006.285.16:31:19.13#ibcon#about to read 3, iclass 38, count 2 2006.285.16:31:19.15#ibcon#read 3, iclass 38, count 2 2006.285.16:31:19.15#ibcon#about to read 4, iclass 38, count 2 2006.285.16:31:19.15#ibcon#read 4, iclass 38, count 2 2006.285.16:31:19.15#ibcon#about to read 5, iclass 38, count 2 2006.285.16:31:19.15#ibcon#read 5, iclass 38, count 2 2006.285.16:31:19.15#ibcon#about to read 6, iclass 38, count 2 2006.285.16:31:19.15#ibcon#read 6, iclass 38, count 2 2006.285.16:31:19.15#ibcon#end of sib2, iclass 38, count 2 2006.285.16:31:19.15#ibcon#*mode == 0, iclass 38, count 2 2006.285.16:31:19.15#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.16:31:19.15#ibcon#[27=AT06-03\r\n] 2006.285.16:31:19.15#ibcon#*before write, iclass 38, count 2 2006.285.16:31:19.15#ibcon#enter sib2, iclass 38, count 2 2006.285.16:31:19.15#ibcon#flushed, iclass 38, count 2 2006.285.16:31:19.15#ibcon#about to write, iclass 38, count 2 2006.285.16:31:19.15#ibcon#wrote, iclass 38, count 2 2006.285.16:31:19.15#ibcon#about to read 3, iclass 38, count 2 2006.285.16:31:19.18#ibcon#read 3, iclass 38, count 2 2006.285.16:31:19.18#ibcon#about to read 4, iclass 38, count 2 2006.285.16:31:19.18#ibcon#read 4, iclass 38, count 2 2006.285.16:31:19.18#ibcon#about to read 5, iclass 38, count 2 2006.285.16:31:19.18#ibcon#read 5, iclass 38, count 2 2006.285.16:31:19.18#ibcon#about to read 6, iclass 38, count 2 2006.285.16:31:19.18#ibcon#read 6, iclass 38, count 2 2006.285.16:31:19.18#ibcon#end of sib2, iclass 38, count 2 2006.285.16:31:19.18#ibcon#*after write, iclass 38, count 2 2006.285.16:31:19.18#ibcon#*before return 0, iclass 38, count 2 2006.285.16:31:19.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:31:19.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:31:19.18#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.16:31:19.18#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:19.18#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:31:19.30#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:31:19.30#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:31:19.30#ibcon#enter wrdev, iclass 38, count 0 2006.285.16:31:19.30#ibcon#first serial, iclass 38, count 0 2006.285.16:31:19.30#ibcon#enter sib2, iclass 38, count 0 2006.285.16:31:19.30#ibcon#flushed, iclass 38, count 0 2006.285.16:31:19.30#ibcon#about to write, iclass 38, count 0 2006.285.16:31:19.30#ibcon#wrote, iclass 38, count 0 2006.285.16:31:19.30#ibcon#about to read 3, iclass 38, count 0 2006.285.16:31:19.32#ibcon#read 3, iclass 38, count 0 2006.285.16:31:19.32#ibcon#about to read 4, iclass 38, count 0 2006.285.16:31:19.32#ibcon#read 4, iclass 38, count 0 2006.285.16:31:19.32#ibcon#about to read 5, iclass 38, count 0 2006.285.16:31:19.32#ibcon#read 5, iclass 38, count 0 2006.285.16:31:19.32#ibcon#about to read 6, iclass 38, count 0 2006.285.16:31:19.32#ibcon#read 6, iclass 38, count 0 2006.285.16:31:19.32#ibcon#end of sib2, iclass 38, count 0 2006.285.16:31:19.32#ibcon#*mode == 0, iclass 38, count 0 2006.285.16:31:19.32#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.16:31:19.32#ibcon#[27=USB\r\n] 2006.285.16:31:19.32#ibcon#*before write, iclass 38, count 0 2006.285.16:31:19.32#ibcon#enter sib2, iclass 38, count 0 2006.285.16:31:19.32#ibcon#flushed, iclass 38, count 0 2006.285.16:31:19.32#ibcon#about to write, iclass 38, count 0 2006.285.16:31:19.32#ibcon#wrote, iclass 38, count 0 2006.285.16:31:19.32#ibcon#about to read 3, iclass 38, count 0 2006.285.16:31:19.35#ibcon#read 3, iclass 38, count 0 2006.285.16:31:19.35#ibcon#about to read 4, iclass 38, count 0 2006.285.16:31:19.35#ibcon#read 4, iclass 38, count 0 2006.285.16:31:19.35#ibcon#about to read 5, iclass 38, count 0 2006.285.16:31:19.35#ibcon#read 5, iclass 38, count 0 2006.285.16:31:19.35#ibcon#about to read 6, iclass 38, count 0 2006.285.16:31:19.35#ibcon#read 6, iclass 38, count 0 2006.285.16:31:19.35#ibcon#end of sib2, iclass 38, count 0 2006.285.16:31:19.35#ibcon#*after write, iclass 38, count 0 2006.285.16:31:19.35#ibcon#*before return 0, iclass 38, count 0 2006.285.16:31:19.35#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:31:19.35#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:31:19.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.16:31:19.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.16:31:19.35$vck44/vblo=7,734.99 2006.285.16:31:19.35#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.16:31:19.35#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.16:31:19.35#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:19.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:31:19.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:31:19.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:31:19.35#ibcon#enter wrdev, iclass 40, count 0 2006.285.16:31:19.35#ibcon#first serial, iclass 40, count 0 2006.285.16:31:19.35#ibcon#enter sib2, iclass 40, count 0 2006.285.16:31:19.35#ibcon#flushed, iclass 40, count 0 2006.285.16:31:19.35#ibcon#about to write, iclass 40, count 0 2006.285.16:31:19.35#ibcon#wrote, iclass 40, count 0 2006.285.16:31:19.35#ibcon#about to read 3, iclass 40, count 0 2006.285.16:31:19.37#ibcon#read 3, iclass 40, count 0 2006.285.16:31:19.37#ibcon#about to read 4, iclass 40, count 0 2006.285.16:31:19.37#ibcon#read 4, iclass 40, count 0 2006.285.16:31:19.37#ibcon#about to read 5, iclass 40, count 0 2006.285.16:31:19.37#ibcon#read 5, iclass 40, count 0 2006.285.16:31:19.37#ibcon#about to read 6, iclass 40, count 0 2006.285.16:31:19.37#ibcon#read 6, iclass 40, count 0 2006.285.16:31:19.37#ibcon#end of sib2, iclass 40, count 0 2006.285.16:31:19.37#ibcon#*mode == 0, iclass 40, count 0 2006.285.16:31:19.37#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.16:31:19.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.16:31:19.37#ibcon#*before write, iclass 40, count 0 2006.285.16:31:19.37#ibcon#enter sib2, iclass 40, count 0 2006.285.16:31:19.37#ibcon#flushed, iclass 40, count 0 2006.285.16:31:19.37#ibcon#about to write, iclass 40, count 0 2006.285.16:31:19.37#ibcon#wrote, iclass 40, count 0 2006.285.16:31:19.37#ibcon#about to read 3, iclass 40, count 0 2006.285.16:31:19.41#ibcon#read 3, iclass 40, count 0 2006.285.16:31:19.41#ibcon#about to read 4, iclass 40, count 0 2006.285.16:31:19.41#ibcon#read 4, iclass 40, count 0 2006.285.16:31:19.41#ibcon#about to read 5, iclass 40, count 0 2006.285.16:31:19.41#ibcon#read 5, iclass 40, count 0 2006.285.16:31:19.41#ibcon#about to read 6, iclass 40, count 0 2006.285.16:31:19.41#ibcon#read 6, iclass 40, count 0 2006.285.16:31:19.41#ibcon#end of sib2, iclass 40, count 0 2006.285.16:31:19.41#ibcon#*after write, iclass 40, count 0 2006.285.16:31:19.41#ibcon#*before return 0, iclass 40, count 0 2006.285.16:31:19.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:31:19.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:31:19.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.16:31:19.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.16:31:19.41$vck44/vb=7,4 2006.285.16:31:19.41#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.16:31:19.41#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.16:31:19.41#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:19.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:31:19.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:31:19.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:31:19.47#ibcon#enter wrdev, iclass 4, count 2 2006.285.16:31:19.47#ibcon#first serial, iclass 4, count 2 2006.285.16:31:19.47#ibcon#enter sib2, iclass 4, count 2 2006.285.16:31:19.47#ibcon#flushed, iclass 4, count 2 2006.285.16:31:19.47#ibcon#about to write, iclass 4, count 2 2006.285.16:31:19.47#ibcon#wrote, iclass 4, count 2 2006.285.16:31:19.47#ibcon#about to read 3, iclass 4, count 2 2006.285.16:31:19.49#ibcon#read 3, iclass 4, count 2 2006.285.16:31:19.49#ibcon#about to read 4, iclass 4, count 2 2006.285.16:31:19.49#ibcon#read 4, iclass 4, count 2 2006.285.16:31:19.49#ibcon#about to read 5, iclass 4, count 2 2006.285.16:31:19.49#ibcon#read 5, iclass 4, count 2 2006.285.16:31:19.49#ibcon#about to read 6, iclass 4, count 2 2006.285.16:31:19.49#ibcon#read 6, iclass 4, count 2 2006.285.16:31:19.49#ibcon#end of sib2, iclass 4, count 2 2006.285.16:31:19.49#ibcon#*mode == 0, iclass 4, count 2 2006.285.16:31:19.49#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.16:31:19.49#ibcon#[27=AT07-04\r\n] 2006.285.16:31:19.49#ibcon#*before write, iclass 4, count 2 2006.285.16:31:19.49#ibcon#enter sib2, iclass 4, count 2 2006.285.16:31:19.49#ibcon#flushed, iclass 4, count 2 2006.285.16:31:19.49#ibcon#about to write, iclass 4, count 2 2006.285.16:31:19.49#ibcon#wrote, iclass 4, count 2 2006.285.16:31:19.49#ibcon#about to read 3, iclass 4, count 2 2006.285.16:31:19.52#ibcon#read 3, iclass 4, count 2 2006.285.16:31:19.52#ibcon#about to read 4, iclass 4, count 2 2006.285.16:31:19.52#ibcon#read 4, iclass 4, count 2 2006.285.16:31:19.52#ibcon#about to read 5, iclass 4, count 2 2006.285.16:31:19.52#ibcon#read 5, iclass 4, count 2 2006.285.16:31:19.52#ibcon#about to read 6, iclass 4, count 2 2006.285.16:31:19.52#ibcon#read 6, iclass 4, count 2 2006.285.16:31:19.52#ibcon#end of sib2, iclass 4, count 2 2006.285.16:31:19.52#ibcon#*after write, iclass 4, count 2 2006.285.16:31:19.52#ibcon#*before return 0, iclass 4, count 2 2006.285.16:31:19.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:31:19.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:31:19.52#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.16:31:19.52#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:19.52#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:31:19.64#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:31:19.64#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:31:19.64#ibcon#enter wrdev, iclass 4, count 0 2006.285.16:31:19.64#ibcon#first serial, iclass 4, count 0 2006.285.16:31:19.64#ibcon#enter sib2, iclass 4, count 0 2006.285.16:31:19.64#ibcon#flushed, iclass 4, count 0 2006.285.16:31:19.64#ibcon#about to write, iclass 4, count 0 2006.285.16:31:19.64#ibcon#wrote, iclass 4, count 0 2006.285.16:31:19.64#ibcon#about to read 3, iclass 4, count 0 2006.285.16:31:19.66#ibcon#read 3, iclass 4, count 0 2006.285.16:31:19.66#ibcon#about to read 4, iclass 4, count 0 2006.285.16:31:19.66#ibcon#read 4, iclass 4, count 0 2006.285.16:31:19.66#ibcon#about to read 5, iclass 4, count 0 2006.285.16:31:19.66#ibcon#read 5, iclass 4, count 0 2006.285.16:31:19.66#ibcon#about to read 6, iclass 4, count 0 2006.285.16:31:19.66#ibcon#read 6, iclass 4, count 0 2006.285.16:31:19.66#ibcon#end of sib2, iclass 4, count 0 2006.285.16:31:19.66#ibcon#*mode == 0, iclass 4, count 0 2006.285.16:31:19.66#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.16:31:19.66#ibcon#[27=USB\r\n] 2006.285.16:31:19.66#ibcon#*before write, iclass 4, count 0 2006.285.16:31:19.66#ibcon#enter sib2, iclass 4, count 0 2006.285.16:31:19.66#ibcon#flushed, iclass 4, count 0 2006.285.16:31:19.66#ibcon#about to write, iclass 4, count 0 2006.285.16:31:19.66#ibcon#wrote, iclass 4, count 0 2006.285.16:31:19.66#ibcon#about to read 3, iclass 4, count 0 2006.285.16:31:19.67#abcon#<5=/01 0.8 2.1 18.55 901014.9\r\n> 2006.285.16:31:19.69#abcon#{5=INTERFACE CLEAR} 2006.285.16:31:19.69#ibcon#read 3, iclass 4, count 0 2006.285.16:31:19.69#ibcon#about to read 4, iclass 4, count 0 2006.285.16:31:19.69#ibcon#read 4, iclass 4, count 0 2006.285.16:31:19.69#ibcon#about to read 5, iclass 4, count 0 2006.285.16:31:19.69#ibcon#read 5, iclass 4, count 0 2006.285.16:31:19.69#ibcon#about to read 6, iclass 4, count 0 2006.285.16:31:19.69#ibcon#read 6, iclass 4, count 0 2006.285.16:31:19.69#ibcon#end of sib2, iclass 4, count 0 2006.285.16:31:19.69#ibcon#*after write, iclass 4, count 0 2006.285.16:31:19.69#ibcon#*before return 0, iclass 4, count 0 2006.285.16:31:19.69#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:31:19.69#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:31:19.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.16:31:19.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.16:31:19.69$vck44/vblo=8,744.99 2006.285.16:31:19.69#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.16:31:19.69#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.16:31:19.69#ibcon#ireg 17 cls_cnt 0 2006.285.16:31:19.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:31:19.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:31:19.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:31:19.69#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:31:19.69#ibcon#first serial, iclass 11, count 0 2006.285.16:31:19.69#ibcon#enter sib2, iclass 11, count 0 2006.285.16:31:19.69#ibcon#flushed, iclass 11, count 0 2006.285.16:31:19.69#ibcon#about to write, iclass 11, count 0 2006.285.16:31:19.69#ibcon#wrote, iclass 11, count 0 2006.285.16:31:19.69#ibcon#about to read 3, iclass 11, count 0 2006.285.16:31:19.71#ibcon#read 3, iclass 11, count 0 2006.285.16:31:19.71#ibcon#about to read 4, iclass 11, count 0 2006.285.16:31:19.71#ibcon#read 4, iclass 11, count 0 2006.285.16:31:19.71#ibcon#about to read 5, iclass 11, count 0 2006.285.16:31:19.71#ibcon#read 5, iclass 11, count 0 2006.285.16:31:19.71#ibcon#about to read 6, iclass 11, count 0 2006.285.16:31:19.71#ibcon#read 6, iclass 11, count 0 2006.285.16:31:19.71#ibcon#end of sib2, iclass 11, count 0 2006.285.16:31:19.71#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:31:19.71#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:31:19.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.16:31:19.71#ibcon#*before write, iclass 11, count 0 2006.285.16:31:19.71#ibcon#enter sib2, iclass 11, count 0 2006.285.16:31:19.71#ibcon#flushed, iclass 11, count 0 2006.285.16:31:19.71#ibcon#about to write, iclass 11, count 0 2006.285.16:31:19.71#ibcon#wrote, iclass 11, count 0 2006.285.16:31:19.71#ibcon#about to read 3, iclass 11, count 0 2006.285.16:31:19.75#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:31:19.75#ibcon#read 3, iclass 11, count 0 2006.285.16:31:19.75#ibcon#about to read 4, iclass 11, count 0 2006.285.16:31:19.75#ibcon#read 4, iclass 11, count 0 2006.285.16:31:19.75#ibcon#about to read 5, iclass 11, count 0 2006.285.16:31:19.75#ibcon#read 5, iclass 11, count 0 2006.285.16:31:19.75#ibcon#about to read 6, iclass 11, count 0 2006.285.16:31:19.75#ibcon#read 6, iclass 11, count 0 2006.285.16:31:19.75#ibcon#end of sib2, iclass 11, count 0 2006.285.16:31:19.75#ibcon#*after write, iclass 11, count 0 2006.285.16:31:19.75#ibcon#*before return 0, iclass 11, count 0 2006.285.16:31:19.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:31:19.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:31:19.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:31:19.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:31:19.75$vck44/vb=8,4 2006.285.16:31:19.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.16:31:19.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.16:31:19.75#ibcon#ireg 11 cls_cnt 2 2006.285.16:31:19.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:31:19.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:31:19.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:31:19.81#ibcon#enter wrdev, iclass 14, count 2 2006.285.16:31:19.81#ibcon#first serial, iclass 14, count 2 2006.285.16:31:19.81#ibcon#enter sib2, iclass 14, count 2 2006.285.16:31:19.81#ibcon#flushed, iclass 14, count 2 2006.285.16:31:19.81#ibcon#about to write, iclass 14, count 2 2006.285.16:31:19.81#ibcon#wrote, iclass 14, count 2 2006.285.16:31:19.81#ibcon#about to read 3, iclass 14, count 2 2006.285.16:31:19.83#ibcon#read 3, iclass 14, count 2 2006.285.16:31:19.83#ibcon#about to read 4, iclass 14, count 2 2006.285.16:31:19.83#ibcon#read 4, iclass 14, count 2 2006.285.16:31:19.83#ibcon#about to read 5, iclass 14, count 2 2006.285.16:31:19.83#ibcon#read 5, iclass 14, count 2 2006.285.16:31:19.83#ibcon#about to read 6, iclass 14, count 2 2006.285.16:31:19.83#ibcon#read 6, iclass 14, count 2 2006.285.16:31:19.83#ibcon#end of sib2, iclass 14, count 2 2006.285.16:31:19.83#ibcon#*mode == 0, iclass 14, count 2 2006.285.16:31:19.83#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.16:31:19.83#ibcon#[27=AT08-04\r\n] 2006.285.16:31:19.83#ibcon#*before write, iclass 14, count 2 2006.285.16:31:19.83#ibcon#enter sib2, iclass 14, count 2 2006.285.16:31:19.83#ibcon#flushed, iclass 14, count 2 2006.285.16:31:19.83#ibcon#about to write, iclass 14, count 2 2006.285.16:31:19.83#ibcon#wrote, iclass 14, count 2 2006.285.16:31:19.83#ibcon#about to read 3, iclass 14, count 2 2006.285.16:31:19.86#ibcon#read 3, iclass 14, count 2 2006.285.16:31:19.86#ibcon#about to read 4, iclass 14, count 2 2006.285.16:31:19.86#ibcon#read 4, iclass 14, count 2 2006.285.16:31:19.86#ibcon#about to read 5, iclass 14, count 2 2006.285.16:31:19.86#ibcon#read 5, iclass 14, count 2 2006.285.16:31:19.86#ibcon#about to read 6, iclass 14, count 2 2006.285.16:31:19.86#ibcon#read 6, iclass 14, count 2 2006.285.16:31:19.86#ibcon#end of sib2, iclass 14, count 2 2006.285.16:31:19.86#ibcon#*after write, iclass 14, count 2 2006.285.16:31:19.86#ibcon#*before return 0, iclass 14, count 2 2006.285.16:31:19.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:31:19.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:31:19.86#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.16:31:19.86#ibcon#ireg 7 cls_cnt 0 2006.285.16:31:19.86#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:31:19.98#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:31:19.98#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:31:19.98#ibcon#enter wrdev, iclass 14, count 0 2006.285.16:31:19.98#ibcon#first serial, iclass 14, count 0 2006.285.16:31:19.98#ibcon#enter sib2, iclass 14, count 0 2006.285.16:31:19.98#ibcon#flushed, iclass 14, count 0 2006.285.16:31:19.98#ibcon#about to write, iclass 14, count 0 2006.285.16:31:19.98#ibcon#wrote, iclass 14, count 0 2006.285.16:31:19.98#ibcon#about to read 3, iclass 14, count 0 2006.285.16:31:20.00#ibcon#read 3, iclass 14, count 0 2006.285.16:31:20.00#ibcon#about to read 4, iclass 14, count 0 2006.285.16:31:20.00#ibcon#read 4, iclass 14, count 0 2006.285.16:31:20.00#ibcon#about to read 5, iclass 14, count 0 2006.285.16:31:20.00#ibcon#read 5, iclass 14, count 0 2006.285.16:31:20.00#ibcon#about to read 6, iclass 14, count 0 2006.285.16:31:20.00#ibcon#read 6, iclass 14, count 0 2006.285.16:31:20.00#ibcon#end of sib2, iclass 14, count 0 2006.285.16:31:20.00#ibcon#*mode == 0, iclass 14, count 0 2006.285.16:31:20.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.16:31:20.00#ibcon#[27=USB\r\n] 2006.285.16:31:20.00#ibcon#*before write, iclass 14, count 0 2006.285.16:31:20.00#ibcon#enter sib2, iclass 14, count 0 2006.285.16:31:20.00#ibcon#flushed, iclass 14, count 0 2006.285.16:31:20.00#ibcon#about to write, iclass 14, count 0 2006.285.16:31:20.00#ibcon#wrote, iclass 14, count 0 2006.285.16:31:20.00#ibcon#about to read 3, iclass 14, count 0 2006.285.16:31:20.03#ibcon#read 3, iclass 14, count 0 2006.285.16:31:20.03#ibcon#about to read 4, iclass 14, count 0 2006.285.16:31:20.03#ibcon#read 4, iclass 14, count 0 2006.285.16:31:20.03#ibcon#about to read 5, iclass 14, count 0 2006.285.16:31:20.03#ibcon#read 5, iclass 14, count 0 2006.285.16:31:20.03#ibcon#about to read 6, iclass 14, count 0 2006.285.16:31:20.03#ibcon#read 6, iclass 14, count 0 2006.285.16:31:20.03#ibcon#end of sib2, iclass 14, count 0 2006.285.16:31:20.03#ibcon#*after write, iclass 14, count 0 2006.285.16:31:20.03#ibcon#*before return 0, iclass 14, count 0 2006.285.16:31:20.03#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:31:20.03#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:31:20.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.16:31:20.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.16:31:20.03$vck44/vabw=wide 2006.285.16:31:20.10#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.16:31:20.10#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.16:31:20.10#ibcon#ireg 8 cls_cnt 0 2006.285.16:31:20.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:31:20.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:31:20.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:31:20.10#ibcon#enter wrdev, iclass 16, count 0 2006.285.16:31:20.10#ibcon#first serial, iclass 16, count 0 2006.285.16:31:20.10#ibcon#enter sib2, iclass 16, count 0 2006.285.16:31:20.10#ibcon#flushed, iclass 16, count 0 2006.285.16:31:20.10#ibcon#about to write, iclass 16, count 0 2006.285.16:31:20.10#ibcon#wrote, iclass 16, count 0 2006.285.16:31:20.10#ibcon#about to read 3, iclass 16, count 0 2006.285.16:31:20.12#ibcon#read 3, iclass 16, count 0 2006.285.16:31:20.12#ibcon#about to read 4, iclass 16, count 0 2006.285.16:31:20.12#ibcon#read 4, iclass 16, count 0 2006.285.16:31:20.12#ibcon#about to read 5, iclass 16, count 0 2006.285.16:31:20.12#ibcon#read 5, iclass 16, count 0 2006.285.16:31:20.12#ibcon#about to read 6, iclass 16, count 0 2006.285.16:31:20.12#ibcon#read 6, iclass 16, count 0 2006.285.16:31:20.12#ibcon#end of sib2, iclass 16, count 0 2006.285.16:31:20.12#ibcon#*mode == 0, iclass 16, count 0 2006.285.16:31:20.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.16:31:20.12#ibcon#[25=BW32\r\n] 2006.285.16:31:20.12#ibcon#*before write, iclass 16, count 0 2006.285.16:31:20.12#ibcon#enter sib2, iclass 16, count 0 2006.285.16:31:20.12#ibcon#flushed, iclass 16, count 0 2006.285.16:31:20.12#ibcon#about to write, iclass 16, count 0 2006.285.16:31:20.12#ibcon#wrote, iclass 16, count 0 2006.285.16:31:20.12#ibcon#about to read 3, iclass 16, count 0 2006.285.16:31:20.15#ibcon#read 3, iclass 16, count 0 2006.285.16:31:20.15#ibcon#about to read 4, iclass 16, count 0 2006.285.16:31:20.15#ibcon#read 4, iclass 16, count 0 2006.285.16:31:20.15#ibcon#about to read 5, iclass 16, count 0 2006.285.16:31:20.15#ibcon#read 5, iclass 16, count 0 2006.285.16:31:20.15#ibcon#about to read 6, iclass 16, count 0 2006.285.16:31:20.15#ibcon#read 6, iclass 16, count 0 2006.285.16:31:20.15#ibcon#end of sib2, iclass 16, count 0 2006.285.16:31:20.15#ibcon#*after write, iclass 16, count 0 2006.285.16:31:20.15#ibcon#*before return 0, iclass 16, count 0 2006.285.16:31:20.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:31:20.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:31:20.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.16:31:20.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.16:31:20.15$vck44/vbbw=wide 2006.285.16:31:20.15#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.16:31:20.15#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.16:31:20.15#ibcon#ireg 8 cls_cnt 0 2006.285.16:31:20.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:31:20.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:31:20.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:31:20.15#ibcon#enter wrdev, iclass 18, count 0 2006.285.16:31:20.15#ibcon#first serial, iclass 18, count 0 2006.285.16:31:20.15#ibcon#enter sib2, iclass 18, count 0 2006.285.16:31:20.15#ibcon#flushed, iclass 18, count 0 2006.285.16:31:20.15#ibcon#about to write, iclass 18, count 0 2006.285.16:31:20.15#ibcon#wrote, iclass 18, count 0 2006.285.16:31:20.15#ibcon#about to read 3, iclass 18, count 0 2006.285.16:31:20.17#ibcon#read 3, iclass 18, count 0 2006.285.16:31:20.17#ibcon#about to read 4, iclass 18, count 0 2006.285.16:31:20.17#ibcon#read 4, iclass 18, count 0 2006.285.16:31:20.17#ibcon#about to read 5, iclass 18, count 0 2006.285.16:31:20.17#ibcon#read 5, iclass 18, count 0 2006.285.16:31:20.17#ibcon#about to read 6, iclass 18, count 0 2006.285.16:31:20.17#ibcon#read 6, iclass 18, count 0 2006.285.16:31:20.17#ibcon#end of sib2, iclass 18, count 0 2006.285.16:31:20.17#ibcon#*mode == 0, iclass 18, count 0 2006.285.16:31:20.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.16:31:20.17#ibcon#[27=BW32\r\n] 2006.285.16:31:20.17#ibcon#*before write, iclass 18, count 0 2006.285.16:31:20.17#ibcon#enter sib2, iclass 18, count 0 2006.285.16:31:20.17#ibcon#flushed, iclass 18, count 0 2006.285.16:31:20.17#ibcon#about to write, iclass 18, count 0 2006.285.16:31:20.17#ibcon#wrote, iclass 18, count 0 2006.285.16:31:20.17#ibcon#about to read 3, iclass 18, count 0 2006.285.16:31:20.20#ibcon#read 3, iclass 18, count 0 2006.285.16:31:20.20#ibcon#about to read 4, iclass 18, count 0 2006.285.16:31:20.20#ibcon#read 4, iclass 18, count 0 2006.285.16:31:20.20#ibcon#about to read 5, iclass 18, count 0 2006.285.16:31:20.20#ibcon#read 5, iclass 18, count 0 2006.285.16:31:20.20#ibcon#about to read 6, iclass 18, count 0 2006.285.16:31:20.20#ibcon#read 6, iclass 18, count 0 2006.285.16:31:20.20#ibcon#end of sib2, iclass 18, count 0 2006.285.16:31:20.20#ibcon#*after write, iclass 18, count 0 2006.285.16:31:20.20#ibcon#*before return 0, iclass 18, count 0 2006.285.16:31:20.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:31:20.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:31:20.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.16:31:20.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.16:31:20.20$setupk4/ifdk4 2006.285.16:31:20.20$ifdk4/lo= 2006.285.16:31:20.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.16:31:20.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.16:31:20.20$ifdk4/patch= 2006.285.16:31:20.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.16:31:20.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.16:31:20.20$setupk4/!*+20s 2006.285.16:31:29.84#abcon#<5=/01 0.8 2.1 18.55 901014.9\r\n> 2006.285.16:31:29.86#abcon#{5=INTERFACE CLEAR} 2006.285.16:31:29.92#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:31:33.73$setupk4/"tpicd 2006.285.16:31:33.73$setupk4/echo=off 2006.285.16:31:33.73$setupk4/xlog=off 2006.285.16:31:33.73:!2006.285.16:37:12 2006.285.16:31:53.14#trakl#Source acquired 2006.285.16:31:53.14#flagr#flagr/antenna,acquired 2006.285.16:37:12.00:preob 2006.285.16:37:12.13/onsource/TRACKING 2006.285.16:37:12.13:!2006.285.16:37:22 2006.285.16:37:22.00:"tape 2006.285.16:37:22.00:"st=record 2006.285.16:37:22.00:data_valid=on 2006.285.16:37:22.00:midob 2006.285.16:37:23.14/onsource/TRACKING 2006.285.16:37:23.15/wx/18.45,1014.9,91 2006.285.16:37:23.19/cable/+6.5023E-03 2006.285.16:37:24.28/va/01,07,usb,yes,32,34 2006.285.16:37:24.28/va/02,06,usb,yes,32,32 2006.285.16:37:24.28/va/03,07,usb,yes,31,33 2006.285.16:37:24.28/va/04,06,usb,yes,33,34 2006.285.16:37:24.28/va/05,03,usb,yes,32,32 2006.285.16:37:24.28/va/06,04,usb,yes,29,28 2006.285.16:37:24.28/va/07,04,usb,yes,29,30 2006.285.16:37:24.28/va/08,03,usb,yes,30,37 2006.285.16:37:24.51/valo/01,524.99,yes,locked 2006.285.16:37:24.51/valo/02,534.99,yes,locked 2006.285.16:37:24.51/valo/03,564.99,yes,locked 2006.285.16:37:24.51/valo/04,624.99,yes,locked 2006.285.16:37:24.51/valo/05,734.99,yes,locked 2006.285.16:37:24.51/valo/06,814.99,yes,locked 2006.285.16:37:24.51/valo/07,864.99,yes,locked 2006.285.16:37:24.51/valo/08,884.99,yes,locked 2006.285.16:37:25.60/vb/01,04,usb,yes,30,28 2006.285.16:37:25.60/vb/02,05,usb,yes,28,28 2006.285.16:37:25.60/vb/03,04,usb,yes,29,32 2006.285.16:37:25.60/vb/04,05,usb,yes,29,28 2006.285.16:37:25.60/vb/05,04,usb,yes,26,28 2006.285.16:37:25.60/vb/06,03,usb,yes,37,33 2006.285.16:37:25.60/vb/07,04,usb,yes,30,30 2006.285.16:37:25.60/vb/08,04,usb,yes,27,31 2006.285.16:37:25.84/vblo/01,629.99,yes,locked 2006.285.16:37:25.84/vblo/02,634.99,yes,locked 2006.285.16:37:25.84/vblo/03,649.99,yes,locked 2006.285.16:37:25.84/vblo/04,679.99,yes,locked 2006.285.16:37:25.84/vblo/05,709.99,yes,locked 2006.285.16:37:25.84/vblo/06,719.99,yes,locked 2006.285.16:37:25.84/vblo/07,734.99,yes,locked 2006.285.16:37:25.84/vblo/08,744.99,yes,locked 2006.285.16:37:25.99/vabw/8 2006.285.16:37:26.14/vbbw/8 2006.285.16:37:26.32/xfe/off,on,12.2 2006.285.16:37:26.69/ifatt/23,28,28,28 2006.285.16:37:27.07/fmout-gps/S +2.56E-07 2006.285.16:37:27.09:!2006.285.16:39:02 2006.285.16:39:02.01:data_valid=off 2006.285.16:39:02.01:"et 2006.285.16:39:02.01:!+3s 2006.285.16:39:05.04:"tape 2006.285.16:39:05.04:postob 2006.285.16:39:05.11/cable/+6.5014E-03 2006.285.16:39:05.11/wx/18.40,1014.9,92 2006.285.16:39:05.17/fmout-gps/S +2.58E-07 2006.285.16:39:05.17:scan_name=285-1640,jd0610,50 2006.285.16:39:05.17:source=0552+398,055530.81,394849.2,2000.0,cw 2006.285.16:39:07.14#flagr#flagr/antenna,new-source 2006.285.16:39:07.14:checkk5 2006.285.16:39:07.61/chk_autoobs//k5ts1/ autoobs is running! 2006.285.16:39:08.00/chk_autoobs//k5ts2/ autoobs is running! 2006.285.16:39:08.40/chk_autoobs//k5ts3/ autoobs is running! 2006.285.16:39:08.95/chk_autoobs//k5ts4/ autoobs is running! 2006.285.16:39:09.34/chk_obsdata//k5ts1/T2851637??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.16:39:09.91/chk_obsdata//k5ts2/T2851637??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.16:39:10.35/chk_obsdata//k5ts3/T2851637??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.16:39:10.94/chk_obsdata//k5ts4/T2851637??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.16:39:12.06/k5log//k5ts1_log_newline 2006.285.16:39:13.12/k5log//k5ts2_log_newline 2006.285.16:39:14.10/k5log//k5ts3_log_newline 2006.285.16:39:14.85/k5log//k5ts4_log_newline 2006.285.16:39:14.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.16:39:14.87:setupk4=1 2006.285.16:39:14.87$setupk4/echo=on 2006.285.16:39:14.87$setupk4/pcalon 2006.285.16:39:14.87$pcalon/"no phase cal control is implemented here 2006.285.16:39:14.87$setupk4/"tpicd=stop 2006.285.16:39:14.87$setupk4/"rec=synch_on 2006.285.16:39:14.87$setupk4/"rec_mode=128 2006.285.16:39:14.87$setupk4/!* 2006.285.16:39:14.87$setupk4/recpk4 2006.285.16:39:14.87$recpk4/recpatch= 2006.285.16:39:14.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.16:39:14.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.16:39:14.88$setupk4/vck44 2006.285.16:39:14.88$vck44/valo=1,524.99 2006.285.16:39:14.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.16:39:14.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.16:39:14.88#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:14.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:39:14.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:39:14.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:39:14.88#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:39:14.88#ibcon#first serial, iclass 27, count 0 2006.285.16:39:14.88#ibcon#enter sib2, iclass 27, count 0 2006.285.16:39:14.88#ibcon#flushed, iclass 27, count 0 2006.285.16:39:14.88#ibcon#about to write, iclass 27, count 0 2006.285.16:39:14.88#ibcon#wrote, iclass 27, count 0 2006.285.16:39:14.88#ibcon#about to read 3, iclass 27, count 0 2006.285.16:39:14.89#ibcon#read 3, iclass 27, count 0 2006.285.16:39:14.89#ibcon#about to read 4, iclass 27, count 0 2006.285.16:39:14.89#ibcon#read 4, iclass 27, count 0 2006.285.16:39:14.89#ibcon#about to read 5, iclass 27, count 0 2006.285.16:39:14.89#ibcon#read 5, iclass 27, count 0 2006.285.16:39:14.89#ibcon#about to read 6, iclass 27, count 0 2006.285.16:39:14.89#ibcon#read 6, iclass 27, count 0 2006.285.16:39:14.89#ibcon#end of sib2, iclass 27, count 0 2006.285.16:39:14.89#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:39:14.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:39:14.89#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.16:39:14.89#ibcon#*before write, iclass 27, count 0 2006.285.16:39:14.89#ibcon#enter sib2, iclass 27, count 0 2006.285.16:39:14.89#ibcon#flushed, iclass 27, count 0 2006.285.16:39:14.89#ibcon#about to write, iclass 27, count 0 2006.285.16:39:14.89#ibcon#wrote, iclass 27, count 0 2006.285.16:39:14.89#ibcon#about to read 3, iclass 27, count 0 2006.285.16:39:14.94#ibcon#read 3, iclass 27, count 0 2006.285.16:39:14.94#ibcon#about to read 4, iclass 27, count 0 2006.285.16:39:14.94#ibcon#read 4, iclass 27, count 0 2006.285.16:39:14.94#ibcon#about to read 5, iclass 27, count 0 2006.285.16:39:14.94#ibcon#read 5, iclass 27, count 0 2006.285.16:39:14.94#ibcon#about to read 6, iclass 27, count 0 2006.285.16:39:14.94#ibcon#read 6, iclass 27, count 0 2006.285.16:39:14.94#ibcon#end of sib2, iclass 27, count 0 2006.285.16:39:14.94#ibcon#*after write, iclass 27, count 0 2006.285.16:39:14.94#ibcon#*before return 0, iclass 27, count 0 2006.285.16:39:14.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:39:14.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:39:14.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:39:14.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:39:14.94$vck44/va=1,7 2006.285.16:39:14.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.16:39:14.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.16:39:14.95#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:14.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:39:14.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:39:14.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:39:14.95#ibcon#enter wrdev, iclass 29, count 2 2006.285.16:39:14.95#ibcon#first serial, iclass 29, count 2 2006.285.16:39:14.95#ibcon#enter sib2, iclass 29, count 2 2006.285.16:39:14.95#ibcon#flushed, iclass 29, count 2 2006.285.16:39:14.95#ibcon#about to write, iclass 29, count 2 2006.285.16:39:14.95#ibcon#wrote, iclass 29, count 2 2006.285.16:39:14.95#ibcon#about to read 3, iclass 29, count 2 2006.285.16:39:14.96#ibcon#read 3, iclass 29, count 2 2006.285.16:39:14.96#ibcon#about to read 4, iclass 29, count 2 2006.285.16:39:14.96#ibcon#read 4, iclass 29, count 2 2006.285.16:39:14.96#ibcon#about to read 5, iclass 29, count 2 2006.285.16:39:14.96#ibcon#read 5, iclass 29, count 2 2006.285.16:39:14.96#ibcon#about to read 6, iclass 29, count 2 2006.285.16:39:14.96#ibcon#read 6, iclass 29, count 2 2006.285.16:39:14.96#ibcon#end of sib2, iclass 29, count 2 2006.285.16:39:14.96#ibcon#*mode == 0, iclass 29, count 2 2006.285.16:39:14.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.16:39:14.96#ibcon#[25=AT01-07\r\n] 2006.285.16:39:14.96#ibcon#*before write, iclass 29, count 2 2006.285.16:39:14.96#ibcon#enter sib2, iclass 29, count 2 2006.285.16:39:14.96#ibcon#flushed, iclass 29, count 2 2006.285.16:39:14.96#ibcon#about to write, iclass 29, count 2 2006.285.16:39:14.96#ibcon#wrote, iclass 29, count 2 2006.285.16:39:14.96#ibcon#about to read 3, iclass 29, count 2 2006.285.16:39:14.99#ibcon#read 3, iclass 29, count 2 2006.285.16:39:14.99#ibcon#about to read 4, iclass 29, count 2 2006.285.16:39:14.99#ibcon#read 4, iclass 29, count 2 2006.285.16:39:14.99#ibcon#about to read 5, iclass 29, count 2 2006.285.16:39:14.99#ibcon#read 5, iclass 29, count 2 2006.285.16:39:14.99#ibcon#about to read 6, iclass 29, count 2 2006.285.16:39:14.99#ibcon#read 6, iclass 29, count 2 2006.285.16:39:14.99#ibcon#end of sib2, iclass 29, count 2 2006.285.16:39:14.99#ibcon#*after write, iclass 29, count 2 2006.285.16:39:14.99#ibcon#*before return 0, iclass 29, count 2 2006.285.16:39:14.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:39:14.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:39:14.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.16:39:14.99#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:14.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:39:15.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:39:15.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:39:15.11#ibcon#enter wrdev, iclass 29, count 0 2006.285.16:39:15.11#ibcon#first serial, iclass 29, count 0 2006.285.16:39:15.11#ibcon#enter sib2, iclass 29, count 0 2006.285.16:39:15.11#ibcon#flushed, iclass 29, count 0 2006.285.16:39:15.11#ibcon#about to write, iclass 29, count 0 2006.285.16:39:15.11#ibcon#wrote, iclass 29, count 0 2006.285.16:39:15.11#ibcon#about to read 3, iclass 29, count 0 2006.285.16:39:15.13#ibcon#read 3, iclass 29, count 0 2006.285.16:39:15.13#ibcon#about to read 4, iclass 29, count 0 2006.285.16:39:15.13#ibcon#read 4, iclass 29, count 0 2006.285.16:39:15.13#ibcon#about to read 5, iclass 29, count 0 2006.285.16:39:15.13#ibcon#read 5, iclass 29, count 0 2006.285.16:39:15.13#ibcon#about to read 6, iclass 29, count 0 2006.285.16:39:15.13#ibcon#read 6, iclass 29, count 0 2006.285.16:39:15.13#ibcon#end of sib2, iclass 29, count 0 2006.285.16:39:15.13#ibcon#*mode == 0, iclass 29, count 0 2006.285.16:39:15.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.16:39:15.13#ibcon#[25=USB\r\n] 2006.285.16:39:15.13#ibcon#*before write, iclass 29, count 0 2006.285.16:39:15.13#ibcon#enter sib2, iclass 29, count 0 2006.285.16:39:15.13#ibcon#flushed, iclass 29, count 0 2006.285.16:39:15.13#ibcon#about to write, iclass 29, count 0 2006.285.16:39:15.13#ibcon#wrote, iclass 29, count 0 2006.285.16:39:15.13#ibcon#about to read 3, iclass 29, count 0 2006.285.16:39:15.16#ibcon#read 3, iclass 29, count 0 2006.285.16:39:15.16#ibcon#about to read 4, iclass 29, count 0 2006.285.16:39:15.16#ibcon#read 4, iclass 29, count 0 2006.285.16:39:15.16#ibcon#about to read 5, iclass 29, count 0 2006.285.16:39:15.16#ibcon#read 5, iclass 29, count 0 2006.285.16:39:15.16#ibcon#about to read 6, iclass 29, count 0 2006.285.16:39:15.16#ibcon#read 6, iclass 29, count 0 2006.285.16:39:15.16#ibcon#end of sib2, iclass 29, count 0 2006.285.16:39:15.16#ibcon#*after write, iclass 29, count 0 2006.285.16:39:15.16#ibcon#*before return 0, iclass 29, count 0 2006.285.16:39:15.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:39:15.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:39:15.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.16:39:15.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.16:39:15.17$vck44/valo=2,534.99 2006.285.16:39:15.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.16:39:15.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.16:39:15.17#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:15.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:39:15.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:39:15.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:39:15.17#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:39:15.17#ibcon#first serial, iclass 31, count 0 2006.285.16:39:15.17#ibcon#enter sib2, iclass 31, count 0 2006.285.16:39:15.17#ibcon#flushed, iclass 31, count 0 2006.285.16:39:15.17#ibcon#about to write, iclass 31, count 0 2006.285.16:39:15.17#ibcon#wrote, iclass 31, count 0 2006.285.16:39:15.17#ibcon#about to read 3, iclass 31, count 0 2006.285.16:39:15.18#ibcon#read 3, iclass 31, count 0 2006.285.16:39:15.18#ibcon#about to read 4, iclass 31, count 0 2006.285.16:39:15.18#ibcon#read 4, iclass 31, count 0 2006.285.16:39:15.18#ibcon#about to read 5, iclass 31, count 0 2006.285.16:39:15.18#ibcon#read 5, iclass 31, count 0 2006.285.16:39:15.18#ibcon#about to read 6, iclass 31, count 0 2006.285.16:39:15.18#ibcon#read 6, iclass 31, count 0 2006.285.16:39:15.18#ibcon#end of sib2, iclass 31, count 0 2006.285.16:39:15.18#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:39:15.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:39:15.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.16:39:15.18#ibcon#*before write, iclass 31, count 0 2006.285.16:39:15.18#ibcon#enter sib2, iclass 31, count 0 2006.285.16:39:15.18#ibcon#flushed, iclass 31, count 0 2006.285.16:39:15.18#ibcon#about to write, iclass 31, count 0 2006.285.16:39:15.18#ibcon#wrote, iclass 31, count 0 2006.285.16:39:15.18#ibcon#about to read 3, iclass 31, count 0 2006.285.16:39:15.22#ibcon#read 3, iclass 31, count 0 2006.285.16:39:15.22#ibcon#about to read 4, iclass 31, count 0 2006.285.16:39:15.22#ibcon#read 4, iclass 31, count 0 2006.285.16:39:15.22#ibcon#about to read 5, iclass 31, count 0 2006.285.16:39:15.22#ibcon#read 5, iclass 31, count 0 2006.285.16:39:15.22#ibcon#about to read 6, iclass 31, count 0 2006.285.16:39:15.22#ibcon#read 6, iclass 31, count 0 2006.285.16:39:15.22#ibcon#end of sib2, iclass 31, count 0 2006.285.16:39:15.22#ibcon#*after write, iclass 31, count 0 2006.285.16:39:15.22#ibcon#*before return 0, iclass 31, count 0 2006.285.16:39:15.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:39:15.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:39:15.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:39:15.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:39:15.23$vck44/va=2,6 2006.285.16:39:15.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.16:39:15.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.16:39:15.23#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:15.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:39:15.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:39:15.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:39:15.27#ibcon#enter wrdev, iclass 33, count 2 2006.285.16:39:15.27#ibcon#first serial, iclass 33, count 2 2006.285.16:39:15.27#ibcon#enter sib2, iclass 33, count 2 2006.285.16:39:15.27#ibcon#flushed, iclass 33, count 2 2006.285.16:39:15.27#ibcon#about to write, iclass 33, count 2 2006.285.16:39:15.27#ibcon#wrote, iclass 33, count 2 2006.285.16:39:15.27#ibcon#about to read 3, iclass 33, count 2 2006.285.16:39:15.29#ibcon#read 3, iclass 33, count 2 2006.285.16:39:15.29#ibcon#about to read 4, iclass 33, count 2 2006.285.16:39:15.29#ibcon#read 4, iclass 33, count 2 2006.285.16:39:15.29#ibcon#about to read 5, iclass 33, count 2 2006.285.16:39:15.29#ibcon#read 5, iclass 33, count 2 2006.285.16:39:15.29#ibcon#about to read 6, iclass 33, count 2 2006.285.16:39:15.29#ibcon#read 6, iclass 33, count 2 2006.285.16:39:15.29#ibcon#end of sib2, iclass 33, count 2 2006.285.16:39:15.29#ibcon#*mode == 0, iclass 33, count 2 2006.285.16:39:15.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.16:39:15.29#ibcon#[25=AT02-06\r\n] 2006.285.16:39:15.29#ibcon#*before write, iclass 33, count 2 2006.285.16:39:15.29#ibcon#enter sib2, iclass 33, count 2 2006.285.16:39:15.29#ibcon#flushed, iclass 33, count 2 2006.285.16:39:15.29#ibcon#about to write, iclass 33, count 2 2006.285.16:39:15.29#ibcon#wrote, iclass 33, count 2 2006.285.16:39:15.29#ibcon#about to read 3, iclass 33, count 2 2006.285.16:39:15.32#ibcon#read 3, iclass 33, count 2 2006.285.16:39:15.32#ibcon#about to read 4, iclass 33, count 2 2006.285.16:39:15.32#ibcon#read 4, iclass 33, count 2 2006.285.16:39:15.32#ibcon#about to read 5, iclass 33, count 2 2006.285.16:39:15.32#ibcon#read 5, iclass 33, count 2 2006.285.16:39:15.32#ibcon#about to read 6, iclass 33, count 2 2006.285.16:39:15.32#ibcon#read 6, iclass 33, count 2 2006.285.16:39:15.32#ibcon#end of sib2, iclass 33, count 2 2006.285.16:39:15.32#ibcon#*after write, iclass 33, count 2 2006.285.16:39:15.32#ibcon#*before return 0, iclass 33, count 2 2006.285.16:39:15.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:39:15.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:39:15.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.16:39:15.32#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:15.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:39:15.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:39:15.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:39:15.44#ibcon#enter wrdev, iclass 33, count 0 2006.285.16:39:15.44#ibcon#first serial, iclass 33, count 0 2006.285.16:39:15.44#ibcon#enter sib2, iclass 33, count 0 2006.285.16:39:15.44#ibcon#flushed, iclass 33, count 0 2006.285.16:39:15.44#ibcon#about to write, iclass 33, count 0 2006.285.16:39:15.44#ibcon#wrote, iclass 33, count 0 2006.285.16:39:15.44#ibcon#about to read 3, iclass 33, count 0 2006.285.16:39:15.46#ibcon#read 3, iclass 33, count 0 2006.285.16:39:15.46#ibcon#about to read 4, iclass 33, count 0 2006.285.16:39:15.46#ibcon#read 4, iclass 33, count 0 2006.285.16:39:15.46#ibcon#about to read 5, iclass 33, count 0 2006.285.16:39:15.46#ibcon#read 5, iclass 33, count 0 2006.285.16:39:15.46#ibcon#about to read 6, iclass 33, count 0 2006.285.16:39:15.46#ibcon#read 6, iclass 33, count 0 2006.285.16:39:15.46#ibcon#end of sib2, iclass 33, count 0 2006.285.16:39:15.46#ibcon#*mode == 0, iclass 33, count 0 2006.285.16:39:15.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.16:39:15.46#ibcon#[25=USB\r\n] 2006.285.16:39:15.46#ibcon#*before write, iclass 33, count 0 2006.285.16:39:15.46#ibcon#enter sib2, iclass 33, count 0 2006.285.16:39:15.46#ibcon#flushed, iclass 33, count 0 2006.285.16:39:15.46#ibcon#about to write, iclass 33, count 0 2006.285.16:39:15.46#ibcon#wrote, iclass 33, count 0 2006.285.16:39:15.46#ibcon#about to read 3, iclass 33, count 0 2006.285.16:39:15.49#ibcon#read 3, iclass 33, count 0 2006.285.16:39:15.49#ibcon#about to read 4, iclass 33, count 0 2006.285.16:39:15.49#ibcon#read 4, iclass 33, count 0 2006.285.16:39:15.49#ibcon#about to read 5, iclass 33, count 0 2006.285.16:39:15.49#ibcon#read 5, iclass 33, count 0 2006.285.16:39:15.49#ibcon#about to read 6, iclass 33, count 0 2006.285.16:39:15.49#ibcon#read 6, iclass 33, count 0 2006.285.16:39:15.49#ibcon#end of sib2, iclass 33, count 0 2006.285.16:39:15.49#ibcon#*after write, iclass 33, count 0 2006.285.16:39:15.49#ibcon#*before return 0, iclass 33, count 0 2006.285.16:39:15.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:39:15.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:39:15.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.16:39:15.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.16:39:15.50$vck44/valo=3,564.99 2006.285.16:39:15.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.16:39:15.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.16:39:15.50#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:15.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:39:15.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:39:15.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:39:15.50#ibcon#enter wrdev, iclass 35, count 0 2006.285.16:39:15.50#ibcon#first serial, iclass 35, count 0 2006.285.16:39:15.50#ibcon#enter sib2, iclass 35, count 0 2006.285.16:39:15.50#ibcon#flushed, iclass 35, count 0 2006.285.16:39:15.50#ibcon#about to write, iclass 35, count 0 2006.285.16:39:15.50#ibcon#wrote, iclass 35, count 0 2006.285.16:39:15.50#ibcon#about to read 3, iclass 35, count 0 2006.285.16:39:15.51#ibcon#read 3, iclass 35, count 0 2006.285.16:39:15.51#ibcon#about to read 4, iclass 35, count 0 2006.285.16:39:15.51#ibcon#read 4, iclass 35, count 0 2006.285.16:39:15.51#ibcon#about to read 5, iclass 35, count 0 2006.285.16:39:15.51#ibcon#read 5, iclass 35, count 0 2006.285.16:39:15.51#ibcon#about to read 6, iclass 35, count 0 2006.285.16:39:15.51#ibcon#read 6, iclass 35, count 0 2006.285.16:39:15.51#ibcon#end of sib2, iclass 35, count 0 2006.285.16:39:15.51#ibcon#*mode == 0, iclass 35, count 0 2006.285.16:39:15.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.16:39:15.51#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.16:39:15.51#ibcon#*before write, iclass 35, count 0 2006.285.16:39:15.51#ibcon#enter sib2, iclass 35, count 0 2006.285.16:39:15.51#ibcon#flushed, iclass 35, count 0 2006.285.16:39:15.51#ibcon#about to write, iclass 35, count 0 2006.285.16:39:15.51#ibcon#wrote, iclass 35, count 0 2006.285.16:39:15.51#ibcon#about to read 3, iclass 35, count 0 2006.285.16:39:15.55#ibcon#read 3, iclass 35, count 0 2006.285.16:39:15.55#ibcon#about to read 4, iclass 35, count 0 2006.285.16:39:15.55#ibcon#read 4, iclass 35, count 0 2006.285.16:39:15.55#ibcon#about to read 5, iclass 35, count 0 2006.285.16:39:15.55#ibcon#read 5, iclass 35, count 0 2006.285.16:39:15.55#ibcon#about to read 6, iclass 35, count 0 2006.285.16:39:15.55#ibcon#read 6, iclass 35, count 0 2006.285.16:39:15.55#ibcon#end of sib2, iclass 35, count 0 2006.285.16:39:15.55#ibcon#*after write, iclass 35, count 0 2006.285.16:39:15.55#ibcon#*before return 0, iclass 35, count 0 2006.285.16:39:15.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:39:15.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:39:15.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.16:39:15.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.16:39:15.55$vck44/va=3,7 2006.285.16:39:15.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.16:39:15.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.16:39:15.55#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:15.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:39:15.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:39:15.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:39:15.61#ibcon#enter wrdev, iclass 37, count 2 2006.285.16:39:15.61#ibcon#first serial, iclass 37, count 2 2006.285.16:39:15.61#ibcon#enter sib2, iclass 37, count 2 2006.285.16:39:15.61#ibcon#flushed, iclass 37, count 2 2006.285.16:39:15.61#ibcon#about to write, iclass 37, count 2 2006.285.16:39:15.61#ibcon#wrote, iclass 37, count 2 2006.285.16:39:15.61#ibcon#about to read 3, iclass 37, count 2 2006.285.16:39:15.63#ibcon#read 3, iclass 37, count 2 2006.285.16:39:15.63#ibcon#about to read 4, iclass 37, count 2 2006.285.16:39:15.63#ibcon#read 4, iclass 37, count 2 2006.285.16:39:15.63#ibcon#about to read 5, iclass 37, count 2 2006.285.16:39:15.63#ibcon#read 5, iclass 37, count 2 2006.285.16:39:15.63#ibcon#about to read 6, iclass 37, count 2 2006.285.16:39:15.63#ibcon#read 6, iclass 37, count 2 2006.285.16:39:15.63#ibcon#end of sib2, iclass 37, count 2 2006.285.16:39:15.63#ibcon#*mode == 0, iclass 37, count 2 2006.285.16:39:15.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.16:39:15.63#ibcon#[25=AT03-07\r\n] 2006.285.16:39:15.63#ibcon#*before write, iclass 37, count 2 2006.285.16:39:15.63#ibcon#enter sib2, iclass 37, count 2 2006.285.16:39:15.63#ibcon#flushed, iclass 37, count 2 2006.285.16:39:15.63#ibcon#about to write, iclass 37, count 2 2006.285.16:39:15.63#ibcon#wrote, iclass 37, count 2 2006.285.16:39:15.63#ibcon#about to read 3, iclass 37, count 2 2006.285.16:39:15.66#ibcon#read 3, iclass 37, count 2 2006.285.16:39:16.04#ibcon#about to read 4, iclass 37, count 2 2006.285.16:39:16.04#ibcon#read 4, iclass 37, count 2 2006.285.16:39:16.04#ibcon#about to read 5, iclass 37, count 2 2006.285.16:39:16.04#ibcon#read 5, iclass 37, count 2 2006.285.16:39:16.04#ibcon#about to read 6, iclass 37, count 2 2006.285.16:39:16.04#ibcon#read 6, iclass 37, count 2 2006.285.16:39:16.04#ibcon#end of sib2, iclass 37, count 2 2006.285.16:39:16.04#ibcon#*after write, iclass 37, count 2 2006.285.16:39:16.04#ibcon#*before return 0, iclass 37, count 2 2006.285.16:39:16.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:39:16.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:39:16.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.16:39:16.04#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:16.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:39:16.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:39:16.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:39:16.15#ibcon#enter wrdev, iclass 37, count 0 2006.285.16:39:16.15#ibcon#first serial, iclass 37, count 0 2006.285.16:39:16.15#ibcon#enter sib2, iclass 37, count 0 2006.285.16:39:16.15#ibcon#flushed, iclass 37, count 0 2006.285.16:39:16.15#ibcon#about to write, iclass 37, count 0 2006.285.16:39:16.15#ibcon#wrote, iclass 37, count 0 2006.285.16:39:16.15#ibcon#about to read 3, iclass 37, count 0 2006.285.16:39:16.17#ibcon#read 3, iclass 37, count 0 2006.285.16:39:16.17#ibcon#about to read 4, iclass 37, count 0 2006.285.16:39:16.17#ibcon#read 4, iclass 37, count 0 2006.285.16:39:16.17#ibcon#about to read 5, iclass 37, count 0 2006.285.16:39:16.17#ibcon#read 5, iclass 37, count 0 2006.285.16:39:16.17#ibcon#about to read 6, iclass 37, count 0 2006.285.16:39:16.17#ibcon#read 6, iclass 37, count 0 2006.285.16:39:16.17#ibcon#end of sib2, iclass 37, count 0 2006.285.16:39:16.17#ibcon#*mode == 0, iclass 37, count 0 2006.285.16:39:16.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.16:39:16.17#ibcon#[25=USB\r\n] 2006.285.16:39:16.17#ibcon#*before write, iclass 37, count 0 2006.285.16:39:16.17#ibcon#enter sib2, iclass 37, count 0 2006.285.16:39:16.17#ibcon#flushed, iclass 37, count 0 2006.285.16:39:16.17#ibcon#about to write, iclass 37, count 0 2006.285.16:39:16.17#ibcon#wrote, iclass 37, count 0 2006.285.16:39:16.17#ibcon#about to read 3, iclass 37, count 0 2006.285.16:39:16.20#ibcon#read 3, iclass 37, count 0 2006.285.16:39:16.20#ibcon#about to read 4, iclass 37, count 0 2006.285.16:39:16.20#ibcon#read 4, iclass 37, count 0 2006.285.16:39:16.20#ibcon#about to read 5, iclass 37, count 0 2006.285.16:39:16.20#ibcon#read 5, iclass 37, count 0 2006.285.16:39:16.20#ibcon#about to read 6, iclass 37, count 0 2006.285.16:39:16.20#ibcon#read 6, iclass 37, count 0 2006.285.16:39:16.20#ibcon#end of sib2, iclass 37, count 0 2006.285.16:39:16.20#ibcon#*after write, iclass 37, count 0 2006.285.16:39:16.20#ibcon#*before return 0, iclass 37, count 0 2006.285.16:39:16.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:39:16.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:39:16.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.16:39:16.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.16:39:16.20$vck44/valo=4,624.99 2006.285.16:39:16.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.16:39:16.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.16:39:16.20#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:16.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:39:16.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:39:16.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:39:16.20#ibcon#enter wrdev, iclass 39, count 0 2006.285.16:39:16.20#ibcon#first serial, iclass 39, count 0 2006.285.16:39:16.20#ibcon#enter sib2, iclass 39, count 0 2006.285.16:39:16.20#ibcon#flushed, iclass 39, count 0 2006.285.16:39:16.20#ibcon#about to write, iclass 39, count 0 2006.285.16:39:16.20#ibcon#wrote, iclass 39, count 0 2006.285.16:39:16.20#ibcon#about to read 3, iclass 39, count 0 2006.285.16:39:16.22#ibcon#read 3, iclass 39, count 0 2006.285.16:39:16.22#ibcon#about to read 4, iclass 39, count 0 2006.285.16:39:16.22#ibcon#read 4, iclass 39, count 0 2006.285.16:39:16.22#ibcon#about to read 5, iclass 39, count 0 2006.285.16:39:16.22#ibcon#read 5, iclass 39, count 0 2006.285.16:39:16.22#ibcon#about to read 6, iclass 39, count 0 2006.285.16:39:16.22#ibcon#read 6, iclass 39, count 0 2006.285.16:39:16.22#ibcon#end of sib2, iclass 39, count 0 2006.285.16:39:16.22#ibcon#*mode == 0, iclass 39, count 0 2006.285.16:39:16.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.16:39:16.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.16:39:16.22#ibcon#*before write, iclass 39, count 0 2006.285.16:39:16.22#ibcon#enter sib2, iclass 39, count 0 2006.285.16:39:16.22#ibcon#flushed, iclass 39, count 0 2006.285.16:39:16.22#ibcon#about to write, iclass 39, count 0 2006.285.16:39:16.22#ibcon#wrote, iclass 39, count 0 2006.285.16:39:16.22#ibcon#about to read 3, iclass 39, count 0 2006.285.16:39:16.26#ibcon#read 3, iclass 39, count 0 2006.285.16:39:16.26#ibcon#about to read 4, iclass 39, count 0 2006.285.16:39:16.26#ibcon#read 4, iclass 39, count 0 2006.285.16:39:16.26#ibcon#about to read 5, iclass 39, count 0 2006.285.16:39:16.26#ibcon#read 5, iclass 39, count 0 2006.285.16:39:16.26#ibcon#about to read 6, iclass 39, count 0 2006.285.16:39:16.26#ibcon#read 6, iclass 39, count 0 2006.285.16:39:16.26#ibcon#end of sib2, iclass 39, count 0 2006.285.16:39:16.26#ibcon#*after write, iclass 39, count 0 2006.285.16:39:16.26#ibcon#*before return 0, iclass 39, count 0 2006.285.16:39:16.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:39:16.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:39:16.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.16:39:16.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.16:39:16.26$vck44/va=4,6 2006.285.16:39:16.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.16:39:16.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.16:39:16.26#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:16.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:39:16.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:39:16.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:39:16.32#ibcon#enter wrdev, iclass 3, count 2 2006.285.16:39:16.32#ibcon#first serial, iclass 3, count 2 2006.285.16:39:16.32#ibcon#enter sib2, iclass 3, count 2 2006.285.16:39:16.32#ibcon#flushed, iclass 3, count 2 2006.285.16:39:16.32#ibcon#about to write, iclass 3, count 2 2006.285.16:39:16.32#ibcon#wrote, iclass 3, count 2 2006.285.16:39:16.32#ibcon#about to read 3, iclass 3, count 2 2006.285.16:39:16.34#ibcon#read 3, iclass 3, count 2 2006.285.16:39:16.72#ibcon#about to read 4, iclass 3, count 2 2006.285.16:39:16.72#ibcon#read 4, iclass 3, count 2 2006.285.16:39:16.72#ibcon#about to read 5, iclass 3, count 2 2006.285.16:39:16.72#ibcon#read 5, iclass 3, count 2 2006.285.16:39:16.72#ibcon#about to read 6, iclass 3, count 2 2006.285.16:39:16.72#ibcon#read 6, iclass 3, count 2 2006.285.16:39:16.72#ibcon#end of sib2, iclass 3, count 2 2006.285.16:39:16.72#ibcon#*mode == 0, iclass 3, count 2 2006.285.16:39:16.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.16:39:16.72#ibcon#[25=AT04-06\r\n] 2006.285.16:39:16.72#ibcon#*before write, iclass 3, count 2 2006.285.16:39:16.72#ibcon#enter sib2, iclass 3, count 2 2006.285.16:39:16.72#ibcon#flushed, iclass 3, count 2 2006.285.16:39:16.72#ibcon#about to write, iclass 3, count 2 2006.285.16:39:16.72#ibcon#wrote, iclass 3, count 2 2006.285.16:39:16.72#ibcon#about to read 3, iclass 3, count 2 2006.285.16:39:16.75#ibcon#read 3, iclass 3, count 2 2006.285.16:39:16.75#ibcon#about to read 4, iclass 3, count 2 2006.285.16:39:16.75#ibcon#read 4, iclass 3, count 2 2006.285.16:39:16.75#ibcon#about to read 5, iclass 3, count 2 2006.285.16:39:16.75#ibcon#read 5, iclass 3, count 2 2006.285.16:39:16.75#ibcon#about to read 6, iclass 3, count 2 2006.285.16:39:16.75#ibcon#read 6, iclass 3, count 2 2006.285.16:39:16.75#ibcon#end of sib2, iclass 3, count 2 2006.285.16:39:16.75#ibcon#*after write, iclass 3, count 2 2006.285.16:39:16.75#ibcon#*before return 0, iclass 3, count 2 2006.285.16:39:16.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:39:16.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:39:16.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.16:39:16.75#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:16.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:39:16.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:39:16.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:39:16.87#ibcon#enter wrdev, iclass 3, count 0 2006.285.16:39:16.87#ibcon#first serial, iclass 3, count 0 2006.285.16:39:16.87#ibcon#enter sib2, iclass 3, count 0 2006.285.16:39:16.87#ibcon#flushed, iclass 3, count 0 2006.285.16:39:16.87#ibcon#about to write, iclass 3, count 0 2006.285.16:39:16.87#ibcon#wrote, iclass 3, count 0 2006.285.16:39:16.87#ibcon#about to read 3, iclass 3, count 0 2006.285.16:39:16.89#ibcon#read 3, iclass 3, count 0 2006.285.16:39:16.89#ibcon#about to read 4, iclass 3, count 0 2006.285.16:39:16.89#ibcon#read 4, iclass 3, count 0 2006.285.16:39:16.89#ibcon#about to read 5, iclass 3, count 0 2006.285.16:39:16.89#ibcon#read 5, iclass 3, count 0 2006.285.16:39:16.89#ibcon#about to read 6, iclass 3, count 0 2006.285.16:39:16.89#ibcon#read 6, iclass 3, count 0 2006.285.16:39:16.89#ibcon#end of sib2, iclass 3, count 0 2006.285.16:39:16.89#ibcon#*mode == 0, iclass 3, count 0 2006.285.16:39:16.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.16:39:16.89#ibcon#[25=USB\r\n] 2006.285.16:39:16.89#ibcon#*before write, iclass 3, count 0 2006.285.16:39:16.89#ibcon#enter sib2, iclass 3, count 0 2006.285.16:39:16.89#ibcon#flushed, iclass 3, count 0 2006.285.16:39:16.89#ibcon#about to write, iclass 3, count 0 2006.285.16:39:16.89#ibcon#wrote, iclass 3, count 0 2006.285.16:39:16.89#ibcon#about to read 3, iclass 3, count 0 2006.285.16:39:16.92#ibcon#read 3, iclass 3, count 0 2006.285.16:39:16.92#ibcon#about to read 4, iclass 3, count 0 2006.285.16:39:16.92#ibcon#read 4, iclass 3, count 0 2006.285.16:39:16.92#ibcon#about to read 5, iclass 3, count 0 2006.285.16:39:16.92#ibcon#read 5, iclass 3, count 0 2006.285.16:39:16.92#ibcon#about to read 6, iclass 3, count 0 2006.285.16:39:16.92#ibcon#read 6, iclass 3, count 0 2006.285.16:39:16.92#ibcon#end of sib2, iclass 3, count 0 2006.285.16:39:16.92#ibcon#*after write, iclass 3, count 0 2006.285.16:39:16.92#ibcon#*before return 0, iclass 3, count 0 2006.285.16:39:16.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:39:16.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:39:16.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.16:39:16.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.16:39:16.92$vck44/valo=5,734.99 2006.285.16:39:16.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.16:39:16.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.16:39:16.92#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:16.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:39:16.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:39:16.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:39:16.92#ibcon#enter wrdev, iclass 5, count 0 2006.285.16:39:16.92#ibcon#first serial, iclass 5, count 0 2006.285.16:39:16.92#ibcon#enter sib2, iclass 5, count 0 2006.285.16:39:16.92#ibcon#flushed, iclass 5, count 0 2006.285.16:39:16.92#ibcon#about to write, iclass 5, count 0 2006.285.16:39:16.92#ibcon#wrote, iclass 5, count 0 2006.285.16:39:16.92#ibcon#about to read 3, iclass 5, count 0 2006.285.16:39:16.94#ibcon#read 3, iclass 5, count 0 2006.285.16:39:16.94#ibcon#about to read 4, iclass 5, count 0 2006.285.16:39:16.94#ibcon#read 4, iclass 5, count 0 2006.285.16:39:16.94#ibcon#about to read 5, iclass 5, count 0 2006.285.16:39:16.94#ibcon#read 5, iclass 5, count 0 2006.285.16:39:16.94#ibcon#about to read 6, iclass 5, count 0 2006.285.16:39:16.94#ibcon#read 6, iclass 5, count 0 2006.285.16:39:16.94#ibcon#end of sib2, iclass 5, count 0 2006.285.16:39:16.94#ibcon#*mode == 0, iclass 5, count 0 2006.285.16:39:16.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.16:39:16.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.16:39:16.94#ibcon#*before write, iclass 5, count 0 2006.285.16:39:16.94#ibcon#enter sib2, iclass 5, count 0 2006.285.16:39:16.94#ibcon#flushed, iclass 5, count 0 2006.285.16:39:16.94#ibcon#about to write, iclass 5, count 0 2006.285.16:39:16.94#ibcon#wrote, iclass 5, count 0 2006.285.16:39:16.94#ibcon#about to read 3, iclass 5, count 0 2006.285.16:39:16.98#ibcon#read 3, iclass 5, count 0 2006.285.16:39:16.98#ibcon#about to read 4, iclass 5, count 0 2006.285.16:39:16.98#ibcon#read 4, iclass 5, count 0 2006.285.16:39:16.98#ibcon#about to read 5, iclass 5, count 0 2006.285.16:39:16.98#ibcon#read 5, iclass 5, count 0 2006.285.16:39:16.98#ibcon#about to read 6, iclass 5, count 0 2006.285.16:39:16.98#ibcon#read 6, iclass 5, count 0 2006.285.16:39:16.98#ibcon#end of sib2, iclass 5, count 0 2006.285.16:39:16.98#ibcon#*after write, iclass 5, count 0 2006.285.16:39:16.98#ibcon#*before return 0, iclass 5, count 0 2006.285.16:39:16.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:39:16.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:39:16.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.16:39:16.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.16:39:16.98$vck44/va=5,3 2006.285.16:39:16.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.16:39:16.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.16:39:16.98#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:16.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:39:17.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:39:17.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:39:17.04#ibcon#enter wrdev, iclass 7, count 2 2006.285.16:39:17.04#ibcon#first serial, iclass 7, count 2 2006.285.16:39:17.04#ibcon#enter sib2, iclass 7, count 2 2006.285.16:39:17.04#ibcon#flushed, iclass 7, count 2 2006.285.16:39:17.04#ibcon#about to write, iclass 7, count 2 2006.285.16:39:17.04#ibcon#wrote, iclass 7, count 2 2006.285.16:39:17.04#ibcon#about to read 3, iclass 7, count 2 2006.285.16:39:17.06#ibcon#read 3, iclass 7, count 2 2006.285.16:39:17.06#ibcon#about to read 4, iclass 7, count 2 2006.285.16:39:17.06#ibcon#read 4, iclass 7, count 2 2006.285.16:39:17.06#ibcon#about to read 5, iclass 7, count 2 2006.285.16:39:17.06#ibcon#read 5, iclass 7, count 2 2006.285.16:39:17.06#ibcon#about to read 6, iclass 7, count 2 2006.285.16:39:17.06#ibcon#read 6, iclass 7, count 2 2006.285.16:39:17.06#ibcon#end of sib2, iclass 7, count 2 2006.285.16:39:17.06#ibcon#*mode == 0, iclass 7, count 2 2006.285.16:39:17.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.16:39:17.06#ibcon#[25=AT05-03\r\n] 2006.285.16:39:17.06#ibcon#*before write, iclass 7, count 2 2006.285.16:39:17.06#ibcon#enter sib2, iclass 7, count 2 2006.285.16:39:17.06#ibcon#flushed, iclass 7, count 2 2006.285.16:39:17.06#ibcon#about to write, iclass 7, count 2 2006.285.16:39:17.06#ibcon#wrote, iclass 7, count 2 2006.285.16:39:17.06#ibcon#about to read 3, iclass 7, count 2 2006.285.16:39:17.09#ibcon#read 3, iclass 7, count 2 2006.285.16:39:17.09#ibcon#about to read 4, iclass 7, count 2 2006.285.16:39:17.09#ibcon#read 4, iclass 7, count 2 2006.285.16:39:17.09#ibcon#about to read 5, iclass 7, count 2 2006.285.16:39:17.09#ibcon#read 5, iclass 7, count 2 2006.285.16:39:17.09#ibcon#about to read 6, iclass 7, count 2 2006.285.16:39:17.09#ibcon#read 6, iclass 7, count 2 2006.285.16:39:17.09#ibcon#end of sib2, iclass 7, count 2 2006.285.16:39:17.09#ibcon#*after write, iclass 7, count 2 2006.285.16:39:17.09#ibcon#*before return 0, iclass 7, count 2 2006.285.16:39:17.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:39:17.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:39:17.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.16:39:17.09#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:17.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:39:17.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:39:17.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:39:17.21#ibcon#enter wrdev, iclass 7, count 0 2006.285.16:39:17.21#ibcon#first serial, iclass 7, count 0 2006.285.16:39:17.21#ibcon#enter sib2, iclass 7, count 0 2006.285.16:39:17.21#ibcon#flushed, iclass 7, count 0 2006.285.16:39:17.21#ibcon#about to write, iclass 7, count 0 2006.285.16:39:17.21#ibcon#wrote, iclass 7, count 0 2006.285.16:39:17.21#ibcon#about to read 3, iclass 7, count 0 2006.285.16:39:17.23#ibcon#read 3, iclass 7, count 0 2006.285.16:39:17.23#ibcon#about to read 4, iclass 7, count 0 2006.285.16:39:17.23#ibcon#read 4, iclass 7, count 0 2006.285.16:39:17.23#ibcon#about to read 5, iclass 7, count 0 2006.285.16:39:17.23#ibcon#read 5, iclass 7, count 0 2006.285.16:39:17.23#ibcon#about to read 6, iclass 7, count 0 2006.285.16:39:17.23#ibcon#read 6, iclass 7, count 0 2006.285.16:39:17.23#ibcon#end of sib2, iclass 7, count 0 2006.285.16:39:17.23#ibcon#*mode == 0, iclass 7, count 0 2006.285.16:39:17.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.16:39:17.23#ibcon#[25=USB\r\n] 2006.285.16:39:17.23#ibcon#*before write, iclass 7, count 0 2006.285.16:39:17.23#ibcon#enter sib2, iclass 7, count 0 2006.285.16:39:17.23#ibcon#flushed, iclass 7, count 0 2006.285.16:39:17.23#ibcon#about to write, iclass 7, count 0 2006.285.16:39:17.23#ibcon#wrote, iclass 7, count 0 2006.285.16:39:17.23#ibcon#about to read 3, iclass 7, count 0 2006.285.16:39:17.26#ibcon#read 3, iclass 7, count 0 2006.285.16:39:17.26#ibcon#about to read 4, iclass 7, count 0 2006.285.16:39:17.26#ibcon#read 4, iclass 7, count 0 2006.285.16:39:17.26#ibcon#about to read 5, iclass 7, count 0 2006.285.16:39:17.26#ibcon#read 5, iclass 7, count 0 2006.285.16:39:17.26#ibcon#about to read 6, iclass 7, count 0 2006.285.16:39:17.26#ibcon#read 6, iclass 7, count 0 2006.285.16:39:17.26#ibcon#end of sib2, iclass 7, count 0 2006.285.16:39:17.26#ibcon#*after write, iclass 7, count 0 2006.285.16:39:17.26#ibcon#*before return 0, iclass 7, count 0 2006.285.16:39:17.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:39:17.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:39:17.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.16:39:17.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.16:39:17.26$vck44/valo=6,814.99 2006.285.16:39:17.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.16:39:17.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.16:39:17.26#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:17.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:39:17.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:39:17.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:39:17.26#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:39:17.26#ibcon#first serial, iclass 11, count 0 2006.285.16:39:17.26#ibcon#enter sib2, iclass 11, count 0 2006.285.16:39:17.26#ibcon#flushed, iclass 11, count 0 2006.285.16:39:17.26#ibcon#about to write, iclass 11, count 0 2006.285.16:39:17.26#ibcon#wrote, iclass 11, count 0 2006.285.16:39:17.26#ibcon#about to read 3, iclass 11, count 0 2006.285.16:39:17.28#ibcon#read 3, iclass 11, count 0 2006.285.16:39:17.28#ibcon#about to read 4, iclass 11, count 0 2006.285.16:39:17.28#ibcon#read 4, iclass 11, count 0 2006.285.16:39:17.28#ibcon#about to read 5, iclass 11, count 0 2006.285.16:39:17.28#ibcon#read 5, iclass 11, count 0 2006.285.16:39:17.28#ibcon#about to read 6, iclass 11, count 0 2006.285.16:39:17.28#ibcon#read 6, iclass 11, count 0 2006.285.16:39:17.28#ibcon#end of sib2, iclass 11, count 0 2006.285.16:39:17.28#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:39:17.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:39:17.28#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.16:39:17.28#ibcon#*before write, iclass 11, count 0 2006.285.16:39:17.28#ibcon#enter sib2, iclass 11, count 0 2006.285.16:39:17.28#ibcon#flushed, iclass 11, count 0 2006.285.16:39:17.28#ibcon#about to write, iclass 11, count 0 2006.285.16:39:17.28#ibcon#wrote, iclass 11, count 0 2006.285.16:39:17.28#ibcon#about to read 3, iclass 11, count 0 2006.285.16:39:17.32#ibcon#read 3, iclass 11, count 0 2006.285.16:39:17.32#ibcon#about to read 4, iclass 11, count 0 2006.285.16:39:17.32#ibcon#read 4, iclass 11, count 0 2006.285.16:39:17.32#ibcon#about to read 5, iclass 11, count 0 2006.285.16:39:17.32#ibcon#read 5, iclass 11, count 0 2006.285.16:39:17.32#ibcon#about to read 6, iclass 11, count 0 2006.285.16:39:17.32#ibcon#read 6, iclass 11, count 0 2006.285.16:39:17.32#ibcon#end of sib2, iclass 11, count 0 2006.285.16:39:17.32#ibcon#*after write, iclass 11, count 0 2006.285.16:39:17.32#ibcon#*before return 0, iclass 11, count 0 2006.285.16:39:17.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:39:17.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:39:17.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:39:17.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:39:17.32$vck44/va=6,4 2006.285.16:39:17.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.16:39:17.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.16:39:17.32#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:17.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:39:17.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:39:17.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:39:17.38#ibcon#enter wrdev, iclass 13, count 2 2006.285.16:39:17.38#ibcon#first serial, iclass 13, count 2 2006.285.16:39:17.38#ibcon#enter sib2, iclass 13, count 2 2006.285.16:39:17.38#ibcon#flushed, iclass 13, count 2 2006.285.16:39:17.38#ibcon#about to write, iclass 13, count 2 2006.285.16:39:17.38#ibcon#wrote, iclass 13, count 2 2006.285.16:39:17.38#ibcon#about to read 3, iclass 13, count 2 2006.285.16:39:17.40#ibcon#read 3, iclass 13, count 2 2006.285.16:39:17.40#ibcon#about to read 4, iclass 13, count 2 2006.285.16:39:17.40#ibcon#read 4, iclass 13, count 2 2006.285.16:39:17.40#ibcon#about to read 5, iclass 13, count 2 2006.285.16:39:17.40#ibcon#read 5, iclass 13, count 2 2006.285.16:39:17.40#ibcon#about to read 6, iclass 13, count 2 2006.285.16:39:17.40#ibcon#read 6, iclass 13, count 2 2006.285.16:39:17.40#ibcon#end of sib2, iclass 13, count 2 2006.285.16:39:17.40#ibcon#*mode == 0, iclass 13, count 2 2006.285.16:39:17.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.16:39:17.40#ibcon#[25=AT06-04\r\n] 2006.285.16:39:17.40#ibcon#*before write, iclass 13, count 2 2006.285.16:39:17.40#ibcon#enter sib2, iclass 13, count 2 2006.285.16:39:17.40#ibcon#flushed, iclass 13, count 2 2006.285.16:39:17.40#ibcon#about to write, iclass 13, count 2 2006.285.16:39:17.40#ibcon#wrote, iclass 13, count 2 2006.285.16:39:17.40#ibcon#about to read 3, iclass 13, count 2 2006.285.16:39:17.43#ibcon#read 3, iclass 13, count 2 2006.285.16:39:17.43#ibcon#about to read 4, iclass 13, count 2 2006.285.16:39:17.43#ibcon#read 4, iclass 13, count 2 2006.285.16:39:17.43#ibcon#about to read 5, iclass 13, count 2 2006.285.16:39:17.43#ibcon#read 5, iclass 13, count 2 2006.285.16:39:17.43#ibcon#about to read 6, iclass 13, count 2 2006.285.16:39:17.43#ibcon#read 6, iclass 13, count 2 2006.285.16:39:17.43#ibcon#end of sib2, iclass 13, count 2 2006.285.16:39:17.43#ibcon#*after write, iclass 13, count 2 2006.285.16:39:17.43#ibcon#*before return 0, iclass 13, count 2 2006.285.16:39:17.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:39:17.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:39:17.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.16:39:17.43#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:17.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:39:17.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:39:17.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:39:17.55#ibcon#enter wrdev, iclass 13, count 0 2006.285.16:39:17.55#ibcon#first serial, iclass 13, count 0 2006.285.16:39:17.55#ibcon#enter sib2, iclass 13, count 0 2006.285.16:39:17.55#ibcon#flushed, iclass 13, count 0 2006.285.16:39:17.55#ibcon#about to write, iclass 13, count 0 2006.285.16:39:17.55#ibcon#wrote, iclass 13, count 0 2006.285.16:39:17.55#ibcon#about to read 3, iclass 13, count 0 2006.285.16:39:17.57#ibcon#read 3, iclass 13, count 0 2006.285.16:39:17.57#ibcon#about to read 4, iclass 13, count 0 2006.285.16:39:17.57#ibcon#read 4, iclass 13, count 0 2006.285.16:39:17.57#ibcon#about to read 5, iclass 13, count 0 2006.285.16:39:17.57#ibcon#read 5, iclass 13, count 0 2006.285.16:39:17.57#ibcon#about to read 6, iclass 13, count 0 2006.285.16:39:17.57#ibcon#read 6, iclass 13, count 0 2006.285.16:39:17.57#ibcon#end of sib2, iclass 13, count 0 2006.285.16:39:17.57#ibcon#*mode == 0, iclass 13, count 0 2006.285.16:39:17.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.16:39:17.57#ibcon#[25=USB\r\n] 2006.285.16:39:17.57#ibcon#*before write, iclass 13, count 0 2006.285.16:39:17.57#ibcon#enter sib2, iclass 13, count 0 2006.285.16:39:17.57#ibcon#flushed, iclass 13, count 0 2006.285.16:39:17.57#ibcon#about to write, iclass 13, count 0 2006.285.16:39:17.57#ibcon#wrote, iclass 13, count 0 2006.285.16:39:17.57#ibcon#about to read 3, iclass 13, count 0 2006.285.16:39:17.60#ibcon#read 3, iclass 13, count 0 2006.285.16:39:17.60#ibcon#about to read 4, iclass 13, count 0 2006.285.16:39:17.60#ibcon#read 4, iclass 13, count 0 2006.285.16:39:17.60#ibcon#about to read 5, iclass 13, count 0 2006.285.16:39:17.60#ibcon#read 5, iclass 13, count 0 2006.285.16:39:17.60#ibcon#about to read 6, iclass 13, count 0 2006.285.16:39:17.60#ibcon#read 6, iclass 13, count 0 2006.285.16:39:17.60#ibcon#end of sib2, iclass 13, count 0 2006.285.16:39:17.60#ibcon#*after write, iclass 13, count 0 2006.285.16:39:17.60#ibcon#*before return 0, iclass 13, count 0 2006.285.16:39:17.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:39:17.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:39:17.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.16:39:17.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.16:39:17.60$vck44/valo=7,864.99 2006.285.16:39:17.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.16:39:17.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.16:39:17.60#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:17.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:39:17.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:39:17.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:39:17.60#ibcon#enter wrdev, iclass 15, count 0 2006.285.16:39:17.60#ibcon#first serial, iclass 15, count 0 2006.285.16:39:17.60#ibcon#enter sib2, iclass 15, count 0 2006.285.16:39:17.60#ibcon#flushed, iclass 15, count 0 2006.285.16:39:17.60#ibcon#about to write, iclass 15, count 0 2006.285.16:39:17.60#ibcon#wrote, iclass 15, count 0 2006.285.16:39:17.60#ibcon#about to read 3, iclass 15, count 0 2006.285.16:39:17.62#ibcon#read 3, iclass 15, count 0 2006.285.16:39:17.62#ibcon#about to read 4, iclass 15, count 0 2006.285.16:39:17.62#ibcon#read 4, iclass 15, count 0 2006.285.16:39:17.71#ibcon#about to read 5, iclass 15, count 0 2006.285.16:39:17.71#ibcon#read 5, iclass 15, count 0 2006.285.16:39:17.71#ibcon#about to read 6, iclass 15, count 0 2006.285.16:39:17.71#ibcon#read 6, iclass 15, count 0 2006.285.16:39:17.71#ibcon#end of sib2, iclass 15, count 0 2006.285.16:39:17.71#ibcon#*mode == 0, iclass 15, count 0 2006.285.16:39:17.71#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.16:39:17.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.16:39:17.71#ibcon#*before write, iclass 15, count 0 2006.285.16:39:17.71#ibcon#enter sib2, iclass 15, count 0 2006.285.16:39:17.71#ibcon#flushed, iclass 15, count 0 2006.285.16:39:17.71#ibcon#about to write, iclass 15, count 0 2006.285.16:39:17.71#ibcon#wrote, iclass 15, count 0 2006.285.16:39:17.71#ibcon#about to read 3, iclass 15, count 0 2006.285.16:39:17.75#ibcon#read 3, iclass 15, count 0 2006.285.16:39:17.75#ibcon#about to read 4, iclass 15, count 0 2006.285.16:39:17.75#ibcon#read 4, iclass 15, count 0 2006.285.16:39:17.75#ibcon#about to read 5, iclass 15, count 0 2006.285.16:39:17.75#ibcon#read 5, iclass 15, count 0 2006.285.16:39:17.75#ibcon#about to read 6, iclass 15, count 0 2006.285.16:39:17.75#ibcon#read 6, iclass 15, count 0 2006.285.16:39:17.75#ibcon#end of sib2, iclass 15, count 0 2006.285.16:39:17.75#ibcon#*after write, iclass 15, count 0 2006.285.16:39:17.75#ibcon#*before return 0, iclass 15, count 0 2006.285.16:39:17.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:39:17.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:39:17.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.16:39:17.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.16:39:17.75$vck44/va=7,4 2006.285.16:39:17.75#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.16:39:17.75#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.16:39:17.75#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:17.75#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:39:17.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:39:17.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:39:17.75#ibcon#enter wrdev, iclass 18, count 2 2006.285.16:39:17.75#ibcon#first serial, iclass 18, count 2 2006.285.16:39:17.75#ibcon#enter sib2, iclass 18, count 2 2006.285.16:39:17.75#ibcon#flushed, iclass 18, count 2 2006.285.16:39:17.75#ibcon#about to write, iclass 18, count 2 2006.285.16:39:17.75#ibcon#wrote, iclass 18, count 2 2006.285.16:39:17.75#ibcon#about to read 3, iclass 18, count 2 2006.285.16:39:17.77#ibcon#read 3, iclass 18, count 2 2006.285.16:39:17.77#ibcon#about to read 4, iclass 18, count 2 2006.285.16:39:17.77#ibcon#read 4, iclass 18, count 2 2006.285.16:39:17.77#ibcon#about to read 5, iclass 18, count 2 2006.285.16:39:17.77#ibcon#read 5, iclass 18, count 2 2006.285.16:39:17.77#ibcon#about to read 6, iclass 18, count 2 2006.285.16:39:17.77#ibcon#read 6, iclass 18, count 2 2006.285.16:39:17.77#ibcon#end of sib2, iclass 18, count 2 2006.285.16:39:17.77#ibcon#*mode == 0, iclass 18, count 2 2006.285.16:39:17.77#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.16:39:17.77#ibcon#[25=AT07-04\r\n] 2006.285.16:39:17.77#ibcon#*before write, iclass 18, count 2 2006.285.16:39:17.77#ibcon#enter sib2, iclass 18, count 2 2006.285.16:39:17.77#ibcon#flushed, iclass 18, count 2 2006.285.16:39:17.77#ibcon#about to write, iclass 18, count 2 2006.285.16:39:17.77#ibcon#wrote, iclass 18, count 2 2006.285.16:39:17.77#ibcon#about to read 3, iclass 18, count 2 2006.285.16:39:17.79#abcon#<5=/15 0.8 1.8 18.39 921015.0\r\n> 2006.285.16:39:17.80#ibcon#read 3, iclass 18, count 2 2006.285.16:39:17.80#ibcon#about to read 4, iclass 18, count 2 2006.285.16:39:17.80#ibcon#read 4, iclass 18, count 2 2006.285.16:39:17.80#ibcon#about to read 5, iclass 18, count 2 2006.285.16:39:17.80#ibcon#read 5, iclass 18, count 2 2006.285.16:39:17.80#ibcon#about to read 6, iclass 18, count 2 2006.285.16:39:17.80#ibcon#read 6, iclass 18, count 2 2006.285.16:39:17.80#ibcon#end of sib2, iclass 18, count 2 2006.285.16:39:17.80#ibcon#*after write, iclass 18, count 2 2006.285.16:39:17.80#ibcon#*before return 0, iclass 18, count 2 2006.285.16:39:17.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:39:17.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:39:17.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.16:39:17.80#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:17.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:39:17.81#abcon#{5=INTERFACE CLEAR} 2006.285.16:39:17.87#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:39:17.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:39:17.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:39:17.92#ibcon#enter wrdev, iclass 18, count 0 2006.285.16:39:17.92#ibcon#first serial, iclass 18, count 0 2006.285.16:39:17.92#ibcon#enter sib2, iclass 18, count 0 2006.285.16:39:17.92#ibcon#flushed, iclass 18, count 0 2006.285.16:39:17.92#ibcon#about to write, iclass 18, count 0 2006.285.16:39:17.92#ibcon#wrote, iclass 18, count 0 2006.285.16:39:17.92#ibcon#about to read 3, iclass 18, count 0 2006.285.16:39:17.94#ibcon#read 3, iclass 18, count 0 2006.285.16:39:17.94#ibcon#about to read 4, iclass 18, count 0 2006.285.16:39:17.94#ibcon#read 4, iclass 18, count 0 2006.285.16:39:17.94#ibcon#about to read 5, iclass 18, count 0 2006.285.16:39:17.94#ibcon#read 5, iclass 18, count 0 2006.285.16:39:17.94#ibcon#about to read 6, iclass 18, count 0 2006.285.16:39:17.94#ibcon#read 6, iclass 18, count 0 2006.285.16:39:17.94#ibcon#end of sib2, iclass 18, count 0 2006.285.16:39:17.94#ibcon#*mode == 0, iclass 18, count 0 2006.285.16:39:17.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.16:39:17.94#ibcon#[25=USB\r\n] 2006.285.16:39:17.94#ibcon#*before write, iclass 18, count 0 2006.285.16:39:17.94#ibcon#enter sib2, iclass 18, count 0 2006.285.16:39:17.94#ibcon#flushed, iclass 18, count 0 2006.285.16:39:17.94#ibcon#about to write, iclass 18, count 0 2006.285.16:39:17.94#ibcon#wrote, iclass 18, count 0 2006.285.16:39:17.94#ibcon#about to read 3, iclass 18, count 0 2006.285.16:39:17.97#ibcon#read 3, iclass 18, count 0 2006.285.16:39:17.97#ibcon#about to read 4, iclass 18, count 0 2006.285.16:39:17.97#ibcon#read 4, iclass 18, count 0 2006.285.16:39:17.97#ibcon#about to read 5, iclass 18, count 0 2006.285.16:39:17.97#ibcon#read 5, iclass 18, count 0 2006.285.16:39:17.97#ibcon#about to read 6, iclass 18, count 0 2006.285.16:39:17.97#ibcon#read 6, iclass 18, count 0 2006.285.16:39:17.97#ibcon#end of sib2, iclass 18, count 0 2006.285.16:39:17.97#ibcon#*after write, iclass 18, count 0 2006.285.16:39:17.97#ibcon#*before return 0, iclass 18, count 0 2006.285.16:39:17.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:39:17.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:39:17.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.16:39:17.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.16:39:17.97$vck44/valo=8,884.99 2006.285.16:39:17.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.16:39:17.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.16:39:17.97#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:17.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:39:17.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:39:17.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:39:17.97#ibcon#enter wrdev, iclass 23, count 0 2006.285.16:39:17.97#ibcon#first serial, iclass 23, count 0 2006.285.16:39:17.97#ibcon#enter sib2, iclass 23, count 0 2006.285.16:39:17.97#ibcon#flushed, iclass 23, count 0 2006.285.16:39:17.97#ibcon#about to write, iclass 23, count 0 2006.285.16:39:17.97#ibcon#wrote, iclass 23, count 0 2006.285.16:39:17.97#ibcon#about to read 3, iclass 23, count 0 2006.285.16:39:17.99#ibcon#read 3, iclass 23, count 0 2006.285.16:39:17.99#ibcon#about to read 4, iclass 23, count 0 2006.285.16:39:17.99#ibcon#read 4, iclass 23, count 0 2006.285.16:39:17.99#ibcon#about to read 5, iclass 23, count 0 2006.285.16:39:17.99#ibcon#read 5, iclass 23, count 0 2006.285.16:39:17.99#ibcon#about to read 6, iclass 23, count 0 2006.285.16:39:17.99#ibcon#read 6, iclass 23, count 0 2006.285.16:39:17.99#ibcon#end of sib2, iclass 23, count 0 2006.285.16:39:17.99#ibcon#*mode == 0, iclass 23, count 0 2006.285.16:39:17.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.16:39:17.99#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.16:39:17.99#ibcon#*before write, iclass 23, count 0 2006.285.16:39:17.99#ibcon#enter sib2, iclass 23, count 0 2006.285.16:39:17.99#ibcon#flushed, iclass 23, count 0 2006.285.16:39:17.99#ibcon#about to write, iclass 23, count 0 2006.285.16:39:17.99#ibcon#wrote, iclass 23, count 0 2006.285.16:39:17.99#ibcon#about to read 3, iclass 23, count 0 2006.285.16:39:18.03#ibcon#read 3, iclass 23, count 0 2006.285.16:39:18.03#ibcon#about to read 4, iclass 23, count 0 2006.285.16:39:18.03#ibcon#read 4, iclass 23, count 0 2006.285.16:39:18.03#ibcon#about to read 5, iclass 23, count 0 2006.285.16:39:18.03#ibcon#read 5, iclass 23, count 0 2006.285.16:39:18.03#ibcon#about to read 6, iclass 23, count 0 2006.285.16:39:18.03#ibcon#read 6, iclass 23, count 0 2006.285.16:39:18.03#ibcon#end of sib2, iclass 23, count 0 2006.285.16:39:18.03#ibcon#*after write, iclass 23, count 0 2006.285.16:39:18.03#ibcon#*before return 0, iclass 23, count 0 2006.285.16:39:18.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:39:18.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:39:18.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.16:39:18.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.16:39:18.03$vck44/va=8,3 2006.285.16:39:18.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.16:39:18.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.16:39:18.03#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:18.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:39:18.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:39:18.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:39:18.09#ibcon#enter wrdev, iclass 25, count 2 2006.285.16:39:18.09#ibcon#first serial, iclass 25, count 2 2006.285.16:39:18.09#ibcon#enter sib2, iclass 25, count 2 2006.285.16:39:18.09#ibcon#flushed, iclass 25, count 2 2006.285.16:39:18.09#ibcon#about to write, iclass 25, count 2 2006.285.16:39:18.09#ibcon#wrote, iclass 25, count 2 2006.285.16:39:18.09#ibcon#about to read 3, iclass 25, count 2 2006.285.16:39:18.11#ibcon#read 3, iclass 25, count 2 2006.285.16:39:18.11#ibcon#about to read 4, iclass 25, count 2 2006.285.16:39:18.11#ibcon#read 4, iclass 25, count 2 2006.285.16:39:18.11#ibcon#about to read 5, iclass 25, count 2 2006.285.16:39:18.11#ibcon#read 5, iclass 25, count 2 2006.285.16:39:18.11#ibcon#about to read 6, iclass 25, count 2 2006.285.16:39:18.11#ibcon#read 6, iclass 25, count 2 2006.285.16:39:18.11#ibcon#end of sib2, iclass 25, count 2 2006.285.16:39:18.11#ibcon#*mode == 0, iclass 25, count 2 2006.285.16:39:18.11#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.16:39:18.11#ibcon#[25=AT08-03\r\n] 2006.285.16:39:18.11#ibcon#*before write, iclass 25, count 2 2006.285.16:39:18.11#ibcon#enter sib2, iclass 25, count 2 2006.285.16:39:18.11#ibcon#flushed, iclass 25, count 2 2006.285.16:39:18.11#ibcon#about to write, iclass 25, count 2 2006.285.16:39:18.11#ibcon#wrote, iclass 25, count 2 2006.285.16:39:18.11#ibcon#about to read 3, iclass 25, count 2 2006.285.16:39:18.14#ibcon#read 3, iclass 25, count 2 2006.285.16:39:18.14#ibcon#about to read 4, iclass 25, count 2 2006.285.16:39:18.14#ibcon#read 4, iclass 25, count 2 2006.285.16:39:18.14#ibcon#about to read 5, iclass 25, count 2 2006.285.16:39:18.14#ibcon#read 5, iclass 25, count 2 2006.285.16:39:18.14#ibcon#about to read 6, iclass 25, count 2 2006.285.16:39:18.14#ibcon#read 6, iclass 25, count 2 2006.285.16:39:18.14#ibcon#end of sib2, iclass 25, count 2 2006.285.16:39:18.14#ibcon#*after write, iclass 25, count 2 2006.285.16:39:18.14#ibcon#*before return 0, iclass 25, count 2 2006.285.16:39:18.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:39:18.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:39:18.14#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.16:39:18.14#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:18.14#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:39:18.26#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:39:18.26#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:39:18.26#ibcon#enter wrdev, iclass 25, count 0 2006.285.16:39:18.26#ibcon#first serial, iclass 25, count 0 2006.285.16:39:18.26#ibcon#enter sib2, iclass 25, count 0 2006.285.16:39:18.26#ibcon#flushed, iclass 25, count 0 2006.285.16:39:18.26#ibcon#about to write, iclass 25, count 0 2006.285.16:39:18.26#ibcon#wrote, iclass 25, count 0 2006.285.16:39:18.26#ibcon#about to read 3, iclass 25, count 0 2006.285.16:39:18.28#ibcon#read 3, iclass 25, count 0 2006.285.16:39:18.28#ibcon#about to read 4, iclass 25, count 0 2006.285.16:39:18.28#ibcon#read 4, iclass 25, count 0 2006.285.16:39:18.28#ibcon#about to read 5, iclass 25, count 0 2006.285.16:39:18.28#ibcon#read 5, iclass 25, count 0 2006.285.16:39:18.28#ibcon#about to read 6, iclass 25, count 0 2006.285.16:39:18.28#ibcon#read 6, iclass 25, count 0 2006.285.16:39:18.28#ibcon#end of sib2, iclass 25, count 0 2006.285.16:39:18.28#ibcon#*mode == 0, iclass 25, count 0 2006.285.16:39:18.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.16:39:18.28#ibcon#[25=USB\r\n] 2006.285.16:39:18.28#ibcon#*before write, iclass 25, count 0 2006.285.16:39:18.28#ibcon#enter sib2, iclass 25, count 0 2006.285.16:39:18.28#ibcon#flushed, iclass 25, count 0 2006.285.16:39:18.28#ibcon#about to write, iclass 25, count 0 2006.285.16:39:18.28#ibcon#wrote, iclass 25, count 0 2006.285.16:39:18.28#ibcon#about to read 3, iclass 25, count 0 2006.285.16:39:18.31#ibcon#read 3, iclass 25, count 0 2006.285.16:39:18.31#ibcon#about to read 4, iclass 25, count 0 2006.285.16:39:18.31#ibcon#read 4, iclass 25, count 0 2006.285.16:39:18.31#ibcon#about to read 5, iclass 25, count 0 2006.285.16:39:18.31#ibcon#read 5, iclass 25, count 0 2006.285.16:39:18.31#ibcon#about to read 6, iclass 25, count 0 2006.285.16:39:18.31#ibcon#read 6, iclass 25, count 0 2006.285.16:39:18.31#ibcon#end of sib2, iclass 25, count 0 2006.285.16:39:18.31#ibcon#*after write, iclass 25, count 0 2006.285.16:39:18.31#ibcon#*before return 0, iclass 25, count 0 2006.285.16:39:18.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:39:18.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:39:18.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.16:39:18.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.16:39:18.31$vck44/vblo=1,629.99 2006.285.16:39:18.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.16:39:18.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.16:39:18.31#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:18.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:39:18.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:39:18.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:39:18.31#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:39:18.31#ibcon#first serial, iclass 27, count 0 2006.285.16:39:18.31#ibcon#enter sib2, iclass 27, count 0 2006.285.16:39:18.31#ibcon#flushed, iclass 27, count 0 2006.285.16:39:18.31#ibcon#about to write, iclass 27, count 0 2006.285.16:39:18.31#ibcon#wrote, iclass 27, count 0 2006.285.16:39:18.31#ibcon#about to read 3, iclass 27, count 0 2006.285.16:39:18.33#ibcon#read 3, iclass 27, count 0 2006.285.16:39:18.33#ibcon#about to read 4, iclass 27, count 0 2006.285.16:39:18.33#ibcon#read 4, iclass 27, count 0 2006.285.16:39:18.33#ibcon#about to read 5, iclass 27, count 0 2006.285.16:39:18.33#ibcon#read 5, iclass 27, count 0 2006.285.16:39:18.33#ibcon#about to read 6, iclass 27, count 0 2006.285.16:39:18.33#ibcon#read 6, iclass 27, count 0 2006.285.16:39:18.33#ibcon#end of sib2, iclass 27, count 0 2006.285.16:39:18.33#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:39:18.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:39:18.33#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.16:39:18.33#ibcon#*before write, iclass 27, count 0 2006.285.16:39:18.33#ibcon#enter sib2, iclass 27, count 0 2006.285.16:39:18.33#ibcon#flushed, iclass 27, count 0 2006.285.16:39:18.33#ibcon#about to write, iclass 27, count 0 2006.285.16:39:18.33#ibcon#wrote, iclass 27, count 0 2006.285.16:39:18.33#ibcon#about to read 3, iclass 27, count 0 2006.285.16:39:18.37#ibcon#read 3, iclass 27, count 0 2006.285.16:39:18.37#ibcon#about to read 4, iclass 27, count 0 2006.285.16:39:18.37#ibcon#read 4, iclass 27, count 0 2006.285.16:39:18.37#ibcon#about to read 5, iclass 27, count 0 2006.285.16:39:18.37#ibcon#read 5, iclass 27, count 0 2006.285.16:39:18.37#ibcon#about to read 6, iclass 27, count 0 2006.285.16:39:18.37#ibcon#read 6, iclass 27, count 0 2006.285.16:39:18.37#ibcon#end of sib2, iclass 27, count 0 2006.285.16:39:18.37#ibcon#*after write, iclass 27, count 0 2006.285.16:39:18.37#ibcon#*before return 0, iclass 27, count 0 2006.285.16:39:18.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:39:18.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:39:18.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:39:18.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:39:18.37$vck44/vb=1,4 2006.285.16:39:18.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.16:39:18.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.16:39:18.37#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:18.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:39:18.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:39:18.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:39:18.37#ibcon#enter wrdev, iclass 29, count 2 2006.285.16:39:18.37#ibcon#first serial, iclass 29, count 2 2006.285.16:39:18.37#ibcon#enter sib2, iclass 29, count 2 2006.285.16:39:18.37#ibcon#flushed, iclass 29, count 2 2006.285.16:39:18.37#ibcon#about to write, iclass 29, count 2 2006.285.16:39:18.37#ibcon#wrote, iclass 29, count 2 2006.285.16:39:18.37#ibcon#about to read 3, iclass 29, count 2 2006.285.16:39:18.39#ibcon#read 3, iclass 29, count 2 2006.285.16:39:18.39#ibcon#about to read 4, iclass 29, count 2 2006.285.16:39:18.39#ibcon#read 4, iclass 29, count 2 2006.285.16:39:18.39#ibcon#about to read 5, iclass 29, count 2 2006.285.16:39:18.39#ibcon#read 5, iclass 29, count 2 2006.285.16:39:18.39#ibcon#about to read 6, iclass 29, count 2 2006.285.16:39:18.39#ibcon#read 6, iclass 29, count 2 2006.285.16:39:18.39#ibcon#end of sib2, iclass 29, count 2 2006.285.16:39:18.39#ibcon#*mode == 0, iclass 29, count 2 2006.285.16:39:18.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.16:39:18.39#ibcon#[27=AT01-04\r\n] 2006.285.16:39:18.39#ibcon#*before write, iclass 29, count 2 2006.285.16:39:18.39#ibcon#enter sib2, iclass 29, count 2 2006.285.16:39:18.39#ibcon#flushed, iclass 29, count 2 2006.285.16:39:18.39#ibcon#about to write, iclass 29, count 2 2006.285.16:39:18.39#ibcon#wrote, iclass 29, count 2 2006.285.16:39:18.39#ibcon#about to read 3, iclass 29, count 2 2006.285.16:39:18.42#ibcon#read 3, iclass 29, count 2 2006.285.16:39:18.42#ibcon#about to read 4, iclass 29, count 2 2006.285.16:39:18.42#ibcon#read 4, iclass 29, count 2 2006.285.16:39:18.42#ibcon#about to read 5, iclass 29, count 2 2006.285.16:39:18.42#ibcon#read 5, iclass 29, count 2 2006.285.16:39:18.42#ibcon#about to read 6, iclass 29, count 2 2006.285.16:39:18.42#ibcon#read 6, iclass 29, count 2 2006.285.16:39:18.42#ibcon#end of sib2, iclass 29, count 2 2006.285.16:39:18.42#ibcon#*after write, iclass 29, count 2 2006.285.16:39:18.42#ibcon#*before return 0, iclass 29, count 2 2006.285.16:39:18.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:39:18.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:39:18.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.16:39:18.42#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:18.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:39:18.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:39:18.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:39:18.54#ibcon#enter wrdev, iclass 29, count 0 2006.285.16:39:18.54#ibcon#first serial, iclass 29, count 0 2006.285.16:39:18.54#ibcon#enter sib2, iclass 29, count 0 2006.285.16:39:18.54#ibcon#flushed, iclass 29, count 0 2006.285.16:39:18.54#ibcon#about to write, iclass 29, count 0 2006.285.16:39:18.54#ibcon#wrote, iclass 29, count 0 2006.285.16:39:18.54#ibcon#about to read 3, iclass 29, count 0 2006.285.16:39:18.56#ibcon#read 3, iclass 29, count 0 2006.285.16:39:18.56#ibcon#about to read 4, iclass 29, count 0 2006.285.16:39:18.56#ibcon#read 4, iclass 29, count 0 2006.285.16:39:18.56#ibcon#about to read 5, iclass 29, count 0 2006.285.16:39:18.56#ibcon#read 5, iclass 29, count 0 2006.285.16:39:18.56#ibcon#about to read 6, iclass 29, count 0 2006.285.16:39:18.56#ibcon#read 6, iclass 29, count 0 2006.285.16:39:18.56#ibcon#end of sib2, iclass 29, count 0 2006.285.16:39:18.56#ibcon#*mode == 0, iclass 29, count 0 2006.285.16:39:18.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.16:39:18.56#ibcon#[27=USB\r\n] 2006.285.16:39:18.56#ibcon#*before write, iclass 29, count 0 2006.285.16:39:18.56#ibcon#enter sib2, iclass 29, count 0 2006.285.16:39:18.56#ibcon#flushed, iclass 29, count 0 2006.285.16:39:18.56#ibcon#about to write, iclass 29, count 0 2006.285.16:39:18.56#ibcon#wrote, iclass 29, count 0 2006.285.16:39:18.56#ibcon#about to read 3, iclass 29, count 0 2006.285.16:39:18.59#ibcon#read 3, iclass 29, count 0 2006.285.16:39:18.59#ibcon#about to read 4, iclass 29, count 0 2006.285.16:39:18.59#ibcon#read 4, iclass 29, count 0 2006.285.16:39:18.59#ibcon#about to read 5, iclass 29, count 0 2006.285.16:39:18.59#ibcon#read 5, iclass 29, count 0 2006.285.16:39:18.59#ibcon#about to read 6, iclass 29, count 0 2006.285.16:39:18.59#ibcon#read 6, iclass 29, count 0 2006.285.16:39:18.59#ibcon#end of sib2, iclass 29, count 0 2006.285.16:39:18.59#ibcon#*after write, iclass 29, count 0 2006.285.16:39:18.59#ibcon#*before return 0, iclass 29, count 0 2006.285.16:39:18.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:39:18.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:39:18.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.16:39:18.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.16:39:18.59$vck44/vblo=2,634.99 2006.285.16:39:18.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.16:39:18.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.16:39:18.59#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:18.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:39:18.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:39:18.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:39:18.59#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:39:18.59#ibcon#first serial, iclass 31, count 0 2006.285.16:39:18.59#ibcon#enter sib2, iclass 31, count 0 2006.285.16:39:18.59#ibcon#flushed, iclass 31, count 0 2006.285.16:39:18.59#ibcon#about to write, iclass 31, count 0 2006.285.16:39:18.59#ibcon#wrote, iclass 31, count 0 2006.285.16:39:18.59#ibcon#about to read 3, iclass 31, count 0 2006.285.16:39:18.61#ibcon#read 3, iclass 31, count 0 2006.285.16:39:18.61#ibcon#about to read 4, iclass 31, count 0 2006.285.16:39:18.61#ibcon#read 4, iclass 31, count 0 2006.285.16:39:18.61#ibcon#about to read 5, iclass 31, count 0 2006.285.16:39:18.61#ibcon#read 5, iclass 31, count 0 2006.285.16:39:18.61#ibcon#about to read 6, iclass 31, count 0 2006.285.16:39:18.61#ibcon#read 6, iclass 31, count 0 2006.285.16:39:18.61#ibcon#end of sib2, iclass 31, count 0 2006.285.16:39:18.61#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:39:18.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:39:18.61#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.16:39:18.61#ibcon#*before write, iclass 31, count 0 2006.285.16:39:18.61#ibcon#enter sib2, iclass 31, count 0 2006.285.16:39:18.61#ibcon#flushed, iclass 31, count 0 2006.285.16:39:18.61#ibcon#about to write, iclass 31, count 0 2006.285.16:39:18.61#ibcon#wrote, iclass 31, count 0 2006.285.16:39:18.61#ibcon#about to read 3, iclass 31, count 0 2006.285.16:39:18.65#ibcon#read 3, iclass 31, count 0 2006.285.16:39:18.65#ibcon#about to read 4, iclass 31, count 0 2006.285.16:39:18.65#ibcon#read 4, iclass 31, count 0 2006.285.16:39:18.65#ibcon#about to read 5, iclass 31, count 0 2006.285.16:39:18.65#ibcon#read 5, iclass 31, count 0 2006.285.16:39:18.65#ibcon#about to read 6, iclass 31, count 0 2006.285.16:39:18.65#ibcon#read 6, iclass 31, count 0 2006.285.16:39:18.65#ibcon#end of sib2, iclass 31, count 0 2006.285.16:39:18.65#ibcon#*after write, iclass 31, count 0 2006.285.16:39:18.65#ibcon#*before return 0, iclass 31, count 0 2006.285.16:39:18.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:39:18.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:39:18.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:39:18.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:39:18.65$vck44/vb=2,5 2006.285.16:39:18.86#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.16:39:18.86#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.16:39:18.86#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:18.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:39:18.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:39:18.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:39:18.86#ibcon#enter wrdev, iclass 33, count 2 2006.285.16:39:18.86#ibcon#first serial, iclass 33, count 2 2006.285.16:39:18.86#ibcon#enter sib2, iclass 33, count 2 2006.285.16:39:18.86#ibcon#flushed, iclass 33, count 2 2006.285.16:39:18.86#ibcon#about to write, iclass 33, count 2 2006.285.16:39:18.86#ibcon#wrote, iclass 33, count 2 2006.285.16:39:18.86#ibcon#about to read 3, iclass 33, count 2 2006.285.16:39:18.87#ibcon#read 3, iclass 33, count 2 2006.285.16:39:18.87#ibcon#about to read 4, iclass 33, count 2 2006.285.16:39:18.87#ibcon#read 4, iclass 33, count 2 2006.285.16:39:18.87#ibcon#about to read 5, iclass 33, count 2 2006.285.16:39:18.87#ibcon#read 5, iclass 33, count 2 2006.285.16:39:18.87#ibcon#about to read 6, iclass 33, count 2 2006.285.16:39:18.87#ibcon#read 6, iclass 33, count 2 2006.285.16:39:18.87#ibcon#end of sib2, iclass 33, count 2 2006.285.16:39:18.87#ibcon#*mode == 0, iclass 33, count 2 2006.285.16:39:18.87#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.16:39:18.87#ibcon#[27=AT02-05\r\n] 2006.285.16:39:18.87#ibcon#*before write, iclass 33, count 2 2006.285.16:39:18.87#ibcon#enter sib2, iclass 33, count 2 2006.285.16:39:18.87#ibcon#flushed, iclass 33, count 2 2006.285.16:39:18.87#ibcon#about to write, iclass 33, count 2 2006.285.16:39:18.87#ibcon#wrote, iclass 33, count 2 2006.285.16:39:18.87#ibcon#about to read 3, iclass 33, count 2 2006.285.16:39:18.90#ibcon#read 3, iclass 33, count 2 2006.285.16:39:18.90#ibcon#about to read 4, iclass 33, count 2 2006.285.16:39:18.90#ibcon#read 4, iclass 33, count 2 2006.285.16:39:18.90#ibcon#about to read 5, iclass 33, count 2 2006.285.16:39:18.90#ibcon#read 5, iclass 33, count 2 2006.285.16:39:18.90#ibcon#about to read 6, iclass 33, count 2 2006.285.16:39:18.90#ibcon#read 6, iclass 33, count 2 2006.285.16:39:18.90#ibcon#end of sib2, iclass 33, count 2 2006.285.16:39:18.90#ibcon#*after write, iclass 33, count 2 2006.285.16:39:18.90#ibcon#*before return 0, iclass 33, count 2 2006.285.16:39:18.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:39:18.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:39:18.90#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.16:39:18.90#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:18.90#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:39:19.02#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:39:19.02#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:39:19.02#ibcon#enter wrdev, iclass 33, count 0 2006.285.16:39:19.02#ibcon#first serial, iclass 33, count 0 2006.285.16:39:19.02#ibcon#enter sib2, iclass 33, count 0 2006.285.16:39:19.02#ibcon#flushed, iclass 33, count 0 2006.285.16:39:19.02#ibcon#about to write, iclass 33, count 0 2006.285.16:39:19.02#ibcon#wrote, iclass 33, count 0 2006.285.16:39:19.02#ibcon#about to read 3, iclass 33, count 0 2006.285.16:39:19.04#ibcon#read 3, iclass 33, count 0 2006.285.16:39:19.04#ibcon#about to read 4, iclass 33, count 0 2006.285.16:39:19.04#ibcon#read 4, iclass 33, count 0 2006.285.16:39:19.04#ibcon#about to read 5, iclass 33, count 0 2006.285.16:39:19.04#ibcon#read 5, iclass 33, count 0 2006.285.16:39:19.04#ibcon#about to read 6, iclass 33, count 0 2006.285.16:39:19.04#ibcon#read 6, iclass 33, count 0 2006.285.16:39:19.04#ibcon#end of sib2, iclass 33, count 0 2006.285.16:39:19.04#ibcon#*mode == 0, iclass 33, count 0 2006.285.16:39:19.04#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.16:39:19.04#ibcon#[27=USB\r\n] 2006.285.16:39:19.04#ibcon#*before write, iclass 33, count 0 2006.285.16:39:19.04#ibcon#enter sib2, iclass 33, count 0 2006.285.16:39:19.04#ibcon#flushed, iclass 33, count 0 2006.285.16:39:19.04#ibcon#about to write, iclass 33, count 0 2006.285.16:39:19.04#ibcon#wrote, iclass 33, count 0 2006.285.16:39:19.04#ibcon#about to read 3, iclass 33, count 0 2006.285.16:39:19.07#ibcon#read 3, iclass 33, count 0 2006.285.16:39:19.07#ibcon#about to read 4, iclass 33, count 0 2006.285.16:39:19.07#ibcon#read 4, iclass 33, count 0 2006.285.16:39:19.07#ibcon#about to read 5, iclass 33, count 0 2006.285.16:39:19.07#ibcon#read 5, iclass 33, count 0 2006.285.16:39:19.07#ibcon#about to read 6, iclass 33, count 0 2006.285.16:39:19.07#ibcon#read 6, iclass 33, count 0 2006.285.16:39:19.07#ibcon#end of sib2, iclass 33, count 0 2006.285.16:39:19.07#ibcon#*after write, iclass 33, count 0 2006.285.16:39:19.07#ibcon#*before return 0, iclass 33, count 0 2006.285.16:39:19.07#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:39:19.07#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:39:19.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.16:39:19.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.16:39:19.07$vck44/vblo=3,649.99 2006.285.16:39:19.07#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.16:39:19.07#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.16:39:19.07#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:19.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:39:19.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:39:19.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:39:19.07#ibcon#enter wrdev, iclass 35, count 0 2006.285.16:39:19.07#ibcon#first serial, iclass 35, count 0 2006.285.16:39:19.07#ibcon#enter sib2, iclass 35, count 0 2006.285.16:39:19.07#ibcon#flushed, iclass 35, count 0 2006.285.16:39:19.07#ibcon#about to write, iclass 35, count 0 2006.285.16:39:19.07#ibcon#wrote, iclass 35, count 0 2006.285.16:39:19.07#ibcon#about to read 3, iclass 35, count 0 2006.285.16:39:19.09#ibcon#read 3, iclass 35, count 0 2006.285.16:39:19.09#ibcon#about to read 4, iclass 35, count 0 2006.285.16:39:19.09#ibcon#read 4, iclass 35, count 0 2006.285.16:39:19.09#ibcon#about to read 5, iclass 35, count 0 2006.285.16:39:19.09#ibcon#read 5, iclass 35, count 0 2006.285.16:39:19.09#ibcon#about to read 6, iclass 35, count 0 2006.285.16:39:19.09#ibcon#read 6, iclass 35, count 0 2006.285.16:39:19.09#ibcon#end of sib2, iclass 35, count 0 2006.285.16:39:19.09#ibcon#*mode == 0, iclass 35, count 0 2006.285.16:39:19.09#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.16:39:19.09#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.16:39:19.09#ibcon#*before write, iclass 35, count 0 2006.285.16:39:19.09#ibcon#enter sib2, iclass 35, count 0 2006.285.16:39:19.09#ibcon#flushed, iclass 35, count 0 2006.285.16:39:19.09#ibcon#about to write, iclass 35, count 0 2006.285.16:39:19.09#ibcon#wrote, iclass 35, count 0 2006.285.16:39:19.09#ibcon#about to read 3, iclass 35, count 0 2006.285.16:39:19.13#ibcon#read 3, iclass 35, count 0 2006.285.16:39:19.13#ibcon#about to read 4, iclass 35, count 0 2006.285.16:39:19.13#ibcon#read 4, iclass 35, count 0 2006.285.16:39:19.13#ibcon#about to read 5, iclass 35, count 0 2006.285.16:39:19.13#ibcon#read 5, iclass 35, count 0 2006.285.16:39:19.13#ibcon#about to read 6, iclass 35, count 0 2006.285.16:39:19.13#ibcon#read 6, iclass 35, count 0 2006.285.16:39:19.13#ibcon#end of sib2, iclass 35, count 0 2006.285.16:39:19.13#ibcon#*after write, iclass 35, count 0 2006.285.16:39:19.13#ibcon#*before return 0, iclass 35, count 0 2006.285.16:39:19.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:39:19.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:39:19.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.16:39:19.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.16:39:19.13$vck44/vb=3,4 2006.285.16:39:19.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.16:39:19.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.16:39:19.13#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:19.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:39:19.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:39:19.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:39:19.19#ibcon#enter wrdev, iclass 37, count 2 2006.285.16:39:19.19#ibcon#first serial, iclass 37, count 2 2006.285.16:39:19.19#ibcon#enter sib2, iclass 37, count 2 2006.285.16:39:19.19#ibcon#flushed, iclass 37, count 2 2006.285.16:39:19.19#ibcon#about to write, iclass 37, count 2 2006.285.16:39:19.19#ibcon#wrote, iclass 37, count 2 2006.285.16:39:19.19#ibcon#about to read 3, iclass 37, count 2 2006.285.16:39:19.21#ibcon#read 3, iclass 37, count 2 2006.285.16:39:19.21#ibcon#about to read 4, iclass 37, count 2 2006.285.16:39:19.21#ibcon#read 4, iclass 37, count 2 2006.285.16:39:19.21#ibcon#about to read 5, iclass 37, count 2 2006.285.16:39:19.21#ibcon#read 5, iclass 37, count 2 2006.285.16:39:19.21#ibcon#about to read 6, iclass 37, count 2 2006.285.16:39:19.21#ibcon#read 6, iclass 37, count 2 2006.285.16:39:19.21#ibcon#end of sib2, iclass 37, count 2 2006.285.16:39:19.21#ibcon#*mode == 0, iclass 37, count 2 2006.285.16:39:19.21#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.16:39:19.21#ibcon#[27=AT03-04\r\n] 2006.285.16:39:19.21#ibcon#*before write, iclass 37, count 2 2006.285.16:39:19.21#ibcon#enter sib2, iclass 37, count 2 2006.285.16:39:19.21#ibcon#flushed, iclass 37, count 2 2006.285.16:39:19.21#ibcon#about to write, iclass 37, count 2 2006.285.16:39:19.21#ibcon#wrote, iclass 37, count 2 2006.285.16:39:19.21#ibcon#about to read 3, iclass 37, count 2 2006.285.16:39:19.24#ibcon#read 3, iclass 37, count 2 2006.285.16:39:19.24#ibcon#about to read 4, iclass 37, count 2 2006.285.16:39:19.24#ibcon#read 4, iclass 37, count 2 2006.285.16:39:19.24#ibcon#about to read 5, iclass 37, count 2 2006.285.16:39:19.24#ibcon#read 5, iclass 37, count 2 2006.285.16:39:19.24#ibcon#about to read 6, iclass 37, count 2 2006.285.16:39:19.24#ibcon#read 6, iclass 37, count 2 2006.285.16:39:19.24#ibcon#end of sib2, iclass 37, count 2 2006.285.16:39:19.24#ibcon#*after write, iclass 37, count 2 2006.285.16:39:19.24#ibcon#*before return 0, iclass 37, count 2 2006.285.16:39:19.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:39:19.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:39:19.24#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.16:39:19.24#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:19.24#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:39:19.36#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:39:19.36#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:39:19.36#ibcon#enter wrdev, iclass 37, count 0 2006.285.16:39:19.36#ibcon#first serial, iclass 37, count 0 2006.285.16:39:19.36#ibcon#enter sib2, iclass 37, count 0 2006.285.16:39:19.36#ibcon#flushed, iclass 37, count 0 2006.285.16:39:19.36#ibcon#about to write, iclass 37, count 0 2006.285.16:39:19.36#ibcon#wrote, iclass 37, count 0 2006.285.16:39:19.36#ibcon#about to read 3, iclass 37, count 0 2006.285.16:39:19.38#ibcon#read 3, iclass 37, count 0 2006.285.16:39:19.38#ibcon#about to read 4, iclass 37, count 0 2006.285.16:39:19.38#ibcon#read 4, iclass 37, count 0 2006.285.16:39:19.38#ibcon#about to read 5, iclass 37, count 0 2006.285.16:39:19.38#ibcon#read 5, iclass 37, count 0 2006.285.16:39:19.38#ibcon#about to read 6, iclass 37, count 0 2006.285.16:39:19.38#ibcon#read 6, iclass 37, count 0 2006.285.16:39:19.38#ibcon#end of sib2, iclass 37, count 0 2006.285.16:39:19.38#ibcon#*mode == 0, iclass 37, count 0 2006.285.16:39:19.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.16:39:19.38#ibcon#[27=USB\r\n] 2006.285.16:39:19.38#ibcon#*before write, iclass 37, count 0 2006.285.16:39:19.38#ibcon#enter sib2, iclass 37, count 0 2006.285.16:39:19.38#ibcon#flushed, iclass 37, count 0 2006.285.16:39:19.38#ibcon#about to write, iclass 37, count 0 2006.285.16:39:19.38#ibcon#wrote, iclass 37, count 0 2006.285.16:39:19.38#ibcon#about to read 3, iclass 37, count 0 2006.285.16:39:19.41#ibcon#read 3, iclass 37, count 0 2006.285.16:39:19.41#ibcon#about to read 4, iclass 37, count 0 2006.285.16:39:19.41#ibcon#read 4, iclass 37, count 0 2006.285.16:39:19.41#ibcon#about to read 5, iclass 37, count 0 2006.285.16:39:19.41#ibcon#read 5, iclass 37, count 0 2006.285.16:39:19.41#ibcon#about to read 6, iclass 37, count 0 2006.285.16:39:19.41#ibcon#read 6, iclass 37, count 0 2006.285.16:39:19.41#ibcon#end of sib2, iclass 37, count 0 2006.285.16:39:19.41#ibcon#*after write, iclass 37, count 0 2006.285.16:39:19.41#ibcon#*before return 0, iclass 37, count 0 2006.285.16:39:19.41#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:39:19.41#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:39:19.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.16:39:19.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.16:39:19.41$vck44/vblo=4,679.99 2006.285.16:39:19.41#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.16:39:19.41#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.16:39:19.41#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:19.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:39:19.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:39:19.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:39:19.41#ibcon#enter wrdev, iclass 39, count 0 2006.285.16:39:19.41#ibcon#first serial, iclass 39, count 0 2006.285.16:39:19.41#ibcon#enter sib2, iclass 39, count 0 2006.285.16:39:19.41#ibcon#flushed, iclass 39, count 0 2006.285.16:39:19.41#ibcon#about to write, iclass 39, count 0 2006.285.16:39:19.41#ibcon#wrote, iclass 39, count 0 2006.285.16:39:19.41#ibcon#about to read 3, iclass 39, count 0 2006.285.16:39:19.43#ibcon#read 3, iclass 39, count 0 2006.285.16:39:19.43#ibcon#about to read 4, iclass 39, count 0 2006.285.16:39:19.43#ibcon#read 4, iclass 39, count 0 2006.285.16:39:19.43#ibcon#about to read 5, iclass 39, count 0 2006.285.16:39:19.43#ibcon#read 5, iclass 39, count 0 2006.285.16:39:19.43#ibcon#about to read 6, iclass 39, count 0 2006.285.16:39:19.43#ibcon#read 6, iclass 39, count 0 2006.285.16:39:19.43#ibcon#end of sib2, iclass 39, count 0 2006.285.16:39:19.43#ibcon#*mode == 0, iclass 39, count 0 2006.285.16:39:19.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.16:39:19.43#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.16:39:19.43#ibcon#*before write, iclass 39, count 0 2006.285.16:39:19.43#ibcon#enter sib2, iclass 39, count 0 2006.285.16:39:19.43#ibcon#flushed, iclass 39, count 0 2006.285.16:39:19.43#ibcon#about to write, iclass 39, count 0 2006.285.16:39:19.43#ibcon#wrote, iclass 39, count 0 2006.285.16:39:19.43#ibcon#about to read 3, iclass 39, count 0 2006.285.16:39:19.47#ibcon#read 3, iclass 39, count 0 2006.285.16:39:19.47#ibcon#about to read 4, iclass 39, count 0 2006.285.16:39:19.47#ibcon#read 4, iclass 39, count 0 2006.285.16:39:19.47#ibcon#about to read 5, iclass 39, count 0 2006.285.16:39:19.47#ibcon#read 5, iclass 39, count 0 2006.285.16:39:19.47#ibcon#about to read 6, iclass 39, count 0 2006.285.16:39:19.47#ibcon#read 6, iclass 39, count 0 2006.285.16:39:19.47#ibcon#end of sib2, iclass 39, count 0 2006.285.16:39:19.47#ibcon#*after write, iclass 39, count 0 2006.285.16:39:19.47#ibcon#*before return 0, iclass 39, count 0 2006.285.16:39:19.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:39:19.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:39:19.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.16:39:19.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.16:39:19.47$vck44/vb=4,5 2006.285.16:39:19.47#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.16:39:19.47#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.16:39:19.47#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:19.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:39:19.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:39:19.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:39:19.53#ibcon#enter wrdev, iclass 3, count 2 2006.285.16:39:19.53#ibcon#first serial, iclass 3, count 2 2006.285.16:39:19.53#ibcon#enter sib2, iclass 3, count 2 2006.285.16:39:19.53#ibcon#flushed, iclass 3, count 2 2006.285.16:39:19.53#ibcon#about to write, iclass 3, count 2 2006.285.16:39:19.53#ibcon#wrote, iclass 3, count 2 2006.285.16:39:19.53#ibcon#about to read 3, iclass 3, count 2 2006.285.16:39:19.55#ibcon#read 3, iclass 3, count 2 2006.285.16:39:19.55#ibcon#about to read 4, iclass 3, count 2 2006.285.16:39:19.55#ibcon#read 4, iclass 3, count 2 2006.285.16:39:19.55#ibcon#about to read 5, iclass 3, count 2 2006.285.16:39:19.55#ibcon#read 5, iclass 3, count 2 2006.285.16:39:19.55#ibcon#about to read 6, iclass 3, count 2 2006.285.16:39:19.55#ibcon#read 6, iclass 3, count 2 2006.285.16:39:19.55#ibcon#end of sib2, iclass 3, count 2 2006.285.16:39:19.55#ibcon#*mode == 0, iclass 3, count 2 2006.285.16:39:19.55#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.16:39:19.55#ibcon#[27=AT04-05\r\n] 2006.285.16:39:19.55#ibcon#*before write, iclass 3, count 2 2006.285.16:39:19.55#ibcon#enter sib2, iclass 3, count 2 2006.285.16:39:19.55#ibcon#flushed, iclass 3, count 2 2006.285.16:39:19.55#ibcon#about to write, iclass 3, count 2 2006.285.16:39:19.55#ibcon#wrote, iclass 3, count 2 2006.285.16:39:19.55#ibcon#about to read 3, iclass 3, count 2 2006.285.16:39:19.58#ibcon#read 3, iclass 3, count 2 2006.285.16:39:19.58#ibcon#about to read 4, iclass 3, count 2 2006.285.16:39:19.58#ibcon#read 4, iclass 3, count 2 2006.285.16:39:19.58#ibcon#about to read 5, iclass 3, count 2 2006.285.16:39:19.58#ibcon#read 5, iclass 3, count 2 2006.285.16:39:19.58#ibcon#about to read 6, iclass 3, count 2 2006.285.16:39:19.58#ibcon#read 6, iclass 3, count 2 2006.285.16:39:19.58#ibcon#end of sib2, iclass 3, count 2 2006.285.16:39:19.58#ibcon#*after write, iclass 3, count 2 2006.285.16:39:19.58#ibcon#*before return 0, iclass 3, count 2 2006.285.16:39:19.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:39:19.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:39:19.58#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.16:39:19.58#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:19.58#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:39:19.70#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:39:19.70#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:39:19.70#ibcon#enter wrdev, iclass 3, count 0 2006.285.16:39:19.70#ibcon#first serial, iclass 3, count 0 2006.285.16:39:19.70#ibcon#enter sib2, iclass 3, count 0 2006.285.16:39:19.70#ibcon#flushed, iclass 3, count 0 2006.285.16:39:19.70#ibcon#about to write, iclass 3, count 0 2006.285.16:39:19.70#ibcon#wrote, iclass 3, count 0 2006.285.16:39:19.70#ibcon#about to read 3, iclass 3, count 0 2006.285.16:39:19.72#ibcon#read 3, iclass 3, count 0 2006.285.16:39:19.72#ibcon#about to read 4, iclass 3, count 0 2006.285.16:39:19.72#ibcon#read 4, iclass 3, count 0 2006.285.16:39:19.72#ibcon#about to read 5, iclass 3, count 0 2006.285.16:39:19.72#ibcon#read 5, iclass 3, count 0 2006.285.16:39:19.72#ibcon#about to read 6, iclass 3, count 0 2006.285.16:39:19.72#ibcon#read 6, iclass 3, count 0 2006.285.16:39:19.72#ibcon#end of sib2, iclass 3, count 0 2006.285.16:39:19.72#ibcon#*mode == 0, iclass 3, count 0 2006.285.16:39:19.72#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.16:39:19.72#ibcon#[27=USB\r\n] 2006.285.16:39:19.72#ibcon#*before write, iclass 3, count 0 2006.285.16:39:19.72#ibcon#enter sib2, iclass 3, count 0 2006.285.16:39:19.72#ibcon#flushed, iclass 3, count 0 2006.285.16:39:19.72#ibcon#about to write, iclass 3, count 0 2006.285.16:39:19.72#ibcon#wrote, iclass 3, count 0 2006.285.16:39:19.72#ibcon#about to read 3, iclass 3, count 0 2006.285.16:39:19.75#ibcon#read 3, iclass 3, count 0 2006.285.16:39:19.75#ibcon#about to read 4, iclass 3, count 0 2006.285.16:39:19.75#ibcon#read 4, iclass 3, count 0 2006.285.16:39:19.75#ibcon#about to read 5, iclass 3, count 0 2006.285.16:39:19.75#ibcon#read 5, iclass 3, count 0 2006.285.16:39:19.75#ibcon#about to read 6, iclass 3, count 0 2006.285.16:39:19.75#ibcon#read 6, iclass 3, count 0 2006.285.16:39:19.75#ibcon#end of sib2, iclass 3, count 0 2006.285.16:39:19.75#ibcon#*after write, iclass 3, count 0 2006.285.16:39:19.75#ibcon#*before return 0, iclass 3, count 0 2006.285.16:39:19.75#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:39:19.75#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:39:19.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.16:39:19.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.16:39:19.75$vck44/vblo=5,709.99 2006.285.16:39:19.75#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.16:39:19.75#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.16:39:19.75#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:19.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:39:19.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:39:19.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:39:19.75#ibcon#enter wrdev, iclass 5, count 0 2006.285.16:39:19.75#ibcon#first serial, iclass 5, count 0 2006.285.16:39:19.75#ibcon#enter sib2, iclass 5, count 0 2006.285.16:39:19.75#ibcon#flushed, iclass 5, count 0 2006.285.16:39:19.75#ibcon#about to write, iclass 5, count 0 2006.285.16:39:19.75#ibcon#wrote, iclass 5, count 0 2006.285.16:39:19.75#ibcon#about to read 3, iclass 5, count 0 2006.285.16:39:19.94#ibcon#read 3, iclass 5, count 0 2006.285.16:39:19.94#ibcon#about to read 4, iclass 5, count 0 2006.285.16:39:19.94#ibcon#read 4, iclass 5, count 0 2006.285.16:39:19.94#ibcon#about to read 5, iclass 5, count 0 2006.285.16:39:19.94#ibcon#read 5, iclass 5, count 0 2006.285.16:39:19.94#ibcon#about to read 6, iclass 5, count 0 2006.285.16:39:19.94#ibcon#read 6, iclass 5, count 0 2006.285.16:39:19.94#ibcon#end of sib2, iclass 5, count 0 2006.285.16:39:19.94#ibcon#*mode == 0, iclass 5, count 0 2006.285.16:39:19.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.16:39:19.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.16:39:19.94#ibcon#*before write, iclass 5, count 0 2006.285.16:39:19.94#ibcon#enter sib2, iclass 5, count 0 2006.285.16:39:19.94#ibcon#flushed, iclass 5, count 0 2006.285.16:39:19.94#ibcon#about to write, iclass 5, count 0 2006.285.16:39:19.94#ibcon#wrote, iclass 5, count 0 2006.285.16:39:19.94#ibcon#about to read 3, iclass 5, count 0 2006.285.16:39:19.98#ibcon#read 3, iclass 5, count 0 2006.285.16:39:19.98#ibcon#about to read 4, iclass 5, count 0 2006.285.16:39:19.98#ibcon#read 4, iclass 5, count 0 2006.285.16:39:19.98#ibcon#about to read 5, iclass 5, count 0 2006.285.16:39:19.98#ibcon#read 5, iclass 5, count 0 2006.285.16:39:19.98#ibcon#about to read 6, iclass 5, count 0 2006.285.16:39:19.98#ibcon#read 6, iclass 5, count 0 2006.285.16:39:19.98#ibcon#end of sib2, iclass 5, count 0 2006.285.16:39:19.98#ibcon#*after write, iclass 5, count 0 2006.285.16:39:19.98#ibcon#*before return 0, iclass 5, count 0 2006.285.16:39:19.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:39:19.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:39:19.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.16:39:19.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.16:39:19.98$vck44/vb=5,4 2006.285.16:39:19.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.16:39:19.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.16:39:19.98#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:19.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:39:19.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:39:19.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:39:19.98#ibcon#enter wrdev, iclass 7, count 2 2006.285.16:39:19.98#ibcon#first serial, iclass 7, count 2 2006.285.16:39:19.98#ibcon#enter sib2, iclass 7, count 2 2006.285.16:39:19.98#ibcon#flushed, iclass 7, count 2 2006.285.16:39:19.98#ibcon#about to write, iclass 7, count 2 2006.285.16:39:19.98#ibcon#wrote, iclass 7, count 2 2006.285.16:39:19.98#ibcon#about to read 3, iclass 7, count 2 2006.285.16:39:20.00#ibcon#read 3, iclass 7, count 2 2006.285.16:39:20.00#ibcon#about to read 4, iclass 7, count 2 2006.285.16:39:20.00#ibcon#read 4, iclass 7, count 2 2006.285.16:39:20.00#ibcon#about to read 5, iclass 7, count 2 2006.285.16:39:20.00#ibcon#read 5, iclass 7, count 2 2006.285.16:39:20.00#ibcon#about to read 6, iclass 7, count 2 2006.285.16:39:20.00#ibcon#read 6, iclass 7, count 2 2006.285.16:39:20.00#ibcon#end of sib2, iclass 7, count 2 2006.285.16:39:20.00#ibcon#*mode == 0, iclass 7, count 2 2006.285.16:39:20.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.16:39:20.00#ibcon#[27=AT05-04\r\n] 2006.285.16:39:20.00#ibcon#*before write, iclass 7, count 2 2006.285.16:39:20.00#ibcon#enter sib2, iclass 7, count 2 2006.285.16:39:20.00#ibcon#flushed, iclass 7, count 2 2006.285.16:39:20.00#ibcon#about to write, iclass 7, count 2 2006.285.16:39:20.00#ibcon#wrote, iclass 7, count 2 2006.285.16:39:20.00#ibcon#about to read 3, iclass 7, count 2 2006.285.16:39:20.03#ibcon#read 3, iclass 7, count 2 2006.285.16:39:20.03#ibcon#about to read 4, iclass 7, count 2 2006.285.16:39:20.03#ibcon#read 4, iclass 7, count 2 2006.285.16:39:20.03#ibcon#about to read 5, iclass 7, count 2 2006.285.16:39:20.03#ibcon#read 5, iclass 7, count 2 2006.285.16:39:20.03#ibcon#about to read 6, iclass 7, count 2 2006.285.16:39:20.03#ibcon#read 6, iclass 7, count 2 2006.285.16:39:20.03#ibcon#end of sib2, iclass 7, count 2 2006.285.16:39:20.03#ibcon#*after write, iclass 7, count 2 2006.285.16:39:20.03#ibcon#*before return 0, iclass 7, count 2 2006.285.16:39:20.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:39:20.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:39:20.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.16:39:20.03#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:20.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:39:20.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:39:20.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:39:20.15#ibcon#enter wrdev, iclass 7, count 0 2006.285.16:39:20.15#ibcon#first serial, iclass 7, count 0 2006.285.16:39:20.15#ibcon#enter sib2, iclass 7, count 0 2006.285.16:39:20.15#ibcon#flushed, iclass 7, count 0 2006.285.16:39:20.15#ibcon#about to write, iclass 7, count 0 2006.285.16:39:20.15#ibcon#wrote, iclass 7, count 0 2006.285.16:39:20.15#ibcon#about to read 3, iclass 7, count 0 2006.285.16:39:20.17#ibcon#read 3, iclass 7, count 0 2006.285.16:39:20.17#ibcon#about to read 4, iclass 7, count 0 2006.285.16:39:20.17#ibcon#read 4, iclass 7, count 0 2006.285.16:39:20.17#ibcon#about to read 5, iclass 7, count 0 2006.285.16:39:20.17#ibcon#read 5, iclass 7, count 0 2006.285.16:39:20.17#ibcon#about to read 6, iclass 7, count 0 2006.285.16:39:20.17#ibcon#read 6, iclass 7, count 0 2006.285.16:39:20.17#ibcon#end of sib2, iclass 7, count 0 2006.285.16:39:20.17#ibcon#*mode == 0, iclass 7, count 0 2006.285.16:39:20.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.16:39:20.17#ibcon#[27=USB\r\n] 2006.285.16:39:20.17#ibcon#*before write, iclass 7, count 0 2006.285.16:39:20.17#ibcon#enter sib2, iclass 7, count 0 2006.285.16:39:20.17#ibcon#flushed, iclass 7, count 0 2006.285.16:39:20.17#ibcon#about to write, iclass 7, count 0 2006.285.16:39:20.17#ibcon#wrote, iclass 7, count 0 2006.285.16:39:20.17#ibcon#about to read 3, iclass 7, count 0 2006.285.16:39:20.20#ibcon#read 3, iclass 7, count 0 2006.285.16:39:20.20#ibcon#about to read 4, iclass 7, count 0 2006.285.16:39:20.20#ibcon#read 4, iclass 7, count 0 2006.285.16:39:20.20#ibcon#about to read 5, iclass 7, count 0 2006.285.16:39:20.20#ibcon#read 5, iclass 7, count 0 2006.285.16:39:20.20#ibcon#about to read 6, iclass 7, count 0 2006.285.16:39:20.20#ibcon#read 6, iclass 7, count 0 2006.285.16:39:20.20#ibcon#end of sib2, iclass 7, count 0 2006.285.16:39:20.20#ibcon#*after write, iclass 7, count 0 2006.285.16:39:20.20#ibcon#*before return 0, iclass 7, count 0 2006.285.16:39:20.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:39:20.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:39:20.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.16:39:20.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.16:39:20.20$vck44/vblo=6,719.99 2006.285.16:39:20.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.16:39:20.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.16:39:20.20#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:20.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:39:20.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:39:20.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:39:20.20#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:39:20.20#ibcon#first serial, iclass 11, count 0 2006.285.16:39:20.20#ibcon#enter sib2, iclass 11, count 0 2006.285.16:39:20.20#ibcon#flushed, iclass 11, count 0 2006.285.16:39:20.20#ibcon#about to write, iclass 11, count 0 2006.285.16:39:20.20#ibcon#wrote, iclass 11, count 0 2006.285.16:39:20.20#ibcon#about to read 3, iclass 11, count 0 2006.285.16:39:20.22#ibcon#read 3, iclass 11, count 0 2006.285.16:39:20.22#ibcon#about to read 4, iclass 11, count 0 2006.285.16:39:20.22#ibcon#read 4, iclass 11, count 0 2006.285.16:39:20.22#ibcon#about to read 5, iclass 11, count 0 2006.285.16:39:20.22#ibcon#read 5, iclass 11, count 0 2006.285.16:39:20.22#ibcon#about to read 6, iclass 11, count 0 2006.285.16:39:20.22#ibcon#read 6, iclass 11, count 0 2006.285.16:39:20.22#ibcon#end of sib2, iclass 11, count 0 2006.285.16:39:20.22#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:39:20.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:39:20.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.16:39:20.22#ibcon#*before write, iclass 11, count 0 2006.285.16:39:20.22#ibcon#enter sib2, iclass 11, count 0 2006.285.16:39:20.22#ibcon#flushed, iclass 11, count 0 2006.285.16:39:20.22#ibcon#about to write, iclass 11, count 0 2006.285.16:39:20.22#ibcon#wrote, iclass 11, count 0 2006.285.16:39:20.22#ibcon#about to read 3, iclass 11, count 0 2006.285.16:39:20.26#ibcon#read 3, iclass 11, count 0 2006.285.16:39:20.26#ibcon#about to read 4, iclass 11, count 0 2006.285.16:39:20.26#ibcon#read 4, iclass 11, count 0 2006.285.16:39:20.26#ibcon#about to read 5, iclass 11, count 0 2006.285.16:39:20.26#ibcon#read 5, iclass 11, count 0 2006.285.16:39:20.26#ibcon#about to read 6, iclass 11, count 0 2006.285.16:39:20.26#ibcon#read 6, iclass 11, count 0 2006.285.16:39:20.26#ibcon#end of sib2, iclass 11, count 0 2006.285.16:39:20.26#ibcon#*after write, iclass 11, count 0 2006.285.16:39:20.26#ibcon#*before return 0, iclass 11, count 0 2006.285.16:39:20.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:39:20.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:39:20.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:39:20.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:39:20.26$vck44/vb=6,3 2006.285.16:39:20.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.16:39:20.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.16:39:20.26#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:20.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:39:20.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:39:20.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:39:20.32#ibcon#enter wrdev, iclass 13, count 2 2006.285.16:39:20.32#ibcon#first serial, iclass 13, count 2 2006.285.16:39:20.32#ibcon#enter sib2, iclass 13, count 2 2006.285.16:39:20.32#ibcon#flushed, iclass 13, count 2 2006.285.16:39:20.32#ibcon#about to write, iclass 13, count 2 2006.285.16:39:20.32#ibcon#wrote, iclass 13, count 2 2006.285.16:39:20.32#ibcon#about to read 3, iclass 13, count 2 2006.285.16:39:20.34#ibcon#read 3, iclass 13, count 2 2006.285.16:39:20.34#ibcon#about to read 4, iclass 13, count 2 2006.285.16:39:20.34#ibcon#read 4, iclass 13, count 2 2006.285.16:39:20.34#ibcon#about to read 5, iclass 13, count 2 2006.285.16:39:20.34#ibcon#read 5, iclass 13, count 2 2006.285.16:39:20.34#ibcon#about to read 6, iclass 13, count 2 2006.285.16:39:20.34#ibcon#read 6, iclass 13, count 2 2006.285.16:39:20.34#ibcon#end of sib2, iclass 13, count 2 2006.285.16:39:20.34#ibcon#*mode == 0, iclass 13, count 2 2006.285.16:39:20.34#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.16:39:20.34#ibcon#[27=AT06-03\r\n] 2006.285.16:39:20.34#ibcon#*before write, iclass 13, count 2 2006.285.16:39:20.34#ibcon#enter sib2, iclass 13, count 2 2006.285.16:39:20.34#ibcon#flushed, iclass 13, count 2 2006.285.16:39:20.34#ibcon#about to write, iclass 13, count 2 2006.285.16:39:20.34#ibcon#wrote, iclass 13, count 2 2006.285.16:39:20.34#ibcon#about to read 3, iclass 13, count 2 2006.285.16:39:20.37#ibcon#read 3, iclass 13, count 2 2006.285.16:39:20.37#ibcon#about to read 4, iclass 13, count 2 2006.285.16:39:20.37#ibcon#read 4, iclass 13, count 2 2006.285.16:39:20.37#ibcon#about to read 5, iclass 13, count 2 2006.285.16:39:20.37#ibcon#read 5, iclass 13, count 2 2006.285.16:39:20.37#ibcon#about to read 6, iclass 13, count 2 2006.285.16:39:20.37#ibcon#read 6, iclass 13, count 2 2006.285.16:39:20.37#ibcon#end of sib2, iclass 13, count 2 2006.285.16:39:20.37#ibcon#*after write, iclass 13, count 2 2006.285.16:39:20.37#ibcon#*before return 0, iclass 13, count 2 2006.285.16:39:20.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:39:20.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:39:20.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.16:39:20.37#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:20.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:39:20.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:39:20.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:39:20.49#ibcon#enter wrdev, iclass 13, count 0 2006.285.16:39:20.49#ibcon#first serial, iclass 13, count 0 2006.285.16:39:20.49#ibcon#enter sib2, iclass 13, count 0 2006.285.16:39:20.49#ibcon#flushed, iclass 13, count 0 2006.285.16:39:20.49#ibcon#about to write, iclass 13, count 0 2006.285.16:39:20.49#ibcon#wrote, iclass 13, count 0 2006.285.16:39:20.49#ibcon#about to read 3, iclass 13, count 0 2006.285.16:39:20.51#ibcon#read 3, iclass 13, count 0 2006.285.16:39:20.51#ibcon#about to read 4, iclass 13, count 0 2006.285.16:39:20.51#ibcon#read 4, iclass 13, count 0 2006.285.16:39:20.51#ibcon#about to read 5, iclass 13, count 0 2006.285.16:39:20.51#ibcon#read 5, iclass 13, count 0 2006.285.16:39:20.51#ibcon#about to read 6, iclass 13, count 0 2006.285.16:39:20.51#ibcon#read 6, iclass 13, count 0 2006.285.16:39:20.51#ibcon#end of sib2, iclass 13, count 0 2006.285.16:39:20.51#ibcon#*mode == 0, iclass 13, count 0 2006.285.16:39:20.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.16:39:20.51#ibcon#[27=USB\r\n] 2006.285.16:39:20.51#ibcon#*before write, iclass 13, count 0 2006.285.16:39:20.51#ibcon#enter sib2, iclass 13, count 0 2006.285.16:39:20.51#ibcon#flushed, iclass 13, count 0 2006.285.16:39:20.51#ibcon#about to write, iclass 13, count 0 2006.285.16:39:20.51#ibcon#wrote, iclass 13, count 0 2006.285.16:39:20.51#ibcon#about to read 3, iclass 13, count 0 2006.285.16:39:20.54#ibcon#read 3, iclass 13, count 0 2006.285.16:39:20.54#ibcon#about to read 4, iclass 13, count 0 2006.285.16:39:20.54#ibcon#read 4, iclass 13, count 0 2006.285.16:39:20.54#ibcon#about to read 5, iclass 13, count 0 2006.285.16:39:20.54#ibcon#read 5, iclass 13, count 0 2006.285.16:39:20.54#ibcon#about to read 6, iclass 13, count 0 2006.285.16:39:20.54#ibcon#read 6, iclass 13, count 0 2006.285.16:39:20.54#ibcon#end of sib2, iclass 13, count 0 2006.285.16:39:20.54#ibcon#*after write, iclass 13, count 0 2006.285.16:39:20.54#ibcon#*before return 0, iclass 13, count 0 2006.285.16:39:20.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:39:20.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:39:20.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.16:39:20.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.16:39:20.54$vck44/vblo=7,734.99 2006.285.16:39:20.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.16:39:20.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.16:39:20.54#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:20.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:39:20.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:39:20.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:39:20.54#ibcon#enter wrdev, iclass 15, count 0 2006.285.16:39:20.54#ibcon#first serial, iclass 15, count 0 2006.285.16:39:20.54#ibcon#enter sib2, iclass 15, count 0 2006.285.16:39:20.54#ibcon#flushed, iclass 15, count 0 2006.285.16:39:20.54#ibcon#about to write, iclass 15, count 0 2006.285.16:39:20.54#ibcon#wrote, iclass 15, count 0 2006.285.16:39:20.54#ibcon#about to read 3, iclass 15, count 0 2006.285.16:39:20.56#ibcon#read 3, iclass 15, count 0 2006.285.16:39:20.56#ibcon#about to read 4, iclass 15, count 0 2006.285.16:39:20.56#ibcon#read 4, iclass 15, count 0 2006.285.16:39:20.56#ibcon#about to read 5, iclass 15, count 0 2006.285.16:39:20.56#ibcon#read 5, iclass 15, count 0 2006.285.16:39:20.56#ibcon#about to read 6, iclass 15, count 0 2006.285.16:39:20.56#ibcon#read 6, iclass 15, count 0 2006.285.16:39:20.56#ibcon#end of sib2, iclass 15, count 0 2006.285.16:39:20.56#ibcon#*mode == 0, iclass 15, count 0 2006.285.16:39:20.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.16:39:20.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.16:39:20.56#ibcon#*before write, iclass 15, count 0 2006.285.16:39:20.56#ibcon#enter sib2, iclass 15, count 0 2006.285.16:39:20.56#ibcon#flushed, iclass 15, count 0 2006.285.16:39:20.56#ibcon#about to write, iclass 15, count 0 2006.285.16:39:20.56#ibcon#wrote, iclass 15, count 0 2006.285.16:39:20.56#ibcon#about to read 3, iclass 15, count 0 2006.285.16:39:20.60#ibcon#read 3, iclass 15, count 0 2006.285.16:39:20.60#ibcon#about to read 4, iclass 15, count 0 2006.285.16:39:20.60#ibcon#read 4, iclass 15, count 0 2006.285.16:39:20.60#ibcon#about to read 5, iclass 15, count 0 2006.285.16:39:20.60#ibcon#read 5, iclass 15, count 0 2006.285.16:39:20.60#ibcon#about to read 6, iclass 15, count 0 2006.285.16:39:20.60#ibcon#read 6, iclass 15, count 0 2006.285.16:39:20.60#ibcon#end of sib2, iclass 15, count 0 2006.285.16:39:20.60#ibcon#*after write, iclass 15, count 0 2006.285.16:39:20.60#ibcon#*before return 0, iclass 15, count 0 2006.285.16:39:20.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:39:20.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:39:20.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.16:39:20.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.16:39:20.60$vck44/vb=7,4 2006.285.16:39:20.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.16:39:20.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.16:39:20.60#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:20.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:39:20.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:39:20.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:39:20.66#ibcon#enter wrdev, iclass 17, count 2 2006.285.16:39:20.66#ibcon#first serial, iclass 17, count 2 2006.285.16:39:20.66#ibcon#enter sib2, iclass 17, count 2 2006.285.16:39:20.66#ibcon#flushed, iclass 17, count 2 2006.285.16:39:20.66#ibcon#about to write, iclass 17, count 2 2006.285.16:39:20.66#ibcon#wrote, iclass 17, count 2 2006.285.16:39:20.66#ibcon#about to read 3, iclass 17, count 2 2006.285.16:39:20.68#ibcon#read 3, iclass 17, count 2 2006.285.16:39:20.68#ibcon#about to read 4, iclass 17, count 2 2006.285.16:39:20.68#ibcon#read 4, iclass 17, count 2 2006.285.16:39:20.68#ibcon#about to read 5, iclass 17, count 2 2006.285.16:39:20.68#ibcon#read 5, iclass 17, count 2 2006.285.16:39:20.68#ibcon#about to read 6, iclass 17, count 2 2006.285.16:39:20.68#ibcon#read 6, iclass 17, count 2 2006.285.16:39:20.68#ibcon#end of sib2, iclass 17, count 2 2006.285.16:39:20.68#ibcon#*mode == 0, iclass 17, count 2 2006.285.16:39:20.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.16:39:20.68#ibcon#[27=AT07-04\r\n] 2006.285.16:39:20.68#ibcon#*before write, iclass 17, count 2 2006.285.16:39:20.68#ibcon#enter sib2, iclass 17, count 2 2006.285.16:39:20.68#ibcon#flushed, iclass 17, count 2 2006.285.16:39:20.68#ibcon#about to write, iclass 17, count 2 2006.285.16:39:20.68#ibcon#wrote, iclass 17, count 2 2006.285.16:39:20.68#ibcon#about to read 3, iclass 17, count 2 2006.285.16:39:20.71#ibcon#read 3, iclass 17, count 2 2006.285.16:39:20.71#ibcon#about to read 4, iclass 17, count 2 2006.285.16:39:20.71#ibcon#read 4, iclass 17, count 2 2006.285.16:39:20.71#ibcon#about to read 5, iclass 17, count 2 2006.285.16:39:20.71#ibcon#read 5, iclass 17, count 2 2006.285.16:39:20.71#ibcon#about to read 6, iclass 17, count 2 2006.285.16:39:20.71#ibcon#read 6, iclass 17, count 2 2006.285.16:39:20.71#ibcon#end of sib2, iclass 17, count 2 2006.285.16:39:20.71#ibcon#*after write, iclass 17, count 2 2006.285.16:39:20.71#ibcon#*before return 0, iclass 17, count 2 2006.285.16:39:20.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:39:20.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:39:20.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.16:39:20.71#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:20.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:39:20.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:39:20.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:39:20.83#ibcon#enter wrdev, iclass 17, count 0 2006.285.16:39:20.83#ibcon#first serial, iclass 17, count 0 2006.285.16:39:20.83#ibcon#enter sib2, iclass 17, count 0 2006.285.16:39:20.83#ibcon#flushed, iclass 17, count 0 2006.285.16:39:20.83#ibcon#about to write, iclass 17, count 0 2006.285.16:39:20.83#ibcon#wrote, iclass 17, count 0 2006.285.16:39:20.83#ibcon#about to read 3, iclass 17, count 0 2006.285.16:39:20.85#ibcon#read 3, iclass 17, count 0 2006.285.16:39:20.85#ibcon#about to read 4, iclass 17, count 0 2006.285.16:39:20.85#ibcon#read 4, iclass 17, count 0 2006.285.16:39:20.85#ibcon#about to read 5, iclass 17, count 0 2006.285.16:39:20.85#ibcon#read 5, iclass 17, count 0 2006.285.16:39:20.85#ibcon#about to read 6, iclass 17, count 0 2006.285.16:39:20.85#ibcon#read 6, iclass 17, count 0 2006.285.16:39:20.85#ibcon#end of sib2, iclass 17, count 0 2006.285.16:39:20.85#ibcon#*mode == 0, iclass 17, count 0 2006.285.16:39:20.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.16:39:20.85#ibcon#[27=USB\r\n] 2006.285.16:39:20.85#ibcon#*before write, iclass 17, count 0 2006.285.16:39:20.85#ibcon#enter sib2, iclass 17, count 0 2006.285.16:39:20.85#ibcon#flushed, iclass 17, count 0 2006.285.16:39:20.85#ibcon#about to write, iclass 17, count 0 2006.285.16:39:20.85#ibcon#wrote, iclass 17, count 0 2006.285.16:39:20.85#ibcon#about to read 3, iclass 17, count 0 2006.285.16:39:20.88#ibcon#read 3, iclass 17, count 0 2006.285.16:39:20.88#ibcon#about to read 4, iclass 17, count 0 2006.285.16:39:20.88#ibcon#read 4, iclass 17, count 0 2006.285.16:39:20.88#ibcon#about to read 5, iclass 17, count 0 2006.285.16:39:20.88#ibcon#read 5, iclass 17, count 0 2006.285.16:39:20.88#ibcon#about to read 6, iclass 17, count 0 2006.285.16:39:20.88#ibcon#read 6, iclass 17, count 0 2006.285.16:39:20.88#ibcon#end of sib2, iclass 17, count 0 2006.285.16:39:20.88#ibcon#*after write, iclass 17, count 0 2006.285.16:39:20.88#ibcon#*before return 0, iclass 17, count 0 2006.285.16:39:20.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:39:20.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:39:20.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.16:39:20.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.16:39:20.88$vck44/vblo=8,744.99 2006.285.16:39:20.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.16:39:20.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.16:39:20.88#ibcon#ireg 17 cls_cnt 0 2006.285.16:39:20.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:39:20.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:39:20.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:39:20.88#ibcon#enter wrdev, iclass 19, count 0 2006.285.16:39:20.88#ibcon#first serial, iclass 19, count 0 2006.285.16:39:20.88#ibcon#enter sib2, iclass 19, count 0 2006.285.16:39:20.88#ibcon#flushed, iclass 19, count 0 2006.285.16:39:20.88#ibcon#about to write, iclass 19, count 0 2006.285.16:39:20.88#ibcon#wrote, iclass 19, count 0 2006.285.16:39:20.88#ibcon#about to read 3, iclass 19, count 0 2006.285.16:39:20.90#ibcon#read 3, iclass 19, count 0 2006.285.16:39:20.90#ibcon#about to read 4, iclass 19, count 0 2006.285.16:39:20.90#ibcon#read 4, iclass 19, count 0 2006.285.16:39:20.90#ibcon#about to read 5, iclass 19, count 0 2006.285.16:39:20.90#ibcon#read 5, iclass 19, count 0 2006.285.16:39:20.90#ibcon#about to read 6, iclass 19, count 0 2006.285.16:39:20.90#ibcon#read 6, iclass 19, count 0 2006.285.16:39:20.90#ibcon#end of sib2, iclass 19, count 0 2006.285.16:39:20.90#ibcon#*mode == 0, iclass 19, count 0 2006.285.16:39:20.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.16:39:20.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.16:39:20.90#ibcon#*before write, iclass 19, count 0 2006.285.16:39:20.90#ibcon#enter sib2, iclass 19, count 0 2006.285.16:39:20.90#ibcon#flushed, iclass 19, count 0 2006.285.16:39:20.90#ibcon#about to write, iclass 19, count 0 2006.285.16:39:20.90#ibcon#wrote, iclass 19, count 0 2006.285.16:39:20.90#ibcon#about to read 3, iclass 19, count 0 2006.285.16:39:20.94#ibcon#read 3, iclass 19, count 0 2006.285.16:39:20.94#ibcon#about to read 4, iclass 19, count 0 2006.285.16:39:20.94#ibcon#read 4, iclass 19, count 0 2006.285.16:39:20.94#ibcon#about to read 5, iclass 19, count 0 2006.285.16:39:20.94#ibcon#read 5, iclass 19, count 0 2006.285.16:39:20.94#ibcon#about to read 6, iclass 19, count 0 2006.285.16:39:20.94#ibcon#read 6, iclass 19, count 0 2006.285.16:39:20.94#ibcon#end of sib2, iclass 19, count 0 2006.285.16:39:20.94#ibcon#*after write, iclass 19, count 0 2006.285.16:39:20.94#ibcon#*before return 0, iclass 19, count 0 2006.285.16:39:20.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:39:20.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:39:20.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.16:39:20.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.16:39:20.94$vck44/vb=8,4 2006.285.16:39:20.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.16:39:20.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.16:39:20.94#ibcon#ireg 11 cls_cnt 2 2006.285.16:39:20.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:39:21.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:39:21.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:39:21.00#ibcon#enter wrdev, iclass 21, count 2 2006.285.16:39:21.00#ibcon#first serial, iclass 21, count 2 2006.285.16:39:21.00#ibcon#enter sib2, iclass 21, count 2 2006.285.16:39:21.00#ibcon#flushed, iclass 21, count 2 2006.285.16:39:21.00#ibcon#about to write, iclass 21, count 2 2006.285.16:39:21.00#ibcon#wrote, iclass 21, count 2 2006.285.16:39:21.00#ibcon#about to read 3, iclass 21, count 2 2006.285.16:39:21.02#ibcon#read 3, iclass 21, count 2 2006.285.16:39:21.02#ibcon#about to read 4, iclass 21, count 2 2006.285.16:39:21.02#ibcon#read 4, iclass 21, count 2 2006.285.16:39:21.02#ibcon#about to read 5, iclass 21, count 2 2006.285.16:39:21.02#ibcon#read 5, iclass 21, count 2 2006.285.16:39:21.02#ibcon#about to read 6, iclass 21, count 2 2006.285.16:39:21.02#ibcon#read 6, iclass 21, count 2 2006.285.16:39:21.02#ibcon#end of sib2, iclass 21, count 2 2006.285.16:39:21.02#ibcon#*mode == 0, iclass 21, count 2 2006.285.16:39:21.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.16:39:21.02#ibcon#[27=AT08-04\r\n] 2006.285.16:39:21.02#ibcon#*before write, iclass 21, count 2 2006.285.16:39:21.02#ibcon#enter sib2, iclass 21, count 2 2006.285.16:39:21.02#ibcon#flushed, iclass 21, count 2 2006.285.16:39:21.02#ibcon#about to write, iclass 21, count 2 2006.285.16:39:21.02#ibcon#wrote, iclass 21, count 2 2006.285.16:39:21.02#ibcon#about to read 3, iclass 21, count 2 2006.285.16:39:21.05#ibcon#read 3, iclass 21, count 2 2006.285.16:39:21.05#ibcon#about to read 4, iclass 21, count 2 2006.285.16:39:21.05#ibcon#read 4, iclass 21, count 2 2006.285.16:39:21.05#ibcon#about to read 5, iclass 21, count 2 2006.285.16:39:21.05#ibcon#read 5, iclass 21, count 2 2006.285.16:39:21.05#ibcon#about to read 6, iclass 21, count 2 2006.285.16:39:21.05#ibcon#read 6, iclass 21, count 2 2006.285.16:39:21.05#ibcon#end of sib2, iclass 21, count 2 2006.285.16:39:21.05#ibcon#*after write, iclass 21, count 2 2006.285.16:39:21.05#ibcon#*before return 0, iclass 21, count 2 2006.285.16:39:21.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:39:21.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:39:21.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.16:39:21.05#ibcon#ireg 7 cls_cnt 0 2006.285.16:39:21.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:39:21.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:39:21.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:39:21.17#ibcon#enter wrdev, iclass 21, count 0 2006.285.16:39:21.17#ibcon#first serial, iclass 21, count 0 2006.285.16:39:21.17#ibcon#enter sib2, iclass 21, count 0 2006.285.16:39:21.17#ibcon#flushed, iclass 21, count 0 2006.285.16:39:21.17#ibcon#about to write, iclass 21, count 0 2006.285.16:39:21.17#ibcon#wrote, iclass 21, count 0 2006.285.16:39:21.17#ibcon#about to read 3, iclass 21, count 0 2006.285.16:39:21.19#ibcon#read 3, iclass 21, count 0 2006.285.16:39:21.19#ibcon#about to read 4, iclass 21, count 0 2006.285.16:39:21.19#ibcon#read 4, iclass 21, count 0 2006.285.16:39:21.19#ibcon#about to read 5, iclass 21, count 0 2006.285.16:39:21.19#ibcon#read 5, iclass 21, count 0 2006.285.16:39:21.19#ibcon#about to read 6, iclass 21, count 0 2006.285.16:39:21.19#ibcon#read 6, iclass 21, count 0 2006.285.16:39:21.19#ibcon#end of sib2, iclass 21, count 0 2006.285.16:39:21.19#ibcon#*mode == 0, iclass 21, count 0 2006.285.16:39:21.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.16:39:21.19#ibcon#[27=USB\r\n] 2006.285.16:39:21.19#ibcon#*before write, iclass 21, count 0 2006.285.16:39:21.19#ibcon#enter sib2, iclass 21, count 0 2006.285.16:39:21.19#ibcon#flushed, iclass 21, count 0 2006.285.16:39:21.19#ibcon#about to write, iclass 21, count 0 2006.285.16:39:21.19#ibcon#wrote, iclass 21, count 0 2006.285.16:39:21.19#ibcon#about to read 3, iclass 21, count 0 2006.285.16:39:21.22#ibcon#read 3, iclass 21, count 0 2006.285.16:39:21.22#ibcon#about to read 4, iclass 21, count 0 2006.285.16:39:21.22#ibcon#read 4, iclass 21, count 0 2006.285.16:39:21.22#ibcon#about to read 5, iclass 21, count 0 2006.285.16:39:21.22#ibcon#read 5, iclass 21, count 0 2006.285.16:39:21.22#ibcon#about to read 6, iclass 21, count 0 2006.285.16:39:21.22#ibcon#read 6, iclass 21, count 0 2006.285.16:39:21.22#ibcon#end of sib2, iclass 21, count 0 2006.285.16:39:21.22#ibcon#*after write, iclass 21, count 0 2006.285.16:39:21.22#ibcon#*before return 0, iclass 21, count 0 2006.285.16:39:21.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:39:21.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:39:21.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.16:39:21.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.16:39:21.22$vck44/vabw=wide 2006.285.16:39:21.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.16:39:21.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.16:39:21.22#ibcon#ireg 8 cls_cnt 0 2006.285.16:39:21.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:39:21.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:39:21.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:39:21.22#ibcon#enter wrdev, iclass 23, count 0 2006.285.16:39:21.22#ibcon#first serial, iclass 23, count 0 2006.285.16:39:21.22#ibcon#enter sib2, iclass 23, count 0 2006.285.16:39:21.22#ibcon#flushed, iclass 23, count 0 2006.285.16:39:21.22#ibcon#about to write, iclass 23, count 0 2006.285.16:39:21.22#ibcon#wrote, iclass 23, count 0 2006.285.16:39:21.22#ibcon#about to read 3, iclass 23, count 0 2006.285.16:39:21.24#ibcon#read 3, iclass 23, count 0 2006.285.16:39:21.24#ibcon#about to read 4, iclass 23, count 0 2006.285.16:39:21.24#ibcon#read 4, iclass 23, count 0 2006.285.16:39:21.24#ibcon#about to read 5, iclass 23, count 0 2006.285.16:39:21.24#ibcon#read 5, iclass 23, count 0 2006.285.16:39:21.24#ibcon#about to read 6, iclass 23, count 0 2006.285.16:39:21.24#ibcon#read 6, iclass 23, count 0 2006.285.16:39:21.24#ibcon#end of sib2, iclass 23, count 0 2006.285.16:39:21.24#ibcon#*mode == 0, iclass 23, count 0 2006.285.16:39:21.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.16:39:21.24#ibcon#[25=BW32\r\n] 2006.285.16:39:21.24#ibcon#*before write, iclass 23, count 0 2006.285.16:39:21.24#ibcon#enter sib2, iclass 23, count 0 2006.285.16:39:21.24#ibcon#flushed, iclass 23, count 0 2006.285.16:39:21.24#ibcon#about to write, iclass 23, count 0 2006.285.16:39:21.24#ibcon#wrote, iclass 23, count 0 2006.285.16:39:21.24#ibcon#about to read 3, iclass 23, count 0 2006.285.16:39:21.27#ibcon#read 3, iclass 23, count 0 2006.285.16:39:21.27#ibcon#about to read 4, iclass 23, count 0 2006.285.16:39:21.27#ibcon#read 4, iclass 23, count 0 2006.285.16:39:21.27#ibcon#about to read 5, iclass 23, count 0 2006.285.16:39:21.27#ibcon#read 5, iclass 23, count 0 2006.285.16:39:21.27#ibcon#about to read 6, iclass 23, count 0 2006.285.16:39:21.27#ibcon#read 6, iclass 23, count 0 2006.285.16:39:21.27#ibcon#end of sib2, iclass 23, count 0 2006.285.16:39:21.27#ibcon#*after write, iclass 23, count 0 2006.285.16:39:21.27#ibcon#*before return 0, iclass 23, count 0 2006.285.16:39:21.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:39:21.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:39:21.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.16:39:21.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.16:39:21.27$vck44/vbbw=wide 2006.285.16:39:21.27#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.16:39:21.27#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.16:39:21.27#ibcon#ireg 8 cls_cnt 0 2006.285.16:39:21.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:39:21.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:39:21.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:39:21.34#ibcon#enter wrdev, iclass 25, count 0 2006.285.16:39:21.34#ibcon#first serial, iclass 25, count 0 2006.285.16:39:21.34#ibcon#enter sib2, iclass 25, count 0 2006.285.16:39:21.34#ibcon#flushed, iclass 25, count 0 2006.285.16:39:21.34#ibcon#about to write, iclass 25, count 0 2006.285.16:39:21.34#ibcon#wrote, iclass 25, count 0 2006.285.16:39:21.34#ibcon#about to read 3, iclass 25, count 0 2006.285.16:39:21.36#ibcon#read 3, iclass 25, count 0 2006.285.16:39:21.36#ibcon#about to read 4, iclass 25, count 0 2006.285.16:39:21.36#ibcon#read 4, iclass 25, count 0 2006.285.16:39:21.36#ibcon#about to read 5, iclass 25, count 0 2006.285.16:39:21.36#ibcon#read 5, iclass 25, count 0 2006.285.16:39:21.36#ibcon#about to read 6, iclass 25, count 0 2006.285.16:39:21.36#ibcon#read 6, iclass 25, count 0 2006.285.16:39:21.36#ibcon#end of sib2, iclass 25, count 0 2006.285.16:39:21.36#ibcon#*mode == 0, iclass 25, count 0 2006.285.16:39:21.36#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.16:39:21.36#ibcon#[27=BW32\r\n] 2006.285.16:39:21.36#ibcon#*before write, iclass 25, count 0 2006.285.16:39:21.36#ibcon#enter sib2, iclass 25, count 0 2006.285.16:39:21.36#ibcon#flushed, iclass 25, count 0 2006.285.16:39:21.36#ibcon#about to write, iclass 25, count 0 2006.285.16:39:21.36#ibcon#wrote, iclass 25, count 0 2006.285.16:39:21.36#ibcon#about to read 3, iclass 25, count 0 2006.285.16:39:21.39#ibcon#read 3, iclass 25, count 0 2006.285.16:39:21.39#ibcon#about to read 4, iclass 25, count 0 2006.285.16:39:21.39#ibcon#read 4, iclass 25, count 0 2006.285.16:39:21.39#ibcon#about to read 5, iclass 25, count 0 2006.285.16:39:21.39#ibcon#read 5, iclass 25, count 0 2006.285.16:39:21.39#ibcon#about to read 6, iclass 25, count 0 2006.285.16:39:21.39#ibcon#read 6, iclass 25, count 0 2006.285.16:39:21.39#ibcon#end of sib2, iclass 25, count 0 2006.285.16:39:21.39#ibcon#*after write, iclass 25, count 0 2006.285.16:39:21.39#ibcon#*before return 0, iclass 25, count 0 2006.285.16:39:21.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:39:21.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:39:21.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.16:39:21.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.16:39:21.39$setupk4/ifdk4 2006.285.16:39:21.39$ifdk4/lo= 2006.285.16:39:21.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.16:39:21.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.16:39:21.40$ifdk4/patch= 2006.285.16:39:21.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.16:39:21.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.16:39:21.40$setupk4/!*+20s 2006.285.16:39:27.96#abcon#<5=/15 0.8 1.8 18.39 921014.9\r\n> 2006.285.16:39:27.98#abcon#{5=INTERFACE CLEAR} 2006.285.16:39:28.04#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:39:32.14#trakl#Source acquired 2006.285.16:39:32.14#flagr#flagr/antenna,acquired 2006.285.16:39:34.89$setupk4/"tpicd 2006.285.16:39:34.89$setupk4/echo=off 2006.285.16:39:34.89$setupk4/xlog=off 2006.285.16:39:34.89:!2006.285.16:40:49 2006.285.16:40:49.00:preob 2006.285.16:40:49.14/onsource/TRACKING 2006.285.16:40:49.14:!2006.285.16:40:59 2006.285.16:40:59.00:"tape 2006.285.16:40:59.00:"st=record 2006.285.16:40:59.00:data_valid=on 2006.285.16:40:59.00:midob 2006.285.16:40:59.14/onsource/TRACKING 2006.285.16:40:59.14/wx/18.35,1014.9,92 2006.285.16:40:59.30/cable/+6.5009E-03 2006.285.16:41:00.39/va/01,07,usb,yes,32,34 2006.285.16:41:00.39/va/02,06,usb,yes,32,32 2006.285.16:41:00.39/va/03,07,usb,yes,31,33 2006.285.16:41:00.39/va/04,06,usb,yes,33,34 2006.285.16:41:00.39/va/05,03,usb,yes,32,32 2006.285.16:41:00.39/va/06,04,usb,yes,29,28 2006.285.16:41:00.39/va/07,04,usb,yes,29,30 2006.285.16:41:00.39/va/08,03,usb,yes,30,37 2006.285.16:41:00.62/valo/01,524.99,yes,locked 2006.285.16:41:00.62/valo/02,534.99,yes,locked 2006.285.16:41:00.62/valo/03,564.99,yes,locked 2006.285.16:41:00.62/valo/04,624.99,yes,locked 2006.285.16:41:00.62/valo/05,734.99,yes,locked 2006.285.16:41:00.62/valo/06,814.99,yes,locked 2006.285.16:41:00.62/valo/07,864.99,yes,locked 2006.285.16:41:00.62/valo/08,884.99,yes,locked 2006.285.16:41:01.71/vb/01,04,usb,yes,30,28 2006.285.16:41:01.71/vb/02,05,usb,yes,29,28 2006.285.16:41:01.71/vb/03,04,usb,yes,29,32 2006.285.16:41:01.71/vb/04,05,usb,yes,30,29 2006.285.16:41:01.71/vb/05,04,usb,yes,26,29 2006.285.16:41:01.71/vb/06,03,usb,yes,38,33 2006.285.16:41:01.71/vb/07,04,usb,yes,30,30 2006.285.16:41:01.71/vb/08,04,usb,yes,28,31 2006.285.16:41:01.94/vblo/01,629.99,yes,locked 2006.285.16:41:01.94/vblo/02,634.99,yes,locked 2006.285.16:41:01.94/vblo/03,649.99,yes,locked 2006.285.16:41:01.94/vblo/04,679.99,yes,locked 2006.285.16:41:01.94/vblo/05,709.99,yes,locked 2006.285.16:41:01.94/vblo/06,719.99,yes,locked 2006.285.16:41:01.94/vblo/07,734.99,yes,locked 2006.285.16:41:01.94/vblo/08,744.99,yes,locked 2006.285.16:41:02.09/vabw/8 2006.285.16:41:02.24/vbbw/8 2006.285.16:41:02.33/xfe/off,on,12.2 2006.285.16:41:02.70/ifatt/23,28,28,28 2006.285.16:41:03.07/fmout-gps/S +2.62E-07 2006.285.16:41:03.09:!2006.285.16:41:49 2006.285.16:41:49.01:data_valid=off 2006.285.16:41:49.01:"et 2006.285.16:41:49.01:!+3s 2006.285.16:41:52.02:"tape 2006.285.16:41:52.02:postob 2006.285.16:41:52.26/cable/+6.5010E-03 2006.285.16:41:52.26/wx/18.32,1014.9,92 2006.285.16:41:52.32/fmout-gps/S +2.64E-07 2006.285.16:41:52.32:scan_name=285-1644,jd0610,220 2006.285.16:41:52.32:source=1044+719,104827.62,714335.9,2000.0,cw 2006.285.16:41:53.14#flagr#flagr/antenna,new-source 2006.285.16:41:53.14:checkk5 2006.285.16:41:53.74/chk_autoobs//k5ts1/ autoobs is running! 2006.285.16:41:54.18/chk_autoobs//k5ts2/ autoobs is running! 2006.285.16:41:54.60/chk_autoobs//k5ts3/ autoobs is running! 2006.285.16:41:55.01/chk_autoobs//k5ts4/ autoobs is running! 2006.285.16:41:55.59/chk_obsdata//k5ts1/T2851640??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.16:41:56.05/chk_obsdata//k5ts2/T2851640??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.16:41:56.45/chk_obsdata//k5ts3/T2851640??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.16:41:56.84/chk_obsdata//k5ts4/T2851640??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.16:41:57.93/k5log//k5ts1_log_newline 2006.285.16:41:58.96/k5log//k5ts2_log_newline 2006.285.16:41:59.81/k5log//k5ts3_log_newline 2006.285.16:42:00.62/k5log//k5ts4_log_newline 2006.285.16:42:00.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.16:42:00.64:setupk4=1 2006.285.16:42:00.64$setupk4/echo=on 2006.285.16:42:00.64$setupk4/pcalon 2006.285.16:42:00.64$pcalon/"no phase cal control is implemented here 2006.285.16:42:00.64$setupk4/"tpicd=stop 2006.285.16:42:00.64$setupk4/"rec=synch_on 2006.285.16:42:00.64$setupk4/"rec_mode=128 2006.285.16:42:00.64$setupk4/!* 2006.285.16:42:00.64$setupk4/recpk4 2006.285.16:42:00.64$recpk4/recpatch= 2006.285.16:42:00.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.16:42:00.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.16:42:00.65$setupk4/vck44 2006.285.16:42:00.65$vck44/valo=1,524.99 2006.285.16:42:00.65#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.16:42:00.65#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.16:42:00.65#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:00.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:42:00.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:42:00.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:42:00.65#ibcon#enter wrdev, iclass 22, count 0 2006.285.16:42:00.65#ibcon#first serial, iclass 22, count 0 2006.285.16:42:00.65#ibcon#enter sib2, iclass 22, count 0 2006.285.16:42:00.65#ibcon#flushed, iclass 22, count 0 2006.285.16:42:00.65#ibcon#about to write, iclass 22, count 0 2006.285.16:42:00.65#ibcon#wrote, iclass 22, count 0 2006.285.16:42:00.65#ibcon#about to read 3, iclass 22, count 0 2006.285.16:42:00.66#ibcon#read 3, iclass 22, count 0 2006.285.16:42:00.66#ibcon#about to read 4, iclass 22, count 0 2006.285.16:42:00.66#ibcon#read 4, iclass 22, count 0 2006.285.16:42:00.66#ibcon#about to read 5, iclass 22, count 0 2006.285.16:42:00.66#ibcon#read 5, iclass 22, count 0 2006.285.16:42:00.66#ibcon#about to read 6, iclass 22, count 0 2006.285.16:42:00.66#ibcon#read 6, iclass 22, count 0 2006.285.16:42:00.66#ibcon#end of sib2, iclass 22, count 0 2006.285.16:42:00.66#ibcon#*mode == 0, iclass 22, count 0 2006.285.16:42:00.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.16:42:00.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.16:42:00.66#ibcon#*before write, iclass 22, count 0 2006.285.16:42:00.66#ibcon#enter sib2, iclass 22, count 0 2006.285.16:42:00.66#ibcon#flushed, iclass 22, count 0 2006.285.16:42:00.66#ibcon#about to write, iclass 22, count 0 2006.285.16:42:00.66#ibcon#wrote, iclass 22, count 0 2006.285.16:42:00.66#ibcon#about to read 3, iclass 22, count 0 2006.285.16:42:00.71#ibcon#read 3, iclass 22, count 0 2006.285.16:42:00.71#ibcon#about to read 4, iclass 22, count 0 2006.285.16:42:00.71#ibcon#read 4, iclass 22, count 0 2006.285.16:42:00.71#ibcon#about to read 5, iclass 22, count 0 2006.285.16:42:00.71#ibcon#read 5, iclass 22, count 0 2006.285.16:42:00.71#ibcon#about to read 6, iclass 22, count 0 2006.285.16:42:00.71#ibcon#read 6, iclass 22, count 0 2006.285.16:42:00.71#ibcon#end of sib2, iclass 22, count 0 2006.285.16:42:00.71#ibcon#*after write, iclass 22, count 0 2006.285.16:42:00.71#ibcon#*before return 0, iclass 22, count 0 2006.285.16:42:00.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:42:00.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:42:00.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.16:42:00.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.16:42:00.71$vck44/va=1,7 2006.285.16:42:00.71#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.16:42:00.71#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.16:42:00.71#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:00.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:42:00.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:42:00.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:42:00.71#ibcon#enter wrdev, iclass 24, count 2 2006.285.16:42:00.71#ibcon#first serial, iclass 24, count 2 2006.285.16:42:00.71#ibcon#enter sib2, iclass 24, count 2 2006.285.16:42:00.71#ibcon#flushed, iclass 24, count 2 2006.285.16:42:00.71#ibcon#about to write, iclass 24, count 2 2006.285.16:42:00.71#ibcon#wrote, iclass 24, count 2 2006.285.16:42:00.71#ibcon#about to read 3, iclass 24, count 2 2006.285.16:42:00.73#ibcon#read 3, iclass 24, count 2 2006.285.16:42:00.73#ibcon#about to read 4, iclass 24, count 2 2006.285.16:42:00.73#ibcon#read 4, iclass 24, count 2 2006.285.16:42:00.73#ibcon#about to read 5, iclass 24, count 2 2006.285.16:42:00.73#ibcon#read 5, iclass 24, count 2 2006.285.16:42:00.73#ibcon#about to read 6, iclass 24, count 2 2006.285.16:42:00.73#ibcon#read 6, iclass 24, count 2 2006.285.16:42:00.73#ibcon#end of sib2, iclass 24, count 2 2006.285.16:42:00.73#ibcon#*mode == 0, iclass 24, count 2 2006.285.16:42:00.73#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.16:42:00.73#ibcon#[25=AT01-07\r\n] 2006.285.16:42:00.73#ibcon#*before write, iclass 24, count 2 2006.285.16:42:00.73#ibcon#enter sib2, iclass 24, count 2 2006.285.16:42:00.73#ibcon#flushed, iclass 24, count 2 2006.285.16:42:00.73#ibcon#about to write, iclass 24, count 2 2006.285.16:42:00.73#ibcon#wrote, iclass 24, count 2 2006.285.16:42:00.73#ibcon#about to read 3, iclass 24, count 2 2006.285.16:42:00.76#ibcon#read 3, iclass 24, count 2 2006.285.16:42:00.76#ibcon#about to read 4, iclass 24, count 2 2006.285.16:42:00.76#ibcon#read 4, iclass 24, count 2 2006.285.16:42:00.76#ibcon#about to read 5, iclass 24, count 2 2006.285.16:42:00.76#ibcon#read 5, iclass 24, count 2 2006.285.16:42:00.76#ibcon#about to read 6, iclass 24, count 2 2006.285.16:42:00.76#ibcon#read 6, iclass 24, count 2 2006.285.16:42:00.76#ibcon#end of sib2, iclass 24, count 2 2006.285.16:42:00.76#ibcon#*after write, iclass 24, count 2 2006.285.16:42:00.76#ibcon#*before return 0, iclass 24, count 2 2006.285.16:42:00.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:42:00.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:42:00.76#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.16:42:00.76#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:00.76#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:42:00.88#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:42:00.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:42:00.88#ibcon#enter wrdev, iclass 24, count 0 2006.285.16:42:00.88#ibcon#first serial, iclass 24, count 0 2006.285.16:42:00.88#ibcon#enter sib2, iclass 24, count 0 2006.285.16:42:00.88#ibcon#flushed, iclass 24, count 0 2006.285.16:42:00.88#ibcon#about to write, iclass 24, count 0 2006.285.16:42:00.88#ibcon#wrote, iclass 24, count 0 2006.285.16:42:00.88#ibcon#about to read 3, iclass 24, count 0 2006.285.16:42:00.90#ibcon#read 3, iclass 24, count 0 2006.285.16:42:00.90#ibcon#about to read 4, iclass 24, count 0 2006.285.16:42:00.90#ibcon#read 4, iclass 24, count 0 2006.285.16:42:00.90#ibcon#about to read 5, iclass 24, count 0 2006.285.16:42:00.90#ibcon#read 5, iclass 24, count 0 2006.285.16:42:00.90#ibcon#about to read 6, iclass 24, count 0 2006.285.16:42:00.90#ibcon#read 6, iclass 24, count 0 2006.285.16:42:00.90#ibcon#end of sib2, iclass 24, count 0 2006.285.16:42:00.90#ibcon#*mode == 0, iclass 24, count 0 2006.285.16:42:00.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.16:42:00.90#ibcon#[25=USB\r\n] 2006.285.16:42:00.90#ibcon#*before write, iclass 24, count 0 2006.285.16:42:00.90#ibcon#enter sib2, iclass 24, count 0 2006.285.16:42:00.90#ibcon#flushed, iclass 24, count 0 2006.285.16:42:00.90#ibcon#about to write, iclass 24, count 0 2006.285.16:42:00.90#ibcon#wrote, iclass 24, count 0 2006.285.16:42:00.90#ibcon#about to read 3, iclass 24, count 0 2006.285.16:42:00.93#ibcon#read 3, iclass 24, count 0 2006.285.16:42:00.93#ibcon#about to read 4, iclass 24, count 0 2006.285.16:42:00.93#ibcon#read 4, iclass 24, count 0 2006.285.16:42:00.93#ibcon#about to read 5, iclass 24, count 0 2006.285.16:42:00.93#ibcon#read 5, iclass 24, count 0 2006.285.16:42:00.93#ibcon#about to read 6, iclass 24, count 0 2006.285.16:42:00.93#ibcon#read 6, iclass 24, count 0 2006.285.16:42:00.93#ibcon#end of sib2, iclass 24, count 0 2006.285.16:42:00.93#ibcon#*after write, iclass 24, count 0 2006.285.16:42:00.93#ibcon#*before return 0, iclass 24, count 0 2006.285.16:42:00.93#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:42:00.93#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:42:00.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.16:42:00.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.16:42:00.93$vck44/valo=2,534.99 2006.285.16:42:00.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.16:42:00.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.16:42:00.93#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:00.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:42:00.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:42:00.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:42:00.93#ibcon#enter wrdev, iclass 26, count 0 2006.285.16:42:00.93#ibcon#first serial, iclass 26, count 0 2006.285.16:42:00.93#ibcon#enter sib2, iclass 26, count 0 2006.285.16:42:00.93#ibcon#flushed, iclass 26, count 0 2006.285.16:42:00.93#ibcon#about to write, iclass 26, count 0 2006.285.16:42:00.93#ibcon#wrote, iclass 26, count 0 2006.285.16:42:00.93#ibcon#about to read 3, iclass 26, count 0 2006.285.16:42:00.95#ibcon#read 3, iclass 26, count 0 2006.285.16:42:00.95#ibcon#about to read 4, iclass 26, count 0 2006.285.16:42:00.95#ibcon#read 4, iclass 26, count 0 2006.285.16:42:00.95#ibcon#about to read 5, iclass 26, count 0 2006.285.16:42:00.95#ibcon#read 5, iclass 26, count 0 2006.285.16:42:00.95#ibcon#about to read 6, iclass 26, count 0 2006.285.16:42:00.95#ibcon#read 6, iclass 26, count 0 2006.285.16:42:00.95#ibcon#end of sib2, iclass 26, count 0 2006.285.16:42:00.95#ibcon#*mode == 0, iclass 26, count 0 2006.285.16:42:00.95#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.16:42:00.95#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.16:42:00.95#ibcon#*before write, iclass 26, count 0 2006.285.16:42:00.95#ibcon#enter sib2, iclass 26, count 0 2006.285.16:42:00.95#ibcon#flushed, iclass 26, count 0 2006.285.16:42:00.95#ibcon#about to write, iclass 26, count 0 2006.285.16:42:00.95#ibcon#wrote, iclass 26, count 0 2006.285.16:42:00.95#ibcon#about to read 3, iclass 26, count 0 2006.285.16:42:00.99#ibcon#read 3, iclass 26, count 0 2006.285.16:42:00.99#ibcon#about to read 4, iclass 26, count 0 2006.285.16:42:00.99#ibcon#read 4, iclass 26, count 0 2006.285.16:42:00.99#ibcon#about to read 5, iclass 26, count 0 2006.285.16:42:00.99#ibcon#read 5, iclass 26, count 0 2006.285.16:42:00.99#ibcon#about to read 6, iclass 26, count 0 2006.285.16:42:00.99#ibcon#read 6, iclass 26, count 0 2006.285.16:42:00.99#ibcon#end of sib2, iclass 26, count 0 2006.285.16:42:00.99#ibcon#*after write, iclass 26, count 0 2006.285.16:42:00.99#ibcon#*before return 0, iclass 26, count 0 2006.285.16:42:00.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:42:00.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:42:00.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.16:42:00.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.16:42:00.99$vck44/va=2,6 2006.285.16:42:00.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.16:42:00.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.16:42:00.99#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:00.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:42:01.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:42:01.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:42:01.05#ibcon#enter wrdev, iclass 28, count 2 2006.285.16:42:01.05#ibcon#first serial, iclass 28, count 2 2006.285.16:42:01.05#ibcon#enter sib2, iclass 28, count 2 2006.285.16:42:01.05#ibcon#flushed, iclass 28, count 2 2006.285.16:42:01.05#ibcon#about to write, iclass 28, count 2 2006.285.16:42:01.05#ibcon#wrote, iclass 28, count 2 2006.285.16:42:01.05#ibcon#about to read 3, iclass 28, count 2 2006.285.16:42:01.07#ibcon#read 3, iclass 28, count 2 2006.285.16:42:01.07#ibcon#about to read 4, iclass 28, count 2 2006.285.16:42:01.07#ibcon#read 4, iclass 28, count 2 2006.285.16:42:01.07#ibcon#about to read 5, iclass 28, count 2 2006.285.16:42:01.07#ibcon#read 5, iclass 28, count 2 2006.285.16:42:01.07#ibcon#about to read 6, iclass 28, count 2 2006.285.16:42:01.07#ibcon#read 6, iclass 28, count 2 2006.285.16:42:01.07#ibcon#end of sib2, iclass 28, count 2 2006.285.16:42:01.07#ibcon#*mode == 0, iclass 28, count 2 2006.285.16:42:01.07#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.16:42:01.07#ibcon#[25=AT02-06\r\n] 2006.285.16:42:01.07#ibcon#*before write, iclass 28, count 2 2006.285.16:42:01.07#ibcon#enter sib2, iclass 28, count 2 2006.285.16:42:01.07#ibcon#flushed, iclass 28, count 2 2006.285.16:42:01.07#ibcon#about to write, iclass 28, count 2 2006.285.16:42:01.07#ibcon#wrote, iclass 28, count 2 2006.285.16:42:01.07#ibcon#about to read 3, iclass 28, count 2 2006.285.16:42:01.10#ibcon#read 3, iclass 28, count 2 2006.285.16:42:01.10#ibcon#about to read 4, iclass 28, count 2 2006.285.16:42:01.10#ibcon#read 4, iclass 28, count 2 2006.285.16:42:01.10#ibcon#about to read 5, iclass 28, count 2 2006.285.16:42:01.10#ibcon#read 5, iclass 28, count 2 2006.285.16:42:01.10#ibcon#about to read 6, iclass 28, count 2 2006.285.16:42:01.10#ibcon#read 6, iclass 28, count 2 2006.285.16:42:01.10#ibcon#end of sib2, iclass 28, count 2 2006.285.16:42:01.10#ibcon#*after write, iclass 28, count 2 2006.285.16:42:01.10#ibcon#*before return 0, iclass 28, count 2 2006.285.16:42:01.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:42:01.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:42:01.10#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.16:42:01.10#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:01.10#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:42:01.22#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:42:01.22#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:42:01.22#ibcon#enter wrdev, iclass 28, count 0 2006.285.16:42:01.22#ibcon#first serial, iclass 28, count 0 2006.285.16:42:01.22#ibcon#enter sib2, iclass 28, count 0 2006.285.16:42:01.22#ibcon#flushed, iclass 28, count 0 2006.285.16:42:01.22#ibcon#about to write, iclass 28, count 0 2006.285.16:42:01.22#ibcon#wrote, iclass 28, count 0 2006.285.16:42:01.22#ibcon#about to read 3, iclass 28, count 0 2006.285.16:42:01.24#ibcon#read 3, iclass 28, count 0 2006.285.16:42:01.24#ibcon#about to read 4, iclass 28, count 0 2006.285.16:42:01.24#ibcon#read 4, iclass 28, count 0 2006.285.16:42:01.24#ibcon#about to read 5, iclass 28, count 0 2006.285.16:42:01.24#ibcon#read 5, iclass 28, count 0 2006.285.16:42:01.24#ibcon#about to read 6, iclass 28, count 0 2006.285.16:42:01.24#ibcon#read 6, iclass 28, count 0 2006.285.16:42:01.24#ibcon#end of sib2, iclass 28, count 0 2006.285.16:42:01.24#ibcon#*mode == 0, iclass 28, count 0 2006.285.16:42:01.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.16:42:01.24#ibcon#[25=USB\r\n] 2006.285.16:42:01.24#ibcon#*before write, iclass 28, count 0 2006.285.16:42:01.24#ibcon#enter sib2, iclass 28, count 0 2006.285.16:42:01.24#ibcon#flushed, iclass 28, count 0 2006.285.16:42:01.24#ibcon#about to write, iclass 28, count 0 2006.285.16:42:01.24#ibcon#wrote, iclass 28, count 0 2006.285.16:42:01.24#ibcon#about to read 3, iclass 28, count 0 2006.285.16:42:01.27#ibcon#read 3, iclass 28, count 0 2006.285.16:42:01.27#ibcon#about to read 4, iclass 28, count 0 2006.285.16:42:01.27#ibcon#read 4, iclass 28, count 0 2006.285.16:42:01.27#ibcon#about to read 5, iclass 28, count 0 2006.285.16:42:01.27#ibcon#read 5, iclass 28, count 0 2006.285.16:42:01.27#ibcon#about to read 6, iclass 28, count 0 2006.285.16:42:01.27#ibcon#read 6, iclass 28, count 0 2006.285.16:42:01.27#ibcon#end of sib2, iclass 28, count 0 2006.285.16:42:01.27#ibcon#*after write, iclass 28, count 0 2006.285.16:42:01.27#ibcon#*before return 0, iclass 28, count 0 2006.285.16:42:01.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:42:01.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:42:01.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.16:42:01.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.16:42:01.27$vck44/valo=3,564.99 2006.285.16:42:01.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.16:42:01.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.16:42:01.27#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:01.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:42:01.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:42:01.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:42:01.27#ibcon#enter wrdev, iclass 30, count 0 2006.285.16:42:01.27#ibcon#first serial, iclass 30, count 0 2006.285.16:42:01.27#ibcon#enter sib2, iclass 30, count 0 2006.285.16:42:01.27#ibcon#flushed, iclass 30, count 0 2006.285.16:42:01.27#ibcon#about to write, iclass 30, count 0 2006.285.16:42:01.27#ibcon#wrote, iclass 30, count 0 2006.285.16:42:01.27#ibcon#about to read 3, iclass 30, count 0 2006.285.16:42:01.93#ibcon#read 3, iclass 30, count 0 2006.285.16:42:01.93#ibcon#about to read 4, iclass 30, count 0 2006.285.16:42:01.93#ibcon#read 4, iclass 30, count 0 2006.285.16:42:01.93#ibcon#about to read 5, iclass 30, count 0 2006.285.16:42:01.93#ibcon#read 5, iclass 30, count 0 2006.285.16:42:01.93#ibcon#about to read 6, iclass 30, count 0 2006.285.16:42:01.93#ibcon#read 6, iclass 30, count 0 2006.285.16:42:01.93#ibcon#end of sib2, iclass 30, count 0 2006.285.16:42:01.93#ibcon#*mode == 0, iclass 30, count 0 2006.285.16:42:01.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.16:42:01.93#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.16:42:01.93#ibcon#*before write, iclass 30, count 0 2006.285.16:42:01.93#ibcon#enter sib2, iclass 30, count 0 2006.285.16:42:01.93#ibcon#flushed, iclass 30, count 0 2006.285.16:42:01.93#ibcon#about to write, iclass 30, count 0 2006.285.16:42:01.93#ibcon#wrote, iclass 30, count 0 2006.285.16:42:01.93#ibcon#about to read 3, iclass 30, count 0 2006.285.16:42:01.97#ibcon#read 3, iclass 30, count 0 2006.285.16:42:01.97#ibcon#about to read 4, iclass 30, count 0 2006.285.16:42:01.97#ibcon#read 4, iclass 30, count 0 2006.285.16:42:01.97#ibcon#about to read 5, iclass 30, count 0 2006.285.16:42:01.97#ibcon#read 5, iclass 30, count 0 2006.285.16:42:01.97#ibcon#about to read 6, iclass 30, count 0 2006.285.16:42:01.97#ibcon#read 6, iclass 30, count 0 2006.285.16:42:01.97#ibcon#end of sib2, iclass 30, count 0 2006.285.16:42:01.97#ibcon#*after write, iclass 30, count 0 2006.285.16:42:01.97#ibcon#*before return 0, iclass 30, count 0 2006.285.16:42:01.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:42:01.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:42:01.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.16:42:01.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.16:42:01.97$vck44/va=3,7 2006.285.16:42:01.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.16:42:01.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.16:42:01.97#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:01.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:42:01.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:42:01.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:42:01.97#ibcon#enter wrdev, iclass 32, count 2 2006.285.16:42:01.97#ibcon#first serial, iclass 32, count 2 2006.285.16:42:01.97#ibcon#enter sib2, iclass 32, count 2 2006.285.16:42:01.97#ibcon#flushed, iclass 32, count 2 2006.285.16:42:01.97#ibcon#about to write, iclass 32, count 2 2006.285.16:42:01.97#ibcon#wrote, iclass 32, count 2 2006.285.16:42:01.97#ibcon#about to read 3, iclass 32, count 2 2006.285.16:42:01.99#ibcon#read 3, iclass 32, count 2 2006.285.16:42:01.99#ibcon#about to read 4, iclass 32, count 2 2006.285.16:42:01.99#ibcon#read 4, iclass 32, count 2 2006.285.16:42:01.99#ibcon#about to read 5, iclass 32, count 2 2006.285.16:42:01.99#ibcon#read 5, iclass 32, count 2 2006.285.16:42:01.99#ibcon#about to read 6, iclass 32, count 2 2006.285.16:42:01.99#ibcon#read 6, iclass 32, count 2 2006.285.16:42:01.99#ibcon#end of sib2, iclass 32, count 2 2006.285.16:42:01.99#ibcon#*mode == 0, iclass 32, count 2 2006.285.16:42:01.99#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.16:42:01.99#ibcon#[25=AT03-07\r\n] 2006.285.16:42:01.99#ibcon#*before write, iclass 32, count 2 2006.285.16:42:01.99#ibcon#enter sib2, iclass 32, count 2 2006.285.16:42:01.99#ibcon#flushed, iclass 32, count 2 2006.285.16:42:01.99#ibcon#about to write, iclass 32, count 2 2006.285.16:42:01.99#ibcon#wrote, iclass 32, count 2 2006.285.16:42:01.99#ibcon#about to read 3, iclass 32, count 2 2006.285.16:42:02.02#ibcon#read 3, iclass 32, count 2 2006.285.16:42:02.02#ibcon#about to read 4, iclass 32, count 2 2006.285.16:42:02.02#ibcon#read 4, iclass 32, count 2 2006.285.16:42:02.02#ibcon#about to read 5, iclass 32, count 2 2006.285.16:42:02.02#ibcon#read 5, iclass 32, count 2 2006.285.16:42:02.02#ibcon#about to read 6, iclass 32, count 2 2006.285.16:42:02.02#ibcon#read 6, iclass 32, count 2 2006.285.16:42:02.02#ibcon#end of sib2, iclass 32, count 2 2006.285.16:42:02.02#ibcon#*after write, iclass 32, count 2 2006.285.16:42:02.02#ibcon#*before return 0, iclass 32, count 2 2006.285.16:42:02.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:42:02.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:42:02.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.16:42:02.02#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:02.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:42:02.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:42:02.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:42:02.14#ibcon#enter wrdev, iclass 32, count 0 2006.285.16:42:02.14#ibcon#first serial, iclass 32, count 0 2006.285.16:42:02.14#ibcon#enter sib2, iclass 32, count 0 2006.285.16:42:02.14#ibcon#flushed, iclass 32, count 0 2006.285.16:42:02.14#ibcon#about to write, iclass 32, count 0 2006.285.16:42:02.14#ibcon#wrote, iclass 32, count 0 2006.285.16:42:02.14#ibcon#about to read 3, iclass 32, count 0 2006.285.16:42:02.16#ibcon#read 3, iclass 32, count 0 2006.285.16:42:02.16#ibcon#about to read 4, iclass 32, count 0 2006.285.16:42:02.16#ibcon#read 4, iclass 32, count 0 2006.285.16:42:02.16#ibcon#about to read 5, iclass 32, count 0 2006.285.16:42:02.16#ibcon#read 5, iclass 32, count 0 2006.285.16:42:02.16#ibcon#about to read 6, iclass 32, count 0 2006.285.16:42:02.16#ibcon#read 6, iclass 32, count 0 2006.285.16:42:02.16#ibcon#end of sib2, iclass 32, count 0 2006.285.16:42:02.16#ibcon#*mode == 0, iclass 32, count 0 2006.285.16:42:02.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.16:42:02.16#ibcon#[25=USB\r\n] 2006.285.16:42:02.16#ibcon#*before write, iclass 32, count 0 2006.285.16:42:02.16#ibcon#enter sib2, iclass 32, count 0 2006.285.16:42:02.16#ibcon#flushed, iclass 32, count 0 2006.285.16:42:02.16#ibcon#about to write, iclass 32, count 0 2006.285.16:42:02.16#ibcon#wrote, iclass 32, count 0 2006.285.16:42:02.16#ibcon#about to read 3, iclass 32, count 0 2006.285.16:42:02.19#ibcon#read 3, iclass 32, count 0 2006.285.16:42:02.19#ibcon#about to read 4, iclass 32, count 0 2006.285.16:42:02.19#ibcon#read 4, iclass 32, count 0 2006.285.16:42:02.19#ibcon#about to read 5, iclass 32, count 0 2006.285.16:42:02.19#ibcon#read 5, iclass 32, count 0 2006.285.16:42:02.19#ibcon#about to read 6, iclass 32, count 0 2006.285.16:42:02.19#ibcon#read 6, iclass 32, count 0 2006.285.16:42:02.19#ibcon#end of sib2, iclass 32, count 0 2006.285.16:42:02.19#ibcon#*after write, iclass 32, count 0 2006.285.16:42:02.19#ibcon#*before return 0, iclass 32, count 0 2006.285.16:42:02.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:42:02.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:42:02.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.16:42:02.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.16:42:02.19$vck44/valo=4,624.99 2006.285.16:42:02.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.16:42:02.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.16:42:02.19#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:02.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:42:02.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:42:02.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:42:02.19#ibcon#enter wrdev, iclass 34, count 0 2006.285.16:42:02.19#ibcon#first serial, iclass 34, count 0 2006.285.16:42:02.19#ibcon#enter sib2, iclass 34, count 0 2006.285.16:42:02.19#ibcon#flushed, iclass 34, count 0 2006.285.16:42:02.19#ibcon#about to write, iclass 34, count 0 2006.285.16:42:02.19#ibcon#wrote, iclass 34, count 0 2006.285.16:42:02.19#ibcon#about to read 3, iclass 34, count 0 2006.285.16:42:02.49#ibcon#read 3, iclass 34, count 0 2006.285.16:42:02.49#ibcon#about to read 4, iclass 34, count 0 2006.285.16:42:02.49#ibcon#read 4, iclass 34, count 0 2006.285.16:42:02.49#ibcon#about to read 5, iclass 34, count 0 2006.285.16:42:02.49#ibcon#read 5, iclass 34, count 0 2006.285.16:42:02.49#ibcon#about to read 6, iclass 34, count 0 2006.285.16:42:02.49#ibcon#read 6, iclass 34, count 0 2006.285.16:42:02.49#ibcon#end of sib2, iclass 34, count 0 2006.285.16:42:02.49#ibcon#*mode == 0, iclass 34, count 0 2006.285.16:42:02.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.16:42:02.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.16:42:02.49#ibcon#*before write, iclass 34, count 0 2006.285.16:42:02.49#ibcon#enter sib2, iclass 34, count 0 2006.285.16:42:02.49#ibcon#flushed, iclass 34, count 0 2006.285.16:42:02.49#ibcon#about to write, iclass 34, count 0 2006.285.16:42:02.49#ibcon#wrote, iclass 34, count 0 2006.285.16:42:02.49#ibcon#about to read 3, iclass 34, count 0 2006.285.16:42:02.53#ibcon#read 3, iclass 34, count 0 2006.285.16:42:02.53#ibcon#about to read 4, iclass 34, count 0 2006.285.16:42:02.53#ibcon#read 4, iclass 34, count 0 2006.285.16:42:02.53#ibcon#about to read 5, iclass 34, count 0 2006.285.16:42:02.53#ibcon#read 5, iclass 34, count 0 2006.285.16:42:02.53#ibcon#about to read 6, iclass 34, count 0 2006.285.16:42:02.53#ibcon#read 6, iclass 34, count 0 2006.285.16:42:02.53#ibcon#end of sib2, iclass 34, count 0 2006.285.16:42:02.53#ibcon#*after write, iclass 34, count 0 2006.285.16:42:02.53#ibcon#*before return 0, iclass 34, count 0 2006.285.16:42:02.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:42:02.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:42:02.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.16:42:02.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.16:42:02.53$vck44/va=4,6 2006.285.16:42:02.53#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.16:42:02.53#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.16:42:02.53#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:02.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:42:02.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:42:02.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:42:02.53#ibcon#enter wrdev, iclass 36, count 2 2006.285.16:42:02.53#ibcon#first serial, iclass 36, count 2 2006.285.16:42:02.53#ibcon#enter sib2, iclass 36, count 2 2006.285.16:42:02.53#ibcon#flushed, iclass 36, count 2 2006.285.16:42:02.53#ibcon#about to write, iclass 36, count 2 2006.285.16:42:02.53#ibcon#wrote, iclass 36, count 2 2006.285.16:42:02.53#ibcon#about to read 3, iclass 36, count 2 2006.285.16:42:02.55#ibcon#read 3, iclass 36, count 2 2006.285.16:42:02.55#ibcon#about to read 4, iclass 36, count 2 2006.285.16:42:02.55#ibcon#read 4, iclass 36, count 2 2006.285.16:42:02.55#ibcon#about to read 5, iclass 36, count 2 2006.285.16:42:02.55#ibcon#read 5, iclass 36, count 2 2006.285.16:42:02.55#ibcon#about to read 6, iclass 36, count 2 2006.285.16:42:02.55#ibcon#read 6, iclass 36, count 2 2006.285.16:42:02.55#ibcon#end of sib2, iclass 36, count 2 2006.285.16:42:02.55#ibcon#*mode == 0, iclass 36, count 2 2006.285.16:42:02.55#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.16:42:02.55#ibcon#[25=AT04-06\r\n] 2006.285.16:42:02.55#ibcon#*before write, iclass 36, count 2 2006.285.16:42:02.55#ibcon#enter sib2, iclass 36, count 2 2006.285.16:42:02.55#ibcon#flushed, iclass 36, count 2 2006.285.16:42:02.55#ibcon#about to write, iclass 36, count 2 2006.285.16:42:02.55#ibcon#wrote, iclass 36, count 2 2006.285.16:42:02.55#ibcon#about to read 3, iclass 36, count 2 2006.285.16:42:02.58#ibcon#read 3, iclass 36, count 2 2006.285.16:42:02.58#ibcon#about to read 4, iclass 36, count 2 2006.285.16:42:02.58#ibcon#read 4, iclass 36, count 2 2006.285.16:42:02.58#ibcon#about to read 5, iclass 36, count 2 2006.285.16:42:02.58#ibcon#read 5, iclass 36, count 2 2006.285.16:42:02.58#ibcon#about to read 6, iclass 36, count 2 2006.285.16:42:02.58#ibcon#read 6, iclass 36, count 2 2006.285.16:42:02.58#ibcon#end of sib2, iclass 36, count 2 2006.285.16:42:02.58#ibcon#*after write, iclass 36, count 2 2006.285.16:42:02.58#ibcon#*before return 0, iclass 36, count 2 2006.285.16:42:02.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:42:02.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:42:02.58#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.16:42:02.58#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:02.58#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:42:02.70#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:42:02.70#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:42:02.70#ibcon#enter wrdev, iclass 36, count 0 2006.285.16:42:02.70#ibcon#first serial, iclass 36, count 0 2006.285.16:42:02.70#ibcon#enter sib2, iclass 36, count 0 2006.285.16:42:02.70#ibcon#flushed, iclass 36, count 0 2006.285.16:42:02.70#ibcon#about to write, iclass 36, count 0 2006.285.16:42:02.70#ibcon#wrote, iclass 36, count 0 2006.285.16:42:02.70#ibcon#about to read 3, iclass 36, count 0 2006.285.16:42:02.72#ibcon#read 3, iclass 36, count 0 2006.285.16:42:02.72#ibcon#about to read 4, iclass 36, count 0 2006.285.16:42:02.72#ibcon#read 4, iclass 36, count 0 2006.285.16:42:02.72#ibcon#about to read 5, iclass 36, count 0 2006.285.16:42:02.72#ibcon#read 5, iclass 36, count 0 2006.285.16:42:02.72#ibcon#about to read 6, iclass 36, count 0 2006.285.16:42:02.72#ibcon#read 6, iclass 36, count 0 2006.285.16:42:02.72#ibcon#end of sib2, iclass 36, count 0 2006.285.16:42:02.72#ibcon#*mode == 0, iclass 36, count 0 2006.285.16:42:02.72#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.16:42:02.72#ibcon#[25=USB\r\n] 2006.285.16:42:02.72#ibcon#*before write, iclass 36, count 0 2006.285.16:42:02.72#ibcon#enter sib2, iclass 36, count 0 2006.285.16:42:02.72#ibcon#flushed, iclass 36, count 0 2006.285.16:42:02.72#ibcon#about to write, iclass 36, count 0 2006.285.16:42:02.72#ibcon#wrote, iclass 36, count 0 2006.285.16:42:02.72#ibcon#about to read 3, iclass 36, count 0 2006.285.16:42:02.75#ibcon#read 3, iclass 36, count 0 2006.285.16:42:02.75#ibcon#about to read 4, iclass 36, count 0 2006.285.16:42:02.75#ibcon#read 4, iclass 36, count 0 2006.285.16:42:02.75#ibcon#about to read 5, iclass 36, count 0 2006.285.16:42:02.75#ibcon#read 5, iclass 36, count 0 2006.285.16:42:02.75#ibcon#about to read 6, iclass 36, count 0 2006.285.16:42:02.75#ibcon#read 6, iclass 36, count 0 2006.285.16:42:02.75#ibcon#end of sib2, iclass 36, count 0 2006.285.16:42:02.75#ibcon#*after write, iclass 36, count 0 2006.285.16:42:02.75#ibcon#*before return 0, iclass 36, count 0 2006.285.16:42:02.75#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:42:02.75#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:42:02.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.16:42:02.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.16:42:02.75$vck44/valo=5,734.99 2006.285.16:42:02.75#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.16:42:02.75#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.16:42:02.75#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:02.75#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:42:02.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:42:02.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:42:02.75#ibcon#enter wrdev, iclass 38, count 0 2006.285.16:42:02.75#ibcon#first serial, iclass 38, count 0 2006.285.16:42:02.75#ibcon#enter sib2, iclass 38, count 0 2006.285.16:42:02.75#ibcon#flushed, iclass 38, count 0 2006.285.16:42:02.75#ibcon#about to write, iclass 38, count 0 2006.285.16:42:02.75#ibcon#wrote, iclass 38, count 0 2006.285.16:42:02.75#ibcon#about to read 3, iclass 38, count 0 2006.285.16:42:02.77#ibcon#read 3, iclass 38, count 0 2006.285.16:42:02.77#ibcon#about to read 4, iclass 38, count 0 2006.285.16:42:02.77#ibcon#read 4, iclass 38, count 0 2006.285.16:42:02.77#ibcon#about to read 5, iclass 38, count 0 2006.285.16:42:02.77#ibcon#read 5, iclass 38, count 0 2006.285.16:42:02.77#ibcon#about to read 6, iclass 38, count 0 2006.285.16:42:02.77#ibcon#read 6, iclass 38, count 0 2006.285.16:42:02.77#ibcon#end of sib2, iclass 38, count 0 2006.285.16:42:02.77#ibcon#*mode == 0, iclass 38, count 0 2006.285.16:42:02.77#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.16:42:02.77#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.16:42:02.77#ibcon#*before write, iclass 38, count 0 2006.285.16:42:02.77#ibcon#enter sib2, iclass 38, count 0 2006.285.16:42:02.77#ibcon#flushed, iclass 38, count 0 2006.285.16:42:02.77#ibcon#about to write, iclass 38, count 0 2006.285.16:42:02.77#ibcon#wrote, iclass 38, count 0 2006.285.16:42:02.77#ibcon#about to read 3, iclass 38, count 0 2006.285.16:42:02.81#ibcon#read 3, iclass 38, count 0 2006.285.16:42:02.81#ibcon#about to read 4, iclass 38, count 0 2006.285.16:42:02.81#ibcon#read 4, iclass 38, count 0 2006.285.16:42:02.81#ibcon#about to read 5, iclass 38, count 0 2006.285.16:42:02.81#ibcon#read 5, iclass 38, count 0 2006.285.16:42:02.81#ibcon#about to read 6, iclass 38, count 0 2006.285.16:42:02.81#ibcon#read 6, iclass 38, count 0 2006.285.16:42:02.81#ibcon#end of sib2, iclass 38, count 0 2006.285.16:42:02.81#ibcon#*after write, iclass 38, count 0 2006.285.16:42:02.81#ibcon#*before return 0, iclass 38, count 0 2006.285.16:42:02.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:42:02.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:42:02.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.16:42:02.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.16:42:02.81$vck44/va=5,3 2006.285.16:42:02.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.16:42:02.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.16:42:02.81#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:02.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:42:02.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:42:02.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:42:02.87#ibcon#enter wrdev, iclass 40, count 2 2006.285.16:42:02.87#ibcon#first serial, iclass 40, count 2 2006.285.16:42:02.87#ibcon#enter sib2, iclass 40, count 2 2006.285.16:42:02.87#ibcon#flushed, iclass 40, count 2 2006.285.16:42:02.87#ibcon#about to write, iclass 40, count 2 2006.285.16:42:02.87#ibcon#wrote, iclass 40, count 2 2006.285.16:42:02.87#ibcon#about to read 3, iclass 40, count 2 2006.285.16:42:02.89#ibcon#read 3, iclass 40, count 2 2006.285.16:42:02.89#ibcon#about to read 4, iclass 40, count 2 2006.285.16:42:02.89#ibcon#read 4, iclass 40, count 2 2006.285.16:42:02.89#ibcon#about to read 5, iclass 40, count 2 2006.285.16:42:02.89#ibcon#read 5, iclass 40, count 2 2006.285.16:42:02.89#ibcon#about to read 6, iclass 40, count 2 2006.285.16:42:02.89#ibcon#read 6, iclass 40, count 2 2006.285.16:42:02.89#ibcon#end of sib2, iclass 40, count 2 2006.285.16:42:02.89#ibcon#*mode == 0, iclass 40, count 2 2006.285.16:42:02.89#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.16:42:02.89#ibcon#[25=AT05-03\r\n] 2006.285.16:42:02.89#ibcon#*before write, iclass 40, count 2 2006.285.16:42:02.89#ibcon#enter sib2, iclass 40, count 2 2006.285.16:42:02.89#ibcon#flushed, iclass 40, count 2 2006.285.16:42:02.89#ibcon#about to write, iclass 40, count 2 2006.285.16:42:02.89#ibcon#wrote, iclass 40, count 2 2006.285.16:42:02.89#ibcon#about to read 3, iclass 40, count 2 2006.285.16:42:02.92#ibcon#read 3, iclass 40, count 2 2006.285.16:42:02.92#ibcon#about to read 4, iclass 40, count 2 2006.285.16:42:02.92#ibcon#read 4, iclass 40, count 2 2006.285.16:42:02.92#ibcon#about to read 5, iclass 40, count 2 2006.285.16:42:02.92#ibcon#read 5, iclass 40, count 2 2006.285.16:42:02.92#ibcon#about to read 6, iclass 40, count 2 2006.285.16:42:02.92#ibcon#read 6, iclass 40, count 2 2006.285.16:42:02.92#ibcon#end of sib2, iclass 40, count 2 2006.285.16:42:02.92#ibcon#*after write, iclass 40, count 2 2006.285.16:42:02.92#ibcon#*before return 0, iclass 40, count 2 2006.285.16:42:02.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:42:02.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:42:02.92#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.16:42:02.92#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:02.92#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:42:03.04#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:42:03.04#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:42:03.04#ibcon#enter wrdev, iclass 40, count 0 2006.285.16:42:03.04#ibcon#first serial, iclass 40, count 0 2006.285.16:42:03.04#ibcon#enter sib2, iclass 40, count 0 2006.285.16:42:03.04#ibcon#flushed, iclass 40, count 0 2006.285.16:42:03.04#ibcon#about to write, iclass 40, count 0 2006.285.16:42:03.04#ibcon#wrote, iclass 40, count 0 2006.285.16:42:03.04#ibcon#about to read 3, iclass 40, count 0 2006.285.16:42:03.06#ibcon#read 3, iclass 40, count 0 2006.285.16:42:03.06#ibcon#about to read 4, iclass 40, count 0 2006.285.16:42:03.06#ibcon#read 4, iclass 40, count 0 2006.285.16:42:03.06#ibcon#about to read 5, iclass 40, count 0 2006.285.16:42:03.06#ibcon#read 5, iclass 40, count 0 2006.285.16:42:03.06#ibcon#about to read 6, iclass 40, count 0 2006.285.16:42:03.06#ibcon#read 6, iclass 40, count 0 2006.285.16:42:03.06#ibcon#end of sib2, iclass 40, count 0 2006.285.16:42:03.06#ibcon#*mode == 0, iclass 40, count 0 2006.285.16:42:03.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.16:42:03.06#ibcon#[25=USB\r\n] 2006.285.16:42:03.06#ibcon#*before write, iclass 40, count 0 2006.285.16:42:03.06#ibcon#enter sib2, iclass 40, count 0 2006.285.16:42:03.06#ibcon#flushed, iclass 40, count 0 2006.285.16:42:03.06#ibcon#about to write, iclass 40, count 0 2006.285.16:42:03.06#ibcon#wrote, iclass 40, count 0 2006.285.16:42:03.06#ibcon#about to read 3, iclass 40, count 0 2006.285.16:42:03.09#ibcon#read 3, iclass 40, count 0 2006.285.16:42:03.09#ibcon#about to read 4, iclass 40, count 0 2006.285.16:42:03.09#ibcon#read 4, iclass 40, count 0 2006.285.16:42:03.09#ibcon#about to read 5, iclass 40, count 0 2006.285.16:42:03.09#ibcon#read 5, iclass 40, count 0 2006.285.16:42:03.09#ibcon#about to read 6, iclass 40, count 0 2006.285.16:42:03.09#ibcon#read 6, iclass 40, count 0 2006.285.16:42:03.09#ibcon#end of sib2, iclass 40, count 0 2006.285.16:42:03.09#ibcon#*after write, iclass 40, count 0 2006.285.16:42:03.09#ibcon#*before return 0, iclass 40, count 0 2006.285.16:42:03.09#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:42:03.09#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:42:03.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.16:42:03.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.16:42:03.09$vck44/valo=6,814.99 2006.285.16:42:03.09#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.16:42:03.09#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.16:42:03.09#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:03.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:42:03.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:42:03.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:42:03.09#ibcon#enter wrdev, iclass 4, count 0 2006.285.16:42:03.09#ibcon#first serial, iclass 4, count 0 2006.285.16:42:03.09#ibcon#enter sib2, iclass 4, count 0 2006.285.16:42:03.09#ibcon#flushed, iclass 4, count 0 2006.285.16:42:03.09#ibcon#about to write, iclass 4, count 0 2006.285.16:42:03.09#ibcon#wrote, iclass 4, count 0 2006.285.16:42:03.09#ibcon#about to read 3, iclass 4, count 0 2006.285.16:42:03.11#ibcon#read 3, iclass 4, count 0 2006.285.16:42:03.11#ibcon#about to read 4, iclass 4, count 0 2006.285.16:42:03.11#ibcon#read 4, iclass 4, count 0 2006.285.16:42:03.11#ibcon#about to read 5, iclass 4, count 0 2006.285.16:42:03.11#ibcon#read 5, iclass 4, count 0 2006.285.16:42:03.11#ibcon#about to read 6, iclass 4, count 0 2006.285.16:42:03.11#ibcon#read 6, iclass 4, count 0 2006.285.16:42:03.11#ibcon#end of sib2, iclass 4, count 0 2006.285.16:42:03.11#ibcon#*mode == 0, iclass 4, count 0 2006.285.16:42:03.11#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.16:42:03.11#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.16:42:03.11#ibcon#*before write, iclass 4, count 0 2006.285.16:42:03.11#ibcon#enter sib2, iclass 4, count 0 2006.285.16:42:03.11#ibcon#flushed, iclass 4, count 0 2006.285.16:42:03.11#ibcon#about to write, iclass 4, count 0 2006.285.16:42:03.11#ibcon#wrote, iclass 4, count 0 2006.285.16:42:03.11#ibcon#about to read 3, iclass 4, count 0 2006.285.16:42:03.15#ibcon#read 3, iclass 4, count 0 2006.285.16:42:03.15#ibcon#about to read 4, iclass 4, count 0 2006.285.16:42:03.15#ibcon#read 4, iclass 4, count 0 2006.285.16:42:03.15#ibcon#about to read 5, iclass 4, count 0 2006.285.16:42:03.15#ibcon#read 5, iclass 4, count 0 2006.285.16:42:03.15#ibcon#about to read 6, iclass 4, count 0 2006.285.16:42:03.15#ibcon#read 6, iclass 4, count 0 2006.285.16:42:03.15#ibcon#end of sib2, iclass 4, count 0 2006.285.16:42:03.15#ibcon#*after write, iclass 4, count 0 2006.285.16:42:03.15#ibcon#*before return 0, iclass 4, count 0 2006.285.16:42:03.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:42:03.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:42:03.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.16:42:03.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.16:42:03.15$vck44/va=6,4 2006.285.16:42:03.15#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.16:42:03.15#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.16:42:03.15#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:03.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:42:03.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:42:03.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:42:03.21#ibcon#enter wrdev, iclass 6, count 2 2006.285.16:42:03.21#ibcon#first serial, iclass 6, count 2 2006.285.16:42:03.21#ibcon#enter sib2, iclass 6, count 2 2006.285.16:42:03.21#ibcon#flushed, iclass 6, count 2 2006.285.16:42:03.21#ibcon#about to write, iclass 6, count 2 2006.285.16:42:03.21#ibcon#wrote, iclass 6, count 2 2006.285.16:42:03.21#ibcon#about to read 3, iclass 6, count 2 2006.285.16:42:03.23#ibcon#read 3, iclass 6, count 2 2006.285.16:42:03.23#ibcon#about to read 4, iclass 6, count 2 2006.285.16:42:03.23#ibcon#read 4, iclass 6, count 2 2006.285.16:42:03.23#ibcon#about to read 5, iclass 6, count 2 2006.285.16:42:03.23#ibcon#read 5, iclass 6, count 2 2006.285.16:42:03.23#ibcon#about to read 6, iclass 6, count 2 2006.285.16:42:03.23#ibcon#read 6, iclass 6, count 2 2006.285.16:42:03.23#ibcon#end of sib2, iclass 6, count 2 2006.285.16:42:03.23#ibcon#*mode == 0, iclass 6, count 2 2006.285.16:42:03.23#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.16:42:03.23#ibcon#[25=AT06-04\r\n] 2006.285.16:42:03.23#ibcon#*before write, iclass 6, count 2 2006.285.16:42:03.23#ibcon#enter sib2, iclass 6, count 2 2006.285.16:42:03.23#ibcon#flushed, iclass 6, count 2 2006.285.16:42:03.23#ibcon#about to write, iclass 6, count 2 2006.285.16:42:03.23#ibcon#wrote, iclass 6, count 2 2006.285.16:42:03.23#ibcon#about to read 3, iclass 6, count 2 2006.285.16:42:03.26#ibcon#read 3, iclass 6, count 2 2006.285.16:42:03.26#ibcon#about to read 4, iclass 6, count 2 2006.285.16:42:03.26#ibcon#read 4, iclass 6, count 2 2006.285.16:42:03.26#ibcon#about to read 5, iclass 6, count 2 2006.285.16:42:03.26#ibcon#read 5, iclass 6, count 2 2006.285.16:42:03.26#ibcon#about to read 6, iclass 6, count 2 2006.285.16:42:03.26#ibcon#read 6, iclass 6, count 2 2006.285.16:42:03.26#ibcon#end of sib2, iclass 6, count 2 2006.285.16:42:03.26#ibcon#*after write, iclass 6, count 2 2006.285.16:42:03.26#ibcon#*before return 0, iclass 6, count 2 2006.285.16:42:03.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:42:03.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:42:03.26#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.16:42:03.26#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:03.26#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:42:03.38#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:42:03.38#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:42:03.38#ibcon#enter wrdev, iclass 6, count 0 2006.285.16:42:03.38#ibcon#first serial, iclass 6, count 0 2006.285.16:42:03.38#ibcon#enter sib2, iclass 6, count 0 2006.285.16:42:03.38#ibcon#flushed, iclass 6, count 0 2006.285.16:42:03.38#ibcon#about to write, iclass 6, count 0 2006.285.16:42:03.38#ibcon#wrote, iclass 6, count 0 2006.285.16:42:03.38#ibcon#about to read 3, iclass 6, count 0 2006.285.16:42:03.40#ibcon#read 3, iclass 6, count 0 2006.285.16:42:03.40#ibcon#about to read 4, iclass 6, count 0 2006.285.16:42:03.40#ibcon#read 4, iclass 6, count 0 2006.285.16:42:03.42#ibcon#about to read 5, iclass 6, count 0 2006.285.16:42:03.42#ibcon#read 5, iclass 6, count 0 2006.285.16:42:03.42#ibcon#about to read 6, iclass 6, count 0 2006.285.16:42:03.42#ibcon#read 6, iclass 6, count 0 2006.285.16:42:03.42#ibcon#end of sib2, iclass 6, count 0 2006.285.16:42:03.42#ibcon#*mode == 0, iclass 6, count 0 2006.285.16:42:03.42#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.16:42:03.42#ibcon#[25=USB\r\n] 2006.285.16:42:03.42#ibcon#*before write, iclass 6, count 0 2006.285.16:42:03.42#ibcon#enter sib2, iclass 6, count 0 2006.285.16:42:03.42#ibcon#flushed, iclass 6, count 0 2006.285.16:42:03.42#ibcon#about to write, iclass 6, count 0 2006.285.16:42:03.42#ibcon#wrote, iclass 6, count 0 2006.285.16:42:03.42#ibcon#about to read 3, iclass 6, count 0 2006.285.16:42:03.45#ibcon#read 3, iclass 6, count 0 2006.285.16:42:03.45#ibcon#about to read 4, iclass 6, count 0 2006.285.16:42:03.45#ibcon#read 4, iclass 6, count 0 2006.285.16:42:03.45#ibcon#about to read 5, iclass 6, count 0 2006.285.16:42:03.45#ibcon#read 5, iclass 6, count 0 2006.285.16:42:03.45#ibcon#about to read 6, iclass 6, count 0 2006.285.16:42:03.45#ibcon#read 6, iclass 6, count 0 2006.285.16:42:03.45#ibcon#end of sib2, iclass 6, count 0 2006.285.16:42:03.45#ibcon#*after write, iclass 6, count 0 2006.285.16:42:03.45#ibcon#*before return 0, iclass 6, count 0 2006.285.16:42:03.45#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:42:03.45#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:42:03.45#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.16:42:03.45#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.16:42:03.45$vck44/valo=7,864.99 2006.285.16:42:03.45#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.16:42:03.45#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.16:42:03.45#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:03.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:42:03.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:42:03.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:42:03.45#ibcon#enter wrdev, iclass 10, count 0 2006.285.16:42:03.45#ibcon#first serial, iclass 10, count 0 2006.285.16:42:03.45#ibcon#enter sib2, iclass 10, count 0 2006.285.16:42:03.45#ibcon#flushed, iclass 10, count 0 2006.285.16:42:03.45#ibcon#about to write, iclass 10, count 0 2006.285.16:42:03.45#ibcon#wrote, iclass 10, count 0 2006.285.16:42:03.45#ibcon#about to read 3, iclass 10, count 0 2006.285.16:42:03.47#ibcon#read 3, iclass 10, count 0 2006.285.16:42:03.47#ibcon#about to read 4, iclass 10, count 0 2006.285.16:42:03.47#ibcon#read 4, iclass 10, count 0 2006.285.16:42:03.47#ibcon#about to read 5, iclass 10, count 0 2006.285.16:42:03.47#ibcon#read 5, iclass 10, count 0 2006.285.16:42:03.47#ibcon#about to read 6, iclass 10, count 0 2006.285.16:42:03.47#ibcon#read 6, iclass 10, count 0 2006.285.16:42:03.47#ibcon#end of sib2, iclass 10, count 0 2006.285.16:42:03.47#ibcon#*mode == 0, iclass 10, count 0 2006.285.16:42:03.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.16:42:03.47#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.16:42:03.47#ibcon#*before write, iclass 10, count 0 2006.285.16:42:03.47#ibcon#enter sib2, iclass 10, count 0 2006.285.16:42:03.47#ibcon#flushed, iclass 10, count 0 2006.285.16:42:03.47#ibcon#about to write, iclass 10, count 0 2006.285.16:42:03.47#ibcon#wrote, iclass 10, count 0 2006.285.16:42:03.47#ibcon#about to read 3, iclass 10, count 0 2006.285.16:42:03.51#ibcon#read 3, iclass 10, count 0 2006.285.16:42:03.51#ibcon#about to read 4, iclass 10, count 0 2006.285.16:42:03.51#ibcon#read 4, iclass 10, count 0 2006.285.16:42:03.51#ibcon#about to read 5, iclass 10, count 0 2006.285.16:42:03.51#ibcon#read 5, iclass 10, count 0 2006.285.16:42:03.51#ibcon#about to read 6, iclass 10, count 0 2006.285.16:42:03.51#ibcon#read 6, iclass 10, count 0 2006.285.16:42:03.51#ibcon#end of sib2, iclass 10, count 0 2006.285.16:42:03.51#ibcon#*after write, iclass 10, count 0 2006.285.16:42:03.51#ibcon#*before return 0, iclass 10, count 0 2006.285.16:42:03.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:42:03.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:42:03.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.16:42:03.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.16:42:03.51$vck44/va=7,4 2006.285.16:42:03.51#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.16:42:03.51#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.16:42:03.51#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:03.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:42:03.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:42:03.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:42:03.57#ibcon#enter wrdev, iclass 12, count 2 2006.285.16:42:03.57#ibcon#first serial, iclass 12, count 2 2006.285.16:42:03.57#ibcon#enter sib2, iclass 12, count 2 2006.285.16:42:03.57#ibcon#flushed, iclass 12, count 2 2006.285.16:42:03.57#ibcon#about to write, iclass 12, count 2 2006.285.16:42:03.57#ibcon#wrote, iclass 12, count 2 2006.285.16:42:03.57#ibcon#about to read 3, iclass 12, count 2 2006.285.16:42:03.59#ibcon#read 3, iclass 12, count 2 2006.285.16:42:03.59#ibcon#about to read 4, iclass 12, count 2 2006.285.16:42:03.59#ibcon#read 4, iclass 12, count 2 2006.285.16:42:03.59#ibcon#about to read 5, iclass 12, count 2 2006.285.16:42:03.59#ibcon#read 5, iclass 12, count 2 2006.285.16:42:03.59#ibcon#about to read 6, iclass 12, count 2 2006.285.16:42:03.59#ibcon#read 6, iclass 12, count 2 2006.285.16:42:03.59#ibcon#end of sib2, iclass 12, count 2 2006.285.16:42:03.59#ibcon#*mode == 0, iclass 12, count 2 2006.285.16:42:03.59#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.16:42:03.59#ibcon#[25=AT07-04\r\n] 2006.285.16:42:03.59#ibcon#*before write, iclass 12, count 2 2006.285.16:42:03.59#ibcon#enter sib2, iclass 12, count 2 2006.285.16:42:03.59#ibcon#flushed, iclass 12, count 2 2006.285.16:42:03.59#ibcon#about to write, iclass 12, count 2 2006.285.16:42:03.59#ibcon#wrote, iclass 12, count 2 2006.285.16:42:03.59#ibcon#about to read 3, iclass 12, count 2 2006.285.16:42:03.62#ibcon#read 3, iclass 12, count 2 2006.285.16:42:03.62#ibcon#about to read 4, iclass 12, count 2 2006.285.16:42:03.62#ibcon#read 4, iclass 12, count 2 2006.285.16:42:03.62#ibcon#about to read 5, iclass 12, count 2 2006.285.16:42:03.62#ibcon#read 5, iclass 12, count 2 2006.285.16:42:03.62#ibcon#about to read 6, iclass 12, count 2 2006.285.16:42:03.62#ibcon#read 6, iclass 12, count 2 2006.285.16:42:03.62#ibcon#end of sib2, iclass 12, count 2 2006.285.16:42:03.62#ibcon#*after write, iclass 12, count 2 2006.285.16:42:03.62#ibcon#*before return 0, iclass 12, count 2 2006.285.16:42:03.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:42:03.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:42:03.62#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.16:42:03.62#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:03.62#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:42:03.74#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:42:03.74#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:42:03.74#ibcon#enter wrdev, iclass 12, count 0 2006.285.16:42:03.74#ibcon#first serial, iclass 12, count 0 2006.285.16:42:03.74#ibcon#enter sib2, iclass 12, count 0 2006.285.16:42:03.74#ibcon#flushed, iclass 12, count 0 2006.285.16:42:03.74#ibcon#about to write, iclass 12, count 0 2006.285.16:42:03.74#ibcon#wrote, iclass 12, count 0 2006.285.16:42:03.74#ibcon#about to read 3, iclass 12, count 0 2006.285.16:42:03.76#ibcon#read 3, iclass 12, count 0 2006.285.16:42:03.76#ibcon#about to read 4, iclass 12, count 0 2006.285.16:42:03.76#ibcon#read 4, iclass 12, count 0 2006.285.16:42:03.76#ibcon#about to read 5, iclass 12, count 0 2006.285.16:42:03.76#ibcon#read 5, iclass 12, count 0 2006.285.16:42:03.76#ibcon#about to read 6, iclass 12, count 0 2006.285.16:42:03.76#ibcon#read 6, iclass 12, count 0 2006.285.16:42:03.76#ibcon#end of sib2, iclass 12, count 0 2006.285.16:42:03.76#ibcon#*mode == 0, iclass 12, count 0 2006.285.16:42:03.76#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.16:42:03.76#ibcon#[25=USB\r\n] 2006.285.16:42:03.76#ibcon#*before write, iclass 12, count 0 2006.285.16:42:03.76#ibcon#enter sib2, iclass 12, count 0 2006.285.16:42:03.76#ibcon#flushed, iclass 12, count 0 2006.285.16:42:03.76#ibcon#about to write, iclass 12, count 0 2006.285.16:42:03.76#ibcon#wrote, iclass 12, count 0 2006.285.16:42:03.76#ibcon#about to read 3, iclass 12, count 0 2006.285.16:42:03.79#ibcon#read 3, iclass 12, count 0 2006.285.16:42:03.79#ibcon#about to read 4, iclass 12, count 0 2006.285.16:42:03.79#ibcon#read 4, iclass 12, count 0 2006.285.16:42:03.79#ibcon#about to read 5, iclass 12, count 0 2006.285.16:42:03.79#ibcon#read 5, iclass 12, count 0 2006.285.16:42:03.79#ibcon#about to read 6, iclass 12, count 0 2006.285.16:42:03.79#ibcon#read 6, iclass 12, count 0 2006.285.16:42:03.79#ibcon#end of sib2, iclass 12, count 0 2006.285.16:42:03.79#ibcon#*after write, iclass 12, count 0 2006.285.16:42:03.79#ibcon#*before return 0, iclass 12, count 0 2006.285.16:42:03.79#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:42:03.79#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:42:03.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.16:42:03.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.16:42:03.79$vck44/valo=8,884.99 2006.285.16:42:03.79#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.16:42:03.79#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.16:42:03.79#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:03.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:42:03.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:42:03.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:42:03.79#ibcon#enter wrdev, iclass 14, count 0 2006.285.16:42:03.79#ibcon#first serial, iclass 14, count 0 2006.285.16:42:03.79#ibcon#enter sib2, iclass 14, count 0 2006.285.16:42:03.79#ibcon#flushed, iclass 14, count 0 2006.285.16:42:03.79#ibcon#about to write, iclass 14, count 0 2006.285.16:42:03.79#ibcon#wrote, iclass 14, count 0 2006.285.16:42:03.79#ibcon#about to read 3, iclass 14, count 0 2006.285.16:42:03.81#ibcon#read 3, iclass 14, count 0 2006.285.16:42:03.81#ibcon#about to read 4, iclass 14, count 0 2006.285.16:42:03.81#ibcon#read 4, iclass 14, count 0 2006.285.16:42:03.81#ibcon#about to read 5, iclass 14, count 0 2006.285.16:42:03.81#ibcon#read 5, iclass 14, count 0 2006.285.16:42:03.81#ibcon#about to read 6, iclass 14, count 0 2006.285.16:42:03.81#ibcon#read 6, iclass 14, count 0 2006.285.16:42:03.81#ibcon#end of sib2, iclass 14, count 0 2006.285.16:42:03.81#ibcon#*mode == 0, iclass 14, count 0 2006.285.16:42:03.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.16:42:03.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.16:42:03.81#ibcon#*before write, iclass 14, count 0 2006.285.16:42:03.81#ibcon#enter sib2, iclass 14, count 0 2006.285.16:42:03.81#ibcon#flushed, iclass 14, count 0 2006.285.16:42:03.81#ibcon#about to write, iclass 14, count 0 2006.285.16:42:03.81#ibcon#wrote, iclass 14, count 0 2006.285.16:42:03.81#ibcon#about to read 3, iclass 14, count 0 2006.285.16:42:03.85#ibcon#read 3, iclass 14, count 0 2006.285.16:42:03.85#ibcon#about to read 4, iclass 14, count 0 2006.285.16:42:03.85#ibcon#read 4, iclass 14, count 0 2006.285.16:42:03.85#ibcon#about to read 5, iclass 14, count 0 2006.285.16:42:03.85#ibcon#read 5, iclass 14, count 0 2006.285.16:42:03.85#ibcon#about to read 6, iclass 14, count 0 2006.285.16:42:03.85#ibcon#read 6, iclass 14, count 0 2006.285.16:42:03.85#ibcon#end of sib2, iclass 14, count 0 2006.285.16:42:03.85#ibcon#*after write, iclass 14, count 0 2006.285.16:42:03.85#ibcon#*before return 0, iclass 14, count 0 2006.285.16:42:03.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:42:03.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:42:03.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.16:42:03.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.16:42:03.85$vck44/va=8,3 2006.285.16:42:03.85#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.16:42:03.85#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.16:42:03.85#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:03.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:42:03.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:42:03.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:42:03.91#ibcon#enter wrdev, iclass 16, count 2 2006.285.16:42:03.91#ibcon#first serial, iclass 16, count 2 2006.285.16:42:03.91#ibcon#enter sib2, iclass 16, count 2 2006.285.16:42:03.91#ibcon#flushed, iclass 16, count 2 2006.285.16:42:03.91#ibcon#about to write, iclass 16, count 2 2006.285.16:42:03.91#ibcon#wrote, iclass 16, count 2 2006.285.16:42:03.91#ibcon#about to read 3, iclass 16, count 2 2006.285.16:42:03.93#ibcon#read 3, iclass 16, count 2 2006.285.16:42:03.93#ibcon#about to read 4, iclass 16, count 2 2006.285.16:42:03.93#ibcon#read 4, iclass 16, count 2 2006.285.16:42:03.93#ibcon#about to read 5, iclass 16, count 2 2006.285.16:42:03.93#ibcon#read 5, iclass 16, count 2 2006.285.16:42:03.93#ibcon#about to read 6, iclass 16, count 2 2006.285.16:42:03.93#ibcon#read 6, iclass 16, count 2 2006.285.16:42:03.93#ibcon#end of sib2, iclass 16, count 2 2006.285.16:42:03.93#ibcon#*mode == 0, iclass 16, count 2 2006.285.16:42:03.93#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.16:42:03.93#ibcon#[25=AT08-03\r\n] 2006.285.16:42:03.93#ibcon#*before write, iclass 16, count 2 2006.285.16:42:03.93#ibcon#enter sib2, iclass 16, count 2 2006.285.16:42:03.93#ibcon#flushed, iclass 16, count 2 2006.285.16:42:03.93#ibcon#about to write, iclass 16, count 2 2006.285.16:42:03.93#ibcon#wrote, iclass 16, count 2 2006.285.16:42:03.93#ibcon#about to read 3, iclass 16, count 2 2006.285.16:42:03.96#ibcon#read 3, iclass 16, count 2 2006.285.16:42:03.96#ibcon#about to read 4, iclass 16, count 2 2006.285.16:42:03.96#ibcon#read 4, iclass 16, count 2 2006.285.16:42:03.96#ibcon#about to read 5, iclass 16, count 2 2006.285.16:42:03.96#ibcon#read 5, iclass 16, count 2 2006.285.16:42:03.96#ibcon#about to read 6, iclass 16, count 2 2006.285.16:42:03.96#ibcon#read 6, iclass 16, count 2 2006.285.16:42:03.96#ibcon#end of sib2, iclass 16, count 2 2006.285.16:42:03.96#ibcon#*after write, iclass 16, count 2 2006.285.16:42:03.96#ibcon#*before return 0, iclass 16, count 2 2006.285.16:42:03.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:42:03.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.16:42:03.96#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.16:42:03.96#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:03.96#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:42:04.08#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:42:04.08#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:42:04.08#ibcon#enter wrdev, iclass 16, count 0 2006.285.16:42:04.08#ibcon#first serial, iclass 16, count 0 2006.285.16:42:04.08#ibcon#enter sib2, iclass 16, count 0 2006.285.16:42:04.08#ibcon#flushed, iclass 16, count 0 2006.285.16:42:04.08#ibcon#about to write, iclass 16, count 0 2006.285.16:42:04.08#ibcon#wrote, iclass 16, count 0 2006.285.16:42:04.08#ibcon#about to read 3, iclass 16, count 0 2006.285.16:42:04.10#ibcon#read 3, iclass 16, count 0 2006.285.16:42:04.10#ibcon#about to read 4, iclass 16, count 0 2006.285.16:42:04.10#ibcon#read 4, iclass 16, count 0 2006.285.16:42:04.10#ibcon#about to read 5, iclass 16, count 0 2006.285.16:42:04.10#ibcon#read 5, iclass 16, count 0 2006.285.16:42:04.10#ibcon#about to read 6, iclass 16, count 0 2006.285.16:42:04.10#ibcon#read 6, iclass 16, count 0 2006.285.16:42:04.10#ibcon#end of sib2, iclass 16, count 0 2006.285.16:42:04.10#ibcon#*mode == 0, iclass 16, count 0 2006.285.16:42:04.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.16:42:04.10#ibcon#[25=USB\r\n] 2006.285.16:42:04.10#ibcon#*before write, iclass 16, count 0 2006.285.16:42:04.10#ibcon#enter sib2, iclass 16, count 0 2006.285.16:42:04.10#ibcon#flushed, iclass 16, count 0 2006.285.16:42:04.10#ibcon#about to write, iclass 16, count 0 2006.285.16:42:04.10#ibcon#wrote, iclass 16, count 0 2006.285.16:42:04.10#ibcon#about to read 3, iclass 16, count 0 2006.285.16:42:04.13#ibcon#read 3, iclass 16, count 0 2006.285.16:42:04.13#ibcon#about to read 4, iclass 16, count 0 2006.285.16:42:04.13#ibcon#read 4, iclass 16, count 0 2006.285.16:42:04.13#ibcon#about to read 5, iclass 16, count 0 2006.285.16:42:04.13#ibcon#read 5, iclass 16, count 0 2006.285.16:42:04.13#ibcon#about to read 6, iclass 16, count 0 2006.285.16:42:04.13#ibcon#read 6, iclass 16, count 0 2006.285.16:42:04.13#ibcon#end of sib2, iclass 16, count 0 2006.285.16:42:04.13#ibcon#*after write, iclass 16, count 0 2006.285.16:42:04.13#ibcon#*before return 0, iclass 16, count 0 2006.285.16:42:04.13#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:42:04.13#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.16:42:04.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.16:42:04.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.16:42:04.13$vck44/vblo=1,629.99 2006.285.16:42:04.13#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.16:42:04.13#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.16:42:04.13#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:04.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:42:04.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:42:04.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:42:04.13#ibcon#enter wrdev, iclass 18, count 0 2006.285.16:42:04.13#ibcon#first serial, iclass 18, count 0 2006.285.16:42:04.13#ibcon#enter sib2, iclass 18, count 0 2006.285.16:42:04.13#ibcon#flushed, iclass 18, count 0 2006.285.16:42:04.13#ibcon#about to write, iclass 18, count 0 2006.285.16:42:04.13#ibcon#wrote, iclass 18, count 0 2006.285.16:42:04.13#ibcon#about to read 3, iclass 18, count 0 2006.285.16:42:04.15#ibcon#read 3, iclass 18, count 0 2006.285.16:42:04.15#ibcon#about to read 4, iclass 18, count 0 2006.285.16:42:04.15#ibcon#read 4, iclass 18, count 0 2006.285.16:42:04.15#ibcon#about to read 5, iclass 18, count 0 2006.285.16:42:04.15#ibcon#read 5, iclass 18, count 0 2006.285.16:42:04.15#ibcon#about to read 6, iclass 18, count 0 2006.285.16:42:04.15#ibcon#read 6, iclass 18, count 0 2006.285.16:42:04.15#ibcon#end of sib2, iclass 18, count 0 2006.285.16:42:04.15#ibcon#*mode == 0, iclass 18, count 0 2006.285.16:42:04.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.16:42:04.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.16:42:04.15#ibcon#*before write, iclass 18, count 0 2006.285.16:42:04.15#ibcon#enter sib2, iclass 18, count 0 2006.285.16:42:04.15#ibcon#flushed, iclass 18, count 0 2006.285.16:42:04.15#ibcon#about to write, iclass 18, count 0 2006.285.16:42:04.15#ibcon#wrote, iclass 18, count 0 2006.285.16:42:04.15#ibcon#about to read 3, iclass 18, count 0 2006.285.16:42:04.19#ibcon#read 3, iclass 18, count 0 2006.285.16:42:04.19#ibcon#about to read 4, iclass 18, count 0 2006.285.16:42:04.19#ibcon#read 4, iclass 18, count 0 2006.285.16:42:04.19#ibcon#about to read 5, iclass 18, count 0 2006.285.16:42:04.19#ibcon#read 5, iclass 18, count 0 2006.285.16:42:04.19#ibcon#about to read 6, iclass 18, count 0 2006.285.16:42:04.19#ibcon#read 6, iclass 18, count 0 2006.285.16:42:04.19#ibcon#end of sib2, iclass 18, count 0 2006.285.16:42:04.19#ibcon#*after write, iclass 18, count 0 2006.285.16:42:04.19#ibcon#*before return 0, iclass 18, count 0 2006.285.16:42:04.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:42:04.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.16:42:04.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.16:42:04.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.16:42:04.19$vck44/vb=1,4 2006.285.16:42:04.19#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.16:42:04.19#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.16:42:04.19#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:04.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:42:04.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:42:04.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:42:04.19#ibcon#enter wrdev, iclass 20, count 2 2006.285.16:42:04.19#ibcon#first serial, iclass 20, count 2 2006.285.16:42:04.19#ibcon#enter sib2, iclass 20, count 2 2006.285.16:42:04.19#ibcon#flushed, iclass 20, count 2 2006.285.16:42:04.19#ibcon#about to write, iclass 20, count 2 2006.285.16:42:04.19#ibcon#wrote, iclass 20, count 2 2006.285.16:42:04.19#ibcon#about to read 3, iclass 20, count 2 2006.285.16:42:04.21#ibcon#read 3, iclass 20, count 2 2006.285.16:42:04.21#ibcon#about to read 4, iclass 20, count 2 2006.285.16:42:04.21#ibcon#read 4, iclass 20, count 2 2006.285.16:42:04.21#ibcon#about to read 5, iclass 20, count 2 2006.285.16:42:04.21#ibcon#read 5, iclass 20, count 2 2006.285.16:42:04.21#ibcon#about to read 6, iclass 20, count 2 2006.285.16:42:04.21#ibcon#read 6, iclass 20, count 2 2006.285.16:42:04.21#ibcon#end of sib2, iclass 20, count 2 2006.285.16:42:04.21#ibcon#*mode == 0, iclass 20, count 2 2006.285.16:42:04.21#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.16:42:04.21#ibcon#[27=AT01-04\r\n] 2006.285.16:42:04.21#ibcon#*before write, iclass 20, count 2 2006.285.16:42:04.21#ibcon#enter sib2, iclass 20, count 2 2006.285.16:42:04.21#ibcon#flushed, iclass 20, count 2 2006.285.16:42:04.21#ibcon#about to write, iclass 20, count 2 2006.285.16:42:04.21#ibcon#wrote, iclass 20, count 2 2006.285.16:42:04.21#ibcon#about to read 3, iclass 20, count 2 2006.285.16:42:04.24#ibcon#read 3, iclass 20, count 2 2006.285.16:42:04.24#ibcon#about to read 4, iclass 20, count 2 2006.285.16:42:04.24#ibcon#read 4, iclass 20, count 2 2006.285.16:42:04.24#ibcon#about to read 5, iclass 20, count 2 2006.285.16:42:04.24#ibcon#read 5, iclass 20, count 2 2006.285.16:42:04.24#ibcon#about to read 6, iclass 20, count 2 2006.285.16:42:04.24#ibcon#read 6, iclass 20, count 2 2006.285.16:42:04.24#ibcon#end of sib2, iclass 20, count 2 2006.285.16:42:04.24#ibcon#*after write, iclass 20, count 2 2006.285.16:42:04.24#ibcon#*before return 0, iclass 20, count 2 2006.285.16:42:04.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:42:04.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.16:42:04.24#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.16:42:04.24#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:04.24#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:42:04.36#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:42:04.36#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:42:04.36#ibcon#enter wrdev, iclass 20, count 0 2006.285.16:42:04.36#ibcon#first serial, iclass 20, count 0 2006.285.16:42:04.36#ibcon#enter sib2, iclass 20, count 0 2006.285.16:42:04.36#ibcon#flushed, iclass 20, count 0 2006.285.16:42:04.36#ibcon#about to write, iclass 20, count 0 2006.285.16:42:04.36#ibcon#wrote, iclass 20, count 0 2006.285.16:42:04.36#ibcon#about to read 3, iclass 20, count 0 2006.285.16:42:04.38#ibcon#read 3, iclass 20, count 0 2006.285.16:42:04.38#ibcon#about to read 4, iclass 20, count 0 2006.285.16:42:04.38#ibcon#read 4, iclass 20, count 0 2006.285.16:42:04.38#ibcon#about to read 5, iclass 20, count 0 2006.285.16:42:04.38#ibcon#read 5, iclass 20, count 0 2006.285.16:42:04.38#ibcon#about to read 6, iclass 20, count 0 2006.285.16:42:04.38#ibcon#read 6, iclass 20, count 0 2006.285.16:42:04.38#ibcon#end of sib2, iclass 20, count 0 2006.285.16:42:04.38#ibcon#*mode == 0, iclass 20, count 0 2006.285.16:42:04.38#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.16:42:04.38#ibcon#[27=USB\r\n] 2006.285.16:42:04.38#ibcon#*before write, iclass 20, count 0 2006.285.16:42:04.38#ibcon#enter sib2, iclass 20, count 0 2006.285.16:42:04.38#ibcon#flushed, iclass 20, count 0 2006.285.16:42:04.38#ibcon#about to write, iclass 20, count 0 2006.285.16:42:04.38#ibcon#wrote, iclass 20, count 0 2006.285.16:42:04.38#ibcon#about to read 3, iclass 20, count 0 2006.285.16:42:04.41#ibcon#read 3, iclass 20, count 0 2006.285.16:42:04.41#ibcon#about to read 4, iclass 20, count 0 2006.285.16:42:04.41#ibcon#read 4, iclass 20, count 0 2006.285.16:42:04.41#ibcon#about to read 5, iclass 20, count 0 2006.285.16:42:04.41#ibcon#read 5, iclass 20, count 0 2006.285.16:42:04.41#ibcon#about to read 6, iclass 20, count 0 2006.285.16:42:04.41#ibcon#read 6, iclass 20, count 0 2006.285.16:42:04.41#ibcon#end of sib2, iclass 20, count 0 2006.285.16:42:04.41#ibcon#*after write, iclass 20, count 0 2006.285.16:42:04.41#ibcon#*before return 0, iclass 20, count 0 2006.285.16:42:04.41#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:42:04.41#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.16:42:04.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.16:42:04.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.16:42:04.41$vck44/vblo=2,634.99 2006.285.16:42:04.41#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.16:42:04.41#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.16:42:04.41#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:04.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:42:04.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:42:04.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:42:04.41#ibcon#enter wrdev, iclass 22, count 0 2006.285.16:42:04.41#ibcon#first serial, iclass 22, count 0 2006.285.16:42:04.41#ibcon#enter sib2, iclass 22, count 0 2006.285.16:42:04.41#ibcon#flushed, iclass 22, count 0 2006.285.16:42:04.41#ibcon#about to write, iclass 22, count 0 2006.285.16:42:04.41#ibcon#wrote, iclass 22, count 0 2006.285.16:42:04.41#ibcon#about to read 3, iclass 22, count 0 2006.285.16:42:04.43#ibcon#read 3, iclass 22, count 0 2006.285.16:42:04.43#ibcon#about to read 4, iclass 22, count 0 2006.285.16:42:04.43#ibcon#read 4, iclass 22, count 0 2006.285.16:42:04.43#ibcon#about to read 5, iclass 22, count 0 2006.285.16:42:04.43#ibcon#read 5, iclass 22, count 0 2006.285.16:42:04.43#ibcon#about to read 6, iclass 22, count 0 2006.285.16:42:04.43#ibcon#read 6, iclass 22, count 0 2006.285.16:42:04.43#ibcon#end of sib2, iclass 22, count 0 2006.285.16:42:04.43#ibcon#*mode == 0, iclass 22, count 0 2006.285.16:42:04.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.16:42:04.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.16:42:04.43#ibcon#*before write, iclass 22, count 0 2006.285.16:42:04.43#ibcon#enter sib2, iclass 22, count 0 2006.285.16:42:04.43#ibcon#flushed, iclass 22, count 0 2006.285.16:42:04.43#ibcon#about to write, iclass 22, count 0 2006.285.16:42:04.43#ibcon#wrote, iclass 22, count 0 2006.285.16:42:04.43#ibcon#about to read 3, iclass 22, count 0 2006.285.16:42:04.47#ibcon#read 3, iclass 22, count 0 2006.285.16:42:04.47#ibcon#about to read 4, iclass 22, count 0 2006.285.16:42:04.47#ibcon#read 4, iclass 22, count 0 2006.285.16:42:04.47#ibcon#about to read 5, iclass 22, count 0 2006.285.16:42:04.47#ibcon#read 5, iclass 22, count 0 2006.285.16:42:04.47#ibcon#about to read 6, iclass 22, count 0 2006.285.16:42:04.47#ibcon#read 6, iclass 22, count 0 2006.285.16:42:04.47#ibcon#end of sib2, iclass 22, count 0 2006.285.16:42:04.47#ibcon#*after write, iclass 22, count 0 2006.285.16:42:04.47#ibcon#*before return 0, iclass 22, count 0 2006.285.16:42:04.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:42:04.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.16:42:04.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.16:42:04.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.16:42:04.47$vck44/vb=2,5 2006.285.16:42:04.47#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.16:42:04.47#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.16:42:04.47#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:04.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:42:04.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:42:04.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:42:04.53#ibcon#enter wrdev, iclass 24, count 2 2006.285.16:42:04.53#ibcon#first serial, iclass 24, count 2 2006.285.16:42:04.53#ibcon#enter sib2, iclass 24, count 2 2006.285.16:42:04.53#ibcon#flushed, iclass 24, count 2 2006.285.16:42:04.53#ibcon#about to write, iclass 24, count 2 2006.285.16:42:04.53#ibcon#wrote, iclass 24, count 2 2006.285.16:42:04.53#ibcon#about to read 3, iclass 24, count 2 2006.285.16:42:04.55#ibcon#read 3, iclass 24, count 2 2006.285.16:42:04.55#ibcon#about to read 4, iclass 24, count 2 2006.285.16:42:04.55#ibcon#read 4, iclass 24, count 2 2006.285.16:42:04.55#ibcon#about to read 5, iclass 24, count 2 2006.285.16:42:04.55#ibcon#read 5, iclass 24, count 2 2006.285.16:42:04.55#ibcon#about to read 6, iclass 24, count 2 2006.285.16:42:04.55#ibcon#read 6, iclass 24, count 2 2006.285.16:42:04.55#ibcon#end of sib2, iclass 24, count 2 2006.285.16:42:04.55#ibcon#*mode == 0, iclass 24, count 2 2006.285.16:42:04.55#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.16:42:04.55#ibcon#[27=AT02-05\r\n] 2006.285.16:42:04.55#ibcon#*before write, iclass 24, count 2 2006.285.16:42:04.55#ibcon#enter sib2, iclass 24, count 2 2006.285.16:42:04.55#ibcon#flushed, iclass 24, count 2 2006.285.16:42:04.55#ibcon#about to write, iclass 24, count 2 2006.285.16:42:04.55#ibcon#wrote, iclass 24, count 2 2006.285.16:42:04.55#ibcon#about to read 3, iclass 24, count 2 2006.285.16:42:04.58#ibcon#read 3, iclass 24, count 2 2006.285.16:42:04.58#ibcon#about to read 4, iclass 24, count 2 2006.285.16:42:04.58#ibcon#read 4, iclass 24, count 2 2006.285.16:42:04.58#ibcon#about to read 5, iclass 24, count 2 2006.285.16:42:04.58#ibcon#read 5, iclass 24, count 2 2006.285.16:42:04.58#ibcon#about to read 6, iclass 24, count 2 2006.285.16:42:04.58#ibcon#read 6, iclass 24, count 2 2006.285.16:42:04.58#ibcon#end of sib2, iclass 24, count 2 2006.285.16:42:04.58#ibcon#*after write, iclass 24, count 2 2006.285.16:42:04.58#ibcon#*before return 0, iclass 24, count 2 2006.285.16:42:04.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:42:04.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.16:42:04.58#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.16:42:04.58#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:04.58#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:42:04.70#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:42:04.70#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:42:04.70#ibcon#enter wrdev, iclass 24, count 0 2006.285.16:42:04.70#ibcon#first serial, iclass 24, count 0 2006.285.16:42:04.70#ibcon#enter sib2, iclass 24, count 0 2006.285.16:42:04.70#ibcon#flushed, iclass 24, count 0 2006.285.16:42:04.70#ibcon#about to write, iclass 24, count 0 2006.285.16:42:04.70#ibcon#wrote, iclass 24, count 0 2006.285.16:42:04.70#ibcon#about to read 3, iclass 24, count 0 2006.285.16:42:04.72#ibcon#read 3, iclass 24, count 0 2006.285.16:42:04.72#ibcon#about to read 4, iclass 24, count 0 2006.285.16:42:04.72#ibcon#read 4, iclass 24, count 0 2006.285.16:42:04.72#ibcon#about to read 5, iclass 24, count 0 2006.285.16:42:04.72#ibcon#read 5, iclass 24, count 0 2006.285.16:42:04.72#ibcon#about to read 6, iclass 24, count 0 2006.285.16:42:04.72#ibcon#read 6, iclass 24, count 0 2006.285.16:42:04.72#ibcon#end of sib2, iclass 24, count 0 2006.285.16:42:04.72#ibcon#*mode == 0, iclass 24, count 0 2006.285.16:42:04.72#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.16:42:04.72#ibcon#[27=USB\r\n] 2006.285.16:42:04.72#ibcon#*before write, iclass 24, count 0 2006.285.16:42:04.72#ibcon#enter sib2, iclass 24, count 0 2006.285.16:42:04.72#ibcon#flushed, iclass 24, count 0 2006.285.16:42:04.72#ibcon#about to write, iclass 24, count 0 2006.285.16:42:04.72#ibcon#wrote, iclass 24, count 0 2006.285.16:42:04.72#ibcon#about to read 3, iclass 24, count 0 2006.285.16:42:04.75#ibcon#read 3, iclass 24, count 0 2006.285.16:42:04.75#ibcon#about to read 4, iclass 24, count 0 2006.285.16:42:04.75#ibcon#read 4, iclass 24, count 0 2006.285.16:42:04.75#ibcon#about to read 5, iclass 24, count 0 2006.285.16:42:04.75#ibcon#read 5, iclass 24, count 0 2006.285.16:42:04.75#ibcon#about to read 6, iclass 24, count 0 2006.285.16:42:04.75#ibcon#read 6, iclass 24, count 0 2006.285.16:42:04.75#ibcon#end of sib2, iclass 24, count 0 2006.285.16:42:04.75#ibcon#*after write, iclass 24, count 0 2006.285.16:42:04.75#ibcon#*before return 0, iclass 24, count 0 2006.285.16:42:04.75#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:42:04.75#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.16:42:04.75#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.16:42:04.75#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.16:42:04.75$vck44/vblo=3,649.99 2006.285.16:42:04.75#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.16:42:04.75#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.16:42:04.75#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:04.75#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:42:04.75#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:42:04.75#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:42:04.75#ibcon#enter wrdev, iclass 26, count 0 2006.285.16:42:04.75#ibcon#first serial, iclass 26, count 0 2006.285.16:42:04.75#ibcon#enter sib2, iclass 26, count 0 2006.285.16:42:04.75#ibcon#flushed, iclass 26, count 0 2006.285.16:42:04.75#ibcon#about to write, iclass 26, count 0 2006.285.16:42:04.75#ibcon#wrote, iclass 26, count 0 2006.285.16:42:04.75#ibcon#about to read 3, iclass 26, count 0 2006.285.16:42:04.77#ibcon#read 3, iclass 26, count 0 2006.285.16:42:04.77#ibcon#about to read 4, iclass 26, count 0 2006.285.16:42:04.77#ibcon#read 4, iclass 26, count 0 2006.285.16:42:04.77#ibcon#about to read 5, iclass 26, count 0 2006.285.16:42:04.77#ibcon#read 5, iclass 26, count 0 2006.285.16:42:04.77#ibcon#about to read 6, iclass 26, count 0 2006.285.16:42:04.77#ibcon#read 6, iclass 26, count 0 2006.285.16:42:04.77#ibcon#end of sib2, iclass 26, count 0 2006.285.16:42:04.77#ibcon#*mode == 0, iclass 26, count 0 2006.285.16:42:04.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.16:42:04.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.16:42:04.77#ibcon#*before write, iclass 26, count 0 2006.285.16:42:04.77#ibcon#enter sib2, iclass 26, count 0 2006.285.16:42:04.77#ibcon#flushed, iclass 26, count 0 2006.285.16:42:04.77#ibcon#about to write, iclass 26, count 0 2006.285.16:42:04.77#ibcon#wrote, iclass 26, count 0 2006.285.16:42:04.77#ibcon#about to read 3, iclass 26, count 0 2006.285.16:42:04.81#ibcon#read 3, iclass 26, count 0 2006.285.16:42:04.81#ibcon#about to read 4, iclass 26, count 0 2006.285.16:42:04.81#ibcon#read 4, iclass 26, count 0 2006.285.16:42:04.81#ibcon#about to read 5, iclass 26, count 0 2006.285.16:42:04.81#ibcon#read 5, iclass 26, count 0 2006.285.16:42:04.81#ibcon#about to read 6, iclass 26, count 0 2006.285.16:42:04.81#ibcon#read 6, iclass 26, count 0 2006.285.16:42:04.81#ibcon#end of sib2, iclass 26, count 0 2006.285.16:42:04.81#ibcon#*after write, iclass 26, count 0 2006.285.16:42:04.81#ibcon#*before return 0, iclass 26, count 0 2006.285.16:42:04.81#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:42:04.81#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.16:42:04.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.16:42:04.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.16:42:04.81$vck44/vb=3,4 2006.285.16:42:04.81#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.16:42:04.81#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.16:42:04.81#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:04.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:42:04.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:42:04.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:42:04.87#ibcon#enter wrdev, iclass 28, count 2 2006.285.16:42:04.87#ibcon#first serial, iclass 28, count 2 2006.285.16:42:04.87#ibcon#enter sib2, iclass 28, count 2 2006.285.16:42:04.87#ibcon#flushed, iclass 28, count 2 2006.285.16:42:04.87#ibcon#about to write, iclass 28, count 2 2006.285.16:42:04.87#ibcon#wrote, iclass 28, count 2 2006.285.16:42:04.87#ibcon#about to read 3, iclass 28, count 2 2006.285.16:42:04.89#ibcon#read 3, iclass 28, count 2 2006.285.16:42:04.89#ibcon#about to read 4, iclass 28, count 2 2006.285.16:42:04.89#ibcon#read 4, iclass 28, count 2 2006.285.16:42:04.89#ibcon#about to read 5, iclass 28, count 2 2006.285.16:42:04.89#ibcon#read 5, iclass 28, count 2 2006.285.16:42:04.89#ibcon#about to read 6, iclass 28, count 2 2006.285.16:42:04.89#ibcon#read 6, iclass 28, count 2 2006.285.16:42:04.89#ibcon#end of sib2, iclass 28, count 2 2006.285.16:42:04.89#ibcon#*mode == 0, iclass 28, count 2 2006.285.16:42:04.89#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.16:42:04.89#ibcon#[27=AT03-04\r\n] 2006.285.16:42:04.89#ibcon#*before write, iclass 28, count 2 2006.285.16:42:04.89#ibcon#enter sib2, iclass 28, count 2 2006.285.16:42:04.89#ibcon#flushed, iclass 28, count 2 2006.285.16:42:04.89#ibcon#about to write, iclass 28, count 2 2006.285.16:42:04.89#ibcon#wrote, iclass 28, count 2 2006.285.16:42:04.89#ibcon#about to read 3, iclass 28, count 2 2006.285.16:42:04.92#ibcon#read 3, iclass 28, count 2 2006.285.16:42:04.92#ibcon#about to read 4, iclass 28, count 2 2006.285.16:42:04.92#ibcon#read 4, iclass 28, count 2 2006.285.16:42:04.92#ibcon#about to read 5, iclass 28, count 2 2006.285.16:42:04.92#ibcon#read 5, iclass 28, count 2 2006.285.16:42:04.92#ibcon#about to read 6, iclass 28, count 2 2006.285.16:42:04.92#ibcon#read 6, iclass 28, count 2 2006.285.16:42:04.92#ibcon#end of sib2, iclass 28, count 2 2006.285.16:42:04.92#ibcon#*after write, iclass 28, count 2 2006.285.16:42:04.92#ibcon#*before return 0, iclass 28, count 2 2006.285.16:42:04.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:42:04.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.16:42:04.92#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.16:42:04.92#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:04.92#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:42:05.04#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:42:05.04#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:42:05.04#ibcon#enter wrdev, iclass 28, count 0 2006.285.16:42:05.04#ibcon#first serial, iclass 28, count 0 2006.285.16:42:05.04#ibcon#enter sib2, iclass 28, count 0 2006.285.16:42:05.04#ibcon#flushed, iclass 28, count 0 2006.285.16:42:05.04#ibcon#about to write, iclass 28, count 0 2006.285.16:42:05.04#ibcon#wrote, iclass 28, count 0 2006.285.16:42:05.04#ibcon#about to read 3, iclass 28, count 0 2006.285.16:42:05.06#ibcon#read 3, iclass 28, count 0 2006.285.16:42:05.06#ibcon#about to read 4, iclass 28, count 0 2006.285.16:42:05.06#ibcon#read 4, iclass 28, count 0 2006.285.16:42:05.06#ibcon#about to read 5, iclass 28, count 0 2006.285.16:42:05.06#ibcon#read 5, iclass 28, count 0 2006.285.16:42:05.06#ibcon#about to read 6, iclass 28, count 0 2006.285.16:42:05.06#ibcon#read 6, iclass 28, count 0 2006.285.16:42:05.06#ibcon#end of sib2, iclass 28, count 0 2006.285.16:42:05.06#ibcon#*mode == 0, iclass 28, count 0 2006.285.16:42:05.06#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.16:42:05.06#ibcon#[27=USB\r\n] 2006.285.16:42:05.06#ibcon#*before write, iclass 28, count 0 2006.285.16:42:05.06#ibcon#enter sib2, iclass 28, count 0 2006.285.16:42:05.06#ibcon#flushed, iclass 28, count 0 2006.285.16:42:05.06#ibcon#about to write, iclass 28, count 0 2006.285.16:42:05.06#ibcon#wrote, iclass 28, count 0 2006.285.16:42:05.06#ibcon#about to read 3, iclass 28, count 0 2006.285.16:42:05.09#ibcon#read 3, iclass 28, count 0 2006.285.16:42:05.09#ibcon#about to read 4, iclass 28, count 0 2006.285.16:42:05.09#ibcon#read 4, iclass 28, count 0 2006.285.16:42:05.09#ibcon#about to read 5, iclass 28, count 0 2006.285.16:42:05.09#ibcon#read 5, iclass 28, count 0 2006.285.16:42:05.09#ibcon#about to read 6, iclass 28, count 0 2006.285.16:42:05.09#ibcon#read 6, iclass 28, count 0 2006.285.16:42:05.09#ibcon#end of sib2, iclass 28, count 0 2006.285.16:42:05.09#ibcon#*after write, iclass 28, count 0 2006.285.16:42:05.09#ibcon#*before return 0, iclass 28, count 0 2006.285.16:42:05.09#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:42:05.09#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.16:42:05.09#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.16:42:05.09#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.16:42:05.09$vck44/vblo=4,679.99 2006.285.16:42:05.09#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.16:42:05.09#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.16:42:05.09#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:05.09#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:42:05.09#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:42:05.09#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:42:05.09#ibcon#enter wrdev, iclass 30, count 0 2006.285.16:42:05.09#ibcon#first serial, iclass 30, count 0 2006.285.16:42:05.09#ibcon#enter sib2, iclass 30, count 0 2006.285.16:42:05.09#ibcon#flushed, iclass 30, count 0 2006.285.16:42:05.09#ibcon#about to write, iclass 30, count 0 2006.285.16:42:05.09#ibcon#wrote, iclass 30, count 0 2006.285.16:42:05.09#ibcon#about to read 3, iclass 30, count 0 2006.285.16:42:05.11#ibcon#read 3, iclass 30, count 0 2006.285.16:42:05.11#ibcon#about to read 4, iclass 30, count 0 2006.285.16:42:05.11#ibcon#read 4, iclass 30, count 0 2006.285.16:42:05.11#ibcon#about to read 5, iclass 30, count 0 2006.285.16:42:05.11#ibcon#read 5, iclass 30, count 0 2006.285.16:42:05.11#ibcon#about to read 6, iclass 30, count 0 2006.285.16:42:05.11#ibcon#read 6, iclass 30, count 0 2006.285.16:42:05.11#ibcon#end of sib2, iclass 30, count 0 2006.285.16:42:05.11#ibcon#*mode == 0, iclass 30, count 0 2006.285.16:42:05.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.16:42:05.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.16:42:05.11#ibcon#*before write, iclass 30, count 0 2006.285.16:42:05.11#ibcon#enter sib2, iclass 30, count 0 2006.285.16:42:05.11#ibcon#flushed, iclass 30, count 0 2006.285.16:42:05.11#ibcon#about to write, iclass 30, count 0 2006.285.16:42:05.11#ibcon#wrote, iclass 30, count 0 2006.285.16:42:05.11#ibcon#about to read 3, iclass 30, count 0 2006.285.16:42:05.15#ibcon#read 3, iclass 30, count 0 2006.285.16:42:05.15#ibcon#about to read 4, iclass 30, count 0 2006.285.16:42:05.15#ibcon#read 4, iclass 30, count 0 2006.285.16:42:05.15#ibcon#about to read 5, iclass 30, count 0 2006.285.16:42:05.15#ibcon#read 5, iclass 30, count 0 2006.285.16:42:05.15#ibcon#about to read 6, iclass 30, count 0 2006.285.16:42:05.15#ibcon#read 6, iclass 30, count 0 2006.285.16:42:05.15#ibcon#end of sib2, iclass 30, count 0 2006.285.16:42:05.15#ibcon#*after write, iclass 30, count 0 2006.285.16:42:05.15#ibcon#*before return 0, iclass 30, count 0 2006.285.16:42:05.15#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:42:05.15#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.16:42:05.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.16:42:05.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.16:42:05.15$vck44/vb=4,5 2006.285.16:42:05.15#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.16:42:05.15#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.16:42:05.15#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:05.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:42:05.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:42:05.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:42:05.21#ibcon#enter wrdev, iclass 32, count 2 2006.285.16:42:05.21#ibcon#first serial, iclass 32, count 2 2006.285.16:42:05.21#ibcon#enter sib2, iclass 32, count 2 2006.285.16:42:05.21#ibcon#flushed, iclass 32, count 2 2006.285.16:42:05.21#ibcon#about to write, iclass 32, count 2 2006.285.16:42:05.21#ibcon#wrote, iclass 32, count 2 2006.285.16:42:05.21#ibcon#about to read 3, iclass 32, count 2 2006.285.16:42:05.23#ibcon#read 3, iclass 32, count 2 2006.285.16:42:05.23#ibcon#about to read 4, iclass 32, count 2 2006.285.16:42:05.23#ibcon#read 4, iclass 32, count 2 2006.285.16:42:05.23#ibcon#about to read 5, iclass 32, count 2 2006.285.16:42:05.23#ibcon#read 5, iclass 32, count 2 2006.285.16:42:05.23#ibcon#about to read 6, iclass 32, count 2 2006.285.16:42:05.23#ibcon#read 6, iclass 32, count 2 2006.285.16:42:05.23#ibcon#end of sib2, iclass 32, count 2 2006.285.16:42:05.23#ibcon#*mode == 0, iclass 32, count 2 2006.285.16:42:05.23#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.16:42:05.23#ibcon#[27=AT04-05\r\n] 2006.285.16:42:05.23#ibcon#*before write, iclass 32, count 2 2006.285.16:42:05.23#ibcon#enter sib2, iclass 32, count 2 2006.285.16:42:05.23#ibcon#flushed, iclass 32, count 2 2006.285.16:42:05.23#ibcon#about to write, iclass 32, count 2 2006.285.16:42:05.23#ibcon#wrote, iclass 32, count 2 2006.285.16:42:05.23#ibcon#about to read 3, iclass 32, count 2 2006.285.16:42:05.26#ibcon#read 3, iclass 32, count 2 2006.285.16:42:05.26#ibcon#about to read 4, iclass 32, count 2 2006.285.16:42:05.26#ibcon#read 4, iclass 32, count 2 2006.285.16:42:05.26#ibcon#about to read 5, iclass 32, count 2 2006.285.16:42:05.26#ibcon#read 5, iclass 32, count 2 2006.285.16:42:05.26#ibcon#about to read 6, iclass 32, count 2 2006.285.16:42:05.26#ibcon#read 6, iclass 32, count 2 2006.285.16:42:05.26#ibcon#end of sib2, iclass 32, count 2 2006.285.16:42:05.26#ibcon#*after write, iclass 32, count 2 2006.285.16:42:05.26#ibcon#*before return 0, iclass 32, count 2 2006.285.16:42:05.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:42:05.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.16:42:05.26#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.16:42:05.26#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:05.26#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:42:05.38#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:42:05.38#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:42:05.38#ibcon#enter wrdev, iclass 32, count 0 2006.285.16:42:05.38#ibcon#first serial, iclass 32, count 0 2006.285.16:42:05.38#ibcon#enter sib2, iclass 32, count 0 2006.285.16:42:05.38#ibcon#flushed, iclass 32, count 0 2006.285.16:42:05.38#ibcon#about to write, iclass 32, count 0 2006.285.16:42:05.38#ibcon#wrote, iclass 32, count 0 2006.285.16:42:05.38#ibcon#about to read 3, iclass 32, count 0 2006.285.16:42:05.40#ibcon#read 3, iclass 32, count 0 2006.285.16:42:05.40#ibcon#about to read 4, iclass 32, count 0 2006.285.16:42:05.40#ibcon#read 4, iclass 32, count 0 2006.285.16:42:05.40#ibcon#about to read 5, iclass 32, count 0 2006.285.16:42:05.40#ibcon#read 5, iclass 32, count 0 2006.285.16:42:05.40#ibcon#about to read 6, iclass 32, count 0 2006.285.16:42:05.40#ibcon#read 6, iclass 32, count 0 2006.285.16:42:05.40#ibcon#end of sib2, iclass 32, count 0 2006.285.16:42:05.40#ibcon#*mode == 0, iclass 32, count 0 2006.285.16:42:05.40#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.16:42:05.40#ibcon#[27=USB\r\n] 2006.285.16:42:05.40#ibcon#*before write, iclass 32, count 0 2006.285.16:42:05.40#ibcon#enter sib2, iclass 32, count 0 2006.285.16:42:05.40#ibcon#flushed, iclass 32, count 0 2006.285.16:42:05.40#ibcon#about to write, iclass 32, count 0 2006.285.16:42:05.40#ibcon#wrote, iclass 32, count 0 2006.285.16:42:05.40#ibcon#about to read 3, iclass 32, count 0 2006.285.16:42:05.43#ibcon#read 3, iclass 32, count 0 2006.285.16:42:05.47#ibcon#about to read 4, iclass 32, count 0 2006.285.16:42:05.47#ibcon#read 4, iclass 32, count 0 2006.285.16:42:05.47#ibcon#about to read 5, iclass 32, count 0 2006.285.16:42:05.47#ibcon#read 5, iclass 32, count 0 2006.285.16:42:05.47#ibcon#about to read 6, iclass 32, count 0 2006.285.16:42:05.47#ibcon#read 6, iclass 32, count 0 2006.285.16:42:05.47#ibcon#end of sib2, iclass 32, count 0 2006.285.16:42:05.47#ibcon#*after write, iclass 32, count 0 2006.285.16:42:05.47#ibcon#*before return 0, iclass 32, count 0 2006.285.16:42:05.47#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:42:05.47#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.16:42:05.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.16:42:05.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.16:42:05.47$vck44/vblo=5,709.99 2006.285.16:42:05.47#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.16:42:05.47#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.16:42:05.47#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:05.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:42:05.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:42:05.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:42:05.47#ibcon#enter wrdev, iclass 34, count 0 2006.285.16:42:05.47#ibcon#first serial, iclass 34, count 0 2006.285.16:42:05.47#ibcon#enter sib2, iclass 34, count 0 2006.285.16:42:05.47#ibcon#flushed, iclass 34, count 0 2006.285.16:42:05.47#ibcon#about to write, iclass 34, count 0 2006.285.16:42:05.47#ibcon#wrote, iclass 34, count 0 2006.285.16:42:05.47#ibcon#about to read 3, iclass 34, count 0 2006.285.16:42:05.48#ibcon#read 3, iclass 34, count 0 2006.285.16:42:05.48#ibcon#about to read 4, iclass 34, count 0 2006.285.16:42:05.48#ibcon#read 4, iclass 34, count 0 2006.285.16:42:05.48#ibcon#about to read 5, iclass 34, count 0 2006.285.16:42:05.48#ibcon#read 5, iclass 34, count 0 2006.285.16:42:05.48#ibcon#about to read 6, iclass 34, count 0 2006.285.16:42:05.48#ibcon#read 6, iclass 34, count 0 2006.285.16:42:05.48#ibcon#end of sib2, iclass 34, count 0 2006.285.16:42:05.48#ibcon#*mode == 0, iclass 34, count 0 2006.285.16:42:05.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.16:42:05.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.16:42:05.48#ibcon#*before write, iclass 34, count 0 2006.285.16:42:05.48#ibcon#enter sib2, iclass 34, count 0 2006.285.16:42:05.48#ibcon#flushed, iclass 34, count 0 2006.285.16:42:05.48#ibcon#about to write, iclass 34, count 0 2006.285.16:42:05.48#ibcon#wrote, iclass 34, count 0 2006.285.16:42:05.48#ibcon#about to read 3, iclass 34, count 0 2006.285.16:42:05.52#ibcon#read 3, iclass 34, count 0 2006.285.16:42:05.52#ibcon#about to read 4, iclass 34, count 0 2006.285.16:42:05.52#ibcon#read 4, iclass 34, count 0 2006.285.16:42:05.52#ibcon#about to read 5, iclass 34, count 0 2006.285.16:42:05.52#ibcon#read 5, iclass 34, count 0 2006.285.16:42:05.52#ibcon#about to read 6, iclass 34, count 0 2006.285.16:42:05.52#ibcon#read 6, iclass 34, count 0 2006.285.16:42:05.52#ibcon#end of sib2, iclass 34, count 0 2006.285.16:42:05.52#ibcon#*after write, iclass 34, count 0 2006.285.16:42:05.52#ibcon#*before return 0, iclass 34, count 0 2006.285.16:42:05.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:42:05.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.16:42:05.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.16:42:05.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.16:42:05.52$vck44/vb=5,4 2006.285.16:42:05.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.16:42:05.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.16:42:05.52#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:05.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:42:05.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:42:05.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:42:05.59#ibcon#enter wrdev, iclass 36, count 2 2006.285.16:42:05.59#ibcon#first serial, iclass 36, count 2 2006.285.16:42:05.59#ibcon#enter sib2, iclass 36, count 2 2006.285.16:42:05.59#ibcon#flushed, iclass 36, count 2 2006.285.16:42:05.59#ibcon#about to write, iclass 36, count 2 2006.285.16:42:05.59#ibcon#wrote, iclass 36, count 2 2006.285.16:42:05.59#ibcon#about to read 3, iclass 36, count 2 2006.285.16:42:05.61#ibcon#read 3, iclass 36, count 2 2006.285.16:42:05.61#ibcon#about to read 4, iclass 36, count 2 2006.285.16:42:05.61#ibcon#read 4, iclass 36, count 2 2006.285.16:42:05.61#ibcon#about to read 5, iclass 36, count 2 2006.285.16:42:05.61#ibcon#read 5, iclass 36, count 2 2006.285.16:42:05.61#ibcon#about to read 6, iclass 36, count 2 2006.285.16:42:05.61#ibcon#read 6, iclass 36, count 2 2006.285.16:42:05.61#ibcon#end of sib2, iclass 36, count 2 2006.285.16:42:05.61#ibcon#*mode == 0, iclass 36, count 2 2006.285.16:42:05.61#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.16:42:05.61#ibcon#[27=AT05-04\r\n] 2006.285.16:42:05.61#ibcon#*before write, iclass 36, count 2 2006.285.16:42:05.61#ibcon#enter sib2, iclass 36, count 2 2006.285.16:42:05.61#ibcon#flushed, iclass 36, count 2 2006.285.16:42:05.61#ibcon#about to write, iclass 36, count 2 2006.285.16:42:05.61#ibcon#wrote, iclass 36, count 2 2006.285.16:42:05.61#ibcon#about to read 3, iclass 36, count 2 2006.285.16:42:05.64#ibcon#read 3, iclass 36, count 2 2006.285.16:42:05.64#ibcon#about to read 4, iclass 36, count 2 2006.285.16:42:05.64#ibcon#read 4, iclass 36, count 2 2006.285.16:42:05.64#ibcon#about to read 5, iclass 36, count 2 2006.285.16:42:05.64#ibcon#read 5, iclass 36, count 2 2006.285.16:42:05.64#ibcon#about to read 6, iclass 36, count 2 2006.285.16:42:05.64#ibcon#read 6, iclass 36, count 2 2006.285.16:42:05.64#ibcon#end of sib2, iclass 36, count 2 2006.285.16:42:05.64#ibcon#*after write, iclass 36, count 2 2006.285.16:42:05.64#ibcon#*before return 0, iclass 36, count 2 2006.285.16:42:05.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:42:05.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.16:42:05.64#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.16:42:05.64#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:05.64#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:42:05.76#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:42:05.76#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:42:05.76#ibcon#enter wrdev, iclass 36, count 0 2006.285.16:42:05.76#ibcon#first serial, iclass 36, count 0 2006.285.16:42:05.76#ibcon#enter sib2, iclass 36, count 0 2006.285.16:42:05.76#ibcon#flushed, iclass 36, count 0 2006.285.16:42:05.76#ibcon#about to write, iclass 36, count 0 2006.285.16:42:05.76#ibcon#wrote, iclass 36, count 0 2006.285.16:42:05.76#ibcon#about to read 3, iclass 36, count 0 2006.285.16:42:05.78#ibcon#read 3, iclass 36, count 0 2006.285.16:42:05.78#ibcon#about to read 4, iclass 36, count 0 2006.285.16:42:05.78#ibcon#read 4, iclass 36, count 0 2006.285.16:42:05.78#ibcon#about to read 5, iclass 36, count 0 2006.285.16:42:05.78#ibcon#read 5, iclass 36, count 0 2006.285.16:42:05.78#ibcon#about to read 6, iclass 36, count 0 2006.285.16:42:05.78#ibcon#read 6, iclass 36, count 0 2006.285.16:42:05.78#ibcon#end of sib2, iclass 36, count 0 2006.285.16:42:05.78#ibcon#*mode == 0, iclass 36, count 0 2006.285.16:42:05.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.16:42:05.78#ibcon#[27=USB\r\n] 2006.285.16:42:05.78#ibcon#*before write, iclass 36, count 0 2006.285.16:42:05.78#ibcon#enter sib2, iclass 36, count 0 2006.285.16:42:05.78#ibcon#flushed, iclass 36, count 0 2006.285.16:42:05.78#ibcon#about to write, iclass 36, count 0 2006.285.16:42:05.78#ibcon#wrote, iclass 36, count 0 2006.285.16:42:05.78#ibcon#about to read 3, iclass 36, count 0 2006.285.16:42:05.81#ibcon#read 3, iclass 36, count 0 2006.285.16:42:05.81#ibcon#about to read 4, iclass 36, count 0 2006.285.16:42:05.81#ibcon#read 4, iclass 36, count 0 2006.285.16:42:05.81#ibcon#about to read 5, iclass 36, count 0 2006.285.16:42:05.81#ibcon#read 5, iclass 36, count 0 2006.285.16:42:05.81#ibcon#about to read 6, iclass 36, count 0 2006.285.16:42:05.81#ibcon#read 6, iclass 36, count 0 2006.285.16:42:05.81#ibcon#end of sib2, iclass 36, count 0 2006.285.16:42:05.81#ibcon#*after write, iclass 36, count 0 2006.285.16:42:05.81#ibcon#*before return 0, iclass 36, count 0 2006.285.16:42:05.81#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:42:05.81#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.16:42:05.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.16:42:05.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.16:42:05.81$vck44/vblo=6,719.99 2006.285.16:42:05.81#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.16:42:05.81#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.16:42:05.81#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:05.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:42:05.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:42:05.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:42:05.81#ibcon#enter wrdev, iclass 38, count 0 2006.285.16:42:05.81#ibcon#first serial, iclass 38, count 0 2006.285.16:42:05.81#ibcon#enter sib2, iclass 38, count 0 2006.285.16:42:05.81#ibcon#flushed, iclass 38, count 0 2006.285.16:42:05.81#ibcon#about to write, iclass 38, count 0 2006.285.16:42:05.81#ibcon#wrote, iclass 38, count 0 2006.285.16:42:05.81#ibcon#about to read 3, iclass 38, count 0 2006.285.16:42:05.83#ibcon#read 3, iclass 38, count 0 2006.285.16:42:05.83#ibcon#about to read 4, iclass 38, count 0 2006.285.16:42:05.83#ibcon#read 4, iclass 38, count 0 2006.285.16:42:05.83#ibcon#about to read 5, iclass 38, count 0 2006.285.16:42:05.83#ibcon#read 5, iclass 38, count 0 2006.285.16:42:05.83#ibcon#about to read 6, iclass 38, count 0 2006.285.16:42:05.83#ibcon#read 6, iclass 38, count 0 2006.285.16:42:05.83#ibcon#end of sib2, iclass 38, count 0 2006.285.16:42:05.83#ibcon#*mode == 0, iclass 38, count 0 2006.285.16:42:05.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.16:42:05.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.16:42:05.83#ibcon#*before write, iclass 38, count 0 2006.285.16:42:05.83#ibcon#enter sib2, iclass 38, count 0 2006.285.16:42:05.83#ibcon#flushed, iclass 38, count 0 2006.285.16:42:05.83#ibcon#about to write, iclass 38, count 0 2006.285.16:42:05.83#ibcon#wrote, iclass 38, count 0 2006.285.16:42:05.83#ibcon#about to read 3, iclass 38, count 0 2006.285.16:42:05.87#ibcon#read 3, iclass 38, count 0 2006.285.16:42:05.87#ibcon#about to read 4, iclass 38, count 0 2006.285.16:42:05.87#ibcon#read 4, iclass 38, count 0 2006.285.16:42:05.87#ibcon#about to read 5, iclass 38, count 0 2006.285.16:42:05.87#ibcon#read 5, iclass 38, count 0 2006.285.16:42:05.87#ibcon#about to read 6, iclass 38, count 0 2006.285.16:42:05.87#ibcon#read 6, iclass 38, count 0 2006.285.16:42:05.87#ibcon#end of sib2, iclass 38, count 0 2006.285.16:42:05.87#ibcon#*after write, iclass 38, count 0 2006.285.16:42:05.87#ibcon#*before return 0, iclass 38, count 0 2006.285.16:42:05.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:42:05.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.16:42:05.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.16:42:05.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.16:42:05.87$vck44/vb=6,3 2006.285.16:42:05.87#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.16:42:05.87#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.16:42:05.87#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:05.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:42:05.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:42:05.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:42:05.93#ibcon#enter wrdev, iclass 40, count 2 2006.285.16:42:05.93#ibcon#first serial, iclass 40, count 2 2006.285.16:42:05.93#ibcon#enter sib2, iclass 40, count 2 2006.285.16:42:05.93#ibcon#flushed, iclass 40, count 2 2006.285.16:42:05.93#ibcon#about to write, iclass 40, count 2 2006.285.16:42:05.93#ibcon#wrote, iclass 40, count 2 2006.285.16:42:05.93#ibcon#about to read 3, iclass 40, count 2 2006.285.16:42:05.95#ibcon#read 3, iclass 40, count 2 2006.285.16:42:05.95#ibcon#about to read 4, iclass 40, count 2 2006.285.16:42:05.95#ibcon#read 4, iclass 40, count 2 2006.285.16:42:05.95#ibcon#about to read 5, iclass 40, count 2 2006.285.16:42:05.95#ibcon#read 5, iclass 40, count 2 2006.285.16:42:05.95#ibcon#about to read 6, iclass 40, count 2 2006.285.16:42:05.95#ibcon#read 6, iclass 40, count 2 2006.285.16:42:05.95#ibcon#end of sib2, iclass 40, count 2 2006.285.16:42:05.95#ibcon#*mode == 0, iclass 40, count 2 2006.285.16:42:05.95#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.16:42:05.95#ibcon#[27=AT06-03\r\n] 2006.285.16:42:05.95#ibcon#*before write, iclass 40, count 2 2006.285.16:42:05.95#ibcon#enter sib2, iclass 40, count 2 2006.285.16:42:05.95#ibcon#flushed, iclass 40, count 2 2006.285.16:42:05.95#ibcon#about to write, iclass 40, count 2 2006.285.16:42:05.95#ibcon#wrote, iclass 40, count 2 2006.285.16:42:05.95#ibcon#about to read 3, iclass 40, count 2 2006.285.16:42:05.98#ibcon#read 3, iclass 40, count 2 2006.285.16:42:05.98#ibcon#about to read 4, iclass 40, count 2 2006.285.16:42:05.98#ibcon#read 4, iclass 40, count 2 2006.285.16:42:05.98#ibcon#about to read 5, iclass 40, count 2 2006.285.16:42:05.98#ibcon#read 5, iclass 40, count 2 2006.285.16:42:05.98#ibcon#about to read 6, iclass 40, count 2 2006.285.16:42:05.98#ibcon#read 6, iclass 40, count 2 2006.285.16:42:05.98#ibcon#end of sib2, iclass 40, count 2 2006.285.16:42:05.98#ibcon#*after write, iclass 40, count 2 2006.285.16:42:05.98#ibcon#*before return 0, iclass 40, count 2 2006.285.16:42:05.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:42:05.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.16:42:05.98#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.16:42:05.98#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:05.98#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:42:06.10#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:42:06.10#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:42:06.10#ibcon#enter wrdev, iclass 40, count 0 2006.285.16:42:06.10#ibcon#first serial, iclass 40, count 0 2006.285.16:42:06.10#ibcon#enter sib2, iclass 40, count 0 2006.285.16:42:06.10#ibcon#flushed, iclass 40, count 0 2006.285.16:42:06.10#ibcon#about to write, iclass 40, count 0 2006.285.16:42:06.10#ibcon#wrote, iclass 40, count 0 2006.285.16:42:06.10#ibcon#about to read 3, iclass 40, count 0 2006.285.16:42:06.12#ibcon#read 3, iclass 40, count 0 2006.285.16:42:06.12#ibcon#about to read 4, iclass 40, count 0 2006.285.16:42:06.12#ibcon#read 4, iclass 40, count 0 2006.285.16:42:06.12#ibcon#about to read 5, iclass 40, count 0 2006.285.16:42:06.12#ibcon#read 5, iclass 40, count 0 2006.285.16:42:06.12#ibcon#about to read 6, iclass 40, count 0 2006.285.16:42:06.12#ibcon#read 6, iclass 40, count 0 2006.285.16:42:06.12#ibcon#end of sib2, iclass 40, count 0 2006.285.16:42:06.12#ibcon#*mode == 0, iclass 40, count 0 2006.285.16:42:06.12#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.16:42:06.12#ibcon#[27=USB\r\n] 2006.285.16:42:06.12#ibcon#*before write, iclass 40, count 0 2006.285.16:42:06.12#ibcon#enter sib2, iclass 40, count 0 2006.285.16:42:06.12#ibcon#flushed, iclass 40, count 0 2006.285.16:42:06.12#ibcon#about to write, iclass 40, count 0 2006.285.16:42:06.12#ibcon#wrote, iclass 40, count 0 2006.285.16:42:06.12#ibcon#about to read 3, iclass 40, count 0 2006.285.16:42:06.15#ibcon#read 3, iclass 40, count 0 2006.285.16:42:06.15#ibcon#about to read 4, iclass 40, count 0 2006.285.16:42:06.15#ibcon#read 4, iclass 40, count 0 2006.285.16:42:06.15#ibcon#about to read 5, iclass 40, count 0 2006.285.16:42:06.15#ibcon#read 5, iclass 40, count 0 2006.285.16:42:06.15#ibcon#about to read 6, iclass 40, count 0 2006.285.16:42:06.15#ibcon#read 6, iclass 40, count 0 2006.285.16:42:06.15#ibcon#end of sib2, iclass 40, count 0 2006.285.16:42:06.15#ibcon#*after write, iclass 40, count 0 2006.285.16:42:06.15#ibcon#*before return 0, iclass 40, count 0 2006.285.16:42:06.15#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:42:06.15#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.16:42:06.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.16:42:06.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.16:42:06.15$vck44/vblo=7,734.99 2006.285.16:42:06.15#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.16:42:06.15#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.16:42:06.15#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:06.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:42:06.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:42:06.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:42:06.15#ibcon#enter wrdev, iclass 4, count 0 2006.285.16:42:06.15#ibcon#first serial, iclass 4, count 0 2006.285.16:42:06.15#ibcon#enter sib2, iclass 4, count 0 2006.285.16:42:06.15#ibcon#flushed, iclass 4, count 0 2006.285.16:42:06.15#ibcon#about to write, iclass 4, count 0 2006.285.16:42:06.15#ibcon#wrote, iclass 4, count 0 2006.285.16:42:06.15#ibcon#about to read 3, iclass 4, count 0 2006.285.16:42:06.17#ibcon#read 3, iclass 4, count 0 2006.285.16:42:06.17#ibcon#about to read 4, iclass 4, count 0 2006.285.16:42:06.17#ibcon#read 4, iclass 4, count 0 2006.285.16:42:06.17#ibcon#about to read 5, iclass 4, count 0 2006.285.16:42:06.17#ibcon#read 5, iclass 4, count 0 2006.285.16:42:06.17#ibcon#about to read 6, iclass 4, count 0 2006.285.16:42:06.17#ibcon#read 6, iclass 4, count 0 2006.285.16:42:06.17#ibcon#end of sib2, iclass 4, count 0 2006.285.16:42:06.17#ibcon#*mode == 0, iclass 4, count 0 2006.285.16:42:06.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.16:42:06.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.16:42:06.17#ibcon#*before write, iclass 4, count 0 2006.285.16:42:06.17#ibcon#enter sib2, iclass 4, count 0 2006.285.16:42:06.17#ibcon#flushed, iclass 4, count 0 2006.285.16:42:06.17#ibcon#about to write, iclass 4, count 0 2006.285.16:42:06.17#ibcon#wrote, iclass 4, count 0 2006.285.16:42:06.17#ibcon#about to read 3, iclass 4, count 0 2006.285.16:42:06.21#ibcon#read 3, iclass 4, count 0 2006.285.16:42:06.21#ibcon#about to read 4, iclass 4, count 0 2006.285.16:42:06.21#ibcon#read 4, iclass 4, count 0 2006.285.16:42:06.21#ibcon#about to read 5, iclass 4, count 0 2006.285.16:42:06.21#ibcon#read 5, iclass 4, count 0 2006.285.16:42:06.21#ibcon#about to read 6, iclass 4, count 0 2006.285.16:42:06.21#ibcon#read 6, iclass 4, count 0 2006.285.16:42:06.21#ibcon#end of sib2, iclass 4, count 0 2006.285.16:42:06.21#ibcon#*after write, iclass 4, count 0 2006.285.16:42:06.21#ibcon#*before return 0, iclass 4, count 0 2006.285.16:42:06.21#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:42:06.21#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:42:06.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.16:42:06.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.16:42:06.21$vck44/vb=7,4 2006.285.16:42:06.21#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.16:42:06.21#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.16:42:06.21#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:06.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:42:06.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:42:06.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:42:06.27#ibcon#enter wrdev, iclass 6, count 2 2006.285.16:42:06.27#ibcon#first serial, iclass 6, count 2 2006.285.16:42:06.27#ibcon#enter sib2, iclass 6, count 2 2006.285.16:42:06.27#ibcon#flushed, iclass 6, count 2 2006.285.16:42:06.27#ibcon#about to write, iclass 6, count 2 2006.285.16:42:06.27#ibcon#wrote, iclass 6, count 2 2006.285.16:42:06.27#ibcon#about to read 3, iclass 6, count 2 2006.285.16:42:06.29#ibcon#read 3, iclass 6, count 2 2006.285.16:42:06.29#ibcon#about to read 4, iclass 6, count 2 2006.285.16:42:06.29#ibcon#read 4, iclass 6, count 2 2006.285.16:42:06.29#ibcon#about to read 5, iclass 6, count 2 2006.285.16:42:06.29#ibcon#read 5, iclass 6, count 2 2006.285.16:42:06.29#ibcon#about to read 6, iclass 6, count 2 2006.285.16:42:06.29#ibcon#read 6, iclass 6, count 2 2006.285.16:42:06.29#ibcon#end of sib2, iclass 6, count 2 2006.285.16:42:06.29#ibcon#*mode == 0, iclass 6, count 2 2006.285.16:42:06.29#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.16:42:06.29#ibcon#[27=AT07-04\r\n] 2006.285.16:42:06.29#ibcon#*before write, iclass 6, count 2 2006.285.16:42:06.29#ibcon#enter sib2, iclass 6, count 2 2006.285.16:42:06.29#ibcon#flushed, iclass 6, count 2 2006.285.16:42:06.29#ibcon#about to write, iclass 6, count 2 2006.285.16:42:06.29#ibcon#wrote, iclass 6, count 2 2006.285.16:42:06.29#ibcon#about to read 3, iclass 6, count 2 2006.285.16:42:06.32#ibcon#read 3, iclass 6, count 2 2006.285.16:42:06.32#ibcon#about to read 4, iclass 6, count 2 2006.285.16:42:06.32#ibcon#read 4, iclass 6, count 2 2006.285.16:42:06.32#ibcon#about to read 5, iclass 6, count 2 2006.285.16:42:06.32#ibcon#read 5, iclass 6, count 2 2006.285.16:42:06.32#ibcon#about to read 6, iclass 6, count 2 2006.285.16:42:06.32#ibcon#read 6, iclass 6, count 2 2006.285.16:42:06.32#ibcon#end of sib2, iclass 6, count 2 2006.285.16:42:06.32#ibcon#*after write, iclass 6, count 2 2006.285.16:42:06.32#ibcon#*before return 0, iclass 6, count 2 2006.285.16:42:06.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:42:06.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.16:42:06.32#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.16:42:06.32#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:06.32#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:42:06.44#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:42:06.44#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:42:06.44#ibcon#enter wrdev, iclass 6, count 0 2006.285.16:42:06.44#ibcon#first serial, iclass 6, count 0 2006.285.16:42:06.44#ibcon#enter sib2, iclass 6, count 0 2006.285.16:42:06.44#ibcon#flushed, iclass 6, count 0 2006.285.16:42:06.44#ibcon#about to write, iclass 6, count 0 2006.285.16:42:06.44#ibcon#wrote, iclass 6, count 0 2006.285.16:42:06.44#ibcon#about to read 3, iclass 6, count 0 2006.285.16:42:06.46#ibcon#read 3, iclass 6, count 0 2006.285.16:42:06.46#ibcon#about to read 4, iclass 6, count 0 2006.285.16:42:06.46#ibcon#read 4, iclass 6, count 0 2006.285.16:42:06.46#ibcon#about to read 5, iclass 6, count 0 2006.285.16:42:06.46#ibcon#read 5, iclass 6, count 0 2006.285.16:42:06.46#ibcon#about to read 6, iclass 6, count 0 2006.285.16:42:06.46#ibcon#read 6, iclass 6, count 0 2006.285.16:42:06.46#ibcon#end of sib2, iclass 6, count 0 2006.285.16:42:06.46#ibcon#*mode == 0, iclass 6, count 0 2006.285.16:42:06.46#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.16:42:06.46#ibcon#[27=USB\r\n] 2006.285.16:42:06.46#ibcon#*before write, iclass 6, count 0 2006.285.16:42:06.46#ibcon#enter sib2, iclass 6, count 0 2006.285.16:42:06.46#ibcon#flushed, iclass 6, count 0 2006.285.16:42:06.46#ibcon#about to write, iclass 6, count 0 2006.285.16:42:06.46#ibcon#wrote, iclass 6, count 0 2006.285.16:42:06.46#ibcon#about to read 3, iclass 6, count 0 2006.285.16:42:06.49#ibcon#read 3, iclass 6, count 0 2006.285.16:42:06.49#ibcon#about to read 4, iclass 6, count 0 2006.285.16:42:06.49#ibcon#read 4, iclass 6, count 0 2006.285.16:42:06.49#ibcon#about to read 5, iclass 6, count 0 2006.285.16:42:06.49#ibcon#read 5, iclass 6, count 0 2006.285.16:42:06.49#ibcon#about to read 6, iclass 6, count 0 2006.285.16:42:06.49#ibcon#read 6, iclass 6, count 0 2006.285.16:42:06.49#ibcon#end of sib2, iclass 6, count 0 2006.285.16:42:06.49#ibcon#*after write, iclass 6, count 0 2006.285.16:42:06.49#ibcon#*before return 0, iclass 6, count 0 2006.285.16:42:06.49#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:42:06.49#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.16:42:06.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.16:42:06.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.16:42:06.49$vck44/vblo=8,744.99 2006.285.16:42:06.49#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.16:42:06.49#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.16:42:06.49#ibcon#ireg 17 cls_cnt 0 2006.285.16:42:06.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:42:06.49#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:42:06.49#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:42:06.49#ibcon#enter wrdev, iclass 10, count 0 2006.285.16:42:06.49#ibcon#first serial, iclass 10, count 0 2006.285.16:42:06.49#ibcon#enter sib2, iclass 10, count 0 2006.285.16:42:06.49#ibcon#flushed, iclass 10, count 0 2006.285.16:42:06.49#ibcon#about to write, iclass 10, count 0 2006.285.16:42:06.49#ibcon#wrote, iclass 10, count 0 2006.285.16:42:06.49#ibcon#about to read 3, iclass 10, count 0 2006.285.16:42:06.51#ibcon#read 3, iclass 10, count 0 2006.285.16:42:06.51#ibcon#about to read 4, iclass 10, count 0 2006.285.16:42:06.51#ibcon#read 4, iclass 10, count 0 2006.285.16:42:06.51#ibcon#about to read 5, iclass 10, count 0 2006.285.16:42:06.51#ibcon#read 5, iclass 10, count 0 2006.285.16:42:06.51#ibcon#about to read 6, iclass 10, count 0 2006.285.16:42:06.51#ibcon#read 6, iclass 10, count 0 2006.285.16:42:06.51#ibcon#end of sib2, iclass 10, count 0 2006.285.16:42:06.51#ibcon#*mode == 0, iclass 10, count 0 2006.285.16:42:06.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.16:42:06.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.16:42:06.51#ibcon#*before write, iclass 10, count 0 2006.285.16:42:06.51#ibcon#enter sib2, iclass 10, count 0 2006.285.16:42:06.51#ibcon#flushed, iclass 10, count 0 2006.285.16:42:06.51#ibcon#about to write, iclass 10, count 0 2006.285.16:42:06.51#ibcon#wrote, iclass 10, count 0 2006.285.16:42:06.51#ibcon#about to read 3, iclass 10, count 0 2006.285.16:42:06.55#ibcon#read 3, iclass 10, count 0 2006.285.16:42:06.55#ibcon#about to read 4, iclass 10, count 0 2006.285.16:42:06.55#ibcon#read 4, iclass 10, count 0 2006.285.16:42:06.55#ibcon#about to read 5, iclass 10, count 0 2006.285.16:42:06.55#ibcon#read 5, iclass 10, count 0 2006.285.16:42:06.55#ibcon#about to read 6, iclass 10, count 0 2006.285.16:42:06.55#ibcon#read 6, iclass 10, count 0 2006.285.16:42:06.55#ibcon#end of sib2, iclass 10, count 0 2006.285.16:42:06.55#ibcon#*after write, iclass 10, count 0 2006.285.16:42:06.55#ibcon#*before return 0, iclass 10, count 0 2006.285.16:42:06.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:42:06.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.16:42:06.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.16:42:06.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.16:42:06.55$vck44/vb=8,4 2006.285.16:42:06.55#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.16:42:06.55#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.16:42:06.55#ibcon#ireg 11 cls_cnt 2 2006.285.16:42:06.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:42:06.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:42:06.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:42:06.61#ibcon#enter wrdev, iclass 12, count 2 2006.285.16:42:06.61#ibcon#first serial, iclass 12, count 2 2006.285.16:42:06.61#ibcon#enter sib2, iclass 12, count 2 2006.285.16:42:06.61#ibcon#flushed, iclass 12, count 2 2006.285.16:42:06.61#ibcon#about to write, iclass 12, count 2 2006.285.16:42:06.61#ibcon#wrote, iclass 12, count 2 2006.285.16:42:06.61#ibcon#about to read 3, iclass 12, count 2 2006.285.16:42:06.63#ibcon#read 3, iclass 12, count 2 2006.285.16:42:06.63#ibcon#about to read 4, iclass 12, count 2 2006.285.16:42:06.63#ibcon#read 4, iclass 12, count 2 2006.285.16:42:06.63#ibcon#about to read 5, iclass 12, count 2 2006.285.16:42:06.63#ibcon#read 5, iclass 12, count 2 2006.285.16:42:06.63#ibcon#about to read 6, iclass 12, count 2 2006.285.16:42:06.63#ibcon#read 6, iclass 12, count 2 2006.285.16:42:06.63#ibcon#end of sib2, iclass 12, count 2 2006.285.16:42:06.63#ibcon#*mode == 0, iclass 12, count 2 2006.285.16:42:06.63#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.16:42:06.63#ibcon#[27=AT08-04\r\n] 2006.285.16:42:06.63#ibcon#*before write, iclass 12, count 2 2006.285.16:42:06.63#ibcon#enter sib2, iclass 12, count 2 2006.285.16:42:06.63#ibcon#flushed, iclass 12, count 2 2006.285.16:42:06.63#ibcon#about to write, iclass 12, count 2 2006.285.16:42:06.63#ibcon#wrote, iclass 12, count 2 2006.285.16:42:06.63#ibcon#about to read 3, iclass 12, count 2 2006.285.16:42:06.66#ibcon#read 3, iclass 12, count 2 2006.285.16:42:06.66#ibcon#about to read 4, iclass 12, count 2 2006.285.16:42:06.66#ibcon#read 4, iclass 12, count 2 2006.285.16:42:06.66#ibcon#about to read 5, iclass 12, count 2 2006.285.16:42:06.66#ibcon#read 5, iclass 12, count 2 2006.285.16:42:06.66#ibcon#about to read 6, iclass 12, count 2 2006.285.16:42:06.66#ibcon#read 6, iclass 12, count 2 2006.285.16:42:06.66#ibcon#end of sib2, iclass 12, count 2 2006.285.16:42:06.66#ibcon#*after write, iclass 12, count 2 2006.285.16:42:06.66#ibcon#*before return 0, iclass 12, count 2 2006.285.16:42:06.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:42:06.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.16:42:06.66#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.16:42:06.66#ibcon#ireg 7 cls_cnt 0 2006.285.16:42:06.66#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:42:06.78#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:42:06.78#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:42:06.78#ibcon#enter wrdev, iclass 12, count 0 2006.285.16:42:06.78#ibcon#first serial, iclass 12, count 0 2006.285.16:42:06.78#ibcon#enter sib2, iclass 12, count 0 2006.285.16:42:06.78#ibcon#flushed, iclass 12, count 0 2006.285.16:42:06.78#ibcon#about to write, iclass 12, count 0 2006.285.16:42:06.78#ibcon#wrote, iclass 12, count 0 2006.285.16:42:06.78#ibcon#about to read 3, iclass 12, count 0 2006.285.16:42:06.80#ibcon#read 3, iclass 12, count 0 2006.285.16:42:06.80#ibcon#about to read 4, iclass 12, count 0 2006.285.16:42:06.80#ibcon#read 4, iclass 12, count 0 2006.285.16:42:06.80#ibcon#about to read 5, iclass 12, count 0 2006.285.16:42:06.80#ibcon#read 5, iclass 12, count 0 2006.285.16:42:06.80#ibcon#about to read 6, iclass 12, count 0 2006.285.16:42:06.80#ibcon#read 6, iclass 12, count 0 2006.285.16:42:06.80#ibcon#end of sib2, iclass 12, count 0 2006.285.16:42:06.80#ibcon#*mode == 0, iclass 12, count 0 2006.285.16:42:06.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.16:42:06.80#ibcon#[27=USB\r\n] 2006.285.16:42:06.80#ibcon#*before write, iclass 12, count 0 2006.285.16:42:06.80#ibcon#enter sib2, iclass 12, count 0 2006.285.16:42:06.80#ibcon#flushed, iclass 12, count 0 2006.285.16:42:06.80#ibcon#about to write, iclass 12, count 0 2006.285.16:42:06.80#ibcon#wrote, iclass 12, count 0 2006.285.16:42:06.80#ibcon#about to read 3, iclass 12, count 0 2006.285.16:42:06.83#ibcon#read 3, iclass 12, count 0 2006.285.16:42:06.83#ibcon#about to read 4, iclass 12, count 0 2006.285.16:42:06.83#ibcon#read 4, iclass 12, count 0 2006.285.16:42:06.83#ibcon#about to read 5, iclass 12, count 0 2006.285.16:42:06.83#ibcon#read 5, iclass 12, count 0 2006.285.16:42:06.83#ibcon#about to read 6, iclass 12, count 0 2006.285.16:42:06.83#ibcon#read 6, iclass 12, count 0 2006.285.16:42:06.83#ibcon#end of sib2, iclass 12, count 0 2006.285.16:42:06.83#ibcon#*after write, iclass 12, count 0 2006.285.16:42:06.83#ibcon#*before return 0, iclass 12, count 0 2006.285.16:42:06.83#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:42:06.83#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.16:42:06.83#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.16:42:06.83#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.16:42:06.83$vck44/vabw=wide 2006.285.16:42:06.83#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.16:42:06.83#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.16:42:06.83#ibcon#ireg 8 cls_cnt 0 2006.285.16:42:06.83#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:42:06.83#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:42:06.83#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:42:06.83#ibcon#enter wrdev, iclass 14, count 0 2006.285.16:42:06.83#ibcon#first serial, iclass 14, count 0 2006.285.16:42:06.83#ibcon#enter sib2, iclass 14, count 0 2006.285.16:42:06.83#ibcon#flushed, iclass 14, count 0 2006.285.16:42:06.83#ibcon#about to write, iclass 14, count 0 2006.285.16:42:06.83#ibcon#wrote, iclass 14, count 0 2006.285.16:42:06.83#ibcon#about to read 3, iclass 14, count 0 2006.285.16:42:06.85#ibcon#read 3, iclass 14, count 0 2006.285.16:42:06.85#ibcon#about to read 4, iclass 14, count 0 2006.285.16:42:06.85#ibcon#read 4, iclass 14, count 0 2006.285.16:42:06.85#ibcon#about to read 5, iclass 14, count 0 2006.285.16:42:06.85#ibcon#read 5, iclass 14, count 0 2006.285.16:42:06.85#ibcon#about to read 6, iclass 14, count 0 2006.285.16:42:06.85#ibcon#read 6, iclass 14, count 0 2006.285.16:42:06.85#ibcon#end of sib2, iclass 14, count 0 2006.285.16:42:06.85#ibcon#*mode == 0, iclass 14, count 0 2006.285.16:42:06.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.16:42:06.85#ibcon#[25=BW32\r\n] 2006.285.16:42:06.85#ibcon#*before write, iclass 14, count 0 2006.285.16:42:06.85#ibcon#enter sib2, iclass 14, count 0 2006.285.16:42:06.85#ibcon#flushed, iclass 14, count 0 2006.285.16:42:06.85#ibcon#about to write, iclass 14, count 0 2006.285.16:42:06.85#ibcon#wrote, iclass 14, count 0 2006.285.16:42:06.85#ibcon#about to read 3, iclass 14, count 0 2006.285.16:42:06.88#ibcon#read 3, iclass 14, count 0 2006.285.16:42:06.88#ibcon#about to read 4, iclass 14, count 0 2006.285.16:42:06.88#ibcon#read 4, iclass 14, count 0 2006.285.16:42:06.88#ibcon#about to read 5, iclass 14, count 0 2006.285.16:42:06.88#ibcon#read 5, iclass 14, count 0 2006.285.16:42:06.88#ibcon#about to read 6, iclass 14, count 0 2006.285.16:42:06.88#ibcon#read 6, iclass 14, count 0 2006.285.16:42:06.88#ibcon#end of sib2, iclass 14, count 0 2006.285.16:42:06.88#ibcon#*after write, iclass 14, count 0 2006.285.16:42:06.88#ibcon#*before return 0, iclass 14, count 0 2006.285.16:42:06.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:42:06.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.16:42:06.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.16:42:06.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.16:42:06.88$vck44/vbbw=wide 2006.285.16:42:06.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.16:42:06.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.16:42:06.88#ibcon#ireg 8 cls_cnt 0 2006.285.16:42:06.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:42:06.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:42:06.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:42:06.95#ibcon#enter wrdev, iclass 16, count 0 2006.285.16:42:06.95#ibcon#first serial, iclass 16, count 0 2006.285.16:42:06.95#ibcon#enter sib2, iclass 16, count 0 2006.285.16:42:06.95#ibcon#flushed, iclass 16, count 0 2006.285.16:42:06.95#ibcon#about to write, iclass 16, count 0 2006.285.16:42:06.95#ibcon#wrote, iclass 16, count 0 2006.285.16:42:06.95#ibcon#about to read 3, iclass 16, count 0 2006.285.16:42:06.97#ibcon#read 3, iclass 16, count 0 2006.285.16:42:06.97#ibcon#about to read 4, iclass 16, count 0 2006.285.16:42:06.97#ibcon#read 4, iclass 16, count 0 2006.285.16:42:06.97#ibcon#about to read 5, iclass 16, count 0 2006.285.16:42:06.97#ibcon#read 5, iclass 16, count 0 2006.285.16:42:06.97#ibcon#about to read 6, iclass 16, count 0 2006.285.16:42:06.97#ibcon#read 6, iclass 16, count 0 2006.285.16:42:06.97#ibcon#end of sib2, iclass 16, count 0 2006.285.16:42:06.97#ibcon#*mode == 0, iclass 16, count 0 2006.285.16:42:06.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.16:42:06.97#ibcon#[27=BW32\r\n] 2006.285.16:42:06.97#ibcon#*before write, iclass 16, count 0 2006.285.16:42:06.97#ibcon#enter sib2, iclass 16, count 0 2006.285.16:42:06.97#ibcon#flushed, iclass 16, count 0 2006.285.16:42:06.97#ibcon#about to write, iclass 16, count 0 2006.285.16:42:06.97#ibcon#wrote, iclass 16, count 0 2006.285.16:42:06.97#ibcon#about to read 3, iclass 16, count 0 2006.285.16:42:07.00#ibcon#read 3, iclass 16, count 0 2006.285.16:42:07.00#ibcon#about to read 4, iclass 16, count 0 2006.285.16:42:07.00#ibcon#read 4, iclass 16, count 0 2006.285.16:42:07.00#ibcon#about to read 5, iclass 16, count 0 2006.285.16:42:07.00#ibcon#read 5, iclass 16, count 0 2006.285.16:42:07.00#ibcon#about to read 6, iclass 16, count 0 2006.285.16:42:07.00#ibcon#read 6, iclass 16, count 0 2006.285.16:42:07.00#ibcon#end of sib2, iclass 16, count 0 2006.285.16:42:07.00#ibcon#*after write, iclass 16, count 0 2006.285.16:42:07.00#ibcon#*before return 0, iclass 16, count 0 2006.285.16:42:07.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:42:07.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:42:07.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.16:42:07.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.16:42:07.00$setupk4/ifdk4 2006.285.16:42:07.00$ifdk4/lo= 2006.285.16:42:07.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.16:42:07.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.16:42:07.00$ifdk4/patch= 2006.285.16:42:07.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.16:42:07.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.16:42:07.01$setupk4/!*+20s 2006.285.16:42:10.68#abcon#<5=/14 0.7 1.5 18.31 921014.9\r\n> 2006.285.16:42:10.70#abcon#{5=INTERFACE CLEAR} 2006.285.16:42:10.76#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:42:19.14#trakl#Source acquired 2006.285.16:42:20.66$setupk4/"tpicd 2006.285.16:42:20.66$setupk4/echo=off 2006.285.16:42:20.66$setupk4/xlog=off 2006.285.16:42:20.66:!2006.285.16:44:16 2006.285.16:42:21.14#flagr#flagr/antenna,acquired 2006.285.16:44:16.00:preob 2006.285.16:44:16.13/onsource/TRACKING 2006.285.16:44:16.13:!2006.285.16:44:26 2006.285.16:44:26.00:"tape 2006.285.16:44:26.00:"st=record 2006.285.16:44:26.00:data_valid=on 2006.285.16:44:26.00:midob 2006.285.16:44:27.13/onsource/TRACKING 2006.285.16:44:27.13/wx/18.24,1014.9,93 2006.285.16:44:27.26/cable/+6.5017E-03 2006.285.16:44:28.35/va/01,07,usb,yes,32,35 2006.285.16:44:28.35/va/02,06,usb,yes,33,33 2006.285.16:44:28.35/va/03,07,usb,yes,32,34 2006.285.16:44:28.35/va/04,06,usb,yes,34,35 2006.285.16:44:28.35/va/05,03,usb,yes,33,33 2006.285.16:44:28.35/va/06,04,usb,yes,30,29 2006.285.16:44:28.35/va/07,04,usb,yes,30,31 2006.285.16:44:28.35/va/08,03,usb,yes,31,38 2006.285.16:44:28.58/valo/01,524.99,yes,locked 2006.285.16:44:28.58/valo/02,534.99,yes,locked 2006.285.16:44:28.58/valo/03,564.99,yes,locked 2006.285.16:44:28.58/valo/04,624.99,yes,locked 2006.285.16:44:28.58/valo/05,734.99,yes,locked 2006.285.16:44:28.58/valo/06,814.99,yes,locked 2006.285.16:44:28.58/valo/07,864.99,yes,locked 2006.285.16:44:28.58/valo/08,884.99,yes,locked 2006.285.16:44:29.67/vb/01,04,usb,yes,30,28 2006.285.16:44:29.67/vb/02,05,usb,yes,29,29 2006.285.16:44:29.67/vb/03,04,usb,yes,30,33 2006.285.16:44:29.67/vb/04,05,usb,yes,30,29 2006.285.16:44:29.67/vb/05,04,usb,yes,26,29 2006.285.16:44:29.67/vb/06,03,usb,yes,38,34 2006.285.16:44:29.67/vb/07,04,usb,yes,30,30 2006.285.16:44:29.67/vb/08,04,usb,yes,28,31 2006.285.16:44:29.90/vblo/01,629.99,yes,locked 2006.285.16:44:29.90/vblo/02,634.99,yes,locked 2006.285.16:44:29.90/vblo/03,649.99,yes,locked 2006.285.16:44:29.90/vblo/04,679.99,yes,locked 2006.285.16:44:29.90/vblo/05,709.99,yes,locked 2006.285.16:44:29.90/vblo/06,719.99,yes,locked 2006.285.16:44:29.90/vblo/07,734.99,yes,locked 2006.285.16:44:29.90/vblo/08,744.99,yes,locked 2006.285.16:44:30.05/vabw/8 2006.285.16:44:30.20/vbbw/8 2006.285.16:44:30.29/xfe/off,on,12.2 2006.285.16:44:30.68/ifatt/23,28,28,28 2006.285.16:44:31.07/fmout-gps/S +2.64E-07 2006.285.16:44:31.09:!2006.285.16:48:06 2006.285.16:48:06.01:data_valid=off 2006.285.16:48:06.01:"et 2006.285.16:48:06.01:!+3s 2006.285.16:48:09.02:"tape 2006.285.16:48:09.02:postob 2006.285.16:48:09.15/cable/+6.5020E-03 2006.285.16:48:09.15/wx/18.18,1014.9,93 2006.285.16:48:09.21/fmout-gps/S +2.68E-07 2006.285.16:48:09.21:scan_name=285-1651,jd0610,110 2006.285.16:48:09.21:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.285.16:48:11.14#flagr#flagr/antenna,new-source 2006.285.16:48:11.14:checkk5 2006.285.16:48:11.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.16:48:12.07/chk_autoobs//k5ts2/ autoobs is running! 2006.285.16:48:12.64/chk_autoobs//k5ts3/ autoobs is running! 2006.285.16:48:13.11/chk_autoobs//k5ts4/ autoobs is running! 2006.285.16:48:13.47/chk_obsdata//k5ts1/T2851644??a.dat file size is correct (nominal:880MB, actual:880MB). 2006.285.16:48:13.88/chk_obsdata//k5ts2/T2851644??b.dat file size is correct (nominal:880MB, actual:880MB). 2006.285.16:48:14.38/chk_obsdata//k5ts3/T2851644??c.dat file size is correct (nominal:880MB, actual:880MB). 2006.285.16:48:14.79/chk_obsdata//k5ts4/T2851644??d.dat file size is correct (nominal:880MB, actual:880MB). 2006.285.16:48:15.69/k5log//k5ts1_log_newline 2006.285.16:48:16.78/k5log//k5ts2_log_newline 2006.285.16:48:17.59/k5log//k5ts3_log_newline 2006.285.16:48:18.34/k5log//k5ts4_log_newline 2006.285.16:48:18.36/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.16:48:18.36:setupk4=1 2006.285.16:48:18.36$setupk4/echo=on 2006.285.16:48:18.36$setupk4/pcalon 2006.285.16:48:18.36$pcalon/"no phase cal control is implemented here 2006.285.16:48:18.36$setupk4/"tpicd=stop 2006.285.16:48:18.36$setupk4/"rec=synch_on 2006.285.16:48:18.36$setupk4/"rec_mode=128 2006.285.16:48:18.36$setupk4/!* 2006.285.16:48:18.36$setupk4/recpk4 2006.285.16:48:18.36$recpk4/recpatch= 2006.285.16:48:18.36$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.16:48:18.36$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.16:48:18.36$setupk4/vck44 2006.285.16:48:18.36$vck44/valo=1,524.99 2006.285.16:48:18.36#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.16:48:18.36#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.16:48:18.36#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:18.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:48:18.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:48:18.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:48:18.36#ibcon#enter wrdev, iclass 25, count 0 2006.285.16:48:18.36#ibcon#first serial, iclass 25, count 0 2006.285.16:48:18.36#ibcon#enter sib2, iclass 25, count 0 2006.285.16:48:18.36#ibcon#flushed, iclass 25, count 0 2006.285.16:48:18.36#ibcon#about to write, iclass 25, count 0 2006.285.16:48:18.36#ibcon#wrote, iclass 25, count 0 2006.285.16:48:18.36#ibcon#about to read 3, iclass 25, count 0 2006.285.16:48:18.38#ibcon#read 3, iclass 25, count 0 2006.285.16:48:18.38#ibcon#about to read 4, iclass 25, count 0 2006.285.16:48:18.38#ibcon#read 4, iclass 25, count 0 2006.285.16:48:18.38#ibcon#about to read 5, iclass 25, count 0 2006.285.16:48:18.38#ibcon#read 5, iclass 25, count 0 2006.285.16:48:18.38#ibcon#about to read 6, iclass 25, count 0 2006.285.16:48:18.38#ibcon#read 6, iclass 25, count 0 2006.285.16:48:18.38#ibcon#end of sib2, iclass 25, count 0 2006.285.16:48:18.38#ibcon#*mode == 0, iclass 25, count 0 2006.285.16:48:18.38#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.16:48:18.38#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.16:48:18.38#ibcon#*before write, iclass 25, count 0 2006.285.16:48:18.38#ibcon#enter sib2, iclass 25, count 0 2006.285.16:48:18.38#ibcon#flushed, iclass 25, count 0 2006.285.16:48:18.38#ibcon#about to write, iclass 25, count 0 2006.285.16:48:18.38#ibcon#wrote, iclass 25, count 0 2006.285.16:48:18.38#ibcon#about to read 3, iclass 25, count 0 2006.285.16:48:18.43#ibcon#read 3, iclass 25, count 0 2006.285.16:48:18.43#ibcon#about to read 4, iclass 25, count 0 2006.285.16:48:18.43#ibcon#read 4, iclass 25, count 0 2006.285.16:48:18.43#ibcon#about to read 5, iclass 25, count 0 2006.285.16:48:18.43#ibcon#read 5, iclass 25, count 0 2006.285.16:48:18.43#ibcon#about to read 6, iclass 25, count 0 2006.285.16:48:18.43#ibcon#read 6, iclass 25, count 0 2006.285.16:48:18.43#ibcon#end of sib2, iclass 25, count 0 2006.285.16:48:18.43#ibcon#*after write, iclass 25, count 0 2006.285.16:48:18.43#ibcon#*before return 0, iclass 25, count 0 2006.285.16:48:18.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:48:18.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:48:18.43#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.16:48:18.43#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.16:48:18.43$vck44/va=1,7 2006.285.16:48:18.43#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.16:48:18.43#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.16:48:18.43#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:18.43#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:48:18.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:48:18.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:48:18.43#ibcon#enter wrdev, iclass 27, count 2 2006.285.16:48:18.43#ibcon#first serial, iclass 27, count 2 2006.285.16:48:18.43#ibcon#enter sib2, iclass 27, count 2 2006.285.16:48:18.43#ibcon#flushed, iclass 27, count 2 2006.285.16:48:18.43#ibcon#about to write, iclass 27, count 2 2006.285.16:48:18.43#ibcon#wrote, iclass 27, count 2 2006.285.16:48:18.43#ibcon#about to read 3, iclass 27, count 2 2006.285.16:48:18.45#ibcon#read 3, iclass 27, count 2 2006.285.16:48:18.45#ibcon#about to read 4, iclass 27, count 2 2006.285.16:48:18.45#ibcon#read 4, iclass 27, count 2 2006.285.16:48:18.45#ibcon#about to read 5, iclass 27, count 2 2006.285.16:48:18.45#ibcon#read 5, iclass 27, count 2 2006.285.16:48:18.45#ibcon#about to read 6, iclass 27, count 2 2006.285.16:48:18.45#ibcon#read 6, iclass 27, count 2 2006.285.16:48:18.45#ibcon#end of sib2, iclass 27, count 2 2006.285.16:48:18.45#ibcon#*mode == 0, iclass 27, count 2 2006.285.16:48:18.45#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.16:48:18.45#ibcon#[25=AT01-07\r\n] 2006.285.16:48:18.45#ibcon#*before write, iclass 27, count 2 2006.285.16:48:18.45#ibcon#enter sib2, iclass 27, count 2 2006.285.16:48:18.45#ibcon#flushed, iclass 27, count 2 2006.285.16:48:18.45#ibcon#about to write, iclass 27, count 2 2006.285.16:48:18.45#ibcon#wrote, iclass 27, count 2 2006.285.16:48:18.45#ibcon#about to read 3, iclass 27, count 2 2006.285.16:48:18.48#ibcon#read 3, iclass 27, count 2 2006.285.16:48:18.48#ibcon#about to read 4, iclass 27, count 2 2006.285.16:48:18.48#ibcon#read 4, iclass 27, count 2 2006.285.16:48:18.48#ibcon#about to read 5, iclass 27, count 2 2006.285.16:48:18.48#ibcon#read 5, iclass 27, count 2 2006.285.16:48:18.48#ibcon#about to read 6, iclass 27, count 2 2006.285.16:48:18.48#ibcon#read 6, iclass 27, count 2 2006.285.16:48:18.48#ibcon#end of sib2, iclass 27, count 2 2006.285.16:48:18.48#ibcon#*after write, iclass 27, count 2 2006.285.16:48:18.48#ibcon#*before return 0, iclass 27, count 2 2006.285.16:48:18.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:48:18.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:48:18.48#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.16:48:18.48#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:18.48#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:48:18.60#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:48:18.60#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:48:18.60#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:48:18.60#ibcon#first serial, iclass 27, count 0 2006.285.16:48:18.60#ibcon#enter sib2, iclass 27, count 0 2006.285.16:48:18.60#ibcon#flushed, iclass 27, count 0 2006.285.16:48:18.60#ibcon#about to write, iclass 27, count 0 2006.285.16:48:18.60#ibcon#wrote, iclass 27, count 0 2006.285.16:48:18.60#ibcon#about to read 3, iclass 27, count 0 2006.285.16:48:18.62#ibcon#read 3, iclass 27, count 0 2006.285.16:48:18.62#ibcon#about to read 4, iclass 27, count 0 2006.285.16:48:18.62#ibcon#read 4, iclass 27, count 0 2006.285.16:48:18.62#ibcon#about to read 5, iclass 27, count 0 2006.285.16:48:18.62#ibcon#read 5, iclass 27, count 0 2006.285.16:48:18.62#ibcon#about to read 6, iclass 27, count 0 2006.285.16:48:18.62#ibcon#read 6, iclass 27, count 0 2006.285.16:48:18.62#ibcon#end of sib2, iclass 27, count 0 2006.285.16:48:18.62#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:48:18.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:48:18.62#ibcon#[25=USB\r\n] 2006.285.16:48:18.62#ibcon#*before write, iclass 27, count 0 2006.285.16:48:18.62#ibcon#enter sib2, iclass 27, count 0 2006.285.16:48:18.62#ibcon#flushed, iclass 27, count 0 2006.285.16:48:18.62#ibcon#about to write, iclass 27, count 0 2006.285.16:48:18.62#ibcon#wrote, iclass 27, count 0 2006.285.16:48:18.62#ibcon#about to read 3, iclass 27, count 0 2006.285.16:48:18.65#ibcon#read 3, iclass 27, count 0 2006.285.16:48:18.65#ibcon#about to read 4, iclass 27, count 0 2006.285.16:48:18.65#ibcon#read 4, iclass 27, count 0 2006.285.16:48:18.65#ibcon#about to read 5, iclass 27, count 0 2006.285.16:48:18.65#ibcon#read 5, iclass 27, count 0 2006.285.16:48:18.65#ibcon#about to read 6, iclass 27, count 0 2006.285.16:48:18.65#ibcon#read 6, iclass 27, count 0 2006.285.16:48:18.65#ibcon#end of sib2, iclass 27, count 0 2006.285.16:48:18.65#ibcon#*after write, iclass 27, count 0 2006.285.16:48:18.65#ibcon#*before return 0, iclass 27, count 0 2006.285.16:48:18.65#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:48:18.65#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:48:18.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:48:18.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:48:18.65$vck44/valo=2,534.99 2006.285.16:48:18.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.16:48:18.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.16:48:18.65#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:18.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:48:18.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:48:18.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:48:18.65#ibcon#enter wrdev, iclass 29, count 0 2006.285.16:48:18.65#ibcon#first serial, iclass 29, count 0 2006.285.16:48:18.65#ibcon#enter sib2, iclass 29, count 0 2006.285.16:48:18.65#ibcon#flushed, iclass 29, count 0 2006.285.16:48:18.65#ibcon#about to write, iclass 29, count 0 2006.285.16:48:18.65#ibcon#wrote, iclass 29, count 0 2006.285.16:48:18.65#ibcon#about to read 3, iclass 29, count 0 2006.285.16:48:18.67#ibcon#read 3, iclass 29, count 0 2006.285.16:48:18.67#ibcon#about to read 4, iclass 29, count 0 2006.285.16:48:18.67#ibcon#read 4, iclass 29, count 0 2006.285.16:48:18.67#ibcon#about to read 5, iclass 29, count 0 2006.285.16:48:18.67#ibcon#read 5, iclass 29, count 0 2006.285.16:48:18.67#ibcon#about to read 6, iclass 29, count 0 2006.285.16:48:18.67#ibcon#read 6, iclass 29, count 0 2006.285.16:48:18.67#ibcon#end of sib2, iclass 29, count 0 2006.285.16:48:18.67#ibcon#*mode == 0, iclass 29, count 0 2006.285.16:48:18.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.16:48:18.67#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.16:48:18.67#ibcon#*before write, iclass 29, count 0 2006.285.16:48:18.67#ibcon#enter sib2, iclass 29, count 0 2006.285.16:48:18.67#ibcon#flushed, iclass 29, count 0 2006.285.16:48:18.67#ibcon#about to write, iclass 29, count 0 2006.285.16:48:18.67#ibcon#wrote, iclass 29, count 0 2006.285.16:48:18.67#ibcon#about to read 3, iclass 29, count 0 2006.285.16:48:18.71#ibcon#read 3, iclass 29, count 0 2006.285.16:48:18.71#ibcon#about to read 4, iclass 29, count 0 2006.285.16:48:18.71#ibcon#read 4, iclass 29, count 0 2006.285.16:48:18.71#ibcon#about to read 5, iclass 29, count 0 2006.285.16:48:18.71#ibcon#read 5, iclass 29, count 0 2006.285.16:48:18.71#ibcon#about to read 6, iclass 29, count 0 2006.285.16:48:18.71#ibcon#read 6, iclass 29, count 0 2006.285.16:48:18.71#ibcon#end of sib2, iclass 29, count 0 2006.285.16:48:18.71#ibcon#*after write, iclass 29, count 0 2006.285.16:48:18.71#ibcon#*before return 0, iclass 29, count 0 2006.285.16:48:18.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:48:18.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:48:18.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.16:48:18.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.16:48:18.71$vck44/va=2,6 2006.285.16:48:18.71#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.16:48:18.71#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.16:48:18.71#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:18.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:48:18.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:48:18.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:48:18.77#ibcon#enter wrdev, iclass 31, count 2 2006.285.16:48:18.77#ibcon#first serial, iclass 31, count 2 2006.285.16:48:18.77#ibcon#enter sib2, iclass 31, count 2 2006.285.16:48:18.77#ibcon#flushed, iclass 31, count 2 2006.285.16:48:18.77#ibcon#about to write, iclass 31, count 2 2006.285.16:48:18.77#ibcon#wrote, iclass 31, count 2 2006.285.16:48:18.77#ibcon#about to read 3, iclass 31, count 2 2006.285.16:48:18.79#ibcon#read 3, iclass 31, count 2 2006.285.16:48:18.79#ibcon#about to read 4, iclass 31, count 2 2006.285.16:48:18.79#ibcon#read 4, iclass 31, count 2 2006.285.16:48:18.79#ibcon#about to read 5, iclass 31, count 2 2006.285.16:48:18.79#ibcon#read 5, iclass 31, count 2 2006.285.16:48:18.79#ibcon#about to read 6, iclass 31, count 2 2006.285.16:48:18.79#ibcon#read 6, iclass 31, count 2 2006.285.16:48:18.79#ibcon#end of sib2, iclass 31, count 2 2006.285.16:48:18.79#ibcon#*mode == 0, iclass 31, count 2 2006.285.16:48:18.79#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.16:48:18.79#ibcon#[25=AT02-06\r\n] 2006.285.16:48:18.79#ibcon#*before write, iclass 31, count 2 2006.285.16:48:18.79#ibcon#enter sib2, iclass 31, count 2 2006.285.16:48:18.79#ibcon#flushed, iclass 31, count 2 2006.285.16:48:18.79#ibcon#about to write, iclass 31, count 2 2006.285.16:48:18.79#ibcon#wrote, iclass 31, count 2 2006.285.16:48:18.79#ibcon#about to read 3, iclass 31, count 2 2006.285.16:48:18.82#ibcon#read 3, iclass 31, count 2 2006.285.16:48:18.82#ibcon#about to read 4, iclass 31, count 2 2006.285.16:48:18.82#ibcon#read 4, iclass 31, count 2 2006.285.16:48:18.82#ibcon#about to read 5, iclass 31, count 2 2006.285.16:48:18.82#ibcon#read 5, iclass 31, count 2 2006.285.16:48:18.82#ibcon#about to read 6, iclass 31, count 2 2006.285.16:48:18.82#ibcon#read 6, iclass 31, count 2 2006.285.16:48:18.82#ibcon#end of sib2, iclass 31, count 2 2006.285.16:48:18.82#ibcon#*after write, iclass 31, count 2 2006.285.16:48:18.82#ibcon#*before return 0, iclass 31, count 2 2006.285.16:48:18.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:48:18.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:48:18.82#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.16:48:18.82#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:18.82#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:48:18.94#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:48:18.94#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:48:18.94#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:48:18.94#ibcon#first serial, iclass 31, count 0 2006.285.16:48:18.94#ibcon#enter sib2, iclass 31, count 0 2006.285.16:48:18.94#ibcon#flushed, iclass 31, count 0 2006.285.16:48:18.94#ibcon#about to write, iclass 31, count 0 2006.285.16:48:18.94#ibcon#wrote, iclass 31, count 0 2006.285.16:48:18.94#ibcon#about to read 3, iclass 31, count 0 2006.285.16:48:18.96#ibcon#read 3, iclass 31, count 0 2006.285.16:48:18.96#ibcon#about to read 4, iclass 31, count 0 2006.285.16:48:18.96#ibcon#read 4, iclass 31, count 0 2006.285.16:48:18.96#ibcon#about to read 5, iclass 31, count 0 2006.285.16:48:18.96#ibcon#read 5, iclass 31, count 0 2006.285.16:48:18.96#ibcon#about to read 6, iclass 31, count 0 2006.285.16:48:18.96#ibcon#read 6, iclass 31, count 0 2006.285.16:48:18.96#ibcon#end of sib2, iclass 31, count 0 2006.285.16:48:18.96#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:48:18.96#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:48:18.96#ibcon#[25=USB\r\n] 2006.285.16:48:18.96#ibcon#*before write, iclass 31, count 0 2006.285.16:48:18.96#ibcon#enter sib2, iclass 31, count 0 2006.285.16:48:18.96#ibcon#flushed, iclass 31, count 0 2006.285.16:48:18.96#ibcon#about to write, iclass 31, count 0 2006.285.16:48:18.96#ibcon#wrote, iclass 31, count 0 2006.285.16:48:18.96#ibcon#about to read 3, iclass 31, count 0 2006.285.16:48:18.99#ibcon#read 3, iclass 31, count 0 2006.285.16:48:18.99#ibcon#about to read 4, iclass 31, count 0 2006.285.16:48:18.99#ibcon#read 4, iclass 31, count 0 2006.285.16:48:18.99#ibcon#about to read 5, iclass 31, count 0 2006.285.16:48:18.99#ibcon#read 5, iclass 31, count 0 2006.285.16:48:18.99#ibcon#about to read 6, iclass 31, count 0 2006.285.16:48:18.99#ibcon#read 6, iclass 31, count 0 2006.285.16:48:18.99#ibcon#end of sib2, iclass 31, count 0 2006.285.16:48:18.99#ibcon#*after write, iclass 31, count 0 2006.285.16:48:18.99#ibcon#*before return 0, iclass 31, count 0 2006.285.16:48:18.99#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:48:18.99#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:48:18.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:48:18.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:48:18.99$vck44/valo=3,564.99 2006.285.16:48:18.99#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.16:48:18.99#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.16:48:18.99#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:18.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:48:18.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:48:18.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:48:18.99#ibcon#enter wrdev, iclass 33, count 0 2006.285.16:48:18.99#ibcon#first serial, iclass 33, count 0 2006.285.16:48:18.99#ibcon#enter sib2, iclass 33, count 0 2006.285.16:48:18.99#ibcon#flushed, iclass 33, count 0 2006.285.16:48:18.99#ibcon#about to write, iclass 33, count 0 2006.285.16:48:18.99#ibcon#wrote, iclass 33, count 0 2006.285.16:48:18.99#ibcon#about to read 3, iclass 33, count 0 2006.285.16:48:19.01#ibcon#read 3, iclass 33, count 0 2006.285.16:48:19.68#ibcon#about to read 4, iclass 33, count 0 2006.285.16:48:19.68#ibcon#read 4, iclass 33, count 0 2006.285.16:48:19.68#ibcon#about to read 5, iclass 33, count 0 2006.285.16:48:19.68#ibcon#read 5, iclass 33, count 0 2006.285.16:48:19.68#ibcon#about to read 6, iclass 33, count 0 2006.285.16:48:19.68#ibcon#read 6, iclass 33, count 0 2006.285.16:48:19.68#ibcon#end of sib2, iclass 33, count 0 2006.285.16:48:19.68#ibcon#*mode == 0, iclass 33, count 0 2006.285.16:48:19.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.16:48:19.68#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.16:48:19.68#ibcon#*before write, iclass 33, count 0 2006.285.16:48:19.68#ibcon#enter sib2, iclass 33, count 0 2006.285.16:48:19.68#ibcon#flushed, iclass 33, count 0 2006.285.16:48:19.68#ibcon#about to write, iclass 33, count 0 2006.285.16:48:19.68#ibcon#wrote, iclass 33, count 0 2006.285.16:48:19.68#ibcon#about to read 3, iclass 33, count 0 2006.285.16:48:19.72#ibcon#read 3, iclass 33, count 0 2006.285.16:48:19.72#ibcon#about to read 4, iclass 33, count 0 2006.285.16:48:19.72#ibcon#read 4, iclass 33, count 0 2006.285.16:48:19.72#ibcon#about to read 5, iclass 33, count 0 2006.285.16:48:19.72#ibcon#read 5, iclass 33, count 0 2006.285.16:48:19.72#ibcon#about to read 6, iclass 33, count 0 2006.285.16:48:19.72#ibcon#read 6, iclass 33, count 0 2006.285.16:48:19.72#ibcon#end of sib2, iclass 33, count 0 2006.285.16:48:19.72#ibcon#*after write, iclass 33, count 0 2006.285.16:48:19.72#ibcon#*before return 0, iclass 33, count 0 2006.285.16:48:19.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:48:19.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:48:19.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.16:48:19.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.16:48:19.72$vck44/va=3,7 2006.285.16:48:19.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.16:48:19.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.16:48:19.72#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:19.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:48:19.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:48:19.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:48:19.72#ibcon#enter wrdev, iclass 35, count 2 2006.285.16:48:19.72#ibcon#first serial, iclass 35, count 2 2006.285.16:48:19.72#ibcon#enter sib2, iclass 35, count 2 2006.285.16:48:19.72#ibcon#flushed, iclass 35, count 2 2006.285.16:48:19.72#ibcon#about to write, iclass 35, count 2 2006.285.16:48:19.72#ibcon#wrote, iclass 35, count 2 2006.285.16:48:19.72#ibcon#about to read 3, iclass 35, count 2 2006.285.16:48:19.74#ibcon#read 3, iclass 35, count 2 2006.285.16:48:19.74#ibcon#about to read 4, iclass 35, count 2 2006.285.16:48:19.74#ibcon#read 4, iclass 35, count 2 2006.285.16:48:19.74#ibcon#about to read 5, iclass 35, count 2 2006.285.16:48:19.74#ibcon#read 5, iclass 35, count 2 2006.285.16:48:19.74#ibcon#about to read 6, iclass 35, count 2 2006.285.16:48:19.74#ibcon#read 6, iclass 35, count 2 2006.285.16:48:19.74#ibcon#end of sib2, iclass 35, count 2 2006.285.16:48:19.74#ibcon#*mode == 0, iclass 35, count 2 2006.285.16:48:19.74#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.16:48:19.74#ibcon#[25=AT03-07\r\n] 2006.285.16:48:19.74#ibcon#*before write, iclass 35, count 2 2006.285.16:48:19.74#ibcon#enter sib2, iclass 35, count 2 2006.285.16:48:19.74#ibcon#flushed, iclass 35, count 2 2006.285.16:48:19.74#ibcon#about to write, iclass 35, count 2 2006.285.16:48:19.74#ibcon#wrote, iclass 35, count 2 2006.285.16:48:19.74#ibcon#about to read 3, iclass 35, count 2 2006.285.16:48:19.77#ibcon#read 3, iclass 35, count 2 2006.285.16:48:19.77#ibcon#about to read 4, iclass 35, count 2 2006.285.16:48:19.77#ibcon#read 4, iclass 35, count 2 2006.285.16:48:19.77#ibcon#about to read 5, iclass 35, count 2 2006.285.16:48:19.77#ibcon#read 5, iclass 35, count 2 2006.285.16:48:19.77#ibcon#about to read 6, iclass 35, count 2 2006.285.16:48:19.77#ibcon#read 6, iclass 35, count 2 2006.285.16:48:19.77#ibcon#end of sib2, iclass 35, count 2 2006.285.16:48:19.77#ibcon#*after write, iclass 35, count 2 2006.285.16:48:19.77#ibcon#*before return 0, iclass 35, count 2 2006.285.16:48:19.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:48:19.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:48:19.77#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.16:48:19.77#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:19.77#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:48:19.89#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:48:19.89#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:48:19.89#ibcon#enter wrdev, iclass 35, count 0 2006.285.16:48:19.89#ibcon#first serial, iclass 35, count 0 2006.285.16:48:19.89#ibcon#enter sib2, iclass 35, count 0 2006.285.16:48:19.89#ibcon#flushed, iclass 35, count 0 2006.285.16:48:19.89#ibcon#about to write, iclass 35, count 0 2006.285.16:48:19.89#ibcon#wrote, iclass 35, count 0 2006.285.16:48:19.89#ibcon#about to read 3, iclass 35, count 0 2006.285.16:48:19.91#ibcon#read 3, iclass 35, count 0 2006.285.16:48:19.91#ibcon#about to read 4, iclass 35, count 0 2006.285.16:48:19.91#ibcon#read 4, iclass 35, count 0 2006.285.16:48:19.91#ibcon#about to read 5, iclass 35, count 0 2006.285.16:48:19.91#ibcon#read 5, iclass 35, count 0 2006.285.16:48:19.91#ibcon#about to read 6, iclass 35, count 0 2006.285.16:48:19.91#ibcon#read 6, iclass 35, count 0 2006.285.16:48:19.91#ibcon#end of sib2, iclass 35, count 0 2006.285.16:48:19.91#ibcon#*mode == 0, iclass 35, count 0 2006.285.16:48:19.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.16:48:19.91#ibcon#[25=USB\r\n] 2006.285.16:48:19.91#ibcon#*before write, iclass 35, count 0 2006.285.16:48:19.91#ibcon#enter sib2, iclass 35, count 0 2006.285.16:48:19.91#ibcon#flushed, iclass 35, count 0 2006.285.16:48:19.91#ibcon#about to write, iclass 35, count 0 2006.285.16:48:19.91#ibcon#wrote, iclass 35, count 0 2006.285.16:48:19.91#ibcon#about to read 3, iclass 35, count 0 2006.285.16:48:19.94#ibcon#read 3, iclass 35, count 0 2006.285.16:48:19.94#ibcon#about to read 4, iclass 35, count 0 2006.285.16:48:19.94#ibcon#read 4, iclass 35, count 0 2006.285.16:48:19.94#ibcon#about to read 5, iclass 35, count 0 2006.285.16:48:19.94#ibcon#read 5, iclass 35, count 0 2006.285.16:48:19.94#ibcon#about to read 6, iclass 35, count 0 2006.285.16:48:19.94#ibcon#read 6, iclass 35, count 0 2006.285.16:48:19.94#ibcon#end of sib2, iclass 35, count 0 2006.285.16:48:19.94#ibcon#*after write, iclass 35, count 0 2006.285.16:48:19.94#ibcon#*before return 0, iclass 35, count 0 2006.285.16:48:19.94#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:48:19.94#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:48:19.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.16:48:19.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.16:48:19.94$vck44/valo=4,624.99 2006.285.16:48:19.94#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.16:48:19.94#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.16:48:19.94#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:19.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:48:19.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:48:19.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:48:19.94#ibcon#enter wrdev, iclass 37, count 0 2006.285.16:48:19.94#ibcon#first serial, iclass 37, count 0 2006.285.16:48:19.94#ibcon#enter sib2, iclass 37, count 0 2006.285.16:48:19.94#ibcon#flushed, iclass 37, count 0 2006.285.16:48:19.94#ibcon#about to write, iclass 37, count 0 2006.285.16:48:19.94#ibcon#wrote, iclass 37, count 0 2006.285.16:48:19.94#ibcon#about to read 3, iclass 37, count 0 2006.285.16:48:19.96#ibcon#read 3, iclass 37, count 0 2006.285.16:48:20.22#ibcon#about to read 4, iclass 37, count 0 2006.285.16:48:20.22#ibcon#read 4, iclass 37, count 0 2006.285.16:48:20.22#ibcon#about to read 5, iclass 37, count 0 2006.285.16:48:20.22#ibcon#read 5, iclass 37, count 0 2006.285.16:48:20.22#ibcon#about to read 6, iclass 37, count 0 2006.285.16:48:20.22#ibcon#read 6, iclass 37, count 0 2006.285.16:48:20.22#ibcon#end of sib2, iclass 37, count 0 2006.285.16:48:20.22#ibcon#*mode == 0, iclass 37, count 0 2006.285.16:48:20.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.16:48:20.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.16:48:20.22#ibcon#*before write, iclass 37, count 0 2006.285.16:48:20.22#ibcon#enter sib2, iclass 37, count 0 2006.285.16:48:20.22#ibcon#flushed, iclass 37, count 0 2006.285.16:48:20.22#ibcon#about to write, iclass 37, count 0 2006.285.16:48:20.22#ibcon#wrote, iclass 37, count 0 2006.285.16:48:20.22#ibcon#about to read 3, iclass 37, count 0 2006.285.16:48:20.26#ibcon#read 3, iclass 37, count 0 2006.285.16:48:20.26#ibcon#about to read 4, iclass 37, count 0 2006.285.16:48:20.26#ibcon#read 4, iclass 37, count 0 2006.285.16:48:20.26#ibcon#about to read 5, iclass 37, count 0 2006.285.16:48:20.26#ibcon#read 5, iclass 37, count 0 2006.285.16:48:20.26#ibcon#about to read 6, iclass 37, count 0 2006.285.16:48:20.26#ibcon#read 6, iclass 37, count 0 2006.285.16:48:20.26#ibcon#end of sib2, iclass 37, count 0 2006.285.16:48:20.26#ibcon#*after write, iclass 37, count 0 2006.285.16:48:20.26#ibcon#*before return 0, iclass 37, count 0 2006.285.16:48:20.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:48:20.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:48:20.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.16:48:20.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.16:48:20.26$vck44/va=4,6 2006.285.16:48:20.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.16:48:20.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.16:48:20.26#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:20.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:48:20.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:48:20.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:48:20.26#ibcon#enter wrdev, iclass 39, count 2 2006.285.16:48:20.26#ibcon#first serial, iclass 39, count 2 2006.285.16:48:20.26#ibcon#enter sib2, iclass 39, count 2 2006.285.16:48:20.26#ibcon#flushed, iclass 39, count 2 2006.285.16:48:20.26#ibcon#about to write, iclass 39, count 2 2006.285.16:48:20.26#ibcon#wrote, iclass 39, count 2 2006.285.16:48:20.26#ibcon#about to read 3, iclass 39, count 2 2006.285.16:48:20.28#ibcon#read 3, iclass 39, count 2 2006.285.16:48:20.28#ibcon#about to read 4, iclass 39, count 2 2006.285.16:48:20.28#ibcon#read 4, iclass 39, count 2 2006.285.16:48:20.28#ibcon#about to read 5, iclass 39, count 2 2006.285.16:48:20.28#ibcon#read 5, iclass 39, count 2 2006.285.16:48:20.28#ibcon#about to read 6, iclass 39, count 2 2006.285.16:48:20.28#ibcon#read 6, iclass 39, count 2 2006.285.16:48:20.28#ibcon#end of sib2, iclass 39, count 2 2006.285.16:48:20.28#ibcon#*mode == 0, iclass 39, count 2 2006.285.16:48:20.28#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.16:48:20.28#ibcon#[25=AT04-06\r\n] 2006.285.16:48:20.28#ibcon#*before write, iclass 39, count 2 2006.285.16:48:20.28#ibcon#enter sib2, iclass 39, count 2 2006.285.16:48:20.28#ibcon#flushed, iclass 39, count 2 2006.285.16:48:20.28#ibcon#about to write, iclass 39, count 2 2006.285.16:48:20.28#ibcon#wrote, iclass 39, count 2 2006.285.16:48:20.28#ibcon#about to read 3, iclass 39, count 2 2006.285.16:48:20.31#ibcon#read 3, iclass 39, count 2 2006.285.16:48:20.31#ibcon#about to read 4, iclass 39, count 2 2006.285.16:48:20.31#ibcon#read 4, iclass 39, count 2 2006.285.16:48:20.31#ibcon#about to read 5, iclass 39, count 2 2006.285.16:48:20.31#ibcon#read 5, iclass 39, count 2 2006.285.16:48:20.31#ibcon#about to read 6, iclass 39, count 2 2006.285.16:48:20.31#ibcon#read 6, iclass 39, count 2 2006.285.16:48:20.31#ibcon#end of sib2, iclass 39, count 2 2006.285.16:48:20.31#ibcon#*after write, iclass 39, count 2 2006.285.16:48:20.31#ibcon#*before return 0, iclass 39, count 2 2006.285.16:48:20.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:48:20.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:48:20.31#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.16:48:20.31#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:20.31#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:48:20.43#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:48:20.43#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:48:20.43#ibcon#enter wrdev, iclass 39, count 0 2006.285.16:48:20.43#ibcon#first serial, iclass 39, count 0 2006.285.16:48:20.43#ibcon#enter sib2, iclass 39, count 0 2006.285.16:48:20.43#ibcon#flushed, iclass 39, count 0 2006.285.16:48:20.43#ibcon#about to write, iclass 39, count 0 2006.285.16:48:20.43#ibcon#wrote, iclass 39, count 0 2006.285.16:48:20.43#ibcon#about to read 3, iclass 39, count 0 2006.285.16:48:20.45#ibcon#read 3, iclass 39, count 0 2006.285.16:48:20.45#ibcon#about to read 4, iclass 39, count 0 2006.285.16:48:20.45#ibcon#read 4, iclass 39, count 0 2006.285.16:48:20.45#ibcon#about to read 5, iclass 39, count 0 2006.285.16:48:20.45#ibcon#read 5, iclass 39, count 0 2006.285.16:48:20.45#ibcon#about to read 6, iclass 39, count 0 2006.285.16:48:20.45#ibcon#read 6, iclass 39, count 0 2006.285.16:48:20.45#ibcon#end of sib2, iclass 39, count 0 2006.285.16:48:20.45#ibcon#*mode == 0, iclass 39, count 0 2006.285.16:48:20.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.16:48:20.45#ibcon#[25=USB\r\n] 2006.285.16:48:20.45#ibcon#*before write, iclass 39, count 0 2006.285.16:48:20.45#ibcon#enter sib2, iclass 39, count 0 2006.285.16:48:20.45#ibcon#flushed, iclass 39, count 0 2006.285.16:48:20.45#ibcon#about to write, iclass 39, count 0 2006.285.16:48:20.45#ibcon#wrote, iclass 39, count 0 2006.285.16:48:20.45#ibcon#about to read 3, iclass 39, count 0 2006.285.16:48:20.48#ibcon#read 3, iclass 39, count 0 2006.285.16:48:20.48#ibcon#about to read 4, iclass 39, count 0 2006.285.16:48:20.48#ibcon#read 4, iclass 39, count 0 2006.285.16:48:20.48#ibcon#about to read 5, iclass 39, count 0 2006.285.16:48:20.48#ibcon#read 5, iclass 39, count 0 2006.285.16:48:20.48#ibcon#about to read 6, iclass 39, count 0 2006.285.16:48:20.48#ibcon#read 6, iclass 39, count 0 2006.285.16:48:20.48#ibcon#end of sib2, iclass 39, count 0 2006.285.16:48:20.48#ibcon#*after write, iclass 39, count 0 2006.285.16:48:20.48#ibcon#*before return 0, iclass 39, count 0 2006.285.16:48:20.48#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:48:20.48#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:48:20.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.16:48:20.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.16:48:20.48$vck44/valo=5,734.99 2006.285.16:48:20.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.16:48:20.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.16:48:20.48#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:20.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:48:20.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:48:20.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:48:20.48#ibcon#enter wrdev, iclass 3, count 0 2006.285.16:48:20.48#ibcon#first serial, iclass 3, count 0 2006.285.16:48:20.48#ibcon#enter sib2, iclass 3, count 0 2006.285.16:48:20.48#ibcon#flushed, iclass 3, count 0 2006.285.16:48:20.48#ibcon#about to write, iclass 3, count 0 2006.285.16:48:20.48#ibcon#wrote, iclass 3, count 0 2006.285.16:48:20.48#ibcon#about to read 3, iclass 3, count 0 2006.285.16:48:20.50#ibcon#read 3, iclass 3, count 0 2006.285.16:48:20.50#ibcon#about to read 4, iclass 3, count 0 2006.285.16:48:20.50#ibcon#read 4, iclass 3, count 0 2006.285.16:48:20.50#ibcon#about to read 5, iclass 3, count 0 2006.285.16:48:20.50#ibcon#read 5, iclass 3, count 0 2006.285.16:48:20.50#ibcon#about to read 6, iclass 3, count 0 2006.285.16:48:20.50#ibcon#read 6, iclass 3, count 0 2006.285.16:48:20.50#ibcon#end of sib2, iclass 3, count 0 2006.285.16:48:20.50#ibcon#*mode == 0, iclass 3, count 0 2006.285.16:48:20.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.16:48:20.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.16:48:20.50#ibcon#*before write, iclass 3, count 0 2006.285.16:48:20.50#ibcon#enter sib2, iclass 3, count 0 2006.285.16:48:20.50#ibcon#flushed, iclass 3, count 0 2006.285.16:48:20.50#ibcon#about to write, iclass 3, count 0 2006.285.16:48:20.50#ibcon#wrote, iclass 3, count 0 2006.285.16:48:20.50#ibcon#about to read 3, iclass 3, count 0 2006.285.16:48:20.54#ibcon#read 3, iclass 3, count 0 2006.285.16:48:20.54#ibcon#about to read 4, iclass 3, count 0 2006.285.16:48:20.54#ibcon#read 4, iclass 3, count 0 2006.285.16:48:20.54#ibcon#about to read 5, iclass 3, count 0 2006.285.16:48:20.54#ibcon#read 5, iclass 3, count 0 2006.285.16:48:20.54#ibcon#about to read 6, iclass 3, count 0 2006.285.16:48:20.54#ibcon#read 6, iclass 3, count 0 2006.285.16:48:20.54#ibcon#end of sib2, iclass 3, count 0 2006.285.16:48:20.54#ibcon#*after write, iclass 3, count 0 2006.285.16:48:20.54#ibcon#*before return 0, iclass 3, count 0 2006.285.16:48:20.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:48:20.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:48:20.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.16:48:20.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.16:48:20.54$vck44/va=5,3 2006.285.16:48:20.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.16:48:20.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.16:48:20.54#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:20.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:48:20.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:48:20.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:48:20.60#ibcon#enter wrdev, iclass 5, count 2 2006.285.16:48:20.60#ibcon#first serial, iclass 5, count 2 2006.285.16:48:20.60#ibcon#enter sib2, iclass 5, count 2 2006.285.16:48:20.60#ibcon#flushed, iclass 5, count 2 2006.285.16:48:20.60#ibcon#about to write, iclass 5, count 2 2006.285.16:48:20.60#ibcon#wrote, iclass 5, count 2 2006.285.16:48:20.60#ibcon#about to read 3, iclass 5, count 2 2006.285.16:48:20.62#ibcon#read 3, iclass 5, count 2 2006.285.16:48:20.62#ibcon#about to read 4, iclass 5, count 2 2006.285.16:48:20.62#ibcon#read 4, iclass 5, count 2 2006.285.16:48:20.62#ibcon#about to read 5, iclass 5, count 2 2006.285.16:48:20.62#ibcon#read 5, iclass 5, count 2 2006.285.16:48:20.62#ibcon#about to read 6, iclass 5, count 2 2006.285.16:48:20.62#ibcon#read 6, iclass 5, count 2 2006.285.16:48:20.62#ibcon#end of sib2, iclass 5, count 2 2006.285.16:48:20.62#ibcon#*mode == 0, iclass 5, count 2 2006.285.16:48:20.62#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.16:48:20.62#ibcon#[25=AT05-03\r\n] 2006.285.16:48:20.62#ibcon#*before write, iclass 5, count 2 2006.285.16:48:20.62#ibcon#enter sib2, iclass 5, count 2 2006.285.16:48:20.62#ibcon#flushed, iclass 5, count 2 2006.285.16:48:20.62#ibcon#about to write, iclass 5, count 2 2006.285.16:48:20.62#ibcon#wrote, iclass 5, count 2 2006.285.16:48:20.62#ibcon#about to read 3, iclass 5, count 2 2006.285.16:48:20.65#ibcon#read 3, iclass 5, count 2 2006.285.16:48:20.65#ibcon#about to read 4, iclass 5, count 2 2006.285.16:48:20.65#ibcon#read 4, iclass 5, count 2 2006.285.16:48:20.65#ibcon#about to read 5, iclass 5, count 2 2006.285.16:48:20.65#ibcon#read 5, iclass 5, count 2 2006.285.16:48:20.65#ibcon#about to read 6, iclass 5, count 2 2006.285.16:48:20.65#ibcon#read 6, iclass 5, count 2 2006.285.16:48:20.65#ibcon#end of sib2, iclass 5, count 2 2006.285.16:48:20.65#ibcon#*after write, iclass 5, count 2 2006.285.16:48:20.65#ibcon#*before return 0, iclass 5, count 2 2006.285.16:48:20.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:48:20.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:48:20.65#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.16:48:20.65#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:20.65#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:48:20.77#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:48:20.77#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:48:20.77#ibcon#enter wrdev, iclass 5, count 0 2006.285.16:48:20.77#ibcon#first serial, iclass 5, count 0 2006.285.16:48:20.77#ibcon#enter sib2, iclass 5, count 0 2006.285.16:48:20.77#ibcon#flushed, iclass 5, count 0 2006.285.16:48:20.77#ibcon#about to write, iclass 5, count 0 2006.285.16:48:20.77#ibcon#wrote, iclass 5, count 0 2006.285.16:48:20.77#ibcon#about to read 3, iclass 5, count 0 2006.285.16:48:20.79#ibcon#read 3, iclass 5, count 0 2006.285.16:48:20.79#ibcon#about to read 4, iclass 5, count 0 2006.285.16:48:20.79#ibcon#read 4, iclass 5, count 0 2006.285.16:48:20.79#ibcon#about to read 5, iclass 5, count 0 2006.285.16:48:20.79#ibcon#read 5, iclass 5, count 0 2006.285.16:48:20.79#ibcon#about to read 6, iclass 5, count 0 2006.285.16:48:20.79#ibcon#read 6, iclass 5, count 0 2006.285.16:48:20.79#ibcon#end of sib2, iclass 5, count 0 2006.285.16:48:20.79#ibcon#*mode == 0, iclass 5, count 0 2006.285.16:48:20.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.16:48:20.79#ibcon#[25=USB\r\n] 2006.285.16:48:20.79#ibcon#*before write, iclass 5, count 0 2006.285.16:48:20.79#ibcon#enter sib2, iclass 5, count 0 2006.285.16:48:20.79#ibcon#flushed, iclass 5, count 0 2006.285.16:48:20.79#ibcon#about to write, iclass 5, count 0 2006.285.16:48:20.79#ibcon#wrote, iclass 5, count 0 2006.285.16:48:20.79#ibcon#about to read 3, iclass 5, count 0 2006.285.16:48:20.82#ibcon#read 3, iclass 5, count 0 2006.285.16:48:20.82#ibcon#about to read 4, iclass 5, count 0 2006.285.16:48:20.82#ibcon#read 4, iclass 5, count 0 2006.285.16:48:20.82#ibcon#about to read 5, iclass 5, count 0 2006.285.16:48:20.82#ibcon#read 5, iclass 5, count 0 2006.285.16:48:20.82#ibcon#about to read 6, iclass 5, count 0 2006.285.16:48:20.82#ibcon#read 6, iclass 5, count 0 2006.285.16:48:20.82#ibcon#end of sib2, iclass 5, count 0 2006.285.16:48:20.82#ibcon#*after write, iclass 5, count 0 2006.285.16:48:20.82#ibcon#*before return 0, iclass 5, count 0 2006.285.16:48:20.82#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:48:20.82#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:48:20.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.16:48:20.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.16:48:20.82$vck44/valo=6,814.99 2006.285.16:48:20.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.16:48:20.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.16:48:20.82#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:20.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:48:20.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:48:20.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:48:20.82#ibcon#enter wrdev, iclass 7, count 0 2006.285.16:48:20.82#ibcon#first serial, iclass 7, count 0 2006.285.16:48:20.82#ibcon#enter sib2, iclass 7, count 0 2006.285.16:48:20.82#ibcon#flushed, iclass 7, count 0 2006.285.16:48:20.82#ibcon#about to write, iclass 7, count 0 2006.285.16:48:20.82#ibcon#wrote, iclass 7, count 0 2006.285.16:48:20.82#ibcon#about to read 3, iclass 7, count 0 2006.285.16:48:20.84#ibcon#read 3, iclass 7, count 0 2006.285.16:48:20.84#ibcon#about to read 4, iclass 7, count 0 2006.285.16:48:20.84#ibcon#read 4, iclass 7, count 0 2006.285.16:48:20.84#ibcon#about to read 5, iclass 7, count 0 2006.285.16:48:20.84#ibcon#read 5, iclass 7, count 0 2006.285.16:48:20.84#ibcon#about to read 6, iclass 7, count 0 2006.285.16:48:20.84#ibcon#read 6, iclass 7, count 0 2006.285.16:48:20.84#ibcon#end of sib2, iclass 7, count 0 2006.285.16:48:20.84#ibcon#*mode == 0, iclass 7, count 0 2006.285.16:48:20.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.16:48:20.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.16:48:20.84#ibcon#*before write, iclass 7, count 0 2006.285.16:48:20.84#ibcon#enter sib2, iclass 7, count 0 2006.285.16:48:20.84#ibcon#flushed, iclass 7, count 0 2006.285.16:48:20.84#ibcon#about to write, iclass 7, count 0 2006.285.16:48:20.84#ibcon#wrote, iclass 7, count 0 2006.285.16:48:20.84#ibcon#about to read 3, iclass 7, count 0 2006.285.16:48:20.88#ibcon#read 3, iclass 7, count 0 2006.285.16:48:20.88#ibcon#about to read 4, iclass 7, count 0 2006.285.16:48:20.88#ibcon#read 4, iclass 7, count 0 2006.285.16:48:20.88#ibcon#about to read 5, iclass 7, count 0 2006.285.16:48:20.88#ibcon#read 5, iclass 7, count 0 2006.285.16:48:20.88#ibcon#about to read 6, iclass 7, count 0 2006.285.16:48:20.88#ibcon#read 6, iclass 7, count 0 2006.285.16:48:20.88#ibcon#end of sib2, iclass 7, count 0 2006.285.16:48:20.88#ibcon#*after write, iclass 7, count 0 2006.285.16:48:20.88#ibcon#*before return 0, iclass 7, count 0 2006.285.16:48:20.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:48:20.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:48:20.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.16:48:20.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.16:48:20.88$vck44/va=6,4 2006.285.16:48:20.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.16:48:20.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.16:48:20.88#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:20.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:48:20.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:48:20.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:48:20.94#ibcon#enter wrdev, iclass 11, count 2 2006.285.16:48:20.94#ibcon#first serial, iclass 11, count 2 2006.285.16:48:20.94#ibcon#enter sib2, iclass 11, count 2 2006.285.16:48:20.94#ibcon#flushed, iclass 11, count 2 2006.285.16:48:20.94#ibcon#about to write, iclass 11, count 2 2006.285.16:48:20.94#ibcon#wrote, iclass 11, count 2 2006.285.16:48:20.94#ibcon#about to read 3, iclass 11, count 2 2006.285.16:48:20.96#ibcon#read 3, iclass 11, count 2 2006.285.16:48:20.96#ibcon#about to read 4, iclass 11, count 2 2006.285.16:48:20.96#ibcon#read 4, iclass 11, count 2 2006.285.16:48:20.96#ibcon#about to read 5, iclass 11, count 2 2006.285.16:48:20.96#ibcon#read 5, iclass 11, count 2 2006.285.16:48:20.96#ibcon#about to read 6, iclass 11, count 2 2006.285.16:48:20.96#ibcon#read 6, iclass 11, count 2 2006.285.16:48:20.96#ibcon#end of sib2, iclass 11, count 2 2006.285.16:48:20.96#ibcon#*mode == 0, iclass 11, count 2 2006.285.16:48:20.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.16:48:20.96#ibcon#[25=AT06-04\r\n] 2006.285.16:48:20.96#ibcon#*before write, iclass 11, count 2 2006.285.16:48:20.96#ibcon#enter sib2, iclass 11, count 2 2006.285.16:48:20.96#ibcon#flushed, iclass 11, count 2 2006.285.16:48:20.96#ibcon#about to write, iclass 11, count 2 2006.285.16:48:20.96#ibcon#wrote, iclass 11, count 2 2006.285.16:48:20.96#ibcon#about to read 3, iclass 11, count 2 2006.285.16:48:20.99#ibcon#read 3, iclass 11, count 2 2006.285.16:48:20.99#ibcon#about to read 4, iclass 11, count 2 2006.285.16:48:20.99#ibcon#read 4, iclass 11, count 2 2006.285.16:48:20.99#ibcon#about to read 5, iclass 11, count 2 2006.285.16:48:20.99#ibcon#read 5, iclass 11, count 2 2006.285.16:48:20.99#ibcon#about to read 6, iclass 11, count 2 2006.285.16:48:20.99#ibcon#read 6, iclass 11, count 2 2006.285.16:48:20.99#ibcon#end of sib2, iclass 11, count 2 2006.285.16:48:20.99#ibcon#*after write, iclass 11, count 2 2006.285.16:48:20.99#ibcon#*before return 0, iclass 11, count 2 2006.285.16:48:20.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:48:20.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:48:20.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.16:48:20.99#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:20.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:48:21.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:48:21.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:48:21.11#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:48:21.11#ibcon#first serial, iclass 11, count 0 2006.285.16:48:21.11#ibcon#enter sib2, iclass 11, count 0 2006.285.16:48:21.11#ibcon#flushed, iclass 11, count 0 2006.285.16:48:21.11#ibcon#about to write, iclass 11, count 0 2006.285.16:48:21.11#ibcon#wrote, iclass 11, count 0 2006.285.16:48:21.11#ibcon#about to read 3, iclass 11, count 0 2006.285.16:48:21.13#ibcon#read 3, iclass 11, count 0 2006.285.16:48:21.13#ibcon#about to read 4, iclass 11, count 0 2006.285.16:48:21.13#ibcon#read 4, iclass 11, count 0 2006.285.16:48:21.13#ibcon#about to read 5, iclass 11, count 0 2006.285.16:48:21.13#ibcon#read 5, iclass 11, count 0 2006.285.16:48:21.13#ibcon#about to read 6, iclass 11, count 0 2006.285.16:48:21.13#ibcon#read 6, iclass 11, count 0 2006.285.16:48:21.13#ibcon#end of sib2, iclass 11, count 0 2006.285.16:48:21.13#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:48:21.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:48:21.13#ibcon#[25=USB\r\n] 2006.285.16:48:21.13#ibcon#*before write, iclass 11, count 0 2006.285.16:48:21.13#ibcon#enter sib2, iclass 11, count 0 2006.285.16:48:21.13#ibcon#flushed, iclass 11, count 0 2006.285.16:48:21.13#ibcon#about to write, iclass 11, count 0 2006.285.16:48:21.13#ibcon#wrote, iclass 11, count 0 2006.285.16:48:21.13#ibcon#about to read 3, iclass 11, count 0 2006.285.16:48:21.16#ibcon#read 3, iclass 11, count 0 2006.285.16:48:21.51#ibcon#about to read 4, iclass 11, count 0 2006.285.16:48:21.51#ibcon#read 4, iclass 11, count 0 2006.285.16:48:21.51#ibcon#about to read 5, iclass 11, count 0 2006.285.16:48:21.51#ibcon#read 5, iclass 11, count 0 2006.285.16:48:21.51#ibcon#about to read 6, iclass 11, count 0 2006.285.16:48:21.51#ibcon#read 6, iclass 11, count 0 2006.285.16:48:21.51#ibcon#end of sib2, iclass 11, count 0 2006.285.16:48:21.51#ibcon#*after write, iclass 11, count 0 2006.285.16:48:21.51#ibcon#*before return 0, iclass 11, count 0 2006.285.16:48:21.51#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:48:21.51#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:48:21.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:48:21.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:48:21.51$vck44/valo=7,864.99 2006.285.16:48:21.51#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.16:48:21.51#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.16:48:21.51#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:21.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:48:21.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:48:21.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:48:21.51#ibcon#enter wrdev, iclass 13, count 0 2006.285.16:48:21.51#ibcon#first serial, iclass 13, count 0 2006.285.16:48:21.51#ibcon#enter sib2, iclass 13, count 0 2006.285.16:48:21.51#ibcon#flushed, iclass 13, count 0 2006.285.16:48:21.51#ibcon#about to write, iclass 13, count 0 2006.285.16:48:21.51#ibcon#wrote, iclass 13, count 0 2006.285.16:48:21.51#ibcon#about to read 3, iclass 13, count 0 2006.285.16:48:21.53#ibcon#read 3, iclass 13, count 0 2006.285.16:48:21.53#ibcon#about to read 4, iclass 13, count 0 2006.285.16:48:21.53#ibcon#read 4, iclass 13, count 0 2006.285.16:48:21.53#ibcon#about to read 5, iclass 13, count 0 2006.285.16:48:21.53#ibcon#read 5, iclass 13, count 0 2006.285.16:48:21.53#ibcon#about to read 6, iclass 13, count 0 2006.285.16:48:21.53#ibcon#read 6, iclass 13, count 0 2006.285.16:48:21.53#ibcon#end of sib2, iclass 13, count 0 2006.285.16:48:21.53#ibcon#*mode == 0, iclass 13, count 0 2006.285.16:48:21.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.16:48:21.53#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.16:48:21.53#ibcon#*before write, iclass 13, count 0 2006.285.16:48:21.53#ibcon#enter sib2, iclass 13, count 0 2006.285.16:48:21.53#ibcon#flushed, iclass 13, count 0 2006.285.16:48:21.53#ibcon#about to write, iclass 13, count 0 2006.285.16:48:21.53#ibcon#wrote, iclass 13, count 0 2006.285.16:48:21.53#ibcon#about to read 3, iclass 13, count 0 2006.285.16:48:21.57#ibcon#read 3, iclass 13, count 0 2006.285.16:48:21.57#ibcon#about to read 4, iclass 13, count 0 2006.285.16:48:21.57#ibcon#read 4, iclass 13, count 0 2006.285.16:48:21.57#ibcon#about to read 5, iclass 13, count 0 2006.285.16:48:21.57#ibcon#read 5, iclass 13, count 0 2006.285.16:48:21.57#ibcon#about to read 6, iclass 13, count 0 2006.285.16:48:21.57#ibcon#read 6, iclass 13, count 0 2006.285.16:48:21.57#ibcon#end of sib2, iclass 13, count 0 2006.285.16:48:21.57#ibcon#*after write, iclass 13, count 0 2006.285.16:48:21.57#ibcon#*before return 0, iclass 13, count 0 2006.285.16:48:21.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:48:21.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:48:21.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.16:48:21.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.16:48:21.57$vck44/va=7,4 2006.285.16:48:21.57#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.16:48:21.57#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.16:48:21.57#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:21.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:48:21.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:48:21.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:48:21.63#ibcon#enter wrdev, iclass 15, count 2 2006.285.16:48:21.63#ibcon#first serial, iclass 15, count 2 2006.285.16:48:21.63#ibcon#enter sib2, iclass 15, count 2 2006.285.16:48:21.63#ibcon#flushed, iclass 15, count 2 2006.285.16:48:21.63#ibcon#about to write, iclass 15, count 2 2006.285.16:48:21.63#ibcon#wrote, iclass 15, count 2 2006.285.16:48:21.63#ibcon#about to read 3, iclass 15, count 2 2006.285.16:48:21.65#ibcon#read 3, iclass 15, count 2 2006.285.16:48:21.65#ibcon#about to read 4, iclass 15, count 2 2006.285.16:48:21.65#ibcon#read 4, iclass 15, count 2 2006.285.16:48:21.65#ibcon#about to read 5, iclass 15, count 2 2006.285.16:48:21.65#ibcon#read 5, iclass 15, count 2 2006.285.16:48:21.65#ibcon#about to read 6, iclass 15, count 2 2006.285.16:48:21.65#ibcon#read 6, iclass 15, count 2 2006.285.16:48:21.65#ibcon#end of sib2, iclass 15, count 2 2006.285.16:48:21.65#ibcon#*mode == 0, iclass 15, count 2 2006.285.16:48:21.65#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.16:48:21.65#ibcon#[25=AT07-04\r\n] 2006.285.16:48:21.65#ibcon#*before write, iclass 15, count 2 2006.285.16:48:21.65#ibcon#enter sib2, iclass 15, count 2 2006.285.16:48:21.65#ibcon#flushed, iclass 15, count 2 2006.285.16:48:21.65#ibcon#about to write, iclass 15, count 2 2006.285.16:48:21.65#ibcon#wrote, iclass 15, count 2 2006.285.16:48:21.65#ibcon#about to read 3, iclass 15, count 2 2006.285.16:48:21.68#ibcon#read 3, iclass 15, count 2 2006.285.16:48:21.68#ibcon#about to read 4, iclass 15, count 2 2006.285.16:48:21.68#ibcon#read 4, iclass 15, count 2 2006.285.16:48:21.68#ibcon#about to read 5, iclass 15, count 2 2006.285.16:48:21.68#ibcon#read 5, iclass 15, count 2 2006.285.16:48:21.68#ibcon#about to read 6, iclass 15, count 2 2006.285.16:48:21.68#ibcon#read 6, iclass 15, count 2 2006.285.16:48:21.68#ibcon#end of sib2, iclass 15, count 2 2006.285.16:48:21.68#ibcon#*after write, iclass 15, count 2 2006.285.16:48:21.68#ibcon#*before return 0, iclass 15, count 2 2006.285.16:48:21.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:48:21.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:48:21.68#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.16:48:21.68#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:21.68#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:48:21.80#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:48:21.80#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:48:21.80#ibcon#enter wrdev, iclass 15, count 0 2006.285.16:48:21.80#ibcon#first serial, iclass 15, count 0 2006.285.16:48:21.80#ibcon#enter sib2, iclass 15, count 0 2006.285.16:48:21.80#ibcon#flushed, iclass 15, count 0 2006.285.16:48:21.80#ibcon#about to write, iclass 15, count 0 2006.285.16:48:21.80#ibcon#wrote, iclass 15, count 0 2006.285.16:48:21.80#ibcon#about to read 3, iclass 15, count 0 2006.285.16:48:21.82#ibcon#read 3, iclass 15, count 0 2006.285.16:48:21.82#ibcon#about to read 4, iclass 15, count 0 2006.285.16:48:21.82#ibcon#read 4, iclass 15, count 0 2006.285.16:48:21.82#ibcon#about to read 5, iclass 15, count 0 2006.285.16:48:21.82#ibcon#read 5, iclass 15, count 0 2006.285.16:48:21.82#ibcon#about to read 6, iclass 15, count 0 2006.285.16:48:21.82#ibcon#read 6, iclass 15, count 0 2006.285.16:48:21.82#ibcon#end of sib2, iclass 15, count 0 2006.285.16:48:21.82#ibcon#*mode == 0, iclass 15, count 0 2006.285.16:48:21.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.16:48:21.82#ibcon#[25=USB\r\n] 2006.285.16:48:21.82#ibcon#*before write, iclass 15, count 0 2006.285.16:48:21.82#ibcon#enter sib2, iclass 15, count 0 2006.285.16:48:21.82#ibcon#flushed, iclass 15, count 0 2006.285.16:48:21.82#ibcon#about to write, iclass 15, count 0 2006.285.16:48:21.82#ibcon#wrote, iclass 15, count 0 2006.285.16:48:21.82#ibcon#about to read 3, iclass 15, count 0 2006.285.16:48:21.85#ibcon#read 3, iclass 15, count 0 2006.285.16:48:21.85#ibcon#about to read 4, iclass 15, count 0 2006.285.16:48:21.85#ibcon#read 4, iclass 15, count 0 2006.285.16:48:21.85#ibcon#about to read 5, iclass 15, count 0 2006.285.16:48:21.85#ibcon#read 5, iclass 15, count 0 2006.285.16:48:21.85#ibcon#about to read 6, iclass 15, count 0 2006.285.16:48:21.85#ibcon#read 6, iclass 15, count 0 2006.285.16:48:21.85#ibcon#end of sib2, iclass 15, count 0 2006.285.16:48:21.85#ibcon#*after write, iclass 15, count 0 2006.285.16:48:21.85#ibcon#*before return 0, iclass 15, count 0 2006.285.16:48:21.85#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:48:21.85#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:48:21.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.16:48:21.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.16:48:21.85$vck44/valo=8,884.99 2006.285.16:48:21.85#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.16:48:21.85#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.16:48:21.85#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:21.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:48:21.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:48:21.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:48:21.85#ibcon#enter wrdev, iclass 17, count 0 2006.285.16:48:21.85#ibcon#first serial, iclass 17, count 0 2006.285.16:48:21.85#ibcon#enter sib2, iclass 17, count 0 2006.285.16:48:21.85#ibcon#flushed, iclass 17, count 0 2006.285.16:48:21.85#ibcon#about to write, iclass 17, count 0 2006.285.16:48:21.85#ibcon#wrote, iclass 17, count 0 2006.285.16:48:21.85#ibcon#about to read 3, iclass 17, count 0 2006.285.16:48:21.87#ibcon#read 3, iclass 17, count 0 2006.285.16:48:21.87#ibcon#about to read 4, iclass 17, count 0 2006.285.16:48:21.87#ibcon#read 4, iclass 17, count 0 2006.285.16:48:21.87#ibcon#about to read 5, iclass 17, count 0 2006.285.16:48:21.87#ibcon#read 5, iclass 17, count 0 2006.285.16:48:21.87#ibcon#about to read 6, iclass 17, count 0 2006.285.16:48:21.87#ibcon#read 6, iclass 17, count 0 2006.285.16:48:21.87#ibcon#end of sib2, iclass 17, count 0 2006.285.16:48:21.87#ibcon#*mode == 0, iclass 17, count 0 2006.285.16:48:21.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.16:48:21.87#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.16:48:21.87#ibcon#*before write, iclass 17, count 0 2006.285.16:48:21.87#ibcon#enter sib2, iclass 17, count 0 2006.285.16:48:21.87#ibcon#flushed, iclass 17, count 0 2006.285.16:48:21.87#ibcon#about to write, iclass 17, count 0 2006.285.16:48:21.87#ibcon#wrote, iclass 17, count 0 2006.285.16:48:21.87#ibcon#about to read 3, iclass 17, count 0 2006.285.16:48:21.91#ibcon#read 3, iclass 17, count 0 2006.285.16:48:21.91#ibcon#about to read 4, iclass 17, count 0 2006.285.16:48:21.91#ibcon#read 4, iclass 17, count 0 2006.285.16:48:21.91#ibcon#about to read 5, iclass 17, count 0 2006.285.16:48:21.91#ibcon#read 5, iclass 17, count 0 2006.285.16:48:21.91#ibcon#about to read 6, iclass 17, count 0 2006.285.16:48:21.91#ibcon#read 6, iclass 17, count 0 2006.285.16:48:21.91#ibcon#end of sib2, iclass 17, count 0 2006.285.16:48:21.91#ibcon#*after write, iclass 17, count 0 2006.285.16:48:21.91#ibcon#*before return 0, iclass 17, count 0 2006.285.16:48:21.91#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:48:21.91#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:48:21.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.16:48:21.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.16:48:21.91$vck44/va=8,3 2006.285.16:48:21.91#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.16:48:21.91#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.16:48:21.91#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:21.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:48:21.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:48:21.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:48:21.97#ibcon#enter wrdev, iclass 19, count 2 2006.285.16:48:21.97#ibcon#first serial, iclass 19, count 2 2006.285.16:48:21.97#ibcon#enter sib2, iclass 19, count 2 2006.285.16:48:21.97#ibcon#flushed, iclass 19, count 2 2006.285.16:48:21.97#ibcon#about to write, iclass 19, count 2 2006.285.16:48:21.97#ibcon#wrote, iclass 19, count 2 2006.285.16:48:21.97#ibcon#about to read 3, iclass 19, count 2 2006.285.16:48:21.99#ibcon#read 3, iclass 19, count 2 2006.285.16:48:21.99#ibcon#about to read 4, iclass 19, count 2 2006.285.16:48:21.99#ibcon#read 4, iclass 19, count 2 2006.285.16:48:21.99#ibcon#about to read 5, iclass 19, count 2 2006.285.16:48:21.99#ibcon#read 5, iclass 19, count 2 2006.285.16:48:21.99#ibcon#about to read 6, iclass 19, count 2 2006.285.16:48:21.99#ibcon#read 6, iclass 19, count 2 2006.285.16:48:21.99#ibcon#end of sib2, iclass 19, count 2 2006.285.16:48:21.99#ibcon#*mode == 0, iclass 19, count 2 2006.285.16:48:21.99#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.16:48:21.99#ibcon#[25=AT08-03\r\n] 2006.285.16:48:21.99#ibcon#*before write, iclass 19, count 2 2006.285.16:48:21.99#ibcon#enter sib2, iclass 19, count 2 2006.285.16:48:21.99#ibcon#flushed, iclass 19, count 2 2006.285.16:48:21.99#ibcon#about to write, iclass 19, count 2 2006.285.16:48:21.99#ibcon#wrote, iclass 19, count 2 2006.285.16:48:21.99#ibcon#about to read 3, iclass 19, count 2 2006.285.16:48:22.02#ibcon#read 3, iclass 19, count 2 2006.285.16:48:22.02#ibcon#about to read 4, iclass 19, count 2 2006.285.16:48:22.02#ibcon#read 4, iclass 19, count 2 2006.285.16:48:22.02#ibcon#about to read 5, iclass 19, count 2 2006.285.16:48:22.02#ibcon#read 5, iclass 19, count 2 2006.285.16:48:22.02#ibcon#about to read 6, iclass 19, count 2 2006.285.16:48:22.02#ibcon#read 6, iclass 19, count 2 2006.285.16:48:22.02#ibcon#end of sib2, iclass 19, count 2 2006.285.16:48:22.02#ibcon#*after write, iclass 19, count 2 2006.285.16:48:22.02#ibcon#*before return 0, iclass 19, count 2 2006.285.16:48:22.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:48:22.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.16:48:22.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.16:48:22.02#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:22.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:48:22.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:48:22.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:48:22.14#ibcon#enter wrdev, iclass 19, count 0 2006.285.16:48:22.14#ibcon#first serial, iclass 19, count 0 2006.285.16:48:22.14#ibcon#enter sib2, iclass 19, count 0 2006.285.16:48:22.14#ibcon#flushed, iclass 19, count 0 2006.285.16:48:22.14#ibcon#about to write, iclass 19, count 0 2006.285.16:48:22.14#ibcon#wrote, iclass 19, count 0 2006.285.16:48:22.14#ibcon#about to read 3, iclass 19, count 0 2006.285.16:48:22.16#ibcon#read 3, iclass 19, count 0 2006.285.16:48:22.18#ibcon#about to read 4, iclass 19, count 0 2006.285.16:48:22.18#ibcon#read 4, iclass 19, count 0 2006.285.16:48:22.18#ibcon#about to read 5, iclass 19, count 0 2006.285.16:48:22.18#ibcon#read 5, iclass 19, count 0 2006.285.16:48:22.18#ibcon#about to read 6, iclass 19, count 0 2006.285.16:48:22.18#ibcon#read 6, iclass 19, count 0 2006.285.16:48:22.18#ibcon#end of sib2, iclass 19, count 0 2006.285.16:48:22.18#ibcon#*mode == 0, iclass 19, count 0 2006.285.16:48:22.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.16:48:22.18#ibcon#[25=USB\r\n] 2006.285.16:48:22.18#ibcon#*before write, iclass 19, count 0 2006.285.16:48:22.18#ibcon#enter sib2, iclass 19, count 0 2006.285.16:48:22.18#ibcon#flushed, iclass 19, count 0 2006.285.16:48:22.18#ibcon#about to write, iclass 19, count 0 2006.285.16:48:22.18#ibcon#wrote, iclass 19, count 0 2006.285.16:48:22.18#ibcon#about to read 3, iclass 19, count 0 2006.285.16:48:22.21#ibcon#read 3, iclass 19, count 0 2006.285.16:48:22.21#ibcon#about to read 4, iclass 19, count 0 2006.285.16:48:22.21#ibcon#read 4, iclass 19, count 0 2006.285.16:48:22.21#ibcon#about to read 5, iclass 19, count 0 2006.285.16:48:22.21#ibcon#read 5, iclass 19, count 0 2006.285.16:48:22.21#ibcon#about to read 6, iclass 19, count 0 2006.285.16:48:22.21#ibcon#read 6, iclass 19, count 0 2006.285.16:48:22.21#ibcon#end of sib2, iclass 19, count 0 2006.285.16:48:22.21#ibcon#*after write, iclass 19, count 0 2006.285.16:48:22.21#ibcon#*before return 0, iclass 19, count 0 2006.285.16:48:22.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:48:22.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.16:48:22.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.16:48:22.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.16:48:22.21$vck44/vblo=1,629.99 2006.285.16:48:22.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.16:48:22.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.16:48:22.21#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:22.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:48:22.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:48:22.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:48:22.21#ibcon#enter wrdev, iclass 21, count 0 2006.285.16:48:22.21#ibcon#first serial, iclass 21, count 0 2006.285.16:48:22.21#ibcon#enter sib2, iclass 21, count 0 2006.285.16:48:22.21#ibcon#flushed, iclass 21, count 0 2006.285.16:48:22.21#ibcon#about to write, iclass 21, count 0 2006.285.16:48:22.21#ibcon#wrote, iclass 21, count 0 2006.285.16:48:22.21#ibcon#about to read 3, iclass 21, count 0 2006.285.16:48:22.23#ibcon#read 3, iclass 21, count 0 2006.285.16:48:22.23#ibcon#about to read 4, iclass 21, count 0 2006.285.16:48:22.23#ibcon#read 4, iclass 21, count 0 2006.285.16:48:22.23#ibcon#about to read 5, iclass 21, count 0 2006.285.16:48:22.23#ibcon#read 5, iclass 21, count 0 2006.285.16:48:22.23#ibcon#about to read 6, iclass 21, count 0 2006.285.16:48:22.23#ibcon#read 6, iclass 21, count 0 2006.285.16:48:22.23#ibcon#end of sib2, iclass 21, count 0 2006.285.16:48:22.23#ibcon#*mode == 0, iclass 21, count 0 2006.285.16:48:22.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.16:48:22.23#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.16:48:22.23#ibcon#*before write, iclass 21, count 0 2006.285.16:48:22.23#ibcon#enter sib2, iclass 21, count 0 2006.285.16:48:22.23#ibcon#flushed, iclass 21, count 0 2006.285.16:48:22.23#ibcon#about to write, iclass 21, count 0 2006.285.16:48:22.23#ibcon#wrote, iclass 21, count 0 2006.285.16:48:22.23#ibcon#about to read 3, iclass 21, count 0 2006.285.16:48:22.27#ibcon#read 3, iclass 21, count 0 2006.285.16:48:22.27#ibcon#about to read 4, iclass 21, count 0 2006.285.16:48:22.27#ibcon#read 4, iclass 21, count 0 2006.285.16:48:22.27#ibcon#about to read 5, iclass 21, count 0 2006.285.16:48:22.27#ibcon#read 5, iclass 21, count 0 2006.285.16:48:22.27#ibcon#about to read 6, iclass 21, count 0 2006.285.16:48:22.27#ibcon#read 6, iclass 21, count 0 2006.285.16:48:22.27#ibcon#end of sib2, iclass 21, count 0 2006.285.16:48:22.27#ibcon#*after write, iclass 21, count 0 2006.285.16:48:22.27#ibcon#*before return 0, iclass 21, count 0 2006.285.16:48:22.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:48:22.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.16:48:22.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.16:48:22.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.16:48:22.27$vck44/vb=1,4 2006.285.16:48:22.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.16:48:22.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.16:48:22.27#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:22.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:48:22.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:48:22.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:48:22.27#ibcon#enter wrdev, iclass 23, count 2 2006.285.16:48:22.27#ibcon#first serial, iclass 23, count 2 2006.285.16:48:22.27#ibcon#enter sib2, iclass 23, count 2 2006.285.16:48:22.27#ibcon#flushed, iclass 23, count 2 2006.285.16:48:22.27#ibcon#about to write, iclass 23, count 2 2006.285.16:48:22.27#ibcon#wrote, iclass 23, count 2 2006.285.16:48:22.27#ibcon#about to read 3, iclass 23, count 2 2006.285.16:48:22.29#ibcon#read 3, iclass 23, count 2 2006.285.16:48:22.29#ibcon#about to read 4, iclass 23, count 2 2006.285.16:48:22.29#ibcon#read 4, iclass 23, count 2 2006.285.16:48:22.29#ibcon#about to read 5, iclass 23, count 2 2006.285.16:48:22.29#ibcon#read 5, iclass 23, count 2 2006.285.16:48:22.29#ibcon#about to read 6, iclass 23, count 2 2006.285.16:48:22.29#ibcon#read 6, iclass 23, count 2 2006.285.16:48:22.29#ibcon#end of sib2, iclass 23, count 2 2006.285.16:48:22.29#ibcon#*mode == 0, iclass 23, count 2 2006.285.16:48:22.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.16:48:22.29#ibcon#[27=AT01-04\r\n] 2006.285.16:48:22.29#ibcon#*before write, iclass 23, count 2 2006.285.16:48:22.29#ibcon#enter sib2, iclass 23, count 2 2006.285.16:48:22.29#ibcon#flushed, iclass 23, count 2 2006.285.16:48:22.29#ibcon#about to write, iclass 23, count 2 2006.285.16:48:22.29#ibcon#wrote, iclass 23, count 2 2006.285.16:48:22.29#ibcon#about to read 3, iclass 23, count 2 2006.285.16:48:22.32#ibcon#read 3, iclass 23, count 2 2006.285.16:48:22.32#ibcon#about to read 4, iclass 23, count 2 2006.285.16:48:22.32#ibcon#read 4, iclass 23, count 2 2006.285.16:48:22.32#ibcon#about to read 5, iclass 23, count 2 2006.285.16:48:22.32#ibcon#read 5, iclass 23, count 2 2006.285.16:48:22.32#ibcon#about to read 6, iclass 23, count 2 2006.285.16:48:22.32#ibcon#read 6, iclass 23, count 2 2006.285.16:48:22.32#ibcon#end of sib2, iclass 23, count 2 2006.285.16:48:22.32#ibcon#*after write, iclass 23, count 2 2006.285.16:48:22.32#ibcon#*before return 0, iclass 23, count 2 2006.285.16:48:22.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:48:22.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.16:48:22.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.16:48:22.32#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:22.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:48:22.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:48:22.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:48:22.44#ibcon#enter wrdev, iclass 23, count 0 2006.285.16:48:22.44#ibcon#first serial, iclass 23, count 0 2006.285.16:48:22.44#ibcon#enter sib2, iclass 23, count 0 2006.285.16:48:22.44#ibcon#flushed, iclass 23, count 0 2006.285.16:48:22.44#ibcon#about to write, iclass 23, count 0 2006.285.16:48:22.44#ibcon#wrote, iclass 23, count 0 2006.285.16:48:22.44#ibcon#about to read 3, iclass 23, count 0 2006.285.16:48:22.46#ibcon#read 3, iclass 23, count 0 2006.285.16:48:22.46#ibcon#about to read 4, iclass 23, count 0 2006.285.16:48:22.46#ibcon#read 4, iclass 23, count 0 2006.285.16:48:22.46#ibcon#about to read 5, iclass 23, count 0 2006.285.16:48:22.46#ibcon#read 5, iclass 23, count 0 2006.285.16:48:22.46#ibcon#about to read 6, iclass 23, count 0 2006.285.16:48:22.46#ibcon#read 6, iclass 23, count 0 2006.285.16:48:22.46#ibcon#end of sib2, iclass 23, count 0 2006.285.16:48:22.46#ibcon#*mode == 0, iclass 23, count 0 2006.285.16:48:22.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.16:48:22.46#ibcon#[27=USB\r\n] 2006.285.16:48:22.46#ibcon#*before write, iclass 23, count 0 2006.285.16:48:22.46#ibcon#enter sib2, iclass 23, count 0 2006.285.16:48:22.46#ibcon#flushed, iclass 23, count 0 2006.285.16:48:22.46#ibcon#about to write, iclass 23, count 0 2006.285.16:48:22.46#ibcon#wrote, iclass 23, count 0 2006.285.16:48:22.46#ibcon#about to read 3, iclass 23, count 0 2006.285.16:48:22.49#ibcon#read 3, iclass 23, count 0 2006.285.16:48:22.49#ibcon#about to read 4, iclass 23, count 0 2006.285.16:48:22.49#ibcon#read 4, iclass 23, count 0 2006.285.16:48:22.49#ibcon#about to read 5, iclass 23, count 0 2006.285.16:48:22.49#ibcon#read 5, iclass 23, count 0 2006.285.16:48:22.49#ibcon#about to read 6, iclass 23, count 0 2006.285.16:48:22.49#ibcon#read 6, iclass 23, count 0 2006.285.16:48:22.49#ibcon#end of sib2, iclass 23, count 0 2006.285.16:48:22.49#ibcon#*after write, iclass 23, count 0 2006.285.16:48:22.49#ibcon#*before return 0, iclass 23, count 0 2006.285.16:48:22.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:48:22.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.16:48:22.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.16:48:22.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.16:48:22.49$vck44/vblo=2,634.99 2006.285.16:48:22.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.16:48:22.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.16:48:22.49#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:22.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:48:22.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:48:22.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:48:22.49#ibcon#enter wrdev, iclass 25, count 0 2006.285.16:48:22.49#ibcon#first serial, iclass 25, count 0 2006.285.16:48:22.49#ibcon#enter sib2, iclass 25, count 0 2006.285.16:48:22.49#ibcon#flushed, iclass 25, count 0 2006.285.16:48:22.49#ibcon#about to write, iclass 25, count 0 2006.285.16:48:22.49#ibcon#wrote, iclass 25, count 0 2006.285.16:48:22.49#ibcon#about to read 3, iclass 25, count 0 2006.285.16:48:22.51#ibcon#read 3, iclass 25, count 0 2006.285.16:48:22.51#ibcon#about to read 4, iclass 25, count 0 2006.285.16:48:22.51#ibcon#read 4, iclass 25, count 0 2006.285.16:48:22.51#ibcon#about to read 5, iclass 25, count 0 2006.285.16:48:22.51#ibcon#read 5, iclass 25, count 0 2006.285.16:48:22.51#ibcon#about to read 6, iclass 25, count 0 2006.285.16:48:22.51#ibcon#read 6, iclass 25, count 0 2006.285.16:48:22.51#ibcon#end of sib2, iclass 25, count 0 2006.285.16:48:22.51#ibcon#*mode == 0, iclass 25, count 0 2006.285.16:48:22.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.16:48:22.51#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.16:48:22.51#ibcon#*before write, iclass 25, count 0 2006.285.16:48:22.51#ibcon#enter sib2, iclass 25, count 0 2006.285.16:48:22.51#ibcon#flushed, iclass 25, count 0 2006.285.16:48:22.51#ibcon#about to write, iclass 25, count 0 2006.285.16:48:22.51#ibcon#wrote, iclass 25, count 0 2006.285.16:48:22.51#ibcon#about to read 3, iclass 25, count 0 2006.285.16:48:22.55#ibcon#read 3, iclass 25, count 0 2006.285.16:48:22.55#ibcon#about to read 4, iclass 25, count 0 2006.285.16:48:22.55#ibcon#read 4, iclass 25, count 0 2006.285.16:48:22.55#ibcon#about to read 5, iclass 25, count 0 2006.285.16:48:22.55#ibcon#read 5, iclass 25, count 0 2006.285.16:48:22.55#ibcon#about to read 6, iclass 25, count 0 2006.285.16:48:22.55#ibcon#read 6, iclass 25, count 0 2006.285.16:48:22.55#ibcon#end of sib2, iclass 25, count 0 2006.285.16:48:22.55#ibcon#*after write, iclass 25, count 0 2006.285.16:48:22.55#ibcon#*before return 0, iclass 25, count 0 2006.285.16:48:22.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:48:22.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.16:48:22.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.16:48:22.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.16:48:22.55$vck44/vb=2,5 2006.285.16:48:22.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.16:48:22.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.16:48:22.55#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:22.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:48:22.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:48:22.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:48:22.61#ibcon#enter wrdev, iclass 27, count 2 2006.285.16:48:22.61#ibcon#first serial, iclass 27, count 2 2006.285.16:48:22.61#ibcon#enter sib2, iclass 27, count 2 2006.285.16:48:22.61#ibcon#flushed, iclass 27, count 2 2006.285.16:48:22.61#ibcon#about to write, iclass 27, count 2 2006.285.16:48:22.61#ibcon#wrote, iclass 27, count 2 2006.285.16:48:22.61#ibcon#about to read 3, iclass 27, count 2 2006.285.16:48:22.63#ibcon#read 3, iclass 27, count 2 2006.285.16:48:22.63#ibcon#about to read 4, iclass 27, count 2 2006.285.16:48:22.63#ibcon#read 4, iclass 27, count 2 2006.285.16:48:22.63#ibcon#about to read 5, iclass 27, count 2 2006.285.16:48:22.63#ibcon#read 5, iclass 27, count 2 2006.285.16:48:22.63#ibcon#about to read 6, iclass 27, count 2 2006.285.16:48:22.63#ibcon#read 6, iclass 27, count 2 2006.285.16:48:22.63#ibcon#end of sib2, iclass 27, count 2 2006.285.16:48:22.63#ibcon#*mode == 0, iclass 27, count 2 2006.285.16:48:22.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.16:48:22.63#ibcon#[27=AT02-05\r\n] 2006.285.16:48:22.63#ibcon#*before write, iclass 27, count 2 2006.285.16:48:22.63#ibcon#enter sib2, iclass 27, count 2 2006.285.16:48:22.63#ibcon#flushed, iclass 27, count 2 2006.285.16:48:22.63#ibcon#about to write, iclass 27, count 2 2006.285.16:48:22.63#ibcon#wrote, iclass 27, count 2 2006.285.16:48:22.63#ibcon#about to read 3, iclass 27, count 2 2006.285.16:48:22.66#ibcon#read 3, iclass 27, count 2 2006.285.16:48:22.66#ibcon#about to read 4, iclass 27, count 2 2006.285.16:48:22.66#ibcon#read 4, iclass 27, count 2 2006.285.16:48:22.66#ibcon#about to read 5, iclass 27, count 2 2006.285.16:48:22.66#ibcon#read 5, iclass 27, count 2 2006.285.16:48:22.66#ibcon#about to read 6, iclass 27, count 2 2006.285.16:48:22.66#ibcon#read 6, iclass 27, count 2 2006.285.16:48:22.66#ibcon#end of sib2, iclass 27, count 2 2006.285.16:48:22.66#ibcon#*after write, iclass 27, count 2 2006.285.16:48:22.66#ibcon#*before return 0, iclass 27, count 2 2006.285.16:48:22.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:48:22.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.16:48:22.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.16:48:22.66#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:22.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:48:22.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:48:22.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:48:22.78#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:48:22.78#ibcon#first serial, iclass 27, count 0 2006.285.16:48:22.78#ibcon#enter sib2, iclass 27, count 0 2006.285.16:48:22.78#ibcon#flushed, iclass 27, count 0 2006.285.16:48:22.78#ibcon#about to write, iclass 27, count 0 2006.285.16:48:22.78#ibcon#wrote, iclass 27, count 0 2006.285.16:48:22.78#ibcon#about to read 3, iclass 27, count 0 2006.285.16:48:22.80#ibcon#read 3, iclass 27, count 0 2006.285.16:48:22.80#ibcon#about to read 4, iclass 27, count 0 2006.285.16:48:22.80#ibcon#read 4, iclass 27, count 0 2006.285.16:48:22.80#ibcon#about to read 5, iclass 27, count 0 2006.285.16:48:22.80#ibcon#read 5, iclass 27, count 0 2006.285.16:48:22.80#ibcon#about to read 6, iclass 27, count 0 2006.285.16:48:22.80#ibcon#read 6, iclass 27, count 0 2006.285.16:48:22.80#ibcon#end of sib2, iclass 27, count 0 2006.285.16:48:22.80#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:48:22.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:48:22.80#ibcon#[27=USB\r\n] 2006.285.16:48:22.80#ibcon#*before write, iclass 27, count 0 2006.285.16:48:22.80#ibcon#enter sib2, iclass 27, count 0 2006.285.16:48:22.80#ibcon#flushed, iclass 27, count 0 2006.285.16:48:22.80#ibcon#about to write, iclass 27, count 0 2006.285.16:48:22.80#ibcon#wrote, iclass 27, count 0 2006.285.16:48:22.80#ibcon#about to read 3, iclass 27, count 0 2006.285.16:48:22.83#ibcon#read 3, iclass 27, count 0 2006.285.16:48:22.83#ibcon#about to read 4, iclass 27, count 0 2006.285.16:48:22.83#ibcon#read 4, iclass 27, count 0 2006.285.16:48:22.83#ibcon#about to read 5, iclass 27, count 0 2006.285.16:48:22.83#ibcon#read 5, iclass 27, count 0 2006.285.16:48:22.83#ibcon#about to read 6, iclass 27, count 0 2006.285.16:48:22.83#ibcon#read 6, iclass 27, count 0 2006.285.16:48:22.83#ibcon#end of sib2, iclass 27, count 0 2006.285.16:48:22.83#ibcon#*after write, iclass 27, count 0 2006.285.16:48:22.83#ibcon#*before return 0, iclass 27, count 0 2006.285.16:48:22.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:48:22.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.16:48:22.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:48:22.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:48:22.83$vck44/vblo=3,649.99 2006.285.16:48:22.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.16:48:22.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.16:48:22.83#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:22.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:48:22.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:48:22.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:48:22.83#ibcon#enter wrdev, iclass 29, count 0 2006.285.16:48:22.83#ibcon#first serial, iclass 29, count 0 2006.285.16:48:22.83#ibcon#enter sib2, iclass 29, count 0 2006.285.16:48:22.83#ibcon#flushed, iclass 29, count 0 2006.285.16:48:22.83#ibcon#about to write, iclass 29, count 0 2006.285.16:48:22.83#ibcon#wrote, iclass 29, count 0 2006.285.16:48:22.83#ibcon#about to read 3, iclass 29, count 0 2006.285.16:48:22.85#ibcon#read 3, iclass 29, count 0 2006.285.16:48:22.85#ibcon#about to read 4, iclass 29, count 0 2006.285.16:48:22.85#ibcon#read 4, iclass 29, count 0 2006.285.16:48:22.85#ibcon#about to read 5, iclass 29, count 0 2006.285.16:48:22.85#ibcon#read 5, iclass 29, count 0 2006.285.16:48:22.85#ibcon#about to read 6, iclass 29, count 0 2006.285.16:48:22.85#ibcon#read 6, iclass 29, count 0 2006.285.16:48:22.85#ibcon#end of sib2, iclass 29, count 0 2006.285.16:48:22.85#ibcon#*mode == 0, iclass 29, count 0 2006.285.16:48:22.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.16:48:22.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.16:48:22.85#ibcon#*before write, iclass 29, count 0 2006.285.16:48:22.85#ibcon#enter sib2, iclass 29, count 0 2006.285.16:48:22.85#ibcon#flushed, iclass 29, count 0 2006.285.16:48:22.85#ibcon#about to write, iclass 29, count 0 2006.285.16:48:22.85#ibcon#wrote, iclass 29, count 0 2006.285.16:48:22.85#ibcon#about to read 3, iclass 29, count 0 2006.285.16:48:22.89#ibcon#read 3, iclass 29, count 0 2006.285.16:48:22.89#ibcon#about to read 4, iclass 29, count 0 2006.285.16:48:22.89#ibcon#read 4, iclass 29, count 0 2006.285.16:48:22.89#ibcon#about to read 5, iclass 29, count 0 2006.285.16:48:22.89#ibcon#read 5, iclass 29, count 0 2006.285.16:48:22.89#ibcon#about to read 6, iclass 29, count 0 2006.285.16:48:22.89#ibcon#read 6, iclass 29, count 0 2006.285.16:48:22.89#ibcon#end of sib2, iclass 29, count 0 2006.285.16:48:22.89#ibcon#*after write, iclass 29, count 0 2006.285.16:48:22.89#ibcon#*before return 0, iclass 29, count 0 2006.285.16:48:22.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:48:22.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.16:48:22.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.16:48:22.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.16:48:22.89$vck44/vb=3,4 2006.285.16:48:22.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.16:48:22.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.16:48:22.89#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:22.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:48:22.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:48:22.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:48:22.95#ibcon#enter wrdev, iclass 31, count 2 2006.285.16:48:22.95#ibcon#first serial, iclass 31, count 2 2006.285.16:48:22.95#ibcon#enter sib2, iclass 31, count 2 2006.285.16:48:22.95#ibcon#flushed, iclass 31, count 2 2006.285.16:48:22.95#ibcon#about to write, iclass 31, count 2 2006.285.16:48:22.95#ibcon#wrote, iclass 31, count 2 2006.285.16:48:22.95#ibcon#about to read 3, iclass 31, count 2 2006.285.16:48:22.97#ibcon#read 3, iclass 31, count 2 2006.285.16:48:22.97#ibcon#about to read 4, iclass 31, count 2 2006.285.16:48:22.97#ibcon#read 4, iclass 31, count 2 2006.285.16:48:22.97#ibcon#about to read 5, iclass 31, count 2 2006.285.16:48:22.97#ibcon#read 5, iclass 31, count 2 2006.285.16:48:22.97#ibcon#about to read 6, iclass 31, count 2 2006.285.16:48:22.97#ibcon#read 6, iclass 31, count 2 2006.285.16:48:22.97#ibcon#end of sib2, iclass 31, count 2 2006.285.16:48:22.97#ibcon#*mode == 0, iclass 31, count 2 2006.285.16:48:22.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.16:48:22.97#ibcon#[27=AT03-04\r\n] 2006.285.16:48:22.97#ibcon#*before write, iclass 31, count 2 2006.285.16:48:22.97#ibcon#enter sib2, iclass 31, count 2 2006.285.16:48:22.97#ibcon#flushed, iclass 31, count 2 2006.285.16:48:22.97#ibcon#about to write, iclass 31, count 2 2006.285.16:48:22.97#ibcon#wrote, iclass 31, count 2 2006.285.16:48:22.97#ibcon#about to read 3, iclass 31, count 2 2006.285.16:48:23.00#ibcon#read 3, iclass 31, count 2 2006.285.16:48:23.00#ibcon#about to read 4, iclass 31, count 2 2006.285.16:48:23.00#ibcon#read 4, iclass 31, count 2 2006.285.16:48:23.00#ibcon#about to read 5, iclass 31, count 2 2006.285.16:48:23.00#ibcon#read 5, iclass 31, count 2 2006.285.16:48:23.00#ibcon#about to read 6, iclass 31, count 2 2006.285.16:48:23.00#ibcon#read 6, iclass 31, count 2 2006.285.16:48:23.00#ibcon#end of sib2, iclass 31, count 2 2006.285.16:48:23.00#ibcon#*after write, iclass 31, count 2 2006.285.16:48:23.00#ibcon#*before return 0, iclass 31, count 2 2006.285.16:48:23.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:48:23.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.16:48:23.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.16:48:23.00#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:23.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:48:23.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:48:23.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:48:23.12#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:48:23.12#ibcon#first serial, iclass 31, count 0 2006.285.16:48:23.12#ibcon#enter sib2, iclass 31, count 0 2006.285.16:48:23.12#ibcon#flushed, iclass 31, count 0 2006.285.16:48:23.12#ibcon#about to write, iclass 31, count 0 2006.285.16:48:23.12#ibcon#wrote, iclass 31, count 0 2006.285.16:48:23.12#ibcon#about to read 3, iclass 31, count 0 2006.285.16:48:23.14#ibcon#read 3, iclass 31, count 0 2006.285.16:48:23.14#ibcon#about to read 4, iclass 31, count 0 2006.285.16:48:23.14#ibcon#read 4, iclass 31, count 0 2006.285.16:48:23.14#ibcon#about to read 5, iclass 31, count 0 2006.285.16:48:23.14#ibcon#read 5, iclass 31, count 0 2006.285.16:48:23.14#ibcon#about to read 6, iclass 31, count 0 2006.285.16:48:23.14#ibcon#read 6, iclass 31, count 0 2006.285.16:48:23.14#ibcon#end of sib2, iclass 31, count 0 2006.285.16:48:23.14#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:48:23.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:48:23.14#ibcon#[27=USB\r\n] 2006.285.16:48:23.14#ibcon#*before write, iclass 31, count 0 2006.285.16:48:23.14#ibcon#enter sib2, iclass 31, count 0 2006.285.16:48:23.14#ibcon#flushed, iclass 31, count 0 2006.285.16:48:23.14#ibcon#about to write, iclass 31, count 0 2006.285.16:48:23.14#ibcon#wrote, iclass 31, count 0 2006.285.16:48:23.14#ibcon#about to read 3, iclass 31, count 0 2006.285.16:48:23.17#ibcon#read 3, iclass 31, count 0 2006.285.16:48:23.17#ibcon#about to read 4, iclass 31, count 0 2006.285.16:48:23.22#ibcon#read 4, iclass 31, count 0 2006.285.16:48:23.22#ibcon#about to read 5, iclass 31, count 0 2006.285.16:48:23.22#ibcon#read 5, iclass 31, count 0 2006.285.16:48:23.22#ibcon#about to read 6, iclass 31, count 0 2006.285.16:48:23.22#ibcon#read 6, iclass 31, count 0 2006.285.16:48:23.22#ibcon#end of sib2, iclass 31, count 0 2006.285.16:48:23.22#ibcon#*after write, iclass 31, count 0 2006.285.16:48:23.22#ibcon#*before return 0, iclass 31, count 0 2006.285.16:48:23.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:48:23.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.16:48:23.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:48:23.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:48:23.22$vck44/vblo=4,679.99 2006.285.16:48:23.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.16:48:23.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.16:48:23.22#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:23.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:48:23.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:48:23.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:48:23.22#ibcon#enter wrdev, iclass 33, count 0 2006.285.16:48:23.22#ibcon#first serial, iclass 33, count 0 2006.285.16:48:23.22#ibcon#enter sib2, iclass 33, count 0 2006.285.16:48:23.22#ibcon#flushed, iclass 33, count 0 2006.285.16:48:23.22#ibcon#about to write, iclass 33, count 0 2006.285.16:48:23.22#ibcon#wrote, iclass 33, count 0 2006.285.16:48:23.22#ibcon#about to read 3, iclass 33, count 0 2006.285.16:48:23.24#ibcon#read 3, iclass 33, count 0 2006.285.16:48:23.24#ibcon#about to read 4, iclass 33, count 0 2006.285.16:48:23.24#ibcon#read 4, iclass 33, count 0 2006.285.16:48:23.24#ibcon#about to read 5, iclass 33, count 0 2006.285.16:48:23.24#ibcon#read 5, iclass 33, count 0 2006.285.16:48:23.24#ibcon#about to read 6, iclass 33, count 0 2006.285.16:48:23.24#ibcon#read 6, iclass 33, count 0 2006.285.16:48:23.24#ibcon#end of sib2, iclass 33, count 0 2006.285.16:48:23.24#ibcon#*mode == 0, iclass 33, count 0 2006.285.16:48:23.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.16:48:23.24#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.16:48:23.24#ibcon#*before write, iclass 33, count 0 2006.285.16:48:23.24#ibcon#enter sib2, iclass 33, count 0 2006.285.16:48:23.24#ibcon#flushed, iclass 33, count 0 2006.285.16:48:23.24#ibcon#about to write, iclass 33, count 0 2006.285.16:48:23.24#ibcon#wrote, iclass 33, count 0 2006.285.16:48:23.24#ibcon#about to read 3, iclass 33, count 0 2006.285.16:48:23.28#ibcon#read 3, iclass 33, count 0 2006.285.16:48:23.28#ibcon#about to read 4, iclass 33, count 0 2006.285.16:48:23.28#ibcon#read 4, iclass 33, count 0 2006.285.16:48:23.28#ibcon#about to read 5, iclass 33, count 0 2006.285.16:48:23.28#ibcon#read 5, iclass 33, count 0 2006.285.16:48:23.28#ibcon#about to read 6, iclass 33, count 0 2006.285.16:48:23.28#ibcon#read 6, iclass 33, count 0 2006.285.16:48:23.28#ibcon#end of sib2, iclass 33, count 0 2006.285.16:48:23.28#ibcon#*after write, iclass 33, count 0 2006.285.16:48:23.28#ibcon#*before return 0, iclass 33, count 0 2006.285.16:48:23.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:48:23.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.16:48:23.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.16:48:23.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.16:48:23.28$vck44/vb=4,5 2006.285.16:48:23.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.16:48:23.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.16:48:23.28#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:23.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:48:23.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:48:23.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:48:23.34#ibcon#enter wrdev, iclass 35, count 2 2006.285.16:48:23.34#ibcon#first serial, iclass 35, count 2 2006.285.16:48:23.34#ibcon#enter sib2, iclass 35, count 2 2006.285.16:48:23.34#ibcon#flushed, iclass 35, count 2 2006.285.16:48:23.34#ibcon#about to write, iclass 35, count 2 2006.285.16:48:23.34#ibcon#wrote, iclass 35, count 2 2006.285.16:48:23.34#ibcon#about to read 3, iclass 35, count 2 2006.285.16:48:23.36#ibcon#read 3, iclass 35, count 2 2006.285.16:48:23.36#ibcon#about to read 4, iclass 35, count 2 2006.285.16:48:23.36#ibcon#read 4, iclass 35, count 2 2006.285.16:48:23.36#ibcon#about to read 5, iclass 35, count 2 2006.285.16:48:23.36#ibcon#read 5, iclass 35, count 2 2006.285.16:48:23.36#ibcon#about to read 6, iclass 35, count 2 2006.285.16:48:23.36#ibcon#read 6, iclass 35, count 2 2006.285.16:48:23.36#ibcon#end of sib2, iclass 35, count 2 2006.285.16:48:23.36#ibcon#*mode == 0, iclass 35, count 2 2006.285.16:48:23.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.16:48:23.36#ibcon#[27=AT04-05\r\n] 2006.285.16:48:23.36#ibcon#*before write, iclass 35, count 2 2006.285.16:48:23.36#ibcon#enter sib2, iclass 35, count 2 2006.285.16:48:23.36#ibcon#flushed, iclass 35, count 2 2006.285.16:48:23.36#ibcon#about to write, iclass 35, count 2 2006.285.16:48:23.36#ibcon#wrote, iclass 35, count 2 2006.285.16:48:23.36#ibcon#about to read 3, iclass 35, count 2 2006.285.16:48:23.39#ibcon#read 3, iclass 35, count 2 2006.285.16:48:23.39#ibcon#about to read 4, iclass 35, count 2 2006.285.16:48:23.39#ibcon#read 4, iclass 35, count 2 2006.285.16:48:23.39#ibcon#about to read 5, iclass 35, count 2 2006.285.16:48:23.39#ibcon#read 5, iclass 35, count 2 2006.285.16:48:23.39#ibcon#about to read 6, iclass 35, count 2 2006.285.16:48:23.39#ibcon#read 6, iclass 35, count 2 2006.285.16:48:23.39#ibcon#end of sib2, iclass 35, count 2 2006.285.16:48:23.39#ibcon#*after write, iclass 35, count 2 2006.285.16:48:23.39#ibcon#*before return 0, iclass 35, count 2 2006.285.16:48:23.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:48:23.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.16:48:23.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.16:48:23.39#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:23.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:48:23.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:48:23.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:48:23.51#ibcon#enter wrdev, iclass 35, count 0 2006.285.16:48:23.51#ibcon#first serial, iclass 35, count 0 2006.285.16:48:23.51#ibcon#enter sib2, iclass 35, count 0 2006.285.16:48:23.51#ibcon#flushed, iclass 35, count 0 2006.285.16:48:23.51#ibcon#about to write, iclass 35, count 0 2006.285.16:48:23.51#ibcon#wrote, iclass 35, count 0 2006.285.16:48:23.51#ibcon#about to read 3, iclass 35, count 0 2006.285.16:48:23.53#ibcon#read 3, iclass 35, count 0 2006.285.16:48:23.53#ibcon#about to read 4, iclass 35, count 0 2006.285.16:48:23.53#ibcon#read 4, iclass 35, count 0 2006.285.16:48:23.53#ibcon#about to read 5, iclass 35, count 0 2006.285.16:48:23.53#ibcon#read 5, iclass 35, count 0 2006.285.16:48:23.53#ibcon#about to read 6, iclass 35, count 0 2006.285.16:48:23.53#ibcon#read 6, iclass 35, count 0 2006.285.16:48:23.53#ibcon#end of sib2, iclass 35, count 0 2006.285.16:48:23.53#ibcon#*mode == 0, iclass 35, count 0 2006.285.16:48:23.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.16:48:23.53#ibcon#[27=USB\r\n] 2006.285.16:48:23.53#ibcon#*before write, iclass 35, count 0 2006.285.16:48:23.53#ibcon#enter sib2, iclass 35, count 0 2006.285.16:48:23.53#ibcon#flushed, iclass 35, count 0 2006.285.16:48:23.53#ibcon#about to write, iclass 35, count 0 2006.285.16:48:23.53#ibcon#wrote, iclass 35, count 0 2006.285.16:48:23.53#ibcon#about to read 3, iclass 35, count 0 2006.285.16:48:23.56#ibcon#read 3, iclass 35, count 0 2006.285.16:48:23.56#ibcon#about to read 4, iclass 35, count 0 2006.285.16:48:23.56#ibcon#read 4, iclass 35, count 0 2006.285.16:48:23.56#ibcon#about to read 5, iclass 35, count 0 2006.285.16:48:23.56#ibcon#read 5, iclass 35, count 0 2006.285.16:48:23.56#ibcon#about to read 6, iclass 35, count 0 2006.285.16:48:23.56#ibcon#read 6, iclass 35, count 0 2006.285.16:48:23.56#ibcon#end of sib2, iclass 35, count 0 2006.285.16:48:23.56#ibcon#*after write, iclass 35, count 0 2006.285.16:48:23.56#ibcon#*before return 0, iclass 35, count 0 2006.285.16:48:23.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:48:23.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.16:48:23.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.16:48:23.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.16:48:23.56$vck44/vblo=5,709.99 2006.285.16:48:23.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.16:48:23.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.16:48:23.56#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:23.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:48:23.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:48:23.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:48:23.56#ibcon#enter wrdev, iclass 37, count 0 2006.285.16:48:23.56#ibcon#first serial, iclass 37, count 0 2006.285.16:48:23.56#ibcon#enter sib2, iclass 37, count 0 2006.285.16:48:23.56#ibcon#flushed, iclass 37, count 0 2006.285.16:48:23.56#ibcon#about to write, iclass 37, count 0 2006.285.16:48:23.56#ibcon#wrote, iclass 37, count 0 2006.285.16:48:23.56#ibcon#about to read 3, iclass 37, count 0 2006.285.16:48:23.58#ibcon#read 3, iclass 37, count 0 2006.285.16:48:23.58#ibcon#about to read 4, iclass 37, count 0 2006.285.16:48:23.58#ibcon#read 4, iclass 37, count 0 2006.285.16:48:23.58#ibcon#about to read 5, iclass 37, count 0 2006.285.16:48:23.58#ibcon#read 5, iclass 37, count 0 2006.285.16:48:23.58#ibcon#about to read 6, iclass 37, count 0 2006.285.16:48:23.58#ibcon#read 6, iclass 37, count 0 2006.285.16:48:23.58#ibcon#end of sib2, iclass 37, count 0 2006.285.16:48:23.58#ibcon#*mode == 0, iclass 37, count 0 2006.285.16:48:23.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.16:48:23.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.16:48:23.58#ibcon#*before write, iclass 37, count 0 2006.285.16:48:23.58#ibcon#enter sib2, iclass 37, count 0 2006.285.16:48:23.58#ibcon#flushed, iclass 37, count 0 2006.285.16:48:23.58#ibcon#about to write, iclass 37, count 0 2006.285.16:48:23.58#ibcon#wrote, iclass 37, count 0 2006.285.16:48:23.58#ibcon#about to read 3, iclass 37, count 0 2006.285.16:48:23.62#ibcon#read 3, iclass 37, count 0 2006.285.16:48:23.62#ibcon#about to read 4, iclass 37, count 0 2006.285.16:48:23.62#ibcon#read 4, iclass 37, count 0 2006.285.16:48:23.62#ibcon#about to read 5, iclass 37, count 0 2006.285.16:48:23.62#ibcon#read 5, iclass 37, count 0 2006.285.16:48:23.62#ibcon#about to read 6, iclass 37, count 0 2006.285.16:48:23.62#ibcon#read 6, iclass 37, count 0 2006.285.16:48:23.62#ibcon#end of sib2, iclass 37, count 0 2006.285.16:48:23.62#ibcon#*after write, iclass 37, count 0 2006.285.16:48:23.62#ibcon#*before return 0, iclass 37, count 0 2006.285.16:48:23.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:48:23.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.16:48:23.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.16:48:23.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.16:48:23.62$vck44/vb=5,4 2006.285.16:48:23.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.16:48:23.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.16:48:23.62#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:23.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:48:23.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:48:23.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:48:23.68#ibcon#enter wrdev, iclass 39, count 2 2006.285.16:48:23.68#ibcon#first serial, iclass 39, count 2 2006.285.16:48:23.68#ibcon#enter sib2, iclass 39, count 2 2006.285.16:48:23.68#ibcon#flushed, iclass 39, count 2 2006.285.16:48:23.68#ibcon#about to write, iclass 39, count 2 2006.285.16:48:23.68#ibcon#wrote, iclass 39, count 2 2006.285.16:48:23.68#ibcon#about to read 3, iclass 39, count 2 2006.285.16:48:23.70#ibcon#read 3, iclass 39, count 2 2006.285.16:48:23.70#ibcon#about to read 4, iclass 39, count 2 2006.285.16:48:23.70#ibcon#read 4, iclass 39, count 2 2006.285.16:48:23.70#ibcon#about to read 5, iclass 39, count 2 2006.285.16:48:23.70#ibcon#read 5, iclass 39, count 2 2006.285.16:48:23.70#ibcon#about to read 6, iclass 39, count 2 2006.285.16:48:23.70#ibcon#read 6, iclass 39, count 2 2006.285.16:48:23.70#ibcon#end of sib2, iclass 39, count 2 2006.285.16:48:23.70#ibcon#*mode == 0, iclass 39, count 2 2006.285.16:48:23.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.16:48:23.70#ibcon#[27=AT05-04\r\n] 2006.285.16:48:23.70#ibcon#*before write, iclass 39, count 2 2006.285.16:48:23.70#ibcon#enter sib2, iclass 39, count 2 2006.285.16:48:23.70#ibcon#flushed, iclass 39, count 2 2006.285.16:48:23.70#ibcon#about to write, iclass 39, count 2 2006.285.16:48:23.70#ibcon#wrote, iclass 39, count 2 2006.285.16:48:23.70#ibcon#about to read 3, iclass 39, count 2 2006.285.16:48:23.73#ibcon#read 3, iclass 39, count 2 2006.285.16:48:23.73#ibcon#about to read 4, iclass 39, count 2 2006.285.16:48:23.73#ibcon#read 4, iclass 39, count 2 2006.285.16:48:23.73#ibcon#about to read 5, iclass 39, count 2 2006.285.16:48:23.73#ibcon#read 5, iclass 39, count 2 2006.285.16:48:23.73#ibcon#about to read 6, iclass 39, count 2 2006.285.16:48:23.73#ibcon#read 6, iclass 39, count 2 2006.285.16:48:23.73#ibcon#end of sib2, iclass 39, count 2 2006.285.16:48:23.73#ibcon#*after write, iclass 39, count 2 2006.285.16:48:23.73#ibcon#*before return 0, iclass 39, count 2 2006.285.16:48:23.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:48:23.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.16:48:23.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.16:48:23.73#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:23.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:48:23.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:48:23.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:48:23.85#ibcon#enter wrdev, iclass 39, count 0 2006.285.16:48:23.85#ibcon#first serial, iclass 39, count 0 2006.285.16:48:23.85#ibcon#enter sib2, iclass 39, count 0 2006.285.16:48:23.85#ibcon#flushed, iclass 39, count 0 2006.285.16:48:23.85#ibcon#about to write, iclass 39, count 0 2006.285.16:48:23.85#ibcon#wrote, iclass 39, count 0 2006.285.16:48:23.85#ibcon#about to read 3, iclass 39, count 0 2006.285.16:48:23.87#ibcon#read 3, iclass 39, count 0 2006.285.16:48:23.87#ibcon#about to read 4, iclass 39, count 0 2006.285.16:48:23.87#ibcon#read 4, iclass 39, count 0 2006.285.16:48:23.87#ibcon#about to read 5, iclass 39, count 0 2006.285.16:48:23.87#ibcon#read 5, iclass 39, count 0 2006.285.16:48:23.87#ibcon#about to read 6, iclass 39, count 0 2006.285.16:48:23.87#ibcon#read 6, iclass 39, count 0 2006.285.16:48:23.87#ibcon#end of sib2, iclass 39, count 0 2006.285.16:48:23.87#ibcon#*mode == 0, iclass 39, count 0 2006.285.16:48:23.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.16:48:23.87#ibcon#[27=USB\r\n] 2006.285.16:48:23.87#ibcon#*before write, iclass 39, count 0 2006.285.16:48:23.87#ibcon#enter sib2, iclass 39, count 0 2006.285.16:48:23.87#ibcon#flushed, iclass 39, count 0 2006.285.16:48:23.87#ibcon#about to write, iclass 39, count 0 2006.285.16:48:23.87#ibcon#wrote, iclass 39, count 0 2006.285.16:48:23.87#ibcon#about to read 3, iclass 39, count 0 2006.285.16:48:23.90#ibcon#read 3, iclass 39, count 0 2006.285.16:48:23.90#ibcon#about to read 4, iclass 39, count 0 2006.285.16:48:23.90#ibcon#read 4, iclass 39, count 0 2006.285.16:48:23.90#ibcon#about to read 5, iclass 39, count 0 2006.285.16:48:23.90#ibcon#read 5, iclass 39, count 0 2006.285.16:48:23.90#ibcon#about to read 6, iclass 39, count 0 2006.285.16:48:23.90#ibcon#read 6, iclass 39, count 0 2006.285.16:48:23.90#ibcon#end of sib2, iclass 39, count 0 2006.285.16:48:23.90#ibcon#*after write, iclass 39, count 0 2006.285.16:48:23.90#ibcon#*before return 0, iclass 39, count 0 2006.285.16:48:23.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:48:23.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.16:48:23.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.16:48:23.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.16:48:23.90$vck44/vblo=6,719.99 2006.285.16:48:23.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.16:48:23.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.16:48:23.90#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:23.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:48:23.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:48:23.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:48:23.90#ibcon#enter wrdev, iclass 3, count 0 2006.285.16:48:23.90#ibcon#first serial, iclass 3, count 0 2006.285.16:48:23.90#ibcon#enter sib2, iclass 3, count 0 2006.285.16:48:23.90#ibcon#flushed, iclass 3, count 0 2006.285.16:48:23.90#ibcon#about to write, iclass 3, count 0 2006.285.16:48:23.90#ibcon#wrote, iclass 3, count 0 2006.285.16:48:23.90#ibcon#about to read 3, iclass 3, count 0 2006.285.16:48:23.92#ibcon#read 3, iclass 3, count 0 2006.285.16:48:23.92#ibcon#about to read 4, iclass 3, count 0 2006.285.16:48:23.92#ibcon#read 4, iclass 3, count 0 2006.285.16:48:23.92#ibcon#about to read 5, iclass 3, count 0 2006.285.16:48:23.92#ibcon#read 5, iclass 3, count 0 2006.285.16:48:23.92#ibcon#about to read 6, iclass 3, count 0 2006.285.16:48:23.92#ibcon#read 6, iclass 3, count 0 2006.285.16:48:23.92#ibcon#end of sib2, iclass 3, count 0 2006.285.16:48:23.92#ibcon#*mode == 0, iclass 3, count 0 2006.285.16:48:23.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.16:48:23.92#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.16:48:23.92#ibcon#*before write, iclass 3, count 0 2006.285.16:48:23.92#ibcon#enter sib2, iclass 3, count 0 2006.285.16:48:23.92#ibcon#flushed, iclass 3, count 0 2006.285.16:48:23.92#ibcon#about to write, iclass 3, count 0 2006.285.16:48:23.92#ibcon#wrote, iclass 3, count 0 2006.285.16:48:23.92#ibcon#about to read 3, iclass 3, count 0 2006.285.16:48:23.96#ibcon#read 3, iclass 3, count 0 2006.285.16:48:23.96#ibcon#about to read 4, iclass 3, count 0 2006.285.16:48:23.96#ibcon#read 4, iclass 3, count 0 2006.285.16:48:23.96#ibcon#about to read 5, iclass 3, count 0 2006.285.16:48:23.96#ibcon#read 5, iclass 3, count 0 2006.285.16:48:23.96#ibcon#about to read 6, iclass 3, count 0 2006.285.16:48:23.96#ibcon#read 6, iclass 3, count 0 2006.285.16:48:23.96#ibcon#end of sib2, iclass 3, count 0 2006.285.16:48:23.96#ibcon#*after write, iclass 3, count 0 2006.285.16:48:23.96#ibcon#*before return 0, iclass 3, count 0 2006.285.16:48:23.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:48:23.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.16:48:23.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.16:48:23.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.16:48:23.96$vck44/vb=6,3 2006.285.16:48:23.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.16:48:23.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.16:48:23.96#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:23.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:48:24.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:48:24.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:48:24.02#ibcon#enter wrdev, iclass 5, count 2 2006.285.16:48:24.02#ibcon#first serial, iclass 5, count 2 2006.285.16:48:24.02#ibcon#enter sib2, iclass 5, count 2 2006.285.16:48:24.02#ibcon#flushed, iclass 5, count 2 2006.285.16:48:24.02#ibcon#about to write, iclass 5, count 2 2006.285.16:48:24.02#ibcon#wrote, iclass 5, count 2 2006.285.16:48:24.02#ibcon#about to read 3, iclass 5, count 2 2006.285.16:48:24.04#ibcon#read 3, iclass 5, count 2 2006.285.16:48:24.04#ibcon#about to read 4, iclass 5, count 2 2006.285.16:48:24.04#ibcon#read 4, iclass 5, count 2 2006.285.16:48:24.04#ibcon#about to read 5, iclass 5, count 2 2006.285.16:48:24.04#ibcon#read 5, iclass 5, count 2 2006.285.16:48:24.04#ibcon#about to read 6, iclass 5, count 2 2006.285.16:48:24.04#ibcon#read 6, iclass 5, count 2 2006.285.16:48:24.04#ibcon#end of sib2, iclass 5, count 2 2006.285.16:48:24.04#ibcon#*mode == 0, iclass 5, count 2 2006.285.16:48:24.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.16:48:24.04#ibcon#[27=AT06-03\r\n] 2006.285.16:48:24.04#ibcon#*before write, iclass 5, count 2 2006.285.16:48:24.04#ibcon#enter sib2, iclass 5, count 2 2006.285.16:48:24.04#ibcon#flushed, iclass 5, count 2 2006.285.16:48:24.04#ibcon#about to write, iclass 5, count 2 2006.285.16:48:24.04#ibcon#wrote, iclass 5, count 2 2006.285.16:48:24.04#ibcon#about to read 3, iclass 5, count 2 2006.285.16:48:24.07#ibcon#read 3, iclass 5, count 2 2006.285.16:48:24.07#ibcon#about to read 4, iclass 5, count 2 2006.285.16:48:24.07#ibcon#read 4, iclass 5, count 2 2006.285.16:48:24.07#ibcon#about to read 5, iclass 5, count 2 2006.285.16:48:24.07#ibcon#read 5, iclass 5, count 2 2006.285.16:48:24.07#ibcon#about to read 6, iclass 5, count 2 2006.285.16:48:24.07#ibcon#read 6, iclass 5, count 2 2006.285.16:48:24.07#ibcon#end of sib2, iclass 5, count 2 2006.285.16:48:24.07#ibcon#*after write, iclass 5, count 2 2006.285.16:48:24.07#ibcon#*before return 0, iclass 5, count 2 2006.285.16:48:24.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:48:24.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.16:48:24.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.16:48:24.07#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:24.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:48:24.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:48:24.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:48:24.19#ibcon#enter wrdev, iclass 5, count 0 2006.285.16:48:24.19#ibcon#first serial, iclass 5, count 0 2006.285.16:48:24.19#ibcon#enter sib2, iclass 5, count 0 2006.285.16:48:24.19#ibcon#flushed, iclass 5, count 0 2006.285.16:48:24.19#ibcon#about to write, iclass 5, count 0 2006.285.16:48:24.19#ibcon#wrote, iclass 5, count 0 2006.285.16:48:24.19#ibcon#about to read 3, iclass 5, count 0 2006.285.16:48:24.21#ibcon#read 3, iclass 5, count 0 2006.285.16:48:24.21#ibcon#about to read 4, iclass 5, count 0 2006.285.16:48:24.21#ibcon#read 4, iclass 5, count 0 2006.285.16:48:24.21#ibcon#about to read 5, iclass 5, count 0 2006.285.16:48:24.21#ibcon#read 5, iclass 5, count 0 2006.285.16:48:24.21#ibcon#about to read 6, iclass 5, count 0 2006.285.16:48:24.21#ibcon#read 6, iclass 5, count 0 2006.285.16:48:24.21#ibcon#end of sib2, iclass 5, count 0 2006.285.16:48:24.21#ibcon#*mode == 0, iclass 5, count 0 2006.285.16:48:24.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.16:48:24.21#ibcon#[27=USB\r\n] 2006.285.16:48:24.21#ibcon#*before write, iclass 5, count 0 2006.285.16:48:24.21#ibcon#enter sib2, iclass 5, count 0 2006.285.16:48:24.21#ibcon#flushed, iclass 5, count 0 2006.285.16:48:24.21#ibcon#about to write, iclass 5, count 0 2006.285.16:48:24.21#ibcon#wrote, iclass 5, count 0 2006.285.16:48:24.21#ibcon#about to read 3, iclass 5, count 0 2006.285.16:48:24.24#ibcon#read 3, iclass 5, count 0 2006.285.16:48:24.24#ibcon#about to read 4, iclass 5, count 0 2006.285.16:48:24.24#ibcon#read 4, iclass 5, count 0 2006.285.16:48:24.24#ibcon#about to read 5, iclass 5, count 0 2006.285.16:48:24.24#ibcon#read 5, iclass 5, count 0 2006.285.16:48:24.24#ibcon#about to read 6, iclass 5, count 0 2006.285.16:48:24.24#ibcon#read 6, iclass 5, count 0 2006.285.16:48:24.24#ibcon#end of sib2, iclass 5, count 0 2006.285.16:48:24.24#ibcon#*after write, iclass 5, count 0 2006.285.16:48:24.24#ibcon#*before return 0, iclass 5, count 0 2006.285.16:48:24.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:48:24.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.16:48:24.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.16:48:24.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.16:48:24.24$vck44/vblo=7,734.99 2006.285.16:48:24.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.16:48:24.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.16:48:24.24#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:24.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:48:24.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:48:24.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:48:24.24#ibcon#enter wrdev, iclass 7, count 0 2006.285.16:48:24.24#ibcon#first serial, iclass 7, count 0 2006.285.16:48:24.24#ibcon#enter sib2, iclass 7, count 0 2006.285.16:48:24.24#ibcon#flushed, iclass 7, count 0 2006.285.16:48:24.24#ibcon#about to write, iclass 7, count 0 2006.285.16:48:24.24#ibcon#wrote, iclass 7, count 0 2006.285.16:48:24.24#ibcon#about to read 3, iclass 7, count 0 2006.285.16:48:24.26#ibcon#read 3, iclass 7, count 0 2006.285.16:48:24.26#ibcon#about to read 4, iclass 7, count 0 2006.285.16:48:24.26#ibcon#read 4, iclass 7, count 0 2006.285.16:48:24.26#ibcon#about to read 5, iclass 7, count 0 2006.285.16:48:24.26#ibcon#read 5, iclass 7, count 0 2006.285.16:48:24.26#ibcon#about to read 6, iclass 7, count 0 2006.285.16:48:24.26#ibcon#read 6, iclass 7, count 0 2006.285.16:48:24.26#ibcon#end of sib2, iclass 7, count 0 2006.285.16:48:24.26#ibcon#*mode == 0, iclass 7, count 0 2006.285.16:48:24.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.16:48:24.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.16:48:24.26#ibcon#*before write, iclass 7, count 0 2006.285.16:48:24.26#ibcon#enter sib2, iclass 7, count 0 2006.285.16:48:24.26#ibcon#flushed, iclass 7, count 0 2006.285.16:48:24.26#ibcon#about to write, iclass 7, count 0 2006.285.16:48:24.26#ibcon#wrote, iclass 7, count 0 2006.285.16:48:24.26#ibcon#about to read 3, iclass 7, count 0 2006.285.16:48:24.30#ibcon#read 3, iclass 7, count 0 2006.285.16:48:24.30#ibcon#about to read 4, iclass 7, count 0 2006.285.16:48:24.30#ibcon#read 4, iclass 7, count 0 2006.285.16:48:24.30#ibcon#about to read 5, iclass 7, count 0 2006.285.16:48:24.30#ibcon#read 5, iclass 7, count 0 2006.285.16:48:24.30#ibcon#about to read 6, iclass 7, count 0 2006.285.16:48:24.30#ibcon#read 6, iclass 7, count 0 2006.285.16:48:24.30#ibcon#end of sib2, iclass 7, count 0 2006.285.16:48:24.30#ibcon#*after write, iclass 7, count 0 2006.285.16:48:24.30#ibcon#*before return 0, iclass 7, count 0 2006.285.16:48:24.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:48:24.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.16:48:24.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.16:48:24.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.16:48:24.30$vck44/vb=7,4 2006.285.16:48:24.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.16:48:24.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.16:48:24.30#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:24.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:48:24.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:48:24.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:48:24.36#ibcon#enter wrdev, iclass 11, count 2 2006.285.16:48:24.36#ibcon#first serial, iclass 11, count 2 2006.285.16:48:24.36#ibcon#enter sib2, iclass 11, count 2 2006.285.16:48:24.36#ibcon#flushed, iclass 11, count 2 2006.285.16:48:24.36#ibcon#about to write, iclass 11, count 2 2006.285.16:48:24.36#ibcon#wrote, iclass 11, count 2 2006.285.16:48:24.36#ibcon#about to read 3, iclass 11, count 2 2006.285.16:48:24.38#ibcon#read 3, iclass 11, count 2 2006.285.16:48:24.38#ibcon#about to read 4, iclass 11, count 2 2006.285.16:48:24.38#ibcon#read 4, iclass 11, count 2 2006.285.16:48:24.38#ibcon#about to read 5, iclass 11, count 2 2006.285.16:48:24.38#ibcon#read 5, iclass 11, count 2 2006.285.16:48:24.38#ibcon#about to read 6, iclass 11, count 2 2006.285.16:48:24.38#ibcon#read 6, iclass 11, count 2 2006.285.16:48:24.38#ibcon#end of sib2, iclass 11, count 2 2006.285.16:48:24.38#ibcon#*mode == 0, iclass 11, count 2 2006.285.16:48:24.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.16:48:24.38#ibcon#[27=AT07-04\r\n] 2006.285.16:48:24.38#ibcon#*before write, iclass 11, count 2 2006.285.16:48:24.38#ibcon#enter sib2, iclass 11, count 2 2006.285.16:48:24.38#ibcon#flushed, iclass 11, count 2 2006.285.16:48:24.38#ibcon#about to write, iclass 11, count 2 2006.285.16:48:24.38#ibcon#wrote, iclass 11, count 2 2006.285.16:48:24.38#ibcon#about to read 3, iclass 11, count 2 2006.285.16:48:24.41#ibcon#read 3, iclass 11, count 2 2006.285.16:48:24.41#ibcon#about to read 4, iclass 11, count 2 2006.285.16:48:24.41#ibcon#read 4, iclass 11, count 2 2006.285.16:48:24.41#ibcon#about to read 5, iclass 11, count 2 2006.285.16:48:24.41#ibcon#read 5, iclass 11, count 2 2006.285.16:48:24.41#ibcon#about to read 6, iclass 11, count 2 2006.285.16:48:24.41#ibcon#read 6, iclass 11, count 2 2006.285.16:48:24.41#ibcon#end of sib2, iclass 11, count 2 2006.285.16:48:24.41#ibcon#*after write, iclass 11, count 2 2006.285.16:48:24.41#ibcon#*before return 0, iclass 11, count 2 2006.285.16:48:24.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:48:24.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.16:48:24.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.16:48:24.41#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:24.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:48:24.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:48:24.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:48:24.53#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:48:24.53#ibcon#first serial, iclass 11, count 0 2006.285.16:48:24.53#ibcon#enter sib2, iclass 11, count 0 2006.285.16:48:24.53#ibcon#flushed, iclass 11, count 0 2006.285.16:48:24.53#ibcon#about to write, iclass 11, count 0 2006.285.16:48:24.53#ibcon#wrote, iclass 11, count 0 2006.285.16:48:24.53#ibcon#about to read 3, iclass 11, count 0 2006.285.16:48:24.55#ibcon#read 3, iclass 11, count 0 2006.285.16:48:24.55#ibcon#about to read 4, iclass 11, count 0 2006.285.16:48:24.55#ibcon#read 4, iclass 11, count 0 2006.285.16:48:24.55#ibcon#about to read 5, iclass 11, count 0 2006.285.16:48:24.55#ibcon#read 5, iclass 11, count 0 2006.285.16:48:24.55#ibcon#about to read 6, iclass 11, count 0 2006.285.16:48:24.55#ibcon#read 6, iclass 11, count 0 2006.285.16:48:24.55#ibcon#end of sib2, iclass 11, count 0 2006.285.16:48:24.55#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:48:24.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:48:24.55#ibcon#[27=USB\r\n] 2006.285.16:48:24.55#ibcon#*before write, iclass 11, count 0 2006.285.16:48:24.55#ibcon#enter sib2, iclass 11, count 0 2006.285.16:48:24.55#ibcon#flushed, iclass 11, count 0 2006.285.16:48:24.55#ibcon#about to write, iclass 11, count 0 2006.285.16:48:24.55#ibcon#wrote, iclass 11, count 0 2006.285.16:48:24.55#ibcon#about to read 3, iclass 11, count 0 2006.285.16:48:24.58#ibcon#read 3, iclass 11, count 0 2006.285.16:48:24.58#ibcon#about to read 4, iclass 11, count 0 2006.285.16:48:24.58#ibcon#read 4, iclass 11, count 0 2006.285.16:48:24.58#ibcon#about to read 5, iclass 11, count 0 2006.285.16:48:24.58#ibcon#read 5, iclass 11, count 0 2006.285.16:48:24.58#ibcon#about to read 6, iclass 11, count 0 2006.285.16:48:24.58#ibcon#read 6, iclass 11, count 0 2006.285.16:48:24.58#ibcon#end of sib2, iclass 11, count 0 2006.285.16:48:24.58#ibcon#*after write, iclass 11, count 0 2006.285.16:48:24.58#ibcon#*before return 0, iclass 11, count 0 2006.285.16:48:24.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:48:24.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.16:48:24.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:48:24.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:48:24.58$vck44/vblo=8,744.99 2006.285.16:48:24.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.16:48:24.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.16:48:24.58#ibcon#ireg 17 cls_cnt 0 2006.285.16:48:24.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:48:24.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:48:24.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:48:24.58#ibcon#enter wrdev, iclass 13, count 0 2006.285.16:48:24.58#ibcon#first serial, iclass 13, count 0 2006.285.16:48:24.58#ibcon#enter sib2, iclass 13, count 0 2006.285.16:48:24.58#ibcon#flushed, iclass 13, count 0 2006.285.16:48:24.58#ibcon#about to write, iclass 13, count 0 2006.285.16:48:24.58#ibcon#wrote, iclass 13, count 0 2006.285.16:48:24.58#ibcon#about to read 3, iclass 13, count 0 2006.285.16:48:24.60#ibcon#read 3, iclass 13, count 0 2006.285.16:48:24.60#ibcon#about to read 4, iclass 13, count 0 2006.285.16:48:24.60#ibcon#read 4, iclass 13, count 0 2006.285.16:48:24.60#ibcon#about to read 5, iclass 13, count 0 2006.285.16:48:24.60#ibcon#read 5, iclass 13, count 0 2006.285.16:48:24.60#ibcon#about to read 6, iclass 13, count 0 2006.285.16:48:24.60#ibcon#read 6, iclass 13, count 0 2006.285.16:48:24.60#ibcon#end of sib2, iclass 13, count 0 2006.285.16:48:24.60#ibcon#*mode == 0, iclass 13, count 0 2006.285.16:48:24.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.16:48:24.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.16:48:24.60#ibcon#*before write, iclass 13, count 0 2006.285.16:48:24.60#ibcon#enter sib2, iclass 13, count 0 2006.285.16:48:24.60#ibcon#flushed, iclass 13, count 0 2006.285.16:48:24.60#ibcon#about to write, iclass 13, count 0 2006.285.16:48:24.60#ibcon#wrote, iclass 13, count 0 2006.285.16:48:24.60#ibcon#about to read 3, iclass 13, count 0 2006.285.16:48:24.64#ibcon#read 3, iclass 13, count 0 2006.285.16:48:24.64#ibcon#about to read 4, iclass 13, count 0 2006.285.16:48:24.64#ibcon#read 4, iclass 13, count 0 2006.285.16:48:24.64#ibcon#about to read 5, iclass 13, count 0 2006.285.16:48:24.64#ibcon#read 5, iclass 13, count 0 2006.285.16:48:24.64#ibcon#about to read 6, iclass 13, count 0 2006.285.16:48:24.64#ibcon#read 6, iclass 13, count 0 2006.285.16:48:24.64#ibcon#end of sib2, iclass 13, count 0 2006.285.16:48:24.64#ibcon#*after write, iclass 13, count 0 2006.285.16:48:24.64#ibcon#*before return 0, iclass 13, count 0 2006.285.16:48:24.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:48:24.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.16:48:24.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.16:48:24.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.16:48:24.64$vck44/vb=8,4 2006.285.16:48:24.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.16:48:24.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.16:48:24.64#ibcon#ireg 11 cls_cnt 2 2006.285.16:48:24.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:48:24.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:48:24.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:48:24.70#ibcon#enter wrdev, iclass 15, count 2 2006.285.16:48:24.70#ibcon#first serial, iclass 15, count 2 2006.285.16:48:24.70#ibcon#enter sib2, iclass 15, count 2 2006.285.16:48:24.70#ibcon#flushed, iclass 15, count 2 2006.285.16:48:24.70#ibcon#about to write, iclass 15, count 2 2006.285.16:48:24.70#ibcon#wrote, iclass 15, count 2 2006.285.16:48:24.70#ibcon#about to read 3, iclass 15, count 2 2006.285.16:48:24.72#ibcon#read 3, iclass 15, count 2 2006.285.16:48:24.72#ibcon#about to read 4, iclass 15, count 2 2006.285.16:48:24.72#ibcon#read 4, iclass 15, count 2 2006.285.16:48:24.72#ibcon#about to read 5, iclass 15, count 2 2006.285.16:48:24.72#ibcon#read 5, iclass 15, count 2 2006.285.16:48:24.72#ibcon#about to read 6, iclass 15, count 2 2006.285.16:48:24.72#ibcon#read 6, iclass 15, count 2 2006.285.16:48:24.72#ibcon#end of sib2, iclass 15, count 2 2006.285.16:48:24.72#ibcon#*mode == 0, iclass 15, count 2 2006.285.16:48:24.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.16:48:24.72#ibcon#[27=AT08-04\r\n] 2006.285.16:48:24.72#ibcon#*before write, iclass 15, count 2 2006.285.16:48:24.72#ibcon#enter sib2, iclass 15, count 2 2006.285.16:48:24.72#ibcon#flushed, iclass 15, count 2 2006.285.16:48:24.72#ibcon#about to write, iclass 15, count 2 2006.285.16:48:24.72#ibcon#wrote, iclass 15, count 2 2006.285.16:48:24.72#ibcon#about to read 3, iclass 15, count 2 2006.285.16:48:24.75#ibcon#read 3, iclass 15, count 2 2006.285.16:48:24.75#ibcon#about to read 4, iclass 15, count 2 2006.285.16:48:24.75#ibcon#read 4, iclass 15, count 2 2006.285.16:48:24.75#ibcon#about to read 5, iclass 15, count 2 2006.285.16:48:24.75#ibcon#read 5, iclass 15, count 2 2006.285.16:48:24.75#ibcon#about to read 6, iclass 15, count 2 2006.285.16:48:24.75#ibcon#read 6, iclass 15, count 2 2006.285.16:48:24.75#ibcon#end of sib2, iclass 15, count 2 2006.285.16:48:24.75#ibcon#*after write, iclass 15, count 2 2006.285.16:48:24.75#ibcon#*before return 0, iclass 15, count 2 2006.285.16:48:24.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:48:24.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.16:48:24.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.16:48:24.75#ibcon#ireg 7 cls_cnt 0 2006.285.16:48:24.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:48:24.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:48:24.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:48:24.87#ibcon#enter wrdev, iclass 15, count 0 2006.285.16:48:24.87#ibcon#first serial, iclass 15, count 0 2006.285.16:48:24.87#ibcon#enter sib2, iclass 15, count 0 2006.285.16:48:24.87#ibcon#flushed, iclass 15, count 0 2006.285.16:48:24.87#ibcon#about to write, iclass 15, count 0 2006.285.16:48:24.87#ibcon#wrote, iclass 15, count 0 2006.285.16:48:24.87#ibcon#about to read 3, iclass 15, count 0 2006.285.16:48:24.89#ibcon#read 3, iclass 15, count 0 2006.285.16:48:24.89#ibcon#about to read 4, iclass 15, count 0 2006.285.16:48:24.89#ibcon#read 4, iclass 15, count 0 2006.285.16:48:24.89#ibcon#about to read 5, iclass 15, count 0 2006.285.16:48:24.89#ibcon#read 5, iclass 15, count 0 2006.285.16:48:24.89#ibcon#about to read 6, iclass 15, count 0 2006.285.16:48:24.89#ibcon#read 6, iclass 15, count 0 2006.285.16:48:24.89#ibcon#end of sib2, iclass 15, count 0 2006.285.16:48:24.89#ibcon#*mode == 0, iclass 15, count 0 2006.285.16:48:24.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.16:48:24.89#ibcon#[27=USB\r\n] 2006.285.16:48:24.89#ibcon#*before write, iclass 15, count 0 2006.285.16:48:24.89#ibcon#enter sib2, iclass 15, count 0 2006.285.16:48:24.89#ibcon#flushed, iclass 15, count 0 2006.285.16:48:24.89#ibcon#about to write, iclass 15, count 0 2006.285.16:48:24.89#ibcon#wrote, iclass 15, count 0 2006.285.16:48:24.89#ibcon#about to read 3, iclass 15, count 0 2006.285.16:48:24.92#ibcon#read 3, iclass 15, count 0 2006.285.16:48:24.92#ibcon#about to read 4, iclass 15, count 0 2006.285.16:48:24.92#ibcon#read 4, iclass 15, count 0 2006.285.16:48:24.92#ibcon#about to read 5, iclass 15, count 0 2006.285.16:48:24.92#ibcon#read 5, iclass 15, count 0 2006.285.16:48:24.92#ibcon#about to read 6, iclass 15, count 0 2006.285.16:48:24.92#ibcon#read 6, iclass 15, count 0 2006.285.16:48:24.92#ibcon#end of sib2, iclass 15, count 0 2006.285.16:48:24.92#ibcon#*after write, iclass 15, count 0 2006.285.16:48:24.92#ibcon#*before return 0, iclass 15, count 0 2006.285.16:48:24.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:48:24.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.16:48:24.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.16:48:24.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.16:48:24.92$vck44/vabw=wide 2006.285.16:48:24.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.16:48:24.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.16:48:24.92#ibcon#ireg 8 cls_cnt 0 2006.285.16:48:24.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:48:24.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:48:24.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:48:24.92#ibcon#enter wrdev, iclass 17, count 0 2006.285.16:48:24.92#ibcon#first serial, iclass 17, count 0 2006.285.16:48:24.92#ibcon#enter sib2, iclass 17, count 0 2006.285.16:48:24.92#ibcon#flushed, iclass 17, count 0 2006.285.16:48:24.92#ibcon#about to write, iclass 17, count 0 2006.285.16:48:24.92#ibcon#wrote, iclass 17, count 0 2006.285.16:48:24.92#ibcon#about to read 3, iclass 17, count 0 2006.285.16:48:24.94#ibcon#read 3, iclass 17, count 0 2006.285.16:48:24.94#ibcon#about to read 4, iclass 17, count 0 2006.285.16:48:24.94#ibcon#read 4, iclass 17, count 0 2006.285.16:48:24.94#ibcon#about to read 5, iclass 17, count 0 2006.285.16:48:24.94#ibcon#read 5, iclass 17, count 0 2006.285.16:48:24.94#ibcon#about to read 6, iclass 17, count 0 2006.285.16:48:24.94#ibcon#read 6, iclass 17, count 0 2006.285.16:48:24.94#ibcon#end of sib2, iclass 17, count 0 2006.285.16:48:24.94#ibcon#*mode == 0, iclass 17, count 0 2006.285.16:48:24.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.16:48:24.94#ibcon#[25=BW32\r\n] 2006.285.16:48:24.94#ibcon#*before write, iclass 17, count 0 2006.285.16:48:24.94#ibcon#enter sib2, iclass 17, count 0 2006.285.16:48:24.94#ibcon#flushed, iclass 17, count 0 2006.285.16:48:24.94#ibcon#about to write, iclass 17, count 0 2006.285.16:48:24.94#ibcon#wrote, iclass 17, count 0 2006.285.16:48:24.94#ibcon#about to read 3, iclass 17, count 0 2006.285.16:48:24.97#ibcon#read 3, iclass 17, count 0 2006.285.16:48:24.97#ibcon#about to read 4, iclass 17, count 0 2006.285.16:48:24.97#ibcon#read 4, iclass 17, count 0 2006.285.16:48:24.97#ibcon#about to read 5, iclass 17, count 0 2006.285.16:48:24.97#ibcon#read 5, iclass 17, count 0 2006.285.16:48:24.97#ibcon#about to read 6, iclass 17, count 0 2006.285.16:48:24.97#ibcon#read 6, iclass 17, count 0 2006.285.16:48:24.97#ibcon#end of sib2, iclass 17, count 0 2006.285.16:48:24.97#ibcon#*after write, iclass 17, count 0 2006.285.16:48:24.97#ibcon#*before return 0, iclass 17, count 0 2006.285.16:48:24.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:48:24.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:48:24.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.16:48:24.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.16:48:24.97$vck44/vbbw=wide 2006.285.16:48:24.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.16:48:24.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.16:48:24.97#ibcon#ireg 8 cls_cnt 0 2006.285.16:48:24.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:48:25.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:48:25.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:48:25.04#ibcon#enter wrdev, iclass 19, count 0 2006.285.16:48:25.04#ibcon#first serial, iclass 19, count 0 2006.285.16:48:25.04#ibcon#enter sib2, iclass 19, count 0 2006.285.16:48:25.04#ibcon#flushed, iclass 19, count 0 2006.285.16:48:25.04#ibcon#about to write, iclass 19, count 0 2006.285.16:48:25.04#ibcon#wrote, iclass 19, count 0 2006.285.16:48:25.04#ibcon#about to read 3, iclass 19, count 0 2006.285.16:48:25.06#ibcon#read 3, iclass 19, count 0 2006.285.16:48:25.06#ibcon#about to read 4, iclass 19, count 0 2006.285.16:48:25.06#ibcon#read 4, iclass 19, count 0 2006.285.16:48:25.06#ibcon#about to read 5, iclass 19, count 0 2006.285.16:48:25.06#ibcon#read 5, iclass 19, count 0 2006.285.16:48:25.06#ibcon#about to read 6, iclass 19, count 0 2006.285.16:48:25.06#ibcon#read 6, iclass 19, count 0 2006.285.16:48:25.06#ibcon#end of sib2, iclass 19, count 0 2006.285.16:48:25.06#ibcon#*mode == 0, iclass 19, count 0 2006.285.16:48:25.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.16:48:25.06#ibcon#[27=BW32\r\n] 2006.285.16:48:25.06#ibcon#*before write, iclass 19, count 0 2006.285.16:48:25.06#ibcon#enter sib2, iclass 19, count 0 2006.285.16:48:25.06#ibcon#flushed, iclass 19, count 0 2006.285.16:48:25.06#ibcon#about to write, iclass 19, count 0 2006.285.16:48:25.06#ibcon#wrote, iclass 19, count 0 2006.285.16:48:25.06#ibcon#about to read 3, iclass 19, count 0 2006.285.16:48:25.09#ibcon#read 3, iclass 19, count 0 2006.285.16:48:25.09#ibcon#about to read 4, iclass 19, count 0 2006.285.16:48:25.09#ibcon#read 4, iclass 19, count 0 2006.285.16:48:25.09#ibcon#about to read 5, iclass 19, count 0 2006.285.16:48:25.09#ibcon#read 5, iclass 19, count 0 2006.285.16:48:25.09#ibcon#about to read 6, iclass 19, count 0 2006.285.16:48:25.09#ibcon#read 6, iclass 19, count 0 2006.285.16:48:25.09#ibcon#end of sib2, iclass 19, count 0 2006.285.16:48:25.09#ibcon#*after write, iclass 19, count 0 2006.285.16:48:25.09#ibcon#*before return 0, iclass 19, count 0 2006.285.16:48:25.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:48:25.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:48:25.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.16:48:25.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.16:48:25.09$setupk4/ifdk4 2006.285.16:48:25.09$ifdk4/lo= 2006.285.16:48:25.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.16:48:25.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.16:48:25.20$ifdk4/patch= 2006.285.16:48:25.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.16:48:25.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.16:48:25.20$setupk4/!*+20s 2006.285.16:48:27.12#abcon#<5=/13 0.8 1.8 18.17 941014.9\r\n> 2006.285.16:48:27.14#abcon#{5=INTERFACE CLEAR} 2006.285.16:48:27.20#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:48:37.29#abcon#<5=/13 0.8 1.8 18.17 941014.9\r\n> 2006.285.16:48:37.31#abcon#{5=INTERFACE CLEAR} 2006.285.16:48:37.37#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:48:38.14#trakl#Source acquired 2006.285.16:48:38.37$setupk4/"tpicd 2006.285.16:48:38.37$setupk4/echo=off 2006.285.16:48:38.37$setupk4/xlog=off 2006.285.16:48:38.37:!2006.285.16:51:43 2006.285.16:48:39.14#flagr#flagr/antenna,acquired 2006.285.16:51:43.00:preob 2006.285.16:51:43.14/onsource/TRACKING 2006.285.16:51:43.14:!2006.285.16:51:53 2006.285.16:51:53.00:"tape 2006.285.16:51:53.00:"st=record 2006.285.16:51:53.00:data_valid=on 2006.285.16:51:53.00:midob 2006.285.16:51:54.14/onsource/TRACKING 2006.285.16:51:54.14/wx/18.09,1014.9,94 2006.285.16:51:54.30/cable/+6.5025E-03 2006.285.16:51:55.39/va/01,07,usb,yes,31,34 2006.285.16:51:55.39/va/02,06,usb,yes,32,32 2006.285.16:51:55.39/va/03,07,usb,yes,31,33 2006.285.16:51:55.39/va/04,06,usb,yes,33,34 2006.285.16:51:55.39/va/05,03,usb,yes,32,32 2006.285.16:51:55.39/va/06,04,usb,yes,29,28 2006.285.16:51:55.39/va/07,04,usb,yes,29,30 2006.285.16:51:55.39/va/08,03,usb,yes,30,37 2006.285.16:51:55.62/valo/01,524.99,yes,locked 2006.285.16:51:55.62/valo/02,534.99,yes,locked 2006.285.16:51:55.62/valo/03,564.99,yes,locked 2006.285.16:51:55.62/valo/04,624.99,yes,locked 2006.285.16:51:55.62/valo/05,734.99,yes,locked 2006.285.16:51:55.62/valo/06,814.99,yes,locked 2006.285.16:51:55.62/valo/07,864.99,yes,locked 2006.285.16:51:55.62/valo/08,884.99,yes,locked 2006.285.16:51:56.71/vb/01,04,usb,yes,30,28 2006.285.16:51:56.71/vb/02,05,usb,yes,28,28 2006.285.16:51:56.71/vb/03,04,usb,yes,29,32 2006.285.16:51:56.71/vb/04,05,usb,yes,30,29 2006.285.16:51:56.71/vb/05,04,usb,yes,26,29 2006.285.16:51:56.71/vb/06,03,usb,yes,38,33 2006.285.16:51:56.71/vb/07,04,usb,yes,30,30 2006.285.16:51:56.71/vb/08,04,usb,yes,28,31 2006.285.16:51:56.94/vblo/01,629.99,yes,locked 2006.285.16:51:56.94/vblo/02,634.99,yes,locked 2006.285.16:51:56.94/vblo/03,649.99,yes,locked 2006.285.16:51:56.94/vblo/04,679.99,yes,locked 2006.285.16:51:56.94/vblo/05,709.99,yes,locked 2006.285.16:51:56.94/vblo/06,719.99,yes,locked 2006.285.16:51:56.94/vblo/07,734.99,yes,locked 2006.285.16:51:56.94/vblo/08,744.99,yes,locked 2006.285.16:51:57.09/vabw/8 2006.285.16:51:57.24/vbbw/8 2006.285.16:51:57.33/xfe/off,on,12.2 2006.285.16:51:57.70/ifatt/23,28,28,28 2006.285.16:51:58.08/fmout-gps/S +2.70E-07 2006.285.16:51:58.10:!2006.285.16:53:43 2006.285.16:53:43.01:data_valid=off 2006.285.16:53:43.01:"et 2006.285.16:53:43.01:!+3s 2006.285.16:53:46.02:"tape 2006.285.16:53:46.02:postob 2006.285.16:53:46.18/cable/+6.5023E-03 2006.285.16:53:46.18/wx/18.02,1014.9,94 2006.285.16:53:47.08/fmout-gps/S +2.71E-07 2006.285.16:53:47.08:scan_name=285-1656,jd0610,40 2006.285.16:53:47.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.285.16:53:48.13#flagr#flagr/antenna,new-source 2006.285.16:53:48.13:checkk5 2006.285.16:53:48.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.16:53:48.96/chk_autoobs//k5ts2/ autoobs is running! 2006.285.16:53:49.43/chk_autoobs//k5ts3/ autoobs is running! 2006.285.16:53:49.80/chk_autoobs//k5ts4/ autoobs is running! 2006.285.16:53:50.16/chk_obsdata//k5ts1/T2851651??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.16:53:50.91/chk_obsdata//k5ts2/T2851651??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.16:53:51.28/chk_obsdata//k5ts3/T2851651??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.16:53:51.66/chk_obsdata//k5ts4/T2851651??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.16:53:52.53/k5log//k5ts1_log_newline 2006.285.16:53:53.64/k5log//k5ts2_log_newline 2006.285.16:53:54.45/k5log//k5ts3_log_newline 2006.285.16:53:55.37/k5log//k5ts4_log_newline 2006.285.16:53:55.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.16:53:55.39:setupk4=1 2006.285.16:53:55.39$setupk4/echo=on 2006.285.16:53:55.39$setupk4/pcalon 2006.285.16:53:55.39$pcalon/"no phase cal control is implemented here 2006.285.16:53:55.39$setupk4/"tpicd=stop 2006.285.16:53:55.39$setupk4/"rec=synch_on 2006.285.16:53:55.39$setupk4/"rec_mode=128 2006.285.16:53:55.39$setupk4/!* 2006.285.16:53:55.39$setupk4/recpk4 2006.285.16:53:55.39$recpk4/recpatch= 2006.285.16:53:55.39$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.16:53:55.39$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.16:53:55.39$setupk4/vck44 2006.285.16:53:55.39$vck44/valo=1,524.99 2006.285.16:53:55.40#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.16:53:55.40#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.16:53:55.40#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:55.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:53:55.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:53:55.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:53:55.40#ibcon#enter wrdev, iclass 12, count 0 2006.285.16:53:55.40#ibcon#first serial, iclass 12, count 0 2006.285.16:53:55.40#ibcon#enter sib2, iclass 12, count 0 2006.285.16:53:55.40#ibcon#flushed, iclass 12, count 0 2006.285.16:53:55.40#ibcon#about to write, iclass 12, count 0 2006.285.16:53:55.40#ibcon#wrote, iclass 12, count 0 2006.285.16:53:55.40#ibcon#about to read 3, iclass 12, count 0 2006.285.16:53:55.41#ibcon#read 3, iclass 12, count 0 2006.285.16:53:55.41#ibcon#about to read 4, iclass 12, count 0 2006.285.16:53:55.41#ibcon#read 4, iclass 12, count 0 2006.285.16:53:55.41#ibcon#about to read 5, iclass 12, count 0 2006.285.16:53:55.41#ibcon#read 5, iclass 12, count 0 2006.285.16:53:55.41#ibcon#about to read 6, iclass 12, count 0 2006.285.16:53:55.41#ibcon#read 6, iclass 12, count 0 2006.285.16:53:55.41#ibcon#end of sib2, iclass 12, count 0 2006.285.16:53:55.41#ibcon#*mode == 0, iclass 12, count 0 2006.285.16:53:55.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.16:53:55.41#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.16:53:55.41#ibcon#*before write, iclass 12, count 0 2006.285.16:53:55.41#ibcon#enter sib2, iclass 12, count 0 2006.285.16:53:55.41#ibcon#flushed, iclass 12, count 0 2006.285.16:53:55.41#ibcon#about to write, iclass 12, count 0 2006.285.16:53:55.41#ibcon#wrote, iclass 12, count 0 2006.285.16:53:55.41#ibcon#about to read 3, iclass 12, count 0 2006.285.16:53:55.46#ibcon#read 3, iclass 12, count 0 2006.285.16:53:55.46#ibcon#about to read 4, iclass 12, count 0 2006.285.16:53:55.46#ibcon#read 4, iclass 12, count 0 2006.285.16:53:55.46#ibcon#about to read 5, iclass 12, count 0 2006.285.16:53:55.46#ibcon#read 5, iclass 12, count 0 2006.285.16:53:55.46#ibcon#about to read 6, iclass 12, count 0 2006.285.16:53:55.46#ibcon#read 6, iclass 12, count 0 2006.285.16:53:55.46#ibcon#end of sib2, iclass 12, count 0 2006.285.16:53:55.46#ibcon#*after write, iclass 12, count 0 2006.285.16:53:55.46#ibcon#*before return 0, iclass 12, count 0 2006.285.16:53:55.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:53:55.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:53:55.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.16:53:55.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.16:53:55.46$vck44/va=1,7 2006.285.16:53:55.46#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.16:53:55.46#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.16:53:55.46#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:55.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:53:55.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:53:55.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:53:55.46#ibcon#enter wrdev, iclass 14, count 2 2006.285.16:53:55.46#ibcon#first serial, iclass 14, count 2 2006.285.16:53:55.46#ibcon#enter sib2, iclass 14, count 2 2006.285.16:53:55.46#ibcon#flushed, iclass 14, count 2 2006.285.16:53:55.46#ibcon#about to write, iclass 14, count 2 2006.285.16:53:55.46#ibcon#wrote, iclass 14, count 2 2006.285.16:53:55.46#ibcon#about to read 3, iclass 14, count 2 2006.285.16:53:55.48#ibcon#read 3, iclass 14, count 2 2006.285.16:53:55.48#ibcon#about to read 4, iclass 14, count 2 2006.285.16:53:55.48#ibcon#read 4, iclass 14, count 2 2006.285.16:53:55.48#ibcon#about to read 5, iclass 14, count 2 2006.285.16:53:55.48#ibcon#read 5, iclass 14, count 2 2006.285.16:53:55.48#ibcon#about to read 6, iclass 14, count 2 2006.285.16:53:55.48#ibcon#read 6, iclass 14, count 2 2006.285.16:53:55.48#ibcon#end of sib2, iclass 14, count 2 2006.285.16:53:55.48#ibcon#*mode == 0, iclass 14, count 2 2006.285.16:53:55.48#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.16:53:55.48#ibcon#[25=AT01-07\r\n] 2006.285.16:53:55.48#ibcon#*before write, iclass 14, count 2 2006.285.16:53:55.48#ibcon#enter sib2, iclass 14, count 2 2006.285.16:53:55.48#ibcon#flushed, iclass 14, count 2 2006.285.16:53:55.48#ibcon#about to write, iclass 14, count 2 2006.285.16:53:55.48#ibcon#wrote, iclass 14, count 2 2006.285.16:53:55.48#ibcon#about to read 3, iclass 14, count 2 2006.285.16:53:55.51#ibcon#read 3, iclass 14, count 2 2006.285.16:53:55.51#ibcon#about to read 4, iclass 14, count 2 2006.285.16:53:55.51#ibcon#read 4, iclass 14, count 2 2006.285.16:53:55.51#ibcon#about to read 5, iclass 14, count 2 2006.285.16:53:55.51#ibcon#read 5, iclass 14, count 2 2006.285.16:53:55.51#ibcon#about to read 6, iclass 14, count 2 2006.285.16:53:55.51#ibcon#read 6, iclass 14, count 2 2006.285.16:53:55.51#ibcon#end of sib2, iclass 14, count 2 2006.285.16:53:55.51#ibcon#*after write, iclass 14, count 2 2006.285.16:53:55.51#ibcon#*before return 0, iclass 14, count 2 2006.285.16:53:55.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:53:55.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:53:55.51#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.16:53:55.51#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:55.51#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:53:55.63#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:53:55.63#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:53:55.63#ibcon#enter wrdev, iclass 14, count 0 2006.285.16:53:55.63#ibcon#first serial, iclass 14, count 0 2006.285.16:53:55.63#ibcon#enter sib2, iclass 14, count 0 2006.285.16:53:55.63#ibcon#flushed, iclass 14, count 0 2006.285.16:53:55.63#ibcon#about to write, iclass 14, count 0 2006.285.16:53:55.63#ibcon#wrote, iclass 14, count 0 2006.285.16:53:55.63#ibcon#about to read 3, iclass 14, count 0 2006.285.16:53:55.65#ibcon#read 3, iclass 14, count 0 2006.285.16:53:55.65#ibcon#about to read 4, iclass 14, count 0 2006.285.16:53:55.65#ibcon#read 4, iclass 14, count 0 2006.285.16:53:55.65#ibcon#about to read 5, iclass 14, count 0 2006.285.16:53:55.65#ibcon#read 5, iclass 14, count 0 2006.285.16:53:55.65#ibcon#about to read 6, iclass 14, count 0 2006.285.16:53:55.65#ibcon#read 6, iclass 14, count 0 2006.285.16:53:55.65#ibcon#end of sib2, iclass 14, count 0 2006.285.16:53:55.65#ibcon#*mode == 0, iclass 14, count 0 2006.285.16:53:55.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.16:53:55.65#ibcon#[25=USB\r\n] 2006.285.16:53:55.65#ibcon#*before write, iclass 14, count 0 2006.285.16:53:55.65#ibcon#enter sib2, iclass 14, count 0 2006.285.16:53:55.65#ibcon#flushed, iclass 14, count 0 2006.285.16:53:55.65#ibcon#about to write, iclass 14, count 0 2006.285.16:53:55.65#ibcon#wrote, iclass 14, count 0 2006.285.16:53:55.65#ibcon#about to read 3, iclass 14, count 0 2006.285.16:53:55.68#ibcon#read 3, iclass 14, count 0 2006.285.16:53:55.68#ibcon#about to read 4, iclass 14, count 0 2006.285.16:53:55.68#ibcon#read 4, iclass 14, count 0 2006.285.16:53:55.68#ibcon#about to read 5, iclass 14, count 0 2006.285.16:53:55.68#ibcon#read 5, iclass 14, count 0 2006.285.16:53:55.68#ibcon#about to read 6, iclass 14, count 0 2006.285.16:53:55.68#ibcon#read 6, iclass 14, count 0 2006.285.16:53:55.68#ibcon#end of sib2, iclass 14, count 0 2006.285.16:53:55.68#ibcon#*after write, iclass 14, count 0 2006.285.16:53:55.68#ibcon#*before return 0, iclass 14, count 0 2006.285.16:53:55.68#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:53:55.68#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:53:55.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.16:53:55.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.16:53:55.68$vck44/valo=2,534.99 2006.285.16:53:55.68#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.16:53:55.68#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.16:53:55.68#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:55.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:53:55.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:53:55.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:53:55.68#ibcon#enter wrdev, iclass 16, count 0 2006.285.16:53:55.68#ibcon#first serial, iclass 16, count 0 2006.285.16:53:55.68#ibcon#enter sib2, iclass 16, count 0 2006.285.16:53:55.68#ibcon#flushed, iclass 16, count 0 2006.285.16:53:55.68#ibcon#about to write, iclass 16, count 0 2006.285.16:53:55.68#ibcon#wrote, iclass 16, count 0 2006.285.16:53:55.68#ibcon#about to read 3, iclass 16, count 0 2006.285.16:53:55.70#ibcon#read 3, iclass 16, count 0 2006.285.16:53:55.70#ibcon#about to read 4, iclass 16, count 0 2006.285.16:53:55.70#ibcon#read 4, iclass 16, count 0 2006.285.16:53:55.70#ibcon#about to read 5, iclass 16, count 0 2006.285.16:53:55.70#ibcon#read 5, iclass 16, count 0 2006.285.16:53:55.70#ibcon#about to read 6, iclass 16, count 0 2006.285.16:53:55.70#ibcon#read 6, iclass 16, count 0 2006.285.16:53:55.70#ibcon#end of sib2, iclass 16, count 0 2006.285.16:53:55.70#ibcon#*mode == 0, iclass 16, count 0 2006.285.16:53:55.70#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.16:53:55.70#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.16:53:55.70#ibcon#*before write, iclass 16, count 0 2006.285.16:53:55.70#ibcon#enter sib2, iclass 16, count 0 2006.285.16:53:55.70#ibcon#flushed, iclass 16, count 0 2006.285.16:53:55.70#ibcon#about to write, iclass 16, count 0 2006.285.16:53:55.70#ibcon#wrote, iclass 16, count 0 2006.285.16:53:55.70#ibcon#about to read 3, iclass 16, count 0 2006.285.16:53:55.74#ibcon#read 3, iclass 16, count 0 2006.285.16:53:55.74#ibcon#about to read 4, iclass 16, count 0 2006.285.16:53:55.74#ibcon#read 4, iclass 16, count 0 2006.285.16:53:55.74#ibcon#about to read 5, iclass 16, count 0 2006.285.16:53:55.74#ibcon#read 5, iclass 16, count 0 2006.285.16:53:55.74#ibcon#about to read 6, iclass 16, count 0 2006.285.16:53:55.74#ibcon#read 6, iclass 16, count 0 2006.285.16:53:55.74#ibcon#end of sib2, iclass 16, count 0 2006.285.16:53:55.74#ibcon#*after write, iclass 16, count 0 2006.285.16:53:55.74#ibcon#*before return 0, iclass 16, count 0 2006.285.16:53:55.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:53:55.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:53:55.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.16:53:55.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.16:53:55.74$vck44/va=2,6 2006.285.16:53:55.74#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.16:53:55.74#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.16:53:55.74#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:55.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:53:55.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:53:55.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:53:55.80#ibcon#enter wrdev, iclass 18, count 2 2006.285.16:53:55.80#ibcon#first serial, iclass 18, count 2 2006.285.16:53:55.80#ibcon#enter sib2, iclass 18, count 2 2006.285.16:53:55.80#ibcon#flushed, iclass 18, count 2 2006.285.16:53:55.80#ibcon#about to write, iclass 18, count 2 2006.285.16:53:55.80#ibcon#wrote, iclass 18, count 2 2006.285.16:53:55.80#ibcon#about to read 3, iclass 18, count 2 2006.285.16:53:55.82#ibcon#read 3, iclass 18, count 2 2006.285.16:53:55.82#ibcon#about to read 4, iclass 18, count 2 2006.285.16:53:55.82#ibcon#read 4, iclass 18, count 2 2006.285.16:53:55.82#ibcon#about to read 5, iclass 18, count 2 2006.285.16:53:55.82#ibcon#read 5, iclass 18, count 2 2006.285.16:53:55.82#ibcon#about to read 6, iclass 18, count 2 2006.285.16:53:55.82#ibcon#read 6, iclass 18, count 2 2006.285.16:53:55.82#ibcon#end of sib2, iclass 18, count 2 2006.285.16:53:55.82#ibcon#*mode == 0, iclass 18, count 2 2006.285.16:53:55.82#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.16:53:55.82#ibcon#[25=AT02-06\r\n] 2006.285.16:53:55.82#ibcon#*before write, iclass 18, count 2 2006.285.16:53:55.82#ibcon#enter sib2, iclass 18, count 2 2006.285.16:53:55.82#ibcon#flushed, iclass 18, count 2 2006.285.16:53:55.82#ibcon#about to write, iclass 18, count 2 2006.285.16:53:55.82#ibcon#wrote, iclass 18, count 2 2006.285.16:53:55.82#ibcon#about to read 3, iclass 18, count 2 2006.285.16:53:55.85#ibcon#read 3, iclass 18, count 2 2006.285.16:53:55.85#ibcon#about to read 4, iclass 18, count 2 2006.285.16:53:55.85#ibcon#read 4, iclass 18, count 2 2006.285.16:53:55.85#ibcon#about to read 5, iclass 18, count 2 2006.285.16:53:55.85#ibcon#read 5, iclass 18, count 2 2006.285.16:53:55.85#ibcon#about to read 6, iclass 18, count 2 2006.285.16:53:55.85#ibcon#read 6, iclass 18, count 2 2006.285.16:53:55.85#ibcon#end of sib2, iclass 18, count 2 2006.285.16:53:55.85#ibcon#*after write, iclass 18, count 2 2006.285.16:53:55.85#ibcon#*before return 0, iclass 18, count 2 2006.285.16:53:55.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:53:55.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:53:55.85#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.16:53:55.85#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:55.85#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:53:55.97#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:53:55.97#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:53:55.97#ibcon#enter wrdev, iclass 18, count 0 2006.285.16:53:55.97#ibcon#first serial, iclass 18, count 0 2006.285.16:53:55.97#ibcon#enter sib2, iclass 18, count 0 2006.285.16:53:55.97#ibcon#flushed, iclass 18, count 0 2006.285.16:53:55.97#ibcon#about to write, iclass 18, count 0 2006.285.16:53:55.97#ibcon#wrote, iclass 18, count 0 2006.285.16:53:55.97#ibcon#about to read 3, iclass 18, count 0 2006.285.16:53:55.99#ibcon#read 3, iclass 18, count 0 2006.285.16:53:55.99#ibcon#about to read 4, iclass 18, count 0 2006.285.16:53:55.99#ibcon#read 4, iclass 18, count 0 2006.285.16:53:55.99#ibcon#about to read 5, iclass 18, count 0 2006.285.16:53:55.99#ibcon#read 5, iclass 18, count 0 2006.285.16:53:55.99#ibcon#about to read 6, iclass 18, count 0 2006.285.16:53:55.99#ibcon#read 6, iclass 18, count 0 2006.285.16:53:55.99#ibcon#end of sib2, iclass 18, count 0 2006.285.16:53:55.99#ibcon#*mode == 0, iclass 18, count 0 2006.285.16:53:55.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.16:53:55.99#ibcon#[25=USB\r\n] 2006.285.16:53:55.99#ibcon#*before write, iclass 18, count 0 2006.285.16:53:55.99#ibcon#enter sib2, iclass 18, count 0 2006.285.16:53:55.99#ibcon#flushed, iclass 18, count 0 2006.285.16:53:55.99#ibcon#about to write, iclass 18, count 0 2006.285.16:53:55.99#ibcon#wrote, iclass 18, count 0 2006.285.16:53:55.99#ibcon#about to read 3, iclass 18, count 0 2006.285.16:53:56.02#ibcon#read 3, iclass 18, count 0 2006.285.16:53:56.02#ibcon#about to read 4, iclass 18, count 0 2006.285.16:53:56.02#ibcon#read 4, iclass 18, count 0 2006.285.16:53:56.02#ibcon#about to read 5, iclass 18, count 0 2006.285.16:53:56.02#ibcon#read 5, iclass 18, count 0 2006.285.16:53:56.02#ibcon#about to read 6, iclass 18, count 0 2006.285.16:53:56.02#ibcon#read 6, iclass 18, count 0 2006.285.16:53:56.02#ibcon#end of sib2, iclass 18, count 0 2006.285.16:53:56.02#ibcon#*after write, iclass 18, count 0 2006.285.16:53:56.02#ibcon#*before return 0, iclass 18, count 0 2006.285.16:53:56.02#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:53:56.02#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:53:56.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.16:53:56.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.16:53:56.02$vck44/valo=3,564.99 2006.285.16:53:56.02#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.16:53:56.02#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.16:53:56.02#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:56.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:53:56.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:53:56.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:53:56.02#ibcon#enter wrdev, iclass 20, count 0 2006.285.16:53:56.02#ibcon#first serial, iclass 20, count 0 2006.285.16:53:56.02#ibcon#enter sib2, iclass 20, count 0 2006.285.16:53:56.02#ibcon#flushed, iclass 20, count 0 2006.285.16:53:56.02#ibcon#about to write, iclass 20, count 0 2006.285.16:53:56.02#ibcon#wrote, iclass 20, count 0 2006.285.16:53:56.02#ibcon#about to read 3, iclass 20, count 0 2006.285.16:53:56.04#ibcon#read 3, iclass 20, count 0 2006.285.16:53:56.04#ibcon#about to read 4, iclass 20, count 0 2006.285.16:53:56.04#ibcon#read 4, iclass 20, count 0 2006.285.16:53:56.04#ibcon#about to read 5, iclass 20, count 0 2006.285.16:53:56.04#ibcon#read 5, iclass 20, count 0 2006.285.16:53:56.04#ibcon#about to read 6, iclass 20, count 0 2006.285.16:53:56.04#ibcon#read 6, iclass 20, count 0 2006.285.16:53:56.04#ibcon#end of sib2, iclass 20, count 0 2006.285.16:53:56.04#ibcon#*mode == 0, iclass 20, count 0 2006.285.16:53:56.04#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.16:53:56.04#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.16:53:56.04#ibcon#*before write, iclass 20, count 0 2006.285.16:53:56.04#ibcon#enter sib2, iclass 20, count 0 2006.285.16:53:56.04#ibcon#flushed, iclass 20, count 0 2006.285.16:53:56.04#ibcon#about to write, iclass 20, count 0 2006.285.16:53:56.04#ibcon#wrote, iclass 20, count 0 2006.285.16:53:56.04#ibcon#about to read 3, iclass 20, count 0 2006.285.16:53:56.08#ibcon#read 3, iclass 20, count 0 2006.285.16:53:56.08#ibcon#about to read 4, iclass 20, count 0 2006.285.16:53:56.08#ibcon#read 4, iclass 20, count 0 2006.285.16:53:56.08#ibcon#about to read 5, iclass 20, count 0 2006.285.16:53:56.08#ibcon#read 5, iclass 20, count 0 2006.285.16:53:56.08#ibcon#about to read 6, iclass 20, count 0 2006.285.16:53:56.08#ibcon#read 6, iclass 20, count 0 2006.285.16:53:56.08#ibcon#end of sib2, iclass 20, count 0 2006.285.16:53:56.08#ibcon#*after write, iclass 20, count 0 2006.285.16:53:56.08#ibcon#*before return 0, iclass 20, count 0 2006.285.16:53:56.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:53:56.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:53:56.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.16:53:56.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.16:53:56.08$vck44/va=3,7 2006.285.16:53:56.08#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.16:53:56.08#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.16:53:56.08#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:56.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:53:56.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:53:56.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:53:56.14#ibcon#enter wrdev, iclass 22, count 2 2006.285.16:53:56.14#ibcon#first serial, iclass 22, count 2 2006.285.16:53:56.14#ibcon#enter sib2, iclass 22, count 2 2006.285.16:53:56.14#ibcon#flushed, iclass 22, count 2 2006.285.16:53:56.14#ibcon#about to write, iclass 22, count 2 2006.285.16:53:56.14#ibcon#wrote, iclass 22, count 2 2006.285.16:53:56.14#ibcon#about to read 3, iclass 22, count 2 2006.285.16:53:56.16#ibcon#read 3, iclass 22, count 2 2006.285.16:53:56.16#ibcon#about to read 4, iclass 22, count 2 2006.285.16:53:56.16#ibcon#read 4, iclass 22, count 2 2006.285.16:53:56.16#ibcon#about to read 5, iclass 22, count 2 2006.285.16:53:56.16#ibcon#read 5, iclass 22, count 2 2006.285.16:53:56.16#ibcon#about to read 6, iclass 22, count 2 2006.285.16:53:56.16#ibcon#read 6, iclass 22, count 2 2006.285.16:53:56.16#ibcon#end of sib2, iclass 22, count 2 2006.285.16:53:56.16#ibcon#*mode == 0, iclass 22, count 2 2006.285.16:53:56.16#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.16:53:56.16#ibcon#[25=AT03-07\r\n] 2006.285.16:53:56.16#ibcon#*before write, iclass 22, count 2 2006.285.16:53:56.16#ibcon#enter sib2, iclass 22, count 2 2006.285.16:53:56.16#ibcon#flushed, iclass 22, count 2 2006.285.16:53:56.16#ibcon#about to write, iclass 22, count 2 2006.285.16:53:56.16#ibcon#wrote, iclass 22, count 2 2006.285.16:53:56.16#ibcon#about to read 3, iclass 22, count 2 2006.285.16:53:56.19#ibcon#read 3, iclass 22, count 2 2006.285.16:53:56.19#ibcon#about to read 4, iclass 22, count 2 2006.285.16:53:56.19#ibcon#read 4, iclass 22, count 2 2006.285.16:53:56.19#ibcon#about to read 5, iclass 22, count 2 2006.285.16:53:56.19#ibcon#read 5, iclass 22, count 2 2006.285.16:53:56.19#ibcon#about to read 6, iclass 22, count 2 2006.285.16:53:56.19#ibcon#read 6, iclass 22, count 2 2006.285.16:53:56.19#ibcon#end of sib2, iclass 22, count 2 2006.285.16:53:56.19#ibcon#*after write, iclass 22, count 2 2006.285.16:53:56.19#ibcon#*before return 0, iclass 22, count 2 2006.285.16:53:56.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:53:56.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:53:56.19#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.16:53:56.19#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:56.19#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:53:56.31#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:53:56.31#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:53:56.31#ibcon#enter wrdev, iclass 22, count 0 2006.285.16:53:56.31#ibcon#first serial, iclass 22, count 0 2006.285.16:53:56.31#ibcon#enter sib2, iclass 22, count 0 2006.285.16:53:56.31#ibcon#flushed, iclass 22, count 0 2006.285.16:53:56.31#ibcon#about to write, iclass 22, count 0 2006.285.16:53:56.31#ibcon#wrote, iclass 22, count 0 2006.285.16:53:56.31#ibcon#about to read 3, iclass 22, count 0 2006.285.16:53:56.33#ibcon#read 3, iclass 22, count 0 2006.285.16:53:56.33#ibcon#about to read 4, iclass 22, count 0 2006.285.16:53:56.33#ibcon#read 4, iclass 22, count 0 2006.285.16:53:56.33#ibcon#about to read 5, iclass 22, count 0 2006.285.16:53:56.33#ibcon#read 5, iclass 22, count 0 2006.285.16:53:56.33#ibcon#about to read 6, iclass 22, count 0 2006.285.16:53:56.33#ibcon#read 6, iclass 22, count 0 2006.285.16:53:56.33#ibcon#end of sib2, iclass 22, count 0 2006.285.16:53:56.33#ibcon#*mode == 0, iclass 22, count 0 2006.285.16:53:56.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.16:53:56.33#ibcon#[25=USB\r\n] 2006.285.16:53:56.33#ibcon#*before write, iclass 22, count 0 2006.285.16:53:56.33#ibcon#enter sib2, iclass 22, count 0 2006.285.16:53:56.33#ibcon#flushed, iclass 22, count 0 2006.285.16:53:56.33#ibcon#about to write, iclass 22, count 0 2006.285.16:53:56.33#ibcon#wrote, iclass 22, count 0 2006.285.16:53:56.33#ibcon#about to read 3, iclass 22, count 0 2006.285.16:53:56.36#ibcon#read 3, iclass 22, count 0 2006.285.16:53:56.36#ibcon#about to read 4, iclass 22, count 0 2006.285.16:53:56.36#ibcon#read 4, iclass 22, count 0 2006.285.16:53:56.36#ibcon#about to read 5, iclass 22, count 0 2006.285.16:53:56.36#ibcon#read 5, iclass 22, count 0 2006.285.16:53:56.36#ibcon#about to read 6, iclass 22, count 0 2006.285.16:53:56.36#ibcon#read 6, iclass 22, count 0 2006.285.16:53:56.36#ibcon#end of sib2, iclass 22, count 0 2006.285.16:53:56.36#ibcon#*after write, iclass 22, count 0 2006.285.16:53:56.36#ibcon#*before return 0, iclass 22, count 0 2006.285.16:53:56.36#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:53:56.36#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:53:56.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.16:53:56.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.16:53:56.36$vck44/valo=4,624.99 2006.285.16:53:56.36#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.16:53:56.36#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.16:53:56.36#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:56.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:53:56.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:53:56.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:53:56.36#ibcon#enter wrdev, iclass 24, count 0 2006.285.16:53:56.36#ibcon#first serial, iclass 24, count 0 2006.285.16:53:56.36#ibcon#enter sib2, iclass 24, count 0 2006.285.16:53:56.36#ibcon#flushed, iclass 24, count 0 2006.285.16:53:56.36#ibcon#about to write, iclass 24, count 0 2006.285.16:53:56.36#ibcon#wrote, iclass 24, count 0 2006.285.16:53:56.36#ibcon#about to read 3, iclass 24, count 0 2006.285.16:53:56.38#ibcon#read 3, iclass 24, count 0 2006.285.16:53:56.85#ibcon#about to read 4, iclass 24, count 0 2006.285.16:53:56.85#ibcon#read 4, iclass 24, count 0 2006.285.16:53:56.85#ibcon#about to read 5, iclass 24, count 0 2006.285.16:53:56.85#ibcon#read 5, iclass 24, count 0 2006.285.16:53:56.85#ibcon#about to read 6, iclass 24, count 0 2006.285.16:53:56.85#ibcon#read 6, iclass 24, count 0 2006.285.16:53:56.85#ibcon#end of sib2, iclass 24, count 0 2006.285.16:53:56.85#ibcon#*mode == 0, iclass 24, count 0 2006.285.16:53:56.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.16:53:56.85#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.16:53:56.85#ibcon#*before write, iclass 24, count 0 2006.285.16:53:56.85#ibcon#enter sib2, iclass 24, count 0 2006.285.16:53:56.85#ibcon#flushed, iclass 24, count 0 2006.285.16:53:56.85#ibcon#about to write, iclass 24, count 0 2006.285.16:53:56.85#ibcon#wrote, iclass 24, count 0 2006.285.16:53:56.85#ibcon#about to read 3, iclass 24, count 0 2006.285.16:53:56.89#ibcon#read 3, iclass 24, count 0 2006.285.16:53:56.89#ibcon#about to read 4, iclass 24, count 0 2006.285.16:53:56.89#ibcon#read 4, iclass 24, count 0 2006.285.16:53:56.89#ibcon#about to read 5, iclass 24, count 0 2006.285.16:53:56.89#ibcon#read 5, iclass 24, count 0 2006.285.16:53:56.89#ibcon#about to read 6, iclass 24, count 0 2006.285.16:53:56.89#ibcon#read 6, iclass 24, count 0 2006.285.16:53:56.89#ibcon#end of sib2, iclass 24, count 0 2006.285.16:53:56.89#ibcon#*after write, iclass 24, count 0 2006.285.16:53:56.89#ibcon#*before return 0, iclass 24, count 0 2006.285.16:53:56.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:53:56.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:53:56.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.16:53:56.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.16:53:56.89$vck44/va=4,6 2006.285.16:53:56.89#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.16:53:56.89#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.16:53:56.89#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:56.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:53:56.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:53:56.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:53:56.89#ibcon#enter wrdev, iclass 26, count 2 2006.285.16:53:56.89#ibcon#first serial, iclass 26, count 2 2006.285.16:53:56.89#ibcon#enter sib2, iclass 26, count 2 2006.285.16:53:56.89#ibcon#flushed, iclass 26, count 2 2006.285.16:53:56.89#ibcon#about to write, iclass 26, count 2 2006.285.16:53:56.89#ibcon#wrote, iclass 26, count 2 2006.285.16:53:56.89#ibcon#about to read 3, iclass 26, count 2 2006.285.16:53:56.91#ibcon#read 3, iclass 26, count 2 2006.285.16:53:56.91#ibcon#about to read 4, iclass 26, count 2 2006.285.16:53:56.91#ibcon#read 4, iclass 26, count 2 2006.285.16:53:56.91#ibcon#about to read 5, iclass 26, count 2 2006.285.16:53:56.91#ibcon#read 5, iclass 26, count 2 2006.285.16:53:56.91#ibcon#about to read 6, iclass 26, count 2 2006.285.16:53:56.91#ibcon#read 6, iclass 26, count 2 2006.285.16:53:56.91#ibcon#end of sib2, iclass 26, count 2 2006.285.16:53:56.91#ibcon#*mode == 0, iclass 26, count 2 2006.285.16:53:56.91#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.16:53:56.91#ibcon#[25=AT04-06\r\n] 2006.285.16:53:56.91#ibcon#*before write, iclass 26, count 2 2006.285.16:53:56.91#ibcon#enter sib2, iclass 26, count 2 2006.285.16:53:56.91#ibcon#flushed, iclass 26, count 2 2006.285.16:53:56.91#ibcon#about to write, iclass 26, count 2 2006.285.16:53:56.91#ibcon#wrote, iclass 26, count 2 2006.285.16:53:56.91#ibcon#about to read 3, iclass 26, count 2 2006.285.16:53:56.94#ibcon#read 3, iclass 26, count 2 2006.285.16:53:56.94#ibcon#about to read 4, iclass 26, count 2 2006.285.16:53:56.94#ibcon#read 4, iclass 26, count 2 2006.285.16:53:56.94#ibcon#about to read 5, iclass 26, count 2 2006.285.16:53:56.94#ibcon#read 5, iclass 26, count 2 2006.285.16:53:56.94#ibcon#about to read 6, iclass 26, count 2 2006.285.16:53:56.94#ibcon#read 6, iclass 26, count 2 2006.285.16:53:56.94#ibcon#end of sib2, iclass 26, count 2 2006.285.16:53:56.94#ibcon#*after write, iclass 26, count 2 2006.285.16:53:56.94#ibcon#*before return 0, iclass 26, count 2 2006.285.16:53:56.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:53:56.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:53:56.94#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.16:53:56.94#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:56.94#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:53:57.06#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:53:57.06#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:53:57.06#ibcon#enter wrdev, iclass 26, count 0 2006.285.16:53:57.06#ibcon#first serial, iclass 26, count 0 2006.285.16:53:57.06#ibcon#enter sib2, iclass 26, count 0 2006.285.16:53:57.06#ibcon#flushed, iclass 26, count 0 2006.285.16:53:57.06#ibcon#about to write, iclass 26, count 0 2006.285.16:53:57.06#ibcon#wrote, iclass 26, count 0 2006.285.16:53:57.06#ibcon#about to read 3, iclass 26, count 0 2006.285.16:53:57.08#ibcon#read 3, iclass 26, count 0 2006.285.16:53:57.08#ibcon#about to read 4, iclass 26, count 0 2006.285.16:53:57.08#ibcon#read 4, iclass 26, count 0 2006.285.16:53:57.08#ibcon#about to read 5, iclass 26, count 0 2006.285.16:53:57.08#ibcon#read 5, iclass 26, count 0 2006.285.16:53:57.08#ibcon#about to read 6, iclass 26, count 0 2006.285.16:53:57.08#ibcon#read 6, iclass 26, count 0 2006.285.16:53:57.08#ibcon#end of sib2, iclass 26, count 0 2006.285.16:53:57.08#ibcon#*mode == 0, iclass 26, count 0 2006.285.16:53:57.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.16:53:57.08#ibcon#[25=USB\r\n] 2006.285.16:53:57.08#ibcon#*before write, iclass 26, count 0 2006.285.16:53:57.08#ibcon#enter sib2, iclass 26, count 0 2006.285.16:53:57.08#ibcon#flushed, iclass 26, count 0 2006.285.16:53:57.08#ibcon#about to write, iclass 26, count 0 2006.285.16:53:57.08#ibcon#wrote, iclass 26, count 0 2006.285.16:53:57.08#ibcon#about to read 3, iclass 26, count 0 2006.285.16:53:57.11#ibcon#read 3, iclass 26, count 0 2006.285.16:53:57.11#ibcon#about to read 4, iclass 26, count 0 2006.285.16:53:57.11#ibcon#read 4, iclass 26, count 0 2006.285.16:53:57.11#ibcon#about to read 5, iclass 26, count 0 2006.285.16:53:57.11#ibcon#read 5, iclass 26, count 0 2006.285.16:53:57.11#ibcon#about to read 6, iclass 26, count 0 2006.285.16:53:57.11#ibcon#read 6, iclass 26, count 0 2006.285.16:53:57.11#ibcon#end of sib2, iclass 26, count 0 2006.285.16:53:57.11#ibcon#*after write, iclass 26, count 0 2006.285.16:53:57.11#ibcon#*before return 0, iclass 26, count 0 2006.285.16:53:57.11#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:53:57.11#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:53:57.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.16:53:57.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.16:53:57.11$vck44/valo=5,734.99 2006.285.16:53:57.11#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.16:53:57.11#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.16:53:57.11#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:57.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:53:57.11#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:53:57.11#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:53:57.11#ibcon#enter wrdev, iclass 28, count 0 2006.285.16:53:57.11#ibcon#first serial, iclass 28, count 0 2006.285.16:53:57.11#ibcon#enter sib2, iclass 28, count 0 2006.285.16:53:57.11#ibcon#flushed, iclass 28, count 0 2006.285.16:53:57.11#ibcon#about to write, iclass 28, count 0 2006.285.16:53:57.11#ibcon#wrote, iclass 28, count 0 2006.285.16:53:57.11#ibcon#about to read 3, iclass 28, count 0 2006.285.16:53:57.13#ibcon#read 3, iclass 28, count 0 2006.285.16:53:57.13#ibcon#about to read 4, iclass 28, count 0 2006.285.16:53:57.13#ibcon#read 4, iclass 28, count 0 2006.285.16:53:57.13#ibcon#about to read 5, iclass 28, count 0 2006.285.16:53:57.13#ibcon#read 5, iclass 28, count 0 2006.285.16:53:57.13#ibcon#about to read 6, iclass 28, count 0 2006.285.16:53:57.13#ibcon#read 6, iclass 28, count 0 2006.285.16:53:57.13#ibcon#end of sib2, iclass 28, count 0 2006.285.16:53:57.13#ibcon#*mode == 0, iclass 28, count 0 2006.285.16:53:57.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.16:53:57.13#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.16:53:57.13#ibcon#*before write, iclass 28, count 0 2006.285.16:53:57.13#ibcon#enter sib2, iclass 28, count 0 2006.285.16:53:57.13#ibcon#flushed, iclass 28, count 0 2006.285.16:53:57.13#ibcon#about to write, iclass 28, count 0 2006.285.16:53:57.13#ibcon#wrote, iclass 28, count 0 2006.285.16:53:57.13#ibcon#about to read 3, iclass 28, count 0 2006.285.16:53:57.17#ibcon#read 3, iclass 28, count 0 2006.285.16:53:57.17#ibcon#about to read 4, iclass 28, count 0 2006.285.16:53:57.17#ibcon#read 4, iclass 28, count 0 2006.285.16:53:57.17#ibcon#about to read 5, iclass 28, count 0 2006.285.16:53:57.17#ibcon#read 5, iclass 28, count 0 2006.285.16:53:57.17#ibcon#about to read 6, iclass 28, count 0 2006.285.16:53:57.17#ibcon#read 6, iclass 28, count 0 2006.285.16:53:57.17#ibcon#end of sib2, iclass 28, count 0 2006.285.16:53:57.17#ibcon#*after write, iclass 28, count 0 2006.285.16:53:57.17#ibcon#*before return 0, iclass 28, count 0 2006.285.16:53:57.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:53:57.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:53:57.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.16:53:57.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.16:53:57.17$vck44/va=5,3 2006.285.16:53:57.17#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.16:53:57.17#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.16:53:57.17#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:57.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:53:57.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:53:57.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:53:57.23#ibcon#enter wrdev, iclass 30, count 2 2006.285.16:53:57.23#ibcon#first serial, iclass 30, count 2 2006.285.16:53:57.23#ibcon#enter sib2, iclass 30, count 2 2006.285.16:53:57.23#ibcon#flushed, iclass 30, count 2 2006.285.16:53:57.23#ibcon#about to write, iclass 30, count 2 2006.285.16:53:57.23#ibcon#wrote, iclass 30, count 2 2006.285.16:53:57.23#ibcon#about to read 3, iclass 30, count 2 2006.285.16:53:57.25#ibcon#read 3, iclass 30, count 2 2006.285.16:53:57.25#ibcon#about to read 4, iclass 30, count 2 2006.285.16:53:57.25#ibcon#read 4, iclass 30, count 2 2006.285.16:53:57.25#ibcon#about to read 5, iclass 30, count 2 2006.285.16:53:57.25#ibcon#read 5, iclass 30, count 2 2006.285.16:53:57.25#ibcon#about to read 6, iclass 30, count 2 2006.285.16:53:57.25#ibcon#read 6, iclass 30, count 2 2006.285.16:53:57.25#ibcon#end of sib2, iclass 30, count 2 2006.285.16:53:57.25#ibcon#*mode == 0, iclass 30, count 2 2006.285.16:53:57.25#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.16:53:57.25#ibcon#[25=AT05-03\r\n] 2006.285.16:53:57.25#ibcon#*before write, iclass 30, count 2 2006.285.16:53:57.25#ibcon#enter sib2, iclass 30, count 2 2006.285.16:53:57.25#ibcon#flushed, iclass 30, count 2 2006.285.16:53:57.25#ibcon#about to write, iclass 30, count 2 2006.285.16:53:57.25#ibcon#wrote, iclass 30, count 2 2006.285.16:53:57.25#ibcon#about to read 3, iclass 30, count 2 2006.285.16:53:57.28#ibcon#read 3, iclass 30, count 2 2006.285.16:53:57.28#ibcon#about to read 4, iclass 30, count 2 2006.285.16:53:57.28#ibcon#read 4, iclass 30, count 2 2006.285.16:53:57.28#ibcon#about to read 5, iclass 30, count 2 2006.285.16:53:57.28#ibcon#read 5, iclass 30, count 2 2006.285.16:53:57.28#ibcon#about to read 6, iclass 30, count 2 2006.285.16:53:57.28#ibcon#read 6, iclass 30, count 2 2006.285.16:53:57.28#ibcon#end of sib2, iclass 30, count 2 2006.285.16:53:57.28#ibcon#*after write, iclass 30, count 2 2006.285.16:53:57.28#ibcon#*before return 0, iclass 30, count 2 2006.285.16:53:57.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:53:57.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:53:57.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.16:53:57.28#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:57.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:53:57.40#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:53:57.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:53:57.48#ibcon#enter wrdev, iclass 30, count 0 2006.285.16:53:57.48#ibcon#first serial, iclass 30, count 0 2006.285.16:53:57.48#ibcon#enter sib2, iclass 30, count 0 2006.285.16:53:57.48#ibcon#flushed, iclass 30, count 0 2006.285.16:53:57.48#ibcon#about to write, iclass 30, count 0 2006.285.16:53:57.48#ibcon#wrote, iclass 30, count 0 2006.285.16:53:57.48#ibcon#about to read 3, iclass 30, count 0 2006.285.16:53:57.50#ibcon#read 3, iclass 30, count 0 2006.285.16:53:57.50#ibcon#about to read 4, iclass 30, count 0 2006.285.16:53:57.50#ibcon#read 4, iclass 30, count 0 2006.285.16:53:57.50#ibcon#about to read 5, iclass 30, count 0 2006.285.16:53:57.50#ibcon#read 5, iclass 30, count 0 2006.285.16:53:57.50#ibcon#about to read 6, iclass 30, count 0 2006.285.16:53:57.50#ibcon#read 6, iclass 30, count 0 2006.285.16:53:57.50#ibcon#end of sib2, iclass 30, count 0 2006.285.16:53:57.50#ibcon#*mode == 0, iclass 30, count 0 2006.285.16:53:57.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.16:53:57.50#ibcon#[25=USB\r\n] 2006.285.16:53:57.50#ibcon#*before write, iclass 30, count 0 2006.285.16:53:57.50#ibcon#enter sib2, iclass 30, count 0 2006.285.16:53:57.50#ibcon#flushed, iclass 30, count 0 2006.285.16:53:57.50#ibcon#about to write, iclass 30, count 0 2006.285.16:53:57.50#ibcon#wrote, iclass 30, count 0 2006.285.16:53:57.50#ibcon#about to read 3, iclass 30, count 0 2006.285.16:53:57.53#ibcon#read 3, iclass 30, count 0 2006.285.16:53:57.53#ibcon#about to read 4, iclass 30, count 0 2006.285.16:53:57.53#ibcon#read 4, iclass 30, count 0 2006.285.16:53:57.53#ibcon#about to read 5, iclass 30, count 0 2006.285.16:53:57.53#ibcon#read 5, iclass 30, count 0 2006.285.16:53:57.53#ibcon#about to read 6, iclass 30, count 0 2006.285.16:53:57.53#ibcon#read 6, iclass 30, count 0 2006.285.16:53:57.53#ibcon#end of sib2, iclass 30, count 0 2006.285.16:53:57.53#ibcon#*after write, iclass 30, count 0 2006.285.16:53:57.53#ibcon#*before return 0, iclass 30, count 0 2006.285.16:53:57.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:53:57.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:53:57.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.16:53:57.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.16:53:57.53$vck44/valo=6,814.99 2006.285.16:53:57.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.16:53:57.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.16:53:57.53#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:57.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:53:57.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:53:57.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:53:57.53#ibcon#enter wrdev, iclass 32, count 0 2006.285.16:53:57.53#ibcon#first serial, iclass 32, count 0 2006.285.16:53:57.53#ibcon#enter sib2, iclass 32, count 0 2006.285.16:53:57.53#ibcon#flushed, iclass 32, count 0 2006.285.16:53:57.53#ibcon#about to write, iclass 32, count 0 2006.285.16:53:57.53#ibcon#wrote, iclass 32, count 0 2006.285.16:53:57.53#ibcon#about to read 3, iclass 32, count 0 2006.285.16:53:57.55#ibcon#read 3, iclass 32, count 0 2006.285.16:53:57.55#ibcon#about to read 4, iclass 32, count 0 2006.285.16:53:57.55#ibcon#read 4, iclass 32, count 0 2006.285.16:53:57.55#ibcon#about to read 5, iclass 32, count 0 2006.285.16:53:57.55#ibcon#read 5, iclass 32, count 0 2006.285.16:53:57.55#ibcon#about to read 6, iclass 32, count 0 2006.285.16:53:57.55#ibcon#read 6, iclass 32, count 0 2006.285.16:53:57.55#ibcon#end of sib2, iclass 32, count 0 2006.285.16:53:57.55#ibcon#*mode == 0, iclass 32, count 0 2006.285.16:53:57.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.16:53:57.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.16:53:57.55#ibcon#*before write, iclass 32, count 0 2006.285.16:53:57.55#ibcon#enter sib2, iclass 32, count 0 2006.285.16:53:57.55#ibcon#flushed, iclass 32, count 0 2006.285.16:53:57.55#ibcon#about to write, iclass 32, count 0 2006.285.16:53:57.55#ibcon#wrote, iclass 32, count 0 2006.285.16:53:57.55#ibcon#about to read 3, iclass 32, count 0 2006.285.16:53:57.59#ibcon#read 3, iclass 32, count 0 2006.285.16:53:57.59#ibcon#about to read 4, iclass 32, count 0 2006.285.16:53:57.59#ibcon#read 4, iclass 32, count 0 2006.285.16:53:57.59#ibcon#about to read 5, iclass 32, count 0 2006.285.16:53:57.59#ibcon#read 5, iclass 32, count 0 2006.285.16:53:57.59#ibcon#about to read 6, iclass 32, count 0 2006.285.16:53:57.59#ibcon#read 6, iclass 32, count 0 2006.285.16:53:57.59#ibcon#end of sib2, iclass 32, count 0 2006.285.16:53:57.59#ibcon#*after write, iclass 32, count 0 2006.285.16:53:57.59#ibcon#*before return 0, iclass 32, count 0 2006.285.16:53:57.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:53:57.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:53:57.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.16:53:57.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.16:53:57.59$vck44/va=6,4 2006.285.16:53:57.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.16:53:57.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.16:53:57.59#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:57.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:53:57.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:53:57.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:53:57.65#ibcon#enter wrdev, iclass 34, count 2 2006.285.16:53:57.65#ibcon#first serial, iclass 34, count 2 2006.285.16:53:57.65#ibcon#enter sib2, iclass 34, count 2 2006.285.16:53:57.65#ibcon#flushed, iclass 34, count 2 2006.285.16:53:57.65#ibcon#about to write, iclass 34, count 2 2006.285.16:53:57.65#ibcon#wrote, iclass 34, count 2 2006.285.16:53:57.65#ibcon#about to read 3, iclass 34, count 2 2006.285.16:53:57.67#ibcon#read 3, iclass 34, count 2 2006.285.16:53:57.67#ibcon#about to read 4, iclass 34, count 2 2006.285.16:53:57.67#ibcon#read 4, iclass 34, count 2 2006.285.16:53:57.67#ibcon#about to read 5, iclass 34, count 2 2006.285.16:53:57.67#ibcon#read 5, iclass 34, count 2 2006.285.16:53:57.67#ibcon#about to read 6, iclass 34, count 2 2006.285.16:53:57.67#ibcon#read 6, iclass 34, count 2 2006.285.16:53:57.67#ibcon#end of sib2, iclass 34, count 2 2006.285.16:53:57.67#ibcon#*mode == 0, iclass 34, count 2 2006.285.16:53:57.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.16:53:57.67#ibcon#[25=AT06-04\r\n] 2006.285.16:53:57.67#ibcon#*before write, iclass 34, count 2 2006.285.16:53:57.67#ibcon#enter sib2, iclass 34, count 2 2006.285.16:53:57.67#ibcon#flushed, iclass 34, count 2 2006.285.16:53:57.67#ibcon#about to write, iclass 34, count 2 2006.285.16:53:57.67#ibcon#wrote, iclass 34, count 2 2006.285.16:53:57.67#ibcon#about to read 3, iclass 34, count 2 2006.285.16:53:57.70#ibcon#read 3, iclass 34, count 2 2006.285.16:53:57.70#ibcon#about to read 4, iclass 34, count 2 2006.285.16:53:57.70#ibcon#read 4, iclass 34, count 2 2006.285.16:53:57.70#ibcon#about to read 5, iclass 34, count 2 2006.285.16:53:57.70#ibcon#read 5, iclass 34, count 2 2006.285.16:53:57.70#ibcon#about to read 6, iclass 34, count 2 2006.285.16:53:57.70#ibcon#read 6, iclass 34, count 2 2006.285.16:53:57.70#ibcon#end of sib2, iclass 34, count 2 2006.285.16:53:57.70#ibcon#*after write, iclass 34, count 2 2006.285.16:53:57.70#ibcon#*before return 0, iclass 34, count 2 2006.285.16:53:57.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:53:57.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:53:57.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.16:53:57.70#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:57.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:53:57.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:53:57.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:53:57.82#ibcon#enter wrdev, iclass 34, count 0 2006.285.16:53:57.82#ibcon#first serial, iclass 34, count 0 2006.285.16:53:57.82#ibcon#enter sib2, iclass 34, count 0 2006.285.16:53:57.82#ibcon#flushed, iclass 34, count 0 2006.285.16:53:57.82#ibcon#about to write, iclass 34, count 0 2006.285.16:53:57.82#ibcon#wrote, iclass 34, count 0 2006.285.16:53:57.82#ibcon#about to read 3, iclass 34, count 0 2006.285.16:53:57.84#ibcon#read 3, iclass 34, count 0 2006.285.16:53:57.84#ibcon#about to read 4, iclass 34, count 0 2006.285.16:53:57.84#ibcon#read 4, iclass 34, count 0 2006.285.16:53:57.84#ibcon#about to read 5, iclass 34, count 0 2006.285.16:53:57.84#ibcon#read 5, iclass 34, count 0 2006.285.16:53:57.84#ibcon#about to read 6, iclass 34, count 0 2006.285.16:53:57.84#ibcon#read 6, iclass 34, count 0 2006.285.16:53:57.84#ibcon#end of sib2, iclass 34, count 0 2006.285.16:53:57.84#ibcon#*mode == 0, iclass 34, count 0 2006.285.16:53:57.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.16:53:57.84#ibcon#[25=USB\r\n] 2006.285.16:53:57.84#ibcon#*before write, iclass 34, count 0 2006.285.16:53:57.84#ibcon#enter sib2, iclass 34, count 0 2006.285.16:53:57.84#ibcon#flushed, iclass 34, count 0 2006.285.16:53:57.84#ibcon#about to write, iclass 34, count 0 2006.285.16:53:57.84#ibcon#wrote, iclass 34, count 0 2006.285.16:53:57.84#ibcon#about to read 3, iclass 34, count 0 2006.285.16:53:57.87#ibcon#read 3, iclass 34, count 0 2006.285.16:53:57.87#ibcon#about to read 4, iclass 34, count 0 2006.285.16:53:57.87#ibcon#read 4, iclass 34, count 0 2006.285.16:53:57.87#ibcon#about to read 5, iclass 34, count 0 2006.285.16:53:57.87#ibcon#read 5, iclass 34, count 0 2006.285.16:53:57.87#ibcon#about to read 6, iclass 34, count 0 2006.285.16:53:57.87#ibcon#read 6, iclass 34, count 0 2006.285.16:53:57.87#ibcon#end of sib2, iclass 34, count 0 2006.285.16:53:57.87#ibcon#*after write, iclass 34, count 0 2006.285.16:53:57.87#ibcon#*before return 0, iclass 34, count 0 2006.285.16:53:57.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:53:57.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:53:57.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.16:53:57.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.16:53:57.87$vck44/valo=7,864.99 2006.285.16:53:57.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.16:53:57.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.16:53:57.87#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:57.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:53:57.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:53:57.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:53:57.87#ibcon#enter wrdev, iclass 36, count 0 2006.285.16:53:57.87#ibcon#first serial, iclass 36, count 0 2006.285.16:53:57.87#ibcon#enter sib2, iclass 36, count 0 2006.285.16:53:57.87#ibcon#flushed, iclass 36, count 0 2006.285.16:53:57.87#ibcon#about to write, iclass 36, count 0 2006.285.16:53:57.87#ibcon#wrote, iclass 36, count 0 2006.285.16:53:57.87#ibcon#about to read 3, iclass 36, count 0 2006.285.16:53:57.89#ibcon#read 3, iclass 36, count 0 2006.285.16:53:57.89#ibcon#about to read 4, iclass 36, count 0 2006.285.16:53:57.89#ibcon#read 4, iclass 36, count 0 2006.285.16:53:57.89#ibcon#about to read 5, iclass 36, count 0 2006.285.16:53:57.89#ibcon#read 5, iclass 36, count 0 2006.285.16:53:57.89#ibcon#about to read 6, iclass 36, count 0 2006.285.16:53:57.89#ibcon#read 6, iclass 36, count 0 2006.285.16:53:57.89#ibcon#end of sib2, iclass 36, count 0 2006.285.16:53:57.89#ibcon#*mode == 0, iclass 36, count 0 2006.285.16:53:57.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.16:53:57.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.16:53:57.89#ibcon#*before write, iclass 36, count 0 2006.285.16:53:57.89#ibcon#enter sib2, iclass 36, count 0 2006.285.16:53:57.89#ibcon#flushed, iclass 36, count 0 2006.285.16:53:57.89#ibcon#about to write, iclass 36, count 0 2006.285.16:53:57.89#ibcon#wrote, iclass 36, count 0 2006.285.16:53:57.89#ibcon#about to read 3, iclass 36, count 0 2006.285.16:53:57.93#ibcon#read 3, iclass 36, count 0 2006.285.16:53:57.93#ibcon#about to read 4, iclass 36, count 0 2006.285.16:53:57.93#ibcon#read 4, iclass 36, count 0 2006.285.16:53:57.93#ibcon#about to read 5, iclass 36, count 0 2006.285.16:53:57.93#ibcon#read 5, iclass 36, count 0 2006.285.16:53:57.93#ibcon#about to read 6, iclass 36, count 0 2006.285.16:53:57.93#ibcon#read 6, iclass 36, count 0 2006.285.16:53:57.93#ibcon#end of sib2, iclass 36, count 0 2006.285.16:53:57.93#ibcon#*after write, iclass 36, count 0 2006.285.16:53:57.93#ibcon#*before return 0, iclass 36, count 0 2006.285.16:53:57.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:53:57.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:53:57.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.16:53:57.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.16:53:57.93$vck44/va=7,4 2006.285.16:53:57.93#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.16:53:57.93#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.16:53:57.93#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:57.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:53:57.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:53:57.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:53:57.99#ibcon#enter wrdev, iclass 38, count 2 2006.285.16:53:57.99#ibcon#first serial, iclass 38, count 2 2006.285.16:53:57.99#ibcon#enter sib2, iclass 38, count 2 2006.285.16:53:57.99#ibcon#flushed, iclass 38, count 2 2006.285.16:53:57.99#ibcon#about to write, iclass 38, count 2 2006.285.16:53:57.99#ibcon#wrote, iclass 38, count 2 2006.285.16:53:57.99#ibcon#about to read 3, iclass 38, count 2 2006.285.16:53:58.01#ibcon#read 3, iclass 38, count 2 2006.285.16:53:58.01#ibcon#about to read 4, iclass 38, count 2 2006.285.16:53:58.01#ibcon#read 4, iclass 38, count 2 2006.285.16:53:58.01#ibcon#about to read 5, iclass 38, count 2 2006.285.16:53:58.01#ibcon#read 5, iclass 38, count 2 2006.285.16:53:58.01#ibcon#about to read 6, iclass 38, count 2 2006.285.16:53:58.01#ibcon#read 6, iclass 38, count 2 2006.285.16:53:58.01#ibcon#end of sib2, iclass 38, count 2 2006.285.16:53:58.01#ibcon#*mode == 0, iclass 38, count 2 2006.285.16:53:58.01#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.16:53:58.01#ibcon#[25=AT07-04\r\n] 2006.285.16:53:58.01#ibcon#*before write, iclass 38, count 2 2006.285.16:53:58.01#ibcon#enter sib2, iclass 38, count 2 2006.285.16:53:58.01#ibcon#flushed, iclass 38, count 2 2006.285.16:53:58.01#ibcon#about to write, iclass 38, count 2 2006.285.16:53:58.01#ibcon#wrote, iclass 38, count 2 2006.285.16:53:58.01#ibcon#about to read 3, iclass 38, count 2 2006.285.16:53:58.04#ibcon#read 3, iclass 38, count 2 2006.285.16:53:58.04#ibcon#about to read 4, iclass 38, count 2 2006.285.16:53:58.04#ibcon#read 4, iclass 38, count 2 2006.285.16:53:58.04#ibcon#about to read 5, iclass 38, count 2 2006.285.16:53:58.04#ibcon#read 5, iclass 38, count 2 2006.285.16:53:58.04#ibcon#about to read 6, iclass 38, count 2 2006.285.16:53:58.04#ibcon#read 6, iclass 38, count 2 2006.285.16:53:58.04#ibcon#end of sib2, iclass 38, count 2 2006.285.16:53:58.04#ibcon#*after write, iclass 38, count 2 2006.285.16:53:58.04#ibcon#*before return 0, iclass 38, count 2 2006.285.16:53:58.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:53:58.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:53:58.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.16:53:58.04#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:58.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:53:58.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:53:58.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:53:58.16#ibcon#enter wrdev, iclass 38, count 0 2006.285.16:53:58.16#ibcon#first serial, iclass 38, count 0 2006.285.16:53:58.16#ibcon#enter sib2, iclass 38, count 0 2006.285.16:53:58.16#ibcon#flushed, iclass 38, count 0 2006.285.16:53:58.16#ibcon#about to write, iclass 38, count 0 2006.285.16:53:58.16#ibcon#wrote, iclass 38, count 0 2006.285.16:53:58.16#ibcon#about to read 3, iclass 38, count 0 2006.285.16:53:58.18#ibcon#read 3, iclass 38, count 0 2006.285.16:53:58.18#ibcon#about to read 4, iclass 38, count 0 2006.285.16:53:58.18#ibcon#read 4, iclass 38, count 0 2006.285.16:53:58.18#ibcon#about to read 5, iclass 38, count 0 2006.285.16:53:58.18#ibcon#read 5, iclass 38, count 0 2006.285.16:53:58.18#ibcon#about to read 6, iclass 38, count 0 2006.285.16:53:58.18#ibcon#read 6, iclass 38, count 0 2006.285.16:53:58.18#ibcon#end of sib2, iclass 38, count 0 2006.285.16:53:58.18#ibcon#*mode == 0, iclass 38, count 0 2006.285.16:53:58.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.16:53:58.18#ibcon#[25=USB\r\n] 2006.285.16:53:58.18#ibcon#*before write, iclass 38, count 0 2006.285.16:53:58.18#ibcon#enter sib2, iclass 38, count 0 2006.285.16:53:58.18#ibcon#flushed, iclass 38, count 0 2006.285.16:53:58.18#ibcon#about to write, iclass 38, count 0 2006.285.16:53:58.18#ibcon#wrote, iclass 38, count 0 2006.285.16:53:58.18#ibcon#about to read 3, iclass 38, count 0 2006.285.16:53:58.21#ibcon#read 3, iclass 38, count 0 2006.285.16:53:58.21#ibcon#about to read 4, iclass 38, count 0 2006.285.16:53:58.21#ibcon#read 4, iclass 38, count 0 2006.285.16:53:58.21#ibcon#about to read 5, iclass 38, count 0 2006.285.16:53:58.21#ibcon#read 5, iclass 38, count 0 2006.285.16:53:58.21#ibcon#about to read 6, iclass 38, count 0 2006.285.16:53:58.21#ibcon#read 6, iclass 38, count 0 2006.285.16:53:58.21#ibcon#end of sib2, iclass 38, count 0 2006.285.16:53:58.21#ibcon#*after write, iclass 38, count 0 2006.285.16:53:58.21#ibcon#*before return 0, iclass 38, count 0 2006.285.16:53:58.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:53:58.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:53:58.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.16:53:58.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.16:53:58.21$vck44/valo=8,884.99 2006.285.16:53:58.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.16:53:58.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.16:53:58.21#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:58.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:53:58.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:53:58.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:53:58.21#ibcon#enter wrdev, iclass 40, count 0 2006.285.16:53:58.21#ibcon#first serial, iclass 40, count 0 2006.285.16:53:58.21#ibcon#enter sib2, iclass 40, count 0 2006.285.16:53:58.21#ibcon#flushed, iclass 40, count 0 2006.285.16:53:58.21#ibcon#about to write, iclass 40, count 0 2006.285.16:53:58.21#ibcon#wrote, iclass 40, count 0 2006.285.16:53:58.21#ibcon#about to read 3, iclass 40, count 0 2006.285.16:53:58.23#ibcon#read 3, iclass 40, count 0 2006.285.16:53:58.23#ibcon#about to read 4, iclass 40, count 0 2006.285.16:53:58.23#ibcon#read 4, iclass 40, count 0 2006.285.16:53:58.23#ibcon#about to read 5, iclass 40, count 0 2006.285.16:53:58.23#ibcon#read 5, iclass 40, count 0 2006.285.16:53:58.23#ibcon#about to read 6, iclass 40, count 0 2006.285.16:53:58.23#ibcon#read 6, iclass 40, count 0 2006.285.16:53:58.23#ibcon#end of sib2, iclass 40, count 0 2006.285.16:53:58.23#ibcon#*mode == 0, iclass 40, count 0 2006.285.16:53:58.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.16:53:58.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.16:53:58.23#ibcon#*before write, iclass 40, count 0 2006.285.16:53:58.23#ibcon#enter sib2, iclass 40, count 0 2006.285.16:53:58.23#ibcon#flushed, iclass 40, count 0 2006.285.16:53:58.23#ibcon#about to write, iclass 40, count 0 2006.285.16:53:58.23#ibcon#wrote, iclass 40, count 0 2006.285.16:53:58.23#ibcon#about to read 3, iclass 40, count 0 2006.285.16:53:58.27#ibcon#read 3, iclass 40, count 0 2006.285.16:53:58.27#ibcon#about to read 4, iclass 40, count 0 2006.285.16:53:58.27#ibcon#read 4, iclass 40, count 0 2006.285.16:53:58.27#ibcon#about to read 5, iclass 40, count 0 2006.285.16:53:58.27#ibcon#read 5, iclass 40, count 0 2006.285.16:53:58.27#ibcon#about to read 6, iclass 40, count 0 2006.285.16:53:58.27#ibcon#read 6, iclass 40, count 0 2006.285.16:53:58.27#ibcon#end of sib2, iclass 40, count 0 2006.285.16:53:58.27#ibcon#*after write, iclass 40, count 0 2006.285.16:53:58.27#ibcon#*before return 0, iclass 40, count 0 2006.285.16:53:58.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:53:58.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:53:58.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.16:53:58.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.16:53:58.27$vck44/va=8,3 2006.285.16:53:58.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.16:53:58.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.16:53:58.27#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:58.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:53:58.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:53:58.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:53:58.33#ibcon#enter wrdev, iclass 4, count 2 2006.285.16:53:58.33#ibcon#first serial, iclass 4, count 2 2006.285.16:53:58.33#ibcon#enter sib2, iclass 4, count 2 2006.285.16:53:58.33#ibcon#flushed, iclass 4, count 2 2006.285.16:53:58.33#ibcon#about to write, iclass 4, count 2 2006.285.16:53:58.33#ibcon#wrote, iclass 4, count 2 2006.285.16:53:58.33#ibcon#about to read 3, iclass 4, count 2 2006.285.16:53:58.35#ibcon#read 3, iclass 4, count 2 2006.285.16:53:58.35#ibcon#about to read 4, iclass 4, count 2 2006.285.16:53:58.35#ibcon#read 4, iclass 4, count 2 2006.285.16:53:58.35#ibcon#about to read 5, iclass 4, count 2 2006.285.16:53:58.35#ibcon#read 5, iclass 4, count 2 2006.285.16:53:58.35#ibcon#about to read 6, iclass 4, count 2 2006.285.16:53:58.35#ibcon#read 6, iclass 4, count 2 2006.285.16:53:58.35#ibcon#end of sib2, iclass 4, count 2 2006.285.16:53:58.35#ibcon#*mode == 0, iclass 4, count 2 2006.285.16:53:58.35#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.16:53:58.35#ibcon#[25=AT08-03\r\n] 2006.285.16:53:58.35#ibcon#*before write, iclass 4, count 2 2006.285.16:53:58.35#ibcon#enter sib2, iclass 4, count 2 2006.285.16:53:58.35#ibcon#flushed, iclass 4, count 2 2006.285.16:53:58.35#ibcon#about to write, iclass 4, count 2 2006.285.16:53:58.35#ibcon#wrote, iclass 4, count 2 2006.285.16:53:58.35#ibcon#about to read 3, iclass 4, count 2 2006.285.16:53:58.38#ibcon#read 3, iclass 4, count 2 2006.285.16:53:58.38#ibcon#about to read 4, iclass 4, count 2 2006.285.16:53:58.38#ibcon#read 4, iclass 4, count 2 2006.285.16:53:58.38#ibcon#about to read 5, iclass 4, count 2 2006.285.16:53:58.38#ibcon#read 5, iclass 4, count 2 2006.285.16:53:58.38#ibcon#about to read 6, iclass 4, count 2 2006.285.16:53:58.38#ibcon#read 6, iclass 4, count 2 2006.285.16:53:58.38#ibcon#end of sib2, iclass 4, count 2 2006.285.16:53:58.38#ibcon#*after write, iclass 4, count 2 2006.285.16:53:58.38#ibcon#*before return 0, iclass 4, count 2 2006.285.16:53:58.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:53:58.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.16:53:58.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.16:53:58.38#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:58.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:53:58.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:53:58.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:53:58.50#ibcon#enter wrdev, iclass 4, count 0 2006.285.16:53:58.50#ibcon#first serial, iclass 4, count 0 2006.285.16:53:58.50#ibcon#enter sib2, iclass 4, count 0 2006.285.16:53:58.50#ibcon#flushed, iclass 4, count 0 2006.285.16:53:58.50#ibcon#about to write, iclass 4, count 0 2006.285.16:53:58.50#ibcon#wrote, iclass 4, count 0 2006.285.16:53:58.50#ibcon#about to read 3, iclass 4, count 0 2006.285.16:53:58.52#ibcon#read 3, iclass 4, count 0 2006.285.16:53:58.52#ibcon#about to read 4, iclass 4, count 0 2006.285.16:53:58.52#ibcon#read 4, iclass 4, count 0 2006.285.16:53:58.52#ibcon#about to read 5, iclass 4, count 0 2006.285.16:53:58.52#ibcon#read 5, iclass 4, count 0 2006.285.16:53:58.52#ibcon#about to read 6, iclass 4, count 0 2006.285.16:53:58.52#ibcon#read 6, iclass 4, count 0 2006.285.16:53:58.52#ibcon#end of sib2, iclass 4, count 0 2006.285.16:53:58.52#ibcon#*mode == 0, iclass 4, count 0 2006.285.16:53:58.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.16:53:58.52#ibcon#[25=USB\r\n] 2006.285.16:53:58.52#ibcon#*before write, iclass 4, count 0 2006.285.16:53:58.52#ibcon#enter sib2, iclass 4, count 0 2006.285.16:53:58.52#ibcon#flushed, iclass 4, count 0 2006.285.16:53:58.52#ibcon#about to write, iclass 4, count 0 2006.285.16:53:58.52#ibcon#wrote, iclass 4, count 0 2006.285.16:53:58.52#ibcon#about to read 3, iclass 4, count 0 2006.285.16:53:58.55#ibcon#read 3, iclass 4, count 0 2006.285.16:53:58.55#ibcon#about to read 4, iclass 4, count 0 2006.285.16:53:58.55#ibcon#read 4, iclass 4, count 0 2006.285.16:53:58.55#ibcon#about to read 5, iclass 4, count 0 2006.285.16:53:58.55#ibcon#read 5, iclass 4, count 0 2006.285.16:53:58.55#ibcon#about to read 6, iclass 4, count 0 2006.285.16:53:58.55#ibcon#read 6, iclass 4, count 0 2006.285.16:53:58.55#ibcon#end of sib2, iclass 4, count 0 2006.285.16:53:58.55#ibcon#*after write, iclass 4, count 0 2006.285.16:53:58.55#ibcon#*before return 0, iclass 4, count 0 2006.285.16:53:58.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:53:58.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.16:53:58.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.16:53:58.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.16:53:58.55$vck44/vblo=1,629.99 2006.285.16:53:58.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.16:53:58.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.16:53:58.55#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:58.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.16:53:58.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.16:53:58.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.16:53:58.55#ibcon#enter wrdev, iclass 6, count 0 2006.285.16:53:58.55#ibcon#first serial, iclass 6, count 0 2006.285.16:53:58.55#ibcon#enter sib2, iclass 6, count 0 2006.285.16:53:58.55#ibcon#flushed, iclass 6, count 0 2006.285.16:53:58.55#ibcon#about to write, iclass 6, count 0 2006.285.16:53:58.55#ibcon#wrote, iclass 6, count 0 2006.285.16:53:58.55#ibcon#about to read 3, iclass 6, count 0 2006.285.16:53:58.57#ibcon#read 3, iclass 6, count 0 2006.285.16:53:58.57#ibcon#about to read 4, iclass 6, count 0 2006.285.16:53:58.57#ibcon#read 4, iclass 6, count 0 2006.285.16:53:58.57#ibcon#about to read 5, iclass 6, count 0 2006.285.16:53:58.57#ibcon#read 5, iclass 6, count 0 2006.285.16:53:58.57#ibcon#about to read 6, iclass 6, count 0 2006.285.16:53:58.57#ibcon#read 6, iclass 6, count 0 2006.285.16:53:58.57#ibcon#end of sib2, iclass 6, count 0 2006.285.16:53:58.57#ibcon#*mode == 0, iclass 6, count 0 2006.285.16:53:58.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.16:53:58.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.16:53:58.57#ibcon#*before write, iclass 6, count 0 2006.285.16:53:58.57#ibcon#enter sib2, iclass 6, count 0 2006.285.16:53:58.57#ibcon#flushed, iclass 6, count 0 2006.285.16:53:58.57#ibcon#about to write, iclass 6, count 0 2006.285.16:53:58.57#ibcon#wrote, iclass 6, count 0 2006.285.16:53:58.57#ibcon#about to read 3, iclass 6, count 0 2006.285.16:53:58.61#ibcon#read 3, iclass 6, count 0 2006.285.16:53:58.61#ibcon#about to read 4, iclass 6, count 0 2006.285.16:53:58.61#ibcon#read 4, iclass 6, count 0 2006.285.16:53:58.61#ibcon#about to read 5, iclass 6, count 0 2006.285.16:53:58.61#ibcon#read 5, iclass 6, count 0 2006.285.16:53:58.61#ibcon#about to read 6, iclass 6, count 0 2006.285.16:53:58.61#ibcon#read 6, iclass 6, count 0 2006.285.16:53:58.61#ibcon#end of sib2, iclass 6, count 0 2006.285.16:53:58.61#ibcon#*after write, iclass 6, count 0 2006.285.16:53:58.61#ibcon#*before return 0, iclass 6, count 0 2006.285.16:53:58.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.16:53:58.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.16:53:58.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.16:53:58.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.16:53:58.61$vck44/vb=1,4 2006.285.16:53:58.61#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.16:53:58.61#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.16:53:58.61#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:58.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.16:53:58.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.16:53:58.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.16:53:58.61#ibcon#enter wrdev, iclass 10, count 2 2006.285.16:53:58.61#ibcon#first serial, iclass 10, count 2 2006.285.16:53:58.61#ibcon#enter sib2, iclass 10, count 2 2006.285.16:53:58.61#ibcon#flushed, iclass 10, count 2 2006.285.16:53:58.61#ibcon#about to write, iclass 10, count 2 2006.285.16:53:58.61#ibcon#wrote, iclass 10, count 2 2006.285.16:53:58.61#ibcon#about to read 3, iclass 10, count 2 2006.285.16:53:58.63#ibcon#read 3, iclass 10, count 2 2006.285.16:53:58.63#ibcon#about to read 4, iclass 10, count 2 2006.285.16:53:58.63#ibcon#read 4, iclass 10, count 2 2006.285.16:53:58.63#ibcon#about to read 5, iclass 10, count 2 2006.285.16:53:58.63#ibcon#read 5, iclass 10, count 2 2006.285.16:53:58.63#ibcon#about to read 6, iclass 10, count 2 2006.285.16:53:58.63#ibcon#read 6, iclass 10, count 2 2006.285.16:53:58.63#ibcon#end of sib2, iclass 10, count 2 2006.285.16:53:58.63#ibcon#*mode == 0, iclass 10, count 2 2006.285.16:53:58.63#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.16:53:58.63#ibcon#[27=AT01-04\r\n] 2006.285.16:53:58.63#ibcon#*before write, iclass 10, count 2 2006.285.16:53:58.63#ibcon#enter sib2, iclass 10, count 2 2006.285.16:53:58.63#ibcon#flushed, iclass 10, count 2 2006.285.16:53:58.63#ibcon#about to write, iclass 10, count 2 2006.285.16:53:58.63#ibcon#wrote, iclass 10, count 2 2006.285.16:53:58.63#ibcon#about to read 3, iclass 10, count 2 2006.285.16:53:58.66#ibcon#read 3, iclass 10, count 2 2006.285.16:53:58.66#ibcon#about to read 4, iclass 10, count 2 2006.285.16:53:58.66#ibcon#read 4, iclass 10, count 2 2006.285.16:53:58.66#ibcon#about to read 5, iclass 10, count 2 2006.285.16:53:58.66#ibcon#read 5, iclass 10, count 2 2006.285.16:53:58.66#ibcon#about to read 6, iclass 10, count 2 2006.285.16:53:58.66#ibcon#read 6, iclass 10, count 2 2006.285.16:53:58.66#ibcon#end of sib2, iclass 10, count 2 2006.285.16:53:58.66#ibcon#*after write, iclass 10, count 2 2006.285.16:53:58.66#ibcon#*before return 0, iclass 10, count 2 2006.285.16:53:58.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.16:53:58.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.16:53:58.66#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.16:53:58.66#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:58.66#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.16:53:58.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.16:53:58.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.16:53:58.78#ibcon#enter wrdev, iclass 10, count 0 2006.285.16:53:58.78#ibcon#first serial, iclass 10, count 0 2006.285.16:53:58.78#ibcon#enter sib2, iclass 10, count 0 2006.285.16:53:58.78#ibcon#flushed, iclass 10, count 0 2006.285.16:53:58.78#ibcon#about to write, iclass 10, count 0 2006.285.16:53:58.78#ibcon#wrote, iclass 10, count 0 2006.285.16:53:58.78#ibcon#about to read 3, iclass 10, count 0 2006.285.16:53:58.80#ibcon#read 3, iclass 10, count 0 2006.285.16:53:58.80#ibcon#about to read 4, iclass 10, count 0 2006.285.16:53:58.80#ibcon#read 4, iclass 10, count 0 2006.285.16:53:58.80#ibcon#about to read 5, iclass 10, count 0 2006.285.16:53:58.80#ibcon#read 5, iclass 10, count 0 2006.285.16:53:58.80#ibcon#about to read 6, iclass 10, count 0 2006.285.16:53:58.80#ibcon#read 6, iclass 10, count 0 2006.285.16:53:58.80#ibcon#end of sib2, iclass 10, count 0 2006.285.16:53:58.80#ibcon#*mode == 0, iclass 10, count 0 2006.285.16:53:58.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.16:53:58.80#ibcon#[27=USB\r\n] 2006.285.16:53:58.80#ibcon#*before write, iclass 10, count 0 2006.285.16:53:58.80#ibcon#enter sib2, iclass 10, count 0 2006.285.16:53:58.80#ibcon#flushed, iclass 10, count 0 2006.285.16:53:58.80#ibcon#about to write, iclass 10, count 0 2006.285.16:53:58.80#ibcon#wrote, iclass 10, count 0 2006.285.16:53:58.80#ibcon#about to read 3, iclass 10, count 0 2006.285.16:53:58.83#ibcon#read 3, iclass 10, count 0 2006.285.16:53:58.83#ibcon#about to read 4, iclass 10, count 0 2006.285.16:53:58.83#ibcon#read 4, iclass 10, count 0 2006.285.16:53:58.83#ibcon#about to read 5, iclass 10, count 0 2006.285.16:53:58.83#ibcon#read 5, iclass 10, count 0 2006.285.16:53:58.83#ibcon#about to read 6, iclass 10, count 0 2006.285.16:53:58.83#ibcon#read 6, iclass 10, count 0 2006.285.16:53:58.83#ibcon#end of sib2, iclass 10, count 0 2006.285.16:53:58.83#ibcon#*after write, iclass 10, count 0 2006.285.16:53:58.83#ibcon#*before return 0, iclass 10, count 0 2006.285.16:53:58.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.16:53:58.83#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.16:53:58.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.16:53:58.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.16:53:58.83$vck44/vblo=2,634.99 2006.285.16:53:58.83#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.16:53:58.83#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.16:53:58.83#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:58.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:53:58.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:53:58.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:53:58.83#ibcon#enter wrdev, iclass 12, count 0 2006.285.16:53:58.83#ibcon#first serial, iclass 12, count 0 2006.285.16:53:58.83#ibcon#enter sib2, iclass 12, count 0 2006.285.16:53:58.83#ibcon#flushed, iclass 12, count 0 2006.285.16:53:58.83#ibcon#about to write, iclass 12, count 0 2006.285.16:53:58.83#ibcon#wrote, iclass 12, count 0 2006.285.16:53:58.83#ibcon#about to read 3, iclass 12, count 0 2006.285.16:53:58.85#ibcon#read 3, iclass 12, count 0 2006.285.16:53:58.85#ibcon#about to read 4, iclass 12, count 0 2006.285.16:53:58.85#ibcon#read 4, iclass 12, count 0 2006.285.16:53:58.85#ibcon#about to read 5, iclass 12, count 0 2006.285.16:53:58.85#ibcon#read 5, iclass 12, count 0 2006.285.16:53:58.85#ibcon#about to read 6, iclass 12, count 0 2006.285.16:53:58.85#ibcon#read 6, iclass 12, count 0 2006.285.16:53:58.85#ibcon#end of sib2, iclass 12, count 0 2006.285.16:53:58.85#ibcon#*mode == 0, iclass 12, count 0 2006.285.16:53:58.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.16:53:58.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.16:53:58.85#ibcon#*before write, iclass 12, count 0 2006.285.16:53:58.85#ibcon#enter sib2, iclass 12, count 0 2006.285.16:53:58.85#ibcon#flushed, iclass 12, count 0 2006.285.16:53:58.85#ibcon#about to write, iclass 12, count 0 2006.285.16:53:58.85#ibcon#wrote, iclass 12, count 0 2006.285.16:53:58.85#ibcon#about to read 3, iclass 12, count 0 2006.285.16:53:58.89#ibcon#read 3, iclass 12, count 0 2006.285.16:53:58.89#ibcon#about to read 4, iclass 12, count 0 2006.285.16:53:58.89#ibcon#read 4, iclass 12, count 0 2006.285.16:53:58.89#ibcon#about to read 5, iclass 12, count 0 2006.285.16:53:58.89#ibcon#read 5, iclass 12, count 0 2006.285.16:53:58.89#ibcon#about to read 6, iclass 12, count 0 2006.285.16:53:58.89#ibcon#read 6, iclass 12, count 0 2006.285.16:53:58.89#ibcon#end of sib2, iclass 12, count 0 2006.285.16:53:58.89#ibcon#*after write, iclass 12, count 0 2006.285.16:53:58.89#ibcon#*before return 0, iclass 12, count 0 2006.285.16:53:58.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:53:58.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.16:53:58.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.16:53:58.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.16:53:58.89$vck44/vb=2,5 2006.285.16:53:58.89#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.16:53:58.89#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.16:53:58.89#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:58.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:53:58.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:53:58.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:53:58.95#ibcon#enter wrdev, iclass 14, count 2 2006.285.16:53:58.95#ibcon#first serial, iclass 14, count 2 2006.285.16:53:58.95#ibcon#enter sib2, iclass 14, count 2 2006.285.16:53:58.95#ibcon#flushed, iclass 14, count 2 2006.285.16:53:58.95#ibcon#about to write, iclass 14, count 2 2006.285.16:53:58.95#ibcon#wrote, iclass 14, count 2 2006.285.16:53:58.95#ibcon#about to read 3, iclass 14, count 2 2006.285.16:53:58.97#ibcon#read 3, iclass 14, count 2 2006.285.16:53:58.97#ibcon#about to read 4, iclass 14, count 2 2006.285.16:53:58.97#ibcon#read 4, iclass 14, count 2 2006.285.16:53:58.97#ibcon#about to read 5, iclass 14, count 2 2006.285.16:53:58.97#ibcon#read 5, iclass 14, count 2 2006.285.16:53:58.97#ibcon#about to read 6, iclass 14, count 2 2006.285.16:53:58.97#ibcon#read 6, iclass 14, count 2 2006.285.16:53:58.97#ibcon#end of sib2, iclass 14, count 2 2006.285.16:53:58.97#ibcon#*mode == 0, iclass 14, count 2 2006.285.16:53:58.97#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.16:53:58.97#ibcon#[27=AT02-05\r\n] 2006.285.16:53:58.97#ibcon#*before write, iclass 14, count 2 2006.285.16:53:58.97#ibcon#enter sib2, iclass 14, count 2 2006.285.16:53:58.97#ibcon#flushed, iclass 14, count 2 2006.285.16:53:58.97#ibcon#about to write, iclass 14, count 2 2006.285.16:53:58.97#ibcon#wrote, iclass 14, count 2 2006.285.16:53:58.97#ibcon#about to read 3, iclass 14, count 2 2006.285.16:53:59.00#ibcon#read 3, iclass 14, count 2 2006.285.16:53:59.00#ibcon#about to read 4, iclass 14, count 2 2006.285.16:53:59.00#ibcon#read 4, iclass 14, count 2 2006.285.16:53:59.00#ibcon#about to read 5, iclass 14, count 2 2006.285.16:53:59.00#ibcon#read 5, iclass 14, count 2 2006.285.16:53:59.00#ibcon#about to read 6, iclass 14, count 2 2006.285.16:53:59.00#ibcon#read 6, iclass 14, count 2 2006.285.16:53:59.00#ibcon#end of sib2, iclass 14, count 2 2006.285.16:53:59.00#ibcon#*after write, iclass 14, count 2 2006.285.16:53:59.00#ibcon#*before return 0, iclass 14, count 2 2006.285.16:53:59.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:53:59.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.16:53:59.00#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.16:53:59.00#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:59.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:53:59.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:53:59.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:53:59.12#ibcon#enter wrdev, iclass 14, count 0 2006.285.16:53:59.12#ibcon#first serial, iclass 14, count 0 2006.285.16:53:59.12#ibcon#enter sib2, iclass 14, count 0 2006.285.16:53:59.12#ibcon#flushed, iclass 14, count 0 2006.285.16:53:59.12#ibcon#about to write, iclass 14, count 0 2006.285.16:53:59.12#ibcon#wrote, iclass 14, count 0 2006.285.16:53:59.12#ibcon#about to read 3, iclass 14, count 0 2006.285.16:53:59.14#ibcon#read 3, iclass 14, count 0 2006.285.16:53:59.14#ibcon#about to read 4, iclass 14, count 0 2006.285.16:53:59.14#ibcon#read 4, iclass 14, count 0 2006.285.16:53:59.14#ibcon#about to read 5, iclass 14, count 0 2006.285.16:53:59.14#ibcon#read 5, iclass 14, count 0 2006.285.16:53:59.14#ibcon#about to read 6, iclass 14, count 0 2006.285.16:53:59.14#ibcon#read 6, iclass 14, count 0 2006.285.16:53:59.14#ibcon#end of sib2, iclass 14, count 0 2006.285.16:53:59.14#ibcon#*mode == 0, iclass 14, count 0 2006.285.16:53:59.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.16:53:59.14#ibcon#[27=USB\r\n] 2006.285.16:53:59.14#ibcon#*before write, iclass 14, count 0 2006.285.16:53:59.14#ibcon#enter sib2, iclass 14, count 0 2006.285.16:53:59.14#ibcon#flushed, iclass 14, count 0 2006.285.16:53:59.14#ibcon#about to write, iclass 14, count 0 2006.285.16:53:59.14#ibcon#wrote, iclass 14, count 0 2006.285.16:53:59.14#ibcon#about to read 3, iclass 14, count 0 2006.285.16:53:59.17#ibcon#read 3, iclass 14, count 0 2006.285.16:53:59.17#ibcon#about to read 4, iclass 14, count 0 2006.285.16:53:59.17#ibcon#read 4, iclass 14, count 0 2006.285.16:53:59.17#ibcon#about to read 5, iclass 14, count 0 2006.285.16:53:59.17#ibcon#read 5, iclass 14, count 0 2006.285.16:53:59.17#ibcon#about to read 6, iclass 14, count 0 2006.285.16:53:59.17#ibcon#read 6, iclass 14, count 0 2006.285.16:53:59.17#ibcon#end of sib2, iclass 14, count 0 2006.285.16:53:59.17#ibcon#*after write, iclass 14, count 0 2006.285.16:53:59.17#ibcon#*before return 0, iclass 14, count 0 2006.285.16:53:59.17#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:53:59.17#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.16:53:59.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.16:53:59.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.16:53:59.17$vck44/vblo=3,649.99 2006.285.16:53:59.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.16:53:59.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.16:53:59.17#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:59.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:53:59.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:53:59.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:53:59.17#ibcon#enter wrdev, iclass 16, count 0 2006.285.16:53:59.17#ibcon#first serial, iclass 16, count 0 2006.285.16:53:59.17#ibcon#enter sib2, iclass 16, count 0 2006.285.16:53:59.17#ibcon#flushed, iclass 16, count 0 2006.285.16:53:59.17#ibcon#about to write, iclass 16, count 0 2006.285.16:53:59.17#ibcon#wrote, iclass 16, count 0 2006.285.16:53:59.17#ibcon#about to read 3, iclass 16, count 0 2006.285.16:53:59.19#ibcon#read 3, iclass 16, count 0 2006.285.16:53:59.19#ibcon#about to read 4, iclass 16, count 0 2006.285.16:53:59.19#ibcon#read 4, iclass 16, count 0 2006.285.16:53:59.19#ibcon#about to read 5, iclass 16, count 0 2006.285.16:53:59.19#ibcon#read 5, iclass 16, count 0 2006.285.16:53:59.19#ibcon#about to read 6, iclass 16, count 0 2006.285.16:53:59.19#ibcon#read 6, iclass 16, count 0 2006.285.16:53:59.19#ibcon#end of sib2, iclass 16, count 0 2006.285.16:53:59.19#ibcon#*mode == 0, iclass 16, count 0 2006.285.16:53:59.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.16:53:59.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.16:53:59.19#ibcon#*before write, iclass 16, count 0 2006.285.16:53:59.19#ibcon#enter sib2, iclass 16, count 0 2006.285.16:53:59.19#ibcon#flushed, iclass 16, count 0 2006.285.16:53:59.19#ibcon#about to write, iclass 16, count 0 2006.285.16:53:59.19#ibcon#wrote, iclass 16, count 0 2006.285.16:53:59.19#ibcon#about to read 3, iclass 16, count 0 2006.285.16:53:59.23#ibcon#read 3, iclass 16, count 0 2006.285.16:53:59.23#ibcon#about to read 4, iclass 16, count 0 2006.285.16:53:59.23#ibcon#read 4, iclass 16, count 0 2006.285.16:53:59.23#ibcon#about to read 5, iclass 16, count 0 2006.285.16:53:59.23#ibcon#read 5, iclass 16, count 0 2006.285.16:53:59.23#ibcon#about to read 6, iclass 16, count 0 2006.285.16:53:59.23#ibcon#read 6, iclass 16, count 0 2006.285.16:53:59.23#ibcon#end of sib2, iclass 16, count 0 2006.285.16:53:59.23#ibcon#*after write, iclass 16, count 0 2006.285.16:53:59.23#ibcon#*before return 0, iclass 16, count 0 2006.285.16:53:59.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:53:59.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.16:53:59.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.16:53:59.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.16:53:59.23$vck44/vb=3,4 2006.285.16:53:59.23#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.16:53:59.23#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.16:53:59.23#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:59.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:53:59.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:53:59.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:53:59.29#ibcon#enter wrdev, iclass 18, count 2 2006.285.16:53:59.29#ibcon#first serial, iclass 18, count 2 2006.285.16:53:59.29#ibcon#enter sib2, iclass 18, count 2 2006.285.16:53:59.29#ibcon#flushed, iclass 18, count 2 2006.285.16:53:59.29#ibcon#about to write, iclass 18, count 2 2006.285.16:53:59.29#ibcon#wrote, iclass 18, count 2 2006.285.16:53:59.29#ibcon#about to read 3, iclass 18, count 2 2006.285.16:53:59.31#ibcon#read 3, iclass 18, count 2 2006.285.16:53:59.31#ibcon#about to read 4, iclass 18, count 2 2006.285.16:53:59.31#ibcon#read 4, iclass 18, count 2 2006.285.16:53:59.31#ibcon#about to read 5, iclass 18, count 2 2006.285.16:53:59.31#ibcon#read 5, iclass 18, count 2 2006.285.16:53:59.31#ibcon#about to read 6, iclass 18, count 2 2006.285.16:53:59.31#ibcon#read 6, iclass 18, count 2 2006.285.16:53:59.31#ibcon#end of sib2, iclass 18, count 2 2006.285.16:53:59.31#ibcon#*mode == 0, iclass 18, count 2 2006.285.16:53:59.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.16:53:59.31#ibcon#[27=AT03-04\r\n] 2006.285.16:53:59.31#ibcon#*before write, iclass 18, count 2 2006.285.16:53:59.31#ibcon#enter sib2, iclass 18, count 2 2006.285.16:53:59.31#ibcon#flushed, iclass 18, count 2 2006.285.16:53:59.31#ibcon#about to write, iclass 18, count 2 2006.285.16:53:59.31#ibcon#wrote, iclass 18, count 2 2006.285.16:53:59.31#ibcon#about to read 3, iclass 18, count 2 2006.285.16:53:59.34#ibcon#read 3, iclass 18, count 2 2006.285.16:53:59.34#ibcon#about to read 4, iclass 18, count 2 2006.285.16:53:59.34#ibcon#read 4, iclass 18, count 2 2006.285.16:53:59.34#ibcon#about to read 5, iclass 18, count 2 2006.285.16:53:59.34#ibcon#read 5, iclass 18, count 2 2006.285.16:53:59.34#ibcon#about to read 6, iclass 18, count 2 2006.285.16:53:59.34#ibcon#read 6, iclass 18, count 2 2006.285.16:53:59.34#ibcon#end of sib2, iclass 18, count 2 2006.285.16:53:59.34#ibcon#*after write, iclass 18, count 2 2006.285.16:53:59.34#ibcon#*before return 0, iclass 18, count 2 2006.285.16:53:59.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:53:59.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.16:53:59.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.16:53:59.34#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:59.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:53:59.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:53:59.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:53:59.46#ibcon#enter wrdev, iclass 18, count 0 2006.285.16:53:59.46#ibcon#first serial, iclass 18, count 0 2006.285.16:53:59.46#ibcon#enter sib2, iclass 18, count 0 2006.285.16:53:59.46#ibcon#flushed, iclass 18, count 0 2006.285.16:53:59.46#ibcon#about to write, iclass 18, count 0 2006.285.16:53:59.46#ibcon#wrote, iclass 18, count 0 2006.285.16:53:59.46#ibcon#about to read 3, iclass 18, count 0 2006.285.16:53:59.48#ibcon#read 3, iclass 18, count 0 2006.285.16:53:59.48#ibcon#about to read 4, iclass 18, count 0 2006.285.16:53:59.48#ibcon#read 4, iclass 18, count 0 2006.285.16:53:59.48#ibcon#about to read 5, iclass 18, count 0 2006.285.16:53:59.48#ibcon#read 5, iclass 18, count 0 2006.285.16:53:59.48#ibcon#about to read 6, iclass 18, count 0 2006.285.16:53:59.48#ibcon#read 6, iclass 18, count 0 2006.285.16:53:59.48#ibcon#end of sib2, iclass 18, count 0 2006.285.16:53:59.48#ibcon#*mode == 0, iclass 18, count 0 2006.285.16:53:59.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.16:53:59.48#ibcon#[27=USB\r\n] 2006.285.16:53:59.48#ibcon#*before write, iclass 18, count 0 2006.285.16:53:59.48#ibcon#enter sib2, iclass 18, count 0 2006.285.16:53:59.48#ibcon#flushed, iclass 18, count 0 2006.285.16:53:59.48#ibcon#about to write, iclass 18, count 0 2006.285.16:53:59.48#ibcon#wrote, iclass 18, count 0 2006.285.16:53:59.48#ibcon#about to read 3, iclass 18, count 0 2006.285.16:53:59.51#ibcon#read 3, iclass 18, count 0 2006.285.16:53:59.51#ibcon#about to read 4, iclass 18, count 0 2006.285.16:53:59.61#ibcon#read 4, iclass 18, count 0 2006.285.16:53:59.61#ibcon#about to read 5, iclass 18, count 0 2006.285.16:53:59.61#ibcon#read 5, iclass 18, count 0 2006.285.16:53:59.61#ibcon#about to read 6, iclass 18, count 0 2006.285.16:53:59.61#ibcon#read 6, iclass 18, count 0 2006.285.16:53:59.61#ibcon#end of sib2, iclass 18, count 0 2006.285.16:53:59.61#ibcon#*after write, iclass 18, count 0 2006.285.16:53:59.61#ibcon#*before return 0, iclass 18, count 0 2006.285.16:53:59.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:53:59.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.16:53:59.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.16:53:59.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.16:53:59.61$vck44/vblo=4,679.99 2006.285.16:53:59.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.16:53:59.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.16:53:59.61#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:59.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:53:59.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:53:59.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:53:59.61#ibcon#enter wrdev, iclass 20, count 0 2006.285.16:53:59.61#ibcon#first serial, iclass 20, count 0 2006.285.16:53:59.61#ibcon#enter sib2, iclass 20, count 0 2006.285.16:53:59.61#ibcon#flushed, iclass 20, count 0 2006.285.16:53:59.61#ibcon#about to write, iclass 20, count 0 2006.285.16:53:59.61#ibcon#wrote, iclass 20, count 0 2006.285.16:53:59.61#ibcon#about to read 3, iclass 20, count 0 2006.285.16:53:59.63#ibcon#read 3, iclass 20, count 0 2006.285.16:53:59.63#ibcon#about to read 4, iclass 20, count 0 2006.285.16:53:59.63#ibcon#read 4, iclass 20, count 0 2006.285.16:53:59.63#ibcon#about to read 5, iclass 20, count 0 2006.285.16:53:59.63#ibcon#read 5, iclass 20, count 0 2006.285.16:53:59.63#ibcon#about to read 6, iclass 20, count 0 2006.285.16:53:59.63#ibcon#read 6, iclass 20, count 0 2006.285.16:53:59.63#ibcon#end of sib2, iclass 20, count 0 2006.285.16:53:59.63#ibcon#*mode == 0, iclass 20, count 0 2006.285.16:53:59.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.16:53:59.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.16:53:59.63#ibcon#*before write, iclass 20, count 0 2006.285.16:53:59.63#ibcon#enter sib2, iclass 20, count 0 2006.285.16:53:59.63#ibcon#flushed, iclass 20, count 0 2006.285.16:53:59.63#ibcon#about to write, iclass 20, count 0 2006.285.16:53:59.63#ibcon#wrote, iclass 20, count 0 2006.285.16:53:59.63#ibcon#about to read 3, iclass 20, count 0 2006.285.16:53:59.67#ibcon#read 3, iclass 20, count 0 2006.285.16:53:59.67#ibcon#about to read 4, iclass 20, count 0 2006.285.16:53:59.67#ibcon#read 4, iclass 20, count 0 2006.285.16:53:59.67#ibcon#about to read 5, iclass 20, count 0 2006.285.16:53:59.67#ibcon#read 5, iclass 20, count 0 2006.285.16:53:59.67#ibcon#about to read 6, iclass 20, count 0 2006.285.16:53:59.67#ibcon#read 6, iclass 20, count 0 2006.285.16:53:59.67#ibcon#end of sib2, iclass 20, count 0 2006.285.16:53:59.67#ibcon#*after write, iclass 20, count 0 2006.285.16:53:59.67#ibcon#*before return 0, iclass 20, count 0 2006.285.16:53:59.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:53:59.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.16:53:59.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.16:53:59.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.16:53:59.67$vck44/vb=4,5 2006.285.16:53:59.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.16:53:59.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.16:53:59.67#ibcon#ireg 11 cls_cnt 2 2006.285.16:53:59.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:53:59.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:53:59.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:53:59.73#ibcon#enter wrdev, iclass 22, count 2 2006.285.16:53:59.73#ibcon#first serial, iclass 22, count 2 2006.285.16:53:59.73#ibcon#enter sib2, iclass 22, count 2 2006.285.16:53:59.73#ibcon#flushed, iclass 22, count 2 2006.285.16:53:59.73#ibcon#about to write, iclass 22, count 2 2006.285.16:53:59.73#ibcon#wrote, iclass 22, count 2 2006.285.16:53:59.73#ibcon#about to read 3, iclass 22, count 2 2006.285.16:53:59.75#ibcon#read 3, iclass 22, count 2 2006.285.16:53:59.75#ibcon#about to read 4, iclass 22, count 2 2006.285.16:53:59.75#ibcon#read 4, iclass 22, count 2 2006.285.16:53:59.75#ibcon#about to read 5, iclass 22, count 2 2006.285.16:53:59.75#ibcon#read 5, iclass 22, count 2 2006.285.16:53:59.75#ibcon#about to read 6, iclass 22, count 2 2006.285.16:53:59.75#ibcon#read 6, iclass 22, count 2 2006.285.16:53:59.75#ibcon#end of sib2, iclass 22, count 2 2006.285.16:53:59.75#ibcon#*mode == 0, iclass 22, count 2 2006.285.16:53:59.75#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.16:53:59.75#ibcon#[27=AT04-05\r\n] 2006.285.16:53:59.75#ibcon#*before write, iclass 22, count 2 2006.285.16:53:59.75#ibcon#enter sib2, iclass 22, count 2 2006.285.16:53:59.75#ibcon#flushed, iclass 22, count 2 2006.285.16:53:59.75#ibcon#about to write, iclass 22, count 2 2006.285.16:53:59.75#ibcon#wrote, iclass 22, count 2 2006.285.16:53:59.75#ibcon#about to read 3, iclass 22, count 2 2006.285.16:53:59.78#ibcon#read 3, iclass 22, count 2 2006.285.16:53:59.78#ibcon#about to read 4, iclass 22, count 2 2006.285.16:53:59.78#ibcon#read 4, iclass 22, count 2 2006.285.16:53:59.78#ibcon#about to read 5, iclass 22, count 2 2006.285.16:53:59.78#ibcon#read 5, iclass 22, count 2 2006.285.16:53:59.78#ibcon#about to read 6, iclass 22, count 2 2006.285.16:53:59.78#ibcon#read 6, iclass 22, count 2 2006.285.16:53:59.78#ibcon#end of sib2, iclass 22, count 2 2006.285.16:53:59.78#ibcon#*after write, iclass 22, count 2 2006.285.16:53:59.78#ibcon#*before return 0, iclass 22, count 2 2006.285.16:53:59.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:53:59.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.16:53:59.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.16:53:59.78#ibcon#ireg 7 cls_cnt 0 2006.285.16:53:59.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:53:59.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:53:59.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:53:59.90#ibcon#enter wrdev, iclass 22, count 0 2006.285.16:53:59.90#ibcon#first serial, iclass 22, count 0 2006.285.16:53:59.90#ibcon#enter sib2, iclass 22, count 0 2006.285.16:53:59.90#ibcon#flushed, iclass 22, count 0 2006.285.16:53:59.90#ibcon#about to write, iclass 22, count 0 2006.285.16:53:59.90#ibcon#wrote, iclass 22, count 0 2006.285.16:53:59.90#ibcon#about to read 3, iclass 22, count 0 2006.285.16:53:59.92#ibcon#read 3, iclass 22, count 0 2006.285.16:53:59.92#ibcon#about to read 4, iclass 22, count 0 2006.285.16:53:59.92#ibcon#read 4, iclass 22, count 0 2006.285.16:53:59.92#ibcon#about to read 5, iclass 22, count 0 2006.285.16:53:59.92#ibcon#read 5, iclass 22, count 0 2006.285.16:53:59.92#ibcon#about to read 6, iclass 22, count 0 2006.285.16:53:59.92#ibcon#read 6, iclass 22, count 0 2006.285.16:53:59.92#ibcon#end of sib2, iclass 22, count 0 2006.285.16:53:59.92#ibcon#*mode == 0, iclass 22, count 0 2006.285.16:53:59.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.16:53:59.92#ibcon#[27=USB\r\n] 2006.285.16:53:59.92#ibcon#*before write, iclass 22, count 0 2006.285.16:53:59.92#ibcon#enter sib2, iclass 22, count 0 2006.285.16:53:59.92#ibcon#flushed, iclass 22, count 0 2006.285.16:53:59.92#ibcon#about to write, iclass 22, count 0 2006.285.16:53:59.92#ibcon#wrote, iclass 22, count 0 2006.285.16:53:59.92#ibcon#about to read 3, iclass 22, count 0 2006.285.16:53:59.95#ibcon#read 3, iclass 22, count 0 2006.285.16:53:59.95#ibcon#about to read 4, iclass 22, count 0 2006.285.16:53:59.95#ibcon#read 4, iclass 22, count 0 2006.285.16:53:59.95#ibcon#about to read 5, iclass 22, count 0 2006.285.16:53:59.95#ibcon#read 5, iclass 22, count 0 2006.285.16:53:59.95#ibcon#about to read 6, iclass 22, count 0 2006.285.16:53:59.95#ibcon#read 6, iclass 22, count 0 2006.285.16:53:59.95#ibcon#end of sib2, iclass 22, count 0 2006.285.16:53:59.95#ibcon#*after write, iclass 22, count 0 2006.285.16:53:59.95#ibcon#*before return 0, iclass 22, count 0 2006.285.16:53:59.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:53:59.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.16:53:59.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.16:53:59.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.16:53:59.95$vck44/vblo=5,709.99 2006.285.16:53:59.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.16:53:59.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.16:53:59.95#ibcon#ireg 17 cls_cnt 0 2006.285.16:53:59.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:53:59.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:53:59.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:53:59.95#ibcon#enter wrdev, iclass 24, count 0 2006.285.16:53:59.95#ibcon#first serial, iclass 24, count 0 2006.285.16:53:59.95#ibcon#enter sib2, iclass 24, count 0 2006.285.16:53:59.95#ibcon#flushed, iclass 24, count 0 2006.285.16:53:59.95#ibcon#about to write, iclass 24, count 0 2006.285.16:53:59.95#ibcon#wrote, iclass 24, count 0 2006.285.16:53:59.95#ibcon#about to read 3, iclass 24, count 0 2006.285.16:53:59.97#ibcon#read 3, iclass 24, count 0 2006.285.16:53:59.97#ibcon#about to read 4, iclass 24, count 0 2006.285.16:53:59.97#ibcon#read 4, iclass 24, count 0 2006.285.16:53:59.97#ibcon#about to read 5, iclass 24, count 0 2006.285.16:53:59.97#ibcon#read 5, iclass 24, count 0 2006.285.16:53:59.97#ibcon#about to read 6, iclass 24, count 0 2006.285.16:53:59.97#ibcon#read 6, iclass 24, count 0 2006.285.16:53:59.97#ibcon#end of sib2, iclass 24, count 0 2006.285.16:53:59.97#ibcon#*mode == 0, iclass 24, count 0 2006.285.16:53:59.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.16:53:59.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.16:53:59.97#ibcon#*before write, iclass 24, count 0 2006.285.16:53:59.97#ibcon#enter sib2, iclass 24, count 0 2006.285.16:53:59.97#ibcon#flushed, iclass 24, count 0 2006.285.16:53:59.97#ibcon#about to write, iclass 24, count 0 2006.285.16:53:59.97#ibcon#wrote, iclass 24, count 0 2006.285.16:53:59.97#ibcon#about to read 3, iclass 24, count 0 2006.285.16:54:00.01#ibcon#read 3, iclass 24, count 0 2006.285.16:54:00.01#ibcon#about to read 4, iclass 24, count 0 2006.285.16:54:00.01#ibcon#read 4, iclass 24, count 0 2006.285.16:54:00.01#ibcon#about to read 5, iclass 24, count 0 2006.285.16:54:00.01#ibcon#read 5, iclass 24, count 0 2006.285.16:54:00.01#ibcon#about to read 6, iclass 24, count 0 2006.285.16:54:00.01#ibcon#read 6, iclass 24, count 0 2006.285.16:54:00.01#ibcon#end of sib2, iclass 24, count 0 2006.285.16:54:00.01#ibcon#*after write, iclass 24, count 0 2006.285.16:54:00.01#ibcon#*before return 0, iclass 24, count 0 2006.285.16:54:00.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:54:00.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.16:54:00.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.16:54:00.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.16:54:00.01$vck44/vb=5,4 2006.285.16:54:00.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.16:54:00.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.16:54:00.01#ibcon#ireg 11 cls_cnt 2 2006.285.16:54:00.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:54:00.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:54:00.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:54:00.07#ibcon#enter wrdev, iclass 26, count 2 2006.285.16:54:00.07#ibcon#first serial, iclass 26, count 2 2006.285.16:54:00.07#ibcon#enter sib2, iclass 26, count 2 2006.285.16:54:00.07#ibcon#flushed, iclass 26, count 2 2006.285.16:54:00.07#ibcon#about to write, iclass 26, count 2 2006.285.16:54:00.07#ibcon#wrote, iclass 26, count 2 2006.285.16:54:00.07#ibcon#about to read 3, iclass 26, count 2 2006.285.16:54:00.09#ibcon#read 3, iclass 26, count 2 2006.285.16:54:00.09#ibcon#about to read 4, iclass 26, count 2 2006.285.16:54:00.09#ibcon#read 4, iclass 26, count 2 2006.285.16:54:00.09#ibcon#about to read 5, iclass 26, count 2 2006.285.16:54:00.09#ibcon#read 5, iclass 26, count 2 2006.285.16:54:00.09#ibcon#about to read 6, iclass 26, count 2 2006.285.16:54:00.09#ibcon#read 6, iclass 26, count 2 2006.285.16:54:00.09#ibcon#end of sib2, iclass 26, count 2 2006.285.16:54:00.09#ibcon#*mode == 0, iclass 26, count 2 2006.285.16:54:00.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.16:54:00.09#ibcon#[27=AT05-04\r\n] 2006.285.16:54:00.09#ibcon#*before write, iclass 26, count 2 2006.285.16:54:00.09#ibcon#enter sib2, iclass 26, count 2 2006.285.16:54:00.09#ibcon#flushed, iclass 26, count 2 2006.285.16:54:00.09#ibcon#about to write, iclass 26, count 2 2006.285.16:54:00.09#ibcon#wrote, iclass 26, count 2 2006.285.16:54:00.09#ibcon#about to read 3, iclass 26, count 2 2006.285.16:54:00.12#ibcon#read 3, iclass 26, count 2 2006.285.16:54:00.12#ibcon#about to read 4, iclass 26, count 2 2006.285.16:54:00.12#ibcon#read 4, iclass 26, count 2 2006.285.16:54:00.12#ibcon#about to read 5, iclass 26, count 2 2006.285.16:54:00.12#ibcon#read 5, iclass 26, count 2 2006.285.16:54:00.12#ibcon#about to read 6, iclass 26, count 2 2006.285.16:54:00.12#ibcon#read 6, iclass 26, count 2 2006.285.16:54:00.12#ibcon#end of sib2, iclass 26, count 2 2006.285.16:54:00.12#ibcon#*after write, iclass 26, count 2 2006.285.16:54:00.12#ibcon#*before return 0, iclass 26, count 2 2006.285.16:54:00.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:54:00.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.16:54:00.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.16:54:00.12#ibcon#ireg 7 cls_cnt 0 2006.285.16:54:00.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:54:00.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:54:00.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:54:00.24#ibcon#enter wrdev, iclass 26, count 0 2006.285.16:54:00.24#ibcon#first serial, iclass 26, count 0 2006.285.16:54:00.24#ibcon#enter sib2, iclass 26, count 0 2006.285.16:54:00.24#ibcon#flushed, iclass 26, count 0 2006.285.16:54:00.24#ibcon#about to write, iclass 26, count 0 2006.285.16:54:00.24#ibcon#wrote, iclass 26, count 0 2006.285.16:54:00.24#ibcon#about to read 3, iclass 26, count 0 2006.285.16:54:00.26#ibcon#read 3, iclass 26, count 0 2006.285.16:54:00.26#ibcon#about to read 4, iclass 26, count 0 2006.285.16:54:00.26#ibcon#read 4, iclass 26, count 0 2006.285.16:54:00.26#ibcon#about to read 5, iclass 26, count 0 2006.285.16:54:00.26#ibcon#read 5, iclass 26, count 0 2006.285.16:54:00.26#ibcon#about to read 6, iclass 26, count 0 2006.285.16:54:00.26#ibcon#read 6, iclass 26, count 0 2006.285.16:54:00.26#ibcon#end of sib2, iclass 26, count 0 2006.285.16:54:00.26#ibcon#*mode == 0, iclass 26, count 0 2006.285.16:54:00.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.16:54:00.26#ibcon#[27=USB\r\n] 2006.285.16:54:00.26#ibcon#*before write, iclass 26, count 0 2006.285.16:54:00.26#ibcon#enter sib2, iclass 26, count 0 2006.285.16:54:00.26#ibcon#flushed, iclass 26, count 0 2006.285.16:54:00.26#ibcon#about to write, iclass 26, count 0 2006.285.16:54:00.26#ibcon#wrote, iclass 26, count 0 2006.285.16:54:00.26#ibcon#about to read 3, iclass 26, count 0 2006.285.16:54:00.29#ibcon#read 3, iclass 26, count 0 2006.285.16:54:00.29#ibcon#about to read 4, iclass 26, count 0 2006.285.16:54:00.29#ibcon#read 4, iclass 26, count 0 2006.285.16:54:00.29#ibcon#about to read 5, iclass 26, count 0 2006.285.16:54:00.29#ibcon#read 5, iclass 26, count 0 2006.285.16:54:00.29#ibcon#about to read 6, iclass 26, count 0 2006.285.16:54:00.29#ibcon#read 6, iclass 26, count 0 2006.285.16:54:00.29#ibcon#end of sib2, iclass 26, count 0 2006.285.16:54:00.29#ibcon#*after write, iclass 26, count 0 2006.285.16:54:00.29#ibcon#*before return 0, iclass 26, count 0 2006.285.16:54:00.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:54:00.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.16:54:00.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.16:54:00.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.16:54:00.29$vck44/vblo=6,719.99 2006.285.16:54:00.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.16:54:00.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.16:54:00.29#ibcon#ireg 17 cls_cnt 0 2006.285.16:54:00.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:54:00.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:54:00.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:54:00.29#ibcon#enter wrdev, iclass 28, count 0 2006.285.16:54:00.29#ibcon#first serial, iclass 28, count 0 2006.285.16:54:00.29#ibcon#enter sib2, iclass 28, count 0 2006.285.16:54:00.29#ibcon#flushed, iclass 28, count 0 2006.285.16:54:00.29#ibcon#about to write, iclass 28, count 0 2006.285.16:54:00.29#ibcon#wrote, iclass 28, count 0 2006.285.16:54:00.29#ibcon#about to read 3, iclass 28, count 0 2006.285.16:54:00.31#ibcon#read 3, iclass 28, count 0 2006.285.16:54:00.31#ibcon#about to read 4, iclass 28, count 0 2006.285.16:54:00.31#ibcon#read 4, iclass 28, count 0 2006.285.16:54:00.31#ibcon#about to read 5, iclass 28, count 0 2006.285.16:54:00.31#ibcon#read 5, iclass 28, count 0 2006.285.16:54:00.31#ibcon#about to read 6, iclass 28, count 0 2006.285.16:54:00.31#ibcon#read 6, iclass 28, count 0 2006.285.16:54:00.31#ibcon#end of sib2, iclass 28, count 0 2006.285.16:54:00.31#ibcon#*mode == 0, iclass 28, count 0 2006.285.16:54:00.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.16:54:00.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.16:54:00.31#ibcon#*before write, iclass 28, count 0 2006.285.16:54:00.31#ibcon#enter sib2, iclass 28, count 0 2006.285.16:54:00.31#ibcon#flushed, iclass 28, count 0 2006.285.16:54:00.31#ibcon#about to write, iclass 28, count 0 2006.285.16:54:00.31#ibcon#wrote, iclass 28, count 0 2006.285.16:54:00.31#ibcon#about to read 3, iclass 28, count 0 2006.285.16:54:00.35#ibcon#read 3, iclass 28, count 0 2006.285.16:54:00.35#ibcon#about to read 4, iclass 28, count 0 2006.285.16:54:00.35#ibcon#read 4, iclass 28, count 0 2006.285.16:54:00.35#ibcon#about to read 5, iclass 28, count 0 2006.285.16:54:00.35#ibcon#read 5, iclass 28, count 0 2006.285.16:54:00.35#ibcon#about to read 6, iclass 28, count 0 2006.285.16:54:00.35#ibcon#read 6, iclass 28, count 0 2006.285.16:54:00.35#ibcon#end of sib2, iclass 28, count 0 2006.285.16:54:00.35#ibcon#*after write, iclass 28, count 0 2006.285.16:54:00.35#ibcon#*before return 0, iclass 28, count 0 2006.285.16:54:00.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:54:00.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.16:54:00.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.16:54:00.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.16:54:00.35$vck44/vb=6,3 2006.285.16:54:00.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.16:54:00.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.16:54:00.35#ibcon#ireg 11 cls_cnt 2 2006.285.16:54:00.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:54:00.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:54:00.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:54:00.41#ibcon#enter wrdev, iclass 30, count 2 2006.285.16:54:00.41#ibcon#first serial, iclass 30, count 2 2006.285.16:54:00.41#ibcon#enter sib2, iclass 30, count 2 2006.285.16:54:00.41#ibcon#flushed, iclass 30, count 2 2006.285.16:54:00.41#ibcon#about to write, iclass 30, count 2 2006.285.16:54:00.41#ibcon#wrote, iclass 30, count 2 2006.285.16:54:00.41#ibcon#about to read 3, iclass 30, count 2 2006.285.16:54:00.43#ibcon#read 3, iclass 30, count 2 2006.285.16:54:00.43#ibcon#about to read 4, iclass 30, count 2 2006.285.16:54:00.43#ibcon#read 4, iclass 30, count 2 2006.285.16:54:00.43#ibcon#about to read 5, iclass 30, count 2 2006.285.16:54:00.43#ibcon#read 5, iclass 30, count 2 2006.285.16:54:00.43#ibcon#about to read 6, iclass 30, count 2 2006.285.16:54:00.43#ibcon#read 6, iclass 30, count 2 2006.285.16:54:00.43#ibcon#end of sib2, iclass 30, count 2 2006.285.16:54:00.43#ibcon#*mode == 0, iclass 30, count 2 2006.285.16:54:00.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.16:54:00.43#ibcon#[27=AT06-03\r\n] 2006.285.16:54:00.43#ibcon#*before write, iclass 30, count 2 2006.285.16:54:00.43#ibcon#enter sib2, iclass 30, count 2 2006.285.16:54:00.43#ibcon#flushed, iclass 30, count 2 2006.285.16:54:00.43#ibcon#about to write, iclass 30, count 2 2006.285.16:54:00.43#ibcon#wrote, iclass 30, count 2 2006.285.16:54:00.43#ibcon#about to read 3, iclass 30, count 2 2006.285.16:54:00.46#ibcon#read 3, iclass 30, count 2 2006.285.16:54:00.52#ibcon#about to read 4, iclass 30, count 2 2006.285.16:54:00.52#ibcon#read 4, iclass 30, count 2 2006.285.16:54:00.52#ibcon#about to read 5, iclass 30, count 2 2006.285.16:54:00.52#ibcon#read 5, iclass 30, count 2 2006.285.16:54:00.52#ibcon#about to read 6, iclass 30, count 2 2006.285.16:54:00.52#ibcon#read 6, iclass 30, count 2 2006.285.16:54:00.52#ibcon#end of sib2, iclass 30, count 2 2006.285.16:54:00.52#ibcon#*after write, iclass 30, count 2 2006.285.16:54:00.52#ibcon#*before return 0, iclass 30, count 2 2006.285.16:54:00.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:54:00.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.16:54:00.52#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.16:54:00.52#ibcon#ireg 7 cls_cnt 0 2006.285.16:54:00.52#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:54:00.64#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:54:00.64#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:54:00.64#ibcon#enter wrdev, iclass 30, count 0 2006.285.16:54:00.64#ibcon#first serial, iclass 30, count 0 2006.285.16:54:00.64#ibcon#enter sib2, iclass 30, count 0 2006.285.16:54:00.64#ibcon#flushed, iclass 30, count 0 2006.285.16:54:00.64#ibcon#about to write, iclass 30, count 0 2006.285.16:54:00.64#ibcon#wrote, iclass 30, count 0 2006.285.16:54:00.64#ibcon#about to read 3, iclass 30, count 0 2006.285.16:54:00.66#ibcon#read 3, iclass 30, count 0 2006.285.16:54:00.66#ibcon#about to read 4, iclass 30, count 0 2006.285.16:54:00.66#ibcon#read 4, iclass 30, count 0 2006.285.16:54:00.66#ibcon#about to read 5, iclass 30, count 0 2006.285.16:54:00.66#ibcon#read 5, iclass 30, count 0 2006.285.16:54:00.66#ibcon#about to read 6, iclass 30, count 0 2006.285.16:54:00.66#ibcon#read 6, iclass 30, count 0 2006.285.16:54:00.66#ibcon#end of sib2, iclass 30, count 0 2006.285.16:54:00.66#ibcon#*mode == 0, iclass 30, count 0 2006.285.16:54:00.66#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.16:54:00.66#ibcon#[27=USB\r\n] 2006.285.16:54:00.66#ibcon#*before write, iclass 30, count 0 2006.285.16:54:00.66#ibcon#enter sib2, iclass 30, count 0 2006.285.16:54:00.66#ibcon#flushed, iclass 30, count 0 2006.285.16:54:00.66#ibcon#about to write, iclass 30, count 0 2006.285.16:54:00.66#ibcon#wrote, iclass 30, count 0 2006.285.16:54:00.66#ibcon#about to read 3, iclass 30, count 0 2006.285.16:54:00.69#ibcon#read 3, iclass 30, count 0 2006.285.16:54:00.69#ibcon#about to read 4, iclass 30, count 0 2006.285.16:54:00.69#ibcon#read 4, iclass 30, count 0 2006.285.16:54:00.69#ibcon#about to read 5, iclass 30, count 0 2006.285.16:54:00.69#ibcon#read 5, iclass 30, count 0 2006.285.16:54:00.69#ibcon#about to read 6, iclass 30, count 0 2006.285.16:54:00.69#ibcon#read 6, iclass 30, count 0 2006.285.16:54:00.69#ibcon#end of sib2, iclass 30, count 0 2006.285.16:54:00.69#ibcon#*after write, iclass 30, count 0 2006.285.16:54:00.69#ibcon#*before return 0, iclass 30, count 0 2006.285.16:54:00.69#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:54:00.69#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.16:54:00.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.16:54:00.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.16:54:00.69$vck44/vblo=7,734.99 2006.285.16:54:00.69#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.16:54:00.69#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.16:54:00.69#ibcon#ireg 17 cls_cnt 0 2006.285.16:54:00.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:54:00.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:54:00.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:54:00.69#ibcon#enter wrdev, iclass 32, count 0 2006.285.16:54:00.69#ibcon#first serial, iclass 32, count 0 2006.285.16:54:00.69#ibcon#enter sib2, iclass 32, count 0 2006.285.16:54:00.69#ibcon#flushed, iclass 32, count 0 2006.285.16:54:00.69#ibcon#about to write, iclass 32, count 0 2006.285.16:54:00.69#ibcon#wrote, iclass 32, count 0 2006.285.16:54:00.69#ibcon#about to read 3, iclass 32, count 0 2006.285.16:54:00.71#ibcon#read 3, iclass 32, count 0 2006.285.16:54:00.71#ibcon#about to read 4, iclass 32, count 0 2006.285.16:54:00.71#ibcon#read 4, iclass 32, count 0 2006.285.16:54:00.71#ibcon#about to read 5, iclass 32, count 0 2006.285.16:54:00.71#ibcon#read 5, iclass 32, count 0 2006.285.16:54:00.71#ibcon#about to read 6, iclass 32, count 0 2006.285.16:54:00.71#ibcon#read 6, iclass 32, count 0 2006.285.16:54:00.71#ibcon#end of sib2, iclass 32, count 0 2006.285.16:54:00.71#ibcon#*mode == 0, iclass 32, count 0 2006.285.16:54:00.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.16:54:00.71#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.16:54:00.71#ibcon#*before write, iclass 32, count 0 2006.285.16:54:00.71#ibcon#enter sib2, iclass 32, count 0 2006.285.16:54:00.71#ibcon#flushed, iclass 32, count 0 2006.285.16:54:00.71#ibcon#about to write, iclass 32, count 0 2006.285.16:54:00.71#ibcon#wrote, iclass 32, count 0 2006.285.16:54:00.71#ibcon#about to read 3, iclass 32, count 0 2006.285.16:54:00.75#ibcon#read 3, iclass 32, count 0 2006.285.16:54:00.75#ibcon#about to read 4, iclass 32, count 0 2006.285.16:54:00.75#ibcon#read 4, iclass 32, count 0 2006.285.16:54:00.75#ibcon#about to read 5, iclass 32, count 0 2006.285.16:54:00.75#ibcon#read 5, iclass 32, count 0 2006.285.16:54:00.75#ibcon#about to read 6, iclass 32, count 0 2006.285.16:54:00.75#ibcon#read 6, iclass 32, count 0 2006.285.16:54:00.75#ibcon#end of sib2, iclass 32, count 0 2006.285.16:54:00.75#ibcon#*after write, iclass 32, count 0 2006.285.16:54:00.75#ibcon#*before return 0, iclass 32, count 0 2006.285.16:54:00.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:54:00.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.16:54:00.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.16:54:00.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.16:54:00.75$vck44/vb=7,4 2006.285.16:54:00.75#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.16:54:00.75#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.16:54:00.75#ibcon#ireg 11 cls_cnt 2 2006.285.16:54:00.75#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:54:00.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:54:00.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:54:00.81#ibcon#enter wrdev, iclass 34, count 2 2006.285.16:54:00.81#ibcon#first serial, iclass 34, count 2 2006.285.16:54:00.81#ibcon#enter sib2, iclass 34, count 2 2006.285.16:54:00.81#ibcon#flushed, iclass 34, count 2 2006.285.16:54:00.81#ibcon#about to write, iclass 34, count 2 2006.285.16:54:00.81#ibcon#wrote, iclass 34, count 2 2006.285.16:54:00.81#ibcon#about to read 3, iclass 34, count 2 2006.285.16:54:00.83#ibcon#read 3, iclass 34, count 2 2006.285.16:54:00.83#ibcon#about to read 4, iclass 34, count 2 2006.285.16:54:00.83#ibcon#read 4, iclass 34, count 2 2006.285.16:54:00.83#ibcon#about to read 5, iclass 34, count 2 2006.285.16:54:00.83#ibcon#read 5, iclass 34, count 2 2006.285.16:54:00.83#ibcon#about to read 6, iclass 34, count 2 2006.285.16:54:00.83#ibcon#read 6, iclass 34, count 2 2006.285.16:54:00.83#ibcon#end of sib2, iclass 34, count 2 2006.285.16:54:00.83#ibcon#*mode == 0, iclass 34, count 2 2006.285.16:54:00.83#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.16:54:00.83#ibcon#[27=AT07-04\r\n] 2006.285.16:54:00.83#ibcon#*before write, iclass 34, count 2 2006.285.16:54:00.83#ibcon#enter sib2, iclass 34, count 2 2006.285.16:54:00.83#ibcon#flushed, iclass 34, count 2 2006.285.16:54:00.83#ibcon#about to write, iclass 34, count 2 2006.285.16:54:00.83#ibcon#wrote, iclass 34, count 2 2006.285.16:54:00.83#ibcon#about to read 3, iclass 34, count 2 2006.285.16:54:00.86#ibcon#read 3, iclass 34, count 2 2006.285.16:54:00.86#ibcon#about to read 4, iclass 34, count 2 2006.285.16:54:00.86#ibcon#read 4, iclass 34, count 2 2006.285.16:54:00.86#ibcon#about to read 5, iclass 34, count 2 2006.285.16:54:00.86#ibcon#read 5, iclass 34, count 2 2006.285.16:54:00.86#ibcon#about to read 6, iclass 34, count 2 2006.285.16:54:00.86#ibcon#read 6, iclass 34, count 2 2006.285.16:54:00.86#ibcon#end of sib2, iclass 34, count 2 2006.285.16:54:00.86#ibcon#*after write, iclass 34, count 2 2006.285.16:54:00.86#ibcon#*before return 0, iclass 34, count 2 2006.285.16:54:00.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:54:00.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.16:54:00.86#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.16:54:00.86#ibcon#ireg 7 cls_cnt 0 2006.285.16:54:00.86#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:54:00.98#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:54:00.98#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:54:00.98#ibcon#enter wrdev, iclass 34, count 0 2006.285.16:54:00.98#ibcon#first serial, iclass 34, count 0 2006.285.16:54:00.98#ibcon#enter sib2, iclass 34, count 0 2006.285.16:54:00.98#ibcon#flushed, iclass 34, count 0 2006.285.16:54:00.98#ibcon#about to write, iclass 34, count 0 2006.285.16:54:00.98#ibcon#wrote, iclass 34, count 0 2006.285.16:54:00.98#ibcon#about to read 3, iclass 34, count 0 2006.285.16:54:01.00#ibcon#read 3, iclass 34, count 0 2006.285.16:54:01.00#ibcon#about to read 4, iclass 34, count 0 2006.285.16:54:01.00#ibcon#read 4, iclass 34, count 0 2006.285.16:54:01.00#ibcon#about to read 5, iclass 34, count 0 2006.285.16:54:01.00#ibcon#read 5, iclass 34, count 0 2006.285.16:54:01.00#ibcon#about to read 6, iclass 34, count 0 2006.285.16:54:01.00#ibcon#read 6, iclass 34, count 0 2006.285.16:54:01.00#ibcon#end of sib2, iclass 34, count 0 2006.285.16:54:01.00#ibcon#*mode == 0, iclass 34, count 0 2006.285.16:54:01.00#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.16:54:01.00#ibcon#[27=USB\r\n] 2006.285.16:54:01.00#ibcon#*before write, iclass 34, count 0 2006.285.16:54:01.00#ibcon#enter sib2, iclass 34, count 0 2006.285.16:54:01.00#ibcon#flushed, iclass 34, count 0 2006.285.16:54:01.00#ibcon#about to write, iclass 34, count 0 2006.285.16:54:01.00#ibcon#wrote, iclass 34, count 0 2006.285.16:54:01.00#ibcon#about to read 3, iclass 34, count 0 2006.285.16:54:01.03#ibcon#read 3, iclass 34, count 0 2006.285.16:54:01.03#ibcon#about to read 4, iclass 34, count 0 2006.285.16:54:01.03#ibcon#read 4, iclass 34, count 0 2006.285.16:54:01.03#ibcon#about to read 5, iclass 34, count 0 2006.285.16:54:01.03#ibcon#read 5, iclass 34, count 0 2006.285.16:54:01.03#ibcon#about to read 6, iclass 34, count 0 2006.285.16:54:01.03#ibcon#read 6, iclass 34, count 0 2006.285.16:54:01.03#ibcon#end of sib2, iclass 34, count 0 2006.285.16:54:01.03#ibcon#*after write, iclass 34, count 0 2006.285.16:54:01.03#ibcon#*before return 0, iclass 34, count 0 2006.285.16:54:01.03#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:54:01.03#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.16:54:01.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.16:54:01.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.16:54:01.03$vck44/vblo=8,744.99 2006.285.16:54:01.03#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.16:54:01.03#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.16:54:01.03#ibcon#ireg 17 cls_cnt 0 2006.285.16:54:01.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:54:01.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:54:01.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:54:01.03#ibcon#enter wrdev, iclass 36, count 0 2006.285.16:54:01.03#ibcon#first serial, iclass 36, count 0 2006.285.16:54:01.03#ibcon#enter sib2, iclass 36, count 0 2006.285.16:54:01.03#ibcon#flushed, iclass 36, count 0 2006.285.16:54:01.03#ibcon#about to write, iclass 36, count 0 2006.285.16:54:01.03#ibcon#wrote, iclass 36, count 0 2006.285.16:54:01.03#ibcon#about to read 3, iclass 36, count 0 2006.285.16:54:01.05#ibcon#read 3, iclass 36, count 0 2006.285.16:54:01.05#ibcon#about to read 4, iclass 36, count 0 2006.285.16:54:01.05#ibcon#read 4, iclass 36, count 0 2006.285.16:54:01.05#ibcon#about to read 5, iclass 36, count 0 2006.285.16:54:01.05#ibcon#read 5, iclass 36, count 0 2006.285.16:54:01.05#ibcon#about to read 6, iclass 36, count 0 2006.285.16:54:01.05#ibcon#read 6, iclass 36, count 0 2006.285.16:54:01.05#ibcon#end of sib2, iclass 36, count 0 2006.285.16:54:01.05#ibcon#*mode == 0, iclass 36, count 0 2006.285.16:54:01.05#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.16:54:01.05#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.16:54:01.05#ibcon#*before write, iclass 36, count 0 2006.285.16:54:01.05#ibcon#enter sib2, iclass 36, count 0 2006.285.16:54:01.05#ibcon#flushed, iclass 36, count 0 2006.285.16:54:01.05#ibcon#about to write, iclass 36, count 0 2006.285.16:54:01.05#ibcon#wrote, iclass 36, count 0 2006.285.16:54:01.05#ibcon#about to read 3, iclass 36, count 0 2006.285.16:54:01.09#ibcon#read 3, iclass 36, count 0 2006.285.16:54:01.09#ibcon#about to read 4, iclass 36, count 0 2006.285.16:54:01.09#ibcon#read 4, iclass 36, count 0 2006.285.16:54:01.09#ibcon#about to read 5, iclass 36, count 0 2006.285.16:54:01.09#ibcon#read 5, iclass 36, count 0 2006.285.16:54:01.09#ibcon#about to read 6, iclass 36, count 0 2006.285.16:54:01.09#ibcon#read 6, iclass 36, count 0 2006.285.16:54:01.09#ibcon#end of sib2, iclass 36, count 0 2006.285.16:54:01.09#ibcon#*after write, iclass 36, count 0 2006.285.16:54:01.09#ibcon#*before return 0, iclass 36, count 0 2006.285.16:54:01.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:54:01.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.16:54:01.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.16:54:01.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.16:54:01.09$vck44/vb=8,4 2006.285.16:54:01.09#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.16:54:01.09#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.16:54:01.09#ibcon#ireg 11 cls_cnt 2 2006.285.16:54:01.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:54:01.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:54:01.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:54:01.15#ibcon#enter wrdev, iclass 38, count 2 2006.285.16:54:01.15#ibcon#first serial, iclass 38, count 2 2006.285.16:54:01.15#ibcon#enter sib2, iclass 38, count 2 2006.285.16:54:01.15#ibcon#flushed, iclass 38, count 2 2006.285.16:54:01.15#ibcon#about to write, iclass 38, count 2 2006.285.16:54:01.15#ibcon#wrote, iclass 38, count 2 2006.285.16:54:01.15#ibcon#about to read 3, iclass 38, count 2 2006.285.16:54:01.17#ibcon#read 3, iclass 38, count 2 2006.285.16:54:01.17#ibcon#about to read 4, iclass 38, count 2 2006.285.16:54:01.17#ibcon#read 4, iclass 38, count 2 2006.285.16:54:01.17#ibcon#about to read 5, iclass 38, count 2 2006.285.16:54:01.17#ibcon#read 5, iclass 38, count 2 2006.285.16:54:01.17#ibcon#about to read 6, iclass 38, count 2 2006.285.16:54:01.17#ibcon#read 6, iclass 38, count 2 2006.285.16:54:01.17#ibcon#end of sib2, iclass 38, count 2 2006.285.16:54:01.17#ibcon#*mode == 0, iclass 38, count 2 2006.285.16:54:01.17#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.16:54:01.17#ibcon#[27=AT08-04\r\n] 2006.285.16:54:01.17#ibcon#*before write, iclass 38, count 2 2006.285.16:54:01.17#ibcon#enter sib2, iclass 38, count 2 2006.285.16:54:01.17#ibcon#flushed, iclass 38, count 2 2006.285.16:54:01.17#ibcon#about to write, iclass 38, count 2 2006.285.16:54:01.17#ibcon#wrote, iclass 38, count 2 2006.285.16:54:01.17#ibcon#about to read 3, iclass 38, count 2 2006.285.16:54:01.20#ibcon#read 3, iclass 38, count 2 2006.285.16:54:01.20#ibcon#about to read 4, iclass 38, count 2 2006.285.16:54:01.20#ibcon#read 4, iclass 38, count 2 2006.285.16:54:01.20#ibcon#about to read 5, iclass 38, count 2 2006.285.16:54:01.20#ibcon#read 5, iclass 38, count 2 2006.285.16:54:01.20#ibcon#about to read 6, iclass 38, count 2 2006.285.16:54:01.20#ibcon#read 6, iclass 38, count 2 2006.285.16:54:01.20#ibcon#end of sib2, iclass 38, count 2 2006.285.16:54:01.20#ibcon#*after write, iclass 38, count 2 2006.285.16:54:01.20#ibcon#*before return 0, iclass 38, count 2 2006.285.16:54:01.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:54:01.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.16:54:01.20#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.16:54:01.20#ibcon#ireg 7 cls_cnt 0 2006.285.16:54:01.20#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:54:01.32#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:54:01.32#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:54:01.32#ibcon#enter wrdev, iclass 38, count 0 2006.285.16:54:01.32#ibcon#first serial, iclass 38, count 0 2006.285.16:54:01.32#ibcon#enter sib2, iclass 38, count 0 2006.285.16:54:01.32#ibcon#flushed, iclass 38, count 0 2006.285.16:54:01.32#ibcon#about to write, iclass 38, count 0 2006.285.16:54:01.32#ibcon#wrote, iclass 38, count 0 2006.285.16:54:01.32#ibcon#about to read 3, iclass 38, count 0 2006.285.16:54:01.34#ibcon#read 3, iclass 38, count 0 2006.285.16:54:01.34#ibcon#about to read 4, iclass 38, count 0 2006.285.16:54:01.34#ibcon#read 4, iclass 38, count 0 2006.285.16:54:01.34#ibcon#about to read 5, iclass 38, count 0 2006.285.16:54:01.34#ibcon#read 5, iclass 38, count 0 2006.285.16:54:01.34#ibcon#about to read 6, iclass 38, count 0 2006.285.16:54:01.34#ibcon#read 6, iclass 38, count 0 2006.285.16:54:01.34#ibcon#end of sib2, iclass 38, count 0 2006.285.16:54:01.34#ibcon#*mode == 0, iclass 38, count 0 2006.285.16:54:01.34#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.16:54:01.34#ibcon#[27=USB\r\n] 2006.285.16:54:01.34#ibcon#*before write, iclass 38, count 0 2006.285.16:54:01.34#ibcon#enter sib2, iclass 38, count 0 2006.285.16:54:01.34#ibcon#flushed, iclass 38, count 0 2006.285.16:54:01.34#ibcon#about to write, iclass 38, count 0 2006.285.16:54:01.34#ibcon#wrote, iclass 38, count 0 2006.285.16:54:01.34#ibcon#about to read 3, iclass 38, count 0 2006.285.16:54:01.37#ibcon#read 3, iclass 38, count 0 2006.285.16:54:01.37#ibcon#about to read 4, iclass 38, count 0 2006.285.16:54:01.37#ibcon#read 4, iclass 38, count 0 2006.285.16:54:01.37#ibcon#about to read 5, iclass 38, count 0 2006.285.16:54:01.37#ibcon#read 5, iclass 38, count 0 2006.285.16:54:01.37#ibcon#about to read 6, iclass 38, count 0 2006.285.16:54:01.37#ibcon#read 6, iclass 38, count 0 2006.285.16:54:01.37#ibcon#end of sib2, iclass 38, count 0 2006.285.16:54:01.37#ibcon#*after write, iclass 38, count 0 2006.285.16:54:01.37#ibcon#*before return 0, iclass 38, count 0 2006.285.16:54:01.37#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:54:01.37#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.16:54:01.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.16:54:01.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.16:54:01.37$vck44/vabw=wide 2006.285.16:54:01.37#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.16:54:01.37#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.16:54:01.37#ibcon#ireg 8 cls_cnt 0 2006.285.16:54:01.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:54:01.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:54:01.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:54:01.37#ibcon#enter wrdev, iclass 40, count 0 2006.285.16:54:01.37#ibcon#first serial, iclass 40, count 0 2006.285.16:54:01.37#ibcon#enter sib2, iclass 40, count 0 2006.285.16:54:01.37#ibcon#flushed, iclass 40, count 0 2006.285.16:54:01.37#ibcon#about to write, iclass 40, count 0 2006.285.16:54:01.37#ibcon#wrote, iclass 40, count 0 2006.285.16:54:01.37#ibcon#about to read 3, iclass 40, count 0 2006.285.16:54:01.39#ibcon#read 3, iclass 40, count 0 2006.285.16:54:01.39#ibcon#about to read 4, iclass 40, count 0 2006.285.16:54:01.39#ibcon#read 4, iclass 40, count 0 2006.285.16:54:01.39#ibcon#about to read 5, iclass 40, count 0 2006.285.16:54:01.39#ibcon#read 5, iclass 40, count 0 2006.285.16:54:01.39#ibcon#about to read 6, iclass 40, count 0 2006.285.16:54:01.39#ibcon#read 6, iclass 40, count 0 2006.285.16:54:01.39#ibcon#end of sib2, iclass 40, count 0 2006.285.16:54:01.39#ibcon#*mode == 0, iclass 40, count 0 2006.285.16:54:01.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.16:54:01.39#ibcon#[25=BW32\r\n] 2006.285.16:54:01.39#ibcon#*before write, iclass 40, count 0 2006.285.16:54:01.39#ibcon#enter sib2, iclass 40, count 0 2006.285.16:54:01.39#ibcon#flushed, iclass 40, count 0 2006.285.16:54:01.39#ibcon#about to write, iclass 40, count 0 2006.285.16:54:01.39#ibcon#wrote, iclass 40, count 0 2006.285.16:54:01.39#ibcon#about to read 3, iclass 40, count 0 2006.285.16:54:01.42#ibcon#read 3, iclass 40, count 0 2006.285.16:54:01.42#ibcon#about to read 4, iclass 40, count 0 2006.285.16:54:01.42#ibcon#read 4, iclass 40, count 0 2006.285.16:54:01.42#ibcon#about to read 5, iclass 40, count 0 2006.285.16:54:01.42#ibcon#read 5, iclass 40, count 0 2006.285.16:54:01.42#ibcon#about to read 6, iclass 40, count 0 2006.285.16:54:01.42#ibcon#read 6, iclass 40, count 0 2006.285.16:54:01.42#ibcon#end of sib2, iclass 40, count 0 2006.285.16:54:01.42#ibcon#*after write, iclass 40, count 0 2006.285.16:54:01.42#ibcon#*before return 0, iclass 40, count 0 2006.285.16:54:01.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:54:01.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.16:54:01.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.16:54:01.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.16:54:01.42$vck44/vbbw=wide 2006.285.16:54:01.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.16:54:01.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.16:54:01.53#ibcon#ireg 8 cls_cnt 0 2006.285.16:54:01.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:54:01.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:54:01.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:54:01.53#ibcon#enter wrdev, iclass 4, count 0 2006.285.16:54:01.53#ibcon#first serial, iclass 4, count 0 2006.285.16:54:01.53#ibcon#enter sib2, iclass 4, count 0 2006.285.16:54:01.53#ibcon#flushed, iclass 4, count 0 2006.285.16:54:01.53#ibcon#about to write, iclass 4, count 0 2006.285.16:54:01.53#ibcon#wrote, iclass 4, count 0 2006.285.16:54:01.53#ibcon#about to read 3, iclass 4, count 0 2006.285.16:54:01.55#ibcon#read 3, iclass 4, count 0 2006.285.16:54:01.55#ibcon#about to read 4, iclass 4, count 0 2006.285.16:54:01.55#ibcon#read 4, iclass 4, count 0 2006.285.16:54:01.55#ibcon#about to read 5, iclass 4, count 0 2006.285.16:54:01.55#ibcon#read 5, iclass 4, count 0 2006.285.16:54:01.55#ibcon#about to read 6, iclass 4, count 0 2006.285.16:54:01.55#ibcon#read 6, iclass 4, count 0 2006.285.16:54:01.55#ibcon#end of sib2, iclass 4, count 0 2006.285.16:54:01.55#ibcon#*mode == 0, iclass 4, count 0 2006.285.16:54:01.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.16:54:01.55#ibcon#[27=BW32\r\n] 2006.285.16:54:01.55#ibcon#*before write, iclass 4, count 0 2006.285.16:54:01.55#ibcon#enter sib2, iclass 4, count 0 2006.285.16:54:01.55#ibcon#flushed, iclass 4, count 0 2006.285.16:54:01.55#ibcon#about to write, iclass 4, count 0 2006.285.16:54:01.55#ibcon#wrote, iclass 4, count 0 2006.285.16:54:01.55#ibcon#about to read 3, iclass 4, count 0 2006.285.16:54:01.58#ibcon#read 3, iclass 4, count 0 2006.285.16:54:01.58#ibcon#about to read 4, iclass 4, count 0 2006.285.16:54:01.58#ibcon#read 4, iclass 4, count 0 2006.285.16:54:01.58#ibcon#about to read 5, iclass 4, count 0 2006.285.16:54:01.58#ibcon#read 5, iclass 4, count 0 2006.285.16:54:01.58#ibcon#about to read 6, iclass 4, count 0 2006.285.16:54:01.58#ibcon#read 6, iclass 4, count 0 2006.285.16:54:01.58#ibcon#end of sib2, iclass 4, count 0 2006.285.16:54:01.58#ibcon#*after write, iclass 4, count 0 2006.285.16:54:01.58#ibcon#*before return 0, iclass 4, count 0 2006.285.16:54:01.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:54:01.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.16:54:01.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.16:54:01.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.16:54:01.58$setupk4/ifdk4 2006.285.16:54:01.58$ifdk4/lo= 2006.285.16:54:01.58$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.16:54:01.58$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.16:54:01.58$ifdk4/patch= 2006.285.16:54:01.58$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.16:54:01.58$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.16:54:01.58$setupk4/!*+20s 2006.285.16:54:02.76#abcon#<5=/14 0.7 1.8 18.00 941014.9\r\n> 2006.285.16:54:02.78#abcon#{5=INTERFACE CLEAR} 2006.285.16:54:02.84#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:54:12.93#abcon#<5=/14 0.6 1.8 17.99 941014.9\r\n> 2006.285.16:54:12.95#abcon#{5=INTERFACE CLEAR} 2006.285.16:54:13.01#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:54:15.13#trakl#Source acquired 2006.285.16:54:15.40$setupk4/"tpicd 2006.285.16:54:15.40$setupk4/echo=off 2006.285.16:54:15.40$setupk4/xlog=off 2006.285.16:54:15.40:!2006.285.16:56:20 2006.285.16:54:17.13#flagr#flagr/antenna,acquired 2006.285.16:56:20.00:preob 2006.285.16:56:21.14/onsource/TRACKING 2006.285.16:56:21.14:!2006.285.16:56:30 2006.285.16:56:30.00:"tape 2006.285.16:56:30.00:"st=record 2006.285.16:56:30.00:data_valid=on 2006.285.16:56:30.00:midob 2006.285.16:56:30.14/onsource/TRACKING 2006.285.16:56:30.14/wx/17.88,1014.9,95 2006.285.16:56:30.35/cable/+6.5023E-03 2006.285.16:56:31.44/va/01,07,usb,yes,40,43 2006.285.16:56:31.44/va/02,06,usb,yes,40,40 2006.285.16:56:31.44/va/03,07,usb,yes,39,42 2006.285.16:56:31.44/va/04,06,usb,yes,41,43 2006.285.16:56:31.44/va/05,03,usb,yes,41,41 2006.285.16:56:31.44/va/06,04,usb,yes,37,36 2006.285.16:56:31.44/va/07,04,usb,yes,37,38 2006.285.16:56:31.44/va/08,03,usb,yes,38,46 2006.285.16:56:31.67/valo/01,524.99,yes,locked 2006.285.16:56:31.67/valo/02,534.99,yes,locked 2006.285.16:56:31.67/valo/03,564.99,yes,locked 2006.285.16:56:31.67/valo/04,624.99,yes,locked 2006.285.16:56:31.67/valo/05,734.99,yes,locked 2006.285.16:56:31.67/valo/06,814.99,yes,locked 2006.285.16:56:31.67/valo/07,864.99,yes,locked 2006.285.16:56:31.67/valo/08,884.99,yes,locked 2006.285.16:56:32.76/vb/01,04,usb,yes,33,31 2006.285.16:56:32.76/vb/02,05,usb,yes,31,31 2006.285.16:56:32.76/vb/03,04,usb,yes,32,36 2006.285.16:56:32.76/vb/04,05,usb,yes,33,31 2006.285.16:56:32.76/vb/05,04,usb,yes,29,32 2006.285.16:56:32.76/vb/06,03,usb,yes,41,37 2006.285.16:56:32.76/vb/07,04,usb,yes,33,33 2006.285.16:56:32.76/vb/08,04,usb,yes,30,34 2006.285.16:56:33.00/vblo/01,629.99,yes,locked 2006.285.16:56:33.00/vblo/02,634.99,yes,locked 2006.285.16:56:33.00/vblo/03,649.99,yes,locked 2006.285.16:56:33.00/vblo/04,679.99,yes,locked 2006.285.16:56:33.00/vblo/05,709.99,yes,locked 2006.285.16:56:33.00/vblo/06,719.99,yes,locked 2006.285.16:56:33.00/vblo/07,734.99,yes,locked 2006.285.16:56:33.00/vblo/08,744.99,yes,locked 2006.285.16:56:33.15/vabw/8 2006.285.16:56:33.30/vbbw/8 2006.285.16:56:33.40/xfe/off,on,12.2 2006.285.16:56:33.77/ifatt/23,28,28,28 2006.285.16:56:34.08/fmout-gps/S +2.68E-07 2006.285.16:56:34.10:!2006.285.16:57:10 2006.285.16:57:10.01:data_valid=off 2006.285.16:57:10.01:"et 2006.285.16:57:10.01:!+3s 2006.285.16:57:13.02:"tape 2006.285.16:57:13.02:postob 2006.285.16:57:13.22/cable/+6.5018E-03 2006.285.16:57:13.22/wx/17.84,1014.9,95 2006.285.16:57:14.08/fmout-gps/S +2.68E-07 2006.285.16:57:14.08:scan_name=285-1657,jd0610,190 2006.285.16:57:14.08:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.285.16:57:15.14#flagr#flagr/antenna,new-source 2006.285.16:57:15.14:checkk5 2006.285.16:57:15.65/chk_autoobs//k5ts1/ autoobs is running! 2006.285.16:57:16.23/chk_autoobs//k5ts2/ autoobs is running! 2006.285.16:57:16.66/chk_autoobs//k5ts3/ autoobs is running! 2006.285.16:57:17.01/chk_autoobs//k5ts4/ autoobs is running! 2006.285.16:57:17.40/chk_obsdata//k5ts1/T2851656??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.16:57:17.81/chk_obsdata//k5ts2/T2851656??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.16:57:18.23/chk_obsdata//k5ts3/T2851656??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.16:57:18.74/chk_obsdata//k5ts4/T2851656??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.16:57:19.84/k5log//k5ts1_log_newline 2006.285.16:57:21.02/k5log//k5ts2_log_newline 2006.285.16:57:22.10/k5log//k5ts3_log_newline 2006.285.16:57:22.87/k5log//k5ts4_log_newline 2006.285.16:57:22.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.16:57:22.89:setupk4=1 2006.285.16:57:22.89$setupk4/echo=on 2006.285.16:57:22.89$setupk4/pcalon 2006.285.16:57:22.89$pcalon/"no phase cal control is implemented here 2006.285.16:57:22.89$setupk4/"tpicd=stop 2006.285.16:57:22.89$setupk4/"rec=synch_on 2006.285.16:57:22.89$setupk4/"rec_mode=128 2006.285.16:57:22.89$setupk4/!* 2006.285.16:57:22.89$setupk4/recpk4 2006.285.16:57:22.89$recpk4/recpatch= 2006.285.16:57:22.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.16:57:22.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.16:57:22.90$setupk4/vck44 2006.285.16:57:22.90$vck44/valo=1,524.99 2006.285.16:57:22.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.16:57:22.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.16:57:22.90#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:22.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:57:22.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:57:22.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:57:22.90#ibcon#enter wrdev, iclass 19, count 0 2006.285.16:57:22.90#ibcon#first serial, iclass 19, count 0 2006.285.16:57:22.90#ibcon#enter sib2, iclass 19, count 0 2006.285.16:57:22.90#ibcon#flushed, iclass 19, count 0 2006.285.16:57:22.90#ibcon#about to write, iclass 19, count 0 2006.285.16:57:22.90#ibcon#wrote, iclass 19, count 0 2006.285.16:57:22.90#ibcon#about to read 3, iclass 19, count 0 2006.285.16:57:22.92#ibcon#read 3, iclass 19, count 0 2006.285.16:57:22.92#ibcon#about to read 4, iclass 19, count 0 2006.285.16:57:22.92#ibcon#read 4, iclass 19, count 0 2006.285.16:57:22.92#ibcon#about to read 5, iclass 19, count 0 2006.285.16:57:22.92#ibcon#read 5, iclass 19, count 0 2006.285.16:57:22.92#ibcon#about to read 6, iclass 19, count 0 2006.285.16:57:22.92#ibcon#read 6, iclass 19, count 0 2006.285.16:57:22.92#ibcon#end of sib2, iclass 19, count 0 2006.285.16:57:22.92#ibcon#*mode == 0, iclass 19, count 0 2006.285.16:57:22.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.16:57:22.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.16:57:22.92#ibcon#*before write, iclass 19, count 0 2006.285.16:57:22.92#ibcon#enter sib2, iclass 19, count 0 2006.285.16:57:22.92#ibcon#flushed, iclass 19, count 0 2006.285.16:57:22.92#ibcon#about to write, iclass 19, count 0 2006.285.16:57:22.92#ibcon#wrote, iclass 19, count 0 2006.285.16:57:22.92#ibcon#about to read 3, iclass 19, count 0 2006.285.16:57:22.97#ibcon#read 3, iclass 19, count 0 2006.285.16:57:22.97#ibcon#about to read 4, iclass 19, count 0 2006.285.16:57:22.97#ibcon#read 4, iclass 19, count 0 2006.285.16:57:22.97#ibcon#about to read 5, iclass 19, count 0 2006.285.16:57:22.97#ibcon#read 5, iclass 19, count 0 2006.285.16:57:22.97#ibcon#about to read 6, iclass 19, count 0 2006.285.16:57:22.97#ibcon#read 6, iclass 19, count 0 2006.285.16:57:22.97#ibcon#end of sib2, iclass 19, count 0 2006.285.16:57:22.97#ibcon#*after write, iclass 19, count 0 2006.285.16:57:22.97#ibcon#*before return 0, iclass 19, count 0 2006.285.16:57:22.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:57:22.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.16:57:22.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.16:57:22.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.16:57:22.97$vck44/va=1,7 2006.285.16:57:22.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.16:57:22.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.16:57:22.97#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:22.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:57:22.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:57:22.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:57:22.97#ibcon#enter wrdev, iclass 21, count 2 2006.285.16:57:22.97#ibcon#first serial, iclass 21, count 2 2006.285.16:57:22.97#ibcon#enter sib2, iclass 21, count 2 2006.285.16:57:22.97#ibcon#flushed, iclass 21, count 2 2006.285.16:57:22.97#ibcon#about to write, iclass 21, count 2 2006.285.16:57:22.97#ibcon#wrote, iclass 21, count 2 2006.285.16:57:22.97#ibcon#about to read 3, iclass 21, count 2 2006.285.16:57:22.99#ibcon#read 3, iclass 21, count 2 2006.285.16:57:22.99#ibcon#about to read 4, iclass 21, count 2 2006.285.16:57:22.99#ibcon#read 4, iclass 21, count 2 2006.285.16:57:22.99#ibcon#about to read 5, iclass 21, count 2 2006.285.16:57:22.99#ibcon#read 5, iclass 21, count 2 2006.285.16:57:22.99#ibcon#about to read 6, iclass 21, count 2 2006.285.16:57:22.99#ibcon#read 6, iclass 21, count 2 2006.285.16:57:22.99#ibcon#end of sib2, iclass 21, count 2 2006.285.16:57:22.99#ibcon#*mode == 0, iclass 21, count 2 2006.285.16:57:22.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.16:57:22.99#ibcon#[25=AT01-07\r\n] 2006.285.16:57:22.99#ibcon#*before write, iclass 21, count 2 2006.285.16:57:22.99#ibcon#enter sib2, iclass 21, count 2 2006.285.16:57:22.99#ibcon#flushed, iclass 21, count 2 2006.285.16:57:22.99#ibcon#about to write, iclass 21, count 2 2006.285.16:57:22.99#ibcon#wrote, iclass 21, count 2 2006.285.16:57:22.99#ibcon#about to read 3, iclass 21, count 2 2006.285.16:57:23.02#ibcon#read 3, iclass 21, count 2 2006.285.16:57:23.02#ibcon#about to read 4, iclass 21, count 2 2006.285.16:57:23.02#ibcon#read 4, iclass 21, count 2 2006.285.16:57:23.02#ibcon#about to read 5, iclass 21, count 2 2006.285.16:57:23.02#ibcon#read 5, iclass 21, count 2 2006.285.16:57:23.02#ibcon#about to read 6, iclass 21, count 2 2006.285.16:57:23.02#ibcon#read 6, iclass 21, count 2 2006.285.16:57:23.02#ibcon#end of sib2, iclass 21, count 2 2006.285.16:57:23.02#ibcon#*after write, iclass 21, count 2 2006.285.16:57:23.02#ibcon#*before return 0, iclass 21, count 2 2006.285.16:57:23.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:57:23.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.16:57:23.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.16:57:23.02#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:23.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:57:23.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:57:23.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:57:23.14#ibcon#enter wrdev, iclass 21, count 0 2006.285.16:57:23.14#ibcon#first serial, iclass 21, count 0 2006.285.16:57:23.14#ibcon#enter sib2, iclass 21, count 0 2006.285.16:57:23.14#ibcon#flushed, iclass 21, count 0 2006.285.16:57:23.14#ibcon#about to write, iclass 21, count 0 2006.285.16:57:23.14#ibcon#wrote, iclass 21, count 0 2006.285.16:57:23.14#ibcon#about to read 3, iclass 21, count 0 2006.285.16:57:23.16#ibcon#read 3, iclass 21, count 0 2006.285.16:57:23.16#ibcon#about to read 4, iclass 21, count 0 2006.285.16:57:23.16#ibcon#read 4, iclass 21, count 0 2006.285.16:57:23.16#ibcon#about to read 5, iclass 21, count 0 2006.285.16:57:23.16#ibcon#read 5, iclass 21, count 0 2006.285.16:57:23.16#ibcon#about to read 6, iclass 21, count 0 2006.285.16:57:23.16#ibcon#read 6, iclass 21, count 0 2006.285.16:57:23.16#ibcon#end of sib2, iclass 21, count 0 2006.285.16:57:23.16#ibcon#*mode == 0, iclass 21, count 0 2006.285.16:57:23.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.16:57:23.16#ibcon#[25=USB\r\n] 2006.285.16:57:23.16#ibcon#*before write, iclass 21, count 0 2006.285.16:57:23.16#ibcon#enter sib2, iclass 21, count 0 2006.285.16:57:23.16#ibcon#flushed, iclass 21, count 0 2006.285.16:57:23.16#ibcon#about to write, iclass 21, count 0 2006.285.16:57:23.16#ibcon#wrote, iclass 21, count 0 2006.285.16:57:23.16#ibcon#about to read 3, iclass 21, count 0 2006.285.16:57:23.19#ibcon#read 3, iclass 21, count 0 2006.285.16:57:23.19#ibcon#about to read 4, iclass 21, count 0 2006.285.16:57:23.19#ibcon#read 4, iclass 21, count 0 2006.285.16:57:23.19#ibcon#about to read 5, iclass 21, count 0 2006.285.16:57:23.19#ibcon#read 5, iclass 21, count 0 2006.285.16:57:23.19#ibcon#about to read 6, iclass 21, count 0 2006.285.16:57:23.19#ibcon#read 6, iclass 21, count 0 2006.285.16:57:23.19#ibcon#end of sib2, iclass 21, count 0 2006.285.16:57:23.19#ibcon#*after write, iclass 21, count 0 2006.285.16:57:23.19#ibcon#*before return 0, iclass 21, count 0 2006.285.16:57:23.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:57:23.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.16:57:23.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.16:57:23.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.16:57:23.19$vck44/valo=2,534.99 2006.285.16:57:23.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.16:57:23.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.16:57:23.19#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:23.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:57:23.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:57:23.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:57:23.19#ibcon#enter wrdev, iclass 23, count 0 2006.285.16:57:23.19#ibcon#first serial, iclass 23, count 0 2006.285.16:57:23.19#ibcon#enter sib2, iclass 23, count 0 2006.285.16:57:23.19#ibcon#flushed, iclass 23, count 0 2006.285.16:57:23.19#ibcon#about to write, iclass 23, count 0 2006.285.16:57:23.19#ibcon#wrote, iclass 23, count 0 2006.285.16:57:23.19#ibcon#about to read 3, iclass 23, count 0 2006.285.16:57:23.21#ibcon#read 3, iclass 23, count 0 2006.285.16:57:23.21#ibcon#about to read 4, iclass 23, count 0 2006.285.16:57:23.21#ibcon#read 4, iclass 23, count 0 2006.285.16:57:23.21#ibcon#about to read 5, iclass 23, count 0 2006.285.16:57:23.21#ibcon#read 5, iclass 23, count 0 2006.285.16:57:23.21#ibcon#about to read 6, iclass 23, count 0 2006.285.16:57:23.21#ibcon#read 6, iclass 23, count 0 2006.285.16:57:23.21#ibcon#end of sib2, iclass 23, count 0 2006.285.16:57:23.21#ibcon#*mode == 0, iclass 23, count 0 2006.285.16:57:23.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.16:57:23.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.16:57:23.21#ibcon#*before write, iclass 23, count 0 2006.285.16:57:23.21#ibcon#enter sib2, iclass 23, count 0 2006.285.16:57:23.21#ibcon#flushed, iclass 23, count 0 2006.285.16:57:23.21#ibcon#about to write, iclass 23, count 0 2006.285.16:57:23.21#ibcon#wrote, iclass 23, count 0 2006.285.16:57:23.21#ibcon#about to read 3, iclass 23, count 0 2006.285.16:57:23.25#ibcon#read 3, iclass 23, count 0 2006.285.16:57:23.25#ibcon#about to read 4, iclass 23, count 0 2006.285.16:57:23.25#ibcon#read 4, iclass 23, count 0 2006.285.16:57:23.25#ibcon#about to read 5, iclass 23, count 0 2006.285.16:57:23.25#ibcon#read 5, iclass 23, count 0 2006.285.16:57:23.25#ibcon#about to read 6, iclass 23, count 0 2006.285.16:57:23.25#ibcon#read 6, iclass 23, count 0 2006.285.16:57:23.25#ibcon#end of sib2, iclass 23, count 0 2006.285.16:57:23.25#ibcon#*after write, iclass 23, count 0 2006.285.16:57:23.25#ibcon#*before return 0, iclass 23, count 0 2006.285.16:57:23.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:57:23.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:57:23.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.16:57:23.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.16:57:23.25$vck44/va=2,6 2006.285.16:57:23.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.16:57:23.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.16:57:23.25#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:23.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:57:23.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:57:23.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:57:23.31#ibcon#enter wrdev, iclass 25, count 2 2006.285.16:57:23.31#ibcon#first serial, iclass 25, count 2 2006.285.16:57:23.31#ibcon#enter sib2, iclass 25, count 2 2006.285.16:57:23.31#ibcon#flushed, iclass 25, count 2 2006.285.16:57:23.31#ibcon#about to write, iclass 25, count 2 2006.285.16:57:23.31#ibcon#wrote, iclass 25, count 2 2006.285.16:57:23.31#ibcon#about to read 3, iclass 25, count 2 2006.285.16:57:23.34#ibcon#read 3, iclass 25, count 2 2006.285.16:57:23.34#ibcon#about to read 4, iclass 25, count 2 2006.285.16:57:23.34#ibcon#read 4, iclass 25, count 2 2006.285.16:57:23.34#ibcon#about to read 5, iclass 25, count 2 2006.285.16:57:23.34#ibcon#read 5, iclass 25, count 2 2006.285.16:57:23.34#ibcon#about to read 6, iclass 25, count 2 2006.285.16:57:23.34#ibcon#read 6, iclass 25, count 2 2006.285.16:57:23.34#ibcon#end of sib2, iclass 25, count 2 2006.285.16:57:23.34#ibcon#*mode == 0, iclass 25, count 2 2006.285.16:57:23.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.16:57:23.34#ibcon#[25=AT02-06\r\n] 2006.285.16:57:23.34#ibcon#*before write, iclass 25, count 2 2006.285.16:57:23.34#ibcon#enter sib2, iclass 25, count 2 2006.285.16:57:23.34#ibcon#flushed, iclass 25, count 2 2006.285.16:57:23.34#ibcon#about to write, iclass 25, count 2 2006.285.16:57:23.34#ibcon#wrote, iclass 25, count 2 2006.285.16:57:23.34#ibcon#about to read 3, iclass 25, count 2 2006.285.16:57:23.37#ibcon#read 3, iclass 25, count 2 2006.285.16:57:23.37#ibcon#about to read 4, iclass 25, count 2 2006.285.16:57:23.37#ibcon#read 4, iclass 25, count 2 2006.285.16:57:23.37#ibcon#about to read 5, iclass 25, count 2 2006.285.16:57:23.37#ibcon#read 5, iclass 25, count 2 2006.285.16:57:23.37#ibcon#about to read 6, iclass 25, count 2 2006.285.16:57:23.37#ibcon#read 6, iclass 25, count 2 2006.285.16:57:23.37#ibcon#end of sib2, iclass 25, count 2 2006.285.16:57:23.37#ibcon#*after write, iclass 25, count 2 2006.285.16:57:23.37#ibcon#*before return 0, iclass 25, count 2 2006.285.16:57:23.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:57:23.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:57:23.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.16:57:23.37#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:23.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:57:23.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:57:23.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:57:23.49#ibcon#enter wrdev, iclass 25, count 0 2006.285.16:57:23.49#ibcon#first serial, iclass 25, count 0 2006.285.16:57:23.49#ibcon#enter sib2, iclass 25, count 0 2006.285.16:57:23.49#ibcon#flushed, iclass 25, count 0 2006.285.16:57:23.49#ibcon#about to write, iclass 25, count 0 2006.285.16:57:23.49#ibcon#wrote, iclass 25, count 0 2006.285.16:57:23.49#ibcon#about to read 3, iclass 25, count 0 2006.285.16:57:23.51#ibcon#read 3, iclass 25, count 0 2006.285.16:57:23.51#ibcon#about to read 4, iclass 25, count 0 2006.285.16:57:23.51#ibcon#read 4, iclass 25, count 0 2006.285.16:57:23.51#ibcon#about to read 5, iclass 25, count 0 2006.285.16:57:23.51#ibcon#read 5, iclass 25, count 0 2006.285.16:57:23.51#ibcon#about to read 6, iclass 25, count 0 2006.285.16:57:23.51#ibcon#read 6, iclass 25, count 0 2006.285.16:57:23.51#ibcon#end of sib2, iclass 25, count 0 2006.285.16:57:23.51#ibcon#*mode == 0, iclass 25, count 0 2006.285.16:57:23.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.16:57:23.51#ibcon#[25=USB\r\n] 2006.285.16:57:23.51#ibcon#*before write, iclass 25, count 0 2006.285.16:57:23.51#ibcon#enter sib2, iclass 25, count 0 2006.285.16:57:23.51#ibcon#flushed, iclass 25, count 0 2006.285.16:57:23.51#ibcon#about to write, iclass 25, count 0 2006.285.16:57:23.51#ibcon#wrote, iclass 25, count 0 2006.285.16:57:23.51#ibcon#about to read 3, iclass 25, count 0 2006.285.16:57:23.54#ibcon#read 3, iclass 25, count 0 2006.285.16:57:23.86#ibcon#about to read 4, iclass 25, count 0 2006.285.16:57:23.86#ibcon#read 4, iclass 25, count 0 2006.285.16:57:23.86#ibcon#about to read 5, iclass 25, count 0 2006.285.16:57:23.86#ibcon#read 5, iclass 25, count 0 2006.285.16:57:23.86#ibcon#about to read 6, iclass 25, count 0 2006.285.16:57:23.86#ibcon#read 6, iclass 25, count 0 2006.285.16:57:23.86#ibcon#end of sib2, iclass 25, count 0 2006.285.16:57:23.86#ibcon#*after write, iclass 25, count 0 2006.285.16:57:23.86#ibcon#*before return 0, iclass 25, count 0 2006.285.16:57:23.86#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:57:23.86#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:57:23.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.16:57:23.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.16:57:23.86$vck44/valo=3,564.99 2006.285.16:57:23.86#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.16:57:23.86#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.16:57:23.86#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:23.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:57:23.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:57:23.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:57:23.86#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:57:23.86#ibcon#first serial, iclass 27, count 0 2006.285.16:57:23.86#ibcon#enter sib2, iclass 27, count 0 2006.285.16:57:23.86#ibcon#flushed, iclass 27, count 0 2006.285.16:57:23.86#ibcon#about to write, iclass 27, count 0 2006.285.16:57:23.86#ibcon#wrote, iclass 27, count 0 2006.285.16:57:23.86#ibcon#about to read 3, iclass 27, count 0 2006.285.16:57:23.88#ibcon#read 3, iclass 27, count 0 2006.285.16:57:23.88#ibcon#about to read 4, iclass 27, count 0 2006.285.16:57:23.88#ibcon#read 4, iclass 27, count 0 2006.285.16:57:23.88#ibcon#about to read 5, iclass 27, count 0 2006.285.16:57:23.88#ibcon#read 5, iclass 27, count 0 2006.285.16:57:23.88#ibcon#about to read 6, iclass 27, count 0 2006.285.16:57:23.88#ibcon#read 6, iclass 27, count 0 2006.285.16:57:23.88#ibcon#end of sib2, iclass 27, count 0 2006.285.16:57:23.88#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:57:23.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:57:23.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.16:57:23.88#ibcon#*before write, iclass 27, count 0 2006.285.16:57:23.88#ibcon#enter sib2, iclass 27, count 0 2006.285.16:57:23.88#ibcon#flushed, iclass 27, count 0 2006.285.16:57:23.88#ibcon#about to write, iclass 27, count 0 2006.285.16:57:23.88#ibcon#wrote, iclass 27, count 0 2006.285.16:57:23.88#ibcon#about to read 3, iclass 27, count 0 2006.285.16:57:23.92#ibcon#read 3, iclass 27, count 0 2006.285.16:57:23.92#ibcon#about to read 4, iclass 27, count 0 2006.285.16:57:23.92#ibcon#read 4, iclass 27, count 0 2006.285.16:57:23.92#ibcon#about to read 5, iclass 27, count 0 2006.285.16:57:23.92#ibcon#read 5, iclass 27, count 0 2006.285.16:57:23.92#ibcon#about to read 6, iclass 27, count 0 2006.285.16:57:23.92#ibcon#read 6, iclass 27, count 0 2006.285.16:57:23.92#ibcon#end of sib2, iclass 27, count 0 2006.285.16:57:23.92#ibcon#*after write, iclass 27, count 0 2006.285.16:57:23.92#ibcon#*before return 0, iclass 27, count 0 2006.285.16:57:23.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:57:23.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:57:23.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:57:23.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:57:23.92$vck44/va=3,7 2006.285.16:57:23.92#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.16:57:23.92#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.16:57:23.92#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:23.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:57:23.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:57:23.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:57:23.98#ibcon#enter wrdev, iclass 29, count 2 2006.285.16:57:23.98#ibcon#first serial, iclass 29, count 2 2006.285.16:57:23.98#ibcon#enter sib2, iclass 29, count 2 2006.285.16:57:23.98#ibcon#flushed, iclass 29, count 2 2006.285.16:57:23.98#ibcon#about to write, iclass 29, count 2 2006.285.16:57:23.98#ibcon#wrote, iclass 29, count 2 2006.285.16:57:23.98#ibcon#about to read 3, iclass 29, count 2 2006.285.16:57:24.00#ibcon#read 3, iclass 29, count 2 2006.285.16:57:24.00#ibcon#about to read 4, iclass 29, count 2 2006.285.16:57:24.00#ibcon#read 4, iclass 29, count 2 2006.285.16:57:24.00#ibcon#about to read 5, iclass 29, count 2 2006.285.16:57:24.00#ibcon#read 5, iclass 29, count 2 2006.285.16:57:24.00#ibcon#about to read 6, iclass 29, count 2 2006.285.16:57:24.00#ibcon#read 6, iclass 29, count 2 2006.285.16:57:24.00#ibcon#end of sib2, iclass 29, count 2 2006.285.16:57:24.00#ibcon#*mode == 0, iclass 29, count 2 2006.285.16:57:24.00#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.16:57:24.00#ibcon#[25=AT03-07\r\n] 2006.285.16:57:24.00#ibcon#*before write, iclass 29, count 2 2006.285.16:57:24.00#ibcon#enter sib2, iclass 29, count 2 2006.285.16:57:24.00#ibcon#flushed, iclass 29, count 2 2006.285.16:57:24.00#ibcon#about to write, iclass 29, count 2 2006.285.16:57:24.00#ibcon#wrote, iclass 29, count 2 2006.285.16:57:24.00#ibcon#about to read 3, iclass 29, count 2 2006.285.16:57:24.03#ibcon#read 3, iclass 29, count 2 2006.285.16:57:24.03#ibcon#about to read 4, iclass 29, count 2 2006.285.16:57:24.03#ibcon#read 4, iclass 29, count 2 2006.285.16:57:24.03#ibcon#about to read 5, iclass 29, count 2 2006.285.16:57:24.03#ibcon#read 5, iclass 29, count 2 2006.285.16:57:24.03#ibcon#about to read 6, iclass 29, count 2 2006.285.16:57:24.03#ibcon#read 6, iclass 29, count 2 2006.285.16:57:24.03#ibcon#end of sib2, iclass 29, count 2 2006.285.16:57:24.03#ibcon#*after write, iclass 29, count 2 2006.285.16:57:24.03#ibcon#*before return 0, iclass 29, count 2 2006.285.16:57:24.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:57:24.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:57:24.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.16:57:24.03#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:24.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:57:24.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:57:24.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:57:24.15#ibcon#enter wrdev, iclass 29, count 0 2006.285.16:57:24.15#ibcon#first serial, iclass 29, count 0 2006.285.16:57:24.15#ibcon#enter sib2, iclass 29, count 0 2006.285.16:57:24.15#ibcon#flushed, iclass 29, count 0 2006.285.16:57:24.15#ibcon#about to write, iclass 29, count 0 2006.285.16:57:24.15#ibcon#wrote, iclass 29, count 0 2006.285.16:57:24.15#ibcon#about to read 3, iclass 29, count 0 2006.285.16:57:24.17#ibcon#read 3, iclass 29, count 0 2006.285.16:57:24.17#ibcon#about to read 4, iclass 29, count 0 2006.285.16:57:24.17#ibcon#read 4, iclass 29, count 0 2006.285.16:57:24.17#ibcon#about to read 5, iclass 29, count 0 2006.285.16:57:24.17#ibcon#read 5, iclass 29, count 0 2006.285.16:57:24.17#ibcon#about to read 6, iclass 29, count 0 2006.285.16:57:24.17#ibcon#read 6, iclass 29, count 0 2006.285.16:57:24.17#ibcon#end of sib2, iclass 29, count 0 2006.285.16:57:24.17#ibcon#*mode == 0, iclass 29, count 0 2006.285.16:57:24.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.16:57:24.17#ibcon#[25=USB\r\n] 2006.285.16:57:24.17#ibcon#*before write, iclass 29, count 0 2006.285.16:57:24.17#ibcon#enter sib2, iclass 29, count 0 2006.285.16:57:24.17#ibcon#flushed, iclass 29, count 0 2006.285.16:57:24.17#ibcon#about to write, iclass 29, count 0 2006.285.16:57:24.17#ibcon#wrote, iclass 29, count 0 2006.285.16:57:24.17#ibcon#about to read 3, iclass 29, count 0 2006.285.16:57:24.20#ibcon#read 3, iclass 29, count 0 2006.285.16:57:24.20#ibcon#about to read 4, iclass 29, count 0 2006.285.16:57:24.20#ibcon#read 4, iclass 29, count 0 2006.285.16:57:24.20#ibcon#about to read 5, iclass 29, count 0 2006.285.16:57:24.20#ibcon#read 5, iclass 29, count 0 2006.285.16:57:24.20#ibcon#about to read 6, iclass 29, count 0 2006.285.16:57:24.20#ibcon#read 6, iclass 29, count 0 2006.285.16:57:24.20#ibcon#end of sib2, iclass 29, count 0 2006.285.16:57:24.20#ibcon#*after write, iclass 29, count 0 2006.285.16:57:24.20#ibcon#*before return 0, iclass 29, count 0 2006.285.16:57:24.20#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:57:24.20#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:57:24.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.16:57:24.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.16:57:24.20$vck44/valo=4,624.99 2006.285.16:57:24.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.16:57:24.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.16:57:24.20#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:24.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:57:24.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:57:24.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:57:24.20#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:57:24.20#ibcon#first serial, iclass 31, count 0 2006.285.16:57:24.20#ibcon#enter sib2, iclass 31, count 0 2006.285.16:57:24.20#ibcon#flushed, iclass 31, count 0 2006.285.16:57:24.44#ibcon#about to write, iclass 31, count 0 2006.285.16:57:24.44#ibcon#wrote, iclass 31, count 0 2006.285.16:57:24.44#ibcon#about to read 3, iclass 31, count 0 2006.285.16:57:24.46#ibcon#read 3, iclass 31, count 0 2006.285.16:57:24.46#ibcon#about to read 4, iclass 31, count 0 2006.285.16:57:24.46#ibcon#read 4, iclass 31, count 0 2006.285.16:57:24.46#ibcon#about to read 5, iclass 31, count 0 2006.285.16:57:24.46#ibcon#read 5, iclass 31, count 0 2006.285.16:57:24.46#ibcon#about to read 6, iclass 31, count 0 2006.285.16:57:24.46#ibcon#read 6, iclass 31, count 0 2006.285.16:57:24.46#ibcon#end of sib2, iclass 31, count 0 2006.285.16:57:24.46#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:57:24.46#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:57:24.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.16:57:24.46#ibcon#*before write, iclass 31, count 0 2006.285.16:57:24.46#ibcon#enter sib2, iclass 31, count 0 2006.285.16:57:24.46#ibcon#flushed, iclass 31, count 0 2006.285.16:57:24.46#ibcon#about to write, iclass 31, count 0 2006.285.16:57:24.46#ibcon#wrote, iclass 31, count 0 2006.285.16:57:24.46#ibcon#about to read 3, iclass 31, count 0 2006.285.16:57:24.50#ibcon#read 3, iclass 31, count 0 2006.285.16:57:24.50#ibcon#about to read 4, iclass 31, count 0 2006.285.16:57:24.50#ibcon#read 4, iclass 31, count 0 2006.285.16:57:24.50#ibcon#about to read 5, iclass 31, count 0 2006.285.16:57:24.50#ibcon#read 5, iclass 31, count 0 2006.285.16:57:24.50#ibcon#about to read 6, iclass 31, count 0 2006.285.16:57:24.50#ibcon#read 6, iclass 31, count 0 2006.285.16:57:24.50#ibcon#end of sib2, iclass 31, count 0 2006.285.16:57:24.50#ibcon#*after write, iclass 31, count 0 2006.285.16:57:24.50#ibcon#*before return 0, iclass 31, count 0 2006.285.16:57:24.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:57:24.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:57:24.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:57:24.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:57:24.50$vck44/va=4,6 2006.285.16:57:24.50#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.16:57:24.50#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.16:57:24.50#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:24.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:57:24.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:57:24.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:57:24.50#ibcon#enter wrdev, iclass 33, count 2 2006.285.16:57:24.50#ibcon#first serial, iclass 33, count 2 2006.285.16:57:24.50#ibcon#enter sib2, iclass 33, count 2 2006.285.16:57:24.50#ibcon#flushed, iclass 33, count 2 2006.285.16:57:24.50#ibcon#about to write, iclass 33, count 2 2006.285.16:57:24.50#ibcon#wrote, iclass 33, count 2 2006.285.16:57:24.50#ibcon#about to read 3, iclass 33, count 2 2006.285.16:57:24.52#ibcon#read 3, iclass 33, count 2 2006.285.16:57:24.52#ibcon#about to read 4, iclass 33, count 2 2006.285.16:57:24.52#ibcon#read 4, iclass 33, count 2 2006.285.16:57:24.52#ibcon#about to read 5, iclass 33, count 2 2006.285.16:57:24.52#ibcon#read 5, iclass 33, count 2 2006.285.16:57:24.52#ibcon#about to read 6, iclass 33, count 2 2006.285.16:57:24.52#ibcon#read 6, iclass 33, count 2 2006.285.16:57:24.52#ibcon#end of sib2, iclass 33, count 2 2006.285.16:57:24.52#ibcon#*mode == 0, iclass 33, count 2 2006.285.16:57:24.52#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.16:57:24.52#ibcon#[25=AT04-06\r\n] 2006.285.16:57:24.52#ibcon#*before write, iclass 33, count 2 2006.285.16:57:24.52#ibcon#enter sib2, iclass 33, count 2 2006.285.16:57:24.52#ibcon#flushed, iclass 33, count 2 2006.285.16:57:24.52#ibcon#about to write, iclass 33, count 2 2006.285.16:57:24.52#ibcon#wrote, iclass 33, count 2 2006.285.16:57:24.52#ibcon#about to read 3, iclass 33, count 2 2006.285.16:57:24.55#ibcon#read 3, iclass 33, count 2 2006.285.16:57:24.55#ibcon#about to read 4, iclass 33, count 2 2006.285.16:57:24.55#ibcon#read 4, iclass 33, count 2 2006.285.16:57:24.55#ibcon#about to read 5, iclass 33, count 2 2006.285.16:57:24.55#ibcon#read 5, iclass 33, count 2 2006.285.16:57:24.55#ibcon#about to read 6, iclass 33, count 2 2006.285.16:57:24.55#ibcon#read 6, iclass 33, count 2 2006.285.16:57:24.55#ibcon#end of sib2, iclass 33, count 2 2006.285.16:57:24.55#ibcon#*after write, iclass 33, count 2 2006.285.16:57:24.55#ibcon#*before return 0, iclass 33, count 2 2006.285.16:57:24.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:57:24.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:57:24.55#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.16:57:24.55#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:24.55#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:57:24.67#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:57:24.67#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:57:24.67#ibcon#enter wrdev, iclass 33, count 0 2006.285.16:57:24.67#ibcon#first serial, iclass 33, count 0 2006.285.16:57:24.67#ibcon#enter sib2, iclass 33, count 0 2006.285.16:57:24.67#ibcon#flushed, iclass 33, count 0 2006.285.16:57:24.67#ibcon#about to write, iclass 33, count 0 2006.285.16:57:24.67#ibcon#wrote, iclass 33, count 0 2006.285.16:57:24.67#ibcon#about to read 3, iclass 33, count 0 2006.285.16:57:24.69#ibcon#read 3, iclass 33, count 0 2006.285.16:57:24.69#ibcon#about to read 4, iclass 33, count 0 2006.285.16:57:24.69#ibcon#read 4, iclass 33, count 0 2006.285.16:57:24.69#ibcon#about to read 5, iclass 33, count 0 2006.285.16:57:24.69#ibcon#read 5, iclass 33, count 0 2006.285.16:57:24.69#ibcon#about to read 6, iclass 33, count 0 2006.285.16:57:24.69#ibcon#read 6, iclass 33, count 0 2006.285.16:57:24.69#ibcon#end of sib2, iclass 33, count 0 2006.285.16:57:24.69#ibcon#*mode == 0, iclass 33, count 0 2006.285.16:57:24.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.16:57:24.69#ibcon#[25=USB\r\n] 2006.285.16:57:24.69#ibcon#*before write, iclass 33, count 0 2006.285.16:57:24.69#ibcon#enter sib2, iclass 33, count 0 2006.285.16:57:24.69#ibcon#flushed, iclass 33, count 0 2006.285.16:57:24.69#ibcon#about to write, iclass 33, count 0 2006.285.16:57:24.69#ibcon#wrote, iclass 33, count 0 2006.285.16:57:24.69#ibcon#about to read 3, iclass 33, count 0 2006.285.16:57:24.72#ibcon#read 3, iclass 33, count 0 2006.285.16:57:24.72#ibcon#about to read 4, iclass 33, count 0 2006.285.16:57:24.72#ibcon#read 4, iclass 33, count 0 2006.285.16:57:24.72#ibcon#about to read 5, iclass 33, count 0 2006.285.16:57:24.72#ibcon#read 5, iclass 33, count 0 2006.285.16:57:24.72#ibcon#about to read 6, iclass 33, count 0 2006.285.16:57:24.72#ibcon#read 6, iclass 33, count 0 2006.285.16:57:24.72#ibcon#end of sib2, iclass 33, count 0 2006.285.16:57:24.72#ibcon#*after write, iclass 33, count 0 2006.285.16:57:24.72#ibcon#*before return 0, iclass 33, count 0 2006.285.16:57:24.72#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:57:24.72#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:57:24.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.16:57:24.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.16:57:24.72$vck44/valo=5,734.99 2006.285.16:57:24.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.16:57:24.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.16:57:24.72#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:24.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:57:24.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:57:24.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:57:24.72#ibcon#enter wrdev, iclass 35, count 0 2006.285.16:57:24.72#ibcon#first serial, iclass 35, count 0 2006.285.16:57:24.72#ibcon#enter sib2, iclass 35, count 0 2006.285.16:57:24.72#ibcon#flushed, iclass 35, count 0 2006.285.16:57:24.72#ibcon#about to write, iclass 35, count 0 2006.285.16:57:24.72#ibcon#wrote, iclass 35, count 0 2006.285.16:57:24.72#ibcon#about to read 3, iclass 35, count 0 2006.285.16:57:24.74#ibcon#read 3, iclass 35, count 0 2006.285.16:57:24.74#ibcon#about to read 4, iclass 35, count 0 2006.285.16:57:24.74#ibcon#read 4, iclass 35, count 0 2006.285.16:57:24.74#ibcon#about to read 5, iclass 35, count 0 2006.285.16:57:24.74#ibcon#read 5, iclass 35, count 0 2006.285.16:57:24.74#ibcon#about to read 6, iclass 35, count 0 2006.285.16:57:24.74#ibcon#read 6, iclass 35, count 0 2006.285.16:57:24.74#ibcon#end of sib2, iclass 35, count 0 2006.285.16:57:24.74#ibcon#*mode == 0, iclass 35, count 0 2006.285.16:57:24.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.16:57:24.74#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.16:57:24.74#ibcon#*before write, iclass 35, count 0 2006.285.16:57:24.74#ibcon#enter sib2, iclass 35, count 0 2006.285.16:57:24.74#ibcon#flushed, iclass 35, count 0 2006.285.16:57:24.74#ibcon#about to write, iclass 35, count 0 2006.285.16:57:24.74#ibcon#wrote, iclass 35, count 0 2006.285.16:57:24.74#ibcon#about to read 3, iclass 35, count 0 2006.285.16:57:24.78#ibcon#read 3, iclass 35, count 0 2006.285.16:57:24.78#ibcon#about to read 4, iclass 35, count 0 2006.285.16:57:24.78#ibcon#read 4, iclass 35, count 0 2006.285.16:57:24.78#ibcon#about to read 5, iclass 35, count 0 2006.285.16:57:24.78#ibcon#read 5, iclass 35, count 0 2006.285.16:57:24.78#ibcon#about to read 6, iclass 35, count 0 2006.285.16:57:24.78#ibcon#read 6, iclass 35, count 0 2006.285.16:57:24.78#ibcon#end of sib2, iclass 35, count 0 2006.285.16:57:24.78#ibcon#*after write, iclass 35, count 0 2006.285.16:57:24.78#ibcon#*before return 0, iclass 35, count 0 2006.285.16:57:24.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:57:24.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:57:24.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.16:57:24.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.16:57:24.78$vck44/va=5,3 2006.285.16:57:24.78#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.16:57:24.78#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.16:57:24.78#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:24.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:57:24.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:57:24.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:57:24.84#ibcon#enter wrdev, iclass 37, count 2 2006.285.16:57:24.84#ibcon#first serial, iclass 37, count 2 2006.285.16:57:24.84#ibcon#enter sib2, iclass 37, count 2 2006.285.16:57:24.84#ibcon#flushed, iclass 37, count 2 2006.285.16:57:24.84#ibcon#about to write, iclass 37, count 2 2006.285.16:57:24.84#ibcon#wrote, iclass 37, count 2 2006.285.16:57:24.84#ibcon#about to read 3, iclass 37, count 2 2006.285.16:57:24.86#ibcon#read 3, iclass 37, count 2 2006.285.16:57:24.86#ibcon#about to read 4, iclass 37, count 2 2006.285.16:57:24.86#ibcon#read 4, iclass 37, count 2 2006.285.16:57:24.86#ibcon#about to read 5, iclass 37, count 2 2006.285.16:57:24.86#ibcon#read 5, iclass 37, count 2 2006.285.16:57:24.86#ibcon#about to read 6, iclass 37, count 2 2006.285.16:57:24.86#ibcon#read 6, iclass 37, count 2 2006.285.16:57:24.86#ibcon#end of sib2, iclass 37, count 2 2006.285.16:57:24.86#ibcon#*mode == 0, iclass 37, count 2 2006.285.16:57:24.86#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.16:57:24.86#ibcon#[25=AT05-03\r\n] 2006.285.16:57:24.86#ibcon#*before write, iclass 37, count 2 2006.285.16:57:24.86#ibcon#enter sib2, iclass 37, count 2 2006.285.16:57:24.86#ibcon#flushed, iclass 37, count 2 2006.285.16:57:24.86#ibcon#about to write, iclass 37, count 2 2006.285.16:57:24.86#ibcon#wrote, iclass 37, count 2 2006.285.16:57:24.86#ibcon#about to read 3, iclass 37, count 2 2006.285.16:57:24.89#ibcon#read 3, iclass 37, count 2 2006.285.16:57:24.89#ibcon#about to read 4, iclass 37, count 2 2006.285.16:57:24.89#ibcon#read 4, iclass 37, count 2 2006.285.16:57:24.89#ibcon#about to read 5, iclass 37, count 2 2006.285.16:57:24.89#ibcon#read 5, iclass 37, count 2 2006.285.16:57:24.89#ibcon#about to read 6, iclass 37, count 2 2006.285.16:57:24.89#ibcon#read 6, iclass 37, count 2 2006.285.16:57:24.89#ibcon#end of sib2, iclass 37, count 2 2006.285.16:57:24.89#ibcon#*after write, iclass 37, count 2 2006.285.16:57:24.89#ibcon#*before return 0, iclass 37, count 2 2006.285.16:57:24.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:57:24.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:57:24.89#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.16:57:24.89#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:24.89#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:57:25.01#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:57:25.01#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:57:25.01#ibcon#enter wrdev, iclass 37, count 0 2006.285.16:57:25.01#ibcon#first serial, iclass 37, count 0 2006.285.16:57:25.01#ibcon#enter sib2, iclass 37, count 0 2006.285.16:57:25.01#ibcon#flushed, iclass 37, count 0 2006.285.16:57:25.01#ibcon#about to write, iclass 37, count 0 2006.285.16:57:25.01#ibcon#wrote, iclass 37, count 0 2006.285.16:57:25.01#ibcon#about to read 3, iclass 37, count 0 2006.285.16:57:25.03#ibcon#read 3, iclass 37, count 0 2006.285.16:57:25.03#ibcon#about to read 4, iclass 37, count 0 2006.285.16:57:25.03#ibcon#read 4, iclass 37, count 0 2006.285.16:57:25.03#ibcon#about to read 5, iclass 37, count 0 2006.285.16:57:25.03#ibcon#read 5, iclass 37, count 0 2006.285.16:57:25.03#ibcon#about to read 6, iclass 37, count 0 2006.285.16:57:25.03#ibcon#read 6, iclass 37, count 0 2006.285.16:57:25.03#ibcon#end of sib2, iclass 37, count 0 2006.285.16:57:25.03#ibcon#*mode == 0, iclass 37, count 0 2006.285.16:57:25.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.16:57:25.03#ibcon#[25=USB\r\n] 2006.285.16:57:25.03#ibcon#*before write, iclass 37, count 0 2006.285.16:57:25.03#ibcon#enter sib2, iclass 37, count 0 2006.285.16:57:25.03#ibcon#flushed, iclass 37, count 0 2006.285.16:57:25.03#ibcon#about to write, iclass 37, count 0 2006.285.16:57:25.03#ibcon#wrote, iclass 37, count 0 2006.285.16:57:25.03#ibcon#about to read 3, iclass 37, count 0 2006.285.16:57:25.06#ibcon#read 3, iclass 37, count 0 2006.285.16:57:25.06#ibcon#about to read 4, iclass 37, count 0 2006.285.16:57:25.06#ibcon#read 4, iclass 37, count 0 2006.285.16:57:25.06#ibcon#about to read 5, iclass 37, count 0 2006.285.16:57:25.06#ibcon#read 5, iclass 37, count 0 2006.285.16:57:25.06#ibcon#about to read 6, iclass 37, count 0 2006.285.16:57:25.06#ibcon#read 6, iclass 37, count 0 2006.285.16:57:25.06#ibcon#end of sib2, iclass 37, count 0 2006.285.16:57:25.06#ibcon#*after write, iclass 37, count 0 2006.285.16:57:25.06#ibcon#*before return 0, iclass 37, count 0 2006.285.16:57:25.06#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:57:25.06#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:57:25.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.16:57:25.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.16:57:25.06$vck44/valo=6,814.99 2006.285.16:57:25.06#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.16:57:25.06#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.16:57:25.06#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:25.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:57:25.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:57:25.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:57:25.06#ibcon#enter wrdev, iclass 39, count 0 2006.285.16:57:25.06#ibcon#first serial, iclass 39, count 0 2006.285.16:57:25.06#ibcon#enter sib2, iclass 39, count 0 2006.285.16:57:25.06#ibcon#flushed, iclass 39, count 0 2006.285.16:57:25.06#ibcon#about to write, iclass 39, count 0 2006.285.16:57:25.06#ibcon#wrote, iclass 39, count 0 2006.285.16:57:25.06#ibcon#about to read 3, iclass 39, count 0 2006.285.16:57:25.08#ibcon#read 3, iclass 39, count 0 2006.285.16:57:25.08#ibcon#about to read 4, iclass 39, count 0 2006.285.16:57:25.08#ibcon#read 4, iclass 39, count 0 2006.285.16:57:25.08#ibcon#about to read 5, iclass 39, count 0 2006.285.16:57:25.08#ibcon#read 5, iclass 39, count 0 2006.285.16:57:25.08#ibcon#about to read 6, iclass 39, count 0 2006.285.16:57:25.08#ibcon#read 6, iclass 39, count 0 2006.285.16:57:25.08#ibcon#end of sib2, iclass 39, count 0 2006.285.16:57:25.08#ibcon#*mode == 0, iclass 39, count 0 2006.285.16:57:25.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.16:57:25.08#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.16:57:25.08#ibcon#*before write, iclass 39, count 0 2006.285.16:57:25.08#ibcon#enter sib2, iclass 39, count 0 2006.285.16:57:25.08#ibcon#flushed, iclass 39, count 0 2006.285.16:57:25.08#ibcon#about to write, iclass 39, count 0 2006.285.16:57:25.08#ibcon#wrote, iclass 39, count 0 2006.285.16:57:25.08#ibcon#about to read 3, iclass 39, count 0 2006.285.16:57:25.12#ibcon#read 3, iclass 39, count 0 2006.285.16:57:25.12#ibcon#about to read 4, iclass 39, count 0 2006.285.16:57:25.12#ibcon#read 4, iclass 39, count 0 2006.285.16:57:25.12#ibcon#about to read 5, iclass 39, count 0 2006.285.16:57:25.12#ibcon#read 5, iclass 39, count 0 2006.285.16:57:25.12#ibcon#about to read 6, iclass 39, count 0 2006.285.16:57:25.12#ibcon#read 6, iclass 39, count 0 2006.285.16:57:25.12#ibcon#end of sib2, iclass 39, count 0 2006.285.16:57:25.12#ibcon#*after write, iclass 39, count 0 2006.285.16:57:25.12#ibcon#*before return 0, iclass 39, count 0 2006.285.16:57:25.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:57:25.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:57:25.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.16:57:25.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.16:57:25.12$vck44/va=6,4 2006.285.16:57:25.12#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.16:57:25.12#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.16:57:25.12#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:25.12#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:57:25.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:57:25.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:57:25.18#ibcon#enter wrdev, iclass 3, count 2 2006.285.16:57:25.18#ibcon#first serial, iclass 3, count 2 2006.285.16:57:25.18#ibcon#enter sib2, iclass 3, count 2 2006.285.16:57:25.18#ibcon#flushed, iclass 3, count 2 2006.285.16:57:25.18#ibcon#about to write, iclass 3, count 2 2006.285.16:57:25.18#ibcon#wrote, iclass 3, count 2 2006.285.16:57:25.18#ibcon#about to read 3, iclass 3, count 2 2006.285.16:57:25.20#ibcon#read 3, iclass 3, count 2 2006.285.16:57:25.20#ibcon#about to read 4, iclass 3, count 2 2006.285.16:57:25.20#ibcon#read 4, iclass 3, count 2 2006.285.16:57:25.20#ibcon#about to read 5, iclass 3, count 2 2006.285.16:57:25.20#ibcon#read 5, iclass 3, count 2 2006.285.16:57:25.20#ibcon#about to read 6, iclass 3, count 2 2006.285.16:57:25.20#ibcon#read 6, iclass 3, count 2 2006.285.16:57:25.20#ibcon#end of sib2, iclass 3, count 2 2006.285.16:57:25.20#ibcon#*mode == 0, iclass 3, count 2 2006.285.16:57:25.20#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.16:57:25.20#ibcon#[25=AT06-04\r\n] 2006.285.16:57:25.20#ibcon#*before write, iclass 3, count 2 2006.285.16:57:25.20#ibcon#enter sib2, iclass 3, count 2 2006.285.16:57:25.20#ibcon#flushed, iclass 3, count 2 2006.285.16:57:25.20#ibcon#about to write, iclass 3, count 2 2006.285.16:57:25.20#ibcon#wrote, iclass 3, count 2 2006.285.16:57:25.20#ibcon#about to read 3, iclass 3, count 2 2006.285.16:57:25.23#ibcon#read 3, iclass 3, count 2 2006.285.16:57:25.23#ibcon#about to read 4, iclass 3, count 2 2006.285.16:57:25.23#ibcon#read 4, iclass 3, count 2 2006.285.16:57:25.23#ibcon#about to read 5, iclass 3, count 2 2006.285.16:57:25.23#ibcon#read 5, iclass 3, count 2 2006.285.16:57:25.23#ibcon#about to read 6, iclass 3, count 2 2006.285.16:57:25.23#ibcon#read 6, iclass 3, count 2 2006.285.16:57:25.23#ibcon#end of sib2, iclass 3, count 2 2006.285.16:57:25.23#ibcon#*after write, iclass 3, count 2 2006.285.16:57:25.23#ibcon#*before return 0, iclass 3, count 2 2006.285.16:57:25.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:57:25.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:57:25.23#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.16:57:25.23#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:25.23#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:57:25.35#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:57:25.35#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:57:25.35#ibcon#enter wrdev, iclass 3, count 0 2006.285.16:57:25.35#ibcon#first serial, iclass 3, count 0 2006.285.16:57:25.35#ibcon#enter sib2, iclass 3, count 0 2006.285.16:57:25.35#ibcon#flushed, iclass 3, count 0 2006.285.16:57:25.35#ibcon#about to write, iclass 3, count 0 2006.285.16:57:25.35#ibcon#wrote, iclass 3, count 0 2006.285.16:57:25.35#ibcon#about to read 3, iclass 3, count 0 2006.285.16:57:25.37#ibcon#read 3, iclass 3, count 0 2006.285.16:57:25.37#ibcon#about to read 4, iclass 3, count 0 2006.285.16:57:25.37#ibcon#read 4, iclass 3, count 0 2006.285.16:57:25.37#ibcon#about to read 5, iclass 3, count 0 2006.285.16:57:25.37#ibcon#read 5, iclass 3, count 0 2006.285.16:57:25.37#ibcon#about to read 6, iclass 3, count 0 2006.285.16:57:25.37#ibcon#read 6, iclass 3, count 0 2006.285.16:57:25.37#ibcon#end of sib2, iclass 3, count 0 2006.285.16:57:25.37#ibcon#*mode == 0, iclass 3, count 0 2006.285.16:57:25.37#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.16:57:25.37#ibcon#[25=USB\r\n] 2006.285.16:57:25.37#ibcon#*before write, iclass 3, count 0 2006.285.16:57:25.37#ibcon#enter sib2, iclass 3, count 0 2006.285.16:57:25.37#ibcon#flushed, iclass 3, count 0 2006.285.16:57:25.37#ibcon#about to write, iclass 3, count 0 2006.285.16:57:25.37#ibcon#wrote, iclass 3, count 0 2006.285.16:57:25.37#ibcon#about to read 3, iclass 3, count 0 2006.285.16:57:25.40#ibcon#read 3, iclass 3, count 0 2006.285.16:57:25.40#ibcon#about to read 4, iclass 3, count 0 2006.285.16:57:25.40#ibcon#read 4, iclass 3, count 0 2006.285.16:57:25.40#ibcon#about to read 5, iclass 3, count 0 2006.285.16:57:25.40#ibcon#read 5, iclass 3, count 0 2006.285.16:57:25.40#ibcon#about to read 6, iclass 3, count 0 2006.285.16:57:25.40#ibcon#read 6, iclass 3, count 0 2006.285.16:57:25.40#ibcon#end of sib2, iclass 3, count 0 2006.285.16:57:25.40#ibcon#*after write, iclass 3, count 0 2006.285.16:57:25.40#ibcon#*before return 0, iclass 3, count 0 2006.285.16:57:25.40#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:57:25.40#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:57:25.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.16:57:25.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.16:57:25.40$vck44/valo=7,864.99 2006.285.16:57:25.40#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.16:57:25.40#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.16:57:25.40#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:25.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:57:25.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:57:25.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:57:25.40#ibcon#enter wrdev, iclass 5, count 0 2006.285.16:57:25.40#ibcon#first serial, iclass 5, count 0 2006.285.16:57:25.40#ibcon#enter sib2, iclass 5, count 0 2006.285.16:57:25.40#ibcon#flushed, iclass 5, count 0 2006.285.16:57:25.40#ibcon#about to write, iclass 5, count 0 2006.285.16:57:25.40#ibcon#wrote, iclass 5, count 0 2006.285.16:57:25.40#ibcon#about to read 3, iclass 5, count 0 2006.285.16:57:25.42#ibcon#read 3, iclass 5, count 0 2006.285.16:57:25.42#ibcon#about to read 4, iclass 5, count 0 2006.285.16:57:25.42#ibcon#read 4, iclass 5, count 0 2006.285.16:57:25.42#ibcon#about to read 5, iclass 5, count 0 2006.285.16:57:25.42#ibcon#read 5, iclass 5, count 0 2006.285.16:57:25.42#ibcon#about to read 6, iclass 5, count 0 2006.285.16:57:25.42#ibcon#read 6, iclass 5, count 0 2006.285.16:57:25.42#ibcon#end of sib2, iclass 5, count 0 2006.285.16:57:25.42#ibcon#*mode == 0, iclass 5, count 0 2006.285.16:57:25.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.16:57:25.42#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.16:57:25.42#ibcon#*before write, iclass 5, count 0 2006.285.16:57:25.42#ibcon#enter sib2, iclass 5, count 0 2006.285.16:57:25.42#ibcon#flushed, iclass 5, count 0 2006.285.16:57:25.42#ibcon#about to write, iclass 5, count 0 2006.285.16:57:25.42#ibcon#wrote, iclass 5, count 0 2006.285.16:57:25.42#ibcon#about to read 3, iclass 5, count 0 2006.285.16:57:25.46#ibcon#read 3, iclass 5, count 0 2006.285.16:57:25.46#ibcon#about to read 4, iclass 5, count 0 2006.285.16:57:25.46#ibcon#read 4, iclass 5, count 0 2006.285.16:57:25.46#ibcon#about to read 5, iclass 5, count 0 2006.285.16:57:25.46#ibcon#read 5, iclass 5, count 0 2006.285.16:57:25.46#ibcon#about to read 6, iclass 5, count 0 2006.285.16:57:25.46#ibcon#read 6, iclass 5, count 0 2006.285.16:57:25.46#ibcon#end of sib2, iclass 5, count 0 2006.285.16:57:25.46#ibcon#*after write, iclass 5, count 0 2006.285.16:57:25.46#ibcon#*before return 0, iclass 5, count 0 2006.285.16:57:25.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:57:25.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:57:25.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.16:57:25.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.16:57:25.46$vck44/va=7,4 2006.285.16:57:25.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.16:57:25.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.16:57:25.58#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:25.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:57:25.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:57:25.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:57:25.58#ibcon#enter wrdev, iclass 7, count 2 2006.285.16:57:25.58#ibcon#first serial, iclass 7, count 2 2006.285.16:57:25.58#ibcon#enter sib2, iclass 7, count 2 2006.285.16:57:25.58#ibcon#flushed, iclass 7, count 2 2006.285.16:57:25.58#ibcon#about to write, iclass 7, count 2 2006.285.16:57:25.58#ibcon#wrote, iclass 7, count 2 2006.285.16:57:25.58#ibcon#about to read 3, iclass 7, count 2 2006.285.16:57:25.59#ibcon#read 3, iclass 7, count 2 2006.285.16:57:25.59#ibcon#about to read 4, iclass 7, count 2 2006.285.16:57:25.59#ibcon#read 4, iclass 7, count 2 2006.285.16:57:25.59#ibcon#about to read 5, iclass 7, count 2 2006.285.16:57:25.59#ibcon#read 5, iclass 7, count 2 2006.285.16:57:25.59#ibcon#about to read 6, iclass 7, count 2 2006.285.16:57:25.59#ibcon#read 6, iclass 7, count 2 2006.285.16:57:25.59#ibcon#end of sib2, iclass 7, count 2 2006.285.16:57:25.59#ibcon#*mode == 0, iclass 7, count 2 2006.285.16:57:25.59#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.16:57:25.59#ibcon#[25=AT07-04\r\n] 2006.285.16:57:25.59#ibcon#*before write, iclass 7, count 2 2006.285.16:57:25.59#ibcon#enter sib2, iclass 7, count 2 2006.285.16:57:25.59#ibcon#flushed, iclass 7, count 2 2006.285.16:57:25.59#ibcon#about to write, iclass 7, count 2 2006.285.16:57:25.59#ibcon#wrote, iclass 7, count 2 2006.285.16:57:25.59#ibcon#about to read 3, iclass 7, count 2 2006.285.16:57:25.62#ibcon#read 3, iclass 7, count 2 2006.285.16:57:25.62#ibcon#about to read 4, iclass 7, count 2 2006.285.16:57:25.62#ibcon#read 4, iclass 7, count 2 2006.285.16:57:25.62#ibcon#about to read 5, iclass 7, count 2 2006.285.16:57:25.62#ibcon#read 5, iclass 7, count 2 2006.285.16:57:25.62#ibcon#about to read 6, iclass 7, count 2 2006.285.16:57:25.62#ibcon#read 6, iclass 7, count 2 2006.285.16:57:25.62#ibcon#end of sib2, iclass 7, count 2 2006.285.16:57:25.62#ibcon#*after write, iclass 7, count 2 2006.285.16:57:25.62#ibcon#*before return 0, iclass 7, count 2 2006.285.16:57:25.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:57:25.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:57:25.62#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.16:57:25.62#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:25.62#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:57:25.74#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:57:25.74#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:57:25.74#ibcon#enter wrdev, iclass 7, count 0 2006.285.16:57:25.74#ibcon#first serial, iclass 7, count 0 2006.285.16:57:25.74#ibcon#enter sib2, iclass 7, count 0 2006.285.16:57:25.74#ibcon#flushed, iclass 7, count 0 2006.285.16:57:25.74#ibcon#about to write, iclass 7, count 0 2006.285.16:57:25.74#ibcon#wrote, iclass 7, count 0 2006.285.16:57:25.74#ibcon#about to read 3, iclass 7, count 0 2006.285.16:57:25.76#ibcon#read 3, iclass 7, count 0 2006.285.16:57:25.76#ibcon#about to read 4, iclass 7, count 0 2006.285.16:57:25.76#ibcon#read 4, iclass 7, count 0 2006.285.16:57:25.76#ibcon#about to read 5, iclass 7, count 0 2006.285.16:57:25.76#ibcon#read 5, iclass 7, count 0 2006.285.16:57:25.76#ibcon#about to read 6, iclass 7, count 0 2006.285.16:57:25.76#ibcon#read 6, iclass 7, count 0 2006.285.16:57:25.76#ibcon#end of sib2, iclass 7, count 0 2006.285.16:57:25.76#ibcon#*mode == 0, iclass 7, count 0 2006.285.16:57:25.76#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.16:57:25.76#ibcon#[25=USB\r\n] 2006.285.16:57:25.76#ibcon#*before write, iclass 7, count 0 2006.285.16:57:25.76#ibcon#enter sib2, iclass 7, count 0 2006.285.16:57:25.76#ibcon#flushed, iclass 7, count 0 2006.285.16:57:25.76#ibcon#about to write, iclass 7, count 0 2006.285.16:57:25.76#ibcon#wrote, iclass 7, count 0 2006.285.16:57:25.76#ibcon#about to read 3, iclass 7, count 0 2006.285.16:57:25.79#ibcon#read 3, iclass 7, count 0 2006.285.16:57:25.79#ibcon#about to read 4, iclass 7, count 0 2006.285.16:57:25.79#ibcon#read 4, iclass 7, count 0 2006.285.16:57:25.79#ibcon#about to read 5, iclass 7, count 0 2006.285.16:57:25.79#ibcon#read 5, iclass 7, count 0 2006.285.16:57:25.79#ibcon#about to read 6, iclass 7, count 0 2006.285.16:57:25.79#ibcon#read 6, iclass 7, count 0 2006.285.16:57:25.79#ibcon#end of sib2, iclass 7, count 0 2006.285.16:57:25.79#ibcon#*after write, iclass 7, count 0 2006.285.16:57:25.79#ibcon#*before return 0, iclass 7, count 0 2006.285.16:57:25.79#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:57:25.79#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:57:25.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.16:57:25.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.16:57:25.79$vck44/valo=8,884.99 2006.285.16:57:25.79#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.16:57:25.79#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.16:57:25.79#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:25.79#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:57:25.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:57:25.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:57:25.79#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:57:25.79#ibcon#first serial, iclass 11, count 0 2006.285.16:57:25.79#ibcon#enter sib2, iclass 11, count 0 2006.285.16:57:25.79#ibcon#flushed, iclass 11, count 0 2006.285.16:57:25.79#ibcon#about to write, iclass 11, count 0 2006.285.16:57:25.79#ibcon#wrote, iclass 11, count 0 2006.285.16:57:25.79#ibcon#about to read 3, iclass 11, count 0 2006.285.16:57:25.81#ibcon#read 3, iclass 11, count 0 2006.285.16:57:25.81#ibcon#about to read 4, iclass 11, count 0 2006.285.16:57:25.81#ibcon#read 4, iclass 11, count 0 2006.285.16:57:25.81#ibcon#about to read 5, iclass 11, count 0 2006.285.16:57:25.81#ibcon#read 5, iclass 11, count 0 2006.285.16:57:25.81#ibcon#about to read 6, iclass 11, count 0 2006.285.16:57:25.81#ibcon#read 6, iclass 11, count 0 2006.285.16:57:25.81#ibcon#end of sib2, iclass 11, count 0 2006.285.16:57:25.81#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:57:25.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:57:25.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.16:57:25.81#ibcon#*before write, iclass 11, count 0 2006.285.16:57:25.81#ibcon#enter sib2, iclass 11, count 0 2006.285.16:57:25.81#ibcon#flushed, iclass 11, count 0 2006.285.16:57:25.81#ibcon#about to write, iclass 11, count 0 2006.285.16:57:25.81#ibcon#wrote, iclass 11, count 0 2006.285.16:57:25.81#ibcon#about to read 3, iclass 11, count 0 2006.285.16:57:25.85#ibcon#read 3, iclass 11, count 0 2006.285.16:57:25.85#ibcon#about to read 4, iclass 11, count 0 2006.285.16:57:25.85#ibcon#read 4, iclass 11, count 0 2006.285.16:57:25.85#ibcon#about to read 5, iclass 11, count 0 2006.285.16:57:25.85#ibcon#read 5, iclass 11, count 0 2006.285.16:57:25.85#ibcon#about to read 6, iclass 11, count 0 2006.285.16:57:25.85#ibcon#read 6, iclass 11, count 0 2006.285.16:57:25.85#ibcon#end of sib2, iclass 11, count 0 2006.285.16:57:25.85#ibcon#*after write, iclass 11, count 0 2006.285.16:57:25.85#ibcon#*before return 0, iclass 11, count 0 2006.285.16:57:25.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:57:25.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:57:25.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:57:25.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:57:25.85$vck44/va=8,3 2006.285.16:57:25.85#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.16:57:25.85#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.16:57:25.85#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:25.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:57:25.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:57:25.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:57:25.91#ibcon#enter wrdev, iclass 13, count 2 2006.285.16:57:25.91#ibcon#first serial, iclass 13, count 2 2006.285.16:57:25.91#ibcon#enter sib2, iclass 13, count 2 2006.285.16:57:25.91#ibcon#flushed, iclass 13, count 2 2006.285.16:57:25.91#ibcon#about to write, iclass 13, count 2 2006.285.16:57:25.91#ibcon#wrote, iclass 13, count 2 2006.285.16:57:25.91#ibcon#about to read 3, iclass 13, count 2 2006.285.16:57:25.93#ibcon#read 3, iclass 13, count 2 2006.285.16:57:25.93#ibcon#about to read 4, iclass 13, count 2 2006.285.16:57:25.93#ibcon#read 4, iclass 13, count 2 2006.285.16:57:25.93#ibcon#about to read 5, iclass 13, count 2 2006.285.16:57:25.93#ibcon#read 5, iclass 13, count 2 2006.285.16:57:25.93#ibcon#about to read 6, iclass 13, count 2 2006.285.16:57:25.93#ibcon#read 6, iclass 13, count 2 2006.285.16:57:25.93#ibcon#end of sib2, iclass 13, count 2 2006.285.16:57:25.93#ibcon#*mode == 0, iclass 13, count 2 2006.285.16:57:25.93#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.16:57:25.93#ibcon#[25=AT08-03\r\n] 2006.285.16:57:25.93#ibcon#*before write, iclass 13, count 2 2006.285.16:57:25.93#ibcon#enter sib2, iclass 13, count 2 2006.285.16:57:25.93#ibcon#flushed, iclass 13, count 2 2006.285.16:57:25.93#ibcon#about to write, iclass 13, count 2 2006.285.16:57:25.93#ibcon#wrote, iclass 13, count 2 2006.285.16:57:25.93#ibcon#about to read 3, iclass 13, count 2 2006.285.16:57:25.96#ibcon#read 3, iclass 13, count 2 2006.285.16:57:25.96#ibcon#about to read 4, iclass 13, count 2 2006.285.16:57:25.96#ibcon#read 4, iclass 13, count 2 2006.285.16:57:25.96#ibcon#about to read 5, iclass 13, count 2 2006.285.16:57:25.96#ibcon#read 5, iclass 13, count 2 2006.285.16:57:25.96#ibcon#about to read 6, iclass 13, count 2 2006.285.16:57:25.96#ibcon#read 6, iclass 13, count 2 2006.285.16:57:25.96#ibcon#end of sib2, iclass 13, count 2 2006.285.16:57:25.96#ibcon#*after write, iclass 13, count 2 2006.285.16:57:25.96#ibcon#*before return 0, iclass 13, count 2 2006.285.16:57:25.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:57:25.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:57:25.96#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.16:57:25.96#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:25.96#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:57:26.08#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:57:26.08#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:57:26.08#ibcon#enter wrdev, iclass 13, count 0 2006.285.16:57:26.08#ibcon#first serial, iclass 13, count 0 2006.285.16:57:26.08#ibcon#enter sib2, iclass 13, count 0 2006.285.16:57:26.08#ibcon#flushed, iclass 13, count 0 2006.285.16:57:26.08#ibcon#about to write, iclass 13, count 0 2006.285.16:57:26.08#ibcon#wrote, iclass 13, count 0 2006.285.16:57:26.08#ibcon#about to read 3, iclass 13, count 0 2006.285.16:57:26.10#ibcon#read 3, iclass 13, count 0 2006.285.16:57:26.10#ibcon#about to read 4, iclass 13, count 0 2006.285.16:57:26.10#ibcon#read 4, iclass 13, count 0 2006.285.16:57:26.10#ibcon#about to read 5, iclass 13, count 0 2006.285.16:57:26.10#ibcon#read 5, iclass 13, count 0 2006.285.16:57:26.10#ibcon#about to read 6, iclass 13, count 0 2006.285.16:57:26.10#ibcon#read 6, iclass 13, count 0 2006.285.16:57:26.10#ibcon#end of sib2, iclass 13, count 0 2006.285.16:57:26.10#ibcon#*mode == 0, iclass 13, count 0 2006.285.16:57:26.10#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.16:57:26.10#ibcon#[25=USB\r\n] 2006.285.16:57:26.10#ibcon#*before write, iclass 13, count 0 2006.285.16:57:26.10#ibcon#enter sib2, iclass 13, count 0 2006.285.16:57:26.10#ibcon#flushed, iclass 13, count 0 2006.285.16:57:26.10#ibcon#about to write, iclass 13, count 0 2006.285.16:57:26.10#ibcon#wrote, iclass 13, count 0 2006.285.16:57:26.10#ibcon#about to read 3, iclass 13, count 0 2006.285.16:57:26.13#ibcon#read 3, iclass 13, count 0 2006.285.16:57:26.13#ibcon#about to read 4, iclass 13, count 0 2006.285.16:57:26.13#ibcon#read 4, iclass 13, count 0 2006.285.16:57:26.13#ibcon#about to read 5, iclass 13, count 0 2006.285.16:57:26.13#ibcon#read 5, iclass 13, count 0 2006.285.16:57:26.13#ibcon#about to read 6, iclass 13, count 0 2006.285.16:57:26.13#ibcon#read 6, iclass 13, count 0 2006.285.16:57:26.13#ibcon#end of sib2, iclass 13, count 0 2006.285.16:57:26.13#ibcon#*after write, iclass 13, count 0 2006.285.16:57:26.13#ibcon#*before return 0, iclass 13, count 0 2006.285.16:57:26.13#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:57:26.13#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:57:26.13#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.16:57:26.13#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.16:57:26.13$vck44/vblo=1,629.99 2006.285.16:57:26.13#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.16:57:26.13#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.16:57:26.13#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:26.13#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:57:26.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:57:26.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:57:26.13#ibcon#enter wrdev, iclass 15, count 0 2006.285.16:57:26.13#ibcon#first serial, iclass 15, count 0 2006.285.16:57:26.13#ibcon#enter sib2, iclass 15, count 0 2006.285.16:57:26.13#ibcon#flushed, iclass 15, count 0 2006.285.16:57:26.13#ibcon#about to write, iclass 15, count 0 2006.285.16:57:26.13#ibcon#wrote, iclass 15, count 0 2006.285.16:57:26.13#ibcon#about to read 3, iclass 15, count 0 2006.285.16:57:26.15#ibcon#read 3, iclass 15, count 0 2006.285.16:57:26.15#ibcon#about to read 4, iclass 15, count 0 2006.285.16:57:26.15#ibcon#read 4, iclass 15, count 0 2006.285.16:57:26.15#ibcon#about to read 5, iclass 15, count 0 2006.285.16:57:26.15#ibcon#read 5, iclass 15, count 0 2006.285.16:57:26.15#ibcon#about to read 6, iclass 15, count 0 2006.285.16:57:26.15#ibcon#read 6, iclass 15, count 0 2006.285.16:57:26.15#ibcon#end of sib2, iclass 15, count 0 2006.285.16:57:26.15#ibcon#*mode == 0, iclass 15, count 0 2006.285.16:57:26.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.16:57:26.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.16:57:26.15#ibcon#*before write, iclass 15, count 0 2006.285.16:57:26.15#ibcon#enter sib2, iclass 15, count 0 2006.285.16:57:26.15#ibcon#flushed, iclass 15, count 0 2006.285.16:57:26.15#ibcon#about to write, iclass 15, count 0 2006.285.16:57:26.15#ibcon#wrote, iclass 15, count 0 2006.285.16:57:26.15#ibcon#about to read 3, iclass 15, count 0 2006.285.16:57:26.19#ibcon#read 3, iclass 15, count 0 2006.285.16:57:26.19#ibcon#about to read 4, iclass 15, count 0 2006.285.16:57:26.19#ibcon#read 4, iclass 15, count 0 2006.285.16:57:26.19#ibcon#about to read 5, iclass 15, count 0 2006.285.16:57:26.19#ibcon#read 5, iclass 15, count 0 2006.285.16:57:26.19#ibcon#about to read 6, iclass 15, count 0 2006.285.16:57:26.19#ibcon#read 6, iclass 15, count 0 2006.285.16:57:26.19#ibcon#end of sib2, iclass 15, count 0 2006.285.16:57:26.19#ibcon#*after write, iclass 15, count 0 2006.285.16:57:26.19#ibcon#*before return 0, iclass 15, count 0 2006.285.16:57:26.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:57:26.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:57:26.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.16:57:26.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.16:57:26.19$vck44/vb=1,4 2006.285.16:57:26.19#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.16:57:26.19#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.16:57:26.19#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:26.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:57:26.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:57:26.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:57:26.19#ibcon#enter wrdev, iclass 17, count 2 2006.285.16:57:26.19#ibcon#first serial, iclass 17, count 2 2006.285.16:57:26.19#ibcon#enter sib2, iclass 17, count 2 2006.285.16:57:26.19#ibcon#flushed, iclass 17, count 2 2006.285.16:57:26.19#ibcon#about to write, iclass 17, count 2 2006.285.16:57:26.19#ibcon#wrote, iclass 17, count 2 2006.285.16:57:26.19#ibcon#about to read 3, iclass 17, count 2 2006.285.16:57:26.21#ibcon#read 3, iclass 17, count 2 2006.285.16:57:26.21#ibcon#about to read 4, iclass 17, count 2 2006.285.16:57:26.21#ibcon#read 4, iclass 17, count 2 2006.285.16:57:26.21#ibcon#about to read 5, iclass 17, count 2 2006.285.16:57:26.21#ibcon#read 5, iclass 17, count 2 2006.285.16:57:26.21#ibcon#about to read 6, iclass 17, count 2 2006.285.16:57:26.21#ibcon#read 6, iclass 17, count 2 2006.285.16:57:26.21#ibcon#end of sib2, iclass 17, count 2 2006.285.16:57:26.21#ibcon#*mode == 0, iclass 17, count 2 2006.285.16:57:26.21#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.16:57:26.21#ibcon#[27=AT01-04\r\n] 2006.285.16:57:26.21#ibcon#*before write, iclass 17, count 2 2006.285.16:57:26.21#ibcon#enter sib2, iclass 17, count 2 2006.285.16:57:26.21#ibcon#flushed, iclass 17, count 2 2006.285.16:57:26.21#ibcon#about to write, iclass 17, count 2 2006.285.16:57:26.21#ibcon#wrote, iclass 17, count 2 2006.285.16:57:26.21#ibcon#about to read 3, iclass 17, count 2 2006.285.16:57:26.24#ibcon#read 3, iclass 17, count 2 2006.285.16:57:26.24#ibcon#about to read 4, iclass 17, count 2 2006.285.16:57:26.24#ibcon#read 4, iclass 17, count 2 2006.285.16:57:26.24#ibcon#about to read 5, iclass 17, count 2 2006.285.16:57:26.24#ibcon#read 5, iclass 17, count 2 2006.285.16:57:26.24#ibcon#about to read 6, iclass 17, count 2 2006.285.16:57:26.24#ibcon#read 6, iclass 17, count 2 2006.285.16:57:26.24#ibcon#end of sib2, iclass 17, count 2 2006.285.16:57:26.24#ibcon#*after write, iclass 17, count 2 2006.285.16:57:26.24#ibcon#*before return 0, iclass 17, count 2 2006.285.16:57:26.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:57:26.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.16:57:26.24#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.16:57:26.24#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:26.24#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:57:26.26#abcon#<5=/15 0.5 1.1 17.82 951014.9\r\n> 2006.285.16:57:26.28#abcon#{5=INTERFACE CLEAR} 2006.285.16:57:26.34#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:57:26.36#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:57:26.36#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:57:26.36#ibcon#enter wrdev, iclass 17, count 0 2006.285.16:57:26.36#ibcon#first serial, iclass 17, count 0 2006.285.16:57:26.36#ibcon#enter sib2, iclass 17, count 0 2006.285.16:57:26.36#ibcon#flushed, iclass 17, count 0 2006.285.16:57:26.36#ibcon#about to write, iclass 17, count 0 2006.285.16:57:26.36#ibcon#wrote, iclass 17, count 0 2006.285.16:57:26.36#ibcon#about to read 3, iclass 17, count 0 2006.285.16:57:26.38#ibcon#read 3, iclass 17, count 0 2006.285.16:57:26.38#ibcon#about to read 4, iclass 17, count 0 2006.285.16:57:26.38#ibcon#read 4, iclass 17, count 0 2006.285.16:57:26.38#ibcon#about to read 5, iclass 17, count 0 2006.285.16:57:26.38#ibcon#read 5, iclass 17, count 0 2006.285.16:57:26.38#ibcon#about to read 6, iclass 17, count 0 2006.285.16:57:26.38#ibcon#read 6, iclass 17, count 0 2006.285.16:57:26.38#ibcon#end of sib2, iclass 17, count 0 2006.285.16:57:26.38#ibcon#*mode == 0, iclass 17, count 0 2006.285.16:57:26.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.16:57:26.38#ibcon#[27=USB\r\n] 2006.285.16:57:26.38#ibcon#*before write, iclass 17, count 0 2006.285.16:57:26.38#ibcon#enter sib2, iclass 17, count 0 2006.285.16:57:26.38#ibcon#flushed, iclass 17, count 0 2006.285.16:57:26.38#ibcon#about to write, iclass 17, count 0 2006.285.16:57:26.38#ibcon#wrote, iclass 17, count 0 2006.285.16:57:26.38#ibcon#about to read 3, iclass 17, count 0 2006.285.16:57:26.41#ibcon#read 3, iclass 17, count 0 2006.285.16:57:26.41#ibcon#about to read 4, iclass 17, count 0 2006.285.16:57:26.41#ibcon#read 4, iclass 17, count 0 2006.285.16:57:26.41#ibcon#about to read 5, iclass 17, count 0 2006.285.16:57:26.41#ibcon#read 5, iclass 17, count 0 2006.285.16:57:26.41#ibcon#about to read 6, iclass 17, count 0 2006.285.16:57:26.41#ibcon#read 6, iclass 17, count 0 2006.285.16:57:26.41#ibcon#end of sib2, iclass 17, count 0 2006.285.16:57:26.41#ibcon#*after write, iclass 17, count 0 2006.285.16:57:26.41#ibcon#*before return 0, iclass 17, count 0 2006.285.16:57:26.41#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:57:26.41#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.16:57:26.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.16:57:26.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.16:57:26.41$vck44/vblo=2,634.99 2006.285.16:57:26.41#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.16:57:26.41#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.16:57:26.41#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:26.41#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:57:26.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:57:26.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:57:26.41#ibcon#enter wrdev, iclass 23, count 0 2006.285.16:57:26.41#ibcon#first serial, iclass 23, count 0 2006.285.16:57:26.41#ibcon#enter sib2, iclass 23, count 0 2006.285.16:57:26.41#ibcon#flushed, iclass 23, count 0 2006.285.16:57:26.41#ibcon#about to write, iclass 23, count 0 2006.285.16:57:26.41#ibcon#wrote, iclass 23, count 0 2006.285.16:57:26.41#ibcon#about to read 3, iclass 23, count 0 2006.285.16:57:26.43#ibcon#read 3, iclass 23, count 0 2006.285.16:57:26.43#ibcon#about to read 4, iclass 23, count 0 2006.285.16:57:26.43#ibcon#read 4, iclass 23, count 0 2006.285.16:57:26.43#ibcon#about to read 5, iclass 23, count 0 2006.285.16:57:26.43#ibcon#read 5, iclass 23, count 0 2006.285.16:57:26.43#ibcon#about to read 6, iclass 23, count 0 2006.285.16:57:26.43#ibcon#read 6, iclass 23, count 0 2006.285.16:57:26.43#ibcon#end of sib2, iclass 23, count 0 2006.285.16:57:26.43#ibcon#*mode == 0, iclass 23, count 0 2006.285.16:57:26.43#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.16:57:26.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.16:57:26.43#ibcon#*before write, iclass 23, count 0 2006.285.16:57:26.43#ibcon#enter sib2, iclass 23, count 0 2006.285.16:57:26.43#ibcon#flushed, iclass 23, count 0 2006.285.16:57:26.43#ibcon#about to write, iclass 23, count 0 2006.285.16:57:26.43#ibcon#wrote, iclass 23, count 0 2006.285.16:57:26.43#ibcon#about to read 3, iclass 23, count 0 2006.285.16:57:26.47#ibcon#read 3, iclass 23, count 0 2006.285.16:57:26.47#ibcon#about to read 4, iclass 23, count 0 2006.285.16:57:26.47#ibcon#read 4, iclass 23, count 0 2006.285.16:57:26.47#ibcon#about to read 5, iclass 23, count 0 2006.285.16:57:26.47#ibcon#read 5, iclass 23, count 0 2006.285.16:57:26.47#ibcon#about to read 6, iclass 23, count 0 2006.285.16:57:26.47#ibcon#read 6, iclass 23, count 0 2006.285.16:57:26.47#ibcon#end of sib2, iclass 23, count 0 2006.285.16:57:26.47#ibcon#*after write, iclass 23, count 0 2006.285.16:57:26.47#ibcon#*before return 0, iclass 23, count 0 2006.285.16:57:26.47#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:57:26.47#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.16:57:26.47#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.16:57:26.47#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.16:57:26.47$vck44/vb=2,5 2006.285.16:57:26.75#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.16:57:26.75#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.16:57:26.75#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:26.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:57:26.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:57:26.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:57:26.75#ibcon#enter wrdev, iclass 25, count 2 2006.285.16:57:26.75#ibcon#first serial, iclass 25, count 2 2006.285.16:57:26.75#ibcon#enter sib2, iclass 25, count 2 2006.285.16:57:26.75#ibcon#flushed, iclass 25, count 2 2006.285.16:57:26.75#ibcon#about to write, iclass 25, count 2 2006.285.16:57:26.75#ibcon#wrote, iclass 25, count 2 2006.285.16:57:26.75#ibcon#about to read 3, iclass 25, count 2 2006.285.16:57:26.77#ibcon#read 3, iclass 25, count 2 2006.285.16:57:26.77#ibcon#about to read 4, iclass 25, count 2 2006.285.16:57:26.77#ibcon#read 4, iclass 25, count 2 2006.285.16:57:26.77#ibcon#about to read 5, iclass 25, count 2 2006.285.16:57:26.77#ibcon#read 5, iclass 25, count 2 2006.285.16:57:26.77#ibcon#about to read 6, iclass 25, count 2 2006.285.16:57:26.77#ibcon#read 6, iclass 25, count 2 2006.285.16:57:26.77#ibcon#end of sib2, iclass 25, count 2 2006.285.16:57:26.77#ibcon#*mode == 0, iclass 25, count 2 2006.285.16:57:26.77#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.16:57:26.77#ibcon#[27=AT02-05\r\n] 2006.285.16:57:26.77#ibcon#*before write, iclass 25, count 2 2006.285.16:57:26.77#ibcon#enter sib2, iclass 25, count 2 2006.285.16:57:26.77#ibcon#flushed, iclass 25, count 2 2006.285.16:57:26.77#ibcon#about to write, iclass 25, count 2 2006.285.16:57:26.77#ibcon#wrote, iclass 25, count 2 2006.285.16:57:26.77#ibcon#about to read 3, iclass 25, count 2 2006.285.16:57:26.80#ibcon#read 3, iclass 25, count 2 2006.285.16:57:26.80#ibcon#about to read 4, iclass 25, count 2 2006.285.16:57:26.80#ibcon#read 4, iclass 25, count 2 2006.285.16:57:26.80#ibcon#about to read 5, iclass 25, count 2 2006.285.16:57:26.80#ibcon#read 5, iclass 25, count 2 2006.285.16:57:26.80#ibcon#about to read 6, iclass 25, count 2 2006.285.16:57:26.80#ibcon#read 6, iclass 25, count 2 2006.285.16:57:26.80#ibcon#end of sib2, iclass 25, count 2 2006.285.16:57:26.80#ibcon#*after write, iclass 25, count 2 2006.285.16:57:26.80#ibcon#*before return 0, iclass 25, count 2 2006.285.16:57:26.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:57:26.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.16:57:26.80#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.16:57:26.80#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:26.80#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:57:26.92#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:57:26.92#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:57:26.92#ibcon#enter wrdev, iclass 25, count 0 2006.285.16:57:26.92#ibcon#first serial, iclass 25, count 0 2006.285.16:57:26.92#ibcon#enter sib2, iclass 25, count 0 2006.285.16:57:26.92#ibcon#flushed, iclass 25, count 0 2006.285.16:57:26.92#ibcon#about to write, iclass 25, count 0 2006.285.16:57:26.92#ibcon#wrote, iclass 25, count 0 2006.285.16:57:26.92#ibcon#about to read 3, iclass 25, count 0 2006.285.16:57:26.94#ibcon#read 3, iclass 25, count 0 2006.285.16:57:26.94#ibcon#about to read 4, iclass 25, count 0 2006.285.16:57:26.94#ibcon#read 4, iclass 25, count 0 2006.285.16:57:26.94#ibcon#about to read 5, iclass 25, count 0 2006.285.16:57:26.94#ibcon#read 5, iclass 25, count 0 2006.285.16:57:26.94#ibcon#about to read 6, iclass 25, count 0 2006.285.16:57:26.94#ibcon#read 6, iclass 25, count 0 2006.285.16:57:26.94#ibcon#end of sib2, iclass 25, count 0 2006.285.16:57:26.94#ibcon#*mode == 0, iclass 25, count 0 2006.285.16:57:26.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.16:57:26.94#ibcon#[27=USB\r\n] 2006.285.16:57:26.94#ibcon#*before write, iclass 25, count 0 2006.285.16:57:26.94#ibcon#enter sib2, iclass 25, count 0 2006.285.16:57:26.94#ibcon#flushed, iclass 25, count 0 2006.285.16:57:26.94#ibcon#about to write, iclass 25, count 0 2006.285.16:57:26.94#ibcon#wrote, iclass 25, count 0 2006.285.16:57:26.94#ibcon#about to read 3, iclass 25, count 0 2006.285.16:57:26.97#ibcon#read 3, iclass 25, count 0 2006.285.16:57:26.97#ibcon#about to read 4, iclass 25, count 0 2006.285.16:57:26.97#ibcon#read 4, iclass 25, count 0 2006.285.16:57:26.97#ibcon#about to read 5, iclass 25, count 0 2006.285.16:57:26.97#ibcon#read 5, iclass 25, count 0 2006.285.16:57:26.97#ibcon#about to read 6, iclass 25, count 0 2006.285.16:57:26.97#ibcon#read 6, iclass 25, count 0 2006.285.16:57:26.97#ibcon#end of sib2, iclass 25, count 0 2006.285.16:57:26.97#ibcon#*after write, iclass 25, count 0 2006.285.16:57:26.97#ibcon#*before return 0, iclass 25, count 0 2006.285.16:57:26.97#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:57:26.97#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.16:57:26.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.16:57:26.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.16:57:26.97$vck44/vblo=3,649.99 2006.285.16:57:26.97#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.16:57:26.97#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.16:57:26.97#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:26.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:57:26.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:57:26.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:57:26.97#ibcon#enter wrdev, iclass 27, count 0 2006.285.16:57:26.97#ibcon#first serial, iclass 27, count 0 2006.285.16:57:26.97#ibcon#enter sib2, iclass 27, count 0 2006.285.16:57:26.97#ibcon#flushed, iclass 27, count 0 2006.285.16:57:26.97#ibcon#about to write, iclass 27, count 0 2006.285.16:57:26.97#ibcon#wrote, iclass 27, count 0 2006.285.16:57:26.97#ibcon#about to read 3, iclass 27, count 0 2006.285.16:57:26.99#ibcon#read 3, iclass 27, count 0 2006.285.16:57:26.99#ibcon#about to read 4, iclass 27, count 0 2006.285.16:57:26.99#ibcon#read 4, iclass 27, count 0 2006.285.16:57:26.99#ibcon#about to read 5, iclass 27, count 0 2006.285.16:57:26.99#ibcon#read 5, iclass 27, count 0 2006.285.16:57:26.99#ibcon#about to read 6, iclass 27, count 0 2006.285.16:57:26.99#ibcon#read 6, iclass 27, count 0 2006.285.16:57:26.99#ibcon#end of sib2, iclass 27, count 0 2006.285.16:57:26.99#ibcon#*mode == 0, iclass 27, count 0 2006.285.16:57:26.99#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.16:57:26.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.16:57:26.99#ibcon#*before write, iclass 27, count 0 2006.285.16:57:26.99#ibcon#enter sib2, iclass 27, count 0 2006.285.16:57:26.99#ibcon#flushed, iclass 27, count 0 2006.285.16:57:26.99#ibcon#about to write, iclass 27, count 0 2006.285.16:57:26.99#ibcon#wrote, iclass 27, count 0 2006.285.16:57:26.99#ibcon#about to read 3, iclass 27, count 0 2006.285.16:57:27.03#ibcon#read 3, iclass 27, count 0 2006.285.16:57:27.03#ibcon#about to read 4, iclass 27, count 0 2006.285.16:57:27.03#ibcon#read 4, iclass 27, count 0 2006.285.16:57:27.03#ibcon#about to read 5, iclass 27, count 0 2006.285.16:57:27.03#ibcon#read 5, iclass 27, count 0 2006.285.16:57:27.03#ibcon#about to read 6, iclass 27, count 0 2006.285.16:57:27.03#ibcon#read 6, iclass 27, count 0 2006.285.16:57:27.03#ibcon#end of sib2, iclass 27, count 0 2006.285.16:57:27.03#ibcon#*after write, iclass 27, count 0 2006.285.16:57:27.03#ibcon#*before return 0, iclass 27, count 0 2006.285.16:57:27.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:57:27.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.16:57:27.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.16:57:27.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.16:57:27.03$vck44/vb=3,4 2006.285.16:57:27.03#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.16:57:27.03#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.16:57:27.03#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:27.03#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:57:27.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:57:27.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:57:27.09#ibcon#enter wrdev, iclass 29, count 2 2006.285.16:57:27.09#ibcon#first serial, iclass 29, count 2 2006.285.16:57:27.09#ibcon#enter sib2, iclass 29, count 2 2006.285.16:57:27.09#ibcon#flushed, iclass 29, count 2 2006.285.16:57:27.09#ibcon#about to write, iclass 29, count 2 2006.285.16:57:27.09#ibcon#wrote, iclass 29, count 2 2006.285.16:57:27.09#ibcon#about to read 3, iclass 29, count 2 2006.285.16:57:27.11#ibcon#read 3, iclass 29, count 2 2006.285.16:57:27.11#ibcon#about to read 4, iclass 29, count 2 2006.285.16:57:27.11#ibcon#read 4, iclass 29, count 2 2006.285.16:57:27.11#ibcon#about to read 5, iclass 29, count 2 2006.285.16:57:27.11#ibcon#read 5, iclass 29, count 2 2006.285.16:57:27.11#ibcon#about to read 6, iclass 29, count 2 2006.285.16:57:27.11#ibcon#read 6, iclass 29, count 2 2006.285.16:57:27.11#ibcon#end of sib2, iclass 29, count 2 2006.285.16:57:27.11#ibcon#*mode == 0, iclass 29, count 2 2006.285.16:57:27.11#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.16:57:27.11#ibcon#[27=AT03-04\r\n] 2006.285.16:57:27.11#ibcon#*before write, iclass 29, count 2 2006.285.16:57:27.11#ibcon#enter sib2, iclass 29, count 2 2006.285.16:57:27.11#ibcon#flushed, iclass 29, count 2 2006.285.16:57:27.11#ibcon#about to write, iclass 29, count 2 2006.285.16:57:27.11#ibcon#wrote, iclass 29, count 2 2006.285.16:57:27.11#ibcon#about to read 3, iclass 29, count 2 2006.285.16:57:27.14#ibcon#read 3, iclass 29, count 2 2006.285.16:57:27.14#ibcon#about to read 4, iclass 29, count 2 2006.285.16:57:27.14#ibcon#read 4, iclass 29, count 2 2006.285.16:57:27.14#ibcon#about to read 5, iclass 29, count 2 2006.285.16:57:27.14#ibcon#read 5, iclass 29, count 2 2006.285.16:57:27.14#ibcon#about to read 6, iclass 29, count 2 2006.285.16:57:27.14#ibcon#read 6, iclass 29, count 2 2006.285.16:57:27.14#ibcon#end of sib2, iclass 29, count 2 2006.285.16:57:27.14#ibcon#*after write, iclass 29, count 2 2006.285.16:57:27.14#ibcon#*before return 0, iclass 29, count 2 2006.285.16:57:27.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:57:27.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.16:57:27.14#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.16:57:27.14#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:27.14#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:57:27.26#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:57:27.26#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:57:27.26#ibcon#enter wrdev, iclass 29, count 0 2006.285.16:57:27.26#ibcon#first serial, iclass 29, count 0 2006.285.16:57:27.26#ibcon#enter sib2, iclass 29, count 0 2006.285.16:57:27.26#ibcon#flushed, iclass 29, count 0 2006.285.16:57:27.26#ibcon#about to write, iclass 29, count 0 2006.285.16:57:27.26#ibcon#wrote, iclass 29, count 0 2006.285.16:57:27.26#ibcon#about to read 3, iclass 29, count 0 2006.285.16:57:27.28#ibcon#read 3, iclass 29, count 0 2006.285.16:57:27.28#ibcon#about to read 4, iclass 29, count 0 2006.285.16:57:27.28#ibcon#read 4, iclass 29, count 0 2006.285.16:57:27.28#ibcon#about to read 5, iclass 29, count 0 2006.285.16:57:27.28#ibcon#read 5, iclass 29, count 0 2006.285.16:57:27.28#ibcon#about to read 6, iclass 29, count 0 2006.285.16:57:27.28#ibcon#read 6, iclass 29, count 0 2006.285.16:57:27.28#ibcon#end of sib2, iclass 29, count 0 2006.285.16:57:27.28#ibcon#*mode == 0, iclass 29, count 0 2006.285.16:57:27.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.16:57:27.28#ibcon#[27=USB\r\n] 2006.285.16:57:27.28#ibcon#*before write, iclass 29, count 0 2006.285.16:57:27.28#ibcon#enter sib2, iclass 29, count 0 2006.285.16:57:27.28#ibcon#flushed, iclass 29, count 0 2006.285.16:57:27.28#ibcon#about to write, iclass 29, count 0 2006.285.16:57:27.28#ibcon#wrote, iclass 29, count 0 2006.285.16:57:27.28#ibcon#about to read 3, iclass 29, count 0 2006.285.16:57:27.31#ibcon#read 3, iclass 29, count 0 2006.285.16:57:27.31#ibcon#about to read 4, iclass 29, count 0 2006.285.16:57:27.31#ibcon#read 4, iclass 29, count 0 2006.285.16:57:27.31#ibcon#about to read 5, iclass 29, count 0 2006.285.16:57:27.31#ibcon#read 5, iclass 29, count 0 2006.285.16:57:27.31#ibcon#about to read 6, iclass 29, count 0 2006.285.16:57:27.31#ibcon#read 6, iclass 29, count 0 2006.285.16:57:27.31#ibcon#end of sib2, iclass 29, count 0 2006.285.16:57:27.31#ibcon#*after write, iclass 29, count 0 2006.285.16:57:27.31#ibcon#*before return 0, iclass 29, count 0 2006.285.16:57:27.31#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:57:27.31#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.16:57:27.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.16:57:27.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.16:57:27.31$vck44/vblo=4,679.99 2006.285.16:57:27.31#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.16:57:27.31#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.16:57:27.31#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:27.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:57:27.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:57:27.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:57:27.31#ibcon#enter wrdev, iclass 31, count 0 2006.285.16:57:27.31#ibcon#first serial, iclass 31, count 0 2006.285.16:57:27.31#ibcon#enter sib2, iclass 31, count 0 2006.285.16:57:27.31#ibcon#flushed, iclass 31, count 0 2006.285.16:57:27.31#ibcon#about to write, iclass 31, count 0 2006.285.16:57:27.31#ibcon#wrote, iclass 31, count 0 2006.285.16:57:27.31#ibcon#about to read 3, iclass 31, count 0 2006.285.16:57:27.33#ibcon#read 3, iclass 31, count 0 2006.285.16:57:27.33#ibcon#about to read 4, iclass 31, count 0 2006.285.16:57:27.33#ibcon#read 4, iclass 31, count 0 2006.285.16:57:27.33#ibcon#about to read 5, iclass 31, count 0 2006.285.16:57:27.33#ibcon#read 5, iclass 31, count 0 2006.285.16:57:27.33#ibcon#about to read 6, iclass 31, count 0 2006.285.16:57:27.33#ibcon#read 6, iclass 31, count 0 2006.285.16:57:27.33#ibcon#end of sib2, iclass 31, count 0 2006.285.16:57:27.33#ibcon#*mode == 0, iclass 31, count 0 2006.285.16:57:27.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.16:57:27.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.16:57:27.33#ibcon#*before write, iclass 31, count 0 2006.285.16:57:27.33#ibcon#enter sib2, iclass 31, count 0 2006.285.16:57:27.33#ibcon#flushed, iclass 31, count 0 2006.285.16:57:27.33#ibcon#about to write, iclass 31, count 0 2006.285.16:57:27.33#ibcon#wrote, iclass 31, count 0 2006.285.16:57:27.33#ibcon#about to read 3, iclass 31, count 0 2006.285.16:57:27.37#ibcon#read 3, iclass 31, count 0 2006.285.16:57:27.37#ibcon#about to read 4, iclass 31, count 0 2006.285.16:57:27.37#ibcon#read 4, iclass 31, count 0 2006.285.16:57:27.37#ibcon#about to read 5, iclass 31, count 0 2006.285.16:57:27.37#ibcon#read 5, iclass 31, count 0 2006.285.16:57:27.37#ibcon#about to read 6, iclass 31, count 0 2006.285.16:57:27.37#ibcon#read 6, iclass 31, count 0 2006.285.16:57:27.37#ibcon#end of sib2, iclass 31, count 0 2006.285.16:57:27.37#ibcon#*after write, iclass 31, count 0 2006.285.16:57:27.37#ibcon#*before return 0, iclass 31, count 0 2006.285.16:57:27.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:57:27.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.16:57:27.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.16:57:27.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.16:57:27.37$vck44/vb=4,5 2006.285.16:57:27.37#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.16:57:27.37#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.16:57:27.37#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:27.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:57:27.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:57:27.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:57:27.43#ibcon#enter wrdev, iclass 33, count 2 2006.285.16:57:27.43#ibcon#first serial, iclass 33, count 2 2006.285.16:57:27.43#ibcon#enter sib2, iclass 33, count 2 2006.285.16:57:27.43#ibcon#flushed, iclass 33, count 2 2006.285.16:57:27.43#ibcon#about to write, iclass 33, count 2 2006.285.16:57:27.43#ibcon#wrote, iclass 33, count 2 2006.285.16:57:27.43#ibcon#about to read 3, iclass 33, count 2 2006.285.16:57:27.45#ibcon#read 3, iclass 33, count 2 2006.285.16:57:27.45#ibcon#about to read 4, iclass 33, count 2 2006.285.16:57:27.45#ibcon#read 4, iclass 33, count 2 2006.285.16:57:27.45#ibcon#about to read 5, iclass 33, count 2 2006.285.16:57:27.45#ibcon#read 5, iclass 33, count 2 2006.285.16:57:27.45#ibcon#about to read 6, iclass 33, count 2 2006.285.16:57:27.45#ibcon#read 6, iclass 33, count 2 2006.285.16:57:27.45#ibcon#end of sib2, iclass 33, count 2 2006.285.16:57:27.45#ibcon#*mode == 0, iclass 33, count 2 2006.285.16:57:27.45#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.16:57:27.45#ibcon#[27=AT04-05\r\n] 2006.285.16:57:27.45#ibcon#*before write, iclass 33, count 2 2006.285.16:57:27.45#ibcon#enter sib2, iclass 33, count 2 2006.285.16:57:27.45#ibcon#flushed, iclass 33, count 2 2006.285.16:57:27.45#ibcon#about to write, iclass 33, count 2 2006.285.16:57:27.45#ibcon#wrote, iclass 33, count 2 2006.285.16:57:27.45#ibcon#about to read 3, iclass 33, count 2 2006.285.16:57:27.48#ibcon#read 3, iclass 33, count 2 2006.285.16:57:27.48#ibcon#about to read 4, iclass 33, count 2 2006.285.16:57:27.48#ibcon#read 4, iclass 33, count 2 2006.285.16:57:27.48#ibcon#about to read 5, iclass 33, count 2 2006.285.16:57:27.48#ibcon#read 5, iclass 33, count 2 2006.285.16:57:27.48#ibcon#about to read 6, iclass 33, count 2 2006.285.16:57:27.48#ibcon#read 6, iclass 33, count 2 2006.285.16:57:27.48#ibcon#end of sib2, iclass 33, count 2 2006.285.16:57:27.48#ibcon#*after write, iclass 33, count 2 2006.285.16:57:27.48#ibcon#*before return 0, iclass 33, count 2 2006.285.16:57:27.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:57:27.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.16:57:27.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.16:57:27.48#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:27.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:57:27.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:57:27.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:57:27.60#ibcon#enter wrdev, iclass 33, count 0 2006.285.16:57:27.60#ibcon#first serial, iclass 33, count 0 2006.285.16:57:27.60#ibcon#enter sib2, iclass 33, count 0 2006.285.16:57:27.60#ibcon#flushed, iclass 33, count 0 2006.285.16:57:27.60#ibcon#about to write, iclass 33, count 0 2006.285.16:57:27.60#ibcon#wrote, iclass 33, count 0 2006.285.16:57:27.60#ibcon#about to read 3, iclass 33, count 0 2006.285.16:57:27.62#ibcon#read 3, iclass 33, count 0 2006.285.16:57:27.62#ibcon#about to read 4, iclass 33, count 0 2006.285.16:57:27.62#ibcon#read 4, iclass 33, count 0 2006.285.16:57:27.62#ibcon#about to read 5, iclass 33, count 0 2006.285.16:57:27.62#ibcon#read 5, iclass 33, count 0 2006.285.16:57:27.62#ibcon#about to read 6, iclass 33, count 0 2006.285.16:57:27.62#ibcon#read 6, iclass 33, count 0 2006.285.16:57:27.62#ibcon#end of sib2, iclass 33, count 0 2006.285.16:57:27.62#ibcon#*mode == 0, iclass 33, count 0 2006.285.16:57:27.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.16:57:27.62#ibcon#[27=USB\r\n] 2006.285.16:57:27.62#ibcon#*before write, iclass 33, count 0 2006.285.16:57:27.62#ibcon#enter sib2, iclass 33, count 0 2006.285.16:57:27.62#ibcon#flushed, iclass 33, count 0 2006.285.16:57:27.62#ibcon#about to write, iclass 33, count 0 2006.285.16:57:27.62#ibcon#wrote, iclass 33, count 0 2006.285.16:57:27.62#ibcon#about to read 3, iclass 33, count 0 2006.285.16:57:27.65#ibcon#read 3, iclass 33, count 0 2006.285.16:57:27.65#ibcon#about to read 4, iclass 33, count 0 2006.285.16:57:27.65#ibcon#read 4, iclass 33, count 0 2006.285.16:57:27.65#ibcon#about to read 5, iclass 33, count 0 2006.285.16:57:27.65#ibcon#read 5, iclass 33, count 0 2006.285.16:57:27.65#ibcon#about to read 6, iclass 33, count 0 2006.285.16:57:27.65#ibcon#read 6, iclass 33, count 0 2006.285.16:57:27.65#ibcon#end of sib2, iclass 33, count 0 2006.285.16:57:27.65#ibcon#*after write, iclass 33, count 0 2006.285.16:57:27.65#ibcon#*before return 0, iclass 33, count 0 2006.285.16:57:27.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:57:27.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.16:57:27.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.16:57:27.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.16:57:27.65$vck44/vblo=5,709.99 2006.285.16:57:27.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.16:57:27.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.16:57:27.65#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:27.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:57:27.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:57:27.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:57:27.65#ibcon#enter wrdev, iclass 35, count 0 2006.285.16:57:27.65#ibcon#first serial, iclass 35, count 0 2006.285.16:57:27.65#ibcon#enter sib2, iclass 35, count 0 2006.285.16:57:27.65#ibcon#flushed, iclass 35, count 0 2006.285.16:57:27.65#ibcon#about to write, iclass 35, count 0 2006.285.16:57:27.65#ibcon#wrote, iclass 35, count 0 2006.285.16:57:27.65#ibcon#about to read 3, iclass 35, count 0 2006.285.16:57:27.67#ibcon#read 3, iclass 35, count 0 2006.285.16:57:27.67#ibcon#about to read 4, iclass 35, count 0 2006.285.16:57:27.67#ibcon#read 4, iclass 35, count 0 2006.285.16:57:27.67#ibcon#about to read 5, iclass 35, count 0 2006.285.16:57:27.67#ibcon#read 5, iclass 35, count 0 2006.285.16:57:27.67#ibcon#about to read 6, iclass 35, count 0 2006.285.16:57:27.67#ibcon#read 6, iclass 35, count 0 2006.285.16:57:27.67#ibcon#end of sib2, iclass 35, count 0 2006.285.16:57:27.67#ibcon#*mode == 0, iclass 35, count 0 2006.285.16:57:27.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.16:57:27.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.16:57:27.67#ibcon#*before write, iclass 35, count 0 2006.285.16:57:27.67#ibcon#enter sib2, iclass 35, count 0 2006.285.16:57:27.67#ibcon#flushed, iclass 35, count 0 2006.285.16:57:27.67#ibcon#about to write, iclass 35, count 0 2006.285.16:57:27.67#ibcon#wrote, iclass 35, count 0 2006.285.16:57:27.67#ibcon#about to read 3, iclass 35, count 0 2006.285.16:57:27.71#ibcon#read 3, iclass 35, count 0 2006.285.16:57:27.71#ibcon#about to read 4, iclass 35, count 0 2006.285.16:57:27.71#ibcon#read 4, iclass 35, count 0 2006.285.16:57:27.71#ibcon#about to read 5, iclass 35, count 0 2006.285.16:57:27.71#ibcon#read 5, iclass 35, count 0 2006.285.16:57:27.71#ibcon#about to read 6, iclass 35, count 0 2006.285.16:57:27.71#ibcon#read 6, iclass 35, count 0 2006.285.16:57:27.71#ibcon#end of sib2, iclass 35, count 0 2006.285.16:57:27.71#ibcon#*after write, iclass 35, count 0 2006.285.16:57:27.71#ibcon#*before return 0, iclass 35, count 0 2006.285.16:57:27.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:57:27.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.16:57:27.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.16:57:27.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.16:57:27.71$vck44/vb=5,4 2006.285.16:57:27.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.16:57:27.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.16:57:27.71#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:27.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:57:27.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:57:27.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:57:27.77#ibcon#enter wrdev, iclass 37, count 2 2006.285.16:57:27.77#ibcon#first serial, iclass 37, count 2 2006.285.16:57:27.77#ibcon#enter sib2, iclass 37, count 2 2006.285.16:57:27.77#ibcon#flushed, iclass 37, count 2 2006.285.16:57:27.77#ibcon#about to write, iclass 37, count 2 2006.285.16:57:27.77#ibcon#wrote, iclass 37, count 2 2006.285.16:57:27.77#ibcon#about to read 3, iclass 37, count 2 2006.285.16:57:27.79#ibcon#read 3, iclass 37, count 2 2006.285.16:57:27.79#ibcon#about to read 4, iclass 37, count 2 2006.285.16:57:27.79#ibcon#read 4, iclass 37, count 2 2006.285.16:57:27.79#ibcon#about to read 5, iclass 37, count 2 2006.285.16:57:27.79#ibcon#read 5, iclass 37, count 2 2006.285.16:57:27.79#ibcon#about to read 6, iclass 37, count 2 2006.285.16:57:27.79#ibcon#read 6, iclass 37, count 2 2006.285.16:57:27.79#ibcon#end of sib2, iclass 37, count 2 2006.285.16:57:27.79#ibcon#*mode == 0, iclass 37, count 2 2006.285.16:57:27.79#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.16:57:27.79#ibcon#[27=AT05-04\r\n] 2006.285.16:57:27.79#ibcon#*before write, iclass 37, count 2 2006.285.16:57:27.79#ibcon#enter sib2, iclass 37, count 2 2006.285.16:57:27.79#ibcon#flushed, iclass 37, count 2 2006.285.16:57:27.79#ibcon#about to write, iclass 37, count 2 2006.285.16:57:27.79#ibcon#wrote, iclass 37, count 2 2006.285.16:57:27.79#ibcon#about to read 3, iclass 37, count 2 2006.285.16:57:27.82#ibcon#read 3, iclass 37, count 2 2006.285.16:57:27.82#ibcon#about to read 4, iclass 37, count 2 2006.285.16:57:27.82#ibcon#read 4, iclass 37, count 2 2006.285.16:57:27.82#ibcon#about to read 5, iclass 37, count 2 2006.285.16:57:27.82#ibcon#read 5, iclass 37, count 2 2006.285.16:57:27.82#ibcon#about to read 6, iclass 37, count 2 2006.285.16:57:27.82#ibcon#read 6, iclass 37, count 2 2006.285.16:57:27.82#ibcon#end of sib2, iclass 37, count 2 2006.285.16:57:27.82#ibcon#*after write, iclass 37, count 2 2006.285.16:57:27.82#ibcon#*before return 0, iclass 37, count 2 2006.285.16:57:27.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:57:27.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.16:57:27.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.16:57:27.82#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:27.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:57:27.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:57:27.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:57:27.94#ibcon#enter wrdev, iclass 37, count 0 2006.285.16:57:27.94#ibcon#first serial, iclass 37, count 0 2006.285.16:57:27.94#ibcon#enter sib2, iclass 37, count 0 2006.285.16:57:27.94#ibcon#flushed, iclass 37, count 0 2006.285.16:57:27.94#ibcon#about to write, iclass 37, count 0 2006.285.16:57:27.94#ibcon#wrote, iclass 37, count 0 2006.285.16:57:27.94#ibcon#about to read 3, iclass 37, count 0 2006.285.16:57:27.96#ibcon#read 3, iclass 37, count 0 2006.285.16:57:27.96#ibcon#about to read 4, iclass 37, count 0 2006.285.16:57:27.96#ibcon#read 4, iclass 37, count 0 2006.285.16:57:27.96#ibcon#about to read 5, iclass 37, count 0 2006.285.16:57:27.96#ibcon#read 5, iclass 37, count 0 2006.285.16:57:27.96#ibcon#about to read 6, iclass 37, count 0 2006.285.16:57:27.96#ibcon#read 6, iclass 37, count 0 2006.285.16:57:27.96#ibcon#end of sib2, iclass 37, count 0 2006.285.16:57:27.96#ibcon#*mode == 0, iclass 37, count 0 2006.285.16:57:27.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.16:57:27.96#ibcon#[27=USB\r\n] 2006.285.16:57:27.96#ibcon#*before write, iclass 37, count 0 2006.285.16:57:27.96#ibcon#enter sib2, iclass 37, count 0 2006.285.16:57:27.96#ibcon#flushed, iclass 37, count 0 2006.285.16:57:27.96#ibcon#about to write, iclass 37, count 0 2006.285.16:57:27.96#ibcon#wrote, iclass 37, count 0 2006.285.16:57:27.96#ibcon#about to read 3, iclass 37, count 0 2006.285.16:57:27.99#ibcon#read 3, iclass 37, count 0 2006.285.16:57:27.99#ibcon#about to read 4, iclass 37, count 0 2006.285.16:57:27.99#ibcon#read 4, iclass 37, count 0 2006.285.16:57:27.99#ibcon#about to read 5, iclass 37, count 0 2006.285.16:57:27.99#ibcon#read 5, iclass 37, count 0 2006.285.16:57:27.99#ibcon#about to read 6, iclass 37, count 0 2006.285.16:57:27.99#ibcon#read 6, iclass 37, count 0 2006.285.16:57:27.99#ibcon#end of sib2, iclass 37, count 0 2006.285.16:57:27.99#ibcon#*after write, iclass 37, count 0 2006.285.16:57:27.99#ibcon#*before return 0, iclass 37, count 0 2006.285.16:57:27.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:57:27.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.16:57:27.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.16:57:27.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.16:57:27.99$vck44/vblo=6,719.99 2006.285.16:57:27.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.16:57:27.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.16:57:27.99#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:27.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:57:27.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:57:27.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:57:27.99#ibcon#enter wrdev, iclass 39, count 0 2006.285.16:57:27.99#ibcon#first serial, iclass 39, count 0 2006.285.16:57:27.99#ibcon#enter sib2, iclass 39, count 0 2006.285.16:57:27.99#ibcon#flushed, iclass 39, count 0 2006.285.16:57:27.99#ibcon#about to write, iclass 39, count 0 2006.285.16:57:27.99#ibcon#wrote, iclass 39, count 0 2006.285.16:57:27.99#ibcon#about to read 3, iclass 39, count 0 2006.285.16:57:28.01#ibcon#read 3, iclass 39, count 0 2006.285.16:57:28.01#ibcon#about to read 4, iclass 39, count 0 2006.285.16:57:28.01#ibcon#read 4, iclass 39, count 0 2006.285.16:57:28.01#ibcon#about to read 5, iclass 39, count 0 2006.285.16:57:28.01#ibcon#read 5, iclass 39, count 0 2006.285.16:57:28.01#ibcon#about to read 6, iclass 39, count 0 2006.285.16:57:28.01#ibcon#read 6, iclass 39, count 0 2006.285.16:57:28.01#ibcon#end of sib2, iclass 39, count 0 2006.285.16:57:28.01#ibcon#*mode == 0, iclass 39, count 0 2006.285.16:57:28.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.16:57:28.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.16:57:28.01#ibcon#*before write, iclass 39, count 0 2006.285.16:57:28.01#ibcon#enter sib2, iclass 39, count 0 2006.285.16:57:28.01#ibcon#flushed, iclass 39, count 0 2006.285.16:57:28.01#ibcon#about to write, iclass 39, count 0 2006.285.16:57:28.01#ibcon#wrote, iclass 39, count 0 2006.285.16:57:28.01#ibcon#about to read 3, iclass 39, count 0 2006.285.16:57:28.05#ibcon#read 3, iclass 39, count 0 2006.285.16:57:28.05#ibcon#about to read 4, iclass 39, count 0 2006.285.16:57:28.05#ibcon#read 4, iclass 39, count 0 2006.285.16:57:28.05#ibcon#about to read 5, iclass 39, count 0 2006.285.16:57:28.05#ibcon#read 5, iclass 39, count 0 2006.285.16:57:28.05#ibcon#about to read 6, iclass 39, count 0 2006.285.16:57:28.05#ibcon#read 6, iclass 39, count 0 2006.285.16:57:28.05#ibcon#end of sib2, iclass 39, count 0 2006.285.16:57:28.05#ibcon#*after write, iclass 39, count 0 2006.285.16:57:28.05#ibcon#*before return 0, iclass 39, count 0 2006.285.16:57:28.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:57:28.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.16:57:28.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.16:57:28.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.16:57:28.05$vck44/vb=6,3 2006.285.16:57:28.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.16:57:28.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.16:57:28.05#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:28.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:57:28.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:57:28.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:57:28.11#ibcon#enter wrdev, iclass 3, count 2 2006.285.16:57:28.11#ibcon#first serial, iclass 3, count 2 2006.285.16:57:28.11#ibcon#enter sib2, iclass 3, count 2 2006.285.16:57:28.11#ibcon#flushed, iclass 3, count 2 2006.285.16:57:28.11#ibcon#about to write, iclass 3, count 2 2006.285.16:57:28.11#ibcon#wrote, iclass 3, count 2 2006.285.16:57:28.11#ibcon#about to read 3, iclass 3, count 2 2006.285.16:57:28.13#ibcon#read 3, iclass 3, count 2 2006.285.16:57:28.13#ibcon#about to read 4, iclass 3, count 2 2006.285.16:57:28.13#ibcon#read 4, iclass 3, count 2 2006.285.16:57:28.13#ibcon#about to read 5, iclass 3, count 2 2006.285.16:57:28.13#ibcon#read 5, iclass 3, count 2 2006.285.16:57:28.13#ibcon#about to read 6, iclass 3, count 2 2006.285.16:57:28.13#ibcon#read 6, iclass 3, count 2 2006.285.16:57:28.13#ibcon#end of sib2, iclass 3, count 2 2006.285.16:57:28.13#ibcon#*mode == 0, iclass 3, count 2 2006.285.16:57:28.13#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.16:57:28.13#ibcon#[27=AT06-03\r\n] 2006.285.16:57:28.13#ibcon#*before write, iclass 3, count 2 2006.285.16:57:28.13#ibcon#enter sib2, iclass 3, count 2 2006.285.16:57:28.13#ibcon#flushed, iclass 3, count 2 2006.285.16:57:28.13#ibcon#about to write, iclass 3, count 2 2006.285.16:57:28.13#ibcon#wrote, iclass 3, count 2 2006.285.16:57:28.13#ibcon#about to read 3, iclass 3, count 2 2006.285.16:57:28.16#ibcon#read 3, iclass 3, count 2 2006.285.16:57:28.16#ibcon#about to read 4, iclass 3, count 2 2006.285.16:57:28.16#ibcon#read 4, iclass 3, count 2 2006.285.16:57:28.16#ibcon#about to read 5, iclass 3, count 2 2006.285.16:57:28.16#ibcon#read 5, iclass 3, count 2 2006.285.16:57:28.16#ibcon#about to read 6, iclass 3, count 2 2006.285.16:57:28.16#ibcon#read 6, iclass 3, count 2 2006.285.16:57:28.16#ibcon#end of sib2, iclass 3, count 2 2006.285.16:57:28.16#ibcon#*after write, iclass 3, count 2 2006.285.16:57:28.16#ibcon#*before return 0, iclass 3, count 2 2006.285.16:57:28.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:57:28.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.16:57:28.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.16:57:28.16#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:28.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:57:28.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:57:28.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:57:28.28#ibcon#enter wrdev, iclass 3, count 0 2006.285.16:57:28.28#ibcon#first serial, iclass 3, count 0 2006.285.16:57:28.28#ibcon#enter sib2, iclass 3, count 0 2006.285.16:57:28.28#ibcon#flushed, iclass 3, count 0 2006.285.16:57:28.28#ibcon#about to write, iclass 3, count 0 2006.285.16:57:28.28#ibcon#wrote, iclass 3, count 0 2006.285.16:57:28.28#ibcon#about to read 3, iclass 3, count 0 2006.285.16:57:28.30#ibcon#read 3, iclass 3, count 0 2006.285.16:57:28.30#ibcon#about to read 4, iclass 3, count 0 2006.285.16:57:28.30#ibcon#read 4, iclass 3, count 0 2006.285.16:57:28.30#ibcon#about to read 5, iclass 3, count 0 2006.285.16:57:28.30#ibcon#read 5, iclass 3, count 0 2006.285.16:57:28.30#ibcon#about to read 6, iclass 3, count 0 2006.285.16:57:28.30#ibcon#read 6, iclass 3, count 0 2006.285.16:57:28.30#ibcon#end of sib2, iclass 3, count 0 2006.285.16:57:28.30#ibcon#*mode == 0, iclass 3, count 0 2006.285.16:57:28.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.16:57:28.30#ibcon#[27=USB\r\n] 2006.285.16:57:28.30#ibcon#*before write, iclass 3, count 0 2006.285.16:57:28.30#ibcon#enter sib2, iclass 3, count 0 2006.285.16:57:28.30#ibcon#flushed, iclass 3, count 0 2006.285.16:57:28.30#ibcon#about to write, iclass 3, count 0 2006.285.16:57:28.30#ibcon#wrote, iclass 3, count 0 2006.285.16:57:28.30#ibcon#about to read 3, iclass 3, count 0 2006.285.16:57:28.33#ibcon#read 3, iclass 3, count 0 2006.285.16:57:28.33#ibcon#about to read 4, iclass 3, count 0 2006.285.16:57:28.33#ibcon#read 4, iclass 3, count 0 2006.285.16:57:28.33#ibcon#about to read 5, iclass 3, count 0 2006.285.16:57:28.33#ibcon#read 5, iclass 3, count 0 2006.285.16:57:28.33#ibcon#about to read 6, iclass 3, count 0 2006.285.16:57:28.33#ibcon#read 6, iclass 3, count 0 2006.285.16:57:28.33#ibcon#end of sib2, iclass 3, count 0 2006.285.16:57:28.33#ibcon#*after write, iclass 3, count 0 2006.285.16:57:28.33#ibcon#*before return 0, iclass 3, count 0 2006.285.16:57:28.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:57:28.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.16:57:28.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.16:57:28.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.16:57:28.33$vck44/vblo=7,734.99 2006.285.16:57:28.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.16:57:28.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.16:57:28.33#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:28.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:57:28.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:57:28.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:57:28.33#ibcon#enter wrdev, iclass 5, count 0 2006.285.16:57:28.33#ibcon#first serial, iclass 5, count 0 2006.285.16:57:28.33#ibcon#enter sib2, iclass 5, count 0 2006.285.16:57:28.33#ibcon#flushed, iclass 5, count 0 2006.285.16:57:28.33#ibcon#about to write, iclass 5, count 0 2006.285.16:57:28.33#ibcon#wrote, iclass 5, count 0 2006.285.16:57:28.33#ibcon#about to read 3, iclass 5, count 0 2006.285.16:57:28.35#ibcon#read 3, iclass 5, count 0 2006.285.16:57:28.35#ibcon#about to read 4, iclass 5, count 0 2006.285.16:57:28.35#ibcon#read 4, iclass 5, count 0 2006.285.16:57:28.35#ibcon#about to read 5, iclass 5, count 0 2006.285.16:57:28.35#ibcon#read 5, iclass 5, count 0 2006.285.16:57:28.35#ibcon#about to read 6, iclass 5, count 0 2006.285.16:57:28.35#ibcon#read 6, iclass 5, count 0 2006.285.16:57:28.35#ibcon#end of sib2, iclass 5, count 0 2006.285.16:57:28.35#ibcon#*mode == 0, iclass 5, count 0 2006.285.16:57:28.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.16:57:28.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.16:57:28.35#ibcon#*before write, iclass 5, count 0 2006.285.16:57:28.35#ibcon#enter sib2, iclass 5, count 0 2006.285.16:57:28.35#ibcon#flushed, iclass 5, count 0 2006.285.16:57:28.35#ibcon#about to write, iclass 5, count 0 2006.285.16:57:28.35#ibcon#wrote, iclass 5, count 0 2006.285.16:57:28.35#ibcon#about to read 3, iclass 5, count 0 2006.285.16:57:28.39#ibcon#read 3, iclass 5, count 0 2006.285.16:57:28.39#ibcon#about to read 4, iclass 5, count 0 2006.285.16:57:28.39#ibcon#read 4, iclass 5, count 0 2006.285.16:57:28.39#ibcon#about to read 5, iclass 5, count 0 2006.285.16:57:28.39#ibcon#read 5, iclass 5, count 0 2006.285.16:57:28.39#ibcon#about to read 6, iclass 5, count 0 2006.285.16:57:28.39#ibcon#read 6, iclass 5, count 0 2006.285.16:57:28.39#ibcon#end of sib2, iclass 5, count 0 2006.285.16:57:28.39#ibcon#*after write, iclass 5, count 0 2006.285.16:57:28.39#ibcon#*before return 0, iclass 5, count 0 2006.285.16:57:28.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:57:28.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.16:57:28.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.16:57:28.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.16:57:28.39$vck44/vb=7,4 2006.285.16:57:28.39#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.16:57:28.39#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.16:57:28.39#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:28.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:57:28.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:57:28.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:57:28.45#ibcon#enter wrdev, iclass 7, count 2 2006.285.16:57:28.45#ibcon#first serial, iclass 7, count 2 2006.285.16:57:28.45#ibcon#enter sib2, iclass 7, count 2 2006.285.16:57:28.45#ibcon#flushed, iclass 7, count 2 2006.285.16:57:28.45#ibcon#about to write, iclass 7, count 2 2006.285.16:57:28.45#ibcon#wrote, iclass 7, count 2 2006.285.16:57:28.45#ibcon#about to read 3, iclass 7, count 2 2006.285.16:57:28.47#ibcon#read 3, iclass 7, count 2 2006.285.16:57:28.47#ibcon#about to read 4, iclass 7, count 2 2006.285.16:57:28.47#ibcon#read 4, iclass 7, count 2 2006.285.16:57:28.47#ibcon#about to read 5, iclass 7, count 2 2006.285.16:57:28.47#ibcon#read 5, iclass 7, count 2 2006.285.16:57:28.47#ibcon#about to read 6, iclass 7, count 2 2006.285.16:57:28.47#ibcon#read 6, iclass 7, count 2 2006.285.16:57:28.47#ibcon#end of sib2, iclass 7, count 2 2006.285.16:57:28.47#ibcon#*mode == 0, iclass 7, count 2 2006.285.16:57:28.47#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.16:57:28.47#ibcon#[27=AT07-04\r\n] 2006.285.16:57:28.47#ibcon#*before write, iclass 7, count 2 2006.285.16:57:28.47#ibcon#enter sib2, iclass 7, count 2 2006.285.16:57:28.47#ibcon#flushed, iclass 7, count 2 2006.285.16:57:28.47#ibcon#about to write, iclass 7, count 2 2006.285.16:57:28.47#ibcon#wrote, iclass 7, count 2 2006.285.16:57:28.47#ibcon#about to read 3, iclass 7, count 2 2006.285.16:57:28.50#ibcon#read 3, iclass 7, count 2 2006.285.16:57:28.50#ibcon#about to read 4, iclass 7, count 2 2006.285.16:57:28.50#ibcon#read 4, iclass 7, count 2 2006.285.16:57:28.50#ibcon#about to read 5, iclass 7, count 2 2006.285.16:57:28.50#ibcon#read 5, iclass 7, count 2 2006.285.16:57:28.50#ibcon#about to read 6, iclass 7, count 2 2006.285.16:57:28.50#ibcon#read 6, iclass 7, count 2 2006.285.16:57:28.50#ibcon#end of sib2, iclass 7, count 2 2006.285.16:57:28.50#ibcon#*after write, iclass 7, count 2 2006.285.16:57:28.50#ibcon#*before return 0, iclass 7, count 2 2006.285.16:57:28.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:57:28.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.16:57:28.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.16:57:28.50#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:28.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:57:28.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:57:28.66#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:57:28.66#ibcon#enter wrdev, iclass 7, count 0 2006.285.16:57:28.66#ibcon#first serial, iclass 7, count 0 2006.285.16:57:28.66#ibcon#enter sib2, iclass 7, count 0 2006.285.16:57:28.66#ibcon#flushed, iclass 7, count 0 2006.285.16:57:28.66#ibcon#about to write, iclass 7, count 0 2006.285.16:57:28.66#ibcon#wrote, iclass 7, count 0 2006.285.16:57:28.66#ibcon#about to read 3, iclass 7, count 0 2006.285.16:57:28.68#ibcon#read 3, iclass 7, count 0 2006.285.16:57:28.68#ibcon#about to read 4, iclass 7, count 0 2006.285.16:57:28.68#ibcon#read 4, iclass 7, count 0 2006.285.16:57:28.68#ibcon#about to read 5, iclass 7, count 0 2006.285.16:57:28.68#ibcon#read 5, iclass 7, count 0 2006.285.16:57:28.68#ibcon#about to read 6, iclass 7, count 0 2006.285.16:57:28.68#ibcon#read 6, iclass 7, count 0 2006.285.16:57:28.68#ibcon#end of sib2, iclass 7, count 0 2006.285.16:57:28.68#ibcon#*mode == 0, iclass 7, count 0 2006.285.16:57:28.68#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.16:57:28.68#ibcon#[27=USB\r\n] 2006.285.16:57:28.68#ibcon#*before write, iclass 7, count 0 2006.285.16:57:28.68#ibcon#enter sib2, iclass 7, count 0 2006.285.16:57:28.68#ibcon#flushed, iclass 7, count 0 2006.285.16:57:28.68#ibcon#about to write, iclass 7, count 0 2006.285.16:57:28.68#ibcon#wrote, iclass 7, count 0 2006.285.16:57:28.68#ibcon#about to read 3, iclass 7, count 0 2006.285.16:57:28.71#ibcon#read 3, iclass 7, count 0 2006.285.16:57:28.71#ibcon#about to read 4, iclass 7, count 0 2006.285.16:57:28.71#ibcon#read 4, iclass 7, count 0 2006.285.16:57:28.71#ibcon#about to read 5, iclass 7, count 0 2006.285.16:57:28.71#ibcon#read 5, iclass 7, count 0 2006.285.16:57:28.71#ibcon#about to read 6, iclass 7, count 0 2006.285.16:57:28.71#ibcon#read 6, iclass 7, count 0 2006.285.16:57:28.71#ibcon#end of sib2, iclass 7, count 0 2006.285.16:57:28.71#ibcon#*after write, iclass 7, count 0 2006.285.16:57:28.71#ibcon#*before return 0, iclass 7, count 0 2006.285.16:57:28.71#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:57:28.71#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.16:57:28.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.16:57:28.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.16:57:28.71$vck44/vblo=8,744.99 2006.285.16:57:28.71#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.16:57:28.71#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.16:57:28.71#ibcon#ireg 17 cls_cnt 0 2006.285.16:57:28.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:57:28.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:57:28.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:57:28.71#ibcon#enter wrdev, iclass 11, count 0 2006.285.16:57:28.71#ibcon#first serial, iclass 11, count 0 2006.285.16:57:28.71#ibcon#enter sib2, iclass 11, count 0 2006.285.16:57:28.71#ibcon#flushed, iclass 11, count 0 2006.285.16:57:28.71#ibcon#about to write, iclass 11, count 0 2006.285.16:57:28.71#ibcon#wrote, iclass 11, count 0 2006.285.16:57:28.71#ibcon#about to read 3, iclass 11, count 0 2006.285.16:57:28.73#ibcon#read 3, iclass 11, count 0 2006.285.16:57:28.73#ibcon#about to read 4, iclass 11, count 0 2006.285.16:57:28.73#ibcon#read 4, iclass 11, count 0 2006.285.16:57:28.73#ibcon#about to read 5, iclass 11, count 0 2006.285.16:57:28.73#ibcon#read 5, iclass 11, count 0 2006.285.16:57:28.73#ibcon#about to read 6, iclass 11, count 0 2006.285.16:57:28.73#ibcon#read 6, iclass 11, count 0 2006.285.16:57:28.73#ibcon#end of sib2, iclass 11, count 0 2006.285.16:57:28.73#ibcon#*mode == 0, iclass 11, count 0 2006.285.16:57:28.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.16:57:28.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.16:57:28.73#ibcon#*before write, iclass 11, count 0 2006.285.16:57:28.73#ibcon#enter sib2, iclass 11, count 0 2006.285.16:57:28.73#ibcon#flushed, iclass 11, count 0 2006.285.16:57:28.73#ibcon#about to write, iclass 11, count 0 2006.285.16:57:28.73#ibcon#wrote, iclass 11, count 0 2006.285.16:57:28.73#ibcon#about to read 3, iclass 11, count 0 2006.285.16:57:28.77#ibcon#read 3, iclass 11, count 0 2006.285.16:57:28.77#ibcon#about to read 4, iclass 11, count 0 2006.285.16:57:28.77#ibcon#read 4, iclass 11, count 0 2006.285.16:57:28.77#ibcon#about to read 5, iclass 11, count 0 2006.285.16:57:28.77#ibcon#read 5, iclass 11, count 0 2006.285.16:57:28.77#ibcon#about to read 6, iclass 11, count 0 2006.285.16:57:28.77#ibcon#read 6, iclass 11, count 0 2006.285.16:57:28.77#ibcon#end of sib2, iclass 11, count 0 2006.285.16:57:28.77#ibcon#*after write, iclass 11, count 0 2006.285.16:57:28.77#ibcon#*before return 0, iclass 11, count 0 2006.285.16:57:28.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:57:28.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.16:57:28.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.16:57:28.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.16:57:28.77$vck44/vb=8,4 2006.285.16:57:28.77#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.16:57:28.77#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.16:57:28.77#ibcon#ireg 11 cls_cnt 2 2006.285.16:57:28.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:57:28.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:57:28.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:57:28.83#ibcon#enter wrdev, iclass 13, count 2 2006.285.16:57:28.83#ibcon#first serial, iclass 13, count 2 2006.285.16:57:28.83#ibcon#enter sib2, iclass 13, count 2 2006.285.16:57:28.83#ibcon#flushed, iclass 13, count 2 2006.285.16:57:28.83#ibcon#about to write, iclass 13, count 2 2006.285.16:57:28.83#ibcon#wrote, iclass 13, count 2 2006.285.16:57:28.83#ibcon#about to read 3, iclass 13, count 2 2006.285.16:57:28.85#ibcon#read 3, iclass 13, count 2 2006.285.16:57:28.85#ibcon#about to read 4, iclass 13, count 2 2006.285.16:57:28.85#ibcon#read 4, iclass 13, count 2 2006.285.16:57:28.85#ibcon#about to read 5, iclass 13, count 2 2006.285.16:57:28.85#ibcon#read 5, iclass 13, count 2 2006.285.16:57:28.85#ibcon#about to read 6, iclass 13, count 2 2006.285.16:57:28.85#ibcon#read 6, iclass 13, count 2 2006.285.16:57:28.85#ibcon#end of sib2, iclass 13, count 2 2006.285.16:57:28.85#ibcon#*mode == 0, iclass 13, count 2 2006.285.16:57:28.85#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.16:57:28.85#ibcon#[27=AT08-04\r\n] 2006.285.16:57:28.85#ibcon#*before write, iclass 13, count 2 2006.285.16:57:28.85#ibcon#enter sib2, iclass 13, count 2 2006.285.16:57:28.85#ibcon#flushed, iclass 13, count 2 2006.285.16:57:28.85#ibcon#about to write, iclass 13, count 2 2006.285.16:57:28.85#ibcon#wrote, iclass 13, count 2 2006.285.16:57:28.85#ibcon#about to read 3, iclass 13, count 2 2006.285.16:57:28.88#ibcon#read 3, iclass 13, count 2 2006.285.16:57:28.88#ibcon#about to read 4, iclass 13, count 2 2006.285.16:57:28.88#ibcon#read 4, iclass 13, count 2 2006.285.16:57:28.88#ibcon#about to read 5, iclass 13, count 2 2006.285.16:57:28.88#ibcon#read 5, iclass 13, count 2 2006.285.16:57:28.88#ibcon#about to read 6, iclass 13, count 2 2006.285.16:57:28.88#ibcon#read 6, iclass 13, count 2 2006.285.16:57:28.88#ibcon#end of sib2, iclass 13, count 2 2006.285.16:57:28.88#ibcon#*after write, iclass 13, count 2 2006.285.16:57:28.88#ibcon#*before return 0, iclass 13, count 2 2006.285.16:57:28.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:57:28.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.16:57:28.88#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.16:57:28.88#ibcon#ireg 7 cls_cnt 0 2006.285.16:57:28.88#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:57:29.00#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:57:29.00#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:57:29.00#ibcon#enter wrdev, iclass 13, count 0 2006.285.16:57:29.00#ibcon#first serial, iclass 13, count 0 2006.285.16:57:29.00#ibcon#enter sib2, iclass 13, count 0 2006.285.16:57:29.00#ibcon#flushed, iclass 13, count 0 2006.285.16:57:29.00#ibcon#about to write, iclass 13, count 0 2006.285.16:57:29.00#ibcon#wrote, iclass 13, count 0 2006.285.16:57:29.00#ibcon#about to read 3, iclass 13, count 0 2006.285.16:57:29.02#ibcon#read 3, iclass 13, count 0 2006.285.16:57:29.02#ibcon#about to read 4, iclass 13, count 0 2006.285.16:57:29.02#ibcon#read 4, iclass 13, count 0 2006.285.16:57:29.02#ibcon#about to read 5, iclass 13, count 0 2006.285.16:57:29.02#ibcon#read 5, iclass 13, count 0 2006.285.16:57:29.02#ibcon#about to read 6, iclass 13, count 0 2006.285.16:57:29.02#ibcon#read 6, iclass 13, count 0 2006.285.16:57:29.02#ibcon#end of sib2, iclass 13, count 0 2006.285.16:57:29.02#ibcon#*mode == 0, iclass 13, count 0 2006.285.16:57:29.02#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.16:57:29.02#ibcon#[27=USB\r\n] 2006.285.16:57:29.02#ibcon#*before write, iclass 13, count 0 2006.285.16:57:29.02#ibcon#enter sib2, iclass 13, count 0 2006.285.16:57:29.02#ibcon#flushed, iclass 13, count 0 2006.285.16:57:29.02#ibcon#about to write, iclass 13, count 0 2006.285.16:57:29.02#ibcon#wrote, iclass 13, count 0 2006.285.16:57:29.02#ibcon#about to read 3, iclass 13, count 0 2006.285.16:57:29.05#ibcon#read 3, iclass 13, count 0 2006.285.16:57:29.05#ibcon#about to read 4, iclass 13, count 0 2006.285.16:57:29.05#ibcon#read 4, iclass 13, count 0 2006.285.16:57:29.05#ibcon#about to read 5, iclass 13, count 0 2006.285.16:57:29.05#ibcon#read 5, iclass 13, count 0 2006.285.16:57:29.05#ibcon#about to read 6, iclass 13, count 0 2006.285.16:57:29.05#ibcon#read 6, iclass 13, count 0 2006.285.16:57:29.05#ibcon#end of sib2, iclass 13, count 0 2006.285.16:57:29.05#ibcon#*after write, iclass 13, count 0 2006.285.16:57:29.05#ibcon#*before return 0, iclass 13, count 0 2006.285.16:57:29.05#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:57:29.05#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.16:57:29.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.16:57:29.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.16:57:29.05$vck44/vabw=wide 2006.285.16:57:29.05#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.16:57:29.05#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.16:57:29.05#ibcon#ireg 8 cls_cnt 0 2006.285.16:57:29.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:57:29.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:57:29.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:57:29.05#ibcon#enter wrdev, iclass 15, count 0 2006.285.16:57:29.05#ibcon#first serial, iclass 15, count 0 2006.285.16:57:29.05#ibcon#enter sib2, iclass 15, count 0 2006.285.16:57:29.05#ibcon#flushed, iclass 15, count 0 2006.285.16:57:29.05#ibcon#about to write, iclass 15, count 0 2006.285.16:57:29.05#ibcon#wrote, iclass 15, count 0 2006.285.16:57:29.05#ibcon#about to read 3, iclass 15, count 0 2006.285.16:57:29.07#ibcon#read 3, iclass 15, count 0 2006.285.16:57:29.07#ibcon#about to read 4, iclass 15, count 0 2006.285.16:57:29.07#ibcon#read 4, iclass 15, count 0 2006.285.16:57:29.07#ibcon#about to read 5, iclass 15, count 0 2006.285.16:57:29.07#ibcon#read 5, iclass 15, count 0 2006.285.16:57:29.07#ibcon#about to read 6, iclass 15, count 0 2006.285.16:57:29.07#ibcon#read 6, iclass 15, count 0 2006.285.16:57:29.07#ibcon#end of sib2, iclass 15, count 0 2006.285.16:57:29.07#ibcon#*mode == 0, iclass 15, count 0 2006.285.16:57:29.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.16:57:29.07#ibcon#[25=BW32\r\n] 2006.285.16:57:29.07#ibcon#*before write, iclass 15, count 0 2006.285.16:57:29.07#ibcon#enter sib2, iclass 15, count 0 2006.285.16:57:29.07#ibcon#flushed, iclass 15, count 0 2006.285.16:57:29.07#ibcon#about to write, iclass 15, count 0 2006.285.16:57:29.07#ibcon#wrote, iclass 15, count 0 2006.285.16:57:29.07#ibcon#about to read 3, iclass 15, count 0 2006.285.16:57:29.10#ibcon#read 3, iclass 15, count 0 2006.285.16:57:29.10#ibcon#about to read 4, iclass 15, count 0 2006.285.16:57:29.10#ibcon#read 4, iclass 15, count 0 2006.285.16:57:29.10#ibcon#about to read 5, iclass 15, count 0 2006.285.16:57:29.10#ibcon#read 5, iclass 15, count 0 2006.285.16:57:29.10#ibcon#about to read 6, iclass 15, count 0 2006.285.16:57:29.10#ibcon#read 6, iclass 15, count 0 2006.285.16:57:29.10#ibcon#end of sib2, iclass 15, count 0 2006.285.16:57:29.10#ibcon#*after write, iclass 15, count 0 2006.285.16:57:29.10#ibcon#*before return 0, iclass 15, count 0 2006.285.16:57:29.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:57:29.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.16:57:29.10#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.16:57:29.10#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.16:57:29.10$vck44/vbbw=wide 2006.285.16:57:29.10#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.16:57:29.10#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.16:57:29.10#ibcon#ireg 8 cls_cnt 0 2006.285.16:57:29.10#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:57:29.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:57:29.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:57:29.17#ibcon#enter wrdev, iclass 17, count 0 2006.285.16:57:29.17#ibcon#first serial, iclass 17, count 0 2006.285.16:57:29.17#ibcon#enter sib2, iclass 17, count 0 2006.285.16:57:29.17#ibcon#flushed, iclass 17, count 0 2006.285.16:57:29.17#ibcon#about to write, iclass 17, count 0 2006.285.16:57:29.17#ibcon#wrote, iclass 17, count 0 2006.285.16:57:29.17#ibcon#about to read 3, iclass 17, count 0 2006.285.16:57:29.19#ibcon#read 3, iclass 17, count 0 2006.285.16:57:29.19#ibcon#about to read 4, iclass 17, count 0 2006.285.16:57:29.19#ibcon#read 4, iclass 17, count 0 2006.285.16:57:29.19#ibcon#about to read 5, iclass 17, count 0 2006.285.16:57:29.19#ibcon#read 5, iclass 17, count 0 2006.285.16:57:29.19#ibcon#about to read 6, iclass 17, count 0 2006.285.16:57:29.19#ibcon#read 6, iclass 17, count 0 2006.285.16:57:29.19#ibcon#end of sib2, iclass 17, count 0 2006.285.16:57:29.19#ibcon#*mode == 0, iclass 17, count 0 2006.285.16:57:29.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.16:57:29.19#ibcon#[27=BW32\r\n] 2006.285.16:57:29.19#ibcon#*before write, iclass 17, count 0 2006.285.16:57:29.19#ibcon#enter sib2, iclass 17, count 0 2006.285.16:57:29.19#ibcon#flushed, iclass 17, count 0 2006.285.16:57:29.19#ibcon#about to write, iclass 17, count 0 2006.285.16:57:29.19#ibcon#wrote, iclass 17, count 0 2006.285.16:57:29.19#ibcon#about to read 3, iclass 17, count 0 2006.285.16:57:29.22#ibcon#read 3, iclass 17, count 0 2006.285.16:57:29.22#ibcon#about to read 4, iclass 17, count 0 2006.285.16:57:29.22#ibcon#read 4, iclass 17, count 0 2006.285.16:57:29.22#ibcon#about to read 5, iclass 17, count 0 2006.285.16:57:29.22#ibcon#read 5, iclass 17, count 0 2006.285.16:57:29.22#ibcon#about to read 6, iclass 17, count 0 2006.285.16:57:29.22#ibcon#read 6, iclass 17, count 0 2006.285.16:57:29.22#ibcon#end of sib2, iclass 17, count 0 2006.285.16:57:29.22#ibcon#*after write, iclass 17, count 0 2006.285.16:57:29.22#ibcon#*before return 0, iclass 17, count 0 2006.285.16:57:29.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:57:29.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.16:57:29.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.16:57:29.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.16:57:29.22$setupk4/ifdk4 2006.285.16:57:29.22$ifdk4/lo= 2006.285.16:57:29.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.16:57:29.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.16:57:29.22$ifdk4/patch= 2006.285.16:57:29.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.16:57:29.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.16:57:29.22$setupk4/!*+20s 2006.285.16:57:30.14#trakl#Source acquired 2006.285.16:57:31.14#flagr#flagr/antenna,acquired 2006.285.16:57:36.43#abcon#<5=/15 0.5 1.1 17.81 951014.9\r\n> 2006.285.16:57:36.45#abcon#{5=INTERFACE CLEAR} 2006.285.16:57:36.51#abcon#[5=S1D000X0/0*\r\n] 2006.285.16:57:42.90$setupk4/"tpicd 2006.285.16:57:42.90$setupk4/echo=off 2006.285.16:57:42.90$setupk4/xlog=off 2006.285.16:57:42.90:!2006.285.16:57:47 2006.285.16:57:47.00:preob 2006.285.16:57:47.14/onsource/TRACKING 2006.285.16:57:47.14:!2006.285.16:57:57 2006.285.16:57:57.00:"tape 2006.285.16:57:57.00:"st=record 2006.285.16:57:57.00:data_valid=on 2006.285.16:57:57.00:midob 2006.285.16:57:58.14/onsource/TRACKING 2006.285.16:57:58.14/wx/17.79,1014.9,95 2006.285.16:57:58.23/cable/+6.5032E-03 2006.285.16:57:59.32/va/01,07,usb,yes,33,36 2006.285.16:57:59.32/va/02,06,usb,yes,33,34 2006.285.16:57:59.32/va/03,07,usb,yes,33,35 2006.285.16:57:59.32/va/04,06,usb,yes,35,36 2006.285.16:57:59.32/va/05,03,usb,yes,34,34 2006.285.16:57:59.32/va/06,04,usb,yes,31,30 2006.285.16:57:59.32/va/07,04,usb,yes,31,32 2006.285.16:57:59.32/va/08,03,usb,yes,32,39 2006.285.16:57:59.55/valo/01,524.99,yes,locked 2006.285.16:57:59.55/valo/02,534.99,yes,locked 2006.285.16:57:59.55/valo/03,564.99,yes,locked 2006.285.16:57:59.55/valo/04,624.99,yes,locked 2006.285.16:57:59.55/valo/05,734.99,yes,locked 2006.285.16:57:59.55/valo/06,814.99,yes,locked 2006.285.16:57:59.55/valo/07,864.99,yes,locked 2006.285.16:57:59.55/valo/08,884.99,yes,locked 2006.285.16:58:00.64/vb/01,04,usb,yes,31,29 2006.285.16:58:00.64/vb/02,05,usb,yes,29,29 2006.285.16:58:00.64/vb/03,04,usb,yes,30,33 2006.285.16:58:00.64/vb/04,05,usb,yes,31,30 2006.285.16:58:00.64/vb/05,04,usb,yes,27,30 2006.285.16:58:00.64/vb/06,03,usb,yes,39,34 2006.285.16:58:00.64/vb/07,04,usb,yes,31,31 2006.285.16:58:00.64/vb/08,04,usb,yes,28,32 2006.285.16:58:00.87/vblo/01,629.99,yes,locked 2006.285.16:58:00.87/vblo/02,634.99,yes,locked 2006.285.16:58:00.87/vblo/03,649.99,yes,locked 2006.285.16:58:00.87/vblo/04,679.99,yes,locked 2006.285.16:58:00.87/vblo/05,709.99,yes,locked 2006.285.16:58:00.87/vblo/06,719.99,yes,locked 2006.285.16:58:00.87/vblo/07,734.99,yes,locked 2006.285.16:58:00.87/vblo/08,744.99,yes,locked 2006.285.16:58:01.02/vabw/8 2006.285.16:58:01.17/vbbw/8 2006.285.16:58:01.26/xfe/off,on,12.2 2006.285.16:58:01.63/ifatt/23,28,28,28 2006.285.16:58:02.08/fmout-gps/S +2.67E-07 2006.285.16:58:02.10:!2006.285.17:01:07 2006.285.17:01:07.01:data_valid=off 2006.285.17:01:07.01:"et 2006.285.17:01:07.01:!+3s 2006.285.17:01:10.02:"tape 2006.285.17:01:10.02:postob 2006.285.17:01:10.22/cable/+6.5026E-03 2006.285.17:01:10.22/wx/17.64,1014.8,96 2006.285.17:01:11.08/fmout-gps/S +2.72E-07 2006.285.17:01:11.08:scan_name=285-1709,jd0610,70 2006.285.17:01:11.08:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.285.17:01:12.13#flagr#flagr/antenna,new-source 2006.285.17:01:12.13:checkk5 2006.285.17:01:13.21/chk_autoobs//k5ts1/ autoobs is running! 2006.285.17:01:13.60/chk_autoobs//k5ts2/ autoobs is running! 2006.285.17:01:13.99/chk_autoobs//k5ts3/ autoobs is running! 2006.285.17:01:14.43/chk_autoobs//k5ts4/ autoobs is running! 2006.285.17:01:14.87/chk_obsdata//k5ts1/T2851657??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.285.17:01:15.27/chk_obsdata//k5ts2/T2851657??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.285.17:01:15.64/chk_obsdata//k5ts3/T2851657??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.285.17:01:16.12/chk_obsdata//k5ts4/T2851657??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.285.17:01:16.92/k5log//k5ts1_log_newline 2006.285.17:01:17.85/k5log//k5ts2_log_newline 2006.285.17:01:18.57/k5log//k5ts3_log_newline 2006.285.17:01:19.43/k5log//k5ts4_log_newline 2006.285.17:01:19.45/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.17:01:19.45:setupk4=1 2006.285.17:01:19.45$setupk4/echo=on 2006.285.17:01:19.45$setupk4/pcalon 2006.285.17:01:19.45$pcalon/"no phase cal control is implemented here 2006.285.17:01:19.45$setupk4/"tpicd=stop 2006.285.17:01:19.45$setupk4/"rec=synch_on 2006.285.17:01:19.45$setupk4/"rec_mode=128 2006.285.17:01:19.46$setupk4/!* 2006.285.17:01:19.46$setupk4/recpk4 2006.285.17:01:19.46$recpk4/recpatch= 2006.285.17:01:19.46$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.17:01:19.46$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.17:01:19.46$setupk4/vck44 2006.285.17:01:19.46$vck44/valo=1,524.99 2006.285.17:01:19.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.17:01:19.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.17:01:19.46#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:19.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:01:19.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:01:19.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:01:19.46#ibcon#enter wrdev, iclass 38, count 0 2006.285.17:01:19.46#ibcon#first serial, iclass 38, count 0 2006.285.17:01:19.46#ibcon#enter sib2, iclass 38, count 0 2006.285.17:01:19.46#ibcon#flushed, iclass 38, count 0 2006.285.17:01:19.46#ibcon#about to write, iclass 38, count 0 2006.285.17:01:19.46#ibcon#wrote, iclass 38, count 0 2006.285.17:01:19.46#ibcon#about to read 3, iclass 38, count 0 2006.285.17:01:19.48#ibcon#read 3, iclass 38, count 0 2006.285.17:01:19.48#ibcon#about to read 4, iclass 38, count 0 2006.285.17:01:19.48#ibcon#read 4, iclass 38, count 0 2006.285.17:01:19.48#ibcon#about to read 5, iclass 38, count 0 2006.285.17:01:19.48#ibcon#read 5, iclass 38, count 0 2006.285.17:01:19.48#ibcon#about to read 6, iclass 38, count 0 2006.285.17:01:19.48#ibcon#read 6, iclass 38, count 0 2006.285.17:01:19.48#ibcon#end of sib2, iclass 38, count 0 2006.285.17:01:19.48#ibcon#*mode == 0, iclass 38, count 0 2006.285.17:01:19.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.17:01:19.48#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.17:01:19.48#ibcon#*before write, iclass 38, count 0 2006.285.17:01:19.48#ibcon#enter sib2, iclass 38, count 0 2006.285.17:01:19.48#ibcon#flushed, iclass 38, count 0 2006.285.17:01:19.48#ibcon#about to write, iclass 38, count 0 2006.285.17:01:19.48#ibcon#wrote, iclass 38, count 0 2006.285.17:01:19.48#ibcon#about to read 3, iclass 38, count 0 2006.285.17:01:19.53#ibcon#read 3, iclass 38, count 0 2006.285.17:01:19.53#ibcon#about to read 4, iclass 38, count 0 2006.285.17:01:19.53#ibcon#read 4, iclass 38, count 0 2006.285.17:01:19.53#ibcon#about to read 5, iclass 38, count 0 2006.285.17:01:19.53#ibcon#read 5, iclass 38, count 0 2006.285.17:01:19.53#ibcon#about to read 6, iclass 38, count 0 2006.285.17:01:19.53#ibcon#read 6, iclass 38, count 0 2006.285.17:01:19.53#ibcon#end of sib2, iclass 38, count 0 2006.285.17:01:19.53#ibcon#*after write, iclass 38, count 0 2006.285.17:01:19.53#ibcon#*before return 0, iclass 38, count 0 2006.285.17:01:19.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:01:19.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:01:19.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.17:01:19.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.17:01:19.53$vck44/va=1,7 2006.285.17:01:19.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.17:01:19.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.17:01:19.53#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:19.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:01:19.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:01:19.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:01:19.53#ibcon#enter wrdev, iclass 40, count 2 2006.285.17:01:19.53#ibcon#first serial, iclass 40, count 2 2006.285.17:01:19.53#ibcon#enter sib2, iclass 40, count 2 2006.285.17:01:19.53#ibcon#flushed, iclass 40, count 2 2006.285.17:01:19.53#ibcon#about to write, iclass 40, count 2 2006.285.17:01:19.53#ibcon#wrote, iclass 40, count 2 2006.285.17:01:19.53#ibcon#about to read 3, iclass 40, count 2 2006.285.17:01:19.55#ibcon#read 3, iclass 40, count 2 2006.285.17:01:19.55#ibcon#about to read 4, iclass 40, count 2 2006.285.17:01:19.55#ibcon#read 4, iclass 40, count 2 2006.285.17:01:19.55#ibcon#about to read 5, iclass 40, count 2 2006.285.17:01:19.55#ibcon#read 5, iclass 40, count 2 2006.285.17:01:19.55#ibcon#about to read 6, iclass 40, count 2 2006.285.17:01:19.55#ibcon#read 6, iclass 40, count 2 2006.285.17:01:19.55#ibcon#end of sib2, iclass 40, count 2 2006.285.17:01:19.55#ibcon#*mode == 0, iclass 40, count 2 2006.285.17:01:19.55#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.17:01:19.55#ibcon#[25=AT01-07\r\n] 2006.285.17:01:19.55#ibcon#*before write, iclass 40, count 2 2006.285.17:01:19.55#ibcon#enter sib2, iclass 40, count 2 2006.285.17:01:19.55#ibcon#flushed, iclass 40, count 2 2006.285.17:01:19.55#ibcon#about to write, iclass 40, count 2 2006.285.17:01:19.55#ibcon#wrote, iclass 40, count 2 2006.285.17:01:19.55#ibcon#about to read 3, iclass 40, count 2 2006.285.17:01:19.58#ibcon#read 3, iclass 40, count 2 2006.285.17:01:19.58#ibcon#about to read 4, iclass 40, count 2 2006.285.17:01:19.58#ibcon#read 4, iclass 40, count 2 2006.285.17:01:19.58#ibcon#about to read 5, iclass 40, count 2 2006.285.17:01:19.58#ibcon#read 5, iclass 40, count 2 2006.285.17:01:19.58#ibcon#about to read 6, iclass 40, count 2 2006.285.17:01:19.58#ibcon#read 6, iclass 40, count 2 2006.285.17:01:19.58#ibcon#end of sib2, iclass 40, count 2 2006.285.17:01:19.58#ibcon#*after write, iclass 40, count 2 2006.285.17:01:19.58#ibcon#*before return 0, iclass 40, count 2 2006.285.17:01:19.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:01:19.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:01:19.58#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.17:01:19.58#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:19.58#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:01:19.70#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:01:19.70#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:01:19.70#ibcon#enter wrdev, iclass 40, count 0 2006.285.17:01:19.70#ibcon#first serial, iclass 40, count 0 2006.285.17:01:19.70#ibcon#enter sib2, iclass 40, count 0 2006.285.17:01:19.70#ibcon#flushed, iclass 40, count 0 2006.285.17:01:19.70#ibcon#about to write, iclass 40, count 0 2006.285.17:01:19.70#ibcon#wrote, iclass 40, count 0 2006.285.17:01:19.70#ibcon#about to read 3, iclass 40, count 0 2006.285.17:01:19.72#ibcon#read 3, iclass 40, count 0 2006.285.17:01:19.72#ibcon#about to read 4, iclass 40, count 0 2006.285.17:01:19.72#ibcon#read 4, iclass 40, count 0 2006.285.17:01:19.72#ibcon#about to read 5, iclass 40, count 0 2006.285.17:01:19.72#ibcon#read 5, iclass 40, count 0 2006.285.17:01:19.72#ibcon#about to read 6, iclass 40, count 0 2006.285.17:01:19.72#ibcon#read 6, iclass 40, count 0 2006.285.17:01:19.72#ibcon#end of sib2, iclass 40, count 0 2006.285.17:01:19.72#ibcon#*mode == 0, iclass 40, count 0 2006.285.17:01:19.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.17:01:19.72#ibcon#[25=USB\r\n] 2006.285.17:01:19.72#ibcon#*before write, iclass 40, count 0 2006.285.17:01:19.72#ibcon#enter sib2, iclass 40, count 0 2006.285.17:01:19.72#ibcon#flushed, iclass 40, count 0 2006.285.17:01:19.72#ibcon#about to write, iclass 40, count 0 2006.285.17:01:19.72#ibcon#wrote, iclass 40, count 0 2006.285.17:01:19.72#ibcon#about to read 3, iclass 40, count 0 2006.285.17:01:19.75#ibcon#read 3, iclass 40, count 0 2006.285.17:01:19.75#ibcon#about to read 4, iclass 40, count 0 2006.285.17:01:19.75#ibcon#read 4, iclass 40, count 0 2006.285.17:01:19.75#ibcon#about to read 5, iclass 40, count 0 2006.285.17:01:19.75#ibcon#read 5, iclass 40, count 0 2006.285.17:01:19.75#ibcon#about to read 6, iclass 40, count 0 2006.285.17:01:19.75#ibcon#read 6, iclass 40, count 0 2006.285.17:01:19.75#ibcon#end of sib2, iclass 40, count 0 2006.285.17:01:19.75#ibcon#*after write, iclass 40, count 0 2006.285.17:01:19.75#ibcon#*before return 0, iclass 40, count 0 2006.285.17:01:19.75#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:01:19.75#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:01:19.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.17:01:19.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.17:01:19.75$vck44/valo=2,534.99 2006.285.17:01:19.75#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.17:01:19.75#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.17:01:19.75#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:19.75#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:01:19.75#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:01:19.75#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:01:19.75#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:01:19.75#ibcon#first serial, iclass 4, count 0 2006.285.17:01:19.75#ibcon#enter sib2, iclass 4, count 0 2006.285.17:01:19.75#ibcon#flushed, iclass 4, count 0 2006.285.17:01:19.75#ibcon#about to write, iclass 4, count 0 2006.285.17:01:19.75#ibcon#wrote, iclass 4, count 0 2006.285.17:01:19.75#ibcon#about to read 3, iclass 4, count 0 2006.285.17:01:19.77#ibcon#read 3, iclass 4, count 0 2006.285.17:01:20.35#ibcon#about to read 4, iclass 4, count 0 2006.285.17:01:20.35#ibcon#read 4, iclass 4, count 0 2006.285.17:01:20.35#ibcon#about to read 5, iclass 4, count 0 2006.285.17:01:20.35#ibcon#read 5, iclass 4, count 0 2006.285.17:01:20.35#ibcon#about to read 6, iclass 4, count 0 2006.285.17:01:20.35#ibcon#read 6, iclass 4, count 0 2006.285.17:01:20.35#ibcon#end of sib2, iclass 4, count 0 2006.285.17:01:20.35#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:01:20.35#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:01:20.35#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.17:01:20.35#ibcon#*before write, iclass 4, count 0 2006.285.17:01:20.35#ibcon#enter sib2, iclass 4, count 0 2006.285.17:01:20.35#ibcon#flushed, iclass 4, count 0 2006.285.17:01:20.35#ibcon#about to write, iclass 4, count 0 2006.285.17:01:20.35#ibcon#wrote, iclass 4, count 0 2006.285.17:01:20.35#ibcon#about to read 3, iclass 4, count 0 2006.285.17:01:20.40#abcon#<5=/14 0.5 1.0 17.63 961014.9\r\n> 2006.285.17:01:20.40#ibcon#read 3, iclass 4, count 0 2006.285.17:01:20.40#ibcon#about to read 4, iclass 4, count 0 2006.285.17:01:20.40#ibcon#read 4, iclass 4, count 0 2006.285.17:01:20.40#ibcon#about to read 5, iclass 4, count 0 2006.285.17:01:20.40#ibcon#read 5, iclass 4, count 0 2006.285.17:01:20.40#ibcon#about to read 6, iclass 4, count 0 2006.285.17:01:20.40#ibcon#read 6, iclass 4, count 0 2006.285.17:01:20.40#ibcon#end of sib2, iclass 4, count 0 2006.285.17:01:20.40#ibcon#*after write, iclass 4, count 0 2006.285.17:01:20.40#ibcon#*before return 0, iclass 4, count 0 2006.285.17:01:20.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:01:20.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:01:20.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:01:20.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:01:20.40$vck44/va=2,6 2006.285.17:01:20.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.17:01:20.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.17:01:20.40#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:20.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:01:20.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:01:20.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:01:20.40#ibcon#enter wrdev, iclass 11, count 2 2006.285.17:01:20.40#ibcon#first serial, iclass 11, count 2 2006.285.17:01:20.40#ibcon#enter sib2, iclass 11, count 2 2006.285.17:01:20.40#ibcon#flushed, iclass 11, count 2 2006.285.17:01:20.40#ibcon#about to write, iclass 11, count 2 2006.285.17:01:20.40#ibcon#wrote, iclass 11, count 2 2006.285.17:01:20.40#ibcon#about to read 3, iclass 11, count 2 2006.285.17:01:20.42#abcon#{5=INTERFACE CLEAR} 2006.285.17:01:20.42#ibcon#read 3, iclass 11, count 2 2006.285.17:01:20.42#ibcon#about to read 4, iclass 11, count 2 2006.285.17:01:20.42#ibcon#read 4, iclass 11, count 2 2006.285.17:01:20.42#ibcon#about to read 5, iclass 11, count 2 2006.285.17:01:20.42#ibcon#read 5, iclass 11, count 2 2006.285.17:01:20.42#ibcon#about to read 6, iclass 11, count 2 2006.285.17:01:20.42#ibcon#read 6, iclass 11, count 2 2006.285.17:01:20.42#ibcon#end of sib2, iclass 11, count 2 2006.285.17:01:20.42#ibcon#*mode == 0, iclass 11, count 2 2006.285.17:01:20.42#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.17:01:20.42#ibcon#[25=AT02-06\r\n] 2006.285.17:01:20.42#ibcon#*before write, iclass 11, count 2 2006.285.17:01:20.42#ibcon#enter sib2, iclass 11, count 2 2006.285.17:01:20.42#ibcon#flushed, iclass 11, count 2 2006.285.17:01:20.42#ibcon#about to write, iclass 11, count 2 2006.285.17:01:20.42#ibcon#wrote, iclass 11, count 2 2006.285.17:01:20.42#ibcon#about to read 3, iclass 11, count 2 2006.285.17:01:20.45#ibcon#read 3, iclass 11, count 2 2006.285.17:01:20.45#ibcon#about to read 4, iclass 11, count 2 2006.285.17:01:20.45#ibcon#read 4, iclass 11, count 2 2006.285.17:01:20.45#ibcon#about to read 5, iclass 11, count 2 2006.285.17:01:20.45#ibcon#read 5, iclass 11, count 2 2006.285.17:01:20.45#ibcon#about to read 6, iclass 11, count 2 2006.285.17:01:20.45#ibcon#read 6, iclass 11, count 2 2006.285.17:01:20.45#ibcon#end of sib2, iclass 11, count 2 2006.285.17:01:20.45#ibcon#*after write, iclass 11, count 2 2006.285.17:01:20.45#ibcon#*before return 0, iclass 11, count 2 2006.285.17:01:20.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:01:20.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:01:20.45#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.17:01:20.45#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:20.45#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:01:20.48#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:01:20.57#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:01:20.57#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:01:20.57#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:01:20.57#ibcon#first serial, iclass 11, count 0 2006.285.17:01:20.57#ibcon#enter sib2, iclass 11, count 0 2006.285.17:01:20.57#ibcon#flushed, iclass 11, count 0 2006.285.17:01:20.57#ibcon#about to write, iclass 11, count 0 2006.285.17:01:20.57#ibcon#wrote, iclass 11, count 0 2006.285.17:01:20.57#ibcon#about to read 3, iclass 11, count 0 2006.285.17:01:20.59#ibcon#read 3, iclass 11, count 0 2006.285.17:01:20.59#ibcon#about to read 4, iclass 11, count 0 2006.285.17:01:20.59#ibcon#read 4, iclass 11, count 0 2006.285.17:01:20.59#ibcon#about to read 5, iclass 11, count 0 2006.285.17:01:20.59#ibcon#read 5, iclass 11, count 0 2006.285.17:01:20.59#ibcon#about to read 6, iclass 11, count 0 2006.285.17:01:20.59#ibcon#read 6, iclass 11, count 0 2006.285.17:01:20.59#ibcon#end of sib2, iclass 11, count 0 2006.285.17:01:20.59#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:01:20.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:01:20.59#ibcon#[25=USB\r\n] 2006.285.17:01:20.59#ibcon#*before write, iclass 11, count 0 2006.285.17:01:20.59#ibcon#enter sib2, iclass 11, count 0 2006.285.17:01:20.59#ibcon#flushed, iclass 11, count 0 2006.285.17:01:20.59#ibcon#about to write, iclass 11, count 0 2006.285.17:01:20.59#ibcon#wrote, iclass 11, count 0 2006.285.17:01:20.59#ibcon#about to read 3, iclass 11, count 0 2006.285.17:01:20.62#ibcon#read 3, iclass 11, count 0 2006.285.17:01:20.62#ibcon#about to read 4, iclass 11, count 0 2006.285.17:01:20.62#ibcon#read 4, iclass 11, count 0 2006.285.17:01:20.62#ibcon#about to read 5, iclass 11, count 0 2006.285.17:01:20.62#ibcon#read 5, iclass 11, count 0 2006.285.17:01:20.62#ibcon#about to read 6, iclass 11, count 0 2006.285.17:01:20.62#ibcon#read 6, iclass 11, count 0 2006.285.17:01:20.62#ibcon#end of sib2, iclass 11, count 0 2006.285.17:01:20.62#ibcon#*after write, iclass 11, count 0 2006.285.17:01:20.62#ibcon#*before return 0, iclass 11, count 0 2006.285.17:01:20.62#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:01:20.62#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:01:20.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:01:20.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:01:20.62$vck44/valo=3,564.99 2006.285.17:01:20.62#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.17:01:20.62#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.17:01:20.62#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:20.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:01:20.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:01:20.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:01:20.62#ibcon#enter wrdev, iclass 14, count 0 2006.285.17:01:20.62#ibcon#first serial, iclass 14, count 0 2006.285.17:01:20.62#ibcon#enter sib2, iclass 14, count 0 2006.285.17:01:20.62#ibcon#flushed, iclass 14, count 0 2006.285.17:01:20.62#ibcon#about to write, iclass 14, count 0 2006.285.17:01:20.62#ibcon#wrote, iclass 14, count 0 2006.285.17:01:20.62#ibcon#about to read 3, iclass 14, count 0 2006.285.17:01:20.64#ibcon#read 3, iclass 14, count 0 2006.285.17:01:20.64#ibcon#about to read 4, iclass 14, count 0 2006.285.17:01:20.64#ibcon#read 4, iclass 14, count 0 2006.285.17:01:20.64#ibcon#about to read 5, iclass 14, count 0 2006.285.17:01:20.64#ibcon#read 5, iclass 14, count 0 2006.285.17:01:20.64#ibcon#about to read 6, iclass 14, count 0 2006.285.17:01:20.64#ibcon#read 6, iclass 14, count 0 2006.285.17:01:20.64#ibcon#end of sib2, iclass 14, count 0 2006.285.17:01:20.64#ibcon#*mode == 0, iclass 14, count 0 2006.285.17:01:20.64#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.17:01:20.64#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.17:01:20.64#ibcon#*before write, iclass 14, count 0 2006.285.17:01:20.64#ibcon#enter sib2, iclass 14, count 0 2006.285.17:01:20.64#ibcon#flushed, iclass 14, count 0 2006.285.17:01:20.64#ibcon#about to write, iclass 14, count 0 2006.285.17:01:20.64#ibcon#wrote, iclass 14, count 0 2006.285.17:01:20.64#ibcon#about to read 3, iclass 14, count 0 2006.285.17:01:20.68#ibcon#read 3, iclass 14, count 0 2006.285.17:01:20.68#ibcon#about to read 4, iclass 14, count 0 2006.285.17:01:20.68#ibcon#read 4, iclass 14, count 0 2006.285.17:01:20.68#ibcon#about to read 5, iclass 14, count 0 2006.285.17:01:20.68#ibcon#read 5, iclass 14, count 0 2006.285.17:01:20.68#ibcon#about to read 6, iclass 14, count 0 2006.285.17:01:20.68#ibcon#read 6, iclass 14, count 0 2006.285.17:01:20.68#ibcon#end of sib2, iclass 14, count 0 2006.285.17:01:20.68#ibcon#*after write, iclass 14, count 0 2006.285.17:01:20.68#ibcon#*before return 0, iclass 14, count 0 2006.285.17:01:20.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:01:20.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:01:20.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.17:01:20.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.17:01:20.68$vck44/va=3,7 2006.285.17:01:20.68#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.17:01:20.68#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.17:01:20.68#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:20.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:01:20.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:01:20.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:01:20.74#ibcon#enter wrdev, iclass 16, count 2 2006.285.17:01:20.74#ibcon#first serial, iclass 16, count 2 2006.285.17:01:20.74#ibcon#enter sib2, iclass 16, count 2 2006.285.17:01:20.74#ibcon#flushed, iclass 16, count 2 2006.285.17:01:20.74#ibcon#about to write, iclass 16, count 2 2006.285.17:01:20.74#ibcon#wrote, iclass 16, count 2 2006.285.17:01:20.74#ibcon#about to read 3, iclass 16, count 2 2006.285.17:01:20.76#ibcon#read 3, iclass 16, count 2 2006.285.17:01:20.76#ibcon#about to read 4, iclass 16, count 2 2006.285.17:01:20.76#ibcon#read 4, iclass 16, count 2 2006.285.17:01:20.76#ibcon#about to read 5, iclass 16, count 2 2006.285.17:01:20.76#ibcon#read 5, iclass 16, count 2 2006.285.17:01:20.76#ibcon#about to read 6, iclass 16, count 2 2006.285.17:01:20.76#ibcon#read 6, iclass 16, count 2 2006.285.17:01:20.76#ibcon#end of sib2, iclass 16, count 2 2006.285.17:01:20.76#ibcon#*mode == 0, iclass 16, count 2 2006.285.17:01:20.76#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.17:01:20.76#ibcon#[25=AT03-07\r\n] 2006.285.17:01:20.76#ibcon#*before write, iclass 16, count 2 2006.285.17:01:20.76#ibcon#enter sib2, iclass 16, count 2 2006.285.17:01:20.76#ibcon#flushed, iclass 16, count 2 2006.285.17:01:20.76#ibcon#about to write, iclass 16, count 2 2006.285.17:01:20.76#ibcon#wrote, iclass 16, count 2 2006.285.17:01:20.76#ibcon#about to read 3, iclass 16, count 2 2006.285.17:01:20.79#ibcon#read 3, iclass 16, count 2 2006.285.17:01:20.79#ibcon#about to read 4, iclass 16, count 2 2006.285.17:01:20.79#ibcon#read 4, iclass 16, count 2 2006.285.17:01:20.79#ibcon#about to read 5, iclass 16, count 2 2006.285.17:01:20.79#ibcon#read 5, iclass 16, count 2 2006.285.17:01:20.79#ibcon#about to read 6, iclass 16, count 2 2006.285.17:01:20.79#ibcon#read 6, iclass 16, count 2 2006.285.17:01:20.79#ibcon#end of sib2, iclass 16, count 2 2006.285.17:01:20.79#ibcon#*after write, iclass 16, count 2 2006.285.17:01:20.79#ibcon#*before return 0, iclass 16, count 2 2006.285.17:01:20.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:01:20.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:01:20.79#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.17:01:20.79#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:20.79#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:01:20.91#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:01:20.91#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:01:20.91#ibcon#enter wrdev, iclass 16, count 0 2006.285.17:01:20.91#ibcon#first serial, iclass 16, count 0 2006.285.17:01:20.91#ibcon#enter sib2, iclass 16, count 0 2006.285.17:01:20.91#ibcon#flushed, iclass 16, count 0 2006.285.17:01:20.91#ibcon#about to write, iclass 16, count 0 2006.285.17:01:20.91#ibcon#wrote, iclass 16, count 0 2006.285.17:01:20.91#ibcon#about to read 3, iclass 16, count 0 2006.285.17:01:20.93#ibcon#read 3, iclass 16, count 0 2006.285.17:01:20.93#ibcon#about to read 4, iclass 16, count 0 2006.285.17:01:20.93#ibcon#read 4, iclass 16, count 0 2006.285.17:01:20.93#ibcon#about to read 5, iclass 16, count 0 2006.285.17:01:20.93#ibcon#read 5, iclass 16, count 0 2006.285.17:01:20.93#ibcon#about to read 6, iclass 16, count 0 2006.285.17:01:20.93#ibcon#read 6, iclass 16, count 0 2006.285.17:01:20.93#ibcon#end of sib2, iclass 16, count 0 2006.285.17:01:20.93#ibcon#*mode == 0, iclass 16, count 0 2006.285.17:01:20.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.17:01:20.93#ibcon#[25=USB\r\n] 2006.285.17:01:20.93#ibcon#*before write, iclass 16, count 0 2006.285.17:01:20.93#ibcon#enter sib2, iclass 16, count 0 2006.285.17:01:20.93#ibcon#flushed, iclass 16, count 0 2006.285.17:01:20.93#ibcon#about to write, iclass 16, count 0 2006.285.17:01:20.93#ibcon#wrote, iclass 16, count 0 2006.285.17:01:20.93#ibcon#about to read 3, iclass 16, count 0 2006.285.17:01:20.96#ibcon#read 3, iclass 16, count 0 2006.285.17:01:20.96#ibcon#about to read 4, iclass 16, count 0 2006.285.17:01:20.96#ibcon#read 4, iclass 16, count 0 2006.285.17:01:20.96#ibcon#about to read 5, iclass 16, count 0 2006.285.17:01:20.96#ibcon#read 5, iclass 16, count 0 2006.285.17:01:20.96#ibcon#about to read 6, iclass 16, count 0 2006.285.17:01:20.96#ibcon#read 6, iclass 16, count 0 2006.285.17:01:20.96#ibcon#end of sib2, iclass 16, count 0 2006.285.17:01:20.96#ibcon#*after write, iclass 16, count 0 2006.285.17:01:20.96#ibcon#*before return 0, iclass 16, count 0 2006.285.17:01:20.96#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:01:20.96#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:01:20.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.17:01:20.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.17:01:20.96$vck44/valo=4,624.99 2006.285.17:01:20.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.17:01:20.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.17:01:20.96#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:20.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:01:20.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:01:20.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:01:20.96#ibcon#enter wrdev, iclass 18, count 0 2006.285.17:01:20.96#ibcon#first serial, iclass 18, count 0 2006.285.17:01:20.96#ibcon#enter sib2, iclass 18, count 0 2006.285.17:01:20.96#ibcon#flushed, iclass 18, count 0 2006.285.17:01:20.96#ibcon#about to write, iclass 18, count 0 2006.285.17:01:20.96#ibcon#wrote, iclass 18, count 0 2006.285.17:01:20.96#ibcon#about to read 3, iclass 18, count 0 2006.285.17:01:20.98#ibcon#read 3, iclass 18, count 0 2006.285.17:01:20.98#ibcon#about to read 4, iclass 18, count 0 2006.285.17:01:20.98#ibcon#read 4, iclass 18, count 0 2006.285.17:01:20.98#ibcon#about to read 5, iclass 18, count 0 2006.285.17:01:20.98#ibcon#read 5, iclass 18, count 0 2006.285.17:01:20.98#ibcon#about to read 6, iclass 18, count 0 2006.285.17:01:20.98#ibcon#read 6, iclass 18, count 0 2006.285.17:01:20.98#ibcon#end of sib2, iclass 18, count 0 2006.285.17:01:20.98#ibcon#*mode == 0, iclass 18, count 0 2006.285.17:01:20.98#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.17:01:20.98#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.17:01:20.98#ibcon#*before write, iclass 18, count 0 2006.285.17:01:20.98#ibcon#enter sib2, iclass 18, count 0 2006.285.17:01:20.98#ibcon#flushed, iclass 18, count 0 2006.285.17:01:20.98#ibcon#about to write, iclass 18, count 0 2006.285.17:01:20.98#ibcon#wrote, iclass 18, count 0 2006.285.17:01:20.98#ibcon#about to read 3, iclass 18, count 0 2006.285.17:01:21.02#ibcon#read 3, iclass 18, count 0 2006.285.17:01:21.02#ibcon#about to read 4, iclass 18, count 0 2006.285.17:01:21.02#ibcon#read 4, iclass 18, count 0 2006.285.17:01:21.02#ibcon#about to read 5, iclass 18, count 0 2006.285.17:01:21.02#ibcon#read 5, iclass 18, count 0 2006.285.17:01:21.02#ibcon#about to read 6, iclass 18, count 0 2006.285.17:01:21.02#ibcon#read 6, iclass 18, count 0 2006.285.17:01:21.02#ibcon#end of sib2, iclass 18, count 0 2006.285.17:01:21.02#ibcon#*after write, iclass 18, count 0 2006.285.17:01:21.02#ibcon#*before return 0, iclass 18, count 0 2006.285.17:01:21.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:01:21.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:01:21.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.17:01:21.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.17:01:21.02$vck44/va=4,6 2006.285.17:01:21.02#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.17:01:21.02#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.17:01:21.02#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:21.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:01:21.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:01:21.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:01:21.08#ibcon#enter wrdev, iclass 20, count 2 2006.285.17:01:21.08#ibcon#first serial, iclass 20, count 2 2006.285.17:01:21.08#ibcon#enter sib2, iclass 20, count 2 2006.285.17:01:21.08#ibcon#flushed, iclass 20, count 2 2006.285.17:01:21.08#ibcon#about to write, iclass 20, count 2 2006.285.17:01:21.08#ibcon#wrote, iclass 20, count 2 2006.285.17:01:21.08#ibcon#about to read 3, iclass 20, count 2 2006.285.17:01:21.10#ibcon#read 3, iclass 20, count 2 2006.285.17:01:21.10#ibcon#about to read 4, iclass 20, count 2 2006.285.17:01:21.10#ibcon#read 4, iclass 20, count 2 2006.285.17:01:21.10#ibcon#about to read 5, iclass 20, count 2 2006.285.17:01:21.10#ibcon#read 5, iclass 20, count 2 2006.285.17:01:21.10#ibcon#about to read 6, iclass 20, count 2 2006.285.17:01:21.10#ibcon#read 6, iclass 20, count 2 2006.285.17:01:21.10#ibcon#end of sib2, iclass 20, count 2 2006.285.17:01:21.10#ibcon#*mode == 0, iclass 20, count 2 2006.285.17:01:21.10#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.17:01:21.10#ibcon#[25=AT04-06\r\n] 2006.285.17:01:21.10#ibcon#*before write, iclass 20, count 2 2006.285.17:01:21.10#ibcon#enter sib2, iclass 20, count 2 2006.285.17:01:21.10#ibcon#flushed, iclass 20, count 2 2006.285.17:01:21.10#ibcon#about to write, iclass 20, count 2 2006.285.17:01:21.10#ibcon#wrote, iclass 20, count 2 2006.285.17:01:21.10#ibcon#about to read 3, iclass 20, count 2 2006.285.17:01:21.13#ibcon#read 3, iclass 20, count 2 2006.285.17:01:21.26#ibcon#about to read 4, iclass 20, count 2 2006.285.17:01:21.26#ibcon#read 4, iclass 20, count 2 2006.285.17:01:21.26#ibcon#about to read 5, iclass 20, count 2 2006.285.17:01:21.26#ibcon#read 5, iclass 20, count 2 2006.285.17:01:21.26#ibcon#about to read 6, iclass 20, count 2 2006.285.17:01:21.26#ibcon#read 6, iclass 20, count 2 2006.285.17:01:21.26#ibcon#end of sib2, iclass 20, count 2 2006.285.17:01:21.26#ibcon#*after write, iclass 20, count 2 2006.285.17:01:21.26#ibcon#*before return 0, iclass 20, count 2 2006.285.17:01:21.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:01:21.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:01:21.26#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.17:01:21.26#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:21.26#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:01:21.38#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:01:21.38#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:01:21.38#ibcon#enter wrdev, iclass 20, count 0 2006.285.17:01:21.38#ibcon#first serial, iclass 20, count 0 2006.285.17:01:21.38#ibcon#enter sib2, iclass 20, count 0 2006.285.17:01:21.38#ibcon#flushed, iclass 20, count 0 2006.285.17:01:21.38#ibcon#about to write, iclass 20, count 0 2006.285.17:01:21.38#ibcon#wrote, iclass 20, count 0 2006.285.17:01:21.38#ibcon#about to read 3, iclass 20, count 0 2006.285.17:01:21.40#ibcon#read 3, iclass 20, count 0 2006.285.17:01:21.40#ibcon#about to read 4, iclass 20, count 0 2006.285.17:01:21.40#ibcon#read 4, iclass 20, count 0 2006.285.17:01:21.40#ibcon#about to read 5, iclass 20, count 0 2006.285.17:01:21.40#ibcon#read 5, iclass 20, count 0 2006.285.17:01:21.40#ibcon#about to read 6, iclass 20, count 0 2006.285.17:01:21.40#ibcon#read 6, iclass 20, count 0 2006.285.17:01:21.40#ibcon#end of sib2, iclass 20, count 0 2006.285.17:01:21.40#ibcon#*mode == 0, iclass 20, count 0 2006.285.17:01:21.40#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.17:01:21.40#ibcon#[25=USB\r\n] 2006.285.17:01:21.40#ibcon#*before write, iclass 20, count 0 2006.285.17:01:21.40#ibcon#enter sib2, iclass 20, count 0 2006.285.17:01:21.40#ibcon#flushed, iclass 20, count 0 2006.285.17:01:21.40#ibcon#about to write, iclass 20, count 0 2006.285.17:01:21.40#ibcon#wrote, iclass 20, count 0 2006.285.17:01:21.40#ibcon#about to read 3, iclass 20, count 0 2006.285.17:01:21.43#ibcon#read 3, iclass 20, count 0 2006.285.17:01:21.43#ibcon#about to read 4, iclass 20, count 0 2006.285.17:01:21.43#ibcon#read 4, iclass 20, count 0 2006.285.17:01:21.43#ibcon#about to read 5, iclass 20, count 0 2006.285.17:01:21.43#ibcon#read 5, iclass 20, count 0 2006.285.17:01:21.43#ibcon#about to read 6, iclass 20, count 0 2006.285.17:01:21.43#ibcon#read 6, iclass 20, count 0 2006.285.17:01:21.43#ibcon#end of sib2, iclass 20, count 0 2006.285.17:01:21.43#ibcon#*after write, iclass 20, count 0 2006.285.17:01:21.43#ibcon#*before return 0, iclass 20, count 0 2006.285.17:01:21.43#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:01:21.43#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:01:21.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.17:01:21.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.17:01:21.43$vck44/valo=5,734.99 2006.285.17:01:21.43#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.17:01:21.43#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.17:01:21.43#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:21.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:01:21.43#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:01:21.43#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:01:21.43#ibcon#enter wrdev, iclass 22, count 0 2006.285.17:01:21.43#ibcon#first serial, iclass 22, count 0 2006.285.17:01:21.43#ibcon#enter sib2, iclass 22, count 0 2006.285.17:01:21.43#ibcon#flushed, iclass 22, count 0 2006.285.17:01:21.43#ibcon#about to write, iclass 22, count 0 2006.285.17:01:21.43#ibcon#wrote, iclass 22, count 0 2006.285.17:01:21.43#ibcon#about to read 3, iclass 22, count 0 2006.285.17:01:21.45#ibcon#read 3, iclass 22, count 0 2006.285.17:01:21.45#ibcon#about to read 4, iclass 22, count 0 2006.285.17:01:21.45#ibcon#read 4, iclass 22, count 0 2006.285.17:01:21.45#ibcon#about to read 5, iclass 22, count 0 2006.285.17:01:21.45#ibcon#read 5, iclass 22, count 0 2006.285.17:01:21.45#ibcon#about to read 6, iclass 22, count 0 2006.285.17:01:21.45#ibcon#read 6, iclass 22, count 0 2006.285.17:01:21.45#ibcon#end of sib2, iclass 22, count 0 2006.285.17:01:21.45#ibcon#*mode == 0, iclass 22, count 0 2006.285.17:01:21.45#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.17:01:21.45#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.17:01:21.45#ibcon#*before write, iclass 22, count 0 2006.285.17:01:21.45#ibcon#enter sib2, iclass 22, count 0 2006.285.17:01:21.45#ibcon#flushed, iclass 22, count 0 2006.285.17:01:21.45#ibcon#about to write, iclass 22, count 0 2006.285.17:01:21.45#ibcon#wrote, iclass 22, count 0 2006.285.17:01:21.45#ibcon#about to read 3, iclass 22, count 0 2006.285.17:01:21.49#ibcon#read 3, iclass 22, count 0 2006.285.17:01:21.49#ibcon#about to read 4, iclass 22, count 0 2006.285.17:01:21.49#ibcon#read 4, iclass 22, count 0 2006.285.17:01:21.49#ibcon#about to read 5, iclass 22, count 0 2006.285.17:01:21.49#ibcon#read 5, iclass 22, count 0 2006.285.17:01:21.49#ibcon#about to read 6, iclass 22, count 0 2006.285.17:01:21.49#ibcon#read 6, iclass 22, count 0 2006.285.17:01:21.49#ibcon#end of sib2, iclass 22, count 0 2006.285.17:01:21.49#ibcon#*after write, iclass 22, count 0 2006.285.17:01:21.49#ibcon#*before return 0, iclass 22, count 0 2006.285.17:01:21.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:01:21.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:01:21.49#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.17:01:21.49#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.17:01:21.49$vck44/va=5,3 2006.285.17:01:21.49#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.17:01:21.49#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.17:01:21.49#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:21.49#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:01:21.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:01:21.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:01:21.55#ibcon#enter wrdev, iclass 24, count 2 2006.285.17:01:21.55#ibcon#first serial, iclass 24, count 2 2006.285.17:01:21.55#ibcon#enter sib2, iclass 24, count 2 2006.285.17:01:21.55#ibcon#flushed, iclass 24, count 2 2006.285.17:01:21.55#ibcon#about to write, iclass 24, count 2 2006.285.17:01:21.55#ibcon#wrote, iclass 24, count 2 2006.285.17:01:21.55#ibcon#about to read 3, iclass 24, count 2 2006.285.17:01:21.57#ibcon#read 3, iclass 24, count 2 2006.285.17:01:21.57#ibcon#about to read 4, iclass 24, count 2 2006.285.17:01:21.57#ibcon#read 4, iclass 24, count 2 2006.285.17:01:21.57#ibcon#about to read 5, iclass 24, count 2 2006.285.17:01:21.57#ibcon#read 5, iclass 24, count 2 2006.285.17:01:21.57#ibcon#about to read 6, iclass 24, count 2 2006.285.17:01:21.57#ibcon#read 6, iclass 24, count 2 2006.285.17:01:21.57#ibcon#end of sib2, iclass 24, count 2 2006.285.17:01:21.57#ibcon#*mode == 0, iclass 24, count 2 2006.285.17:01:21.57#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.17:01:21.57#ibcon#[25=AT05-03\r\n] 2006.285.17:01:21.57#ibcon#*before write, iclass 24, count 2 2006.285.17:01:21.57#ibcon#enter sib2, iclass 24, count 2 2006.285.17:01:21.57#ibcon#flushed, iclass 24, count 2 2006.285.17:01:21.57#ibcon#about to write, iclass 24, count 2 2006.285.17:01:21.57#ibcon#wrote, iclass 24, count 2 2006.285.17:01:21.57#ibcon#about to read 3, iclass 24, count 2 2006.285.17:01:21.60#ibcon#read 3, iclass 24, count 2 2006.285.17:01:21.60#ibcon#about to read 4, iclass 24, count 2 2006.285.17:01:21.60#ibcon#read 4, iclass 24, count 2 2006.285.17:01:21.60#ibcon#about to read 5, iclass 24, count 2 2006.285.17:01:21.60#ibcon#read 5, iclass 24, count 2 2006.285.17:01:21.60#ibcon#about to read 6, iclass 24, count 2 2006.285.17:01:21.60#ibcon#read 6, iclass 24, count 2 2006.285.17:01:21.60#ibcon#end of sib2, iclass 24, count 2 2006.285.17:01:21.60#ibcon#*after write, iclass 24, count 2 2006.285.17:01:21.60#ibcon#*before return 0, iclass 24, count 2 2006.285.17:01:21.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:01:21.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:01:21.60#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.17:01:21.60#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:21.60#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:01:21.72#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:01:21.72#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:01:21.72#ibcon#enter wrdev, iclass 24, count 0 2006.285.17:01:21.72#ibcon#first serial, iclass 24, count 0 2006.285.17:01:21.72#ibcon#enter sib2, iclass 24, count 0 2006.285.17:01:21.72#ibcon#flushed, iclass 24, count 0 2006.285.17:01:21.72#ibcon#about to write, iclass 24, count 0 2006.285.17:01:21.72#ibcon#wrote, iclass 24, count 0 2006.285.17:01:21.72#ibcon#about to read 3, iclass 24, count 0 2006.285.17:01:21.74#ibcon#read 3, iclass 24, count 0 2006.285.17:01:21.74#ibcon#about to read 4, iclass 24, count 0 2006.285.17:01:21.74#ibcon#read 4, iclass 24, count 0 2006.285.17:01:21.74#ibcon#about to read 5, iclass 24, count 0 2006.285.17:01:21.74#ibcon#read 5, iclass 24, count 0 2006.285.17:01:21.74#ibcon#about to read 6, iclass 24, count 0 2006.285.17:01:21.74#ibcon#read 6, iclass 24, count 0 2006.285.17:01:21.74#ibcon#end of sib2, iclass 24, count 0 2006.285.17:01:21.74#ibcon#*mode == 0, iclass 24, count 0 2006.285.17:01:21.74#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.17:01:21.74#ibcon#[25=USB\r\n] 2006.285.17:01:21.74#ibcon#*before write, iclass 24, count 0 2006.285.17:01:21.74#ibcon#enter sib2, iclass 24, count 0 2006.285.17:01:21.74#ibcon#flushed, iclass 24, count 0 2006.285.17:01:21.74#ibcon#about to write, iclass 24, count 0 2006.285.17:01:21.74#ibcon#wrote, iclass 24, count 0 2006.285.17:01:21.74#ibcon#about to read 3, iclass 24, count 0 2006.285.17:01:21.77#ibcon#read 3, iclass 24, count 0 2006.285.17:01:21.77#ibcon#about to read 4, iclass 24, count 0 2006.285.17:01:21.77#ibcon#read 4, iclass 24, count 0 2006.285.17:01:21.77#ibcon#about to read 5, iclass 24, count 0 2006.285.17:01:21.77#ibcon#read 5, iclass 24, count 0 2006.285.17:01:21.77#ibcon#about to read 6, iclass 24, count 0 2006.285.17:01:21.77#ibcon#read 6, iclass 24, count 0 2006.285.17:01:21.77#ibcon#end of sib2, iclass 24, count 0 2006.285.17:01:21.77#ibcon#*after write, iclass 24, count 0 2006.285.17:01:21.77#ibcon#*before return 0, iclass 24, count 0 2006.285.17:01:21.77#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:01:21.77#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:01:21.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.17:01:21.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.17:01:21.77$vck44/valo=6,814.99 2006.285.17:01:21.77#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.17:01:21.77#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.17:01:21.77#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:21.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:01:21.77#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:01:21.77#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:01:21.77#ibcon#enter wrdev, iclass 26, count 0 2006.285.17:01:21.77#ibcon#first serial, iclass 26, count 0 2006.285.17:01:21.77#ibcon#enter sib2, iclass 26, count 0 2006.285.17:01:21.77#ibcon#flushed, iclass 26, count 0 2006.285.17:01:21.77#ibcon#about to write, iclass 26, count 0 2006.285.17:01:21.77#ibcon#wrote, iclass 26, count 0 2006.285.17:01:21.77#ibcon#about to read 3, iclass 26, count 0 2006.285.17:01:21.79#ibcon#read 3, iclass 26, count 0 2006.285.17:01:21.89#ibcon#about to read 4, iclass 26, count 0 2006.285.17:01:21.89#ibcon#read 4, iclass 26, count 0 2006.285.17:01:21.89#ibcon#about to read 5, iclass 26, count 0 2006.285.17:01:21.89#ibcon#read 5, iclass 26, count 0 2006.285.17:01:21.89#ibcon#about to read 6, iclass 26, count 0 2006.285.17:01:21.89#ibcon#read 6, iclass 26, count 0 2006.285.17:01:21.89#ibcon#end of sib2, iclass 26, count 0 2006.285.17:01:21.89#ibcon#*mode == 0, iclass 26, count 0 2006.285.17:01:21.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.17:01:21.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.17:01:21.89#ibcon#*before write, iclass 26, count 0 2006.285.17:01:21.89#ibcon#enter sib2, iclass 26, count 0 2006.285.17:01:21.89#ibcon#flushed, iclass 26, count 0 2006.285.17:01:21.89#ibcon#about to write, iclass 26, count 0 2006.285.17:01:21.89#ibcon#wrote, iclass 26, count 0 2006.285.17:01:21.89#ibcon#about to read 3, iclass 26, count 0 2006.285.17:01:21.93#ibcon#read 3, iclass 26, count 0 2006.285.17:01:21.93#ibcon#about to read 4, iclass 26, count 0 2006.285.17:01:21.93#ibcon#read 4, iclass 26, count 0 2006.285.17:01:21.93#ibcon#about to read 5, iclass 26, count 0 2006.285.17:01:21.93#ibcon#read 5, iclass 26, count 0 2006.285.17:01:21.93#ibcon#about to read 6, iclass 26, count 0 2006.285.17:01:21.93#ibcon#read 6, iclass 26, count 0 2006.285.17:01:21.93#ibcon#end of sib2, iclass 26, count 0 2006.285.17:01:21.93#ibcon#*after write, iclass 26, count 0 2006.285.17:01:21.93#ibcon#*before return 0, iclass 26, count 0 2006.285.17:01:21.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:01:21.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:01:21.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.17:01:21.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.17:01:21.93$vck44/va=6,4 2006.285.17:01:21.93#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.17:01:21.93#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.17:01:21.93#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:21.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:01:21.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:01:21.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:01:21.93#ibcon#enter wrdev, iclass 28, count 2 2006.285.17:01:21.93#ibcon#first serial, iclass 28, count 2 2006.285.17:01:21.93#ibcon#enter sib2, iclass 28, count 2 2006.285.17:01:21.93#ibcon#flushed, iclass 28, count 2 2006.285.17:01:21.93#ibcon#about to write, iclass 28, count 2 2006.285.17:01:21.93#ibcon#wrote, iclass 28, count 2 2006.285.17:01:21.93#ibcon#about to read 3, iclass 28, count 2 2006.285.17:01:21.95#ibcon#read 3, iclass 28, count 2 2006.285.17:01:21.95#ibcon#about to read 4, iclass 28, count 2 2006.285.17:01:21.95#ibcon#read 4, iclass 28, count 2 2006.285.17:01:21.95#ibcon#about to read 5, iclass 28, count 2 2006.285.17:01:21.95#ibcon#read 5, iclass 28, count 2 2006.285.17:01:21.95#ibcon#about to read 6, iclass 28, count 2 2006.285.17:01:21.95#ibcon#read 6, iclass 28, count 2 2006.285.17:01:21.95#ibcon#end of sib2, iclass 28, count 2 2006.285.17:01:21.95#ibcon#*mode == 0, iclass 28, count 2 2006.285.17:01:21.95#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.17:01:21.95#ibcon#[25=AT06-04\r\n] 2006.285.17:01:21.95#ibcon#*before write, iclass 28, count 2 2006.285.17:01:21.95#ibcon#enter sib2, iclass 28, count 2 2006.285.17:01:21.95#ibcon#flushed, iclass 28, count 2 2006.285.17:01:21.95#ibcon#about to write, iclass 28, count 2 2006.285.17:01:21.95#ibcon#wrote, iclass 28, count 2 2006.285.17:01:21.95#ibcon#about to read 3, iclass 28, count 2 2006.285.17:01:21.98#ibcon#read 3, iclass 28, count 2 2006.285.17:01:21.98#ibcon#about to read 4, iclass 28, count 2 2006.285.17:01:21.98#ibcon#read 4, iclass 28, count 2 2006.285.17:01:21.98#ibcon#about to read 5, iclass 28, count 2 2006.285.17:01:21.98#ibcon#read 5, iclass 28, count 2 2006.285.17:01:21.98#ibcon#about to read 6, iclass 28, count 2 2006.285.17:01:21.98#ibcon#read 6, iclass 28, count 2 2006.285.17:01:21.98#ibcon#end of sib2, iclass 28, count 2 2006.285.17:01:21.98#ibcon#*after write, iclass 28, count 2 2006.285.17:01:21.98#ibcon#*before return 0, iclass 28, count 2 2006.285.17:01:21.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:01:21.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:01:21.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.17:01:21.98#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:21.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:01:22.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:01:22.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:01:22.10#ibcon#enter wrdev, iclass 28, count 0 2006.285.17:01:22.10#ibcon#first serial, iclass 28, count 0 2006.285.17:01:22.10#ibcon#enter sib2, iclass 28, count 0 2006.285.17:01:22.10#ibcon#flushed, iclass 28, count 0 2006.285.17:01:22.10#ibcon#about to write, iclass 28, count 0 2006.285.17:01:22.10#ibcon#wrote, iclass 28, count 0 2006.285.17:01:22.10#ibcon#about to read 3, iclass 28, count 0 2006.285.17:01:22.12#ibcon#read 3, iclass 28, count 0 2006.285.17:01:22.12#ibcon#about to read 4, iclass 28, count 0 2006.285.17:01:22.12#ibcon#read 4, iclass 28, count 0 2006.285.17:01:22.12#ibcon#about to read 5, iclass 28, count 0 2006.285.17:01:22.12#ibcon#read 5, iclass 28, count 0 2006.285.17:01:22.12#ibcon#about to read 6, iclass 28, count 0 2006.285.17:01:22.12#ibcon#read 6, iclass 28, count 0 2006.285.17:01:22.12#ibcon#end of sib2, iclass 28, count 0 2006.285.17:01:22.12#ibcon#*mode == 0, iclass 28, count 0 2006.285.17:01:22.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.17:01:22.12#ibcon#[25=USB\r\n] 2006.285.17:01:22.12#ibcon#*before write, iclass 28, count 0 2006.285.17:01:22.12#ibcon#enter sib2, iclass 28, count 0 2006.285.17:01:22.12#ibcon#flushed, iclass 28, count 0 2006.285.17:01:22.12#ibcon#about to write, iclass 28, count 0 2006.285.17:01:22.12#ibcon#wrote, iclass 28, count 0 2006.285.17:01:22.12#ibcon#about to read 3, iclass 28, count 0 2006.285.17:01:22.15#ibcon#read 3, iclass 28, count 0 2006.285.17:01:22.15#ibcon#about to read 4, iclass 28, count 0 2006.285.17:01:22.15#ibcon#read 4, iclass 28, count 0 2006.285.17:01:22.15#ibcon#about to read 5, iclass 28, count 0 2006.285.17:01:22.15#ibcon#read 5, iclass 28, count 0 2006.285.17:01:22.15#ibcon#about to read 6, iclass 28, count 0 2006.285.17:01:22.15#ibcon#read 6, iclass 28, count 0 2006.285.17:01:22.15#ibcon#end of sib2, iclass 28, count 0 2006.285.17:01:22.15#ibcon#*after write, iclass 28, count 0 2006.285.17:01:22.15#ibcon#*before return 0, iclass 28, count 0 2006.285.17:01:22.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:01:22.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:01:22.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.17:01:22.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.17:01:22.15$vck44/valo=7,864.99 2006.285.17:01:22.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.17:01:22.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.17:01:22.15#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:22.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:01:22.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:01:22.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:01:22.15#ibcon#enter wrdev, iclass 30, count 0 2006.285.17:01:22.15#ibcon#first serial, iclass 30, count 0 2006.285.17:01:22.15#ibcon#enter sib2, iclass 30, count 0 2006.285.17:01:22.15#ibcon#flushed, iclass 30, count 0 2006.285.17:01:22.15#ibcon#about to write, iclass 30, count 0 2006.285.17:01:22.15#ibcon#wrote, iclass 30, count 0 2006.285.17:01:22.15#ibcon#about to read 3, iclass 30, count 0 2006.285.17:01:22.17#ibcon#read 3, iclass 30, count 0 2006.285.17:01:22.17#ibcon#about to read 4, iclass 30, count 0 2006.285.17:01:22.17#ibcon#read 4, iclass 30, count 0 2006.285.17:01:22.17#ibcon#about to read 5, iclass 30, count 0 2006.285.17:01:22.17#ibcon#read 5, iclass 30, count 0 2006.285.17:01:22.17#ibcon#about to read 6, iclass 30, count 0 2006.285.17:01:22.17#ibcon#read 6, iclass 30, count 0 2006.285.17:01:22.17#ibcon#end of sib2, iclass 30, count 0 2006.285.17:01:22.17#ibcon#*mode == 0, iclass 30, count 0 2006.285.17:01:22.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.17:01:22.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.17:01:22.17#ibcon#*before write, iclass 30, count 0 2006.285.17:01:22.17#ibcon#enter sib2, iclass 30, count 0 2006.285.17:01:22.17#ibcon#flushed, iclass 30, count 0 2006.285.17:01:22.17#ibcon#about to write, iclass 30, count 0 2006.285.17:01:22.17#ibcon#wrote, iclass 30, count 0 2006.285.17:01:22.17#ibcon#about to read 3, iclass 30, count 0 2006.285.17:01:22.21#ibcon#read 3, iclass 30, count 0 2006.285.17:01:22.21#ibcon#about to read 4, iclass 30, count 0 2006.285.17:01:22.21#ibcon#read 4, iclass 30, count 0 2006.285.17:01:22.21#ibcon#about to read 5, iclass 30, count 0 2006.285.17:01:22.21#ibcon#read 5, iclass 30, count 0 2006.285.17:01:22.21#ibcon#about to read 6, iclass 30, count 0 2006.285.17:01:22.21#ibcon#read 6, iclass 30, count 0 2006.285.17:01:22.21#ibcon#end of sib2, iclass 30, count 0 2006.285.17:01:22.21#ibcon#*after write, iclass 30, count 0 2006.285.17:01:22.21#ibcon#*before return 0, iclass 30, count 0 2006.285.17:01:22.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:01:22.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:01:22.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.17:01:22.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.17:01:22.21$vck44/va=7,4 2006.285.17:01:22.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.17:01:22.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.17:01:22.21#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:22.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:01:22.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:01:22.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:01:22.27#ibcon#enter wrdev, iclass 32, count 2 2006.285.17:01:22.27#ibcon#first serial, iclass 32, count 2 2006.285.17:01:22.27#ibcon#enter sib2, iclass 32, count 2 2006.285.17:01:22.27#ibcon#flushed, iclass 32, count 2 2006.285.17:01:22.27#ibcon#about to write, iclass 32, count 2 2006.285.17:01:22.27#ibcon#wrote, iclass 32, count 2 2006.285.17:01:22.27#ibcon#about to read 3, iclass 32, count 2 2006.285.17:01:22.29#ibcon#read 3, iclass 32, count 2 2006.285.17:01:22.29#ibcon#about to read 4, iclass 32, count 2 2006.285.17:01:22.29#ibcon#read 4, iclass 32, count 2 2006.285.17:01:22.29#ibcon#about to read 5, iclass 32, count 2 2006.285.17:01:22.29#ibcon#read 5, iclass 32, count 2 2006.285.17:01:22.29#ibcon#about to read 6, iclass 32, count 2 2006.285.17:01:22.29#ibcon#read 6, iclass 32, count 2 2006.285.17:01:22.29#ibcon#end of sib2, iclass 32, count 2 2006.285.17:01:22.29#ibcon#*mode == 0, iclass 32, count 2 2006.285.17:01:22.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.17:01:22.29#ibcon#[25=AT07-04\r\n] 2006.285.17:01:22.29#ibcon#*before write, iclass 32, count 2 2006.285.17:01:22.29#ibcon#enter sib2, iclass 32, count 2 2006.285.17:01:22.29#ibcon#flushed, iclass 32, count 2 2006.285.17:01:22.29#ibcon#about to write, iclass 32, count 2 2006.285.17:01:22.29#ibcon#wrote, iclass 32, count 2 2006.285.17:01:22.29#ibcon#about to read 3, iclass 32, count 2 2006.285.17:01:22.32#ibcon#read 3, iclass 32, count 2 2006.285.17:01:22.32#ibcon#about to read 4, iclass 32, count 2 2006.285.17:01:22.32#ibcon#read 4, iclass 32, count 2 2006.285.17:01:22.32#ibcon#about to read 5, iclass 32, count 2 2006.285.17:01:22.32#ibcon#read 5, iclass 32, count 2 2006.285.17:01:22.32#ibcon#about to read 6, iclass 32, count 2 2006.285.17:01:22.32#ibcon#read 6, iclass 32, count 2 2006.285.17:01:22.32#ibcon#end of sib2, iclass 32, count 2 2006.285.17:01:22.32#ibcon#*after write, iclass 32, count 2 2006.285.17:01:22.32#ibcon#*before return 0, iclass 32, count 2 2006.285.17:01:22.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:01:22.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:01:22.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.17:01:22.32#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:22.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:01:22.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:01:22.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:01:22.44#ibcon#enter wrdev, iclass 32, count 0 2006.285.17:01:22.44#ibcon#first serial, iclass 32, count 0 2006.285.17:01:22.44#ibcon#enter sib2, iclass 32, count 0 2006.285.17:01:22.44#ibcon#flushed, iclass 32, count 0 2006.285.17:01:22.44#ibcon#about to write, iclass 32, count 0 2006.285.17:01:22.44#ibcon#wrote, iclass 32, count 0 2006.285.17:01:22.44#ibcon#about to read 3, iclass 32, count 0 2006.285.17:01:22.46#ibcon#read 3, iclass 32, count 0 2006.285.17:01:22.46#ibcon#about to read 4, iclass 32, count 0 2006.285.17:01:22.46#ibcon#read 4, iclass 32, count 0 2006.285.17:01:22.46#ibcon#about to read 5, iclass 32, count 0 2006.285.17:01:22.46#ibcon#read 5, iclass 32, count 0 2006.285.17:01:22.46#ibcon#about to read 6, iclass 32, count 0 2006.285.17:01:22.46#ibcon#read 6, iclass 32, count 0 2006.285.17:01:22.46#ibcon#end of sib2, iclass 32, count 0 2006.285.17:01:22.46#ibcon#*mode == 0, iclass 32, count 0 2006.285.17:01:22.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.17:01:22.46#ibcon#[25=USB\r\n] 2006.285.17:01:22.46#ibcon#*before write, iclass 32, count 0 2006.285.17:01:22.46#ibcon#enter sib2, iclass 32, count 0 2006.285.17:01:22.46#ibcon#flushed, iclass 32, count 0 2006.285.17:01:22.46#ibcon#about to write, iclass 32, count 0 2006.285.17:01:22.46#ibcon#wrote, iclass 32, count 0 2006.285.17:01:22.46#ibcon#about to read 3, iclass 32, count 0 2006.285.17:01:22.49#ibcon#read 3, iclass 32, count 0 2006.285.17:01:22.49#ibcon#about to read 4, iclass 32, count 0 2006.285.17:01:22.49#ibcon#read 4, iclass 32, count 0 2006.285.17:01:22.49#ibcon#about to read 5, iclass 32, count 0 2006.285.17:01:22.49#ibcon#read 5, iclass 32, count 0 2006.285.17:01:22.49#ibcon#about to read 6, iclass 32, count 0 2006.285.17:01:22.49#ibcon#read 6, iclass 32, count 0 2006.285.17:01:22.49#ibcon#end of sib2, iclass 32, count 0 2006.285.17:01:22.49#ibcon#*after write, iclass 32, count 0 2006.285.17:01:22.49#ibcon#*before return 0, iclass 32, count 0 2006.285.17:01:22.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:01:22.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:01:22.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.17:01:22.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.17:01:22.49$vck44/valo=8,884.99 2006.285.17:01:22.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.17:01:22.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.17:01:22.49#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:22.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:01:22.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:01:22.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:01:22.49#ibcon#enter wrdev, iclass 34, count 0 2006.285.17:01:22.49#ibcon#first serial, iclass 34, count 0 2006.285.17:01:22.49#ibcon#enter sib2, iclass 34, count 0 2006.285.17:01:22.49#ibcon#flushed, iclass 34, count 0 2006.285.17:01:22.49#ibcon#about to write, iclass 34, count 0 2006.285.17:01:22.49#ibcon#wrote, iclass 34, count 0 2006.285.17:01:22.49#ibcon#about to read 3, iclass 34, count 0 2006.285.17:01:22.51#ibcon#read 3, iclass 34, count 0 2006.285.17:01:22.51#ibcon#about to read 4, iclass 34, count 0 2006.285.17:01:22.51#ibcon#read 4, iclass 34, count 0 2006.285.17:01:22.51#ibcon#about to read 5, iclass 34, count 0 2006.285.17:01:22.51#ibcon#read 5, iclass 34, count 0 2006.285.17:01:22.51#ibcon#about to read 6, iclass 34, count 0 2006.285.17:01:22.51#ibcon#read 6, iclass 34, count 0 2006.285.17:01:22.51#ibcon#end of sib2, iclass 34, count 0 2006.285.17:01:22.51#ibcon#*mode == 0, iclass 34, count 0 2006.285.17:01:22.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.17:01:22.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.17:01:22.51#ibcon#*before write, iclass 34, count 0 2006.285.17:01:22.51#ibcon#enter sib2, iclass 34, count 0 2006.285.17:01:22.51#ibcon#flushed, iclass 34, count 0 2006.285.17:01:22.51#ibcon#about to write, iclass 34, count 0 2006.285.17:01:22.51#ibcon#wrote, iclass 34, count 0 2006.285.17:01:22.51#ibcon#about to read 3, iclass 34, count 0 2006.285.17:01:22.55#ibcon#read 3, iclass 34, count 0 2006.285.17:01:22.55#ibcon#about to read 4, iclass 34, count 0 2006.285.17:01:22.55#ibcon#read 4, iclass 34, count 0 2006.285.17:01:22.55#ibcon#about to read 5, iclass 34, count 0 2006.285.17:01:22.55#ibcon#read 5, iclass 34, count 0 2006.285.17:01:22.55#ibcon#about to read 6, iclass 34, count 0 2006.285.17:01:22.55#ibcon#read 6, iclass 34, count 0 2006.285.17:01:22.55#ibcon#end of sib2, iclass 34, count 0 2006.285.17:01:22.55#ibcon#*after write, iclass 34, count 0 2006.285.17:01:22.55#ibcon#*before return 0, iclass 34, count 0 2006.285.17:01:22.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:01:22.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:01:22.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.17:01:22.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.17:01:22.55$vck44/va=8,3 2006.285.17:01:22.55#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.17:01:22.55#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.17:01:22.55#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:22.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:01:22.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:01:22.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:01:22.61#ibcon#enter wrdev, iclass 36, count 2 2006.285.17:01:22.61#ibcon#first serial, iclass 36, count 2 2006.285.17:01:22.61#ibcon#enter sib2, iclass 36, count 2 2006.285.17:01:22.61#ibcon#flushed, iclass 36, count 2 2006.285.17:01:22.61#ibcon#about to write, iclass 36, count 2 2006.285.17:01:22.61#ibcon#wrote, iclass 36, count 2 2006.285.17:01:22.61#ibcon#about to read 3, iclass 36, count 2 2006.285.17:01:22.63#ibcon#read 3, iclass 36, count 2 2006.285.17:01:22.63#ibcon#about to read 4, iclass 36, count 2 2006.285.17:01:22.63#ibcon#read 4, iclass 36, count 2 2006.285.17:01:22.63#ibcon#about to read 5, iclass 36, count 2 2006.285.17:01:22.63#ibcon#read 5, iclass 36, count 2 2006.285.17:01:22.63#ibcon#about to read 6, iclass 36, count 2 2006.285.17:01:22.63#ibcon#read 6, iclass 36, count 2 2006.285.17:01:22.63#ibcon#end of sib2, iclass 36, count 2 2006.285.17:01:22.63#ibcon#*mode == 0, iclass 36, count 2 2006.285.17:01:22.63#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.17:01:22.63#ibcon#[25=AT08-03\r\n] 2006.285.17:01:22.63#ibcon#*before write, iclass 36, count 2 2006.285.17:01:22.63#ibcon#enter sib2, iclass 36, count 2 2006.285.17:01:22.63#ibcon#flushed, iclass 36, count 2 2006.285.17:01:22.63#ibcon#about to write, iclass 36, count 2 2006.285.17:01:22.63#ibcon#wrote, iclass 36, count 2 2006.285.17:01:22.63#ibcon#about to read 3, iclass 36, count 2 2006.285.17:01:22.66#ibcon#read 3, iclass 36, count 2 2006.285.17:01:22.66#ibcon#about to read 4, iclass 36, count 2 2006.285.17:01:22.66#ibcon#read 4, iclass 36, count 2 2006.285.17:01:22.66#ibcon#about to read 5, iclass 36, count 2 2006.285.17:01:22.66#ibcon#read 5, iclass 36, count 2 2006.285.17:01:22.66#ibcon#about to read 6, iclass 36, count 2 2006.285.17:01:22.66#ibcon#read 6, iclass 36, count 2 2006.285.17:01:22.66#ibcon#end of sib2, iclass 36, count 2 2006.285.17:01:22.66#ibcon#*after write, iclass 36, count 2 2006.285.17:01:22.66#ibcon#*before return 0, iclass 36, count 2 2006.285.17:01:22.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:01:22.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:01:22.66#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.17:01:22.66#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:22.66#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:01:22.78#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:01:22.78#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:01:22.78#ibcon#enter wrdev, iclass 36, count 0 2006.285.17:01:22.78#ibcon#first serial, iclass 36, count 0 2006.285.17:01:22.78#ibcon#enter sib2, iclass 36, count 0 2006.285.17:01:22.78#ibcon#flushed, iclass 36, count 0 2006.285.17:01:22.78#ibcon#about to write, iclass 36, count 0 2006.285.17:01:22.78#ibcon#wrote, iclass 36, count 0 2006.285.17:01:22.78#ibcon#about to read 3, iclass 36, count 0 2006.285.17:01:22.80#ibcon#read 3, iclass 36, count 0 2006.285.17:01:22.80#ibcon#about to read 4, iclass 36, count 0 2006.285.17:01:22.80#ibcon#read 4, iclass 36, count 0 2006.285.17:01:22.80#ibcon#about to read 5, iclass 36, count 0 2006.285.17:01:22.80#ibcon#read 5, iclass 36, count 0 2006.285.17:01:22.80#ibcon#about to read 6, iclass 36, count 0 2006.285.17:01:22.80#ibcon#read 6, iclass 36, count 0 2006.285.17:01:22.80#ibcon#end of sib2, iclass 36, count 0 2006.285.17:01:22.80#ibcon#*mode == 0, iclass 36, count 0 2006.285.17:01:22.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.17:01:22.80#ibcon#[25=USB\r\n] 2006.285.17:01:22.80#ibcon#*before write, iclass 36, count 0 2006.285.17:01:22.80#ibcon#enter sib2, iclass 36, count 0 2006.285.17:01:22.80#ibcon#flushed, iclass 36, count 0 2006.285.17:01:22.80#ibcon#about to write, iclass 36, count 0 2006.285.17:01:22.80#ibcon#wrote, iclass 36, count 0 2006.285.17:01:22.80#ibcon#about to read 3, iclass 36, count 0 2006.285.17:01:22.83#ibcon#read 3, iclass 36, count 0 2006.285.17:01:22.83#ibcon#about to read 4, iclass 36, count 0 2006.285.17:01:22.83#ibcon#read 4, iclass 36, count 0 2006.285.17:01:22.83#ibcon#about to read 5, iclass 36, count 0 2006.285.17:01:22.83#ibcon#read 5, iclass 36, count 0 2006.285.17:01:22.83#ibcon#about to read 6, iclass 36, count 0 2006.285.17:01:22.83#ibcon#read 6, iclass 36, count 0 2006.285.17:01:22.83#ibcon#end of sib2, iclass 36, count 0 2006.285.17:01:22.83#ibcon#*after write, iclass 36, count 0 2006.285.17:01:22.83#ibcon#*before return 0, iclass 36, count 0 2006.285.17:01:22.83#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:01:22.83#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:01:22.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.17:01:22.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.17:01:22.83$vck44/vblo=1,629.99 2006.285.17:01:22.83#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.17:01:22.83#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.17:01:22.83#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:22.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:01:22.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:01:22.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:01:22.83#ibcon#enter wrdev, iclass 38, count 0 2006.285.17:01:22.83#ibcon#first serial, iclass 38, count 0 2006.285.17:01:22.83#ibcon#enter sib2, iclass 38, count 0 2006.285.17:01:22.83#ibcon#flushed, iclass 38, count 0 2006.285.17:01:22.83#ibcon#about to write, iclass 38, count 0 2006.285.17:01:22.83#ibcon#wrote, iclass 38, count 0 2006.285.17:01:22.83#ibcon#about to read 3, iclass 38, count 0 2006.285.17:01:22.85#ibcon#read 3, iclass 38, count 0 2006.285.17:01:23.21#ibcon#about to read 4, iclass 38, count 0 2006.285.17:01:23.21#ibcon#read 4, iclass 38, count 0 2006.285.17:01:23.21#ibcon#about to read 5, iclass 38, count 0 2006.285.17:01:23.21#ibcon#read 5, iclass 38, count 0 2006.285.17:01:23.21#ibcon#about to read 6, iclass 38, count 0 2006.285.17:01:23.21#ibcon#read 6, iclass 38, count 0 2006.285.17:01:23.21#ibcon#end of sib2, iclass 38, count 0 2006.285.17:01:23.21#ibcon#*mode == 0, iclass 38, count 0 2006.285.17:01:23.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.17:01:23.21#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.17:01:23.21#ibcon#*before write, iclass 38, count 0 2006.285.17:01:23.21#ibcon#enter sib2, iclass 38, count 0 2006.285.17:01:23.21#ibcon#flushed, iclass 38, count 0 2006.285.17:01:23.21#ibcon#about to write, iclass 38, count 0 2006.285.17:01:23.21#ibcon#wrote, iclass 38, count 0 2006.285.17:01:23.21#ibcon#about to read 3, iclass 38, count 0 2006.285.17:01:23.25#ibcon#read 3, iclass 38, count 0 2006.285.17:01:23.25#ibcon#about to read 4, iclass 38, count 0 2006.285.17:01:23.25#ibcon#read 4, iclass 38, count 0 2006.285.17:01:23.25#ibcon#about to read 5, iclass 38, count 0 2006.285.17:01:23.25#ibcon#read 5, iclass 38, count 0 2006.285.17:01:23.25#ibcon#about to read 6, iclass 38, count 0 2006.285.17:01:23.25#ibcon#read 6, iclass 38, count 0 2006.285.17:01:23.25#ibcon#end of sib2, iclass 38, count 0 2006.285.17:01:23.25#ibcon#*after write, iclass 38, count 0 2006.285.17:01:23.25#ibcon#*before return 0, iclass 38, count 0 2006.285.17:01:23.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:01:23.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:01:23.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.17:01:23.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.17:01:23.25$vck44/vb=1,4 2006.285.17:01:23.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.17:01:23.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.17:01:23.25#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:23.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:01:23.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:01:23.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:01:23.25#ibcon#enter wrdev, iclass 40, count 2 2006.285.17:01:23.25#ibcon#first serial, iclass 40, count 2 2006.285.17:01:23.25#ibcon#enter sib2, iclass 40, count 2 2006.285.17:01:23.25#ibcon#flushed, iclass 40, count 2 2006.285.17:01:23.25#ibcon#about to write, iclass 40, count 2 2006.285.17:01:23.25#ibcon#wrote, iclass 40, count 2 2006.285.17:01:23.25#ibcon#about to read 3, iclass 40, count 2 2006.285.17:01:23.27#ibcon#read 3, iclass 40, count 2 2006.285.17:01:23.27#ibcon#about to read 4, iclass 40, count 2 2006.285.17:01:23.27#ibcon#read 4, iclass 40, count 2 2006.285.17:01:23.27#ibcon#about to read 5, iclass 40, count 2 2006.285.17:01:23.27#ibcon#read 5, iclass 40, count 2 2006.285.17:01:23.27#ibcon#about to read 6, iclass 40, count 2 2006.285.17:01:23.27#ibcon#read 6, iclass 40, count 2 2006.285.17:01:23.27#ibcon#end of sib2, iclass 40, count 2 2006.285.17:01:23.27#ibcon#*mode == 0, iclass 40, count 2 2006.285.17:01:23.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.17:01:23.27#ibcon#[27=AT01-04\r\n] 2006.285.17:01:23.27#ibcon#*before write, iclass 40, count 2 2006.285.17:01:23.27#ibcon#enter sib2, iclass 40, count 2 2006.285.17:01:23.27#ibcon#flushed, iclass 40, count 2 2006.285.17:01:23.27#ibcon#about to write, iclass 40, count 2 2006.285.17:01:23.27#ibcon#wrote, iclass 40, count 2 2006.285.17:01:23.27#ibcon#about to read 3, iclass 40, count 2 2006.285.17:01:23.30#ibcon#read 3, iclass 40, count 2 2006.285.17:01:23.30#ibcon#about to read 4, iclass 40, count 2 2006.285.17:01:23.30#ibcon#read 4, iclass 40, count 2 2006.285.17:01:23.30#ibcon#about to read 5, iclass 40, count 2 2006.285.17:01:23.30#ibcon#read 5, iclass 40, count 2 2006.285.17:01:23.30#ibcon#about to read 6, iclass 40, count 2 2006.285.17:01:23.30#ibcon#read 6, iclass 40, count 2 2006.285.17:01:23.30#ibcon#end of sib2, iclass 40, count 2 2006.285.17:01:23.30#ibcon#*after write, iclass 40, count 2 2006.285.17:01:23.30#ibcon#*before return 0, iclass 40, count 2 2006.285.17:01:23.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:01:23.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:01:23.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.17:01:23.30#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:23.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:01:23.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:01:23.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:01:23.42#ibcon#enter wrdev, iclass 40, count 0 2006.285.17:01:23.42#ibcon#first serial, iclass 40, count 0 2006.285.17:01:23.42#ibcon#enter sib2, iclass 40, count 0 2006.285.17:01:23.42#ibcon#flushed, iclass 40, count 0 2006.285.17:01:23.42#ibcon#about to write, iclass 40, count 0 2006.285.17:01:23.42#ibcon#wrote, iclass 40, count 0 2006.285.17:01:23.42#ibcon#about to read 3, iclass 40, count 0 2006.285.17:01:23.44#ibcon#read 3, iclass 40, count 0 2006.285.17:01:23.44#ibcon#about to read 4, iclass 40, count 0 2006.285.17:01:23.44#ibcon#read 4, iclass 40, count 0 2006.285.17:01:23.44#ibcon#about to read 5, iclass 40, count 0 2006.285.17:01:23.44#ibcon#read 5, iclass 40, count 0 2006.285.17:01:23.44#ibcon#about to read 6, iclass 40, count 0 2006.285.17:01:23.44#ibcon#read 6, iclass 40, count 0 2006.285.17:01:23.44#ibcon#end of sib2, iclass 40, count 0 2006.285.17:01:23.44#ibcon#*mode == 0, iclass 40, count 0 2006.285.17:01:23.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.17:01:23.44#ibcon#[27=USB\r\n] 2006.285.17:01:23.44#ibcon#*before write, iclass 40, count 0 2006.285.17:01:23.44#ibcon#enter sib2, iclass 40, count 0 2006.285.17:01:23.44#ibcon#flushed, iclass 40, count 0 2006.285.17:01:23.44#ibcon#about to write, iclass 40, count 0 2006.285.17:01:23.44#ibcon#wrote, iclass 40, count 0 2006.285.17:01:23.44#ibcon#about to read 3, iclass 40, count 0 2006.285.17:01:23.47#ibcon#read 3, iclass 40, count 0 2006.285.17:01:23.47#ibcon#about to read 4, iclass 40, count 0 2006.285.17:01:23.47#ibcon#read 4, iclass 40, count 0 2006.285.17:01:23.47#ibcon#about to read 5, iclass 40, count 0 2006.285.17:01:23.47#ibcon#read 5, iclass 40, count 0 2006.285.17:01:23.47#ibcon#about to read 6, iclass 40, count 0 2006.285.17:01:23.47#ibcon#read 6, iclass 40, count 0 2006.285.17:01:23.47#ibcon#end of sib2, iclass 40, count 0 2006.285.17:01:23.47#ibcon#*after write, iclass 40, count 0 2006.285.17:01:23.47#ibcon#*before return 0, iclass 40, count 0 2006.285.17:01:23.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:01:23.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:01:23.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.17:01:23.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.17:01:23.47$vck44/vblo=2,634.99 2006.285.17:01:23.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.17:01:23.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.17:01:23.47#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:23.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:01:23.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:01:23.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:01:23.47#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:01:23.47#ibcon#first serial, iclass 4, count 0 2006.285.17:01:23.47#ibcon#enter sib2, iclass 4, count 0 2006.285.17:01:23.47#ibcon#flushed, iclass 4, count 0 2006.285.17:01:23.47#ibcon#about to write, iclass 4, count 0 2006.285.17:01:23.47#ibcon#wrote, iclass 4, count 0 2006.285.17:01:23.47#ibcon#about to read 3, iclass 4, count 0 2006.285.17:01:23.49#ibcon#read 3, iclass 4, count 0 2006.285.17:01:23.49#ibcon#about to read 4, iclass 4, count 0 2006.285.17:01:23.49#ibcon#read 4, iclass 4, count 0 2006.285.17:01:23.49#ibcon#about to read 5, iclass 4, count 0 2006.285.17:01:23.49#ibcon#read 5, iclass 4, count 0 2006.285.17:01:23.49#ibcon#about to read 6, iclass 4, count 0 2006.285.17:01:23.49#ibcon#read 6, iclass 4, count 0 2006.285.17:01:23.49#ibcon#end of sib2, iclass 4, count 0 2006.285.17:01:23.49#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:01:23.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:01:23.49#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.17:01:23.49#ibcon#*before write, iclass 4, count 0 2006.285.17:01:23.49#ibcon#enter sib2, iclass 4, count 0 2006.285.17:01:23.49#ibcon#flushed, iclass 4, count 0 2006.285.17:01:23.49#ibcon#about to write, iclass 4, count 0 2006.285.17:01:23.49#ibcon#wrote, iclass 4, count 0 2006.285.17:01:23.49#ibcon#about to read 3, iclass 4, count 0 2006.285.17:01:23.53#ibcon#read 3, iclass 4, count 0 2006.285.17:01:23.53#ibcon#about to read 4, iclass 4, count 0 2006.285.17:01:23.53#ibcon#read 4, iclass 4, count 0 2006.285.17:01:23.53#ibcon#about to read 5, iclass 4, count 0 2006.285.17:01:23.53#ibcon#read 5, iclass 4, count 0 2006.285.17:01:23.53#ibcon#about to read 6, iclass 4, count 0 2006.285.17:01:23.53#ibcon#read 6, iclass 4, count 0 2006.285.17:01:23.53#ibcon#end of sib2, iclass 4, count 0 2006.285.17:01:23.53#ibcon#*after write, iclass 4, count 0 2006.285.17:01:23.53#ibcon#*before return 0, iclass 4, count 0 2006.285.17:01:23.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:01:23.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:01:23.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:01:23.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:01:23.53$vck44/vb=2,5 2006.285.17:01:23.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.17:01:23.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.17:01:23.53#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:23.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:01:23.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:01:23.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:01:23.59#ibcon#enter wrdev, iclass 6, count 2 2006.285.17:01:23.59#ibcon#first serial, iclass 6, count 2 2006.285.17:01:23.59#ibcon#enter sib2, iclass 6, count 2 2006.285.17:01:23.59#ibcon#flushed, iclass 6, count 2 2006.285.17:01:23.59#ibcon#about to write, iclass 6, count 2 2006.285.17:01:23.59#ibcon#wrote, iclass 6, count 2 2006.285.17:01:23.59#ibcon#about to read 3, iclass 6, count 2 2006.285.17:01:23.61#ibcon#read 3, iclass 6, count 2 2006.285.17:01:23.61#ibcon#about to read 4, iclass 6, count 2 2006.285.17:01:23.61#ibcon#read 4, iclass 6, count 2 2006.285.17:01:23.61#ibcon#about to read 5, iclass 6, count 2 2006.285.17:01:23.61#ibcon#read 5, iclass 6, count 2 2006.285.17:01:23.61#ibcon#about to read 6, iclass 6, count 2 2006.285.17:01:23.61#ibcon#read 6, iclass 6, count 2 2006.285.17:01:23.61#ibcon#end of sib2, iclass 6, count 2 2006.285.17:01:23.61#ibcon#*mode == 0, iclass 6, count 2 2006.285.17:01:23.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.17:01:23.61#ibcon#[27=AT02-05\r\n] 2006.285.17:01:23.61#ibcon#*before write, iclass 6, count 2 2006.285.17:01:23.61#ibcon#enter sib2, iclass 6, count 2 2006.285.17:01:23.61#ibcon#flushed, iclass 6, count 2 2006.285.17:01:23.61#ibcon#about to write, iclass 6, count 2 2006.285.17:01:23.61#ibcon#wrote, iclass 6, count 2 2006.285.17:01:23.61#ibcon#about to read 3, iclass 6, count 2 2006.285.17:01:23.64#ibcon#read 3, iclass 6, count 2 2006.285.17:01:23.64#ibcon#about to read 4, iclass 6, count 2 2006.285.17:01:23.64#ibcon#read 4, iclass 6, count 2 2006.285.17:01:23.64#ibcon#about to read 5, iclass 6, count 2 2006.285.17:01:23.64#ibcon#read 5, iclass 6, count 2 2006.285.17:01:23.64#ibcon#about to read 6, iclass 6, count 2 2006.285.17:01:23.64#ibcon#read 6, iclass 6, count 2 2006.285.17:01:23.64#ibcon#end of sib2, iclass 6, count 2 2006.285.17:01:23.64#ibcon#*after write, iclass 6, count 2 2006.285.17:01:23.64#ibcon#*before return 0, iclass 6, count 2 2006.285.17:01:23.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:01:23.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:01:23.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.17:01:23.64#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:23.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:01:23.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:01:23.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:01:23.76#ibcon#enter wrdev, iclass 6, count 0 2006.285.17:01:23.76#ibcon#first serial, iclass 6, count 0 2006.285.17:01:23.76#ibcon#enter sib2, iclass 6, count 0 2006.285.17:01:23.76#ibcon#flushed, iclass 6, count 0 2006.285.17:01:23.76#ibcon#about to write, iclass 6, count 0 2006.285.17:01:23.76#ibcon#wrote, iclass 6, count 0 2006.285.17:01:23.76#ibcon#about to read 3, iclass 6, count 0 2006.285.17:01:23.78#ibcon#read 3, iclass 6, count 0 2006.285.17:01:23.78#ibcon#about to read 4, iclass 6, count 0 2006.285.17:01:23.78#ibcon#read 4, iclass 6, count 0 2006.285.17:01:23.78#ibcon#about to read 5, iclass 6, count 0 2006.285.17:01:23.78#ibcon#read 5, iclass 6, count 0 2006.285.17:01:23.78#ibcon#about to read 6, iclass 6, count 0 2006.285.17:01:23.78#ibcon#read 6, iclass 6, count 0 2006.285.17:01:23.78#ibcon#end of sib2, iclass 6, count 0 2006.285.17:01:23.78#ibcon#*mode == 0, iclass 6, count 0 2006.285.17:01:23.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.17:01:23.78#ibcon#[27=USB\r\n] 2006.285.17:01:23.78#ibcon#*before write, iclass 6, count 0 2006.285.17:01:23.78#ibcon#enter sib2, iclass 6, count 0 2006.285.17:01:23.78#ibcon#flushed, iclass 6, count 0 2006.285.17:01:23.78#ibcon#about to write, iclass 6, count 0 2006.285.17:01:23.78#ibcon#wrote, iclass 6, count 0 2006.285.17:01:23.78#ibcon#about to read 3, iclass 6, count 0 2006.285.17:01:23.81#ibcon#read 3, iclass 6, count 0 2006.285.17:01:23.81#ibcon#about to read 4, iclass 6, count 0 2006.285.17:01:23.81#ibcon#read 4, iclass 6, count 0 2006.285.17:01:23.81#ibcon#about to read 5, iclass 6, count 0 2006.285.17:01:23.81#ibcon#read 5, iclass 6, count 0 2006.285.17:01:23.81#ibcon#about to read 6, iclass 6, count 0 2006.285.17:01:23.81#ibcon#read 6, iclass 6, count 0 2006.285.17:01:23.81#ibcon#end of sib2, iclass 6, count 0 2006.285.17:01:23.81#ibcon#*after write, iclass 6, count 0 2006.285.17:01:23.81#ibcon#*before return 0, iclass 6, count 0 2006.285.17:01:23.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:01:23.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:01:23.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.17:01:23.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.17:01:23.81$vck44/vblo=3,649.99 2006.285.17:01:23.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.17:01:23.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.17:01:23.81#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:23.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:01:23.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:01:23.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:01:23.81#ibcon#enter wrdev, iclass 10, count 0 2006.285.17:01:23.81#ibcon#first serial, iclass 10, count 0 2006.285.17:01:23.81#ibcon#enter sib2, iclass 10, count 0 2006.285.17:01:23.81#ibcon#flushed, iclass 10, count 0 2006.285.17:01:23.81#ibcon#about to write, iclass 10, count 0 2006.285.17:01:23.81#ibcon#wrote, iclass 10, count 0 2006.285.17:01:23.95#ibcon#about to read 3, iclass 10, count 0 2006.285.17:01:23.95#ibcon#read 3, iclass 10, count 0 2006.285.17:01:23.95#ibcon#about to read 4, iclass 10, count 0 2006.285.17:01:23.95#ibcon#read 4, iclass 10, count 0 2006.285.17:01:23.95#ibcon#about to read 5, iclass 10, count 0 2006.285.17:01:23.95#ibcon#read 5, iclass 10, count 0 2006.285.17:01:23.95#ibcon#about to read 6, iclass 10, count 0 2006.285.17:01:23.95#ibcon#read 6, iclass 10, count 0 2006.285.17:01:23.95#ibcon#end of sib2, iclass 10, count 0 2006.285.17:01:23.95#ibcon#*mode == 0, iclass 10, count 0 2006.285.17:01:23.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.17:01:23.95#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.17:01:23.95#ibcon#*before write, iclass 10, count 0 2006.285.17:01:23.95#ibcon#enter sib2, iclass 10, count 0 2006.285.17:01:23.95#ibcon#flushed, iclass 10, count 0 2006.285.17:01:23.95#ibcon#about to write, iclass 10, count 0 2006.285.17:01:23.95#ibcon#wrote, iclass 10, count 0 2006.285.17:01:23.95#ibcon#about to read 3, iclass 10, count 0 2006.285.17:01:23.99#ibcon#read 3, iclass 10, count 0 2006.285.17:01:23.99#ibcon#about to read 4, iclass 10, count 0 2006.285.17:01:23.99#ibcon#read 4, iclass 10, count 0 2006.285.17:01:23.99#ibcon#about to read 5, iclass 10, count 0 2006.285.17:01:23.99#ibcon#read 5, iclass 10, count 0 2006.285.17:01:23.99#ibcon#about to read 6, iclass 10, count 0 2006.285.17:01:23.99#ibcon#read 6, iclass 10, count 0 2006.285.17:01:23.99#ibcon#end of sib2, iclass 10, count 0 2006.285.17:01:23.99#ibcon#*after write, iclass 10, count 0 2006.285.17:01:23.99#ibcon#*before return 0, iclass 10, count 0 2006.285.17:01:23.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:01:23.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:01:23.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.17:01:23.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.17:01:23.99$vck44/vb=3,4 2006.285.17:01:23.99#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.17:01:23.99#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.17:01:23.99#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:23.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:01:23.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:01:23.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:01:23.99#ibcon#enter wrdev, iclass 12, count 2 2006.285.17:01:23.99#ibcon#first serial, iclass 12, count 2 2006.285.17:01:23.99#ibcon#enter sib2, iclass 12, count 2 2006.285.17:01:23.99#ibcon#flushed, iclass 12, count 2 2006.285.17:01:23.99#ibcon#about to write, iclass 12, count 2 2006.285.17:01:23.99#ibcon#wrote, iclass 12, count 2 2006.285.17:01:23.99#ibcon#about to read 3, iclass 12, count 2 2006.285.17:01:24.01#ibcon#read 3, iclass 12, count 2 2006.285.17:01:24.01#ibcon#about to read 4, iclass 12, count 2 2006.285.17:01:24.01#ibcon#read 4, iclass 12, count 2 2006.285.17:01:24.01#ibcon#about to read 5, iclass 12, count 2 2006.285.17:01:24.01#ibcon#read 5, iclass 12, count 2 2006.285.17:01:24.01#ibcon#about to read 6, iclass 12, count 2 2006.285.17:01:24.01#ibcon#read 6, iclass 12, count 2 2006.285.17:01:24.01#ibcon#end of sib2, iclass 12, count 2 2006.285.17:01:24.01#ibcon#*mode == 0, iclass 12, count 2 2006.285.17:01:24.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.17:01:24.01#ibcon#[27=AT03-04\r\n] 2006.285.17:01:24.01#ibcon#*before write, iclass 12, count 2 2006.285.17:01:24.01#ibcon#enter sib2, iclass 12, count 2 2006.285.17:01:24.01#ibcon#flushed, iclass 12, count 2 2006.285.17:01:24.01#ibcon#about to write, iclass 12, count 2 2006.285.17:01:24.01#ibcon#wrote, iclass 12, count 2 2006.285.17:01:24.01#ibcon#about to read 3, iclass 12, count 2 2006.285.17:01:24.04#ibcon#read 3, iclass 12, count 2 2006.285.17:01:24.04#ibcon#about to read 4, iclass 12, count 2 2006.285.17:01:24.04#ibcon#read 4, iclass 12, count 2 2006.285.17:01:24.04#ibcon#about to read 5, iclass 12, count 2 2006.285.17:01:24.04#ibcon#read 5, iclass 12, count 2 2006.285.17:01:24.04#ibcon#about to read 6, iclass 12, count 2 2006.285.17:01:24.04#ibcon#read 6, iclass 12, count 2 2006.285.17:01:24.04#ibcon#end of sib2, iclass 12, count 2 2006.285.17:01:24.04#ibcon#*after write, iclass 12, count 2 2006.285.17:01:24.04#ibcon#*before return 0, iclass 12, count 2 2006.285.17:01:24.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:01:24.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:01:24.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.17:01:24.04#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:24.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:01:24.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:01:24.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:01:24.16#ibcon#enter wrdev, iclass 12, count 0 2006.285.17:01:24.16#ibcon#first serial, iclass 12, count 0 2006.285.17:01:24.16#ibcon#enter sib2, iclass 12, count 0 2006.285.17:01:24.16#ibcon#flushed, iclass 12, count 0 2006.285.17:01:24.16#ibcon#about to write, iclass 12, count 0 2006.285.17:01:24.16#ibcon#wrote, iclass 12, count 0 2006.285.17:01:24.16#ibcon#about to read 3, iclass 12, count 0 2006.285.17:01:24.18#ibcon#read 3, iclass 12, count 0 2006.285.17:01:24.18#ibcon#about to read 4, iclass 12, count 0 2006.285.17:01:24.18#ibcon#read 4, iclass 12, count 0 2006.285.17:01:24.18#ibcon#about to read 5, iclass 12, count 0 2006.285.17:01:24.18#ibcon#read 5, iclass 12, count 0 2006.285.17:01:24.18#ibcon#about to read 6, iclass 12, count 0 2006.285.17:01:24.18#ibcon#read 6, iclass 12, count 0 2006.285.17:01:24.18#ibcon#end of sib2, iclass 12, count 0 2006.285.17:01:24.18#ibcon#*mode == 0, iclass 12, count 0 2006.285.17:01:24.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.17:01:24.18#ibcon#[27=USB\r\n] 2006.285.17:01:24.18#ibcon#*before write, iclass 12, count 0 2006.285.17:01:24.18#ibcon#enter sib2, iclass 12, count 0 2006.285.17:01:24.18#ibcon#flushed, iclass 12, count 0 2006.285.17:01:24.18#ibcon#about to write, iclass 12, count 0 2006.285.17:01:24.18#ibcon#wrote, iclass 12, count 0 2006.285.17:01:24.18#ibcon#about to read 3, iclass 12, count 0 2006.285.17:01:24.21#ibcon#read 3, iclass 12, count 0 2006.285.17:01:24.21#ibcon#about to read 4, iclass 12, count 0 2006.285.17:01:24.21#ibcon#read 4, iclass 12, count 0 2006.285.17:01:24.21#ibcon#about to read 5, iclass 12, count 0 2006.285.17:01:24.21#ibcon#read 5, iclass 12, count 0 2006.285.17:01:24.21#ibcon#about to read 6, iclass 12, count 0 2006.285.17:01:24.21#ibcon#read 6, iclass 12, count 0 2006.285.17:01:24.21#ibcon#end of sib2, iclass 12, count 0 2006.285.17:01:24.21#ibcon#*after write, iclass 12, count 0 2006.285.17:01:24.21#ibcon#*before return 0, iclass 12, count 0 2006.285.17:01:24.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:01:24.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:01:24.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.17:01:24.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.17:01:24.21$vck44/vblo=4,679.99 2006.285.17:01:24.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.17:01:24.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.17:01:24.21#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:24.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:01:24.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:01:24.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:01:24.21#ibcon#enter wrdev, iclass 14, count 0 2006.285.17:01:24.21#ibcon#first serial, iclass 14, count 0 2006.285.17:01:24.21#ibcon#enter sib2, iclass 14, count 0 2006.285.17:01:24.21#ibcon#flushed, iclass 14, count 0 2006.285.17:01:24.21#ibcon#about to write, iclass 14, count 0 2006.285.17:01:24.21#ibcon#wrote, iclass 14, count 0 2006.285.17:01:24.21#ibcon#about to read 3, iclass 14, count 0 2006.285.17:01:24.23#ibcon#read 3, iclass 14, count 0 2006.285.17:01:24.23#ibcon#about to read 4, iclass 14, count 0 2006.285.17:01:24.23#ibcon#read 4, iclass 14, count 0 2006.285.17:01:24.23#ibcon#about to read 5, iclass 14, count 0 2006.285.17:01:24.23#ibcon#read 5, iclass 14, count 0 2006.285.17:01:24.23#ibcon#about to read 6, iclass 14, count 0 2006.285.17:01:24.23#ibcon#read 6, iclass 14, count 0 2006.285.17:01:24.23#ibcon#end of sib2, iclass 14, count 0 2006.285.17:01:24.23#ibcon#*mode == 0, iclass 14, count 0 2006.285.17:01:24.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.17:01:24.23#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.17:01:24.23#ibcon#*before write, iclass 14, count 0 2006.285.17:01:24.23#ibcon#enter sib2, iclass 14, count 0 2006.285.17:01:24.23#ibcon#flushed, iclass 14, count 0 2006.285.17:01:24.23#ibcon#about to write, iclass 14, count 0 2006.285.17:01:24.23#ibcon#wrote, iclass 14, count 0 2006.285.17:01:24.23#ibcon#about to read 3, iclass 14, count 0 2006.285.17:01:24.27#ibcon#read 3, iclass 14, count 0 2006.285.17:01:24.27#ibcon#about to read 4, iclass 14, count 0 2006.285.17:01:24.27#ibcon#read 4, iclass 14, count 0 2006.285.17:01:24.27#ibcon#about to read 5, iclass 14, count 0 2006.285.17:01:24.27#ibcon#read 5, iclass 14, count 0 2006.285.17:01:24.27#ibcon#about to read 6, iclass 14, count 0 2006.285.17:01:24.27#ibcon#read 6, iclass 14, count 0 2006.285.17:01:24.27#ibcon#end of sib2, iclass 14, count 0 2006.285.17:01:24.27#ibcon#*after write, iclass 14, count 0 2006.285.17:01:24.27#ibcon#*before return 0, iclass 14, count 0 2006.285.17:01:24.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:01:24.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:01:24.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.17:01:24.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.17:01:24.27$vck44/vb=4,5 2006.285.17:01:24.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.17:01:24.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.17:01:24.27#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:24.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:01:24.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:01:24.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:01:24.33#ibcon#enter wrdev, iclass 16, count 2 2006.285.17:01:24.33#ibcon#first serial, iclass 16, count 2 2006.285.17:01:24.33#ibcon#enter sib2, iclass 16, count 2 2006.285.17:01:24.33#ibcon#flushed, iclass 16, count 2 2006.285.17:01:24.33#ibcon#about to write, iclass 16, count 2 2006.285.17:01:24.33#ibcon#wrote, iclass 16, count 2 2006.285.17:01:24.33#ibcon#about to read 3, iclass 16, count 2 2006.285.17:01:24.35#ibcon#read 3, iclass 16, count 2 2006.285.17:01:24.35#ibcon#about to read 4, iclass 16, count 2 2006.285.17:01:24.35#ibcon#read 4, iclass 16, count 2 2006.285.17:01:24.35#ibcon#about to read 5, iclass 16, count 2 2006.285.17:01:24.35#ibcon#read 5, iclass 16, count 2 2006.285.17:01:24.35#ibcon#about to read 6, iclass 16, count 2 2006.285.17:01:24.35#ibcon#read 6, iclass 16, count 2 2006.285.17:01:24.35#ibcon#end of sib2, iclass 16, count 2 2006.285.17:01:24.35#ibcon#*mode == 0, iclass 16, count 2 2006.285.17:01:24.35#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.17:01:24.35#ibcon#[27=AT04-05\r\n] 2006.285.17:01:24.35#ibcon#*before write, iclass 16, count 2 2006.285.17:01:24.35#ibcon#enter sib2, iclass 16, count 2 2006.285.17:01:24.35#ibcon#flushed, iclass 16, count 2 2006.285.17:01:24.35#ibcon#about to write, iclass 16, count 2 2006.285.17:01:24.35#ibcon#wrote, iclass 16, count 2 2006.285.17:01:24.35#ibcon#about to read 3, iclass 16, count 2 2006.285.17:01:24.38#ibcon#read 3, iclass 16, count 2 2006.285.17:01:24.38#ibcon#about to read 4, iclass 16, count 2 2006.285.17:01:24.38#ibcon#read 4, iclass 16, count 2 2006.285.17:01:24.38#ibcon#about to read 5, iclass 16, count 2 2006.285.17:01:24.38#ibcon#read 5, iclass 16, count 2 2006.285.17:01:24.38#ibcon#about to read 6, iclass 16, count 2 2006.285.17:01:24.38#ibcon#read 6, iclass 16, count 2 2006.285.17:01:24.38#ibcon#end of sib2, iclass 16, count 2 2006.285.17:01:24.38#ibcon#*after write, iclass 16, count 2 2006.285.17:01:24.38#ibcon#*before return 0, iclass 16, count 2 2006.285.17:01:24.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:01:24.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:01:24.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.17:01:24.38#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:24.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:01:24.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:01:24.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:01:24.50#ibcon#enter wrdev, iclass 16, count 0 2006.285.17:01:24.50#ibcon#first serial, iclass 16, count 0 2006.285.17:01:24.50#ibcon#enter sib2, iclass 16, count 0 2006.285.17:01:24.50#ibcon#flushed, iclass 16, count 0 2006.285.17:01:24.50#ibcon#about to write, iclass 16, count 0 2006.285.17:01:24.50#ibcon#wrote, iclass 16, count 0 2006.285.17:01:24.50#ibcon#about to read 3, iclass 16, count 0 2006.285.17:01:24.52#ibcon#read 3, iclass 16, count 0 2006.285.17:01:24.52#ibcon#about to read 4, iclass 16, count 0 2006.285.17:01:24.52#ibcon#read 4, iclass 16, count 0 2006.285.17:01:24.52#ibcon#about to read 5, iclass 16, count 0 2006.285.17:01:24.52#ibcon#read 5, iclass 16, count 0 2006.285.17:01:24.52#ibcon#about to read 6, iclass 16, count 0 2006.285.17:01:24.52#ibcon#read 6, iclass 16, count 0 2006.285.17:01:24.52#ibcon#end of sib2, iclass 16, count 0 2006.285.17:01:24.52#ibcon#*mode == 0, iclass 16, count 0 2006.285.17:01:24.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.17:01:24.52#ibcon#[27=USB\r\n] 2006.285.17:01:24.52#ibcon#*before write, iclass 16, count 0 2006.285.17:01:24.52#ibcon#enter sib2, iclass 16, count 0 2006.285.17:01:24.52#ibcon#flushed, iclass 16, count 0 2006.285.17:01:24.52#ibcon#about to write, iclass 16, count 0 2006.285.17:01:24.52#ibcon#wrote, iclass 16, count 0 2006.285.17:01:24.52#ibcon#about to read 3, iclass 16, count 0 2006.285.17:01:24.55#ibcon#read 3, iclass 16, count 0 2006.285.17:01:24.55#ibcon#about to read 4, iclass 16, count 0 2006.285.17:01:24.55#ibcon#read 4, iclass 16, count 0 2006.285.17:01:24.55#ibcon#about to read 5, iclass 16, count 0 2006.285.17:01:24.55#ibcon#read 5, iclass 16, count 0 2006.285.17:01:24.55#ibcon#about to read 6, iclass 16, count 0 2006.285.17:01:24.55#ibcon#read 6, iclass 16, count 0 2006.285.17:01:24.55#ibcon#end of sib2, iclass 16, count 0 2006.285.17:01:24.55#ibcon#*after write, iclass 16, count 0 2006.285.17:01:24.55#ibcon#*before return 0, iclass 16, count 0 2006.285.17:01:24.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:01:24.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:01:24.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.17:01:24.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.17:01:24.55$vck44/vblo=5,709.99 2006.285.17:01:24.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.17:01:24.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.17:01:24.55#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:24.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:01:24.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:01:24.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:01:24.55#ibcon#enter wrdev, iclass 18, count 0 2006.285.17:01:24.55#ibcon#first serial, iclass 18, count 0 2006.285.17:01:24.55#ibcon#enter sib2, iclass 18, count 0 2006.285.17:01:24.55#ibcon#flushed, iclass 18, count 0 2006.285.17:01:24.55#ibcon#about to write, iclass 18, count 0 2006.285.17:01:24.55#ibcon#wrote, iclass 18, count 0 2006.285.17:01:24.55#ibcon#about to read 3, iclass 18, count 0 2006.285.17:01:24.57#ibcon#read 3, iclass 18, count 0 2006.285.17:01:24.57#ibcon#about to read 4, iclass 18, count 0 2006.285.17:01:24.57#ibcon#read 4, iclass 18, count 0 2006.285.17:01:24.57#ibcon#about to read 5, iclass 18, count 0 2006.285.17:01:24.57#ibcon#read 5, iclass 18, count 0 2006.285.17:01:24.57#ibcon#about to read 6, iclass 18, count 0 2006.285.17:01:24.57#ibcon#read 6, iclass 18, count 0 2006.285.17:01:24.57#ibcon#end of sib2, iclass 18, count 0 2006.285.17:01:24.57#ibcon#*mode == 0, iclass 18, count 0 2006.285.17:01:24.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.17:01:24.57#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.17:01:24.57#ibcon#*before write, iclass 18, count 0 2006.285.17:01:24.57#ibcon#enter sib2, iclass 18, count 0 2006.285.17:01:24.57#ibcon#flushed, iclass 18, count 0 2006.285.17:01:24.57#ibcon#about to write, iclass 18, count 0 2006.285.17:01:24.57#ibcon#wrote, iclass 18, count 0 2006.285.17:01:24.57#ibcon#about to read 3, iclass 18, count 0 2006.285.17:01:24.61#ibcon#read 3, iclass 18, count 0 2006.285.17:01:24.61#ibcon#about to read 4, iclass 18, count 0 2006.285.17:01:24.61#ibcon#read 4, iclass 18, count 0 2006.285.17:01:24.61#ibcon#about to read 5, iclass 18, count 0 2006.285.17:01:24.61#ibcon#read 5, iclass 18, count 0 2006.285.17:01:24.61#ibcon#about to read 6, iclass 18, count 0 2006.285.17:01:24.61#ibcon#read 6, iclass 18, count 0 2006.285.17:01:24.61#ibcon#end of sib2, iclass 18, count 0 2006.285.17:01:24.61#ibcon#*after write, iclass 18, count 0 2006.285.17:01:24.61#ibcon#*before return 0, iclass 18, count 0 2006.285.17:01:24.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:01:24.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:01:24.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.17:01:24.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.17:01:24.61$vck44/vb=5,4 2006.285.17:01:24.61#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.17:01:24.61#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.17:01:24.61#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:24.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:01:24.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:01:24.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:01:24.67#ibcon#enter wrdev, iclass 20, count 2 2006.285.17:01:24.67#ibcon#first serial, iclass 20, count 2 2006.285.17:01:24.67#ibcon#enter sib2, iclass 20, count 2 2006.285.17:01:24.67#ibcon#flushed, iclass 20, count 2 2006.285.17:01:24.67#ibcon#about to write, iclass 20, count 2 2006.285.17:01:24.67#ibcon#wrote, iclass 20, count 2 2006.285.17:01:24.67#ibcon#about to read 3, iclass 20, count 2 2006.285.17:01:24.69#ibcon#read 3, iclass 20, count 2 2006.285.17:01:24.69#ibcon#about to read 4, iclass 20, count 2 2006.285.17:01:24.69#ibcon#read 4, iclass 20, count 2 2006.285.17:01:24.69#ibcon#about to read 5, iclass 20, count 2 2006.285.17:01:24.69#ibcon#read 5, iclass 20, count 2 2006.285.17:01:24.69#ibcon#about to read 6, iclass 20, count 2 2006.285.17:01:24.69#ibcon#read 6, iclass 20, count 2 2006.285.17:01:24.69#ibcon#end of sib2, iclass 20, count 2 2006.285.17:01:24.69#ibcon#*mode == 0, iclass 20, count 2 2006.285.17:01:24.69#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.17:01:24.69#ibcon#[27=AT05-04\r\n] 2006.285.17:01:24.69#ibcon#*before write, iclass 20, count 2 2006.285.17:01:24.69#ibcon#enter sib2, iclass 20, count 2 2006.285.17:01:24.69#ibcon#flushed, iclass 20, count 2 2006.285.17:01:24.69#ibcon#about to write, iclass 20, count 2 2006.285.17:01:24.69#ibcon#wrote, iclass 20, count 2 2006.285.17:01:24.69#ibcon#about to read 3, iclass 20, count 2 2006.285.17:01:24.72#ibcon#read 3, iclass 20, count 2 2006.285.17:01:24.72#ibcon#about to read 4, iclass 20, count 2 2006.285.17:01:24.72#ibcon#read 4, iclass 20, count 2 2006.285.17:01:24.72#ibcon#about to read 5, iclass 20, count 2 2006.285.17:01:24.72#ibcon#read 5, iclass 20, count 2 2006.285.17:01:24.72#ibcon#about to read 6, iclass 20, count 2 2006.285.17:01:24.72#ibcon#read 6, iclass 20, count 2 2006.285.17:01:24.72#ibcon#end of sib2, iclass 20, count 2 2006.285.17:01:24.72#ibcon#*after write, iclass 20, count 2 2006.285.17:01:24.72#ibcon#*before return 0, iclass 20, count 2 2006.285.17:01:24.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:01:24.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:01:24.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.17:01:24.72#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:24.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:01:24.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:01:24.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:01:24.84#ibcon#enter wrdev, iclass 20, count 0 2006.285.17:01:24.84#ibcon#first serial, iclass 20, count 0 2006.285.17:01:24.84#ibcon#enter sib2, iclass 20, count 0 2006.285.17:01:24.84#ibcon#flushed, iclass 20, count 0 2006.285.17:01:24.84#ibcon#about to write, iclass 20, count 0 2006.285.17:01:24.84#ibcon#wrote, iclass 20, count 0 2006.285.17:01:24.84#ibcon#about to read 3, iclass 20, count 0 2006.285.17:01:24.86#ibcon#read 3, iclass 20, count 0 2006.285.17:01:24.86#ibcon#about to read 4, iclass 20, count 0 2006.285.17:01:24.86#ibcon#read 4, iclass 20, count 0 2006.285.17:01:24.86#ibcon#about to read 5, iclass 20, count 0 2006.285.17:01:24.86#ibcon#read 5, iclass 20, count 0 2006.285.17:01:24.86#ibcon#about to read 6, iclass 20, count 0 2006.285.17:01:24.86#ibcon#read 6, iclass 20, count 0 2006.285.17:01:24.86#ibcon#end of sib2, iclass 20, count 0 2006.285.17:01:24.86#ibcon#*mode == 0, iclass 20, count 0 2006.285.17:01:24.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.17:01:24.86#ibcon#[27=USB\r\n] 2006.285.17:01:24.86#ibcon#*before write, iclass 20, count 0 2006.285.17:01:24.86#ibcon#enter sib2, iclass 20, count 0 2006.285.17:01:24.86#ibcon#flushed, iclass 20, count 0 2006.285.17:01:24.86#ibcon#about to write, iclass 20, count 0 2006.285.17:01:24.86#ibcon#wrote, iclass 20, count 0 2006.285.17:01:24.86#ibcon#about to read 3, iclass 20, count 0 2006.285.17:01:24.89#ibcon#read 3, iclass 20, count 0 2006.285.17:01:24.89#ibcon#about to read 4, iclass 20, count 0 2006.285.17:01:24.89#ibcon#read 4, iclass 20, count 0 2006.285.17:01:24.89#ibcon#about to read 5, iclass 20, count 0 2006.285.17:01:24.89#ibcon#read 5, iclass 20, count 0 2006.285.17:01:24.89#ibcon#about to read 6, iclass 20, count 0 2006.285.17:01:24.89#ibcon#read 6, iclass 20, count 0 2006.285.17:01:24.89#ibcon#end of sib2, iclass 20, count 0 2006.285.17:01:24.89#ibcon#*after write, iclass 20, count 0 2006.285.17:01:24.89#ibcon#*before return 0, iclass 20, count 0 2006.285.17:01:24.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:01:24.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:01:24.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.17:01:24.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.17:01:24.89$vck44/vblo=6,719.99 2006.285.17:01:24.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.17:01:24.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.17:01:24.89#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:24.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:01:24.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:01:24.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:01:24.89#ibcon#enter wrdev, iclass 22, count 0 2006.285.17:01:24.89#ibcon#first serial, iclass 22, count 0 2006.285.17:01:24.89#ibcon#enter sib2, iclass 22, count 0 2006.285.17:01:24.89#ibcon#flushed, iclass 22, count 0 2006.285.17:01:25.03#ibcon#about to write, iclass 22, count 0 2006.285.17:01:25.03#ibcon#wrote, iclass 22, count 0 2006.285.17:01:25.03#ibcon#about to read 3, iclass 22, count 0 2006.285.17:01:25.05#ibcon#read 3, iclass 22, count 0 2006.285.17:01:25.05#ibcon#about to read 4, iclass 22, count 0 2006.285.17:01:25.05#ibcon#read 4, iclass 22, count 0 2006.285.17:01:25.05#ibcon#about to read 5, iclass 22, count 0 2006.285.17:01:25.05#ibcon#read 5, iclass 22, count 0 2006.285.17:01:25.05#ibcon#about to read 6, iclass 22, count 0 2006.285.17:01:25.05#ibcon#read 6, iclass 22, count 0 2006.285.17:01:25.05#ibcon#end of sib2, iclass 22, count 0 2006.285.17:01:25.05#ibcon#*mode == 0, iclass 22, count 0 2006.285.17:01:25.05#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.17:01:25.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.17:01:25.05#ibcon#*before write, iclass 22, count 0 2006.285.17:01:25.05#ibcon#enter sib2, iclass 22, count 0 2006.285.17:01:25.05#ibcon#flushed, iclass 22, count 0 2006.285.17:01:25.05#ibcon#about to write, iclass 22, count 0 2006.285.17:01:25.05#ibcon#wrote, iclass 22, count 0 2006.285.17:01:25.05#ibcon#about to read 3, iclass 22, count 0 2006.285.17:01:25.09#ibcon#read 3, iclass 22, count 0 2006.285.17:01:25.09#ibcon#about to read 4, iclass 22, count 0 2006.285.17:01:25.09#ibcon#read 4, iclass 22, count 0 2006.285.17:01:25.09#ibcon#about to read 5, iclass 22, count 0 2006.285.17:01:25.09#ibcon#read 5, iclass 22, count 0 2006.285.17:01:25.09#ibcon#about to read 6, iclass 22, count 0 2006.285.17:01:25.09#ibcon#read 6, iclass 22, count 0 2006.285.17:01:25.09#ibcon#end of sib2, iclass 22, count 0 2006.285.17:01:25.09#ibcon#*after write, iclass 22, count 0 2006.285.17:01:25.09#ibcon#*before return 0, iclass 22, count 0 2006.285.17:01:25.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:01:25.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:01:25.09#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.17:01:25.09#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.17:01:25.09$vck44/vb=6,3 2006.285.17:01:25.09#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.17:01:25.09#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.17:01:25.09#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:25.09#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:01:25.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:01:25.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:01:25.09#ibcon#enter wrdev, iclass 24, count 2 2006.285.17:01:25.09#ibcon#first serial, iclass 24, count 2 2006.285.17:01:25.09#ibcon#enter sib2, iclass 24, count 2 2006.285.17:01:25.09#ibcon#flushed, iclass 24, count 2 2006.285.17:01:25.09#ibcon#about to write, iclass 24, count 2 2006.285.17:01:25.09#ibcon#wrote, iclass 24, count 2 2006.285.17:01:25.09#ibcon#about to read 3, iclass 24, count 2 2006.285.17:01:25.11#ibcon#read 3, iclass 24, count 2 2006.285.17:01:25.11#ibcon#about to read 4, iclass 24, count 2 2006.285.17:01:25.11#ibcon#read 4, iclass 24, count 2 2006.285.17:01:25.11#ibcon#about to read 5, iclass 24, count 2 2006.285.17:01:25.11#ibcon#read 5, iclass 24, count 2 2006.285.17:01:25.11#ibcon#about to read 6, iclass 24, count 2 2006.285.17:01:25.11#ibcon#read 6, iclass 24, count 2 2006.285.17:01:25.11#ibcon#end of sib2, iclass 24, count 2 2006.285.17:01:25.11#ibcon#*mode == 0, iclass 24, count 2 2006.285.17:01:25.11#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.17:01:25.11#ibcon#[27=AT06-03\r\n] 2006.285.17:01:25.11#ibcon#*before write, iclass 24, count 2 2006.285.17:01:25.11#ibcon#enter sib2, iclass 24, count 2 2006.285.17:01:25.11#ibcon#flushed, iclass 24, count 2 2006.285.17:01:25.11#ibcon#about to write, iclass 24, count 2 2006.285.17:01:25.11#ibcon#wrote, iclass 24, count 2 2006.285.17:01:25.11#ibcon#about to read 3, iclass 24, count 2 2006.285.17:01:25.14#ibcon#read 3, iclass 24, count 2 2006.285.17:01:25.14#ibcon#about to read 4, iclass 24, count 2 2006.285.17:01:25.14#ibcon#read 4, iclass 24, count 2 2006.285.17:01:25.14#ibcon#about to read 5, iclass 24, count 2 2006.285.17:01:25.14#ibcon#read 5, iclass 24, count 2 2006.285.17:01:25.14#ibcon#about to read 6, iclass 24, count 2 2006.285.17:01:25.14#ibcon#read 6, iclass 24, count 2 2006.285.17:01:25.14#ibcon#end of sib2, iclass 24, count 2 2006.285.17:01:25.14#ibcon#*after write, iclass 24, count 2 2006.285.17:01:25.14#ibcon#*before return 0, iclass 24, count 2 2006.285.17:01:25.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:01:25.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:01:25.14#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.17:01:25.14#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:25.14#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:01:25.26#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:01:25.26#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:01:25.26#ibcon#enter wrdev, iclass 24, count 0 2006.285.17:01:25.26#ibcon#first serial, iclass 24, count 0 2006.285.17:01:25.26#ibcon#enter sib2, iclass 24, count 0 2006.285.17:01:25.26#ibcon#flushed, iclass 24, count 0 2006.285.17:01:25.26#ibcon#about to write, iclass 24, count 0 2006.285.17:01:25.26#ibcon#wrote, iclass 24, count 0 2006.285.17:01:25.26#ibcon#about to read 3, iclass 24, count 0 2006.285.17:01:25.28#ibcon#read 3, iclass 24, count 0 2006.285.17:01:25.28#ibcon#about to read 4, iclass 24, count 0 2006.285.17:01:25.28#ibcon#read 4, iclass 24, count 0 2006.285.17:01:25.28#ibcon#about to read 5, iclass 24, count 0 2006.285.17:01:25.28#ibcon#read 5, iclass 24, count 0 2006.285.17:01:25.28#ibcon#about to read 6, iclass 24, count 0 2006.285.17:01:25.28#ibcon#read 6, iclass 24, count 0 2006.285.17:01:25.28#ibcon#end of sib2, iclass 24, count 0 2006.285.17:01:25.28#ibcon#*mode == 0, iclass 24, count 0 2006.285.17:01:25.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.17:01:25.28#ibcon#[27=USB\r\n] 2006.285.17:01:25.28#ibcon#*before write, iclass 24, count 0 2006.285.17:01:25.28#ibcon#enter sib2, iclass 24, count 0 2006.285.17:01:25.28#ibcon#flushed, iclass 24, count 0 2006.285.17:01:25.28#ibcon#about to write, iclass 24, count 0 2006.285.17:01:25.28#ibcon#wrote, iclass 24, count 0 2006.285.17:01:25.28#ibcon#about to read 3, iclass 24, count 0 2006.285.17:01:25.31#ibcon#read 3, iclass 24, count 0 2006.285.17:01:25.31#ibcon#about to read 4, iclass 24, count 0 2006.285.17:01:25.31#ibcon#read 4, iclass 24, count 0 2006.285.17:01:25.31#ibcon#about to read 5, iclass 24, count 0 2006.285.17:01:25.31#ibcon#read 5, iclass 24, count 0 2006.285.17:01:25.31#ibcon#about to read 6, iclass 24, count 0 2006.285.17:01:25.31#ibcon#read 6, iclass 24, count 0 2006.285.17:01:25.31#ibcon#end of sib2, iclass 24, count 0 2006.285.17:01:25.31#ibcon#*after write, iclass 24, count 0 2006.285.17:01:25.31#ibcon#*before return 0, iclass 24, count 0 2006.285.17:01:25.31#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:01:25.31#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:01:25.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.17:01:25.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.17:01:25.31$vck44/vblo=7,734.99 2006.285.17:01:25.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.17:01:25.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.17:01:25.31#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:25.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:01:25.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:01:25.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:01:25.31#ibcon#enter wrdev, iclass 26, count 0 2006.285.17:01:25.31#ibcon#first serial, iclass 26, count 0 2006.285.17:01:25.31#ibcon#enter sib2, iclass 26, count 0 2006.285.17:01:25.31#ibcon#flushed, iclass 26, count 0 2006.285.17:01:25.31#ibcon#about to write, iclass 26, count 0 2006.285.17:01:25.31#ibcon#wrote, iclass 26, count 0 2006.285.17:01:25.31#ibcon#about to read 3, iclass 26, count 0 2006.285.17:01:25.33#ibcon#read 3, iclass 26, count 0 2006.285.17:01:25.33#ibcon#about to read 4, iclass 26, count 0 2006.285.17:01:25.33#ibcon#read 4, iclass 26, count 0 2006.285.17:01:25.33#ibcon#about to read 5, iclass 26, count 0 2006.285.17:01:25.33#ibcon#read 5, iclass 26, count 0 2006.285.17:01:25.33#ibcon#about to read 6, iclass 26, count 0 2006.285.17:01:25.33#ibcon#read 6, iclass 26, count 0 2006.285.17:01:25.33#ibcon#end of sib2, iclass 26, count 0 2006.285.17:01:25.33#ibcon#*mode == 0, iclass 26, count 0 2006.285.17:01:25.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.17:01:25.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.17:01:25.33#ibcon#*before write, iclass 26, count 0 2006.285.17:01:25.33#ibcon#enter sib2, iclass 26, count 0 2006.285.17:01:25.33#ibcon#flushed, iclass 26, count 0 2006.285.17:01:25.33#ibcon#about to write, iclass 26, count 0 2006.285.17:01:25.33#ibcon#wrote, iclass 26, count 0 2006.285.17:01:25.33#ibcon#about to read 3, iclass 26, count 0 2006.285.17:01:25.37#ibcon#read 3, iclass 26, count 0 2006.285.17:01:25.37#ibcon#about to read 4, iclass 26, count 0 2006.285.17:01:25.37#ibcon#read 4, iclass 26, count 0 2006.285.17:01:25.37#ibcon#about to read 5, iclass 26, count 0 2006.285.17:01:25.37#ibcon#read 5, iclass 26, count 0 2006.285.17:01:25.37#ibcon#about to read 6, iclass 26, count 0 2006.285.17:01:25.37#ibcon#read 6, iclass 26, count 0 2006.285.17:01:25.37#ibcon#end of sib2, iclass 26, count 0 2006.285.17:01:25.37#ibcon#*after write, iclass 26, count 0 2006.285.17:01:25.37#ibcon#*before return 0, iclass 26, count 0 2006.285.17:01:25.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:01:25.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:01:25.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.17:01:25.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.17:01:25.37$vck44/vb=7,4 2006.285.17:01:25.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.17:01:25.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.17:01:25.37#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:25.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:01:25.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:01:25.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:01:25.43#ibcon#enter wrdev, iclass 28, count 2 2006.285.17:01:25.43#ibcon#first serial, iclass 28, count 2 2006.285.17:01:25.43#ibcon#enter sib2, iclass 28, count 2 2006.285.17:01:25.43#ibcon#flushed, iclass 28, count 2 2006.285.17:01:25.43#ibcon#about to write, iclass 28, count 2 2006.285.17:01:25.43#ibcon#wrote, iclass 28, count 2 2006.285.17:01:25.43#ibcon#about to read 3, iclass 28, count 2 2006.285.17:01:25.45#ibcon#read 3, iclass 28, count 2 2006.285.17:01:25.45#ibcon#about to read 4, iclass 28, count 2 2006.285.17:01:25.45#ibcon#read 4, iclass 28, count 2 2006.285.17:01:25.45#ibcon#about to read 5, iclass 28, count 2 2006.285.17:01:25.45#ibcon#read 5, iclass 28, count 2 2006.285.17:01:25.45#ibcon#about to read 6, iclass 28, count 2 2006.285.17:01:25.45#ibcon#read 6, iclass 28, count 2 2006.285.17:01:25.45#ibcon#end of sib2, iclass 28, count 2 2006.285.17:01:25.45#ibcon#*mode == 0, iclass 28, count 2 2006.285.17:01:25.45#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.17:01:25.45#ibcon#[27=AT07-04\r\n] 2006.285.17:01:25.45#ibcon#*before write, iclass 28, count 2 2006.285.17:01:25.45#ibcon#enter sib2, iclass 28, count 2 2006.285.17:01:25.45#ibcon#flushed, iclass 28, count 2 2006.285.17:01:25.45#ibcon#about to write, iclass 28, count 2 2006.285.17:01:25.45#ibcon#wrote, iclass 28, count 2 2006.285.17:01:25.45#ibcon#about to read 3, iclass 28, count 2 2006.285.17:01:25.48#ibcon#read 3, iclass 28, count 2 2006.285.17:01:25.48#ibcon#about to read 4, iclass 28, count 2 2006.285.17:01:25.48#ibcon#read 4, iclass 28, count 2 2006.285.17:01:25.48#ibcon#about to read 5, iclass 28, count 2 2006.285.17:01:25.48#ibcon#read 5, iclass 28, count 2 2006.285.17:01:25.48#ibcon#about to read 6, iclass 28, count 2 2006.285.17:01:25.48#ibcon#read 6, iclass 28, count 2 2006.285.17:01:25.48#ibcon#end of sib2, iclass 28, count 2 2006.285.17:01:25.48#ibcon#*after write, iclass 28, count 2 2006.285.17:01:25.48#ibcon#*before return 0, iclass 28, count 2 2006.285.17:01:25.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:01:25.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:01:25.48#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.17:01:25.48#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:25.48#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:01:25.60#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:01:25.60#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:01:25.60#ibcon#enter wrdev, iclass 28, count 0 2006.285.17:01:25.60#ibcon#first serial, iclass 28, count 0 2006.285.17:01:25.60#ibcon#enter sib2, iclass 28, count 0 2006.285.17:01:25.60#ibcon#flushed, iclass 28, count 0 2006.285.17:01:25.60#ibcon#about to write, iclass 28, count 0 2006.285.17:01:25.60#ibcon#wrote, iclass 28, count 0 2006.285.17:01:25.60#ibcon#about to read 3, iclass 28, count 0 2006.285.17:01:25.62#ibcon#read 3, iclass 28, count 0 2006.285.17:01:25.62#ibcon#about to read 4, iclass 28, count 0 2006.285.17:01:25.62#ibcon#read 4, iclass 28, count 0 2006.285.17:01:25.62#ibcon#about to read 5, iclass 28, count 0 2006.285.17:01:25.62#ibcon#read 5, iclass 28, count 0 2006.285.17:01:25.62#ibcon#about to read 6, iclass 28, count 0 2006.285.17:01:25.62#ibcon#read 6, iclass 28, count 0 2006.285.17:01:25.62#ibcon#end of sib2, iclass 28, count 0 2006.285.17:01:25.62#ibcon#*mode == 0, iclass 28, count 0 2006.285.17:01:25.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.17:01:25.62#ibcon#[27=USB\r\n] 2006.285.17:01:25.62#ibcon#*before write, iclass 28, count 0 2006.285.17:01:25.62#ibcon#enter sib2, iclass 28, count 0 2006.285.17:01:25.62#ibcon#flushed, iclass 28, count 0 2006.285.17:01:25.62#ibcon#about to write, iclass 28, count 0 2006.285.17:01:25.62#ibcon#wrote, iclass 28, count 0 2006.285.17:01:25.62#ibcon#about to read 3, iclass 28, count 0 2006.285.17:01:25.65#ibcon#read 3, iclass 28, count 0 2006.285.17:01:25.65#ibcon#about to read 4, iclass 28, count 0 2006.285.17:01:25.65#ibcon#read 4, iclass 28, count 0 2006.285.17:01:25.65#ibcon#about to read 5, iclass 28, count 0 2006.285.17:01:25.65#ibcon#read 5, iclass 28, count 0 2006.285.17:01:25.65#ibcon#about to read 6, iclass 28, count 0 2006.285.17:01:25.65#ibcon#read 6, iclass 28, count 0 2006.285.17:01:25.65#ibcon#end of sib2, iclass 28, count 0 2006.285.17:01:25.65#ibcon#*after write, iclass 28, count 0 2006.285.17:01:25.65#ibcon#*before return 0, iclass 28, count 0 2006.285.17:01:25.65#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:01:25.65#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:01:25.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.17:01:25.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.17:01:25.65$vck44/vblo=8,744.99 2006.285.17:01:25.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.17:01:25.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.17:01:25.65#ibcon#ireg 17 cls_cnt 0 2006.285.17:01:25.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:01:25.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:01:25.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:01:25.65#ibcon#enter wrdev, iclass 30, count 0 2006.285.17:01:25.65#ibcon#first serial, iclass 30, count 0 2006.285.17:01:25.65#ibcon#enter sib2, iclass 30, count 0 2006.285.17:01:25.65#ibcon#flushed, iclass 30, count 0 2006.285.17:01:25.65#ibcon#about to write, iclass 30, count 0 2006.285.17:01:25.65#ibcon#wrote, iclass 30, count 0 2006.285.17:01:25.65#ibcon#about to read 3, iclass 30, count 0 2006.285.17:01:25.67#ibcon#read 3, iclass 30, count 0 2006.285.17:01:25.67#ibcon#about to read 4, iclass 30, count 0 2006.285.17:01:25.67#ibcon#read 4, iclass 30, count 0 2006.285.17:01:25.67#ibcon#about to read 5, iclass 30, count 0 2006.285.17:01:25.67#ibcon#read 5, iclass 30, count 0 2006.285.17:01:25.67#ibcon#about to read 6, iclass 30, count 0 2006.285.17:01:25.67#ibcon#read 6, iclass 30, count 0 2006.285.17:01:25.67#ibcon#end of sib2, iclass 30, count 0 2006.285.17:01:25.67#ibcon#*mode == 0, iclass 30, count 0 2006.285.17:01:25.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.17:01:25.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.17:01:25.67#ibcon#*before write, iclass 30, count 0 2006.285.17:01:25.67#ibcon#enter sib2, iclass 30, count 0 2006.285.17:01:25.67#ibcon#flushed, iclass 30, count 0 2006.285.17:01:25.67#ibcon#about to write, iclass 30, count 0 2006.285.17:01:25.67#ibcon#wrote, iclass 30, count 0 2006.285.17:01:25.67#ibcon#about to read 3, iclass 30, count 0 2006.285.17:01:25.71#ibcon#read 3, iclass 30, count 0 2006.285.17:01:25.71#ibcon#about to read 4, iclass 30, count 0 2006.285.17:01:25.71#ibcon#read 4, iclass 30, count 0 2006.285.17:01:25.71#ibcon#about to read 5, iclass 30, count 0 2006.285.17:01:25.71#ibcon#read 5, iclass 30, count 0 2006.285.17:01:25.71#ibcon#about to read 6, iclass 30, count 0 2006.285.17:01:25.71#ibcon#read 6, iclass 30, count 0 2006.285.17:01:25.71#ibcon#end of sib2, iclass 30, count 0 2006.285.17:01:25.71#ibcon#*after write, iclass 30, count 0 2006.285.17:01:25.71#ibcon#*before return 0, iclass 30, count 0 2006.285.17:01:25.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:01:25.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:01:25.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.17:01:25.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.17:01:25.71$vck44/vb=8,4 2006.285.17:01:25.71#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.17:01:25.71#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.17:01:25.71#ibcon#ireg 11 cls_cnt 2 2006.285.17:01:25.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:01:25.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:01:25.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:01:25.77#ibcon#enter wrdev, iclass 32, count 2 2006.285.17:01:25.77#ibcon#first serial, iclass 32, count 2 2006.285.17:01:25.77#ibcon#enter sib2, iclass 32, count 2 2006.285.17:01:25.77#ibcon#flushed, iclass 32, count 2 2006.285.17:01:25.77#ibcon#about to write, iclass 32, count 2 2006.285.17:01:25.77#ibcon#wrote, iclass 32, count 2 2006.285.17:01:25.77#ibcon#about to read 3, iclass 32, count 2 2006.285.17:01:25.79#ibcon#read 3, iclass 32, count 2 2006.285.17:01:25.79#ibcon#about to read 4, iclass 32, count 2 2006.285.17:01:25.79#ibcon#read 4, iclass 32, count 2 2006.285.17:01:25.79#ibcon#about to read 5, iclass 32, count 2 2006.285.17:01:25.79#ibcon#read 5, iclass 32, count 2 2006.285.17:01:25.79#ibcon#about to read 6, iclass 32, count 2 2006.285.17:01:25.79#ibcon#read 6, iclass 32, count 2 2006.285.17:01:25.79#ibcon#end of sib2, iclass 32, count 2 2006.285.17:01:25.79#ibcon#*mode == 0, iclass 32, count 2 2006.285.17:01:25.79#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.17:01:25.79#ibcon#[27=AT08-04\r\n] 2006.285.17:01:25.79#ibcon#*before write, iclass 32, count 2 2006.285.17:01:25.79#ibcon#enter sib2, iclass 32, count 2 2006.285.17:01:25.79#ibcon#flushed, iclass 32, count 2 2006.285.17:01:25.79#ibcon#about to write, iclass 32, count 2 2006.285.17:01:25.79#ibcon#wrote, iclass 32, count 2 2006.285.17:01:25.79#ibcon#about to read 3, iclass 32, count 2 2006.285.17:01:25.82#ibcon#read 3, iclass 32, count 2 2006.285.17:01:25.82#ibcon#about to read 4, iclass 32, count 2 2006.285.17:01:25.82#ibcon#read 4, iclass 32, count 2 2006.285.17:01:25.82#ibcon#about to read 5, iclass 32, count 2 2006.285.17:01:25.82#ibcon#read 5, iclass 32, count 2 2006.285.17:01:25.82#ibcon#about to read 6, iclass 32, count 2 2006.285.17:01:25.82#ibcon#read 6, iclass 32, count 2 2006.285.17:01:25.82#ibcon#end of sib2, iclass 32, count 2 2006.285.17:01:25.82#ibcon#*after write, iclass 32, count 2 2006.285.17:01:25.82#ibcon#*before return 0, iclass 32, count 2 2006.285.17:01:25.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:01:25.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:01:25.82#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.17:01:25.82#ibcon#ireg 7 cls_cnt 0 2006.285.17:01:25.82#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:01:25.94#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:01:25.94#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:01:25.94#ibcon#enter wrdev, iclass 32, count 0 2006.285.17:01:25.94#ibcon#first serial, iclass 32, count 0 2006.285.17:01:25.94#ibcon#enter sib2, iclass 32, count 0 2006.285.17:01:25.94#ibcon#flushed, iclass 32, count 0 2006.285.17:01:25.94#ibcon#about to write, iclass 32, count 0 2006.285.17:01:25.94#ibcon#wrote, iclass 32, count 0 2006.285.17:01:25.94#ibcon#about to read 3, iclass 32, count 0 2006.285.17:01:25.96#ibcon#read 3, iclass 32, count 0 2006.285.17:01:25.96#ibcon#about to read 4, iclass 32, count 0 2006.285.17:01:25.96#ibcon#read 4, iclass 32, count 0 2006.285.17:01:25.96#ibcon#about to read 5, iclass 32, count 0 2006.285.17:01:25.96#ibcon#read 5, iclass 32, count 0 2006.285.17:01:25.96#ibcon#about to read 6, iclass 32, count 0 2006.285.17:01:25.96#ibcon#read 6, iclass 32, count 0 2006.285.17:01:25.96#ibcon#end of sib2, iclass 32, count 0 2006.285.17:01:25.96#ibcon#*mode == 0, iclass 32, count 0 2006.285.17:01:25.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.17:01:25.96#ibcon#[27=USB\r\n] 2006.285.17:01:25.96#ibcon#*before write, iclass 32, count 0 2006.285.17:01:25.96#ibcon#enter sib2, iclass 32, count 0 2006.285.17:01:25.96#ibcon#flushed, iclass 32, count 0 2006.285.17:01:25.96#ibcon#about to write, iclass 32, count 0 2006.285.17:01:25.96#ibcon#wrote, iclass 32, count 0 2006.285.17:01:25.96#ibcon#about to read 3, iclass 32, count 0 2006.285.17:01:25.99#ibcon#read 3, iclass 32, count 0 2006.285.17:01:25.99#ibcon#about to read 4, iclass 32, count 0 2006.285.17:01:25.99#ibcon#read 4, iclass 32, count 0 2006.285.17:01:25.99#ibcon#about to read 5, iclass 32, count 0 2006.285.17:01:25.99#ibcon#read 5, iclass 32, count 0 2006.285.17:01:25.99#ibcon#about to read 6, iclass 32, count 0 2006.285.17:01:25.99#ibcon#read 6, iclass 32, count 0 2006.285.17:01:25.99#ibcon#end of sib2, iclass 32, count 0 2006.285.17:01:25.99#ibcon#*after write, iclass 32, count 0 2006.285.17:01:25.99#ibcon#*before return 0, iclass 32, count 0 2006.285.17:01:25.99#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:01:25.99#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:01:25.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.17:01:25.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.17:01:25.99$vck44/vabw=wide 2006.285.17:01:25.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.17:01:25.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.17:01:25.99#ibcon#ireg 8 cls_cnt 0 2006.285.17:01:25.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:01:25.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:01:25.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:01:25.99#ibcon#enter wrdev, iclass 34, count 0 2006.285.17:01:25.99#ibcon#first serial, iclass 34, count 0 2006.285.17:01:25.99#ibcon#enter sib2, iclass 34, count 0 2006.285.17:01:25.99#ibcon#flushed, iclass 34, count 0 2006.285.17:01:25.99#ibcon#about to write, iclass 34, count 0 2006.285.17:01:25.99#ibcon#wrote, iclass 34, count 0 2006.285.17:01:25.99#ibcon#about to read 3, iclass 34, count 0 2006.285.17:01:26.01#ibcon#read 3, iclass 34, count 0 2006.285.17:01:26.01#ibcon#about to read 4, iclass 34, count 0 2006.285.17:01:26.01#ibcon#read 4, iclass 34, count 0 2006.285.17:01:26.01#ibcon#about to read 5, iclass 34, count 0 2006.285.17:01:26.01#ibcon#read 5, iclass 34, count 0 2006.285.17:01:26.01#ibcon#about to read 6, iclass 34, count 0 2006.285.17:01:26.01#ibcon#read 6, iclass 34, count 0 2006.285.17:01:26.01#ibcon#end of sib2, iclass 34, count 0 2006.285.17:01:26.01#ibcon#*mode == 0, iclass 34, count 0 2006.285.17:01:26.01#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.17:01:26.01#ibcon#[25=BW32\r\n] 2006.285.17:01:26.01#ibcon#*before write, iclass 34, count 0 2006.285.17:01:26.01#ibcon#enter sib2, iclass 34, count 0 2006.285.17:01:26.01#ibcon#flushed, iclass 34, count 0 2006.285.17:01:26.01#ibcon#about to write, iclass 34, count 0 2006.285.17:01:26.01#ibcon#wrote, iclass 34, count 0 2006.285.17:01:26.01#ibcon#about to read 3, iclass 34, count 0 2006.285.17:01:26.04#ibcon#read 3, iclass 34, count 0 2006.285.17:01:26.04#ibcon#about to read 4, iclass 34, count 0 2006.285.17:01:26.04#ibcon#read 4, iclass 34, count 0 2006.285.17:01:26.04#ibcon#about to read 5, iclass 34, count 0 2006.285.17:01:26.04#ibcon#read 5, iclass 34, count 0 2006.285.17:01:26.04#ibcon#about to read 6, iclass 34, count 0 2006.285.17:01:26.04#ibcon#read 6, iclass 34, count 0 2006.285.17:01:26.04#ibcon#end of sib2, iclass 34, count 0 2006.285.17:01:26.04#ibcon#*after write, iclass 34, count 0 2006.285.17:01:26.04#ibcon#*before return 0, iclass 34, count 0 2006.285.17:01:26.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:01:26.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:01:26.04#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.17:01:26.04#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.17:01:26.04$vck44/vbbw=wide 2006.285.17:01:26.04#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.17:01:26.04#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.17:01:26.04#ibcon#ireg 8 cls_cnt 0 2006.285.17:01:26.04#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:01:26.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:01:26.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:01:26.11#ibcon#enter wrdev, iclass 36, count 0 2006.285.17:01:26.11#ibcon#first serial, iclass 36, count 0 2006.285.17:01:26.11#ibcon#enter sib2, iclass 36, count 0 2006.285.17:01:26.11#ibcon#flushed, iclass 36, count 0 2006.285.17:01:26.11#ibcon#about to write, iclass 36, count 0 2006.285.17:01:26.11#ibcon#wrote, iclass 36, count 0 2006.285.17:01:26.11#ibcon#about to read 3, iclass 36, count 0 2006.285.17:01:26.13#ibcon#read 3, iclass 36, count 0 2006.285.17:01:26.13#ibcon#about to read 4, iclass 36, count 0 2006.285.17:01:26.13#ibcon#read 4, iclass 36, count 0 2006.285.17:01:26.13#ibcon#about to read 5, iclass 36, count 0 2006.285.17:01:26.13#ibcon#read 5, iclass 36, count 0 2006.285.17:01:26.13#ibcon#about to read 6, iclass 36, count 0 2006.285.17:01:26.13#ibcon#read 6, iclass 36, count 0 2006.285.17:01:26.13#ibcon#end of sib2, iclass 36, count 0 2006.285.17:01:26.13#ibcon#*mode == 0, iclass 36, count 0 2006.285.17:01:26.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.17:01:26.13#ibcon#[27=BW32\r\n] 2006.285.17:01:26.13#ibcon#*before write, iclass 36, count 0 2006.285.17:01:26.13#ibcon#enter sib2, iclass 36, count 0 2006.285.17:01:26.13#ibcon#flushed, iclass 36, count 0 2006.285.17:01:26.13#ibcon#about to write, iclass 36, count 0 2006.285.17:01:26.13#ibcon#wrote, iclass 36, count 0 2006.285.17:01:26.13#ibcon#about to read 3, iclass 36, count 0 2006.285.17:01:26.16#ibcon#read 3, iclass 36, count 0 2006.285.17:01:26.16#ibcon#about to read 4, iclass 36, count 0 2006.285.17:01:26.16#ibcon#read 4, iclass 36, count 0 2006.285.17:01:26.16#ibcon#about to read 5, iclass 36, count 0 2006.285.17:01:26.16#ibcon#read 5, iclass 36, count 0 2006.285.17:01:26.16#ibcon#about to read 6, iclass 36, count 0 2006.285.17:01:26.16#ibcon#read 6, iclass 36, count 0 2006.285.17:01:26.16#ibcon#end of sib2, iclass 36, count 0 2006.285.17:01:26.16#ibcon#*after write, iclass 36, count 0 2006.285.17:01:26.16#ibcon#*before return 0, iclass 36, count 0 2006.285.17:01:26.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:01:26.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:01:26.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.17:01:26.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.17:01:26.16$setupk4/ifdk4 2006.285.17:01:26.16$ifdk4/lo= 2006.285.17:01:26.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.17:01:26.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.17:01:26.16$ifdk4/patch= 2006.285.17:01:26.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.17:01:26.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.17:01:26.16$setupk4/!*+20s 2006.285.17:01:30.57#abcon#<5=/14 0.5 1.0 17.63 961014.8\r\n> 2006.285.17:01:30.59#abcon#{5=INTERFACE CLEAR} 2006.285.17:01:30.65#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:01:39.47$setupk4/"tpicd 2006.285.17:01:39.47$setupk4/echo=off 2006.285.17:01:39.47$setupk4/xlog=off 2006.285.17:01:39.47:!2006.285.17:09:43 2006.285.17:02:15.13#trakl#Source acquired 2006.285.17:02:16.13#flagr#flagr/antenna,acquired 2006.285.17:09:43.02:preob 2006.285.17:09:44.14/onsource/TRACKING 2006.285.17:09:44.14:!2006.285.17:09:53 2006.285.17:09:53.01:"tape 2006.285.17:09:53.02:"st=record 2006.285.17:09:53.02:data_valid=on 2006.285.17:09:53.02:midob 2006.285.17:09:54.14/onsource/TRACKING 2006.285.17:09:54.14/wx/17.31,1014.8,97 2006.285.17:09:54.31/cable/+6.5011E-03 2006.285.17:09:55.40/va/01,07,usb,yes,34,37 2006.285.17:09:55.40/va/02,06,usb,yes,34,34 2006.285.17:09:55.40/va/03,07,usb,yes,33,35 2006.285.17:09:55.40/va/04,06,usb,yes,35,37 2006.285.17:09:55.40/va/05,03,usb,yes,35,35 2006.285.17:09:55.40/va/06,04,usb,yes,31,31 2006.285.17:09:55.40/va/07,04,usb,yes,32,32 2006.285.17:09:55.40/va/08,03,usb,yes,32,39 2006.285.17:09:55.63/valo/01,524.99,yes,locked 2006.285.17:09:55.63/valo/02,534.99,yes,locked 2006.285.17:09:55.63/valo/03,564.99,yes,locked 2006.285.17:09:55.63/valo/04,624.99,yes,locked 2006.285.17:09:55.63/valo/05,734.99,yes,locked 2006.285.17:09:55.63/valo/06,814.99,yes,locked 2006.285.17:09:55.63/valo/07,864.99,yes,locked 2006.285.17:09:55.63/valo/08,884.99,yes,locked 2006.285.17:09:56.72/vb/01,04,usb,yes,31,29 2006.285.17:09:56.72/vb/02,05,usb,yes,29,30 2006.285.17:09:56.72/vb/03,04,usb,yes,31,34 2006.285.17:09:56.72/vb/04,05,usb,yes,31,30 2006.285.17:09:56.72/vb/05,04,usb,yes,27,30 2006.285.17:09:56.72/vb/06,03,usb,yes,39,34 2006.285.17:09:56.72/vb/07,04,usb,yes,31,31 2006.285.17:09:56.72/vb/08,04,usb,yes,28,32 2006.285.17:09:56.95/vblo/01,629.99,yes,locked 2006.285.17:09:56.95/vblo/02,634.99,yes,locked 2006.285.17:09:56.95/vblo/03,649.99,yes,locked 2006.285.17:09:56.95/vblo/04,679.99,yes,locked 2006.285.17:09:56.95/vblo/05,709.99,yes,locked 2006.285.17:09:56.95/vblo/06,719.99,yes,locked 2006.285.17:09:56.95/vblo/07,734.99,yes,locked 2006.285.17:09:56.95/vblo/08,744.99,yes,locked 2006.285.17:09:57.10/vabw/8 2006.285.17:09:57.25/vbbw/8 2006.285.17:09:57.34/xfe/off,on,12.2 2006.285.17:09:57.72/ifatt/23,28,28,28 2006.285.17:09:58.07/fmout-gps/S +2.69E-07 2006.285.17:09:58.09:!2006.285.17:11:03 2006.285.17:11:03.01:data_valid=off 2006.285.17:11:03.02:"et 2006.285.17:11:03.02:!+3s 2006.285.17:11:06.04:"tape 2006.285.17:11:06.04:postob 2006.285.17:11:06.23/cable/+6.5017E-03 2006.285.17:11:06.24/wx/17.28,1014.8,97 2006.285.17:11:06.29/fmout-gps/S +2.69E-07 2006.285.17:11:06.29:scan_name=285-1713,jd0610,100 2006.285.17:11:06.30:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.285.17:11:07.13#flagr#flagr/antenna,new-source 2006.285.17:11:07.14:checkk5 2006.285.17:11:07.50/chk_autoobs//k5ts1/ autoobs is running! 2006.285.17:11:08.03/chk_autoobs//k5ts2/ autoobs is running! 2006.285.17:11:08.43/chk_autoobs//k5ts3/ autoobs is running! 2006.285.17:11:08.96/chk_autoobs//k5ts4/ autoobs is running! 2006.285.17:11:09.36/chk_obsdata//k5ts1/T2851709??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.17:11:09.82/chk_obsdata//k5ts2/T2851709??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.17:11:10.22/chk_obsdata//k5ts3/T2851709??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.17:11:10.64/chk_obsdata//k5ts4/T2851709??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.17:11:11.50/k5log//k5ts1_log_newline 2006.285.17:11:12.27/k5log//k5ts2_log_newline 2006.285.17:11:13.01/k5log//k5ts3_log_newline 2006.285.17:11:14.09/k5log//k5ts4_log_newline 2006.285.17:11:14.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.17:11:14.11:setupk4=1 2006.285.17:11:14.12$setupk4/echo=on 2006.285.17:11:14.12$setupk4/pcalon 2006.285.17:11:14.12$pcalon/"no phase cal control is implemented here 2006.285.17:11:14.12$setupk4/"tpicd=stop 2006.285.17:11:14.12$setupk4/"rec=synch_on 2006.285.17:11:14.12$setupk4/"rec_mode=128 2006.285.17:11:14.12$setupk4/!* 2006.285.17:11:14.12$setupk4/recpk4 2006.285.17:11:14.12$recpk4/recpatch= 2006.285.17:11:14.12$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.17:11:14.12$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.17:11:14.12$setupk4/vck44 2006.285.17:11:14.12$vck44/valo=1,524.99 2006.285.17:11:14.12#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.17:11:14.12#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.17:11:14.12#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:14.12#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:11:14.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:11:14.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:11:14.12#ibcon#enter wrdev, iclass 21, count 0 2006.285.17:11:14.12#ibcon#first serial, iclass 21, count 0 2006.285.17:11:14.12#ibcon#enter sib2, iclass 21, count 0 2006.285.17:11:14.12#ibcon#flushed, iclass 21, count 0 2006.285.17:11:14.12#ibcon#about to write, iclass 21, count 0 2006.285.17:11:14.12#ibcon#wrote, iclass 21, count 0 2006.285.17:11:14.12#ibcon#about to read 3, iclass 21, count 0 2006.285.17:11:14.13#ibcon#read 3, iclass 21, count 0 2006.285.17:11:14.13#ibcon#about to read 4, iclass 21, count 0 2006.285.17:11:14.13#ibcon#read 4, iclass 21, count 0 2006.285.17:11:14.13#ibcon#about to read 5, iclass 21, count 0 2006.285.17:11:14.13#ibcon#read 5, iclass 21, count 0 2006.285.17:11:14.13#ibcon#about to read 6, iclass 21, count 0 2006.285.17:11:14.13#ibcon#read 6, iclass 21, count 0 2006.285.17:11:14.13#ibcon#end of sib2, iclass 21, count 0 2006.285.17:11:14.13#ibcon#*mode == 0, iclass 21, count 0 2006.285.17:11:14.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.17:11:14.13#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.17:11:14.13#ibcon#*before write, iclass 21, count 0 2006.285.17:11:14.13#ibcon#enter sib2, iclass 21, count 0 2006.285.17:11:14.13#ibcon#flushed, iclass 21, count 0 2006.285.17:11:14.13#ibcon#about to write, iclass 21, count 0 2006.285.17:11:14.13#ibcon#wrote, iclass 21, count 0 2006.285.17:11:14.13#ibcon#about to read 3, iclass 21, count 0 2006.285.17:11:14.18#ibcon#read 3, iclass 21, count 0 2006.285.17:11:14.18#ibcon#about to read 4, iclass 21, count 0 2006.285.17:11:14.18#ibcon#read 4, iclass 21, count 0 2006.285.17:11:14.18#ibcon#about to read 5, iclass 21, count 0 2006.285.17:11:14.18#ibcon#read 5, iclass 21, count 0 2006.285.17:11:14.18#ibcon#about to read 6, iclass 21, count 0 2006.285.17:11:14.18#ibcon#read 6, iclass 21, count 0 2006.285.17:11:14.18#ibcon#end of sib2, iclass 21, count 0 2006.285.17:11:14.18#ibcon#*after write, iclass 21, count 0 2006.285.17:11:14.18#ibcon#*before return 0, iclass 21, count 0 2006.285.17:11:14.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:11:14.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:11:14.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.17:11:14.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.17:11:14.18$vck44/va=1,7 2006.285.17:11:14.18#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.17:11:14.18#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.17:11:14.18#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:14.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:11:14.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:11:14.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:11:14.18#ibcon#enter wrdev, iclass 23, count 2 2006.285.17:11:14.18#ibcon#first serial, iclass 23, count 2 2006.285.17:11:14.18#ibcon#enter sib2, iclass 23, count 2 2006.285.17:11:14.18#ibcon#flushed, iclass 23, count 2 2006.285.17:11:14.18#ibcon#about to write, iclass 23, count 2 2006.285.17:11:14.18#ibcon#wrote, iclass 23, count 2 2006.285.17:11:14.18#ibcon#about to read 3, iclass 23, count 2 2006.285.17:11:14.20#ibcon#read 3, iclass 23, count 2 2006.285.17:11:14.20#ibcon#about to read 4, iclass 23, count 2 2006.285.17:11:14.20#ibcon#read 4, iclass 23, count 2 2006.285.17:11:14.20#ibcon#about to read 5, iclass 23, count 2 2006.285.17:11:14.20#ibcon#read 5, iclass 23, count 2 2006.285.17:11:14.20#ibcon#about to read 6, iclass 23, count 2 2006.285.17:11:14.20#ibcon#read 6, iclass 23, count 2 2006.285.17:11:14.20#ibcon#end of sib2, iclass 23, count 2 2006.285.17:11:14.20#ibcon#*mode == 0, iclass 23, count 2 2006.285.17:11:14.20#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.17:11:14.20#ibcon#[25=AT01-07\r\n] 2006.285.17:11:14.20#ibcon#*before write, iclass 23, count 2 2006.285.17:11:14.20#ibcon#enter sib2, iclass 23, count 2 2006.285.17:11:14.20#ibcon#flushed, iclass 23, count 2 2006.285.17:11:14.20#ibcon#about to write, iclass 23, count 2 2006.285.17:11:14.20#ibcon#wrote, iclass 23, count 2 2006.285.17:11:14.20#ibcon#about to read 3, iclass 23, count 2 2006.285.17:11:14.23#ibcon#read 3, iclass 23, count 2 2006.285.17:11:14.23#ibcon#about to read 4, iclass 23, count 2 2006.285.17:11:14.23#ibcon#read 4, iclass 23, count 2 2006.285.17:11:14.23#ibcon#about to read 5, iclass 23, count 2 2006.285.17:11:14.23#ibcon#read 5, iclass 23, count 2 2006.285.17:11:14.23#ibcon#about to read 6, iclass 23, count 2 2006.285.17:11:14.23#ibcon#read 6, iclass 23, count 2 2006.285.17:11:14.23#ibcon#end of sib2, iclass 23, count 2 2006.285.17:11:14.23#ibcon#*after write, iclass 23, count 2 2006.285.17:11:14.23#ibcon#*before return 0, iclass 23, count 2 2006.285.17:11:14.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:11:14.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:11:14.23#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.17:11:14.23#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:14.23#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:11:14.35#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:11:14.35#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:11:14.35#ibcon#enter wrdev, iclass 23, count 0 2006.285.17:11:14.35#ibcon#first serial, iclass 23, count 0 2006.285.17:11:14.35#ibcon#enter sib2, iclass 23, count 0 2006.285.17:11:14.35#ibcon#flushed, iclass 23, count 0 2006.285.17:11:14.35#ibcon#about to write, iclass 23, count 0 2006.285.17:11:14.35#ibcon#wrote, iclass 23, count 0 2006.285.17:11:14.35#ibcon#about to read 3, iclass 23, count 0 2006.285.17:11:14.37#ibcon#read 3, iclass 23, count 0 2006.285.17:11:14.37#ibcon#about to read 4, iclass 23, count 0 2006.285.17:11:14.37#ibcon#read 4, iclass 23, count 0 2006.285.17:11:14.37#ibcon#about to read 5, iclass 23, count 0 2006.285.17:11:14.37#ibcon#read 5, iclass 23, count 0 2006.285.17:11:14.37#ibcon#about to read 6, iclass 23, count 0 2006.285.17:11:14.37#ibcon#read 6, iclass 23, count 0 2006.285.17:11:14.37#ibcon#end of sib2, iclass 23, count 0 2006.285.17:11:14.37#ibcon#*mode == 0, iclass 23, count 0 2006.285.17:11:14.37#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.17:11:14.37#ibcon#[25=USB\r\n] 2006.285.17:11:14.37#ibcon#*before write, iclass 23, count 0 2006.285.17:11:14.37#ibcon#enter sib2, iclass 23, count 0 2006.285.17:11:14.37#ibcon#flushed, iclass 23, count 0 2006.285.17:11:14.37#ibcon#about to write, iclass 23, count 0 2006.285.17:11:14.37#ibcon#wrote, iclass 23, count 0 2006.285.17:11:14.37#ibcon#about to read 3, iclass 23, count 0 2006.285.17:11:14.40#ibcon#read 3, iclass 23, count 0 2006.285.17:11:14.40#ibcon#about to read 4, iclass 23, count 0 2006.285.17:11:14.40#ibcon#read 4, iclass 23, count 0 2006.285.17:11:14.40#ibcon#about to read 5, iclass 23, count 0 2006.285.17:11:14.40#ibcon#read 5, iclass 23, count 0 2006.285.17:11:14.40#ibcon#about to read 6, iclass 23, count 0 2006.285.17:11:14.40#ibcon#read 6, iclass 23, count 0 2006.285.17:11:14.40#ibcon#end of sib2, iclass 23, count 0 2006.285.17:11:14.40#ibcon#*after write, iclass 23, count 0 2006.285.17:11:14.40#ibcon#*before return 0, iclass 23, count 0 2006.285.17:11:14.40#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:11:14.40#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:11:14.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.17:11:14.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.17:11:14.40$vck44/valo=2,534.99 2006.285.17:11:14.40#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.17:11:14.40#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.17:11:14.40#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:14.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:11:14.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:11:14.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:11:14.40#ibcon#enter wrdev, iclass 25, count 0 2006.285.17:11:14.40#ibcon#first serial, iclass 25, count 0 2006.285.17:11:14.40#ibcon#enter sib2, iclass 25, count 0 2006.285.17:11:14.40#ibcon#flushed, iclass 25, count 0 2006.285.17:11:14.40#ibcon#about to write, iclass 25, count 0 2006.285.17:11:14.40#ibcon#wrote, iclass 25, count 0 2006.285.17:11:14.40#ibcon#about to read 3, iclass 25, count 0 2006.285.17:11:14.42#ibcon#read 3, iclass 25, count 0 2006.285.17:11:14.42#ibcon#about to read 4, iclass 25, count 0 2006.285.17:11:14.42#ibcon#read 4, iclass 25, count 0 2006.285.17:11:14.42#ibcon#about to read 5, iclass 25, count 0 2006.285.17:11:14.42#ibcon#read 5, iclass 25, count 0 2006.285.17:11:14.42#ibcon#about to read 6, iclass 25, count 0 2006.285.17:11:14.42#ibcon#read 6, iclass 25, count 0 2006.285.17:11:14.42#ibcon#end of sib2, iclass 25, count 0 2006.285.17:11:14.42#ibcon#*mode == 0, iclass 25, count 0 2006.285.17:11:14.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.17:11:14.42#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.17:11:14.42#ibcon#*before write, iclass 25, count 0 2006.285.17:11:14.42#ibcon#enter sib2, iclass 25, count 0 2006.285.17:11:14.42#ibcon#flushed, iclass 25, count 0 2006.285.17:11:14.42#ibcon#about to write, iclass 25, count 0 2006.285.17:11:14.42#ibcon#wrote, iclass 25, count 0 2006.285.17:11:14.42#ibcon#about to read 3, iclass 25, count 0 2006.285.17:11:14.46#ibcon#read 3, iclass 25, count 0 2006.285.17:11:14.46#ibcon#about to read 4, iclass 25, count 0 2006.285.17:11:14.46#ibcon#read 4, iclass 25, count 0 2006.285.17:11:14.46#ibcon#about to read 5, iclass 25, count 0 2006.285.17:11:14.46#ibcon#read 5, iclass 25, count 0 2006.285.17:11:14.46#ibcon#about to read 6, iclass 25, count 0 2006.285.17:11:14.46#ibcon#read 6, iclass 25, count 0 2006.285.17:11:14.46#ibcon#end of sib2, iclass 25, count 0 2006.285.17:11:14.46#ibcon#*after write, iclass 25, count 0 2006.285.17:11:14.46#ibcon#*before return 0, iclass 25, count 0 2006.285.17:11:14.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:11:14.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:11:14.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.17:11:14.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.17:11:14.46$vck44/va=2,6 2006.285.17:11:14.46#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.17:11:14.46#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.17:11:14.46#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:14.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:11:14.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:11:14.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:11:14.52#ibcon#enter wrdev, iclass 27, count 2 2006.285.17:11:14.52#ibcon#first serial, iclass 27, count 2 2006.285.17:11:14.52#ibcon#enter sib2, iclass 27, count 2 2006.285.17:11:14.52#ibcon#flushed, iclass 27, count 2 2006.285.17:11:14.52#ibcon#about to write, iclass 27, count 2 2006.285.17:11:14.52#ibcon#wrote, iclass 27, count 2 2006.285.17:11:14.52#ibcon#about to read 3, iclass 27, count 2 2006.285.17:11:14.54#ibcon#read 3, iclass 27, count 2 2006.285.17:11:14.54#ibcon#about to read 4, iclass 27, count 2 2006.285.17:11:14.54#ibcon#read 4, iclass 27, count 2 2006.285.17:11:14.54#ibcon#about to read 5, iclass 27, count 2 2006.285.17:11:14.54#ibcon#read 5, iclass 27, count 2 2006.285.17:11:14.54#ibcon#about to read 6, iclass 27, count 2 2006.285.17:11:14.54#ibcon#read 6, iclass 27, count 2 2006.285.17:11:14.54#ibcon#end of sib2, iclass 27, count 2 2006.285.17:11:14.54#ibcon#*mode == 0, iclass 27, count 2 2006.285.17:11:14.54#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.17:11:14.54#ibcon#[25=AT02-06\r\n] 2006.285.17:11:14.54#ibcon#*before write, iclass 27, count 2 2006.285.17:11:14.54#ibcon#enter sib2, iclass 27, count 2 2006.285.17:11:14.54#ibcon#flushed, iclass 27, count 2 2006.285.17:11:14.54#ibcon#about to write, iclass 27, count 2 2006.285.17:11:14.54#ibcon#wrote, iclass 27, count 2 2006.285.17:11:14.54#ibcon#about to read 3, iclass 27, count 2 2006.285.17:11:14.57#ibcon#read 3, iclass 27, count 2 2006.285.17:11:14.57#ibcon#about to read 4, iclass 27, count 2 2006.285.17:11:14.57#ibcon#read 4, iclass 27, count 2 2006.285.17:11:14.57#ibcon#about to read 5, iclass 27, count 2 2006.285.17:11:14.57#ibcon#read 5, iclass 27, count 2 2006.285.17:11:14.57#ibcon#about to read 6, iclass 27, count 2 2006.285.17:11:14.57#ibcon#read 6, iclass 27, count 2 2006.285.17:11:14.57#ibcon#end of sib2, iclass 27, count 2 2006.285.17:11:14.57#ibcon#*after write, iclass 27, count 2 2006.285.17:11:14.57#ibcon#*before return 0, iclass 27, count 2 2006.285.17:11:14.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:11:14.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:11:14.57#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.17:11:14.57#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:14.57#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:11:14.69#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:11:14.69#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:11:14.69#ibcon#enter wrdev, iclass 27, count 0 2006.285.17:11:14.69#ibcon#first serial, iclass 27, count 0 2006.285.17:11:14.69#ibcon#enter sib2, iclass 27, count 0 2006.285.17:11:14.69#ibcon#flushed, iclass 27, count 0 2006.285.17:11:14.69#ibcon#about to write, iclass 27, count 0 2006.285.17:11:14.69#ibcon#wrote, iclass 27, count 0 2006.285.17:11:14.69#ibcon#about to read 3, iclass 27, count 0 2006.285.17:11:14.71#ibcon#read 3, iclass 27, count 0 2006.285.17:11:14.71#ibcon#about to read 4, iclass 27, count 0 2006.285.17:11:14.71#ibcon#read 4, iclass 27, count 0 2006.285.17:11:14.71#ibcon#about to read 5, iclass 27, count 0 2006.285.17:11:14.71#ibcon#read 5, iclass 27, count 0 2006.285.17:11:14.71#ibcon#about to read 6, iclass 27, count 0 2006.285.17:11:14.71#ibcon#read 6, iclass 27, count 0 2006.285.17:11:14.71#ibcon#end of sib2, iclass 27, count 0 2006.285.17:11:14.71#ibcon#*mode == 0, iclass 27, count 0 2006.285.17:11:14.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.17:11:14.71#ibcon#[25=USB\r\n] 2006.285.17:11:14.71#ibcon#*before write, iclass 27, count 0 2006.285.17:11:14.71#ibcon#enter sib2, iclass 27, count 0 2006.285.17:11:14.71#ibcon#flushed, iclass 27, count 0 2006.285.17:11:14.71#ibcon#about to write, iclass 27, count 0 2006.285.17:11:14.71#ibcon#wrote, iclass 27, count 0 2006.285.17:11:14.71#ibcon#about to read 3, iclass 27, count 0 2006.285.17:11:14.74#ibcon#read 3, iclass 27, count 0 2006.285.17:11:14.74#ibcon#about to read 4, iclass 27, count 0 2006.285.17:11:14.74#ibcon#read 4, iclass 27, count 0 2006.285.17:11:14.74#ibcon#about to read 5, iclass 27, count 0 2006.285.17:11:14.74#ibcon#read 5, iclass 27, count 0 2006.285.17:11:14.74#ibcon#about to read 6, iclass 27, count 0 2006.285.17:11:14.74#ibcon#read 6, iclass 27, count 0 2006.285.17:11:14.74#ibcon#end of sib2, iclass 27, count 0 2006.285.17:11:14.74#ibcon#*after write, iclass 27, count 0 2006.285.17:11:14.74#ibcon#*before return 0, iclass 27, count 0 2006.285.17:11:14.74#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:11:14.74#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:11:14.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.17:11:14.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.17:11:14.74$vck44/valo=3,564.99 2006.285.17:11:14.74#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.17:11:15.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.17:11:15.21#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:15.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:11:15.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:11:15.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:11:15.21#ibcon#enter wrdev, iclass 29, count 0 2006.285.17:11:15.21#ibcon#first serial, iclass 29, count 0 2006.285.17:11:15.21#ibcon#enter sib2, iclass 29, count 0 2006.285.17:11:15.21#ibcon#flushed, iclass 29, count 0 2006.285.17:11:15.21#ibcon#about to write, iclass 29, count 0 2006.285.17:11:15.21#ibcon#wrote, iclass 29, count 0 2006.285.17:11:15.21#ibcon#about to read 3, iclass 29, count 0 2006.285.17:11:15.22#ibcon#read 3, iclass 29, count 0 2006.285.17:11:15.22#ibcon#about to read 4, iclass 29, count 0 2006.285.17:11:15.22#ibcon#read 4, iclass 29, count 0 2006.285.17:11:15.22#ibcon#about to read 5, iclass 29, count 0 2006.285.17:11:15.22#ibcon#read 5, iclass 29, count 0 2006.285.17:11:15.22#ibcon#about to read 6, iclass 29, count 0 2006.285.17:11:15.22#ibcon#read 6, iclass 29, count 0 2006.285.17:11:15.22#ibcon#end of sib2, iclass 29, count 0 2006.285.17:11:15.22#ibcon#*mode == 0, iclass 29, count 0 2006.285.17:11:15.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.17:11:15.22#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.17:11:15.22#ibcon#*before write, iclass 29, count 0 2006.285.17:11:15.22#ibcon#enter sib2, iclass 29, count 0 2006.285.17:11:15.22#ibcon#flushed, iclass 29, count 0 2006.285.17:11:15.22#ibcon#about to write, iclass 29, count 0 2006.285.17:11:15.22#ibcon#wrote, iclass 29, count 0 2006.285.17:11:15.22#ibcon#about to read 3, iclass 29, count 0 2006.285.17:11:15.26#ibcon#read 3, iclass 29, count 0 2006.285.17:11:15.26#ibcon#about to read 4, iclass 29, count 0 2006.285.17:11:15.26#ibcon#read 4, iclass 29, count 0 2006.285.17:11:15.26#ibcon#about to read 5, iclass 29, count 0 2006.285.17:11:15.26#ibcon#read 5, iclass 29, count 0 2006.285.17:11:15.26#ibcon#about to read 6, iclass 29, count 0 2006.285.17:11:15.26#ibcon#read 6, iclass 29, count 0 2006.285.17:11:15.26#ibcon#end of sib2, iclass 29, count 0 2006.285.17:11:15.26#ibcon#*after write, iclass 29, count 0 2006.285.17:11:15.26#ibcon#*before return 0, iclass 29, count 0 2006.285.17:11:15.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:11:15.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:11:15.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.17:11:15.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.17:11:15.26$vck44/va=3,7 2006.285.17:11:15.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.17:11:15.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.17:11:15.26#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:15.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:11:15.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:11:15.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:11:15.26#ibcon#enter wrdev, iclass 31, count 2 2006.285.17:11:15.26#ibcon#first serial, iclass 31, count 2 2006.285.17:11:15.26#ibcon#enter sib2, iclass 31, count 2 2006.285.17:11:15.26#ibcon#flushed, iclass 31, count 2 2006.285.17:11:15.26#ibcon#about to write, iclass 31, count 2 2006.285.17:11:15.26#ibcon#wrote, iclass 31, count 2 2006.285.17:11:15.26#ibcon#about to read 3, iclass 31, count 2 2006.285.17:11:15.28#ibcon#read 3, iclass 31, count 2 2006.285.17:11:15.28#ibcon#about to read 4, iclass 31, count 2 2006.285.17:11:15.28#ibcon#read 4, iclass 31, count 2 2006.285.17:11:15.28#ibcon#about to read 5, iclass 31, count 2 2006.285.17:11:15.28#ibcon#read 5, iclass 31, count 2 2006.285.17:11:15.28#ibcon#about to read 6, iclass 31, count 2 2006.285.17:11:15.28#ibcon#read 6, iclass 31, count 2 2006.285.17:11:15.28#ibcon#end of sib2, iclass 31, count 2 2006.285.17:11:15.28#ibcon#*mode == 0, iclass 31, count 2 2006.285.17:11:15.28#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.17:11:15.28#ibcon#[25=AT03-07\r\n] 2006.285.17:11:15.28#ibcon#*before write, iclass 31, count 2 2006.285.17:11:15.28#ibcon#enter sib2, iclass 31, count 2 2006.285.17:11:15.28#ibcon#flushed, iclass 31, count 2 2006.285.17:11:15.28#ibcon#about to write, iclass 31, count 2 2006.285.17:11:15.28#ibcon#wrote, iclass 31, count 2 2006.285.17:11:15.28#ibcon#about to read 3, iclass 31, count 2 2006.285.17:11:15.31#ibcon#read 3, iclass 31, count 2 2006.285.17:11:15.31#ibcon#about to read 4, iclass 31, count 2 2006.285.17:11:15.31#ibcon#read 4, iclass 31, count 2 2006.285.17:11:15.31#ibcon#about to read 5, iclass 31, count 2 2006.285.17:11:15.31#ibcon#read 5, iclass 31, count 2 2006.285.17:11:15.31#ibcon#about to read 6, iclass 31, count 2 2006.285.17:11:15.31#ibcon#read 6, iclass 31, count 2 2006.285.17:11:15.31#ibcon#end of sib2, iclass 31, count 2 2006.285.17:11:15.31#ibcon#*after write, iclass 31, count 2 2006.285.17:11:15.31#ibcon#*before return 0, iclass 31, count 2 2006.285.17:11:15.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:11:15.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:11:15.31#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.17:11:15.31#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:15.31#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:11:15.43#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:11:15.43#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:11:15.43#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:11:15.43#ibcon#first serial, iclass 31, count 0 2006.285.17:11:15.43#ibcon#enter sib2, iclass 31, count 0 2006.285.17:11:15.43#ibcon#flushed, iclass 31, count 0 2006.285.17:11:15.43#ibcon#about to write, iclass 31, count 0 2006.285.17:11:15.43#ibcon#wrote, iclass 31, count 0 2006.285.17:11:15.43#ibcon#about to read 3, iclass 31, count 0 2006.285.17:11:15.45#ibcon#read 3, iclass 31, count 0 2006.285.17:11:15.45#ibcon#about to read 4, iclass 31, count 0 2006.285.17:11:15.45#ibcon#read 4, iclass 31, count 0 2006.285.17:11:15.45#ibcon#about to read 5, iclass 31, count 0 2006.285.17:11:15.45#ibcon#read 5, iclass 31, count 0 2006.285.17:11:15.45#ibcon#about to read 6, iclass 31, count 0 2006.285.17:11:15.45#ibcon#read 6, iclass 31, count 0 2006.285.17:11:15.45#ibcon#end of sib2, iclass 31, count 0 2006.285.17:11:15.45#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:11:15.45#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:11:15.45#ibcon#[25=USB\r\n] 2006.285.17:11:15.45#ibcon#*before write, iclass 31, count 0 2006.285.17:11:15.45#ibcon#enter sib2, iclass 31, count 0 2006.285.17:11:15.45#ibcon#flushed, iclass 31, count 0 2006.285.17:11:15.45#ibcon#about to write, iclass 31, count 0 2006.285.17:11:15.45#ibcon#wrote, iclass 31, count 0 2006.285.17:11:15.45#ibcon#about to read 3, iclass 31, count 0 2006.285.17:11:15.48#ibcon#read 3, iclass 31, count 0 2006.285.17:11:15.48#ibcon#about to read 4, iclass 31, count 0 2006.285.17:11:15.48#ibcon#read 4, iclass 31, count 0 2006.285.17:11:15.48#ibcon#about to read 5, iclass 31, count 0 2006.285.17:11:15.48#ibcon#read 5, iclass 31, count 0 2006.285.17:11:15.48#ibcon#about to read 6, iclass 31, count 0 2006.285.17:11:15.48#ibcon#read 6, iclass 31, count 0 2006.285.17:11:15.48#ibcon#end of sib2, iclass 31, count 0 2006.285.17:11:15.48#ibcon#*after write, iclass 31, count 0 2006.285.17:11:15.48#ibcon#*before return 0, iclass 31, count 0 2006.285.17:11:15.48#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:11:15.48#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:11:15.48#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:11:15.48#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:11:15.48$vck44/valo=4,624.99 2006.285.17:11:15.48#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.17:11:15.48#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.17:11:15.48#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:15.48#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:11:15.48#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:11:15.48#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:11:15.48#ibcon#enter wrdev, iclass 33, count 0 2006.285.17:11:15.48#ibcon#first serial, iclass 33, count 0 2006.285.17:11:15.48#ibcon#enter sib2, iclass 33, count 0 2006.285.17:11:15.48#ibcon#flushed, iclass 33, count 0 2006.285.17:11:15.48#ibcon#about to write, iclass 33, count 0 2006.285.17:11:15.48#ibcon#wrote, iclass 33, count 0 2006.285.17:11:15.48#ibcon#about to read 3, iclass 33, count 0 2006.285.17:11:15.50#ibcon#read 3, iclass 33, count 0 2006.285.17:11:15.80#ibcon#about to read 4, iclass 33, count 0 2006.285.17:11:15.80#ibcon#read 4, iclass 33, count 0 2006.285.17:11:15.80#ibcon#about to read 5, iclass 33, count 0 2006.285.17:11:15.80#ibcon#read 5, iclass 33, count 0 2006.285.17:11:15.80#ibcon#about to read 6, iclass 33, count 0 2006.285.17:11:15.80#ibcon#read 6, iclass 33, count 0 2006.285.17:11:15.80#ibcon#end of sib2, iclass 33, count 0 2006.285.17:11:15.80#ibcon#*mode == 0, iclass 33, count 0 2006.285.17:11:15.80#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.17:11:15.80#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.17:11:15.80#ibcon#*before write, iclass 33, count 0 2006.285.17:11:15.80#ibcon#enter sib2, iclass 33, count 0 2006.285.17:11:15.80#ibcon#flushed, iclass 33, count 0 2006.285.17:11:15.80#ibcon#about to write, iclass 33, count 0 2006.285.17:11:15.80#ibcon#wrote, iclass 33, count 0 2006.285.17:11:15.80#ibcon#about to read 3, iclass 33, count 0 2006.285.17:11:15.83#ibcon#read 3, iclass 33, count 0 2006.285.17:11:15.83#ibcon#about to read 4, iclass 33, count 0 2006.285.17:11:15.83#ibcon#read 4, iclass 33, count 0 2006.285.17:11:15.83#ibcon#about to read 5, iclass 33, count 0 2006.285.17:11:15.83#ibcon#read 5, iclass 33, count 0 2006.285.17:11:15.83#ibcon#about to read 6, iclass 33, count 0 2006.285.17:11:15.83#ibcon#read 6, iclass 33, count 0 2006.285.17:11:15.83#ibcon#end of sib2, iclass 33, count 0 2006.285.17:11:15.83#ibcon#*after write, iclass 33, count 0 2006.285.17:11:15.83#ibcon#*before return 0, iclass 33, count 0 2006.285.17:11:15.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:11:15.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:11:15.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.17:11:15.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.17:11:15.83$vck44/va=4,6 2006.285.17:11:15.83#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.17:11:15.83#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.17:11:15.83#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:15.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:11:15.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:11:15.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:11:15.83#ibcon#enter wrdev, iclass 35, count 2 2006.285.17:11:15.83#ibcon#first serial, iclass 35, count 2 2006.285.17:11:15.83#ibcon#enter sib2, iclass 35, count 2 2006.285.17:11:15.83#ibcon#flushed, iclass 35, count 2 2006.285.17:11:15.83#ibcon#about to write, iclass 35, count 2 2006.285.17:11:15.83#ibcon#wrote, iclass 35, count 2 2006.285.17:11:15.83#ibcon#about to read 3, iclass 35, count 2 2006.285.17:11:15.85#ibcon#read 3, iclass 35, count 2 2006.285.17:11:15.85#ibcon#about to read 4, iclass 35, count 2 2006.285.17:11:15.85#ibcon#read 4, iclass 35, count 2 2006.285.17:11:15.85#ibcon#about to read 5, iclass 35, count 2 2006.285.17:11:15.85#ibcon#read 5, iclass 35, count 2 2006.285.17:11:15.85#ibcon#about to read 6, iclass 35, count 2 2006.285.17:11:15.85#ibcon#read 6, iclass 35, count 2 2006.285.17:11:15.85#ibcon#end of sib2, iclass 35, count 2 2006.285.17:11:15.85#ibcon#*mode == 0, iclass 35, count 2 2006.285.17:11:15.85#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.17:11:15.85#ibcon#[25=AT04-06\r\n] 2006.285.17:11:15.85#ibcon#*before write, iclass 35, count 2 2006.285.17:11:15.85#ibcon#enter sib2, iclass 35, count 2 2006.285.17:11:15.85#ibcon#flushed, iclass 35, count 2 2006.285.17:11:15.85#ibcon#about to write, iclass 35, count 2 2006.285.17:11:15.85#ibcon#wrote, iclass 35, count 2 2006.285.17:11:15.85#ibcon#about to read 3, iclass 35, count 2 2006.285.17:11:15.88#ibcon#read 3, iclass 35, count 2 2006.285.17:11:15.88#ibcon#about to read 4, iclass 35, count 2 2006.285.17:11:15.88#ibcon#read 4, iclass 35, count 2 2006.285.17:11:15.88#ibcon#about to read 5, iclass 35, count 2 2006.285.17:11:15.88#ibcon#read 5, iclass 35, count 2 2006.285.17:11:15.88#ibcon#about to read 6, iclass 35, count 2 2006.285.17:11:15.88#ibcon#read 6, iclass 35, count 2 2006.285.17:11:15.88#ibcon#end of sib2, iclass 35, count 2 2006.285.17:11:15.88#ibcon#*after write, iclass 35, count 2 2006.285.17:11:15.88#ibcon#*before return 0, iclass 35, count 2 2006.285.17:11:15.88#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:11:15.88#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:11:15.88#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.17:11:15.88#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:15.88#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:11:16.00#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:11:16.00#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:11:16.00#ibcon#enter wrdev, iclass 35, count 0 2006.285.17:11:16.00#ibcon#first serial, iclass 35, count 0 2006.285.17:11:16.00#ibcon#enter sib2, iclass 35, count 0 2006.285.17:11:16.00#ibcon#flushed, iclass 35, count 0 2006.285.17:11:16.00#ibcon#about to write, iclass 35, count 0 2006.285.17:11:16.00#ibcon#wrote, iclass 35, count 0 2006.285.17:11:16.00#ibcon#about to read 3, iclass 35, count 0 2006.285.17:11:16.02#ibcon#read 3, iclass 35, count 0 2006.285.17:11:16.02#ibcon#about to read 4, iclass 35, count 0 2006.285.17:11:16.02#ibcon#read 4, iclass 35, count 0 2006.285.17:11:16.02#ibcon#about to read 5, iclass 35, count 0 2006.285.17:11:16.02#ibcon#read 5, iclass 35, count 0 2006.285.17:11:16.02#ibcon#about to read 6, iclass 35, count 0 2006.285.17:11:16.02#ibcon#read 6, iclass 35, count 0 2006.285.17:11:16.02#ibcon#end of sib2, iclass 35, count 0 2006.285.17:11:16.02#ibcon#*mode == 0, iclass 35, count 0 2006.285.17:11:16.02#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.17:11:16.02#ibcon#[25=USB\r\n] 2006.285.17:11:16.02#ibcon#*before write, iclass 35, count 0 2006.285.17:11:16.02#ibcon#enter sib2, iclass 35, count 0 2006.285.17:11:16.02#ibcon#flushed, iclass 35, count 0 2006.285.17:11:16.02#ibcon#about to write, iclass 35, count 0 2006.285.17:11:16.02#ibcon#wrote, iclass 35, count 0 2006.285.17:11:16.02#ibcon#about to read 3, iclass 35, count 0 2006.285.17:11:16.05#ibcon#read 3, iclass 35, count 0 2006.285.17:11:16.05#ibcon#about to read 4, iclass 35, count 0 2006.285.17:11:16.05#ibcon#read 4, iclass 35, count 0 2006.285.17:11:16.05#ibcon#about to read 5, iclass 35, count 0 2006.285.17:11:16.05#ibcon#read 5, iclass 35, count 0 2006.285.17:11:16.05#ibcon#about to read 6, iclass 35, count 0 2006.285.17:11:16.05#ibcon#read 6, iclass 35, count 0 2006.285.17:11:16.05#ibcon#end of sib2, iclass 35, count 0 2006.285.17:11:16.05#ibcon#*after write, iclass 35, count 0 2006.285.17:11:16.05#ibcon#*before return 0, iclass 35, count 0 2006.285.17:11:16.05#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:11:16.05#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:11:16.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.17:11:16.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.17:11:16.05$vck44/valo=5,734.99 2006.285.17:11:16.05#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.17:11:16.05#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.17:11:16.05#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:16.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:11:16.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:11:16.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:11:16.05#ibcon#enter wrdev, iclass 37, count 0 2006.285.17:11:16.05#ibcon#first serial, iclass 37, count 0 2006.285.17:11:16.05#ibcon#enter sib2, iclass 37, count 0 2006.285.17:11:16.05#ibcon#flushed, iclass 37, count 0 2006.285.17:11:16.05#ibcon#about to write, iclass 37, count 0 2006.285.17:11:16.05#ibcon#wrote, iclass 37, count 0 2006.285.17:11:16.05#ibcon#about to read 3, iclass 37, count 0 2006.285.17:11:16.07#ibcon#read 3, iclass 37, count 0 2006.285.17:11:16.07#ibcon#about to read 4, iclass 37, count 0 2006.285.17:11:16.07#ibcon#read 4, iclass 37, count 0 2006.285.17:11:16.07#ibcon#about to read 5, iclass 37, count 0 2006.285.17:11:16.07#ibcon#read 5, iclass 37, count 0 2006.285.17:11:16.07#ibcon#about to read 6, iclass 37, count 0 2006.285.17:11:16.07#ibcon#read 6, iclass 37, count 0 2006.285.17:11:16.07#ibcon#end of sib2, iclass 37, count 0 2006.285.17:11:16.07#ibcon#*mode == 0, iclass 37, count 0 2006.285.17:11:16.07#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.17:11:16.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.17:11:16.07#ibcon#*before write, iclass 37, count 0 2006.285.17:11:16.07#ibcon#enter sib2, iclass 37, count 0 2006.285.17:11:16.07#ibcon#flushed, iclass 37, count 0 2006.285.17:11:16.07#ibcon#about to write, iclass 37, count 0 2006.285.17:11:16.07#ibcon#wrote, iclass 37, count 0 2006.285.17:11:16.07#ibcon#about to read 3, iclass 37, count 0 2006.285.17:11:16.11#ibcon#read 3, iclass 37, count 0 2006.285.17:11:16.11#ibcon#about to read 4, iclass 37, count 0 2006.285.17:11:16.11#ibcon#read 4, iclass 37, count 0 2006.285.17:11:16.11#ibcon#about to read 5, iclass 37, count 0 2006.285.17:11:16.11#ibcon#read 5, iclass 37, count 0 2006.285.17:11:16.11#ibcon#about to read 6, iclass 37, count 0 2006.285.17:11:16.11#ibcon#read 6, iclass 37, count 0 2006.285.17:11:16.11#ibcon#end of sib2, iclass 37, count 0 2006.285.17:11:16.11#ibcon#*after write, iclass 37, count 0 2006.285.17:11:16.11#ibcon#*before return 0, iclass 37, count 0 2006.285.17:11:16.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:11:16.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:11:16.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.17:11:16.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.17:11:16.11$vck44/va=5,3 2006.285.17:11:16.11#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.17:11:16.11#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.17:11:16.11#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:16.11#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:11:16.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:11:16.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:11:16.17#ibcon#enter wrdev, iclass 39, count 2 2006.285.17:11:16.17#ibcon#first serial, iclass 39, count 2 2006.285.17:11:16.17#ibcon#enter sib2, iclass 39, count 2 2006.285.17:11:16.17#ibcon#flushed, iclass 39, count 2 2006.285.17:11:16.17#ibcon#about to write, iclass 39, count 2 2006.285.17:11:16.17#ibcon#wrote, iclass 39, count 2 2006.285.17:11:16.17#ibcon#about to read 3, iclass 39, count 2 2006.285.17:11:16.19#ibcon#read 3, iclass 39, count 2 2006.285.17:11:16.19#ibcon#about to read 4, iclass 39, count 2 2006.285.17:11:16.19#ibcon#read 4, iclass 39, count 2 2006.285.17:11:16.19#ibcon#about to read 5, iclass 39, count 2 2006.285.17:11:16.19#ibcon#read 5, iclass 39, count 2 2006.285.17:11:16.19#ibcon#about to read 6, iclass 39, count 2 2006.285.17:11:16.19#ibcon#read 6, iclass 39, count 2 2006.285.17:11:16.19#ibcon#end of sib2, iclass 39, count 2 2006.285.17:11:16.19#ibcon#*mode == 0, iclass 39, count 2 2006.285.17:11:16.19#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.17:11:16.19#ibcon#[25=AT05-03\r\n] 2006.285.17:11:16.19#ibcon#*before write, iclass 39, count 2 2006.285.17:11:16.19#ibcon#enter sib2, iclass 39, count 2 2006.285.17:11:16.19#ibcon#flushed, iclass 39, count 2 2006.285.17:11:16.19#ibcon#about to write, iclass 39, count 2 2006.285.17:11:16.19#ibcon#wrote, iclass 39, count 2 2006.285.17:11:16.19#ibcon#about to read 3, iclass 39, count 2 2006.285.17:11:16.22#ibcon#read 3, iclass 39, count 2 2006.285.17:11:16.22#ibcon#about to read 4, iclass 39, count 2 2006.285.17:11:16.22#ibcon#read 4, iclass 39, count 2 2006.285.17:11:16.22#ibcon#about to read 5, iclass 39, count 2 2006.285.17:11:16.22#ibcon#read 5, iclass 39, count 2 2006.285.17:11:16.22#ibcon#about to read 6, iclass 39, count 2 2006.285.17:11:16.22#ibcon#read 6, iclass 39, count 2 2006.285.17:11:16.22#ibcon#end of sib2, iclass 39, count 2 2006.285.17:11:16.22#ibcon#*after write, iclass 39, count 2 2006.285.17:11:16.22#ibcon#*before return 0, iclass 39, count 2 2006.285.17:11:16.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:11:16.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:11:16.22#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.17:11:16.22#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:16.22#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:11:16.34#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:11:16.34#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:11:16.34#ibcon#enter wrdev, iclass 39, count 0 2006.285.17:11:16.34#ibcon#first serial, iclass 39, count 0 2006.285.17:11:16.34#ibcon#enter sib2, iclass 39, count 0 2006.285.17:11:16.34#ibcon#flushed, iclass 39, count 0 2006.285.17:11:16.34#ibcon#about to write, iclass 39, count 0 2006.285.17:11:16.34#ibcon#wrote, iclass 39, count 0 2006.285.17:11:16.34#ibcon#about to read 3, iclass 39, count 0 2006.285.17:11:16.36#ibcon#read 3, iclass 39, count 0 2006.285.17:11:16.36#ibcon#about to read 4, iclass 39, count 0 2006.285.17:11:16.36#ibcon#read 4, iclass 39, count 0 2006.285.17:11:16.36#ibcon#about to read 5, iclass 39, count 0 2006.285.17:11:16.36#ibcon#read 5, iclass 39, count 0 2006.285.17:11:16.36#ibcon#about to read 6, iclass 39, count 0 2006.285.17:11:16.36#ibcon#read 6, iclass 39, count 0 2006.285.17:11:16.36#ibcon#end of sib2, iclass 39, count 0 2006.285.17:11:16.36#ibcon#*mode == 0, iclass 39, count 0 2006.285.17:11:16.36#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.17:11:16.36#ibcon#[25=USB\r\n] 2006.285.17:11:16.36#ibcon#*before write, iclass 39, count 0 2006.285.17:11:16.36#ibcon#enter sib2, iclass 39, count 0 2006.285.17:11:16.36#ibcon#flushed, iclass 39, count 0 2006.285.17:11:16.36#ibcon#about to write, iclass 39, count 0 2006.285.17:11:16.36#ibcon#wrote, iclass 39, count 0 2006.285.17:11:16.36#ibcon#about to read 3, iclass 39, count 0 2006.285.17:11:16.39#ibcon#read 3, iclass 39, count 0 2006.285.17:11:16.39#ibcon#about to read 4, iclass 39, count 0 2006.285.17:11:16.39#ibcon#read 4, iclass 39, count 0 2006.285.17:11:16.39#ibcon#about to read 5, iclass 39, count 0 2006.285.17:11:16.39#ibcon#read 5, iclass 39, count 0 2006.285.17:11:16.39#ibcon#about to read 6, iclass 39, count 0 2006.285.17:11:16.39#ibcon#read 6, iclass 39, count 0 2006.285.17:11:16.39#ibcon#end of sib2, iclass 39, count 0 2006.285.17:11:16.39#ibcon#*after write, iclass 39, count 0 2006.285.17:11:16.39#ibcon#*before return 0, iclass 39, count 0 2006.285.17:11:16.39#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:11:16.39#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:11:16.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.17:11:16.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.17:11:16.39$vck44/valo=6,814.99 2006.285.17:11:16.39#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.17:11:16.39#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.17:11:16.39#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:16.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:11:16.39#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:11:16.39#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:11:16.39#ibcon#enter wrdev, iclass 3, count 0 2006.285.17:11:16.39#ibcon#first serial, iclass 3, count 0 2006.285.17:11:16.39#ibcon#enter sib2, iclass 3, count 0 2006.285.17:11:16.39#ibcon#flushed, iclass 3, count 0 2006.285.17:11:16.39#ibcon#about to write, iclass 3, count 0 2006.285.17:11:16.39#ibcon#wrote, iclass 3, count 0 2006.285.17:11:16.39#ibcon#about to read 3, iclass 3, count 0 2006.285.17:11:16.41#ibcon#read 3, iclass 3, count 0 2006.285.17:11:16.41#ibcon#about to read 4, iclass 3, count 0 2006.285.17:11:16.41#ibcon#read 4, iclass 3, count 0 2006.285.17:11:16.41#ibcon#about to read 5, iclass 3, count 0 2006.285.17:11:16.41#ibcon#read 5, iclass 3, count 0 2006.285.17:11:16.41#ibcon#about to read 6, iclass 3, count 0 2006.285.17:11:16.41#ibcon#read 6, iclass 3, count 0 2006.285.17:11:16.41#ibcon#end of sib2, iclass 3, count 0 2006.285.17:11:16.41#ibcon#*mode == 0, iclass 3, count 0 2006.285.17:11:16.41#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.17:11:16.41#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.17:11:16.41#ibcon#*before write, iclass 3, count 0 2006.285.17:11:16.41#ibcon#enter sib2, iclass 3, count 0 2006.285.17:11:16.41#ibcon#flushed, iclass 3, count 0 2006.285.17:11:16.41#ibcon#about to write, iclass 3, count 0 2006.285.17:11:16.41#ibcon#wrote, iclass 3, count 0 2006.285.17:11:16.41#ibcon#about to read 3, iclass 3, count 0 2006.285.17:11:16.45#ibcon#read 3, iclass 3, count 0 2006.285.17:11:16.45#ibcon#about to read 4, iclass 3, count 0 2006.285.17:11:16.45#ibcon#read 4, iclass 3, count 0 2006.285.17:11:16.45#ibcon#about to read 5, iclass 3, count 0 2006.285.17:11:16.45#ibcon#read 5, iclass 3, count 0 2006.285.17:11:16.45#ibcon#about to read 6, iclass 3, count 0 2006.285.17:11:16.45#ibcon#read 6, iclass 3, count 0 2006.285.17:11:16.45#ibcon#end of sib2, iclass 3, count 0 2006.285.17:11:16.45#ibcon#*after write, iclass 3, count 0 2006.285.17:11:16.45#ibcon#*before return 0, iclass 3, count 0 2006.285.17:11:16.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:11:16.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:11:16.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.17:11:16.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.17:11:16.45$vck44/va=6,4 2006.285.17:11:16.45#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.17:11:16.45#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.17:11:16.45#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:16.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:11:16.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:11:16.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:11:16.51#ibcon#enter wrdev, iclass 5, count 2 2006.285.17:11:16.51#ibcon#first serial, iclass 5, count 2 2006.285.17:11:16.51#ibcon#enter sib2, iclass 5, count 2 2006.285.17:11:16.51#ibcon#flushed, iclass 5, count 2 2006.285.17:11:16.51#ibcon#about to write, iclass 5, count 2 2006.285.17:11:16.51#ibcon#wrote, iclass 5, count 2 2006.285.17:11:16.51#ibcon#about to read 3, iclass 5, count 2 2006.285.17:11:16.53#ibcon#read 3, iclass 5, count 2 2006.285.17:11:16.53#ibcon#about to read 4, iclass 5, count 2 2006.285.17:11:16.53#ibcon#read 4, iclass 5, count 2 2006.285.17:11:16.53#ibcon#about to read 5, iclass 5, count 2 2006.285.17:11:16.53#ibcon#read 5, iclass 5, count 2 2006.285.17:11:16.53#ibcon#about to read 6, iclass 5, count 2 2006.285.17:11:16.53#ibcon#read 6, iclass 5, count 2 2006.285.17:11:16.53#ibcon#end of sib2, iclass 5, count 2 2006.285.17:11:16.53#ibcon#*mode == 0, iclass 5, count 2 2006.285.17:11:16.53#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.17:11:16.53#ibcon#[25=AT06-04\r\n] 2006.285.17:11:16.53#ibcon#*before write, iclass 5, count 2 2006.285.17:11:16.53#ibcon#enter sib2, iclass 5, count 2 2006.285.17:11:16.53#ibcon#flushed, iclass 5, count 2 2006.285.17:11:16.53#ibcon#about to write, iclass 5, count 2 2006.285.17:11:16.53#ibcon#wrote, iclass 5, count 2 2006.285.17:11:16.53#ibcon#about to read 3, iclass 5, count 2 2006.285.17:11:16.56#ibcon#read 3, iclass 5, count 2 2006.285.17:11:16.56#ibcon#about to read 4, iclass 5, count 2 2006.285.17:11:16.56#ibcon#read 4, iclass 5, count 2 2006.285.17:11:16.56#ibcon#about to read 5, iclass 5, count 2 2006.285.17:11:16.56#ibcon#read 5, iclass 5, count 2 2006.285.17:11:16.56#ibcon#about to read 6, iclass 5, count 2 2006.285.17:11:16.56#ibcon#read 6, iclass 5, count 2 2006.285.17:11:16.56#ibcon#end of sib2, iclass 5, count 2 2006.285.17:11:16.56#ibcon#*after write, iclass 5, count 2 2006.285.17:11:16.56#ibcon#*before return 0, iclass 5, count 2 2006.285.17:11:16.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:11:16.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:11:16.56#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.17:11:16.56#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:16.56#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:11:16.68#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:11:16.68#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:11:16.68#ibcon#enter wrdev, iclass 5, count 0 2006.285.17:11:16.68#ibcon#first serial, iclass 5, count 0 2006.285.17:11:16.68#ibcon#enter sib2, iclass 5, count 0 2006.285.17:11:16.68#ibcon#flushed, iclass 5, count 0 2006.285.17:11:16.68#ibcon#about to write, iclass 5, count 0 2006.285.17:11:16.68#ibcon#wrote, iclass 5, count 0 2006.285.17:11:16.68#ibcon#about to read 3, iclass 5, count 0 2006.285.17:11:16.70#ibcon#read 3, iclass 5, count 0 2006.285.17:11:16.70#ibcon#about to read 4, iclass 5, count 0 2006.285.17:11:16.70#ibcon#read 4, iclass 5, count 0 2006.285.17:11:16.70#ibcon#about to read 5, iclass 5, count 0 2006.285.17:11:16.70#ibcon#read 5, iclass 5, count 0 2006.285.17:11:16.70#ibcon#about to read 6, iclass 5, count 0 2006.285.17:11:16.70#ibcon#read 6, iclass 5, count 0 2006.285.17:11:16.70#ibcon#end of sib2, iclass 5, count 0 2006.285.17:11:16.70#ibcon#*mode == 0, iclass 5, count 0 2006.285.17:11:16.70#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.17:11:16.70#ibcon#[25=USB\r\n] 2006.285.17:11:16.70#ibcon#*before write, iclass 5, count 0 2006.285.17:11:16.70#ibcon#enter sib2, iclass 5, count 0 2006.285.17:11:16.70#ibcon#flushed, iclass 5, count 0 2006.285.17:11:16.70#ibcon#about to write, iclass 5, count 0 2006.285.17:11:16.70#ibcon#wrote, iclass 5, count 0 2006.285.17:11:16.70#ibcon#about to read 3, iclass 5, count 0 2006.285.17:11:16.73#ibcon#read 3, iclass 5, count 0 2006.285.17:11:16.73#ibcon#about to read 4, iclass 5, count 0 2006.285.17:11:16.73#ibcon#read 4, iclass 5, count 0 2006.285.17:11:16.73#ibcon#about to read 5, iclass 5, count 0 2006.285.17:11:16.73#ibcon#read 5, iclass 5, count 0 2006.285.17:11:16.73#ibcon#about to read 6, iclass 5, count 0 2006.285.17:11:16.73#ibcon#read 6, iclass 5, count 0 2006.285.17:11:16.73#ibcon#end of sib2, iclass 5, count 0 2006.285.17:11:16.73#ibcon#*after write, iclass 5, count 0 2006.285.17:11:16.73#ibcon#*before return 0, iclass 5, count 0 2006.285.17:11:16.73#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:11:16.73#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:11:16.73#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.17:11:16.73#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.17:11:16.73$vck44/valo=7,864.99 2006.285.17:11:16.73#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.17:11:16.73#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.17:11:16.73#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:16.73#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:11:16.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:11:16.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:11:16.73#ibcon#enter wrdev, iclass 7, count 0 2006.285.17:11:16.73#ibcon#first serial, iclass 7, count 0 2006.285.17:11:16.73#ibcon#enter sib2, iclass 7, count 0 2006.285.17:11:16.73#ibcon#flushed, iclass 7, count 0 2006.285.17:11:16.73#ibcon#about to write, iclass 7, count 0 2006.285.17:11:16.73#ibcon#wrote, iclass 7, count 0 2006.285.17:11:16.73#ibcon#about to read 3, iclass 7, count 0 2006.285.17:11:16.80#ibcon#read 3, iclass 7, count 0 2006.285.17:11:16.80#ibcon#about to read 4, iclass 7, count 0 2006.285.17:11:16.80#ibcon#read 4, iclass 7, count 0 2006.285.17:11:16.80#ibcon#about to read 5, iclass 7, count 0 2006.285.17:11:16.80#ibcon#read 5, iclass 7, count 0 2006.285.17:11:16.80#ibcon#about to read 6, iclass 7, count 0 2006.285.17:11:16.80#ibcon#read 6, iclass 7, count 0 2006.285.17:11:16.80#ibcon#end of sib2, iclass 7, count 0 2006.285.17:11:16.80#ibcon#*mode == 0, iclass 7, count 0 2006.285.17:11:16.80#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.17:11:16.80#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.17:11:16.80#ibcon#*before write, iclass 7, count 0 2006.285.17:11:16.80#ibcon#enter sib2, iclass 7, count 0 2006.285.17:11:16.80#ibcon#flushed, iclass 7, count 0 2006.285.17:11:16.80#ibcon#about to write, iclass 7, count 0 2006.285.17:11:16.80#ibcon#wrote, iclass 7, count 0 2006.285.17:11:16.80#ibcon#about to read 3, iclass 7, count 0 2006.285.17:11:16.83#ibcon#read 3, iclass 7, count 0 2006.285.17:11:16.83#ibcon#about to read 4, iclass 7, count 0 2006.285.17:11:16.83#ibcon#read 4, iclass 7, count 0 2006.285.17:11:16.83#ibcon#about to read 5, iclass 7, count 0 2006.285.17:11:16.83#ibcon#read 5, iclass 7, count 0 2006.285.17:11:16.83#ibcon#about to read 6, iclass 7, count 0 2006.285.17:11:16.83#ibcon#read 6, iclass 7, count 0 2006.285.17:11:16.83#ibcon#end of sib2, iclass 7, count 0 2006.285.17:11:16.83#ibcon#*after write, iclass 7, count 0 2006.285.17:11:16.83#ibcon#*before return 0, iclass 7, count 0 2006.285.17:11:16.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:11:16.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:11:16.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.17:11:16.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.17:11:16.83$vck44/va=7,4 2006.285.17:11:16.83#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.17:11:16.83#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.17:11:16.83#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:16.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:11:16.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:11:16.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:11:16.85#ibcon#enter wrdev, iclass 11, count 2 2006.285.17:11:16.85#ibcon#first serial, iclass 11, count 2 2006.285.17:11:16.85#ibcon#enter sib2, iclass 11, count 2 2006.285.17:11:16.85#ibcon#flushed, iclass 11, count 2 2006.285.17:11:16.85#ibcon#about to write, iclass 11, count 2 2006.285.17:11:16.85#ibcon#wrote, iclass 11, count 2 2006.285.17:11:16.85#ibcon#about to read 3, iclass 11, count 2 2006.285.17:11:16.87#ibcon#read 3, iclass 11, count 2 2006.285.17:11:16.87#ibcon#about to read 4, iclass 11, count 2 2006.285.17:11:16.87#ibcon#read 4, iclass 11, count 2 2006.285.17:11:16.87#ibcon#about to read 5, iclass 11, count 2 2006.285.17:11:16.87#ibcon#read 5, iclass 11, count 2 2006.285.17:11:16.87#ibcon#about to read 6, iclass 11, count 2 2006.285.17:11:16.87#ibcon#read 6, iclass 11, count 2 2006.285.17:11:16.87#ibcon#end of sib2, iclass 11, count 2 2006.285.17:11:16.87#ibcon#*mode == 0, iclass 11, count 2 2006.285.17:11:16.87#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.17:11:16.87#ibcon#[25=AT07-04\r\n] 2006.285.17:11:16.87#ibcon#*before write, iclass 11, count 2 2006.285.17:11:16.87#ibcon#enter sib2, iclass 11, count 2 2006.285.17:11:16.87#ibcon#flushed, iclass 11, count 2 2006.285.17:11:16.87#ibcon#about to write, iclass 11, count 2 2006.285.17:11:16.87#ibcon#wrote, iclass 11, count 2 2006.285.17:11:16.87#ibcon#about to read 3, iclass 11, count 2 2006.285.17:11:16.90#ibcon#read 3, iclass 11, count 2 2006.285.17:11:16.90#ibcon#about to read 4, iclass 11, count 2 2006.285.17:11:16.90#ibcon#read 4, iclass 11, count 2 2006.285.17:11:16.90#ibcon#about to read 5, iclass 11, count 2 2006.285.17:11:16.90#ibcon#read 5, iclass 11, count 2 2006.285.17:11:16.90#ibcon#about to read 6, iclass 11, count 2 2006.285.17:11:16.90#ibcon#read 6, iclass 11, count 2 2006.285.17:11:16.90#ibcon#end of sib2, iclass 11, count 2 2006.285.17:11:16.90#ibcon#*after write, iclass 11, count 2 2006.285.17:11:16.90#ibcon#*before return 0, iclass 11, count 2 2006.285.17:11:16.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:11:16.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:11:16.90#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.17:11:16.90#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:16.90#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:11:17.02#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:11:17.02#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:11:17.02#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:11:17.02#ibcon#first serial, iclass 11, count 0 2006.285.17:11:17.02#ibcon#enter sib2, iclass 11, count 0 2006.285.17:11:17.02#ibcon#flushed, iclass 11, count 0 2006.285.17:11:17.02#ibcon#about to write, iclass 11, count 0 2006.285.17:11:17.02#ibcon#wrote, iclass 11, count 0 2006.285.17:11:17.02#ibcon#about to read 3, iclass 11, count 0 2006.285.17:11:17.04#ibcon#read 3, iclass 11, count 0 2006.285.17:11:17.04#ibcon#about to read 4, iclass 11, count 0 2006.285.17:11:17.04#ibcon#read 4, iclass 11, count 0 2006.285.17:11:17.04#ibcon#about to read 5, iclass 11, count 0 2006.285.17:11:17.04#ibcon#read 5, iclass 11, count 0 2006.285.17:11:17.04#ibcon#about to read 6, iclass 11, count 0 2006.285.17:11:17.04#ibcon#read 6, iclass 11, count 0 2006.285.17:11:17.04#ibcon#end of sib2, iclass 11, count 0 2006.285.17:11:17.04#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:11:17.04#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:11:17.04#ibcon#[25=USB\r\n] 2006.285.17:11:17.04#ibcon#*before write, iclass 11, count 0 2006.285.17:11:17.04#ibcon#enter sib2, iclass 11, count 0 2006.285.17:11:17.04#ibcon#flushed, iclass 11, count 0 2006.285.17:11:17.04#ibcon#about to write, iclass 11, count 0 2006.285.17:11:17.04#ibcon#wrote, iclass 11, count 0 2006.285.17:11:17.04#ibcon#about to read 3, iclass 11, count 0 2006.285.17:11:17.07#ibcon#read 3, iclass 11, count 0 2006.285.17:11:17.07#ibcon#about to read 4, iclass 11, count 0 2006.285.17:11:17.07#ibcon#read 4, iclass 11, count 0 2006.285.17:11:17.07#ibcon#about to read 5, iclass 11, count 0 2006.285.17:11:17.07#ibcon#read 5, iclass 11, count 0 2006.285.17:11:17.07#ibcon#about to read 6, iclass 11, count 0 2006.285.17:11:17.07#ibcon#read 6, iclass 11, count 0 2006.285.17:11:17.07#ibcon#end of sib2, iclass 11, count 0 2006.285.17:11:17.07#ibcon#*after write, iclass 11, count 0 2006.285.17:11:17.07#ibcon#*before return 0, iclass 11, count 0 2006.285.17:11:17.07#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:11:17.07#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:11:17.07#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:11:17.07#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:11:17.07$vck44/valo=8,884.99 2006.285.17:11:17.07#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.17:11:17.07#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.17:11:17.07#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:17.07#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:11:17.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:11:17.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:11:17.07#ibcon#enter wrdev, iclass 13, count 0 2006.285.17:11:17.07#ibcon#first serial, iclass 13, count 0 2006.285.17:11:17.07#ibcon#enter sib2, iclass 13, count 0 2006.285.17:11:17.07#ibcon#flushed, iclass 13, count 0 2006.285.17:11:17.07#ibcon#about to write, iclass 13, count 0 2006.285.17:11:17.07#ibcon#wrote, iclass 13, count 0 2006.285.17:11:17.07#ibcon#about to read 3, iclass 13, count 0 2006.285.17:11:17.09#ibcon#read 3, iclass 13, count 0 2006.285.17:11:17.09#ibcon#about to read 4, iclass 13, count 0 2006.285.17:11:17.09#ibcon#read 4, iclass 13, count 0 2006.285.17:11:17.09#ibcon#about to read 5, iclass 13, count 0 2006.285.17:11:17.09#ibcon#read 5, iclass 13, count 0 2006.285.17:11:17.09#ibcon#about to read 6, iclass 13, count 0 2006.285.17:11:17.09#ibcon#read 6, iclass 13, count 0 2006.285.17:11:17.09#ibcon#end of sib2, iclass 13, count 0 2006.285.17:11:17.09#ibcon#*mode == 0, iclass 13, count 0 2006.285.17:11:17.09#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.17:11:17.09#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.17:11:17.09#ibcon#*before write, iclass 13, count 0 2006.285.17:11:17.09#ibcon#enter sib2, iclass 13, count 0 2006.285.17:11:17.09#ibcon#flushed, iclass 13, count 0 2006.285.17:11:17.09#ibcon#about to write, iclass 13, count 0 2006.285.17:11:17.09#ibcon#wrote, iclass 13, count 0 2006.285.17:11:17.09#ibcon#about to read 3, iclass 13, count 0 2006.285.17:11:17.13#ibcon#read 3, iclass 13, count 0 2006.285.17:11:17.13#ibcon#about to read 4, iclass 13, count 0 2006.285.17:11:17.13#ibcon#read 4, iclass 13, count 0 2006.285.17:11:17.13#ibcon#about to read 5, iclass 13, count 0 2006.285.17:11:17.13#ibcon#read 5, iclass 13, count 0 2006.285.17:11:17.13#ibcon#about to read 6, iclass 13, count 0 2006.285.17:11:17.13#ibcon#read 6, iclass 13, count 0 2006.285.17:11:17.13#ibcon#end of sib2, iclass 13, count 0 2006.285.17:11:17.13#ibcon#*after write, iclass 13, count 0 2006.285.17:11:17.13#ibcon#*before return 0, iclass 13, count 0 2006.285.17:11:17.13#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:11:17.13#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:11:17.13#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.17:11:17.13#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.17:11:17.13$vck44/va=8,3 2006.285.17:11:17.13#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.17:11:17.13#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.17:11:17.13#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:17.13#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:11:17.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:11:17.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:11:17.19#ibcon#enter wrdev, iclass 15, count 2 2006.285.17:11:17.19#ibcon#first serial, iclass 15, count 2 2006.285.17:11:17.19#ibcon#enter sib2, iclass 15, count 2 2006.285.17:11:17.19#ibcon#flushed, iclass 15, count 2 2006.285.17:11:17.19#ibcon#about to write, iclass 15, count 2 2006.285.17:11:17.19#ibcon#wrote, iclass 15, count 2 2006.285.17:11:17.19#ibcon#about to read 3, iclass 15, count 2 2006.285.17:11:17.21#ibcon#read 3, iclass 15, count 2 2006.285.17:11:17.21#ibcon#about to read 4, iclass 15, count 2 2006.285.17:11:17.21#ibcon#read 4, iclass 15, count 2 2006.285.17:11:17.21#ibcon#about to read 5, iclass 15, count 2 2006.285.17:11:17.21#ibcon#read 5, iclass 15, count 2 2006.285.17:11:17.21#ibcon#about to read 6, iclass 15, count 2 2006.285.17:11:17.21#ibcon#read 6, iclass 15, count 2 2006.285.17:11:17.21#ibcon#end of sib2, iclass 15, count 2 2006.285.17:11:17.21#ibcon#*mode == 0, iclass 15, count 2 2006.285.17:11:17.21#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.17:11:17.21#ibcon#[25=AT08-03\r\n] 2006.285.17:11:17.21#ibcon#*before write, iclass 15, count 2 2006.285.17:11:17.21#ibcon#enter sib2, iclass 15, count 2 2006.285.17:11:17.21#ibcon#flushed, iclass 15, count 2 2006.285.17:11:17.21#ibcon#about to write, iclass 15, count 2 2006.285.17:11:17.21#ibcon#wrote, iclass 15, count 2 2006.285.17:11:17.21#ibcon#about to read 3, iclass 15, count 2 2006.285.17:11:17.24#ibcon#read 3, iclass 15, count 2 2006.285.17:11:17.24#ibcon#about to read 4, iclass 15, count 2 2006.285.17:11:17.24#ibcon#read 4, iclass 15, count 2 2006.285.17:11:17.24#ibcon#about to read 5, iclass 15, count 2 2006.285.17:11:17.24#ibcon#read 5, iclass 15, count 2 2006.285.17:11:17.24#ibcon#about to read 6, iclass 15, count 2 2006.285.17:11:17.24#ibcon#read 6, iclass 15, count 2 2006.285.17:11:17.24#ibcon#end of sib2, iclass 15, count 2 2006.285.17:11:17.24#ibcon#*after write, iclass 15, count 2 2006.285.17:11:17.24#ibcon#*before return 0, iclass 15, count 2 2006.285.17:11:17.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:11:17.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:11:17.24#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.17:11:17.24#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:17.24#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:11:17.36#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:11:17.36#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:11:17.36#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:11:17.36#ibcon#first serial, iclass 15, count 0 2006.285.17:11:17.36#ibcon#enter sib2, iclass 15, count 0 2006.285.17:11:17.36#ibcon#flushed, iclass 15, count 0 2006.285.17:11:17.36#ibcon#about to write, iclass 15, count 0 2006.285.17:11:17.36#ibcon#wrote, iclass 15, count 0 2006.285.17:11:17.36#ibcon#about to read 3, iclass 15, count 0 2006.285.17:11:17.38#ibcon#read 3, iclass 15, count 0 2006.285.17:11:17.38#ibcon#about to read 4, iclass 15, count 0 2006.285.17:11:17.38#ibcon#read 4, iclass 15, count 0 2006.285.17:11:17.38#ibcon#about to read 5, iclass 15, count 0 2006.285.17:11:17.38#ibcon#read 5, iclass 15, count 0 2006.285.17:11:17.38#ibcon#about to read 6, iclass 15, count 0 2006.285.17:11:17.38#ibcon#read 6, iclass 15, count 0 2006.285.17:11:17.38#ibcon#end of sib2, iclass 15, count 0 2006.285.17:11:17.38#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:11:17.38#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:11:17.38#ibcon#[25=USB\r\n] 2006.285.17:11:17.38#ibcon#*before write, iclass 15, count 0 2006.285.17:11:17.38#ibcon#enter sib2, iclass 15, count 0 2006.285.17:11:17.38#ibcon#flushed, iclass 15, count 0 2006.285.17:11:17.38#ibcon#about to write, iclass 15, count 0 2006.285.17:11:17.38#ibcon#wrote, iclass 15, count 0 2006.285.17:11:17.38#ibcon#about to read 3, iclass 15, count 0 2006.285.17:11:17.41#ibcon#read 3, iclass 15, count 0 2006.285.17:11:17.41#ibcon#about to read 4, iclass 15, count 0 2006.285.17:11:17.41#ibcon#read 4, iclass 15, count 0 2006.285.17:11:17.41#ibcon#about to read 5, iclass 15, count 0 2006.285.17:11:17.41#ibcon#read 5, iclass 15, count 0 2006.285.17:11:17.41#ibcon#about to read 6, iclass 15, count 0 2006.285.17:11:17.41#ibcon#read 6, iclass 15, count 0 2006.285.17:11:17.41#ibcon#end of sib2, iclass 15, count 0 2006.285.17:11:17.41#ibcon#*after write, iclass 15, count 0 2006.285.17:11:17.41#ibcon#*before return 0, iclass 15, count 0 2006.285.17:11:17.41#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:11:17.41#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:11:17.41#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:11:17.41#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:11:17.41$vck44/vblo=1,629.99 2006.285.17:11:17.41#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.17:11:17.41#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.17:11:17.41#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:17.41#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:11:17.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:11:17.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:11:17.41#ibcon#enter wrdev, iclass 17, count 0 2006.285.17:11:17.41#ibcon#first serial, iclass 17, count 0 2006.285.17:11:17.41#ibcon#enter sib2, iclass 17, count 0 2006.285.17:11:17.41#ibcon#flushed, iclass 17, count 0 2006.285.17:11:17.41#ibcon#about to write, iclass 17, count 0 2006.285.17:11:17.41#ibcon#wrote, iclass 17, count 0 2006.285.17:11:17.41#ibcon#about to read 3, iclass 17, count 0 2006.285.17:11:17.43#ibcon#read 3, iclass 17, count 0 2006.285.17:11:17.43#ibcon#about to read 4, iclass 17, count 0 2006.285.17:11:17.43#ibcon#read 4, iclass 17, count 0 2006.285.17:11:17.43#ibcon#about to read 5, iclass 17, count 0 2006.285.17:11:17.43#ibcon#read 5, iclass 17, count 0 2006.285.17:11:17.43#ibcon#about to read 6, iclass 17, count 0 2006.285.17:11:17.43#ibcon#read 6, iclass 17, count 0 2006.285.17:11:17.43#ibcon#end of sib2, iclass 17, count 0 2006.285.17:11:17.43#ibcon#*mode == 0, iclass 17, count 0 2006.285.17:11:17.43#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.17:11:17.43#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.17:11:17.43#ibcon#*before write, iclass 17, count 0 2006.285.17:11:17.43#ibcon#enter sib2, iclass 17, count 0 2006.285.17:11:17.43#ibcon#flushed, iclass 17, count 0 2006.285.17:11:17.43#ibcon#about to write, iclass 17, count 0 2006.285.17:11:17.43#ibcon#wrote, iclass 17, count 0 2006.285.17:11:17.43#ibcon#about to read 3, iclass 17, count 0 2006.285.17:11:17.47#ibcon#read 3, iclass 17, count 0 2006.285.17:11:17.47#ibcon#about to read 4, iclass 17, count 0 2006.285.17:11:17.47#ibcon#read 4, iclass 17, count 0 2006.285.17:11:17.47#ibcon#about to read 5, iclass 17, count 0 2006.285.17:11:17.47#ibcon#read 5, iclass 17, count 0 2006.285.17:11:17.47#ibcon#about to read 6, iclass 17, count 0 2006.285.17:11:17.47#ibcon#read 6, iclass 17, count 0 2006.285.17:11:17.47#ibcon#end of sib2, iclass 17, count 0 2006.285.17:11:17.47#ibcon#*after write, iclass 17, count 0 2006.285.17:11:17.47#ibcon#*before return 0, iclass 17, count 0 2006.285.17:11:17.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:11:17.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:11:17.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.17:11:17.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.17:11:17.47$vck44/vb=1,4 2006.285.17:11:17.47#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.17:11:17.47#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.17:11:17.47#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:17.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:11:17.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:11:17.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:11:17.47#ibcon#enter wrdev, iclass 19, count 2 2006.285.17:11:17.47#ibcon#first serial, iclass 19, count 2 2006.285.17:11:17.47#ibcon#enter sib2, iclass 19, count 2 2006.285.17:11:17.47#ibcon#flushed, iclass 19, count 2 2006.285.17:11:17.47#ibcon#about to write, iclass 19, count 2 2006.285.17:11:17.47#ibcon#wrote, iclass 19, count 2 2006.285.17:11:17.47#ibcon#about to read 3, iclass 19, count 2 2006.285.17:11:17.49#ibcon#read 3, iclass 19, count 2 2006.285.17:11:17.49#ibcon#about to read 4, iclass 19, count 2 2006.285.17:11:17.49#ibcon#read 4, iclass 19, count 2 2006.285.17:11:17.49#ibcon#about to read 5, iclass 19, count 2 2006.285.17:11:17.49#ibcon#read 5, iclass 19, count 2 2006.285.17:11:17.49#ibcon#about to read 6, iclass 19, count 2 2006.285.17:11:17.49#ibcon#read 6, iclass 19, count 2 2006.285.17:11:17.49#ibcon#end of sib2, iclass 19, count 2 2006.285.17:11:17.49#ibcon#*mode == 0, iclass 19, count 2 2006.285.17:11:17.49#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.17:11:17.49#ibcon#[27=AT01-04\r\n] 2006.285.17:11:17.49#ibcon#*before write, iclass 19, count 2 2006.285.17:11:17.49#ibcon#enter sib2, iclass 19, count 2 2006.285.17:11:17.49#ibcon#flushed, iclass 19, count 2 2006.285.17:11:17.49#ibcon#about to write, iclass 19, count 2 2006.285.17:11:17.49#ibcon#wrote, iclass 19, count 2 2006.285.17:11:17.49#ibcon#about to read 3, iclass 19, count 2 2006.285.17:11:17.52#ibcon#read 3, iclass 19, count 2 2006.285.17:11:17.52#ibcon#about to read 4, iclass 19, count 2 2006.285.17:11:17.52#ibcon#read 4, iclass 19, count 2 2006.285.17:11:17.52#ibcon#about to read 5, iclass 19, count 2 2006.285.17:11:17.52#ibcon#read 5, iclass 19, count 2 2006.285.17:11:17.52#ibcon#about to read 6, iclass 19, count 2 2006.285.17:11:17.52#ibcon#read 6, iclass 19, count 2 2006.285.17:11:17.52#ibcon#end of sib2, iclass 19, count 2 2006.285.17:11:17.52#ibcon#*after write, iclass 19, count 2 2006.285.17:11:17.52#ibcon#*before return 0, iclass 19, count 2 2006.285.17:11:17.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:11:17.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:11:17.52#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.17:11:17.52#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:17.52#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:11:17.64#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:11:17.64#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:11:17.64#ibcon#enter wrdev, iclass 19, count 0 2006.285.17:11:17.64#ibcon#first serial, iclass 19, count 0 2006.285.17:11:17.64#ibcon#enter sib2, iclass 19, count 0 2006.285.17:11:17.64#ibcon#flushed, iclass 19, count 0 2006.285.17:11:17.64#ibcon#about to write, iclass 19, count 0 2006.285.17:11:17.64#ibcon#wrote, iclass 19, count 0 2006.285.17:11:17.64#ibcon#about to read 3, iclass 19, count 0 2006.285.17:11:17.66#ibcon#read 3, iclass 19, count 0 2006.285.17:11:17.66#ibcon#about to read 4, iclass 19, count 0 2006.285.17:11:17.66#ibcon#read 4, iclass 19, count 0 2006.285.17:11:17.66#ibcon#about to read 5, iclass 19, count 0 2006.285.17:11:17.66#ibcon#read 5, iclass 19, count 0 2006.285.17:11:17.66#ibcon#about to read 6, iclass 19, count 0 2006.285.17:11:17.66#ibcon#read 6, iclass 19, count 0 2006.285.17:11:17.66#ibcon#end of sib2, iclass 19, count 0 2006.285.17:11:17.66#ibcon#*mode == 0, iclass 19, count 0 2006.285.17:11:17.66#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.17:11:17.66#ibcon#[27=USB\r\n] 2006.285.17:11:17.66#ibcon#*before write, iclass 19, count 0 2006.285.17:11:17.66#ibcon#enter sib2, iclass 19, count 0 2006.285.17:11:17.66#ibcon#flushed, iclass 19, count 0 2006.285.17:11:17.66#ibcon#about to write, iclass 19, count 0 2006.285.17:11:17.66#ibcon#wrote, iclass 19, count 0 2006.285.17:11:17.66#ibcon#about to read 3, iclass 19, count 0 2006.285.17:11:17.69#ibcon#read 3, iclass 19, count 0 2006.285.17:11:17.69#ibcon#about to read 4, iclass 19, count 0 2006.285.17:11:17.69#ibcon#read 4, iclass 19, count 0 2006.285.17:11:17.69#ibcon#about to read 5, iclass 19, count 0 2006.285.17:11:17.69#ibcon#read 5, iclass 19, count 0 2006.285.17:11:17.69#ibcon#about to read 6, iclass 19, count 0 2006.285.17:11:17.69#ibcon#read 6, iclass 19, count 0 2006.285.17:11:17.69#ibcon#end of sib2, iclass 19, count 0 2006.285.17:11:17.69#ibcon#*after write, iclass 19, count 0 2006.285.17:11:17.69#ibcon#*before return 0, iclass 19, count 0 2006.285.17:11:17.69#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:11:17.69#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:11:17.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.17:11:17.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.17:11:17.69$vck44/vblo=2,634.99 2006.285.17:11:17.69#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.17:11:17.69#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.17:11:17.69#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:17.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:11:17.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:11:17.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:11:17.69#ibcon#enter wrdev, iclass 21, count 0 2006.285.17:11:17.69#ibcon#first serial, iclass 21, count 0 2006.285.17:11:17.69#ibcon#enter sib2, iclass 21, count 0 2006.285.17:11:17.69#ibcon#flushed, iclass 21, count 0 2006.285.17:11:17.69#ibcon#about to write, iclass 21, count 0 2006.285.17:11:17.69#ibcon#wrote, iclass 21, count 0 2006.285.17:11:17.69#ibcon#about to read 3, iclass 21, count 0 2006.285.17:11:17.71#ibcon#read 3, iclass 21, count 0 2006.285.17:11:17.88#ibcon#about to read 4, iclass 21, count 0 2006.285.17:11:17.88#ibcon#read 4, iclass 21, count 0 2006.285.17:11:17.88#ibcon#about to read 5, iclass 21, count 0 2006.285.17:11:17.88#ibcon#read 5, iclass 21, count 0 2006.285.17:11:17.88#ibcon#about to read 6, iclass 21, count 0 2006.285.17:11:17.88#ibcon#read 6, iclass 21, count 0 2006.285.17:11:17.88#ibcon#end of sib2, iclass 21, count 0 2006.285.17:11:17.88#ibcon#*mode == 0, iclass 21, count 0 2006.285.17:11:17.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.17:11:17.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.17:11:17.88#ibcon#*before write, iclass 21, count 0 2006.285.17:11:17.88#ibcon#enter sib2, iclass 21, count 0 2006.285.17:11:17.88#ibcon#flushed, iclass 21, count 0 2006.285.17:11:17.88#ibcon#about to write, iclass 21, count 0 2006.285.17:11:17.88#ibcon#wrote, iclass 21, count 0 2006.285.17:11:17.88#ibcon#about to read 3, iclass 21, count 0 2006.285.17:11:17.91#ibcon#read 3, iclass 21, count 0 2006.285.17:11:17.91#ibcon#about to read 4, iclass 21, count 0 2006.285.17:11:17.91#ibcon#read 4, iclass 21, count 0 2006.285.17:11:17.91#ibcon#about to read 5, iclass 21, count 0 2006.285.17:11:17.91#ibcon#read 5, iclass 21, count 0 2006.285.17:11:17.91#ibcon#about to read 6, iclass 21, count 0 2006.285.17:11:17.91#ibcon#read 6, iclass 21, count 0 2006.285.17:11:17.91#ibcon#end of sib2, iclass 21, count 0 2006.285.17:11:17.91#ibcon#*after write, iclass 21, count 0 2006.285.17:11:17.91#ibcon#*before return 0, iclass 21, count 0 2006.285.17:11:17.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:11:17.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:11:17.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.17:11:17.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.17:11:17.91$vck44/vb=2,5 2006.285.17:11:17.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.17:11:17.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.17:11:17.91#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:17.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:11:17.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:11:17.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:11:17.91#ibcon#enter wrdev, iclass 23, count 2 2006.285.17:11:17.91#ibcon#first serial, iclass 23, count 2 2006.285.17:11:17.91#ibcon#enter sib2, iclass 23, count 2 2006.285.17:11:17.91#ibcon#flushed, iclass 23, count 2 2006.285.17:11:17.91#ibcon#about to write, iclass 23, count 2 2006.285.17:11:17.91#ibcon#wrote, iclass 23, count 2 2006.285.17:11:17.91#ibcon#about to read 3, iclass 23, count 2 2006.285.17:11:17.93#ibcon#read 3, iclass 23, count 2 2006.285.17:11:17.93#ibcon#about to read 4, iclass 23, count 2 2006.285.17:11:17.93#ibcon#read 4, iclass 23, count 2 2006.285.17:11:17.93#ibcon#about to read 5, iclass 23, count 2 2006.285.17:11:17.93#ibcon#read 5, iclass 23, count 2 2006.285.17:11:17.93#ibcon#about to read 6, iclass 23, count 2 2006.285.17:11:17.93#ibcon#read 6, iclass 23, count 2 2006.285.17:11:17.93#ibcon#end of sib2, iclass 23, count 2 2006.285.17:11:17.93#ibcon#*mode == 0, iclass 23, count 2 2006.285.17:11:17.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.17:11:17.93#ibcon#[27=AT02-05\r\n] 2006.285.17:11:17.93#ibcon#*before write, iclass 23, count 2 2006.285.17:11:17.93#ibcon#enter sib2, iclass 23, count 2 2006.285.17:11:17.93#ibcon#flushed, iclass 23, count 2 2006.285.17:11:17.93#ibcon#about to write, iclass 23, count 2 2006.285.17:11:17.93#ibcon#wrote, iclass 23, count 2 2006.285.17:11:17.93#ibcon#about to read 3, iclass 23, count 2 2006.285.17:11:17.96#ibcon#read 3, iclass 23, count 2 2006.285.17:11:17.96#ibcon#about to read 4, iclass 23, count 2 2006.285.17:11:17.96#ibcon#read 4, iclass 23, count 2 2006.285.17:11:17.96#ibcon#about to read 5, iclass 23, count 2 2006.285.17:11:17.96#ibcon#read 5, iclass 23, count 2 2006.285.17:11:17.96#ibcon#about to read 6, iclass 23, count 2 2006.285.17:11:17.96#ibcon#read 6, iclass 23, count 2 2006.285.17:11:17.96#ibcon#end of sib2, iclass 23, count 2 2006.285.17:11:17.96#ibcon#*after write, iclass 23, count 2 2006.285.17:11:17.96#ibcon#*before return 0, iclass 23, count 2 2006.285.17:11:17.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:11:17.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:11:17.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.17:11:17.96#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:17.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:11:18.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:11:18.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:11:18.08#ibcon#enter wrdev, iclass 23, count 0 2006.285.17:11:18.08#ibcon#first serial, iclass 23, count 0 2006.285.17:11:18.08#ibcon#enter sib2, iclass 23, count 0 2006.285.17:11:18.08#ibcon#flushed, iclass 23, count 0 2006.285.17:11:18.08#ibcon#about to write, iclass 23, count 0 2006.285.17:11:18.08#ibcon#wrote, iclass 23, count 0 2006.285.17:11:18.08#ibcon#about to read 3, iclass 23, count 0 2006.285.17:11:18.10#ibcon#read 3, iclass 23, count 0 2006.285.17:11:18.10#ibcon#about to read 4, iclass 23, count 0 2006.285.17:11:18.10#ibcon#read 4, iclass 23, count 0 2006.285.17:11:18.10#ibcon#about to read 5, iclass 23, count 0 2006.285.17:11:18.10#ibcon#read 5, iclass 23, count 0 2006.285.17:11:18.10#ibcon#about to read 6, iclass 23, count 0 2006.285.17:11:18.10#ibcon#read 6, iclass 23, count 0 2006.285.17:11:18.10#ibcon#end of sib2, iclass 23, count 0 2006.285.17:11:18.10#ibcon#*mode == 0, iclass 23, count 0 2006.285.17:11:18.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.17:11:18.10#ibcon#[27=USB\r\n] 2006.285.17:11:18.10#ibcon#*before write, iclass 23, count 0 2006.285.17:11:18.10#ibcon#enter sib2, iclass 23, count 0 2006.285.17:11:18.10#ibcon#flushed, iclass 23, count 0 2006.285.17:11:18.10#ibcon#about to write, iclass 23, count 0 2006.285.17:11:18.10#ibcon#wrote, iclass 23, count 0 2006.285.17:11:18.10#ibcon#about to read 3, iclass 23, count 0 2006.285.17:11:18.13#ibcon#read 3, iclass 23, count 0 2006.285.17:11:18.13#ibcon#about to read 4, iclass 23, count 0 2006.285.17:11:18.13#ibcon#read 4, iclass 23, count 0 2006.285.17:11:18.13#ibcon#about to read 5, iclass 23, count 0 2006.285.17:11:18.13#ibcon#read 5, iclass 23, count 0 2006.285.17:11:18.13#ibcon#about to read 6, iclass 23, count 0 2006.285.17:11:18.13#ibcon#read 6, iclass 23, count 0 2006.285.17:11:18.13#ibcon#end of sib2, iclass 23, count 0 2006.285.17:11:18.13#ibcon#*after write, iclass 23, count 0 2006.285.17:11:18.13#ibcon#*before return 0, iclass 23, count 0 2006.285.17:11:18.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:11:18.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:11:18.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.17:11:18.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.17:11:18.13$vck44/vblo=3,649.99 2006.285.17:11:18.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.17:11:18.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.17:11:18.13#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:18.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:11:18.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:11:18.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:11:18.13#ibcon#enter wrdev, iclass 25, count 0 2006.285.17:11:18.13#ibcon#first serial, iclass 25, count 0 2006.285.17:11:18.13#ibcon#enter sib2, iclass 25, count 0 2006.285.17:11:18.13#ibcon#flushed, iclass 25, count 0 2006.285.17:11:18.13#ibcon#about to write, iclass 25, count 0 2006.285.17:11:18.13#ibcon#wrote, iclass 25, count 0 2006.285.17:11:18.13#ibcon#about to read 3, iclass 25, count 0 2006.285.17:11:18.15#ibcon#read 3, iclass 25, count 0 2006.285.17:11:18.15#ibcon#about to read 4, iclass 25, count 0 2006.285.17:11:18.15#ibcon#read 4, iclass 25, count 0 2006.285.17:11:18.15#ibcon#about to read 5, iclass 25, count 0 2006.285.17:11:18.15#ibcon#read 5, iclass 25, count 0 2006.285.17:11:18.15#ibcon#about to read 6, iclass 25, count 0 2006.285.17:11:18.15#ibcon#read 6, iclass 25, count 0 2006.285.17:11:18.15#ibcon#end of sib2, iclass 25, count 0 2006.285.17:11:18.15#ibcon#*mode == 0, iclass 25, count 0 2006.285.17:11:18.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.17:11:18.15#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.17:11:18.15#ibcon#*before write, iclass 25, count 0 2006.285.17:11:18.15#ibcon#enter sib2, iclass 25, count 0 2006.285.17:11:18.15#ibcon#flushed, iclass 25, count 0 2006.285.17:11:18.15#ibcon#about to write, iclass 25, count 0 2006.285.17:11:18.15#ibcon#wrote, iclass 25, count 0 2006.285.17:11:18.15#ibcon#about to read 3, iclass 25, count 0 2006.285.17:11:18.19#ibcon#read 3, iclass 25, count 0 2006.285.17:11:18.19#ibcon#about to read 4, iclass 25, count 0 2006.285.17:11:18.19#ibcon#read 4, iclass 25, count 0 2006.285.17:11:18.19#ibcon#about to read 5, iclass 25, count 0 2006.285.17:11:18.19#ibcon#read 5, iclass 25, count 0 2006.285.17:11:18.19#ibcon#about to read 6, iclass 25, count 0 2006.285.17:11:18.19#ibcon#read 6, iclass 25, count 0 2006.285.17:11:18.19#ibcon#end of sib2, iclass 25, count 0 2006.285.17:11:18.19#ibcon#*after write, iclass 25, count 0 2006.285.17:11:18.19#ibcon#*before return 0, iclass 25, count 0 2006.285.17:11:18.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:11:18.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:11:18.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.17:11:18.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.17:11:18.19$vck44/vb=3,4 2006.285.17:11:18.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.17:11:18.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.17:11:18.19#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:18.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:11:18.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:11:18.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:11:18.25#ibcon#enter wrdev, iclass 27, count 2 2006.285.17:11:18.25#ibcon#first serial, iclass 27, count 2 2006.285.17:11:18.25#ibcon#enter sib2, iclass 27, count 2 2006.285.17:11:18.25#ibcon#flushed, iclass 27, count 2 2006.285.17:11:18.25#ibcon#about to write, iclass 27, count 2 2006.285.17:11:18.25#ibcon#wrote, iclass 27, count 2 2006.285.17:11:18.25#ibcon#about to read 3, iclass 27, count 2 2006.285.17:11:18.27#ibcon#read 3, iclass 27, count 2 2006.285.17:11:18.27#ibcon#about to read 4, iclass 27, count 2 2006.285.17:11:18.27#ibcon#read 4, iclass 27, count 2 2006.285.17:11:18.27#ibcon#about to read 5, iclass 27, count 2 2006.285.17:11:18.27#ibcon#read 5, iclass 27, count 2 2006.285.17:11:18.27#ibcon#about to read 6, iclass 27, count 2 2006.285.17:11:18.27#ibcon#read 6, iclass 27, count 2 2006.285.17:11:18.27#ibcon#end of sib2, iclass 27, count 2 2006.285.17:11:18.27#ibcon#*mode == 0, iclass 27, count 2 2006.285.17:11:18.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.17:11:18.27#ibcon#[27=AT03-04\r\n] 2006.285.17:11:18.27#ibcon#*before write, iclass 27, count 2 2006.285.17:11:18.27#ibcon#enter sib2, iclass 27, count 2 2006.285.17:11:18.27#ibcon#flushed, iclass 27, count 2 2006.285.17:11:18.27#ibcon#about to write, iclass 27, count 2 2006.285.17:11:18.27#ibcon#wrote, iclass 27, count 2 2006.285.17:11:18.27#ibcon#about to read 3, iclass 27, count 2 2006.285.17:11:18.30#ibcon#read 3, iclass 27, count 2 2006.285.17:11:18.30#ibcon#about to read 4, iclass 27, count 2 2006.285.17:11:18.30#ibcon#read 4, iclass 27, count 2 2006.285.17:11:18.30#ibcon#about to read 5, iclass 27, count 2 2006.285.17:11:18.30#ibcon#read 5, iclass 27, count 2 2006.285.17:11:18.30#ibcon#about to read 6, iclass 27, count 2 2006.285.17:11:18.30#ibcon#read 6, iclass 27, count 2 2006.285.17:11:18.30#ibcon#end of sib2, iclass 27, count 2 2006.285.17:11:18.30#ibcon#*after write, iclass 27, count 2 2006.285.17:11:18.30#ibcon#*before return 0, iclass 27, count 2 2006.285.17:11:18.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:11:18.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:11:18.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.17:11:18.30#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:18.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:11:18.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:11:18.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:11:18.42#ibcon#enter wrdev, iclass 27, count 0 2006.285.17:11:18.42#ibcon#first serial, iclass 27, count 0 2006.285.17:11:18.42#ibcon#enter sib2, iclass 27, count 0 2006.285.17:11:18.42#ibcon#flushed, iclass 27, count 0 2006.285.17:11:18.42#ibcon#about to write, iclass 27, count 0 2006.285.17:11:18.42#ibcon#wrote, iclass 27, count 0 2006.285.17:11:18.42#ibcon#about to read 3, iclass 27, count 0 2006.285.17:11:18.44#ibcon#read 3, iclass 27, count 0 2006.285.17:11:18.44#ibcon#about to read 4, iclass 27, count 0 2006.285.17:11:18.44#ibcon#read 4, iclass 27, count 0 2006.285.17:11:18.44#ibcon#about to read 5, iclass 27, count 0 2006.285.17:11:18.44#ibcon#read 5, iclass 27, count 0 2006.285.17:11:18.44#ibcon#about to read 6, iclass 27, count 0 2006.285.17:11:18.44#ibcon#read 6, iclass 27, count 0 2006.285.17:11:18.44#ibcon#end of sib2, iclass 27, count 0 2006.285.17:11:18.44#ibcon#*mode == 0, iclass 27, count 0 2006.285.17:11:18.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.17:11:18.44#ibcon#[27=USB\r\n] 2006.285.17:11:18.44#ibcon#*before write, iclass 27, count 0 2006.285.17:11:18.44#ibcon#enter sib2, iclass 27, count 0 2006.285.17:11:18.44#ibcon#flushed, iclass 27, count 0 2006.285.17:11:18.44#ibcon#about to write, iclass 27, count 0 2006.285.17:11:18.44#ibcon#wrote, iclass 27, count 0 2006.285.17:11:18.44#ibcon#about to read 3, iclass 27, count 0 2006.285.17:11:18.47#ibcon#read 3, iclass 27, count 0 2006.285.17:11:18.47#ibcon#about to read 4, iclass 27, count 0 2006.285.17:11:18.47#ibcon#read 4, iclass 27, count 0 2006.285.17:11:18.47#ibcon#about to read 5, iclass 27, count 0 2006.285.17:11:18.47#ibcon#read 5, iclass 27, count 0 2006.285.17:11:18.47#ibcon#about to read 6, iclass 27, count 0 2006.285.17:11:18.47#ibcon#read 6, iclass 27, count 0 2006.285.17:11:18.47#ibcon#end of sib2, iclass 27, count 0 2006.285.17:11:18.47#ibcon#*after write, iclass 27, count 0 2006.285.17:11:18.47#ibcon#*before return 0, iclass 27, count 0 2006.285.17:11:18.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:11:18.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:11:18.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.17:11:18.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.17:11:18.47$vck44/vblo=4,679.99 2006.285.17:11:18.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.17:11:18.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.17:11:18.47#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:18.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:11:18.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:11:18.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:11:18.47#ibcon#enter wrdev, iclass 29, count 0 2006.285.17:11:18.47#ibcon#first serial, iclass 29, count 0 2006.285.17:11:18.47#ibcon#enter sib2, iclass 29, count 0 2006.285.17:11:18.47#ibcon#flushed, iclass 29, count 0 2006.285.17:11:18.47#ibcon#about to write, iclass 29, count 0 2006.285.17:11:18.47#ibcon#wrote, iclass 29, count 0 2006.285.17:11:18.47#ibcon#about to read 3, iclass 29, count 0 2006.285.17:11:18.49#ibcon#read 3, iclass 29, count 0 2006.285.17:11:18.49#ibcon#about to read 4, iclass 29, count 0 2006.285.17:11:18.49#ibcon#read 4, iclass 29, count 0 2006.285.17:11:18.49#ibcon#about to read 5, iclass 29, count 0 2006.285.17:11:18.49#ibcon#read 5, iclass 29, count 0 2006.285.17:11:18.49#ibcon#about to read 6, iclass 29, count 0 2006.285.17:11:18.49#ibcon#read 6, iclass 29, count 0 2006.285.17:11:18.49#ibcon#end of sib2, iclass 29, count 0 2006.285.17:11:18.49#ibcon#*mode == 0, iclass 29, count 0 2006.285.17:11:18.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.17:11:18.49#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.17:11:18.49#ibcon#*before write, iclass 29, count 0 2006.285.17:11:18.49#ibcon#enter sib2, iclass 29, count 0 2006.285.17:11:18.49#ibcon#flushed, iclass 29, count 0 2006.285.17:11:18.49#ibcon#about to write, iclass 29, count 0 2006.285.17:11:18.49#ibcon#wrote, iclass 29, count 0 2006.285.17:11:18.49#ibcon#about to read 3, iclass 29, count 0 2006.285.17:11:18.53#ibcon#read 3, iclass 29, count 0 2006.285.17:11:18.53#ibcon#about to read 4, iclass 29, count 0 2006.285.17:11:18.53#ibcon#read 4, iclass 29, count 0 2006.285.17:11:18.53#ibcon#about to read 5, iclass 29, count 0 2006.285.17:11:18.53#ibcon#read 5, iclass 29, count 0 2006.285.17:11:18.53#ibcon#about to read 6, iclass 29, count 0 2006.285.17:11:18.53#ibcon#read 6, iclass 29, count 0 2006.285.17:11:18.53#ibcon#end of sib2, iclass 29, count 0 2006.285.17:11:18.53#ibcon#*after write, iclass 29, count 0 2006.285.17:11:18.53#ibcon#*before return 0, iclass 29, count 0 2006.285.17:11:18.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:11:18.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:11:18.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.17:11:18.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.17:11:18.53$vck44/vb=4,5 2006.285.17:11:18.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.17:11:18.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.17:11:18.53#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:18.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:11:18.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:11:18.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:11:18.59#ibcon#enter wrdev, iclass 31, count 2 2006.285.17:11:18.59#ibcon#first serial, iclass 31, count 2 2006.285.17:11:18.59#ibcon#enter sib2, iclass 31, count 2 2006.285.17:11:18.59#ibcon#flushed, iclass 31, count 2 2006.285.17:11:18.59#ibcon#about to write, iclass 31, count 2 2006.285.17:11:18.59#ibcon#wrote, iclass 31, count 2 2006.285.17:11:18.59#ibcon#about to read 3, iclass 31, count 2 2006.285.17:11:18.61#ibcon#read 3, iclass 31, count 2 2006.285.17:11:18.61#ibcon#about to read 4, iclass 31, count 2 2006.285.17:11:18.61#ibcon#read 4, iclass 31, count 2 2006.285.17:11:18.61#ibcon#about to read 5, iclass 31, count 2 2006.285.17:11:18.61#ibcon#read 5, iclass 31, count 2 2006.285.17:11:18.61#ibcon#about to read 6, iclass 31, count 2 2006.285.17:11:18.61#ibcon#read 6, iclass 31, count 2 2006.285.17:11:18.61#ibcon#end of sib2, iclass 31, count 2 2006.285.17:11:18.61#ibcon#*mode == 0, iclass 31, count 2 2006.285.17:11:18.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.17:11:18.61#ibcon#[27=AT04-05\r\n] 2006.285.17:11:18.61#ibcon#*before write, iclass 31, count 2 2006.285.17:11:18.61#ibcon#enter sib2, iclass 31, count 2 2006.285.17:11:18.61#ibcon#flushed, iclass 31, count 2 2006.285.17:11:18.61#ibcon#about to write, iclass 31, count 2 2006.285.17:11:18.61#ibcon#wrote, iclass 31, count 2 2006.285.17:11:18.61#ibcon#about to read 3, iclass 31, count 2 2006.285.17:11:18.64#ibcon#read 3, iclass 31, count 2 2006.285.17:11:18.64#ibcon#about to read 4, iclass 31, count 2 2006.285.17:11:18.64#ibcon#read 4, iclass 31, count 2 2006.285.17:11:18.64#ibcon#about to read 5, iclass 31, count 2 2006.285.17:11:18.64#ibcon#read 5, iclass 31, count 2 2006.285.17:11:18.64#ibcon#about to read 6, iclass 31, count 2 2006.285.17:11:18.64#ibcon#read 6, iclass 31, count 2 2006.285.17:11:18.64#ibcon#end of sib2, iclass 31, count 2 2006.285.17:11:18.64#ibcon#*after write, iclass 31, count 2 2006.285.17:11:18.64#ibcon#*before return 0, iclass 31, count 2 2006.285.17:11:18.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:11:18.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:11:18.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.17:11:18.64#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:18.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:11:18.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:11:18.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:11:18.76#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:11:18.76#ibcon#first serial, iclass 31, count 0 2006.285.17:11:18.76#ibcon#enter sib2, iclass 31, count 0 2006.285.17:11:18.76#ibcon#flushed, iclass 31, count 0 2006.285.17:11:18.76#ibcon#about to write, iclass 31, count 0 2006.285.17:11:18.76#ibcon#wrote, iclass 31, count 0 2006.285.17:11:18.76#ibcon#about to read 3, iclass 31, count 0 2006.285.17:11:18.78#ibcon#read 3, iclass 31, count 0 2006.285.17:11:18.78#ibcon#about to read 4, iclass 31, count 0 2006.285.17:11:18.78#ibcon#read 4, iclass 31, count 0 2006.285.17:11:18.78#ibcon#about to read 5, iclass 31, count 0 2006.285.17:11:18.78#ibcon#read 5, iclass 31, count 0 2006.285.17:11:18.78#ibcon#about to read 6, iclass 31, count 0 2006.285.17:11:18.78#ibcon#read 6, iclass 31, count 0 2006.285.17:11:18.78#ibcon#end of sib2, iclass 31, count 0 2006.285.17:11:18.78#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:11:18.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:11:18.78#ibcon#[27=USB\r\n] 2006.285.17:11:18.78#ibcon#*before write, iclass 31, count 0 2006.285.17:11:18.78#ibcon#enter sib2, iclass 31, count 0 2006.285.17:11:18.78#ibcon#flushed, iclass 31, count 0 2006.285.17:11:18.78#ibcon#about to write, iclass 31, count 0 2006.285.17:11:18.78#ibcon#wrote, iclass 31, count 0 2006.285.17:11:18.78#ibcon#about to read 3, iclass 31, count 0 2006.285.17:11:18.81#ibcon#read 3, iclass 31, count 0 2006.285.17:11:18.81#ibcon#about to read 4, iclass 31, count 0 2006.285.17:11:18.81#ibcon#read 4, iclass 31, count 0 2006.285.17:11:18.81#ibcon#about to read 5, iclass 31, count 0 2006.285.17:11:18.81#ibcon#read 5, iclass 31, count 0 2006.285.17:11:18.81#ibcon#about to read 6, iclass 31, count 0 2006.285.17:11:18.81#ibcon#read 6, iclass 31, count 0 2006.285.17:11:18.81#ibcon#end of sib2, iclass 31, count 0 2006.285.17:11:18.81#ibcon#*after write, iclass 31, count 0 2006.285.17:11:18.81#ibcon#*before return 0, iclass 31, count 0 2006.285.17:11:18.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:11:18.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:11:18.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:11:18.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:11:18.81$vck44/vblo=5,709.99 2006.285.17:11:18.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.17:11:18.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.17:11:18.92#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:18.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:11:18.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:11:18.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:11:18.92#ibcon#enter wrdev, iclass 33, count 0 2006.285.17:11:18.92#ibcon#first serial, iclass 33, count 0 2006.285.17:11:18.92#ibcon#enter sib2, iclass 33, count 0 2006.285.17:11:18.92#ibcon#flushed, iclass 33, count 0 2006.285.17:11:18.92#ibcon#about to write, iclass 33, count 0 2006.285.17:11:18.92#ibcon#wrote, iclass 33, count 0 2006.285.17:11:18.92#ibcon#about to read 3, iclass 33, count 0 2006.285.17:11:18.93#ibcon#read 3, iclass 33, count 0 2006.285.17:11:18.93#ibcon#about to read 4, iclass 33, count 0 2006.285.17:11:18.93#ibcon#read 4, iclass 33, count 0 2006.285.17:11:18.93#ibcon#about to read 5, iclass 33, count 0 2006.285.17:11:18.93#ibcon#read 5, iclass 33, count 0 2006.285.17:11:18.93#ibcon#about to read 6, iclass 33, count 0 2006.285.17:11:18.93#ibcon#read 6, iclass 33, count 0 2006.285.17:11:18.93#ibcon#end of sib2, iclass 33, count 0 2006.285.17:11:18.93#ibcon#*mode == 0, iclass 33, count 0 2006.285.17:11:18.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.17:11:18.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.17:11:18.93#ibcon#*before write, iclass 33, count 0 2006.285.17:11:18.93#ibcon#enter sib2, iclass 33, count 0 2006.285.17:11:18.93#ibcon#flushed, iclass 33, count 0 2006.285.17:11:18.93#ibcon#about to write, iclass 33, count 0 2006.285.17:11:18.93#ibcon#wrote, iclass 33, count 0 2006.285.17:11:18.93#ibcon#about to read 3, iclass 33, count 0 2006.285.17:11:18.97#ibcon#read 3, iclass 33, count 0 2006.285.17:11:18.97#ibcon#about to read 4, iclass 33, count 0 2006.285.17:11:18.97#ibcon#read 4, iclass 33, count 0 2006.285.17:11:18.97#ibcon#about to read 5, iclass 33, count 0 2006.285.17:11:18.97#ibcon#read 5, iclass 33, count 0 2006.285.17:11:18.97#ibcon#about to read 6, iclass 33, count 0 2006.285.17:11:18.97#ibcon#read 6, iclass 33, count 0 2006.285.17:11:18.97#ibcon#end of sib2, iclass 33, count 0 2006.285.17:11:18.97#ibcon#*after write, iclass 33, count 0 2006.285.17:11:18.97#ibcon#*before return 0, iclass 33, count 0 2006.285.17:11:18.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:11:18.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:11:18.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.17:11:18.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.17:11:18.97$vck44/vb=5,4 2006.285.17:11:18.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.17:11:18.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.17:11:18.97#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:18.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:11:18.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:11:18.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:11:18.97#ibcon#enter wrdev, iclass 35, count 2 2006.285.17:11:18.97#ibcon#first serial, iclass 35, count 2 2006.285.17:11:18.97#ibcon#enter sib2, iclass 35, count 2 2006.285.17:11:18.97#ibcon#flushed, iclass 35, count 2 2006.285.17:11:18.97#ibcon#about to write, iclass 35, count 2 2006.285.17:11:18.97#ibcon#wrote, iclass 35, count 2 2006.285.17:11:18.97#ibcon#about to read 3, iclass 35, count 2 2006.285.17:11:18.99#ibcon#read 3, iclass 35, count 2 2006.285.17:11:18.99#ibcon#about to read 4, iclass 35, count 2 2006.285.17:11:18.99#ibcon#read 4, iclass 35, count 2 2006.285.17:11:18.99#ibcon#about to read 5, iclass 35, count 2 2006.285.17:11:18.99#ibcon#read 5, iclass 35, count 2 2006.285.17:11:18.99#ibcon#about to read 6, iclass 35, count 2 2006.285.17:11:18.99#ibcon#read 6, iclass 35, count 2 2006.285.17:11:18.99#ibcon#end of sib2, iclass 35, count 2 2006.285.17:11:18.99#ibcon#*mode == 0, iclass 35, count 2 2006.285.17:11:18.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.17:11:18.99#ibcon#[27=AT05-04\r\n] 2006.285.17:11:18.99#ibcon#*before write, iclass 35, count 2 2006.285.17:11:18.99#ibcon#enter sib2, iclass 35, count 2 2006.285.17:11:18.99#ibcon#flushed, iclass 35, count 2 2006.285.17:11:18.99#ibcon#about to write, iclass 35, count 2 2006.285.17:11:18.99#ibcon#wrote, iclass 35, count 2 2006.285.17:11:18.99#ibcon#about to read 3, iclass 35, count 2 2006.285.17:11:19.02#ibcon#read 3, iclass 35, count 2 2006.285.17:11:19.02#ibcon#about to read 4, iclass 35, count 2 2006.285.17:11:19.02#ibcon#read 4, iclass 35, count 2 2006.285.17:11:19.02#ibcon#about to read 5, iclass 35, count 2 2006.285.17:11:19.02#ibcon#read 5, iclass 35, count 2 2006.285.17:11:19.02#ibcon#about to read 6, iclass 35, count 2 2006.285.17:11:19.02#ibcon#read 6, iclass 35, count 2 2006.285.17:11:19.02#ibcon#end of sib2, iclass 35, count 2 2006.285.17:11:19.02#ibcon#*after write, iclass 35, count 2 2006.285.17:11:19.02#ibcon#*before return 0, iclass 35, count 2 2006.285.17:11:19.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:11:19.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:11:19.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.17:11:19.02#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:19.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:11:19.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:11:19.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:11:19.14#ibcon#enter wrdev, iclass 35, count 0 2006.285.17:11:19.14#ibcon#first serial, iclass 35, count 0 2006.285.17:11:19.14#ibcon#enter sib2, iclass 35, count 0 2006.285.17:11:19.14#ibcon#flushed, iclass 35, count 0 2006.285.17:11:19.14#ibcon#about to write, iclass 35, count 0 2006.285.17:11:19.14#ibcon#wrote, iclass 35, count 0 2006.285.17:11:19.14#ibcon#about to read 3, iclass 35, count 0 2006.285.17:11:19.16#ibcon#read 3, iclass 35, count 0 2006.285.17:11:19.16#ibcon#about to read 4, iclass 35, count 0 2006.285.17:11:19.16#ibcon#read 4, iclass 35, count 0 2006.285.17:11:19.16#ibcon#about to read 5, iclass 35, count 0 2006.285.17:11:19.16#ibcon#read 5, iclass 35, count 0 2006.285.17:11:19.16#ibcon#about to read 6, iclass 35, count 0 2006.285.17:11:19.16#ibcon#read 6, iclass 35, count 0 2006.285.17:11:19.16#ibcon#end of sib2, iclass 35, count 0 2006.285.17:11:19.16#ibcon#*mode == 0, iclass 35, count 0 2006.285.17:11:19.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.17:11:19.16#ibcon#[27=USB\r\n] 2006.285.17:11:19.16#ibcon#*before write, iclass 35, count 0 2006.285.17:11:19.16#ibcon#enter sib2, iclass 35, count 0 2006.285.17:11:19.16#ibcon#flushed, iclass 35, count 0 2006.285.17:11:19.16#ibcon#about to write, iclass 35, count 0 2006.285.17:11:19.16#ibcon#wrote, iclass 35, count 0 2006.285.17:11:19.16#ibcon#about to read 3, iclass 35, count 0 2006.285.17:11:19.19#ibcon#read 3, iclass 35, count 0 2006.285.17:11:19.19#ibcon#about to read 4, iclass 35, count 0 2006.285.17:11:19.19#ibcon#read 4, iclass 35, count 0 2006.285.17:11:19.19#ibcon#about to read 5, iclass 35, count 0 2006.285.17:11:19.19#ibcon#read 5, iclass 35, count 0 2006.285.17:11:19.19#ibcon#about to read 6, iclass 35, count 0 2006.285.17:11:19.19#ibcon#read 6, iclass 35, count 0 2006.285.17:11:19.19#ibcon#end of sib2, iclass 35, count 0 2006.285.17:11:19.19#ibcon#*after write, iclass 35, count 0 2006.285.17:11:19.19#ibcon#*before return 0, iclass 35, count 0 2006.285.17:11:19.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:11:19.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:11:19.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.17:11:19.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.17:11:19.19$vck44/vblo=6,719.99 2006.285.17:11:19.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.17:11:19.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.17:11:19.19#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:19.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:11:19.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:11:19.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:11:19.19#ibcon#enter wrdev, iclass 37, count 0 2006.285.17:11:19.19#ibcon#first serial, iclass 37, count 0 2006.285.17:11:19.19#ibcon#enter sib2, iclass 37, count 0 2006.285.17:11:19.19#ibcon#flushed, iclass 37, count 0 2006.285.17:11:19.19#ibcon#about to write, iclass 37, count 0 2006.285.17:11:19.19#ibcon#wrote, iclass 37, count 0 2006.285.17:11:19.19#ibcon#about to read 3, iclass 37, count 0 2006.285.17:11:19.21#ibcon#read 3, iclass 37, count 0 2006.285.17:11:19.21#ibcon#about to read 4, iclass 37, count 0 2006.285.17:11:19.21#ibcon#read 4, iclass 37, count 0 2006.285.17:11:19.21#ibcon#about to read 5, iclass 37, count 0 2006.285.17:11:19.21#ibcon#read 5, iclass 37, count 0 2006.285.17:11:19.21#ibcon#about to read 6, iclass 37, count 0 2006.285.17:11:19.21#ibcon#read 6, iclass 37, count 0 2006.285.17:11:19.21#ibcon#end of sib2, iclass 37, count 0 2006.285.17:11:19.21#ibcon#*mode == 0, iclass 37, count 0 2006.285.17:11:19.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.17:11:19.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.17:11:19.21#ibcon#*before write, iclass 37, count 0 2006.285.17:11:19.21#ibcon#enter sib2, iclass 37, count 0 2006.285.17:11:19.21#ibcon#flushed, iclass 37, count 0 2006.285.17:11:19.21#ibcon#about to write, iclass 37, count 0 2006.285.17:11:19.21#ibcon#wrote, iclass 37, count 0 2006.285.17:11:19.21#ibcon#about to read 3, iclass 37, count 0 2006.285.17:11:19.25#ibcon#read 3, iclass 37, count 0 2006.285.17:11:19.25#ibcon#about to read 4, iclass 37, count 0 2006.285.17:11:19.25#ibcon#read 4, iclass 37, count 0 2006.285.17:11:19.25#ibcon#about to read 5, iclass 37, count 0 2006.285.17:11:19.25#ibcon#read 5, iclass 37, count 0 2006.285.17:11:19.25#ibcon#about to read 6, iclass 37, count 0 2006.285.17:11:19.25#ibcon#read 6, iclass 37, count 0 2006.285.17:11:19.25#ibcon#end of sib2, iclass 37, count 0 2006.285.17:11:19.25#ibcon#*after write, iclass 37, count 0 2006.285.17:11:19.25#ibcon#*before return 0, iclass 37, count 0 2006.285.17:11:19.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:11:19.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:11:19.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.17:11:19.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.17:11:19.25$vck44/vb=6,3 2006.285.17:11:19.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.17:11:19.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.17:11:19.25#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:19.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:11:19.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:11:19.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:11:19.31#ibcon#enter wrdev, iclass 39, count 2 2006.285.17:11:19.31#ibcon#first serial, iclass 39, count 2 2006.285.17:11:19.31#ibcon#enter sib2, iclass 39, count 2 2006.285.17:11:19.31#ibcon#flushed, iclass 39, count 2 2006.285.17:11:19.31#ibcon#about to write, iclass 39, count 2 2006.285.17:11:19.31#ibcon#wrote, iclass 39, count 2 2006.285.17:11:19.31#ibcon#about to read 3, iclass 39, count 2 2006.285.17:11:19.33#ibcon#read 3, iclass 39, count 2 2006.285.17:11:19.33#ibcon#about to read 4, iclass 39, count 2 2006.285.17:11:19.33#ibcon#read 4, iclass 39, count 2 2006.285.17:11:19.33#ibcon#about to read 5, iclass 39, count 2 2006.285.17:11:19.33#ibcon#read 5, iclass 39, count 2 2006.285.17:11:19.33#ibcon#about to read 6, iclass 39, count 2 2006.285.17:11:19.33#ibcon#read 6, iclass 39, count 2 2006.285.17:11:19.33#ibcon#end of sib2, iclass 39, count 2 2006.285.17:11:19.33#ibcon#*mode == 0, iclass 39, count 2 2006.285.17:11:19.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.17:11:19.33#ibcon#[27=AT06-03\r\n] 2006.285.17:11:19.33#ibcon#*before write, iclass 39, count 2 2006.285.17:11:19.33#ibcon#enter sib2, iclass 39, count 2 2006.285.17:11:19.33#ibcon#flushed, iclass 39, count 2 2006.285.17:11:19.33#ibcon#about to write, iclass 39, count 2 2006.285.17:11:19.33#ibcon#wrote, iclass 39, count 2 2006.285.17:11:19.33#ibcon#about to read 3, iclass 39, count 2 2006.285.17:11:19.36#ibcon#read 3, iclass 39, count 2 2006.285.17:11:19.36#ibcon#about to read 4, iclass 39, count 2 2006.285.17:11:19.36#ibcon#read 4, iclass 39, count 2 2006.285.17:11:19.36#ibcon#about to read 5, iclass 39, count 2 2006.285.17:11:19.36#ibcon#read 5, iclass 39, count 2 2006.285.17:11:19.36#ibcon#about to read 6, iclass 39, count 2 2006.285.17:11:19.36#ibcon#read 6, iclass 39, count 2 2006.285.17:11:19.36#ibcon#end of sib2, iclass 39, count 2 2006.285.17:11:19.36#ibcon#*after write, iclass 39, count 2 2006.285.17:11:19.36#ibcon#*before return 0, iclass 39, count 2 2006.285.17:11:19.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:11:19.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:11:19.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.17:11:19.36#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:19.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:11:19.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:11:19.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:11:19.48#ibcon#enter wrdev, iclass 39, count 0 2006.285.17:11:19.48#ibcon#first serial, iclass 39, count 0 2006.285.17:11:19.48#ibcon#enter sib2, iclass 39, count 0 2006.285.17:11:19.48#ibcon#flushed, iclass 39, count 0 2006.285.17:11:19.48#ibcon#about to write, iclass 39, count 0 2006.285.17:11:19.48#ibcon#wrote, iclass 39, count 0 2006.285.17:11:19.48#ibcon#about to read 3, iclass 39, count 0 2006.285.17:11:19.50#ibcon#read 3, iclass 39, count 0 2006.285.17:11:19.50#ibcon#about to read 4, iclass 39, count 0 2006.285.17:11:19.50#ibcon#read 4, iclass 39, count 0 2006.285.17:11:19.50#ibcon#about to read 5, iclass 39, count 0 2006.285.17:11:19.50#ibcon#read 5, iclass 39, count 0 2006.285.17:11:19.50#ibcon#about to read 6, iclass 39, count 0 2006.285.17:11:19.50#ibcon#read 6, iclass 39, count 0 2006.285.17:11:19.50#ibcon#end of sib2, iclass 39, count 0 2006.285.17:11:19.50#ibcon#*mode == 0, iclass 39, count 0 2006.285.17:11:19.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.17:11:19.50#ibcon#[27=USB\r\n] 2006.285.17:11:19.50#ibcon#*before write, iclass 39, count 0 2006.285.17:11:19.50#ibcon#enter sib2, iclass 39, count 0 2006.285.17:11:19.50#ibcon#flushed, iclass 39, count 0 2006.285.17:11:19.50#ibcon#about to write, iclass 39, count 0 2006.285.17:11:19.50#ibcon#wrote, iclass 39, count 0 2006.285.17:11:19.50#ibcon#about to read 3, iclass 39, count 0 2006.285.17:11:19.53#ibcon#read 3, iclass 39, count 0 2006.285.17:11:19.53#ibcon#about to read 4, iclass 39, count 0 2006.285.17:11:19.53#ibcon#read 4, iclass 39, count 0 2006.285.17:11:19.53#ibcon#about to read 5, iclass 39, count 0 2006.285.17:11:19.53#ibcon#read 5, iclass 39, count 0 2006.285.17:11:19.53#ibcon#about to read 6, iclass 39, count 0 2006.285.17:11:19.53#ibcon#read 6, iclass 39, count 0 2006.285.17:11:19.53#ibcon#end of sib2, iclass 39, count 0 2006.285.17:11:19.53#ibcon#*after write, iclass 39, count 0 2006.285.17:11:19.53#ibcon#*before return 0, iclass 39, count 0 2006.285.17:11:19.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:11:19.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:11:19.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.17:11:19.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.17:11:19.53$vck44/vblo=7,734.99 2006.285.17:11:19.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.17:11:19.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.17:11:19.53#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:19.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:11:19.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:11:19.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:11:19.53#ibcon#enter wrdev, iclass 3, count 0 2006.285.17:11:19.53#ibcon#first serial, iclass 3, count 0 2006.285.17:11:19.53#ibcon#enter sib2, iclass 3, count 0 2006.285.17:11:19.53#ibcon#flushed, iclass 3, count 0 2006.285.17:11:19.53#ibcon#about to write, iclass 3, count 0 2006.285.17:11:19.53#ibcon#wrote, iclass 3, count 0 2006.285.17:11:19.53#ibcon#about to read 3, iclass 3, count 0 2006.285.17:11:19.55#ibcon#read 3, iclass 3, count 0 2006.285.17:11:19.55#ibcon#about to read 4, iclass 3, count 0 2006.285.17:11:19.55#ibcon#read 4, iclass 3, count 0 2006.285.17:11:19.55#ibcon#about to read 5, iclass 3, count 0 2006.285.17:11:19.55#ibcon#read 5, iclass 3, count 0 2006.285.17:11:19.55#ibcon#about to read 6, iclass 3, count 0 2006.285.17:11:19.55#ibcon#read 6, iclass 3, count 0 2006.285.17:11:19.55#ibcon#end of sib2, iclass 3, count 0 2006.285.17:11:19.55#ibcon#*mode == 0, iclass 3, count 0 2006.285.17:11:19.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.17:11:19.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.17:11:19.55#ibcon#*before write, iclass 3, count 0 2006.285.17:11:19.55#ibcon#enter sib2, iclass 3, count 0 2006.285.17:11:19.55#ibcon#flushed, iclass 3, count 0 2006.285.17:11:19.55#ibcon#about to write, iclass 3, count 0 2006.285.17:11:19.55#ibcon#wrote, iclass 3, count 0 2006.285.17:11:19.55#ibcon#about to read 3, iclass 3, count 0 2006.285.17:11:19.59#ibcon#read 3, iclass 3, count 0 2006.285.17:11:19.59#ibcon#about to read 4, iclass 3, count 0 2006.285.17:11:19.59#ibcon#read 4, iclass 3, count 0 2006.285.17:11:19.59#ibcon#about to read 5, iclass 3, count 0 2006.285.17:11:19.59#ibcon#read 5, iclass 3, count 0 2006.285.17:11:19.59#ibcon#about to read 6, iclass 3, count 0 2006.285.17:11:19.59#ibcon#read 6, iclass 3, count 0 2006.285.17:11:19.59#ibcon#end of sib2, iclass 3, count 0 2006.285.17:11:19.59#ibcon#*after write, iclass 3, count 0 2006.285.17:11:19.59#ibcon#*before return 0, iclass 3, count 0 2006.285.17:11:19.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:11:19.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:11:19.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.17:11:19.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.17:11:19.59$vck44/vb=7,4 2006.285.17:11:19.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.17:11:19.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.17:11:19.59#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:19.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:11:19.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:11:19.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:11:19.65#ibcon#enter wrdev, iclass 5, count 2 2006.285.17:11:19.65#ibcon#first serial, iclass 5, count 2 2006.285.17:11:19.65#ibcon#enter sib2, iclass 5, count 2 2006.285.17:11:19.65#ibcon#flushed, iclass 5, count 2 2006.285.17:11:19.65#ibcon#about to write, iclass 5, count 2 2006.285.17:11:19.65#ibcon#wrote, iclass 5, count 2 2006.285.17:11:19.65#ibcon#about to read 3, iclass 5, count 2 2006.285.17:11:19.67#ibcon#read 3, iclass 5, count 2 2006.285.17:11:19.67#ibcon#about to read 4, iclass 5, count 2 2006.285.17:11:19.67#ibcon#read 4, iclass 5, count 2 2006.285.17:11:19.67#ibcon#about to read 5, iclass 5, count 2 2006.285.17:11:19.67#ibcon#read 5, iclass 5, count 2 2006.285.17:11:19.67#ibcon#about to read 6, iclass 5, count 2 2006.285.17:11:19.67#ibcon#read 6, iclass 5, count 2 2006.285.17:11:19.67#ibcon#end of sib2, iclass 5, count 2 2006.285.17:11:19.67#ibcon#*mode == 0, iclass 5, count 2 2006.285.17:11:19.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.17:11:19.67#ibcon#[27=AT07-04\r\n] 2006.285.17:11:19.67#ibcon#*before write, iclass 5, count 2 2006.285.17:11:19.67#ibcon#enter sib2, iclass 5, count 2 2006.285.17:11:19.67#ibcon#flushed, iclass 5, count 2 2006.285.17:11:19.67#ibcon#about to write, iclass 5, count 2 2006.285.17:11:19.67#ibcon#wrote, iclass 5, count 2 2006.285.17:11:19.67#ibcon#about to read 3, iclass 5, count 2 2006.285.17:11:19.70#ibcon#read 3, iclass 5, count 2 2006.285.17:11:19.70#ibcon#about to read 4, iclass 5, count 2 2006.285.17:11:19.70#ibcon#read 4, iclass 5, count 2 2006.285.17:11:19.70#ibcon#about to read 5, iclass 5, count 2 2006.285.17:11:19.70#ibcon#read 5, iclass 5, count 2 2006.285.17:11:19.70#ibcon#about to read 6, iclass 5, count 2 2006.285.17:11:19.70#ibcon#read 6, iclass 5, count 2 2006.285.17:11:19.70#ibcon#end of sib2, iclass 5, count 2 2006.285.17:11:19.70#ibcon#*after write, iclass 5, count 2 2006.285.17:11:19.70#ibcon#*before return 0, iclass 5, count 2 2006.285.17:11:19.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:11:19.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:11:19.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.17:11:19.70#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:19.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:11:19.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:11:19.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:11:19.85#ibcon#enter wrdev, iclass 5, count 0 2006.285.17:11:19.85#ibcon#first serial, iclass 5, count 0 2006.285.17:11:19.85#ibcon#enter sib2, iclass 5, count 0 2006.285.17:11:19.85#ibcon#flushed, iclass 5, count 0 2006.285.17:11:19.85#ibcon#about to write, iclass 5, count 0 2006.285.17:11:19.85#ibcon#wrote, iclass 5, count 0 2006.285.17:11:19.85#ibcon#about to read 3, iclass 5, count 0 2006.285.17:11:19.86#ibcon#read 3, iclass 5, count 0 2006.285.17:11:19.86#ibcon#about to read 4, iclass 5, count 0 2006.285.17:11:19.86#ibcon#read 4, iclass 5, count 0 2006.285.17:11:19.86#ibcon#about to read 5, iclass 5, count 0 2006.285.17:11:19.86#ibcon#read 5, iclass 5, count 0 2006.285.17:11:19.86#ibcon#about to read 6, iclass 5, count 0 2006.285.17:11:19.86#ibcon#read 6, iclass 5, count 0 2006.285.17:11:19.86#ibcon#end of sib2, iclass 5, count 0 2006.285.17:11:19.86#ibcon#*mode == 0, iclass 5, count 0 2006.285.17:11:19.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.17:11:19.86#ibcon#[27=USB\r\n] 2006.285.17:11:19.86#ibcon#*before write, iclass 5, count 0 2006.285.17:11:19.86#ibcon#enter sib2, iclass 5, count 0 2006.285.17:11:19.86#ibcon#flushed, iclass 5, count 0 2006.285.17:11:19.86#ibcon#about to write, iclass 5, count 0 2006.285.17:11:19.86#ibcon#wrote, iclass 5, count 0 2006.285.17:11:19.86#ibcon#about to read 3, iclass 5, count 0 2006.285.17:11:19.89#ibcon#read 3, iclass 5, count 0 2006.285.17:11:19.89#ibcon#about to read 4, iclass 5, count 0 2006.285.17:11:19.89#ibcon#read 4, iclass 5, count 0 2006.285.17:11:19.89#ibcon#about to read 5, iclass 5, count 0 2006.285.17:11:19.89#ibcon#read 5, iclass 5, count 0 2006.285.17:11:19.89#ibcon#about to read 6, iclass 5, count 0 2006.285.17:11:19.89#ibcon#read 6, iclass 5, count 0 2006.285.17:11:19.89#ibcon#end of sib2, iclass 5, count 0 2006.285.17:11:19.89#ibcon#*after write, iclass 5, count 0 2006.285.17:11:19.89#ibcon#*before return 0, iclass 5, count 0 2006.285.17:11:19.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:11:19.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:11:19.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.17:11:19.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.17:11:19.89$vck44/vblo=8,744.99 2006.285.17:11:19.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.17:11:19.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.17:11:19.89#ibcon#ireg 17 cls_cnt 0 2006.285.17:11:19.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:11:19.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:11:19.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:11:19.89#ibcon#enter wrdev, iclass 7, count 0 2006.285.17:11:19.89#ibcon#first serial, iclass 7, count 0 2006.285.17:11:19.89#ibcon#enter sib2, iclass 7, count 0 2006.285.17:11:19.89#ibcon#flushed, iclass 7, count 0 2006.285.17:11:19.89#ibcon#about to write, iclass 7, count 0 2006.285.17:11:19.89#ibcon#wrote, iclass 7, count 0 2006.285.17:11:19.89#ibcon#about to read 3, iclass 7, count 0 2006.285.17:11:19.91#ibcon#read 3, iclass 7, count 0 2006.285.17:11:19.91#ibcon#about to read 4, iclass 7, count 0 2006.285.17:11:19.91#ibcon#read 4, iclass 7, count 0 2006.285.17:11:19.91#ibcon#about to read 5, iclass 7, count 0 2006.285.17:11:19.91#ibcon#read 5, iclass 7, count 0 2006.285.17:11:19.91#ibcon#about to read 6, iclass 7, count 0 2006.285.17:11:19.91#ibcon#read 6, iclass 7, count 0 2006.285.17:11:19.91#ibcon#end of sib2, iclass 7, count 0 2006.285.17:11:19.91#ibcon#*mode == 0, iclass 7, count 0 2006.285.17:11:19.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.17:11:19.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.17:11:19.91#ibcon#*before write, iclass 7, count 0 2006.285.17:11:19.91#ibcon#enter sib2, iclass 7, count 0 2006.285.17:11:19.91#ibcon#flushed, iclass 7, count 0 2006.285.17:11:19.91#ibcon#about to write, iclass 7, count 0 2006.285.17:11:19.91#ibcon#wrote, iclass 7, count 0 2006.285.17:11:19.91#ibcon#about to read 3, iclass 7, count 0 2006.285.17:11:19.95#ibcon#read 3, iclass 7, count 0 2006.285.17:11:19.95#ibcon#about to read 4, iclass 7, count 0 2006.285.17:11:19.95#ibcon#read 4, iclass 7, count 0 2006.285.17:11:19.95#ibcon#about to read 5, iclass 7, count 0 2006.285.17:11:19.95#ibcon#read 5, iclass 7, count 0 2006.285.17:11:19.95#ibcon#about to read 6, iclass 7, count 0 2006.285.17:11:19.95#ibcon#read 6, iclass 7, count 0 2006.285.17:11:19.95#ibcon#end of sib2, iclass 7, count 0 2006.285.17:11:19.95#ibcon#*after write, iclass 7, count 0 2006.285.17:11:19.95#ibcon#*before return 0, iclass 7, count 0 2006.285.17:11:19.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:11:19.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:11:19.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.17:11:19.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.17:11:19.95$vck44/vb=8,4 2006.285.17:11:19.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.17:11:19.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.17:11:19.95#ibcon#ireg 11 cls_cnt 2 2006.285.17:11:19.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:11:20.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:11:20.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:11:20.01#ibcon#enter wrdev, iclass 11, count 2 2006.285.17:11:20.01#ibcon#first serial, iclass 11, count 2 2006.285.17:11:20.01#ibcon#enter sib2, iclass 11, count 2 2006.285.17:11:20.01#ibcon#flushed, iclass 11, count 2 2006.285.17:11:20.01#ibcon#about to write, iclass 11, count 2 2006.285.17:11:20.01#ibcon#wrote, iclass 11, count 2 2006.285.17:11:20.01#ibcon#about to read 3, iclass 11, count 2 2006.285.17:11:20.03#ibcon#read 3, iclass 11, count 2 2006.285.17:11:20.03#ibcon#about to read 4, iclass 11, count 2 2006.285.17:11:20.03#ibcon#read 4, iclass 11, count 2 2006.285.17:11:20.03#ibcon#about to read 5, iclass 11, count 2 2006.285.17:11:20.03#ibcon#read 5, iclass 11, count 2 2006.285.17:11:20.03#ibcon#about to read 6, iclass 11, count 2 2006.285.17:11:20.03#ibcon#read 6, iclass 11, count 2 2006.285.17:11:20.03#ibcon#end of sib2, iclass 11, count 2 2006.285.17:11:20.03#ibcon#*mode == 0, iclass 11, count 2 2006.285.17:11:20.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.17:11:20.03#ibcon#[27=AT08-04\r\n] 2006.285.17:11:20.03#ibcon#*before write, iclass 11, count 2 2006.285.17:11:20.03#ibcon#enter sib2, iclass 11, count 2 2006.285.17:11:20.03#ibcon#flushed, iclass 11, count 2 2006.285.17:11:20.03#ibcon#about to write, iclass 11, count 2 2006.285.17:11:20.03#ibcon#wrote, iclass 11, count 2 2006.285.17:11:20.03#ibcon#about to read 3, iclass 11, count 2 2006.285.17:11:20.06#ibcon#read 3, iclass 11, count 2 2006.285.17:11:20.06#ibcon#about to read 4, iclass 11, count 2 2006.285.17:11:20.06#ibcon#read 4, iclass 11, count 2 2006.285.17:11:20.06#ibcon#about to read 5, iclass 11, count 2 2006.285.17:11:20.06#ibcon#read 5, iclass 11, count 2 2006.285.17:11:20.06#ibcon#about to read 6, iclass 11, count 2 2006.285.17:11:20.06#ibcon#read 6, iclass 11, count 2 2006.285.17:11:20.06#ibcon#end of sib2, iclass 11, count 2 2006.285.17:11:20.06#ibcon#*after write, iclass 11, count 2 2006.285.17:11:20.06#ibcon#*before return 0, iclass 11, count 2 2006.285.17:11:20.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:11:20.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:11:20.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.17:11:20.06#ibcon#ireg 7 cls_cnt 0 2006.285.17:11:20.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:11:20.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:11:20.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:11:20.18#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:11:20.18#ibcon#first serial, iclass 11, count 0 2006.285.17:11:20.18#ibcon#enter sib2, iclass 11, count 0 2006.285.17:11:20.18#ibcon#flushed, iclass 11, count 0 2006.285.17:11:20.18#ibcon#about to write, iclass 11, count 0 2006.285.17:11:20.18#ibcon#wrote, iclass 11, count 0 2006.285.17:11:20.18#ibcon#about to read 3, iclass 11, count 0 2006.285.17:11:20.20#ibcon#read 3, iclass 11, count 0 2006.285.17:11:20.20#ibcon#about to read 4, iclass 11, count 0 2006.285.17:11:20.20#ibcon#read 4, iclass 11, count 0 2006.285.17:11:20.20#ibcon#about to read 5, iclass 11, count 0 2006.285.17:11:20.20#ibcon#read 5, iclass 11, count 0 2006.285.17:11:20.20#ibcon#about to read 6, iclass 11, count 0 2006.285.17:11:20.20#ibcon#read 6, iclass 11, count 0 2006.285.17:11:20.20#ibcon#end of sib2, iclass 11, count 0 2006.285.17:11:20.20#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:11:20.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:11:20.20#ibcon#[27=USB\r\n] 2006.285.17:11:20.20#ibcon#*before write, iclass 11, count 0 2006.285.17:11:20.20#ibcon#enter sib2, iclass 11, count 0 2006.285.17:11:20.20#ibcon#flushed, iclass 11, count 0 2006.285.17:11:20.20#ibcon#about to write, iclass 11, count 0 2006.285.17:11:20.20#ibcon#wrote, iclass 11, count 0 2006.285.17:11:20.20#ibcon#about to read 3, iclass 11, count 0 2006.285.17:11:20.23#ibcon#read 3, iclass 11, count 0 2006.285.17:11:20.23#ibcon#about to read 4, iclass 11, count 0 2006.285.17:11:20.23#ibcon#read 4, iclass 11, count 0 2006.285.17:11:20.23#ibcon#about to read 5, iclass 11, count 0 2006.285.17:11:20.23#ibcon#read 5, iclass 11, count 0 2006.285.17:11:20.23#ibcon#about to read 6, iclass 11, count 0 2006.285.17:11:20.23#ibcon#read 6, iclass 11, count 0 2006.285.17:11:20.23#ibcon#end of sib2, iclass 11, count 0 2006.285.17:11:20.23#ibcon#*after write, iclass 11, count 0 2006.285.17:11:20.23#ibcon#*before return 0, iclass 11, count 0 2006.285.17:11:20.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:11:20.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:11:20.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:11:20.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:11:20.23$vck44/vabw=wide 2006.285.17:11:20.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.17:11:20.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.17:11:20.23#ibcon#ireg 8 cls_cnt 0 2006.285.17:11:20.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:11:20.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:11:20.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:11:20.23#ibcon#enter wrdev, iclass 13, count 0 2006.285.17:11:20.23#ibcon#first serial, iclass 13, count 0 2006.285.17:11:20.23#ibcon#enter sib2, iclass 13, count 0 2006.285.17:11:20.23#ibcon#flushed, iclass 13, count 0 2006.285.17:11:20.23#ibcon#about to write, iclass 13, count 0 2006.285.17:11:20.23#ibcon#wrote, iclass 13, count 0 2006.285.17:11:20.23#ibcon#about to read 3, iclass 13, count 0 2006.285.17:11:20.25#ibcon#read 3, iclass 13, count 0 2006.285.17:11:20.25#ibcon#about to read 4, iclass 13, count 0 2006.285.17:11:20.25#ibcon#read 4, iclass 13, count 0 2006.285.17:11:20.25#ibcon#about to read 5, iclass 13, count 0 2006.285.17:11:20.25#ibcon#read 5, iclass 13, count 0 2006.285.17:11:20.25#ibcon#about to read 6, iclass 13, count 0 2006.285.17:11:20.25#ibcon#read 6, iclass 13, count 0 2006.285.17:11:20.25#ibcon#end of sib2, iclass 13, count 0 2006.285.17:11:20.25#ibcon#*mode == 0, iclass 13, count 0 2006.285.17:11:20.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.17:11:20.25#ibcon#[25=BW32\r\n] 2006.285.17:11:20.25#ibcon#*before write, iclass 13, count 0 2006.285.17:11:20.25#ibcon#enter sib2, iclass 13, count 0 2006.285.17:11:20.25#ibcon#flushed, iclass 13, count 0 2006.285.17:11:20.25#ibcon#about to write, iclass 13, count 0 2006.285.17:11:20.25#ibcon#wrote, iclass 13, count 0 2006.285.17:11:20.25#ibcon#about to read 3, iclass 13, count 0 2006.285.17:11:20.28#ibcon#read 3, iclass 13, count 0 2006.285.17:11:20.28#ibcon#about to read 4, iclass 13, count 0 2006.285.17:11:20.28#ibcon#read 4, iclass 13, count 0 2006.285.17:11:20.28#ibcon#about to read 5, iclass 13, count 0 2006.285.17:11:20.28#ibcon#read 5, iclass 13, count 0 2006.285.17:11:20.28#ibcon#about to read 6, iclass 13, count 0 2006.285.17:11:20.28#ibcon#read 6, iclass 13, count 0 2006.285.17:11:20.28#ibcon#end of sib2, iclass 13, count 0 2006.285.17:11:20.28#ibcon#*after write, iclass 13, count 0 2006.285.17:11:20.28#ibcon#*before return 0, iclass 13, count 0 2006.285.17:11:20.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:11:20.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:11:20.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.17:11:20.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.17:11:20.28$vck44/vbbw=wide 2006.285.17:11:20.28#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.17:11:20.28#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.17:11:20.28#ibcon#ireg 8 cls_cnt 0 2006.285.17:11:20.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:11:20.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:11:20.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:11:20.35#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:11:20.35#ibcon#first serial, iclass 15, count 0 2006.285.17:11:20.35#ibcon#enter sib2, iclass 15, count 0 2006.285.17:11:20.35#ibcon#flushed, iclass 15, count 0 2006.285.17:11:20.35#ibcon#about to write, iclass 15, count 0 2006.285.17:11:20.35#ibcon#wrote, iclass 15, count 0 2006.285.17:11:20.35#ibcon#about to read 3, iclass 15, count 0 2006.285.17:11:20.37#ibcon#read 3, iclass 15, count 0 2006.285.17:11:20.37#ibcon#about to read 4, iclass 15, count 0 2006.285.17:11:20.37#ibcon#read 4, iclass 15, count 0 2006.285.17:11:20.37#ibcon#about to read 5, iclass 15, count 0 2006.285.17:11:20.37#ibcon#read 5, iclass 15, count 0 2006.285.17:11:20.37#ibcon#about to read 6, iclass 15, count 0 2006.285.17:11:20.37#ibcon#read 6, iclass 15, count 0 2006.285.17:11:20.37#ibcon#end of sib2, iclass 15, count 0 2006.285.17:11:20.37#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:11:20.37#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:11:20.37#ibcon#[27=BW32\r\n] 2006.285.17:11:20.37#ibcon#*before write, iclass 15, count 0 2006.285.17:11:20.37#ibcon#enter sib2, iclass 15, count 0 2006.285.17:11:20.37#ibcon#flushed, iclass 15, count 0 2006.285.17:11:20.37#ibcon#about to write, iclass 15, count 0 2006.285.17:11:20.37#ibcon#wrote, iclass 15, count 0 2006.285.17:11:20.37#ibcon#about to read 3, iclass 15, count 0 2006.285.17:11:20.40#ibcon#read 3, iclass 15, count 0 2006.285.17:11:20.40#ibcon#about to read 4, iclass 15, count 0 2006.285.17:11:20.40#ibcon#read 4, iclass 15, count 0 2006.285.17:11:20.40#ibcon#about to read 5, iclass 15, count 0 2006.285.17:11:20.40#ibcon#read 5, iclass 15, count 0 2006.285.17:11:20.40#ibcon#about to read 6, iclass 15, count 0 2006.285.17:11:20.40#ibcon#read 6, iclass 15, count 0 2006.285.17:11:20.40#ibcon#end of sib2, iclass 15, count 0 2006.285.17:11:20.40#ibcon#*after write, iclass 15, count 0 2006.285.17:11:20.40#ibcon#*before return 0, iclass 15, count 0 2006.285.17:11:20.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:11:20.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:11:20.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:11:20.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:11:20.40$setupk4/ifdk4 2006.285.17:11:20.40$ifdk4/lo= 2006.285.17:11:20.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.17:11:20.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.17:11:20.41$ifdk4/patch= 2006.285.17:11:20.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.17:11:20.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.17:11:20.41$setupk4/!*+20s 2006.285.17:11:20.50#abcon#<5=/13 0.3 1.0 17.27 971014.8\r\n> 2006.285.17:11:20.52#abcon#{5=INTERFACE CLEAR} 2006.285.17:11:20.58#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:11:30.14#trakl#Source acquired 2006.285.17:11:30.14#flagr#flagr/antenna,acquired 2006.285.17:11:30.67#abcon#<5=/13 0.3 1.0 17.27 971014.8\r\n> 2006.285.17:11:30.69#abcon#{5=INTERFACE CLEAR} 2006.285.17:11:30.75#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:11:34.14$setupk4/"tpicd 2006.285.17:11:34.14$setupk4/echo=off 2006.285.17:11:34.14$setupk4/xlog=off 2006.285.17:11:34.14:!2006.285.17:13:40 2006.285.17:13:40.01:preob 2006.285.17:13:41.14/onsource/TRACKING 2006.285.17:13:41.14:!2006.285.17:13:50 2006.285.17:13:50.00:"tape 2006.285.17:13:50.00:"st=record 2006.285.17:13:50.00:data_valid=on 2006.285.17:13:50.00:midob 2006.285.17:13:50.14/onsource/TRACKING 2006.285.17:13:50.15/wx/17.19,1014.8,97 2006.285.17:13:50.34/cable/+6.5006E-03 2006.285.17:13:51.43/va/01,07,usb,yes,31,34 2006.285.17:13:51.43/va/02,06,usb,yes,32,32 2006.285.17:13:51.43/va/03,07,usb,yes,31,33 2006.285.17:13:51.43/va/04,06,usb,yes,33,34 2006.285.17:13:51.43/va/05,03,usb,yes,32,32 2006.285.17:13:51.43/va/06,04,usb,yes,29,28 2006.285.17:13:51.43/va/07,04,usb,yes,29,30 2006.285.17:13:51.43/va/08,03,usb,yes,30,37 2006.285.17:13:51.66/valo/01,524.99,yes,locked 2006.285.17:13:51.66/valo/02,534.99,yes,locked 2006.285.17:13:51.66/valo/03,564.99,yes,locked 2006.285.17:13:51.66/valo/04,624.99,yes,locked 2006.285.17:13:51.66/valo/05,734.99,yes,locked 2006.285.17:13:51.66/valo/06,814.99,yes,locked 2006.285.17:13:51.66/valo/07,864.99,yes,locked 2006.285.17:13:51.66/valo/08,884.99,yes,locked 2006.285.17:13:52.75/vb/01,04,usb,yes,30,28 2006.285.17:13:52.75/vb/02,05,usb,yes,28,28 2006.285.17:13:52.75/vb/03,04,usb,yes,29,32 2006.285.17:13:52.75/vb/04,05,usb,yes,29,28 2006.285.17:13:52.75/vb/05,04,usb,yes,26,28 2006.285.17:13:52.75/vb/06,03,usb,yes,37,33 2006.285.17:13:52.75/vb/07,04,usb,yes,30,30 2006.285.17:13:52.75/vb/08,04,usb,yes,27,31 2006.285.17:13:52.98/vblo/01,629.99,yes,locked 2006.285.17:13:52.98/vblo/02,634.99,yes,locked 2006.285.17:13:52.98/vblo/03,649.99,yes,locked 2006.285.17:13:52.98/vblo/04,679.99,yes,locked 2006.285.17:13:52.98/vblo/05,709.99,yes,locked 2006.285.17:13:52.98/vblo/06,719.99,yes,locked 2006.285.17:13:52.98/vblo/07,734.99,yes,locked 2006.285.17:13:52.98/vblo/08,744.99,yes,locked 2006.285.17:13:53.13/vabw/8 2006.285.17:13:53.28/vbbw/8 2006.285.17:13:53.38/xfe/off,on,12.0 2006.285.17:13:53.76/ifatt/23,28,28,28 2006.285.17:13:54.07/fmout-gps/S +2.61E-07 2006.285.17:13:54.09:!2006.285.17:15:30 2006.285.17:15:30.01:data_valid=off 2006.285.17:15:30.01:"et 2006.285.17:15:30.01:!+3s 2006.285.17:15:33.02:"tape 2006.285.17:15:33.02:postob 2006.285.17:15:33.23/cable/+6.5014E-03 2006.285.17:15:33.23/wx/17.13,1014.8,97 2006.285.17:15:33.29/fmout-gps/S +2.56E-07 2006.285.17:15:33.29:scan_name=285-1717,jd0610,330 2006.285.17:15:33.29:source=oj287,085448.87,200630.6,2000.0,ccw 2006.285.17:15:34.14#flagr#flagr/antenna,new-source 2006.285.17:15:34.14:checkk5 2006.285.17:15:34.79/chk_autoobs//k5ts1/ autoobs is running! 2006.285.17:15:35.59/chk_autoobs//k5ts2/ autoobs is running! 2006.285.17:15:36.02/chk_autoobs//k5ts3/ autoobs is running! 2006.285.17:15:36.65/chk_autoobs//k5ts4/ autoobs is running! 2006.285.17:15:37.30/chk_obsdata//k5ts1/T2851713??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.17:15:37.90/chk_obsdata//k5ts2/T2851713??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.17:15:38.30/chk_obsdata//k5ts3/T2851713??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.17:15:38.72/chk_obsdata//k5ts4/T2851713??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.17:15:39.85/k5log//k5ts1_log_newline 2006.285.17:15:40.71/k5log//k5ts2_log_newline 2006.285.17:15:41.52/k5log//k5ts3_log_newline 2006.285.17:15:42.58/k5log//k5ts4_log_newline 2006.285.17:15:42.60/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.17:15:42.60:setupk4=1 2006.285.17:15:42.60$setupk4/echo=on 2006.285.17:15:42.60$setupk4/pcalon 2006.285.17:15:42.60$pcalon/"no phase cal control is implemented here 2006.285.17:15:42.60$setupk4/"tpicd=stop 2006.285.17:15:42.60$setupk4/"rec=synch_on 2006.285.17:15:42.60$setupk4/"rec_mode=128 2006.285.17:15:42.60$setupk4/!* 2006.285.17:15:42.60$setupk4/recpk4 2006.285.17:15:42.60$recpk4/recpatch= 2006.285.17:15:42.60$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.17:15:42.60$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.17:15:42.60$setupk4/vck44 2006.285.17:15:42.60$vck44/valo=1,524.99 2006.285.17:15:42.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.17:15:42.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.17:15:42.60#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:42.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:15:42.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:15:42.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:15:42.60#ibcon#enter wrdev, iclass 16, count 0 2006.285.17:15:42.60#ibcon#first serial, iclass 16, count 0 2006.285.17:15:42.60#ibcon#enter sib2, iclass 16, count 0 2006.285.17:15:42.60#ibcon#flushed, iclass 16, count 0 2006.285.17:15:42.60#ibcon#about to write, iclass 16, count 0 2006.285.17:15:42.60#ibcon#wrote, iclass 16, count 0 2006.285.17:15:42.60#ibcon#about to read 3, iclass 16, count 0 2006.285.17:15:42.62#ibcon#read 3, iclass 16, count 0 2006.285.17:15:42.62#ibcon#about to read 4, iclass 16, count 0 2006.285.17:15:42.62#ibcon#read 4, iclass 16, count 0 2006.285.17:15:42.62#ibcon#about to read 5, iclass 16, count 0 2006.285.17:15:42.62#ibcon#read 5, iclass 16, count 0 2006.285.17:15:42.62#ibcon#about to read 6, iclass 16, count 0 2006.285.17:15:42.62#ibcon#read 6, iclass 16, count 0 2006.285.17:15:42.62#ibcon#end of sib2, iclass 16, count 0 2006.285.17:15:42.62#ibcon#*mode == 0, iclass 16, count 0 2006.285.17:15:42.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.17:15:42.62#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.17:15:42.62#ibcon#*before write, iclass 16, count 0 2006.285.17:15:42.62#ibcon#enter sib2, iclass 16, count 0 2006.285.17:15:42.62#ibcon#flushed, iclass 16, count 0 2006.285.17:15:42.62#ibcon#about to write, iclass 16, count 0 2006.285.17:15:42.62#ibcon#wrote, iclass 16, count 0 2006.285.17:15:42.62#ibcon#about to read 3, iclass 16, count 0 2006.285.17:15:42.67#ibcon#read 3, iclass 16, count 0 2006.285.17:15:42.67#ibcon#about to read 4, iclass 16, count 0 2006.285.17:15:42.67#ibcon#read 4, iclass 16, count 0 2006.285.17:15:42.67#ibcon#about to read 5, iclass 16, count 0 2006.285.17:15:42.67#ibcon#read 5, iclass 16, count 0 2006.285.17:15:42.67#ibcon#about to read 6, iclass 16, count 0 2006.285.17:15:42.67#ibcon#read 6, iclass 16, count 0 2006.285.17:15:42.67#ibcon#end of sib2, iclass 16, count 0 2006.285.17:15:42.67#ibcon#*after write, iclass 16, count 0 2006.285.17:15:42.67#ibcon#*before return 0, iclass 16, count 0 2006.285.17:15:42.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:15:42.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:15:42.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.17:15:42.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.17:15:42.67$vck44/va=1,7 2006.285.17:15:42.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.17:15:42.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.17:15:42.67#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:42.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:15:42.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:15:42.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:15:42.67#ibcon#enter wrdev, iclass 18, count 2 2006.285.17:15:42.67#ibcon#first serial, iclass 18, count 2 2006.285.17:15:42.67#ibcon#enter sib2, iclass 18, count 2 2006.285.17:15:42.67#ibcon#flushed, iclass 18, count 2 2006.285.17:15:42.67#ibcon#about to write, iclass 18, count 2 2006.285.17:15:42.67#ibcon#wrote, iclass 18, count 2 2006.285.17:15:42.67#ibcon#about to read 3, iclass 18, count 2 2006.285.17:15:42.69#ibcon#read 3, iclass 18, count 2 2006.285.17:15:42.69#ibcon#about to read 4, iclass 18, count 2 2006.285.17:15:42.69#ibcon#read 4, iclass 18, count 2 2006.285.17:15:42.69#ibcon#about to read 5, iclass 18, count 2 2006.285.17:15:42.69#ibcon#read 5, iclass 18, count 2 2006.285.17:15:42.69#ibcon#about to read 6, iclass 18, count 2 2006.285.17:15:42.69#ibcon#read 6, iclass 18, count 2 2006.285.17:15:42.69#ibcon#end of sib2, iclass 18, count 2 2006.285.17:15:42.69#ibcon#*mode == 0, iclass 18, count 2 2006.285.17:15:42.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.17:15:42.69#ibcon#[25=AT01-07\r\n] 2006.285.17:15:42.69#ibcon#*before write, iclass 18, count 2 2006.285.17:15:42.69#ibcon#enter sib2, iclass 18, count 2 2006.285.17:15:42.69#ibcon#flushed, iclass 18, count 2 2006.285.17:15:42.69#ibcon#about to write, iclass 18, count 2 2006.285.17:15:42.69#ibcon#wrote, iclass 18, count 2 2006.285.17:15:42.69#ibcon#about to read 3, iclass 18, count 2 2006.285.17:15:42.72#ibcon#read 3, iclass 18, count 2 2006.285.17:15:42.72#ibcon#about to read 4, iclass 18, count 2 2006.285.17:15:42.72#ibcon#read 4, iclass 18, count 2 2006.285.17:15:42.72#ibcon#about to read 5, iclass 18, count 2 2006.285.17:15:42.72#ibcon#read 5, iclass 18, count 2 2006.285.17:15:42.72#ibcon#about to read 6, iclass 18, count 2 2006.285.17:15:42.72#ibcon#read 6, iclass 18, count 2 2006.285.17:15:42.72#ibcon#end of sib2, iclass 18, count 2 2006.285.17:15:42.72#ibcon#*after write, iclass 18, count 2 2006.285.17:15:42.72#ibcon#*before return 0, iclass 18, count 2 2006.285.17:15:42.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:15:42.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:15:42.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.17:15:42.72#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:42.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:15:42.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:15:42.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:15:42.84#ibcon#enter wrdev, iclass 18, count 0 2006.285.17:15:42.84#ibcon#first serial, iclass 18, count 0 2006.285.17:15:42.84#ibcon#enter sib2, iclass 18, count 0 2006.285.17:15:42.84#ibcon#flushed, iclass 18, count 0 2006.285.17:15:42.84#ibcon#about to write, iclass 18, count 0 2006.285.17:15:42.84#ibcon#wrote, iclass 18, count 0 2006.285.17:15:42.84#ibcon#about to read 3, iclass 18, count 0 2006.285.17:15:42.86#ibcon#read 3, iclass 18, count 0 2006.285.17:15:42.86#ibcon#about to read 4, iclass 18, count 0 2006.285.17:15:42.86#ibcon#read 4, iclass 18, count 0 2006.285.17:15:42.86#ibcon#about to read 5, iclass 18, count 0 2006.285.17:15:42.86#ibcon#read 5, iclass 18, count 0 2006.285.17:15:42.86#ibcon#about to read 6, iclass 18, count 0 2006.285.17:15:42.86#ibcon#read 6, iclass 18, count 0 2006.285.17:15:42.86#ibcon#end of sib2, iclass 18, count 0 2006.285.17:15:42.86#ibcon#*mode == 0, iclass 18, count 0 2006.285.17:15:42.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.17:15:42.86#ibcon#[25=USB\r\n] 2006.285.17:15:42.86#ibcon#*before write, iclass 18, count 0 2006.285.17:15:42.86#ibcon#enter sib2, iclass 18, count 0 2006.285.17:15:42.86#ibcon#flushed, iclass 18, count 0 2006.285.17:15:42.86#ibcon#about to write, iclass 18, count 0 2006.285.17:15:42.86#ibcon#wrote, iclass 18, count 0 2006.285.17:15:42.86#ibcon#about to read 3, iclass 18, count 0 2006.285.17:15:42.89#ibcon#read 3, iclass 18, count 0 2006.285.17:15:42.89#ibcon#about to read 4, iclass 18, count 0 2006.285.17:15:42.89#ibcon#read 4, iclass 18, count 0 2006.285.17:15:42.89#ibcon#about to read 5, iclass 18, count 0 2006.285.17:15:42.89#ibcon#read 5, iclass 18, count 0 2006.285.17:15:42.89#ibcon#about to read 6, iclass 18, count 0 2006.285.17:15:42.89#ibcon#read 6, iclass 18, count 0 2006.285.17:15:42.89#ibcon#end of sib2, iclass 18, count 0 2006.285.17:15:42.89#ibcon#*after write, iclass 18, count 0 2006.285.17:15:42.89#ibcon#*before return 0, iclass 18, count 0 2006.285.17:15:42.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:15:42.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:15:42.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.17:15:42.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.17:15:42.89$vck44/valo=2,534.99 2006.285.17:15:42.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.17:15:42.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.17:15:42.89#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:42.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:15:42.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:15:42.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:15:42.89#ibcon#enter wrdev, iclass 20, count 0 2006.285.17:15:42.89#ibcon#first serial, iclass 20, count 0 2006.285.17:15:42.89#ibcon#enter sib2, iclass 20, count 0 2006.285.17:15:42.89#ibcon#flushed, iclass 20, count 0 2006.285.17:15:42.89#ibcon#about to write, iclass 20, count 0 2006.285.17:15:42.89#ibcon#wrote, iclass 20, count 0 2006.285.17:15:42.89#ibcon#about to read 3, iclass 20, count 0 2006.285.17:15:42.91#ibcon#read 3, iclass 20, count 0 2006.285.17:15:42.91#ibcon#about to read 4, iclass 20, count 0 2006.285.17:15:42.91#ibcon#read 4, iclass 20, count 0 2006.285.17:15:42.91#ibcon#about to read 5, iclass 20, count 0 2006.285.17:15:42.91#ibcon#read 5, iclass 20, count 0 2006.285.17:15:42.91#ibcon#about to read 6, iclass 20, count 0 2006.285.17:15:42.91#ibcon#read 6, iclass 20, count 0 2006.285.17:15:42.91#ibcon#end of sib2, iclass 20, count 0 2006.285.17:15:42.91#ibcon#*mode == 0, iclass 20, count 0 2006.285.17:15:42.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.17:15:42.91#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.17:15:42.91#ibcon#*before write, iclass 20, count 0 2006.285.17:15:42.91#ibcon#enter sib2, iclass 20, count 0 2006.285.17:15:42.91#ibcon#flushed, iclass 20, count 0 2006.285.17:15:42.91#ibcon#about to write, iclass 20, count 0 2006.285.17:15:42.91#ibcon#wrote, iclass 20, count 0 2006.285.17:15:42.91#ibcon#about to read 3, iclass 20, count 0 2006.285.17:15:42.95#ibcon#read 3, iclass 20, count 0 2006.285.17:15:42.95#ibcon#about to read 4, iclass 20, count 0 2006.285.17:15:42.95#ibcon#read 4, iclass 20, count 0 2006.285.17:15:42.95#ibcon#about to read 5, iclass 20, count 0 2006.285.17:15:42.95#ibcon#read 5, iclass 20, count 0 2006.285.17:15:42.95#ibcon#about to read 6, iclass 20, count 0 2006.285.17:15:42.95#ibcon#read 6, iclass 20, count 0 2006.285.17:15:42.95#ibcon#end of sib2, iclass 20, count 0 2006.285.17:15:42.95#ibcon#*after write, iclass 20, count 0 2006.285.17:15:42.95#ibcon#*before return 0, iclass 20, count 0 2006.285.17:15:42.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:15:42.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:15:42.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.17:15:42.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.17:15:42.95$vck44/va=2,6 2006.285.17:15:42.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.17:15:42.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.17:15:42.95#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:42.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:15:43.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:15:43.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:15:43.01#ibcon#enter wrdev, iclass 22, count 2 2006.285.17:15:43.01#ibcon#first serial, iclass 22, count 2 2006.285.17:15:43.01#ibcon#enter sib2, iclass 22, count 2 2006.285.17:15:43.01#ibcon#flushed, iclass 22, count 2 2006.285.17:15:43.01#ibcon#about to write, iclass 22, count 2 2006.285.17:15:43.01#ibcon#wrote, iclass 22, count 2 2006.285.17:15:43.01#ibcon#about to read 3, iclass 22, count 2 2006.285.17:15:43.03#ibcon#read 3, iclass 22, count 2 2006.285.17:15:43.03#ibcon#about to read 4, iclass 22, count 2 2006.285.17:15:43.03#ibcon#read 4, iclass 22, count 2 2006.285.17:15:43.03#ibcon#about to read 5, iclass 22, count 2 2006.285.17:15:43.03#ibcon#read 5, iclass 22, count 2 2006.285.17:15:43.03#ibcon#about to read 6, iclass 22, count 2 2006.285.17:15:43.03#ibcon#read 6, iclass 22, count 2 2006.285.17:15:43.03#ibcon#end of sib2, iclass 22, count 2 2006.285.17:15:43.03#ibcon#*mode == 0, iclass 22, count 2 2006.285.17:15:43.03#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.17:15:43.03#ibcon#[25=AT02-06\r\n] 2006.285.17:15:43.03#ibcon#*before write, iclass 22, count 2 2006.285.17:15:43.03#ibcon#enter sib2, iclass 22, count 2 2006.285.17:15:43.03#ibcon#flushed, iclass 22, count 2 2006.285.17:15:43.03#ibcon#about to write, iclass 22, count 2 2006.285.17:15:43.03#ibcon#wrote, iclass 22, count 2 2006.285.17:15:43.03#ibcon#about to read 3, iclass 22, count 2 2006.285.17:15:43.06#ibcon#read 3, iclass 22, count 2 2006.285.17:15:43.06#ibcon#about to read 4, iclass 22, count 2 2006.285.17:15:43.06#ibcon#read 4, iclass 22, count 2 2006.285.17:15:43.06#ibcon#about to read 5, iclass 22, count 2 2006.285.17:15:43.06#ibcon#read 5, iclass 22, count 2 2006.285.17:15:43.06#ibcon#about to read 6, iclass 22, count 2 2006.285.17:15:43.06#ibcon#read 6, iclass 22, count 2 2006.285.17:15:43.06#ibcon#end of sib2, iclass 22, count 2 2006.285.17:15:43.06#ibcon#*after write, iclass 22, count 2 2006.285.17:15:43.06#ibcon#*before return 0, iclass 22, count 2 2006.285.17:15:43.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:15:43.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:15:43.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.17:15:43.06#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:43.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:15:43.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:15:43.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:15:43.18#ibcon#enter wrdev, iclass 22, count 0 2006.285.17:15:43.18#ibcon#first serial, iclass 22, count 0 2006.285.17:15:43.18#ibcon#enter sib2, iclass 22, count 0 2006.285.17:15:43.18#ibcon#flushed, iclass 22, count 0 2006.285.17:15:43.18#ibcon#about to write, iclass 22, count 0 2006.285.17:15:43.18#ibcon#wrote, iclass 22, count 0 2006.285.17:15:43.18#ibcon#about to read 3, iclass 22, count 0 2006.285.17:15:43.20#ibcon#read 3, iclass 22, count 0 2006.285.17:15:43.20#ibcon#about to read 4, iclass 22, count 0 2006.285.17:15:43.20#ibcon#read 4, iclass 22, count 0 2006.285.17:15:43.20#ibcon#about to read 5, iclass 22, count 0 2006.285.17:15:43.20#ibcon#read 5, iclass 22, count 0 2006.285.17:15:43.20#ibcon#about to read 6, iclass 22, count 0 2006.285.17:15:43.20#ibcon#read 6, iclass 22, count 0 2006.285.17:15:43.20#ibcon#end of sib2, iclass 22, count 0 2006.285.17:15:43.20#ibcon#*mode == 0, iclass 22, count 0 2006.285.17:15:43.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.17:15:43.20#ibcon#[25=USB\r\n] 2006.285.17:15:43.20#ibcon#*before write, iclass 22, count 0 2006.285.17:15:43.20#ibcon#enter sib2, iclass 22, count 0 2006.285.17:15:43.20#ibcon#flushed, iclass 22, count 0 2006.285.17:15:43.20#ibcon#about to write, iclass 22, count 0 2006.285.17:15:43.20#ibcon#wrote, iclass 22, count 0 2006.285.17:15:43.20#ibcon#about to read 3, iclass 22, count 0 2006.285.17:15:43.23#ibcon#read 3, iclass 22, count 0 2006.285.17:15:43.23#ibcon#about to read 4, iclass 22, count 0 2006.285.17:15:43.23#ibcon#read 4, iclass 22, count 0 2006.285.17:15:43.23#ibcon#about to read 5, iclass 22, count 0 2006.285.17:15:43.23#ibcon#read 5, iclass 22, count 0 2006.285.17:15:43.23#ibcon#about to read 6, iclass 22, count 0 2006.285.17:15:43.23#ibcon#read 6, iclass 22, count 0 2006.285.17:15:43.23#ibcon#end of sib2, iclass 22, count 0 2006.285.17:15:43.23#ibcon#*after write, iclass 22, count 0 2006.285.17:15:43.23#ibcon#*before return 0, iclass 22, count 0 2006.285.17:15:43.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:15:43.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:15:43.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.17:15:43.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.17:15:43.23$vck44/valo=3,564.99 2006.285.17:15:43.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.17:15:43.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.17:15:43.23#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:43.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:15:43.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:15:43.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:15:43.23#ibcon#enter wrdev, iclass 24, count 0 2006.285.17:15:43.23#ibcon#first serial, iclass 24, count 0 2006.285.17:15:43.23#ibcon#enter sib2, iclass 24, count 0 2006.285.17:15:43.23#ibcon#flushed, iclass 24, count 0 2006.285.17:15:43.23#ibcon#about to write, iclass 24, count 0 2006.285.17:15:43.23#ibcon#wrote, iclass 24, count 0 2006.285.17:15:43.23#ibcon#about to read 3, iclass 24, count 0 2006.285.17:15:43.25#ibcon#read 3, iclass 24, count 0 2006.285.17:15:43.25#ibcon#about to read 4, iclass 24, count 0 2006.285.17:15:43.25#ibcon#read 4, iclass 24, count 0 2006.285.17:15:43.25#ibcon#about to read 5, iclass 24, count 0 2006.285.17:15:43.25#ibcon#read 5, iclass 24, count 0 2006.285.17:15:43.25#ibcon#about to read 6, iclass 24, count 0 2006.285.17:15:43.25#ibcon#read 6, iclass 24, count 0 2006.285.17:15:43.25#ibcon#end of sib2, iclass 24, count 0 2006.285.17:15:43.25#ibcon#*mode == 0, iclass 24, count 0 2006.285.17:15:43.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.17:15:43.25#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.17:15:43.25#ibcon#*before write, iclass 24, count 0 2006.285.17:15:43.25#ibcon#enter sib2, iclass 24, count 0 2006.285.17:15:43.25#ibcon#flushed, iclass 24, count 0 2006.285.17:15:43.25#ibcon#about to write, iclass 24, count 0 2006.285.17:15:43.25#ibcon#wrote, iclass 24, count 0 2006.285.17:15:43.25#ibcon#about to read 3, iclass 24, count 0 2006.285.17:15:43.29#ibcon#read 3, iclass 24, count 0 2006.285.17:15:43.29#ibcon#about to read 4, iclass 24, count 0 2006.285.17:15:43.29#ibcon#read 4, iclass 24, count 0 2006.285.17:15:43.29#ibcon#about to read 5, iclass 24, count 0 2006.285.17:15:43.29#ibcon#read 5, iclass 24, count 0 2006.285.17:15:43.29#ibcon#about to read 6, iclass 24, count 0 2006.285.17:15:43.29#ibcon#read 6, iclass 24, count 0 2006.285.17:15:43.29#ibcon#end of sib2, iclass 24, count 0 2006.285.17:15:43.29#ibcon#*after write, iclass 24, count 0 2006.285.17:15:43.29#ibcon#*before return 0, iclass 24, count 0 2006.285.17:15:43.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:15:43.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:15:43.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.17:15:43.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.17:15:43.29$vck44/va=3,7 2006.285.17:15:43.29#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.17:15:43.29#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.17:15:43.29#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:43.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:15:43.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:15:43.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:15:43.35#ibcon#enter wrdev, iclass 26, count 2 2006.285.17:15:43.35#ibcon#first serial, iclass 26, count 2 2006.285.17:15:43.35#ibcon#enter sib2, iclass 26, count 2 2006.285.17:15:43.35#ibcon#flushed, iclass 26, count 2 2006.285.17:15:43.35#ibcon#about to write, iclass 26, count 2 2006.285.17:15:43.35#ibcon#wrote, iclass 26, count 2 2006.285.17:15:43.35#ibcon#about to read 3, iclass 26, count 2 2006.285.17:15:43.37#ibcon#read 3, iclass 26, count 2 2006.285.17:15:43.37#ibcon#about to read 4, iclass 26, count 2 2006.285.17:15:43.37#ibcon#read 4, iclass 26, count 2 2006.285.17:15:43.37#ibcon#about to read 5, iclass 26, count 2 2006.285.17:15:43.37#ibcon#read 5, iclass 26, count 2 2006.285.17:15:43.37#ibcon#about to read 6, iclass 26, count 2 2006.285.17:15:43.37#ibcon#read 6, iclass 26, count 2 2006.285.17:15:43.37#ibcon#end of sib2, iclass 26, count 2 2006.285.17:15:43.37#ibcon#*mode == 0, iclass 26, count 2 2006.285.17:15:43.37#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.17:15:43.37#ibcon#[25=AT03-07\r\n] 2006.285.17:15:43.37#ibcon#*before write, iclass 26, count 2 2006.285.17:15:43.37#ibcon#enter sib2, iclass 26, count 2 2006.285.17:15:43.37#ibcon#flushed, iclass 26, count 2 2006.285.17:15:43.37#ibcon#about to write, iclass 26, count 2 2006.285.17:15:43.37#ibcon#wrote, iclass 26, count 2 2006.285.17:15:43.37#ibcon#about to read 3, iclass 26, count 2 2006.285.17:15:43.40#ibcon#read 3, iclass 26, count 2 2006.285.17:15:43.73#ibcon#about to read 4, iclass 26, count 2 2006.285.17:15:43.73#ibcon#read 4, iclass 26, count 2 2006.285.17:15:43.73#ibcon#about to read 5, iclass 26, count 2 2006.285.17:15:43.73#ibcon#read 5, iclass 26, count 2 2006.285.17:15:43.73#ibcon#about to read 6, iclass 26, count 2 2006.285.17:15:43.73#ibcon#read 6, iclass 26, count 2 2006.285.17:15:43.73#ibcon#end of sib2, iclass 26, count 2 2006.285.17:15:43.73#ibcon#*after write, iclass 26, count 2 2006.285.17:15:43.73#ibcon#*before return 0, iclass 26, count 2 2006.285.17:15:43.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:15:43.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:15:43.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.17:15:43.73#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:43.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:15:43.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:15:43.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:15:43.84#ibcon#enter wrdev, iclass 26, count 0 2006.285.17:15:43.84#ibcon#first serial, iclass 26, count 0 2006.285.17:15:43.84#ibcon#enter sib2, iclass 26, count 0 2006.285.17:15:43.84#ibcon#flushed, iclass 26, count 0 2006.285.17:15:43.84#ibcon#about to write, iclass 26, count 0 2006.285.17:15:43.84#ibcon#wrote, iclass 26, count 0 2006.285.17:15:43.84#ibcon#about to read 3, iclass 26, count 0 2006.285.17:15:43.86#ibcon#read 3, iclass 26, count 0 2006.285.17:15:43.86#ibcon#about to read 4, iclass 26, count 0 2006.285.17:15:43.86#ibcon#read 4, iclass 26, count 0 2006.285.17:15:43.86#ibcon#about to read 5, iclass 26, count 0 2006.285.17:15:43.86#ibcon#read 5, iclass 26, count 0 2006.285.17:15:43.86#ibcon#about to read 6, iclass 26, count 0 2006.285.17:15:43.86#ibcon#read 6, iclass 26, count 0 2006.285.17:15:43.86#ibcon#end of sib2, iclass 26, count 0 2006.285.17:15:43.86#ibcon#*mode == 0, iclass 26, count 0 2006.285.17:15:43.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.17:15:43.86#ibcon#[25=USB\r\n] 2006.285.17:15:43.86#ibcon#*before write, iclass 26, count 0 2006.285.17:15:43.86#ibcon#enter sib2, iclass 26, count 0 2006.285.17:15:43.86#ibcon#flushed, iclass 26, count 0 2006.285.17:15:43.86#ibcon#about to write, iclass 26, count 0 2006.285.17:15:43.86#ibcon#wrote, iclass 26, count 0 2006.285.17:15:43.86#ibcon#about to read 3, iclass 26, count 0 2006.285.17:15:43.89#ibcon#read 3, iclass 26, count 0 2006.285.17:15:43.89#ibcon#about to read 4, iclass 26, count 0 2006.285.17:15:43.89#ibcon#read 4, iclass 26, count 0 2006.285.17:15:43.89#ibcon#about to read 5, iclass 26, count 0 2006.285.17:15:43.89#ibcon#read 5, iclass 26, count 0 2006.285.17:15:43.89#ibcon#about to read 6, iclass 26, count 0 2006.285.17:15:43.89#ibcon#read 6, iclass 26, count 0 2006.285.17:15:43.89#ibcon#end of sib2, iclass 26, count 0 2006.285.17:15:43.89#ibcon#*after write, iclass 26, count 0 2006.285.17:15:43.89#ibcon#*before return 0, iclass 26, count 0 2006.285.17:15:43.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:15:43.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:15:43.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.17:15:43.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.17:15:43.89$vck44/valo=4,624.99 2006.285.17:15:43.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.17:15:43.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.17:15:43.89#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:43.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:15:43.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:15:43.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:15:43.89#ibcon#enter wrdev, iclass 28, count 0 2006.285.17:15:43.89#ibcon#first serial, iclass 28, count 0 2006.285.17:15:43.89#ibcon#enter sib2, iclass 28, count 0 2006.285.17:15:43.89#ibcon#flushed, iclass 28, count 0 2006.285.17:15:43.89#ibcon#about to write, iclass 28, count 0 2006.285.17:15:43.89#ibcon#wrote, iclass 28, count 0 2006.285.17:15:43.89#ibcon#about to read 3, iclass 28, count 0 2006.285.17:15:43.91#ibcon#read 3, iclass 28, count 0 2006.285.17:15:43.91#ibcon#about to read 4, iclass 28, count 0 2006.285.17:15:43.91#ibcon#read 4, iclass 28, count 0 2006.285.17:15:43.91#ibcon#about to read 5, iclass 28, count 0 2006.285.17:15:43.91#ibcon#read 5, iclass 28, count 0 2006.285.17:15:43.91#ibcon#about to read 6, iclass 28, count 0 2006.285.17:15:43.91#ibcon#read 6, iclass 28, count 0 2006.285.17:15:43.91#ibcon#end of sib2, iclass 28, count 0 2006.285.17:15:43.91#ibcon#*mode == 0, iclass 28, count 0 2006.285.17:15:43.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.17:15:43.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.17:15:43.91#ibcon#*before write, iclass 28, count 0 2006.285.17:15:43.91#ibcon#enter sib2, iclass 28, count 0 2006.285.17:15:43.91#ibcon#flushed, iclass 28, count 0 2006.285.17:15:43.91#ibcon#about to write, iclass 28, count 0 2006.285.17:15:43.91#ibcon#wrote, iclass 28, count 0 2006.285.17:15:43.91#ibcon#about to read 3, iclass 28, count 0 2006.285.17:15:43.95#ibcon#read 3, iclass 28, count 0 2006.285.17:15:43.95#ibcon#about to read 4, iclass 28, count 0 2006.285.17:15:43.95#ibcon#read 4, iclass 28, count 0 2006.285.17:15:43.95#ibcon#about to read 5, iclass 28, count 0 2006.285.17:15:43.95#ibcon#read 5, iclass 28, count 0 2006.285.17:15:43.95#ibcon#about to read 6, iclass 28, count 0 2006.285.17:15:43.95#ibcon#read 6, iclass 28, count 0 2006.285.17:15:43.95#ibcon#end of sib2, iclass 28, count 0 2006.285.17:15:43.95#ibcon#*after write, iclass 28, count 0 2006.285.17:15:43.95#ibcon#*before return 0, iclass 28, count 0 2006.285.17:15:43.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:15:43.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:15:43.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.17:15:43.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.17:15:43.95$vck44/va=4,6 2006.285.17:15:44.23#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.17:15:44.23#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.17:15:44.23#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:44.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:15:44.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:15:44.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:15:44.23#ibcon#enter wrdev, iclass 30, count 2 2006.285.17:15:44.23#ibcon#first serial, iclass 30, count 2 2006.285.17:15:44.23#ibcon#enter sib2, iclass 30, count 2 2006.285.17:15:44.23#ibcon#flushed, iclass 30, count 2 2006.285.17:15:44.23#ibcon#about to write, iclass 30, count 2 2006.285.17:15:44.23#ibcon#wrote, iclass 30, count 2 2006.285.17:15:44.23#ibcon#about to read 3, iclass 30, count 2 2006.285.17:15:44.24#ibcon#read 3, iclass 30, count 2 2006.285.17:15:44.24#ibcon#about to read 4, iclass 30, count 2 2006.285.17:15:44.24#ibcon#read 4, iclass 30, count 2 2006.285.17:15:44.24#ibcon#about to read 5, iclass 30, count 2 2006.285.17:15:44.24#ibcon#read 5, iclass 30, count 2 2006.285.17:15:44.24#ibcon#about to read 6, iclass 30, count 2 2006.285.17:15:44.24#ibcon#read 6, iclass 30, count 2 2006.285.17:15:44.24#ibcon#end of sib2, iclass 30, count 2 2006.285.17:15:44.24#ibcon#*mode == 0, iclass 30, count 2 2006.285.17:15:44.24#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.17:15:44.24#ibcon#[25=AT04-06\r\n] 2006.285.17:15:44.24#ibcon#*before write, iclass 30, count 2 2006.285.17:15:44.24#ibcon#enter sib2, iclass 30, count 2 2006.285.17:15:44.24#ibcon#flushed, iclass 30, count 2 2006.285.17:15:44.24#ibcon#about to write, iclass 30, count 2 2006.285.17:15:44.24#ibcon#wrote, iclass 30, count 2 2006.285.17:15:44.24#ibcon#about to read 3, iclass 30, count 2 2006.285.17:15:44.27#ibcon#read 3, iclass 30, count 2 2006.285.17:15:44.27#ibcon#about to read 4, iclass 30, count 2 2006.285.17:15:44.27#ibcon#read 4, iclass 30, count 2 2006.285.17:15:44.27#ibcon#about to read 5, iclass 30, count 2 2006.285.17:15:44.27#ibcon#read 5, iclass 30, count 2 2006.285.17:15:44.27#ibcon#about to read 6, iclass 30, count 2 2006.285.17:15:44.27#ibcon#read 6, iclass 30, count 2 2006.285.17:15:44.27#ibcon#end of sib2, iclass 30, count 2 2006.285.17:15:44.27#ibcon#*after write, iclass 30, count 2 2006.285.17:15:44.27#ibcon#*before return 0, iclass 30, count 2 2006.285.17:15:44.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:15:44.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:15:44.27#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.17:15:44.27#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:44.27#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:15:44.39#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:15:44.39#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:15:44.39#ibcon#enter wrdev, iclass 30, count 0 2006.285.17:15:44.39#ibcon#first serial, iclass 30, count 0 2006.285.17:15:44.39#ibcon#enter sib2, iclass 30, count 0 2006.285.17:15:44.39#ibcon#flushed, iclass 30, count 0 2006.285.17:15:44.39#ibcon#about to write, iclass 30, count 0 2006.285.17:15:44.39#ibcon#wrote, iclass 30, count 0 2006.285.17:15:44.39#ibcon#about to read 3, iclass 30, count 0 2006.285.17:15:44.41#ibcon#read 3, iclass 30, count 0 2006.285.17:15:44.41#ibcon#about to read 4, iclass 30, count 0 2006.285.17:15:44.41#ibcon#read 4, iclass 30, count 0 2006.285.17:15:44.41#ibcon#about to read 5, iclass 30, count 0 2006.285.17:15:44.41#ibcon#read 5, iclass 30, count 0 2006.285.17:15:44.41#ibcon#about to read 6, iclass 30, count 0 2006.285.17:15:44.41#ibcon#read 6, iclass 30, count 0 2006.285.17:15:44.41#ibcon#end of sib2, iclass 30, count 0 2006.285.17:15:44.41#ibcon#*mode == 0, iclass 30, count 0 2006.285.17:15:44.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.17:15:44.41#ibcon#[25=USB\r\n] 2006.285.17:15:44.41#ibcon#*before write, iclass 30, count 0 2006.285.17:15:44.41#ibcon#enter sib2, iclass 30, count 0 2006.285.17:15:44.41#ibcon#flushed, iclass 30, count 0 2006.285.17:15:44.41#ibcon#about to write, iclass 30, count 0 2006.285.17:15:44.41#ibcon#wrote, iclass 30, count 0 2006.285.17:15:44.41#ibcon#about to read 3, iclass 30, count 0 2006.285.17:15:44.44#ibcon#read 3, iclass 30, count 0 2006.285.17:15:44.44#ibcon#about to read 4, iclass 30, count 0 2006.285.17:15:44.44#ibcon#read 4, iclass 30, count 0 2006.285.17:15:44.44#ibcon#about to read 5, iclass 30, count 0 2006.285.17:15:44.44#ibcon#read 5, iclass 30, count 0 2006.285.17:15:44.44#ibcon#about to read 6, iclass 30, count 0 2006.285.17:15:44.44#ibcon#read 6, iclass 30, count 0 2006.285.17:15:44.44#ibcon#end of sib2, iclass 30, count 0 2006.285.17:15:44.44#ibcon#*after write, iclass 30, count 0 2006.285.17:15:44.44#ibcon#*before return 0, iclass 30, count 0 2006.285.17:15:44.44#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:15:44.44#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:15:44.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.17:15:44.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.17:15:44.44$vck44/valo=5,734.99 2006.285.17:15:44.44#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.17:15:44.44#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.17:15:44.44#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:44.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:15:44.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:15:44.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:15:44.44#ibcon#enter wrdev, iclass 32, count 0 2006.285.17:15:44.44#ibcon#first serial, iclass 32, count 0 2006.285.17:15:44.44#ibcon#enter sib2, iclass 32, count 0 2006.285.17:15:44.44#ibcon#flushed, iclass 32, count 0 2006.285.17:15:44.44#ibcon#about to write, iclass 32, count 0 2006.285.17:15:44.44#ibcon#wrote, iclass 32, count 0 2006.285.17:15:44.44#ibcon#about to read 3, iclass 32, count 0 2006.285.17:15:44.46#ibcon#read 3, iclass 32, count 0 2006.285.17:15:44.58#ibcon#about to read 4, iclass 32, count 0 2006.285.17:15:44.58#ibcon#read 4, iclass 32, count 0 2006.285.17:15:44.58#ibcon#about to read 5, iclass 32, count 0 2006.285.17:15:44.58#ibcon#read 5, iclass 32, count 0 2006.285.17:15:44.58#ibcon#about to read 6, iclass 32, count 0 2006.285.17:15:44.58#ibcon#read 6, iclass 32, count 0 2006.285.17:15:44.58#ibcon#end of sib2, iclass 32, count 0 2006.285.17:15:44.58#ibcon#*mode == 0, iclass 32, count 0 2006.285.17:15:44.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.17:15:44.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.17:15:44.58#ibcon#*before write, iclass 32, count 0 2006.285.17:15:44.58#ibcon#enter sib2, iclass 32, count 0 2006.285.17:15:44.58#ibcon#flushed, iclass 32, count 0 2006.285.17:15:44.58#ibcon#about to write, iclass 32, count 0 2006.285.17:15:44.58#ibcon#wrote, iclass 32, count 0 2006.285.17:15:44.58#ibcon#about to read 3, iclass 32, count 0 2006.285.17:15:44.61#ibcon#read 3, iclass 32, count 0 2006.285.17:15:44.61#ibcon#about to read 4, iclass 32, count 0 2006.285.17:15:44.61#ibcon#read 4, iclass 32, count 0 2006.285.17:15:44.61#ibcon#about to read 5, iclass 32, count 0 2006.285.17:15:44.61#ibcon#read 5, iclass 32, count 0 2006.285.17:15:44.61#ibcon#about to read 6, iclass 32, count 0 2006.285.17:15:44.61#ibcon#read 6, iclass 32, count 0 2006.285.17:15:44.61#ibcon#end of sib2, iclass 32, count 0 2006.285.17:15:44.61#ibcon#*after write, iclass 32, count 0 2006.285.17:15:44.61#ibcon#*before return 0, iclass 32, count 0 2006.285.17:15:44.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:15:44.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:15:44.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.17:15:44.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.17:15:44.61$vck44/va=5,3 2006.285.17:15:44.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.17:15:44.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.17:15:44.61#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:44.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:15:44.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:15:44.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:15:44.61#ibcon#enter wrdev, iclass 34, count 2 2006.285.17:15:44.61#ibcon#first serial, iclass 34, count 2 2006.285.17:15:44.61#ibcon#enter sib2, iclass 34, count 2 2006.285.17:15:44.61#ibcon#flushed, iclass 34, count 2 2006.285.17:15:44.61#ibcon#about to write, iclass 34, count 2 2006.285.17:15:44.61#ibcon#wrote, iclass 34, count 2 2006.285.17:15:44.61#ibcon#about to read 3, iclass 34, count 2 2006.285.17:15:44.63#ibcon#read 3, iclass 34, count 2 2006.285.17:15:44.63#ibcon#about to read 4, iclass 34, count 2 2006.285.17:15:44.63#ibcon#read 4, iclass 34, count 2 2006.285.17:15:44.63#ibcon#about to read 5, iclass 34, count 2 2006.285.17:15:44.63#ibcon#read 5, iclass 34, count 2 2006.285.17:15:44.63#ibcon#about to read 6, iclass 34, count 2 2006.285.17:15:44.63#ibcon#read 6, iclass 34, count 2 2006.285.17:15:44.63#ibcon#end of sib2, iclass 34, count 2 2006.285.17:15:44.63#ibcon#*mode == 0, iclass 34, count 2 2006.285.17:15:44.63#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.17:15:44.63#ibcon#[25=AT05-03\r\n] 2006.285.17:15:44.63#ibcon#*before write, iclass 34, count 2 2006.285.17:15:44.63#ibcon#enter sib2, iclass 34, count 2 2006.285.17:15:44.63#ibcon#flushed, iclass 34, count 2 2006.285.17:15:44.63#ibcon#about to write, iclass 34, count 2 2006.285.17:15:44.63#ibcon#wrote, iclass 34, count 2 2006.285.17:15:44.63#ibcon#about to read 3, iclass 34, count 2 2006.285.17:15:44.66#ibcon#read 3, iclass 34, count 2 2006.285.17:15:44.66#ibcon#about to read 4, iclass 34, count 2 2006.285.17:15:44.66#ibcon#read 4, iclass 34, count 2 2006.285.17:15:44.66#ibcon#about to read 5, iclass 34, count 2 2006.285.17:15:44.66#ibcon#read 5, iclass 34, count 2 2006.285.17:15:44.66#ibcon#about to read 6, iclass 34, count 2 2006.285.17:15:44.66#ibcon#read 6, iclass 34, count 2 2006.285.17:15:44.66#ibcon#end of sib2, iclass 34, count 2 2006.285.17:15:44.66#ibcon#*after write, iclass 34, count 2 2006.285.17:15:44.66#ibcon#*before return 0, iclass 34, count 2 2006.285.17:15:44.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:15:44.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:15:44.66#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.17:15:44.66#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:44.66#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:15:44.78#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:15:44.78#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:15:44.78#ibcon#enter wrdev, iclass 34, count 0 2006.285.17:15:44.78#ibcon#first serial, iclass 34, count 0 2006.285.17:15:44.78#ibcon#enter sib2, iclass 34, count 0 2006.285.17:15:44.78#ibcon#flushed, iclass 34, count 0 2006.285.17:15:44.78#ibcon#about to write, iclass 34, count 0 2006.285.17:15:44.78#ibcon#wrote, iclass 34, count 0 2006.285.17:15:44.78#ibcon#about to read 3, iclass 34, count 0 2006.285.17:15:44.80#ibcon#read 3, iclass 34, count 0 2006.285.17:15:44.80#ibcon#about to read 4, iclass 34, count 0 2006.285.17:15:44.80#ibcon#read 4, iclass 34, count 0 2006.285.17:15:44.80#ibcon#about to read 5, iclass 34, count 0 2006.285.17:15:44.80#ibcon#read 5, iclass 34, count 0 2006.285.17:15:44.80#ibcon#about to read 6, iclass 34, count 0 2006.285.17:15:44.80#ibcon#read 6, iclass 34, count 0 2006.285.17:15:44.80#ibcon#end of sib2, iclass 34, count 0 2006.285.17:15:44.80#ibcon#*mode == 0, iclass 34, count 0 2006.285.17:15:44.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.17:15:44.80#ibcon#[25=USB\r\n] 2006.285.17:15:44.80#ibcon#*before write, iclass 34, count 0 2006.285.17:15:44.80#ibcon#enter sib2, iclass 34, count 0 2006.285.17:15:44.80#ibcon#flushed, iclass 34, count 0 2006.285.17:15:44.80#ibcon#about to write, iclass 34, count 0 2006.285.17:15:44.80#ibcon#wrote, iclass 34, count 0 2006.285.17:15:44.80#ibcon#about to read 3, iclass 34, count 0 2006.285.17:15:44.83#ibcon#read 3, iclass 34, count 0 2006.285.17:15:44.83#ibcon#about to read 4, iclass 34, count 0 2006.285.17:15:44.83#ibcon#read 4, iclass 34, count 0 2006.285.17:15:44.83#ibcon#about to read 5, iclass 34, count 0 2006.285.17:15:44.83#ibcon#read 5, iclass 34, count 0 2006.285.17:15:44.83#ibcon#about to read 6, iclass 34, count 0 2006.285.17:15:44.83#ibcon#read 6, iclass 34, count 0 2006.285.17:15:44.83#ibcon#end of sib2, iclass 34, count 0 2006.285.17:15:44.83#ibcon#*after write, iclass 34, count 0 2006.285.17:15:44.83#ibcon#*before return 0, iclass 34, count 0 2006.285.17:15:44.83#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:15:44.83#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:15:44.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.17:15:44.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.17:15:44.83$vck44/valo=6,814.99 2006.285.17:15:44.83#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.17:15:44.83#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.17:15:44.83#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:44.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:15:44.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:15:44.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:15:44.83#ibcon#enter wrdev, iclass 36, count 0 2006.285.17:15:44.83#ibcon#first serial, iclass 36, count 0 2006.285.17:15:44.83#ibcon#enter sib2, iclass 36, count 0 2006.285.17:15:44.83#ibcon#flushed, iclass 36, count 0 2006.285.17:15:44.83#ibcon#about to write, iclass 36, count 0 2006.285.17:15:44.83#ibcon#wrote, iclass 36, count 0 2006.285.17:15:44.83#ibcon#about to read 3, iclass 36, count 0 2006.285.17:15:44.85#ibcon#read 3, iclass 36, count 0 2006.285.17:15:44.85#ibcon#about to read 4, iclass 36, count 0 2006.285.17:15:44.85#ibcon#read 4, iclass 36, count 0 2006.285.17:15:44.85#ibcon#about to read 5, iclass 36, count 0 2006.285.17:15:44.85#ibcon#read 5, iclass 36, count 0 2006.285.17:15:44.85#ibcon#about to read 6, iclass 36, count 0 2006.285.17:15:44.85#ibcon#read 6, iclass 36, count 0 2006.285.17:15:44.85#ibcon#end of sib2, iclass 36, count 0 2006.285.17:15:44.85#ibcon#*mode == 0, iclass 36, count 0 2006.285.17:15:44.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.17:15:44.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.17:15:44.85#ibcon#*before write, iclass 36, count 0 2006.285.17:15:44.85#ibcon#enter sib2, iclass 36, count 0 2006.285.17:15:44.85#ibcon#flushed, iclass 36, count 0 2006.285.17:15:44.85#ibcon#about to write, iclass 36, count 0 2006.285.17:15:44.85#ibcon#wrote, iclass 36, count 0 2006.285.17:15:44.85#ibcon#about to read 3, iclass 36, count 0 2006.285.17:15:44.89#ibcon#read 3, iclass 36, count 0 2006.285.17:15:44.89#ibcon#about to read 4, iclass 36, count 0 2006.285.17:15:44.89#ibcon#read 4, iclass 36, count 0 2006.285.17:15:44.89#ibcon#about to read 5, iclass 36, count 0 2006.285.17:15:44.89#ibcon#read 5, iclass 36, count 0 2006.285.17:15:44.89#ibcon#about to read 6, iclass 36, count 0 2006.285.17:15:44.89#ibcon#read 6, iclass 36, count 0 2006.285.17:15:44.89#ibcon#end of sib2, iclass 36, count 0 2006.285.17:15:44.89#ibcon#*after write, iclass 36, count 0 2006.285.17:15:44.89#ibcon#*before return 0, iclass 36, count 0 2006.285.17:15:44.89#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:15:44.89#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:15:44.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.17:15:44.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.17:15:44.89$vck44/va=6,4 2006.285.17:15:44.89#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.17:15:44.89#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.17:15:44.89#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:44.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:15:44.92#abcon#<5=/13 0.3 1.2 17.12 971014.8\r\n> 2006.285.17:15:44.94#abcon#{5=INTERFACE CLEAR} 2006.285.17:15:44.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:15:44.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:15:44.95#ibcon#enter wrdev, iclass 39, count 2 2006.285.17:15:44.95#ibcon#first serial, iclass 39, count 2 2006.285.17:15:44.95#ibcon#enter sib2, iclass 39, count 2 2006.285.17:15:44.95#ibcon#flushed, iclass 39, count 2 2006.285.17:15:44.95#ibcon#about to write, iclass 39, count 2 2006.285.17:15:44.95#ibcon#wrote, iclass 39, count 2 2006.285.17:15:44.95#ibcon#about to read 3, iclass 39, count 2 2006.285.17:15:44.97#ibcon#read 3, iclass 39, count 2 2006.285.17:15:44.97#ibcon#about to read 4, iclass 39, count 2 2006.285.17:15:44.97#ibcon#read 4, iclass 39, count 2 2006.285.17:15:44.97#ibcon#about to read 5, iclass 39, count 2 2006.285.17:15:44.97#ibcon#read 5, iclass 39, count 2 2006.285.17:15:44.97#ibcon#about to read 6, iclass 39, count 2 2006.285.17:15:44.97#ibcon#read 6, iclass 39, count 2 2006.285.17:15:44.97#ibcon#end of sib2, iclass 39, count 2 2006.285.17:15:44.97#ibcon#*mode == 0, iclass 39, count 2 2006.285.17:15:44.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.17:15:44.97#ibcon#[25=AT06-04\r\n] 2006.285.17:15:44.97#ibcon#*before write, iclass 39, count 2 2006.285.17:15:44.97#ibcon#enter sib2, iclass 39, count 2 2006.285.17:15:44.97#ibcon#flushed, iclass 39, count 2 2006.285.17:15:44.97#ibcon#about to write, iclass 39, count 2 2006.285.17:15:44.97#ibcon#wrote, iclass 39, count 2 2006.285.17:15:44.97#ibcon#about to read 3, iclass 39, count 2 2006.285.17:15:45.00#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:15:45.00#ibcon#read 3, iclass 39, count 2 2006.285.17:15:45.00#ibcon#about to read 4, iclass 39, count 2 2006.285.17:15:45.00#ibcon#read 4, iclass 39, count 2 2006.285.17:15:45.00#ibcon#about to read 5, iclass 39, count 2 2006.285.17:15:45.00#ibcon#read 5, iclass 39, count 2 2006.285.17:15:45.00#ibcon#about to read 6, iclass 39, count 2 2006.285.17:15:45.00#ibcon#read 6, iclass 39, count 2 2006.285.17:15:45.00#ibcon#end of sib2, iclass 39, count 2 2006.285.17:15:45.00#ibcon#*after write, iclass 39, count 2 2006.285.17:15:45.00#ibcon#*before return 0, iclass 39, count 2 2006.285.17:15:45.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:15:45.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:15:45.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.17:15:45.00#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:45.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:15:45.12#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:15:45.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:15:45.12#ibcon#enter wrdev, iclass 39, count 0 2006.285.17:15:45.12#ibcon#first serial, iclass 39, count 0 2006.285.17:15:45.12#ibcon#enter sib2, iclass 39, count 0 2006.285.17:15:45.12#ibcon#flushed, iclass 39, count 0 2006.285.17:15:45.12#ibcon#about to write, iclass 39, count 0 2006.285.17:15:45.12#ibcon#wrote, iclass 39, count 0 2006.285.17:15:45.12#ibcon#about to read 3, iclass 39, count 0 2006.285.17:15:45.14#ibcon#read 3, iclass 39, count 0 2006.285.17:15:45.14#ibcon#about to read 4, iclass 39, count 0 2006.285.17:15:45.14#ibcon#read 4, iclass 39, count 0 2006.285.17:15:45.14#ibcon#about to read 5, iclass 39, count 0 2006.285.17:15:45.14#ibcon#read 5, iclass 39, count 0 2006.285.17:15:45.14#ibcon#about to read 6, iclass 39, count 0 2006.285.17:15:45.14#ibcon#read 6, iclass 39, count 0 2006.285.17:15:45.14#ibcon#end of sib2, iclass 39, count 0 2006.285.17:15:45.14#ibcon#*mode == 0, iclass 39, count 0 2006.285.17:15:45.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.17:15:45.14#ibcon#[25=USB\r\n] 2006.285.17:15:45.14#ibcon#*before write, iclass 39, count 0 2006.285.17:15:45.14#ibcon#enter sib2, iclass 39, count 0 2006.285.17:15:45.14#ibcon#flushed, iclass 39, count 0 2006.285.17:15:45.14#ibcon#about to write, iclass 39, count 0 2006.285.17:15:45.14#ibcon#wrote, iclass 39, count 0 2006.285.17:15:45.14#ibcon#about to read 3, iclass 39, count 0 2006.285.17:15:45.17#ibcon#read 3, iclass 39, count 0 2006.285.17:15:45.17#ibcon#about to read 4, iclass 39, count 0 2006.285.17:15:45.17#ibcon#read 4, iclass 39, count 0 2006.285.17:15:45.17#ibcon#about to read 5, iclass 39, count 0 2006.285.17:15:45.17#ibcon#read 5, iclass 39, count 0 2006.285.17:15:45.17#ibcon#about to read 6, iclass 39, count 0 2006.285.17:15:45.17#ibcon#read 6, iclass 39, count 0 2006.285.17:15:45.17#ibcon#end of sib2, iclass 39, count 0 2006.285.17:15:45.17#ibcon#*after write, iclass 39, count 0 2006.285.17:15:45.17#ibcon#*before return 0, iclass 39, count 0 2006.285.17:15:45.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:15:45.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:15:45.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.17:15:45.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.17:15:45.17$vck44/valo=7,864.99 2006.285.17:15:45.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.17:15:45.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.17:15:45.17#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:45.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:15:45.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:15:45.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:15:45.17#ibcon#enter wrdev, iclass 6, count 0 2006.285.17:15:45.17#ibcon#first serial, iclass 6, count 0 2006.285.17:15:45.17#ibcon#enter sib2, iclass 6, count 0 2006.285.17:15:45.17#ibcon#flushed, iclass 6, count 0 2006.285.17:15:45.17#ibcon#about to write, iclass 6, count 0 2006.285.17:15:45.17#ibcon#wrote, iclass 6, count 0 2006.285.17:15:45.17#ibcon#about to read 3, iclass 6, count 0 2006.285.17:15:45.19#ibcon#read 3, iclass 6, count 0 2006.285.17:15:45.19#ibcon#about to read 4, iclass 6, count 0 2006.285.17:15:45.19#ibcon#read 4, iclass 6, count 0 2006.285.17:15:45.19#ibcon#about to read 5, iclass 6, count 0 2006.285.17:15:45.19#ibcon#read 5, iclass 6, count 0 2006.285.17:15:45.19#ibcon#about to read 6, iclass 6, count 0 2006.285.17:15:45.19#ibcon#read 6, iclass 6, count 0 2006.285.17:15:45.19#ibcon#end of sib2, iclass 6, count 0 2006.285.17:15:45.19#ibcon#*mode == 0, iclass 6, count 0 2006.285.17:15:45.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.17:15:45.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.17:15:45.19#ibcon#*before write, iclass 6, count 0 2006.285.17:15:45.19#ibcon#enter sib2, iclass 6, count 0 2006.285.17:15:45.19#ibcon#flushed, iclass 6, count 0 2006.285.17:15:45.19#ibcon#about to write, iclass 6, count 0 2006.285.17:15:45.19#ibcon#wrote, iclass 6, count 0 2006.285.17:15:45.19#ibcon#about to read 3, iclass 6, count 0 2006.285.17:15:45.23#ibcon#read 3, iclass 6, count 0 2006.285.17:15:45.23#ibcon#about to read 4, iclass 6, count 0 2006.285.17:15:45.23#ibcon#read 4, iclass 6, count 0 2006.285.17:15:45.23#ibcon#about to read 5, iclass 6, count 0 2006.285.17:15:45.23#ibcon#read 5, iclass 6, count 0 2006.285.17:15:45.23#ibcon#about to read 6, iclass 6, count 0 2006.285.17:15:45.23#ibcon#read 6, iclass 6, count 0 2006.285.17:15:45.23#ibcon#end of sib2, iclass 6, count 0 2006.285.17:15:45.23#ibcon#*after write, iclass 6, count 0 2006.285.17:15:45.23#ibcon#*before return 0, iclass 6, count 0 2006.285.17:15:45.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:15:45.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:15:45.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.17:15:45.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.17:15:45.23$vck44/va=7,4 2006.285.17:15:45.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.17:15:45.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.17:15:45.23#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:45.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:15:45.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:15:45.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:15:45.29#ibcon#enter wrdev, iclass 10, count 2 2006.285.17:15:45.29#ibcon#first serial, iclass 10, count 2 2006.285.17:15:45.29#ibcon#enter sib2, iclass 10, count 2 2006.285.17:15:45.29#ibcon#flushed, iclass 10, count 2 2006.285.17:15:45.29#ibcon#about to write, iclass 10, count 2 2006.285.17:15:45.29#ibcon#wrote, iclass 10, count 2 2006.285.17:15:45.29#ibcon#about to read 3, iclass 10, count 2 2006.285.17:15:45.31#ibcon#read 3, iclass 10, count 2 2006.285.17:15:45.31#ibcon#about to read 4, iclass 10, count 2 2006.285.17:15:45.31#ibcon#read 4, iclass 10, count 2 2006.285.17:15:45.31#ibcon#about to read 5, iclass 10, count 2 2006.285.17:15:45.31#ibcon#read 5, iclass 10, count 2 2006.285.17:15:45.31#ibcon#about to read 6, iclass 10, count 2 2006.285.17:15:45.31#ibcon#read 6, iclass 10, count 2 2006.285.17:15:45.31#ibcon#end of sib2, iclass 10, count 2 2006.285.17:15:45.31#ibcon#*mode == 0, iclass 10, count 2 2006.285.17:15:45.31#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.17:15:45.31#ibcon#[25=AT07-04\r\n] 2006.285.17:15:45.31#ibcon#*before write, iclass 10, count 2 2006.285.17:15:45.31#ibcon#enter sib2, iclass 10, count 2 2006.285.17:15:45.31#ibcon#flushed, iclass 10, count 2 2006.285.17:15:45.31#ibcon#about to write, iclass 10, count 2 2006.285.17:15:45.31#ibcon#wrote, iclass 10, count 2 2006.285.17:15:45.31#ibcon#about to read 3, iclass 10, count 2 2006.285.17:15:45.34#ibcon#read 3, iclass 10, count 2 2006.285.17:15:45.34#ibcon#about to read 4, iclass 10, count 2 2006.285.17:15:45.34#ibcon#read 4, iclass 10, count 2 2006.285.17:15:45.34#ibcon#about to read 5, iclass 10, count 2 2006.285.17:15:45.34#ibcon#read 5, iclass 10, count 2 2006.285.17:15:45.34#ibcon#about to read 6, iclass 10, count 2 2006.285.17:15:45.34#ibcon#read 6, iclass 10, count 2 2006.285.17:15:45.34#ibcon#end of sib2, iclass 10, count 2 2006.285.17:15:45.34#ibcon#*after write, iclass 10, count 2 2006.285.17:15:45.34#ibcon#*before return 0, iclass 10, count 2 2006.285.17:15:45.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:15:45.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:15:45.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.17:15:45.34#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:45.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:15:45.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:15:45.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:15:45.55#ibcon#enter wrdev, iclass 10, count 0 2006.285.17:15:45.55#ibcon#first serial, iclass 10, count 0 2006.285.17:15:45.55#ibcon#enter sib2, iclass 10, count 0 2006.285.17:15:45.55#ibcon#flushed, iclass 10, count 0 2006.285.17:15:45.55#ibcon#about to write, iclass 10, count 0 2006.285.17:15:45.55#ibcon#wrote, iclass 10, count 0 2006.285.17:15:45.55#ibcon#about to read 3, iclass 10, count 0 2006.285.17:15:45.57#ibcon#read 3, iclass 10, count 0 2006.285.17:15:45.57#ibcon#about to read 4, iclass 10, count 0 2006.285.17:15:45.57#ibcon#read 4, iclass 10, count 0 2006.285.17:15:45.57#ibcon#about to read 5, iclass 10, count 0 2006.285.17:15:45.57#ibcon#read 5, iclass 10, count 0 2006.285.17:15:45.57#ibcon#about to read 6, iclass 10, count 0 2006.285.17:15:45.57#ibcon#read 6, iclass 10, count 0 2006.285.17:15:45.57#ibcon#end of sib2, iclass 10, count 0 2006.285.17:15:45.57#ibcon#*mode == 0, iclass 10, count 0 2006.285.17:15:45.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.17:15:45.57#ibcon#[25=USB\r\n] 2006.285.17:15:45.57#ibcon#*before write, iclass 10, count 0 2006.285.17:15:45.57#ibcon#enter sib2, iclass 10, count 0 2006.285.17:15:45.57#ibcon#flushed, iclass 10, count 0 2006.285.17:15:45.57#ibcon#about to write, iclass 10, count 0 2006.285.17:15:45.57#ibcon#wrote, iclass 10, count 0 2006.285.17:15:45.57#ibcon#about to read 3, iclass 10, count 0 2006.285.17:15:45.60#ibcon#read 3, iclass 10, count 0 2006.285.17:15:45.60#ibcon#about to read 4, iclass 10, count 0 2006.285.17:15:45.60#ibcon#read 4, iclass 10, count 0 2006.285.17:15:45.60#ibcon#about to read 5, iclass 10, count 0 2006.285.17:15:45.60#ibcon#read 5, iclass 10, count 0 2006.285.17:15:45.60#ibcon#about to read 6, iclass 10, count 0 2006.285.17:15:45.60#ibcon#read 6, iclass 10, count 0 2006.285.17:15:45.60#ibcon#end of sib2, iclass 10, count 0 2006.285.17:15:45.60#ibcon#*after write, iclass 10, count 0 2006.285.17:15:45.60#ibcon#*before return 0, iclass 10, count 0 2006.285.17:15:45.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:15:45.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:15:45.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.17:15:45.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.17:15:45.60$vck44/valo=8,884.99 2006.285.17:15:45.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.17:15:45.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.17:15:45.60#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:45.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:15:45.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:15:45.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:15:45.60#ibcon#enter wrdev, iclass 12, count 0 2006.285.17:15:45.60#ibcon#first serial, iclass 12, count 0 2006.285.17:15:45.60#ibcon#enter sib2, iclass 12, count 0 2006.285.17:15:45.60#ibcon#flushed, iclass 12, count 0 2006.285.17:15:45.60#ibcon#about to write, iclass 12, count 0 2006.285.17:15:45.60#ibcon#wrote, iclass 12, count 0 2006.285.17:15:45.60#ibcon#about to read 3, iclass 12, count 0 2006.285.17:15:45.62#ibcon#read 3, iclass 12, count 0 2006.285.17:15:45.62#ibcon#about to read 4, iclass 12, count 0 2006.285.17:15:45.62#ibcon#read 4, iclass 12, count 0 2006.285.17:15:45.62#ibcon#about to read 5, iclass 12, count 0 2006.285.17:15:45.62#ibcon#read 5, iclass 12, count 0 2006.285.17:15:45.62#ibcon#about to read 6, iclass 12, count 0 2006.285.17:15:45.62#ibcon#read 6, iclass 12, count 0 2006.285.17:15:45.62#ibcon#end of sib2, iclass 12, count 0 2006.285.17:15:45.62#ibcon#*mode == 0, iclass 12, count 0 2006.285.17:15:45.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.17:15:45.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.17:15:45.62#ibcon#*before write, iclass 12, count 0 2006.285.17:15:45.62#ibcon#enter sib2, iclass 12, count 0 2006.285.17:15:45.62#ibcon#flushed, iclass 12, count 0 2006.285.17:15:45.62#ibcon#about to write, iclass 12, count 0 2006.285.17:15:45.62#ibcon#wrote, iclass 12, count 0 2006.285.17:15:45.62#ibcon#about to read 3, iclass 12, count 0 2006.285.17:15:45.66#ibcon#read 3, iclass 12, count 0 2006.285.17:15:45.66#ibcon#about to read 4, iclass 12, count 0 2006.285.17:15:45.66#ibcon#read 4, iclass 12, count 0 2006.285.17:15:45.66#ibcon#about to read 5, iclass 12, count 0 2006.285.17:15:45.66#ibcon#read 5, iclass 12, count 0 2006.285.17:15:45.66#ibcon#about to read 6, iclass 12, count 0 2006.285.17:15:45.66#ibcon#read 6, iclass 12, count 0 2006.285.17:15:45.66#ibcon#end of sib2, iclass 12, count 0 2006.285.17:15:45.66#ibcon#*after write, iclass 12, count 0 2006.285.17:15:45.66#ibcon#*before return 0, iclass 12, count 0 2006.285.17:15:45.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:15:45.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:15:45.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.17:15:45.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.17:15:45.66$vck44/va=8,3 2006.285.17:15:45.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.17:15:45.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.17:15:45.66#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:45.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:15:45.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:15:45.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:15:45.72#ibcon#enter wrdev, iclass 14, count 2 2006.285.17:15:45.72#ibcon#first serial, iclass 14, count 2 2006.285.17:15:45.72#ibcon#enter sib2, iclass 14, count 2 2006.285.17:15:45.72#ibcon#flushed, iclass 14, count 2 2006.285.17:15:45.72#ibcon#about to write, iclass 14, count 2 2006.285.17:15:45.72#ibcon#wrote, iclass 14, count 2 2006.285.17:15:45.72#ibcon#about to read 3, iclass 14, count 2 2006.285.17:15:45.74#ibcon#read 3, iclass 14, count 2 2006.285.17:15:45.74#ibcon#about to read 4, iclass 14, count 2 2006.285.17:15:45.74#ibcon#read 4, iclass 14, count 2 2006.285.17:15:45.74#ibcon#about to read 5, iclass 14, count 2 2006.285.17:15:45.74#ibcon#read 5, iclass 14, count 2 2006.285.17:15:45.74#ibcon#about to read 6, iclass 14, count 2 2006.285.17:15:45.74#ibcon#read 6, iclass 14, count 2 2006.285.17:15:45.74#ibcon#end of sib2, iclass 14, count 2 2006.285.17:15:45.74#ibcon#*mode == 0, iclass 14, count 2 2006.285.17:15:45.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.17:15:45.74#ibcon#[25=AT08-03\r\n] 2006.285.17:15:45.74#ibcon#*before write, iclass 14, count 2 2006.285.17:15:45.74#ibcon#enter sib2, iclass 14, count 2 2006.285.17:15:45.74#ibcon#flushed, iclass 14, count 2 2006.285.17:15:45.74#ibcon#about to write, iclass 14, count 2 2006.285.17:15:45.74#ibcon#wrote, iclass 14, count 2 2006.285.17:15:45.74#ibcon#about to read 3, iclass 14, count 2 2006.285.17:15:45.77#ibcon#read 3, iclass 14, count 2 2006.285.17:15:45.77#ibcon#about to read 4, iclass 14, count 2 2006.285.17:15:45.77#ibcon#read 4, iclass 14, count 2 2006.285.17:15:45.77#ibcon#about to read 5, iclass 14, count 2 2006.285.17:15:45.77#ibcon#read 5, iclass 14, count 2 2006.285.17:15:45.77#ibcon#about to read 6, iclass 14, count 2 2006.285.17:15:45.77#ibcon#read 6, iclass 14, count 2 2006.285.17:15:45.77#ibcon#end of sib2, iclass 14, count 2 2006.285.17:15:45.77#ibcon#*after write, iclass 14, count 2 2006.285.17:15:45.77#ibcon#*before return 0, iclass 14, count 2 2006.285.17:15:45.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:15:45.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:15:45.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.17:15:45.77#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:45.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:15:45.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:15:45.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:15:45.89#ibcon#enter wrdev, iclass 14, count 0 2006.285.17:15:45.89#ibcon#first serial, iclass 14, count 0 2006.285.17:15:45.89#ibcon#enter sib2, iclass 14, count 0 2006.285.17:15:45.89#ibcon#flushed, iclass 14, count 0 2006.285.17:15:45.89#ibcon#about to write, iclass 14, count 0 2006.285.17:15:45.89#ibcon#wrote, iclass 14, count 0 2006.285.17:15:45.89#ibcon#about to read 3, iclass 14, count 0 2006.285.17:15:45.91#ibcon#read 3, iclass 14, count 0 2006.285.17:15:45.91#ibcon#about to read 4, iclass 14, count 0 2006.285.17:15:45.91#ibcon#read 4, iclass 14, count 0 2006.285.17:15:45.91#ibcon#about to read 5, iclass 14, count 0 2006.285.17:15:45.91#ibcon#read 5, iclass 14, count 0 2006.285.17:15:45.91#ibcon#about to read 6, iclass 14, count 0 2006.285.17:15:45.91#ibcon#read 6, iclass 14, count 0 2006.285.17:15:45.91#ibcon#end of sib2, iclass 14, count 0 2006.285.17:15:45.91#ibcon#*mode == 0, iclass 14, count 0 2006.285.17:15:45.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.17:15:45.91#ibcon#[25=USB\r\n] 2006.285.17:15:45.91#ibcon#*before write, iclass 14, count 0 2006.285.17:15:45.91#ibcon#enter sib2, iclass 14, count 0 2006.285.17:15:45.91#ibcon#flushed, iclass 14, count 0 2006.285.17:15:45.91#ibcon#about to write, iclass 14, count 0 2006.285.17:15:45.91#ibcon#wrote, iclass 14, count 0 2006.285.17:15:45.91#ibcon#about to read 3, iclass 14, count 0 2006.285.17:15:45.94#ibcon#read 3, iclass 14, count 0 2006.285.17:15:45.94#ibcon#about to read 4, iclass 14, count 0 2006.285.17:15:45.94#ibcon#read 4, iclass 14, count 0 2006.285.17:15:45.94#ibcon#about to read 5, iclass 14, count 0 2006.285.17:15:45.94#ibcon#read 5, iclass 14, count 0 2006.285.17:15:45.94#ibcon#about to read 6, iclass 14, count 0 2006.285.17:15:45.94#ibcon#read 6, iclass 14, count 0 2006.285.17:15:45.94#ibcon#end of sib2, iclass 14, count 0 2006.285.17:15:45.94#ibcon#*after write, iclass 14, count 0 2006.285.17:15:45.94#ibcon#*before return 0, iclass 14, count 0 2006.285.17:15:45.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:15:45.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:15:45.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.17:15:45.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.17:15:45.94$vck44/vblo=1,629.99 2006.285.17:15:45.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.17:15:45.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.17:15:45.94#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:45.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:15:45.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:15:45.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:15:45.94#ibcon#enter wrdev, iclass 16, count 0 2006.285.17:15:45.94#ibcon#first serial, iclass 16, count 0 2006.285.17:15:45.94#ibcon#enter sib2, iclass 16, count 0 2006.285.17:15:45.94#ibcon#flushed, iclass 16, count 0 2006.285.17:15:45.94#ibcon#about to write, iclass 16, count 0 2006.285.17:15:45.94#ibcon#wrote, iclass 16, count 0 2006.285.17:15:45.94#ibcon#about to read 3, iclass 16, count 0 2006.285.17:15:45.96#ibcon#read 3, iclass 16, count 0 2006.285.17:15:45.96#ibcon#about to read 4, iclass 16, count 0 2006.285.17:15:45.96#ibcon#read 4, iclass 16, count 0 2006.285.17:15:45.96#ibcon#about to read 5, iclass 16, count 0 2006.285.17:15:45.96#ibcon#read 5, iclass 16, count 0 2006.285.17:15:45.96#ibcon#about to read 6, iclass 16, count 0 2006.285.17:15:45.96#ibcon#read 6, iclass 16, count 0 2006.285.17:15:45.96#ibcon#end of sib2, iclass 16, count 0 2006.285.17:15:45.96#ibcon#*mode == 0, iclass 16, count 0 2006.285.17:15:45.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.17:15:45.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.17:15:45.96#ibcon#*before write, iclass 16, count 0 2006.285.17:15:45.96#ibcon#enter sib2, iclass 16, count 0 2006.285.17:15:45.96#ibcon#flushed, iclass 16, count 0 2006.285.17:15:45.96#ibcon#about to write, iclass 16, count 0 2006.285.17:15:45.96#ibcon#wrote, iclass 16, count 0 2006.285.17:15:45.96#ibcon#about to read 3, iclass 16, count 0 2006.285.17:15:46.00#ibcon#read 3, iclass 16, count 0 2006.285.17:15:46.00#ibcon#about to read 4, iclass 16, count 0 2006.285.17:15:46.00#ibcon#read 4, iclass 16, count 0 2006.285.17:15:46.00#ibcon#about to read 5, iclass 16, count 0 2006.285.17:15:46.00#ibcon#read 5, iclass 16, count 0 2006.285.17:15:46.00#ibcon#about to read 6, iclass 16, count 0 2006.285.17:15:46.00#ibcon#read 6, iclass 16, count 0 2006.285.17:15:46.00#ibcon#end of sib2, iclass 16, count 0 2006.285.17:15:46.00#ibcon#*after write, iclass 16, count 0 2006.285.17:15:46.00#ibcon#*before return 0, iclass 16, count 0 2006.285.17:15:46.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:15:46.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:15:46.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.17:15:46.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.17:15:46.00$vck44/vb=1,4 2006.285.17:15:46.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.17:15:46.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.17:15:46.00#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:46.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:15:46.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:15:46.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:15:46.00#ibcon#enter wrdev, iclass 18, count 2 2006.285.17:15:46.00#ibcon#first serial, iclass 18, count 2 2006.285.17:15:46.00#ibcon#enter sib2, iclass 18, count 2 2006.285.17:15:46.00#ibcon#flushed, iclass 18, count 2 2006.285.17:15:46.00#ibcon#about to write, iclass 18, count 2 2006.285.17:15:46.00#ibcon#wrote, iclass 18, count 2 2006.285.17:15:46.00#ibcon#about to read 3, iclass 18, count 2 2006.285.17:15:46.02#ibcon#read 3, iclass 18, count 2 2006.285.17:15:46.02#ibcon#about to read 4, iclass 18, count 2 2006.285.17:15:46.02#ibcon#read 4, iclass 18, count 2 2006.285.17:15:46.02#ibcon#about to read 5, iclass 18, count 2 2006.285.17:15:46.02#ibcon#read 5, iclass 18, count 2 2006.285.17:15:46.02#ibcon#about to read 6, iclass 18, count 2 2006.285.17:15:46.02#ibcon#read 6, iclass 18, count 2 2006.285.17:15:46.02#ibcon#end of sib2, iclass 18, count 2 2006.285.17:15:46.02#ibcon#*mode == 0, iclass 18, count 2 2006.285.17:15:46.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.17:15:46.02#ibcon#[27=AT01-04\r\n] 2006.285.17:15:46.02#ibcon#*before write, iclass 18, count 2 2006.285.17:15:46.02#ibcon#enter sib2, iclass 18, count 2 2006.285.17:15:46.02#ibcon#flushed, iclass 18, count 2 2006.285.17:15:46.02#ibcon#about to write, iclass 18, count 2 2006.285.17:15:46.02#ibcon#wrote, iclass 18, count 2 2006.285.17:15:46.02#ibcon#about to read 3, iclass 18, count 2 2006.285.17:15:46.05#ibcon#read 3, iclass 18, count 2 2006.285.17:15:46.05#ibcon#about to read 4, iclass 18, count 2 2006.285.17:15:46.05#ibcon#read 4, iclass 18, count 2 2006.285.17:15:46.05#ibcon#about to read 5, iclass 18, count 2 2006.285.17:15:46.05#ibcon#read 5, iclass 18, count 2 2006.285.17:15:46.05#ibcon#about to read 6, iclass 18, count 2 2006.285.17:15:46.05#ibcon#read 6, iclass 18, count 2 2006.285.17:15:46.05#ibcon#end of sib2, iclass 18, count 2 2006.285.17:15:46.05#ibcon#*after write, iclass 18, count 2 2006.285.17:15:46.05#ibcon#*before return 0, iclass 18, count 2 2006.285.17:15:46.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:15:46.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:15:46.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.17:15:46.05#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:46.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:15:46.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:15:46.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:15:46.17#ibcon#enter wrdev, iclass 18, count 0 2006.285.17:15:46.17#ibcon#first serial, iclass 18, count 0 2006.285.17:15:46.17#ibcon#enter sib2, iclass 18, count 0 2006.285.17:15:46.17#ibcon#flushed, iclass 18, count 0 2006.285.17:15:46.17#ibcon#about to write, iclass 18, count 0 2006.285.17:15:46.17#ibcon#wrote, iclass 18, count 0 2006.285.17:15:46.17#ibcon#about to read 3, iclass 18, count 0 2006.285.17:15:46.19#ibcon#read 3, iclass 18, count 0 2006.285.17:15:46.19#ibcon#about to read 4, iclass 18, count 0 2006.285.17:15:46.19#ibcon#read 4, iclass 18, count 0 2006.285.17:15:46.19#ibcon#about to read 5, iclass 18, count 0 2006.285.17:15:46.19#ibcon#read 5, iclass 18, count 0 2006.285.17:15:46.19#ibcon#about to read 6, iclass 18, count 0 2006.285.17:15:46.19#ibcon#read 6, iclass 18, count 0 2006.285.17:15:46.19#ibcon#end of sib2, iclass 18, count 0 2006.285.17:15:46.19#ibcon#*mode == 0, iclass 18, count 0 2006.285.17:15:46.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.17:15:46.19#ibcon#[27=USB\r\n] 2006.285.17:15:46.19#ibcon#*before write, iclass 18, count 0 2006.285.17:15:46.19#ibcon#enter sib2, iclass 18, count 0 2006.285.17:15:46.19#ibcon#flushed, iclass 18, count 0 2006.285.17:15:46.19#ibcon#about to write, iclass 18, count 0 2006.285.17:15:46.19#ibcon#wrote, iclass 18, count 0 2006.285.17:15:46.19#ibcon#about to read 3, iclass 18, count 0 2006.285.17:15:46.22#ibcon#read 3, iclass 18, count 0 2006.285.17:15:46.22#ibcon#about to read 4, iclass 18, count 0 2006.285.17:15:46.22#ibcon#read 4, iclass 18, count 0 2006.285.17:15:46.22#ibcon#about to read 5, iclass 18, count 0 2006.285.17:15:46.22#ibcon#read 5, iclass 18, count 0 2006.285.17:15:46.22#ibcon#about to read 6, iclass 18, count 0 2006.285.17:15:46.22#ibcon#read 6, iclass 18, count 0 2006.285.17:15:46.22#ibcon#end of sib2, iclass 18, count 0 2006.285.17:15:46.22#ibcon#*after write, iclass 18, count 0 2006.285.17:15:46.22#ibcon#*before return 0, iclass 18, count 0 2006.285.17:15:46.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:15:46.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:15:46.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.17:15:46.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.17:15:46.22$vck44/vblo=2,634.99 2006.285.17:15:46.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.17:15:46.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.17:15:46.22#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:46.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:15:46.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:15:46.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:15:46.22#ibcon#enter wrdev, iclass 20, count 0 2006.285.17:15:46.22#ibcon#first serial, iclass 20, count 0 2006.285.17:15:46.22#ibcon#enter sib2, iclass 20, count 0 2006.285.17:15:46.22#ibcon#flushed, iclass 20, count 0 2006.285.17:15:46.22#ibcon#about to write, iclass 20, count 0 2006.285.17:15:46.22#ibcon#wrote, iclass 20, count 0 2006.285.17:15:46.22#ibcon#about to read 3, iclass 20, count 0 2006.285.17:15:46.24#ibcon#read 3, iclass 20, count 0 2006.285.17:15:46.24#ibcon#about to read 4, iclass 20, count 0 2006.285.17:15:46.24#ibcon#read 4, iclass 20, count 0 2006.285.17:15:46.24#ibcon#about to read 5, iclass 20, count 0 2006.285.17:15:46.24#ibcon#read 5, iclass 20, count 0 2006.285.17:15:46.24#ibcon#about to read 6, iclass 20, count 0 2006.285.17:15:46.24#ibcon#read 6, iclass 20, count 0 2006.285.17:15:46.24#ibcon#end of sib2, iclass 20, count 0 2006.285.17:15:46.24#ibcon#*mode == 0, iclass 20, count 0 2006.285.17:15:46.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.17:15:46.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.17:15:46.24#ibcon#*before write, iclass 20, count 0 2006.285.17:15:46.24#ibcon#enter sib2, iclass 20, count 0 2006.285.17:15:46.24#ibcon#flushed, iclass 20, count 0 2006.285.17:15:46.24#ibcon#about to write, iclass 20, count 0 2006.285.17:15:46.24#ibcon#wrote, iclass 20, count 0 2006.285.17:15:46.24#ibcon#about to read 3, iclass 20, count 0 2006.285.17:15:46.28#ibcon#read 3, iclass 20, count 0 2006.285.17:15:46.28#ibcon#about to read 4, iclass 20, count 0 2006.285.17:15:46.28#ibcon#read 4, iclass 20, count 0 2006.285.17:15:46.28#ibcon#about to read 5, iclass 20, count 0 2006.285.17:15:46.28#ibcon#read 5, iclass 20, count 0 2006.285.17:15:46.28#ibcon#about to read 6, iclass 20, count 0 2006.285.17:15:46.28#ibcon#read 6, iclass 20, count 0 2006.285.17:15:46.28#ibcon#end of sib2, iclass 20, count 0 2006.285.17:15:46.28#ibcon#*after write, iclass 20, count 0 2006.285.17:15:46.28#ibcon#*before return 0, iclass 20, count 0 2006.285.17:15:46.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:15:46.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:15:46.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.17:15:46.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.17:15:46.28$vck44/vb=2,5 2006.285.17:15:46.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.17:15:46.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.17:15:46.28#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:46.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:15:46.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:15:46.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:15:46.34#ibcon#enter wrdev, iclass 22, count 2 2006.285.17:15:46.34#ibcon#first serial, iclass 22, count 2 2006.285.17:15:46.34#ibcon#enter sib2, iclass 22, count 2 2006.285.17:15:46.34#ibcon#flushed, iclass 22, count 2 2006.285.17:15:46.34#ibcon#about to write, iclass 22, count 2 2006.285.17:15:46.34#ibcon#wrote, iclass 22, count 2 2006.285.17:15:46.34#ibcon#about to read 3, iclass 22, count 2 2006.285.17:15:46.36#ibcon#read 3, iclass 22, count 2 2006.285.17:15:46.36#ibcon#about to read 4, iclass 22, count 2 2006.285.17:15:46.36#ibcon#read 4, iclass 22, count 2 2006.285.17:15:46.36#ibcon#about to read 5, iclass 22, count 2 2006.285.17:15:46.36#ibcon#read 5, iclass 22, count 2 2006.285.17:15:46.36#ibcon#about to read 6, iclass 22, count 2 2006.285.17:15:46.36#ibcon#read 6, iclass 22, count 2 2006.285.17:15:46.36#ibcon#end of sib2, iclass 22, count 2 2006.285.17:15:46.36#ibcon#*mode == 0, iclass 22, count 2 2006.285.17:15:46.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.17:15:46.36#ibcon#[27=AT02-05\r\n] 2006.285.17:15:46.36#ibcon#*before write, iclass 22, count 2 2006.285.17:15:46.36#ibcon#enter sib2, iclass 22, count 2 2006.285.17:15:46.36#ibcon#flushed, iclass 22, count 2 2006.285.17:15:46.36#ibcon#about to write, iclass 22, count 2 2006.285.17:15:46.36#ibcon#wrote, iclass 22, count 2 2006.285.17:15:46.36#ibcon#about to read 3, iclass 22, count 2 2006.285.17:15:46.39#ibcon#read 3, iclass 22, count 2 2006.285.17:15:46.39#ibcon#about to read 4, iclass 22, count 2 2006.285.17:15:46.39#ibcon#read 4, iclass 22, count 2 2006.285.17:15:46.39#ibcon#about to read 5, iclass 22, count 2 2006.285.17:15:46.39#ibcon#read 5, iclass 22, count 2 2006.285.17:15:46.39#ibcon#about to read 6, iclass 22, count 2 2006.285.17:15:46.39#ibcon#read 6, iclass 22, count 2 2006.285.17:15:46.39#ibcon#end of sib2, iclass 22, count 2 2006.285.17:15:46.39#ibcon#*after write, iclass 22, count 2 2006.285.17:15:46.39#ibcon#*before return 0, iclass 22, count 2 2006.285.17:15:46.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:15:46.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:15:46.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.17:15:46.39#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:46.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:15:46.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:15:46.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:15:46.51#ibcon#enter wrdev, iclass 22, count 0 2006.285.17:15:46.51#ibcon#first serial, iclass 22, count 0 2006.285.17:15:46.51#ibcon#enter sib2, iclass 22, count 0 2006.285.17:15:46.51#ibcon#flushed, iclass 22, count 0 2006.285.17:15:46.51#ibcon#about to write, iclass 22, count 0 2006.285.17:15:46.51#ibcon#wrote, iclass 22, count 0 2006.285.17:15:46.51#ibcon#about to read 3, iclass 22, count 0 2006.285.17:15:46.53#ibcon#read 3, iclass 22, count 0 2006.285.17:15:46.53#ibcon#about to read 4, iclass 22, count 0 2006.285.17:15:46.53#ibcon#read 4, iclass 22, count 0 2006.285.17:15:46.53#ibcon#about to read 5, iclass 22, count 0 2006.285.17:15:46.53#ibcon#read 5, iclass 22, count 0 2006.285.17:15:46.53#ibcon#about to read 6, iclass 22, count 0 2006.285.17:15:46.53#ibcon#read 6, iclass 22, count 0 2006.285.17:15:46.53#ibcon#end of sib2, iclass 22, count 0 2006.285.17:15:46.53#ibcon#*mode == 0, iclass 22, count 0 2006.285.17:15:46.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.17:15:46.53#ibcon#[27=USB\r\n] 2006.285.17:15:46.53#ibcon#*before write, iclass 22, count 0 2006.285.17:15:46.53#ibcon#enter sib2, iclass 22, count 0 2006.285.17:15:46.53#ibcon#flushed, iclass 22, count 0 2006.285.17:15:46.53#ibcon#about to write, iclass 22, count 0 2006.285.17:15:46.53#ibcon#wrote, iclass 22, count 0 2006.285.17:15:46.53#ibcon#about to read 3, iclass 22, count 0 2006.285.17:15:46.56#ibcon#read 3, iclass 22, count 0 2006.285.17:15:46.56#ibcon#about to read 4, iclass 22, count 0 2006.285.17:15:46.56#ibcon#read 4, iclass 22, count 0 2006.285.17:15:46.56#ibcon#about to read 5, iclass 22, count 0 2006.285.17:15:46.56#ibcon#read 5, iclass 22, count 0 2006.285.17:15:46.56#ibcon#about to read 6, iclass 22, count 0 2006.285.17:15:46.56#ibcon#read 6, iclass 22, count 0 2006.285.17:15:46.56#ibcon#end of sib2, iclass 22, count 0 2006.285.17:15:46.56#ibcon#*after write, iclass 22, count 0 2006.285.17:15:46.56#ibcon#*before return 0, iclass 22, count 0 2006.285.17:15:46.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:15:46.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:15:46.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.17:15:46.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.17:15:46.56$vck44/vblo=3,649.99 2006.285.17:15:46.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.17:15:46.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.17:15:46.56#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:46.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:15:46.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:15:46.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:15:46.56#ibcon#enter wrdev, iclass 24, count 0 2006.285.17:15:46.56#ibcon#first serial, iclass 24, count 0 2006.285.17:15:46.56#ibcon#enter sib2, iclass 24, count 0 2006.285.17:15:46.56#ibcon#flushed, iclass 24, count 0 2006.285.17:15:46.56#ibcon#about to write, iclass 24, count 0 2006.285.17:15:46.56#ibcon#wrote, iclass 24, count 0 2006.285.17:15:46.56#ibcon#about to read 3, iclass 24, count 0 2006.285.17:15:46.58#ibcon#read 3, iclass 24, count 0 2006.285.17:15:46.58#ibcon#about to read 4, iclass 24, count 0 2006.285.17:15:46.58#ibcon#read 4, iclass 24, count 0 2006.285.17:15:46.58#ibcon#about to read 5, iclass 24, count 0 2006.285.17:15:46.58#ibcon#read 5, iclass 24, count 0 2006.285.17:15:46.58#ibcon#about to read 6, iclass 24, count 0 2006.285.17:15:46.58#ibcon#read 6, iclass 24, count 0 2006.285.17:15:46.58#ibcon#end of sib2, iclass 24, count 0 2006.285.17:15:46.58#ibcon#*mode == 0, iclass 24, count 0 2006.285.17:15:46.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.17:15:46.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.17:15:46.58#ibcon#*before write, iclass 24, count 0 2006.285.17:15:46.58#ibcon#enter sib2, iclass 24, count 0 2006.285.17:15:46.58#ibcon#flushed, iclass 24, count 0 2006.285.17:15:46.58#ibcon#about to write, iclass 24, count 0 2006.285.17:15:46.58#ibcon#wrote, iclass 24, count 0 2006.285.17:15:46.58#ibcon#about to read 3, iclass 24, count 0 2006.285.17:15:46.62#ibcon#read 3, iclass 24, count 0 2006.285.17:15:46.62#ibcon#about to read 4, iclass 24, count 0 2006.285.17:15:46.62#ibcon#read 4, iclass 24, count 0 2006.285.17:15:46.62#ibcon#about to read 5, iclass 24, count 0 2006.285.17:15:46.62#ibcon#read 5, iclass 24, count 0 2006.285.17:15:46.62#ibcon#about to read 6, iclass 24, count 0 2006.285.17:15:46.62#ibcon#read 6, iclass 24, count 0 2006.285.17:15:46.62#ibcon#end of sib2, iclass 24, count 0 2006.285.17:15:46.62#ibcon#*after write, iclass 24, count 0 2006.285.17:15:46.62#ibcon#*before return 0, iclass 24, count 0 2006.285.17:15:46.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:15:46.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:15:46.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.17:15:46.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.17:15:46.62$vck44/vb=3,4 2006.285.17:15:46.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.17:15:46.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.17:15:46.62#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:46.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:15:46.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:15:46.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:15:46.68#ibcon#enter wrdev, iclass 26, count 2 2006.285.17:15:46.68#ibcon#first serial, iclass 26, count 2 2006.285.17:15:46.68#ibcon#enter sib2, iclass 26, count 2 2006.285.17:15:46.68#ibcon#flushed, iclass 26, count 2 2006.285.17:15:46.68#ibcon#about to write, iclass 26, count 2 2006.285.17:15:46.68#ibcon#wrote, iclass 26, count 2 2006.285.17:15:46.68#ibcon#about to read 3, iclass 26, count 2 2006.285.17:15:46.70#ibcon#read 3, iclass 26, count 2 2006.285.17:15:46.70#ibcon#about to read 4, iclass 26, count 2 2006.285.17:15:46.70#ibcon#read 4, iclass 26, count 2 2006.285.17:15:46.70#ibcon#about to read 5, iclass 26, count 2 2006.285.17:15:46.70#ibcon#read 5, iclass 26, count 2 2006.285.17:15:46.70#ibcon#about to read 6, iclass 26, count 2 2006.285.17:15:46.70#ibcon#read 6, iclass 26, count 2 2006.285.17:15:46.70#ibcon#end of sib2, iclass 26, count 2 2006.285.17:15:46.70#ibcon#*mode == 0, iclass 26, count 2 2006.285.17:15:46.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.17:15:46.70#ibcon#[27=AT03-04\r\n] 2006.285.17:15:46.70#ibcon#*before write, iclass 26, count 2 2006.285.17:15:46.70#ibcon#enter sib2, iclass 26, count 2 2006.285.17:15:46.70#ibcon#flushed, iclass 26, count 2 2006.285.17:15:46.70#ibcon#about to write, iclass 26, count 2 2006.285.17:15:46.70#ibcon#wrote, iclass 26, count 2 2006.285.17:15:46.70#ibcon#about to read 3, iclass 26, count 2 2006.285.17:15:46.73#ibcon#read 3, iclass 26, count 2 2006.285.17:15:46.73#ibcon#about to read 4, iclass 26, count 2 2006.285.17:15:46.73#ibcon#read 4, iclass 26, count 2 2006.285.17:15:46.73#ibcon#about to read 5, iclass 26, count 2 2006.285.17:15:46.73#ibcon#read 5, iclass 26, count 2 2006.285.17:15:46.73#ibcon#about to read 6, iclass 26, count 2 2006.285.17:15:46.73#ibcon#read 6, iclass 26, count 2 2006.285.17:15:46.73#ibcon#end of sib2, iclass 26, count 2 2006.285.17:15:46.73#ibcon#*after write, iclass 26, count 2 2006.285.17:15:46.73#ibcon#*before return 0, iclass 26, count 2 2006.285.17:15:46.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:15:46.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:15:46.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.17:15:46.73#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:46.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:15:46.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:15:46.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:15:46.85#ibcon#enter wrdev, iclass 26, count 0 2006.285.17:15:46.85#ibcon#first serial, iclass 26, count 0 2006.285.17:15:46.85#ibcon#enter sib2, iclass 26, count 0 2006.285.17:15:46.85#ibcon#flushed, iclass 26, count 0 2006.285.17:15:46.85#ibcon#about to write, iclass 26, count 0 2006.285.17:15:46.85#ibcon#wrote, iclass 26, count 0 2006.285.17:15:46.85#ibcon#about to read 3, iclass 26, count 0 2006.285.17:15:46.87#ibcon#read 3, iclass 26, count 0 2006.285.17:15:46.87#ibcon#about to read 4, iclass 26, count 0 2006.285.17:15:46.87#ibcon#read 4, iclass 26, count 0 2006.285.17:15:46.87#ibcon#about to read 5, iclass 26, count 0 2006.285.17:15:46.87#ibcon#read 5, iclass 26, count 0 2006.285.17:15:46.87#ibcon#about to read 6, iclass 26, count 0 2006.285.17:15:46.87#ibcon#read 6, iclass 26, count 0 2006.285.17:15:46.87#ibcon#end of sib2, iclass 26, count 0 2006.285.17:15:46.87#ibcon#*mode == 0, iclass 26, count 0 2006.285.17:15:46.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.17:15:46.87#ibcon#[27=USB\r\n] 2006.285.17:15:46.87#ibcon#*before write, iclass 26, count 0 2006.285.17:15:46.87#ibcon#enter sib2, iclass 26, count 0 2006.285.17:15:46.87#ibcon#flushed, iclass 26, count 0 2006.285.17:15:46.87#ibcon#about to write, iclass 26, count 0 2006.285.17:15:46.87#ibcon#wrote, iclass 26, count 0 2006.285.17:15:46.87#ibcon#about to read 3, iclass 26, count 0 2006.285.17:15:46.90#ibcon#read 3, iclass 26, count 0 2006.285.17:15:46.90#ibcon#about to read 4, iclass 26, count 0 2006.285.17:15:46.90#ibcon#read 4, iclass 26, count 0 2006.285.17:15:46.90#ibcon#about to read 5, iclass 26, count 0 2006.285.17:15:46.90#ibcon#read 5, iclass 26, count 0 2006.285.17:15:46.90#ibcon#about to read 6, iclass 26, count 0 2006.285.17:15:46.90#ibcon#read 6, iclass 26, count 0 2006.285.17:15:46.90#ibcon#end of sib2, iclass 26, count 0 2006.285.17:15:46.90#ibcon#*after write, iclass 26, count 0 2006.285.17:15:46.90#ibcon#*before return 0, iclass 26, count 0 2006.285.17:15:46.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:15:46.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:15:46.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.17:15:46.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.17:15:46.90$vck44/vblo=4,679.99 2006.285.17:15:46.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.17:15:46.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.17:15:46.90#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:46.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:15:46.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:15:46.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:15:46.90#ibcon#enter wrdev, iclass 28, count 0 2006.285.17:15:46.90#ibcon#first serial, iclass 28, count 0 2006.285.17:15:46.90#ibcon#enter sib2, iclass 28, count 0 2006.285.17:15:46.90#ibcon#flushed, iclass 28, count 0 2006.285.17:15:46.90#ibcon#about to write, iclass 28, count 0 2006.285.17:15:46.90#ibcon#wrote, iclass 28, count 0 2006.285.17:15:46.90#ibcon#about to read 3, iclass 28, count 0 2006.285.17:15:46.92#ibcon#read 3, iclass 28, count 0 2006.285.17:15:46.92#ibcon#about to read 4, iclass 28, count 0 2006.285.17:15:46.92#ibcon#read 4, iclass 28, count 0 2006.285.17:15:46.92#ibcon#about to read 5, iclass 28, count 0 2006.285.17:15:46.92#ibcon#read 5, iclass 28, count 0 2006.285.17:15:46.92#ibcon#about to read 6, iclass 28, count 0 2006.285.17:15:46.92#ibcon#read 6, iclass 28, count 0 2006.285.17:15:46.92#ibcon#end of sib2, iclass 28, count 0 2006.285.17:15:46.92#ibcon#*mode == 0, iclass 28, count 0 2006.285.17:15:46.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.17:15:46.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.17:15:46.92#ibcon#*before write, iclass 28, count 0 2006.285.17:15:46.92#ibcon#enter sib2, iclass 28, count 0 2006.285.17:15:46.92#ibcon#flushed, iclass 28, count 0 2006.285.17:15:46.92#ibcon#about to write, iclass 28, count 0 2006.285.17:15:46.92#ibcon#wrote, iclass 28, count 0 2006.285.17:15:46.92#ibcon#about to read 3, iclass 28, count 0 2006.285.17:15:46.96#ibcon#read 3, iclass 28, count 0 2006.285.17:15:46.96#ibcon#about to read 4, iclass 28, count 0 2006.285.17:15:46.96#ibcon#read 4, iclass 28, count 0 2006.285.17:15:46.96#ibcon#about to read 5, iclass 28, count 0 2006.285.17:15:46.96#ibcon#read 5, iclass 28, count 0 2006.285.17:15:46.96#ibcon#about to read 6, iclass 28, count 0 2006.285.17:15:46.96#ibcon#read 6, iclass 28, count 0 2006.285.17:15:46.96#ibcon#end of sib2, iclass 28, count 0 2006.285.17:15:46.96#ibcon#*after write, iclass 28, count 0 2006.285.17:15:46.96#ibcon#*before return 0, iclass 28, count 0 2006.285.17:15:46.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:15:46.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:15:46.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.17:15:46.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.17:15:46.96$vck44/vb=4,5 2006.285.17:15:46.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.17:15:46.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.17:15:46.96#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:46.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:15:47.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:15:47.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:15:47.02#ibcon#enter wrdev, iclass 30, count 2 2006.285.17:15:47.02#ibcon#first serial, iclass 30, count 2 2006.285.17:15:47.02#ibcon#enter sib2, iclass 30, count 2 2006.285.17:15:47.02#ibcon#flushed, iclass 30, count 2 2006.285.17:15:47.02#ibcon#about to write, iclass 30, count 2 2006.285.17:15:47.02#ibcon#wrote, iclass 30, count 2 2006.285.17:15:47.02#ibcon#about to read 3, iclass 30, count 2 2006.285.17:15:47.04#ibcon#read 3, iclass 30, count 2 2006.285.17:15:47.04#ibcon#about to read 4, iclass 30, count 2 2006.285.17:15:47.04#ibcon#read 4, iclass 30, count 2 2006.285.17:15:47.04#ibcon#about to read 5, iclass 30, count 2 2006.285.17:15:47.04#ibcon#read 5, iclass 30, count 2 2006.285.17:15:47.04#ibcon#about to read 6, iclass 30, count 2 2006.285.17:15:47.04#ibcon#read 6, iclass 30, count 2 2006.285.17:15:47.04#ibcon#end of sib2, iclass 30, count 2 2006.285.17:15:47.04#ibcon#*mode == 0, iclass 30, count 2 2006.285.17:15:47.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.17:15:47.04#ibcon#[27=AT04-05\r\n] 2006.285.17:15:47.04#ibcon#*before write, iclass 30, count 2 2006.285.17:15:47.04#ibcon#enter sib2, iclass 30, count 2 2006.285.17:15:47.04#ibcon#flushed, iclass 30, count 2 2006.285.17:15:47.04#ibcon#about to write, iclass 30, count 2 2006.285.17:15:47.04#ibcon#wrote, iclass 30, count 2 2006.285.17:15:47.04#ibcon#about to read 3, iclass 30, count 2 2006.285.17:15:47.07#ibcon#read 3, iclass 30, count 2 2006.285.17:15:47.07#ibcon#about to read 4, iclass 30, count 2 2006.285.17:15:47.07#ibcon#read 4, iclass 30, count 2 2006.285.17:15:47.07#ibcon#about to read 5, iclass 30, count 2 2006.285.17:15:47.07#ibcon#read 5, iclass 30, count 2 2006.285.17:15:47.07#ibcon#about to read 6, iclass 30, count 2 2006.285.17:15:47.07#ibcon#read 6, iclass 30, count 2 2006.285.17:15:47.07#ibcon#end of sib2, iclass 30, count 2 2006.285.17:15:47.07#ibcon#*after write, iclass 30, count 2 2006.285.17:15:47.07#ibcon#*before return 0, iclass 30, count 2 2006.285.17:15:47.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:15:47.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:15:47.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.17:15:47.07#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:47.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:15:47.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:15:47.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:15:47.19#ibcon#enter wrdev, iclass 30, count 0 2006.285.17:15:47.19#ibcon#first serial, iclass 30, count 0 2006.285.17:15:47.19#ibcon#enter sib2, iclass 30, count 0 2006.285.17:15:47.19#ibcon#flushed, iclass 30, count 0 2006.285.17:15:47.19#ibcon#about to write, iclass 30, count 0 2006.285.17:15:47.19#ibcon#wrote, iclass 30, count 0 2006.285.17:15:47.19#ibcon#about to read 3, iclass 30, count 0 2006.285.17:15:47.21#ibcon#read 3, iclass 30, count 0 2006.285.17:15:47.21#ibcon#about to read 4, iclass 30, count 0 2006.285.17:15:47.21#ibcon#read 4, iclass 30, count 0 2006.285.17:15:47.21#ibcon#about to read 5, iclass 30, count 0 2006.285.17:15:47.21#ibcon#read 5, iclass 30, count 0 2006.285.17:15:47.21#ibcon#about to read 6, iclass 30, count 0 2006.285.17:15:47.21#ibcon#read 6, iclass 30, count 0 2006.285.17:15:47.21#ibcon#end of sib2, iclass 30, count 0 2006.285.17:15:47.21#ibcon#*mode == 0, iclass 30, count 0 2006.285.17:15:47.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.17:15:47.21#ibcon#[27=USB\r\n] 2006.285.17:15:47.21#ibcon#*before write, iclass 30, count 0 2006.285.17:15:47.21#ibcon#enter sib2, iclass 30, count 0 2006.285.17:15:47.21#ibcon#flushed, iclass 30, count 0 2006.285.17:15:47.21#ibcon#about to write, iclass 30, count 0 2006.285.17:15:47.21#ibcon#wrote, iclass 30, count 0 2006.285.17:15:47.21#ibcon#about to read 3, iclass 30, count 0 2006.285.17:15:47.24#ibcon#read 3, iclass 30, count 0 2006.285.17:15:47.24#ibcon#about to read 4, iclass 30, count 0 2006.285.17:15:47.24#ibcon#read 4, iclass 30, count 0 2006.285.17:15:47.24#ibcon#about to read 5, iclass 30, count 0 2006.285.17:15:47.24#ibcon#read 5, iclass 30, count 0 2006.285.17:15:47.24#ibcon#about to read 6, iclass 30, count 0 2006.285.17:15:47.24#ibcon#read 6, iclass 30, count 0 2006.285.17:15:47.24#ibcon#end of sib2, iclass 30, count 0 2006.285.17:15:47.24#ibcon#*after write, iclass 30, count 0 2006.285.17:15:47.24#ibcon#*before return 0, iclass 30, count 0 2006.285.17:15:47.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:15:47.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:15:47.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.17:15:47.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.17:15:47.24$vck44/vblo=5,709.99 2006.285.17:15:47.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.17:15:47.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.17:15:47.24#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:47.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:15:47.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:15:47.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:15:47.24#ibcon#enter wrdev, iclass 32, count 0 2006.285.17:15:47.24#ibcon#first serial, iclass 32, count 0 2006.285.17:15:47.24#ibcon#enter sib2, iclass 32, count 0 2006.285.17:15:47.24#ibcon#flushed, iclass 32, count 0 2006.285.17:15:47.24#ibcon#about to write, iclass 32, count 0 2006.285.17:15:47.24#ibcon#wrote, iclass 32, count 0 2006.285.17:15:47.24#ibcon#about to read 3, iclass 32, count 0 2006.285.17:15:47.26#ibcon#read 3, iclass 32, count 0 2006.285.17:15:47.26#ibcon#about to read 4, iclass 32, count 0 2006.285.17:15:47.26#ibcon#read 4, iclass 32, count 0 2006.285.17:15:47.26#ibcon#about to read 5, iclass 32, count 0 2006.285.17:15:47.26#ibcon#read 5, iclass 32, count 0 2006.285.17:15:47.26#ibcon#about to read 6, iclass 32, count 0 2006.285.17:15:47.26#ibcon#read 6, iclass 32, count 0 2006.285.17:15:47.26#ibcon#end of sib2, iclass 32, count 0 2006.285.17:15:47.26#ibcon#*mode == 0, iclass 32, count 0 2006.285.17:15:47.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.17:15:47.26#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.17:15:47.26#ibcon#*before write, iclass 32, count 0 2006.285.17:15:47.26#ibcon#enter sib2, iclass 32, count 0 2006.285.17:15:47.26#ibcon#flushed, iclass 32, count 0 2006.285.17:15:47.26#ibcon#about to write, iclass 32, count 0 2006.285.17:15:47.26#ibcon#wrote, iclass 32, count 0 2006.285.17:15:47.26#ibcon#about to read 3, iclass 32, count 0 2006.285.17:15:47.30#ibcon#read 3, iclass 32, count 0 2006.285.17:15:47.30#ibcon#about to read 4, iclass 32, count 0 2006.285.17:15:47.30#ibcon#read 4, iclass 32, count 0 2006.285.17:15:47.30#ibcon#about to read 5, iclass 32, count 0 2006.285.17:15:47.30#ibcon#read 5, iclass 32, count 0 2006.285.17:15:47.30#ibcon#about to read 6, iclass 32, count 0 2006.285.17:15:47.30#ibcon#read 6, iclass 32, count 0 2006.285.17:15:47.30#ibcon#end of sib2, iclass 32, count 0 2006.285.17:15:47.30#ibcon#*after write, iclass 32, count 0 2006.285.17:15:47.30#ibcon#*before return 0, iclass 32, count 0 2006.285.17:15:47.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:15:47.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:15:47.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.17:15:47.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.17:15:47.30$vck44/vb=5,4 2006.285.17:15:47.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.17:15:47.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.17:15:47.30#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:47.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:15:47.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:15:47.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:15:47.36#ibcon#enter wrdev, iclass 34, count 2 2006.285.17:15:47.36#ibcon#first serial, iclass 34, count 2 2006.285.17:15:47.36#ibcon#enter sib2, iclass 34, count 2 2006.285.17:15:47.36#ibcon#flushed, iclass 34, count 2 2006.285.17:15:47.36#ibcon#about to write, iclass 34, count 2 2006.285.17:15:47.36#ibcon#wrote, iclass 34, count 2 2006.285.17:15:47.36#ibcon#about to read 3, iclass 34, count 2 2006.285.17:15:47.38#ibcon#read 3, iclass 34, count 2 2006.285.17:15:47.38#ibcon#about to read 4, iclass 34, count 2 2006.285.17:15:47.38#ibcon#read 4, iclass 34, count 2 2006.285.17:15:47.38#ibcon#about to read 5, iclass 34, count 2 2006.285.17:15:47.38#ibcon#read 5, iclass 34, count 2 2006.285.17:15:47.38#ibcon#about to read 6, iclass 34, count 2 2006.285.17:15:47.38#ibcon#read 6, iclass 34, count 2 2006.285.17:15:47.38#ibcon#end of sib2, iclass 34, count 2 2006.285.17:15:47.38#ibcon#*mode == 0, iclass 34, count 2 2006.285.17:15:47.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.17:15:47.38#ibcon#[27=AT05-04\r\n] 2006.285.17:15:47.38#ibcon#*before write, iclass 34, count 2 2006.285.17:15:47.38#ibcon#enter sib2, iclass 34, count 2 2006.285.17:15:47.38#ibcon#flushed, iclass 34, count 2 2006.285.17:15:47.38#ibcon#about to write, iclass 34, count 2 2006.285.17:15:47.38#ibcon#wrote, iclass 34, count 2 2006.285.17:15:47.38#ibcon#about to read 3, iclass 34, count 2 2006.285.17:15:47.41#ibcon#read 3, iclass 34, count 2 2006.285.17:15:47.41#ibcon#about to read 4, iclass 34, count 2 2006.285.17:15:47.41#ibcon#read 4, iclass 34, count 2 2006.285.17:15:47.41#ibcon#about to read 5, iclass 34, count 2 2006.285.17:15:47.41#ibcon#read 5, iclass 34, count 2 2006.285.17:15:47.41#ibcon#about to read 6, iclass 34, count 2 2006.285.17:15:47.41#ibcon#read 6, iclass 34, count 2 2006.285.17:15:47.41#ibcon#end of sib2, iclass 34, count 2 2006.285.17:15:47.41#ibcon#*after write, iclass 34, count 2 2006.285.17:15:47.41#ibcon#*before return 0, iclass 34, count 2 2006.285.17:15:47.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:15:47.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:15:47.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.17:15:47.41#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:47.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:15:47.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:15:47.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:15:47.53#ibcon#enter wrdev, iclass 34, count 0 2006.285.17:15:47.53#ibcon#first serial, iclass 34, count 0 2006.285.17:15:47.53#ibcon#enter sib2, iclass 34, count 0 2006.285.17:15:47.53#ibcon#flushed, iclass 34, count 0 2006.285.17:15:47.53#ibcon#about to write, iclass 34, count 0 2006.285.17:15:47.53#ibcon#wrote, iclass 34, count 0 2006.285.17:15:47.53#ibcon#about to read 3, iclass 34, count 0 2006.285.17:15:47.55#ibcon#read 3, iclass 34, count 0 2006.285.17:15:47.55#ibcon#about to read 4, iclass 34, count 0 2006.285.17:15:47.55#ibcon#read 4, iclass 34, count 0 2006.285.17:15:47.55#ibcon#about to read 5, iclass 34, count 0 2006.285.17:15:47.55#ibcon#read 5, iclass 34, count 0 2006.285.17:15:47.55#ibcon#about to read 6, iclass 34, count 0 2006.285.17:15:47.55#ibcon#read 6, iclass 34, count 0 2006.285.17:15:47.55#ibcon#end of sib2, iclass 34, count 0 2006.285.17:15:47.55#ibcon#*mode == 0, iclass 34, count 0 2006.285.17:15:47.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.17:15:47.55#ibcon#[27=USB\r\n] 2006.285.17:15:47.55#ibcon#*before write, iclass 34, count 0 2006.285.17:15:47.55#ibcon#enter sib2, iclass 34, count 0 2006.285.17:15:47.55#ibcon#flushed, iclass 34, count 0 2006.285.17:15:47.55#ibcon#about to write, iclass 34, count 0 2006.285.17:15:47.55#ibcon#wrote, iclass 34, count 0 2006.285.17:15:47.55#ibcon#about to read 3, iclass 34, count 0 2006.285.17:15:47.58#ibcon#read 3, iclass 34, count 0 2006.285.17:15:47.58#ibcon#about to read 4, iclass 34, count 0 2006.285.17:15:47.58#ibcon#read 4, iclass 34, count 0 2006.285.17:15:47.58#ibcon#about to read 5, iclass 34, count 0 2006.285.17:15:47.58#ibcon#read 5, iclass 34, count 0 2006.285.17:15:47.58#ibcon#about to read 6, iclass 34, count 0 2006.285.17:15:47.58#ibcon#read 6, iclass 34, count 0 2006.285.17:15:47.58#ibcon#end of sib2, iclass 34, count 0 2006.285.17:15:47.58#ibcon#*after write, iclass 34, count 0 2006.285.17:15:47.58#ibcon#*before return 0, iclass 34, count 0 2006.285.17:15:47.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:15:47.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:15:47.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.17:15:47.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.17:15:47.58$vck44/vblo=6,719.99 2006.285.17:15:47.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.17:15:47.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.17:15:47.58#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:47.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:15:47.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:15:47.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:15:47.58#ibcon#enter wrdev, iclass 36, count 0 2006.285.17:15:47.58#ibcon#first serial, iclass 36, count 0 2006.285.17:15:47.58#ibcon#enter sib2, iclass 36, count 0 2006.285.17:15:47.58#ibcon#flushed, iclass 36, count 0 2006.285.17:15:47.58#ibcon#about to write, iclass 36, count 0 2006.285.17:15:47.58#ibcon#wrote, iclass 36, count 0 2006.285.17:15:47.58#ibcon#about to read 3, iclass 36, count 0 2006.285.17:15:47.60#ibcon#read 3, iclass 36, count 0 2006.285.17:15:47.60#ibcon#about to read 4, iclass 36, count 0 2006.285.17:15:47.60#ibcon#read 4, iclass 36, count 0 2006.285.17:15:47.60#ibcon#about to read 5, iclass 36, count 0 2006.285.17:15:47.60#ibcon#read 5, iclass 36, count 0 2006.285.17:15:47.60#ibcon#about to read 6, iclass 36, count 0 2006.285.17:15:47.60#ibcon#read 6, iclass 36, count 0 2006.285.17:15:47.60#ibcon#end of sib2, iclass 36, count 0 2006.285.17:15:47.60#ibcon#*mode == 0, iclass 36, count 0 2006.285.17:15:47.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.17:15:47.60#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.17:15:47.60#ibcon#*before write, iclass 36, count 0 2006.285.17:15:47.60#ibcon#enter sib2, iclass 36, count 0 2006.285.17:15:47.60#ibcon#flushed, iclass 36, count 0 2006.285.17:15:47.60#ibcon#about to write, iclass 36, count 0 2006.285.17:15:47.60#ibcon#wrote, iclass 36, count 0 2006.285.17:15:47.60#ibcon#about to read 3, iclass 36, count 0 2006.285.17:15:47.64#ibcon#read 3, iclass 36, count 0 2006.285.17:15:47.64#ibcon#about to read 4, iclass 36, count 0 2006.285.17:15:47.64#ibcon#read 4, iclass 36, count 0 2006.285.17:15:47.64#ibcon#about to read 5, iclass 36, count 0 2006.285.17:15:47.64#ibcon#read 5, iclass 36, count 0 2006.285.17:15:47.64#ibcon#about to read 6, iclass 36, count 0 2006.285.17:15:47.64#ibcon#read 6, iclass 36, count 0 2006.285.17:15:47.64#ibcon#end of sib2, iclass 36, count 0 2006.285.17:15:47.64#ibcon#*after write, iclass 36, count 0 2006.285.17:15:47.64#ibcon#*before return 0, iclass 36, count 0 2006.285.17:15:47.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:15:47.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:15:47.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.17:15:47.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.17:15:47.64$vck44/vb=6,3 2006.285.17:15:47.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.17:15:47.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.17:15:47.64#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:47.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:15:47.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:15:47.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:15:47.70#ibcon#enter wrdev, iclass 38, count 2 2006.285.17:15:47.70#ibcon#first serial, iclass 38, count 2 2006.285.17:15:47.70#ibcon#enter sib2, iclass 38, count 2 2006.285.17:15:47.70#ibcon#flushed, iclass 38, count 2 2006.285.17:15:47.70#ibcon#about to write, iclass 38, count 2 2006.285.17:15:47.70#ibcon#wrote, iclass 38, count 2 2006.285.17:15:47.70#ibcon#about to read 3, iclass 38, count 2 2006.285.17:15:47.72#ibcon#read 3, iclass 38, count 2 2006.285.17:15:47.72#ibcon#about to read 4, iclass 38, count 2 2006.285.17:15:47.72#ibcon#read 4, iclass 38, count 2 2006.285.17:15:47.72#ibcon#about to read 5, iclass 38, count 2 2006.285.17:15:47.72#ibcon#read 5, iclass 38, count 2 2006.285.17:15:47.72#ibcon#about to read 6, iclass 38, count 2 2006.285.17:15:47.72#ibcon#read 6, iclass 38, count 2 2006.285.17:15:47.72#ibcon#end of sib2, iclass 38, count 2 2006.285.17:15:47.72#ibcon#*mode == 0, iclass 38, count 2 2006.285.17:15:47.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.17:15:47.72#ibcon#[27=AT06-03\r\n] 2006.285.17:15:47.72#ibcon#*before write, iclass 38, count 2 2006.285.17:15:47.72#ibcon#enter sib2, iclass 38, count 2 2006.285.17:15:47.72#ibcon#flushed, iclass 38, count 2 2006.285.17:15:47.72#ibcon#about to write, iclass 38, count 2 2006.285.17:15:47.72#ibcon#wrote, iclass 38, count 2 2006.285.17:15:47.72#ibcon#about to read 3, iclass 38, count 2 2006.285.17:15:47.75#ibcon#read 3, iclass 38, count 2 2006.285.17:15:47.75#ibcon#about to read 4, iclass 38, count 2 2006.285.17:15:47.75#ibcon#read 4, iclass 38, count 2 2006.285.17:15:47.75#ibcon#about to read 5, iclass 38, count 2 2006.285.17:15:47.75#ibcon#read 5, iclass 38, count 2 2006.285.17:15:47.75#ibcon#about to read 6, iclass 38, count 2 2006.285.17:15:47.75#ibcon#read 6, iclass 38, count 2 2006.285.17:15:47.75#ibcon#end of sib2, iclass 38, count 2 2006.285.17:15:47.75#ibcon#*after write, iclass 38, count 2 2006.285.17:15:47.75#ibcon#*before return 0, iclass 38, count 2 2006.285.17:15:47.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:15:47.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:15:47.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.17:15:47.75#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:47.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:15:47.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:15:47.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:15:47.87#ibcon#enter wrdev, iclass 38, count 0 2006.285.17:15:47.87#ibcon#first serial, iclass 38, count 0 2006.285.17:15:47.87#ibcon#enter sib2, iclass 38, count 0 2006.285.17:15:47.87#ibcon#flushed, iclass 38, count 0 2006.285.17:15:47.87#ibcon#about to write, iclass 38, count 0 2006.285.17:15:47.87#ibcon#wrote, iclass 38, count 0 2006.285.17:15:47.87#ibcon#about to read 3, iclass 38, count 0 2006.285.17:15:47.89#ibcon#read 3, iclass 38, count 0 2006.285.17:15:47.89#ibcon#about to read 4, iclass 38, count 0 2006.285.17:15:47.89#ibcon#read 4, iclass 38, count 0 2006.285.17:15:47.89#ibcon#about to read 5, iclass 38, count 0 2006.285.17:15:47.89#ibcon#read 5, iclass 38, count 0 2006.285.17:15:47.89#ibcon#about to read 6, iclass 38, count 0 2006.285.17:15:47.89#ibcon#read 6, iclass 38, count 0 2006.285.17:15:47.89#ibcon#end of sib2, iclass 38, count 0 2006.285.17:15:47.89#ibcon#*mode == 0, iclass 38, count 0 2006.285.17:15:47.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.17:15:47.89#ibcon#[27=USB\r\n] 2006.285.17:15:47.89#ibcon#*before write, iclass 38, count 0 2006.285.17:15:47.89#ibcon#enter sib2, iclass 38, count 0 2006.285.17:15:47.89#ibcon#flushed, iclass 38, count 0 2006.285.17:15:47.89#ibcon#about to write, iclass 38, count 0 2006.285.17:15:47.89#ibcon#wrote, iclass 38, count 0 2006.285.17:15:47.89#ibcon#about to read 3, iclass 38, count 0 2006.285.17:15:47.92#ibcon#read 3, iclass 38, count 0 2006.285.17:15:47.92#ibcon#about to read 4, iclass 38, count 0 2006.285.17:15:47.92#ibcon#read 4, iclass 38, count 0 2006.285.17:15:47.92#ibcon#about to read 5, iclass 38, count 0 2006.285.17:15:47.92#ibcon#read 5, iclass 38, count 0 2006.285.17:15:47.92#ibcon#about to read 6, iclass 38, count 0 2006.285.17:15:47.92#ibcon#read 6, iclass 38, count 0 2006.285.17:15:47.92#ibcon#end of sib2, iclass 38, count 0 2006.285.17:15:47.92#ibcon#*after write, iclass 38, count 0 2006.285.17:15:47.92#ibcon#*before return 0, iclass 38, count 0 2006.285.17:15:47.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:15:47.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:15:47.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.17:15:47.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.17:15:47.92$vck44/vblo=7,734.99 2006.285.17:15:47.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.17:15:47.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.17:15:47.92#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:47.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:15:47.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:15:47.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:15:47.92#ibcon#enter wrdev, iclass 40, count 0 2006.285.17:15:47.92#ibcon#first serial, iclass 40, count 0 2006.285.17:15:47.92#ibcon#enter sib2, iclass 40, count 0 2006.285.17:15:47.92#ibcon#flushed, iclass 40, count 0 2006.285.17:15:47.92#ibcon#about to write, iclass 40, count 0 2006.285.17:15:47.92#ibcon#wrote, iclass 40, count 0 2006.285.17:15:47.92#ibcon#about to read 3, iclass 40, count 0 2006.285.17:15:47.94#ibcon#read 3, iclass 40, count 0 2006.285.17:15:47.94#ibcon#about to read 4, iclass 40, count 0 2006.285.17:15:47.94#ibcon#read 4, iclass 40, count 0 2006.285.17:15:47.94#ibcon#about to read 5, iclass 40, count 0 2006.285.17:15:47.94#ibcon#read 5, iclass 40, count 0 2006.285.17:15:47.94#ibcon#about to read 6, iclass 40, count 0 2006.285.17:15:47.94#ibcon#read 6, iclass 40, count 0 2006.285.17:15:47.94#ibcon#end of sib2, iclass 40, count 0 2006.285.17:15:47.94#ibcon#*mode == 0, iclass 40, count 0 2006.285.17:15:47.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.17:15:47.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.17:15:47.94#ibcon#*before write, iclass 40, count 0 2006.285.17:15:47.94#ibcon#enter sib2, iclass 40, count 0 2006.285.17:15:47.94#ibcon#flushed, iclass 40, count 0 2006.285.17:15:47.94#ibcon#about to write, iclass 40, count 0 2006.285.17:15:47.94#ibcon#wrote, iclass 40, count 0 2006.285.17:15:47.94#ibcon#about to read 3, iclass 40, count 0 2006.285.17:15:47.98#ibcon#read 3, iclass 40, count 0 2006.285.17:15:47.98#ibcon#about to read 4, iclass 40, count 0 2006.285.17:15:47.98#ibcon#read 4, iclass 40, count 0 2006.285.17:15:47.98#ibcon#about to read 5, iclass 40, count 0 2006.285.17:15:47.98#ibcon#read 5, iclass 40, count 0 2006.285.17:15:47.98#ibcon#about to read 6, iclass 40, count 0 2006.285.17:15:47.98#ibcon#read 6, iclass 40, count 0 2006.285.17:15:47.98#ibcon#end of sib2, iclass 40, count 0 2006.285.17:15:47.98#ibcon#*after write, iclass 40, count 0 2006.285.17:15:47.98#ibcon#*before return 0, iclass 40, count 0 2006.285.17:15:47.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:15:47.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:15:47.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.17:15:47.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.17:15:47.98$vck44/vb=7,4 2006.285.17:15:47.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.17:15:47.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.17:15:47.98#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:47.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:15:48.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:15:48.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:15:48.04#ibcon#enter wrdev, iclass 4, count 2 2006.285.17:15:48.04#ibcon#first serial, iclass 4, count 2 2006.285.17:15:48.04#ibcon#enter sib2, iclass 4, count 2 2006.285.17:15:48.04#ibcon#flushed, iclass 4, count 2 2006.285.17:15:48.04#ibcon#about to write, iclass 4, count 2 2006.285.17:15:48.04#ibcon#wrote, iclass 4, count 2 2006.285.17:15:48.04#ibcon#about to read 3, iclass 4, count 2 2006.285.17:15:48.06#ibcon#read 3, iclass 4, count 2 2006.285.17:15:48.06#ibcon#about to read 4, iclass 4, count 2 2006.285.17:15:48.06#ibcon#read 4, iclass 4, count 2 2006.285.17:15:48.06#ibcon#about to read 5, iclass 4, count 2 2006.285.17:15:48.06#ibcon#read 5, iclass 4, count 2 2006.285.17:15:48.06#ibcon#about to read 6, iclass 4, count 2 2006.285.17:15:48.06#ibcon#read 6, iclass 4, count 2 2006.285.17:15:48.06#ibcon#end of sib2, iclass 4, count 2 2006.285.17:15:48.06#ibcon#*mode == 0, iclass 4, count 2 2006.285.17:15:48.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.17:15:48.06#ibcon#[27=AT07-04\r\n] 2006.285.17:15:48.06#ibcon#*before write, iclass 4, count 2 2006.285.17:15:48.06#ibcon#enter sib2, iclass 4, count 2 2006.285.17:15:48.06#ibcon#flushed, iclass 4, count 2 2006.285.17:15:48.06#ibcon#about to write, iclass 4, count 2 2006.285.17:15:48.06#ibcon#wrote, iclass 4, count 2 2006.285.17:15:48.06#ibcon#about to read 3, iclass 4, count 2 2006.285.17:15:48.09#ibcon#read 3, iclass 4, count 2 2006.285.17:15:48.09#ibcon#about to read 4, iclass 4, count 2 2006.285.17:15:48.09#ibcon#read 4, iclass 4, count 2 2006.285.17:15:48.09#ibcon#about to read 5, iclass 4, count 2 2006.285.17:15:48.09#ibcon#read 5, iclass 4, count 2 2006.285.17:15:48.09#ibcon#about to read 6, iclass 4, count 2 2006.285.17:15:48.09#ibcon#read 6, iclass 4, count 2 2006.285.17:15:48.09#ibcon#end of sib2, iclass 4, count 2 2006.285.17:15:48.09#ibcon#*after write, iclass 4, count 2 2006.285.17:15:48.09#ibcon#*before return 0, iclass 4, count 2 2006.285.17:15:48.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:15:48.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:15:48.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.17:15:48.09#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:48.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:15:48.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:15:48.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:15:48.21#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:15:48.21#ibcon#first serial, iclass 4, count 0 2006.285.17:15:48.21#ibcon#enter sib2, iclass 4, count 0 2006.285.17:15:48.21#ibcon#flushed, iclass 4, count 0 2006.285.17:15:48.21#ibcon#about to write, iclass 4, count 0 2006.285.17:15:48.21#ibcon#wrote, iclass 4, count 0 2006.285.17:15:48.21#ibcon#about to read 3, iclass 4, count 0 2006.285.17:15:48.23#ibcon#read 3, iclass 4, count 0 2006.285.17:15:48.23#ibcon#about to read 4, iclass 4, count 0 2006.285.17:15:48.23#ibcon#read 4, iclass 4, count 0 2006.285.17:15:48.23#ibcon#about to read 5, iclass 4, count 0 2006.285.17:15:48.23#ibcon#read 5, iclass 4, count 0 2006.285.17:15:48.23#ibcon#about to read 6, iclass 4, count 0 2006.285.17:15:48.23#ibcon#read 6, iclass 4, count 0 2006.285.17:15:48.23#ibcon#end of sib2, iclass 4, count 0 2006.285.17:15:48.23#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:15:48.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:15:48.23#ibcon#[27=USB\r\n] 2006.285.17:15:48.23#ibcon#*before write, iclass 4, count 0 2006.285.17:15:48.23#ibcon#enter sib2, iclass 4, count 0 2006.285.17:15:48.23#ibcon#flushed, iclass 4, count 0 2006.285.17:15:48.23#ibcon#about to write, iclass 4, count 0 2006.285.17:15:48.23#ibcon#wrote, iclass 4, count 0 2006.285.17:15:48.23#ibcon#about to read 3, iclass 4, count 0 2006.285.17:15:48.26#ibcon#read 3, iclass 4, count 0 2006.285.17:15:48.26#ibcon#about to read 4, iclass 4, count 0 2006.285.17:15:48.26#ibcon#read 4, iclass 4, count 0 2006.285.17:15:48.26#ibcon#about to read 5, iclass 4, count 0 2006.285.17:15:48.26#ibcon#read 5, iclass 4, count 0 2006.285.17:15:48.26#ibcon#about to read 6, iclass 4, count 0 2006.285.17:15:48.26#ibcon#read 6, iclass 4, count 0 2006.285.17:15:48.26#ibcon#end of sib2, iclass 4, count 0 2006.285.17:15:48.26#ibcon#*after write, iclass 4, count 0 2006.285.17:15:48.26#ibcon#*before return 0, iclass 4, count 0 2006.285.17:15:48.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:15:48.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:15:48.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:15:48.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:15:48.26$vck44/vblo=8,744.99 2006.285.17:15:48.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.17:15:48.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.17:15:48.26#ibcon#ireg 17 cls_cnt 0 2006.285.17:15:48.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:15:48.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:15:48.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:15:48.26#ibcon#enter wrdev, iclass 6, count 0 2006.285.17:15:48.26#ibcon#first serial, iclass 6, count 0 2006.285.17:15:48.26#ibcon#enter sib2, iclass 6, count 0 2006.285.17:15:48.26#ibcon#flushed, iclass 6, count 0 2006.285.17:15:48.26#ibcon#about to write, iclass 6, count 0 2006.285.17:15:48.26#ibcon#wrote, iclass 6, count 0 2006.285.17:15:48.26#ibcon#about to read 3, iclass 6, count 0 2006.285.17:15:48.28#ibcon#read 3, iclass 6, count 0 2006.285.17:15:48.28#ibcon#about to read 4, iclass 6, count 0 2006.285.17:15:48.28#ibcon#read 4, iclass 6, count 0 2006.285.17:15:48.28#ibcon#about to read 5, iclass 6, count 0 2006.285.17:15:48.28#ibcon#read 5, iclass 6, count 0 2006.285.17:15:48.28#ibcon#about to read 6, iclass 6, count 0 2006.285.17:15:48.28#ibcon#read 6, iclass 6, count 0 2006.285.17:15:48.28#ibcon#end of sib2, iclass 6, count 0 2006.285.17:15:48.28#ibcon#*mode == 0, iclass 6, count 0 2006.285.17:15:48.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.17:15:48.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.17:15:48.28#ibcon#*before write, iclass 6, count 0 2006.285.17:15:48.28#ibcon#enter sib2, iclass 6, count 0 2006.285.17:15:48.28#ibcon#flushed, iclass 6, count 0 2006.285.17:15:48.28#ibcon#about to write, iclass 6, count 0 2006.285.17:15:48.28#ibcon#wrote, iclass 6, count 0 2006.285.17:15:48.28#ibcon#about to read 3, iclass 6, count 0 2006.285.17:15:48.32#ibcon#read 3, iclass 6, count 0 2006.285.17:15:48.32#ibcon#about to read 4, iclass 6, count 0 2006.285.17:15:48.32#ibcon#read 4, iclass 6, count 0 2006.285.17:15:48.32#ibcon#about to read 5, iclass 6, count 0 2006.285.17:15:48.32#ibcon#read 5, iclass 6, count 0 2006.285.17:15:48.32#ibcon#about to read 6, iclass 6, count 0 2006.285.17:15:48.32#ibcon#read 6, iclass 6, count 0 2006.285.17:15:48.32#ibcon#end of sib2, iclass 6, count 0 2006.285.17:15:48.32#ibcon#*after write, iclass 6, count 0 2006.285.17:15:48.32#ibcon#*before return 0, iclass 6, count 0 2006.285.17:15:48.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:15:48.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:15:48.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.17:15:48.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.17:15:48.32$vck44/vb=8,4 2006.285.17:15:48.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.17:15:48.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.17:15:48.32#ibcon#ireg 11 cls_cnt 2 2006.285.17:15:48.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:15:48.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:15:48.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:15:48.38#ibcon#enter wrdev, iclass 10, count 2 2006.285.17:15:48.38#ibcon#first serial, iclass 10, count 2 2006.285.17:15:48.38#ibcon#enter sib2, iclass 10, count 2 2006.285.17:15:48.38#ibcon#flushed, iclass 10, count 2 2006.285.17:15:48.38#ibcon#about to write, iclass 10, count 2 2006.285.17:15:48.38#ibcon#wrote, iclass 10, count 2 2006.285.17:15:48.38#ibcon#about to read 3, iclass 10, count 2 2006.285.17:15:48.40#ibcon#read 3, iclass 10, count 2 2006.285.17:15:48.40#ibcon#about to read 4, iclass 10, count 2 2006.285.17:15:48.40#ibcon#read 4, iclass 10, count 2 2006.285.17:15:48.40#ibcon#about to read 5, iclass 10, count 2 2006.285.17:15:48.40#ibcon#read 5, iclass 10, count 2 2006.285.17:15:48.40#ibcon#about to read 6, iclass 10, count 2 2006.285.17:15:48.40#ibcon#read 6, iclass 10, count 2 2006.285.17:15:48.40#ibcon#end of sib2, iclass 10, count 2 2006.285.17:15:48.40#ibcon#*mode == 0, iclass 10, count 2 2006.285.17:15:48.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.17:15:48.40#ibcon#[27=AT08-04\r\n] 2006.285.17:15:48.40#ibcon#*before write, iclass 10, count 2 2006.285.17:15:48.40#ibcon#enter sib2, iclass 10, count 2 2006.285.17:15:48.40#ibcon#flushed, iclass 10, count 2 2006.285.17:15:48.40#ibcon#about to write, iclass 10, count 2 2006.285.17:15:48.40#ibcon#wrote, iclass 10, count 2 2006.285.17:15:48.40#ibcon#about to read 3, iclass 10, count 2 2006.285.17:15:48.43#ibcon#read 3, iclass 10, count 2 2006.285.17:15:48.55#ibcon#about to read 4, iclass 10, count 2 2006.285.17:15:48.55#ibcon#read 4, iclass 10, count 2 2006.285.17:15:48.55#ibcon#about to read 5, iclass 10, count 2 2006.285.17:15:48.55#ibcon#read 5, iclass 10, count 2 2006.285.17:15:48.55#ibcon#about to read 6, iclass 10, count 2 2006.285.17:15:48.55#ibcon#read 6, iclass 10, count 2 2006.285.17:15:48.55#ibcon#end of sib2, iclass 10, count 2 2006.285.17:15:48.55#ibcon#*after write, iclass 10, count 2 2006.285.17:15:48.55#ibcon#*before return 0, iclass 10, count 2 2006.285.17:15:48.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:15:48.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:15:48.55#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.17:15:48.55#ibcon#ireg 7 cls_cnt 0 2006.285.17:15:48.55#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:15:48.66#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:15:48.66#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:15:48.66#ibcon#enter wrdev, iclass 10, count 0 2006.285.17:15:48.66#ibcon#first serial, iclass 10, count 0 2006.285.17:15:48.66#ibcon#enter sib2, iclass 10, count 0 2006.285.17:15:48.66#ibcon#flushed, iclass 10, count 0 2006.285.17:15:48.66#ibcon#about to write, iclass 10, count 0 2006.285.17:15:48.66#ibcon#wrote, iclass 10, count 0 2006.285.17:15:48.66#ibcon#about to read 3, iclass 10, count 0 2006.285.17:15:48.68#ibcon#read 3, iclass 10, count 0 2006.285.17:15:48.68#ibcon#about to read 4, iclass 10, count 0 2006.285.17:15:48.68#ibcon#read 4, iclass 10, count 0 2006.285.17:15:48.68#ibcon#about to read 5, iclass 10, count 0 2006.285.17:15:48.68#ibcon#read 5, iclass 10, count 0 2006.285.17:15:48.68#ibcon#about to read 6, iclass 10, count 0 2006.285.17:15:48.68#ibcon#read 6, iclass 10, count 0 2006.285.17:15:48.68#ibcon#end of sib2, iclass 10, count 0 2006.285.17:15:48.68#ibcon#*mode == 0, iclass 10, count 0 2006.285.17:15:48.68#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.17:15:48.68#ibcon#[27=USB\r\n] 2006.285.17:15:48.68#ibcon#*before write, iclass 10, count 0 2006.285.17:15:48.68#ibcon#enter sib2, iclass 10, count 0 2006.285.17:15:48.68#ibcon#flushed, iclass 10, count 0 2006.285.17:15:48.68#ibcon#about to write, iclass 10, count 0 2006.285.17:15:48.68#ibcon#wrote, iclass 10, count 0 2006.285.17:15:48.68#ibcon#about to read 3, iclass 10, count 0 2006.285.17:15:48.71#ibcon#read 3, iclass 10, count 0 2006.285.17:15:48.71#ibcon#about to read 4, iclass 10, count 0 2006.285.17:15:48.71#ibcon#read 4, iclass 10, count 0 2006.285.17:15:48.71#ibcon#about to read 5, iclass 10, count 0 2006.285.17:15:48.71#ibcon#read 5, iclass 10, count 0 2006.285.17:15:48.71#ibcon#about to read 6, iclass 10, count 0 2006.285.17:15:48.71#ibcon#read 6, iclass 10, count 0 2006.285.17:15:48.71#ibcon#end of sib2, iclass 10, count 0 2006.285.17:15:48.71#ibcon#*after write, iclass 10, count 0 2006.285.17:15:48.71#ibcon#*before return 0, iclass 10, count 0 2006.285.17:15:48.71#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:15:48.71#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:15:48.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.17:15:48.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.17:15:48.71$vck44/vabw=wide 2006.285.17:15:48.71#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.17:15:48.71#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.17:15:48.71#ibcon#ireg 8 cls_cnt 0 2006.285.17:15:48.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:15:48.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:15:48.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:15:48.71#ibcon#enter wrdev, iclass 12, count 0 2006.285.17:15:48.71#ibcon#first serial, iclass 12, count 0 2006.285.17:15:48.71#ibcon#enter sib2, iclass 12, count 0 2006.285.17:15:48.71#ibcon#flushed, iclass 12, count 0 2006.285.17:15:48.71#ibcon#about to write, iclass 12, count 0 2006.285.17:15:48.71#ibcon#wrote, iclass 12, count 0 2006.285.17:15:48.71#ibcon#about to read 3, iclass 12, count 0 2006.285.17:15:48.73#ibcon#read 3, iclass 12, count 0 2006.285.17:15:48.73#ibcon#about to read 4, iclass 12, count 0 2006.285.17:15:48.73#ibcon#read 4, iclass 12, count 0 2006.285.17:15:48.73#ibcon#about to read 5, iclass 12, count 0 2006.285.17:15:48.73#ibcon#read 5, iclass 12, count 0 2006.285.17:15:48.73#ibcon#about to read 6, iclass 12, count 0 2006.285.17:15:48.73#ibcon#read 6, iclass 12, count 0 2006.285.17:15:48.73#ibcon#end of sib2, iclass 12, count 0 2006.285.17:15:48.73#ibcon#*mode == 0, iclass 12, count 0 2006.285.17:15:48.73#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.17:15:48.73#ibcon#[25=BW32\r\n] 2006.285.17:15:48.73#ibcon#*before write, iclass 12, count 0 2006.285.17:15:48.73#ibcon#enter sib2, iclass 12, count 0 2006.285.17:15:48.73#ibcon#flushed, iclass 12, count 0 2006.285.17:15:48.73#ibcon#about to write, iclass 12, count 0 2006.285.17:15:48.73#ibcon#wrote, iclass 12, count 0 2006.285.17:15:48.73#ibcon#about to read 3, iclass 12, count 0 2006.285.17:15:48.76#ibcon#read 3, iclass 12, count 0 2006.285.17:15:48.76#ibcon#about to read 4, iclass 12, count 0 2006.285.17:15:48.76#ibcon#read 4, iclass 12, count 0 2006.285.17:15:48.76#ibcon#about to read 5, iclass 12, count 0 2006.285.17:15:48.76#ibcon#read 5, iclass 12, count 0 2006.285.17:15:48.76#ibcon#about to read 6, iclass 12, count 0 2006.285.17:15:48.76#ibcon#read 6, iclass 12, count 0 2006.285.17:15:48.76#ibcon#end of sib2, iclass 12, count 0 2006.285.17:15:48.76#ibcon#*after write, iclass 12, count 0 2006.285.17:15:48.76#ibcon#*before return 0, iclass 12, count 0 2006.285.17:15:48.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:15:48.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:15:48.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.17:15:48.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.17:15:48.76$vck44/vbbw=wide 2006.285.17:15:48.76#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.17:15:48.76#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.17:15:48.76#ibcon#ireg 8 cls_cnt 0 2006.285.17:15:48.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:15:48.83#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:15:48.83#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:15:48.83#ibcon#enter wrdev, iclass 14, count 0 2006.285.17:15:48.83#ibcon#first serial, iclass 14, count 0 2006.285.17:15:48.83#ibcon#enter sib2, iclass 14, count 0 2006.285.17:15:48.83#ibcon#flushed, iclass 14, count 0 2006.285.17:15:48.83#ibcon#about to write, iclass 14, count 0 2006.285.17:15:48.83#ibcon#wrote, iclass 14, count 0 2006.285.17:15:48.83#ibcon#about to read 3, iclass 14, count 0 2006.285.17:15:48.85#ibcon#read 3, iclass 14, count 0 2006.285.17:15:48.85#ibcon#about to read 4, iclass 14, count 0 2006.285.17:15:48.85#ibcon#read 4, iclass 14, count 0 2006.285.17:15:48.85#ibcon#about to read 5, iclass 14, count 0 2006.285.17:15:48.85#ibcon#read 5, iclass 14, count 0 2006.285.17:15:48.85#ibcon#about to read 6, iclass 14, count 0 2006.285.17:15:48.85#ibcon#read 6, iclass 14, count 0 2006.285.17:15:48.85#ibcon#end of sib2, iclass 14, count 0 2006.285.17:15:48.85#ibcon#*mode == 0, iclass 14, count 0 2006.285.17:15:48.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.17:15:48.85#ibcon#[27=BW32\r\n] 2006.285.17:15:48.85#ibcon#*before write, iclass 14, count 0 2006.285.17:15:48.85#ibcon#enter sib2, iclass 14, count 0 2006.285.17:15:48.85#ibcon#flushed, iclass 14, count 0 2006.285.17:15:48.85#ibcon#about to write, iclass 14, count 0 2006.285.17:15:48.85#ibcon#wrote, iclass 14, count 0 2006.285.17:15:48.85#ibcon#about to read 3, iclass 14, count 0 2006.285.17:15:48.88#ibcon#read 3, iclass 14, count 0 2006.285.17:15:48.88#ibcon#about to read 4, iclass 14, count 0 2006.285.17:15:48.88#ibcon#read 4, iclass 14, count 0 2006.285.17:15:48.88#ibcon#about to read 5, iclass 14, count 0 2006.285.17:15:48.88#ibcon#read 5, iclass 14, count 0 2006.285.17:15:48.88#ibcon#about to read 6, iclass 14, count 0 2006.285.17:15:48.88#ibcon#read 6, iclass 14, count 0 2006.285.17:15:48.88#ibcon#end of sib2, iclass 14, count 0 2006.285.17:15:48.88#ibcon#*after write, iclass 14, count 0 2006.285.17:15:48.88#ibcon#*before return 0, iclass 14, count 0 2006.285.17:15:48.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:15:48.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:15:48.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.17:15:48.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.17:15:48.88$setupk4/ifdk4 2006.285.17:15:48.88$ifdk4/lo= 2006.285.17:15:48.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.17:15:48.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.17:15:48.88$ifdk4/patch= 2006.285.17:15:48.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.17:15:48.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.17:15:48.88$setupk4/!*+20s 2006.285.17:15:55.09#abcon#<5=/13 0.3 1.2 17.11 971014.8\r\n> 2006.285.17:15:55.11#abcon#{5=INTERFACE CLEAR} 2006.285.17:15:55.17#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:15:59.14#trakl#Source acquired 2006.285.17:15:59.14#flagr#flagr/antenna,acquired 2006.285.17:16:02.61$setupk4/"tpicd 2006.285.17:16:02.61$setupk4/echo=off 2006.285.17:16:02.61$setupk4/xlog=off 2006.285.17:16:02.61:!2006.285.17:17:07 2006.285.17:17:07.00:preob 2006.285.17:17:07.14/onsource/TRACKING 2006.285.17:17:07.14:!2006.285.17:17:17 2006.285.17:17:17.00:"tape 2006.285.17:17:17.00:"st=record 2006.285.17:17:17.00:data_valid=on 2006.285.17:17:17.00:midob 2006.285.17:17:17.14/onsource/TRACKING 2006.285.17:17:17.14/wx/17.06,1014.8,97 2006.285.17:17:17.31/cable/+6.5024E-03 2006.285.17:17:18.40/va/01,07,usb,yes,33,36 2006.285.17:17:18.40/va/02,06,usb,yes,33,34 2006.285.17:17:18.40/va/03,07,usb,yes,33,35 2006.285.17:17:18.40/va/04,06,usb,yes,34,36 2006.285.17:17:18.40/va/05,03,usb,yes,34,34 2006.285.17:17:18.40/va/06,04,usb,yes,30,30 2006.285.17:17:18.40/va/07,04,usb,yes,31,31 2006.285.17:17:18.40/va/08,03,usb,yes,32,38 2006.285.17:17:18.63/valo/01,524.99,yes,locked 2006.285.17:17:18.63/valo/02,534.99,yes,locked 2006.285.17:17:18.63/valo/03,564.99,yes,locked 2006.285.17:17:18.63/valo/04,624.99,yes,locked 2006.285.17:17:18.63/valo/05,734.99,yes,locked 2006.285.17:17:18.63/valo/06,814.99,yes,locked 2006.285.17:17:18.63/valo/07,864.99,yes,locked 2006.285.17:17:18.63/valo/08,884.99,yes,locked 2006.285.17:17:19.72/vb/01,04,usb,yes,31,29 2006.285.17:17:19.72/vb/02,05,usb,yes,29,29 2006.285.17:17:19.72/vb/03,04,usb,yes,30,33 2006.285.17:17:19.72/vb/04,05,usb,yes,30,29 2006.285.17:17:19.72/vb/05,04,usb,yes,27,29 2006.285.17:17:19.72/vb/06,03,usb,yes,38,34 2006.285.17:17:19.72/vb/07,04,usb,yes,31,31 2006.285.17:17:19.72/vb/08,04,usb,yes,28,32 2006.285.17:17:19.96/vblo/01,629.99,yes,locked 2006.285.17:17:19.96/vblo/02,634.99,yes,locked 2006.285.17:17:19.96/vblo/03,649.99,yes,locked 2006.285.17:17:19.96/vblo/04,679.99,yes,locked 2006.285.17:17:19.96/vblo/05,709.99,yes,locked 2006.285.17:17:19.96/vblo/06,719.99,yes,locked 2006.285.17:17:19.96/vblo/07,734.99,yes,locked 2006.285.17:17:19.96/vblo/08,744.99,yes,locked 2006.285.17:17:20.11/vabw/8 2006.285.17:17:20.26/vbbw/8 2006.285.17:17:20.35/xfe/off,on,12.0 2006.285.17:17:20.73/ifatt/23,28,28,28 2006.285.17:17:21.07/fmout-gps/S +2.55E-07 2006.285.17:17:21.09:!2006.285.17:22:47 2006.285.17:22:47.00:data_valid=off 2006.285.17:22:47.00:"et 2006.285.17:22:47.00:!+3s 2006.285.17:22:50.01:"tape 2006.285.17:22:50.01:postob 2006.285.17:22:50.11/cable/+6.5031E-03 2006.285.17:22:50.11/wx/16.94,1014.8,98 2006.285.17:22:51.07/fmout-gps/S +2.59E-07 2006.285.17:22:51.07:scan_name=285-1727,jd0610,50 2006.285.17:22:51.07:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.285.17:22:51.14#flagr#flagr/antenna,new-source 2006.285.17:22:52.14:checkk5 2006.285.17:22:52.49/chk_autoobs//k5ts1/ autoobs is running! 2006.285.17:22:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.285.17:22:53.35/chk_autoobs//k5ts3/ autoobs is running! 2006.285.17:22:53.89/chk_autoobs//k5ts4/ autoobs is running! 2006.285.17:22:54.28/chk_obsdata//k5ts1/T2851717??a.dat file size is correct (nominal:1320MB, actual:1320MB). 2006.285.17:22:54.90/chk_obsdata//k5ts2/T2851717??b.dat file size is correct (nominal:1320MB, actual:1320MB). 2006.285.17:22:55.29/chk_obsdata//k5ts3/T2851717??c.dat file size is correct (nominal:1320MB, actual:1320MB). 2006.285.17:22:55.75/chk_obsdata//k5ts4/T2851717??d.dat file size is correct (nominal:1320MB, actual:1320MB). 2006.285.17:22:56.54/k5log//k5ts1_log_newline 2006.285.17:22:57.35/k5log//k5ts2_log_newline 2006.285.17:22:58.13/k5log//k5ts3_log_newline 2006.285.17:22:59.17/k5log//k5ts4_log_newline 2006.285.17:22:59.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.17:22:59.20:setupk4=1 2006.285.17:22:59.20$setupk4/echo=on 2006.285.17:22:59.20$setupk4/pcalon 2006.285.17:22:59.20$pcalon/"no phase cal control is implemented here 2006.285.17:22:59.20$setupk4/"tpicd=stop 2006.285.17:22:59.20$setupk4/"rec=synch_on 2006.285.17:22:59.20$setupk4/"rec_mode=128 2006.285.17:22:59.20$setupk4/!* 2006.285.17:22:59.20$setupk4/recpk4 2006.285.17:22:59.20$recpk4/recpatch= 2006.285.17:22:59.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.17:22:59.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.17:22:59.20$setupk4/vck44 2006.285.17:22:59.20$vck44/valo=1,524.99 2006.285.17:22:59.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.17:22:59.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.17:22:59.20#ibcon#ireg 17 cls_cnt 0 2006.285.17:22:59.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.17:22:59.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.17:22:59.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.17:22:59.20#ibcon#enter wrdev, iclass 5, count 0 2006.285.17:22:59.20#ibcon#first serial, iclass 5, count 0 2006.285.17:22:59.20#ibcon#enter sib2, iclass 5, count 0 2006.285.17:22:59.20#ibcon#flushed, iclass 5, count 0 2006.285.17:22:59.20#ibcon#about to write, iclass 5, count 0 2006.285.17:22:59.20#ibcon#wrote, iclass 5, count 0 2006.285.17:22:59.20#ibcon#about to read 3, iclass 5, count 0 2006.285.17:22:59.22#ibcon#read 3, iclass 5, count 0 2006.285.17:22:59.22#ibcon#about to read 4, iclass 5, count 0 2006.285.17:22:59.22#ibcon#read 4, iclass 5, count 0 2006.285.17:22:59.22#ibcon#about to read 5, iclass 5, count 0 2006.285.17:22:59.22#ibcon#read 5, iclass 5, count 0 2006.285.17:22:59.22#ibcon#about to read 6, iclass 5, count 0 2006.285.17:22:59.22#ibcon#read 6, iclass 5, count 0 2006.285.17:22:59.22#ibcon#end of sib2, iclass 5, count 0 2006.285.17:22:59.22#ibcon#*mode == 0, iclass 5, count 0 2006.285.17:22:59.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.17:22:59.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.17:22:59.22#ibcon#*before write, iclass 5, count 0 2006.285.17:22:59.22#ibcon#enter sib2, iclass 5, count 0 2006.285.17:22:59.22#ibcon#flushed, iclass 5, count 0 2006.285.17:22:59.22#ibcon#about to write, iclass 5, count 0 2006.285.17:22:59.22#ibcon#wrote, iclass 5, count 0 2006.285.17:22:59.22#ibcon#about to read 3, iclass 5, count 0 2006.285.17:22:59.27#ibcon#read 3, iclass 5, count 0 2006.285.17:22:59.27#ibcon#about to read 4, iclass 5, count 0 2006.285.17:22:59.27#ibcon#read 4, iclass 5, count 0 2006.285.17:22:59.27#ibcon#about to read 5, iclass 5, count 0 2006.285.17:22:59.27#ibcon#read 5, iclass 5, count 0 2006.285.17:22:59.27#ibcon#about to read 6, iclass 5, count 0 2006.285.17:22:59.27#ibcon#read 6, iclass 5, count 0 2006.285.17:22:59.27#ibcon#end of sib2, iclass 5, count 0 2006.285.17:22:59.27#ibcon#*after write, iclass 5, count 0 2006.285.17:22:59.27#ibcon#*before return 0, iclass 5, count 0 2006.285.17:22:59.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.17:22:59.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.17:22:59.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.17:22:59.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.17:22:59.27$vck44/va=1,7 2006.285.17:22:59.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.17:22:59.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.17:22:59.27#ibcon#ireg 11 cls_cnt 2 2006.285.17:22:59.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.17:22:59.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.17:22:59.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.17:22:59.27#ibcon#enter wrdev, iclass 7, count 2 2006.285.17:22:59.27#ibcon#first serial, iclass 7, count 2 2006.285.17:22:59.27#ibcon#enter sib2, iclass 7, count 2 2006.285.17:22:59.27#ibcon#flushed, iclass 7, count 2 2006.285.17:22:59.27#ibcon#about to write, iclass 7, count 2 2006.285.17:22:59.27#ibcon#wrote, iclass 7, count 2 2006.285.17:22:59.27#ibcon#about to read 3, iclass 7, count 2 2006.285.17:22:59.29#ibcon#read 3, iclass 7, count 2 2006.285.17:22:59.29#ibcon#about to read 4, iclass 7, count 2 2006.285.17:22:59.29#ibcon#read 4, iclass 7, count 2 2006.285.17:22:59.29#ibcon#about to read 5, iclass 7, count 2 2006.285.17:22:59.29#ibcon#read 5, iclass 7, count 2 2006.285.17:22:59.29#ibcon#about to read 6, iclass 7, count 2 2006.285.17:22:59.29#ibcon#read 6, iclass 7, count 2 2006.285.17:22:59.29#ibcon#end of sib2, iclass 7, count 2 2006.285.17:22:59.29#ibcon#*mode == 0, iclass 7, count 2 2006.285.17:22:59.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.17:22:59.29#ibcon#[25=AT01-07\r\n] 2006.285.17:22:59.29#ibcon#*before write, iclass 7, count 2 2006.285.17:22:59.29#ibcon#enter sib2, iclass 7, count 2 2006.285.17:22:59.29#ibcon#flushed, iclass 7, count 2 2006.285.17:22:59.29#ibcon#about to write, iclass 7, count 2 2006.285.17:22:59.29#ibcon#wrote, iclass 7, count 2 2006.285.17:22:59.29#ibcon#about to read 3, iclass 7, count 2 2006.285.17:22:59.32#ibcon#read 3, iclass 7, count 2 2006.285.17:22:59.32#ibcon#about to read 4, iclass 7, count 2 2006.285.17:22:59.32#ibcon#read 4, iclass 7, count 2 2006.285.17:22:59.32#ibcon#about to read 5, iclass 7, count 2 2006.285.17:22:59.32#ibcon#read 5, iclass 7, count 2 2006.285.17:22:59.32#ibcon#about to read 6, iclass 7, count 2 2006.285.17:22:59.32#ibcon#read 6, iclass 7, count 2 2006.285.17:22:59.32#ibcon#end of sib2, iclass 7, count 2 2006.285.17:22:59.32#ibcon#*after write, iclass 7, count 2 2006.285.17:22:59.32#ibcon#*before return 0, iclass 7, count 2 2006.285.17:22:59.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.17:22:59.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.17:22:59.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.17:22:59.32#ibcon#ireg 7 cls_cnt 0 2006.285.17:22:59.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.17:22:59.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.17:22:59.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.17:22:59.44#ibcon#enter wrdev, iclass 7, count 0 2006.285.17:22:59.44#ibcon#first serial, iclass 7, count 0 2006.285.17:22:59.44#ibcon#enter sib2, iclass 7, count 0 2006.285.17:22:59.44#ibcon#flushed, iclass 7, count 0 2006.285.17:22:59.44#ibcon#about to write, iclass 7, count 0 2006.285.17:22:59.44#ibcon#wrote, iclass 7, count 0 2006.285.17:22:59.44#ibcon#about to read 3, iclass 7, count 0 2006.285.17:22:59.46#ibcon#read 3, iclass 7, count 0 2006.285.17:22:59.46#ibcon#about to read 4, iclass 7, count 0 2006.285.17:22:59.46#ibcon#read 4, iclass 7, count 0 2006.285.17:22:59.46#ibcon#about to read 5, iclass 7, count 0 2006.285.17:22:59.46#ibcon#read 5, iclass 7, count 0 2006.285.17:22:59.46#ibcon#about to read 6, iclass 7, count 0 2006.285.17:22:59.46#ibcon#read 6, iclass 7, count 0 2006.285.17:22:59.46#ibcon#end of sib2, iclass 7, count 0 2006.285.17:22:59.46#ibcon#*mode == 0, iclass 7, count 0 2006.285.17:22:59.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.17:22:59.46#ibcon#[25=USB\r\n] 2006.285.17:22:59.46#ibcon#*before write, iclass 7, count 0 2006.285.17:22:59.46#ibcon#enter sib2, iclass 7, count 0 2006.285.17:22:59.46#ibcon#flushed, iclass 7, count 0 2006.285.17:22:59.46#ibcon#about to write, iclass 7, count 0 2006.285.17:22:59.46#ibcon#wrote, iclass 7, count 0 2006.285.17:22:59.46#ibcon#about to read 3, iclass 7, count 0 2006.285.17:22:59.49#ibcon#read 3, iclass 7, count 0 2006.285.17:22:59.49#ibcon#about to read 4, iclass 7, count 0 2006.285.17:22:59.49#ibcon#read 4, iclass 7, count 0 2006.285.17:22:59.49#ibcon#about to read 5, iclass 7, count 0 2006.285.17:22:59.49#ibcon#read 5, iclass 7, count 0 2006.285.17:22:59.49#ibcon#about to read 6, iclass 7, count 0 2006.285.17:22:59.49#ibcon#read 6, iclass 7, count 0 2006.285.17:22:59.49#ibcon#end of sib2, iclass 7, count 0 2006.285.17:22:59.49#ibcon#*after write, iclass 7, count 0 2006.285.17:22:59.49#ibcon#*before return 0, iclass 7, count 0 2006.285.17:22:59.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.17:22:59.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.17:22:59.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.17:22:59.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.17:22:59.49$vck44/valo=2,534.99 2006.285.17:22:59.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.17:22:59.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.17:22:59.49#ibcon#ireg 17 cls_cnt 0 2006.285.17:22:59.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:22:59.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:22:59.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:22:59.49#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:22:59.49#ibcon#first serial, iclass 11, count 0 2006.285.17:22:59.49#ibcon#enter sib2, iclass 11, count 0 2006.285.17:22:59.49#ibcon#flushed, iclass 11, count 0 2006.285.17:22:59.49#ibcon#about to write, iclass 11, count 0 2006.285.17:22:59.49#ibcon#wrote, iclass 11, count 0 2006.285.17:22:59.49#ibcon#about to read 3, iclass 11, count 0 2006.285.17:22:59.51#ibcon#read 3, iclass 11, count 0 2006.285.17:22:59.51#ibcon#about to read 4, iclass 11, count 0 2006.285.17:22:59.51#ibcon#read 4, iclass 11, count 0 2006.285.17:22:59.51#ibcon#about to read 5, iclass 11, count 0 2006.285.17:22:59.51#ibcon#read 5, iclass 11, count 0 2006.285.17:22:59.51#ibcon#about to read 6, iclass 11, count 0 2006.285.17:22:59.51#ibcon#read 6, iclass 11, count 0 2006.285.17:22:59.51#ibcon#end of sib2, iclass 11, count 0 2006.285.17:22:59.51#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:22:59.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:22:59.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.17:22:59.51#ibcon#*before write, iclass 11, count 0 2006.285.17:22:59.51#ibcon#enter sib2, iclass 11, count 0 2006.285.17:22:59.51#ibcon#flushed, iclass 11, count 0 2006.285.17:22:59.51#ibcon#about to write, iclass 11, count 0 2006.285.17:22:59.51#ibcon#wrote, iclass 11, count 0 2006.285.17:22:59.51#ibcon#about to read 3, iclass 11, count 0 2006.285.17:22:59.55#ibcon#read 3, iclass 11, count 0 2006.285.17:22:59.55#ibcon#about to read 4, iclass 11, count 0 2006.285.17:22:59.55#ibcon#read 4, iclass 11, count 0 2006.285.17:22:59.55#ibcon#about to read 5, iclass 11, count 0 2006.285.17:22:59.55#ibcon#read 5, iclass 11, count 0 2006.285.17:22:59.55#ibcon#about to read 6, iclass 11, count 0 2006.285.17:22:59.55#ibcon#read 6, iclass 11, count 0 2006.285.17:22:59.55#ibcon#end of sib2, iclass 11, count 0 2006.285.17:22:59.55#ibcon#*after write, iclass 11, count 0 2006.285.17:22:59.55#ibcon#*before return 0, iclass 11, count 0 2006.285.17:22:59.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:22:59.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:22:59.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:22:59.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:22:59.55$vck44/va=2,6 2006.285.17:22:59.55#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.17:22:59.55#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.17:22:59.55#ibcon#ireg 11 cls_cnt 2 2006.285.17:22:59.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:22:59.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:22:59.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:22:59.61#ibcon#enter wrdev, iclass 13, count 2 2006.285.17:22:59.61#ibcon#first serial, iclass 13, count 2 2006.285.17:22:59.61#ibcon#enter sib2, iclass 13, count 2 2006.285.17:22:59.61#ibcon#flushed, iclass 13, count 2 2006.285.17:22:59.61#ibcon#about to write, iclass 13, count 2 2006.285.17:22:59.61#ibcon#wrote, iclass 13, count 2 2006.285.17:22:59.61#ibcon#about to read 3, iclass 13, count 2 2006.285.17:22:59.63#ibcon#read 3, iclass 13, count 2 2006.285.17:22:59.63#ibcon#about to read 4, iclass 13, count 2 2006.285.17:22:59.63#ibcon#read 4, iclass 13, count 2 2006.285.17:22:59.63#ibcon#about to read 5, iclass 13, count 2 2006.285.17:22:59.63#ibcon#read 5, iclass 13, count 2 2006.285.17:22:59.63#ibcon#about to read 6, iclass 13, count 2 2006.285.17:22:59.63#ibcon#read 6, iclass 13, count 2 2006.285.17:22:59.63#ibcon#end of sib2, iclass 13, count 2 2006.285.17:22:59.63#ibcon#*mode == 0, iclass 13, count 2 2006.285.17:22:59.63#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.17:22:59.63#ibcon#[25=AT02-06\r\n] 2006.285.17:22:59.63#ibcon#*before write, iclass 13, count 2 2006.285.17:22:59.63#ibcon#enter sib2, iclass 13, count 2 2006.285.17:22:59.63#ibcon#flushed, iclass 13, count 2 2006.285.17:22:59.63#ibcon#about to write, iclass 13, count 2 2006.285.17:22:59.63#ibcon#wrote, iclass 13, count 2 2006.285.17:22:59.63#ibcon#about to read 3, iclass 13, count 2 2006.285.17:22:59.66#ibcon#read 3, iclass 13, count 2 2006.285.17:22:59.66#ibcon#about to read 4, iclass 13, count 2 2006.285.17:22:59.66#ibcon#read 4, iclass 13, count 2 2006.285.17:22:59.66#ibcon#about to read 5, iclass 13, count 2 2006.285.17:22:59.66#ibcon#read 5, iclass 13, count 2 2006.285.17:22:59.66#ibcon#about to read 6, iclass 13, count 2 2006.285.17:22:59.66#ibcon#read 6, iclass 13, count 2 2006.285.17:22:59.66#ibcon#end of sib2, iclass 13, count 2 2006.285.17:22:59.66#ibcon#*after write, iclass 13, count 2 2006.285.17:22:59.66#ibcon#*before return 0, iclass 13, count 2 2006.285.17:22:59.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:22:59.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:22:59.66#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.17:22:59.66#ibcon#ireg 7 cls_cnt 0 2006.285.17:22:59.66#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:22:59.78#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:23:00.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:23:00.21#ibcon#enter wrdev, iclass 13, count 0 2006.285.17:23:00.21#ibcon#first serial, iclass 13, count 0 2006.285.17:23:00.21#ibcon#enter sib2, iclass 13, count 0 2006.285.17:23:00.21#ibcon#flushed, iclass 13, count 0 2006.285.17:23:00.21#ibcon#about to write, iclass 13, count 0 2006.285.17:23:00.21#ibcon#wrote, iclass 13, count 0 2006.285.17:23:00.21#ibcon#about to read 3, iclass 13, count 0 2006.285.17:23:00.22#ibcon#read 3, iclass 13, count 0 2006.285.17:23:00.22#ibcon#about to read 4, iclass 13, count 0 2006.285.17:23:00.22#ibcon#read 4, iclass 13, count 0 2006.285.17:23:00.22#ibcon#about to read 5, iclass 13, count 0 2006.285.17:23:00.22#ibcon#read 5, iclass 13, count 0 2006.285.17:23:00.22#ibcon#about to read 6, iclass 13, count 0 2006.285.17:23:00.22#ibcon#read 6, iclass 13, count 0 2006.285.17:23:00.22#ibcon#end of sib2, iclass 13, count 0 2006.285.17:23:00.22#ibcon#*mode == 0, iclass 13, count 0 2006.285.17:23:00.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.17:23:00.22#ibcon#[25=USB\r\n] 2006.285.17:23:00.22#ibcon#*before write, iclass 13, count 0 2006.285.17:23:00.22#ibcon#enter sib2, iclass 13, count 0 2006.285.17:23:00.22#ibcon#flushed, iclass 13, count 0 2006.285.17:23:00.22#ibcon#about to write, iclass 13, count 0 2006.285.17:23:00.22#ibcon#wrote, iclass 13, count 0 2006.285.17:23:00.22#ibcon#about to read 3, iclass 13, count 0 2006.285.17:23:00.25#ibcon#read 3, iclass 13, count 0 2006.285.17:23:00.25#ibcon#about to read 4, iclass 13, count 0 2006.285.17:23:00.25#ibcon#read 4, iclass 13, count 0 2006.285.17:23:00.25#ibcon#about to read 5, iclass 13, count 0 2006.285.17:23:00.25#ibcon#read 5, iclass 13, count 0 2006.285.17:23:00.25#ibcon#about to read 6, iclass 13, count 0 2006.285.17:23:00.25#ibcon#read 6, iclass 13, count 0 2006.285.17:23:00.25#ibcon#end of sib2, iclass 13, count 0 2006.285.17:23:00.25#ibcon#*after write, iclass 13, count 0 2006.285.17:23:00.25#ibcon#*before return 0, iclass 13, count 0 2006.285.17:23:00.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:23:00.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:23:00.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.17:23:00.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.17:23:00.25$vck44/valo=3,564.99 2006.285.17:23:00.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.17:23:00.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.17:23:00.25#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:00.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:23:00.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:23:00.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:23:00.25#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:23:00.25#ibcon#first serial, iclass 15, count 0 2006.285.17:23:00.25#ibcon#enter sib2, iclass 15, count 0 2006.285.17:23:00.25#ibcon#flushed, iclass 15, count 0 2006.285.17:23:00.25#ibcon#about to write, iclass 15, count 0 2006.285.17:23:00.25#ibcon#wrote, iclass 15, count 0 2006.285.17:23:00.25#ibcon#about to read 3, iclass 15, count 0 2006.285.17:23:00.27#ibcon#read 3, iclass 15, count 0 2006.285.17:23:00.27#ibcon#about to read 4, iclass 15, count 0 2006.285.17:23:00.27#ibcon#read 4, iclass 15, count 0 2006.285.17:23:00.27#ibcon#about to read 5, iclass 15, count 0 2006.285.17:23:00.27#ibcon#read 5, iclass 15, count 0 2006.285.17:23:00.27#ibcon#about to read 6, iclass 15, count 0 2006.285.17:23:00.27#ibcon#read 6, iclass 15, count 0 2006.285.17:23:00.27#ibcon#end of sib2, iclass 15, count 0 2006.285.17:23:00.27#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:23:00.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:23:00.27#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.17:23:00.27#ibcon#*before write, iclass 15, count 0 2006.285.17:23:00.27#ibcon#enter sib2, iclass 15, count 0 2006.285.17:23:00.27#ibcon#flushed, iclass 15, count 0 2006.285.17:23:00.27#ibcon#about to write, iclass 15, count 0 2006.285.17:23:00.27#ibcon#wrote, iclass 15, count 0 2006.285.17:23:00.27#ibcon#about to read 3, iclass 15, count 0 2006.285.17:23:00.31#ibcon#read 3, iclass 15, count 0 2006.285.17:23:00.31#ibcon#about to read 4, iclass 15, count 0 2006.285.17:23:00.31#ibcon#read 4, iclass 15, count 0 2006.285.17:23:00.31#ibcon#about to read 5, iclass 15, count 0 2006.285.17:23:00.31#ibcon#read 5, iclass 15, count 0 2006.285.17:23:00.31#ibcon#about to read 6, iclass 15, count 0 2006.285.17:23:00.31#ibcon#read 6, iclass 15, count 0 2006.285.17:23:00.31#ibcon#end of sib2, iclass 15, count 0 2006.285.17:23:00.31#ibcon#*after write, iclass 15, count 0 2006.285.17:23:00.31#ibcon#*before return 0, iclass 15, count 0 2006.285.17:23:00.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:23:00.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:23:00.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:23:00.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:23:00.31$vck44/va=3,7 2006.285.17:23:00.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.17:23:00.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.17:23:00.31#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:00.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:23:00.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:23:00.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:23:00.37#ibcon#enter wrdev, iclass 17, count 2 2006.285.17:23:00.37#ibcon#first serial, iclass 17, count 2 2006.285.17:23:00.37#ibcon#enter sib2, iclass 17, count 2 2006.285.17:23:00.37#ibcon#flushed, iclass 17, count 2 2006.285.17:23:00.37#ibcon#about to write, iclass 17, count 2 2006.285.17:23:00.37#ibcon#wrote, iclass 17, count 2 2006.285.17:23:00.37#ibcon#about to read 3, iclass 17, count 2 2006.285.17:23:00.39#ibcon#read 3, iclass 17, count 2 2006.285.17:23:00.39#ibcon#about to read 4, iclass 17, count 2 2006.285.17:23:00.39#ibcon#read 4, iclass 17, count 2 2006.285.17:23:00.39#ibcon#about to read 5, iclass 17, count 2 2006.285.17:23:00.39#ibcon#read 5, iclass 17, count 2 2006.285.17:23:00.39#ibcon#about to read 6, iclass 17, count 2 2006.285.17:23:00.39#ibcon#read 6, iclass 17, count 2 2006.285.17:23:00.39#ibcon#end of sib2, iclass 17, count 2 2006.285.17:23:00.39#ibcon#*mode == 0, iclass 17, count 2 2006.285.17:23:00.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.17:23:00.39#ibcon#[25=AT03-07\r\n] 2006.285.17:23:00.39#ibcon#*before write, iclass 17, count 2 2006.285.17:23:00.39#ibcon#enter sib2, iclass 17, count 2 2006.285.17:23:00.39#ibcon#flushed, iclass 17, count 2 2006.285.17:23:00.39#ibcon#about to write, iclass 17, count 2 2006.285.17:23:00.39#ibcon#wrote, iclass 17, count 2 2006.285.17:23:00.39#ibcon#about to read 3, iclass 17, count 2 2006.285.17:23:00.42#ibcon#read 3, iclass 17, count 2 2006.285.17:23:00.42#ibcon#about to read 4, iclass 17, count 2 2006.285.17:23:00.42#ibcon#read 4, iclass 17, count 2 2006.285.17:23:00.42#ibcon#about to read 5, iclass 17, count 2 2006.285.17:23:00.42#ibcon#read 5, iclass 17, count 2 2006.285.17:23:00.42#ibcon#about to read 6, iclass 17, count 2 2006.285.17:23:00.42#ibcon#read 6, iclass 17, count 2 2006.285.17:23:00.42#ibcon#end of sib2, iclass 17, count 2 2006.285.17:23:00.42#ibcon#*after write, iclass 17, count 2 2006.285.17:23:00.42#ibcon#*before return 0, iclass 17, count 2 2006.285.17:23:00.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:23:00.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:23:00.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.17:23:00.42#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:00.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:23:00.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:23:00.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:23:00.54#ibcon#enter wrdev, iclass 17, count 0 2006.285.17:23:00.54#ibcon#first serial, iclass 17, count 0 2006.285.17:23:00.54#ibcon#enter sib2, iclass 17, count 0 2006.285.17:23:00.54#ibcon#flushed, iclass 17, count 0 2006.285.17:23:00.54#ibcon#about to write, iclass 17, count 0 2006.285.17:23:00.54#ibcon#wrote, iclass 17, count 0 2006.285.17:23:00.54#ibcon#about to read 3, iclass 17, count 0 2006.285.17:23:00.56#ibcon#read 3, iclass 17, count 0 2006.285.17:23:00.56#ibcon#about to read 4, iclass 17, count 0 2006.285.17:23:00.56#ibcon#read 4, iclass 17, count 0 2006.285.17:23:00.56#ibcon#about to read 5, iclass 17, count 0 2006.285.17:23:00.56#ibcon#read 5, iclass 17, count 0 2006.285.17:23:00.56#ibcon#about to read 6, iclass 17, count 0 2006.285.17:23:00.56#ibcon#read 6, iclass 17, count 0 2006.285.17:23:00.56#ibcon#end of sib2, iclass 17, count 0 2006.285.17:23:00.56#ibcon#*mode == 0, iclass 17, count 0 2006.285.17:23:00.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.17:23:00.56#ibcon#[25=USB\r\n] 2006.285.17:23:00.56#ibcon#*before write, iclass 17, count 0 2006.285.17:23:00.56#ibcon#enter sib2, iclass 17, count 0 2006.285.17:23:00.56#ibcon#flushed, iclass 17, count 0 2006.285.17:23:00.56#ibcon#about to write, iclass 17, count 0 2006.285.17:23:00.56#ibcon#wrote, iclass 17, count 0 2006.285.17:23:00.56#ibcon#about to read 3, iclass 17, count 0 2006.285.17:23:00.59#ibcon#read 3, iclass 17, count 0 2006.285.17:23:00.59#ibcon#about to read 4, iclass 17, count 0 2006.285.17:23:00.65#ibcon#read 4, iclass 17, count 0 2006.285.17:23:00.65#ibcon#about to read 5, iclass 17, count 0 2006.285.17:23:00.65#ibcon#read 5, iclass 17, count 0 2006.285.17:23:00.65#ibcon#about to read 6, iclass 17, count 0 2006.285.17:23:00.65#ibcon#read 6, iclass 17, count 0 2006.285.17:23:00.65#ibcon#end of sib2, iclass 17, count 0 2006.285.17:23:00.65#ibcon#*after write, iclass 17, count 0 2006.285.17:23:00.65#ibcon#*before return 0, iclass 17, count 0 2006.285.17:23:00.65#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:23:00.65#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:23:00.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.17:23:00.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.17:23:00.65$vck44/valo=4,624.99 2006.285.17:23:00.65#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.17:23:00.65#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.17:23:00.65#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:00.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:23:00.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:23:00.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:23:00.65#ibcon#enter wrdev, iclass 19, count 0 2006.285.17:23:00.65#ibcon#first serial, iclass 19, count 0 2006.285.17:23:00.65#ibcon#enter sib2, iclass 19, count 0 2006.285.17:23:00.65#ibcon#flushed, iclass 19, count 0 2006.285.17:23:00.65#ibcon#about to write, iclass 19, count 0 2006.285.17:23:00.65#ibcon#wrote, iclass 19, count 0 2006.285.17:23:00.65#ibcon#about to read 3, iclass 19, count 0 2006.285.17:23:00.67#ibcon#read 3, iclass 19, count 0 2006.285.17:23:00.67#ibcon#about to read 4, iclass 19, count 0 2006.285.17:23:00.67#ibcon#read 4, iclass 19, count 0 2006.285.17:23:00.67#ibcon#about to read 5, iclass 19, count 0 2006.285.17:23:00.67#ibcon#read 5, iclass 19, count 0 2006.285.17:23:00.67#ibcon#about to read 6, iclass 19, count 0 2006.285.17:23:00.67#ibcon#read 6, iclass 19, count 0 2006.285.17:23:00.67#ibcon#end of sib2, iclass 19, count 0 2006.285.17:23:00.67#ibcon#*mode == 0, iclass 19, count 0 2006.285.17:23:00.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.17:23:00.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.17:23:00.67#ibcon#*before write, iclass 19, count 0 2006.285.17:23:00.67#ibcon#enter sib2, iclass 19, count 0 2006.285.17:23:00.67#ibcon#flushed, iclass 19, count 0 2006.285.17:23:00.67#ibcon#about to write, iclass 19, count 0 2006.285.17:23:00.67#ibcon#wrote, iclass 19, count 0 2006.285.17:23:00.67#ibcon#about to read 3, iclass 19, count 0 2006.285.17:23:00.71#ibcon#read 3, iclass 19, count 0 2006.285.17:23:00.71#ibcon#about to read 4, iclass 19, count 0 2006.285.17:23:00.71#ibcon#read 4, iclass 19, count 0 2006.285.17:23:00.71#ibcon#about to read 5, iclass 19, count 0 2006.285.17:23:00.71#ibcon#read 5, iclass 19, count 0 2006.285.17:23:00.71#ibcon#about to read 6, iclass 19, count 0 2006.285.17:23:00.71#ibcon#read 6, iclass 19, count 0 2006.285.17:23:00.71#ibcon#end of sib2, iclass 19, count 0 2006.285.17:23:00.71#ibcon#*after write, iclass 19, count 0 2006.285.17:23:00.71#ibcon#*before return 0, iclass 19, count 0 2006.285.17:23:00.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:23:00.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:23:00.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.17:23:00.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.17:23:00.71$vck44/va=4,6 2006.285.17:23:00.71#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.17:23:00.71#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.17:23:00.71#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:00.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:23:00.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:23:00.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:23:00.77#ibcon#enter wrdev, iclass 21, count 2 2006.285.17:23:00.77#ibcon#first serial, iclass 21, count 2 2006.285.17:23:00.77#ibcon#enter sib2, iclass 21, count 2 2006.285.17:23:00.77#ibcon#flushed, iclass 21, count 2 2006.285.17:23:00.77#ibcon#about to write, iclass 21, count 2 2006.285.17:23:00.77#ibcon#wrote, iclass 21, count 2 2006.285.17:23:00.77#ibcon#about to read 3, iclass 21, count 2 2006.285.17:23:00.79#ibcon#read 3, iclass 21, count 2 2006.285.17:23:00.79#ibcon#about to read 4, iclass 21, count 2 2006.285.17:23:00.79#ibcon#read 4, iclass 21, count 2 2006.285.17:23:00.79#ibcon#about to read 5, iclass 21, count 2 2006.285.17:23:00.79#ibcon#read 5, iclass 21, count 2 2006.285.17:23:00.79#ibcon#about to read 6, iclass 21, count 2 2006.285.17:23:00.79#ibcon#read 6, iclass 21, count 2 2006.285.17:23:00.79#ibcon#end of sib2, iclass 21, count 2 2006.285.17:23:00.79#ibcon#*mode == 0, iclass 21, count 2 2006.285.17:23:00.79#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.17:23:00.79#ibcon#[25=AT04-06\r\n] 2006.285.17:23:00.79#ibcon#*before write, iclass 21, count 2 2006.285.17:23:00.79#ibcon#enter sib2, iclass 21, count 2 2006.285.17:23:00.79#ibcon#flushed, iclass 21, count 2 2006.285.17:23:00.79#ibcon#about to write, iclass 21, count 2 2006.285.17:23:00.79#ibcon#wrote, iclass 21, count 2 2006.285.17:23:00.79#ibcon#about to read 3, iclass 21, count 2 2006.285.17:23:00.82#ibcon#read 3, iclass 21, count 2 2006.285.17:23:00.82#ibcon#about to read 4, iclass 21, count 2 2006.285.17:23:00.82#ibcon#read 4, iclass 21, count 2 2006.285.17:23:00.82#ibcon#about to read 5, iclass 21, count 2 2006.285.17:23:00.82#ibcon#read 5, iclass 21, count 2 2006.285.17:23:00.82#ibcon#about to read 6, iclass 21, count 2 2006.285.17:23:00.82#ibcon#read 6, iclass 21, count 2 2006.285.17:23:00.82#ibcon#end of sib2, iclass 21, count 2 2006.285.17:23:00.82#ibcon#*after write, iclass 21, count 2 2006.285.17:23:00.82#ibcon#*before return 0, iclass 21, count 2 2006.285.17:23:00.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:23:00.82#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:23:00.82#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.17:23:00.82#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:00.82#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:23:00.94#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:23:00.94#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:23:00.94#ibcon#enter wrdev, iclass 21, count 0 2006.285.17:23:00.94#ibcon#first serial, iclass 21, count 0 2006.285.17:23:00.94#ibcon#enter sib2, iclass 21, count 0 2006.285.17:23:00.94#ibcon#flushed, iclass 21, count 0 2006.285.17:23:00.94#ibcon#about to write, iclass 21, count 0 2006.285.17:23:00.94#ibcon#wrote, iclass 21, count 0 2006.285.17:23:00.94#ibcon#about to read 3, iclass 21, count 0 2006.285.17:23:00.96#ibcon#read 3, iclass 21, count 0 2006.285.17:23:00.96#ibcon#about to read 4, iclass 21, count 0 2006.285.17:23:00.96#ibcon#read 4, iclass 21, count 0 2006.285.17:23:00.96#ibcon#about to read 5, iclass 21, count 0 2006.285.17:23:00.96#ibcon#read 5, iclass 21, count 0 2006.285.17:23:00.96#ibcon#about to read 6, iclass 21, count 0 2006.285.17:23:00.96#ibcon#read 6, iclass 21, count 0 2006.285.17:23:00.96#ibcon#end of sib2, iclass 21, count 0 2006.285.17:23:00.96#ibcon#*mode == 0, iclass 21, count 0 2006.285.17:23:00.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.17:23:00.96#ibcon#[25=USB\r\n] 2006.285.17:23:00.96#ibcon#*before write, iclass 21, count 0 2006.285.17:23:00.96#ibcon#enter sib2, iclass 21, count 0 2006.285.17:23:00.96#ibcon#flushed, iclass 21, count 0 2006.285.17:23:00.96#ibcon#about to write, iclass 21, count 0 2006.285.17:23:00.96#ibcon#wrote, iclass 21, count 0 2006.285.17:23:00.96#ibcon#about to read 3, iclass 21, count 0 2006.285.17:23:00.99#ibcon#read 3, iclass 21, count 0 2006.285.17:23:00.99#ibcon#about to read 4, iclass 21, count 0 2006.285.17:23:00.99#ibcon#read 4, iclass 21, count 0 2006.285.17:23:00.99#ibcon#about to read 5, iclass 21, count 0 2006.285.17:23:00.99#ibcon#read 5, iclass 21, count 0 2006.285.17:23:00.99#ibcon#about to read 6, iclass 21, count 0 2006.285.17:23:00.99#ibcon#read 6, iclass 21, count 0 2006.285.17:23:00.99#ibcon#end of sib2, iclass 21, count 0 2006.285.17:23:00.99#ibcon#*after write, iclass 21, count 0 2006.285.17:23:00.99#ibcon#*before return 0, iclass 21, count 0 2006.285.17:23:00.99#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:23:00.99#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:23:00.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.17:23:00.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.17:23:00.99$vck44/valo=5,734.99 2006.285.17:23:00.99#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.17:23:00.99#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.17:23:00.99#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:00.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:23:00.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:23:00.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:23:00.99#ibcon#enter wrdev, iclass 23, count 0 2006.285.17:23:00.99#ibcon#first serial, iclass 23, count 0 2006.285.17:23:00.99#ibcon#enter sib2, iclass 23, count 0 2006.285.17:23:00.99#ibcon#flushed, iclass 23, count 0 2006.285.17:23:00.99#ibcon#about to write, iclass 23, count 0 2006.285.17:23:00.99#ibcon#wrote, iclass 23, count 0 2006.285.17:23:00.99#ibcon#about to read 3, iclass 23, count 0 2006.285.17:23:01.01#ibcon#read 3, iclass 23, count 0 2006.285.17:23:01.01#ibcon#about to read 4, iclass 23, count 0 2006.285.17:23:01.01#ibcon#read 4, iclass 23, count 0 2006.285.17:23:01.01#ibcon#about to read 5, iclass 23, count 0 2006.285.17:23:01.01#ibcon#read 5, iclass 23, count 0 2006.285.17:23:01.01#ibcon#about to read 6, iclass 23, count 0 2006.285.17:23:01.01#ibcon#read 6, iclass 23, count 0 2006.285.17:23:01.01#ibcon#end of sib2, iclass 23, count 0 2006.285.17:23:01.01#ibcon#*mode == 0, iclass 23, count 0 2006.285.17:23:01.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.17:23:01.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.17:23:01.01#ibcon#*before write, iclass 23, count 0 2006.285.17:23:01.01#ibcon#enter sib2, iclass 23, count 0 2006.285.17:23:01.01#ibcon#flushed, iclass 23, count 0 2006.285.17:23:01.01#ibcon#about to write, iclass 23, count 0 2006.285.17:23:01.01#ibcon#wrote, iclass 23, count 0 2006.285.17:23:01.01#ibcon#about to read 3, iclass 23, count 0 2006.285.17:23:01.05#ibcon#read 3, iclass 23, count 0 2006.285.17:23:01.05#ibcon#about to read 4, iclass 23, count 0 2006.285.17:23:01.05#ibcon#read 4, iclass 23, count 0 2006.285.17:23:01.05#ibcon#about to read 5, iclass 23, count 0 2006.285.17:23:01.05#ibcon#read 5, iclass 23, count 0 2006.285.17:23:01.05#ibcon#about to read 6, iclass 23, count 0 2006.285.17:23:01.05#ibcon#read 6, iclass 23, count 0 2006.285.17:23:01.05#ibcon#end of sib2, iclass 23, count 0 2006.285.17:23:01.05#ibcon#*after write, iclass 23, count 0 2006.285.17:23:01.05#ibcon#*before return 0, iclass 23, count 0 2006.285.17:23:01.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:23:01.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:23:01.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.17:23:01.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.17:23:01.05$vck44/va=5,3 2006.285.17:23:01.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.17:23:01.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.17:23:01.05#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:01.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:23:01.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:23:01.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:23:01.11#ibcon#enter wrdev, iclass 25, count 2 2006.285.17:23:01.11#ibcon#first serial, iclass 25, count 2 2006.285.17:23:01.11#ibcon#enter sib2, iclass 25, count 2 2006.285.17:23:01.11#ibcon#flushed, iclass 25, count 2 2006.285.17:23:01.11#ibcon#about to write, iclass 25, count 2 2006.285.17:23:01.11#ibcon#wrote, iclass 25, count 2 2006.285.17:23:01.11#ibcon#about to read 3, iclass 25, count 2 2006.285.17:23:01.13#ibcon#read 3, iclass 25, count 2 2006.285.17:23:01.13#ibcon#about to read 4, iclass 25, count 2 2006.285.17:23:01.13#ibcon#read 4, iclass 25, count 2 2006.285.17:23:01.13#ibcon#about to read 5, iclass 25, count 2 2006.285.17:23:01.13#ibcon#read 5, iclass 25, count 2 2006.285.17:23:01.13#ibcon#about to read 6, iclass 25, count 2 2006.285.17:23:01.13#ibcon#read 6, iclass 25, count 2 2006.285.17:23:01.13#ibcon#end of sib2, iclass 25, count 2 2006.285.17:23:01.13#ibcon#*mode == 0, iclass 25, count 2 2006.285.17:23:01.13#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.17:23:01.13#ibcon#[25=AT05-03\r\n] 2006.285.17:23:01.13#ibcon#*before write, iclass 25, count 2 2006.285.17:23:01.13#ibcon#enter sib2, iclass 25, count 2 2006.285.17:23:01.13#ibcon#flushed, iclass 25, count 2 2006.285.17:23:01.13#ibcon#about to write, iclass 25, count 2 2006.285.17:23:01.13#ibcon#wrote, iclass 25, count 2 2006.285.17:23:01.13#ibcon#about to read 3, iclass 25, count 2 2006.285.17:23:01.16#ibcon#read 3, iclass 25, count 2 2006.285.17:23:01.16#ibcon#about to read 4, iclass 25, count 2 2006.285.17:23:01.16#ibcon#read 4, iclass 25, count 2 2006.285.17:23:01.16#ibcon#about to read 5, iclass 25, count 2 2006.285.17:23:01.16#ibcon#read 5, iclass 25, count 2 2006.285.17:23:01.16#ibcon#about to read 6, iclass 25, count 2 2006.285.17:23:01.16#ibcon#read 6, iclass 25, count 2 2006.285.17:23:01.16#ibcon#end of sib2, iclass 25, count 2 2006.285.17:23:01.16#ibcon#*after write, iclass 25, count 2 2006.285.17:23:01.16#ibcon#*before return 0, iclass 25, count 2 2006.285.17:23:01.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:23:01.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:23:01.16#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.17:23:01.16#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:01.16#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:23:01.28#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:23:01.28#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:23:01.28#ibcon#enter wrdev, iclass 25, count 0 2006.285.17:23:01.28#ibcon#first serial, iclass 25, count 0 2006.285.17:23:01.28#ibcon#enter sib2, iclass 25, count 0 2006.285.17:23:01.28#ibcon#flushed, iclass 25, count 0 2006.285.17:23:01.28#ibcon#about to write, iclass 25, count 0 2006.285.17:23:01.28#ibcon#wrote, iclass 25, count 0 2006.285.17:23:01.28#ibcon#about to read 3, iclass 25, count 0 2006.285.17:23:01.30#ibcon#read 3, iclass 25, count 0 2006.285.17:23:01.30#ibcon#about to read 4, iclass 25, count 0 2006.285.17:23:01.30#ibcon#read 4, iclass 25, count 0 2006.285.17:23:01.30#ibcon#about to read 5, iclass 25, count 0 2006.285.17:23:01.30#ibcon#read 5, iclass 25, count 0 2006.285.17:23:01.30#ibcon#about to read 6, iclass 25, count 0 2006.285.17:23:01.30#ibcon#read 6, iclass 25, count 0 2006.285.17:23:01.30#ibcon#end of sib2, iclass 25, count 0 2006.285.17:23:01.30#ibcon#*mode == 0, iclass 25, count 0 2006.285.17:23:01.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.17:23:01.30#ibcon#[25=USB\r\n] 2006.285.17:23:01.30#ibcon#*before write, iclass 25, count 0 2006.285.17:23:01.30#ibcon#enter sib2, iclass 25, count 0 2006.285.17:23:01.30#ibcon#flushed, iclass 25, count 0 2006.285.17:23:01.30#ibcon#about to write, iclass 25, count 0 2006.285.17:23:01.30#ibcon#wrote, iclass 25, count 0 2006.285.17:23:01.30#ibcon#about to read 3, iclass 25, count 0 2006.285.17:23:01.33#ibcon#read 3, iclass 25, count 0 2006.285.17:23:01.33#ibcon#about to read 4, iclass 25, count 0 2006.285.17:23:01.33#ibcon#read 4, iclass 25, count 0 2006.285.17:23:01.33#ibcon#about to read 5, iclass 25, count 0 2006.285.17:23:01.33#ibcon#read 5, iclass 25, count 0 2006.285.17:23:01.33#ibcon#about to read 6, iclass 25, count 0 2006.285.17:23:01.33#ibcon#read 6, iclass 25, count 0 2006.285.17:23:01.33#ibcon#end of sib2, iclass 25, count 0 2006.285.17:23:01.33#ibcon#*after write, iclass 25, count 0 2006.285.17:23:01.33#ibcon#*before return 0, iclass 25, count 0 2006.285.17:23:01.33#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:23:01.33#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:23:01.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.17:23:01.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.17:23:01.33$vck44/valo=6,814.99 2006.285.17:23:01.33#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.17:23:01.33#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.17:23:01.33#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:01.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:23:01.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:23:01.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:23:01.33#ibcon#enter wrdev, iclass 27, count 0 2006.285.17:23:01.33#ibcon#first serial, iclass 27, count 0 2006.285.17:23:01.33#ibcon#enter sib2, iclass 27, count 0 2006.285.17:23:01.33#ibcon#flushed, iclass 27, count 0 2006.285.17:23:01.33#ibcon#about to write, iclass 27, count 0 2006.285.17:23:01.33#ibcon#wrote, iclass 27, count 0 2006.285.17:23:01.33#ibcon#about to read 3, iclass 27, count 0 2006.285.17:23:01.35#ibcon#read 3, iclass 27, count 0 2006.285.17:23:01.35#ibcon#about to read 4, iclass 27, count 0 2006.285.17:23:01.35#ibcon#read 4, iclass 27, count 0 2006.285.17:23:01.35#ibcon#about to read 5, iclass 27, count 0 2006.285.17:23:01.35#ibcon#read 5, iclass 27, count 0 2006.285.17:23:01.35#ibcon#about to read 6, iclass 27, count 0 2006.285.17:23:01.35#ibcon#read 6, iclass 27, count 0 2006.285.17:23:01.35#ibcon#end of sib2, iclass 27, count 0 2006.285.17:23:01.35#ibcon#*mode == 0, iclass 27, count 0 2006.285.17:23:01.35#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.17:23:01.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.17:23:01.35#ibcon#*before write, iclass 27, count 0 2006.285.17:23:01.35#ibcon#enter sib2, iclass 27, count 0 2006.285.17:23:01.35#ibcon#flushed, iclass 27, count 0 2006.285.17:23:01.35#ibcon#about to write, iclass 27, count 0 2006.285.17:23:01.35#ibcon#wrote, iclass 27, count 0 2006.285.17:23:01.35#ibcon#about to read 3, iclass 27, count 0 2006.285.17:23:01.39#ibcon#read 3, iclass 27, count 0 2006.285.17:23:01.39#ibcon#about to read 4, iclass 27, count 0 2006.285.17:23:01.39#ibcon#read 4, iclass 27, count 0 2006.285.17:23:01.39#ibcon#about to read 5, iclass 27, count 0 2006.285.17:23:01.39#ibcon#read 5, iclass 27, count 0 2006.285.17:23:01.39#ibcon#about to read 6, iclass 27, count 0 2006.285.17:23:01.39#ibcon#read 6, iclass 27, count 0 2006.285.17:23:01.39#ibcon#end of sib2, iclass 27, count 0 2006.285.17:23:01.39#ibcon#*after write, iclass 27, count 0 2006.285.17:23:01.39#ibcon#*before return 0, iclass 27, count 0 2006.285.17:23:01.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:23:01.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:23:01.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.17:23:01.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.17:23:01.39$vck44/va=6,4 2006.285.17:23:01.39#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.17:23:01.39#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.17:23:01.39#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:01.39#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:23:01.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:23:01.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:23:01.45#ibcon#enter wrdev, iclass 29, count 2 2006.285.17:23:01.45#ibcon#first serial, iclass 29, count 2 2006.285.17:23:01.45#ibcon#enter sib2, iclass 29, count 2 2006.285.17:23:01.45#ibcon#flushed, iclass 29, count 2 2006.285.17:23:01.45#ibcon#about to write, iclass 29, count 2 2006.285.17:23:01.45#ibcon#wrote, iclass 29, count 2 2006.285.17:23:01.45#ibcon#about to read 3, iclass 29, count 2 2006.285.17:23:01.47#ibcon#read 3, iclass 29, count 2 2006.285.17:23:01.47#ibcon#about to read 4, iclass 29, count 2 2006.285.17:23:01.47#ibcon#read 4, iclass 29, count 2 2006.285.17:23:01.47#ibcon#about to read 5, iclass 29, count 2 2006.285.17:23:01.47#ibcon#read 5, iclass 29, count 2 2006.285.17:23:01.47#ibcon#about to read 6, iclass 29, count 2 2006.285.17:23:01.47#ibcon#read 6, iclass 29, count 2 2006.285.17:23:01.47#ibcon#end of sib2, iclass 29, count 2 2006.285.17:23:01.47#ibcon#*mode == 0, iclass 29, count 2 2006.285.17:23:01.47#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.17:23:01.47#ibcon#[25=AT06-04\r\n] 2006.285.17:23:01.47#ibcon#*before write, iclass 29, count 2 2006.285.17:23:01.47#ibcon#enter sib2, iclass 29, count 2 2006.285.17:23:01.47#ibcon#flushed, iclass 29, count 2 2006.285.17:23:01.47#ibcon#about to write, iclass 29, count 2 2006.285.17:23:01.47#ibcon#wrote, iclass 29, count 2 2006.285.17:23:01.47#ibcon#about to read 3, iclass 29, count 2 2006.285.17:23:01.50#ibcon#read 3, iclass 29, count 2 2006.285.17:23:01.50#ibcon#about to read 4, iclass 29, count 2 2006.285.17:23:01.50#ibcon#read 4, iclass 29, count 2 2006.285.17:23:01.50#ibcon#about to read 5, iclass 29, count 2 2006.285.17:23:01.50#ibcon#read 5, iclass 29, count 2 2006.285.17:23:01.50#ibcon#about to read 6, iclass 29, count 2 2006.285.17:23:01.50#ibcon#read 6, iclass 29, count 2 2006.285.17:23:01.50#ibcon#end of sib2, iclass 29, count 2 2006.285.17:23:01.50#ibcon#*after write, iclass 29, count 2 2006.285.17:23:01.50#ibcon#*before return 0, iclass 29, count 2 2006.285.17:23:01.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:23:01.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:23:01.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.17:23:01.50#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:01.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:23:01.62#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:23:01.62#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:23:01.62#ibcon#enter wrdev, iclass 29, count 0 2006.285.17:23:01.62#ibcon#first serial, iclass 29, count 0 2006.285.17:23:01.62#ibcon#enter sib2, iclass 29, count 0 2006.285.17:23:01.62#ibcon#flushed, iclass 29, count 0 2006.285.17:23:01.62#ibcon#about to write, iclass 29, count 0 2006.285.17:23:01.62#ibcon#wrote, iclass 29, count 0 2006.285.17:23:01.62#ibcon#about to read 3, iclass 29, count 0 2006.285.17:23:01.64#ibcon#read 3, iclass 29, count 0 2006.285.17:23:01.64#ibcon#about to read 4, iclass 29, count 0 2006.285.17:23:01.64#ibcon#read 4, iclass 29, count 0 2006.285.17:23:01.64#ibcon#about to read 5, iclass 29, count 0 2006.285.17:23:01.64#ibcon#read 5, iclass 29, count 0 2006.285.17:23:01.64#ibcon#about to read 6, iclass 29, count 0 2006.285.17:23:01.64#ibcon#read 6, iclass 29, count 0 2006.285.17:23:01.64#ibcon#end of sib2, iclass 29, count 0 2006.285.17:23:01.64#ibcon#*mode == 0, iclass 29, count 0 2006.285.17:23:01.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.17:23:01.64#ibcon#[25=USB\r\n] 2006.285.17:23:01.64#ibcon#*before write, iclass 29, count 0 2006.285.17:23:01.64#ibcon#enter sib2, iclass 29, count 0 2006.285.17:23:01.64#ibcon#flushed, iclass 29, count 0 2006.285.17:23:01.64#ibcon#about to write, iclass 29, count 0 2006.285.17:23:01.64#ibcon#wrote, iclass 29, count 0 2006.285.17:23:01.64#ibcon#about to read 3, iclass 29, count 0 2006.285.17:23:01.67#ibcon#read 3, iclass 29, count 0 2006.285.17:23:01.67#ibcon#about to read 4, iclass 29, count 0 2006.285.17:23:01.67#ibcon#read 4, iclass 29, count 0 2006.285.17:23:01.67#ibcon#about to read 5, iclass 29, count 0 2006.285.17:23:01.67#ibcon#read 5, iclass 29, count 0 2006.285.17:23:01.67#ibcon#about to read 6, iclass 29, count 0 2006.285.17:23:01.67#ibcon#read 6, iclass 29, count 0 2006.285.17:23:01.67#ibcon#end of sib2, iclass 29, count 0 2006.285.17:23:01.67#ibcon#*after write, iclass 29, count 0 2006.285.17:23:01.67#ibcon#*before return 0, iclass 29, count 0 2006.285.17:23:01.67#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:23:01.67#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:23:01.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.17:23:01.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.17:23:01.67$vck44/valo=7,864.99 2006.285.17:23:01.67#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.17:23:01.67#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.17:23:01.67#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:01.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:23:01.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:23:01.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:23:01.67#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:23:01.67#ibcon#first serial, iclass 31, count 0 2006.285.17:23:01.67#ibcon#enter sib2, iclass 31, count 0 2006.285.17:23:01.67#ibcon#flushed, iclass 31, count 0 2006.285.17:23:01.67#ibcon#about to write, iclass 31, count 0 2006.285.17:23:01.67#ibcon#wrote, iclass 31, count 0 2006.285.17:23:01.67#ibcon#about to read 3, iclass 31, count 0 2006.285.17:23:01.69#ibcon#read 3, iclass 31, count 0 2006.285.17:23:01.79#ibcon#about to read 4, iclass 31, count 0 2006.285.17:23:01.79#ibcon#read 4, iclass 31, count 0 2006.285.17:23:01.79#ibcon#about to read 5, iclass 31, count 0 2006.285.17:23:01.79#ibcon#read 5, iclass 31, count 0 2006.285.17:23:01.79#ibcon#about to read 6, iclass 31, count 0 2006.285.17:23:01.79#ibcon#read 6, iclass 31, count 0 2006.285.17:23:01.79#ibcon#end of sib2, iclass 31, count 0 2006.285.17:23:01.79#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:23:01.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:23:01.79#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.17:23:01.79#ibcon#*before write, iclass 31, count 0 2006.285.17:23:01.79#ibcon#enter sib2, iclass 31, count 0 2006.285.17:23:01.79#ibcon#flushed, iclass 31, count 0 2006.285.17:23:01.79#ibcon#about to write, iclass 31, count 0 2006.285.17:23:01.79#ibcon#wrote, iclass 31, count 0 2006.285.17:23:01.79#ibcon#about to read 3, iclass 31, count 0 2006.285.17:23:01.83#ibcon#read 3, iclass 31, count 0 2006.285.17:23:01.83#ibcon#about to read 4, iclass 31, count 0 2006.285.17:23:01.83#ibcon#read 4, iclass 31, count 0 2006.285.17:23:01.83#ibcon#about to read 5, iclass 31, count 0 2006.285.17:23:01.83#ibcon#read 5, iclass 31, count 0 2006.285.17:23:01.83#ibcon#about to read 6, iclass 31, count 0 2006.285.17:23:01.83#ibcon#read 6, iclass 31, count 0 2006.285.17:23:01.83#ibcon#end of sib2, iclass 31, count 0 2006.285.17:23:01.83#ibcon#*after write, iclass 31, count 0 2006.285.17:23:01.83#ibcon#*before return 0, iclass 31, count 0 2006.285.17:23:01.83#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:23:01.83#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:23:01.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:23:01.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:23:01.83$vck44/va=7,4 2006.285.17:23:01.83#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.17:23:01.83#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.17:23:01.83#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:01.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:23:01.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:23:01.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:23:01.83#ibcon#enter wrdev, iclass 33, count 2 2006.285.17:23:01.83#ibcon#first serial, iclass 33, count 2 2006.285.17:23:01.83#ibcon#enter sib2, iclass 33, count 2 2006.285.17:23:01.83#ibcon#flushed, iclass 33, count 2 2006.285.17:23:01.83#ibcon#about to write, iclass 33, count 2 2006.285.17:23:01.83#ibcon#wrote, iclass 33, count 2 2006.285.17:23:01.83#ibcon#about to read 3, iclass 33, count 2 2006.285.17:23:01.85#ibcon#read 3, iclass 33, count 2 2006.285.17:23:01.85#ibcon#about to read 4, iclass 33, count 2 2006.285.17:23:01.85#ibcon#read 4, iclass 33, count 2 2006.285.17:23:01.85#ibcon#about to read 5, iclass 33, count 2 2006.285.17:23:01.85#ibcon#read 5, iclass 33, count 2 2006.285.17:23:01.85#ibcon#about to read 6, iclass 33, count 2 2006.285.17:23:01.85#ibcon#read 6, iclass 33, count 2 2006.285.17:23:01.85#ibcon#end of sib2, iclass 33, count 2 2006.285.17:23:01.85#ibcon#*mode == 0, iclass 33, count 2 2006.285.17:23:01.85#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.17:23:01.85#ibcon#[25=AT07-04\r\n] 2006.285.17:23:01.85#ibcon#*before write, iclass 33, count 2 2006.285.17:23:01.85#ibcon#enter sib2, iclass 33, count 2 2006.285.17:23:01.85#ibcon#flushed, iclass 33, count 2 2006.285.17:23:01.85#ibcon#about to write, iclass 33, count 2 2006.285.17:23:01.85#ibcon#wrote, iclass 33, count 2 2006.285.17:23:01.85#ibcon#about to read 3, iclass 33, count 2 2006.285.17:23:01.88#ibcon#read 3, iclass 33, count 2 2006.285.17:23:01.88#ibcon#about to read 4, iclass 33, count 2 2006.285.17:23:01.88#ibcon#read 4, iclass 33, count 2 2006.285.17:23:01.88#ibcon#about to read 5, iclass 33, count 2 2006.285.17:23:01.88#ibcon#read 5, iclass 33, count 2 2006.285.17:23:01.88#ibcon#about to read 6, iclass 33, count 2 2006.285.17:23:01.88#ibcon#read 6, iclass 33, count 2 2006.285.17:23:01.88#ibcon#end of sib2, iclass 33, count 2 2006.285.17:23:01.88#ibcon#*after write, iclass 33, count 2 2006.285.17:23:01.88#ibcon#*before return 0, iclass 33, count 2 2006.285.17:23:01.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:23:01.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:23:01.88#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.17:23:01.88#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:01.88#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:23:02.00#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:23:02.00#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:23:02.00#ibcon#enter wrdev, iclass 33, count 0 2006.285.17:23:02.00#ibcon#first serial, iclass 33, count 0 2006.285.17:23:02.00#ibcon#enter sib2, iclass 33, count 0 2006.285.17:23:02.00#ibcon#flushed, iclass 33, count 0 2006.285.17:23:02.00#ibcon#about to write, iclass 33, count 0 2006.285.17:23:02.00#ibcon#wrote, iclass 33, count 0 2006.285.17:23:02.00#ibcon#about to read 3, iclass 33, count 0 2006.285.17:23:02.02#ibcon#read 3, iclass 33, count 0 2006.285.17:23:02.02#ibcon#about to read 4, iclass 33, count 0 2006.285.17:23:02.02#ibcon#read 4, iclass 33, count 0 2006.285.17:23:02.02#ibcon#about to read 5, iclass 33, count 0 2006.285.17:23:02.02#ibcon#read 5, iclass 33, count 0 2006.285.17:23:02.02#ibcon#about to read 6, iclass 33, count 0 2006.285.17:23:02.02#ibcon#read 6, iclass 33, count 0 2006.285.17:23:02.02#ibcon#end of sib2, iclass 33, count 0 2006.285.17:23:02.02#ibcon#*mode == 0, iclass 33, count 0 2006.285.17:23:02.02#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.17:23:02.02#ibcon#[25=USB\r\n] 2006.285.17:23:02.02#ibcon#*before write, iclass 33, count 0 2006.285.17:23:02.02#ibcon#enter sib2, iclass 33, count 0 2006.285.17:23:02.02#ibcon#flushed, iclass 33, count 0 2006.285.17:23:02.02#ibcon#about to write, iclass 33, count 0 2006.285.17:23:02.02#ibcon#wrote, iclass 33, count 0 2006.285.17:23:02.02#ibcon#about to read 3, iclass 33, count 0 2006.285.17:23:02.05#ibcon#read 3, iclass 33, count 0 2006.285.17:23:02.05#ibcon#about to read 4, iclass 33, count 0 2006.285.17:23:02.05#ibcon#read 4, iclass 33, count 0 2006.285.17:23:02.05#ibcon#about to read 5, iclass 33, count 0 2006.285.17:23:02.05#ibcon#read 5, iclass 33, count 0 2006.285.17:23:02.05#ibcon#about to read 6, iclass 33, count 0 2006.285.17:23:02.05#ibcon#read 6, iclass 33, count 0 2006.285.17:23:02.05#ibcon#end of sib2, iclass 33, count 0 2006.285.17:23:02.05#ibcon#*after write, iclass 33, count 0 2006.285.17:23:02.05#ibcon#*before return 0, iclass 33, count 0 2006.285.17:23:02.05#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:23:02.05#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:23:02.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.17:23:02.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.17:23:02.05$vck44/valo=8,884.99 2006.285.17:23:02.05#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.17:23:02.05#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.17:23:02.05#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:02.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:23:02.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:23:02.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:23:02.05#ibcon#enter wrdev, iclass 35, count 0 2006.285.17:23:02.05#ibcon#first serial, iclass 35, count 0 2006.285.17:23:02.05#ibcon#enter sib2, iclass 35, count 0 2006.285.17:23:02.05#ibcon#flushed, iclass 35, count 0 2006.285.17:23:02.05#ibcon#about to write, iclass 35, count 0 2006.285.17:23:02.05#ibcon#wrote, iclass 35, count 0 2006.285.17:23:02.05#ibcon#about to read 3, iclass 35, count 0 2006.285.17:23:02.07#ibcon#read 3, iclass 35, count 0 2006.285.17:23:02.07#ibcon#about to read 4, iclass 35, count 0 2006.285.17:23:02.07#ibcon#read 4, iclass 35, count 0 2006.285.17:23:02.07#ibcon#about to read 5, iclass 35, count 0 2006.285.17:23:02.07#ibcon#read 5, iclass 35, count 0 2006.285.17:23:02.07#ibcon#about to read 6, iclass 35, count 0 2006.285.17:23:02.07#ibcon#read 6, iclass 35, count 0 2006.285.17:23:02.07#ibcon#end of sib2, iclass 35, count 0 2006.285.17:23:02.07#ibcon#*mode == 0, iclass 35, count 0 2006.285.17:23:02.07#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.17:23:02.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.17:23:02.07#ibcon#*before write, iclass 35, count 0 2006.285.17:23:02.07#ibcon#enter sib2, iclass 35, count 0 2006.285.17:23:02.07#ibcon#flushed, iclass 35, count 0 2006.285.17:23:02.07#ibcon#about to write, iclass 35, count 0 2006.285.17:23:02.07#ibcon#wrote, iclass 35, count 0 2006.285.17:23:02.07#ibcon#about to read 3, iclass 35, count 0 2006.285.17:23:02.11#ibcon#read 3, iclass 35, count 0 2006.285.17:23:02.11#ibcon#about to read 4, iclass 35, count 0 2006.285.17:23:02.11#ibcon#read 4, iclass 35, count 0 2006.285.17:23:02.11#ibcon#about to read 5, iclass 35, count 0 2006.285.17:23:02.11#ibcon#read 5, iclass 35, count 0 2006.285.17:23:02.11#ibcon#about to read 6, iclass 35, count 0 2006.285.17:23:02.11#ibcon#read 6, iclass 35, count 0 2006.285.17:23:02.11#ibcon#end of sib2, iclass 35, count 0 2006.285.17:23:02.11#ibcon#*after write, iclass 35, count 0 2006.285.17:23:02.11#ibcon#*before return 0, iclass 35, count 0 2006.285.17:23:02.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:23:02.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:23:02.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.17:23:02.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.17:23:02.11$vck44/va=8,3 2006.285.17:23:02.11#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.17:23:02.11#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.17:23:02.11#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:02.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:23:02.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:23:02.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:23:02.17#ibcon#enter wrdev, iclass 37, count 2 2006.285.17:23:02.17#ibcon#first serial, iclass 37, count 2 2006.285.17:23:02.17#ibcon#enter sib2, iclass 37, count 2 2006.285.17:23:02.17#ibcon#flushed, iclass 37, count 2 2006.285.17:23:02.17#ibcon#about to write, iclass 37, count 2 2006.285.17:23:02.17#ibcon#wrote, iclass 37, count 2 2006.285.17:23:02.17#ibcon#about to read 3, iclass 37, count 2 2006.285.17:23:02.19#ibcon#read 3, iclass 37, count 2 2006.285.17:23:02.19#ibcon#about to read 4, iclass 37, count 2 2006.285.17:23:02.19#ibcon#read 4, iclass 37, count 2 2006.285.17:23:02.19#ibcon#about to read 5, iclass 37, count 2 2006.285.17:23:02.19#ibcon#read 5, iclass 37, count 2 2006.285.17:23:02.19#ibcon#about to read 6, iclass 37, count 2 2006.285.17:23:02.19#ibcon#read 6, iclass 37, count 2 2006.285.17:23:02.19#ibcon#end of sib2, iclass 37, count 2 2006.285.17:23:02.19#ibcon#*mode == 0, iclass 37, count 2 2006.285.17:23:02.19#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.17:23:02.19#ibcon#[25=AT08-03\r\n] 2006.285.17:23:02.19#ibcon#*before write, iclass 37, count 2 2006.285.17:23:02.19#ibcon#enter sib2, iclass 37, count 2 2006.285.17:23:02.19#ibcon#flushed, iclass 37, count 2 2006.285.17:23:02.19#ibcon#about to write, iclass 37, count 2 2006.285.17:23:02.19#ibcon#wrote, iclass 37, count 2 2006.285.17:23:02.19#ibcon#about to read 3, iclass 37, count 2 2006.285.17:23:02.22#ibcon#read 3, iclass 37, count 2 2006.285.17:23:02.22#ibcon#about to read 4, iclass 37, count 2 2006.285.17:23:02.22#ibcon#read 4, iclass 37, count 2 2006.285.17:23:02.22#ibcon#about to read 5, iclass 37, count 2 2006.285.17:23:02.22#ibcon#read 5, iclass 37, count 2 2006.285.17:23:02.22#ibcon#about to read 6, iclass 37, count 2 2006.285.17:23:02.22#ibcon#read 6, iclass 37, count 2 2006.285.17:23:02.22#ibcon#end of sib2, iclass 37, count 2 2006.285.17:23:02.22#ibcon#*after write, iclass 37, count 2 2006.285.17:23:02.22#ibcon#*before return 0, iclass 37, count 2 2006.285.17:23:02.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:23:02.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:23:02.22#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.17:23:02.22#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:02.22#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:23:02.34#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:23:02.34#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:23:02.34#ibcon#enter wrdev, iclass 37, count 0 2006.285.17:23:02.34#ibcon#first serial, iclass 37, count 0 2006.285.17:23:02.34#ibcon#enter sib2, iclass 37, count 0 2006.285.17:23:02.34#ibcon#flushed, iclass 37, count 0 2006.285.17:23:02.34#ibcon#about to write, iclass 37, count 0 2006.285.17:23:02.34#ibcon#wrote, iclass 37, count 0 2006.285.17:23:02.34#ibcon#about to read 3, iclass 37, count 0 2006.285.17:23:02.36#ibcon#read 3, iclass 37, count 0 2006.285.17:23:02.36#ibcon#about to read 4, iclass 37, count 0 2006.285.17:23:02.36#ibcon#read 4, iclass 37, count 0 2006.285.17:23:02.36#ibcon#about to read 5, iclass 37, count 0 2006.285.17:23:02.36#ibcon#read 5, iclass 37, count 0 2006.285.17:23:02.36#ibcon#about to read 6, iclass 37, count 0 2006.285.17:23:02.36#ibcon#read 6, iclass 37, count 0 2006.285.17:23:02.36#ibcon#end of sib2, iclass 37, count 0 2006.285.17:23:02.36#ibcon#*mode == 0, iclass 37, count 0 2006.285.17:23:02.36#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.17:23:02.36#ibcon#[25=USB\r\n] 2006.285.17:23:02.36#ibcon#*before write, iclass 37, count 0 2006.285.17:23:02.36#ibcon#enter sib2, iclass 37, count 0 2006.285.17:23:02.36#ibcon#flushed, iclass 37, count 0 2006.285.17:23:02.36#ibcon#about to write, iclass 37, count 0 2006.285.17:23:02.36#ibcon#wrote, iclass 37, count 0 2006.285.17:23:02.36#ibcon#about to read 3, iclass 37, count 0 2006.285.17:23:02.39#ibcon#read 3, iclass 37, count 0 2006.285.17:23:02.39#ibcon#about to read 4, iclass 37, count 0 2006.285.17:23:02.39#ibcon#read 4, iclass 37, count 0 2006.285.17:23:02.39#ibcon#about to read 5, iclass 37, count 0 2006.285.17:23:02.39#ibcon#read 5, iclass 37, count 0 2006.285.17:23:02.39#ibcon#about to read 6, iclass 37, count 0 2006.285.17:23:02.39#ibcon#read 6, iclass 37, count 0 2006.285.17:23:02.39#ibcon#end of sib2, iclass 37, count 0 2006.285.17:23:02.39#ibcon#*after write, iclass 37, count 0 2006.285.17:23:02.39#ibcon#*before return 0, iclass 37, count 0 2006.285.17:23:02.39#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:23:02.39#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:23:02.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.17:23:02.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.17:23:02.39$vck44/vblo=1,629.99 2006.285.17:23:02.39#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.17:23:02.39#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.17:23:02.39#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:02.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:23:02.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:23:02.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:23:02.39#ibcon#enter wrdev, iclass 39, count 0 2006.285.17:23:02.39#ibcon#first serial, iclass 39, count 0 2006.285.17:23:02.39#ibcon#enter sib2, iclass 39, count 0 2006.285.17:23:02.39#ibcon#flushed, iclass 39, count 0 2006.285.17:23:02.39#ibcon#about to write, iclass 39, count 0 2006.285.17:23:02.39#ibcon#wrote, iclass 39, count 0 2006.285.17:23:02.39#ibcon#about to read 3, iclass 39, count 0 2006.285.17:23:02.41#ibcon#read 3, iclass 39, count 0 2006.285.17:23:02.41#ibcon#about to read 4, iclass 39, count 0 2006.285.17:23:02.41#ibcon#read 4, iclass 39, count 0 2006.285.17:23:02.41#ibcon#about to read 5, iclass 39, count 0 2006.285.17:23:02.41#ibcon#read 5, iclass 39, count 0 2006.285.17:23:02.41#ibcon#about to read 6, iclass 39, count 0 2006.285.17:23:02.41#ibcon#read 6, iclass 39, count 0 2006.285.17:23:02.41#ibcon#end of sib2, iclass 39, count 0 2006.285.17:23:02.41#ibcon#*mode == 0, iclass 39, count 0 2006.285.17:23:02.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.17:23:02.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.17:23:02.41#ibcon#*before write, iclass 39, count 0 2006.285.17:23:02.41#ibcon#enter sib2, iclass 39, count 0 2006.285.17:23:02.41#ibcon#flushed, iclass 39, count 0 2006.285.17:23:02.41#ibcon#about to write, iclass 39, count 0 2006.285.17:23:02.41#ibcon#wrote, iclass 39, count 0 2006.285.17:23:02.41#ibcon#about to read 3, iclass 39, count 0 2006.285.17:23:02.45#ibcon#read 3, iclass 39, count 0 2006.285.17:23:02.45#ibcon#about to read 4, iclass 39, count 0 2006.285.17:23:02.45#ibcon#read 4, iclass 39, count 0 2006.285.17:23:02.45#ibcon#about to read 5, iclass 39, count 0 2006.285.17:23:02.45#ibcon#read 5, iclass 39, count 0 2006.285.17:23:02.45#ibcon#about to read 6, iclass 39, count 0 2006.285.17:23:02.45#ibcon#read 6, iclass 39, count 0 2006.285.17:23:02.45#ibcon#end of sib2, iclass 39, count 0 2006.285.17:23:02.45#ibcon#*after write, iclass 39, count 0 2006.285.17:23:02.45#ibcon#*before return 0, iclass 39, count 0 2006.285.17:23:02.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:23:02.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:23:02.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.17:23:02.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.17:23:02.45$vck44/vb=1,4 2006.285.17:23:02.45#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.17:23:02.45#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.17:23:02.45#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:02.45#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:23:02.45#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:23:02.45#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:23:02.45#ibcon#enter wrdev, iclass 4, count 2 2006.285.17:23:02.45#ibcon#first serial, iclass 4, count 2 2006.285.17:23:02.45#ibcon#enter sib2, iclass 4, count 2 2006.285.17:23:02.45#ibcon#flushed, iclass 4, count 2 2006.285.17:23:02.45#ibcon#about to write, iclass 4, count 2 2006.285.17:23:02.45#ibcon#wrote, iclass 4, count 2 2006.285.17:23:02.45#ibcon#about to read 3, iclass 4, count 2 2006.285.17:23:02.47#ibcon#read 3, iclass 4, count 2 2006.285.17:23:02.47#ibcon#about to read 4, iclass 4, count 2 2006.285.17:23:02.47#ibcon#read 4, iclass 4, count 2 2006.285.17:23:02.47#ibcon#about to read 5, iclass 4, count 2 2006.285.17:23:02.47#ibcon#read 5, iclass 4, count 2 2006.285.17:23:02.47#ibcon#about to read 6, iclass 4, count 2 2006.285.17:23:02.47#ibcon#read 6, iclass 4, count 2 2006.285.17:23:02.47#ibcon#end of sib2, iclass 4, count 2 2006.285.17:23:02.47#ibcon#*mode == 0, iclass 4, count 2 2006.285.17:23:02.47#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.17:23:02.47#ibcon#[27=AT01-04\r\n] 2006.285.17:23:02.47#ibcon#*before write, iclass 4, count 2 2006.285.17:23:02.47#ibcon#enter sib2, iclass 4, count 2 2006.285.17:23:02.47#ibcon#flushed, iclass 4, count 2 2006.285.17:23:02.47#ibcon#about to write, iclass 4, count 2 2006.285.17:23:02.47#ibcon#wrote, iclass 4, count 2 2006.285.17:23:02.47#ibcon#about to read 3, iclass 4, count 2 2006.285.17:23:02.47#abcon#<5=/12 0.3 1.2 16.93 981014.8\r\n> 2006.285.17:23:02.49#abcon#{5=INTERFACE CLEAR} 2006.285.17:23:02.50#ibcon#read 3, iclass 4, count 2 2006.285.17:23:02.50#ibcon#about to read 4, iclass 4, count 2 2006.285.17:23:02.50#ibcon#read 4, iclass 4, count 2 2006.285.17:23:02.50#ibcon#about to read 5, iclass 4, count 2 2006.285.17:23:02.50#ibcon#read 5, iclass 4, count 2 2006.285.17:23:02.50#ibcon#about to read 6, iclass 4, count 2 2006.285.17:23:02.50#ibcon#read 6, iclass 4, count 2 2006.285.17:23:02.50#ibcon#end of sib2, iclass 4, count 2 2006.285.17:23:02.50#ibcon#*after write, iclass 4, count 2 2006.285.17:23:02.50#ibcon#*before return 0, iclass 4, count 2 2006.285.17:23:02.50#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:23:02.50#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:23:02.50#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.17:23:02.50#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:02.50#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:23:02.55#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:23:02.62#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:23:02.62#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:23:02.62#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:23:02.62#ibcon#first serial, iclass 4, count 0 2006.285.17:23:02.62#ibcon#enter sib2, iclass 4, count 0 2006.285.17:23:02.62#ibcon#flushed, iclass 4, count 0 2006.285.17:23:02.62#ibcon#about to write, iclass 4, count 0 2006.285.17:23:02.62#ibcon#wrote, iclass 4, count 0 2006.285.17:23:02.62#ibcon#about to read 3, iclass 4, count 0 2006.285.17:23:02.64#ibcon#read 3, iclass 4, count 0 2006.285.17:23:02.64#ibcon#about to read 4, iclass 4, count 0 2006.285.17:23:02.64#ibcon#read 4, iclass 4, count 0 2006.285.17:23:02.64#ibcon#about to read 5, iclass 4, count 0 2006.285.17:23:02.64#ibcon#read 5, iclass 4, count 0 2006.285.17:23:02.64#ibcon#about to read 6, iclass 4, count 0 2006.285.17:23:02.64#ibcon#read 6, iclass 4, count 0 2006.285.17:23:02.64#ibcon#end of sib2, iclass 4, count 0 2006.285.17:23:02.64#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:23:02.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:23:02.64#ibcon#[27=USB\r\n] 2006.285.17:23:02.64#ibcon#*before write, iclass 4, count 0 2006.285.17:23:02.64#ibcon#enter sib2, iclass 4, count 0 2006.285.17:23:02.64#ibcon#flushed, iclass 4, count 0 2006.285.17:23:02.64#ibcon#about to write, iclass 4, count 0 2006.285.17:23:02.64#ibcon#wrote, iclass 4, count 0 2006.285.17:23:02.64#ibcon#about to read 3, iclass 4, count 0 2006.285.17:23:02.67#ibcon#read 3, iclass 4, count 0 2006.285.17:23:02.67#ibcon#about to read 4, iclass 4, count 0 2006.285.17:23:02.67#ibcon#read 4, iclass 4, count 0 2006.285.17:23:02.67#ibcon#about to read 5, iclass 4, count 0 2006.285.17:23:02.67#ibcon#read 5, iclass 4, count 0 2006.285.17:23:02.67#ibcon#about to read 6, iclass 4, count 0 2006.285.17:23:02.67#ibcon#read 6, iclass 4, count 0 2006.285.17:23:02.67#ibcon#end of sib2, iclass 4, count 0 2006.285.17:23:02.67#ibcon#*after write, iclass 4, count 0 2006.285.17:23:02.67#ibcon#*before return 0, iclass 4, count 0 2006.285.17:23:02.67#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:23:02.67#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:23:02.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:23:02.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:23:02.67$vck44/vblo=2,634.99 2006.285.17:23:02.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.17:23:02.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.17:23:02.67#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:02.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:23:02.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:23:02.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:23:02.67#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:23:02.67#ibcon#first serial, iclass 11, count 0 2006.285.17:23:02.67#ibcon#enter sib2, iclass 11, count 0 2006.285.17:23:02.67#ibcon#flushed, iclass 11, count 0 2006.285.17:23:02.67#ibcon#about to write, iclass 11, count 0 2006.285.17:23:02.67#ibcon#wrote, iclass 11, count 0 2006.285.17:23:02.67#ibcon#about to read 3, iclass 11, count 0 2006.285.17:23:02.69#ibcon#read 3, iclass 11, count 0 2006.285.17:23:02.89#ibcon#about to read 4, iclass 11, count 0 2006.285.17:23:02.89#ibcon#read 4, iclass 11, count 0 2006.285.17:23:02.89#ibcon#about to read 5, iclass 11, count 0 2006.285.17:23:02.89#ibcon#read 5, iclass 11, count 0 2006.285.17:23:02.89#ibcon#about to read 6, iclass 11, count 0 2006.285.17:23:02.89#ibcon#read 6, iclass 11, count 0 2006.285.17:23:02.89#ibcon#end of sib2, iclass 11, count 0 2006.285.17:23:02.89#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:23:02.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:23:02.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.17:23:02.89#ibcon#*before write, iclass 11, count 0 2006.285.17:23:02.89#ibcon#enter sib2, iclass 11, count 0 2006.285.17:23:02.89#ibcon#flushed, iclass 11, count 0 2006.285.17:23:02.89#ibcon#about to write, iclass 11, count 0 2006.285.17:23:02.89#ibcon#wrote, iclass 11, count 0 2006.285.17:23:02.89#ibcon#about to read 3, iclass 11, count 0 2006.285.17:23:02.93#ibcon#read 3, iclass 11, count 0 2006.285.17:23:02.93#ibcon#about to read 4, iclass 11, count 0 2006.285.17:23:02.93#ibcon#read 4, iclass 11, count 0 2006.285.17:23:02.93#ibcon#about to read 5, iclass 11, count 0 2006.285.17:23:02.93#ibcon#read 5, iclass 11, count 0 2006.285.17:23:02.93#ibcon#about to read 6, iclass 11, count 0 2006.285.17:23:02.93#ibcon#read 6, iclass 11, count 0 2006.285.17:23:02.93#ibcon#end of sib2, iclass 11, count 0 2006.285.17:23:02.93#ibcon#*after write, iclass 11, count 0 2006.285.17:23:02.93#ibcon#*before return 0, iclass 11, count 0 2006.285.17:23:02.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:23:02.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:23:02.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:23:02.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:23:02.93$vck44/vb=2,5 2006.285.17:23:02.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.17:23:02.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.17:23:02.93#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:02.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:23:02.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:23:02.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:23:02.93#ibcon#enter wrdev, iclass 13, count 2 2006.285.17:23:02.93#ibcon#first serial, iclass 13, count 2 2006.285.17:23:02.93#ibcon#enter sib2, iclass 13, count 2 2006.285.17:23:02.93#ibcon#flushed, iclass 13, count 2 2006.285.17:23:02.93#ibcon#about to write, iclass 13, count 2 2006.285.17:23:02.93#ibcon#wrote, iclass 13, count 2 2006.285.17:23:02.93#ibcon#about to read 3, iclass 13, count 2 2006.285.17:23:02.95#ibcon#read 3, iclass 13, count 2 2006.285.17:23:02.95#ibcon#about to read 4, iclass 13, count 2 2006.285.17:23:02.95#ibcon#read 4, iclass 13, count 2 2006.285.17:23:02.95#ibcon#about to read 5, iclass 13, count 2 2006.285.17:23:02.95#ibcon#read 5, iclass 13, count 2 2006.285.17:23:02.95#ibcon#about to read 6, iclass 13, count 2 2006.285.17:23:02.95#ibcon#read 6, iclass 13, count 2 2006.285.17:23:02.95#ibcon#end of sib2, iclass 13, count 2 2006.285.17:23:02.95#ibcon#*mode == 0, iclass 13, count 2 2006.285.17:23:02.95#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.17:23:02.95#ibcon#[27=AT02-05\r\n] 2006.285.17:23:02.95#ibcon#*before write, iclass 13, count 2 2006.285.17:23:02.95#ibcon#enter sib2, iclass 13, count 2 2006.285.17:23:02.95#ibcon#flushed, iclass 13, count 2 2006.285.17:23:02.95#ibcon#about to write, iclass 13, count 2 2006.285.17:23:02.95#ibcon#wrote, iclass 13, count 2 2006.285.17:23:02.95#ibcon#about to read 3, iclass 13, count 2 2006.285.17:23:02.98#ibcon#read 3, iclass 13, count 2 2006.285.17:23:02.98#ibcon#about to read 4, iclass 13, count 2 2006.285.17:23:02.98#ibcon#read 4, iclass 13, count 2 2006.285.17:23:02.98#ibcon#about to read 5, iclass 13, count 2 2006.285.17:23:02.98#ibcon#read 5, iclass 13, count 2 2006.285.17:23:02.98#ibcon#about to read 6, iclass 13, count 2 2006.285.17:23:02.98#ibcon#read 6, iclass 13, count 2 2006.285.17:23:02.98#ibcon#end of sib2, iclass 13, count 2 2006.285.17:23:02.98#ibcon#*after write, iclass 13, count 2 2006.285.17:23:02.98#ibcon#*before return 0, iclass 13, count 2 2006.285.17:23:02.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:23:02.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:23:02.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.17:23:02.98#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:02.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:23:03.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:23:03.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:23:03.10#ibcon#enter wrdev, iclass 13, count 0 2006.285.17:23:03.10#ibcon#first serial, iclass 13, count 0 2006.285.17:23:03.10#ibcon#enter sib2, iclass 13, count 0 2006.285.17:23:03.10#ibcon#flushed, iclass 13, count 0 2006.285.17:23:03.10#ibcon#about to write, iclass 13, count 0 2006.285.17:23:03.10#ibcon#wrote, iclass 13, count 0 2006.285.17:23:03.10#ibcon#about to read 3, iclass 13, count 0 2006.285.17:23:03.12#ibcon#read 3, iclass 13, count 0 2006.285.17:23:03.12#ibcon#about to read 4, iclass 13, count 0 2006.285.17:23:03.12#ibcon#read 4, iclass 13, count 0 2006.285.17:23:03.12#ibcon#about to read 5, iclass 13, count 0 2006.285.17:23:03.12#ibcon#read 5, iclass 13, count 0 2006.285.17:23:03.12#ibcon#about to read 6, iclass 13, count 0 2006.285.17:23:03.12#ibcon#read 6, iclass 13, count 0 2006.285.17:23:03.12#ibcon#end of sib2, iclass 13, count 0 2006.285.17:23:03.12#ibcon#*mode == 0, iclass 13, count 0 2006.285.17:23:03.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.17:23:03.12#ibcon#[27=USB\r\n] 2006.285.17:23:03.12#ibcon#*before write, iclass 13, count 0 2006.285.17:23:03.12#ibcon#enter sib2, iclass 13, count 0 2006.285.17:23:03.12#ibcon#flushed, iclass 13, count 0 2006.285.17:23:03.12#ibcon#about to write, iclass 13, count 0 2006.285.17:23:03.12#ibcon#wrote, iclass 13, count 0 2006.285.17:23:03.12#ibcon#about to read 3, iclass 13, count 0 2006.285.17:23:03.15#ibcon#read 3, iclass 13, count 0 2006.285.17:23:03.15#ibcon#about to read 4, iclass 13, count 0 2006.285.17:23:03.15#ibcon#read 4, iclass 13, count 0 2006.285.17:23:03.15#ibcon#about to read 5, iclass 13, count 0 2006.285.17:23:03.15#ibcon#read 5, iclass 13, count 0 2006.285.17:23:03.15#ibcon#about to read 6, iclass 13, count 0 2006.285.17:23:03.15#ibcon#read 6, iclass 13, count 0 2006.285.17:23:03.15#ibcon#end of sib2, iclass 13, count 0 2006.285.17:23:03.15#ibcon#*after write, iclass 13, count 0 2006.285.17:23:03.15#ibcon#*before return 0, iclass 13, count 0 2006.285.17:23:03.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:23:03.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:23:03.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.17:23:03.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.17:23:03.15$vck44/vblo=3,649.99 2006.285.17:23:03.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.17:23:03.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.17:23:03.15#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:03.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:23:03.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:23:03.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:23:03.15#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:23:03.15#ibcon#first serial, iclass 15, count 0 2006.285.17:23:03.15#ibcon#enter sib2, iclass 15, count 0 2006.285.17:23:03.15#ibcon#flushed, iclass 15, count 0 2006.285.17:23:03.15#ibcon#about to write, iclass 15, count 0 2006.285.17:23:03.15#ibcon#wrote, iclass 15, count 0 2006.285.17:23:03.15#ibcon#about to read 3, iclass 15, count 0 2006.285.17:23:03.17#ibcon#read 3, iclass 15, count 0 2006.285.17:23:03.17#ibcon#about to read 4, iclass 15, count 0 2006.285.17:23:03.17#ibcon#read 4, iclass 15, count 0 2006.285.17:23:03.17#ibcon#about to read 5, iclass 15, count 0 2006.285.17:23:03.17#ibcon#read 5, iclass 15, count 0 2006.285.17:23:03.17#ibcon#about to read 6, iclass 15, count 0 2006.285.17:23:03.17#ibcon#read 6, iclass 15, count 0 2006.285.17:23:03.17#ibcon#end of sib2, iclass 15, count 0 2006.285.17:23:03.17#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:23:03.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:23:03.17#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.17:23:03.17#ibcon#*before write, iclass 15, count 0 2006.285.17:23:03.17#ibcon#enter sib2, iclass 15, count 0 2006.285.17:23:03.17#ibcon#flushed, iclass 15, count 0 2006.285.17:23:03.17#ibcon#about to write, iclass 15, count 0 2006.285.17:23:03.17#ibcon#wrote, iclass 15, count 0 2006.285.17:23:03.17#ibcon#about to read 3, iclass 15, count 0 2006.285.17:23:03.21#ibcon#read 3, iclass 15, count 0 2006.285.17:23:03.21#ibcon#about to read 4, iclass 15, count 0 2006.285.17:23:03.21#ibcon#read 4, iclass 15, count 0 2006.285.17:23:03.21#ibcon#about to read 5, iclass 15, count 0 2006.285.17:23:03.21#ibcon#read 5, iclass 15, count 0 2006.285.17:23:03.21#ibcon#about to read 6, iclass 15, count 0 2006.285.17:23:03.21#ibcon#read 6, iclass 15, count 0 2006.285.17:23:03.21#ibcon#end of sib2, iclass 15, count 0 2006.285.17:23:03.21#ibcon#*after write, iclass 15, count 0 2006.285.17:23:03.21#ibcon#*before return 0, iclass 15, count 0 2006.285.17:23:03.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:23:03.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:23:03.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:23:03.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:23:03.21$vck44/vb=3,4 2006.285.17:23:03.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.17:23:03.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.17:23:03.21#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:03.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:23:03.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:23:03.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:23:03.27#ibcon#enter wrdev, iclass 17, count 2 2006.285.17:23:03.27#ibcon#first serial, iclass 17, count 2 2006.285.17:23:03.27#ibcon#enter sib2, iclass 17, count 2 2006.285.17:23:03.27#ibcon#flushed, iclass 17, count 2 2006.285.17:23:03.27#ibcon#about to write, iclass 17, count 2 2006.285.17:23:03.27#ibcon#wrote, iclass 17, count 2 2006.285.17:23:03.27#ibcon#about to read 3, iclass 17, count 2 2006.285.17:23:03.29#ibcon#read 3, iclass 17, count 2 2006.285.17:23:03.29#ibcon#about to read 4, iclass 17, count 2 2006.285.17:23:03.29#ibcon#read 4, iclass 17, count 2 2006.285.17:23:03.29#ibcon#about to read 5, iclass 17, count 2 2006.285.17:23:03.29#ibcon#read 5, iclass 17, count 2 2006.285.17:23:03.29#ibcon#about to read 6, iclass 17, count 2 2006.285.17:23:03.29#ibcon#read 6, iclass 17, count 2 2006.285.17:23:03.29#ibcon#end of sib2, iclass 17, count 2 2006.285.17:23:03.29#ibcon#*mode == 0, iclass 17, count 2 2006.285.17:23:03.29#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.17:23:03.29#ibcon#[27=AT03-04\r\n] 2006.285.17:23:03.29#ibcon#*before write, iclass 17, count 2 2006.285.17:23:03.29#ibcon#enter sib2, iclass 17, count 2 2006.285.17:23:03.29#ibcon#flushed, iclass 17, count 2 2006.285.17:23:03.29#ibcon#about to write, iclass 17, count 2 2006.285.17:23:03.29#ibcon#wrote, iclass 17, count 2 2006.285.17:23:03.29#ibcon#about to read 3, iclass 17, count 2 2006.285.17:23:03.32#ibcon#read 3, iclass 17, count 2 2006.285.17:23:03.32#ibcon#about to read 4, iclass 17, count 2 2006.285.17:23:03.32#ibcon#read 4, iclass 17, count 2 2006.285.17:23:03.32#ibcon#about to read 5, iclass 17, count 2 2006.285.17:23:03.32#ibcon#read 5, iclass 17, count 2 2006.285.17:23:03.32#ibcon#about to read 6, iclass 17, count 2 2006.285.17:23:03.32#ibcon#read 6, iclass 17, count 2 2006.285.17:23:03.32#ibcon#end of sib2, iclass 17, count 2 2006.285.17:23:03.32#ibcon#*after write, iclass 17, count 2 2006.285.17:23:03.32#ibcon#*before return 0, iclass 17, count 2 2006.285.17:23:03.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:23:03.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:23:03.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.17:23:03.32#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:03.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:23:03.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:23:03.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:23:03.44#ibcon#enter wrdev, iclass 17, count 0 2006.285.17:23:03.44#ibcon#first serial, iclass 17, count 0 2006.285.17:23:03.44#ibcon#enter sib2, iclass 17, count 0 2006.285.17:23:03.44#ibcon#flushed, iclass 17, count 0 2006.285.17:23:03.44#ibcon#about to write, iclass 17, count 0 2006.285.17:23:03.44#ibcon#wrote, iclass 17, count 0 2006.285.17:23:03.44#ibcon#about to read 3, iclass 17, count 0 2006.285.17:23:03.46#ibcon#read 3, iclass 17, count 0 2006.285.17:23:03.46#ibcon#about to read 4, iclass 17, count 0 2006.285.17:23:03.46#ibcon#read 4, iclass 17, count 0 2006.285.17:23:03.46#ibcon#about to read 5, iclass 17, count 0 2006.285.17:23:03.46#ibcon#read 5, iclass 17, count 0 2006.285.17:23:03.46#ibcon#about to read 6, iclass 17, count 0 2006.285.17:23:03.46#ibcon#read 6, iclass 17, count 0 2006.285.17:23:03.46#ibcon#end of sib2, iclass 17, count 0 2006.285.17:23:03.46#ibcon#*mode == 0, iclass 17, count 0 2006.285.17:23:03.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.17:23:03.46#ibcon#[27=USB\r\n] 2006.285.17:23:03.46#ibcon#*before write, iclass 17, count 0 2006.285.17:23:03.46#ibcon#enter sib2, iclass 17, count 0 2006.285.17:23:03.46#ibcon#flushed, iclass 17, count 0 2006.285.17:23:03.46#ibcon#about to write, iclass 17, count 0 2006.285.17:23:03.46#ibcon#wrote, iclass 17, count 0 2006.285.17:23:03.46#ibcon#about to read 3, iclass 17, count 0 2006.285.17:23:03.49#ibcon#read 3, iclass 17, count 0 2006.285.17:23:03.49#ibcon#about to read 4, iclass 17, count 0 2006.285.17:23:03.49#ibcon#read 4, iclass 17, count 0 2006.285.17:23:03.49#ibcon#about to read 5, iclass 17, count 0 2006.285.17:23:03.49#ibcon#read 5, iclass 17, count 0 2006.285.17:23:03.49#ibcon#about to read 6, iclass 17, count 0 2006.285.17:23:03.49#ibcon#read 6, iclass 17, count 0 2006.285.17:23:03.49#ibcon#end of sib2, iclass 17, count 0 2006.285.17:23:03.49#ibcon#*after write, iclass 17, count 0 2006.285.17:23:03.49#ibcon#*before return 0, iclass 17, count 0 2006.285.17:23:03.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:23:03.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:23:03.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.17:23:03.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.17:23:03.49$vck44/vblo=4,679.99 2006.285.17:23:03.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.17:23:03.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.17:23:03.49#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:03.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:23:03.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:23:03.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:23:03.49#ibcon#enter wrdev, iclass 19, count 0 2006.285.17:23:03.49#ibcon#first serial, iclass 19, count 0 2006.285.17:23:03.49#ibcon#enter sib2, iclass 19, count 0 2006.285.17:23:03.49#ibcon#flushed, iclass 19, count 0 2006.285.17:23:03.49#ibcon#about to write, iclass 19, count 0 2006.285.17:23:03.49#ibcon#wrote, iclass 19, count 0 2006.285.17:23:03.49#ibcon#about to read 3, iclass 19, count 0 2006.285.17:23:03.51#ibcon#read 3, iclass 19, count 0 2006.285.17:23:03.51#ibcon#about to read 4, iclass 19, count 0 2006.285.17:23:03.51#ibcon#read 4, iclass 19, count 0 2006.285.17:23:03.51#ibcon#about to read 5, iclass 19, count 0 2006.285.17:23:03.51#ibcon#read 5, iclass 19, count 0 2006.285.17:23:03.51#ibcon#about to read 6, iclass 19, count 0 2006.285.17:23:03.51#ibcon#read 6, iclass 19, count 0 2006.285.17:23:03.51#ibcon#end of sib2, iclass 19, count 0 2006.285.17:23:03.51#ibcon#*mode == 0, iclass 19, count 0 2006.285.17:23:03.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.17:23:03.51#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.17:23:03.51#ibcon#*before write, iclass 19, count 0 2006.285.17:23:03.51#ibcon#enter sib2, iclass 19, count 0 2006.285.17:23:03.51#ibcon#flushed, iclass 19, count 0 2006.285.17:23:03.51#ibcon#about to write, iclass 19, count 0 2006.285.17:23:03.51#ibcon#wrote, iclass 19, count 0 2006.285.17:23:03.51#ibcon#about to read 3, iclass 19, count 0 2006.285.17:23:03.55#ibcon#read 3, iclass 19, count 0 2006.285.17:23:03.55#ibcon#about to read 4, iclass 19, count 0 2006.285.17:23:03.55#ibcon#read 4, iclass 19, count 0 2006.285.17:23:03.55#ibcon#about to read 5, iclass 19, count 0 2006.285.17:23:03.55#ibcon#read 5, iclass 19, count 0 2006.285.17:23:03.55#ibcon#about to read 6, iclass 19, count 0 2006.285.17:23:03.55#ibcon#read 6, iclass 19, count 0 2006.285.17:23:03.55#ibcon#end of sib2, iclass 19, count 0 2006.285.17:23:03.55#ibcon#*after write, iclass 19, count 0 2006.285.17:23:03.55#ibcon#*before return 0, iclass 19, count 0 2006.285.17:23:03.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:23:03.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:23:03.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.17:23:03.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.17:23:03.55$vck44/vb=4,5 2006.285.17:23:03.55#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.17:23:03.55#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.17:23:03.55#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:03.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:23:03.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:23:03.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:23:03.61#ibcon#enter wrdev, iclass 21, count 2 2006.285.17:23:03.61#ibcon#first serial, iclass 21, count 2 2006.285.17:23:03.61#ibcon#enter sib2, iclass 21, count 2 2006.285.17:23:03.61#ibcon#flushed, iclass 21, count 2 2006.285.17:23:03.61#ibcon#about to write, iclass 21, count 2 2006.285.17:23:03.61#ibcon#wrote, iclass 21, count 2 2006.285.17:23:03.61#ibcon#about to read 3, iclass 21, count 2 2006.285.17:23:03.63#ibcon#read 3, iclass 21, count 2 2006.285.17:23:03.63#ibcon#about to read 4, iclass 21, count 2 2006.285.17:23:03.63#ibcon#read 4, iclass 21, count 2 2006.285.17:23:03.63#ibcon#about to read 5, iclass 21, count 2 2006.285.17:23:03.63#ibcon#read 5, iclass 21, count 2 2006.285.17:23:03.63#ibcon#about to read 6, iclass 21, count 2 2006.285.17:23:03.63#ibcon#read 6, iclass 21, count 2 2006.285.17:23:03.63#ibcon#end of sib2, iclass 21, count 2 2006.285.17:23:03.63#ibcon#*mode == 0, iclass 21, count 2 2006.285.17:23:03.63#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.17:23:03.63#ibcon#[27=AT04-05\r\n] 2006.285.17:23:03.63#ibcon#*before write, iclass 21, count 2 2006.285.17:23:03.63#ibcon#enter sib2, iclass 21, count 2 2006.285.17:23:03.63#ibcon#flushed, iclass 21, count 2 2006.285.17:23:03.63#ibcon#about to write, iclass 21, count 2 2006.285.17:23:03.63#ibcon#wrote, iclass 21, count 2 2006.285.17:23:03.63#ibcon#about to read 3, iclass 21, count 2 2006.285.17:23:03.66#ibcon#read 3, iclass 21, count 2 2006.285.17:23:03.66#ibcon#about to read 4, iclass 21, count 2 2006.285.17:23:03.66#ibcon#read 4, iclass 21, count 2 2006.285.17:23:03.66#ibcon#about to read 5, iclass 21, count 2 2006.285.17:23:03.66#ibcon#read 5, iclass 21, count 2 2006.285.17:23:03.66#ibcon#about to read 6, iclass 21, count 2 2006.285.17:23:03.66#ibcon#read 6, iclass 21, count 2 2006.285.17:23:03.66#ibcon#end of sib2, iclass 21, count 2 2006.285.17:23:03.66#ibcon#*after write, iclass 21, count 2 2006.285.17:23:03.66#ibcon#*before return 0, iclass 21, count 2 2006.285.17:23:03.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:23:03.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:23:03.66#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.17:23:03.66#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:03.66#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:23:03.78#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:23:03.78#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:23:03.78#ibcon#enter wrdev, iclass 21, count 0 2006.285.17:23:03.78#ibcon#first serial, iclass 21, count 0 2006.285.17:23:03.78#ibcon#enter sib2, iclass 21, count 0 2006.285.17:23:03.78#ibcon#flushed, iclass 21, count 0 2006.285.17:23:03.78#ibcon#about to write, iclass 21, count 0 2006.285.17:23:03.78#ibcon#wrote, iclass 21, count 0 2006.285.17:23:03.78#ibcon#about to read 3, iclass 21, count 0 2006.285.17:23:03.80#ibcon#read 3, iclass 21, count 0 2006.285.17:23:03.80#ibcon#about to read 4, iclass 21, count 0 2006.285.17:23:03.80#ibcon#read 4, iclass 21, count 0 2006.285.17:23:03.80#ibcon#about to read 5, iclass 21, count 0 2006.285.17:23:03.80#ibcon#read 5, iclass 21, count 0 2006.285.17:23:03.80#ibcon#about to read 6, iclass 21, count 0 2006.285.17:23:03.80#ibcon#read 6, iclass 21, count 0 2006.285.17:23:03.80#ibcon#end of sib2, iclass 21, count 0 2006.285.17:23:03.80#ibcon#*mode == 0, iclass 21, count 0 2006.285.17:23:03.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.17:23:03.80#ibcon#[27=USB\r\n] 2006.285.17:23:03.80#ibcon#*before write, iclass 21, count 0 2006.285.17:23:03.80#ibcon#enter sib2, iclass 21, count 0 2006.285.17:23:03.80#ibcon#flushed, iclass 21, count 0 2006.285.17:23:03.80#ibcon#about to write, iclass 21, count 0 2006.285.17:23:03.80#ibcon#wrote, iclass 21, count 0 2006.285.17:23:03.80#ibcon#about to read 3, iclass 21, count 0 2006.285.17:23:03.83#ibcon#read 3, iclass 21, count 0 2006.285.17:23:03.91#ibcon#about to read 4, iclass 21, count 0 2006.285.17:23:03.91#ibcon#read 4, iclass 21, count 0 2006.285.17:23:03.91#ibcon#about to read 5, iclass 21, count 0 2006.285.17:23:03.91#ibcon#read 5, iclass 21, count 0 2006.285.17:23:03.91#ibcon#about to read 6, iclass 21, count 0 2006.285.17:23:03.91#ibcon#read 6, iclass 21, count 0 2006.285.17:23:03.91#ibcon#end of sib2, iclass 21, count 0 2006.285.17:23:03.91#ibcon#*after write, iclass 21, count 0 2006.285.17:23:03.91#ibcon#*before return 0, iclass 21, count 0 2006.285.17:23:03.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:23:03.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:23:03.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.17:23:03.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.17:23:03.91$vck44/vblo=5,709.99 2006.285.17:23:03.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.17:23:03.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.17:23:03.91#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:03.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:23:03.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:23:03.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:23:03.91#ibcon#enter wrdev, iclass 23, count 0 2006.285.17:23:03.91#ibcon#first serial, iclass 23, count 0 2006.285.17:23:03.91#ibcon#enter sib2, iclass 23, count 0 2006.285.17:23:03.91#ibcon#flushed, iclass 23, count 0 2006.285.17:23:03.91#ibcon#about to write, iclass 23, count 0 2006.285.17:23:03.91#ibcon#wrote, iclass 23, count 0 2006.285.17:23:03.91#ibcon#about to read 3, iclass 23, count 0 2006.285.17:23:03.92#ibcon#read 3, iclass 23, count 0 2006.285.17:23:03.92#ibcon#about to read 4, iclass 23, count 0 2006.285.17:23:03.92#ibcon#read 4, iclass 23, count 0 2006.285.17:23:03.92#ibcon#about to read 5, iclass 23, count 0 2006.285.17:23:03.92#ibcon#read 5, iclass 23, count 0 2006.285.17:23:03.92#ibcon#about to read 6, iclass 23, count 0 2006.285.17:23:03.92#ibcon#read 6, iclass 23, count 0 2006.285.17:23:03.92#ibcon#end of sib2, iclass 23, count 0 2006.285.17:23:03.92#ibcon#*mode == 0, iclass 23, count 0 2006.285.17:23:03.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.17:23:03.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.17:23:03.92#ibcon#*before write, iclass 23, count 0 2006.285.17:23:03.92#ibcon#enter sib2, iclass 23, count 0 2006.285.17:23:03.92#ibcon#flushed, iclass 23, count 0 2006.285.17:23:03.92#ibcon#about to write, iclass 23, count 0 2006.285.17:23:03.92#ibcon#wrote, iclass 23, count 0 2006.285.17:23:03.92#ibcon#about to read 3, iclass 23, count 0 2006.285.17:23:03.96#ibcon#read 3, iclass 23, count 0 2006.285.17:23:03.96#ibcon#about to read 4, iclass 23, count 0 2006.285.17:23:03.96#ibcon#read 4, iclass 23, count 0 2006.285.17:23:03.96#ibcon#about to read 5, iclass 23, count 0 2006.285.17:23:03.96#ibcon#read 5, iclass 23, count 0 2006.285.17:23:03.96#ibcon#about to read 6, iclass 23, count 0 2006.285.17:23:03.96#ibcon#read 6, iclass 23, count 0 2006.285.17:23:03.96#ibcon#end of sib2, iclass 23, count 0 2006.285.17:23:03.96#ibcon#*after write, iclass 23, count 0 2006.285.17:23:03.96#ibcon#*before return 0, iclass 23, count 0 2006.285.17:23:03.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:23:03.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:23:03.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.17:23:03.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.17:23:03.96$vck44/vb=5,4 2006.285.17:23:03.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.17:23:03.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.17:23:03.96#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:03.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:23:04.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:23:04.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:23:04.03#ibcon#enter wrdev, iclass 25, count 2 2006.285.17:23:04.03#ibcon#first serial, iclass 25, count 2 2006.285.17:23:04.03#ibcon#enter sib2, iclass 25, count 2 2006.285.17:23:04.03#ibcon#flushed, iclass 25, count 2 2006.285.17:23:04.03#ibcon#about to write, iclass 25, count 2 2006.285.17:23:04.03#ibcon#wrote, iclass 25, count 2 2006.285.17:23:04.03#ibcon#about to read 3, iclass 25, count 2 2006.285.17:23:04.05#ibcon#read 3, iclass 25, count 2 2006.285.17:23:04.05#ibcon#about to read 4, iclass 25, count 2 2006.285.17:23:04.05#ibcon#read 4, iclass 25, count 2 2006.285.17:23:04.05#ibcon#about to read 5, iclass 25, count 2 2006.285.17:23:04.05#ibcon#read 5, iclass 25, count 2 2006.285.17:23:04.05#ibcon#about to read 6, iclass 25, count 2 2006.285.17:23:04.05#ibcon#read 6, iclass 25, count 2 2006.285.17:23:04.05#ibcon#end of sib2, iclass 25, count 2 2006.285.17:23:04.05#ibcon#*mode == 0, iclass 25, count 2 2006.285.17:23:04.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.17:23:04.05#ibcon#[27=AT05-04\r\n] 2006.285.17:23:04.05#ibcon#*before write, iclass 25, count 2 2006.285.17:23:04.05#ibcon#enter sib2, iclass 25, count 2 2006.285.17:23:04.05#ibcon#flushed, iclass 25, count 2 2006.285.17:23:04.05#ibcon#about to write, iclass 25, count 2 2006.285.17:23:04.05#ibcon#wrote, iclass 25, count 2 2006.285.17:23:04.05#ibcon#about to read 3, iclass 25, count 2 2006.285.17:23:04.08#ibcon#read 3, iclass 25, count 2 2006.285.17:23:04.08#ibcon#about to read 4, iclass 25, count 2 2006.285.17:23:04.08#ibcon#read 4, iclass 25, count 2 2006.285.17:23:04.08#ibcon#about to read 5, iclass 25, count 2 2006.285.17:23:04.08#ibcon#read 5, iclass 25, count 2 2006.285.17:23:04.08#ibcon#about to read 6, iclass 25, count 2 2006.285.17:23:04.08#ibcon#read 6, iclass 25, count 2 2006.285.17:23:04.08#ibcon#end of sib2, iclass 25, count 2 2006.285.17:23:04.08#ibcon#*after write, iclass 25, count 2 2006.285.17:23:04.08#ibcon#*before return 0, iclass 25, count 2 2006.285.17:23:04.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:23:04.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:23:04.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.17:23:04.08#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:04.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:23:04.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:23:04.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:23:04.20#ibcon#enter wrdev, iclass 25, count 0 2006.285.17:23:04.20#ibcon#first serial, iclass 25, count 0 2006.285.17:23:04.20#ibcon#enter sib2, iclass 25, count 0 2006.285.17:23:04.20#ibcon#flushed, iclass 25, count 0 2006.285.17:23:04.20#ibcon#about to write, iclass 25, count 0 2006.285.17:23:04.20#ibcon#wrote, iclass 25, count 0 2006.285.17:23:04.20#ibcon#about to read 3, iclass 25, count 0 2006.285.17:23:04.22#ibcon#read 3, iclass 25, count 0 2006.285.17:23:04.22#ibcon#about to read 4, iclass 25, count 0 2006.285.17:23:04.22#ibcon#read 4, iclass 25, count 0 2006.285.17:23:04.22#ibcon#about to read 5, iclass 25, count 0 2006.285.17:23:04.22#ibcon#read 5, iclass 25, count 0 2006.285.17:23:04.22#ibcon#about to read 6, iclass 25, count 0 2006.285.17:23:04.22#ibcon#read 6, iclass 25, count 0 2006.285.17:23:04.22#ibcon#end of sib2, iclass 25, count 0 2006.285.17:23:04.22#ibcon#*mode == 0, iclass 25, count 0 2006.285.17:23:04.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.17:23:04.22#ibcon#[27=USB\r\n] 2006.285.17:23:04.22#ibcon#*before write, iclass 25, count 0 2006.285.17:23:04.22#ibcon#enter sib2, iclass 25, count 0 2006.285.17:23:04.22#ibcon#flushed, iclass 25, count 0 2006.285.17:23:04.22#ibcon#about to write, iclass 25, count 0 2006.285.17:23:04.22#ibcon#wrote, iclass 25, count 0 2006.285.17:23:04.22#ibcon#about to read 3, iclass 25, count 0 2006.285.17:23:04.25#ibcon#read 3, iclass 25, count 0 2006.285.17:23:04.25#ibcon#about to read 4, iclass 25, count 0 2006.285.17:23:04.25#ibcon#read 4, iclass 25, count 0 2006.285.17:23:04.25#ibcon#about to read 5, iclass 25, count 0 2006.285.17:23:04.25#ibcon#read 5, iclass 25, count 0 2006.285.17:23:04.25#ibcon#about to read 6, iclass 25, count 0 2006.285.17:23:04.25#ibcon#read 6, iclass 25, count 0 2006.285.17:23:04.25#ibcon#end of sib2, iclass 25, count 0 2006.285.17:23:04.25#ibcon#*after write, iclass 25, count 0 2006.285.17:23:04.25#ibcon#*before return 0, iclass 25, count 0 2006.285.17:23:04.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:23:04.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:23:04.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.17:23:04.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.17:23:04.25$vck44/vblo=6,719.99 2006.285.17:23:04.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.17:23:04.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.17:23:04.25#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:04.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:23:04.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:23:04.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:23:04.25#ibcon#enter wrdev, iclass 27, count 0 2006.285.17:23:04.25#ibcon#first serial, iclass 27, count 0 2006.285.17:23:04.25#ibcon#enter sib2, iclass 27, count 0 2006.285.17:23:04.25#ibcon#flushed, iclass 27, count 0 2006.285.17:23:04.25#ibcon#about to write, iclass 27, count 0 2006.285.17:23:04.25#ibcon#wrote, iclass 27, count 0 2006.285.17:23:04.25#ibcon#about to read 3, iclass 27, count 0 2006.285.17:23:04.27#ibcon#read 3, iclass 27, count 0 2006.285.17:23:04.27#ibcon#about to read 4, iclass 27, count 0 2006.285.17:23:04.27#ibcon#read 4, iclass 27, count 0 2006.285.17:23:04.27#ibcon#about to read 5, iclass 27, count 0 2006.285.17:23:04.27#ibcon#read 5, iclass 27, count 0 2006.285.17:23:04.27#ibcon#about to read 6, iclass 27, count 0 2006.285.17:23:04.27#ibcon#read 6, iclass 27, count 0 2006.285.17:23:04.27#ibcon#end of sib2, iclass 27, count 0 2006.285.17:23:04.27#ibcon#*mode == 0, iclass 27, count 0 2006.285.17:23:04.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.17:23:04.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.17:23:04.27#ibcon#*before write, iclass 27, count 0 2006.285.17:23:04.27#ibcon#enter sib2, iclass 27, count 0 2006.285.17:23:04.27#ibcon#flushed, iclass 27, count 0 2006.285.17:23:04.27#ibcon#about to write, iclass 27, count 0 2006.285.17:23:04.27#ibcon#wrote, iclass 27, count 0 2006.285.17:23:04.27#ibcon#about to read 3, iclass 27, count 0 2006.285.17:23:04.31#ibcon#read 3, iclass 27, count 0 2006.285.17:23:04.31#ibcon#about to read 4, iclass 27, count 0 2006.285.17:23:04.31#ibcon#read 4, iclass 27, count 0 2006.285.17:23:04.31#ibcon#about to read 5, iclass 27, count 0 2006.285.17:23:04.31#ibcon#read 5, iclass 27, count 0 2006.285.17:23:04.31#ibcon#about to read 6, iclass 27, count 0 2006.285.17:23:04.31#ibcon#read 6, iclass 27, count 0 2006.285.17:23:04.31#ibcon#end of sib2, iclass 27, count 0 2006.285.17:23:04.31#ibcon#*after write, iclass 27, count 0 2006.285.17:23:04.31#ibcon#*before return 0, iclass 27, count 0 2006.285.17:23:04.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:23:04.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:23:04.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.17:23:04.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.17:23:04.31$vck44/vb=6,3 2006.285.17:23:04.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.17:23:04.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.17:23:04.31#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:04.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:23:04.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:23:04.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:23:04.37#ibcon#enter wrdev, iclass 29, count 2 2006.285.17:23:04.37#ibcon#first serial, iclass 29, count 2 2006.285.17:23:04.37#ibcon#enter sib2, iclass 29, count 2 2006.285.17:23:04.37#ibcon#flushed, iclass 29, count 2 2006.285.17:23:04.37#ibcon#about to write, iclass 29, count 2 2006.285.17:23:04.37#ibcon#wrote, iclass 29, count 2 2006.285.17:23:04.37#ibcon#about to read 3, iclass 29, count 2 2006.285.17:23:04.39#ibcon#read 3, iclass 29, count 2 2006.285.17:23:04.39#ibcon#about to read 4, iclass 29, count 2 2006.285.17:23:04.39#ibcon#read 4, iclass 29, count 2 2006.285.17:23:04.39#ibcon#about to read 5, iclass 29, count 2 2006.285.17:23:04.39#ibcon#read 5, iclass 29, count 2 2006.285.17:23:04.39#ibcon#about to read 6, iclass 29, count 2 2006.285.17:23:04.39#ibcon#read 6, iclass 29, count 2 2006.285.17:23:04.39#ibcon#end of sib2, iclass 29, count 2 2006.285.17:23:04.39#ibcon#*mode == 0, iclass 29, count 2 2006.285.17:23:04.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.17:23:04.39#ibcon#[27=AT06-03\r\n] 2006.285.17:23:04.39#ibcon#*before write, iclass 29, count 2 2006.285.17:23:04.39#ibcon#enter sib2, iclass 29, count 2 2006.285.17:23:04.39#ibcon#flushed, iclass 29, count 2 2006.285.17:23:04.39#ibcon#about to write, iclass 29, count 2 2006.285.17:23:04.39#ibcon#wrote, iclass 29, count 2 2006.285.17:23:04.39#ibcon#about to read 3, iclass 29, count 2 2006.285.17:23:04.42#ibcon#read 3, iclass 29, count 2 2006.285.17:23:04.42#ibcon#about to read 4, iclass 29, count 2 2006.285.17:23:04.42#ibcon#read 4, iclass 29, count 2 2006.285.17:23:04.42#ibcon#about to read 5, iclass 29, count 2 2006.285.17:23:04.42#ibcon#read 5, iclass 29, count 2 2006.285.17:23:04.42#ibcon#about to read 6, iclass 29, count 2 2006.285.17:23:04.42#ibcon#read 6, iclass 29, count 2 2006.285.17:23:04.42#ibcon#end of sib2, iclass 29, count 2 2006.285.17:23:04.42#ibcon#*after write, iclass 29, count 2 2006.285.17:23:04.42#ibcon#*before return 0, iclass 29, count 2 2006.285.17:23:04.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:23:04.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:23:04.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.17:23:04.42#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:04.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:23:04.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:23:04.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:23:04.54#ibcon#enter wrdev, iclass 29, count 0 2006.285.17:23:04.54#ibcon#first serial, iclass 29, count 0 2006.285.17:23:04.54#ibcon#enter sib2, iclass 29, count 0 2006.285.17:23:04.54#ibcon#flushed, iclass 29, count 0 2006.285.17:23:04.54#ibcon#about to write, iclass 29, count 0 2006.285.17:23:04.54#ibcon#wrote, iclass 29, count 0 2006.285.17:23:04.54#ibcon#about to read 3, iclass 29, count 0 2006.285.17:23:04.56#ibcon#read 3, iclass 29, count 0 2006.285.17:23:04.56#ibcon#about to read 4, iclass 29, count 0 2006.285.17:23:04.56#ibcon#read 4, iclass 29, count 0 2006.285.17:23:04.56#ibcon#about to read 5, iclass 29, count 0 2006.285.17:23:04.56#ibcon#read 5, iclass 29, count 0 2006.285.17:23:04.56#ibcon#about to read 6, iclass 29, count 0 2006.285.17:23:04.56#ibcon#read 6, iclass 29, count 0 2006.285.17:23:04.56#ibcon#end of sib2, iclass 29, count 0 2006.285.17:23:04.56#ibcon#*mode == 0, iclass 29, count 0 2006.285.17:23:04.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.17:23:04.56#ibcon#[27=USB\r\n] 2006.285.17:23:04.56#ibcon#*before write, iclass 29, count 0 2006.285.17:23:04.56#ibcon#enter sib2, iclass 29, count 0 2006.285.17:23:04.56#ibcon#flushed, iclass 29, count 0 2006.285.17:23:04.56#ibcon#about to write, iclass 29, count 0 2006.285.17:23:04.56#ibcon#wrote, iclass 29, count 0 2006.285.17:23:04.56#ibcon#about to read 3, iclass 29, count 0 2006.285.17:23:04.59#ibcon#read 3, iclass 29, count 0 2006.285.17:23:04.59#ibcon#about to read 4, iclass 29, count 0 2006.285.17:23:04.59#ibcon#read 4, iclass 29, count 0 2006.285.17:23:04.59#ibcon#about to read 5, iclass 29, count 0 2006.285.17:23:04.59#ibcon#read 5, iclass 29, count 0 2006.285.17:23:04.59#ibcon#about to read 6, iclass 29, count 0 2006.285.17:23:04.59#ibcon#read 6, iclass 29, count 0 2006.285.17:23:04.59#ibcon#end of sib2, iclass 29, count 0 2006.285.17:23:04.59#ibcon#*after write, iclass 29, count 0 2006.285.17:23:04.59#ibcon#*before return 0, iclass 29, count 0 2006.285.17:23:04.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:23:04.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:23:04.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.17:23:04.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.17:23:04.59$vck44/vblo=7,734.99 2006.285.17:23:04.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.17:23:04.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.17:23:04.59#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:04.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:23:04.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:23:04.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:23:04.59#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:23:04.59#ibcon#first serial, iclass 31, count 0 2006.285.17:23:04.59#ibcon#enter sib2, iclass 31, count 0 2006.285.17:23:04.59#ibcon#flushed, iclass 31, count 0 2006.285.17:23:04.59#ibcon#about to write, iclass 31, count 0 2006.285.17:23:04.59#ibcon#wrote, iclass 31, count 0 2006.285.17:23:04.59#ibcon#about to read 3, iclass 31, count 0 2006.285.17:23:04.61#ibcon#read 3, iclass 31, count 0 2006.285.17:23:04.61#ibcon#about to read 4, iclass 31, count 0 2006.285.17:23:04.61#ibcon#read 4, iclass 31, count 0 2006.285.17:23:04.61#ibcon#about to read 5, iclass 31, count 0 2006.285.17:23:04.61#ibcon#read 5, iclass 31, count 0 2006.285.17:23:04.61#ibcon#about to read 6, iclass 31, count 0 2006.285.17:23:04.61#ibcon#read 6, iclass 31, count 0 2006.285.17:23:04.61#ibcon#end of sib2, iclass 31, count 0 2006.285.17:23:04.61#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:23:04.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:23:04.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.17:23:04.61#ibcon#*before write, iclass 31, count 0 2006.285.17:23:04.61#ibcon#enter sib2, iclass 31, count 0 2006.285.17:23:04.61#ibcon#flushed, iclass 31, count 0 2006.285.17:23:04.61#ibcon#about to write, iclass 31, count 0 2006.285.17:23:04.61#ibcon#wrote, iclass 31, count 0 2006.285.17:23:04.61#ibcon#about to read 3, iclass 31, count 0 2006.285.17:23:04.65#ibcon#read 3, iclass 31, count 0 2006.285.17:23:04.65#ibcon#about to read 4, iclass 31, count 0 2006.285.17:23:04.65#ibcon#read 4, iclass 31, count 0 2006.285.17:23:04.65#ibcon#about to read 5, iclass 31, count 0 2006.285.17:23:04.65#ibcon#read 5, iclass 31, count 0 2006.285.17:23:04.65#ibcon#about to read 6, iclass 31, count 0 2006.285.17:23:04.65#ibcon#read 6, iclass 31, count 0 2006.285.17:23:04.65#ibcon#end of sib2, iclass 31, count 0 2006.285.17:23:04.65#ibcon#*after write, iclass 31, count 0 2006.285.17:23:04.65#ibcon#*before return 0, iclass 31, count 0 2006.285.17:23:04.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:23:04.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:23:04.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:23:04.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:23:04.65$vck44/vb=7,4 2006.285.17:23:04.65#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.17:23:04.65#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.17:23:04.65#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:04.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:23:04.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:23:04.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:23:04.71#ibcon#enter wrdev, iclass 33, count 2 2006.285.17:23:04.71#ibcon#first serial, iclass 33, count 2 2006.285.17:23:04.71#ibcon#enter sib2, iclass 33, count 2 2006.285.17:23:04.71#ibcon#flushed, iclass 33, count 2 2006.285.17:23:04.71#ibcon#about to write, iclass 33, count 2 2006.285.17:23:04.71#ibcon#wrote, iclass 33, count 2 2006.285.17:23:04.71#ibcon#about to read 3, iclass 33, count 2 2006.285.17:23:04.73#ibcon#read 3, iclass 33, count 2 2006.285.17:23:04.73#ibcon#about to read 4, iclass 33, count 2 2006.285.17:23:04.73#ibcon#read 4, iclass 33, count 2 2006.285.17:23:04.73#ibcon#about to read 5, iclass 33, count 2 2006.285.17:23:04.73#ibcon#read 5, iclass 33, count 2 2006.285.17:23:04.73#ibcon#about to read 6, iclass 33, count 2 2006.285.17:23:04.73#ibcon#read 6, iclass 33, count 2 2006.285.17:23:04.73#ibcon#end of sib2, iclass 33, count 2 2006.285.17:23:04.73#ibcon#*mode == 0, iclass 33, count 2 2006.285.17:23:04.73#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.17:23:04.73#ibcon#[27=AT07-04\r\n] 2006.285.17:23:04.73#ibcon#*before write, iclass 33, count 2 2006.285.17:23:04.73#ibcon#enter sib2, iclass 33, count 2 2006.285.17:23:04.73#ibcon#flushed, iclass 33, count 2 2006.285.17:23:04.73#ibcon#about to write, iclass 33, count 2 2006.285.17:23:04.73#ibcon#wrote, iclass 33, count 2 2006.285.17:23:04.73#ibcon#about to read 3, iclass 33, count 2 2006.285.17:23:04.76#ibcon#read 3, iclass 33, count 2 2006.285.17:23:04.76#ibcon#about to read 4, iclass 33, count 2 2006.285.17:23:04.76#ibcon#read 4, iclass 33, count 2 2006.285.17:23:04.76#ibcon#about to read 5, iclass 33, count 2 2006.285.17:23:04.76#ibcon#read 5, iclass 33, count 2 2006.285.17:23:04.76#ibcon#about to read 6, iclass 33, count 2 2006.285.17:23:04.76#ibcon#read 6, iclass 33, count 2 2006.285.17:23:04.76#ibcon#end of sib2, iclass 33, count 2 2006.285.17:23:04.76#ibcon#*after write, iclass 33, count 2 2006.285.17:23:04.76#ibcon#*before return 0, iclass 33, count 2 2006.285.17:23:04.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:23:04.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:23:04.76#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.17:23:04.76#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:04.76#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:23:04.88#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:23:04.88#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:23:04.88#ibcon#enter wrdev, iclass 33, count 0 2006.285.17:23:04.88#ibcon#first serial, iclass 33, count 0 2006.285.17:23:04.88#ibcon#enter sib2, iclass 33, count 0 2006.285.17:23:04.88#ibcon#flushed, iclass 33, count 0 2006.285.17:23:04.88#ibcon#about to write, iclass 33, count 0 2006.285.17:23:04.88#ibcon#wrote, iclass 33, count 0 2006.285.17:23:04.88#ibcon#about to read 3, iclass 33, count 0 2006.285.17:23:04.90#ibcon#read 3, iclass 33, count 0 2006.285.17:23:04.90#ibcon#about to read 4, iclass 33, count 0 2006.285.17:23:04.90#ibcon#read 4, iclass 33, count 0 2006.285.17:23:04.90#ibcon#about to read 5, iclass 33, count 0 2006.285.17:23:04.90#ibcon#read 5, iclass 33, count 0 2006.285.17:23:04.90#ibcon#about to read 6, iclass 33, count 0 2006.285.17:23:04.90#ibcon#read 6, iclass 33, count 0 2006.285.17:23:04.90#ibcon#end of sib2, iclass 33, count 0 2006.285.17:23:04.90#ibcon#*mode == 0, iclass 33, count 0 2006.285.17:23:04.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.17:23:04.90#ibcon#[27=USB\r\n] 2006.285.17:23:04.90#ibcon#*before write, iclass 33, count 0 2006.285.17:23:04.90#ibcon#enter sib2, iclass 33, count 0 2006.285.17:23:04.90#ibcon#flushed, iclass 33, count 0 2006.285.17:23:04.90#ibcon#about to write, iclass 33, count 0 2006.285.17:23:04.90#ibcon#wrote, iclass 33, count 0 2006.285.17:23:04.90#ibcon#about to read 3, iclass 33, count 0 2006.285.17:23:04.93#ibcon#read 3, iclass 33, count 0 2006.285.17:23:04.93#ibcon#about to read 4, iclass 33, count 0 2006.285.17:23:04.93#ibcon#read 4, iclass 33, count 0 2006.285.17:23:04.93#ibcon#about to read 5, iclass 33, count 0 2006.285.17:23:04.93#ibcon#read 5, iclass 33, count 0 2006.285.17:23:04.93#ibcon#about to read 6, iclass 33, count 0 2006.285.17:23:04.93#ibcon#read 6, iclass 33, count 0 2006.285.17:23:04.93#ibcon#end of sib2, iclass 33, count 0 2006.285.17:23:04.93#ibcon#*after write, iclass 33, count 0 2006.285.17:23:04.93#ibcon#*before return 0, iclass 33, count 0 2006.285.17:23:04.93#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:23:04.93#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:23:04.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.17:23:04.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.17:23:04.93$vck44/vblo=8,744.99 2006.285.17:23:04.93#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.17:23:04.93#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.17:23:04.93#ibcon#ireg 17 cls_cnt 0 2006.285.17:23:04.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:23:04.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:23:04.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:23:04.93#ibcon#enter wrdev, iclass 35, count 0 2006.285.17:23:04.93#ibcon#first serial, iclass 35, count 0 2006.285.17:23:04.93#ibcon#enter sib2, iclass 35, count 0 2006.285.17:23:04.93#ibcon#flushed, iclass 35, count 0 2006.285.17:23:04.93#ibcon#about to write, iclass 35, count 0 2006.285.17:23:04.93#ibcon#wrote, iclass 35, count 0 2006.285.17:23:04.93#ibcon#about to read 3, iclass 35, count 0 2006.285.17:23:04.95#ibcon#read 3, iclass 35, count 0 2006.285.17:23:04.95#ibcon#about to read 4, iclass 35, count 0 2006.285.17:23:04.95#ibcon#read 4, iclass 35, count 0 2006.285.17:23:04.95#ibcon#about to read 5, iclass 35, count 0 2006.285.17:23:04.95#ibcon#read 5, iclass 35, count 0 2006.285.17:23:04.95#ibcon#about to read 6, iclass 35, count 0 2006.285.17:23:04.95#ibcon#read 6, iclass 35, count 0 2006.285.17:23:04.95#ibcon#end of sib2, iclass 35, count 0 2006.285.17:23:04.95#ibcon#*mode == 0, iclass 35, count 0 2006.285.17:23:04.95#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.17:23:04.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.17:23:04.95#ibcon#*before write, iclass 35, count 0 2006.285.17:23:04.95#ibcon#enter sib2, iclass 35, count 0 2006.285.17:23:04.95#ibcon#flushed, iclass 35, count 0 2006.285.17:23:04.95#ibcon#about to write, iclass 35, count 0 2006.285.17:23:04.95#ibcon#wrote, iclass 35, count 0 2006.285.17:23:04.95#ibcon#about to read 3, iclass 35, count 0 2006.285.17:23:04.99#ibcon#read 3, iclass 35, count 0 2006.285.17:23:04.99#ibcon#about to read 4, iclass 35, count 0 2006.285.17:23:04.99#ibcon#read 4, iclass 35, count 0 2006.285.17:23:04.99#ibcon#about to read 5, iclass 35, count 0 2006.285.17:23:04.99#ibcon#read 5, iclass 35, count 0 2006.285.17:23:04.99#ibcon#about to read 6, iclass 35, count 0 2006.285.17:23:04.99#ibcon#read 6, iclass 35, count 0 2006.285.17:23:04.99#ibcon#end of sib2, iclass 35, count 0 2006.285.17:23:04.99#ibcon#*after write, iclass 35, count 0 2006.285.17:23:04.99#ibcon#*before return 0, iclass 35, count 0 2006.285.17:23:04.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:23:04.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:23:04.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.17:23:04.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.17:23:04.99$vck44/vb=8,4 2006.285.17:23:04.99#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.17:23:04.99#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.17:23:04.99#ibcon#ireg 11 cls_cnt 2 2006.285.17:23:04.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:23:05.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:23:05.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:23:05.05#ibcon#enter wrdev, iclass 37, count 2 2006.285.17:23:05.05#ibcon#first serial, iclass 37, count 2 2006.285.17:23:05.05#ibcon#enter sib2, iclass 37, count 2 2006.285.17:23:05.05#ibcon#flushed, iclass 37, count 2 2006.285.17:23:05.05#ibcon#about to write, iclass 37, count 2 2006.285.17:23:05.05#ibcon#wrote, iclass 37, count 2 2006.285.17:23:05.05#ibcon#about to read 3, iclass 37, count 2 2006.285.17:23:05.07#ibcon#read 3, iclass 37, count 2 2006.285.17:23:05.07#ibcon#about to read 4, iclass 37, count 2 2006.285.17:23:05.07#ibcon#read 4, iclass 37, count 2 2006.285.17:23:05.07#ibcon#about to read 5, iclass 37, count 2 2006.285.17:23:05.07#ibcon#read 5, iclass 37, count 2 2006.285.17:23:05.07#ibcon#about to read 6, iclass 37, count 2 2006.285.17:23:05.07#ibcon#read 6, iclass 37, count 2 2006.285.17:23:05.07#ibcon#end of sib2, iclass 37, count 2 2006.285.17:23:05.07#ibcon#*mode == 0, iclass 37, count 2 2006.285.17:23:05.07#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.17:23:05.07#ibcon#[27=AT08-04\r\n] 2006.285.17:23:05.07#ibcon#*before write, iclass 37, count 2 2006.285.17:23:05.07#ibcon#enter sib2, iclass 37, count 2 2006.285.17:23:05.07#ibcon#flushed, iclass 37, count 2 2006.285.17:23:05.07#ibcon#about to write, iclass 37, count 2 2006.285.17:23:05.07#ibcon#wrote, iclass 37, count 2 2006.285.17:23:05.07#ibcon#about to read 3, iclass 37, count 2 2006.285.17:23:05.10#ibcon#read 3, iclass 37, count 2 2006.285.17:23:05.10#ibcon#about to read 4, iclass 37, count 2 2006.285.17:23:05.10#ibcon#read 4, iclass 37, count 2 2006.285.17:23:05.10#ibcon#about to read 5, iclass 37, count 2 2006.285.17:23:05.10#ibcon#read 5, iclass 37, count 2 2006.285.17:23:05.10#ibcon#about to read 6, iclass 37, count 2 2006.285.17:23:05.10#ibcon#read 6, iclass 37, count 2 2006.285.17:23:05.10#ibcon#end of sib2, iclass 37, count 2 2006.285.17:23:05.10#ibcon#*after write, iclass 37, count 2 2006.285.17:23:05.10#ibcon#*before return 0, iclass 37, count 2 2006.285.17:23:05.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:23:05.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:23:05.10#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.17:23:05.10#ibcon#ireg 7 cls_cnt 0 2006.285.17:23:05.10#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:23:05.22#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:23:05.22#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:23:05.22#ibcon#enter wrdev, iclass 37, count 0 2006.285.17:23:05.22#ibcon#first serial, iclass 37, count 0 2006.285.17:23:05.22#ibcon#enter sib2, iclass 37, count 0 2006.285.17:23:05.22#ibcon#flushed, iclass 37, count 0 2006.285.17:23:05.22#ibcon#about to write, iclass 37, count 0 2006.285.17:23:05.22#ibcon#wrote, iclass 37, count 0 2006.285.17:23:05.22#ibcon#about to read 3, iclass 37, count 0 2006.285.17:23:05.24#ibcon#read 3, iclass 37, count 0 2006.285.17:23:05.24#ibcon#about to read 4, iclass 37, count 0 2006.285.17:23:05.24#ibcon#read 4, iclass 37, count 0 2006.285.17:23:05.24#ibcon#about to read 5, iclass 37, count 0 2006.285.17:23:05.24#ibcon#read 5, iclass 37, count 0 2006.285.17:23:05.24#ibcon#about to read 6, iclass 37, count 0 2006.285.17:23:05.24#ibcon#read 6, iclass 37, count 0 2006.285.17:23:05.24#ibcon#end of sib2, iclass 37, count 0 2006.285.17:23:05.24#ibcon#*mode == 0, iclass 37, count 0 2006.285.17:23:05.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.17:23:05.24#ibcon#[27=USB\r\n] 2006.285.17:23:05.24#ibcon#*before write, iclass 37, count 0 2006.285.17:23:05.24#ibcon#enter sib2, iclass 37, count 0 2006.285.17:23:05.24#ibcon#flushed, iclass 37, count 0 2006.285.17:23:05.24#ibcon#about to write, iclass 37, count 0 2006.285.17:23:05.24#ibcon#wrote, iclass 37, count 0 2006.285.17:23:05.24#ibcon#about to read 3, iclass 37, count 0 2006.285.17:23:05.27#ibcon#read 3, iclass 37, count 0 2006.285.17:23:05.27#ibcon#about to read 4, iclass 37, count 0 2006.285.17:23:05.27#ibcon#read 4, iclass 37, count 0 2006.285.17:23:05.27#ibcon#about to read 5, iclass 37, count 0 2006.285.17:23:05.27#ibcon#read 5, iclass 37, count 0 2006.285.17:23:05.27#ibcon#about to read 6, iclass 37, count 0 2006.285.17:23:05.27#ibcon#read 6, iclass 37, count 0 2006.285.17:23:05.27#ibcon#end of sib2, iclass 37, count 0 2006.285.17:23:05.27#ibcon#*after write, iclass 37, count 0 2006.285.17:23:05.27#ibcon#*before return 0, iclass 37, count 0 2006.285.17:23:05.27#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:23:05.27#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:23:05.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.17:23:05.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.17:23:05.27$vck44/vabw=wide 2006.285.17:23:05.27#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.17:23:05.27#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.17:23:05.27#ibcon#ireg 8 cls_cnt 0 2006.285.17:23:05.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:23:05.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:23:05.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:23:05.27#ibcon#enter wrdev, iclass 39, count 0 2006.285.17:23:05.27#ibcon#first serial, iclass 39, count 0 2006.285.17:23:05.27#ibcon#enter sib2, iclass 39, count 0 2006.285.17:23:05.27#ibcon#flushed, iclass 39, count 0 2006.285.17:23:05.27#ibcon#about to write, iclass 39, count 0 2006.285.17:23:05.27#ibcon#wrote, iclass 39, count 0 2006.285.17:23:05.27#ibcon#about to read 3, iclass 39, count 0 2006.285.17:23:05.29#ibcon#read 3, iclass 39, count 0 2006.285.17:23:05.29#ibcon#about to read 4, iclass 39, count 0 2006.285.17:23:05.29#ibcon#read 4, iclass 39, count 0 2006.285.17:23:05.29#ibcon#about to read 5, iclass 39, count 0 2006.285.17:23:05.29#ibcon#read 5, iclass 39, count 0 2006.285.17:23:05.29#ibcon#about to read 6, iclass 39, count 0 2006.285.17:23:05.29#ibcon#read 6, iclass 39, count 0 2006.285.17:23:05.29#ibcon#end of sib2, iclass 39, count 0 2006.285.17:23:05.29#ibcon#*mode == 0, iclass 39, count 0 2006.285.17:23:05.29#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.17:23:05.29#ibcon#[25=BW32\r\n] 2006.285.17:23:05.29#ibcon#*before write, iclass 39, count 0 2006.285.17:23:05.29#ibcon#enter sib2, iclass 39, count 0 2006.285.17:23:05.29#ibcon#flushed, iclass 39, count 0 2006.285.17:23:05.29#ibcon#about to write, iclass 39, count 0 2006.285.17:23:05.29#ibcon#wrote, iclass 39, count 0 2006.285.17:23:05.29#ibcon#about to read 3, iclass 39, count 0 2006.285.17:23:05.32#ibcon#read 3, iclass 39, count 0 2006.285.17:23:05.32#ibcon#about to read 4, iclass 39, count 0 2006.285.17:23:05.32#ibcon#read 4, iclass 39, count 0 2006.285.17:23:05.32#ibcon#about to read 5, iclass 39, count 0 2006.285.17:23:05.32#ibcon#read 5, iclass 39, count 0 2006.285.17:23:05.32#ibcon#about to read 6, iclass 39, count 0 2006.285.17:23:05.32#ibcon#read 6, iclass 39, count 0 2006.285.17:23:05.32#ibcon#end of sib2, iclass 39, count 0 2006.285.17:23:05.32#ibcon#*after write, iclass 39, count 0 2006.285.17:23:05.32#ibcon#*before return 0, iclass 39, count 0 2006.285.17:23:05.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:23:05.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:23:05.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.17:23:05.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.17:23:05.32$vck44/vbbw=wide 2006.285.17:23:05.32#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.17:23:05.32#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.17:23:05.32#ibcon#ireg 8 cls_cnt 0 2006.285.17:23:05.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:23:05.39#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:23:05.39#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:23:05.39#ibcon#enter wrdev, iclass 3, count 0 2006.285.17:23:05.39#ibcon#first serial, iclass 3, count 0 2006.285.17:23:05.39#ibcon#enter sib2, iclass 3, count 0 2006.285.17:23:05.39#ibcon#flushed, iclass 3, count 0 2006.285.17:23:05.39#ibcon#about to write, iclass 3, count 0 2006.285.17:23:05.39#ibcon#wrote, iclass 3, count 0 2006.285.17:23:05.39#ibcon#about to read 3, iclass 3, count 0 2006.285.17:23:05.41#ibcon#read 3, iclass 3, count 0 2006.285.17:23:05.41#ibcon#about to read 4, iclass 3, count 0 2006.285.17:23:05.41#ibcon#read 4, iclass 3, count 0 2006.285.17:23:05.41#ibcon#about to read 5, iclass 3, count 0 2006.285.17:23:05.41#ibcon#read 5, iclass 3, count 0 2006.285.17:23:05.41#ibcon#about to read 6, iclass 3, count 0 2006.285.17:23:05.41#ibcon#read 6, iclass 3, count 0 2006.285.17:23:05.41#ibcon#end of sib2, iclass 3, count 0 2006.285.17:23:05.41#ibcon#*mode == 0, iclass 3, count 0 2006.285.17:23:05.41#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.17:23:05.41#ibcon#[27=BW32\r\n] 2006.285.17:23:05.41#ibcon#*before write, iclass 3, count 0 2006.285.17:23:05.41#ibcon#enter sib2, iclass 3, count 0 2006.285.17:23:05.41#ibcon#flushed, iclass 3, count 0 2006.285.17:23:05.41#ibcon#about to write, iclass 3, count 0 2006.285.17:23:05.41#ibcon#wrote, iclass 3, count 0 2006.285.17:23:05.41#ibcon#about to read 3, iclass 3, count 0 2006.285.17:23:05.44#ibcon#read 3, iclass 3, count 0 2006.285.17:23:05.44#ibcon#about to read 4, iclass 3, count 0 2006.285.17:23:05.44#ibcon#read 4, iclass 3, count 0 2006.285.17:23:05.44#ibcon#about to read 5, iclass 3, count 0 2006.285.17:23:05.44#ibcon#read 5, iclass 3, count 0 2006.285.17:23:05.44#ibcon#about to read 6, iclass 3, count 0 2006.285.17:23:05.44#ibcon#read 6, iclass 3, count 0 2006.285.17:23:05.44#ibcon#end of sib2, iclass 3, count 0 2006.285.17:23:05.44#ibcon#*after write, iclass 3, count 0 2006.285.17:23:05.44#ibcon#*before return 0, iclass 3, count 0 2006.285.17:23:05.44#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:23:05.44#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:23:05.44#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.17:23:05.44#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.17:23:05.44$setupk4/ifdk4 2006.285.17:23:05.44$ifdk4/lo= 2006.285.17:23:05.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.17:23:05.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.17:23:05.44$ifdk4/patch= 2006.285.17:23:05.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.17:23:05.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.17:23:05.44$setupk4/!*+20s 2006.285.17:23:12.64#abcon#<5=/12 0.3 1.2 16.93 981014.8\r\n> 2006.285.17:23:12.66#abcon#{5=INTERFACE CLEAR} 2006.285.17:23:12.72#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:23:16.14#trakl#Source acquired 2006.285.17:23:18.14#flagr#flagr/antenna,acquired 2006.285.17:23:19.21$setupk4/"tpicd 2006.285.17:23:19.21$setupk4/echo=off 2006.285.17:23:19.21$setupk4/xlog=off 2006.285.17:23:19.21:!2006.285.17:27:14 2006.285.17:27:14.00:preob 2006.285.17:27:14.13/onsource/TRACKING 2006.285.17:27:14.13:!2006.285.17:27:24 2006.285.17:27:24.00:"tape 2006.285.17:27:24.00:"st=record 2006.285.17:27:24.00:data_valid=on 2006.285.17:27:24.00:midob 2006.285.17:27:24.13/onsource/TRACKING 2006.285.17:27:24.13/wx/16.90,1014.8,98 2006.285.17:27:24.24/cable/+6.5002E-03 2006.285.17:27:25.33/va/01,07,usb,yes,31,34 2006.285.17:27:25.33/va/02,06,usb,yes,31,32 2006.285.17:27:25.33/va/03,07,usb,yes,31,33 2006.285.17:27:25.33/va/04,06,usb,yes,32,34 2006.285.17:27:25.33/va/05,03,usb,yes,32,32 2006.285.17:27:25.33/va/06,04,usb,yes,29,28 2006.285.17:27:25.33/va/07,04,usb,yes,29,30 2006.285.17:27:25.33/va/08,03,usb,yes,30,36 2006.285.17:27:25.56/valo/01,524.99,yes,locked 2006.285.17:27:25.56/valo/02,534.99,yes,locked 2006.285.17:27:25.56/valo/03,564.99,yes,locked 2006.285.17:27:25.56/valo/04,624.99,yes,locked 2006.285.17:27:25.56/valo/05,734.99,yes,locked 2006.285.17:27:25.56/valo/06,814.99,yes,locked 2006.285.17:27:25.56/valo/07,864.99,yes,locked 2006.285.17:27:25.56/valo/08,884.99,yes,locked 2006.285.17:27:26.65/vb/01,04,usb,yes,30,28 2006.285.17:27:26.65/vb/02,05,usb,yes,28,28 2006.285.17:27:26.65/vb/03,04,usb,yes,29,32 2006.285.17:27:26.65/vb/04,05,usb,yes,29,28 2006.285.17:27:26.65/vb/05,04,usb,yes,26,28 2006.285.17:27:26.65/vb/06,03,usb,yes,37,33 2006.285.17:27:26.65/vb/07,04,usb,yes,30,30 2006.285.17:27:26.65/vb/08,04,usb,yes,27,31 2006.285.17:27:26.88/vblo/01,629.99,yes,locked 2006.285.17:27:26.88/vblo/02,634.99,yes,locked 2006.285.17:27:26.88/vblo/03,649.99,yes,locked 2006.285.17:27:26.88/vblo/04,679.99,yes,locked 2006.285.17:27:26.88/vblo/05,709.99,yes,locked 2006.285.17:27:26.88/vblo/06,719.99,yes,locked 2006.285.17:27:26.88/vblo/07,734.99,yes,locked 2006.285.17:27:26.88/vblo/08,744.99,yes,locked 2006.285.17:27:27.03/vabw/8 2006.285.17:27:27.18/vbbw/8 2006.285.17:27:27.30/xfe/off,on,12.2 2006.285.17:27:27.67/ifatt/23,28,28,28 2006.285.17:27:28.07/fmout-gps/S +2.60E-07 2006.285.17:27:28.09:!2006.285.17:28:14 2006.285.17:28:14.00:data_valid=off 2006.285.17:28:14.00:"et 2006.285.17:28:14.00:!+3s 2006.285.17:28:17.01:"tape 2006.285.17:28:17.01:postob 2006.285.17:28:17.14/cable/+6.5023E-03 2006.285.17:28:17.14/wx/16.88,1014.8,98 2006.285.17:28:18.07/fmout-gps/S +2.62E-07 2006.285.17:28:18.07:scan_name=285-1730,jd0610,460 2006.285.17:28:18.07:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.285.17:28:19.13#flagr#flagr/antenna,new-source 2006.285.17:28:19.13:checkk5 2006.285.17:28:19.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.17:28:20.05/chk_autoobs//k5ts2/ autoobs is running! 2006.285.17:28:20.43/chk_autoobs//k5ts3/ autoobs is running! 2006.285.17:28:20.78/chk_autoobs//k5ts4/ autoobs is running! 2006.285.17:28:21.21/chk_obsdata//k5ts1/T2851727??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.17:28:21.62/chk_obsdata//k5ts2/T2851727??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.17:28:22.15/chk_obsdata//k5ts3/T2851727??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.17:28:22.56/chk_obsdata//k5ts4/T2851727??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.285.17:28:23.52/k5log//k5ts1_log_newline 2006.285.17:28:24.29/k5log//k5ts2_log_newline 2006.285.17:28:25.04/k5log//k5ts3_log_newline 2006.285.17:28:25.79/k5log//k5ts4_log_newline 2006.285.17:28:25.81/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.17:28:25.81:setupk4=1 2006.285.17:28:25.81$setupk4/echo=on 2006.285.17:28:25.81$setupk4/pcalon 2006.285.17:28:25.81$pcalon/"no phase cal control is implemented here 2006.285.17:28:25.81$setupk4/"tpicd=stop 2006.285.17:28:25.81$setupk4/"rec=synch_on 2006.285.17:28:25.82$setupk4/"rec_mode=128 2006.285.17:28:25.82$setupk4/!* 2006.285.17:28:25.82$setupk4/recpk4 2006.285.17:28:25.82$recpk4/recpatch= 2006.285.17:28:25.82$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.17:28:25.82$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.17:28:25.82$setupk4/vck44 2006.285.17:28:25.82$vck44/valo=1,524.99 2006.285.17:28:25.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.17:28:25.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.17:28:25.82#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:25.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:28:25.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:28:25.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:28:25.82#ibcon#enter wrdev, iclass 26, count 0 2006.285.17:28:25.82#ibcon#first serial, iclass 26, count 0 2006.285.17:28:25.82#ibcon#enter sib2, iclass 26, count 0 2006.285.17:28:25.82#ibcon#flushed, iclass 26, count 0 2006.285.17:28:25.82#ibcon#about to write, iclass 26, count 0 2006.285.17:28:25.82#ibcon#wrote, iclass 26, count 0 2006.285.17:28:25.82#ibcon#about to read 3, iclass 26, count 0 2006.285.17:28:25.84#ibcon#read 3, iclass 26, count 0 2006.285.17:28:25.84#ibcon#about to read 4, iclass 26, count 0 2006.285.17:28:25.84#ibcon#read 4, iclass 26, count 0 2006.285.17:28:25.84#ibcon#about to read 5, iclass 26, count 0 2006.285.17:28:25.84#ibcon#read 5, iclass 26, count 0 2006.285.17:28:25.84#ibcon#about to read 6, iclass 26, count 0 2006.285.17:28:25.84#ibcon#read 6, iclass 26, count 0 2006.285.17:28:25.84#ibcon#end of sib2, iclass 26, count 0 2006.285.17:28:25.84#ibcon#*mode == 0, iclass 26, count 0 2006.285.17:28:25.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.17:28:25.84#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.17:28:25.84#ibcon#*before write, iclass 26, count 0 2006.285.17:28:25.84#ibcon#enter sib2, iclass 26, count 0 2006.285.17:28:25.84#ibcon#flushed, iclass 26, count 0 2006.285.17:28:25.84#ibcon#about to write, iclass 26, count 0 2006.285.17:28:25.84#ibcon#wrote, iclass 26, count 0 2006.285.17:28:25.84#ibcon#about to read 3, iclass 26, count 0 2006.285.17:28:25.89#ibcon#read 3, iclass 26, count 0 2006.285.17:28:25.89#ibcon#about to read 4, iclass 26, count 0 2006.285.17:28:25.89#ibcon#read 4, iclass 26, count 0 2006.285.17:28:25.89#ibcon#about to read 5, iclass 26, count 0 2006.285.17:28:25.89#ibcon#read 5, iclass 26, count 0 2006.285.17:28:25.89#ibcon#about to read 6, iclass 26, count 0 2006.285.17:28:25.89#ibcon#read 6, iclass 26, count 0 2006.285.17:28:25.89#ibcon#end of sib2, iclass 26, count 0 2006.285.17:28:25.89#ibcon#*after write, iclass 26, count 0 2006.285.17:28:25.89#ibcon#*before return 0, iclass 26, count 0 2006.285.17:28:25.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:28:25.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:28:25.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.17:28:25.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.17:28:25.89$vck44/va=1,7 2006.285.17:28:25.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.17:28:25.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.17:28:25.89#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:25.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:28:25.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:28:25.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:28:25.89#ibcon#enter wrdev, iclass 28, count 2 2006.285.17:28:25.89#ibcon#first serial, iclass 28, count 2 2006.285.17:28:25.89#ibcon#enter sib2, iclass 28, count 2 2006.285.17:28:25.89#ibcon#flushed, iclass 28, count 2 2006.285.17:28:25.89#ibcon#about to write, iclass 28, count 2 2006.285.17:28:25.89#ibcon#wrote, iclass 28, count 2 2006.285.17:28:25.89#ibcon#about to read 3, iclass 28, count 2 2006.285.17:28:25.91#ibcon#read 3, iclass 28, count 2 2006.285.17:28:25.91#ibcon#about to read 4, iclass 28, count 2 2006.285.17:28:25.91#ibcon#read 4, iclass 28, count 2 2006.285.17:28:25.91#ibcon#about to read 5, iclass 28, count 2 2006.285.17:28:25.91#ibcon#read 5, iclass 28, count 2 2006.285.17:28:25.91#ibcon#about to read 6, iclass 28, count 2 2006.285.17:28:25.91#ibcon#read 6, iclass 28, count 2 2006.285.17:28:25.91#ibcon#end of sib2, iclass 28, count 2 2006.285.17:28:25.91#ibcon#*mode == 0, iclass 28, count 2 2006.285.17:28:25.91#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.17:28:25.91#ibcon#[25=AT01-07\r\n] 2006.285.17:28:25.91#ibcon#*before write, iclass 28, count 2 2006.285.17:28:25.91#ibcon#enter sib2, iclass 28, count 2 2006.285.17:28:25.91#ibcon#flushed, iclass 28, count 2 2006.285.17:28:25.91#ibcon#about to write, iclass 28, count 2 2006.285.17:28:25.91#ibcon#wrote, iclass 28, count 2 2006.285.17:28:25.91#ibcon#about to read 3, iclass 28, count 2 2006.285.17:28:25.94#ibcon#read 3, iclass 28, count 2 2006.285.17:28:25.94#ibcon#about to read 4, iclass 28, count 2 2006.285.17:28:25.94#ibcon#read 4, iclass 28, count 2 2006.285.17:28:25.94#ibcon#about to read 5, iclass 28, count 2 2006.285.17:28:25.94#ibcon#read 5, iclass 28, count 2 2006.285.17:28:25.94#ibcon#about to read 6, iclass 28, count 2 2006.285.17:28:25.94#ibcon#read 6, iclass 28, count 2 2006.285.17:28:25.94#ibcon#end of sib2, iclass 28, count 2 2006.285.17:28:25.94#ibcon#*after write, iclass 28, count 2 2006.285.17:28:25.94#ibcon#*before return 0, iclass 28, count 2 2006.285.17:28:25.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:28:25.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:28:25.94#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.17:28:25.94#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:25.94#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:28:26.06#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:28:26.06#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:28:26.06#ibcon#enter wrdev, iclass 28, count 0 2006.285.17:28:26.06#ibcon#first serial, iclass 28, count 0 2006.285.17:28:26.06#ibcon#enter sib2, iclass 28, count 0 2006.285.17:28:26.06#ibcon#flushed, iclass 28, count 0 2006.285.17:28:26.06#ibcon#about to write, iclass 28, count 0 2006.285.17:28:26.06#ibcon#wrote, iclass 28, count 0 2006.285.17:28:26.06#ibcon#about to read 3, iclass 28, count 0 2006.285.17:28:26.08#ibcon#read 3, iclass 28, count 0 2006.285.17:28:26.08#ibcon#about to read 4, iclass 28, count 0 2006.285.17:28:26.08#ibcon#read 4, iclass 28, count 0 2006.285.17:28:26.08#ibcon#about to read 5, iclass 28, count 0 2006.285.17:28:26.08#ibcon#read 5, iclass 28, count 0 2006.285.17:28:26.08#ibcon#about to read 6, iclass 28, count 0 2006.285.17:28:26.08#ibcon#read 6, iclass 28, count 0 2006.285.17:28:26.08#ibcon#end of sib2, iclass 28, count 0 2006.285.17:28:26.08#ibcon#*mode == 0, iclass 28, count 0 2006.285.17:28:26.08#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.17:28:26.08#ibcon#[25=USB\r\n] 2006.285.17:28:26.08#ibcon#*before write, iclass 28, count 0 2006.285.17:28:26.08#ibcon#enter sib2, iclass 28, count 0 2006.285.17:28:26.08#ibcon#flushed, iclass 28, count 0 2006.285.17:28:26.08#ibcon#about to write, iclass 28, count 0 2006.285.17:28:26.08#ibcon#wrote, iclass 28, count 0 2006.285.17:28:26.08#ibcon#about to read 3, iclass 28, count 0 2006.285.17:28:26.11#ibcon#read 3, iclass 28, count 0 2006.285.17:28:26.11#ibcon#about to read 4, iclass 28, count 0 2006.285.17:28:26.11#ibcon#read 4, iclass 28, count 0 2006.285.17:28:26.11#ibcon#about to read 5, iclass 28, count 0 2006.285.17:28:26.11#ibcon#read 5, iclass 28, count 0 2006.285.17:28:26.11#ibcon#about to read 6, iclass 28, count 0 2006.285.17:28:26.11#ibcon#read 6, iclass 28, count 0 2006.285.17:28:26.11#ibcon#end of sib2, iclass 28, count 0 2006.285.17:28:26.11#ibcon#*after write, iclass 28, count 0 2006.285.17:28:26.11#ibcon#*before return 0, iclass 28, count 0 2006.285.17:28:26.11#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:28:26.11#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:28:26.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.17:28:26.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.17:28:26.11$vck44/valo=2,534.99 2006.285.17:28:26.11#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.17:28:26.11#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.17:28:26.11#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:26.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:28:26.11#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:28:26.11#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:28:26.11#ibcon#enter wrdev, iclass 30, count 0 2006.285.17:28:26.11#ibcon#first serial, iclass 30, count 0 2006.285.17:28:26.11#ibcon#enter sib2, iclass 30, count 0 2006.285.17:28:26.11#ibcon#flushed, iclass 30, count 0 2006.285.17:28:26.11#ibcon#about to write, iclass 30, count 0 2006.285.17:28:26.11#ibcon#wrote, iclass 30, count 0 2006.285.17:28:26.11#ibcon#about to read 3, iclass 30, count 0 2006.285.17:28:26.13#ibcon#read 3, iclass 30, count 0 2006.285.17:28:26.13#ibcon#about to read 4, iclass 30, count 0 2006.285.17:28:26.13#ibcon#read 4, iclass 30, count 0 2006.285.17:28:26.13#ibcon#about to read 5, iclass 30, count 0 2006.285.17:28:26.13#ibcon#read 5, iclass 30, count 0 2006.285.17:28:26.13#ibcon#about to read 6, iclass 30, count 0 2006.285.17:28:26.13#ibcon#read 6, iclass 30, count 0 2006.285.17:28:26.13#ibcon#end of sib2, iclass 30, count 0 2006.285.17:28:26.13#ibcon#*mode == 0, iclass 30, count 0 2006.285.17:28:26.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.17:28:26.13#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.17:28:26.13#ibcon#*before write, iclass 30, count 0 2006.285.17:28:26.13#ibcon#enter sib2, iclass 30, count 0 2006.285.17:28:26.13#ibcon#flushed, iclass 30, count 0 2006.285.17:28:26.13#ibcon#about to write, iclass 30, count 0 2006.285.17:28:26.13#ibcon#wrote, iclass 30, count 0 2006.285.17:28:26.13#ibcon#about to read 3, iclass 30, count 0 2006.285.17:28:26.17#ibcon#read 3, iclass 30, count 0 2006.285.17:28:26.17#ibcon#about to read 4, iclass 30, count 0 2006.285.17:28:26.17#ibcon#read 4, iclass 30, count 0 2006.285.17:28:26.17#ibcon#about to read 5, iclass 30, count 0 2006.285.17:28:26.17#ibcon#read 5, iclass 30, count 0 2006.285.17:28:26.17#ibcon#about to read 6, iclass 30, count 0 2006.285.17:28:26.17#ibcon#read 6, iclass 30, count 0 2006.285.17:28:26.17#ibcon#end of sib2, iclass 30, count 0 2006.285.17:28:26.17#ibcon#*after write, iclass 30, count 0 2006.285.17:28:26.17#ibcon#*before return 0, iclass 30, count 0 2006.285.17:28:26.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:28:26.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:28:26.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.17:28:26.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.17:28:26.17$vck44/va=2,6 2006.285.17:28:26.17#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.17:28:26.17#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.17:28:26.17#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:26.17#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:28:26.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:28:26.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:28:26.23#ibcon#enter wrdev, iclass 32, count 2 2006.285.17:28:26.23#ibcon#first serial, iclass 32, count 2 2006.285.17:28:26.23#ibcon#enter sib2, iclass 32, count 2 2006.285.17:28:26.23#ibcon#flushed, iclass 32, count 2 2006.285.17:28:26.23#ibcon#about to write, iclass 32, count 2 2006.285.17:28:26.23#ibcon#wrote, iclass 32, count 2 2006.285.17:28:26.23#ibcon#about to read 3, iclass 32, count 2 2006.285.17:28:26.25#ibcon#read 3, iclass 32, count 2 2006.285.17:28:26.25#ibcon#about to read 4, iclass 32, count 2 2006.285.17:28:26.25#ibcon#read 4, iclass 32, count 2 2006.285.17:28:26.25#ibcon#about to read 5, iclass 32, count 2 2006.285.17:28:26.25#ibcon#read 5, iclass 32, count 2 2006.285.17:28:26.25#ibcon#about to read 6, iclass 32, count 2 2006.285.17:28:26.25#ibcon#read 6, iclass 32, count 2 2006.285.17:28:26.25#ibcon#end of sib2, iclass 32, count 2 2006.285.17:28:26.25#ibcon#*mode == 0, iclass 32, count 2 2006.285.17:28:26.25#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.17:28:26.25#ibcon#[25=AT02-06\r\n] 2006.285.17:28:26.25#ibcon#*before write, iclass 32, count 2 2006.285.17:28:26.25#ibcon#enter sib2, iclass 32, count 2 2006.285.17:28:26.25#ibcon#flushed, iclass 32, count 2 2006.285.17:28:26.25#ibcon#about to write, iclass 32, count 2 2006.285.17:28:26.25#ibcon#wrote, iclass 32, count 2 2006.285.17:28:26.25#ibcon#about to read 3, iclass 32, count 2 2006.285.17:28:26.28#ibcon#read 3, iclass 32, count 2 2006.285.17:28:26.28#ibcon#about to read 4, iclass 32, count 2 2006.285.17:28:26.28#ibcon#read 4, iclass 32, count 2 2006.285.17:28:26.28#ibcon#about to read 5, iclass 32, count 2 2006.285.17:28:26.28#ibcon#read 5, iclass 32, count 2 2006.285.17:28:26.28#ibcon#about to read 6, iclass 32, count 2 2006.285.17:28:26.28#ibcon#read 6, iclass 32, count 2 2006.285.17:28:26.28#ibcon#end of sib2, iclass 32, count 2 2006.285.17:28:26.28#ibcon#*after write, iclass 32, count 2 2006.285.17:28:26.28#ibcon#*before return 0, iclass 32, count 2 2006.285.17:28:26.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:28:26.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:28:26.28#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.17:28:26.28#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:26.28#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:28:26.40#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:28:26.40#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:28:26.40#ibcon#enter wrdev, iclass 32, count 0 2006.285.17:28:26.40#ibcon#first serial, iclass 32, count 0 2006.285.17:28:26.40#ibcon#enter sib2, iclass 32, count 0 2006.285.17:28:26.40#ibcon#flushed, iclass 32, count 0 2006.285.17:28:26.40#ibcon#about to write, iclass 32, count 0 2006.285.17:28:26.40#ibcon#wrote, iclass 32, count 0 2006.285.17:28:26.40#ibcon#about to read 3, iclass 32, count 0 2006.285.17:28:26.42#ibcon#read 3, iclass 32, count 0 2006.285.17:28:26.42#ibcon#about to read 4, iclass 32, count 0 2006.285.17:28:26.42#ibcon#read 4, iclass 32, count 0 2006.285.17:28:26.42#ibcon#about to read 5, iclass 32, count 0 2006.285.17:28:26.42#ibcon#read 5, iclass 32, count 0 2006.285.17:28:26.42#ibcon#about to read 6, iclass 32, count 0 2006.285.17:28:26.42#ibcon#read 6, iclass 32, count 0 2006.285.17:28:26.42#ibcon#end of sib2, iclass 32, count 0 2006.285.17:28:26.42#ibcon#*mode == 0, iclass 32, count 0 2006.285.17:28:26.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.17:28:26.42#ibcon#[25=USB\r\n] 2006.285.17:28:26.42#ibcon#*before write, iclass 32, count 0 2006.285.17:28:26.42#ibcon#enter sib2, iclass 32, count 0 2006.285.17:28:26.42#ibcon#flushed, iclass 32, count 0 2006.285.17:28:26.42#ibcon#about to write, iclass 32, count 0 2006.285.17:28:26.42#ibcon#wrote, iclass 32, count 0 2006.285.17:28:26.42#ibcon#about to read 3, iclass 32, count 0 2006.285.17:28:26.45#ibcon#read 3, iclass 32, count 0 2006.285.17:28:26.45#ibcon#about to read 4, iclass 32, count 0 2006.285.17:28:26.45#ibcon#read 4, iclass 32, count 0 2006.285.17:28:26.45#ibcon#about to read 5, iclass 32, count 0 2006.285.17:28:26.45#ibcon#read 5, iclass 32, count 0 2006.285.17:28:26.45#ibcon#about to read 6, iclass 32, count 0 2006.285.17:28:26.45#ibcon#read 6, iclass 32, count 0 2006.285.17:28:26.45#ibcon#end of sib2, iclass 32, count 0 2006.285.17:28:26.45#ibcon#*after write, iclass 32, count 0 2006.285.17:28:26.45#ibcon#*before return 0, iclass 32, count 0 2006.285.17:28:26.45#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:28:26.45#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:28:26.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.17:28:26.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.17:28:26.45$vck44/valo=3,564.99 2006.285.17:28:26.45#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.17:28:26.45#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.17:28:26.45#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:26.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:28:26.45#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:28:26.45#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:28:26.45#ibcon#enter wrdev, iclass 34, count 0 2006.285.17:28:26.45#ibcon#first serial, iclass 34, count 0 2006.285.17:28:26.45#ibcon#enter sib2, iclass 34, count 0 2006.285.17:28:26.45#ibcon#flushed, iclass 34, count 0 2006.285.17:28:26.45#ibcon#about to write, iclass 34, count 0 2006.285.17:28:26.45#ibcon#wrote, iclass 34, count 0 2006.285.17:28:26.45#ibcon#about to read 3, iclass 34, count 0 2006.285.17:28:26.47#ibcon#read 3, iclass 34, count 0 2006.285.17:28:26.47#ibcon#about to read 4, iclass 34, count 0 2006.285.17:28:26.47#ibcon#read 4, iclass 34, count 0 2006.285.17:28:26.47#ibcon#about to read 5, iclass 34, count 0 2006.285.17:28:26.47#ibcon#read 5, iclass 34, count 0 2006.285.17:28:26.47#ibcon#about to read 6, iclass 34, count 0 2006.285.17:28:26.47#ibcon#read 6, iclass 34, count 0 2006.285.17:28:26.47#ibcon#end of sib2, iclass 34, count 0 2006.285.17:28:26.47#ibcon#*mode == 0, iclass 34, count 0 2006.285.17:28:26.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.17:28:26.47#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.17:28:26.47#ibcon#*before write, iclass 34, count 0 2006.285.17:28:26.47#ibcon#enter sib2, iclass 34, count 0 2006.285.17:28:26.47#ibcon#flushed, iclass 34, count 0 2006.285.17:28:26.47#ibcon#about to write, iclass 34, count 0 2006.285.17:28:26.47#ibcon#wrote, iclass 34, count 0 2006.285.17:28:26.47#ibcon#about to read 3, iclass 34, count 0 2006.285.17:28:26.51#ibcon#read 3, iclass 34, count 0 2006.285.17:28:26.51#ibcon#about to read 4, iclass 34, count 0 2006.285.17:28:26.51#ibcon#read 4, iclass 34, count 0 2006.285.17:28:26.51#ibcon#about to read 5, iclass 34, count 0 2006.285.17:28:26.51#ibcon#read 5, iclass 34, count 0 2006.285.17:28:26.51#ibcon#about to read 6, iclass 34, count 0 2006.285.17:28:26.51#ibcon#read 6, iclass 34, count 0 2006.285.17:28:26.51#ibcon#end of sib2, iclass 34, count 0 2006.285.17:28:26.51#ibcon#*after write, iclass 34, count 0 2006.285.17:28:26.51#ibcon#*before return 0, iclass 34, count 0 2006.285.17:28:26.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:28:26.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:28:26.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.17:28:26.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.17:28:26.51$vck44/va=3,7 2006.285.17:28:26.51#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.17:28:26.51#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.17:28:26.51#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:26.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:28:26.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:28:26.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:28:26.57#ibcon#enter wrdev, iclass 36, count 2 2006.285.17:28:26.57#ibcon#first serial, iclass 36, count 2 2006.285.17:28:26.57#ibcon#enter sib2, iclass 36, count 2 2006.285.17:28:26.57#ibcon#flushed, iclass 36, count 2 2006.285.17:28:26.57#ibcon#about to write, iclass 36, count 2 2006.285.17:28:26.57#ibcon#wrote, iclass 36, count 2 2006.285.17:28:26.57#ibcon#about to read 3, iclass 36, count 2 2006.285.17:28:26.59#ibcon#read 3, iclass 36, count 2 2006.285.17:28:26.59#ibcon#about to read 4, iclass 36, count 2 2006.285.17:28:26.59#ibcon#read 4, iclass 36, count 2 2006.285.17:28:26.59#ibcon#about to read 5, iclass 36, count 2 2006.285.17:28:26.59#ibcon#read 5, iclass 36, count 2 2006.285.17:28:26.59#ibcon#about to read 6, iclass 36, count 2 2006.285.17:28:26.59#ibcon#read 6, iclass 36, count 2 2006.285.17:28:26.59#ibcon#end of sib2, iclass 36, count 2 2006.285.17:28:26.59#ibcon#*mode == 0, iclass 36, count 2 2006.285.17:28:26.59#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.17:28:26.59#ibcon#[25=AT03-07\r\n] 2006.285.17:28:26.59#ibcon#*before write, iclass 36, count 2 2006.285.17:28:26.59#ibcon#enter sib2, iclass 36, count 2 2006.285.17:28:26.59#ibcon#flushed, iclass 36, count 2 2006.285.17:28:26.59#ibcon#about to write, iclass 36, count 2 2006.285.17:28:26.59#ibcon#wrote, iclass 36, count 2 2006.285.17:28:26.59#ibcon#about to read 3, iclass 36, count 2 2006.285.17:28:26.62#ibcon#read 3, iclass 36, count 2 2006.285.17:28:26.62#ibcon#about to read 4, iclass 36, count 2 2006.285.17:28:26.62#ibcon#read 4, iclass 36, count 2 2006.285.17:28:26.62#ibcon#about to read 5, iclass 36, count 2 2006.285.17:28:26.62#ibcon#read 5, iclass 36, count 2 2006.285.17:28:26.62#ibcon#about to read 6, iclass 36, count 2 2006.285.17:28:26.62#ibcon#read 6, iclass 36, count 2 2006.285.17:28:26.62#ibcon#end of sib2, iclass 36, count 2 2006.285.17:28:26.62#ibcon#*after write, iclass 36, count 2 2006.285.17:28:26.62#ibcon#*before return 0, iclass 36, count 2 2006.285.17:28:26.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:28:26.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:28:26.62#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.17:28:26.62#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:26.62#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:28:26.74#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:28:26.74#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:28:26.74#ibcon#enter wrdev, iclass 36, count 0 2006.285.17:28:26.74#ibcon#first serial, iclass 36, count 0 2006.285.17:28:26.74#ibcon#enter sib2, iclass 36, count 0 2006.285.17:28:26.74#ibcon#flushed, iclass 36, count 0 2006.285.17:28:26.74#ibcon#about to write, iclass 36, count 0 2006.285.17:28:26.74#ibcon#wrote, iclass 36, count 0 2006.285.17:28:26.74#ibcon#about to read 3, iclass 36, count 0 2006.285.17:28:26.76#ibcon#read 3, iclass 36, count 0 2006.285.17:28:26.76#ibcon#about to read 4, iclass 36, count 0 2006.285.17:28:26.76#ibcon#read 4, iclass 36, count 0 2006.285.17:28:26.76#ibcon#about to read 5, iclass 36, count 0 2006.285.17:28:26.76#ibcon#read 5, iclass 36, count 0 2006.285.17:28:26.76#ibcon#about to read 6, iclass 36, count 0 2006.285.17:28:26.76#ibcon#read 6, iclass 36, count 0 2006.285.17:28:26.76#ibcon#end of sib2, iclass 36, count 0 2006.285.17:28:26.76#ibcon#*mode == 0, iclass 36, count 0 2006.285.17:28:26.76#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.17:28:26.76#ibcon#[25=USB\r\n] 2006.285.17:28:26.76#ibcon#*before write, iclass 36, count 0 2006.285.17:28:26.76#ibcon#enter sib2, iclass 36, count 0 2006.285.17:28:26.76#ibcon#flushed, iclass 36, count 0 2006.285.17:28:26.76#ibcon#about to write, iclass 36, count 0 2006.285.17:28:26.76#ibcon#wrote, iclass 36, count 0 2006.285.17:28:26.76#ibcon#about to read 3, iclass 36, count 0 2006.285.17:28:26.79#ibcon#read 3, iclass 36, count 0 2006.285.17:28:26.79#ibcon#about to read 4, iclass 36, count 0 2006.285.17:28:26.79#ibcon#read 4, iclass 36, count 0 2006.285.17:28:26.79#ibcon#about to read 5, iclass 36, count 0 2006.285.17:28:26.79#ibcon#read 5, iclass 36, count 0 2006.285.17:28:26.79#ibcon#about to read 6, iclass 36, count 0 2006.285.17:28:26.79#ibcon#read 6, iclass 36, count 0 2006.285.17:28:26.79#ibcon#end of sib2, iclass 36, count 0 2006.285.17:28:26.79#ibcon#*after write, iclass 36, count 0 2006.285.17:28:26.79#ibcon#*before return 0, iclass 36, count 0 2006.285.17:28:26.79#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:28:26.79#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:28:26.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.17:28:26.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.17:28:26.79$vck44/valo=4,624.99 2006.285.17:28:26.79#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.17:28:26.79#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.17:28:26.79#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:26.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:28:26.79#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:28:26.79#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:28:26.79#ibcon#enter wrdev, iclass 38, count 0 2006.285.17:28:26.79#ibcon#first serial, iclass 38, count 0 2006.285.17:28:26.79#ibcon#enter sib2, iclass 38, count 0 2006.285.17:28:26.79#ibcon#flushed, iclass 38, count 0 2006.285.17:28:26.79#ibcon#about to write, iclass 38, count 0 2006.285.17:28:26.79#ibcon#wrote, iclass 38, count 0 2006.285.17:28:26.79#ibcon#about to read 3, iclass 38, count 0 2006.285.17:28:26.81#ibcon#read 3, iclass 38, count 0 2006.285.17:28:26.81#ibcon#about to read 4, iclass 38, count 0 2006.285.17:28:26.81#ibcon#read 4, iclass 38, count 0 2006.285.17:28:26.81#ibcon#about to read 5, iclass 38, count 0 2006.285.17:28:26.81#ibcon#read 5, iclass 38, count 0 2006.285.17:28:26.81#ibcon#about to read 6, iclass 38, count 0 2006.285.17:28:26.81#ibcon#read 6, iclass 38, count 0 2006.285.17:28:26.81#ibcon#end of sib2, iclass 38, count 0 2006.285.17:28:26.81#ibcon#*mode == 0, iclass 38, count 0 2006.285.17:28:26.81#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.17:28:26.81#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.17:28:26.81#ibcon#*before write, iclass 38, count 0 2006.285.17:28:26.81#ibcon#enter sib2, iclass 38, count 0 2006.285.17:28:26.81#ibcon#flushed, iclass 38, count 0 2006.285.17:28:26.81#ibcon#about to write, iclass 38, count 0 2006.285.17:28:26.81#ibcon#wrote, iclass 38, count 0 2006.285.17:28:26.81#ibcon#about to read 3, iclass 38, count 0 2006.285.17:28:26.85#ibcon#read 3, iclass 38, count 0 2006.285.17:28:26.85#ibcon#about to read 4, iclass 38, count 0 2006.285.17:28:26.85#ibcon#read 4, iclass 38, count 0 2006.285.17:28:26.85#ibcon#about to read 5, iclass 38, count 0 2006.285.17:28:26.85#ibcon#read 5, iclass 38, count 0 2006.285.17:28:26.85#ibcon#about to read 6, iclass 38, count 0 2006.285.17:28:26.85#ibcon#read 6, iclass 38, count 0 2006.285.17:28:26.85#ibcon#end of sib2, iclass 38, count 0 2006.285.17:28:26.85#ibcon#*after write, iclass 38, count 0 2006.285.17:28:26.85#ibcon#*before return 0, iclass 38, count 0 2006.285.17:28:26.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:28:26.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:28:26.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.17:28:26.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.17:28:26.85$vck44/va=4,6 2006.285.17:28:26.85#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.17:28:26.85#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.17:28:26.85#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:26.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:28:26.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:28:26.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:28:26.91#ibcon#enter wrdev, iclass 40, count 2 2006.285.17:28:26.91#ibcon#first serial, iclass 40, count 2 2006.285.17:28:26.91#ibcon#enter sib2, iclass 40, count 2 2006.285.17:28:26.91#ibcon#flushed, iclass 40, count 2 2006.285.17:28:26.91#ibcon#about to write, iclass 40, count 2 2006.285.17:28:26.91#ibcon#wrote, iclass 40, count 2 2006.285.17:28:26.91#ibcon#about to read 3, iclass 40, count 2 2006.285.17:28:26.93#ibcon#read 3, iclass 40, count 2 2006.285.17:28:26.93#ibcon#about to read 4, iclass 40, count 2 2006.285.17:28:26.93#ibcon#read 4, iclass 40, count 2 2006.285.17:28:26.93#ibcon#about to read 5, iclass 40, count 2 2006.285.17:28:26.93#ibcon#read 5, iclass 40, count 2 2006.285.17:28:26.93#ibcon#about to read 6, iclass 40, count 2 2006.285.17:28:26.93#ibcon#read 6, iclass 40, count 2 2006.285.17:28:26.93#ibcon#end of sib2, iclass 40, count 2 2006.285.17:28:26.93#ibcon#*mode == 0, iclass 40, count 2 2006.285.17:28:26.93#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.17:28:26.93#ibcon#[25=AT04-06\r\n] 2006.285.17:28:26.93#ibcon#*before write, iclass 40, count 2 2006.285.17:28:26.93#ibcon#enter sib2, iclass 40, count 2 2006.285.17:28:26.93#ibcon#flushed, iclass 40, count 2 2006.285.17:28:26.93#ibcon#about to write, iclass 40, count 2 2006.285.17:28:26.93#ibcon#wrote, iclass 40, count 2 2006.285.17:28:26.93#ibcon#about to read 3, iclass 40, count 2 2006.285.17:28:26.96#ibcon#read 3, iclass 40, count 2 2006.285.17:28:27.31#ibcon#about to read 4, iclass 40, count 2 2006.285.17:28:27.31#ibcon#read 4, iclass 40, count 2 2006.285.17:28:27.31#ibcon#about to read 5, iclass 40, count 2 2006.285.17:28:27.31#ibcon#read 5, iclass 40, count 2 2006.285.17:28:27.31#ibcon#about to read 6, iclass 40, count 2 2006.285.17:28:27.31#ibcon#read 6, iclass 40, count 2 2006.285.17:28:27.31#ibcon#end of sib2, iclass 40, count 2 2006.285.17:28:27.31#ibcon#*after write, iclass 40, count 2 2006.285.17:28:27.31#ibcon#*before return 0, iclass 40, count 2 2006.285.17:28:27.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:28:27.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:28:27.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.17:28:27.31#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:27.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:28:27.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:28:27.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:28:27.43#ibcon#enter wrdev, iclass 40, count 0 2006.285.17:28:27.43#ibcon#first serial, iclass 40, count 0 2006.285.17:28:27.43#ibcon#enter sib2, iclass 40, count 0 2006.285.17:28:27.43#ibcon#flushed, iclass 40, count 0 2006.285.17:28:27.43#ibcon#about to write, iclass 40, count 0 2006.285.17:28:27.43#ibcon#wrote, iclass 40, count 0 2006.285.17:28:27.43#ibcon#about to read 3, iclass 40, count 0 2006.285.17:28:27.45#ibcon#read 3, iclass 40, count 0 2006.285.17:28:27.45#ibcon#about to read 4, iclass 40, count 0 2006.285.17:28:27.45#ibcon#read 4, iclass 40, count 0 2006.285.17:28:27.45#ibcon#about to read 5, iclass 40, count 0 2006.285.17:28:27.45#ibcon#read 5, iclass 40, count 0 2006.285.17:28:27.45#ibcon#about to read 6, iclass 40, count 0 2006.285.17:28:27.45#ibcon#read 6, iclass 40, count 0 2006.285.17:28:27.45#ibcon#end of sib2, iclass 40, count 0 2006.285.17:28:27.45#ibcon#*mode == 0, iclass 40, count 0 2006.285.17:28:27.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.17:28:27.45#ibcon#[25=USB\r\n] 2006.285.17:28:27.45#ibcon#*before write, iclass 40, count 0 2006.285.17:28:27.45#ibcon#enter sib2, iclass 40, count 0 2006.285.17:28:27.45#ibcon#flushed, iclass 40, count 0 2006.285.17:28:27.45#ibcon#about to write, iclass 40, count 0 2006.285.17:28:27.45#ibcon#wrote, iclass 40, count 0 2006.285.17:28:27.45#ibcon#about to read 3, iclass 40, count 0 2006.285.17:28:27.48#ibcon#read 3, iclass 40, count 0 2006.285.17:28:27.48#ibcon#about to read 4, iclass 40, count 0 2006.285.17:28:27.48#ibcon#read 4, iclass 40, count 0 2006.285.17:28:27.48#ibcon#about to read 5, iclass 40, count 0 2006.285.17:28:27.48#ibcon#read 5, iclass 40, count 0 2006.285.17:28:27.48#ibcon#about to read 6, iclass 40, count 0 2006.285.17:28:27.48#ibcon#read 6, iclass 40, count 0 2006.285.17:28:27.48#ibcon#end of sib2, iclass 40, count 0 2006.285.17:28:27.48#ibcon#*after write, iclass 40, count 0 2006.285.17:28:27.48#ibcon#*before return 0, iclass 40, count 0 2006.285.17:28:27.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:28:27.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:28:27.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.17:28:27.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.17:28:27.48$vck44/valo=5,734.99 2006.285.17:28:27.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.17:28:27.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.17:28:27.48#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:27.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:28:27.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:28:27.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:28:27.48#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:28:27.48#ibcon#first serial, iclass 4, count 0 2006.285.17:28:27.48#ibcon#enter sib2, iclass 4, count 0 2006.285.17:28:27.48#ibcon#flushed, iclass 4, count 0 2006.285.17:28:27.48#ibcon#about to write, iclass 4, count 0 2006.285.17:28:27.48#ibcon#wrote, iclass 4, count 0 2006.285.17:28:27.48#ibcon#about to read 3, iclass 4, count 0 2006.285.17:28:27.50#ibcon#read 3, iclass 4, count 0 2006.285.17:28:27.50#ibcon#about to read 4, iclass 4, count 0 2006.285.17:28:27.50#ibcon#read 4, iclass 4, count 0 2006.285.17:28:27.50#ibcon#about to read 5, iclass 4, count 0 2006.285.17:28:27.50#ibcon#read 5, iclass 4, count 0 2006.285.17:28:27.50#ibcon#about to read 6, iclass 4, count 0 2006.285.17:28:27.50#ibcon#read 6, iclass 4, count 0 2006.285.17:28:27.50#ibcon#end of sib2, iclass 4, count 0 2006.285.17:28:27.50#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:28:27.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:28:27.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.17:28:27.50#ibcon#*before write, iclass 4, count 0 2006.285.17:28:27.50#ibcon#enter sib2, iclass 4, count 0 2006.285.17:28:27.50#ibcon#flushed, iclass 4, count 0 2006.285.17:28:27.50#ibcon#about to write, iclass 4, count 0 2006.285.17:28:27.50#ibcon#wrote, iclass 4, count 0 2006.285.17:28:27.50#ibcon#about to read 3, iclass 4, count 0 2006.285.17:28:27.54#ibcon#read 3, iclass 4, count 0 2006.285.17:28:27.54#ibcon#about to read 4, iclass 4, count 0 2006.285.17:28:27.54#ibcon#read 4, iclass 4, count 0 2006.285.17:28:27.54#ibcon#about to read 5, iclass 4, count 0 2006.285.17:28:27.54#ibcon#read 5, iclass 4, count 0 2006.285.17:28:27.54#ibcon#about to read 6, iclass 4, count 0 2006.285.17:28:27.54#ibcon#read 6, iclass 4, count 0 2006.285.17:28:27.54#ibcon#end of sib2, iclass 4, count 0 2006.285.17:28:27.54#ibcon#*after write, iclass 4, count 0 2006.285.17:28:27.54#ibcon#*before return 0, iclass 4, count 0 2006.285.17:28:27.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:28:27.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:28:27.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:28:27.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:28:27.54$vck44/va=5,3 2006.285.17:28:27.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.17:28:27.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.17:28:27.54#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:27.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:28:27.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:28:27.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:28:27.60#ibcon#enter wrdev, iclass 6, count 2 2006.285.17:28:27.60#ibcon#first serial, iclass 6, count 2 2006.285.17:28:27.60#ibcon#enter sib2, iclass 6, count 2 2006.285.17:28:27.60#ibcon#flushed, iclass 6, count 2 2006.285.17:28:27.60#ibcon#about to write, iclass 6, count 2 2006.285.17:28:27.60#ibcon#wrote, iclass 6, count 2 2006.285.17:28:27.60#ibcon#about to read 3, iclass 6, count 2 2006.285.17:28:27.62#ibcon#read 3, iclass 6, count 2 2006.285.17:28:27.62#ibcon#about to read 4, iclass 6, count 2 2006.285.17:28:27.62#ibcon#read 4, iclass 6, count 2 2006.285.17:28:27.62#ibcon#about to read 5, iclass 6, count 2 2006.285.17:28:27.62#ibcon#read 5, iclass 6, count 2 2006.285.17:28:27.62#ibcon#about to read 6, iclass 6, count 2 2006.285.17:28:27.62#ibcon#read 6, iclass 6, count 2 2006.285.17:28:27.62#ibcon#end of sib2, iclass 6, count 2 2006.285.17:28:27.62#ibcon#*mode == 0, iclass 6, count 2 2006.285.17:28:27.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.17:28:27.62#ibcon#[25=AT05-03\r\n] 2006.285.17:28:27.62#ibcon#*before write, iclass 6, count 2 2006.285.17:28:27.62#ibcon#enter sib2, iclass 6, count 2 2006.285.17:28:27.62#ibcon#flushed, iclass 6, count 2 2006.285.17:28:27.62#ibcon#about to write, iclass 6, count 2 2006.285.17:28:27.62#ibcon#wrote, iclass 6, count 2 2006.285.17:28:27.62#ibcon#about to read 3, iclass 6, count 2 2006.285.17:28:27.65#ibcon#read 3, iclass 6, count 2 2006.285.17:28:27.65#ibcon#about to read 4, iclass 6, count 2 2006.285.17:28:27.65#ibcon#read 4, iclass 6, count 2 2006.285.17:28:27.65#ibcon#about to read 5, iclass 6, count 2 2006.285.17:28:27.65#ibcon#read 5, iclass 6, count 2 2006.285.17:28:27.65#ibcon#about to read 6, iclass 6, count 2 2006.285.17:28:27.65#ibcon#read 6, iclass 6, count 2 2006.285.17:28:27.65#ibcon#end of sib2, iclass 6, count 2 2006.285.17:28:27.65#ibcon#*after write, iclass 6, count 2 2006.285.17:28:27.65#ibcon#*before return 0, iclass 6, count 2 2006.285.17:28:27.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:28:27.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:28:27.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.17:28:27.65#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:27.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:28:27.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:28:27.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:28:27.77#ibcon#enter wrdev, iclass 6, count 0 2006.285.17:28:27.77#ibcon#first serial, iclass 6, count 0 2006.285.17:28:27.77#ibcon#enter sib2, iclass 6, count 0 2006.285.17:28:27.77#ibcon#flushed, iclass 6, count 0 2006.285.17:28:27.77#ibcon#about to write, iclass 6, count 0 2006.285.17:28:27.77#ibcon#wrote, iclass 6, count 0 2006.285.17:28:27.77#ibcon#about to read 3, iclass 6, count 0 2006.285.17:28:27.79#ibcon#read 3, iclass 6, count 0 2006.285.17:28:28.05#ibcon#about to read 4, iclass 6, count 0 2006.285.17:28:28.05#ibcon#read 4, iclass 6, count 0 2006.285.17:28:28.05#ibcon#about to read 5, iclass 6, count 0 2006.285.17:28:28.05#ibcon#read 5, iclass 6, count 0 2006.285.17:28:28.05#ibcon#about to read 6, iclass 6, count 0 2006.285.17:28:28.05#ibcon#read 6, iclass 6, count 0 2006.285.17:28:28.05#ibcon#end of sib2, iclass 6, count 0 2006.285.17:28:28.05#ibcon#*mode == 0, iclass 6, count 0 2006.285.17:28:28.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.17:28:28.05#ibcon#[25=USB\r\n] 2006.285.17:28:28.05#ibcon#*before write, iclass 6, count 0 2006.285.17:28:28.05#ibcon#enter sib2, iclass 6, count 0 2006.285.17:28:28.05#ibcon#flushed, iclass 6, count 0 2006.285.17:28:28.05#ibcon#about to write, iclass 6, count 0 2006.285.17:28:28.05#ibcon#wrote, iclass 6, count 0 2006.285.17:28:28.05#ibcon#about to read 3, iclass 6, count 0 2006.285.17:28:28.08#ibcon#read 3, iclass 6, count 0 2006.285.17:28:28.08#ibcon#about to read 4, iclass 6, count 0 2006.285.17:28:28.08#ibcon#read 4, iclass 6, count 0 2006.285.17:28:28.08#ibcon#about to read 5, iclass 6, count 0 2006.285.17:28:28.08#ibcon#read 5, iclass 6, count 0 2006.285.17:28:28.08#ibcon#about to read 6, iclass 6, count 0 2006.285.17:28:28.08#ibcon#read 6, iclass 6, count 0 2006.285.17:28:28.08#ibcon#end of sib2, iclass 6, count 0 2006.285.17:28:28.08#ibcon#*after write, iclass 6, count 0 2006.285.17:28:28.08#ibcon#*before return 0, iclass 6, count 0 2006.285.17:28:28.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:28:28.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:28:28.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.17:28:28.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.17:28:28.08$vck44/valo=6,814.99 2006.285.17:28:28.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.17:28:28.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.17:28:28.08#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:28.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:28:28.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:28:28.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:28:28.08#ibcon#enter wrdev, iclass 10, count 0 2006.285.17:28:28.08#ibcon#first serial, iclass 10, count 0 2006.285.17:28:28.08#ibcon#enter sib2, iclass 10, count 0 2006.285.17:28:28.08#ibcon#flushed, iclass 10, count 0 2006.285.17:28:28.08#ibcon#about to write, iclass 10, count 0 2006.285.17:28:28.08#ibcon#wrote, iclass 10, count 0 2006.285.17:28:28.08#ibcon#about to read 3, iclass 10, count 0 2006.285.17:28:28.10#ibcon#read 3, iclass 10, count 0 2006.285.17:28:28.10#ibcon#about to read 4, iclass 10, count 0 2006.285.17:28:28.10#ibcon#read 4, iclass 10, count 0 2006.285.17:28:28.10#ibcon#about to read 5, iclass 10, count 0 2006.285.17:28:28.10#ibcon#read 5, iclass 10, count 0 2006.285.17:28:28.10#ibcon#about to read 6, iclass 10, count 0 2006.285.17:28:28.10#ibcon#read 6, iclass 10, count 0 2006.285.17:28:28.10#ibcon#end of sib2, iclass 10, count 0 2006.285.17:28:28.10#ibcon#*mode == 0, iclass 10, count 0 2006.285.17:28:28.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.17:28:28.10#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.17:28:28.10#ibcon#*before write, iclass 10, count 0 2006.285.17:28:28.10#ibcon#enter sib2, iclass 10, count 0 2006.285.17:28:28.10#ibcon#flushed, iclass 10, count 0 2006.285.17:28:28.10#ibcon#about to write, iclass 10, count 0 2006.285.17:28:28.10#ibcon#wrote, iclass 10, count 0 2006.285.17:28:28.10#ibcon#about to read 3, iclass 10, count 0 2006.285.17:28:28.13#abcon#<5=/00 0.2 1.0 16.87 981014.8\r\n> 2006.285.17:28:28.14#ibcon#read 3, iclass 10, count 0 2006.285.17:28:28.14#ibcon#about to read 4, iclass 10, count 0 2006.285.17:28:28.14#ibcon#read 4, iclass 10, count 0 2006.285.17:28:28.14#ibcon#about to read 5, iclass 10, count 0 2006.285.17:28:28.14#ibcon#read 5, iclass 10, count 0 2006.285.17:28:28.14#ibcon#about to read 6, iclass 10, count 0 2006.285.17:28:28.14#ibcon#read 6, iclass 10, count 0 2006.285.17:28:28.14#ibcon#end of sib2, iclass 10, count 0 2006.285.17:28:28.14#ibcon#*after write, iclass 10, count 0 2006.285.17:28:28.14#ibcon#*before return 0, iclass 10, count 0 2006.285.17:28:28.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:28:28.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:28:28.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.17:28:28.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.17:28:28.14$vck44/va=6,4 2006.285.17:28:28.14#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.17:28:28.14#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.17:28:28.14#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:28.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:28:28.15#abcon#{5=INTERFACE CLEAR} 2006.285.17:28:28.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:28:28.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:28:28.20#ibcon#enter wrdev, iclass 15, count 2 2006.285.17:28:28.20#ibcon#first serial, iclass 15, count 2 2006.285.17:28:28.20#ibcon#enter sib2, iclass 15, count 2 2006.285.17:28:28.20#ibcon#flushed, iclass 15, count 2 2006.285.17:28:28.20#ibcon#about to write, iclass 15, count 2 2006.285.17:28:28.20#ibcon#wrote, iclass 15, count 2 2006.285.17:28:28.20#ibcon#about to read 3, iclass 15, count 2 2006.285.17:28:28.21#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:28:28.22#ibcon#read 3, iclass 15, count 2 2006.285.17:28:28.22#ibcon#about to read 4, iclass 15, count 2 2006.285.17:28:28.22#ibcon#read 4, iclass 15, count 2 2006.285.17:28:28.22#ibcon#about to read 5, iclass 15, count 2 2006.285.17:28:28.22#ibcon#read 5, iclass 15, count 2 2006.285.17:28:28.22#ibcon#about to read 6, iclass 15, count 2 2006.285.17:28:28.22#ibcon#read 6, iclass 15, count 2 2006.285.17:28:28.22#ibcon#end of sib2, iclass 15, count 2 2006.285.17:28:28.22#ibcon#*mode == 0, iclass 15, count 2 2006.285.17:28:28.22#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.17:28:28.22#ibcon#[25=AT06-04\r\n] 2006.285.17:28:28.22#ibcon#*before write, iclass 15, count 2 2006.285.17:28:28.22#ibcon#enter sib2, iclass 15, count 2 2006.285.17:28:28.22#ibcon#flushed, iclass 15, count 2 2006.285.17:28:28.22#ibcon#about to write, iclass 15, count 2 2006.285.17:28:28.22#ibcon#wrote, iclass 15, count 2 2006.285.17:28:28.22#ibcon#about to read 3, iclass 15, count 2 2006.285.17:28:28.25#ibcon#read 3, iclass 15, count 2 2006.285.17:28:28.25#ibcon#about to read 4, iclass 15, count 2 2006.285.17:28:28.25#ibcon#read 4, iclass 15, count 2 2006.285.17:28:28.25#ibcon#about to read 5, iclass 15, count 2 2006.285.17:28:28.25#ibcon#read 5, iclass 15, count 2 2006.285.17:28:28.25#ibcon#about to read 6, iclass 15, count 2 2006.285.17:28:28.25#ibcon#read 6, iclass 15, count 2 2006.285.17:28:28.25#ibcon#end of sib2, iclass 15, count 2 2006.285.17:28:28.25#ibcon#*after write, iclass 15, count 2 2006.285.17:28:28.25#ibcon#*before return 0, iclass 15, count 2 2006.285.17:28:28.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:28:28.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:28:28.25#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.17:28:28.25#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:28.25#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:28:28.37#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:28:28.37#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:28:28.37#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:28:28.37#ibcon#first serial, iclass 15, count 0 2006.285.17:28:28.37#ibcon#enter sib2, iclass 15, count 0 2006.285.17:28:28.37#ibcon#flushed, iclass 15, count 0 2006.285.17:28:28.37#ibcon#about to write, iclass 15, count 0 2006.285.17:28:28.37#ibcon#wrote, iclass 15, count 0 2006.285.17:28:28.37#ibcon#about to read 3, iclass 15, count 0 2006.285.17:28:28.39#ibcon#read 3, iclass 15, count 0 2006.285.17:28:28.39#ibcon#about to read 4, iclass 15, count 0 2006.285.17:28:28.39#ibcon#read 4, iclass 15, count 0 2006.285.17:28:28.39#ibcon#about to read 5, iclass 15, count 0 2006.285.17:28:28.39#ibcon#read 5, iclass 15, count 0 2006.285.17:28:28.39#ibcon#about to read 6, iclass 15, count 0 2006.285.17:28:28.39#ibcon#read 6, iclass 15, count 0 2006.285.17:28:28.39#ibcon#end of sib2, iclass 15, count 0 2006.285.17:28:28.39#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:28:28.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:28:28.39#ibcon#[25=USB\r\n] 2006.285.17:28:28.39#ibcon#*before write, iclass 15, count 0 2006.285.17:28:28.39#ibcon#enter sib2, iclass 15, count 0 2006.285.17:28:28.39#ibcon#flushed, iclass 15, count 0 2006.285.17:28:28.39#ibcon#about to write, iclass 15, count 0 2006.285.17:28:28.39#ibcon#wrote, iclass 15, count 0 2006.285.17:28:28.39#ibcon#about to read 3, iclass 15, count 0 2006.285.17:28:28.42#ibcon#read 3, iclass 15, count 0 2006.285.17:28:28.42#ibcon#about to read 4, iclass 15, count 0 2006.285.17:28:28.42#ibcon#read 4, iclass 15, count 0 2006.285.17:28:28.42#ibcon#about to read 5, iclass 15, count 0 2006.285.17:28:28.42#ibcon#read 5, iclass 15, count 0 2006.285.17:28:28.42#ibcon#about to read 6, iclass 15, count 0 2006.285.17:28:28.42#ibcon#read 6, iclass 15, count 0 2006.285.17:28:28.42#ibcon#end of sib2, iclass 15, count 0 2006.285.17:28:28.42#ibcon#*after write, iclass 15, count 0 2006.285.17:28:28.42#ibcon#*before return 0, iclass 15, count 0 2006.285.17:28:28.42#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:28:28.42#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:28:28.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:28:28.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:28:28.42$vck44/valo=7,864.99 2006.285.17:28:28.42#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.17:28:28.42#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.17:28:28.42#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:28.42#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:28:28.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:28:28.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:28:28.42#ibcon#enter wrdev, iclass 18, count 0 2006.285.17:28:28.42#ibcon#first serial, iclass 18, count 0 2006.285.17:28:28.42#ibcon#enter sib2, iclass 18, count 0 2006.285.17:28:28.42#ibcon#flushed, iclass 18, count 0 2006.285.17:28:28.42#ibcon#about to write, iclass 18, count 0 2006.285.17:28:28.42#ibcon#wrote, iclass 18, count 0 2006.285.17:28:28.42#ibcon#about to read 3, iclass 18, count 0 2006.285.17:28:28.44#ibcon#read 3, iclass 18, count 0 2006.285.17:28:28.44#ibcon#about to read 4, iclass 18, count 0 2006.285.17:28:28.44#ibcon#read 4, iclass 18, count 0 2006.285.17:28:28.44#ibcon#about to read 5, iclass 18, count 0 2006.285.17:28:28.44#ibcon#read 5, iclass 18, count 0 2006.285.17:28:28.44#ibcon#about to read 6, iclass 18, count 0 2006.285.17:28:28.44#ibcon#read 6, iclass 18, count 0 2006.285.17:28:28.44#ibcon#end of sib2, iclass 18, count 0 2006.285.17:28:28.44#ibcon#*mode == 0, iclass 18, count 0 2006.285.17:28:28.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.17:28:28.44#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.17:28:28.44#ibcon#*before write, iclass 18, count 0 2006.285.17:28:28.44#ibcon#enter sib2, iclass 18, count 0 2006.285.17:28:28.44#ibcon#flushed, iclass 18, count 0 2006.285.17:28:28.44#ibcon#about to write, iclass 18, count 0 2006.285.17:28:28.44#ibcon#wrote, iclass 18, count 0 2006.285.17:28:28.44#ibcon#about to read 3, iclass 18, count 0 2006.285.17:28:28.48#ibcon#read 3, iclass 18, count 0 2006.285.17:28:28.48#ibcon#about to read 4, iclass 18, count 0 2006.285.17:28:28.48#ibcon#read 4, iclass 18, count 0 2006.285.17:28:28.48#ibcon#about to read 5, iclass 18, count 0 2006.285.17:28:28.48#ibcon#read 5, iclass 18, count 0 2006.285.17:28:28.48#ibcon#about to read 6, iclass 18, count 0 2006.285.17:28:28.48#ibcon#read 6, iclass 18, count 0 2006.285.17:28:28.48#ibcon#end of sib2, iclass 18, count 0 2006.285.17:28:28.48#ibcon#*after write, iclass 18, count 0 2006.285.17:28:28.48#ibcon#*before return 0, iclass 18, count 0 2006.285.17:28:28.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:28:28.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:28:28.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.17:28:28.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.17:28:28.48$vck44/va=7,4 2006.285.17:28:28.48#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.17:28:28.48#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.17:28:28.48#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:28.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:28:28.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:28:28.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:28:28.54#ibcon#enter wrdev, iclass 20, count 2 2006.285.17:28:28.54#ibcon#first serial, iclass 20, count 2 2006.285.17:28:28.54#ibcon#enter sib2, iclass 20, count 2 2006.285.17:28:28.54#ibcon#flushed, iclass 20, count 2 2006.285.17:28:28.54#ibcon#about to write, iclass 20, count 2 2006.285.17:28:28.54#ibcon#wrote, iclass 20, count 2 2006.285.17:28:28.54#ibcon#about to read 3, iclass 20, count 2 2006.285.17:28:28.56#ibcon#read 3, iclass 20, count 2 2006.285.17:28:28.56#ibcon#about to read 4, iclass 20, count 2 2006.285.17:28:28.56#ibcon#read 4, iclass 20, count 2 2006.285.17:28:28.56#ibcon#about to read 5, iclass 20, count 2 2006.285.17:28:28.56#ibcon#read 5, iclass 20, count 2 2006.285.17:28:28.56#ibcon#about to read 6, iclass 20, count 2 2006.285.17:28:28.56#ibcon#read 6, iclass 20, count 2 2006.285.17:28:28.56#ibcon#end of sib2, iclass 20, count 2 2006.285.17:28:28.56#ibcon#*mode == 0, iclass 20, count 2 2006.285.17:28:28.56#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.17:28:28.56#ibcon#[25=AT07-04\r\n] 2006.285.17:28:28.56#ibcon#*before write, iclass 20, count 2 2006.285.17:28:28.56#ibcon#enter sib2, iclass 20, count 2 2006.285.17:28:28.56#ibcon#flushed, iclass 20, count 2 2006.285.17:28:28.56#ibcon#about to write, iclass 20, count 2 2006.285.17:28:28.56#ibcon#wrote, iclass 20, count 2 2006.285.17:28:28.56#ibcon#about to read 3, iclass 20, count 2 2006.285.17:28:28.59#ibcon#read 3, iclass 20, count 2 2006.285.17:28:28.59#ibcon#about to read 4, iclass 20, count 2 2006.285.17:28:28.59#ibcon#read 4, iclass 20, count 2 2006.285.17:28:28.59#ibcon#about to read 5, iclass 20, count 2 2006.285.17:28:28.59#ibcon#read 5, iclass 20, count 2 2006.285.17:28:28.59#ibcon#about to read 6, iclass 20, count 2 2006.285.17:28:28.59#ibcon#read 6, iclass 20, count 2 2006.285.17:28:28.59#ibcon#end of sib2, iclass 20, count 2 2006.285.17:28:28.59#ibcon#*after write, iclass 20, count 2 2006.285.17:28:28.59#ibcon#*before return 0, iclass 20, count 2 2006.285.17:28:28.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:28:28.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:28:28.59#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.17:28:28.59#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:28.59#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:28:28.71#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:28:28.71#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:28:28.71#ibcon#enter wrdev, iclass 20, count 0 2006.285.17:28:28.71#ibcon#first serial, iclass 20, count 0 2006.285.17:28:28.71#ibcon#enter sib2, iclass 20, count 0 2006.285.17:28:28.71#ibcon#flushed, iclass 20, count 0 2006.285.17:28:28.71#ibcon#about to write, iclass 20, count 0 2006.285.17:28:28.71#ibcon#wrote, iclass 20, count 0 2006.285.17:28:28.71#ibcon#about to read 3, iclass 20, count 0 2006.285.17:28:28.73#ibcon#read 3, iclass 20, count 0 2006.285.17:28:28.73#ibcon#about to read 4, iclass 20, count 0 2006.285.17:28:28.73#ibcon#read 4, iclass 20, count 0 2006.285.17:28:28.73#ibcon#about to read 5, iclass 20, count 0 2006.285.17:28:28.73#ibcon#read 5, iclass 20, count 0 2006.285.17:28:28.73#ibcon#about to read 6, iclass 20, count 0 2006.285.17:28:28.73#ibcon#read 6, iclass 20, count 0 2006.285.17:28:28.73#ibcon#end of sib2, iclass 20, count 0 2006.285.17:28:28.73#ibcon#*mode == 0, iclass 20, count 0 2006.285.17:28:28.73#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.17:28:28.73#ibcon#[25=USB\r\n] 2006.285.17:28:28.73#ibcon#*before write, iclass 20, count 0 2006.285.17:28:28.73#ibcon#enter sib2, iclass 20, count 0 2006.285.17:28:28.73#ibcon#flushed, iclass 20, count 0 2006.285.17:28:28.73#ibcon#about to write, iclass 20, count 0 2006.285.17:28:28.73#ibcon#wrote, iclass 20, count 0 2006.285.17:28:28.73#ibcon#about to read 3, iclass 20, count 0 2006.285.17:28:28.76#ibcon#read 3, iclass 20, count 0 2006.285.17:28:28.76#ibcon#about to read 4, iclass 20, count 0 2006.285.17:28:28.76#ibcon#read 4, iclass 20, count 0 2006.285.17:28:28.76#ibcon#about to read 5, iclass 20, count 0 2006.285.17:28:28.76#ibcon#read 5, iclass 20, count 0 2006.285.17:28:28.76#ibcon#about to read 6, iclass 20, count 0 2006.285.17:28:28.76#ibcon#read 6, iclass 20, count 0 2006.285.17:28:28.76#ibcon#end of sib2, iclass 20, count 0 2006.285.17:28:28.76#ibcon#*after write, iclass 20, count 0 2006.285.17:28:28.76#ibcon#*before return 0, iclass 20, count 0 2006.285.17:28:28.76#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:28:28.76#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:28:28.76#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.17:28:28.76#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.17:28:28.76$vck44/valo=8,884.99 2006.285.17:28:28.76#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.17:28:28.76#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.17:28:28.76#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:28.76#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:28:28.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:28:28.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:28:28.76#ibcon#enter wrdev, iclass 22, count 0 2006.285.17:28:28.76#ibcon#first serial, iclass 22, count 0 2006.285.17:28:28.76#ibcon#enter sib2, iclass 22, count 0 2006.285.17:28:28.76#ibcon#flushed, iclass 22, count 0 2006.285.17:28:28.76#ibcon#about to write, iclass 22, count 0 2006.285.17:28:28.76#ibcon#wrote, iclass 22, count 0 2006.285.17:28:28.76#ibcon#about to read 3, iclass 22, count 0 2006.285.17:28:28.78#ibcon#read 3, iclass 22, count 0 2006.285.17:28:28.78#ibcon#about to read 4, iclass 22, count 0 2006.285.17:28:28.78#ibcon#read 4, iclass 22, count 0 2006.285.17:28:28.78#ibcon#about to read 5, iclass 22, count 0 2006.285.17:28:28.78#ibcon#read 5, iclass 22, count 0 2006.285.17:28:28.78#ibcon#about to read 6, iclass 22, count 0 2006.285.17:28:28.78#ibcon#read 6, iclass 22, count 0 2006.285.17:28:28.78#ibcon#end of sib2, iclass 22, count 0 2006.285.17:28:28.78#ibcon#*mode == 0, iclass 22, count 0 2006.285.17:28:28.78#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.17:28:28.78#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.17:28:28.78#ibcon#*before write, iclass 22, count 0 2006.285.17:28:28.78#ibcon#enter sib2, iclass 22, count 0 2006.285.17:28:28.78#ibcon#flushed, iclass 22, count 0 2006.285.17:28:28.78#ibcon#about to write, iclass 22, count 0 2006.285.17:28:28.78#ibcon#wrote, iclass 22, count 0 2006.285.17:28:28.78#ibcon#about to read 3, iclass 22, count 0 2006.285.17:28:28.82#ibcon#read 3, iclass 22, count 0 2006.285.17:28:28.82#ibcon#about to read 4, iclass 22, count 0 2006.285.17:28:28.82#ibcon#read 4, iclass 22, count 0 2006.285.17:28:28.82#ibcon#about to read 5, iclass 22, count 0 2006.285.17:28:28.82#ibcon#read 5, iclass 22, count 0 2006.285.17:28:28.82#ibcon#about to read 6, iclass 22, count 0 2006.285.17:28:28.82#ibcon#read 6, iclass 22, count 0 2006.285.17:28:28.82#ibcon#end of sib2, iclass 22, count 0 2006.285.17:28:28.82#ibcon#*after write, iclass 22, count 0 2006.285.17:28:28.82#ibcon#*before return 0, iclass 22, count 0 2006.285.17:28:28.82#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:28:28.82#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:28:28.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.17:28:28.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.17:28:28.82$vck44/va=8,3 2006.285.17:28:28.82#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.17:28:28.82#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.17:28:28.82#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:28.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:28:28.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:28:28.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:28:28.88#ibcon#enter wrdev, iclass 24, count 2 2006.285.17:28:28.88#ibcon#first serial, iclass 24, count 2 2006.285.17:28:28.88#ibcon#enter sib2, iclass 24, count 2 2006.285.17:28:28.88#ibcon#flushed, iclass 24, count 2 2006.285.17:28:28.88#ibcon#about to write, iclass 24, count 2 2006.285.17:28:28.88#ibcon#wrote, iclass 24, count 2 2006.285.17:28:28.88#ibcon#about to read 3, iclass 24, count 2 2006.285.17:28:28.90#ibcon#read 3, iclass 24, count 2 2006.285.17:28:28.90#ibcon#about to read 4, iclass 24, count 2 2006.285.17:28:28.90#ibcon#read 4, iclass 24, count 2 2006.285.17:28:28.90#ibcon#about to read 5, iclass 24, count 2 2006.285.17:28:28.90#ibcon#read 5, iclass 24, count 2 2006.285.17:28:28.90#ibcon#about to read 6, iclass 24, count 2 2006.285.17:28:28.90#ibcon#read 6, iclass 24, count 2 2006.285.17:28:28.90#ibcon#end of sib2, iclass 24, count 2 2006.285.17:28:28.90#ibcon#*mode == 0, iclass 24, count 2 2006.285.17:28:28.90#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.17:28:28.90#ibcon#[25=AT08-03\r\n] 2006.285.17:28:28.90#ibcon#*before write, iclass 24, count 2 2006.285.17:28:28.90#ibcon#enter sib2, iclass 24, count 2 2006.285.17:28:28.90#ibcon#flushed, iclass 24, count 2 2006.285.17:28:28.90#ibcon#about to write, iclass 24, count 2 2006.285.17:28:28.90#ibcon#wrote, iclass 24, count 2 2006.285.17:28:28.90#ibcon#about to read 3, iclass 24, count 2 2006.285.17:28:28.93#ibcon#read 3, iclass 24, count 2 2006.285.17:28:28.93#ibcon#about to read 4, iclass 24, count 2 2006.285.17:28:28.93#ibcon#read 4, iclass 24, count 2 2006.285.17:28:28.93#ibcon#about to read 5, iclass 24, count 2 2006.285.17:28:28.93#ibcon#read 5, iclass 24, count 2 2006.285.17:28:28.93#ibcon#about to read 6, iclass 24, count 2 2006.285.17:28:28.93#ibcon#read 6, iclass 24, count 2 2006.285.17:28:28.93#ibcon#end of sib2, iclass 24, count 2 2006.285.17:28:28.93#ibcon#*after write, iclass 24, count 2 2006.285.17:28:28.93#ibcon#*before return 0, iclass 24, count 2 2006.285.17:28:28.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:28:28.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:28:28.93#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.17:28:28.93#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:28.93#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:28:29.05#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:28:29.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:28:29.15#ibcon#enter wrdev, iclass 24, count 0 2006.285.17:28:29.15#ibcon#first serial, iclass 24, count 0 2006.285.17:28:29.15#ibcon#enter sib2, iclass 24, count 0 2006.285.17:28:29.15#ibcon#flushed, iclass 24, count 0 2006.285.17:28:29.15#ibcon#about to write, iclass 24, count 0 2006.285.17:28:29.15#ibcon#wrote, iclass 24, count 0 2006.285.17:28:29.15#ibcon#about to read 3, iclass 24, count 0 2006.285.17:28:29.17#ibcon#read 3, iclass 24, count 0 2006.285.17:28:29.17#ibcon#about to read 4, iclass 24, count 0 2006.285.17:28:29.17#ibcon#read 4, iclass 24, count 0 2006.285.17:28:29.17#ibcon#about to read 5, iclass 24, count 0 2006.285.17:28:29.17#ibcon#read 5, iclass 24, count 0 2006.285.17:28:29.17#ibcon#about to read 6, iclass 24, count 0 2006.285.17:28:29.17#ibcon#read 6, iclass 24, count 0 2006.285.17:28:29.17#ibcon#end of sib2, iclass 24, count 0 2006.285.17:28:29.17#ibcon#*mode == 0, iclass 24, count 0 2006.285.17:28:29.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.17:28:29.17#ibcon#[25=USB\r\n] 2006.285.17:28:29.17#ibcon#*before write, iclass 24, count 0 2006.285.17:28:29.17#ibcon#enter sib2, iclass 24, count 0 2006.285.17:28:29.17#ibcon#flushed, iclass 24, count 0 2006.285.17:28:29.17#ibcon#about to write, iclass 24, count 0 2006.285.17:28:29.17#ibcon#wrote, iclass 24, count 0 2006.285.17:28:29.17#ibcon#about to read 3, iclass 24, count 0 2006.285.17:28:29.20#ibcon#read 3, iclass 24, count 0 2006.285.17:28:29.20#ibcon#about to read 4, iclass 24, count 0 2006.285.17:28:29.20#ibcon#read 4, iclass 24, count 0 2006.285.17:28:29.20#ibcon#about to read 5, iclass 24, count 0 2006.285.17:28:29.20#ibcon#read 5, iclass 24, count 0 2006.285.17:28:29.20#ibcon#about to read 6, iclass 24, count 0 2006.285.17:28:29.20#ibcon#read 6, iclass 24, count 0 2006.285.17:28:29.20#ibcon#end of sib2, iclass 24, count 0 2006.285.17:28:29.20#ibcon#*after write, iclass 24, count 0 2006.285.17:28:29.20#ibcon#*before return 0, iclass 24, count 0 2006.285.17:28:29.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:28:29.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:28:29.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.17:28:29.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.17:28:29.20$vck44/vblo=1,629.99 2006.285.17:28:29.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.17:28:29.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.17:28:29.20#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:29.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:28:29.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:28:29.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:28:29.20#ibcon#enter wrdev, iclass 26, count 0 2006.285.17:28:29.20#ibcon#first serial, iclass 26, count 0 2006.285.17:28:29.20#ibcon#enter sib2, iclass 26, count 0 2006.285.17:28:29.20#ibcon#flushed, iclass 26, count 0 2006.285.17:28:29.20#ibcon#about to write, iclass 26, count 0 2006.285.17:28:29.20#ibcon#wrote, iclass 26, count 0 2006.285.17:28:29.20#ibcon#about to read 3, iclass 26, count 0 2006.285.17:28:29.22#ibcon#read 3, iclass 26, count 0 2006.285.17:28:29.22#ibcon#about to read 4, iclass 26, count 0 2006.285.17:28:29.22#ibcon#read 4, iclass 26, count 0 2006.285.17:28:29.22#ibcon#about to read 5, iclass 26, count 0 2006.285.17:28:29.22#ibcon#read 5, iclass 26, count 0 2006.285.17:28:29.22#ibcon#about to read 6, iclass 26, count 0 2006.285.17:28:29.22#ibcon#read 6, iclass 26, count 0 2006.285.17:28:29.22#ibcon#end of sib2, iclass 26, count 0 2006.285.17:28:29.22#ibcon#*mode == 0, iclass 26, count 0 2006.285.17:28:29.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.17:28:29.22#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.17:28:29.22#ibcon#*before write, iclass 26, count 0 2006.285.17:28:29.22#ibcon#enter sib2, iclass 26, count 0 2006.285.17:28:29.22#ibcon#flushed, iclass 26, count 0 2006.285.17:28:29.22#ibcon#about to write, iclass 26, count 0 2006.285.17:28:29.22#ibcon#wrote, iclass 26, count 0 2006.285.17:28:29.22#ibcon#about to read 3, iclass 26, count 0 2006.285.17:28:29.26#ibcon#read 3, iclass 26, count 0 2006.285.17:28:29.26#ibcon#about to read 4, iclass 26, count 0 2006.285.17:28:29.26#ibcon#read 4, iclass 26, count 0 2006.285.17:28:29.26#ibcon#about to read 5, iclass 26, count 0 2006.285.17:28:29.26#ibcon#read 5, iclass 26, count 0 2006.285.17:28:29.26#ibcon#about to read 6, iclass 26, count 0 2006.285.17:28:29.26#ibcon#read 6, iclass 26, count 0 2006.285.17:28:29.26#ibcon#end of sib2, iclass 26, count 0 2006.285.17:28:29.26#ibcon#*after write, iclass 26, count 0 2006.285.17:28:29.26#ibcon#*before return 0, iclass 26, count 0 2006.285.17:28:29.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:28:29.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:28:29.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.17:28:29.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.17:28:29.26$vck44/vb=1,4 2006.285.17:28:29.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.17:28:29.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.17:28:29.26#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:29.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:28:29.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:28:29.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:28:29.26#ibcon#enter wrdev, iclass 28, count 2 2006.285.17:28:29.26#ibcon#first serial, iclass 28, count 2 2006.285.17:28:29.26#ibcon#enter sib2, iclass 28, count 2 2006.285.17:28:29.26#ibcon#flushed, iclass 28, count 2 2006.285.17:28:29.26#ibcon#about to write, iclass 28, count 2 2006.285.17:28:29.26#ibcon#wrote, iclass 28, count 2 2006.285.17:28:29.26#ibcon#about to read 3, iclass 28, count 2 2006.285.17:28:29.28#ibcon#read 3, iclass 28, count 2 2006.285.17:28:29.28#ibcon#about to read 4, iclass 28, count 2 2006.285.17:28:29.28#ibcon#read 4, iclass 28, count 2 2006.285.17:28:29.28#ibcon#about to read 5, iclass 28, count 2 2006.285.17:28:29.28#ibcon#read 5, iclass 28, count 2 2006.285.17:28:29.28#ibcon#about to read 6, iclass 28, count 2 2006.285.17:28:29.28#ibcon#read 6, iclass 28, count 2 2006.285.17:28:29.28#ibcon#end of sib2, iclass 28, count 2 2006.285.17:28:29.28#ibcon#*mode == 0, iclass 28, count 2 2006.285.17:28:29.28#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.17:28:29.28#ibcon#[27=AT01-04\r\n] 2006.285.17:28:29.28#ibcon#*before write, iclass 28, count 2 2006.285.17:28:29.28#ibcon#enter sib2, iclass 28, count 2 2006.285.17:28:29.28#ibcon#flushed, iclass 28, count 2 2006.285.17:28:29.28#ibcon#about to write, iclass 28, count 2 2006.285.17:28:29.28#ibcon#wrote, iclass 28, count 2 2006.285.17:28:29.28#ibcon#about to read 3, iclass 28, count 2 2006.285.17:28:29.31#ibcon#read 3, iclass 28, count 2 2006.285.17:28:29.31#ibcon#about to read 4, iclass 28, count 2 2006.285.17:28:29.31#ibcon#read 4, iclass 28, count 2 2006.285.17:28:29.31#ibcon#about to read 5, iclass 28, count 2 2006.285.17:28:29.31#ibcon#read 5, iclass 28, count 2 2006.285.17:28:29.31#ibcon#about to read 6, iclass 28, count 2 2006.285.17:28:29.31#ibcon#read 6, iclass 28, count 2 2006.285.17:28:29.31#ibcon#end of sib2, iclass 28, count 2 2006.285.17:28:29.31#ibcon#*after write, iclass 28, count 2 2006.285.17:28:29.31#ibcon#*before return 0, iclass 28, count 2 2006.285.17:28:29.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:28:29.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:28:29.31#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.17:28:29.31#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:29.31#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:28:29.43#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:28:29.43#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:28:29.43#ibcon#enter wrdev, iclass 28, count 0 2006.285.17:28:29.43#ibcon#first serial, iclass 28, count 0 2006.285.17:28:29.43#ibcon#enter sib2, iclass 28, count 0 2006.285.17:28:29.43#ibcon#flushed, iclass 28, count 0 2006.285.17:28:29.43#ibcon#about to write, iclass 28, count 0 2006.285.17:28:29.43#ibcon#wrote, iclass 28, count 0 2006.285.17:28:29.43#ibcon#about to read 3, iclass 28, count 0 2006.285.17:28:29.45#ibcon#read 3, iclass 28, count 0 2006.285.17:28:29.45#ibcon#about to read 4, iclass 28, count 0 2006.285.17:28:29.45#ibcon#read 4, iclass 28, count 0 2006.285.17:28:29.45#ibcon#about to read 5, iclass 28, count 0 2006.285.17:28:29.45#ibcon#read 5, iclass 28, count 0 2006.285.17:28:29.45#ibcon#about to read 6, iclass 28, count 0 2006.285.17:28:29.45#ibcon#read 6, iclass 28, count 0 2006.285.17:28:29.45#ibcon#end of sib2, iclass 28, count 0 2006.285.17:28:29.45#ibcon#*mode == 0, iclass 28, count 0 2006.285.17:28:29.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.17:28:29.45#ibcon#[27=USB\r\n] 2006.285.17:28:29.45#ibcon#*before write, iclass 28, count 0 2006.285.17:28:29.45#ibcon#enter sib2, iclass 28, count 0 2006.285.17:28:29.45#ibcon#flushed, iclass 28, count 0 2006.285.17:28:29.45#ibcon#about to write, iclass 28, count 0 2006.285.17:28:29.45#ibcon#wrote, iclass 28, count 0 2006.285.17:28:29.45#ibcon#about to read 3, iclass 28, count 0 2006.285.17:28:29.48#ibcon#read 3, iclass 28, count 0 2006.285.17:28:29.48#ibcon#about to read 4, iclass 28, count 0 2006.285.17:28:29.48#ibcon#read 4, iclass 28, count 0 2006.285.17:28:29.48#ibcon#about to read 5, iclass 28, count 0 2006.285.17:28:29.48#ibcon#read 5, iclass 28, count 0 2006.285.17:28:29.48#ibcon#about to read 6, iclass 28, count 0 2006.285.17:28:29.48#ibcon#read 6, iclass 28, count 0 2006.285.17:28:29.48#ibcon#end of sib2, iclass 28, count 0 2006.285.17:28:29.48#ibcon#*after write, iclass 28, count 0 2006.285.17:28:29.48#ibcon#*before return 0, iclass 28, count 0 2006.285.17:28:29.48#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:28:29.48#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:28:29.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.17:28:29.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.17:28:29.48$vck44/vblo=2,634.99 2006.285.17:28:29.48#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.17:28:29.48#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.17:28:29.48#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:29.48#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:28:29.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:28:29.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:28:29.48#ibcon#enter wrdev, iclass 30, count 0 2006.285.17:28:29.48#ibcon#first serial, iclass 30, count 0 2006.285.17:28:29.48#ibcon#enter sib2, iclass 30, count 0 2006.285.17:28:29.48#ibcon#flushed, iclass 30, count 0 2006.285.17:28:29.48#ibcon#about to write, iclass 30, count 0 2006.285.17:28:29.48#ibcon#wrote, iclass 30, count 0 2006.285.17:28:29.48#ibcon#about to read 3, iclass 30, count 0 2006.285.17:28:29.50#ibcon#read 3, iclass 30, count 0 2006.285.17:28:29.50#ibcon#about to read 4, iclass 30, count 0 2006.285.17:28:29.50#ibcon#read 4, iclass 30, count 0 2006.285.17:28:29.50#ibcon#about to read 5, iclass 30, count 0 2006.285.17:28:29.50#ibcon#read 5, iclass 30, count 0 2006.285.17:28:29.50#ibcon#about to read 6, iclass 30, count 0 2006.285.17:28:29.50#ibcon#read 6, iclass 30, count 0 2006.285.17:28:29.50#ibcon#end of sib2, iclass 30, count 0 2006.285.17:28:29.50#ibcon#*mode == 0, iclass 30, count 0 2006.285.17:28:29.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.17:28:29.50#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.17:28:29.50#ibcon#*before write, iclass 30, count 0 2006.285.17:28:29.50#ibcon#enter sib2, iclass 30, count 0 2006.285.17:28:29.50#ibcon#flushed, iclass 30, count 0 2006.285.17:28:29.50#ibcon#about to write, iclass 30, count 0 2006.285.17:28:29.50#ibcon#wrote, iclass 30, count 0 2006.285.17:28:29.50#ibcon#about to read 3, iclass 30, count 0 2006.285.17:28:29.54#ibcon#read 3, iclass 30, count 0 2006.285.17:28:29.54#ibcon#about to read 4, iclass 30, count 0 2006.285.17:28:29.54#ibcon#read 4, iclass 30, count 0 2006.285.17:28:29.54#ibcon#about to read 5, iclass 30, count 0 2006.285.17:28:29.54#ibcon#read 5, iclass 30, count 0 2006.285.17:28:29.54#ibcon#about to read 6, iclass 30, count 0 2006.285.17:28:29.54#ibcon#read 6, iclass 30, count 0 2006.285.17:28:29.54#ibcon#end of sib2, iclass 30, count 0 2006.285.17:28:29.54#ibcon#*after write, iclass 30, count 0 2006.285.17:28:29.54#ibcon#*before return 0, iclass 30, count 0 2006.285.17:28:29.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:28:29.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:28:29.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.17:28:29.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.17:28:29.54$vck44/vb=2,5 2006.285.17:28:29.54#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.17:28:29.54#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.17:28:29.54#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:29.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:28:29.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:28:29.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:28:29.60#ibcon#enter wrdev, iclass 32, count 2 2006.285.17:28:29.60#ibcon#first serial, iclass 32, count 2 2006.285.17:28:29.60#ibcon#enter sib2, iclass 32, count 2 2006.285.17:28:29.60#ibcon#flushed, iclass 32, count 2 2006.285.17:28:29.60#ibcon#about to write, iclass 32, count 2 2006.285.17:28:29.60#ibcon#wrote, iclass 32, count 2 2006.285.17:28:29.60#ibcon#about to read 3, iclass 32, count 2 2006.285.17:28:29.62#ibcon#read 3, iclass 32, count 2 2006.285.17:28:29.62#ibcon#about to read 4, iclass 32, count 2 2006.285.17:28:29.62#ibcon#read 4, iclass 32, count 2 2006.285.17:28:29.62#ibcon#about to read 5, iclass 32, count 2 2006.285.17:28:29.62#ibcon#read 5, iclass 32, count 2 2006.285.17:28:29.62#ibcon#about to read 6, iclass 32, count 2 2006.285.17:28:29.62#ibcon#read 6, iclass 32, count 2 2006.285.17:28:29.62#ibcon#end of sib2, iclass 32, count 2 2006.285.17:28:29.62#ibcon#*mode == 0, iclass 32, count 2 2006.285.17:28:29.62#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.17:28:29.62#ibcon#[27=AT02-05\r\n] 2006.285.17:28:29.62#ibcon#*before write, iclass 32, count 2 2006.285.17:28:29.62#ibcon#enter sib2, iclass 32, count 2 2006.285.17:28:29.62#ibcon#flushed, iclass 32, count 2 2006.285.17:28:29.62#ibcon#about to write, iclass 32, count 2 2006.285.17:28:29.62#ibcon#wrote, iclass 32, count 2 2006.285.17:28:29.62#ibcon#about to read 3, iclass 32, count 2 2006.285.17:28:29.65#ibcon#read 3, iclass 32, count 2 2006.285.17:28:29.65#ibcon#about to read 4, iclass 32, count 2 2006.285.17:28:29.65#ibcon#read 4, iclass 32, count 2 2006.285.17:28:29.65#ibcon#about to read 5, iclass 32, count 2 2006.285.17:28:29.65#ibcon#read 5, iclass 32, count 2 2006.285.17:28:29.65#ibcon#about to read 6, iclass 32, count 2 2006.285.17:28:29.65#ibcon#read 6, iclass 32, count 2 2006.285.17:28:29.65#ibcon#end of sib2, iclass 32, count 2 2006.285.17:28:29.65#ibcon#*after write, iclass 32, count 2 2006.285.17:28:29.65#ibcon#*before return 0, iclass 32, count 2 2006.285.17:28:29.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:28:29.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:28:29.65#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.17:28:29.65#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:29.65#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:28:29.77#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:28:29.77#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:28:29.77#ibcon#enter wrdev, iclass 32, count 0 2006.285.17:28:29.77#ibcon#first serial, iclass 32, count 0 2006.285.17:28:29.77#ibcon#enter sib2, iclass 32, count 0 2006.285.17:28:29.77#ibcon#flushed, iclass 32, count 0 2006.285.17:28:29.77#ibcon#about to write, iclass 32, count 0 2006.285.17:28:29.77#ibcon#wrote, iclass 32, count 0 2006.285.17:28:29.77#ibcon#about to read 3, iclass 32, count 0 2006.285.17:28:29.79#ibcon#read 3, iclass 32, count 0 2006.285.17:28:29.79#ibcon#about to read 4, iclass 32, count 0 2006.285.17:28:29.79#ibcon#read 4, iclass 32, count 0 2006.285.17:28:29.79#ibcon#about to read 5, iclass 32, count 0 2006.285.17:28:29.79#ibcon#read 5, iclass 32, count 0 2006.285.17:28:29.79#ibcon#about to read 6, iclass 32, count 0 2006.285.17:28:29.79#ibcon#read 6, iclass 32, count 0 2006.285.17:28:29.79#ibcon#end of sib2, iclass 32, count 0 2006.285.17:28:29.79#ibcon#*mode == 0, iclass 32, count 0 2006.285.17:28:29.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.17:28:29.79#ibcon#[27=USB\r\n] 2006.285.17:28:29.79#ibcon#*before write, iclass 32, count 0 2006.285.17:28:29.79#ibcon#enter sib2, iclass 32, count 0 2006.285.17:28:29.79#ibcon#flushed, iclass 32, count 0 2006.285.17:28:29.79#ibcon#about to write, iclass 32, count 0 2006.285.17:28:29.79#ibcon#wrote, iclass 32, count 0 2006.285.17:28:29.79#ibcon#about to read 3, iclass 32, count 0 2006.285.17:28:29.82#ibcon#read 3, iclass 32, count 0 2006.285.17:28:29.82#ibcon#about to read 4, iclass 32, count 0 2006.285.17:28:29.82#ibcon#read 4, iclass 32, count 0 2006.285.17:28:29.82#ibcon#about to read 5, iclass 32, count 0 2006.285.17:28:29.82#ibcon#read 5, iclass 32, count 0 2006.285.17:28:29.82#ibcon#about to read 6, iclass 32, count 0 2006.285.17:28:29.82#ibcon#read 6, iclass 32, count 0 2006.285.17:28:29.82#ibcon#end of sib2, iclass 32, count 0 2006.285.17:28:29.82#ibcon#*after write, iclass 32, count 0 2006.285.17:28:29.82#ibcon#*before return 0, iclass 32, count 0 2006.285.17:28:29.82#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:28:29.82#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:28:29.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.17:28:29.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.17:28:29.82$vck44/vblo=3,649.99 2006.285.17:28:29.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.17:28:29.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.17:28:29.82#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:29.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:28:29.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:28:29.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:28:29.82#ibcon#enter wrdev, iclass 34, count 0 2006.285.17:28:29.82#ibcon#first serial, iclass 34, count 0 2006.285.17:28:29.82#ibcon#enter sib2, iclass 34, count 0 2006.285.17:28:29.82#ibcon#flushed, iclass 34, count 0 2006.285.17:28:29.82#ibcon#about to write, iclass 34, count 0 2006.285.17:28:29.82#ibcon#wrote, iclass 34, count 0 2006.285.17:28:29.82#ibcon#about to read 3, iclass 34, count 0 2006.285.17:28:29.84#ibcon#read 3, iclass 34, count 0 2006.285.17:28:29.84#ibcon#about to read 4, iclass 34, count 0 2006.285.17:28:29.84#ibcon#read 4, iclass 34, count 0 2006.285.17:28:29.84#ibcon#about to read 5, iclass 34, count 0 2006.285.17:28:29.84#ibcon#read 5, iclass 34, count 0 2006.285.17:28:29.84#ibcon#about to read 6, iclass 34, count 0 2006.285.17:28:29.84#ibcon#read 6, iclass 34, count 0 2006.285.17:28:29.84#ibcon#end of sib2, iclass 34, count 0 2006.285.17:28:29.84#ibcon#*mode == 0, iclass 34, count 0 2006.285.17:28:29.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.17:28:29.84#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.17:28:29.84#ibcon#*before write, iclass 34, count 0 2006.285.17:28:29.84#ibcon#enter sib2, iclass 34, count 0 2006.285.17:28:29.84#ibcon#flushed, iclass 34, count 0 2006.285.17:28:29.84#ibcon#about to write, iclass 34, count 0 2006.285.17:28:29.84#ibcon#wrote, iclass 34, count 0 2006.285.17:28:29.84#ibcon#about to read 3, iclass 34, count 0 2006.285.17:28:29.88#ibcon#read 3, iclass 34, count 0 2006.285.17:28:29.88#ibcon#about to read 4, iclass 34, count 0 2006.285.17:28:29.88#ibcon#read 4, iclass 34, count 0 2006.285.17:28:29.88#ibcon#about to read 5, iclass 34, count 0 2006.285.17:28:29.88#ibcon#read 5, iclass 34, count 0 2006.285.17:28:29.88#ibcon#about to read 6, iclass 34, count 0 2006.285.17:28:29.88#ibcon#read 6, iclass 34, count 0 2006.285.17:28:29.88#ibcon#end of sib2, iclass 34, count 0 2006.285.17:28:29.88#ibcon#*after write, iclass 34, count 0 2006.285.17:28:29.88#ibcon#*before return 0, iclass 34, count 0 2006.285.17:28:29.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:28:29.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:28:29.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.17:28:29.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.17:28:29.88$vck44/vb=3,4 2006.285.17:28:29.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.17:28:29.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.17:28:29.88#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:29.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:28:29.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:28:29.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:28:29.94#ibcon#enter wrdev, iclass 36, count 2 2006.285.17:28:29.94#ibcon#first serial, iclass 36, count 2 2006.285.17:28:29.94#ibcon#enter sib2, iclass 36, count 2 2006.285.17:28:29.94#ibcon#flushed, iclass 36, count 2 2006.285.17:28:29.94#ibcon#about to write, iclass 36, count 2 2006.285.17:28:29.94#ibcon#wrote, iclass 36, count 2 2006.285.17:28:29.94#ibcon#about to read 3, iclass 36, count 2 2006.285.17:28:29.96#ibcon#read 3, iclass 36, count 2 2006.285.17:28:29.96#ibcon#about to read 4, iclass 36, count 2 2006.285.17:28:29.96#ibcon#read 4, iclass 36, count 2 2006.285.17:28:29.96#ibcon#about to read 5, iclass 36, count 2 2006.285.17:28:29.96#ibcon#read 5, iclass 36, count 2 2006.285.17:28:29.96#ibcon#about to read 6, iclass 36, count 2 2006.285.17:28:29.96#ibcon#read 6, iclass 36, count 2 2006.285.17:28:29.96#ibcon#end of sib2, iclass 36, count 2 2006.285.17:28:29.96#ibcon#*mode == 0, iclass 36, count 2 2006.285.17:28:29.96#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.17:28:29.96#ibcon#[27=AT03-04\r\n] 2006.285.17:28:29.96#ibcon#*before write, iclass 36, count 2 2006.285.17:28:29.96#ibcon#enter sib2, iclass 36, count 2 2006.285.17:28:29.96#ibcon#flushed, iclass 36, count 2 2006.285.17:28:29.96#ibcon#about to write, iclass 36, count 2 2006.285.17:28:29.96#ibcon#wrote, iclass 36, count 2 2006.285.17:28:29.96#ibcon#about to read 3, iclass 36, count 2 2006.285.17:28:29.99#ibcon#read 3, iclass 36, count 2 2006.285.17:28:30.02#ibcon#about to read 4, iclass 36, count 2 2006.285.17:28:30.02#ibcon#read 4, iclass 36, count 2 2006.285.17:28:30.02#ibcon#about to read 5, iclass 36, count 2 2006.285.17:28:30.02#ibcon#read 5, iclass 36, count 2 2006.285.17:28:30.02#ibcon#about to read 6, iclass 36, count 2 2006.285.17:28:30.02#ibcon#read 6, iclass 36, count 2 2006.285.17:28:30.02#ibcon#end of sib2, iclass 36, count 2 2006.285.17:28:30.02#ibcon#*after write, iclass 36, count 2 2006.285.17:28:30.02#ibcon#*before return 0, iclass 36, count 2 2006.285.17:28:30.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:28:30.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:28:30.02#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.17:28:30.02#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:30.02#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:28:30.14#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:28:30.14#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:28:30.14#ibcon#enter wrdev, iclass 36, count 0 2006.285.17:28:30.14#ibcon#first serial, iclass 36, count 0 2006.285.17:28:30.14#ibcon#enter sib2, iclass 36, count 0 2006.285.17:28:30.14#ibcon#flushed, iclass 36, count 0 2006.285.17:28:30.14#ibcon#about to write, iclass 36, count 0 2006.285.17:28:30.14#ibcon#wrote, iclass 36, count 0 2006.285.17:28:30.14#ibcon#about to read 3, iclass 36, count 0 2006.285.17:28:30.16#ibcon#read 3, iclass 36, count 0 2006.285.17:28:30.16#ibcon#about to read 4, iclass 36, count 0 2006.285.17:28:30.16#ibcon#read 4, iclass 36, count 0 2006.285.17:28:30.16#ibcon#about to read 5, iclass 36, count 0 2006.285.17:28:30.16#ibcon#read 5, iclass 36, count 0 2006.285.17:28:30.16#ibcon#about to read 6, iclass 36, count 0 2006.285.17:28:30.16#ibcon#read 6, iclass 36, count 0 2006.285.17:28:30.16#ibcon#end of sib2, iclass 36, count 0 2006.285.17:28:30.16#ibcon#*mode == 0, iclass 36, count 0 2006.285.17:28:30.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.17:28:30.16#ibcon#[27=USB\r\n] 2006.285.17:28:30.16#ibcon#*before write, iclass 36, count 0 2006.285.17:28:30.16#ibcon#enter sib2, iclass 36, count 0 2006.285.17:28:30.16#ibcon#flushed, iclass 36, count 0 2006.285.17:28:30.16#ibcon#about to write, iclass 36, count 0 2006.285.17:28:30.16#ibcon#wrote, iclass 36, count 0 2006.285.17:28:30.16#ibcon#about to read 3, iclass 36, count 0 2006.285.17:28:30.19#ibcon#read 3, iclass 36, count 0 2006.285.17:28:30.19#ibcon#about to read 4, iclass 36, count 0 2006.285.17:28:30.19#ibcon#read 4, iclass 36, count 0 2006.285.17:28:30.19#ibcon#about to read 5, iclass 36, count 0 2006.285.17:28:30.19#ibcon#read 5, iclass 36, count 0 2006.285.17:28:30.19#ibcon#about to read 6, iclass 36, count 0 2006.285.17:28:30.19#ibcon#read 6, iclass 36, count 0 2006.285.17:28:30.19#ibcon#end of sib2, iclass 36, count 0 2006.285.17:28:30.19#ibcon#*after write, iclass 36, count 0 2006.285.17:28:30.19#ibcon#*before return 0, iclass 36, count 0 2006.285.17:28:30.19#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:28:30.19#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:28:30.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.17:28:30.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.17:28:30.19$vck44/vblo=4,679.99 2006.285.17:28:30.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.17:28:30.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.17:28:30.19#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:30.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:28:30.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:28:30.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:28:30.19#ibcon#enter wrdev, iclass 38, count 0 2006.285.17:28:30.19#ibcon#first serial, iclass 38, count 0 2006.285.17:28:30.19#ibcon#enter sib2, iclass 38, count 0 2006.285.17:28:30.19#ibcon#flushed, iclass 38, count 0 2006.285.17:28:30.19#ibcon#about to write, iclass 38, count 0 2006.285.17:28:30.19#ibcon#wrote, iclass 38, count 0 2006.285.17:28:30.19#ibcon#about to read 3, iclass 38, count 0 2006.285.17:28:30.21#ibcon#read 3, iclass 38, count 0 2006.285.17:28:30.21#ibcon#about to read 4, iclass 38, count 0 2006.285.17:28:30.21#ibcon#read 4, iclass 38, count 0 2006.285.17:28:30.21#ibcon#about to read 5, iclass 38, count 0 2006.285.17:28:30.21#ibcon#read 5, iclass 38, count 0 2006.285.17:28:30.21#ibcon#about to read 6, iclass 38, count 0 2006.285.17:28:30.21#ibcon#read 6, iclass 38, count 0 2006.285.17:28:30.21#ibcon#end of sib2, iclass 38, count 0 2006.285.17:28:30.21#ibcon#*mode == 0, iclass 38, count 0 2006.285.17:28:30.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.17:28:30.21#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.17:28:30.21#ibcon#*before write, iclass 38, count 0 2006.285.17:28:30.21#ibcon#enter sib2, iclass 38, count 0 2006.285.17:28:30.21#ibcon#flushed, iclass 38, count 0 2006.285.17:28:30.21#ibcon#about to write, iclass 38, count 0 2006.285.17:28:30.21#ibcon#wrote, iclass 38, count 0 2006.285.17:28:30.21#ibcon#about to read 3, iclass 38, count 0 2006.285.17:28:30.25#ibcon#read 3, iclass 38, count 0 2006.285.17:28:30.25#ibcon#about to read 4, iclass 38, count 0 2006.285.17:28:30.25#ibcon#read 4, iclass 38, count 0 2006.285.17:28:30.25#ibcon#about to read 5, iclass 38, count 0 2006.285.17:28:30.25#ibcon#read 5, iclass 38, count 0 2006.285.17:28:30.25#ibcon#about to read 6, iclass 38, count 0 2006.285.17:28:30.25#ibcon#read 6, iclass 38, count 0 2006.285.17:28:30.25#ibcon#end of sib2, iclass 38, count 0 2006.285.17:28:30.25#ibcon#*after write, iclass 38, count 0 2006.285.17:28:30.25#ibcon#*before return 0, iclass 38, count 0 2006.285.17:28:30.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:28:30.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:28:30.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.17:28:30.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.17:28:30.25$vck44/vb=4,5 2006.285.17:28:30.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.17:28:30.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.17:28:30.25#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:30.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:28:30.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:28:30.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:28:30.31#ibcon#enter wrdev, iclass 40, count 2 2006.285.17:28:30.31#ibcon#first serial, iclass 40, count 2 2006.285.17:28:30.31#ibcon#enter sib2, iclass 40, count 2 2006.285.17:28:30.31#ibcon#flushed, iclass 40, count 2 2006.285.17:28:30.31#ibcon#about to write, iclass 40, count 2 2006.285.17:28:30.31#ibcon#wrote, iclass 40, count 2 2006.285.17:28:30.31#ibcon#about to read 3, iclass 40, count 2 2006.285.17:28:30.33#ibcon#read 3, iclass 40, count 2 2006.285.17:28:30.33#ibcon#about to read 4, iclass 40, count 2 2006.285.17:28:30.33#ibcon#read 4, iclass 40, count 2 2006.285.17:28:30.33#ibcon#about to read 5, iclass 40, count 2 2006.285.17:28:30.33#ibcon#read 5, iclass 40, count 2 2006.285.17:28:30.33#ibcon#about to read 6, iclass 40, count 2 2006.285.17:28:30.33#ibcon#read 6, iclass 40, count 2 2006.285.17:28:30.33#ibcon#end of sib2, iclass 40, count 2 2006.285.17:28:30.33#ibcon#*mode == 0, iclass 40, count 2 2006.285.17:28:30.33#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.17:28:30.33#ibcon#[27=AT04-05\r\n] 2006.285.17:28:30.33#ibcon#*before write, iclass 40, count 2 2006.285.17:28:30.33#ibcon#enter sib2, iclass 40, count 2 2006.285.17:28:30.33#ibcon#flushed, iclass 40, count 2 2006.285.17:28:30.33#ibcon#about to write, iclass 40, count 2 2006.285.17:28:30.33#ibcon#wrote, iclass 40, count 2 2006.285.17:28:30.33#ibcon#about to read 3, iclass 40, count 2 2006.285.17:28:30.36#ibcon#read 3, iclass 40, count 2 2006.285.17:28:30.36#ibcon#about to read 4, iclass 40, count 2 2006.285.17:28:30.36#ibcon#read 4, iclass 40, count 2 2006.285.17:28:30.36#ibcon#about to read 5, iclass 40, count 2 2006.285.17:28:30.36#ibcon#read 5, iclass 40, count 2 2006.285.17:28:30.36#ibcon#about to read 6, iclass 40, count 2 2006.285.17:28:30.36#ibcon#read 6, iclass 40, count 2 2006.285.17:28:30.36#ibcon#end of sib2, iclass 40, count 2 2006.285.17:28:30.36#ibcon#*after write, iclass 40, count 2 2006.285.17:28:30.36#ibcon#*before return 0, iclass 40, count 2 2006.285.17:28:30.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:28:30.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:28:30.36#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.17:28:30.36#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:30.36#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:28:30.48#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:28:30.48#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:28:30.48#ibcon#enter wrdev, iclass 40, count 0 2006.285.17:28:30.48#ibcon#first serial, iclass 40, count 0 2006.285.17:28:30.48#ibcon#enter sib2, iclass 40, count 0 2006.285.17:28:30.48#ibcon#flushed, iclass 40, count 0 2006.285.17:28:30.48#ibcon#about to write, iclass 40, count 0 2006.285.17:28:30.48#ibcon#wrote, iclass 40, count 0 2006.285.17:28:30.48#ibcon#about to read 3, iclass 40, count 0 2006.285.17:28:30.50#ibcon#read 3, iclass 40, count 0 2006.285.17:28:30.50#ibcon#about to read 4, iclass 40, count 0 2006.285.17:28:30.50#ibcon#read 4, iclass 40, count 0 2006.285.17:28:30.50#ibcon#about to read 5, iclass 40, count 0 2006.285.17:28:30.50#ibcon#read 5, iclass 40, count 0 2006.285.17:28:30.50#ibcon#about to read 6, iclass 40, count 0 2006.285.17:28:30.50#ibcon#read 6, iclass 40, count 0 2006.285.17:28:30.50#ibcon#end of sib2, iclass 40, count 0 2006.285.17:28:30.50#ibcon#*mode == 0, iclass 40, count 0 2006.285.17:28:30.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.17:28:30.50#ibcon#[27=USB\r\n] 2006.285.17:28:30.50#ibcon#*before write, iclass 40, count 0 2006.285.17:28:30.50#ibcon#enter sib2, iclass 40, count 0 2006.285.17:28:30.50#ibcon#flushed, iclass 40, count 0 2006.285.17:28:30.50#ibcon#about to write, iclass 40, count 0 2006.285.17:28:30.50#ibcon#wrote, iclass 40, count 0 2006.285.17:28:30.50#ibcon#about to read 3, iclass 40, count 0 2006.285.17:28:30.53#ibcon#read 3, iclass 40, count 0 2006.285.17:28:30.53#ibcon#about to read 4, iclass 40, count 0 2006.285.17:28:30.53#ibcon#read 4, iclass 40, count 0 2006.285.17:28:30.53#ibcon#about to read 5, iclass 40, count 0 2006.285.17:28:30.53#ibcon#read 5, iclass 40, count 0 2006.285.17:28:30.53#ibcon#about to read 6, iclass 40, count 0 2006.285.17:28:30.53#ibcon#read 6, iclass 40, count 0 2006.285.17:28:30.53#ibcon#end of sib2, iclass 40, count 0 2006.285.17:28:30.53#ibcon#*after write, iclass 40, count 0 2006.285.17:28:30.53#ibcon#*before return 0, iclass 40, count 0 2006.285.17:28:30.53#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:28:30.53#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:28:30.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.17:28:30.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.17:28:30.53$vck44/vblo=5,709.99 2006.285.17:28:30.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.17:28:30.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.17:28:30.53#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:30.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:28:30.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:28:30.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:28:30.53#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:28:30.53#ibcon#first serial, iclass 4, count 0 2006.285.17:28:30.53#ibcon#enter sib2, iclass 4, count 0 2006.285.17:28:30.53#ibcon#flushed, iclass 4, count 0 2006.285.17:28:30.53#ibcon#about to write, iclass 4, count 0 2006.285.17:28:30.53#ibcon#wrote, iclass 4, count 0 2006.285.17:28:30.53#ibcon#about to read 3, iclass 4, count 0 2006.285.17:28:30.55#ibcon#read 3, iclass 4, count 0 2006.285.17:28:30.55#ibcon#about to read 4, iclass 4, count 0 2006.285.17:28:30.55#ibcon#read 4, iclass 4, count 0 2006.285.17:28:30.55#ibcon#about to read 5, iclass 4, count 0 2006.285.17:28:30.55#ibcon#read 5, iclass 4, count 0 2006.285.17:28:30.55#ibcon#about to read 6, iclass 4, count 0 2006.285.17:28:30.55#ibcon#read 6, iclass 4, count 0 2006.285.17:28:30.55#ibcon#end of sib2, iclass 4, count 0 2006.285.17:28:30.55#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:28:30.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:28:30.55#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.17:28:30.55#ibcon#*before write, iclass 4, count 0 2006.285.17:28:30.55#ibcon#enter sib2, iclass 4, count 0 2006.285.17:28:30.55#ibcon#flushed, iclass 4, count 0 2006.285.17:28:30.55#ibcon#about to write, iclass 4, count 0 2006.285.17:28:30.55#ibcon#wrote, iclass 4, count 0 2006.285.17:28:30.55#ibcon#about to read 3, iclass 4, count 0 2006.285.17:28:30.59#ibcon#read 3, iclass 4, count 0 2006.285.17:28:30.59#ibcon#about to read 4, iclass 4, count 0 2006.285.17:28:30.59#ibcon#read 4, iclass 4, count 0 2006.285.17:28:30.59#ibcon#about to read 5, iclass 4, count 0 2006.285.17:28:30.59#ibcon#read 5, iclass 4, count 0 2006.285.17:28:30.59#ibcon#about to read 6, iclass 4, count 0 2006.285.17:28:30.59#ibcon#read 6, iclass 4, count 0 2006.285.17:28:30.59#ibcon#end of sib2, iclass 4, count 0 2006.285.17:28:30.59#ibcon#*after write, iclass 4, count 0 2006.285.17:28:30.59#ibcon#*before return 0, iclass 4, count 0 2006.285.17:28:30.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:28:30.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:28:30.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:28:30.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:28:30.59$vck44/vb=5,4 2006.285.17:28:30.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.17:28:30.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.17:28:30.59#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:30.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:28:30.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:28:30.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:28:30.65#ibcon#enter wrdev, iclass 6, count 2 2006.285.17:28:30.65#ibcon#first serial, iclass 6, count 2 2006.285.17:28:30.65#ibcon#enter sib2, iclass 6, count 2 2006.285.17:28:30.65#ibcon#flushed, iclass 6, count 2 2006.285.17:28:30.65#ibcon#about to write, iclass 6, count 2 2006.285.17:28:30.65#ibcon#wrote, iclass 6, count 2 2006.285.17:28:30.65#ibcon#about to read 3, iclass 6, count 2 2006.285.17:28:30.67#ibcon#read 3, iclass 6, count 2 2006.285.17:28:30.67#ibcon#about to read 4, iclass 6, count 2 2006.285.17:28:30.67#ibcon#read 4, iclass 6, count 2 2006.285.17:28:30.67#ibcon#about to read 5, iclass 6, count 2 2006.285.17:28:30.67#ibcon#read 5, iclass 6, count 2 2006.285.17:28:30.67#ibcon#about to read 6, iclass 6, count 2 2006.285.17:28:30.67#ibcon#read 6, iclass 6, count 2 2006.285.17:28:30.67#ibcon#end of sib2, iclass 6, count 2 2006.285.17:28:30.67#ibcon#*mode == 0, iclass 6, count 2 2006.285.17:28:30.67#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.17:28:30.67#ibcon#[27=AT05-04\r\n] 2006.285.17:28:30.67#ibcon#*before write, iclass 6, count 2 2006.285.17:28:30.67#ibcon#enter sib2, iclass 6, count 2 2006.285.17:28:30.67#ibcon#flushed, iclass 6, count 2 2006.285.17:28:30.67#ibcon#about to write, iclass 6, count 2 2006.285.17:28:30.67#ibcon#wrote, iclass 6, count 2 2006.285.17:28:30.67#ibcon#about to read 3, iclass 6, count 2 2006.285.17:28:30.70#ibcon#read 3, iclass 6, count 2 2006.285.17:28:30.70#ibcon#about to read 4, iclass 6, count 2 2006.285.17:28:30.70#ibcon#read 4, iclass 6, count 2 2006.285.17:28:30.70#ibcon#about to read 5, iclass 6, count 2 2006.285.17:28:30.70#ibcon#read 5, iclass 6, count 2 2006.285.17:28:30.70#ibcon#about to read 6, iclass 6, count 2 2006.285.17:28:30.70#ibcon#read 6, iclass 6, count 2 2006.285.17:28:30.70#ibcon#end of sib2, iclass 6, count 2 2006.285.17:28:30.70#ibcon#*after write, iclass 6, count 2 2006.285.17:28:30.70#ibcon#*before return 0, iclass 6, count 2 2006.285.17:28:30.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:28:30.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:28:30.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.17:28:30.70#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:30.70#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:28:30.82#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:28:30.82#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:28:30.82#ibcon#enter wrdev, iclass 6, count 0 2006.285.17:28:30.82#ibcon#first serial, iclass 6, count 0 2006.285.17:28:30.82#ibcon#enter sib2, iclass 6, count 0 2006.285.17:28:30.82#ibcon#flushed, iclass 6, count 0 2006.285.17:28:30.82#ibcon#about to write, iclass 6, count 0 2006.285.17:28:30.82#ibcon#wrote, iclass 6, count 0 2006.285.17:28:30.82#ibcon#about to read 3, iclass 6, count 0 2006.285.17:28:30.84#ibcon#read 3, iclass 6, count 0 2006.285.17:28:30.84#ibcon#about to read 4, iclass 6, count 0 2006.285.17:28:30.84#ibcon#read 4, iclass 6, count 0 2006.285.17:28:30.84#ibcon#about to read 5, iclass 6, count 0 2006.285.17:28:30.84#ibcon#read 5, iclass 6, count 0 2006.285.17:28:30.84#ibcon#about to read 6, iclass 6, count 0 2006.285.17:28:30.84#ibcon#read 6, iclass 6, count 0 2006.285.17:28:30.84#ibcon#end of sib2, iclass 6, count 0 2006.285.17:28:30.84#ibcon#*mode == 0, iclass 6, count 0 2006.285.17:28:30.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.17:28:30.84#ibcon#[27=USB\r\n] 2006.285.17:28:30.84#ibcon#*before write, iclass 6, count 0 2006.285.17:28:30.84#ibcon#enter sib2, iclass 6, count 0 2006.285.17:28:30.84#ibcon#flushed, iclass 6, count 0 2006.285.17:28:30.84#ibcon#about to write, iclass 6, count 0 2006.285.17:28:30.84#ibcon#wrote, iclass 6, count 0 2006.285.17:28:30.84#ibcon#about to read 3, iclass 6, count 0 2006.285.17:28:30.87#ibcon#read 3, iclass 6, count 0 2006.285.17:28:30.87#ibcon#about to read 4, iclass 6, count 0 2006.285.17:28:30.87#ibcon#read 4, iclass 6, count 0 2006.285.17:28:30.87#ibcon#about to read 5, iclass 6, count 0 2006.285.17:28:30.87#ibcon#read 5, iclass 6, count 0 2006.285.17:28:30.87#ibcon#about to read 6, iclass 6, count 0 2006.285.17:28:30.87#ibcon#read 6, iclass 6, count 0 2006.285.17:28:30.87#ibcon#end of sib2, iclass 6, count 0 2006.285.17:28:30.87#ibcon#*after write, iclass 6, count 0 2006.285.17:28:30.87#ibcon#*before return 0, iclass 6, count 0 2006.285.17:28:30.87#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:28:30.87#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:28:30.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.17:28:30.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.17:28:30.87$vck44/vblo=6,719.99 2006.285.17:28:30.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.17:28:30.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.17:28:30.87#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:30.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:28:30.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:28:30.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:28:30.87#ibcon#enter wrdev, iclass 10, count 0 2006.285.17:28:30.87#ibcon#first serial, iclass 10, count 0 2006.285.17:28:30.87#ibcon#enter sib2, iclass 10, count 0 2006.285.17:28:30.87#ibcon#flushed, iclass 10, count 0 2006.285.17:28:30.87#ibcon#about to write, iclass 10, count 0 2006.285.17:28:30.87#ibcon#wrote, iclass 10, count 0 2006.285.17:28:30.87#ibcon#about to read 3, iclass 10, count 0 2006.285.17:28:30.89#ibcon#read 3, iclass 10, count 0 2006.285.17:28:30.89#ibcon#about to read 4, iclass 10, count 0 2006.285.17:28:30.89#ibcon#read 4, iclass 10, count 0 2006.285.17:28:30.89#ibcon#about to read 5, iclass 10, count 0 2006.285.17:28:30.89#ibcon#read 5, iclass 10, count 0 2006.285.17:28:30.89#ibcon#about to read 6, iclass 10, count 0 2006.285.17:28:30.89#ibcon#read 6, iclass 10, count 0 2006.285.17:28:30.89#ibcon#end of sib2, iclass 10, count 0 2006.285.17:28:30.89#ibcon#*mode == 0, iclass 10, count 0 2006.285.17:28:30.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.17:28:30.89#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.17:28:30.89#ibcon#*before write, iclass 10, count 0 2006.285.17:28:30.89#ibcon#enter sib2, iclass 10, count 0 2006.285.17:28:30.89#ibcon#flushed, iclass 10, count 0 2006.285.17:28:30.89#ibcon#about to write, iclass 10, count 0 2006.285.17:28:30.89#ibcon#wrote, iclass 10, count 0 2006.285.17:28:30.89#ibcon#about to read 3, iclass 10, count 0 2006.285.17:28:30.93#ibcon#read 3, iclass 10, count 0 2006.285.17:28:30.93#ibcon#about to read 4, iclass 10, count 0 2006.285.17:28:30.93#ibcon#read 4, iclass 10, count 0 2006.285.17:28:30.93#ibcon#about to read 5, iclass 10, count 0 2006.285.17:28:30.93#ibcon#read 5, iclass 10, count 0 2006.285.17:28:30.93#ibcon#about to read 6, iclass 10, count 0 2006.285.17:28:30.93#ibcon#read 6, iclass 10, count 0 2006.285.17:28:30.93#ibcon#end of sib2, iclass 10, count 0 2006.285.17:28:30.93#ibcon#*after write, iclass 10, count 0 2006.285.17:28:30.93#ibcon#*before return 0, iclass 10, count 0 2006.285.17:28:30.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:28:30.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:28:30.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.17:28:30.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.17:28:30.93$vck44/vb=6,3 2006.285.17:28:30.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.17:28:30.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.17:28:30.93#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:30.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:28:30.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:28:30.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:28:30.99#ibcon#enter wrdev, iclass 12, count 2 2006.285.17:28:30.99#ibcon#first serial, iclass 12, count 2 2006.285.17:28:30.99#ibcon#enter sib2, iclass 12, count 2 2006.285.17:28:30.99#ibcon#flushed, iclass 12, count 2 2006.285.17:28:30.99#ibcon#about to write, iclass 12, count 2 2006.285.17:28:30.99#ibcon#wrote, iclass 12, count 2 2006.285.17:28:30.99#ibcon#about to read 3, iclass 12, count 2 2006.285.17:28:31.01#ibcon#read 3, iclass 12, count 2 2006.285.17:28:31.07#ibcon#about to read 4, iclass 12, count 2 2006.285.17:28:31.07#ibcon#read 4, iclass 12, count 2 2006.285.17:28:31.07#ibcon#about to read 5, iclass 12, count 2 2006.285.17:28:31.07#ibcon#read 5, iclass 12, count 2 2006.285.17:28:31.07#ibcon#about to read 6, iclass 12, count 2 2006.285.17:28:31.07#ibcon#read 6, iclass 12, count 2 2006.285.17:28:31.07#ibcon#end of sib2, iclass 12, count 2 2006.285.17:28:31.07#ibcon#*mode == 0, iclass 12, count 2 2006.285.17:28:31.07#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.17:28:31.07#ibcon#[27=AT06-03\r\n] 2006.285.17:28:31.07#ibcon#*before write, iclass 12, count 2 2006.285.17:28:31.07#ibcon#enter sib2, iclass 12, count 2 2006.285.17:28:31.07#ibcon#flushed, iclass 12, count 2 2006.285.17:28:31.07#ibcon#about to write, iclass 12, count 2 2006.285.17:28:31.07#ibcon#wrote, iclass 12, count 2 2006.285.17:28:31.07#ibcon#about to read 3, iclass 12, count 2 2006.285.17:28:31.10#ibcon#read 3, iclass 12, count 2 2006.285.17:28:31.10#ibcon#about to read 4, iclass 12, count 2 2006.285.17:28:31.10#ibcon#read 4, iclass 12, count 2 2006.285.17:28:31.10#ibcon#about to read 5, iclass 12, count 2 2006.285.17:28:31.10#ibcon#read 5, iclass 12, count 2 2006.285.17:28:31.10#ibcon#about to read 6, iclass 12, count 2 2006.285.17:28:31.10#ibcon#read 6, iclass 12, count 2 2006.285.17:28:31.10#ibcon#end of sib2, iclass 12, count 2 2006.285.17:28:31.10#ibcon#*after write, iclass 12, count 2 2006.285.17:28:31.10#ibcon#*before return 0, iclass 12, count 2 2006.285.17:28:31.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:28:31.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:28:31.10#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.17:28:31.10#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:31.10#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:28:31.22#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:28:31.22#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:28:31.22#ibcon#enter wrdev, iclass 12, count 0 2006.285.17:28:31.22#ibcon#first serial, iclass 12, count 0 2006.285.17:28:31.22#ibcon#enter sib2, iclass 12, count 0 2006.285.17:28:31.22#ibcon#flushed, iclass 12, count 0 2006.285.17:28:31.22#ibcon#about to write, iclass 12, count 0 2006.285.17:28:31.22#ibcon#wrote, iclass 12, count 0 2006.285.17:28:31.22#ibcon#about to read 3, iclass 12, count 0 2006.285.17:28:31.24#ibcon#read 3, iclass 12, count 0 2006.285.17:28:31.24#ibcon#about to read 4, iclass 12, count 0 2006.285.17:28:31.24#ibcon#read 4, iclass 12, count 0 2006.285.17:28:31.24#ibcon#about to read 5, iclass 12, count 0 2006.285.17:28:31.24#ibcon#read 5, iclass 12, count 0 2006.285.17:28:31.24#ibcon#about to read 6, iclass 12, count 0 2006.285.17:28:31.24#ibcon#read 6, iclass 12, count 0 2006.285.17:28:31.24#ibcon#end of sib2, iclass 12, count 0 2006.285.17:28:31.24#ibcon#*mode == 0, iclass 12, count 0 2006.285.17:28:31.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.17:28:31.24#ibcon#[27=USB\r\n] 2006.285.17:28:31.24#ibcon#*before write, iclass 12, count 0 2006.285.17:28:31.24#ibcon#enter sib2, iclass 12, count 0 2006.285.17:28:31.24#ibcon#flushed, iclass 12, count 0 2006.285.17:28:31.24#ibcon#about to write, iclass 12, count 0 2006.285.17:28:31.24#ibcon#wrote, iclass 12, count 0 2006.285.17:28:31.24#ibcon#about to read 3, iclass 12, count 0 2006.285.17:28:31.27#ibcon#read 3, iclass 12, count 0 2006.285.17:28:31.27#ibcon#about to read 4, iclass 12, count 0 2006.285.17:28:31.27#ibcon#read 4, iclass 12, count 0 2006.285.17:28:31.27#ibcon#about to read 5, iclass 12, count 0 2006.285.17:28:31.27#ibcon#read 5, iclass 12, count 0 2006.285.17:28:31.27#ibcon#about to read 6, iclass 12, count 0 2006.285.17:28:31.27#ibcon#read 6, iclass 12, count 0 2006.285.17:28:31.27#ibcon#end of sib2, iclass 12, count 0 2006.285.17:28:31.27#ibcon#*after write, iclass 12, count 0 2006.285.17:28:31.27#ibcon#*before return 0, iclass 12, count 0 2006.285.17:28:31.27#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:28:31.27#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:28:31.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.17:28:31.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.17:28:31.27$vck44/vblo=7,734.99 2006.285.17:28:31.27#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.17:28:31.27#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.17:28:31.27#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:31.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:28:31.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:28:31.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:28:31.27#ibcon#enter wrdev, iclass 14, count 0 2006.285.17:28:31.27#ibcon#first serial, iclass 14, count 0 2006.285.17:28:31.27#ibcon#enter sib2, iclass 14, count 0 2006.285.17:28:31.27#ibcon#flushed, iclass 14, count 0 2006.285.17:28:31.27#ibcon#about to write, iclass 14, count 0 2006.285.17:28:31.27#ibcon#wrote, iclass 14, count 0 2006.285.17:28:31.27#ibcon#about to read 3, iclass 14, count 0 2006.285.17:28:31.29#ibcon#read 3, iclass 14, count 0 2006.285.17:28:31.29#ibcon#about to read 4, iclass 14, count 0 2006.285.17:28:31.29#ibcon#read 4, iclass 14, count 0 2006.285.17:28:31.29#ibcon#about to read 5, iclass 14, count 0 2006.285.17:28:31.29#ibcon#read 5, iclass 14, count 0 2006.285.17:28:31.29#ibcon#about to read 6, iclass 14, count 0 2006.285.17:28:31.29#ibcon#read 6, iclass 14, count 0 2006.285.17:28:31.29#ibcon#end of sib2, iclass 14, count 0 2006.285.17:28:31.29#ibcon#*mode == 0, iclass 14, count 0 2006.285.17:28:31.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.17:28:31.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.17:28:31.29#ibcon#*before write, iclass 14, count 0 2006.285.17:28:31.29#ibcon#enter sib2, iclass 14, count 0 2006.285.17:28:31.29#ibcon#flushed, iclass 14, count 0 2006.285.17:28:31.29#ibcon#about to write, iclass 14, count 0 2006.285.17:28:31.29#ibcon#wrote, iclass 14, count 0 2006.285.17:28:31.29#ibcon#about to read 3, iclass 14, count 0 2006.285.17:28:31.33#ibcon#read 3, iclass 14, count 0 2006.285.17:28:31.33#ibcon#about to read 4, iclass 14, count 0 2006.285.17:28:31.33#ibcon#read 4, iclass 14, count 0 2006.285.17:28:31.33#ibcon#about to read 5, iclass 14, count 0 2006.285.17:28:31.33#ibcon#read 5, iclass 14, count 0 2006.285.17:28:31.33#ibcon#about to read 6, iclass 14, count 0 2006.285.17:28:31.33#ibcon#read 6, iclass 14, count 0 2006.285.17:28:31.33#ibcon#end of sib2, iclass 14, count 0 2006.285.17:28:31.33#ibcon#*after write, iclass 14, count 0 2006.285.17:28:31.33#ibcon#*before return 0, iclass 14, count 0 2006.285.17:28:31.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:28:31.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:28:31.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.17:28:31.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.17:28:31.33$vck44/vb=7,4 2006.285.17:28:31.33#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.17:28:31.33#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.17:28:31.33#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:31.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:28:31.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:28:31.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:28:31.39#ibcon#enter wrdev, iclass 16, count 2 2006.285.17:28:31.39#ibcon#first serial, iclass 16, count 2 2006.285.17:28:31.39#ibcon#enter sib2, iclass 16, count 2 2006.285.17:28:31.39#ibcon#flushed, iclass 16, count 2 2006.285.17:28:31.39#ibcon#about to write, iclass 16, count 2 2006.285.17:28:31.39#ibcon#wrote, iclass 16, count 2 2006.285.17:28:31.39#ibcon#about to read 3, iclass 16, count 2 2006.285.17:28:31.41#ibcon#read 3, iclass 16, count 2 2006.285.17:28:31.41#ibcon#about to read 4, iclass 16, count 2 2006.285.17:28:31.41#ibcon#read 4, iclass 16, count 2 2006.285.17:28:31.41#ibcon#about to read 5, iclass 16, count 2 2006.285.17:28:31.41#ibcon#read 5, iclass 16, count 2 2006.285.17:28:31.41#ibcon#about to read 6, iclass 16, count 2 2006.285.17:28:31.41#ibcon#read 6, iclass 16, count 2 2006.285.17:28:31.41#ibcon#end of sib2, iclass 16, count 2 2006.285.17:28:31.41#ibcon#*mode == 0, iclass 16, count 2 2006.285.17:28:31.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.17:28:31.41#ibcon#[27=AT07-04\r\n] 2006.285.17:28:31.41#ibcon#*before write, iclass 16, count 2 2006.285.17:28:31.41#ibcon#enter sib2, iclass 16, count 2 2006.285.17:28:31.41#ibcon#flushed, iclass 16, count 2 2006.285.17:28:31.41#ibcon#about to write, iclass 16, count 2 2006.285.17:28:31.41#ibcon#wrote, iclass 16, count 2 2006.285.17:28:31.41#ibcon#about to read 3, iclass 16, count 2 2006.285.17:28:31.44#ibcon#read 3, iclass 16, count 2 2006.285.17:28:31.44#ibcon#about to read 4, iclass 16, count 2 2006.285.17:28:31.44#ibcon#read 4, iclass 16, count 2 2006.285.17:28:31.44#ibcon#about to read 5, iclass 16, count 2 2006.285.17:28:31.44#ibcon#read 5, iclass 16, count 2 2006.285.17:28:31.44#ibcon#about to read 6, iclass 16, count 2 2006.285.17:28:31.44#ibcon#read 6, iclass 16, count 2 2006.285.17:28:31.44#ibcon#end of sib2, iclass 16, count 2 2006.285.17:28:31.44#ibcon#*after write, iclass 16, count 2 2006.285.17:28:31.44#ibcon#*before return 0, iclass 16, count 2 2006.285.17:28:31.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:28:31.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:28:31.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.17:28:31.44#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:31.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:28:31.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:28:31.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:28:31.56#ibcon#enter wrdev, iclass 16, count 0 2006.285.17:28:31.56#ibcon#first serial, iclass 16, count 0 2006.285.17:28:31.56#ibcon#enter sib2, iclass 16, count 0 2006.285.17:28:31.56#ibcon#flushed, iclass 16, count 0 2006.285.17:28:31.56#ibcon#about to write, iclass 16, count 0 2006.285.17:28:31.56#ibcon#wrote, iclass 16, count 0 2006.285.17:28:31.56#ibcon#about to read 3, iclass 16, count 0 2006.285.17:28:31.58#ibcon#read 3, iclass 16, count 0 2006.285.17:28:31.58#ibcon#about to read 4, iclass 16, count 0 2006.285.17:28:31.58#ibcon#read 4, iclass 16, count 0 2006.285.17:28:31.58#ibcon#about to read 5, iclass 16, count 0 2006.285.17:28:31.58#ibcon#read 5, iclass 16, count 0 2006.285.17:28:31.58#ibcon#about to read 6, iclass 16, count 0 2006.285.17:28:31.58#ibcon#read 6, iclass 16, count 0 2006.285.17:28:31.58#ibcon#end of sib2, iclass 16, count 0 2006.285.17:28:31.58#ibcon#*mode == 0, iclass 16, count 0 2006.285.17:28:31.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.17:28:31.58#ibcon#[27=USB\r\n] 2006.285.17:28:31.58#ibcon#*before write, iclass 16, count 0 2006.285.17:28:31.58#ibcon#enter sib2, iclass 16, count 0 2006.285.17:28:31.58#ibcon#flushed, iclass 16, count 0 2006.285.17:28:31.58#ibcon#about to write, iclass 16, count 0 2006.285.17:28:31.58#ibcon#wrote, iclass 16, count 0 2006.285.17:28:31.58#ibcon#about to read 3, iclass 16, count 0 2006.285.17:28:31.61#ibcon#read 3, iclass 16, count 0 2006.285.17:28:31.61#ibcon#about to read 4, iclass 16, count 0 2006.285.17:28:31.61#ibcon#read 4, iclass 16, count 0 2006.285.17:28:31.61#ibcon#about to read 5, iclass 16, count 0 2006.285.17:28:31.61#ibcon#read 5, iclass 16, count 0 2006.285.17:28:31.61#ibcon#about to read 6, iclass 16, count 0 2006.285.17:28:31.61#ibcon#read 6, iclass 16, count 0 2006.285.17:28:31.61#ibcon#end of sib2, iclass 16, count 0 2006.285.17:28:31.61#ibcon#*after write, iclass 16, count 0 2006.285.17:28:31.61#ibcon#*before return 0, iclass 16, count 0 2006.285.17:28:31.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:28:31.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:28:31.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.17:28:31.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.17:28:31.61$vck44/vblo=8,744.99 2006.285.17:28:31.61#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.17:28:31.61#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.17:28:31.61#ibcon#ireg 17 cls_cnt 0 2006.285.17:28:31.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:28:31.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:28:31.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:28:31.61#ibcon#enter wrdev, iclass 18, count 0 2006.285.17:28:31.61#ibcon#first serial, iclass 18, count 0 2006.285.17:28:31.61#ibcon#enter sib2, iclass 18, count 0 2006.285.17:28:31.61#ibcon#flushed, iclass 18, count 0 2006.285.17:28:31.61#ibcon#about to write, iclass 18, count 0 2006.285.17:28:31.61#ibcon#wrote, iclass 18, count 0 2006.285.17:28:31.61#ibcon#about to read 3, iclass 18, count 0 2006.285.17:28:31.63#ibcon#read 3, iclass 18, count 0 2006.285.17:28:31.63#ibcon#about to read 4, iclass 18, count 0 2006.285.17:28:31.63#ibcon#read 4, iclass 18, count 0 2006.285.17:28:31.63#ibcon#about to read 5, iclass 18, count 0 2006.285.17:28:31.63#ibcon#read 5, iclass 18, count 0 2006.285.17:28:31.63#ibcon#about to read 6, iclass 18, count 0 2006.285.17:28:31.63#ibcon#read 6, iclass 18, count 0 2006.285.17:28:31.63#ibcon#end of sib2, iclass 18, count 0 2006.285.17:28:31.63#ibcon#*mode == 0, iclass 18, count 0 2006.285.17:28:31.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.17:28:31.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.17:28:31.63#ibcon#*before write, iclass 18, count 0 2006.285.17:28:31.63#ibcon#enter sib2, iclass 18, count 0 2006.285.17:28:31.63#ibcon#flushed, iclass 18, count 0 2006.285.17:28:31.63#ibcon#about to write, iclass 18, count 0 2006.285.17:28:31.63#ibcon#wrote, iclass 18, count 0 2006.285.17:28:31.63#ibcon#about to read 3, iclass 18, count 0 2006.285.17:28:31.67#ibcon#read 3, iclass 18, count 0 2006.285.17:28:31.67#ibcon#about to read 4, iclass 18, count 0 2006.285.17:28:31.67#ibcon#read 4, iclass 18, count 0 2006.285.17:28:31.67#ibcon#about to read 5, iclass 18, count 0 2006.285.17:28:31.67#ibcon#read 5, iclass 18, count 0 2006.285.17:28:31.67#ibcon#about to read 6, iclass 18, count 0 2006.285.17:28:31.67#ibcon#read 6, iclass 18, count 0 2006.285.17:28:31.67#ibcon#end of sib2, iclass 18, count 0 2006.285.17:28:31.67#ibcon#*after write, iclass 18, count 0 2006.285.17:28:31.67#ibcon#*before return 0, iclass 18, count 0 2006.285.17:28:31.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:28:31.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:28:31.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.17:28:31.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.17:28:31.67$vck44/vb=8,4 2006.285.17:28:31.67#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.17:28:31.67#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.17:28:31.67#ibcon#ireg 11 cls_cnt 2 2006.285.17:28:31.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:28:31.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:28:31.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:28:31.73#ibcon#enter wrdev, iclass 20, count 2 2006.285.17:28:31.73#ibcon#first serial, iclass 20, count 2 2006.285.17:28:31.73#ibcon#enter sib2, iclass 20, count 2 2006.285.17:28:31.73#ibcon#flushed, iclass 20, count 2 2006.285.17:28:31.73#ibcon#about to write, iclass 20, count 2 2006.285.17:28:31.73#ibcon#wrote, iclass 20, count 2 2006.285.17:28:31.73#ibcon#about to read 3, iclass 20, count 2 2006.285.17:28:31.75#ibcon#read 3, iclass 20, count 2 2006.285.17:28:31.75#ibcon#about to read 4, iclass 20, count 2 2006.285.17:28:31.75#ibcon#read 4, iclass 20, count 2 2006.285.17:28:31.75#ibcon#about to read 5, iclass 20, count 2 2006.285.17:28:31.75#ibcon#read 5, iclass 20, count 2 2006.285.17:28:31.75#ibcon#about to read 6, iclass 20, count 2 2006.285.17:28:31.75#ibcon#read 6, iclass 20, count 2 2006.285.17:28:31.75#ibcon#end of sib2, iclass 20, count 2 2006.285.17:28:31.75#ibcon#*mode == 0, iclass 20, count 2 2006.285.17:28:31.75#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.17:28:31.75#ibcon#[27=AT08-04\r\n] 2006.285.17:28:31.75#ibcon#*before write, iclass 20, count 2 2006.285.17:28:31.75#ibcon#enter sib2, iclass 20, count 2 2006.285.17:28:31.75#ibcon#flushed, iclass 20, count 2 2006.285.17:28:31.75#ibcon#about to write, iclass 20, count 2 2006.285.17:28:31.75#ibcon#wrote, iclass 20, count 2 2006.285.17:28:31.75#ibcon#about to read 3, iclass 20, count 2 2006.285.17:28:31.78#ibcon#read 3, iclass 20, count 2 2006.285.17:28:31.78#ibcon#about to read 4, iclass 20, count 2 2006.285.17:28:31.78#ibcon#read 4, iclass 20, count 2 2006.285.17:28:31.78#ibcon#about to read 5, iclass 20, count 2 2006.285.17:28:31.78#ibcon#read 5, iclass 20, count 2 2006.285.17:28:31.78#ibcon#about to read 6, iclass 20, count 2 2006.285.17:28:31.78#ibcon#read 6, iclass 20, count 2 2006.285.17:28:31.78#ibcon#end of sib2, iclass 20, count 2 2006.285.17:28:31.78#ibcon#*after write, iclass 20, count 2 2006.285.17:28:31.78#ibcon#*before return 0, iclass 20, count 2 2006.285.17:28:31.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:28:31.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:28:31.78#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.17:28:31.78#ibcon#ireg 7 cls_cnt 0 2006.285.17:28:31.78#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:28:31.90#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:28:31.90#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:28:31.90#ibcon#enter wrdev, iclass 20, count 0 2006.285.17:28:31.90#ibcon#first serial, iclass 20, count 0 2006.285.17:28:31.90#ibcon#enter sib2, iclass 20, count 0 2006.285.17:28:31.90#ibcon#flushed, iclass 20, count 0 2006.285.17:28:31.90#ibcon#about to write, iclass 20, count 0 2006.285.17:28:31.90#ibcon#wrote, iclass 20, count 0 2006.285.17:28:31.90#ibcon#about to read 3, iclass 20, count 0 2006.285.17:28:31.92#ibcon#read 3, iclass 20, count 0 2006.285.17:28:31.92#ibcon#about to read 4, iclass 20, count 0 2006.285.17:28:31.92#ibcon#read 4, iclass 20, count 0 2006.285.17:28:31.92#ibcon#about to read 5, iclass 20, count 0 2006.285.17:28:31.92#ibcon#read 5, iclass 20, count 0 2006.285.17:28:31.92#ibcon#about to read 6, iclass 20, count 0 2006.285.17:28:31.92#ibcon#read 6, iclass 20, count 0 2006.285.17:28:31.92#ibcon#end of sib2, iclass 20, count 0 2006.285.17:28:31.92#ibcon#*mode == 0, iclass 20, count 0 2006.285.17:28:31.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.17:28:31.92#ibcon#[27=USB\r\n] 2006.285.17:28:31.92#ibcon#*before write, iclass 20, count 0 2006.285.17:28:31.92#ibcon#enter sib2, iclass 20, count 0 2006.285.17:28:31.92#ibcon#flushed, iclass 20, count 0 2006.285.17:28:31.92#ibcon#about to write, iclass 20, count 0 2006.285.17:28:31.92#ibcon#wrote, iclass 20, count 0 2006.285.17:28:31.92#ibcon#about to read 3, iclass 20, count 0 2006.285.17:28:31.95#ibcon#read 3, iclass 20, count 0 2006.285.17:28:31.95#ibcon#about to read 4, iclass 20, count 0 2006.285.17:28:31.95#ibcon#read 4, iclass 20, count 0 2006.285.17:28:31.95#ibcon#about to read 5, iclass 20, count 0 2006.285.17:28:31.95#ibcon#read 5, iclass 20, count 0 2006.285.17:28:31.95#ibcon#about to read 6, iclass 20, count 0 2006.285.17:28:31.95#ibcon#read 6, iclass 20, count 0 2006.285.17:28:31.95#ibcon#end of sib2, iclass 20, count 0 2006.285.17:28:31.95#ibcon#*after write, iclass 20, count 0 2006.285.17:28:31.95#ibcon#*before return 0, iclass 20, count 0 2006.285.17:28:31.95#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:28:31.95#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:28:31.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.17:28:31.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.17:28:31.95$vck44/vabw=wide 2006.285.17:28:31.95#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.17:28:31.95#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.17:28:31.95#ibcon#ireg 8 cls_cnt 0 2006.285.17:28:31.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:28:31.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:28:31.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:28:31.95#ibcon#enter wrdev, iclass 22, count 0 2006.285.17:28:31.95#ibcon#first serial, iclass 22, count 0 2006.285.17:28:31.95#ibcon#enter sib2, iclass 22, count 0 2006.285.17:28:31.95#ibcon#flushed, iclass 22, count 0 2006.285.17:28:31.95#ibcon#about to write, iclass 22, count 0 2006.285.17:28:31.95#ibcon#wrote, iclass 22, count 0 2006.285.17:28:31.95#ibcon#about to read 3, iclass 22, count 0 2006.285.17:28:31.97#ibcon#read 3, iclass 22, count 0 2006.285.17:28:32.16#ibcon#about to read 4, iclass 22, count 0 2006.285.17:28:32.16#ibcon#read 4, iclass 22, count 0 2006.285.17:28:32.16#ibcon#about to read 5, iclass 22, count 0 2006.285.17:28:32.16#ibcon#read 5, iclass 22, count 0 2006.285.17:28:32.16#ibcon#about to read 6, iclass 22, count 0 2006.285.17:28:32.16#ibcon#read 6, iclass 22, count 0 2006.285.17:28:32.16#ibcon#end of sib2, iclass 22, count 0 2006.285.17:28:32.16#ibcon#*mode == 0, iclass 22, count 0 2006.285.17:28:32.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.17:28:32.16#ibcon#[25=BW32\r\n] 2006.285.17:28:32.16#ibcon#*before write, iclass 22, count 0 2006.285.17:28:32.16#ibcon#enter sib2, iclass 22, count 0 2006.285.17:28:32.16#ibcon#flushed, iclass 22, count 0 2006.285.17:28:32.16#ibcon#about to write, iclass 22, count 0 2006.285.17:28:32.16#ibcon#wrote, iclass 22, count 0 2006.285.17:28:32.16#ibcon#about to read 3, iclass 22, count 0 2006.285.17:28:32.19#ibcon#read 3, iclass 22, count 0 2006.285.17:28:32.19#ibcon#about to read 4, iclass 22, count 0 2006.285.17:28:32.19#ibcon#read 4, iclass 22, count 0 2006.285.17:28:32.19#ibcon#about to read 5, iclass 22, count 0 2006.285.17:28:32.19#ibcon#read 5, iclass 22, count 0 2006.285.17:28:32.19#ibcon#about to read 6, iclass 22, count 0 2006.285.17:28:32.19#ibcon#read 6, iclass 22, count 0 2006.285.17:28:32.19#ibcon#end of sib2, iclass 22, count 0 2006.285.17:28:32.19#ibcon#*after write, iclass 22, count 0 2006.285.17:28:32.19#ibcon#*before return 0, iclass 22, count 0 2006.285.17:28:32.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:28:32.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:28:32.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.17:28:32.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.17:28:32.19$vck44/vbbw=wide 2006.285.17:28:32.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.17:28:32.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.17:28:32.19#ibcon#ireg 8 cls_cnt 0 2006.285.17:28:32.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:28:32.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:28:32.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:28:32.19#ibcon#enter wrdev, iclass 24, count 0 2006.285.17:28:32.19#ibcon#first serial, iclass 24, count 0 2006.285.17:28:32.19#ibcon#enter sib2, iclass 24, count 0 2006.285.17:28:32.19#ibcon#flushed, iclass 24, count 0 2006.285.17:28:32.19#ibcon#about to write, iclass 24, count 0 2006.285.17:28:32.19#ibcon#wrote, iclass 24, count 0 2006.285.17:28:32.19#ibcon#about to read 3, iclass 24, count 0 2006.285.17:28:32.21#ibcon#read 3, iclass 24, count 0 2006.285.17:28:32.21#ibcon#about to read 4, iclass 24, count 0 2006.285.17:28:32.21#ibcon#read 4, iclass 24, count 0 2006.285.17:28:32.21#ibcon#about to read 5, iclass 24, count 0 2006.285.17:28:32.21#ibcon#read 5, iclass 24, count 0 2006.285.17:28:32.21#ibcon#about to read 6, iclass 24, count 0 2006.285.17:28:32.21#ibcon#read 6, iclass 24, count 0 2006.285.17:28:32.21#ibcon#end of sib2, iclass 24, count 0 2006.285.17:28:32.21#ibcon#*mode == 0, iclass 24, count 0 2006.285.17:28:32.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.17:28:32.21#ibcon#[27=BW32\r\n] 2006.285.17:28:32.21#ibcon#*before write, iclass 24, count 0 2006.285.17:28:32.21#ibcon#enter sib2, iclass 24, count 0 2006.285.17:28:32.21#ibcon#flushed, iclass 24, count 0 2006.285.17:28:32.21#ibcon#about to write, iclass 24, count 0 2006.285.17:28:32.21#ibcon#wrote, iclass 24, count 0 2006.285.17:28:32.21#ibcon#about to read 3, iclass 24, count 0 2006.285.17:28:32.24#ibcon#read 3, iclass 24, count 0 2006.285.17:28:32.24#ibcon#about to read 4, iclass 24, count 0 2006.285.17:28:32.24#ibcon#read 4, iclass 24, count 0 2006.285.17:28:32.24#ibcon#about to read 5, iclass 24, count 0 2006.285.17:28:32.24#ibcon#read 5, iclass 24, count 0 2006.285.17:28:32.24#ibcon#about to read 6, iclass 24, count 0 2006.285.17:28:32.24#ibcon#read 6, iclass 24, count 0 2006.285.17:28:32.24#ibcon#end of sib2, iclass 24, count 0 2006.285.17:28:32.24#ibcon#*after write, iclass 24, count 0 2006.285.17:28:32.24#ibcon#*before return 0, iclass 24, count 0 2006.285.17:28:32.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:28:32.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:28:32.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.17:28:32.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.17:28:32.24$setupk4/ifdk4 2006.285.17:28:32.24$ifdk4/lo= 2006.285.17:28:32.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.17:28:32.24$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.17:28:32.24$ifdk4/patch= 2006.285.17:28:32.24$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.17:28:32.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.17:28:32.24$setupk4/!*+20s 2006.285.17:28:38.30#abcon#<5=/00 0.2 1.0 16.86 981014.8\r\n> 2006.285.17:28:38.32#abcon#{5=INTERFACE CLEAR} 2006.285.17:28:38.38#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:28:39.14#trakl#Source acquired 2006.285.17:28:39.14#flagr#flagr/antenna,acquired 2006.285.17:28:45.83$setupk4/"tpicd 2006.285.17:28:45.83$setupk4/echo=off 2006.285.17:28:45.83$setupk4/xlog=off 2006.285.17:28:45.83:!2006.285.17:30:41 2006.285.17:30:41.00:preob 2006.285.17:30:41.14/onsource/TRACKING 2006.285.17:30:41.14:!2006.285.17:30:51 2006.285.17:30:51.00:"tape 2006.285.17:30:51.00:"st=record 2006.285.17:30:51.00:data_valid=on 2006.285.17:30:51.00:midob 2006.285.17:30:51.14/onsource/TRACKING 2006.285.17:30:51.14/wx/16.81,1014.8,99 2006.285.17:30:51.35/cable/+6.5020E-03 2006.285.17:30:52.44/va/01,07,usb,yes,31,34 2006.285.17:30:52.44/va/02,06,usb,yes,31,32 2006.285.17:30:52.44/va/03,07,usb,yes,31,33 2006.285.17:30:52.44/va/04,06,usb,yes,33,34 2006.285.17:30:52.44/va/05,03,usb,yes,32,32 2006.285.17:30:52.44/va/06,04,usb,yes,29,28 2006.285.17:30:52.44/va/07,04,usb,yes,29,30 2006.285.17:30:52.44/va/08,03,usb,yes,30,37 2006.285.17:30:52.67/valo/01,524.99,yes,locked 2006.285.17:30:52.67/valo/02,534.99,yes,locked 2006.285.17:30:52.67/valo/03,564.99,yes,locked 2006.285.17:30:52.67/valo/04,624.99,yes,locked 2006.285.17:30:52.67/valo/05,734.99,yes,locked 2006.285.17:30:52.67/valo/06,814.99,yes,locked 2006.285.17:30:52.67/valo/07,864.99,yes,locked 2006.285.17:30:52.67/valo/08,884.99,yes,locked 2006.285.17:30:53.76/vb/01,04,usb,yes,30,28 2006.285.17:30:53.76/vb/02,05,usb,yes,28,28 2006.285.17:30:53.76/vb/03,04,usb,yes,29,32 2006.285.17:30:53.76/vb/04,05,usb,yes,30,29 2006.285.17:30:53.76/vb/05,04,usb,yes,26,28 2006.285.17:30:53.76/vb/06,03,usb,yes,38,33 2006.285.17:30:53.76/vb/07,04,usb,yes,30,30 2006.285.17:30:53.76/vb/08,04,usb,yes,28,31 2006.285.17:30:53.99/vblo/01,629.99,yes,locked 2006.285.17:30:53.99/vblo/02,634.99,yes,locked 2006.285.17:30:53.99/vblo/03,649.99,yes,locked 2006.285.17:30:53.99/vblo/04,679.99,yes,locked 2006.285.17:30:53.99/vblo/05,709.99,yes,locked 2006.285.17:30:53.99/vblo/06,719.99,yes,locked 2006.285.17:30:53.99/vblo/07,734.99,yes,locked 2006.285.17:30:53.99/vblo/08,744.99,yes,locked 2006.285.17:30:54.14/vabw/8 2006.285.17:30:54.29/vbbw/8 2006.285.17:30:54.39/xfe/off,on,12.2 2006.285.17:30:54.77/ifatt/23,28,28,28 2006.285.17:30:55.08/fmout-gps/S +2.68E-07 2006.285.17:30:55.10:!2006.285.17:38:31 2006.285.17:38:31.00:data_valid=off 2006.285.17:38:31.00:"et 2006.285.17:38:31.00:!+3s 2006.285.17:38:34.01:"tape 2006.285.17:38:34.01:postob 2006.285.17:38:34.20/cable/+6.5009E-03 2006.285.17:38:34.20/wx/16.59,1014.7,99 2006.285.17:38:35.08/fmout-gps/S +2.74E-07 2006.285.17:38:35.08:scan_name=285-1745,jd0610,40 2006.285.17:38:35.08:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.285.17:38:36.14#flagr#flagr/antenna,new-source 2006.285.17:38:36.14:checkk5 2006.285.17:38:36.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.17:38:36.95/chk_autoobs//k5ts2/ autoobs is running! 2006.285.17:38:37.74/chk_autoobs//k5ts3/ autoobs is running! 2006.285.17:38:38.38/chk_autoobs//k5ts4/ autoobs is running! 2006.285.17:38:38.74/chk_obsdata//k5ts1/T2851730??a.dat file size is correct (nominal:1840MB, actual:1840MB). 2006.285.17:38:39.25/chk_obsdata//k5ts2/T2851730??b.dat file size is correct (nominal:1840MB, actual:1840MB). 2006.285.17:38:39.61/chk_obsdata//k5ts3/T2851730??c.dat file size is correct (nominal:1840MB, actual:1840MB). 2006.285.17:38:39.96/chk_obsdata//k5ts4/T2851730??d.dat file size is correct (nominal:1840MB, actual:1840MB). 2006.285.17:38:40.81/k5log//k5ts1_log_newline 2006.285.17:38:41.79/k5log//k5ts2_log_newline 2006.285.17:38:42.56/k5log//k5ts3_log_newline 2006.285.17:38:43.37/k5log//k5ts4_log_newline 2006.285.17:38:43.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.17:38:43.39:setupk4=1 2006.285.17:38:43.39$setupk4/echo=on 2006.285.17:38:43.39$setupk4/pcalon 2006.285.17:38:43.39$pcalon/"no phase cal control is implemented here 2006.285.17:38:43.39$setupk4/"tpicd=stop 2006.285.17:38:43.39$setupk4/"rec=synch_on 2006.285.17:38:43.39$setupk4/"rec_mode=128 2006.285.17:38:43.39$setupk4/!* 2006.285.17:38:43.39$setupk4/recpk4 2006.285.17:38:43.39$recpk4/recpatch= 2006.285.17:38:43.39$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.17:38:43.39$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.17:38:43.39$setupk4/vck44 2006.285.17:38:43.39$vck44/valo=1,524.99 2006.285.17:38:43.39#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.17:38:43.39#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.17:38:43.39#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:43.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:38:43.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:38:43.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:38:43.39#ibcon#enter wrdev, iclass 17, count 0 2006.285.17:38:43.39#ibcon#first serial, iclass 17, count 0 2006.285.17:38:43.39#ibcon#enter sib2, iclass 17, count 0 2006.285.17:38:43.39#ibcon#flushed, iclass 17, count 0 2006.285.17:38:43.39#ibcon#about to write, iclass 17, count 0 2006.285.17:38:43.39#ibcon#wrote, iclass 17, count 0 2006.285.17:38:43.39#ibcon#about to read 3, iclass 17, count 0 2006.285.17:38:43.41#ibcon#read 3, iclass 17, count 0 2006.285.17:38:43.41#ibcon#about to read 4, iclass 17, count 0 2006.285.17:38:43.41#ibcon#read 4, iclass 17, count 0 2006.285.17:38:43.41#ibcon#about to read 5, iclass 17, count 0 2006.285.17:38:43.41#ibcon#read 5, iclass 17, count 0 2006.285.17:38:43.41#ibcon#about to read 6, iclass 17, count 0 2006.285.17:38:43.41#ibcon#read 6, iclass 17, count 0 2006.285.17:38:43.41#ibcon#end of sib2, iclass 17, count 0 2006.285.17:38:43.41#ibcon#*mode == 0, iclass 17, count 0 2006.285.17:38:43.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.17:38:43.41#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.17:38:43.41#ibcon#*before write, iclass 17, count 0 2006.285.17:38:43.41#ibcon#enter sib2, iclass 17, count 0 2006.285.17:38:43.41#ibcon#flushed, iclass 17, count 0 2006.285.17:38:43.41#ibcon#about to write, iclass 17, count 0 2006.285.17:38:43.41#ibcon#wrote, iclass 17, count 0 2006.285.17:38:43.41#ibcon#about to read 3, iclass 17, count 0 2006.285.17:38:43.46#ibcon#read 3, iclass 17, count 0 2006.285.17:38:43.46#ibcon#about to read 4, iclass 17, count 0 2006.285.17:38:43.46#ibcon#read 4, iclass 17, count 0 2006.285.17:38:43.46#ibcon#about to read 5, iclass 17, count 0 2006.285.17:38:43.46#ibcon#read 5, iclass 17, count 0 2006.285.17:38:43.46#ibcon#about to read 6, iclass 17, count 0 2006.285.17:38:43.46#ibcon#read 6, iclass 17, count 0 2006.285.17:38:43.46#ibcon#end of sib2, iclass 17, count 0 2006.285.17:38:43.46#ibcon#*after write, iclass 17, count 0 2006.285.17:38:43.46#ibcon#*before return 0, iclass 17, count 0 2006.285.17:38:43.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:38:43.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:38:43.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.17:38:43.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.17:38:43.46$vck44/va=1,7 2006.285.17:38:43.46#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.17:38:43.46#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.17:38:43.46#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:43.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:38:43.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:38:43.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:38:43.46#ibcon#enter wrdev, iclass 19, count 2 2006.285.17:38:43.46#ibcon#first serial, iclass 19, count 2 2006.285.17:38:43.46#ibcon#enter sib2, iclass 19, count 2 2006.285.17:38:43.46#ibcon#flushed, iclass 19, count 2 2006.285.17:38:43.46#ibcon#about to write, iclass 19, count 2 2006.285.17:38:43.46#ibcon#wrote, iclass 19, count 2 2006.285.17:38:43.46#ibcon#about to read 3, iclass 19, count 2 2006.285.17:38:43.48#ibcon#read 3, iclass 19, count 2 2006.285.17:38:43.48#ibcon#about to read 4, iclass 19, count 2 2006.285.17:38:43.48#ibcon#read 4, iclass 19, count 2 2006.285.17:38:43.48#ibcon#about to read 5, iclass 19, count 2 2006.285.17:38:43.48#ibcon#read 5, iclass 19, count 2 2006.285.17:38:43.48#ibcon#about to read 6, iclass 19, count 2 2006.285.17:38:43.48#ibcon#read 6, iclass 19, count 2 2006.285.17:38:43.48#ibcon#end of sib2, iclass 19, count 2 2006.285.17:38:43.48#ibcon#*mode == 0, iclass 19, count 2 2006.285.17:38:43.48#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.17:38:43.48#ibcon#[25=AT01-07\r\n] 2006.285.17:38:43.48#ibcon#*before write, iclass 19, count 2 2006.285.17:38:43.48#ibcon#enter sib2, iclass 19, count 2 2006.285.17:38:43.48#ibcon#flushed, iclass 19, count 2 2006.285.17:38:43.48#ibcon#about to write, iclass 19, count 2 2006.285.17:38:43.48#ibcon#wrote, iclass 19, count 2 2006.285.17:38:43.48#ibcon#about to read 3, iclass 19, count 2 2006.285.17:38:43.51#ibcon#read 3, iclass 19, count 2 2006.285.17:38:43.51#ibcon#about to read 4, iclass 19, count 2 2006.285.17:38:43.51#ibcon#read 4, iclass 19, count 2 2006.285.17:38:43.51#ibcon#about to read 5, iclass 19, count 2 2006.285.17:38:43.51#ibcon#read 5, iclass 19, count 2 2006.285.17:38:43.51#ibcon#about to read 6, iclass 19, count 2 2006.285.17:38:43.51#ibcon#read 6, iclass 19, count 2 2006.285.17:38:43.51#ibcon#end of sib2, iclass 19, count 2 2006.285.17:38:43.51#ibcon#*after write, iclass 19, count 2 2006.285.17:38:43.51#ibcon#*before return 0, iclass 19, count 2 2006.285.17:38:43.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:38:43.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:38:43.51#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.17:38:43.51#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:43.51#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:38:43.63#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:38:43.63#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:38:43.63#ibcon#enter wrdev, iclass 19, count 0 2006.285.17:38:43.63#ibcon#first serial, iclass 19, count 0 2006.285.17:38:43.63#ibcon#enter sib2, iclass 19, count 0 2006.285.17:38:43.63#ibcon#flushed, iclass 19, count 0 2006.285.17:38:43.63#ibcon#about to write, iclass 19, count 0 2006.285.17:38:43.63#ibcon#wrote, iclass 19, count 0 2006.285.17:38:43.63#ibcon#about to read 3, iclass 19, count 0 2006.285.17:38:43.65#ibcon#read 3, iclass 19, count 0 2006.285.17:38:43.65#ibcon#about to read 4, iclass 19, count 0 2006.285.17:38:43.65#ibcon#read 4, iclass 19, count 0 2006.285.17:38:43.65#ibcon#about to read 5, iclass 19, count 0 2006.285.17:38:43.65#ibcon#read 5, iclass 19, count 0 2006.285.17:38:43.65#ibcon#about to read 6, iclass 19, count 0 2006.285.17:38:43.65#ibcon#read 6, iclass 19, count 0 2006.285.17:38:43.65#ibcon#end of sib2, iclass 19, count 0 2006.285.17:38:43.65#ibcon#*mode == 0, iclass 19, count 0 2006.285.17:38:43.65#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.17:38:43.65#ibcon#[25=USB\r\n] 2006.285.17:38:43.65#ibcon#*before write, iclass 19, count 0 2006.285.17:38:43.65#ibcon#enter sib2, iclass 19, count 0 2006.285.17:38:43.65#ibcon#flushed, iclass 19, count 0 2006.285.17:38:43.65#ibcon#about to write, iclass 19, count 0 2006.285.17:38:43.65#ibcon#wrote, iclass 19, count 0 2006.285.17:38:43.65#ibcon#about to read 3, iclass 19, count 0 2006.285.17:38:43.68#ibcon#read 3, iclass 19, count 0 2006.285.17:38:43.68#ibcon#about to read 4, iclass 19, count 0 2006.285.17:38:43.68#ibcon#read 4, iclass 19, count 0 2006.285.17:38:43.68#ibcon#about to read 5, iclass 19, count 0 2006.285.17:38:43.68#ibcon#read 5, iclass 19, count 0 2006.285.17:38:43.68#ibcon#about to read 6, iclass 19, count 0 2006.285.17:38:43.68#ibcon#read 6, iclass 19, count 0 2006.285.17:38:43.68#ibcon#end of sib2, iclass 19, count 0 2006.285.17:38:43.68#ibcon#*after write, iclass 19, count 0 2006.285.17:38:43.68#ibcon#*before return 0, iclass 19, count 0 2006.285.17:38:43.68#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:38:43.68#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:38:43.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.17:38:43.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.17:38:43.68$vck44/valo=2,534.99 2006.285.17:38:43.68#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.17:38:43.68#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.17:38:43.68#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:43.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:38:43.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:38:43.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:38:43.68#ibcon#enter wrdev, iclass 21, count 0 2006.285.17:38:43.68#ibcon#first serial, iclass 21, count 0 2006.285.17:38:43.68#ibcon#enter sib2, iclass 21, count 0 2006.285.17:38:43.68#ibcon#flushed, iclass 21, count 0 2006.285.17:38:43.68#ibcon#about to write, iclass 21, count 0 2006.285.17:38:43.68#ibcon#wrote, iclass 21, count 0 2006.285.17:38:43.68#ibcon#about to read 3, iclass 21, count 0 2006.285.17:38:43.70#ibcon#read 3, iclass 21, count 0 2006.285.17:38:43.70#ibcon#about to read 4, iclass 21, count 0 2006.285.17:38:43.70#ibcon#read 4, iclass 21, count 0 2006.285.17:38:43.70#ibcon#about to read 5, iclass 21, count 0 2006.285.17:38:43.70#ibcon#read 5, iclass 21, count 0 2006.285.17:38:43.70#ibcon#about to read 6, iclass 21, count 0 2006.285.17:38:43.70#ibcon#read 6, iclass 21, count 0 2006.285.17:38:43.70#ibcon#end of sib2, iclass 21, count 0 2006.285.17:38:43.70#ibcon#*mode == 0, iclass 21, count 0 2006.285.17:38:43.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.17:38:43.70#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.17:38:43.70#ibcon#*before write, iclass 21, count 0 2006.285.17:38:43.70#ibcon#enter sib2, iclass 21, count 0 2006.285.17:38:43.70#ibcon#flushed, iclass 21, count 0 2006.285.17:38:43.70#ibcon#about to write, iclass 21, count 0 2006.285.17:38:43.70#ibcon#wrote, iclass 21, count 0 2006.285.17:38:43.70#ibcon#about to read 3, iclass 21, count 0 2006.285.17:38:43.74#ibcon#read 3, iclass 21, count 0 2006.285.17:38:43.74#ibcon#about to read 4, iclass 21, count 0 2006.285.17:38:43.74#ibcon#read 4, iclass 21, count 0 2006.285.17:38:43.74#ibcon#about to read 5, iclass 21, count 0 2006.285.17:38:43.74#ibcon#read 5, iclass 21, count 0 2006.285.17:38:43.74#ibcon#about to read 6, iclass 21, count 0 2006.285.17:38:43.74#ibcon#read 6, iclass 21, count 0 2006.285.17:38:43.74#ibcon#end of sib2, iclass 21, count 0 2006.285.17:38:43.74#ibcon#*after write, iclass 21, count 0 2006.285.17:38:43.74#ibcon#*before return 0, iclass 21, count 0 2006.285.17:38:43.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:38:43.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:38:43.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.17:38:43.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.17:38:43.74$vck44/va=2,6 2006.285.17:38:43.74#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.17:38:43.74#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.17:38:43.74#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:43.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:38:43.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:38:43.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:38:43.80#ibcon#enter wrdev, iclass 23, count 2 2006.285.17:38:43.80#ibcon#first serial, iclass 23, count 2 2006.285.17:38:43.80#ibcon#enter sib2, iclass 23, count 2 2006.285.17:38:43.80#ibcon#flushed, iclass 23, count 2 2006.285.17:38:43.80#ibcon#about to write, iclass 23, count 2 2006.285.17:38:43.80#ibcon#wrote, iclass 23, count 2 2006.285.17:38:43.80#ibcon#about to read 3, iclass 23, count 2 2006.285.17:38:43.82#ibcon#read 3, iclass 23, count 2 2006.285.17:38:43.82#ibcon#about to read 4, iclass 23, count 2 2006.285.17:38:43.82#ibcon#read 4, iclass 23, count 2 2006.285.17:38:43.82#ibcon#about to read 5, iclass 23, count 2 2006.285.17:38:43.82#ibcon#read 5, iclass 23, count 2 2006.285.17:38:43.82#ibcon#about to read 6, iclass 23, count 2 2006.285.17:38:43.82#ibcon#read 6, iclass 23, count 2 2006.285.17:38:43.82#ibcon#end of sib2, iclass 23, count 2 2006.285.17:38:43.82#ibcon#*mode == 0, iclass 23, count 2 2006.285.17:38:43.82#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.17:38:43.82#ibcon#[25=AT02-06\r\n] 2006.285.17:38:43.82#ibcon#*before write, iclass 23, count 2 2006.285.17:38:43.82#ibcon#enter sib2, iclass 23, count 2 2006.285.17:38:43.82#ibcon#flushed, iclass 23, count 2 2006.285.17:38:43.82#ibcon#about to write, iclass 23, count 2 2006.285.17:38:43.82#ibcon#wrote, iclass 23, count 2 2006.285.17:38:43.82#ibcon#about to read 3, iclass 23, count 2 2006.285.17:38:43.85#ibcon#read 3, iclass 23, count 2 2006.285.17:38:43.85#ibcon#about to read 4, iclass 23, count 2 2006.285.17:38:43.85#ibcon#read 4, iclass 23, count 2 2006.285.17:38:43.85#ibcon#about to read 5, iclass 23, count 2 2006.285.17:38:43.85#ibcon#read 5, iclass 23, count 2 2006.285.17:38:43.85#ibcon#about to read 6, iclass 23, count 2 2006.285.17:38:43.85#ibcon#read 6, iclass 23, count 2 2006.285.17:38:43.85#ibcon#end of sib2, iclass 23, count 2 2006.285.17:38:43.85#ibcon#*after write, iclass 23, count 2 2006.285.17:38:43.85#ibcon#*before return 0, iclass 23, count 2 2006.285.17:38:43.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:38:43.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:38:43.85#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.17:38:43.85#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:43.85#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:38:43.97#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:38:43.97#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:38:43.97#ibcon#enter wrdev, iclass 23, count 0 2006.285.17:38:43.97#ibcon#first serial, iclass 23, count 0 2006.285.17:38:43.97#ibcon#enter sib2, iclass 23, count 0 2006.285.17:38:43.97#ibcon#flushed, iclass 23, count 0 2006.285.17:38:43.97#ibcon#about to write, iclass 23, count 0 2006.285.17:38:43.97#ibcon#wrote, iclass 23, count 0 2006.285.17:38:43.97#ibcon#about to read 3, iclass 23, count 0 2006.285.17:38:43.99#ibcon#read 3, iclass 23, count 0 2006.285.17:38:43.99#ibcon#about to read 4, iclass 23, count 0 2006.285.17:38:43.99#ibcon#read 4, iclass 23, count 0 2006.285.17:38:43.99#ibcon#about to read 5, iclass 23, count 0 2006.285.17:38:43.99#ibcon#read 5, iclass 23, count 0 2006.285.17:38:43.99#ibcon#about to read 6, iclass 23, count 0 2006.285.17:38:43.99#ibcon#read 6, iclass 23, count 0 2006.285.17:38:43.99#ibcon#end of sib2, iclass 23, count 0 2006.285.17:38:43.99#ibcon#*mode == 0, iclass 23, count 0 2006.285.17:38:43.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.17:38:43.99#ibcon#[25=USB\r\n] 2006.285.17:38:43.99#ibcon#*before write, iclass 23, count 0 2006.285.17:38:43.99#ibcon#enter sib2, iclass 23, count 0 2006.285.17:38:43.99#ibcon#flushed, iclass 23, count 0 2006.285.17:38:43.99#ibcon#about to write, iclass 23, count 0 2006.285.17:38:43.99#ibcon#wrote, iclass 23, count 0 2006.285.17:38:43.99#ibcon#about to read 3, iclass 23, count 0 2006.285.17:38:44.02#ibcon#read 3, iclass 23, count 0 2006.285.17:38:44.02#ibcon#about to read 4, iclass 23, count 0 2006.285.17:38:44.02#ibcon#read 4, iclass 23, count 0 2006.285.17:38:44.02#ibcon#about to read 5, iclass 23, count 0 2006.285.17:38:44.02#ibcon#read 5, iclass 23, count 0 2006.285.17:38:44.02#ibcon#about to read 6, iclass 23, count 0 2006.285.17:38:44.02#ibcon#read 6, iclass 23, count 0 2006.285.17:38:44.02#ibcon#end of sib2, iclass 23, count 0 2006.285.17:38:44.02#ibcon#*after write, iclass 23, count 0 2006.285.17:38:44.02#ibcon#*before return 0, iclass 23, count 0 2006.285.17:38:44.02#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:38:44.02#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:38:44.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.17:38:44.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.17:38:44.02$vck44/valo=3,564.99 2006.285.17:38:44.02#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.17:38:44.02#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.17:38:44.02#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:44.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:38:44.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:38:44.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:38:44.02#ibcon#enter wrdev, iclass 25, count 0 2006.285.17:38:44.02#ibcon#first serial, iclass 25, count 0 2006.285.17:38:44.02#ibcon#enter sib2, iclass 25, count 0 2006.285.17:38:44.02#ibcon#flushed, iclass 25, count 0 2006.285.17:38:44.02#ibcon#about to write, iclass 25, count 0 2006.285.17:38:44.02#ibcon#wrote, iclass 25, count 0 2006.285.17:38:44.02#ibcon#about to read 3, iclass 25, count 0 2006.285.17:38:44.04#ibcon#read 3, iclass 25, count 0 2006.285.17:38:44.61#ibcon#about to read 4, iclass 25, count 0 2006.285.17:38:44.61#ibcon#read 4, iclass 25, count 0 2006.285.17:38:44.61#ibcon#about to read 5, iclass 25, count 0 2006.285.17:38:44.61#ibcon#read 5, iclass 25, count 0 2006.285.17:38:44.61#ibcon#about to read 6, iclass 25, count 0 2006.285.17:38:44.61#ibcon#read 6, iclass 25, count 0 2006.285.17:38:44.61#ibcon#end of sib2, iclass 25, count 0 2006.285.17:38:44.61#ibcon#*mode == 0, iclass 25, count 0 2006.285.17:38:44.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.17:38:44.61#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.17:38:44.61#ibcon#*before write, iclass 25, count 0 2006.285.17:38:44.61#ibcon#enter sib2, iclass 25, count 0 2006.285.17:38:44.61#ibcon#flushed, iclass 25, count 0 2006.285.17:38:44.61#ibcon#about to write, iclass 25, count 0 2006.285.17:38:44.61#ibcon#wrote, iclass 25, count 0 2006.285.17:38:44.61#ibcon#about to read 3, iclass 25, count 0 2006.285.17:38:44.66#ibcon#read 3, iclass 25, count 0 2006.285.17:38:44.66#ibcon#about to read 4, iclass 25, count 0 2006.285.17:38:44.66#ibcon#read 4, iclass 25, count 0 2006.285.17:38:44.66#ibcon#about to read 5, iclass 25, count 0 2006.285.17:38:44.66#ibcon#read 5, iclass 25, count 0 2006.285.17:38:44.66#ibcon#about to read 6, iclass 25, count 0 2006.285.17:38:44.66#ibcon#read 6, iclass 25, count 0 2006.285.17:38:44.66#ibcon#end of sib2, iclass 25, count 0 2006.285.17:38:44.66#ibcon#*after write, iclass 25, count 0 2006.285.17:38:44.66#ibcon#*before return 0, iclass 25, count 0 2006.285.17:38:44.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:38:44.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:38:44.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.17:38:44.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.17:38:44.66$vck44/va=3,7 2006.285.17:38:44.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.17:38:44.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.17:38:44.66#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:44.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:38:44.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:38:44.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:38:44.66#ibcon#enter wrdev, iclass 27, count 2 2006.285.17:38:44.66#ibcon#first serial, iclass 27, count 2 2006.285.17:38:44.66#ibcon#enter sib2, iclass 27, count 2 2006.285.17:38:44.66#ibcon#flushed, iclass 27, count 2 2006.285.17:38:44.66#ibcon#about to write, iclass 27, count 2 2006.285.17:38:44.66#ibcon#wrote, iclass 27, count 2 2006.285.17:38:44.66#ibcon#about to read 3, iclass 27, count 2 2006.285.17:38:44.68#ibcon#read 3, iclass 27, count 2 2006.285.17:38:44.68#ibcon#about to read 4, iclass 27, count 2 2006.285.17:38:44.68#ibcon#read 4, iclass 27, count 2 2006.285.17:38:44.68#ibcon#about to read 5, iclass 27, count 2 2006.285.17:38:44.68#ibcon#read 5, iclass 27, count 2 2006.285.17:38:44.68#ibcon#about to read 6, iclass 27, count 2 2006.285.17:38:44.68#ibcon#read 6, iclass 27, count 2 2006.285.17:38:44.68#ibcon#end of sib2, iclass 27, count 2 2006.285.17:38:44.68#ibcon#*mode == 0, iclass 27, count 2 2006.285.17:38:44.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.17:38:44.68#ibcon#[25=AT03-07\r\n] 2006.285.17:38:44.68#ibcon#*before write, iclass 27, count 2 2006.285.17:38:44.68#ibcon#enter sib2, iclass 27, count 2 2006.285.17:38:44.68#ibcon#flushed, iclass 27, count 2 2006.285.17:38:44.68#ibcon#about to write, iclass 27, count 2 2006.285.17:38:44.68#ibcon#wrote, iclass 27, count 2 2006.285.17:38:44.68#ibcon#about to read 3, iclass 27, count 2 2006.285.17:38:44.71#ibcon#read 3, iclass 27, count 2 2006.285.17:38:44.71#ibcon#about to read 4, iclass 27, count 2 2006.285.17:38:44.71#ibcon#read 4, iclass 27, count 2 2006.285.17:38:44.71#ibcon#about to read 5, iclass 27, count 2 2006.285.17:38:44.71#ibcon#read 5, iclass 27, count 2 2006.285.17:38:44.71#ibcon#about to read 6, iclass 27, count 2 2006.285.17:38:44.71#ibcon#read 6, iclass 27, count 2 2006.285.17:38:44.71#ibcon#end of sib2, iclass 27, count 2 2006.285.17:38:44.71#ibcon#*after write, iclass 27, count 2 2006.285.17:38:44.71#ibcon#*before return 0, iclass 27, count 2 2006.285.17:38:44.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:38:44.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:38:44.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.17:38:44.71#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:44.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:38:44.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:38:44.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:38:44.83#ibcon#enter wrdev, iclass 27, count 0 2006.285.17:38:44.83#ibcon#first serial, iclass 27, count 0 2006.285.17:38:44.83#ibcon#enter sib2, iclass 27, count 0 2006.285.17:38:44.83#ibcon#flushed, iclass 27, count 0 2006.285.17:38:44.83#ibcon#about to write, iclass 27, count 0 2006.285.17:38:44.83#ibcon#wrote, iclass 27, count 0 2006.285.17:38:44.83#ibcon#about to read 3, iclass 27, count 0 2006.285.17:38:44.85#ibcon#read 3, iclass 27, count 0 2006.285.17:38:44.85#ibcon#about to read 4, iclass 27, count 0 2006.285.17:38:44.85#ibcon#read 4, iclass 27, count 0 2006.285.17:38:44.85#ibcon#about to read 5, iclass 27, count 0 2006.285.17:38:44.85#ibcon#read 5, iclass 27, count 0 2006.285.17:38:44.85#ibcon#about to read 6, iclass 27, count 0 2006.285.17:38:44.85#ibcon#read 6, iclass 27, count 0 2006.285.17:38:44.85#ibcon#end of sib2, iclass 27, count 0 2006.285.17:38:44.85#ibcon#*mode == 0, iclass 27, count 0 2006.285.17:38:44.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.17:38:44.85#ibcon#[25=USB\r\n] 2006.285.17:38:44.85#ibcon#*before write, iclass 27, count 0 2006.285.17:38:44.85#ibcon#enter sib2, iclass 27, count 0 2006.285.17:38:44.85#ibcon#flushed, iclass 27, count 0 2006.285.17:38:44.85#ibcon#about to write, iclass 27, count 0 2006.285.17:38:44.85#ibcon#wrote, iclass 27, count 0 2006.285.17:38:44.85#ibcon#about to read 3, iclass 27, count 0 2006.285.17:38:44.88#ibcon#read 3, iclass 27, count 0 2006.285.17:38:44.88#ibcon#about to read 4, iclass 27, count 0 2006.285.17:38:44.88#ibcon#read 4, iclass 27, count 0 2006.285.17:38:44.88#ibcon#about to read 5, iclass 27, count 0 2006.285.17:38:44.88#ibcon#read 5, iclass 27, count 0 2006.285.17:38:44.88#ibcon#about to read 6, iclass 27, count 0 2006.285.17:38:44.88#ibcon#read 6, iclass 27, count 0 2006.285.17:38:44.88#ibcon#end of sib2, iclass 27, count 0 2006.285.17:38:44.88#ibcon#*after write, iclass 27, count 0 2006.285.17:38:44.88#ibcon#*before return 0, iclass 27, count 0 2006.285.17:38:44.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:38:44.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:38:44.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.17:38:44.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.17:38:44.88$vck44/valo=4,624.99 2006.285.17:38:44.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.17:38:44.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.17:38:44.88#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:44.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:38:44.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:38:44.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:38:44.88#ibcon#enter wrdev, iclass 29, count 0 2006.285.17:38:44.88#ibcon#first serial, iclass 29, count 0 2006.285.17:38:44.88#ibcon#enter sib2, iclass 29, count 0 2006.285.17:38:44.88#ibcon#flushed, iclass 29, count 0 2006.285.17:38:44.88#ibcon#about to write, iclass 29, count 0 2006.285.17:38:44.88#ibcon#wrote, iclass 29, count 0 2006.285.17:38:44.88#ibcon#about to read 3, iclass 29, count 0 2006.285.17:38:44.90#ibcon#read 3, iclass 29, count 0 2006.285.17:38:45.20#ibcon#about to read 4, iclass 29, count 0 2006.285.17:38:45.20#ibcon#read 4, iclass 29, count 0 2006.285.17:38:45.20#ibcon#about to read 5, iclass 29, count 0 2006.285.17:38:45.20#ibcon#read 5, iclass 29, count 0 2006.285.17:38:45.20#ibcon#about to read 6, iclass 29, count 0 2006.285.17:38:45.20#ibcon#read 6, iclass 29, count 0 2006.285.17:38:45.20#ibcon#end of sib2, iclass 29, count 0 2006.285.17:38:45.20#ibcon#*mode == 0, iclass 29, count 0 2006.285.17:38:45.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.17:38:45.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.17:38:45.20#ibcon#*before write, iclass 29, count 0 2006.285.17:38:45.20#ibcon#enter sib2, iclass 29, count 0 2006.285.17:38:45.20#ibcon#flushed, iclass 29, count 0 2006.285.17:38:45.20#ibcon#about to write, iclass 29, count 0 2006.285.17:38:45.20#ibcon#wrote, iclass 29, count 0 2006.285.17:38:45.20#ibcon#about to read 3, iclass 29, count 0 2006.285.17:38:45.25#ibcon#read 3, iclass 29, count 0 2006.285.17:38:45.25#ibcon#about to read 4, iclass 29, count 0 2006.285.17:38:45.25#ibcon#read 4, iclass 29, count 0 2006.285.17:38:45.25#ibcon#about to read 5, iclass 29, count 0 2006.285.17:38:45.25#ibcon#read 5, iclass 29, count 0 2006.285.17:38:45.25#ibcon#about to read 6, iclass 29, count 0 2006.285.17:38:45.25#ibcon#read 6, iclass 29, count 0 2006.285.17:38:45.25#ibcon#end of sib2, iclass 29, count 0 2006.285.17:38:45.25#ibcon#*after write, iclass 29, count 0 2006.285.17:38:45.25#ibcon#*before return 0, iclass 29, count 0 2006.285.17:38:45.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:38:45.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:38:45.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.17:38:45.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.17:38:45.25$vck44/va=4,6 2006.285.17:38:45.25#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.17:38:45.25#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.17:38:45.25#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:45.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:38:45.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:38:45.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:38:45.25#ibcon#enter wrdev, iclass 31, count 2 2006.285.17:38:45.25#ibcon#first serial, iclass 31, count 2 2006.285.17:38:45.25#ibcon#enter sib2, iclass 31, count 2 2006.285.17:38:45.25#ibcon#flushed, iclass 31, count 2 2006.285.17:38:45.25#ibcon#about to write, iclass 31, count 2 2006.285.17:38:45.25#ibcon#wrote, iclass 31, count 2 2006.285.17:38:45.25#ibcon#about to read 3, iclass 31, count 2 2006.285.17:38:45.27#ibcon#read 3, iclass 31, count 2 2006.285.17:38:45.27#ibcon#about to read 4, iclass 31, count 2 2006.285.17:38:45.27#ibcon#read 4, iclass 31, count 2 2006.285.17:38:45.27#ibcon#about to read 5, iclass 31, count 2 2006.285.17:38:45.27#ibcon#read 5, iclass 31, count 2 2006.285.17:38:45.27#ibcon#about to read 6, iclass 31, count 2 2006.285.17:38:45.27#ibcon#read 6, iclass 31, count 2 2006.285.17:38:45.27#ibcon#end of sib2, iclass 31, count 2 2006.285.17:38:45.27#ibcon#*mode == 0, iclass 31, count 2 2006.285.17:38:45.27#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.17:38:45.27#ibcon#[25=AT04-06\r\n] 2006.285.17:38:45.27#ibcon#*before write, iclass 31, count 2 2006.285.17:38:45.27#ibcon#enter sib2, iclass 31, count 2 2006.285.17:38:45.27#ibcon#flushed, iclass 31, count 2 2006.285.17:38:45.27#ibcon#about to write, iclass 31, count 2 2006.285.17:38:45.27#ibcon#wrote, iclass 31, count 2 2006.285.17:38:45.27#ibcon#about to read 3, iclass 31, count 2 2006.285.17:38:45.30#ibcon#read 3, iclass 31, count 2 2006.285.17:38:45.30#ibcon#about to read 4, iclass 31, count 2 2006.285.17:38:45.30#ibcon#read 4, iclass 31, count 2 2006.285.17:38:45.30#ibcon#about to read 5, iclass 31, count 2 2006.285.17:38:45.30#ibcon#read 5, iclass 31, count 2 2006.285.17:38:45.30#ibcon#about to read 6, iclass 31, count 2 2006.285.17:38:45.30#ibcon#read 6, iclass 31, count 2 2006.285.17:38:45.30#ibcon#end of sib2, iclass 31, count 2 2006.285.17:38:45.30#ibcon#*after write, iclass 31, count 2 2006.285.17:38:45.30#ibcon#*before return 0, iclass 31, count 2 2006.285.17:38:45.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:38:45.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:38:45.30#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.17:38:45.30#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:45.30#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:38:45.42#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:38:45.42#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:38:45.42#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:38:45.42#ibcon#first serial, iclass 31, count 0 2006.285.17:38:45.42#ibcon#enter sib2, iclass 31, count 0 2006.285.17:38:45.42#ibcon#flushed, iclass 31, count 0 2006.285.17:38:45.42#ibcon#about to write, iclass 31, count 0 2006.285.17:38:45.42#ibcon#wrote, iclass 31, count 0 2006.285.17:38:45.42#ibcon#about to read 3, iclass 31, count 0 2006.285.17:38:45.44#ibcon#read 3, iclass 31, count 0 2006.285.17:38:45.44#ibcon#about to read 4, iclass 31, count 0 2006.285.17:38:45.44#ibcon#read 4, iclass 31, count 0 2006.285.17:38:45.44#ibcon#about to read 5, iclass 31, count 0 2006.285.17:38:45.44#ibcon#read 5, iclass 31, count 0 2006.285.17:38:45.44#ibcon#about to read 6, iclass 31, count 0 2006.285.17:38:45.44#ibcon#read 6, iclass 31, count 0 2006.285.17:38:45.44#ibcon#end of sib2, iclass 31, count 0 2006.285.17:38:45.44#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:38:45.44#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:38:45.44#ibcon#[25=USB\r\n] 2006.285.17:38:45.44#ibcon#*before write, iclass 31, count 0 2006.285.17:38:45.44#ibcon#enter sib2, iclass 31, count 0 2006.285.17:38:45.44#ibcon#flushed, iclass 31, count 0 2006.285.17:38:45.44#ibcon#about to write, iclass 31, count 0 2006.285.17:38:45.44#ibcon#wrote, iclass 31, count 0 2006.285.17:38:45.44#ibcon#about to read 3, iclass 31, count 0 2006.285.17:38:45.47#ibcon#read 3, iclass 31, count 0 2006.285.17:38:45.47#ibcon#about to read 4, iclass 31, count 0 2006.285.17:38:45.47#ibcon#read 4, iclass 31, count 0 2006.285.17:38:45.47#ibcon#about to read 5, iclass 31, count 0 2006.285.17:38:45.47#ibcon#read 5, iclass 31, count 0 2006.285.17:38:45.47#ibcon#about to read 6, iclass 31, count 0 2006.285.17:38:45.47#ibcon#read 6, iclass 31, count 0 2006.285.17:38:45.47#ibcon#end of sib2, iclass 31, count 0 2006.285.17:38:45.47#ibcon#*after write, iclass 31, count 0 2006.285.17:38:45.47#ibcon#*before return 0, iclass 31, count 0 2006.285.17:38:45.47#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:38:45.47#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:38:45.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:38:45.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:38:45.47$vck44/valo=5,734.99 2006.285.17:38:45.47#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.17:38:45.47#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.17:38:45.47#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:45.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:38:45.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:38:45.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:38:45.47#ibcon#enter wrdev, iclass 33, count 0 2006.285.17:38:45.47#ibcon#first serial, iclass 33, count 0 2006.285.17:38:45.47#ibcon#enter sib2, iclass 33, count 0 2006.285.17:38:45.47#ibcon#flushed, iclass 33, count 0 2006.285.17:38:45.47#ibcon#about to write, iclass 33, count 0 2006.285.17:38:45.47#ibcon#wrote, iclass 33, count 0 2006.285.17:38:45.47#ibcon#about to read 3, iclass 33, count 0 2006.285.17:38:45.49#ibcon#read 3, iclass 33, count 0 2006.285.17:38:45.49#ibcon#about to read 4, iclass 33, count 0 2006.285.17:38:45.49#ibcon#read 4, iclass 33, count 0 2006.285.17:38:45.49#ibcon#about to read 5, iclass 33, count 0 2006.285.17:38:45.49#ibcon#read 5, iclass 33, count 0 2006.285.17:38:45.49#ibcon#about to read 6, iclass 33, count 0 2006.285.17:38:45.49#ibcon#read 6, iclass 33, count 0 2006.285.17:38:45.49#ibcon#end of sib2, iclass 33, count 0 2006.285.17:38:45.49#ibcon#*mode == 0, iclass 33, count 0 2006.285.17:38:45.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.17:38:45.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.17:38:45.49#ibcon#*before write, iclass 33, count 0 2006.285.17:38:45.49#ibcon#enter sib2, iclass 33, count 0 2006.285.17:38:45.49#ibcon#flushed, iclass 33, count 0 2006.285.17:38:45.49#ibcon#about to write, iclass 33, count 0 2006.285.17:38:45.49#ibcon#wrote, iclass 33, count 0 2006.285.17:38:45.49#ibcon#about to read 3, iclass 33, count 0 2006.285.17:38:45.53#ibcon#read 3, iclass 33, count 0 2006.285.17:38:45.53#ibcon#about to read 4, iclass 33, count 0 2006.285.17:38:45.53#ibcon#read 4, iclass 33, count 0 2006.285.17:38:45.53#ibcon#about to read 5, iclass 33, count 0 2006.285.17:38:45.53#ibcon#read 5, iclass 33, count 0 2006.285.17:38:45.53#ibcon#about to read 6, iclass 33, count 0 2006.285.17:38:45.53#ibcon#read 6, iclass 33, count 0 2006.285.17:38:45.53#ibcon#end of sib2, iclass 33, count 0 2006.285.17:38:45.53#ibcon#*after write, iclass 33, count 0 2006.285.17:38:45.53#ibcon#*before return 0, iclass 33, count 0 2006.285.17:38:45.53#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:38:45.53#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:38:45.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.17:38:45.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.17:38:45.53$vck44/va=5,3 2006.285.17:38:45.53#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.17:38:45.53#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.17:38:45.53#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:45.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:38:45.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:38:45.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:38:45.59#ibcon#enter wrdev, iclass 35, count 2 2006.285.17:38:45.59#ibcon#first serial, iclass 35, count 2 2006.285.17:38:45.59#ibcon#enter sib2, iclass 35, count 2 2006.285.17:38:45.59#ibcon#flushed, iclass 35, count 2 2006.285.17:38:45.59#ibcon#about to write, iclass 35, count 2 2006.285.17:38:45.59#ibcon#wrote, iclass 35, count 2 2006.285.17:38:45.59#ibcon#about to read 3, iclass 35, count 2 2006.285.17:38:45.61#ibcon#read 3, iclass 35, count 2 2006.285.17:38:45.61#ibcon#about to read 4, iclass 35, count 2 2006.285.17:38:45.61#ibcon#read 4, iclass 35, count 2 2006.285.17:38:45.61#ibcon#about to read 5, iclass 35, count 2 2006.285.17:38:45.61#ibcon#read 5, iclass 35, count 2 2006.285.17:38:45.61#ibcon#about to read 6, iclass 35, count 2 2006.285.17:38:45.61#ibcon#read 6, iclass 35, count 2 2006.285.17:38:45.61#ibcon#end of sib2, iclass 35, count 2 2006.285.17:38:45.61#ibcon#*mode == 0, iclass 35, count 2 2006.285.17:38:45.61#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.17:38:45.61#ibcon#[25=AT05-03\r\n] 2006.285.17:38:45.61#ibcon#*before write, iclass 35, count 2 2006.285.17:38:45.61#ibcon#enter sib2, iclass 35, count 2 2006.285.17:38:45.61#ibcon#flushed, iclass 35, count 2 2006.285.17:38:45.61#ibcon#about to write, iclass 35, count 2 2006.285.17:38:45.61#ibcon#wrote, iclass 35, count 2 2006.285.17:38:45.61#ibcon#about to read 3, iclass 35, count 2 2006.285.17:38:45.64#ibcon#read 3, iclass 35, count 2 2006.285.17:38:45.64#ibcon#about to read 4, iclass 35, count 2 2006.285.17:38:45.64#ibcon#read 4, iclass 35, count 2 2006.285.17:38:45.64#ibcon#about to read 5, iclass 35, count 2 2006.285.17:38:45.64#ibcon#read 5, iclass 35, count 2 2006.285.17:38:45.64#ibcon#about to read 6, iclass 35, count 2 2006.285.17:38:45.64#ibcon#read 6, iclass 35, count 2 2006.285.17:38:45.64#ibcon#end of sib2, iclass 35, count 2 2006.285.17:38:45.64#ibcon#*after write, iclass 35, count 2 2006.285.17:38:45.64#ibcon#*before return 0, iclass 35, count 2 2006.285.17:38:45.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:38:45.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:38:45.64#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.17:38:45.64#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:45.64#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:38:45.76#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:38:45.76#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:38:45.76#ibcon#enter wrdev, iclass 35, count 0 2006.285.17:38:45.76#ibcon#first serial, iclass 35, count 0 2006.285.17:38:45.76#ibcon#enter sib2, iclass 35, count 0 2006.285.17:38:45.76#ibcon#flushed, iclass 35, count 0 2006.285.17:38:45.76#ibcon#about to write, iclass 35, count 0 2006.285.17:38:45.76#ibcon#wrote, iclass 35, count 0 2006.285.17:38:45.76#ibcon#about to read 3, iclass 35, count 0 2006.285.17:38:45.78#ibcon#read 3, iclass 35, count 0 2006.285.17:38:45.78#ibcon#about to read 4, iclass 35, count 0 2006.285.17:38:45.78#ibcon#read 4, iclass 35, count 0 2006.285.17:38:45.78#ibcon#about to read 5, iclass 35, count 0 2006.285.17:38:45.78#ibcon#read 5, iclass 35, count 0 2006.285.17:38:45.78#ibcon#about to read 6, iclass 35, count 0 2006.285.17:38:45.78#ibcon#read 6, iclass 35, count 0 2006.285.17:38:45.78#ibcon#end of sib2, iclass 35, count 0 2006.285.17:38:45.78#ibcon#*mode == 0, iclass 35, count 0 2006.285.17:38:45.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.17:38:45.78#ibcon#[25=USB\r\n] 2006.285.17:38:45.78#ibcon#*before write, iclass 35, count 0 2006.285.17:38:45.78#ibcon#enter sib2, iclass 35, count 0 2006.285.17:38:45.78#ibcon#flushed, iclass 35, count 0 2006.285.17:38:45.78#ibcon#about to write, iclass 35, count 0 2006.285.17:38:45.78#ibcon#wrote, iclass 35, count 0 2006.285.17:38:45.78#ibcon#about to read 3, iclass 35, count 0 2006.285.17:38:45.81#ibcon#read 3, iclass 35, count 0 2006.285.17:38:45.81#ibcon#about to read 4, iclass 35, count 0 2006.285.17:38:45.81#ibcon#read 4, iclass 35, count 0 2006.285.17:38:45.81#ibcon#about to read 5, iclass 35, count 0 2006.285.17:38:45.81#ibcon#read 5, iclass 35, count 0 2006.285.17:38:45.81#ibcon#about to read 6, iclass 35, count 0 2006.285.17:38:45.81#ibcon#read 6, iclass 35, count 0 2006.285.17:38:45.81#ibcon#end of sib2, iclass 35, count 0 2006.285.17:38:45.81#ibcon#*after write, iclass 35, count 0 2006.285.17:38:45.81#ibcon#*before return 0, iclass 35, count 0 2006.285.17:38:45.81#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:38:45.81#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:38:45.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.17:38:45.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.17:38:45.81$vck44/valo=6,814.99 2006.285.17:38:45.81#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.17:38:45.81#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.17:38:45.81#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:45.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:38:45.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:38:45.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:38:45.81#ibcon#enter wrdev, iclass 37, count 0 2006.285.17:38:45.81#ibcon#first serial, iclass 37, count 0 2006.285.17:38:45.81#ibcon#enter sib2, iclass 37, count 0 2006.285.17:38:45.81#ibcon#flushed, iclass 37, count 0 2006.285.17:38:45.81#ibcon#about to write, iclass 37, count 0 2006.285.17:38:45.81#ibcon#wrote, iclass 37, count 0 2006.285.17:38:45.81#ibcon#about to read 3, iclass 37, count 0 2006.285.17:38:45.83#ibcon#read 3, iclass 37, count 0 2006.285.17:38:45.83#ibcon#about to read 4, iclass 37, count 0 2006.285.17:38:45.83#ibcon#read 4, iclass 37, count 0 2006.285.17:38:45.83#ibcon#about to read 5, iclass 37, count 0 2006.285.17:38:45.83#ibcon#read 5, iclass 37, count 0 2006.285.17:38:45.83#ibcon#about to read 6, iclass 37, count 0 2006.285.17:38:45.83#ibcon#read 6, iclass 37, count 0 2006.285.17:38:45.83#ibcon#end of sib2, iclass 37, count 0 2006.285.17:38:45.83#ibcon#*mode == 0, iclass 37, count 0 2006.285.17:38:45.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.17:38:45.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.17:38:45.83#ibcon#*before write, iclass 37, count 0 2006.285.17:38:45.83#ibcon#enter sib2, iclass 37, count 0 2006.285.17:38:45.83#ibcon#flushed, iclass 37, count 0 2006.285.17:38:45.83#ibcon#about to write, iclass 37, count 0 2006.285.17:38:45.83#ibcon#wrote, iclass 37, count 0 2006.285.17:38:45.83#ibcon#about to read 3, iclass 37, count 0 2006.285.17:38:45.87#ibcon#read 3, iclass 37, count 0 2006.285.17:38:45.87#ibcon#about to read 4, iclass 37, count 0 2006.285.17:38:45.87#ibcon#read 4, iclass 37, count 0 2006.285.17:38:45.87#ibcon#about to read 5, iclass 37, count 0 2006.285.17:38:45.87#ibcon#read 5, iclass 37, count 0 2006.285.17:38:45.87#ibcon#about to read 6, iclass 37, count 0 2006.285.17:38:45.87#ibcon#read 6, iclass 37, count 0 2006.285.17:38:45.87#ibcon#end of sib2, iclass 37, count 0 2006.285.17:38:45.87#ibcon#*after write, iclass 37, count 0 2006.285.17:38:45.87#ibcon#*before return 0, iclass 37, count 0 2006.285.17:38:45.87#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:38:45.87#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:38:45.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.17:38:45.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.17:38:45.87$vck44/va=6,4 2006.285.17:38:45.87#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.17:38:45.87#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.17:38:45.87#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:45.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:38:45.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:38:45.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:38:45.93#ibcon#enter wrdev, iclass 39, count 2 2006.285.17:38:45.93#ibcon#first serial, iclass 39, count 2 2006.285.17:38:45.93#ibcon#enter sib2, iclass 39, count 2 2006.285.17:38:45.93#ibcon#flushed, iclass 39, count 2 2006.285.17:38:45.93#ibcon#about to write, iclass 39, count 2 2006.285.17:38:45.93#ibcon#wrote, iclass 39, count 2 2006.285.17:38:45.93#ibcon#about to read 3, iclass 39, count 2 2006.285.17:38:45.95#ibcon#read 3, iclass 39, count 2 2006.285.17:38:45.95#ibcon#about to read 4, iclass 39, count 2 2006.285.17:38:45.95#ibcon#read 4, iclass 39, count 2 2006.285.17:38:45.95#ibcon#about to read 5, iclass 39, count 2 2006.285.17:38:45.95#ibcon#read 5, iclass 39, count 2 2006.285.17:38:45.95#ibcon#about to read 6, iclass 39, count 2 2006.285.17:38:45.95#ibcon#read 6, iclass 39, count 2 2006.285.17:38:45.95#ibcon#end of sib2, iclass 39, count 2 2006.285.17:38:45.95#ibcon#*mode == 0, iclass 39, count 2 2006.285.17:38:45.95#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.17:38:45.95#ibcon#[25=AT06-04\r\n] 2006.285.17:38:45.95#ibcon#*before write, iclass 39, count 2 2006.285.17:38:45.95#ibcon#enter sib2, iclass 39, count 2 2006.285.17:38:45.95#ibcon#flushed, iclass 39, count 2 2006.285.17:38:45.95#ibcon#about to write, iclass 39, count 2 2006.285.17:38:45.95#ibcon#wrote, iclass 39, count 2 2006.285.17:38:45.95#ibcon#about to read 3, iclass 39, count 2 2006.285.17:38:45.98#ibcon#read 3, iclass 39, count 2 2006.285.17:38:45.98#ibcon#about to read 4, iclass 39, count 2 2006.285.17:38:45.98#ibcon#read 4, iclass 39, count 2 2006.285.17:38:45.98#ibcon#about to read 5, iclass 39, count 2 2006.285.17:38:45.98#ibcon#read 5, iclass 39, count 2 2006.285.17:38:45.98#ibcon#about to read 6, iclass 39, count 2 2006.285.17:38:45.98#ibcon#read 6, iclass 39, count 2 2006.285.17:38:45.98#ibcon#end of sib2, iclass 39, count 2 2006.285.17:38:45.98#ibcon#*after write, iclass 39, count 2 2006.285.17:38:45.98#ibcon#*before return 0, iclass 39, count 2 2006.285.17:38:45.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:38:45.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:38:45.98#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.17:38:45.98#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:45.98#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:38:46.10#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:38:46.10#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:38:46.10#ibcon#enter wrdev, iclass 39, count 0 2006.285.17:38:46.10#ibcon#first serial, iclass 39, count 0 2006.285.17:38:46.10#ibcon#enter sib2, iclass 39, count 0 2006.285.17:38:46.10#ibcon#flushed, iclass 39, count 0 2006.285.17:38:46.10#ibcon#about to write, iclass 39, count 0 2006.285.17:38:46.10#ibcon#wrote, iclass 39, count 0 2006.285.17:38:46.10#ibcon#about to read 3, iclass 39, count 0 2006.285.17:38:46.12#ibcon#read 3, iclass 39, count 0 2006.285.17:38:46.12#ibcon#about to read 4, iclass 39, count 0 2006.285.17:38:46.12#ibcon#read 4, iclass 39, count 0 2006.285.17:38:46.12#ibcon#about to read 5, iclass 39, count 0 2006.285.17:38:46.12#ibcon#read 5, iclass 39, count 0 2006.285.17:38:46.12#ibcon#about to read 6, iclass 39, count 0 2006.285.17:38:46.12#ibcon#read 6, iclass 39, count 0 2006.285.17:38:46.12#ibcon#end of sib2, iclass 39, count 0 2006.285.17:38:46.12#ibcon#*mode == 0, iclass 39, count 0 2006.285.17:38:46.12#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.17:38:46.12#ibcon#[25=USB\r\n] 2006.285.17:38:46.12#ibcon#*before write, iclass 39, count 0 2006.285.17:38:46.12#ibcon#enter sib2, iclass 39, count 0 2006.285.17:38:46.12#ibcon#flushed, iclass 39, count 0 2006.285.17:38:46.12#ibcon#about to write, iclass 39, count 0 2006.285.17:38:46.12#ibcon#wrote, iclass 39, count 0 2006.285.17:38:46.12#ibcon#about to read 3, iclass 39, count 0 2006.285.17:38:46.15#ibcon#read 3, iclass 39, count 0 2006.285.17:38:46.15#ibcon#about to read 4, iclass 39, count 0 2006.285.17:38:46.15#ibcon#read 4, iclass 39, count 0 2006.285.17:38:46.15#ibcon#about to read 5, iclass 39, count 0 2006.285.17:38:46.15#ibcon#read 5, iclass 39, count 0 2006.285.17:38:46.15#ibcon#about to read 6, iclass 39, count 0 2006.285.17:38:46.15#ibcon#read 6, iclass 39, count 0 2006.285.17:38:46.15#ibcon#end of sib2, iclass 39, count 0 2006.285.17:38:46.15#ibcon#*after write, iclass 39, count 0 2006.285.17:38:46.15#ibcon#*before return 0, iclass 39, count 0 2006.285.17:38:46.15#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:38:46.15#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:38:46.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.17:38:46.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.17:38:46.15$vck44/valo=7,864.99 2006.285.17:38:46.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.17:38:46.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.17:38:46.22#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:46.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:38:46.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:38:46.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:38:46.22#ibcon#enter wrdev, iclass 3, count 0 2006.285.17:38:46.22#ibcon#first serial, iclass 3, count 0 2006.285.17:38:46.22#ibcon#enter sib2, iclass 3, count 0 2006.285.17:38:46.22#ibcon#flushed, iclass 3, count 0 2006.285.17:38:46.22#ibcon#about to write, iclass 3, count 0 2006.285.17:38:46.22#ibcon#wrote, iclass 3, count 0 2006.285.17:38:46.22#ibcon#about to read 3, iclass 3, count 0 2006.285.17:38:46.24#ibcon#read 3, iclass 3, count 0 2006.285.17:38:46.24#ibcon#about to read 4, iclass 3, count 0 2006.285.17:38:46.24#ibcon#read 4, iclass 3, count 0 2006.285.17:38:46.24#ibcon#about to read 5, iclass 3, count 0 2006.285.17:38:46.24#ibcon#read 5, iclass 3, count 0 2006.285.17:38:46.24#ibcon#about to read 6, iclass 3, count 0 2006.285.17:38:46.24#ibcon#read 6, iclass 3, count 0 2006.285.17:38:46.24#ibcon#end of sib2, iclass 3, count 0 2006.285.17:38:46.24#ibcon#*mode == 0, iclass 3, count 0 2006.285.17:38:46.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.17:38:46.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.17:38:46.24#ibcon#*before write, iclass 3, count 0 2006.285.17:38:46.24#ibcon#enter sib2, iclass 3, count 0 2006.285.17:38:46.24#ibcon#flushed, iclass 3, count 0 2006.285.17:38:46.24#ibcon#about to write, iclass 3, count 0 2006.285.17:38:46.24#ibcon#wrote, iclass 3, count 0 2006.285.17:38:46.24#ibcon#about to read 3, iclass 3, count 0 2006.285.17:38:46.28#ibcon#read 3, iclass 3, count 0 2006.285.17:38:46.28#ibcon#about to read 4, iclass 3, count 0 2006.285.17:38:46.28#ibcon#read 4, iclass 3, count 0 2006.285.17:38:46.28#ibcon#about to read 5, iclass 3, count 0 2006.285.17:38:46.28#ibcon#read 5, iclass 3, count 0 2006.285.17:38:46.28#ibcon#about to read 6, iclass 3, count 0 2006.285.17:38:46.28#ibcon#read 6, iclass 3, count 0 2006.285.17:38:46.28#ibcon#end of sib2, iclass 3, count 0 2006.285.17:38:46.28#ibcon#*after write, iclass 3, count 0 2006.285.17:38:46.28#ibcon#*before return 0, iclass 3, count 0 2006.285.17:38:46.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:38:46.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:38:46.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.17:38:46.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.17:38:46.28$vck44/va=7,4 2006.285.17:38:46.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.17:38:46.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.17:38:46.28#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:46.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:38:46.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:38:46.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:38:46.28#ibcon#enter wrdev, iclass 5, count 2 2006.285.17:38:46.28#ibcon#first serial, iclass 5, count 2 2006.285.17:38:46.28#ibcon#enter sib2, iclass 5, count 2 2006.285.17:38:46.28#ibcon#flushed, iclass 5, count 2 2006.285.17:38:46.28#ibcon#about to write, iclass 5, count 2 2006.285.17:38:46.28#ibcon#wrote, iclass 5, count 2 2006.285.17:38:46.28#ibcon#about to read 3, iclass 5, count 2 2006.285.17:38:46.30#ibcon#read 3, iclass 5, count 2 2006.285.17:38:46.30#ibcon#about to read 4, iclass 5, count 2 2006.285.17:38:46.30#ibcon#read 4, iclass 5, count 2 2006.285.17:38:46.30#ibcon#about to read 5, iclass 5, count 2 2006.285.17:38:46.30#ibcon#read 5, iclass 5, count 2 2006.285.17:38:46.30#ibcon#about to read 6, iclass 5, count 2 2006.285.17:38:46.30#ibcon#read 6, iclass 5, count 2 2006.285.17:38:46.30#ibcon#end of sib2, iclass 5, count 2 2006.285.17:38:46.30#ibcon#*mode == 0, iclass 5, count 2 2006.285.17:38:46.30#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.17:38:46.30#ibcon#[25=AT07-04\r\n] 2006.285.17:38:46.30#ibcon#*before write, iclass 5, count 2 2006.285.17:38:46.30#ibcon#enter sib2, iclass 5, count 2 2006.285.17:38:46.30#ibcon#flushed, iclass 5, count 2 2006.285.17:38:46.30#ibcon#about to write, iclass 5, count 2 2006.285.17:38:46.30#ibcon#wrote, iclass 5, count 2 2006.285.17:38:46.30#ibcon#about to read 3, iclass 5, count 2 2006.285.17:38:46.33#ibcon#read 3, iclass 5, count 2 2006.285.17:38:46.33#ibcon#about to read 4, iclass 5, count 2 2006.285.17:38:46.33#ibcon#read 4, iclass 5, count 2 2006.285.17:38:46.33#ibcon#about to read 5, iclass 5, count 2 2006.285.17:38:46.33#ibcon#read 5, iclass 5, count 2 2006.285.17:38:46.33#ibcon#about to read 6, iclass 5, count 2 2006.285.17:38:46.33#ibcon#read 6, iclass 5, count 2 2006.285.17:38:46.33#ibcon#end of sib2, iclass 5, count 2 2006.285.17:38:46.33#ibcon#*after write, iclass 5, count 2 2006.285.17:38:46.33#ibcon#*before return 0, iclass 5, count 2 2006.285.17:38:46.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:38:46.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:38:46.33#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.17:38:46.33#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:46.33#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:38:46.45#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:38:46.45#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:38:46.45#ibcon#enter wrdev, iclass 5, count 0 2006.285.17:38:46.45#ibcon#first serial, iclass 5, count 0 2006.285.17:38:46.45#ibcon#enter sib2, iclass 5, count 0 2006.285.17:38:46.45#ibcon#flushed, iclass 5, count 0 2006.285.17:38:46.45#ibcon#about to write, iclass 5, count 0 2006.285.17:38:46.45#ibcon#wrote, iclass 5, count 0 2006.285.17:38:46.45#ibcon#about to read 3, iclass 5, count 0 2006.285.17:38:46.47#ibcon#read 3, iclass 5, count 0 2006.285.17:38:46.47#ibcon#about to read 4, iclass 5, count 0 2006.285.17:38:46.47#ibcon#read 4, iclass 5, count 0 2006.285.17:38:46.47#ibcon#about to read 5, iclass 5, count 0 2006.285.17:38:46.47#ibcon#read 5, iclass 5, count 0 2006.285.17:38:46.47#ibcon#about to read 6, iclass 5, count 0 2006.285.17:38:46.47#ibcon#read 6, iclass 5, count 0 2006.285.17:38:46.47#ibcon#end of sib2, iclass 5, count 0 2006.285.17:38:46.47#ibcon#*mode == 0, iclass 5, count 0 2006.285.17:38:46.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.17:38:46.47#ibcon#[25=USB\r\n] 2006.285.17:38:46.47#ibcon#*before write, iclass 5, count 0 2006.285.17:38:46.47#ibcon#enter sib2, iclass 5, count 0 2006.285.17:38:46.47#ibcon#flushed, iclass 5, count 0 2006.285.17:38:46.47#ibcon#about to write, iclass 5, count 0 2006.285.17:38:46.47#ibcon#wrote, iclass 5, count 0 2006.285.17:38:46.47#ibcon#about to read 3, iclass 5, count 0 2006.285.17:38:46.50#ibcon#read 3, iclass 5, count 0 2006.285.17:38:46.50#ibcon#about to read 4, iclass 5, count 0 2006.285.17:38:46.50#ibcon#read 4, iclass 5, count 0 2006.285.17:38:46.50#ibcon#about to read 5, iclass 5, count 0 2006.285.17:38:46.50#ibcon#read 5, iclass 5, count 0 2006.285.17:38:46.50#ibcon#about to read 6, iclass 5, count 0 2006.285.17:38:46.50#ibcon#read 6, iclass 5, count 0 2006.285.17:38:46.50#ibcon#end of sib2, iclass 5, count 0 2006.285.17:38:46.50#ibcon#*after write, iclass 5, count 0 2006.285.17:38:46.50#ibcon#*before return 0, iclass 5, count 0 2006.285.17:38:46.50#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:38:46.50#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:38:46.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.17:38:46.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.17:38:46.50$vck44/valo=8,884.99 2006.285.17:38:46.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.17:38:46.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.17:38:46.50#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:46.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:38:46.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:38:46.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:38:46.50#ibcon#enter wrdev, iclass 7, count 0 2006.285.17:38:46.50#ibcon#first serial, iclass 7, count 0 2006.285.17:38:46.50#ibcon#enter sib2, iclass 7, count 0 2006.285.17:38:46.50#ibcon#flushed, iclass 7, count 0 2006.285.17:38:46.50#ibcon#about to write, iclass 7, count 0 2006.285.17:38:46.50#ibcon#wrote, iclass 7, count 0 2006.285.17:38:46.50#ibcon#about to read 3, iclass 7, count 0 2006.285.17:38:46.52#ibcon#read 3, iclass 7, count 0 2006.285.17:38:46.52#ibcon#about to read 4, iclass 7, count 0 2006.285.17:38:46.52#ibcon#read 4, iclass 7, count 0 2006.285.17:38:46.52#ibcon#about to read 5, iclass 7, count 0 2006.285.17:38:46.52#ibcon#read 5, iclass 7, count 0 2006.285.17:38:46.52#ibcon#about to read 6, iclass 7, count 0 2006.285.17:38:46.52#ibcon#read 6, iclass 7, count 0 2006.285.17:38:46.52#ibcon#end of sib2, iclass 7, count 0 2006.285.17:38:46.52#ibcon#*mode == 0, iclass 7, count 0 2006.285.17:38:46.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.17:38:46.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.17:38:46.52#ibcon#*before write, iclass 7, count 0 2006.285.17:38:46.52#ibcon#enter sib2, iclass 7, count 0 2006.285.17:38:46.52#ibcon#flushed, iclass 7, count 0 2006.285.17:38:46.52#ibcon#about to write, iclass 7, count 0 2006.285.17:38:46.52#ibcon#wrote, iclass 7, count 0 2006.285.17:38:46.52#ibcon#about to read 3, iclass 7, count 0 2006.285.17:38:46.56#ibcon#read 3, iclass 7, count 0 2006.285.17:38:46.56#ibcon#about to read 4, iclass 7, count 0 2006.285.17:38:46.56#ibcon#read 4, iclass 7, count 0 2006.285.17:38:46.56#ibcon#about to read 5, iclass 7, count 0 2006.285.17:38:46.56#ibcon#read 5, iclass 7, count 0 2006.285.17:38:46.56#ibcon#about to read 6, iclass 7, count 0 2006.285.17:38:46.56#ibcon#read 6, iclass 7, count 0 2006.285.17:38:46.56#ibcon#end of sib2, iclass 7, count 0 2006.285.17:38:46.56#ibcon#*after write, iclass 7, count 0 2006.285.17:38:46.56#ibcon#*before return 0, iclass 7, count 0 2006.285.17:38:46.56#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:38:46.56#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:38:46.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.17:38:46.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.17:38:46.56$vck44/va=8,3 2006.285.17:38:46.56#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.17:38:46.56#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.17:38:46.56#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:46.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:38:46.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:38:46.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:38:46.62#ibcon#enter wrdev, iclass 11, count 2 2006.285.17:38:46.62#ibcon#first serial, iclass 11, count 2 2006.285.17:38:46.62#ibcon#enter sib2, iclass 11, count 2 2006.285.17:38:46.62#ibcon#flushed, iclass 11, count 2 2006.285.17:38:46.62#ibcon#about to write, iclass 11, count 2 2006.285.17:38:46.62#ibcon#wrote, iclass 11, count 2 2006.285.17:38:46.62#ibcon#about to read 3, iclass 11, count 2 2006.285.17:38:46.64#ibcon#read 3, iclass 11, count 2 2006.285.17:38:46.64#ibcon#about to read 4, iclass 11, count 2 2006.285.17:38:46.64#ibcon#read 4, iclass 11, count 2 2006.285.17:38:46.64#ibcon#about to read 5, iclass 11, count 2 2006.285.17:38:46.64#ibcon#read 5, iclass 11, count 2 2006.285.17:38:46.64#ibcon#about to read 6, iclass 11, count 2 2006.285.17:38:46.64#ibcon#read 6, iclass 11, count 2 2006.285.17:38:46.64#ibcon#end of sib2, iclass 11, count 2 2006.285.17:38:46.64#ibcon#*mode == 0, iclass 11, count 2 2006.285.17:38:46.64#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.17:38:46.64#ibcon#[25=AT08-03\r\n] 2006.285.17:38:46.64#ibcon#*before write, iclass 11, count 2 2006.285.17:38:46.64#ibcon#enter sib2, iclass 11, count 2 2006.285.17:38:46.64#ibcon#flushed, iclass 11, count 2 2006.285.17:38:46.64#ibcon#about to write, iclass 11, count 2 2006.285.17:38:46.64#ibcon#wrote, iclass 11, count 2 2006.285.17:38:46.64#ibcon#about to read 3, iclass 11, count 2 2006.285.17:38:46.67#ibcon#read 3, iclass 11, count 2 2006.285.17:38:46.67#ibcon#about to read 4, iclass 11, count 2 2006.285.17:38:46.67#ibcon#read 4, iclass 11, count 2 2006.285.17:38:46.67#ibcon#about to read 5, iclass 11, count 2 2006.285.17:38:46.67#ibcon#read 5, iclass 11, count 2 2006.285.17:38:46.67#ibcon#about to read 6, iclass 11, count 2 2006.285.17:38:46.67#ibcon#read 6, iclass 11, count 2 2006.285.17:38:46.67#ibcon#end of sib2, iclass 11, count 2 2006.285.17:38:46.67#ibcon#*after write, iclass 11, count 2 2006.285.17:38:46.67#ibcon#*before return 0, iclass 11, count 2 2006.285.17:38:46.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:38:46.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:38:46.67#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.17:38:46.67#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:46.67#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:38:46.79#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:38:46.79#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:38:46.79#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:38:46.79#ibcon#first serial, iclass 11, count 0 2006.285.17:38:46.79#ibcon#enter sib2, iclass 11, count 0 2006.285.17:38:46.79#ibcon#flushed, iclass 11, count 0 2006.285.17:38:46.79#ibcon#about to write, iclass 11, count 0 2006.285.17:38:46.79#ibcon#wrote, iclass 11, count 0 2006.285.17:38:46.79#ibcon#about to read 3, iclass 11, count 0 2006.285.17:38:46.81#ibcon#read 3, iclass 11, count 0 2006.285.17:38:46.81#ibcon#about to read 4, iclass 11, count 0 2006.285.17:38:46.81#ibcon#read 4, iclass 11, count 0 2006.285.17:38:46.81#ibcon#about to read 5, iclass 11, count 0 2006.285.17:38:46.81#ibcon#read 5, iclass 11, count 0 2006.285.17:38:46.81#ibcon#about to read 6, iclass 11, count 0 2006.285.17:38:46.81#ibcon#read 6, iclass 11, count 0 2006.285.17:38:46.81#ibcon#end of sib2, iclass 11, count 0 2006.285.17:38:46.81#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:38:46.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:38:46.81#ibcon#[25=USB\r\n] 2006.285.17:38:46.81#ibcon#*before write, iclass 11, count 0 2006.285.17:38:46.81#ibcon#enter sib2, iclass 11, count 0 2006.285.17:38:46.81#ibcon#flushed, iclass 11, count 0 2006.285.17:38:46.81#ibcon#about to write, iclass 11, count 0 2006.285.17:38:46.81#ibcon#wrote, iclass 11, count 0 2006.285.17:38:46.81#ibcon#about to read 3, iclass 11, count 0 2006.285.17:38:46.84#ibcon#read 3, iclass 11, count 0 2006.285.17:38:46.84#ibcon#about to read 4, iclass 11, count 0 2006.285.17:38:46.84#ibcon#read 4, iclass 11, count 0 2006.285.17:38:46.84#ibcon#about to read 5, iclass 11, count 0 2006.285.17:38:46.84#ibcon#read 5, iclass 11, count 0 2006.285.17:38:46.84#ibcon#about to read 6, iclass 11, count 0 2006.285.17:38:46.84#ibcon#read 6, iclass 11, count 0 2006.285.17:38:46.84#ibcon#end of sib2, iclass 11, count 0 2006.285.17:38:46.84#ibcon#*after write, iclass 11, count 0 2006.285.17:38:46.84#ibcon#*before return 0, iclass 11, count 0 2006.285.17:38:46.84#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:38:46.84#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:38:46.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:38:46.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:38:46.84$vck44/vblo=1,629.99 2006.285.17:38:46.84#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.17:38:46.84#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.17:38:46.84#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:46.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:38:46.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:38:46.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:38:46.84#ibcon#enter wrdev, iclass 13, count 0 2006.285.17:38:46.84#ibcon#first serial, iclass 13, count 0 2006.285.17:38:46.84#ibcon#enter sib2, iclass 13, count 0 2006.285.17:38:46.84#ibcon#flushed, iclass 13, count 0 2006.285.17:38:46.84#ibcon#about to write, iclass 13, count 0 2006.285.17:38:46.84#ibcon#wrote, iclass 13, count 0 2006.285.17:38:46.84#ibcon#about to read 3, iclass 13, count 0 2006.285.17:38:46.86#ibcon#read 3, iclass 13, count 0 2006.285.17:38:46.86#ibcon#about to read 4, iclass 13, count 0 2006.285.17:38:46.86#ibcon#read 4, iclass 13, count 0 2006.285.17:38:46.86#ibcon#about to read 5, iclass 13, count 0 2006.285.17:38:46.86#ibcon#read 5, iclass 13, count 0 2006.285.17:38:46.86#ibcon#about to read 6, iclass 13, count 0 2006.285.17:38:46.86#ibcon#read 6, iclass 13, count 0 2006.285.17:38:46.86#ibcon#end of sib2, iclass 13, count 0 2006.285.17:38:46.86#ibcon#*mode == 0, iclass 13, count 0 2006.285.17:38:46.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.17:38:46.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.17:38:46.86#ibcon#*before write, iclass 13, count 0 2006.285.17:38:46.86#ibcon#enter sib2, iclass 13, count 0 2006.285.17:38:46.86#ibcon#flushed, iclass 13, count 0 2006.285.17:38:46.86#ibcon#about to write, iclass 13, count 0 2006.285.17:38:46.86#ibcon#wrote, iclass 13, count 0 2006.285.17:38:46.86#ibcon#about to read 3, iclass 13, count 0 2006.285.17:38:46.90#ibcon#read 3, iclass 13, count 0 2006.285.17:38:46.90#ibcon#about to read 4, iclass 13, count 0 2006.285.17:38:46.90#ibcon#read 4, iclass 13, count 0 2006.285.17:38:46.90#ibcon#about to read 5, iclass 13, count 0 2006.285.17:38:46.90#ibcon#read 5, iclass 13, count 0 2006.285.17:38:46.90#ibcon#about to read 6, iclass 13, count 0 2006.285.17:38:46.90#ibcon#read 6, iclass 13, count 0 2006.285.17:38:46.90#ibcon#end of sib2, iclass 13, count 0 2006.285.17:38:46.90#ibcon#*after write, iclass 13, count 0 2006.285.17:38:46.90#ibcon#*before return 0, iclass 13, count 0 2006.285.17:38:46.90#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:38:46.90#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:38:46.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.17:38:46.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.17:38:46.90$vck44/vb=1,4 2006.285.17:38:46.90#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.17:38:46.90#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.17:38:46.90#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:46.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:38:46.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:38:46.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:38:46.90#ibcon#enter wrdev, iclass 15, count 2 2006.285.17:38:46.90#ibcon#first serial, iclass 15, count 2 2006.285.17:38:46.90#ibcon#enter sib2, iclass 15, count 2 2006.285.17:38:46.90#ibcon#flushed, iclass 15, count 2 2006.285.17:38:46.90#ibcon#about to write, iclass 15, count 2 2006.285.17:38:46.90#ibcon#wrote, iclass 15, count 2 2006.285.17:38:46.90#ibcon#about to read 3, iclass 15, count 2 2006.285.17:38:46.92#ibcon#read 3, iclass 15, count 2 2006.285.17:38:46.92#ibcon#about to read 4, iclass 15, count 2 2006.285.17:38:46.92#ibcon#read 4, iclass 15, count 2 2006.285.17:38:46.92#ibcon#about to read 5, iclass 15, count 2 2006.285.17:38:46.92#ibcon#read 5, iclass 15, count 2 2006.285.17:38:46.92#ibcon#about to read 6, iclass 15, count 2 2006.285.17:38:46.92#ibcon#read 6, iclass 15, count 2 2006.285.17:38:46.92#ibcon#end of sib2, iclass 15, count 2 2006.285.17:38:46.92#ibcon#*mode == 0, iclass 15, count 2 2006.285.17:38:46.92#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.17:38:46.92#ibcon#[27=AT01-04\r\n] 2006.285.17:38:46.92#ibcon#*before write, iclass 15, count 2 2006.285.17:38:46.92#ibcon#enter sib2, iclass 15, count 2 2006.285.17:38:46.92#ibcon#flushed, iclass 15, count 2 2006.285.17:38:46.92#ibcon#about to write, iclass 15, count 2 2006.285.17:38:46.92#ibcon#wrote, iclass 15, count 2 2006.285.17:38:46.92#ibcon#about to read 3, iclass 15, count 2 2006.285.17:38:46.95#ibcon#read 3, iclass 15, count 2 2006.285.17:38:46.95#ibcon#about to read 4, iclass 15, count 2 2006.285.17:38:46.95#ibcon#read 4, iclass 15, count 2 2006.285.17:38:46.95#ibcon#about to read 5, iclass 15, count 2 2006.285.17:38:46.95#ibcon#read 5, iclass 15, count 2 2006.285.17:38:46.95#ibcon#about to read 6, iclass 15, count 2 2006.285.17:38:46.95#ibcon#read 6, iclass 15, count 2 2006.285.17:38:46.95#ibcon#end of sib2, iclass 15, count 2 2006.285.17:38:46.95#ibcon#*after write, iclass 15, count 2 2006.285.17:38:46.95#ibcon#*before return 0, iclass 15, count 2 2006.285.17:38:46.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:38:46.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:38:46.95#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.17:38:46.95#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:46.95#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:38:47.07#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:38:47.07#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:38:47.07#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:38:47.07#ibcon#first serial, iclass 15, count 0 2006.285.17:38:47.07#ibcon#enter sib2, iclass 15, count 0 2006.285.17:38:47.07#ibcon#flushed, iclass 15, count 0 2006.285.17:38:47.07#ibcon#about to write, iclass 15, count 0 2006.285.17:38:47.07#ibcon#wrote, iclass 15, count 0 2006.285.17:38:47.07#ibcon#about to read 3, iclass 15, count 0 2006.285.17:38:47.09#ibcon#read 3, iclass 15, count 0 2006.285.17:38:47.09#ibcon#about to read 4, iclass 15, count 0 2006.285.17:38:47.09#ibcon#read 4, iclass 15, count 0 2006.285.17:38:47.09#ibcon#about to read 5, iclass 15, count 0 2006.285.17:38:47.09#ibcon#read 5, iclass 15, count 0 2006.285.17:38:47.09#ibcon#about to read 6, iclass 15, count 0 2006.285.17:38:47.09#ibcon#read 6, iclass 15, count 0 2006.285.17:38:47.09#ibcon#end of sib2, iclass 15, count 0 2006.285.17:38:47.09#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:38:47.09#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:38:47.09#ibcon#[27=USB\r\n] 2006.285.17:38:47.09#ibcon#*before write, iclass 15, count 0 2006.285.17:38:47.09#ibcon#enter sib2, iclass 15, count 0 2006.285.17:38:47.09#ibcon#flushed, iclass 15, count 0 2006.285.17:38:47.09#ibcon#about to write, iclass 15, count 0 2006.285.17:38:47.09#ibcon#wrote, iclass 15, count 0 2006.285.17:38:47.09#ibcon#about to read 3, iclass 15, count 0 2006.285.17:38:47.12#ibcon#read 3, iclass 15, count 0 2006.285.17:38:47.12#ibcon#about to read 4, iclass 15, count 0 2006.285.17:38:47.12#ibcon#read 4, iclass 15, count 0 2006.285.17:38:47.12#ibcon#about to read 5, iclass 15, count 0 2006.285.17:38:47.12#ibcon#read 5, iclass 15, count 0 2006.285.17:38:47.12#ibcon#about to read 6, iclass 15, count 0 2006.285.17:38:47.12#ibcon#read 6, iclass 15, count 0 2006.285.17:38:47.12#ibcon#end of sib2, iclass 15, count 0 2006.285.17:38:47.12#ibcon#*after write, iclass 15, count 0 2006.285.17:38:47.12#ibcon#*before return 0, iclass 15, count 0 2006.285.17:38:47.12#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:38:47.12#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:38:47.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:38:47.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:38:47.12$vck44/vblo=2,634.99 2006.285.17:38:47.12#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.17:38:47.12#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.17:38:47.12#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:47.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:38:47.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:38:47.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:38:47.12#ibcon#enter wrdev, iclass 17, count 0 2006.285.17:38:47.12#ibcon#first serial, iclass 17, count 0 2006.285.17:38:47.12#ibcon#enter sib2, iclass 17, count 0 2006.285.17:38:47.12#ibcon#flushed, iclass 17, count 0 2006.285.17:38:47.12#ibcon#about to write, iclass 17, count 0 2006.285.17:38:47.12#ibcon#wrote, iclass 17, count 0 2006.285.17:38:47.12#ibcon#about to read 3, iclass 17, count 0 2006.285.17:38:47.14#ibcon#read 3, iclass 17, count 0 2006.285.17:38:47.24#ibcon#about to read 4, iclass 17, count 0 2006.285.17:38:47.24#ibcon#read 4, iclass 17, count 0 2006.285.17:38:47.24#ibcon#about to read 5, iclass 17, count 0 2006.285.17:38:47.24#ibcon#read 5, iclass 17, count 0 2006.285.17:38:47.24#ibcon#about to read 6, iclass 17, count 0 2006.285.17:38:47.24#ibcon#read 6, iclass 17, count 0 2006.285.17:38:47.24#ibcon#end of sib2, iclass 17, count 0 2006.285.17:38:47.24#ibcon#*mode == 0, iclass 17, count 0 2006.285.17:38:47.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.17:38:47.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.17:38:47.24#ibcon#*before write, iclass 17, count 0 2006.285.17:38:47.24#ibcon#enter sib2, iclass 17, count 0 2006.285.17:38:47.24#ibcon#flushed, iclass 17, count 0 2006.285.17:38:47.24#ibcon#about to write, iclass 17, count 0 2006.285.17:38:47.24#ibcon#wrote, iclass 17, count 0 2006.285.17:38:47.24#ibcon#about to read 3, iclass 17, count 0 2006.285.17:38:47.29#ibcon#read 3, iclass 17, count 0 2006.285.17:38:47.29#ibcon#about to read 4, iclass 17, count 0 2006.285.17:38:47.29#ibcon#read 4, iclass 17, count 0 2006.285.17:38:47.29#ibcon#about to read 5, iclass 17, count 0 2006.285.17:38:47.29#ibcon#read 5, iclass 17, count 0 2006.285.17:38:47.29#ibcon#about to read 6, iclass 17, count 0 2006.285.17:38:47.29#ibcon#read 6, iclass 17, count 0 2006.285.17:38:47.29#ibcon#end of sib2, iclass 17, count 0 2006.285.17:38:47.29#ibcon#*after write, iclass 17, count 0 2006.285.17:38:47.29#ibcon#*before return 0, iclass 17, count 0 2006.285.17:38:47.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:38:47.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:38:47.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.17:38:47.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.17:38:47.29$vck44/vb=2,5 2006.285.17:38:47.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.17:38:47.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.17:38:47.29#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:47.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:38:47.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:38:47.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:38:47.29#ibcon#enter wrdev, iclass 19, count 2 2006.285.17:38:47.29#ibcon#first serial, iclass 19, count 2 2006.285.17:38:47.29#ibcon#enter sib2, iclass 19, count 2 2006.285.17:38:47.29#ibcon#flushed, iclass 19, count 2 2006.285.17:38:47.29#ibcon#about to write, iclass 19, count 2 2006.285.17:38:47.29#ibcon#wrote, iclass 19, count 2 2006.285.17:38:47.29#ibcon#about to read 3, iclass 19, count 2 2006.285.17:38:47.31#ibcon#read 3, iclass 19, count 2 2006.285.17:38:47.31#ibcon#about to read 4, iclass 19, count 2 2006.285.17:38:47.31#ibcon#read 4, iclass 19, count 2 2006.285.17:38:47.31#ibcon#about to read 5, iclass 19, count 2 2006.285.17:38:47.31#ibcon#read 5, iclass 19, count 2 2006.285.17:38:47.31#ibcon#about to read 6, iclass 19, count 2 2006.285.17:38:47.31#ibcon#read 6, iclass 19, count 2 2006.285.17:38:47.31#ibcon#end of sib2, iclass 19, count 2 2006.285.17:38:47.31#ibcon#*mode == 0, iclass 19, count 2 2006.285.17:38:47.31#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.17:38:47.31#ibcon#[27=AT02-05\r\n] 2006.285.17:38:47.31#ibcon#*before write, iclass 19, count 2 2006.285.17:38:47.31#ibcon#enter sib2, iclass 19, count 2 2006.285.17:38:47.31#ibcon#flushed, iclass 19, count 2 2006.285.17:38:47.31#ibcon#about to write, iclass 19, count 2 2006.285.17:38:47.31#ibcon#wrote, iclass 19, count 2 2006.285.17:38:47.31#ibcon#about to read 3, iclass 19, count 2 2006.285.17:38:47.34#ibcon#read 3, iclass 19, count 2 2006.285.17:38:47.34#ibcon#about to read 4, iclass 19, count 2 2006.285.17:38:47.34#ibcon#read 4, iclass 19, count 2 2006.285.17:38:47.34#ibcon#about to read 5, iclass 19, count 2 2006.285.17:38:47.34#ibcon#read 5, iclass 19, count 2 2006.285.17:38:47.34#ibcon#about to read 6, iclass 19, count 2 2006.285.17:38:47.34#ibcon#read 6, iclass 19, count 2 2006.285.17:38:47.34#ibcon#end of sib2, iclass 19, count 2 2006.285.17:38:47.34#ibcon#*after write, iclass 19, count 2 2006.285.17:38:47.34#ibcon#*before return 0, iclass 19, count 2 2006.285.17:38:47.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:38:47.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:38:47.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.17:38:47.34#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:47.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:38:47.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:38:47.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:38:47.46#ibcon#enter wrdev, iclass 19, count 0 2006.285.17:38:47.46#ibcon#first serial, iclass 19, count 0 2006.285.17:38:47.46#ibcon#enter sib2, iclass 19, count 0 2006.285.17:38:47.46#ibcon#flushed, iclass 19, count 0 2006.285.17:38:47.46#ibcon#about to write, iclass 19, count 0 2006.285.17:38:47.46#ibcon#wrote, iclass 19, count 0 2006.285.17:38:47.46#ibcon#about to read 3, iclass 19, count 0 2006.285.17:38:47.48#ibcon#read 3, iclass 19, count 0 2006.285.17:38:47.48#ibcon#about to read 4, iclass 19, count 0 2006.285.17:38:47.48#ibcon#read 4, iclass 19, count 0 2006.285.17:38:47.48#ibcon#about to read 5, iclass 19, count 0 2006.285.17:38:47.48#ibcon#read 5, iclass 19, count 0 2006.285.17:38:47.48#ibcon#about to read 6, iclass 19, count 0 2006.285.17:38:47.48#ibcon#read 6, iclass 19, count 0 2006.285.17:38:47.48#ibcon#end of sib2, iclass 19, count 0 2006.285.17:38:47.48#ibcon#*mode == 0, iclass 19, count 0 2006.285.17:38:47.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.17:38:47.48#ibcon#[27=USB\r\n] 2006.285.17:38:47.48#ibcon#*before write, iclass 19, count 0 2006.285.17:38:47.48#ibcon#enter sib2, iclass 19, count 0 2006.285.17:38:47.48#ibcon#flushed, iclass 19, count 0 2006.285.17:38:47.48#ibcon#about to write, iclass 19, count 0 2006.285.17:38:47.48#ibcon#wrote, iclass 19, count 0 2006.285.17:38:47.48#ibcon#about to read 3, iclass 19, count 0 2006.285.17:38:47.51#ibcon#read 3, iclass 19, count 0 2006.285.17:38:47.51#ibcon#about to read 4, iclass 19, count 0 2006.285.17:38:47.51#ibcon#read 4, iclass 19, count 0 2006.285.17:38:47.51#ibcon#about to read 5, iclass 19, count 0 2006.285.17:38:47.51#ibcon#read 5, iclass 19, count 0 2006.285.17:38:47.51#ibcon#about to read 6, iclass 19, count 0 2006.285.17:38:47.51#ibcon#read 6, iclass 19, count 0 2006.285.17:38:47.51#ibcon#end of sib2, iclass 19, count 0 2006.285.17:38:47.51#ibcon#*after write, iclass 19, count 0 2006.285.17:38:47.51#ibcon#*before return 0, iclass 19, count 0 2006.285.17:38:47.51#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:38:47.51#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:38:47.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.17:38:47.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.17:38:47.51$vck44/vblo=3,649.99 2006.285.17:38:47.51#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.17:38:47.51#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.17:38:47.51#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:47.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:38:47.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:38:47.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:38:47.51#ibcon#enter wrdev, iclass 21, count 0 2006.285.17:38:47.51#ibcon#first serial, iclass 21, count 0 2006.285.17:38:47.51#ibcon#enter sib2, iclass 21, count 0 2006.285.17:38:47.51#ibcon#flushed, iclass 21, count 0 2006.285.17:38:47.51#ibcon#about to write, iclass 21, count 0 2006.285.17:38:47.51#ibcon#wrote, iclass 21, count 0 2006.285.17:38:47.51#ibcon#about to read 3, iclass 21, count 0 2006.285.17:38:47.53#ibcon#read 3, iclass 21, count 0 2006.285.17:38:47.53#ibcon#about to read 4, iclass 21, count 0 2006.285.17:38:47.53#ibcon#read 4, iclass 21, count 0 2006.285.17:38:47.53#ibcon#about to read 5, iclass 21, count 0 2006.285.17:38:47.53#ibcon#read 5, iclass 21, count 0 2006.285.17:38:47.53#ibcon#about to read 6, iclass 21, count 0 2006.285.17:38:47.53#ibcon#read 6, iclass 21, count 0 2006.285.17:38:47.53#ibcon#end of sib2, iclass 21, count 0 2006.285.17:38:47.53#ibcon#*mode == 0, iclass 21, count 0 2006.285.17:38:47.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.17:38:47.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.17:38:47.53#ibcon#*before write, iclass 21, count 0 2006.285.17:38:47.53#ibcon#enter sib2, iclass 21, count 0 2006.285.17:38:47.53#ibcon#flushed, iclass 21, count 0 2006.285.17:38:47.53#ibcon#about to write, iclass 21, count 0 2006.285.17:38:47.53#ibcon#wrote, iclass 21, count 0 2006.285.17:38:47.53#ibcon#about to read 3, iclass 21, count 0 2006.285.17:38:47.57#ibcon#read 3, iclass 21, count 0 2006.285.17:38:47.57#ibcon#about to read 4, iclass 21, count 0 2006.285.17:38:47.57#ibcon#read 4, iclass 21, count 0 2006.285.17:38:47.57#ibcon#about to read 5, iclass 21, count 0 2006.285.17:38:47.57#ibcon#read 5, iclass 21, count 0 2006.285.17:38:47.57#ibcon#about to read 6, iclass 21, count 0 2006.285.17:38:47.57#ibcon#read 6, iclass 21, count 0 2006.285.17:38:47.57#ibcon#end of sib2, iclass 21, count 0 2006.285.17:38:47.57#ibcon#*after write, iclass 21, count 0 2006.285.17:38:47.57#ibcon#*before return 0, iclass 21, count 0 2006.285.17:38:47.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:38:47.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:38:47.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.17:38:47.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.17:38:47.57$vck44/vb=3,4 2006.285.17:38:47.57#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.17:38:47.57#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.17:38:47.57#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:47.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:38:47.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:38:47.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:38:47.63#ibcon#enter wrdev, iclass 23, count 2 2006.285.17:38:47.63#ibcon#first serial, iclass 23, count 2 2006.285.17:38:47.63#ibcon#enter sib2, iclass 23, count 2 2006.285.17:38:47.63#ibcon#flushed, iclass 23, count 2 2006.285.17:38:47.63#ibcon#about to write, iclass 23, count 2 2006.285.17:38:47.63#ibcon#wrote, iclass 23, count 2 2006.285.17:38:47.63#ibcon#about to read 3, iclass 23, count 2 2006.285.17:38:47.65#ibcon#read 3, iclass 23, count 2 2006.285.17:38:47.65#ibcon#about to read 4, iclass 23, count 2 2006.285.17:38:47.65#ibcon#read 4, iclass 23, count 2 2006.285.17:38:47.65#ibcon#about to read 5, iclass 23, count 2 2006.285.17:38:47.65#ibcon#read 5, iclass 23, count 2 2006.285.17:38:47.65#ibcon#about to read 6, iclass 23, count 2 2006.285.17:38:47.65#ibcon#read 6, iclass 23, count 2 2006.285.17:38:47.65#ibcon#end of sib2, iclass 23, count 2 2006.285.17:38:47.65#ibcon#*mode == 0, iclass 23, count 2 2006.285.17:38:47.65#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.17:38:47.65#ibcon#[27=AT03-04\r\n] 2006.285.17:38:47.65#ibcon#*before write, iclass 23, count 2 2006.285.17:38:47.65#ibcon#enter sib2, iclass 23, count 2 2006.285.17:38:47.65#ibcon#flushed, iclass 23, count 2 2006.285.17:38:47.65#ibcon#about to write, iclass 23, count 2 2006.285.17:38:47.65#ibcon#wrote, iclass 23, count 2 2006.285.17:38:47.65#ibcon#about to read 3, iclass 23, count 2 2006.285.17:38:47.68#ibcon#read 3, iclass 23, count 2 2006.285.17:38:47.68#ibcon#about to read 4, iclass 23, count 2 2006.285.17:38:47.68#ibcon#read 4, iclass 23, count 2 2006.285.17:38:47.68#ibcon#about to read 5, iclass 23, count 2 2006.285.17:38:47.68#ibcon#read 5, iclass 23, count 2 2006.285.17:38:47.68#ibcon#about to read 6, iclass 23, count 2 2006.285.17:38:47.68#ibcon#read 6, iclass 23, count 2 2006.285.17:38:47.68#ibcon#end of sib2, iclass 23, count 2 2006.285.17:38:47.68#ibcon#*after write, iclass 23, count 2 2006.285.17:38:47.68#ibcon#*before return 0, iclass 23, count 2 2006.285.17:38:47.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:38:47.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:38:47.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.17:38:47.68#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:47.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:38:47.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:38:47.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:38:47.80#ibcon#enter wrdev, iclass 23, count 0 2006.285.17:38:47.80#ibcon#first serial, iclass 23, count 0 2006.285.17:38:47.80#ibcon#enter sib2, iclass 23, count 0 2006.285.17:38:47.80#ibcon#flushed, iclass 23, count 0 2006.285.17:38:47.80#ibcon#about to write, iclass 23, count 0 2006.285.17:38:47.80#ibcon#wrote, iclass 23, count 0 2006.285.17:38:47.80#ibcon#about to read 3, iclass 23, count 0 2006.285.17:38:47.82#ibcon#read 3, iclass 23, count 0 2006.285.17:38:47.82#ibcon#about to read 4, iclass 23, count 0 2006.285.17:38:47.82#ibcon#read 4, iclass 23, count 0 2006.285.17:38:47.82#ibcon#about to read 5, iclass 23, count 0 2006.285.17:38:47.82#ibcon#read 5, iclass 23, count 0 2006.285.17:38:47.82#ibcon#about to read 6, iclass 23, count 0 2006.285.17:38:47.82#ibcon#read 6, iclass 23, count 0 2006.285.17:38:47.82#ibcon#end of sib2, iclass 23, count 0 2006.285.17:38:47.82#ibcon#*mode == 0, iclass 23, count 0 2006.285.17:38:47.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.17:38:47.82#ibcon#[27=USB\r\n] 2006.285.17:38:47.82#ibcon#*before write, iclass 23, count 0 2006.285.17:38:47.82#ibcon#enter sib2, iclass 23, count 0 2006.285.17:38:47.82#ibcon#flushed, iclass 23, count 0 2006.285.17:38:47.82#ibcon#about to write, iclass 23, count 0 2006.285.17:38:47.82#ibcon#wrote, iclass 23, count 0 2006.285.17:38:47.82#ibcon#about to read 3, iclass 23, count 0 2006.285.17:38:47.85#ibcon#read 3, iclass 23, count 0 2006.285.17:38:47.85#ibcon#about to read 4, iclass 23, count 0 2006.285.17:38:47.85#ibcon#read 4, iclass 23, count 0 2006.285.17:38:47.85#ibcon#about to read 5, iclass 23, count 0 2006.285.17:38:47.85#ibcon#read 5, iclass 23, count 0 2006.285.17:38:47.85#ibcon#about to read 6, iclass 23, count 0 2006.285.17:38:47.85#ibcon#read 6, iclass 23, count 0 2006.285.17:38:47.85#ibcon#end of sib2, iclass 23, count 0 2006.285.17:38:47.85#ibcon#*after write, iclass 23, count 0 2006.285.17:38:47.85#ibcon#*before return 0, iclass 23, count 0 2006.285.17:38:47.85#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:38:47.85#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:38:47.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.17:38:47.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.17:38:47.85$vck44/vblo=4,679.99 2006.285.17:38:47.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.17:38:47.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.17:38:47.85#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:47.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:38:47.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:38:47.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:38:47.85#ibcon#enter wrdev, iclass 25, count 0 2006.285.17:38:47.85#ibcon#first serial, iclass 25, count 0 2006.285.17:38:47.85#ibcon#enter sib2, iclass 25, count 0 2006.285.17:38:47.85#ibcon#flushed, iclass 25, count 0 2006.285.17:38:47.85#ibcon#about to write, iclass 25, count 0 2006.285.17:38:47.85#ibcon#wrote, iclass 25, count 0 2006.285.17:38:47.85#ibcon#about to read 3, iclass 25, count 0 2006.285.17:38:47.87#ibcon#read 3, iclass 25, count 0 2006.285.17:38:47.87#ibcon#about to read 4, iclass 25, count 0 2006.285.17:38:47.87#ibcon#read 4, iclass 25, count 0 2006.285.17:38:47.87#ibcon#about to read 5, iclass 25, count 0 2006.285.17:38:47.87#ibcon#read 5, iclass 25, count 0 2006.285.17:38:47.87#ibcon#about to read 6, iclass 25, count 0 2006.285.17:38:47.87#ibcon#read 6, iclass 25, count 0 2006.285.17:38:47.87#ibcon#end of sib2, iclass 25, count 0 2006.285.17:38:47.87#ibcon#*mode == 0, iclass 25, count 0 2006.285.17:38:47.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.17:38:47.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.17:38:47.87#ibcon#*before write, iclass 25, count 0 2006.285.17:38:47.87#ibcon#enter sib2, iclass 25, count 0 2006.285.17:38:47.87#ibcon#flushed, iclass 25, count 0 2006.285.17:38:47.87#ibcon#about to write, iclass 25, count 0 2006.285.17:38:47.87#ibcon#wrote, iclass 25, count 0 2006.285.17:38:47.87#ibcon#about to read 3, iclass 25, count 0 2006.285.17:38:47.91#ibcon#read 3, iclass 25, count 0 2006.285.17:38:47.91#ibcon#about to read 4, iclass 25, count 0 2006.285.17:38:47.91#ibcon#read 4, iclass 25, count 0 2006.285.17:38:47.91#ibcon#about to read 5, iclass 25, count 0 2006.285.17:38:47.91#ibcon#read 5, iclass 25, count 0 2006.285.17:38:47.91#ibcon#about to read 6, iclass 25, count 0 2006.285.17:38:47.91#ibcon#read 6, iclass 25, count 0 2006.285.17:38:47.91#ibcon#end of sib2, iclass 25, count 0 2006.285.17:38:47.91#ibcon#*after write, iclass 25, count 0 2006.285.17:38:47.91#ibcon#*before return 0, iclass 25, count 0 2006.285.17:38:47.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:38:47.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:38:47.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.17:38:47.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.17:38:47.91$vck44/vb=4,5 2006.285.17:38:47.91#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.17:38:47.91#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.17:38:47.91#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:47.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:38:47.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:38:47.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:38:47.97#ibcon#enter wrdev, iclass 27, count 2 2006.285.17:38:47.97#ibcon#first serial, iclass 27, count 2 2006.285.17:38:47.97#ibcon#enter sib2, iclass 27, count 2 2006.285.17:38:47.97#ibcon#flushed, iclass 27, count 2 2006.285.17:38:47.97#ibcon#about to write, iclass 27, count 2 2006.285.17:38:47.97#ibcon#wrote, iclass 27, count 2 2006.285.17:38:47.97#ibcon#about to read 3, iclass 27, count 2 2006.285.17:38:47.99#ibcon#read 3, iclass 27, count 2 2006.285.17:38:47.99#ibcon#about to read 4, iclass 27, count 2 2006.285.17:38:47.99#ibcon#read 4, iclass 27, count 2 2006.285.17:38:47.99#ibcon#about to read 5, iclass 27, count 2 2006.285.17:38:47.99#ibcon#read 5, iclass 27, count 2 2006.285.17:38:47.99#ibcon#about to read 6, iclass 27, count 2 2006.285.17:38:47.99#ibcon#read 6, iclass 27, count 2 2006.285.17:38:47.99#ibcon#end of sib2, iclass 27, count 2 2006.285.17:38:47.99#ibcon#*mode == 0, iclass 27, count 2 2006.285.17:38:47.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.17:38:47.99#ibcon#[27=AT04-05\r\n] 2006.285.17:38:47.99#ibcon#*before write, iclass 27, count 2 2006.285.17:38:47.99#ibcon#enter sib2, iclass 27, count 2 2006.285.17:38:47.99#ibcon#flushed, iclass 27, count 2 2006.285.17:38:47.99#ibcon#about to write, iclass 27, count 2 2006.285.17:38:47.99#ibcon#wrote, iclass 27, count 2 2006.285.17:38:47.99#ibcon#about to read 3, iclass 27, count 2 2006.285.17:38:48.02#ibcon#read 3, iclass 27, count 2 2006.285.17:38:48.02#ibcon#about to read 4, iclass 27, count 2 2006.285.17:38:48.02#ibcon#read 4, iclass 27, count 2 2006.285.17:38:48.02#ibcon#about to read 5, iclass 27, count 2 2006.285.17:38:48.02#ibcon#read 5, iclass 27, count 2 2006.285.17:38:48.02#ibcon#about to read 6, iclass 27, count 2 2006.285.17:38:48.02#ibcon#read 6, iclass 27, count 2 2006.285.17:38:48.02#ibcon#end of sib2, iclass 27, count 2 2006.285.17:38:48.02#ibcon#*after write, iclass 27, count 2 2006.285.17:38:48.02#ibcon#*before return 0, iclass 27, count 2 2006.285.17:38:48.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:38:48.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:38:48.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.17:38:48.02#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:48.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:38:48.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:38:48.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:38:48.14#ibcon#enter wrdev, iclass 27, count 0 2006.285.17:38:48.14#ibcon#first serial, iclass 27, count 0 2006.285.17:38:48.14#ibcon#enter sib2, iclass 27, count 0 2006.285.17:38:48.14#ibcon#flushed, iclass 27, count 0 2006.285.17:38:48.14#ibcon#about to write, iclass 27, count 0 2006.285.17:38:48.14#ibcon#wrote, iclass 27, count 0 2006.285.17:38:48.14#ibcon#about to read 3, iclass 27, count 0 2006.285.17:38:48.16#ibcon#read 3, iclass 27, count 0 2006.285.17:38:48.16#ibcon#about to read 4, iclass 27, count 0 2006.285.17:38:48.16#ibcon#read 4, iclass 27, count 0 2006.285.17:38:48.16#ibcon#about to read 5, iclass 27, count 0 2006.285.17:38:48.16#ibcon#read 5, iclass 27, count 0 2006.285.17:38:48.16#ibcon#about to read 6, iclass 27, count 0 2006.285.17:38:48.16#ibcon#read 6, iclass 27, count 0 2006.285.17:38:48.16#ibcon#end of sib2, iclass 27, count 0 2006.285.17:38:48.16#ibcon#*mode == 0, iclass 27, count 0 2006.285.17:38:48.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.17:38:48.16#ibcon#[27=USB\r\n] 2006.285.17:38:48.16#ibcon#*before write, iclass 27, count 0 2006.285.17:38:48.16#ibcon#enter sib2, iclass 27, count 0 2006.285.17:38:48.16#ibcon#flushed, iclass 27, count 0 2006.285.17:38:48.16#ibcon#about to write, iclass 27, count 0 2006.285.17:38:48.16#ibcon#wrote, iclass 27, count 0 2006.285.17:38:48.16#ibcon#about to read 3, iclass 27, count 0 2006.285.17:38:48.19#ibcon#read 3, iclass 27, count 0 2006.285.17:38:48.19#ibcon#about to read 4, iclass 27, count 0 2006.285.17:38:48.19#ibcon#read 4, iclass 27, count 0 2006.285.17:38:48.19#ibcon#about to read 5, iclass 27, count 0 2006.285.17:38:48.19#ibcon#read 5, iclass 27, count 0 2006.285.17:38:48.19#ibcon#about to read 6, iclass 27, count 0 2006.285.17:38:48.19#ibcon#read 6, iclass 27, count 0 2006.285.17:38:48.19#ibcon#end of sib2, iclass 27, count 0 2006.285.17:38:48.19#ibcon#*after write, iclass 27, count 0 2006.285.17:38:48.19#ibcon#*before return 0, iclass 27, count 0 2006.285.17:38:48.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:38:48.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:38:48.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.17:38:48.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.17:38:48.19$vck44/vblo=5,709.99 2006.285.17:38:48.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.17:38:48.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.17:38:48.21#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:48.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:38:48.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:38:48.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:38:48.21#ibcon#enter wrdev, iclass 29, count 0 2006.285.17:38:48.21#ibcon#first serial, iclass 29, count 0 2006.285.17:38:48.21#ibcon#enter sib2, iclass 29, count 0 2006.285.17:38:48.21#ibcon#flushed, iclass 29, count 0 2006.285.17:38:48.21#ibcon#about to write, iclass 29, count 0 2006.285.17:38:48.21#ibcon#wrote, iclass 29, count 0 2006.285.17:38:48.21#ibcon#about to read 3, iclass 29, count 0 2006.285.17:38:48.23#ibcon#read 3, iclass 29, count 0 2006.285.17:38:48.23#ibcon#about to read 4, iclass 29, count 0 2006.285.17:38:48.23#ibcon#read 4, iclass 29, count 0 2006.285.17:38:48.23#ibcon#about to read 5, iclass 29, count 0 2006.285.17:38:48.23#ibcon#read 5, iclass 29, count 0 2006.285.17:38:48.23#ibcon#about to read 6, iclass 29, count 0 2006.285.17:38:48.23#ibcon#read 6, iclass 29, count 0 2006.285.17:38:48.23#ibcon#end of sib2, iclass 29, count 0 2006.285.17:38:48.23#ibcon#*mode == 0, iclass 29, count 0 2006.285.17:38:48.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.17:38:48.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.17:38:48.23#ibcon#*before write, iclass 29, count 0 2006.285.17:38:48.23#ibcon#enter sib2, iclass 29, count 0 2006.285.17:38:48.23#ibcon#flushed, iclass 29, count 0 2006.285.17:38:48.23#ibcon#about to write, iclass 29, count 0 2006.285.17:38:48.23#ibcon#wrote, iclass 29, count 0 2006.285.17:38:48.23#ibcon#about to read 3, iclass 29, count 0 2006.285.17:38:48.27#ibcon#read 3, iclass 29, count 0 2006.285.17:38:48.27#ibcon#about to read 4, iclass 29, count 0 2006.285.17:38:48.27#ibcon#read 4, iclass 29, count 0 2006.285.17:38:48.27#ibcon#about to read 5, iclass 29, count 0 2006.285.17:38:48.27#ibcon#read 5, iclass 29, count 0 2006.285.17:38:48.27#ibcon#about to read 6, iclass 29, count 0 2006.285.17:38:48.27#ibcon#read 6, iclass 29, count 0 2006.285.17:38:48.27#ibcon#end of sib2, iclass 29, count 0 2006.285.17:38:48.27#ibcon#*after write, iclass 29, count 0 2006.285.17:38:48.27#ibcon#*before return 0, iclass 29, count 0 2006.285.17:38:48.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:38:48.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:38:48.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.17:38:48.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.17:38:48.27$vck44/vb=5,4 2006.285.17:38:48.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.17:38:48.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.17:38:48.27#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:48.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:38:48.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:38:48.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:38:48.31#ibcon#enter wrdev, iclass 31, count 2 2006.285.17:38:48.31#ibcon#first serial, iclass 31, count 2 2006.285.17:38:48.31#ibcon#enter sib2, iclass 31, count 2 2006.285.17:38:48.31#ibcon#flushed, iclass 31, count 2 2006.285.17:38:48.31#ibcon#about to write, iclass 31, count 2 2006.285.17:38:48.31#ibcon#wrote, iclass 31, count 2 2006.285.17:38:48.31#ibcon#about to read 3, iclass 31, count 2 2006.285.17:38:48.33#ibcon#read 3, iclass 31, count 2 2006.285.17:38:48.33#ibcon#about to read 4, iclass 31, count 2 2006.285.17:38:48.33#ibcon#read 4, iclass 31, count 2 2006.285.17:38:48.33#ibcon#about to read 5, iclass 31, count 2 2006.285.17:38:48.33#ibcon#read 5, iclass 31, count 2 2006.285.17:38:48.33#ibcon#about to read 6, iclass 31, count 2 2006.285.17:38:48.33#ibcon#read 6, iclass 31, count 2 2006.285.17:38:48.33#ibcon#end of sib2, iclass 31, count 2 2006.285.17:38:48.33#ibcon#*mode == 0, iclass 31, count 2 2006.285.17:38:48.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.17:38:48.33#ibcon#[27=AT05-04\r\n] 2006.285.17:38:48.33#ibcon#*before write, iclass 31, count 2 2006.285.17:38:48.33#ibcon#enter sib2, iclass 31, count 2 2006.285.17:38:48.33#ibcon#flushed, iclass 31, count 2 2006.285.17:38:48.33#ibcon#about to write, iclass 31, count 2 2006.285.17:38:48.33#ibcon#wrote, iclass 31, count 2 2006.285.17:38:48.33#ibcon#about to read 3, iclass 31, count 2 2006.285.17:38:48.36#ibcon#read 3, iclass 31, count 2 2006.285.17:38:48.36#ibcon#about to read 4, iclass 31, count 2 2006.285.17:38:48.36#ibcon#read 4, iclass 31, count 2 2006.285.17:38:48.36#ibcon#about to read 5, iclass 31, count 2 2006.285.17:38:48.36#ibcon#read 5, iclass 31, count 2 2006.285.17:38:48.36#ibcon#about to read 6, iclass 31, count 2 2006.285.17:38:48.36#ibcon#read 6, iclass 31, count 2 2006.285.17:38:48.36#ibcon#end of sib2, iclass 31, count 2 2006.285.17:38:48.36#ibcon#*after write, iclass 31, count 2 2006.285.17:38:48.36#ibcon#*before return 0, iclass 31, count 2 2006.285.17:38:48.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:38:48.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:38:48.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.17:38:48.36#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:48.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:38:48.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:38:48.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:38:48.48#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:38:48.48#ibcon#first serial, iclass 31, count 0 2006.285.17:38:48.48#ibcon#enter sib2, iclass 31, count 0 2006.285.17:38:48.48#ibcon#flushed, iclass 31, count 0 2006.285.17:38:48.48#ibcon#about to write, iclass 31, count 0 2006.285.17:38:48.48#ibcon#wrote, iclass 31, count 0 2006.285.17:38:48.48#ibcon#about to read 3, iclass 31, count 0 2006.285.17:38:48.50#ibcon#read 3, iclass 31, count 0 2006.285.17:38:48.50#ibcon#about to read 4, iclass 31, count 0 2006.285.17:38:48.50#ibcon#read 4, iclass 31, count 0 2006.285.17:38:48.50#ibcon#about to read 5, iclass 31, count 0 2006.285.17:38:48.50#ibcon#read 5, iclass 31, count 0 2006.285.17:38:48.50#ibcon#about to read 6, iclass 31, count 0 2006.285.17:38:48.50#ibcon#read 6, iclass 31, count 0 2006.285.17:38:48.50#ibcon#end of sib2, iclass 31, count 0 2006.285.17:38:48.50#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:38:48.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:38:48.50#ibcon#[27=USB\r\n] 2006.285.17:38:48.50#ibcon#*before write, iclass 31, count 0 2006.285.17:38:48.50#ibcon#enter sib2, iclass 31, count 0 2006.285.17:38:48.50#ibcon#flushed, iclass 31, count 0 2006.285.17:38:48.50#ibcon#about to write, iclass 31, count 0 2006.285.17:38:48.50#ibcon#wrote, iclass 31, count 0 2006.285.17:38:48.50#ibcon#about to read 3, iclass 31, count 0 2006.285.17:38:48.53#ibcon#read 3, iclass 31, count 0 2006.285.17:38:48.53#ibcon#about to read 4, iclass 31, count 0 2006.285.17:38:48.53#ibcon#read 4, iclass 31, count 0 2006.285.17:38:48.53#ibcon#about to read 5, iclass 31, count 0 2006.285.17:38:48.53#ibcon#read 5, iclass 31, count 0 2006.285.17:38:48.53#ibcon#about to read 6, iclass 31, count 0 2006.285.17:38:48.53#ibcon#read 6, iclass 31, count 0 2006.285.17:38:48.53#ibcon#end of sib2, iclass 31, count 0 2006.285.17:38:48.53#ibcon#*after write, iclass 31, count 0 2006.285.17:38:48.53#ibcon#*before return 0, iclass 31, count 0 2006.285.17:38:48.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:38:48.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:38:48.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:38:48.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:38:48.53$vck44/vblo=6,719.99 2006.285.17:38:48.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.17:38:48.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.17:38:48.53#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:48.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:38:48.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:38:48.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:38:48.53#ibcon#enter wrdev, iclass 33, count 0 2006.285.17:38:48.53#ibcon#first serial, iclass 33, count 0 2006.285.17:38:48.53#ibcon#enter sib2, iclass 33, count 0 2006.285.17:38:48.53#ibcon#flushed, iclass 33, count 0 2006.285.17:38:48.53#ibcon#about to write, iclass 33, count 0 2006.285.17:38:48.53#ibcon#wrote, iclass 33, count 0 2006.285.17:38:48.53#ibcon#about to read 3, iclass 33, count 0 2006.285.17:38:48.55#ibcon#read 3, iclass 33, count 0 2006.285.17:38:48.55#ibcon#about to read 4, iclass 33, count 0 2006.285.17:38:48.55#ibcon#read 4, iclass 33, count 0 2006.285.17:38:48.55#ibcon#about to read 5, iclass 33, count 0 2006.285.17:38:48.55#ibcon#read 5, iclass 33, count 0 2006.285.17:38:48.55#ibcon#about to read 6, iclass 33, count 0 2006.285.17:38:48.55#ibcon#read 6, iclass 33, count 0 2006.285.17:38:48.55#ibcon#end of sib2, iclass 33, count 0 2006.285.17:38:48.55#ibcon#*mode == 0, iclass 33, count 0 2006.285.17:38:48.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.17:38:48.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.17:38:48.55#ibcon#*before write, iclass 33, count 0 2006.285.17:38:48.55#ibcon#enter sib2, iclass 33, count 0 2006.285.17:38:48.55#ibcon#flushed, iclass 33, count 0 2006.285.17:38:48.55#ibcon#about to write, iclass 33, count 0 2006.285.17:38:48.55#ibcon#wrote, iclass 33, count 0 2006.285.17:38:48.55#ibcon#about to read 3, iclass 33, count 0 2006.285.17:38:48.59#ibcon#read 3, iclass 33, count 0 2006.285.17:38:48.59#ibcon#about to read 4, iclass 33, count 0 2006.285.17:38:48.59#ibcon#read 4, iclass 33, count 0 2006.285.17:38:48.59#ibcon#about to read 5, iclass 33, count 0 2006.285.17:38:48.59#ibcon#read 5, iclass 33, count 0 2006.285.17:38:48.59#ibcon#about to read 6, iclass 33, count 0 2006.285.17:38:48.59#ibcon#read 6, iclass 33, count 0 2006.285.17:38:48.59#ibcon#end of sib2, iclass 33, count 0 2006.285.17:38:48.59#ibcon#*after write, iclass 33, count 0 2006.285.17:38:48.59#ibcon#*before return 0, iclass 33, count 0 2006.285.17:38:48.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:38:48.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:38:48.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.17:38:48.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.17:38:48.59$vck44/vb=6,3 2006.285.17:38:48.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.17:38:48.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.17:38:48.59#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:48.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:38:48.64#abcon#<5=/14 0.3 1.2 16.58 991014.7\r\n> 2006.285.17:38:48.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:38:48.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:38:48.65#ibcon#enter wrdev, iclass 35, count 2 2006.285.17:38:48.65#ibcon#first serial, iclass 35, count 2 2006.285.17:38:48.65#ibcon#enter sib2, iclass 35, count 2 2006.285.17:38:48.65#ibcon#flushed, iclass 35, count 2 2006.285.17:38:48.65#ibcon#about to write, iclass 35, count 2 2006.285.17:38:48.65#ibcon#wrote, iclass 35, count 2 2006.285.17:38:48.65#ibcon#about to read 3, iclass 35, count 2 2006.285.17:38:48.66#abcon#{5=INTERFACE CLEAR} 2006.285.17:38:48.67#ibcon#read 3, iclass 35, count 2 2006.285.17:38:48.67#ibcon#about to read 4, iclass 35, count 2 2006.285.17:38:48.67#ibcon#read 4, iclass 35, count 2 2006.285.17:38:48.67#ibcon#about to read 5, iclass 35, count 2 2006.285.17:38:48.67#ibcon#read 5, iclass 35, count 2 2006.285.17:38:48.67#ibcon#about to read 6, iclass 35, count 2 2006.285.17:38:48.67#ibcon#read 6, iclass 35, count 2 2006.285.17:38:48.67#ibcon#end of sib2, iclass 35, count 2 2006.285.17:38:48.67#ibcon#*mode == 0, iclass 35, count 2 2006.285.17:38:48.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.17:38:48.67#ibcon#[27=AT06-03\r\n] 2006.285.17:38:48.67#ibcon#*before write, iclass 35, count 2 2006.285.17:38:48.67#ibcon#enter sib2, iclass 35, count 2 2006.285.17:38:48.67#ibcon#flushed, iclass 35, count 2 2006.285.17:38:48.67#ibcon#about to write, iclass 35, count 2 2006.285.17:38:48.67#ibcon#wrote, iclass 35, count 2 2006.285.17:38:48.67#ibcon#about to read 3, iclass 35, count 2 2006.285.17:38:48.70#ibcon#read 3, iclass 35, count 2 2006.285.17:38:48.70#ibcon#about to read 4, iclass 35, count 2 2006.285.17:38:48.70#ibcon#read 4, iclass 35, count 2 2006.285.17:38:48.70#ibcon#about to read 5, iclass 35, count 2 2006.285.17:38:48.70#ibcon#read 5, iclass 35, count 2 2006.285.17:38:48.70#ibcon#about to read 6, iclass 35, count 2 2006.285.17:38:48.70#ibcon#read 6, iclass 35, count 2 2006.285.17:38:48.70#ibcon#end of sib2, iclass 35, count 2 2006.285.17:38:48.70#ibcon#*after write, iclass 35, count 2 2006.285.17:38:48.70#ibcon#*before return 0, iclass 35, count 2 2006.285.17:38:48.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:38:48.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:38:48.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.17:38:48.70#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:48.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:38:48.72#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:38:48.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:38:48.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:38:48.82#ibcon#enter wrdev, iclass 35, count 0 2006.285.17:38:48.82#ibcon#first serial, iclass 35, count 0 2006.285.17:38:48.82#ibcon#enter sib2, iclass 35, count 0 2006.285.17:38:48.82#ibcon#flushed, iclass 35, count 0 2006.285.17:38:48.82#ibcon#about to write, iclass 35, count 0 2006.285.17:38:48.82#ibcon#wrote, iclass 35, count 0 2006.285.17:38:48.82#ibcon#about to read 3, iclass 35, count 0 2006.285.17:38:48.84#ibcon#read 3, iclass 35, count 0 2006.285.17:38:48.84#ibcon#about to read 4, iclass 35, count 0 2006.285.17:38:48.84#ibcon#read 4, iclass 35, count 0 2006.285.17:38:48.84#ibcon#about to read 5, iclass 35, count 0 2006.285.17:38:48.84#ibcon#read 5, iclass 35, count 0 2006.285.17:38:48.84#ibcon#about to read 6, iclass 35, count 0 2006.285.17:38:48.84#ibcon#read 6, iclass 35, count 0 2006.285.17:38:48.84#ibcon#end of sib2, iclass 35, count 0 2006.285.17:38:48.84#ibcon#*mode == 0, iclass 35, count 0 2006.285.17:38:48.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.17:38:48.84#ibcon#[27=USB\r\n] 2006.285.17:38:48.84#ibcon#*before write, iclass 35, count 0 2006.285.17:38:48.84#ibcon#enter sib2, iclass 35, count 0 2006.285.17:38:48.84#ibcon#flushed, iclass 35, count 0 2006.285.17:38:48.84#ibcon#about to write, iclass 35, count 0 2006.285.17:38:48.84#ibcon#wrote, iclass 35, count 0 2006.285.17:38:48.84#ibcon#about to read 3, iclass 35, count 0 2006.285.17:38:48.87#ibcon#read 3, iclass 35, count 0 2006.285.17:38:48.87#ibcon#about to read 4, iclass 35, count 0 2006.285.17:38:48.87#ibcon#read 4, iclass 35, count 0 2006.285.17:38:48.87#ibcon#about to read 5, iclass 35, count 0 2006.285.17:38:48.87#ibcon#read 5, iclass 35, count 0 2006.285.17:38:48.87#ibcon#about to read 6, iclass 35, count 0 2006.285.17:38:48.87#ibcon#read 6, iclass 35, count 0 2006.285.17:38:48.87#ibcon#end of sib2, iclass 35, count 0 2006.285.17:38:48.87#ibcon#*after write, iclass 35, count 0 2006.285.17:38:48.87#ibcon#*before return 0, iclass 35, count 0 2006.285.17:38:48.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:38:48.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:38:48.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.17:38:48.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.17:38:48.87$vck44/vblo=7,734.99 2006.285.17:38:48.87#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.17:38:48.87#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.17:38:48.87#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:48.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:38:48.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:38:48.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:38:48.87#ibcon#enter wrdev, iclass 3, count 0 2006.285.17:38:48.87#ibcon#first serial, iclass 3, count 0 2006.285.17:38:48.87#ibcon#enter sib2, iclass 3, count 0 2006.285.17:38:48.87#ibcon#flushed, iclass 3, count 0 2006.285.17:38:48.87#ibcon#about to write, iclass 3, count 0 2006.285.17:38:48.87#ibcon#wrote, iclass 3, count 0 2006.285.17:38:48.87#ibcon#about to read 3, iclass 3, count 0 2006.285.17:38:48.89#ibcon#read 3, iclass 3, count 0 2006.285.17:38:48.89#ibcon#about to read 4, iclass 3, count 0 2006.285.17:38:48.89#ibcon#read 4, iclass 3, count 0 2006.285.17:38:48.89#ibcon#about to read 5, iclass 3, count 0 2006.285.17:38:48.89#ibcon#read 5, iclass 3, count 0 2006.285.17:38:48.89#ibcon#about to read 6, iclass 3, count 0 2006.285.17:38:48.89#ibcon#read 6, iclass 3, count 0 2006.285.17:38:48.89#ibcon#end of sib2, iclass 3, count 0 2006.285.17:38:48.89#ibcon#*mode == 0, iclass 3, count 0 2006.285.17:38:48.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.17:38:48.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.17:38:48.89#ibcon#*before write, iclass 3, count 0 2006.285.17:38:48.89#ibcon#enter sib2, iclass 3, count 0 2006.285.17:38:48.89#ibcon#flushed, iclass 3, count 0 2006.285.17:38:48.89#ibcon#about to write, iclass 3, count 0 2006.285.17:38:48.89#ibcon#wrote, iclass 3, count 0 2006.285.17:38:48.89#ibcon#about to read 3, iclass 3, count 0 2006.285.17:38:48.93#ibcon#read 3, iclass 3, count 0 2006.285.17:38:48.93#ibcon#about to read 4, iclass 3, count 0 2006.285.17:38:48.93#ibcon#read 4, iclass 3, count 0 2006.285.17:38:48.93#ibcon#about to read 5, iclass 3, count 0 2006.285.17:38:48.93#ibcon#read 5, iclass 3, count 0 2006.285.17:38:48.93#ibcon#about to read 6, iclass 3, count 0 2006.285.17:38:48.93#ibcon#read 6, iclass 3, count 0 2006.285.17:38:48.93#ibcon#end of sib2, iclass 3, count 0 2006.285.17:38:48.93#ibcon#*after write, iclass 3, count 0 2006.285.17:38:48.93#ibcon#*before return 0, iclass 3, count 0 2006.285.17:38:48.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:38:48.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:38:48.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.17:38:48.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.17:38:48.93$vck44/vb=7,4 2006.285.17:38:48.93#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.17:38:48.93#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.17:38:48.93#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:48.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:38:48.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:38:48.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:38:48.99#ibcon#enter wrdev, iclass 5, count 2 2006.285.17:38:48.99#ibcon#first serial, iclass 5, count 2 2006.285.17:38:48.99#ibcon#enter sib2, iclass 5, count 2 2006.285.17:38:48.99#ibcon#flushed, iclass 5, count 2 2006.285.17:38:48.99#ibcon#about to write, iclass 5, count 2 2006.285.17:38:48.99#ibcon#wrote, iclass 5, count 2 2006.285.17:38:48.99#ibcon#about to read 3, iclass 5, count 2 2006.285.17:38:49.01#ibcon#read 3, iclass 5, count 2 2006.285.17:38:49.01#ibcon#about to read 4, iclass 5, count 2 2006.285.17:38:49.01#ibcon#read 4, iclass 5, count 2 2006.285.17:38:49.01#ibcon#about to read 5, iclass 5, count 2 2006.285.17:38:49.01#ibcon#read 5, iclass 5, count 2 2006.285.17:38:49.01#ibcon#about to read 6, iclass 5, count 2 2006.285.17:38:49.01#ibcon#read 6, iclass 5, count 2 2006.285.17:38:49.01#ibcon#end of sib2, iclass 5, count 2 2006.285.17:38:49.01#ibcon#*mode == 0, iclass 5, count 2 2006.285.17:38:49.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.17:38:49.01#ibcon#[27=AT07-04\r\n] 2006.285.17:38:49.01#ibcon#*before write, iclass 5, count 2 2006.285.17:38:49.01#ibcon#enter sib2, iclass 5, count 2 2006.285.17:38:49.01#ibcon#flushed, iclass 5, count 2 2006.285.17:38:49.01#ibcon#about to write, iclass 5, count 2 2006.285.17:38:49.01#ibcon#wrote, iclass 5, count 2 2006.285.17:38:49.01#ibcon#about to read 3, iclass 5, count 2 2006.285.17:38:49.04#ibcon#read 3, iclass 5, count 2 2006.285.17:38:49.04#ibcon#about to read 4, iclass 5, count 2 2006.285.17:38:49.04#ibcon#read 4, iclass 5, count 2 2006.285.17:38:49.04#ibcon#about to read 5, iclass 5, count 2 2006.285.17:38:49.04#ibcon#read 5, iclass 5, count 2 2006.285.17:38:49.04#ibcon#about to read 6, iclass 5, count 2 2006.285.17:38:49.04#ibcon#read 6, iclass 5, count 2 2006.285.17:38:49.04#ibcon#end of sib2, iclass 5, count 2 2006.285.17:38:49.04#ibcon#*after write, iclass 5, count 2 2006.285.17:38:49.04#ibcon#*before return 0, iclass 5, count 2 2006.285.17:38:49.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:38:49.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:38:49.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.17:38:49.04#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:49.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:38:49.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:38:49.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:38:49.16#ibcon#enter wrdev, iclass 5, count 0 2006.285.17:38:49.16#ibcon#first serial, iclass 5, count 0 2006.285.17:38:49.16#ibcon#enter sib2, iclass 5, count 0 2006.285.17:38:49.16#ibcon#flushed, iclass 5, count 0 2006.285.17:38:49.16#ibcon#about to write, iclass 5, count 0 2006.285.17:38:49.16#ibcon#wrote, iclass 5, count 0 2006.285.17:38:49.16#ibcon#about to read 3, iclass 5, count 0 2006.285.17:38:49.18#ibcon#read 3, iclass 5, count 0 2006.285.17:38:49.18#ibcon#about to read 4, iclass 5, count 0 2006.285.17:38:49.18#ibcon#read 4, iclass 5, count 0 2006.285.17:38:49.18#ibcon#about to read 5, iclass 5, count 0 2006.285.17:38:49.18#ibcon#read 5, iclass 5, count 0 2006.285.17:38:49.18#ibcon#about to read 6, iclass 5, count 0 2006.285.17:38:49.18#ibcon#read 6, iclass 5, count 0 2006.285.17:38:49.18#ibcon#end of sib2, iclass 5, count 0 2006.285.17:38:49.18#ibcon#*mode == 0, iclass 5, count 0 2006.285.17:38:49.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.17:38:49.18#ibcon#[27=USB\r\n] 2006.285.17:38:49.18#ibcon#*before write, iclass 5, count 0 2006.285.17:38:49.18#ibcon#enter sib2, iclass 5, count 0 2006.285.17:38:49.18#ibcon#flushed, iclass 5, count 0 2006.285.17:38:49.26#ibcon#about to write, iclass 5, count 0 2006.285.17:38:49.26#ibcon#wrote, iclass 5, count 0 2006.285.17:38:49.26#ibcon#about to read 3, iclass 5, count 0 2006.285.17:38:49.29#ibcon#read 3, iclass 5, count 0 2006.285.17:38:49.29#ibcon#about to read 4, iclass 5, count 0 2006.285.17:38:49.29#ibcon#read 4, iclass 5, count 0 2006.285.17:38:49.29#ibcon#about to read 5, iclass 5, count 0 2006.285.17:38:49.29#ibcon#read 5, iclass 5, count 0 2006.285.17:38:49.29#ibcon#about to read 6, iclass 5, count 0 2006.285.17:38:49.29#ibcon#read 6, iclass 5, count 0 2006.285.17:38:49.29#ibcon#end of sib2, iclass 5, count 0 2006.285.17:38:49.29#ibcon#*after write, iclass 5, count 0 2006.285.17:38:49.29#ibcon#*before return 0, iclass 5, count 0 2006.285.17:38:49.29#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:38:49.29#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:38:49.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.17:38:49.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.17:38:49.29$vck44/vblo=8,744.99 2006.285.17:38:49.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.17:38:49.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.17:38:49.29#ibcon#ireg 17 cls_cnt 0 2006.285.17:38:49.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:38:49.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:38:49.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:38:49.29#ibcon#enter wrdev, iclass 7, count 0 2006.285.17:38:49.29#ibcon#first serial, iclass 7, count 0 2006.285.17:38:49.29#ibcon#enter sib2, iclass 7, count 0 2006.285.17:38:49.29#ibcon#flushed, iclass 7, count 0 2006.285.17:38:49.29#ibcon#about to write, iclass 7, count 0 2006.285.17:38:49.29#ibcon#wrote, iclass 7, count 0 2006.285.17:38:49.29#ibcon#about to read 3, iclass 7, count 0 2006.285.17:38:49.31#ibcon#read 3, iclass 7, count 0 2006.285.17:38:49.31#ibcon#about to read 4, iclass 7, count 0 2006.285.17:38:49.31#ibcon#read 4, iclass 7, count 0 2006.285.17:38:49.31#ibcon#about to read 5, iclass 7, count 0 2006.285.17:38:49.31#ibcon#read 5, iclass 7, count 0 2006.285.17:38:49.31#ibcon#about to read 6, iclass 7, count 0 2006.285.17:38:49.31#ibcon#read 6, iclass 7, count 0 2006.285.17:38:49.31#ibcon#end of sib2, iclass 7, count 0 2006.285.17:38:49.31#ibcon#*mode == 0, iclass 7, count 0 2006.285.17:38:49.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.17:38:49.31#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.17:38:49.31#ibcon#*before write, iclass 7, count 0 2006.285.17:38:49.31#ibcon#enter sib2, iclass 7, count 0 2006.285.17:38:49.31#ibcon#flushed, iclass 7, count 0 2006.285.17:38:49.31#ibcon#about to write, iclass 7, count 0 2006.285.17:38:49.31#ibcon#wrote, iclass 7, count 0 2006.285.17:38:49.31#ibcon#about to read 3, iclass 7, count 0 2006.285.17:38:49.35#ibcon#read 3, iclass 7, count 0 2006.285.17:38:49.35#ibcon#about to read 4, iclass 7, count 0 2006.285.17:38:49.35#ibcon#read 4, iclass 7, count 0 2006.285.17:38:49.35#ibcon#about to read 5, iclass 7, count 0 2006.285.17:38:49.35#ibcon#read 5, iclass 7, count 0 2006.285.17:38:49.35#ibcon#about to read 6, iclass 7, count 0 2006.285.17:38:49.35#ibcon#read 6, iclass 7, count 0 2006.285.17:38:49.35#ibcon#end of sib2, iclass 7, count 0 2006.285.17:38:49.35#ibcon#*after write, iclass 7, count 0 2006.285.17:38:49.35#ibcon#*before return 0, iclass 7, count 0 2006.285.17:38:49.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:38:49.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:38:49.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.17:38:49.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.17:38:49.35$vck44/vb=8,4 2006.285.17:38:49.35#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.17:38:49.35#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.17:38:49.35#ibcon#ireg 11 cls_cnt 2 2006.285.17:38:49.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:38:49.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:38:49.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:38:49.41#ibcon#enter wrdev, iclass 11, count 2 2006.285.17:38:49.41#ibcon#first serial, iclass 11, count 2 2006.285.17:38:49.41#ibcon#enter sib2, iclass 11, count 2 2006.285.17:38:49.41#ibcon#flushed, iclass 11, count 2 2006.285.17:38:49.41#ibcon#about to write, iclass 11, count 2 2006.285.17:38:49.41#ibcon#wrote, iclass 11, count 2 2006.285.17:38:49.41#ibcon#about to read 3, iclass 11, count 2 2006.285.17:38:49.43#ibcon#read 3, iclass 11, count 2 2006.285.17:38:49.43#ibcon#about to read 4, iclass 11, count 2 2006.285.17:38:49.43#ibcon#read 4, iclass 11, count 2 2006.285.17:38:49.43#ibcon#about to read 5, iclass 11, count 2 2006.285.17:38:49.43#ibcon#read 5, iclass 11, count 2 2006.285.17:38:49.43#ibcon#about to read 6, iclass 11, count 2 2006.285.17:38:49.43#ibcon#read 6, iclass 11, count 2 2006.285.17:38:49.43#ibcon#end of sib2, iclass 11, count 2 2006.285.17:38:49.43#ibcon#*mode == 0, iclass 11, count 2 2006.285.17:38:49.43#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.17:38:49.43#ibcon#[27=AT08-04\r\n] 2006.285.17:38:49.43#ibcon#*before write, iclass 11, count 2 2006.285.17:38:49.43#ibcon#enter sib2, iclass 11, count 2 2006.285.17:38:49.43#ibcon#flushed, iclass 11, count 2 2006.285.17:38:49.43#ibcon#about to write, iclass 11, count 2 2006.285.17:38:49.43#ibcon#wrote, iclass 11, count 2 2006.285.17:38:49.43#ibcon#about to read 3, iclass 11, count 2 2006.285.17:38:49.46#ibcon#read 3, iclass 11, count 2 2006.285.17:38:49.46#ibcon#about to read 4, iclass 11, count 2 2006.285.17:38:49.46#ibcon#read 4, iclass 11, count 2 2006.285.17:38:49.46#ibcon#about to read 5, iclass 11, count 2 2006.285.17:38:49.46#ibcon#read 5, iclass 11, count 2 2006.285.17:38:49.46#ibcon#about to read 6, iclass 11, count 2 2006.285.17:38:49.46#ibcon#read 6, iclass 11, count 2 2006.285.17:38:49.46#ibcon#end of sib2, iclass 11, count 2 2006.285.17:38:49.46#ibcon#*after write, iclass 11, count 2 2006.285.17:38:49.46#ibcon#*before return 0, iclass 11, count 2 2006.285.17:38:49.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:38:49.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:38:49.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.17:38:49.46#ibcon#ireg 7 cls_cnt 0 2006.285.17:38:49.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:38:49.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:38:49.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:38:49.58#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:38:49.58#ibcon#first serial, iclass 11, count 0 2006.285.17:38:49.58#ibcon#enter sib2, iclass 11, count 0 2006.285.17:38:49.58#ibcon#flushed, iclass 11, count 0 2006.285.17:38:49.58#ibcon#about to write, iclass 11, count 0 2006.285.17:38:49.58#ibcon#wrote, iclass 11, count 0 2006.285.17:38:49.58#ibcon#about to read 3, iclass 11, count 0 2006.285.17:38:49.60#ibcon#read 3, iclass 11, count 0 2006.285.17:38:49.60#ibcon#about to read 4, iclass 11, count 0 2006.285.17:38:49.60#ibcon#read 4, iclass 11, count 0 2006.285.17:38:49.60#ibcon#about to read 5, iclass 11, count 0 2006.285.17:38:49.60#ibcon#read 5, iclass 11, count 0 2006.285.17:38:49.60#ibcon#about to read 6, iclass 11, count 0 2006.285.17:38:49.60#ibcon#read 6, iclass 11, count 0 2006.285.17:38:49.60#ibcon#end of sib2, iclass 11, count 0 2006.285.17:38:49.60#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:38:49.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:38:49.60#ibcon#[27=USB\r\n] 2006.285.17:38:49.60#ibcon#*before write, iclass 11, count 0 2006.285.17:38:49.60#ibcon#enter sib2, iclass 11, count 0 2006.285.17:38:49.60#ibcon#flushed, iclass 11, count 0 2006.285.17:38:49.60#ibcon#about to write, iclass 11, count 0 2006.285.17:38:49.60#ibcon#wrote, iclass 11, count 0 2006.285.17:38:49.60#ibcon#about to read 3, iclass 11, count 0 2006.285.17:38:49.63#ibcon#read 3, iclass 11, count 0 2006.285.17:38:49.63#ibcon#about to read 4, iclass 11, count 0 2006.285.17:38:49.63#ibcon#read 4, iclass 11, count 0 2006.285.17:38:49.63#ibcon#about to read 5, iclass 11, count 0 2006.285.17:38:49.63#ibcon#read 5, iclass 11, count 0 2006.285.17:38:49.63#ibcon#about to read 6, iclass 11, count 0 2006.285.17:38:49.63#ibcon#read 6, iclass 11, count 0 2006.285.17:38:49.63#ibcon#end of sib2, iclass 11, count 0 2006.285.17:38:49.63#ibcon#*after write, iclass 11, count 0 2006.285.17:38:49.63#ibcon#*before return 0, iclass 11, count 0 2006.285.17:38:49.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:38:49.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:38:49.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:38:49.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:38:49.63$vck44/vabw=wide 2006.285.17:38:49.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.17:38:49.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.17:38:49.63#ibcon#ireg 8 cls_cnt 0 2006.285.17:38:49.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:38:49.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:38:49.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:38:49.63#ibcon#enter wrdev, iclass 13, count 0 2006.285.17:38:49.63#ibcon#first serial, iclass 13, count 0 2006.285.17:38:49.63#ibcon#enter sib2, iclass 13, count 0 2006.285.17:38:49.63#ibcon#flushed, iclass 13, count 0 2006.285.17:38:49.63#ibcon#about to write, iclass 13, count 0 2006.285.17:38:49.63#ibcon#wrote, iclass 13, count 0 2006.285.17:38:49.63#ibcon#about to read 3, iclass 13, count 0 2006.285.17:38:49.65#ibcon#read 3, iclass 13, count 0 2006.285.17:38:49.65#ibcon#about to read 4, iclass 13, count 0 2006.285.17:38:49.65#ibcon#read 4, iclass 13, count 0 2006.285.17:38:49.65#ibcon#about to read 5, iclass 13, count 0 2006.285.17:38:49.65#ibcon#read 5, iclass 13, count 0 2006.285.17:38:49.65#ibcon#about to read 6, iclass 13, count 0 2006.285.17:38:49.65#ibcon#read 6, iclass 13, count 0 2006.285.17:38:49.65#ibcon#end of sib2, iclass 13, count 0 2006.285.17:38:49.65#ibcon#*mode == 0, iclass 13, count 0 2006.285.17:38:49.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.17:38:49.65#ibcon#[25=BW32\r\n] 2006.285.17:38:49.65#ibcon#*before write, iclass 13, count 0 2006.285.17:38:49.65#ibcon#enter sib2, iclass 13, count 0 2006.285.17:38:49.65#ibcon#flushed, iclass 13, count 0 2006.285.17:38:49.65#ibcon#about to write, iclass 13, count 0 2006.285.17:38:49.65#ibcon#wrote, iclass 13, count 0 2006.285.17:38:49.65#ibcon#about to read 3, iclass 13, count 0 2006.285.17:38:49.68#ibcon#read 3, iclass 13, count 0 2006.285.17:38:49.68#ibcon#about to read 4, iclass 13, count 0 2006.285.17:38:49.68#ibcon#read 4, iclass 13, count 0 2006.285.17:38:49.68#ibcon#about to read 5, iclass 13, count 0 2006.285.17:38:49.68#ibcon#read 5, iclass 13, count 0 2006.285.17:38:49.68#ibcon#about to read 6, iclass 13, count 0 2006.285.17:38:49.68#ibcon#read 6, iclass 13, count 0 2006.285.17:38:49.68#ibcon#end of sib2, iclass 13, count 0 2006.285.17:38:49.68#ibcon#*after write, iclass 13, count 0 2006.285.17:38:49.68#ibcon#*before return 0, iclass 13, count 0 2006.285.17:38:49.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:38:49.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:38:49.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.17:38:49.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.17:38:49.68$vck44/vbbw=wide 2006.285.17:38:49.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.17:38:49.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.17:38:49.68#ibcon#ireg 8 cls_cnt 0 2006.285.17:38:49.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:38:49.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:38:49.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:38:49.75#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:38:49.75#ibcon#first serial, iclass 15, count 0 2006.285.17:38:49.75#ibcon#enter sib2, iclass 15, count 0 2006.285.17:38:49.75#ibcon#flushed, iclass 15, count 0 2006.285.17:38:49.75#ibcon#about to write, iclass 15, count 0 2006.285.17:38:49.75#ibcon#wrote, iclass 15, count 0 2006.285.17:38:49.75#ibcon#about to read 3, iclass 15, count 0 2006.285.17:38:49.77#ibcon#read 3, iclass 15, count 0 2006.285.17:38:49.77#ibcon#about to read 4, iclass 15, count 0 2006.285.17:38:49.77#ibcon#read 4, iclass 15, count 0 2006.285.17:38:49.77#ibcon#about to read 5, iclass 15, count 0 2006.285.17:38:49.77#ibcon#read 5, iclass 15, count 0 2006.285.17:38:49.77#ibcon#about to read 6, iclass 15, count 0 2006.285.17:38:49.77#ibcon#read 6, iclass 15, count 0 2006.285.17:38:49.77#ibcon#end of sib2, iclass 15, count 0 2006.285.17:38:49.77#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:38:49.77#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:38:49.77#ibcon#[27=BW32\r\n] 2006.285.17:38:49.77#ibcon#*before write, iclass 15, count 0 2006.285.17:38:49.77#ibcon#enter sib2, iclass 15, count 0 2006.285.17:38:49.77#ibcon#flushed, iclass 15, count 0 2006.285.17:38:49.77#ibcon#about to write, iclass 15, count 0 2006.285.17:38:49.77#ibcon#wrote, iclass 15, count 0 2006.285.17:38:49.77#ibcon#about to read 3, iclass 15, count 0 2006.285.17:38:49.80#ibcon#read 3, iclass 15, count 0 2006.285.17:38:49.80#ibcon#about to read 4, iclass 15, count 0 2006.285.17:38:49.80#ibcon#read 4, iclass 15, count 0 2006.285.17:38:49.80#ibcon#about to read 5, iclass 15, count 0 2006.285.17:38:49.80#ibcon#read 5, iclass 15, count 0 2006.285.17:38:49.80#ibcon#about to read 6, iclass 15, count 0 2006.285.17:38:49.80#ibcon#read 6, iclass 15, count 0 2006.285.17:38:49.80#ibcon#end of sib2, iclass 15, count 0 2006.285.17:38:49.80#ibcon#*after write, iclass 15, count 0 2006.285.17:38:49.80#ibcon#*before return 0, iclass 15, count 0 2006.285.17:38:49.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:38:49.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:38:49.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:38:49.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:38:49.80$setupk4/ifdk4 2006.285.17:38:49.80$ifdk4/lo= 2006.285.17:38:49.80$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.17:38:49.80$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.17:38:49.80$ifdk4/patch= 2006.285.17:38:49.80$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.17:38:49.80$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.17:38:49.80$setupk4/!*+20s 2006.285.17:38:58.81#abcon#<5=/14 0.3 1.2 16.58 991014.7\r\n> 2006.285.17:38:58.83#abcon#{5=INTERFACE CLEAR} 2006.285.17:38:58.89#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:39:03.40$setupk4/"tpicd 2006.285.17:39:03.40$setupk4/echo=off 2006.285.17:39:03.40$setupk4/xlog=off 2006.285.17:39:03.40:!2006.285.17:45:31 2006.285.17:39:55.14#trakl#Source acquired 2006.285.17:39:55.14#flagr#flagr/antenna,acquired 2006.285.17:45:31.02:preob 2006.285.17:45:32.14/onsource/TRACKING 2006.285.17:45:32.14:!2006.285.17:45:41 2006.285.17:45:41.02:"tape 2006.285.17:45:41.02:"st=record 2006.285.17:45:41.02:data_valid=on 2006.285.17:45:41.02:midob 2006.285.17:45:42.14/onsource/TRACKING 2006.285.17:45:42.14/wx/16.40,1014.5,99 2006.285.17:45:42.27/cable/+6.5061E-03 2006.285.17:45:43.36/va/01,07,usb,yes,35,38 2006.285.17:45:43.36/va/02,06,usb,yes,36,36 2006.285.17:45:43.36/va/03,07,usb,yes,35,37 2006.285.17:45:43.36/va/04,06,usb,yes,37,38 2006.285.17:45:43.36/va/05,03,usb,yes,36,37 2006.285.17:45:43.36/va/06,04,usb,yes,33,32 2006.285.17:45:43.36/va/07,04,usb,yes,33,34 2006.285.17:45:43.36/va/08,03,usb,yes,34,41 2006.285.17:45:43.59/valo/01,524.99,yes,locked 2006.285.17:45:43.59/valo/02,534.99,yes,locked 2006.285.17:45:43.59/valo/03,564.99,yes,locked 2006.285.17:45:43.59/valo/04,624.99,yes,locked 2006.285.17:45:43.59/valo/05,734.99,yes,locked 2006.285.17:45:43.59/valo/06,814.99,yes,locked 2006.285.17:45:43.59/valo/07,864.99,yes,locked 2006.285.17:45:43.59/valo/08,884.99,yes,locked 2006.285.17:45:44.68/vb/01,04,usb,yes,32,30 2006.285.17:45:44.68/vb/02,05,usb,yes,30,30 2006.285.17:45:44.68/vb/03,04,usb,yes,31,35 2006.285.17:45:44.68/vb/04,05,usb,yes,32,31 2006.285.17:45:44.68/vb/05,04,usb,yes,28,31 2006.285.17:45:44.68/vb/06,03,usb,yes,40,36 2006.285.17:45:44.68/vb/07,04,usb,yes,32,32 2006.285.17:45:44.68/vb/08,04,usb,yes,29,33 2006.285.17:45:44.91/vblo/01,629.99,yes,locked 2006.285.17:45:44.91/vblo/02,634.99,yes,locked 2006.285.17:45:44.91/vblo/03,649.99,yes,locked 2006.285.17:45:44.91/vblo/04,679.99,yes,locked 2006.285.17:45:44.91/vblo/05,709.99,yes,locked 2006.285.17:45:44.91/vblo/06,719.99,yes,locked 2006.285.17:45:44.91/vblo/07,734.99,yes,locked 2006.285.17:45:44.91/vblo/08,744.99,yes,locked 2006.285.17:45:45.06/vabw/8 2006.285.17:45:45.21/vbbw/8 2006.285.17:45:45.35/xfe/off,on,12.2 2006.285.17:45:45.72/ifatt/23,28,28,28 2006.285.17:45:46.08/fmout-gps/S +2.81E-07 2006.285.17:45:46.09:!2006.285.17:46:21 2006.285.17:46:21.02:data_valid=off 2006.285.17:46:21.02:"et 2006.285.17:46:21.02:!+3s 2006.285.17:46:24.04:"tape 2006.285.17:46:24.05:postob 2006.285.17:46:24.15/cable/+6.5043E-03 2006.285.17:46:24.15/wx/16.39,1014.5,99 2006.285.17:46:24.20/fmout-gps/S +2.82E-07 2006.285.17:46:24.21:scan_name=285-1747,jd0610,220 2006.285.17:46:24.21:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.285.17:46:25.15#flagr#flagr/antenna,new-source 2006.285.17:46:25.15:checkk5 2006.285.17:46:25.59/chk_autoobs//k5ts1/ autoobs is running! 2006.285.17:46:26.25/chk_autoobs//k5ts2/ autoobs is running! 2006.285.17:46:26.70/chk_autoobs//k5ts3/ autoobs is running! 2006.285.17:46:27.11/chk_autoobs//k5ts4/ autoobs is running! 2006.285.17:46:27.44/chk_obsdata//k5ts1/T2851745??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.17:46:27.93/chk_obsdata//k5ts2/T2851745??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.17:46:28.32/chk_obsdata//k5ts3/T2851745??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.17:46:28.86/chk_obsdata//k5ts4/T2851745??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.17:46:29.95/k5log//k5ts1_log_newline 2006.285.17:46:30.76/k5log//k5ts2_log_newline 2006.285.17:46:31.61/k5log//k5ts3_log_newline 2006.285.17:46:32.49/k5log//k5ts4_log_newline 2006.285.17:46:32.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.17:46:32.51:setupk4=1 2006.285.17:46:32.51$setupk4/echo=on 2006.285.17:46:32.51$setupk4/pcalon 2006.285.17:46:32.51$pcalon/"no phase cal control is implemented here 2006.285.17:46:32.51$setupk4/"tpicd=stop 2006.285.17:46:32.51$setupk4/"rec=synch_on 2006.285.17:46:32.51$setupk4/"rec_mode=128 2006.285.17:46:32.51$setupk4/!* 2006.285.17:46:32.51$setupk4/recpk4 2006.285.17:46:32.51$recpk4/recpatch= 2006.285.17:46:32.51$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.17:46:32.51$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.17:46:32.51$setupk4/vck44 2006.285.17:46:32.51$vck44/valo=1,524.99 2006.285.17:46:32.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.17:46:32.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.17:46:32.51#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:32.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:46:32.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:46:32.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:46:32.51#ibcon#enter wrdev, iclass 20, count 0 2006.285.17:46:32.51#ibcon#first serial, iclass 20, count 0 2006.285.17:46:32.51#ibcon#enter sib2, iclass 20, count 0 2006.285.17:46:32.51#ibcon#flushed, iclass 20, count 0 2006.285.17:46:32.51#ibcon#about to write, iclass 20, count 0 2006.285.17:46:32.51#ibcon#wrote, iclass 20, count 0 2006.285.17:46:32.51#ibcon#about to read 3, iclass 20, count 0 2006.285.17:46:32.52#ibcon#read 3, iclass 20, count 0 2006.285.17:46:32.52#ibcon#about to read 4, iclass 20, count 0 2006.285.17:46:32.52#ibcon#read 4, iclass 20, count 0 2006.285.17:46:32.52#ibcon#about to read 5, iclass 20, count 0 2006.285.17:46:32.52#ibcon#read 5, iclass 20, count 0 2006.285.17:46:32.52#ibcon#about to read 6, iclass 20, count 0 2006.285.17:46:32.52#ibcon#read 6, iclass 20, count 0 2006.285.17:46:32.52#ibcon#end of sib2, iclass 20, count 0 2006.285.17:46:32.52#ibcon#*mode == 0, iclass 20, count 0 2006.285.17:46:32.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.17:46:32.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.17:46:32.52#ibcon#*before write, iclass 20, count 0 2006.285.17:46:32.52#ibcon#enter sib2, iclass 20, count 0 2006.285.17:46:32.52#ibcon#flushed, iclass 20, count 0 2006.285.17:46:32.52#ibcon#about to write, iclass 20, count 0 2006.285.17:46:32.53#ibcon#wrote, iclass 20, count 0 2006.285.17:46:32.53#ibcon#about to read 3, iclass 20, count 0 2006.285.17:46:32.57#ibcon#read 3, iclass 20, count 0 2006.285.17:46:32.57#ibcon#about to read 4, iclass 20, count 0 2006.285.17:46:32.57#ibcon#read 4, iclass 20, count 0 2006.285.17:46:32.57#ibcon#about to read 5, iclass 20, count 0 2006.285.17:46:32.57#ibcon#read 5, iclass 20, count 0 2006.285.17:46:32.57#ibcon#about to read 6, iclass 20, count 0 2006.285.17:46:32.57#ibcon#read 6, iclass 20, count 0 2006.285.17:46:32.57#ibcon#end of sib2, iclass 20, count 0 2006.285.17:46:32.57#ibcon#*after write, iclass 20, count 0 2006.285.17:46:32.57#ibcon#*before return 0, iclass 20, count 0 2006.285.17:46:32.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:46:32.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:46:32.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.17:46:32.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.17:46:32.58$vck44/va=1,7 2006.285.17:46:32.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.17:46:32.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.17:46:32.58#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:32.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:46:32.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:46:32.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:46:32.58#ibcon#enter wrdev, iclass 22, count 2 2006.285.17:46:32.58#ibcon#first serial, iclass 22, count 2 2006.285.17:46:32.58#ibcon#enter sib2, iclass 22, count 2 2006.285.17:46:32.58#ibcon#flushed, iclass 22, count 2 2006.285.17:46:32.58#ibcon#about to write, iclass 22, count 2 2006.285.17:46:32.58#ibcon#wrote, iclass 22, count 2 2006.285.17:46:32.58#ibcon#about to read 3, iclass 22, count 2 2006.285.17:46:32.59#ibcon#read 3, iclass 22, count 2 2006.285.17:46:32.59#ibcon#about to read 4, iclass 22, count 2 2006.285.17:46:32.59#ibcon#read 4, iclass 22, count 2 2006.285.17:46:32.59#ibcon#about to read 5, iclass 22, count 2 2006.285.17:46:32.59#ibcon#read 5, iclass 22, count 2 2006.285.17:46:32.59#ibcon#about to read 6, iclass 22, count 2 2006.285.17:46:32.59#ibcon#read 6, iclass 22, count 2 2006.285.17:46:32.59#ibcon#end of sib2, iclass 22, count 2 2006.285.17:46:32.59#ibcon#*mode == 0, iclass 22, count 2 2006.285.17:46:32.59#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.17:46:32.59#ibcon#[25=AT01-07\r\n] 2006.285.17:46:32.59#ibcon#*before write, iclass 22, count 2 2006.285.17:46:32.59#ibcon#enter sib2, iclass 22, count 2 2006.285.17:46:32.60#ibcon#flushed, iclass 22, count 2 2006.285.17:46:32.60#ibcon#about to write, iclass 22, count 2 2006.285.17:46:32.60#ibcon#wrote, iclass 22, count 2 2006.285.17:46:32.60#ibcon#about to read 3, iclass 22, count 2 2006.285.17:46:32.62#ibcon#read 3, iclass 22, count 2 2006.285.17:46:32.62#ibcon#about to read 4, iclass 22, count 2 2006.285.17:46:32.62#ibcon#read 4, iclass 22, count 2 2006.285.17:46:32.62#ibcon#about to read 5, iclass 22, count 2 2006.285.17:46:32.62#ibcon#read 5, iclass 22, count 2 2006.285.17:46:32.62#ibcon#about to read 6, iclass 22, count 2 2006.285.17:46:32.62#ibcon#read 6, iclass 22, count 2 2006.285.17:46:32.62#ibcon#end of sib2, iclass 22, count 2 2006.285.17:46:32.62#ibcon#*after write, iclass 22, count 2 2006.285.17:46:32.62#ibcon#*before return 0, iclass 22, count 2 2006.285.17:46:32.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:46:32.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:46:32.62#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.17:46:32.62#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:32.63#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:46:32.73#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:46:32.73#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:46:32.73#ibcon#enter wrdev, iclass 22, count 0 2006.285.17:46:32.73#ibcon#first serial, iclass 22, count 0 2006.285.17:46:32.73#ibcon#enter sib2, iclass 22, count 0 2006.285.17:46:32.73#ibcon#flushed, iclass 22, count 0 2006.285.17:46:32.73#ibcon#about to write, iclass 22, count 0 2006.285.17:46:32.73#ibcon#wrote, iclass 22, count 0 2006.285.17:46:32.73#ibcon#about to read 3, iclass 22, count 0 2006.285.17:46:32.75#ibcon#read 3, iclass 22, count 0 2006.285.17:46:33.17#ibcon#about to read 4, iclass 22, count 0 2006.285.17:46:33.17#ibcon#read 4, iclass 22, count 0 2006.285.17:46:33.17#ibcon#about to read 5, iclass 22, count 0 2006.285.17:46:33.17#ibcon#read 5, iclass 22, count 0 2006.285.17:46:33.17#ibcon#about to read 6, iclass 22, count 0 2006.285.17:46:33.17#ibcon#read 6, iclass 22, count 0 2006.285.17:46:33.17#ibcon#end of sib2, iclass 22, count 0 2006.285.17:46:33.17#ibcon#*mode == 0, iclass 22, count 0 2006.285.17:46:33.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.17:46:33.17#ibcon#[25=USB\r\n] 2006.285.17:46:33.17#ibcon#*before write, iclass 22, count 0 2006.285.17:46:33.17#ibcon#enter sib2, iclass 22, count 0 2006.285.17:46:33.17#ibcon#flushed, iclass 22, count 0 2006.285.17:46:33.17#ibcon#about to write, iclass 22, count 0 2006.285.17:46:33.17#ibcon#wrote, iclass 22, count 0 2006.285.17:46:33.17#ibcon#about to read 3, iclass 22, count 0 2006.285.17:46:33.20#ibcon#read 3, iclass 22, count 0 2006.285.17:46:33.20#ibcon#about to read 4, iclass 22, count 0 2006.285.17:46:33.20#ibcon#read 4, iclass 22, count 0 2006.285.17:46:33.20#ibcon#about to read 5, iclass 22, count 0 2006.285.17:46:33.20#ibcon#read 5, iclass 22, count 0 2006.285.17:46:33.20#ibcon#about to read 6, iclass 22, count 0 2006.285.17:46:33.20#ibcon#read 6, iclass 22, count 0 2006.285.17:46:33.20#ibcon#end of sib2, iclass 22, count 0 2006.285.17:46:33.20#ibcon#*after write, iclass 22, count 0 2006.285.17:46:33.20#ibcon#*before return 0, iclass 22, count 0 2006.285.17:46:33.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:46:33.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:46:33.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.17:46:33.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.17:46:33.21$vck44/valo=2,534.99 2006.285.17:46:33.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.17:46:33.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.17:46:33.21#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:33.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:46:33.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:46:33.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:46:33.21#ibcon#enter wrdev, iclass 24, count 0 2006.285.17:46:33.21#ibcon#first serial, iclass 24, count 0 2006.285.17:46:33.21#ibcon#enter sib2, iclass 24, count 0 2006.285.17:46:33.21#ibcon#flushed, iclass 24, count 0 2006.285.17:46:33.21#ibcon#about to write, iclass 24, count 0 2006.285.17:46:33.21#ibcon#wrote, iclass 24, count 0 2006.285.17:46:33.21#ibcon#about to read 3, iclass 24, count 0 2006.285.17:46:33.22#ibcon#read 3, iclass 24, count 0 2006.285.17:46:33.22#ibcon#about to read 4, iclass 24, count 0 2006.285.17:46:33.22#ibcon#read 4, iclass 24, count 0 2006.285.17:46:33.22#ibcon#about to read 5, iclass 24, count 0 2006.285.17:46:33.22#ibcon#read 5, iclass 24, count 0 2006.285.17:46:33.22#ibcon#about to read 6, iclass 24, count 0 2006.285.17:46:33.22#ibcon#read 6, iclass 24, count 0 2006.285.17:46:33.22#ibcon#end of sib2, iclass 24, count 0 2006.285.17:46:33.22#ibcon#*mode == 0, iclass 24, count 0 2006.285.17:46:33.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.17:46:33.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.17:46:33.22#ibcon#*before write, iclass 24, count 0 2006.285.17:46:33.22#ibcon#enter sib2, iclass 24, count 0 2006.285.17:46:33.22#ibcon#flushed, iclass 24, count 0 2006.285.17:46:33.22#ibcon#about to write, iclass 24, count 0 2006.285.17:46:33.23#ibcon#wrote, iclass 24, count 0 2006.285.17:46:33.23#ibcon#about to read 3, iclass 24, count 0 2006.285.17:46:33.26#ibcon#read 3, iclass 24, count 0 2006.285.17:46:33.26#ibcon#about to read 4, iclass 24, count 0 2006.285.17:46:33.26#ibcon#read 4, iclass 24, count 0 2006.285.17:46:33.26#ibcon#about to read 5, iclass 24, count 0 2006.285.17:46:33.26#ibcon#read 5, iclass 24, count 0 2006.285.17:46:33.26#ibcon#about to read 6, iclass 24, count 0 2006.285.17:46:33.26#ibcon#read 6, iclass 24, count 0 2006.285.17:46:33.26#ibcon#end of sib2, iclass 24, count 0 2006.285.17:46:33.26#ibcon#*after write, iclass 24, count 0 2006.285.17:46:33.26#ibcon#*before return 0, iclass 24, count 0 2006.285.17:46:33.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:46:33.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:46:33.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.17:46:33.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.17:46:33.27$vck44/va=2,6 2006.285.17:46:33.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.17:46:33.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.17:46:33.27#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:33.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:46:33.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:46:33.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:46:33.31#ibcon#enter wrdev, iclass 26, count 2 2006.285.17:46:33.31#ibcon#first serial, iclass 26, count 2 2006.285.17:46:33.31#ibcon#enter sib2, iclass 26, count 2 2006.285.17:46:33.31#ibcon#flushed, iclass 26, count 2 2006.285.17:46:33.31#ibcon#about to write, iclass 26, count 2 2006.285.17:46:33.31#ibcon#wrote, iclass 26, count 2 2006.285.17:46:33.31#ibcon#about to read 3, iclass 26, count 2 2006.285.17:46:33.33#ibcon#read 3, iclass 26, count 2 2006.285.17:46:33.33#ibcon#about to read 4, iclass 26, count 2 2006.285.17:46:33.33#ibcon#read 4, iclass 26, count 2 2006.285.17:46:33.33#ibcon#about to read 5, iclass 26, count 2 2006.285.17:46:33.33#ibcon#read 5, iclass 26, count 2 2006.285.17:46:33.33#ibcon#about to read 6, iclass 26, count 2 2006.285.17:46:33.33#ibcon#read 6, iclass 26, count 2 2006.285.17:46:33.33#ibcon#end of sib2, iclass 26, count 2 2006.285.17:46:33.33#ibcon#*mode == 0, iclass 26, count 2 2006.285.17:46:33.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.17:46:33.33#ibcon#[25=AT02-06\r\n] 2006.285.17:46:33.33#ibcon#*before write, iclass 26, count 2 2006.285.17:46:33.33#ibcon#enter sib2, iclass 26, count 2 2006.285.17:46:33.33#ibcon#flushed, iclass 26, count 2 2006.285.17:46:33.33#ibcon#about to write, iclass 26, count 2 2006.285.17:46:33.34#ibcon#wrote, iclass 26, count 2 2006.285.17:46:33.34#ibcon#about to read 3, iclass 26, count 2 2006.285.17:46:33.36#ibcon#read 3, iclass 26, count 2 2006.285.17:46:33.36#ibcon#about to read 4, iclass 26, count 2 2006.285.17:46:33.36#ibcon#read 4, iclass 26, count 2 2006.285.17:46:33.36#ibcon#about to read 5, iclass 26, count 2 2006.285.17:46:33.36#ibcon#read 5, iclass 26, count 2 2006.285.17:46:33.36#ibcon#about to read 6, iclass 26, count 2 2006.285.17:46:33.36#ibcon#read 6, iclass 26, count 2 2006.285.17:46:33.36#ibcon#end of sib2, iclass 26, count 2 2006.285.17:46:33.36#ibcon#*after write, iclass 26, count 2 2006.285.17:46:33.36#ibcon#*before return 0, iclass 26, count 2 2006.285.17:46:33.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:46:33.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:46:33.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.17:46:33.36#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:33.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:46:33.47#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:46:33.47#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:46:33.47#ibcon#enter wrdev, iclass 26, count 0 2006.285.17:46:33.47#ibcon#first serial, iclass 26, count 0 2006.285.17:46:33.47#ibcon#enter sib2, iclass 26, count 0 2006.285.17:46:33.47#ibcon#flushed, iclass 26, count 0 2006.285.17:46:33.47#ibcon#about to write, iclass 26, count 0 2006.285.17:46:33.47#ibcon#wrote, iclass 26, count 0 2006.285.17:46:33.47#ibcon#about to read 3, iclass 26, count 0 2006.285.17:46:33.49#ibcon#read 3, iclass 26, count 0 2006.285.17:46:33.49#ibcon#about to read 4, iclass 26, count 0 2006.285.17:46:33.49#ibcon#read 4, iclass 26, count 0 2006.285.17:46:33.49#ibcon#about to read 5, iclass 26, count 0 2006.285.17:46:33.49#ibcon#read 5, iclass 26, count 0 2006.285.17:46:33.49#ibcon#about to read 6, iclass 26, count 0 2006.285.17:46:33.49#ibcon#read 6, iclass 26, count 0 2006.285.17:46:33.49#ibcon#end of sib2, iclass 26, count 0 2006.285.17:46:33.49#ibcon#*mode == 0, iclass 26, count 0 2006.285.17:46:33.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.17:46:33.49#ibcon#[25=USB\r\n] 2006.285.17:46:33.49#ibcon#*before write, iclass 26, count 0 2006.285.17:46:33.49#ibcon#enter sib2, iclass 26, count 0 2006.285.17:46:33.49#ibcon#flushed, iclass 26, count 0 2006.285.17:46:33.49#ibcon#about to write, iclass 26, count 0 2006.285.17:46:33.49#ibcon#wrote, iclass 26, count 0 2006.285.17:46:33.50#ibcon#about to read 3, iclass 26, count 0 2006.285.17:46:33.52#ibcon#read 3, iclass 26, count 0 2006.285.17:46:33.52#ibcon#about to read 4, iclass 26, count 0 2006.285.17:46:33.58#ibcon#read 4, iclass 26, count 0 2006.285.17:46:33.58#ibcon#about to read 5, iclass 26, count 0 2006.285.17:46:33.58#ibcon#read 5, iclass 26, count 0 2006.285.17:46:33.58#ibcon#about to read 6, iclass 26, count 0 2006.285.17:46:33.58#ibcon#read 6, iclass 26, count 0 2006.285.17:46:33.58#ibcon#end of sib2, iclass 26, count 0 2006.285.17:46:33.58#ibcon#*after write, iclass 26, count 0 2006.285.17:46:33.58#ibcon#*before return 0, iclass 26, count 0 2006.285.17:46:33.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:46:33.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:46:33.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.17:46:33.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.17:46:33.58$vck44/valo=3,564.99 2006.285.17:46:33.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.17:46:33.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.17:46:33.58#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:33.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:46:33.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:46:33.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:46:33.58#ibcon#enter wrdev, iclass 28, count 0 2006.285.17:46:33.58#ibcon#first serial, iclass 28, count 0 2006.285.17:46:33.58#ibcon#enter sib2, iclass 28, count 0 2006.285.17:46:33.58#ibcon#flushed, iclass 28, count 0 2006.285.17:46:33.58#ibcon#about to write, iclass 28, count 0 2006.285.17:46:33.58#ibcon#wrote, iclass 28, count 0 2006.285.17:46:33.58#ibcon#about to read 3, iclass 28, count 0 2006.285.17:46:33.59#ibcon#read 3, iclass 28, count 0 2006.285.17:46:33.59#ibcon#about to read 4, iclass 28, count 0 2006.285.17:46:33.59#ibcon#read 4, iclass 28, count 0 2006.285.17:46:33.59#ibcon#about to read 5, iclass 28, count 0 2006.285.17:46:33.59#ibcon#read 5, iclass 28, count 0 2006.285.17:46:33.59#ibcon#about to read 6, iclass 28, count 0 2006.285.17:46:33.59#ibcon#read 6, iclass 28, count 0 2006.285.17:46:33.59#ibcon#end of sib2, iclass 28, count 0 2006.285.17:46:33.59#ibcon#*mode == 0, iclass 28, count 0 2006.285.17:46:33.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.17:46:33.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.17:46:33.59#ibcon#*before write, iclass 28, count 0 2006.285.17:46:33.59#ibcon#enter sib2, iclass 28, count 0 2006.285.17:46:33.59#ibcon#flushed, iclass 28, count 0 2006.285.17:46:33.59#ibcon#about to write, iclass 28, count 0 2006.285.17:46:33.60#ibcon#wrote, iclass 28, count 0 2006.285.17:46:33.60#ibcon#about to read 3, iclass 28, count 0 2006.285.17:46:33.63#ibcon#read 3, iclass 28, count 0 2006.285.17:46:33.63#ibcon#about to read 4, iclass 28, count 0 2006.285.17:46:33.63#ibcon#read 4, iclass 28, count 0 2006.285.17:46:33.63#ibcon#about to read 5, iclass 28, count 0 2006.285.17:46:33.63#ibcon#read 5, iclass 28, count 0 2006.285.17:46:33.63#ibcon#about to read 6, iclass 28, count 0 2006.285.17:46:33.63#ibcon#read 6, iclass 28, count 0 2006.285.17:46:33.63#ibcon#end of sib2, iclass 28, count 0 2006.285.17:46:33.63#ibcon#*after write, iclass 28, count 0 2006.285.17:46:33.63#ibcon#*before return 0, iclass 28, count 0 2006.285.17:46:33.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:46:33.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:46:33.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.17:46:33.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.17:46:33.64$vck44/va=3,7 2006.285.17:46:33.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.17:46:33.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.17:46:33.64#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:33.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:46:33.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:46:33.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:46:33.69#ibcon#enter wrdev, iclass 30, count 2 2006.285.17:46:33.69#ibcon#first serial, iclass 30, count 2 2006.285.17:46:33.69#ibcon#enter sib2, iclass 30, count 2 2006.285.17:46:33.69#ibcon#flushed, iclass 30, count 2 2006.285.17:46:33.69#ibcon#about to write, iclass 30, count 2 2006.285.17:46:33.69#ibcon#wrote, iclass 30, count 2 2006.285.17:46:33.69#ibcon#about to read 3, iclass 30, count 2 2006.285.17:46:33.71#ibcon#read 3, iclass 30, count 2 2006.285.17:46:33.71#ibcon#about to read 4, iclass 30, count 2 2006.285.17:46:33.71#ibcon#read 4, iclass 30, count 2 2006.285.17:46:33.71#ibcon#about to read 5, iclass 30, count 2 2006.285.17:46:33.71#ibcon#read 5, iclass 30, count 2 2006.285.17:46:33.71#ibcon#about to read 6, iclass 30, count 2 2006.285.17:46:33.71#ibcon#read 6, iclass 30, count 2 2006.285.17:46:33.71#ibcon#end of sib2, iclass 30, count 2 2006.285.17:46:33.71#ibcon#*mode == 0, iclass 30, count 2 2006.285.17:46:33.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.17:46:33.71#ibcon#[25=AT03-07\r\n] 2006.285.17:46:33.71#ibcon#*before write, iclass 30, count 2 2006.285.17:46:33.71#ibcon#enter sib2, iclass 30, count 2 2006.285.17:46:33.71#ibcon#flushed, iclass 30, count 2 2006.285.17:46:33.72#ibcon#about to write, iclass 30, count 2 2006.285.17:46:33.72#ibcon#wrote, iclass 30, count 2 2006.285.17:46:33.72#ibcon#about to read 3, iclass 30, count 2 2006.285.17:46:33.74#ibcon#read 3, iclass 30, count 2 2006.285.17:46:33.74#ibcon#about to read 4, iclass 30, count 2 2006.285.17:46:33.74#ibcon#read 4, iclass 30, count 2 2006.285.17:46:33.74#ibcon#about to read 5, iclass 30, count 2 2006.285.17:46:33.74#ibcon#read 5, iclass 30, count 2 2006.285.17:46:33.74#ibcon#about to read 6, iclass 30, count 2 2006.285.17:46:33.74#ibcon#read 6, iclass 30, count 2 2006.285.17:46:33.74#ibcon#end of sib2, iclass 30, count 2 2006.285.17:46:33.74#ibcon#*after write, iclass 30, count 2 2006.285.17:46:33.74#ibcon#*before return 0, iclass 30, count 2 2006.285.17:46:33.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:46:33.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.17:46:33.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.17:46:33.75#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:33.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:46:33.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:46:33.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:46:33.86#ibcon#enter wrdev, iclass 30, count 0 2006.285.17:46:33.86#ibcon#first serial, iclass 30, count 0 2006.285.17:46:33.86#ibcon#enter sib2, iclass 30, count 0 2006.285.17:46:33.86#ibcon#flushed, iclass 30, count 0 2006.285.17:46:33.86#ibcon#about to write, iclass 30, count 0 2006.285.17:46:33.86#ibcon#wrote, iclass 30, count 0 2006.285.17:46:33.86#ibcon#about to read 3, iclass 30, count 0 2006.285.17:46:33.88#ibcon#read 3, iclass 30, count 0 2006.285.17:46:33.88#ibcon#about to read 4, iclass 30, count 0 2006.285.17:46:33.88#ibcon#read 4, iclass 30, count 0 2006.285.17:46:33.88#ibcon#about to read 5, iclass 30, count 0 2006.285.17:46:33.88#ibcon#read 5, iclass 30, count 0 2006.285.17:46:33.88#ibcon#about to read 6, iclass 30, count 0 2006.285.17:46:33.88#ibcon#read 6, iclass 30, count 0 2006.285.17:46:33.88#ibcon#end of sib2, iclass 30, count 0 2006.285.17:46:33.88#ibcon#*mode == 0, iclass 30, count 0 2006.285.17:46:33.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.17:46:33.88#ibcon#[25=USB\r\n] 2006.285.17:46:33.88#ibcon#*before write, iclass 30, count 0 2006.285.17:46:33.88#ibcon#enter sib2, iclass 30, count 0 2006.285.17:46:33.88#ibcon#flushed, iclass 30, count 0 2006.285.17:46:33.88#ibcon#about to write, iclass 30, count 0 2006.285.17:46:33.89#ibcon#wrote, iclass 30, count 0 2006.285.17:46:33.89#ibcon#about to read 3, iclass 30, count 0 2006.285.17:46:33.91#ibcon#read 3, iclass 30, count 0 2006.285.17:46:33.91#ibcon#about to read 4, iclass 30, count 0 2006.285.17:46:33.91#ibcon#read 4, iclass 30, count 0 2006.285.17:46:33.91#ibcon#about to read 5, iclass 30, count 0 2006.285.17:46:33.91#ibcon#read 5, iclass 30, count 0 2006.285.17:46:33.91#ibcon#about to read 6, iclass 30, count 0 2006.285.17:46:33.91#ibcon#read 6, iclass 30, count 0 2006.285.17:46:33.91#ibcon#end of sib2, iclass 30, count 0 2006.285.17:46:33.91#ibcon#*after write, iclass 30, count 0 2006.285.17:46:33.91#ibcon#*before return 0, iclass 30, count 0 2006.285.17:46:33.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:46:33.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.17:46:33.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.17:46:33.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.17:46:33.92$vck44/valo=4,624.99 2006.285.17:46:33.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.17:46:33.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.17:46:33.92#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:33.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:46:33.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:46:33.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:46:33.92#ibcon#enter wrdev, iclass 32, count 0 2006.285.17:46:33.92#ibcon#first serial, iclass 32, count 0 2006.285.17:46:33.92#ibcon#enter sib2, iclass 32, count 0 2006.285.17:46:33.92#ibcon#flushed, iclass 32, count 0 2006.285.17:46:33.92#ibcon#about to write, iclass 32, count 0 2006.285.17:46:33.92#ibcon#wrote, iclass 32, count 0 2006.285.17:46:33.92#ibcon#about to read 3, iclass 32, count 0 2006.285.17:46:33.93#ibcon#read 3, iclass 32, count 0 2006.285.17:46:33.93#ibcon#about to read 4, iclass 32, count 0 2006.285.17:46:33.93#ibcon#read 4, iclass 32, count 0 2006.285.17:46:33.93#ibcon#about to read 5, iclass 32, count 0 2006.285.17:46:33.93#ibcon#read 5, iclass 32, count 0 2006.285.17:46:33.93#ibcon#about to read 6, iclass 32, count 0 2006.285.17:46:33.93#ibcon#read 6, iclass 32, count 0 2006.285.17:46:33.93#ibcon#end of sib2, iclass 32, count 0 2006.285.17:46:33.93#ibcon#*mode == 0, iclass 32, count 0 2006.285.17:46:33.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.17:46:33.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.17:46:33.93#ibcon#*before write, iclass 32, count 0 2006.285.17:46:33.93#ibcon#enter sib2, iclass 32, count 0 2006.285.17:46:33.93#ibcon#flushed, iclass 32, count 0 2006.285.17:46:33.93#ibcon#about to write, iclass 32, count 0 2006.285.17:46:33.94#ibcon#wrote, iclass 32, count 0 2006.285.17:46:33.94#ibcon#about to read 3, iclass 32, count 0 2006.285.17:46:33.97#ibcon#read 3, iclass 32, count 0 2006.285.17:46:33.97#ibcon#about to read 4, iclass 32, count 0 2006.285.17:46:33.97#ibcon#read 4, iclass 32, count 0 2006.285.17:46:33.97#ibcon#about to read 5, iclass 32, count 0 2006.285.17:46:33.97#ibcon#read 5, iclass 32, count 0 2006.285.17:46:33.97#ibcon#about to read 6, iclass 32, count 0 2006.285.17:46:33.97#ibcon#read 6, iclass 32, count 0 2006.285.17:46:33.97#ibcon#end of sib2, iclass 32, count 0 2006.285.17:46:33.97#ibcon#*after write, iclass 32, count 0 2006.285.17:46:33.97#ibcon#*before return 0, iclass 32, count 0 2006.285.17:46:33.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:46:33.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.17:46:33.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.17:46:33.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.17:46:33.98$vck44/va=4,6 2006.285.17:46:33.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.17:46:33.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.17:46:33.98#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:33.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:46:34.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:46:34.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:46:34.02#ibcon#enter wrdev, iclass 34, count 2 2006.285.17:46:34.02#ibcon#first serial, iclass 34, count 2 2006.285.17:46:34.02#ibcon#enter sib2, iclass 34, count 2 2006.285.17:46:34.02#ibcon#flushed, iclass 34, count 2 2006.285.17:46:34.02#ibcon#about to write, iclass 34, count 2 2006.285.17:46:34.02#ibcon#wrote, iclass 34, count 2 2006.285.17:46:34.02#ibcon#about to read 3, iclass 34, count 2 2006.285.17:46:34.04#ibcon#read 3, iclass 34, count 2 2006.285.17:46:34.04#ibcon#about to read 4, iclass 34, count 2 2006.285.17:46:34.04#ibcon#read 4, iclass 34, count 2 2006.285.17:46:34.04#ibcon#about to read 5, iclass 34, count 2 2006.285.17:46:34.04#ibcon#read 5, iclass 34, count 2 2006.285.17:46:34.04#ibcon#about to read 6, iclass 34, count 2 2006.285.17:46:34.04#ibcon#read 6, iclass 34, count 2 2006.285.17:46:34.04#ibcon#end of sib2, iclass 34, count 2 2006.285.17:46:34.04#ibcon#*mode == 0, iclass 34, count 2 2006.285.17:46:34.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.17:46:34.04#ibcon#[25=AT04-06\r\n] 2006.285.17:46:34.04#ibcon#*before write, iclass 34, count 2 2006.285.17:46:34.04#ibcon#enter sib2, iclass 34, count 2 2006.285.17:46:34.04#ibcon#flushed, iclass 34, count 2 2006.285.17:46:34.04#ibcon#about to write, iclass 34, count 2 2006.285.17:46:34.04#ibcon#wrote, iclass 34, count 2 2006.285.17:46:34.04#ibcon#about to read 3, iclass 34, count 2 2006.285.17:46:34.07#ibcon#read 3, iclass 34, count 2 2006.285.17:46:34.07#ibcon#about to read 4, iclass 34, count 2 2006.285.17:46:34.07#ibcon#read 4, iclass 34, count 2 2006.285.17:46:34.07#ibcon#about to read 5, iclass 34, count 2 2006.285.17:46:34.07#ibcon#read 5, iclass 34, count 2 2006.285.17:46:34.07#ibcon#about to read 6, iclass 34, count 2 2006.285.17:46:34.07#ibcon#read 6, iclass 34, count 2 2006.285.17:46:34.07#ibcon#end of sib2, iclass 34, count 2 2006.285.17:46:34.07#ibcon#*after write, iclass 34, count 2 2006.285.17:46:34.07#ibcon#*before return 0, iclass 34, count 2 2006.285.17:46:34.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:46:34.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.17:46:34.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.17:46:34.07#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:34.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:46:34.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:46:34.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:46:34.19#ibcon#enter wrdev, iclass 34, count 0 2006.285.17:46:34.19#ibcon#first serial, iclass 34, count 0 2006.285.17:46:34.19#ibcon#enter sib2, iclass 34, count 0 2006.285.17:46:34.19#ibcon#flushed, iclass 34, count 0 2006.285.17:46:34.19#ibcon#about to write, iclass 34, count 0 2006.285.17:46:34.19#ibcon#wrote, iclass 34, count 0 2006.285.17:46:34.19#ibcon#about to read 3, iclass 34, count 0 2006.285.17:46:34.21#ibcon#read 3, iclass 34, count 0 2006.285.17:46:34.21#ibcon#about to read 4, iclass 34, count 0 2006.285.17:46:34.21#ibcon#read 4, iclass 34, count 0 2006.285.17:46:34.21#ibcon#about to read 5, iclass 34, count 0 2006.285.17:46:34.21#ibcon#read 5, iclass 34, count 0 2006.285.17:46:34.21#ibcon#about to read 6, iclass 34, count 0 2006.285.17:46:34.21#ibcon#read 6, iclass 34, count 0 2006.285.17:46:34.21#ibcon#end of sib2, iclass 34, count 0 2006.285.17:46:34.21#ibcon#*mode == 0, iclass 34, count 0 2006.285.17:46:34.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.17:46:34.21#ibcon#[25=USB\r\n] 2006.285.17:46:34.21#ibcon#*before write, iclass 34, count 0 2006.285.17:46:34.21#ibcon#enter sib2, iclass 34, count 0 2006.285.17:46:34.21#ibcon#flushed, iclass 34, count 0 2006.285.17:46:34.21#ibcon#about to write, iclass 34, count 0 2006.285.17:46:34.21#ibcon#wrote, iclass 34, count 0 2006.285.17:46:34.22#ibcon#about to read 3, iclass 34, count 0 2006.285.17:46:34.24#ibcon#read 3, iclass 34, count 0 2006.285.17:46:34.24#ibcon#about to read 4, iclass 34, count 0 2006.285.17:46:34.24#ibcon#read 4, iclass 34, count 0 2006.285.17:46:34.24#ibcon#about to read 5, iclass 34, count 0 2006.285.17:46:34.24#ibcon#read 5, iclass 34, count 0 2006.285.17:46:34.24#ibcon#about to read 6, iclass 34, count 0 2006.285.17:46:34.24#ibcon#read 6, iclass 34, count 0 2006.285.17:46:34.24#ibcon#end of sib2, iclass 34, count 0 2006.285.17:46:34.24#ibcon#*after write, iclass 34, count 0 2006.285.17:46:34.24#ibcon#*before return 0, iclass 34, count 0 2006.285.17:46:34.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:46:34.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.17:46:34.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.17:46:34.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.17:46:34.25$vck44/valo=5,734.99 2006.285.17:46:34.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.17:46:34.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.17:46:34.25#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:34.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:46:34.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:46:34.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:46:34.25#ibcon#enter wrdev, iclass 36, count 0 2006.285.17:46:34.25#ibcon#first serial, iclass 36, count 0 2006.285.17:46:34.25#ibcon#enter sib2, iclass 36, count 0 2006.285.17:46:34.25#ibcon#flushed, iclass 36, count 0 2006.285.17:46:34.25#ibcon#about to write, iclass 36, count 0 2006.285.17:46:34.25#ibcon#wrote, iclass 36, count 0 2006.285.17:46:34.25#ibcon#about to read 3, iclass 36, count 0 2006.285.17:46:34.26#ibcon#read 3, iclass 36, count 0 2006.285.17:46:34.26#ibcon#about to read 4, iclass 36, count 0 2006.285.17:46:34.26#ibcon#read 4, iclass 36, count 0 2006.285.17:46:34.26#ibcon#about to read 5, iclass 36, count 0 2006.285.17:46:34.26#ibcon#read 5, iclass 36, count 0 2006.285.17:46:34.26#ibcon#about to read 6, iclass 36, count 0 2006.285.17:46:34.26#ibcon#read 6, iclass 36, count 0 2006.285.17:46:34.26#ibcon#end of sib2, iclass 36, count 0 2006.285.17:46:34.26#ibcon#*mode == 0, iclass 36, count 0 2006.285.17:46:34.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.17:46:34.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.17:46:34.26#ibcon#*before write, iclass 36, count 0 2006.285.17:46:34.26#ibcon#enter sib2, iclass 36, count 0 2006.285.17:46:34.26#ibcon#flushed, iclass 36, count 0 2006.285.17:46:34.26#ibcon#about to write, iclass 36, count 0 2006.285.17:46:34.26#ibcon#wrote, iclass 36, count 0 2006.285.17:46:34.27#ibcon#about to read 3, iclass 36, count 0 2006.285.17:46:34.30#ibcon#read 3, iclass 36, count 0 2006.285.17:46:34.30#ibcon#about to read 4, iclass 36, count 0 2006.285.17:46:34.30#ibcon#read 4, iclass 36, count 0 2006.285.17:46:34.30#ibcon#about to read 5, iclass 36, count 0 2006.285.17:46:34.30#ibcon#read 5, iclass 36, count 0 2006.285.17:46:34.30#ibcon#about to read 6, iclass 36, count 0 2006.285.17:46:34.30#ibcon#read 6, iclass 36, count 0 2006.285.17:46:34.30#ibcon#end of sib2, iclass 36, count 0 2006.285.17:46:34.30#ibcon#*after write, iclass 36, count 0 2006.285.17:46:34.30#ibcon#*before return 0, iclass 36, count 0 2006.285.17:46:34.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:46:34.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:46:34.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.17:46:34.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.17:46:34.31$vck44/va=5,3 2006.285.17:46:34.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.17:46:34.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.17:46:34.31#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:34.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:46:34.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:46:34.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:46:34.35#ibcon#enter wrdev, iclass 38, count 2 2006.285.17:46:34.35#ibcon#first serial, iclass 38, count 2 2006.285.17:46:34.35#ibcon#enter sib2, iclass 38, count 2 2006.285.17:46:34.35#ibcon#flushed, iclass 38, count 2 2006.285.17:46:34.35#ibcon#about to write, iclass 38, count 2 2006.285.17:46:34.35#ibcon#wrote, iclass 38, count 2 2006.285.17:46:34.35#ibcon#about to read 3, iclass 38, count 2 2006.285.17:46:34.37#ibcon#read 3, iclass 38, count 2 2006.285.17:46:34.37#ibcon#about to read 4, iclass 38, count 2 2006.285.17:46:34.37#ibcon#read 4, iclass 38, count 2 2006.285.17:46:34.37#ibcon#about to read 5, iclass 38, count 2 2006.285.17:46:34.37#ibcon#read 5, iclass 38, count 2 2006.285.17:46:34.37#ibcon#about to read 6, iclass 38, count 2 2006.285.17:46:34.37#ibcon#read 6, iclass 38, count 2 2006.285.17:46:34.37#ibcon#end of sib2, iclass 38, count 2 2006.285.17:46:34.37#ibcon#*mode == 0, iclass 38, count 2 2006.285.17:46:34.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.17:46:34.37#ibcon#[25=AT05-03\r\n] 2006.285.17:46:34.37#ibcon#*before write, iclass 38, count 2 2006.285.17:46:34.37#ibcon#enter sib2, iclass 38, count 2 2006.285.17:46:34.37#ibcon#flushed, iclass 38, count 2 2006.285.17:46:34.37#ibcon#about to write, iclass 38, count 2 2006.285.17:46:34.37#ibcon#wrote, iclass 38, count 2 2006.285.17:46:34.37#ibcon#about to read 3, iclass 38, count 2 2006.285.17:46:34.40#ibcon#read 3, iclass 38, count 2 2006.285.17:46:34.40#ibcon#about to read 4, iclass 38, count 2 2006.285.17:46:34.40#ibcon#read 4, iclass 38, count 2 2006.285.17:46:34.40#ibcon#about to read 5, iclass 38, count 2 2006.285.17:46:34.40#ibcon#read 5, iclass 38, count 2 2006.285.17:46:34.40#ibcon#about to read 6, iclass 38, count 2 2006.285.17:46:34.40#ibcon#read 6, iclass 38, count 2 2006.285.17:46:34.40#ibcon#end of sib2, iclass 38, count 2 2006.285.17:46:34.40#ibcon#*after write, iclass 38, count 2 2006.285.17:46:34.40#ibcon#*before return 0, iclass 38, count 2 2006.285.17:46:34.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:46:34.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:46:34.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.17:46:34.40#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:34.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:46:34.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:46:34.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:46:34.52#ibcon#enter wrdev, iclass 38, count 0 2006.285.17:46:34.52#ibcon#first serial, iclass 38, count 0 2006.285.17:46:34.52#ibcon#enter sib2, iclass 38, count 0 2006.285.17:46:34.52#ibcon#flushed, iclass 38, count 0 2006.285.17:46:34.52#ibcon#about to write, iclass 38, count 0 2006.285.17:46:34.52#ibcon#wrote, iclass 38, count 0 2006.285.17:46:34.52#ibcon#about to read 3, iclass 38, count 0 2006.285.17:46:34.54#ibcon#read 3, iclass 38, count 0 2006.285.17:46:34.54#ibcon#about to read 4, iclass 38, count 0 2006.285.17:46:34.54#ibcon#read 4, iclass 38, count 0 2006.285.17:46:34.54#ibcon#about to read 5, iclass 38, count 0 2006.285.17:46:34.54#ibcon#read 5, iclass 38, count 0 2006.285.17:46:34.54#ibcon#about to read 6, iclass 38, count 0 2006.285.17:46:34.54#ibcon#read 6, iclass 38, count 0 2006.285.17:46:34.54#ibcon#end of sib2, iclass 38, count 0 2006.285.17:46:34.54#ibcon#*mode == 0, iclass 38, count 0 2006.285.17:46:34.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.17:46:34.54#ibcon#[25=USB\r\n] 2006.285.17:46:34.54#ibcon#*before write, iclass 38, count 0 2006.285.17:46:34.54#ibcon#enter sib2, iclass 38, count 0 2006.285.17:46:34.54#ibcon#flushed, iclass 38, count 0 2006.285.17:46:34.54#ibcon#about to write, iclass 38, count 0 2006.285.17:46:34.54#ibcon#wrote, iclass 38, count 0 2006.285.17:46:34.54#ibcon#about to read 3, iclass 38, count 0 2006.285.17:46:34.57#ibcon#read 3, iclass 38, count 0 2006.285.17:46:34.57#ibcon#about to read 4, iclass 38, count 0 2006.285.17:46:34.57#ibcon#read 4, iclass 38, count 0 2006.285.17:46:34.57#ibcon#about to read 5, iclass 38, count 0 2006.285.17:46:34.57#ibcon#read 5, iclass 38, count 0 2006.285.17:46:34.57#ibcon#about to read 6, iclass 38, count 0 2006.285.17:46:34.57#ibcon#read 6, iclass 38, count 0 2006.285.17:46:34.57#ibcon#end of sib2, iclass 38, count 0 2006.285.17:46:34.57#ibcon#*after write, iclass 38, count 0 2006.285.17:46:34.57#ibcon#*before return 0, iclass 38, count 0 2006.285.17:46:34.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:46:34.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:46:34.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.17:46:34.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.17:46:34.58$vck44/valo=6,814.99 2006.285.17:46:34.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.17:46:34.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.17:46:34.58#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:34.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:46:34.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:46:34.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:46:34.58#ibcon#enter wrdev, iclass 40, count 0 2006.285.17:46:34.58#ibcon#first serial, iclass 40, count 0 2006.285.17:46:34.58#ibcon#enter sib2, iclass 40, count 0 2006.285.17:46:34.58#ibcon#flushed, iclass 40, count 0 2006.285.17:46:34.58#ibcon#about to write, iclass 40, count 0 2006.285.17:46:34.58#ibcon#wrote, iclass 40, count 0 2006.285.17:46:34.58#ibcon#about to read 3, iclass 40, count 0 2006.285.17:46:34.59#ibcon#read 3, iclass 40, count 0 2006.285.17:46:34.59#ibcon#about to read 4, iclass 40, count 0 2006.285.17:46:34.59#ibcon#read 4, iclass 40, count 0 2006.285.17:46:34.59#ibcon#about to read 5, iclass 40, count 0 2006.285.17:46:34.59#ibcon#read 5, iclass 40, count 0 2006.285.17:46:34.59#ibcon#about to read 6, iclass 40, count 0 2006.285.17:46:34.59#ibcon#read 6, iclass 40, count 0 2006.285.17:46:34.59#ibcon#end of sib2, iclass 40, count 0 2006.285.17:46:34.59#ibcon#*mode == 0, iclass 40, count 0 2006.285.17:46:34.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.17:46:34.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.17:46:34.59#ibcon#*before write, iclass 40, count 0 2006.285.17:46:34.59#ibcon#enter sib2, iclass 40, count 0 2006.285.17:46:34.60#ibcon#flushed, iclass 40, count 0 2006.285.17:46:34.60#ibcon#about to write, iclass 40, count 0 2006.285.17:46:34.60#ibcon#wrote, iclass 40, count 0 2006.285.17:46:34.60#ibcon#about to read 3, iclass 40, count 0 2006.285.17:46:34.63#ibcon#read 3, iclass 40, count 0 2006.285.17:46:34.63#ibcon#about to read 4, iclass 40, count 0 2006.285.17:46:34.63#ibcon#read 4, iclass 40, count 0 2006.285.17:46:34.63#ibcon#about to read 5, iclass 40, count 0 2006.285.17:46:34.63#ibcon#read 5, iclass 40, count 0 2006.285.17:46:34.63#ibcon#about to read 6, iclass 40, count 0 2006.285.17:46:34.63#ibcon#read 6, iclass 40, count 0 2006.285.17:46:34.63#ibcon#end of sib2, iclass 40, count 0 2006.285.17:46:34.63#ibcon#*after write, iclass 40, count 0 2006.285.17:46:34.63#ibcon#*before return 0, iclass 40, count 0 2006.285.17:46:34.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:46:34.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:46:34.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.17:46:34.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.17:46:34.64$vck44/va=6,4 2006.285.17:46:34.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.17:46:34.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.17:46:34.64#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:34.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:46:34.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:46:34.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:46:34.68#ibcon#enter wrdev, iclass 4, count 2 2006.285.17:46:34.68#ibcon#first serial, iclass 4, count 2 2006.285.17:46:34.68#ibcon#enter sib2, iclass 4, count 2 2006.285.17:46:34.68#ibcon#flushed, iclass 4, count 2 2006.285.17:46:34.68#ibcon#about to write, iclass 4, count 2 2006.285.17:46:34.68#ibcon#wrote, iclass 4, count 2 2006.285.17:46:34.68#ibcon#about to read 3, iclass 4, count 2 2006.285.17:46:34.70#ibcon#read 3, iclass 4, count 2 2006.285.17:46:34.70#ibcon#about to read 4, iclass 4, count 2 2006.285.17:46:34.70#ibcon#read 4, iclass 4, count 2 2006.285.17:46:34.70#ibcon#about to read 5, iclass 4, count 2 2006.285.17:46:34.70#ibcon#read 5, iclass 4, count 2 2006.285.17:46:34.70#ibcon#about to read 6, iclass 4, count 2 2006.285.17:46:34.70#ibcon#read 6, iclass 4, count 2 2006.285.17:46:34.70#ibcon#end of sib2, iclass 4, count 2 2006.285.17:46:34.70#ibcon#*mode == 0, iclass 4, count 2 2006.285.17:46:34.70#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.17:46:34.70#ibcon#[25=AT06-04\r\n] 2006.285.17:46:34.70#ibcon#*before write, iclass 4, count 2 2006.285.17:46:34.70#ibcon#enter sib2, iclass 4, count 2 2006.285.17:46:34.70#ibcon#flushed, iclass 4, count 2 2006.285.17:46:34.70#ibcon#about to write, iclass 4, count 2 2006.285.17:46:34.70#ibcon#wrote, iclass 4, count 2 2006.285.17:46:34.70#ibcon#about to read 3, iclass 4, count 2 2006.285.17:46:34.73#ibcon#read 3, iclass 4, count 2 2006.285.17:46:34.73#ibcon#about to read 4, iclass 4, count 2 2006.285.17:46:34.73#ibcon#read 4, iclass 4, count 2 2006.285.17:46:34.73#ibcon#about to read 5, iclass 4, count 2 2006.285.17:46:34.73#ibcon#read 5, iclass 4, count 2 2006.285.17:46:34.73#ibcon#about to read 6, iclass 4, count 2 2006.285.17:46:34.73#ibcon#read 6, iclass 4, count 2 2006.285.17:46:34.73#ibcon#end of sib2, iclass 4, count 2 2006.285.17:46:34.73#ibcon#*after write, iclass 4, count 2 2006.285.17:46:34.73#ibcon#*before return 0, iclass 4, count 2 2006.285.17:46:34.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:46:34.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:46:34.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.17:46:34.73#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:34.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:46:34.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:46:34.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:46:34.88#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:46:34.88#ibcon#first serial, iclass 4, count 0 2006.285.17:46:34.88#ibcon#enter sib2, iclass 4, count 0 2006.285.17:46:34.88#ibcon#flushed, iclass 4, count 0 2006.285.17:46:34.88#ibcon#about to write, iclass 4, count 0 2006.285.17:46:34.88#ibcon#wrote, iclass 4, count 0 2006.285.17:46:34.88#ibcon#about to read 3, iclass 4, count 0 2006.285.17:46:34.89#ibcon#read 3, iclass 4, count 0 2006.285.17:46:34.89#ibcon#about to read 4, iclass 4, count 0 2006.285.17:46:34.89#ibcon#read 4, iclass 4, count 0 2006.285.17:46:34.89#ibcon#about to read 5, iclass 4, count 0 2006.285.17:46:34.89#ibcon#read 5, iclass 4, count 0 2006.285.17:46:34.89#ibcon#about to read 6, iclass 4, count 0 2006.285.17:46:34.89#ibcon#read 6, iclass 4, count 0 2006.285.17:46:34.89#ibcon#end of sib2, iclass 4, count 0 2006.285.17:46:34.89#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:46:34.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:46:34.89#ibcon#[25=USB\r\n] 2006.285.17:46:34.89#ibcon#*before write, iclass 4, count 0 2006.285.17:46:34.90#ibcon#enter sib2, iclass 4, count 0 2006.285.17:46:34.90#ibcon#flushed, iclass 4, count 0 2006.285.17:46:34.90#ibcon#about to write, iclass 4, count 0 2006.285.17:46:34.90#ibcon#wrote, iclass 4, count 0 2006.285.17:46:34.90#ibcon#about to read 3, iclass 4, count 0 2006.285.17:46:34.92#ibcon#read 3, iclass 4, count 0 2006.285.17:46:34.92#ibcon#about to read 4, iclass 4, count 0 2006.285.17:46:34.92#ibcon#read 4, iclass 4, count 0 2006.285.17:46:34.92#ibcon#about to read 5, iclass 4, count 0 2006.285.17:46:34.92#ibcon#read 5, iclass 4, count 0 2006.285.17:46:34.92#ibcon#about to read 6, iclass 4, count 0 2006.285.17:46:34.92#ibcon#read 6, iclass 4, count 0 2006.285.17:46:34.92#ibcon#end of sib2, iclass 4, count 0 2006.285.17:46:34.92#ibcon#*after write, iclass 4, count 0 2006.285.17:46:34.92#ibcon#*before return 0, iclass 4, count 0 2006.285.17:46:34.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:46:34.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:46:34.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:46:34.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:46:34.93$vck44/valo=7,864.99 2006.285.17:46:34.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.17:46:34.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.17:46:34.93#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:34.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:46:34.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:46:34.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:46:34.93#ibcon#enter wrdev, iclass 6, count 0 2006.285.17:46:34.93#ibcon#first serial, iclass 6, count 0 2006.285.17:46:34.93#ibcon#enter sib2, iclass 6, count 0 2006.285.17:46:34.93#ibcon#flushed, iclass 6, count 0 2006.285.17:46:34.93#ibcon#about to write, iclass 6, count 0 2006.285.17:46:34.93#ibcon#wrote, iclass 6, count 0 2006.285.17:46:34.93#ibcon#about to read 3, iclass 6, count 0 2006.285.17:46:34.94#ibcon#read 3, iclass 6, count 0 2006.285.17:46:34.94#ibcon#about to read 4, iclass 6, count 0 2006.285.17:46:34.94#ibcon#read 4, iclass 6, count 0 2006.285.17:46:34.94#ibcon#about to read 5, iclass 6, count 0 2006.285.17:46:34.94#ibcon#read 5, iclass 6, count 0 2006.285.17:46:34.94#ibcon#about to read 6, iclass 6, count 0 2006.285.17:46:34.94#ibcon#read 6, iclass 6, count 0 2006.285.17:46:34.94#ibcon#end of sib2, iclass 6, count 0 2006.285.17:46:34.94#ibcon#*mode == 0, iclass 6, count 0 2006.285.17:46:34.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.17:46:34.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.17:46:34.94#ibcon#*before write, iclass 6, count 0 2006.285.17:46:34.94#ibcon#enter sib2, iclass 6, count 0 2006.285.17:46:34.94#ibcon#flushed, iclass 6, count 0 2006.285.17:46:34.94#ibcon#about to write, iclass 6, count 0 2006.285.17:46:34.95#ibcon#wrote, iclass 6, count 0 2006.285.17:46:34.95#ibcon#about to read 3, iclass 6, count 0 2006.285.17:46:34.98#ibcon#read 3, iclass 6, count 0 2006.285.17:46:34.98#ibcon#about to read 4, iclass 6, count 0 2006.285.17:46:34.98#ibcon#read 4, iclass 6, count 0 2006.285.17:46:34.98#ibcon#about to read 5, iclass 6, count 0 2006.285.17:46:34.98#ibcon#read 5, iclass 6, count 0 2006.285.17:46:34.98#ibcon#about to read 6, iclass 6, count 0 2006.285.17:46:34.98#ibcon#read 6, iclass 6, count 0 2006.285.17:46:34.98#ibcon#end of sib2, iclass 6, count 0 2006.285.17:46:34.98#ibcon#*after write, iclass 6, count 0 2006.285.17:46:34.98#ibcon#*before return 0, iclass 6, count 0 2006.285.17:46:34.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:46:34.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:46:34.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.17:46:34.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.17:46:34.99$vck44/va=7,4 2006.285.17:46:34.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.17:46:34.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.17:46:34.99#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:34.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:46:35.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:46:35.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:46:35.03#ibcon#enter wrdev, iclass 10, count 2 2006.285.17:46:35.03#ibcon#first serial, iclass 10, count 2 2006.285.17:46:35.03#ibcon#enter sib2, iclass 10, count 2 2006.285.17:46:35.03#ibcon#flushed, iclass 10, count 2 2006.285.17:46:35.03#ibcon#about to write, iclass 10, count 2 2006.285.17:46:35.03#ibcon#wrote, iclass 10, count 2 2006.285.17:46:35.03#ibcon#about to read 3, iclass 10, count 2 2006.285.17:46:35.05#ibcon#read 3, iclass 10, count 2 2006.285.17:46:35.05#ibcon#about to read 4, iclass 10, count 2 2006.285.17:46:35.05#ibcon#read 4, iclass 10, count 2 2006.285.17:46:35.05#ibcon#about to read 5, iclass 10, count 2 2006.285.17:46:35.05#ibcon#read 5, iclass 10, count 2 2006.285.17:46:35.05#ibcon#about to read 6, iclass 10, count 2 2006.285.17:46:35.05#ibcon#read 6, iclass 10, count 2 2006.285.17:46:35.05#ibcon#end of sib2, iclass 10, count 2 2006.285.17:46:35.05#ibcon#*mode == 0, iclass 10, count 2 2006.285.17:46:35.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.17:46:35.05#ibcon#[25=AT07-04\r\n] 2006.285.17:46:35.05#ibcon#*before write, iclass 10, count 2 2006.285.17:46:35.05#ibcon#enter sib2, iclass 10, count 2 2006.285.17:46:35.05#ibcon#flushed, iclass 10, count 2 2006.285.17:46:35.05#ibcon#about to write, iclass 10, count 2 2006.285.17:46:35.06#ibcon#wrote, iclass 10, count 2 2006.285.17:46:35.06#ibcon#about to read 3, iclass 10, count 2 2006.285.17:46:35.08#ibcon#read 3, iclass 10, count 2 2006.285.17:46:35.08#ibcon#about to read 4, iclass 10, count 2 2006.285.17:46:35.08#ibcon#read 4, iclass 10, count 2 2006.285.17:46:35.08#ibcon#about to read 5, iclass 10, count 2 2006.285.17:46:35.08#ibcon#read 5, iclass 10, count 2 2006.285.17:46:35.08#ibcon#about to read 6, iclass 10, count 2 2006.285.17:46:35.08#ibcon#read 6, iclass 10, count 2 2006.285.17:46:35.08#ibcon#end of sib2, iclass 10, count 2 2006.285.17:46:35.08#ibcon#*after write, iclass 10, count 2 2006.285.17:46:35.08#ibcon#*before return 0, iclass 10, count 2 2006.285.17:46:35.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:46:35.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:46:35.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.17:46:35.08#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:35.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:46:35.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:46:35.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:46:35.20#ibcon#enter wrdev, iclass 10, count 0 2006.285.17:46:35.20#ibcon#first serial, iclass 10, count 0 2006.285.17:46:35.20#ibcon#enter sib2, iclass 10, count 0 2006.285.17:46:35.20#ibcon#flushed, iclass 10, count 0 2006.285.17:46:35.20#ibcon#about to write, iclass 10, count 0 2006.285.17:46:35.20#ibcon#wrote, iclass 10, count 0 2006.285.17:46:35.20#ibcon#about to read 3, iclass 10, count 0 2006.285.17:46:35.22#ibcon#read 3, iclass 10, count 0 2006.285.17:46:35.22#ibcon#about to read 4, iclass 10, count 0 2006.285.17:46:35.22#ibcon#read 4, iclass 10, count 0 2006.285.17:46:35.22#ibcon#about to read 5, iclass 10, count 0 2006.285.17:46:35.22#ibcon#read 5, iclass 10, count 0 2006.285.17:46:35.22#ibcon#about to read 6, iclass 10, count 0 2006.285.17:46:35.22#ibcon#read 6, iclass 10, count 0 2006.285.17:46:35.22#ibcon#end of sib2, iclass 10, count 0 2006.285.17:46:35.22#ibcon#*mode == 0, iclass 10, count 0 2006.285.17:46:35.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.17:46:35.22#ibcon#[25=USB\r\n] 2006.285.17:46:35.22#ibcon#*before write, iclass 10, count 0 2006.285.17:46:35.22#ibcon#enter sib2, iclass 10, count 0 2006.285.17:46:35.22#ibcon#flushed, iclass 10, count 0 2006.285.17:46:35.22#ibcon#about to write, iclass 10, count 0 2006.285.17:46:35.23#ibcon#wrote, iclass 10, count 0 2006.285.17:46:35.23#ibcon#about to read 3, iclass 10, count 0 2006.285.17:46:35.25#ibcon#read 3, iclass 10, count 0 2006.285.17:46:35.25#ibcon#about to read 4, iclass 10, count 0 2006.285.17:46:35.25#ibcon#read 4, iclass 10, count 0 2006.285.17:46:35.25#ibcon#about to read 5, iclass 10, count 0 2006.285.17:46:35.25#ibcon#read 5, iclass 10, count 0 2006.285.17:46:35.25#ibcon#about to read 6, iclass 10, count 0 2006.285.17:46:35.25#ibcon#read 6, iclass 10, count 0 2006.285.17:46:35.25#ibcon#end of sib2, iclass 10, count 0 2006.285.17:46:35.25#ibcon#*after write, iclass 10, count 0 2006.285.17:46:35.25#ibcon#*before return 0, iclass 10, count 0 2006.285.17:46:35.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:46:35.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:46:35.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.17:46:35.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.17:46:35.26$vck44/valo=8,884.99 2006.285.17:46:35.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.17:46:35.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.17:46:35.26#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:35.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:46:35.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:46:35.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:46:35.26#ibcon#enter wrdev, iclass 12, count 0 2006.285.17:46:35.26#ibcon#first serial, iclass 12, count 0 2006.285.17:46:35.26#ibcon#enter sib2, iclass 12, count 0 2006.285.17:46:35.26#ibcon#flushed, iclass 12, count 0 2006.285.17:46:35.26#ibcon#about to write, iclass 12, count 0 2006.285.17:46:35.26#ibcon#wrote, iclass 12, count 0 2006.285.17:46:35.26#ibcon#about to read 3, iclass 12, count 0 2006.285.17:46:35.27#ibcon#read 3, iclass 12, count 0 2006.285.17:46:35.27#ibcon#about to read 4, iclass 12, count 0 2006.285.17:46:35.27#ibcon#read 4, iclass 12, count 0 2006.285.17:46:35.27#ibcon#about to read 5, iclass 12, count 0 2006.285.17:46:35.27#ibcon#read 5, iclass 12, count 0 2006.285.17:46:35.27#ibcon#about to read 6, iclass 12, count 0 2006.285.17:46:35.27#ibcon#read 6, iclass 12, count 0 2006.285.17:46:35.27#ibcon#end of sib2, iclass 12, count 0 2006.285.17:46:35.27#ibcon#*mode == 0, iclass 12, count 0 2006.285.17:46:35.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.17:46:35.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.17:46:35.27#ibcon#*before write, iclass 12, count 0 2006.285.17:46:35.27#ibcon#enter sib2, iclass 12, count 0 2006.285.17:46:35.27#ibcon#flushed, iclass 12, count 0 2006.285.17:46:35.27#ibcon#about to write, iclass 12, count 0 2006.285.17:46:35.27#ibcon#wrote, iclass 12, count 0 2006.285.17:46:35.28#ibcon#about to read 3, iclass 12, count 0 2006.285.17:46:35.31#ibcon#read 3, iclass 12, count 0 2006.285.17:46:35.31#ibcon#about to read 4, iclass 12, count 0 2006.285.17:46:35.31#ibcon#read 4, iclass 12, count 0 2006.285.17:46:35.31#ibcon#about to read 5, iclass 12, count 0 2006.285.17:46:35.31#ibcon#read 5, iclass 12, count 0 2006.285.17:46:35.31#ibcon#about to read 6, iclass 12, count 0 2006.285.17:46:35.31#ibcon#read 6, iclass 12, count 0 2006.285.17:46:35.31#ibcon#end of sib2, iclass 12, count 0 2006.285.17:46:35.31#ibcon#*after write, iclass 12, count 0 2006.285.17:46:35.31#ibcon#*before return 0, iclass 12, count 0 2006.285.17:46:35.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:46:35.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:46:35.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.17:46:35.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.17:46:35.32$vck44/va=8,3 2006.285.17:46:35.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.17:46:35.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.17:46:35.32#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:35.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:46:35.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:46:35.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:46:35.36#ibcon#enter wrdev, iclass 14, count 2 2006.285.17:46:35.36#ibcon#first serial, iclass 14, count 2 2006.285.17:46:35.36#ibcon#enter sib2, iclass 14, count 2 2006.285.17:46:35.36#ibcon#flushed, iclass 14, count 2 2006.285.17:46:35.36#ibcon#about to write, iclass 14, count 2 2006.285.17:46:35.36#ibcon#wrote, iclass 14, count 2 2006.285.17:46:35.36#ibcon#about to read 3, iclass 14, count 2 2006.285.17:46:35.38#ibcon#read 3, iclass 14, count 2 2006.285.17:46:35.38#ibcon#about to read 4, iclass 14, count 2 2006.285.17:46:35.38#ibcon#read 4, iclass 14, count 2 2006.285.17:46:35.38#ibcon#about to read 5, iclass 14, count 2 2006.285.17:46:35.38#ibcon#read 5, iclass 14, count 2 2006.285.17:46:35.38#ibcon#about to read 6, iclass 14, count 2 2006.285.17:46:35.38#ibcon#read 6, iclass 14, count 2 2006.285.17:46:35.38#ibcon#end of sib2, iclass 14, count 2 2006.285.17:46:35.38#ibcon#*mode == 0, iclass 14, count 2 2006.285.17:46:35.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.17:46:35.38#ibcon#[25=AT08-03\r\n] 2006.285.17:46:35.38#ibcon#*before write, iclass 14, count 2 2006.285.17:46:35.38#ibcon#enter sib2, iclass 14, count 2 2006.285.17:46:35.38#ibcon#flushed, iclass 14, count 2 2006.285.17:46:35.38#ibcon#about to write, iclass 14, count 2 2006.285.17:46:35.38#ibcon#wrote, iclass 14, count 2 2006.285.17:46:35.38#ibcon#about to read 3, iclass 14, count 2 2006.285.17:46:35.41#ibcon#read 3, iclass 14, count 2 2006.285.17:46:35.41#ibcon#about to read 4, iclass 14, count 2 2006.285.17:46:35.41#ibcon#read 4, iclass 14, count 2 2006.285.17:46:35.41#ibcon#about to read 5, iclass 14, count 2 2006.285.17:46:35.41#ibcon#read 5, iclass 14, count 2 2006.285.17:46:35.41#ibcon#about to read 6, iclass 14, count 2 2006.285.17:46:35.41#ibcon#read 6, iclass 14, count 2 2006.285.17:46:35.41#ibcon#end of sib2, iclass 14, count 2 2006.285.17:46:35.41#ibcon#*after write, iclass 14, count 2 2006.285.17:46:35.41#ibcon#*before return 0, iclass 14, count 2 2006.285.17:46:35.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:46:35.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:46:35.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.17:46:35.41#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:35.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:46:35.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:46:35.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:46:35.53#ibcon#enter wrdev, iclass 14, count 0 2006.285.17:46:35.53#ibcon#first serial, iclass 14, count 0 2006.285.17:46:35.53#ibcon#enter sib2, iclass 14, count 0 2006.285.17:46:35.53#ibcon#flushed, iclass 14, count 0 2006.285.17:46:35.53#ibcon#about to write, iclass 14, count 0 2006.285.17:46:35.53#ibcon#wrote, iclass 14, count 0 2006.285.17:46:35.53#ibcon#about to read 3, iclass 14, count 0 2006.285.17:46:35.55#ibcon#read 3, iclass 14, count 0 2006.285.17:46:35.55#ibcon#about to read 4, iclass 14, count 0 2006.285.17:46:35.55#ibcon#read 4, iclass 14, count 0 2006.285.17:46:35.55#ibcon#about to read 5, iclass 14, count 0 2006.285.17:46:35.55#ibcon#read 5, iclass 14, count 0 2006.285.17:46:35.55#ibcon#about to read 6, iclass 14, count 0 2006.285.17:46:35.55#ibcon#read 6, iclass 14, count 0 2006.285.17:46:35.55#ibcon#end of sib2, iclass 14, count 0 2006.285.17:46:35.55#ibcon#*mode == 0, iclass 14, count 0 2006.285.17:46:35.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.17:46:35.55#ibcon#[25=USB\r\n] 2006.285.17:46:35.55#ibcon#*before write, iclass 14, count 0 2006.285.17:46:35.55#ibcon#enter sib2, iclass 14, count 0 2006.285.17:46:35.55#ibcon#flushed, iclass 14, count 0 2006.285.17:46:35.55#ibcon#about to write, iclass 14, count 0 2006.285.17:46:35.55#ibcon#wrote, iclass 14, count 0 2006.285.17:46:35.55#ibcon#about to read 3, iclass 14, count 0 2006.285.17:46:35.58#ibcon#read 3, iclass 14, count 0 2006.285.17:46:35.58#ibcon#about to read 4, iclass 14, count 0 2006.285.17:46:35.58#ibcon#read 4, iclass 14, count 0 2006.285.17:46:35.58#ibcon#about to read 5, iclass 14, count 0 2006.285.17:46:35.58#ibcon#read 5, iclass 14, count 0 2006.285.17:46:35.58#ibcon#about to read 6, iclass 14, count 0 2006.285.17:46:35.58#ibcon#read 6, iclass 14, count 0 2006.285.17:46:35.58#ibcon#end of sib2, iclass 14, count 0 2006.285.17:46:35.58#ibcon#*after write, iclass 14, count 0 2006.285.17:46:35.58#ibcon#*before return 0, iclass 14, count 0 2006.285.17:46:35.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:46:35.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:46:35.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.17:46:35.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.17:46:35.59$vck44/vblo=1,629.99 2006.285.17:46:35.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.17:46:35.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.17:46:35.59#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:35.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:46:35.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:46:35.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:46:35.59#ibcon#enter wrdev, iclass 16, count 0 2006.285.17:46:35.59#ibcon#first serial, iclass 16, count 0 2006.285.17:46:35.59#ibcon#enter sib2, iclass 16, count 0 2006.285.17:46:35.59#ibcon#flushed, iclass 16, count 0 2006.285.17:46:35.59#ibcon#about to write, iclass 16, count 0 2006.285.17:46:35.59#ibcon#wrote, iclass 16, count 0 2006.285.17:46:35.59#ibcon#about to read 3, iclass 16, count 0 2006.285.17:46:35.60#ibcon#read 3, iclass 16, count 0 2006.285.17:46:35.60#ibcon#about to read 4, iclass 16, count 0 2006.285.17:46:35.60#ibcon#read 4, iclass 16, count 0 2006.285.17:46:35.60#ibcon#about to read 5, iclass 16, count 0 2006.285.17:46:35.60#ibcon#read 5, iclass 16, count 0 2006.285.17:46:35.60#ibcon#about to read 6, iclass 16, count 0 2006.285.17:46:35.60#ibcon#read 6, iclass 16, count 0 2006.285.17:46:35.60#ibcon#end of sib2, iclass 16, count 0 2006.285.17:46:35.60#ibcon#*mode == 0, iclass 16, count 0 2006.285.17:46:35.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.17:46:35.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.17:46:35.60#ibcon#*before write, iclass 16, count 0 2006.285.17:46:35.60#ibcon#enter sib2, iclass 16, count 0 2006.285.17:46:35.61#ibcon#flushed, iclass 16, count 0 2006.285.17:46:35.61#ibcon#about to write, iclass 16, count 0 2006.285.17:46:35.61#ibcon#wrote, iclass 16, count 0 2006.285.17:46:35.61#ibcon#about to read 3, iclass 16, count 0 2006.285.17:46:35.64#ibcon#read 3, iclass 16, count 0 2006.285.17:46:35.64#ibcon#about to read 4, iclass 16, count 0 2006.285.17:46:35.64#ibcon#read 4, iclass 16, count 0 2006.285.17:46:35.64#ibcon#about to read 5, iclass 16, count 0 2006.285.17:46:35.64#ibcon#read 5, iclass 16, count 0 2006.285.17:46:35.64#ibcon#about to read 6, iclass 16, count 0 2006.285.17:46:35.64#ibcon#read 6, iclass 16, count 0 2006.285.17:46:35.64#ibcon#end of sib2, iclass 16, count 0 2006.285.17:46:35.64#ibcon#*after write, iclass 16, count 0 2006.285.17:46:35.64#ibcon#*before return 0, iclass 16, count 0 2006.285.17:46:35.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:46:35.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:46:35.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.17:46:35.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.17:46:35.65$vck44/vb=1,4 2006.285.17:46:35.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.17:46:35.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.17:46:35.65#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:35.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:46:35.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:46:35.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:46:35.65#ibcon#enter wrdev, iclass 18, count 2 2006.285.17:46:35.65#ibcon#first serial, iclass 18, count 2 2006.285.17:46:35.65#ibcon#enter sib2, iclass 18, count 2 2006.285.17:46:35.65#ibcon#flushed, iclass 18, count 2 2006.285.17:46:35.65#ibcon#about to write, iclass 18, count 2 2006.285.17:46:35.65#ibcon#wrote, iclass 18, count 2 2006.285.17:46:35.65#ibcon#about to read 3, iclass 18, count 2 2006.285.17:46:35.66#ibcon#read 3, iclass 18, count 2 2006.285.17:46:35.66#ibcon#about to read 4, iclass 18, count 2 2006.285.17:46:35.66#ibcon#read 4, iclass 18, count 2 2006.285.17:46:35.66#ibcon#about to read 5, iclass 18, count 2 2006.285.17:46:35.66#ibcon#read 5, iclass 18, count 2 2006.285.17:46:35.66#ibcon#about to read 6, iclass 18, count 2 2006.285.17:46:35.66#ibcon#read 6, iclass 18, count 2 2006.285.17:46:35.66#ibcon#end of sib2, iclass 18, count 2 2006.285.17:46:35.66#ibcon#*mode == 0, iclass 18, count 2 2006.285.17:46:35.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.17:46:35.66#ibcon#[27=AT01-04\r\n] 2006.285.17:46:35.66#ibcon#*before write, iclass 18, count 2 2006.285.17:46:35.66#ibcon#enter sib2, iclass 18, count 2 2006.285.17:46:35.66#ibcon#flushed, iclass 18, count 2 2006.285.17:46:35.66#ibcon#about to write, iclass 18, count 2 2006.285.17:46:35.67#ibcon#wrote, iclass 18, count 2 2006.285.17:46:35.67#ibcon#about to read 3, iclass 18, count 2 2006.285.17:46:35.69#ibcon#read 3, iclass 18, count 2 2006.285.17:46:35.69#ibcon#about to read 4, iclass 18, count 2 2006.285.17:46:35.69#ibcon#read 4, iclass 18, count 2 2006.285.17:46:35.69#ibcon#about to read 5, iclass 18, count 2 2006.285.17:46:35.69#ibcon#read 5, iclass 18, count 2 2006.285.17:46:35.69#ibcon#about to read 6, iclass 18, count 2 2006.285.17:46:35.69#ibcon#read 6, iclass 18, count 2 2006.285.17:46:35.69#ibcon#end of sib2, iclass 18, count 2 2006.285.17:46:35.69#ibcon#*after write, iclass 18, count 2 2006.285.17:46:35.69#ibcon#*before return 0, iclass 18, count 2 2006.285.17:46:35.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:46:35.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.17:46:35.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.17:46:35.69#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:35.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:46:35.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:46:35.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:46:35.85#ibcon#enter wrdev, iclass 18, count 0 2006.285.17:46:35.85#ibcon#first serial, iclass 18, count 0 2006.285.17:46:35.85#ibcon#enter sib2, iclass 18, count 0 2006.285.17:46:35.85#ibcon#flushed, iclass 18, count 0 2006.285.17:46:35.85#ibcon#about to write, iclass 18, count 0 2006.285.17:46:35.85#ibcon#wrote, iclass 18, count 0 2006.285.17:46:35.85#ibcon#about to read 3, iclass 18, count 0 2006.285.17:46:35.86#ibcon#read 3, iclass 18, count 0 2006.285.17:46:35.86#ibcon#about to read 4, iclass 18, count 0 2006.285.17:46:35.86#ibcon#read 4, iclass 18, count 0 2006.285.17:46:35.86#ibcon#about to read 5, iclass 18, count 0 2006.285.17:46:35.86#ibcon#read 5, iclass 18, count 0 2006.285.17:46:35.86#ibcon#about to read 6, iclass 18, count 0 2006.285.17:46:35.86#ibcon#read 6, iclass 18, count 0 2006.285.17:46:35.86#ibcon#end of sib2, iclass 18, count 0 2006.285.17:46:35.86#ibcon#*mode == 0, iclass 18, count 0 2006.285.17:46:35.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.17:46:35.86#ibcon#[27=USB\r\n] 2006.285.17:46:35.86#ibcon#*before write, iclass 18, count 0 2006.285.17:46:35.86#ibcon#enter sib2, iclass 18, count 0 2006.285.17:46:35.86#ibcon#flushed, iclass 18, count 0 2006.285.17:46:35.86#ibcon#about to write, iclass 18, count 0 2006.285.17:46:35.87#ibcon#wrote, iclass 18, count 0 2006.285.17:46:35.87#ibcon#about to read 3, iclass 18, count 0 2006.285.17:46:35.89#ibcon#read 3, iclass 18, count 0 2006.285.17:46:35.89#ibcon#about to read 4, iclass 18, count 0 2006.285.17:46:35.89#ibcon#read 4, iclass 18, count 0 2006.285.17:46:35.89#ibcon#about to read 5, iclass 18, count 0 2006.285.17:46:35.89#ibcon#read 5, iclass 18, count 0 2006.285.17:46:35.89#ibcon#about to read 6, iclass 18, count 0 2006.285.17:46:35.89#ibcon#read 6, iclass 18, count 0 2006.285.17:46:35.89#ibcon#end of sib2, iclass 18, count 0 2006.285.17:46:35.89#ibcon#*after write, iclass 18, count 0 2006.285.17:46:35.89#ibcon#*before return 0, iclass 18, count 0 2006.285.17:46:35.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:46:35.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.17:46:35.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.17:46:35.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.17:46:35.90$vck44/vblo=2,634.99 2006.285.17:46:35.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.17:46:35.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.17:46:35.90#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:35.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:46:35.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:46:35.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:46:35.90#ibcon#enter wrdev, iclass 20, count 0 2006.285.17:46:35.90#ibcon#first serial, iclass 20, count 0 2006.285.17:46:35.90#ibcon#enter sib2, iclass 20, count 0 2006.285.17:46:35.90#ibcon#flushed, iclass 20, count 0 2006.285.17:46:35.90#ibcon#about to write, iclass 20, count 0 2006.285.17:46:35.90#ibcon#wrote, iclass 20, count 0 2006.285.17:46:35.90#ibcon#about to read 3, iclass 20, count 0 2006.285.17:46:35.91#ibcon#read 3, iclass 20, count 0 2006.285.17:46:35.91#ibcon#about to read 4, iclass 20, count 0 2006.285.17:46:35.91#ibcon#read 4, iclass 20, count 0 2006.285.17:46:35.91#ibcon#about to read 5, iclass 20, count 0 2006.285.17:46:35.91#ibcon#read 5, iclass 20, count 0 2006.285.17:46:35.91#ibcon#about to read 6, iclass 20, count 0 2006.285.17:46:35.91#ibcon#read 6, iclass 20, count 0 2006.285.17:46:35.91#ibcon#end of sib2, iclass 20, count 0 2006.285.17:46:35.91#ibcon#*mode == 0, iclass 20, count 0 2006.285.17:46:35.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.17:46:35.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.17:46:35.91#ibcon#*before write, iclass 20, count 0 2006.285.17:46:35.91#ibcon#enter sib2, iclass 20, count 0 2006.285.17:46:35.91#ibcon#flushed, iclass 20, count 0 2006.285.17:46:35.91#ibcon#about to write, iclass 20, count 0 2006.285.17:46:35.92#ibcon#wrote, iclass 20, count 0 2006.285.17:46:35.92#ibcon#about to read 3, iclass 20, count 0 2006.285.17:46:35.95#ibcon#read 3, iclass 20, count 0 2006.285.17:46:35.95#ibcon#about to read 4, iclass 20, count 0 2006.285.17:46:35.95#ibcon#read 4, iclass 20, count 0 2006.285.17:46:35.95#ibcon#about to read 5, iclass 20, count 0 2006.285.17:46:35.95#ibcon#read 5, iclass 20, count 0 2006.285.17:46:35.95#ibcon#about to read 6, iclass 20, count 0 2006.285.17:46:35.95#ibcon#read 6, iclass 20, count 0 2006.285.17:46:35.95#ibcon#end of sib2, iclass 20, count 0 2006.285.17:46:35.95#ibcon#*after write, iclass 20, count 0 2006.285.17:46:35.95#ibcon#*before return 0, iclass 20, count 0 2006.285.17:46:35.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:46:35.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.17:46:35.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.17:46:35.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.17:46:35.96$vck44/vb=2,5 2006.285.17:46:35.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.17:46:35.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.17:46:35.96#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:35.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:46:36.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:46:36.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:46:36.01#ibcon#enter wrdev, iclass 22, count 2 2006.285.17:46:36.01#ibcon#first serial, iclass 22, count 2 2006.285.17:46:36.01#ibcon#enter sib2, iclass 22, count 2 2006.285.17:46:36.01#ibcon#flushed, iclass 22, count 2 2006.285.17:46:36.01#ibcon#about to write, iclass 22, count 2 2006.285.17:46:36.01#ibcon#wrote, iclass 22, count 2 2006.285.17:46:36.01#ibcon#about to read 3, iclass 22, count 2 2006.285.17:46:36.02#ibcon#read 3, iclass 22, count 2 2006.285.17:46:36.02#ibcon#about to read 4, iclass 22, count 2 2006.285.17:46:36.02#ibcon#read 4, iclass 22, count 2 2006.285.17:46:36.02#ibcon#about to read 5, iclass 22, count 2 2006.285.17:46:36.02#ibcon#read 5, iclass 22, count 2 2006.285.17:46:36.02#ibcon#about to read 6, iclass 22, count 2 2006.285.17:46:36.02#ibcon#read 6, iclass 22, count 2 2006.285.17:46:36.02#ibcon#end of sib2, iclass 22, count 2 2006.285.17:46:36.02#ibcon#*mode == 0, iclass 22, count 2 2006.285.17:46:36.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.17:46:36.02#ibcon#[27=AT02-05\r\n] 2006.285.17:46:36.02#ibcon#*before write, iclass 22, count 2 2006.285.17:46:36.02#ibcon#enter sib2, iclass 22, count 2 2006.285.17:46:36.02#ibcon#flushed, iclass 22, count 2 2006.285.17:46:36.02#ibcon#about to write, iclass 22, count 2 2006.285.17:46:36.02#ibcon#wrote, iclass 22, count 2 2006.285.17:46:36.03#ibcon#about to read 3, iclass 22, count 2 2006.285.17:46:36.05#ibcon#read 3, iclass 22, count 2 2006.285.17:46:36.05#ibcon#about to read 4, iclass 22, count 2 2006.285.17:46:36.05#ibcon#read 4, iclass 22, count 2 2006.285.17:46:36.05#ibcon#about to read 5, iclass 22, count 2 2006.285.17:46:36.05#ibcon#read 5, iclass 22, count 2 2006.285.17:46:36.05#ibcon#about to read 6, iclass 22, count 2 2006.285.17:46:36.05#ibcon#read 6, iclass 22, count 2 2006.285.17:46:36.05#ibcon#end of sib2, iclass 22, count 2 2006.285.17:46:36.05#ibcon#*after write, iclass 22, count 2 2006.285.17:46:36.05#ibcon#*before return 0, iclass 22, count 2 2006.285.17:46:36.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:46:36.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.17:46:36.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.17:46:36.05#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:36.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:46:36.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:46:36.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:46:36.16#ibcon#enter wrdev, iclass 22, count 0 2006.285.17:46:36.16#ibcon#first serial, iclass 22, count 0 2006.285.17:46:36.16#ibcon#enter sib2, iclass 22, count 0 2006.285.17:46:36.16#ibcon#flushed, iclass 22, count 0 2006.285.17:46:36.16#ibcon#about to write, iclass 22, count 0 2006.285.17:46:36.16#ibcon#wrote, iclass 22, count 0 2006.285.17:46:36.16#ibcon#about to read 3, iclass 22, count 0 2006.285.17:46:36.18#ibcon#read 3, iclass 22, count 0 2006.285.17:46:36.18#ibcon#about to read 4, iclass 22, count 0 2006.285.17:46:36.18#ibcon#read 4, iclass 22, count 0 2006.285.17:46:36.18#ibcon#about to read 5, iclass 22, count 0 2006.285.17:46:36.18#ibcon#read 5, iclass 22, count 0 2006.285.17:46:36.18#ibcon#about to read 6, iclass 22, count 0 2006.285.17:46:36.18#ibcon#read 6, iclass 22, count 0 2006.285.17:46:36.18#ibcon#end of sib2, iclass 22, count 0 2006.285.17:46:36.18#ibcon#*mode == 0, iclass 22, count 0 2006.285.17:46:36.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.17:46:36.18#ibcon#[27=USB\r\n] 2006.285.17:46:36.18#ibcon#*before write, iclass 22, count 0 2006.285.17:46:36.18#ibcon#enter sib2, iclass 22, count 0 2006.285.17:46:36.18#ibcon#flushed, iclass 22, count 0 2006.285.17:46:36.18#ibcon#about to write, iclass 22, count 0 2006.285.17:46:36.18#ibcon#wrote, iclass 22, count 0 2006.285.17:46:36.18#ibcon#about to read 3, iclass 22, count 0 2006.285.17:46:36.21#ibcon#read 3, iclass 22, count 0 2006.285.17:46:36.21#ibcon#about to read 4, iclass 22, count 0 2006.285.17:46:36.21#ibcon#read 4, iclass 22, count 0 2006.285.17:46:36.21#ibcon#about to read 5, iclass 22, count 0 2006.285.17:46:36.21#ibcon#read 5, iclass 22, count 0 2006.285.17:46:36.21#ibcon#about to read 6, iclass 22, count 0 2006.285.17:46:36.21#ibcon#read 6, iclass 22, count 0 2006.285.17:46:36.21#ibcon#end of sib2, iclass 22, count 0 2006.285.17:46:36.21#ibcon#*after write, iclass 22, count 0 2006.285.17:46:36.21#ibcon#*before return 0, iclass 22, count 0 2006.285.17:46:36.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:46:36.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.17:46:36.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.17:46:36.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.17:46:36.22$vck44/vblo=3,649.99 2006.285.17:46:36.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.17:46:36.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.17:46:36.22#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:36.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:46:36.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:46:36.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:46:36.22#ibcon#enter wrdev, iclass 24, count 0 2006.285.17:46:36.22#ibcon#first serial, iclass 24, count 0 2006.285.17:46:36.22#ibcon#enter sib2, iclass 24, count 0 2006.285.17:46:36.22#ibcon#flushed, iclass 24, count 0 2006.285.17:46:36.22#ibcon#about to write, iclass 24, count 0 2006.285.17:46:36.22#ibcon#wrote, iclass 24, count 0 2006.285.17:46:36.22#ibcon#about to read 3, iclass 24, count 0 2006.285.17:46:36.23#ibcon#read 3, iclass 24, count 0 2006.285.17:46:36.23#ibcon#about to read 4, iclass 24, count 0 2006.285.17:46:36.23#ibcon#read 4, iclass 24, count 0 2006.285.17:46:36.23#ibcon#about to read 5, iclass 24, count 0 2006.285.17:46:36.23#ibcon#read 5, iclass 24, count 0 2006.285.17:46:36.23#ibcon#about to read 6, iclass 24, count 0 2006.285.17:46:36.23#ibcon#read 6, iclass 24, count 0 2006.285.17:46:36.23#ibcon#end of sib2, iclass 24, count 0 2006.285.17:46:36.23#ibcon#*mode == 0, iclass 24, count 0 2006.285.17:46:36.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.17:46:36.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.17:46:36.23#ibcon#*before write, iclass 24, count 0 2006.285.17:46:36.23#ibcon#enter sib2, iclass 24, count 0 2006.285.17:46:36.23#ibcon#flushed, iclass 24, count 0 2006.285.17:46:36.23#ibcon#about to write, iclass 24, count 0 2006.285.17:46:36.23#ibcon#wrote, iclass 24, count 0 2006.285.17:46:36.24#ibcon#about to read 3, iclass 24, count 0 2006.285.17:46:36.27#ibcon#read 3, iclass 24, count 0 2006.285.17:46:36.27#ibcon#about to read 4, iclass 24, count 0 2006.285.17:46:36.27#ibcon#read 4, iclass 24, count 0 2006.285.17:46:36.27#ibcon#about to read 5, iclass 24, count 0 2006.285.17:46:36.27#ibcon#read 5, iclass 24, count 0 2006.285.17:46:36.27#ibcon#about to read 6, iclass 24, count 0 2006.285.17:46:36.27#ibcon#read 6, iclass 24, count 0 2006.285.17:46:36.27#ibcon#end of sib2, iclass 24, count 0 2006.285.17:46:36.27#ibcon#*after write, iclass 24, count 0 2006.285.17:46:36.27#ibcon#*before return 0, iclass 24, count 0 2006.285.17:46:36.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:46:36.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.17:46:36.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.17:46:36.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.17:46:36.28$vck44/vb=3,4 2006.285.17:46:36.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.17:46:36.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.17:46:36.28#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:36.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:46:36.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:46:36.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:46:36.32#ibcon#enter wrdev, iclass 26, count 2 2006.285.17:46:36.32#ibcon#first serial, iclass 26, count 2 2006.285.17:46:36.32#ibcon#enter sib2, iclass 26, count 2 2006.285.17:46:36.32#ibcon#flushed, iclass 26, count 2 2006.285.17:46:36.32#ibcon#about to write, iclass 26, count 2 2006.285.17:46:36.32#ibcon#wrote, iclass 26, count 2 2006.285.17:46:36.32#ibcon#about to read 3, iclass 26, count 2 2006.285.17:46:36.34#ibcon#read 3, iclass 26, count 2 2006.285.17:46:36.34#ibcon#about to read 4, iclass 26, count 2 2006.285.17:46:36.34#ibcon#read 4, iclass 26, count 2 2006.285.17:46:36.34#ibcon#about to read 5, iclass 26, count 2 2006.285.17:46:36.34#ibcon#read 5, iclass 26, count 2 2006.285.17:46:36.34#ibcon#about to read 6, iclass 26, count 2 2006.285.17:46:36.34#ibcon#read 6, iclass 26, count 2 2006.285.17:46:36.34#ibcon#end of sib2, iclass 26, count 2 2006.285.17:46:36.34#ibcon#*mode == 0, iclass 26, count 2 2006.285.17:46:36.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.17:46:36.34#ibcon#[27=AT03-04\r\n] 2006.285.17:46:36.34#ibcon#*before write, iclass 26, count 2 2006.285.17:46:36.34#ibcon#enter sib2, iclass 26, count 2 2006.285.17:46:36.34#ibcon#flushed, iclass 26, count 2 2006.285.17:46:36.34#ibcon#about to write, iclass 26, count 2 2006.285.17:46:36.34#ibcon#wrote, iclass 26, count 2 2006.285.17:46:36.34#ibcon#about to read 3, iclass 26, count 2 2006.285.17:46:36.37#ibcon#read 3, iclass 26, count 2 2006.285.17:46:36.37#ibcon#about to read 4, iclass 26, count 2 2006.285.17:46:36.37#ibcon#read 4, iclass 26, count 2 2006.285.17:46:36.37#ibcon#about to read 5, iclass 26, count 2 2006.285.17:46:36.37#ibcon#read 5, iclass 26, count 2 2006.285.17:46:36.37#ibcon#about to read 6, iclass 26, count 2 2006.285.17:46:36.37#ibcon#read 6, iclass 26, count 2 2006.285.17:46:36.37#ibcon#end of sib2, iclass 26, count 2 2006.285.17:46:36.37#ibcon#*after write, iclass 26, count 2 2006.285.17:46:36.37#ibcon#*before return 0, iclass 26, count 2 2006.285.17:46:36.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:46:36.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.17:46:36.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.17:46:36.37#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:36.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:46:36.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:46:36.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:46:36.49#ibcon#enter wrdev, iclass 26, count 0 2006.285.17:46:36.49#ibcon#first serial, iclass 26, count 0 2006.285.17:46:36.49#ibcon#enter sib2, iclass 26, count 0 2006.285.17:46:36.49#ibcon#flushed, iclass 26, count 0 2006.285.17:46:36.49#ibcon#about to write, iclass 26, count 0 2006.285.17:46:36.49#ibcon#wrote, iclass 26, count 0 2006.285.17:46:36.49#ibcon#about to read 3, iclass 26, count 0 2006.285.17:46:36.51#ibcon#read 3, iclass 26, count 0 2006.285.17:46:36.51#ibcon#about to read 4, iclass 26, count 0 2006.285.17:46:36.51#ibcon#read 4, iclass 26, count 0 2006.285.17:46:36.51#ibcon#about to read 5, iclass 26, count 0 2006.285.17:46:36.51#ibcon#read 5, iclass 26, count 0 2006.285.17:46:36.51#ibcon#about to read 6, iclass 26, count 0 2006.285.17:46:36.51#ibcon#read 6, iclass 26, count 0 2006.285.17:46:36.51#ibcon#end of sib2, iclass 26, count 0 2006.285.17:46:36.51#ibcon#*mode == 0, iclass 26, count 0 2006.285.17:46:36.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.17:46:36.51#ibcon#[27=USB\r\n] 2006.285.17:46:36.51#ibcon#*before write, iclass 26, count 0 2006.285.17:46:36.51#ibcon#enter sib2, iclass 26, count 0 2006.285.17:46:36.51#ibcon#flushed, iclass 26, count 0 2006.285.17:46:36.51#ibcon#about to write, iclass 26, count 0 2006.285.17:46:36.51#ibcon#wrote, iclass 26, count 0 2006.285.17:46:36.51#ibcon#about to read 3, iclass 26, count 0 2006.285.17:46:36.54#ibcon#read 3, iclass 26, count 0 2006.285.17:46:36.54#ibcon#about to read 4, iclass 26, count 0 2006.285.17:46:36.54#ibcon#read 4, iclass 26, count 0 2006.285.17:46:36.54#ibcon#about to read 5, iclass 26, count 0 2006.285.17:46:36.54#ibcon#read 5, iclass 26, count 0 2006.285.17:46:36.54#ibcon#about to read 6, iclass 26, count 0 2006.285.17:46:36.54#ibcon#read 6, iclass 26, count 0 2006.285.17:46:36.54#ibcon#end of sib2, iclass 26, count 0 2006.285.17:46:36.54#ibcon#*after write, iclass 26, count 0 2006.285.17:46:36.54#ibcon#*before return 0, iclass 26, count 0 2006.285.17:46:36.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:46:36.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.17:46:36.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.17:46:36.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.17:46:36.55$vck44/vblo=4,679.99 2006.285.17:46:36.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.17:46:36.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.17:46:36.55#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:36.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:46:36.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:46:36.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:46:36.55#ibcon#enter wrdev, iclass 28, count 0 2006.285.17:46:36.55#ibcon#first serial, iclass 28, count 0 2006.285.17:46:36.55#ibcon#enter sib2, iclass 28, count 0 2006.285.17:46:36.55#ibcon#flushed, iclass 28, count 0 2006.285.17:46:36.55#ibcon#about to write, iclass 28, count 0 2006.285.17:46:36.55#ibcon#wrote, iclass 28, count 0 2006.285.17:46:36.55#ibcon#about to read 3, iclass 28, count 0 2006.285.17:46:36.56#ibcon#read 3, iclass 28, count 0 2006.285.17:46:36.56#ibcon#about to read 4, iclass 28, count 0 2006.285.17:46:36.56#ibcon#read 4, iclass 28, count 0 2006.285.17:46:36.56#ibcon#about to read 5, iclass 28, count 0 2006.285.17:46:36.56#ibcon#read 5, iclass 28, count 0 2006.285.17:46:36.56#ibcon#about to read 6, iclass 28, count 0 2006.285.17:46:36.56#ibcon#read 6, iclass 28, count 0 2006.285.17:46:36.56#ibcon#end of sib2, iclass 28, count 0 2006.285.17:46:36.56#ibcon#*mode == 0, iclass 28, count 0 2006.285.17:46:36.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.17:46:36.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.17:46:36.56#ibcon#*before write, iclass 28, count 0 2006.285.17:46:36.56#ibcon#enter sib2, iclass 28, count 0 2006.285.17:46:36.56#ibcon#flushed, iclass 28, count 0 2006.285.17:46:36.56#ibcon#about to write, iclass 28, count 0 2006.285.17:46:36.56#ibcon#wrote, iclass 28, count 0 2006.285.17:46:36.57#ibcon#about to read 3, iclass 28, count 0 2006.285.17:46:36.60#ibcon#read 3, iclass 28, count 0 2006.285.17:46:36.60#ibcon#about to read 4, iclass 28, count 0 2006.285.17:46:36.60#ibcon#read 4, iclass 28, count 0 2006.285.17:46:36.60#ibcon#about to read 5, iclass 28, count 0 2006.285.17:46:36.60#ibcon#read 5, iclass 28, count 0 2006.285.17:46:36.60#ibcon#about to read 6, iclass 28, count 0 2006.285.17:46:36.60#ibcon#read 6, iclass 28, count 0 2006.285.17:46:36.60#ibcon#end of sib2, iclass 28, count 0 2006.285.17:46:36.60#ibcon#*after write, iclass 28, count 0 2006.285.17:46:36.60#ibcon#*before return 0, iclass 28, count 0 2006.285.17:46:36.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:46:36.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.17:46:36.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.17:46:36.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.17:46:36.61$vck44/vb=4,5 2006.285.17:46:36.61#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.17:46:36.61#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.17:46:36.61#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:36.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:46:36.61#abcon#<5=/00 0.1 1.0 16.38 991014.5\r\n> 2006.285.17:46:36.63#abcon#{5=INTERFACE CLEAR} 2006.285.17:46:36.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:46:36.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:46:36.65#ibcon#enter wrdev, iclass 31, count 2 2006.285.17:46:36.65#ibcon#first serial, iclass 31, count 2 2006.285.17:46:36.65#ibcon#enter sib2, iclass 31, count 2 2006.285.17:46:36.65#ibcon#flushed, iclass 31, count 2 2006.285.17:46:36.65#ibcon#about to write, iclass 31, count 2 2006.285.17:46:36.65#ibcon#wrote, iclass 31, count 2 2006.285.17:46:36.65#ibcon#about to read 3, iclass 31, count 2 2006.285.17:46:36.67#ibcon#read 3, iclass 31, count 2 2006.285.17:46:36.67#ibcon#about to read 4, iclass 31, count 2 2006.285.17:46:36.67#ibcon#read 4, iclass 31, count 2 2006.285.17:46:36.67#ibcon#about to read 5, iclass 31, count 2 2006.285.17:46:36.67#ibcon#read 5, iclass 31, count 2 2006.285.17:46:36.67#ibcon#about to read 6, iclass 31, count 2 2006.285.17:46:36.67#ibcon#read 6, iclass 31, count 2 2006.285.17:46:36.67#ibcon#end of sib2, iclass 31, count 2 2006.285.17:46:36.67#ibcon#*mode == 0, iclass 31, count 2 2006.285.17:46:36.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.17:46:36.67#ibcon#[27=AT04-05\r\n] 2006.285.17:46:36.67#ibcon#*before write, iclass 31, count 2 2006.285.17:46:36.67#ibcon#enter sib2, iclass 31, count 2 2006.285.17:46:36.67#ibcon#flushed, iclass 31, count 2 2006.285.17:46:36.67#ibcon#about to write, iclass 31, count 2 2006.285.17:46:36.67#ibcon#wrote, iclass 31, count 2 2006.285.17:46:36.67#ibcon#about to read 3, iclass 31, count 2 2006.285.17:46:36.69#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:46:36.70#ibcon#read 3, iclass 31, count 2 2006.285.17:46:36.70#ibcon#about to read 4, iclass 31, count 2 2006.285.17:46:36.70#ibcon#read 4, iclass 31, count 2 2006.285.17:46:36.70#ibcon#about to read 5, iclass 31, count 2 2006.285.17:46:36.70#ibcon#read 5, iclass 31, count 2 2006.285.17:46:36.70#ibcon#about to read 6, iclass 31, count 2 2006.285.17:46:36.70#ibcon#read 6, iclass 31, count 2 2006.285.17:46:36.70#ibcon#end of sib2, iclass 31, count 2 2006.285.17:46:36.70#ibcon#*after write, iclass 31, count 2 2006.285.17:46:36.70#ibcon#*before return 0, iclass 31, count 2 2006.285.17:46:36.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:46:36.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:46:36.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.17:46:36.70#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:36.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:46:36.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:46:36.93#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:46:36.93#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:46:36.93#ibcon#first serial, iclass 31, count 0 2006.285.17:46:36.93#ibcon#enter sib2, iclass 31, count 0 2006.285.17:46:36.93#ibcon#flushed, iclass 31, count 0 2006.285.17:46:36.93#ibcon#about to write, iclass 31, count 0 2006.285.17:46:36.93#ibcon#wrote, iclass 31, count 0 2006.285.17:46:36.93#ibcon#about to read 3, iclass 31, count 0 2006.285.17:46:36.94#ibcon#read 3, iclass 31, count 0 2006.285.17:46:36.94#ibcon#about to read 4, iclass 31, count 0 2006.285.17:46:36.94#ibcon#read 4, iclass 31, count 0 2006.285.17:46:36.94#ibcon#about to read 5, iclass 31, count 0 2006.285.17:46:36.94#ibcon#read 5, iclass 31, count 0 2006.285.17:46:36.94#ibcon#about to read 6, iclass 31, count 0 2006.285.17:46:36.94#ibcon#read 6, iclass 31, count 0 2006.285.17:46:36.94#ibcon#end of sib2, iclass 31, count 0 2006.285.17:46:36.94#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:46:36.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:46:36.94#ibcon#[27=USB\r\n] 2006.285.17:46:36.94#ibcon#*before write, iclass 31, count 0 2006.285.17:46:36.94#ibcon#enter sib2, iclass 31, count 0 2006.285.17:46:36.94#ibcon#flushed, iclass 31, count 0 2006.285.17:46:36.94#ibcon#about to write, iclass 31, count 0 2006.285.17:46:36.95#ibcon#wrote, iclass 31, count 0 2006.285.17:46:36.95#ibcon#about to read 3, iclass 31, count 0 2006.285.17:46:36.97#ibcon#read 3, iclass 31, count 0 2006.285.17:46:36.97#ibcon#about to read 4, iclass 31, count 0 2006.285.17:46:36.97#ibcon#read 4, iclass 31, count 0 2006.285.17:46:36.97#ibcon#about to read 5, iclass 31, count 0 2006.285.17:46:36.97#ibcon#read 5, iclass 31, count 0 2006.285.17:46:36.97#ibcon#about to read 6, iclass 31, count 0 2006.285.17:46:36.97#ibcon#read 6, iclass 31, count 0 2006.285.17:46:36.97#ibcon#end of sib2, iclass 31, count 0 2006.285.17:46:36.97#ibcon#*after write, iclass 31, count 0 2006.285.17:46:36.97#ibcon#*before return 0, iclass 31, count 0 2006.285.17:46:36.97#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:46:36.97#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:46:36.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:46:36.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:46:36.98$vck44/vblo=5,709.99 2006.285.17:46:36.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.17:46:36.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.17:46:36.98#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:36.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:46:36.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:46:36.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:46:36.98#ibcon#enter wrdev, iclass 36, count 0 2006.285.17:46:36.98#ibcon#first serial, iclass 36, count 0 2006.285.17:46:36.98#ibcon#enter sib2, iclass 36, count 0 2006.285.17:46:36.98#ibcon#flushed, iclass 36, count 0 2006.285.17:46:36.98#ibcon#about to write, iclass 36, count 0 2006.285.17:46:36.98#ibcon#wrote, iclass 36, count 0 2006.285.17:46:36.98#ibcon#about to read 3, iclass 36, count 0 2006.285.17:46:36.99#ibcon#read 3, iclass 36, count 0 2006.285.17:46:36.99#ibcon#about to read 4, iclass 36, count 0 2006.285.17:46:36.99#ibcon#read 4, iclass 36, count 0 2006.285.17:46:36.99#ibcon#about to read 5, iclass 36, count 0 2006.285.17:46:36.99#ibcon#read 5, iclass 36, count 0 2006.285.17:46:36.99#ibcon#about to read 6, iclass 36, count 0 2006.285.17:46:36.99#ibcon#read 6, iclass 36, count 0 2006.285.17:46:36.99#ibcon#end of sib2, iclass 36, count 0 2006.285.17:46:36.99#ibcon#*mode == 0, iclass 36, count 0 2006.285.17:46:36.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.17:46:36.99#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.17:46:36.99#ibcon#*before write, iclass 36, count 0 2006.285.17:46:36.99#ibcon#enter sib2, iclass 36, count 0 2006.285.17:46:36.99#ibcon#flushed, iclass 36, count 0 2006.285.17:46:36.99#ibcon#about to write, iclass 36, count 0 2006.285.17:46:37.00#ibcon#wrote, iclass 36, count 0 2006.285.17:46:37.00#ibcon#about to read 3, iclass 36, count 0 2006.285.17:46:37.03#ibcon#read 3, iclass 36, count 0 2006.285.17:46:37.03#ibcon#about to read 4, iclass 36, count 0 2006.285.17:46:37.03#ibcon#read 4, iclass 36, count 0 2006.285.17:46:37.03#ibcon#about to read 5, iclass 36, count 0 2006.285.17:46:37.03#ibcon#read 5, iclass 36, count 0 2006.285.17:46:37.03#ibcon#about to read 6, iclass 36, count 0 2006.285.17:46:37.03#ibcon#read 6, iclass 36, count 0 2006.285.17:46:37.03#ibcon#end of sib2, iclass 36, count 0 2006.285.17:46:37.03#ibcon#*after write, iclass 36, count 0 2006.285.17:46:37.03#ibcon#*before return 0, iclass 36, count 0 2006.285.17:46:37.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:46:37.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.17:46:37.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.17:46:37.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.17:46:37.04$vck44/vb=5,4 2006.285.17:46:37.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.17:46:37.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.17:46:37.04#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:37.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:46:37.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:46:37.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:46:37.08#ibcon#enter wrdev, iclass 38, count 2 2006.285.17:46:37.08#ibcon#first serial, iclass 38, count 2 2006.285.17:46:37.08#ibcon#enter sib2, iclass 38, count 2 2006.285.17:46:37.08#ibcon#flushed, iclass 38, count 2 2006.285.17:46:37.08#ibcon#about to write, iclass 38, count 2 2006.285.17:46:37.08#ibcon#wrote, iclass 38, count 2 2006.285.17:46:37.08#ibcon#about to read 3, iclass 38, count 2 2006.285.17:46:37.10#ibcon#read 3, iclass 38, count 2 2006.285.17:46:37.10#ibcon#about to read 4, iclass 38, count 2 2006.285.17:46:37.10#ibcon#read 4, iclass 38, count 2 2006.285.17:46:37.10#ibcon#about to read 5, iclass 38, count 2 2006.285.17:46:37.10#ibcon#read 5, iclass 38, count 2 2006.285.17:46:37.10#ibcon#about to read 6, iclass 38, count 2 2006.285.17:46:37.10#ibcon#read 6, iclass 38, count 2 2006.285.17:46:37.10#ibcon#end of sib2, iclass 38, count 2 2006.285.17:46:37.10#ibcon#*mode == 0, iclass 38, count 2 2006.285.17:46:37.10#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.17:46:37.10#ibcon#[27=AT05-04\r\n] 2006.285.17:46:37.10#ibcon#*before write, iclass 38, count 2 2006.285.17:46:37.10#ibcon#enter sib2, iclass 38, count 2 2006.285.17:46:37.10#ibcon#flushed, iclass 38, count 2 2006.285.17:46:37.10#ibcon#about to write, iclass 38, count 2 2006.285.17:46:37.10#ibcon#wrote, iclass 38, count 2 2006.285.17:46:37.11#ibcon#about to read 3, iclass 38, count 2 2006.285.17:46:37.13#ibcon#read 3, iclass 38, count 2 2006.285.17:46:37.13#ibcon#about to read 4, iclass 38, count 2 2006.285.17:46:37.13#ibcon#read 4, iclass 38, count 2 2006.285.17:46:37.13#ibcon#about to read 5, iclass 38, count 2 2006.285.17:46:37.13#ibcon#read 5, iclass 38, count 2 2006.285.17:46:37.13#ibcon#about to read 6, iclass 38, count 2 2006.285.17:46:37.13#ibcon#read 6, iclass 38, count 2 2006.285.17:46:37.13#ibcon#end of sib2, iclass 38, count 2 2006.285.17:46:37.13#ibcon#*after write, iclass 38, count 2 2006.285.17:46:37.13#ibcon#*before return 0, iclass 38, count 2 2006.285.17:46:37.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:46:37.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.17:46:37.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.17:46:37.13#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:37.14#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:46:37.24#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:46:37.24#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:46:37.24#ibcon#enter wrdev, iclass 38, count 0 2006.285.17:46:37.24#ibcon#first serial, iclass 38, count 0 2006.285.17:46:37.24#ibcon#enter sib2, iclass 38, count 0 2006.285.17:46:37.24#ibcon#flushed, iclass 38, count 0 2006.285.17:46:37.24#ibcon#about to write, iclass 38, count 0 2006.285.17:46:37.24#ibcon#wrote, iclass 38, count 0 2006.285.17:46:37.24#ibcon#about to read 3, iclass 38, count 0 2006.285.17:46:37.26#ibcon#read 3, iclass 38, count 0 2006.285.17:46:37.26#ibcon#about to read 4, iclass 38, count 0 2006.285.17:46:37.26#ibcon#read 4, iclass 38, count 0 2006.285.17:46:37.26#ibcon#about to read 5, iclass 38, count 0 2006.285.17:46:37.26#ibcon#read 5, iclass 38, count 0 2006.285.17:46:37.26#ibcon#about to read 6, iclass 38, count 0 2006.285.17:46:37.26#ibcon#read 6, iclass 38, count 0 2006.285.17:46:37.26#ibcon#end of sib2, iclass 38, count 0 2006.285.17:46:37.26#ibcon#*mode == 0, iclass 38, count 0 2006.285.17:46:37.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.17:46:37.26#ibcon#[27=USB\r\n] 2006.285.17:46:37.26#ibcon#*before write, iclass 38, count 0 2006.285.17:46:37.26#ibcon#enter sib2, iclass 38, count 0 2006.285.17:46:37.26#ibcon#flushed, iclass 38, count 0 2006.285.17:46:37.26#ibcon#about to write, iclass 38, count 0 2006.285.17:46:37.26#ibcon#wrote, iclass 38, count 0 2006.285.17:46:37.26#ibcon#about to read 3, iclass 38, count 0 2006.285.17:46:37.29#ibcon#read 3, iclass 38, count 0 2006.285.17:46:37.29#ibcon#about to read 4, iclass 38, count 0 2006.285.17:46:37.29#ibcon#read 4, iclass 38, count 0 2006.285.17:46:37.29#ibcon#about to read 5, iclass 38, count 0 2006.285.17:46:37.29#ibcon#read 5, iclass 38, count 0 2006.285.17:46:37.29#ibcon#about to read 6, iclass 38, count 0 2006.285.17:46:37.29#ibcon#read 6, iclass 38, count 0 2006.285.17:46:37.29#ibcon#end of sib2, iclass 38, count 0 2006.285.17:46:37.29#ibcon#*after write, iclass 38, count 0 2006.285.17:46:37.29#ibcon#*before return 0, iclass 38, count 0 2006.285.17:46:37.29#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:46:37.29#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.17:46:37.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.17:46:37.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.17:46:37.30$vck44/vblo=6,719.99 2006.285.17:46:37.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.17:46:37.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.17:46:37.30#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:37.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:46:37.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:46:37.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:46:37.30#ibcon#enter wrdev, iclass 40, count 0 2006.285.17:46:37.30#ibcon#first serial, iclass 40, count 0 2006.285.17:46:37.30#ibcon#enter sib2, iclass 40, count 0 2006.285.17:46:37.30#ibcon#flushed, iclass 40, count 0 2006.285.17:46:37.30#ibcon#about to write, iclass 40, count 0 2006.285.17:46:37.30#ibcon#wrote, iclass 40, count 0 2006.285.17:46:37.30#ibcon#about to read 3, iclass 40, count 0 2006.285.17:46:37.31#ibcon#read 3, iclass 40, count 0 2006.285.17:46:37.31#ibcon#about to read 4, iclass 40, count 0 2006.285.17:46:37.31#ibcon#read 4, iclass 40, count 0 2006.285.17:46:37.31#ibcon#about to read 5, iclass 40, count 0 2006.285.17:46:37.31#ibcon#read 5, iclass 40, count 0 2006.285.17:46:37.31#ibcon#about to read 6, iclass 40, count 0 2006.285.17:46:37.31#ibcon#read 6, iclass 40, count 0 2006.285.17:46:37.31#ibcon#end of sib2, iclass 40, count 0 2006.285.17:46:37.31#ibcon#*mode == 0, iclass 40, count 0 2006.285.17:46:37.31#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.17:46:37.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.17:46:37.31#ibcon#*before write, iclass 40, count 0 2006.285.17:46:37.31#ibcon#enter sib2, iclass 40, count 0 2006.285.17:46:37.31#ibcon#flushed, iclass 40, count 0 2006.285.17:46:37.31#ibcon#about to write, iclass 40, count 0 2006.285.17:46:37.31#ibcon#wrote, iclass 40, count 0 2006.285.17:46:37.31#ibcon#about to read 3, iclass 40, count 0 2006.285.17:46:37.35#ibcon#read 3, iclass 40, count 0 2006.285.17:46:37.35#ibcon#about to read 4, iclass 40, count 0 2006.285.17:46:37.35#ibcon#read 4, iclass 40, count 0 2006.285.17:46:37.35#ibcon#about to read 5, iclass 40, count 0 2006.285.17:46:37.35#ibcon#read 5, iclass 40, count 0 2006.285.17:46:37.35#ibcon#about to read 6, iclass 40, count 0 2006.285.17:46:37.35#ibcon#read 6, iclass 40, count 0 2006.285.17:46:37.35#ibcon#end of sib2, iclass 40, count 0 2006.285.17:46:37.35#ibcon#*after write, iclass 40, count 0 2006.285.17:46:37.35#ibcon#*before return 0, iclass 40, count 0 2006.285.17:46:37.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:46:37.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.17:46:37.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.17:46:37.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.17:46:37.36$vck44/vb=6,3 2006.285.17:46:37.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.17:46:37.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.17:46:37.36#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:37.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:46:37.40#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:46:37.40#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:46:37.40#ibcon#enter wrdev, iclass 4, count 2 2006.285.17:46:37.40#ibcon#first serial, iclass 4, count 2 2006.285.17:46:37.40#ibcon#enter sib2, iclass 4, count 2 2006.285.17:46:37.40#ibcon#flushed, iclass 4, count 2 2006.285.17:46:37.40#ibcon#about to write, iclass 4, count 2 2006.285.17:46:37.40#ibcon#wrote, iclass 4, count 2 2006.285.17:46:37.40#ibcon#about to read 3, iclass 4, count 2 2006.285.17:46:37.42#ibcon#read 3, iclass 4, count 2 2006.285.17:46:37.42#ibcon#about to read 4, iclass 4, count 2 2006.285.17:46:37.42#ibcon#read 4, iclass 4, count 2 2006.285.17:46:37.42#ibcon#about to read 5, iclass 4, count 2 2006.285.17:46:37.42#ibcon#read 5, iclass 4, count 2 2006.285.17:46:37.42#ibcon#about to read 6, iclass 4, count 2 2006.285.17:46:37.42#ibcon#read 6, iclass 4, count 2 2006.285.17:46:37.42#ibcon#end of sib2, iclass 4, count 2 2006.285.17:46:37.42#ibcon#*mode == 0, iclass 4, count 2 2006.285.17:46:37.42#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.17:46:37.42#ibcon#[27=AT06-03\r\n] 2006.285.17:46:37.42#ibcon#*before write, iclass 4, count 2 2006.285.17:46:37.42#ibcon#enter sib2, iclass 4, count 2 2006.285.17:46:37.42#ibcon#flushed, iclass 4, count 2 2006.285.17:46:37.42#ibcon#about to write, iclass 4, count 2 2006.285.17:46:37.42#ibcon#wrote, iclass 4, count 2 2006.285.17:46:37.42#ibcon#about to read 3, iclass 4, count 2 2006.285.17:46:37.45#ibcon#read 3, iclass 4, count 2 2006.285.17:46:37.45#ibcon#about to read 4, iclass 4, count 2 2006.285.17:46:37.45#ibcon#read 4, iclass 4, count 2 2006.285.17:46:37.45#ibcon#about to read 5, iclass 4, count 2 2006.285.17:46:37.45#ibcon#read 5, iclass 4, count 2 2006.285.17:46:37.45#ibcon#about to read 6, iclass 4, count 2 2006.285.17:46:37.45#ibcon#read 6, iclass 4, count 2 2006.285.17:46:37.45#ibcon#end of sib2, iclass 4, count 2 2006.285.17:46:37.45#ibcon#*after write, iclass 4, count 2 2006.285.17:46:37.45#ibcon#*before return 0, iclass 4, count 2 2006.285.17:46:37.45#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:46:37.45#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:46:37.45#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.17:46:37.45#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:37.45#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:46:37.57#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:46:37.57#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:46:37.57#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:46:37.57#ibcon#first serial, iclass 4, count 0 2006.285.17:46:37.57#ibcon#enter sib2, iclass 4, count 0 2006.285.17:46:37.57#ibcon#flushed, iclass 4, count 0 2006.285.17:46:37.57#ibcon#about to write, iclass 4, count 0 2006.285.17:46:37.57#ibcon#wrote, iclass 4, count 0 2006.285.17:46:37.57#ibcon#about to read 3, iclass 4, count 0 2006.285.17:46:37.59#ibcon#read 3, iclass 4, count 0 2006.285.17:46:37.59#ibcon#about to read 4, iclass 4, count 0 2006.285.17:46:37.59#ibcon#read 4, iclass 4, count 0 2006.285.17:46:37.59#ibcon#about to read 5, iclass 4, count 0 2006.285.17:46:37.59#ibcon#read 5, iclass 4, count 0 2006.285.17:46:37.59#ibcon#about to read 6, iclass 4, count 0 2006.285.17:46:37.59#ibcon#read 6, iclass 4, count 0 2006.285.17:46:37.59#ibcon#end of sib2, iclass 4, count 0 2006.285.17:46:37.59#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:46:37.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:46:37.59#ibcon#[27=USB\r\n] 2006.285.17:46:37.59#ibcon#*before write, iclass 4, count 0 2006.285.17:46:37.59#ibcon#enter sib2, iclass 4, count 0 2006.285.17:46:37.59#ibcon#flushed, iclass 4, count 0 2006.285.17:46:37.59#ibcon#about to write, iclass 4, count 0 2006.285.17:46:37.59#ibcon#wrote, iclass 4, count 0 2006.285.17:46:37.59#ibcon#about to read 3, iclass 4, count 0 2006.285.17:46:37.62#ibcon#read 3, iclass 4, count 0 2006.285.17:46:37.62#ibcon#about to read 4, iclass 4, count 0 2006.285.17:46:37.62#ibcon#read 4, iclass 4, count 0 2006.285.17:46:37.62#ibcon#about to read 5, iclass 4, count 0 2006.285.17:46:37.62#ibcon#read 5, iclass 4, count 0 2006.285.17:46:37.62#ibcon#about to read 6, iclass 4, count 0 2006.285.17:46:37.62#ibcon#read 6, iclass 4, count 0 2006.285.17:46:37.62#ibcon#end of sib2, iclass 4, count 0 2006.285.17:46:37.62#ibcon#*after write, iclass 4, count 0 2006.285.17:46:37.62#ibcon#*before return 0, iclass 4, count 0 2006.285.17:46:37.62#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:46:37.62#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:46:37.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:46:37.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:46:37.63$vck44/vblo=7,734.99 2006.285.17:46:37.63#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.17:46:37.63#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.17:46:37.63#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:37.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:46:37.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:46:37.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:46:37.63#ibcon#enter wrdev, iclass 6, count 0 2006.285.17:46:37.63#ibcon#first serial, iclass 6, count 0 2006.285.17:46:37.63#ibcon#enter sib2, iclass 6, count 0 2006.285.17:46:37.63#ibcon#flushed, iclass 6, count 0 2006.285.17:46:37.63#ibcon#about to write, iclass 6, count 0 2006.285.17:46:37.63#ibcon#wrote, iclass 6, count 0 2006.285.17:46:37.63#ibcon#about to read 3, iclass 6, count 0 2006.285.17:46:37.64#ibcon#read 3, iclass 6, count 0 2006.285.17:46:37.64#ibcon#about to read 4, iclass 6, count 0 2006.285.17:46:37.64#ibcon#read 4, iclass 6, count 0 2006.285.17:46:37.64#ibcon#about to read 5, iclass 6, count 0 2006.285.17:46:37.64#ibcon#read 5, iclass 6, count 0 2006.285.17:46:37.64#ibcon#about to read 6, iclass 6, count 0 2006.285.17:46:37.64#ibcon#read 6, iclass 6, count 0 2006.285.17:46:37.64#ibcon#end of sib2, iclass 6, count 0 2006.285.17:46:37.64#ibcon#*mode == 0, iclass 6, count 0 2006.285.17:46:37.64#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.17:46:37.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.17:46:37.64#ibcon#*before write, iclass 6, count 0 2006.285.17:46:37.64#ibcon#enter sib2, iclass 6, count 0 2006.285.17:46:37.64#ibcon#flushed, iclass 6, count 0 2006.285.17:46:37.64#ibcon#about to write, iclass 6, count 0 2006.285.17:46:37.64#ibcon#wrote, iclass 6, count 0 2006.285.17:46:37.65#ibcon#about to read 3, iclass 6, count 0 2006.285.17:46:37.68#ibcon#read 3, iclass 6, count 0 2006.285.17:46:37.68#ibcon#about to read 4, iclass 6, count 0 2006.285.17:46:37.68#ibcon#read 4, iclass 6, count 0 2006.285.17:46:37.68#ibcon#about to read 5, iclass 6, count 0 2006.285.17:46:37.68#ibcon#read 5, iclass 6, count 0 2006.285.17:46:37.68#ibcon#about to read 6, iclass 6, count 0 2006.285.17:46:37.68#ibcon#read 6, iclass 6, count 0 2006.285.17:46:37.68#ibcon#end of sib2, iclass 6, count 0 2006.285.17:46:37.68#ibcon#*after write, iclass 6, count 0 2006.285.17:46:37.68#ibcon#*before return 0, iclass 6, count 0 2006.285.17:46:37.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:46:37.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.17:46:37.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.17:46:37.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.17:46:37.69$vck44/vb=7,4 2006.285.17:46:37.69#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.17:46:37.69#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.17:46:37.69#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:37.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:46:37.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:46:37.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:46:37.73#ibcon#enter wrdev, iclass 10, count 2 2006.285.17:46:37.73#ibcon#first serial, iclass 10, count 2 2006.285.17:46:37.73#ibcon#enter sib2, iclass 10, count 2 2006.285.17:46:37.73#ibcon#flushed, iclass 10, count 2 2006.285.17:46:37.73#ibcon#about to write, iclass 10, count 2 2006.285.17:46:37.73#ibcon#wrote, iclass 10, count 2 2006.285.17:46:37.73#ibcon#about to read 3, iclass 10, count 2 2006.285.17:46:37.75#ibcon#read 3, iclass 10, count 2 2006.285.17:46:37.88#ibcon#about to read 4, iclass 10, count 2 2006.285.17:46:37.88#ibcon#read 4, iclass 10, count 2 2006.285.17:46:37.88#ibcon#about to read 5, iclass 10, count 2 2006.285.17:46:37.88#ibcon#read 5, iclass 10, count 2 2006.285.17:46:37.88#ibcon#about to read 6, iclass 10, count 2 2006.285.17:46:37.88#ibcon#read 6, iclass 10, count 2 2006.285.17:46:37.88#ibcon#end of sib2, iclass 10, count 2 2006.285.17:46:37.88#ibcon#*mode == 0, iclass 10, count 2 2006.285.17:46:37.88#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.17:46:37.88#ibcon#[27=AT07-04\r\n] 2006.285.17:46:37.88#ibcon#*before write, iclass 10, count 2 2006.285.17:46:37.88#ibcon#enter sib2, iclass 10, count 2 2006.285.17:46:37.88#ibcon#flushed, iclass 10, count 2 2006.285.17:46:37.88#ibcon#about to write, iclass 10, count 2 2006.285.17:46:37.88#ibcon#wrote, iclass 10, count 2 2006.285.17:46:37.88#ibcon#about to read 3, iclass 10, count 2 2006.285.17:46:37.91#ibcon#read 3, iclass 10, count 2 2006.285.17:46:37.91#ibcon#about to read 4, iclass 10, count 2 2006.285.17:46:37.91#ibcon#read 4, iclass 10, count 2 2006.285.17:46:37.91#ibcon#about to read 5, iclass 10, count 2 2006.285.17:46:37.91#ibcon#read 5, iclass 10, count 2 2006.285.17:46:37.91#ibcon#about to read 6, iclass 10, count 2 2006.285.17:46:37.91#ibcon#read 6, iclass 10, count 2 2006.285.17:46:37.91#ibcon#end of sib2, iclass 10, count 2 2006.285.17:46:37.91#ibcon#*after write, iclass 10, count 2 2006.285.17:46:37.91#ibcon#*before return 0, iclass 10, count 2 2006.285.17:46:37.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:46:37.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.17:46:37.91#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.17:46:37.91#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:37.92#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:46:38.02#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:46:38.02#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:46:38.02#ibcon#enter wrdev, iclass 10, count 0 2006.285.17:46:38.02#ibcon#first serial, iclass 10, count 0 2006.285.17:46:38.02#ibcon#enter sib2, iclass 10, count 0 2006.285.17:46:38.02#ibcon#flushed, iclass 10, count 0 2006.285.17:46:38.02#ibcon#about to write, iclass 10, count 0 2006.285.17:46:38.02#ibcon#wrote, iclass 10, count 0 2006.285.17:46:38.02#ibcon#about to read 3, iclass 10, count 0 2006.285.17:46:38.04#ibcon#read 3, iclass 10, count 0 2006.285.17:46:38.04#ibcon#about to read 4, iclass 10, count 0 2006.285.17:46:38.04#ibcon#read 4, iclass 10, count 0 2006.285.17:46:38.04#ibcon#about to read 5, iclass 10, count 0 2006.285.17:46:38.04#ibcon#read 5, iclass 10, count 0 2006.285.17:46:38.04#ibcon#about to read 6, iclass 10, count 0 2006.285.17:46:38.04#ibcon#read 6, iclass 10, count 0 2006.285.17:46:38.04#ibcon#end of sib2, iclass 10, count 0 2006.285.17:46:38.04#ibcon#*mode == 0, iclass 10, count 0 2006.285.17:46:38.04#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.17:46:38.04#ibcon#[27=USB\r\n] 2006.285.17:46:38.04#ibcon#*before write, iclass 10, count 0 2006.285.17:46:38.04#ibcon#enter sib2, iclass 10, count 0 2006.285.17:46:38.04#ibcon#flushed, iclass 10, count 0 2006.285.17:46:38.04#ibcon#about to write, iclass 10, count 0 2006.285.17:46:38.05#ibcon#wrote, iclass 10, count 0 2006.285.17:46:38.05#ibcon#about to read 3, iclass 10, count 0 2006.285.17:46:38.07#ibcon#read 3, iclass 10, count 0 2006.285.17:46:38.07#ibcon#about to read 4, iclass 10, count 0 2006.285.17:46:38.07#ibcon#read 4, iclass 10, count 0 2006.285.17:46:38.07#ibcon#about to read 5, iclass 10, count 0 2006.285.17:46:38.07#ibcon#read 5, iclass 10, count 0 2006.285.17:46:38.07#ibcon#about to read 6, iclass 10, count 0 2006.285.17:46:38.07#ibcon#read 6, iclass 10, count 0 2006.285.17:46:38.07#ibcon#end of sib2, iclass 10, count 0 2006.285.17:46:38.07#ibcon#*after write, iclass 10, count 0 2006.285.17:46:38.07#ibcon#*before return 0, iclass 10, count 0 2006.285.17:46:38.07#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:46:38.07#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.17:46:38.07#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.17:46:38.07#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.17:46:38.08$vck44/vblo=8,744.99 2006.285.17:46:38.08#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.17:46:38.08#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.17:46:38.08#ibcon#ireg 17 cls_cnt 0 2006.285.17:46:38.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:46:38.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:46:38.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:46:38.08#ibcon#enter wrdev, iclass 12, count 0 2006.285.17:46:38.08#ibcon#first serial, iclass 12, count 0 2006.285.17:46:38.08#ibcon#enter sib2, iclass 12, count 0 2006.285.17:46:38.08#ibcon#flushed, iclass 12, count 0 2006.285.17:46:38.08#ibcon#about to write, iclass 12, count 0 2006.285.17:46:38.08#ibcon#wrote, iclass 12, count 0 2006.285.17:46:38.08#ibcon#about to read 3, iclass 12, count 0 2006.285.17:46:38.09#ibcon#read 3, iclass 12, count 0 2006.285.17:46:38.09#ibcon#about to read 4, iclass 12, count 0 2006.285.17:46:38.09#ibcon#read 4, iclass 12, count 0 2006.285.17:46:38.09#ibcon#about to read 5, iclass 12, count 0 2006.285.17:46:38.09#ibcon#read 5, iclass 12, count 0 2006.285.17:46:38.09#ibcon#about to read 6, iclass 12, count 0 2006.285.17:46:38.09#ibcon#read 6, iclass 12, count 0 2006.285.17:46:38.09#ibcon#end of sib2, iclass 12, count 0 2006.285.17:46:38.09#ibcon#*mode == 0, iclass 12, count 0 2006.285.17:46:38.09#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.17:46:38.09#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.17:46:38.09#ibcon#*before write, iclass 12, count 0 2006.285.17:46:38.09#ibcon#enter sib2, iclass 12, count 0 2006.285.17:46:38.10#ibcon#flushed, iclass 12, count 0 2006.285.17:46:38.10#ibcon#about to write, iclass 12, count 0 2006.285.17:46:38.10#ibcon#wrote, iclass 12, count 0 2006.285.17:46:38.10#ibcon#about to read 3, iclass 12, count 0 2006.285.17:46:38.13#ibcon#read 3, iclass 12, count 0 2006.285.17:46:38.13#ibcon#about to read 4, iclass 12, count 0 2006.285.17:46:38.13#ibcon#read 4, iclass 12, count 0 2006.285.17:46:38.13#ibcon#about to read 5, iclass 12, count 0 2006.285.17:46:38.13#ibcon#read 5, iclass 12, count 0 2006.285.17:46:38.13#ibcon#about to read 6, iclass 12, count 0 2006.285.17:46:38.13#ibcon#read 6, iclass 12, count 0 2006.285.17:46:38.13#ibcon#end of sib2, iclass 12, count 0 2006.285.17:46:38.13#ibcon#*after write, iclass 12, count 0 2006.285.17:46:38.13#ibcon#*before return 0, iclass 12, count 0 2006.285.17:46:38.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:46:38.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.17:46:38.13#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.17:46:38.13#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.17:46:38.14$vck44/vb=8,4 2006.285.17:46:38.14#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.17:46:38.14#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.17:46:38.14#ibcon#ireg 11 cls_cnt 2 2006.285.17:46:38.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:46:38.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:46:38.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:46:38.18#ibcon#enter wrdev, iclass 14, count 2 2006.285.17:46:38.18#ibcon#first serial, iclass 14, count 2 2006.285.17:46:38.18#ibcon#enter sib2, iclass 14, count 2 2006.285.17:46:38.18#ibcon#flushed, iclass 14, count 2 2006.285.17:46:38.18#ibcon#about to write, iclass 14, count 2 2006.285.17:46:38.18#ibcon#wrote, iclass 14, count 2 2006.285.17:46:38.18#ibcon#about to read 3, iclass 14, count 2 2006.285.17:46:38.20#ibcon#read 3, iclass 14, count 2 2006.285.17:46:38.20#ibcon#about to read 4, iclass 14, count 2 2006.285.17:46:38.20#ibcon#read 4, iclass 14, count 2 2006.285.17:46:38.20#ibcon#about to read 5, iclass 14, count 2 2006.285.17:46:38.20#ibcon#read 5, iclass 14, count 2 2006.285.17:46:38.20#ibcon#about to read 6, iclass 14, count 2 2006.285.17:46:38.20#ibcon#read 6, iclass 14, count 2 2006.285.17:46:38.20#ibcon#end of sib2, iclass 14, count 2 2006.285.17:46:38.20#ibcon#*mode == 0, iclass 14, count 2 2006.285.17:46:38.20#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.17:46:38.20#ibcon#[27=AT08-04\r\n] 2006.285.17:46:38.20#ibcon#*before write, iclass 14, count 2 2006.285.17:46:38.20#ibcon#enter sib2, iclass 14, count 2 2006.285.17:46:38.20#ibcon#flushed, iclass 14, count 2 2006.285.17:46:38.20#ibcon#about to write, iclass 14, count 2 2006.285.17:46:38.21#ibcon#wrote, iclass 14, count 2 2006.285.17:46:38.21#ibcon#about to read 3, iclass 14, count 2 2006.285.17:46:38.23#ibcon#read 3, iclass 14, count 2 2006.285.17:46:38.23#ibcon#about to read 4, iclass 14, count 2 2006.285.17:46:38.23#ibcon#read 4, iclass 14, count 2 2006.285.17:46:38.23#ibcon#about to read 5, iclass 14, count 2 2006.285.17:46:38.23#ibcon#read 5, iclass 14, count 2 2006.285.17:46:38.23#ibcon#about to read 6, iclass 14, count 2 2006.285.17:46:38.23#ibcon#read 6, iclass 14, count 2 2006.285.17:46:38.23#ibcon#end of sib2, iclass 14, count 2 2006.285.17:46:38.23#ibcon#*after write, iclass 14, count 2 2006.285.17:46:38.23#ibcon#*before return 0, iclass 14, count 2 2006.285.17:46:38.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:46:38.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.17:46:38.23#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.17:46:38.23#ibcon#ireg 7 cls_cnt 0 2006.285.17:46:38.23#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:46:38.35#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:46:38.35#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:46:38.35#ibcon#enter wrdev, iclass 14, count 0 2006.285.17:46:38.35#ibcon#first serial, iclass 14, count 0 2006.285.17:46:38.35#ibcon#enter sib2, iclass 14, count 0 2006.285.17:46:38.35#ibcon#flushed, iclass 14, count 0 2006.285.17:46:38.35#ibcon#about to write, iclass 14, count 0 2006.285.17:46:38.35#ibcon#wrote, iclass 14, count 0 2006.285.17:46:38.35#ibcon#about to read 3, iclass 14, count 0 2006.285.17:46:38.37#ibcon#read 3, iclass 14, count 0 2006.285.17:46:38.37#ibcon#about to read 4, iclass 14, count 0 2006.285.17:46:38.37#ibcon#read 4, iclass 14, count 0 2006.285.17:46:38.37#ibcon#about to read 5, iclass 14, count 0 2006.285.17:46:38.37#ibcon#read 5, iclass 14, count 0 2006.285.17:46:38.37#ibcon#about to read 6, iclass 14, count 0 2006.285.17:46:38.37#ibcon#read 6, iclass 14, count 0 2006.285.17:46:38.37#ibcon#end of sib2, iclass 14, count 0 2006.285.17:46:38.37#ibcon#*mode == 0, iclass 14, count 0 2006.285.17:46:38.37#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.17:46:38.37#ibcon#[27=USB\r\n] 2006.285.17:46:38.37#ibcon#*before write, iclass 14, count 0 2006.285.17:46:38.37#ibcon#enter sib2, iclass 14, count 0 2006.285.17:46:38.37#ibcon#flushed, iclass 14, count 0 2006.285.17:46:38.37#ibcon#about to write, iclass 14, count 0 2006.285.17:46:38.37#ibcon#wrote, iclass 14, count 0 2006.285.17:46:38.37#ibcon#about to read 3, iclass 14, count 0 2006.285.17:46:38.40#ibcon#read 3, iclass 14, count 0 2006.285.17:46:38.40#ibcon#about to read 4, iclass 14, count 0 2006.285.17:46:38.40#ibcon#read 4, iclass 14, count 0 2006.285.17:46:38.40#ibcon#about to read 5, iclass 14, count 0 2006.285.17:46:38.40#ibcon#read 5, iclass 14, count 0 2006.285.17:46:38.40#ibcon#about to read 6, iclass 14, count 0 2006.285.17:46:38.40#ibcon#read 6, iclass 14, count 0 2006.285.17:46:38.40#ibcon#end of sib2, iclass 14, count 0 2006.285.17:46:38.40#ibcon#*after write, iclass 14, count 0 2006.285.17:46:38.40#ibcon#*before return 0, iclass 14, count 0 2006.285.17:46:38.40#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:46:38.40#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.17:46:38.40#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.17:46:38.40#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.17:46:38.41$vck44/vabw=wide 2006.285.17:46:38.41#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.17:46:38.41#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.17:46:38.41#ibcon#ireg 8 cls_cnt 0 2006.285.17:46:38.41#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:46:38.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:46:38.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:46:38.41#ibcon#enter wrdev, iclass 16, count 0 2006.285.17:46:38.41#ibcon#first serial, iclass 16, count 0 2006.285.17:46:38.41#ibcon#enter sib2, iclass 16, count 0 2006.285.17:46:38.41#ibcon#flushed, iclass 16, count 0 2006.285.17:46:38.41#ibcon#about to write, iclass 16, count 0 2006.285.17:46:38.41#ibcon#wrote, iclass 16, count 0 2006.285.17:46:38.41#ibcon#about to read 3, iclass 16, count 0 2006.285.17:46:38.42#ibcon#read 3, iclass 16, count 0 2006.285.17:46:38.42#ibcon#about to read 4, iclass 16, count 0 2006.285.17:46:38.42#ibcon#read 4, iclass 16, count 0 2006.285.17:46:38.42#ibcon#about to read 5, iclass 16, count 0 2006.285.17:46:38.42#ibcon#read 5, iclass 16, count 0 2006.285.17:46:38.42#ibcon#about to read 6, iclass 16, count 0 2006.285.17:46:38.42#ibcon#read 6, iclass 16, count 0 2006.285.17:46:38.42#ibcon#end of sib2, iclass 16, count 0 2006.285.17:46:38.42#ibcon#*mode == 0, iclass 16, count 0 2006.285.17:46:38.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.17:46:38.42#ibcon#[25=BW32\r\n] 2006.285.17:46:38.42#ibcon#*before write, iclass 16, count 0 2006.285.17:46:38.42#ibcon#enter sib2, iclass 16, count 0 2006.285.17:46:38.42#ibcon#flushed, iclass 16, count 0 2006.285.17:46:38.42#ibcon#about to write, iclass 16, count 0 2006.285.17:46:38.42#ibcon#wrote, iclass 16, count 0 2006.285.17:46:38.42#ibcon#about to read 3, iclass 16, count 0 2006.285.17:46:38.45#ibcon#read 3, iclass 16, count 0 2006.285.17:46:38.45#ibcon#about to read 4, iclass 16, count 0 2006.285.17:46:38.45#ibcon#read 4, iclass 16, count 0 2006.285.17:46:38.45#ibcon#about to read 5, iclass 16, count 0 2006.285.17:46:38.45#ibcon#read 5, iclass 16, count 0 2006.285.17:46:38.45#ibcon#about to read 6, iclass 16, count 0 2006.285.17:46:38.45#ibcon#read 6, iclass 16, count 0 2006.285.17:46:38.45#ibcon#end of sib2, iclass 16, count 0 2006.285.17:46:38.45#ibcon#*after write, iclass 16, count 0 2006.285.17:46:38.45#ibcon#*before return 0, iclass 16, count 0 2006.285.17:46:38.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:46:38.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:46:38.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.17:46:38.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.17:46:38.46$vck44/vbbw=wide 2006.285.17:46:38.46#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.17:46:38.46#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.17:46:38.46#ibcon#ireg 8 cls_cnt 0 2006.285.17:46:38.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:46:38.51#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:46:38.51#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:46:38.51#ibcon#enter wrdev, iclass 18, count 0 2006.285.17:46:38.51#ibcon#first serial, iclass 18, count 0 2006.285.17:46:38.51#ibcon#enter sib2, iclass 18, count 0 2006.285.17:46:38.51#ibcon#flushed, iclass 18, count 0 2006.285.17:46:38.51#ibcon#about to write, iclass 18, count 0 2006.285.17:46:38.51#ibcon#wrote, iclass 18, count 0 2006.285.17:46:38.51#ibcon#about to read 3, iclass 18, count 0 2006.285.17:46:38.53#ibcon#read 3, iclass 18, count 0 2006.285.17:46:38.53#ibcon#about to read 4, iclass 18, count 0 2006.285.17:46:38.53#ibcon#read 4, iclass 18, count 0 2006.285.17:46:38.53#ibcon#about to read 5, iclass 18, count 0 2006.285.17:46:38.53#ibcon#read 5, iclass 18, count 0 2006.285.17:46:38.53#ibcon#about to read 6, iclass 18, count 0 2006.285.17:46:38.53#ibcon#read 6, iclass 18, count 0 2006.285.17:46:38.53#ibcon#end of sib2, iclass 18, count 0 2006.285.17:46:38.53#ibcon#*mode == 0, iclass 18, count 0 2006.285.17:46:38.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.17:46:38.53#ibcon#[27=BW32\r\n] 2006.285.17:46:38.53#ibcon#*before write, iclass 18, count 0 2006.285.17:46:38.53#ibcon#enter sib2, iclass 18, count 0 2006.285.17:46:38.53#ibcon#flushed, iclass 18, count 0 2006.285.17:46:38.53#ibcon#about to write, iclass 18, count 0 2006.285.17:46:38.53#ibcon#wrote, iclass 18, count 0 2006.285.17:46:38.53#ibcon#about to read 3, iclass 18, count 0 2006.285.17:46:38.56#ibcon#read 3, iclass 18, count 0 2006.285.17:46:38.56#ibcon#about to read 4, iclass 18, count 0 2006.285.17:46:38.56#ibcon#read 4, iclass 18, count 0 2006.285.17:46:38.56#ibcon#about to read 5, iclass 18, count 0 2006.285.17:46:38.56#ibcon#read 5, iclass 18, count 0 2006.285.17:46:38.56#ibcon#about to read 6, iclass 18, count 0 2006.285.17:46:38.56#ibcon#read 6, iclass 18, count 0 2006.285.17:46:38.56#ibcon#end of sib2, iclass 18, count 0 2006.285.17:46:38.56#ibcon#*after write, iclass 18, count 0 2006.285.17:46:38.56#ibcon#*before return 0, iclass 18, count 0 2006.285.17:46:38.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:46:38.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:46:38.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.17:46:38.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.17:46:38.57$setupk4/ifdk4 2006.285.17:46:38.57$ifdk4/lo= 2006.285.17:46:38.57$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.17:46:38.57$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.17:46:38.57$ifdk4/patch= 2006.285.17:46:38.57$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.17:46:38.57$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.17:46:38.57$setupk4/!*+20s 2006.285.17:46:41.14#trakl#Source acquired 2006.285.17:46:42.15#flagr#flagr/antenna,acquired 2006.285.17:46:46.99#abcon#<5=/00 0.1 1.0 16.38 991014.5\r\n> 2006.285.17:46:47.01#abcon#{5=INTERFACE CLEAR} 2006.285.17:46:47.07#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:46:52.53$setupk4/"tpicd 2006.285.17:46:52.53$setupk4/echo=off 2006.285.17:46:52.53$setupk4/xlog=off 2006.285.17:46:52.54:!2006.285.17:47:18 2006.285.17:47:18.02:preob 2006.285.17:47:19.15/onsource/TRACKING 2006.285.17:47:19.15:!2006.285.17:47:28 2006.285.17:47:28.02:"tape 2006.285.17:47:28.02:"st=record 2006.285.17:47:28.02:data_valid=on 2006.285.17:47:28.02:midob 2006.285.17:47:29.15/onsource/TRACKING 2006.285.17:47:29.15/wx/16.36,1014.5,99 2006.285.17:47:29.30/cable/+6.5041E-03 2006.285.17:47:30.39/va/01,07,usb,yes,36,39 2006.285.17:47:30.39/va/02,06,usb,yes,36,36 2006.285.17:47:30.39/va/03,07,usb,yes,35,37 2006.285.17:47:30.39/va/04,06,usb,yes,37,39 2006.285.17:47:30.39/va/05,03,usb,yes,36,37 2006.285.17:47:30.39/va/06,04,usb,yes,33,32 2006.285.17:47:30.39/va/07,04,usb,yes,34,34 2006.285.17:47:30.39/va/08,03,usb,yes,34,41 2006.285.17:47:30.62/valo/01,524.99,yes,locked 2006.285.17:47:30.62/valo/02,534.99,yes,locked 2006.285.17:47:30.62/valo/03,564.99,yes,locked 2006.285.17:47:30.62/valo/04,624.99,yes,locked 2006.285.17:47:30.62/valo/05,734.99,yes,locked 2006.285.17:47:30.62/valo/06,814.99,yes,locked 2006.285.17:47:30.62/valo/07,864.99,yes,locked 2006.285.17:47:30.62/valo/08,884.99,yes,locked 2006.285.17:47:31.71/vb/01,04,usb,yes,33,30 2006.285.17:47:31.71/vb/02,05,usb,yes,31,31 2006.285.17:47:31.71/vb/03,04,usb,yes,32,35 2006.285.17:47:31.71/vb/04,05,usb,yes,32,31 2006.285.17:47:31.71/vb/05,04,usb,yes,28,31 2006.285.17:47:31.71/vb/06,03,usb,yes,41,36 2006.285.17:47:31.71/vb/07,04,usb,yes,33,33 2006.285.17:47:31.71/vb/08,04,usb,yes,30,34 2006.285.17:47:31.94/vblo/01,629.99,yes,locked 2006.285.17:47:31.94/vblo/02,634.99,yes,locked 2006.285.17:47:31.94/vblo/03,649.99,yes,locked 2006.285.17:47:31.94/vblo/04,679.99,yes,locked 2006.285.17:47:31.94/vblo/05,709.99,yes,locked 2006.285.17:47:31.94/vblo/06,719.99,yes,locked 2006.285.17:47:31.94/vblo/07,734.99,yes,locked 2006.285.17:47:31.94/vblo/08,744.99,yes,locked 2006.285.17:47:32.09/vabw/8 2006.285.17:47:32.24/vbbw/8 2006.285.17:47:32.42/xfe/off,on,12.0 2006.285.17:47:32.81/ifatt/23,28,28,28 2006.285.17:47:33.07/fmout-gps/S +2.81E-07 2006.285.17:47:33.09:!2006.285.17:51:08 2006.285.17:51:08.01:data_valid=off 2006.285.17:51:08.01:"et 2006.285.17:51:08.01:!+3s 2006.285.17:51:11.02:"tape 2006.285.17:51:11.02:postob 2006.285.17:51:11.19/cable/+6.5043E-03 2006.285.17:51:11.19/wx/16.28,1014.5,100 2006.285.17:51:11.25/fmout-gps/S +2.73E-07 2006.285.17:51:11.25:scan_name=285-1753,jd0610,100 2006.285.17:51:11.25:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.285.17:51:12.14#flagr#flagr/antenna,new-source 2006.285.17:51:12.14:checkk5 2006.285.17:51:12.62/chk_autoobs//k5ts1/ autoobs is running! 2006.285.17:51:13.05/chk_autoobs//k5ts2/ autoobs is running! 2006.285.17:51:13.44/chk_autoobs//k5ts3/ autoobs is running! 2006.285.17:51:13.93/chk_autoobs//k5ts4/ autoobs is running! 2006.285.17:51:14.31/chk_obsdata//k5ts1/T2851747??a.dat file size is correct (nominal:880MB, actual:880MB). 2006.285.17:51:14.78/chk_obsdata//k5ts2/T2851747??b.dat file size is correct (nominal:880MB, actual:880MB). 2006.285.17:51:15.15/chk_obsdata//k5ts3/T2851747??c.dat file size is correct (nominal:880MB, actual:880MB). 2006.285.17:51:15.66/chk_obsdata//k5ts4/T2851747??d.dat file size is correct (nominal:880MB, actual:880MB). 2006.285.17:51:16.48/k5log//k5ts1_log_newline 2006.285.17:51:17.39/k5log//k5ts2_log_newline 2006.285.17:51:18.40/k5log//k5ts3_log_newline 2006.285.17:51:19.51/k5log//k5ts4_log_newline 2006.285.17:51:19.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.17:51:19.53:setupk4=1 2006.285.17:51:19.53$setupk4/echo=on 2006.285.17:51:19.54$setupk4/pcalon 2006.285.17:51:19.54$pcalon/"no phase cal control is implemented here 2006.285.17:51:19.54$setupk4/"tpicd=stop 2006.285.17:51:19.54$setupk4/"rec=synch_on 2006.285.17:51:19.54$setupk4/"rec_mode=128 2006.285.17:51:19.54$setupk4/!* 2006.285.17:51:19.54$setupk4/recpk4 2006.285.17:51:19.54$recpk4/recpatch= 2006.285.17:51:19.54$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.17:51:19.54$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.17:51:19.54$setupk4/vck44 2006.285.17:51:19.54$vck44/valo=1,524.99 2006.285.17:51:19.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.17:51:19.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.17:51:19.54#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:19.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:51:19.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:51:19.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:51:19.54#ibcon#enter wrdev, iclass 23, count 0 2006.285.17:51:19.54#ibcon#first serial, iclass 23, count 0 2006.285.17:51:19.54#ibcon#enter sib2, iclass 23, count 0 2006.285.17:51:19.54#ibcon#flushed, iclass 23, count 0 2006.285.17:51:19.54#ibcon#about to write, iclass 23, count 0 2006.285.17:51:19.54#ibcon#wrote, iclass 23, count 0 2006.285.17:51:19.54#ibcon#about to read 3, iclass 23, count 0 2006.285.17:51:19.55#ibcon#read 3, iclass 23, count 0 2006.285.17:51:19.55#ibcon#about to read 4, iclass 23, count 0 2006.285.17:51:19.55#ibcon#read 4, iclass 23, count 0 2006.285.17:51:19.55#ibcon#about to read 5, iclass 23, count 0 2006.285.17:51:19.55#ibcon#read 5, iclass 23, count 0 2006.285.17:51:19.55#ibcon#about to read 6, iclass 23, count 0 2006.285.17:51:19.55#ibcon#read 6, iclass 23, count 0 2006.285.17:51:19.55#ibcon#end of sib2, iclass 23, count 0 2006.285.17:51:19.55#ibcon#*mode == 0, iclass 23, count 0 2006.285.17:51:19.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.17:51:19.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.17:51:19.55#ibcon#*before write, iclass 23, count 0 2006.285.17:51:19.55#ibcon#enter sib2, iclass 23, count 0 2006.285.17:51:19.55#ibcon#flushed, iclass 23, count 0 2006.285.17:51:19.55#ibcon#about to write, iclass 23, count 0 2006.285.17:51:19.55#ibcon#wrote, iclass 23, count 0 2006.285.17:51:19.55#ibcon#about to read 3, iclass 23, count 0 2006.285.17:51:19.60#ibcon#read 3, iclass 23, count 0 2006.285.17:51:19.60#ibcon#about to read 4, iclass 23, count 0 2006.285.17:51:19.60#ibcon#read 4, iclass 23, count 0 2006.285.17:51:19.60#ibcon#about to read 5, iclass 23, count 0 2006.285.17:51:19.60#ibcon#read 5, iclass 23, count 0 2006.285.17:51:19.60#ibcon#about to read 6, iclass 23, count 0 2006.285.17:51:19.60#ibcon#read 6, iclass 23, count 0 2006.285.17:51:19.60#ibcon#end of sib2, iclass 23, count 0 2006.285.17:51:19.60#ibcon#*after write, iclass 23, count 0 2006.285.17:51:19.60#ibcon#*before return 0, iclass 23, count 0 2006.285.17:51:19.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:51:19.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:51:19.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.17:51:19.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.17:51:19.60$vck44/va=1,7 2006.285.17:51:19.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.17:51:19.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.17:51:19.60#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:19.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:51:19.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:51:19.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:51:19.60#ibcon#enter wrdev, iclass 25, count 2 2006.285.17:51:19.60#ibcon#first serial, iclass 25, count 2 2006.285.17:51:19.60#ibcon#enter sib2, iclass 25, count 2 2006.285.17:51:19.60#ibcon#flushed, iclass 25, count 2 2006.285.17:51:19.60#ibcon#about to write, iclass 25, count 2 2006.285.17:51:19.60#ibcon#wrote, iclass 25, count 2 2006.285.17:51:19.60#ibcon#about to read 3, iclass 25, count 2 2006.285.17:51:19.62#ibcon#read 3, iclass 25, count 2 2006.285.17:51:19.62#ibcon#about to read 4, iclass 25, count 2 2006.285.17:51:19.62#ibcon#read 4, iclass 25, count 2 2006.285.17:51:19.62#ibcon#about to read 5, iclass 25, count 2 2006.285.17:51:19.62#ibcon#read 5, iclass 25, count 2 2006.285.17:51:19.62#ibcon#about to read 6, iclass 25, count 2 2006.285.17:51:19.62#ibcon#read 6, iclass 25, count 2 2006.285.17:51:19.62#ibcon#end of sib2, iclass 25, count 2 2006.285.17:51:19.62#ibcon#*mode == 0, iclass 25, count 2 2006.285.17:51:19.62#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.17:51:19.62#ibcon#[25=AT01-07\r\n] 2006.285.17:51:19.62#ibcon#*before write, iclass 25, count 2 2006.285.17:51:19.62#ibcon#enter sib2, iclass 25, count 2 2006.285.17:51:19.62#ibcon#flushed, iclass 25, count 2 2006.285.17:51:19.62#ibcon#about to write, iclass 25, count 2 2006.285.17:51:19.62#ibcon#wrote, iclass 25, count 2 2006.285.17:51:19.62#ibcon#about to read 3, iclass 25, count 2 2006.285.17:51:19.65#ibcon#read 3, iclass 25, count 2 2006.285.17:51:19.65#ibcon#about to read 4, iclass 25, count 2 2006.285.17:51:19.65#ibcon#read 4, iclass 25, count 2 2006.285.17:51:19.65#ibcon#about to read 5, iclass 25, count 2 2006.285.17:51:19.65#ibcon#read 5, iclass 25, count 2 2006.285.17:51:19.65#ibcon#about to read 6, iclass 25, count 2 2006.285.17:51:19.65#ibcon#read 6, iclass 25, count 2 2006.285.17:51:19.65#ibcon#end of sib2, iclass 25, count 2 2006.285.17:51:19.65#ibcon#*after write, iclass 25, count 2 2006.285.17:51:19.65#ibcon#*before return 0, iclass 25, count 2 2006.285.17:51:19.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:51:19.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:51:19.65#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.17:51:19.65#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:19.65#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:51:19.77#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:51:19.77#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:51:19.77#ibcon#enter wrdev, iclass 25, count 0 2006.285.17:51:19.77#ibcon#first serial, iclass 25, count 0 2006.285.17:51:19.77#ibcon#enter sib2, iclass 25, count 0 2006.285.17:51:19.77#ibcon#flushed, iclass 25, count 0 2006.285.17:51:19.77#ibcon#about to write, iclass 25, count 0 2006.285.17:51:19.77#ibcon#wrote, iclass 25, count 0 2006.285.17:51:19.77#ibcon#about to read 3, iclass 25, count 0 2006.285.17:51:19.79#ibcon#read 3, iclass 25, count 0 2006.285.17:51:19.79#ibcon#about to read 4, iclass 25, count 0 2006.285.17:51:19.79#ibcon#read 4, iclass 25, count 0 2006.285.17:51:19.79#ibcon#about to read 5, iclass 25, count 0 2006.285.17:51:19.79#ibcon#read 5, iclass 25, count 0 2006.285.17:51:19.79#ibcon#about to read 6, iclass 25, count 0 2006.285.17:51:19.79#ibcon#read 6, iclass 25, count 0 2006.285.17:51:19.79#ibcon#end of sib2, iclass 25, count 0 2006.285.17:51:19.79#ibcon#*mode == 0, iclass 25, count 0 2006.285.17:51:19.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.17:51:19.79#ibcon#[25=USB\r\n] 2006.285.17:51:19.79#ibcon#*before write, iclass 25, count 0 2006.285.17:51:19.79#ibcon#enter sib2, iclass 25, count 0 2006.285.17:51:19.79#ibcon#flushed, iclass 25, count 0 2006.285.17:51:19.79#ibcon#about to write, iclass 25, count 0 2006.285.17:51:19.79#ibcon#wrote, iclass 25, count 0 2006.285.17:51:19.79#ibcon#about to read 3, iclass 25, count 0 2006.285.17:51:19.82#ibcon#read 3, iclass 25, count 0 2006.285.17:51:19.82#ibcon#about to read 4, iclass 25, count 0 2006.285.17:51:19.82#ibcon#read 4, iclass 25, count 0 2006.285.17:51:19.82#ibcon#about to read 5, iclass 25, count 0 2006.285.17:51:19.82#ibcon#read 5, iclass 25, count 0 2006.285.17:51:19.82#ibcon#about to read 6, iclass 25, count 0 2006.285.17:51:19.82#ibcon#read 6, iclass 25, count 0 2006.285.17:51:19.82#ibcon#end of sib2, iclass 25, count 0 2006.285.17:51:19.82#ibcon#*after write, iclass 25, count 0 2006.285.17:51:19.82#ibcon#*before return 0, iclass 25, count 0 2006.285.17:51:19.82#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:51:19.82#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:51:19.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.17:51:19.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.17:51:19.82$vck44/valo=2,534.99 2006.285.17:51:19.82#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.17:51:19.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.17:51:19.82#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:19.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:51:19.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:51:19.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:51:19.82#ibcon#enter wrdev, iclass 27, count 0 2006.285.17:51:19.82#ibcon#first serial, iclass 27, count 0 2006.285.17:51:19.82#ibcon#enter sib2, iclass 27, count 0 2006.285.17:51:19.82#ibcon#flushed, iclass 27, count 0 2006.285.17:51:19.82#ibcon#about to write, iclass 27, count 0 2006.285.17:51:19.82#ibcon#wrote, iclass 27, count 0 2006.285.17:51:19.82#ibcon#about to read 3, iclass 27, count 0 2006.285.17:51:19.84#ibcon#read 3, iclass 27, count 0 2006.285.17:51:19.84#ibcon#about to read 4, iclass 27, count 0 2006.285.17:51:19.84#ibcon#read 4, iclass 27, count 0 2006.285.17:51:19.84#ibcon#about to read 5, iclass 27, count 0 2006.285.17:51:19.84#ibcon#read 5, iclass 27, count 0 2006.285.17:51:19.84#ibcon#about to read 6, iclass 27, count 0 2006.285.17:51:19.84#ibcon#read 6, iclass 27, count 0 2006.285.17:51:19.84#ibcon#end of sib2, iclass 27, count 0 2006.285.17:51:19.84#ibcon#*mode == 0, iclass 27, count 0 2006.285.17:51:19.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.17:51:19.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.17:51:19.84#ibcon#*before write, iclass 27, count 0 2006.285.17:51:19.84#ibcon#enter sib2, iclass 27, count 0 2006.285.17:51:19.84#ibcon#flushed, iclass 27, count 0 2006.285.17:51:19.84#ibcon#about to write, iclass 27, count 0 2006.285.17:51:19.84#ibcon#wrote, iclass 27, count 0 2006.285.17:51:19.84#ibcon#about to read 3, iclass 27, count 0 2006.285.17:51:19.88#ibcon#read 3, iclass 27, count 0 2006.285.17:51:19.88#ibcon#about to read 4, iclass 27, count 0 2006.285.17:51:19.88#ibcon#read 4, iclass 27, count 0 2006.285.17:51:19.88#ibcon#about to read 5, iclass 27, count 0 2006.285.17:51:19.88#ibcon#read 5, iclass 27, count 0 2006.285.17:51:19.88#ibcon#about to read 6, iclass 27, count 0 2006.285.17:51:19.88#ibcon#read 6, iclass 27, count 0 2006.285.17:51:19.88#ibcon#end of sib2, iclass 27, count 0 2006.285.17:51:19.88#ibcon#*after write, iclass 27, count 0 2006.285.17:51:19.88#ibcon#*before return 0, iclass 27, count 0 2006.285.17:51:19.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:51:19.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:51:19.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.17:51:19.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.17:51:19.88$vck44/va=2,6 2006.285.17:51:19.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.17:51:19.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.17:51:19.88#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:19.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:51:19.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:51:19.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:51:19.94#ibcon#enter wrdev, iclass 29, count 2 2006.285.17:51:19.94#ibcon#first serial, iclass 29, count 2 2006.285.17:51:19.94#ibcon#enter sib2, iclass 29, count 2 2006.285.17:51:19.94#ibcon#flushed, iclass 29, count 2 2006.285.17:51:19.94#ibcon#about to write, iclass 29, count 2 2006.285.17:51:19.94#ibcon#wrote, iclass 29, count 2 2006.285.17:51:19.94#ibcon#about to read 3, iclass 29, count 2 2006.285.17:51:19.96#ibcon#read 3, iclass 29, count 2 2006.285.17:51:19.96#ibcon#about to read 4, iclass 29, count 2 2006.285.17:51:19.96#ibcon#read 4, iclass 29, count 2 2006.285.17:51:19.96#ibcon#about to read 5, iclass 29, count 2 2006.285.17:51:19.96#ibcon#read 5, iclass 29, count 2 2006.285.17:51:19.96#ibcon#about to read 6, iclass 29, count 2 2006.285.17:51:19.96#ibcon#read 6, iclass 29, count 2 2006.285.17:51:19.96#ibcon#end of sib2, iclass 29, count 2 2006.285.17:51:19.96#ibcon#*mode == 0, iclass 29, count 2 2006.285.17:51:19.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.17:51:19.96#ibcon#[25=AT02-06\r\n] 2006.285.17:51:19.96#ibcon#*before write, iclass 29, count 2 2006.285.17:51:19.96#ibcon#enter sib2, iclass 29, count 2 2006.285.17:51:19.96#ibcon#flushed, iclass 29, count 2 2006.285.17:51:19.96#ibcon#about to write, iclass 29, count 2 2006.285.17:51:19.96#ibcon#wrote, iclass 29, count 2 2006.285.17:51:19.96#ibcon#about to read 3, iclass 29, count 2 2006.285.17:51:19.99#ibcon#read 3, iclass 29, count 2 2006.285.17:51:19.99#ibcon#about to read 4, iclass 29, count 2 2006.285.17:51:19.99#ibcon#read 4, iclass 29, count 2 2006.285.17:51:19.99#ibcon#about to read 5, iclass 29, count 2 2006.285.17:51:19.99#ibcon#read 5, iclass 29, count 2 2006.285.17:51:19.99#ibcon#about to read 6, iclass 29, count 2 2006.285.17:51:19.99#ibcon#read 6, iclass 29, count 2 2006.285.17:51:19.99#ibcon#end of sib2, iclass 29, count 2 2006.285.17:51:19.99#ibcon#*after write, iclass 29, count 2 2006.285.17:51:19.99#ibcon#*before return 0, iclass 29, count 2 2006.285.17:51:19.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:51:19.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:51:19.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.17:51:19.99#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:19.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:51:20.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:51:20.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:51:20.11#ibcon#enter wrdev, iclass 29, count 0 2006.285.17:51:20.11#ibcon#first serial, iclass 29, count 0 2006.285.17:51:20.11#ibcon#enter sib2, iclass 29, count 0 2006.285.17:51:20.11#ibcon#flushed, iclass 29, count 0 2006.285.17:51:20.11#ibcon#about to write, iclass 29, count 0 2006.285.17:51:20.11#ibcon#wrote, iclass 29, count 0 2006.285.17:51:20.11#ibcon#about to read 3, iclass 29, count 0 2006.285.17:51:20.13#ibcon#read 3, iclass 29, count 0 2006.285.17:51:20.13#ibcon#about to read 4, iclass 29, count 0 2006.285.17:51:20.13#ibcon#read 4, iclass 29, count 0 2006.285.17:51:20.13#ibcon#about to read 5, iclass 29, count 0 2006.285.17:51:20.13#ibcon#read 5, iclass 29, count 0 2006.285.17:51:20.13#ibcon#about to read 6, iclass 29, count 0 2006.285.17:51:20.13#ibcon#read 6, iclass 29, count 0 2006.285.17:51:20.13#ibcon#end of sib2, iclass 29, count 0 2006.285.17:51:20.13#ibcon#*mode == 0, iclass 29, count 0 2006.285.17:51:20.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.17:51:20.13#ibcon#[25=USB\r\n] 2006.285.17:51:20.13#ibcon#*before write, iclass 29, count 0 2006.285.17:51:20.13#ibcon#enter sib2, iclass 29, count 0 2006.285.17:51:20.13#ibcon#flushed, iclass 29, count 0 2006.285.17:51:20.13#ibcon#about to write, iclass 29, count 0 2006.285.17:51:20.13#ibcon#wrote, iclass 29, count 0 2006.285.17:51:20.13#ibcon#about to read 3, iclass 29, count 0 2006.285.17:51:20.16#ibcon#read 3, iclass 29, count 0 2006.285.17:51:20.16#ibcon#about to read 4, iclass 29, count 0 2006.285.17:51:20.16#ibcon#read 4, iclass 29, count 0 2006.285.17:51:20.16#ibcon#about to read 5, iclass 29, count 0 2006.285.17:51:20.16#ibcon#read 5, iclass 29, count 0 2006.285.17:51:20.16#ibcon#about to read 6, iclass 29, count 0 2006.285.17:51:20.16#ibcon#read 6, iclass 29, count 0 2006.285.17:51:20.16#ibcon#end of sib2, iclass 29, count 0 2006.285.17:51:20.16#ibcon#*after write, iclass 29, count 0 2006.285.17:51:20.16#ibcon#*before return 0, iclass 29, count 0 2006.285.17:51:20.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:51:20.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:51:20.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.17:51:20.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.17:51:20.16$vck44/valo=3,564.99 2006.285.17:51:20.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.17:51:20.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.17:51:20.16#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:20.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:51:20.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:51:20.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:51:20.16#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:51:20.16#ibcon#first serial, iclass 31, count 0 2006.285.17:51:20.16#ibcon#enter sib2, iclass 31, count 0 2006.285.17:51:20.16#ibcon#flushed, iclass 31, count 0 2006.285.17:51:20.16#ibcon#about to write, iclass 31, count 0 2006.285.17:51:20.16#ibcon#wrote, iclass 31, count 0 2006.285.17:51:20.16#ibcon#about to read 3, iclass 31, count 0 2006.285.17:51:20.18#ibcon#read 3, iclass 31, count 0 2006.285.17:51:20.18#ibcon#about to read 4, iclass 31, count 0 2006.285.17:51:20.18#ibcon#read 4, iclass 31, count 0 2006.285.17:51:20.18#ibcon#about to read 5, iclass 31, count 0 2006.285.17:51:20.18#ibcon#read 5, iclass 31, count 0 2006.285.17:51:20.18#ibcon#about to read 6, iclass 31, count 0 2006.285.17:51:20.18#ibcon#read 6, iclass 31, count 0 2006.285.17:51:20.18#ibcon#end of sib2, iclass 31, count 0 2006.285.17:51:20.18#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:51:20.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:51:20.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.17:51:20.18#ibcon#*before write, iclass 31, count 0 2006.285.17:51:20.18#ibcon#enter sib2, iclass 31, count 0 2006.285.17:51:20.18#ibcon#flushed, iclass 31, count 0 2006.285.17:51:20.18#ibcon#about to write, iclass 31, count 0 2006.285.17:51:20.18#ibcon#wrote, iclass 31, count 0 2006.285.17:51:20.18#ibcon#about to read 3, iclass 31, count 0 2006.285.17:51:20.22#ibcon#read 3, iclass 31, count 0 2006.285.17:51:20.22#ibcon#about to read 4, iclass 31, count 0 2006.285.17:51:20.22#ibcon#read 4, iclass 31, count 0 2006.285.17:51:20.22#ibcon#about to read 5, iclass 31, count 0 2006.285.17:51:20.22#ibcon#read 5, iclass 31, count 0 2006.285.17:51:20.22#ibcon#about to read 6, iclass 31, count 0 2006.285.17:51:20.22#ibcon#read 6, iclass 31, count 0 2006.285.17:51:20.22#ibcon#end of sib2, iclass 31, count 0 2006.285.17:51:20.22#ibcon#*after write, iclass 31, count 0 2006.285.17:51:20.22#ibcon#*before return 0, iclass 31, count 0 2006.285.17:51:20.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:51:20.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:51:20.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:51:20.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:51:20.22$vck44/va=3,7 2006.285.17:51:20.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.17:51:20.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.17:51:20.22#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:20.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:51:20.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:51:20.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:51:20.28#ibcon#enter wrdev, iclass 33, count 2 2006.285.17:51:20.28#ibcon#first serial, iclass 33, count 2 2006.285.17:51:20.28#ibcon#enter sib2, iclass 33, count 2 2006.285.17:51:20.28#ibcon#flushed, iclass 33, count 2 2006.285.17:51:20.28#ibcon#about to write, iclass 33, count 2 2006.285.17:51:20.28#ibcon#wrote, iclass 33, count 2 2006.285.17:51:20.28#ibcon#about to read 3, iclass 33, count 2 2006.285.17:51:20.30#ibcon#read 3, iclass 33, count 2 2006.285.17:51:20.30#ibcon#about to read 4, iclass 33, count 2 2006.285.17:51:20.30#ibcon#read 4, iclass 33, count 2 2006.285.17:51:20.30#ibcon#about to read 5, iclass 33, count 2 2006.285.17:51:20.30#ibcon#read 5, iclass 33, count 2 2006.285.17:51:20.30#ibcon#about to read 6, iclass 33, count 2 2006.285.17:51:20.30#ibcon#read 6, iclass 33, count 2 2006.285.17:51:20.30#ibcon#end of sib2, iclass 33, count 2 2006.285.17:51:20.30#ibcon#*mode == 0, iclass 33, count 2 2006.285.17:51:20.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.17:51:20.30#ibcon#[25=AT03-07\r\n] 2006.285.17:51:20.30#ibcon#*before write, iclass 33, count 2 2006.285.17:51:20.30#ibcon#enter sib2, iclass 33, count 2 2006.285.17:51:20.30#ibcon#flushed, iclass 33, count 2 2006.285.17:51:20.30#ibcon#about to write, iclass 33, count 2 2006.285.17:51:20.30#ibcon#wrote, iclass 33, count 2 2006.285.17:51:20.30#ibcon#about to read 3, iclass 33, count 2 2006.285.17:51:20.33#ibcon#read 3, iclass 33, count 2 2006.285.17:51:20.33#ibcon#about to read 4, iclass 33, count 2 2006.285.17:51:20.33#ibcon#read 4, iclass 33, count 2 2006.285.17:51:20.33#ibcon#about to read 5, iclass 33, count 2 2006.285.17:51:20.33#ibcon#read 5, iclass 33, count 2 2006.285.17:51:20.33#ibcon#about to read 6, iclass 33, count 2 2006.285.17:51:20.33#ibcon#read 6, iclass 33, count 2 2006.285.17:51:20.33#ibcon#end of sib2, iclass 33, count 2 2006.285.17:51:20.33#ibcon#*after write, iclass 33, count 2 2006.285.17:51:20.33#ibcon#*before return 0, iclass 33, count 2 2006.285.17:51:20.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:51:20.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:51:20.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.17:51:20.33#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:20.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:51:20.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:51:20.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:51:20.45#ibcon#enter wrdev, iclass 33, count 0 2006.285.17:51:20.45#ibcon#first serial, iclass 33, count 0 2006.285.17:51:20.45#ibcon#enter sib2, iclass 33, count 0 2006.285.17:51:20.45#ibcon#flushed, iclass 33, count 0 2006.285.17:51:20.45#ibcon#about to write, iclass 33, count 0 2006.285.17:51:20.45#ibcon#wrote, iclass 33, count 0 2006.285.17:51:20.45#ibcon#about to read 3, iclass 33, count 0 2006.285.17:51:20.47#ibcon#read 3, iclass 33, count 0 2006.285.17:51:20.47#ibcon#about to read 4, iclass 33, count 0 2006.285.17:51:20.47#ibcon#read 4, iclass 33, count 0 2006.285.17:51:20.47#ibcon#about to read 5, iclass 33, count 0 2006.285.17:51:20.47#ibcon#read 5, iclass 33, count 0 2006.285.17:51:20.47#ibcon#about to read 6, iclass 33, count 0 2006.285.17:51:20.47#ibcon#read 6, iclass 33, count 0 2006.285.17:51:20.47#ibcon#end of sib2, iclass 33, count 0 2006.285.17:51:20.47#ibcon#*mode == 0, iclass 33, count 0 2006.285.17:51:20.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.17:51:20.47#ibcon#[25=USB\r\n] 2006.285.17:51:20.47#ibcon#*before write, iclass 33, count 0 2006.285.17:51:20.47#ibcon#enter sib2, iclass 33, count 0 2006.285.17:51:20.47#ibcon#flushed, iclass 33, count 0 2006.285.17:51:20.47#ibcon#about to write, iclass 33, count 0 2006.285.17:51:20.47#ibcon#wrote, iclass 33, count 0 2006.285.17:51:20.47#ibcon#about to read 3, iclass 33, count 0 2006.285.17:51:20.50#ibcon#read 3, iclass 33, count 0 2006.285.17:51:20.50#ibcon#about to read 4, iclass 33, count 0 2006.285.17:51:20.50#ibcon#read 4, iclass 33, count 0 2006.285.17:51:20.50#ibcon#about to read 5, iclass 33, count 0 2006.285.17:51:20.50#ibcon#read 5, iclass 33, count 0 2006.285.17:51:20.50#ibcon#about to read 6, iclass 33, count 0 2006.285.17:51:20.50#ibcon#read 6, iclass 33, count 0 2006.285.17:51:20.50#ibcon#end of sib2, iclass 33, count 0 2006.285.17:51:20.50#ibcon#*after write, iclass 33, count 0 2006.285.17:51:20.50#ibcon#*before return 0, iclass 33, count 0 2006.285.17:51:20.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:51:20.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:51:20.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.17:51:20.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.17:51:20.50$vck44/valo=4,624.99 2006.285.17:51:20.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.17:51:20.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.17:51:20.50#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:20.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:51:20.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:51:20.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:51:20.50#ibcon#enter wrdev, iclass 35, count 0 2006.285.17:51:20.50#ibcon#first serial, iclass 35, count 0 2006.285.17:51:20.50#ibcon#enter sib2, iclass 35, count 0 2006.285.17:51:20.50#ibcon#flushed, iclass 35, count 0 2006.285.17:51:20.50#ibcon#about to write, iclass 35, count 0 2006.285.17:51:20.50#ibcon#wrote, iclass 35, count 0 2006.285.17:51:20.50#ibcon#about to read 3, iclass 35, count 0 2006.285.17:51:20.52#ibcon#read 3, iclass 35, count 0 2006.285.17:51:20.97#ibcon#about to read 4, iclass 35, count 0 2006.285.17:51:20.97#ibcon#read 4, iclass 35, count 0 2006.285.17:51:20.97#ibcon#about to read 5, iclass 35, count 0 2006.285.17:51:20.97#ibcon#read 5, iclass 35, count 0 2006.285.17:51:20.97#ibcon#about to read 6, iclass 35, count 0 2006.285.17:51:20.97#ibcon#read 6, iclass 35, count 0 2006.285.17:51:20.97#ibcon#end of sib2, iclass 35, count 0 2006.285.17:51:20.97#ibcon#*mode == 0, iclass 35, count 0 2006.285.17:51:20.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.17:51:20.97#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.17:51:20.97#ibcon#*before write, iclass 35, count 0 2006.285.17:51:20.97#ibcon#enter sib2, iclass 35, count 0 2006.285.17:51:20.97#ibcon#flushed, iclass 35, count 0 2006.285.17:51:20.97#ibcon#about to write, iclass 35, count 0 2006.285.17:51:20.97#ibcon#wrote, iclass 35, count 0 2006.285.17:51:20.97#ibcon#about to read 3, iclass 35, count 0 2006.285.17:51:21.01#ibcon#read 3, iclass 35, count 0 2006.285.17:51:21.01#ibcon#about to read 4, iclass 35, count 0 2006.285.17:51:21.01#ibcon#read 4, iclass 35, count 0 2006.285.17:51:21.01#ibcon#about to read 5, iclass 35, count 0 2006.285.17:51:21.01#ibcon#read 5, iclass 35, count 0 2006.285.17:51:21.01#ibcon#about to read 6, iclass 35, count 0 2006.285.17:51:21.01#ibcon#read 6, iclass 35, count 0 2006.285.17:51:21.01#ibcon#end of sib2, iclass 35, count 0 2006.285.17:51:21.01#ibcon#*after write, iclass 35, count 0 2006.285.17:51:21.01#ibcon#*before return 0, iclass 35, count 0 2006.285.17:51:21.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:51:21.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:51:21.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.17:51:21.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.17:51:21.01$vck44/va=4,6 2006.285.17:51:21.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.17:51:21.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.17:51:21.01#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:21.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:51:21.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:51:21.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:51:21.01#ibcon#enter wrdev, iclass 37, count 2 2006.285.17:51:21.01#ibcon#first serial, iclass 37, count 2 2006.285.17:51:21.01#ibcon#enter sib2, iclass 37, count 2 2006.285.17:51:21.01#ibcon#flushed, iclass 37, count 2 2006.285.17:51:21.01#ibcon#about to write, iclass 37, count 2 2006.285.17:51:21.01#ibcon#wrote, iclass 37, count 2 2006.285.17:51:21.01#ibcon#about to read 3, iclass 37, count 2 2006.285.17:51:21.03#ibcon#read 3, iclass 37, count 2 2006.285.17:51:21.03#ibcon#about to read 4, iclass 37, count 2 2006.285.17:51:21.03#ibcon#read 4, iclass 37, count 2 2006.285.17:51:21.03#ibcon#about to read 5, iclass 37, count 2 2006.285.17:51:21.03#ibcon#read 5, iclass 37, count 2 2006.285.17:51:21.03#ibcon#about to read 6, iclass 37, count 2 2006.285.17:51:21.03#ibcon#read 6, iclass 37, count 2 2006.285.17:51:21.03#ibcon#end of sib2, iclass 37, count 2 2006.285.17:51:21.03#ibcon#*mode == 0, iclass 37, count 2 2006.285.17:51:21.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.17:51:21.03#ibcon#[25=AT04-06\r\n] 2006.285.17:51:21.03#ibcon#*before write, iclass 37, count 2 2006.285.17:51:21.03#ibcon#enter sib2, iclass 37, count 2 2006.285.17:51:21.03#ibcon#flushed, iclass 37, count 2 2006.285.17:51:21.03#ibcon#about to write, iclass 37, count 2 2006.285.17:51:21.03#ibcon#wrote, iclass 37, count 2 2006.285.17:51:21.03#ibcon#about to read 3, iclass 37, count 2 2006.285.17:51:21.06#ibcon#read 3, iclass 37, count 2 2006.285.17:51:21.06#ibcon#about to read 4, iclass 37, count 2 2006.285.17:51:21.06#ibcon#read 4, iclass 37, count 2 2006.285.17:51:21.06#ibcon#about to read 5, iclass 37, count 2 2006.285.17:51:21.06#ibcon#read 5, iclass 37, count 2 2006.285.17:51:21.06#ibcon#about to read 6, iclass 37, count 2 2006.285.17:51:21.06#ibcon#read 6, iclass 37, count 2 2006.285.17:51:21.06#ibcon#end of sib2, iclass 37, count 2 2006.285.17:51:21.06#ibcon#*after write, iclass 37, count 2 2006.285.17:51:21.06#ibcon#*before return 0, iclass 37, count 2 2006.285.17:51:21.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:51:21.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:51:21.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.17:51:21.06#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:21.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:51:21.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:51:21.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:51:21.18#ibcon#enter wrdev, iclass 37, count 0 2006.285.17:51:21.18#ibcon#first serial, iclass 37, count 0 2006.285.17:51:21.18#ibcon#enter sib2, iclass 37, count 0 2006.285.17:51:21.18#ibcon#flushed, iclass 37, count 0 2006.285.17:51:21.18#ibcon#about to write, iclass 37, count 0 2006.285.17:51:21.18#ibcon#wrote, iclass 37, count 0 2006.285.17:51:21.18#ibcon#about to read 3, iclass 37, count 0 2006.285.17:51:21.20#ibcon#read 3, iclass 37, count 0 2006.285.17:51:21.20#ibcon#about to read 4, iclass 37, count 0 2006.285.17:51:21.20#ibcon#read 4, iclass 37, count 0 2006.285.17:51:21.20#ibcon#about to read 5, iclass 37, count 0 2006.285.17:51:21.20#ibcon#read 5, iclass 37, count 0 2006.285.17:51:21.20#ibcon#about to read 6, iclass 37, count 0 2006.285.17:51:21.20#ibcon#read 6, iclass 37, count 0 2006.285.17:51:21.20#ibcon#end of sib2, iclass 37, count 0 2006.285.17:51:21.20#ibcon#*mode == 0, iclass 37, count 0 2006.285.17:51:21.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.17:51:21.20#ibcon#[25=USB\r\n] 2006.285.17:51:21.20#ibcon#*before write, iclass 37, count 0 2006.285.17:51:21.20#ibcon#enter sib2, iclass 37, count 0 2006.285.17:51:21.20#ibcon#flushed, iclass 37, count 0 2006.285.17:51:21.20#ibcon#about to write, iclass 37, count 0 2006.285.17:51:21.20#ibcon#wrote, iclass 37, count 0 2006.285.17:51:21.20#ibcon#about to read 3, iclass 37, count 0 2006.285.17:51:21.23#ibcon#read 3, iclass 37, count 0 2006.285.17:51:21.23#ibcon#about to read 4, iclass 37, count 0 2006.285.17:51:21.23#ibcon#read 4, iclass 37, count 0 2006.285.17:51:21.23#ibcon#about to read 5, iclass 37, count 0 2006.285.17:51:21.23#ibcon#read 5, iclass 37, count 0 2006.285.17:51:21.23#ibcon#about to read 6, iclass 37, count 0 2006.285.17:51:21.23#ibcon#read 6, iclass 37, count 0 2006.285.17:51:21.23#ibcon#end of sib2, iclass 37, count 0 2006.285.17:51:21.23#ibcon#*after write, iclass 37, count 0 2006.285.17:51:21.23#ibcon#*before return 0, iclass 37, count 0 2006.285.17:51:21.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:51:21.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:51:21.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.17:51:21.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.17:51:21.23$vck44/valo=5,734.99 2006.285.17:51:21.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.17:51:21.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.17:51:21.23#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:21.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:51:21.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:51:21.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:51:21.23#ibcon#enter wrdev, iclass 39, count 0 2006.285.17:51:21.23#ibcon#first serial, iclass 39, count 0 2006.285.17:51:21.23#ibcon#enter sib2, iclass 39, count 0 2006.285.17:51:21.23#ibcon#flushed, iclass 39, count 0 2006.285.17:51:21.23#ibcon#about to write, iclass 39, count 0 2006.285.17:51:21.23#ibcon#wrote, iclass 39, count 0 2006.285.17:51:21.23#ibcon#about to read 3, iclass 39, count 0 2006.285.17:51:21.25#ibcon#read 3, iclass 39, count 0 2006.285.17:51:21.69#ibcon#about to read 4, iclass 39, count 0 2006.285.17:51:21.69#ibcon#read 4, iclass 39, count 0 2006.285.17:51:21.69#ibcon#about to read 5, iclass 39, count 0 2006.285.17:51:21.69#ibcon#read 5, iclass 39, count 0 2006.285.17:51:21.69#ibcon#about to read 6, iclass 39, count 0 2006.285.17:51:21.69#ibcon#read 6, iclass 39, count 0 2006.285.17:51:21.69#ibcon#end of sib2, iclass 39, count 0 2006.285.17:51:21.69#ibcon#*mode == 0, iclass 39, count 0 2006.285.17:51:21.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.17:51:21.69#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.17:51:21.69#ibcon#*before write, iclass 39, count 0 2006.285.17:51:21.69#ibcon#enter sib2, iclass 39, count 0 2006.285.17:51:21.69#ibcon#flushed, iclass 39, count 0 2006.285.17:51:21.69#ibcon#about to write, iclass 39, count 0 2006.285.17:51:21.69#ibcon#wrote, iclass 39, count 0 2006.285.17:51:21.69#ibcon#about to read 3, iclass 39, count 0 2006.285.17:51:21.73#ibcon#read 3, iclass 39, count 0 2006.285.17:51:21.73#ibcon#about to read 4, iclass 39, count 0 2006.285.17:51:21.73#ibcon#read 4, iclass 39, count 0 2006.285.17:51:21.73#ibcon#about to read 5, iclass 39, count 0 2006.285.17:51:21.73#ibcon#read 5, iclass 39, count 0 2006.285.17:51:21.73#ibcon#about to read 6, iclass 39, count 0 2006.285.17:51:21.73#ibcon#read 6, iclass 39, count 0 2006.285.17:51:21.73#ibcon#end of sib2, iclass 39, count 0 2006.285.17:51:21.73#ibcon#*after write, iclass 39, count 0 2006.285.17:51:21.73#ibcon#*before return 0, iclass 39, count 0 2006.285.17:51:21.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:51:21.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:51:21.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.17:51:21.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.17:51:21.73$vck44/va=5,3 2006.285.17:51:21.73#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.17:51:21.73#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.17:51:21.73#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:21.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:51:21.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:51:21.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:51:21.73#ibcon#enter wrdev, iclass 4, count 2 2006.285.17:51:21.73#ibcon#first serial, iclass 4, count 2 2006.285.17:51:21.73#ibcon#enter sib2, iclass 4, count 2 2006.285.17:51:21.73#ibcon#flushed, iclass 4, count 2 2006.285.17:51:21.73#ibcon#about to write, iclass 4, count 2 2006.285.17:51:21.73#ibcon#wrote, iclass 4, count 2 2006.285.17:51:21.73#ibcon#about to read 3, iclass 4, count 2 2006.285.17:51:21.73#abcon#<5=/00 0.2 1.0 16.281001014.5\r\n> 2006.285.17:51:21.75#ibcon#read 3, iclass 4, count 2 2006.285.17:51:21.75#ibcon#about to read 4, iclass 4, count 2 2006.285.17:51:21.75#ibcon#read 4, iclass 4, count 2 2006.285.17:51:21.75#ibcon#about to read 5, iclass 4, count 2 2006.285.17:51:21.75#ibcon#read 5, iclass 4, count 2 2006.285.17:51:21.75#ibcon#about to read 6, iclass 4, count 2 2006.285.17:51:21.75#ibcon#read 6, iclass 4, count 2 2006.285.17:51:21.75#ibcon#end of sib2, iclass 4, count 2 2006.285.17:51:21.75#ibcon#*mode == 0, iclass 4, count 2 2006.285.17:51:21.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.17:51:21.75#ibcon#[25=AT05-03\r\n] 2006.285.17:51:21.75#ibcon#*before write, iclass 4, count 2 2006.285.17:51:21.75#ibcon#enter sib2, iclass 4, count 2 2006.285.17:51:21.75#ibcon#flushed, iclass 4, count 2 2006.285.17:51:21.75#ibcon#about to write, iclass 4, count 2 2006.285.17:51:21.75#ibcon#wrote, iclass 4, count 2 2006.285.17:51:21.75#ibcon#about to read 3, iclass 4, count 2 2006.285.17:51:21.75#abcon#{5=INTERFACE CLEAR} 2006.285.17:51:21.78#ibcon#read 3, iclass 4, count 2 2006.285.17:51:21.78#ibcon#about to read 4, iclass 4, count 2 2006.285.17:51:21.78#ibcon#read 4, iclass 4, count 2 2006.285.17:51:21.78#ibcon#about to read 5, iclass 4, count 2 2006.285.17:51:21.78#ibcon#read 5, iclass 4, count 2 2006.285.17:51:21.78#ibcon#about to read 6, iclass 4, count 2 2006.285.17:51:21.78#ibcon#read 6, iclass 4, count 2 2006.285.17:51:21.78#ibcon#end of sib2, iclass 4, count 2 2006.285.17:51:21.78#ibcon#*after write, iclass 4, count 2 2006.285.17:51:21.78#ibcon#*before return 0, iclass 4, count 2 2006.285.17:51:21.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:51:21.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.17:51:21.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.17:51:21.78#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:21.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:51:21.81#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:51:21.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:51:21.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:51:21.90#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:51:21.90#ibcon#first serial, iclass 4, count 0 2006.285.17:51:21.90#ibcon#enter sib2, iclass 4, count 0 2006.285.17:51:21.90#ibcon#flushed, iclass 4, count 0 2006.285.17:51:21.90#ibcon#about to write, iclass 4, count 0 2006.285.17:51:21.90#ibcon#wrote, iclass 4, count 0 2006.285.17:51:21.90#ibcon#about to read 3, iclass 4, count 0 2006.285.17:51:21.92#ibcon#read 3, iclass 4, count 0 2006.285.17:51:21.92#ibcon#about to read 4, iclass 4, count 0 2006.285.17:51:21.92#ibcon#read 4, iclass 4, count 0 2006.285.17:51:21.92#ibcon#about to read 5, iclass 4, count 0 2006.285.17:51:21.92#ibcon#read 5, iclass 4, count 0 2006.285.17:51:21.92#ibcon#about to read 6, iclass 4, count 0 2006.285.17:51:21.92#ibcon#read 6, iclass 4, count 0 2006.285.17:51:21.92#ibcon#end of sib2, iclass 4, count 0 2006.285.17:51:21.92#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:51:21.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:51:21.92#ibcon#[25=USB\r\n] 2006.285.17:51:21.92#ibcon#*before write, iclass 4, count 0 2006.285.17:51:21.92#ibcon#enter sib2, iclass 4, count 0 2006.285.17:51:21.92#ibcon#flushed, iclass 4, count 0 2006.285.17:51:21.92#ibcon#about to write, iclass 4, count 0 2006.285.17:51:21.92#ibcon#wrote, iclass 4, count 0 2006.285.17:51:21.92#ibcon#about to read 3, iclass 4, count 0 2006.285.17:51:21.95#ibcon#read 3, iclass 4, count 0 2006.285.17:51:21.95#ibcon#about to read 4, iclass 4, count 0 2006.285.17:51:21.95#ibcon#read 4, iclass 4, count 0 2006.285.17:51:21.95#ibcon#about to read 5, iclass 4, count 0 2006.285.17:51:21.95#ibcon#read 5, iclass 4, count 0 2006.285.17:51:21.95#ibcon#about to read 6, iclass 4, count 0 2006.285.17:51:21.95#ibcon#read 6, iclass 4, count 0 2006.285.17:51:21.95#ibcon#end of sib2, iclass 4, count 0 2006.285.17:51:21.95#ibcon#*after write, iclass 4, count 0 2006.285.17:51:21.95#ibcon#*before return 0, iclass 4, count 0 2006.285.17:51:21.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:51:21.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.17:51:21.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:51:21.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:51:21.95$vck44/valo=6,814.99 2006.285.17:51:21.95#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.17:51:21.95#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.17:51:21.95#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:21.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:51:21.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:51:21.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:51:21.95#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:51:21.95#ibcon#first serial, iclass 11, count 0 2006.285.17:51:21.95#ibcon#enter sib2, iclass 11, count 0 2006.285.17:51:21.95#ibcon#flushed, iclass 11, count 0 2006.285.17:51:21.95#ibcon#about to write, iclass 11, count 0 2006.285.17:51:21.95#ibcon#wrote, iclass 11, count 0 2006.285.17:51:21.95#ibcon#about to read 3, iclass 11, count 0 2006.285.17:51:21.97#ibcon#read 3, iclass 11, count 0 2006.285.17:51:21.97#ibcon#about to read 4, iclass 11, count 0 2006.285.17:51:21.97#ibcon#read 4, iclass 11, count 0 2006.285.17:51:21.97#ibcon#about to read 5, iclass 11, count 0 2006.285.17:51:21.97#ibcon#read 5, iclass 11, count 0 2006.285.17:51:21.97#ibcon#about to read 6, iclass 11, count 0 2006.285.17:51:21.97#ibcon#read 6, iclass 11, count 0 2006.285.17:51:21.97#ibcon#end of sib2, iclass 11, count 0 2006.285.17:51:21.97#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:51:21.97#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:51:21.97#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.17:51:21.97#ibcon#*before write, iclass 11, count 0 2006.285.17:51:21.97#ibcon#enter sib2, iclass 11, count 0 2006.285.17:51:21.97#ibcon#flushed, iclass 11, count 0 2006.285.17:51:21.97#ibcon#about to write, iclass 11, count 0 2006.285.17:51:21.97#ibcon#wrote, iclass 11, count 0 2006.285.17:51:21.97#ibcon#about to read 3, iclass 11, count 0 2006.285.17:51:22.01#ibcon#read 3, iclass 11, count 0 2006.285.17:51:22.01#ibcon#about to read 4, iclass 11, count 0 2006.285.17:51:22.01#ibcon#read 4, iclass 11, count 0 2006.285.17:51:22.01#ibcon#about to read 5, iclass 11, count 0 2006.285.17:51:22.01#ibcon#read 5, iclass 11, count 0 2006.285.17:51:22.01#ibcon#about to read 6, iclass 11, count 0 2006.285.17:51:22.01#ibcon#read 6, iclass 11, count 0 2006.285.17:51:22.01#ibcon#end of sib2, iclass 11, count 0 2006.285.17:51:22.01#ibcon#*after write, iclass 11, count 0 2006.285.17:51:22.01#ibcon#*before return 0, iclass 11, count 0 2006.285.17:51:22.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:51:22.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:51:22.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:51:22.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:51:22.01$vck44/va=6,4 2006.285.17:51:22.01#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.17:51:22.01#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.17:51:22.01#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:22.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:51:22.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:51:22.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:51:22.07#ibcon#enter wrdev, iclass 13, count 2 2006.285.17:51:22.07#ibcon#first serial, iclass 13, count 2 2006.285.17:51:22.07#ibcon#enter sib2, iclass 13, count 2 2006.285.17:51:22.07#ibcon#flushed, iclass 13, count 2 2006.285.17:51:22.07#ibcon#about to write, iclass 13, count 2 2006.285.17:51:22.07#ibcon#wrote, iclass 13, count 2 2006.285.17:51:22.07#ibcon#about to read 3, iclass 13, count 2 2006.285.17:51:22.09#ibcon#read 3, iclass 13, count 2 2006.285.17:51:22.09#ibcon#about to read 4, iclass 13, count 2 2006.285.17:51:22.09#ibcon#read 4, iclass 13, count 2 2006.285.17:51:22.09#ibcon#about to read 5, iclass 13, count 2 2006.285.17:51:22.09#ibcon#read 5, iclass 13, count 2 2006.285.17:51:22.09#ibcon#about to read 6, iclass 13, count 2 2006.285.17:51:22.09#ibcon#read 6, iclass 13, count 2 2006.285.17:51:22.09#ibcon#end of sib2, iclass 13, count 2 2006.285.17:51:22.09#ibcon#*mode == 0, iclass 13, count 2 2006.285.17:51:22.09#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.17:51:22.09#ibcon#[25=AT06-04\r\n] 2006.285.17:51:22.09#ibcon#*before write, iclass 13, count 2 2006.285.17:51:22.09#ibcon#enter sib2, iclass 13, count 2 2006.285.17:51:22.09#ibcon#flushed, iclass 13, count 2 2006.285.17:51:22.09#ibcon#about to write, iclass 13, count 2 2006.285.17:51:22.09#ibcon#wrote, iclass 13, count 2 2006.285.17:51:22.09#ibcon#about to read 3, iclass 13, count 2 2006.285.17:51:22.12#ibcon#read 3, iclass 13, count 2 2006.285.17:51:22.12#ibcon#about to read 4, iclass 13, count 2 2006.285.17:51:22.12#ibcon#read 4, iclass 13, count 2 2006.285.17:51:22.12#ibcon#about to read 5, iclass 13, count 2 2006.285.17:51:22.12#ibcon#read 5, iclass 13, count 2 2006.285.17:51:22.12#ibcon#about to read 6, iclass 13, count 2 2006.285.17:51:22.12#ibcon#read 6, iclass 13, count 2 2006.285.17:51:22.12#ibcon#end of sib2, iclass 13, count 2 2006.285.17:51:22.12#ibcon#*after write, iclass 13, count 2 2006.285.17:51:22.12#ibcon#*before return 0, iclass 13, count 2 2006.285.17:51:22.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:51:22.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:51:22.12#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.17:51:22.12#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:22.12#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:51:22.24#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:51:22.24#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:51:22.24#ibcon#enter wrdev, iclass 13, count 0 2006.285.17:51:22.24#ibcon#first serial, iclass 13, count 0 2006.285.17:51:22.24#ibcon#enter sib2, iclass 13, count 0 2006.285.17:51:22.24#ibcon#flushed, iclass 13, count 0 2006.285.17:51:22.24#ibcon#about to write, iclass 13, count 0 2006.285.17:51:22.24#ibcon#wrote, iclass 13, count 0 2006.285.17:51:22.24#ibcon#about to read 3, iclass 13, count 0 2006.285.17:51:22.26#ibcon#read 3, iclass 13, count 0 2006.285.17:51:22.26#ibcon#about to read 4, iclass 13, count 0 2006.285.17:51:22.26#ibcon#read 4, iclass 13, count 0 2006.285.17:51:22.26#ibcon#about to read 5, iclass 13, count 0 2006.285.17:51:22.26#ibcon#read 5, iclass 13, count 0 2006.285.17:51:22.26#ibcon#about to read 6, iclass 13, count 0 2006.285.17:51:22.26#ibcon#read 6, iclass 13, count 0 2006.285.17:51:22.26#ibcon#end of sib2, iclass 13, count 0 2006.285.17:51:22.26#ibcon#*mode == 0, iclass 13, count 0 2006.285.17:51:22.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.17:51:22.26#ibcon#[25=USB\r\n] 2006.285.17:51:22.26#ibcon#*before write, iclass 13, count 0 2006.285.17:51:22.26#ibcon#enter sib2, iclass 13, count 0 2006.285.17:51:22.26#ibcon#flushed, iclass 13, count 0 2006.285.17:51:22.26#ibcon#about to write, iclass 13, count 0 2006.285.17:51:22.26#ibcon#wrote, iclass 13, count 0 2006.285.17:51:22.26#ibcon#about to read 3, iclass 13, count 0 2006.285.17:51:22.29#ibcon#read 3, iclass 13, count 0 2006.285.17:51:22.29#ibcon#about to read 4, iclass 13, count 0 2006.285.17:51:22.29#ibcon#read 4, iclass 13, count 0 2006.285.17:51:22.29#ibcon#about to read 5, iclass 13, count 0 2006.285.17:51:22.29#ibcon#read 5, iclass 13, count 0 2006.285.17:51:22.29#ibcon#about to read 6, iclass 13, count 0 2006.285.17:51:22.29#ibcon#read 6, iclass 13, count 0 2006.285.17:51:22.29#ibcon#end of sib2, iclass 13, count 0 2006.285.17:51:22.29#ibcon#*after write, iclass 13, count 0 2006.285.17:51:22.29#ibcon#*before return 0, iclass 13, count 0 2006.285.17:51:22.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:51:22.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:51:22.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.17:51:22.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.17:51:22.29$vck44/valo=7,864.99 2006.285.17:51:22.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.17:51:22.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.17:51:22.29#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:22.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:51:22.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:51:22.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:51:22.29#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:51:22.29#ibcon#first serial, iclass 15, count 0 2006.285.17:51:22.29#ibcon#enter sib2, iclass 15, count 0 2006.285.17:51:22.29#ibcon#flushed, iclass 15, count 0 2006.285.17:51:22.29#ibcon#about to write, iclass 15, count 0 2006.285.17:51:22.29#ibcon#wrote, iclass 15, count 0 2006.285.17:51:22.29#ibcon#about to read 3, iclass 15, count 0 2006.285.17:51:22.31#ibcon#read 3, iclass 15, count 0 2006.285.17:51:22.31#ibcon#about to read 4, iclass 15, count 0 2006.285.17:51:22.31#ibcon#read 4, iclass 15, count 0 2006.285.17:51:22.31#ibcon#about to read 5, iclass 15, count 0 2006.285.17:51:22.31#ibcon#read 5, iclass 15, count 0 2006.285.17:51:22.31#ibcon#about to read 6, iclass 15, count 0 2006.285.17:51:22.31#ibcon#read 6, iclass 15, count 0 2006.285.17:51:22.31#ibcon#end of sib2, iclass 15, count 0 2006.285.17:51:22.31#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:51:22.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:51:22.31#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.17:51:22.31#ibcon#*before write, iclass 15, count 0 2006.285.17:51:22.31#ibcon#enter sib2, iclass 15, count 0 2006.285.17:51:22.31#ibcon#flushed, iclass 15, count 0 2006.285.17:51:22.31#ibcon#about to write, iclass 15, count 0 2006.285.17:51:22.31#ibcon#wrote, iclass 15, count 0 2006.285.17:51:22.31#ibcon#about to read 3, iclass 15, count 0 2006.285.17:51:22.35#ibcon#read 3, iclass 15, count 0 2006.285.17:51:22.35#ibcon#about to read 4, iclass 15, count 0 2006.285.17:51:22.35#ibcon#read 4, iclass 15, count 0 2006.285.17:51:22.35#ibcon#about to read 5, iclass 15, count 0 2006.285.17:51:22.35#ibcon#read 5, iclass 15, count 0 2006.285.17:51:22.35#ibcon#about to read 6, iclass 15, count 0 2006.285.17:51:22.35#ibcon#read 6, iclass 15, count 0 2006.285.17:51:22.35#ibcon#end of sib2, iclass 15, count 0 2006.285.17:51:22.35#ibcon#*after write, iclass 15, count 0 2006.285.17:51:22.35#ibcon#*before return 0, iclass 15, count 0 2006.285.17:51:22.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:51:22.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:51:22.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:51:22.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:51:22.35$vck44/va=7,4 2006.285.17:51:22.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.17:51:22.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.17:51:22.35#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:22.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:51:22.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:51:22.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:51:22.41#ibcon#enter wrdev, iclass 17, count 2 2006.285.17:51:22.41#ibcon#first serial, iclass 17, count 2 2006.285.17:51:22.41#ibcon#enter sib2, iclass 17, count 2 2006.285.17:51:22.41#ibcon#flushed, iclass 17, count 2 2006.285.17:51:22.41#ibcon#about to write, iclass 17, count 2 2006.285.17:51:22.41#ibcon#wrote, iclass 17, count 2 2006.285.17:51:22.41#ibcon#about to read 3, iclass 17, count 2 2006.285.17:51:22.43#ibcon#read 3, iclass 17, count 2 2006.285.17:51:22.43#ibcon#about to read 4, iclass 17, count 2 2006.285.17:51:22.43#ibcon#read 4, iclass 17, count 2 2006.285.17:51:22.43#ibcon#about to read 5, iclass 17, count 2 2006.285.17:51:22.43#ibcon#read 5, iclass 17, count 2 2006.285.17:51:22.43#ibcon#about to read 6, iclass 17, count 2 2006.285.17:51:22.43#ibcon#read 6, iclass 17, count 2 2006.285.17:51:22.43#ibcon#end of sib2, iclass 17, count 2 2006.285.17:51:22.43#ibcon#*mode == 0, iclass 17, count 2 2006.285.17:51:22.43#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.17:51:22.43#ibcon#[25=AT07-04\r\n] 2006.285.17:51:22.43#ibcon#*before write, iclass 17, count 2 2006.285.17:51:22.43#ibcon#enter sib2, iclass 17, count 2 2006.285.17:51:22.43#ibcon#flushed, iclass 17, count 2 2006.285.17:51:22.43#ibcon#about to write, iclass 17, count 2 2006.285.17:51:22.43#ibcon#wrote, iclass 17, count 2 2006.285.17:51:22.43#ibcon#about to read 3, iclass 17, count 2 2006.285.17:51:22.46#ibcon#read 3, iclass 17, count 2 2006.285.17:51:22.46#ibcon#about to read 4, iclass 17, count 2 2006.285.17:51:22.46#ibcon#read 4, iclass 17, count 2 2006.285.17:51:22.46#ibcon#about to read 5, iclass 17, count 2 2006.285.17:51:22.46#ibcon#read 5, iclass 17, count 2 2006.285.17:51:22.46#ibcon#about to read 6, iclass 17, count 2 2006.285.17:51:22.46#ibcon#read 6, iclass 17, count 2 2006.285.17:51:22.46#ibcon#end of sib2, iclass 17, count 2 2006.285.17:51:22.46#ibcon#*after write, iclass 17, count 2 2006.285.17:51:22.46#ibcon#*before return 0, iclass 17, count 2 2006.285.17:51:22.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:51:22.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:51:22.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.17:51:22.46#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:22.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:51:22.58#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:51:22.58#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:51:22.58#ibcon#enter wrdev, iclass 17, count 0 2006.285.17:51:22.58#ibcon#first serial, iclass 17, count 0 2006.285.17:51:22.58#ibcon#enter sib2, iclass 17, count 0 2006.285.17:51:22.58#ibcon#flushed, iclass 17, count 0 2006.285.17:51:22.58#ibcon#about to write, iclass 17, count 0 2006.285.17:51:22.58#ibcon#wrote, iclass 17, count 0 2006.285.17:51:22.58#ibcon#about to read 3, iclass 17, count 0 2006.285.17:51:22.60#ibcon#read 3, iclass 17, count 0 2006.285.17:51:22.60#ibcon#about to read 4, iclass 17, count 0 2006.285.17:51:22.60#ibcon#read 4, iclass 17, count 0 2006.285.17:51:22.60#ibcon#about to read 5, iclass 17, count 0 2006.285.17:51:22.60#ibcon#read 5, iclass 17, count 0 2006.285.17:51:22.60#ibcon#about to read 6, iclass 17, count 0 2006.285.17:51:22.60#ibcon#read 6, iclass 17, count 0 2006.285.17:51:22.60#ibcon#end of sib2, iclass 17, count 0 2006.285.17:51:22.60#ibcon#*mode == 0, iclass 17, count 0 2006.285.17:51:22.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.17:51:22.60#ibcon#[25=USB\r\n] 2006.285.17:51:22.60#ibcon#*before write, iclass 17, count 0 2006.285.17:51:22.60#ibcon#enter sib2, iclass 17, count 0 2006.285.17:51:22.60#ibcon#flushed, iclass 17, count 0 2006.285.17:51:22.60#ibcon#about to write, iclass 17, count 0 2006.285.17:51:22.60#ibcon#wrote, iclass 17, count 0 2006.285.17:51:22.60#ibcon#about to read 3, iclass 17, count 0 2006.285.17:51:22.63#ibcon#read 3, iclass 17, count 0 2006.285.17:51:22.63#ibcon#about to read 4, iclass 17, count 0 2006.285.17:51:22.72#ibcon#read 4, iclass 17, count 0 2006.285.17:51:22.72#ibcon#about to read 5, iclass 17, count 0 2006.285.17:51:22.72#ibcon#read 5, iclass 17, count 0 2006.285.17:51:22.72#ibcon#about to read 6, iclass 17, count 0 2006.285.17:51:22.72#ibcon#read 6, iclass 17, count 0 2006.285.17:51:22.72#ibcon#end of sib2, iclass 17, count 0 2006.285.17:51:22.72#ibcon#*after write, iclass 17, count 0 2006.285.17:51:22.73#ibcon#*before return 0, iclass 17, count 0 2006.285.17:51:22.73#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:51:22.73#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:51:22.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.17:51:22.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.17:51:22.73$vck44/valo=8,884.99 2006.285.17:51:22.73#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.17:51:22.73#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.17:51:22.73#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:22.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:51:22.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:51:22.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:51:22.73#ibcon#enter wrdev, iclass 19, count 0 2006.285.17:51:22.73#ibcon#first serial, iclass 19, count 0 2006.285.17:51:22.73#ibcon#enter sib2, iclass 19, count 0 2006.285.17:51:22.73#ibcon#flushed, iclass 19, count 0 2006.285.17:51:22.73#ibcon#about to write, iclass 19, count 0 2006.285.17:51:22.73#ibcon#wrote, iclass 19, count 0 2006.285.17:51:22.73#ibcon#about to read 3, iclass 19, count 0 2006.285.17:51:22.74#ibcon#read 3, iclass 19, count 0 2006.285.17:51:22.74#ibcon#about to read 4, iclass 19, count 0 2006.285.17:51:22.74#ibcon#read 4, iclass 19, count 0 2006.285.17:51:22.74#ibcon#about to read 5, iclass 19, count 0 2006.285.17:51:22.74#ibcon#read 5, iclass 19, count 0 2006.285.17:51:22.74#ibcon#about to read 6, iclass 19, count 0 2006.285.17:51:22.74#ibcon#read 6, iclass 19, count 0 2006.285.17:51:22.74#ibcon#end of sib2, iclass 19, count 0 2006.285.17:51:22.74#ibcon#*mode == 0, iclass 19, count 0 2006.285.17:51:22.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.17:51:22.74#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.17:51:22.74#ibcon#*before write, iclass 19, count 0 2006.285.17:51:22.74#ibcon#enter sib2, iclass 19, count 0 2006.285.17:51:22.74#ibcon#flushed, iclass 19, count 0 2006.285.17:51:22.74#ibcon#about to write, iclass 19, count 0 2006.285.17:51:22.74#ibcon#wrote, iclass 19, count 0 2006.285.17:51:22.74#ibcon#about to read 3, iclass 19, count 0 2006.285.17:51:22.78#ibcon#read 3, iclass 19, count 0 2006.285.17:51:22.78#ibcon#about to read 4, iclass 19, count 0 2006.285.17:51:22.78#ibcon#read 4, iclass 19, count 0 2006.285.17:51:22.78#ibcon#about to read 5, iclass 19, count 0 2006.285.17:51:22.78#ibcon#read 5, iclass 19, count 0 2006.285.17:51:22.78#ibcon#about to read 6, iclass 19, count 0 2006.285.17:51:22.78#ibcon#read 6, iclass 19, count 0 2006.285.17:51:22.78#ibcon#end of sib2, iclass 19, count 0 2006.285.17:51:22.78#ibcon#*after write, iclass 19, count 0 2006.285.17:51:22.78#ibcon#*before return 0, iclass 19, count 0 2006.285.17:51:22.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:51:22.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:51:22.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.17:51:22.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.17:51:22.78$vck44/va=8,3 2006.285.17:51:22.78#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.17:51:22.78#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.17:51:22.78#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:22.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:51:22.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:51:22.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:51:22.85#ibcon#enter wrdev, iclass 21, count 2 2006.285.17:51:22.85#ibcon#first serial, iclass 21, count 2 2006.285.17:51:22.85#ibcon#enter sib2, iclass 21, count 2 2006.285.17:51:22.85#ibcon#flushed, iclass 21, count 2 2006.285.17:51:22.85#ibcon#about to write, iclass 21, count 2 2006.285.17:51:22.85#ibcon#wrote, iclass 21, count 2 2006.285.17:51:22.85#ibcon#about to read 3, iclass 21, count 2 2006.285.17:51:22.87#ibcon#read 3, iclass 21, count 2 2006.285.17:51:22.87#ibcon#about to read 4, iclass 21, count 2 2006.285.17:51:22.87#ibcon#read 4, iclass 21, count 2 2006.285.17:51:22.87#ibcon#about to read 5, iclass 21, count 2 2006.285.17:51:22.87#ibcon#read 5, iclass 21, count 2 2006.285.17:51:22.87#ibcon#about to read 6, iclass 21, count 2 2006.285.17:51:22.87#ibcon#read 6, iclass 21, count 2 2006.285.17:51:22.87#ibcon#end of sib2, iclass 21, count 2 2006.285.17:51:22.87#ibcon#*mode == 0, iclass 21, count 2 2006.285.17:51:22.87#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.17:51:22.87#ibcon#[25=AT08-03\r\n] 2006.285.17:51:22.87#ibcon#*before write, iclass 21, count 2 2006.285.17:51:22.87#ibcon#enter sib2, iclass 21, count 2 2006.285.17:51:22.87#ibcon#flushed, iclass 21, count 2 2006.285.17:51:22.87#ibcon#about to write, iclass 21, count 2 2006.285.17:51:22.87#ibcon#wrote, iclass 21, count 2 2006.285.17:51:22.87#ibcon#about to read 3, iclass 21, count 2 2006.285.17:51:22.90#ibcon#read 3, iclass 21, count 2 2006.285.17:51:22.90#ibcon#about to read 4, iclass 21, count 2 2006.285.17:51:22.90#ibcon#read 4, iclass 21, count 2 2006.285.17:51:22.90#ibcon#about to read 5, iclass 21, count 2 2006.285.17:51:22.90#ibcon#read 5, iclass 21, count 2 2006.285.17:51:22.90#ibcon#about to read 6, iclass 21, count 2 2006.285.17:51:22.90#ibcon#read 6, iclass 21, count 2 2006.285.17:51:22.90#ibcon#end of sib2, iclass 21, count 2 2006.285.17:51:22.90#ibcon#*after write, iclass 21, count 2 2006.285.17:51:22.90#ibcon#*before return 0, iclass 21, count 2 2006.285.17:51:22.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:51:22.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.17:51:22.90#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.17:51:22.90#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:22.90#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:51:23.02#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:51:23.02#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:51:23.02#ibcon#enter wrdev, iclass 21, count 0 2006.285.17:51:23.02#ibcon#first serial, iclass 21, count 0 2006.285.17:51:23.02#ibcon#enter sib2, iclass 21, count 0 2006.285.17:51:23.02#ibcon#flushed, iclass 21, count 0 2006.285.17:51:23.02#ibcon#about to write, iclass 21, count 0 2006.285.17:51:23.02#ibcon#wrote, iclass 21, count 0 2006.285.17:51:23.02#ibcon#about to read 3, iclass 21, count 0 2006.285.17:51:23.04#ibcon#read 3, iclass 21, count 0 2006.285.17:51:23.04#ibcon#about to read 4, iclass 21, count 0 2006.285.17:51:23.04#ibcon#read 4, iclass 21, count 0 2006.285.17:51:23.04#ibcon#about to read 5, iclass 21, count 0 2006.285.17:51:23.04#ibcon#read 5, iclass 21, count 0 2006.285.17:51:23.04#ibcon#about to read 6, iclass 21, count 0 2006.285.17:51:23.04#ibcon#read 6, iclass 21, count 0 2006.285.17:51:23.04#ibcon#end of sib2, iclass 21, count 0 2006.285.17:51:23.04#ibcon#*mode == 0, iclass 21, count 0 2006.285.17:51:23.04#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.17:51:23.04#ibcon#[25=USB\r\n] 2006.285.17:51:23.04#ibcon#*before write, iclass 21, count 0 2006.285.17:51:23.04#ibcon#enter sib2, iclass 21, count 0 2006.285.17:51:23.04#ibcon#flushed, iclass 21, count 0 2006.285.17:51:23.04#ibcon#about to write, iclass 21, count 0 2006.285.17:51:23.04#ibcon#wrote, iclass 21, count 0 2006.285.17:51:23.04#ibcon#about to read 3, iclass 21, count 0 2006.285.17:51:23.07#ibcon#read 3, iclass 21, count 0 2006.285.17:51:23.07#ibcon#about to read 4, iclass 21, count 0 2006.285.17:51:23.07#ibcon#read 4, iclass 21, count 0 2006.285.17:51:23.07#ibcon#about to read 5, iclass 21, count 0 2006.285.17:51:23.07#ibcon#read 5, iclass 21, count 0 2006.285.17:51:23.07#ibcon#about to read 6, iclass 21, count 0 2006.285.17:51:23.07#ibcon#read 6, iclass 21, count 0 2006.285.17:51:23.07#ibcon#end of sib2, iclass 21, count 0 2006.285.17:51:23.07#ibcon#*after write, iclass 21, count 0 2006.285.17:51:23.07#ibcon#*before return 0, iclass 21, count 0 2006.285.17:51:23.07#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:51:23.07#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.17:51:23.07#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.17:51:23.07#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.17:51:23.07$vck44/vblo=1,629.99 2006.285.17:51:23.07#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.17:51:23.07#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.17:51:23.07#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:23.07#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:51:23.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:51:23.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:51:23.07#ibcon#enter wrdev, iclass 23, count 0 2006.285.17:51:23.07#ibcon#first serial, iclass 23, count 0 2006.285.17:51:23.07#ibcon#enter sib2, iclass 23, count 0 2006.285.17:51:23.07#ibcon#flushed, iclass 23, count 0 2006.285.17:51:23.07#ibcon#about to write, iclass 23, count 0 2006.285.17:51:23.07#ibcon#wrote, iclass 23, count 0 2006.285.17:51:23.07#ibcon#about to read 3, iclass 23, count 0 2006.285.17:51:23.09#ibcon#read 3, iclass 23, count 0 2006.285.17:51:23.09#ibcon#about to read 4, iclass 23, count 0 2006.285.17:51:23.09#ibcon#read 4, iclass 23, count 0 2006.285.17:51:23.09#ibcon#about to read 5, iclass 23, count 0 2006.285.17:51:23.09#ibcon#read 5, iclass 23, count 0 2006.285.17:51:23.09#ibcon#about to read 6, iclass 23, count 0 2006.285.17:51:23.09#ibcon#read 6, iclass 23, count 0 2006.285.17:51:23.09#ibcon#end of sib2, iclass 23, count 0 2006.285.17:51:23.09#ibcon#*mode == 0, iclass 23, count 0 2006.285.17:51:23.09#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.17:51:23.09#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.17:51:23.09#ibcon#*before write, iclass 23, count 0 2006.285.17:51:23.09#ibcon#enter sib2, iclass 23, count 0 2006.285.17:51:23.09#ibcon#flushed, iclass 23, count 0 2006.285.17:51:23.09#ibcon#about to write, iclass 23, count 0 2006.285.17:51:23.09#ibcon#wrote, iclass 23, count 0 2006.285.17:51:23.09#ibcon#about to read 3, iclass 23, count 0 2006.285.17:51:23.13#ibcon#read 3, iclass 23, count 0 2006.285.17:51:23.13#ibcon#about to read 4, iclass 23, count 0 2006.285.17:51:23.13#ibcon#read 4, iclass 23, count 0 2006.285.17:51:23.13#ibcon#about to read 5, iclass 23, count 0 2006.285.17:51:23.13#ibcon#read 5, iclass 23, count 0 2006.285.17:51:23.13#ibcon#about to read 6, iclass 23, count 0 2006.285.17:51:23.13#ibcon#read 6, iclass 23, count 0 2006.285.17:51:23.13#ibcon#end of sib2, iclass 23, count 0 2006.285.17:51:23.13#ibcon#*after write, iclass 23, count 0 2006.285.17:51:23.13#ibcon#*before return 0, iclass 23, count 0 2006.285.17:51:23.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:51:23.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.17:51:23.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.17:51:23.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.17:51:23.13$vck44/vb=1,4 2006.285.17:51:23.13#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.17:51:23.13#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.17:51:23.13#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:23.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:51:23.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:51:23.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:51:23.13#ibcon#enter wrdev, iclass 25, count 2 2006.285.17:51:23.13#ibcon#first serial, iclass 25, count 2 2006.285.17:51:23.13#ibcon#enter sib2, iclass 25, count 2 2006.285.17:51:23.13#ibcon#flushed, iclass 25, count 2 2006.285.17:51:23.13#ibcon#about to write, iclass 25, count 2 2006.285.17:51:23.13#ibcon#wrote, iclass 25, count 2 2006.285.17:51:23.13#ibcon#about to read 3, iclass 25, count 2 2006.285.17:51:23.15#ibcon#read 3, iclass 25, count 2 2006.285.17:51:23.15#ibcon#about to read 4, iclass 25, count 2 2006.285.17:51:23.15#ibcon#read 4, iclass 25, count 2 2006.285.17:51:23.15#ibcon#about to read 5, iclass 25, count 2 2006.285.17:51:23.15#ibcon#read 5, iclass 25, count 2 2006.285.17:51:23.15#ibcon#about to read 6, iclass 25, count 2 2006.285.17:51:23.15#ibcon#read 6, iclass 25, count 2 2006.285.17:51:23.15#ibcon#end of sib2, iclass 25, count 2 2006.285.17:51:23.15#ibcon#*mode == 0, iclass 25, count 2 2006.285.17:51:23.15#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.17:51:23.15#ibcon#[27=AT01-04\r\n] 2006.285.17:51:23.15#ibcon#*before write, iclass 25, count 2 2006.285.17:51:23.15#ibcon#enter sib2, iclass 25, count 2 2006.285.17:51:23.15#ibcon#flushed, iclass 25, count 2 2006.285.17:51:23.15#ibcon#about to write, iclass 25, count 2 2006.285.17:51:23.15#ibcon#wrote, iclass 25, count 2 2006.285.17:51:23.15#ibcon#about to read 3, iclass 25, count 2 2006.285.17:51:23.18#ibcon#read 3, iclass 25, count 2 2006.285.17:51:23.18#ibcon#about to read 4, iclass 25, count 2 2006.285.17:51:23.18#ibcon#read 4, iclass 25, count 2 2006.285.17:51:23.18#ibcon#about to read 5, iclass 25, count 2 2006.285.17:51:23.18#ibcon#read 5, iclass 25, count 2 2006.285.17:51:23.18#ibcon#about to read 6, iclass 25, count 2 2006.285.17:51:23.18#ibcon#read 6, iclass 25, count 2 2006.285.17:51:23.18#ibcon#end of sib2, iclass 25, count 2 2006.285.17:51:23.18#ibcon#*after write, iclass 25, count 2 2006.285.17:51:23.18#ibcon#*before return 0, iclass 25, count 2 2006.285.17:51:23.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:51:23.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.17:51:23.18#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.17:51:23.18#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:23.18#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:51:23.30#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:51:23.30#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:51:23.30#ibcon#enter wrdev, iclass 25, count 0 2006.285.17:51:23.30#ibcon#first serial, iclass 25, count 0 2006.285.17:51:23.30#ibcon#enter sib2, iclass 25, count 0 2006.285.17:51:23.30#ibcon#flushed, iclass 25, count 0 2006.285.17:51:23.30#ibcon#about to write, iclass 25, count 0 2006.285.17:51:23.30#ibcon#wrote, iclass 25, count 0 2006.285.17:51:23.30#ibcon#about to read 3, iclass 25, count 0 2006.285.17:51:23.32#ibcon#read 3, iclass 25, count 0 2006.285.17:51:23.32#ibcon#about to read 4, iclass 25, count 0 2006.285.17:51:23.32#ibcon#read 4, iclass 25, count 0 2006.285.17:51:23.32#ibcon#about to read 5, iclass 25, count 0 2006.285.17:51:23.32#ibcon#read 5, iclass 25, count 0 2006.285.17:51:23.32#ibcon#about to read 6, iclass 25, count 0 2006.285.17:51:23.32#ibcon#read 6, iclass 25, count 0 2006.285.17:51:23.32#ibcon#end of sib2, iclass 25, count 0 2006.285.17:51:23.32#ibcon#*mode == 0, iclass 25, count 0 2006.285.17:51:23.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.17:51:23.32#ibcon#[27=USB\r\n] 2006.285.17:51:23.32#ibcon#*before write, iclass 25, count 0 2006.285.17:51:23.32#ibcon#enter sib2, iclass 25, count 0 2006.285.17:51:23.32#ibcon#flushed, iclass 25, count 0 2006.285.17:51:23.32#ibcon#about to write, iclass 25, count 0 2006.285.17:51:23.32#ibcon#wrote, iclass 25, count 0 2006.285.17:51:23.32#ibcon#about to read 3, iclass 25, count 0 2006.285.17:51:23.35#ibcon#read 3, iclass 25, count 0 2006.285.17:51:23.35#ibcon#about to read 4, iclass 25, count 0 2006.285.17:51:23.35#ibcon#read 4, iclass 25, count 0 2006.285.17:51:23.35#ibcon#about to read 5, iclass 25, count 0 2006.285.17:51:23.35#ibcon#read 5, iclass 25, count 0 2006.285.17:51:23.35#ibcon#about to read 6, iclass 25, count 0 2006.285.17:51:23.35#ibcon#read 6, iclass 25, count 0 2006.285.17:51:23.35#ibcon#end of sib2, iclass 25, count 0 2006.285.17:51:23.35#ibcon#*after write, iclass 25, count 0 2006.285.17:51:23.35#ibcon#*before return 0, iclass 25, count 0 2006.285.17:51:23.35#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:51:23.35#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.17:51:23.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.17:51:23.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.17:51:23.35$vck44/vblo=2,634.99 2006.285.17:51:23.35#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.17:51:23.35#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.17:51:23.35#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:23.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:51:23.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:51:23.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:51:23.35#ibcon#enter wrdev, iclass 27, count 0 2006.285.17:51:23.35#ibcon#first serial, iclass 27, count 0 2006.285.17:51:23.35#ibcon#enter sib2, iclass 27, count 0 2006.285.17:51:23.35#ibcon#flushed, iclass 27, count 0 2006.285.17:51:23.35#ibcon#about to write, iclass 27, count 0 2006.285.17:51:23.35#ibcon#wrote, iclass 27, count 0 2006.285.17:51:23.35#ibcon#about to read 3, iclass 27, count 0 2006.285.17:51:23.37#ibcon#read 3, iclass 27, count 0 2006.285.17:51:23.37#ibcon#about to read 4, iclass 27, count 0 2006.285.17:51:23.37#ibcon#read 4, iclass 27, count 0 2006.285.17:51:23.37#ibcon#about to read 5, iclass 27, count 0 2006.285.17:51:23.37#ibcon#read 5, iclass 27, count 0 2006.285.17:51:23.37#ibcon#about to read 6, iclass 27, count 0 2006.285.17:51:23.37#ibcon#read 6, iclass 27, count 0 2006.285.17:51:23.37#ibcon#end of sib2, iclass 27, count 0 2006.285.17:51:23.37#ibcon#*mode == 0, iclass 27, count 0 2006.285.17:51:23.37#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.17:51:23.37#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.17:51:23.37#ibcon#*before write, iclass 27, count 0 2006.285.17:51:23.37#ibcon#enter sib2, iclass 27, count 0 2006.285.17:51:23.37#ibcon#flushed, iclass 27, count 0 2006.285.17:51:23.37#ibcon#about to write, iclass 27, count 0 2006.285.17:51:23.37#ibcon#wrote, iclass 27, count 0 2006.285.17:51:23.37#ibcon#about to read 3, iclass 27, count 0 2006.285.17:51:23.41#ibcon#read 3, iclass 27, count 0 2006.285.17:51:23.41#ibcon#about to read 4, iclass 27, count 0 2006.285.17:51:23.41#ibcon#read 4, iclass 27, count 0 2006.285.17:51:23.41#ibcon#about to read 5, iclass 27, count 0 2006.285.17:51:23.41#ibcon#read 5, iclass 27, count 0 2006.285.17:51:23.41#ibcon#about to read 6, iclass 27, count 0 2006.285.17:51:23.41#ibcon#read 6, iclass 27, count 0 2006.285.17:51:23.41#ibcon#end of sib2, iclass 27, count 0 2006.285.17:51:23.41#ibcon#*after write, iclass 27, count 0 2006.285.17:51:23.41#ibcon#*before return 0, iclass 27, count 0 2006.285.17:51:23.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:51:23.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.17:51:23.41#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.17:51:23.41#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.17:51:23.41$vck44/vb=2,5 2006.285.17:51:23.41#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.17:51:23.41#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.17:51:23.41#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:23.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:51:23.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:51:23.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:51:23.47#ibcon#enter wrdev, iclass 29, count 2 2006.285.17:51:23.47#ibcon#first serial, iclass 29, count 2 2006.285.17:51:23.47#ibcon#enter sib2, iclass 29, count 2 2006.285.17:51:23.47#ibcon#flushed, iclass 29, count 2 2006.285.17:51:23.47#ibcon#about to write, iclass 29, count 2 2006.285.17:51:23.47#ibcon#wrote, iclass 29, count 2 2006.285.17:51:23.47#ibcon#about to read 3, iclass 29, count 2 2006.285.17:51:23.49#ibcon#read 3, iclass 29, count 2 2006.285.17:51:23.49#ibcon#about to read 4, iclass 29, count 2 2006.285.17:51:23.49#ibcon#read 4, iclass 29, count 2 2006.285.17:51:23.49#ibcon#about to read 5, iclass 29, count 2 2006.285.17:51:23.49#ibcon#read 5, iclass 29, count 2 2006.285.17:51:23.49#ibcon#about to read 6, iclass 29, count 2 2006.285.17:51:23.49#ibcon#read 6, iclass 29, count 2 2006.285.17:51:23.49#ibcon#end of sib2, iclass 29, count 2 2006.285.17:51:23.49#ibcon#*mode == 0, iclass 29, count 2 2006.285.17:51:23.49#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.17:51:23.49#ibcon#[27=AT02-05\r\n] 2006.285.17:51:23.49#ibcon#*before write, iclass 29, count 2 2006.285.17:51:23.49#ibcon#enter sib2, iclass 29, count 2 2006.285.17:51:23.49#ibcon#flushed, iclass 29, count 2 2006.285.17:51:23.49#ibcon#about to write, iclass 29, count 2 2006.285.17:51:23.49#ibcon#wrote, iclass 29, count 2 2006.285.17:51:23.49#ibcon#about to read 3, iclass 29, count 2 2006.285.17:51:23.52#ibcon#read 3, iclass 29, count 2 2006.285.17:51:23.52#ibcon#about to read 4, iclass 29, count 2 2006.285.17:51:23.52#ibcon#read 4, iclass 29, count 2 2006.285.17:51:23.52#ibcon#about to read 5, iclass 29, count 2 2006.285.17:51:23.52#ibcon#read 5, iclass 29, count 2 2006.285.17:51:23.52#ibcon#about to read 6, iclass 29, count 2 2006.285.17:51:23.52#ibcon#read 6, iclass 29, count 2 2006.285.17:51:23.52#ibcon#end of sib2, iclass 29, count 2 2006.285.17:51:23.52#ibcon#*after write, iclass 29, count 2 2006.285.17:51:23.52#ibcon#*before return 0, iclass 29, count 2 2006.285.17:51:23.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:51:23.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.17:51:23.52#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.17:51:23.52#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:23.52#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:51:23.64#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:51:23.67#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:51:23.67#ibcon#enter wrdev, iclass 29, count 0 2006.285.17:51:23.67#ibcon#first serial, iclass 29, count 0 2006.285.17:51:23.67#ibcon#enter sib2, iclass 29, count 0 2006.285.17:51:23.67#ibcon#flushed, iclass 29, count 0 2006.285.17:51:23.67#ibcon#about to write, iclass 29, count 0 2006.285.17:51:23.67#ibcon#wrote, iclass 29, count 0 2006.285.17:51:23.67#ibcon#about to read 3, iclass 29, count 0 2006.285.17:51:23.68#ibcon#read 3, iclass 29, count 0 2006.285.17:51:23.68#ibcon#about to read 4, iclass 29, count 0 2006.285.17:51:23.68#ibcon#read 4, iclass 29, count 0 2006.285.17:51:23.68#ibcon#about to read 5, iclass 29, count 0 2006.285.17:51:23.68#ibcon#read 5, iclass 29, count 0 2006.285.17:51:23.68#ibcon#about to read 6, iclass 29, count 0 2006.285.17:51:23.68#ibcon#read 6, iclass 29, count 0 2006.285.17:51:23.68#ibcon#end of sib2, iclass 29, count 0 2006.285.17:51:23.68#ibcon#*mode == 0, iclass 29, count 0 2006.285.17:51:23.68#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.17:51:23.68#ibcon#[27=USB\r\n] 2006.285.17:51:23.68#ibcon#*before write, iclass 29, count 0 2006.285.17:51:23.68#ibcon#enter sib2, iclass 29, count 0 2006.285.17:51:23.68#ibcon#flushed, iclass 29, count 0 2006.285.17:51:23.68#ibcon#about to write, iclass 29, count 0 2006.285.17:51:23.68#ibcon#wrote, iclass 29, count 0 2006.285.17:51:23.68#ibcon#about to read 3, iclass 29, count 0 2006.285.17:51:23.71#ibcon#read 3, iclass 29, count 0 2006.285.17:51:23.71#ibcon#about to read 4, iclass 29, count 0 2006.285.17:51:23.71#ibcon#read 4, iclass 29, count 0 2006.285.17:51:23.71#ibcon#about to read 5, iclass 29, count 0 2006.285.17:51:23.71#ibcon#read 5, iclass 29, count 0 2006.285.17:51:23.71#ibcon#about to read 6, iclass 29, count 0 2006.285.17:51:23.71#ibcon#read 6, iclass 29, count 0 2006.285.17:51:23.71#ibcon#end of sib2, iclass 29, count 0 2006.285.17:51:23.71#ibcon#*after write, iclass 29, count 0 2006.285.17:51:23.71#ibcon#*before return 0, iclass 29, count 0 2006.285.17:51:23.71#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:51:23.71#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.17:51:23.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.17:51:23.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.17:51:23.71$vck44/vblo=3,649.99 2006.285.17:51:23.71#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.17:51:23.71#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.17:51:23.71#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:23.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:51:23.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:51:23.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:51:23.71#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:51:23.71#ibcon#first serial, iclass 31, count 0 2006.285.17:51:23.71#ibcon#enter sib2, iclass 31, count 0 2006.285.17:51:23.71#ibcon#flushed, iclass 31, count 0 2006.285.17:51:23.71#ibcon#about to write, iclass 31, count 0 2006.285.17:51:23.71#ibcon#wrote, iclass 31, count 0 2006.285.17:51:23.71#ibcon#about to read 3, iclass 31, count 0 2006.285.17:51:23.73#ibcon#read 3, iclass 31, count 0 2006.285.17:51:23.73#ibcon#about to read 4, iclass 31, count 0 2006.285.17:51:23.73#ibcon#read 4, iclass 31, count 0 2006.285.17:51:23.73#ibcon#about to read 5, iclass 31, count 0 2006.285.17:51:23.73#ibcon#read 5, iclass 31, count 0 2006.285.17:51:23.73#ibcon#about to read 6, iclass 31, count 0 2006.285.17:51:23.73#ibcon#read 6, iclass 31, count 0 2006.285.17:51:23.73#ibcon#end of sib2, iclass 31, count 0 2006.285.17:51:23.73#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:51:23.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:51:23.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.17:51:23.73#ibcon#*before write, iclass 31, count 0 2006.285.17:51:23.73#ibcon#enter sib2, iclass 31, count 0 2006.285.17:51:23.73#ibcon#flushed, iclass 31, count 0 2006.285.17:51:23.73#ibcon#about to write, iclass 31, count 0 2006.285.17:51:23.73#ibcon#wrote, iclass 31, count 0 2006.285.17:51:23.73#ibcon#about to read 3, iclass 31, count 0 2006.285.17:51:23.77#ibcon#read 3, iclass 31, count 0 2006.285.17:51:23.77#ibcon#about to read 4, iclass 31, count 0 2006.285.17:51:23.77#ibcon#read 4, iclass 31, count 0 2006.285.17:51:23.77#ibcon#about to read 5, iclass 31, count 0 2006.285.17:51:23.77#ibcon#read 5, iclass 31, count 0 2006.285.17:51:23.77#ibcon#about to read 6, iclass 31, count 0 2006.285.17:51:23.77#ibcon#read 6, iclass 31, count 0 2006.285.17:51:23.77#ibcon#end of sib2, iclass 31, count 0 2006.285.17:51:23.77#ibcon#*after write, iclass 31, count 0 2006.285.17:51:23.77#ibcon#*before return 0, iclass 31, count 0 2006.285.17:51:23.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:51:23.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.17:51:23.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:51:23.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:51:23.77$vck44/vb=3,4 2006.285.17:51:23.77#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.17:51:23.77#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.17:51:23.77#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:23.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:51:23.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:51:23.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:51:23.83#ibcon#enter wrdev, iclass 33, count 2 2006.285.17:51:23.83#ibcon#first serial, iclass 33, count 2 2006.285.17:51:23.83#ibcon#enter sib2, iclass 33, count 2 2006.285.17:51:23.83#ibcon#flushed, iclass 33, count 2 2006.285.17:51:23.83#ibcon#about to write, iclass 33, count 2 2006.285.17:51:23.83#ibcon#wrote, iclass 33, count 2 2006.285.17:51:23.83#ibcon#about to read 3, iclass 33, count 2 2006.285.17:51:23.85#ibcon#read 3, iclass 33, count 2 2006.285.17:51:23.85#ibcon#about to read 4, iclass 33, count 2 2006.285.17:51:23.85#ibcon#read 4, iclass 33, count 2 2006.285.17:51:23.85#ibcon#about to read 5, iclass 33, count 2 2006.285.17:51:23.85#ibcon#read 5, iclass 33, count 2 2006.285.17:51:23.85#ibcon#about to read 6, iclass 33, count 2 2006.285.17:51:23.85#ibcon#read 6, iclass 33, count 2 2006.285.17:51:23.85#ibcon#end of sib2, iclass 33, count 2 2006.285.17:51:23.85#ibcon#*mode == 0, iclass 33, count 2 2006.285.17:51:23.85#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.17:51:23.85#ibcon#[27=AT03-04\r\n] 2006.285.17:51:23.85#ibcon#*before write, iclass 33, count 2 2006.285.17:51:23.85#ibcon#enter sib2, iclass 33, count 2 2006.285.17:51:23.85#ibcon#flushed, iclass 33, count 2 2006.285.17:51:23.85#ibcon#about to write, iclass 33, count 2 2006.285.17:51:23.85#ibcon#wrote, iclass 33, count 2 2006.285.17:51:23.85#ibcon#about to read 3, iclass 33, count 2 2006.285.17:51:23.88#ibcon#read 3, iclass 33, count 2 2006.285.17:51:23.88#ibcon#about to read 4, iclass 33, count 2 2006.285.17:51:23.88#ibcon#read 4, iclass 33, count 2 2006.285.17:51:23.88#ibcon#about to read 5, iclass 33, count 2 2006.285.17:51:23.88#ibcon#read 5, iclass 33, count 2 2006.285.17:51:23.88#ibcon#about to read 6, iclass 33, count 2 2006.285.17:51:23.88#ibcon#read 6, iclass 33, count 2 2006.285.17:51:23.88#ibcon#end of sib2, iclass 33, count 2 2006.285.17:51:23.88#ibcon#*after write, iclass 33, count 2 2006.285.17:51:23.88#ibcon#*before return 0, iclass 33, count 2 2006.285.17:51:23.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:51:23.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.17:51:23.88#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.17:51:23.88#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:23.88#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:51:24.00#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:51:24.00#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:51:24.00#ibcon#enter wrdev, iclass 33, count 0 2006.285.17:51:24.00#ibcon#first serial, iclass 33, count 0 2006.285.17:51:24.00#ibcon#enter sib2, iclass 33, count 0 2006.285.17:51:24.00#ibcon#flushed, iclass 33, count 0 2006.285.17:51:24.00#ibcon#about to write, iclass 33, count 0 2006.285.17:51:24.00#ibcon#wrote, iclass 33, count 0 2006.285.17:51:24.00#ibcon#about to read 3, iclass 33, count 0 2006.285.17:51:24.02#ibcon#read 3, iclass 33, count 0 2006.285.17:51:24.02#ibcon#about to read 4, iclass 33, count 0 2006.285.17:51:24.02#ibcon#read 4, iclass 33, count 0 2006.285.17:51:24.02#ibcon#about to read 5, iclass 33, count 0 2006.285.17:51:24.02#ibcon#read 5, iclass 33, count 0 2006.285.17:51:24.02#ibcon#about to read 6, iclass 33, count 0 2006.285.17:51:24.02#ibcon#read 6, iclass 33, count 0 2006.285.17:51:24.02#ibcon#end of sib2, iclass 33, count 0 2006.285.17:51:24.02#ibcon#*mode == 0, iclass 33, count 0 2006.285.17:51:24.02#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.17:51:24.02#ibcon#[27=USB\r\n] 2006.285.17:51:24.02#ibcon#*before write, iclass 33, count 0 2006.285.17:51:24.02#ibcon#enter sib2, iclass 33, count 0 2006.285.17:51:24.02#ibcon#flushed, iclass 33, count 0 2006.285.17:51:24.02#ibcon#about to write, iclass 33, count 0 2006.285.17:51:24.02#ibcon#wrote, iclass 33, count 0 2006.285.17:51:24.02#ibcon#about to read 3, iclass 33, count 0 2006.285.17:51:24.05#ibcon#read 3, iclass 33, count 0 2006.285.17:51:24.05#ibcon#about to read 4, iclass 33, count 0 2006.285.17:51:24.05#ibcon#read 4, iclass 33, count 0 2006.285.17:51:24.05#ibcon#about to read 5, iclass 33, count 0 2006.285.17:51:24.05#ibcon#read 5, iclass 33, count 0 2006.285.17:51:24.05#ibcon#about to read 6, iclass 33, count 0 2006.285.17:51:24.05#ibcon#read 6, iclass 33, count 0 2006.285.17:51:24.05#ibcon#end of sib2, iclass 33, count 0 2006.285.17:51:24.05#ibcon#*after write, iclass 33, count 0 2006.285.17:51:24.05#ibcon#*before return 0, iclass 33, count 0 2006.285.17:51:24.05#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:51:24.05#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.17:51:24.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.17:51:24.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.17:51:24.05$vck44/vblo=4,679.99 2006.285.17:51:24.05#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.17:51:24.05#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.17:51:24.05#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:24.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:51:24.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:51:24.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:51:24.05#ibcon#enter wrdev, iclass 35, count 0 2006.285.17:51:24.05#ibcon#first serial, iclass 35, count 0 2006.285.17:51:24.05#ibcon#enter sib2, iclass 35, count 0 2006.285.17:51:24.05#ibcon#flushed, iclass 35, count 0 2006.285.17:51:24.05#ibcon#about to write, iclass 35, count 0 2006.285.17:51:24.05#ibcon#wrote, iclass 35, count 0 2006.285.17:51:24.05#ibcon#about to read 3, iclass 35, count 0 2006.285.17:51:24.07#ibcon#read 3, iclass 35, count 0 2006.285.17:51:24.07#ibcon#about to read 4, iclass 35, count 0 2006.285.17:51:24.07#ibcon#read 4, iclass 35, count 0 2006.285.17:51:24.07#ibcon#about to read 5, iclass 35, count 0 2006.285.17:51:24.07#ibcon#read 5, iclass 35, count 0 2006.285.17:51:24.07#ibcon#about to read 6, iclass 35, count 0 2006.285.17:51:24.07#ibcon#read 6, iclass 35, count 0 2006.285.17:51:24.07#ibcon#end of sib2, iclass 35, count 0 2006.285.17:51:24.07#ibcon#*mode == 0, iclass 35, count 0 2006.285.17:51:24.07#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.17:51:24.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.17:51:24.07#ibcon#*before write, iclass 35, count 0 2006.285.17:51:24.07#ibcon#enter sib2, iclass 35, count 0 2006.285.17:51:24.07#ibcon#flushed, iclass 35, count 0 2006.285.17:51:24.07#ibcon#about to write, iclass 35, count 0 2006.285.17:51:24.07#ibcon#wrote, iclass 35, count 0 2006.285.17:51:24.07#ibcon#about to read 3, iclass 35, count 0 2006.285.17:51:24.11#ibcon#read 3, iclass 35, count 0 2006.285.17:51:24.11#ibcon#about to read 4, iclass 35, count 0 2006.285.17:51:24.11#ibcon#read 4, iclass 35, count 0 2006.285.17:51:24.11#ibcon#about to read 5, iclass 35, count 0 2006.285.17:51:24.11#ibcon#read 5, iclass 35, count 0 2006.285.17:51:24.11#ibcon#about to read 6, iclass 35, count 0 2006.285.17:51:24.11#ibcon#read 6, iclass 35, count 0 2006.285.17:51:24.11#ibcon#end of sib2, iclass 35, count 0 2006.285.17:51:24.11#ibcon#*after write, iclass 35, count 0 2006.285.17:51:24.11#ibcon#*before return 0, iclass 35, count 0 2006.285.17:51:24.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:51:24.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.17:51:24.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.17:51:24.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.17:51:24.11$vck44/vb=4,5 2006.285.17:51:24.11#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.17:51:24.11#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.17:51:24.11#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:24.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:51:24.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:51:24.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:51:24.17#ibcon#enter wrdev, iclass 37, count 2 2006.285.17:51:24.17#ibcon#first serial, iclass 37, count 2 2006.285.17:51:24.17#ibcon#enter sib2, iclass 37, count 2 2006.285.17:51:24.17#ibcon#flushed, iclass 37, count 2 2006.285.17:51:24.17#ibcon#about to write, iclass 37, count 2 2006.285.17:51:24.17#ibcon#wrote, iclass 37, count 2 2006.285.17:51:24.17#ibcon#about to read 3, iclass 37, count 2 2006.285.17:51:24.19#ibcon#read 3, iclass 37, count 2 2006.285.17:51:24.19#ibcon#about to read 4, iclass 37, count 2 2006.285.17:51:24.19#ibcon#read 4, iclass 37, count 2 2006.285.17:51:24.19#ibcon#about to read 5, iclass 37, count 2 2006.285.17:51:24.19#ibcon#read 5, iclass 37, count 2 2006.285.17:51:24.19#ibcon#about to read 6, iclass 37, count 2 2006.285.17:51:24.19#ibcon#read 6, iclass 37, count 2 2006.285.17:51:24.19#ibcon#end of sib2, iclass 37, count 2 2006.285.17:51:24.19#ibcon#*mode == 0, iclass 37, count 2 2006.285.17:51:24.19#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.17:51:24.19#ibcon#[27=AT04-05\r\n] 2006.285.17:51:24.19#ibcon#*before write, iclass 37, count 2 2006.285.17:51:24.19#ibcon#enter sib2, iclass 37, count 2 2006.285.17:51:24.19#ibcon#flushed, iclass 37, count 2 2006.285.17:51:24.19#ibcon#about to write, iclass 37, count 2 2006.285.17:51:24.19#ibcon#wrote, iclass 37, count 2 2006.285.17:51:24.19#ibcon#about to read 3, iclass 37, count 2 2006.285.17:51:24.22#ibcon#read 3, iclass 37, count 2 2006.285.17:51:24.22#ibcon#about to read 4, iclass 37, count 2 2006.285.17:51:24.22#ibcon#read 4, iclass 37, count 2 2006.285.17:51:24.22#ibcon#about to read 5, iclass 37, count 2 2006.285.17:51:24.22#ibcon#read 5, iclass 37, count 2 2006.285.17:51:24.22#ibcon#about to read 6, iclass 37, count 2 2006.285.17:51:24.22#ibcon#read 6, iclass 37, count 2 2006.285.17:51:24.22#ibcon#end of sib2, iclass 37, count 2 2006.285.17:51:24.22#ibcon#*after write, iclass 37, count 2 2006.285.17:51:24.22#ibcon#*before return 0, iclass 37, count 2 2006.285.17:51:24.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:51:24.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.17:51:24.22#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.17:51:24.22#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:24.22#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:51:24.34#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:51:24.34#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:51:24.34#ibcon#enter wrdev, iclass 37, count 0 2006.285.17:51:24.34#ibcon#first serial, iclass 37, count 0 2006.285.17:51:24.34#ibcon#enter sib2, iclass 37, count 0 2006.285.17:51:24.34#ibcon#flushed, iclass 37, count 0 2006.285.17:51:24.34#ibcon#about to write, iclass 37, count 0 2006.285.17:51:24.34#ibcon#wrote, iclass 37, count 0 2006.285.17:51:24.34#ibcon#about to read 3, iclass 37, count 0 2006.285.17:51:24.36#ibcon#read 3, iclass 37, count 0 2006.285.17:51:24.36#ibcon#about to read 4, iclass 37, count 0 2006.285.17:51:24.36#ibcon#read 4, iclass 37, count 0 2006.285.17:51:24.36#ibcon#about to read 5, iclass 37, count 0 2006.285.17:51:24.36#ibcon#read 5, iclass 37, count 0 2006.285.17:51:24.36#ibcon#about to read 6, iclass 37, count 0 2006.285.17:51:24.36#ibcon#read 6, iclass 37, count 0 2006.285.17:51:24.36#ibcon#end of sib2, iclass 37, count 0 2006.285.17:51:24.36#ibcon#*mode == 0, iclass 37, count 0 2006.285.17:51:24.36#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.17:51:24.36#ibcon#[27=USB\r\n] 2006.285.17:51:24.36#ibcon#*before write, iclass 37, count 0 2006.285.17:51:24.36#ibcon#enter sib2, iclass 37, count 0 2006.285.17:51:24.36#ibcon#flushed, iclass 37, count 0 2006.285.17:51:24.36#ibcon#about to write, iclass 37, count 0 2006.285.17:51:24.36#ibcon#wrote, iclass 37, count 0 2006.285.17:51:24.36#ibcon#about to read 3, iclass 37, count 0 2006.285.17:51:24.39#ibcon#read 3, iclass 37, count 0 2006.285.17:51:24.39#ibcon#about to read 4, iclass 37, count 0 2006.285.17:51:24.39#ibcon#read 4, iclass 37, count 0 2006.285.17:51:24.39#ibcon#about to read 5, iclass 37, count 0 2006.285.17:51:24.39#ibcon#read 5, iclass 37, count 0 2006.285.17:51:24.39#ibcon#about to read 6, iclass 37, count 0 2006.285.17:51:24.39#ibcon#read 6, iclass 37, count 0 2006.285.17:51:24.39#ibcon#end of sib2, iclass 37, count 0 2006.285.17:51:24.39#ibcon#*after write, iclass 37, count 0 2006.285.17:51:24.39#ibcon#*before return 0, iclass 37, count 0 2006.285.17:51:24.39#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:51:24.39#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.17:51:24.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.17:51:24.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.17:51:24.39$vck44/vblo=5,709.99 2006.285.17:51:24.39#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.17:51:24.39#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.17:51:24.39#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:24.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:51:24.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:51:24.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:51:24.39#ibcon#enter wrdev, iclass 39, count 0 2006.285.17:51:24.39#ibcon#first serial, iclass 39, count 0 2006.285.17:51:24.39#ibcon#enter sib2, iclass 39, count 0 2006.285.17:51:24.39#ibcon#flushed, iclass 39, count 0 2006.285.17:51:24.39#ibcon#about to write, iclass 39, count 0 2006.285.17:51:24.39#ibcon#wrote, iclass 39, count 0 2006.285.17:51:24.39#ibcon#about to read 3, iclass 39, count 0 2006.285.17:51:24.41#ibcon#read 3, iclass 39, count 0 2006.285.17:51:24.41#ibcon#about to read 4, iclass 39, count 0 2006.285.17:51:24.41#ibcon#read 4, iclass 39, count 0 2006.285.17:51:24.41#ibcon#about to read 5, iclass 39, count 0 2006.285.17:51:24.41#ibcon#read 5, iclass 39, count 0 2006.285.17:51:24.41#ibcon#about to read 6, iclass 39, count 0 2006.285.17:51:24.41#ibcon#read 6, iclass 39, count 0 2006.285.17:51:24.41#ibcon#end of sib2, iclass 39, count 0 2006.285.17:51:24.41#ibcon#*mode == 0, iclass 39, count 0 2006.285.17:51:24.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.17:51:24.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.17:51:24.41#ibcon#*before write, iclass 39, count 0 2006.285.17:51:24.41#ibcon#enter sib2, iclass 39, count 0 2006.285.17:51:24.41#ibcon#flushed, iclass 39, count 0 2006.285.17:51:24.41#ibcon#about to write, iclass 39, count 0 2006.285.17:51:24.41#ibcon#wrote, iclass 39, count 0 2006.285.17:51:24.41#ibcon#about to read 3, iclass 39, count 0 2006.285.17:51:24.45#ibcon#read 3, iclass 39, count 0 2006.285.17:51:24.45#ibcon#about to read 4, iclass 39, count 0 2006.285.17:51:24.45#ibcon#read 4, iclass 39, count 0 2006.285.17:51:24.45#ibcon#about to read 5, iclass 39, count 0 2006.285.17:51:24.45#ibcon#read 5, iclass 39, count 0 2006.285.17:51:24.45#ibcon#about to read 6, iclass 39, count 0 2006.285.17:51:24.45#ibcon#read 6, iclass 39, count 0 2006.285.17:51:24.45#ibcon#end of sib2, iclass 39, count 0 2006.285.17:51:24.45#ibcon#*after write, iclass 39, count 0 2006.285.17:51:24.45#ibcon#*before return 0, iclass 39, count 0 2006.285.17:51:24.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:51:24.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.17:51:24.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.17:51:24.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.17:51:24.45$vck44/vb=5,4 2006.285.17:51:24.45#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.17:51:24.45#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.17:51:24.45#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:24.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.17:51:24.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.17:51:24.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.17:51:24.51#ibcon#enter wrdev, iclass 3, count 2 2006.285.17:51:24.51#ibcon#first serial, iclass 3, count 2 2006.285.17:51:24.51#ibcon#enter sib2, iclass 3, count 2 2006.285.17:51:24.51#ibcon#flushed, iclass 3, count 2 2006.285.17:51:24.51#ibcon#about to write, iclass 3, count 2 2006.285.17:51:24.51#ibcon#wrote, iclass 3, count 2 2006.285.17:51:24.51#ibcon#about to read 3, iclass 3, count 2 2006.285.17:51:24.53#ibcon#read 3, iclass 3, count 2 2006.285.17:51:24.53#ibcon#about to read 4, iclass 3, count 2 2006.285.17:51:24.53#ibcon#read 4, iclass 3, count 2 2006.285.17:51:24.53#ibcon#about to read 5, iclass 3, count 2 2006.285.17:51:24.53#ibcon#read 5, iclass 3, count 2 2006.285.17:51:24.53#ibcon#about to read 6, iclass 3, count 2 2006.285.17:51:24.53#ibcon#read 6, iclass 3, count 2 2006.285.17:51:24.53#ibcon#end of sib2, iclass 3, count 2 2006.285.17:51:24.53#ibcon#*mode == 0, iclass 3, count 2 2006.285.17:51:24.53#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.17:51:24.53#ibcon#[27=AT05-04\r\n] 2006.285.17:51:24.53#ibcon#*before write, iclass 3, count 2 2006.285.17:51:24.53#ibcon#enter sib2, iclass 3, count 2 2006.285.17:51:24.53#ibcon#flushed, iclass 3, count 2 2006.285.17:51:24.53#ibcon#about to write, iclass 3, count 2 2006.285.17:51:24.53#ibcon#wrote, iclass 3, count 2 2006.285.17:51:24.53#ibcon#about to read 3, iclass 3, count 2 2006.285.17:51:24.56#ibcon#read 3, iclass 3, count 2 2006.285.17:51:24.56#ibcon#about to read 4, iclass 3, count 2 2006.285.17:51:24.56#ibcon#read 4, iclass 3, count 2 2006.285.17:51:24.56#ibcon#about to read 5, iclass 3, count 2 2006.285.17:51:24.56#ibcon#read 5, iclass 3, count 2 2006.285.17:51:24.56#ibcon#about to read 6, iclass 3, count 2 2006.285.17:51:24.56#ibcon#read 6, iclass 3, count 2 2006.285.17:51:24.56#ibcon#end of sib2, iclass 3, count 2 2006.285.17:51:24.56#ibcon#*after write, iclass 3, count 2 2006.285.17:51:24.56#ibcon#*before return 0, iclass 3, count 2 2006.285.17:51:24.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.17:51:24.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.17:51:24.56#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.17:51:24.56#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:24.56#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.17:51:24.68#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.17:51:24.70#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.17:51:24.70#ibcon#enter wrdev, iclass 3, count 0 2006.285.17:51:24.70#ibcon#first serial, iclass 3, count 0 2006.285.17:51:24.70#ibcon#enter sib2, iclass 3, count 0 2006.285.17:51:24.70#ibcon#flushed, iclass 3, count 0 2006.285.17:51:24.70#ibcon#about to write, iclass 3, count 0 2006.285.17:51:24.70#ibcon#wrote, iclass 3, count 0 2006.285.17:51:24.70#ibcon#about to read 3, iclass 3, count 0 2006.285.17:51:24.71#ibcon#read 3, iclass 3, count 0 2006.285.17:51:24.71#ibcon#about to read 4, iclass 3, count 0 2006.285.17:51:24.71#ibcon#read 4, iclass 3, count 0 2006.285.17:51:24.71#ibcon#about to read 5, iclass 3, count 0 2006.285.17:51:24.71#ibcon#read 5, iclass 3, count 0 2006.285.17:51:24.71#ibcon#about to read 6, iclass 3, count 0 2006.285.17:51:24.71#ibcon#read 6, iclass 3, count 0 2006.285.17:51:24.71#ibcon#end of sib2, iclass 3, count 0 2006.285.17:51:24.71#ibcon#*mode == 0, iclass 3, count 0 2006.285.17:51:24.71#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.17:51:24.71#ibcon#[27=USB\r\n] 2006.285.17:51:24.71#ibcon#*before write, iclass 3, count 0 2006.285.17:51:24.71#ibcon#enter sib2, iclass 3, count 0 2006.285.17:51:24.71#ibcon#flushed, iclass 3, count 0 2006.285.17:51:24.71#ibcon#about to write, iclass 3, count 0 2006.285.17:51:24.71#ibcon#wrote, iclass 3, count 0 2006.285.17:51:24.71#ibcon#about to read 3, iclass 3, count 0 2006.285.17:51:24.74#ibcon#read 3, iclass 3, count 0 2006.285.17:51:24.74#ibcon#about to read 4, iclass 3, count 0 2006.285.17:51:24.74#ibcon#read 4, iclass 3, count 0 2006.285.17:51:24.74#ibcon#about to read 5, iclass 3, count 0 2006.285.17:51:24.74#ibcon#read 5, iclass 3, count 0 2006.285.17:51:24.74#ibcon#about to read 6, iclass 3, count 0 2006.285.17:51:24.74#ibcon#read 6, iclass 3, count 0 2006.285.17:51:24.74#ibcon#end of sib2, iclass 3, count 0 2006.285.17:51:24.74#ibcon#*after write, iclass 3, count 0 2006.285.17:51:24.74#ibcon#*before return 0, iclass 3, count 0 2006.285.17:51:24.74#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.17:51:24.74#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.17:51:24.74#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.17:51:24.74#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.17:51:24.74$vck44/vblo=6,719.99 2006.285.17:51:24.74#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.17:51:24.74#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.17:51:24.74#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:24.74#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.17:51:24.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.17:51:24.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.17:51:24.74#ibcon#enter wrdev, iclass 5, count 0 2006.285.17:51:24.74#ibcon#first serial, iclass 5, count 0 2006.285.17:51:24.74#ibcon#enter sib2, iclass 5, count 0 2006.285.17:51:24.74#ibcon#flushed, iclass 5, count 0 2006.285.17:51:24.74#ibcon#about to write, iclass 5, count 0 2006.285.17:51:24.74#ibcon#wrote, iclass 5, count 0 2006.285.17:51:24.74#ibcon#about to read 3, iclass 5, count 0 2006.285.17:51:24.76#ibcon#read 3, iclass 5, count 0 2006.285.17:51:24.76#ibcon#about to read 4, iclass 5, count 0 2006.285.17:51:24.76#ibcon#read 4, iclass 5, count 0 2006.285.17:51:24.76#ibcon#about to read 5, iclass 5, count 0 2006.285.17:51:24.76#ibcon#read 5, iclass 5, count 0 2006.285.17:51:24.76#ibcon#about to read 6, iclass 5, count 0 2006.285.17:51:24.76#ibcon#read 6, iclass 5, count 0 2006.285.17:51:24.76#ibcon#end of sib2, iclass 5, count 0 2006.285.17:51:24.76#ibcon#*mode == 0, iclass 5, count 0 2006.285.17:51:24.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.17:51:24.76#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.17:51:24.76#ibcon#*before write, iclass 5, count 0 2006.285.17:51:24.76#ibcon#enter sib2, iclass 5, count 0 2006.285.17:51:24.76#ibcon#flushed, iclass 5, count 0 2006.285.17:51:24.76#ibcon#about to write, iclass 5, count 0 2006.285.17:51:24.76#ibcon#wrote, iclass 5, count 0 2006.285.17:51:24.76#ibcon#about to read 3, iclass 5, count 0 2006.285.17:51:24.80#ibcon#read 3, iclass 5, count 0 2006.285.17:51:24.80#ibcon#about to read 4, iclass 5, count 0 2006.285.17:51:24.80#ibcon#read 4, iclass 5, count 0 2006.285.17:51:24.80#ibcon#about to read 5, iclass 5, count 0 2006.285.17:51:24.80#ibcon#read 5, iclass 5, count 0 2006.285.17:51:24.80#ibcon#about to read 6, iclass 5, count 0 2006.285.17:51:24.80#ibcon#read 6, iclass 5, count 0 2006.285.17:51:24.80#ibcon#end of sib2, iclass 5, count 0 2006.285.17:51:24.80#ibcon#*after write, iclass 5, count 0 2006.285.17:51:24.80#ibcon#*before return 0, iclass 5, count 0 2006.285.17:51:24.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.17:51:24.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.17:51:24.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.17:51:24.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.17:51:24.80$vck44/vb=6,3 2006.285.17:51:24.80#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.17:51:24.80#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.17:51:24.80#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:24.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.17:51:24.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.17:51:24.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.17:51:24.86#ibcon#enter wrdev, iclass 7, count 2 2006.285.17:51:24.86#ibcon#first serial, iclass 7, count 2 2006.285.17:51:24.86#ibcon#enter sib2, iclass 7, count 2 2006.285.17:51:24.86#ibcon#flushed, iclass 7, count 2 2006.285.17:51:24.86#ibcon#about to write, iclass 7, count 2 2006.285.17:51:24.86#ibcon#wrote, iclass 7, count 2 2006.285.17:51:24.86#ibcon#about to read 3, iclass 7, count 2 2006.285.17:51:24.88#ibcon#read 3, iclass 7, count 2 2006.285.17:51:24.88#ibcon#about to read 4, iclass 7, count 2 2006.285.17:51:24.88#ibcon#read 4, iclass 7, count 2 2006.285.17:51:24.88#ibcon#about to read 5, iclass 7, count 2 2006.285.17:51:24.88#ibcon#read 5, iclass 7, count 2 2006.285.17:51:24.88#ibcon#about to read 6, iclass 7, count 2 2006.285.17:51:24.88#ibcon#read 6, iclass 7, count 2 2006.285.17:51:24.88#ibcon#end of sib2, iclass 7, count 2 2006.285.17:51:24.88#ibcon#*mode == 0, iclass 7, count 2 2006.285.17:51:24.88#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.17:51:24.88#ibcon#[27=AT06-03\r\n] 2006.285.17:51:24.88#ibcon#*before write, iclass 7, count 2 2006.285.17:51:24.88#ibcon#enter sib2, iclass 7, count 2 2006.285.17:51:24.88#ibcon#flushed, iclass 7, count 2 2006.285.17:51:24.88#ibcon#about to write, iclass 7, count 2 2006.285.17:51:24.88#ibcon#wrote, iclass 7, count 2 2006.285.17:51:24.88#ibcon#about to read 3, iclass 7, count 2 2006.285.17:51:24.91#ibcon#read 3, iclass 7, count 2 2006.285.17:51:24.91#ibcon#about to read 4, iclass 7, count 2 2006.285.17:51:24.91#ibcon#read 4, iclass 7, count 2 2006.285.17:51:24.91#ibcon#about to read 5, iclass 7, count 2 2006.285.17:51:24.91#ibcon#read 5, iclass 7, count 2 2006.285.17:51:24.91#ibcon#about to read 6, iclass 7, count 2 2006.285.17:51:24.91#ibcon#read 6, iclass 7, count 2 2006.285.17:51:24.91#ibcon#end of sib2, iclass 7, count 2 2006.285.17:51:24.91#ibcon#*after write, iclass 7, count 2 2006.285.17:51:24.91#ibcon#*before return 0, iclass 7, count 2 2006.285.17:51:24.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.17:51:24.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.17:51:24.91#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.17:51:24.91#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:24.91#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.17:51:25.03#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.17:51:25.03#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.17:51:25.03#ibcon#enter wrdev, iclass 7, count 0 2006.285.17:51:25.03#ibcon#first serial, iclass 7, count 0 2006.285.17:51:25.03#ibcon#enter sib2, iclass 7, count 0 2006.285.17:51:25.03#ibcon#flushed, iclass 7, count 0 2006.285.17:51:25.03#ibcon#about to write, iclass 7, count 0 2006.285.17:51:25.03#ibcon#wrote, iclass 7, count 0 2006.285.17:51:25.03#ibcon#about to read 3, iclass 7, count 0 2006.285.17:51:25.05#ibcon#read 3, iclass 7, count 0 2006.285.17:51:25.05#ibcon#about to read 4, iclass 7, count 0 2006.285.17:51:25.05#ibcon#read 4, iclass 7, count 0 2006.285.17:51:25.05#ibcon#about to read 5, iclass 7, count 0 2006.285.17:51:25.05#ibcon#read 5, iclass 7, count 0 2006.285.17:51:25.05#ibcon#about to read 6, iclass 7, count 0 2006.285.17:51:25.05#ibcon#read 6, iclass 7, count 0 2006.285.17:51:25.05#ibcon#end of sib2, iclass 7, count 0 2006.285.17:51:25.05#ibcon#*mode == 0, iclass 7, count 0 2006.285.17:51:25.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.17:51:25.05#ibcon#[27=USB\r\n] 2006.285.17:51:25.05#ibcon#*before write, iclass 7, count 0 2006.285.17:51:25.05#ibcon#enter sib2, iclass 7, count 0 2006.285.17:51:25.05#ibcon#flushed, iclass 7, count 0 2006.285.17:51:25.05#ibcon#about to write, iclass 7, count 0 2006.285.17:51:25.05#ibcon#wrote, iclass 7, count 0 2006.285.17:51:25.05#ibcon#about to read 3, iclass 7, count 0 2006.285.17:51:25.08#ibcon#read 3, iclass 7, count 0 2006.285.17:51:25.08#ibcon#about to read 4, iclass 7, count 0 2006.285.17:51:25.08#ibcon#read 4, iclass 7, count 0 2006.285.17:51:25.08#ibcon#about to read 5, iclass 7, count 0 2006.285.17:51:25.08#ibcon#read 5, iclass 7, count 0 2006.285.17:51:25.08#ibcon#about to read 6, iclass 7, count 0 2006.285.17:51:25.08#ibcon#read 6, iclass 7, count 0 2006.285.17:51:25.08#ibcon#end of sib2, iclass 7, count 0 2006.285.17:51:25.08#ibcon#*after write, iclass 7, count 0 2006.285.17:51:25.08#ibcon#*before return 0, iclass 7, count 0 2006.285.17:51:25.08#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.17:51:25.08#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.17:51:25.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.17:51:25.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.17:51:25.08$vck44/vblo=7,734.99 2006.285.17:51:25.08#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.17:51:25.08#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.17:51:25.08#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:25.08#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:51:25.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:51:25.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:51:25.08#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:51:25.08#ibcon#first serial, iclass 11, count 0 2006.285.17:51:25.08#ibcon#enter sib2, iclass 11, count 0 2006.285.17:51:25.08#ibcon#flushed, iclass 11, count 0 2006.285.17:51:25.08#ibcon#about to write, iclass 11, count 0 2006.285.17:51:25.08#ibcon#wrote, iclass 11, count 0 2006.285.17:51:25.08#ibcon#about to read 3, iclass 11, count 0 2006.285.17:51:25.10#ibcon#read 3, iclass 11, count 0 2006.285.17:51:25.10#ibcon#about to read 4, iclass 11, count 0 2006.285.17:51:25.10#ibcon#read 4, iclass 11, count 0 2006.285.17:51:25.10#ibcon#about to read 5, iclass 11, count 0 2006.285.17:51:25.10#ibcon#read 5, iclass 11, count 0 2006.285.17:51:25.10#ibcon#about to read 6, iclass 11, count 0 2006.285.17:51:25.10#ibcon#read 6, iclass 11, count 0 2006.285.17:51:25.10#ibcon#end of sib2, iclass 11, count 0 2006.285.17:51:25.10#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:51:25.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:51:25.10#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.17:51:25.10#ibcon#*before write, iclass 11, count 0 2006.285.17:51:25.10#ibcon#enter sib2, iclass 11, count 0 2006.285.17:51:25.10#ibcon#flushed, iclass 11, count 0 2006.285.17:51:25.10#ibcon#about to write, iclass 11, count 0 2006.285.17:51:25.10#ibcon#wrote, iclass 11, count 0 2006.285.17:51:25.10#ibcon#about to read 3, iclass 11, count 0 2006.285.17:51:25.14#ibcon#read 3, iclass 11, count 0 2006.285.17:51:25.14#ibcon#about to read 4, iclass 11, count 0 2006.285.17:51:25.14#ibcon#read 4, iclass 11, count 0 2006.285.17:51:25.14#ibcon#about to read 5, iclass 11, count 0 2006.285.17:51:25.14#ibcon#read 5, iclass 11, count 0 2006.285.17:51:25.14#ibcon#about to read 6, iclass 11, count 0 2006.285.17:51:25.14#ibcon#read 6, iclass 11, count 0 2006.285.17:51:25.14#ibcon#end of sib2, iclass 11, count 0 2006.285.17:51:25.14#ibcon#*after write, iclass 11, count 0 2006.285.17:51:25.14#ibcon#*before return 0, iclass 11, count 0 2006.285.17:51:25.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:51:25.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:51:25.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:51:25.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:51:25.14$vck44/vb=7,4 2006.285.17:51:25.14#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.17:51:25.14#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.17:51:25.14#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:25.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:51:25.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:51:25.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:51:25.20#ibcon#enter wrdev, iclass 13, count 2 2006.285.17:51:25.20#ibcon#first serial, iclass 13, count 2 2006.285.17:51:25.20#ibcon#enter sib2, iclass 13, count 2 2006.285.17:51:25.20#ibcon#flushed, iclass 13, count 2 2006.285.17:51:25.20#ibcon#about to write, iclass 13, count 2 2006.285.17:51:25.20#ibcon#wrote, iclass 13, count 2 2006.285.17:51:25.20#ibcon#about to read 3, iclass 13, count 2 2006.285.17:51:25.22#ibcon#read 3, iclass 13, count 2 2006.285.17:51:25.22#ibcon#about to read 4, iclass 13, count 2 2006.285.17:51:25.22#ibcon#read 4, iclass 13, count 2 2006.285.17:51:25.22#ibcon#about to read 5, iclass 13, count 2 2006.285.17:51:25.22#ibcon#read 5, iclass 13, count 2 2006.285.17:51:25.22#ibcon#about to read 6, iclass 13, count 2 2006.285.17:51:25.22#ibcon#read 6, iclass 13, count 2 2006.285.17:51:25.22#ibcon#end of sib2, iclass 13, count 2 2006.285.17:51:25.22#ibcon#*mode == 0, iclass 13, count 2 2006.285.17:51:25.22#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.17:51:25.22#ibcon#[27=AT07-04\r\n] 2006.285.17:51:25.22#ibcon#*before write, iclass 13, count 2 2006.285.17:51:25.22#ibcon#enter sib2, iclass 13, count 2 2006.285.17:51:25.22#ibcon#flushed, iclass 13, count 2 2006.285.17:51:25.22#ibcon#about to write, iclass 13, count 2 2006.285.17:51:25.22#ibcon#wrote, iclass 13, count 2 2006.285.17:51:25.22#ibcon#about to read 3, iclass 13, count 2 2006.285.17:51:25.25#ibcon#read 3, iclass 13, count 2 2006.285.17:51:25.25#ibcon#about to read 4, iclass 13, count 2 2006.285.17:51:25.25#ibcon#read 4, iclass 13, count 2 2006.285.17:51:25.25#ibcon#about to read 5, iclass 13, count 2 2006.285.17:51:25.25#ibcon#read 5, iclass 13, count 2 2006.285.17:51:25.25#ibcon#about to read 6, iclass 13, count 2 2006.285.17:51:25.25#ibcon#read 6, iclass 13, count 2 2006.285.17:51:25.25#ibcon#end of sib2, iclass 13, count 2 2006.285.17:51:25.25#ibcon#*after write, iclass 13, count 2 2006.285.17:51:25.25#ibcon#*before return 0, iclass 13, count 2 2006.285.17:51:25.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:51:25.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.17:51:25.25#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.17:51:25.25#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:25.25#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:51:25.37#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:51:25.37#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:51:25.37#ibcon#enter wrdev, iclass 13, count 0 2006.285.17:51:25.37#ibcon#first serial, iclass 13, count 0 2006.285.17:51:25.37#ibcon#enter sib2, iclass 13, count 0 2006.285.17:51:25.37#ibcon#flushed, iclass 13, count 0 2006.285.17:51:25.37#ibcon#about to write, iclass 13, count 0 2006.285.17:51:25.37#ibcon#wrote, iclass 13, count 0 2006.285.17:51:25.37#ibcon#about to read 3, iclass 13, count 0 2006.285.17:51:25.39#ibcon#read 3, iclass 13, count 0 2006.285.17:51:25.39#ibcon#about to read 4, iclass 13, count 0 2006.285.17:51:25.39#ibcon#read 4, iclass 13, count 0 2006.285.17:51:25.39#ibcon#about to read 5, iclass 13, count 0 2006.285.17:51:25.39#ibcon#read 5, iclass 13, count 0 2006.285.17:51:25.39#ibcon#about to read 6, iclass 13, count 0 2006.285.17:51:25.39#ibcon#read 6, iclass 13, count 0 2006.285.17:51:25.39#ibcon#end of sib2, iclass 13, count 0 2006.285.17:51:25.39#ibcon#*mode == 0, iclass 13, count 0 2006.285.17:51:25.39#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.17:51:25.39#ibcon#[27=USB\r\n] 2006.285.17:51:25.39#ibcon#*before write, iclass 13, count 0 2006.285.17:51:25.39#ibcon#enter sib2, iclass 13, count 0 2006.285.17:51:25.39#ibcon#flushed, iclass 13, count 0 2006.285.17:51:25.39#ibcon#about to write, iclass 13, count 0 2006.285.17:51:25.39#ibcon#wrote, iclass 13, count 0 2006.285.17:51:25.39#ibcon#about to read 3, iclass 13, count 0 2006.285.17:51:25.42#ibcon#read 3, iclass 13, count 0 2006.285.17:51:25.42#ibcon#about to read 4, iclass 13, count 0 2006.285.17:51:25.42#ibcon#read 4, iclass 13, count 0 2006.285.17:51:25.42#ibcon#about to read 5, iclass 13, count 0 2006.285.17:51:25.42#ibcon#read 5, iclass 13, count 0 2006.285.17:51:25.42#ibcon#about to read 6, iclass 13, count 0 2006.285.17:51:25.42#ibcon#read 6, iclass 13, count 0 2006.285.17:51:25.42#ibcon#end of sib2, iclass 13, count 0 2006.285.17:51:25.42#ibcon#*after write, iclass 13, count 0 2006.285.17:51:25.42#ibcon#*before return 0, iclass 13, count 0 2006.285.17:51:25.42#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:51:25.42#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.17:51:25.42#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.17:51:25.42#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.17:51:25.42$vck44/vblo=8,744.99 2006.285.17:51:25.42#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.17:51:25.42#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.17:51:25.42#ibcon#ireg 17 cls_cnt 0 2006.285.17:51:25.42#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:51:25.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:51:25.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:51:25.42#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:51:25.42#ibcon#first serial, iclass 15, count 0 2006.285.17:51:25.42#ibcon#enter sib2, iclass 15, count 0 2006.285.17:51:25.42#ibcon#flushed, iclass 15, count 0 2006.285.17:51:25.42#ibcon#about to write, iclass 15, count 0 2006.285.17:51:25.42#ibcon#wrote, iclass 15, count 0 2006.285.17:51:25.42#ibcon#about to read 3, iclass 15, count 0 2006.285.17:51:25.44#ibcon#read 3, iclass 15, count 0 2006.285.17:51:25.44#ibcon#about to read 4, iclass 15, count 0 2006.285.17:51:25.44#ibcon#read 4, iclass 15, count 0 2006.285.17:51:25.44#ibcon#about to read 5, iclass 15, count 0 2006.285.17:51:25.44#ibcon#read 5, iclass 15, count 0 2006.285.17:51:25.44#ibcon#about to read 6, iclass 15, count 0 2006.285.17:51:25.44#ibcon#read 6, iclass 15, count 0 2006.285.17:51:25.44#ibcon#end of sib2, iclass 15, count 0 2006.285.17:51:25.44#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:51:25.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:51:25.44#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.17:51:25.44#ibcon#*before write, iclass 15, count 0 2006.285.17:51:25.44#ibcon#enter sib2, iclass 15, count 0 2006.285.17:51:25.44#ibcon#flushed, iclass 15, count 0 2006.285.17:51:25.44#ibcon#about to write, iclass 15, count 0 2006.285.17:51:25.44#ibcon#wrote, iclass 15, count 0 2006.285.17:51:25.44#ibcon#about to read 3, iclass 15, count 0 2006.285.17:51:25.48#ibcon#read 3, iclass 15, count 0 2006.285.17:51:25.48#ibcon#about to read 4, iclass 15, count 0 2006.285.17:51:25.48#ibcon#read 4, iclass 15, count 0 2006.285.17:51:25.48#ibcon#about to read 5, iclass 15, count 0 2006.285.17:51:25.48#ibcon#read 5, iclass 15, count 0 2006.285.17:51:25.48#ibcon#about to read 6, iclass 15, count 0 2006.285.17:51:25.48#ibcon#read 6, iclass 15, count 0 2006.285.17:51:25.48#ibcon#end of sib2, iclass 15, count 0 2006.285.17:51:25.48#ibcon#*after write, iclass 15, count 0 2006.285.17:51:25.48#ibcon#*before return 0, iclass 15, count 0 2006.285.17:51:25.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:51:25.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.17:51:25.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:51:25.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:51:25.48$vck44/vb=8,4 2006.285.17:51:25.48#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.17:51:25.48#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.17:51:25.48#ibcon#ireg 11 cls_cnt 2 2006.285.17:51:25.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:51:25.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:51:25.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:51:25.54#ibcon#enter wrdev, iclass 17, count 2 2006.285.17:51:25.54#ibcon#first serial, iclass 17, count 2 2006.285.17:51:25.54#ibcon#enter sib2, iclass 17, count 2 2006.285.17:51:25.54#ibcon#flushed, iclass 17, count 2 2006.285.17:51:25.54#ibcon#about to write, iclass 17, count 2 2006.285.17:51:25.54#ibcon#wrote, iclass 17, count 2 2006.285.17:51:25.54#ibcon#about to read 3, iclass 17, count 2 2006.285.17:51:25.56#ibcon#read 3, iclass 17, count 2 2006.285.17:51:25.56#ibcon#about to read 4, iclass 17, count 2 2006.285.17:51:25.56#ibcon#read 4, iclass 17, count 2 2006.285.17:51:25.56#ibcon#about to read 5, iclass 17, count 2 2006.285.17:51:25.56#ibcon#read 5, iclass 17, count 2 2006.285.17:51:25.56#ibcon#about to read 6, iclass 17, count 2 2006.285.17:51:25.56#ibcon#read 6, iclass 17, count 2 2006.285.17:51:25.56#ibcon#end of sib2, iclass 17, count 2 2006.285.17:51:25.56#ibcon#*mode == 0, iclass 17, count 2 2006.285.17:51:25.56#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.17:51:25.56#ibcon#[27=AT08-04\r\n] 2006.285.17:51:25.56#ibcon#*before write, iclass 17, count 2 2006.285.17:51:25.56#ibcon#enter sib2, iclass 17, count 2 2006.285.17:51:25.56#ibcon#flushed, iclass 17, count 2 2006.285.17:51:25.56#ibcon#about to write, iclass 17, count 2 2006.285.17:51:25.56#ibcon#wrote, iclass 17, count 2 2006.285.17:51:25.56#ibcon#about to read 3, iclass 17, count 2 2006.285.17:51:25.59#ibcon#read 3, iclass 17, count 2 2006.285.17:51:25.59#ibcon#about to read 4, iclass 17, count 2 2006.285.17:51:25.59#ibcon#read 4, iclass 17, count 2 2006.285.17:51:25.59#ibcon#about to read 5, iclass 17, count 2 2006.285.17:51:25.59#ibcon#read 5, iclass 17, count 2 2006.285.17:51:25.59#ibcon#about to read 6, iclass 17, count 2 2006.285.17:51:25.59#ibcon#read 6, iclass 17, count 2 2006.285.17:51:25.59#ibcon#end of sib2, iclass 17, count 2 2006.285.17:51:25.59#ibcon#*after write, iclass 17, count 2 2006.285.17:51:25.59#ibcon#*before return 0, iclass 17, count 2 2006.285.17:51:25.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:51:25.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.17:51:25.59#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.17:51:25.59#ibcon#ireg 7 cls_cnt 0 2006.285.17:51:25.59#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:51:25.71#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:51:25.71#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:51:25.71#ibcon#enter wrdev, iclass 17, count 0 2006.285.17:51:25.71#ibcon#first serial, iclass 17, count 0 2006.285.17:51:25.71#ibcon#enter sib2, iclass 17, count 0 2006.285.17:51:25.71#ibcon#flushed, iclass 17, count 0 2006.285.17:51:25.71#ibcon#about to write, iclass 17, count 0 2006.285.17:51:25.71#ibcon#wrote, iclass 17, count 0 2006.285.17:51:25.71#ibcon#about to read 3, iclass 17, count 0 2006.285.17:51:25.73#ibcon#read 3, iclass 17, count 0 2006.285.17:51:25.73#ibcon#about to read 4, iclass 17, count 0 2006.285.17:51:25.73#ibcon#read 4, iclass 17, count 0 2006.285.17:51:25.73#ibcon#about to read 5, iclass 17, count 0 2006.285.17:51:25.73#ibcon#read 5, iclass 17, count 0 2006.285.17:51:25.73#ibcon#about to read 6, iclass 17, count 0 2006.285.17:51:25.73#ibcon#read 6, iclass 17, count 0 2006.285.17:51:25.73#ibcon#end of sib2, iclass 17, count 0 2006.285.17:51:25.73#ibcon#*mode == 0, iclass 17, count 0 2006.285.17:51:25.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.17:51:25.73#ibcon#[27=USB\r\n] 2006.285.17:51:25.73#ibcon#*before write, iclass 17, count 0 2006.285.17:51:25.73#ibcon#enter sib2, iclass 17, count 0 2006.285.17:51:25.73#ibcon#flushed, iclass 17, count 0 2006.285.17:51:25.73#ibcon#about to write, iclass 17, count 0 2006.285.17:51:25.73#ibcon#wrote, iclass 17, count 0 2006.285.17:51:25.73#ibcon#about to read 3, iclass 17, count 0 2006.285.17:51:25.76#ibcon#read 3, iclass 17, count 0 2006.285.17:51:25.76#ibcon#about to read 4, iclass 17, count 0 2006.285.17:51:25.76#ibcon#read 4, iclass 17, count 0 2006.285.17:51:25.76#ibcon#about to read 5, iclass 17, count 0 2006.285.17:51:25.76#ibcon#read 5, iclass 17, count 0 2006.285.17:51:25.76#ibcon#about to read 6, iclass 17, count 0 2006.285.17:51:25.76#ibcon#read 6, iclass 17, count 0 2006.285.17:51:25.76#ibcon#end of sib2, iclass 17, count 0 2006.285.17:51:25.76#ibcon#*after write, iclass 17, count 0 2006.285.17:51:25.76#ibcon#*before return 0, iclass 17, count 0 2006.285.17:51:25.76#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:51:25.76#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.17:51:25.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.17:51:25.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.17:51:25.76$vck44/vabw=wide 2006.285.17:51:25.76#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.17:51:25.76#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.17:51:25.76#ibcon#ireg 8 cls_cnt 0 2006.285.17:51:25.76#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:51:25.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:51:25.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:51:25.76#ibcon#enter wrdev, iclass 19, count 0 2006.285.17:51:25.76#ibcon#first serial, iclass 19, count 0 2006.285.17:51:25.76#ibcon#enter sib2, iclass 19, count 0 2006.285.17:51:25.76#ibcon#flushed, iclass 19, count 0 2006.285.17:51:25.76#ibcon#about to write, iclass 19, count 0 2006.285.17:51:25.76#ibcon#wrote, iclass 19, count 0 2006.285.17:51:25.76#ibcon#about to read 3, iclass 19, count 0 2006.285.17:51:25.78#ibcon#read 3, iclass 19, count 0 2006.285.17:51:25.78#ibcon#about to read 4, iclass 19, count 0 2006.285.17:51:25.78#ibcon#read 4, iclass 19, count 0 2006.285.17:51:25.78#ibcon#about to read 5, iclass 19, count 0 2006.285.17:51:25.78#ibcon#read 5, iclass 19, count 0 2006.285.17:51:25.78#ibcon#about to read 6, iclass 19, count 0 2006.285.17:51:25.78#ibcon#read 6, iclass 19, count 0 2006.285.17:51:25.78#ibcon#end of sib2, iclass 19, count 0 2006.285.17:51:25.78#ibcon#*mode == 0, iclass 19, count 0 2006.285.17:51:25.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.17:51:25.78#ibcon#[25=BW32\r\n] 2006.285.17:51:25.78#ibcon#*before write, iclass 19, count 0 2006.285.17:51:25.78#ibcon#enter sib2, iclass 19, count 0 2006.285.17:51:25.78#ibcon#flushed, iclass 19, count 0 2006.285.17:51:25.78#ibcon#about to write, iclass 19, count 0 2006.285.17:51:25.78#ibcon#wrote, iclass 19, count 0 2006.285.17:51:25.78#ibcon#about to read 3, iclass 19, count 0 2006.285.17:51:25.81#ibcon#read 3, iclass 19, count 0 2006.285.17:51:25.81#ibcon#about to read 4, iclass 19, count 0 2006.285.17:51:25.81#ibcon#read 4, iclass 19, count 0 2006.285.17:51:25.81#ibcon#about to read 5, iclass 19, count 0 2006.285.17:51:25.81#ibcon#read 5, iclass 19, count 0 2006.285.17:51:25.81#ibcon#about to read 6, iclass 19, count 0 2006.285.17:51:25.81#ibcon#read 6, iclass 19, count 0 2006.285.17:51:25.81#ibcon#end of sib2, iclass 19, count 0 2006.285.17:51:25.81#ibcon#*after write, iclass 19, count 0 2006.285.17:51:25.81#ibcon#*before return 0, iclass 19, count 0 2006.285.17:51:25.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:51:25.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.17:51:25.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.17:51:25.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.17:51:25.81$vck44/vbbw=wide 2006.285.17:51:25.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.17:51:25.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.17:51:25.81#ibcon#ireg 8 cls_cnt 0 2006.285.17:51:25.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:51:25.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:51:25.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:51:25.88#ibcon#enter wrdev, iclass 21, count 0 2006.285.17:51:25.88#ibcon#first serial, iclass 21, count 0 2006.285.17:51:25.88#ibcon#enter sib2, iclass 21, count 0 2006.285.17:51:25.88#ibcon#flushed, iclass 21, count 0 2006.285.17:51:25.88#ibcon#about to write, iclass 21, count 0 2006.285.17:51:25.88#ibcon#wrote, iclass 21, count 0 2006.285.17:51:25.88#ibcon#about to read 3, iclass 21, count 0 2006.285.17:51:25.90#ibcon#read 3, iclass 21, count 0 2006.285.17:51:25.90#ibcon#about to read 4, iclass 21, count 0 2006.285.17:51:25.90#ibcon#read 4, iclass 21, count 0 2006.285.17:51:25.90#ibcon#about to read 5, iclass 21, count 0 2006.285.17:51:25.90#ibcon#read 5, iclass 21, count 0 2006.285.17:51:25.90#ibcon#about to read 6, iclass 21, count 0 2006.285.17:51:25.90#ibcon#read 6, iclass 21, count 0 2006.285.17:51:25.90#ibcon#end of sib2, iclass 21, count 0 2006.285.17:51:25.90#ibcon#*mode == 0, iclass 21, count 0 2006.285.17:51:25.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.17:51:25.90#ibcon#[27=BW32\r\n] 2006.285.17:51:25.90#ibcon#*before write, iclass 21, count 0 2006.285.17:51:25.90#ibcon#enter sib2, iclass 21, count 0 2006.285.17:51:25.90#ibcon#flushed, iclass 21, count 0 2006.285.17:51:25.90#ibcon#about to write, iclass 21, count 0 2006.285.17:51:25.90#ibcon#wrote, iclass 21, count 0 2006.285.17:51:25.90#ibcon#about to read 3, iclass 21, count 0 2006.285.17:51:25.93#ibcon#read 3, iclass 21, count 0 2006.285.17:51:25.93#ibcon#about to read 4, iclass 21, count 0 2006.285.17:51:25.93#ibcon#read 4, iclass 21, count 0 2006.285.17:51:25.93#ibcon#about to read 5, iclass 21, count 0 2006.285.17:51:25.93#ibcon#read 5, iclass 21, count 0 2006.285.17:51:25.93#ibcon#about to read 6, iclass 21, count 0 2006.285.17:51:25.93#ibcon#read 6, iclass 21, count 0 2006.285.17:51:25.93#ibcon#end of sib2, iclass 21, count 0 2006.285.17:51:25.93#ibcon#*after write, iclass 21, count 0 2006.285.17:51:25.93#ibcon#*before return 0, iclass 21, count 0 2006.285.17:51:25.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:51:25.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:51:25.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.17:51:25.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.17:51:25.93$setupk4/ifdk4 2006.285.17:51:25.93$ifdk4/lo= 2006.285.17:51:25.93$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.17:51:25.93$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.17:51:25.93$ifdk4/patch= 2006.285.17:51:25.93$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.17:51:25.94$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.17:51:25.94$setupk4/!*+20s 2006.285.17:51:31.90#abcon#<5=/00 0.2 1.0 16.281001014.5\r\n> 2006.285.17:51:31.92#abcon#{5=INTERFACE CLEAR} 2006.285.17:51:31.98#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:51:39.56$setupk4/"tpicd 2006.285.17:51:39.56$setupk4/echo=off 2006.285.17:51:39.56$setupk4/xlog=off 2006.285.17:51:39.56:!2006.285.17:53:46 2006.285.17:52:09.13#trakl#Source acquired 2006.285.17:52:11.13#flagr#flagr/antenna,acquired 2006.285.17:53:46.00:preob 2006.285.17:53:46.13/onsource/TRACKING 2006.285.17:53:46.13:!2006.285.17:53:56 2006.285.17:53:56.00:"tape 2006.285.17:53:56.00:"st=record 2006.285.17:53:56.00:data_valid=on 2006.285.17:53:56.00:midob 2006.285.17:53:56.13/onsource/TRACKING 2006.285.17:53:56.13/wx/16.28,1014.5,100 2006.285.17:53:56.22/cable/+6.5031E-03 2006.285.17:53:57.31/va/01,07,usb,yes,31,34 2006.285.17:53:57.31/va/02,06,usb,yes,31,32 2006.285.17:53:57.31/va/03,07,usb,yes,31,33 2006.285.17:53:57.31/va/04,06,usb,yes,32,34 2006.285.17:53:57.31/va/05,03,usb,yes,32,32 2006.285.17:53:57.31/va/06,04,usb,yes,29,28 2006.285.17:53:57.31/va/07,04,usb,yes,29,30 2006.285.17:53:57.31/va/08,03,usb,yes,30,36 2006.285.17:53:57.54/valo/01,524.99,yes,locked 2006.285.17:53:57.54/valo/02,534.99,yes,locked 2006.285.17:53:57.54/valo/03,564.99,yes,locked 2006.285.17:53:57.54/valo/04,624.99,yes,locked 2006.285.17:53:57.54/valo/05,734.99,yes,locked 2006.285.17:53:57.54/valo/06,814.99,yes,locked 2006.285.17:53:57.54/valo/07,864.99,yes,locked 2006.285.17:53:57.54/valo/08,884.99,yes,locked 2006.285.17:53:58.63/vb/01,04,usb,yes,30,28 2006.285.17:53:58.63/vb/02,05,usb,yes,28,28 2006.285.17:53:58.63/vb/03,04,usb,yes,29,32 2006.285.17:53:58.63/vb/04,05,usb,yes,29,28 2006.285.17:53:58.63/vb/05,04,usb,yes,26,28 2006.285.17:53:58.63/vb/06,03,usb,yes,37,33 2006.285.17:53:58.63/vb/07,04,usb,yes,30,30 2006.285.17:53:58.63/vb/08,04,usb,yes,27,31 2006.285.17:53:58.86/vblo/01,629.99,yes,locked 2006.285.17:53:58.86/vblo/02,634.99,yes,locked 2006.285.17:53:58.86/vblo/03,649.99,yes,locked 2006.285.17:53:58.86/vblo/04,679.99,yes,locked 2006.285.17:53:58.86/vblo/05,709.99,yes,locked 2006.285.17:53:58.86/vblo/06,719.99,yes,locked 2006.285.17:53:58.86/vblo/07,734.99,yes,locked 2006.285.17:53:58.86/vblo/08,744.99,yes,locked 2006.285.17:53:59.01/vabw/8 2006.285.17:53:59.16/vbbw/8 2006.285.17:53:59.25/xfe/off,on,12.2 2006.285.17:53:59.64/ifatt/23,28,28,28 2006.285.17:54:00.07/fmout-gps/S +2.66E-07 2006.285.17:54:00.09:!2006.285.17:55:36 2006.285.17:55:36.01:data_valid=off 2006.285.17:55:36.01:"et 2006.285.17:55:36.01:!+3s 2006.285.17:55:39.02:"tape 2006.285.17:55:39.02:postob 2006.285.17:55:39.26/cable/+6.5044E-03 2006.285.17:55:39.26/wx/16.25,1014.4,100 2006.285.17:55:40.07/fmout-gps/S +2.65E-07 2006.285.17:55:40.07:scan_name=285-1757,jd0610,60 2006.285.17:55:40.07:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.285.17:55:41.14#flagr#flagr/antenna,new-source 2006.285.17:55:41.14:checkk5 2006.285.17:55:41.89/chk_autoobs//k5ts1/ autoobs is running! 2006.285.17:55:42.46/chk_autoobs//k5ts2/ autoobs is running! 2006.285.17:55:42.87/chk_autoobs//k5ts3/ autoobs is running! 2006.285.17:55:43.33/chk_autoobs//k5ts4/ autoobs is running! 2006.285.17:55:43.75/chk_obsdata//k5ts1/T2851753??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.17:55:44.19/chk_obsdata//k5ts2/T2851753??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.17:55:44.62/chk_obsdata//k5ts3/T2851753??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.17:55:45.00/chk_obsdata//k5ts4/T2851753??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.17:55:45.94/k5log//k5ts1_log_newline 2006.285.17:55:46.77/k5log//k5ts2_log_newline 2006.285.17:55:47.57/k5log//k5ts3_log_newline 2006.285.17:55:48.42/k5log//k5ts4_log_newline 2006.285.17:55:48.44/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.17:55:48.44:setupk4=1 2006.285.17:55:48.44$setupk4/echo=on 2006.285.17:55:48.44$setupk4/pcalon 2006.285.17:55:48.44$pcalon/"no phase cal control is implemented here 2006.285.17:55:48.44$setupk4/"tpicd=stop 2006.285.17:55:48.44$setupk4/"rec=synch_on 2006.285.17:55:48.44$setupk4/"rec_mode=128 2006.285.17:55:48.44$setupk4/!* 2006.285.17:55:48.44$setupk4/recpk4 2006.285.17:55:48.44$recpk4/recpatch= 2006.285.17:55:48.44$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.17:55:48.44$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.17:55:48.44$setupk4/vck44 2006.285.17:55:48.44$vck44/valo=1,524.99 2006.285.17:55:48.44#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.17:55:48.44#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.17:55:48.44#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:48.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:55:48.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:55:48.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:55:48.44#ibcon#enter wrdev, iclass 22, count 0 2006.285.17:55:48.44#ibcon#first serial, iclass 22, count 0 2006.285.17:55:48.44#ibcon#enter sib2, iclass 22, count 0 2006.285.17:55:48.44#ibcon#flushed, iclass 22, count 0 2006.285.17:55:48.44#ibcon#about to write, iclass 22, count 0 2006.285.17:55:48.44#ibcon#wrote, iclass 22, count 0 2006.285.17:55:48.44#ibcon#about to read 3, iclass 22, count 0 2006.285.17:55:48.46#ibcon#read 3, iclass 22, count 0 2006.285.17:55:48.46#ibcon#about to read 4, iclass 22, count 0 2006.285.17:55:48.46#ibcon#read 4, iclass 22, count 0 2006.285.17:55:48.46#ibcon#about to read 5, iclass 22, count 0 2006.285.17:55:48.46#ibcon#read 5, iclass 22, count 0 2006.285.17:55:48.46#ibcon#about to read 6, iclass 22, count 0 2006.285.17:55:48.46#ibcon#read 6, iclass 22, count 0 2006.285.17:55:48.46#ibcon#end of sib2, iclass 22, count 0 2006.285.17:55:48.46#ibcon#*mode == 0, iclass 22, count 0 2006.285.17:55:48.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.17:55:48.46#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.17:55:48.46#ibcon#*before write, iclass 22, count 0 2006.285.17:55:48.46#ibcon#enter sib2, iclass 22, count 0 2006.285.17:55:48.46#ibcon#flushed, iclass 22, count 0 2006.285.17:55:48.46#ibcon#about to write, iclass 22, count 0 2006.285.17:55:48.46#ibcon#wrote, iclass 22, count 0 2006.285.17:55:48.46#ibcon#about to read 3, iclass 22, count 0 2006.285.17:55:48.51#ibcon#read 3, iclass 22, count 0 2006.285.17:55:48.51#ibcon#about to read 4, iclass 22, count 0 2006.285.17:55:48.51#ibcon#read 4, iclass 22, count 0 2006.285.17:55:48.51#ibcon#about to read 5, iclass 22, count 0 2006.285.17:55:48.51#ibcon#read 5, iclass 22, count 0 2006.285.17:55:48.51#ibcon#about to read 6, iclass 22, count 0 2006.285.17:55:48.51#ibcon#read 6, iclass 22, count 0 2006.285.17:55:48.51#ibcon#end of sib2, iclass 22, count 0 2006.285.17:55:48.51#ibcon#*after write, iclass 22, count 0 2006.285.17:55:48.51#ibcon#*before return 0, iclass 22, count 0 2006.285.17:55:48.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:55:48.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:55:48.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.17:55:48.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.17:55:48.51$vck44/va=1,7 2006.285.17:55:48.51#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.17:55:48.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.17:55:48.51#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:48.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:55:48.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:55:48.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:55:48.51#ibcon#enter wrdev, iclass 24, count 2 2006.285.17:55:48.51#ibcon#first serial, iclass 24, count 2 2006.285.17:55:48.51#ibcon#enter sib2, iclass 24, count 2 2006.285.17:55:48.51#ibcon#flushed, iclass 24, count 2 2006.285.17:55:48.51#ibcon#about to write, iclass 24, count 2 2006.285.17:55:48.51#ibcon#wrote, iclass 24, count 2 2006.285.17:55:48.51#ibcon#about to read 3, iclass 24, count 2 2006.285.17:55:48.53#ibcon#read 3, iclass 24, count 2 2006.285.17:55:48.53#ibcon#about to read 4, iclass 24, count 2 2006.285.17:55:48.53#ibcon#read 4, iclass 24, count 2 2006.285.17:55:48.53#ibcon#about to read 5, iclass 24, count 2 2006.285.17:55:48.53#ibcon#read 5, iclass 24, count 2 2006.285.17:55:48.53#ibcon#about to read 6, iclass 24, count 2 2006.285.17:55:48.53#ibcon#read 6, iclass 24, count 2 2006.285.17:55:48.53#ibcon#end of sib2, iclass 24, count 2 2006.285.17:55:48.53#ibcon#*mode == 0, iclass 24, count 2 2006.285.17:55:48.53#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.17:55:48.53#ibcon#[25=AT01-07\r\n] 2006.285.17:55:48.53#ibcon#*before write, iclass 24, count 2 2006.285.17:55:48.53#ibcon#enter sib2, iclass 24, count 2 2006.285.17:55:48.53#ibcon#flushed, iclass 24, count 2 2006.285.17:55:48.53#ibcon#about to write, iclass 24, count 2 2006.285.17:55:48.53#ibcon#wrote, iclass 24, count 2 2006.285.17:55:48.53#ibcon#about to read 3, iclass 24, count 2 2006.285.17:55:48.56#ibcon#read 3, iclass 24, count 2 2006.285.17:55:48.56#ibcon#about to read 4, iclass 24, count 2 2006.285.17:55:48.56#ibcon#read 4, iclass 24, count 2 2006.285.17:55:48.56#ibcon#about to read 5, iclass 24, count 2 2006.285.17:55:48.56#ibcon#read 5, iclass 24, count 2 2006.285.17:55:48.56#ibcon#about to read 6, iclass 24, count 2 2006.285.17:55:48.56#ibcon#read 6, iclass 24, count 2 2006.285.17:55:48.56#ibcon#end of sib2, iclass 24, count 2 2006.285.17:55:48.56#ibcon#*after write, iclass 24, count 2 2006.285.17:55:48.56#ibcon#*before return 0, iclass 24, count 2 2006.285.17:55:48.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:55:48.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:55:48.56#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.17:55:48.56#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:48.56#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:55:48.68#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:55:48.68#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:55:48.68#ibcon#enter wrdev, iclass 24, count 0 2006.285.17:55:48.68#ibcon#first serial, iclass 24, count 0 2006.285.17:55:48.68#ibcon#enter sib2, iclass 24, count 0 2006.285.17:55:48.68#ibcon#flushed, iclass 24, count 0 2006.285.17:55:48.68#ibcon#about to write, iclass 24, count 0 2006.285.17:55:48.68#ibcon#wrote, iclass 24, count 0 2006.285.17:55:48.68#ibcon#about to read 3, iclass 24, count 0 2006.285.17:55:48.70#ibcon#read 3, iclass 24, count 0 2006.285.17:55:48.70#ibcon#about to read 4, iclass 24, count 0 2006.285.17:55:48.70#ibcon#read 4, iclass 24, count 0 2006.285.17:55:48.70#ibcon#about to read 5, iclass 24, count 0 2006.285.17:55:48.70#ibcon#read 5, iclass 24, count 0 2006.285.17:55:48.70#ibcon#about to read 6, iclass 24, count 0 2006.285.17:55:48.70#ibcon#read 6, iclass 24, count 0 2006.285.17:55:48.70#ibcon#end of sib2, iclass 24, count 0 2006.285.17:55:48.70#ibcon#*mode == 0, iclass 24, count 0 2006.285.17:55:48.70#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.17:55:48.70#ibcon#[25=USB\r\n] 2006.285.17:55:48.70#ibcon#*before write, iclass 24, count 0 2006.285.17:55:48.70#ibcon#enter sib2, iclass 24, count 0 2006.285.17:55:48.70#ibcon#flushed, iclass 24, count 0 2006.285.17:55:48.70#ibcon#about to write, iclass 24, count 0 2006.285.17:55:48.70#ibcon#wrote, iclass 24, count 0 2006.285.17:55:48.70#ibcon#about to read 3, iclass 24, count 0 2006.285.17:55:48.73#ibcon#read 3, iclass 24, count 0 2006.285.17:55:48.73#ibcon#about to read 4, iclass 24, count 0 2006.285.17:55:48.73#ibcon#read 4, iclass 24, count 0 2006.285.17:55:48.73#ibcon#about to read 5, iclass 24, count 0 2006.285.17:55:48.73#ibcon#read 5, iclass 24, count 0 2006.285.17:55:48.73#ibcon#about to read 6, iclass 24, count 0 2006.285.17:55:48.73#ibcon#read 6, iclass 24, count 0 2006.285.17:55:48.73#ibcon#end of sib2, iclass 24, count 0 2006.285.17:55:48.73#ibcon#*after write, iclass 24, count 0 2006.285.17:55:48.73#ibcon#*before return 0, iclass 24, count 0 2006.285.17:55:48.73#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:55:48.73#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:55:48.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.17:55:48.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.17:55:48.73$vck44/valo=2,534.99 2006.285.17:55:48.73#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.17:55:48.73#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.17:55:48.73#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:48.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:55:48.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:55:48.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:55:48.73#ibcon#enter wrdev, iclass 26, count 0 2006.285.17:55:48.73#ibcon#first serial, iclass 26, count 0 2006.285.17:55:48.73#ibcon#enter sib2, iclass 26, count 0 2006.285.17:55:48.73#ibcon#flushed, iclass 26, count 0 2006.285.17:55:48.73#ibcon#about to write, iclass 26, count 0 2006.285.17:55:48.73#ibcon#wrote, iclass 26, count 0 2006.285.17:55:48.73#ibcon#about to read 3, iclass 26, count 0 2006.285.17:55:48.75#ibcon#read 3, iclass 26, count 0 2006.285.17:55:48.75#ibcon#about to read 4, iclass 26, count 0 2006.285.17:55:48.75#ibcon#read 4, iclass 26, count 0 2006.285.17:55:48.75#ibcon#about to read 5, iclass 26, count 0 2006.285.17:55:48.75#ibcon#read 5, iclass 26, count 0 2006.285.17:55:48.75#ibcon#about to read 6, iclass 26, count 0 2006.285.17:55:48.75#ibcon#read 6, iclass 26, count 0 2006.285.17:55:48.75#ibcon#end of sib2, iclass 26, count 0 2006.285.17:55:48.75#ibcon#*mode == 0, iclass 26, count 0 2006.285.17:55:48.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.17:55:48.75#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.17:55:48.75#ibcon#*before write, iclass 26, count 0 2006.285.17:55:48.75#ibcon#enter sib2, iclass 26, count 0 2006.285.17:55:48.75#ibcon#flushed, iclass 26, count 0 2006.285.17:55:48.75#ibcon#about to write, iclass 26, count 0 2006.285.17:55:48.75#ibcon#wrote, iclass 26, count 0 2006.285.17:55:48.75#ibcon#about to read 3, iclass 26, count 0 2006.285.17:55:48.79#ibcon#read 3, iclass 26, count 0 2006.285.17:55:48.79#ibcon#about to read 4, iclass 26, count 0 2006.285.17:55:48.79#ibcon#read 4, iclass 26, count 0 2006.285.17:55:48.79#ibcon#about to read 5, iclass 26, count 0 2006.285.17:55:48.79#ibcon#read 5, iclass 26, count 0 2006.285.17:55:48.79#ibcon#about to read 6, iclass 26, count 0 2006.285.17:55:48.79#ibcon#read 6, iclass 26, count 0 2006.285.17:55:48.79#ibcon#end of sib2, iclass 26, count 0 2006.285.17:55:48.79#ibcon#*after write, iclass 26, count 0 2006.285.17:55:48.79#ibcon#*before return 0, iclass 26, count 0 2006.285.17:55:48.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:55:48.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:55:48.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.17:55:48.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.17:55:48.79$vck44/va=2,6 2006.285.17:55:48.79#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.17:55:48.79#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.17:55:48.79#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:48.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:55:48.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:55:48.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:55:48.85#ibcon#enter wrdev, iclass 28, count 2 2006.285.17:55:48.85#ibcon#first serial, iclass 28, count 2 2006.285.17:55:48.85#ibcon#enter sib2, iclass 28, count 2 2006.285.17:55:48.85#ibcon#flushed, iclass 28, count 2 2006.285.17:55:48.85#ibcon#about to write, iclass 28, count 2 2006.285.17:55:48.85#ibcon#wrote, iclass 28, count 2 2006.285.17:55:48.85#ibcon#about to read 3, iclass 28, count 2 2006.285.17:55:48.87#ibcon#read 3, iclass 28, count 2 2006.285.17:55:48.87#ibcon#about to read 4, iclass 28, count 2 2006.285.17:55:48.87#ibcon#read 4, iclass 28, count 2 2006.285.17:55:48.87#ibcon#about to read 5, iclass 28, count 2 2006.285.17:55:48.87#ibcon#read 5, iclass 28, count 2 2006.285.17:55:48.87#ibcon#about to read 6, iclass 28, count 2 2006.285.17:55:48.87#ibcon#read 6, iclass 28, count 2 2006.285.17:55:48.87#ibcon#end of sib2, iclass 28, count 2 2006.285.17:55:48.87#ibcon#*mode == 0, iclass 28, count 2 2006.285.17:55:48.87#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.17:55:48.87#ibcon#[25=AT02-06\r\n] 2006.285.17:55:48.87#ibcon#*before write, iclass 28, count 2 2006.285.17:55:48.87#ibcon#enter sib2, iclass 28, count 2 2006.285.17:55:48.87#ibcon#flushed, iclass 28, count 2 2006.285.17:55:48.87#ibcon#about to write, iclass 28, count 2 2006.285.17:55:48.87#ibcon#wrote, iclass 28, count 2 2006.285.17:55:48.87#ibcon#about to read 3, iclass 28, count 2 2006.285.17:55:48.90#ibcon#read 3, iclass 28, count 2 2006.285.17:55:48.90#ibcon#about to read 4, iclass 28, count 2 2006.285.17:55:48.90#ibcon#read 4, iclass 28, count 2 2006.285.17:55:48.90#ibcon#about to read 5, iclass 28, count 2 2006.285.17:55:48.90#ibcon#read 5, iclass 28, count 2 2006.285.17:55:48.90#ibcon#about to read 6, iclass 28, count 2 2006.285.17:55:48.90#ibcon#read 6, iclass 28, count 2 2006.285.17:55:48.90#ibcon#end of sib2, iclass 28, count 2 2006.285.17:55:48.90#ibcon#*after write, iclass 28, count 2 2006.285.17:55:48.90#ibcon#*before return 0, iclass 28, count 2 2006.285.17:55:48.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:55:48.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:55:48.90#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.17:55:48.90#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:48.90#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:55:49.02#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:55:49.02#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:55:49.02#ibcon#enter wrdev, iclass 28, count 0 2006.285.17:55:49.02#ibcon#first serial, iclass 28, count 0 2006.285.17:55:49.02#ibcon#enter sib2, iclass 28, count 0 2006.285.17:55:49.02#ibcon#flushed, iclass 28, count 0 2006.285.17:55:49.02#ibcon#about to write, iclass 28, count 0 2006.285.17:55:49.02#ibcon#wrote, iclass 28, count 0 2006.285.17:55:49.02#ibcon#about to read 3, iclass 28, count 0 2006.285.17:55:49.04#ibcon#read 3, iclass 28, count 0 2006.285.17:55:49.04#ibcon#about to read 4, iclass 28, count 0 2006.285.17:55:49.04#ibcon#read 4, iclass 28, count 0 2006.285.17:55:49.04#ibcon#about to read 5, iclass 28, count 0 2006.285.17:55:49.04#ibcon#read 5, iclass 28, count 0 2006.285.17:55:49.04#ibcon#about to read 6, iclass 28, count 0 2006.285.17:55:49.04#ibcon#read 6, iclass 28, count 0 2006.285.17:55:49.04#ibcon#end of sib2, iclass 28, count 0 2006.285.17:55:49.04#ibcon#*mode == 0, iclass 28, count 0 2006.285.17:55:49.04#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.17:55:49.04#ibcon#[25=USB\r\n] 2006.285.17:55:49.04#ibcon#*before write, iclass 28, count 0 2006.285.17:55:49.04#ibcon#enter sib2, iclass 28, count 0 2006.285.17:55:49.04#ibcon#flushed, iclass 28, count 0 2006.285.17:55:49.04#ibcon#about to write, iclass 28, count 0 2006.285.17:55:49.04#ibcon#wrote, iclass 28, count 0 2006.285.17:55:49.04#ibcon#about to read 3, iclass 28, count 0 2006.285.17:55:49.07#ibcon#read 3, iclass 28, count 0 2006.285.17:55:49.07#ibcon#about to read 4, iclass 28, count 0 2006.285.17:55:49.07#ibcon#read 4, iclass 28, count 0 2006.285.17:55:49.07#ibcon#about to read 5, iclass 28, count 0 2006.285.17:55:49.07#ibcon#read 5, iclass 28, count 0 2006.285.17:55:49.07#ibcon#about to read 6, iclass 28, count 0 2006.285.17:55:49.07#ibcon#read 6, iclass 28, count 0 2006.285.17:55:49.07#ibcon#end of sib2, iclass 28, count 0 2006.285.17:55:49.07#ibcon#*after write, iclass 28, count 0 2006.285.17:55:49.07#ibcon#*before return 0, iclass 28, count 0 2006.285.17:55:49.07#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:55:49.07#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:55:49.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.17:55:49.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.17:55:49.07$vck44/valo=3,564.99 2006.285.17:55:49.07#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.17:55:49.07#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.17:55:49.07#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:49.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:55:49.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:55:49.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:55:49.07#ibcon#enter wrdev, iclass 30, count 0 2006.285.17:55:49.07#ibcon#first serial, iclass 30, count 0 2006.285.17:55:49.07#ibcon#enter sib2, iclass 30, count 0 2006.285.17:55:49.07#ibcon#flushed, iclass 30, count 0 2006.285.17:55:49.07#ibcon#about to write, iclass 30, count 0 2006.285.17:55:49.07#ibcon#wrote, iclass 30, count 0 2006.285.17:55:49.07#ibcon#about to read 3, iclass 30, count 0 2006.285.17:55:49.09#ibcon#read 3, iclass 30, count 0 2006.285.17:55:49.09#ibcon#about to read 4, iclass 30, count 0 2006.285.17:55:49.09#ibcon#read 4, iclass 30, count 0 2006.285.17:55:49.09#ibcon#about to read 5, iclass 30, count 0 2006.285.17:55:49.09#ibcon#read 5, iclass 30, count 0 2006.285.17:55:49.09#ibcon#about to read 6, iclass 30, count 0 2006.285.17:55:49.09#ibcon#read 6, iclass 30, count 0 2006.285.17:55:49.09#ibcon#end of sib2, iclass 30, count 0 2006.285.17:55:49.09#ibcon#*mode == 0, iclass 30, count 0 2006.285.17:55:49.09#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.17:55:49.09#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.17:55:49.09#ibcon#*before write, iclass 30, count 0 2006.285.17:55:49.09#ibcon#enter sib2, iclass 30, count 0 2006.285.17:55:49.09#ibcon#flushed, iclass 30, count 0 2006.285.17:55:49.09#ibcon#about to write, iclass 30, count 0 2006.285.17:55:49.09#ibcon#wrote, iclass 30, count 0 2006.285.17:55:49.09#ibcon#about to read 3, iclass 30, count 0 2006.285.17:55:49.13#ibcon#read 3, iclass 30, count 0 2006.285.17:55:49.13#ibcon#about to read 4, iclass 30, count 0 2006.285.17:55:49.13#ibcon#read 4, iclass 30, count 0 2006.285.17:55:49.13#ibcon#about to read 5, iclass 30, count 0 2006.285.17:55:49.13#ibcon#read 5, iclass 30, count 0 2006.285.17:55:49.13#ibcon#about to read 6, iclass 30, count 0 2006.285.17:55:49.13#ibcon#read 6, iclass 30, count 0 2006.285.17:55:49.13#ibcon#end of sib2, iclass 30, count 0 2006.285.17:55:49.13#ibcon#*after write, iclass 30, count 0 2006.285.17:55:49.13#ibcon#*before return 0, iclass 30, count 0 2006.285.17:55:49.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:55:49.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:55:49.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.17:55:49.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.17:55:49.13$vck44/va=3,7 2006.285.17:55:49.13#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.17:55:49.13#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.17:55:49.13#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:49.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:55:49.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:55:49.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:55:49.19#ibcon#enter wrdev, iclass 32, count 2 2006.285.17:55:49.19#ibcon#first serial, iclass 32, count 2 2006.285.17:55:49.19#ibcon#enter sib2, iclass 32, count 2 2006.285.17:55:49.19#ibcon#flushed, iclass 32, count 2 2006.285.17:55:49.19#ibcon#about to write, iclass 32, count 2 2006.285.17:55:49.19#ibcon#wrote, iclass 32, count 2 2006.285.17:55:49.19#ibcon#about to read 3, iclass 32, count 2 2006.285.17:55:49.21#ibcon#read 3, iclass 32, count 2 2006.285.17:55:49.21#ibcon#about to read 4, iclass 32, count 2 2006.285.17:55:49.21#ibcon#read 4, iclass 32, count 2 2006.285.17:55:49.21#ibcon#about to read 5, iclass 32, count 2 2006.285.17:55:49.21#ibcon#read 5, iclass 32, count 2 2006.285.17:55:49.21#ibcon#about to read 6, iclass 32, count 2 2006.285.17:55:49.21#ibcon#read 6, iclass 32, count 2 2006.285.17:55:49.21#ibcon#end of sib2, iclass 32, count 2 2006.285.17:55:49.21#ibcon#*mode == 0, iclass 32, count 2 2006.285.17:55:49.21#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.17:55:49.21#ibcon#[25=AT03-07\r\n] 2006.285.17:55:49.21#ibcon#*before write, iclass 32, count 2 2006.285.17:55:49.21#ibcon#enter sib2, iclass 32, count 2 2006.285.17:55:49.21#ibcon#flushed, iclass 32, count 2 2006.285.17:55:49.21#ibcon#about to write, iclass 32, count 2 2006.285.17:55:49.21#ibcon#wrote, iclass 32, count 2 2006.285.17:55:49.21#ibcon#about to read 3, iclass 32, count 2 2006.285.17:55:49.24#ibcon#read 3, iclass 32, count 2 2006.285.17:55:49.67#ibcon#about to read 4, iclass 32, count 2 2006.285.17:55:49.67#ibcon#read 4, iclass 32, count 2 2006.285.17:55:49.67#ibcon#about to read 5, iclass 32, count 2 2006.285.17:55:49.67#ibcon#read 5, iclass 32, count 2 2006.285.17:55:49.67#ibcon#about to read 6, iclass 32, count 2 2006.285.17:55:49.67#ibcon#read 6, iclass 32, count 2 2006.285.17:55:49.67#ibcon#end of sib2, iclass 32, count 2 2006.285.17:55:49.67#ibcon#*after write, iclass 32, count 2 2006.285.17:55:49.67#ibcon#*before return 0, iclass 32, count 2 2006.285.17:55:49.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:55:49.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:55:49.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.17:55:49.67#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:49.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:55:49.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:55:49.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:55:49.78#ibcon#enter wrdev, iclass 32, count 0 2006.285.17:55:49.78#ibcon#first serial, iclass 32, count 0 2006.285.17:55:49.78#ibcon#enter sib2, iclass 32, count 0 2006.285.17:55:49.78#ibcon#flushed, iclass 32, count 0 2006.285.17:55:49.78#ibcon#about to write, iclass 32, count 0 2006.285.17:55:49.78#ibcon#wrote, iclass 32, count 0 2006.285.17:55:49.78#ibcon#about to read 3, iclass 32, count 0 2006.285.17:55:49.80#ibcon#read 3, iclass 32, count 0 2006.285.17:55:49.80#ibcon#about to read 4, iclass 32, count 0 2006.285.17:55:49.80#ibcon#read 4, iclass 32, count 0 2006.285.17:55:49.80#ibcon#about to read 5, iclass 32, count 0 2006.285.17:55:49.80#ibcon#read 5, iclass 32, count 0 2006.285.17:55:49.80#ibcon#about to read 6, iclass 32, count 0 2006.285.17:55:49.80#ibcon#read 6, iclass 32, count 0 2006.285.17:55:49.80#ibcon#end of sib2, iclass 32, count 0 2006.285.17:55:49.80#ibcon#*mode == 0, iclass 32, count 0 2006.285.17:55:49.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.17:55:49.80#ibcon#[25=USB\r\n] 2006.285.17:55:49.80#ibcon#*before write, iclass 32, count 0 2006.285.17:55:49.80#ibcon#enter sib2, iclass 32, count 0 2006.285.17:55:49.80#ibcon#flushed, iclass 32, count 0 2006.285.17:55:49.80#ibcon#about to write, iclass 32, count 0 2006.285.17:55:49.80#ibcon#wrote, iclass 32, count 0 2006.285.17:55:49.80#ibcon#about to read 3, iclass 32, count 0 2006.285.17:55:49.83#ibcon#read 3, iclass 32, count 0 2006.285.17:55:49.83#ibcon#about to read 4, iclass 32, count 0 2006.285.17:55:49.83#ibcon#read 4, iclass 32, count 0 2006.285.17:55:49.83#ibcon#about to read 5, iclass 32, count 0 2006.285.17:55:49.83#ibcon#read 5, iclass 32, count 0 2006.285.17:55:49.83#ibcon#about to read 6, iclass 32, count 0 2006.285.17:55:49.83#ibcon#read 6, iclass 32, count 0 2006.285.17:55:49.83#ibcon#end of sib2, iclass 32, count 0 2006.285.17:55:49.83#ibcon#*after write, iclass 32, count 0 2006.285.17:55:49.83#ibcon#*before return 0, iclass 32, count 0 2006.285.17:55:49.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:55:49.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:55:49.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.17:55:49.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.17:55:49.83$vck44/valo=4,624.99 2006.285.17:55:49.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.17:55:49.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.17:55:49.83#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:49.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:55:49.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:55:49.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:55:49.83#ibcon#enter wrdev, iclass 34, count 0 2006.285.17:55:49.83#ibcon#first serial, iclass 34, count 0 2006.285.17:55:49.83#ibcon#enter sib2, iclass 34, count 0 2006.285.17:55:49.83#ibcon#flushed, iclass 34, count 0 2006.285.17:55:49.83#ibcon#about to write, iclass 34, count 0 2006.285.17:55:49.83#ibcon#wrote, iclass 34, count 0 2006.285.17:55:49.83#ibcon#about to read 3, iclass 34, count 0 2006.285.17:55:49.85#ibcon#read 3, iclass 34, count 0 2006.285.17:55:49.85#ibcon#about to read 4, iclass 34, count 0 2006.285.17:55:49.85#ibcon#read 4, iclass 34, count 0 2006.285.17:55:49.85#ibcon#about to read 5, iclass 34, count 0 2006.285.17:55:49.85#ibcon#read 5, iclass 34, count 0 2006.285.17:55:49.85#ibcon#about to read 6, iclass 34, count 0 2006.285.17:55:49.85#ibcon#read 6, iclass 34, count 0 2006.285.17:55:49.85#ibcon#end of sib2, iclass 34, count 0 2006.285.17:55:49.85#ibcon#*mode == 0, iclass 34, count 0 2006.285.17:55:49.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.17:55:49.85#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.17:55:49.85#ibcon#*before write, iclass 34, count 0 2006.285.17:55:49.85#ibcon#enter sib2, iclass 34, count 0 2006.285.17:55:49.85#ibcon#flushed, iclass 34, count 0 2006.285.17:55:49.85#ibcon#about to write, iclass 34, count 0 2006.285.17:55:49.85#ibcon#wrote, iclass 34, count 0 2006.285.17:55:49.85#ibcon#about to read 3, iclass 34, count 0 2006.285.17:55:49.89#ibcon#read 3, iclass 34, count 0 2006.285.17:55:49.89#ibcon#about to read 4, iclass 34, count 0 2006.285.17:55:49.89#ibcon#read 4, iclass 34, count 0 2006.285.17:55:49.89#ibcon#about to read 5, iclass 34, count 0 2006.285.17:55:49.89#ibcon#read 5, iclass 34, count 0 2006.285.17:55:49.89#ibcon#about to read 6, iclass 34, count 0 2006.285.17:55:49.89#ibcon#read 6, iclass 34, count 0 2006.285.17:55:49.89#ibcon#end of sib2, iclass 34, count 0 2006.285.17:55:49.89#ibcon#*after write, iclass 34, count 0 2006.285.17:55:49.89#ibcon#*before return 0, iclass 34, count 0 2006.285.17:55:49.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:55:49.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:55:49.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.17:55:49.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.17:55:49.89$vck44/va=4,6 2006.285.17:55:49.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.17:55:49.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.17:55:49.89#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:49.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:55:49.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:55:49.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:55:49.95#ibcon#enter wrdev, iclass 36, count 2 2006.285.17:55:49.95#ibcon#first serial, iclass 36, count 2 2006.285.17:55:49.95#ibcon#enter sib2, iclass 36, count 2 2006.285.17:55:49.95#ibcon#flushed, iclass 36, count 2 2006.285.17:55:49.95#ibcon#about to write, iclass 36, count 2 2006.285.17:55:49.95#ibcon#wrote, iclass 36, count 2 2006.285.17:55:49.95#ibcon#about to read 3, iclass 36, count 2 2006.285.17:55:49.97#ibcon#read 3, iclass 36, count 2 2006.285.17:55:49.97#ibcon#about to read 4, iclass 36, count 2 2006.285.17:55:49.97#ibcon#read 4, iclass 36, count 2 2006.285.17:55:49.97#ibcon#about to read 5, iclass 36, count 2 2006.285.17:55:49.97#ibcon#read 5, iclass 36, count 2 2006.285.17:55:49.97#ibcon#about to read 6, iclass 36, count 2 2006.285.17:55:49.97#ibcon#read 6, iclass 36, count 2 2006.285.17:55:49.97#ibcon#end of sib2, iclass 36, count 2 2006.285.17:55:49.97#ibcon#*mode == 0, iclass 36, count 2 2006.285.17:55:49.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.17:55:49.97#ibcon#[25=AT04-06\r\n] 2006.285.17:55:49.97#ibcon#*before write, iclass 36, count 2 2006.285.17:55:49.97#ibcon#enter sib2, iclass 36, count 2 2006.285.17:55:49.97#ibcon#flushed, iclass 36, count 2 2006.285.17:55:49.97#ibcon#about to write, iclass 36, count 2 2006.285.17:55:49.97#ibcon#wrote, iclass 36, count 2 2006.285.17:55:49.97#ibcon#about to read 3, iclass 36, count 2 2006.285.17:55:50.00#ibcon#read 3, iclass 36, count 2 2006.285.17:55:50.00#ibcon#about to read 4, iclass 36, count 2 2006.285.17:55:50.00#ibcon#read 4, iclass 36, count 2 2006.285.17:55:50.00#ibcon#about to read 5, iclass 36, count 2 2006.285.17:55:50.00#ibcon#read 5, iclass 36, count 2 2006.285.17:55:50.00#ibcon#about to read 6, iclass 36, count 2 2006.285.17:55:50.00#ibcon#read 6, iclass 36, count 2 2006.285.17:55:50.00#ibcon#end of sib2, iclass 36, count 2 2006.285.17:55:50.00#ibcon#*after write, iclass 36, count 2 2006.285.17:55:50.00#ibcon#*before return 0, iclass 36, count 2 2006.285.17:55:50.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:55:50.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:55:50.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.17:55:50.00#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:50.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:55:50.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:55:50.36#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:55:50.36#ibcon#enter wrdev, iclass 36, count 0 2006.285.17:55:50.36#ibcon#first serial, iclass 36, count 0 2006.285.17:55:50.36#ibcon#enter sib2, iclass 36, count 0 2006.285.17:55:50.36#ibcon#flushed, iclass 36, count 0 2006.285.17:55:50.36#ibcon#about to write, iclass 36, count 0 2006.285.17:55:50.36#ibcon#wrote, iclass 36, count 0 2006.285.17:55:50.36#ibcon#about to read 3, iclass 36, count 0 2006.285.17:55:50.37#ibcon#read 3, iclass 36, count 0 2006.285.17:55:50.37#ibcon#about to read 4, iclass 36, count 0 2006.285.17:55:50.37#ibcon#read 4, iclass 36, count 0 2006.285.17:55:50.37#ibcon#about to read 5, iclass 36, count 0 2006.285.17:55:50.37#ibcon#read 5, iclass 36, count 0 2006.285.17:55:50.37#ibcon#about to read 6, iclass 36, count 0 2006.285.17:55:50.37#ibcon#read 6, iclass 36, count 0 2006.285.17:55:50.37#ibcon#end of sib2, iclass 36, count 0 2006.285.17:55:50.37#ibcon#*mode == 0, iclass 36, count 0 2006.285.17:55:50.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.17:55:50.37#ibcon#[25=USB\r\n] 2006.285.17:55:50.37#ibcon#*before write, iclass 36, count 0 2006.285.17:55:50.37#ibcon#enter sib2, iclass 36, count 0 2006.285.17:55:50.37#ibcon#flushed, iclass 36, count 0 2006.285.17:55:50.37#ibcon#about to write, iclass 36, count 0 2006.285.17:55:50.37#ibcon#wrote, iclass 36, count 0 2006.285.17:55:50.37#ibcon#about to read 3, iclass 36, count 0 2006.285.17:55:50.40#ibcon#read 3, iclass 36, count 0 2006.285.17:55:50.40#ibcon#about to read 4, iclass 36, count 0 2006.285.17:55:50.40#ibcon#read 4, iclass 36, count 0 2006.285.17:55:50.40#ibcon#about to read 5, iclass 36, count 0 2006.285.17:55:50.40#ibcon#read 5, iclass 36, count 0 2006.285.17:55:50.40#ibcon#about to read 6, iclass 36, count 0 2006.285.17:55:50.40#ibcon#read 6, iclass 36, count 0 2006.285.17:55:50.40#ibcon#end of sib2, iclass 36, count 0 2006.285.17:55:50.40#ibcon#*after write, iclass 36, count 0 2006.285.17:55:50.40#ibcon#*before return 0, iclass 36, count 0 2006.285.17:55:50.40#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:55:50.40#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:55:50.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.17:55:50.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.17:55:50.40$vck44/valo=5,734.99 2006.285.17:55:50.40#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.17:55:50.40#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.17:55:50.40#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:50.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:55:50.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:55:50.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:55:50.40#ibcon#enter wrdev, iclass 38, count 0 2006.285.17:55:50.40#ibcon#first serial, iclass 38, count 0 2006.285.17:55:50.40#ibcon#enter sib2, iclass 38, count 0 2006.285.17:55:50.40#ibcon#flushed, iclass 38, count 0 2006.285.17:55:50.40#ibcon#about to write, iclass 38, count 0 2006.285.17:55:50.40#ibcon#wrote, iclass 38, count 0 2006.285.17:55:50.40#ibcon#about to read 3, iclass 38, count 0 2006.285.17:55:50.42#ibcon#read 3, iclass 38, count 0 2006.285.17:55:50.42#ibcon#about to read 4, iclass 38, count 0 2006.285.17:55:50.42#ibcon#read 4, iclass 38, count 0 2006.285.17:55:50.42#ibcon#about to read 5, iclass 38, count 0 2006.285.17:55:50.42#ibcon#read 5, iclass 38, count 0 2006.285.17:55:50.42#ibcon#about to read 6, iclass 38, count 0 2006.285.17:55:50.42#ibcon#read 6, iclass 38, count 0 2006.285.17:55:50.42#ibcon#end of sib2, iclass 38, count 0 2006.285.17:55:50.42#ibcon#*mode == 0, iclass 38, count 0 2006.285.17:55:50.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.17:55:50.42#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.17:55:50.42#ibcon#*before write, iclass 38, count 0 2006.285.17:55:50.42#ibcon#enter sib2, iclass 38, count 0 2006.285.17:55:50.42#ibcon#flushed, iclass 38, count 0 2006.285.17:55:50.42#ibcon#about to write, iclass 38, count 0 2006.285.17:55:50.42#ibcon#wrote, iclass 38, count 0 2006.285.17:55:50.42#ibcon#about to read 3, iclass 38, count 0 2006.285.17:55:50.46#ibcon#read 3, iclass 38, count 0 2006.285.17:55:50.46#ibcon#about to read 4, iclass 38, count 0 2006.285.17:55:50.46#ibcon#read 4, iclass 38, count 0 2006.285.17:55:50.46#ibcon#about to read 5, iclass 38, count 0 2006.285.17:55:50.46#ibcon#read 5, iclass 38, count 0 2006.285.17:55:50.46#ibcon#about to read 6, iclass 38, count 0 2006.285.17:55:50.46#ibcon#read 6, iclass 38, count 0 2006.285.17:55:50.46#ibcon#end of sib2, iclass 38, count 0 2006.285.17:55:50.46#ibcon#*after write, iclass 38, count 0 2006.285.17:55:50.46#ibcon#*before return 0, iclass 38, count 0 2006.285.17:55:50.46#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:55:50.46#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:55:50.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.17:55:50.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.17:55:50.46$vck44/va=5,3 2006.285.17:55:50.46#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.17:55:50.46#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.17:55:50.46#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:50.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:55:50.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:55:50.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:55:50.52#ibcon#enter wrdev, iclass 40, count 2 2006.285.17:55:50.52#ibcon#first serial, iclass 40, count 2 2006.285.17:55:50.52#ibcon#enter sib2, iclass 40, count 2 2006.285.17:55:50.52#ibcon#flushed, iclass 40, count 2 2006.285.17:55:50.52#ibcon#about to write, iclass 40, count 2 2006.285.17:55:50.52#ibcon#wrote, iclass 40, count 2 2006.285.17:55:50.52#ibcon#about to read 3, iclass 40, count 2 2006.285.17:55:50.54#ibcon#read 3, iclass 40, count 2 2006.285.17:55:50.54#ibcon#about to read 4, iclass 40, count 2 2006.285.17:55:50.54#ibcon#read 4, iclass 40, count 2 2006.285.17:55:50.54#ibcon#about to read 5, iclass 40, count 2 2006.285.17:55:50.54#ibcon#read 5, iclass 40, count 2 2006.285.17:55:50.54#ibcon#about to read 6, iclass 40, count 2 2006.285.17:55:50.54#ibcon#read 6, iclass 40, count 2 2006.285.17:55:50.54#ibcon#end of sib2, iclass 40, count 2 2006.285.17:55:50.54#ibcon#*mode == 0, iclass 40, count 2 2006.285.17:55:50.54#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.17:55:50.54#ibcon#[25=AT05-03\r\n] 2006.285.17:55:50.54#ibcon#*before write, iclass 40, count 2 2006.285.17:55:50.54#ibcon#enter sib2, iclass 40, count 2 2006.285.17:55:50.54#ibcon#flushed, iclass 40, count 2 2006.285.17:55:50.54#ibcon#about to write, iclass 40, count 2 2006.285.17:55:50.54#ibcon#wrote, iclass 40, count 2 2006.285.17:55:50.54#ibcon#about to read 3, iclass 40, count 2 2006.285.17:55:50.57#ibcon#read 3, iclass 40, count 2 2006.285.17:55:50.57#ibcon#about to read 4, iclass 40, count 2 2006.285.17:55:50.57#ibcon#read 4, iclass 40, count 2 2006.285.17:55:50.57#ibcon#about to read 5, iclass 40, count 2 2006.285.17:55:50.57#ibcon#read 5, iclass 40, count 2 2006.285.17:55:50.57#ibcon#about to read 6, iclass 40, count 2 2006.285.17:55:50.57#ibcon#read 6, iclass 40, count 2 2006.285.17:55:50.57#ibcon#end of sib2, iclass 40, count 2 2006.285.17:55:50.57#ibcon#*after write, iclass 40, count 2 2006.285.17:55:50.57#ibcon#*before return 0, iclass 40, count 2 2006.285.17:55:50.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:55:50.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:55:50.57#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.17:55:50.57#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:50.57#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:55:50.69#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:55:50.72#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:55:50.72#ibcon#enter wrdev, iclass 40, count 0 2006.285.17:55:50.72#ibcon#first serial, iclass 40, count 0 2006.285.17:55:50.72#ibcon#enter sib2, iclass 40, count 0 2006.285.17:55:50.72#ibcon#flushed, iclass 40, count 0 2006.285.17:55:50.72#ibcon#about to write, iclass 40, count 0 2006.285.17:55:50.72#ibcon#wrote, iclass 40, count 0 2006.285.17:55:50.72#ibcon#about to read 3, iclass 40, count 0 2006.285.17:55:50.73#ibcon#read 3, iclass 40, count 0 2006.285.17:55:50.73#ibcon#about to read 4, iclass 40, count 0 2006.285.17:55:50.73#ibcon#read 4, iclass 40, count 0 2006.285.17:55:50.73#ibcon#about to read 5, iclass 40, count 0 2006.285.17:55:50.73#ibcon#read 5, iclass 40, count 0 2006.285.17:55:50.73#ibcon#about to read 6, iclass 40, count 0 2006.285.17:55:50.73#ibcon#read 6, iclass 40, count 0 2006.285.17:55:50.73#ibcon#end of sib2, iclass 40, count 0 2006.285.17:55:50.73#ibcon#*mode == 0, iclass 40, count 0 2006.285.17:55:50.73#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.17:55:50.73#ibcon#[25=USB\r\n] 2006.285.17:55:50.73#ibcon#*before write, iclass 40, count 0 2006.285.17:55:50.73#ibcon#enter sib2, iclass 40, count 0 2006.285.17:55:50.73#ibcon#flushed, iclass 40, count 0 2006.285.17:55:50.73#ibcon#about to write, iclass 40, count 0 2006.285.17:55:50.73#ibcon#wrote, iclass 40, count 0 2006.285.17:55:50.73#ibcon#about to read 3, iclass 40, count 0 2006.285.17:55:50.76#ibcon#read 3, iclass 40, count 0 2006.285.17:55:50.76#ibcon#about to read 4, iclass 40, count 0 2006.285.17:55:50.76#ibcon#read 4, iclass 40, count 0 2006.285.17:55:50.76#ibcon#about to read 5, iclass 40, count 0 2006.285.17:55:50.76#ibcon#read 5, iclass 40, count 0 2006.285.17:55:50.76#ibcon#about to read 6, iclass 40, count 0 2006.285.17:55:50.76#ibcon#read 6, iclass 40, count 0 2006.285.17:55:50.76#ibcon#end of sib2, iclass 40, count 0 2006.285.17:55:50.76#ibcon#*after write, iclass 40, count 0 2006.285.17:55:50.76#ibcon#*before return 0, iclass 40, count 0 2006.285.17:55:50.76#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:55:50.76#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:55:50.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.17:55:50.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.17:55:50.76$vck44/valo=6,814.99 2006.285.17:55:50.76#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.17:55:50.76#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.17:55:50.76#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:50.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:55:50.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:55:50.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:55:50.76#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:55:50.76#ibcon#first serial, iclass 4, count 0 2006.285.17:55:50.76#ibcon#enter sib2, iclass 4, count 0 2006.285.17:55:50.76#ibcon#flushed, iclass 4, count 0 2006.285.17:55:50.76#ibcon#about to write, iclass 4, count 0 2006.285.17:55:50.76#ibcon#wrote, iclass 4, count 0 2006.285.17:55:50.76#ibcon#about to read 3, iclass 4, count 0 2006.285.17:55:50.78#ibcon#read 3, iclass 4, count 0 2006.285.17:55:50.78#ibcon#about to read 4, iclass 4, count 0 2006.285.17:55:50.78#ibcon#read 4, iclass 4, count 0 2006.285.17:55:50.78#ibcon#about to read 5, iclass 4, count 0 2006.285.17:55:50.78#ibcon#read 5, iclass 4, count 0 2006.285.17:55:50.78#ibcon#about to read 6, iclass 4, count 0 2006.285.17:55:50.78#ibcon#read 6, iclass 4, count 0 2006.285.17:55:50.78#ibcon#end of sib2, iclass 4, count 0 2006.285.17:55:50.78#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:55:50.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:55:50.78#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.17:55:50.78#ibcon#*before write, iclass 4, count 0 2006.285.17:55:50.78#ibcon#enter sib2, iclass 4, count 0 2006.285.17:55:50.78#ibcon#flushed, iclass 4, count 0 2006.285.17:55:50.78#ibcon#about to write, iclass 4, count 0 2006.285.17:55:50.78#ibcon#wrote, iclass 4, count 0 2006.285.17:55:50.78#ibcon#about to read 3, iclass 4, count 0 2006.285.17:55:50.82#ibcon#read 3, iclass 4, count 0 2006.285.17:55:50.82#ibcon#about to read 4, iclass 4, count 0 2006.285.17:55:50.82#ibcon#read 4, iclass 4, count 0 2006.285.17:55:50.82#ibcon#about to read 5, iclass 4, count 0 2006.285.17:55:50.82#ibcon#read 5, iclass 4, count 0 2006.285.17:55:50.82#ibcon#about to read 6, iclass 4, count 0 2006.285.17:55:50.82#ibcon#read 6, iclass 4, count 0 2006.285.17:55:50.82#ibcon#end of sib2, iclass 4, count 0 2006.285.17:55:50.82#ibcon#*after write, iclass 4, count 0 2006.285.17:55:50.82#ibcon#*before return 0, iclass 4, count 0 2006.285.17:55:50.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:55:50.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:55:50.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:55:50.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:55:50.82$vck44/va=6,4 2006.285.17:55:50.82#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.17:55:50.82#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.17:55:50.82#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:50.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:55:50.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:55:50.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:55:50.88#ibcon#enter wrdev, iclass 6, count 2 2006.285.17:55:50.88#ibcon#first serial, iclass 6, count 2 2006.285.17:55:50.88#ibcon#enter sib2, iclass 6, count 2 2006.285.17:55:50.88#ibcon#flushed, iclass 6, count 2 2006.285.17:55:50.88#ibcon#about to write, iclass 6, count 2 2006.285.17:55:50.88#ibcon#wrote, iclass 6, count 2 2006.285.17:55:50.88#ibcon#about to read 3, iclass 6, count 2 2006.285.17:55:50.90#ibcon#read 3, iclass 6, count 2 2006.285.17:55:50.90#ibcon#about to read 4, iclass 6, count 2 2006.285.17:55:50.90#ibcon#read 4, iclass 6, count 2 2006.285.17:55:50.90#ibcon#about to read 5, iclass 6, count 2 2006.285.17:55:50.90#ibcon#read 5, iclass 6, count 2 2006.285.17:55:50.90#ibcon#about to read 6, iclass 6, count 2 2006.285.17:55:50.90#ibcon#read 6, iclass 6, count 2 2006.285.17:55:50.90#ibcon#end of sib2, iclass 6, count 2 2006.285.17:55:50.90#ibcon#*mode == 0, iclass 6, count 2 2006.285.17:55:50.90#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.17:55:50.90#ibcon#[25=AT06-04\r\n] 2006.285.17:55:50.90#ibcon#*before write, iclass 6, count 2 2006.285.17:55:50.90#ibcon#enter sib2, iclass 6, count 2 2006.285.17:55:50.90#ibcon#flushed, iclass 6, count 2 2006.285.17:55:50.90#ibcon#about to write, iclass 6, count 2 2006.285.17:55:50.90#ibcon#wrote, iclass 6, count 2 2006.285.17:55:50.90#ibcon#about to read 3, iclass 6, count 2 2006.285.17:55:50.93#ibcon#read 3, iclass 6, count 2 2006.285.17:55:50.93#ibcon#about to read 4, iclass 6, count 2 2006.285.17:55:50.93#ibcon#read 4, iclass 6, count 2 2006.285.17:55:50.93#ibcon#about to read 5, iclass 6, count 2 2006.285.17:55:50.93#ibcon#read 5, iclass 6, count 2 2006.285.17:55:50.93#ibcon#about to read 6, iclass 6, count 2 2006.285.17:55:50.93#ibcon#read 6, iclass 6, count 2 2006.285.17:55:50.93#ibcon#end of sib2, iclass 6, count 2 2006.285.17:55:50.93#ibcon#*after write, iclass 6, count 2 2006.285.17:55:50.93#ibcon#*before return 0, iclass 6, count 2 2006.285.17:55:50.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:55:50.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:55:50.93#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.17:55:50.93#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:50.93#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:55:51.05#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:55:51.05#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:55:51.05#ibcon#enter wrdev, iclass 6, count 0 2006.285.17:55:51.05#ibcon#first serial, iclass 6, count 0 2006.285.17:55:51.05#ibcon#enter sib2, iclass 6, count 0 2006.285.17:55:51.05#ibcon#flushed, iclass 6, count 0 2006.285.17:55:51.05#ibcon#about to write, iclass 6, count 0 2006.285.17:55:51.05#ibcon#wrote, iclass 6, count 0 2006.285.17:55:51.05#ibcon#about to read 3, iclass 6, count 0 2006.285.17:55:51.07#ibcon#read 3, iclass 6, count 0 2006.285.17:55:51.07#ibcon#about to read 4, iclass 6, count 0 2006.285.17:55:51.07#ibcon#read 4, iclass 6, count 0 2006.285.17:55:51.07#ibcon#about to read 5, iclass 6, count 0 2006.285.17:55:51.07#ibcon#read 5, iclass 6, count 0 2006.285.17:55:51.07#ibcon#about to read 6, iclass 6, count 0 2006.285.17:55:51.07#ibcon#read 6, iclass 6, count 0 2006.285.17:55:51.07#ibcon#end of sib2, iclass 6, count 0 2006.285.17:55:51.07#ibcon#*mode == 0, iclass 6, count 0 2006.285.17:55:51.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.17:55:51.07#ibcon#[25=USB\r\n] 2006.285.17:55:51.07#ibcon#*before write, iclass 6, count 0 2006.285.17:55:51.07#ibcon#enter sib2, iclass 6, count 0 2006.285.17:55:51.07#ibcon#flushed, iclass 6, count 0 2006.285.17:55:51.07#ibcon#about to write, iclass 6, count 0 2006.285.17:55:51.07#ibcon#wrote, iclass 6, count 0 2006.285.17:55:51.07#ibcon#about to read 3, iclass 6, count 0 2006.285.17:55:51.10#ibcon#read 3, iclass 6, count 0 2006.285.17:55:51.10#ibcon#about to read 4, iclass 6, count 0 2006.285.17:55:51.10#ibcon#read 4, iclass 6, count 0 2006.285.17:55:51.10#ibcon#about to read 5, iclass 6, count 0 2006.285.17:55:51.10#ibcon#read 5, iclass 6, count 0 2006.285.17:55:51.10#ibcon#about to read 6, iclass 6, count 0 2006.285.17:55:51.10#ibcon#read 6, iclass 6, count 0 2006.285.17:55:51.10#ibcon#end of sib2, iclass 6, count 0 2006.285.17:55:51.10#ibcon#*after write, iclass 6, count 0 2006.285.17:55:51.10#ibcon#*before return 0, iclass 6, count 0 2006.285.17:55:51.10#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:55:51.10#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:55:51.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.17:55:51.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.17:55:51.10$vck44/valo=7,864.99 2006.285.17:55:51.10#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.17:55:51.10#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.17:55:51.10#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:51.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:55:51.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:55:51.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:55:51.10#ibcon#enter wrdev, iclass 10, count 0 2006.285.17:55:51.10#ibcon#first serial, iclass 10, count 0 2006.285.17:55:51.10#ibcon#enter sib2, iclass 10, count 0 2006.285.17:55:51.10#ibcon#flushed, iclass 10, count 0 2006.285.17:55:51.10#ibcon#about to write, iclass 10, count 0 2006.285.17:55:51.10#ibcon#wrote, iclass 10, count 0 2006.285.17:55:51.10#ibcon#about to read 3, iclass 10, count 0 2006.285.17:55:51.12#ibcon#read 3, iclass 10, count 0 2006.285.17:55:51.12#ibcon#about to read 4, iclass 10, count 0 2006.285.17:55:51.12#ibcon#read 4, iclass 10, count 0 2006.285.17:55:51.12#ibcon#about to read 5, iclass 10, count 0 2006.285.17:55:51.12#ibcon#read 5, iclass 10, count 0 2006.285.17:55:51.12#ibcon#about to read 6, iclass 10, count 0 2006.285.17:55:51.12#ibcon#read 6, iclass 10, count 0 2006.285.17:55:51.12#ibcon#end of sib2, iclass 10, count 0 2006.285.17:55:51.12#ibcon#*mode == 0, iclass 10, count 0 2006.285.17:55:51.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.17:55:51.12#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.17:55:51.12#ibcon#*before write, iclass 10, count 0 2006.285.17:55:51.12#ibcon#enter sib2, iclass 10, count 0 2006.285.17:55:51.12#ibcon#flushed, iclass 10, count 0 2006.285.17:55:51.12#ibcon#about to write, iclass 10, count 0 2006.285.17:55:51.12#ibcon#wrote, iclass 10, count 0 2006.285.17:55:51.12#ibcon#about to read 3, iclass 10, count 0 2006.285.17:55:51.16#ibcon#read 3, iclass 10, count 0 2006.285.17:55:51.16#ibcon#about to read 4, iclass 10, count 0 2006.285.17:55:51.16#ibcon#read 4, iclass 10, count 0 2006.285.17:55:51.16#ibcon#about to read 5, iclass 10, count 0 2006.285.17:55:51.16#ibcon#read 5, iclass 10, count 0 2006.285.17:55:51.16#ibcon#about to read 6, iclass 10, count 0 2006.285.17:55:51.16#ibcon#read 6, iclass 10, count 0 2006.285.17:55:51.16#ibcon#end of sib2, iclass 10, count 0 2006.285.17:55:51.16#ibcon#*after write, iclass 10, count 0 2006.285.17:55:51.16#ibcon#*before return 0, iclass 10, count 0 2006.285.17:55:51.16#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:55:51.16#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:55:51.16#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.17:55:51.16#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.17:55:51.16$vck44/va=7,4 2006.285.17:55:51.16#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.17:55:51.16#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.17:55:51.16#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:51.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:55:51.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:55:51.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:55:51.22#ibcon#enter wrdev, iclass 12, count 2 2006.285.17:55:51.22#ibcon#first serial, iclass 12, count 2 2006.285.17:55:51.22#ibcon#enter sib2, iclass 12, count 2 2006.285.17:55:51.22#ibcon#flushed, iclass 12, count 2 2006.285.17:55:51.22#ibcon#about to write, iclass 12, count 2 2006.285.17:55:51.22#ibcon#wrote, iclass 12, count 2 2006.285.17:55:51.22#ibcon#about to read 3, iclass 12, count 2 2006.285.17:55:51.24#ibcon#read 3, iclass 12, count 2 2006.285.17:55:51.24#ibcon#about to read 4, iclass 12, count 2 2006.285.17:55:51.24#ibcon#read 4, iclass 12, count 2 2006.285.17:55:51.24#ibcon#about to read 5, iclass 12, count 2 2006.285.17:55:51.24#ibcon#read 5, iclass 12, count 2 2006.285.17:55:51.24#ibcon#about to read 6, iclass 12, count 2 2006.285.17:55:51.24#ibcon#read 6, iclass 12, count 2 2006.285.17:55:51.24#ibcon#end of sib2, iclass 12, count 2 2006.285.17:55:51.24#ibcon#*mode == 0, iclass 12, count 2 2006.285.17:55:51.24#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.17:55:51.24#ibcon#[25=AT07-04\r\n] 2006.285.17:55:51.24#ibcon#*before write, iclass 12, count 2 2006.285.17:55:51.24#ibcon#enter sib2, iclass 12, count 2 2006.285.17:55:51.24#ibcon#flushed, iclass 12, count 2 2006.285.17:55:51.24#ibcon#about to write, iclass 12, count 2 2006.285.17:55:51.24#ibcon#wrote, iclass 12, count 2 2006.285.17:55:51.24#ibcon#about to read 3, iclass 12, count 2 2006.285.17:55:51.27#ibcon#read 3, iclass 12, count 2 2006.285.17:55:51.27#ibcon#about to read 4, iclass 12, count 2 2006.285.17:55:51.29#ibcon#read 4, iclass 12, count 2 2006.285.17:55:51.29#ibcon#about to read 5, iclass 12, count 2 2006.285.17:55:51.29#ibcon#read 5, iclass 12, count 2 2006.285.17:55:51.29#ibcon#about to read 6, iclass 12, count 2 2006.285.17:55:51.29#ibcon#read 6, iclass 12, count 2 2006.285.17:55:51.29#ibcon#end of sib2, iclass 12, count 2 2006.285.17:55:51.29#ibcon#*after write, iclass 12, count 2 2006.285.17:55:51.29#ibcon#*before return 0, iclass 12, count 2 2006.285.17:55:51.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:55:51.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:55:51.29#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.17:55:51.29#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:51.29#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:55:51.41#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:55:51.41#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:55:51.41#ibcon#enter wrdev, iclass 12, count 0 2006.285.17:55:51.41#ibcon#first serial, iclass 12, count 0 2006.285.17:55:51.41#ibcon#enter sib2, iclass 12, count 0 2006.285.17:55:51.41#ibcon#flushed, iclass 12, count 0 2006.285.17:55:51.41#ibcon#about to write, iclass 12, count 0 2006.285.17:55:51.41#ibcon#wrote, iclass 12, count 0 2006.285.17:55:51.41#ibcon#about to read 3, iclass 12, count 0 2006.285.17:55:51.43#ibcon#read 3, iclass 12, count 0 2006.285.17:55:51.43#ibcon#about to read 4, iclass 12, count 0 2006.285.17:55:51.43#ibcon#read 4, iclass 12, count 0 2006.285.17:55:51.43#ibcon#about to read 5, iclass 12, count 0 2006.285.17:55:51.43#ibcon#read 5, iclass 12, count 0 2006.285.17:55:51.43#ibcon#about to read 6, iclass 12, count 0 2006.285.17:55:51.43#ibcon#read 6, iclass 12, count 0 2006.285.17:55:51.43#ibcon#end of sib2, iclass 12, count 0 2006.285.17:55:51.43#ibcon#*mode == 0, iclass 12, count 0 2006.285.17:55:51.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.17:55:51.43#ibcon#[25=USB\r\n] 2006.285.17:55:51.43#ibcon#*before write, iclass 12, count 0 2006.285.17:55:51.43#ibcon#enter sib2, iclass 12, count 0 2006.285.17:55:51.43#ibcon#flushed, iclass 12, count 0 2006.285.17:55:51.43#ibcon#about to write, iclass 12, count 0 2006.285.17:55:51.43#ibcon#wrote, iclass 12, count 0 2006.285.17:55:51.43#ibcon#about to read 3, iclass 12, count 0 2006.285.17:55:51.46#ibcon#read 3, iclass 12, count 0 2006.285.17:55:51.46#ibcon#about to read 4, iclass 12, count 0 2006.285.17:55:51.46#ibcon#read 4, iclass 12, count 0 2006.285.17:55:51.46#ibcon#about to read 5, iclass 12, count 0 2006.285.17:55:51.46#ibcon#read 5, iclass 12, count 0 2006.285.17:55:51.46#ibcon#about to read 6, iclass 12, count 0 2006.285.17:55:51.46#ibcon#read 6, iclass 12, count 0 2006.285.17:55:51.46#ibcon#end of sib2, iclass 12, count 0 2006.285.17:55:51.46#ibcon#*after write, iclass 12, count 0 2006.285.17:55:51.46#ibcon#*before return 0, iclass 12, count 0 2006.285.17:55:51.46#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:55:51.46#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:55:51.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.17:55:51.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.17:55:51.46$vck44/valo=8,884.99 2006.285.17:55:51.46#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.17:55:51.46#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.17:55:51.46#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:51.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:55:51.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:55:51.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:55:51.46#ibcon#enter wrdev, iclass 14, count 0 2006.285.17:55:51.46#ibcon#first serial, iclass 14, count 0 2006.285.17:55:51.46#ibcon#enter sib2, iclass 14, count 0 2006.285.17:55:51.46#ibcon#flushed, iclass 14, count 0 2006.285.17:55:51.46#ibcon#about to write, iclass 14, count 0 2006.285.17:55:51.46#ibcon#wrote, iclass 14, count 0 2006.285.17:55:51.46#ibcon#about to read 3, iclass 14, count 0 2006.285.17:55:51.48#ibcon#read 3, iclass 14, count 0 2006.285.17:55:51.48#ibcon#about to read 4, iclass 14, count 0 2006.285.17:55:51.48#ibcon#read 4, iclass 14, count 0 2006.285.17:55:51.48#ibcon#about to read 5, iclass 14, count 0 2006.285.17:55:51.48#ibcon#read 5, iclass 14, count 0 2006.285.17:55:51.48#ibcon#about to read 6, iclass 14, count 0 2006.285.17:55:51.48#ibcon#read 6, iclass 14, count 0 2006.285.17:55:51.48#ibcon#end of sib2, iclass 14, count 0 2006.285.17:55:51.48#ibcon#*mode == 0, iclass 14, count 0 2006.285.17:55:51.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.17:55:51.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.17:55:51.48#ibcon#*before write, iclass 14, count 0 2006.285.17:55:51.48#ibcon#enter sib2, iclass 14, count 0 2006.285.17:55:51.48#ibcon#flushed, iclass 14, count 0 2006.285.17:55:51.48#ibcon#about to write, iclass 14, count 0 2006.285.17:55:51.48#ibcon#wrote, iclass 14, count 0 2006.285.17:55:51.48#ibcon#about to read 3, iclass 14, count 0 2006.285.17:55:51.52#ibcon#read 3, iclass 14, count 0 2006.285.17:55:51.52#ibcon#about to read 4, iclass 14, count 0 2006.285.17:55:51.52#ibcon#read 4, iclass 14, count 0 2006.285.17:55:51.52#ibcon#about to read 5, iclass 14, count 0 2006.285.17:55:51.52#ibcon#read 5, iclass 14, count 0 2006.285.17:55:51.52#ibcon#about to read 6, iclass 14, count 0 2006.285.17:55:51.52#ibcon#read 6, iclass 14, count 0 2006.285.17:55:51.52#ibcon#end of sib2, iclass 14, count 0 2006.285.17:55:51.52#ibcon#*after write, iclass 14, count 0 2006.285.17:55:51.52#ibcon#*before return 0, iclass 14, count 0 2006.285.17:55:51.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:55:51.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:55:51.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.17:55:51.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.17:55:51.52$vck44/va=8,3 2006.285.17:55:51.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.17:55:51.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.17:55:51.52#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:51.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:55:51.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:55:51.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:55:51.58#ibcon#enter wrdev, iclass 16, count 2 2006.285.17:55:51.58#ibcon#first serial, iclass 16, count 2 2006.285.17:55:51.58#ibcon#enter sib2, iclass 16, count 2 2006.285.17:55:51.58#ibcon#flushed, iclass 16, count 2 2006.285.17:55:51.58#ibcon#about to write, iclass 16, count 2 2006.285.17:55:51.58#ibcon#wrote, iclass 16, count 2 2006.285.17:55:51.58#ibcon#about to read 3, iclass 16, count 2 2006.285.17:55:51.60#ibcon#read 3, iclass 16, count 2 2006.285.17:55:51.60#ibcon#about to read 4, iclass 16, count 2 2006.285.17:55:51.60#ibcon#read 4, iclass 16, count 2 2006.285.17:55:51.60#ibcon#about to read 5, iclass 16, count 2 2006.285.17:55:51.60#ibcon#read 5, iclass 16, count 2 2006.285.17:55:51.60#ibcon#about to read 6, iclass 16, count 2 2006.285.17:55:51.60#ibcon#read 6, iclass 16, count 2 2006.285.17:55:51.60#ibcon#end of sib2, iclass 16, count 2 2006.285.17:55:51.60#ibcon#*mode == 0, iclass 16, count 2 2006.285.17:55:51.60#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.17:55:51.60#ibcon#[25=AT08-03\r\n] 2006.285.17:55:51.60#ibcon#*before write, iclass 16, count 2 2006.285.17:55:51.60#ibcon#enter sib2, iclass 16, count 2 2006.285.17:55:51.60#ibcon#flushed, iclass 16, count 2 2006.285.17:55:51.60#ibcon#about to write, iclass 16, count 2 2006.285.17:55:51.60#ibcon#wrote, iclass 16, count 2 2006.285.17:55:51.60#ibcon#about to read 3, iclass 16, count 2 2006.285.17:55:51.63#ibcon#read 3, iclass 16, count 2 2006.285.17:55:51.63#ibcon#about to read 4, iclass 16, count 2 2006.285.17:55:51.63#ibcon#read 4, iclass 16, count 2 2006.285.17:55:51.63#ibcon#about to read 5, iclass 16, count 2 2006.285.17:55:51.63#ibcon#read 5, iclass 16, count 2 2006.285.17:55:51.63#ibcon#about to read 6, iclass 16, count 2 2006.285.17:55:51.63#ibcon#read 6, iclass 16, count 2 2006.285.17:55:51.63#ibcon#end of sib2, iclass 16, count 2 2006.285.17:55:51.63#ibcon#*after write, iclass 16, count 2 2006.285.17:55:51.63#ibcon#*before return 0, iclass 16, count 2 2006.285.17:55:51.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:55:51.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.17:55:51.63#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.17:55:51.63#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:51.63#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:55:51.75#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:55:51.75#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:55:51.75#ibcon#enter wrdev, iclass 16, count 0 2006.285.17:55:51.75#ibcon#first serial, iclass 16, count 0 2006.285.17:55:51.75#ibcon#enter sib2, iclass 16, count 0 2006.285.17:55:51.75#ibcon#flushed, iclass 16, count 0 2006.285.17:55:51.75#ibcon#about to write, iclass 16, count 0 2006.285.17:55:51.75#ibcon#wrote, iclass 16, count 0 2006.285.17:55:51.75#ibcon#about to read 3, iclass 16, count 0 2006.285.17:55:51.77#ibcon#read 3, iclass 16, count 0 2006.285.17:55:51.77#ibcon#about to read 4, iclass 16, count 0 2006.285.17:55:51.77#ibcon#read 4, iclass 16, count 0 2006.285.17:55:51.77#ibcon#about to read 5, iclass 16, count 0 2006.285.17:55:51.77#ibcon#read 5, iclass 16, count 0 2006.285.17:55:51.77#ibcon#about to read 6, iclass 16, count 0 2006.285.17:55:51.77#ibcon#read 6, iclass 16, count 0 2006.285.17:55:51.77#ibcon#end of sib2, iclass 16, count 0 2006.285.17:55:51.77#ibcon#*mode == 0, iclass 16, count 0 2006.285.17:55:51.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.17:55:51.77#ibcon#[25=USB\r\n] 2006.285.17:55:51.77#ibcon#*before write, iclass 16, count 0 2006.285.17:55:51.77#ibcon#enter sib2, iclass 16, count 0 2006.285.17:55:51.77#ibcon#flushed, iclass 16, count 0 2006.285.17:55:51.77#ibcon#about to write, iclass 16, count 0 2006.285.17:55:51.77#ibcon#wrote, iclass 16, count 0 2006.285.17:55:51.77#ibcon#about to read 3, iclass 16, count 0 2006.285.17:55:51.80#ibcon#read 3, iclass 16, count 0 2006.285.17:55:51.80#ibcon#about to read 4, iclass 16, count 0 2006.285.17:55:51.80#ibcon#read 4, iclass 16, count 0 2006.285.17:55:51.80#ibcon#about to read 5, iclass 16, count 0 2006.285.17:55:51.80#ibcon#read 5, iclass 16, count 0 2006.285.17:55:51.80#ibcon#about to read 6, iclass 16, count 0 2006.285.17:55:51.80#ibcon#read 6, iclass 16, count 0 2006.285.17:55:51.80#ibcon#end of sib2, iclass 16, count 0 2006.285.17:55:51.80#ibcon#*after write, iclass 16, count 0 2006.285.17:55:51.80#ibcon#*before return 0, iclass 16, count 0 2006.285.17:55:51.80#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:55:51.80#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.17:55:51.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.17:55:51.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.17:55:51.80$vck44/vblo=1,629.99 2006.285.17:55:51.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.17:55:51.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.17:55:51.80#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:51.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:55:51.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:55:51.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:55:51.80#ibcon#enter wrdev, iclass 18, count 0 2006.285.17:55:51.80#ibcon#first serial, iclass 18, count 0 2006.285.17:55:51.80#ibcon#enter sib2, iclass 18, count 0 2006.285.17:55:51.80#ibcon#flushed, iclass 18, count 0 2006.285.17:55:51.80#ibcon#about to write, iclass 18, count 0 2006.285.17:55:51.80#ibcon#wrote, iclass 18, count 0 2006.285.17:55:51.80#ibcon#about to read 3, iclass 18, count 0 2006.285.17:55:51.82#ibcon#read 3, iclass 18, count 0 2006.285.17:55:51.82#ibcon#about to read 4, iclass 18, count 0 2006.285.17:55:51.82#ibcon#read 4, iclass 18, count 0 2006.285.17:55:51.82#ibcon#about to read 5, iclass 18, count 0 2006.285.17:55:51.82#ibcon#read 5, iclass 18, count 0 2006.285.17:55:51.82#ibcon#about to read 6, iclass 18, count 0 2006.285.17:55:51.82#ibcon#read 6, iclass 18, count 0 2006.285.17:55:51.82#ibcon#end of sib2, iclass 18, count 0 2006.285.17:55:51.82#ibcon#*mode == 0, iclass 18, count 0 2006.285.17:55:51.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.17:55:51.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.17:55:51.82#ibcon#*before write, iclass 18, count 0 2006.285.17:55:51.82#ibcon#enter sib2, iclass 18, count 0 2006.285.17:55:51.82#ibcon#flushed, iclass 18, count 0 2006.285.17:55:51.82#ibcon#about to write, iclass 18, count 0 2006.285.17:55:51.82#ibcon#wrote, iclass 18, count 0 2006.285.17:55:51.82#ibcon#about to read 3, iclass 18, count 0 2006.285.17:55:51.86#ibcon#read 3, iclass 18, count 0 2006.285.17:55:51.86#ibcon#about to read 4, iclass 18, count 0 2006.285.17:55:51.86#ibcon#read 4, iclass 18, count 0 2006.285.17:55:51.86#ibcon#about to read 5, iclass 18, count 0 2006.285.17:55:51.86#ibcon#read 5, iclass 18, count 0 2006.285.17:55:51.86#ibcon#about to read 6, iclass 18, count 0 2006.285.17:55:51.86#ibcon#read 6, iclass 18, count 0 2006.285.17:55:51.86#ibcon#end of sib2, iclass 18, count 0 2006.285.17:55:51.86#ibcon#*after write, iclass 18, count 0 2006.285.17:55:51.86#ibcon#*before return 0, iclass 18, count 0 2006.285.17:55:51.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:55:51.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.17:55:51.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.17:55:51.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.17:55:51.86$vck44/vb=1,4 2006.285.17:55:51.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.17:55:51.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.17:55:51.86#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:51.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:55:51.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:55:51.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:55:51.86#ibcon#enter wrdev, iclass 20, count 2 2006.285.17:55:51.86#ibcon#first serial, iclass 20, count 2 2006.285.17:55:51.86#ibcon#enter sib2, iclass 20, count 2 2006.285.17:55:51.86#ibcon#flushed, iclass 20, count 2 2006.285.17:55:51.86#ibcon#about to write, iclass 20, count 2 2006.285.17:55:51.86#ibcon#wrote, iclass 20, count 2 2006.285.17:55:51.86#ibcon#about to read 3, iclass 20, count 2 2006.285.17:55:51.88#ibcon#read 3, iclass 20, count 2 2006.285.17:55:51.88#ibcon#about to read 4, iclass 20, count 2 2006.285.17:55:51.88#ibcon#read 4, iclass 20, count 2 2006.285.17:55:51.88#ibcon#about to read 5, iclass 20, count 2 2006.285.17:55:51.88#ibcon#read 5, iclass 20, count 2 2006.285.17:55:51.88#ibcon#about to read 6, iclass 20, count 2 2006.285.17:55:51.88#ibcon#read 6, iclass 20, count 2 2006.285.17:55:51.88#ibcon#end of sib2, iclass 20, count 2 2006.285.17:55:51.88#ibcon#*mode == 0, iclass 20, count 2 2006.285.17:55:51.88#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.17:55:51.88#ibcon#[27=AT01-04\r\n] 2006.285.17:55:51.88#ibcon#*before write, iclass 20, count 2 2006.285.17:55:51.88#ibcon#enter sib2, iclass 20, count 2 2006.285.17:55:51.88#ibcon#flushed, iclass 20, count 2 2006.285.17:55:51.88#ibcon#about to write, iclass 20, count 2 2006.285.17:55:51.88#ibcon#wrote, iclass 20, count 2 2006.285.17:55:51.88#ibcon#about to read 3, iclass 20, count 2 2006.285.17:55:51.91#ibcon#read 3, iclass 20, count 2 2006.285.17:55:51.91#ibcon#about to read 4, iclass 20, count 2 2006.285.17:55:51.91#ibcon#read 4, iclass 20, count 2 2006.285.17:55:51.91#ibcon#about to read 5, iclass 20, count 2 2006.285.17:55:51.91#ibcon#read 5, iclass 20, count 2 2006.285.17:55:51.91#ibcon#about to read 6, iclass 20, count 2 2006.285.17:55:51.91#ibcon#read 6, iclass 20, count 2 2006.285.17:55:51.91#ibcon#end of sib2, iclass 20, count 2 2006.285.17:55:51.91#ibcon#*after write, iclass 20, count 2 2006.285.17:55:51.91#ibcon#*before return 0, iclass 20, count 2 2006.285.17:55:51.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:55:51.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.17:55:51.91#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.17:55:51.91#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:51.91#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:55:52.03#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:55:52.03#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:55:52.03#ibcon#enter wrdev, iclass 20, count 0 2006.285.17:55:52.03#ibcon#first serial, iclass 20, count 0 2006.285.17:55:52.03#ibcon#enter sib2, iclass 20, count 0 2006.285.17:55:52.03#ibcon#flushed, iclass 20, count 0 2006.285.17:55:52.03#ibcon#about to write, iclass 20, count 0 2006.285.17:55:52.03#ibcon#wrote, iclass 20, count 0 2006.285.17:55:52.03#ibcon#about to read 3, iclass 20, count 0 2006.285.17:55:52.05#ibcon#read 3, iclass 20, count 0 2006.285.17:55:52.05#ibcon#about to read 4, iclass 20, count 0 2006.285.17:55:52.05#ibcon#read 4, iclass 20, count 0 2006.285.17:55:52.05#ibcon#about to read 5, iclass 20, count 0 2006.285.17:55:52.05#ibcon#read 5, iclass 20, count 0 2006.285.17:55:52.05#ibcon#about to read 6, iclass 20, count 0 2006.285.17:55:52.05#ibcon#read 6, iclass 20, count 0 2006.285.17:55:52.05#ibcon#end of sib2, iclass 20, count 0 2006.285.17:55:52.05#ibcon#*mode == 0, iclass 20, count 0 2006.285.17:55:52.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.17:55:52.05#ibcon#[27=USB\r\n] 2006.285.17:55:52.05#ibcon#*before write, iclass 20, count 0 2006.285.17:55:52.05#ibcon#enter sib2, iclass 20, count 0 2006.285.17:55:52.05#ibcon#flushed, iclass 20, count 0 2006.285.17:55:52.05#ibcon#about to write, iclass 20, count 0 2006.285.17:55:52.05#ibcon#wrote, iclass 20, count 0 2006.285.17:55:52.05#ibcon#about to read 3, iclass 20, count 0 2006.285.17:55:52.08#ibcon#read 3, iclass 20, count 0 2006.285.17:55:52.08#ibcon#about to read 4, iclass 20, count 0 2006.285.17:55:52.08#ibcon#read 4, iclass 20, count 0 2006.285.17:55:52.08#ibcon#about to read 5, iclass 20, count 0 2006.285.17:55:52.08#ibcon#read 5, iclass 20, count 0 2006.285.17:55:52.08#ibcon#about to read 6, iclass 20, count 0 2006.285.17:55:52.08#ibcon#read 6, iclass 20, count 0 2006.285.17:55:52.08#ibcon#end of sib2, iclass 20, count 0 2006.285.17:55:52.08#ibcon#*after write, iclass 20, count 0 2006.285.17:55:52.08#ibcon#*before return 0, iclass 20, count 0 2006.285.17:55:52.08#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:55:52.08#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.17:55:52.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.17:55:52.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.17:55:52.08$vck44/vblo=2,634.99 2006.285.17:55:52.08#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.17:55:52.08#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.17:55:52.08#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:52.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:55:52.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:55:52.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:55:52.08#ibcon#enter wrdev, iclass 22, count 0 2006.285.17:55:52.08#ibcon#first serial, iclass 22, count 0 2006.285.17:55:52.08#ibcon#enter sib2, iclass 22, count 0 2006.285.17:55:52.08#ibcon#flushed, iclass 22, count 0 2006.285.17:55:52.08#ibcon#about to write, iclass 22, count 0 2006.285.17:55:52.08#ibcon#wrote, iclass 22, count 0 2006.285.17:55:52.08#ibcon#about to read 3, iclass 22, count 0 2006.285.17:55:52.10#ibcon#read 3, iclass 22, count 0 2006.285.17:55:52.10#ibcon#about to read 4, iclass 22, count 0 2006.285.17:55:52.10#ibcon#read 4, iclass 22, count 0 2006.285.17:55:52.10#ibcon#about to read 5, iclass 22, count 0 2006.285.17:55:52.10#ibcon#read 5, iclass 22, count 0 2006.285.17:55:52.10#ibcon#about to read 6, iclass 22, count 0 2006.285.17:55:52.10#ibcon#read 6, iclass 22, count 0 2006.285.17:55:52.10#ibcon#end of sib2, iclass 22, count 0 2006.285.17:55:52.10#ibcon#*mode == 0, iclass 22, count 0 2006.285.17:55:52.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.17:55:52.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.17:55:52.10#ibcon#*before write, iclass 22, count 0 2006.285.17:55:52.10#ibcon#enter sib2, iclass 22, count 0 2006.285.17:55:52.10#ibcon#flushed, iclass 22, count 0 2006.285.17:55:52.10#ibcon#about to write, iclass 22, count 0 2006.285.17:55:52.10#ibcon#wrote, iclass 22, count 0 2006.285.17:55:52.10#ibcon#about to read 3, iclass 22, count 0 2006.285.17:55:52.14#ibcon#read 3, iclass 22, count 0 2006.285.17:55:52.14#ibcon#about to read 4, iclass 22, count 0 2006.285.17:55:52.14#ibcon#read 4, iclass 22, count 0 2006.285.17:55:52.14#ibcon#about to read 5, iclass 22, count 0 2006.285.17:55:52.14#ibcon#read 5, iclass 22, count 0 2006.285.17:55:52.14#ibcon#about to read 6, iclass 22, count 0 2006.285.17:55:52.14#ibcon#read 6, iclass 22, count 0 2006.285.17:55:52.14#ibcon#end of sib2, iclass 22, count 0 2006.285.17:55:52.14#ibcon#*after write, iclass 22, count 0 2006.285.17:55:52.14#ibcon#*before return 0, iclass 22, count 0 2006.285.17:55:52.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:55:52.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.17:55:52.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.17:55:52.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.17:55:52.14$vck44/vb=2,5 2006.285.17:55:52.14#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.17:55:52.14#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.17:55:52.14#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:52.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:55:52.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:55:52.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:55:52.20#ibcon#enter wrdev, iclass 24, count 2 2006.285.17:55:52.20#ibcon#first serial, iclass 24, count 2 2006.285.17:55:52.20#ibcon#enter sib2, iclass 24, count 2 2006.285.17:55:52.20#ibcon#flushed, iclass 24, count 2 2006.285.17:55:52.20#ibcon#about to write, iclass 24, count 2 2006.285.17:55:52.20#ibcon#wrote, iclass 24, count 2 2006.285.17:55:52.20#ibcon#about to read 3, iclass 24, count 2 2006.285.17:55:52.22#ibcon#read 3, iclass 24, count 2 2006.285.17:55:52.22#ibcon#about to read 4, iclass 24, count 2 2006.285.17:55:52.22#ibcon#read 4, iclass 24, count 2 2006.285.17:55:52.22#ibcon#about to read 5, iclass 24, count 2 2006.285.17:55:52.22#ibcon#read 5, iclass 24, count 2 2006.285.17:55:52.22#ibcon#about to read 6, iclass 24, count 2 2006.285.17:55:52.22#ibcon#read 6, iclass 24, count 2 2006.285.17:55:52.22#ibcon#end of sib2, iclass 24, count 2 2006.285.17:55:52.22#ibcon#*mode == 0, iclass 24, count 2 2006.285.17:55:52.22#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.17:55:52.22#ibcon#[27=AT02-05\r\n] 2006.285.17:55:52.22#ibcon#*before write, iclass 24, count 2 2006.285.17:55:52.22#ibcon#enter sib2, iclass 24, count 2 2006.285.17:55:52.22#ibcon#flushed, iclass 24, count 2 2006.285.17:55:52.22#ibcon#about to write, iclass 24, count 2 2006.285.17:55:52.22#ibcon#wrote, iclass 24, count 2 2006.285.17:55:52.22#ibcon#about to read 3, iclass 24, count 2 2006.285.17:55:52.25#ibcon#read 3, iclass 24, count 2 2006.285.17:55:52.25#ibcon#about to read 4, iclass 24, count 2 2006.285.17:55:52.25#ibcon#read 4, iclass 24, count 2 2006.285.17:55:52.25#ibcon#about to read 5, iclass 24, count 2 2006.285.17:55:52.25#ibcon#read 5, iclass 24, count 2 2006.285.17:55:52.25#ibcon#about to read 6, iclass 24, count 2 2006.285.17:55:52.25#ibcon#read 6, iclass 24, count 2 2006.285.17:55:52.25#ibcon#end of sib2, iclass 24, count 2 2006.285.17:55:52.25#ibcon#*after write, iclass 24, count 2 2006.285.17:55:52.25#ibcon#*before return 0, iclass 24, count 2 2006.285.17:55:52.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:55:52.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.17:55:52.25#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.17:55:52.25#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:52.25#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:55:52.37#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:55:52.47#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:55:52.47#ibcon#enter wrdev, iclass 24, count 0 2006.285.17:55:52.47#ibcon#first serial, iclass 24, count 0 2006.285.17:55:52.47#ibcon#enter sib2, iclass 24, count 0 2006.285.17:55:52.47#ibcon#flushed, iclass 24, count 0 2006.285.17:55:52.47#ibcon#about to write, iclass 24, count 0 2006.285.17:55:52.47#ibcon#wrote, iclass 24, count 0 2006.285.17:55:52.47#ibcon#about to read 3, iclass 24, count 0 2006.285.17:55:52.48#ibcon#read 3, iclass 24, count 0 2006.285.17:55:52.48#ibcon#about to read 4, iclass 24, count 0 2006.285.17:55:52.48#ibcon#read 4, iclass 24, count 0 2006.285.17:55:52.48#ibcon#about to read 5, iclass 24, count 0 2006.285.17:55:52.48#ibcon#read 5, iclass 24, count 0 2006.285.17:55:52.48#ibcon#about to read 6, iclass 24, count 0 2006.285.17:55:52.48#ibcon#read 6, iclass 24, count 0 2006.285.17:55:52.48#ibcon#end of sib2, iclass 24, count 0 2006.285.17:55:52.48#ibcon#*mode == 0, iclass 24, count 0 2006.285.17:55:52.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.17:55:52.48#ibcon#[27=USB\r\n] 2006.285.17:55:52.48#ibcon#*before write, iclass 24, count 0 2006.285.17:55:52.48#ibcon#enter sib2, iclass 24, count 0 2006.285.17:55:52.48#ibcon#flushed, iclass 24, count 0 2006.285.17:55:52.48#ibcon#about to write, iclass 24, count 0 2006.285.17:55:52.48#ibcon#wrote, iclass 24, count 0 2006.285.17:55:52.48#ibcon#about to read 3, iclass 24, count 0 2006.285.17:55:52.51#ibcon#read 3, iclass 24, count 0 2006.285.17:55:52.51#ibcon#about to read 4, iclass 24, count 0 2006.285.17:55:52.51#ibcon#read 4, iclass 24, count 0 2006.285.17:55:52.51#ibcon#about to read 5, iclass 24, count 0 2006.285.17:55:52.51#ibcon#read 5, iclass 24, count 0 2006.285.17:55:52.51#ibcon#about to read 6, iclass 24, count 0 2006.285.17:55:52.51#ibcon#read 6, iclass 24, count 0 2006.285.17:55:52.51#ibcon#end of sib2, iclass 24, count 0 2006.285.17:55:52.51#ibcon#*after write, iclass 24, count 0 2006.285.17:55:52.51#ibcon#*before return 0, iclass 24, count 0 2006.285.17:55:52.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:55:52.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.17:55:52.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.17:55:52.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.17:55:52.51$vck44/vblo=3,649.99 2006.285.17:55:52.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.17:55:52.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.17:55:52.51#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:52.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:55:52.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:55:52.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:55:52.51#ibcon#enter wrdev, iclass 26, count 0 2006.285.17:55:52.51#ibcon#first serial, iclass 26, count 0 2006.285.17:55:52.51#ibcon#enter sib2, iclass 26, count 0 2006.285.17:55:52.51#ibcon#flushed, iclass 26, count 0 2006.285.17:55:52.51#ibcon#about to write, iclass 26, count 0 2006.285.17:55:52.51#ibcon#wrote, iclass 26, count 0 2006.285.17:55:52.51#ibcon#about to read 3, iclass 26, count 0 2006.285.17:55:52.53#ibcon#read 3, iclass 26, count 0 2006.285.17:55:52.53#ibcon#about to read 4, iclass 26, count 0 2006.285.17:55:52.53#ibcon#read 4, iclass 26, count 0 2006.285.17:55:52.53#ibcon#about to read 5, iclass 26, count 0 2006.285.17:55:52.53#ibcon#read 5, iclass 26, count 0 2006.285.17:55:52.53#ibcon#about to read 6, iclass 26, count 0 2006.285.17:55:52.53#ibcon#read 6, iclass 26, count 0 2006.285.17:55:52.53#ibcon#end of sib2, iclass 26, count 0 2006.285.17:55:52.53#ibcon#*mode == 0, iclass 26, count 0 2006.285.17:55:52.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.17:55:52.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.17:55:52.53#ibcon#*before write, iclass 26, count 0 2006.285.17:55:52.53#ibcon#enter sib2, iclass 26, count 0 2006.285.17:55:52.53#ibcon#flushed, iclass 26, count 0 2006.285.17:55:52.53#ibcon#about to write, iclass 26, count 0 2006.285.17:55:52.53#ibcon#wrote, iclass 26, count 0 2006.285.17:55:52.53#ibcon#about to read 3, iclass 26, count 0 2006.285.17:55:52.57#ibcon#read 3, iclass 26, count 0 2006.285.17:55:52.57#ibcon#about to read 4, iclass 26, count 0 2006.285.17:55:52.57#ibcon#read 4, iclass 26, count 0 2006.285.17:55:52.57#ibcon#about to read 5, iclass 26, count 0 2006.285.17:55:52.57#ibcon#read 5, iclass 26, count 0 2006.285.17:55:52.57#ibcon#about to read 6, iclass 26, count 0 2006.285.17:55:52.57#ibcon#read 6, iclass 26, count 0 2006.285.17:55:52.57#ibcon#end of sib2, iclass 26, count 0 2006.285.17:55:52.57#ibcon#*after write, iclass 26, count 0 2006.285.17:55:52.57#ibcon#*before return 0, iclass 26, count 0 2006.285.17:55:52.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:55:52.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.17:55:52.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.17:55:52.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.17:55:52.57$vck44/vb=3,4 2006.285.17:55:52.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.17:55:52.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.17:55:52.57#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:52.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:55:52.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:55:52.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:55:52.63#ibcon#enter wrdev, iclass 28, count 2 2006.285.17:55:52.63#ibcon#first serial, iclass 28, count 2 2006.285.17:55:52.63#ibcon#enter sib2, iclass 28, count 2 2006.285.17:55:52.63#ibcon#flushed, iclass 28, count 2 2006.285.17:55:52.63#ibcon#about to write, iclass 28, count 2 2006.285.17:55:52.63#ibcon#wrote, iclass 28, count 2 2006.285.17:55:52.63#ibcon#about to read 3, iclass 28, count 2 2006.285.17:55:52.65#ibcon#read 3, iclass 28, count 2 2006.285.17:55:52.65#ibcon#about to read 4, iclass 28, count 2 2006.285.17:55:52.65#ibcon#read 4, iclass 28, count 2 2006.285.17:55:52.65#ibcon#about to read 5, iclass 28, count 2 2006.285.17:55:52.65#ibcon#read 5, iclass 28, count 2 2006.285.17:55:52.65#ibcon#about to read 6, iclass 28, count 2 2006.285.17:55:52.65#ibcon#read 6, iclass 28, count 2 2006.285.17:55:52.65#ibcon#end of sib2, iclass 28, count 2 2006.285.17:55:52.65#ibcon#*mode == 0, iclass 28, count 2 2006.285.17:55:52.65#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.17:55:52.65#ibcon#[27=AT03-04\r\n] 2006.285.17:55:52.65#ibcon#*before write, iclass 28, count 2 2006.285.17:55:52.65#ibcon#enter sib2, iclass 28, count 2 2006.285.17:55:52.65#ibcon#flushed, iclass 28, count 2 2006.285.17:55:52.65#ibcon#about to write, iclass 28, count 2 2006.285.17:55:52.65#ibcon#wrote, iclass 28, count 2 2006.285.17:55:52.65#ibcon#about to read 3, iclass 28, count 2 2006.285.17:55:52.68#ibcon#read 3, iclass 28, count 2 2006.285.17:55:52.68#ibcon#about to read 4, iclass 28, count 2 2006.285.17:55:52.68#ibcon#read 4, iclass 28, count 2 2006.285.17:55:52.68#ibcon#about to read 5, iclass 28, count 2 2006.285.17:55:52.68#ibcon#read 5, iclass 28, count 2 2006.285.17:55:52.68#ibcon#about to read 6, iclass 28, count 2 2006.285.17:55:52.68#ibcon#read 6, iclass 28, count 2 2006.285.17:55:52.68#ibcon#end of sib2, iclass 28, count 2 2006.285.17:55:52.68#ibcon#*after write, iclass 28, count 2 2006.285.17:55:52.68#ibcon#*before return 0, iclass 28, count 2 2006.285.17:55:52.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:55:52.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.17:55:52.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.17:55:52.68#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:52.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:55:52.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:55:52.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:55:52.80#ibcon#enter wrdev, iclass 28, count 0 2006.285.17:55:52.80#ibcon#first serial, iclass 28, count 0 2006.285.17:55:52.80#ibcon#enter sib2, iclass 28, count 0 2006.285.17:55:52.80#ibcon#flushed, iclass 28, count 0 2006.285.17:55:52.80#ibcon#about to write, iclass 28, count 0 2006.285.17:55:52.80#ibcon#wrote, iclass 28, count 0 2006.285.17:55:52.80#ibcon#about to read 3, iclass 28, count 0 2006.285.17:55:52.82#ibcon#read 3, iclass 28, count 0 2006.285.17:55:52.82#ibcon#about to read 4, iclass 28, count 0 2006.285.17:55:52.82#ibcon#read 4, iclass 28, count 0 2006.285.17:55:52.82#ibcon#about to read 5, iclass 28, count 0 2006.285.17:55:52.82#ibcon#read 5, iclass 28, count 0 2006.285.17:55:52.82#ibcon#about to read 6, iclass 28, count 0 2006.285.17:55:52.82#ibcon#read 6, iclass 28, count 0 2006.285.17:55:52.82#ibcon#end of sib2, iclass 28, count 0 2006.285.17:55:52.82#ibcon#*mode == 0, iclass 28, count 0 2006.285.17:55:52.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.17:55:52.82#ibcon#[27=USB\r\n] 2006.285.17:55:52.82#ibcon#*before write, iclass 28, count 0 2006.285.17:55:52.82#ibcon#enter sib2, iclass 28, count 0 2006.285.17:55:52.82#ibcon#flushed, iclass 28, count 0 2006.285.17:55:52.82#ibcon#about to write, iclass 28, count 0 2006.285.17:55:52.82#ibcon#wrote, iclass 28, count 0 2006.285.17:55:52.82#ibcon#about to read 3, iclass 28, count 0 2006.285.17:55:52.85#ibcon#read 3, iclass 28, count 0 2006.285.17:55:52.85#ibcon#about to read 4, iclass 28, count 0 2006.285.17:55:52.85#ibcon#read 4, iclass 28, count 0 2006.285.17:55:52.85#ibcon#about to read 5, iclass 28, count 0 2006.285.17:55:52.85#ibcon#read 5, iclass 28, count 0 2006.285.17:55:52.85#ibcon#about to read 6, iclass 28, count 0 2006.285.17:55:52.85#ibcon#read 6, iclass 28, count 0 2006.285.17:55:52.85#ibcon#end of sib2, iclass 28, count 0 2006.285.17:55:52.85#ibcon#*after write, iclass 28, count 0 2006.285.17:55:52.85#ibcon#*before return 0, iclass 28, count 0 2006.285.17:55:52.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:55:52.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.17:55:52.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.17:55:52.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.17:55:52.85$vck44/vblo=4,679.99 2006.285.17:55:52.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.17:55:52.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.17:55:52.85#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:52.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:55:52.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:55:52.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:55:52.85#ibcon#enter wrdev, iclass 30, count 0 2006.285.17:55:52.85#ibcon#first serial, iclass 30, count 0 2006.285.17:55:52.85#ibcon#enter sib2, iclass 30, count 0 2006.285.17:55:52.85#ibcon#flushed, iclass 30, count 0 2006.285.17:55:52.85#ibcon#about to write, iclass 30, count 0 2006.285.17:55:52.85#ibcon#wrote, iclass 30, count 0 2006.285.17:55:52.85#ibcon#about to read 3, iclass 30, count 0 2006.285.17:55:52.87#ibcon#read 3, iclass 30, count 0 2006.285.17:55:52.87#ibcon#about to read 4, iclass 30, count 0 2006.285.17:55:52.87#ibcon#read 4, iclass 30, count 0 2006.285.17:55:52.87#ibcon#about to read 5, iclass 30, count 0 2006.285.17:55:52.87#ibcon#read 5, iclass 30, count 0 2006.285.17:55:52.87#ibcon#about to read 6, iclass 30, count 0 2006.285.17:55:52.87#ibcon#read 6, iclass 30, count 0 2006.285.17:55:52.87#ibcon#end of sib2, iclass 30, count 0 2006.285.17:55:52.87#ibcon#*mode == 0, iclass 30, count 0 2006.285.17:55:52.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.17:55:52.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.17:55:52.87#ibcon#*before write, iclass 30, count 0 2006.285.17:55:52.87#ibcon#enter sib2, iclass 30, count 0 2006.285.17:55:52.87#ibcon#flushed, iclass 30, count 0 2006.285.17:55:52.87#ibcon#about to write, iclass 30, count 0 2006.285.17:55:52.87#ibcon#wrote, iclass 30, count 0 2006.285.17:55:52.87#ibcon#about to read 3, iclass 30, count 0 2006.285.17:55:52.91#ibcon#read 3, iclass 30, count 0 2006.285.17:55:52.91#ibcon#about to read 4, iclass 30, count 0 2006.285.17:55:52.91#ibcon#read 4, iclass 30, count 0 2006.285.17:55:52.91#ibcon#about to read 5, iclass 30, count 0 2006.285.17:55:52.91#ibcon#read 5, iclass 30, count 0 2006.285.17:55:52.91#ibcon#about to read 6, iclass 30, count 0 2006.285.17:55:52.91#ibcon#read 6, iclass 30, count 0 2006.285.17:55:52.91#ibcon#end of sib2, iclass 30, count 0 2006.285.17:55:52.91#ibcon#*after write, iclass 30, count 0 2006.285.17:55:52.91#ibcon#*before return 0, iclass 30, count 0 2006.285.17:55:52.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:55:52.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.17:55:52.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.17:55:52.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.17:55:52.91$vck44/vb=4,5 2006.285.17:55:52.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.17:55:52.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.17:55:52.91#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:52.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:55:52.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:55:52.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:55:52.97#ibcon#enter wrdev, iclass 32, count 2 2006.285.17:55:52.97#ibcon#first serial, iclass 32, count 2 2006.285.17:55:52.97#ibcon#enter sib2, iclass 32, count 2 2006.285.17:55:52.97#ibcon#flushed, iclass 32, count 2 2006.285.17:55:52.97#ibcon#about to write, iclass 32, count 2 2006.285.17:55:52.97#ibcon#wrote, iclass 32, count 2 2006.285.17:55:52.97#ibcon#about to read 3, iclass 32, count 2 2006.285.17:55:52.99#ibcon#read 3, iclass 32, count 2 2006.285.17:55:52.99#ibcon#about to read 4, iclass 32, count 2 2006.285.17:55:52.99#ibcon#read 4, iclass 32, count 2 2006.285.17:55:52.99#ibcon#about to read 5, iclass 32, count 2 2006.285.17:55:52.99#ibcon#read 5, iclass 32, count 2 2006.285.17:55:52.99#ibcon#about to read 6, iclass 32, count 2 2006.285.17:55:52.99#ibcon#read 6, iclass 32, count 2 2006.285.17:55:52.99#ibcon#end of sib2, iclass 32, count 2 2006.285.17:55:52.99#ibcon#*mode == 0, iclass 32, count 2 2006.285.17:55:52.99#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.17:55:52.99#ibcon#[27=AT04-05\r\n] 2006.285.17:55:52.99#ibcon#*before write, iclass 32, count 2 2006.285.17:55:52.99#ibcon#enter sib2, iclass 32, count 2 2006.285.17:55:52.99#ibcon#flushed, iclass 32, count 2 2006.285.17:55:52.99#ibcon#about to write, iclass 32, count 2 2006.285.17:55:52.99#ibcon#wrote, iclass 32, count 2 2006.285.17:55:52.99#ibcon#about to read 3, iclass 32, count 2 2006.285.17:55:53.02#ibcon#read 3, iclass 32, count 2 2006.285.17:55:53.02#ibcon#about to read 4, iclass 32, count 2 2006.285.17:55:53.02#ibcon#read 4, iclass 32, count 2 2006.285.17:55:53.02#ibcon#about to read 5, iclass 32, count 2 2006.285.17:55:53.02#ibcon#read 5, iclass 32, count 2 2006.285.17:55:53.02#ibcon#about to read 6, iclass 32, count 2 2006.285.17:55:53.02#ibcon#read 6, iclass 32, count 2 2006.285.17:55:53.02#ibcon#end of sib2, iclass 32, count 2 2006.285.17:55:53.02#ibcon#*after write, iclass 32, count 2 2006.285.17:55:53.02#ibcon#*before return 0, iclass 32, count 2 2006.285.17:55:53.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:55:53.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.17:55:53.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.17:55:53.02#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:53.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:55:53.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:55:53.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:55:53.14#ibcon#enter wrdev, iclass 32, count 0 2006.285.17:55:53.14#ibcon#first serial, iclass 32, count 0 2006.285.17:55:53.14#ibcon#enter sib2, iclass 32, count 0 2006.285.17:55:53.14#ibcon#flushed, iclass 32, count 0 2006.285.17:55:53.14#ibcon#about to write, iclass 32, count 0 2006.285.17:55:53.14#ibcon#wrote, iclass 32, count 0 2006.285.17:55:53.14#ibcon#about to read 3, iclass 32, count 0 2006.285.17:55:53.16#ibcon#read 3, iclass 32, count 0 2006.285.17:55:53.16#ibcon#about to read 4, iclass 32, count 0 2006.285.17:55:53.16#ibcon#read 4, iclass 32, count 0 2006.285.17:55:53.16#ibcon#about to read 5, iclass 32, count 0 2006.285.17:55:53.16#ibcon#read 5, iclass 32, count 0 2006.285.17:55:53.16#ibcon#about to read 6, iclass 32, count 0 2006.285.17:55:53.16#ibcon#read 6, iclass 32, count 0 2006.285.17:55:53.16#ibcon#end of sib2, iclass 32, count 0 2006.285.17:55:53.16#ibcon#*mode == 0, iclass 32, count 0 2006.285.17:55:53.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.17:55:53.16#ibcon#[27=USB\r\n] 2006.285.17:55:53.16#ibcon#*before write, iclass 32, count 0 2006.285.17:55:53.16#ibcon#enter sib2, iclass 32, count 0 2006.285.17:55:53.16#ibcon#flushed, iclass 32, count 0 2006.285.17:55:53.16#ibcon#about to write, iclass 32, count 0 2006.285.17:55:53.16#ibcon#wrote, iclass 32, count 0 2006.285.17:55:53.16#ibcon#about to read 3, iclass 32, count 0 2006.285.17:55:53.19#ibcon#read 3, iclass 32, count 0 2006.285.17:55:53.19#ibcon#about to read 4, iclass 32, count 0 2006.285.17:55:53.19#ibcon#read 4, iclass 32, count 0 2006.285.17:55:53.19#ibcon#about to read 5, iclass 32, count 0 2006.285.17:55:53.19#ibcon#read 5, iclass 32, count 0 2006.285.17:55:53.19#ibcon#about to read 6, iclass 32, count 0 2006.285.17:55:53.19#ibcon#read 6, iclass 32, count 0 2006.285.17:55:53.19#ibcon#end of sib2, iclass 32, count 0 2006.285.17:55:53.19#ibcon#*after write, iclass 32, count 0 2006.285.17:55:53.19#ibcon#*before return 0, iclass 32, count 0 2006.285.17:55:53.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:55:53.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.17:55:53.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.17:55:53.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.17:55:53.19$vck44/vblo=5,709.99 2006.285.17:55:53.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.17:55:53.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.17:55:53.19#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:53.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:55:53.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:55:53.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:55:53.19#ibcon#enter wrdev, iclass 34, count 0 2006.285.17:55:53.19#ibcon#first serial, iclass 34, count 0 2006.285.17:55:53.19#ibcon#enter sib2, iclass 34, count 0 2006.285.17:55:53.19#ibcon#flushed, iclass 34, count 0 2006.285.17:55:53.19#ibcon#about to write, iclass 34, count 0 2006.285.17:55:53.19#ibcon#wrote, iclass 34, count 0 2006.285.17:55:53.19#ibcon#about to read 3, iclass 34, count 0 2006.285.17:55:53.21#ibcon#read 3, iclass 34, count 0 2006.285.17:55:53.21#ibcon#about to read 4, iclass 34, count 0 2006.285.17:55:53.21#ibcon#read 4, iclass 34, count 0 2006.285.17:55:53.54#ibcon#about to read 5, iclass 34, count 0 2006.285.17:55:53.54#ibcon#read 5, iclass 34, count 0 2006.285.17:55:53.54#ibcon#about to read 6, iclass 34, count 0 2006.285.17:55:53.54#ibcon#read 6, iclass 34, count 0 2006.285.17:55:53.54#ibcon#end of sib2, iclass 34, count 0 2006.285.17:55:53.54#ibcon#*mode == 0, iclass 34, count 0 2006.285.17:55:53.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.17:55:53.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.17:55:53.54#ibcon#*before write, iclass 34, count 0 2006.285.17:55:53.54#ibcon#enter sib2, iclass 34, count 0 2006.285.17:55:53.54#ibcon#flushed, iclass 34, count 0 2006.285.17:55:53.54#ibcon#about to write, iclass 34, count 0 2006.285.17:55:53.54#ibcon#wrote, iclass 34, count 0 2006.285.17:55:53.54#ibcon#about to read 3, iclass 34, count 0 2006.285.17:55:53.58#ibcon#read 3, iclass 34, count 0 2006.285.17:55:53.58#ibcon#about to read 4, iclass 34, count 0 2006.285.17:55:53.58#ibcon#read 4, iclass 34, count 0 2006.285.17:55:53.58#ibcon#about to read 5, iclass 34, count 0 2006.285.17:55:53.58#ibcon#read 5, iclass 34, count 0 2006.285.17:55:53.58#ibcon#about to read 6, iclass 34, count 0 2006.285.17:55:53.58#ibcon#read 6, iclass 34, count 0 2006.285.17:55:53.58#ibcon#end of sib2, iclass 34, count 0 2006.285.17:55:53.58#ibcon#*after write, iclass 34, count 0 2006.285.17:55:53.58#ibcon#*before return 0, iclass 34, count 0 2006.285.17:55:53.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:55:53.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.17:55:53.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.17:55:53.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.17:55:53.58$vck44/vb=5,4 2006.285.17:55:53.58#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.17:55:53.58#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.17:55:53.58#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:53.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:55:53.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:55:53.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:55:53.58#ibcon#enter wrdev, iclass 36, count 2 2006.285.17:55:53.58#ibcon#first serial, iclass 36, count 2 2006.285.17:55:53.58#ibcon#enter sib2, iclass 36, count 2 2006.285.17:55:53.58#ibcon#flushed, iclass 36, count 2 2006.285.17:55:53.58#ibcon#about to write, iclass 36, count 2 2006.285.17:55:53.58#ibcon#wrote, iclass 36, count 2 2006.285.17:55:53.58#ibcon#about to read 3, iclass 36, count 2 2006.285.17:55:53.60#ibcon#read 3, iclass 36, count 2 2006.285.17:55:53.60#ibcon#about to read 4, iclass 36, count 2 2006.285.17:55:53.60#ibcon#read 4, iclass 36, count 2 2006.285.17:55:53.60#ibcon#about to read 5, iclass 36, count 2 2006.285.17:55:53.60#ibcon#read 5, iclass 36, count 2 2006.285.17:55:53.60#ibcon#about to read 6, iclass 36, count 2 2006.285.17:55:53.60#ibcon#read 6, iclass 36, count 2 2006.285.17:55:53.60#ibcon#end of sib2, iclass 36, count 2 2006.285.17:55:53.60#ibcon#*mode == 0, iclass 36, count 2 2006.285.17:55:53.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.17:55:53.60#ibcon#[27=AT05-04\r\n] 2006.285.17:55:53.60#ibcon#*before write, iclass 36, count 2 2006.285.17:55:53.60#ibcon#enter sib2, iclass 36, count 2 2006.285.17:55:53.60#ibcon#flushed, iclass 36, count 2 2006.285.17:55:53.60#ibcon#about to write, iclass 36, count 2 2006.285.17:55:53.60#ibcon#wrote, iclass 36, count 2 2006.285.17:55:53.60#ibcon#about to read 3, iclass 36, count 2 2006.285.17:55:53.63#ibcon#read 3, iclass 36, count 2 2006.285.17:55:53.63#ibcon#about to read 4, iclass 36, count 2 2006.285.17:55:53.63#ibcon#read 4, iclass 36, count 2 2006.285.17:55:53.63#ibcon#about to read 5, iclass 36, count 2 2006.285.17:55:53.63#ibcon#read 5, iclass 36, count 2 2006.285.17:55:53.63#ibcon#about to read 6, iclass 36, count 2 2006.285.17:55:53.63#ibcon#read 6, iclass 36, count 2 2006.285.17:55:53.63#ibcon#end of sib2, iclass 36, count 2 2006.285.17:55:53.63#ibcon#*after write, iclass 36, count 2 2006.285.17:55:53.63#ibcon#*before return 0, iclass 36, count 2 2006.285.17:55:53.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:55:53.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.17:55:53.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.17:55:53.63#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:53.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:55:53.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:55:53.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:55:53.75#ibcon#enter wrdev, iclass 36, count 0 2006.285.17:55:53.75#ibcon#first serial, iclass 36, count 0 2006.285.17:55:53.75#ibcon#enter sib2, iclass 36, count 0 2006.285.17:55:53.75#ibcon#flushed, iclass 36, count 0 2006.285.17:55:53.75#ibcon#about to write, iclass 36, count 0 2006.285.17:55:53.75#ibcon#wrote, iclass 36, count 0 2006.285.17:55:53.75#ibcon#about to read 3, iclass 36, count 0 2006.285.17:55:53.77#ibcon#read 3, iclass 36, count 0 2006.285.17:55:53.77#ibcon#about to read 4, iclass 36, count 0 2006.285.17:55:53.77#ibcon#read 4, iclass 36, count 0 2006.285.17:55:53.77#ibcon#about to read 5, iclass 36, count 0 2006.285.17:55:53.77#ibcon#read 5, iclass 36, count 0 2006.285.17:55:53.77#ibcon#about to read 6, iclass 36, count 0 2006.285.17:55:53.77#ibcon#read 6, iclass 36, count 0 2006.285.17:55:53.77#ibcon#end of sib2, iclass 36, count 0 2006.285.17:55:53.77#ibcon#*mode == 0, iclass 36, count 0 2006.285.17:55:53.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.17:55:53.77#ibcon#[27=USB\r\n] 2006.285.17:55:53.77#ibcon#*before write, iclass 36, count 0 2006.285.17:55:53.77#ibcon#enter sib2, iclass 36, count 0 2006.285.17:55:53.77#ibcon#flushed, iclass 36, count 0 2006.285.17:55:53.77#ibcon#about to write, iclass 36, count 0 2006.285.17:55:53.77#ibcon#wrote, iclass 36, count 0 2006.285.17:55:53.77#ibcon#about to read 3, iclass 36, count 0 2006.285.17:55:53.80#ibcon#read 3, iclass 36, count 0 2006.285.17:55:53.80#ibcon#about to read 4, iclass 36, count 0 2006.285.17:55:53.80#ibcon#read 4, iclass 36, count 0 2006.285.17:55:53.80#ibcon#about to read 5, iclass 36, count 0 2006.285.17:55:53.80#ibcon#read 5, iclass 36, count 0 2006.285.17:55:53.80#ibcon#about to read 6, iclass 36, count 0 2006.285.17:55:53.80#ibcon#read 6, iclass 36, count 0 2006.285.17:55:53.80#ibcon#end of sib2, iclass 36, count 0 2006.285.17:55:53.80#ibcon#*after write, iclass 36, count 0 2006.285.17:55:53.80#ibcon#*before return 0, iclass 36, count 0 2006.285.17:55:53.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:55:53.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.17:55:53.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.17:55:53.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.17:55:53.80$vck44/vblo=6,719.99 2006.285.17:55:53.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.17:55:53.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.17:55:53.80#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:53.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:55:53.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:55:53.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:55:53.80#ibcon#enter wrdev, iclass 38, count 0 2006.285.17:55:53.80#ibcon#first serial, iclass 38, count 0 2006.285.17:55:53.80#ibcon#enter sib2, iclass 38, count 0 2006.285.17:55:53.80#ibcon#flushed, iclass 38, count 0 2006.285.17:55:53.80#ibcon#about to write, iclass 38, count 0 2006.285.17:55:53.80#ibcon#wrote, iclass 38, count 0 2006.285.17:55:53.80#ibcon#about to read 3, iclass 38, count 0 2006.285.17:55:53.82#ibcon#read 3, iclass 38, count 0 2006.285.17:55:53.82#ibcon#about to read 4, iclass 38, count 0 2006.285.17:55:53.82#ibcon#read 4, iclass 38, count 0 2006.285.17:55:53.82#ibcon#about to read 5, iclass 38, count 0 2006.285.17:55:53.82#ibcon#read 5, iclass 38, count 0 2006.285.17:55:53.82#ibcon#about to read 6, iclass 38, count 0 2006.285.17:55:53.82#ibcon#read 6, iclass 38, count 0 2006.285.17:55:53.82#ibcon#end of sib2, iclass 38, count 0 2006.285.17:55:53.82#ibcon#*mode == 0, iclass 38, count 0 2006.285.17:55:53.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.17:55:53.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.17:55:53.82#ibcon#*before write, iclass 38, count 0 2006.285.17:55:53.82#ibcon#enter sib2, iclass 38, count 0 2006.285.17:55:53.82#ibcon#flushed, iclass 38, count 0 2006.285.17:55:53.82#ibcon#about to write, iclass 38, count 0 2006.285.17:55:53.82#ibcon#wrote, iclass 38, count 0 2006.285.17:55:53.82#ibcon#about to read 3, iclass 38, count 0 2006.285.17:55:53.86#ibcon#read 3, iclass 38, count 0 2006.285.17:55:53.86#ibcon#about to read 4, iclass 38, count 0 2006.285.17:55:53.86#ibcon#read 4, iclass 38, count 0 2006.285.17:55:53.86#ibcon#about to read 5, iclass 38, count 0 2006.285.17:55:53.86#ibcon#read 5, iclass 38, count 0 2006.285.17:55:53.86#ibcon#about to read 6, iclass 38, count 0 2006.285.17:55:53.86#ibcon#read 6, iclass 38, count 0 2006.285.17:55:53.86#ibcon#end of sib2, iclass 38, count 0 2006.285.17:55:53.86#ibcon#*after write, iclass 38, count 0 2006.285.17:55:53.86#ibcon#*before return 0, iclass 38, count 0 2006.285.17:55:53.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:55:53.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.17:55:53.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.17:55:53.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.17:55:53.86$vck44/vb=6,3 2006.285.17:55:53.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.17:55:53.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.17:55:53.86#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:53.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:55:53.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:55:53.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:55:53.92#ibcon#enter wrdev, iclass 40, count 2 2006.285.17:55:53.92#ibcon#first serial, iclass 40, count 2 2006.285.17:55:53.92#ibcon#enter sib2, iclass 40, count 2 2006.285.17:55:53.92#ibcon#flushed, iclass 40, count 2 2006.285.17:55:53.92#ibcon#about to write, iclass 40, count 2 2006.285.17:55:53.92#ibcon#wrote, iclass 40, count 2 2006.285.17:55:53.92#ibcon#about to read 3, iclass 40, count 2 2006.285.17:55:53.94#ibcon#read 3, iclass 40, count 2 2006.285.17:55:53.94#ibcon#about to read 4, iclass 40, count 2 2006.285.17:55:53.94#ibcon#read 4, iclass 40, count 2 2006.285.17:55:53.94#ibcon#about to read 5, iclass 40, count 2 2006.285.17:55:53.94#ibcon#read 5, iclass 40, count 2 2006.285.17:55:53.94#ibcon#about to read 6, iclass 40, count 2 2006.285.17:55:53.94#ibcon#read 6, iclass 40, count 2 2006.285.17:55:53.94#ibcon#end of sib2, iclass 40, count 2 2006.285.17:55:53.94#ibcon#*mode == 0, iclass 40, count 2 2006.285.17:55:53.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.17:55:53.94#ibcon#[27=AT06-03\r\n] 2006.285.17:55:53.94#ibcon#*before write, iclass 40, count 2 2006.285.17:55:53.94#ibcon#enter sib2, iclass 40, count 2 2006.285.17:55:53.94#ibcon#flushed, iclass 40, count 2 2006.285.17:55:53.94#ibcon#about to write, iclass 40, count 2 2006.285.17:55:53.94#ibcon#wrote, iclass 40, count 2 2006.285.17:55:53.94#ibcon#about to read 3, iclass 40, count 2 2006.285.17:55:53.97#ibcon#read 3, iclass 40, count 2 2006.285.17:55:53.97#ibcon#about to read 4, iclass 40, count 2 2006.285.17:55:53.97#ibcon#read 4, iclass 40, count 2 2006.285.17:55:53.97#ibcon#about to read 5, iclass 40, count 2 2006.285.17:55:53.97#ibcon#read 5, iclass 40, count 2 2006.285.17:55:53.97#ibcon#about to read 6, iclass 40, count 2 2006.285.17:55:53.97#ibcon#read 6, iclass 40, count 2 2006.285.17:55:53.97#ibcon#end of sib2, iclass 40, count 2 2006.285.17:55:53.97#ibcon#*after write, iclass 40, count 2 2006.285.17:55:53.97#ibcon#*before return 0, iclass 40, count 2 2006.285.17:55:53.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:55:53.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.17:55:53.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.17:55:53.97#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:53.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:55:54.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:55:54.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:55:54.09#ibcon#enter wrdev, iclass 40, count 0 2006.285.17:55:54.09#ibcon#first serial, iclass 40, count 0 2006.285.17:55:54.09#ibcon#enter sib2, iclass 40, count 0 2006.285.17:55:54.09#ibcon#flushed, iclass 40, count 0 2006.285.17:55:54.09#ibcon#about to write, iclass 40, count 0 2006.285.17:55:54.09#ibcon#wrote, iclass 40, count 0 2006.285.17:55:54.09#ibcon#about to read 3, iclass 40, count 0 2006.285.17:55:54.11#ibcon#read 3, iclass 40, count 0 2006.285.17:55:54.11#ibcon#about to read 4, iclass 40, count 0 2006.285.17:55:54.11#ibcon#read 4, iclass 40, count 0 2006.285.17:55:54.11#ibcon#about to read 5, iclass 40, count 0 2006.285.17:55:54.11#ibcon#read 5, iclass 40, count 0 2006.285.17:55:54.11#ibcon#about to read 6, iclass 40, count 0 2006.285.17:55:54.11#ibcon#read 6, iclass 40, count 0 2006.285.17:55:54.11#ibcon#end of sib2, iclass 40, count 0 2006.285.17:55:54.11#ibcon#*mode == 0, iclass 40, count 0 2006.285.17:55:54.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.17:55:54.11#ibcon#[27=USB\r\n] 2006.285.17:55:54.11#ibcon#*before write, iclass 40, count 0 2006.285.17:55:54.11#ibcon#enter sib2, iclass 40, count 0 2006.285.17:55:54.11#ibcon#flushed, iclass 40, count 0 2006.285.17:55:54.11#ibcon#about to write, iclass 40, count 0 2006.285.17:55:54.11#ibcon#wrote, iclass 40, count 0 2006.285.17:55:54.11#ibcon#about to read 3, iclass 40, count 0 2006.285.17:55:54.14#ibcon#read 3, iclass 40, count 0 2006.285.17:55:54.14#ibcon#about to read 4, iclass 40, count 0 2006.285.17:55:54.14#ibcon#read 4, iclass 40, count 0 2006.285.17:55:54.14#ibcon#about to read 5, iclass 40, count 0 2006.285.17:55:54.14#ibcon#read 5, iclass 40, count 0 2006.285.17:55:54.14#ibcon#about to read 6, iclass 40, count 0 2006.285.17:55:54.14#ibcon#read 6, iclass 40, count 0 2006.285.17:55:54.14#ibcon#end of sib2, iclass 40, count 0 2006.285.17:55:54.14#ibcon#*after write, iclass 40, count 0 2006.285.17:55:54.14#ibcon#*before return 0, iclass 40, count 0 2006.285.17:55:54.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:55:54.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.17:55:54.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.17:55:54.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.17:55:54.14$vck44/vblo=7,734.99 2006.285.17:55:54.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.17:55:54.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.17:55:54.14#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:54.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:55:54.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:55:54.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:55:54.14#ibcon#enter wrdev, iclass 4, count 0 2006.285.17:55:54.14#ibcon#first serial, iclass 4, count 0 2006.285.17:55:54.14#ibcon#enter sib2, iclass 4, count 0 2006.285.17:55:54.14#ibcon#flushed, iclass 4, count 0 2006.285.17:55:54.14#ibcon#about to write, iclass 4, count 0 2006.285.17:55:54.14#ibcon#wrote, iclass 4, count 0 2006.285.17:55:54.14#ibcon#about to read 3, iclass 4, count 0 2006.285.17:55:54.16#ibcon#read 3, iclass 4, count 0 2006.285.17:55:54.16#ibcon#about to read 4, iclass 4, count 0 2006.285.17:55:54.16#ibcon#read 4, iclass 4, count 0 2006.285.17:55:54.16#ibcon#about to read 5, iclass 4, count 0 2006.285.17:55:54.16#ibcon#read 5, iclass 4, count 0 2006.285.17:55:54.16#ibcon#about to read 6, iclass 4, count 0 2006.285.17:55:54.16#ibcon#read 6, iclass 4, count 0 2006.285.17:55:54.16#ibcon#end of sib2, iclass 4, count 0 2006.285.17:55:54.16#ibcon#*mode == 0, iclass 4, count 0 2006.285.17:55:54.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.17:55:54.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.17:55:54.16#ibcon#*before write, iclass 4, count 0 2006.285.17:55:54.16#ibcon#enter sib2, iclass 4, count 0 2006.285.17:55:54.16#ibcon#flushed, iclass 4, count 0 2006.285.17:55:54.16#ibcon#about to write, iclass 4, count 0 2006.285.17:55:54.16#ibcon#wrote, iclass 4, count 0 2006.285.17:55:54.16#ibcon#about to read 3, iclass 4, count 0 2006.285.17:55:54.20#ibcon#read 3, iclass 4, count 0 2006.285.17:55:54.20#ibcon#about to read 4, iclass 4, count 0 2006.285.17:55:54.20#ibcon#read 4, iclass 4, count 0 2006.285.17:55:54.20#ibcon#about to read 5, iclass 4, count 0 2006.285.17:55:54.20#ibcon#read 5, iclass 4, count 0 2006.285.17:55:54.20#ibcon#about to read 6, iclass 4, count 0 2006.285.17:55:54.20#ibcon#read 6, iclass 4, count 0 2006.285.17:55:54.20#ibcon#end of sib2, iclass 4, count 0 2006.285.17:55:54.20#ibcon#*after write, iclass 4, count 0 2006.285.17:55:54.20#ibcon#*before return 0, iclass 4, count 0 2006.285.17:55:54.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:55:54.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.17:55:54.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.17:55:54.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.17:55:54.20$vck44/vb=7,4 2006.285.17:55:54.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.17:55:54.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.17:55:54.20#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:54.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:55:54.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:55:54.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:55:54.26#ibcon#enter wrdev, iclass 6, count 2 2006.285.17:55:54.26#ibcon#first serial, iclass 6, count 2 2006.285.17:55:54.26#ibcon#enter sib2, iclass 6, count 2 2006.285.17:55:54.26#ibcon#flushed, iclass 6, count 2 2006.285.17:55:54.26#ibcon#about to write, iclass 6, count 2 2006.285.17:55:54.26#ibcon#wrote, iclass 6, count 2 2006.285.17:55:54.26#ibcon#about to read 3, iclass 6, count 2 2006.285.17:55:54.28#ibcon#read 3, iclass 6, count 2 2006.285.17:55:54.28#ibcon#about to read 4, iclass 6, count 2 2006.285.17:55:54.28#ibcon#read 4, iclass 6, count 2 2006.285.17:55:54.28#ibcon#about to read 5, iclass 6, count 2 2006.285.17:55:54.28#ibcon#read 5, iclass 6, count 2 2006.285.17:55:54.28#ibcon#about to read 6, iclass 6, count 2 2006.285.17:55:54.28#ibcon#read 6, iclass 6, count 2 2006.285.17:55:54.28#ibcon#end of sib2, iclass 6, count 2 2006.285.17:55:54.28#ibcon#*mode == 0, iclass 6, count 2 2006.285.17:55:54.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.17:55:54.28#ibcon#[27=AT07-04\r\n] 2006.285.17:55:54.28#ibcon#*before write, iclass 6, count 2 2006.285.17:55:54.28#ibcon#enter sib2, iclass 6, count 2 2006.285.17:55:54.28#ibcon#flushed, iclass 6, count 2 2006.285.17:55:54.28#ibcon#about to write, iclass 6, count 2 2006.285.17:55:54.28#ibcon#wrote, iclass 6, count 2 2006.285.17:55:54.28#ibcon#about to read 3, iclass 6, count 2 2006.285.17:55:54.31#ibcon#read 3, iclass 6, count 2 2006.285.17:55:54.31#ibcon#about to read 4, iclass 6, count 2 2006.285.17:55:54.31#ibcon#read 4, iclass 6, count 2 2006.285.17:55:54.31#ibcon#about to read 5, iclass 6, count 2 2006.285.17:55:54.31#ibcon#read 5, iclass 6, count 2 2006.285.17:55:54.31#ibcon#about to read 6, iclass 6, count 2 2006.285.17:55:54.31#ibcon#read 6, iclass 6, count 2 2006.285.17:55:54.31#ibcon#end of sib2, iclass 6, count 2 2006.285.17:55:54.31#ibcon#*after write, iclass 6, count 2 2006.285.17:55:54.31#ibcon#*before return 0, iclass 6, count 2 2006.285.17:55:54.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:55:54.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.17:55:54.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.17:55:54.31#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:54.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:55:54.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:55:54.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:55:54.43#ibcon#enter wrdev, iclass 6, count 0 2006.285.17:55:54.43#ibcon#first serial, iclass 6, count 0 2006.285.17:55:54.43#ibcon#enter sib2, iclass 6, count 0 2006.285.17:55:54.43#ibcon#flushed, iclass 6, count 0 2006.285.17:55:54.43#ibcon#about to write, iclass 6, count 0 2006.285.17:55:54.43#ibcon#wrote, iclass 6, count 0 2006.285.17:55:54.43#ibcon#about to read 3, iclass 6, count 0 2006.285.17:55:54.45#ibcon#read 3, iclass 6, count 0 2006.285.17:55:54.45#ibcon#about to read 4, iclass 6, count 0 2006.285.17:55:54.45#ibcon#read 4, iclass 6, count 0 2006.285.17:55:54.45#ibcon#about to read 5, iclass 6, count 0 2006.285.17:55:54.45#ibcon#read 5, iclass 6, count 0 2006.285.17:55:54.45#ibcon#about to read 6, iclass 6, count 0 2006.285.17:55:54.45#ibcon#read 6, iclass 6, count 0 2006.285.17:55:54.45#ibcon#end of sib2, iclass 6, count 0 2006.285.17:55:54.45#ibcon#*mode == 0, iclass 6, count 0 2006.285.17:55:54.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.17:55:54.45#ibcon#[27=USB\r\n] 2006.285.17:55:54.45#ibcon#*before write, iclass 6, count 0 2006.285.17:55:54.45#ibcon#enter sib2, iclass 6, count 0 2006.285.17:55:54.45#ibcon#flushed, iclass 6, count 0 2006.285.17:55:54.45#ibcon#about to write, iclass 6, count 0 2006.285.17:55:54.45#ibcon#wrote, iclass 6, count 0 2006.285.17:55:54.45#ibcon#about to read 3, iclass 6, count 0 2006.285.17:55:54.48#ibcon#read 3, iclass 6, count 0 2006.285.17:55:54.48#ibcon#about to read 4, iclass 6, count 0 2006.285.17:55:54.48#ibcon#read 4, iclass 6, count 0 2006.285.17:55:54.48#ibcon#about to read 5, iclass 6, count 0 2006.285.17:55:54.48#ibcon#read 5, iclass 6, count 0 2006.285.17:55:54.48#ibcon#about to read 6, iclass 6, count 0 2006.285.17:55:54.48#ibcon#read 6, iclass 6, count 0 2006.285.17:55:54.48#ibcon#end of sib2, iclass 6, count 0 2006.285.17:55:54.48#ibcon#*after write, iclass 6, count 0 2006.285.17:55:54.48#ibcon#*before return 0, iclass 6, count 0 2006.285.17:55:54.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:55:54.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.17:55:54.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.17:55:54.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.17:55:54.48$vck44/vblo=8,744.99 2006.285.17:55:54.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.17:55:54.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.17:55:54.48#ibcon#ireg 17 cls_cnt 0 2006.285.17:55:54.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:55:54.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:55:54.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:55:54.48#ibcon#enter wrdev, iclass 10, count 0 2006.285.17:55:54.48#ibcon#first serial, iclass 10, count 0 2006.285.17:55:54.48#ibcon#enter sib2, iclass 10, count 0 2006.285.17:55:54.48#ibcon#flushed, iclass 10, count 0 2006.285.17:55:54.48#ibcon#about to write, iclass 10, count 0 2006.285.17:55:54.48#ibcon#wrote, iclass 10, count 0 2006.285.17:55:54.48#ibcon#about to read 3, iclass 10, count 0 2006.285.17:55:54.50#ibcon#read 3, iclass 10, count 0 2006.285.17:55:54.50#ibcon#about to read 4, iclass 10, count 0 2006.285.17:55:54.50#ibcon#read 4, iclass 10, count 0 2006.285.17:55:54.50#ibcon#about to read 5, iclass 10, count 0 2006.285.17:55:54.50#ibcon#read 5, iclass 10, count 0 2006.285.17:55:54.50#ibcon#about to read 6, iclass 10, count 0 2006.285.17:55:54.50#ibcon#read 6, iclass 10, count 0 2006.285.17:55:54.50#ibcon#end of sib2, iclass 10, count 0 2006.285.17:55:54.50#ibcon#*mode == 0, iclass 10, count 0 2006.285.17:55:54.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.17:55:54.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.17:55:54.50#ibcon#*before write, iclass 10, count 0 2006.285.17:55:54.50#ibcon#enter sib2, iclass 10, count 0 2006.285.17:55:54.50#ibcon#flushed, iclass 10, count 0 2006.285.17:55:54.50#ibcon#about to write, iclass 10, count 0 2006.285.17:55:54.50#ibcon#wrote, iclass 10, count 0 2006.285.17:55:54.50#ibcon#about to read 3, iclass 10, count 0 2006.285.17:55:54.54#ibcon#read 3, iclass 10, count 0 2006.285.17:55:54.54#ibcon#about to read 4, iclass 10, count 0 2006.285.17:55:54.54#ibcon#read 4, iclass 10, count 0 2006.285.17:55:54.54#ibcon#about to read 5, iclass 10, count 0 2006.285.17:55:54.54#ibcon#read 5, iclass 10, count 0 2006.285.17:55:54.54#ibcon#about to read 6, iclass 10, count 0 2006.285.17:55:54.54#ibcon#read 6, iclass 10, count 0 2006.285.17:55:54.54#ibcon#end of sib2, iclass 10, count 0 2006.285.17:55:54.54#ibcon#*after write, iclass 10, count 0 2006.285.17:55:54.54#ibcon#*before return 0, iclass 10, count 0 2006.285.17:55:54.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:55:54.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.17:55:54.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.17:55:54.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.17:55:54.54$vck44/vb=8,4 2006.285.17:55:54.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.17:55:54.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.17:55:54.54#ibcon#ireg 11 cls_cnt 2 2006.285.17:55:54.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:55:54.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:55:54.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:55:54.60#ibcon#enter wrdev, iclass 12, count 2 2006.285.17:55:54.60#ibcon#first serial, iclass 12, count 2 2006.285.17:55:54.60#ibcon#enter sib2, iclass 12, count 2 2006.285.17:55:54.60#ibcon#flushed, iclass 12, count 2 2006.285.17:55:54.60#ibcon#about to write, iclass 12, count 2 2006.285.17:55:54.60#ibcon#wrote, iclass 12, count 2 2006.285.17:55:54.60#ibcon#about to read 3, iclass 12, count 2 2006.285.17:55:54.62#ibcon#read 3, iclass 12, count 2 2006.285.17:55:54.62#ibcon#about to read 4, iclass 12, count 2 2006.285.17:55:54.62#ibcon#read 4, iclass 12, count 2 2006.285.17:55:54.62#ibcon#about to read 5, iclass 12, count 2 2006.285.17:55:54.62#ibcon#read 5, iclass 12, count 2 2006.285.17:55:54.62#ibcon#about to read 6, iclass 12, count 2 2006.285.17:55:54.62#ibcon#read 6, iclass 12, count 2 2006.285.17:55:54.62#ibcon#end of sib2, iclass 12, count 2 2006.285.17:55:54.62#ibcon#*mode == 0, iclass 12, count 2 2006.285.17:55:54.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.17:55:54.62#ibcon#[27=AT08-04\r\n] 2006.285.17:55:54.62#ibcon#*before write, iclass 12, count 2 2006.285.17:55:54.62#ibcon#enter sib2, iclass 12, count 2 2006.285.17:55:54.62#ibcon#flushed, iclass 12, count 2 2006.285.17:55:54.62#ibcon#about to write, iclass 12, count 2 2006.285.17:55:54.62#ibcon#wrote, iclass 12, count 2 2006.285.17:55:54.62#ibcon#about to read 3, iclass 12, count 2 2006.285.17:55:54.65#ibcon#read 3, iclass 12, count 2 2006.285.17:55:54.65#ibcon#about to read 4, iclass 12, count 2 2006.285.17:55:54.65#ibcon#read 4, iclass 12, count 2 2006.285.17:55:54.65#ibcon#about to read 5, iclass 12, count 2 2006.285.17:55:54.65#ibcon#read 5, iclass 12, count 2 2006.285.17:55:54.65#ibcon#about to read 6, iclass 12, count 2 2006.285.17:55:54.65#ibcon#read 6, iclass 12, count 2 2006.285.17:55:54.65#ibcon#end of sib2, iclass 12, count 2 2006.285.17:55:54.65#ibcon#*after write, iclass 12, count 2 2006.285.17:55:54.65#ibcon#*before return 0, iclass 12, count 2 2006.285.17:55:54.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:55:54.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.17:55:54.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.17:55:54.65#ibcon#ireg 7 cls_cnt 0 2006.285.17:55:54.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:55:54.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:55:54.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:55:54.77#ibcon#enter wrdev, iclass 12, count 0 2006.285.17:55:54.77#ibcon#first serial, iclass 12, count 0 2006.285.17:55:54.77#ibcon#enter sib2, iclass 12, count 0 2006.285.17:55:54.77#ibcon#flushed, iclass 12, count 0 2006.285.17:55:54.77#ibcon#about to write, iclass 12, count 0 2006.285.17:55:54.77#ibcon#wrote, iclass 12, count 0 2006.285.17:55:54.77#ibcon#about to read 3, iclass 12, count 0 2006.285.17:55:54.79#ibcon#read 3, iclass 12, count 0 2006.285.17:55:54.79#ibcon#about to read 4, iclass 12, count 0 2006.285.17:55:54.79#ibcon#read 4, iclass 12, count 0 2006.285.17:55:54.79#ibcon#about to read 5, iclass 12, count 0 2006.285.17:55:54.79#ibcon#read 5, iclass 12, count 0 2006.285.17:55:54.79#ibcon#about to read 6, iclass 12, count 0 2006.285.17:55:54.79#ibcon#read 6, iclass 12, count 0 2006.285.17:55:54.79#ibcon#end of sib2, iclass 12, count 0 2006.285.17:55:54.79#ibcon#*mode == 0, iclass 12, count 0 2006.285.17:55:54.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.17:55:54.79#ibcon#[27=USB\r\n] 2006.285.17:55:54.79#ibcon#*before write, iclass 12, count 0 2006.285.17:55:54.79#ibcon#enter sib2, iclass 12, count 0 2006.285.17:55:54.79#ibcon#flushed, iclass 12, count 0 2006.285.17:55:54.79#ibcon#about to write, iclass 12, count 0 2006.285.17:55:54.79#ibcon#wrote, iclass 12, count 0 2006.285.17:55:54.79#ibcon#about to read 3, iclass 12, count 0 2006.285.17:55:54.82#ibcon#read 3, iclass 12, count 0 2006.285.17:55:54.82#ibcon#about to read 4, iclass 12, count 0 2006.285.17:55:54.82#ibcon#read 4, iclass 12, count 0 2006.285.17:55:54.82#ibcon#about to read 5, iclass 12, count 0 2006.285.17:55:54.82#ibcon#read 5, iclass 12, count 0 2006.285.17:55:54.82#ibcon#about to read 6, iclass 12, count 0 2006.285.17:55:54.82#ibcon#read 6, iclass 12, count 0 2006.285.17:55:54.82#ibcon#end of sib2, iclass 12, count 0 2006.285.17:55:54.82#ibcon#*after write, iclass 12, count 0 2006.285.17:55:54.82#ibcon#*before return 0, iclass 12, count 0 2006.285.17:55:54.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:55:54.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.17:55:54.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.17:55:54.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.17:55:54.82$vck44/vabw=wide 2006.285.17:55:54.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.17:55:54.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.17:55:54.82#ibcon#ireg 8 cls_cnt 0 2006.285.17:55:54.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:55:54.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:55:54.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:55:54.82#ibcon#enter wrdev, iclass 14, count 0 2006.285.17:55:54.82#ibcon#first serial, iclass 14, count 0 2006.285.17:55:54.82#ibcon#enter sib2, iclass 14, count 0 2006.285.17:55:54.82#ibcon#flushed, iclass 14, count 0 2006.285.17:55:54.82#ibcon#about to write, iclass 14, count 0 2006.285.17:55:54.82#ibcon#wrote, iclass 14, count 0 2006.285.17:55:54.82#ibcon#about to read 3, iclass 14, count 0 2006.285.17:55:54.84#ibcon#read 3, iclass 14, count 0 2006.285.17:55:54.84#ibcon#about to read 4, iclass 14, count 0 2006.285.17:55:54.84#ibcon#read 4, iclass 14, count 0 2006.285.17:55:54.84#ibcon#about to read 5, iclass 14, count 0 2006.285.17:55:54.84#ibcon#read 5, iclass 14, count 0 2006.285.17:55:54.84#ibcon#about to read 6, iclass 14, count 0 2006.285.17:55:54.84#ibcon#read 6, iclass 14, count 0 2006.285.17:55:54.84#ibcon#end of sib2, iclass 14, count 0 2006.285.17:55:54.84#ibcon#*mode == 0, iclass 14, count 0 2006.285.17:55:54.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.17:55:54.84#ibcon#[25=BW32\r\n] 2006.285.17:55:54.84#ibcon#*before write, iclass 14, count 0 2006.285.17:55:54.84#ibcon#enter sib2, iclass 14, count 0 2006.285.17:55:54.84#ibcon#flushed, iclass 14, count 0 2006.285.17:55:54.84#ibcon#about to write, iclass 14, count 0 2006.285.17:55:54.84#ibcon#wrote, iclass 14, count 0 2006.285.17:55:54.84#ibcon#about to read 3, iclass 14, count 0 2006.285.17:55:54.87#ibcon#read 3, iclass 14, count 0 2006.285.17:55:54.87#ibcon#about to read 4, iclass 14, count 0 2006.285.17:55:54.87#ibcon#read 4, iclass 14, count 0 2006.285.17:55:54.87#ibcon#about to read 5, iclass 14, count 0 2006.285.17:55:54.87#ibcon#read 5, iclass 14, count 0 2006.285.17:55:54.87#ibcon#about to read 6, iclass 14, count 0 2006.285.17:55:54.87#ibcon#read 6, iclass 14, count 0 2006.285.17:55:54.87#ibcon#end of sib2, iclass 14, count 0 2006.285.17:55:54.87#ibcon#*after write, iclass 14, count 0 2006.285.17:55:54.87#ibcon#*before return 0, iclass 14, count 0 2006.285.17:55:54.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:55:54.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.17:55:54.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.17:55:54.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.17:55:54.87$vck44/vbbw=wide 2006.285.17:55:54.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.17:55:54.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.17:55:54.87#ibcon#ireg 8 cls_cnt 0 2006.285.17:55:54.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:55:54.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:55:54.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:55:54.94#ibcon#enter wrdev, iclass 16, count 0 2006.285.17:55:54.94#ibcon#first serial, iclass 16, count 0 2006.285.17:55:54.94#ibcon#enter sib2, iclass 16, count 0 2006.285.17:55:54.94#ibcon#flushed, iclass 16, count 0 2006.285.17:55:54.94#ibcon#about to write, iclass 16, count 0 2006.285.17:55:54.94#ibcon#wrote, iclass 16, count 0 2006.285.17:55:54.94#ibcon#about to read 3, iclass 16, count 0 2006.285.17:55:54.96#ibcon#read 3, iclass 16, count 0 2006.285.17:55:54.96#ibcon#about to read 4, iclass 16, count 0 2006.285.17:55:54.96#ibcon#read 4, iclass 16, count 0 2006.285.17:55:54.96#ibcon#about to read 5, iclass 16, count 0 2006.285.17:55:54.96#ibcon#read 5, iclass 16, count 0 2006.285.17:55:54.96#ibcon#about to read 6, iclass 16, count 0 2006.285.17:55:54.96#ibcon#read 6, iclass 16, count 0 2006.285.17:55:54.96#ibcon#end of sib2, iclass 16, count 0 2006.285.17:55:54.96#ibcon#*mode == 0, iclass 16, count 0 2006.285.17:55:54.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.17:55:54.96#ibcon#[27=BW32\r\n] 2006.285.17:55:54.96#ibcon#*before write, iclass 16, count 0 2006.285.17:55:54.96#ibcon#enter sib2, iclass 16, count 0 2006.285.17:55:54.96#ibcon#flushed, iclass 16, count 0 2006.285.17:55:54.96#ibcon#about to write, iclass 16, count 0 2006.285.17:55:54.96#ibcon#wrote, iclass 16, count 0 2006.285.17:55:54.96#ibcon#about to read 3, iclass 16, count 0 2006.285.17:55:54.99#ibcon#read 3, iclass 16, count 0 2006.285.17:55:54.99#ibcon#about to read 4, iclass 16, count 0 2006.285.17:55:54.99#ibcon#read 4, iclass 16, count 0 2006.285.17:55:54.99#ibcon#about to read 5, iclass 16, count 0 2006.285.17:55:54.99#ibcon#read 5, iclass 16, count 0 2006.285.17:55:54.99#ibcon#about to read 6, iclass 16, count 0 2006.285.17:55:54.99#ibcon#read 6, iclass 16, count 0 2006.285.17:55:54.99#ibcon#end of sib2, iclass 16, count 0 2006.285.17:55:54.99#ibcon#*after write, iclass 16, count 0 2006.285.17:55:54.99#ibcon#*before return 0, iclass 16, count 0 2006.285.17:55:54.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:55:54.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.17:55:54.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.17:55:54.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.17:55:54.99$setupk4/ifdk4 2006.285.17:55:54.99$ifdk4/lo= 2006.285.17:55:54.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.17:55:54.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.17:55:54.99$ifdk4/patch= 2006.285.17:55:54.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.17:55:54.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.17:55:54.99$setupk4/!*+20s 2006.285.17:55:56.60#abcon#<5=/09 0.5 1.0 16.241001014.5\r\n> 2006.285.17:55:56.62#abcon#{5=INTERFACE CLEAR} 2006.285.17:55:56.68#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:56:05.14#trakl#Source acquired 2006.285.17:56:06.14#flagr#flagr/antenna,acquired 2006.285.17:56:06.77#abcon#<5=/08 0.5 1.0 16.231001014.4\r\n> 2006.285.17:56:06.79#abcon#{5=INTERFACE CLEAR} 2006.285.17:56:06.85#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:56:08.45$setupk4/"tpicd 2006.285.17:56:08.45$setupk4/echo=off 2006.285.17:56:08.45$setupk4/xlog=off 2006.285.17:56:08.45:!2006.285.17:57:13 2006.285.17:57:13.00:preob 2006.285.17:57:13.14/onsource/TRACKING 2006.285.17:57:13.14:!2006.285.17:57:23 2006.285.17:57:23.00:"tape 2006.285.17:57:23.00:"st=record 2006.285.17:57:23.00:data_valid=on 2006.285.17:57:23.00:midob 2006.285.17:57:24.14/onsource/TRACKING 2006.285.17:57:24.14/wx/16.20,1014.4,100 2006.285.17:57:24.27/cable/+6.5031E-03 2006.285.17:57:25.36/va/01,07,usb,yes,33,35 2006.285.17:57:25.36/va/02,06,usb,yes,33,33 2006.285.17:57:25.36/va/03,07,usb,yes,32,34 2006.285.17:57:25.36/va/04,06,usb,yes,34,35 2006.285.17:57:25.36/va/05,03,usb,yes,34,34 2006.285.17:57:25.36/va/06,04,usb,yes,30,30 2006.285.17:57:25.36/va/07,04,usb,yes,31,31 2006.285.17:57:25.36/va/08,03,usb,yes,32,38 2006.285.17:57:25.59/valo/01,524.99,yes,locked 2006.285.17:57:25.59/valo/02,534.99,yes,locked 2006.285.17:57:25.59/valo/03,564.99,yes,locked 2006.285.17:57:25.59/valo/04,624.99,yes,locked 2006.285.17:57:25.59/valo/05,734.99,yes,locked 2006.285.17:57:25.59/valo/06,814.99,yes,locked 2006.285.17:57:25.59/valo/07,864.99,yes,locked 2006.285.17:57:25.59/valo/08,884.99,yes,locked 2006.285.17:57:26.68/vb/01,04,usb,yes,30,28 2006.285.17:57:26.68/vb/02,05,usb,yes,29,29 2006.285.17:57:26.68/vb/03,04,usb,yes,30,33 2006.285.17:57:26.68/vb/04,05,usb,yes,30,29 2006.285.17:57:26.68/vb/05,04,usb,yes,26,29 2006.285.17:57:26.68/vb/06,03,usb,yes,38,34 2006.285.17:57:26.68/vb/07,04,usb,yes,31,30 2006.285.17:57:26.68/vb/08,04,usb,yes,28,31 2006.285.17:57:26.91/vblo/01,629.99,yes,locked 2006.285.17:57:26.91/vblo/02,634.99,yes,locked 2006.285.17:57:26.91/vblo/03,649.99,yes,locked 2006.285.17:57:26.91/vblo/04,679.99,yes,locked 2006.285.17:57:26.91/vblo/05,709.99,yes,locked 2006.285.17:57:26.91/vblo/06,719.99,yes,locked 2006.285.17:57:26.91/vblo/07,734.99,yes,locked 2006.285.17:57:26.91/vblo/08,744.99,yes,locked 2006.285.17:57:27.06/vabw/8 2006.285.17:57:27.21/vbbw/8 2006.285.17:57:27.37/xfe/off,on,12.0 2006.285.17:57:27.75/ifatt/23,28,28,28 2006.285.17:57:28.07/fmout-gps/S +2.63E-07 2006.285.17:57:28.09:!2006.285.17:58:23 2006.285.17:58:23.01:data_valid=off 2006.285.17:58:23.01:"et 2006.285.17:58:23.01:!+3s 2006.285.17:58:26.02:"tape 2006.285.17:58:26.02:postob 2006.285.17:58:26.22/cable/+6.5029E-03 2006.285.17:58:26.22/wx/16.19,1014.4,100 2006.285.17:58:26.28/fmout-gps/S +2.62E-07 2006.285.17:58:26.28:scan_name=285-1800,jd0610,40 2006.285.17:58:26.28:source=0537-441,053850.36,-440508.9,2000.0,ccw 2006.285.17:58:27.14#flagr#flagr/antenna,new-source 2006.285.17:58:27.14:checkk5 2006.285.17:58:27.58/chk_autoobs//k5ts1/ autoobs is running! 2006.285.17:58:28.29/chk_autoobs//k5ts2/ autoobs is running! 2006.285.17:58:28.75/chk_autoobs//k5ts3/ autoobs is running! 2006.285.17:58:29.22/chk_autoobs//k5ts4/ autoobs is running! 2006.285.17:58:29.59/chk_obsdata//k5ts1/T2851757??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.17:58:30.25/chk_obsdata//k5ts2/T2851757??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.17:58:30.64/chk_obsdata//k5ts3/T2851757??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.17:58:31.14/chk_obsdata//k5ts4/T2851757??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.17:58:31.98/k5log//k5ts1_log_newline 2006.285.17:58:32.66/k5log//k5ts2_log_newline 2006.285.17:58:33.39/k5log//k5ts3_log_newline 2006.285.17:58:34.30/k5log//k5ts4_log_newline 2006.285.17:58:34.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.17:58:34.32:setupk4=1 2006.285.17:58:34.32$setupk4/echo=on 2006.285.17:58:34.32$setupk4/pcalon 2006.285.17:58:34.32$pcalon/"no phase cal control is implemented here 2006.285.17:58:34.32$setupk4/"tpicd=stop 2006.285.17:58:34.32$setupk4/"rec=synch_on 2006.285.17:58:34.32$setupk4/"rec_mode=128 2006.285.17:58:34.32$setupk4/!* 2006.285.17:58:34.32$setupk4/recpk4 2006.285.17:58:34.32$recpk4/recpatch= 2006.285.17:58:34.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.17:58:34.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.17:58:34.32$setupk4/vck44 2006.285.17:58:34.32$vck44/valo=1,524.99 2006.285.17:58:34.32#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.17:58:34.32#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.17:58:34.32#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:34.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:58:34.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:58:34.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:58:34.32#ibcon#enter wrdev, iclass 13, count 0 2006.285.17:58:34.32#ibcon#first serial, iclass 13, count 0 2006.285.17:58:34.32#ibcon#enter sib2, iclass 13, count 0 2006.285.17:58:34.32#ibcon#flushed, iclass 13, count 0 2006.285.17:58:34.32#ibcon#about to write, iclass 13, count 0 2006.285.17:58:34.32#ibcon#wrote, iclass 13, count 0 2006.285.17:58:34.32#ibcon#about to read 3, iclass 13, count 0 2006.285.17:58:34.34#ibcon#read 3, iclass 13, count 0 2006.285.17:58:34.34#ibcon#about to read 4, iclass 13, count 0 2006.285.17:58:34.34#ibcon#read 4, iclass 13, count 0 2006.285.17:58:34.34#ibcon#about to read 5, iclass 13, count 0 2006.285.17:58:34.34#ibcon#read 5, iclass 13, count 0 2006.285.17:58:34.34#ibcon#about to read 6, iclass 13, count 0 2006.285.17:58:34.34#ibcon#read 6, iclass 13, count 0 2006.285.17:58:34.34#ibcon#end of sib2, iclass 13, count 0 2006.285.17:58:34.34#ibcon#*mode == 0, iclass 13, count 0 2006.285.17:58:34.34#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.17:58:34.34#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.17:58:34.34#ibcon#*before write, iclass 13, count 0 2006.285.17:58:34.34#ibcon#enter sib2, iclass 13, count 0 2006.285.17:58:34.34#ibcon#flushed, iclass 13, count 0 2006.285.17:58:34.34#ibcon#about to write, iclass 13, count 0 2006.285.17:58:34.34#ibcon#wrote, iclass 13, count 0 2006.285.17:58:34.34#ibcon#about to read 3, iclass 13, count 0 2006.285.17:58:34.39#ibcon#read 3, iclass 13, count 0 2006.285.17:58:34.39#ibcon#about to read 4, iclass 13, count 0 2006.285.17:58:34.39#ibcon#read 4, iclass 13, count 0 2006.285.17:58:34.39#ibcon#about to read 5, iclass 13, count 0 2006.285.17:58:34.39#ibcon#read 5, iclass 13, count 0 2006.285.17:58:34.39#ibcon#about to read 6, iclass 13, count 0 2006.285.17:58:34.39#ibcon#read 6, iclass 13, count 0 2006.285.17:58:34.39#ibcon#end of sib2, iclass 13, count 0 2006.285.17:58:34.39#ibcon#*after write, iclass 13, count 0 2006.285.17:58:34.39#ibcon#*before return 0, iclass 13, count 0 2006.285.17:58:34.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:58:34.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:58:34.39#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.17:58:34.39#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.17:58:34.39$vck44/va=1,7 2006.285.17:58:34.39#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.17:58:34.39#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.17:58:34.39#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:34.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:58:34.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:58:34.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:58:34.39#ibcon#enter wrdev, iclass 15, count 2 2006.285.17:58:34.39#ibcon#first serial, iclass 15, count 2 2006.285.17:58:34.39#ibcon#enter sib2, iclass 15, count 2 2006.285.17:58:34.39#ibcon#flushed, iclass 15, count 2 2006.285.17:58:34.39#ibcon#about to write, iclass 15, count 2 2006.285.17:58:34.39#ibcon#wrote, iclass 15, count 2 2006.285.17:58:34.39#ibcon#about to read 3, iclass 15, count 2 2006.285.17:58:34.41#ibcon#read 3, iclass 15, count 2 2006.285.17:58:34.41#ibcon#about to read 4, iclass 15, count 2 2006.285.17:58:34.41#ibcon#read 4, iclass 15, count 2 2006.285.17:58:34.41#ibcon#about to read 5, iclass 15, count 2 2006.285.17:58:34.41#ibcon#read 5, iclass 15, count 2 2006.285.17:58:34.41#ibcon#about to read 6, iclass 15, count 2 2006.285.17:58:34.41#ibcon#read 6, iclass 15, count 2 2006.285.17:58:34.41#ibcon#end of sib2, iclass 15, count 2 2006.285.17:58:34.41#ibcon#*mode == 0, iclass 15, count 2 2006.285.17:58:34.41#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.17:58:34.41#ibcon#[25=AT01-07\r\n] 2006.285.17:58:34.41#ibcon#*before write, iclass 15, count 2 2006.285.17:58:34.41#ibcon#enter sib2, iclass 15, count 2 2006.285.17:58:34.41#ibcon#flushed, iclass 15, count 2 2006.285.17:58:34.41#ibcon#about to write, iclass 15, count 2 2006.285.17:58:34.41#ibcon#wrote, iclass 15, count 2 2006.285.17:58:34.41#ibcon#about to read 3, iclass 15, count 2 2006.285.17:58:34.44#ibcon#read 3, iclass 15, count 2 2006.285.17:58:34.44#ibcon#about to read 4, iclass 15, count 2 2006.285.17:58:34.44#ibcon#read 4, iclass 15, count 2 2006.285.17:58:34.44#ibcon#about to read 5, iclass 15, count 2 2006.285.17:58:34.44#ibcon#read 5, iclass 15, count 2 2006.285.17:58:34.44#ibcon#about to read 6, iclass 15, count 2 2006.285.17:58:34.44#ibcon#read 6, iclass 15, count 2 2006.285.17:58:34.44#ibcon#end of sib2, iclass 15, count 2 2006.285.17:58:34.44#ibcon#*after write, iclass 15, count 2 2006.285.17:58:34.44#ibcon#*before return 0, iclass 15, count 2 2006.285.17:58:34.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:58:34.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:58:34.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.17:58:34.44#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:34.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:58:34.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:58:34.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:58:34.56#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:58:34.56#ibcon#first serial, iclass 15, count 0 2006.285.17:58:34.56#ibcon#enter sib2, iclass 15, count 0 2006.285.17:58:34.56#ibcon#flushed, iclass 15, count 0 2006.285.17:58:34.56#ibcon#about to write, iclass 15, count 0 2006.285.17:58:34.56#ibcon#wrote, iclass 15, count 0 2006.285.17:58:34.56#ibcon#about to read 3, iclass 15, count 0 2006.285.17:58:34.58#ibcon#read 3, iclass 15, count 0 2006.285.17:58:34.58#ibcon#about to read 4, iclass 15, count 0 2006.285.17:58:34.58#ibcon#read 4, iclass 15, count 0 2006.285.17:58:34.58#ibcon#about to read 5, iclass 15, count 0 2006.285.17:58:34.58#ibcon#read 5, iclass 15, count 0 2006.285.17:58:34.58#ibcon#about to read 6, iclass 15, count 0 2006.285.17:58:34.58#ibcon#read 6, iclass 15, count 0 2006.285.17:58:34.58#ibcon#end of sib2, iclass 15, count 0 2006.285.17:58:34.58#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:58:34.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:58:34.58#ibcon#[25=USB\r\n] 2006.285.17:58:34.58#ibcon#*before write, iclass 15, count 0 2006.285.17:58:34.58#ibcon#enter sib2, iclass 15, count 0 2006.285.17:58:34.58#ibcon#flushed, iclass 15, count 0 2006.285.17:58:34.58#ibcon#about to write, iclass 15, count 0 2006.285.17:58:34.58#ibcon#wrote, iclass 15, count 0 2006.285.17:58:34.58#ibcon#about to read 3, iclass 15, count 0 2006.285.17:58:34.61#ibcon#read 3, iclass 15, count 0 2006.285.17:58:34.61#ibcon#about to read 4, iclass 15, count 0 2006.285.17:58:34.61#ibcon#read 4, iclass 15, count 0 2006.285.17:58:34.61#ibcon#about to read 5, iclass 15, count 0 2006.285.17:58:34.61#ibcon#read 5, iclass 15, count 0 2006.285.17:58:34.61#ibcon#about to read 6, iclass 15, count 0 2006.285.17:58:34.61#ibcon#read 6, iclass 15, count 0 2006.285.17:58:34.61#ibcon#end of sib2, iclass 15, count 0 2006.285.17:58:34.61#ibcon#*after write, iclass 15, count 0 2006.285.17:58:34.61#ibcon#*before return 0, iclass 15, count 0 2006.285.17:58:34.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:58:34.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:58:34.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:58:34.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:58:34.61$vck44/valo=2,534.99 2006.285.17:58:34.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.17:58:34.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.17:58:34.61#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:34.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:58:34.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:58:34.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:58:34.61#ibcon#enter wrdev, iclass 17, count 0 2006.285.17:58:34.61#ibcon#first serial, iclass 17, count 0 2006.285.17:58:34.61#ibcon#enter sib2, iclass 17, count 0 2006.285.17:58:34.61#ibcon#flushed, iclass 17, count 0 2006.285.17:58:34.61#ibcon#about to write, iclass 17, count 0 2006.285.17:58:34.61#ibcon#wrote, iclass 17, count 0 2006.285.17:58:34.61#ibcon#about to read 3, iclass 17, count 0 2006.285.17:58:34.63#ibcon#read 3, iclass 17, count 0 2006.285.17:58:34.63#ibcon#about to read 4, iclass 17, count 0 2006.285.17:58:34.63#ibcon#read 4, iclass 17, count 0 2006.285.17:58:34.63#ibcon#about to read 5, iclass 17, count 0 2006.285.17:58:34.63#ibcon#read 5, iclass 17, count 0 2006.285.17:58:34.63#ibcon#about to read 6, iclass 17, count 0 2006.285.17:58:34.63#ibcon#read 6, iclass 17, count 0 2006.285.17:58:34.63#ibcon#end of sib2, iclass 17, count 0 2006.285.17:58:34.63#ibcon#*mode == 0, iclass 17, count 0 2006.285.17:58:34.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.17:58:34.63#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.17:58:34.63#ibcon#*before write, iclass 17, count 0 2006.285.17:58:34.63#ibcon#enter sib2, iclass 17, count 0 2006.285.17:58:34.63#ibcon#flushed, iclass 17, count 0 2006.285.17:58:34.63#ibcon#about to write, iclass 17, count 0 2006.285.17:58:34.63#ibcon#wrote, iclass 17, count 0 2006.285.17:58:34.63#ibcon#about to read 3, iclass 17, count 0 2006.285.17:58:34.67#ibcon#read 3, iclass 17, count 0 2006.285.17:58:34.67#ibcon#about to read 4, iclass 17, count 0 2006.285.17:58:34.67#ibcon#read 4, iclass 17, count 0 2006.285.17:58:34.67#ibcon#about to read 5, iclass 17, count 0 2006.285.17:58:34.67#ibcon#read 5, iclass 17, count 0 2006.285.17:58:34.67#ibcon#about to read 6, iclass 17, count 0 2006.285.17:58:34.67#ibcon#read 6, iclass 17, count 0 2006.285.17:58:34.67#ibcon#end of sib2, iclass 17, count 0 2006.285.17:58:34.67#ibcon#*after write, iclass 17, count 0 2006.285.17:58:34.67#ibcon#*before return 0, iclass 17, count 0 2006.285.17:58:34.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:58:34.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:58:34.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.17:58:34.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.17:58:34.67$vck44/va=2,6 2006.285.17:58:34.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.17:58:34.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.17:58:34.67#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:34.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:58:34.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:58:34.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:58:34.73#ibcon#enter wrdev, iclass 19, count 2 2006.285.17:58:34.73#ibcon#first serial, iclass 19, count 2 2006.285.17:58:34.73#ibcon#enter sib2, iclass 19, count 2 2006.285.17:58:34.73#ibcon#flushed, iclass 19, count 2 2006.285.17:58:34.73#ibcon#about to write, iclass 19, count 2 2006.285.17:58:34.73#ibcon#wrote, iclass 19, count 2 2006.285.17:58:34.73#ibcon#about to read 3, iclass 19, count 2 2006.285.17:58:34.75#ibcon#read 3, iclass 19, count 2 2006.285.17:58:34.75#ibcon#about to read 4, iclass 19, count 2 2006.285.17:58:34.75#ibcon#read 4, iclass 19, count 2 2006.285.17:58:34.75#ibcon#about to read 5, iclass 19, count 2 2006.285.17:58:34.75#ibcon#read 5, iclass 19, count 2 2006.285.17:58:34.75#ibcon#about to read 6, iclass 19, count 2 2006.285.17:58:34.75#ibcon#read 6, iclass 19, count 2 2006.285.17:58:34.75#ibcon#end of sib2, iclass 19, count 2 2006.285.17:58:34.75#ibcon#*mode == 0, iclass 19, count 2 2006.285.17:58:34.75#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.17:58:34.75#ibcon#[25=AT02-06\r\n] 2006.285.17:58:34.75#ibcon#*before write, iclass 19, count 2 2006.285.17:58:34.75#ibcon#enter sib2, iclass 19, count 2 2006.285.17:58:34.75#ibcon#flushed, iclass 19, count 2 2006.285.17:58:34.75#ibcon#about to write, iclass 19, count 2 2006.285.17:58:34.75#ibcon#wrote, iclass 19, count 2 2006.285.17:58:34.75#ibcon#about to read 3, iclass 19, count 2 2006.285.17:58:34.78#ibcon#read 3, iclass 19, count 2 2006.285.17:58:34.78#ibcon#about to read 4, iclass 19, count 2 2006.285.17:58:34.78#ibcon#read 4, iclass 19, count 2 2006.285.17:58:34.78#ibcon#about to read 5, iclass 19, count 2 2006.285.17:58:34.78#ibcon#read 5, iclass 19, count 2 2006.285.17:58:34.78#ibcon#about to read 6, iclass 19, count 2 2006.285.17:58:34.78#ibcon#read 6, iclass 19, count 2 2006.285.17:58:34.78#ibcon#end of sib2, iclass 19, count 2 2006.285.17:58:34.78#ibcon#*after write, iclass 19, count 2 2006.285.17:58:34.78#ibcon#*before return 0, iclass 19, count 2 2006.285.17:58:34.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:58:34.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:58:34.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.17:58:34.78#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:34.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:58:34.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:58:34.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:58:34.90#ibcon#enter wrdev, iclass 19, count 0 2006.285.17:58:34.90#ibcon#first serial, iclass 19, count 0 2006.285.17:58:34.90#ibcon#enter sib2, iclass 19, count 0 2006.285.17:58:34.90#ibcon#flushed, iclass 19, count 0 2006.285.17:58:34.90#ibcon#about to write, iclass 19, count 0 2006.285.17:58:34.90#ibcon#wrote, iclass 19, count 0 2006.285.17:58:34.90#ibcon#about to read 3, iclass 19, count 0 2006.285.17:58:34.92#ibcon#read 3, iclass 19, count 0 2006.285.17:58:34.92#ibcon#about to read 4, iclass 19, count 0 2006.285.17:58:34.92#ibcon#read 4, iclass 19, count 0 2006.285.17:58:34.92#ibcon#about to read 5, iclass 19, count 0 2006.285.17:58:34.92#ibcon#read 5, iclass 19, count 0 2006.285.17:58:34.92#ibcon#about to read 6, iclass 19, count 0 2006.285.17:58:34.92#ibcon#read 6, iclass 19, count 0 2006.285.17:58:34.92#ibcon#end of sib2, iclass 19, count 0 2006.285.17:58:34.92#ibcon#*mode == 0, iclass 19, count 0 2006.285.17:58:34.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.17:58:34.92#ibcon#[25=USB\r\n] 2006.285.17:58:34.92#ibcon#*before write, iclass 19, count 0 2006.285.17:58:34.92#ibcon#enter sib2, iclass 19, count 0 2006.285.17:58:34.92#ibcon#flushed, iclass 19, count 0 2006.285.17:58:34.92#ibcon#about to write, iclass 19, count 0 2006.285.17:58:34.92#ibcon#wrote, iclass 19, count 0 2006.285.17:58:34.92#ibcon#about to read 3, iclass 19, count 0 2006.285.17:58:34.95#ibcon#read 3, iclass 19, count 0 2006.285.17:58:35.15#ibcon#about to read 4, iclass 19, count 0 2006.285.17:58:35.15#ibcon#read 4, iclass 19, count 0 2006.285.17:58:35.15#ibcon#about to read 5, iclass 19, count 0 2006.285.17:58:35.15#ibcon#read 5, iclass 19, count 0 2006.285.17:58:35.15#ibcon#about to read 6, iclass 19, count 0 2006.285.17:58:35.15#ibcon#read 6, iclass 19, count 0 2006.285.17:58:35.15#ibcon#end of sib2, iclass 19, count 0 2006.285.17:58:35.15#ibcon#*after write, iclass 19, count 0 2006.285.17:58:35.15#ibcon#*before return 0, iclass 19, count 0 2006.285.17:58:35.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:58:35.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:58:35.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.17:58:35.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.17:58:35.15$vck44/valo=3,564.99 2006.285.17:58:35.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.17:58:35.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.17:58:35.15#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:35.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:58:35.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:58:35.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:58:35.15#ibcon#enter wrdev, iclass 21, count 0 2006.285.17:58:35.15#ibcon#first serial, iclass 21, count 0 2006.285.17:58:35.15#ibcon#enter sib2, iclass 21, count 0 2006.285.17:58:35.15#ibcon#flushed, iclass 21, count 0 2006.285.17:58:35.15#ibcon#about to write, iclass 21, count 0 2006.285.17:58:35.15#ibcon#wrote, iclass 21, count 0 2006.285.17:58:35.15#ibcon#about to read 3, iclass 21, count 0 2006.285.17:58:35.17#ibcon#read 3, iclass 21, count 0 2006.285.17:58:35.17#ibcon#about to read 4, iclass 21, count 0 2006.285.17:58:35.17#ibcon#read 4, iclass 21, count 0 2006.285.17:58:35.17#ibcon#about to read 5, iclass 21, count 0 2006.285.17:58:35.17#ibcon#read 5, iclass 21, count 0 2006.285.17:58:35.17#ibcon#about to read 6, iclass 21, count 0 2006.285.17:58:35.17#ibcon#read 6, iclass 21, count 0 2006.285.17:58:35.17#ibcon#end of sib2, iclass 21, count 0 2006.285.17:58:35.17#ibcon#*mode == 0, iclass 21, count 0 2006.285.17:58:35.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.17:58:35.17#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.17:58:35.17#ibcon#*before write, iclass 21, count 0 2006.285.17:58:35.17#ibcon#enter sib2, iclass 21, count 0 2006.285.17:58:35.17#ibcon#flushed, iclass 21, count 0 2006.285.17:58:35.17#ibcon#about to write, iclass 21, count 0 2006.285.17:58:35.17#ibcon#wrote, iclass 21, count 0 2006.285.17:58:35.17#ibcon#about to read 3, iclass 21, count 0 2006.285.17:58:35.21#ibcon#read 3, iclass 21, count 0 2006.285.17:58:35.21#ibcon#about to read 4, iclass 21, count 0 2006.285.17:58:35.21#ibcon#read 4, iclass 21, count 0 2006.285.17:58:35.21#ibcon#about to read 5, iclass 21, count 0 2006.285.17:58:35.21#ibcon#read 5, iclass 21, count 0 2006.285.17:58:35.21#ibcon#about to read 6, iclass 21, count 0 2006.285.17:58:35.21#ibcon#read 6, iclass 21, count 0 2006.285.17:58:35.21#ibcon#end of sib2, iclass 21, count 0 2006.285.17:58:35.21#ibcon#*after write, iclass 21, count 0 2006.285.17:58:35.21#ibcon#*before return 0, iclass 21, count 0 2006.285.17:58:35.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:58:35.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:58:35.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.17:58:35.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.17:58:35.21$vck44/va=3,7 2006.285.17:58:35.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.17:58:35.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.17:58:35.21#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:35.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:58:35.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:58:35.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:58:35.27#ibcon#enter wrdev, iclass 23, count 2 2006.285.17:58:35.27#ibcon#first serial, iclass 23, count 2 2006.285.17:58:35.27#ibcon#enter sib2, iclass 23, count 2 2006.285.17:58:35.27#ibcon#flushed, iclass 23, count 2 2006.285.17:58:35.27#ibcon#about to write, iclass 23, count 2 2006.285.17:58:35.27#ibcon#wrote, iclass 23, count 2 2006.285.17:58:35.27#ibcon#about to read 3, iclass 23, count 2 2006.285.17:58:35.29#ibcon#read 3, iclass 23, count 2 2006.285.17:58:35.29#ibcon#about to read 4, iclass 23, count 2 2006.285.17:58:35.29#ibcon#read 4, iclass 23, count 2 2006.285.17:58:35.29#ibcon#about to read 5, iclass 23, count 2 2006.285.17:58:35.29#ibcon#read 5, iclass 23, count 2 2006.285.17:58:35.29#ibcon#about to read 6, iclass 23, count 2 2006.285.17:58:35.29#ibcon#read 6, iclass 23, count 2 2006.285.17:58:35.29#ibcon#end of sib2, iclass 23, count 2 2006.285.17:58:35.29#ibcon#*mode == 0, iclass 23, count 2 2006.285.17:58:35.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.17:58:35.29#ibcon#[25=AT03-07\r\n] 2006.285.17:58:35.29#ibcon#*before write, iclass 23, count 2 2006.285.17:58:35.29#ibcon#enter sib2, iclass 23, count 2 2006.285.17:58:35.29#ibcon#flushed, iclass 23, count 2 2006.285.17:58:35.29#ibcon#about to write, iclass 23, count 2 2006.285.17:58:35.29#ibcon#wrote, iclass 23, count 2 2006.285.17:58:35.29#ibcon#about to read 3, iclass 23, count 2 2006.285.17:58:35.32#ibcon#read 3, iclass 23, count 2 2006.285.17:58:35.32#ibcon#about to read 4, iclass 23, count 2 2006.285.17:58:35.32#ibcon#read 4, iclass 23, count 2 2006.285.17:58:35.32#ibcon#about to read 5, iclass 23, count 2 2006.285.17:58:35.32#ibcon#read 5, iclass 23, count 2 2006.285.17:58:35.32#ibcon#about to read 6, iclass 23, count 2 2006.285.17:58:35.32#ibcon#read 6, iclass 23, count 2 2006.285.17:58:35.32#ibcon#end of sib2, iclass 23, count 2 2006.285.17:58:35.32#ibcon#*after write, iclass 23, count 2 2006.285.17:58:35.32#ibcon#*before return 0, iclass 23, count 2 2006.285.17:58:35.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:58:35.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:58:35.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.17:58:35.32#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:35.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:58:35.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:58:35.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:58:35.44#ibcon#enter wrdev, iclass 23, count 0 2006.285.17:58:35.44#ibcon#first serial, iclass 23, count 0 2006.285.17:58:35.44#ibcon#enter sib2, iclass 23, count 0 2006.285.17:58:35.44#ibcon#flushed, iclass 23, count 0 2006.285.17:58:35.44#ibcon#about to write, iclass 23, count 0 2006.285.17:58:35.44#ibcon#wrote, iclass 23, count 0 2006.285.17:58:35.44#ibcon#about to read 3, iclass 23, count 0 2006.285.17:58:35.46#ibcon#read 3, iclass 23, count 0 2006.285.17:58:35.46#ibcon#about to read 4, iclass 23, count 0 2006.285.17:58:35.46#ibcon#read 4, iclass 23, count 0 2006.285.17:58:35.46#ibcon#about to read 5, iclass 23, count 0 2006.285.17:58:35.46#ibcon#read 5, iclass 23, count 0 2006.285.17:58:35.46#ibcon#about to read 6, iclass 23, count 0 2006.285.17:58:35.46#ibcon#read 6, iclass 23, count 0 2006.285.17:58:35.46#ibcon#end of sib2, iclass 23, count 0 2006.285.17:58:35.46#ibcon#*mode == 0, iclass 23, count 0 2006.285.17:58:35.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.17:58:35.46#ibcon#[25=USB\r\n] 2006.285.17:58:35.46#ibcon#*before write, iclass 23, count 0 2006.285.17:58:35.46#ibcon#enter sib2, iclass 23, count 0 2006.285.17:58:35.46#ibcon#flushed, iclass 23, count 0 2006.285.17:58:35.46#ibcon#about to write, iclass 23, count 0 2006.285.17:58:35.46#ibcon#wrote, iclass 23, count 0 2006.285.17:58:35.46#ibcon#about to read 3, iclass 23, count 0 2006.285.17:58:35.49#ibcon#read 3, iclass 23, count 0 2006.285.17:58:35.49#ibcon#about to read 4, iclass 23, count 0 2006.285.17:58:35.49#ibcon#read 4, iclass 23, count 0 2006.285.17:58:35.49#ibcon#about to read 5, iclass 23, count 0 2006.285.17:58:35.49#ibcon#read 5, iclass 23, count 0 2006.285.17:58:35.49#ibcon#about to read 6, iclass 23, count 0 2006.285.17:58:35.49#ibcon#read 6, iclass 23, count 0 2006.285.17:58:35.49#ibcon#end of sib2, iclass 23, count 0 2006.285.17:58:35.49#ibcon#*after write, iclass 23, count 0 2006.285.17:58:35.49#ibcon#*before return 0, iclass 23, count 0 2006.285.17:58:35.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:58:35.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:58:35.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.17:58:35.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.17:58:35.49$vck44/valo=4,624.99 2006.285.17:58:35.66#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.17:58:35.66#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.17:58:35.66#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:35.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:58:35.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:58:35.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:58:35.66#ibcon#enter wrdev, iclass 25, count 0 2006.285.17:58:35.66#ibcon#first serial, iclass 25, count 0 2006.285.17:58:35.66#ibcon#enter sib2, iclass 25, count 0 2006.285.17:58:35.66#ibcon#flushed, iclass 25, count 0 2006.285.17:58:35.66#ibcon#about to write, iclass 25, count 0 2006.285.17:58:35.66#ibcon#wrote, iclass 25, count 0 2006.285.17:58:35.66#ibcon#about to read 3, iclass 25, count 0 2006.285.17:58:35.67#ibcon#read 3, iclass 25, count 0 2006.285.17:58:35.67#ibcon#about to read 4, iclass 25, count 0 2006.285.17:58:35.67#ibcon#read 4, iclass 25, count 0 2006.285.17:58:35.67#ibcon#about to read 5, iclass 25, count 0 2006.285.17:58:35.67#ibcon#read 5, iclass 25, count 0 2006.285.17:58:35.67#ibcon#about to read 6, iclass 25, count 0 2006.285.17:58:35.67#ibcon#read 6, iclass 25, count 0 2006.285.17:58:35.67#ibcon#end of sib2, iclass 25, count 0 2006.285.17:58:35.67#ibcon#*mode == 0, iclass 25, count 0 2006.285.17:58:35.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.17:58:35.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.17:58:35.67#ibcon#*before write, iclass 25, count 0 2006.285.17:58:35.67#ibcon#enter sib2, iclass 25, count 0 2006.285.17:58:35.67#ibcon#flushed, iclass 25, count 0 2006.285.17:58:35.67#ibcon#about to write, iclass 25, count 0 2006.285.17:58:35.67#ibcon#wrote, iclass 25, count 0 2006.285.17:58:35.67#ibcon#about to read 3, iclass 25, count 0 2006.285.17:58:35.71#ibcon#read 3, iclass 25, count 0 2006.285.17:58:35.71#ibcon#about to read 4, iclass 25, count 0 2006.285.17:58:35.71#ibcon#read 4, iclass 25, count 0 2006.285.17:58:35.71#ibcon#about to read 5, iclass 25, count 0 2006.285.17:58:35.71#ibcon#read 5, iclass 25, count 0 2006.285.17:58:35.71#ibcon#about to read 6, iclass 25, count 0 2006.285.17:58:35.71#ibcon#read 6, iclass 25, count 0 2006.285.17:58:35.71#ibcon#end of sib2, iclass 25, count 0 2006.285.17:58:35.71#ibcon#*after write, iclass 25, count 0 2006.285.17:58:35.71#ibcon#*before return 0, iclass 25, count 0 2006.285.17:58:35.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:58:35.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:58:35.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.17:58:35.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.17:58:35.71$vck44/va=4,6 2006.285.17:58:35.71#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.17:58:35.71#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.17:58:35.71#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:35.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:58:35.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:58:35.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:58:35.71#ibcon#enter wrdev, iclass 27, count 2 2006.285.17:58:35.71#ibcon#first serial, iclass 27, count 2 2006.285.17:58:35.71#ibcon#enter sib2, iclass 27, count 2 2006.285.17:58:35.71#ibcon#flushed, iclass 27, count 2 2006.285.17:58:35.71#ibcon#about to write, iclass 27, count 2 2006.285.17:58:35.71#ibcon#wrote, iclass 27, count 2 2006.285.17:58:35.71#ibcon#about to read 3, iclass 27, count 2 2006.285.17:58:35.73#ibcon#read 3, iclass 27, count 2 2006.285.17:58:35.73#ibcon#about to read 4, iclass 27, count 2 2006.285.17:58:35.73#ibcon#read 4, iclass 27, count 2 2006.285.17:58:35.73#ibcon#about to read 5, iclass 27, count 2 2006.285.17:58:35.73#ibcon#read 5, iclass 27, count 2 2006.285.17:58:35.73#ibcon#about to read 6, iclass 27, count 2 2006.285.17:58:35.73#ibcon#read 6, iclass 27, count 2 2006.285.17:58:35.73#ibcon#end of sib2, iclass 27, count 2 2006.285.17:58:35.73#ibcon#*mode == 0, iclass 27, count 2 2006.285.17:58:35.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.17:58:35.73#ibcon#[25=AT04-06\r\n] 2006.285.17:58:35.73#ibcon#*before write, iclass 27, count 2 2006.285.17:58:35.73#ibcon#enter sib2, iclass 27, count 2 2006.285.17:58:35.73#ibcon#flushed, iclass 27, count 2 2006.285.17:58:35.73#ibcon#about to write, iclass 27, count 2 2006.285.17:58:35.73#ibcon#wrote, iclass 27, count 2 2006.285.17:58:35.73#ibcon#about to read 3, iclass 27, count 2 2006.285.17:58:35.76#ibcon#read 3, iclass 27, count 2 2006.285.17:58:35.76#ibcon#about to read 4, iclass 27, count 2 2006.285.17:58:35.76#ibcon#read 4, iclass 27, count 2 2006.285.17:58:35.76#ibcon#about to read 5, iclass 27, count 2 2006.285.17:58:35.76#ibcon#read 5, iclass 27, count 2 2006.285.17:58:35.76#ibcon#about to read 6, iclass 27, count 2 2006.285.17:58:35.76#ibcon#read 6, iclass 27, count 2 2006.285.17:58:35.76#ibcon#end of sib2, iclass 27, count 2 2006.285.17:58:35.76#ibcon#*after write, iclass 27, count 2 2006.285.17:58:35.76#ibcon#*before return 0, iclass 27, count 2 2006.285.17:58:35.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:58:35.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:58:35.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.17:58:35.76#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:35.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:58:35.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:58:35.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:58:35.88#ibcon#enter wrdev, iclass 27, count 0 2006.285.17:58:35.88#ibcon#first serial, iclass 27, count 0 2006.285.17:58:35.88#ibcon#enter sib2, iclass 27, count 0 2006.285.17:58:35.88#ibcon#flushed, iclass 27, count 0 2006.285.17:58:35.88#ibcon#about to write, iclass 27, count 0 2006.285.17:58:35.88#ibcon#wrote, iclass 27, count 0 2006.285.17:58:35.88#ibcon#about to read 3, iclass 27, count 0 2006.285.17:58:35.90#ibcon#read 3, iclass 27, count 0 2006.285.17:58:35.90#ibcon#about to read 4, iclass 27, count 0 2006.285.17:58:35.90#ibcon#read 4, iclass 27, count 0 2006.285.17:58:35.90#ibcon#about to read 5, iclass 27, count 0 2006.285.17:58:35.90#ibcon#read 5, iclass 27, count 0 2006.285.17:58:35.90#ibcon#about to read 6, iclass 27, count 0 2006.285.17:58:35.90#ibcon#read 6, iclass 27, count 0 2006.285.17:58:35.90#ibcon#end of sib2, iclass 27, count 0 2006.285.17:58:35.90#ibcon#*mode == 0, iclass 27, count 0 2006.285.17:58:35.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.17:58:35.90#ibcon#[25=USB\r\n] 2006.285.17:58:35.90#ibcon#*before write, iclass 27, count 0 2006.285.17:58:35.90#ibcon#enter sib2, iclass 27, count 0 2006.285.17:58:35.90#ibcon#flushed, iclass 27, count 0 2006.285.17:58:35.90#ibcon#about to write, iclass 27, count 0 2006.285.17:58:35.90#ibcon#wrote, iclass 27, count 0 2006.285.17:58:35.90#ibcon#about to read 3, iclass 27, count 0 2006.285.17:58:35.93#ibcon#read 3, iclass 27, count 0 2006.285.17:58:35.93#ibcon#about to read 4, iclass 27, count 0 2006.285.17:58:35.93#ibcon#read 4, iclass 27, count 0 2006.285.17:58:35.93#ibcon#about to read 5, iclass 27, count 0 2006.285.17:58:35.93#ibcon#read 5, iclass 27, count 0 2006.285.17:58:35.93#ibcon#about to read 6, iclass 27, count 0 2006.285.17:58:35.93#ibcon#read 6, iclass 27, count 0 2006.285.17:58:35.93#ibcon#end of sib2, iclass 27, count 0 2006.285.17:58:35.93#ibcon#*after write, iclass 27, count 0 2006.285.17:58:35.93#ibcon#*before return 0, iclass 27, count 0 2006.285.17:58:35.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:58:35.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:58:35.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.17:58:35.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.17:58:35.93$vck44/valo=5,734.99 2006.285.17:58:35.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.17:58:35.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.17:58:35.93#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:35.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:58:35.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:58:35.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:58:35.93#ibcon#enter wrdev, iclass 29, count 0 2006.285.17:58:35.93#ibcon#first serial, iclass 29, count 0 2006.285.17:58:35.93#ibcon#enter sib2, iclass 29, count 0 2006.285.17:58:35.93#ibcon#flushed, iclass 29, count 0 2006.285.17:58:35.93#ibcon#about to write, iclass 29, count 0 2006.285.17:58:35.93#ibcon#wrote, iclass 29, count 0 2006.285.17:58:35.93#ibcon#about to read 3, iclass 29, count 0 2006.285.17:58:35.95#ibcon#read 3, iclass 29, count 0 2006.285.17:58:36.02#ibcon#about to read 4, iclass 29, count 0 2006.285.17:58:36.02#ibcon#read 4, iclass 29, count 0 2006.285.17:58:36.02#ibcon#about to read 5, iclass 29, count 0 2006.285.17:58:36.02#ibcon#read 5, iclass 29, count 0 2006.285.17:58:36.02#ibcon#about to read 6, iclass 29, count 0 2006.285.17:58:36.02#ibcon#read 6, iclass 29, count 0 2006.285.17:58:36.02#ibcon#end of sib2, iclass 29, count 0 2006.285.17:58:36.02#ibcon#*mode == 0, iclass 29, count 0 2006.285.17:58:36.02#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.17:58:36.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.17:58:36.02#ibcon#*before write, iclass 29, count 0 2006.285.17:58:36.02#ibcon#enter sib2, iclass 29, count 0 2006.285.17:58:36.02#ibcon#flushed, iclass 29, count 0 2006.285.17:58:36.02#ibcon#about to write, iclass 29, count 0 2006.285.17:58:36.02#ibcon#wrote, iclass 29, count 0 2006.285.17:58:36.02#ibcon#about to read 3, iclass 29, count 0 2006.285.17:58:36.06#ibcon#read 3, iclass 29, count 0 2006.285.17:58:36.06#ibcon#about to read 4, iclass 29, count 0 2006.285.17:58:36.06#ibcon#read 4, iclass 29, count 0 2006.285.17:58:36.06#ibcon#about to read 5, iclass 29, count 0 2006.285.17:58:36.06#ibcon#read 5, iclass 29, count 0 2006.285.17:58:36.06#ibcon#about to read 6, iclass 29, count 0 2006.285.17:58:36.06#ibcon#read 6, iclass 29, count 0 2006.285.17:58:36.06#ibcon#end of sib2, iclass 29, count 0 2006.285.17:58:36.06#ibcon#*after write, iclass 29, count 0 2006.285.17:58:36.06#ibcon#*before return 0, iclass 29, count 0 2006.285.17:58:36.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:58:36.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:58:36.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.17:58:36.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.17:58:36.06$vck44/va=5,3 2006.285.17:58:36.06#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.17:58:36.06#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.17:58:36.06#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:36.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:58:36.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:58:36.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:58:36.06#ibcon#enter wrdev, iclass 31, count 2 2006.285.17:58:36.06#ibcon#first serial, iclass 31, count 2 2006.285.17:58:36.06#ibcon#enter sib2, iclass 31, count 2 2006.285.17:58:36.06#ibcon#flushed, iclass 31, count 2 2006.285.17:58:36.06#ibcon#about to write, iclass 31, count 2 2006.285.17:58:36.06#ibcon#wrote, iclass 31, count 2 2006.285.17:58:36.06#ibcon#about to read 3, iclass 31, count 2 2006.285.17:58:36.08#ibcon#read 3, iclass 31, count 2 2006.285.17:58:36.08#ibcon#about to read 4, iclass 31, count 2 2006.285.17:58:36.08#ibcon#read 4, iclass 31, count 2 2006.285.17:58:36.08#ibcon#about to read 5, iclass 31, count 2 2006.285.17:58:36.08#ibcon#read 5, iclass 31, count 2 2006.285.17:58:36.08#ibcon#about to read 6, iclass 31, count 2 2006.285.17:58:36.08#ibcon#read 6, iclass 31, count 2 2006.285.17:58:36.08#ibcon#end of sib2, iclass 31, count 2 2006.285.17:58:36.08#ibcon#*mode == 0, iclass 31, count 2 2006.285.17:58:36.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.17:58:36.08#ibcon#[25=AT05-03\r\n] 2006.285.17:58:36.08#ibcon#*before write, iclass 31, count 2 2006.285.17:58:36.08#ibcon#enter sib2, iclass 31, count 2 2006.285.17:58:36.08#ibcon#flushed, iclass 31, count 2 2006.285.17:58:36.08#ibcon#about to write, iclass 31, count 2 2006.285.17:58:36.08#ibcon#wrote, iclass 31, count 2 2006.285.17:58:36.08#ibcon#about to read 3, iclass 31, count 2 2006.285.17:58:36.11#ibcon#read 3, iclass 31, count 2 2006.285.17:58:36.11#ibcon#about to read 4, iclass 31, count 2 2006.285.17:58:36.11#ibcon#read 4, iclass 31, count 2 2006.285.17:58:36.11#ibcon#about to read 5, iclass 31, count 2 2006.285.17:58:36.11#ibcon#read 5, iclass 31, count 2 2006.285.17:58:36.11#ibcon#about to read 6, iclass 31, count 2 2006.285.17:58:36.11#ibcon#read 6, iclass 31, count 2 2006.285.17:58:36.11#ibcon#end of sib2, iclass 31, count 2 2006.285.17:58:36.11#ibcon#*after write, iclass 31, count 2 2006.285.17:58:36.11#ibcon#*before return 0, iclass 31, count 2 2006.285.17:58:36.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:58:36.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:58:36.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.17:58:36.11#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:36.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:58:36.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:58:36.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:58:36.23#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:58:36.23#ibcon#first serial, iclass 31, count 0 2006.285.17:58:36.23#ibcon#enter sib2, iclass 31, count 0 2006.285.17:58:36.23#ibcon#flushed, iclass 31, count 0 2006.285.17:58:36.23#ibcon#about to write, iclass 31, count 0 2006.285.17:58:36.23#ibcon#wrote, iclass 31, count 0 2006.285.17:58:36.23#ibcon#about to read 3, iclass 31, count 0 2006.285.17:58:36.25#ibcon#read 3, iclass 31, count 0 2006.285.17:58:36.25#ibcon#about to read 4, iclass 31, count 0 2006.285.17:58:36.25#ibcon#read 4, iclass 31, count 0 2006.285.17:58:36.25#ibcon#about to read 5, iclass 31, count 0 2006.285.17:58:36.25#ibcon#read 5, iclass 31, count 0 2006.285.17:58:36.25#ibcon#about to read 6, iclass 31, count 0 2006.285.17:58:36.25#ibcon#read 6, iclass 31, count 0 2006.285.17:58:36.25#ibcon#end of sib2, iclass 31, count 0 2006.285.17:58:36.25#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:58:36.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:58:36.25#ibcon#[25=USB\r\n] 2006.285.17:58:36.25#ibcon#*before write, iclass 31, count 0 2006.285.17:58:36.25#ibcon#enter sib2, iclass 31, count 0 2006.285.17:58:36.25#ibcon#flushed, iclass 31, count 0 2006.285.17:58:36.25#ibcon#about to write, iclass 31, count 0 2006.285.17:58:36.25#ibcon#wrote, iclass 31, count 0 2006.285.17:58:36.25#ibcon#about to read 3, iclass 31, count 0 2006.285.17:58:36.28#ibcon#read 3, iclass 31, count 0 2006.285.17:58:36.28#ibcon#about to read 4, iclass 31, count 0 2006.285.17:58:36.28#ibcon#read 4, iclass 31, count 0 2006.285.17:58:36.28#ibcon#about to read 5, iclass 31, count 0 2006.285.17:58:36.28#ibcon#read 5, iclass 31, count 0 2006.285.17:58:36.28#ibcon#about to read 6, iclass 31, count 0 2006.285.17:58:36.28#ibcon#read 6, iclass 31, count 0 2006.285.17:58:36.28#ibcon#end of sib2, iclass 31, count 0 2006.285.17:58:36.28#ibcon#*after write, iclass 31, count 0 2006.285.17:58:36.28#ibcon#*before return 0, iclass 31, count 0 2006.285.17:58:36.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:58:36.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:58:36.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:58:36.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:58:36.28$vck44/valo=6,814.99 2006.285.17:58:36.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.17:58:36.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.17:58:36.28#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:36.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:58:36.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:58:36.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:58:36.28#ibcon#enter wrdev, iclass 33, count 0 2006.285.17:58:36.28#ibcon#first serial, iclass 33, count 0 2006.285.17:58:36.28#ibcon#enter sib2, iclass 33, count 0 2006.285.17:58:36.28#ibcon#flushed, iclass 33, count 0 2006.285.17:58:36.28#ibcon#about to write, iclass 33, count 0 2006.285.17:58:36.28#ibcon#wrote, iclass 33, count 0 2006.285.17:58:36.28#ibcon#about to read 3, iclass 33, count 0 2006.285.17:58:36.30#ibcon#read 3, iclass 33, count 0 2006.285.17:58:36.30#ibcon#about to read 4, iclass 33, count 0 2006.285.17:58:36.30#ibcon#read 4, iclass 33, count 0 2006.285.17:58:36.30#ibcon#about to read 5, iclass 33, count 0 2006.285.17:58:36.30#ibcon#read 5, iclass 33, count 0 2006.285.17:58:36.30#ibcon#about to read 6, iclass 33, count 0 2006.285.17:58:36.30#ibcon#read 6, iclass 33, count 0 2006.285.17:58:36.30#ibcon#end of sib2, iclass 33, count 0 2006.285.17:58:36.30#ibcon#*mode == 0, iclass 33, count 0 2006.285.17:58:36.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.17:58:36.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.17:58:36.30#ibcon#*before write, iclass 33, count 0 2006.285.17:58:36.30#ibcon#enter sib2, iclass 33, count 0 2006.285.17:58:36.30#ibcon#flushed, iclass 33, count 0 2006.285.17:58:36.30#ibcon#about to write, iclass 33, count 0 2006.285.17:58:36.30#ibcon#wrote, iclass 33, count 0 2006.285.17:58:36.30#ibcon#about to read 3, iclass 33, count 0 2006.285.17:58:36.34#ibcon#read 3, iclass 33, count 0 2006.285.17:58:36.34#ibcon#about to read 4, iclass 33, count 0 2006.285.17:58:36.34#ibcon#read 4, iclass 33, count 0 2006.285.17:58:36.34#ibcon#about to read 5, iclass 33, count 0 2006.285.17:58:36.34#ibcon#read 5, iclass 33, count 0 2006.285.17:58:36.34#ibcon#about to read 6, iclass 33, count 0 2006.285.17:58:36.34#ibcon#read 6, iclass 33, count 0 2006.285.17:58:36.34#ibcon#end of sib2, iclass 33, count 0 2006.285.17:58:36.34#ibcon#*after write, iclass 33, count 0 2006.285.17:58:36.34#ibcon#*before return 0, iclass 33, count 0 2006.285.17:58:36.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:58:36.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:58:36.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.17:58:36.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.17:58:36.34$vck44/va=6,4 2006.285.17:58:36.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.17:58:36.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.17:58:36.34#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:36.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:58:36.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:58:36.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:58:36.40#ibcon#enter wrdev, iclass 35, count 2 2006.285.17:58:36.40#ibcon#first serial, iclass 35, count 2 2006.285.17:58:36.40#ibcon#enter sib2, iclass 35, count 2 2006.285.17:58:36.40#ibcon#flushed, iclass 35, count 2 2006.285.17:58:36.40#ibcon#about to write, iclass 35, count 2 2006.285.17:58:36.40#ibcon#wrote, iclass 35, count 2 2006.285.17:58:36.40#ibcon#about to read 3, iclass 35, count 2 2006.285.17:58:36.42#ibcon#read 3, iclass 35, count 2 2006.285.17:58:36.42#ibcon#about to read 4, iclass 35, count 2 2006.285.17:58:36.42#ibcon#read 4, iclass 35, count 2 2006.285.17:58:36.42#ibcon#about to read 5, iclass 35, count 2 2006.285.17:58:36.42#ibcon#read 5, iclass 35, count 2 2006.285.17:58:36.42#ibcon#about to read 6, iclass 35, count 2 2006.285.17:58:36.42#ibcon#read 6, iclass 35, count 2 2006.285.17:58:36.42#ibcon#end of sib2, iclass 35, count 2 2006.285.17:58:36.42#ibcon#*mode == 0, iclass 35, count 2 2006.285.17:58:36.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.17:58:36.42#ibcon#[25=AT06-04\r\n] 2006.285.17:58:36.42#ibcon#*before write, iclass 35, count 2 2006.285.17:58:36.42#ibcon#enter sib2, iclass 35, count 2 2006.285.17:58:36.42#ibcon#flushed, iclass 35, count 2 2006.285.17:58:36.42#ibcon#about to write, iclass 35, count 2 2006.285.17:58:36.42#ibcon#wrote, iclass 35, count 2 2006.285.17:58:36.42#ibcon#about to read 3, iclass 35, count 2 2006.285.17:58:36.45#ibcon#read 3, iclass 35, count 2 2006.285.17:58:36.45#ibcon#about to read 4, iclass 35, count 2 2006.285.17:58:36.45#ibcon#read 4, iclass 35, count 2 2006.285.17:58:36.45#ibcon#about to read 5, iclass 35, count 2 2006.285.17:58:36.45#ibcon#read 5, iclass 35, count 2 2006.285.17:58:36.45#ibcon#about to read 6, iclass 35, count 2 2006.285.17:58:36.45#ibcon#read 6, iclass 35, count 2 2006.285.17:58:36.45#ibcon#end of sib2, iclass 35, count 2 2006.285.17:58:36.45#ibcon#*after write, iclass 35, count 2 2006.285.17:58:36.45#ibcon#*before return 0, iclass 35, count 2 2006.285.17:58:36.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:58:36.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:58:36.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.17:58:36.45#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:36.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:58:36.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:58:36.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:58:36.57#ibcon#enter wrdev, iclass 35, count 0 2006.285.17:58:36.57#ibcon#first serial, iclass 35, count 0 2006.285.17:58:36.57#ibcon#enter sib2, iclass 35, count 0 2006.285.17:58:36.57#ibcon#flushed, iclass 35, count 0 2006.285.17:58:36.57#ibcon#about to write, iclass 35, count 0 2006.285.17:58:36.57#ibcon#wrote, iclass 35, count 0 2006.285.17:58:36.57#ibcon#about to read 3, iclass 35, count 0 2006.285.17:58:36.59#ibcon#read 3, iclass 35, count 0 2006.285.17:58:36.59#ibcon#about to read 4, iclass 35, count 0 2006.285.17:58:36.59#ibcon#read 4, iclass 35, count 0 2006.285.17:58:36.59#ibcon#about to read 5, iclass 35, count 0 2006.285.17:58:36.59#ibcon#read 5, iclass 35, count 0 2006.285.17:58:36.59#ibcon#about to read 6, iclass 35, count 0 2006.285.17:58:36.59#ibcon#read 6, iclass 35, count 0 2006.285.17:58:36.59#ibcon#end of sib2, iclass 35, count 0 2006.285.17:58:36.59#ibcon#*mode == 0, iclass 35, count 0 2006.285.17:58:36.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.17:58:36.59#ibcon#[25=USB\r\n] 2006.285.17:58:36.59#ibcon#*before write, iclass 35, count 0 2006.285.17:58:36.59#ibcon#enter sib2, iclass 35, count 0 2006.285.17:58:36.59#ibcon#flushed, iclass 35, count 0 2006.285.17:58:36.59#ibcon#about to write, iclass 35, count 0 2006.285.17:58:36.59#ibcon#wrote, iclass 35, count 0 2006.285.17:58:36.59#ibcon#about to read 3, iclass 35, count 0 2006.285.17:58:36.62#ibcon#read 3, iclass 35, count 0 2006.285.17:58:36.62#ibcon#about to read 4, iclass 35, count 0 2006.285.17:58:36.62#ibcon#read 4, iclass 35, count 0 2006.285.17:58:36.62#ibcon#about to read 5, iclass 35, count 0 2006.285.17:58:36.62#ibcon#read 5, iclass 35, count 0 2006.285.17:58:36.62#ibcon#about to read 6, iclass 35, count 0 2006.285.17:58:36.62#ibcon#read 6, iclass 35, count 0 2006.285.17:58:36.62#ibcon#end of sib2, iclass 35, count 0 2006.285.17:58:36.62#ibcon#*after write, iclass 35, count 0 2006.285.17:58:36.62#ibcon#*before return 0, iclass 35, count 0 2006.285.17:58:36.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:58:36.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:58:36.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.17:58:36.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.17:58:36.62$vck44/valo=7,864.99 2006.285.17:58:36.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.17:58:36.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.17:58:36.62#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:36.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:58:36.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:58:36.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:58:36.62#ibcon#enter wrdev, iclass 37, count 0 2006.285.17:58:36.62#ibcon#first serial, iclass 37, count 0 2006.285.17:58:36.62#ibcon#enter sib2, iclass 37, count 0 2006.285.17:58:36.62#ibcon#flushed, iclass 37, count 0 2006.285.17:58:36.62#ibcon#about to write, iclass 37, count 0 2006.285.17:58:36.62#ibcon#wrote, iclass 37, count 0 2006.285.17:58:36.62#ibcon#about to read 3, iclass 37, count 0 2006.285.17:58:36.64#ibcon#read 3, iclass 37, count 0 2006.285.17:58:36.64#ibcon#about to read 4, iclass 37, count 0 2006.285.17:58:36.64#ibcon#read 4, iclass 37, count 0 2006.285.17:58:36.64#ibcon#about to read 5, iclass 37, count 0 2006.285.17:58:36.64#ibcon#read 5, iclass 37, count 0 2006.285.17:58:36.64#ibcon#about to read 6, iclass 37, count 0 2006.285.17:58:36.64#ibcon#read 6, iclass 37, count 0 2006.285.17:58:36.64#ibcon#end of sib2, iclass 37, count 0 2006.285.17:58:36.64#ibcon#*mode == 0, iclass 37, count 0 2006.285.17:58:36.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.17:58:36.64#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.17:58:36.64#ibcon#*before write, iclass 37, count 0 2006.285.17:58:36.64#ibcon#enter sib2, iclass 37, count 0 2006.285.17:58:36.64#ibcon#flushed, iclass 37, count 0 2006.285.17:58:36.64#ibcon#about to write, iclass 37, count 0 2006.285.17:58:36.64#ibcon#wrote, iclass 37, count 0 2006.285.17:58:36.64#ibcon#about to read 3, iclass 37, count 0 2006.285.17:58:36.68#ibcon#read 3, iclass 37, count 0 2006.285.17:58:36.68#ibcon#about to read 4, iclass 37, count 0 2006.285.17:58:36.68#ibcon#read 4, iclass 37, count 0 2006.285.17:58:36.68#ibcon#about to read 5, iclass 37, count 0 2006.285.17:58:36.68#ibcon#read 5, iclass 37, count 0 2006.285.17:58:36.68#ibcon#about to read 6, iclass 37, count 0 2006.285.17:58:36.68#ibcon#read 6, iclass 37, count 0 2006.285.17:58:36.68#ibcon#end of sib2, iclass 37, count 0 2006.285.17:58:36.68#ibcon#*after write, iclass 37, count 0 2006.285.17:58:36.68#ibcon#*before return 0, iclass 37, count 0 2006.285.17:58:36.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:58:36.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.17:58:36.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.17:58:36.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.17:58:36.68$vck44/va=7,4 2006.285.17:58:36.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.17:58:36.68#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.17:58:36.68#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:36.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:58:36.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:58:36.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:58:36.74#ibcon#enter wrdev, iclass 39, count 2 2006.285.17:58:36.74#ibcon#first serial, iclass 39, count 2 2006.285.17:58:36.74#ibcon#enter sib2, iclass 39, count 2 2006.285.17:58:36.74#ibcon#flushed, iclass 39, count 2 2006.285.17:58:36.74#ibcon#about to write, iclass 39, count 2 2006.285.17:58:36.74#ibcon#wrote, iclass 39, count 2 2006.285.17:58:36.74#ibcon#about to read 3, iclass 39, count 2 2006.285.17:58:36.76#ibcon#read 3, iclass 39, count 2 2006.285.17:58:36.76#ibcon#about to read 4, iclass 39, count 2 2006.285.17:58:36.76#ibcon#read 4, iclass 39, count 2 2006.285.17:58:36.76#ibcon#about to read 5, iclass 39, count 2 2006.285.17:58:36.76#ibcon#read 5, iclass 39, count 2 2006.285.17:58:36.76#ibcon#about to read 6, iclass 39, count 2 2006.285.17:58:36.76#ibcon#read 6, iclass 39, count 2 2006.285.17:58:36.76#ibcon#end of sib2, iclass 39, count 2 2006.285.17:58:36.76#ibcon#*mode == 0, iclass 39, count 2 2006.285.17:58:36.76#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.17:58:36.76#ibcon#[25=AT07-04\r\n] 2006.285.17:58:36.76#ibcon#*before write, iclass 39, count 2 2006.285.17:58:36.76#ibcon#enter sib2, iclass 39, count 2 2006.285.17:58:36.76#ibcon#flushed, iclass 39, count 2 2006.285.17:58:36.76#ibcon#about to write, iclass 39, count 2 2006.285.17:58:36.76#ibcon#wrote, iclass 39, count 2 2006.285.17:58:36.76#ibcon#about to read 3, iclass 39, count 2 2006.285.17:58:36.79#ibcon#read 3, iclass 39, count 2 2006.285.17:58:36.79#ibcon#about to read 4, iclass 39, count 2 2006.285.17:58:36.79#ibcon#read 4, iclass 39, count 2 2006.285.17:58:36.79#ibcon#about to read 5, iclass 39, count 2 2006.285.17:58:36.79#ibcon#read 5, iclass 39, count 2 2006.285.17:58:36.79#ibcon#about to read 6, iclass 39, count 2 2006.285.17:58:36.79#ibcon#read 6, iclass 39, count 2 2006.285.17:58:36.79#ibcon#end of sib2, iclass 39, count 2 2006.285.17:58:36.79#ibcon#*after write, iclass 39, count 2 2006.285.17:58:36.79#ibcon#*before return 0, iclass 39, count 2 2006.285.17:58:36.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:58:36.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.17:58:36.79#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.17:58:36.79#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:36.79#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:58:36.91#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:58:36.91#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:58:36.91#ibcon#enter wrdev, iclass 39, count 0 2006.285.17:58:36.91#ibcon#first serial, iclass 39, count 0 2006.285.17:58:36.91#ibcon#enter sib2, iclass 39, count 0 2006.285.17:58:36.91#ibcon#flushed, iclass 39, count 0 2006.285.17:58:36.91#ibcon#about to write, iclass 39, count 0 2006.285.17:58:36.91#ibcon#wrote, iclass 39, count 0 2006.285.17:58:36.91#ibcon#about to read 3, iclass 39, count 0 2006.285.17:58:36.93#ibcon#read 3, iclass 39, count 0 2006.285.17:58:36.93#ibcon#about to read 4, iclass 39, count 0 2006.285.17:58:36.93#ibcon#read 4, iclass 39, count 0 2006.285.17:58:36.93#ibcon#about to read 5, iclass 39, count 0 2006.285.17:58:36.93#ibcon#read 5, iclass 39, count 0 2006.285.17:58:36.93#ibcon#about to read 6, iclass 39, count 0 2006.285.17:58:36.93#ibcon#read 6, iclass 39, count 0 2006.285.17:58:36.93#ibcon#end of sib2, iclass 39, count 0 2006.285.17:58:36.93#ibcon#*mode == 0, iclass 39, count 0 2006.285.17:58:36.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.17:58:36.93#ibcon#[25=USB\r\n] 2006.285.17:58:36.93#ibcon#*before write, iclass 39, count 0 2006.285.17:58:36.93#ibcon#enter sib2, iclass 39, count 0 2006.285.17:58:36.93#ibcon#flushed, iclass 39, count 0 2006.285.17:58:36.93#ibcon#about to write, iclass 39, count 0 2006.285.17:58:36.93#ibcon#wrote, iclass 39, count 0 2006.285.17:58:36.93#ibcon#about to read 3, iclass 39, count 0 2006.285.17:58:36.96#ibcon#read 3, iclass 39, count 0 2006.285.17:58:36.96#ibcon#about to read 4, iclass 39, count 0 2006.285.17:58:36.96#ibcon#read 4, iclass 39, count 0 2006.285.17:58:36.96#ibcon#about to read 5, iclass 39, count 0 2006.285.17:58:36.96#ibcon#read 5, iclass 39, count 0 2006.285.17:58:36.96#ibcon#about to read 6, iclass 39, count 0 2006.285.17:58:36.96#ibcon#read 6, iclass 39, count 0 2006.285.17:58:36.96#ibcon#end of sib2, iclass 39, count 0 2006.285.17:58:36.96#ibcon#*after write, iclass 39, count 0 2006.285.17:58:36.96#ibcon#*before return 0, iclass 39, count 0 2006.285.17:58:36.96#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:58:36.96#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.17:58:36.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.17:58:36.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.17:58:36.96$vck44/valo=8,884.99 2006.285.17:58:36.96#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.17:58:36.96#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.17:58:36.96#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:36.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:58:36.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:58:36.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:58:36.96#ibcon#enter wrdev, iclass 3, count 0 2006.285.17:58:36.96#ibcon#first serial, iclass 3, count 0 2006.285.17:58:36.96#ibcon#enter sib2, iclass 3, count 0 2006.285.17:58:36.96#ibcon#flushed, iclass 3, count 0 2006.285.17:58:36.96#ibcon#about to write, iclass 3, count 0 2006.285.17:58:36.96#ibcon#wrote, iclass 3, count 0 2006.285.17:58:36.96#ibcon#about to read 3, iclass 3, count 0 2006.285.17:58:36.98#ibcon#read 3, iclass 3, count 0 2006.285.17:58:36.98#ibcon#about to read 4, iclass 3, count 0 2006.285.17:58:36.98#ibcon#read 4, iclass 3, count 0 2006.285.17:58:36.98#ibcon#about to read 5, iclass 3, count 0 2006.285.17:58:36.98#ibcon#read 5, iclass 3, count 0 2006.285.17:58:36.98#ibcon#about to read 6, iclass 3, count 0 2006.285.17:58:36.98#ibcon#read 6, iclass 3, count 0 2006.285.17:58:36.98#ibcon#end of sib2, iclass 3, count 0 2006.285.17:58:36.98#ibcon#*mode == 0, iclass 3, count 0 2006.285.17:58:36.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.17:58:36.98#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.17:58:36.98#ibcon#*before write, iclass 3, count 0 2006.285.17:58:36.98#ibcon#enter sib2, iclass 3, count 0 2006.285.17:58:36.98#ibcon#flushed, iclass 3, count 0 2006.285.17:58:36.98#ibcon#about to write, iclass 3, count 0 2006.285.17:58:36.98#ibcon#wrote, iclass 3, count 0 2006.285.17:58:36.98#ibcon#about to read 3, iclass 3, count 0 2006.285.17:58:37.02#ibcon#read 3, iclass 3, count 0 2006.285.17:58:37.02#ibcon#about to read 4, iclass 3, count 0 2006.285.17:58:37.02#ibcon#read 4, iclass 3, count 0 2006.285.17:58:37.02#ibcon#about to read 5, iclass 3, count 0 2006.285.17:58:37.02#ibcon#read 5, iclass 3, count 0 2006.285.17:58:37.02#ibcon#about to read 6, iclass 3, count 0 2006.285.17:58:37.02#ibcon#read 6, iclass 3, count 0 2006.285.17:58:37.02#ibcon#end of sib2, iclass 3, count 0 2006.285.17:58:37.02#ibcon#*after write, iclass 3, count 0 2006.285.17:58:37.02#ibcon#*before return 0, iclass 3, count 0 2006.285.17:58:37.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:58:37.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:58:37.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.17:58:37.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.17:58:37.02$vck44/va=8,3 2006.285.17:58:37.02#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.17:58:37.02#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.17:58:37.02#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:37.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:58:37.08#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:58:37.08#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:58:37.08#ibcon#enter wrdev, iclass 5, count 2 2006.285.17:58:37.08#ibcon#first serial, iclass 5, count 2 2006.285.17:58:37.08#ibcon#enter sib2, iclass 5, count 2 2006.285.17:58:37.08#ibcon#flushed, iclass 5, count 2 2006.285.17:58:37.08#ibcon#about to write, iclass 5, count 2 2006.285.17:58:37.08#ibcon#wrote, iclass 5, count 2 2006.285.17:58:37.08#ibcon#about to read 3, iclass 5, count 2 2006.285.17:58:37.10#ibcon#read 3, iclass 5, count 2 2006.285.17:58:37.10#ibcon#about to read 4, iclass 5, count 2 2006.285.17:58:37.10#ibcon#read 4, iclass 5, count 2 2006.285.17:58:37.10#ibcon#about to read 5, iclass 5, count 2 2006.285.17:58:37.10#ibcon#read 5, iclass 5, count 2 2006.285.17:58:37.10#ibcon#about to read 6, iclass 5, count 2 2006.285.17:58:37.10#ibcon#read 6, iclass 5, count 2 2006.285.17:58:37.10#ibcon#end of sib2, iclass 5, count 2 2006.285.17:58:37.10#ibcon#*mode == 0, iclass 5, count 2 2006.285.17:58:37.10#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.17:58:37.10#ibcon#[25=AT08-03\r\n] 2006.285.17:58:37.10#ibcon#*before write, iclass 5, count 2 2006.285.17:58:37.10#ibcon#enter sib2, iclass 5, count 2 2006.285.17:58:37.10#ibcon#flushed, iclass 5, count 2 2006.285.17:58:37.10#ibcon#about to write, iclass 5, count 2 2006.285.17:58:37.10#ibcon#wrote, iclass 5, count 2 2006.285.17:58:37.10#ibcon#about to read 3, iclass 5, count 2 2006.285.17:58:37.13#ibcon#read 3, iclass 5, count 2 2006.285.17:58:37.13#ibcon#about to read 4, iclass 5, count 2 2006.285.17:58:37.13#ibcon#read 4, iclass 5, count 2 2006.285.17:58:37.13#ibcon#about to read 5, iclass 5, count 2 2006.285.17:58:37.13#ibcon#read 5, iclass 5, count 2 2006.285.17:58:37.13#ibcon#about to read 6, iclass 5, count 2 2006.285.17:58:37.13#ibcon#read 6, iclass 5, count 2 2006.285.17:58:37.13#ibcon#end of sib2, iclass 5, count 2 2006.285.17:58:37.13#ibcon#*after write, iclass 5, count 2 2006.285.17:58:37.13#ibcon#*before return 0, iclass 5, count 2 2006.285.17:58:37.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:58:37.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:58:37.13#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.17:58:37.13#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:37.13#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:58:37.25#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:58:37.25#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:58:37.25#ibcon#enter wrdev, iclass 5, count 0 2006.285.17:58:37.25#ibcon#first serial, iclass 5, count 0 2006.285.17:58:37.25#ibcon#enter sib2, iclass 5, count 0 2006.285.17:58:37.25#ibcon#flushed, iclass 5, count 0 2006.285.17:58:37.25#ibcon#about to write, iclass 5, count 0 2006.285.17:58:37.25#ibcon#wrote, iclass 5, count 0 2006.285.17:58:37.25#ibcon#about to read 3, iclass 5, count 0 2006.285.17:58:37.27#ibcon#read 3, iclass 5, count 0 2006.285.17:58:37.27#ibcon#about to read 4, iclass 5, count 0 2006.285.17:58:37.27#ibcon#read 4, iclass 5, count 0 2006.285.17:58:37.27#ibcon#about to read 5, iclass 5, count 0 2006.285.17:58:37.27#ibcon#read 5, iclass 5, count 0 2006.285.17:58:37.27#ibcon#about to read 6, iclass 5, count 0 2006.285.17:58:37.27#ibcon#read 6, iclass 5, count 0 2006.285.17:58:37.27#ibcon#end of sib2, iclass 5, count 0 2006.285.17:58:37.27#ibcon#*mode == 0, iclass 5, count 0 2006.285.17:58:37.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.17:58:37.27#ibcon#[25=USB\r\n] 2006.285.17:58:37.27#ibcon#*before write, iclass 5, count 0 2006.285.17:58:37.27#ibcon#enter sib2, iclass 5, count 0 2006.285.17:58:37.27#ibcon#flushed, iclass 5, count 0 2006.285.17:58:37.27#ibcon#about to write, iclass 5, count 0 2006.285.17:58:37.27#ibcon#wrote, iclass 5, count 0 2006.285.17:58:37.27#ibcon#about to read 3, iclass 5, count 0 2006.285.17:58:37.30#ibcon#read 3, iclass 5, count 0 2006.285.17:58:37.30#ibcon#about to read 4, iclass 5, count 0 2006.285.17:58:37.30#ibcon#read 4, iclass 5, count 0 2006.285.17:58:37.30#ibcon#about to read 5, iclass 5, count 0 2006.285.17:58:37.30#ibcon#read 5, iclass 5, count 0 2006.285.17:58:37.30#ibcon#about to read 6, iclass 5, count 0 2006.285.17:58:37.30#ibcon#read 6, iclass 5, count 0 2006.285.17:58:37.30#ibcon#end of sib2, iclass 5, count 0 2006.285.17:58:37.30#ibcon#*after write, iclass 5, count 0 2006.285.17:58:37.30#ibcon#*before return 0, iclass 5, count 0 2006.285.17:58:37.30#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:58:37.30#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:58:37.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.17:58:37.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.17:58:37.30$vck44/vblo=1,629.99 2006.285.17:58:37.30#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.17:58:37.30#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.17:58:37.30#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:37.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:58:37.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:58:37.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:58:37.30#ibcon#enter wrdev, iclass 7, count 0 2006.285.17:58:37.30#ibcon#first serial, iclass 7, count 0 2006.285.17:58:37.30#ibcon#enter sib2, iclass 7, count 0 2006.285.17:58:37.30#ibcon#flushed, iclass 7, count 0 2006.285.17:58:37.30#ibcon#about to write, iclass 7, count 0 2006.285.17:58:37.30#ibcon#wrote, iclass 7, count 0 2006.285.17:58:37.30#ibcon#about to read 3, iclass 7, count 0 2006.285.17:58:37.32#ibcon#read 3, iclass 7, count 0 2006.285.17:58:37.32#ibcon#about to read 4, iclass 7, count 0 2006.285.17:58:37.32#ibcon#read 4, iclass 7, count 0 2006.285.17:58:37.32#ibcon#about to read 5, iclass 7, count 0 2006.285.17:58:37.32#ibcon#read 5, iclass 7, count 0 2006.285.17:58:37.32#ibcon#about to read 6, iclass 7, count 0 2006.285.17:58:37.32#ibcon#read 6, iclass 7, count 0 2006.285.17:58:37.32#ibcon#end of sib2, iclass 7, count 0 2006.285.17:58:37.32#ibcon#*mode == 0, iclass 7, count 0 2006.285.17:58:37.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.17:58:37.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.17:58:37.32#ibcon#*before write, iclass 7, count 0 2006.285.17:58:37.32#ibcon#enter sib2, iclass 7, count 0 2006.285.17:58:37.32#ibcon#flushed, iclass 7, count 0 2006.285.17:58:37.32#ibcon#about to write, iclass 7, count 0 2006.285.17:58:37.32#ibcon#wrote, iclass 7, count 0 2006.285.17:58:37.32#ibcon#about to read 3, iclass 7, count 0 2006.285.17:58:37.36#ibcon#read 3, iclass 7, count 0 2006.285.17:58:37.36#ibcon#about to read 4, iclass 7, count 0 2006.285.17:58:37.36#ibcon#read 4, iclass 7, count 0 2006.285.17:58:37.36#ibcon#about to read 5, iclass 7, count 0 2006.285.17:58:37.36#ibcon#read 5, iclass 7, count 0 2006.285.17:58:37.36#ibcon#about to read 6, iclass 7, count 0 2006.285.17:58:37.36#ibcon#read 6, iclass 7, count 0 2006.285.17:58:37.36#ibcon#end of sib2, iclass 7, count 0 2006.285.17:58:37.36#ibcon#*after write, iclass 7, count 0 2006.285.17:58:37.36#ibcon#*before return 0, iclass 7, count 0 2006.285.17:58:37.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:58:37.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:58:37.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.17:58:37.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.17:58:37.36$vck44/vb=1,4 2006.285.17:58:37.36#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.17:58:37.36#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.17:58:37.36#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:37.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:58:37.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:58:37.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:58:37.36#ibcon#enter wrdev, iclass 11, count 2 2006.285.17:58:37.36#ibcon#first serial, iclass 11, count 2 2006.285.17:58:37.36#ibcon#enter sib2, iclass 11, count 2 2006.285.17:58:37.36#ibcon#flushed, iclass 11, count 2 2006.285.17:58:37.36#ibcon#about to write, iclass 11, count 2 2006.285.17:58:37.36#ibcon#wrote, iclass 11, count 2 2006.285.17:58:37.36#ibcon#about to read 3, iclass 11, count 2 2006.285.17:58:37.38#ibcon#read 3, iclass 11, count 2 2006.285.17:58:37.38#ibcon#about to read 4, iclass 11, count 2 2006.285.17:58:37.38#ibcon#read 4, iclass 11, count 2 2006.285.17:58:37.38#ibcon#about to read 5, iclass 11, count 2 2006.285.17:58:37.38#ibcon#read 5, iclass 11, count 2 2006.285.17:58:37.38#ibcon#about to read 6, iclass 11, count 2 2006.285.17:58:37.38#ibcon#read 6, iclass 11, count 2 2006.285.17:58:37.38#ibcon#end of sib2, iclass 11, count 2 2006.285.17:58:37.38#ibcon#*mode == 0, iclass 11, count 2 2006.285.17:58:37.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.17:58:37.38#ibcon#[27=AT01-04\r\n] 2006.285.17:58:37.38#ibcon#*before write, iclass 11, count 2 2006.285.17:58:37.38#ibcon#enter sib2, iclass 11, count 2 2006.285.17:58:37.38#ibcon#flushed, iclass 11, count 2 2006.285.17:58:37.38#ibcon#about to write, iclass 11, count 2 2006.285.17:58:37.38#ibcon#wrote, iclass 11, count 2 2006.285.17:58:37.38#ibcon#about to read 3, iclass 11, count 2 2006.285.17:58:37.41#ibcon#read 3, iclass 11, count 2 2006.285.17:58:37.41#ibcon#about to read 4, iclass 11, count 2 2006.285.17:58:37.41#ibcon#read 4, iclass 11, count 2 2006.285.17:58:37.41#ibcon#about to read 5, iclass 11, count 2 2006.285.17:58:37.41#ibcon#read 5, iclass 11, count 2 2006.285.17:58:37.41#ibcon#about to read 6, iclass 11, count 2 2006.285.17:58:37.41#ibcon#read 6, iclass 11, count 2 2006.285.17:58:37.41#ibcon#end of sib2, iclass 11, count 2 2006.285.17:58:37.41#ibcon#*after write, iclass 11, count 2 2006.285.17:58:37.41#ibcon#*before return 0, iclass 11, count 2 2006.285.17:58:37.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:58:37.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.17:58:37.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.17:58:37.41#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:37.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:58:37.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:58:37.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:58:37.53#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:58:37.53#ibcon#first serial, iclass 11, count 0 2006.285.17:58:37.53#ibcon#enter sib2, iclass 11, count 0 2006.285.17:58:37.53#ibcon#flushed, iclass 11, count 0 2006.285.17:58:37.53#ibcon#about to write, iclass 11, count 0 2006.285.17:58:37.53#ibcon#wrote, iclass 11, count 0 2006.285.17:58:37.53#ibcon#about to read 3, iclass 11, count 0 2006.285.17:58:37.55#ibcon#read 3, iclass 11, count 0 2006.285.17:58:37.55#ibcon#about to read 4, iclass 11, count 0 2006.285.17:58:37.55#ibcon#read 4, iclass 11, count 0 2006.285.17:58:37.55#ibcon#about to read 5, iclass 11, count 0 2006.285.17:58:37.55#ibcon#read 5, iclass 11, count 0 2006.285.17:58:37.55#ibcon#about to read 6, iclass 11, count 0 2006.285.17:58:37.55#ibcon#read 6, iclass 11, count 0 2006.285.17:58:37.55#ibcon#end of sib2, iclass 11, count 0 2006.285.17:58:37.55#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:58:37.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:58:37.55#ibcon#[27=USB\r\n] 2006.285.17:58:37.55#ibcon#*before write, iclass 11, count 0 2006.285.17:58:37.55#ibcon#enter sib2, iclass 11, count 0 2006.285.17:58:37.55#ibcon#flushed, iclass 11, count 0 2006.285.17:58:37.55#ibcon#about to write, iclass 11, count 0 2006.285.17:58:37.55#ibcon#wrote, iclass 11, count 0 2006.285.17:58:37.55#ibcon#about to read 3, iclass 11, count 0 2006.285.17:58:37.58#ibcon#read 3, iclass 11, count 0 2006.285.17:58:37.58#ibcon#about to read 4, iclass 11, count 0 2006.285.17:58:37.58#ibcon#read 4, iclass 11, count 0 2006.285.17:58:37.58#ibcon#about to read 5, iclass 11, count 0 2006.285.17:58:37.58#ibcon#read 5, iclass 11, count 0 2006.285.17:58:37.58#ibcon#about to read 6, iclass 11, count 0 2006.285.17:58:37.58#ibcon#read 6, iclass 11, count 0 2006.285.17:58:37.58#ibcon#end of sib2, iclass 11, count 0 2006.285.17:58:37.58#ibcon#*after write, iclass 11, count 0 2006.285.17:58:37.58#ibcon#*before return 0, iclass 11, count 0 2006.285.17:58:37.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:58:37.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.17:58:37.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:58:37.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:58:37.58$vck44/vblo=2,634.99 2006.285.17:58:37.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.17:58:37.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.17:58:37.58#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:37.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:58:37.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:58:37.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:58:37.58#ibcon#enter wrdev, iclass 13, count 0 2006.285.17:58:37.58#ibcon#first serial, iclass 13, count 0 2006.285.17:58:37.58#ibcon#enter sib2, iclass 13, count 0 2006.285.17:58:37.58#ibcon#flushed, iclass 13, count 0 2006.285.17:58:37.58#ibcon#about to write, iclass 13, count 0 2006.285.17:58:37.58#ibcon#wrote, iclass 13, count 0 2006.285.17:58:37.58#ibcon#about to read 3, iclass 13, count 0 2006.285.17:58:37.60#ibcon#read 3, iclass 13, count 0 2006.285.17:58:37.60#ibcon#about to read 4, iclass 13, count 0 2006.285.17:58:37.60#ibcon#read 4, iclass 13, count 0 2006.285.17:58:37.60#ibcon#about to read 5, iclass 13, count 0 2006.285.17:58:37.60#ibcon#read 5, iclass 13, count 0 2006.285.17:58:37.60#ibcon#about to read 6, iclass 13, count 0 2006.285.17:58:37.60#ibcon#read 6, iclass 13, count 0 2006.285.17:58:37.60#ibcon#end of sib2, iclass 13, count 0 2006.285.17:58:37.60#ibcon#*mode == 0, iclass 13, count 0 2006.285.17:58:37.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.17:58:37.60#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.17:58:37.60#ibcon#*before write, iclass 13, count 0 2006.285.17:58:37.60#ibcon#enter sib2, iclass 13, count 0 2006.285.17:58:37.60#ibcon#flushed, iclass 13, count 0 2006.285.17:58:37.60#ibcon#about to write, iclass 13, count 0 2006.285.17:58:37.60#ibcon#wrote, iclass 13, count 0 2006.285.17:58:37.60#ibcon#about to read 3, iclass 13, count 0 2006.285.17:58:37.64#ibcon#read 3, iclass 13, count 0 2006.285.17:58:37.64#ibcon#about to read 4, iclass 13, count 0 2006.285.17:58:37.64#ibcon#read 4, iclass 13, count 0 2006.285.17:58:37.64#ibcon#about to read 5, iclass 13, count 0 2006.285.17:58:37.64#ibcon#read 5, iclass 13, count 0 2006.285.17:58:37.64#ibcon#about to read 6, iclass 13, count 0 2006.285.17:58:37.64#ibcon#read 6, iclass 13, count 0 2006.285.17:58:37.64#ibcon#end of sib2, iclass 13, count 0 2006.285.17:58:37.64#ibcon#*after write, iclass 13, count 0 2006.285.17:58:37.64#ibcon#*before return 0, iclass 13, count 0 2006.285.17:58:37.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:58:37.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.17:58:37.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.17:58:37.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.17:58:37.64$vck44/vb=2,5 2006.285.17:58:37.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.17:58:37.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.17:58:37.64#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:37.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:58:37.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:58:37.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:58:37.70#ibcon#enter wrdev, iclass 15, count 2 2006.285.17:58:37.70#ibcon#first serial, iclass 15, count 2 2006.285.17:58:37.70#ibcon#enter sib2, iclass 15, count 2 2006.285.17:58:37.70#ibcon#flushed, iclass 15, count 2 2006.285.17:58:37.70#ibcon#about to write, iclass 15, count 2 2006.285.17:58:37.70#ibcon#wrote, iclass 15, count 2 2006.285.17:58:37.70#ibcon#about to read 3, iclass 15, count 2 2006.285.17:58:37.72#ibcon#read 3, iclass 15, count 2 2006.285.17:58:37.72#ibcon#about to read 4, iclass 15, count 2 2006.285.17:58:37.72#ibcon#read 4, iclass 15, count 2 2006.285.17:58:37.72#ibcon#about to read 5, iclass 15, count 2 2006.285.17:58:37.72#ibcon#read 5, iclass 15, count 2 2006.285.17:58:37.72#ibcon#about to read 6, iclass 15, count 2 2006.285.17:58:37.72#ibcon#read 6, iclass 15, count 2 2006.285.17:58:37.72#ibcon#end of sib2, iclass 15, count 2 2006.285.17:58:37.72#ibcon#*mode == 0, iclass 15, count 2 2006.285.17:58:37.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.17:58:37.72#ibcon#[27=AT02-05\r\n] 2006.285.17:58:37.72#ibcon#*before write, iclass 15, count 2 2006.285.17:58:37.72#ibcon#enter sib2, iclass 15, count 2 2006.285.17:58:37.72#ibcon#flushed, iclass 15, count 2 2006.285.17:58:37.72#ibcon#about to write, iclass 15, count 2 2006.285.17:58:37.72#ibcon#wrote, iclass 15, count 2 2006.285.17:58:37.72#ibcon#about to read 3, iclass 15, count 2 2006.285.17:58:37.75#ibcon#read 3, iclass 15, count 2 2006.285.17:58:37.75#ibcon#about to read 4, iclass 15, count 2 2006.285.17:58:37.75#ibcon#read 4, iclass 15, count 2 2006.285.17:58:37.75#ibcon#about to read 5, iclass 15, count 2 2006.285.17:58:37.75#ibcon#read 5, iclass 15, count 2 2006.285.17:58:37.75#ibcon#about to read 6, iclass 15, count 2 2006.285.17:58:37.75#ibcon#read 6, iclass 15, count 2 2006.285.17:58:37.75#ibcon#end of sib2, iclass 15, count 2 2006.285.17:58:37.75#ibcon#*after write, iclass 15, count 2 2006.285.17:58:37.75#ibcon#*before return 0, iclass 15, count 2 2006.285.17:58:37.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:58:37.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.17:58:37.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.17:58:37.75#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:37.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:58:37.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:58:37.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:58:37.87#ibcon#enter wrdev, iclass 15, count 0 2006.285.17:58:37.87#ibcon#first serial, iclass 15, count 0 2006.285.17:58:37.87#ibcon#enter sib2, iclass 15, count 0 2006.285.17:58:37.87#ibcon#flushed, iclass 15, count 0 2006.285.17:58:37.87#ibcon#about to write, iclass 15, count 0 2006.285.17:58:37.87#ibcon#wrote, iclass 15, count 0 2006.285.17:58:37.87#ibcon#about to read 3, iclass 15, count 0 2006.285.17:58:37.89#ibcon#read 3, iclass 15, count 0 2006.285.17:58:37.89#ibcon#about to read 4, iclass 15, count 0 2006.285.17:58:37.89#ibcon#read 4, iclass 15, count 0 2006.285.17:58:37.89#ibcon#about to read 5, iclass 15, count 0 2006.285.17:58:37.89#ibcon#read 5, iclass 15, count 0 2006.285.17:58:37.89#ibcon#about to read 6, iclass 15, count 0 2006.285.17:58:37.89#ibcon#read 6, iclass 15, count 0 2006.285.17:58:37.89#ibcon#end of sib2, iclass 15, count 0 2006.285.17:58:37.89#ibcon#*mode == 0, iclass 15, count 0 2006.285.17:58:37.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.17:58:37.89#ibcon#[27=USB\r\n] 2006.285.17:58:37.89#ibcon#*before write, iclass 15, count 0 2006.285.17:58:37.89#ibcon#enter sib2, iclass 15, count 0 2006.285.17:58:37.89#ibcon#flushed, iclass 15, count 0 2006.285.17:58:37.89#ibcon#about to write, iclass 15, count 0 2006.285.17:58:37.89#ibcon#wrote, iclass 15, count 0 2006.285.17:58:37.89#ibcon#about to read 3, iclass 15, count 0 2006.285.17:58:37.92#ibcon#read 3, iclass 15, count 0 2006.285.17:58:37.92#ibcon#about to read 4, iclass 15, count 0 2006.285.17:58:37.92#ibcon#read 4, iclass 15, count 0 2006.285.17:58:37.92#ibcon#about to read 5, iclass 15, count 0 2006.285.17:58:37.92#ibcon#read 5, iclass 15, count 0 2006.285.17:58:37.92#ibcon#about to read 6, iclass 15, count 0 2006.285.17:58:37.92#ibcon#read 6, iclass 15, count 0 2006.285.17:58:37.92#ibcon#end of sib2, iclass 15, count 0 2006.285.17:58:37.92#ibcon#*after write, iclass 15, count 0 2006.285.17:58:37.92#ibcon#*before return 0, iclass 15, count 0 2006.285.17:58:37.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:58:37.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.17:58:37.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.17:58:37.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.17:58:37.92$vck44/vblo=3,649.99 2006.285.17:58:37.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.17:58:37.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.17:58:37.92#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:37.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:58:37.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:58:37.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:58:37.92#ibcon#enter wrdev, iclass 17, count 0 2006.285.17:58:37.92#ibcon#first serial, iclass 17, count 0 2006.285.17:58:37.92#ibcon#enter sib2, iclass 17, count 0 2006.285.17:58:37.92#ibcon#flushed, iclass 17, count 0 2006.285.17:58:37.92#ibcon#about to write, iclass 17, count 0 2006.285.17:58:37.92#ibcon#wrote, iclass 17, count 0 2006.285.17:58:37.92#ibcon#about to read 3, iclass 17, count 0 2006.285.17:58:37.94#ibcon#read 3, iclass 17, count 0 2006.285.17:58:37.99#ibcon#about to read 4, iclass 17, count 0 2006.285.17:58:37.99#ibcon#read 4, iclass 17, count 0 2006.285.17:58:37.99#ibcon#about to read 5, iclass 17, count 0 2006.285.17:58:37.99#ibcon#read 5, iclass 17, count 0 2006.285.17:58:37.99#ibcon#about to read 6, iclass 17, count 0 2006.285.17:58:37.99#ibcon#read 6, iclass 17, count 0 2006.285.17:58:37.99#ibcon#end of sib2, iclass 17, count 0 2006.285.17:58:37.99#ibcon#*mode == 0, iclass 17, count 0 2006.285.17:58:37.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.17:58:37.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.17:58:37.99#ibcon#*before write, iclass 17, count 0 2006.285.17:58:37.99#ibcon#enter sib2, iclass 17, count 0 2006.285.17:58:37.99#ibcon#flushed, iclass 17, count 0 2006.285.17:58:37.99#ibcon#about to write, iclass 17, count 0 2006.285.17:58:37.99#ibcon#wrote, iclass 17, count 0 2006.285.17:58:37.99#ibcon#about to read 3, iclass 17, count 0 2006.285.17:58:38.03#ibcon#read 3, iclass 17, count 0 2006.285.17:58:38.03#ibcon#about to read 4, iclass 17, count 0 2006.285.17:58:38.03#ibcon#read 4, iclass 17, count 0 2006.285.17:58:38.03#ibcon#about to read 5, iclass 17, count 0 2006.285.17:58:38.03#ibcon#read 5, iclass 17, count 0 2006.285.17:58:38.03#ibcon#about to read 6, iclass 17, count 0 2006.285.17:58:38.03#ibcon#read 6, iclass 17, count 0 2006.285.17:58:38.03#ibcon#end of sib2, iclass 17, count 0 2006.285.17:58:38.03#ibcon#*after write, iclass 17, count 0 2006.285.17:58:38.03#ibcon#*before return 0, iclass 17, count 0 2006.285.17:58:38.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:58:38.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.17:58:38.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.17:58:38.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.17:58:38.03$vck44/vb=3,4 2006.285.17:58:38.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.17:58:38.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.17:58:38.03#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:38.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:58:38.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:58:38.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:58:38.03#ibcon#enter wrdev, iclass 19, count 2 2006.285.17:58:38.03#ibcon#first serial, iclass 19, count 2 2006.285.17:58:38.03#ibcon#enter sib2, iclass 19, count 2 2006.285.17:58:38.03#ibcon#flushed, iclass 19, count 2 2006.285.17:58:38.03#ibcon#about to write, iclass 19, count 2 2006.285.17:58:38.03#ibcon#wrote, iclass 19, count 2 2006.285.17:58:38.03#ibcon#about to read 3, iclass 19, count 2 2006.285.17:58:38.05#ibcon#read 3, iclass 19, count 2 2006.285.17:58:38.05#ibcon#about to read 4, iclass 19, count 2 2006.285.17:58:38.05#ibcon#read 4, iclass 19, count 2 2006.285.17:58:38.05#ibcon#about to read 5, iclass 19, count 2 2006.285.17:58:38.05#ibcon#read 5, iclass 19, count 2 2006.285.17:58:38.05#ibcon#about to read 6, iclass 19, count 2 2006.285.17:58:38.05#ibcon#read 6, iclass 19, count 2 2006.285.17:58:38.05#ibcon#end of sib2, iclass 19, count 2 2006.285.17:58:38.05#ibcon#*mode == 0, iclass 19, count 2 2006.285.17:58:38.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.17:58:38.05#ibcon#[27=AT03-04\r\n] 2006.285.17:58:38.05#ibcon#*before write, iclass 19, count 2 2006.285.17:58:38.05#ibcon#enter sib2, iclass 19, count 2 2006.285.17:58:38.05#ibcon#flushed, iclass 19, count 2 2006.285.17:58:38.05#ibcon#about to write, iclass 19, count 2 2006.285.17:58:38.05#ibcon#wrote, iclass 19, count 2 2006.285.17:58:38.05#ibcon#about to read 3, iclass 19, count 2 2006.285.17:58:38.08#ibcon#read 3, iclass 19, count 2 2006.285.17:58:38.08#ibcon#about to read 4, iclass 19, count 2 2006.285.17:58:38.08#ibcon#read 4, iclass 19, count 2 2006.285.17:58:38.08#ibcon#about to read 5, iclass 19, count 2 2006.285.17:58:38.08#ibcon#read 5, iclass 19, count 2 2006.285.17:58:38.08#ibcon#about to read 6, iclass 19, count 2 2006.285.17:58:38.08#ibcon#read 6, iclass 19, count 2 2006.285.17:58:38.08#ibcon#end of sib2, iclass 19, count 2 2006.285.17:58:38.08#ibcon#*after write, iclass 19, count 2 2006.285.17:58:38.08#ibcon#*before return 0, iclass 19, count 2 2006.285.17:58:38.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:58:38.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.17:58:38.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.17:58:38.08#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:38.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:58:38.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:58:38.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:58:38.20#ibcon#enter wrdev, iclass 19, count 0 2006.285.17:58:38.20#ibcon#first serial, iclass 19, count 0 2006.285.17:58:38.20#ibcon#enter sib2, iclass 19, count 0 2006.285.17:58:38.20#ibcon#flushed, iclass 19, count 0 2006.285.17:58:38.20#ibcon#about to write, iclass 19, count 0 2006.285.17:58:38.20#ibcon#wrote, iclass 19, count 0 2006.285.17:58:38.20#ibcon#about to read 3, iclass 19, count 0 2006.285.17:58:38.22#ibcon#read 3, iclass 19, count 0 2006.285.17:58:38.22#ibcon#about to read 4, iclass 19, count 0 2006.285.17:58:38.22#ibcon#read 4, iclass 19, count 0 2006.285.17:58:38.22#ibcon#about to read 5, iclass 19, count 0 2006.285.17:58:38.22#ibcon#read 5, iclass 19, count 0 2006.285.17:58:38.22#ibcon#about to read 6, iclass 19, count 0 2006.285.17:58:38.22#ibcon#read 6, iclass 19, count 0 2006.285.17:58:38.22#ibcon#end of sib2, iclass 19, count 0 2006.285.17:58:38.22#ibcon#*mode == 0, iclass 19, count 0 2006.285.17:58:38.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.17:58:38.22#ibcon#[27=USB\r\n] 2006.285.17:58:38.22#ibcon#*before write, iclass 19, count 0 2006.285.17:58:38.22#ibcon#enter sib2, iclass 19, count 0 2006.285.17:58:38.22#ibcon#flushed, iclass 19, count 0 2006.285.17:58:38.22#ibcon#about to write, iclass 19, count 0 2006.285.17:58:38.22#ibcon#wrote, iclass 19, count 0 2006.285.17:58:38.22#ibcon#about to read 3, iclass 19, count 0 2006.285.17:58:38.25#ibcon#read 3, iclass 19, count 0 2006.285.17:58:38.25#ibcon#about to read 4, iclass 19, count 0 2006.285.17:58:38.25#ibcon#read 4, iclass 19, count 0 2006.285.17:58:38.25#ibcon#about to read 5, iclass 19, count 0 2006.285.17:58:38.25#ibcon#read 5, iclass 19, count 0 2006.285.17:58:38.25#ibcon#about to read 6, iclass 19, count 0 2006.285.17:58:38.25#ibcon#read 6, iclass 19, count 0 2006.285.17:58:38.25#ibcon#end of sib2, iclass 19, count 0 2006.285.17:58:38.25#ibcon#*after write, iclass 19, count 0 2006.285.17:58:38.25#ibcon#*before return 0, iclass 19, count 0 2006.285.17:58:38.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:58:38.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.17:58:38.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.17:58:38.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.17:58:38.25$vck44/vblo=4,679.99 2006.285.17:58:38.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.17:58:38.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.17:58:38.25#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:38.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:58:38.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:58:38.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:58:38.25#ibcon#enter wrdev, iclass 21, count 0 2006.285.17:58:38.25#ibcon#first serial, iclass 21, count 0 2006.285.17:58:38.25#ibcon#enter sib2, iclass 21, count 0 2006.285.17:58:38.25#ibcon#flushed, iclass 21, count 0 2006.285.17:58:38.25#ibcon#about to write, iclass 21, count 0 2006.285.17:58:38.25#ibcon#wrote, iclass 21, count 0 2006.285.17:58:38.25#ibcon#about to read 3, iclass 21, count 0 2006.285.17:58:38.27#ibcon#read 3, iclass 21, count 0 2006.285.17:58:38.27#ibcon#about to read 4, iclass 21, count 0 2006.285.17:58:38.27#ibcon#read 4, iclass 21, count 0 2006.285.17:58:38.27#ibcon#about to read 5, iclass 21, count 0 2006.285.17:58:38.27#ibcon#read 5, iclass 21, count 0 2006.285.17:58:38.27#ibcon#about to read 6, iclass 21, count 0 2006.285.17:58:38.27#ibcon#read 6, iclass 21, count 0 2006.285.17:58:38.27#ibcon#end of sib2, iclass 21, count 0 2006.285.17:58:38.27#ibcon#*mode == 0, iclass 21, count 0 2006.285.17:58:38.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.17:58:38.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.17:58:38.27#ibcon#*before write, iclass 21, count 0 2006.285.17:58:38.27#ibcon#enter sib2, iclass 21, count 0 2006.285.17:58:38.27#ibcon#flushed, iclass 21, count 0 2006.285.17:58:38.27#ibcon#about to write, iclass 21, count 0 2006.285.17:58:38.27#ibcon#wrote, iclass 21, count 0 2006.285.17:58:38.27#ibcon#about to read 3, iclass 21, count 0 2006.285.17:58:38.31#ibcon#read 3, iclass 21, count 0 2006.285.17:58:38.31#ibcon#about to read 4, iclass 21, count 0 2006.285.17:58:38.31#ibcon#read 4, iclass 21, count 0 2006.285.17:58:38.31#ibcon#about to read 5, iclass 21, count 0 2006.285.17:58:38.31#ibcon#read 5, iclass 21, count 0 2006.285.17:58:38.31#ibcon#about to read 6, iclass 21, count 0 2006.285.17:58:38.31#ibcon#read 6, iclass 21, count 0 2006.285.17:58:38.31#ibcon#end of sib2, iclass 21, count 0 2006.285.17:58:38.31#ibcon#*after write, iclass 21, count 0 2006.285.17:58:38.31#ibcon#*before return 0, iclass 21, count 0 2006.285.17:58:38.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:58:38.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.17:58:38.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.17:58:38.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.17:58:38.31$vck44/vb=4,5 2006.285.17:58:38.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.17:58:38.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.17:58:38.31#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:38.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:58:38.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:58:38.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:58:38.37#ibcon#enter wrdev, iclass 23, count 2 2006.285.17:58:38.37#ibcon#first serial, iclass 23, count 2 2006.285.17:58:38.37#ibcon#enter sib2, iclass 23, count 2 2006.285.17:58:38.37#ibcon#flushed, iclass 23, count 2 2006.285.17:58:38.37#ibcon#about to write, iclass 23, count 2 2006.285.17:58:38.37#ibcon#wrote, iclass 23, count 2 2006.285.17:58:38.37#ibcon#about to read 3, iclass 23, count 2 2006.285.17:58:38.39#ibcon#read 3, iclass 23, count 2 2006.285.17:58:38.39#ibcon#about to read 4, iclass 23, count 2 2006.285.17:58:38.39#ibcon#read 4, iclass 23, count 2 2006.285.17:58:38.39#ibcon#about to read 5, iclass 23, count 2 2006.285.17:58:38.39#ibcon#read 5, iclass 23, count 2 2006.285.17:58:38.39#ibcon#about to read 6, iclass 23, count 2 2006.285.17:58:38.39#ibcon#read 6, iclass 23, count 2 2006.285.17:58:38.39#ibcon#end of sib2, iclass 23, count 2 2006.285.17:58:38.39#ibcon#*mode == 0, iclass 23, count 2 2006.285.17:58:38.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.17:58:38.39#ibcon#[27=AT04-05\r\n] 2006.285.17:58:38.39#ibcon#*before write, iclass 23, count 2 2006.285.17:58:38.39#ibcon#enter sib2, iclass 23, count 2 2006.285.17:58:38.39#ibcon#flushed, iclass 23, count 2 2006.285.17:58:38.39#ibcon#about to write, iclass 23, count 2 2006.285.17:58:38.39#ibcon#wrote, iclass 23, count 2 2006.285.17:58:38.39#ibcon#about to read 3, iclass 23, count 2 2006.285.17:58:38.42#ibcon#read 3, iclass 23, count 2 2006.285.17:58:38.42#ibcon#about to read 4, iclass 23, count 2 2006.285.17:58:38.42#ibcon#read 4, iclass 23, count 2 2006.285.17:58:38.42#ibcon#about to read 5, iclass 23, count 2 2006.285.17:58:38.42#ibcon#read 5, iclass 23, count 2 2006.285.17:58:38.42#ibcon#about to read 6, iclass 23, count 2 2006.285.17:58:38.42#ibcon#read 6, iclass 23, count 2 2006.285.17:58:38.42#ibcon#end of sib2, iclass 23, count 2 2006.285.17:58:38.42#ibcon#*after write, iclass 23, count 2 2006.285.17:58:38.42#ibcon#*before return 0, iclass 23, count 2 2006.285.17:58:38.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:58:38.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.17:58:38.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.17:58:38.42#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:38.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:58:38.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:58:38.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:58:38.54#ibcon#enter wrdev, iclass 23, count 0 2006.285.17:58:38.54#ibcon#first serial, iclass 23, count 0 2006.285.17:58:38.54#ibcon#enter sib2, iclass 23, count 0 2006.285.17:58:38.54#ibcon#flushed, iclass 23, count 0 2006.285.17:58:38.54#ibcon#about to write, iclass 23, count 0 2006.285.17:58:38.54#ibcon#wrote, iclass 23, count 0 2006.285.17:58:38.54#ibcon#about to read 3, iclass 23, count 0 2006.285.17:58:38.56#ibcon#read 3, iclass 23, count 0 2006.285.17:58:38.56#ibcon#about to read 4, iclass 23, count 0 2006.285.17:58:38.56#ibcon#read 4, iclass 23, count 0 2006.285.17:58:38.56#ibcon#about to read 5, iclass 23, count 0 2006.285.17:58:38.56#ibcon#read 5, iclass 23, count 0 2006.285.17:58:38.56#ibcon#about to read 6, iclass 23, count 0 2006.285.17:58:38.56#ibcon#read 6, iclass 23, count 0 2006.285.17:58:38.56#ibcon#end of sib2, iclass 23, count 0 2006.285.17:58:38.56#ibcon#*mode == 0, iclass 23, count 0 2006.285.17:58:38.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.17:58:38.56#ibcon#[27=USB\r\n] 2006.285.17:58:38.56#ibcon#*before write, iclass 23, count 0 2006.285.17:58:38.56#ibcon#enter sib2, iclass 23, count 0 2006.285.17:58:38.56#ibcon#flushed, iclass 23, count 0 2006.285.17:58:38.56#ibcon#about to write, iclass 23, count 0 2006.285.17:58:38.56#ibcon#wrote, iclass 23, count 0 2006.285.17:58:38.56#ibcon#about to read 3, iclass 23, count 0 2006.285.17:58:38.59#ibcon#read 3, iclass 23, count 0 2006.285.17:58:38.59#ibcon#about to read 4, iclass 23, count 0 2006.285.17:58:38.59#ibcon#read 4, iclass 23, count 0 2006.285.17:58:38.59#ibcon#about to read 5, iclass 23, count 0 2006.285.17:58:38.59#ibcon#read 5, iclass 23, count 0 2006.285.17:58:38.59#ibcon#about to read 6, iclass 23, count 0 2006.285.17:58:38.59#ibcon#read 6, iclass 23, count 0 2006.285.17:58:38.59#ibcon#end of sib2, iclass 23, count 0 2006.285.17:58:38.59#ibcon#*after write, iclass 23, count 0 2006.285.17:58:38.59#ibcon#*before return 0, iclass 23, count 0 2006.285.17:58:38.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:58:38.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.17:58:38.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.17:58:38.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.17:58:38.59$vck44/vblo=5,709.99 2006.285.17:58:38.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.17:58:38.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.17:58:38.59#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:38.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:58:38.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:58:38.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:58:38.59#ibcon#enter wrdev, iclass 25, count 0 2006.285.17:58:38.59#ibcon#first serial, iclass 25, count 0 2006.285.17:58:38.59#ibcon#enter sib2, iclass 25, count 0 2006.285.17:58:38.59#ibcon#flushed, iclass 25, count 0 2006.285.17:58:38.59#ibcon#about to write, iclass 25, count 0 2006.285.17:58:38.59#ibcon#wrote, iclass 25, count 0 2006.285.17:58:38.59#ibcon#about to read 3, iclass 25, count 0 2006.285.17:58:38.61#ibcon#read 3, iclass 25, count 0 2006.285.17:58:38.61#ibcon#about to read 4, iclass 25, count 0 2006.285.17:58:38.61#ibcon#read 4, iclass 25, count 0 2006.285.17:58:38.61#ibcon#about to read 5, iclass 25, count 0 2006.285.17:58:38.61#ibcon#read 5, iclass 25, count 0 2006.285.17:58:38.61#ibcon#about to read 6, iclass 25, count 0 2006.285.17:58:38.61#ibcon#read 6, iclass 25, count 0 2006.285.17:58:38.61#ibcon#end of sib2, iclass 25, count 0 2006.285.17:58:38.61#ibcon#*mode == 0, iclass 25, count 0 2006.285.17:58:38.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.17:58:38.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.17:58:38.61#ibcon#*before write, iclass 25, count 0 2006.285.17:58:38.61#ibcon#enter sib2, iclass 25, count 0 2006.285.17:58:38.61#ibcon#flushed, iclass 25, count 0 2006.285.17:58:38.61#ibcon#about to write, iclass 25, count 0 2006.285.17:58:38.61#ibcon#wrote, iclass 25, count 0 2006.285.17:58:38.61#ibcon#about to read 3, iclass 25, count 0 2006.285.17:58:38.65#ibcon#read 3, iclass 25, count 0 2006.285.17:58:38.65#ibcon#about to read 4, iclass 25, count 0 2006.285.17:58:38.65#ibcon#read 4, iclass 25, count 0 2006.285.17:58:38.65#ibcon#about to read 5, iclass 25, count 0 2006.285.17:58:38.65#ibcon#read 5, iclass 25, count 0 2006.285.17:58:38.65#ibcon#about to read 6, iclass 25, count 0 2006.285.17:58:38.65#ibcon#read 6, iclass 25, count 0 2006.285.17:58:38.65#ibcon#end of sib2, iclass 25, count 0 2006.285.17:58:38.65#ibcon#*after write, iclass 25, count 0 2006.285.17:58:38.65#ibcon#*before return 0, iclass 25, count 0 2006.285.17:58:38.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:58:38.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.17:58:38.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.17:58:38.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.17:58:38.65$vck44/vb=5,4 2006.285.17:58:38.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.17:58:38.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.17:58:38.65#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:38.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:58:38.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:58:38.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:58:38.71#ibcon#enter wrdev, iclass 27, count 2 2006.285.17:58:38.71#ibcon#first serial, iclass 27, count 2 2006.285.17:58:38.71#ibcon#enter sib2, iclass 27, count 2 2006.285.17:58:38.71#ibcon#flushed, iclass 27, count 2 2006.285.17:58:38.71#ibcon#about to write, iclass 27, count 2 2006.285.17:58:38.71#ibcon#wrote, iclass 27, count 2 2006.285.17:58:38.71#ibcon#about to read 3, iclass 27, count 2 2006.285.17:58:38.73#ibcon#read 3, iclass 27, count 2 2006.285.17:58:38.73#ibcon#about to read 4, iclass 27, count 2 2006.285.17:58:38.73#ibcon#read 4, iclass 27, count 2 2006.285.17:58:38.73#ibcon#about to read 5, iclass 27, count 2 2006.285.17:58:38.73#ibcon#read 5, iclass 27, count 2 2006.285.17:58:38.73#ibcon#about to read 6, iclass 27, count 2 2006.285.17:58:38.73#ibcon#read 6, iclass 27, count 2 2006.285.17:58:38.73#ibcon#end of sib2, iclass 27, count 2 2006.285.17:58:38.73#ibcon#*mode == 0, iclass 27, count 2 2006.285.17:58:38.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.17:58:38.73#ibcon#[27=AT05-04\r\n] 2006.285.17:58:38.73#ibcon#*before write, iclass 27, count 2 2006.285.17:58:38.73#ibcon#enter sib2, iclass 27, count 2 2006.285.17:58:38.73#ibcon#flushed, iclass 27, count 2 2006.285.17:58:38.73#ibcon#about to write, iclass 27, count 2 2006.285.17:58:38.73#ibcon#wrote, iclass 27, count 2 2006.285.17:58:38.73#ibcon#about to read 3, iclass 27, count 2 2006.285.17:58:38.76#ibcon#read 3, iclass 27, count 2 2006.285.17:58:38.76#ibcon#about to read 4, iclass 27, count 2 2006.285.17:58:38.76#ibcon#read 4, iclass 27, count 2 2006.285.17:58:38.76#ibcon#about to read 5, iclass 27, count 2 2006.285.17:58:38.76#ibcon#read 5, iclass 27, count 2 2006.285.17:58:38.76#ibcon#about to read 6, iclass 27, count 2 2006.285.17:58:38.76#ibcon#read 6, iclass 27, count 2 2006.285.17:58:38.76#ibcon#end of sib2, iclass 27, count 2 2006.285.17:58:38.76#ibcon#*after write, iclass 27, count 2 2006.285.17:58:38.76#ibcon#*before return 0, iclass 27, count 2 2006.285.17:58:38.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:58:38.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.17:58:38.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.17:58:38.76#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:38.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:58:38.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:58:38.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:58:38.88#ibcon#enter wrdev, iclass 27, count 0 2006.285.17:58:38.88#ibcon#first serial, iclass 27, count 0 2006.285.17:58:38.88#ibcon#enter sib2, iclass 27, count 0 2006.285.17:58:38.88#ibcon#flushed, iclass 27, count 0 2006.285.17:58:38.88#ibcon#about to write, iclass 27, count 0 2006.285.17:58:38.88#ibcon#wrote, iclass 27, count 0 2006.285.17:58:38.88#ibcon#about to read 3, iclass 27, count 0 2006.285.17:58:38.90#ibcon#read 3, iclass 27, count 0 2006.285.17:58:38.90#ibcon#about to read 4, iclass 27, count 0 2006.285.17:58:38.90#ibcon#read 4, iclass 27, count 0 2006.285.17:58:38.90#ibcon#about to read 5, iclass 27, count 0 2006.285.17:58:38.90#ibcon#read 5, iclass 27, count 0 2006.285.17:58:38.90#ibcon#about to read 6, iclass 27, count 0 2006.285.17:58:38.90#ibcon#read 6, iclass 27, count 0 2006.285.17:58:38.90#ibcon#end of sib2, iclass 27, count 0 2006.285.17:58:38.90#ibcon#*mode == 0, iclass 27, count 0 2006.285.17:58:38.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.17:58:38.90#ibcon#[27=USB\r\n] 2006.285.17:58:38.90#ibcon#*before write, iclass 27, count 0 2006.285.17:58:38.90#ibcon#enter sib2, iclass 27, count 0 2006.285.17:58:38.90#ibcon#flushed, iclass 27, count 0 2006.285.17:58:38.90#ibcon#about to write, iclass 27, count 0 2006.285.17:58:38.90#ibcon#wrote, iclass 27, count 0 2006.285.17:58:38.90#ibcon#about to read 3, iclass 27, count 0 2006.285.17:58:38.93#ibcon#read 3, iclass 27, count 0 2006.285.17:58:38.93#ibcon#about to read 4, iclass 27, count 0 2006.285.17:58:38.93#ibcon#read 4, iclass 27, count 0 2006.285.17:58:38.93#ibcon#about to read 5, iclass 27, count 0 2006.285.17:58:38.93#ibcon#read 5, iclass 27, count 0 2006.285.17:58:38.93#ibcon#about to read 6, iclass 27, count 0 2006.285.17:58:38.93#ibcon#read 6, iclass 27, count 0 2006.285.17:58:38.93#ibcon#end of sib2, iclass 27, count 0 2006.285.17:58:38.93#ibcon#*after write, iclass 27, count 0 2006.285.17:58:38.93#ibcon#*before return 0, iclass 27, count 0 2006.285.17:58:38.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:58:38.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.17:58:38.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.17:58:38.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.17:58:38.93$vck44/vblo=6,719.99 2006.285.17:58:38.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.17:58:38.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.17:58:38.93#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:38.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:58:38.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:58:38.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:58:38.93#ibcon#enter wrdev, iclass 29, count 0 2006.285.17:58:38.93#ibcon#first serial, iclass 29, count 0 2006.285.17:58:38.93#ibcon#enter sib2, iclass 29, count 0 2006.285.17:58:38.93#ibcon#flushed, iclass 29, count 0 2006.285.17:58:38.93#ibcon#about to write, iclass 29, count 0 2006.285.17:58:38.93#ibcon#wrote, iclass 29, count 0 2006.285.17:58:38.93#ibcon#about to read 3, iclass 29, count 0 2006.285.17:58:38.95#ibcon#read 3, iclass 29, count 0 2006.285.17:58:39.01#ibcon#about to read 4, iclass 29, count 0 2006.285.17:58:39.01#ibcon#read 4, iclass 29, count 0 2006.285.17:58:39.01#ibcon#about to read 5, iclass 29, count 0 2006.285.17:58:39.01#ibcon#read 5, iclass 29, count 0 2006.285.17:58:39.01#ibcon#about to read 6, iclass 29, count 0 2006.285.17:58:39.01#ibcon#read 6, iclass 29, count 0 2006.285.17:58:39.01#ibcon#end of sib2, iclass 29, count 0 2006.285.17:58:39.01#ibcon#*mode == 0, iclass 29, count 0 2006.285.17:58:39.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.17:58:39.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.17:58:39.01#ibcon#*before write, iclass 29, count 0 2006.285.17:58:39.01#ibcon#enter sib2, iclass 29, count 0 2006.285.17:58:39.01#ibcon#flushed, iclass 29, count 0 2006.285.17:58:39.01#ibcon#about to write, iclass 29, count 0 2006.285.17:58:39.01#ibcon#wrote, iclass 29, count 0 2006.285.17:58:39.01#ibcon#about to read 3, iclass 29, count 0 2006.285.17:58:39.05#ibcon#read 3, iclass 29, count 0 2006.285.17:58:39.05#ibcon#about to read 4, iclass 29, count 0 2006.285.17:58:39.05#ibcon#read 4, iclass 29, count 0 2006.285.17:58:39.05#ibcon#about to read 5, iclass 29, count 0 2006.285.17:58:39.05#ibcon#read 5, iclass 29, count 0 2006.285.17:58:39.05#ibcon#about to read 6, iclass 29, count 0 2006.285.17:58:39.05#ibcon#read 6, iclass 29, count 0 2006.285.17:58:39.05#ibcon#end of sib2, iclass 29, count 0 2006.285.17:58:39.05#ibcon#*after write, iclass 29, count 0 2006.285.17:58:39.05#ibcon#*before return 0, iclass 29, count 0 2006.285.17:58:39.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:58:39.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.17:58:39.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.17:58:39.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.17:58:39.05$vck44/vb=6,3 2006.285.17:58:39.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.17:58:39.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.17:58:39.05#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:39.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:58:39.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:58:39.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:58:39.05#ibcon#enter wrdev, iclass 31, count 2 2006.285.17:58:39.05#ibcon#first serial, iclass 31, count 2 2006.285.17:58:39.05#ibcon#enter sib2, iclass 31, count 2 2006.285.17:58:39.05#ibcon#flushed, iclass 31, count 2 2006.285.17:58:39.05#ibcon#about to write, iclass 31, count 2 2006.285.17:58:39.05#ibcon#wrote, iclass 31, count 2 2006.285.17:58:39.05#ibcon#about to read 3, iclass 31, count 2 2006.285.17:58:39.07#ibcon#read 3, iclass 31, count 2 2006.285.17:58:39.07#ibcon#about to read 4, iclass 31, count 2 2006.285.17:58:39.07#ibcon#read 4, iclass 31, count 2 2006.285.17:58:39.07#ibcon#about to read 5, iclass 31, count 2 2006.285.17:58:39.07#ibcon#read 5, iclass 31, count 2 2006.285.17:58:39.07#ibcon#about to read 6, iclass 31, count 2 2006.285.17:58:39.07#ibcon#read 6, iclass 31, count 2 2006.285.17:58:39.07#ibcon#end of sib2, iclass 31, count 2 2006.285.17:58:39.07#ibcon#*mode == 0, iclass 31, count 2 2006.285.17:58:39.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.17:58:39.07#ibcon#[27=AT06-03\r\n] 2006.285.17:58:39.07#ibcon#*before write, iclass 31, count 2 2006.285.17:58:39.07#ibcon#enter sib2, iclass 31, count 2 2006.285.17:58:39.07#ibcon#flushed, iclass 31, count 2 2006.285.17:58:39.07#ibcon#about to write, iclass 31, count 2 2006.285.17:58:39.07#ibcon#wrote, iclass 31, count 2 2006.285.17:58:39.07#ibcon#about to read 3, iclass 31, count 2 2006.285.17:58:39.10#ibcon#read 3, iclass 31, count 2 2006.285.17:58:39.10#ibcon#about to read 4, iclass 31, count 2 2006.285.17:58:39.10#ibcon#read 4, iclass 31, count 2 2006.285.17:58:39.10#ibcon#about to read 5, iclass 31, count 2 2006.285.17:58:39.10#ibcon#read 5, iclass 31, count 2 2006.285.17:58:39.10#ibcon#about to read 6, iclass 31, count 2 2006.285.17:58:39.10#ibcon#read 6, iclass 31, count 2 2006.285.17:58:39.10#ibcon#end of sib2, iclass 31, count 2 2006.285.17:58:39.10#ibcon#*after write, iclass 31, count 2 2006.285.17:58:39.10#ibcon#*before return 0, iclass 31, count 2 2006.285.17:58:39.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:58:39.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.17:58:39.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.17:58:39.10#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:39.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:58:39.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:58:39.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:58:39.22#ibcon#enter wrdev, iclass 31, count 0 2006.285.17:58:39.22#ibcon#first serial, iclass 31, count 0 2006.285.17:58:39.22#ibcon#enter sib2, iclass 31, count 0 2006.285.17:58:39.22#ibcon#flushed, iclass 31, count 0 2006.285.17:58:39.22#ibcon#about to write, iclass 31, count 0 2006.285.17:58:39.22#ibcon#wrote, iclass 31, count 0 2006.285.17:58:39.22#ibcon#about to read 3, iclass 31, count 0 2006.285.17:58:39.24#ibcon#read 3, iclass 31, count 0 2006.285.17:58:39.24#ibcon#about to read 4, iclass 31, count 0 2006.285.17:58:39.24#ibcon#read 4, iclass 31, count 0 2006.285.17:58:39.24#ibcon#about to read 5, iclass 31, count 0 2006.285.17:58:39.24#ibcon#read 5, iclass 31, count 0 2006.285.17:58:39.24#ibcon#about to read 6, iclass 31, count 0 2006.285.17:58:39.24#ibcon#read 6, iclass 31, count 0 2006.285.17:58:39.24#ibcon#end of sib2, iclass 31, count 0 2006.285.17:58:39.24#ibcon#*mode == 0, iclass 31, count 0 2006.285.17:58:39.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.17:58:39.24#ibcon#[27=USB\r\n] 2006.285.17:58:39.24#ibcon#*before write, iclass 31, count 0 2006.285.17:58:39.24#ibcon#enter sib2, iclass 31, count 0 2006.285.17:58:39.24#ibcon#flushed, iclass 31, count 0 2006.285.17:58:39.24#ibcon#about to write, iclass 31, count 0 2006.285.17:58:39.24#ibcon#wrote, iclass 31, count 0 2006.285.17:58:39.24#ibcon#about to read 3, iclass 31, count 0 2006.285.17:58:39.27#ibcon#read 3, iclass 31, count 0 2006.285.17:58:39.27#ibcon#about to read 4, iclass 31, count 0 2006.285.17:58:39.27#ibcon#read 4, iclass 31, count 0 2006.285.17:58:39.27#ibcon#about to read 5, iclass 31, count 0 2006.285.17:58:39.27#ibcon#read 5, iclass 31, count 0 2006.285.17:58:39.27#ibcon#about to read 6, iclass 31, count 0 2006.285.17:58:39.27#ibcon#read 6, iclass 31, count 0 2006.285.17:58:39.27#ibcon#end of sib2, iclass 31, count 0 2006.285.17:58:39.27#ibcon#*after write, iclass 31, count 0 2006.285.17:58:39.27#ibcon#*before return 0, iclass 31, count 0 2006.285.17:58:39.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:58:39.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.17:58:39.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.17:58:39.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.17:58:39.27$vck44/vblo=7,734.99 2006.285.17:58:39.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.17:58:39.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.17:58:39.27#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:39.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:58:39.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:58:39.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:58:39.27#ibcon#enter wrdev, iclass 33, count 0 2006.285.17:58:39.27#ibcon#first serial, iclass 33, count 0 2006.285.17:58:39.27#ibcon#enter sib2, iclass 33, count 0 2006.285.17:58:39.27#ibcon#flushed, iclass 33, count 0 2006.285.17:58:39.27#ibcon#about to write, iclass 33, count 0 2006.285.17:58:39.27#ibcon#wrote, iclass 33, count 0 2006.285.17:58:39.27#ibcon#about to read 3, iclass 33, count 0 2006.285.17:58:39.29#ibcon#read 3, iclass 33, count 0 2006.285.17:58:39.29#ibcon#about to read 4, iclass 33, count 0 2006.285.17:58:39.29#ibcon#read 4, iclass 33, count 0 2006.285.17:58:39.29#ibcon#about to read 5, iclass 33, count 0 2006.285.17:58:39.29#ibcon#read 5, iclass 33, count 0 2006.285.17:58:39.29#ibcon#about to read 6, iclass 33, count 0 2006.285.17:58:39.29#ibcon#read 6, iclass 33, count 0 2006.285.17:58:39.29#ibcon#end of sib2, iclass 33, count 0 2006.285.17:58:39.29#ibcon#*mode == 0, iclass 33, count 0 2006.285.17:58:39.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.17:58:39.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.17:58:39.29#ibcon#*before write, iclass 33, count 0 2006.285.17:58:39.29#ibcon#enter sib2, iclass 33, count 0 2006.285.17:58:39.29#ibcon#flushed, iclass 33, count 0 2006.285.17:58:39.29#ibcon#about to write, iclass 33, count 0 2006.285.17:58:39.29#ibcon#wrote, iclass 33, count 0 2006.285.17:58:39.29#ibcon#about to read 3, iclass 33, count 0 2006.285.17:58:39.33#ibcon#read 3, iclass 33, count 0 2006.285.17:58:39.33#ibcon#about to read 4, iclass 33, count 0 2006.285.17:58:39.33#ibcon#read 4, iclass 33, count 0 2006.285.17:58:39.33#ibcon#about to read 5, iclass 33, count 0 2006.285.17:58:39.33#ibcon#read 5, iclass 33, count 0 2006.285.17:58:39.33#ibcon#about to read 6, iclass 33, count 0 2006.285.17:58:39.33#ibcon#read 6, iclass 33, count 0 2006.285.17:58:39.33#ibcon#end of sib2, iclass 33, count 0 2006.285.17:58:39.33#ibcon#*after write, iclass 33, count 0 2006.285.17:58:39.33#ibcon#*before return 0, iclass 33, count 0 2006.285.17:58:39.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:58:39.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.17:58:39.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.17:58:39.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.17:58:39.33$vck44/vb=7,4 2006.285.17:58:39.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.17:58:39.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.17:58:39.33#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:39.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:58:39.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:58:39.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:58:39.39#ibcon#enter wrdev, iclass 35, count 2 2006.285.17:58:39.39#ibcon#first serial, iclass 35, count 2 2006.285.17:58:39.39#ibcon#enter sib2, iclass 35, count 2 2006.285.17:58:39.39#ibcon#flushed, iclass 35, count 2 2006.285.17:58:39.39#ibcon#about to write, iclass 35, count 2 2006.285.17:58:39.39#ibcon#wrote, iclass 35, count 2 2006.285.17:58:39.39#ibcon#about to read 3, iclass 35, count 2 2006.285.17:58:39.41#abcon#<5=/08 0.5 1.0 16.191001014.4\r\n> 2006.285.17:58:39.41#ibcon#read 3, iclass 35, count 2 2006.285.17:58:39.41#ibcon#about to read 4, iclass 35, count 2 2006.285.17:58:39.41#ibcon#read 4, iclass 35, count 2 2006.285.17:58:39.41#ibcon#about to read 5, iclass 35, count 2 2006.285.17:58:39.41#ibcon#read 5, iclass 35, count 2 2006.285.17:58:39.41#ibcon#about to read 6, iclass 35, count 2 2006.285.17:58:39.41#ibcon#read 6, iclass 35, count 2 2006.285.17:58:39.41#ibcon#end of sib2, iclass 35, count 2 2006.285.17:58:39.41#ibcon#*mode == 0, iclass 35, count 2 2006.285.17:58:39.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.17:58:39.41#ibcon#[27=AT07-04\r\n] 2006.285.17:58:39.41#ibcon#*before write, iclass 35, count 2 2006.285.17:58:39.41#ibcon#enter sib2, iclass 35, count 2 2006.285.17:58:39.41#ibcon#flushed, iclass 35, count 2 2006.285.17:58:39.41#ibcon#about to write, iclass 35, count 2 2006.285.17:58:39.41#ibcon#wrote, iclass 35, count 2 2006.285.17:58:39.41#ibcon#about to read 3, iclass 35, count 2 2006.285.17:58:39.43#abcon#{5=INTERFACE CLEAR} 2006.285.17:58:39.44#ibcon#read 3, iclass 35, count 2 2006.285.17:58:39.44#ibcon#about to read 4, iclass 35, count 2 2006.285.17:58:39.44#ibcon#read 4, iclass 35, count 2 2006.285.17:58:39.44#ibcon#about to read 5, iclass 35, count 2 2006.285.17:58:39.44#ibcon#read 5, iclass 35, count 2 2006.285.17:58:39.44#ibcon#about to read 6, iclass 35, count 2 2006.285.17:58:39.44#ibcon#read 6, iclass 35, count 2 2006.285.17:58:39.44#ibcon#end of sib2, iclass 35, count 2 2006.285.17:58:39.44#ibcon#*after write, iclass 35, count 2 2006.285.17:58:39.44#ibcon#*before return 0, iclass 35, count 2 2006.285.17:58:39.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:58:39.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.17:58:39.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.17:58:39.44#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:39.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:58:39.49#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:58:39.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:58:39.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:58:39.56#ibcon#enter wrdev, iclass 35, count 0 2006.285.17:58:39.56#ibcon#first serial, iclass 35, count 0 2006.285.17:58:39.56#ibcon#enter sib2, iclass 35, count 0 2006.285.17:58:39.56#ibcon#flushed, iclass 35, count 0 2006.285.17:58:39.56#ibcon#about to write, iclass 35, count 0 2006.285.17:58:39.56#ibcon#wrote, iclass 35, count 0 2006.285.17:58:39.56#ibcon#about to read 3, iclass 35, count 0 2006.285.17:58:39.58#ibcon#read 3, iclass 35, count 0 2006.285.17:58:39.58#ibcon#about to read 4, iclass 35, count 0 2006.285.17:58:39.58#ibcon#read 4, iclass 35, count 0 2006.285.17:58:39.58#ibcon#about to read 5, iclass 35, count 0 2006.285.17:58:39.58#ibcon#read 5, iclass 35, count 0 2006.285.17:58:39.58#ibcon#about to read 6, iclass 35, count 0 2006.285.17:58:39.58#ibcon#read 6, iclass 35, count 0 2006.285.17:58:39.58#ibcon#end of sib2, iclass 35, count 0 2006.285.17:58:39.58#ibcon#*mode == 0, iclass 35, count 0 2006.285.17:58:39.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.17:58:39.58#ibcon#[27=USB\r\n] 2006.285.17:58:39.58#ibcon#*before write, iclass 35, count 0 2006.285.17:58:39.58#ibcon#enter sib2, iclass 35, count 0 2006.285.17:58:39.58#ibcon#flushed, iclass 35, count 0 2006.285.17:58:39.58#ibcon#about to write, iclass 35, count 0 2006.285.17:58:39.58#ibcon#wrote, iclass 35, count 0 2006.285.17:58:39.58#ibcon#about to read 3, iclass 35, count 0 2006.285.17:58:39.61#ibcon#read 3, iclass 35, count 0 2006.285.17:58:39.61#ibcon#about to read 4, iclass 35, count 0 2006.285.17:58:39.61#ibcon#read 4, iclass 35, count 0 2006.285.17:58:39.61#ibcon#about to read 5, iclass 35, count 0 2006.285.17:58:39.61#ibcon#read 5, iclass 35, count 0 2006.285.17:58:39.61#ibcon#about to read 6, iclass 35, count 0 2006.285.17:58:39.61#ibcon#read 6, iclass 35, count 0 2006.285.17:58:39.61#ibcon#end of sib2, iclass 35, count 0 2006.285.17:58:39.61#ibcon#*after write, iclass 35, count 0 2006.285.17:58:39.61#ibcon#*before return 0, iclass 35, count 0 2006.285.17:58:39.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:58:39.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.17:58:39.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.17:58:39.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.17:58:39.61$vck44/vblo=8,744.99 2006.285.17:58:39.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.17:58:39.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.17:58:39.61#ibcon#ireg 17 cls_cnt 0 2006.285.17:58:39.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:58:39.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:58:39.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:58:39.61#ibcon#enter wrdev, iclass 3, count 0 2006.285.17:58:39.61#ibcon#first serial, iclass 3, count 0 2006.285.17:58:39.61#ibcon#enter sib2, iclass 3, count 0 2006.285.17:58:39.61#ibcon#flushed, iclass 3, count 0 2006.285.17:58:39.61#ibcon#about to write, iclass 3, count 0 2006.285.17:58:39.61#ibcon#wrote, iclass 3, count 0 2006.285.17:58:39.61#ibcon#about to read 3, iclass 3, count 0 2006.285.17:58:39.63#ibcon#read 3, iclass 3, count 0 2006.285.17:58:39.63#ibcon#about to read 4, iclass 3, count 0 2006.285.17:58:39.63#ibcon#read 4, iclass 3, count 0 2006.285.17:58:39.63#ibcon#about to read 5, iclass 3, count 0 2006.285.17:58:39.63#ibcon#read 5, iclass 3, count 0 2006.285.17:58:39.63#ibcon#about to read 6, iclass 3, count 0 2006.285.17:58:39.63#ibcon#read 6, iclass 3, count 0 2006.285.17:58:39.63#ibcon#end of sib2, iclass 3, count 0 2006.285.17:58:39.63#ibcon#*mode == 0, iclass 3, count 0 2006.285.17:58:39.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.17:58:39.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.17:58:39.63#ibcon#*before write, iclass 3, count 0 2006.285.17:58:39.63#ibcon#enter sib2, iclass 3, count 0 2006.285.17:58:39.63#ibcon#flushed, iclass 3, count 0 2006.285.17:58:39.63#ibcon#about to write, iclass 3, count 0 2006.285.17:58:39.63#ibcon#wrote, iclass 3, count 0 2006.285.17:58:39.63#ibcon#about to read 3, iclass 3, count 0 2006.285.17:58:39.67#ibcon#read 3, iclass 3, count 0 2006.285.17:58:39.67#ibcon#about to read 4, iclass 3, count 0 2006.285.17:58:39.67#ibcon#read 4, iclass 3, count 0 2006.285.17:58:39.67#ibcon#about to read 5, iclass 3, count 0 2006.285.17:58:39.67#ibcon#read 5, iclass 3, count 0 2006.285.17:58:39.67#ibcon#about to read 6, iclass 3, count 0 2006.285.17:58:39.67#ibcon#read 6, iclass 3, count 0 2006.285.17:58:39.67#ibcon#end of sib2, iclass 3, count 0 2006.285.17:58:39.67#ibcon#*after write, iclass 3, count 0 2006.285.17:58:39.67#ibcon#*before return 0, iclass 3, count 0 2006.285.17:58:39.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:58:39.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.17:58:39.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.17:58:39.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.17:58:39.67$vck44/vb=8,4 2006.285.17:58:39.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.17:58:39.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.17:58:39.67#ibcon#ireg 11 cls_cnt 2 2006.285.17:58:39.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:58:39.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:58:39.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:58:39.73#ibcon#enter wrdev, iclass 5, count 2 2006.285.17:58:39.73#ibcon#first serial, iclass 5, count 2 2006.285.17:58:39.73#ibcon#enter sib2, iclass 5, count 2 2006.285.17:58:39.73#ibcon#flushed, iclass 5, count 2 2006.285.17:58:39.73#ibcon#about to write, iclass 5, count 2 2006.285.17:58:39.73#ibcon#wrote, iclass 5, count 2 2006.285.17:58:39.73#ibcon#about to read 3, iclass 5, count 2 2006.285.17:58:39.75#ibcon#read 3, iclass 5, count 2 2006.285.17:58:39.75#ibcon#about to read 4, iclass 5, count 2 2006.285.17:58:39.75#ibcon#read 4, iclass 5, count 2 2006.285.17:58:39.75#ibcon#about to read 5, iclass 5, count 2 2006.285.17:58:39.75#ibcon#read 5, iclass 5, count 2 2006.285.17:58:39.75#ibcon#about to read 6, iclass 5, count 2 2006.285.17:58:39.75#ibcon#read 6, iclass 5, count 2 2006.285.17:58:39.75#ibcon#end of sib2, iclass 5, count 2 2006.285.17:58:39.75#ibcon#*mode == 0, iclass 5, count 2 2006.285.17:58:39.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.17:58:39.75#ibcon#[27=AT08-04\r\n] 2006.285.17:58:39.75#ibcon#*before write, iclass 5, count 2 2006.285.17:58:39.75#ibcon#enter sib2, iclass 5, count 2 2006.285.17:58:39.75#ibcon#flushed, iclass 5, count 2 2006.285.17:58:39.75#ibcon#about to write, iclass 5, count 2 2006.285.17:58:39.75#ibcon#wrote, iclass 5, count 2 2006.285.17:58:39.75#ibcon#about to read 3, iclass 5, count 2 2006.285.17:58:39.78#ibcon#read 3, iclass 5, count 2 2006.285.17:58:39.78#ibcon#about to read 4, iclass 5, count 2 2006.285.17:58:39.78#ibcon#read 4, iclass 5, count 2 2006.285.17:58:39.78#ibcon#about to read 5, iclass 5, count 2 2006.285.17:58:39.78#ibcon#read 5, iclass 5, count 2 2006.285.17:58:39.78#ibcon#about to read 6, iclass 5, count 2 2006.285.17:58:39.78#ibcon#read 6, iclass 5, count 2 2006.285.17:58:39.78#ibcon#end of sib2, iclass 5, count 2 2006.285.17:58:39.78#ibcon#*after write, iclass 5, count 2 2006.285.17:58:39.78#ibcon#*before return 0, iclass 5, count 2 2006.285.17:58:39.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:58:39.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.17:58:39.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.17:58:39.78#ibcon#ireg 7 cls_cnt 0 2006.285.17:58:39.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:58:39.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:58:39.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:58:39.90#ibcon#enter wrdev, iclass 5, count 0 2006.285.17:58:39.90#ibcon#first serial, iclass 5, count 0 2006.285.17:58:39.90#ibcon#enter sib2, iclass 5, count 0 2006.285.17:58:39.90#ibcon#flushed, iclass 5, count 0 2006.285.17:58:39.90#ibcon#about to write, iclass 5, count 0 2006.285.17:58:39.90#ibcon#wrote, iclass 5, count 0 2006.285.17:58:39.90#ibcon#about to read 3, iclass 5, count 0 2006.285.17:58:39.92#ibcon#read 3, iclass 5, count 0 2006.285.17:58:39.92#ibcon#about to read 4, iclass 5, count 0 2006.285.17:58:39.92#ibcon#read 4, iclass 5, count 0 2006.285.17:58:39.92#ibcon#about to read 5, iclass 5, count 0 2006.285.17:58:39.92#ibcon#read 5, iclass 5, count 0 2006.285.17:58:39.92#ibcon#about to read 6, iclass 5, count 0 2006.285.17:58:39.92#ibcon#read 6, iclass 5, count 0 2006.285.17:58:39.92#ibcon#end of sib2, iclass 5, count 0 2006.285.17:58:39.92#ibcon#*mode == 0, iclass 5, count 0 2006.285.17:58:39.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.17:58:39.92#ibcon#[27=USB\r\n] 2006.285.17:58:39.92#ibcon#*before write, iclass 5, count 0 2006.285.17:58:39.92#ibcon#enter sib2, iclass 5, count 0 2006.285.17:58:39.92#ibcon#flushed, iclass 5, count 0 2006.285.17:58:39.92#ibcon#about to write, iclass 5, count 0 2006.285.17:58:39.92#ibcon#wrote, iclass 5, count 0 2006.285.17:58:39.92#ibcon#about to read 3, iclass 5, count 0 2006.285.17:58:39.95#ibcon#read 3, iclass 5, count 0 2006.285.17:58:39.95#ibcon#about to read 4, iclass 5, count 0 2006.285.17:58:39.95#ibcon#read 4, iclass 5, count 0 2006.285.17:58:39.95#ibcon#about to read 5, iclass 5, count 0 2006.285.17:58:39.95#ibcon#read 5, iclass 5, count 0 2006.285.17:58:39.95#ibcon#about to read 6, iclass 5, count 0 2006.285.17:58:39.95#ibcon#read 6, iclass 5, count 0 2006.285.17:58:39.95#ibcon#end of sib2, iclass 5, count 0 2006.285.17:58:39.95#ibcon#*after write, iclass 5, count 0 2006.285.17:58:39.95#ibcon#*before return 0, iclass 5, count 0 2006.285.17:58:39.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:58:39.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.17:58:39.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.17:58:39.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.17:58:39.95$vck44/vabw=wide 2006.285.17:58:39.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.17:58:39.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.17:58:39.95#ibcon#ireg 8 cls_cnt 0 2006.285.17:58:39.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:58:39.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:58:39.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:58:39.95#ibcon#enter wrdev, iclass 7, count 0 2006.285.17:58:39.95#ibcon#first serial, iclass 7, count 0 2006.285.17:58:39.95#ibcon#enter sib2, iclass 7, count 0 2006.285.17:58:39.95#ibcon#flushed, iclass 7, count 0 2006.285.17:58:39.95#ibcon#about to write, iclass 7, count 0 2006.285.17:58:39.95#ibcon#wrote, iclass 7, count 0 2006.285.17:58:39.95#ibcon#about to read 3, iclass 7, count 0 2006.285.17:58:39.97#ibcon#read 3, iclass 7, count 0 2006.285.17:58:40.22#ibcon#about to read 4, iclass 7, count 0 2006.285.17:58:40.22#ibcon#read 4, iclass 7, count 0 2006.285.17:58:40.22#ibcon#about to read 5, iclass 7, count 0 2006.285.17:58:40.22#ibcon#read 5, iclass 7, count 0 2006.285.17:58:40.22#ibcon#about to read 6, iclass 7, count 0 2006.285.17:58:40.22#ibcon#read 6, iclass 7, count 0 2006.285.17:58:40.22#ibcon#end of sib2, iclass 7, count 0 2006.285.17:58:40.22#ibcon#*mode == 0, iclass 7, count 0 2006.285.17:58:40.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.17:58:40.22#ibcon#[25=BW32\r\n] 2006.285.17:58:40.22#ibcon#*before write, iclass 7, count 0 2006.285.17:58:40.22#ibcon#enter sib2, iclass 7, count 0 2006.285.17:58:40.22#ibcon#flushed, iclass 7, count 0 2006.285.17:58:40.22#ibcon#about to write, iclass 7, count 0 2006.285.17:58:40.22#ibcon#wrote, iclass 7, count 0 2006.285.17:58:40.22#ibcon#about to read 3, iclass 7, count 0 2006.285.17:58:40.25#ibcon#read 3, iclass 7, count 0 2006.285.17:58:40.25#ibcon#about to read 4, iclass 7, count 0 2006.285.17:58:40.25#ibcon#read 4, iclass 7, count 0 2006.285.17:58:40.25#ibcon#about to read 5, iclass 7, count 0 2006.285.17:58:40.25#ibcon#read 5, iclass 7, count 0 2006.285.17:58:40.25#ibcon#about to read 6, iclass 7, count 0 2006.285.17:58:40.25#ibcon#read 6, iclass 7, count 0 2006.285.17:58:40.25#ibcon#end of sib2, iclass 7, count 0 2006.285.17:58:40.25#ibcon#*after write, iclass 7, count 0 2006.285.17:58:40.25#ibcon#*before return 0, iclass 7, count 0 2006.285.17:58:40.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:58:40.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.17:58:40.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.17:58:40.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.17:58:40.25$vck44/vbbw=wide 2006.285.17:58:40.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.17:58:40.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.17:58:40.25#ibcon#ireg 8 cls_cnt 0 2006.285.17:58:40.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:58:40.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:58:40.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:58:40.25#ibcon#enter wrdev, iclass 11, count 0 2006.285.17:58:40.25#ibcon#first serial, iclass 11, count 0 2006.285.17:58:40.25#ibcon#enter sib2, iclass 11, count 0 2006.285.17:58:40.25#ibcon#flushed, iclass 11, count 0 2006.285.17:58:40.25#ibcon#about to write, iclass 11, count 0 2006.285.17:58:40.25#ibcon#wrote, iclass 11, count 0 2006.285.17:58:40.25#ibcon#about to read 3, iclass 11, count 0 2006.285.17:58:40.27#ibcon#read 3, iclass 11, count 0 2006.285.17:58:40.27#ibcon#about to read 4, iclass 11, count 0 2006.285.17:58:40.27#ibcon#read 4, iclass 11, count 0 2006.285.17:58:40.27#ibcon#about to read 5, iclass 11, count 0 2006.285.17:58:40.27#ibcon#read 5, iclass 11, count 0 2006.285.17:58:40.27#ibcon#about to read 6, iclass 11, count 0 2006.285.17:58:40.27#ibcon#read 6, iclass 11, count 0 2006.285.17:58:40.27#ibcon#end of sib2, iclass 11, count 0 2006.285.17:58:40.27#ibcon#*mode == 0, iclass 11, count 0 2006.285.17:58:40.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.17:58:40.27#ibcon#[27=BW32\r\n] 2006.285.17:58:40.27#ibcon#*before write, iclass 11, count 0 2006.285.17:58:40.27#ibcon#enter sib2, iclass 11, count 0 2006.285.17:58:40.27#ibcon#flushed, iclass 11, count 0 2006.285.17:58:40.27#ibcon#about to write, iclass 11, count 0 2006.285.17:58:40.27#ibcon#wrote, iclass 11, count 0 2006.285.17:58:40.27#ibcon#about to read 3, iclass 11, count 0 2006.285.17:58:40.30#ibcon#read 3, iclass 11, count 0 2006.285.17:58:40.30#ibcon#about to read 4, iclass 11, count 0 2006.285.17:58:40.30#ibcon#read 4, iclass 11, count 0 2006.285.17:58:40.30#ibcon#about to read 5, iclass 11, count 0 2006.285.17:58:40.30#ibcon#read 5, iclass 11, count 0 2006.285.17:58:40.30#ibcon#about to read 6, iclass 11, count 0 2006.285.17:58:40.30#ibcon#read 6, iclass 11, count 0 2006.285.17:58:40.30#ibcon#end of sib2, iclass 11, count 0 2006.285.17:58:40.30#ibcon#*after write, iclass 11, count 0 2006.285.17:58:40.30#ibcon#*before return 0, iclass 11, count 0 2006.285.17:58:40.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:58:40.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.17:58:40.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.17:58:40.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.17:58:40.30$setupk4/ifdk4 2006.285.17:58:40.30$ifdk4/lo= 2006.285.17:58:40.30$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.17:58:40.30$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.17:58:40.30$ifdk4/patch= 2006.285.17:58:40.30$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.17:58:40.30$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.17:58:40.30$setupk4/!*+20s 2006.285.17:58:48.14#trakl#Source acquired 2006.285.17:58:49.58#abcon#<5=/08 0.5 1.0 16.191001014.4\r\n> 2006.285.17:58:49.60#abcon#{5=INTERFACE CLEAR} 2006.285.17:58:49.66#abcon#[5=S1D000X0/0*\r\n] 2006.285.17:58:50.14#flagr#flagr/antenna,acquired 2006.285.17:58:54.33$setupk4/"tpicd 2006.285.17:58:54.33$setupk4/echo=off 2006.285.17:58:54.33$setupk4/xlog=off 2006.285.17:58:54.33:!2006.285.18:00:40 2006.285.18:00:40.00:preob 2006.285.18:00:40.13/onsource/TRACKING 2006.285.18:00:40.13:!2006.285.18:00:50 2006.285.18:00:50.00:"tape 2006.285.18:00:50.00:"st=record 2006.285.18:00:50.00:data_valid=on 2006.285.18:00:50.00:midob 2006.285.18:00:50.13/onsource/TRACKING 2006.285.18:00:50.13/wx/16.16,1014.4,100 2006.285.18:00:50.24/cable/+6.5041E-03 2006.285.18:00:51.33/va/01,07,usb,yes,39,42 2006.285.18:00:51.33/va/02,06,usb,yes,39,40 2006.285.18:00:51.33/va/03,07,usb,yes,38,41 2006.285.18:00:51.33/va/04,06,usb,yes,40,42 2006.285.18:00:51.33/va/05,03,usb,yes,39,40 2006.285.18:00:51.33/va/06,04,usb,yes,36,35 2006.285.18:00:51.33/va/07,04,usb,yes,37,37 2006.285.18:00:51.33/va/08,03,usb,yes,37,45 2006.285.18:00:51.56/valo/01,524.99,yes,locked 2006.285.18:00:51.56/valo/02,534.99,yes,locked 2006.285.18:00:51.56/valo/03,564.99,yes,locked 2006.285.18:00:51.56/valo/04,624.99,yes,locked 2006.285.18:00:51.56/valo/05,734.99,yes,locked 2006.285.18:00:51.56/valo/06,814.99,yes,locked 2006.285.18:00:51.56/valo/07,864.99,yes,locked 2006.285.18:00:51.56/valo/08,884.99,yes,locked 2006.285.18:00:52.65/vb/01,04,usb,yes,33,31 2006.285.18:00:52.65/vb/02,05,usb,yes,32,31 2006.285.18:00:52.65/vb/03,04,usb,yes,33,36 2006.285.18:00:52.65/vb/04,05,usb,yes,33,32 2006.285.18:00:52.65/vb/05,04,usb,yes,29,32 2006.285.18:00:52.65/vb/06,03,usb,yes,42,37 2006.285.18:00:52.65/vb/07,04,usb,yes,34,34 2006.285.18:00:52.65/vb/08,04,usb,yes,31,35 2006.285.18:00:52.88/vblo/01,629.99,yes,locked 2006.285.18:00:52.88/vblo/02,634.99,yes,locked 2006.285.18:00:52.88/vblo/03,649.99,yes,locked 2006.285.18:00:52.88/vblo/04,679.99,yes,locked 2006.285.18:00:52.88/vblo/05,709.99,yes,locked 2006.285.18:00:52.88/vblo/06,719.99,yes,locked 2006.285.18:00:52.88/vblo/07,734.99,yes,locked 2006.285.18:00:52.88/vblo/08,744.99,yes,locked 2006.285.18:00:53.03/vabw/8 2006.285.18:00:53.18/vbbw/8 2006.285.18:00:53.27/xfe/off,on,12.0 2006.285.18:00:53.66/ifatt/23,28,28,28 2006.285.18:00:54.08/fmout-gps/S +2.60E-07 2006.285.18:00:54.10:!2006.285.18:01:30 2006.285.18:01:30.01:data_valid=off 2006.285.18:01:30.01:"et 2006.285.18:01:30.01:!+3s 2006.285.18:01:33.02:"tape 2006.285.18:01:33.02:postob 2006.285.18:01:33.11/cable/+6.5035E-03 2006.285.18:01:33.11/wx/16.13,1014.4,100 2006.285.18:01:34.07/fmout-gps/S +2.59E-07 2006.285.18:01:34.07:scan_name=285-1809,jd0610,110 2006.285.18:01:34.07:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.285.18:01:35.13#flagr#flagr/antenna,new-source 2006.285.18:01:35.13:checkk5 2006.285.18:01:35.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.18:01:36.15/chk_autoobs//k5ts2/ autoobs is running! 2006.285.18:01:36.58/chk_autoobs//k5ts3/ autoobs is running! 2006.285.18:01:36.99/chk_autoobs//k5ts4/ autoobs is running! 2006.285.18:01:37.40/chk_obsdata//k5ts1/T2851800??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.18:01:37.84/chk_obsdata//k5ts2/T2851800??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.18:01:38.29/chk_obsdata//k5ts3/T2851800??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.18:01:38.70/chk_obsdata//k5ts4/T2851800??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.18:01:39.52/k5log//k5ts1_log_newline 2006.285.18:01:40.33/k5log//k5ts2_log_newline 2006.285.18:01:41.08/k5log//k5ts3_log_newline 2006.285.18:01:41.94/k5log//k5ts4_log_newline 2006.285.18:01:41.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.18:01:41.96:setupk4=1 2006.285.18:01:41.96$setupk4/echo=on 2006.285.18:01:41.96$setupk4/pcalon 2006.285.18:01:41.96$pcalon/"no phase cal control is implemented here 2006.285.18:01:41.96$setupk4/"tpicd=stop 2006.285.18:01:41.96$setupk4/"rec=synch_on 2006.285.18:01:41.96$setupk4/"rec_mode=128 2006.285.18:01:41.97$setupk4/!* 2006.285.18:01:41.97$setupk4/recpk4 2006.285.18:01:41.97$recpk4/recpatch= 2006.285.18:01:41.97$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.18:01:41.97$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.18:01:41.97$setupk4/vck44 2006.285.18:01:41.97$vck44/valo=1,524.99 2006.285.18:01:41.97#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.18:01:41.97#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.18:01:41.97#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:41.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:01:41.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:01:41.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:01:41.97#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:01:41.97#ibcon#first serial, iclass 12, count 0 2006.285.18:01:41.97#ibcon#enter sib2, iclass 12, count 0 2006.285.18:01:41.97#ibcon#flushed, iclass 12, count 0 2006.285.18:01:41.97#ibcon#about to write, iclass 12, count 0 2006.285.18:01:41.97#ibcon#wrote, iclass 12, count 0 2006.285.18:01:41.97#ibcon#about to read 3, iclass 12, count 0 2006.285.18:01:41.99#ibcon#read 3, iclass 12, count 0 2006.285.18:01:41.99#ibcon#about to read 4, iclass 12, count 0 2006.285.18:01:41.99#ibcon#read 4, iclass 12, count 0 2006.285.18:01:41.99#ibcon#about to read 5, iclass 12, count 0 2006.285.18:01:41.99#ibcon#read 5, iclass 12, count 0 2006.285.18:01:41.99#ibcon#about to read 6, iclass 12, count 0 2006.285.18:01:41.99#ibcon#read 6, iclass 12, count 0 2006.285.18:01:41.99#ibcon#end of sib2, iclass 12, count 0 2006.285.18:01:41.99#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:01:41.99#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:01:41.99#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.18:01:41.99#ibcon#*before write, iclass 12, count 0 2006.285.18:01:41.99#ibcon#enter sib2, iclass 12, count 0 2006.285.18:01:41.99#ibcon#flushed, iclass 12, count 0 2006.285.18:01:41.99#ibcon#about to write, iclass 12, count 0 2006.285.18:01:41.99#ibcon#wrote, iclass 12, count 0 2006.285.18:01:41.99#ibcon#about to read 3, iclass 12, count 0 2006.285.18:01:42.04#ibcon#read 3, iclass 12, count 0 2006.285.18:01:42.04#ibcon#about to read 4, iclass 12, count 0 2006.285.18:01:42.04#ibcon#read 4, iclass 12, count 0 2006.285.18:01:42.04#ibcon#about to read 5, iclass 12, count 0 2006.285.18:01:42.04#ibcon#read 5, iclass 12, count 0 2006.285.18:01:42.04#ibcon#about to read 6, iclass 12, count 0 2006.285.18:01:42.04#ibcon#read 6, iclass 12, count 0 2006.285.18:01:42.04#ibcon#end of sib2, iclass 12, count 0 2006.285.18:01:42.04#ibcon#*after write, iclass 12, count 0 2006.285.18:01:42.04#ibcon#*before return 0, iclass 12, count 0 2006.285.18:01:42.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:01:42.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:01:42.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:01:42.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:01:42.04$vck44/va=1,7 2006.285.18:01:42.04#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.18:01:42.04#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.18:01:42.04#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:42.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:01:42.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:01:42.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:01:42.04#ibcon#enter wrdev, iclass 14, count 2 2006.285.18:01:42.04#ibcon#first serial, iclass 14, count 2 2006.285.18:01:42.04#ibcon#enter sib2, iclass 14, count 2 2006.285.18:01:42.04#ibcon#flushed, iclass 14, count 2 2006.285.18:01:42.04#ibcon#about to write, iclass 14, count 2 2006.285.18:01:42.04#ibcon#wrote, iclass 14, count 2 2006.285.18:01:42.04#ibcon#about to read 3, iclass 14, count 2 2006.285.18:01:42.06#ibcon#read 3, iclass 14, count 2 2006.285.18:01:42.06#ibcon#about to read 4, iclass 14, count 2 2006.285.18:01:42.06#ibcon#read 4, iclass 14, count 2 2006.285.18:01:42.06#ibcon#about to read 5, iclass 14, count 2 2006.285.18:01:42.06#ibcon#read 5, iclass 14, count 2 2006.285.18:01:42.06#ibcon#about to read 6, iclass 14, count 2 2006.285.18:01:42.06#ibcon#read 6, iclass 14, count 2 2006.285.18:01:42.06#ibcon#end of sib2, iclass 14, count 2 2006.285.18:01:42.06#ibcon#*mode == 0, iclass 14, count 2 2006.285.18:01:42.06#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.18:01:42.06#ibcon#[25=AT01-07\r\n] 2006.285.18:01:42.06#ibcon#*before write, iclass 14, count 2 2006.285.18:01:42.06#ibcon#enter sib2, iclass 14, count 2 2006.285.18:01:42.06#ibcon#flushed, iclass 14, count 2 2006.285.18:01:42.06#ibcon#about to write, iclass 14, count 2 2006.285.18:01:42.06#ibcon#wrote, iclass 14, count 2 2006.285.18:01:42.06#ibcon#about to read 3, iclass 14, count 2 2006.285.18:01:42.09#ibcon#read 3, iclass 14, count 2 2006.285.18:01:42.09#ibcon#about to read 4, iclass 14, count 2 2006.285.18:01:42.09#ibcon#read 4, iclass 14, count 2 2006.285.18:01:42.09#ibcon#about to read 5, iclass 14, count 2 2006.285.18:01:42.09#ibcon#read 5, iclass 14, count 2 2006.285.18:01:42.09#ibcon#about to read 6, iclass 14, count 2 2006.285.18:01:42.09#ibcon#read 6, iclass 14, count 2 2006.285.18:01:42.09#ibcon#end of sib2, iclass 14, count 2 2006.285.18:01:42.09#ibcon#*after write, iclass 14, count 2 2006.285.18:01:42.09#ibcon#*before return 0, iclass 14, count 2 2006.285.18:01:42.09#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:01:42.09#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:01:42.09#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.18:01:42.09#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:42.09#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:01:42.21#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:01:42.21#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:01:42.21#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:01:42.21#ibcon#first serial, iclass 14, count 0 2006.285.18:01:42.21#ibcon#enter sib2, iclass 14, count 0 2006.285.18:01:42.21#ibcon#flushed, iclass 14, count 0 2006.285.18:01:42.21#ibcon#about to write, iclass 14, count 0 2006.285.18:01:42.21#ibcon#wrote, iclass 14, count 0 2006.285.18:01:42.21#ibcon#about to read 3, iclass 14, count 0 2006.285.18:01:42.23#ibcon#read 3, iclass 14, count 0 2006.285.18:01:42.23#ibcon#about to read 4, iclass 14, count 0 2006.285.18:01:42.23#ibcon#read 4, iclass 14, count 0 2006.285.18:01:42.23#ibcon#about to read 5, iclass 14, count 0 2006.285.18:01:42.23#ibcon#read 5, iclass 14, count 0 2006.285.18:01:42.23#ibcon#about to read 6, iclass 14, count 0 2006.285.18:01:42.23#ibcon#read 6, iclass 14, count 0 2006.285.18:01:42.23#ibcon#end of sib2, iclass 14, count 0 2006.285.18:01:42.23#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:01:42.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:01:42.23#ibcon#[25=USB\r\n] 2006.285.18:01:42.23#ibcon#*before write, iclass 14, count 0 2006.285.18:01:42.23#ibcon#enter sib2, iclass 14, count 0 2006.285.18:01:42.23#ibcon#flushed, iclass 14, count 0 2006.285.18:01:42.23#ibcon#about to write, iclass 14, count 0 2006.285.18:01:42.23#ibcon#wrote, iclass 14, count 0 2006.285.18:01:42.23#ibcon#about to read 3, iclass 14, count 0 2006.285.18:01:42.26#ibcon#read 3, iclass 14, count 0 2006.285.18:01:42.26#ibcon#about to read 4, iclass 14, count 0 2006.285.18:01:42.26#ibcon#read 4, iclass 14, count 0 2006.285.18:01:42.26#ibcon#about to read 5, iclass 14, count 0 2006.285.18:01:42.26#ibcon#read 5, iclass 14, count 0 2006.285.18:01:42.26#ibcon#about to read 6, iclass 14, count 0 2006.285.18:01:42.26#ibcon#read 6, iclass 14, count 0 2006.285.18:01:42.26#ibcon#end of sib2, iclass 14, count 0 2006.285.18:01:42.26#ibcon#*after write, iclass 14, count 0 2006.285.18:01:42.26#ibcon#*before return 0, iclass 14, count 0 2006.285.18:01:42.26#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:01:42.26#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:01:42.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:01:42.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:01:42.26$vck44/valo=2,534.99 2006.285.18:01:42.26#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.18:01:42.26#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.18:01:42.26#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:42.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:01:42.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:01:42.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:01:42.26#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:01:42.26#ibcon#first serial, iclass 16, count 0 2006.285.18:01:42.26#ibcon#enter sib2, iclass 16, count 0 2006.285.18:01:42.26#ibcon#flushed, iclass 16, count 0 2006.285.18:01:42.26#ibcon#about to write, iclass 16, count 0 2006.285.18:01:42.26#ibcon#wrote, iclass 16, count 0 2006.285.18:01:42.26#ibcon#about to read 3, iclass 16, count 0 2006.285.18:01:42.28#ibcon#read 3, iclass 16, count 0 2006.285.18:01:42.28#ibcon#about to read 4, iclass 16, count 0 2006.285.18:01:42.28#ibcon#read 4, iclass 16, count 0 2006.285.18:01:42.28#ibcon#about to read 5, iclass 16, count 0 2006.285.18:01:42.28#ibcon#read 5, iclass 16, count 0 2006.285.18:01:42.28#ibcon#about to read 6, iclass 16, count 0 2006.285.18:01:42.28#ibcon#read 6, iclass 16, count 0 2006.285.18:01:42.28#ibcon#end of sib2, iclass 16, count 0 2006.285.18:01:42.28#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:01:42.28#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:01:42.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.18:01:42.28#ibcon#*before write, iclass 16, count 0 2006.285.18:01:42.28#ibcon#enter sib2, iclass 16, count 0 2006.285.18:01:42.28#ibcon#flushed, iclass 16, count 0 2006.285.18:01:42.28#ibcon#about to write, iclass 16, count 0 2006.285.18:01:42.28#ibcon#wrote, iclass 16, count 0 2006.285.18:01:42.28#ibcon#about to read 3, iclass 16, count 0 2006.285.18:01:42.32#ibcon#read 3, iclass 16, count 0 2006.285.18:01:42.32#ibcon#about to read 4, iclass 16, count 0 2006.285.18:01:42.32#ibcon#read 4, iclass 16, count 0 2006.285.18:01:42.32#ibcon#about to read 5, iclass 16, count 0 2006.285.18:01:42.32#ibcon#read 5, iclass 16, count 0 2006.285.18:01:42.32#ibcon#about to read 6, iclass 16, count 0 2006.285.18:01:42.32#ibcon#read 6, iclass 16, count 0 2006.285.18:01:42.32#ibcon#end of sib2, iclass 16, count 0 2006.285.18:01:42.32#ibcon#*after write, iclass 16, count 0 2006.285.18:01:42.32#ibcon#*before return 0, iclass 16, count 0 2006.285.18:01:42.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:01:42.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:01:42.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:01:42.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:01:42.32$vck44/va=2,6 2006.285.18:01:42.32#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.18:01:42.32#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.18:01:42.32#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:42.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:01:42.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:01:42.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:01:42.38#ibcon#enter wrdev, iclass 18, count 2 2006.285.18:01:42.38#ibcon#first serial, iclass 18, count 2 2006.285.18:01:42.38#ibcon#enter sib2, iclass 18, count 2 2006.285.18:01:42.38#ibcon#flushed, iclass 18, count 2 2006.285.18:01:42.38#ibcon#about to write, iclass 18, count 2 2006.285.18:01:42.38#ibcon#wrote, iclass 18, count 2 2006.285.18:01:42.38#ibcon#about to read 3, iclass 18, count 2 2006.285.18:01:42.40#ibcon#read 3, iclass 18, count 2 2006.285.18:01:42.40#ibcon#about to read 4, iclass 18, count 2 2006.285.18:01:42.40#ibcon#read 4, iclass 18, count 2 2006.285.18:01:42.40#ibcon#about to read 5, iclass 18, count 2 2006.285.18:01:42.40#ibcon#read 5, iclass 18, count 2 2006.285.18:01:42.40#ibcon#about to read 6, iclass 18, count 2 2006.285.18:01:42.40#ibcon#read 6, iclass 18, count 2 2006.285.18:01:42.40#ibcon#end of sib2, iclass 18, count 2 2006.285.18:01:42.40#ibcon#*mode == 0, iclass 18, count 2 2006.285.18:01:42.40#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.18:01:42.40#ibcon#[25=AT02-06\r\n] 2006.285.18:01:42.40#ibcon#*before write, iclass 18, count 2 2006.285.18:01:42.40#ibcon#enter sib2, iclass 18, count 2 2006.285.18:01:42.40#ibcon#flushed, iclass 18, count 2 2006.285.18:01:42.40#ibcon#about to write, iclass 18, count 2 2006.285.18:01:42.40#ibcon#wrote, iclass 18, count 2 2006.285.18:01:42.40#ibcon#about to read 3, iclass 18, count 2 2006.285.18:01:42.43#ibcon#read 3, iclass 18, count 2 2006.285.18:01:42.43#ibcon#about to read 4, iclass 18, count 2 2006.285.18:01:42.43#ibcon#read 4, iclass 18, count 2 2006.285.18:01:42.43#ibcon#about to read 5, iclass 18, count 2 2006.285.18:01:42.43#ibcon#read 5, iclass 18, count 2 2006.285.18:01:42.43#ibcon#about to read 6, iclass 18, count 2 2006.285.18:01:42.43#ibcon#read 6, iclass 18, count 2 2006.285.18:01:42.43#ibcon#end of sib2, iclass 18, count 2 2006.285.18:01:42.43#ibcon#*after write, iclass 18, count 2 2006.285.18:01:42.43#ibcon#*before return 0, iclass 18, count 2 2006.285.18:01:42.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:01:42.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:01:42.43#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.18:01:42.43#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:42.43#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:01:42.47#abcon#<5=/08 0.5 1.0 16.131001014.4\r\n> 2006.285.18:01:42.49#abcon#{5=INTERFACE CLEAR} 2006.285.18:01:42.55#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:01:42.55#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:01:42.55#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:01:42.55#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:01:42.55#ibcon#first serial, iclass 18, count 0 2006.285.18:01:42.55#ibcon#enter sib2, iclass 18, count 0 2006.285.18:01:42.55#ibcon#flushed, iclass 18, count 0 2006.285.18:01:42.55#ibcon#about to write, iclass 18, count 0 2006.285.18:01:42.55#ibcon#wrote, iclass 18, count 0 2006.285.18:01:42.55#ibcon#about to read 3, iclass 18, count 0 2006.285.18:01:42.57#ibcon#read 3, iclass 18, count 0 2006.285.18:01:42.57#ibcon#about to read 4, iclass 18, count 0 2006.285.18:01:42.57#ibcon#read 4, iclass 18, count 0 2006.285.18:01:42.57#ibcon#about to read 5, iclass 18, count 0 2006.285.18:01:42.57#ibcon#read 5, iclass 18, count 0 2006.285.18:01:42.57#ibcon#about to read 6, iclass 18, count 0 2006.285.18:01:42.57#ibcon#read 6, iclass 18, count 0 2006.285.18:01:42.57#ibcon#end of sib2, iclass 18, count 0 2006.285.18:01:42.57#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:01:42.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:01:42.57#ibcon#[25=USB\r\n] 2006.285.18:01:42.57#ibcon#*before write, iclass 18, count 0 2006.285.18:01:42.57#ibcon#enter sib2, iclass 18, count 0 2006.285.18:01:42.57#ibcon#flushed, iclass 18, count 0 2006.285.18:01:42.57#ibcon#about to write, iclass 18, count 0 2006.285.18:01:42.57#ibcon#wrote, iclass 18, count 0 2006.285.18:01:42.57#ibcon#about to read 3, iclass 18, count 0 2006.285.18:01:42.60#ibcon#read 3, iclass 18, count 0 2006.285.18:01:42.60#ibcon#about to read 4, iclass 18, count 0 2006.285.18:01:42.60#ibcon#read 4, iclass 18, count 0 2006.285.18:01:42.60#ibcon#about to read 5, iclass 18, count 0 2006.285.18:01:42.60#ibcon#read 5, iclass 18, count 0 2006.285.18:01:42.60#ibcon#about to read 6, iclass 18, count 0 2006.285.18:01:42.60#ibcon#read 6, iclass 18, count 0 2006.285.18:01:42.60#ibcon#end of sib2, iclass 18, count 0 2006.285.18:01:42.60#ibcon#*after write, iclass 18, count 0 2006.285.18:01:42.60#ibcon#*before return 0, iclass 18, count 0 2006.285.18:01:42.60#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:01:42.60#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:01:42.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:01:42.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:01:42.60$vck44/valo=3,564.99 2006.285.18:01:42.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.18:01:42.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.18:01:42.60#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:42.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:01:42.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:01:42.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:01:42.60#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:01:42.60#ibcon#first serial, iclass 24, count 0 2006.285.18:01:42.60#ibcon#enter sib2, iclass 24, count 0 2006.285.18:01:42.60#ibcon#flushed, iclass 24, count 0 2006.285.18:01:42.60#ibcon#about to write, iclass 24, count 0 2006.285.18:01:42.60#ibcon#wrote, iclass 24, count 0 2006.285.18:01:42.60#ibcon#about to read 3, iclass 24, count 0 2006.285.18:01:42.62#ibcon#read 3, iclass 24, count 0 2006.285.18:01:42.62#ibcon#about to read 4, iclass 24, count 0 2006.285.18:01:42.62#ibcon#read 4, iclass 24, count 0 2006.285.18:01:42.62#ibcon#about to read 5, iclass 24, count 0 2006.285.18:01:42.62#ibcon#read 5, iclass 24, count 0 2006.285.18:01:42.62#ibcon#about to read 6, iclass 24, count 0 2006.285.18:01:42.62#ibcon#read 6, iclass 24, count 0 2006.285.18:01:42.62#ibcon#end of sib2, iclass 24, count 0 2006.285.18:01:42.62#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:01:42.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:01:42.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.18:01:42.62#ibcon#*before write, iclass 24, count 0 2006.285.18:01:42.62#ibcon#enter sib2, iclass 24, count 0 2006.285.18:01:42.62#ibcon#flushed, iclass 24, count 0 2006.285.18:01:42.62#ibcon#about to write, iclass 24, count 0 2006.285.18:01:42.62#ibcon#wrote, iclass 24, count 0 2006.285.18:01:42.62#ibcon#about to read 3, iclass 24, count 0 2006.285.18:01:42.66#ibcon#read 3, iclass 24, count 0 2006.285.18:01:42.66#ibcon#about to read 4, iclass 24, count 0 2006.285.18:01:42.66#ibcon#read 4, iclass 24, count 0 2006.285.18:01:42.66#ibcon#about to read 5, iclass 24, count 0 2006.285.18:01:42.66#ibcon#read 5, iclass 24, count 0 2006.285.18:01:42.66#ibcon#about to read 6, iclass 24, count 0 2006.285.18:01:42.66#ibcon#read 6, iclass 24, count 0 2006.285.18:01:42.66#ibcon#end of sib2, iclass 24, count 0 2006.285.18:01:42.66#ibcon#*after write, iclass 24, count 0 2006.285.18:01:42.66#ibcon#*before return 0, iclass 24, count 0 2006.285.18:01:42.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:01:42.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:01:42.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:01:42.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:01:42.66$vck44/va=3,7 2006.285.18:01:42.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.18:01:42.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.18:01:42.66#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:42.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:01:42.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:01:42.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:01:42.72#ibcon#enter wrdev, iclass 26, count 2 2006.285.18:01:42.72#ibcon#first serial, iclass 26, count 2 2006.285.18:01:42.72#ibcon#enter sib2, iclass 26, count 2 2006.285.18:01:42.72#ibcon#flushed, iclass 26, count 2 2006.285.18:01:42.72#ibcon#about to write, iclass 26, count 2 2006.285.18:01:42.72#ibcon#wrote, iclass 26, count 2 2006.285.18:01:42.72#ibcon#about to read 3, iclass 26, count 2 2006.285.18:01:42.74#ibcon#read 3, iclass 26, count 2 2006.285.18:01:42.74#ibcon#about to read 4, iclass 26, count 2 2006.285.18:01:42.74#ibcon#read 4, iclass 26, count 2 2006.285.18:01:42.74#ibcon#about to read 5, iclass 26, count 2 2006.285.18:01:42.74#ibcon#read 5, iclass 26, count 2 2006.285.18:01:42.74#ibcon#about to read 6, iclass 26, count 2 2006.285.18:01:42.74#ibcon#read 6, iclass 26, count 2 2006.285.18:01:42.74#ibcon#end of sib2, iclass 26, count 2 2006.285.18:01:42.74#ibcon#*mode == 0, iclass 26, count 2 2006.285.18:01:42.74#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.18:01:43.11#ibcon#[25=AT03-07\r\n] 2006.285.18:01:43.11#ibcon#*before write, iclass 26, count 2 2006.285.18:01:43.11#ibcon#enter sib2, iclass 26, count 2 2006.285.18:01:43.11#ibcon#flushed, iclass 26, count 2 2006.285.18:01:43.11#ibcon#about to write, iclass 26, count 2 2006.285.18:01:43.11#ibcon#wrote, iclass 26, count 2 2006.285.18:01:43.11#ibcon#about to read 3, iclass 26, count 2 2006.285.18:01:43.14#ibcon#read 3, iclass 26, count 2 2006.285.18:01:43.14#ibcon#about to read 4, iclass 26, count 2 2006.285.18:01:43.14#ibcon#read 4, iclass 26, count 2 2006.285.18:01:43.14#ibcon#about to read 5, iclass 26, count 2 2006.285.18:01:43.14#ibcon#read 5, iclass 26, count 2 2006.285.18:01:43.14#ibcon#about to read 6, iclass 26, count 2 2006.285.18:01:43.14#ibcon#read 6, iclass 26, count 2 2006.285.18:01:43.14#ibcon#end of sib2, iclass 26, count 2 2006.285.18:01:43.14#ibcon#*after write, iclass 26, count 2 2006.285.18:01:43.14#ibcon#*before return 0, iclass 26, count 2 2006.285.18:01:43.14#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:01:43.14#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:01:43.14#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.18:01:43.14#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:43.14#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:01:43.26#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:01:43.26#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:01:43.26#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:01:43.26#ibcon#first serial, iclass 26, count 0 2006.285.18:01:43.26#ibcon#enter sib2, iclass 26, count 0 2006.285.18:01:43.26#ibcon#flushed, iclass 26, count 0 2006.285.18:01:43.26#ibcon#about to write, iclass 26, count 0 2006.285.18:01:43.26#ibcon#wrote, iclass 26, count 0 2006.285.18:01:43.26#ibcon#about to read 3, iclass 26, count 0 2006.285.18:01:43.28#ibcon#read 3, iclass 26, count 0 2006.285.18:01:43.28#ibcon#about to read 4, iclass 26, count 0 2006.285.18:01:43.28#ibcon#read 4, iclass 26, count 0 2006.285.18:01:43.28#ibcon#about to read 5, iclass 26, count 0 2006.285.18:01:43.28#ibcon#read 5, iclass 26, count 0 2006.285.18:01:43.28#ibcon#about to read 6, iclass 26, count 0 2006.285.18:01:43.28#ibcon#read 6, iclass 26, count 0 2006.285.18:01:43.28#ibcon#end of sib2, iclass 26, count 0 2006.285.18:01:43.28#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:01:43.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:01:43.28#ibcon#[25=USB\r\n] 2006.285.18:01:43.28#ibcon#*before write, iclass 26, count 0 2006.285.18:01:43.28#ibcon#enter sib2, iclass 26, count 0 2006.285.18:01:43.28#ibcon#flushed, iclass 26, count 0 2006.285.18:01:43.28#ibcon#about to write, iclass 26, count 0 2006.285.18:01:43.28#ibcon#wrote, iclass 26, count 0 2006.285.18:01:43.28#ibcon#about to read 3, iclass 26, count 0 2006.285.18:01:43.31#ibcon#read 3, iclass 26, count 0 2006.285.18:01:43.31#ibcon#about to read 4, iclass 26, count 0 2006.285.18:01:43.31#ibcon#read 4, iclass 26, count 0 2006.285.18:01:43.31#ibcon#about to read 5, iclass 26, count 0 2006.285.18:01:43.31#ibcon#read 5, iclass 26, count 0 2006.285.18:01:43.31#ibcon#about to read 6, iclass 26, count 0 2006.285.18:01:43.31#ibcon#read 6, iclass 26, count 0 2006.285.18:01:43.31#ibcon#end of sib2, iclass 26, count 0 2006.285.18:01:43.31#ibcon#*after write, iclass 26, count 0 2006.285.18:01:43.31#ibcon#*before return 0, iclass 26, count 0 2006.285.18:01:43.31#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:01:43.31#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:01:43.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:01:43.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:01:43.31$vck44/valo=4,624.99 2006.285.18:01:43.31#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.18:01:43.31#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.18:01:43.31#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:43.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:01:43.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:01:43.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:01:43.31#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:01:43.31#ibcon#first serial, iclass 28, count 0 2006.285.18:01:43.31#ibcon#enter sib2, iclass 28, count 0 2006.285.18:01:43.31#ibcon#flushed, iclass 28, count 0 2006.285.18:01:43.31#ibcon#about to write, iclass 28, count 0 2006.285.18:01:43.31#ibcon#wrote, iclass 28, count 0 2006.285.18:01:43.31#ibcon#about to read 3, iclass 28, count 0 2006.285.18:01:43.33#ibcon#read 3, iclass 28, count 0 2006.285.18:01:43.81#ibcon#about to read 4, iclass 28, count 0 2006.285.18:01:43.81#ibcon#read 4, iclass 28, count 0 2006.285.18:01:43.81#ibcon#about to read 5, iclass 28, count 0 2006.285.18:01:43.81#ibcon#read 5, iclass 28, count 0 2006.285.18:01:43.81#ibcon#about to read 6, iclass 28, count 0 2006.285.18:01:43.81#ibcon#read 6, iclass 28, count 0 2006.285.18:01:43.81#ibcon#end of sib2, iclass 28, count 0 2006.285.18:01:43.81#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:01:43.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:01:43.81#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.18:01:43.81#ibcon#*before write, iclass 28, count 0 2006.285.18:01:43.81#ibcon#enter sib2, iclass 28, count 0 2006.285.18:01:43.81#ibcon#flushed, iclass 28, count 0 2006.285.18:01:43.81#ibcon#about to write, iclass 28, count 0 2006.285.18:01:43.81#ibcon#wrote, iclass 28, count 0 2006.285.18:01:43.81#ibcon#about to read 3, iclass 28, count 0 2006.285.18:01:43.85#ibcon#read 3, iclass 28, count 0 2006.285.18:01:43.85#ibcon#about to read 4, iclass 28, count 0 2006.285.18:01:43.85#ibcon#read 4, iclass 28, count 0 2006.285.18:01:43.85#ibcon#about to read 5, iclass 28, count 0 2006.285.18:01:43.85#ibcon#read 5, iclass 28, count 0 2006.285.18:01:43.85#ibcon#about to read 6, iclass 28, count 0 2006.285.18:01:43.85#ibcon#read 6, iclass 28, count 0 2006.285.18:01:43.85#ibcon#end of sib2, iclass 28, count 0 2006.285.18:01:43.85#ibcon#*after write, iclass 28, count 0 2006.285.18:01:43.85#ibcon#*before return 0, iclass 28, count 0 2006.285.18:01:43.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:01:43.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:01:43.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:01:43.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:01:43.85$vck44/va=4,6 2006.285.18:01:43.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.18:01:43.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.18:01:43.85#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:43.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:01:43.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:01:43.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:01:43.85#ibcon#enter wrdev, iclass 30, count 2 2006.285.18:01:43.85#ibcon#first serial, iclass 30, count 2 2006.285.18:01:43.85#ibcon#enter sib2, iclass 30, count 2 2006.285.18:01:43.85#ibcon#flushed, iclass 30, count 2 2006.285.18:01:43.85#ibcon#about to write, iclass 30, count 2 2006.285.18:01:43.85#ibcon#wrote, iclass 30, count 2 2006.285.18:01:43.85#ibcon#about to read 3, iclass 30, count 2 2006.285.18:01:43.87#ibcon#read 3, iclass 30, count 2 2006.285.18:01:43.87#ibcon#about to read 4, iclass 30, count 2 2006.285.18:01:43.87#ibcon#read 4, iclass 30, count 2 2006.285.18:01:43.87#ibcon#about to read 5, iclass 30, count 2 2006.285.18:01:43.87#ibcon#read 5, iclass 30, count 2 2006.285.18:01:43.87#ibcon#about to read 6, iclass 30, count 2 2006.285.18:01:43.87#ibcon#read 6, iclass 30, count 2 2006.285.18:01:43.87#ibcon#end of sib2, iclass 30, count 2 2006.285.18:01:43.87#ibcon#*mode == 0, iclass 30, count 2 2006.285.18:01:43.87#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.18:01:43.87#ibcon#[25=AT04-06\r\n] 2006.285.18:01:43.87#ibcon#*before write, iclass 30, count 2 2006.285.18:01:43.87#ibcon#enter sib2, iclass 30, count 2 2006.285.18:01:43.87#ibcon#flushed, iclass 30, count 2 2006.285.18:01:43.87#ibcon#about to write, iclass 30, count 2 2006.285.18:01:43.87#ibcon#wrote, iclass 30, count 2 2006.285.18:01:43.87#ibcon#about to read 3, iclass 30, count 2 2006.285.18:01:43.90#ibcon#read 3, iclass 30, count 2 2006.285.18:01:43.90#ibcon#about to read 4, iclass 30, count 2 2006.285.18:01:43.90#ibcon#read 4, iclass 30, count 2 2006.285.18:01:43.90#ibcon#about to read 5, iclass 30, count 2 2006.285.18:01:43.90#ibcon#read 5, iclass 30, count 2 2006.285.18:01:43.90#ibcon#about to read 6, iclass 30, count 2 2006.285.18:01:43.90#ibcon#read 6, iclass 30, count 2 2006.285.18:01:43.90#ibcon#end of sib2, iclass 30, count 2 2006.285.18:01:43.90#ibcon#*after write, iclass 30, count 2 2006.285.18:01:43.90#ibcon#*before return 0, iclass 30, count 2 2006.285.18:01:43.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:01:43.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:01:43.90#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.18:01:43.90#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:43.90#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:01:44.02#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:01:44.02#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:01:44.02#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:01:44.02#ibcon#first serial, iclass 30, count 0 2006.285.18:01:44.02#ibcon#enter sib2, iclass 30, count 0 2006.285.18:01:44.02#ibcon#flushed, iclass 30, count 0 2006.285.18:01:44.02#ibcon#about to write, iclass 30, count 0 2006.285.18:01:44.02#ibcon#wrote, iclass 30, count 0 2006.285.18:01:44.02#ibcon#about to read 3, iclass 30, count 0 2006.285.18:01:44.04#ibcon#read 3, iclass 30, count 0 2006.285.18:01:44.04#ibcon#about to read 4, iclass 30, count 0 2006.285.18:01:44.04#ibcon#read 4, iclass 30, count 0 2006.285.18:01:44.04#ibcon#about to read 5, iclass 30, count 0 2006.285.18:01:44.04#ibcon#read 5, iclass 30, count 0 2006.285.18:01:44.04#ibcon#about to read 6, iclass 30, count 0 2006.285.18:01:44.04#ibcon#read 6, iclass 30, count 0 2006.285.18:01:44.04#ibcon#end of sib2, iclass 30, count 0 2006.285.18:01:44.04#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:01:44.04#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:01:44.04#ibcon#[25=USB\r\n] 2006.285.18:01:44.04#ibcon#*before write, iclass 30, count 0 2006.285.18:01:44.04#ibcon#enter sib2, iclass 30, count 0 2006.285.18:01:44.04#ibcon#flushed, iclass 30, count 0 2006.285.18:01:44.04#ibcon#about to write, iclass 30, count 0 2006.285.18:01:44.04#ibcon#wrote, iclass 30, count 0 2006.285.18:01:44.04#ibcon#about to read 3, iclass 30, count 0 2006.285.18:01:44.07#ibcon#read 3, iclass 30, count 0 2006.285.18:01:44.07#ibcon#about to read 4, iclass 30, count 0 2006.285.18:01:44.07#ibcon#read 4, iclass 30, count 0 2006.285.18:01:44.07#ibcon#about to read 5, iclass 30, count 0 2006.285.18:01:44.07#ibcon#read 5, iclass 30, count 0 2006.285.18:01:44.07#ibcon#about to read 6, iclass 30, count 0 2006.285.18:01:44.07#ibcon#read 6, iclass 30, count 0 2006.285.18:01:44.07#ibcon#end of sib2, iclass 30, count 0 2006.285.18:01:44.07#ibcon#*after write, iclass 30, count 0 2006.285.18:01:44.07#ibcon#*before return 0, iclass 30, count 0 2006.285.18:01:44.07#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:01:44.07#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:01:44.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:01:44.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:01:44.07$vck44/valo=5,734.99 2006.285.18:01:44.07#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.18:01:44.07#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.18:01:44.07#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:44.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:01:44.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:01:44.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:01:44.07#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:01:44.07#ibcon#first serial, iclass 32, count 0 2006.285.18:01:44.07#ibcon#enter sib2, iclass 32, count 0 2006.285.18:01:44.07#ibcon#flushed, iclass 32, count 0 2006.285.18:01:44.07#ibcon#about to write, iclass 32, count 0 2006.285.18:01:44.07#ibcon#wrote, iclass 32, count 0 2006.285.18:01:44.07#ibcon#about to read 3, iclass 32, count 0 2006.285.18:01:44.09#ibcon#read 3, iclass 32, count 0 2006.285.18:01:44.09#ibcon#about to read 4, iclass 32, count 0 2006.285.18:01:44.09#ibcon#read 4, iclass 32, count 0 2006.285.18:01:44.09#ibcon#about to read 5, iclass 32, count 0 2006.285.18:01:44.09#ibcon#read 5, iclass 32, count 0 2006.285.18:01:44.09#ibcon#about to read 6, iclass 32, count 0 2006.285.18:01:44.09#ibcon#read 6, iclass 32, count 0 2006.285.18:01:44.09#ibcon#end of sib2, iclass 32, count 0 2006.285.18:01:44.09#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:01:44.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:01:44.09#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.18:01:44.09#ibcon#*before write, iclass 32, count 0 2006.285.18:01:44.09#ibcon#enter sib2, iclass 32, count 0 2006.285.18:01:44.09#ibcon#flushed, iclass 32, count 0 2006.285.18:01:44.09#ibcon#about to write, iclass 32, count 0 2006.285.18:01:44.09#ibcon#wrote, iclass 32, count 0 2006.285.18:01:44.09#ibcon#about to read 3, iclass 32, count 0 2006.285.18:01:44.13#ibcon#read 3, iclass 32, count 0 2006.285.18:01:44.13#ibcon#about to read 4, iclass 32, count 0 2006.285.18:01:44.13#ibcon#read 4, iclass 32, count 0 2006.285.18:01:44.13#ibcon#about to read 5, iclass 32, count 0 2006.285.18:01:44.13#ibcon#read 5, iclass 32, count 0 2006.285.18:01:44.13#ibcon#about to read 6, iclass 32, count 0 2006.285.18:01:44.13#ibcon#read 6, iclass 32, count 0 2006.285.18:01:44.13#ibcon#end of sib2, iclass 32, count 0 2006.285.18:01:44.13#ibcon#*after write, iclass 32, count 0 2006.285.18:01:44.13#ibcon#*before return 0, iclass 32, count 0 2006.285.18:01:44.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:01:44.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:01:44.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:01:44.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:01:44.13$vck44/va=5,3 2006.285.18:01:44.13#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.18:01:44.13#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.18:01:44.13#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:44.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:01:44.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:01:44.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:01:44.19#ibcon#enter wrdev, iclass 34, count 2 2006.285.18:01:44.19#ibcon#first serial, iclass 34, count 2 2006.285.18:01:44.19#ibcon#enter sib2, iclass 34, count 2 2006.285.18:01:44.19#ibcon#flushed, iclass 34, count 2 2006.285.18:01:44.19#ibcon#about to write, iclass 34, count 2 2006.285.18:01:44.19#ibcon#wrote, iclass 34, count 2 2006.285.18:01:44.19#ibcon#about to read 3, iclass 34, count 2 2006.285.18:01:44.21#ibcon#read 3, iclass 34, count 2 2006.285.18:01:44.21#ibcon#about to read 4, iclass 34, count 2 2006.285.18:01:44.21#ibcon#read 4, iclass 34, count 2 2006.285.18:01:44.21#ibcon#about to read 5, iclass 34, count 2 2006.285.18:01:44.21#ibcon#read 5, iclass 34, count 2 2006.285.18:01:44.21#ibcon#about to read 6, iclass 34, count 2 2006.285.18:01:44.21#ibcon#read 6, iclass 34, count 2 2006.285.18:01:44.21#ibcon#end of sib2, iclass 34, count 2 2006.285.18:01:44.21#ibcon#*mode == 0, iclass 34, count 2 2006.285.18:01:44.21#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.18:01:44.21#ibcon#[25=AT05-03\r\n] 2006.285.18:01:44.21#ibcon#*before write, iclass 34, count 2 2006.285.18:01:44.21#ibcon#enter sib2, iclass 34, count 2 2006.285.18:01:44.21#ibcon#flushed, iclass 34, count 2 2006.285.18:01:44.21#ibcon#about to write, iclass 34, count 2 2006.285.18:01:44.21#ibcon#wrote, iclass 34, count 2 2006.285.18:01:44.21#ibcon#about to read 3, iclass 34, count 2 2006.285.18:01:44.24#ibcon#read 3, iclass 34, count 2 2006.285.18:01:44.24#ibcon#about to read 4, iclass 34, count 2 2006.285.18:01:44.24#ibcon#read 4, iclass 34, count 2 2006.285.18:01:44.24#ibcon#about to read 5, iclass 34, count 2 2006.285.18:01:44.24#ibcon#read 5, iclass 34, count 2 2006.285.18:01:44.24#ibcon#about to read 6, iclass 34, count 2 2006.285.18:01:44.24#ibcon#read 6, iclass 34, count 2 2006.285.18:01:44.24#ibcon#end of sib2, iclass 34, count 2 2006.285.18:01:44.24#ibcon#*after write, iclass 34, count 2 2006.285.18:01:44.24#ibcon#*before return 0, iclass 34, count 2 2006.285.18:01:44.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:01:44.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:01:44.24#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.18:01:44.24#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:44.24#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:01:44.36#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:01:44.36#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:01:44.36#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:01:44.36#ibcon#first serial, iclass 34, count 0 2006.285.18:01:44.36#ibcon#enter sib2, iclass 34, count 0 2006.285.18:01:44.36#ibcon#flushed, iclass 34, count 0 2006.285.18:01:44.36#ibcon#about to write, iclass 34, count 0 2006.285.18:01:44.36#ibcon#wrote, iclass 34, count 0 2006.285.18:01:44.36#ibcon#about to read 3, iclass 34, count 0 2006.285.18:01:44.38#ibcon#read 3, iclass 34, count 0 2006.285.18:01:44.38#ibcon#about to read 4, iclass 34, count 0 2006.285.18:01:44.38#ibcon#read 4, iclass 34, count 0 2006.285.18:01:44.38#ibcon#about to read 5, iclass 34, count 0 2006.285.18:01:44.38#ibcon#read 5, iclass 34, count 0 2006.285.18:01:44.38#ibcon#about to read 6, iclass 34, count 0 2006.285.18:01:44.38#ibcon#read 6, iclass 34, count 0 2006.285.18:01:44.38#ibcon#end of sib2, iclass 34, count 0 2006.285.18:01:44.38#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:01:44.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:01:44.38#ibcon#[25=USB\r\n] 2006.285.18:01:44.38#ibcon#*before write, iclass 34, count 0 2006.285.18:01:44.38#ibcon#enter sib2, iclass 34, count 0 2006.285.18:01:44.38#ibcon#flushed, iclass 34, count 0 2006.285.18:01:44.38#ibcon#about to write, iclass 34, count 0 2006.285.18:01:44.38#ibcon#wrote, iclass 34, count 0 2006.285.18:01:44.38#ibcon#about to read 3, iclass 34, count 0 2006.285.18:01:44.41#ibcon#read 3, iclass 34, count 0 2006.285.18:01:44.41#ibcon#about to read 4, iclass 34, count 0 2006.285.18:01:44.41#ibcon#read 4, iclass 34, count 0 2006.285.18:01:44.41#ibcon#about to read 5, iclass 34, count 0 2006.285.18:01:44.41#ibcon#read 5, iclass 34, count 0 2006.285.18:01:44.41#ibcon#about to read 6, iclass 34, count 0 2006.285.18:01:44.41#ibcon#read 6, iclass 34, count 0 2006.285.18:01:44.41#ibcon#end of sib2, iclass 34, count 0 2006.285.18:01:44.41#ibcon#*after write, iclass 34, count 0 2006.285.18:01:44.41#ibcon#*before return 0, iclass 34, count 0 2006.285.18:01:44.41#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:01:44.41#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:01:44.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:01:44.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:01:44.41$vck44/valo=6,814.99 2006.285.18:01:44.41#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.18:01:44.41#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.18:01:44.41#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:44.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:01:44.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:01:44.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:01:44.41#ibcon#enter wrdev, iclass 36, count 0 2006.285.18:01:44.41#ibcon#first serial, iclass 36, count 0 2006.285.18:01:44.41#ibcon#enter sib2, iclass 36, count 0 2006.285.18:01:44.41#ibcon#flushed, iclass 36, count 0 2006.285.18:01:44.41#ibcon#about to write, iclass 36, count 0 2006.285.18:01:44.41#ibcon#wrote, iclass 36, count 0 2006.285.18:01:44.41#ibcon#about to read 3, iclass 36, count 0 2006.285.18:01:44.43#ibcon#read 3, iclass 36, count 0 2006.285.18:01:44.43#ibcon#about to read 4, iclass 36, count 0 2006.285.18:01:44.43#ibcon#read 4, iclass 36, count 0 2006.285.18:01:44.43#ibcon#about to read 5, iclass 36, count 0 2006.285.18:01:44.43#ibcon#read 5, iclass 36, count 0 2006.285.18:01:44.43#ibcon#about to read 6, iclass 36, count 0 2006.285.18:01:44.43#ibcon#read 6, iclass 36, count 0 2006.285.18:01:44.43#ibcon#end of sib2, iclass 36, count 0 2006.285.18:01:44.43#ibcon#*mode == 0, iclass 36, count 0 2006.285.18:01:44.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.18:01:44.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.18:01:44.43#ibcon#*before write, iclass 36, count 0 2006.285.18:01:44.43#ibcon#enter sib2, iclass 36, count 0 2006.285.18:01:44.43#ibcon#flushed, iclass 36, count 0 2006.285.18:01:44.43#ibcon#about to write, iclass 36, count 0 2006.285.18:01:44.43#ibcon#wrote, iclass 36, count 0 2006.285.18:01:44.43#ibcon#about to read 3, iclass 36, count 0 2006.285.18:01:44.47#ibcon#read 3, iclass 36, count 0 2006.285.18:01:44.47#ibcon#about to read 4, iclass 36, count 0 2006.285.18:01:44.47#ibcon#read 4, iclass 36, count 0 2006.285.18:01:44.47#ibcon#about to read 5, iclass 36, count 0 2006.285.18:01:44.47#ibcon#read 5, iclass 36, count 0 2006.285.18:01:44.47#ibcon#about to read 6, iclass 36, count 0 2006.285.18:01:44.47#ibcon#read 6, iclass 36, count 0 2006.285.18:01:44.47#ibcon#end of sib2, iclass 36, count 0 2006.285.18:01:44.47#ibcon#*after write, iclass 36, count 0 2006.285.18:01:44.47#ibcon#*before return 0, iclass 36, count 0 2006.285.18:01:44.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:01:44.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:01:44.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.18:01:44.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.18:01:44.47$vck44/va=6,4 2006.285.18:01:44.47#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.18:01:44.47#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.18:01:44.47#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:44.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:01:44.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:01:44.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:01:44.53#ibcon#enter wrdev, iclass 38, count 2 2006.285.18:01:44.53#ibcon#first serial, iclass 38, count 2 2006.285.18:01:44.53#ibcon#enter sib2, iclass 38, count 2 2006.285.18:01:44.53#ibcon#flushed, iclass 38, count 2 2006.285.18:01:44.53#ibcon#about to write, iclass 38, count 2 2006.285.18:01:44.53#ibcon#wrote, iclass 38, count 2 2006.285.18:01:44.53#ibcon#about to read 3, iclass 38, count 2 2006.285.18:01:44.55#ibcon#read 3, iclass 38, count 2 2006.285.18:01:44.55#ibcon#about to read 4, iclass 38, count 2 2006.285.18:01:44.55#ibcon#read 4, iclass 38, count 2 2006.285.18:01:44.55#ibcon#about to read 5, iclass 38, count 2 2006.285.18:01:44.55#ibcon#read 5, iclass 38, count 2 2006.285.18:01:44.55#ibcon#about to read 6, iclass 38, count 2 2006.285.18:01:44.55#ibcon#read 6, iclass 38, count 2 2006.285.18:01:44.55#ibcon#end of sib2, iclass 38, count 2 2006.285.18:01:44.55#ibcon#*mode == 0, iclass 38, count 2 2006.285.18:01:44.55#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.18:01:44.55#ibcon#[25=AT06-04\r\n] 2006.285.18:01:44.55#ibcon#*before write, iclass 38, count 2 2006.285.18:01:44.55#ibcon#enter sib2, iclass 38, count 2 2006.285.18:01:44.55#ibcon#flushed, iclass 38, count 2 2006.285.18:01:44.55#ibcon#about to write, iclass 38, count 2 2006.285.18:01:44.55#ibcon#wrote, iclass 38, count 2 2006.285.18:01:44.55#ibcon#about to read 3, iclass 38, count 2 2006.285.18:01:44.58#ibcon#read 3, iclass 38, count 2 2006.285.18:01:44.58#ibcon#about to read 4, iclass 38, count 2 2006.285.18:01:44.58#ibcon#read 4, iclass 38, count 2 2006.285.18:01:44.58#ibcon#about to read 5, iclass 38, count 2 2006.285.18:01:44.58#ibcon#read 5, iclass 38, count 2 2006.285.18:01:44.58#ibcon#about to read 6, iclass 38, count 2 2006.285.18:01:44.58#ibcon#read 6, iclass 38, count 2 2006.285.18:01:44.58#ibcon#end of sib2, iclass 38, count 2 2006.285.18:01:44.58#ibcon#*after write, iclass 38, count 2 2006.285.18:01:44.58#ibcon#*before return 0, iclass 38, count 2 2006.285.18:01:44.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:01:44.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:01:44.58#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.18:01:44.58#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:44.58#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:01:44.70#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:01:44.70#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:01:44.70#ibcon#enter wrdev, iclass 38, count 0 2006.285.18:01:44.70#ibcon#first serial, iclass 38, count 0 2006.285.18:01:44.70#ibcon#enter sib2, iclass 38, count 0 2006.285.18:01:44.70#ibcon#flushed, iclass 38, count 0 2006.285.18:01:44.70#ibcon#about to write, iclass 38, count 0 2006.285.18:01:44.70#ibcon#wrote, iclass 38, count 0 2006.285.18:01:44.70#ibcon#about to read 3, iclass 38, count 0 2006.285.18:01:44.72#ibcon#read 3, iclass 38, count 0 2006.285.18:01:44.72#ibcon#about to read 4, iclass 38, count 0 2006.285.18:01:44.72#ibcon#read 4, iclass 38, count 0 2006.285.18:01:44.72#ibcon#about to read 5, iclass 38, count 0 2006.285.18:01:44.72#ibcon#read 5, iclass 38, count 0 2006.285.18:01:44.72#ibcon#about to read 6, iclass 38, count 0 2006.285.18:01:44.72#ibcon#read 6, iclass 38, count 0 2006.285.18:01:44.72#ibcon#end of sib2, iclass 38, count 0 2006.285.18:01:44.72#ibcon#*mode == 0, iclass 38, count 0 2006.285.18:01:44.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.18:01:44.72#ibcon#[25=USB\r\n] 2006.285.18:01:44.72#ibcon#*before write, iclass 38, count 0 2006.285.18:01:44.72#ibcon#enter sib2, iclass 38, count 0 2006.285.18:01:44.72#ibcon#flushed, iclass 38, count 0 2006.285.18:01:44.72#ibcon#about to write, iclass 38, count 0 2006.285.18:01:44.72#ibcon#wrote, iclass 38, count 0 2006.285.18:01:44.72#ibcon#about to read 3, iclass 38, count 0 2006.285.18:01:44.75#ibcon#read 3, iclass 38, count 0 2006.285.18:01:44.75#ibcon#about to read 4, iclass 38, count 0 2006.285.18:01:44.75#ibcon#read 4, iclass 38, count 0 2006.285.18:01:44.75#ibcon#about to read 5, iclass 38, count 0 2006.285.18:01:44.75#ibcon#read 5, iclass 38, count 0 2006.285.18:01:44.75#ibcon#about to read 6, iclass 38, count 0 2006.285.18:01:44.75#ibcon#read 6, iclass 38, count 0 2006.285.18:01:44.75#ibcon#end of sib2, iclass 38, count 0 2006.285.18:01:44.75#ibcon#*after write, iclass 38, count 0 2006.285.18:01:44.75#ibcon#*before return 0, iclass 38, count 0 2006.285.18:01:44.75#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:01:44.75#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:01:44.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.18:01:44.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.18:01:44.75$vck44/valo=7,864.99 2006.285.18:01:44.75#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.18:01:44.75#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.18:01:44.75#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:44.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:01:44.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:01:44.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:01:44.75#ibcon#enter wrdev, iclass 40, count 0 2006.285.18:01:44.75#ibcon#first serial, iclass 40, count 0 2006.285.18:01:44.75#ibcon#enter sib2, iclass 40, count 0 2006.285.18:01:44.75#ibcon#flushed, iclass 40, count 0 2006.285.18:01:44.75#ibcon#about to write, iclass 40, count 0 2006.285.18:01:44.75#ibcon#wrote, iclass 40, count 0 2006.285.18:01:44.75#ibcon#about to read 3, iclass 40, count 0 2006.285.18:01:44.77#ibcon#read 3, iclass 40, count 0 2006.285.18:01:44.84#ibcon#about to read 4, iclass 40, count 0 2006.285.18:01:44.84#ibcon#read 4, iclass 40, count 0 2006.285.18:01:44.84#ibcon#about to read 5, iclass 40, count 0 2006.285.18:01:44.84#ibcon#read 5, iclass 40, count 0 2006.285.18:01:44.84#ibcon#about to read 6, iclass 40, count 0 2006.285.18:01:44.84#ibcon#read 6, iclass 40, count 0 2006.285.18:01:44.84#ibcon#end of sib2, iclass 40, count 0 2006.285.18:01:44.84#ibcon#*mode == 0, iclass 40, count 0 2006.285.18:01:44.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.18:01:44.84#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.18:01:44.84#ibcon#*before write, iclass 40, count 0 2006.285.18:01:44.84#ibcon#enter sib2, iclass 40, count 0 2006.285.18:01:44.84#ibcon#flushed, iclass 40, count 0 2006.285.18:01:44.84#ibcon#about to write, iclass 40, count 0 2006.285.18:01:44.84#ibcon#wrote, iclass 40, count 0 2006.285.18:01:44.84#ibcon#about to read 3, iclass 40, count 0 2006.285.18:01:44.88#ibcon#read 3, iclass 40, count 0 2006.285.18:01:44.88#ibcon#about to read 4, iclass 40, count 0 2006.285.18:01:44.88#ibcon#read 4, iclass 40, count 0 2006.285.18:01:44.88#ibcon#about to read 5, iclass 40, count 0 2006.285.18:01:44.88#ibcon#read 5, iclass 40, count 0 2006.285.18:01:44.88#ibcon#about to read 6, iclass 40, count 0 2006.285.18:01:44.88#ibcon#read 6, iclass 40, count 0 2006.285.18:01:44.88#ibcon#end of sib2, iclass 40, count 0 2006.285.18:01:44.88#ibcon#*after write, iclass 40, count 0 2006.285.18:01:44.88#ibcon#*before return 0, iclass 40, count 0 2006.285.18:01:44.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:01:44.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:01:44.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.18:01:44.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.18:01:44.88$vck44/va=7,4 2006.285.18:01:44.88#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.18:01:44.88#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.18:01:44.88#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:44.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:01:44.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:01:44.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:01:44.88#ibcon#enter wrdev, iclass 4, count 2 2006.285.18:01:44.88#ibcon#first serial, iclass 4, count 2 2006.285.18:01:44.88#ibcon#enter sib2, iclass 4, count 2 2006.285.18:01:44.88#ibcon#flushed, iclass 4, count 2 2006.285.18:01:44.88#ibcon#about to write, iclass 4, count 2 2006.285.18:01:44.88#ibcon#wrote, iclass 4, count 2 2006.285.18:01:44.88#ibcon#about to read 3, iclass 4, count 2 2006.285.18:01:44.90#ibcon#read 3, iclass 4, count 2 2006.285.18:01:44.90#ibcon#about to read 4, iclass 4, count 2 2006.285.18:01:44.90#ibcon#read 4, iclass 4, count 2 2006.285.18:01:44.90#ibcon#about to read 5, iclass 4, count 2 2006.285.18:01:44.90#ibcon#read 5, iclass 4, count 2 2006.285.18:01:44.90#ibcon#about to read 6, iclass 4, count 2 2006.285.18:01:44.90#ibcon#read 6, iclass 4, count 2 2006.285.18:01:44.90#ibcon#end of sib2, iclass 4, count 2 2006.285.18:01:44.90#ibcon#*mode == 0, iclass 4, count 2 2006.285.18:01:44.90#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.18:01:44.90#ibcon#[25=AT07-04\r\n] 2006.285.18:01:44.90#ibcon#*before write, iclass 4, count 2 2006.285.18:01:44.90#ibcon#enter sib2, iclass 4, count 2 2006.285.18:01:44.90#ibcon#flushed, iclass 4, count 2 2006.285.18:01:44.90#ibcon#about to write, iclass 4, count 2 2006.285.18:01:44.90#ibcon#wrote, iclass 4, count 2 2006.285.18:01:44.90#ibcon#about to read 3, iclass 4, count 2 2006.285.18:01:44.93#ibcon#read 3, iclass 4, count 2 2006.285.18:01:44.93#ibcon#about to read 4, iclass 4, count 2 2006.285.18:01:44.93#ibcon#read 4, iclass 4, count 2 2006.285.18:01:44.93#ibcon#about to read 5, iclass 4, count 2 2006.285.18:01:44.93#ibcon#read 5, iclass 4, count 2 2006.285.18:01:44.93#ibcon#about to read 6, iclass 4, count 2 2006.285.18:01:44.93#ibcon#read 6, iclass 4, count 2 2006.285.18:01:44.93#ibcon#end of sib2, iclass 4, count 2 2006.285.18:01:44.93#ibcon#*after write, iclass 4, count 2 2006.285.18:01:44.93#ibcon#*before return 0, iclass 4, count 2 2006.285.18:01:44.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:01:44.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:01:44.93#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.18:01:44.93#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:44.93#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:01:45.05#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:01:45.05#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:01:45.05#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:01:45.05#ibcon#first serial, iclass 4, count 0 2006.285.18:01:45.05#ibcon#enter sib2, iclass 4, count 0 2006.285.18:01:45.05#ibcon#flushed, iclass 4, count 0 2006.285.18:01:45.05#ibcon#about to write, iclass 4, count 0 2006.285.18:01:45.05#ibcon#wrote, iclass 4, count 0 2006.285.18:01:45.05#ibcon#about to read 3, iclass 4, count 0 2006.285.18:01:45.07#ibcon#read 3, iclass 4, count 0 2006.285.18:01:45.07#ibcon#about to read 4, iclass 4, count 0 2006.285.18:01:45.07#ibcon#read 4, iclass 4, count 0 2006.285.18:01:45.07#ibcon#about to read 5, iclass 4, count 0 2006.285.18:01:45.07#ibcon#read 5, iclass 4, count 0 2006.285.18:01:45.07#ibcon#about to read 6, iclass 4, count 0 2006.285.18:01:45.07#ibcon#read 6, iclass 4, count 0 2006.285.18:01:45.07#ibcon#end of sib2, iclass 4, count 0 2006.285.18:01:45.07#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:01:45.07#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:01:45.07#ibcon#[25=USB\r\n] 2006.285.18:01:45.07#ibcon#*before write, iclass 4, count 0 2006.285.18:01:45.07#ibcon#enter sib2, iclass 4, count 0 2006.285.18:01:45.07#ibcon#flushed, iclass 4, count 0 2006.285.18:01:45.07#ibcon#about to write, iclass 4, count 0 2006.285.18:01:45.07#ibcon#wrote, iclass 4, count 0 2006.285.18:01:45.07#ibcon#about to read 3, iclass 4, count 0 2006.285.18:01:45.10#ibcon#read 3, iclass 4, count 0 2006.285.18:01:45.10#ibcon#about to read 4, iclass 4, count 0 2006.285.18:01:45.10#ibcon#read 4, iclass 4, count 0 2006.285.18:01:45.10#ibcon#about to read 5, iclass 4, count 0 2006.285.18:01:45.10#ibcon#read 5, iclass 4, count 0 2006.285.18:01:45.10#ibcon#about to read 6, iclass 4, count 0 2006.285.18:01:45.10#ibcon#read 6, iclass 4, count 0 2006.285.18:01:45.10#ibcon#end of sib2, iclass 4, count 0 2006.285.18:01:45.10#ibcon#*after write, iclass 4, count 0 2006.285.18:01:45.10#ibcon#*before return 0, iclass 4, count 0 2006.285.18:01:45.10#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:01:45.10#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:01:45.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:01:45.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:01:45.10$vck44/valo=8,884.99 2006.285.18:01:45.10#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.18:01:45.10#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.18:01:45.10#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:45.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:01:45.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:01:45.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:01:45.10#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:01:45.10#ibcon#first serial, iclass 6, count 0 2006.285.18:01:45.10#ibcon#enter sib2, iclass 6, count 0 2006.285.18:01:45.10#ibcon#flushed, iclass 6, count 0 2006.285.18:01:45.10#ibcon#about to write, iclass 6, count 0 2006.285.18:01:45.10#ibcon#wrote, iclass 6, count 0 2006.285.18:01:45.10#ibcon#about to read 3, iclass 6, count 0 2006.285.18:01:45.12#ibcon#read 3, iclass 6, count 0 2006.285.18:01:45.12#ibcon#about to read 4, iclass 6, count 0 2006.285.18:01:45.12#ibcon#read 4, iclass 6, count 0 2006.285.18:01:45.12#ibcon#about to read 5, iclass 6, count 0 2006.285.18:01:45.12#ibcon#read 5, iclass 6, count 0 2006.285.18:01:45.12#ibcon#about to read 6, iclass 6, count 0 2006.285.18:01:45.12#ibcon#read 6, iclass 6, count 0 2006.285.18:01:45.12#ibcon#end of sib2, iclass 6, count 0 2006.285.18:01:45.12#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:01:45.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:01:45.12#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.18:01:45.12#ibcon#*before write, iclass 6, count 0 2006.285.18:01:45.12#ibcon#enter sib2, iclass 6, count 0 2006.285.18:01:45.12#ibcon#flushed, iclass 6, count 0 2006.285.18:01:45.12#ibcon#about to write, iclass 6, count 0 2006.285.18:01:45.12#ibcon#wrote, iclass 6, count 0 2006.285.18:01:45.12#ibcon#about to read 3, iclass 6, count 0 2006.285.18:01:45.16#ibcon#read 3, iclass 6, count 0 2006.285.18:01:45.16#ibcon#about to read 4, iclass 6, count 0 2006.285.18:01:45.16#ibcon#read 4, iclass 6, count 0 2006.285.18:01:45.16#ibcon#about to read 5, iclass 6, count 0 2006.285.18:01:45.16#ibcon#read 5, iclass 6, count 0 2006.285.18:01:45.16#ibcon#about to read 6, iclass 6, count 0 2006.285.18:01:45.16#ibcon#read 6, iclass 6, count 0 2006.285.18:01:45.16#ibcon#end of sib2, iclass 6, count 0 2006.285.18:01:45.16#ibcon#*after write, iclass 6, count 0 2006.285.18:01:45.16#ibcon#*before return 0, iclass 6, count 0 2006.285.18:01:45.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:01:45.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:01:45.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:01:45.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:01:45.16$vck44/va=8,3 2006.285.18:01:45.16#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.18:01:45.16#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.18:01:45.16#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:45.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:01:45.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:01:45.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:01:45.22#ibcon#enter wrdev, iclass 10, count 2 2006.285.18:01:45.22#ibcon#first serial, iclass 10, count 2 2006.285.18:01:45.22#ibcon#enter sib2, iclass 10, count 2 2006.285.18:01:45.22#ibcon#flushed, iclass 10, count 2 2006.285.18:01:45.22#ibcon#about to write, iclass 10, count 2 2006.285.18:01:45.22#ibcon#wrote, iclass 10, count 2 2006.285.18:01:45.22#ibcon#about to read 3, iclass 10, count 2 2006.285.18:01:45.24#ibcon#read 3, iclass 10, count 2 2006.285.18:01:45.24#ibcon#about to read 4, iclass 10, count 2 2006.285.18:01:45.24#ibcon#read 4, iclass 10, count 2 2006.285.18:01:45.24#ibcon#about to read 5, iclass 10, count 2 2006.285.18:01:45.24#ibcon#read 5, iclass 10, count 2 2006.285.18:01:45.24#ibcon#about to read 6, iclass 10, count 2 2006.285.18:01:45.24#ibcon#read 6, iclass 10, count 2 2006.285.18:01:45.24#ibcon#end of sib2, iclass 10, count 2 2006.285.18:01:45.24#ibcon#*mode == 0, iclass 10, count 2 2006.285.18:01:45.24#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.18:01:45.24#ibcon#[25=AT08-03\r\n] 2006.285.18:01:45.24#ibcon#*before write, iclass 10, count 2 2006.285.18:01:45.24#ibcon#enter sib2, iclass 10, count 2 2006.285.18:01:45.24#ibcon#flushed, iclass 10, count 2 2006.285.18:01:45.24#ibcon#about to write, iclass 10, count 2 2006.285.18:01:45.24#ibcon#wrote, iclass 10, count 2 2006.285.18:01:45.24#ibcon#about to read 3, iclass 10, count 2 2006.285.18:01:45.27#ibcon#read 3, iclass 10, count 2 2006.285.18:01:45.27#ibcon#about to read 4, iclass 10, count 2 2006.285.18:01:45.27#ibcon#read 4, iclass 10, count 2 2006.285.18:01:45.27#ibcon#about to read 5, iclass 10, count 2 2006.285.18:01:45.27#ibcon#read 5, iclass 10, count 2 2006.285.18:01:45.27#ibcon#about to read 6, iclass 10, count 2 2006.285.18:01:45.27#ibcon#read 6, iclass 10, count 2 2006.285.18:01:45.27#ibcon#end of sib2, iclass 10, count 2 2006.285.18:01:45.27#ibcon#*after write, iclass 10, count 2 2006.285.18:01:45.27#ibcon#*before return 0, iclass 10, count 2 2006.285.18:01:45.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:01:45.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:01:45.27#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.18:01:45.27#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:45.27#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:01:45.39#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:01:45.39#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:01:45.39#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:01:45.39#ibcon#first serial, iclass 10, count 0 2006.285.18:01:45.39#ibcon#enter sib2, iclass 10, count 0 2006.285.18:01:45.39#ibcon#flushed, iclass 10, count 0 2006.285.18:01:45.39#ibcon#about to write, iclass 10, count 0 2006.285.18:01:45.39#ibcon#wrote, iclass 10, count 0 2006.285.18:01:45.39#ibcon#about to read 3, iclass 10, count 0 2006.285.18:01:45.41#ibcon#read 3, iclass 10, count 0 2006.285.18:01:45.41#ibcon#about to read 4, iclass 10, count 0 2006.285.18:01:45.41#ibcon#read 4, iclass 10, count 0 2006.285.18:01:45.41#ibcon#about to read 5, iclass 10, count 0 2006.285.18:01:45.41#ibcon#read 5, iclass 10, count 0 2006.285.18:01:45.41#ibcon#about to read 6, iclass 10, count 0 2006.285.18:01:45.41#ibcon#read 6, iclass 10, count 0 2006.285.18:01:45.41#ibcon#end of sib2, iclass 10, count 0 2006.285.18:01:45.41#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:01:45.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:01:45.41#ibcon#[25=USB\r\n] 2006.285.18:01:45.41#ibcon#*before write, iclass 10, count 0 2006.285.18:01:45.41#ibcon#enter sib2, iclass 10, count 0 2006.285.18:01:45.41#ibcon#flushed, iclass 10, count 0 2006.285.18:01:45.41#ibcon#about to write, iclass 10, count 0 2006.285.18:01:45.41#ibcon#wrote, iclass 10, count 0 2006.285.18:01:45.41#ibcon#about to read 3, iclass 10, count 0 2006.285.18:01:45.44#ibcon#read 3, iclass 10, count 0 2006.285.18:01:45.44#ibcon#about to read 4, iclass 10, count 0 2006.285.18:01:45.44#ibcon#read 4, iclass 10, count 0 2006.285.18:01:45.44#ibcon#about to read 5, iclass 10, count 0 2006.285.18:01:45.44#ibcon#read 5, iclass 10, count 0 2006.285.18:01:45.44#ibcon#about to read 6, iclass 10, count 0 2006.285.18:01:45.44#ibcon#read 6, iclass 10, count 0 2006.285.18:01:45.44#ibcon#end of sib2, iclass 10, count 0 2006.285.18:01:45.44#ibcon#*after write, iclass 10, count 0 2006.285.18:01:45.44#ibcon#*before return 0, iclass 10, count 0 2006.285.18:01:45.44#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:01:45.44#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:01:45.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:01:45.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:01:45.44$vck44/vblo=1,629.99 2006.285.18:01:45.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.18:01:45.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.18:01:45.44#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:45.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:01:45.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:01:45.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:01:45.44#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:01:45.44#ibcon#first serial, iclass 12, count 0 2006.285.18:01:45.44#ibcon#enter sib2, iclass 12, count 0 2006.285.18:01:45.44#ibcon#flushed, iclass 12, count 0 2006.285.18:01:45.44#ibcon#about to write, iclass 12, count 0 2006.285.18:01:45.44#ibcon#wrote, iclass 12, count 0 2006.285.18:01:45.44#ibcon#about to read 3, iclass 12, count 0 2006.285.18:01:45.46#ibcon#read 3, iclass 12, count 0 2006.285.18:01:45.46#ibcon#about to read 4, iclass 12, count 0 2006.285.18:01:45.46#ibcon#read 4, iclass 12, count 0 2006.285.18:01:45.46#ibcon#about to read 5, iclass 12, count 0 2006.285.18:01:45.46#ibcon#read 5, iclass 12, count 0 2006.285.18:01:45.46#ibcon#about to read 6, iclass 12, count 0 2006.285.18:01:45.46#ibcon#read 6, iclass 12, count 0 2006.285.18:01:45.46#ibcon#end of sib2, iclass 12, count 0 2006.285.18:01:45.46#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:01:45.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:01:45.46#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.18:01:45.46#ibcon#*before write, iclass 12, count 0 2006.285.18:01:45.46#ibcon#enter sib2, iclass 12, count 0 2006.285.18:01:45.46#ibcon#flushed, iclass 12, count 0 2006.285.18:01:45.46#ibcon#about to write, iclass 12, count 0 2006.285.18:01:45.46#ibcon#wrote, iclass 12, count 0 2006.285.18:01:45.46#ibcon#about to read 3, iclass 12, count 0 2006.285.18:01:45.50#ibcon#read 3, iclass 12, count 0 2006.285.18:01:45.50#ibcon#about to read 4, iclass 12, count 0 2006.285.18:01:45.50#ibcon#read 4, iclass 12, count 0 2006.285.18:01:45.50#ibcon#about to read 5, iclass 12, count 0 2006.285.18:01:45.50#ibcon#read 5, iclass 12, count 0 2006.285.18:01:45.50#ibcon#about to read 6, iclass 12, count 0 2006.285.18:01:45.50#ibcon#read 6, iclass 12, count 0 2006.285.18:01:45.50#ibcon#end of sib2, iclass 12, count 0 2006.285.18:01:45.50#ibcon#*after write, iclass 12, count 0 2006.285.18:01:45.50#ibcon#*before return 0, iclass 12, count 0 2006.285.18:01:45.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:01:45.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:01:45.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:01:45.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:01:45.50$vck44/vb=1,4 2006.285.18:01:45.50#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.18:01:45.50#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.18:01:45.50#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:45.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:01:45.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:01:45.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:01:45.50#ibcon#enter wrdev, iclass 14, count 2 2006.285.18:01:45.50#ibcon#first serial, iclass 14, count 2 2006.285.18:01:45.50#ibcon#enter sib2, iclass 14, count 2 2006.285.18:01:45.50#ibcon#flushed, iclass 14, count 2 2006.285.18:01:45.50#ibcon#about to write, iclass 14, count 2 2006.285.18:01:45.50#ibcon#wrote, iclass 14, count 2 2006.285.18:01:45.50#ibcon#about to read 3, iclass 14, count 2 2006.285.18:01:45.52#ibcon#read 3, iclass 14, count 2 2006.285.18:01:45.52#ibcon#about to read 4, iclass 14, count 2 2006.285.18:01:45.52#ibcon#read 4, iclass 14, count 2 2006.285.18:01:45.52#ibcon#about to read 5, iclass 14, count 2 2006.285.18:01:45.52#ibcon#read 5, iclass 14, count 2 2006.285.18:01:45.52#ibcon#about to read 6, iclass 14, count 2 2006.285.18:01:45.52#ibcon#read 6, iclass 14, count 2 2006.285.18:01:45.52#ibcon#end of sib2, iclass 14, count 2 2006.285.18:01:45.52#ibcon#*mode == 0, iclass 14, count 2 2006.285.18:01:45.52#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.18:01:45.52#ibcon#[27=AT01-04\r\n] 2006.285.18:01:45.52#ibcon#*before write, iclass 14, count 2 2006.285.18:01:45.52#ibcon#enter sib2, iclass 14, count 2 2006.285.18:01:45.52#ibcon#flushed, iclass 14, count 2 2006.285.18:01:45.52#ibcon#about to write, iclass 14, count 2 2006.285.18:01:45.52#ibcon#wrote, iclass 14, count 2 2006.285.18:01:45.52#ibcon#about to read 3, iclass 14, count 2 2006.285.18:01:45.55#ibcon#read 3, iclass 14, count 2 2006.285.18:01:45.55#ibcon#about to read 4, iclass 14, count 2 2006.285.18:01:45.55#ibcon#read 4, iclass 14, count 2 2006.285.18:01:45.55#ibcon#about to read 5, iclass 14, count 2 2006.285.18:01:45.55#ibcon#read 5, iclass 14, count 2 2006.285.18:01:45.55#ibcon#about to read 6, iclass 14, count 2 2006.285.18:01:45.55#ibcon#read 6, iclass 14, count 2 2006.285.18:01:45.55#ibcon#end of sib2, iclass 14, count 2 2006.285.18:01:45.55#ibcon#*after write, iclass 14, count 2 2006.285.18:01:45.55#ibcon#*before return 0, iclass 14, count 2 2006.285.18:01:45.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:01:45.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:01:45.55#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.18:01:45.55#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:45.55#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:01:45.67#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:01:45.67#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:01:45.67#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:01:45.67#ibcon#first serial, iclass 14, count 0 2006.285.18:01:45.67#ibcon#enter sib2, iclass 14, count 0 2006.285.18:01:45.67#ibcon#flushed, iclass 14, count 0 2006.285.18:01:45.67#ibcon#about to write, iclass 14, count 0 2006.285.18:01:45.67#ibcon#wrote, iclass 14, count 0 2006.285.18:01:45.67#ibcon#about to read 3, iclass 14, count 0 2006.285.18:01:45.69#ibcon#read 3, iclass 14, count 0 2006.285.18:01:45.69#ibcon#about to read 4, iclass 14, count 0 2006.285.18:01:45.69#ibcon#read 4, iclass 14, count 0 2006.285.18:01:45.69#ibcon#about to read 5, iclass 14, count 0 2006.285.18:01:45.69#ibcon#read 5, iclass 14, count 0 2006.285.18:01:45.69#ibcon#about to read 6, iclass 14, count 0 2006.285.18:01:45.69#ibcon#read 6, iclass 14, count 0 2006.285.18:01:45.69#ibcon#end of sib2, iclass 14, count 0 2006.285.18:01:45.69#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:01:45.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:01:45.69#ibcon#[27=USB\r\n] 2006.285.18:01:45.69#ibcon#*before write, iclass 14, count 0 2006.285.18:01:45.69#ibcon#enter sib2, iclass 14, count 0 2006.285.18:01:45.69#ibcon#flushed, iclass 14, count 0 2006.285.18:01:45.69#ibcon#about to write, iclass 14, count 0 2006.285.18:01:45.69#ibcon#wrote, iclass 14, count 0 2006.285.18:01:45.69#ibcon#about to read 3, iclass 14, count 0 2006.285.18:01:45.72#ibcon#read 3, iclass 14, count 0 2006.285.18:01:45.72#ibcon#about to read 4, iclass 14, count 0 2006.285.18:01:45.72#ibcon#read 4, iclass 14, count 0 2006.285.18:01:45.72#ibcon#about to read 5, iclass 14, count 0 2006.285.18:01:45.72#ibcon#read 5, iclass 14, count 0 2006.285.18:01:45.72#ibcon#about to read 6, iclass 14, count 0 2006.285.18:01:45.72#ibcon#read 6, iclass 14, count 0 2006.285.18:01:45.72#ibcon#end of sib2, iclass 14, count 0 2006.285.18:01:45.72#ibcon#*after write, iclass 14, count 0 2006.285.18:01:45.72#ibcon#*before return 0, iclass 14, count 0 2006.285.18:01:45.72#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:01:45.72#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:01:45.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:01:45.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:01:45.72$vck44/vblo=2,634.99 2006.285.18:01:45.72#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.18:01:45.72#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.18:01:45.72#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:45.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:01:45.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:01:45.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:01:45.72#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:01:45.72#ibcon#first serial, iclass 16, count 0 2006.285.18:01:45.72#ibcon#enter sib2, iclass 16, count 0 2006.285.18:01:45.72#ibcon#flushed, iclass 16, count 0 2006.285.18:01:45.72#ibcon#about to write, iclass 16, count 0 2006.285.18:01:45.72#ibcon#wrote, iclass 16, count 0 2006.285.18:01:45.72#ibcon#about to read 3, iclass 16, count 0 2006.285.18:01:45.74#ibcon#read 3, iclass 16, count 0 2006.285.18:01:45.91#ibcon#about to read 4, iclass 16, count 0 2006.285.18:01:45.91#ibcon#read 4, iclass 16, count 0 2006.285.18:01:45.91#ibcon#about to read 5, iclass 16, count 0 2006.285.18:01:45.91#ibcon#read 5, iclass 16, count 0 2006.285.18:01:45.91#ibcon#about to read 6, iclass 16, count 0 2006.285.18:01:45.91#ibcon#read 6, iclass 16, count 0 2006.285.18:01:45.91#ibcon#end of sib2, iclass 16, count 0 2006.285.18:01:45.91#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:01:45.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:01:45.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.18:01:45.91#ibcon#*before write, iclass 16, count 0 2006.285.18:01:45.91#ibcon#enter sib2, iclass 16, count 0 2006.285.18:01:45.91#ibcon#flushed, iclass 16, count 0 2006.285.18:01:45.91#ibcon#about to write, iclass 16, count 0 2006.285.18:01:45.91#ibcon#wrote, iclass 16, count 0 2006.285.18:01:45.91#ibcon#about to read 3, iclass 16, count 0 2006.285.18:01:45.95#ibcon#read 3, iclass 16, count 0 2006.285.18:01:45.95#ibcon#about to read 4, iclass 16, count 0 2006.285.18:01:45.95#ibcon#read 4, iclass 16, count 0 2006.285.18:01:45.95#ibcon#about to read 5, iclass 16, count 0 2006.285.18:01:45.95#ibcon#read 5, iclass 16, count 0 2006.285.18:01:45.95#ibcon#about to read 6, iclass 16, count 0 2006.285.18:01:45.95#ibcon#read 6, iclass 16, count 0 2006.285.18:01:45.95#ibcon#end of sib2, iclass 16, count 0 2006.285.18:01:45.95#ibcon#*after write, iclass 16, count 0 2006.285.18:01:45.95#ibcon#*before return 0, iclass 16, count 0 2006.285.18:01:45.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:01:45.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:01:45.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:01:45.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:01:45.95$vck44/vb=2,5 2006.285.18:01:45.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.18:01:45.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.18:01:45.95#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:45.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:01:45.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:01:45.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:01:45.95#ibcon#enter wrdev, iclass 18, count 2 2006.285.18:01:45.95#ibcon#first serial, iclass 18, count 2 2006.285.18:01:45.95#ibcon#enter sib2, iclass 18, count 2 2006.285.18:01:45.95#ibcon#flushed, iclass 18, count 2 2006.285.18:01:45.95#ibcon#about to write, iclass 18, count 2 2006.285.18:01:45.95#ibcon#wrote, iclass 18, count 2 2006.285.18:01:45.95#ibcon#about to read 3, iclass 18, count 2 2006.285.18:01:45.97#ibcon#read 3, iclass 18, count 2 2006.285.18:01:45.97#ibcon#about to read 4, iclass 18, count 2 2006.285.18:01:45.97#ibcon#read 4, iclass 18, count 2 2006.285.18:01:45.97#ibcon#about to read 5, iclass 18, count 2 2006.285.18:01:45.97#ibcon#read 5, iclass 18, count 2 2006.285.18:01:45.97#ibcon#about to read 6, iclass 18, count 2 2006.285.18:01:45.97#ibcon#read 6, iclass 18, count 2 2006.285.18:01:45.97#ibcon#end of sib2, iclass 18, count 2 2006.285.18:01:45.97#ibcon#*mode == 0, iclass 18, count 2 2006.285.18:01:45.97#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.18:01:45.97#ibcon#[27=AT02-05\r\n] 2006.285.18:01:45.97#ibcon#*before write, iclass 18, count 2 2006.285.18:01:45.97#ibcon#enter sib2, iclass 18, count 2 2006.285.18:01:45.97#ibcon#flushed, iclass 18, count 2 2006.285.18:01:45.97#ibcon#about to write, iclass 18, count 2 2006.285.18:01:45.97#ibcon#wrote, iclass 18, count 2 2006.285.18:01:45.97#ibcon#about to read 3, iclass 18, count 2 2006.285.18:01:46.00#ibcon#read 3, iclass 18, count 2 2006.285.18:01:46.00#ibcon#about to read 4, iclass 18, count 2 2006.285.18:01:46.00#ibcon#read 4, iclass 18, count 2 2006.285.18:01:46.00#ibcon#about to read 5, iclass 18, count 2 2006.285.18:01:46.00#ibcon#read 5, iclass 18, count 2 2006.285.18:01:46.00#ibcon#about to read 6, iclass 18, count 2 2006.285.18:01:46.00#ibcon#read 6, iclass 18, count 2 2006.285.18:01:46.00#ibcon#end of sib2, iclass 18, count 2 2006.285.18:01:46.00#ibcon#*after write, iclass 18, count 2 2006.285.18:01:46.00#ibcon#*before return 0, iclass 18, count 2 2006.285.18:01:46.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:01:46.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:01:46.00#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.18:01:46.00#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:46.00#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:01:46.12#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:01:46.12#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:01:46.12#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:01:46.12#ibcon#first serial, iclass 18, count 0 2006.285.18:01:46.12#ibcon#enter sib2, iclass 18, count 0 2006.285.18:01:46.12#ibcon#flushed, iclass 18, count 0 2006.285.18:01:46.12#ibcon#about to write, iclass 18, count 0 2006.285.18:01:46.12#ibcon#wrote, iclass 18, count 0 2006.285.18:01:46.12#ibcon#about to read 3, iclass 18, count 0 2006.285.18:01:46.14#ibcon#read 3, iclass 18, count 0 2006.285.18:01:46.14#ibcon#about to read 4, iclass 18, count 0 2006.285.18:01:46.14#ibcon#read 4, iclass 18, count 0 2006.285.18:01:46.14#ibcon#about to read 5, iclass 18, count 0 2006.285.18:01:46.14#ibcon#read 5, iclass 18, count 0 2006.285.18:01:46.14#ibcon#about to read 6, iclass 18, count 0 2006.285.18:01:46.14#ibcon#read 6, iclass 18, count 0 2006.285.18:01:46.14#ibcon#end of sib2, iclass 18, count 0 2006.285.18:01:46.14#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:01:46.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:01:46.14#ibcon#[27=USB\r\n] 2006.285.18:01:46.14#ibcon#*before write, iclass 18, count 0 2006.285.18:01:46.14#ibcon#enter sib2, iclass 18, count 0 2006.285.18:01:46.14#ibcon#flushed, iclass 18, count 0 2006.285.18:01:46.14#ibcon#about to write, iclass 18, count 0 2006.285.18:01:46.14#ibcon#wrote, iclass 18, count 0 2006.285.18:01:46.14#ibcon#about to read 3, iclass 18, count 0 2006.285.18:01:46.17#ibcon#read 3, iclass 18, count 0 2006.285.18:01:46.17#ibcon#about to read 4, iclass 18, count 0 2006.285.18:01:46.17#ibcon#read 4, iclass 18, count 0 2006.285.18:01:46.17#ibcon#about to read 5, iclass 18, count 0 2006.285.18:01:46.17#ibcon#read 5, iclass 18, count 0 2006.285.18:01:46.17#ibcon#about to read 6, iclass 18, count 0 2006.285.18:01:46.17#ibcon#read 6, iclass 18, count 0 2006.285.18:01:46.17#ibcon#end of sib2, iclass 18, count 0 2006.285.18:01:46.17#ibcon#*after write, iclass 18, count 0 2006.285.18:01:46.17#ibcon#*before return 0, iclass 18, count 0 2006.285.18:01:46.17#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:01:46.17#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:01:46.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:01:46.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:01:46.17$vck44/vblo=3,649.99 2006.285.18:01:46.17#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.18:01:46.17#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.18:01:46.17#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:46.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:01:46.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:01:46.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:01:46.17#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:01:46.17#ibcon#first serial, iclass 20, count 0 2006.285.18:01:46.17#ibcon#enter sib2, iclass 20, count 0 2006.285.18:01:46.17#ibcon#flushed, iclass 20, count 0 2006.285.18:01:46.17#ibcon#about to write, iclass 20, count 0 2006.285.18:01:46.17#ibcon#wrote, iclass 20, count 0 2006.285.18:01:46.17#ibcon#about to read 3, iclass 20, count 0 2006.285.18:01:46.19#ibcon#read 3, iclass 20, count 0 2006.285.18:01:46.19#ibcon#about to read 4, iclass 20, count 0 2006.285.18:01:46.19#ibcon#read 4, iclass 20, count 0 2006.285.18:01:46.19#ibcon#about to read 5, iclass 20, count 0 2006.285.18:01:46.19#ibcon#read 5, iclass 20, count 0 2006.285.18:01:46.19#ibcon#about to read 6, iclass 20, count 0 2006.285.18:01:46.19#ibcon#read 6, iclass 20, count 0 2006.285.18:01:46.19#ibcon#end of sib2, iclass 20, count 0 2006.285.18:01:46.19#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:01:46.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:01:46.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.18:01:46.19#ibcon#*before write, iclass 20, count 0 2006.285.18:01:46.19#ibcon#enter sib2, iclass 20, count 0 2006.285.18:01:46.19#ibcon#flushed, iclass 20, count 0 2006.285.18:01:46.19#ibcon#about to write, iclass 20, count 0 2006.285.18:01:46.19#ibcon#wrote, iclass 20, count 0 2006.285.18:01:46.19#ibcon#about to read 3, iclass 20, count 0 2006.285.18:01:46.23#ibcon#read 3, iclass 20, count 0 2006.285.18:01:46.23#ibcon#about to read 4, iclass 20, count 0 2006.285.18:01:46.23#ibcon#read 4, iclass 20, count 0 2006.285.18:01:46.23#ibcon#about to read 5, iclass 20, count 0 2006.285.18:01:46.23#ibcon#read 5, iclass 20, count 0 2006.285.18:01:46.23#ibcon#about to read 6, iclass 20, count 0 2006.285.18:01:46.23#ibcon#read 6, iclass 20, count 0 2006.285.18:01:46.23#ibcon#end of sib2, iclass 20, count 0 2006.285.18:01:46.23#ibcon#*after write, iclass 20, count 0 2006.285.18:01:46.23#ibcon#*before return 0, iclass 20, count 0 2006.285.18:01:46.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:01:46.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:01:46.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:01:46.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:01:46.23$vck44/vb=3,4 2006.285.18:01:46.23#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.18:01:46.23#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.18:01:46.23#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:46.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:01:46.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:01:46.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:01:46.29#ibcon#enter wrdev, iclass 22, count 2 2006.285.18:01:46.29#ibcon#first serial, iclass 22, count 2 2006.285.18:01:46.29#ibcon#enter sib2, iclass 22, count 2 2006.285.18:01:46.29#ibcon#flushed, iclass 22, count 2 2006.285.18:01:46.29#ibcon#about to write, iclass 22, count 2 2006.285.18:01:46.29#ibcon#wrote, iclass 22, count 2 2006.285.18:01:46.29#ibcon#about to read 3, iclass 22, count 2 2006.285.18:01:46.31#ibcon#read 3, iclass 22, count 2 2006.285.18:01:46.31#ibcon#about to read 4, iclass 22, count 2 2006.285.18:01:46.31#ibcon#read 4, iclass 22, count 2 2006.285.18:01:46.31#ibcon#about to read 5, iclass 22, count 2 2006.285.18:01:46.31#ibcon#read 5, iclass 22, count 2 2006.285.18:01:46.31#ibcon#about to read 6, iclass 22, count 2 2006.285.18:01:46.31#ibcon#read 6, iclass 22, count 2 2006.285.18:01:46.31#ibcon#end of sib2, iclass 22, count 2 2006.285.18:01:46.31#ibcon#*mode == 0, iclass 22, count 2 2006.285.18:01:46.31#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.18:01:46.31#ibcon#[27=AT03-04\r\n] 2006.285.18:01:46.31#ibcon#*before write, iclass 22, count 2 2006.285.18:01:46.31#ibcon#enter sib2, iclass 22, count 2 2006.285.18:01:46.31#ibcon#flushed, iclass 22, count 2 2006.285.18:01:46.31#ibcon#about to write, iclass 22, count 2 2006.285.18:01:46.31#ibcon#wrote, iclass 22, count 2 2006.285.18:01:46.31#ibcon#about to read 3, iclass 22, count 2 2006.285.18:01:46.34#ibcon#read 3, iclass 22, count 2 2006.285.18:01:46.34#ibcon#about to read 4, iclass 22, count 2 2006.285.18:01:46.34#ibcon#read 4, iclass 22, count 2 2006.285.18:01:46.34#ibcon#about to read 5, iclass 22, count 2 2006.285.18:01:46.34#ibcon#read 5, iclass 22, count 2 2006.285.18:01:46.34#ibcon#about to read 6, iclass 22, count 2 2006.285.18:01:46.34#ibcon#read 6, iclass 22, count 2 2006.285.18:01:46.34#ibcon#end of sib2, iclass 22, count 2 2006.285.18:01:46.34#ibcon#*after write, iclass 22, count 2 2006.285.18:01:46.34#ibcon#*before return 0, iclass 22, count 2 2006.285.18:01:46.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:01:46.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:01:46.34#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.18:01:46.34#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:46.34#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:01:46.46#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:01:46.46#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:01:46.46#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:01:46.46#ibcon#first serial, iclass 22, count 0 2006.285.18:01:46.46#ibcon#enter sib2, iclass 22, count 0 2006.285.18:01:46.46#ibcon#flushed, iclass 22, count 0 2006.285.18:01:46.46#ibcon#about to write, iclass 22, count 0 2006.285.18:01:46.46#ibcon#wrote, iclass 22, count 0 2006.285.18:01:46.46#ibcon#about to read 3, iclass 22, count 0 2006.285.18:01:46.48#ibcon#read 3, iclass 22, count 0 2006.285.18:01:46.48#ibcon#about to read 4, iclass 22, count 0 2006.285.18:01:46.48#ibcon#read 4, iclass 22, count 0 2006.285.18:01:46.48#ibcon#about to read 5, iclass 22, count 0 2006.285.18:01:46.48#ibcon#read 5, iclass 22, count 0 2006.285.18:01:46.48#ibcon#about to read 6, iclass 22, count 0 2006.285.18:01:46.48#ibcon#read 6, iclass 22, count 0 2006.285.18:01:46.48#ibcon#end of sib2, iclass 22, count 0 2006.285.18:01:46.48#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:01:46.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:01:46.48#ibcon#[27=USB\r\n] 2006.285.18:01:46.48#ibcon#*before write, iclass 22, count 0 2006.285.18:01:46.48#ibcon#enter sib2, iclass 22, count 0 2006.285.18:01:46.48#ibcon#flushed, iclass 22, count 0 2006.285.18:01:46.48#ibcon#about to write, iclass 22, count 0 2006.285.18:01:46.48#ibcon#wrote, iclass 22, count 0 2006.285.18:01:46.48#ibcon#about to read 3, iclass 22, count 0 2006.285.18:01:46.51#ibcon#read 3, iclass 22, count 0 2006.285.18:01:46.51#ibcon#about to read 4, iclass 22, count 0 2006.285.18:01:46.51#ibcon#read 4, iclass 22, count 0 2006.285.18:01:46.51#ibcon#about to read 5, iclass 22, count 0 2006.285.18:01:46.51#ibcon#read 5, iclass 22, count 0 2006.285.18:01:46.51#ibcon#about to read 6, iclass 22, count 0 2006.285.18:01:46.51#ibcon#read 6, iclass 22, count 0 2006.285.18:01:46.51#ibcon#end of sib2, iclass 22, count 0 2006.285.18:01:46.51#ibcon#*after write, iclass 22, count 0 2006.285.18:01:46.51#ibcon#*before return 0, iclass 22, count 0 2006.285.18:01:46.51#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:01:46.51#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:01:46.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:01:46.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:01:46.51$vck44/vblo=4,679.99 2006.285.18:01:46.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.18:01:46.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.18:01:46.51#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:46.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:01:46.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:01:46.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:01:46.51#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:01:46.51#ibcon#first serial, iclass 24, count 0 2006.285.18:01:46.51#ibcon#enter sib2, iclass 24, count 0 2006.285.18:01:46.51#ibcon#flushed, iclass 24, count 0 2006.285.18:01:46.51#ibcon#about to write, iclass 24, count 0 2006.285.18:01:46.51#ibcon#wrote, iclass 24, count 0 2006.285.18:01:46.51#ibcon#about to read 3, iclass 24, count 0 2006.285.18:01:46.53#ibcon#read 3, iclass 24, count 0 2006.285.18:01:46.53#ibcon#about to read 4, iclass 24, count 0 2006.285.18:01:46.53#ibcon#read 4, iclass 24, count 0 2006.285.18:01:46.53#ibcon#about to read 5, iclass 24, count 0 2006.285.18:01:46.53#ibcon#read 5, iclass 24, count 0 2006.285.18:01:46.53#ibcon#about to read 6, iclass 24, count 0 2006.285.18:01:46.53#ibcon#read 6, iclass 24, count 0 2006.285.18:01:46.53#ibcon#end of sib2, iclass 24, count 0 2006.285.18:01:46.53#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:01:46.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:01:46.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.18:01:46.53#ibcon#*before write, iclass 24, count 0 2006.285.18:01:46.53#ibcon#enter sib2, iclass 24, count 0 2006.285.18:01:46.53#ibcon#flushed, iclass 24, count 0 2006.285.18:01:46.53#ibcon#about to write, iclass 24, count 0 2006.285.18:01:46.53#ibcon#wrote, iclass 24, count 0 2006.285.18:01:46.53#ibcon#about to read 3, iclass 24, count 0 2006.285.18:01:46.57#ibcon#read 3, iclass 24, count 0 2006.285.18:01:46.57#ibcon#about to read 4, iclass 24, count 0 2006.285.18:01:46.57#ibcon#read 4, iclass 24, count 0 2006.285.18:01:46.57#ibcon#about to read 5, iclass 24, count 0 2006.285.18:01:46.57#ibcon#read 5, iclass 24, count 0 2006.285.18:01:46.57#ibcon#about to read 6, iclass 24, count 0 2006.285.18:01:46.57#ibcon#read 6, iclass 24, count 0 2006.285.18:01:46.57#ibcon#end of sib2, iclass 24, count 0 2006.285.18:01:46.57#ibcon#*after write, iclass 24, count 0 2006.285.18:01:46.57#ibcon#*before return 0, iclass 24, count 0 2006.285.18:01:46.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:01:46.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:01:46.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:01:46.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:01:46.57$vck44/vb=4,5 2006.285.18:01:46.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.18:01:46.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.18:01:46.57#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:46.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:01:46.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:01:46.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:01:46.63#ibcon#enter wrdev, iclass 26, count 2 2006.285.18:01:46.63#ibcon#first serial, iclass 26, count 2 2006.285.18:01:46.63#ibcon#enter sib2, iclass 26, count 2 2006.285.18:01:46.63#ibcon#flushed, iclass 26, count 2 2006.285.18:01:46.63#ibcon#about to write, iclass 26, count 2 2006.285.18:01:46.63#ibcon#wrote, iclass 26, count 2 2006.285.18:01:46.63#ibcon#about to read 3, iclass 26, count 2 2006.285.18:01:46.65#ibcon#read 3, iclass 26, count 2 2006.285.18:01:46.65#ibcon#about to read 4, iclass 26, count 2 2006.285.18:01:46.65#ibcon#read 4, iclass 26, count 2 2006.285.18:01:46.65#ibcon#about to read 5, iclass 26, count 2 2006.285.18:01:46.65#ibcon#read 5, iclass 26, count 2 2006.285.18:01:46.65#ibcon#about to read 6, iclass 26, count 2 2006.285.18:01:46.65#ibcon#read 6, iclass 26, count 2 2006.285.18:01:46.65#ibcon#end of sib2, iclass 26, count 2 2006.285.18:01:46.65#ibcon#*mode == 0, iclass 26, count 2 2006.285.18:01:46.65#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.18:01:46.65#ibcon#[27=AT04-05\r\n] 2006.285.18:01:46.65#ibcon#*before write, iclass 26, count 2 2006.285.18:01:46.65#ibcon#enter sib2, iclass 26, count 2 2006.285.18:01:46.65#ibcon#flushed, iclass 26, count 2 2006.285.18:01:46.65#ibcon#about to write, iclass 26, count 2 2006.285.18:01:46.65#ibcon#wrote, iclass 26, count 2 2006.285.18:01:46.65#ibcon#about to read 3, iclass 26, count 2 2006.285.18:01:46.68#ibcon#read 3, iclass 26, count 2 2006.285.18:01:46.68#ibcon#about to read 4, iclass 26, count 2 2006.285.18:01:46.68#ibcon#read 4, iclass 26, count 2 2006.285.18:01:46.68#ibcon#about to read 5, iclass 26, count 2 2006.285.18:01:46.68#ibcon#read 5, iclass 26, count 2 2006.285.18:01:46.68#ibcon#about to read 6, iclass 26, count 2 2006.285.18:01:46.68#ibcon#read 6, iclass 26, count 2 2006.285.18:01:46.68#ibcon#end of sib2, iclass 26, count 2 2006.285.18:01:46.68#ibcon#*after write, iclass 26, count 2 2006.285.18:01:46.68#ibcon#*before return 0, iclass 26, count 2 2006.285.18:01:46.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:01:46.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:01:46.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.18:01:46.68#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:46.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:01:46.80#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:01:46.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:01:46.80#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:01:46.80#ibcon#first serial, iclass 26, count 0 2006.285.18:01:46.80#ibcon#enter sib2, iclass 26, count 0 2006.285.18:01:46.80#ibcon#flushed, iclass 26, count 0 2006.285.18:01:46.80#ibcon#about to write, iclass 26, count 0 2006.285.18:01:46.80#ibcon#wrote, iclass 26, count 0 2006.285.18:01:46.80#ibcon#about to read 3, iclass 26, count 0 2006.285.18:01:46.82#ibcon#read 3, iclass 26, count 0 2006.285.18:01:46.82#ibcon#about to read 4, iclass 26, count 0 2006.285.18:01:46.82#ibcon#read 4, iclass 26, count 0 2006.285.18:01:46.82#ibcon#about to read 5, iclass 26, count 0 2006.285.18:01:46.82#ibcon#read 5, iclass 26, count 0 2006.285.18:01:46.82#ibcon#about to read 6, iclass 26, count 0 2006.285.18:01:46.82#ibcon#read 6, iclass 26, count 0 2006.285.18:01:46.82#ibcon#end of sib2, iclass 26, count 0 2006.285.18:01:46.82#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:01:46.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:01:46.82#ibcon#[27=USB\r\n] 2006.285.18:01:46.82#ibcon#*before write, iclass 26, count 0 2006.285.18:01:46.82#ibcon#enter sib2, iclass 26, count 0 2006.285.18:01:46.82#ibcon#flushed, iclass 26, count 0 2006.285.18:01:46.82#ibcon#about to write, iclass 26, count 0 2006.285.18:01:46.82#ibcon#wrote, iclass 26, count 0 2006.285.18:01:46.82#ibcon#about to read 3, iclass 26, count 0 2006.285.18:01:46.85#ibcon#read 3, iclass 26, count 0 2006.285.18:01:46.85#ibcon#about to read 4, iclass 26, count 0 2006.285.18:01:46.85#ibcon#read 4, iclass 26, count 0 2006.285.18:01:46.85#ibcon#about to read 5, iclass 26, count 0 2006.285.18:01:46.85#ibcon#read 5, iclass 26, count 0 2006.285.18:01:46.85#ibcon#about to read 6, iclass 26, count 0 2006.285.18:01:46.85#ibcon#read 6, iclass 26, count 0 2006.285.18:01:46.85#ibcon#end of sib2, iclass 26, count 0 2006.285.18:01:46.85#ibcon#*after write, iclass 26, count 0 2006.285.18:01:46.85#ibcon#*before return 0, iclass 26, count 0 2006.285.18:01:46.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:01:46.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:01:46.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:01:46.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:01:46.85$vck44/vblo=5,709.99 2006.285.18:01:46.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.18:01:46.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.18:01:46.93#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:46.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:01:46.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:01:46.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:01:46.93#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:01:46.93#ibcon#first serial, iclass 28, count 0 2006.285.18:01:46.93#ibcon#enter sib2, iclass 28, count 0 2006.285.18:01:46.93#ibcon#flushed, iclass 28, count 0 2006.285.18:01:46.93#ibcon#about to write, iclass 28, count 0 2006.285.18:01:46.93#ibcon#wrote, iclass 28, count 0 2006.285.18:01:46.93#ibcon#about to read 3, iclass 28, count 0 2006.285.18:01:46.95#ibcon#read 3, iclass 28, count 0 2006.285.18:01:46.95#ibcon#about to read 4, iclass 28, count 0 2006.285.18:01:46.95#ibcon#read 4, iclass 28, count 0 2006.285.18:01:46.95#ibcon#about to read 5, iclass 28, count 0 2006.285.18:01:46.95#ibcon#read 5, iclass 28, count 0 2006.285.18:01:46.95#ibcon#about to read 6, iclass 28, count 0 2006.285.18:01:46.95#ibcon#read 6, iclass 28, count 0 2006.285.18:01:46.95#ibcon#end of sib2, iclass 28, count 0 2006.285.18:01:46.95#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:01:46.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:01:46.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.18:01:46.95#ibcon#*before write, iclass 28, count 0 2006.285.18:01:46.95#ibcon#enter sib2, iclass 28, count 0 2006.285.18:01:46.95#ibcon#flushed, iclass 28, count 0 2006.285.18:01:46.95#ibcon#about to write, iclass 28, count 0 2006.285.18:01:46.95#ibcon#wrote, iclass 28, count 0 2006.285.18:01:46.95#ibcon#about to read 3, iclass 28, count 0 2006.285.18:01:46.99#ibcon#read 3, iclass 28, count 0 2006.285.18:01:46.99#ibcon#about to read 4, iclass 28, count 0 2006.285.18:01:46.99#ibcon#read 4, iclass 28, count 0 2006.285.18:01:46.99#ibcon#about to read 5, iclass 28, count 0 2006.285.18:01:46.99#ibcon#read 5, iclass 28, count 0 2006.285.18:01:46.99#ibcon#about to read 6, iclass 28, count 0 2006.285.18:01:46.99#ibcon#read 6, iclass 28, count 0 2006.285.18:01:46.99#ibcon#end of sib2, iclass 28, count 0 2006.285.18:01:46.99#ibcon#*after write, iclass 28, count 0 2006.285.18:01:46.99#ibcon#*before return 0, iclass 28, count 0 2006.285.18:01:46.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:01:46.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:01:46.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:01:46.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:01:46.99$vck44/vb=5,4 2006.285.18:01:46.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.18:01:46.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.18:01:46.99#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:46.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:01:46.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:01:46.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:01:46.99#ibcon#enter wrdev, iclass 30, count 2 2006.285.18:01:46.99#ibcon#first serial, iclass 30, count 2 2006.285.18:01:46.99#ibcon#enter sib2, iclass 30, count 2 2006.285.18:01:46.99#ibcon#flushed, iclass 30, count 2 2006.285.18:01:46.99#ibcon#about to write, iclass 30, count 2 2006.285.18:01:46.99#ibcon#wrote, iclass 30, count 2 2006.285.18:01:46.99#ibcon#about to read 3, iclass 30, count 2 2006.285.18:01:47.01#ibcon#read 3, iclass 30, count 2 2006.285.18:01:47.01#ibcon#about to read 4, iclass 30, count 2 2006.285.18:01:47.01#ibcon#read 4, iclass 30, count 2 2006.285.18:01:47.01#ibcon#about to read 5, iclass 30, count 2 2006.285.18:01:47.01#ibcon#read 5, iclass 30, count 2 2006.285.18:01:47.01#ibcon#about to read 6, iclass 30, count 2 2006.285.18:01:47.01#ibcon#read 6, iclass 30, count 2 2006.285.18:01:47.01#ibcon#end of sib2, iclass 30, count 2 2006.285.18:01:47.01#ibcon#*mode == 0, iclass 30, count 2 2006.285.18:01:47.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.18:01:47.01#ibcon#[27=AT05-04\r\n] 2006.285.18:01:47.01#ibcon#*before write, iclass 30, count 2 2006.285.18:01:47.01#ibcon#enter sib2, iclass 30, count 2 2006.285.18:01:47.01#ibcon#flushed, iclass 30, count 2 2006.285.18:01:47.01#ibcon#about to write, iclass 30, count 2 2006.285.18:01:47.01#ibcon#wrote, iclass 30, count 2 2006.285.18:01:47.01#ibcon#about to read 3, iclass 30, count 2 2006.285.18:01:47.04#ibcon#read 3, iclass 30, count 2 2006.285.18:01:47.04#ibcon#about to read 4, iclass 30, count 2 2006.285.18:01:47.04#ibcon#read 4, iclass 30, count 2 2006.285.18:01:47.04#ibcon#about to read 5, iclass 30, count 2 2006.285.18:01:47.04#ibcon#read 5, iclass 30, count 2 2006.285.18:01:47.04#ibcon#about to read 6, iclass 30, count 2 2006.285.18:01:47.04#ibcon#read 6, iclass 30, count 2 2006.285.18:01:47.04#ibcon#end of sib2, iclass 30, count 2 2006.285.18:01:47.04#ibcon#*after write, iclass 30, count 2 2006.285.18:01:47.04#ibcon#*before return 0, iclass 30, count 2 2006.285.18:01:47.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:01:47.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:01:47.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.18:01:47.04#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:47.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:01:47.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:01:47.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:01:47.16#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:01:47.16#ibcon#first serial, iclass 30, count 0 2006.285.18:01:47.16#ibcon#enter sib2, iclass 30, count 0 2006.285.18:01:47.16#ibcon#flushed, iclass 30, count 0 2006.285.18:01:47.16#ibcon#about to write, iclass 30, count 0 2006.285.18:01:47.16#ibcon#wrote, iclass 30, count 0 2006.285.18:01:47.16#ibcon#about to read 3, iclass 30, count 0 2006.285.18:01:47.18#ibcon#read 3, iclass 30, count 0 2006.285.18:01:47.18#ibcon#about to read 4, iclass 30, count 0 2006.285.18:01:47.18#ibcon#read 4, iclass 30, count 0 2006.285.18:01:47.18#ibcon#about to read 5, iclass 30, count 0 2006.285.18:01:47.18#ibcon#read 5, iclass 30, count 0 2006.285.18:01:47.18#ibcon#about to read 6, iclass 30, count 0 2006.285.18:01:47.18#ibcon#read 6, iclass 30, count 0 2006.285.18:01:47.18#ibcon#end of sib2, iclass 30, count 0 2006.285.18:01:47.18#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:01:47.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:01:47.18#ibcon#[27=USB\r\n] 2006.285.18:01:47.18#ibcon#*before write, iclass 30, count 0 2006.285.18:01:47.18#ibcon#enter sib2, iclass 30, count 0 2006.285.18:01:47.18#ibcon#flushed, iclass 30, count 0 2006.285.18:01:47.18#ibcon#about to write, iclass 30, count 0 2006.285.18:01:47.18#ibcon#wrote, iclass 30, count 0 2006.285.18:01:47.18#ibcon#about to read 3, iclass 30, count 0 2006.285.18:01:47.21#ibcon#read 3, iclass 30, count 0 2006.285.18:01:47.21#ibcon#about to read 4, iclass 30, count 0 2006.285.18:01:47.21#ibcon#read 4, iclass 30, count 0 2006.285.18:01:47.21#ibcon#about to read 5, iclass 30, count 0 2006.285.18:01:47.21#ibcon#read 5, iclass 30, count 0 2006.285.18:01:47.21#ibcon#about to read 6, iclass 30, count 0 2006.285.18:01:47.21#ibcon#read 6, iclass 30, count 0 2006.285.18:01:47.21#ibcon#end of sib2, iclass 30, count 0 2006.285.18:01:47.21#ibcon#*after write, iclass 30, count 0 2006.285.18:01:47.21#ibcon#*before return 0, iclass 30, count 0 2006.285.18:01:47.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:01:47.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:01:47.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:01:47.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:01:47.21$vck44/vblo=6,719.99 2006.285.18:01:47.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.18:01:47.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.18:01:47.21#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:47.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:01:47.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:01:47.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:01:47.21#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:01:47.21#ibcon#first serial, iclass 32, count 0 2006.285.18:01:47.21#ibcon#enter sib2, iclass 32, count 0 2006.285.18:01:47.21#ibcon#flushed, iclass 32, count 0 2006.285.18:01:47.21#ibcon#about to write, iclass 32, count 0 2006.285.18:01:47.21#ibcon#wrote, iclass 32, count 0 2006.285.18:01:47.21#ibcon#about to read 3, iclass 32, count 0 2006.285.18:01:47.23#ibcon#read 3, iclass 32, count 0 2006.285.18:01:47.23#ibcon#about to read 4, iclass 32, count 0 2006.285.18:01:47.23#ibcon#read 4, iclass 32, count 0 2006.285.18:01:47.23#ibcon#about to read 5, iclass 32, count 0 2006.285.18:01:47.23#ibcon#read 5, iclass 32, count 0 2006.285.18:01:47.23#ibcon#about to read 6, iclass 32, count 0 2006.285.18:01:47.23#ibcon#read 6, iclass 32, count 0 2006.285.18:01:47.23#ibcon#end of sib2, iclass 32, count 0 2006.285.18:01:47.23#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:01:47.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:01:47.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.18:01:47.23#ibcon#*before write, iclass 32, count 0 2006.285.18:01:47.23#ibcon#enter sib2, iclass 32, count 0 2006.285.18:01:47.23#ibcon#flushed, iclass 32, count 0 2006.285.18:01:47.23#ibcon#about to write, iclass 32, count 0 2006.285.18:01:47.23#ibcon#wrote, iclass 32, count 0 2006.285.18:01:47.23#ibcon#about to read 3, iclass 32, count 0 2006.285.18:01:47.27#ibcon#read 3, iclass 32, count 0 2006.285.18:01:47.27#ibcon#about to read 4, iclass 32, count 0 2006.285.18:01:47.27#ibcon#read 4, iclass 32, count 0 2006.285.18:01:47.27#ibcon#about to read 5, iclass 32, count 0 2006.285.18:01:47.27#ibcon#read 5, iclass 32, count 0 2006.285.18:01:47.27#ibcon#about to read 6, iclass 32, count 0 2006.285.18:01:47.27#ibcon#read 6, iclass 32, count 0 2006.285.18:01:47.27#ibcon#end of sib2, iclass 32, count 0 2006.285.18:01:47.27#ibcon#*after write, iclass 32, count 0 2006.285.18:01:47.27#ibcon#*before return 0, iclass 32, count 0 2006.285.18:01:47.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:01:47.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:01:47.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:01:47.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:01:47.27$vck44/vb=6,3 2006.285.18:01:47.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.18:01:47.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.18:01:47.27#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:47.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:01:47.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:01:47.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:01:47.33#ibcon#enter wrdev, iclass 34, count 2 2006.285.18:01:47.33#ibcon#first serial, iclass 34, count 2 2006.285.18:01:47.33#ibcon#enter sib2, iclass 34, count 2 2006.285.18:01:47.33#ibcon#flushed, iclass 34, count 2 2006.285.18:01:47.33#ibcon#about to write, iclass 34, count 2 2006.285.18:01:47.33#ibcon#wrote, iclass 34, count 2 2006.285.18:01:47.33#ibcon#about to read 3, iclass 34, count 2 2006.285.18:01:47.35#ibcon#read 3, iclass 34, count 2 2006.285.18:01:47.35#ibcon#about to read 4, iclass 34, count 2 2006.285.18:01:47.35#ibcon#read 4, iclass 34, count 2 2006.285.18:01:47.35#ibcon#about to read 5, iclass 34, count 2 2006.285.18:01:47.35#ibcon#read 5, iclass 34, count 2 2006.285.18:01:47.35#ibcon#about to read 6, iclass 34, count 2 2006.285.18:01:47.35#ibcon#read 6, iclass 34, count 2 2006.285.18:01:47.35#ibcon#end of sib2, iclass 34, count 2 2006.285.18:01:47.35#ibcon#*mode == 0, iclass 34, count 2 2006.285.18:01:47.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.18:01:47.35#ibcon#[27=AT06-03\r\n] 2006.285.18:01:47.35#ibcon#*before write, iclass 34, count 2 2006.285.18:01:47.35#ibcon#enter sib2, iclass 34, count 2 2006.285.18:01:47.35#ibcon#flushed, iclass 34, count 2 2006.285.18:01:47.35#ibcon#about to write, iclass 34, count 2 2006.285.18:01:47.35#ibcon#wrote, iclass 34, count 2 2006.285.18:01:47.35#ibcon#about to read 3, iclass 34, count 2 2006.285.18:01:47.38#ibcon#read 3, iclass 34, count 2 2006.285.18:01:47.38#ibcon#about to read 4, iclass 34, count 2 2006.285.18:01:47.38#ibcon#read 4, iclass 34, count 2 2006.285.18:01:47.38#ibcon#about to read 5, iclass 34, count 2 2006.285.18:01:47.38#ibcon#read 5, iclass 34, count 2 2006.285.18:01:47.38#ibcon#about to read 6, iclass 34, count 2 2006.285.18:01:47.38#ibcon#read 6, iclass 34, count 2 2006.285.18:01:47.38#ibcon#end of sib2, iclass 34, count 2 2006.285.18:01:47.38#ibcon#*after write, iclass 34, count 2 2006.285.18:01:47.38#ibcon#*before return 0, iclass 34, count 2 2006.285.18:01:47.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:01:47.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:01:47.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.18:01:47.38#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:47.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:01:47.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:01:47.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:01:47.50#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:01:47.50#ibcon#first serial, iclass 34, count 0 2006.285.18:01:47.50#ibcon#enter sib2, iclass 34, count 0 2006.285.18:01:47.50#ibcon#flushed, iclass 34, count 0 2006.285.18:01:47.50#ibcon#about to write, iclass 34, count 0 2006.285.18:01:47.50#ibcon#wrote, iclass 34, count 0 2006.285.18:01:47.50#ibcon#about to read 3, iclass 34, count 0 2006.285.18:01:47.52#ibcon#read 3, iclass 34, count 0 2006.285.18:01:47.52#ibcon#about to read 4, iclass 34, count 0 2006.285.18:01:47.52#ibcon#read 4, iclass 34, count 0 2006.285.18:01:47.52#ibcon#about to read 5, iclass 34, count 0 2006.285.18:01:47.52#ibcon#read 5, iclass 34, count 0 2006.285.18:01:47.52#ibcon#about to read 6, iclass 34, count 0 2006.285.18:01:47.52#ibcon#read 6, iclass 34, count 0 2006.285.18:01:47.52#ibcon#end of sib2, iclass 34, count 0 2006.285.18:01:47.52#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:01:47.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:01:47.52#ibcon#[27=USB\r\n] 2006.285.18:01:47.52#ibcon#*before write, iclass 34, count 0 2006.285.18:01:47.52#ibcon#enter sib2, iclass 34, count 0 2006.285.18:01:47.52#ibcon#flushed, iclass 34, count 0 2006.285.18:01:47.52#ibcon#about to write, iclass 34, count 0 2006.285.18:01:47.52#ibcon#wrote, iclass 34, count 0 2006.285.18:01:47.52#ibcon#about to read 3, iclass 34, count 0 2006.285.18:01:47.55#ibcon#read 3, iclass 34, count 0 2006.285.18:01:47.55#ibcon#about to read 4, iclass 34, count 0 2006.285.18:01:47.55#ibcon#read 4, iclass 34, count 0 2006.285.18:01:47.55#ibcon#about to read 5, iclass 34, count 0 2006.285.18:01:47.55#ibcon#read 5, iclass 34, count 0 2006.285.18:01:47.55#ibcon#about to read 6, iclass 34, count 0 2006.285.18:01:47.55#ibcon#read 6, iclass 34, count 0 2006.285.18:01:47.55#ibcon#end of sib2, iclass 34, count 0 2006.285.18:01:47.55#ibcon#*after write, iclass 34, count 0 2006.285.18:01:47.55#ibcon#*before return 0, iclass 34, count 0 2006.285.18:01:47.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:01:47.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:01:47.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:01:47.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:01:47.55$vck44/vblo=7,734.99 2006.285.18:01:47.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.18:01:47.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.18:01:47.55#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:47.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:01:47.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:01:47.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:01:47.55#ibcon#enter wrdev, iclass 36, count 0 2006.285.18:01:47.55#ibcon#first serial, iclass 36, count 0 2006.285.18:01:47.55#ibcon#enter sib2, iclass 36, count 0 2006.285.18:01:47.55#ibcon#flushed, iclass 36, count 0 2006.285.18:01:47.55#ibcon#about to write, iclass 36, count 0 2006.285.18:01:47.55#ibcon#wrote, iclass 36, count 0 2006.285.18:01:47.55#ibcon#about to read 3, iclass 36, count 0 2006.285.18:01:47.57#ibcon#read 3, iclass 36, count 0 2006.285.18:01:47.57#ibcon#about to read 4, iclass 36, count 0 2006.285.18:01:47.57#ibcon#read 4, iclass 36, count 0 2006.285.18:01:47.57#ibcon#about to read 5, iclass 36, count 0 2006.285.18:01:47.57#ibcon#read 5, iclass 36, count 0 2006.285.18:01:47.57#ibcon#about to read 6, iclass 36, count 0 2006.285.18:01:47.57#ibcon#read 6, iclass 36, count 0 2006.285.18:01:47.57#ibcon#end of sib2, iclass 36, count 0 2006.285.18:01:47.57#ibcon#*mode == 0, iclass 36, count 0 2006.285.18:01:47.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.18:01:47.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.18:01:47.57#ibcon#*before write, iclass 36, count 0 2006.285.18:01:47.57#ibcon#enter sib2, iclass 36, count 0 2006.285.18:01:47.57#ibcon#flushed, iclass 36, count 0 2006.285.18:01:47.57#ibcon#about to write, iclass 36, count 0 2006.285.18:01:47.57#ibcon#wrote, iclass 36, count 0 2006.285.18:01:47.57#ibcon#about to read 3, iclass 36, count 0 2006.285.18:01:47.61#ibcon#read 3, iclass 36, count 0 2006.285.18:01:47.61#ibcon#about to read 4, iclass 36, count 0 2006.285.18:01:47.61#ibcon#read 4, iclass 36, count 0 2006.285.18:01:47.61#ibcon#about to read 5, iclass 36, count 0 2006.285.18:01:47.61#ibcon#read 5, iclass 36, count 0 2006.285.18:01:47.61#ibcon#about to read 6, iclass 36, count 0 2006.285.18:01:47.61#ibcon#read 6, iclass 36, count 0 2006.285.18:01:47.61#ibcon#end of sib2, iclass 36, count 0 2006.285.18:01:47.61#ibcon#*after write, iclass 36, count 0 2006.285.18:01:47.61#ibcon#*before return 0, iclass 36, count 0 2006.285.18:01:47.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:01:47.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:01:47.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.18:01:47.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.18:01:47.61$vck44/vb=7,4 2006.285.18:01:47.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.18:01:47.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.18:01:47.61#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:47.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:01:47.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:01:47.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:01:47.67#ibcon#enter wrdev, iclass 38, count 2 2006.285.18:01:47.67#ibcon#first serial, iclass 38, count 2 2006.285.18:01:47.67#ibcon#enter sib2, iclass 38, count 2 2006.285.18:01:47.67#ibcon#flushed, iclass 38, count 2 2006.285.18:01:47.67#ibcon#about to write, iclass 38, count 2 2006.285.18:01:47.67#ibcon#wrote, iclass 38, count 2 2006.285.18:01:47.67#ibcon#about to read 3, iclass 38, count 2 2006.285.18:01:47.69#ibcon#read 3, iclass 38, count 2 2006.285.18:01:47.69#ibcon#about to read 4, iclass 38, count 2 2006.285.18:01:47.69#ibcon#read 4, iclass 38, count 2 2006.285.18:01:47.69#ibcon#about to read 5, iclass 38, count 2 2006.285.18:01:47.69#ibcon#read 5, iclass 38, count 2 2006.285.18:01:47.69#ibcon#about to read 6, iclass 38, count 2 2006.285.18:01:47.69#ibcon#read 6, iclass 38, count 2 2006.285.18:01:47.69#ibcon#end of sib2, iclass 38, count 2 2006.285.18:01:47.69#ibcon#*mode == 0, iclass 38, count 2 2006.285.18:01:47.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.18:01:47.69#ibcon#[27=AT07-04\r\n] 2006.285.18:01:47.69#ibcon#*before write, iclass 38, count 2 2006.285.18:01:47.69#ibcon#enter sib2, iclass 38, count 2 2006.285.18:01:47.69#ibcon#flushed, iclass 38, count 2 2006.285.18:01:47.69#ibcon#about to write, iclass 38, count 2 2006.285.18:01:47.69#ibcon#wrote, iclass 38, count 2 2006.285.18:01:47.69#ibcon#about to read 3, iclass 38, count 2 2006.285.18:01:47.72#ibcon#read 3, iclass 38, count 2 2006.285.18:01:47.72#ibcon#about to read 4, iclass 38, count 2 2006.285.18:01:47.72#ibcon#read 4, iclass 38, count 2 2006.285.18:01:47.72#ibcon#about to read 5, iclass 38, count 2 2006.285.18:01:47.72#ibcon#read 5, iclass 38, count 2 2006.285.18:01:47.72#ibcon#about to read 6, iclass 38, count 2 2006.285.18:01:47.72#ibcon#read 6, iclass 38, count 2 2006.285.18:01:47.72#ibcon#end of sib2, iclass 38, count 2 2006.285.18:01:47.72#ibcon#*after write, iclass 38, count 2 2006.285.18:01:47.72#ibcon#*before return 0, iclass 38, count 2 2006.285.18:01:47.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:01:47.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:01:47.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.18:01:47.72#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:47.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:01:47.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:01:47.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:01:47.84#ibcon#enter wrdev, iclass 38, count 0 2006.285.18:01:47.84#ibcon#first serial, iclass 38, count 0 2006.285.18:01:47.84#ibcon#enter sib2, iclass 38, count 0 2006.285.18:01:47.84#ibcon#flushed, iclass 38, count 0 2006.285.18:01:47.84#ibcon#about to write, iclass 38, count 0 2006.285.18:01:47.84#ibcon#wrote, iclass 38, count 0 2006.285.18:01:47.84#ibcon#about to read 3, iclass 38, count 0 2006.285.18:01:47.86#ibcon#read 3, iclass 38, count 0 2006.285.18:01:47.86#ibcon#about to read 4, iclass 38, count 0 2006.285.18:01:47.86#ibcon#read 4, iclass 38, count 0 2006.285.18:01:47.86#ibcon#about to read 5, iclass 38, count 0 2006.285.18:01:47.86#ibcon#read 5, iclass 38, count 0 2006.285.18:01:47.86#ibcon#about to read 6, iclass 38, count 0 2006.285.18:01:47.86#ibcon#read 6, iclass 38, count 0 2006.285.18:01:47.86#ibcon#end of sib2, iclass 38, count 0 2006.285.18:01:47.86#ibcon#*mode == 0, iclass 38, count 0 2006.285.18:01:47.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.18:01:47.87#ibcon#[27=USB\r\n] 2006.285.18:01:47.87#ibcon#*before write, iclass 38, count 0 2006.285.18:01:47.87#ibcon#enter sib2, iclass 38, count 0 2006.285.18:01:47.87#ibcon#flushed, iclass 38, count 0 2006.285.18:01:47.87#ibcon#about to write, iclass 38, count 0 2006.285.18:01:47.87#ibcon#wrote, iclass 38, count 0 2006.285.18:01:47.87#ibcon#about to read 3, iclass 38, count 0 2006.285.18:01:47.90#ibcon#read 3, iclass 38, count 0 2006.285.18:01:47.90#ibcon#about to read 4, iclass 38, count 0 2006.285.18:01:47.90#ibcon#read 4, iclass 38, count 0 2006.285.18:01:47.90#ibcon#about to read 5, iclass 38, count 0 2006.285.18:01:47.90#ibcon#read 5, iclass 38, count 0 2006.285.18:01:47.90#ibcon#about to read 6, iclass 38, count 0 2006.285.18:01:47.90#ibcon#read 6, iclass 38, count 0 2006.285.18:01:47.90#ibcon#end of sib2, iclass 38, count 0 2006.285.18:01:47.90#ibcon#*after write, iclass 38, count 0 2006.285.18:01:47.90#ibcon#*before return 0, iclass 38, count 0 2006.285.18:01:47.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:01:47.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:01:47.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.18:01:47.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.18:01:47.90$vck44/vblo=8,744.99 2006.285.18:01:47.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.18:01:47.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.18:01:47.90#ibcon#ireg 17 cls_cnt 0 2006.285.18:01:47.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:01:47.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:01:47.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:01:47.90#ibcon#enter wrdev, iclass 40, count 0 2006.285.18:01:47.90#ibcon#first serial, iclass 40, count 0 2006.285.18:01:47.90#ibcon#enter sib2, iclass 40, count 0 2006.285.18:01:47.90#ibcon#flushed, iclass 40, count 0 2006.285.18:01:47.90#ibcon#about to write, iclass 40, count 0 2006.285.18:01:47.90#ibcon#wrote, iclass 40, count 0 2006.285.18:01:47.90#ibcon#about to read 3, iclass 40, count 0 2006.285.18:01:47.92#ibcon#read 3, iclass 40, count 0 2006.285.18:01:47.92#ibcon#about to read 4, iclass 40, count 0 2006.285.18:01:47.92#ibcon#read 4, iclass 40, count 0 2006.285.18:01:47.92#ibcon#about to read 5, iclass 40, count 0 2006.285.18:01:47.92#ibcon#read 5, iclass 40, count 0 2006.285.18:01:47.92#ibcon#about to read 6, iclass 40, count 0 2006.285.18:01:47.92#ibcon#read 6, iclass 40, count 0 2006.285.18:01:47.92#ibcon#end of sib2, iclass 40, count 0 2006.285.18:01:47.92#ibcon#*mode == 0, iclass 40, count 0 2006.285.18:01:47.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.18:01:47.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.18:01:47.92#ibcon#*before write, iclass 40, count 0 2006.285.18:01:47.92#ibcon#enter sib2, iclass 40, count 0 2006.285.18:01:47.92#ibcon#flushed, iclass 40, count 0 2006.285.18:01:47.92#ibcon#about to write, iclass 40, count 0 2006.285.18:01:47.92#ibcon#wrote, iclass 40, count 0 2006.285.18:01:47.92#ibcon#about to read 3, iclass 40, count 0 2006.285.18:01:47.96#ibcon#read 3, iclass 40, count 0 2006.285.18:01:47.96#ibcon#about to read 4, iclass 40, count 0 2006.285.18:01:47.96#ibcon#read 4, iclass 40, count 0 2006.285.18:01:47.96#ibcon#about to read 5, iclass 40, count 0 2006.285.18:01:47.96#ibcon#read 5, iclass 40, count 0 2006.285.18:01:47.96#ibcon#about to read 6, iclass 40, count 0 2006.285.18:01:47.96#ibcon#read 6, iclass 40, count 0 2006.285.18:01:47.96#ibcon#end of sib2, iclass 40, count 0 2006.285.18:01:47.96#ibcon#*after write, iclass 40, count 0 2006.285.18:01:47.96#ibcon#*before return 0, iclass 40, count 0 2006.285.18:01:47.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:01:47.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:01:47.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.18:01:47.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.18:01:47.96$vck44/vb=8,4 2006.285.18:01:47.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.18:01:47.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.18:01:47.96#ibcon#ireg 11 cls_cnt 2 2006.285.18:01:47.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:01:48.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:01:48.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:01:48.02#ibcon#enter wrdev, iclass 4, count 2 2006.285.18:01:48.02#ibcon#first serial, iclass 4, count 2 2006.285.18:01:48.02#ibcon#enter sib2, iclass 4, count 2 2006.285.18:01:48.02#ibcon#flushed, iclass 4, count 2 2006.285.18:01:48.02#ibcon#about to write, iclass 4, count 2 2006.285.18:01:48.02#ibcon#wrote, iclass 4, count 2 2006.285.18:01:48.02#ibcon#about to read 3, iclass 4, count 2 2006.285.18:01:48.04#ibcon#read 3, iclass 4, count 2 2006.285.18:01:48.04#ibcon#about to read 4, iclass 4, count 2 2006.285.18:01:48.04#ibcon#read 4, iclass 4, count 2 2006.285.18:01:48.04#ibcon#about to read 5, iclass 4, count 2 2006.285.18:01:48.04#ibcon#read 5, iclass 4, count 2 2006.285.18:01:48.04#ibcon#about to read 6, iclass 4, count 2 2006.285.18:01:48.04#ibcon#read 6, iclass 4, count 2 2006.285.18:01:48.04#ibcon#end of sib2, iclass 4, count 2 2006.285.18:01:48.04#ibcon#*mode == 0, iclass 4, count 2 2006.285.18:01:48.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.18:01:48.04#ibcon#[27=AT08-04\r\n] 2006.285.18:01:48.04#ibcon#*before write, iclass 4, count 2 2006.285.18:01:48.04#ibcon#enter sib2, iclass 4, count 2 2006.285.18:01:48.04#ibcon#flushed, iclass 4, count 2 2006.285.18:01:48.04#ibcon#about to write, iclass 4, count 2 2006.285.18:01:48.04#ibcon#wrote, iclass 4, count 2 2006.285.18:01:48.04#ibcon#about to read 3, iclass 4, count 2 2006.285.18:01:48.07#ibcon#read 3, iclass 4, count 2 2006.285.18:01:48.07#ibcon#about to read 4, iclass 4, count 2 2006.285.18:01:48.07#ibcon#read 4, iclass 4, count 2 2006.285.18:01:48.07#ibcon#about to read 5, iclass 4, count 2 2006.285.18:01:48.07#ibcon#read 5, iclass 4, count 2 2006.285.18:01:48.07#ibcon#about to read 6, iclass 4, count 2 2006.285.18:01:48.07#ibcon#read 6, iclass 4, count 2 2006.285.18:01:48.07#ibcon#end of sib2, iclass 4, count 2 2006.285.18:01:48.07#ibcon#*after write, iclass 4, count 2 2006.285.18:01:48.07#ibcon#*before return 0, iclass 4, count 2 2006.285.18:01:48.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:01:48.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:01:48.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.18:01:48.07#ibcon#ireg 7 cls_cnt 0 2006.285.18:01:48.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:01:48.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:01:48.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:01:48.19#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:01:48.19#ibcon#first serial, iclass 4, count 0 2006.285.18:01:48.19#ibcon#enter sib2, iclass 4, count 0 2006.285.18:01:48.19#ibcon#flushed, iclass 4, count 0 2006.285.18:01:48.19#ibcon#about to write, iclass 4, count 0 2006.285.18:01:48.19#ibcon#wrote, iclass 4, count 0 2006.285.18:01:48.19#ibcon#about to read 3, iclass 4, count 0 2006.285.18:01:48.21#ibcon#read 3, iclass 4, count 0 2006.285.18:01:48.21#ibcon#about to read 4, iclass 4, count 0 2006.285.18:01:48.21#ibcon#read 4, iclass 4, count 0 2006.285.18:01:48.21#ibcon#about to read 5, iclass 4, count 0 2006.285.18:01:48.21#ibcon#read 5, iclass 4, count 0 2006.285.18:01:48.21#ibcon#about to read 6, iclass 4, count 0 2006.285.18:01:48.21#ibcon#read 6, iclass 4, count 0 2006.285.18:01:48.21#ibcon#end of sib2, iclass 4, count 0 2006.285.18:01:48.21#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:01:48.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:01:48.21#ibcon#[27=USB\r\n] 2006.285.18:01:48.21#ibcon#*before write, iclass 4, count 0 2006.285.18:01:48.21#ibcon#enter sib2, iclass 4, count 0 2006.285.18:01:48.21#ibcon#flushed, iclass 4, count 0 2006.285.18:01:48.21#ibcon#about to write, iclass 4, count 0 2006.285.18:01:48.21#ibcon#wrote, iclass 4, count 0 2006.285.18:01:48.21#ibcon#about to read 3, iclass 4, count 0 2006.285.18:01:48.24#ibcon#read 3, iclass 4, count 0 2006.285.18:01:48.24#ibcon#about to read 4, iclass 4, count 0 2006.285.18:01:48.24#ibcon#read 4, iclass 4, count 0 2006.285.18:01:48.24#ibcon#about to read 5, iclass 4, count 0 2006.285.18:01:48.24#ibcon#read 5, iclass 4, count 0 2006.285.18:01:48.24#ibcon#about to read 6, iclass 4, count 0 2006.285.18:01:48.24#ibcon#read 6, iclass 4, count 0 2006.285.18:01:48.24#ibcon#end of sib2, iclass 4, count 0 2006.285.18:01:48.24#ibcon#*after write, iclass 4, count 0 2006.285.18:01:48.24#ibcon#*before return 0, iclass 4, count 0 2006.285.18:01:48.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:01:48.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:01:48.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:01:48.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:01:48.24$vck44/vabw=wide 2006.285.18:01:48.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.18:01:48.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.18:01:48.24#ibcon#ireg 8 cls_cnt 0 2006.285.18:01:48.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:01:48.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:01:48.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:01:48.24#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:01:48.24#ibcon#first serial, iclass 6, count 0 2006.285.18:01:48.24#ibcon#enter sib2, iclass 6, count 0 2006.285.18:01:48.24#ibcon#flushed, iclass 6, count 0 2006.285.18:01:48.24#ibcon#about to write, iclass 6, count 0 2006.285.18:01:48.24#ibcon#wrote, iclass 6, count 0 2006.285.18:01:48.24#ibcon#about to read 3, iclass 6, count 0 2006.285.18:01:48.26#ibcon#read 3, iclass 6, count 0 2006.285.18:01:48.26#ibcon#about to read 4, iclass 6, count 0 2006.285.18:01:48.26#ibcon#read 4, iclass 6, count 0 2006.285.18:01:48.26#ibcon#about to read 5, iclass 6, count 0 2006.285.18:01:48.26#ibcon#read 5, iclass 6, count 0 2006.285.18:01:48.26#ibcon#about to read 6, iclass 6, count 0 2006.285.18:01:48.26#ibcon#read 6, iclass 6, count 0 2006.285.18:01:48.26#ibcon#end of sib2, iclass 6, count 0 2006.285.18:01:48.26#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:01:48.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:01:48.26#ibcon#[25=BW32\r\n] 2006.285.18:01:48.26#ibcon#*before write, iclass 6, count 0 2006.285.18:01:48.26#ibcon#enter sib2, iclass 6, count 0 2006.285.18:01:48.26#ibcon#flushed, iclass 6, count 0 2006.285.18:01:48.26#ibcon#about to write, iclass 6, count 0 2006.285.18:01:48.26#ibcon#wrote, iclass 6, count 0 2006.285.18:01:48.26#ibcon#about to read 3, iclass 6, count 0 2006.285.18:01:48.29#ibcon#read 3, iclass 6, count 0 2006.285.18:01:48.29#ibcon#about to read 4, iclass 6, count 0 2006.285.18:01:48.29#ibcon#read 4, iclass 6, count 0 2006.285.18:01:48.29#ibcon#about to read 5, iclass 6, count 0 2006.285.18:01:48.29#ibcon#read 5, iclass 6, count 0 2006.285.18:01:48.29#ibcon#about to read 6, iclass 6, count 0 2006.285.18:01:48.29#ibcon#read 6, iclass 6, count 0 2006.285.18:01:48.29#ibcon#end of sib2, iclass 6, count 0 2006.285.18:01:48.29#ibcon#*after write, iclass 6, count 0 2006.285.18:01:48.29#ibcon#*before return 0, iclass 6, count 0 2006.285.18:01:48.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:01:48.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:01:48.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:01:48.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:01:48.29$vck44/vbbw=wide 2006.285.18:01:48.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.18:01:48.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.18:01:48.29#ibcon#ireg 8 cls_cnt 0 2006.285.18:01:48.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:01:48.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:01:48.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:01:48.36#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:01:48.36#ibcon#first serial, iclass 10, count 0 2006.285.18:01:48.36#ibcon#enter sib2, iclass 10, count 0 2006.285.18:01:48.36#ibcon#flushed, iclass 10, count 0 2006.285.18:01:48.36#ibcon#about to write, iclass 10, count 0 2006.285.18:01:48.36#ibcon#wrote, iclass 10, count 0 2006.285.18:01:48.36#ibcon#about to read 3, iclass 10, count 0 2006.285.18:01:48.38#ibcon#read 3, iclass 10, count 0 2006.285.18:01:48.38#ibcon#about to read 4, iclass 10, count 0 2006.285.18:01:48.38#ibcon#read 4, iclass 10, count 0 2006.285.18:01:48.38#ibcon#about to read 5, iclass 10, count 0 2006.285.18:01:48.38#ibcon#read 5, iclass 10, count 0 2006.285.18:01:48.38#ibcon#about to read 6, iclass 10, count 0 2006.285.18:01:48.38#ibcon#read 6, iclass 10, count 0 2006.285.18:01:48.38#ibcon#end of sib2, iclass 10, count 0 2006.285.18:01:48.38#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:01:48.38#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:01:48.38#ibcon#[27=BW32\r\n] 2006.285.18:01:48.38#ibcon#*before write, iclass 10, count 0 2006.285.18:01:48.38#ibcon#enter sib2, iclass 10, count 0 2006.285.18:01:48.38#ibcon#flushed, iclass 10, count 0 2006.285.18:01:48.38#ibcon#about to write, iclass 10, count 0 2006.285.18:01:48.38#ibcon#wrote, iclass 10, count 0 2006.285.18:01:48.38#ibcon#about to read 3, iclass 10, count 0 2006.285.18:01:48.41#ibcon#read 3, iclass 10, count 0 2006.285.18:01:48.41#ibcon#about to read 4, iclass 10, count 0 2006.285.18:01:48.41#ibcon#read 4, iclass 10, count 0 2006.285.18:01:48.41#ibcon#about to read 5, iclass 10, count 0 2006.285.18:01:48.41#ibcon#read 5, iclass 10, count 0 2006.285.18:01:48.41#ibcon#about to read 6, iclass 10, count 0 2006.285.18:01:48.41#ibcon#read 6, iclass 10, count 0 2006.285.18:01:48.41#ibcon#end of sib2, iclass 10, count 0 2006.285.18:01:48.41#ibcon#*after write, iclass 10, count 0 2006.285.18:01:48.41#ibcon#*before return 0, iclass 10, count 0 2006.285.18:01:48.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:01:48.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:01:48.41#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:01:48.41#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:01:48.41$setupk4/ifdk4 2006.285.18:01:48.41$ifdk4/lo= 2006.285.18:01:48.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.18:01:48.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.18:01:48.41$ifdk4/patch= 2006.285.18:01:48.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.18:01:48.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.18:01:48.41$setupk4/!*+20s 2006.285.18:01:52.64#abcon#<5=/08 0.5 1.0 16.121001014.4\r\n> 2006.285.18:01:52.66#abcon#{5=INTERFACE CLEAR} 2006.285.18:01:52.72#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:02:01.98$setupk4/"tpicd 2006.285.18:02:01.98$setupk4/echo=off 2006.285.18:02:01.98$setupk4/xlog=off 2006.285.18:02:01.98:!2006.285.18:09:20 2006.285.18:02:31.13#trakl#Source acquired 2006.285.18:02:33.13#flagr#flagr/antenna,acquired 2006.285.18:09:20.00:preob 2006.285.18:09:20.13/onsource/TRACKING 2006.285.18:09:20.13:!2006.285.18:09:30 2006.285.18:09:30.00:"tape 2006.285.18:09:30.00:"st=record 2006.285.18:09:30.00:data_valid=on 2006.285.18:09:30.00:midob 2006.285.18:09:30.13/onsource/TRACKING 2006.285.18:09:30.13/wx/15.88,1014.5,100 2006.285.18:09:30.19/cable/+6.5049E-03 2006.285.18:09:31.28/va/01,07,usb,yes,32,34 2006.285.18:09:31.28/va/02,06,usb,yes,32,32 2006.285.18:09:31.28/va/03,07,usb,yes,31,33 2006.285.18:09:31.28/va/04,06,usb,yes,33,34 2006.285.18:09:31.28/va/05,03,usb,yes,32,33 2006.285.18:09:31.28/va/06,04,usb,yes,29,29 2006.285.18:09:31.28/va/07,04,usb,yes,30,30 2006.285.18:09:31.28/va/08,03,usb,yes,30,37 2006.285.18:09:31.51/valo/01,524.99,yes,locked 2006.285.18:09:31.51/valo/02,534.99,yes,locked 2006.285.18:09:31.51/valo/03,564.99,yes,locked 2006.285.18:09:31.51/valo/04,624.99,yes,locked 2006.285.18:09:31.51/valo/05,734.99,yes,locked 2006.285.18:09:31.51/valo/06,814.99,yes,locked 2006.285.18:09:31.51/valo/07,864.99,yes,locked 2006.285.18:09:31.51/valo/08,884.99,yes,locked 2006.285.18:09:32.60/vb/01,04,usb,yes,30,28 2006.285.18:09:32.60/vb/02,05,usb,yes,28,28 2006.285.18:09:32.60/vb/03,04,usb,yes,29,32 2006.285.18:09:32.60/vb/04,05,usb,yes,29,28 2006.285.18:09:32.60/vb/05,04,usb,yes,26,28 2006.285.18:09:32.60/vb/06,03,usb,yes,37,33 2006.285.18:09:32.60/vb/07,04,usb,yes,30,30 2006.285.18:09:32.60/vb/08,04,usb,yes,27,31 2006.285.18:09:32.83/vblo/01,629.99,yes,locked 2006.285.18:09:32.83/vblo/02,634.99,yes,locked 2006.285.18:09:32.83/vblo/03,649.99,yes,locked 2006.285.18:09:32.83/vblo/04,679.99,yes,locked 2006.285.18:09:32.83/vblo/05,709.99,yes,locked 2006.285.18:09:32.83/vblo/06,719.99,yes,locked 2006.285.18:09:32.83/vblo/07,734.99,yes,locked 2006.285.18:09:32.83/vblo/08,744.99,yes,locked 2006.285.18:09:32.98/vabw/8 2006.285.18:09:33.13/vbbw/8 2006.285.18:09:33.22/xfe/off,on,12.0 2006.285.18:09:33.60/ifatt/23,28,28,28 2006.285.18:09:34.07/fmout-gps/S +2.73E-07 2006.285.18:09:34.09:!2006.285.18:11:20 2006.285.18:11:20.01:data_valid=off 2006.285.18:11:20.01:"et 2006.285.18:11:20.01:!+3s 2006.285.18:11:23.02:"tape 2006.285.18:11:23.02:postob 2006.285.18:11:23.11/cable/+6.5047E-03 2006.285.18:11:23.11/wx/15.83,1014.5,100 2006.285.18:11:24.08/fmout-gps/S +2.77E-07 2006.285.18:11:24.08:scan_name=285-1814,jd0610,260 2006.285.18:11:24.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.285.18:11:25.14#flagr#flagr/antenna,new-source 2006.285.18:11:25.14:checkk5 2006.285.18:11:25.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.18:11:25.98/chk_autoobs//k5ts2/ autoobs is running! 2006.285.18:11:26.50/chk_autoobs//k5ts3/ autoobs is running! 2006.285.18:11:26.90/chk_autoobs//k5ts4/ autoobs is running! 2006.285.18:11:27.34/chk_obsdata//k5ts1/T2851809??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.18:11:27.77/chk_obsdata//k5ts2/T2851809??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.18:11:28.12/chk_obsdata//k5ts3/T2851809??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.18:11:28.52/chk_obsdata//k5ts4/T2851809??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.18:11:29.49/k5log//k5ts1_log_newline 2006.285.18:11:30.55/k5log//k5ts2_log_newline 2006.285.18:11:31.28/k5log//k5ts3_log_newline 2006.285.18:11:32.09/k5log//k5ts4_log_newline 2006.285.18:11:32.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.18:11:32.11:setupk4=1 2006.285.18:11:32.11$setupk4/echo=on 2006.285.18:11:32.11$setupk4/pcalon 2006.285.18:11:32.11$pcalon/"no phase cal control is implemented here 2006.285.18:11:32.11$setupk4/"tpicd=stop 2006.285.18:11:32.11$setupk4/"rec=synch_on 2006.285.18:11:32.11$setupk4/"rec_mode=128 2006.285.18:11:32.11$setupk4/!* 2006.285.18:11:32.11$setupk4/recpk4 2006.285.18:11:32.11$recpk4/recpatch= 2006.285.18:11:32.11$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.18:11:32.11$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.18:11:32.11$setupk4/vck44 2006.285.18:11:32.11$vck44/valo=1,524.99 2006.285.18:11:32.11#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.18:11:32.11#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.18:11:32.11#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:32.11#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:11:32.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:11:32.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:11:32.11#ibcon#enter wrdev, iclass 27, count 0 2006.285.18:11:32.11#ibcon#first serial, iclass 27, count 0 2006.285.18:11:32.11#ibcon#enter sib2, iclass 27, count 0 2006.285.18:11:32.11#ibcon#flushed, iclass 27, count 0 2006.285.18:11:32.11#ibcon#about to write, iclass 27, count 0 2006.285.18:11:32.11#ibcon#wrote, iclass 27, count 0 2006.285.18:11:32.11#ibcon#about to read 3, iclass 27, count 0 2006.285.18:11:32.13#ibcon#read 3, iclass 27, count 0 2006.285.18:11:32.13#ibcon#about to read 4, iclass 27, count 0 2006.285.18:11:32.13#ibcon#read 4, iclass 27, count 0 2006.285.18:11:32.13#ibcon#about to read 5, iclass 27, count 0 2006.285.18:11:32.13#ibcon#read 5, iclass 27, count 0 2006.285.18:11:32.13#ibcon#about to read 6, iclass 27, count 0 2006.285.18:11:32.13#ibcon#read 6, iclass 27, count 0 2006.285.18:11:32.13#ibcon#end of sib2, iclass 27, count 0 2006.285.18:11:32.13#ibcon#*mode == 0, iclass 27, count 0 2006.285.18:11:32.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.18:11:32.13#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.18:11:32.13#ibcon#*before write, iclass 27, count 0 2006.285.18:11:32.13#ibcon#enter sib2, iclass 27, count 0 2006.285.18:11:32.13#ibcon#flushed, iclass 27, count 0 2006.285.18:11:32.13#ibcon#about to write, iclass 27, count 0 2006.285.18:11:32.13#ibcon#wrote, iclass 27, count 0 2006.285.18:11:32.13#ibcon#about to read 3, iclass 27, count 0 2006.285.18:11:32.18#ibcon#read 3, iclass 27, count 0 2006.285.18:11:32.18#ibcon#about to read 4, iclass 27, count 0 2006.285.18:11:32.18#ibcon#read 4, iclass 27, count 0 2006.285.18:11:32.18#ibcon#about to read 5, iclass 27, count 0 2006.285.18:11:32.18#ibcon#read 5, iclass 27, count 0 2006.285.18:11:32.18#ibcon#about to read 6, iclass 27, count 0 2006.285.18:11:32.18#ibcon#read 6, iclass 27, count 0 2006.285.18:11:32.18#ibcon#end of sib2, iclass 27, count 0 2006.285.18:11:32.18#ibcon#*after write, iclass 27, count 0 2006.285.18:11:32.18#ibcon#*before return 0, iclass 27, count 0 2006.285.18:11:32.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:11:32.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:11:32.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.18:11:32.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.18:11:32.18$vck44/va=1,7 2006.285.18:11:32.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.18:11:32.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.18:11:32.18#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:32.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:11:32.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:11:32.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:11:32.18#ibcon#enter wrdev, iclass 29, count 2 2006.285.18:11:32.18#ibcon#first serial, iclass 29, count 2 2006.285.18:11:32.18#ibcon#enter sib2, iclass 29, count 2 2006.285.18:11:32.18#ibcon#flushed, iclass 29, count 2 2006.285.18:11:32.18#ibcon#about to write, iclass 29, count 2 2006.285.18:11:32.18#ibcon#wrote, iclass 29, count 2 2006.285.18:11:32.18#ibcon#about to read 3, iclass 29, count 2 2006.285.18:11:32.20#ibcon#read 3, iclass 29, count 2 2006.285.18:11:32.20#ibcon#about to read 4, iclass 29, count 2 2006.285.18:11:32.20#ibcon#read 4, iclass 29, count 2 2006.285.18:11:32.20#ibcon#about to read 5, iclass 29, count 2 2006.285.18:11:32.20#ibcon#read 5, iclass 29, count 2 2006.285.18:11:32.20#ibcon#about to read 6, iclass 29, count 2 2006.285.18:11:32.20#ibcon#read 6, iclass 29, count 2 2006.285.18:11:32.20#ibcon#end of sib2, iclass 29, count 2 2006.285.18:11:32.20#ibcon#*mode == 0, iclass 29, count 2 2006.285.18:11:32.20#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.18:11:32.20#ibcon#[25=AT01-07\r\n] 2006.285.18:11:32.20#ibcon#*before write, iclass 29, count 2 2006.285.18:11:32.20#ibcon#enter sib2, iclass 29, count 2 2006.285.18:11:32.20#ibcon#flushed, iclass 29, count 2 2006.285.18:11:32.20#ibcon#about to write, iclass 29, count 2 2006.285.18:11:32.20#ibcon#wrote, iclass 29, count 2 2006.285.18:11:32.20#ibcon#about to read 3, iclass 29, count 2 2006.285.18:11:32.23#ibcon#read 3, iclass 29, count 2 2006.285.18:11:32.23#ibcon#about to read 4, iclass 29, count 2 2006.285.18:11:32.23#ibcon#read 4, iclass 29, count 2 2006.285.18:11:32.23#ibcon#about to read 5, iclass 29, count 2 2006.285.18:11:32.23#ibcon#read 5, iclass 29, count 2 2006.285.18:11:32.23#ibcon#about to read 6, iclass 29, count 2 2006.285.18:11:32.23#ibcon#read 6, iclass 29, count 2 2006.285.18:11:32.23#ibcon#end of sib2, iclass 29, count 2 2006.285.18:11:32.23#ibcon#*after write, iclass 29, count 2 2006.285.18:11:32.23#ibcon#*before return 0, iclass 29, count 2 2006.285.18:11:32.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:11:32.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:11:32.23#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.18:11:32.23#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:32.23#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:11:32.35#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:11:32.35#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:11:32.35#ibcon#enter wrdev, iclass 29, count 0 2006.285.18:11:32.35#ibcon#first serial, iclass 29, count 0 2006.285.18:11:32.35#ibcon#enter sib2, iclass 29, count 0 2006.285.18:11:32.35#ibcon#flushed, iclass 29, count 0 2006.285.18:11:32.35#ibcon#about to write, iclass 29, count 0 2006.285.18:11:32.35#ibcon#wrote, iclass 29, count 0 2006.285.18:11:32.35#ibcon#about to read 3, iclass 29, count 0 2006.285.18:11:32.37#ibcon#read 3, iclass 29, count 0 2006.285.18:11:32.37#ibcon#about to read 4, iclass 29, count 0 2006.285.18:11:32.37#ibcon#read 4, iclass 29, count 0 2006.285.18:11:32.37#ibcon#about to read 5, iclass 29, count 0 2006.285.18:11:32.37#ibcon#read 5, iclass 29, count 0 2006.285.18:11:32.37#ibcon#about to read 6, iclass 29, count 0 2006.285.18:11:32.37#ibcon#read 6, iclass 29, count 0 2006.285.18:11:32.37#ibcon#end of sib2, iclass 29, count 0 2006.285.18:11:32.37#ibcon#*mode == 0, iclass 29, count 0 2006.285.18:11:32.37#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.18:11:32.37#ibcon#[25=USB\r\n] 2006.285.18:11:32.37#ibcon#*before write, iclass 29, count 0 2006.285.18:11:32.37#ibcon#enter sib2, iclass 29, count 0 2006.285.18:11:32.37#ibcon#flushed, iclass 29, count 0 2006.285.18:11:32.37#ibcon#about to write, iclass 29, count 0 2006.285.18:11:32.37#ibcon#wrote, iclass 29, count 0 2006.285.18:11:32.37#ibcon#about to read 3, iclass 29, count 0 2006.285.18:11:32.40#ibcon#read 3, iclass 29, count 0 2006.285.18:11:32.40#ibcon#about to read 4, iclass 29, count 0 2006.285.18:11:32.40#ibcon#read 4, iclass 29, count 0 2006.285.18:11:32.40#ibcon#about to read 5, iclass 29, count 0 2006.285.18:11:32.40#ibcon#read 5, iclass 29, count 0 2006.285.18:11:32.40#ibcon#about to read 6, iclass 29, count 0 2006.285.18:11:32.40#ibcon#read 6, iclass 29, count 0 2006.285.18:11:32.40#ibcon#end of sib2, iclass 29, count 0 2006.285.18:11:32.40#ibcon#*after write, iclass 29, count 0 2006.285.18:11:32.40#ibcon#*before return 0, iclass 29, count 0 2006.285.18:11:32.40#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:11:32.40#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:11:32.40#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.18:11:32.40#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.18:11:32.40$vck44/valo=2,534.99 2006.285.18:11:32.40#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.18:11:32.40#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.18:11:32.40#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:32.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:11:32.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:11:32.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:11:32.40#ibcon#enter wrdev, iclass 31, count 0 2006.285.18:11:32.40#ibcon#first serial, iclass 31, count 0 2006.285.18:11:32.40#ibcon#enter sib2, iclass 31, count 0 2006.285.18:11:32.40#ibcon#flushed, iclass 31, count 0 2006.285.18:11:32.40#ibcon#about to write, iclass 31, count 0 2006.285.18:11:32.40#ibcon#wrote, iclass 31, count 0 2006.285.18:11:32.40#ibcon#about to read 3, iclass 31, count 0 2006.285.18:11:32.42#ibcon#read 3, iclass 31, count 0 2006.285.18:11:32.42#ibcon#about to read 4, iclass 31, count 0 2006.285.18:11:32.42#ibcon#read 4, iclass 31, count 0 2006.285.18:11:32.42#ibcon#about to read 5, iclass 31, count 0 2006.285.18:11:32.42#ibcon#read 5, iclass 31, count 0 2006.285.18:11:32.42#ibcon#about to read 6, iclass 31, count 0 2006.285.18:11:32.42#ibcon#read 6, iclass 31, count 0 2006.285.18:11:32.42#ibcon#end of sib2, iclass 31, count 0 2006.285.18:11:32.42#ibcon#*mode == 0, iclass 31, count 0 2006.285.18:11:32.42#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.18:11:32.42#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.18:11:32.42#ibcon#*before write, iclass 31, count 0 2006.285.18:11:32.42#ibcon#enter sib2, iclass 31, count 0 2006.285.18:11:32.42#ibcon#flushed, iclass 31, count 0 2006.285.18:11:32.42#ibcon#about to write, iclass 31, count 0 2006.285.18:11:32.42#ibcon#wrote, iclass 31, count 0 2006.285.18:11:32.42#ibcon#about to read 3, iclass 31, count 0 2006.285.18:11:32.46#ibcon#read 3, iclass 31, count 0 2006.285.18:11:32.46#ibcon#about to read 4, iclass 31, count 0 2006.285.18:11:32.46#ibcon#read 4, iclass 31, count 0 2006.285.18:11:32.46#ibcon#about to read 5, iclass 31, count 0 2006.285.18:11:32.46#ibcon#read 5, iclass 31, count 0 2006.285.18:11:32.46#ibcon#about to read 6, iclass 31, count 0 2006.285.18:11:32.46#ibcon#read 6, iclass 31, count 0 2006.285.18:11:32.46#ibcon#end of sib2, iclass 31, count 0 2006.285.18:11:32.46#ibcon#*after write, iclass 31, count 0 2006.285.18:11:32.46#ibcon#*before return 0, iclass 31, count 0 2006.285.18:11:32.46#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:11:32.46#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:11:32.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.18:11:32.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.18:11:32.46$vck44/va=2,6 2006.285.18:11:32.46#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.18:11:32.46#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.18:11:32.46#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:32.46#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:11:32.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:11:32.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:11:32.52#ibcon#enter wrdev, iclass 33, count 2 2006.285.18:11:32.52#ibcon#first serial, iclass 33, count 2 2006.285.18:11:32.52#ibcon#enter sib2, iclass 33, count 2 2006.285.18:11:32.52#ibcon#flushed, iclass 33, count 2 2006.285.18:11:32.52#ibcon#about to write, iclass 33, count 2 2006.285.18:11:32.52#ibcon#wrote, iclass 33, count 2 2006.285.18:11:32.52#ibcon#about to read 3, iclass 33, count 2 2006.285.18:11:32.54#ibcon#read 3, iclass 33, count 2 2006.285.18:11:32.54#ibcon#about to read 4, iclass 33, count 2 2006.285.18:11:32.54#ibcon#read 4, iclass 33, count 2 2006.285.18:11:32.54#ibcon#about to read 5, iclass 33, count 2 2006.285.18:11:32.54#ibcon#read 5, iclass 33, count 2 2006.285.18:11:32.54#ibcon#about to read 6, iclass 33, count 2 2006.285.18:11:32.54#ibcon#read 6, iclass 33, count 2 2006.285.18:11:32.54#ibcon#end of sib2, iclass 33, count 2 2006.285.18:11:32.54#ibcon#*mode == 0, iclass 33, count 2 2006.285.18:11:32.54#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.18:11:32.54#ibcon#[25=AT02-06\r\n] 2006.285.18:11:32.54#ibcon#*before write, iclass 33, count 2 2006.285.18:11:32.54#ibcon#enter sib2, iclass 33, count 2 2006.285.18:11:32.54#ibcon#flushed, iclass 33, count 2 2006.285.18:11:32.54#ibcon#about to write, iclass 33, count 2 2006.285.18:11:32.54#ibcon#wrote, iclass 33, count 2 2006.285.18:11:32.54#ibcon#about to read 3, iclass 33, count 2 2006.285.18:11:32.54#abcon#<5=/13 0.7 1.5 15.831001014.5\r\n> 2006.285.18:11:32.56#abcon#{5=INTERFACE CLEAR} 2006.285.18:11:32.57#ibcon#read 3, iclass 33, count 2 2006.285.18:11:32.57#ibcon#about to read 4, iclass 33, count 2 2006.285.18:11:32.57#ibcon#read 4, iclass 33, count 2 2006.285.18:11:32.57#ibcon#about to read 5, iclass 33, count 2 2006.285.18:11:32.57#ibcon#read 5, iclass 33, count 2 2006.285.18:11:32.57#ibcon#about to read 6, iclass 33, count 2 2006.285.18:11:32.57#ibcon#read 6, iclass 33, count 2 2006.285.18:11:32.57#ibcon#end of sib2, iclass 33, count 2 2006.285.18:11:32.57#ibcon#*after write, iclass 33, count 2 2006.285.18:11:32.57#ibcon#*before return 0, iclass 33, count 2 2006.285.18:11:32.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:11:32.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:11:32.57#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.18:11:32.57#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:32.57#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:11:32.69#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:11:33.13#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:11:33.13#ibcon#enter wrdev, iclass 33, count 0 2006.285.18:11:33.13#ibcon#first serial, iclass 33, count 0 2006.285.18:11:33.13#ibcon#enter sib2, iclass 33, count 0 2006.285.18:11:33.13#ibcon#flushed, iclass 33, count 0 2006.285.18:11:33.13#ibcon#about to write, iclass 33, count 0 2006.285.18:11:33.13#ibcon#wrote, iclass 33, count 0 2006.285.18:11:33.13#ibcon#about to read 3, iclass 33, count 0 2006.285.18:11:33.14#ibcon#read 3, iclass 33, count 0 2006.285.18:11:33.14#ibcon#about to read 4, iclass 33, count 0 2006.285.18:11:33.14#ibcon#read 4, iclass 33, count 0 2006.285.18:11:33.14#ibcon#about to read 5, iclass 33, count 0 2006.285.18:11:33.14#ibcon#read 5, iclass 33, count 0 2006.285.18:11:33.14#ibcon#about to read 6, iclass 33, count 0 2006.285.18:11:33.14#ibcon#read 6, iclass 33, count 0 2006.285.18:11:33.14#ibcon#end of sib2, iclass 33, count 0 2006.285.18:11:33.14#ibcon#*mode == 0, iclass 33, count 0 2006.285.18:11:33.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.18:11:33.14#ibcon#[25=USB\r\n] 2006.285.18:11:33.14#ibcon#*before write, iclass 33, count 0 2006.285.18:11:33.14#ibcon#enter sib2, iclass 33, count 0 2006.285.18:11:33.14#ibcon#flushed, iclass 33, count 0 2006.285.18:11:33.14#ibcon#about to write, iclass 33, count 0 2006.285.18:11:33.14#ibcon#wrote, iclass 33, count 0 2006.285.18:11:33.14#ibcon#about to read 3, iclass 33, count 0 2006.285.18:11:33.14#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:11:33.17#ibcon#read 3, iclass 33, count 0 2006.285.18:11:33.17#ibcon#about to read 4, iclass 33, count 0 2006.285.18:11:33.17#ibcon#read 4, iclass 33, count 0 2006.285.18:11:33.17#ibcon#about to read 5, iclass 33, count 0 2006.285.18:11:33.17#ibcon#read 5, iclass 33, count 0 2006.285.18:11:33.17#ibcon#about to read 6, iclass 33, count 0 2006.285.18:11:33.17#ibcon#read 6, iclass 33, count 0 2006.285.18:11:33.17#ibcon#end of sib2, iclass 33, count 0 2006.285.18:11:33.17#ibcon#*after write, iclass 33, count 0 2006.285.18:11:33.17#ibcon#*before return 0, iclass 33, count 0 2006.285.18:11:33.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:11:33.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:11:33.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.18:11:33.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.18:11:33.17$vck44/valo=3,564.99 2006.285.18:11:33.17#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.18:11:33.17#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.18:11:33.17#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:33.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:11:33.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:11:33.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:11:33.17#ibcon#enter wrdev, iclass 39, count 0 2006.285.18:11:33.17#ibcon#first serial, iclass 39, count 0 2006.285.18:11:33.17#ibcon#enter sib2, iclass 39, count 0 2006.285.18:11:33.17#ibcon#flushed, iclass 39, count 0 2006.285.18:11:33.17#ibcon#about to write, iclass 39, count 0 2006.285.18:11:33.17#ibcon#wrote, iclass 39, count 0 2006.285.18:11:33.17#ibcon#about to read 3, iclass 39, count 0 2006.285.18:11:33.19#ibcon#read 3, iclass 39, count 0 2006.285.18:11:33.19#ibcon#about to read 4, iclass 39, count 0 2006.285.18:11:33.19#ibcon#read 4, iclass 39, count 0 2006.285.18:11:33.19#ibcon#about to read 5, iclass 39, count 0 2006.285.18:11:33.19#ibcon#read 5, iclass 39, count 0 2006.285.18:11:33.19#ibcon#about to read 6, iclass 39, count 0 2006.285.18:11:33.19#ibcon#read 6, iclass 39, count 0 2006.285.18:11:33.19#ibcon#end of sib2, iclass 39, count 0 2006.285.18:11:33.19#ibcon#*mode == 0, iclass 39, count 0 2006.285.18:11:33.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.18:11:33.19#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.18:11:33.19#ibcon#*before write, iclass 39, count 0 2006.285.18:11:33.19#ibcon#enter sib2, iclass 39, count 0 2006.285.18:11:33.19#ibcon#flushed, iclass 39, count 0 2006.285.18:11:33.19#ibcon#about to write, iclass 39, count 0 2006.285.18:11:33.19#ibcon#wrote, iclass 39, count 0 2006.285.18:11:33.19#ibcon#about to read 3, iclass 39, count 0 2006.285.18:11:33.23#ibcon#read 3, iclass 39, count 0 2006.285.18:11:33.23#ibcon#about to read 4, iclass 39, count 0 2006.285.18:11:33.23#ibcon#read 4, iclass 39, count 0 2006.285.18:11:33.23#ibcon#about to read 5, iclass 39, count 0 2006.285.18:11:33.23#ibcon#read 5, iclass 39, count 0 2006.285.18:11:33.23#ibcon#about to read 6, iclass 39, count 0 2006.285.18:11:33.23#ibcon#read 6, iclass 39, count 0 2006.285.18:11:33.23#ibcon#end of sib2, iclass 39, count 0 2006.285.18:11:33.23#ibcon#*after write, iclass 39, count 0 2006.285.18:11:33.23#ibcon#*before return 0, iclass 39, count 0 2006.285.18:11:33.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:11:33.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:11:33.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.18:11:33.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.18:11:33.23$vck44/va=3,7 2006.285.18:11:33.23#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.18:11:33.23#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.18:11:33.23#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:33.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:11:33.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:11:33.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:11:33.29#ibcon#enter wrdev, iclass 3, count 2 2006.285.18:11:33.29#ibcon#first serial, iclass 3, count 2 2006.285.18:11:33.29#ibcon#enter sib2, iclass 3, count 2 2006.285.18:11:33.29#ibcon#flushed, iclass 3, count 2 2006.285.18:11:33.29#ibcon#about to write, iclass 3, count 2 2006.285.18:11:33.29#ibcon#wrote, iclass 3, count 2 2006.285.18:11:33.29#ibcon#about to read 3, iclass 3, count 2 2006.285.18:11:33.31#ibcon#read 3, iclass 3, count 2 2006.285.18:11:33.31#ibcon#about to read 4, iclass 3, count 2 2006.285.18:11:33.31#ibcon#read 4, iclass 3, count 2 2006.285.18:11:33.31#ibcon#about to read 5, iclass 3, count 2 2006.285.18:11:33.31#ibcon#read 5, iclass 3, count 2 2006.285.18:11:33.31#ibcon#about to read 6, iclass 3, count 2 2006.285.18:11:33.31#ibcon#read 6, iclass 3, count 2 2006.285.18:11:33.31#ibcon#end of sib2, iclass 3, count 2 2006.285.18:11:33.31#ibcon#*mode == 0, iclass 3, count 2 2006.285.18:11:33.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.18:11:33.31#ibcon#[25=AT03-07\r\n] 2006.285.18:11:33.31#ibcon#*before write, iclass 3, count 2 2006.285.18:11:33.31#ibcon#enter sib2, iclass 3, count 2 2006.285.18:11:33.31#ibcon#flushed, iclass 3, count 2 2006.285.18:11:33.31#ibcon#about to write, iclass 3, count 2 2006.285.18:11:33.31#ibcon#wrote, iclass 3, count 2 2006.285.18:11:33.31#ibcon#about to read 3, iclass 3, count 2 2006.285.18:11:33.34#ibcon#read 3, iclass 3, count 2 2006.285.18:11:33.34#ibcon#about to read 4, iclass 3, count 2 2006.285.18:11:33.34#ibcon#read 4, iclass 3, count 2 2006.285.18:11:33.34#ibcon#about to read 5, iclass 3, count 2 2006.285.18:11:33.34#ibcon#read 5, iclass 3, count 2 2006.285.18:11:33.34#ibcon#about to read 6, iclass 3, count 2 2006.285.18:11:33.34#ibcon#read 6, iclass 3, count 2 2006.285.18:11:33.34#ibcon#end of sib2, iclass 3, count 2 2006.285.18:11:33.34#ibcon#*after write, iclass 3, count 2 2006.285.18:11:33.34#ibcon#*before return 0, iclass 3, count 2 2006.285.18:11:33.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:11:33.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:11:33.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.18:11:33.34#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:33.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:11:33.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:11:33.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:11:33.46#ibcon#enter wrdev, iclass 3, count 0 2006.285.18:11:33.46#ibcon#first serial, iclass 3, count 0 2006.285.18:11:33.46#ibcon#enter sib2, iclass 3, count 0 2006.285.18:11:33.46#ibcon#flushed, iclass 3, count 0 2006.285.18:11:33.46#ibcon#about to write, iclass 3, count 0 2006.285.18:11:33.46#ibcon#wrote, iclass 3, count 0 2006.285.18:11:33.46#ibcon#about to read 3, iclass 3, count 0 2006.285.18:11:33.48#ibcon#read 3, iclass 3, count 0 2006.285.18:11:33.48#ibcon#about to read 4, iclass 3, count 0 2006.285.18:11:33.48#ibcon#read 4, iclass 3, count 0 2006.285.18:11:33.48#ibcon#about to read 5, iclass 3, count 0 2006.285.18:11:33.48#ibcon#read 5, iclass 3, count 0 2006.285.18:11:33.48#ibcon#about to read 6, iclass 3, count 0 2006.285.18:11:33.48#ibcon#read 6, iclass 3, count 0 2006.285.18:11:33.48#ibcon#end of sib2, iclass 3, count 0 2006.285.18:11:33.48#ibcon#*mode == 0, iclass 3, count 0 2006.285.18:11:33.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.18:11:33.48#ibcon#[25=USB\r\n] 2006.285.18:11:33.48#ibcon#*before write, iclass 3, count 0 2006.285.18:11:33.55#ibcon#enter sib2, iclass 3, count 0 2006.285.18:11:33.55#ibcon#flushed, iclass 3, count 0 2006.285.18:11:33.55#ibcon#about to write, iclass 3, count 0 2006.285.18:11:33.55#ibcon#wrote, iclass 3, count 0 2006.285.18:11:33.55#ibcon#about to read 3, iclass 3, count 0 2006.285.18:11:33.58#ibcon#read 3, iclass 3, count 0 2006.285.18:11:33.58#ibcon#about to read 4, iclass 3, count 0 2006.285.18:11:33.58#ibcon#read 4, iclass 3, count 0 2006.285.18:11:33.58#ibcon#about to read 5, iclass 3, count 0 2006.285.18:11:33.58#ibcon#read 5, iclass 3, count 0 2006.285.18:11:33.58#ibcon#about to read 6, iclass 3, count 0 2006.285.18:11:33.58#ibcon#read 6, iclass 3, count 0 2006.285.18:11:33.58#ibcon#end of sib2, iclass 3, count 0 2006.285.18:11:33.58#ibcon#*after write, iclass 3, count 0 2006.285.18:11:33.58#ibcon#*before return 0, iclass 3, count 0 2006.285.18:11:33.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:11:33.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:11:33.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.18:11:33.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.18:11:33.58$vck44/valo=4,624.99 2006.285.18:11:33.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.18:11:33.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.18:11:33.58#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:33.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:11:33.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:11:33.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:11:33.58#ibcon#enter wrdev, iclass 5, count 0 2006.285.18:11:33.58#ibcon#first serial, iclass 5, count 0 2006.285.18:11:33.58#ibcon#enter sib2, iclass 5, count 0 2006.285.18:11:33.58#ibcon#flushed, iclass 5, count 0 2006.285.18:11:33.58#ibcon#about to write, iclass 5, count 0 2006.285.18:11:33.58#ibcon#wrote, iclass 5, count 0 2006.285.18:11:33.58#ibcon#about to read 3, iclass 5, count 0 2006.285.18:11:33.60#ibcon#read 3, iclass 5, count 0 2006.285.18:11:33.60#ibcon#about to read 4, iclass 5, count 0 2006.285.18:11:33.60#ibcon#read 4, iclass 5, count 0 2006.285.18:11:33.60#ibcon#about to read 5, iclass 5, count 0 2006.285.18:11:33.60#ibcon#read 5, iclass 5, count 0 2006.285.18:11:33.60#ibcon#about to read 6, iclass 5, count 0 2006.285.18:11:33.60#ibcon#read 6, iclass 5, count 0 2006.285.18:11:33.60#ibcon#end of sib2, iclass 5, count 0 2006.285.18:11:33.60#ibcon#*mode == 0, iclass 5, count 0 2006.285.18:11:33.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.18:11:33.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.18:11:33.60#ibcon#*before write, iclass 5, count 0 2006.285.18:11:33.60#ibcon#enter sib2, iclass 5, count 0 2006.285.18:11:33.60#ibcon#flushed, iclass 5, count 0 2006.285.18:11:33.60#ibcon#about to write, iclass 5, count 0 2006.285.18:11:33.60#ibcon#wrote, iclass 5, count 0 2006.285.18:11:33.60#ibcon#about to read 3, iclass 5, count 0 2006.285.18:11:33.64#ibcon#read 3, iclass 5, count 0 2006.285.18:11:33.64#ibcon#about to read 4, iclass 5, count 0 2006.285.18:11:33.64#ibcon#read 4, iclass 5, count 0 2006.285.18:11:33.64#ibcon#about to read 5, iclass 5, count 0 2006.285.18:11:33.64#ibcon#read 5, iclass 5, count 0 2006.285.18:11:33.64#ibcon#about to read 6, iclass 5, count 0 2006.285.18:11:33.64#ibcon#read 6, iclass 5, count 0 2006.285.18:11:33.64#ibcon#end of sib2, iclass 5, count 0 2006.285.18:11:33.64#ibcon#*after write, iclass 5, count 0 2006.285.18:11:33.64#ibcon#*before return 0, iclass 5, count 0 2006.285.18:11:33.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:11:33.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:11:33.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.18:11:33.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.18:11:33.64$vck44/va=4,6 2006.285.18:11:33.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.18:11:33.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.18:11:33.64#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:33.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:11:33.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:11:33.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:11:33.70#ibcon#enter wrdev, iclass 7, count 2 2006.285.18:11:33.70#ibcon#first serial, iclass 7, count 2 2006.285.18:11:33.70#ibcon#enter sib2, iclass 7, count 2 2006.285.18:11:33.70#ibcon#flushed, iclass 7, count 2 2006.285.18:11:33.70#ibcon#about to write, iclass 7, count 2 2006.285.18:11:33.70#ibcon#wrote, iclass 7, count 2 2006.285.18:11:33.70#ibcon#about to read 3, iclass 7, count 2 2006.285.18:11:33.72#ibcon#read 3, iclass 7, count 2 2006.285.18:11:33.72#ibcon#about to read 4, iclass 7, count 2 2006.285.18:11:33.72#ibcon#read 4, iclass 7, count 2 2006.285.18:11:33.72#ibcon#about to read 5, iclass 7, count 2 2006.285.18:11:33.72#ibcon#read 5, iclass 7, count 2 2006.285.18:11:33.72#ibcon#about to read 6, iclass 7, count 2 2006.285.18:11:33.72#ibcon#read 6, iclass 7, count 2 2006.285.18:11:33.72#ibcon#end of sib2, iclass 7, count 2 2006.285.18:11:33.72#ibcon#*mode == 0, iclass 7, count 2 2006.285.18:11:33.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.18:11:33.72#ibcon#[25=AT04-06\r\n] 2006.285.18:11:33.72#ibcon#*before write, iclass 7, count 2 2006.285.18:11:33.72#ibcon#enter sib2, iclass 7, count 2 2006.285.18:11:33.72#ibcon#flushed, iclass 7, count 2 2006.285.18:11:33.72#ibcon#about to write, iclass 7, count 2 2006.285.18:11:33.72#ibcon#wrote, iclass 7, count 2 2006.285.18:11:33.72#ibcon#about to read 3, iclass 7, count 2 2006.285.18:11:33.75#ibcon#read 3, iclass 7, count 2 2006.285.18:11:33.75#ibcon#about to read 4, iclass 7, count 2 2006.285.18:11:33.75#ibcon#read 4, iclass 7, count 2 2006.285.18:11:33.75#ibcon#about to read 5, iclass 7, count 2 2006.285.18:11:33.75#ibcon#read 5, iclass 7, count 2 2006.285.18:11:33.75#ibcon#about to read 6, iclass 7, count 2 2006.285.18:11:33.75#ibcon#read 6, iclass 7, count 2 2006.285.18:11:33.75#ibcon#end of sib2, iclass 7, count 2 2006.285.18:11:33.75#ibcon#*after write, iclass 7, count 2 2006.285.18:11:33.75#ibcon#*before return 0, iclass 7, count 2 2006.285.18:11:33.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:11:33.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:11:33.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.18:11:33.75#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:33.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:11:33.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:11:33.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:11:33.93#ibcon#enter wrdev, iclass 7, count 0 2006.285.18:11:33.93#ibcon#first serial, iclass 7, count 0 2006.285.18:11:33.93#ibcon#enter sib2, iclass 7, count 0 2006.285.18:11:33.93#ibcon#flushed, iclass 7, count 0 2006.285.18:11:33.93#ibcon#about to write, iclass 7, count 0 2006.285.18:11:33.93#ibcon#wrote, iclass 7, count 0 2006.285.18:11:33.93#ibcon#about to read 3, iclass 7, count 0 2006.285.18:11:33.95#ibcon#read 3, iclass 7, count 0 2006.285.18:11:33.95#ibcon#about to read 4, iclass 7, count 0 2006.285.18:11:33.95#ibcon#read 4, iclass 7, count 0 2006.285.18:11:33.95#ibcon#about to read 5, iclass 7, count 0 2006.285.18:11:33.95#ibcon#read 5, iclass 7, count 0 2006.285.18:11:33.95#ibcon#about to read 6, iclass 7, count 0 2006.285.18:11:33.95#ibcon#read 6, iclass 7, count 0 2006.285.18:11:33.95#ibcon#end of sib2, iclass 7, count 0 2006.285.18:11:33.95#ibcon#*mode == 0, iclass 7, count 0 2006.285.18:11:33.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.18:11:33.95#ibcon#[25=USB\r\n] 2006.285.18:11:33.95#ibcon#*before write, iclass 7, count 0 2006.285.18:11:33.95#ibcon#enter sib2, iclass 7, count 0 2006.285.18:11:33.95#ibcon#flushed, iclass 7, count 0 2006.285.18:11:33.95#ibcon#about to write, iclass 7, count 0 2006.285.18:11:33.95#ibcon#wrote, iclass 7, count 0 2006.285.18:11:33.95#ibcon#about to read 3, iclass 7, count 0 2006.285.18:11:33.98#ibcon#read 3, iclass 7, count 0 2006.285.18:11:33.98#ibcon#about to read 4, iclass 7, count 0 2006.285.18:11:33.98#ibcon#read 4, iclass 7, count 0 2006.285.18:11:33.98#ibcon#about to read 5, iclass 7, count 0 2006.285.18:11:33.98#ibcon#read 5, iclass 7, count 0 2006.285.18:11:33.98#ibcon#about to read 6, iclass 7, count 0 2006.285.18:11:33.98#ibcon#read 6, iclass 7, count 0 2006.285.18:11:33.98#ibcon#end of sib2, iclass 7, count 0 2006.285.18:11:33.98#ibcon#*after write, iclass 7, count 0 2006.285.18:11:33.98#ibcon#*before return 0, iclass 7, count 0 2006.285.18:11:33.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:11:33.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:11:33.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.18:11:33.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.18:11:33.98$vck44/valo=5,734.99 2006.285.18:11:33.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.18:11:33.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.18:11:33.98#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:33.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:11:33.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:11:33.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:11:33.98#ibcon#enter wrdev, iclass 11, count 0 2006.285.18:11:33.98#ibcon#first serial, iclass 11, count 0 2006.285.18:11:33.98#ibcon#enter sib2, iclass 11, count 0 2006.285.18:11:33.98#ibcon#flushed, iclass 11, count 0 2006.285.18:11:33.98#ibcon#about to write, iclass 11, count 0 2006.285.18:11:33.98#ibcon#wrote, iclass 11, count 0 2006.285.18:11:33.98#ibcon#about to read 3, iclass 11, count 0 2006.285.18:11:34.00#ibcon#read 3, iclass 11, count 0 2006.285.18:11:34.00#ibcon#about to read 4, iclass 11, count 0 2006.285.18:11:34.00#ibcon#read 4, iclass 11, count 0 2006.285.18:11:34.00#ibcon#about to read 5, iclass 11, count 0 2006.285.18:11:34.00#ibcon#read 5, iclass 11, count 0 2006.285.18:11:34.00#ibcon#about to read 6, iclass 11, count 0 2006.285.18:11:34.00#ibcon#read 6, iclass 11, count 0 2006.285.18:11:34.00#ibcon#end of sib2, iclass 11, count 0 2006.285.18:11:34.00#ibcon#*mode == 0, iclass 11, count 0 2006.285.18:11:34.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.18:11:34.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.18:11:34.00#ibcon#*before write, iclass 11, count 0 2006.285.18:11:34.00#ibcon#enter sib2, iclass 11, count 0 2006.285.18:11:34.00#ibcon#flushed, iclass 11, count 0 2006.285.18:11:34.00#ibcon#about to write, iclass 11, count 0 2006.285.18:11:34.00#ibcon#wrote, iclass 11, count 0 2006.285.18:11:34.00#ibcon#about to read 3, iclass 11, count 0 2006.285.18:11:34.04#ibcon#read 3, iclass 11, count 0 2006.285.18:11:34.04#ibcon#about to read 4, iclass 11, count 0 2006.285.18:11:34.04#ibcon#read 4, iclass 11, count 0 2006.285.18:11:34.04#ibcon#about to read 5, iclass 11, count 0 2006.285.18:11:34.04#ibcon#read 5, iclass 11, count 0 2006.285.18:11:34.04#ibcon#about to read 6, iclass 11, count 0 2006.285.18:11:34.04#ibcon#read 6, iclass 11, count 0 2006.285.18:11:34.04#ibcon#end of sib2, iclass 11, count 0 2006.285.18:11:34.04#ibcon#*after write, iclass 11, count 0 2006.285.18:11:34.04#ibcon#*before return 0, iclass 11, count 0 2006.285.18:11:34.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:11:34.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:11:34.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.18:11:34.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.18:11:34.04$vck44/va=5,3 2006.285.18:11:34.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.18:11:34.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.18:11:34.04#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:34.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:11:34.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:11:34.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:11:34.10#ibcon#enter wrdev, iclass 13, count 2 2006.285.18:11:34.10#ibcon#first serial, iclass 13, count 2 2006.285.18:11:34.10#ibcon#enter sib2, iclass 13, count 2 2006.285.18:11:34.10#ibcon#flushed, iclass 13, count 2 2006.285.18:11:34.10#ibcon#about to write, iclass 13, count 2 2006.285.18:11:34.10#ibcon#wrote, iclass 13, count 2 2006.285.18:11:34.10#ibcon#about to read 3, iclass 13, count 2 2006.285.18:11:34.12#ibcon#read 3, iclass 13, count 2 2006.285.18:11:34.12#ibcon#about to read 4, iclass 13, count 2 2006.285.18:11:34.12#ibcon#read 4, iclass 13, count 2 2006.285.18:11:34.12#ibcon#about to read 5, iclass 13, count 2 2006.285.18:11:34.12#ibcon#read 5, iclass 13, count 2 2006.285.18:11:34.12#ibcon#about to read 6, iclass 13, count 2 2006.285.18:11:34.12#ibcon#read 6, iclass 13, count 2 2006.285.18:11:34.12#ibcon#end of sib2, iclass 13, count 2 2006.285.18:11:34.12#ibcon#*mode == 0, iclass 13, count 2 2006.285.18:11:34.12#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.18:11:34.12#ibcon#[25=AT05-03\r\n] 2006.285.18:11:34.12#ibcon#*before write, iclass 13, count 2 2006.285.18:11:34.12#ibcon#enter sib2, iclass 13, count 2 2006.285.18:11:34.12#ibcon#flushed, iclass 13, count 2 2006.285.18:11:34.12#ibcon#about to write, iclass 13, count 2 2006.285.18:11:34.12#ibcon#wrote, iclass 13, count 2 2006.285.18:11:34.12#ibcon#about to read 3, iclass 13, count 2 2006.285.18:11:34.15#ibcon#read 3, iclass 13, count 2 2006.285.18:11:34.15#ibcon#about to read 4, iclass 13, count 2 2006.285.18:11:34.15#ibcon#read 4, iclass 13, count 2 2006.285.18:11:34.15#ibcon#about to read 5, iclass 13, count 2 2006.285.18:11:34.15#ibcon#read 5, iclass 13, count 2 2006.285.18:11:34.15#ibcon#about to read 6, iclass 13, count 2 2006.285.18:11:34.15#ibcon#read 6, iclass 13, count 2 2006.285.18:11:34.15#ibcon#end of sib2, iclass 13, count 2 2006.285.18:11:34.15#ibcon#*after write, iclass 13, count 2 2006.285.18:11:34.15#ibcon#*before return 0, iclass 13, count 2 2006.285.18:11:34.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:11:34.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:11:34.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.18:11:34.15#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:34.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:11:34.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:11:34.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:11:34.27#ibcon#enter wrdev, iclass 13, count 0 2006.285.18:11:34.27#ibcon#first serial, iclass 13, count 0 2006.285.18:11:34.27#ibcon#enter sib2, iclass 13, count 0 2006.285.18:11:34.27#ibcon#flushed, iclass 13, count 0 2006.285.18:11:34.27#ibcon#about to write, iclass 13, count 0 2006.285.18:11:34.27#ibcon#wrote, iclass 13, count 0 2006.285.18:11:34.27#ibcon#about to read 3, iclass 13, count 0 2006.285.18:11:34.29#ibcon#read 3, iclass 13, count 0 2006.285.18:11:34.29#ibcon#about to read 4, iclass 13, count 0 2006.285.18:11:34.29#ibcon#read 4, iclass 13, count 0 2006.285.18:11:34.29#ibcon#about to read 5, iclass 13, count 0 2006.285.18:11:34.29#ibcon#read 5, iclass 13, count 0 2006.285.18:11:34.29#ibcon#about to read 6, iclass 13, count 0 2006.285.18:11:34.29#ibcon#read 6, iclass 13, count 0 2006.285.18:11:34.29#ibcon#end of sib2, iclass 13, count 0 2006.285.18:11:34.29#ibcon#*mode == 0, iclass 13, count 0 2006.285.18:11:34.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.18:11:34.29#ibcon#[25=USB\r\n] 2006.285.18:11:34.29#ibcon#*before write, iclass 13, count 0 2006.285.18:11:34.29#ibcon#enter sib2, iclass 13, count 0 2006.285.18:11:34.29#ibcon#flushed, iclass 13, count 0 2006.285.18:11:34.29#ibcon#about to write, iclass 13, count 0 2006.285.18:11:34.29#ibcon#wrote, iclass 13, count 0 2006.285.18:11:34.29#ibcon#about to read 3, iclass 13, count 0 2006.285.18:11:34.32#ibcon#read 3, iclass 13, count 0 2006.285.18:11:34.32#ibcon#about to read 4, iclass 13, count 0 2006.285.18:11:34.32#ibcon#read 4, iclass 13, count 0 2006.285.18:11:34.32#ibcon#about to read 5, iclass 13, count 0 2006.285.18:11:34.32#ibcon#read 5, iclass 13, count 0 2006.285.18:11:34.32#ibcon#about to read 6, iclass 13, count 0 2006.285.18:11:34.32#ibcon#read 6, iclass 13, count 0 2006.285.18:11:34.32#ibcon#end of sib2, iclass 13, count 0 2006.285.18:11:34.32#ibcon#*after write, iclass 13, count 0 2006.285.18:11:34.32#ibcon#*before return 0, iclass 13, count 0 2006.285.18:11:34.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:11:34.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:11:34.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.18:11:34.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.18:11:34.32$vck44/valo=6,814.99 2006.285.18:11:34.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.18:11:34.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.18:11:34.32#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:34.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:11:34.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:11:34.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:11:34.32#ibcon#enter wrdev, iclass 15, count 0 2006.285.18:11:34.32#ibcon#first serial, iclass 15, count 0 2006.285.18:11:34.32#ibcon#enter sib2, iclass 15, count 0 2006.285.18:11:34.32#ibcon#flushed, iclass 15, count 0 2006.285.18:11:34.32#ibcon#about to write, iclass 15, count 0 2006.285.18:11:34.32#ibcon#wrote, iclass 15, count 0 2006.285.18:11:34.32#ibcon#about to read 3, iclass 15, count 0 2006.285.18:11:34.34#ibcon#read 3, iclass 15, count 0 2006.285.18:11:34.34#ibcon#about to read 4, iclass 15, count 0 2006.285.18:11:34.34#ibcon#read 4, iclass 15, count 0 2006.285.18:11:34.34#ibcon#about to read 5, iclass 15, count 0 2006.285.18:11:34.34#ibcon#read 5, iclass 15, count 0 2006.285.18:11:34.34#ibcon#about to read 6, iclass 15, count 0 2006.285.18:11:34.34#ibcon#read 6, iclass 15, count 0 2006.285.18:11:34.34#ibcon#end of sib2, iclass 15, count 0 2006.285.18:11:34.34#ibcon#*mode == 0, iclass 15, count 0 2006.285.18:11:34.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.18:11:34.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.18:11:34.34#ibcon#*before write, iclass 15, count 0 2006.285.18:11:34.34#ibcon#enter sib2, iclass 15, count 0 2006.285.18:11:34.34#ibcon#flushed, iclass 15, count 0 2006.285.18:11:34.34#ibcon#about to write, iclass 15, count 0 2006.285.18:11:34.34#ibcon#wrote, iclass 15, count 0 2006.285.18:11:34.34#ibcon#about to read 3, iclass 15, count 0 2006.285.18:11:34.38#ibcon#read 3, iclass 15, count 0 2006.285.18:11:34.38#ibcon#about to read 4, iclass 15, count 0 2006.285.18:11:34.38#ibcon#read 4, iclass 15, count 0 2006.285.18:11:34.38#ibcon#about to read 5, iclass 15, count 0 2006.285.18:11:34.38#ibcon#read 5, iclass 15, count 0 2006.285.18:11:34.38#ibcon#about to read 6, iclass 15, count 0 2006.285.18:11:34.38#ibcon#read 6, iclass 15, count 0 2006.285.18:11:34.38#ibcon#end of sib2, iclass 15, count 0 2006.285.18:11:34.38#ibcon#*after write, iclass 15, count 0 2006.285.18:11:34.38#ibcon#*before return 0, iclass 15, count 0 2006.285.18:11:34.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:11:34.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:11:34.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.18:11:34.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.18:11:34.38$vck44/va=6,4 2006.285.18:11:34.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.18:11:34.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.18:11:34.38#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:34.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:11:34.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:11:34.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:11:34.44#ibcon#enter wrdev, iclass 17, count 2 2006.285.18:11:34.44#ibcon#first serial, iclass 17, count 2 2006.285.18:11:34.44#ibcon#enter sib2, iclass 17, count 2 2006.285.18:11:34.44#ibcon#flushed, iclass 17, count 2 2006.285.18:11:34.44#ibcon#about to write, iclass 17, count 2 2006.285.18:11:34.44#ibcon#wrote, iclass 17, count 2 2006.285.18:11:34.44#ibcon#about to read 3, iclass 17, count 2 2006.285.18:11:34.46#ibcon#read 3, iclass 17, count 2 2006.285.18:11:34.46#ibcon#about to read 4, iclass 17, count 2 2006.285.18:11:34.46#ibcon#read 4, iclass 17, count 2 2006.285.18:11:34.46#ibcon#about to read 5, iclass 17, count 2 2006.285.18:11:34.46#ibcon#read 5, iclass 17, count 2 2006.285.18:11:34.46#ibcon#about to read 6, iclass 17, count 2 2006.285.18:11:34.46#ibcon#read 6, iclass 17, count 2 2006.285.18:11:34.46#ibcon#end of sib2, iclass 17, count 2 2006.285.18:11:34.46#ibcon#*mode == 0, iclass 17, count 2 2006.285.18:11:34.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.18:11:34.46#ibcon#[25=AT06-04\r\n] 2006.285.18:11:34.46#ibcon#*before write, iclass 17, count 2 2006.285.18:11:34.46#ibcon#enter sib2, iclass 17, count 2 2006.285.18:11:34.46#ibcon#flushed, iclass 17, count 2 2006.285.18:11:34.46#ibcon#about to write, iclass 17, count 2 2006.285.18:11:34.46#ibcon#wrote, iclass 17, count 2 2006.285.18:11:34.46#ibcon#about to read 3, iclass 17, count 2 2006.285.18:11:34.49#ibcon#read 3, iclass 17, count 2 2006.285.18:11:34.49#ibcon#about to read 4, iclass 17, count 2 2006.285.18:11:34.49#ibcon#read 4, iclass 17, count 2 2006.285.18:11:34.49#ibcon#about to read 5, iclass 17, count 2 2006.285.18:11:34.49#ibcon#read 5, iclass 17, count 2 2006.285.18:11:34.49#ibcon#about to read 6, iclass 17, count 2 2006.285.18:11:34.49#ibcon#read 6, iclass 17, count 2 2006.285.18:11:34.49#ibcon#end of sib2, iclass 17, count 2 2006.285.18:11:34.49#ibcon#*after write, iclass 17, count 2 2006.285.18:11:34.49#ibcon#*before return 0, iclass 17, count 2 2006.285.18:11:34.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:11:34.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:11:34.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.18:11:34.49#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:34.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:11:34.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:11:34.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:11:34.61#ibcon#enter wrdev, iclass 17, count 0 2006.285.18:11:34.61#ibcon#first serial, iclass 17, count 0 2006.285.18:11:34.61#ibcon#enter sib2, iclass 17, count 0 2006.285.18:11:34.61#ibcon#flushed, iclass 17, count 0 2006.285.18:11:34.61#ibcon#about to write, iclass 17, count 0 2006.285.18:11:34.61#ibcon#wrote, iclass 17, count 0 2006.285.18:11:34.61#ibcon#about to read 3, iclass 17, count 0 2006.285.18:11:34.63#ibcon#read 3, iclass 17, count 0 2006.285.18:11:34.63#ibcon#about to read 4, iclass 17, count 0 2006.285.18:11:34.63#ibcon#read 4, iclass 17, count 0 2006.285.18:11:34.63#ibcon#about to read 5, iclass 17, count 0 2006.285.18:11:34.63#ibcon#read 5, iclass 17, count 0 2006.285.18:11:34.63#ibcon#about to read 6, iclass 17, count 0 2006.285.18:11:34.63#ibcon#read 6, iclass 17, count 0 2006.285.18:11:34.63#ibcon#end of sib2, iclass 17, count 0 2006.285.18:11:34.63#ibcon#*mode == 0, iclass 17, count 0 2006.285.18:11:34.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.18:11:34.63#ibcon#[25=USB\r\n] 2006.285.18:11:34.63#ibcon#*before write, iclass 17, count 0 2006.285.18:11:34.63#ibcon#enter sib2, iclass 17, count 0 2006.285.18:11:34.63#ibcon#flushed, iclass 17, count 0 2006.285.18:11:34.63#ibcon#about to write, iclass 17, count 0 2006.285.18:11:34.63#ibcon#wrote, iclass 17, count 0 2006.285.18:11:34.63#ibcon#about to read 3, iclass 17, count 0 2006.285.18:11:34.66#ibcon#read 3, iclass 17, count 0 2006.285.18:11:34.66#ibcon#about to read 4, iclass 17, count 0 2006.285.18:11:34.66#ibcon#read 4, iclass 17, count 0 2006.285.18:11:34.66#ibcon#about to read 5, iclass 17, count 0 2006.285.18:11:34.66#ibcon#read 5, iclass 17, count 0 2006.285.18:11:34.66#ibcon#about to read 6, iclass 17, count 0 2006.285.18:11:34.66#ibcon#read 6, iclass 17, count 0 2006.285.18:11:34.66#ibcon#end of sib2, iclass 17, count 0 2006.285.18:11:34.66#ibcon#*after write, iclass 17, count 0 2006.285.18:11:34.66#ibcon#*before return 0, iclass 17, count 0 2006.285.18:11:34.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:11:34.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:11:34.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.18:11:34.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.18:11:34.66$vck44/valo=7,864.99 2006.285.18:11:34.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.18:11:34.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.18:11:34.66#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:34.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:11:34.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:11:34.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:11:34.66#ibcon#enter wrdev, iclass 19, count 0 2006.285.18:11:34.66#ibcon#first serial, iclass 19, count 0 2006.285.18:11:34.66#ibcon#enter sib2, iclass 19, count 0 2006.285.18:11:34.66#ibcon#flushed, iclass 19, count 0 2006.285.18:11:34.66#ibcon#about to write, iclass 19, count 0 2006.285.18:11:34.66#ibcon#wrote, iclass 19, count 0 2006.285.18:11:34.66#ibcon#about to read 3, iclass 19, count 0 2006.285.18:11:34.68#ibcon#read 3, iclass 19, count 0 2006.285.18:11:34.69#ibcon#about to read 4, iclass 19, count 0 2006.285.18:11:34.69#ibcon#read 4, iclass 19, count 0 2006.285.18:11:34.69#ibcon#about to read 5, iclass 19, count 0 2006.285.18:11:34.69#ibcon#read 5, iclass 19, count 0 2006.285.18:11:34.69#ibcon#about to read 6, iclass 19, count 0 2006.285.18:11:34.69#ibcon#read 6, iclass 19, count 0 2006.285.18:11:34.69#ibcon#end of sib2, iclass 19, count 0 2006.285.18:11:34.69#ibcon#*mode == 0, iclass 19, count 0 2006.285.18:11:34.69#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.18:11:34.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.18:11:34.69#ibcon#*before write, iclass 19, count 0 2006.285.18:11:34.69#ibcon#enter sib2, iclass 19, count 0 2006.285.18:11:34.69#ibcon#flushed, iclass 19, count 0 2006.285.18:11:34.69#ibcon#about to write, iclass 19, count 0 2006.285.18:11:34.69#ibcon#wrote, iclass 19, count 0 2006.285.18:11:34.69#ibcon#about to read 3, iclass 19, count 0 2006.285.18:11:34.73#ibcon#read 3, iclass 19, count 0 2006.285.18:11:34.73#ibcon#about to read 4, iclass 19, count 0 2006.285.18:11:34.73#ibcon#read 4, iclass 19, count 0 2006.285.18:11:34.73#ibcon#about to read 5, iclass 19, count 0 2006.285.18:11:34.73#ibcon#read 5, iclass 19, count 0 2006.285.18:11:34.73#ibcon#about to read 6, iclass 19, count 0 2006.285.18:11:34.73#ibcon#read 6, iclass 19, count 0 2006.285.18:11:34.73#ibcon#end of sib2, iclass 19, count 0 2006.285.18:11:34.73#ibcon#*after write, iclass 19, count 0 2006.285.18:11:34.73#ibcon#*before return 0, iclass 19, count 0 2006.285.18:11:34.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:11:34.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:11:34.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.18:11:34.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.18:11:34.73$vck44/va=7,4 2006.285.18:11:34.73#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.18:11:34.73#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.18:11:34.73#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:34.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:11:34.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:11:34.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:11:34.78#ibcon#enter wrdev, iclass 21, count 2 2006.285.18:11:34.78#ibcon#first serial, iclass 21, count 2 2006.285.18:11:34.78#ibcon#enter sib2, iclass 21, count 2 2006.285.18:11:34.78#ibcon#flushed, iclass 21, count 2 2006.285.18:11:34.78#ibcon#about to write, iclass 21, count 2 2006.285.18:11:34.78#ibcon#wrote, iclass 21, count 2 2006.285.18:11:34.78#ibcon#about to read 3, iclass 21, count 2 2006.285.18:11:34.80#ibcon#read 3, iclass 21, count 2 2006.285.18:11:34.80#ibcon#about to read 4, iclass 21, count 2 2006.285.18:11:34.80#ibcon#read 4, iclass 21, count 2 2006.285.18:11:34.80#ibcon#about to read 5, iclass 21, count 2 2006.285.18:11:34.80#ibcon#read 5, iclass 21, count 2 2006.285.18:11:34.80#ibcon#about to read 6, iclass 21, count 2 2006.285.18:11:34.80#ibcon#read 6, iclass 21, count 2 2006.285.18:11:34.80#ibcon#end of sib2, iclass 21, count 2 2006.285.18:11:34.80#ibcon#*mode == 0, iclass 21, count 2 2006.285.18:11:34.80#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.18:11:34.80#ibcon#[25=AT07-04\r\n] 2006.285.18:11:34.80#ibcon#*before write, iclass 21, count 2 2006.285.18:11:34.80#ibcon#enter sib2, iclass 21, count 2 2006.285.18:11:34.80#ibcon#flushed, iclass 21, count 2 2006.285.18:11:34.80#ibcon#about to write, iclass 21, count 2 2006.285.18:11:34.80#ibcon#wrote, iclass 21, count 2 2006.285.18:11:34.80#ibcon#about to read 3, iclass 21, count 2 2006.285.18:11:34.83#ibcon#read 3, iclass 21, count 2 2006.285.18:11:34.83#ibcon#about to read 4, iclass 21, count 2 2006.285.18:11:34.83#ibcon#read 4, iclass 21, count 2 2006.285.18:11:34.83#ibcon#about to read 5, iclass 21, count 2 2006.285.18:11:34.83#ibcon#read 5, iclass 21, count 2 2006.285.18:11:34.83#ibcon#about to read 6, iclass 21, count 2 2006.285.18:11:34.83#ibcon#read 6, iclass 21, count 2 2006.285.18:11:34.83#ibcon#end of sib2, iclass 21, count 2 2006.285.18:11:34.83#ibcon#*after write, iclass 21, count 2 2006.285.18:11:34.83#ibcon#*before return 0, iclass 21, count 2 2006.285.18:11:34.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:11:34.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:11:34.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.18:11:34.83#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:34.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:11:34.95#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:11:34.95#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:11:34.95#ibcon#enter wrdev, iclass 21, count 0 2006.285.18:11:34.95#ibcon#first serial, iclass 21, count 0 2006.285.18:11:34.95#ibcon#enter sib2, iclass 21, count 0 2006.285.18:11:34.95#ibcon#flushed, iclass 21, count 0 2006.285.18:11:34.95#ibcon#about to write, iclass 21, count 0 2006.285.18:11:34.95#ibcon#wrote, iclass 21, count 0 2006.285.18:11:34.95#ibcon#about to read 3, iclass 21, count 0 2006.285.18:11:34.97#ibcon#read 3, iclass 21, count 0 2006.285.18:11:34.97#ibcon#about to read 4, iclass 21, count 0 2006.285.18:11:34.97#ibcon#read 4, iclass 21, count 0 2006.285.18:11:34.97#ibcon#about to read 5, iclass 21, count 0 2006.285.18:11:34.97#ibcon#read 5, iclass 21, count 0 2006.285.18:11:34.97#ibcon#about to read 6, iclass 21, count 0 2006.285.18:11:34.97#ibcon#read 6, iclass 21, count 0 2006.285.18:11:34.97#ibcon#end of sib2, iclass 21, count 0 2006.285.18:11:34.97#ibcon#*mode == 0, iclass 21, count 0 2006.285.18:11:34.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.18:11:34.97#ibcon#[25=USB\r\n] 2006.285.18:11:34.97#ibcon#*before write, iclass 21, count 0 2006.285.18:11:34.97#ibcon#enter sib2, iclass 21, count 0 2006.285.18:11:34.97#ibcon#flushed, iclass 21, count 0 2006.285.18:11:34.97#ibcon#about to write, iclass 21, count 0 2006.285.18:11:34.97#ibcon#wrote, iclass 21, count 0 2006.285.18:11:34.97#ibcon#about to read 3, iclass 21, count 0 2006.285.18:11:35.00#ibcon#read 3, iclass 21, count 0 2006.285.18:11:35.00#ibcon#about to read 4, iclass 21, count 0 2006.285.18:11:35.00#ibcon#read 4, iclass 21, count 0 2006.285.18:11:35.00#ibcon#about to read 5, iclass 21, count 0 2006.285.18:11:35.00#ibcon#read 5, iclass 21, count 0 2006.285.18:11:35.00#ibcon#about to read 6, iclass 21, count 0 2006.285.18:11:35.00#ibcon#read 6, iclass 21, count 0 2006.285.18:11:35.00#ibcon#end of sib2, iclass 21, count 0 2006.285.18:11:35.00#ibcon#*after write, iclass 21, count 0 2006.285.18:11:35.00#ibcon#*before return 0, iclass 21, count 0 2006.285.18:11:35.00#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:11:35.00#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:11:35.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.18:11:35.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.18:11:35.00$vck44/valo=8,884.99 2006.285.18:11:35.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.18:11:35.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.18:11:35.00#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:35.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:11:35.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:11:35.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:11:35.00#ibcon#enter wrdev, iclass 23, count 0 2006.285.18:11:35.00#ibcon#first serial, iclass 23, count 0 2006.285.18:11:35.00#ibcon#enter sib2, iclass 23, count 0 2006.285.18:11:35.00#ibcon#flushed, iclass 23, count 0 2006.285.18:11:35.00#ibcon#about to write, iclass 23, count 0 2006.285.18:11:35.00#ibcon#wrote, iclass 23, count 0 2006.285.18:11:35.00#ibcon#about to read 3, iclass 23, count 0 2006.285.18:11:35.02#ibcon#read 3, iclass 23, count 0 2006.285.18:11:35.02#ibcon#about to read 4, iclass 23, count 0 2006.285.18:11:35.02#ibcon#read 4, iclass 23, count 0 2006.285.18:11:35.02#ibcon#about to read 5, iclass 23, count 0 2006.285.18:11:35.02#ibcon#read 5, iclass 23, count 0 2006.285.18:11:35.02#ibcon#about to read 6, iclass 23, count 0 2006.285.18:11:35.02#ibcon#read 6, iclass 23, count 0 2006.285.18:11:35.02#ibcon#end of sib2, iclass 23, count 0 2006.285.18:11:35.02#ibcon#*mode == 0, iclass 23, count 0 2006.285.18:11:35.02#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.18:11:35.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.18:11:35.02#ibcon#*before write, iclass 23, count 0 2006.285.18:11:35.02#ibcon#enter sib2, iclass 23, count 0 2006.285.18:11:35.02#ibcon#flushed, iclass 23, count 0 2006.285.18:11:35.02#ibcon#about to write, iclass 23, count 0 2006.285.18:11:35.02#ibcon#wrote, iclass 23, count 0 2006.285.18:11:35.02#ibcon#about to read 3, iclass 23, count 0 2006.285.18:11:35.06#ibcon#read 3, iclass 23, count 0 2006.285.18:11:35.06#ibcon#about to read 4, iclass 23, count 0 2006.285.18:11:35.06#ibcon#read 4, iclass 23, count 0 2006.285.18:11:35.06#ibcon#about to read 5, iclass 23, count 0 2006.285.18:11:35.06#ibcon#read 5, iclass 23, count 0 2006.285.18:11:35.06#ibcon#about to read 6, iclass 23, count 0 2006.285.18:11:35.06#ibcon#read 6, iclass 23, count 0 2006.285.18:11:35.06#ibcon#end of sib2, iclass 23, count 0 2006.285.18:11:35.06#ibcon#*after write, iclass 23, count 0 2006.285.18:11:35.06#ibcon#*before return 0, iclass 23, count 0 2006.285.18:11:35.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:11:35.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:11:35.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.18:11:35.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.18:11:35.06$vck44/va=8,3 2006.285.18:11:35.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.18:11:35.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.18:11:35.06#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:35.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:11:35.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:11:35.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:11:35.12#ibcon#enter wrdev, iclass 25, count 2 2006.285.18:11:35.12#ibcon#first serial, iclass 25, count 2 2006.285.18:11:35.12#ibcon#enter sib2, iclass 25, count 2 2006.285.18:11:35.12#ibcon#flushed, iclass 25, count 2 2006.285.18:11:35.12#ibcon#about to write, iclass 25, count 2 2006.285.18:11:35.12#ibcon#wrote, iclass 25, count 2 2006.285.18:11:35.12#ibcon#about to read 3, iclass 25, count 2 2006.285.18:11:35.14#ibcon#read 3, iclass 25, count 2 2006.285.18:11:35.14#ibcon#about to read 4, iclass 25, count 2 2006.285.18:11:35.14#ibcon#read 4, iclass 25, count 2 2006.285.18:11:35.14#ibcon#about to read 5, iclass 25, count 2 2006.285.18:11:35.14#ibcon#read 5, iclass 25, count 2 2006.285.18:11:35.14#ibcon#about to read 6, iclass 25, count 2 2006.285.18:11:35.14#ibcon#read 6, iclass 25, count 2 2006.285.18:11:35.14#ibcon#end of sib2, iclass 25, count 2 2006.285.18:11:35.14#ibcon#*mode == 0, iclass 25, count 2 2006.285.18:11:35.14#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.18:11:35.14#ibcon#[25=AT08-03\r\n] 2006.285.18:11:35.14#ibcon#*before write, iclass 25, count 2 2006.285.18:11:35.14#ibcon#enter sib2, iclass 25, count 2 2006.285.18:11:35.14#ibcon#flushed, iclass 25, count 2 2006.285.18:11:35.14#ibcon#about to write, iclass 25, count 2 2006.285.18:11:35.14#ibcon#wrote, iclass 25, count 2 2006.285.18:11:35.14#ibcon#about to read 3, iclass 25, count 2 2006.285.18:11:35.17#ibcon#read 3, iclass 25, count 2 2006.285.18:11:35.17#ibcon#about to read 4, iclass 25, count 2 2006.285.18:11:35.17#ibcon#read 4, iclass 25, count 2 2006.285.18:11:35.17#ibcon#about to read 5, iclass 25, count 2 2006.285.18:11:35.17#ibcon#read 5, iclass 25, count 2 2006.285.18:11:35.17#ibcon#about to read 6, iclass 25, count 2 2006.285.18:11:35.17#ibcon#read 6, iclass 25, count 2 2006.285.18:11:35.17#ibcon#end of sib2, iclass 25, count 2 2006.285.18:11:35.17#ibcon#*after write, iclass 25, count 2 2006.285.18:11:35.17#ibcon#*before return 0, iclass 25, count 2 2006.285.18:11:35.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:11:35.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:11:35.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.18:11:35.17#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:35.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:11:35.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:11:35.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:11:35.29#ibcon#enter wrdev, iclass 25, count 0 2006.285.18:11:35.29#ibcon#first serial, iclass 25, count 0 2006.285.18:11:35.29#ibcon#enter sib2, iclass 25, count 0 2006.285.18:11:35.29#ibcon#flushed, iclass 25, count 0 2006.285.18:11:35.29#ibcon#about to write, iclass 25, count 0 2006.285.18:11:35.29#ibcon#wrote, iclass 25, count 0 2006.285.18:11:35.29#ibcon#about to read 3, iclass 25, count 0 2006.285.18:11:35.31#ibcon#read 3, iclass 25, count 0 2006.285.18:11:35.31#ibcon#about to read 4, iclass 25, count 0 2006.285.18:11:35.31#ibcon#read 4, iclass 25, count 0 2006.285.18:11:35.31#ibcon#about to read 5, iclass 25, count 0 2006.285.18:11:35.31#ibcon#read 5, iclass 25, count 0 2006.285.18:11:35.31#ibcon#about to read 6, iclass 25, count 0 2006.285.18:11:35.31#ibcon#read 6, iclass 25, count 0 2006.285.18:11:35.31#ibcon#end of sib2, iclass 25, count 0 2006.285.18:11:35.31#ibcon#*mode == 0, iclass 25, count 0 2006.285.18:11:35.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.18:11:35.31#ibcon#[25=USB\r\n] 2006.285.18:11:35.31#ibcon#*before write, iclass 25, count 0 2006.285.18:11:35.31#ibcon#enter sib2, iclass 25, count 0 2006.285.18:11:35.31#ibcon#flushed, iclass 25, count 0 2006.285.18:11:35.31#ibcon#about to write, iclass 25, count 0 2006.285.18:11:35.31#ibcon#wrote, iclass 25, count 0 2006.285.18:11:35.31#ibcon#about to read 3, iclass 25, count 0 2006.285.18:11:35.34#ibcon#read 3, iclass 25, count 0 2006.285.18:11:35.34#ibcon#about to read 4, iclass 25, count 0 2006.285.18:11:35.34#ibcon#read 4, iclass 25, count 0 2006.285.18:11:35.34#ibcon#about to read 5, iclass 25, count 0 2006.285.18:11:35.34#ibcon#read 5, iclass 25, count 0 2006.285.18:11:35.34#ibcon#about to read 6, iclass 25, count 0 2006.285.18:11:35.34#ibcon#read 6, iclass 25, count 0 2006.285.18:11:35.34#ibcon#end of sib2, iclass 25, count 0 2006.285.18:11:35.34#ibcon#*after write, iclass 25, count 0 2006.285.18:11:35.34#ibcon#*before return 0, iclass 25, count 0 2006.285.18:11:35.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:11:35.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:11:35.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.18:11:35.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.18:11:35.34$vck44/vblo=1,629.99 2006.285.18:11:35.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.18:11:35.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.18:11:35.34#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:35.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:11:35.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:11:35.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:11:35.34#ibcon#enter wrdev, iclass 27, count 0 2006.285.18:11:35.34#ibcon#first serial, iclass 27, count 0 2006.285.18:11:35.34#ibcon#enter sib2, iclass 27, count 0 2006.285.18:11:35.34#ibcon#flushed, iclass 27, count 0 2006.285.18:11:35.34#ibcon#about to write, iclass 27, count 0 2006.285.18:11:35.34#ibcon#wrote, iclass 27, count 0 2006.285.18:11:35.34#ibcon#about to read 3, iclass 27, count 0 2006.285.18:11:35.36#ibcon#read 3, iclass 27, count 0 2006.285.18:11:35.36#ibcon#about to read 4, iclass 27, count 0 2006.285.18:11:35.36#ibcon#read 4, iclass 27, count 0 2006.285.18:11:35.36#ibcon#about to read 5, iclass 27, count 0 2006.285.18:11:35.36#ibcon#read 5, iclass 27, count 0 2006.285.18:11:35.36#ibcon#about to read 6, iclass 27, count 0 2006.285.18:11:35.36#ibcon#read 6, iclass 27, count 0 2006.285.18:11:35.36#ibcon#end of sib2, iclass 27, count 0 2006.285.18:11:35.36#ibcon#*mode == 0, iclass 27, count 0 2006.285.18:11:35.36#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.18:11:35.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.18:11:35.36#ibcon#*before write, iclass 27, count 0 2006.285.18:11:35.36#ibcon#enter sib2, iclass 27, count 0 2006.285.18:11:35.36#ibcon#flushed, iclass 27, count 0 2006.285.18:11:35.36#ibcon#about to write, iclass 27, count 0 2006.285.18:11:35.36#ibcon#wrote, iclass 27, count 0 2006.285.18:11:35.36#ibcon#about to read 3, iclass 27, count 0 2006.285.18:11:35.40#ibcon#read 3, iclass 27, count 0 2006.285.18:11:35.40#ibcon#about to read 4, iclass 27, count 0 2006.285.18:11:35.40#ibcon#read 4, iclass 27, count 0 2006.285.18:11:35.40#ibcon#about to read 5, iclass 27, count 0 2006.285.18:11:35.40#ibcon#read 5, iclass 27, count 0 2006.285.18:11:35.40#ibcon#about to read 6, iclass 27, count 0 2006.285.18:11:35.40#ibcon#read 6, iclass 27, count 0 2006.285.18:11:35.40#ibcon#end of sib2, iclass 27, count 0 2006.285.18:11:35.40#ibcon#*after write, iclass 27, count 0 2006.285.18:11:35.40#ibcon#*before return 0, iclass 27, count 0 2006.285.18:11:35.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:11:35.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:11:35.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.18:11:35.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.18:11:35.40$vck44/vb=1,4 2006.285.18:11:35.40#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.18:11:35.40#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.18:11:35.40#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:35.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:11:35.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:11:35.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:11:35.40#ibcon#enter wrdev, iclass 29, count 2 2006.285.18:11:35.40#ibcon#first serial, iclass 29, count 2 2006.285.18:11:35.40#ibcon#enter sib2, iclass 29, count 2 2006.285.18:11:35.40#ibcon#flushed, iclass 29, count 2 2006.285.18:11:35.40#ibcon#about to write, iclass 29, count 2 2006.285.18:11:35.40#ibcon#wrote, iclass 29, count 2 2006.285.18:11:35.40#ibcon#about to read 3, iclass 29, count 2 2006.285.18:11:35.42#ibcon#read 3, iclass 29, count 2 2006.285.18:11:35.42#ibcon#about to read 4, iclass 29, count 2 2006.285.18:11:35.42#ibcon#read 4, iclass 29, count 2 2006.285.18:11:35.42#ibcon#about to read 5, iclass 29, count 2 2006.285.18:11:35.42#ibcon#read 5, iclass 29, count 2 2006.285.18:11:35.42#ibcon#about to read 6, iclass 29, count 2 2006.285.18:11:35.42#ibcon#read 6, iclass 29, count 2 2006.285.18:11:35.42#ibcon#end of sib2, iclass 29, count 2 2006.285.18:11:35.42#ibcon#*mode == 0, iclass 29, count 2 2006.285.18:11:35.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.18:11:35.42#ibcon#[27=AT01-04\r\n] 2006.285.18:11:35.42#ibcon#*before write, iclass 29, count 2 2006.285.18:11:35.42#ibcon#enter sib2, iclass 29, count 2 2006.285.18:11:35.42#ibcon#flushed, iclass 29, count 2 2006.285.18:11:35.42#ibcon#about to write, iclass 29, count 2 2006.285.18:11:35.42#ibcon#wrote, iclass 29, count 2 2006.285.18:11:35.42#ibcon#about to read 3, iclass 29, count 2 2006.285.18:11:35.45#ibcon#read 3, iclass 29, count 2 2006.285.18:11:35.45#ibcon#about to read 4, iclass 29, count 2 2006.285.18:11:35.45#ibcon#read 4, iclass 29, count 2 2006.285.18:11:35.45#ibcon#about to read 5, iclass 29, count 2 2006.285.18:11:35.45#ibcon#read 5, iclass 29, count 2 2006.285.18:11:35.45#ibcon#about to read 6, iclass 29, count 2 2006.285.18:11:35.45#ibcon#read 6, iclass 29, count 2 2006.285.18:11:35.45#ibcon#end of sib2, iclass 29, count 2 2006.285.18:11:35.45#ibcon#*after write, iclass 29, count 2 2006.285.18:11:35.45#ibcon#*before return 0, iclass 29, count 2 2006.285.18:11:35.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:11:35.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:11:35.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.18:11:35.45#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:35.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:11:35.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:11:35.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:11:35.57#ibcon#enter wrdev, iclass 29, count 0 2006.285.18:11:35.57#ibcon#first serial, iclass 29, count 0 2006.285.18:11:35.57#ibcon#enter sib2, iclass 29, count 0 2006.285.18:11:35.57#ibcon#flushed, iclass 29, count 0 2006.285.18:11:35.57#ibcon#about to write, iclass 29, count 0 2006.285.18:11:35.57#ibcon#wrote, iclass 29, count 0 2006.285.18:11:35.57#ibcon#about to read 3, iclass 29, count 0 2006.285.18:11:35.59#ibcon#read 3, iclass 29, count 0 2006.285.18:11:35.59#ibcon#about to read 4, iclass 29, count 0 2006.285.18:11:35.59#ibcon#read 4, iclass 29, count 0 2006.285.18:11:35.59#ibcon#about to read 5, iclass 29, count 0 2006.285.18:11:35.59#ibcon#read 5, iclass 29, count 0 2006.285.18:11:35.59#ibcon#about to read 6, iclass 29, count 0 2006.285.18:11:35.59#ibcon#read 6, iclass 29, count 0 2006.285.18:11:35.59#ibcon#end of sib2, iclass 29, count 0 2006.285.18:11:35.59#ibcon#*mode == 0, iclass 29, count 0 2006.285.18:11:35.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.18:11:35.59#ibcon#[27=USB\r\n] 2006.285.18:11:35.59#ibcon#*before write, iclass 29, count 0 2006.285.18:11:35.59#ibcon#enter sib2, iclass 29, count 0 2006.285.18:11:35.59#ibcon#flushed, iclass 29, count 0 2006.285.18:11:35.59#ibcon#about to write, iclass 29, count 0 2006.285.18:11:35.59#ibcon#wrote, iclass 29, count 0 2006.285.18:11:35.59#ibcon#about to read 3, iclass 29, count 0 2006.285.18:11:35.62#ibcon#read 3, iclass 29, count 0 2006.285.18:11:35.62#ibcon#about to read 4, iclass 29, count 0 2006.285.18:11:35.62#ibcon#read 4, iclass 29, count 0 2006.285.18:11:35.62#ibcon#about to read 5, iclass 29, count 0 2006.285.18:11:35.62#ibcon#read 5, iclass 29, count 0 2006.285.18:11:35.62#ibcon#about to read 6, iclass 29, count 0 2006.285.18:11:35.62#ibcon#read 6, iclass 29, count 0 2006.285.18:11:35.62#ibcon#end of sib2, iclass 29, count 0 2006.285.18:11:35.62#ibcon#*after write, iclass 29, count 0 2006.285.18:11:35.62#ibcon#*before return 0, iclass 29, count 0 2006.285.18:11:35.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:11:35.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:11:35.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.18:11:35.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.18:11:35.62$vck44/vblo=2,634.99 2006.285.18:11:35.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.18:11:35.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.18:11:35.62#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:35.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:11:35.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:11:35.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:11:35.62#ibcon#enter wrdev, iclass 31, count 0 2006.285.18:11:35.62#ibcon#first serial, iclass 31, count 0 2006.285.18:11:35.62#ibcon#enter sib2, iclass 31, count 0 2006.285.18:11:35.62#ibcon#flushed, iclass 31, count 0 2006.285.18:11:35.62#ibcon#about to write, iclass 31, count 0 2006.285.18:11:35.62#ibcon#wrote, iclass 31, count 0 2006.285.18:11:35.62#ibcon#about to read 3, iclass 31, count 0 2006.285.18:11:35.64#ibcon#read 3, iclass 31, count 0 2006.285.18:11:35.73#ibcon#about to read 4, iclass 31, count 0 2006.285.18:11:35.73#ibcon#read 4, iclass 31, count 0 2006.285.18:11:35.73#ibcon#about to read 5, iclass 31, count 0 2006.285.18:11:35.73#ibcon#read 5, iclass 31, count 0 2006.285.18:11:35.73#ibcon#about to read 6, iclass 31, count 0 2006.285.18:11:35.73#ibcon#read 6, iclass 31, count 0 2006.285.18:11:35.73#ibcon#end of sib2, iclass 31, count 0 2006.285.18:11:35.73#ibcon#*mode == 0, iclass 31, count 0 2006.285.18:11:35.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.18:11:35.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.18:11:35.73#ibcon#*before write, iclass 31, count 0 2006.285.18:11:35.73#ibcon#enter sib2, iclass 31, count 0 2006.285.18:11:35.73#ibcon#flushed, iclass 31, count 0 2006.285.18:11:35.73#ibcon#about to write, iclass 31, count 0 2006.285.18:11:35.73#ibcon#wrote, iclass 31, count 0 2006.285.18:11:35.73#ibcon#about to read 3, iclass 31, count 0 2006.285.18:11:35.77#ibcon#read 3, iclass 31, count 0 2006.285.18:11:35.77#ibcon#about to read 4, iclass 31, count 0 2006.285.18:11:35.77#ibcon#read 4, iclass 31, count 0 2006.285.18:11:35.77#ibcon#about to read 5, iclass 31, count 0 2006.285.18:11:35.77#ibcon#read 5, iclass 31, count 0 2006.285.18:11:35.77#ibcon#about to read 6, iclass 31, count 0 2006.285.18:11:35.77#ibcon#read 6, iclass 31, count 0 2006.285.18:11:35.77#ibcon#end of sib2, iclass 31, count 0 2006.285.18:11:35.77#ibcon#*after write, iclass 31, count 0 2006.285.18:11:35.77#ibcon#*before return 0, iclass 31, count 0 2006.285.18:11:35.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:11:35.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:11:35.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.18:11:35.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.18:11:35.77$vck44/vb=2,5 2006.285.18:11:35.77#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.18:11:35.77#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.18:11:35.77#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:35.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:11:35.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:11:35.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:11:35.77#ibcon#enter wrdev, iclass 33, count 2 2006.285.18:11:35.77#ibcon#first serial, iclass 33, count 2 2006.285.18:11:35.77#ibcon#enter sib2, iclass 33, count 2 2006.285.18:11:35.77#ibcon#flushed, iclass 33, count 2 2006.285.18:11:35.77#ibcon#about to write, iclass 33, count 2 2006.285.18:11:35.77#ibcon#wrote, iclass 33, count 2 2006.285.18:11:35.77#ibcon#about to read 3, iclass 33, count 2 2006.285.18:11:35.79#ibcon#read 3, iclass 33, count 2 2006.285.18:11:35.79#ibcon#about to read 4, iclass 33, count 2 2006.285.18:11:35.79#ibcon#read 4, iclass 33, count 2 2006.285.18:11:35.79#ibcon#about to read 5, iclass 33, count 2 2006.285.18:11:35.79#ibcon#read 5, iclass 33, count 2 2006.285.18:11:35.79#ibcon#about to read 6, iclass 33, count 2 2006.285.18:11:35.79#ibcon#read 6, iclass 33, count 2 2006.285.18:11:35.79#ibcon#end of sib2, iclass 33, count 2 2006.285.18:11:35.79#ibcon#*mode == 0, iclass 33, count 2 2006.285.18:11:35.79#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.18:11:35.79#ibcon#[27=AT02-05\r\n] 2006.285.18:11:35.79#ibcon#*before write, iclass 33, count 2 2006.285.18:11:35.79#ibcon#enter sib2, iclass 33, count 2 2006.285.18:11:35.79#ibcon#flushed, iclass 33, count 2 2006.285.18:11:35.79#ibcon#about to write, iclass 33, count 2 2006.285.18:11:35.79#ibcon#wrote, iclass 33, count 2 2006.285.18:11:35.79#ibcon#about to read 3, iclass 33, count 2 2006.285.18:11:35.82#ibcon#read 3, iclass 33, count 2 2006.285.18:11:35.82#ibcon#about to read 4, iclass 33, count 2 2006.285.18:11:35.82#ibcon#read 4, iclass 33, count 2 2006.285.18:11:35.82#ibcon#about to read 5, iclass 33, count 2 2006.285.18:11:35.82#ibcon#read 5, iclass 33, count 2 2006.285.18:11:35.82#ibcon#about to read 6, iclass 33, count 2 2006.285.18:11:35.82#ibcon#read 6, iclass 33, count 2 2006.285.18:11:35.82#ibcon#end of sib2, iclass 33, count 2 2006.285.18:11:35.82#ibcon#*after write, iclass 33, count 2 2006.285.18:11:35.82#ibcon#*before return 0, iclass 33, count 2 2006.285.18:11:35.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:11:35.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:11:35.82#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.18:11:35.82#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:35.82#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:11:35.94#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:11:35.94#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:11:35.94#ibcon#enter wrdev, iclass 33, count 0 2006.285.18:11:35.94#ibcon#first serial, iclass 33, count 0 2006.285.18:11:35.94#ibcon#enter sib2, iclass 33, count 0 2006.285.18:11:35.94#ibcon#flushed, iclass 33, count 0 2006.285.18:11:35.94#ibcon#about to write, iclass 33, count 0 2006.285.18:11:35.94#ibcon#wrote, iclass 33, count 0 2006.285.18:11:35.94#ibcon#about to read 3, iclass 33, count 0 2006.285.18:11:35.96#ibcon#read 3, iclass 33, count 0 2006.285.18:11:35.96#ibcon#about to read 4, iclass 33, count 0 2006.285.18:11:35.96#ibcon#read 4, iclass 33, count 0 2006.285.18:11:35.96#ibcon#about to read 5, iclass 33, count 0 2006.285.18:11:35.96#ibcon#read 5, iclass 33, count 0 2006.285.18:11:35.96#ibcon#about to read 6, iclass 33, count 0 2006.285.18:11:35.96#ibcon#read 6, iclass 33, count 0 2006.285.18:11:35.96#ibcon#end of sib2, iclass 33, count 0 2006.285.18:11:35.96#ibcon#*mode == 0, iclass 33, count 0 2006.285.18:11:35.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.18:11:35.96#ibcon#[27=USB\r\n] 2006.285.18:11:35.96#ibcon#*before write, iclass 33, count 0 2006.285.18:11:35.96#ibcon#enter sib2, iclass 33, count 0 2006.285.18:11:35.96#ibcon#flushed, iclass 33, count 0 2006.285.18:11:35.96#ibcon#about to write, iclass 33, count 0 2006.285.18:11:35.96#ibcon#wrote, iclass 33, count 0 2006.285.18:11:35.96#ibcon#about to read 3, iclass 33, count 0 2006.285.18:11:35.99#ibcon#read 3, iclass 33, count 0 2006.285.18:11:35.99#ibcon#about to read 4, iclass 33, count 0 2006.285.18:11:35.99#ibcon#read 4, iclass 33, count 0 2006.285.18:11:35.99#ibcon#about to read 5, iclass 33, count 0 2006.285.18:11:35.99#ibcon#read 5, iclass 33, count 0 2006.285.18:11:35.99#ibcon#about to read 6, iclass 33, count 0 2006.285.18:11:35.99#ibcon#read 6, iclass 33, count 0 2006.285.18:11:35.99#ibcon#end of sib2, iclass 33, count 0 2006.285.18:11:35.99#ibcon#*after write, iclass 33, count 0 2006.285.18:11:35.99#ibcon#*before return 0, iclass 33, count 0 2006.285.18:11:35.99#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:11:35.99#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:11:35.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.18:11:35.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.18:11:35.99$vck44/vblo=3,649.99 2006.285.18:11:35.99#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.18:11:35.99#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.18:11:35.99#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:35.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:11:35.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:11:35.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:11:35.99#ibcon#enter wrdev, iclass 35, count 0 2006.285.18:11:35.99#ibcon#first serial, iclass 35, count 0 2006.285.18:11:35.99#ibcon#enter sib2, iclass 35, count 0 2006.285.18:11:35.99#ibcon#flushed, iclass 35, count 0 2006.285.18:11:35.99#ibcon#about to write, iclass 35, count 0 2006.285.18:11:35.99#ibcon#wrote, iclass 35, count 0 2006.285.18:11:35.99#ibcon#about to read 3, iclass 35, count 0 2006.285.18:11:36.01#ibcon#read 3, iclass 35, count 0 2006.285.18:11:36.01#ibcon#about to read 4, iclass 35, count 0 2006.285.18:11:36.01#ibcon#read 4, iclass 35, count 0 2006.285.18:11:36.01#ibcon#about to read 5, iclass 35, count 0 2006.285.18:11:36.01#ibcon#read 5, iclass 35, count 0 2006.285.18:11:36.01#ibcon#about to read 6, iclass 35, count 0 2006.285.18:11:36.01#ibcon#read 6, iclass 35, count 0 2006.285.18:11:36.01#ibcon#end of sib2, iclass 35, count 0 2006.285.18:11:36.01#ibcon#*mode == 0, iclass 35, count 0 2006.285.18:11:36.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.18:11:36.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.18:11:36.01#ibcon#*before write, iclass 35, count 0 2006.285.18:11:36.01#ibcon#enter sib2, iclass 35, count 0 2006.285.18:11:36.01#ibcon#flushed, iclass 35, count 0 2006.285.18:11:36.01#ibcon#about to write, iclass 35, count 0 2006.285.18:11:36.01#ibcon#wrote, iclass 35, count 0 2006.285.18:11:36.01#ibcon#about to read 3, iclass 35, count 0 2006.285.18:11:36.05#ibcon#read 3, iclass 35, count 0 2006.285.18:11:36.05#ibcon#about to read 4, iclass 35, count 0 2006.285.18:11:36.05#ibcon#read 4, iclass 35, count 0 2006.285.18:11:36.05#ibcon#about to read 5, iclass 35, count 0 2006.285.18:11:36.05#ibcon#read 5, iclass 35, count 0 2006.285.18:11:36.05#ibcon#about to read 6, iclass 35, count 0 2006.285.18:11:36.05#ibcon#read 6, iclass 35, count 0 2006.285.18:11:36.05#ibcon#end of sib2, iclass 35, count 0 2006.285.18:11:36.05#ibcon#*after write, iclass 35, count 0 2006.285.18:11:36.05#ibcon#*before return 0, iclass 35, count 0 2006.285.18:11:36.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:11:36.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:11:36.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.18:11:36.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.18:11:36.05$vck44/vb=3,4 2006.285.18:11:36.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.18:11:36.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.18:11:36.05#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:36.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:11:36.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:11:36.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:11:36.11#ibcon#enter wrdev, iclass 37, count 2 2006.285.18:11:36.11#ibcon#first serial, iclass 37, count 2 2006.285.18:11:36.11#ibcon#enter sib2, iclass 37, count 2 2006.285.18:11:36.11#ibcon#flushed, iclass 37, count 2 2006.285.18:11:36.11#ibcon#about to write, iclass 37, count 2 2006.285.18:11:36.11#ibcon#wrote, iclass 37, count 2 2006.285.18:11:36.11#ibcon#about to read 3, iclass 37, count 2 2006.285.18:11:36.13#ibcon#read 3, iclass 37, count 2 2006.285.18:11:36.13#ibcon#about to read 4, iclass 37, count 2 2006.285.18:11:36.13#ibcon#read 4, iclass 37, count 2 2006.285.18:11:36.13#ibcon#about to read 5, iclass 37, count 2 2006.285.18:11:36.13#ibcon#read 5, iclass 37, count 2 2006.285.18:11:36.13#ibcon#about to read 6, iclass 37, count 2 2006.285.18:11:36.13#ibcon#read 6, iclass 37, count 2 2006.285.18:11:36.13#ibcon#end of sib2, iclass 37, count 2 2006.285.18:11:36.13#ibcon#*mode == 0, iclass 37, count 2 2006.285.18:11:36.13#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.18:11:36.13#ibcon#[27=AT03-04\r\n] 2006.285.18:11:36.13#ibcon#*before write, iclass 37, count 2 2006.285.18:11:36.13#ibcon#enter sib2, iclass 37, count 2 2006.285.18:11:36.13#ibcon#flushed, iclass 37, count 2 2006.285.18:11:36.13#ibcon#about to write, iclass 37, count 2 2006.285.18:11:36.13#ibcon#wrote, iclass 37, count 2 2006.285.18:11:36.13#ibcon#about to read 3, iclass 37, count 2 2006.285.18:11:36.16#ibcon#read 3, iclass 37, count 2 2006.285.18:11:36.16#ibcon#about to read 4, iclass 37, count 2 2006.285.18:11:36.16#ibcon#read 4, iclass 37, count 2 2006.285.18:11:36.16#ibcon#about to read 5, iclass 37, count 2 2006.285.18:11:36.16#ibcon#read 5, iclass 37, count 2 2006.285.18:11:36.16#ibcon#about to read 6, iclass 37, count 2 2006.285.18:11:36.16#ibcon#read 6, iclass 37, count 2 2006.285.18:11:36.16#ibcon#end of sib2, iclass 37, count 2 2006.285.18:11:36.16#ibcon#*after write, iclass 37, count 2 2006.285.18:11:36.16#ibcon#*before return 0, iclass 37, count 2 2006.285.18:11:36.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:11:36.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:11:36.16#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.18:11:36.16#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:36.16#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:11:36.28#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:11:36.28#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:11:36.28#ibcon#enter wrdev, iclass 37, count 0 2006.285.18:11:36.28#ibcon#first serial, iclass 37, count 0 2006.285.18:11:36.28#ibcon#enter sib2, iclass 37, count 0 2006.285.18:11:36.28#ibcon#flushed, iclass 37, count 0 2006.285.18:11:36.28#ibcon#about to write, iclass 37, count 0 2006.285.18:11:36.28#ibcon#wrote, iclass 37, count 0 2006.285.18:11:36.28#ibcon#about to read 3, iclass 37, count 0 2006.285.18:11:36.30#ibcon#read 3, iclass 37, count 0 2006.285.18:11:36.30#ibcon#about to read 4, iclass 37, count 0 2006.285.18:11:36.30#ibcon#read 4, iclass 37, count 0 2006.285.18:11:36.30#ibcon#about to read 5, iclass 37, count 0 2006.285.18:11:36.30#ibcon#read 5, iclass 37, count 0 2006.285.18:11:36.30#ibcon#about to read 6, iclass 37, count 0 2006.285.18:11:36.30#ibcon#read 6, iclass 37, count 0 2006.285.18:11:36.30#ibcon#end of sib2, iclass 37, count 0 2006.285.18:11:36.30#ibcon#*mode == 0, iclass 37, count 0 2006.285.18:11:36.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.18:11:36.30#ibcon#[27=USB\r\n] 2006.285.18:11:36.30#ibcon#*before write, iclass 37, count 0 2006.285.18:11:36.30#ibcon#enter sib2, iclass 37, count 0 2006.285.18:11:36.30#ibcon#flushed, iclass 37, count 0 2006.285.18:11:36.30#ibcon#about to write, iclass 37, count 0 2006.285.18:11:36.30#ibcon#wrote, iclass 37, count 0 2006.285.18:11:36.30#ibcon#about to read 3, iclass 37, count 0 2006.285.18:11:36.33#ibcon#read 3, iclass 37, count 0 2006.285.18:11:36.33#ibcon#about to read 4, iclass 37, count 0 2006.285.18:11:36.33#ibcon#read 4, iclass 37, count 0 2006.285.18:11:36.33#ibcon#about to read 5, iclass 37, count 0 2006.285.18:11:36.33#ibcon#read 5, iclass 37, count 0 2006.285.18:11:36.33#ibcon#about to read 6, iclass 37, count 0 2006.285.18:11:36.33#ibcon#read 6, iclass 37, count 0 2006.285.18:11:36.33#ibcon#end of sib2, iclass 37, count 0 2006.285.18:11:36.33#ibcon#*after write, iclass 37, count 0 2006.285.18:11:36.33#ibcon#*before return 0, iclass 37, count 0 2006.285.18:11:36.33#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:11:36.33#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:11:36.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.18:11:36.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.18:11:36.33$vck44/vblo=4,679.99 2006.285.18:11:36.33#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.18:11:36.33#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.18:11:36.33#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:36.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:11:36.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:11:36.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:11:36.33#ibcon#enter wrdev, iclass 39, count 0 2006.285.18:11:36.33#ibcon#first serial, iclass 39, count 0 2006.285.18:11:36.33#ibcon#enter sib2, iclass 39, count 0 2006.285.18:11:36.33#ibcon#flushed, iclass 39, count 0 2006.285.18:11:36.33#ibcon#about to write, iclass 39, count 0 2006.285.18:11:36.33#ibcon#wrote, iclass 39, count 0 2006.285.18:11:36.33#ibcon#about to read 3, iclass 39, count 0 2006.285.18:11:36.35#ibcon#read 3, iclass 39, count 0 2006.285.18:11:36.35#ibcon#about to read 4, iclass 39, count 0 2006.285.18:11:36.35#ibcon#read 4, iclass 39, count 0 2006.285.18:11:36.35#ibcon#about to read 5, iclass 39, count 0 2006.285.18:11:36.35#ibcon#read 5, iclass 39, count 0 2006.285.18:11:36.35#ibcon#about to read 6, iclass 39, count 0 2006.285.18:11:36.35#ibcon#read 6, iclass 39, count 0 2006.285.18:11:36.35#ibcon#end of sib2, iclass 39, count 0 2006.285.18:11:36.35#ibcon#*mode == 0, iclass 39, count 0 2006.285.18:11:36.35#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.18:11:36.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.18:11:36.35#ibcon#*before write, iclass 39, count 0 2006.285.18:11:36.35#ibcon#enter sib2, iclass 39, count 0 2006.285.18:11:36.35#ibcon#flushed, iclass 39, count 0 2006.285.18:11:36.35#ibcon#about to write, iclass 39, count 0 2006.285.18:11:36.35#ibcon#wrote, iclass 39, count 0 2006.285.18:11:36.35#ibcon#about to read 3, iclass 39, count 0 2006.285.18:11:36.39#ibcon#read 3, iclass 39, count 0 2006.285.18:11:36.39#ibcon#about to read 4, iclass 39, count 0 2006.285.18:11:36.39#ibcon#read 4, iclass 39, count 0 2006.285.18:11:36.39#ibcon#about to read 5, iclass 39, count 0 2006.285.18:11:36.39#ibcon#read 5, iclass 39, count 0 2006.285.18:11:36.39#ibcon#about to read 6, iclass 39, count 0 2006.285.18:11:36.39#ibcon#read 6, iclass 39, count 0 2006.285.18:11:36.39#ibcon#end of sib2, iclass 39, count 0 2006.285.18:11:36.39#ibcon#*after write, iclass 39, count 0 2006.285.18:11:36.39#ibcon#*before return 0, iclass 39, count 0 2006.285.18:11:36.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:11:36.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:11:36.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.18:11:36.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.18:11:36.39$vck44/vb=4,5 2006.285.18:11:36.39#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.18:11:36.39#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.18:11:36.39#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:36.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:11:36.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:11:36.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:11:36.45#ibcon#enter wrdev, iclass 3, count 2 2006.285.18:11:36.45#ibcon#first serial, iclass 3, count 2 2006.285.18:11:36.45#ibcon#enter sib2, iclass 3, count 2 2006.285.18:11:36.45#ibcon#flushed, iclass 3, count 2 2006.285.18:11:36.45#ibcon#about to write, iclass 3, count 2 2006.285.18:11:36.45#ibcon#wrote, iclass 3, count 2 2006.285.18:11:36.45#ibcon#about to read 3, iclass 3, count 2 2006.285.18:11:36.47#ibcon#read 3, iclass 3, count 2 2006.285.18:11:36.47#ibcon#about to read 4, iclass 3, count 2 2006.285.18:11:36.47#ibcon#read 4, iclass 3, count 2 2006.285.18:11:36.47#ibcon#about to read 5, iclass 3, count 2 2006.285.18:11:36.47#ibcon#read 5, iclass 3, count 2 2006.285.18:11:36.47#ibcon#about to read 6, iclass 3, count 2 2006.285.18:11:36.47#ibcon#read 6, iclass 3, count 2 2006.285.18:11:36.47#ibcon#end of sib2, iclass 3, count 2 2006.285.18:11:36.47#ibcon#*mode == 0, iclass 3, count 2 2006.285.18:11:36.47#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.18:11:36.47#ibcon#[27=AT04-05\r\n] 2006.285.18:11:36.47#ibcon#*before write, iclass 3, count 2 2006.285.18:11:36.47#ibcon#enter sib2, iclass 3, count 2 2006.285.18:11:36.47#ibcon#flushed, iclass 3, count 2 2006.285.18:11:36.47#ibcon#about to write, iclass 3, count 2 2006.285.18:11:36.47#ibcon#wrote, iclass 3, count 2 2006.285.18:11:36.47#ibcon#about to read 3, iclass 3, count 2 2006.285.18:11:36.50#ibcon#read 3, iclass 3, count 2 2006.285.18:11:36.50#ibcon#about to read 4, iclass 3, count 2 2006.285.18:11:36.50#ibcon#read 4, iclass 3, count 2 2006.285.18:11:36.50#ibcon#about to read 5, iclass 3, count 2 2006.285.18:11:36.50#ibcon#read 5, iclass 3, count 2 2006.285.18:11:36.50#ibcon#about to read 6, iclass 3, count 2 2006.285.18:11:36.50#ibcon#read 6, iclass 3, count 2 2006.285.18:11:36.50#ibcon#end of sib2, iclass 3, count 2 2006.285.18:11:36.50#ibcon#*after write, iclass 3, count 2 2006.285.18:11:36.50#ibcon#*before return 0, iclass 3, count 2 2006.285.18:11:36.50#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:11:36.50#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:11:36.50#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.18:11:36.50#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:36.50#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:11:36.62#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:11:36.62#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:11:36.62#ibcon#enter wrdev, iclass 3, count 0 2006.285.18:11:36.62#ibcon#first serial, iclass 3, count 0 2006.285.18:11:36.62#ibcon#enter sib2, iclass 3, count 0 2006.285.18:11:36.62#ibcon#flushed, iclass 3, count 0 2006.285.18:11:36.62#ibcon#about to write, iclass 3, count 0 2006.285.18:11:36.62#ibcon#wrote, iclass 3, count 0 2006.285.18:11:36.62#ibcon#about to read 3, iclass 3, count 0 2006.285.18:11:36.64#ibcon#read 3, iclass 3, count 0 2006.285.18:11:36.64#ibcon#about to read 4, iclass 3, count 0 2006.285.18:11:36.64#ibcon#read 4, iclass 3, count 0 2006.285.18:11:36.64#ibcon#about to read 5, iclass 3, count 0 2006.285.18:11:36.64#ibcon#read 5, iclass 3, count 0 2006.285.18:11:36.64#ibcon#about to read 6, iclass 3, count 0 2006.285.18:11:36.64#ibcon#read 6, iclass 3, count 0 2006.285.18:11:36.64#ibcon#end of sib2, iclass 3, count 0 2006.285.18:11:36.64#ibcon#*mode == 0, iclass 3, count 0 2006.285.18:11:36.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.18:11:36.64#ibcon#[27=USB\r\n] 2006.285.18:11:36.64#ibcon#*before write, iclass 3, count 0 2006.285.18:11:36.64#ibcon#enter sib2, iclass 3, count 0 2006.285.18:11:36.64#ibcon#flushed, iclass 3, count 0 2006.285.18:11:36.64#ibcon#about to write, iclass 3, count 0 2006.285.18:11:36.64#ibcon#wrote, iclass 3, count 0 2006.285.18:11:36.64#ibcon#about to read 3, iclass 3, count 0 2006.285.18:11:36.67#ibcon#read 3, iclass 3, count 0 2006.285.18:11:36.67#ibcon#about to read 4, iclass 3, count 0 2006.285.18:11:36.67#ibcon#read 4, iclass 3, count 0 2006.285.18:11:36.67#ibcon#about to read 5, iclass 3, count 0 2006.285.18:11:36.67#ibcon#read 5, iclass 3, count 0 2006.285.18:11:36.67#ibcon#about to read 6, iclass 3, count 0 2006.285.18:11:36.67#ibcon#read 6, iclass 3, count 0 2006.285.18:11:36.67#ibcon#end of sib2, iclass 3, count 0 2006.285.18:11:36.67#ibcon#*after write, iclass 3, count 0 2006.285.18:11:36.67#ibcon#*before return 0, iclass 3, count 0 2006.285.18:11:36.67#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:11:36.67#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:11:36.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.18:11:36.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.18:11:36.67$vck44/vblo=5,709.99 2006.285.18:11:36.67#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.18:11:36.67#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.18:11:36.67#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:36.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:11:36.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:11:36.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:11:36.67#ibcon#enter wrdev, iclass 5, count 0 2006.285.18:11:36.67#ibcon#first serial, iclass 5, count 0 2006.285.18:11:36.67#ibcon#enter sib2, iclass 5, count 0 2006.285.18:11:36.67#ibcon#flushed, iclass 5, count 0 2006.285.18:11:36.67#ibcon#about to write, iclass 5, count 0 2006.285.18:11:36.67#ibcon#wrote, iclass 5, count 0 2006.285.18:11:36.67#ibcon#about to read 3, iclass 5, count 0 2006.285.18:11:36.69#ibcon#read 3, iclass 5, count 0 2006.285.18:11:36.81#ibcon#about to read 4, iclass 5, count 0 2006.285.18:11:36.81#ibcon#read 4, iclass 5, count 0 2006.285.18:11:36.81#ibcon#about to read 5, iclass 5, count 0 2006.285.18:11:36.81#ibcon#read 5, iclass 5, count 0 2006.285.18:11:36.81#ibcon#about to read 6, iclass 5, count 0 2006.285.18:11:36.81#ibcon#read 6, iclass 5, count 0 2006.285.18:11:36.81#ibcon#end of sib2, iclass 5, count 0 2006.285.18:11:36.81#ibcon#*mode == 0, iclass 5, count 0 2006.285.18:11:36.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.18:11:36.81#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.18:11:36.81#ibcon#*before write, iclass 5, count 0 2006.285.18:11:36.81#ibcon#enter sib2, iclass 5, count 0 2006.285.18:11:36.81#ibcon#flushed, iclass 5, count 0 2006.285.18:11:36.81#ibcon#about to write, iclass 5, count 0 2006.285.18:11:36.81#ibcon#wrote, iclass 5, count 0 2006.285.18:11:36.81#ibcon#about to read 3, iclass 5, count 0 2006.285.18:11:36.85#ibcon#read 3, iclass 5, count 0 2006.285.18:11:36.85#ibcon#about to read 4, iclass 5, count 0 2006.285.18:11:36.85#ibcon#read 4, iclass 5, count 0 2006.285.18:11:36.85#ibcon#about to read 5, iclass 5, count 0 2006.285.18:11:36.85#ibcon#read 5, iclass 5, count 0 2006.285.18:11:36.85#ibcon#about to read 6, iclass 5, count 0 2006.285.18:11:36.85#ibcon#read 6, iclass 5, count 0 2006.285.18:11:36.85#ibcon#end of sib2, iclass 5, count 0 2006.285.18:11:36.85#ibcon#*after write, iclass 5, count 0 2006.285.18:11:36.85#ibcon#*before return 0, iclass 5, count 0 2006.285.18:11:36.85#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:11:36.85#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:11:36.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.18:11:36.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.18:11:36.85$vck44/vb=5,4 2006.285.18:11:36.85#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.18:11:36.85#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.18:11:36.85#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:36.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:11:36.85#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:11:36.85#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:11:36.85#ibcon#enter wrdev, iclass 7, count 2 2006.285.18:11:36.85#ibcon#first serial, iclass 7, count 2 2006.285.18:11:36.85#ibcon#enter sib2, iclass 7, count 2 2006.285.18:11:36.85#ibcon#flushed, iclass 7, count 2 2006.285.18:11:36.85#ibcon#about to write, iclass 7, count 2 2006.285.18:11:36.85#ibcon#wrote, iclass 7, count 2 2006.285.18:11:36.85#ibcon#about to read 3, iclass 7, count 2 2006.285.18:11:36.87#ibcon#read 3, iclass 7, count 2 2006.285.18:11:36.87#ibcon#about to read 4, iclass 7, count 2 2006.285.18:11:36.87#ibcon#read 4, iclass 7, count 2 2006.285.18:11:36.87#ibcon#about to read 5, iclass 7, count 2 2006.285.18:11:36.87#ibcon#read 5, iclass 7, count 2 2006.285.18:11:36.87#ibcon#about to read 6, iclass 7, count 2 2006.285.18:11:36.87#ibcon#read 6, iclass 7, count 2 2006.285.18:11:36.87#ibcon#end of sib2, iclass 7, count 2 2006.285.18:11:36.87#ibcon#*mode == 0, iclass 7, count 2 2006.285.18:11:36.87#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.18:11:36.87#ibcon#[27=AT05-04\r\n] 2006.285.18:11:36.87#ibcon#*before write, iclass 7, count 2 2006.285.18:11:36.87#ibcon#enter sib2, iclass 7, count 2 2006.285.18:11:36.87#ibcon#flushed, iclass 7, count 2 2006.285.18:11:36.87#ibcon#about to write, iclass 7, count 2 2006.285.18:11:36.87#ibcon#wrote, iclass 7, count 2 2006.285.18:11:36.87#ibcon#about to read 3, iclass 7, count 2 2006.285.18:11:36.90#ibcon#read 3, iclass 7, count 2 2006.285.18:11:36.90#ibcon#about to read 4, iclass 7, count 2 2006.285.18:11:36.90#ibcon#read 4, iclass 7, count 2 2006.285.18:11:36.90#ibcon#about to read 5, iclass 7, count 2 2006.285.18:11:36.90#ibcon#read 5, iclass 7, count 2 2006.285.18:11:36.90#ibcon#about to read 6, iclass 7, count 2 2006.285.18:11:36.90#ibcon#read 6, iclass 7, count 2 2006.285.18:11:36.90#ibcon#end of sib2, iclass 7, count 2 2006.285.18:11:36.90#ibcon#*after write, iclass 7, count 2 2006.285.18:11:36.90#ibcon#*before return 0, iclass 7, count 2 2006.285.18:11:36.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:11:36.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:11:36.90#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.18:11:36.90#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:36.90#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:11:37.02#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:11:37.02#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:11:37.02#ibcon#enter wrdev, iclass 7, count 0 2006.285.18:11:37.02#ibcon#first serial, iclass 7, count 0 2006.285.18:11:37.02#ibcon#enter sib2, iclass 7, count 0 2006.285.18:11:37.02#ibcon#flushed, iclass 7, count 0 2006.285.18:11:37.02#ibcon#about to write, iclass 7, count 0 2006.285.18:11:37.02#ibcon#wrote, iclass 7, count 0 2006.285.18:11:37.02#ibcon#about to read 3, iclass 7, count 0 2006.285.18:11:37.04#ibcon#read 3, iclass 7, count 0 2006.285.18:11:37.04#ibcon#about to read 4, iclass 7, count 0 2006.285.18:11:37.04#ibcon#read 4, iclass 7, count 0 2006.285.18:11:37.04#ibcon#about to read 5, iclass 7, count 0 2006.285.18:11:37.04#ibcon#read 5, iclass 7, count 0 2006.285.18:11:37.04#ibcon#about to read 6, iclass 7, count 0 2006.285.18:11:37.04#ibcon#read 6, iclass 7, count 0 2006.285.18:11:37.04#ibcon#end of sib2, iclass 7, count 0 2006.285.18:11:37.04#ibcon#*mode == 0, iclass 7, count 0 2006.285.18:11:37.04#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.18:11:37.04#ibcon#[27=USB\r\n] 2006.285.18:11:37.04#ibcon#*before write, iclass 7, count 0 2006.285.18:11:37.04#ibcon#enter sib2, iclass 7, count 0 2006.285.18:11:37.04#ibcon#flushed, iclass 7, count 0 2006.285.18:11:37.04#ibcon#about to write, iclass 7, count 0 2006.285.18:11:37.04#ibcon#wrote, iclass 7, count 0 2006.285.18:11:37.04#ibcon#about to read 3, iclass 7, count 0 2006.285.18:11:37.07#ibcon#read 3, iclass 7, count 0 2006.285.18:11:37.07#ibcon#about to read 4, iclass 7, count 0 2006.285.18:11:37.07#ibcon#read 4, iclass 7, count 0 2006.285.18:11:37.07#ibcon#about to read 5, iclass 7, count 0 2006.285.18:11:37.07#ibcon#read 5, iclass 7, count 0 2006.285.18:11:37.07#ibcon#about to read 6, iclass 7, count 0 2006.285.18:11:37.07#ibcon#read 6, iclass 7, count 0 2006.285.18:11:37.07#ibcon#end of sib2, iclass 7, count 0 2006.285.18:11:37.07#ibcon#*after write, iclass 7, count 0 2006.285.18:11:37.07#ibcon#*before return 0, iclass 7, count 0 2006.285.18:11:37.07#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:11:37.07#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:11:37.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.18:11:37.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.18:11:37.07$vck44/vblo=6,719.99 2006.285.18:11:37.07#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.18:11:37.07#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.18:11:37.07#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:37.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:11:37.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:11:37.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:11:37.07#ibcon#enter wrdev, iclass 11, count 0 2006.285.18:11:37.07#ibcon#first serial, iclass 11, count 0 2006.285.18:11:37.07#ibcon#enter sib2, iclass 11, count 0 2006.285.18:11:37.07#ibcon#flushed, iclass 11, count 0 2006.285.18:11:37.07#ibcon#about to write, iclass 11, count 0 2006.285.18:11:37.07#ibcon#wrote, iclass 11, count 0 2006.285.18:11:37.07#ibcon#about to read 3, iclass 11, count 0 2006.285.18:11:37.09#ibcon#read 3, iclass 11, count 0 2006.285.18:11:37.09#ibcon#about to read 4, iclass 11, count 0 2006.285.18:11:37.09#ibcon#read 4, iclass 11, count 0 2006.285.18:11:37.09#ibcon#about to read 5, iclass 11, count 0 2006.285.18:11:37.09#ibcon#read 5, iclass 11, count 0 2006.285.18:11:37.09#ibcon#about to read 6, iclass 11, count 0 2006.285.18:11:37.09#ibcon#read 6, iclass 11, count 0 2006.285.18:11:37.09#ibcon#end of sib2, iclass 11, count 0 2006.285.18:11:37.09#ibcon#*mode == 0, iclass 11, count 0 2006.285.18:11:37.09#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.18:11:37.09#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.18:11:37.09#ibcon#*before write, iclass 11, count 0 2006.285.18:11:37.09#ibcon#enter sib2, iclass 11, count 0 2006.285.18:11:37.09#ibcon#flushed, iclass 11, count 0 2006.285.18:11:37.09#ibcon#about to write, iclass 11, count 0 2006.285.18:11:37.09#ibcon#wrote, iclass 11, count 0 2006.285.18:11:37.09#ibcon#about to read 3, iclass 11, count 0 2006.285.18:11:37.13#ibcon#read 3, iclass 11, count 0 2006.285.18:11:37.13#ibcon#about to read 4, iclass 11, count 0 2006.285.18:11:37.13#ibcon#read 4, iclass 11, count 0 2006.285.18:11:37.13#ibcon#about to read 5, iclass 11, count 0 2006.285.18:11:37.13#ibcon#read 5, iclass 11, count 0 2006.285.18:11:37.13#ibcon#about to read 6, iclass 11, count 0 2006.285.18:11:37.13#ibcon#read 6, iclass 11, count 0 2006.285.18:11:37.13#ibcon#end of sib2, iclass 11, count 0 2006.285.18:11:37.13#ibcon#*after write, iclass 11, count 0 2006.285.18:11:37.13#ibcon#*before return 0, iclass 11, count 0 2006.285.18:11:37.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:11:37.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:11:37.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.18:11:37.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.18:11:37.13$vck44/vb=6,3 2006.285.18:11:37.13#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.18:11:37.13#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.18:11:37.13#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:37.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:11:37.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:11:37.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:11:37.19#ibcon#enter wrdev, iclass 13, count 2 2006.285.18:11:37.19#ibcon#first serial, iclass 13, count 2 2006.285.18:11:37.19#ibcon#enter sib2, iclass 13, count 2 2006.285.18:11:37.19#ibcon#flushed, iclass 13, count 2 2006.285.18:11:37.19#ibcon#about to write, iclass 13, count 2 2006.285.18:11:37.19#ibcon#wrote, iclass 13, count 2 2006.285.18:11:37.19#ibcon#about to read 3, iclass 13, count 2 2006.285.18:11:37.21#ibcon#read 3, iclass 13, count 2 2006.285.18:11:37.21#ibcon#about to read 4, iclass 13, count 2 2006.285.18:11:37.21#ibcon#read 4, iclass 13, count 2 2006.285.18:11:37.21#ibcon#about to read 5, iclass 13, count 2 2006.285.18:11:37.21#ibcon#read 5, iclass 13, count 2 2006.285.18:11:37.21#ibcon#about to read 6, iclass 13, count 2 2006.285.18:11:37.21#ibcon#read 6, iclass 13, count 2 2006.285.18:11:37.21#ibcon#end of sib2, iclass 13, count 2 2006.285.18:11:37.21#ibcon#*mode == 0, iclass 13, count 2 2006.285.18:11:37.21#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.18:11:37.21#ibcon#[27=AT06-03\r\n] 2006.285.18:11:37.21#ibcon#*before write, iclass 13, count 2 2006.285.18:11:37.21#ibcon#enter sib2, iclass 13, count 2 2006.285.18:11:37.21#ibcon#flushed, iclass 13, count 2 2006.285.18:11:37.21#ibcon#about to write, iclass 13, count 2 2006.285.18:11:37.21#ibcon#wrote, iclass 13, count 2 2006.285.18:11:37.21#ibcon#about to read 3, iclass 13, count 2 2006.285.18:11:37.24#ibcon#read 3, iclass 13, count 2 2006.285.18:11:37.24#ibcon#about to read 4, iclass 13, count 2 2006.285.18:11:37.24#ibcon#read 4, iclass 13, count 2 2006.285.18:11:37.24#ibcon#about to read 5, iclass 13, count 2 2006.285.18:11:37.24#ibcon#read 5, iclass 13, count 2 2006.285.18:11:37.24#ibcon#about to read 6, iclass 13, count 2 2006.285.18:11:37.24#ibcon#read 6, iclass 13, count 2 2006.285.18:11:37.24#ibcon#end of sib2, iclass 13, count 2 2006.285.18:11:37.24#ibcon#*after write, iclass 13, count 2 2006.285.18:11:37.24#ibcon#*before return 0, iclass 13, count 2 2006.285.18:11:37.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:11:37.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:11:37.24#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.18:11:37.24#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:37.24#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:11:37.36#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:11:37.36#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:11:37.36#ibcon#enter wrdev, iclass 13, count 0 2006.285.18:11:37.36#ibcon#first serial, iclass 13, count 0 2006.285.18:11:37.36#ibcon#enter sib2, iclass 13, count 0 2006.285.18:11:37.36#ibcon#flushed, iclass 13, count 0 2006.285.18:11:37.36#ibcon#about to write, iclass 13, count 0 2006.285.18:11:37.36#ibcon#wrote, iclass 13, count 0 2006.285.18:11:37.36#ibcon#about to read 3, iclass 13, count 0 2006.285.18:11:37.38#ibcon#read 3, iclass 13, count 0 2006.285.18:11:37.38#ibcon#about to read 4, iclass 13, count 0 2006.285.18:11:37.38#ibcon#read 4, iclass 13, count 0 2006.285.18:11:37.38#ibcon#about to read 5, iclass 13, count 0 2006.285.18:11:37.38#ibcon#read 5, iclass 13, count 0 2006.285.18:11:37.38#ibcon#about to read 6, iclass 13, count 0 2006.285.18:11:37.38#ibcon#read 6, iclass 13, count 0 2006.285.18:11:37.38#ibcon#end of sib2, iclass 13, count 0 2006.285.18:11:37.38#ibcon#*mode == 0, iclass 13, count 0 2006.285.18:11:37.38#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.18:11:37.38#ibcon#[27=USB\r\n] 2006.285.18:11:37.38#ibcon#*before write, iclass 13, count 0 2006.285.18:11:37.38#ibcon#enter sib2, iclass 13, count 0 2006.285.18:11:37.38#ibcon#flushed, iclass 13, count 0 2006.285.18:11:37.38#ibcon#about to write, iclass 13, count 0 2006.285.18:11:37.38#ibcon#wrote, iclass 13, count 0 2006.285.18:11:37.38#ibcon#about to read 3, iclass 13, count 0 2006.285.18:11:37.41#ibcon#read 3, iclass 13, count 0 2006.285.18:11:37.41#ibcon#about to read 4, iclass 13, count 0 2006.285.18:11:37.41#ibcon#read 4, iclass 13, count 0 2006.285.18:11:37.41#ibcon#about to read 5, iclass 13, count 0 2006.285.18:11:37.41#ibcon#read 5, iclass 13, count 0 2006.285.18:11:37.41#ibcon#about to read 6, iclass 13, count 0 2006.285.18:11:37.41#ibcon#read 6, iclass 13, count 0 2006.285.18:11:37.41#ibcon#end of sib2, iclass 13, count 0 2006.285.18:11:37.41#ibcon#*after write, iclass 13, count 0 2006.285.18:11:37.41#ibcon#*before return 0, iclass 13, count 0 2006.285.18:11:37.41#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:11:37.41#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:11:37.41#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.18:11:37.41#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.18:11:37.41$vck44/vblo=7,734.99 2006.285.18:11:37.41#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.18:11:37.41#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.18:11:37.41#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:37.41#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:11:37.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:11:37.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:11:37.41#ibcon#enter wrdev, iclass 15, count 0 2006.285.18:11:37.41#ibcon#first serial, iclass 15, count 0 2006.285.18:11:37.41#ibcon#enter sib2, iclass 15, count 0 2006.285.18:11:37.41#ibcon#flushed, iclass 15, count 0 2006.285.18:11:37.41#ibcon#about to write, iclass 15, count 0 2006.285.18:11:37.41#ibcon#wrote, iclass 15, count 0 2006.285.18:11:37.41#ibcon#about to read 3, iclass 15, count 0 2006.285.18:11:37.43#ibcon#read 3, iclass 15, count 0 2006.285.18:11:37.43#ibcon#about to read 4, iclass 15, count 0 2006.285.18:11:37.43#ibcon#read 4, iclass 15, count 0 2006.285.18:11:37.43#ibcon#about to read 5, iclass 15, count 0 2006.285.18:11:37.43#ibcon#read 5, iclass 15, count 0 2006.285.18:11:37.43#ibcon#about to read 6, iclass 15, count 0 2006.285.18:11:37.43#ibcon#read 6, iclass 15, count 0 2006.285.18:11:37.43#ibcon#end of sib2, iclass 15, count 0 2006.285.18:11:37.43#ibcon#*mode == 0, iclass 15, count 0 2006.285.18:11:37.43#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.18:11:37.43#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.18:11:37.43#ibcon#*before write, iclass 15, count 0 2006.285.18:11:37.43#ibcon#enter sib2, iclass 15, count 0 2006.285.18:11:37.43#ibcon#flushed, iclass 15, count 0 2006.285.18:11:37.43#ibcon#about to write, iclass 15, count 0 2006.285.18:11:37.43#ibcon#wrote, iclass 15, count 0 2006.285.18:11:37.43#ibcon#about to read 3, iclass 15, count 0 2006.285.18:11:37.47#ibcon#read 3, iclass 15, count 0 2006.285.18:11:37.47#ibcon#about to read 4, iclass 15, count 0 2006.285.18:11:37.47#ibcon#read 4, iclass 15, count 0 2006.285.18:11:37.47#ibcon#about to read 5, iclass 15, count 0 2006.285.18:11:37.47#ibcon#read 5, iclass 15, count 0 2006.285.18:11:37.47#ibcon#about to read 6, iclass 15, count 0 2006.285.18:11:37.47#ibcon#read 6, iclass 15, count 0 2006.285.18:11:37.47#ibcon#end of sib2, iclass 15, count 0 2006.285.18:11:37.47#ibcon#*after write, iclass 15, count 0 2006.285.18:11:37.47#ibcon#*before return 0, iclass 15, count 0 2006.285.18:11:37.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:11:37.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:11:37.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.18:11:37.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.18:11:37.47$vck44/vb=7,4 2006.285.18:11:37.47#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.18:11:37.47#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.18:11:37.47#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:37.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:11:37.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:11:37.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:11:37.53#ibcon#enter wrdev, iclass 17, count 2 2006.285.18:11:37.53#ibcon#first serial, iclass 17, count 2 2006.285.18:11:37.53#ibcon#enter sib2, iclass 17, count 2 2006.285.18:11:37.53#ibcon#flushed, iclass 17, count 2 2006.285.18:11:37.53#ibcon#about to write, iclass 17, count 2 2006.285.18:11:37.53#ibcon#wrote, iclass 17, count 2 2006.285.18:11:37.53#ibcon#about to read 3, iclass 17, count 2 2006.285.18:11:37.55#ibcon#read 3, iclass 17, count 2 2006.285.18:11:37.55#ibcon#about to read 4, iclass 17, count 2 2006.285.18:11:37.55#ibcon#read 4, iclass 17, count 2 2006.285.18:11:37.55#ibcon#about to read 5, iclass 17, count 2 2006.285.18:11:37.55#ibcon#read 5, iclass 17, count 2 2006.285.18:11:37.55#ibcon#about to read 6, iclass 17, count 2 2006.285.18:11:37.55#ibcon#read 6, iclass 17, count 2 2006.285.18:11:37.55#ibcon#end of sib2, iclass 17, count 2 2006.285.18:11:37.55#ibcon#*mode == 0, iclass 17, count 2 2006.285.18:11:37.55#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.18:11:37.55#ibcon#[27=AT07-04\r\n] 2006.285.18:11:37.55#ibcon#*before write, iclass 17, count 2 2006.285.18:11:37.55#ibcon#enter sib2, iclass 17, count 2 2006.285.18:11:37.55#ibcon#flushed, iclass 17, count 2 2006.285.18:11:37.55#ibcon#about to write, iclass 17, count 2 2006.285.18:11:37.55#ibcon#wrote, iclass 17, count 2 2006.285.18:11:37.55#ibcon#about to read 3, iclass 17, count 2 2006.285.18:11:37.58#ibcon#read 3, iclass 17, count 2 2006.285.18:11:37.58#ibcon#about to read 4, iclass 17, count 2 2006.285.18:11:37.58#ibcon#read 4, iclass 17, count 2 2006.285.18:11:37.58#ibcon#about to read 5, iclass 17, count 2 2006.285.18:11:37.58#ibcon#read 5, iclass 17, count 2 2006.285.18:11:37.58#ibcon#about to read 6, iclass 17, count 2 2006.285.18:11:37.58#ibcon#read 6, iclass 17, count 2 2006.285.18:11:37.58#ibcon#end of sib2, iclass 17, count 2 2006.285.18:11:37.58#ibcon#*after write, iclass 17, count 2 2006.285.18:11:37.58#ibcon#*before return 0, iclass 17, count 2 2006.285.18:11:37.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:11:37.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:11:37.58#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.18:11:37.58#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:37.58#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:11:37.70#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:11:37.70#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:11:37.70#ibcon#enter wrdev, iclass 17, count 0 2006.285.18:11:37.70#ibcon#first serial, iclass 17, count 0 2006.285.18:11:37.70#ibcon#enter sib2, iclass 17, count 0 2006.285.18:11:37.70#ibcon#flushed, iclass 17, count 0 2006.285.18:11:37.70#ibcon#about to write, iclass 17, count 0 2006.285.18:11:37.70#ibcon#wrote, iclass 17, count 0 2006.285.18:11:37.70#ibcon#about to read 3, iclass 17, count 0 2006.285.18:11:37.72#ibcon#read 3, iclass 17, count 0 2006.285.18:11:37.72#ibcon#about to read 4, iclass 17, count 0 2006.285.18:11:37.72#ibcon#read 4, iclass 17, count 0 2006.285.18:11:37.72#ibcon#about to read 5, iclass 17, count 0 2006.285.18:11:37.72#ibcon#read 5, iclass 17, count 0 2006.285.18:11:37.72#ibcon#about to read 6, iclass 17, count 0 2006.285.18:11:37.72#ibcon#read 6, iclass 17, count 0 2006.285.18:11:37.72#ibcon#end of sib2, iclass 17, count 0 2006.285.18:11:37.72#ibcon#*mode == 0, iclass 17, count 0 2006.285.18:11:37.72#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.18:11:37.72#ibcon#[27=USB\r\n] 2006.285.18:11:37.72#ibcon#*before write, iclass 17, count 0 2006.285.18:11:37.72#ibcon#enter sib2, iclass 17, count 0 2006.285.18:11:37.72#ibcon#flushed, iclass 17, count 0 2006.285.18:11:37.72#ibcon#about to write, iclass 17, count 0 2006.285.18:11:37.72#ibcon#wrote, iclass 17, count 0 2006.285.18:11:37.72#ibcon#about to read 3, iclass 17, count 0 2006.285.18:11:37.75#ibcon#read 3, iclass 17, count 0 2006.285.18:11:37.75#ibcon#about to read 4, iclass 17, count 0 2006.285.18:11:37.75#ibcon#read 4, iclass 17, count 0 2006.285.18:11:37.75#ibcon#about to read 5, iclass 17, count 0 2006.285.18:11:37.75#ibcon#read 5, iclass 17, count 0 2006.285.18:11:37.75#ibcon#about to read 6, iclass 17, count 0 2006.285.18:11:37.75#ibcon#read 6, iclass 17, count 0 2006.285.18:11:37.75#ibcon#end of sib2, iclass 17, count 0 2006.285.18:11:37.75#ibcon#*after write, iclass 17, count 0 2006.285.18:11:37.75#ibcon#*before return 0, iclass 17, count 0 2006.285.18:11:37.75#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:11:37.75#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:11:37.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.18:11:37.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.18:11:37.75$vck44/vblo=8,744.99 2006.285.18:11:37.75#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.18:11:37.75#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.18:11:37.75#ibcon#ireg 17 cls_cnt 0 2006.285.18:11:37.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:11:37.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:11:37.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:11:37.75#ibcon#enter wrdev, iclass 19, count 0 2006.285.18:11:37.75#ibcon#first serial, iclass 19, count 0 2006.285.18:11:37.75#ibcon#enter sib2, iclass 19, count 0 2006.285.18:11:37.75#ibcon#flushed, iclass 19, count 0 2006.285.18:11:37.75#ibcon#about to write, iclass 19, count 0 2006.285.18:11:37.75#ibcon#wrote, iclass 19, count 0 2006.285.18:11:37.75#ibcon#about to read 3, iclass 19, count 0 2006.285.18:11:37.77#ibcon#read 3, iclass 19, count 0 2006.285.18:11:37.77#ibcon#about to read 4, iclass 19, count 0 2006.285.18:11:37.77#ibcon#read 4, iclass 19, count 0 2006.285.18:11:37.77#ibcon#about to read 5, iclass 19, count 0 2006.285.18:11:37.77#ibcon#read 5, iclass 19, count 0 2006.285.18:11:37.77#ibcon#about to read 6, iclass 19, count 0 2006.285.18:11:37.77#ibcon#read 6, iclass 19, count 0 2006.285.18:11:37.77#ibcon#end of sib2, iclass 19, count 0 2006.285.18:11:37.77#ibcon#*mode == 0, iclass 19, count 0 2006.285.18:11:37.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.18:11:37.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.18:11:37.77#ibcon#*before write, iclass 19, count 0 2006.285.18:11:37.77#ibcon#enter sib2, iclass 19, count 0 2006.285.18:11:37.77#ibcon#flushed, iclass 19, count 0 2006.285.18:11:37.77#ibcon#about to write, iclass 19, count 0 2006.285.18:11:37.77#ibcon#wrote, iclass 19, count 0 2006.285.18:11:37.77#ibcon#about to read 3, iclass 19, count 0 2006.285.18:11:37.81#ibcon#read 3, iclass 19, count 0 2006.285.18:11:37.81#ibcon#about to read 4, iclass 19, count 0 2006.285.18:11:37.81#ibcon#read 4, iclass 19, count 0 2006.285.18:11:37.81#ibcon#about to read 5, iclass 19, count 0 2006.285.18:11:37.81#ibcon#read 5, iclass 19, count 0 2006.285.18:11:37.81#ibcon#about to read 6, iclass 19, count 0 2006.285.18:11:37.81#ibcon#read 6, iclass 19, count 0 2006.285.18:11:37.81#ibcon#end of sib2, iclass 19, count 0 2006.285.18:11:37.81#ibcon#*after write, iclass 19, count 0 2006.285.18:11:37.81#ibcon#*before return 0, iclass 19, count 0 2006.285.18:11:37.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:11:37.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:11:37.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.18:11:37.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.18:11:37.81$vck44/vb=8,4 2006.285.18:11:37.81#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.18:11:37.81#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.18:11:37.81#ibcon#ireg 11 cls_cnt 2 2006.285.18:11:37.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:11:37.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:11:37.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:11:37.87#ibcon#enter wrdev, iclass 21, count 2 2006.285.18:11:37.87#ibcon#first serial, iclass 21, count 2 2006.285.18:11:37.87#ibcon#enter sib2, iclass 21, count 2 2006.285.18:11:37.87#ibcon#flushed, iclass 21, count 2 2006.285.18:11:37.87#ibcon#about to write, iclass 21, count 2 2006.285.18:11:37.87#ibcon#wrote, iclass 21, count 2 2006.285.18:11:37.87#ibcon#about to read 3, iclass 21, count 2 2006.285.18:11:37.89#ibcon#read 3, iclass 21, count 2 2006.285.18:11:37.89#ibcon#about to read 4, iclass 21, count 2 2006.285.18:11:37.89#ibcon#read 4, iclass 21, count 2 2006.285.18:11:37.89#ibcon#about to read 5, iclass 21, count 2 2006.285.18:11:37.89#ibcon#read 5, iclass 21, count 2 2006.285.18:11:37.89#ibcon#about to read 6, iclass 21, count 2 2006.285.18:11:37.89#ibcon#read 6, iclass 21, count 2 2006.285.18:11:37.89#ibcon#end of sib2, iclass 21, count 2 2006.285.18:11:37.89#ibcon#*mode == 0, iclass 21, count 2 2006.285.18:11:37.89#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.18:11:37.89#ibcon#[27=AT08-04\r\n] 2006.285.18:11:37.89#ibcon#*before write, iclass 21, count 2 2006.285.18:11:37.89#ibcon#enter sib2, iclass 21, count 2 2006.285.18:11:37.89#ibcon#flushed, iclass 21, count 2 2006.285.18:11:37.89#ibcon#about to write, iclass 21, count 2 2006.285.18:11:37.89#ibcon#wrote, iclass 21, count 2 2006.285.18:11:37.89#ibcon#about to read 3, iclass 21, count 2 2006.285.18:11:37.92#ibcon#read 3, iclass 21, count 2 2006.285.18:11:37.92#ibcon#about to read 4, iclass 21, count 2 2006.285.18:11:37.92#ibcon#read 4, iclass 21, count 2 2006.285.18:11:37.92#ibcon#about to read 5, iclass 21, count 2 2006.285.18:11:37.92#ibcon#read 5, iclass 21, count 2 2006.285.18:11:37.92#ibcon#about to read 6, iclass 21, count 2 2006.285.18:11:37.92#ibcon#read 6, iclass 21, count 2 2006.285.18:11:37.92#ibcon#end of sib2, iclass 21, count 2 2006.285.18:11:37.92#ibcon#*after write, iclass 21, count 2 2006.285.18:11:37.92#ibcon#*before return 0, iclass 21, count 2 2006.285.18:11:37.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:11:37.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:11:37.92#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.18:11:37.92#ibcon#ireg 7 cls_cnt 0 2006.285.18:11:37.92#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:11:38.04#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:11:38.04#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:11:38.04#ibcon#enter wrdev, iclass 21, count 0 2006.285.18:11:38.04#ibcon#first serial, iclass 21, count 0 2006.285.18:11:38.04#ibcon#enter sib2, iclass 21, count 0 2006.285.18:11:38.04#ibcon#flushed, iclass 21, count 0 2006.285.18:11:38.04#ibcon#about to write, iclass 21, count 0 2006.285.18:11:38.04#ibcon#wrote, iclass 21, count 0 2006.285.18:11:38.04#ibcon#about to read 3, iclass 21, count 0 2006.285.18:11:38.06#ibcon#read 3, iclass 21, count 0 2006.285.18:11:38.06#ibcon#about to read 4, iclass 21, count 0 2006.285.18:11:38.06#ibcon#read 4, iclass 21, count 0 2006.285.18:11:38.06#ibcon#about to read 5, iclass 21, count 0 2006.285.18:11:38.06#ibcon#read 5, iclass 21, count 0 2006.285.18:11:38.06#ibcon#about to read 6, iclass 21, count 0 2006.285.18:11:38.06#ibcon#read 6, iclass 21, count 0 2006.285.18:11:38.06#ibcon#end of sib2, iclass 21, count 0 2006.285.18:11:38.06#ibcon#*mode == 0, iclass 21, count 0 2006.285.18:11:38.06#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.18:11:38.06#ibcon#[27=USB\r\n] 2006.285.18:11:38.06#ibcon#*before write, iclass 21, count 0 2006.285.18:11:38.06#ibcon#enter sib2, iclass 21, count 0 2006.285.18:11:38.06#ibcon#flushed, iclass 21, count 0 2006.285.18:11:38.06#ibcon#about to write, iclass 21, count 0 2006.285.18:11:38.06#ibcon#wrote, iclass 21, count 0 2006.285.18:11:38.06#ibcon#about to read 3, iclass 21, count 0 2006.285.18:11:38.09#ibcon#read 3, iclass 21, count 0 2006.285.18:11:38.09#ibcon#about to read 4, iclass 21, count 0 2006.285.18:11:38.09#ibcon#read 4, iclass 21, count 0 2006.285.18:11:38.09#ibcon#about to read 5, iclass 21, count 0 2006.285.18:11:38.09#ibcon#read 5, iclass 21, count 0 2006.285.18:11:38.09#ibcon#about to read 6, iclass 21, count 0 2006.285.18:11:38.09#ibcon#read 6, iclass 21, count 0 2006.285.18:11:38.09#ibcon#end of sib2, iclass 21, count 0 2006.285.18:11:38.09#ibcon#*after write, iclass 21, count 0 2006.285.18:11:38.09#ibcon#*before return 0, iclass 21, count 0 2006.285.18:11:38.09#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:11:38.09#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:11:38.09#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.18:11:38.09#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.18:11:38.09$vck44/vabw=wide 2006.285.18:11:38.09#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.18:11:38.09#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.18:11:38.09#ibcon#ireg 8 cls_cnt 0 2006.285.18:11:38.09#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:11:38.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:11:38.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:11:38.09#ibcon#enter wrdev, iclass 23, count 0 2006.285.18:11:38.09#ibcon#first serial, iclass 23, count 0 2006.285.18:11:38.09#ibcon#enter sib2, iclass 23, count 0 2006.285.18:11:38.09#ibcon#flushed, iclass 23, count 0 2006.285.18:11:38.09#ibcon#about to write, iclass 23, count 0 2006.285.18:11:38.09#ibcon#wrote, iclass 23, count 0 2006.285.18:11:38.09#ibcon#about to read 3, iclass 23, count 0 2006.285.18:11:38.11#ibcon#read 3, iclass 23, count 0 2006.285.18:11:38.11#ibcon#about to read 4, iclass 23, count 0 2006.285.18:11:38.11#ibcon#read 4, iclass 23, count 0 2006.285.18:11:38.11#ibcon#about to read 5, iclass 23, count 0 2006.285.18:11:38.11#ibcon#read 5, iclass 23, count 0 2006.285.18:11:38.11#ibcon#about to read 6, iclass 23, count 0 2006.285.18:11:38.11#ibcon#read 6, iclass 23, count 0 2006.285.18:11:38.11#ibcon#end of sib2, iclass 23, count 0 2006.285.18:11:38.11#ibcon#*mode == 0, iclass 23, count 0 2006.285.18:11:38.11#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.18:11:38.11#ibcon#[25=BW32\r\n] 2006.285.18:11:38.11#ibcon#*before write, iclass 23, count 0 2006.285.18:11:38.11#ibcon#enter sib2, iclass 23, count 0 2006.285.18:11:38.11#ibcon#flushed, iclass 23, count 0 2006.285.18:11:38.11#ibcon#about to write, iclass 23, count 0 2006.285.18:11:38.11#ibcon#wrote, iclass 23, count 0 2006.285.18:11:38.11#ibcon#about to read 3, iclass 23, count 0 2006.285.18:11:38.14#ibcon#read 3, iclass 23, count 0 2006.285.18:11:38.14#ibcon#about to read 4, iclass 23, count 0 2006.285.18:11:38.14#ibcon#read 4, iclass 23, count 0 2006.285.18:11:38.14#ibcon#about to read 5, iclass 23, count 0 2006.285.18:11:38.14#ibcon#read 5, iclass 23, count 0 2006.285.18:11:38.14#ibcon#about to read 6, iclass 23, count 0 2006.285.18:11:38.14#ibcon#read 6, iclass 23, count 0 2006.285.18:11:38.14#ibcon#end of sib2, iclass 23, count 0 2006.285.18:11:38.14#ibcon#*after write, iclass 23, count 0 2006.285.18:11:38.14#ibcon#*before return 0, iclass 23, count 0 2006.285.18:11:38.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:11:38.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:11:38.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.18:11:38.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.18:11:38.14$vck44/vbbw=wide 2006.285.18:11:38.14#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.18:11:38.14#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.18:11:38.14#ibcon#ireg 8 cls_cnt 0 2006.285.18:11:38.14#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.18:11:38.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.18:11:38.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.18:11:38.21#ibcon#enter wrdev, iclass 25, count 0 2006.285.18:11:38.21#ibcon#first serial, iclass 25, count 0 2006.285.18:11:38.21#ibcon#enter sib2, iclass 25, count 0 2006.285.18:11:38.21#ibcon#flushed, iclass 25, count 0 2006.285.18:11:38.21#ibcon#about to write, iclass 25, count 0 2006.285.18:11:38.21#ibcon#wrote, iclass 25, count 0 2006.285.18:11:38.21#ibcon#about to read 3, iclass 25, count 0 2006.285.18:11:38.23#ibcon#read 3, iclass 25, count 0 2006.285.18:11:38.23#ibcon#about to read 4, iclass 25, count 0 2006.285.18:11:38.23#ibcon#read 4, iclass 25, count 0 2006.285.18:11:38.23#ibcon#about to read 5, iclass 25, count 0 2006.285.18:11:38.23#ibcon#read 5, iclass 25, count 0 2006.285.18:11:38.23#ibcon#about to read 6, iclass 25, count 0 2006.285.18:11:38.23#ibcon#read 6, iclass 25, count 0 2006.285.18:11:38.23#ibcon#end of sib2, iclass 25, count 0 2006.285.18:11:38.23#ibcon#*mode == 0, iclass 25, count 0 2006.285.18:11:38.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.18:11:38.23#ibcon#[27=BW32\r\n] 2006.285.18:11:38.23#ibcon#*before write, iclass 25, count 0 2006.285.18:11:38.23#ibcon#enter sib2, iclass 25, count 0 2006.285.18:11:38.23#ibcon#flushed, iclass 25, count 0 2006.285.18:11:38.23#ibcon#about to write, iclass 25, count 0 2006.285.18:11:38.23#ibcon#wrote, iclass 25, count 0 2006.285.18:11:38.23#ibcon#about to read 3, iclass 25, count 0 2006.285.18:11:38.26#ibcon#read 3, iclass 25, count 0 2006.285.18:11:38.26#ibcon#about to read 4, iclass 25, count 0 2006.285.18:11:38.26#ibcon#read 4, iclass 25, count 0 2006.285.18:11:38.26#ibcon#about to read 5, iclass 25, count 0 2006.285.18:11:38.26#ibcon#read 5, iclass 25, count 0 2006.285.18:11:38.26#ibcon#about to read 6, iclass 25, count 0 2006.285.18:11:38.26#ibcon#read 6, iclass 25, count 0 2006.285.18:11:38.26#ibcon#end of sib2, iclass 25, count 0 2006.285.18:11:38.26#ibcon#*after write, iclass 25, count 0 2006.285.18:11:38.26#ibcon#*before return 0, iclass 25, count 0 2006.285.18:11:38.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.18:11:38.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.18:11:38.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.18:11:38.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.18:11:38.26$setupk4/ifdk4 2006.285.18:11:38.26$ifdk4/lo= 2006.285.18:11:38.26$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.18:11:38.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.18:11:38.26$ifdk4/patch= 2006.285.18:11:38.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.18:11:38.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.18:11:38.26$setupk4/!*+20s 2006.285.18:11:43.23#abcon#<5=/13 0.7 1.5 15.821001014.5\r\n> 2006.285.18:11:43.25#abcon#{5=INTERFACE CLEAR} 2006.285.18:11:43.31#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:11:46.14#trakl#Source acquired 2006.285.18:11:48.14#flagr#flagr/antenna,acquired 2006.285.18:11:52.12$setupk4/"tpicd 2006.285.18:11:52.12$setupk4/echo=off 2006.285.18:11:52.12$setupk4/xlog=off 2006.285.18:11:52.12:!2006.285.18:14:07 2006.285.18:14:07.00:preob 2006.285.18:14:07.14/onsource/TRACKING 2006.285.18:14:07.14:!2006.285.18:14:17 2006.285.18:14:17.00:"tape 2006.285.18:14:17.00:"st=record 2006.285.18:14:17.00:data_valid=on 2006.285.18:14:17.00:midob 2006.285.18:14:18.14/onsource/TRACKING 2006.285.18:14:18.14/wx/15.77,1014.5,100 2006.285.18:14:18.19/cable/+6.5046E-03 2006.285.18:14:19.28/va/01,07,usb,yes,33,36 2006.285.18:14:19.28/va/02,06,usb,yes,33,34 2006.285.18:14:19.28/va/03,07,usb,yes,33,35 2006.285.18:14:19.28/va/04,06,usb,yes,34,36 2006.285.18:14:19.28/va/05,03,usb,yes,34,34 2006.285.18:14:19.28/va/06,04,usb,yes,30,30 2006.285.18:14:19.28/va/07,04,usb,yes,31,32 2006.285.18:14:19.28/va/08,03,usb,yes,32,38 2006.285.18:14:19.51/valo/01,524.99,yes,locked 2006.285.18:14:19.51/valo/02,534.99,yes,locked 2006.285.18:14:19.51/valo/03,564.99,yes,locked 2006.285.18:14:19.51/valo/04,624.99,yes,locked 2006.285.18:14:19.51/valo/05,734.99,yes,locked 2006.285.18:14:19.51/valo/06,814.99,yes,locked 2006.285.18:14:19.51/valo/07,864.99,yes,locked 2006.285.18:14:19.51/valo/08,884.99,yes,locked 2006.285.18:14:20.60/vb/01,04,usb,yes,31,29 2006.285.18:14:20.60/vb/02,05,usb,yes,29,29 2006.285.18:14:20.60/vb/03,04,usb,yes,30,33 2006.285.18:14:20.60/vb/04,05,usb,yes,30,29 2006.285.18:14:20.60/vb/05,04,usb,yes,27,29 2006.285.18:14:20.60/vb/06,03,usb,yes,39,34 2006.285.18:14:20.60/vb/07,04,usb,yes,31,31 2006.285.18:14:20.60/vb/08,04,usb,yes,28,32 2006.285.18:14:20.83/vblo/01,629.99,yes,locked 2006.285.18:14:20.83/vblo/02,634.99,yes,locked 2006.285.18:14:20.83/vblo/03,649.99,yes,locked 2006.285.18:14:20.83/vblo/04,679.99,yes,locked 2006.285.18:14:20.83/vblo/05,709.99,yes,locked 2006.285.18:14:20.83/vblo/06,719.99,yes,locked 2006.285.18:14:20.83/vblo/07,734.99,yes,locked 2006.285.18:14:20.83/vblo/08,744.99,yes,locked 2006.285.18:14:20.98/vabw/8 2006.285.18:14:21.13/vbbw/8 2006.285.18:14:21.25/xfe/off,on,12.2 2006.285.18:14:21.63/ifatt/23,28,28,28 2006.285.18:14:22.08/fmout-gps/S +2.84E-07 2006.285.18:14:22.10:!2006.285.18:18:37 2006.285.18:18:37.01:data_valid=off 2006.285.18:18:37.01:"et 2006.285.18:18:37.01:!+3s 2006.285.18:18:40.02:"tape 2006.285.18:18:40.02:postob 2006.285.18:18:40.20/cable/+6.5060E-03 2006.285.18:18:40.20/wx/15.67,1014.5,100 2006.285.18:18:41.08/fmout-gps/S +2.82E-07 2006.285.18:18:41.08:scan_name=285-1828,jd0610,50 2006.285.18:18:41.08:source=0552+398,055530.81,394849.2,2000.0,cw 2006.285.18:18:42.13#flagr#flagr/antenna,new-source 2006.285.18:18:42.13:checkk5 2006.285.18:18:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.18:18:43.08/chk_autoobs//k5ts2/ autoobs is running! 2006.285.18:18:43.54/chk_autoobs//k5ts3/ autoobs is running! 2006.285.18:18:43.99/chk_autoobs//k5ts4/ autoobs is running! 2006.285.18:18:44.32/chk_obsdata//k5ts1/T2851814??a.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.285.18:18:44.71/chk_obsdata//k5ts2/T2851814??b.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.285.18:18:45.33/chk_obsdata//k5ts3/T2851814??c.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.285.18:18:45.74/chk_obsdata//k5ts4/T2851814??d.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.285.18:18:46.77/k5log//k5ts1_log_newline 2006.285.18:18:47.62/k5log//k5ts2_log_newline 2006.285.18:18:48.46/k5log//k5ts3_log_newline 2006.285.18:18:49.24/k5log//k5ts4_log_newline 2006.285.18:18:49.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.18:18:49.26:setupk4=1 2006.285.18:18:49.26$setupk4/echo=on 2006.285.18:18:49.26$setupk4/pcalon 2006.285.18:18:49.26$pcalon/"no phase cal control is implemented here 2006.285.18:18:49.26$setupk4/"tpicd=stop 2006.285.18:18:49.26$setupk4/"rec=synch_on 2006.285.18:18:49.26$setupk4/"rec_mode=128 2006.285.18:18:49.26$setupk4/!* 2006.285.18:18:49.26$setupk4/recpk4 2006.285.18:18:49.26$recpk4/recpatch= 2006.285.18:18:49.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.18:18:49.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.18:18:49.26$setupk4/vck44 2006.285.18:18:49.26$vck44/valo=1,524.99 2006.285.18:18:49.26#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.18:18:49.26#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.18:18:49.26#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:49.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:18:49.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:18:49.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:18:49.26#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:18:49.26#ibcon#first serial, iclass 18, count 0 2006.285.18:18:49.26#ibcon#enter sib2, iclass 18, count 0 2006.285.18:18:49.26#ibcon#flushed, iclass 18, count 0 2006.285.18:18:49.26#ibcon#about to write, iclass 18, count 0 2006.285.18:18:49.26#ibcon#wrote, iclass 18, count 0 2006.285.18:18:49.26#ibcon#about to read 3, iclass 18, count 0 2006.285.18:18:49.28#ibcon#read 3, iclass 18, count 0 2006.285.18:18:49.28#ibcon#about to read 4, iclass 18, count 0 2006.285.18:18:49.28#ibcon#read 4, iclass 18, count 0 2006.285.18:18:49.28#ibcon#about to read 5, iclass 18, count 0 2006.285.18:18:49.28#ibcon#read 5, iclass 18, count 0 2006.285.18:18:49.28#ibcon#about to read 6, iclass 18, count 0 2006.285.18:18:49.28#ibcon#read 6, iclass 18, count 0 2006.285.18:18:49.28#ibcon#end of sib2, iclass 18, count 0 2006.285.18:18:49.28#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:18:49.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:18:49.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.18:18:49.28#ibcon#*before write, iclass 18, count 0 2006.285.18:18:49.28#ibcon#enter sib2, iclass 18, count 0 2006.285.18:18:49.28#ibcon#flushed, iclass 18, count 0 2006.285.18:18:49.28#ibcon#about to write, iclass 18, count 0 2006.285.18:18:49.28#ibcon#wrote, iclass 18, count 0 2006.285.18:18:49.28#ibcon#about to read 3, iclass 18, count 0 2006.285.18:18:49.33#ibcon#read 3, iclass 18, count 0 2006.285.18:18:49.33#ibcon#about to read 4, iclass 18, count 0 2006.285.18:18:49.33#ibcon#read 4, iclass 18, count 0 2006.285.18:18:49.33#ibcon#about to read 5, iclass 18, count 0 2006.285.18:18:49.33#ibcon#read 5, iclass 18, count 0 2006.285.18:18:49.33#ibcon#about to read 6, iclass 18, count 0 2006.285.18:18:49.33#ibcon#read 6, iclass 18, count 0 2006.285.18:18:49.33#ibcon#end of sib2, iclass 18, count 0 2006.285.18:18:49.33#ibcon#*after write, iclass 18, count 0 2006.285.18:18:49.33#ibcon#*before return 0, iclass 18, count 0 2006.285.18:18:49.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:18:49.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:18:49.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:18:49.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:18:49.33$vck44/va=1,7 2006.285.18:18:49.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.18:18:49.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.18:18:49.33#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:49.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:18:49.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:18:49.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:18:49.33#ibcon#enter wrdev, iclass 20, count 2 2006.285.18:18:49.33#ibcon#first serial, iclass 20, count 2 2006.285.18:18:49.33#ibcon#enter sib2, iclass 20, count 2 2006.285.18:18:49.33#ibcon#flushed, iclass 20, count 2 2006.285.18:18:49.33#ibcon#about to write, iclass 20, count 2 2006.285.18:18:49.33#ibcon#wrote, iclass 20, count 2 2006.285.18:18:49.33#ibcon#about to read 3, iclass 20, count 2 2006.285.18:18:49.35#ibcon#read 3, iclass 20, count 2 2006.285.18:18:49.35#ibcon#about to read 4, iclass 20, count 2 2006.285.18:18:49.35#ibcon#read 4, iclass 20, count 2 2006.285.18:18:49.35#ibcon#about to read 5, iclass 20, count 2 2006.285.18:18:49.35#ibcon#read 5, iclass 20, count 2 2006.285.18:18:49.35#ibcon#about to read 6, iclass 20, count 2 2006.285.18:18:49.35#ibcon#read 6, iclass 20, count 2 2006.285.18:18:49.35#ibcon#end of sib2, iclass 20, count 2 2006.285.18:18:49.35#ibcon#*mode == 0, iclass 20, count 2 2006.285.18:18:49.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.18:18:49.35#ibcon#[25=AT01-07\r\n] 2006.285.18:18:49.35#ibcon#*before write, iclass 20, count 2 2006.285.18:18:49.35#ibcon#enter sib2, iclass 20, count 2 2006.285.18:18:49.35#ibcon#flushed, iclass 20, count 2 2006.285.18:18:49.35#ibcon#about to write, iclass 20, count 2 2006.285.18:18:49.35#ibcon#wrote, iclass 20, count 2 2006.285.18:18:49.35#ibcon#about to read 3, iclass 20, count 2 2006.285.18:18:49.38#ibcon#read 3, iclass 20, count 2 2006.285.18:18:49.38#ibcon#about to read 4, iclass 20, count 2 2006.285.18:18:49.38#ibcon#read 4, iclass 20, count 2 2006.285.18:18:49.38#ibcon#about to read 5, iclass 20, count 2 2006.285.18:18:49.38#ibcon#read 5, iclass 20, count 2 2006.285.18:18:49.38#ibcon#about to read 6, iclass 20, count 2 2006.285.18:18:49.38#ibcon#read 6, iclass 20, count 2 2006.285.18:18:49.38#ibcon#end of sib2, iclass 20, count 2 2006.285.18:18:49.38#ibcon#*after write, iclass 20, count 2 2006.285.18:18:49.38#ibcon#*before return 0, iclass 20, count 2 2006.285.18:18:49.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:18:49.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:18:49.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.18:18:49.38#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:49.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:18:49.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:18:49.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:18:49.50#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:18:49.50#ibcon#first serial, iclass 20, count 0 2006.285.18:18:49.50#ibcon#enter sib2, iclass 20, count 0 2006.285.18:18:49.50#ibcon#flushed, iclass 20, count 0 2006.285.18:18:49.50#ibcon#about to write, iclass 20, count 0 2006.285.18:18:49.50#ibcon#wrote, iclass 20, count 0 2006.285.18:18:49.50#ibcon#about to read 3, iclass 20, count 0 2006.285.18:18:49.52#ibcon#read 3, iclass 20, count 0 2006.285.18:18:49.52#ibcon#about to read 4, iclass 20, count 0 2006.285.18:18:49.52#ibcon#read 4, iclass 20, count 0 2006.285.18:18:49.52#ibcon#about to read 5, iclass 20, count 0 2006.285.18:18:49.52#ibcon#read 5, iclass 20, count 0 2006.285.18:18:49.52#ibcon#about to read 6, iclass 20, count 0 2006.285.18:18:49.52#ibcon#read 6, iclass 20, count 0 2006.285.18:18:49.52#ibcon#end of sib2, iclass 20, count 0 2006.285.18:18:49.52#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:18:49.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:18:49.52#ibcon#[25=USB\r\n] 2006.285.18:18:49.52#ibcon#*before write, iclass 20, count 0 2006.285.18:18:49.52#ibcon#enter sib2, iclass 20, count 0 2006.285.18:18:49.52#ibcon#flushed, iclass 20, count 0 2006.285.18:18:49.52#ibcon#about to write, iclass 20, count 0 2006.285.18:18:49.52#ibcon#wrote, iclass 20, count 0 2006.285.18:18:49.52#ibcon#about to read 3, iclass 20, count 0 2006.285.18:18:49.55#ibcon#read 3, iclass 20, count 0 2006.285.18:18:49.55#ibcon#about to read 4, iclass 20, count 0 2006.285.18:18:49.55#ibcon#read 4, iclass 20, count 0 2006.285.18:18:49.55#ibcon#about to read 5, iclass 20, count 0 2006.285.18:18:49.55#ibcon#read 5, iclass 20, count 0 2006.285.18:18:49.55#ibcon#about to read 6, iclass 20, count 0 2006.285.18:18:49.55#ibcon#read 6, iclass 20, count 0 2006.285.18:18:49.55#ibcon#end of sib2, iclass 20, count 0 2006.285.18:18:49.55#ibcon#*after write, iclass 20, count 0 2006.285.18:18:49.55#ibcon#*before return 0, iclass 20, count 0 2006.285.18:18:49.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:18:49.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:18:49.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:18:49.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:18:49.55$vck44/valo=2,534.99 2006.285.18:18:49.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.18:18:49.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.18:18:49.55#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:49.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:18:49.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:18:49.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:18:49.55#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:18:49.55#ibcon#first serial, iclass 22, count 0 2006.285.18:18:49.55#ibcon#enter sib2, iclass 22, count 0 2006.285.18:18:49.55#ibcon#flushed, iclass 22, count 0 2006.285.18:18:49.55#ibcon#about to write, iclass 22, count 0 2006.285.18:18:49.55#ibcon#wrote, iclass 22, count 0 2006.285.18:18:49.55#ibcon#about to read 3, iclass 22, count 0 2006.285.18:18:49.57#ibcon#read 3, iclass 22, count 0 2006.285.18:18:49.57#ibcon#about to read 4, iclass 22, count 0 2006.285.18:18:49.57#ibcon#read 4, iclass 22, count 0 2006.285.18:18:49.57#ibcon#about to read 5, iclass 22, count 0 2006.285.18:18:49.57#ibcon#read 5, iclass 22, count 0 2006.285.18:18:49.57#ibcon#about to read 6, iclass 22, count 0 2006.285.18:18:49.57#ibcon#read 6, iclass 22, count 0 2006.285.18:18:49.57#ibcon#end of sib2, iclass 22, count 0 2006.285.18:18:49.57#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:18:49.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:18:49.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.18:18:49.57#ibcon#*before write, iclass 22, count 0 2006.285.18:18:49.57#ibcon#enter sib2, iclass 22, count 0 2006.285.18:18:49.57#ibcon#flushed, iclass 22, count 0 2006.285.18:18:49.57#ibcon#about to write, iclass 22, count 0 2006.285.18:18:49.57#ibcon#wrote, iclass 22, count 0 2006.285.18:18:49.57#ibcon#about to read 3, iclass 22, count 0 2006.285.18:18:49.61#ibcon#read 3, iclass 22, count 0 2006.285.18:18:49.61#ibcon#about to read 4, iclass 22, count 0 2006.285.18:18:49.61#ibcon#read 4, iclass 22, count 0 2006.285.18:18:49.61#ibcon#about to read 5, iclass 22, count 0 2006.285.18:18:49.61#ibcon#read 5, iclass 22, count 0 2006.285.18:18:49.61#ibcon#about to read 6, iclass 22, count 0 2006.285.18:18:49.61#ibcon#read 6, iclass 22, count 0 2006.285.18:18:49.61#ibcon#end of sib2, iclass 22, count 0 2006.285.18:18:49.61#ibcon#*after write, iclass 22, count 0 2006.285.18:18:49.61#ibcon#*before return 0, iclass 22, count 0 2006.285.18:18:49.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:18:49.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:18:49.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:18:49.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:18:49.61$vck44/va=2,6 2006.285.18:18:49.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.18:18:49.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.18:18:49.61#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:49.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:18:49.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:18:49.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:18:49.67#ibcon#enter wrdev, iclass 24, count 2 2006.285.18:18:49.67#ibcon#first serial, iclass 24, count 2 2006.285.18:18:49.67#ibcon#enter sib2, iclass 24, count 2 2006.285.18:18:49.67#ibcon#flushed, iclass 24, count 2 2006.285.18:18:49.67#ibcon#about to write, iclass 24, count 2 2006.285.18:18:49.67#ibcon#wrote, iclass 24, count 2 2006.285.18:18:49.67#ibcon#about to read 3, iclass 24, count 2 2006.285.18:18:49.69#ibcon#read 3, iclass 24, count 2 2006.285.18:18:49.69#ibcon#about to read 4, iclass 24, count 2 2006.285.18:18:49.69#ibcon#read 4, iclass 24, count 2 2006.285.18:18:49.69#ibcon#about to read 5, iclass 24, count 2 2006.285.18:18:49.69#ibcon#read 5, iclass 24, count 2 2006.285.18:18:49.69#ibcon#about to read 6, iclass 24, count 2 2006.285.18:18:49.69#ibcon#read 6, iclass 24, count 2 2006.285.18:18:49.69#ibcon#end of sib2, iclass 24, count 2 2006.285.18:18:49.69#ibcon#*mode == 0, iclass 24, count 2 2006.285.18:18:49.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.18:18:49.69#ibcon#[25=AT02-06\r\n] 2006.285.18:18:49.69#ibcon#*before write, iclass 24, count 2 2006.285.18:18:49.69#ibcon#enter sib2, iclass 24, count 2 2006.285.18:18:49.69#ibcon#flushed, iclass 24, count 2 2006.285.18:18:49.69#ibcon#about to write, iclass 24, count 2 2006.285.18:18:49.69#ibcon#wrote, iclass 24, count 2 2006.285.18:18:49.69#ibcon#about to read 3, iclass 24, count 2 2006.285.18:18:49.72#ibcon#read 3, iclass 24, count 2 2006.285.18:18:49.72#ibcon#about to read 4, iclass 24, count 2 2006.285.18:18:49.72#ibcon#read 4, iclass 24, count 2 2006.285.18:18:49.72#ibcon#about to read 5, iclass 24, count 2 2006.285.18:18:49.72#ibcon#read 5, iclass 24, count 2 2006.285.18:18:49.72#ibcon#about to read 6, iclass 24, count 2 2006.285.18:18:49.72#ibcon#read 6, iclass 24, count 2 2006.285.18:18:49.72#ibcon#end of sib2, iclass 24, count 2 2006.285.18:18:49.72#ibcon#*after write, iclass 24, count 2 2006.285.18:18:49.72#ibcon#*before return 0, iclass 24, count 2 2006.285.18:18:49.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:18:49.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:18:49.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.18:18:49.72#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:49.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:18:49.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:18:49.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:18:49.84#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:18:49.84#ibcon#first serial, iclass 24, count 0 2006.285.18:18:49.84#ibcon#enter sib2, iclass 24, count 0 2006.285.18:18:49.84#ibcon#flushed, iclass 24, count 0 2006.285.18:18:49.84#ibcon#about to write, iclass 24, count 0 2006.285.18:18:49.84#ibcon#wrote, iclass 24, count 0 2006.285.18:18:49.84#ibcon#about to read 3, iclass 24, count 0 2006.285.18:18:49.86#ibcon#read 3, iclass 24, count 0 2006.285.18:18:49.86#ibcon#about to read 4, iclass 24, count 0 2006.285.18:18:49.86#ibcon#read 4, iclass 24, count 0 2006.285.18:18:49.86#ibcon#about to read 5, iclass 24, count 0 2006.285.18:18:49.86#ibcon#read 5, iclass 24, count 0 2006.285.18:18:49.86#ibcon#about to read 6, iclass 24, count 0 2006.285.18:18:49.86#ibcon#read 6, iclass 24, count 0 2006.285.18:18:49.86#ibcon#end of sib2, iclass 24, count 0 2006.285.18:18:49.86#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:18:49.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:18:49.86#ibcon#[25=USB\r\n] 2006.285.18:18:49.86#ibcon#*before write, iclass 24, count 0 2006.285.18:18:49.86#ibcon#enter sib2, iclass 24, count 0 2006.285.18:18:49.86#ibcon#flushed, iclass 24, count 0 2006.285.18:18:49.86#ibcon#about to write, iclass 24, count 0 2006.285.18:18:49.86#ibcon#wrote, iclass 24, count 0 2006.285.18:18:49.86#ibcon#about to read 3, iclass 24, count 0 2006.285.18:18:49.89#ibcon#read 3, iclass 24, count 0 2006.285.18:18:49.89#ibcon#about to read 4, iclass 24, count 0 2006.285.18:18:49.89#ibcon#read 4, iclass 24, count 0 2006.285.18:18:49.89#ibcon#about to read 5, iclass 24, count 0 2006.285.18:18:49.89#ibcon#read 5, iclass 24, count 0 2006.285.18:18:49.89#ibcon#about to read 6, iclass 24, count 0 2006.285.18:18:49.89#ibcon#read 6, iclass 24, count 0 2006.285.18:18:49.89#ibcon#end of sib2, iclass 24, count 0 2006.285.18:18:49.89#ibcon#*after write, iclass 24, count 0 2006.285.18:18:49.89#ibcon#*before return 0, iclass 24, count 0 2006.285.18:18:49.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:18:49.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:18:49.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:18:49.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:18:49.89$vck44/valo=3,564.99 2006.285.18:18:49.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.18:18:49.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.18:18:49.89#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:49.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:18:49.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:18:49.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:18:49.89#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:18:49.89#ibcon#first serial, iclass 26, count 0 2006.285.18:18:49.89#ibcon#enter sib2, iclass 26, count 0 2006.285.18:18:49.89#ibcon#flushed, iclass 26, count 0 2006.285.18:18:49.89#ibcon#about to write, iclass 26, count 0 2006.285.18:18:49.89#ibcon#wrote, iclass 26, count 0 2006.285.18:18:49.89#ibcon#about to read 3, iclass 26, count 0 2006.285.18:18:49.91#ibcon#read 3, iclass 26, count 0 2006.285.18:18:50.53#ibcon#about to read 4, iclass 26, count 0 2006.285.18:18:50.53#ibcon#read 4, iclass 26, count 0 2006.285.18:18:50.53#ibcon#about to read 5, iclass 26, count 0 2006.285.18:18:50.53#ibcon#read 5, iclass 26, count 0 2006.285.18:18:50.53#ibcon#about to read 6, iclass 26, count 0 2006.285.18:18:50.53#ibcon#read 6, iclass 26, count 0 2006.285.18:18:50.53#ibcon#end of sib2, iclass 26, count 0 2006.285.18:18:50.53#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:18:50.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:18:50.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.18:18:50.53#ibcon#*before write, iclass 26, count 0 2006.285.18:18:50.53#ibcon#enter sib2, iclass 26, count 0 2006.285.18:18:50.53#ibcon#flushed, iclass 26, count 0 2006.285.18:18:50.53#ibcon#about to write, iclass 26, count 0 2006.285.18:18:50.53#ibcon#wrote, iclass 26, count 0 2006.285.18:18:50.53#ibcon#about to read 3, iclass 26, count 0 2006.285.18:18:50.57#ibcon#read 3, iclass 26, count 0 2006.285.18:18:50.57#ibcon#about to read 4, iclass 26, count 0 2006.285.18:18:50.57#ibcon#read 4, iclass 26, count 0 2006.285.18:18:50.57#ibcon#about to read 5, iclass 26, count 0 2006.285.18:18:50.57#ibcon#read 5, iclass 26, count 0 2006.285.18:18:50.57#ibcon#about to read 6, iclass 26, count 0 2006.285.18:18:50.57#ibcon#read 6, iclass 26, count 0 2006.285.18:18:50.57#ibcon#end of sib2, iclass 26, count 0 2006.285.18:18:50.57#ibcon#*after write, iclass 26, count 0 2006.285.18:18:50.57#ibcon#*before return 0, iclass 26, count 0 2006.285.18:18:50.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:18:50.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:18:50.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:18:50.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:18:50.57$vck44/va=3,7 2006.285.18:18:50.57#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.18:18:50.57#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.18:18:50.57#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:50.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:18:50.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:18:50.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:18:50.57#ibcon#enter wrdev, iclass 29, count 2 2006.285.18:18:50.57#ibcon#first serial, iclass 29, count 2 2006.285.18:18:50.57#ibcon#enter sib2, iclass 29, count 2 2006.285.18:18:50.57#ibcon#flushed, iclass 29, count 2 2006.285.18:18:50.57#ibcon#about to write, iclass 29, count 2 2006.285.18:18:50.57#ibcon#wrote, iclass 29, count 2 2006.285.18:18:50.57#ibcon#about to read 3, iclass 29, count 2 2006.285.18:18:50.59#ibcon#read 3, iclass 29, count 2 2006.285.18:18:50.59#ibcon#about to read 4, iclass 29, count 2 2006.285.18:18:50.59#ibcon#read 4, iclass 29, count 2 2006.285.18:18:50.59#ibcon#about to read 5, iclass 29, count 2 2006.285.18:18:50.59#ibcon#read 5, iclass 29, count 2 2006.285.18:18:50.59#ibcon#about to read 6, iclass 29, count 2 2006.285.18:18:50.59#ibcon#read 6, iclass 29, count 2 2006.285.18:18:50.59#ibcon#end of sib2, iclass 29, count 2 2006.285.18:18:50.59#ibcon#*mode == 0, iclass 29, count 2 2006.285.18:18:50.59#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.18:18:50.59#ibcon#[25=AT03-07\r\n] 2006.285.18:18:50.59#ibcon#*before write, iclass 29, count 2 2006.285.18:18:50.59#ibcon#enter sib2, iclass 29, count 2 2006.285.18:18:50.59#ibcon#flushed, iclass 29, count 2 2006.285.18:18:50.59#ibcon#about to write, iclass 29, count 2 2006.285.18:18:50.59#ibcon#wrote, iclass 29, count 2 2006.285.18:18:50.59#ibcon#about to read 3, iclass 29, count 2 2006.285.18:18:50.59#abcon#<5=/14 0.4 1.4 15.651001014.5\r\n> 2006.285.18:18:50.61#abcon#{5=INTERFACE CLEAR} 2006.285.18:18:50.62#ibcon#read 3, iclass 29, count 2 2006.285.18:18:50.62#ibcon#about to read 4, iclass 29, count 2 2006.285.18:18:50.62#ibcon#read 4, iclass 29, count 2 2006.285.18:18:50.62#ibcon#about to read 5, iclass 29, count 2 2006.285.18:18:50.62#ibcon#read 5, iclass 29, count 2 2006.285.18:18:50.62#ibcon#about to read 6, iclass 29, count 2 2006.285.18:18:50.62#ibcon#read 6, iclass 29, count 2 2006.285.18:18:50.62#ibcon#end of sib2, iclass 29, count 2 2006.285.18:18:50.62#ibcon#*after write, iclass 29, count 2 2006.285.18:18:50.62#ibcon#*before return 0, iclass 29, count 2 2006.285.18:18:50.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:18:50.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:18:50.62#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.18:18:50.62#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:50.62#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:18:50.67#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:18:50.74#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:18:50.74#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:18:50.74#ibcon#enter wrdev, iclass 29, count 0 2006.285.18:18:50.74#ibcon#first serial, iclass 29, count 0 2006.285.18:18:50.74#ibcon#enter sib2, iclass 29, count 0 2006.285.18:18:50.74#ibcon#flushed, iclass 29, count 0 2006.285.18:18:50.74#ibcon#about to write, iclass 29, count 0 2006.285.18:18:50.74#ibcon#wrote, iclass 29, count 0 2006.285.18:18:50.74#ibcon#about to read 3, iclass 29, count 0 2006.285.18:18:50.76#ibcon#read 3, iclass 29, count 0 2006.285.18:18:50.76#ibcon#about to read 4, iclass 29, count 0 2006.285.18:18:50.76#ibcon#read 4, iclass 29, count 0 2006.285.18:18:50.76#ibcon#about to read 5, iclass 29, count 0 2006.285.18:18:50.76#ibcon#read 5, iclass 29, count 0 2006.285.18:18:50.76#ibcon#about to read 6, iclass 29, count 0 2006.285.18:18:50.76#ibcon#read 6, iclass 29, count 0 2006.285.18:18:50.76#ibcon#end of sib2, iclass 29, count 0 2006.285.18:18:50.76#ibcon#*mode == 0, iclass 29, count 0 2006.285.18:18:50.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.18:18:50.76#ibcon#[25=USB\r\n] 2006.285.18:18:50.76#ibcon#*before write, iclass 29, count 0 2006.285.18:18:50.76#ibcon#enter sib2, iclass 29, count 0 2006.285.18:18:50.76#ibcon#flushed, iclass 29, count 0 2006.285.18:18:50.76#ibcon#about to write, iclass 29, count 0 2006.285.18:18:50.76#ibcon#wrote, iclass 29, count 0 2006.285.18:18:50.76#ibcon#about to read 3, iclass 29, count 0 2006.285.18:18:50.79#ibcon#read 3, iclass 29, count 0 2006.285.18:18:50.79#ibcon#about to read 4, iclass 29, count 0 2006.285.18:18:50.79#ibcon#read 4, iclass 29, count 0 2006.285.18:18:50.79#ibcon#about to read 5, iclass 29, count 0 2006.285.18:18:50.79#ibcon#read 5, iclass 29, count 0 2006.285.18:18:50.79#ibcon#about to read 6, iclass 29, count 0 2006.285.18:18:50.79#ibcon#read 6, iclass 29, count 0 2006.285.18:18:50.79#ibcon#end of sib2, iclass 29, count 0 2006.285.18:18:50.79#ibcon#*after write, iclass 29, count 0 2006.285.18:18:50.79#ibcon#*before return 0, iclass 29, count 0 2006.285.18:18:50.79#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:18:50.79#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:18:50.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.18:18:50.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.18:18:50.79$vck44/valo=4,624.99 2006.285.18:18:50.79#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.18:18:50.79#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.18:18:50.79#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:50.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:18:50.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:18:50.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:18:50.79#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:18:50.79#ibcon#first serial, iclass 34, count 0 2006.285.18:18:50.79#ibcon#enter sib2, iclass 34, count 0 2006.285.18:18:50.79#ibcon#flushed, iclass 34, count 0 2006.285.18:18:50.79#ibcon#about to write, iclass 34, count 0 2006.285.18:18:50.79#ibcon#wrote, iclass 34, count 0 2006.285.18:18:50.79#ibcon#about to read 3, iclass 34, count 0 2006.285.18:18:50.81#ibcon#read 3, iclass 34, count 0 2006.285.18:18:50.81#ibcon#about to read 4, iclass 34, count 0 2006.285.18:18:50.81#ibcon#read 4, iclass 34, count 0 2006.285.18:18:50.81#ibcon#about to read 5, iclass 34, count 0 2006.285.18:18:50.81#ibcon#read 5, iclass 34, count 0 2006.285.18:18:50.81#ibcon#about to read 6, iclass 34, count 0 2006.285.18:18:50.81#ibcon#read 6, iclass 34, count 0 2006.285.18:18:50.81#ibcon#end of sib2, iclass 34, count 0 2006.285.18:18:50.81#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:18:50.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:18:50.81#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.18:18:50.81#ibcon#*before write, iclass 34, count 0 2006.285.18:18:50.81#ibcon#enter sib2, iclass 34, count 0 2006.285.18:18:50.81#ibcon#flushed, iclass 34, count 0 2006.285.18:18:50.81#ibcon#about to write, iclass 34, count 0 2006.285.18:18:50.81#ibcon#wrote, iclass 34, count 0 2006.285.18:18:50.81#ibcon#about to read 3, iclass 34, count 0 2006.285.18:18:50.85#ibcon#read 3, iclass 34, count 0 2006.285.18:18:50.85#ibcon#about to read 4, iclass 34, count 0 2006.285.18:18:50.85#ibcon#read 4, iclass 34, count 0 2006.285.18:18:50.85#ibcon#about to read 5, iclass 34, count 0 2006.285.18:18:50.85#ibcon#read 5, iclass 34, count 0 2006.285.18:18:50.85#ibcon#about to read 6, iclass 34, count 0 2006.285.18:18:50.85#ibcon#read 6, iclass 34, count 0 2006.285.18:18:50.85#ibcon#end of sib2, iclass 34, count 0 2006.285.18:18:50.85#ibcon#*after write, iclass 34, count 0 2006.285.18:18:50.85#ibcon#*before return 0, iclass 34, count 0 2006.285.18:18:50.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:18:50.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:18:50.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:18:50.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:18:50.85$vck44/va=4,6 2006.285.18:18:50.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.18:18:50.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.18:18:50.85#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:50.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:18:50.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:18:50.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:18:50.91#ibcon#enter wrdev, iclass 36, count 2 2006.285.18:18:50.91#ibcon#first serial, iclass 36, count 2 2006.285.18:18:50.91#ibcon#enter sib2, iclass 36, count 2 2006.285.18:18:50.91#ibcon#flushed, iclass 36, count 2 2006.285.18:18:50.91#ibcon#about to write, iclass 36, count 2 2006.285.18:18:50.91#ibcon#wrote, iclass 36, count 2 2006.285.18:18:50.91#ibcon#about to read 3, iclass 36, count 2 2006.285.18:18:50.93#ibcon#read 3, iclass 36, count 2 2006.285.18:18:50.93#ibcon#about to read 4, iclass 36, count 2 2006.285.18:18:50.93#ibcon#read 4, iclass 36, count 2 2006.285.18:18:50.93#ibcon#about to read 5, iclass 36, count 2 2006.285.18:18:50.93#ibcon#read 5, iclass 36, count 2 2006.285.18:18:50.93#ibcon#about to read 6, iclass 36, count 2 2006.285.18:18:50.93#ibcon#read 6, iclass 36, count 2 2006.285.18:18:50.93#ibcon#end of sib2, iclass 36, count 2 2006.285.18:18:50.93#ibcon#*mode == 0, iclass 36, count 2 2006.285.18:18:50.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.18:18:50.93#ibcon#[25=AT04-06\r\n] 2006.285.18:18:50.93#ibcon#*before write, iclass 36, count 2 2006.285.18:18:50.93#ibcon#enter sib2, iclass 36, count 2 2006.285.18:18:50.93#ibcon#flushed, iclass 36, count 2 2006.285.18:18:50.93#ibcon#about to write, iclass 36, count 2 2006.285.18:18:50.93#ibcon#wrote, iclass 36, count 2 2006.285.18:18:50.93#ibcon#about to read 3, iclass 36, count 2 2006.285.18:18:50.96#ibcon#read 3, iclass 36, count 2 2006.285.18:18:50.96#ibcon#about to read 4, iclass 36, count 2 2006.285.18:18:50.96#ibcon#read 4, iclass 36, count 2 2006.285.18:18:50.96#ibcon#about to read 5, iclass 36, count 2 2006.285.18:18:50.96#ibcon#read 5, iclass 36, count 2 2006.285.18:18:50.96#ibcon#about to read 6, iclass 36, count 2 2006.285.18:18:50.96#ibcon#read 6, iclass 36, count 2 2006.285.18:18:50.96#ibcon#end of sib2, iclass 36, count 2 2006.285.18:18:50.96#ibcon#*after write, iclass 36, count 2 2006.285.18:18:50.96#ibcon#*before return 0, iclass 36, count 2 2006.285.18:18:50.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:18:50.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:18:50.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.18:18:50.96#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:50.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:18:51.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:18:51.51#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:18:51.51#ibcon#enter wrdev, iclass 36, count 0 2006.285.18:18:51.51#ibcon#first serial, iclass 36, count 0 2006.285.18:18:51.51#ibcon#enter sib2, iclass 36, count 0 2006.285.18:18:51.51#ibcon#flushed, iclass 36, count 0 2006.285.18:18:51.51#ibcon#about to write, iclass 36, count 0 2006.285.18:18:51.51#ibcon#wrote, iclass 36, count 0 2006.285.18:18:51.51#ibcon#about to read 3, iclass 36, count 0 2006.285.18:18:51.53#ibcon#read 3, iclass 36, count 0 2006.285.18:18:51.53#ibcon#about to read 4, iclass 36, count 0 2006.285.18:18:51.53#ibcon#read 4, iclass 36, count 0 2006.285.18:18:51.53#ibcon#about to read 5, iclass 36, count 0 2006.285.18:18:51.53#ibcon#read 5, iclass 36, count 0 2006.285.18:18:51.53#ibcon#about to read 6, iclass 36, count 0 2006.285.18:18:51.53#ibcon#read 6, iclass 36, count 0 2006.285.18:18:51.53#ibcon#end of sib2, iclass 36, count 0 2006.285.18:18:51.53#ibcon#*mode == 0, iclass 36, count 0 2006.285.18:18:51.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.18:18:51.53#ibcon#[25=USB\r\n] 2006.285.18:18:51.53#ibcon#*before write, iclass 36, count 0 2006.285.18:18:51.53#ibcon#enter sib2, iclass 36, count 0 2006.285.18:18:51.53#ibcon#flushed, iclass 36, count 0 2006.285.18:18:51.53#ibcon#about to write, iclass 36, count 0 2006.285.18:18:51.53#ibcon#wrote, iclass 36, count 0 2006.285.18:18:51.53#ibcon#about to read 3, iclass 36, count 0 2006.285.18:18:51.56#ibcon#read 3, iclass 36, count 0 2006.285.18:18:51.56#ibcon#about to read 4, iclass 36, count 0 2006.285.18:18:51.56#ibcon#read 4, iclass 36, count 0 2006.285.18:18:51.56#ibcon#about to read 5, iclass 36, count 0 2006.285.18:18:51.56#ibcon#read 5, iclass 36, count 0 2006.285.18:18:51.56#ibcon#about to read 6, iclass 36, count 0 2006.285.18:18:51.56#ibcon#read 6, iclass 36, count 0 2006.285.18:18:51.56#ibcon#end of sib2, iclass 36, count 0 2006.285.18:18:51.56#ibcon#*after write, iclass 36, count 0 2006.285.18:18:51.56#ibcon#*before return 0, iclass 36, count 0 2006.285.18:18:51.56#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:18:51.56#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:18:51.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.18:18:51.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.18:18:51.56$vck44/valo=5,734.99 2006.285.18:18:51.56#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.18:18:51.56#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.18:18:51.56#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:51.56#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:18:51.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:18:51.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:18:51.56#ibcon#enter wrdev, iclass 38, count 0 2006.285.18:18:51.56#ibcon#first serial, iclass 38, count 0 2006.285.18:18:51.56#ibcon#enter sib2, iclass 38, count 0 2006.285.18:18:51.56#ibcon#flushed, iclass 38, count 0 2006.285.18:18:51.56#ibcon#about to write, iclass 38, count 0 2006.285.18:18:51.56#ibcon#wrote, iclass 38, count 0 2006.285.18:18:51.56#ibcon#about to read 3, iclass 38, count 0 2006.285.18:18:51.58#ibcon#read 3, iclass 38, count 0 2006.285.18:18:51.58#ibcon#about to read 4, iclass 38, count 0 2006.285.18:18:51.58#ibcon#read 4, iclass 38, count 0 2006.285.18:18:51.58#ibcon#about to read 5, iclass 38, count 0 2006.285.18:18:51.58#ibcon#read 5, iclass 38, count 0 2006.285.18:18:51.58#ibcon#about to read 6, iclass 38, count 0 2006.285.18:18:51.58#ibcon#read 6, iclass 38, count 0 2006.285.18:18:51.58#ibcon#end of sib2, iclass 38, count 0 2006.285.18:18:51.58#ibcon#*mode == 0, iclass 38, count 0 2006.285.18:18:51.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.18:18:51.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.18:18:51.58#ibcon#*before write, iclass 38, count 0 2006.285.18:18:51.58#ibcon#enter sib2, iclass 38, count 0 2006.285.18:18:51.58#ibcon#flushed, iclass 38, count 0 2006.285.18:18:51.58#ibcon#about to write, iclass 38, count 0 2006.285.18:18:51.58#ibcon#wrote, iclass 38, count 0 2006.285.18:18:51.58#ibcon#about to read 3, iclass 38, count 0 2006.285.18:18:51.62#ibcon#read 3, iclass 38, count 0 2006.285.18:18:51.62#ibcon#about to read 4, iclass 38, count 0 2006.285.18:18:51.62#ibcon#read 4, iclass 38, count 0 2006.285.18:18:51.62#ibcon#about to read 5, iclass 38, count 0 2006.285.18:18:51.62#ibcon#read 5, iclass 38, count 0 2006.285.18:18:51.62#ibcon#about to read 6, iclass 38, count 0 2006.285.18:18:51.62#ibcon#read 6, iclass 38, count 0 2006.285.18:18:51.62#ibcon#end of sib2, iclass 38, count 0 2006.285.18:18:51.62#ibcon#*after write, iclass 38, count 0 2006.285.18:18:51.62#ibcon#*before return 0, iclass 38, count 0 2006.285.18:18:51.62#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:18:51.62#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:18:51.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.18:18:51.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.18:18:51.62$vck44/va=5,3 2006.285.18:18:51.62#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.18:18:51.62#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.18:18:51.62#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:51.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:18:51.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:18:51.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:18:51.68#ibcon#enter wrdev, iclass 40, count 2 2006.285.18:18:51.68#ibcon#first serial, iclass 40, count 2 2006.285.18:18:51.68#ibcon#enter sib2, iclass 40, count 2 2006.285.18:18:51.68#ibcon#flushed, iclass 40, count 2 2006.285.18:18:51.68#ibcon#about to write, iclass 40, count 2 2006.285.18:18:51.68#ibcon#wrote, iclass 40, count 2 2006.285.18:18:51.68#ibcon#about to read 3, iclass 40, count 2 2006.285.18:18:51.70#ibcon#read 3, iclass 40, count 2 2006.285.18:18:51.70#ibcon#about to read 4, iclass 40, count 2 2006.285.18:18:51.70#ibcon#read 4, iclass 40, count 2 2006.285.18:18:51.70#ibcon#about to read 5, iclass 40, count 2 2006.285.18:18:51.70#ibcon#read 5, iclass 40, count 2 2006.285.18:18:51.70#ibcon#about to read 6, iclass 40, count 2 2006.285.18:18:51.70#ibcon#read 6, iclass 40, count 2 2006.285.18:18:51.70#ibcon#end of sib2, iclass 40, count 2 2006.285.18:18:51.70#ibcon#*mode == 0, iclass 40, count 2 2006.285.18:18:51.70#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.18:18:51.70#ibcon#[25=AT05-03\r\n] 2006.285.18:18:51.70#ibcon#*before write, iclass 40, count 2 2006.285.18:18:51.70#ibcon#enter sib2, iclass 40, count 2 2006.285.18:18:51.70#ibcon#flushed, iclass 40, count 2 2006.285.18:18:51.70#ibcon#about to write, iclass 40, count 2 2006.285.18:18:51.70#ibcon#wrote, iclass 40, count 2 2006.285.18:18:51.70#ibcon#about to read 3, iclass 40, count 2 2006.285.18:18:51.73#ibcon#read 3, iclass 40, count 2 2006.285.18:18:51.73#ibcon#about to read 4, iclass 40, count 2 2006.285.18:18:51.73#ibcon#read 4, iclass 40, count 2 2006.285.18:18:51.73#ibcon#about to read 5, iclass 40, count 2 2006.285.18:18:51.73#ibcon#read 5, iclass 40, count 2 2006.285.18:18:51.73#ibcon#about to read 6, iclass 40, count 2 2006.285.18:18:51.73#ibcon#read 6, iclass 40, count 2 2006.285.18:18:51.73#ibcon#end of sib2, iclass 40, count 2 2006.285.18:18:51.73#ibcon#*after write, iclass 40, count 2 2006.285.18:18:51.73#ibcon#*before return 0, iclass 40, count 2 2006.285.18:18:51.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:18:51.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:18:51.73#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.18:18:51.73#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:51.73#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:18:51.85#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:18:51.85#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:18:51.85#ibcon#enter wrdev, iclass 40, count 0 2006.285.18:18:51.85#ibcon#first serial, iclass 40, count 0 2006.285.18:18:51.85#ibcon#enter sib2, iclass 40, count 0 2006.285.18:18:51.85#ibcon#flushed, iclass 40, count 0 2006.285.18:18:51.85#ibcon#about to write, iclass 40, count 0 2006.285.18:18:51.85#ibcon#wrote, iclass 40, count 0 2006.285.18:18:51.85#ibcon#about to read 3, iclass 40, count 0 2006.285.18:18:51.87#ibcon#read 3, iclass 40, count 0 2006.285.18:18:51.87#ibcon#about to read 4, iclass 40, count 0 2006.285.18:18:51.87#ibcon#read 4, iclass 40, count 0 2006.285.18:18:51.87#ibcon#about to read 5, iclass 40, count 0 2006.285.18:18:51.87#ibcon#read 5, iclass 40, count 0 2006.285.18:18:51.87#ibcon#about to read 6, iclass 40, count 0 2006.285.18:18:51.87#ibcon#read 6, iclass 40, count 0 2006.285.18:18:51.87#ibcon#end of sib2, iclass 40, count 0 2006.285.18:18:51.87#ibcon#*mode == 0, iclass 40, count 0 2006.285.18:18:51.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.18:18:51.87#ibcon#[25=USB\r\n] 2006.285.18:18:51.87#ibcon#*before write, iclass 40, count 0 2006.285.18:18:51.87#ibcon#enter sib2, iclass 40, count 0 2006.285.18:18:51.87#ibcon#flushed, iclass 40, count 0 2006.285.18:18:51.87#ibcon#about to write, iclass 40, count 0 2006.285.18:18:51.87#ibcon#wrote, iclass 40, count 0 2006.285.18:18:51.87#ibcon#about to read 3, iclass 40, count 0 2006.285.18:18:51.90#ibcon#read 3, iclass 40, count 0 2006.285.18:18:51.90#ibcon#about to read 4, iclass 40, count 0 2006.285.18:18:51.90#ibcon#read 4, iclass 40, count 0 2006.285.18:18:51.90#ibcon#about to read 5, iclass 40, count 0 2006.285.18:18:51.90#ibcon#read 5, iclass 40, count 0 2006.285.18:18:51.90#ibcon#about to read 6, iclass 40, count 0 2006.285.18:18:51.90#ibcon#read 6, iclass 40, count 0 2006.285.18:18:51.90#ibcon#end of sib2, iclass 40, count 0 2006.285.18:18:51.90#ibcon#*after write, iclass 40, count 0 2006.285.18:18:51.90#ibcon#*before return 0, iclass 40, count 0 2006.285.18:18:51.90#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:18:51.90#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:18:51.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.18:18:51.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.18:18:51.90$vck44/valo=6,814.99 2006.285.18:18:51.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.18:18:51.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.18:18:51.90#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:51.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:18:51.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:18:51.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:18:51.90#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:18:51.90#ibcon#first serial, iclass 4, count 0 2006.285.18:18:51.90#ibcon#enter sib2, iclass 4, count 0 2006.285.18:18:51.90#ibcon#flushed, iclass 4, count 0 2006.285.18:18:51.90#ibcon#about to write, iclass 4, count 0 2006.285.18:18:51.90#ibcon#wrote, iclass 4, count 0 2006.285.18:18:51.90#ibcon#about to read 3, iclass 4, count 0 2006.285.18:18:51.92#ibcon#read 3, iclass 4, count 0 2006.285.18:18:51.92#ibcon#about to read 4, iclass 4, count 0 2006.285.18:18:51.92#ibcon#read 4, iclass 4, count 0 2006.285.18:18:51.92#ibcon#about to read 5, iclass 4, count 0 2006.285.18:18:51.92#ibcon#read 5, iclass 4, count 0 2006.285.18:18:51.92#ibcon#about to read 6, iclass 4, count 0 2006.285.18:18:51.92#ibcon#read 6, iclass 4, count 0 2006.285.18:18:51.92#ibcon#end of sib2, iclass 4, count 0 2006.285.18:18:51.92#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:18:51.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:18:51.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.18:18:51.92#ibcon#*before write, iclass 4, count 0 2006.285.18:18:51.92#ibcon#enter sib2, iclass 4, count 0 2006.285.18:18:51.92#ibcon#flushed, iclass 4, count 0 2006.285.18:18:51.92#ibcon#about to write, iclass 4, count 0 2006.285.18:18:51.92#ibcon#wrote, iclass 4, count 0 2006.285.18:18:51.92#ibcon#about to read 3, iclass 4, count 0 2006.285.18:18:51.96#ibcon#read 3, iclass 4, count 0 2006.285.18:18:51.96#ibcon#about to read 4, iclass 4, count 0 2006.285.18:18:51.96#ibcon#read 4, iclass 4, count 0 2006.285.18:18:51.96#ibcon#about to read 5, iclass 4, count 0 2006.285.18:18:51.96#ibcon#read 5, iclass 4, count 0 2006.285.18:18:51.96#ibcon#about to read 6, iclass 4, count 0 2006.285.18:18:51.96#ibcon#read 6, iclass 4, count 0 2006.285.18:18:51.96#ibcon#end of sib2, iclass 4, count 0 2006.285.18:18:51.96#ibcon#*after write, iclass 4, count 0 2006.285.18:18:51.96#ibcon#*before return 0, iclass 4, count 0 2006.285.18:18:51.96#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:18:51.96#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:18:51.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:18:51.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:18:51.96$vck44/va=6,4 2006.285.18:18:51.96#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.18:18:51.96#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.18:18:51.96#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:51.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:18:52.02#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:18:52.02#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:18:52.02#ibcon#enter wrdev, iclass 6, count 2 2006.285.18:18:52.02#ibcon#first serial, iclass 6, count 2 2006.285.18:18:52.02#ibcon#enter sib2, iclass 6, count 2 2006.285.18:18:52.02#ibcon#flushed, iclass 6, count 2 2006.285.18:18:52.02#ibcon#about to write, iclass 6, count 2 2006.285.18:18:52.02#ibcon#wrote, iclass 6, count 2 2006.285.18:18:52.02#ibcon#about to read 3, iclass 6, count 2 2006.285.18:18:52.04#ibcon#read 3, iclass 6, count 2 2006.285.18:18:52.04#ibcon#about to read 4, iclass 6, count 2 2006.285.18:18:52.04#ibcon#read 4, iclass 6, count 2 2006.285.18:18:52.04#ibcon#about to read 5, iclass 6, count 2 2006.285.18:18:52.04#ibcon#read 5, iclass 6, count 2 2006.285.18:18:52.04#ibcon#about to read 6, iclass 6, count 2 2006.285.18:18:52.04#ibcon#read 6, iclass 6, count 2 2006.285.18:18:52.04#ibcon#end of sib2, iclass 6, count 2 2006.285.18:18:52.04#ibcon#*mode == 0, iclass 6, count 2 2006.285.18:18:52.04#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.18:18:52.04#ibcon#[25=AT06-04\r\n] 2006.285.18:18:52.04#ibcon#*before write, iclass 6, count 2 2006.285.18:18:52.04#ibcon#enter sib2, iclass 6, count 2 2006.285.18:18:52.04#ibcon#flushed, iclass 6, count 2 2006.285.18:18:52.04#ibcon#about to write, iclass 6, count 2 2006.285.18:18:52.04#ibcon#wrote, iclass 6, count 2 2006.285.18:18:52.04#ibcon#about to read 3, iclass 6, count 2 2006.285.18:18:52.07#ibcon#read 3, iclass 6, count 2 2006.285.18:18:52.07#ibcon#about to read 4, iclass 6, count 2 2006.285.18:18:52.07#ibcon#read 4, iclass 6, count 2 2006.285.18:18:52.07#ibcon#about to read 5, iclass 6, count 2 2006.285.18:18:52.07#ibcon#read 5, iclass 6, count 2 2006.285.18:18:52.07#ibcon#about to read 6, iclass 6, count 2 2006.285.18:18:52.07#ibcon#read 6, iclass 6, count 2 2006.285.18:18:52.07#ibcon#end of sib2, iclass 6, count 2 2006.285.18:18:52.07#ibcon#*after write, iclass 6, count 2 2006.285.18:18:52.07#ibcon#*before return 0, iclass 6, count 2 2006.285.18:18:52.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:18:52.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:18:52.07#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.18:18:52.07#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:52.07#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:18:52.19#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:18:52.19#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:18:52.19#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:18:52.19#ibcon#first serial, iclass 6, count 0 2006.285.18:18:52.19#ibcon#enter sib2, iclass 6, count 0 2006.285.18:18:52.19#ibcon#flushed, iclass 6, count 0 2006.285.18:18:52.19#ibcon#about to write, iclass 6, count 0 2006.285.18:18:52.19#ibcon#wrote, iclass 6, count 0 2006.285.18:18:52.19#ibcon#about to read 3, iclass 6, count 0 2006.285.18:18:52.21#ibcon#read 3, iclass 6, count 0 2006.285.18:18:52.21#ibcon#about to read 4, iclass 6, count 0 2006.285.18:18:52.21#ibcon#read 4, iclass 6, count 0 2006.285.18:18:52.21#ibcon#about to read 5, iclass 6, count 0 2006.285.18:18:52.21#ibcon#read 5, iclass 6, count 0 2006.285.18:18:52.21#ibcon#about to read 6, iclass 6, count 0 2006.285.18:18:52.21#ibcon#read 6, iclass 6, count 0 2006.285.18:18:52.21#ibcon#end of sib2, iclass 6, count 0 2006.285.18:18:52.21#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:18:52.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:18:52.21#ibcon#[25=USB\r\n] 2006.285.18:18:52.21#ibcon#*before write, iclass 6, count 0 2006.285.18:18:52.21#ibcon#enter sib2, iclass 6, count 0 2006.285.18:18:52.21#ibcon#flushed, iclass 6, count 0 2006.285.18:18:52.21#ibcon#about to write, iclass 6, count 0 2006.285.18:18:52.21#ibcon#wrote, iclass 6, count 0 2006.285.18:18:52.21#ibcon#about to read 3, iclass 6, count 0 2006.285.18:18:52.24#ibcon#read 3, iclass 6, count 0 2006.285.18:18:52.24#ibcon#about to read 4, iclass 6, count 0 2006.285.18:18:52.24#ibcon#read 4, iclass 6, count 0 2006.285.18:18:52.24#ibcon#about to read 5, iclass 6, count 0 2006.285.18:18:52.24#ibcon#read 5, iclass 6, count 0 2006.285.18:18:52.24#ibcon#about to read 6, iclass 6, count 0 2006.285.18:18:52.24#ibcon#read 6, iclass 6, count 0 2006.285.18:18:52.24#ibcon#end of sib2, iclass 6, count 0 2006.285.18:18:52.24#ibcon#*after write, iclass 6, count 0 2006.285.18:18:52.24#ibcon#*before return 0, iclass 6, count 0 2006.285.18:18:52.24#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:18:52.24#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:18:52.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:18:52.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:18:52.24$vck44/valo=7,864.99 2006.285.18:18:52.24#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.18:18:52.24#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.18:18:52.24#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:52.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:18:52.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:18:52.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:18:52.24#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:18:52.24#ibcon#first serial, iclass 10, count 0 2006.285.18:18:52.24#ibcon#enter sib2, iclass 10, count 0 2006.285.18:18:52.24#ibcon#flushed, iclass 10, count 0 2006.285.18:18:52.24#ibcon#about to write, iclass 10, count 0 2006.285.18:18:52.24#ibcon#wrote, iclass 10, count 0 2006.285.18:18:52.24#ibcon#about to read 3, iclass 10, count 0 2006.285.18:18:52.26#ibcon#read 3, iclass 10, count 0 2006.285.18:18:52.26#ibcon#about to read 4, iclass 10, count 0 2006.285.18:18:52.26#ibcon#read 4, iclass 10, count 0 2006.285.18:18:52.26#ibcon#about to read 5, iclass 10, count 0 2006.285.18:18:52.26#ibcon#read 5, iclass 10, count 0 2006.285.18:18:52.26#ibcon#about to read 6, iclass 10, count 0 2006.285.18:18:52.26#ibcon#read 6, iclass 10, count 0 2006.285.18:18:52.26#ibcon#end of sib2, iclass 10, count 0 2006.285.18:18:52.26#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:18:52.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:18:52.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.18:18:52.26#ibcon#*before write, iclass 10, count 0 2006.285.18:18:52.26#ibcon#enter sib2, iclass 10, count 0 2006.285.18:18:52.26#ibcon#flushed, iclass 10, count 0 2006.285.18:18:52.26#ibcon#about to write, iclass 10, count 0 2006.285.18:18:52.26#ibcon#wrote, iclass 10, count 0 2006.285.18:18:52.26#ibcon#about to read 3, iclass 10, count 0 2006.285.18:18:52.30#ibcon#read 3, iclass 10, count 0 2006.285.18:18:52.30#ibcon#about to read 4, iclass 10, count 0 2006.285.18:18:52.30#ibcon#read 4, iclass 10, count 0 2006.285.18:18:52.30#ibcon#about to read 5, iclass 10, count 0 2006.285.18:18:52.30#ibcon#read 5, iclass 10, count 0 2006.285.18:18:52.30#ibcon#about to read 6, iclass 10, count 0 2006.285.18:18:52.30#ibcon#read 6, iclass 10, count 0 2006.285.18:18:52.30#ibcon#end of sib2, iclass 10, count 0 2006.285.18:18:52.30#ibcon#*after write, iclass 10, count 0 2006.285.18:18:52.30#ibcon#*before return 0, iclass 10, count 0 2006.285.18:18:52.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:18:52.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:18:52.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:18:52.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:18:52.30$vck44/va=7,4 2006.285.18:18:52.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.18:18:52.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.18:18:52.30#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:52.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:18:52.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:18:52.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:18:52.36#ibcon#enter wrdev, iclass 12, count 2 2006.285.18:18:52.36#ibcon#first serial, iclass 12, count 2 2006.285.18:18:52.36#ibcon#enter sib2, iclass 12, count 2 2006.285.18:18:52.36#ibcon#flushed, iclass 12, count 2 2006.285.18:18:52.36#ibcon#about to write, iclass 12, count 2 2006.285.18:18:52.36#ibcon#wrote, iclass 12, count 2 2006.285.18:18:52.36#ibcon#about to read 3, iclass 12, count 2 2006.285.18:18:52.38#ibcon#read 3, iclass 12, count 2 2006.285.18:18:52.38#ibcon#about to read 4, iclass 12, count 2 2006.285.18:18:52.38#ibcon#read 4, iclass 12, count 2 2006.285.18:18:52.38#ibcon#about to read 5, iclass 12, count 2 2006.285.18:18:52.38#ibcon#read 5, iclass 12, count 2 2006.285.18:18:52.38#ibcon#about to read 6, iclass 12, count 2 2006.285.18:18:52.38#ibcon#read 6, iclass 12, count 2 2006.285.18:18:52.38#ibcon#end of sib2, iclass 12, count 2 2006.285.18:18:52.38#ibcon#*mode == 0, iclass 12, count 2 2006.285.18:18:52.38#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.18:18:52.38#ibcon#[25=AT07-04\r\n] 2006.285.18:18:52.38#ibcon#*before write, iclass 12, count 2 2006.285.18:18:52.38#ibcon#enter sib2, iclass 12, count 2 2006.285.18:18:52.38#ibcon#flushed, iclass 12, count 2 2006.285.18:18:52.38#ibcon#about to write, iclass 12, count 2 2006.285.18:18:52.38#ibcon#wrote, iclass 12, count 2 2006.285.18:18:52.38#ibcon#about to read 3, iclass 12, count 2 2006.285.18:18:52.41#ibcon#read 3, iclass 12, count 2 2006.285.18:18:52.41#ibcon#about to read 4, iclass 12, count 2 2006.285.18:18:52.41#ibcon#read 4, iclass 12, count 2 2006.285.18:18:52.41#ibcon#about to read 5, iclass 12, count 2 2006.285.18:18:52.41#ibcon#read 5, iclass 12, count 2 2006.285.18:18:52.41#ibcon#about to read 6, iclass 12, count 2 2006.285.18:18:52.41#ibcon#read 6, iclass 12, count 2 2006.285.18:18:52.41#ibcon#end of sib2, iclass 12, count 2 2006.285.18:18:52.41#ibcon#*after write, iclass 12, count 2 2006.285.18:18:52.41#ibcon#*before return 0, iclass 12, count 2 2006.285.18:18:52.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:18:52.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:18:52.41#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.18:18:52.41#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:52.41#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:18:52.53#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:18:52.53#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:18:52.53#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:18:52.53#ibcon#first serial, iclass 12, count 0 2006.285.18:18:52.53#ibcon#enter sib2, iclass 12, count 0 2006.285.18:18:52.53#ibcon#flushed, iclass 12, count 0 2006.285.18:18:52.53#ibcon#about to write, iclass 12, count 0 2006.285.18:18:52.53#ibcon#wrote, iclass 12, count 0 2006.285.18:18:52.53#ibcon#about to read 3, iclass 12, count 0 2006.285.18:18:52.55#ibcon#read 3, iclass 12, count 0 2006.285.18:18:52.55#ibcon#about to read 4, iclass 12, count 0 2006.285.18:18:52.55#ibcon#read 4, iclass 12, count 0 2006.285.18:18:52.55#ibcon#about to read 5, iclass 12, count 0 2006.285.18:18:52.55#ibcon#read 5, iclass 12, count 0 2006.285.18:18:52.55#ibcon#about to read 6, iclass 12, count 0 2006.285.18:18:52.55#ibcon#read 6, iclass 12, count 0 2006.285.18:18:52.55#ibcon#end of sib2, iclass 12, count 0 2006.285.18:18:52.55#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:18:52.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:18:52.55#ibcon#[25=USB\r\n] 2006.285.18:18:52.55#ibcon#*before write, iclass 12, count 0 2006.285.18:18:52.55#ibcon#enter sib2, iclass 12, count 0 2006.285.18:18:52.55#ibcon#flushed, iclass 12, count 0 2006.285.18:18:52.55#ibcon#about to write, iclass 12, count 0 2006.285.18:18:52.55#ibcon#wrote, iclass 12, count 0 2006.285.18:18:52.55#ibcon#about to read 3, iclass 12, count 0 2006.285.18:18:52.58#ibcon#read 3, iclass 12, count 0 2006.285.18:18:52.58#ibcon#about to read 4, iclass 12, count 0 2006.285.18:18:52.58#ibcon#read 4, iclass 12, count 0 2006.285.18:18:52.58#ibcon#about to read 5, iclass 12, count 0 2006.285.18:18:52.58#ibcon#read 5, iclass 12, count 0 2006.285.18:18:52.58#ibcon#about to read 6, iclass 12, count 0 2006.285.18:18:52.58#ibcon#read 6, iclass 12, count 0 2006.285.18:18:52.58#ibcon#end of sib2, iclass 12, count 0 2006.285.18:18:52.58#ibcon#*after write, iclass 12, count 0 2006.285.18:18:52.58#ibcon#*before return 0, iclass 12, count 0 2006.285.18:18:52.58#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:18:52.58#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:18:52.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:18:52.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:18:52.58$vck44/valo=8,884.99 2006.285.18:18:52.58#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.18:18:52.58#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.18:18:52.58#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:52.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:18:52.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:18:52.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:18:52.58#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:18:52.58#ibcon#first serial, iclass 14, count 0 2006.285.18:18:52.58#ibcon#enter sib2, iclass 14, count 0 2006.285.18:18:52.58#ibcon#flushed, iclass 14, count 0 2006.285.18:18:52.58#ibcon#about to write, iclass 14, count 0 2006.285.18:18:52.58#ibcon#wrote, iclass 14, count 0 2006.285.18:18:52.58#ibcon#about to read 3, iclass 14, count 0 2006.285.18:18:52.60#ibcon#read 3, iclass 14, count 0 2006.285.18:18:52.60#ibcon#about to read 4, iclass 14, count 0 2006.285.18:18:52.60#ibcon#read 4, iclass 14, count 0 2006.285.18:18:52.60#ibcon#about to read 5, iclass 14, count 0 2006.285.18:18:52.60#ibcon#read 5, iclass 14, count 0 2006.285.18:18:52.60#ibcon#about to read 6, iclass 14, count 0 2006.285.18:18:52.60#ibcon#read 6, iclass 14, count 0 2006.285.18:18:52.60#ibcon#end of sib2, iclass 14, count 0 2006.285.18:18:52.60#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:18:52.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:18:52.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.18:18:52.60#ibcon#*before write, iclass 14, count 0 2006.285.18:18:52.60#ibcon#enter sib2, iclass 14, count 0 2006.285.18:18:52.60#ibcon#flushed, iclass 14, count 0 2006.285.18:18:52.60#ibcon#about to write, iclass 14, count 0 2006.285.18:18:52.60#ibcon#wrote, iclass 14, count 0 2006.285.18:18:52.60#ibcon#about to read 3, iclass 14, count 0 2006.285.18:18:52.64#ibcon#read 3, iclass 14, count 0 2006.285.18:18:52.64#ibcon#about to read 4, iclass 14, count 0 2006.285.18:18:52.64#ibcon#read 4, iclass 14, count 0 2006.285.18:18:52.64#ibcon#about to read 5, iclass 14, count 0 2006.285.18:18:52.64#ibcon#read 5, iclass 14, count 0 2006.285.18:18:52.64#ibcon#about to read 6, iclass 14, count 0 2006.285.18:18:52.64#ibcon#read 6, iclass 14, count 0 2006.285.18:18:52.64#ibcon#end of sib2, iclass 14, count 0 2006.285.18:18:52.64#ibcon#*after write, iclass 14, count 0 2006.285.18:18:52.64#ibcon#*before return 0, iclass 14, count 0 2006.285.18:18:52.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:18:52.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:18:52.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:18:52.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:18:52.64$vck44/va=8,3 2006.285.18:18:52.64#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.18:18:52.64#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.18:18:52.64#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:52.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:18:52.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:18:52.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:18:52.70#ibcon#enter wrdev, iclass 16, count 2 2006.285.18:18:52.70#ibcon#first serial, iclass 16, count 2 2006.285.18:18:52.70#ibcon#enter sib2, iclass 16, count 2 2006.285.18:18:52.70#ibcon#flushed, iclass 16, count 2 2006.285.18:18:52.70#ibcon#about to write, iclass 16, count 2 2006.285.18:18:52.70#ibcon#wrote, iclass 16, count 2 2006.285.18:18:52.70#ibcon#about to read 3, iclass 16, count 2 2006.285.18:18:52.72#ibcon#read 3, iclass 16, count 2 2006.285.18:18:52.72#ibcon#about to read 4, iclass 16, count 2 2006.285.18:18:52.72#ibcon#read 4, iclass 16, count 2 2006.285.18:18:52.72#ibcon#about to read 5, iclass 16, count 2 2006.285.18:18:52.72#ibcon#read 5, iclass 16, count 2 2006.285.18:18:52.72#ibcon#about to read 6, iclass 16, count 2 2006.285.18:18:52.72#ibcon#read 6, iclass 16, count 2 2006.285.18:18:52.72#ibcon#end of sib2, iclass 16, count 2 2006.285.18:18:52.72#ibcon#*mode == 0, iclass 16, count 2 2006.285.18:18:52.72#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.18:18:52.72#ibcon#[25=AT08-03\r\n] 2006.285.18:18:52.72#ibcon#*before write, iclass 16, count 2 2006.285.18:18:52.72#ibcon#enter sib2, iclass 16, count 2 2006.285.18:18:52.72#ibcon#flushed, iclass 16, count 2 2006.285.18:18:52.72#ibcon#about to write, iclass 16, count 2 2006.285.18:18:52.72#ibcon#wrote, iclass 16, count 2 2006.285.18:18:52.72#ibcon#about to read 3, iclass 16, count 2 2006.285.18:18:52.75#ibcon#read 3, iclass 16, count 2 2006.285.18:18:52.75#ibcon#about to read 4, iclass 16, count 2 2006.285.18:18:52.75#ibcon#read 4, iclass 16, count 2 2006.285.18:18:52.75#ibcon#about to read 5, iclass 16, count 2 2006.285.18:18:52.75#ibcon#read 5, iclass 16, count 2 2006.285.18:18:52.75#ibcon#about to read 6, iclass 16, count 2 2006.285.18:18:52.75#ibcon#read 6, iclass 16, count 2 2006.285.18:18:52.75#ibcon#end of sib2, iclass 16, count 2 2006.285.18:18:52.75#ibcon#*after write, iclass 16, count 2 2006.285.18:18:52.75#ibcon#*before return 0, iclass 16, count 2 2006.285.18:18:52.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:18:52.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:18:52.75#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.18:18:52.75#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:52.75#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:18:52.87#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:18:52.87#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:18:52.87#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:18:52.87#ibcon#first serial, iclass 16, count 0 2006.285.18:18:52.87#ibcon#enter sib2, iclass 16, count 0 2006.285.18:18:52.87#ibcon#flushed, iclass 16, count 0 2006.285.18:18:52.87#ibcon#about to write, iclass 16, count 0 2006.285.18:18:52.87#ibcon#wrote, iclass 16, count 0 2006.285.18:18:52.87#ibcon#about to read 3, iclass 16, count 0 2006.285.18:18:52.89#ibcon#read 3, iclass 16, count 0 2006.285.18:18:52.89#ibcon#about to read 4, iclass 16, count 0 2006.285.18:18:52.89#ibcon#read 4, iclass 16, count 0 2006.285.18:18:52.89#ibcon#about to read 5, iclass 16, count 0 2006.285.18:18:52.89#ibcon#read 5, iclass 16, count 0 2006.285.18:18:52.89#ibcon#about to read 6, iclass 16, count 0 2006.285.18:18:52.89#ibcon#read 6, iclass 16, count 0 2006.285.18:18:52.89#ibcon#end of sib2, iclass 16, count 0 2006.285.18:18:52.89#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:18:52.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:18:52.89#ibcon#[25=USB\r\n] 2006.285.18:18:52.89#ibcon#*before write, iclass 16, count 0 2006.285.18:18:52.89#ibcon#enter sib2, iclass 16, count 0 2006.285.18:18:52.89#ibcon#flushed, iclass 16, count 0 2006.285.18:18:52.89#ibcon#about to write, iclass 16, count 0 2006.285.18:18:52.89#ibcon#wrote, iclass 16, count 0 2006.285.18:18:52.89#ibcon#about to read 3, iclass 16, count 0 2006.285.18:18:52.92#ibcon#read 3, iclass 16, count 0 2006.285.18:18:52.92#ibcon#about to read 4, iclass 16, count 0 2006.285.18:18:52.92#ibcon#read 4, iclass 16, count 0 2006.285.18:18:52.92#ibcon#about to read 5, iclass 16, count 0 2006.285.18:18:52.92#ibcon#read 5, iclass 16, count 0 2006.285.18:18:52.92#ibcon#about to read 6, iclass 16, count 0 2006.285.18:18:52.92#ibcon#read 6, iclass 16, count 0 2006.285.18:18:52.92#ibcon#end of sib2, iclass 16, count 0 2006.285.18:18:52.92#ibcon#*after write, iclass 16, count 0 2006.285.18:18:52.92#ibcon#*before return 0, iclass 16, count 0 2006.285.18:18:52.92#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:18:52.92#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:18:52.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:18:52.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:18:52.92$vck44/vblo=1,629.99 2006.285.18:18:52.92#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.18:18:52.92#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.18:18:52.92#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:52.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:18:52.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:18:52.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:18:52.92#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:18:52.92#ibcon#first serial, iclass 18, count 0 2006.285.18:18:52.92#ibcon#enter sib2, iclass 18, count 0 2006.285.18:18:52.92#ibcon#flushed, iclass 18, count 0 2006.285.18:18:52.92#ibcon#about to write, iclass 18, count 0 2006.285.18:18:52.92#ibcon#wrote, iclass 18, count 0 2006.285.18:18:52.92#ibcon#about to read 3, iclass 18, count 0 2006.285.18:18:52.94#ibcon#read 3, iclass 18, count 0 2006.285.18:18:53.03#ibcon#about to read 4, iclass 18, count 0 2006.285.18:18:53.03#ibcon#read 4, iclass 18, count 0 2006.285.18:18:53.03#ibcon#about to read 5, iclass 18, count 0 2006.285.18:18:53.03#ibcon#read 5, iclass 18, count 0 2006.285.18:18:53.03#ibcon#about to read 6, iclass 18, count 0 2006.285.18:18:53.03#ibcon#read 6, iclass 18, count 0 2006.285.18:18:53.03#ibcon#end of sib2, iclass 18, count 0 2006.285.18:18:53.03#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:18:53.03#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:18:53.03#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.18:18:53.03#ibcon#*before write, iclass 18, count 0 2006.285.18:18:53.03#ibcon#enter sib2, iclass 18, count 0 2006.285.18:18:53.03#ibcon#flushed, iclass 18, count 0 2006.285.18:18:53.03#ibcon#about to write, iclass 18, count 0 2006.285.18:18:53.03#ibcon#wrote, iclass 18, count 0 2006.285.18:18:53.03#ibcon#about to read 3, iclass 18, count 0 2006.285.18:18:53.07#ibcon#read 3, iclass 18, count 0 2006.285.18:18:53.07#ibcon#about to read 4, iclass 18, count 0 2006.285.18:18:53.07#ibcon#read 4, iclass 18, count 0 2006.285.18:18:53.07#ibcon#about to read 5, iclass 18, count 0 2006.285.18:18:53.07#ibcon#read 5, iclass 18, count 0 2006.285.18:18:53.07#ibcon#about to read 6, iclass 18, count 0 2006.285.18:18:53.07#ibcon#read 6, iclass 18, count 0 2006.285.18:18:53.07#ibcon#end of sib2, iclass 18, count 0 2006.285.18:18:53.07#ibcon#*after write, iclass 18, count 0 2006.285.18:18:53.07#ibcon#*before return 0, iclass 18, count 0 2006.285.18:18:53.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:18:53.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:18:53.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:18:53.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:18:53.07$vck44/vb=1,4 2006.285.18:18:53.07#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.18:18:53.07#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.18:18:53.07#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:53.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:18:53.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:18:53.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:18:53.07#ibcon#enter wrdev, iclass 20, count 2 2006.285.18:18:53.07#ibcon#first serial, iclass 20, count 2 2006.285.18:18:53.07#ibcon#enter sib2, iclass 20, count 2 2006.285.18:18:53.07#ibcon#flushed, iclass 20, count 2 2006.285.18:18:53.07#ibcon#about to write, iclass 20, count 2 2006.285.18:18:53.07#ibcon#wrote, iclass 20, count 2 2006.285.18:18:53.07#ibcon#about to read 3, iclass 20, count 2 2006.285.18:18:53.09#ibcon#read 3, iclass 20, count 2 2006.285.18:18:53.09#ibcon#about to read 4, iclass 20, count 2 2006.285.18:18:53.09#ibcon#read 4, iclass 20, count 2 2006.285.18:18:53.09#ibcon#about to read 5, iclass 20, count 2 2006.285.18:18:53.09#ibcon#read 5, iclass 20, count 2 2006.285.18:18:53.09#ibcon#about to read 6, iclass 20, count 2 2006.285.18:18:53.09#ibcon#read 6, iclass 20, count 2 2006.285.18:18:53.09#ibcon#end of sib2, iclass 20, count 2 2006.285.18:18:53.09#ibcon#*mode == 0, iclass 20, count 2 2006.285.18:18:53.09#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.18:18:53.09#ibcon#[27=AT01-04\r\n] 2006.285.18:18:53.09#ibcon#*before write, iclass 20, count 2 2006.285.18:18:53.09#ibcon#enter sib2, iclass 20, count 2 2006.285.18:18:53.09#ibcon#flushed, iclass 20, count 2 2006.285.18:18:53.09#ibcon#about to write, iclass 20, count 2 2006.285.18:18:53.09#ibcon#wrote, iclass 20, count 2 2006.285.18:18:53.09#ibcon#about to read 3, iclass 20, count 2 2006.285.18:18:53.12#ibcon#read 3, iclass 20, count 2 2006.285.18:18:53.12#ibcon#about to read 4, iclass 20, count 2 2006.285.18:18:53.12#ibcon#read 4, iclass 20, count 2 2006.285.18:18:53.12#ibcon#about to read 5, iclass 20, count 2 2006.285.18:18:53.12#ibcon#read 5, iclass 20, count 2 2006.285.18:18:53.12#ibcon#about to read 6, iclass 20, count 2 2006.285.18:18:53.12#ibcon#read 6, iclass 20, count 2 2006.285.18:18:53.12#ibcon#end of sib2, iclass 20, count 2 2006.285.18:18:53.12#ibcon#*after write, iclass 20, count 2 2006.285.18:18:53.12#ibcon#*before return 0, iclass 20, count 2 2006.285.18:18:53.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:18:53.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:18:53.12#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.18:18:53.12#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:53.12#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:18:53.24#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:18:53.24#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:18:53.24#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:18:53.24#ibcon#first serial, iclass 20, count 0 2006.285.18:18:53.24#ibcon#enter sib2, iclass 20, count 0 2006.285.18:18:53.24#ibcon#flushed, iclass 20, count 0 2006.285.18:18:53.24#ibcon#about to write, iclass 20, count 0 2006.285.18:18:53.24#ibcon#wrote, iclass 20, count 0 2006.285.18:18:53.24#ibcon#about to read 3, iclass 20, count 0 2006.285.18:18:53.26#ibcon#read 3, iclass 20, count 0 2006.285.18:18:53.26#ibcon#about to read 4, iclass 20, count 0 2006.285.18:18:53.26#ibcon#read 4, iclass 20, count 0 2006.285.18:18:53.26#ibcon#about to read 5, iclass 20, count 0 2006.285.18:18:53.26#ibcon#read 5, iclass 20, count 0 2006.285.18:18:53.26#ibcon#about to read 6, iclass 20, count 0 2006.285.18:18:53.26#ibcon#read 6, iclass 20, count 0 2006.285.18:18:53.26#ibcon#end of sib2, iclass 20, count 0 2006.285.18:18:53.26#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:18:53.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:18:53.26#ibcon#[27=USB\r\n] 2006.285.18:18:53.26#ibcon#*before write, iclass 20, count 0 2006.285.18:18:53.26#ibcon#enter sib2, iclass 20, count 0 2006.285.18:18:53.26#ibcon#flushed, iclass 20, count 0 2006.285.18:18:53.26#ibcon#about to write, iclass 20, count 0 2006.285.18:18:53.26#ibcon#wrote, iclass 20, count 0 2006.285.18:18:53.26#ibcon#about to read 3, iclass 20, count 0 2006.285.18:18:53.29#ibcon#read 3, iclass 20, count 0 2006.285.18:18:53.29#ibcon#about to read 4, iclass 20, count 0 2006.285.18:18:53.29#ibcon#read 4, iclass 20, count 0 2006.285.18:18:53.29#ibcon#about to read 5, iclass 20, count 0 2006.285.18:18:53.29#ibcon#read 5, iclass 20, count 0 2006.285.18:18:53.29#ibcon#about to read 6, iclass 20, count 0 2006.285.18:18:53.29#ibcon#read 6, iclass 20, count 0 2006.285.18:18:53.29#ibcon#end of sib2, iclass 20, count 0 2006.285.18:18:53.29#ibcon#*after write, iclass 20, count 0 2006.285.18:18:53.29#ibcon#*before return 0, iclass 20, count 0 2006.285.18:18:53.29#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:18:53.29#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:18:53.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:18:53.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:18:53.29$vck44/vblo=2,634.99 2006.285.18:18:53.29#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.18:18:53.29#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.18:18:53.29#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:53.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:18:53.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:18:53.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:18:53.29#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:18:53.29#ibcon#first serial, iclass 22, count 0 2006.285.18:18:53.29#ibcon#enter sib2, iclass 22, count 0 2006.285.18:18:53.29#ibcon#flushed, iclass 22, count 0 2006.285.18:18:53.29#ibcon#about to write, iclass 22, count 0 2006.285.18:18:53.29#ibcon#wrote, iclass 22, count 0 2006.285.18:18:53.29#ibcon#about to read 3, iclass 22, count 0 2006.285.18:18:53.31#ibcon#read 3, iclass 22, count 0 2006.285.18:18:53.31#ibcon#about to read 4, iclass 22, count 0 2006.285.18:18:53.31#ibcon#read 4, iclass 22, count 0 2006.285.18:18:53.31#ibcon#about to read 5, iclass 22, count 0 2006.285.18:18:53.31#ibcon#read 5, iclass 22, count 0 2006.285.18:18:53.31#ibcon#about to read 6, iclass 22, count 0 2006.285.18:18:53.31#ibcon#read 6, iclass 22, count 0 2006.285.18:18:53.31#ibcon#end of sib2, iclass 22, count 0 2006.285.18:18:53.31#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:18:53.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:18:53.31#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.18:18:53.31#ibcon#*before write, iclass 22, count 0 2006.285.18:18:53.31#ibcon#enter sib2, iclass 22, count 0 2006.285.18:18:53.31#ibcon#flushed, iclass 22, count 0 2006.285.18:18:53.31#ibcon#about to write, iclass 22, count 0 2006.285.18:18:53.31#ibcon#wrote, iclass 22, count 0 2006.285.18:18:53.31#ibcon#about to read 3, iclass 22, count 0 2006.285.18:18:53.35#ibcon#read 3, iclass 22, count 0 2006.285.18:18:53.35#ibcon#about to read 4, iclass 22, count 0 2006.285.18:18:53.35#ibcon#read 4, iclass 22, count 0 2006.285.18:18:53.35#ibcon#about to read 5, iclass 22, count 0 2006.285.18:18:53.35#ibcon#read 5, iclass 22, count 0 2006.285.18:18:53.35#ibcon#about to read 6, iclass 22, count 0 2006.285.18:18:53.35#ibcon#read 6, iclass 22, count 0 2006.285.18:18:53.35#ibcon#end of sib2, iclass 22, count 0 2006.285.18:18:53.35#ibcon#*after write, iclass 22, count 0 2006.285.18:18:53.35#ibcon#*before return 0, iclass 22, count 0 2006.285.18:18:53.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:18:53.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:18:53.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:18:53.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:18:53.35$vck44/vb=2,5 2006.285.18:18:53.35#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.18:18:53.35#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.18:18:53.35#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:53.35#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:18:53.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:18:53.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:18:53.41#ibcon#enter wrdev, iclass 24, count 2 2006.285.18:18:53.41#ibcon#first serial, iclass 24, count 2 2006.285.18:18:53.41#ibcon#enter sib2, iclass 24, count 2 2006.285.18:18:53.41#ibcon#flushed, iclass 24, count 2 2006.285.18:18:53.41#ibcon#about to write, iclass 24, count 2 2006.285.18:18:53.41#ibcon#wrote, iclass 24, count 2 2006.285.18:18:53.41#ibcon#about to read 3, iclass 24, count 2 2006.285.18:18:53.43#ibcon#read 3, iclass 24, count 2 2006.285.18:18:53.43#ibcon#about to read 4, iclass 24, count 2 2006.285.18:18:53.43#ibcon#read 4, iclass 24, count 2 2006.285.18:18:53.43#ibcon#about to read 5, iclass 24, count 2 2006.285.18:18:53.43#ibcon#read 5, iclass 24, count 2 2006.285.18:18:53.43#ibcon#about to read 6, iclass 24, count 2 2006.285.18:18:53.43#ibcon#read 6, iclass 24, count 2 2006.285.18:18:53.43#ibcon#end of sib2, iclass 24, count 2 2006.285.18:18:53.43#ibcon#*mode == 0, iclass 24, count 2 2006.285.18:18:53.43#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.18:18:53.43#ibcon#[27=AT02-05\r\n] 2006.285.18:18:53.43#ibcon#*before write, iclass 24, count 2 2006.285.18:18:53.43#ibcon#enter sib2, iclass 24, count 2 2006.285.18:18:53.43#ibcon#flushed, iclass 24, count 2 2006.285.18:18:53.43#ibcon#about to write, iclass 24, count 2 2006.285.18:18:53.43#ibcon#wrote, iclass 24, count 2 2006.285.18:18:53.43#ibcon#about to read 3, iclass 24, count 2 2006.285.18:18:53.46#ibcon#read 3, iclass 24, count 2 2006.285.18:18:53.46#ibcon#about to read 4, iclass 24, count 2 2006.285.18:18:53.46#ibcon#read 4, iclass 24, count 2 2006.285.18:18:53.46#ibcon#about to read 5, iclass 24, count 2 2006.285.18:18:53.46#ibcon#read 5, iclass 24, count 2 2006.285.18:18:53.46#ibcon#about to read 6, iclass 24, count 2 2006.285.18:18:53.46#ibcon#read 6, iclass 24, count 2 2006.285.18:18:53.46#ibcon#end of sib2, iclass 24, count 2 2006.285.18:18:53.46#ibcon#*after write, iclass 24, count 2 2006.285.18:18:53.46#ibcon#*before return 0, iclass 24, count 2 2006.285.18:18:53.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:18:53.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:18:53.46#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.18:18:53.46#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:53.46#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:18:53.58#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:18:53.58#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:18:53.58#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:18:53.58#ibcon#first serial, iclass 24, count 0 2006.285.18:18:53.58#ibcon#enter sib2, iclass 24, count 0 2006.285.18:18:53.58#ibcon#flushed, iclass 24, count 0 2006.285.18:18:53.58#ibcon#about to write, iclass 24, count 0 2006.285.18:18:53.58#ibcon#wrote, iclass 24, count 0 2006.285.18:18:53.58#ibcon#about to read 3, iclass 24, count 0 2006.285.18:18:53.60#ibcon#read 3, iclass 24, count 0 2006.285.18:18:53.60#ibcon#about to read 4, iclass 24, count 0 2006.285.18:18:53.60#ibcon#read 4, iclass 24, count 0 2006.285.18:18:53.60#ibcon#about to read 5, iclass 24, count 0 2006.285.18:18:53.60#ibcon#read 5, iclass 24, count 0 2006.285.18:18:53.60#ibcon#about to read 6, iclass 24, count 0 2006.285.18:18:53.60#ibcon#read 6, iclass 24, count 0 2006.285.18:18:53.60#ibcon#end of sib2, iclass 24, count 0 2006.285.18:18:53.60#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:18:53.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:18:53.60#ibcon#[27=USB\r\n] 2006.285.18:18:53.60#ibcon#*before write, iclass 24, count 0 2006.285.18:18:53.60#ibcon#enter sib2, iclass 24, count 0 2006.285.18:18:53.60#ibcon#flushed, iclass 24, count 0 2006.285.18:18:53.60#ibcon#about to write, iclass 24, count 0 2006.285.18:18:53.60#ibcon#wrote, iclass 24, count 0 2006.285.18:18:53.60#ibcon#about to read 3, iclass 24, count 0 2006.285.18:18:53.63#ibcon#read 3, iclass 24, count 0 2006.285.18:18:53.63#ibcon#about to read 4, iclass 24, count 0 2006.285.18:18:53.63#ibcon#read 4, iclass 24, count 0 2006.285.18:18:53.63#ibcon#about to read 5, iclass 24, count 0 2006.285.18:18:53.63#ibcon#read 5, iclass 24, count 0 2006.285.18:18:53.63#ibcon#about to read 6, iclass 24, count 0 2006.285.18:18:53.63#ibcon#read 6, iclass 24, count 0 2006.285.18:18:53.63#ibcon#end of sib2, iclass 24, count 0 2006.285.18:18:53.63#ibcon#*after write, iclass 24, count 0 2006.285.18:18:53.63#ibcon#*before return 0, iclass 24, count 0 2006.285.18:18:53.63#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:18:53.63#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:18:53.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:18:53.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:18:53.63$vck44/vblo=3,649.99 2006.285.18:18:53.63#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.18:18:53.63#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.18:18:53.63#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:53.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:18:53.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:18:53.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:18:53.63#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:18:53.63#ibcon#first serial, iclass 26, count 0 2006.285.18:18:53.63#ibcon#enter sib2, iclass 26, count 0 2006.285.18:18:53.63#ibcon#flushed, iclass 26, count 0 2006.285.18:18:53.63#ibcon#about to write, iclass 26, count 0 2006.285.18:18:53.63#ibcon#wrote, iclass 26, count 0 2006.285.18:18:53.63#ibcon#about to read 3, iclass 26, count 0 2006.285.18:18:53.65#ibcon#read 3, iclass 26, count 0 2006.285.18:18:53.65#ibcon#about to read 4, iclass 26, count 0 2006.285.18:18:53.65#ibcon#read 4, iclass 26, count 0 2006.285.18:18:53.65#ibcon#about to read 5, iclass 26, count 0 2006.285.18:18:53.65#ibcon#read 5, iclass 26, count 0 2006.285.18:18:53.65#ibcon#about to read 6, iclass 26, count 0 2006.285.18:18:53.65#ibcon#read 6, iclass 26, count 0 2006.285.18:18:53.65#ibcon#end of sib2, iclass 26, count 0 2006.285.18:18:53.65#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:18:53.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:18:53.65#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.18:18:53.65#ibcon#*before write, iclass 26, count 0 2006.285.18:18:53.65#ibcon#enter sib2, iclass 26, count 0 2006.285.18:18:53.65#ibcon#flushed, iclass 26, count 0 2006.285.18:18:53.65#ibcon#about to write, iclass 26, count 0 2006.285.18:18:53.65#ibcon#wrote, iclass 26, count 0 2006.285.18:18:53.65#ibcon#about to read 3, iclass 26, count 0 2006.285.18:18:53.69#ibcon#read 3, iclass 26, count 0 2006.285.18:18:53.69#ibcon#about to read 4, iclass 26, count 0 2006.285.18:18:53.69#ibcon#read 4, iclass 26, count 0 2006.285.18:18:53.69#ibcon#about to read 5, iclass 26, count 0 2006.285.18:18:53.69#ibcon#read 5, iclass 26, count 0 2006.285.18:18:53.69#ibcon#about to read 6, iclass 26, count 0 2006.285.18:18:53.69#ibcon#read 6, iclass 26, count 0 2006.285.18:18:53.69#ibcon#end of sib2, iclass 26, count 0 2006.285.18:18:53.69#ibcon#*after write, iclass 26, count 0 2006.285.18:18:53.69#ibcon#*before return 0, iclass 26, count 0 2006.285.18:18:53.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:18:53.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:18:53.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:18:53.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:18:53.69$vck44/vb=3,4 2006.285.18:18:53.69#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.18:18:53.69#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.18:18:53.69#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:53.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:18:53.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:18:53.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:18:53.75#ibcon#enter wrdev, iclass 28, count 2 2006.285.18:18:53.75#ibcon#first serial, iclass 28, count 2 2006.285.18:18:53.75#ibcon#enter sib2, iclass 28, count 2 2006.285.18:18:53.75#ibcon#flushed, iclass 28, count 2 2006.285.18:18:53.75#ibcon#about to write, iclass 28, count 2 2006.285.18:18:53.75#ibcon#wrote, iclass 28, count 2 2006.285.18:18:53.75#ibcon#about to read 3, iclass 28, count 2 2006.285.18:18:53.77#ibcon#read 3, iclass 28, count 2 2006.285.18:18:53.77#ibcon#about to read 4, iclass 28, count 2 2006.285.18:18:53.77#ibcon#read 4, iclass 28, count 2 2006.285.18:18:53.77#ibcon#about to read 5, iclass 28, count 2 2006.285.18:18:53.77#ibcon#read 5, iclass 28, count 2 2006.285.18:18:53.77#ibcon#about to read 6, iclass 28, count 2 2006.285.18:18:53.77#ibcon#read 6, iclass 28, count 2 2006.285.18:18:53.77#ibcon#end of sib2, iclass 28, count 2 2006.285.18:18:53.77#ibcon#*mode == 0, iclass 28, count 2 2006.285.18:18:53.77#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.18:18:53.77#ibcon#[27=AT03-04\r\n] 2006.285.18:18:53.77#ibcon#*before write, iclass 28, count 2 2006.285.18:18:53.77#ibcon#enter sib2, iclass 28, count 2 2006.285.18:18:53.77#ibcon#flushed, iclass 28, count 2 2006.285.18:18:53.77#ibcon#about to write, iclass 28, count 2 2006.285.18:18:53.77#ibcon#wrote, iclass 28, count 2 2006.285.18:18:53.77#ibcon#about to read 3, iclass 28, count 2 2006.285.18:18:53.80#ibcon#read 3, iclass 28, count 2 2006.285.18:18:53.80#ibcon#about to read 4, iclass 28, count 2 2006.285.18:18:53.80#ibcon#read 4, iclass 28, count 2 2006.285.18:18:53.80#ibcon#about to read 5, iclass 28, count 2 2006.285.18:18:53.80#ibcon#read 5, iclass 28, count 2 2006.285.18:18:53.80#ibcon#about to read 6, iclass 28, count 2 2006.285.18:18:53.80#ibcon#read 6, iclass 28, count 2 2006.285.18:18:53.80#ibcon#end of sib2, iclass 28, count 2 2006.285.18:18:53.80#ibcon#*after write, iclass 28, count 2 2006.285.18:18:53.80#ibcon#*before return 0, iclass 28, count 2 2006.285.18:18:53.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:18:53.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:18:53.80#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.18:18:53.80#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:53.80#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:18:53.92#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:18:53.92#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:18:53.92#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:18:53.92#ibcon#first serial, iclass 28, count 0 2006.285.18:18:53.92#ibcon#enter sib2, iclass 28, count 0 2006.285.18:18:53.92#ibcon#flushed, iclass 28, count 0 2006.285.18:18:53.92#ibcon#about to write, iclass 28, count 0 2006.285.18:18:53.92#ibcon#wrote, iclass 28, count 0 2006.285.18:18:53.92#ibcon#about to read 3, iclass 28, count 0 2006.285.18:18:53.94#ibcon#read 3, iclass 28, count 0 2006.285.18:18:53.94#ibcon#about to read 4, iclass 28, count 0 2006.285.18:18:53.94#ibcon#read 4, iclass 28, count 0 2006.285.18:18:53.94#ibcon#about to read 5, iclass 28, count 0 2006.285.18:18:53.94#ibcon#read 5, iclass 28, count 0 2006.285.18:18:53.94#ibcon#about to read 6, iclass 28, count 0 2006.285.18:18:53.94#ibcon#read 6, iclass 28, count 0 2006.285.18:18:53.94#ibcon#end of sib2, iclass 28, count 0 2006.285.18:18:53.94#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:18:53.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:18:53.94#ibcon#[27=USB\r\n] 2006.285.18:18:53.94#ibcon#*before write, iclass 28, count 0 2006.285.18:18:53.94#ibcon#enter sib2, iclass 28, count 0 2006.285.18:18:53.94#ibcon#flushed, iclass 28, count 0 2006.285.18:18:53.94#ibcon#about to write, iclass 28, count 0 2006.285.18:18:53.94#ibcon#wrote, iclass 28, count 0 2006.285.18:18:53.94#ibcon#about to read 3, iclass 28, count 0 2006.285.18:18:53.97#ibcon#read 3, iclass 28, count 0 2006.285.18:18:53.97#ibcon#about to read 4, iclass 28, count 0 2006.285.18:18:53.97#ibcon#read 4, iclass 28, count 0 2006.285.18:18:53.97#ibcon#about to read 5, iclass 28, count 0 2006.285.18:18:53.97#ibcon#read 5, iclass 28, count 0 2006.285.18:18:53.97#ibcon#about to read 6, iclass 28, count 0 2006.285.18:18:53.97#ibcon#read 6, iclass 28, count 0 2006.285.18:18:53.97#ibcon#end of sib2, iclass 28, count 0 2006.285.18:18:53.97#ibcon#*after write, iclass 28, count 0 2006.285.18:18:53.97#ibcon#*before return 0, iclass 28, count 0 2006.285.18:18:53.97#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:18:53.97#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:18:53.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:18:53.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:18:53.97$vck44/vblo=4,679.99 2006.285.18:18:53.97#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.18:18:53.97#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.18:18:53.97#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:53.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:18:53.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:18:53.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:18:53.97#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:18:53.97#ibcon#first serial, iclass 30, count 0 2006.285.18:18:53.97#ibcon#enter sib2, iclass 30, count 0 2006.285.18:18:53.97#ibcon#flushed, iclass 30, count 0 2006.285.18:18:53.97#ibcon#about to write, iclass 30, count 0 2006.285.18:18:53.97#ibcon#wrote, iclass 30, count 0 2006.285.18:18:53.97#ibcon#about to read 3, iclass 30, count 0 2006.285.18:18:53.99#ibcon#read 3, iclass 30, count 0 2006.285.18:18:54.07#ibcon#about to read 4, iclass 30, count 0 2006.285.18:18:54.07#ibcon#read 4, iclass 30, count 0 2006.285.18:18:54.07#ibcon#about to read 5, iclass 30, count 0 2006.285.18:18:54.07#ibcon#read 5, iclass 30, count 0 2006.285.18:18:54.07#ibcon#about to read 6, iclass 30, count 0 2006.285.18:18:54.07#ibcon#read 6, iclass 30, count 0 2006.285.18:18:54.07#ibcon#end of sib2, iclass 30, count 0 2006.285.18:18:54.07#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:18:54.07#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:18:54.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.18:18:54.07#ibcon#*before write, iclass 30, count 0 2006.285.18:18:54.07#ibcon#enter sib2, iclass 30, count 0 2006.285.18:18:54.07#ibcon#flushed, iclass 30, count 0 2006.285.18:18:54.07#ibcon#about to write, iclass 30, count 0 2006.285.18:18:54.07#ibcon#wrote, iclass 30, count 0 2006.285.18:18:54.07#ibcon#about to read 3, iclass 30, count 0 2006.285.18:18:54.11#ibcon#read 3, iclass 30, count 0 2006.285.18:18:54.11#ibcon#about to read 4, iclass 30, count 0 2006.285.18:18:54.11#ibcon#read 4, iclass 30, count 0 2006.285.18:18:54.11#ibcon#about to read 5, iclass 30, count 0 2006.285.18:18:54.11#ibcon#read 5, iclass 30, count 0 2006.285.18:18:54.11#ibcon#about to read 6, iclass 30, count 0 2006.285.18:18:54.11#ibcon#read 6, iclass 30, count 0 2006.285.18:18:54.11#ibcon#end of sib2, iclass 30, count 0 2006.285.18:18:54.11#ibcon#*after write, iclass 30, count 0 2006.285.18:18:54.11#ibcon#*before return 0, iclass 30, count 0 2006.285.18:18:54.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:18:54.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:18:54.11#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:18:54.11#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:18:54.11$vck44/vb=4,5 2006.285.18:18:54.11#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.18:18:54.11#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.18:18:54.11#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:54.11#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:18:54.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:18:54.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:18:54.11#ibcon#enter wrdev, iclass 32, count 2 2006.285.18:18:54.11#ibcon#first serial, iclass 32, count 2 2006.285.18:18:54.11#ibcon#enter sib2, iclass 32, count 2 2006.285.18:18:54.11#ibcon#flushed, iclass 32, count 2 2006.285.18:18:54.11#ibcon#about to write, iclass 32, count 2 2006.285.18:18:54.11#ibcon#wrote, iclass 32, count 2 2006.285.18:18:54.11#ibcon#about to read 3, iclass 32, count 2 2006.285.18:18:54.13#ibcon#read 3, iclass 32, count 2 2006.285.18:18:54.13#ibcon#about to read 4, iclass 32, count 2 2006.285.18:18:54.13#ibcon#read 4, iclass 32, count 2 2006.285.18:18:54.13#ibcon#about to read 5, iclass 32, count 2 2006.285.18:18:54.13#ibcon#read 5, iclass 32, count 2 2006.285.18:18:54.13#ibcon#about to read 6, iclass 32, count 2 2006.285.18:18:54.13#ibcon#read 6, iclass 32, count 2 2006.285.18:18:54.13#ibcon#end of sib2, iclass 32, count 2 2006.285.18:18:54.13#ibcon#*mode == 0, iclass 32, count 2 2006.285.18:18:54.13#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.18:18:54.13#ibcon#[27=AT04-05\r\n] 2006.285.18:18:54.13#ibcon#*before write, iclass 32, count 2 2006.285.18:18:54.13#ibcon#enter sib2, iclass 32, count 2 2006.285.18:18:54.13#ibcon#flushed, iclass 32, count 2 2006.285.18:18:54.13#ibcon#about to write, iclass 32, count 2 2006.285.18:18:54.13#ibcon#wrote, iclass 32, count 2 2006.285.18:18:54.13#ibcon#about to read 3, iclass 32, count 2 2006.285.18:18:54.16#ibcon#read 3, iclass 32, count 2 2006.285.18:18:54.16#ibcon#about to read 4, iclass 32, count 2 2006.285.18:18:54.16#ibcon#read 4, iclass 32, count 2 2006.285.18:18:54.16#ibcon#about to read 5, iclass 32, count 2 2006.285.18:18:54.16#ibcon#read 5, iclass 32, count 2 2006.285.18:18:54.16#ibcon#about to read 6, iclass 32, count 2 2006.285.18:18:54.16#ibcon#read 6, iclass 32, count 2 2006.285.18:18:54.16#ibcon#end of sib2, iclass 32, count 2 2006.285.18:18:54.16#ibcon#*after write, iclass 32, count 2 2006.285.18:18:54.16#ibcon#*before return 0, iclass 32, count 2 2006.285.18:18:54.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:18:54.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:18:54.16#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.18:18:54.16#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:54.16#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:18:54.28#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:18:54.28#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:18:54.28#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:18:54.28#ibcon#first serial, iclass 32, count 0 2006.285.18:18:54.28#ibcon#enter sib2, iclass 32, count 0 2006.285.18:18:54.28#ibcon#flushed, iclass 32, count 0 2006.285.18:18:54.28#ibcon#about to write, iclass 32, count 0 2006.285.18:18:54.28#ibcon#wrote, iclass 32, count 0 2006.285.18:18:54.28#ibcon#about to read 3, iclass 32, count 0 2006.285.18:18:54.30#ibcon#read 3, iclass 32, count 0 2006.285.18:18:54.30#ibcon#about to read 4, iclass 32, count 0 2006.285.18:18:54.30#ibcon#read 4, iclass 32, count 0 2006.285.18:18:54.30#ibcon#about to read 5, iclass 32, count 0 2006.285.18:18:54.30#ibcon#read 5, iclass 32, count 0 2006.285.18:18:54.30#ibcon#about to read 6, iclass 32, count 0 2006.285.18:18:54.30#ibcon#read 6, iclass 32, count 0 2006.285.18:18:54.30#ibcon#end of sib2, iclass 32, count 0 2006.285.18:18:54.30#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:18:54.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:18:54.30#ibcon#[27=USB\r\n] 2006.285.18:18:54.30#ibcon#*before write, iclass 32, count 0 2006.285.18:18:54.30#ibcon#enter sib2, iclass 32, count 0 2006.285.18:18:54.30#ibcon#flushed, iclass 32, count 0 2006.285.18:18:54.30#ibcon#about to write, iclass 32, count 0 2006.285.18:18:54.30#ibcon#wrote, iclass 32, count 0 2006.285.18:18:54.30#ibcon#about to read 3, iclass 32, count 0 2006.285.18:18:54.33#ibcon#read 3, iclass 32, count 0 2006.285.18:18:54.33#ibcon#about to read 4, iclass 32, count 0 2006.285.18:18:54.33#ibcon#read 4, iclass 32, count 0 2006.285.18:18:54.33#ibcon#about to read 5, iclass 32, count 0 2006.285.18:18:54.33#ibcon#read 5, iclass 32, count 0 2006.285.18:18:54.33#ibcon#about to read 6, iclass 32, count 0 2006.285.18:18:54.33#ibcon#read 6, iclass 32, count 0 2006.285.18:18:54.33#ibcon#end of sib2, iclass 32, count 0 2006.285.18:18:54.33#ibcon#*after write, iclass 32, count 0 2006.285.18:18:54.33#ibcon#*before return 0, iclass 32, count 0 2006.285.18:18:54.33#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:18:54.33#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:18:54.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:18:54.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:18:54.33$vck44/vblo=5,709.99 2006.285.18:18:54.33#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.18:18:54.33#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.18:18:54.33#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:54.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:18:54.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:18:54.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:18:54.33#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:18:54.33#ibcon#first serial, iclass 34, count 0 2006.285.18:18:54.33#ibcon#enter sib2, iclass 34, count 0 2006.285.18:18:54.33#ibcon#flushed, iclass 34, count 0 2006.285.18:18:54.33#ibcon#about to write, iclass 34, count 0 2006.285.18:18:54.33#ibcon#wrote, iclass 34, count 0 2006.285.18:18:54.33#ibcon#about to read 3, iclass 34, count 0 2006.285.18:18:54.35#ibcon#read 3, iclass 34, count 0 2006.285.18:18:54.35#ibcon#about to read 4, iclass 34, count 0 2006.285.18:18:54.35#ibcon#read 4, iclass 34, count 0 2006.285.18:18:54.35#ibcon#about to read 5, iclass 34, count 0 2006.285.18:18:54.35#ibcon#read 5, iclass 34, count 0 2006.285.18:18:54.35#ibcon#about to read 6, iclass 34, count 0 2006.285.18:18:54.35#ibcon#read 6, iclass 34, count 0 2006.285.18:18:54.35#ibcon#end of sib2, iclass 34, count 0 2006.285.18:18:54.35#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:18:54.35#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:18:54.35#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.18:18:54.35#ibcon#*before write, iclass 34, count 0 2006.285.18:18:54.35#ibcon#enter sib2, iclass 34, count 0 2006.285.18:18:54.35#ibcon#flushed, iclass 34, count 0 2006.285.18:18:54.35#ibcon#about to write, iclass 34, count 0 2006.285.18:18:54.35#ibcon#wrote, iclass 34, count 0 2006.285.18:18:54.35#ibcon#about to read 3, iclass 34, count 0 2006.285.18:18:54.39#ibcon#read 3, iclass 34, count 0 2006.285.18:18:54.39#ibcon#about to read 4, iclass 34, count 0 2006.285.18:18:54.39#ibcon#read 4, iclass 34, count 0 2006.285.18:18:54.39#ibcon#about to read 5, iclass 34, count 0 2006.285.18:18:54.39#ibcon#read 5, iclass 34, count 0 2006.285.18:18:54.39#ibcon#about to read 6, iclass 34, count 0 2006.285.18:18:54.39#ibcon#read 6, iclass 34, count 0 2006.285.18:18:54.39#ibcon#end of sib2, iclass 34, count 0 2006.285.18:18:54.39#ibcon#*after write, iclass 34, count 0 2006.285.18:18:54.39#ibcon#*before return 0, iclass 34, count 0 2006.285.18:18:54.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:18:54.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:18:54.39#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:18:54.39#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:18:54.39$vck44/vb=5,4 2006.285.18:18:54.39#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.18:18:54.39#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.18:18:54.39#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:54.39#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:18:54.45#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:18:54.45#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:18:54.45#ibcon#enter wrdev, iclass 36, count 2 2006.285.18:18:54.45#ibcon#first serial, iclass 36, count 2 2006.285.18:18:54.45#ibcon#enter sib2, iclass 36, count 2 2006.285.18:18:54.45#ibcon#flushed, iclass 36, count 2 2006.285.18:18:54.45#ibcon#about to write, iclass 36, count 2 2006.285.18:18:54.45#ibcon#wrote, iclass 36, count 2 2006.285.18:18:54.45#ibcon#about to read 3, iclass 36, count 2 2006.285.18:18:54.47#ibcon#read 3, iclass 36, count 2 2006.285.18:18:54.47#ibcon#about to read 4, iclass 36, count 2 2006.285.18:18:54.47#ibcon#read 4, iclass 36, count 2 2006.285.18:18:54.47#ibcon#about to read 5, iclass 36, count 2 2006.285.18:18:54.47#ibcon#read 5, iclass 36, count 2 2006.285.18:18:54.47#ibcon#about to read 6, iclass 36, count 2 2006.285.18:18:54.47#ibcon#read 6, iclass 36, count 2 2006.285.18:18:54.47#ibcon#end of sib2, iclass 36, count 2 2006.285.18:18:54.47#ibcon#*mode == 0, iclass 36, count 2 2006.285.18:18:54.47#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.18:18:54.47#ibcon#[27=AT05-04\r\n] 2006.285.18:18:54.47#ibcon#*before write, iclass 36, count 2 2006.285.18:18:54.47#ibcon#enter sib2, iclass 36, count 2 2006.285.18:18:54.47#ibcon#flushed, iclass 36, count 2 2006.285.18:18:54.47#ibcon#about to write, iclass 36, count 2 2006.285.18:18:54.47#ibcon#wrote, iclass 36, count 2 2006.285.18:18:54.47#ibcon#about to read 3, iclass 36, count 2 2006.285.18:18:54.50#ibcon#read 3, iclass 36, count 2 2006.285.18:18:54.50#ibcon#about to read 4, iclass 36, count 2 2006.285.18:18:54.50#ibcon#read 4, iclass 36, count 2 2006.285.18:18:54.50#ibcon#about to read 5, iclass 36, count 2 2006.285.18:18:54.50#ibcon#read 5, iclass 36, count 2 2006.285.18:18:54.50#ibcon#about to read 6, iclass 36, count 2 2006.285.18:18:54.50#ibcon#read 6, iclass 36, count 2 2006.285.18:18:54.50#ibcon#end of sib2, iclass 36, count 2 2006.285.18:18:54.50#ibcon#*after write, iclass 36, count 2 2006.285.18:18:54.50#ibcon#*before return 0, iclass 36, count 2 2006.285.18:18:54.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:18:54.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:18:54.50#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.18:18:54.50#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:54.50#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:18:54.62#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:18:54.62#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:18:54.62#ibcon#enter wrdev, iclass 36, count 0 2006.285.18:18:54.62#ibcon#first serial, iclass 36, count 0 2006.285.18:18:54.62#ibcon#enter sib2, iclass 36, count 0 2006.285.18:18:54.62#ibcon#flushed, iclass 36, count 0 2006.285.18:18:54.62#ibcon#about to write, iclass 36, count 0 2006.285.18:18:54.62#ibcon#wrote, iclass 36, count 0 2006.285.18:18:54.62#ibcon#about to read 3, iclass 36, count 0 2006.285.18:18:54.64#ibcon#read 3, iclass 36, count 0 2006.285.18:18:54.64#ibcon#about to read 4, iclass 36, count 0 2006.285.18:18:54.64#ibcon#read 4, iclass 36, count 0 2006.285.18:18:54.64#ibcon#about to read 5, iclass 36, count 0 2006.285.18:18:54.64#ibcon#read 5, iclass 36, count 0 2006.285.18:18:54.64#ibcon#about to read 6, iclass 36, count 0 2006.285.18:18:54.64#ibcon#read 6, iclass 36, count 0 2006.285.18:18:54.64#ibcon#end of sib2, iclass 36, count 0 2006.285.18:18:54.64#ibcon#*mode == 0, iclass 36, count 0 2006.285.18:18:54.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.18:18:54.64#ibcon#[27=USB\r\n] 2006.285.18:18:54.64#ibcon#*before write, iclass 36, count 0 2006.285.18:18:54.64#ibcon#enter sib2, iclass 36, count 0 2006.285.18:18:54.64#ibcon#flushed, iclass 36, count 0 2006.285.18:18:54.64#ibcon#about to write, iclass 36, count 0 2006.285.18:18:54.64#ibcon#wrote, iclass 36, count 0 2006.285.18:18:54.64#ibcon#about to read 3, iclass 36, count 0 2006.285.18:18:54.67#ibcon#read 3, iclass 36, count 0 2006.285.18:18:54.67#ibcon#about to read 4, iclass 36, count 0 2006.285.18:18:54.67#ibcon#read 4, iclass 36, count 0 2006.285.18:18:54.67#ibcon#about to read 5, iclass 36, count 0 2006.285.18:18:54.67#ibcon#read 5, iclass 36, count 0 2006.285.18:18:54.67#ibcon#about to read 6, iclass 36, count 0 2006.285.18:18:54.67#ibcon#read 6, iclass 36, count 0 2006.285.18:18:54.67#ibcon#end of sib2, iclass 36, count 0 2006.285.18:18:54.67#ibcon#*after write, iclass 36, count 0 2006.285.18:18:54.67#ibcon#*before return 0, iclass 36, count 0 2006.285.18:18:54.67#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:18:54.67#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:18:54.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.18:18:54.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.18:18:54.67$vck44/vblo=6,719.99 2006.285.18:18:54.67#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.18:18:54.67#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.18:18:54.67#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:54.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:18:54.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:18:54.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:18:54.67#ibcon#enter wrdev, iclass 38, count 0 2006.285.18:18:54.67#ibcon#first serial, iclass 38, count 0 2006.285.18:18:54.67#ibcon#enter sib2, iclass 38, count 0 2006.285.18:18:54.67#ibcon#flushed, iclass 38, count 0 2006.285.18:18:54.67#ibcon#about to write, iclass 38, count 0 2006.285.18:18:54.67#ibcon#wrote, iclass 38, count 0 2006.285.18:18:54.67#ibcon#about to read 3, iclass 38, count 0 2006.285.18:18:54.69#ibcon#read 3, iclass 38, count 0 2006.285.18:18:54.69#ibcon#about to read 4, iclass 38, count 0 2006.285.18:18:54.69#ibcon#read 4, iclass 38, count 0 2006.285.18:18:54.69#ibcon#about to read 5, iclass 38, count 0 2006.285.18:18:54.69#ibcon#read 5, iclass 38, count 0 2006.285.18:18:54.69#ibcon#about to read 6, iclass 38, count 0 2006.285.18:18:54.69#ibcon#read 6, iclass 38, count 0 2006.285.18:18:54.69#ibcon#end of sib2, iclass 38, count 0 2006.285.18:18:54.69#ibcon#*mode == 0, iclass 38, count 0 2006.285.18:18:54.69#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.18:18:54.69#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.18:18:54.69#ibcon#*before write, iclass 38, count 0 2006.285.18:18:54.69#ibcon#enter sib2, iclass 38, count 0 2006.285.18:18:54.69#ibcon#flushed, iclass 38, count 0 2006.285.18:18:54.69#ibcon#about to write, iclass 38, count 0 2006.285.18:18:54.69#ibcon#wrote, iclass 38, count 0 2006.285.18:18:54.69#ibcon#about to read 3, iclass 38, count 0 2006.285.18:18:54.73#ibcon#read 3, iclass 38, count 0 2006.285.18:18:54.73#ibcon#about to read 4, iclass 38, count 0 2006.285.18:18:54.73#ibcon#read 4, iclass 38, count 0 2006.285.18:18:54.73#ibcon#about to read 5, iclass 38, count 0 2006.285.18:18:54.73#ibcon#read 5, iclass 38, count 0 2006.285.18:18:54.73#ibcon#about to read 6, iclass 38, count 0 2006.285.18:18:54.73#ibcon#read 6, iclass 38, count 0 2006.285.18:18:54.73#ibcon#end of sib2, iclass 38, count 0 2006.285.18:18:54.73#ibcon#*after write, iclass 38, count 0 2006.285.18:18:54.73#ibcon#*before return 0, iclass 38, count 0 2006.285.18:18:54.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:18:54.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:18:54.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.18:18:54.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.18:18:54.73$vck44/vb=6,3 2006.285.18:18:54.73#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.18:18:54.73#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.18:18:54.73#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:54.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:18:54.79#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:18:54.79#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:18:54.79#ibcon#enter wrdev, iclass 40, count 2 2006.285.18:18:54.79#ibcon#first serial, iclass 40, count 2 2006.285.18:18:54.79#ibcon#enter sib2, iclass 40, count 2 2006.285.18:18:54.79#ibcon#flushed, iclass 40, count 2 2006.285.18:18:54.79#ibcon#about to write, iclass 40, count 2 2006.285.18:18:54.79#ibcon#wrote, iclass 40, count 2 2006.285.18:18:54.79#ibcon#about to read 3, iclass 40, count 2 2006.285.18:18:54.81#ibcon#read 3, iclass 40, count 2 2006.285.18:18:54.81#ibcon#about to read 4, iclass 40, count 2 2006.285.18:18:54.81#ibcon#read 4, iclass 40, count 2 2006.285.18:18:54.81#ibcon#about to read 5, iclass 40, count 2 2006.285.18:18:54.81#ibcon#read 5, iclass 40, count 2 2006.285.18:18:54.81#ibcon#about to read 6, iclass 40, count 2 2006.285.18:18:54.81#ibcon#read 6, iclass 40, count 2 2006.285.18:18:54.81#ibcon#end of sib2, iclass 40, count 2 2006.285.18:18:54.81#ibcon#*mode == 0, iclass 40, count 2 2006.285.18:18:54.81#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.18:18:54.81#ibcon#[27=AT06-03\r\n] 2006.285.18:18:54.81#ibcon#*before write, iclass 40, count 2 2006.285.18:18:54.81#ibcon#enter sib2, iclass 40, count 2 2006.285.18:18:54.81#ibcon#flushed, iclass 40, count 2 2006.285.18:18:54.81#ibcon#about to write, iclass 40, count 2 2006.285.18:18:54.81#ibcon#wrote, iclass 40, count 2 2006.285.18:18:54.81#ibcon#about to read 3, iclass 40, count 2 2006.285.18:18:54.84#ibcon#read 3, iclass 40, count 2 2006.285.18:18:54.84#ibcon#about to read 4, iclass 40, count 2 2006.285.18:18:54.84#ibcon#read 4, iclass 40, count 2 2006.285.18:18:54.84#ibcon#about to read 5, iclass 40, count 2 2006.285.18:18:54.84#ibcon#read 5, iclass 40, count 2 2006.285.18:18:54.84#ibcon#about to read 6, iclass 40, count 2 2006.285.18:18:54.84#ibcon#read 6, iclass 40, count 2 2006.285.18:18:54.84#ibcon#end of sib2, iclass 40, count 2 2006.285.18:18:54.84#ibcon#*after write, iclass 40, count 2 2006.285.18:18:54.84#ibcon#*before return 0, iclass 40, count 2 2006.285.18:18:54.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:18:54.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:18:54.84#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.18:18:54.84#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:54.84#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:18:54.96#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:18:54.96#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:18:54.96#ibcon#enter wrdev, iclass 40, count 0 2006.285.18:18:54.96#ibcon#first serial, iclass 40, count 0 2006.285.18:18:54.96#ibcon#enter sib2, iclass 40, count 0 2006.285.18:18:54.96#ibcon#flushed, iclass 40, count 0 2006.285.18:18:54.96#ibcon#about to write, iclass 40, count 0 2006.285.18:18:54.96#ibcon#wrote, iclass 40, count 0 2006.285.18:18:54.96#ibcon#about to read 3, iclass 40, count 0 2006.285.18:18:54.98#ibcon#read 3, iclass 40, count 0 2006.285.18:18:54.98#ibcon#about to read 4, iclass 40, count 0 2006.285.18:18:54.98#ibcon#read 4, iclass 40, count 0 2006.285.18:18:54.98#ibcon#about to read 5, iclass 40, count 0 2006.285.18:18:54.98#ibcon#read 5, iclass 40, count 0 2006.285.18:18:54.98#ibcon#about to read 6, iclass 40, count 0 2006.285.18:18:54.98#ibcon#read 6, iclass 40, count 0 2006.285.18:18:54.98#ibcon#end of sib2, iclass 40, count 0 2006.285.18:18:54.98#ibcon#*mode == 0, iclass 40, count 0 2006.285.18:18:54.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.18:18:54.98#ibcon#[27=USB\r\n] 2006.285.18:18:54.98#ibcon#*before write, iclass 40, count 0 2006.285.18:18:54.98#ibcon#enter sib2, iclass 40, count 0 2006.285.18:18:54.98#ibcon#flushed, iclass 40, count 0 2006.285.18:18:54.98#ibcon#about to write, iclass 40, count 0 2006.285.18:18:54.98#ibcon#wrote, iclass 40, count 0 2006.285.18:18:54.98#ibcon#about to read 3, iclass 40, count 0 2006.285.18:18:55.01#ibcon#read 3, iclass 40, count 0 2006.285.18:18:55.01#ibcon#about to read 4, iclass 40, count 0 2006.285.18:18:55.01#ibcon#read 4, iclass 40, count 0 2006.285.18:18:55.01#ibcon#about to read 5, iclass 40, count 0 2006.285.18:18:55.01#ibcon#read 5, iclass 40, count 0 2006.285.18:18:55.01#ibcon#about to read 6, iclass 40, count 0 2006.285.18:18:55.01#ibcon#read 6, iclass 40, count 0 2006.285.18:18:55.01#ibcon#end of sib2, iclass 40, count 0 2006.285.18:18:55.01#ibcon#*after write, iclass 40, count 0 2006.285.18:18:55.01#ibcon#*before return 0, iclass 40, count 0 2006.285.18:18:55.01#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:18:55.01#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:18:55.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.18:18:55.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.18:18:55.01$vck44/vblo=7,734.99 2006.285.18:18:55.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.18:18:55.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.18:18:55.01#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:55.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:18:55.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:18:55.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:18:55.01#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:18:55.01#ibcon#first serial, iclass 4, count 0 2006.285.18:18:55.01#ibcon#enter sib2, iclass 4, count 0 2006.285.18:18:55.01#ibcon#flushed, iclass 4, count 0 2006.285.18:18:55.01#ibcon#about to write, iclass 4, count 0 2006.285.18:18:55.01#ibcon#wrote, iclass 4, count 0 2006.285.18:18:55.01#ibcon#about to read 3, iclass 4, count 0 2006.285.18:18:55.03#ibcon#read 3, iclass 4, count 0 2006.285.18:18:55.07#ibcon#about to read 4, iclass 4, count 0 2006.285.18:18:55.07#ibcon#read 4, iclass 4, count 0 2006.285.18:18:55.07#ibcon#about to read 5, iclass 4, count 0 2006.285.18:18:55.07#ibcon#read 5, iclass 4, count 0 2006.285.18:18:55.07#ibcon#about to read 6, iclass 4, count 0 2006.285.18:18:55.07#ibcon#read 6, iclass 4, count 0 2006.285.18:18:55.07#ibcon#end of sib2, iclass 4, count 0 2006.285.18:18:55.07#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:18:55.07#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:18:55.07#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.18:18:55.07#ibcon#*before write, iclass 4, count 0 2006.285.18:18:55.07#ibcon#enter sib2, iclass 4, count 0 2006.285.18:18:55.07#ibcon#flushed, iclass 4, count 0 2006.285.18:18:55.07#ibcon#about to write, iclass 4, count 0 2006.285.18:18:55.07#ibcon#wrote, iclass 4, count 0 2006.285.18:18:55.07#ibcon#about to read 3, iclass 4, count 0 2006.285.18:18:55.12#ibcon#read 3, iclass 4, count 0 2006.285.18:18:55.12#ibcon#about to read 4, iclass 4, count 0 2006.285.18:18:55.12#ibcon#read 4, iclass 4, count 0 2006.285.18:18:55.12#ibcon#about to read 5, iclass 4, count 0 2006.285.18:18:55.12#ibcon#read 5, iclass 4, count 0 2006.285.18:18:55.12#ibcon#about to read 6, iclass 4, count 0 2006.285.18:18:55.12#ibcon#read 6, iclass 4, count 0 2006.285.18:18:55.12#ibcon#end of sib2, iclass 4, count 0 2006.285.18:18:55.12#ibcon#*after write, iclass 4, count 0 2006.285.18:18:55.12#ibcon#*before return 0, iclass 4, count 0 2006.285.18:18:55.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:18:55.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:18:55.12#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:18:55.12#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:18:55.12$vck44/vb=7,4 2006.285.18:18:55.12#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.18:18:55.12#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.18:18:55.12#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:55.12#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:18:55.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:18:55.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:18:55.12#ibcon#enter wrdev, iclass 6, count 2 2006.285.18:18:55.12#ibcon#first serial, iclass 6, count 2 2006.285.18:18:55.12#ibcon#enter sib2, iclass 6, count 2 2006.285.18:18:55.12#ibcon#flushed, iclass 6, count 2 2006.285.18:18:55.12#ibcon#about to write, iclass 6, count 2 2006.285.18:18:55.12#ibcon#wrote, iclass 6, count 2 2006.285.18:18:55.12#ibcon#about to read 3, iclass 6, count 2 2006.285.18:18:55.14#ibcon#read 3, iclass 6, count 2 2006.285.18:18:55.14#ibcon#about to read 4, iclass 6, count 2 2006.285.18:18:55.14#ibcon#read 4, iclass 6, count 2 2006.285.18:18:55.14#ibcon#about to read 5, iclass 6, count 2 2006.285.18:18:55.14#ibcon#read 5, iclass 6, count 2 2006.285.18:18:55.14#ibcon#about to read 6, iclass 6, count 2 2006.285.18:18:55.14#ibcon#read 6, iclass 6, count 2 2006.285.18:18:55.14#ibcon#end of sib2, iclass 6, count 2 2006.285.18:18:55.14#ibcon#*mode == 0, iclass 6, count 2 2006.285.18:18:55.14#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.18:18:55.14#ibcon#[27=AT07-04\r\n] 2006.285.18:18:55.14#ibcon#*before write, iclass 6, count 2 2006.285.18:18:55.14#ibcon#enter sib2, iclass 6, count 2 2006.285.18:18:55.14#ibcon#flushed, iclass 6, count 2 2006.285.18:18:55.14#ibcon#about to write, iclass 6, count 2 2006.285.18:18:55.14#ibcon#wrote, iclass 6, count 2 2006.285.18:18:55.14#ibcon#about to read 3, iclass 6, count 2 2006.285.18:18:55.17#ibcon#read 3, iclass 6, count 2 2006.285.18:18:55.17#ibcon#about to read 4, iclass 6, count 2 2006.285.18:18:55.17#ibcon#read 4, iclass 6, count 2 2006.285.18:18:55.17#ibcon#about to read 5, iclass 6, count 2 2006.285.18:18:55.17#ibcon#read 5, iclass 6, count 2 2006.285.18:18:55.17#ibcon#about to read 6, iclass 6, count 2 2006.285.18:18:55.17#ibcon#read 6, iclass 6, count 2 2006.285.18:18:55.17#ibcon#end of sib2, iclass 6, count 2 2006.285.18:18:55.17#ibcon#*after write, iclass 6, count 2 2006.285.18:18:55.17#ibcon#*before return 0, iclass 6, count 2 2006.285.18:18:55.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:18:55.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:18:55.17#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.18:18:55.17#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:55.17#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:18:55.29#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:18:55.29#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:18:55.29#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:18:55.29#ibcon#first serial, iclass 6, count 0 2006.285.18:18:55.29#ibcon#enter sib2, iclass 6, count 0 2006.285.18:18:55.29#ibcon#flushed, iclass 6, count 0 2006.285.18:18:55.29#ibcon#about to write, iclass 6, count 0 2006.285.18:18:55.29#ibcon#wrote, iclass 6, count 0 2006.285.18:18:55.29#ibcon#about to read 3, iclass 6, count 0 2006.285.18:18:55.31#ibcon#read 3, iclass 6, count 0 2006.285.18:18:55.31#ibcon#about to read 4, iclass 6, count 0 2006.285.18:18:55.31#ibcon#read 4, iclass 6, count 0 2006.285.18:18:55.31#ibcon#about to read 5, iclass 6, count 0 2006.285.18:18:55.31#ibcon#read 5, iclass 6, count 0 2006.285.18:18:55.31#ibcon#about to read 6, iclass 6, count 0 2006.285.18:18:55.31#ibcon#read 6, iclass 6, count 0 2006.285.18:18:55.31#ibcon#end of sib2, iclass 6, count 0 2006.285.18:18:55.31#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:18:55.31#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:18:55.31#ibcon#[27=USB\r\n] 2006.285.18:18:55.31#ibcon#*before write, iclass 6, count 0 2006.285.18:18:55.31#ibcon#enter sib2, iclass 6, count 0 2006.285.18:18:55.31#ibcon#flushed, iclass 6, count 0 2006.285.18:18:55.31#ibcon#about to write, iclass 6, count 0 2006.285.18:18:55.31#ibcon#wrote, iclass 6, count 0 2006.285.18:18:55.31#ibcon#about to read 3, iclass 6, count 0 2006.285.18:18:55.34#ibcon#read 3, iclass 6, count 0 2006.285.18:18:55.34#ibcon#about to read 4, iclass 6, count 0 2006.285.18:18:55.34#ibcon#read 4, iclass 6, count 0 2006.285.18:18:55.34#ibcon#about to read 5, iclass 6, count 0 2006.285.18:18:55.34#ibcon#read 5, iclass 6, count 0 2006.285.18:18:55.34#ibcon#about to read 6, iclass 6, count 0 2006.285.18:18:55.34#ibcon#read 6, iclass 6, count 0 2006.285.18:18:55.34#ibcon#end of sib2, iclass 6, count 0 2006.285.18:18:55.34#ibcon#*after write, iclass 6, count 0 2006.285.18:18:55.34#ibcon#*before return 0, iclass 6, count 0 2006.285.18:18:55.34#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:18:55.34#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:18:55.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:18:55.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:18:55.34$vck44/vblo=8,744.99 2006.285.18:18:55.34#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.18:18:55.34#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.18:18:55.34#ibcon#ireg 17 cls_cnt 0 2006.285.18:18:55.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:18:55.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:18:55.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:18:55.34#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:18:55.34#ibcon#first serial, iclass 10, count 0 2006.285.18:18:55.34#ibcon#enter sib2, iclass 10, count 0 2006.285.18:18:55.34#ibcon#flushed, iclass 10, count 0 2006.285.18:18:55.34#ibcon#about to write, iclass 10, count 0 2006.285.18:18:55.34#ibcon#wrote, iclass 10, count 0 2006.285.18:18:55.34#ibcon#about to read 3, iclass 10, count 0 2006.285.18:18:55.36#ibcon#read 3, iclass 10, count 0 2006.285.18:18:55.36#ibcon#about to read 4, iclass 10, count 0 2006.285.18:18:55.36#ibcon#read 4, iclass 10, count 0 2006.285.18:18:55.36#ibcon#about to read 5, iclass 10, count 0 2006.285.18:18:55.36#ibcon#read 5, iclass 10, count 0 2006.285.18:18:55.36#ibcon#about to read 6, iclass 10, count 0 2006.285.18:18:55.36#ibcon#read 6, iclass 10, count 0 2006.285.18:18:55.36#ibcon#end of sib2, iclass 10, count 0 2006.285.18:18:55.36#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:18:55.36#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:18:55.36#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.18:18:55.36#ibcon#*before write, iclass 10, count 0 2006.285.18:18:55.36#ibcon#enter sib2, iclass 10, count 0 2006.285.18:18:55.36#ibcon#flushed, iclass 10, count 0 2006.285.18:18:55.36#ibcon#about to write, iclass 10, count 0 2006.285.18:18:55.36#ibcon#wrote, iclass 10, count 0 2006.285.18:18:55.36#ibcon#about to read 3, iclass 10, count 0 2006.285.18:18:55.40#ibcon#read 3, iclass 10, count 0 2006.285.18:18:55.40#ibcon#about to read 4, iclass 10, count 0 2006.285.18:18:55.40#ibcon#read 4, iclass 10, count 0 2006.285.18:18:55.40#ibcon#about to read 5, iclass 10, count 0 2006.285.18:18:55.40#ibcon#read 5, iclass 10, count 0 2006.285.18:18:55.40#ibcon#about to read 6, iclass 10, count 0 2006.285.18:18:55.40#ibcon#read 6, iclass 10, count 0 2006.285.18:18:55.40#ibcon#end of sib2, iclass 10, count 0 2006.285.18:18:55.40#ibcon#*after write, iclass 10, count 0 2006.285.18:18:55.40#ibcon#*before return 0, iclass 10, count 0 2006.285.18:18:55.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:18:55.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:18:55.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:18:55.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:18:55.40$vck44/vb=8,4 2006.285.18:18:55.40#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.18:18:55.40#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.18:18:55.40#ibcon#ireg 11 cls_cnt 2 2006.285.18:18:55.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:18:55.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:18:55.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:18:55.46#ibcon#enter wrdev, iclass 12, count 2 2006.285.18:18:55.46#ibcon#first serial, iclass 12, count 2 2006.285.18:18:55.46#ibcon#enter sib2, iclass 12, count 2 2006.285.18:18:55.46#ibcon#flushed, iclass 12, count 2 2006.285.18:18:55.46#ibcon#about to write, iclass 12, count 2 2006.285.18:18:55.46#ibcon#wrote, iclass 12, count 2 2006.285.18:18:55.46#ibcon#about to read 3, iclass 12, count 2 2006.285.18:18:55.48#ibcon#read 3, iclass 12, count 2 2006.285.18:18:55.48#ibcon#about to read 4, iclass 12, count 2 2006.285.18:18:55.48#ibcon#read 4, iclass 12, count 2 2006.285.18:18:55.48#ibcon#about to read 5, iclass 12, count 2 2006.285.18:18:55.48#ibcon#read 5, iclass 12, count 2 2006.285.18:18:55.48#ibcon#about to read 6, iclass 12, count 2 2006.285.18:18:55.48#ibcon#read 6, iclass 12, count 2 2006.285.18:18:55.48#ibcon#end of sib2, iclass 12, count 2 2006.285.18:18:55.48#ibcon#*mode == 0, iclass 12, count 2 2006.285.18:18:55.48#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.18:18:55.48#ibcon#[27=AT08-04\r\n] 2006.285.18:18:55.48#ibcon#*before write, iclass 12, count 2 2006.285.18:18:55.48#ibcon#enter sib2, iclass 12, count 2 2006.285.18:18:55.48#ibcon#flushed, iclass 12, count 2 2006.285.18:18:55.48#ibcon#about to write, iclass 12, count 2 2006.285.18:18:55.48#ibcon#wrote, iclass 12, count 2 2006.285.18:18:55.48#ibcon#about to read 3, iclass 12, count 2 2006.285.18:18:55.51#ibcon#read 3, iclass 12, count 2 2006.285.18:18:55.51#ibcon#about to read 4, iclass 12, count 2 2006.285.18:18:55.51#ibcon#read 4, iclass 12, count 2 2006.285.18:18:55.51#ibcon#about to read 5, iclass 12, count 2 2006.285.18:18:55.51#ibcon#read 5, iclass 12, count 2 2006.285.18:18:55.51#ibcon#about to read 6, iclass 12, count 2 2006.285.18:18:55.51#ibcon#read 6, iclass 12, count 2 2006.285.18:18:55.51#ibcon#end of sib2, iclass 12, count 2 2006.285.18:18:55.51#ibcon#*after write, iclass 12, count 2 2006.285.18:18:55.51#ibcon#*before return 0, iclass 12, count 2 2006.285.18:18:55.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:18:55.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:18:55.51#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.18:18:55.51#ibcon#ireg 7 cls_cnt 0 2006.285.18:18:55.51#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:18:55.63#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:18:55.63#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:18:55.63#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:18:55.63#ibcon#first serial, iclass 12, count 0 2006.285.18:18:55.63#ibcon#enter sib2, iclass 12, count 0 2006.285.18:18:55.63#ibcon#flushed, iclass 12, count 0 2006.285.18:18:55.63#ibcon#about to write, iclass 12, count 0 2006.285.18:18:55.63#ibcon#wrote, iclass 12, count 0 2006.285.18:18:55.63#ibcon#about to read 3, iclass 12, count 0 2006.285.18:18:55.65#ibcon#read 3, iclass 12, count 0 2006.285.18:18:55.65#ibcon#about to read 4, iclass 12, count 0 2006.285.18:18:55.65#ibcon#read 4, iclass 12, count 0 2006.285.18:18:55.65#ibcon#about to read 5, iclass 12, count 0 2006.285.18:18:55.65#ibcon#read 5, iclass 12, count 0 2006.285.18:18:55.65#ibcon#about to read 6, iclass 12, count 0 2006.285.18:18:55.65#ibcon#read 6, iclass 12, count 0 2006.285.18:18:55.65#ibcon#end of sib2, iclass 12, count 0 2006.285.18:18:55.65#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:18:55.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:18:55.65#ibcon#[27=USB\r\n] 2006.285.18:18:55.65#ibcon#*before write, iclass 12, count 0 2006.285.18:18:55.65#ibcon#enter sib2, iclass 12, count 0 2006.285.18:18:55.65#ibcon#flushed, iclass 12, count 0 2006.285.18:18:55.65#ibcon#about to write, iclass 12, count 0 2006.285.18:18:55.65#ibcon#wrote, iclass 12, count 0 2006.285.18:18:55.65#ibcon#about to read 3, iclass 12, count 0 2006.285.18:18:55.68#ibcon#read 3, iclass 12, count 0 2006.285.18:18:55.68#ibcon#about to read 4, iclass 12, count 0 2006.285.18:18:55.68#ibcon#read 4, iclass 12, count 0 2006.285.18:18:55.68#ibcon#about to read 5, iclass 12, count 0 2006.285.18:18:55.68#ibcon#read 5, iclass 12, count 0 2006.285.18:18:55.68#ibcon#about to read 6, iclass 12, count 0 2006.285.18:18:55.68#ibcon#read 6, iclass 12, count 0 2006.285.18:18:55.68#ibcon#end of sib2, iclass 12, count 0 2006.285.18:18:55.68#ibcon#*after write, iclass 12, count 0 2006.285.18:18:55.68#ibcon#*before return 0, iclass 12, count 0 2006.285.18:18:55.68#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:18:55.68#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:18:55.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:18:55.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:18:55.68$vck44/vabw=wide 2006.285.18:18:55.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.18:18:55.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.18:18:55.68#ibcon#ireg 8 cls_cnt 0 2006.285.18:18:55.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:18:55.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:18:55.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:18:55.68#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:18:55.68#ibcon#first serial, iclass 14, count 0 2006.285.18:18:55.68#ibcon#enter sib2, iclass 14, count 0 2006.285.18:18:55.68#ibcon#flushed, iclass 14, count 0 2006.285.18:18:55.68#ibcon#about to write, iclass 14, count 0 2006.285.18:18:55.68#ibcon#wrote, iclass 14, count 0 2006.285.18:18:55.68#ibcon#about to read 3, iclass 14, count 0 2006.285.18:18:55.70#ibcon#read 3, iclass 14, count 0 2006.285.18:18:55.70#ibcon#about to read 4, iclass 14, count 0 2006.285.18:18:55.70#ibcon#read 4, iclass 14, count 0 2006.285.18:18:55.70#ibcon#about to read 5, iclass 14, count 0 2006.285.18:18:55.70#ibcon#read 5, iclass 14, count 0 2006.285.18:18:55.70#ibcon#about to read 6, iclass 14, count 0 2006.285.18:18:55.70#ibcon#read 6, iclass 14, count 0 2006.285.18:18:55.70#ibcon#end of sib2, iclass 14, count 0 2006.285.18:18:55.70#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:18:55.70#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:18:55.70#ibcon#[25=BW32\r\n] 2006.285.18:18:55.70#ibcon#*before write, iclass 14, count 0 2006.285.18:18:55.70#ibcon#enter sib2, iclass 14, count 0 2006.285.18:18:55.70#ibcon#flushed, iclass 14, count 0 2006.285.18:18:55.70#ibcon#about to write, iclass 14, count 0 2006.285.18:18:55.70#ibcon#wrote, iclass 14, count 0 2006.285.18:18:55.70#ibcon#about to read 3, iclass 14, count 0 2006.285.18:18:55.73#ibcon#read 3, iclass 14, count 0 2006.285.18:18:55.73#ibcon#about to read 4, iclass 14, count 0 2006.285.18:18:55.73#ibcon#read 4, iclass 14, count 0 2006.285.18:18:55.73#ibcon#about to read 5, iclass 14, count 0 2006.285.18:18:55.73#ibcon#read 5, iclass 14, count 0 2006.285.18:18:55.73#ibcon#about to read 6, iclass 14, count 0 2006.285.18:18:55.73#ibcon#read 6, iclass 14, count 0 2006.285.18:18:55.73#ibcon#end of sib2, iclass 14, count 0 2006.285.18:18:55.73#ibcon#*after write, iclass 14, count 0 2006.285.18:18:55.73#ibcon#*before return 0, iclass 14, count 0 2006.285.18:18:55.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:18:55.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:18:55.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:18:55.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:18:55.73$vck44/vbbw=wide 2006.285.18:18:55.73#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.18:18:55.73#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.18:18:55.73#ibcon#ireg 8 cls_cnt 0 2006.285.18:18:55.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:18:55.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:18:55.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:18:55.80#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:18:55.80#ibcon#first serial, iclass 16, count 0 2006.285.18:18:55.80#ibcon#enter sib2, iclass 16, count 0 2006.285.18:18:55.80#ibcon#flushed, iclass 16, count 0 2006.285.18:18:55.80#ibcon#about to write, iclass 16, count 0 2006.285.18:18:55.80#ibcon#wrote, iclass 16, count 0 2006.285.18:18:55.80#ibcon#about to read 3, iclass 16, count 0 2006.285.18:18:55.82#ibcon#read 3, iclass 16, count 0 2006.285.18:18:55.82#ibcon#about to read 4, iclass 16, count 0 2006.285.18:18:55.82#ibcon#read 4, iclass 16, count 0 2006.285.18:18:55.82#ibcon#about to read 5, iclass 16, count 0 2006.285.18:18:55.82#ibcon#read 5, iclass 16, count 0 2006.285.18:18:55.82#ibcon#about to read 6, iclass 16, count 0 2006.285.18:18:55.82#ibcon#read 6, iclass 16, count 0 2006.285.18:18:55.82#ibcon#end of sib2, iclass 16, count 0 2006.285.18:18:55.82#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:18:55.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:18:55.82#ibcon#[27=BW32\r\n] 2006.285.18:18:55.82#ibcon#*before write, iclass 16, count 0 2006.285.18:18:55.82#ibcon#enter sib2, iclass 16, count 0 2006.285.18:18:55.82#ibcon#flushed, iclass 16, count 0 2006.285.18:18:55.82#ibcon#about to write, iclass 16, count 0 2006.285.18:18:55.82#ibcon#wrote, iclass 16, count 0 2006.285.18:18:55.82#ibcon#about to read 3, iclass 16, count 0 2006.285.18:18:55.85#ibcon#read 3, iclass 16, count 0 2006.285.18:18:55.85#ibcon#about to read 4, iclass 16, count 0 2006.285.18:18:55.85#ibcon#read 4, iclass 16, count 0 2006.285.18:18:55.85#ibcon#about to read 5, iclass 16, count 0 2006.285.18:18:55.85#ibcon#read 5, iclass 16, count 0 2006.285.18:18:55.85#ibcon#about to read 6, iclass 16, count 0 2006.285.18:18:55.85#ibcon#read 6, iclass 16, count 0 2006.285.18:18:55.85#ibcon#end of sib2, iclass 16, count 0 2006.285.18:18:55.85#ibcon#*after write, iclass 16, count 0 2006.285.18:18:55.85#ibcon#*before return 0, iclass 16, count 0 2006.285.18:18:55.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:18:55.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:18:55.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:18:55.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:18:55.85$setupk4/ifdk4 2006.285.18:18:55.85$ifdk4/lo= 2006.285.18:18:55.85$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.18:18:55.85$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.18:18:55.85$ifdk4/patch= 2006.285.18:18:55.85$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.18:18:55.85$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.18:18:55.85$setupk4/!*+20s 2006.285.18:19:00.76#abcon#<5=/14 0.4 1.4 15.651001014.5\r\n> 2006.285.18:19:00.78#abcon#{5=INTERFACE CLEAR} 2006.285.18:19:00.84#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:19:09.27$setupk4/"tpicd 2006.285.18:19:09.27$setupk4/echo=off 2006.285.18:19:09.27$setupk4/xlog=off 2006.285.18:19:09.27:!2006.285.18:27:58 2006.285.18:19:15.13#trakl#Source acquired 2006.285.18:19:17.13#flagr#flagr/antenna,acquired 2006.285.18:27:58.00:preob 2006.285.18:27:58.13/onsource/TRACKING 2006.285.18:27:58.13:!2006.285.18:28:08 2006.285.18:28:08.00:"tape 2006.285.18:28:08.00:"st=record 2006.285.18:28:08.00:data_valid=on 2006.285.18:28:08.00:midob 2006.285.18:28:08.13/onsource/TRACKING 2006.285.18:28:08.13/wx/15.39,1014.7,100 2006.285.18:28:08.31/cable/+6.5045E-03 2006.285.18:28:09.40/va/01,07,usb,yes,31,34 2006.285.18:28:09.40/va/02,06,usb,yes,32,32 2006.285.18:28:09.40/va/03,07,usb,yes,31,33 2006.285.18:28:09.40/va/04,06,usb,yes,33,34 2006.285.18:28:09.40/va/05,03,usb,yes,32,32 2006.285.18:28:09.40/va/06,04,usb,yes,29,28 2006.285.18:28:09.40/va/07,04,usb,yes,29,30 2006.285.18:28:09.40/va/08,03,usb,yes,30,37 2006.285.18:28:09.63/valo/01,524.99,yes,locked 2006.285.18:28:09.63/valo/02,534.99,yes,locked 2006.285.18:28:09.63/valo/03,564.99,yes,locked 2006.285.18:28:09.63/valo/04,624.99,yes,locked 2006.285.18:28:09.63/valo/05,734.99,yes,locked 2006.285.18:28:09.63/valo/06,814.99,yes,locked 2006.285.18:28:09.63/valo/07,864.99,yes,locked 2006.285.18:28:09.63/valo/08,884.99,yes,locked 2006.285.18:28:10.72/vb/01,04,usb,yes,30,28 2006.285.18:28:10.72/vb/02,05,usb,yes,28,28 2006.285.18:28:10.72/vb/03,04,usb,yes,29,32 2006.285.18:28:10.72/vb/04,05,usb,yes,29,28 2006.285.18:28:10.72/vb/05,04,usb,yes,26,28 2006.285.18:28:10.72/vb/06,03,usb,yes,37,33 2006.285.18:28:10.72/vb/07,04,usb,yes,30,30 2006.285.18:28:10.72/vb/08,04,usb,yes,27,31 2006.285.18:28:10.95/vblo/01,629.99,yes,locked 2006.285.18:28:10.95/vblo/02,634.99,yes,locked 2006.285.18:28:10.95/vblo/03,649.99,yes,locked 2006.285.18:28:10.95/vblo/04,679.99,yes,locked 2006.285.18:28:10.95/vblo/05,709.99,yes,locked 2006.285.18:28:10.95/vblo/06,719.99,yes,locked 2006.285.18:28:10.95/vblo/07,734.99,yes,locked 2006.285.18:28:10.95/vblo/08,744.99,yes,locked 2006.285.18:28:11.10/vabw/8 2006.285.18:28:11.25/vbbw/8 2006.285.18:28:11.34/xfe/off,on,12.0 2006.285.18:28:11.72/ifatt/23,28,28,28 2006.285.18:28:12.07/fmout-gps/S +2.68E-07 2006.285.18:28:12.09:!2006.285.18:28:58 2006.285.18:28:58.00:data_valid=off 2006.285.18:28:58.00:"et 2006.285.18:28:58.00:!+3s 2006.285.18:29:01.01:"tape 2006.285.18:29:01.01:postob 2006.285.18:29:01.19/cable/+6.5040E-03 2006.285.18:29:01.19/wx/15.37,1014.7,100 2006.285.18:29:02.07/fmout-gps/S +2.67E-07 2006.285.18:29:02.07:scan_name=285-1831,jd0610,60 2006.285.18:29:02.07:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.285.18:29:03.14#flagr#flagr/antenna,new-source 2006.285.18:29:03.14:checkk5 2006.285.18:29:03.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.18:29:03.95/chk_autoobs//k5ts2/ autoobs is running! 2006.285.18:29:04.47/chk_autoobs//k5ts3/ autoobs is running! 2006.285.18:29:04.84/chk_autoobs//k5ts4/ autoobs is running! 2006.285.18:29:05.32/chk_obsdata//k5ts1/T2851828??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.18:29:05.72/chk_obsdata//k5ts2/T2851828??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.18:29:06.20/chk_obsdata//k5ts3/T2851828??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.18:29:06.84/chk_obsdata//k5ts4/T2851828??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.18:29:07.90/k5log//k5ts1_log_newline 2006.285.18:29:08.77/k5log//k5ts2_log_newline 2006.285.18:29:09.52/k5log//k5ts3_log_newline 2006.285.18:29:10.50/k5log//k5ts4_log_newline 2006.285.18:29:10.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.18:29:10.52:setupk4=1 2006.285.18:29:10.52$setupk4/echo=on 2006.285.18:29:10.52$setupk4/pcalon 2006.285.18:29:10.52$pcalon/"no phase cal control is implemented here 2006.285.18:29:10.52$setupk4/"tpicd=stop 2006.285.18:29:10.52$setupk4/"rec=synch_on 2006.285.18:29:10.52$setupk4/"rec_mode=128 2006.285.18:29:10.52$setupk4/!* 2006.285.18:29:10.52$setupk4/recpk4 2006.285.18:29:10.52$recpk4/recpatch= 2006.285.18:29:10.52$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.18:29:10.52$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.18:29:10.52$setupk4/vck44 2006.285.18:29:10.52$vck44/valo=1,524.99 2006.285.18:29:10.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.18:29:10.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.18:29:10.52#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:10.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:29:10.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:29:10.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:29:10.52#ibcon#enter wrdev, iclass 40, count 0 2006.285.18:29:10.52#ibcon#first serial, iclass 40, count 0 2006.285.18:29:10.52#ibcon#enter sib2, iclass 40, count 0 2006.285.18:29:10.52#ibcon#flushed, iclass 40, count 0 2006.285.18:29:10.52#ibcon#about to write, iclass 40, count 0 2006.285.18:29:10.52#ibcon#wrote, iclass 40, count 0 2006.285.18:29:10.52#ibcon#about to read 3, iclass 40, count 0 2006.285.18:29:10.54#ibcon#read 3, iclass 40, count 0 2006.285.18:29:10.54#ibcon#about to read 4, iclass 40, count 0 2006.285.18:29:10.54#ibcon#read 4, iclass 40, count 0 2006.285.18:29:10.54#ibcon#about to read 5, iclass 40, count 0 2006.285.18:29:10.54#ibcon#read 5, iclass 40, count 0 2006.285.18:29:10.54#ibcon#about to read 6, iclass 40, count 0 2006.285.18:29:10.54#ibcon#read 6, iclass 40, count 0 2006.285.18:29:10.54#ibcon#end of sib2, iclass 40, count 0 2006.285.18:29:10.54#ibcon#*mode == 0, iclass 40, count 0 2006.285.18:29:10.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.18:29:10.54#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.18:29:10.54#ibcon#*before write, iclass 40, count 0 2006.285.18:29:10.54#ibcon#enter sib2, iclass 40, count 0 2006.285.18:29:10.54#ibcon#flushed, iclass 40, count 0 2006.285.18:29:10.54#ibcon#about to write, iclass 40, count 0 2006.285.18:29:10.54#ibcon#wrote, iclass 40, count 0 2006.285.18:29:10.54#ibcon#about to read 3, iclass 40, count 0 2006.285.18:29:10.59#ibcon#read 3, iclass 40, count 0 2006.285.18:29:10.59#ibcon#about to read 4, iclass 40, count 0 2006.285.18:29:10.59#ibcon#read 4, iclass 40, count 0 2006.285.18:29:10.59#ibcon#about to read 5, iclass 40, count 0 2006.285.18:29:10.59#ibcon#read 5, iclass 40, count 0 2006.285.18:29:10.59#ibcon#about to read 6, iclass 40, count 0 2006.285.18:29:10.59#ibcon#read 6, iclass 40, count 0 2006.285.18:29:10.59#ibcon#end of sib2, iclass 40, count 0 2006.285.18:29:10.59#ibcon#*after write, iclass 40, count 0 2006.285.18:29:10.59#ibcon#*before return 0, iclass 40, count 0 2006.285.18:29:10.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:29:10.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:29:10.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.18:29:10.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.18:29:10.59$vck44/va=1,7 2006.285.18:29:10.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.18:29:10.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.18:29:10.59#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:10.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:29:10.59#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:29:10.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:29:10.59#ibcon#enter wrdev, iclass 4, count 2 2006.285.18:29:10.59#ibcon#first serial, iclass 4, count 2 2006.285.18:29:10.59#ibcon#enter sib2, iclass 4, count 2 2006.285.18:29:10.59#ibcon#flushed, iclass 4, count 2 2006.285.18:29:10.59#ibcon#about to write, iclass 4, count 2 2006.285.18:29:10.59#ibcon#wrote, iclass 4, count 2 2006.285.18:29:10.59#ibcon#about to read 3, iclass 4, count 2 2006.285.18:29:10.61#ibcon#read 3, iclass 4, count 2 2006.285.18:29:10.61#ibcon#about to read 4, iclass 4, count 2 2006.285.18:29:10.61#ibcon#read 4, iclass 4, count 2 2006.285.18:29:10.61#ibcon#about to read 5, iclass 4, count 2 2006.285.18:29:10.61#ibcon#read 5, iclass 4, count 2 2006.285.18:29:10.61#ibcon#about to read 6, iclass 4, count 2 2006.285.18:29:10.61#ibcon#read 6, iclass 4, count 2 2006.285.18:29:10.61#ibcon#end of sib2, iclass 4, count 2 2006.285.18:29:10.61#ibcon#*mode == 0, iclass 4, count 2 2006.285.18:29:10.61#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.18:29:10.61#ibcon#[25=AT01-07\r\n] 2006.285.18:29:10.61#ibcon#*before write, iclass 4, count 2 2006.285.18:29:10.61#ibcon#enter sib2, iclass 4, count 2 2006.285.18:29:10.61#ibcon#flushed, iclass 4, count 2 2006.285.18:29:10.61#ibcon#about to write, iclass 4, count 2 2006.285.18:29:10.61#ibcon#wrote, iclass 4, count 2 2006.285.18:29:10.61#ibcon#about to read 3, iclass 4, count 2 2006.285.18:29:10.64#ibcon#read 3, iclass 4, count 2 2006.285.18:29:10.64#ibcon#about to read 4, iclass 4, count 2 2006.285.18:29:10.64#ibcon#read 4, iclass 4, count 2 2006.285.18:29:10.64#ibcon#about to read 5, iclass 4, count 2 2006.285.18:29:10.64#ibcon#read 5, iclass 4, count 2 2006.285.18:29:10.64#ibcon#about to read 6, iclass 4, count 2 2006.285.18:29:10.64#ibcon#read 6, iclass 4, count 2 2006.285.18:29:10.64#ibcon#end of sib2, iclass 4, count 2 2006.285.18:29:10.64#ibcon#*after write, iclass 4, count 2 2006.285.18:29:10.64#ibcon#*before return 0, iclass 4, count 2 2006.285.18:29:10.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:29:10.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:29:10.64#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.18:29:10.64#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:10.64#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:29:10.76#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:29:10.76#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:29:10.76#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:29:10.76#ibcon#first serial, iclass 4, count 0 2006.285.18:29:10.76#ibcon#enter sib2, iclass 4, count 0 2006.285.18:29:10.76#ibcon#flushed, iclass 4, count 0 2006.285.18:29:10.76#ibcon#about to write, iclass 4, count 0 2006.285.18:29:10.76#ibcon#wrote, iclass 4, count 0 2006.285.18:29:10.76#ibcon#about to read 3, iclass 4, count 0 2006.285.18:29:10.78#ibcon#read 3, iclass 4, count 0 2006.285.18:29:10.78#ibcon#about to read 4, iclass 4, count 0 2006.285.18:29:10.78#ibcon#read 4, iclass 4, count 0 2006.285.18:29:10.78#ibcon#about to read 5, iclass 4, count 0 2006.285.18:29:10.78#ibcon#read 5, iclass 4, count 0 2006.285.18:29:10.78#ibcon#about to read 6, iclass 4, count 0 2006.285.18:29:10.78#ibcon#read 6, iclass 4, count 0 2006.285.18:29:10.78#ibcon#end of sib2, iclass 4, count 0 2006.285.18:29:10.78#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:29:10.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:29:10.78#ibcon#[25=USB\r\n] 2006.285.18:29:10.78#ibcon#*before write, iclass 4, count 0 2006.285.18:29:10.78#ibcon#enter sib2, iclass 4, count 0 2006.285.18:29:10.78#ibcon#flushed, iclass 4, count 0 2006.285.18:29:10.78#ibcon#about to write, iclass 4, count 0 2006.285.18:29:10.78#ibcon#wrote, iclass 4, count 0 2006.285.18:29:10.78#ibcon#about to read 3, iclass 4, count 0 2006.285.18:29:10.81#ibcon#read 3, iclass 4, count 0 2006.285.18:29:10.81#ibcon#about to read 4, iclass 4, count 0 2006.285.18:29:10.81#ibcon#read 4, iclass 4, count 0 2006.285.18:29:10.81#ibcon#about to read 5, iclass 4, count 0 2006.285.18:29:10.81#ibcon#read 5, iclass 4, count 0 2006.285.18:29:10.81#ibcon#about to read 6, iclass 4, count 0 2006.285.18:29:10.81#ibcon#read 6, iclass 4, count 0 2006.285.18:29:10.81#ibcon#end of sib2, iclass 4, count 0 2006.285.18:29:10.81#ibcon#*after write, iclass 4, count 0 2006.285.18:29:10.81#ibcon#*before return 0, iclass 4, count 0 2006.285.18:29:10.81#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:29:10.81#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:29:10.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:29:10.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:29:10.81$vck44/valo=2,534.99 2006.285.18:29:10.81#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.18:29:10.81#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.18:29:10.81#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:10.81#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:29:10.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:29:10.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:29:10.81#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:29:10.81#ibcon#first serial, iclass 6, count 0 2006.285.18:29:10.81#ibcon#enter sib2, iclass 6, count 0 2006.285.18:29:10.81#ibcon#flushed, iclass 6, count 0 2006.285.18:29:10.81#ibcon#about to write, iclass 6, count 0 2006.285.18:29:10.81#ibcon#wrote, iclass 6, count 0 2006.285.18:29:10.81#ibcon#about to read 3, iclass 6, count 0 2006.285.18:29:10.83#ibcon#read 3, iclass 6, count 0 2006.285.18:29:10.83#ibcon#about to read 4, iclass 6, count 0 2006.285.18:29:10.83#ibcon#read 4, iclass 6, count 0 2006.285.18:29:10.83#ibcon#about to read 5, iclass 6, count 0 2006.285.18:29:10.83#ibcon#read 5, iclass 6, count 0 2006.285.18:29:10.83#ibcon#about to read 6, iclass 6, count 0 2006.285.18:29:10.83#ibcon#read 6, iclass 6, count 0 2006.285.18:29:10.83#ibcon#end of sib2, iclass 6, count 0 2006.285.18:29:10.83#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:29:10.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:29:10.83#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.18:29:10.83#ibcon#*before write, iclass 6, count 0 2006.285.18:29:10.83#ibcon#enter sib2, iclass 6, count 0 2006.285.18:29:10.83#ibcon#flushed, iclass 6, count 0 2006.285.18:29:10.83#ibcon#about to write, iclass 6, count 0 2006.285.18:29:10.83#ibcon#wrote, iclass 6, count 0 2006.285.18:29:10.83#ibcon#about to read 3, iclass 6, count 0 2006.285.18:29:10.87#ibcon#read 3, iclass 6, count 0 2006.285.18:29:10.87#ibcon#about to read 4, iclass 6, count 0 2006.285.18:29:10.87#ibcon#read 4, iclass 6, count 0 2006.285.18:29:10.87#ibcon#about to read 5, iclass 6, count 0 2006.285.18:29:10.87#ibcon#read 5, iclass 6, count 0 2006.285.18:29:10.87#ibcon#about to read 6, iclass 6, count 0 2006.285.18:29:10.87#ibcon#read 6, iclass 6, count 0 2006.285.18:29:10.87#ibcon#end of sib2, iclass 6, count 0 2006.285.18:29:10.87#ibcon#*after write, iclass 6, count 0 2006.285.18:29:10.87#ibcon#*before return 0, iclass 6, count 0 2006.285.18:29:10.87#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:29:10.87#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:29:10.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:29:10.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:29:10.87$vck44/va=2,6 2006.285.18:29:10.87#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.18:29:10.87#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.18:29:10.87#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:10.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:29:10.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:29:10.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:29:10.93#ibcon#enter wrdev, iclass 10, count 2 2006.285.18:29:10.93#ibcon#first serial, iclass 10, count 2 2006.285.18:29:10.93#ibcon#enter sib2, iclass 10, count 2 2006.285.18:29:10.93#ibcon#flushed, iclass 10, count 2 2006.285.18:29:10.93#ibcon#about to write, iclass 10, count 2 2006.285.18:29:10.93#ibcon#wrote, iclass 10, count 2 2006.285.18:29:10.93#ibcon#about to read 3, iclass 10, count 2 2006.285.18:29:10.95#ibcon#read 3, iclass 10, count 2 2006.285.18:29:10.95#ibcon#about to read 4, iclass 10, count 2 2006.285.18:29:10.95#ibcon#read 4, iclass 10, count 2 2006.285.18:29:10.95#ibcon#about to read 5, iclass 10, count 2 2006.285.18:29:10.95#ibcon#read 5, iclass 10, count 2 2006.285.18:29:10.95#ibcon#about to read 6, iclass 10, count 2 2006.285.18:29:10.95#ibcon#read 6, iclass 10, count 2 2006.285.18:29:10.95#ibcon#end of sib2, iclass 10, count 2 2006.285.18:29:10.95#ibcon#*mode == 0, iclass 10, count 2 2006.285.18:29:10.95#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.18:29:10.95#ibcon#[25=AT02-06\r\n] 2006.285.18:29:10.95#ibcon#*before write, iclass 10, count 2 2006.285.18:29:10.95#ibcon#enter sib2, iclass 10, count 2 2006.285.18:29:10.95#ibcon#flushed, iclass 10, count 2 2006.285.18:29:10.95#ibcon#about to write, iclass 10, count 2 2006.285.18:29:10.95#ibcon#wrote, iclass 10, count 2 2006.285.18:29:10.95#ibcon#about to read 3, iclass 10, count 2 2006.285.18:29:10.98#ibcon#read 3, iclass 10, count 2 2006.285.18:29:10.98#ibcon#about to read 4, iclass 10, count 2 2006.285.18:29:10.98#ibcon#read 4, iclass 10, count 2 2006.285.18:29:10.98#ibcon#about to read 5, iclass 10, count 2 2006.285.18:29:10.98#ibcon#read 5, iclass 10, count 2 2006.285.18:29:10.98#ibcon#about to read 6, iclass 10, count 2 2006.285.18:29:10.98#ibcon#read 6, iclass 10, count 2 2006.285.18:29:10.98#ibcon#end of sib2, iclass 10, count 2 2006.285.18:29:10.98#ibcon#*after write, iclass 10, count 2 2006.285.18:29:10.98#ibcon#*before return 0, iclass 10, count 2 2006.285.18:29:10.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:29:10.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:29:10.98#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.18:29:10.98#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:10.98#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:29:11.10#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:29:11.10#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:29:11.10#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:29:11.10#ibcon#first serial, iclass 10, count 0 2006.285.18:29:11.10#ibcon#enter sib2, iclass 10, count 0 2006.285.18:29:11.10#ibcon#flushed, iclass 10, count 0 2006.285.18:29:11.10#ibcon#about to write, iclass 10, count 0 2006.285.18:29:11.10#ibcon#wrote, iclass 10, count 0 2006.285.18:29:11.10#ibcon#about to read 3, iclass 10, count 0 2006.285.18:29:11.12#ibcon#read 3, iclass 10, count 0 2006.285.18:29:11.12#ibcon#about to read 4, iclass 10, count 0 2006.285.18:29:11.12#ibcon#read 4, iclass 10, count 0 2006.285.18:29:11.12#ibcon#about to read 5, iclass 10, count 0 2006.285.18:29:11.12#ibcon#read 5, iclass 10, count 0 2006.285.18:29:11.12#ibcon#about to read 6, iclass 10, count 0 2006.285.18:29:11.12#ibcon#read 6, iclass 10, count 0 2006.285.18:29:11.12#ibcon#end of sib2, iclass 10, count 0 2006.285.18:29:11.12#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:29:11.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:29:11.12#ibcon#[25=USB\r\n] 2006.285.18:29:11.12#ibcon#*before write, iclass 10, count 0 2006.285.18:29:11.12#ibcon#enter sib2, iclass 10, count 0 2006.285.18:29:11.12#ibcon#flushed, iclass 10, count 0 2006.285.18:29:11.12#ibcon#about to write, iclass 10, count 0 2006.285.18:29:11.12#ibcon#wrote, iclass 10, count 0 2006.285.18:29:11.12#ibcon#about to read 3, iclass 10, count 0 2006.285.18:29:11.15#ibcon#read 3, iclass 10, count 0 2006.285.18:29:11.15#ibcon#about to read 4, iclass 10, count 0 2006.285.18:29:11.15#ibcon#read 4, iclass 10, count 0 2006.285.18:29:11.15#ibcon#about to read 5, iclass 10, count 0 2006.285.18:29:11.15#ibcon#read 5, iclass 10, count 0 2006.285.18:29:11.15#ibcon#about to read 6, iclass 10, count 0 2006.285.18:29:11.15#ibcon#read 6, iclass 10, count 0 2006.285.18:29:11.15#ibcon#end of sib2, iclass 10, count 0 2006.285.18:29:11.15#ibcon#*after write, iclass 10, count 0 2006.285.18:29:11.15#ibcon#*before return 0, iclass 10, count 0 2006.285.18:29:11.15#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:29:11.15#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:29:11.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:29:11.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:29:11.15$vck44/valo=3,564.99 2006.285.18:29:11.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.18:29:11.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.18:29:11.64#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:11.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:29:11.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:29:11.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:29:11.64#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:29:11.64#ibcon#first serial, iclass 12, count 0 2006.285.18:29:11.64#ibcon#enter sib2, iclass 12, count 0 2006.285.18:29:11.64#ibcon#flushed, iclass 12, count 0 2006.285.18:29:11.64#ibcon#about to write, iclass 12, count 0 2006.285.18:29:11.64#ibcon#wrote, iclass 12, count 0 2006.285.18:29:11.64#ibcon#about to read 3, iclass 12, count 0 2006.285.18:29:11.66#ibcon#read 3, iclass 12, count 0 2006.285.18:29:11.66#ibcon#about to read 4, iclass 12, count 0 2006.285.18:29:11.66#ibcon#read 4, iclass 12, count 0 2006.285.18:29:11.66#ibcon#about to read 5, iclass 12, count 0 2006.285.18:29:11.66#ibcon#read 5, iclass 12, count 0 2006.285.18:29:11.66#ibcon#about to read 6, iclass 12, count 0 2006.285.18:29:11.66#ibcon#read 6, iclass 12, count 0 2006.285.18:29:11.66#ibcon#end of sib2, iclass 12, count 0 2006.285.18:29:11.66#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:29:11.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:29:11.66#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.18:29:11.66#ibcon#*before write, iclass 12, count 0 2006.285.18:29:11.66#ibcon#enter sib2, iclass 12, count 0 2006.285.18:29:11.66#ibcon#flushed, iclass 12, count 0 2006.285.18:29:11.66#ibcon#about to write, iclass 12, count 0 2006.285.18:29:11.66#ibcon#wrote, iclass 12, count 0 2006.285.18:29:11.66#ibcon#about to read 3, iclass 12, count 0 2006.285.18:29:11.70#ibcon#read 3, iclass 12, count 0 2006.285.18:29:11.70#ibcon#about to read 4, iclass 12, count 0 2006.285.18:29:11.70#ibcon#read 4, iclass 12, count 0 2006.285.18:29:11.70#ibcon#about to read 5, iclass 12, count 0 2006.285.18:29:11.70#ibcon#read 5, iclass 12, count 0 2006.285.18:29:11.70#ibcon#about to read 6, iclass 12, count 0 2006.285.18:29:11.70#ibcon#read 6, iclass 12, count 0 2006.285.18:29:11.70#ibcon#end of sib2, iclass 12, count 0 2006.285.18:29:11.70#ibcon#*after write, iclass 12, count 0 2006.285.18:29:11.70#ibcon#*before return 0, iclass 12, count 0 2006.285.18:29:11.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:29:11.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:29:11.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:29:11.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:29:11.70$vck44/va=3,7 2006.285.18:29:11.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.18:29:11.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.18:29:11.70#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:11.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:29:11.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:29:11.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:29:11.70#ibcon#enter wrdev, iclass 14, count 2 2006.285.18:29:11.70#ibcon#first serial, iclass 14, count 2 2006.285.18:29:11.70#ibcon#enter sib2, iclass 14, count 2 2006.285.18:29:11.70#ibcon#flushed, iclass 14, count 2 2006.285.18:29:11.70#ibcon#about to write, iclass 14, count 2 2006.285.18:29:11.70#ibcon#wrote, iclass 14, count 2 2006.285.18:29:11.70#ibcon#about to read 3, iclass 14, count 2 2006.285.18:29:11.72#ibcon#read 3, iclass 14, count 2 2006.285.18:29:11.72#ibcon#about to read 4, iclass 14, count 2 2006.285.18:29:11.72#ibcon#read 4, iclass 14, count 2 2006.285.18:29:11.72#ibcon#about to read 5, iclass 14, count 2 2006.285.18:29:11.72#ibcon#read 5, iclass 14, count 2 2006.285.18:29:11.72#ibcon#about to read 6, iclass 14, count 2 2006.285.18:29:11.72#ibcon#read 6, iclass 14, count 2 2006.285.18:29:11.72#ibcon#end of sib2, iclass 14, count 2 2006.285.18:29:11.72#ibcon#*mode == 0, iclass 14, count 2 2006.285.18:29:11.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.18:29:11.72#ibcon#[25=AT03-07\r\n] 2006.285.18:29:11.72#ibcon#*before write, iclass 14, count 2 2006.285.18:29:11.72#ibcon#enter sib2, iclass 14, count 2 2006.285.18:29:11.72#ibcon#flushed, iclass 14, count 2 2006.285.18:29:11.72#ibcon#about to write, iclass 14, count 2 2006.285.18:29:11.72#ibcon#wrote, iclass 14, count 2 2006.285.18:29:11.72#ibcon#about to read 3, iclass 14, count 2 2006.285.18:29:11.75#ibcon#read 3, iclass 14, count 2 2006.285.18:29:11.75#ibcon#about to read 4, iclass 14, count 2 2006.285.18:29:11.75#ibcon#read 4, iclass 14, count 2 2006.285.18:29:11.75#ibcon#about to read 5, iclass 14, count 2 2006.285.18:29:11.75#ibcon#read 5, iclass 14, count 2 2006.285.18:29:11.75#ibcon#about to read 6, iclass 14, count 2 2006.285.18:29:11.75#ibcon#read 6, iclass 14, count 2 2006.285.18:29:11.75#ibcon#end of sib2, iclass 14, count 2 2006.285.18:29:11.75#ibcon#*after write, iclass 14, count 2 2006.285.18:29:11.75#ibcon#*before return 0, iclass 14, count 2 2006.285.18:29:11.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:29:11.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:29:11.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.18:29:11.75#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:11.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:29:11.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:29:11.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:29:11.87#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:29:11.87#ibcon#first serial, iclass 14, count 0 2006.285.18:29:11.87#ibcon#enter sib2, iclass 14, count 0 2006.285.18:29:11.87#ibcon#flushed, iclass 14, count 0 2006.285.18:29:11.87#ibcon#about to write, iclass 14, count 0 2006.285.18:29:11.87#ibcon#wrote, iclass 14, count 0 2006.285.18:29:11.87#ibcon#about to read 3, iclass 14, count 0 2006.285.18:29:11.89#ibcon#read 3, iclass 14, count 0 2006.285.18:29:11.89#ibcon#about to read 4, iclass 14, count 0 2006.285.18:29:11.89#ibcon#read 4, iclass 14, count 0 2006.285.18:29:11.89#ibcon#about to read 5, iclass 14, count 0 2006.285.18:29:11.89#ibcon#read 5, iclass 14, count 0 2006.285.18:29:11.89#ibcon#about to read 6, iclass 14, count 0 2006.285.18:29:11.89#ibcon#read 6, iclass 14, count 0 2006.285.18:29:11.89#ibcon#end of sib2, iclass 14, count 0 2006.285.18:29:11.89#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:29:11.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:29:11.89#ibcon#[25=USB\r\n] 2006.285.18:29:11.89#ibcon#*before write, iclass 14, count 0 2006.285.18:29:11.89#ibcon#enter sib2, iclass 14, count 0 2006.285.18:29:11.89#ibcon#flushed, iclass 14, count 0 2006.285.18:29:11.89#ibcon#about to write, iclass 14, count 0 2006.285.18:29:11.89#ibcon#wrote, iclass 14, count 0 2006.285.18:29:11.89#ibcon#about to read 3, iclass 14, count 0 2006.285.18:29:11.92#ibcon#read 3, iclass 14, count 0 2006.285.18:29:11.92#ibcon#about to read 4, iclass 14, count 0 2006.285.18:29:11.92#ibcon#read 4, iclass 14, count 0 2006.285.18:29:11.92#ibcon#about to read 5, iclass 14, count 0 2006.285.18:29:11.92#ibcon#read 5, iclass 14, count 0 2006.285.18:29:11.92#ibcon#about to read 6, iclass 14, count 0 2006.285.18:29:11.92#ibcon#read 6, iclass 14, count 0 2006.285.18:29:11.92#ibcon#end of sib2, iclass 14, count 0 2006.285.18:29:11.92#ibcon#*after write, iclass 14, count 0 2006.285.18:29:11.92#ibcon#*before return 0, iclass 14, count 0 2006.285.18:29:11.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:29:11.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:29:11.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:29:11.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:29:11.92$vck44/valo=4,624.99 2006.285.18:29:11.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.18:29:11.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.18:29:11.92#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:11.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:29:11.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:29:11.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:29:11.92#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:29:11.92#ibcon#first serial, iclass 16, count 0 2006.285.18:29:11.92#ibcon#enter sib2, iclass 16, count 0 2006.285.18:29:11.92#ibcon#flushed, iclass 16, count 0 2006.285.18:29:11.92#ibcon#about to write, iclass 16, count 0 2006.285.18:29:11.92#ibcon#wrote, iclass 16, count 0 2006.285.18:29:11.92#ibcon#about to read 3, iclass 16, count 0 2006.285.18:29:11.94#ibcon#read 3, iclass 16, count 0 2006.285.18:29:12.25#ibcon#about to read 4, iclass 16, count 0 2006.285.18:29:12.25#ibcon#read 4, iclass 16, count 0 2006.285.18:29:12.25#ibcon#about to read 5, iclass 16, count 0 2006.285.18:29:12.25#ibcon#read 5, iclass 16, count 0 2006.285.18:29:12.25#ibcon#about to read 6, iclass 16, count 0 2006.285.18:29:12.25#ibcon#read 6, iclass 16, count 0 2006.285.18:29:12.25#ibcon#end of sib2, iclass 16, count 0 2006.285.18:29:12.25#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:29:12.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:29:12.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.18:29:12.25#ibcon#*before write, iclass 16, count 0 2006.285.18:29:12.25#ibcon#enter sib2, iclass 16, count 0 2006.285.18:29:12.25#ibcon#flushed, iclass 16, count 0 2006.285.18:29:12.25#ibcon#about to write, iclass 16, count 0 2006.285.18:29:12.25#ibcon#wrote, iclass 16, count 0 2006.285.18:29:12.25#ibcon#about to read 3, iclass 16, count 0 2006.285.18:29:12.29#ibcon#read 3, iclass 16, count 0 2006.285.18:29:12.29#ibcon#about to read 4, iclass 16, count 0 2006.285.18:29:12.29#ibcon#read 4, iclass 16, count 0 2006.285.18:29:12.29#ibcon#about to read 5, iclass 16, count 0 2006.285.18:29:12.29#ibcon#read 5, iclass 16, count 0 2006.285.18:29:12.29#ibcon#about to read 6, iclass 16, count 0 2006.285.18:29:12.29#ibcon#read 6, iclass 16, count 0 2006.285.18:29:12.29#ibcon#end of sib2, iclass 16, count 0 2006.285.18:29:12.29#ibcon#*after write, iclass 16, count 0 2006.285.18:29:12.29#ibcon#*before return 0, iclass 16, count 0 2006.285.18:29:12.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:29:12.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:29:12.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:29:12.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:29:12.29$vck44/va=4,6 2006.285.18:29:12.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.18:29:12.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.18:29:12.29#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:12.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:29:12.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:29:12.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:29:12.29#ibcon#enter wrdev, iclass 18, count 2 2006.285.18:29:12.29#ibcon#first serial, iclass 18, count 2 2006.285.18:29:12.29#ibcon#enter sib2, iclass 18, count 2 2006.285.18:29:12.29#ibcon#flushed, iclass 18, count 2 2006.285.18:29:12.29#ibcon#about to write, iclass 18, count 2 2006.285.18:29:12.29#ibcon#wrote, iclass 18, count 2 2006.285.18:29:12.29#ibcon#about to read 3, iclass 18, count 2 2006.285.18:29:12.31#ibcon#read 3, iclass 18, count 2 2006.285.18:29:12.31#ibcon#about to read 4, iclass 18, count 2 2006.285.18:29:12.31#ibcon#read 4, iclass 18, count 2 2006.285.18:29:12.31#ibcon#about to read 5, iclass 18, count 2 2006.285.18:29:12.31#ibcon#read 5, iclass 18, count 2 2006.285.18:29:12.31#ibcon#about to read 6, iclass 18, count 2 2006.285.18:29:12.31#ibcon#read 6, iclass 18, count 2 2006.285.18:29:12.31#ibcon#end of sib2, iclass 18, count 2 2006.285.18:29:12.31#ibcon#*mode == 0, iclass 18, count 2 2006.285.18:29:12.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.18:29:12.31#ibcon#[25=AT04-06\r\n] 2006.285.18:29:12.31#ibcon#*before write, iclass 18, count 2 2006.285.18:29:12.31#ibcon#enter sib2, iclass 18, count 2 2006.285.18:29:12.31#ibcon#flushed, iclass 18, count 2 2006.285.18:29:12.31#ibcon#about to write, iclass 18, count 2 2006.285.18:29:12.31#ibcon#wrote, iclass 18, count 2 2006.285.18:29:12.31#ibcon#about to read 3, iclass 18, count 2 2006.285.18:29:12.34#ibcon#read 3, iclass 18, count 2 2006.285.18:29:12.34#ibcon#about to read 4, iclass 18, count 2 2006.285.18:29:12.34#ibcon#read 4, iclass 18, count 2 2006.285.18:29:12.34#ibcon#about to read 5, iclass 18, count 2 2006.285.18:29:12.34#ibcon#read 5, iclass 18, count 2 2006.285.18:29:12.34#ibcon#about to read 6, iclass 18, count 2 2006.285.18:29:12.34#ibcon#read 6, iclass 18, count 2 2006.285.18:29:12.34#ibcon#end of sib2, iclass 18, count 2 2006.285.18:29:12.34#ibcon#*after write, iclass 18, count 2 2006.285.18:29:12.34#ibcon#*before return 0, iclass 18, count 2 2006.285.18:29:12.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:29:12.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:29:12.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.18:29:12.34#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:12.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:29:12.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:29:12.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:29:12.46#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:29:12.46#ibcon#first serial, iclass 18, count 0 2006.285.18:29:12.46#ibcon#enter sib2, iclass 18, count 0 2006.285.18:29:12.46#ibcon#flushed, iclass 18, count 0 2006.285.18:29:12.46#ibcon#about to write, iclass 18, count 0 2006.285.18:29:12.46#ibcon#wrote, iclass 18, count 0 2006.285.18:29:12.46#ibcon#about to read 3, iclass 18, count 0 2006.285.18:29:12.48#ibcon#read 3, iclass 18, count 0 2006.285.18:29:12.48#ibcon#about to read 4, iclass 18, count 0 2006.285.18:29:12.48#ibcon#read 4, iclass 18, count 0 2006.285.18:29:12.48#ibcon#about to read 5, iclass 18, count 0 2006.285.18:29:12.48#ibcon#read 5, iclass 18, count 0 2006.285.18:29:12.48#ibcon#about to read 6, iclass 18, count 0 2006.285.18:29:12.48#ibcon#read 6, iclass 18, count 0 2006.285.18:29:12.48#ibcon#end of sib2, iclass 18, count 0 2006.285.18:29:12.48#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:29:12.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:29:12.48#ibcon#[25=USB\r\n] 2006.285.18:29:12.48#ibcon#*before write, iclass 18, count 0 2006.285.18:29:12.48#ibcon#enter sib2, iclass 18, count 0 2006.285.18:29:12.48#ibcon#flushed, iclass 18, count 0 2006.285.18:29:12.48#ibcon#about to write, iclass 18, count 0 2006.285.18:29:12.48#ibcon#wrote, iclass 18, count 0 2006.285.18:29:12.48#ibcon#about to read 3, iclass 18, count 0 2006.285.18:29:12.51#ibcon#read 3, iclass 18, count 0 2006.285.18:29:12.51#ibcon#about to read 4, iclass 18, count 0 2006.285.18:29:12.51#ibcon#read 4, iclass 18, count 0 2006.285.18:29:12.51#ibcon#about to read 5, iclass 18, count 0 2006.285.18:29:12.51#ibcon#read 5, iclass 18, count 0 2006.285.18:29:12.51#ibcon#about to read 6, iclass 18, count 0 2006.285.18:29:12.51#ibcon#read 6, iclass 18, count 0 2006.285.18:29:12.51#ibcon#end of sib2, iclass 18, count 0 2006.285.18:29:12.51#ibcon#*after write, iclass 18, count 0 2006.285.18:29:12.51#ibcon#*before return 0, iclass 18, count 0 2006.285.18:29:12.51#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:29:12.51#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:29:12.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:29:12.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:29:12.51$vck44/valo=5,734.99 2006.285.18:29:12.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.18:29:12.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.18:29:12.51#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:12.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:29:12.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:29:12.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:29:12.51#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:29:12.51#ibcon#first serial, iclass 20, count 0 2006.285.18:29:12.51#ibcon#enter sib2, iclass 20, count 0 2006.285.18:29:12.51#ibcon#flushed, iclass 20, count 0 2006.285.18:29:12.51#ibcon#about to write, iclass 20, count 0 2006.285.18:29:12.51#ibcon#wrote, iclass 20, count 0 2006.285.18:29:12.51#ibcon#about to read 3, iclass 20, count 0 2006.285.18:29:12.53#ibcon#read 3, iclass 20, count 0 2006.285.18:29:12.53#ibcon#about to read 4, iclass 20, count 0 2006.285.18:29:12.53#ibcon#read 4, iclass 20, count 0 2006.285.18:29:12.53#ibcon#about to read 5, iclass 20, count 0 2006.285.18:29:12.53#ibcon#read 5, iclass 20, count 0 2006.285.18:29:12.53#ibcon#about to read 6, iclass 20, count 0 2006.285.18:29:12.53#ibcon#read 6, iclass 20, count 0 2006.285.18:29:12.53#ibcon#end of sib2, iclass 20, count 0 2006.285.18:29:12.53#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:29:12.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:29:12.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.18:29:12.53#ibcon#*before write, iclass 20, count 0 2006.285.18:29:12.53#ibcon#enter sib2, iclass 20, count 0 2006.285.18:29:12.53#ibcon#flushed, iclass 20, count 0 2006.285.18:29:12.53#ibcon#about to write, iclass 20, count 0 2006.285.18:29:12.53#ibcon#wrote, iclass 20, count 0 2006.285.18:29:12.53#ibcon#about to read 3, iclass 20, count 0 2006.285.18:29:12.57#ibcon#read 3, iclass 20, count 0 2006.285.18:29:12.57#ibcon#about to read 4, iclass 20, count 0 2006.285.18:29:12.57#ibcon#read 4, iclass 20, count 0 2006.285.18:29:12.57#ibcon#about to read 5, iclass 20, count 0 2006.285.18:29:12.57#ibcon#read 5, iclass 20, count 0 2006.285.18:29:12.57#ibcon#about to read 6, iclass 20, count 0 2006.285.18:29:12.57#ibcon#read 6, iclass 20, count 0 2006.285.18:29:12.57#ibcon#end of sib2, iclass 20, count 0 2006.285.18:29:12.57#ibcon#*after write, iclass 20, count 0 2006.285.18:29:12.57#ibcon#*before return 0, iclass 20, count 0 2006.285.18:29:12.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:29:12.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:29:12.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:29:12.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:29:12.57$vck44/va=5,3 2006.285.18:29:12.57#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.18:29:12.57#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.18:29:12.57#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:12.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:29:12.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:29:12.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:29:12.63#ibcon#enter wrdev, iclass 22, count 2 2006.285.18:29:12.63#ibcon#first serial, iclass 22, count 2 2006.285.18:29:12.63#ibcon#enter sib2, iclass 22, count 2 2006.285.18:29:12.63#ibcon#flushed, iclass 22, count 2 2006.285.18:29:12.63#ibcon#about to write, iclass 22, count 2 2006.285.18:29:12.63#ibcon#wrote, iclass 22, count 2 2006.285.18:29:12.63#ibcon#about to read 3, iclass 22, count 2 2006.285.18:29:12.65#ibcon#read 3, iclass 22, count 2 2006.285.18:29:12.65#ibcon#about to read 4, iclass 22, count 2 2006.285.18:29:12.65#ibcon#read 4, iclass 22, count 2 2006.285.18:29:12.65#ibcon#about to read 5, iclass 22, count 2 2006.285.18:29:12.65#ibcon#read 5, iclass 22, count 2 2006.285.18:29:12.65#ibcon#about to read 6, iclass 22, count 2 2006.285.18:29:12.65#ibcon#read 6, iclass 22, count 2 2006.285.18:29:12.65#ibcon#end of sib2, iclass 22, count 2 2006.285.18:29:12.65#ibcon#*mode == 0, iclass 22, count 2 2006.285.18:29:12.65#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.18:29:12.65#ibcon#[25=AT05-03\r\n] 2006.285.18:29:12.65#ibcon#*before write, iclass 22, count 2 2006.285.18:29:12.65#ibcon#enter sib2, iclass 22, count 2 2006.285.18:29:12.65#ibcon#flushed, iclass 22, count 2 2006.285.18:29:12.65#ibcon#about to write, iclass 22, count 2 2006.285.18:29:12.65#ibcon#wrote, iclass 22, count 2 2006.285.18:29:12.65#ibcon#about to read 3, iclass 22, count 2 2006.285.18:29:12.68#ibcon#read 3, iclass 22, count 2 2006.285.18:29:12.68#ibcon#about to read 4, iclass 22, count 2 2006.285.18:29:12.68#ibcon#read 4, iclass 22, count 2 2006.285.18:29:12.68#ibcon#about to read 5, iclass 22, count 2 2006.285.18:29:12.68#ibcon#read 5, iclass 22, count 2 2006.285.18:29:12.68#ibcon#about to read 6, iclass 22, count 2 2006.285.18:29:12.68#ibcon#read 6, iclass 22, count 2 2006.285.18:29:12.68#ibcon#end of sib2, iclass 22, count 2 2006.285.18:29:12.68#ibcon#*after write, iclass 22, count 2 2006.285.18:29:12.68#ibcon#*before return 0, iclass 22, count 2 2006.285.18:29:12.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:29:12.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:29:12.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.18:29:12.68#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:12.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:29:12.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:29:12.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:29:12.80#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:29:12.80#ibcon#first serial, iclass 22, count 0 2006.285.18:29:12.80#ibcon#enter sib2, iclass 22, count 0 2006.285.18:29:12.80#ibcon#flushed, iclass 22, count 0 2006.285.18:29:12.80#ibcon#about to write, iclass 22, count 0 2006.285.18:29:12.80#ibcon#wrote, iclass 22, count 0 2006.285.18:29:12.80#ibcon#about to read 3, iclass 22, count 0 2006.285.18:29:12.82#ibcon#read 3, iclass 22, count 0 2006.285.18:29:12.82#ibcon#about to read 4, iclass 22, count 0 2006.285.18:29:12.82#ibcon#read 4, iclass 22, count 0 2006.285.18:29:12.82#ibcon#about to read 5, iclass 22, count 0 2006.285.18:29:12.82#ibcon#read 5, iclass 22, count 0 2006.285.18:29:12.82#ibcon#about to read 6, iclass 22, count 0 2006.285.18:29:12.82#ibcon#read 6, iclass 22, count 0 2006.285.18:29:12.82#ibcon#end of sib2, iclass 22, count 0 2006.285.18:29:12.82#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:29:12.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:29:12.82#ibcon#[25=USB\r\n] 2006.285.18:29:12.82#ibcon#*before write, iclass 22, count 0 2006.285.18:29:12.82#ibcon#enter sib2, iclass 22, count 0 2006.285.18:29:12.82#ibcon#flushed, iclass 22, count 0 2006.285.18:29:12.82#ibcon#about to write, iclass 22, count 0 2006.285.18:29:12.82#ibcon#wrote, iclass 22, count 0 2006.285.18:29:12.82#ibcon#about to read 3, iclass 22, count 0 2006.285.18:29:12.85#ibcon#read 3, iclass 22, count 0 2006.285.18:29:12.85#ibcon#about to read 4, iclass 22, count 0 2006.285.18:29:12.85#ibcon#read 4, iclass 22, count 0 2006.285.18:29:12.85#ibcon#about to read 5, iclass 22, count 0 2006.285.18:29:12.85#ibcon#read 5, iclass 22, count 0 2006.285.18:29:12.85#ibcon#about to read 6, iclass 22, count 0 2006.285.18:29:12.85#ibcon#read 6, iclass 22, count 0 2006.285.18:29:12.85#ibcon#end of sib2, iclass 22, count 0 2006.285.18:29:12.85#ibcon#*after write, iclass 22, count 0 2006.285.18:29:12.85#ibcon#*before return 0, iclass 22, count 0 2006.285.18:29:12.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:29:12.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:29:12.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:29:12.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:29:12.85$vck44/valo=6,814.99 2006.285.18:29:12.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.18:29:12.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.18:29:12.85#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:12.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:29:12.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:29:12.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:29:12.85#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:29:12.85#ibcon#first serial, iclass 24, count 0 2006.285.18:29:12.85#ibcon#enter sib2, iclass 24, count 0 2006.285.18:29:12.85#ibcon#flushed, iclass 24, count 0 2006.285.18:29:12.85#ibcon#about to write, iclass 24, count 0 2006.285.18:29:12.85#ibcon#wrote, iclass 24, count 0 2006.285.18:29:12.85#ibcon#about to read 3, iclass 24, count 0 2006.285.18:29:12.87#ibcon#read 3, iclass 24, count 0 2006.285.18:29:12.87#ibcon#about to read 4, iclass 24, count 0 2006.285.18:29:12.87#ibcon#read 4, iclass 24, count 0 2006.285.18:29:12.87#ibcon#about to read 5, iclass 24, count 0 2006.285.18:29:12.87#ibcon#read 5, iclass 24, count 0 2006.285.18:29:12.87#ibcon#about to read 6, iclass 24, count 0 2006.285.18:29:12.87#ibcon#read 6, iclass 24, count 0 2006.285.18:29:12.87#ibcon#end of sib2, iclass 24, count 0 2006.285.18:29:12.87#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:29:12.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:29:12.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.18:29:12.87#ibcon#*before write, iclass 24, count 0 2006.285.18:29:12.87#ibcon#enter sib2, iclass 24, count 0 2006.285.18:29:12.87#ibcon#flushed, iclass 24, count 0 2006.285.18:29:12.87#ibcon#about to write, iclass 24, count 0 2006.285.18:29:12.87#ibcon#wrote, iclass 24, count 0 2006.285.18:29:12.87#ibcon#about to read 3, iclass 24, count 0 2006.285.18:29:12.91#ibcon#read 3, iclass 24, count 0 2006.285.18:29:12.91#ibcon#about to read 4, iclass 24, count 0 2006.285.18:29:12.91#ibcon#read 4, iclass 24, count 0 2006.285.18:29:12.91#ibcon#about to read 5, iclass 24, count 0 2006.285.18:29:12.91#ibcon#read 5, iclass 24, count 0 2006.285.18:29:12.91#ibcon#about to read 6, iclass 24, count 0 2006.285.18:29:12.91#ibcon#read 6, iclass 24, count 0 2006.285.18:29:12.91#ibcon#end of sib2, iclass 24, count 0 2006.285.18:29:12.91#ibcon#*after write, iclass 24, count 0 2006.285.18:29:12.91#ibcon#*before return 0, iclass 24, count 0 2006.285.18:29:12.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:29:12.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:29:12.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:29:12.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:29:12.91$vck44/va=6,4 2006.285.18:29:12.91#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.18:29:12.91#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.18:29:12.91#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:12.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:29:12.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:29:12.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:29:12.97#ibcon#enter wrdev, iclass 26, count 2 2006.285.18:29:12.97#ibcon#first serial, iclass 26, count 2 2006.285.18:29:12.97#ibcon#enter sib2, iclass 26, count 2 2006.285.18:29:12.97#ibcon#flushed, iclass 26, count 2 2006.285.18:29:12.97#ibcon#about to write, iclass 26, count 2 2006.285.18:29:12.97#ibcon#wrote, iclass 26, count 2 2006.285.18:29:12.97#ibcon#about to read 3, iclass 26, count 2 2006.285.18:29:12.99#ibcon#read 3, iclass 26, count 2 2006.285.18:29:12.99#ibcon#about to read 4, iclass 26, count 2 2006.285.18:29:12.99#ibcon#read 4, iclass 26, count 2 2006.285.18:29:12.99#ibcon#about to read 5, iclass 26, count 2 2006.285.18:29:12.99#ibcon#read 5, iclass 26, count 2 2006.285.18:29:12.99#ibcon#about to read 6, iclass 26, count 2 2006.285.18:29:12.99#ibcon#read 6, iclass 26, count 2 2006.285.18:29:12.99#ibcon#end of sib2, iclass 26, count 2 2006.285.18:29:12.99#ibcon#*mode == 0, iclass 26, count 2 2006.285.18:29:12.99#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.18:29:12.99#ibcon#[25=AT06-04\r\n] 2006.285.18:29:12.99#ibcon#*before write, iclass 26, count 2 2006.285.18:29:12.99#ibcon#enter sib2, iclass 26, count 2 2006.285.18:29:12.99#ibcon#flushed, iclass 26, count 2 2006.285.18:29:12.99#ibcon#about to write, iclass 26, count 2 2006.285.18:29:12.99#ibcon#wrote, iclass 26, count 2 2006.285.18:29:12.99#ibcon#about to read 3, iclass 26, count 2 2006.285.18:29:13.02#ibcon#read 3, iclass 26, count 2 2006.285.18:29:13.02#ibcon#about to read 4, iclass 26, count 2 2006.285.18:29:13.02#ibcon#read 4, iclass 26, count 2 2006.285.18:29:13.02#ibcon#about to read 5, iclass 26, count 2 2006.285.18:29:13.02#ibcon#read 5, iclass 26, count 2 2006.285.18:29:13.02#ibcon#about to read 6, iclass 26, count 2 2006.285.18:29:13.02#ibcon#read 6, iclass 26, count 2 2006.285.18:29:13.02#ibcon#end of sib2, iclass 26, count 2 2006.285.18:29:13.02#ibcon#*after write, iclass 26, count 2 2006.285.18:29:13.02#ibcon#*before return 0, iclass 26, count 2 2006.285.18:29:13.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:29:13.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:29:13.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.18:29:13.02#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:13.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:29:13.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:29:13.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:29:13.14#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:29:13.14#ibcon#first serial, iclass 26, count 0 2006.285.18:29:13.14#ibcon#enter sib2, iclass 26, count 0 2006.285.18:29:13.14#ibcon#flushed, iclass 26, count 0 2006.285.18:29:13.14#ibcon#about to write, iclass 26, count 0 2006.285.18:29:13.14#ibcon#wrote, iclass 26, count 0 2006.285.18:29:13.14#ibcon#about to read 3, iclass 26, count 0 2006.285.18:29:13.16#ibcon#read 3, iclass 26, count 0 2006.285.18:29:13.16#ibcon#about to read 4, iclass 26, count 0 2006.285.18:29:13.16#ibcon#read 4, iclass 26, count 0 2006.285.18:29:13.16#ibcon#about to read 5, iclass 26, count 0 2006.285.18:29:13.16#ibcon#read 5, iclass 26, count 0 2006.285.18:29:13.16#ibcon#about to read 6, iclass 26, count 0 2006.285.18:29:13.16#ibcon#read 6, iclass 26, count 0 2006.285.18:29:13.16#ibcon#end of sib2, iclass 26, count 0 2006.285.18:29:13.16#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:29:13.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:29:13.16#ibcon#[25=USB\r\n] 2006.285.18:29:13.16#ibcon#*before write, iclass 26, count 0 2006.285.18:29:13.16#ibcon#enter sib2, iclass 26, count 0 2006.285.18:29:13.16#ibcon#flushed, iclass 26, count 0 2006.285.18:29:13.16#ibcon#about to write, iclass 26, count 0 2006.285.18:29:13.16#ibcon#wrote, iclass 26, count 0 2006.285.18:29:13.16#ibcon#about to read 3, iclass 26, count 0 2006.285.18:29:13.19#ibcon#read 3, iclass 26, count 0 2006.285.18:29:13.19#ibcon#about to read 4, iclass 26, count 0 2006.285.18:29:13.19#ibcon#read 4, iclass 26, count 0 2006.285.18:29:13.19#ibcon#about to read 5, iclass 26, count 0 2006.285.18:29:13.19#ibcon#read 5, iclass 26, count 0 2006.285.18:29:13.19#ibcon#about to read 6, iclass 26, count 0 2006.285.18:29:13.19#ibcon#read 6, iclass 26, count 0 2006.285.18:29:13.19#ibcon#end of sib2, iclass 26, count 0 2006.285.18:29:13.19#ibcon#*after write, iclass 26, count 0 2006.285.18:29:13.19#ibcon#*before return 0, iclass 26, count 0 2006.285.18:29:13.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:29:13.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:29:13.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:29:13.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:29:13.19$vck44/valo=7,864.99 2006.285.18:29:13.20#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.18:29:13.20#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.18:29:13.20#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:13.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:29:13.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:29:13.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:29:13.20#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:29:13.20#ibcon#first serial, iclass 28, count 0 2006.285.18:29:13.20#ibcon#enter sib2, iclass 28, count 0 2006.285.18:29:13.20#ibcon#flushed, iclass 28, count 0 2006.285.18:29:13.20#ibcon#about to write, iclass 28, count 0 2006.285.18:29:13.20#ibcon#wrote, iclass 28, count 0 2006.285.18:29:13.20#ibcon#about to read 3, iclass 28, count 0 2006.285.18:29:13.22#ibcon#read 3, iclass 28, count 0 2006.285.18:29:13.22#ibcon#about to read 4, iclass 28, count 0 2006.285.18:29:13.22#ibcon#read 4, iclass 28, count 0 2006.285.18:29:13.22#ibcon#about to read 5, iclass 28, count 0 2006.285.18:29:13.22#ibcon#read 5, iclass 28, count 0 2006.285.18:29:13.22#ibcon#about to read 6, iclass 28, count 0 2006.285.18:29:13.22#ibcon#read 6, iclass 28, count 0 2006.285.18:29:13.22#ibcon#end of sib2, iclass 28, count 0 2006.285.18:29:13.22#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:29:13.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:29:13.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.18:29:13.22#ibcon#*before write, iclass 28, count 0 2006.285.18:29:13.22#ibcon#enter sib2, iclass 28, count 0 2006.285.18:29:13.22#ibcon#flushed, iclass 28, count 0 2006.285.18:29:13.22#ibcon#about to write, iclass 28, count 0 2006.285.18:29:13.22#ibcon#wrote, iclass 28, count 0 2006.285.18:29:13.22#ibcon#about to read 3, iclass 28, count 0 2006.285.18:29:13.26#ibcon#read 3, iclass 28, count 0 2006.285.18:29:13.26#ibcon#about to read 4, iclass 28, count 0 2006.285.18:29:13.26#ibcon#read 4, iclass 28, count 0 2006.285.18:29:13.26#ibcon#about to read 5, iclass 28, count 0 2006.285.18:29:13.26#ibcon#read 5, iclass 28, count 0 2006.285.18:29:13.26#ibcon#about to read 6, iclass 28, count 0 2006.285.18:29:13.26#ibcon#read 6, iclass 28, count 0 2006.285.18:29:13.26#ibcon#end of sib2, iclass 28, count 0 2006.285.18:29:13.26#ibcon#*after write, iclass 28, count 0 2006.285.18:29:13.26#ibcon#*before return 0, iclass 28, count 0 2006.285.18:29:13.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:29:13.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:29:13.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:29:13.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:29:13.26$vck44/va=7,4 2006.285.18:29:13.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.18:29:13.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.18:29:13.26#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:13.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:29:13.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:29:13.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:29:13.31#ibcon#enter wrdev, iclass 30, count 2 2006.285.18:29:13.31#ibcon#first serial, iclass 30, count 2 2006.285.18:29:13.31#ibcon#enter sib2, iclass 30, count 2 2006.285.18:29:13.31#ibcon#flushed, iclass 30, count 2 2006.285.18:29:13.31#ibcon#about to write, iclass 30, count 2 2006.285.18:29:13.31#ibcon#wrote, iclass 30, count 2 2006.285.18:29:13.31#ibcon#about to read 3, iclass 30, count 2 2006.285.18:29:13.33#ibcon#read 3, iclass 30, count 2 2006.285.18:29:13.33#ibcon#about to read 4, iclass 30, count 2 2006.285.18:29:13.33#ibcon#read 4, iclass 30, count 2 2006.285.18:29:13.33#ibcon#about to read 5, iclass 30, count 2 2006.285.18:29:13.33#ibcon#read 5, iclass 30, count 2 2006.285.18:29:13.33#ibcon#about to read 6, iclass 30, count 2 2006.285.18:29:13.33#ibcon#read 6, iclass 30, count 2 2006.285.18:29:13.33#ibcon#end of sib2, iclass 30, count 2 2006.285.18:29:13.33#ibcon#*mode == 0, iclass 30, count 2 2006.285.18:29:13.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.18:29:13.33#ibcon#[25=AT07-04\r\n] 2006.285.18:29:13.33#ibcon#*before write, iclass 30, count 2 2006.285.18:29:13.33#ibcon#enter sib2, iclass 30, count 2 2006.285.18:29:13.33#ibcon#flushed, iclass 30, count 2 2006.285.18:29:13.33#ibcon#about to write, iclass 30, count 2 2006.285.18:29:13.33#ibcon#wrote, iclass 30, count 2 2006.285.18:29:13.33#ibcon#about to read 3, iclass 30, count 2 2006.285.18:29:13.36#ibcon#read 3, iclass 30, count 2 2006.285.18:29:13.36#ibcon#about to read 4, iclass 30, count 2 2006.285.18:29:13.36#ibcon#read 4, iclass 30, count 2 2006.285.18:29:13.36#ibcon#about to read 5, iclass 30, count 2 2006.285.18:29:13.36#ibcon#read 5, iclass 30, count 2 2006.285.18:29:13.36#ibcon#about to read 6, iclass 30, count 2 2006.285.18:29:13.36#ibcon#read 6, iclass 30, count 2 2006.285.18:29:13.36#ibcon#end of sib2, iclass 30, count 2 2006.285.18:29:13.36#ibcon#*after write, iclass 30, count 2 2006.285.18:29:13.36#ibcon#*before return 0, iclass 30, count 2 2006.285.18:29:13.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:29:13.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:29:13.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.18:29:13.36#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:13.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:29:13.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:29:13.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:29:13.48#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:29:13.48#ibcon#first serial, iclass 30, count 0 2006.285.18:29:13.48#ibcon#enter sib2, iclass 30, count 0 2006.285.18:29:13.48#ibcon#flushed, iclass 30, count 0 2006.285.18:29:13.48#ibcon#about to write, iclass 30, count 0 2006.285.18:29:13.48#ibcon#wrote, iclass 30, count 0 2006.285.18:29:13.48#ibcon#about to read 3, iclass 30, count 0 2006.285.18:29:13.50#ibcon#read 3, iclass 30, count 0 2006.285.18:29:13.50#ibcon#about to read 4, iclass 30, count 0 2006.285.18:29:13.50#ibcon#read 4, iclass 30, count 0 2006.285.18:29:13.50#ibcon#about to read 5, iclass 30, count 0 2006.285.18:29:13.50#ibcon#read 5, iclass 30, count 0 2006.285.18:29:13.50#ibcon#about to read 6, iclass 30, count 0 2006.285.18:29:13.50#ibcon#read 6, iclass 30, count 0 2006.285.18:29:13.50#ibcon#end of sib2, iclass 30, count 0 2006.285.18:29:13.50#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:29:13.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:29:13.50#ibcon#[25=USB\r\n] 2006.285.18:29:13.50#ibcon#*before write, iclass 30, count 0 2006.285.18:29:13.50#ibcon#enter sib2, iclass 30, count 0 2006.285.18:29:13.50#ibcon#flushed, iclass 30, count 0 2006.285.18:29:13.50#ibcon#about to write, iclass 30, count 0 2006.285.18:29:13.50#ibcon#wrote, iclass 30, count 0 2006.285.18:29:13.50#ibcon#about to read 3, iclass 30, count 0 2006.285.18:29:13.53#ibcon#read 3, iclass 30, count 0 2006.285.18:29:13.53#ibcon#about to read 4, iclass 30, count 0 2006.285.18:29:13.53#ibcon#read 4, iclass 30, count 0 2006.285.18:29:13.53#ibcon#about to read 5, iclass 30, count 0 2006.285.18:29:13.53#ibcon#read 5, iclass 30, count 0 2006.285.18:29:13.53#ibcon#about to read 6, iclass 30, count 0 2006.285.18:29:13.53#ibcon#read 6, iclass 30, count 0 2006.285.18:29:13.53#ibcon#end of sib2, iclass 30, count 0 2006.285.18:29:13.53#ibcon#*after write, iclass 30, count 0 2006.285.18:29:13.53#ibcon#*before return 0, iclass 30, count 0 2006.285.18:29:13.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:29:13.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:29:13.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:29:13.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:29:13.53$vck44/valo=8,884.99 2006.285.18:29:13.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.18:29:13.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.18:29:13.53#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:13.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:29:13.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:29:13.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:29:13.53#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:29:13.53#ibcon#first serial, iclass 32, count 0 2006.285.18:29:13.53#ibcon#enter sib2, iclass 32, count 0 2006.285.18:29:13.53#ibcon#flushed, iclass 32, count 0 2006.285.18:29:13.53#ibcon#about to write, iclass 32, count 0 2006.285.18:29:13.53#ibcon#wrote, iclass 32, count 0 2006.285.18:29:13.53#ibcon#about to read 3, iclass 32, count 0 2006.285.18:29:13.55#ibcon#read 3, iclass 32, count 0 2006.285.18:29:13.55#ibcon#about to read 4, iclass 32, count 0 2006.285.18:29:13.55#ibcon#read 4, iclass 32, count 0 2006.285.18:29:13.55#ibcon#about to read 5, iclass 32, count 0 2006.285.18:29:13.55#ibcon#read 5, iclass 32, count 0 2006.285.18:29:13.55#ibcon#about to read 6, iclass 32, count 0 2006.285.18:29:13.55#ibcon#read 6, iclass 32, count 0 2006.285.18:29:13.55#ibcon#end of sib2, iclass 32, count 0 2006.285.18:29:13.55#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:29:13.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:29:13.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.18:29:13.55#ibcon#*before write, iclass 32, count 0 2006.285.18:29:13.55#ibcon#enter sib2, iclass 32, count 0 2006.285.18:29:13.55#ibcon#flushed, iclass 32, count 0 2006.285.18:29:13.55#ibcon#about to write, iclass 32, count 0 2006.285.18:29:13.55#ibcon#wrote, iclass 32, count 0 2006.285.18:29:13.55#ibcon#about to read 3, iclass 32, count 0 2006.285.18:29:13.59#ibcon#read 3, iclass 32, count 0 2006.285.18:29:13.59#ibcon#about to read 4, iclass 32, count 0 2006.285.18:29:13.59#ibcon#read 4, iclass 32, count 0 2006.285.18:29:13.59#ibcon#about to read 5, iclass 32, count 0 2006.285.18:29:13.59#ibcon#read 5, iclass 32, count 0 2006.285.18:29:13.59#ibcon#about to read 6, iclass 32, count 0 2006.285.18:29:13.59#ibcon#read 6, iclass 32, count 0 2006.285.18:29:13.59#ibcon#end of sib2, iclass 32, count 0 2006.285.18:29:13.59#ibcon#*after write, iclass 32, count 0 2006.285.18:29:13.59#ibcon#*before return 0, iclass 32, count 0 2006.285.18:29:13.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:29:13.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:29:13.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:29:13.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:29:13.59$vck44/va=8,3 2006.285.18:29:13.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.18:29:13.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.18:29:13.59#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:13.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:29:13.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:29:13.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:29:13.65#ibcon#enter wrdev, iclass 34, count 2 2006.285.18:29:13.65#ibcon#first serial, iclass 34, count 2 2006.285.18:29:13.65#ibcon#enter sib2, iclass 34, count 2 2006.285.18:29:13.65#ibcon#flushed, iclass 34, count 2 2006.285.18:29:13.65#ibcon#about to write, iclass 34, count 2 2006.285.18:29:13.65#ibcon#wrote, iclass 34, count 2 2006.285.18:29:13.65#ibcon#about to read 3, iclass 34, count 2 2006.285.18:29:13.67#ibcon#read 3, iclass 34, count 2 2006.285.18:29:13.67#ibcon#about to read 4, iclass 34, count 2 2006.285.18:29:13.67#ibcon#read 4, iclass 34, count 2 2006.285.18:29:13.67#ibcon#about to read 5, iclass 34, count 2 2006.285.18:29:13.67#ibcon#read 5, iclass 34, count 2 2006.285.18:29:13.67#ibcon#about to read 6, iclass 34, count 2 2006.285.18:29:13.67#ibcon#read 6, iclass 34, count 2 2006.285.18:29:13.67#ibcon#end of sib2, iclass 34, count 2 2006.285.18:29:13.67#ibcon#*mode == 0, iclass 34, count 2 2006.285.18:29:13.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.18:29:13.67#ibcon#[25=AT08-03\r\n] 2006.285.18:29:13.67#ibcon#*before write, iclass 34, count 2 2006.285.18:29:13.67#ibcon#enter sib2, iclass 34, count 2 2006.285.18:29:13.67#ibcon#flushed, iclass 34, count 2 2006.285.18:29:13.67#ibcon#about to write, iclass 34, count 2 2006.285.18:29:13.67#ibcon#wrote, iclass 34, count 2 2006.285.18:29:13.67#ibcon#about to read 3, iclass 34, count 2 2006.285.18:29:13.70#ibcon#read 3, iclass 34, count 2 2006.285.18:29:13.70#ibcon#about to read 4, iclass 34, count 2 2006.285.18:29:13.70#ibcon#read 4, iclass 34, count 2 2006.285.18:29:13.70#ibcon#about to read 5, iclass 34, count 2 2006.285.18:29:13.70#ibcon#read 5, iclass 34, count 2 2006.285.18:29:13.70#ibcon#about to read 6, iclass 34, count 2 2006.285.18:29:13.70#ibcon#read 6, iclass 34, count 2 2006.285.18:29:13.70#ibcon#end of sib2, iclass 34, count 2 2006.285.18:29:13.70#ibcon#*after write, iclass 34, count 2 2006.285.18:29:13.70#ibcon#*before return 0, iclass 34, count 2 2006.285.18:29:13.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:29:13.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:29:13.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.18:29:13.70#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:13.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:29:13.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:29:13.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:29:13.82#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:29:13.82#ibcon#first serial, iclass 34, count 0 2006.285.18:29:13.82#ibcon#enter sib2, iclass 34, count 0 2006.285.18:29:13.82#ibcon#flushed, iclass 34, count 0 2006.285.18:29:13.82#ibcon#about to write, iclass 34, count 0 2006.285.18:29:13.82#ibcon#wrote, iclass 34, count 0 2006.285.18:29:13.82#ibcon#about to read 3, iclass 34, count 0 2006.285.18:29:13.84#ibcon#read 3, iclass 34, count 0 2006.285.18:29:13.84#ibcon#about to read 4, iclass 34, count 0 2006.285.18:29:13.84#ibcon#read 4, iclass 34, count 0 2006.285.18:29:13.84#ibcon#about to read 5, iclass 34, count 0 2006.285.18:29:13.84#ibcon#read 5, iclass 34, count 0 2006.285.18:29:13.84#ibcon#about to read 6, iclass 34, count 0 2006.285.18:29:13.84#ibcon#read 6, iclass 34, count 0 2006.285.18:29:13.84#ibcon#end of sib2, iclass 34, count 0 2006.285.18:29:13.84#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:29:13.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:29:13.84#ibcon#[25=USB\r\n] 2006.285.18:29:13.84#ibcon#*before write, iclass 34, count 0 2006.285.18:29:13.84#ibcon#enter sib2, iclass 34, count 0 2006.285.18:29:13.84#ibcon#flushed, iclass 34, count 0 2006.285.18:29:13.84#ibcon#about to write, iclass 34, count 0 2006.285.18:29:13.84#ibcon#wrote, iclass 34, count 0 2006.285.18:29:13.84#ibcon#about to read 3, iclass 34, count 0 2006.285.18:29:13.87#abcon#<5=/00 0.2 0.6 15.371001014.7\r\n> 2006.285.18:29:13.87#ibcon#read 3, iclass 34, count 0 2006.285.18:29:13.87#ibcon#about to read 4, iclass 34, count 0 2006.285.18:29:13.87#ibcon#read 4, iclass 34, count 0 2006.285.18:29:13.87#ibcon#about to read 5, iclass 34, count 0 2006.285.18:29:13.87#ibcon#read 5, iclass 34, count 0 2006.285.18:29:13.87#ibcon#about to read 6, iclass 34, count 0 2006.285.18:29:13.87#ibcon#read 6, iclass 34, count 0 2006.285.18:29:13.87#ibcon#end of sib2, iclass 34, count 0 2006.285.18:29:13.87#ibcon#*after write, iclass 34, count 0 2006.285.18:29:13.87#ibcon#*before return 0, iclass 34, count 0 2006.285.18:29:13.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:29:13.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:29:13.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:29:13.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:29:13.87$vck44/vblo=1,629.99 2006.285.18:29:13.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.18:29:13.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.18:29:13.87#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:13.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:29:13.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:29:13.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:29:13.87#ibcon#enter wrdev, iclass 39, count 0 2006.285.18:29:13.87#ibcon#first serial, iclass 39, count 0 2006.285.18:29:13.87#ibcon#enter sib2, iclass 39, count 0 2006.285.18:29:13.87#ibcon#flushed, iclass 39, count 0 2006.285.18:29:13.87#ibcon#about to write, iclass 39, count 0 2006.285.18:29:13.87#ibcon#wrote, iclass 39, count 0 2006.285.18:29:13.87#ibcon#about to read 3, iclass 39, count 0 2006.285.18:29:13.89#abcon#{5=INTERFACE CLEAR} 2006.285.18:29:13.89#ibcon#read 3, iclass 39, count 0 2006.285.18:29:13.89#ibcon#about to read 4, iclass 39, count 0 2006.285.18:29:13.89#ibcon#read 4, iclass 39, count 0 2006.285.18:29:13.89#ibcon#about to read 5, iclass 39, count 0 2006.285.18:29:13.89#ibcon#read 5, iclass 39, count 0 2006.285.18:29:13.89#ibcon#about to read 6, iclass 39, count 0 2006.285.18:29:13.89#ibcon#read 6, iclass 39, count 0 2006.285.18:29:13.89#ibcon#end of sib2, iclass 39, count 0 2006.285.18:29:13.89#ibcon#*mode == 0, iclass 39, count 0 2006.285.18:29:13.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.18:29:13.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.18:29:13.89#ibcon#*before write, iclass 39, count 0 2006.285.18:29:13.89#ibcon#enter sib2, iclass 39, count 0 2006.285.18:29:13.89#ibcon#flushed, iclass 39, count 0 2006.285.18:29:13.89#ibcon#about to write, iclass 39, count 0 2006.285.18:29:13.89#ibcon#wrote, iclass 39, count 0 2006.285.18:29:13.89#ibcon#about to read 3, iclass 39, count 0 2006.285.18:29:13.93#ibcon#read 3, iclass 39, count 0 2006.285.18:29:13.93#ibcon#about to read 4, iclass 39, count 0 2006.285.18:29:13.93#ibcon#read 4, iclass 39, count 0 2006.285.18:29:13.93#ibcon#about to read 5, iclass 39, count 0 2006.285.18:29:13.93#ibcon#read 5, iclass 39, count 0 2006.285.18:29:13.93#ibcon#about to read 6, iclass 39, count 0 2006.285.18:29:13.93#ibcon#read 6, iclass 39, count 0 2006.285.18:29:13.93#ibcon#end of sib2, iclass 39, count 0 2006.285.18:29:13.93#ibcon#*after write, iclass 39, count 0 2006.285.18:29:13.93#ibcon#*before return 0, iclass 39, count 0 2006.285.18:29:13.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:29:13.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:29:13.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.18:29:13.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.18:29:13.93$vck44/vb=1,4 2006.285.18:29:13.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.18:29:13.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.18:29:13.93#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:13.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:29:13.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:29:13.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:29:13.93#ibcon#enter wrdev, iclass 3, count 2 2006.285.18:29:13.93#ibcon#first serial, iclass 3, count 2 2006.285.18:29:13.93#ibcon#enter sib2, iclass 3, count 2 2006.285.18:29:13.93#ibcon#flushed, iclass 3, count 2 2006.285.18:29:13.93#ibcon#about to write, iclass 3, count 2 2006.285.18:29:13.93#ibcon#wrote, iclass 3, count 2 2006.285.18:29:13.93#ibcon#about to read 3, iclass 3, count 2 2006.285.18:29:13.95#ibcon#read 3, iclass 3, count 2 2006.285.18:29:13.95#ibcon#about to read 4, iclass 3, count 2 2006.285.18:29:13.95#ibcon#read 4, iclass 3, count 2 2006.285.18:29:13.95#ibcon#about to read 5, iclass 3, count 2 2006.285.18:29:13.95#ibcon#read 5, iclass 3, count 2 2006.285.18:29:13.95#ibcon#about to read 6, iclass 3, count 2 2006.285.18:29:13.95#ibcon#read 6, iclass 3, count 2 2006.285.18:29:13.95#ibcon#end of sib2, iclass 3, count 2 2006.285.18:29:13.95#ibcon#*mode == 0, iclass 3, count 2 2006.285.18:29:13.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.18:29:13.95#ibcon#[27=AT01-04\r\n] 2006.285.18:29:13.95#ibcon#*before write, iclass 3, count 2 2006.285.18:29:13.95#ibcon#enter sib2, iclass 3, count 2 2006.285.18:29:13.95#ibcon#flushed, iclass 3, count 2 2006.285.18:29:13.95#ibcon#about to write, iclass 3, count 2 2006.285.18:29:13.95#ibcon#wrote, iclass 3, count 2 2006.285.18:29:13.95#ibcon#about to read 3, iclass 3, count 2 2006.285.18:29:13.95#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:29:13.98#ibcon#read 3, iclass 3, count 2 2006.285.18:29:13.98#ibcon#about to read 4, iclass 3, count 2 2006.285.18:29:13.98#ibcon#read 4, iclass 3, count 2 2006.285.18:29:13.98#ibcon#about to read 5, iclass 3, count 2 2006.285.18:29:13.98#ibcon#read 5, iclass 3, count 2 2006.285.18:29:13.98#ibcon#about to read 6, iclass 3, count 2 2006.285.18:29:13.98#ibcon#read 6, iclass 3, count 2 2006.285.18:29:13.98#ibcon#end of sib2, iclass 3, count 2 2006.285.18:29:13.98#ibcon#*after write, iclass 3, count 2 2006.285.18:29:13.98#ibcon#*before return 0, iclass 3, count 2 2006.285.18:29:13.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:29:13.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:29:13.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.18:29:13.98#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:13.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:29:14.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:29:14.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:29:14.10#ibcon#enter wrdev, iclass 3, count 0 2006.285.18:29:14.10#ibcon#first serial, iclass 3, count 0 2006.285.18:29:14.10#ibcon#enter sib2, iclass 3, count 0 2006.285.18:29:14.10#ibcon#flushed, iclass 3, count 0 2006.285.18:29:14.10#ibcon#about to write, iclass 3, count 0 2006.285.18:29:14.10#ibcon#wrote, iclass 3, count 0 2006.285.18:29:14.10#ibcon#about to read 3, iclass 3, count 0 2006.285.18:29:14.12#ibcon#read 3, iclass 3, count 0 2006.285.18:29:14.12#ibcon#about to read 4, iclass 3, count 0 2006.285.18:29:14.12#ibcon#read 4, iclass 3, count 0 2006.285.18:29:14.12#ibcon#about to read 5, iclass 3, count 0 2006.285.18:29:14.12#ibcon#read 5, iclass 3, count 0 2006.285.18:29:14.12#ibcon#about to read 6, iclass 3, count 0 2006.285.18:29:14.12#ibcon#read 6, iclass 3, count 0 2006.285.18:29:14.12#ibcon#end of sib2, iclass 3, count 0 2006.285.18:29:14.12#ibcon#*mode == 0, iclass 3, count 0 2006.285.18:29:14.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.18:29:14.12#ibcon#[27=USB\r\n] 2006.285.18:29:14.12#ibcon#*before write, iclass 3, count 0 2006.285.18:29:14.12#ibcon#enter sib2, iclass 3, count 0 2006.285.18:29:14.12#ibcon#flushed, iclass 3, count 0 2006.285.18:29:14.12#ibcon#about to write, iclass 3, count 0 2006.285.18:29:14.12#ibcon#wrote, iclass 3, count 0 2006.285.18:29:14.12#ibcon#about to read 3, iclass 3, count 0 2006.285.18:29:14.15#ibcon#read 3, iclass 3, count 0 2006.285.18:29:14.15#ibcon#about to read 4, iclass 3, count 0 2006.285.18:29:14.15#ibcon#read 4, iclass 3, count 0 2006.285.18:29:14.15#ibcon#about to read 5, iclass 3, count 0 2006.285.18:29:14.15#ibcon#read 5, iclass 3, count 0 2006.285.18:29:14.15#ibcon#about to read 6, iclass 3, count 0 2006.285.18:29:14.15#ibcon#read 6, iclass 3, count 0 2006.285.18:29:14.15#ibcon#end of sib2, iclass 3, count 0 2006.285.18:29:14.15#ibcon#*after write, iclass 3, count 0 2006.285.18:29:14.15#ibcon#*before return 0, iclass 3, count 0 2006.285.18:29:14.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:29:14.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:29:14.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.18:29:14.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.18:29:14.15$vck44/vblo=2,634.99 2006.285.18:29:14.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.18:29:14.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.18:29:14.15#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:14.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:29:14.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:29:14.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:29:14.15#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:29:14.15#ibcon#first serial, iclass 6, count 0 2006.285.18:29:14.15#ibcon#enter sib2, iclass 6, count 0 2006.285.18:29:14.15#ibcon#flushed, iclass 6, count 0 2006.285.18:29:14.15#ibcon#about to write, iclass 6, count 0 2006.285.18:29:14.15#ibcon#wrote, iclass 6, count 0 2006.285.18:29:14.15#ibcon#about to read 3, iclass 6, count 0 2006.285.18:29:14.17#ibcon#read 3, iclass 6, count 0 2006.285.18:29:14.52#ibcon#about to read 4, iclass 6, count 0 2006.285.18:29:14.52#ibcon#read 4, iclass 6, count 0 2006.285.18:29:14.52#ibcon#about to read 5, iclass 6, count 0 2006.285.18:29:14.52#ibcon#read 5, iclass 6, count 0 2006.285.18:29:14.52#ibcon#about to read 6, iclass 6, count 0 2006.285.18:29:14.52#ibcon#read 6, iclass 6, count 0 2006.285.18:29:14.52#ibcon#end of sib2, iclass 6, count 0 2006.285.18:29:14.52#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:29:14.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:29:14.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.18:29:14.52#ibcon#*before write, iclass 6, count 0 2006.285.18:29:14.52#ibcon#enter sib2, iclass 6, count 0 2006.285.18:29:14.52#ibcon#flushed, iclass 6, count 0 2006.285.18:29:14.52#ibcon#about to write, iclass 6, count 0 2006.285.18:29:14.52#ibcon#wrote, iclass 6, count 0 2006.285.18:29:14.52#ibcon#about to read 3, iclass 6, count 0 2006.285.18:29:14.56#ibcon#read 3, iclass 6, count 0 2006.285.18:29:14.56#ibcon#about to read 4, iclass 6, count 0 2006.285.18:29:14.56#ibcon#read 4, iclass 6, count 0 2006.285.18:29:14.56#ibcon#about to read 5, iclass 6, count 0 2006.285.18:29:14.56#ibcon#read 5, iclass 6, count 0 2006.285.18:29:14.56#ibcon#about to read 6, iclass 6, count 0 2006.285.18:29:14.56#ibcon#read 6, iclass 6, count 0 2006.285.18:29:14.56#ibcon#end of sib2, iclass 6, count 0 2006.285.18:29:14.56#ibcon#*after write, iclass 6, count 0 2006.285.18:29:14.56#ibcon#*before return 0, iclass 6, count 0 2006.285.18:29:14.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:29:14.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:29:14.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:29:14.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:29:14.56$vck44/vb=2,5 2006.285.18:29:14.56#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.18:29:14.56#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.18:29:14.56#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:14.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:29:14.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:29:14.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:29:14.56#ibcon#enter wrdev, iclass 10, count 2 2006.285.18:29:14.56#ibcon#first serial, iclass 10, count 2 2006.285.18:29:14.56#ibcon#enter sib2, iclass 10, count 2 2006.285.18:29:14.56#ibcon#flushed, iclass 10, count 2 2006.285.18:29:14.56#ibcon#about to write, iclass 10, count 2 2006.285.18:29:14.56#ibcon#wrote, iclass 10, count 2 2006.285.18:29:14.56#ibcon#about to read 3, iclass 10, count 2 2006.285.18:29:14.58#ibcon#read 3, iclass 10, count 2 2006.285.18:29:14.58#ibcon#about to read 4, iclass 10, count 2 2006.285.18:29:14.58#ibcon#read 4, iclass 10, count 2 2006.285.18:29:14.58#ibcon#about to read 5, iclass 10, count 2 2006.285.18:29:14.58#ibcon#read 5, iclass 10, count 2 2006.285.18:29:14.58#ibcon#about to read 6, iclass 10, count 2 2006.285.18:29:14.58#ibcon#read 6, iclass 10, count 2 2006.285.18:29:14.58#ibcon#end of sib2, iclass 10, count 2 2006.285.18:29:14.58#ibcon#*mode == 0, iclass 10, count 2 2006.285.18:29:14.58#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.18:29:14.58#ibcon#[27=AT02-05\r\n] 2006.285.18:29:14.58#ibcon#*before write, iclass 10, count 2 2006.285.18:29:14.58#ibcon#enter sib2, iclass 10, count 2 2006.285.18:29:14.58#ibcon#flushed, iclass 10, count 2 2006.285.18:29:14.58#ibcon#about to write, iclass 10, count 2 2006.285.18:29:14.58#ibcon#wrote, iclass 10, count 2 2006.285.18:29:14.58#ibcon#about to read 3, iclass 10, count 2 2006.285.18:29:14.61#ibcon#read 3, iclass 10, count 2 2006.285.18:29:14.61#ibcon#about to read 4, iclass 10, count 2 2006.285.18:29:14.61#ibcon#read 4, iclass 10, count 2 2006.285.18:29:14.61#ibcon#about to read 5, iclass 10, count 2 2006.285.18:29:14.61#ibcon#read 5, iclass 10, count 2 2006.285.18:29:14.61#ibcon#about to read 6, iclass 10, count 2 2006.285.18:29:14.61#ibcon#read 6, iclass 10, count 2 2006.285.18:29:14.61#ibcon#end of sib2, iclass 10, count 2 2006.285.18:29:14.61#ibcon#*after write, iclass 10, count 2 2006.285.18:29:14.61#ibcon#*before return 0, iclass 10, count 2 2006.285.18:29:14.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:29:14.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:29:14.61#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.18:29:14.61#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:14.61#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:29:14.73#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:29:14.73#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:29:14.73#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:29:14.73#ibcon#first serial, iclass 10, count 0 2006.285.18:29:14.73#ibcon#enter sib2, iclass 10, count 0 2006.285.18:29:14.73#ibcon#flushed, iclass 10, count 0 2006.285.18:29:14.73#ibcon#about to write, iclass 10, count 0 2006.285.18:29:14.73#ibcon#wrote, iclass 10, count 0 2006.285.18:29:14.73#ibcon#about to read 3, iclass 10, count 0 2006.285.18:29:14.75#ibcon#read 3, iclass 10, count 0 2006.285.18:29:14.75#ibcon#about to read 4, iclass 10, count 0 2006.285.18:29:14.75#ibcon#read 4, iclass 10, count 0 2006.285.18:29:14.75#ibcon#about to read 5, iclass 10, count 0 2006.285.18:29:14.75#ibcon#read 5, iclass 10, count 0 2006.285.18:29:14.75#ibcon#about to read 6, iclass 10, count 0 2006.285.18:29:14.75#ibcon#read 6, iclass 10, count 0 2006.285.18:29:14.75#ibcon#end of sib2, iclass 10, count 0 2006.285.18:29:14.75#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:29:14.75#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:29:14.75#ibcon#[27=USB\r\n] 2006.285.18:29:14.75#ibcon#*before write, iclass 10, count 0 2006.285.18:29:14.75#ibcon#enter sib2, iclass 10, count 0 2006.285.18:29:14.75#ibcon#flushed, iclass 10, count 0 2006.285.18:29:14.75#ibcon#about to write, iclass 10, count 0 2006.285.18:29:14.75#ibcon#wrote, iclass 10, count 0 2006.285.18:29:14.75#ibcon#about to read 3, iclass 10, count 0 2006.285.18:29:14.78#ibcon#read 3, iclass 10, count 0 2006.285.18:29:14.78#ibcon#about to read 4, iclass 10, count 0 2006.285.18:29:14.78#ibcon#read 4, iclass 10, count 0 2006.285.18:29:14.78#ibcon#about to read 5, iclass 10, count 0 2006.285.18:29:14.78#ibcon#read 5, iclass 10, count 0 2006.285.18:29:14.78#ibcon#about to read 6, iclass 10, count 0 2006.285.18:29:14.78#ibcon#read 6, iclass 10, count 0 2006.285.18:29:14.78#ibcon#end of sib2, iclass 10, count 0 2006.285.18:29:14.78#ibcon#*after write, iclass 10, count 0 2006.285.18:29:14.78#ibcon#*before return 0, iclass 10, count 0 2006.285.18:29:14.78#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:29:14.78#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:29:14.78#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:29:14.78#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:29:14.78$vck44/vblo=3,649.99 2006.285.18:29:14.78#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.18:29:14.78#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.18:29:14.78#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:14.78#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:29:14.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:29:14.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:29:14.78#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:29:14.78#ibcon#first serial, iclass 12, count 0 2006.285.18:29:14.78#ibcon#enter sib2, iclass 12, count 0 2006.285.18:29:14.78#ibcon#flushed, iclass 12, count 0 2006.285.18:29:14.78#ibcon#about to write, iclass 12, count 0 2006.285.18:29:14.78#ibcon#wrote, iclass 12, count 0 2006.285.18:29:14.78#ibcon#about to read 3, iclass 12, count 0 2006.285.18:29:14.80#ibcon#read 3, iclass 12, count 0 2006.285.18:29:14.80#ibcon#about to read 4, iclass 12, count 0 2006.285.18:29:14.80#ibcon#read 4, iclass 12, count 0 2006.285.18:29:14.80#ibcon#about to read 5, iclass 12, count 0 2006.285.18:29:14.80#ibcon#read 5, iclass 12, count 0 2006.285.18:29:14.80#ibcon#about to read 6, iclass 12, count 0 2006.285.18:29:14.80#ibcon#read 6, iclass 12, count 0 2006.285.18:29:14.80#ibcon#end of sib2, iclass 12, count 0 2006.285.18:29:14.80#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:29:14.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:29:14.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.18:29:14.80#ibcon#*before write, iclass 12, count 0 2006.285.18:29:14.80#ibcon#enter sib2, iclass 12, count 0 2006.285.18:29:14.80#ibcon#flushed, iclass 12, count 0 2006.285.18:29:14.80#ibcon#about to write, iclass 12, count 0 2006.285.18:29:14.80#ibcon#wrote, iclass 12, count 0 2006.285.18:29:14.80#ibcon#about to read 3, iclass 12, count 0 2006.285.18:29:14.84#ibcon#read 3, iclass 12, count 0 2006.285.18:29:14.84#ibcon#about to read 4, iclass 12, count 0 2006.285.18:29:14.84#ibcon#read 4, iclass 12, count 0 2006.285.18:29:14.84#ibcon#about to read 5, iclass 12, count 0 2006.285.18:29:14.84#ibcon#read 5, iclass 12, count 0 2006.285.18:29:14.84#ibcon#about to read 6, iclass 12, count 0 2006.285.18:29:14.84#ibcon#read 6, iclass 12, count 0 2006.285.18:29:14.84#ibcon#end of sib2, iclass 12, count 0 2006.285.18:29:14.84#ibcon#*after write, iclass 12, count 0 2006.285.18:29:14.84#ibcon#*before return 0, iclass 12, count 0 2006.285.18:29:14.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:29:14.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:29:14.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:29:14.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:29:14.84$vck44/vb=3,4 2006.285.18:29:14.84#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.18:29:14.84#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.18:29:14.84#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:14.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:29:14.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:29:14.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:29:14.90#ibcon#enter wrdev, iclass 14, count 2 2006.285.18:29:14.90#ibcon#first serial, iclass 14, count 2 2006.285.18:29:14.90#ibcon#enter sib2, iclass 14, count 2 2006.285.18:29:14.90#ibcon#flushed, iclass 14, count 2 2006.285.18:29:14.90#ibcon#about to write, iclass 14, count 2 2006.285.18:29:14.90#ibcon#wrote, iclass 14, count 2 2006.285.18:29:14.90#ibcon#about to read 3, iclass 14, count 2 2006.285.18:29:14.92#ibcon#read 3, iclass 14, count 2 2006.285.18:29:14.92#ibcon#about to read 4, iclass 14, count 2 2006.285.18:29:14.92#ibcon#read 4, iclass 14, count 2 2006.285.18:29:14.92#ibcon#about to read 5, iclass 14, count 2 2006.285.18:29:14.92#ibcon#read 5, iclass 14, count 2 2006.285.18:29:14.92#ibcon#about to read 6, iclass 14, count 2 2006.285.18:29:14.92#ibcon#read 6, iclass 14, count 2 2006.285.18:29:14.92#ibcon#end of sib2, iclass 14, count 2 2006.285.18:29:14.92#ibcon#*mode == 0, iclass 14, count 2 2006.285.18:29:14.92#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.18:29:14.92#ibcon#[27=AT03-04\r\n] 2006.285.18:29:14.92#ibcon#*before write, iclass 14, count 2 2006.285.18:29:14.92#ibcon#enter sib2, iclass 14, count 2 2006.285.18:29:14.92#ibcon#flushed, iclass 14, count 2 2006.285.18:29:14.92#ibcon#about to write, iclass 14, count 2 2006.285.18:29:14.92#ibcon#wrote, iclass 14, count 2 2006.285.18:29:14.92#ibcon#about to read 3, iclass 14, count 2 2006.285.18:29:14.95#ibcon#read 3, iclass 14, count 2 2006.285.18:29:14.95#ibcon#about to read 4, iclass 14, count 2 2006.285.18:29:14.95#ibcon#read 4, iclass 14, count 2 2006.285.18:29:14.95#ibcon#about to read 5, iclass 14, count 2 2006.285.18:29:14.95#ibcon#read 5, iclass 14, count 2 2006.285.18:29:14.95#ibcon#about to read 6, iclass 14, count 2 2006.285.18:29:14.95#ibcon#read 6, iclass 14, count 2 2006.285.18:29:14.95#ibcon#end of sib2, iclass 14, count 2 2006.285.18:29:14.95#ibcon#*after write, iclass 14, count 2 2006.285.18:29:14.95#ibcon#*before return 0, iclass 14, count 2 2006.285.18:29:14.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:29:14.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:29:14.95#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.18:29:14.95#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:14.95#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:29:15.07#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:29:15.07#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:29:15.07#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:29:15.07#ibcon#first serial, iclass 14, count 0 2006.285.18:29:15.07#ibcon#enter sib2, iclass 14, count 0 2006.285.18:29:15.07#ibcon#flushed, iclass 14, count 0 2006.285.18:29:15.07#ibcon#about to write, iclass 14, count 0 2006.285.18:29:15.07#ibcon#wrote, iclass 14, count 0 2006.285.18:29:15.07#ibcon#about to read 3, iclass 14, count 0 2006.285.18:29:15.09#ibcon#read 3, iclass 14, count 0 2006.285.18:29:15.09#ibcon#about to read 4, iclass 14, count 0 2006.285.18:29:15.09#ibcon#read 4, iclass 14, count 0 2006.285.18:29:15.09#ibcon#about to read 5, iclass 14, count 0 2006.285.18:29:15.09#ibcon#read 5, iclass 14, count 0 2006.285.18:29:15.09#ibcon#about to read 6, iclass 14, count 0 2006.285.18:29:15.09#ibcon#read 6, iclass 14, count 0 2006.285.18:29:15.09#ibcon#end of sib2, iclass 14, count 0 2006.285.18:29:15.09#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:29:15.09#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:29:15.09#ibcon#[27=USB\r\n] 2006.285.18:29:15.09#ibcon#*before write, iclass 14, count 0 2006.285.18:29:15.09#ibcon#enter sib2, iclass 14, count 0 2006.285.18:29:15.09#ibcon#flushed, iclass 14, count 0 2006.285.18:29:15.09#ibcon#about to write, iclass 14, count 0 2006.285.18:29:15.09#ibcon#wrote, iclass 14, count 0 2006.285.18:29:15.09#ibcon#about to read 3, iclass 14, count 0 2006.285.18:29:15.12#ibcon#read 3, iclass 14, count 0 2006.285.18:29:15.12#ibcon#about to read 4, iclass 14, count 0 2006.285.18:29:15.12#ibcon#read 4, iclass 14, count 0 2006.285.18:29:15.12#ibcon#about to read 5, iclass 14, count 0 2006.285.18:29:15.12#ibcon#read 5, iclass 14, count 0 2006.285.18:29:15.12#ibcon#about to read 6, iclass 14, count 0 2006.285.18:29:15.12#ibcon#read 6, iclass 14, count 0 2006.285.18:29:15.12#ibcon#end of sib2, iclass 14, count 0 2006.285.18:29:15.12#ibcon#*after write, iclass 14, count 0 2006.285.18:29:15.12#ibcon#*before return 0, iclass 14, count 0 2006.285.18:29:15.12#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:29:15.12#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:29:15.12#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:29:15.12#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:29:15.12$vck44/vblo=4,679.99 2006.285.18:29:15.12#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.18:29:15.12#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.18:29:15.12#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:15.12#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:29:15.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:29:15.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:29:15.12#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:29:15.12#ibcon#first serial, iclass 16, count 0 2006.285.18:29:15.12#ibcon#enter sib2, iclass 16, count 0 2006.285.18:29:15.12#ibcon#flushed, iclass 16, count 0 2006.285.18:29:15.12#ibcon#about to write, iclass 16, count 0 2006.285.18:29:15.12#ibcon#wrote, iclass 16, count 0 2006.285.18:29:15.12#ibcon#about to read 3, iclass 16, count 0 2006.285.18:29:15.14#ibcon#read 3, iclass 16, count 0 2006.285.18:29:15.14#ibcon#about to read 4, iclass 16, count 0 2006.285.18:29:15.14#ibcon#read 4, iclass 16, count 0 2006.285.18:29:15.14#ibcon#about to read 5, iclass 16, count 0 2006.285.18:29:15.14#ibcon#read 5, iclass 16, count 0 2006.285.18:29:15.14#ibcon#about to read 6, iclass 16, count 0 2006.285.18:29:15.14#ibcon#read 6, iclass 16, count 0 2006.285.18:29:15.14#ibcon#end of sib2, iclass 16, count 0 2006.285.18:29:15.14#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:29:15.14#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:29:15.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.18:29:15.14#ibcon#*before write, iclass 16, count 0 2006.285.18:29:15.14#ibcon#enter sib2, iclass 16, count 0 2006.285.18:29:15.14#ibcon#flushed, iclass 16, count 0 2006.285.18:29:15.14#ibcon#about to write, iclass 16, count 0 2006.285.18:29:15.14#ibcon#wrote, iclass 16, count 0 2006.285.18:29:15.14#ibcon#about to read 3, iclass 16, count 0 2006.285.18:29:15.18#ibcon#read 3, iclass 16, count 0 2006.285.18:29:15.18#ibcon#about to read 4, iclass 16, count 0 2006.285.18:29:15.18#ibcon#read 4, iclass 16, count 0 2006.285.18:29:15.18#ibcon#about to read 5, iclass 16, count 0 2006.285.18:29:15.18#ibcon#read 5, iclass 16, count 0 2006.285.18:29:15.18#ibcon#about to read 6, iclass 16, count 0 2006.285.18:29:15.18#ibcon#read 6, iclass 16, count 0 2006.285.18:29:15.18#ibcon#end of sib2, iclass 16, count 0 2006.285.18:29:15.18#ibcon#*after write, iclass 16, count 0 2006.285.18:29:15.18#ibcon#*before return 0, iclass 16, count 0 2006.285.18:29:15.18#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:29:15.18#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:29:15.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:29:15.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:29:15.18$vck44/vb=4,5 2006.285.18:29:15.18#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.18:29:15.18#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.18:29:15.18#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:15.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:29:15.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:29:15.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:29:15.24#ibcon#enter wrdev, iclass 18, count 2 2006.285.18:29:15.24#ibcon#first serial, iclass 18, count 2 2006.285.18:29:15.24#ibcon#enter sib2, iclass 18, count 2 2006.285.18:29:15.24#ibcon#flushed, iclass 18, count 2 2006.285.18:29:15.24#ibcon#about to write, iclass 18, count 2 2006.285.18:29:15.24#ibcon#wrote, iclass 18, count 2 2006.285.18:29:15.24#ibcon#about to read 3, iclass 18, count 2 2006.285.18:29:15.26#ibcon#read 3, iclass 18, count 2 2006.285.18:29:15.26#ibcon#about to read 4, iclass 18, count 2 2006.285.18:29:15.26#ibcon#read 4, iclass 18, count 2 2006.285.18:29:15.26#ibcon#about to read 5, iclass 18, count 2 2006.285.18:29:15.26#ibcon#read 5, iclass 18, count 2 2006.285.18:29:15.26#ibcon#about to read 6, iclass 18, count 2 2006.285.18:29:15.26#ibcon#read 6, iclass 18, count 2 2006.285.18:29:15.26#ibcon#end of sib2, iclass 18, count 2 2006.285.18:29:15.26#ibcon#*mode == 0, iclass 18, count 2 2006.285.18:29:15.26#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.18:29:15.26#ibcon#[27=AT04-05\r\n] 2006.285.18:29:15.26#ibcon#*before write, iclass 18, count 2 2006.285.18:29:15.26#ibcon#enter sib2, iclass 18, count 2 2006.285.18:29:15.26#ibcon#flushed, iclass 18, count 2 2006.285.18:29:15.26#ibcon#about to write, iclass 18, count 2 2006.285.18:29:15.26#ibcon#wrote, iclass 18, count 2 2006.285.18:29:15.26#ibcon#about to read 3, iclass 18, count 2 2006.285.18:29:15.29#ibcon#read 3, iclass 18, count 2 2006.285.18:29:15.29#ibcon#about to read 4, iclass 18, count 2 2006.285.18:29:15.29#ibcon#read 4, iclass 18, count 2 2006.285.18:29:15.29#ibcon#about to read 5, iclass 18, count 2 2006.285.18:29:15.29#ibcon#read 5, iclass 18, count 2 2006.285.18:29:15.29#ibcon#about to read 6, iclass 18, count 2 2006.285.18:29:15.29#ibcon#read 6, iclass 18, count 2 2006.285.18:29:15.29#ibcon#end of sib2, iclass 18, count 2 2006.285.18:29:15.29#ibcon#*after write, iclass 18, count 2 2006.285.18:29:15.29#ibcon#*before return 0, iclass 18, count 2 2006.285.18:29:15.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:29:15.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:29:15.29#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.18:29:15.29#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:15.29#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:29:15.41#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:29:15.41#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:29:15.41#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:29:15.41#ibcon#first serial, iclass 18, count 0 2006.285.18:29:15.41#ibcon#enter sib2, iclass 18, count 0 2006.285.18:29:15.41#ibcon#flushed, iclass 18, count 0 2006.285.18:29:15.41#ibcon#about to write, iclass 18, count 0 2006.285.18:29:15.41#ibcon#wrote, iclass 18, count 0 2006.285.18:29:15.41#ibcon#about to read 3, iclass 18, count 0 2006.285.18:29:15.43#ibcon#read 3, iclass 18, count 0 2006.285.18:29:15.43#ibcon#about to read 4, iclass 18, count 0 2006.285.18:29:15.43#ibcon#read 4, iclass 18, count 0 2006.285.18:29:15.43#ibcon#about to read 5, iclass 18, count 0 2006.285.18:29:15.43#ibcon#read 5, iclass 18, count 0 2006.285.18:29:15.43#ibcon#about to read 6, iclass 18, count 0 2006.285.18:29:15.43#ibcon#read 6, iclass 18, count 0 2006.285.18:29:15.43#ibcon#end of sib2, iclass 18, count 0 2006.285.18:29:15.43#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:29:15.43#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:29:15.43#ibcon#[27=USB\r\n] 2006.285.18:29:15.43#ibcon#*before write, iclass 18, count 0 2006.285.18:29:15.43#ibcon#enter sib2, iclass 18, count 0 2006.285.18:29:15.43#ibcon#flushed, iclass 18, count 0 2006.285.18:29:15.43#ibcon#about to write, iclass 18, count 0 2006.285.18:29:15.43#ibcon#wrote, iclass 18, count 0 2006.285.18:29:15.43#ibcon#about to read 3, iclass 18, count 0 2006.285.18:29:15.46#ibcon#read 3, iclass 18, count 0 2006.285.18:29:15.46#ibcon#about to read 4, iclass 18, count 0 2006.285.18:29:15.46#ibcon#read 4, iclass 18, count 0 2006.285.18:29:15.46#ibcon#about to read 5, iclass 18, count 0 2006.285.18:29:15.46#ibcon#read 5, iclass 18, count 0 2006.285.18:29:15.46#ibcon#about to read 6, iclass 18, count 0 2006.285.18:29:15.46#ibcon#read 6, iclass 18, count 0 2006.285.18:29:15.46#ibcon#end of sib2, iclass 18, count 0 2006.285.18:29:15.46#ibcon#*after write, iclass 18, count 0 2006.285.18:29:15.46#ibcon#*before return 0, iclass 18, count 0 2006.285.18:29:15.46#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:29:15.46#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:29:15.46#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:29:15.46#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:29:15.46$vck44/vblo=5,709.99 2006.285.18:29:15.46#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.18:29:15.46#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.18:29:15.46#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:15.46#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:29:15.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:29:15.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:29:15.46#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:29:15.46#ibcon#first serial, iclass 20, count 0 2006.285.18:29:15.46#ibcon#enter sib2, iclass 20, count 0 2006.285.18:29:15.46#ibcon#flushed, iclass 20, count 0 2006.285.18:29:15.46#ibcon#about to write, iclass 20, count 0 2006.285.18:29:15.46#ibcon#wrote, iclass 20, count 0 2006.285.18:29:15.46#ibcon#about to read 3, iclass 20, count 0 2006.285.18:29:15.48#ibcon#read 3, iclass 20, count 0 2006.285.18:29:15.48#ibcon#about to read 4, iclass 20, count 0 2006.285.18:29:15.48#ibcon#read 4, iclass 20, count 0 2006.285.18:29:15.48#ibcon#about to read 5, iclass 20, count 0 2006.285.18:29:15.48#ibcon#read 5, iclass 20, count 0 2006.285.18:29:15.48#ibcon#about to read 6, iclass 20, count 0 2006.285.18:29:15.48#ibcon#read 6, iclass 20, count 0 2006.285.18:29:15.48#ibcon#end of sib2, iclass 20, count 0 2006.285.18:29:15.48#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:29:15.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:29:15.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.18:29:15.48#ibcon#*before write, iclass 20, count 0 2006.285.18:29:15.48#ibcon#enter sib2, iclass 20, count 0 2006.285.18:29:15.48#ibcon#flushed, iclass 20, count 0 2006.285.18:29:15.48#ibcon#about to write, iclass 20, count 0 2006.285.18:29:15.48#ibcon#wrote, iclass 20, count 0 2006.285.18:29:15.48#ibcon#about to read 3, iclass 20, count 0 2006.285.18:29:15.52#ibcon#read 3, iclass 20, count 0 2006.285.18:29:15.52#ibcon#about to read 4, iclass 20, count 0 2006.285.18:29:15.52#ibcon#read 4, iclass 20, count 0 2006.285.18:29:15.52#ibcon#about to read 5, iclass 20, count 0 2006.285.18:29:15.52#ibcon#read 5, iclass 20, count 0 2006.285.18:29:15.52#ibcon#about to read 6, iclass 20, count 0 2006.285.18:29:15.52#ibcon#read 6, iclass 20, count 0 2006.285.18:29:15.52#ibcon#end of sib2, iclass 20, count 0 2006.285.18:29:15.52#ibcon#*after write, iclass 20, count 0 2006.285.18:29:15.52#ibcon#*before return 0, iclass 20, count 0 2006.285.18:29:15.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:29:15.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:29:15.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:29:15.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:29:15.52$vck44/vb=5,4 2006.285.18:29:15.52#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.18:29:15.52#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.18:29:15.52#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:15.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:29:15.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:29:15.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:29:15.58#ibcon#enter wrdev, iclass 22, count 2 2006.285.18:29:15.58#ibcon#first serial, iclass 22, count 2 2006.285.18:29:15.58#ibcon#enter sib2, iclass 22, count 2 2006.285.18:29:15.58#ibcon#flushed, iclass 22, count 2 2006.285.18:29:15.58#ibcon#about to write, iclass 22, count 2 2006.285.18:29:15.58#ibcon#wrote, iclass 22, count 2 2006.285.18:29:15.58#ibcon#about to read 3, iclass 22, count 2 2006.285.18:29:15.60#ibcon#read 3, iclass 22, count 2 2006.285.18:29:15.60#ibcon#about to read 4, iclass 22, count 2 2006.285.18:29:15.60#ibcon#read 4, iclass 22, count 2 2006.285.18:29:15.60#ibcon#about to read 5, iclass 22, count 2 2006.285.18:29:15.60#ibcon#read 5, iclass 22, count 2 2006.285.18:29:15.60#ibcon#about to read 6, iclass 22, count 2 2006.285.18:29:15.60#ibcon#read 6, iclass 22, count 2 2006.285.18:29:15.60#ibcon#end of sib2, iclass 22, count 2 2006.285.18:29:15.60#ibcon#*mode == 0, iclass 22, count 2 2006.285.18:29:15.60#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.18:29:15.60#ibcon#[27=AT05-04\r\n] 2006.285.18:29:15.60#ibcon#*before write, iclass 22, count 2 2006.285.18:29:15.60#ibcon#enter sib2, iclass 22, count 2 2006.285.18:29:15.60#ibcon#flushed, iclass 22, count 2 2006.285.18:29:15.60#ibcon#about to write, iclass 22, count 2 2006.285.18:29:15.60#ibcon#wrote, iclass 22, count 2 2006.285.18:29:15.60#ibcon#about to read 3, iclass 22, count 2 2006.285.18:29:15.63#ibcon#read 3, iclass 22, count 2 2006.285.18:29:15.63#ibcon#about to read 4, iclass 22, count 2 2006.285.18:29:15.63#ibcon#read 4, iclass 22, count 2 2006.285.18:29:15.63#ibcon#about to read 5, iclass 22, count 2 2006.285.18:29:15.63#ibcon#read 5, iclass 22, count 2 2006.285.18:29:15.63#ibcon#about to read 6, iclass 22, count 2 2006.285.18:29:15.63#ibcon#read 6, iclass 22, count 2 2006.285.18:29:15.63#ibcon#end of sib2, iclass 22, count 2 2006.285.18:29:15.63#ibcon#*after write, iclass 22, count 2 2006.285.18:29:15.63#ibcon#*before return 0, iclass 22, count 2 2006.285.18:29:15.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:29:15.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:29:15.63#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.18:29:15.63#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:15.63#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:29:15.75#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:29:15.75#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:29:15.75#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:29:15.75#ibcon#first serial, iclass 22, count 0 2006.285.18:29:15.75#ibcon#enter sib2, iclass 22, count 0 2006.285.18:29:15.75#ibcon#flushed, iclass 22, count 0 2006.285.18:29:15.75#ibcon#about to write, iclass 22, count 0 2006.285.18:29:15.75#ibcon#wrote, iclass 22, count 0 2006.285.18:29:15.75#ibcon#about to read 3, iclass 22, count 0 2006.285.18:29:15.77#ibcon#read 3, iclass 22, count 0 2006.285.18:29:15.77#ibcon#about to read 4, iclass 22, count 0 2006.285.18:29:15.77#ibcon#read 4, iclass 22, count 0 2006.285.18:29:15.77#ibcon#about to read 5, iclass 22, count 0 2006.285.18:29:15.77#ibcon#read 5, iclass 22, count 0 2006.285.18:29:15.77#ibcon#about to read 6, iclass 22, count 0 2006.285.18:29:15.77#ibcon#read 6, iclass 22, count 0 2006.285.18:29:15.77#ibcon#end of sib2, iclass 22, count 0 2006.285.18:29:15.77#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:29:15.77#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:29:15.77#ibcon#[27=USB\r\n] 2006.285.18:29:15.77#ibcon#*before write, iclass 22, count 0 2006.285.18:29:15.77#ibcon#enter sib2, iclass 22, count 0 2006.285.18:29:15.77#ibcon#flushed, iclass 22, count 0 2006.285.18:29:15.77#ibcon#about to write, iclass 22, count 0 2006.285.18:29:15.77#ibcon#wrote, iclass 22, count 0 2006.285.18:29:15.77#ibcon#about to read 3, iclass 22, count 0 2006.285.18:29:15.80#ibcon#read 3, iclass 22, count 0 2006.285.18:29:15.80#ibcon#about to read 4, iclass 22, count 0 2006.285.18:29:15.80#ibcon#read 4, iclass 22, count 0 2006.285.18:29:15.80#ibcon#about to read 5, iclass 22, count 0 2006.285.18:29:15.80#ibcon#read 5, iclass 22, count 0 2006.285.18:29:15.80#ibcon#about to read 6, iclass 22, count 0 2006.285.18:29:15.80#ibcon#read 6, iclass 22, count 0 2006.285.18:29:15.80#ibcon#end of sib2, iclass 22, count 0 2006.285.18:29:15.80#ibcon#*after write, iclass 22, count 0 2006.285.18:29:15.80#ibcon#*before return 0, iclass 22, count 0 2006.285.18:29:15.80#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:29:15.80#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:29:15.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:29:15.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:29:15.80$vck44/vblo=6,719.99 2006.285.18:29:15.80#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.18:29:15.80#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.18:29:15.80#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:15.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:29:15.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:29:15.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:29:15.80#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:29:15.80#ibcon#first serial, iclass 24, count 0 2006.285.18:29:15.80#ibcon#enter sib2, iclass 24, count 0 2006.285.18:29:15.80#ibcon#flushed, iclass 24, count 0 2006.285.18:29:15.80#ibcon#about to write, iclass 24, count 0 2006.285.18:29:15.80#ibcon#wrote, iclass 24, count 0 2006.285.18:29:15.80#ibcon#about to read 3, iclass 24, count 0 2006.285.18:29:15.82#ibcon#read 3, iclass 24, count 0 2006.285.18:29:15.82#ibcon#about to read 4, iclass 24, count 0 2006.285.18:29:15.82#ibcon#read 4, iclass 24, count 0 2006.285.18:29:15.82#ibcon#about to read 5, iclass 24, count 0 2006.285.18:29:15.82#ibcon#read 5, iclass 24, count 0 2006.285.18:29:15.82#ibcon#about to read 6, iclass 24, count 0 2006.285.18:29:15.82#ibcon#read 6, iclass 24, count 0 2006.285.18:29:15.82#ibcon#end of sib2, iclass 24, count 0 2006.285.18:29:15.82#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:29:15.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:29:15.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.18:29:15.82#ibcon#*before write, iclass 24, count 0 2006.285.18:29:15.82#ibcon#enter sib2, iclass 24, count 0 2006.285.18:29:15.82#ibcon#flushed, iclass 24, count 0 2006.285.18:29:15.82#ibcon#about to write, iclass 24, count 0 2006.285.18:29:15.82#ibcon#wrote, iclass 24, count 0 2006.285.18:29:15.82#ibcon#about to read 3, iclass 24, count 0 2006.285.18:29:15.86#ibcon#read 3, iclass 24, count 0 2006.285.18:29:15.86#ibcon#about to read 4, iclass 24, count 0 2006.285.18:29:15.86#ibcon#read 4, iclass 24, count 0 2006.285.18:29:15.86#ibcon#about to read 5, iclass 24, count 0 2006.285.18:29:15.86#ibcon#read 5, iclass 24, count 0 2006.285.18:29:15.86#ibcon#about to read 6, iclass 24, count 0 2006.285.18:29:15.86#ibcon#read 6, iclass 24, count 0 2006.285.18:29:15.86#ibcon#end of sib2, iclass 24, count 0 2006.285.18:29:15.86#ibcon#*after write, iclass 24, count 0 2006.285.18:29:15.86#ibcon#*before return 0, iclass 24, count 0 2006.285.18:29:15.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:29:15.86#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:29:15.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:29:15.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:29:15.86$vck44/vb=6,3 2006.285.18:29:15.86#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.18:29:15.86#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.18:29:15.86#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:15.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:29:15.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:29:15.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:29:15.92#ibcon#enter wrdev, iclass 26, count 2 2006.285.18:29:15.92#ibcon#first serial, iclass 26, count 2 2006.285.18:29:15.92#ibcon#enter sib2, iclass 26, count 2 2006.285.18:29:15.92#ibcon#flushed, iclass 26, count 2 2006.285.18:29:15.92#ibcon#about to write, iclass 26, count 2 2006.285.18:29:15.92#ibcon#wrote, iclass 26, count 2 2006.285.18:29:15.92#ibcon#about to read 3, iclass 26, count 2 2006.285.18:29:15.94#ibcon#read 3, iclass 26, count 2 2006.285.18:29:15.94#ibcon#about to read 4, iclass 26, count 2 2006.285.18:29:15.94#ibcon#read 4, iclass 26, count 2 2006.285.18:29:15.94#ibcon#about to read 5, iclass 26, count 2 2006.285.18:29:15.94#ibcon#read 5, iclass 26, count 2 2006.285.18:29:15.94#ibcon#about to read 6, iclass 26, count 2 2006.285.18:29:15.94#ibcon#read 6, iclass 26, count 2 2006.285.18:29:15.94#ibcon#end of sib2, iclass 26, count 2 2006.285.18:29:15.94#ibcon#*mode == 0, iclass 26, count 2 2006.285.18:29:15.94#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.18:29:15.94#ibcon#[27=AT06-03\r\n] 2006.285.18:29:15.94#ibcon#*before write, iclass 26, count 2 2006.285.18:29:15.94#ibcon#enter sib2, iclass 26, count 2 2006.285.18:29:15.94#ibcon#flushed, iclass 26, count 2 2006.285.18:29:15.94#ibcon#about to write, iclass 26, count 2 2006.285.18:29:15.94#ibcon#wrote, iclass 26, count 2 2006.285.18:29:15.94#ibcon#about to read 3, iclass 26, count 2 2006.285.18:29:15.97#ibcon#read 3, iclass 26, count 2 2006.285.18:29:15.97#ibcon#about to read 4, iclass 26, count 2 2006.285.18:29:15.97#ibcon#read 4, iclass 26, count 2 2006.285.18:29:15.97#ibcon#about to read 5, iclass 26, count 2 2006.285.18:29:15.97#ibcon#read 5, iclass 26, count 2 2006.285.18:29:15.97#ibcon#about to read 6, iclass 26, count 2 2006.285.18:29:15.97#ibcon#read 6, iclass 26, count 2 2006.285.18:29:15.97#ibcon#end of sib2, iclass 26, count 2 2006.285.18:29:15.97#ibcon#*after write, iclass 26, count 2 2006.285.18:29:15.97#ibcon#*before return 0, iclass 26, count 2 2006.285.18:29:15.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:29:15.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:29:15.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.18:29:15.97#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:15.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:29:16.09#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:29:16.09#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:29:16.09#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:29:16.09#ibcon#first serial, iclass 26, count 0 2006.285.18:29:16.09#ibcon#enter sib2, iclass 26, count 0 2006.285.18:29:16.09#ibcon#flushed, iclass 26, count 0 2006.285.18:29:16.09#ibcon#about to write, iclass 26, count 0 2006.285.18:29:16.09#ibcon#wrote, iclass 26, count 0 2006.285.18:29:16.09#ibcon#about to read 3, iclass 26, count 0 2006.285.18:29:16.11#ibcon#read 3, iclass 26, count 0 2006.285.18:29:16.11#ibcon#about to read 4, iclass 26, count 0 2006.285.18:29:16.11#ibcon#read 4, iclass 26, count 0 2006.285.18:29:16.11#ibcon#about to read 5, iclass 26, count 0 2006.285.18:29:16.11#ibcon#read 5, iclass 26, count 0 2006.285.18:29:16.11#ibcon#about to read 6, iclass 26, count 0 2006.285.18:29:16.11#ibcon#read 6, iclass 26, count 0 2006.285.18:29:16.11#ibcon#end of sib2, iclass 26, count 0 2006.285.18:29:16.11#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:29:16.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:29:16.11#ibcon#[27=USB\r\n] 2006.285.18:29:16.11#ibcon#*before write, iclass 26, count 0 2006.285.18:29:16.11#ibcon#enter sib2, iclass 26, count 0 2006.285.18:29:16.11#ibcon#flushed, iclass 26, count 0 2006.285.18:29:16.11#ibcon#about to write, iclass 26, count 0 2006.285.18:29:16.11#ibcon#wrote, iclass 26, count 0 2006.285.18:29:16.11#ibcon#about to read 3, iclass 26, count 0 2006.285.18:29:16.14#ibcon#read 3, iclass 26, count 0 2006.285.18:29:16.14#ibcon#about to read 4, iclass 26, count 0 2006.285.18:29:16.14#ibcon#read 4, iclass 26, count 0 2006.285.18:29:16.14#ibcon#about to read 5, iclass 26, count 0 2006.285.18:29:16.14#ibcon#read 5, iclass 26, count 0 2006.285.18:29:16.14#ibcon#about to read 6, iclass 26, count 0 2006.285.18:29:16.14#ibcon#read 6, iclass 26, count 0 2006.285.18:29:16.14#ibcon#end of sib2, iclass 26, count 0 2006.285.18:29:16.14#ibcon#*after write, iclass 26, count 0 2006.285.18:29:16.14#ibcon#*before return 0, iclass 26, count 0 2006.285.18:29:16.14#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:29:16.14#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:29:16.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:29:16.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:29:16.14$vck44/vblo=7,734.99 2006.285.18:29:16.14#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.18:29:16.14#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.18:29:16.14#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:16.14#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:29:16.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:29:16.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:29:16.14#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:29:16.14#ibcon#first serial, iclass 28, count 0 2006.285.18:29:16.14#ibcon#enter sib2, iclass 28, count 0 2006.285.18:29:16.14#ibcon#flushed, iclass 28, count 0 2006.285.18:29:16.14#ibcon#about to write, iclass 28, count 0 2006.285.18:29:16.14#ibcon#wrote, iclass 28, count 0 2006.285.18:29:16.14#ibcon#about to read 3, iclass 28, count 0 2006.285.18:29:16.16#ibcon#read 3, iclass 28, count 0 2006.285.18:29:16.29#ibcon#about to read 4, iclass 28, count 0 2006.285.18:29:16.29#ibcon#read 4, iclass 28, count 0 2006.285.18:29:16.29#ibcon#about to read 5, iclass 28, count 0 2006.285.18:29:16.29#ibcon#read 5, iclass 28, count 0 2006.285.18:29:16.29#ibcon#about to read 6, iclass 28, count 0 2006.285.18:29:16.29#ibcon#read 6, iclass 28, count 0 2006.285.18:29:16.29#ibcon#end of sib2, iclass 28, count 0 2006.285.18:29:16.29#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:29:16.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:29:16.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.18:29:16.29#ibcon#*before write, iclass 28, count 0 2006.285.18:29:16.29#ibcon#enter sib2, iclass 28, count 0 2006.285.18:29:16.29#ibcon#flushed, iclass 28, count 0 2006.285.18:29:16.29#ibcon#about to write, iclass 28, count 0 2006.285.18:29:16.29#ibcon#wrote, iclass 28, count 0 2006.285.18:29:16.29#ibcon#about to read 3, iclass 28, count 0 2006.285.18:29:16.33#ibcon#read 3, iclass 28, count 0 2006.285.18:29:16.33#ibcon#about to read 4, iclass 28, count 0 2006.285.18:29:16.33#ibcon#read 4, iclass 28, count 0 2006.285.18:29:16.33#ibcon#about to read 5, iclass 28, count 0 2006.285.18:29:16.33#ibcon#read 5, iclass 28, count 0 2006.285.18:29:16.33#ibcon#about to read 6, iclass 28, count 0 2006.285.18:29:16.33#ibcon#read 6, iclass 28, count 0 2006.285.18:29:16.33#ibcon#end of sib2, iclass 28, count 0 2006.285.18:29:16.33#ibcon#*after write, iclass 28, count 0 2006.285.18:29:16.33#ibcon#*before return 0, iclass 28, count 0 2006.285.18:29:16.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:29:16.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:29:16.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:29:16.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:29:16.33$vck44/vb=7,4 2006.285.18:29:16.33#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.18:29:16.33#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.18:29:16.33#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:16.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:29:16.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:29:16.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:29:16.33#ibcon#enter wrdev, iclass 30, count 2 2006.285.18:29:16.33#ibcon#first serial, iclass 30, count 2 2006.285.18:29:16.33#ibcon#enter sib2, iclass 30, count 2 2006.285.18:29:16.33#ibcon#flushed, iclass 30, count 2 2006.285.18:29:16.33#ibcon#about to write, iclass 30, count 2 2006.285.18:29:16.33#ibcon#wrote, iclass 30, count 2 2006.285.18:29:16.33#ibcon#about to read 3, iclass 30, count 2 2006.285.18:29:16.35#ibcon#read 3, iclass 30, count 2 2006.285.18:29:16.35#ibcon#about to read 4, iclass 30, count 2 2006.285.18:29:16.35#ibcon#read 4, iclass 30, count 2 2006.285.18:29:16.35#ibcon#about to read 5, iclass 30, count 2 2006.285.18:29:16.35#ibcon#read 5, iclass 30, count 2 2006.285.18:29:16.35#ibcon#about to read 6, iclass 30, count 2 2006.285.18:29:16.35#ibcon#read 6, iclass 30, count 2 2006.285.18:29:16.35#ibcon#end of sib2, iclass 30, count 2 2006.285.18:29:16.35#ibcon#*mode == 0, iclass 30, count 2 2006.285.18:29:16.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.18:29:16.35#ibcon#[27=AT07-04\r\n] 2006.285.18:29:16.35#ibcon#*before write, iclass 30, count 2 2006.285.18:29:16.35#ibcon#enter sib2, iclass 30, count 2 2006.285.18:29:16.35#ibcon#flushed, iclass 30, count 2 2006.285.18:29:16.35#ibcon#about to write, iclass 30, count 2 2006.285.18:29:16.35#ibcon#wrote, iclass 30, count 2 2006.285.18:29:16.35#ibcon#about to read 3, iclass 30, count 2 2006.285.18:29:16.38#ibcon#read 3, iclass 30, count 2 2006.285.18:29:16.38#ibcon#about to read 4, iclass 30, count 2 2006.285.18:29:16.38#ibcon#read 4, iclass 30, count 2 2006.285.18:29:16.38#ibcon#about to read 5, iclass 30, count 2 2006.285.18:29:16.38#ibcon#read 5, iclass 30, count 2 2006.285.18:29:16.38#ibcon#about to read 6, iclass 30, count 2 2006.285.18:29:16.38#ibcon#read 6, iclass 30, count 2 2006.285.18:29:16.38#ibcon#end of sib2, iclass 30, count 2 2006.285.18:29:16.38#ibcon#*after write, iclass 30, count 2 2006.285.18:29:16.38#ibcon#*before return 0, iclass 30, count 2 2006.285.18:29:16.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:29:16.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:29:16.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.18:29:16.38#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:16.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:29:16.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:29:16.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:29:16.50#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:29:16.50#ibcon#first serial, iclass 30, count 0 2006.285.18:29:16.50#ibcon#enter sib2, iclass 30, count 0 2006.285.18:29:16.50#ibcon#flushed, iclass 30, count 0 2006.285.18:29:16.50#ibcon#about to write, iclass 30, count 0 2006.285.18:29:16.50#ibcon#wrote, iclass 30, count 0 2006.285.18:29:16.50#ibcon#about to read 3, iclass 30, count 0 2006.285.18:29:16.52#ibcon#read 3, iclass 30, count 0 2006.285.18:29:16.52#ibcon#about to read 4, iclass 30, count 0 2006.285.18:29:16.52#ibcon#read 4, iclass 30, count 0 2006.285.18:29:16.52#ibcon#about to read 5, iclass 30, count 0 2006.285.18:29:16.52#ibcon#read 5, iclass 30, count 0 2006.285.18:29:16.52#ibcon#about to read 6, iclass 30, count 0 2006.285.18:29:16.52#ibcon#read 6, iclass 30, count 0 2006.285.18:29:16.52#ibcon#end of sib2, iclass 30, count 0 2006.285.18:29:16.52#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:29:16.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:29:16.52#ibcon#[27=USB\r\n] 2006.285.18:29:16.52#ibcon#*before write, iclass 30, count 0 2006.285.18:29:16.52#ibcon#enter sib2, iclass 30, count 0 2006.285.18:29:16.52#ibcon#flushed, iclass 30, count 0 2006.285.18:29:16.52#ibcon#about to write, iclass 30, count 0 2006.285.18:29:16.52#ibcon#wrote, iclass 30, count 0 2006.285.18:29:16.52#ibcon#about to read 3, iclass 30, count 0 2006.285.18:29:16.55#ibcon#read 3, iclass 30, count 0 2006.285.18:29:16.55#ibcon#about to read 4, iclass 30, count 0 2006.285.18:29:16.55#ibcon#read 4, iclass 30, count 0 2006.285.18:29:16.55#ibcon#about to read 5, iclass 30, count 0 2006.285.18:29:16.55#ibcon#read 5, iclass 30, count 0 2006.285.18:29:16.55#ibcon#about to read 6, iclass 30, count 0 2006.285.18:29:16.55#ibcon#read 6, iclass 30, count 0 2006.285.18:29:16.55#ibcon#end of sib2, iclass 30, count 0 2006.285.18:29:16.55#ibcon#*after write, iclass 30, count 0 2006.285.18:29:16.55#ibcon#*before return 0, iclass 30, count 0 2006.285.18:29:16.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:29:16.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:29:16.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:29:16.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:29:16.55$vck44/vblo=8,744.99 2006.285.18:29:16.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.18:29:16.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.18:29:16.55#ibcon#ireg 17 cls_cnt 0 2006.285.18:29:16.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:29:16.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:29:16.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:29:16.55#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:29:16.55#ibcon#first serial, iclass 32, count 0 2006.285.18:29:16.55#ibcon#enter sib2, iclass 32, count 0 2006.285.18:29:16.55#ibcon#flushed, iclass 32, count 0 2006.285.18:29:16.55#ibcon#about to write, iclass 32, count 0 2006.285.18:29:16.55#ibcon#wrote, iclass 32, count 0 2006.285.18:29:16.55#ibcon#about to read 3, iclass 32, count 0 2006.285.18:29:16.57#ibcon#read 3, iclass 32, count 0 2006.285.18:29:16.57#ibcon#about to read 4, iclass 32, count 0 2006.285.18:29:16.57#ibcon#read 4, iclass 32, count 0 2006.285.18:29:16.57#ibcon#about to read 5, iclass 32, count 0 2006.285.18:29:16.57#ibcon#read 5, iclass 32, count 0 2006.285.18:29:16.57#ibcon#about to read 6, iclass 32, count 0 2006.285.18:29:16.57#ibcon#read 6, iclass 32, count 0 2006.285.18:29:16.57#ibcon#end of sib2, iclass 32, count 0 2006.285.18:29:16.57#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:29:16.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:29:16.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.18:29:16.57#ibcon#*before write, iclass 32, count 0 2006.285.18:29:16.57#ibcon#enter sib2, iclass 32, count 0 2006.285.18:29:16.57#ibcon#flushed, iclass 32, count 0 2006.285.18:29:16.57#ibcon#about to write, iclass 32, count 0 2006.285.18:29:16.57#ibcon#wrote, iclass 32, count 0 2006.285.18:29:16.57#ibcon#about to read 3, iclass 32, count 0 2006.285.18:29:16.61#ibcon#read 3, iclass 32, count 0 2006.285.18:29:16.61#ibcon#about to read 4, iclass 32, count 0 2006.285.18:29:16.61#ibcon#read 4, iclass 32, count 0 2006.285.18:29:16.61#ibcon#about to read 5, iclass 32, count 0 2006.285.18:29:16.61#ibcon#read 5, iclass 32, count 0 2006.285.18:29:16.61#ibcon#about to read 6, iclass 32, count 0 2006.285.18:29:16.61#ibcon#read 6, iclass 32, count 0 2006.285.18:29:16.61#ibcon#end of sib2, iclass 32, count 0 2006.285.18:29:16.61#ibcon#*after write, iclass 32, count 0 2006.285.18:29:16.61#ibcon#*before return 0, iclass 32, count 0 2006.285.18:29:16.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:29:16.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:29:16.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:29:16.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:29:16.61$vck44/vb=8,4 2006.285.18:29:16.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.18:29:16.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.18:29:16.61#ibcon#ireg 11 cls_cnt 2 2006.285.18:29:16.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:29:16.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:29:16.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:29:16.67#ibcon#enter wrdev, iclass 34, count 2 2006.285.18:29:16.67#ibcon#first serial, iclass 34, count 2 2006.285.18:29:16.67#ibcon#enter sib2, iclass 34, count 2 2006.285.18:29:16.67#ibcon#flushed, iclass 34, count 2 2006.285.18:29:16.67#ibcon#about to write, iclass 34, count 2 2006.285.18:29:16.67#ibcon#wrote, iclass 34, count 2 2006.285.18:29:16.67#ibcon#about to read 3, iclass 34, count 2 2006.285.18:29:16.69#ibcon#read 3, iclass 34, count 2 2006.285.18:29:16.69#ibcon#about to read 4, iclass 34, count 2 2006.285.18:29:16.69#ibcon#read 4, iclass 34, count 2 2006.285.18:29:16.69#ibcon#about to read 5, iclass 34, count 2 2006.285.18:29:16.69#ibcon#read 5, iclass 34, count 2 2006.285.18:29:16.69#ibcon#about to read 6, iclass 34, count 2 2006.285.18:29:16.69#ibcon#read 6, iclass 34, count 2 2006.285.18:29:16.69#ibcon#end of sib2, iclass 34, count 2 2006.285.18:29:16.69#ibcon#*mode == 0, iclass 34, count 2 2006.285.18:29:16.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.18:29:16.69#ibcon#[27=AT08-04\r\n] 2006.285.18:29:16.69#ibcon#*before write, iclass 34, count 2 2006.285.18:29:16.69#ibcon#enter sib2, iclass 34, count 2 2006.285.18:29:16.69#ibcon#flushed, iclass 34, count 2 2006.285.18:29:16.69#ibcon#about to write, iclass 34, count 2 2006.285.18:29:16.69#ibcon#wrote, iclass 34, count 2 2006.285.18:29:16.69#ibcon#about to read 3, iclass 34, count 2 2006.285.18:29:16.72#ibcon#read 3, iclass 34, count 2 2006.285.18:29:16.72#ibcon#about to read 4, iclass 34, count 2 2006.285.18:29:16.72#ibcon#read 4, iclass 34, count 2 2006.285.18:29:16.72#ibcon#about to read 5, iclass 34, count 2 2006.285.18:29:16.72#ibcon#read 5, iclass 34, count 2 2006.285.18:29:16.72#ibcon#about to read 6, iclass 34, count 2 2006.285.18:29:16.72#ibcon#read 6, iclass 34, count 2 2006.285.18:29:16.72#ibcon#end of sib2, iclass 34, count 2 2006.285.18:29:16.72#ibcon#*after write, iclass 34, count 2 2006.285.18:29:16.72#ibcon#*before return 0, iclass 34, count 2 2006.285.18:29:16.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:29:16.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:29:16.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.18:29:16.72#ibcon#ireg 7 cls_cnt 0 2006.285.18:29:16.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:29:16.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:29:16.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:29:16.84#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:29:16.84#ibcon#first serial, iclass 34, count 0 2006.285.18:29:16.84#ibcon#enter sib2, iclass 34, count 0 2006.285.18:29:16.84#ibcon#flushed, iclass 34, count 0 2006.285.18:29:16.84#ibcon#about to write, iclass 34, count 0 2006.285.18:29:16.84#ibcon#wrote, iclass 34, count 0 2006.285.18:29:16.84#ibcon#about to read 3, iclass 34, count 0 2006.285.18:29:16.86#ibcon#read 3, iclass 34, count 0 2006.285.18:29:16.86#ibcon#about to read 4, iclass 34, count 0 2006.285.18:29:16.86#ibcon#read 4, iclass 34, count 0 2006.285.18:29:16.86#ibcon#about to read 5, iclass 34, count 0 2006.285.18:29:16.86#ibcon#read 5, iclass 34, count 0 2006.285.18:29:16.86#ibcon#about to read 6, iclass 34, count 0 2006.285.18:29:16.86#ibcon#read 6, iclass 34, count 0 2006.285.18:29:16.86#ibcon#end of sib2, iclass 34, count 0 2006.285.18:29:16.86#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:29:16.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:29:16.86#ibcon#[27=USB\r\n] 2006.285.18:29:16.86#ibcon#*before write, iclass 34, count 0 2006.285.18:29:16.86#ibcon#enter sib2, iclass 34, count 0 2006.285.18:29:16.86#ibcon#flushed, iclass 34, count 0 2006.285.18:29:16.86#ibcon#about to write, iclass 34, count 0 2006.285.18:29:16.86#ibcon#wrote, iclass 34, count 0 2006.285.18:29:16.86#ibcon#about to read 3, iclass 34, count 0 2006.285.18:29:16.89#ibcon#read 3, iclass 34, count 0 2006.285.18:29:16.89#ibcon#about to read 4, iclass 34, count 0 2006.285.18:29:16.89#ibcon#read 4, iclass 34, count 0 2006.285.18:29:16.89#ibcon#about to read 5, iclass 34, count 0 2006.285.18:29:16.89#ibcon#read 5, iclass 34, count 0 2006.285.18:29:16.89#ibcon#about to read 6, iclass 34, count 0 2006.285.18:29:16.89#ibcon#read 6, iclass 34, count 0 2006.285.18:29:16.89#ibcon#end of sib2, iclass 34, count 0 2006.285.18:29:16.89#ibcon#*after write, iclass 34, count 0 2006.285.18:29:16.89#ibcon#*before return 0, iclass 34, count 0 2006.285.18:29:16.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:29:16.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:29:16.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:29:16.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:29:16.89$vck44/vabw=wide 2006.285.18:29:16.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.18:29:16.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.18:29:16.89#ibcon#ireg 8 cls_cnt 0 2006.285.18:29:16.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:29:16.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:29:16.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:29:16.89#ibcon#enter wrdev, iclass 36, count 0 2006.285.18:29:16.89#ibcon#first serial, iclass 36, count 0 2006.285.18:29:16.89#ibcon#enter sib2, iclass 36, count 0 2006.285.18:29:16.89#ibcon#flushed, iclass 36, count 0 2006.285.18:29:16.89#ibcon#about to write, iclass 36, count 0 2006.285.18:29:16.89#ibcon#wrote, iclass 36, count 0 2006.285.18:29:16.89#ibcon#about to read 3, iclass 36, count 0 2006.285.18:29:16.91#ibcon#read 3, iclass 36, count 0 2006.285.18:29:16.91#ibcon#about to read 4, iclass 36, count 0 2006.285.18:29:16.91#ibcon#read 4, iclass 36, count 0 2006.285.18:29:16.91#ibcon#about to read 5, iclass 36, count 0 2006.285.18:29:16.91#ibcon#read 5, iclass 36, count 0 2006.285.18:29:16.91#ibcon#about to read 6, iclass 36, count 0 2006.285.18:29:16.91#ibcon#read 6, iclass 36, count 0 2006.285.18:29:16.91#ibcon#end of sib2, iclass 36, count 0 2006.285.18:29:16.91#ibcon#*mode == 0, iclass 36, count 0 2006.285.18:29:16.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.18:29:16.91#ibcon#[25=BW32\r\n] 2006.285.18:29:16.91#ibcon#*before write, iclass 36, count 0 2006.285.18:29:16.91#ibcon#enter sib2, iclass 36, count 0 2006.285.18:29:16.91#ibcon#flushed, iclass 36, count 0 2006.285.18:29:16.91#ibcon#about to write, iclass 36, count 0 2006.285.18:29:16.91#ibcon#wrote, iclass 36, count 0 2006.285.18:29:16.91#ibcon#about to read 3, iclass 36, count 0 2006.285.18:29:16.94#ibcon#read 3, iclass 36, count 0 2006.285.18:29:16.94#ibcon#about to read 4, iclass 36, count 0 2006.285.18:29:16.94#ibcon#read 4, iclass 36, count 0 2006.285.18:29:16.94#ibcon#about to read 5, iclass 36, count 0 2006.285.18:29:16.94#ibcon#read 5, iclass 36, count 0 2006.285.18:29:16.94#ibcon#about to read 6, iclass 36, count 0 2006.285.18:29:16.94#ibcon#read 6, iclass 36, count 0 2006.285.18:29:16.94#ibcon#end of sib2, iclass 36, count 0 2006.285.18:29:16.94#ibcon#*after write, iclass 36, count 0 2006.285.18:29:16.94#ibcon#*before return 0, iclass 36, count 0 2006.285.18:29:16.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:29:16.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:29:16.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.18:29:16.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.18:29:16.94$vck44/vbbw=wide 2006.285.18:29:16.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.18:29:16.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.18:29:16.94#ibcon#ireg 8 cls_cnt 0 2006.285.18:29:16.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:29:17.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:29:17.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:29:17.01#ibcon#enter wrdev, iclass 38, count 0 2006.285.18:29:17.01#ibcon#first serial, iclass 38, count 0 2006.285.18:29:17.01#ibcon#enter sib2, iclass 38, count 0 2006.285.18:29:17.01#ibcon#flushed, iclass 38, count 0 2006.285.18:29:17.01#ibcon#about to write, iclass 38, count 0 2006.285.18:29:17.01#ibcon#wrote, iclass 38, count 0 2006.285.18:29:17.01#ibcon#about to read 3, iclass 38, count 0 2006.285.18:29:17.03#ibcon#read 3, iclass 38, count 0 2006.285.18:29:17.03#ibcon#about to read 4, iclass 38, count 0 2006.285.18:29:17.03#ibcon#read 4, iclass 38, count 0 2006.285.18:29:17.03#ibcon#about to read 5, iclass 38, count 0 2006.285.18:29:17.03#ibcon#read 5, iclass 38, count 0 2006.285.18:29:17.03#ibcon#about to read 6, iclass 38, count 0 2006.285.18:29:17.03#ibcon#read 6, iclass 38, count 0 2006.285.18:29:17.03#ibcon#end of sib2, iclass 38, count 0 2006.285.18:29:17.03#ibcon#*mode == 0, iclass 38, count 0 2006.285.18:29:17.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.18:29:17.03#ibcon#[27=BW32\r\n] 2006.285.18:29:17.03#ibcon#*before write, iclass 38, count 0 2006.285.18:29:17.03#ibcon#enter sib2, iclass 38, count 0 2006.285.18:29:17.03#ibcon#flushed, iclass 38, count 0 2006.285.18:29:17.03#ibcon#about to write, iclass 38, count 0 2006.285.18:29:17.03#ibcon#wrote, iclass 38, count 0 2006.285.18:29:17.03#ibcon#about to read 3, iclass 38, count 0 2006.285.18:29:17.06#ibcon#read 3, iclass 38, count 0 2006.285.18:29:17.06#ibcon#about to read 4, iclass 38, count 0 2006.285.18:29:17.06#ibcon#read 4, iclass 38, count 0 2006.285.18:29:17.06#ibcon#about to read 5, iclass 38, count 0 2006.285.18:29:17.06#ibcon#read 5, iclass 38, count 0 2006.285.18:29:17.06#ibcon#about to read 6, iclass 38, count 0 2006.285.18:29:17.06#ibcon#read 6, iclass 38, count 0 2006.285.18:29:17.06#ibcon#end of sib2, iclass 38, count 0 2006.285.18:29:17.06#ibcon#*after write, iclass 38, count 0 2006.285.18:29:17.06#ibcon#*before return 0, iclass 38, count 0 2006.285.18:29:17.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:29:17.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:29:17.06#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.18:29:17.06#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.18:29:17.06$setupk4/ifdk4 2006.285.18:29:17.06$ifdk4/lo= 2006.285.18:29:17.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.18:29:17.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.18:29:17.06$ifdk4/patch= 2006.285.18:29:17.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.18:29:17.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.18:29:17.06$setupk4/!*+20s 2006.285.18:29:24.04#abcon#<5=/00 0.2 0.6 15.361001014.7\r\n> 2006.285.18:29:24.06#abcon#{5=INTERFACE CLEAR} 2006.285.18:29:24.12#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:29:30.53$setupk4/"tpicd 2006.285.18:29:30.53$setupk4/echo=off 2006.285.18:29:30.53$setupk4/xlog=off 2006.285.18:29:30.53:!2006.285.18:31:32 2006.285.18:29:37.14#trakl#Source acquired 2006.285.18:29:38.14#flagr#flagr/antenna,acquired 2006.285.18:31:32.00:preob 2006.285.18:31:33.14/onsource/TRACKING 2006.285.18:31:33.14:!2006.285.18:31:42 2006.285.18:31:42.00:"tape 2006.285.18:31:42.00:"st=record 2006.285.18:31:42.00:data_valid=on 2006.285.18:31:42.00:midob 2006.285.18:31:42.14/onsource/TRACKING 2006.285.18:31:42.14/wx/15.32,1014.7,100 2006.285.18:31:42.30/cable/+6.5049E-03 2006.285.18:31:43.39/va/01,07,usb,yes,33,35 2006.285.18:31:43.39/va/02,06,usb,yes,33,33 2006.285.18:31:43.39/va/03,07,usb,yes,32,34 2006.285.18:31:43.39/va/04,06,usb,yes,34,35 2006.285.18:31:43.39/va/05,03,usb,yes,33,34 2006.285.18:31:43.39/va/06,04,usb,yes,30,29 2006.285.18:31:43.39/va/07,04,usb,yes,30,31 2006.285.18:31:43.39/va/08,03,usb,yes,31,38 2006.285.18:31:43.62/valo/01,524.99,yes,locked 2006.285.18:31:43.62/valo/02,534.99,yes,locked 2006.285.18:31:43.62/valo/03,564.99,yes,locked 2006.285.18:31:43.62/valo/04,624.99,yes,locked 2006.285.18:31:43.62/valo/05,734.99,yes,locked 2006.285.18:31:43.62/valo/06,814.99,yes,locked 2006.285.18:31:43.62/valo/07,864.99,yes,locked 2006.285.18:31:43.62/valo/08,884.99,yes,locked 2006.285.18:31:44.71/vb/01,04,usb,yes,30,28 2006.285.18:31:44.71/vb/02,05,usb,yes,29,29 2006.285.18:31:44.71/vb/03,04,usb,yes,30,33 2006.285.18:31:44.71/vb/04,05,usb,yes,30,29 2006.285.18:31:44.71/vb/05,04,usb,yes,26,29 2006.285.18:31:44.71/vb/06,03,usb,yes,38,33 2006.285.18:31:44.71/vb/07,04,usb,yes,30,30 2006.285.18:31:44.71/vb/08,04,usb,yes,28,31 2006.285.18:31:44.94/vblo/01,629.99,yes,locked 2006.285.18:31:44.94/vblo/02,634.99,yes,locked 2006.285.18:31:44.94/vblo/03,649.99,yes,locked 2006.285.18:31:44.94/vblo/04,679.99,yes,locked 2006.285.18:31:44.94/vblo/05,709.99,yes,locked 2006.285.18:31:44.94/vblo/06,719.99,yes,locked 2006.285.18:31:44.94/vblo/07,734.99,yes,locked 2006.285.18:31:44.94/vblo/08,744.99,yes,locked 2006.285.18:31:45.09/vabw/8 2006.285.18:31:45.24/vbbw/8 2006.285.18:31:45.33/xfe/off,on,12.0 2006.285.18:31:45.70/ifatt/23,28,28,28 2006.285.18:31:46.07/fmout-gps/S +2.64E-07 2006.285.18:31:46.09:!2006.285.18:32:42 2006.285.18:32:42.01:data_valid=off 2006.285.18:32:42.01:"et 2006.285.18:32:42.01:!+3s 2006.285.18:32:45.02:"tape 2006.285.18:32:45.02:postob 2006.285.18:32:45.15/cable/+6.5059E-03 2006.285.18:32:45.15/wx/15.32,1014.7,100 2006.285.18:32:45.21/fmout-gps/S +2.59E-07 2006.285.18:32:45.21:scan_name=285-1834,jd0610,100 2006.285.18:32:45.21:source=0528+134,053056.42,133155.1,2000.0,cw 2006.285.18:32:46.14#flagr#flagr/antenna,new-source 2006.285.18:32:46.14:checkk5 2006.285.18:32:47.00/chk_autoobs//k5ts1/ autoobs is running! 2006.285.18:32:47.48/chk_autoobs//k5ts2/ autoobs is running! 2006.285.18:32:47.85/chk_autoobs//k5ts3/ autoobs is running! 2006.285.18:32:48.28/chk_autoobs//k5ts4/ autoobs is running! 2006.285.18:32:48.72/chk_obsdata//k5ts1/T2851831??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.18:32:49.09/chk_obsdata//k5ts2/T2851831??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.18:32:49.72/chk_obsdata//k5ts3/T2851831??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.18:32:50.08/chk_obsdata//k5ts4/T2851831??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.18:32:51.19/k5log//k5ts1_log_newline 2006.285.18:32:51.91/k5log//k5ts2_log_newline 2006.285.18:32:52.77/k5log//k5ts3_log_newline 2006.285.18:32:53.75/k5log//k5ts4_log_newline 2006.285.18:32:53.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.18:32:53.77:setupk4=1 2006.285.18:32:53.77$setupk4/echo=on 2006.285.18:32:53.77$setupk4/pcalon 2006.285.18:32:53.77$pcalon/"no phase cal control is implemented here 2006.285.18:32:53.77$setupk4/"tpicd=stop 2006.285.18:32:53.77$setupk4/"rec=synch_on 2006.285.18:32:53.77$setupk4/"rec_mode=128 2006.285.18:32:53.77$setupk4/!* 2006.285.18:32:53.77$setupk4/recpk4 2006.285.18:32:53.77$recpk4/recpatch= 2006.285.18:32:53.78$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.18:32:53.78$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.18:32:53.78$setupk4/vck44 2006.285.18:32:53.78$vck44/valo=1,524.99 2006.285.18:32:53.78#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.18:32:53.78#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.18:32:53.78#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:53.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:32:53.78#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:32:53.78#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:32:53.78#ibcon#enter wrdev, iclass 19, count 0 2006.285.18:32:53.78#ibcon#first serial, iclass 19, count 0 2006.285.18:32:53.78#ibcon#enter sib2, iclass 19, count 0 2006.285.18:32:53.78#ibcon#flushed, iclass 19, count 0 2006.285.18:32:53.78#ibcon#about to write, iclass 19, count 0 2006.285.18:32:53.78#ibcon#wrote, iclass 19, count 0 2006.285.18:32:53.78#ibcon#about to read 3, iclass 19, count 0 2006.285.18:32:53.79#ibcon#read 3, iclass 19, count 0 2006.285.18:32:53.79#ibcon#about to read 4, iclass 19, count 0 2006.285.18:32:53.79#ibcon#read 4, iclass 19, count 0 2006.285.18:32:53.79#ibcon#about to read 5, iclass 19, count 0 2006.285.18:32:53.79#ibcon#read 5, iclass 19, count 0 2006.285.18:32:53.79#ibcon#about to read 6, iclass 19, count 0 2006.285.18:32:53.79#ibcon#read 6, iclass 19, count 0 2006.285.18:32:53.79#ibcon#end of sib2, iclass 19, count 0 2006.285.18:32:53.79#ibcon#*mode == 0, iclass 19, count 0 2006.285.18:32:53.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.18:32:53.79#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.18:32:53.79#ibcon#*before write, iclass 19, count 0 2006.285.18:32:53.79#ibcon#enter sib2, iclass 19, count 0 2006.285.18:32:53.79#ibcon#flushed, iclass 19, count 0 2006.285.18:32:53.79#ibcon#about to write, iclass 19, count 0 2006.285.18:32:53.79#ibcon#wrote, iclass 19, count 0 2006.285.18:32:53.79#ibcon#about to read 3, iclass 19, count 0 2006.285.18:32:53.84#ibcon#read 3, iclass 19, count 0 2006.285.18:32:53.84#ibcon#about to read 4, iclass 19, count 0 2006.285.18:32:53.84#ibcon#read 4, iclass 19, count 0 2006.285.18:32:53.84#ibcon#about to read 5, iclass 19, count 0 2006.285.18:32:53.84#ibcon#read 5, iclass 19, count 0 2006.285.18:32:53.84#ibcon#about to read 6, iclass 19, count 0 2006.285.18:32:53.84#ibcon#read 6, iclass 19, count 0 2006.285.18:32:53.84#ibcon#end of sib2, iclass 19, count 0 2006.285.18:32:53.84#ibcon#*after write, iclass 19, count 0 2006.285.18:32:53.84#ibcon#*before return 0, iclass 19, count 0 2006.285.18:32:53.84#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:32:53.84#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:32:53.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.18:32:53.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.18:32:53.84$vck44/va=1,7 2006.285.18:32:53.84#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.18:32:53.84#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.18:32:53.84#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:53.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:32:53.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:32:53.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:32:53.84#ibcon#enter wrdev, iclass 21, count 2 2006.285.18:32:53.84#ibcon#first serial, iclass 21, count 2 2006.285.18:32:53.84#ibcon#enter sib2, iclass 21, count 2 2006.285.18:32:53.84#ibcon#flushed, iclass 21, count 2 2006.285.18:32:53.84#ibcon#about to write, iclass 21, count 2 2006.285.18:32:53.84#ibcon#wrote, iclass 21, count 2 2006.285.18:32:53.84#ibcon#about to read 3, iclass 21, count 2 2006.285.18:32:53.86#ibcon#read 3, iclass 21, count 2 2006.285.18:32:53.86#ibcon#about to read 4, iclass 21, count 2 2006.285.18:32:53.86#ibcon#read 4, iclass 21, count 2 2006.285.18:32:53.86#ibcon#about to read 5, iclass 21, count 2 2006.285.18:32:53.86#ibcon#read 5, iclass 21, count 2 2006.285.18:32:53.86#ibcon#about to read 6, iclass 21, count 2 2006.285.18:32:53.86#ibcon#read 6, iclass 21, count 2 2006.285.18:32:53.86#ibcon#end of sib2, iclass 21, count 2 2006.285.18:32:53.86#ibcon#*mode == 0, iclass 21, count 2 2006.285.18:32:53.86#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.18:32:53.86#ibcon#[25=AT01-07\r\n] 2006.285.18:32:53.86#ibcon#*before write, iclass 21, count 2 2006.285.18:32:53.86#ibcon#enter sib2, iclass 21, count 2 2006.285.18:32:53.86#ibcon#flushed, iclass 21, count 2 2006.285.18:32:53.86#ibcon#about to write, iclass 21, count 2 2006.285.18:32:53.86#ibcon#wrote, iclass 21, count 2 2006.285.18:32:53.86#ibcon#about to read 3, iclass 21, count 2 2006.285.18:32:53.89#ibcon#read 3, iclass 21, count 2 2006.285.18:32:53.89#ibcon#about to read 4, iclass 21, count 2 2006.285.18:32:53.89#ibcon#read 4, iclass 21, count 2 2006.285.18:32:53.89#ibcon#about to read 5, iclass 21, count 2 2006.285.18:32:53.89#ibcon#read 5, iclass 21, count 2 2006.285.18:32:53.89#ibcon#about to read 6, iclass 21, count 2 2006.285.18:32:53.89#ibcon#read 6, iclass 21, count 2 2006.285.18:32:53.89#ibcon#end of sib2, iclass 21, count 2 2006.285.18:32:53.89#ibcon#*after write, iclass 21, count 2 2006.285.18:32:53.89#ibcon#*before return 0, iclass 21, count 2 2006.285.18:32:53.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:32:53.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:32:53.89#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.18:32:53.89#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:53.89#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:32:54.01#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:32:54.01#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:32:54.01#ibcon#enter wrdev, iclass 21, count 0 2006.285.18:32:54.01#ibcon#first serial, iclass 21, count 0 2006.285.18:32:54.01#ibcon#enter sib2, iclass 21, count 0 2006.285.18:32:54.01#ibcon#flushed, iclass 21, count 0 2006.285.18:32:54.01#ibcon#about to write, iclass 21, count 0 2006.285.18:32:54.01#ibcon#wrote, iclass 21, count 0 2006.285.18:32:54.01#ibcon#about to read 3, iclass 21, count 0 2006.285.18:32:54.03#ibcon#read 3, iclass 21, count 0 2006.285.18:32:54.03#ibcon#about to read 4, iclass 21, count 0 2006.285.18:32:54.03#ibcon#read 4, iclass 21, count 0 2006.285.18:32:54.03#ibcon#about to read 5, iclass 21, count 0 2006.285.18:32:54.03#ibcon#read 5, iclass 21, count 0 2006.285.18:32:54.03#ibcon#about to read 6, iclass 21, count 0 2006.285.18:32:54.03#ibcon#read 6, iclass 21, count 0 2006.285.18:32:54.03#ibcon#end of sib2, iclass 21, count 0 2006.285.18:32:54.03#ibcon#*mode == 0, iclass 21, count 0 2006.285.18:32:54.03#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.18:32:54.03#ibcon#[25=USB\r\n] 2006.285.18:32:54.03#ibcon#*before write, iclass 21, count 0 2006.285.18:32:54.03#ibcon#enter sib2, iclass 21, count 0 2006.285.18:32:54.03#ibcon#flushed, iclass 21, count 0 2006.285.18:32:54.03#ibcon#about to write, iclass 21, count 0 2006.285.18:32:54.03#ibcon#wrote, iclass 21, count 0 2006.285.18:32:54.03#ibcon#about to read 3, iclass 21, count 0 2006.285.18:32:54.06#ibcon#read 3, iclass 21, count 0 2006.285.18:32:54.06#ibcon#about to read 4, iclass 21, count 0 2006.285.18:32:54.06#ibcon#read 4, iclass 21, count 0 2006.285.18:32:54.06#ibcon#about to read 5, iclass 21, count 0 2006.285.18:32:54.06#ibcon#read 5, iclass 21, count 0 2006.285.18:32:54.06#ibcon#about to read 6, iclass 21, count 0 2006.285.18:32:54.06#ibcon#read 6, iclass 21, count 0 2006.285.18:32:54.06#ibcon#end of sib2, iclass 21, count 0 2006.285.18:32:54.06#ibcon#*after write, iclass 21, count 0 2006.285.18:32:54.06#ibcon#*before return 0, iclass 21, count 0 2006.285.18:32:54.06#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:32:54.06#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:32:54.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.18:32:54.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.18:32:54.06$vck44/valo=2,534.99 2006.285.18:32:54.06#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.18:32:54.06#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.18:32:54.06#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:54.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:32:54.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:32:54.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:32:54.06#ibcon#enter wrdev, iclass 23, count 0 2006.285.18:32:54.06#ibcon#first serial, iclass 23, count 0 2006.285.18:32:54.06#ibcon#enter sib2, iclass 23, count 0 2006.285.18:32:54.06#ibcon#flushed, iclass 23, count 0 2006.285.18:32:54.06#ibcon#about to write, iclass 23, count 0 2006.285.18:32:54.06#ibcon#wrote, iclass 23, count 0 2006.285.18:32:54.06#ibcon#about to read 3, iclass 23, count 0 2006.285.18:32:54.08#ibcon#read 3, iclass 23, count 0 2006.285.18:32:54.08#ibcon#about to read 4, iclass 23, count 0 2006.285.18:32:54.08#ibcon#read 4, iclass 23, count 0 2006.285.18:32:54.08#ibcon#about to read 5, iclass 23, count 0 2006.285.18:32:54.08#ibcon#read 5, iclass 23, count 0 2006.285.18:32:54.08#ibcon#about to read 6, iclass 23, count 0 2006.285.18:32:54.08#ibcon#read 6, iclass 23, count 0 2006.285.18:32:54.08#ibcon#end of sib2, iclass 23, count 0 2006.285.18:32:54.08#ibcon#*mode == 0, iclass 23, count 0 2006.285.18:32:54.08#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.18:32:54.08#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.18:32:54.08#ibcon#*before write, iclass 23, count 0 2006.285.18:32:54.08#ibcon#enter sib2, iclass 23, count 0 2006.285.18:32:54.08#ibcon#flushed, iclass 23, count 0 2006.285.18:32:54.08#ibcon#about to write, iclass 23, count 0 2006.285.18:32:54.08#ibcon#wrote, iclass 23, count 0 2006.285.18:32:54.08#ibcon#about to read 3, iclass 23, count 0 2006.285.18:32:54.12#ibcon#read 3, iclass 23, count 0 2006.285.18:32:54.12#ibcon#about to read 4, iclass 23, count 0 2006.285.18:32:54.12#ibcon#read 4, iclass 23, count 0 2006.285.18:32:54.12#ibcon#about to read 5, iclass 23, count 0 2006.285.18:32:54.12#ibcon#read 5, iclass 23, count 0 2006.285.18:32:54.12#ibcon#about to read 6, iclass 23, count 0 2006.285.18:32:54.12#ibcon#read 6, iclass 23, count 0 2006.285.18:32:54.12#ibcon#end of sib2, iclass 23, count 0 2006.285.18:32:54.12#ibcon#*after write, iclass 23, count 0 2006.285.18:32:54.12#ibcon#*before return 0, iclass 23, count 0 2006.285.18:32:54.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:32:54.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:32:54.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.18:32:54.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.18:32:54.12$vck44/va=2,6 2006.285.18:32:54.12#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.18:32:54.12#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.18:32:54.12#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:54.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:32:54.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:32:54.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:32:54.18#ibcon#enter wrdev, iclass 25, count 2 2006.285.18:32:54.18#ibcon#first serial, iclass 25, count 2 2006.285.18:32:54.18#ibcon#enter sib2, iclass 25, count 2 2006.285.18:32:54.18#ibcon#flushed, iclass 25, count 2 2006.285.18:32:54.18#ibcon#about to write, iclass 25, count 2 2006.285.18:32:54.18#ibcon#wrote, iclass 25, count 2 2006.285.18:32:54.18#ibcon#about to read 3, iclass 25, count 2 2006.285.18:32:54.20#ibcon#read 3, iclass 25, count 2 2006.285.18:32:54.20#ibcon#about to read 4, iclass 25, count 2 2006.285.18:32:54.20#ibcon#read 4, iclass 25, count 2 2006.285.18:32:54.20#ibcon#about to read 5, iclass 25, count 2 2006.285.18:32:54.20#ibcon#read 5, iclass 25, count 2 2006.285.18:32:54.20#ibcon#about to read 6, iclass 25, count 2 2006.285.18:32:54.20#ibcon#read 6, iclass 25, count 2 2006.285.18:32:54.20#ibcon#end of sib2, iclass 25, count 2 2006.285.18:32:54.20#ibcon#*mode == 0, iclass 25, count 2 2006.285.18:32:54.20#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.18:32:54.20#ibcon#[25=AT02-06\r\n] 2006.285.18:32:54.20#ibcon#*before write, iclass 25, count 2 2006.285.18:32:54.20#ibcon#enter sib2, iclass 25, count 2 2006.285.18:32:54.20#ibcon#flushed, iclass 25, count 2 2006.285.18:32:54.20#ibcon#about to write, iclass 25, count 2 2006.285.18:32:54.20#ibcon#wrote, iclass 25, count 2 2006.285.18:32:54.20#ibcon#about to read 3, iclass 25, count 2 2006.285.18:32:54.23#ibcon#read 3, iclass 25, count 2 2006.285.18:32:54.23#ibcon#about to read 4, iclass 25, count 2 2006.285.18:32:54.23#ibcon#read 4, iclass 25, count 2 2006.285.18:32:54.23#ibcon#about to read 5, iclass 25, count 2 2006.285.18:32:54.23#ibcon#read 5, iclass 25, count 2 2006.285.18:32:54.23#ibcon#about to read 6, iclass 25, count 2 2006.285.18:32:54.23#ibcon#read 6, iclass 25, count 2 2006.285.18:32:54.23#ibcon#end of sib2, iclass 25, count 2 2006.285.18:32:54.23#ibcon#*after write, iclass 25, count 2 2006.285.18:32:54.23#ibcon#*before return 0, iclass 25, count 2 2006.285.18:32:54.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:32:54.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:32:54.23#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.18:32:54.23#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:54.23#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:32:54.35#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:32:54.69#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:32:54.69#ibcon#enter wrdev, iclass 25, count 0 2006.285.18:32:54.69#ibcon#first serial, iclass 25, count 0 2006.285.18:32:54.69#ibcon#enter sib2, iclass 25, count 0 2006.285.18:32:54.69#ibcon#flushed, iclass 25, count 0 2006.285.18:32:54.69#ibcon#about to write, iclass 25, count 0 2006.285.18:32:54.70#ibcon#wrote, iclass 25, count 0 2006.285.18:32:54.70#ibcon#about to read 3, iclass 25, count 0 2006.285.18:32:54.71#ibcon#read 3, iclass 25, count 0 2006.285.18:32:54.71#ibcon#about to read 4, iclass 25, count 0 2006.285.18:32:54.71#ibcon#read 4, iclass 25, count 0 2006.285.18:32:54.71#ibcon#about to read 5, iclass 25, count 0 2006.285.18:32:54.71#ibcon#read 5, iclass 25, count 0 2006.285.18:32:54.71#ibcon#about to read 6, iclass 25, count 0 2006.285.18:32:54.71#ibcon#read 6, iclass 25, count 0 2006.285.18:32:54.71#ibcon#end of sib2, iclass 25, count 0 2006.285.18:32:54.71#ibcon#*mode == 0, iclass 25, count 0 2006.285.18:32:54.71#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.18:32:54.71#ibcon#[25=USB\r\n] 2006.285.18:32:54.71#ibcon#*before write, iclass 25, count 0 2006.285.18:32:54.71#ibcon#enter sib2, iclass 25, count 0 2006.285.18:32:54.71#ibcon#flushed, iclass 25, count 0 2006.285.18:32:54.71#ibcon#about to write, iclass 25, count 0 2006.285.18:32:54.71#ibcon#wrote, iclass 25, count 0 2006.285.18:32:54.71#ibcon#about to read 3, iclass 25, count 0 2006.285.18:32:54.74#ibcon#read 3, iclass 25, count 0 2006.285.18:32:54.74#ibcon#about to read 4, iclass 25, count 0 2006.285.18:32:54.74#ibcon#read 4, iclass 25, count 0 2006.285.18:32:54.74#ibcon#about to read 5, iclass 25, count 0 2006.285.18:32:54.74#ibcon#read 5, iclass 25, count 0 2006.285.18:32:54.74#ibcon#about to read 6, iclass 25, count 0 2006.285.18:32:54.74#ibcon#read 6, iclass 25, count 0 2006.285.18:32:54.74#ibcon#end of sib2, iclass 25, count 0 2006.285.18:32:54.74#ibcon#*after write, iclass 25, count 0 2006.285.18:32:54.74#ibcon#*before return 0, iclass 25, count 0 2006.285.18:32:54.74#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:32:54.74#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:32:54.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.18:32:54.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.18:32:54.74$vck44/valo=3,564.99 2006.285.18:32:54.74#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.18:32:54.74#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.18:32:54.74#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:54.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:32:54.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:32:54.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:32:54.74#ibcon#enter wrdev, iclass 27, count 0 2006.285.18:32:54.74#ibcon#first serial, iclass 27, count 0 2006.285.18:32:54.74#ibcon#enter sib2, iclass 27, count 0 2006.285.18:32:54.74#ibcon#flushed, iclass 27, count 0 2006.285.18:32:54.74#ibcon#about to write, iclass 27, count 0 2006.285.18:32:54.74#ibcon#wrote, iclass 27, count 0 2006.285.18:32:54.74#ibcon#about to read 3, iclass 27, count 0 2006.285.18:32:54.76#ibcon#read 3, iclass 27, count 0 2006.285.18:32:54.76#ibcon#about to read 4, iclass 27, count 0 2006.285.18:32:54.76#ibcon#read 4, iclass 27, count 0 2006.285.18:32:54.76#ibcon#about to read 5, iclass 27, count 0 2006.285.18:32:54.76#ibcon#read 5, iclass 27, count 0 2006.285.18:32:54.76#ibcon#about to read 6, iclass 27, count 0 2006.285.18:32:54.76#ibcon#read 6, iclass 27, count 0 2006.285.18:32:54.76#ibcon#end of sib2, iclass 27, count 0 2006.285.18:32:54.76#ibcon#*mode == 0, iclass 27, count 0 2006.285.18:32:54.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.18:32:54.76#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.18:32:54.76#ibcon#*before write, iclass 27, count 0 2006.285.18:32:54.76#ibcon#enter sib2, iclass 27, count 0 2006.285.18:32:54.76#ibcon#flushed, iclass 27, count 0 2006.285.18:32:54.76#ibcon#about to write, iclass 27, count 0 2006.285.18:32:54.76#ibcon#wrote, iclass 27, count 0 2006.285.18:32:54.76#ibcon#about to read 3, iclass 27, count 0 2006.285.18:32:54.80#ibcon#read 3, iclass 27, count 0 2006.285.18:32:54.80#ibcon#about to read 4, iclass 27, count 0 2006.285.18:32:54.80#ibcon#read 4, iclass 27, count 0 2006.285.18:32:54.80#ibcon#about to read 5, iclass 27, count 0 2006.285.18:32:54.80#ibcon#read 5, iclass 27, count 0 2006.285.18:32:54.80#ibcon#about to read 6, iclass 27, count 0 2006.285.18:32:54.80#ibcon#read 6, iclass 27, count 0 2006.285.18:32:54.80#ibcon#end of sib2, iclass 27, count 0 2006.285.18:32:54.80#ibcon#*after write, iclass 27, count 0 2006.285.18:32:54.80#ibcon#*before return 0, iclass 27, count 0 2006.285.18:32:54.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:32:54.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:32:54.80#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.18:32:54.80#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.18:32:54.80$vck44/va=3,7 2006.285.18:32:54.80#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.18:32:54.80#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.18:32:54.80#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:54.80#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:32:54.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:32:54.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:32:54.86#ibcon#enter wrdev, iclass 29, count 2 2006.285.18:32:54.86#ibcon#first serial, iclass 29, count 2 2006.285.18:32:54.86#ibcon#enter sib2, iclass 29, count 2 2006.285.18:32:54.86#ibcon#flushed, iclass 29, count 2 2006.285.18:32:54.86#ibcon#about to write, iclass 29, count 2 2006.285.18:32:54.86#ibcon#wrote, iclass 29, count 2 2006.285.18:32:54.86#ibcon#about to read 3, iclass 29, count 2 2006.285.18:32:54.88#ibcon#read 3, iclass 29, count 2 2006.285.18:32:54.88#ibcon#about to read 4, iclass 29, count 2 2006.285.18:32:54.88#ibcon#read 4, iclass 29, count 2 2006.285.18:32:54.88#ibcon#about to read 5, iclass 29, count 2 2006.285.18:32:54.88#ibcon#read 5, iclass 29, count 2 2006.285.18:32:54.88#ibcon#about to read 6, iclass 29, count 2 2006.285.18:32:54.88#ibcon#read 6, iclass 29, count 2 2006.285.18:32:54.88#ibcon#end of sib2, iclass 29, count 2 2006.285.18:32:54.88#ibcon#*mode == 0, iclass 29, count 2 2006.285.18:32:54.88#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.18:32:54.88#ibcon#[25=AT03-07\r\n] 2006.285.18:32:54.88#ibcon#*before write, iclass 29, count 2 2006.285.18:32:54.88#ibcon#enter sib2, iclass 29, count 2 2006.285.18:32:54.88#ibcon#flushed, iclass 29, count 2 2006.285.18:32:54.88#ibcon#about to write, iclass 29, count 2 2006.285.18:32:54.88#ibcon#wrote, iclass 29, count 2 2006.285.18:32:54.88#ibcon#about to read 3, iclass 29, count 2 2006.285.18:32:54.91#ibcon#read 3, iclass 29, count 2 2006.285.18:32:54.91#ibcon#about to read 4, iclass 29, count 2 2006.285.18:32:54.91#ibcon#read 4, iclass 29, count 2 2006.285.18:32:54.91#ibcon#about to read 5, iclass 29, count 2 2006.285.18:32:54.91#ibcon#read 5, iclass 29, count 2 2006.285.18:32:54.91#ibcon#about to read 6, iclass 29, count 2 2006.285.18:32:54.91#ibcon#read 6, iclass 29, count 2 2006.285.18:32:54.91#ibcon#end of sib2, iclass 29, count 2 2006.285.18:32:54.91#ibcon#*after write, iclass 29, count 2 2006.285.18:32:54.91#ibcon#*before return 0, iclass 29, count 2 2006.285.18:32:54.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:32:54.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:32:54.91#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.18:32:54.91#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:54.91#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:32:55.03#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:32:55.30#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:32:55.30#ibcon#enter wrdev, iclass 29, count 0 2006.285.18:32:55.30#ibcon#first serial, iclass 29, count 0 2006.285.18:32:55.30#ibcon#enter sib2, iclass 29, count 0 2006.285.18:32:55.30#ibcon#flushed, iclass 29, count 0 2006.285.18:32:55.30#ibcon#about to write, iclass 29, count 0 2006.285.18:32:55.30#ibcon#wrote, iclass 29, count 0 2006.285.18:32:55.30#ibcon#about to read 3, iclass 29, count 0 2006.285.18:32:55.31#ibcon#read 3, iclass 29, count 0 2006.285.18:32:55.31#ibcon#about to read 4, iclass 29, count 0 2006.285.18:32:55.31#ibcon#read 4, iclass 29, count 0 2006.285.18:32:55.31#ibcon#about to read 5, iclass 29, count 0 2006.285.18:32:55.31#ibcon#read 5, iclass 29, count 0 2006.285.18:32:55.31#ibcon#about to read 6, iclass 29, count 0 2006.285.18:32:55.31#ibcon#read 6, iclass 29, count 0 2006.285.18:32:55.31#ibcon#end of sib2, iclass 29, count 0 2006.285.18:32:55.31#ibcon#*mode == 0, iclass 29, count 0 2006.285.18:32:55.31#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.18:32:55.31#ibcon#[25=USB\r\n] 2006.285.18:32:55.31#ibcon#*before write, iclass 29, count 0 2006.285.18:32:55.31#ibcon#enter sib2, iclass 29, count 0 2006.285.18:32:55.31#ibcon#flushed, iclass 29, count 0 2006.285.18:32:55.31#ibcon#about to write, iclass 29, count 0 2006.285.18:32:55.31#ibcon#wrote, iclass 29, count 0 2006.285.18:32:55.31#ibcon#about to read 3, iclass 29, count 0 2006.285.18:32:55.34#ibcon#read 3, iclass 29, count 0 2006.285.18:32:55.34#ibcon#about to read 4, iclass 29, count 0 2006.285.18:32:55.34#ibcon#read 4, iclass 29, count 0 2006.285.18:32:55.34#ibcon#about to read 5, iclass 29, count 0 2006.285.18:32:55.34#ibcon#read 5, iclass 29, count 0 2006.285.18:32:55.34#ibcon#about to read 6, iclass 29, count 0 2006.285.18:32:55.34#ibcon#read 6, iclass 29, count 0 2006.285.18:32:55.34#ibcon#end of sib2, iclass 29, count 0 2006.285.18:32:55.34#ibcon#*after write, iclass 29, count 0 2006.285.18:32:55.34#ibcon#*before return 0, iclass 29, count 0 2006.285.18:32:55.34#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:32:55.34#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:32:55.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.18:32:55.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.18:32:55.34$vck44/valo=4,624.99 2006.285.18:32:55.34#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.18:32:55.34#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.18:32:55.34#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:55.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:32:55.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:32:55.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:32:55.34#ibcon#enter wrdev, iclass 31, count 0 2006.285.18:32:55.34#ibcon#first serial, iclass 31, count 0 2006.285.18:32:55.34#ibcon#enter sib2, iclass 31, count 0 2006.285.18:32:55.34#ibcon#flushed, iclass 31, count 0 2006.285.18:32:55.34#ibcon#about to write, iclass 31, count 0 2006.285.18:32:55.34#ibcon#wrote, iclass 31, count 0 2006.285.18:32:55.34#ibcon#about to read 3, iclass 31, count 0 2006.285.18:32:55.36#ibcon#read 3, iclass 31, count 0 2006.285.18:32:55.36#ibcon#about to read 4, iclass 31, count 0 2006.285.18:32:55.36#ibcon#read 4, iclass 31, count 0 2006.285.18:32:55.36#ibcon#about to read 5, iclass 31, count 0 2006.285.18:32:55.36#ibcon#read 5, iclass 31, count 0 2006.285.18:32:55.36#ibcon#about to read 6, iclass 31, count 0 2006.285.18:32:55.36#ibcon#read 6, iclass 31, count 0 2006.285.18:32:55.36#ibcon#end of sib2, iclass 31, count 0 2006.285.18:32:55.36#ibcon#*mode == 0, iclass 31, count 0 2006.285.18:32:55.36#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.18:32:55.36#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.18:32:55.36#ibcon#*before write, iclass 31, count 0 2006.285.18:32:55.36#ibcon#enter sib2, iclass 31, count 0 2006.285.18:32:55.36#ibcon#flushed, iclass 31, count 0 2006.285.18:32:55.36#ibcon#about to write, iclass 31, count 0 2006.285.18:32:55.36#ibcon#wrote, iclass 31, count 0 2006.285.18:32:55.36#ibcon#about to read 3, iclass 31, count 0 2006.285.18:32:55.40#ibcon#read 3, iclass 31, count 0 2006.285.18:32:55.40#ibcon#about to read 4, iclass 31, count 0 2006.285.18:32:55.40#ibcon#read 4, iclass 31, count 0 2006.285.18:32:55.40#ibcon#about to read 5, iclass 31, count 0 2006.285.18:32:55.40#ibcon#read 5, iclass 31, count 0 2006.285.18:32:55.40#ibcon#about to read 6, iclass 31, count 0 2006.285.18:32:55.40#ibcon#read 6, iclass 31, count 0 2006.285.18:32:55.40#ibcon#end of sib2, iclass 31, count 0 2006.285.18:32:55.40#ibcon#*after write, iclass 31, count 0 2006.285.18:32:55.40#ibcon#*before return 0, iclass 31, count 0 2006.285.18:32:55.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:32:55.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:32:55.40#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.18:32:55.40#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.18:32:55.40$vck44/va=4,6 2006.285.18:32:55.40#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.18:32:55.40#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.18:32:55.40#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:55.40#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:32:55.46#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:32:55.46#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:32:55.46#ibcon#enter wrdev, iclass 33, count 2 2006.285.18:32:55.46#ibcon#first serial, iclass 33, count 2 2006.285.18:32:55.46#ibcon#enter sib2, iclass 33, count 2 2006.285.18:32:55.46#ibcon#flushed, iclass 33, count 2 2006.285.18:32:55.46#ibcon#about to write, iclass 33, count 2 2006.285.18:32:55.46#ibcon#wrote, iclass 33, count 2 2006.285.18:32:55.46#ibcon#about to read 3, iclass 33, count 2 2006.285.18:32:55.48#ibcon#read 3, iclass 33, count 2 2006.285.18:32:55.48#ibcon#about to read 4, iclass 33, count 2 2006.285.18:32:55.48#ibcon#read 4, iclass 33, count 2 2006.285.18:32:55.48#ibcon#about to read 5, iclass 33, count 2 2006.285.18:32:55.48#ibcon#read 5, iclass 33, count 2 2006.285.18:32:55.48#ibcon#about to read 6, iclass 33, count 2 2006.285.18:32:55.48#ibcon#read 6, iclass 33, count 2 2006.285.18:32:55.48#ibcon#end of sib2, iclass 33, count 2 2006.285.18:32:55.48#ibcon#*mode == 0, iclass 33, count 2 2006.285.18:32:55.48#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.18:32:55.48#ibcon#[25=AT04-06\r\n] 2006.285.18:32:55.48#ibcon#*before write, iclass 33, count 2 2006.285.18:32:55.48#ibcon#enter sib2, iclass 33, count 2 2006.285.18:32:55.48#ibcon#flushed, iclass 33, count 2 2006.285.18:32:55.48#ibcon#about to write, iclass 33, count 2 2006.285.18:32:55.48#ibcon#wrote, iclass 33, count 2 2006.285.18:32:55.48#ibcon#about to read 3, iclass 33, count 2 2006.285.18:32:55.51#ibcon#read 3, iclass 33, count 2 2006.285.18:32:55.51#ibcon#about to read 4, iclass 33, count 2 2006.285.18:32:55.51#ibcon#read 4, iclass 33, count 2 2006.285.18:32:55.51#ibcon#about to read 5, iclass 33, count 2 2006.285.18:32:55.51#ibcon#read 5, iclass 33, count 2 2006.285.18:32:55.51#ibcon#about to read 6, iclass 33, count 2 2006.285.18:32:55.51#ibcon#read 6, iclass 33, count 2 2006.285.18:32:55.51#ibcon#end of sib2, iclass 33, count 2 2006.285.18:32:55.51#ibcon#*after write, iclass 33, count 2 2006.285.18:32:55.51#ibcon#*before return 0, iclass 33, count 2 2006.285.18:32:55.51#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:32:55.51#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:32:55.51#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.18:32:55.51#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:55.51#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:32:55.63#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:32:55.63#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:32:55.63#ibcon#enter wrdev, iclass 33, count 0 2006.285.18:32:55.63#ibcon#first serial, iclass 33, count 0 2006.285.18:32:55.63#ibcon#enter sib2, iclass 33, count 0 2006.285.18:32:55.63#ibcon#flushed, iclass 33, count 0 2006.285.18:32:55.63#ibcon#about to write, iclass 33, count 0 2006.285.18:32:55.63#ibcon#wrote, iclass 33, count 0 2006.285.18:32:55.63#ibcon#about to read 3, iclass 33, count 0 2006.285.18:32:55.65#ibcon#read 3, iclass 33, count 0 2006.285.18:32:55.65#ibcon#about to read 4, iclass 33, count 0 2006.285.18:32:55.65#ibcon#read 4, iclass 33, count 0 2006.285.18:32:55.65#ibcon#about to read 5, iclass 33, count 0 2006.285.18:32:55.65#ibcon#read 5, iclass 33, count 0 2006.285.18:32:55.65#ibcon#about to read 6, iclass 33, count 0 2006.285.18:32:55.65#ibcon#read 6, iclass 33, count 0 2006.285.18:32:55.65#ibcon#end of sib2, iclass 33, count 0 2006.285.18:32:55.65#ibcon#*mode == 0, iclass 33, count 0 2006.285.18:32:55.65#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.18:32:55.65#ibcon#[25=USB\r\n] 2006.285.18:32:55.65#ibcon#*before write, iclass 33, count 0 2006.285.18:32:55.65#ibcon#enter sib2, iclass 33, count 0 2006.285.18:32:55.65#ibcon#flushed, iclass 33, count 0 2006.285.18:32:55.65#ibcon#about to write, iclass 33, count 0 2006.285.18:32:55.65#ibcon#wrote, iclass 33, count 0 2006.285.18:32:55.65#ibcon#about to read 3, iclass 33, count 0 2006.285.18:32:55.68#ibcon#read 3, iclass 33, count 0 2006.285.18:32:55.68#ibcon#about to read 4, iclass 33, count 0 2006.285.18:32:55.68#ibcon#read 4, iclass 33, count 0 2006.285.18:32:55.68#ibcon#about to read 5, iclass 33, count 0 2006.285.18:32:55.68#ibcon#read 5, iclass 33, count 0 2006.285.18:32:55.68#ibcon#about to read 6, iclass 33, count 0 2006.285.18:32:55.68#ibcon#read 6, iclass 33, count 0 2006.285.18:32:55.68#ibcon#end of sib2, iclass 33, count 0 2006.285.18:32:55.68#ibcon#*after write, iclass 33, count 0 2006.285.18:32:55.68#ibcon#*before return 0, iclass 33, count 0 2006.285.18:32:55.68#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:32:55.68#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:32:55.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.18:32:55.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.18:32:55.68$vck44/valo=5,734.99 2006.285.18:32:55.68#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.18:32:55.68#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.18:32:55.68#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:55.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:32:55.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:32:55.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:32:55.68#ibcon#enter wrdev, iclass 35, count 0 2006.285.18:32:55.68#ibcon#first serial, iclass 35, count 0 2006.285.18:32:55.68#ibcon#enter sib2, iclass 35, count 0 2006.285.18:32:55.68#ibcon#flushed, iclass 35, count 0 2006.285.18:32:55.68#ibcon#about to write, iclass 35, count 0 2006.285.18:32:55.68#ibcon#wrote, iclass 35, count 0 2006.285.18:32:55.68#ibcon#about to read 3, iclass 35, count 0 2006.285.18:32:55.70#ibcon#read 3, iclass 35, count 0 2006.285.18:32:55.70#ibcon#about to read 4, iclass 35, count 0 2006.285.18:32:55.70#ibcon#read 4, iclass 35, count 0 2006.285.18:32:55.70#ibcon#about to read 5, iclass 35, count 0 2006.285.18:32:55.70#ibcon#read 5, iclass 35, count 0 2006.285.18:32:55.70#ibcon#about to read 6, iclass 35, count 0 2006.285.18:32:55.70#ibcon#read 6, iclass 35, count 0 2006.285.18:32:55.70#ibcon#end of sib2, iclass 35, count 0 2006.285.18:32:55.70#ibcon#*mode == 0, iclass 35, count 0 2006.285.18:32:55.70#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.18:32:55.70#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.18:32:55.70#ibcon#*before write, iclass 35, count 0 2006.285.18:32:55.70#ibcon#enter sib2, iclass 35, count 0 2006.285.18:32:55.70#ibcon#flushed, iclass 35, count 0 2006.285.18:32:55.70#ibcon#about to write, iclass 35, count 0 2006.285.18:32:55.70#ibcon#wrote, iclass 35, count 0 2006.285.18:32:55.70#ibcon#about to read 3, iclass 35, count 0 2006.285.18:32:55.74#ibcon#read 3, iclass 35, count 0 2006.285.18:32:55.74#ibcon#about to read 4, iclass 35, count 0 2006.285.18:32:55.74#ibcon#read 4, iclass 35, count 0 2006.285.18:32:55.74#ibcon#about to read 5, iclass 35, count 0 2006.285.18:32:55.74#ibcon#read 5, iclass 35, count 0 2006.285.18:32:55.74#ibcon#about to read 6, iclass 35, count 0 2006.285.18:32:55.74#ibcon#read 6, iclass 35, count 0 2006.285.18:32:55.74#ibcon#end of sib2, iclass 35, count 0 2006.285.18:32:55.74#ibcon#*after write, iclass 35, count 0 2006.285.18:32:55.74#ibcon#*before return 0, iclass 35, count 0 2006.285.18:32:55.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:32:55.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:32:55.74#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.18:32:55.74#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.18:32:55.74$vck44/va=5,3 2006.285.18:32:55.74#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.18:32:55.74#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.18:32:55.74#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:55.74#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:32:55.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:32:55.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:32:55.80#ibcon#enter wrdev, iclass 37, count 2 2006.285.18:32:55.80#ibcon#first serial, iclass 37, count 2 2006.285.18:32:55.80#ibcon#enter sib2, iclass 37, count 2 2006.285.18:32:55.80#ibcon#flushed, iclass 37, count 2 2006.285.18:32:55.80#ibcon#about to write, iclass 37, count 2 2006.285.18:32:55.80#ibcon#wrote, iclass 37, count 2 2006.285.18:32:55.80#ibcon#about to read 3, iclass 37, count 2 2006.285.18:32:55.82#ibcon#read 3, iclass 37, count 2 2006.285.18:32:55.82#ibcon#about to read 4, iclass 37, count 2 2006.285.18:32:55.82#ibcon#read 4, iclass 37, count 2 2006.285.18:32:55.82#ibcon#about to read 5, iclass 37, count 2 2006.285.18:32:55.82#ibcon#read 5, iclass 37, count 2 2006.285.18:32:55.82#ibcon#about to read 6, iclass 37, count 2 2006.285.18:32:55.82#ibcon#read 6, iclass 37, count 2 2006.285.18:32:55.82#ibcon#end of sib2, iclass 37, count 2 2006.285.18:32:55.82#ibcon#*mode == 0, iclass 37, count 2 2006.285.18:32:55.82#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.18:32:55.82#ibcon#[25=AT05-03\r\n] 2006.285.18:32:55.82#ibcon#*before write, iclass 37, count 2 2006.285.18:32:55.82#ibcon#enter sib2, iclass 37, count 2 2006.285.18:32:55.82#ibcon#flushed, iclass 37, count 2 2006.285.18:32:55.82#ibcon#about to write, iclass 37, count 2 2006.285.18:32:55.82#ibcon#wrote, iclass 37, count 2 2006.285.18:32:55.82#ibcon#about to read 3, iclass 37, count 2 2006.285.18:32:55.85#ibcon#read 3, iclass 37, count 2 2006.285.18:32:55.85#ibcon#about to read 4, iclass 37, count 2 2006.285.18:32:55.85#ibcon#read 4, iclass 37, count 2 2006.285.18:32:55.85#ibcon#about to read 5, iclass 37, count 2 2006.285.18:32:55.85#ibcon#read 5, iclass 37, count 2 2006.285.18:32:55.85#ibcon#about to read 6, iclass 37, count 2 2006.285.18:32:55.85#ibcon#read 6, iclass 37, count 2 2006.285.18:32:55.85#ibcon#end of sib2, iclass 37, count 2 2006.285.18:32:55.85#ibcon#*after write, iclass 37, count 2 2006.285.18:32:55.85#ibcon#*before return 0, iclass 37, count 2 2006.285.18:32:55.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:32:55.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:32:55.85#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.18:32:55.85#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:55.85#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:32:55.97#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:32:55.97#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:32:55.97#ibcon#enter wrdev, iclass 37, count 0 2006.285.18:32:55.97#ibcon#first serial, iclass 37, count 0 2006.285.18:32:55.97#ibcon#enter sib2, iclass 37, count 0 2006.285.18:32:55.97#ibcon#flushed, iclass 37, count 0 2006.285.18:32:55.97#ibcon#about to write, iclass 37, count 0 2006.285.18:32:55.97#ibcon#wrote, iclass 37, count 0 2006.285.18:32:55.97#ibcon#about to read 3, iclass 37, count 0 2006.285.18:32:55.99#ibcon#read 3, iclass 37, count 0 2006.285.18:32:55.99#ibcon#about to read 4, iclass 37, count 0 2006.285.18:32:55.99#ibcon#read 4, iclass 37, count 0 2006.285.18:32:55.99#ibcon#about to read 5, iclass 37, count 0 2006.285.18:32:55.99#ibcon#read 5, iclass 37, count 0 2006.285.18:32:55.99#ibcon#about to read 6, iclass 37, count 0 2006.285.18:32:55.99#ibcon#read 6, iclass 37, count 0 2006.285.18:32:55.99#ibcon#end of sib2, iclass 37, count 0 2006.285.18:32:55.99#ibcon#*mode == 0, iclass 37, count 0 2006.285.18:32:55.99#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.18:32:55.99#ibcon#[25=USB\r\n] 2006.285.18:32:55.99#ibcon#*before write, iclass 37, count 0 2006.285.18:32:55.99#ibcon#enter sib2, iclass 37, count 0 2006.285.18:32:55.99#ibcon#flushed, iclass 37, count 0 2006.285.18:32:55.99#ibcon#about to write, iclass 37, count 0 2006.285.18:32:55.99#ibcon#wrote, iclass 37, count 0 2006.285.18:32:55.99#ibcon#about to read 3, iclass 37, count 0 2006.285.18:32:56.02#ibcon#read 3, iclass 37, count 0 2006.285.18:32:56.02#ibcon#about to read 4, iclass 37, count 0 2006.285.18:32:56.02#ibcon#read 4, iclass 37, count 0 2006.285.18:32:56.02#ibcon#about to read 5, iclass 37, count 0 2006.285.18:32:56.02#ibcon#read 5, iclass 37, count 0 2006.285.18:32:56.02#ibcon#about to read 6, iclass 37, count 0 2006.285.18:32:56.02#ibcon#read 6, iclass 37, count 0 2006.285.18:32:56.02#ibcon#end of sib2, iclass 37, count 0 2006.285.18:32:56.02#ibcon#*after write, iclass 37, count 0 2006.285.18:32:56.02#ibcon#*before return 0, iclass 37, count 0 2006.285.18:32:56.02#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:32:56.02#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:32:56.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.18:32:56.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.18:32:56.02$vck44/valo=6,814.99 2006.285.18:32:56.02#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.18:32:56.02#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.18:32:56.02#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:56.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:32:56.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:32:56.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:32:56.02#ibcon#enter wrdev, iclass 39, count 0 2006.285.18:32:56.02#ibcon#first serial, iclass 39, count 0 2006.285.18:32:56.02#ibcon#enter sib2, iclass 39, count 0 2006.285.18:32:56.02#ibcon#flushed, iclass 39, count 0 2006.285.18:32:56.02#ibcon#about to write, iclass 39, count 0 2006.285.18:32:56.02#ibcon#wrote, iclass 39, count 0 2006.285.18:32:56.02#ibcon#about to read 3, iclass 39, count 0 2006.285.18:32:56.04#ibcon#read 3, iclass 39, count 0 2006.285.18:32:56.04#ibcon#about to read 4, iclass 39, count 0 2006.285.18:32:56.04#ibcon#read 4, iclass 39, count 0 2006.285.18:32:56.04#ibcon#about to read 5, iclass 39, count 0 2006.285.18:32:56.04#ibcon#read 5, iclass 39, count 0 2006.285.18:32:56.04#ibcon#about to read 6, iclass 39, count 0 2006.285.18:32:56.04#ibcon#read 6, iclass 39, count 0 2006.285.18:32:56.04#ibcon#end of sib2, iclass 39, count 0 2006.285.18:32:56.04#ibcon#*mode == 0, iclass 39, count 0 2006.285.18:32:56.04#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.18:32:56.04#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.18:32:56.04#ibcon#*before write, iclass 39, count 0 2006.285.18:32:56.04#ibcon#enter sib2, iclass 39, count 0 2006.285.18:32:56.04#ibcon#flushed, iclass 39, count 0 2006.285.18:32:56.04#ibcon#about to write, iclass 39, count 0 2006.285.18:32:56.04#ibcon#wrote, iclass 39, count 0 2006.285.18:32:56.04#ibcon#about to read 3, iclass 39, count 0 2006.285.18:32:56.08#ibcon#read 3, iclass 39, count 0 2006.285.18:32:56.08#ibcon#about to read 4, iclass 39, count 0 2006.285.18:32:56.08#ibcon#read 4, iclass 39, count 0 2006.285.18:32:56.08#ibcon#about to read 5, iclass 39, count 0 2006.285.18:32:56.08#ibcon#read 5, iclass 39, count 0 2006.285.18:32:56.08#ibcon#about to read 6, iclass 39, count 0 2006.285.18:32:56.08#ibcon#read 6, iclass 39, count 0 2006.285.18:32:56.08#ibcon#end of sib2, iclass 39, count 0 2006.285.18:32:56.08#ibcon#*after write, iclass 39, count 0 2006.285.18:32:56.08#ibcon#*before return 0, iclass 39, count 0 2006.285.18:32:56.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:32:56.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:32:56.08#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.18:32:56.08#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.18:32:56.08$vck44/va=6,4 2006.285.18:32:56.08#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.18:32:56.08#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.18:32:56.08#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:56.08#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:32:56.14#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:32:56.14#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:32:56.14#ibcon#enter wrdev, iclass 3, count 2 2006.285.18:32:56.14#ibcon#first serial, iclass 3, count 2 2006.285.18:32:56.14#ibcon#enter sib2, iclass 3, count 2 2006.285.18:32:56.14#ibcon#flushed, iclass 3, count 2 2006.285.18:32:56.14#ibcon#about to write, iclass 3, count 2 2006.285.18:32:56.14#ibcon#wrote, iclass 3, count 2 2006.285.18:32:56.14#ibcon#about to read 3, iclass 3, count 2 2006.285.18:32:56.16#ibcon#read 3, iclass 3, count 2 2006.285.18:32:56.16#ibcon#about to read 4, iclass 3, count 2 2006.285.18:32:56.16#ibcon#read 4, iclass 3, count 2 2006.285.18:32:56.16#ibcon#about to read 5, iclass 3, count 2 2006.285.18:32:56.16#ibcon#read 5, iclass 3, count 2 2006.285.18:32:56.16#ibcon#about to read 6, iclass 3, count 2 2006.285.18:32:56.16#ibcon#read 6, iclass 3, count 2 2006.285.18:32:56.16#ibcon#end of sib2, iclass 3, count 2 2006.285.18:32:56.16#ibcon#*mode == 0, iclass 3, count 2 2006.285.18:32:56.16#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.18:32:56.16#ibcon#[25=AT06-04\r\n] 2006.285.18:32:56.16#ibcon#*before write, iclass 3, count 2 2006.285.18:32:56.16#ibcon#enter sib2, iclass 3, count 2 2006.285.18:32:56.16#ibcon#flushed, iclass 3, count 2 2006.285.18:32:56.16#ibcon#about to write, iclass 3, count 2 2006.285.18:32:56.16#ibcon#wrote, iclass 3, count 2 2006.285.18:32:56.16#ibcon#about to read 3, iclass 3, count 2 2006.285.18:32:56.19#ibcon#read 3, iclass 3, count 2 2006.285.18:32:56.19#ibcon#about to read 4, iclass 3, count 2 2006.285.18:32:56.19#ibcon#read 4, iclass 3, count 2 2006.285.18:32:56.19#ibcon#about to read 5, iclass 3, count 2 2006.285.18:32:56.19#ibcon#read 5, iclass 3, count 2 2006.285.18:32:56.19#ibcon#about to read 6, iclass 3, count 2 2006.285.18:32:56.19#ibcon#read 6, iclass 3, count 2 2006.285.18:32:56.19#ibcon#end of sib2, iclass 3, count 2 2006.285.18:32:56.19#ibcon#*after write, iclass 3, count 2 2006.285.18:32:56.19#ibcon#*before return 0, iclass 3, count 2 2006.285.18:32:56.19#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:32:56.19#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:32:56.19#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.18:32:56.19#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:56.19#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:32:56.31#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:32:56.31#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:32:56.31#ibcon#enter wrdev, iclass 3, count 0 2006.285.18:32:56.31#ibcon#first serial, iclass 3, count 0 2006.285.18:32:56.31#ibcon#enter sib2, iclass 3, count 0 2006.285.18:32:56.31#ibcon#flushed, iclass 3, count 0 2006.285.18:32:56.31#ibcon#about to write, iclass 3, count 0 2006.285.18:32:56.31#ibcon#wrote, iclass 3, count 0 2006.285.18:32:56.31#ibcon#about to read 3, iclass 3, count 0 2006.285.18:32:56.33#ibcon#read 3, iclass 3, count 0 2006.285.18:32:56.33#ibcon#about to read 4, iclass 3, count 0 2006.285.18:32:56.33#ibcon#read 4, iclass 3, count 0 2006.285.18:32:56.33#ibcon#about to read 5, iclass 3, count 0 2006.285.18:32:56.33#ibcon#read 5, iclass 3, count 0 2006.285.18:32:56.33#ibcon#about to read 6, iclass 3, count 0 2006.285.18:32:56.33#ibcon#read 6, iclass 3, count 0 2006.285.18:32:56.33#ibcon#end of sib2, iclass 3, count 0 2006.285.18:32:56.33#ibcon#*mode == 0, iclass 3, count 0 2006.285.18:32:56.33#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.18:32:56.33#ibcon#[25=USB\r\n] 2006.285.18:32:56.33#ibcon#*before write, iclass 3, count 0 2006.285.18:32:56.33#ibcon#enter sib2, iclass 3, count 0 2006.285.18:32:56.33#ibcon#flushed, iclass 3, count 0 2006.285.18:32:56.33#ibcon#about to write, iclass 3, count 0 2006.285.18:32:56.33#ibcon#wrote, iclass 3, count 0 2006.285.18:32:56.33#ibcon#about to read 3, iclass 3, count 0 2006.285.18:32:56.36#ibcon#read 3, iclass 3, count 0 2006.285.18:32:56.36#ibcon#about to read 4, iclass 3, count 0 2006.285.18:32:56.36#ibcon#read 4, iclass 3, count 0 2006.285.18:32:56.36#ibcon#about to read 5, iclass 3, count 0 2006.285.18:32:56.36#ibcon#read 5, iclass 3, count 0 2006.285.18:32:56.36#ibcon#about to read 6, iclass 3, count 0 2006.285.18:32:56.36#ibcon#read 6, iclass 3, count 0 2006.285.18:32:56.36#ibcon#end of sib2, iclass 3, count 0 2006.285.18:32:56.36#ibcon#*after write, iclass 3, count 0 2006.285.18:32:56.36#ibcon#*before return 0, iclass 3, count 0 2006.285.18:32:56.36#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:32:56.36#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:32:56.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.18:32:56.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.18:32:56.36$vck44/valo=7,864.99 2006.285.18:32:56.36#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.18:32:56.36#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.18:32:56.36#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:56.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:32:56.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:32:56.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:32:56.36#ibcon#enter wrdev, iclass 5, count 0 2006.285.18:32:56.36#ibcon#first serial, iclass 5, count 0 2006.285.18:32:56.36#ibcon#enter sib2, iclass 5, count 0 2006.285.18:32:56.36#ibcon#flushed, iclass 5, count 0 2006.285.18:32:56.36#ibcon#about to write, iclass 5, count 0 2006.285.18:32:56.36#ibcon#wrote, iclass 5, count 0 2006.285.18:32:56.36#ibcon#about to read 3, iclass 5, count 0 2006.285.18:32:56.38#ibcon#read 3, iclass 5, count 0 2006.285.18:32:56.47#ibcon#about to read 4, iclass 5, count 0 2006.285.18:32:56.47#ibcon#read 4, iclass 5, count 0 2006.285.18:32:56.47#ibcon#about to read 5, iclass 5, count 0 2006.285.18:32:56.47#ibcon#read 5, iclass 5, count 0 2006.285.18:32:56.47#ibcon#about to read 6, iclass 5, count 0 2006.285.18:32:56.47#ibcon#read 6, iclass 5, count 0 2006.285.18:32:56.47#ibcon#end of sib2, iclass 5, count 0 2006.285.18:32:56.47#ibcon#*mode == 0, iclass 5, count 0 2006.285.18:32:56.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.18:32:56.47#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.18:32:56.47#ibcon#*before write, iclass 5, count 0 2006.285.18:32:56.47#ibcon#enter sib2, iclass 5, count 0 2006.285.18:32:56.47#ibcon#flushed, iclass 5, count 0 2006.285.18:32:56.47#ibcon#about to write, iclass 5, count 0 2006.285.18:32:56.47#ibcon#wrote, iclass 5, count 0 2006.285.18:32:56.47#ibcon#about to read 3, iclass 5, count 0 2006.285.18:32:56.51#ibcon#read 3, iclass 5, count 0 2006.285.18:32:56.51#ibcon#about to read 4, iclass 5, count 0 2006.285.18:32:56.51#ibcon#read 4, iclass 5, count 0 2006.285.18:32:56.51#ibcon#about to read 5, iclass 5, count 0 2006.285.18:32:56.51#ibcon#read 5, iclass 5, count 0 2006.285.18:32:56.51#ibcon#about to read 6, iclass 5, count 0 2006.285.18:32:56.51#ibcon#read 6, iclass 5, count 0 2006.285.18:32:56.51#ibcon#end of sib2, iclass 5, count 0 2006.285.18:32:56.51#ibcon#*after write, iclass 5, count 0 2006.285.18:32:56.51#ibcon#*before return 0, iclass 5, count 0 2006.285.18:32:56.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:32:56.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:32:56.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.18:32:56.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.18:32:56.51$vck44/va=7,4 2006.285.18:32:56.51#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.18:32:56.51#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.18:32:56.51#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:56.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:32:56.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:32:56.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:32:56.51#ibcon#enter wrdev, iclass 7, count 2 2006.285.18:32:56.51#ibcon#first serial, iclass 7, count 2 2006.285.18:32:56.51#ibcon#enter sib2, iclass 7, count 2 2006.285.18:32:56.51#ibcon#flushed, iclass 7, count 2 2006.285.18:32:56.51#ibcon#about to write, iclass 7, count 2 2006.285.18:32:56.51#ibcon#wrote, iclass 7, count 2 2006.285.18:32:56.51#ibcon#about to read 3, iclass 7, count 2 2006.285.18:32:56.53#ibcon#read 3, iclass 7, count 2 2006.285.18:32:56.53#ibcon#about to read 4, iclass 7, count 2 2006.285.18:32:56.53#ibcon#read 4, iclass 7, count 2 2006.285.18:32:56.53#ibcon#about to read 5, iclass 7, count 2 2006.285.18:32:56.53#ibcon#read 5, iclass 7, count 2 2006.285.18:32:56.53#ibcon#about to read 6, iclass 7, count 2 2006.285.18:32:56.53#ibcon#read 6, iclass 7, count 2 2006.285.18:32:56.53#ibcon#end of sib2, iclass 7, count 2 2006.285.18:32:56.53#ibcon#*mode == 0, iclass 7, count 2 2006.285.18:32:56.53#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.18:32:56.53#ibcon#[25=AT07-04\r\n] 2006.285.18:32:56.53#ibcon#*before write, iclass 7, count 2 2006.285.18:32:56.53#ibcon#enter sib2, iclass 7, count 2 2006.285.18:32:56.53#ibcon#flushed, iclass 7, count 2 2006.285.18:32:56.53#ibcon#about to write, iclass 7, count 2 2006.285.18:32:56.53#ibcon#wrote, iclass 7, count 2 2006.285.18:32:56.53#ibcon#about to read 3, iclass 7, count 2 2006.285.18:32:56.56#ibcon#read 3, iclass 7, count 2 2006.285.18:32:56.56#ibcon#about to read 4, iclass 7, count 2 2006.285.18:32:56.56#ibcon#read 4, iclass 7, count 2 2006.285.18:32:56.56#ibcon#about to read 5, iclass 7, count 2 2006.285.18:32:56.56#ibcon#read 5, iclass 7, count 2 2006.285.18:32:56.56#ibcon#about to read 6, iclass 7, count 2 2006.285.18:32:56.56#ibcon#read 6, iclass 7, count 2 2006.285.18:32:56.56#ibcon#end of sib2, iclass 7, count 2 2006.285.18:32:56.56#ibcon#*after write, iclass 7, count 2 2006.285.18:32:56.56#ibcon#*before return 0, iclass 7, count 2 2006.285.18:32:56.56#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:32:56.56#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:32:56.56#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.18:32:56.56#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:56.56#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:32:56.68#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:32:56.68#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:32:56.68#ibcon#enter wrdev, iclass 7, count 0 2006.285.18:32:56.68#ibcon#first serial, iclass 7, count 0 2006.285.18:32:56.68#ibcon#enter sib2, iclass 7, count 0 2006.285.18:32:56.68#ibcon#flushed, iclass 7, count 0 2006.285.18:32:56.68#ibcon#about to write, iclass 7, count 0 2006.285.18:32:56.68#ibcon#wrote, iclass 7, count 0 2006.285.18:32:56.68#ibcon#about to read 3, iclass 7, count 0 2006.285.18:32:56.70#ibcon#read 3, iclass 7, count 0 2006.285.18:32:56.70#ibcon#about to read 4, iclass 7, count 0 2006.285.18:32:56.70#ibcon#read 4, iclass 7, count 0 2006.285.18:32:56.70#ibcon#about to read 5, iclass 7, count 0 2006.285.18:32:56.70#ibcon#read 5, iclass 7, count 0 2006.285.18:32:56.70#ibcon#about to read 6, iclass 7, count 0 2006.285.18:32:56.70#ibcon#read 6, iclass 7, count 0 2006.285.18:32:56.70#ibcon#end of sib2, iclass 7, count 0 2006.285.18:32:56.70#ibcon#*mode == 0, iclass 7, count 0 2006.285.18:32:56.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.18:32:56.70#ibcon#[25=USB\r\n] 2006.285.18:32:56.70#ibcon#*before write, iclass 7, count 0 2006.285.18:32:56.70#ibcon#enter sib2, iclass 7, count 0 2006.285.18:32:56.70#ibcon#flushed, iclass 7, count 0 2006.285.18:32:56.70#ibcon#about to write, iclass 7, count 0 2006.285.18:32:56.70#ibcon#wrote, iclass 7, count 0 2006.285.18:32:56.70#ibcon#about to read 3, iclass 7, count 0 2006.285.18:32:56.73#ibcon#read 3, iclass 7, count 0 2006.285.18:32:56.73#ibcon#about to read 4, iclass 7, count 0 2006.285.18:32:56.73#ibcon#read 4, iclass 7, count 0 2006.285.18:32:56.73#ibcon#about to read 5, iclass 7, count 0 2006.285.18:32:56.73#ibcon#read 5, iclass 7, count 0 2006.285.18:32:56.73#ibcon#about to read 6, iclass 7, count 0 2006.285.18:32:56.73#ibcon#read 6, iclass 7, count 0 2006.285.18:32:56.73#ibcon#end of sib2, iclass 7, count 0 2006.285.18:32:56.73#ibcon#*after write, iclass 7, count 0 2006.285.18:32:56.73#ibcon#*before return 0, iclass 7, count 0 2006.285.18:32:56.73#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:32:56.73#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:32:56.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.18:32:56.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.18:32:56.73$vck44/valo=8,884.99 2006.285.18:32:56.73#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.18:32:56.73#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.18:32:56.73#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:56.73#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:32:56.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:32:56.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:32:56.73#ibcon#enter wrdev, iclass 11, count 0 2006.285.18:32:56.73#ibcon#first serial, iclass 11, count 0 2006.285.18:32:56.73#ibcon#enter sib2, iclass 11, count 0 2006.285.18:32:56.73#ibcon#flushed, iclass 11, count 0 2006.285.18:32:56.73#ibcon#about to write, iclass 11, count 0 2006.285.18:32:56.73#ibcon#wrote, iclass 11, count 0 2006.285.18:32:56.73#ibcon#about to read 3, iclass 11, count 0 2006.285.18:32:56.75#ibcon#read 3, iclass 11, count 0 2006.285.18:32:56.75#ibcon#about to read 4, iclass 11, count 0 2006.285.18:32:56.75#ibcon#read 4, iclass 11, count 0 2006.285.18:32:56.75#ibcon#about to read 5, iclass 11, count 0 2006.285.18:32:56.75#ibcon#read 5, iclass 11, count 0 2006.285.18:32:56.75#ibcon#about to read 6, iclass 11, count 0 2006.285.18:32:56.75#ibcon#read 6, iclass 11, count 0 2006.285.18:32:56.75#ibcon#end of sib2, iclass 11, count 0 2006.285.18:32:56.75#ibcon#*mode == 0, iclass 11, count 0 2006.285.18:32:56.75#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.18:32:56.75#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.18:32:56.75#ibcon#*before write, iclass 11, count 0 2006.285.18:32:56.75#ibcon#enter sib2, iclass 11, count 0 2006.285.18:32:56.75#ibcon#flushed, iclass 11, count 0 2006.285.18:32:56.75#ibcon#about to write, iclass 11, count 0 2006.285.18:32:56.75#ibcon#wrote, iclass 11, count 0 2006.285.18:32:56.75#ibcon#about to read 3, iclass 11, count 0 2006.285.18:32:56.79#ibcon#read 3, iclass 11, count 0 2006.285.18:32:56.79#ibcon#about to read 4, iclass 11, count 0 2006.285.18:32:56.79#ibcon#read 4, iclass 11, count 0 2006.285.18:32:56.79#ibcon#about to read 5, iclass 11, count 0 2006.285.18:32:56.79#ibcon#read 5, iclass 11, count 0 2006.285.18:32:56.79#ibcon#about to read 6, iclass 11, count 0 2006.285.18:32:56.79#ibcon#read 6, iclass 11, count 0 2006.285.18:32:56.79#ibcon#end of sib2, iclass 11, count 0 2006.285.18:32:56.79#ibcon#*after write, iclass 11, count 0 2006.285.18:32:56.79#ibcon#*before return 0, iclass 11, count 0 2006.285.18:32:56.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:32:56.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:32:56.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.18:32:56.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.18:32:56.79$vck44/va=8,3 2006.285.18:32:56.79#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.18:32:56.79#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.18:32:56.79#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:56.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:32:56.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:32:56.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:32:56.85#ibcon#enter wrdev, iclass 13, count 2 2006.285.18:32:56.85#ibcon#first serial, iclass 13, count 2 2006.285.18:32:56.85#ibcon#enter sib2, iclass 13, count 2 2006.285.18:32:56.85#ibcon#flushed, iclass 13, count 2 2006.285.18:32:56.85#ibcon#about to write, iclass 13, count 2 2006.285.18:32:56.85#ibcon#wrote, iclass 13, count 2 2006.285.18:32:56.85#ibcon#about to read 3, iclass 13, count 2 2006.285.18:32:56.87#ibcon#read 3, iclass 13, count 2 2006.285.18:32:56.87#ibcon#about to read 4, iclass 13, count 2 2006.285.18:32:56.87#ibcon#read 4, iclass 13, count 2 2006.285.18:32:56.87#ibcon#about to read 5, iclass 13, count 2 2006.285.18:32:56.87#ibcon#read 5, iclass 13, count 2 2006.285.18:32:56.87#ibcon#about to read 6, iclass 13, count 2 2006.285.18:32:56.87#ibcon#read 6, iclass 13, count 2 2006.285.18:32:56.87#ibcon#end of sib2, iclass 13, count 2 2006.285.18:32:56.87#ibcon#*mode == 0, iclass 13, count 2 2006.285.18:32:56.87#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.18:32:56.87#ibcon#[25=AT08-03\r\n] 2006.285.18:32:56.87#ibcon#*before write, iclass 13, count 2 2006.285.18:32:56.87#ibcon#enter sib2, iclass 13, count 2 2006.285.18:32:56.87#ibcon#flushed, iclass 13, count 2 2006.285.18:32:56.87#ibcon#about to write, iclass 13, count 2 2006.285.18:32:56.87#ibcon#wrote, iclass 13, count 2 2006.285.18:32:56.87#ibcon#about to read 3, iclass 13, count 2 2006.285.18:32:56.90#ibcon#read 3, iclass 13, count 2 2006.285.18:32:56.90#ibcon#about to read 4, iclass 13, count 2 2006.285.18:32:56.90#ibcon#read 4, iclass 13, count 2 2006.285.18:32:56.90#ibcon#about to read 5, iclass 13, count 2 2006.285.18:32:56.90#ibcon#read 5, iclass 13, count 2 2006.285.18:32:56.90#ibcon#about to read 6, iclass 13, count 2 2006.285.18:32:56.90#ibcon#read 6, iclass 13, count 2 2006.285.18:32:56.90#ibcon#end of sib2, iclass 13, count 2 2006.285.18:32:56.90#ibcon#*after write, iclass 13, count 2 2006.285.18:32:56.90#ibcon#*before return 0, iclass 13, count 2 2006.285.18:32:56.90#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:32:56.90#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:32:56.90#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.18:32:56.90#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:56.90#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:32:57.02#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:32:57.02#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:32:57.02#ibcon#enter wrdev, iclass 13, count 0 2006.285.18:32:57.02#ibcon#first serial, iclass 13, count 0 2006.285.18:32:57.02#ibcon#enter sib2, iclass 13, count 0 2006.285.18:32:57.02#ibcon#flushed, iclass 13, count 0 2006.285.18:32:57.02#ibcon#about to write, iclass 13, count 0 2006.285.18:32:57.02#ibcon#wrote, iclass 13, count 0 2006.285.18:32:57.02#ibcon#about to read 3, iclass 13, count 0 2006.285.18:32:57.04#ibcon#read 3, iclass 13, count 0 2006.285.18:32:57.04#ibcon#about to read 4, iclass 13, count 0 2006.285.18:32:57.04#ibcon#read 4, iclass 13, count 0 2006.285.18:32:57.04#ibcon#about to read 5, iclass 13, count 0 2006.285.18:32:57.04#ibcon#read 5, iclass 13, count 0 2006.285.18:32:57.04#ibcon#about to read 6, iclass 13, count 0 2006.285.18:32:57.04#ibcon#read 6, iclass 13, count 0 2006.285.18:32:57.04#ibcon#end of sib2, iclass 13, count 0 2006.285.18:32:57.04#ibcon#*mode == 0, iclass 13, count 0 2006.285.18:32:57.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.18:32:57.04#ibcon#[25=USB\r\n] 2006.285.18:32:57.04#ibcon#*before write, iclass 13, count 0 2006.285.18:32:57.04#ibcon#enter sib2, iclass 13, count 0 2006.285.18:32:57.04#ibcon#flushed, iclass 13, count 0 2006.285.18:32:57.04#ibcon#about to write, iclass 13, count 0 2006.285.18:32:57.04#ibcon#wrote, iclass 13, count 0 2006.285.18:32:57.04#ibcon#about to read 3, iclass 13, count 0 2006.285.18:32:57.07#ibcon#read 3, iclass 13, count 0 2006.285.18:32:57.07#ibcon#about to read 4, iclass 13, count 0 2006.285.18:32:57.07#ibcon#read 4, iclass 13, count 0 2006.285.18:32:57.07#ibcon#about to read 5, iclass 13, count 0 2006.285.18:32:57.07#ibcon#read 5, iclass 13, count 0 2006.285.18:32:57.07#ibcon#about to read 6, iclass 13, count 0 2006.285.18:32:57.07#ibcon#read 6, iclass 13, count 0 2006.285.18:32:57.07#ibcon#end of sib2, iclass 13, count 0 2006.285.18:32:57.07#ibcon#*after write, iclass 13, count 0 2006.285.18:32:57.07#ibcon#*before return 0, iclass 13, count 0 2006.285.18:32:57.07#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:32:57.07#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:32:57.07#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.18:32:57.07#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.18:32:57.07$vck44/vblo=1,629.99 2006.285.18:32:57.07#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.18:32:57.07#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.18:32:57.07#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:57.07#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:32:57.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:32:57.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:32:57.07#ibcon#enter wrdev, iclass 15, count 0 2006.285.18:32:57.07#ibcon#first serial, iclass 15, count 0 2006.285.18:32:57.07#ibcon#enter sib2, iclass 15, count 0 2006.285.18:32:57.07#ibcon#flushed, iclass 15, count 0 2006.285.18:32:57.07#ibcon#about to write, iclass 15, count 0 2006.285.18:32:57.07#ibcon#wrote, iclass 15, count 0 2006.285.18:32:57.07#ibcon#about to read 3, iclass 15, count 0 2006.285.18:32:57.09#ibcon#read 3, iclass 15, count 0 2006.285.18:32:57.09#ibcon#about to read 4, iclass 15, count 0 2006.285.18:32:57.09#ibcon#read 4, iclass 15, count 0 2006.285.18:32:57.09#ibcon#about to read 5, iclass 15, count 0 2006.285.18:32:57.09#ibcon#read 5, iclass 15, count 0 2006.285.18:32:57.09#ibcon#about to read 6, iclass 15, count 0 2006.285.18:32:57.09#ibcon#read 6, iclass 15, count 0 2006.285.18:32:57.09#ibcon#end of sib2, iclass 15, count 0 2006.285.18:32:57.09#ibcon#*mode == 0, iclass 15, count 0 2006.285.18:32:57.09#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.18:32:57.09#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.18:32:57.09#ibcon#*before write, iclass 15, count 0 2006.285.18:32:57.09#ibcon#enter sib2, iclass 15, count 0 2006.285.18:32:57.09#ibcon#flushed, iclass 15, count 0 2006.285.18:32:57.09#ibcon#about to write, iclass 15, count 0 2006.285.18:32:57.09#ibcon#wrote, iclass 15, count 0 2006.285.18:32:57.09#ibcon#about to read 3, iclass 15, count 0 2006.285.18:32:57.13#ibcon#read 3, iclass 15, count 0 2006.285.18:32:57.13#ibcon#about to read 4, iclass 15, count 0 2006.285.18:32:57.13#ibcon#read 4, iclass 15, count 0 2006.285.18:32:57.13#ibcon#about to read 5, iclass 15, count 0 2006.285.18:32:57.13#ibcon#read 5, iclass 15, count 0 2006.285.18:32:57.13#ibcon#about to read 6, iclass 15, count 0 2006.285.18:32:57.13#ibcon#read 6, iclass 15, count 0 2006.285.18:32:57.13#ibcon#end of sib2, iclass 15, count 0 2006.285.18:32:57.13#ibcon#*after write, iclass 15, count 0 2006.285.18:32:57.13#ibcon#*before return 0, iclass 15, count 0 2006.285.18:32:57.13#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:32:57.13#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:32:57.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.18:32:57.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.18:32:57.13$vck44/vb=1,4 2006.285.18:32:57.13#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.18:32:57.13#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.18:32:57.13#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:57.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:32:57.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:32:57.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:32:57.13#ibcon#enter wrdev, iclass 17, count 2 2006.285.18:32:57.13#ibcon#first serial, iclass 17, count 2 2006.285.18:32:57.13#ibcon#enter sib2, iclass 17, count 2 2006.285.18:32:57.13#ibcon#flushed, iclass 17, count 2 2006.285.18:32:57.13#ibcon#about to write, iclass 17, count 2 2006.285.18:32:57.13#ibcon#wrote, iclass 17, count 2 2006.285.18:32:57.13#ibcon#about to read 3, iclass 17, count 2 2006.285.18:32:57.15#ibcon#read 3, iclass 17, count 2 2006.285.18:32:57.15#ibcon#about to read 4, iclass 17, count 2 2006.285.18:32:57.15#ibcon#read 4, iclass 17, count 2 2006.285.18:32:57.15#ibcon#about to read 5, iclass 17, count 2 2006.285.18:32:57.15#ibcon#read 5, iclass 17, count 2 2006.285.18:32:57.15#ibcon#about to read 6, iclass 17, count 2 2006.285.18:32:57.15#ibcon#read 6, iclass 17, count 2 2006.285.18:32:57.15#ibcon#end of sib2, iclass 17, count 2 2006.285.18:32:57.15#ibcon#*mode == 0, iclass 17, count 2 2006.285.18:32:57.15#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.18:32:57.15#ibcon#[27=AT01-04\r\n] 2006.285.18:32:57.15#ibcon#*before write, iclass 17, count 2 2006.285.18:32:57.15#ibcon#enter sib2, iclass 17, count 2 2006.285.18:32:57.15#ibcon#flushed, iclass 17, count 2 2006.285.18:32:57.15#ibcon#about to write, iclass 17, count 2 2006.285.18:32:57.15#ibcon#wrote, iclass 17, count 2 2006.285.18:32:57.15#ibcon#about to read 3, iclass 17, count 2 2006.285.18:32:57.18#ibcon#read 3, iclass 17, count 2 2006.285.18:32:57.18#ibcon#about to read 4, iclass 17, count 2 2006.285.18:32:57.18#ibcon#read 4, iclass 17, count 2 2006.285.18:32:57.18#ibcon#about to read 5, iclass 17, count 2 2006.285.18:32:57.18#ibcon#read 5, iclass 17, count 2 2006.285.18:32:57.18#ibcon#about to read 6, iclass 17, count 2 2006.285.18:32:57.18#ibcon#read 6, iclass 17, count 2 2006.285.18:32:57.18#ibcon#end of sib2, iclass 17, count 2 2006.285.18:32:57.18#ibcon#*after write, iclass 17, count 2 2006.285.18:32:57.18#ibcon#*before return 0, iclass 17, count 2 2006.285.18:32:57.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:32:57.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:32:57.18#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.18:32:57.18#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:57.18#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:32:57.30#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:32:57.30#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:32:57.30#ibcon#enter wrdev, iclass 17, count 0 2006.285.18:32:57.30#ibcon#first serial, iclass 17, count 0 2006.285.18:32:57.30#ibcon#enter sib2, iclass 17, count 0 2006.285.18:32:57.30#ibcon#flushed, iclass 17, count 0 2006.285.18:32:57.30#ibcon#about to write, iclass 17, count 0 2006.285.18:32:57.30#ibcon#wrote, iclass 17, count 0 2006.285.18:32:57.30#ibcon#about to read 3, iclass 17, count 0 2006.285.18:32:57.32#ibcon#read 3, iclass 17, count 0 2006.285.18:32:57.32#ibcon#about to read 4, iclass 17, count 0 2006.285.18:32:57.32#ibcon#read 4, iclass 17, count 0 2006.285.18:32:57.32#ibcon#about to read 5, iclass 17, count 0 2006.285.18:32:57.32#ibcon#read 5, iclass 17, count 0 2006.285.18:32:57.32#ibcon#about to read 6, iclass 17, count 0 2006.285.18:32:57.32#ibcon#read 6, iclass 17, count 0 2006.285.18:32:57.32#ibcon#end of sib2, iclass 17, count 0 2006.285.18:32:57.32#ibcon#*mode == 0, iclass 17, count 0 2006.285.18:32:57.32#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.18:32:57.32#ibcon#[27=USB\r\n] 2006.285.18:32:57.32#ibcon#*before write, iclass 17, count 0 2006.285.18:32:57.32#ibcon#enter sib2, iclass 17, count 0 2006.285.18:32:57.32#ibcon#flushed, iclass 17, count 0 2006.285.18:32:57.32#ibcon#about to write, iclass 17, count 0 2006.285.18:32:57.32#ibcon#wrote, iclass 17, count 0 2006.285.18:32:57.32#ibcon#about to read 3, iclass 17, count 0 2006.285.18:32:57.35#ibcon#read 3, iclass 17, count 0 2006.285.18:32:57.35#ibcon#about to read 4, iclass 17, count 0 2006.285.18:32:57.35#ibcon#read 4, iclass 17, count 0 2006.285.18:32:57.35#ibcon#about to read 5, iclass 17, count 0 2006.285.18:32:57.35#ibcon#read 5, iclass 17, count 0 2006.285.18:32:57.35#ibcon#about to read 6, iclass 17, count 0 2006.285.18:32:57.35#ibcon#read 6, iclass 17, count 0 2006.285.18:32:57.35#ibcon#end of sib2, iclass 17, count 0 2006.285.18:32:57.35#ibcon#*after write, iclass 17, count 0 2006.285.18:32:57.35#ibcon#*before return 0, iclass 17, count 0 2006.285.18:32:57.35#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:32:57.35#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:32:57.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.18:32:57.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.18:32:57.35$vck44/vblo=2,634.99 2006.285.18:32:57.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.18:32:57.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.18:32:57.35#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:57.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:32:57.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:32:57.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:32:57.35#ibcon#enter wrdev, iclass 19, count 0 2006.285.18:32:57.35#ibcon#first serial, iclass 19, count 0 2006.285.18:32:57.35#ibcon#enter sib2, iclass 19, count 0 2006.285.18:32:57.35#ibcon#flushed, iclass 19, count 0 2006.285.18:32:57.35#ibcon#about to write, iclass 19, count 0 2006.285.18:32:57.35#ibcon#wrote, iclass 19, count 0 2006.285.18:32:57.35#ibcon#about to read 3, iclass 19, count 0 2006.285.18:32:57.37#ibcon#read 3, iclass 19, count 0 2006.285.18:32:57.57#ibcon#about to read 4, iclass 19, count 0 2006.285.18:32:57.57#ibcon#read 4, iclass 19, count 0 2006.285.18:32:57.57#ibcon#about to read 5, iclass 19, count 0 2006.285.18:32:57.57#ibcon#read 5, iclass 19, count 0 2006.285.18:32:57.57#ibcon#about to read 6, iclass 19, count 0 2006.285.18:32:57.57#ibcon#read 6, iclass 19, count 0 2006.285.18:32:57.57#ibcon#end of sib2, iclass 19, count 0 2006.285.18:32:57.57#ibcon#*mode == 0, iclass 19, count 0 2006.285.18:32:57.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.18:32:57.57#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.18:32:57.57#ibcon#*before write, iclass 19, count 0 2006.285.18:32:57.57#ibcon#enter sib2, iclass 19, count 0 2006.285.18:32:57.57#ibcon#flushed, iclass 19, count 0 2006.285.18:32:57.57#ibcon#about to write, iclass 19, count 0 2006.285.18:32:57.57#ibcon#wrote, iclass 19, count 0 2006.285.18:32:57.57#ibcon#about to read 3, iclass 19, count 0 2006.285.18:32:57.61#ibcon#read 3, iclass 19, count 0 2006.285.18:32:57.61#ibcon#about to read 4, iclass 19, count 0 2006.285.18:32:57.61#ibcon#read 4, iclass 19, count 0 2006.285.18:32:57.61#ibcon#about to read 5, iclass 19, count 0 2006.285.18:32:57.61#ibcon#read 5, iclass 19, count 0 2006.285.18:32:57.61#ibcon#about to read 6, iclass 19, count 0 2006.285.18:32:57.61#ibcon#read 6, iclass 19, count 0 2006.285.18:32:57.61#ibcon#end of sib2, iclass 19, count 0 2006.285.18:32:57.61#ibcon#*after write, iclass 19, count 0 2006.285.18:32:57.61#ibcon#*before return 0, iclass 19, count 0 2006.285.18:32:57.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:32:57.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:32:57.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.18:32:57.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.18:32:57.61$vck44/vb=2,5 2006.285.18:32:57.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.18:32:57.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.18:32:57.61#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:57.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:32:57.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:32:57.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:32:57.61#ibcon#enter wrdev, iclass 21, count 2 2006.285.18:32:57.61#ibcon#first serial, iclass 21, count 2 2006.285.18:32:57.61#ibcon#enter sib2, iclass 21, count 2 2006.285.18:32:57.61#ibcon#flushed, iclass 21, count 2 2006.285.18:32:57.61#ibcon#about to write, iclass 21, count 2 2006.285.18:32:57.61#ibcon#wrote, iclass 21, count 2 2006.285.18:32:57.61#ibcon#about to read 3, iclass 21, count 2 2006.285.18:32:57.63#ibcon#read 3, iclass 21, count 2 2006.285.18:32:57.63#ibcon#about to read 4, iclass 21, count 2 2006.285.18:32:57.63#ibcon#read 4, iclass 21, count 2 2006.285.18:32:57.63#ibcon#about to read 5, iclass 21, count 2 2006.285.18:32:57.63#ibcon#read 5, iclass 21, count 2 2006.285.18:32:57.63#ibcon#about to read 6, iclass 21, count 2 2006.285.18:32:57.63#ibcon#read 6, iclass 21, count 2 2006.285.18:32:57.63#ibcon#end of sib2, iclass 21, count 2 2006.285.18:32:57.63#ibcon#*mode == 0, iclass 21, count 2 2006.285.18:32:57.63#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.18:32:57.63#ibcon#[27=AT02-05\r\n] 2006.285.18:32:57.63#ibcon#*before write, iclass 21, count 2 2006.285.18:32:57.63#ibcon#enter sib2, iclass 21, count 2 2006.285.18:32:57.63#ibcon#flushed, iclass 21, count 2 2006.285.18:32:57.63#ibcon#about to write, iclass 21, count 2 2006.285.18:32:57.63#ibcon#wrote, iclass 21, count 2 2006.285.18:32:57.63#ibcon#about to read 3, iclass 21, count 2 2006.285.18:32:57.66#ibcon#read 3, iclass 21, count 2 2006.285.18:32:57.66#ibcon#about to read 4, iclass 21, count 2 2006.285.18:32:57.66#ibcon#read 4, iclass 21, count 2 2006.285.18:32:57.66#ibcon#about to read 5, iclass 21, count 2 2006.285.18:32:57.66#ibcon#read 5, iclass 21, count 2 2006.285.18:32:57.66#ibcon#about to read 6, iclass 21, count 2 2006.285.18:32:57.66#ibcon#read 6, iclass 21, count 2 2006.285.18:32:57.66#ibcon#end of sib2, iclass 21, count 2 2006.285.18:32:57.66#ibcon#*after write, iclass 21, count 2 2006.285.18:32:57.66#ibcon#*before return 0, iclass 21, count 2 2006.285.18:32:57.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:32:57.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:32:57.66#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.18:32:57.66#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:57.66#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:32:57.78#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:32:57.78#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:32:57.78#ibcon#enter wrdev, iclass 21, count 0 2006.285.18:32:57.78#ibcon#first serial, iclass 21, count 0 2006.285.18:32:57.78#ibcon#enter sib2, iclass 21, count 0 2006.285.18:32:57.78#ibcon#flushed, iclass 21, count 0 2006.285.18:32:57.78#ibcon#about to write, iclass 21, count 0 2006.285.18:32:57.78#ibcon#wrote, iclass 21, count 0 2006.285.18:32:57.78#ibcon#about to read 3, iclass 21, count 0 2006.285.18:32:57.80#ibcon#read 3, iclass 21, count 0 2006.285.18:32:57.80#ibcon#about to read 4, iclass 21, count 0 2006.285.18:32:57.80#ibcon#read 4, iclass 21, count 0 2006.285.18:32:57.80#ibcon#about to read 5, iclass 21, count 0 2006.285.18:32:57.80#ibcon#read 5, iclass 21, count 0 2006.285.18:32:57.80#ibcon#about to read 6, iclass 21, count 0 2006.285.18:32:57.80#ibcon#read 6, iclass 21, count 0 2006.285.18:32:57.80#ibcon#end of sib2, iclass 21, count 0 2006.285.18:32:57.80#ibcon#*mode == 0, iclass 21, count 0 2006.285.18:32:57.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.18:32:57.80#ibcon#[27=USB\r\n] 2006.285.18:32:57.80#ibcon#*before write, iclass 21, count 0 2006.285.18:32:57.80#ibcon#enter sib2, iclass 21, count 0 2006.285.18:32:57.80#ibcon#flushed, iclass 21, count 0 2006.285.18:32:57.80#ibcon#about to write, iclass 21, count 0 2006.285.18:32:57.80#ibcon#wrote, iclass 21, count 0 2006.285.18:32:57.80#ibcon#about to read 3, iclass 21, count 0 2006.285.18:32:57.83#ibcon#read 3, iclass 21, count 0 2006.285.18:32:57.83#ibcon#about to read 4, iclass 21, count 0 2006.285.18:32:57.83#ibcon#read 4, iclass 21, count 0 2006.285.18:32:57.83#ibcon#about to read 5, iclass 21, count 0 2006.285.18:32:57.83#ibcon#read 5, iclass 21, count 0 2006.285.18:32:57.83#ibcon#about to read 6, iclass 21, count 0 2006.285.18:32:57.83#ibcon#read 6, iclass 21, count 0 2006.285.18:32:57.83#ibcon#end of sib2, iclass 21, count 0 2006.285.18:32:57.83#ibcon#*after write, iclass 21, count 0 2006.285.18:32:57.83#ibcon#*before return 0, iclass 21, count 0 2006.285.18:32:57.83#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:32:57.83#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:32:57.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.18:32:57.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.18:32:57.83$vck44/vblo=3,649.99 2006.285.18:32:57.83#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.18:32:57.83#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.18:32:57.83#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:57.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:32:57.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:32:57.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:32:57.83#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:32:57.83#ibcon#first serial, iclass 24, count 0 2006.285.18:32:57.83#ibcon#enter sib2, iclass 24, count 0 2006.285.18:32:57.83#ibcon#flushed, iclass 24, count 0 2006.285.18:32:57.83#ibcon#about to write, iclass 24, count 0 2006.285.18:32:57.83#ibcon#wrote, iclass 24, count 0 2006.285.18:32:57.83#ibcon#about to read 3, iclass 24, count 0 2006.285.18:32:57.85#ibcon#read 3, iclass 24, count 0 2006.285.18:32:57.85#ibcon#about to read 4, iclass 24, count 0 2006.285.18:32:57.85#ibcon#read 4, iclass 24, count 0 2006.285.18:32:57.85#ibcon#about to read 5, iclass 24, count 0 2006.285.18:32:57.85#ibcon#read 5, iclass 24, count 0 2006.285.18:32:57.85#ibcon#about to read 6, iclass 24, count 0 2006.285.18:32:57.85#ibcon#read 6, iclass 24, count 0 2006.285.18:32:57.85#ibcon#end of sib2, iclass 24, count 0 2006.285.18:32:57.85#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:32:57.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:32:57.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.18:32:57.85#ibcon#*before write, iclass 24, count 0 2006.285.18:32:57.85#ibcon#enter sib2, iclass 24, count 0 2006.285.18:32:57.85#ibcon#flushed, iclass 24, count 0 2006.285.18:32:57.85#ibcon#about to write, iclass 24, count 0 2006.285.18:32:57.85#ibcon#wrote, iclass 24, count 0 2006.285.18:32:57.85#ibcon#about to read 3, iclass 24, count 0 2006.285.18:32:57.86#abcon#<5=/00 0.2 0.6 15.321001014.7\r\n> 2006.285.18:32:57.88#abcon#{5=INTERFACE CLEAR} 2006.285.18:32:57.89#ibcon#read 3, iclass 24, count 0 2006.285.18:32:57.89#ibcon#about to read 4, iclass 24, count 0 2006.285.18:32:57.89#ibcon#read 4, iclass 24, count 0 2006.285.18:32:57.89#ibcon#about to read 5, iclass 24, count 0 2006.285.18:32:57.89#ibcon#read 5, iclass 24, count 0 2006.285.18:32:57.89#ibcon#about to read 6, iclass 24, count 0 2006.285.18:32:57.89#ibcon#read 6, iclass 24, count 0 2006.285.18:32:57.89#ibcon#end of sib2, iclass 24, count 0 2006.285.18:32:57.89#ibcon#*after write, iclass 24, count 0 2006.285.18:32:57.89#ibcon#*before return 0, iclass 24, count 0 2006.285.18:32:57.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:32:57.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:32:57.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:32:57.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:32:57.89$vck44/vb=3,4 2006.285.18:32:57.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.18:32:57.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.18:32:57.89#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:57.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:32:57.94#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:32:57.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:32:57.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:32:57.95#ibcon#enter wrdev, iclass 28, count 2 2006.285.18:32:57.95#ibcon#first serial, iclass 28, count 2 2006.285.18:32:57.95#ibcon#enter sib2, iclass 28, count 2 2006.285.18:32:57.95#ibcon#flushed, iclass 28, count 2 2006.285.18:32:57.95#ibcon#about to write, iclass 28, count 2 2006.285.18:32:57.95#ibcon#wrote, iclass 28, count 2 2006.285.18:32:57.95#ibcon#about to read 3, iclass 28, count 2 2006.285.18:32:57.97#ibcon#read 3, iclass 28, count 2 2006.285.18:32:57.97#ibcon#about to read 4, iclass 28, count 2 2006.285.18:32:57.97#ibcon#read 4, iclass 28, count 2 2006.285.18:32:57.97#ibcon#about to read 5, iclass 28, count 2 2006.285.18:32:57.97#ibcon#read 5, iclass 28, count 2 2006.285.18:32:57.97#ibcon#about to read 6, iclass 28, count 2 2006.285.18:32:57.97#ibcon#read 6, iclass 28, count 2 2006.285.18:32:57.97#ibcon#end of sib2, iclass 28, count 2 2006.285.18:32:57.97#ibcon#*mode == 0, iclass 28, count 2 2006.285.18:32:57.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.18:32:57.97#ibcon#[27=AT03-04\r\n] 2006.285.18:32:57.97#ibcon#*before write, iclass 28, count 2 2006.285.18:32:57.97#ibcon#enter sib2, iclass 28, count 2 2006.285.18:32:57.97#ibcon#flushed, iclass 28, count 2 2006.285.18:32:57.97#ibcon#about to write, iclass 28, count 2 2006.285.18:32:57.97#ibcon#wrote, iclass 28, count 2 2006.285.18:32:57.97#ibcon#about to read 3, iclass 28, count 2 2006.285.18:32:58.00#ibcon#read 3, iclass 28, count 2 2006.285.18:32:58.00#ibcon#about to read 4, iclass 28, count 2 2006.285.18:32:58.00#ibcon#read 4, iclass 28, count 2 2006.285.18:32:58.00#ibcon#about to read 5, iclass 28, count 2 2006.285.18:32:58.00#ibcon#read 5, iclass 28, count 2 2006.285.18:32:58.00#ibcon#about to read 6, iclass 28, count 2 2006.285.18:32:58.00#ibcon#read 6, iclass 28, count 2 2006.285.18:32:58.00#ibcon#end of sib2, iclass 28, count 2 2006.285.18:32:58.00#ibcon#*after write, iclass 28, count 2 2006.285.18:32:58.00#ibcon#*before return 0, iclass 28, count 2 2006.285.18:32:58.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:32:58.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:32:58.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.18:32:58.00#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:58.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:32:58.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:32:58.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:32:58.12#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:32:58.12#ibcon#first serial, iclass 28, count 0 2006.285.18:32:58.12#ibcon#enter sib2, iclass 28, count 0 2006.285.18:32:58.12#ibcon#flushed, iclass 28, count 0 2006.285.18:32:58.12#ibcon#about to write, iclass 28, count 0 2006.285.18:32:58.12#ibcon#wrote, iclass 28, count 0 2006.285.18:32:58.12#ibcon#about to read 3, iclass 28, count 0 2006.285.18:32:58.14#ibcon#read 3, iclass 28, count 0 2006.285.18:32:58.14#ibcon#about to read 4, iclass 28, count 0 2006.285.18:32:58.14#ibcon#read 4, iclass 28, count 0 2006.285.18:32:58.14#ibcon#about to read 5, iclass 28, count 0 2006.285.18:32:58.14#ibcon#read 5, iclass 28, count 0 2006.285.18:32:58.14#ibcon#about to read 6, iclass 28, count 0 2006.285.18:32:58.14#ibcon#read 6, iclass 28, count 0 2006.285.18:32:58.14#ibcon#end of sib2, iclass 28, count 0 2006.285.18:32:58.14#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:32:58.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:32:58.14#ibcon#[27=USB\r\n] 2006.285.18:32:58.14#ibcon#*before write, iclass 28, count 0 2006.285.18:32:58.14#ibcon#enter sib2, iclass 28, count 0 2006.285.18:32:58.14#ibcon#flushed, iclass 28, count 0 2006.285.18:32:58.14#ibcon#about to write, iclass 28, count 0 2006.285.18:32:58.14#ibcon#wrote, iclass 28, count 0 2006.285.18:32:58.14#ibcon#about to read 3, iclass 28, count 0 2006.285.18:32:58.17#ibcon#read 3, iclass 28, count 0 2006.285.18:32:58.17#ibcon#about to read 4, iclass 28, count 0 2006.285.18:32:58.17#ibcon#read 4, iclass 28, count 0 2006.285.18:32:58.17#ibcon#about to read 5, iclass 28, count 0 2006.285.18:32:58.17#ibcon#read 5, iclass 28, count 0 2006.285.18:32:58.17#ibcon#about to read 6, iclass 28, count 0 2006.285.18:32:58.17#ibcon#read 6, iclass 28, count 0 2006.285.18:32:58.17#ibcon#end of sib2, iclass 28, count 0 2006.285.18:32:58.17#ibcon#*after write, iclass 28, count 0 2006.285.18:32:58.17#ibcon#*before return 0, iclass 28, count 0 2006.285.18:32:58.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:32:58.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:32:58.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:32:58.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:32:58.17$vck44/vblo=4,679.99 2006.285.18:32:58.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.18:32:58.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.18:32:58.17#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:58.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:32:58.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:32:58.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:32:58.17#ibcon#enter wrdev, iclass 31, count 0 2006.285.18:32:58.17#ibcon#first serial, iclass 31, count 0 2006.285.18:32:58.17#ibcon#enter sib2, iclass 31, count 0 2006.285.18:32:58.17#ibcon#flushed, iclass 31, count 0 2006.285.18:32:58.17#ibcon#about to write, iclass 31, count 0 2006.285.18:32:58.17#ibcon#wrote, iclass 31, count 0 2006.285.18:32:58.17#ibcon#about to read 3, iclass 31, count 0 2006.285.18:32:58.19#ibcon#read 3, iclass 31, count 0 2006.285.18:32:58.19#ibcon#about to read 4, iclass 31, count 0 2006.285.18:32:58.19#ibcon#read 4, iclass 31, count 0 2006.285.18:32:58.19#ibcon#about to read 5, iclass 31, count 0 2006.285.18:32:58.19#ibcon#read 5, iclass 31, count 0 2006.285.18:32:58.19#ibcon#about to read 6, iclass 31, count 0 2006.285.18:32:58.19#ibcon#read 6, iclass 31, count 0 2006.285.18:32:58.19#ibcon#end of sib2, iclass 31, count 0 2006.285.18:32:58.19#ibcon#*mode == 0, iclass 31, count 0 2006.285.18:32:58.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.18:32:58.19#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.18:32:58.19#ibcon#*before write, iclass 31, count 0 2006.285.18:32:58.19#ibcon#enter sib2, iclass 31, count 0 2006.285.18:32:58.19#ibcon#flushed, iclass 31, count 0 2006.285.18:32:58.19#ibcon#about to write, iclass 31, count 0 2006.285.18:32:58.19#ibcon#wrote, iclass 31, count 0 2006.285.18:32:58.19#ibcon#about to read 3, iclass 31, count 0 2006.285.18:32:58.23#ibcon#read 3, iclass 31, count 0 2006.285.18:32:58.23#ibcon#about to read 4, iclass 31, count 0 2006.285.18:32:58.23#ibcon#read 4, iclass 31, count 0 2006.285.18:32:58.23#ibcon#about to read 5, iclass 31, count 0 2006.285.18:32:58.23#ibcon#read 5, iclass 31, count 0 2006.285.18:32:58.23#ibcon#about to read 6, iclass 31, count 0 2006.285.18:32:58.23#ibcon#read 6, iclass 31, count 0 2006.285.18:32:58.23#ibcon#end of sib2, iclass 31, count 0 2006.285.18:32:58.23#ibcon#*after write, iclass 31, count 0 2006.285.18:32:58.23#ibcon#*before return 0, iclass 31, count 0 2006.285.18:32:58.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:32:58.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:32:58.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.18:32:58.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.18:32:58.23$vck44/vb=4,5 2006.285.18:32:58.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.18:32:58.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.18:32:58.23#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:58.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:32:58.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:32:58.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:32:58.29#ibcon#enter wrdev, iclass 33, count 2 2006.285.18:32:58.29#ibcon#first serial, iclass 33, count 2 2006.285.18:32:58.29#ibcon#enter sib2, iclass 33, count 2 2006.285.18:32:58.29#ibcon#flushed, iclass 33, count 2 2006.285.18:32:58.29#ibcon#about to write, iclass 33, count 2 2006.285.18:32:58.29#ibcon#wrote, iclass 33, count 2 2006.285.18:32:58.29#ibcon#about to read 3, iclass 33, count 2 2006.285.18:32:58.31#ibcon#read 3, iclass 33, count 2 2006.285.18:32:58.31#ibcon#about to read 4, iclass 33, count 2 2006.285.18:32:58.31#ibcon#read 4, iclass 33, count 2 2006.285.18:32:58.31#ibcon#about to read 5, iclass 33, count 2 2006.285.18:32:58.31#ibcon#read 5, iclass 33, count 2 2006.285.18:32:58.31#ibcon#about to read 6, iclass 33, count 2 2006.285.18:32:58.31#ibcon#read 6, iclass 33, count 2 2006.285.18:32:58.31#ibcon#end of sib2, iclass 33, count 2 2006.285.18:32:58.31#ibcon#*mode == 0, iclass 33, count 2 2006.285.18:32:58.31#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.18:32:58.31#ibcon#[27=AT04-05\r\n] 2006.285.18:32:58.31#ibcon#*before write, iclass 33, count 2 2006.285.18:32:58.31#ibcon#enter sib2, iclass 33, count 2 2006.285.18:32:58.31#ibcon#flushed, iclass 33, count 2 2006.285.18:32:58.31#ibcon#about to write, iclass 33, count 2 2006.285.18:32:58.31#ibcon#wrote, iclass 33, count 2 2006.285.18:32:58.31#ibcon#about to read 3, iclass 33, count 2 2006.285.18:32:58.34#ibcon#read 3, iclass 33, count 2 2006.285.18:32:58.34#ibcon#about to read 4, iclass 33, count 2 2006.285.18:32:58.34#ibcon#read 4, iclass 33, count 2 2006.285.18:32:58.34#ibcon#about to read 5, iclass 33, count 2 2006.285.18:32:58.34#ibcon#read 5, iclass 33, count 2 2006.285.18:32:58.34#ibcon#about to read 6, iclass 33, count 2 2006.285.18:32:58.34#ibcon#read 6, iclass 33, count 2 2006.285.18:32:58.34#ibcon#end of sib2, iclass 33, count 2 2006.285.18:32:58.34#ibcon#*after write, iclass 33, count 2 2006.285.18:32:58.34#ibcon#*before return 0, iclass 33, count 2 2006.285.18:32:58.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:32:58.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:32:58.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.18:32:58.34#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:58.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:32:58.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:32:58.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:32:58.85#ibcon#enter wrdev, iclass 33, count 0 2006.285.18:32:58.85#ibcon#first serial, iclass 33, count 0 2006.285.18:32:58.85#ibcon#enter sib2, iclass 33, count 0 2006.285.18:32:58.85#ibcon#flushed, iclass 33, count 0 2006.285.18:32:58.85#ibcon#about to write, iclass 33, count 0 2006.285.18:32:58.85#ibcon#wrote, iclass 33, count 0 2006.285.18:32:58.85#ibcon#about to read 3, iclass 33, count 0 2006.285.18:32:58.87#ibcon#read 3, iclass 33, count 0 2006.285.18:32:58.87#ibcon#about to read 4, iclass 33, count 0 2006.285.18:32:58.87#ibcon#read 4, iclass 33, count 0 2006.285.18:32:58.87#ibcon#about to read 5, iclass 33, count 0 2006.285.18:32:58.87#ibcon#read 5, iclass 33, count 0 2006.285.18:32:58.87#ibcon#about to read 6, iclass 33, count 0 2006.285.18:32:58.87#ibcon#read 6, iclass 33, count 0 2006.285.18:32:58.87#ibcon#end of sib2, iclass 33, count 0 2006.285.18:32:58.87#ibcon#*mode == 0, iclass 33, count 0 2006.285.18:32:58.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.18:32:58.87#ibcon#[27=USB\r\n] 2006.285.18:32:58.87#ibcon#*before write, iclass 33, count 0 2006.285.18:32:58.87#ibcon#enter sib2, iclass 33, count 0 2006.285.18:32:58.87#ibcon#flushed, iclass 33, count 0 2006.285.18:32:58.87#ibcon#about to write, iclass 33, count 0 2006.285.18:32:58.87#ibcon#wrote, iclass 33, count 0 2006.285.18:32:58.87#ibcon#about to read 3, iclass 33, count 0 2006.285.18:32:58.90#ibcon#read 3, iclass 33, count 0 2006.285.18:32:58.90#ibcon#about to read 4, iclass 33, count 0 2006.285.18:32:58.90#ibcon#read 4, iclass 33, count 0 2006.285.18:32:58.90#ibcon#about to read 5, iclass 33, count 0 2006.285.18:32:58.90#ibcon#read 5, iclass 33, count 0 2006.285.18:32:58.90#ibcon#about to read 6, iclass 33, count 0 2006.285.18:32:58.90#ibcon#read 6, iclass 33, count 0 2006.285.18:32:58.90#ibcon#end of sib2, iclass 33, count 0 2006.285.18:32:58.90#ibcon#*after write, iclass 33, count 0 2006.285.18:32:58.90#ibcon#*before return 0, iclass 33, count 0 2006.285.18:32:58.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:32:58.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:32:58.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.18:32:58.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.18:32:58.90$vck44/vblo=5,709.99 2006.285.18:32:58.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.18:32:58.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.18:32:58.90#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:58.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:32:58.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:32:58.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:32:58.90#ibcon#enter wrdev, iclass 35, count 0 2006.285.18:32:58.90#ibcon#first serial, iclass 35, count 0 2006.285.18:32:58.90#ibcon#enter sib2, iclass 35, count 0 2006.285.18:32:58.90#ibcon#flushed, iclass 35, count 0 2006.285.18:32:58.90#ibcon#about to write, iclass 35, count 0 2006.285.18:32:58.90#ibcon#wrote, iclass 35, count 0 2006.285.18:32:58.90#ibcon#about to read 3, iclass 35, count 0 2006.285.18:32:58.92#ibcon#read 3, iclass 35, count 0 2006.285.18:32:58.92#ibcon#about to read 4, iclass 35, count 0 2006.285.18:32:58.92#ibcon#read 4, iclass 35, count 0 2006.285.18:32:58.92#ibcon#about to read 5, iclass 35, count 0 2006.285.18:32:58.92#ibcon#read 5, iclass 35, count 0 2006.285.18:32:58.92#ibcon#about to read 6, iclass 35, count 0 2006.285.18:32:58.92#ibcon#read 6, iclass 35, count 0 2006.285.18:32:58.92#ibcon#end of sib2, iclass 35, count 0 2006.285.18:32:58.92#ibcon#*mode == 0, iclass 35, count 0 2006.285.18:32:58.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.18:32:58.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.18:32:58.92#ibcon#*before write, iclass 35, count 0 2006.285.18:32:58.92#ibcon#enter sib2, iclass 35, count 0 2006.285.18:32:58.92#ibcon#flushed, iclass 35, count 0 2006.285.18:32:58.92#ibcon#about to write, iclass 35, count 0 2006.285.18:32:58.92#ibcon#wrote, iclass 35, count 0 2006.285.18:32:58.92#ibcon#about to read 3, iclass 35, count 0 2006.285.18:32:58.96#ibcon#read 3, iclass 35, count 0 2006.285.18:32:58.96#ibcon#about to read 4, iclass 35, count 0 2006.285.18:32:58.96#ibcon#read 4, iclass 35, count 0 2006.285.18:32:58.96#ibcon#about to read 5, iclass 35, count 0 2006.285.18:32:58.96#ibcon#read 5, iclass 35, count 0 2006.285.18:32:58.96#ibcon#about to read 6, iclass 35, count 0 2006.285.18:32:58.96#ibcon#read 6, iclass 35, count 0 2006.285.18:32:58.96#ibcon#end of sib2, iclass 35, count 0 2006.285.18:32:58.96#ibcon#*after write, iclass 35, count 0 2006.285.18:32:58.96#ibcon#*before return 0, iclass 35, count 0 2006.285.18:32:58.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:32:58.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:32:58.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.18:32:58.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.18:32:58.96$vck44/vb=5,4 2006.285.18:32:58.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.18:32:58.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.18:32:58.96#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:58.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:32:59.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:32:59.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:32:59.02#ibcon#enter wrdev, iclass 37, count 2 2006.285.18:32:59.02#ibcon#first serial, iclass 37, count 2 2006.285.18:32:59.02#ibcon#enter sib2, iclass 37, count 2 2006.285.18:32:59.02#ibcon#flushed, iclass 37, count 2 2006.285.18:32:59.02#ibcon#about to write, iclass 37, count 2 2006.285.18:32:59.02#ibcon#wrote, iclass 37, count 2 2006.285.18:32:59.02#ibcon#about to read 3, iclass 37, count 2 2006.285.18:32:59.04#ibcon#read 3, iclass 37, count 2 2006.285.18:32:59.04#ibcon#about to read 4, iclass 37, count 2 2006.285.18:32:59.04#ibcon#read 4, iclass 37, count 2 2006.285.18:32:59.04#ibcon#about to read 5, iclass 37, count 2 2006.285.18:32:59.04#ibcon#read 5, iclass 37, count 2 2006.285.18:32:59.04#ibcon#about to read 6, iclass 37, count 2 2006.285.18:32:59.04#ibcon#read 6, iclass 37, count 2 2006.285.18:32:59.04#ibcon#end of sib2, iclass 37, count 2 2006.285.18:32:59.04#ibcon#*mode == 0, iclass 37, count 2 2006.285.18:32:59.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.18:32:59.04#ibcon#[27=AT05-04\r\n] 2006.285.18:32:59.04#ibcon#*before write, iclass 37, count 2 2006.285.18:32:59.04#ibcon#enter sib2, iclass 37, count 2 2006.285.18:32:59.04#ibcon#flushed, iclass 37, count 2 2006.285.18:32:59.04#ibcon#about to write, iclass 37, count 2 2006.285.18:32:59.04#ibcon#wrote, iclass 37, count 2 2006.285.18:32:59.04#ibcon#about to read 3, iclass 37, count 2 2006.285.18:32:59.07#ibcon#read 3, iclass 37, count 2 2006.285.18:32:59.07#ibcon#about to read 4, iclass 37, count 2 2006.285.18:32:59.07#ibcon#read 4, iclass 37, count 2 2006.285.18:32:59.07#ibcon#about to read 5, iclass 37, count 2 2006.285.18:32:59.07#ibcon#read 5, iclass 37, count 2 2006.285.18:32:59.07#ibcon#about to read 6, iclass 37, count 2 2006.285.18:32:59.07#ibcon#read 6, iclass 37, count 2 2006.285.18:32:59.07#ibcon#end of sib2, iclass 37, count 2 2006.285.18:32:59.07#ibcon#*after write, iclass 37, count 2 2006.285.18:32:59.07#ibcon#*before return 0, iclass 37, count 2 2006.285.18:32:59.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:32:59.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:32:59.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.18:32:59.07#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:59.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:32:59.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:32:59.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:32:59.19#ibcon#enter wrdev, iclass 37, count 0 2006.285.18:32:59.19#ibcon#first serial, iclass 37, count 0 2006.285.18:32:59.19#ibcon#enter sib2, iclass 37, count 0 2006.285.18:32:59.19#ibcon#flushed, iclass 37, count 0 2006.285.18:32:59.19#ibcon#about to write, iclass 37, count 0 2006.285.18:32:59.19#ibcon#wrote, iclass 37, count 0 2006.285.18:32:59.19#ibcon#about to read 3, iclass 37, count 0 2006.285.18:32:59.21#ibcon#read 3, iclass 37, count 0 2006.285.18:32:59.21#ibcon#about to read 4, iclass 37, count 0 2006.285.18:32:59.21#ibcon#read 4, iclass 37, count 0 2006.285.18:32:59.21#ibcon#about to read 5, iclass 37, count 0 2006.285.18:32:59.21#ibcon#read 5, iclass 37, count 0 2006.285.18:32:59.21#ibcon#about to read 6, iclass 37, count 0 2006.285.18:32:59.21#ibcon#read 6, iclass 37, count 0 2006.285.18:32:59.21#ibcon#end of sib2, iclass 37, count 0 2006.285.18:32:59.21#ibcon#*mode == 0, iclass 37, count 0 2006.285.18:32:59.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.18:32:59.21#ibcon#[27=USB\r\n] 2006.285.18:32:59.21#ibcon#*before write, iclass 37, count 0 2006.285.18:32:59.21#ibcon#enter sib2, iclass 37, count 0 2006.285.18:32:59.21#ibcon#flushed, iclass 37, count 0 2006.285.18:32:59.21#ibcon#about to write, iclass 37, count 0 2006.285.18:32:59.21#ibcon#wrote, iclass 37, count 0 2006.285.18:32:59.21#ibcon#about to read 3, iclass 37, count 0 2006.285.18:32:59.24#ibcon#read 3, iclass 37, count 0 2006.285.18:32:59.24#ibcon#about to read 4, iclass 37, count 0 2006.285.18:32:59.24#ibcon#read 4, iclass 37, count 0 2006.285.18:32:59.24#ibcon#about to read 5, iclass 37, count 0 2006.285.18:32:59.24#ibcon#read 5, iclass 37, count 0 2006.285.18:32:59.24#ibcon#about to read 6, iclass 37, count 0 2006.285.18:32:59.24#ibcon#read 6, iclass 37, count 0 2006.285.18:32:59.24#ibcon#end of sib2, iclass 37, count 0 2006.285.18:32:59.24#ibcon#*after write, iclass 37, count 0 2006.285.18:32:59.24#ibcon#*before return 0, iclass 37, count 0 2006.285.18:32:59.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:32:59.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:32:59.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.18:32:59.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.18:32:59.24$vck44/vblo=6,719.99 2006.285.18:32:59.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.18:32:59.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.18:32:59.24#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:59.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:32:59.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:32:59.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:32:59.24#ibcon#enter wrdev, iclass 39, count 0 2006.285.18:32:59.24#ibcon#first serial, iclass 39, count 0 2006.285.18:32:59.24#ibcon#enter sib2, iclass 39, count 0 2006.285.18:32:59.24#ibcon#flushed, iclass 39, count 0 2006.285.18:32:59.24#ibcon#about to write, iclass 39, count 0 2006.285.18:32:59.24#ibcon#wrote, iclass 39, count 0 2006.285.18:32:59.24#ibcon#about to read 3, iclass 39, count 0 2006.285.18:32:59.26#ibcon#read 3, iclass 39, count 0 2006.285.18:32:59.26#ibcon#about to read 4, iclass 39, count 0 2006.285.18:32:59.26#ibcon#read 4, iclass 39, count 0 2006.285.18:32:59.26#ibcon#about to read 5, iclass 39, count 0 2006.285.18:32:59.26#ibcon#read 5, iclass 39, count 0 2006.285.18:32:59.26#ibcon#about to read 6, iclass 39, count 0 2006.285.18:32:59.26#ibcon#read 6, iclass 39, count 0 2006.285.18:32:59.26#ibcon#end of sib2, iclass 39, count 0 2006.285.18:32:59.26#ibcon#*mode == 0, iclass 39, count 0 2006.285.18:32:59.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.18:32:59.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.18:32:59.26#ibcon#*before write, iclass 39, count 0 2006.285.18:32:59.26#ibcon#enter sib2, iclass 39, count 0 2006.285.18:32:59.26#ibcon#flushed, iclass 39, count 0 2006.285.18:32:59.26#ibcon#about to write, iclass 39, count 0 2006.285.18:32:59.26#ibcon#wrote, iclass 39, count 0 2006.285.18:32:59.26#ibcon#about to read 3, iclass 39, count 0 2006.285.18:32:59.30#ibcon#read 3, iclass 39, count 0 2006.285.18:32:59.30#ibcon#about to read 4, iclass 39, count 0 2006.285.18:32:59.30#ibcon#read 4, iclass 39, count 0 2006.285.18:32:59.30#ibcon#about to read 5, iclass 39, count 0 2006.285.18:32:59.30#ibcon#read 5, iclass 39, count 0 2006.285.18:32:59.30#ibcon#about to read 6, iclass 39, count 0 2006.285.18:32:59.30#ibcon#read 6, iclass 39, count 0 2006.285.18:32:59.30#ibcon#end of sib2, iclass 39, count 0 2006.285.18:32:59.30#ibcon#*after write, iclass 39, count 0 2006.285.18:32:59.30#ibcon#*before return 0, iclass 39, count 0 2006.285.18:32:59.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:32:59.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:32:59.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.18:32:59.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.18:32:59.30$vck44/vb=6,3 2006.285.18:32:59.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.18:32:59.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.18:32:59.30#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:59.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:32:59.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:32:59.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:32:59.36#ibcon#enter wrdev, iclass 3, count 2 2006.285.18:32:59.36#ibcon#first serial, iclass 3, count 2 2006.285.18:32:59.36#ibcon#enter sib2, iclass 3, count 2 2006.285.18:32:59.36#ibcon#flushed, iclass 3, count 2 2006.285.18:32:59.36#ibcon#about to write, iclass 3, count 2 2006.285.18:32:59.36#ibcon#wrote, iclass 3, count 2 2006.285.18:32:59.36#ibcon#about to read 3, iclass 3, count 2 2006.285.18:32:59.38#ibcon#read 3, iclass 3, count 2 2006.285.18:32:59.38#ibcon#about to read 4, iclass 3, count 2 2006.285.18:32:59.38#ibcon#read 4, iclass 3, count 2 2006.285.18:32:59.38#ibcon#about to read 5, iclass 3, count 2 2006.285.18:32:59.38#ibcon#read 5, iclass 3, count 2 2006.285.18:32:59.38#ibcon#about to read 6, iclass 3, count 2 2006.285.18:32:59.38#ibcon#read 6, iclass 3, count 2 2006.285.18:32:59.38#ibcon#end of sib2, iclass 3, count 2 2006.285.18:32:59.38#ibcon#*mode == 0, iclass 3, count 2 2006.285.18:32:59.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.18:32:59.38#ibcon#[27=AT06-03\r\n] 2006.285.18:32:59.38#ibcon#*before write, iclass 3, count 2 2006.285.18:32:59.38#ibcon#enter sib2, iclass 3, count 2 2006.285.18:32:59.38#ibcon#flushed, iclass 3, count 2 2006.285.18:32:59.38#ibcon#about to write, iclass 3, count 2 2006.285.18:32:59.38#ibcon#wrote, iclass 3, count 2 2006.285.18:32:59.38#ibcon#about to read 3, iclass 3, count 2 2006.285.18:32:59.41#ibcon#read 3, iclass 3, count 2 2006.285.18:32:59.41#ibcon#about to read 4, iclass 3, count 2 2006.285.18:32:59.41#ibcon#read 4, iclass 3, count 2 2006.285.18:32:59.41#ibcon#about to read 5, iclass 3, count 2 2006.285.18:32:59.41#ibcon#read 5, iclass 3, count 2 2006.285.18:32:59.41#ibcon#about to read 6, iclass 3, count 2 2006.285.18:32:59.41#ibcon#read 6, iclass 3, count 2 2006.285.18:32:59.41#ibcon#end of sib2, iclass 3, count 2 2006.285.18:32:59.41#ibcon#*after write, iclass 3, count 2 2006.285.18:32:59.41#ibcon#*before return 0, iclass 3, count 2 2006.285.18:32:59.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:32:59.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:32:59.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.18:32:59.41#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:59.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:32:59.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:32:59.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:32:59.53#ibcon#enter wrdev, iclass 3, count 0 2006.285.18:32:59.53#ibcon#first serial, iclass 3, count 0 2006.285.18:32:59.53#ibcon#enter sib2, iclass 3, count 0 2006.285.18:32:59.53#ibcon#flushed, iclass 3, count 0 2006.285.18:32:59.53#ibcon#about to write, iclass 3, count 0 2006.285.18:32:59.53#ibcon#wrote, iclass 3, count 0 2006.285.18:32:59.53#ibcon#about to read 3, iclass 3, count 0 2006.285.18:32:59.55#ibcon#read 3, iclass 3, count 0 2006.285.18:32:59.55#ibcon#about to read 4, iclass 3, count 0 2006.285.18:32:59.55#ibcon#read 4, iclass 3, count 0 2006.285.18:32:59.55#ibcon#about to read 5, iclass 3, count 0 2006.285.18:32:59.55#ibcon#read 5, iclass 3, count 0 2006.285.18:32:59.55#ibcon#about to read 6, iclass 3, count 0 2006.285.18:32:59.55#ibcon#read 6, iclass 3, count 0 2006.285.18:32:59.55#ibcon#end of sib2, iclass 3, count 0 2006.285.18:32:59.55#ibcon#*mode == 0, iclass 3, count 0 2006.285.18:32:59.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.18:32:59.55#ibcon#[27=USB\r\n] 2006.285.18:32:59.55#ibcon#*before write, iclass 3, count 0 2006.285.18:32:59.55#ibcon#enter sib2, iclass 3, count 0 2006.285.18:32:59.55#ibcon#flushed, iclass 3, count 0 2006.285.18:32:59.55#ibcon#about to write, iclass 3, count 0 2006.285.18:32:59.55#ibcon#wrote, iclass 3, count 0 2006.285.18:32:59.55#ibcon#about to read 3, iclass 3, count 0 2006.285.18:32:59.58#ibcon#read 3, iclass 3, count 0 2006.285.18:32:59.58#ibcon#about to read 4, iclass 3, count 0 2006.285.18:32:59.58#ibcon#read 4, iclass 3, count 0 2006.285.18:32:59.58#ibcon#about to read 5, iclass 3, count 0 2006.285.18:32:59.58#ibcon#read 5, iclass 3, count 0 2006.285.18:32:59.58#ibcon#about to read 6, iclass 3, count 0 2006.285.18:32:59.58#ibcon#read 6, iclass 3, count 0 2006.285.18:32:59.58#ibcon#end of sib2, iclass 3, count 0 2006.285.18:32:59.58#ibcon#*after write, iclass 3, count 0 2006.285.18:32:59.58#ibcon#*before return 0, iclass 3, count 0 2006.285.18:32:59.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:32:59.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:32:59.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.18:32:59.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.18:32:59.58$vck44/vblo=7,734.99 2006.285.18:32:59.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.18:32:59.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.18:32:59.58#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:59.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:32:59.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:32:59.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:32:59.58#ibcon#enter wrdev, iclass 5, count 0 2006.285.18:32:59.58#ibcon#first serial, iclass 5, count 0 2006.285.18:32:59.58#ibcon#enter sib2, iclass 5, count 0 2006.285.18:32:59.58#ibcon#flushed, iclass 5, count 0 2006.285.18:32:59.58#ibcon#about to write, iclass 5, count 0 2006.285.18:32:59.58#ibcon#wrote, iclass 5, count 0 2006.285.18:32:59.58#ibcon#about to read 3, iclass 5, count 0 2006.285.18:32:59.60#ibcon#read 3, iclass 5, count 0 2006.285.18:32:59.60#ibcon#about to read 4, iclass 5, count 0 2006.285.18:32:59.60#ibcon#read 4, iclass 5, count 0 2006.285.18:32:59.60#ibcon#about to read 5, iclass 5, count 0 2006.285.18:32:59.60#ibcon#read 5, iclass 5, count 0 2006.285.18:32:59.60#ibcon#about to read 6, iclass 5, count 0 2006.285.18:32:59.60#ibcon#read 6, iclass 5, count 0 2006.285.18:32:59.60#ibcon#end of sib2, iclass 5, count 0 2006.285.18:32:59.60#ibcon#*mode == 0, iclass 5, count 0 2006.285.18:32:59.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.18:32:59.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.18:32:59.60#ibcon#*before write, iclass 5, count 0 2006.285.18:32:59.60#ibcon#enter sib2, iclass 5, count 0 2006.285.18:32:59.60#ibcon#flushed, iclass 5, count 0 2006.285.18:32:59.60#ibcon#about to write, iclass 5, count 0 2006.285.18:32:59.60#ibcon#wrote, iclass 5, count 0 2006.285.18:32:59.60#ibcon#about to read 3, iclass 5, count 0 2006.285.18:32:59.64#ibcon#read 3, iclass 5, count 0 2006.285.18:32:59.64#ibcon#about to read 4, iclass 5, count 0 2006.285.18:32:59.64#ibcon#read 4, iclass 5, count 0 2006.285.18:32:59.64#ibcon#about to read 5, iclass 5, count 0 2006.285.18:32:59.64#ibcon#read 5, iclass 5, count 0 2006.285.18:32:59.64#ibcon#about to read 6, iclass 5, count 0 2006.285.18:32:59.64#ibcon#read 6, iclass 5, count 0 2006.285.18:32:59.64#ibcon#end of sib2, iclass 5, count 0 2006.285.18:32:59.64#ibcon#*after write, iclass 5, count 0 2006.285.18:32:59.64#ibcon#*before return 0, iclass 5, count 0 2006.285.18:32:59.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:32:59.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:32:59.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.18:32:59.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.18:32:59.64$vck44/vb=7,4 2006.285.18:32:59.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.18:32:59.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.18:32:59.64#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:59.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:32:59.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:32:59.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:32:59.70#ibcon#enter wrdev, iclass 7, count 2 2006.285.18:32:59.70#ibcon#first serial, iclass 7, count 2 2006.285.18:32:59.70#ibcon#enter sib2, iclass 7, count 2 2006.285.18:32:59.70#ibcon#flushed, iclass 7, count 2 2006.285.18:32:59.70#ibcon#about to write, iclass 7, count 2 2006.285.18:32:59.70#ibcon#wrote, iclass 7, count 2 2006.285.18:32:59.70#ibcon#about to read 3, iclass 7, count 2 2006.285.18:32:59.72#ibcon#read 3, iclass 7, count 2 2006.285.18:32:59.72#ibcon#about to read 4, iclass 7, count 2 2006.285.18:32:59.72#ibcon#read 4, iclass 7, count 2 2006.285.18:32:59.72#ibcon#about to read 5, iclass 7, count 2 2006.285.18:32:59.72#ibcon#read 5, iclass 7, count 2 2006.285.18:32:59.72#ibcon#about to read 6, iclass 7, count 2 2006.285.18:32:59.72#ibcon#read 6, iclass 7, count 2 2006.285.18:32:59.72#ibcon#end of sib2, iclass 7, count 2 2006.285.18:32:59.72#ibcon#*mode == 0, iclass 7, count 2 2006.285.18:32:59.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.18:32:59.72#ibcon#[27=AT07-04\r\n] 2006.285.18:32:59.72#ibcon#*before write, iclass 7, count 2 2006.285.18:32:59.72#ibcon#enter sib2, iclass 7, count 2 2006.285.18:32:59.72#ibcon#flushed, iclass 7, count 2 2006.285.18:32:59.72#ibcon#about to write, iclass 7, count 2 2006.285.18:32:59.72#ibcon#wrote, iclass 7, count 2 2006.285.18:32:59.72#ibcon#about to read 3, iclass 7, count 2 2006.285.18:32:59.75#ibcon#read 3, iclass 7, count 2 2006.285.18:32:59.75#ibcon#about to read 4, iclass 7, count 2 2006.285.18:32:59.75#ibcon#read 4, iclass 7, count 2 2006.285.18:32:59.75#ibcon#about to read 5, iclass 7, count 2 2006.285.18:32:59.75#ibcon#read 5, iclass 7, count 2 2006.285.18:32:59.75#ibcon#about to read 6, iclass 7, count 2 2006.285.18:32:59.75#ibcon#read 6, iclass 7, count 2 2006.285.18:32:59.75#ibcon#end of sib2, iclass 7, count 2 2006.285.18:32:59.75#ibcon#*after write, iclass 7, count 2 2006.285.18:32:59.75#ibcon#*before return 0, iclass 7, count 2 2006.285.18:32:59.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:32:59.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:32:59.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.18:32:59.75#ibcon#ireg 7 cls_cnt 0 2006.285.18:32:59.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:32:59.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:32:59.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:32:59.87#ibcon#enter wrdev, iclass 7, count 0 2006.285.18:32:59.87#ibcon#first serial, iclass 7, count 0 2006.285.18:32:59.87#ibcon#enter sib2, iclass 7, count 0 2006.285.18:32:59.87#ibcon#flushed, iclass 7, count 0 2006.285.18:32:59.87#ibcon#about to write, iclass 7, count 0 2006.285.18:32:59.87#ibcon#wrote, iclass 7, count 0 2006.285.18:32:59.87#ibcon#about to read 3, iclass 7, count 0 2006.285.18:32:59.89#ibcon#read 3, iclass 7, count 0 2006.285.18:32:59.89#ibcon#about to read 4, iclass 7, count 0 2006.285.18:32:59.89#ibcon#read 4, iclass 7, count 0 2006.285.18:32:59.89#ibcon#about to read 5, iclass 7, count 0 2006.285.18:32:59.89#ibcon#read 5, iclass 7, count 0 2006.285.18:32:59.89#ibcon#about to read 6, iclass 7, count 0 2006.285.18:32:59.89#ibcon#read 6, iclass 7, count 0 2006.285.18:32:59.89#ibcon#end of sib2, iclass 7, count 0 2006.285.18:32:59.89#ibcon#*mode == 0, iclass 7, count 0 2006.285.18:32:59.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.18:32:59.89#ibcon#[27=USB\r\n] 2006.285.18:32:59.89#ibcon#*before write, iclass 7, count 0 2006.285.18:32:59.89#ibcon#enter sib2, iclass 7, count 0 2006.285.18:32:59.89#ibcon#flushed, iclass 7, count 0 2006.285.18:32:59.89#ibcon#about to write, iclass 7, count 0 2006.285.18:32:59.89#ibcon#wrote, iclass 7, count 0 2006.285.18:32:59.89#ibcon#about to read 3, iclass 7, count 0 2006.285.18:32:59.92#ibcon#read 3, iclass 7, count 0 2006.285.18:32:59.92#ibcon#about to read 4, iclass 7, count 0 2006.285.18:32:59.92#ibcon#read 4, iclass 7, count 0 2006.285.18:32:59.92#ibcon#about to read 5, iclass 7, count 0 2006.285.18:32:59.92#ibcon#read 5, iclass 7, count 0 2006.285.18:32:59.92#ibcon#about to read 6, iclass 7, count 0 2006.285.18:32:59.92#ibcon#read 6, iclass 7, count 0 2006.285.18:32:59.92#ibcon#end of sib2, iclass 7, count 0 2006.285.18:32:59.92#ibcon#*after write, iclass 7, count 0 2006.285.18:32:59.92#ibcon#*before return 0, iclass 7, count 0 2006.285.18:32:59.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:32:59.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:32:59.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.18:32:59.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.18:32:59.92$vck44/vblo=8,744.99 2006.285.18:32:59.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.18:32:59.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.18:32:59.92#ibcon#ireg 17 cls_cnt 0 2006.285.18:32:59.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:32:59.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:32:59.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:32:59.92#ibcon#enter wrdev, iclass 11, count 0 2006.285.18:32:59.92#ibcon#first serial, iclass 11, count 0 2006.285.18:32:59.92#ibcon#enter sib2, iclass 11, count 0 2006.285.18:32:59.92#ibcon#flushed, iclass 11, count 0 2006.285.18:32:59.92#ibcon#about to write, iclass 11, count 0 2006.285.18:32:59.92#ibcon#wrote, iclass 11, count 0 2006.285.18:32:59.92#ibcon#about to read 3, iclass 11, count 0 2006.285.18:32:59.94#ibcon#read 3, iclass 11, count 0 2006.285.18:32:59.94#ibcon#about to read 4, iclass 11, count 0 2006.285.18:32:59.94#ibcon#read 4, iclass 11, count 0 2006.285.18:32:59.94#ibcon#about to read 5, iclass 11, count 0 2006.285.18:32:59.94#ibcon#read 5, iclass 11, count 0 2006.285.18:32:59.94#ibcon#about to read 6, iclass 11, count 0 2006.285.18:32:59.94#ibcon#read 6, iclass 11, count 0 2006.285.18:32:59.94#ibcon#end of sib2, iclass 11, count 0 2006.285.18:32:59.94#ibcon#*mode == 0, iclass 11, count 0 2006.285.18:32:59.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.18:32:59.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.18:32:59.94#ibcon#*before write, iclass 11, count 0 2006.285.18:32:59.94#ibcon#enter sib2, iclass 11, count 0 2006.285.18:32:59.94#ibcon#flushed, iclass 11, count 0 2006.285.18:32:59.94#ibcon#about to write, iclass 11, count 0 2006.285.18:32:59.94#ibcon#wrote, iclass 11, count 0 2006.285.18:32:59.94#ibcon#about to read 3, iclass 11, count 0 2006.285.18:32:59.98#ibcon#read 3, iclass 11, count 0 2006.285.18:32:59.98#ibcon#about to read 4, iclass 11, count 0 2006.285.18:32:59.98#ibcon#read 4, iclass 11, count 0 2006.285.18:32:59.98#ibcon#about to read 5, iclass 11, count 0 2006.285.18:32:59.98#ibcon#read 5, iclass 11, count 0 2006.285.18:32:59.98#ibcon#about to read 6, iclass 11, count 0 2006.285.18:32:59.98#ibcon#read 6, iclass 11, count 0 2006.285.18:32:59.98#ibcon#end of sib2, iclass 11, count 0 2006.285.18:32:59.98#ibcon#*after write, iclass 11, count 0 2006.285.18:32:59.98#ibcon#*before return 0, iclass 11, count 0 2006.285.18:32:59.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:32:59.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:32:59.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.18:32:59.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.18:32:59.98$vck44/vb=8,4 2006.285.18:32:59.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.18:32:59.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.18:32:59.98#ibcon#ireg 11 cls_cnt 2 2006.285.18:32:59.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:33:00.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:33:00.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:33:00.04#ibcon#enter wrdev, iclass 13, count 2 2006.285.18:33:00.04#ibcon#first serial, iclass 13, count 2 2006.285.18:33:00.04#ibcon#enter sib2, iclass 13, count 2 2006.285.18:33:00.04#ibcon#flushed, iclass 13, count 2 2006.285.18:33:00.04#ibcon#about to write, iclass 13, count 2 2006.285.18:33:00.04#ibcon#wrote, iclass 13, count 2 2006.285.18:33:00.04#ibcon#about to read 3, iclass 13, count 2 2006.285.18:33:00.06#ibcon#read 3, iclass 13, count 2 2006.285.18:33:00.06#ibcon#about to read 4, iclass 13, count 2 2006.285.18:33:00.06#ibcon#read 4, iclass 13, count 2 2006.285.18:33:00.06#ibcon#about to read 5, iclass 13, count 2 2006.285.18:33:00.06#ibcon#read 5, iclass 13, count 2 2006.285.18:33:00.06#ibcon#about to read 6, iclass 13, count 2 2006.285.18:33:00.06#ibcon#read 6, iclass 13, count 2 2006.285.18:33:00.06#ibcon#end of sib2, iclass 13, count 2 2006.285.18:33:00.06#ibcon#*mode == 0, iclass 13, count 2 2006.285.18:33:00.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.18:33:00.06#ibcon#[27=AT08-04\r\n] 2006.285.18:33:00.06#ibcon#*before write, iclass 13, count 2 2006.285.18:33:00.06#ibcon#enter sib2, iclass 13, count 2 2006.285.18:33:00.06#ibcon#flushed, iclass 13, count 2 2006.285.18:33:00.06#ibcon#about to write, iclass 13, count 2 2006.285.18:33:00.06#ibcon#wrote, iclass 13, count 2 2006.285.18:33:00.06#ibcon#about to read 3, iclass 13, count 2 2006.285.18:33:00.09#ibcon#read 3, iclass 13, count 2 2006.285.18:33:00.09#ibcon#about to read 4, iclass 13, count 2 2006.285.18:33:00.09#ibcon#read 4, iclass 13, count 2 2006.285.18:33:00.09#ibcon#about to read 5, iclass 13, count 2 2006.285.18:33:00.09#ibcon#read 5, iclass 13, count 2 2006.285.18:33:00.09#ibcon#about to read 6, iclass 13, count 2 2006.285.18:33:00.09#ibcon#read 6, iclass 13, count 2 2006.285.18:33:00.09#ibcon#end of sib2, iclass 13, count 2 2006.285.18:33:00.09#ibcon#*after write, iclass 13, count 2 2006.285.18:33:00.09#ibcon#*before return 0, iclass 13, count 2 2006.285.18:33:00.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:33:00.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:33:00.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.18:33:00.09#ibcon#ireg 7 cls_cnt 0 2006.285.18:33:00.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:33:00.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:33:00.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:33:00.21#ibcon#enter wrdev, iclass 13, count 0 2006.285.18:33:00.21#ibcon#first serial, iclass 13, count 0 2006.285.18:33:00.21#ibcon#enter sib2, iclass 13, count 0 2006.285.18:33:00.21#ibcon#flushed, iclass 13, count 0 2006.285.18:33:00.21#ibcon#about to write, iclass 13, count 0 2006.285.18:33:00.21#ibcon#wrote, iclass 13, count 0 2006.285.18:33:00.21#ibcon#about to read 3, iclass 13, count 0 2006.285.18:33:00.23#ibcon#read 3, iclass 13, count 0 2006.285.18:33:00.23#ibcon#about to read 4, iclass 13, count 0 2006.285.18:33:00.23#ibcon#read 4, iclass 13, count 0 2006.285.18:33:00.23#ibcon#about to read 5, iclass 13, count 0 2006.285.18:33:00.23#ibcon#read 5, iclass 13, count 0 2006.285.18:33:00.23#ibcon#about to read 6, iclass 13, count 0 2006.285.18:33:00.23#ibcon#read 6, iclass 13, count 0 2006.285.18:33:00.23#ibcon#end of sib2, iclass 13, count 0 2006.285.18:33:00.23#ibcon#*mode == 0, iclass 13, count 0 2006.285.18:33:00.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.18:33:00.23#ibcon#[27=USB\r\n] 2006.285.18:33:00.23#ibcon#*before write, iclass 13, count 0 2006.285.18:33:00.23#ibcon#enter sib2, iclass 13, count 0 2006.285.18:33:00.23#ibcon#flushed, iclass 13, count 0 2006.285.18:33:00.23#ibcon#about to write, iclass 13, count 0 2006.285.18:33:00.23#ibcon#wrote, iclass 13, count 0 2006.285.18:33:00.23#ibcon#about to read 3, iclass 13, count 0 2006.285.18:33:00.26#ibcon#read 3, iclass 13, count 0 2006.285.18:33:00.26#ibcon#about to read 4, iclass 13, count 0 2006.285.18:33:00.26#ibcon#read 4, iclass 13, count 0 2006.285.18:33:00.26#ibcon#about to read 5, iclass 13, count 0 2006.285.18:33:00.26#ibcon#read 5, iclass 13, count 0 2006.285.18:33:00.26#ibcon#about to read 6, iclass 13, count 0 2006.285.18:33:00.26#ibcon#read 6, iclass 13, count 0 2006.285.18:33:00.26#ibcon#end of sib2, iclass 13, count 0 2006.285.18:33:00.26#ibcon#*after write, iclass 13, count 0 2006.285.18:33:00.26#ibcon#*before return 0, iclass 13, count 0 2006.285.18:33:00.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:33:00.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:33:00.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.18:33:00.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.18:33:00.26$vck44/vabw=wide 2006.285.18:33:00.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.18:33:00.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.18:33:00.26#ibcon#ireg 8 cls_cnt 0 2006.285.18:33:00.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:33:00.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:33:00.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:33:00.26#ibcon#enter wrdev, iclass 15, count 0 2006.285.18:33:00.26#ibcon#first serial, iclass 15, count 0 2006.285.18:33:00.26#ibcon#enter sib2, iclass 15, count 0 2006.285.18:33:00.26#ibcon#flushed, iclass 15, count 0 2006.285.18:33:00.26#ibcon#about to write, iclass 15, count 0 2006.285.18:33:00.26#ibcon#wrote, iclass 15, count 0 2006.285.18:33:00.26#ibcon#about to read 3, iclass 15, count 0 2006.285.18:33:00.28#ibcon#read 3, iclass 15, count 0 2006.285.18:33:00.28#ibcon#about to read 4, iclass 15, count 0 2006.285.18:33:00.28#ibcon#read 4, iclass 15, count 0 2006.285.18:33:00.28#ibcon#about to read 5, iclass 15, count 0 2006.285.18:33:00.28#ibcon#read 5, iclass 15, count 0 2006.285.18:33:00.28#ibcon#about to read 6, iclass 15, count 0 2006.285.18:33:00.28#ibcon#read 6, iclass 15, count 0 2006.285.18:33:00.28#ibcon#end of sib2, iclass 15, count 0 2006.285.18:33:00.28#ibcon#*mode == 0, iclass 15, count 0 2006.285.18:33:00.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.18:33:00.28#ibcon#[25=BW32\r\n] 2006.285.18:33:00.28#ibcon#*before write, iclass 15, count 0 2006.285.18:33:00.28#ibcon#enter sib2, iclass 15, count 0 2006.285.18:33:00.28#ibcon#flushed, iclass 15, count 0 2006.285.18:33:00.28#ibcon#about to write, iclass 15, count 0 2006.285.18:33:00.28#ibcon#wrote, iclass 15, count 0 2006.285.18:33:00.28#ibcon#about to read 3, iclass 15, count 0 2006.285.18:33:00.31#ibcon#read 3, iclass 15, count 0 2006.285.18:33:00.31#ibcon#about to read 4, iclass 15, count 0 2006.285.18:33:00.31#ibcon#read 4, iclass 15, count 0 2006.285.18:33:00.31#ibcon#about to read 5, iclass 15, count 0 2006.285.18:33:00.31#ibcon#read 5, iclass 15, count 0 2006.285.18:33:00.31#ibcon#about to read 6, iclass 15, count 0 2006.285.18:33:00.31#ibcon#read 6, iclass 15, count 0 2006.285.18:33:00.31#ibcon#end of sib2, iclass 15, count 0 2006.285.18:33:00.31#ibcon#*after write, iclass 15, count 0 2006.285.18:33:00.31#ibcon#*before return 0, iclass 15, count 0 2006.285.18:33:00.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:33:00.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:33:00.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.18:33:00.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.18:33:00.31$vck44/vbbw=wide 2006.285.18:33:00.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.18:33:00.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.18:33:00.31#ibcon#ireg 8 cls_cnt 0 2006.285.18:33:00.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.18:33:00.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.18:33:00.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.18:33:00.38#ibcon#enter wrdev, iclass 17, count 0 2006.285.18:33:00.38#ibcon#first serial, iclass 17, count 0 2006.285.18:33:00.38#ibcon#enter sib2, iclass 17, count 0 2006.285.18:33:00.38#ibcon#flushed, iclass 17, count 0 2006.285.18:33:00.38#ibcon#about to write, iclass 17, count 0 2006.285.18:33:00.38#ibcon#wrote, iclass 17, count 0 2006.285.18:33:00.38#ibcon#about to read 3, iclass 17, count 0 2006.285.18:33:00.40#ibcon#read 3, iclass 17, count 0 2006.285.18:33:00.46#ibcon#about to read 4, iclass 17, count 0 2006.285.18:33:00.46#ibcon#read 4, iclass 17, count 0 2006.285.18:33:00.46#ibcon#about to read 5, iclass 17, count 0 2006.285.18:33:00.46#ibcon#read 5, iclass 17, count 0 2006.285.18:33:00.46#ibcon#about to read 6, iclass 17, count 0 2006.285.18:33:00.46#ibcon#read 6, iclass 17, count 0 2006.285.18:33:00.46#ibcon#end of sib2, iclass 17, count 0 2006.285.18:33:00.46#ibcon#*mode == 0, iclass 17, count 0 2006.285.18:33:00.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.18:33:00.46#ibcon#[27=BW32\r\n] 2006.285.18:33:00.46#ibcon#*before write, iclass 17, count 0 2006.285.18:33:00.46#ibcon#enter sib2, iclass 17, count 0 2006.285.18:33:00.46#ibcon#flushed, iclass 17, count 0 2006.285.18:33:00.46#ibcon#about to write, iclass 17, count 0 2006.285.18:33:00.46#ibcon#wrote, iclass 17, count 0 2006.285.18:33:00.46#ibcon#about to read 3, iclass 17, count 0 2006.285.18:33:00.49#ibcon#read 3, iclass 17, count 0 2006.285.18:33:00.49#ibcon#about to read 4, iclass 17, count 0 2006.285.18:33:00.49#ibcon#read 4, iclass 17, count 0 2006.285.18:33:00.49#ibcon#about to read 5, iclass 17, count 0 2006.285.18:33:00.49#ibcon#read 5, iclass 17, count 0 2006.285.18:33:00.49#ibcon#about to read 6, iclass 17, count 0 2006.285.18:33:00.49#ibcon#read 6, iclass 17, count 0 2006.285.18:33:00.49#ibcon#end of sib2, iclass 17, count 0 2006.285.18:33:00.49#ibcon#*after write, iclass 17, count 0 2006.285.18:33:00.49#ibcon#*before return 0, iclass 17, count 0 2006.285.18:33:00.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.18:33:00.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.18:33:00.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.18:33:00.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.18:33:00.49$setupk4/ifdk4 2006.285.18:33:00.49$ifdk4/lo= 2006.285.18:33:00.49$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.18:33:00.49$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.18:33:00.49$ifdk4/patch= 2006.285.18:33:00.49$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.18:33:00.49$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.18:33:00.49$setupk4/!*+20s 2006.285.18:33:06.14#trakl#Source acquired 2006.285.18:33:06.14#flagr#flagr/antenna,acquired 2006.285.18:33:08.03#abcon#<5=/00 0.2 0.6 15.321001014.7\r\n> 2006.285.18:33:08.05#abcon#{5=INTERFACE CLEAR} 2006.285.18:33:08.11#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:33:13.78$setupk4/"tpicd 2006.285.18:33:13.78$setupk4/echo=off 2006.285.18:33:13.78$setupk4/xlog=off 2006.285.18:33:13.78:!2006.285.18:34:49 2006.285.18:34:49.00:preob 2006.285.18:34:49.13/onsource/TRACKING 2006.285.18:34:49.13:!2006.285.18:34:59 2006.285.18:34:59.00:"tape 2006.285.18:34:59.00:"st=record 2006.285.18:34:59.00:data_valid=on 2006.285.18:34:59.00:midob 2006.285.18:35:00.13/onsource/TRACKING 2006.285.18:35:00.13/wx/15.33,1014.8,100 2006.285.18:35:00.30/cable/+6.5045E-03 2006.285.18:35:01.39/va/01,07,usb,yes,32,34 2006.285.18:35:01.39/va/02,06,usb,yes,32,32 2006.285.18:35:01.39/va/03,07,usb,yes,31,33 2006.285.18:35:01.39/va/04,06,usb,yes,33,34 2006.285.18:35:01.39/va/05,03,usb,yes,32,32 2006.285.18:35:01.39/va/06,04,usb,yes,29,28 2006.285.18:35:01.39/va/07,04,usb,yes,29,30 2006.285.18:35:01.39/va/08,03,usb,yes,30,37 2006.285.18:35:01.62/valo/01,524.99,yes,locked 2006.285.18:35:01.62/valo/02,534.99,yes,locked 2006.285.18:35:01.62/valo/03,564.99,yes,locked 2006.285.18:35:01.62/valo/04,624.99,yes,locked 2006.285.18:35:01.62/valo/05,734.99,yes,locked 2006.285.18:35:01.62/valo/06,814.99,yes,locked 2006.285.18:35:01.62/valo/07,864.99,yes,locked 2006.285.18:35:01.62/valo/08,884.99,yes,locked 2006.285.18:35:02.71/vb/01,04,usb,yes,30,28 2006.285.18:35:02.71/vb/02,05,usb,yes,28,28 2006.285.18:35:02.71/vb/03,04,usb,yes,29,32 2006.285.18:35:02.71/vb/04,05,usb,yes,29,28 2006.285.18:35:02.71/vb/05,04,usb,yes,26,28 2006.285.18:35:02.71/vb/06,03,usb,yes,37,33 2006.285.18:35:02.71/vb/07,04,usb,yes,30,30 2006.285.18:35:02.71/vb/08,04,usb,yes,27,30 2006.285.18:35:02.94/vblo/01,629.99,yes,locked 2006.285.18:35:02.94/vblo/02,634.99,yes,locked 2006.285.18:35:02.94/vblo/03,649.99,yes,locked 2006.285.18:35:02.94/vblo/04,679.99,yes,locked 2006.285.18:35:02.94/vblo/05,709.99,yes,locked 2006.285.18:35:02.94/vblo/06,719.99,yes,locked 2006.285.18:35:02.94/vblo/07,734.99,yes,locked 2006.285.18:35:02.94/vblo/08,744.99,yes,locked 2006.285.18:35:03.09/vabw/8 2006.285.18:35:03.24/vbbw/8 2006.285.18:35:03.33/xfe/off,on,12.0 2006.285.18:35:03.70/ifatt/23,28,28,28 2006.285.18:35:04.07/fmout-gps/S +2.53E-07 2006.285.18:35:04.09:!2006.285.18:36:39 2006.285.18:36:39.01:data_valid=off 2006.285.18:36:39.01:"et 2006.285.18:36:39.01:!+3s 2006.285.18:36:42.02:"tape 2006.285.18:36:42.02:postob 2006.285.18:36:42.20/cable/+6.5064E-03 2006.285.18:36:42.20/wx/15.30,1014.8,100 2006.285.18:36:42.26/fmout-gps/S +2.51E-07 2006.285.18:36:42.26:scan_name=285-1839,jd0610,210 2006.285.18:36:42.26:source=1044+719,104827.62,714335.9,2000.0,cw 2006.285.18:36:44.14#flagr#flagr/antenna,new-source 2006.285.18:36:44.14:checkk5 2006.285.18:36:47.71/chk_autoobs//k5ts1/ autoobs is running! 2006.285.18:36:48.32/chk_autoobs//k5ts2/ autoobs is running! 2006.285.18:36:48.79/chk_autoobs//k5ts3/ autoobs is running! 2006.285.18:36:49.18/chk_autoobs//k5ts4/ autoobs is running! 2006.285.18:36:49.58/chk_obsdata//k5ts1/T2851834??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.18:36:49.99/chk_obsdata//k5ts2/T2851834??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.18:36:50.40/chk_obsdata//k5ts3/T2851834??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.18:36:50.88/chk_obsdata//k5ts4/T2851834??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.18:36:52.14/k5log//k5ts1_log_newline 2006.285.18:36:52.95/k5log//k5ts2_log_newline 2006.285.18:36:53.83/k5log//k5ts3_log_newline 2006.285.18:36:54.59/k5log//k5ts4_log_newline 2006.285.18:36:54.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.18:36:54.61:setupk4=1 2006.285.18:36:54.62$setupk4/echo=on 2006.285.18:36:54.62$setupk4/pcalon 2006.285.18:36:54.62$pcalon/"no phase cal control is implemented here 2006.285.18:36:54.62$setupk4/"tpicd=stop 2006.285.18:36:54.62$setupk4/"rec=synch_on 2006.285.18:36:54.62$setupk4/"rec_mode=128 2006.285.18:36:54.62$setupk4/!* 2006.285.18:36:54.62$setupk4/recpk4 2006.285.18:36:54.62$recpk4/recpatch= 2006.285.18:36:54.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.18:36:54.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.18:36:54.62$setupk4/vck44 2006.285.18:36:54.62$vck44/valo=1,524.99 2006.285.18:36:54.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.18:36:54.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.18:36:54.62#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:54.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:36:54.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:36:54.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:36:54.62#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:36:54.62#ibcon#first serial, iclass 4, count 0 2006.285.18:36:54.62#ibcon#enter sib2, iclass 4, count 0 2006.285.18:36:54.62#ibcon#flushed, iclass 4, count 0 2006.285.18:36:54.62#ibcon#about to write, iclass 4, count 0 2006.285.18:36:54.62#ibcon#wrote, iclass 4, count 0 2006.285.18:36:54.62#ibcon#about to read 3, iclass 4, count 0 2006.285.18:36:54.64#ibcon#read 3, iclass 4, count 0 2006.285.18:36:54.64#ibcon#about to read 4, iclass 4, count 0 2006.285.18:36:54.64#ibcon#read 4, iclass 4, count 0 2006.285.18:36:54.64#ibcon#about to read 5, iclass 4, count 0 2006.285.18:36:54.64#ibcon#read 5, iclass 4, count 0 2006.285.18:36:54.64#ibcon#about to read 6, iclass 4, count 0 2006.285.18:36:54.64#ibcon#read 6, iclass 4, count 0 2006.285.18:36:54.64#ibcon#end of sib2, iclass 4, count 0 2006.285.18:36:54.64#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:36:54.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:36:54.64#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.18:36:54.64#ibcon#*before write, iclass 4, count 0 2006.285.18:36:54.64#ibcon#enter sib2, iclass 4, count 0 2006.285.18:36:54.64#ibcon#flushed, iclass 4, count 0 2006.285.18:36:54.64#ibcon#about to write, iclass 4, count 0 2006.285.18:36:54.64#ibcon#wrote, iclass 4, count 0 2006.285.18:36:54.64#ibcon#about to read 3, iclass 4, count 0 2006.285.18:36:54.69#ibcon#read 3, iclass 4, count 0 2006.285.18:36:54.69#ibcon#about to read 4, iclass 4, count 0 2006.285.18:36:54.69#ibcon#read 4, iclass 4, count 0 2006.285.18:36:54.69#ibcon#about to read 5, iclass 4, count 0 2006.285.18:36:54.69#ibcon#read 5, iclass 4, count 0 2006.285.18:36:54.69#ibcon#about to read 6, iclass 4, count 0 2006.285.18:36:54.69#ibcon#read 6, iclass 4, count 0 2006.285.18:36:54.69#ibcon#end of sib2, iclass 4, count 0 2006.285.18:36:54.69#ibcon#*after write, iclass 4, count 0 2006.285.18:36:54.69#ibcon#*before return 0, iclass 4, count 0 2006.285.18:36:54.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:36:54.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:36:54.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:36:54.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:36:54.69$vck44/va=1,7 2006.285.18:36:54.69#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.18:36:54.69#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.18:36:54.69#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:54.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:36:54.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:36:54.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:36:54.69#ibcon#enter wrdev, iclass 6, count 2 2006.285.18:36:54.69#ibcon#first serial, iclass 6, count 2 2006.285.18:36:54.69#ibcon#enter sib2, iclass 6, count 2 2006.285.18:36:54.69#ibcon#flushed, iclass 6, count 2 2006.285.18:36:54.69#ibcon#about to write, iclass 6, count 2 2006.285.18:36:54.69#ibcon#wrote, iclass 6, count 2 2006.285.18:36:54.69#ibcon#about to read 3, iclass 6, count 2 2006.285.18:36:54.71#ibcon#read 3, iclass 6, count 2 2006.285.18:36:54.71#ibcon#about to read 4, iclass 6, count 2 2006.285.18:36:54.71#ibcon#read 4, iclass 6, count 2 2006.285.18:36:54.71#ibcon#about to read 5, iclass 6, count 2 2006.285.18:36:54.71#ibcon#read 5, iclass 6, count 2 2006.285.18:36:54.71#ibcon#about to read 6, iclass 6, count 2 2006.285.18:36:54.71#ibcon#read 6, iclass 6, count 2 2006.285.18:36:54.71#ibcon#end of sib2, iclass 6, count 2 2006.285.18:36:54.71#ibcon#*mode == 0, iclass 6, count 2 2006.285.18:36:54.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.18:36:54.71#ibcon#[25=AT01-07\r\n] 2006.285.18:36:54.71#ibcon#*before write, iclass 6, count 2 2006.285.18:36:54.71#ibcon#enter sib2, iclass 6, count 2 2006.285.18:36:54.71#ibcon#flushed, iclass 6, count 2 2006.285.18:36:54.71#ibcon#about to write, iclass 6, count 2 2006.285.18:36:54.71#ibcon#wrote, iclass 6, count 2 2006.285.18:36:54.71#ibcon#about to read 3, iclass 6, count 2 2006.285.18:36:54.74#ibcon#read 3, iclass 6, count 2 2006.285.18:36:54.74#ibcon#about to read 4, iclass 6, count 2 2006.285.18:36:54.74#ibcon#read 4, iclass 6, count 2 2006.285.18:36:54.74#ibcon#about to read 5, iclass 6, count 2 2006.285.18:36:54.74#ibcon#read 5, iclass 6, count 2 2006.285.18:36:54.74#ibcon#about to read 6, iclass 6, count 2 2006.285.18:36:54.74#ibcon#read 6, iclass 6, count 2 2006.285.18:36:54.74#ibcon#end of sib2, iclass 6, count 2 2006.285.18:36:54.74#ibcon#*after write, iclass 6, count 2 2006.285.18:36:54.74#ibcon#*before return 0, iclass 6, count 2 2006.285.18:36:54.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:36:54.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:36:54.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.18:36:54.74#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:54.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:36:54.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:36:54.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:36:54.86#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:36:54.86#ibcon#first serial, iclass 6, count 0 2006.285.18:36:54.86#ibcon#enter sib2, iclass 6, count 0 2006.285.18:36:54.86#ibcon#flushed, iclass 6, count 0 2006.285.18:36:54.86#ibcon#about to write, iclass 6, count 0 2006.285.18:36:54.86#ibcon#wrote, iclass 6, count 0 2006.285.18:36:54.86#ibcon#about to read 3, iclass 6, count 0 2006.285.18:36:54.88#ibcon#read 3, iclass 6, count 0 2006.285.18:36:54.88#ibcon#about to read 4, iclass 6, count 0 2006.285.18:36:54.88#ibcon#read 4, iclass 6, count 0 2006.285.18:36:54.88#ibcon#about to read 5, iclass 6, count 0 2006.285.18:36:54.88#ibcon#read 5, iclass 6, count 0 2006.285.18:36:54.88#ibcon#about to read 6, iclass 6, count 0 2006.285.18:36:54.88#ibcon#read 6, iclass 6, count 0 2006.285.18:36:54.88#ibcon#end of sib2, iclass 6, count 0 2006.285.18:36:54.88#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:36:54.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:36:54.88#ibcon#[25=USB\r\n] 2006.285.18:36:54.88#ibcon#*before write, iclass 6, count 0 2006.285.18:36:54.88#ibcon#enter sib2, iclass 6, count 0 2006.285.18:36:54.88#ibcon#flushed, iclass 6, count 0 2006.285.18:36:54.88#ibcon#about to write, iclass 6, count 0 2006.285.18:36:54.88#ibcon#wrote, iclass 6, count 0 2006.285.18:36:54.88#ibcon#about to read 3, iclass 6, count 0 2006.285.18:36:54.91#ibcon#read 3, iclass 6, count 0 2006.285.18:36:54.91#ibcon#about to read 4, iclass 6, count 0 2006.285.18:36:54.91#ibcon#read 4, iclass 6, count 0 2006.285.18:36:54.91#ibcon#about to read 5, iclass 6, count 0 2006.285.18:36:54.91#ibcon#read 5, iclass 6, count 0 2006.285.18:36:54.91#ibcon#about to read 6, iclass 6, count 0 2006.285.18:36:54.91#ibcon#read 6, iclass 6, count 0 2006.285.18:36:54.91#ibcon#end of sib2, iclass 6, count 0 2006.285.18:36:54.91#ibcon#*after write, iclass 6, count 0 2006.285.18:36:54.91#ibcon#*before return 0, iclass 6, count 0 2006.285.18:36:54.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:36:54.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:36:54.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:36:54.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:36:54.91$vck44/valo=2,534.99 2006.285.18:36:54.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.18:36:54.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.18:36:54.91#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:54.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:36:54.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:36:54.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:36:54.91#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:36:54.91#ibcon#first serial, iclass 10, count 0 2006.285.18:36:54.91#ibcon#enter sib2, iclass 10, count 0 2006.285.18:36:54.91#ibcon#flushed, iclass 10, count 0 2006.285.18:36:54.91#ibcon#about to write, iclass 10, count 0 2006.285.18:36:54.91#ibcon#wrote, iclass 10, count 0 2006.285.18:36:54.91#ibcon#about to read 3, iclass 10, count 0 2006.285.18:36:54.93#ibcon#read 3, iclass 10, count 0 2006.285.18:36:54.93#ibcon#about to read 4, iclass 10, count 0 2006.285.18:36:54.93#ibcon#read 4, iclass 10, count 0 2006.285.18:36:54.93#ibcon#about to read 5, iclass 10, count 0 2006.285.18:36:54.93#ibcon#read 5, iclass 10, count 0 2006.285.18:36:54.93#ibcon#about to read 6, iclass 10, count 0 2006.285.18:36:54.93#ibcon#read 6, iclass 10, count 0 2006.285.18:36:54.93#ibcon#end of sib2, iclass 10, count 0 2006.285.18:36:54.93#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:36:54.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:36:54.93#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.18:36:54.93#ibcon#*before write, iclass 10, count 0 2006.285.18:36:54.93#ibcon#enter sib2, iclass 10, count 0 2006.285.18:36:54.93#ibcon#flushed, iclass 10, count 0 2006.285.18:36:54.93#ibcon#about to write, iclass 10, count 0 2006.285.18:36:54.93#ibcon#wrote, iclass 10, count 0 2006.285.18:36:54.93#ibcon#about to read 3, iclass 10, count 0 2006.285.18:36:54.97#ibcon#read 3, iclass 10, count 0 2006.285.18:36:54.97#ibcon#about to read 4, iclass 10, count 0 2006.285.18:36:54.97#ibcon#read 4, iclass 10, count 0 2006.285.18:36:54.97#ibcon#about to read 5, iclass 10, count 0 2006.285.18:36:54.97#ibcon#read 5, iclass 10, count 0 2006.285.18:36:54.97#ibcon#about to read 6, iclass 10, count 0 2006.285.18:36:54.97#ibcon#read 6, iclass 10, count 0 2006.285.18:36:54.97#ibcon#end of sib2, iclass 10, count 0 2006.285.18:36:54.97#ibcon#*after write, iclass 10, count 0 2006.285.18:36:54.97#ibcon#*before return 0, iclass 10, count 0 2006.285.18:36:54.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:36:54.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:36:54.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:36:54.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:36:54.97$vck44/va=2,6 2006.285.18:36:54.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.18:36:54.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.18:36:54.97#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:54.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:36:55.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:36:55.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:36:55.03#ibcon#enter wrdev, iclass 12, count 2 2006.285.18:36:55.03#ibcon#first serial, iclass 12, count 2 2006.285.18:36:55.03#ibcon#enter sib2, iclass 12, count 2 2006.285.18:36:55.03#ibcon#flushed, iclass 12, count 2 2006.285.18:36:55.03#ibcon#about to write, iclass 12, count 2 2006.285.18:36:55.03#ibcon#wrote, iclass 12, count 2 2006.285.18:36:55.03#ibcon#about to read 3, iclass 12, count 2 2006.285.18:36:55.05#ibcon#read 3, iclass 12, count 2 2006.285.18:36:55.05#ibcon#about to read 4, iclass 12, count 2 2006.285.18:36:55.05#ibcon#read 4, iclass 12, count 2 2006.285.18:36:55.05#ibcon#about to read 5, iclass 12, count 2 2006.285.18:36:55.05#ibcon#read 5, iclass 12, count 2 2006.285.18:36:55.05#ibcon#about to read 6, iclass 12, count 2 2006.285.18:36:55.05#ibcon#read 6, iclass 12, count 2 2006.285.18:36:55.05#ibcon#end of sib2, iclass 12, count 2 2006.285.18:36:55.05#ibcon#*mode == 0, iclass 12, count 2 2006.285.18:36:55.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.18:36:55.05#ibcon#[25=AT02-06\r\n] 2006.285.18:36:55.05#ibcon#*before write, iclass 12, count 2 2006.285.18:36:55.05#ibcon#enter sib2, iclass 12, count 2 2006.285.18:36:55.05#ibcon#flushed, iclass 12, count 2 2006.285.18:36:55.05#ibcon#about to write, iclass 12, count 2 2006.285.18:36:55.05#ibcon#wrote, iclass 12, count 2 2006.285.18:36:55.05#ibcon#about to read 3, iclass 12, count 2 2006.285.18:36:55.08#ibcon#read 3, iclass 12, count 2 2006.285.18:36:55.08#ibcon#about to read 4, iclass 12, count 2 2006.285.18:36:55.08#ibcon#read 4, iclass 12, count 2 2006.285.18:36:55.08#ibcon#about to read 5, iclass 12, count 2 2006.285.18:36:55.08#ibcon#read 5, iclass 12, count 2 2006.285.18:36:55.08#ibcon#about to read 6, iclass 12, count 2 2006.285.18:36:55.08#ibcon#read 6, iclass 12, count 2 2006.285.18:36:55.08#ibcon#end of sib2, iclass 12, count 2 2006.285.18:36:55.08#ibcon#*after write, iclass 12, count 2 2006.285.18:36:55.08#ibcon#*before return 0, iclass 12, count 2 2006.285.18:36:55.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:36:55.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:36:55.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.18:36:55.08#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:55.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:36:55.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:36:55.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:36:55.20#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:36:55.20#ibcon#first serial, iclass 12, count 0 2006.285.18:36:55.20#ibcon#enter sib2, iclass 12, count 0 2006.285.18:36:55.20#ibcon#flushed, iclass 12, count 0 2006.285.18:36:55.20#ibcon#about to write, iclass 12, count 0 2006.285.18:36:55.20#ibcon#wrote, iclass 12, count 0 2006.285.18:36:55.20#ibcon#about to read 3, iclass 12, count 0 2006.285.18:36:55.22#ibcon#read 3, iclass 12, count 0 2006.285.18:36:55.22#ibcon#about to read 4, iclass 12, count 0 2006.285.18:36:55.22#ibcon#read 4, iclass 12, count 0 2006.285.18:36:55.22#ibcon#about to read 5, iclass 12, count 0 2006.285.18:36:55.22#ibcon#read 5, iclass 12, count 0 2006.285.18:36:55.22#ibcon#about to read 6, iclass 12, count 0 2006.285.18:36:55.22#ibcon#read 6, iclass 12, count 0 2006.285.18:36:55.22#ibcon#end of sib2, iclass 12, count 0 2006.285.18:36:55.22#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:36:55.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:36:55.22#ibcon#[25=USB\r\n] 2006.285.18:36:55.22#ibcon#*before write, iclass 12, count 0 2006.285.18:36:55.22#ibcon#enter sib2, iclass 12, count 0 2006.285.18:36:55.22#ibcon#flushed, iclass 12, count 0 2006.285.18:36:55.22#ibcon#about to write, iclass 12, count 0 2006.285.18:36:55.22#ibcon#wrote, iclass 12, count 0 2006.285.18:36:55.22#ibcon#about to read 3, iclass 12, count 0 2006.285.18:36:55.25#ibcon#read 3, iclass 12, count 0 2006.285.18:36:55.25#ibcon#about to read 4, iclass 12, count 0 2006.285.18:36:55.25#ibcon#read 4, iclass 12, count 0 2006.285.18:36:55.25#ibcon#about to read 5, iclass 12, count 0 2006.285.18:36:55.25#ibcon#read 5, iclass 12, count 0 2006.285.18:36:55.25#ibcon#about to read 6, iclass 12, count 0 2006.285.18:36:55.25#ibcon#read 6, iclass 12, count 0 2006.285.18:36:55.25#ibcon#end of sib2, iclass 12, count 0 2006.285.18:36:55.25#ibcon#*after write, iclass 12, count 0 2006.285.18:36:55.25#ibcon#*before return 0, iclass 12, count 0 2006.285.18:36:55.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:36:55.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:36:55.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:36:55.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:36:55.25$vck44/valo=3,564.99 2006.285.18:36:55.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.18:36:55.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.18:36:55.25#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:55.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:36:55.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:36:55.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:36:55.25#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:36:55.25#ibcon#first serial, iclass 14, count 0 2006.285.18:36:55.25#ibcon#enter sib2, iclass 14, count 0 2006.285.18:36:55.25#ibcon#flushed, iclass 14, count 0 2006.285.18:36:55.25#ibcon#about to write, iclass 14, count 0 2006.285.18:36:55.25#ibcon#wrote, iclass 14, count 0 2006.285.18:36:55.25#ibcon#about to read 3, iclass 14, count 0 2006.285.18:36:55.27#ibcon#read 3, iclass 14, count 0 2006.285.18:36:55.27#ibcon#about to read 4, iclass 14, count 0 2006.285.18:36:55.27#ibcon#read 4, iclass 14, count 0 2006.285.18:36:55.27#ibcon#about to read 5, iclass 14, count 0 2006.285.18:36:55.27#ibcon#read 5, iclass 14, count 0 2006.285.18:36:55.27#ibcon#about to read 6, iclass 14, count 0 2006.285.18:36:55.27#ibcon#read 6, iclass 14, count 0 2006.285.18:36:55.27#ibcon#end of sib2, iclass 14, count 0 2006.285.18:36:55.27#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:36:55.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:36:55.27#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.18:36:55.27#ibcon#*before write, iclass 14, count 0 2006.285.18:36:55.27#ibcon#enter sib2, iclass 14, count 0 2006.285.18:36:55.27#ibcon#flushed, iclass 14, count 0 2006.285.18:36:55.27#ibcon#about to write, iclass 14, count 0 2006.285.18:36:55.27#ibcon#wrote, iclass 14, count 0 2006.285.18:36:55.27#ibcon#about to read 3, iclass 14, count 0 2006.285.18:36:55.31#ibcon#read 3, iclass 14, count 0 2006.285.18:36:55.31#ibcon#about to read 4, iclass 14, count 0 2006.285.18:36:55.31#ibcon#read 4, iclass 14, count 0 2006.285.18:36:55.31#ibcon#about to read 5, iclass 14, count 0 2006.285.18:36:55.31#ibcon#read 5, iclass 14, count 0 2006.285.18:36:55.31#ibcon#about to read 6, iclass 14, count 0 2006.285.18:36:55.31#ibcon#read 6, iclass 14, count 0 2006.285.18:36:55.31#ibcon#end of sib2, iclass 14, count 0 2006.285.18:36:55.31#ibcon#*after write, iclass 14, count 0 2006.285.18:36:55.31#ibcon#*before return 0, iclass 14, count 0 2006.285.18:36:55.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:36:55.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:36:55.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:36:55.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:36:55.31$vck44/va=3,7 2006.285.18:36:55.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.18:36:55.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.18:36:55.31#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:55.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:36:55.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:36:55.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:36:55.37#ibcon#enter wrdev, iclass 16, count 2 2006.285.18:36:55.37#ibcon#first serial, iclass 16, count 2 2006.285.18:36:55.37#ibcon#enter sib2, iclass 16, count 2 2006.285.18:36:55.37#ibcon#flushed, iclass 16, count 2 2006.285.18:36:55.37#ibcon#about to write, iclass 16, count 2 2006.285.18:36:55.37#ibcon#wrote, iclass 16, count 2 2006.285.18:36:55.37#ibcon#about to read 3, iclass 16, count 2 2006.285.18:36:55.39#ibcon#read 3, iclass 16, count 2 2006.285.18:36:55.39#ibcon#about to read 4, iclass 16, count 2 2006.285.18:36:55.39#ibcon#read 4, iclass 16, count 2 2006.285.18:36:55.39#ibcon#about to read 5, iclass 16, count 2 2006.285.18:36:55.39#ibcon#read 5, iclass 16, count 2 2006.285.18:36:55.39#ibcon#about to read 6, iclass 16, count 2 2006.285.18:36:55.39#ibcon#read 6, iclass 16, count 2 2006.285.18:36:55.39#ibcon#end of sib2, iclass 16, count 2 2006.285.18:36:55.39#ibcon#*mode == 0, iclass 16, count 2 2006.285.18:36:55.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.18:36:55.39#ibcon#[25=AT03-07\r\n] 2006.285.18:36:55.39#ibcon#*before write, iclass 16, count 2 2006.285.18:36:55.39#ibcon#enter sib2, iclass 16, count 2 2006.285.18:36:55.39#ibcon#flushed, iclass 16, count 2 2006.285.18:36:55.39#ibcon#about to write, iclass 16, count 2 2006.285.18:36:55.39#ibcon#wrote, iclass 16, count 2 2006.285.18:36:55.39#ibcon#about to read 3, iclass 16, count 2 2006.285.18:36:55.42#ibcon#read 3, iclass 16, count 2 2006.285.18:36:55.42#ibcon#about to read 4, iclass 16, count 2 2006.285.18:36:55.42#ibcon#read 4, iclass 16, count 2 2006.285.18:36:55.42#ibcon#about to read 5, iclass 16, count 2 2006.285.18:36:55.42#ibcon#read 5, iclass 16, count 2 2006.285.18:36:55.42#ibcon#about to read 6, iclass 16, count 2 2006.285.18:36:55.42#ibcon#read 6, iclass 16, count 2 2006.285.18:36:55.42#ibcon#end of sib2, iclass 16, count 2 2006.285.18:36:55.42#ibcon#*after write, iclass 16, count 2 2006.285.18:36:55.42#ibcon#*before return 0, iclass 16, count 2 2006.285.18:36:55.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:36:55.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:36:55.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.18:36:55.42#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:55.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:36:55.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:36:55.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:36:55.54#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:36:55.54#ibcon#first serial, iclass 16, count 0 2006.285.18:36:55.54#ibcon#enter sib2, iclass 16, count 0 2006.285.18:36:55.54#ibcon#flushed, iclass 16, count 0 2006.285.18:36:55.54#ibcon#about to write, iclass 16, count 0 2006.285.18:36:55.54#ibcon#wrote, iclass 16, count 0 2006.285.18:36:55.54#ibcon#about to read 3, iclass 16, count 0 2006.285.18:36:55.56#ibcon#read 3, iclass 16, count 0 2006.285.18:36:55.56#ibcon#about to read 4, iclass 16, count 0 2006.285.18:36:55.56#ibcon#read 4, iclass 16, count 0 2006.285.18:36:55.56#ibcon#about to read 5, iclass 16, count 0 2006.285.18:36:55.56#ibcon#read 5, iclass 16, count 0 2006.285.18:36:55.56#ibcon#about to read 6, iclass 16, count 0 2006.285.18:36:55.56#ibcon#read 6, iclass 16, count 0 2006.285.18:36:55.56#ibcon#end of sib2, iclass 16, count 0 2006.285.18:36:55.56#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:36:55.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:36:55.56#ibcon#[25=USB\r\n] 2006.285.18:36:55.56#ibcon#*before write, iclass 16, count 0 2006.285.18:36:55.56#ibcon#enter sib2, iclass 16, count 0 2006.285.18:36:55.56#ibcon#flushed, iclass 16, count 0 2006.285.18:36:55.56#ibcon#about to write, iclass 16, count 0 2006.285.18:36:55.56#ibcon#wrote, iclass 16, count 0 2006.285.18:36:55.56#ibcon#about to read 3, iclass 16, count 0 2006.285.18:36:55.59#ibcon#read 3, iclass 16, count 0 2006.285.18:36:55.59#ibcon#about to read 4, iclass 16, count 0 2006.285.18:36:55.59#ibcon#read 4, iclass 16, count 0 2006.285.18:36:55.59#ibcon#about to read 5, iclass 16, count 0 2006.285.18:36:55.59#ibcon#read 5, iclass 16, count 0 2006.285.18:36:55.59#ibcon#about to read 6, iclass 16, count 0 2006.285.18:36:55.59#ibcon#read 6, iclass 16, count 0 2006.285.18:36:55.59#ibcon#end of sib2, iclass 16, count 0 2006.285.18:36:55.59#ibcon#*after write, iclass 16, count 0 2006.285.18:36:55.59#ibcon#*before return 0, iclass 16, count 0 2006.285.18:36:55.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:36:55.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:36:55.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:36:55.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:36:55.59$vck44/valo=4,624.99 2006.285.18:36:55.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.18:36:55.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.18:36:55.59#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:55.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:36:55.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:36:55.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:36:55.59#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:36:55.59#ibcon#first serial, iclass 18, count 0 2006.285.18:36:55.59#ibcon#enter sib2, iclass 18, count 0 2006.285.18:36:55.59#ibcon#flushed, iclass 18, count 0 2006.285.18:36:55.59#ibcon#about to write, iclass 18, count 0 2006.285.18:36:55.59#ibcon#wrote, iclass 18, count 0 2006.285.18:36:55.59#ibcon#about to read 3, iclass 18, count 0 2006.285.18:36:55.61#ibcon#read 3, iclass 18, count 0 2006.285.18:36:55.61#ibcon#about to read 4, iclass 18, count 0 2006.285.18:36:55.61#ibcon#read 4, iclass 18, count 0 2006.285.18:36:55.61#ibcon#about to read 5, iclass 18, count 0 2006.285.18:36:55.61#ibcon#read 5, iclass 18, count 0 2006.285.18:36:55.61#ibcon#about to read 6, iclass 18, count 0 2006.285.18:36:55.61#ibcon#read 6, iclass 18, count 0 2006.285.18:36:55.61#ibcon#end of sib2, iclass 18, count 0 2006.285.18:36:55.61#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:36:55.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:36:55.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.18:36:55.61#ibcon#*before write, iclass 18, count 0 2006.285.18:36:55.61#ibcon#enter sib2, iclass 18, count 0 2006.285.18:36:55.61#ibcon#flushed, iclass 18, count 0 2006.285.18:36:55.61#ibcon#about to write, iclass 18, count 0 2006.285.18:36:55.61#ibcon#wrote, iclass 18, count 0 2006.285.18:36:55.61#ibcon#about to read 3, iclass 18, count 0 2006.285.18:36:55.65#ibcon#read 3, iclass 18, count 0 2006.285.18:36:55.65#ibcon#about to read 4, iclass 18, count 0 2006.285.18:36:55.65#ibcon#read 4, iclass 18, count 0 2006.285.18:36:55.65#ibcon#about to read 5, iclass 18, count 0 2006.285.18:36:55.65#ibcon#read 5, iclass 18, count 0 2006.285.18:36:55.65#ibcon#about to read 6, iclass 18, count 0 2006.285.18:36:55.65#ibcon#read 6, iclass 18, count 0 2006.285.18:36:55.65#ibcon#end of sib2, iclass 18, count 0 2006.285.18:36:55.65#ibcon#*after write, iclass 18, count 0 2006.285.18:36:55.65#ibcon#*before return 0, iclass 18, count 0 2006.285.18:36:55.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:36:55.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:36:55.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:36:55.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:36:55.65$vck44/va=4,6 2006.285.18:36:55.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.18:36:55.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.18:36:55.65#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:55.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:36:55.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:36:55.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:36:55.71#ibcon#enter wrdev, iclass 20, count 2 2006.285.18:36:55.71#ibcon#first serial, iclass 20, count 2 2006.285.18:36:56.03#ibcon#enter sib2, iclass 20, count 2 2006.285.18:36:56.03#ibcon#flushed, iclass 20, count 2 2006.285.18:36:56.03#ibcon#about to write, iclass 20, count 2 2006.285.18:36:56.03#ibcon#wrote, iclass 20, count 2 2006.285.18:36:56.03#ibcon#about to read 3, iclass 20, count 2 2006.285.18:36:56.05#ibcon#read 3, iclass 20, count 2 2006.285.18:36:56.05#ibcon#about to read 4, iclass 20, count 2 2006.285.18:36:56.05#ibcon#read 4, iclass 20, count 2 2006.285.18:36:56.05#ibcon#about to read 5, iclass 20, count 2 2006.285.18:36:56.05#ibcon#read 5, iclass 20, count 2 2006.285.18:36:56.05#ibcon#about to read 6, iclass 20, count 2 2006.285.18:36:56.05#ibcon#read 6, iclass 20, count 2 2006.285.18:36:56.05#ibcon#end of sib2, iclass 20, count 2 2006.285.18:36:56.05#ibcon#*mode == 0, iclass 20, count 2 2006.285.18:36:56.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.18:36:56.05#ibcon#[25=AT04-06\r\n] 2006.285.18:36:56.05#ibcon#*before write, iclass 20, count 2 2006.285.18:36:56.05#ibcon#enter sib2, iclass 20, count 2 2006.285.18:36:56.05#ibcon#flushed, iclass 20, count 2 2006.285.18:36:56.05#ibcon#about to write, iclass 20, count 2 2006.285.18:36:56.05#ibcon#wrote, iclass 20, count 2 2006.285.18:36:56.05#ibcon#about to read 3, iclass 20, count 2 2006.285.18:36:56.08#ibcon#read 3, iclass 20, count 2 2006.285.18:36:56.08#ibcon#about to read 4, iclass 20, count 2 2006.285.18:36:56.08#ibcon#read 4, iclass 20, count 2 2006.285.18:36:56.08#ibcon#about to read 5, iclass 20, count 2 2006.285.18:36:56.08#ibcon#read 5, iclass 20, count 2 2006.285.18:36:56.08#ibcon#about to read 6, iclass 20, count 2 2006.285.18:36:56.08#ibcon#read 6, iclass 20, count 2 2006.285.18:36:56.08#ibcon#end of sib2, iclass 20, count 2 2006.285.18:36:56.08#ibcon#*after write, iclass 20, count 2 2006.285.18:36:56.08#ibcon#*before return 0, iclass 20, count 2 2006.285.18:36:56.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:36:56.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:36:56.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.18:36:56.08#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:56.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:36:56.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:36:56.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:36:56.20#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:36:56.20#ibcon#first serial, iclass 20, count 0 2006.285.18:36:56.20#ibcon#enter sib2, iclass 20, count 0 2006.285.18:36:56.20#ibcon#flushed, iclass 20, count 0 2006.285.18:36:56.20#ibcon#about to write, iclass 20, count 0 2006.285.18:36:56.20#ibcon#wrote, iclass 20, count 0 2006.285.18:36:56.20#ibcon#about to read 3, iclass 20, count 0 2006.285.18:36:56.22#ibcon#read 3, iclass 20, count 0 2006.285.18:36:56.22#ibcon#about to read 4, iclass 20, count 0 2006.285.18:36:56.22#ibcon#read 4, iclass 20, count 0 2006.285.18:36:56.22#ibcon#about to read 5, iclass 20, count 0 2006.285.18:36:56.22#ibcon#read 5, iclass 20, count 0 2006.285.18:36:56.22#ibcon#about to read 6, iclass 20, count 0 2006.285.18:36:56.22#ibcon#read 6, iclass 20, count 0 2006.285.18:36:56.22#ibcon#end of sib2, iclass 20, count 0 2006.285.18:36:56.22#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:36:56.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:36:56.22#ibcon#[25=USB\r\n] 2006.285.18:36:56.22#ibcon#*before write, iclass 20, count 0 2006.285.18:36:56.22#ibcon#enter sib2, iclass 20, count 0 2006.285.18:36:56.22#ibcon#flushed, iclass 20, count 0 2006.285.18:36:56.22#ibcon#about to write, iclass 20, count 0 2006.285.18:36:56.22#ibcon#wrote, iclass 20, count 0 2006.285.18:36:56.22#ibcon#about to read 3, iclass 20, count 0 2006.285.18:36:56.25#ibcon#read 3, iclass 20, count 0 2006.285.18:36:56.25#ibcon#about to read 4, iclass 20, count 0 2006.285.18:36:56.25#ibcon#read 4, iclass 20, count 0 2006.285.18:36:56.25#ibcon#about to read 5, iclass 20, count 0 2006.285.18:36:56.25#ibcon#read 5, iclass 20, count 0 2006.285.18:36:56.25#ibcon#about to read 6, iclass 20, count 0 2006.285.18:36:56.25#ibcon#read 6, iclass 20, count 0 2006.285.18:36:56.25#ibcon#end of sib2, iclass 20, count 0 2006.285.18:36:56.25#ibcon#*after write, iclass 20, count 0 2006.285.18:36:56.25#ibcon#*before return 0, iclass 20, count 0 2006.285.18:36:56.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:36:56.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:36:56.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:36:56.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:36:56.25$vck44/valo=5,734.99 2006.285.18:36:56.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.18:36:56.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.18:36:56.25#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:56.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:36:56.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:36:56.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:36:56.25#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:36:56.25#ibcon#first serial, iclass 22, count 0 2006.285.18:36:56.25#ibcon#enter sib2, iclass 22, count 0 2006.285.18:36:56.25#ibcon#flushed, iclass 22, count 0 2006.285.18:36:56.25#ibcon#about to write, iclass 22, count 0 2006.285.18:36:56.25#ibcon#wrote, iclass 22, count 0 2006.285.18:36:56.25#ibcon#about to read 3, iclass 22, count 0 2006.285.18:36:56.27#ibcon#read 3, iclass 22, count 0 2006.285.18:36:56.27#ibcon#about to read 4, iclass 22, count 0 2006.285.18:36:56.27#ibcon#read 4, iclass 22, count 0 2006.285.18:36:56.27#ibcon#about to read 5, iclass 22, count 0 2006.285.18:36:56.27#ibcon#read 5, iclass 22, count 0 2006.285.18:36:56.27#ibcon#about to read 6, iclass 22, count 0 2006.285.18:36:56.27#ibcon#read 6, iclass 22, count 0 2006.285.18:36:56.27#ibcon#end of sib2, iclass 22, count 0 2006.285.18:36:56.27#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:36:56.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:36:56.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.18:36:56.27#ibcon#*before write, iclass 22, count 0 2006.285.18:36:56.27#ibcon#enter sib2, iclass 22, count 0 2006.285.18:36:56.27#ibcon#flushed, iclass 22, count 0 2006.285.18:36:56.27#ibcon#about to write, iclass 22, count 0 2006.285.18:36:56.27#ibcon#wrote, iclass 22, count 0 2006.285.18:36:56.27#ibcon#about to read 3, iclass 22, count 0 2006.285.18:36:56.31#ibcon#read 3, iclass 22, count 0 2006.285.18:36:56.31#ibcon#about to read 4, iclass 22, count 0 2006.285.18:36:56.31#ibcon#read 4, iclass 22, count 0 2006.285.18:36:56.31#ibcon#about to read 5, iclass 22, count 0 2006.285.18:36:56.31#ibcon#read 5, iclass 22, count 0 2006.285.18:36:56.31#ibcon#about to read 6, iclass 22, count 0 2006.285.18:36:56.31#ibcon#read 6, iclass 22, count 0 2006.285.18:36:56.31#ibcon#end of sib2, iclass 22, count 0 2006.285.18:36:56.31#ibcon#*after write, iclass 22, count 0 2006.285.18:36:56.31#ibcon#*before return 0, iclass 22, count 0 2006.285.18:36:56.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:36:56.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:36:56.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:36:56.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:36:56.31$vck44/va=5,3 2006.285.18:36:56.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.18:36:56.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.18:36:56.31#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:56.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:36:56.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:36:56.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:36:56.37#ibcon#enter wrdev, iclass 24, count 2 2006.285.18:36:56.37#ibcon#first serial, iclass 24, count 2 2006.285.18:36:56.37#ibcon#enter sib2, iclass 24, count 2 2006.285.18:36:56.37#ibcon#flushed, iclass 24, count 2 2006.285.18:36:56.37#ibcon#about to write, iclass 24, count 2 2006.285.18:36:56.37#ibcon#wrote, iclass 24, count 2 2006.285.18:36:56.37#ibcon#about to read 3, iclass 24, count 2 2006.285.18:36:56.39#ibcon#read 3, iclass 24, count 2 2006.285.18:36:56.39#ibcon#about to read 4, iclass 24, count 2 2006.285.18:36:56.39#ibcon#read 4, iclass 24, count 2 2006.285.18:36:56.39#ibcon#about to read 5, iclass 24, count 2 2006.285.18:36:56.39#ibcon#read 5, iclass 24, count 2 2006.285.18:36:56.39#ibcon#about to read 6, iclass 24, count 2 2006.285.18:36:56.39#ibcon#read 6, iclass 24, count 2 2006.285.18:36:56.39#ibcon#end of sib2, iclass 24, count 2 2006.285.18:36:56.39#ibcon#*mode == 0, iclass 24, count 2 2006.285.18:36:56.39#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.18:36:56.39#ibcon#[25=AT05-03\r\n] 2006.285.18:36:56.39#ibcon#*before write, iclass 24, count 2 2006.285.18:36:56.39#ibcon#enter sib2, iclass 24, count 2 2006.285.18:36:56.39#ibcon#flushed, iclass 24, count 2 2006.285.18:36:56.39#ibcon#about to write, iclass 24, count 2 2006.285.18:36:56.39#ibcon#wrote, iclass 24, count 2 2006.285.18:36:56.39#ibcon#about to read 3, iclass 24, count 2 2006.285.18:36:56.42#ibcon#read 3, iclass 24, count 2 2006.285.18:36:56.42#ibcon#about to read 4, iclass 24, count 2 2006.285.18:36:56.42#ibcon#read 4, iclass 24, count 2 2006.285.18:36:56.42#ibcon#about to read 5, iclass 24, count 2 2006.285.18:36:56.42#ibcon#read 5, iclass 24, count 2 2006.285.18:36:56.42#ibcon#about to read 6, iclass 24, count 2 2006.285.18:36:56.42#ibcon#read 6, iclass 24, count 2 2006.285.18:36:56.42#ibcon#end of sib2, iclass 24, count 2 2006.285.18:36:56.42#ibcon#*after write, iclass 24, count 2 2006.285.18:36:56.42#ibcon#*before return 0, iclass 24, count 2 2006.285.18:36:56.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:36:56.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:36:56.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.18:36:56.42#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:56.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:36:56.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:36:56.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:36:56.88#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:36:56.88#ibcon#first serial, iclass 24, count 0 2006.285.18:36:56.88#ibcon#enter sib2, iclass 24, count 0 2006.285.18:36:56.88#ibcon#flushed, iclass 24, count 0 2006.285.18:36:56.88#ibcon#about to write, iclass 24, count 0 2006.285.18:36:56.88#ibcon#wrote, iclass 24, count 0 2006.285.18:36:56.88#ibcon#about to read 3, iclass 24, count 0 2006.285.18:36:56.90#ibcon#read 3, iclass 24, count 0 2006.285.18:36:56.90#ibcon#about to read 4, iclass 24, count 0 2006.285.18:36:56.90#ibcon#read 4, iclass 24, count 0 2006.285.18:36:56.90#ibcon#about to read 5, iclass 24, count 0 2006.285.18:36:56.90#ibcon#read 5, iclass 24, count 0 2006.285.18:36:56.90#ibcon#about to read 6, iclass 24, count 0 2006.285.18:36:56.90#ibcon#read 6, iclass 24, count 0 2006.285.18:36:56.90#ibcon#end of sib2, iclass 24, count 0 2006.285.18:36:56.90#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:36:56.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:36:56.90#ibcon#[25=USB\r\n] 2006.285.18:36:56.90#ibcon#*before write, iclass 24, count 0 2006.285.18:36:56.90#ibcon#enter sib2, iclass 24, count 0 2006.285.18:36:56.90#ibcon#flushed, iclass 24, count 0 2006.285.18:36:56.90#ibcon#about to write, iclass 24, count 0 2006.285.18:36:56.90#ibcon#wrote, iclass 24, count 0 2006.285.18:36:56.90#ibcon#about to read 3, iclass 24, count 0 2006.285.18:36:56.93#ibcon#read 3, iclass 24, count 0 2006.285.18:36:56.93#ibcon#about to read 4, iclass 24, count 0 2006.285.18:36:56.93#ibcon#read 4, iclass 24, count 0 2006.285.18:36:56.93#ibcon#about to read 5, iclass 24, count 0 2006.285.18:36:56.93#ibcon#read 5, iclass 24, count 0 2006.285.18:36:56.93#ibcon#about to read 6, iclass 24, count 0 2006.285.18:36:56.93#ibcon#read 6, iclass 24, count 0 2006.285.18:36:56.93#ibcon#end of sib2, iclass 24, count 0 2006.285.18:36:56.93#ibcon#*after write, iclass 24, count 0 2006.285.18:36:56.93#ibcon#*before return 0, iclass 24, count 0 2006.285.18:36:56.93#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:36:56.93#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:36:56.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:36:56.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:36:56.93$vck44/valo=6,814.99 2006.285.18:36:56.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.18:36:56.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.18:36:56.93#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:56.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:36:56.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:36:56.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:36:56.93#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:36:56.93#ibcon#first serial, iclass 26, count 0 2006.285.18:36:56.93#ibcon#enter sib2, iclass 26, count 0 2006.285.18:36:56.93#ibcon#flushed, iclass 26, count 0 2006.285.18:36:56.93#ibcon#about to write, iclass 26, count 0 2006.285.18:36:56.93#ibcon#wrote, iclass 26, count 0 2006.285.18:36:56.93#ibcon#about to read 3, iclass 26, count 0 2006.285.18:36:56.95#ibcon#read 3, iclass 26, count 0 2006.285.18:36:56.95#ibcon#about to read 4, iclass 26, count 0 2006.285.18:36:56.95#ibcon#read 4, iclass 26, count 0 2006.285.18:36:56.95#ibcon#about to read 5, iclass 26, count 0 2006.285.18:36:56.95#ibcon#read 5, iclass 26, count 0 2006.285.18:36:56.95#ibcon#about to read 6, iclass 26, count 0 2006.285.18:36:56.95#ibcon#read 6, iclass 26, count 0 2006.285.18:36:56.95#ibcon#end of sib2, iclass 26, count 0 2006.285.18:36:56.95#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:36:56.95#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:36:56.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.18:36:56.95#ibcon#*before write, iclass 26, count 0 2006.285.18:36:56.95#ibcon#enter sib2, iclass 26, count 0 2006.285.18:36:56.95#ibcon#flushed, iclass 26, count 0 2006.285.18:36:56.95#ibcon#about to write, iclass 26, count 0 2006.285.18:36:56.95#ibcon#wrote, iclass 26, count 0 2006.285.18:36:56.95#ibcon#about to read 3, iclass 26, count 0 2006.285.18:36:56.99#ibcon#read 3, iclass 26, count 0 2006.285.18:36:56.99#ibcon#about to read 4, iclass 26, count 0 2006.285.18:36:56.99#ibcon#read 4, iclass 26, count 0 2006.285.18:36:56.99#ibcon#about to read 5, iclass 26, count 0 2006.285.18:36:56.99#ibcon#read 5, iclass 26, count 0 2006.285.18:36:56.99#ibcon#about to read 6, iclass 26, count 0 2006.285.18:36:56.99#ibcon#read 6, iclass 26, count 0 2006.285.18:36:56.99#ibcon#end of sib2, iclass 26, count 0 2006.285.18:36:56.99#ibcon#*after write, iclass 26, count 0 2006.285.18:36:56.99#ibcon#*before return 0, iclass 26, count 0 2006.285.18:36:56.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:36:56.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:36:56.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:36:56.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:36:56.99$vck44/va=6,4 2006.285.18:36:56.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.18:36:56.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.18:36:56.99#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:56.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:36:57.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:36:57.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:36:57.05#ibcon#enter wrdev, iclass 28, count 2 2006.285.18:36:57.05#ibcon#first serial, iclass 28, count 2 2006.285.18:36:57.05#ibcon#enter sib2, iclass 28, count 2 2006.285.18:36:57.05#ibcon#flushed, iclass 28, count 2 2006.285.18:36:57.05#ibcon#about to write, iclass 28, count 2 2006.285.18:36:57.05#ibcon#wrote, iclass 28, count 2 2006.285.18:36:57.05#ibcon#about to read 3, iclass 28, count 2 2006.285.18:36:57.07#ibcon#read 3, iclass 28, count 2 2006.285.18:36:57.07#ibcon#about to read 4, iclass 28, count 2 2006.285.18:36:57.07#ibcon#read 4, iclass 28, count 2 2006.285.18:36:57.07#ibcon#about to read 5, iclass 28, count 2 2006.285.18:36:57.07#ibcon#read 5, iclass 28, count 2 2006.285.18:36:57.07#ibcon#about to read 6, iclass 28, count 2 2006.285.18:36:57.07#ibcon#read 6, iclass 28, count 2 2006.285.18:36:57.07#ibcon#end of sib2, iclass 28, count 2 2006.285.18:36:57.07#ibcon#*mode == 0, iclass 28, count 2 2006.285.18:36:57.07#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.18:36:57.07#ibcon#[25=AT06-04\r\n] 2006.285.18:36:57.07#ibcon#*before write, iclass 28, count 2 2006.285.18:36:57.07#ibcon#enter sib2, iclass 28, count 2 2006.285.18:36:57.07#ibcon#flushed, iclass 28, count 2 2006.285.18:36:57.07#ibcon#about to write, iclass 28, count 2 2006.285.18:36:57.07#ibcon#wrote, iclass 28, count 2 2006.285.18:36:57.07#ibcon#about to read 3, iclass 28, count 2 2006.285.18:36:57.10#ibcon#read 3, iclass 28, count 2 2006.285.18:36:57.10#ibcon#about to read 4, iclass 28, count 2 2006.285.18:36:57.10#ibcon#read 4, iclass 28, count 2 2006.285.18:36:57.10#ibcon#about to read 5, iclass 28, count 2 2006.285.18:36:57.10#ibcon#read 5, iclass 28, count 2 2006.285.18:36:57.10#ibcon#about to read 6, iclass 28, count 2 2006.285.18:36:57.10#ibcon#read 6, iclass 28, count 2 2006.285.18:36:57.10#ibcon#end of sib2, iclass 28, count 2 2006.285.18:36:57.10#ibcon#*after write, iclass 28, count 2 2006.285.18:36:57.10#ibcon#*before return 0, iclass 28, count 2 2006.285.18:36:57.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:36:57.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:36:57.10#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.18:36:57.10#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:57.10#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:36:57.22#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:36:57.22#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:36:57.22#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:36:57.22#ibcon#first serial, iclass 28, count 0 2006.285.18:36:57.22#ibcon#enter sib2, iclass 28, count 0 2006.285.18:36:57.22#ibcon#flushed, iclass 28, count 0 2006.285.18:36:57.22#ibcon#about to write, iclass 28, count 0 2006.285.18:36:57.22#ibcon#wrote, iclass 28, count 0 2006.285.18:36:57.22#ibcon#about to read 3, iclass 28, count 0 2006.285.18:36:57.24#ibcon#read 3, iclass 28, count 0 2006.285.18:36:57.24#ibcon#about to read 4, iclass 28, count 0 2006.285.18:36:57.24#ibcon#read 4, iclass 28, count 0 2006.285.18:36:57.24#ibcon#about to read 5, iclass 28, count 0 2006.285.18:36:57.24#ibcon#read 5, iclass 28, count 0 2006.285.18:36:57.24#ibcon#about to read 6, iclass 28, count 0 2006.285.18:36:57.24#ibcon#read 6, iclass 28, count 0 2006.285.18:36:57.24#ibcon#end of sib2, iclass 28, count 0 2006.285.18:36:57.24#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:36:57.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:36:57.24#ibcon#[25=USB\r\n] 2006.285.18:36:57.24#ibcon#*before write, iclass 28, count 0 2006.285.18:36:57.24#ibcon#enter sib2, iclass 28, count 0 2006.285.18:36:57.24#ibcon#flushed, iclass 28, count 0 2006.285.18:36:57.24#ibcon#about to write, iclass 28, count 0 2006.285.18:36:57.24#ibcon#wrote, iclass 28, count 0 2006.285.18:36:57.24#ibcon#about to read 3, iclass 28, count 0 2006.285.18:36:57.27#ibcon#read 3, iclass 28, count 0 2006.285.18:36:57.27#ibcon#about to read 4, iclass 28, count 0 2006.285.18:36:57.27#ibcon#read 4, iclass 28, count 0 2006.285.18:36:57.27#ibcon#about to read 5, iclass 28, count 0 2006.285.18:36:57.27#ibcon#read 5, iclass 28, count 0 2006.285.18:36:57.27#ibcon#about to read 6, iclass 28, count 0 2006.285.18:36:57.27#ibcon#read 6, iclass 28, count 0 2006.285.18:36:57.27#ibcon#end of sib2, iclass 28, count 0 2006.285.18:36:57.27#ibcon#*after write, iclass 28, count 0 2006.285.18:36:57.27#ibcon#*before return 0, iclass 28, count 0 2006.285.18:36:57.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:36:57.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:36:57.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:36:57.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:36:57.27$vck44/valo=7,864.99 2006.285.18:36:57.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.18:36:57.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.18:36:57.27#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:57.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:36:57.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:36:57.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:36:57.27#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:36:57.27#ibcon#first serial, iclass 30, count 0 2006.285.18:36:57.27#ibcon#enter sib2, iclass 30, count 0 2006.285.18:36:57.27#ibcon#flushed, iclass 30, count 0 2006.285.18:36:57.27#ibcon#about to write, iclass 30, count 0 2006.285.18:36:57.27#ibcon#wrote, iclass 30, count 0 2006.285.18:36:57.27#ibcon#about to read 3, iclass 30, count 0 2006.285.18:36:57.29#ibcon#read 3, iclass 30, count 0 2006.285.18:36:57.34#ibcon#about to read 4, iclass 30, count 0 2006.285.18:36:57.34#ibcon#read 4, iclass 30, count 0 2006.285.18:36:57.34#ibcon#about to read 5, iclass 30, count 0 2006.285.18:36:57.34#ibcon#read 5, iclass 30, count 0 2006.285.18:36:57.34#ibcon#about to read 6, iclass 30, count 0 2006.285.18:36:57.34#ibcon#read 6, iclass 30, count 0 2006.285.18:36:57.34#ibcon#end of sib2, iclass 30, count 0 2006.285.18:36:57.34#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:36:57.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:36:57.34#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.18:36:57.34#ibcon#*before write, iclass 30, count 0 2006.285.18:36:57.34#ibcon#enter sib2, iclass 30, count 0 2006.285.18:36:57.34#ibcon#flushed, iclass 30, count 0 2006.285.18:36:57.34#ibcon#about to write, iclass 30, count 0 2006.285.18:36:57.34#ibcon#wrote, iclass 30, count 0 2006.285.18:36:57.34#ibcon#about to read 3, iclass 30, count 0 2006.285.18:36:57.38#ibcon#read 3, iclass 30, count 0 2006.285.18:36:57.38#ibcon#about to read 4, iclass 30, count 0 2006.285.18:36:57.38#ibcon#read 4, iclass 30, count 0 2006.285.18:36:57.38#ibcon#about to read 5, iclass 30, count 0 2006.285.18:36:57.38#ibcon#read 5, iclass 30, count 0 2006.285.18:36:57.38#ibcon#about to read 6, iclass 30, count 0 2006.285.18:36:57.38#ibcon#read 6, iclass 30, count 0 2006.285.18:36:57.38#ibcon#end of sib2, iclass 30, count 0 2006.285.18:36:57.38#ibcon#*after write, iclass 30, count 0 2006.285.18:36:57.38#ibcon#*before return 0, iclass 30, count 0 2006.285.18:36:57.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:36:57.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:36:57.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:36:57.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:36:57.38$vck44/va=7,4 2006.285.18:36:57.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.18:36:57.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.18:36:57.38#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:57.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:36:57.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:36:57.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:36:57.38#ibcon#enter wrdev, iclass 32, count 2 2006.285.18:36:57.38#ibcon#first serial, iclass 32, count 2 2006.285.18:36:57.38#ibcon#enter sib2, iclass 32, count 2 2006.285.18:36:57.38#ibcon#flushed, iclass 32, count 2 2006.285.18:36:57.38#ibcon#about to write, iclass 32, count 2 2006.285.18:36:57.38#ibcon#wrote, iclass 32, count 2 2006.285.18:36:57.38#ibcon#about to read 3, iclass 32, count 2 2006.285.18:36:57.40#ibcon#read 3, iclass 32, count 2 2006.285.18:36:57.40#ibcon#about to read 4, iclass 32, count 2 2006.285.18:36:57.40#ibcon#read 4, iclass 32, count 2 2006.285.18:36:57.40#ibcon#about to read 5, iclass 32, count 2 2006.285.18:36:57.40#ibcon#read 5, iclass 32, count 2 2006.285.18:36:57.40#ibcon#about to read 6, iclass 32, count 2 2006.285.18:36:57.40#ibcon#read 6, iclass 32, count 2 2006.285.18:36:57.40#ibcon#end of sib2, iclass 32, count 2 2006.285.18:36:57.40#ibcon#*mode == 0, iclass 32, count 2 2006.285.18:36:57.40#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.18:36:57.40#ibcon#[25=AT07-04\r\n] 2006.285.18:36:57.40#ibcon#*before write, iclass 32, count 2 2006.285.18:36:57.40#ibcon#enter sib2, iclass 32, count 2 2006.285.18:36:57.40#ibcon#flushed, iclass 32, count 2 2006.285.18:36:57.40#ibcon#about to write, iclass 32, count 2 2006.285.18:36:57.40#ibcon#wrote, iclass 32, count 2 2006.285.18:36:57.40#ibcon#about to read 3, iclass 32, count 2 2006.285.18:36:57.43#ibcon#read 3, iclass 32, count 2 2006.285.18:36:57.43#ibcon#about to read 4, iclass 32, count 2 2006.285.18:36:57.43#ibcon#read 4, iclass 32, count 2 2006.285.18:36:57.43#ibcon#about to read 5, iclass 32, count 2 2006.285.18:36:57.43#ibcon#read 5, iclass 32, count 2 2006.285.18:36:57.43#ibcon#about to read 6, iclass 32, count 2 2006.285.18:36:57.43#ibcon#read 6, iclass 32, count 2 2006.285.18:36:57.43#ibcon#end of sib2, iclass 32, count 2 2006.285.18:36:57.43#ibcon#*after write, iclass 32, count 2 2006.285.18:36:57.43#ibcon#*before return 0, iclass 32, count 2 2006.285.18:36:57.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:36:57.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:36:57.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.18:36:57.43#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:57.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:36:57.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:36:57.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:36:57.55#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:36:57.55#ibcon#first serial, iclass 32, count 0 2006.285.18:36:57.55#ibcon#enter sib2, iclass 32, count 0 2006.285.18:36:57.55#ibcon#flushed, iclass 32, count 0 2006.285.18:36:57.55#ibcon#about to write, iclass 32, count 0 2006.285.18:36:57.55#ibcon#wrote, iclass 32, count 0 2006.285.18:36:57.55#ibcon#about to read 3, iclass 32, count 0 2006.285.18:36:57.57#ibcon#read 3, iclass 32, count 0 2006.285.18:36:57.57#ibcon#about to read 4, iclass 32, count 0 2006.285.18:36:57.57#ibcon#read 4, iclass 32, count 0 2006.285.18:36:57.57#ibcon#about to read 5, iclass 32, count 0 2006.285.18:36:57.57#ibcon#read 5, iclass 32, count 0 2006.285.18:36:57.57#ibcon#about to read 6, iclass 32, count 0 2006.285.18:36:57.57#ibcon#read 6, iclass 32, count 0 2006.285.18:36:57.57#ibcon#end of sib2, iclass 32, count 0 2006.285.18:36:57.57#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:36:57.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:36:57.57#ibcon#[25=USB\r\n] 2006.285.18:36:57.57#ibcon#*before write, iclass 32, count 0 2006.285.18:36:57.57#ibcon#enter sib2, iclass 32, count 0 2006.285.18:36:57.57#ibcon#flushed, iclass 32, count 0 2006.285.18:36:57.57#ibcon#about to write, iclass 32, count 0 2006.285.18:36:57.57#ibcon#wrote, iclass 32, count 0 2006.285.18:36:57.57#ibcon#about to read 3, iclass 32, count 0 2006.285.18:36:57.60#ibcon#read 3, iclass 32, count 0 2006.285.18:36:57.60#ibcon#about to read 4, iclass 32, count 0 2006.285.18:36:57.60#ibcon#read 4, iclass 32, count 0 2006.285.18:36:57.60#ibcon#about to read 5, iclass 32, count 0 2006.285.18:36:57.60#ibcon#read 5, iclass 32, count 0 2006.285.18:36:57.60#ibcon#about to read 6, iclass 32, count 0 2006.285.18:36:57.60#ibcon#read 6, iclass 32, count 0 2006.285.18:36:57.60#ibcon#end of sib2, iclass 32, count 0 2006.285.18:36:57.60#ibcon#*after write, iclass 32, count 0 2006.285.18:36:57.60#ibcon#*before return 0, iclass 32, count 0 2006.285.18:36:57.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:36:57.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:36:57.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:36:57.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:36:57.60$vck44/valo=8,884.99 2006.285.18:36:57.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.18:36:57.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.18:36:57.60#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:57.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:36:57.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:36:57.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:36:57.60#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:36:57.60#ibcon#first serial, iclass 34, count 0 2006.285.18:36:57.60#ibcon#enter sib2, iclass 34, count 0 2006.285.18:36:57.60#ibcon#flushed, iclass 34, count 0 2006.285.18:36:57.60#ibcon#about to write, iclass 34, count 0 2006.285.18:36:57.60#ibcon#wrote, iclass 34, count 0 2006.285.18:36:57.60#ibcon#about to read 3, iclass 34, count 0 2006.285.18:36:57.62#ibcon#read 3, iclass 34, count 0 2006.285.18:36:57.62#ibcon#about to read 4, iclass 34, count 0 2006.285.18:36:57.62#ibcon#read 4, iclass 34, count 0 2006.285.18:36:57.62#ibcon#about to read 5, iclass 34, count 0 2006.285.18:36:57.62#ibcon#read 5, iclass 34, count 0 2006.285.18:36:57.62#ibcon#about to read 6, iclass 34, count 0 2006.285.18:36:57.62#ibcon#read 6, iclass 34, count 0 2006.285.18:36:57.62#ibcon#end of sib2, iclass 34, count 0 2006.285.18:36:57.62#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:36:57.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:36:57.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.18:36:57.62#ibcon#*before write, iclass 34, count 0 2006.285.18:36:57.62#ibcon#enter sib2, iclass 34, count 0 2006.285.18:36:57.62#ibcon#flushed, iclass 34, count 0 2006.285.18:36:57.62#ibcon#about to write, iclass 34, count 0 2006.285.18:36:57.62#ibcon#wrote, iclass 34, count 0 2006.285.18:36:57.62#ibcon#about to read 3, iclass 34, count 0 2006.285.18:36:57.66#ibcon#read 3, iclass 34, count 0 2006.285.18:36:57.66#ibcon#about to read 4, iclass 34, count 0 2006.285.18:36:57.66#ibcon#read 4, iclass 34, count 0 2006.285.18:36:57.66#ibcon#about to read 5, iclass 34, count 0 2006.285.18:36:57.66#ibcon#read 5, iclass 34, count 0 2006.285.18:36:57.66#ibcon#about to read 6, iclass 34, count 0 2006.285.18:36:57.66#ibcon#read 6, iclass 34, count 0 2006.285.18:36:57.66#ibcon#end of sib2, iclass 34, count 0 2006.285.18:36:57.66#ibcon#*after write, iclass 34, count 0 2006.285.18:36:57.66#ibcon#*before return 0, iclass 34, count 0 2006.285.18:36:57.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:36:57.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:36:57.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:36:57.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:36:57.66$vck44/va=8,3 2006.285.18:36:57.66#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.18:36:57.66#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.18:36:57.66#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:57.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:36:57.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:36:57.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:36:57.72#ibcon#enter wrdev, iclass 36, count 2 2006.285.18:36:57.72#ibcon#first serial, iclass 36, count 2 2006.285.18:36:57.72#ibcon#enter sib2, iclass 36, count 2 2006.285.18:36:57.72#ibcon#flushed, iclass 36, count 2 2006.285.18:36:57.72#ibcon#about to write, iclass 36, count 2 2006.285.18:36:57.72#ibcon#wrote, iclass 36, count 2 2006.285.18:36:57.72#ibcon#about to read 3, iclass 36, count 2 2006.285.18:36:57.74#ibcon#read 3, iclass 36, count 2 2006.285.18:36:57.74#ibcon#about to read 4, iclass 36, count 2 2006.285.18:36:57.74#ibcon#read 4, iclass 36, count 2 2006.285.18:36:57.74#ibcon#about to read 5, iclass 36, count 2 2006.285.18:36:57.74#ibcon#read 5, iclass 36, count 2 2006.285.18:36:57.74#ibcon#about to read 6, iclass 36, count 2 2006.285.18:36:57.74#ibcon#read 6, iclass 36, count 2 2006.285.18:36:57.74#ibcon#end of sib2, iclass 36, count 2 2006.285.18:36:57.74#ibcon#*mode == 0, iclass 36, count 2 2006.285.18:36:57.74#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.18:36:57.74#ibcon#[25=AT08-03\r\n] 2006.285.18:36:57.74#ibcon#*before write, iclass 36, count 2 2006.285.18:36:57.74#ibcon#enter sib2, iclass 36, count 2 2006.285.18:36:57.74#ibcon#flushed, iclass 36, count 2 2006.285.18:36:57.74#ibcon#about to write, iclass 36, count 2 2006.285.18:36:57.74#ibcon#wrote, iclass 36, count 2 2006.285.18:36:57.74#ibcon#about to read 3, iclass 36, count 2 2006.285.18:36:57.77#ibcon#read 3, iclass 36, count 2 2006.285.18:36:57.77#ibcon#about to read 4, iclass 36, count 2 2006.285.18:36:57.84#ibcon#read 4, iclass 36, count 2 2006.285.18:36:57.84#ibcon#about to read 5, iclass 36, count 2 2006.285.18:36:57.84#ibcon#read 5, iclass 36, count 2 2006.285.18:36:57.84#ibcon#about to read 6, iclass 36, count 2 2006.285.18:36:57.84#ibcon#read 6, iclass 36, count 2 2006.285.18:36:57.84#ibcon#end of sib2, iclass 36, count 2 2006.285.18:36:57.84#ibcon#*after write, iclass 36, count 2 2006.285.18:36:57.84#ibcon#*before return 0, iclass 36, count 2 2006.285.18:36:57.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:36:57.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:36:57.84#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.18:36:57.84#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:57.84#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:36:57.96#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:36:57.96#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:36:57.96#ibcon#enter wrdev, iclass 36, count 0 2006.285.18:36:57.96#ibcon#first serial, iclass 36, count 0 2006.285.18:36:57.96#ibcon#enter sib2, iclass 36, count 0 2006.285.18:36:57.96#ibcon#flushed, iclass 36, count 0 2006.285.18:36:57.96#ibcon#about to write, iclass 36, count 0 2006.285.18:36:57.96#ibcon#wrote, iclass 36, count 0 2006.285.18:36:57.96#ibcon#about to read 3, iclass 36, count 0 2006.285.18:36:57.98#ibcon#read 3, iclass 36, count 0 2006.285.18:36:57.98#ibcon#about to read 4, iclass 36, count 0 2006.285.18:36:57.98#ibcon#read 4, iclass 36, count 0 2006.285.18:36:57.98#ibcon#about to read 5, iclass 36, count 0 2006.285.18:36:57.98#ibcon#read 5, iclass 36, count 0 2006.285.18:36:57.98#ibcon#about to read 6, iclass 36, count 0 2006.285.18:36:57.98#ibcon#read 6, iclass 36, count 0 2006.285.18:36:57.98#ibcon#end of sib2, iclass 36, count 0 2006.285.18:36:57.98#ibcon#*mode == 0, iclass 36, count 0 2006.285.18:36:57.98#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.18:36:57.98#ibcon#[25=USB\r\n] 2006.285.18:36:57.98#ibcon#*before write, iclass 36, count 0 2006.285.18:36:57.98#ibcon#enter sib2, iclass 36, count 0 2006.285.18:36:57.98#ibcon#flushed, iclass 36, count 0 2006.285.18:36:57.98#ibcon#about to write, iclass 36, count 0 2006.285.18:36:57.98#ibcon#wrote, iclass 36, count 0 2006.285.18:36:57.98#ibcon#about to read 3, iclass 36, count 0 2006.285.18:36:58.01#ibcon#read 3, iclass 36, count 0 2006.285.18:36:58.01#ibcon#about to read 4, iclass 36, count 0 2006.285.18:36:58.01#ibcon#read 4, iclass 36, count 0 2006.285.18:36:58.01#ibcon#about to read 5, iclass 36, count 0 2006.285.18:36:58.01#ibcon#read 5, iclass 36, count 0 2006.285.18:36:58.01#ibcon#about to read 6, iclass 36, count 0 2006.285.18:36:58.01#ibcon#read 6, iclass 36, count 0 2006.285.18:36:58.01#ibcon#end of sib2, iclass 36, count 0 2006.285.18:36:58.01#ibcon#*after write, iclass 36, count 0 2006.285.18:36:58.01#ibcon#*before return 0, iclass 36, count 0 2006.285.18:36:58.01#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:36:58.01#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:36:58.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.18:36:58.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.18:36:58.01$vck44/vblo=1,629.99 2006.285.18:36:58.01#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.18:36:58.01#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.18:36:58.01#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:58.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:36:58.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:36:58.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:36:58.01#ibcon#enter wrdev, iclass 38, count 0 2006.285.18:36:58.01#ibcon#first serial, iclass 38, count 0 2006.285.18:36:58.01#ibcon#enter sib2, iclass 38, count 0 2006.285.18:36:58.01#ibcon#flushed, iclass 38, count 0 2006.285.18:36:58.01#ibcon#about to write, iclass 38, count 0 2006.285.18:36:58.01#ibcon#wrote, iclass 38, count 0 2006.285.18:36:58.01#ibcon#about to read 3, iclass 38, count 0 2006.285.18:36:58.03#ibcon#read 3, iclass 38, count 0 2006.285.18:36:58.03#ibcon#about to read 4, iclass 38, count 0 2006.285.18:36:58.03#ibcon#read 4, iclass 38, count 0 2006.285.18:36:58.03#ibcon#about to read 5, iclass 38, count 0 2006.285.18:36:58.03#ibcon#read 5, iclass 38, count 0 2006.285.18:36:58.03#ibcon#about to read 6, iclass 38, count 0 2006.285.18:36:58.03#ibcon#read 6, iclass 38, count 0 2006.285.18:36:58.03#ibcon#end of sib2, iclass 38, count 0 2006.285.18:36:58.03#ibcon#*mode == 0, iclass 38, count 0 2006.285.18:36:58.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.18:36:58.03#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.18:36:58.03#ibcon#*before write, iclass 38, count 0 2006.285.18:36:58.03#ibcon#enter sib2, iclass 38, count 0 2006.285.18:36:58.03#ibcon#flushed, iclass 38, count 0 2006.285.18:36:58.03#ibcon#about to write, iclass 38, count 0 2006.285.18:36:58.03#ibcon#wrote, iclass 38, count 0 2006.285.18:36:58.03#ibcon#about to read 3, iclass 38, count 0 2006.285.18:36:58.07#ibcon#read 3, iclass 38, count 0 2006.285.18:36:58.07#ibcon#about to read 4, iclass 38, count 0 2006.285.18:36:58.07#ibcon#read 4, iclass 38, count 0 2006.285.18:36:58.07#ibcon#about to read 5, iclass 38, count 0 2006.285.18:36:58.07#ibcon#read 5, iclass 38, count 0 2006.285.18:36:58.07#ibcon#about to read 6, iclass 38, count 0 2006.285.18:36:58.07#ibcon#read 6, iclass 38, count 0 2006.285.18:36:58.07#ibcon#end of sib2, iclass 38, count 0 2006.285.18:36:58.07#ibcon#*after write, iclass 38, count 0 2006.285.18:36:58.07#ibcon#*before return 0, iclass 38, count 0 2006.285.18:36:58.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:36:58.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:36:58.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.18:36:58.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.18:36:58.07$vck44/vb=1,4 2006.285.18:36:58.07#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.18:36:58.07#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.18:36:58.07#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:58.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:36:58.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:36:58.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:36:58.07#ibcon#enter wrdev, iclass 40, count 2 2006.285.18:36:58.07#ibcon#first serial, iclass 40, count 2 2006.285.18:36:58.07#ibcon#enter sib2, iclass 40, count 2 2006.285.18:36:58.07#ibcon#flushed, iclass 40, count 2 2006.285.18:36:58.07#ibcon#about to write, iclass 40, count 2 2006.285.18:36:58.07#ibcon#wrote, iclass 40, count 2 2006.285.18:36:58.07#ibcon#about to read 3, iclass 40, count 2 2006.285.18:36:58.09#ibcon#read 3, iclass 40, count 2 2006.285.18:36:58.09#ibcon#about to read 4, iclass 40, count 2 2006.285.18:36:58.09#ibcon#read 4, iclass 40, count 2 2006.285.18:36:58.09#ibcon#about to read 5, iclass 40, count 2 2006.285.18:36:58.09#ibcon#read 5, iclass 40, count 2 2006.285.18:36:58.09#ibcon#about to read 6, iclass 40, count 2 2006.285.18:36:58.09#ibcon#read 6, iclass 40, count 2 2006.285.18:36:58.09#ibcon#end of sib2, iclass 40, count 2 2006.285.18:36:58.09#ibcon#*mode == 0, iclass 40, count 2 2006.285.18:36:58.09#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.18:36:58.09#ibcon#[27=AT01-04\r\n] 2006.285.18:36:58.09#ibcon#*before write, iclass 40, count 2 2006.285.18:36:58.09#ibcon#enter sib2, iclass 40, count 2 2006.285.18:36:58.09#ibcon#flushed, iclass 40, count 2 2006.285.18:36:58.09#ibcon#about to write, iclass 40, count 2 2006.285.18:36:58.09#ibcon#wrote, iclass 40, count 2 2006.285.18:36:58.09#ibcon#about to read 3, iclass 40, count 2 2006.285.18:36:58.12#ibcon#read 3, iclass 40, count 2 2006.285.18:36:58.12#ibcon#about to read 4, iclass 40, count 2 2006.285.18:36:58.12#ibcon#read 4, iclass 40, count 2 2006.285.18:36:58.12#ibcon#about to read 5, iclass 40, count 2 2006.285.18:36:58.12#ibcon#read 5, iclass 40, count 2 2006.285.18:36:58.12#ibcon#about to read 6, iclass 40, count 2 2006.285.18:36:58.12#ibcon#read 6, iclass 40, count 2 2006.285.18:36:58.12#ibcon#end of sib2, iclass 40, count 2 2006.285.18:36:58.12#ibcon#*after write, iclass 40, count 2 2006.285.18:36:58.12#ibcon#*before return 0, iclass 40, count 2 2006.285.18:36:58.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:36:58.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:36:58.12#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.18:36:58.12#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:58.12#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:36:58.24#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:36:58.24#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:36:58.24#ibcon#enter wrdev, iclass 40, count 0 2006.285.18:36:58.24#ibcon#first serial, iclass 40, count 0 2006.285.18:36:58.24#ibcon#enter sib2, iclass 40, count 0 2006.285.18:36:58.24#ibcon#flushed, iclass 40, count 0 2006.285.18:36:58.24#ibcon#about to write, iclass 40, count 0 2006.285.18:36:58.24#ibcon#wrote, iclass 40, count 0 2006.285.18:36:58.24#ibcon#about to read 3, iclass 40, count 0 2006.285.18:36:58.26#ibcon#read 3, iclass 40, count 0 2006.285.18:36:58.26#ibcon#about to read 4, iclass 40, count 0 2006.285.18:36:58.26#ibcon#read 4, iclass 40, count 0 2006.285.18:36:58.26#ibcon#about to read 5, iclass 40, count 0 2006.285.18:36:58.26#ibcon#read 5, iclass 40, count 0 2006.285.18:36:58.26#ibcon#about to read 6, iclass 40, count 0 2006.285.18:36:58.26#ibcon#read 6, iclass 40, count 0 2006.285.18:36:58.26#ibcon#end of sib2, iclass 40, count 0 2006.285.18:36:58.26#ibcon#*mode == 0, iclass 40, count 0 2006.285.18:36:58.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.18:36:58.26#ibcon#[27=USB\r\n] 2006.285.18:36:58.26#ibcon#*before write, iclass 40, count 0 2006.285.18:36:58.26#ibcon#enter sib2, iclass 40, count 0 2006.285.18:36:58.26#ibcon#flushed, iclass 40, count 0 2006.285.18:36:58.26#ibcon#about to write, iclass 40, count 0 2006.285.18:36:58.26#ibcon#wrote, iclass 40, count 0 2006.285.18:36:58.26#ibcon#about to read 3, iclass 40, count 0 2006.285.18:36:58.29#ibcon#read 3, iclass 40, count 0 2006.285.18:36:58.29#ibcon#about to read 4, iclass 40, count 0 2006.285.18:36:58.29#ibcon#read 4, iclass 40, count 0 2006.285.18:36:58.29#ibcon#about to read 5, iclass 40, count 0 2006.285.18:36:58.29#ibcon#read 5, iclass 40, count 0 2006.285.18:36:58.29#ibcon#about to read 6, iclass 40, count 0 2006.285.18:36:58.29#ibcon#read 6, iclass 40, count 0 2006.285.18:36:58.29#ibcon#end of sib2, iclass 40, count 0 2006.285.18:36:58.29#ibcon#*after write, iclass 40, count 0 2006.285.18:36:58.29#ibcon#*before return 0, iclass 40, count 0 2006.285.18:36:58.29#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:36:58.29#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:36:58.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.18:36:58.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.18:36:58.29$vck44/vblo=2,634.99 2006.285.18:36:58.29#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.18:36:58.29#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.18:36:58.29#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:58.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:36:58.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:36:58.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:36:58.29#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:36:58.29#ibcon#first serial, iclass 4, count 0 2006.285.18:36:58.29#ibcon#enter sib2, iclass 4, count 0 2006.285.18:36:58.29#ibcon#flushed, iclass 4, count 0 2006.285.18:36:58.29#ibcon#about to write, iclass 4, count 0 2006.285.18:36:58.29#ibcon#wrote, iclass 4, count 0 2006.285.18:36:58.29#ibcon#about to read 3, iclass 4, count 0 2006.285.18:36:58.31#ibcon#read 3, iclass 4, count 0 2006.285.18:36:58.31#ibcon#about to read 4, iclass 4, count 0 2006.285.18:36:58.31#ibcon#read 4, iclass 4, count 0 2006.285.18:36:58.31#ibcon#about to read 5, iclass 4, count 0 2006.285.18:36:58.31#ibcon#read 5, iclass 4, count 0 2006.285.18:36:58.31#ibcon#about to read 6, iclass 4, count 0 2006.285.18:36:58.31#ibcon#read 6, iclass 4, count 0 2006.285.18:36:58.31#ibcon#end of sib2, iclass 4, count 0 2006.285.18:36:58.31#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:36:58.31#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:36:58.31#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.18:36:58.31#ibcon#*before write, iclass 4, count 0 2006.285.18:36:58.31#ibcon#enter sib2, iclass 4, count 0 2006.285.18:36:58.31#ibcon#flushed, iclass 4, count 0 2006.285.18:36:58.31#ibcon#about to write, iclass 4, count 0 2006.285.18:36:58.31#ibcon#wrote, iclass 4, count 0 2006.285.18:36:58.31#ibcon#about to read 3, iclass 4, count 0 2006.285.18:36:58.35#ibcon#read 3, iclass 4, count 0 2006.285.18:36:58.35#ibcon#about to read 4, iclass 4, count 0 2006.285.18:36:58.35#ibcon#read 4, iclass 4, count 0 2006.285.18:36:58.35#ibcon#about to read 5, iclass 4, count 0 2006.285.18:36:58.35#ibcon#read 5, iclass 4, count 0 2006.285.18:36:58.35#ibcon#about to read 6, iclass 4, count 0 2006.285.18:36:58.35#ibcon#read 6, iclass 4, count 0 2006.285.18:36:58.35#ibcon#end of sib2, iclass 4, count 0 2006.285.18:36:58.35#ibcon#*after write, iclass 4, count 0 2006.285.18:36:58.35#ibcon#*before return 0, iclass 4, count 0 2006.285.18:36:58.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:36:58.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:36:58.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:36:58.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:36:58.35$vck44/vb=2,5 2006.285.18:36:58.35#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.18:36:58.35#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.18:36:58.35#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:58.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:36:58.41#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:36:58.41#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:36:58.41#ibcon#enter wrdev, iclass 6, count 2 2006.285.18:36:58.41#ibcon#first serial, iclass 6, count 2 2006.285.18:36:58.41#ibcon#enter sib2, iclass 6, count 2 2006.285.18:36:58.41#ibcon#flushed, iclass 6, count 2 2006.285.18:36:58.41#ibcon#about to write, iclass 6, count 2 2006.285.18:36:58.41#ibcon#wrote, iclass 6, count 2 2006.285.18:36:58.41#ibcon#about to read 3, iclass 6, count 2 2006.285.18:36:58.43#ibcon#read 3, iclass 6, count 2 2006.285.18:36:58.43#ibcon#about to read 4, iclass 6, count 2 2006.285.18:36:58.43#ibcon#read 4, iclass 6, count 2 2006.285.18:36:58.43#ibcon#about to read 5, iclass 6, count 2 2006.285.18:36:58.43#ibcon#read 5, iclass 6, count 2 2006.285.18:36:58.43#ibcon#about to read 6, iclass 6, count 2 2006.285.18:36:58.43#ibcon#read 6, iclass 6, count 2 2006.285.18:36:58.43#ibcon#end of sib2, iclass 6, count 2 2006.285.18:36:58.43#ibcon#*mode == 0, iclass 6, count 2 2006.285.18:36:58.43#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.18:36:58.43#ibcon#[27=AT02-05\r\n] 2006.285.18:36:58.43#ibcon#*before write, iclass 6, count 2 2006.285.18:36:58.43#ibcon#enter sib2, iclass 6, count 2 2006.285.18:36:58.43#ibcon#flushed, iclass 6, count 2 2006.285.18:36:58.43#ibcon#about to write, iclass 6, count 2 2006.285.18:36:58.43#ibcon#wrote, iclass 6, count 2 2006.285.18:36:58.43#ibcon#about to read 3, iclass 6, count 2 2006.285.18:36:58.46#ibcon#read 3, iclass 6, count 2 2006.285.18:36:58.46#ibcon#about to read 4, iclass 6, count 2 2006.285.18:36:58.46#ibcon#read 4, iclass 6, count 2 2006.285.18:36:58.46#ibcon#about to read 5, iclass 6, count 2 2006.285.18:36:58.46#ibcon#read 5, iclass 6, count 2 2006.285.18:36:58.46#ibcon#about to read 6, iclass 6, count 2 2006.285.18:36:58.46#ibcon#read 6, iclass 6, count 2 2006.285.18:36:58.46#ibcon#end of sib2, iclass 6, count 2 2006.285.18:36:58.46#ibcon#*after write, iclass 6, count 2 2006.285.18:36:58.46#ibcon#*before return 0, iclass 6, count 2 2006.285.18:36:58.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:36:58.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:36:58.46#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.18:36:58.46#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:58.46#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:36:58.58#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:36:58.58#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:36:58.58#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:36:58.58#ibcon#first serial, iclass 6, count 0 2006.285.18:36:58.58#ibcon#enter sib2, iclass 6, count 0 2006.285.18:36:58.58#ibcon#flushed, iclass 6, count 0 2006.285.18:36:58.58#ibcon#about to write, iclass 6, count 0 2006.285.18:36:58.58#ibcon#wrote, iclass 6, count 0 2006.285.18:36:58.58#ibcon#about to read 3, iclass 6, count 0 2006.285.18:36:58.60#ibcon#read 3, iclass 6, count 0 2006.285.18:36:58.60#ibcon#about to read 4, iclass 6, count 0 2006.285.18:36:58.60#ibcon#read 4, iclass 6, count 0 2006.285.18:36:58.60#ibcon#about to read 5, iclass 6, count 0 2006.285.18:36:58.60#ibcon#read 5, iclass 6, count 0 2006.285.18:36:58.60#ibcon#about to read 6, iclass 6, count 0 2006.285.18:36:58.60#ibcon#read 6, iclass 6, count 0 2006.285.18:36:58.60#ibcon#end of sib2, iclass 6, count 0 2006.285.18:36:58.60#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:36:58.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:36:58.60#ibcon#[27=USB\r\n] 2006.285.18:36:58.60#ibcon#*before write, iclass 6, count 0 2006.285.18:36:58.60#ibcon#enter sib2, iclass 6, count 0 2006.285.18:36:58.60#ibcon#flushed, iclass 6, count 0 2006.285.18:36:58.60#ibcon#about to write, iclass 6, count 0 2006.285.18:36:58.60#ibcon#wrote, iclass 6, count 0 2006.285.18:36:58.60#ibcon#about to read 3, iclass 6, count 0 2006.285.18:36:58.63#ibcon#read 3, iclass 6, count 0 2006.285.18:36:58.63#ibcon#about to read 4, iclass 6, count 0 2006.285.18:36:58.63#ibcon#read 4, iclass 6, count 0 2006.285.18:36:58.63#ibcon#about to read 5, iclass 6, count 0 2006.285.18:36:58.63#ibcon#read 5, iclass 6, count 0 2006.285.18:36:58.63#ibcon#about to read 6, iclass 6, count 0 2006.285.18:36:58.63#ibcon#read 6, iclass 6, count 0 2006.285.18:36:58.63#ibcon#end of sib2, iclass 6, count 0 2006.285.18:36:58.63#ibcon#*after write, iclass 6, count 0 2006.285.18:36:58.63#ibcon#*before return 0, iclass 6, count 0 2006.285.18:36:58.63#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:36:58.63#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:36:58.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:36:58.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:36:58.63$vck44/vblo=3,649.99 2006.285.18:36:58.63#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.18:36:58.63#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.18:36:58.63#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:58.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:36:58.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:36:58.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:36:58.63#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:36:58.63#ibcon#first serial, iclass 10, count 0 2006.285.18:36:58.63#ibcon#enter sib2, iclass 10, count 0 2006.285.18:36:58.63#ibcon#flushed, iclass 10, count 0 2006.285.18:36:58.63#ibcon#about to write, iclass 10, count 0 2006.285.18:36:58.63#ibcon#wrote, iclass 10, count 0 2006.285.18:36:58.63#ibcon#about to read 3, iclass 10, count 0 2006.285.18:36:58.65#ibcon#read 3, iclass 10, count 0 2006.285.18:36:58.65#ibcon#about to read 4, iclass 10, count 0 2006.285.18:36:58.65#ibcon#read 4, iclass 10, count 0 2006.285.18:36:58.65#ibcon#about to read 5, iclass 10, count 0 2006.285.18:36:58.65#ibcon#read 5, iclass 10, count 0 2006.285.18:36:58.65#ibcon#about to read 6, iclass 10, count 0 2006.285.18:36:58.65#ibcon#read 6, iclass 10, count 0 2006.285.18:36:58.65#ibcon#end of sib2, iclass 10, count 0 2006.285.18:36:58.65#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:36:58.65#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:36:58.65#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.18:36:58.65#ibcon#*before write, iclass 10, count 0 2006.285.18:36:58.65#ibcon#enter sib2, iclass 10, count 0 2006.285.18:36:58.65#ibcon#flushed, iclass 10, count 0 2006.285.18:36:58.65#ibcon#about to write, iclass 10, count 0 2006.285.18:36:58.65#ibcon#wrote, iclass 10, count 0 2006.285.18:36:58.65#ibcon#about to read 3, iclass 10, count 0 2006.285.18:36:58.69#ibcon#read 3, iclass 10, count 0 2006.285.18:36:58.69#ibcon#about to read 4, iclass 10, count 0 2006.285.18:36:58.69#ibcon#read 4, iclass 10, count 0 2006.285.18:36:58.69#ibcon#about to read 5, iclass 10, count 0 2006.285.18:36:58.69#ibcon#read 5, iclass 10, count 0 2006.285.18:36:58.69#ibcon#about to read 6, iclass 10, count 0 2006.285.18:36:58.69#ibcon#read 6, iclass 10, count 0 2006.285.18:36:58.69#ibcon#end of sib2, iclass 10, count 0 2006.285.18:36:58.69#ibcon#*after write, iclass 10, count 0 2006.285.18:36:58.69#ibcon#*before return 0, iclass 10, count 0 2006.285.18:36:58.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:36:58.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:36:58.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:36:58.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:36:58.69$vck44/vb=3,4 2006.285.18:36:58.69#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.18:36:58.69#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.18:36:58.69#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:58.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:36:58.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:36:58.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:36:58.75#ibcon#enter wrdev, iclass 12, count 2 2006.285.18:36:58.75#ibcon#first serial, iclass 12, count 2 2006.285.18:36:58.75#ibcon#enter sib2, iclass 12, count 2 2006.285.18:36:58.75#ibcon#flushed, iclass 12, count 2 2006.285.18:36:58.75#ibcon#about to write, iclass 12, count 2 2006.285.18:36:58.75#ibcon#wrote, iclass 12, count 2 2006.285.18:36:58.75#ibcon#about to read 3, iclass 12, count 2 2006.285.18:36:58.77#ibcon#read 3, iclass 12, count 2 2006.285.18:36:58.88#ibcon#about to read 4, iclass 12, count 2 2006.285.18:36:58.88#ibcon#read 4, iclass 12, count 2 2006.285.18:36:58.88#ibcon#about to read 5, iclass 12, count 2 2006.285.18:36:58.88#ibcon#read 5, iclass 12, count 2 2006.285.18:36:58.88#ibcon#about to read 6, iclass 12, count 2 2006.285.18:36:58.88#ibcon#read 6, iclass 12, count 2 2006.285.18:36:58.88#ibcon#end of sib2, iclass 12, count 2 2006.285.18:36:58.88#ibcon#*mode == 0, iclass 12, count 2 2006.285.18:36:58.88#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.18:36:58.88#ibcon#[27=AT03-04\r\n] 2006.285.18:36:58.88#ibcon#*before write, iclass 12, count 2 2006.285.18:36:58.88#ibcon#enter sib2, iclass 12, count 2 2006.285.18:36:58.88#ibcon#flushed, iclass 12, count 2 2006.285.18:36:58.88#ibcon#about to write, iclass 12, count 2 2006.285.18:36:58.88#ibcon#wrote, iclass 12, count 2 2006.285.18:36:58.88#ibcon#about to read 3, iclass 12, count 2 2006.285.18:36:58.91#ibcon#read 3, iclass 12, count 2 2006.285.18:36:58.91#ibcon#about to read 4, iclass 12, count 2 2006.285.18:36:58.91#ibcon#read 4, iclass 12, count 2 2006.285.18:36:58.91#ibcon#about to read 5, iclass 12, count 2 2006.285.18:36:58.91#ibcon#read 5, iclass 12, count 2 2006.285.18:36:58.91#ibcon#about to read 6, iclass 12, count 2 2006.285.18:36:58.91#ibcon#read 6, iclass 12, count 2 2006.285.18:36:58.91#ibcon#end of sib2, iclass 12, count 2 2006.285.18:36:58.91#ibcon#*after write, iclass 12, count 2 2006.285.18:36:58.91#ibcon#*before return 0, iclass 12, count 2 2006.285.18:36:58.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:36:58.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:36:58.91#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.18:36:58.91#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:58.91#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:36:59.03#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:36:59.03#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:36:59.03#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:36:59.03#ibcon#first serial, iclass 12, count 0 2006.285.18:36:59.03#ibcon#enter sib2, iclass 12, count 0 2006.285.18:36:59.03#ibcon#flushed, iclass 12, count 0 2006.285.18:36:59.03#ibcon#about to write, iclass 12, count 0 2006.285.18:36:59.03#ibcon#wrote, iclass 12, count 0 2006.285.18:36:59.03#ibcon#about to read 3, iclass 12, count 0 2006.285.18:36:59.05#ibcon#read 3, iclass 12, count 0 2006.285.18:36:59.05#ibcon#about to read 4, iclass 12, count 0 2006.285.18:36:59.05#ibcon#read 4, iclass 12, count 0 2006.285.18:36:59.05#ibcon#about to read 5, iclass 12, count 0 2006.285.18:36:59.05#ibcon#read 5, iclass 12, count 0 2006.285.18:36:59.05#ibcon#about to read 6, iclass 12, count 0 2006.285.18:36:59.05#ibcon#read 6, iclass 12, count 0 2006.285.18:36:59.05#ibcon#end of sib2, iclass 12, count 0 2006.285.18:36:59.05#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:36:59.05#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:36:59.05#ibcon#[27=USB\r\n] 2006.285.18:36:59.05#ibcon#*before write, iclass 12, count 0 2006.285.18:36:59.05#ibcon#enter sib2, iclass 12, count 0 2006.285.18:36:59.05#ibcon#flushed, iclass 12, count 0 2006.285.18:36:59.05#ibcon#about to write, iclass 12, count 0 2006.285.18:36:59.05#ibcon#wrote, iclass 12, count 0 2006.285.18:36:59.05#ibcon#about to read 3, iclass 12, count 0 2006.285.18:36:59.08#ibcon#read 3, iclass 12, count 0 2006.285.18:36:59.08#ibcon#about to read 4, iclass 12, count 0 2006.285.18:36:59.08#ibcon#read 4, iclass 12, count 0 2006.285.18:36:59.08#ibcon#about to read 5, iclass 12, count 0 2006.285.18:36:59.08#ibcon#read 5, iclass 12, count 0 2006.285.18:36:59.08#ibcon#about to read 6, iclass 12, count 0 2006.285.18:36:59.08#ibcon#read 6, iclass 12, count 0 2006.285.18:36:59.08#ibcon#end of sib2, iclass 12, count 0 2006.285.18:36:59.08#ibcon#*after write, iclass 12, count 0 2006.285.18:36:59.08#ibcon#*before return 0, iclass 12, count 0 2006.285.18:36:59.08#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:36:59.08#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:36:59.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:36:59.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:36:59.08$vck44/vblo=4,679.99 2006.285.18:36:59.08#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.18:36:59.08#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.18:36:59.08#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:59.08#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:36:59.08#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:36:59.08#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:36:59.08#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:36:59.08#ibcon#first serial, iclass 14, count 0 2006.285.18:36:59.08#ibcon#enter sib2, iclass 14, count 0 2006.285.18:36:59.08#ibcon#flushed, iclass 14, count 0 2006.285.18:36:59.08#ibcon#about to write, iclass 14, count 0 2006.285.18:36:59.08#ibcon#wrote, iclass 14, count 0 2006.285.18:36:59.08#ibcon#about to read 3, iclass 14, count 0 2006.285.18:36:59.10#ibcon#read 3, iclass 14, count 0 2006.285.18:36:59.10#ibcon#about to read 4, iclass 14, count 0 2006.285.18:36:59.10#ibcon#read 4, iclass 14, count 0 2006.285.18:36:59.10#ibcon#about to read 5, iclass 14, count 0 2006.285.18:36:59.10#ibcon#read 5, iclass 14, count 0 2006.285.18:36:59.10#ibcon#about to read 6, iclass 14, count 0 2006.285.18:36:59.10#ibcon#read 6, iclass 14, count 0 2006.285.18:36:59.10#ibcon#end of sib2, iclass 14, count 0 2006.285.18:36:59.10#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:36:59.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:36:59.10#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.18:36:59.10#ibcon#*before write, iclass 14, count 0 2006.285.18:36:59.10#ibcon#enter sib2, iclass 14, count 0 2006.285.18:36:59.10#ibcon#flushed, iclass 14, count 0 2006.285.18:36:59.10#ibcon#about to write, iclass 14, count 0 2006.285.18:36:59.10#ibcon#wrote, iclass 14, count 0 2006.285.18:36:59.10#ibcon#about to read 3, iclass 14, count 0 2006.285.18:36:59.14#ibcon#read 3, iclass 14, count 0 2006.285.18:36:59.14#ibcon#about to read 4, iclass 14, count 0 2006.285.18:36:59.14#ibcon#read 4, iclass 14, count 0 2006.285.18:36:59.14#ibcon#about to read 5, iclass 14, count 0 2006.285.18:36:59.14#ibcon#read 5, iclass 14, count 0 2006.285.18:36:59.14#ibcon#about to read 6, iclass 14, count 0 2006.285.18:36:59.14#ibcon#read 6, iclass 14, count 0 2006.285.18:36:59.14#ibcon#end of sib2, iclass 14, count 0 2006.285.18:36:59.14#ibcon#*after write, iclass 14, count 0 2006.285.18:36:59.14#ibcon#*before return 0, iclass 14, count 0 2006.285.18:36:59.14#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:36:59.14#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:36:59.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:36:59.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:36:59.14$vck44/vb=4,5 2006.285.18:36:59.14#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.18:36:59.14#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.18:36:59.14#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:59.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:36:59.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:36:59.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:36:59.20#ibcon#enter wrdev, iclass 16, count 2 2006.285.18:36:59.20#ibcon#first serial, iclass 16, count 2 2006.285.18:36:59.20#ibcon#enter sib2, iclass 16, count 2 2006.285.18:36:59.20#ibcon#flushed, iclass 16, count 2 2006.285.18:36:59.20#ibcon#about to write, iclass 16, count 2 2006.285.18:36:59.20#ibcon#wrote, iclass 16, count 2 2006.285.18:36:59.20#ibcon#about to read 3, iclass 16, count 2 2006.285.18:36:59.22#ibcon#read 3, iclass 16, count 2 2006.285.18:36:59.22#ibcon#about to read 4, iclass 16, count 2 2006.285.18:36:59.22#ibcon#read 4, iclass 16, count 2 2006.285.18:36:59.22#ibcon#about to read 5, iclass 16, count 2 2006.285.18:36:59.22#ibcon#read 5, iclass 16, count 2 2006.285.18:36:59.22#ibcon#about to read 6, iclass 16, count 2 2006.285.18:36:59.22#ibcon#read 6, iclass 16, count 2 2006.285.18:36:59.22#ibcon#end of sib2, iclass 16, count 2 2006.285.18:36:59.22#ibcon#*mode == 0, iclass 16, count 2 2006.285.18:36:59.22#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.18:36:59.22#ibcon#[27=AT04-05\r\n] 2006.285.18:36:59.22#ibcon#*before write, iclass 16, count 2 2006.285.18:36:59.22#ibcon#enter sib2, iclass 16, count 2 2006.285.18:36:59.22#ibcon#flushed, iclass 16, count 2 2006.285.18:36:59.22#ibcon#about to write, iclass 16, count 2 2006.285.18:36:59.22#ibcon#wrote, iclass 16, count 2 2006.285.18:36:59.22#ibcon#about to read 3, iclass 16, count 2 2006.285.18:36:59.25#ibcon#read 3, iclass 16, count 2 2006.285.18:36:59.25#ibcon#about to read 4, iclass 16, count 2 2006.285.18:36:59.25#ibcon#read 4, iclass 16, count 2 2006.285.18:36:59.25#ibcon#about to read 5, iclass 16, count 2 2006.285.18:36:59.25#ibcon#read 5, iclass 16, count 2 2006.285.18:36:59.25#ibcon#about to read 6, iclass 16, count 2 2006.285.18:36:59.25#ibcon#read 6, iclass 16, count 2 2006.285.18:36:59.25#ibcon#end of sib2, iclass 16, count 2 2006.285.18:36:59.25#ibcon#*after write, iclass 16, count 2 2006.285.18:36:59.25#ibcon#*before return 0, iclass 16, count 2 2006.285.18:36:59.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:36:59.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:36:59.25#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.18:36:59.25#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:59.25#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:36:59.37#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:36:59.37#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:36:59.37#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:36:59.37#ibcon#first serial, iclass 16, count 0 2006.285.18:36:59.37#ibcon#enter sib2, iclass 16, count 0 2006.285.18:36:59.37#ibcon#flushed, iclass 16, count 0 2006.285.18:36:59.37#ibcon#about to write, iclass 16, count 0 2006.285.18:36:59.37#ibcon#wrote, iclass 16, count 0 2006.285.18:36:59.37#ibcon#about to read 3, iclass 16, count 0 2006.285.18:36:59.39#ibcon#read 3, iclass 16, count 0 2006.285.18:36:59.39#ibcon#about to read 4, iclass 16, count 0 2006.285.18:36:59.39#ibcon#read 4, iclass 16, count 0 2006.285.18:36:59.39#ibcon#about to read 5, iclass 16, count 0 2006.285.18:36:59.39#ibcon#read 5, iclass 16, count 0 2006.285.18:36:59.39#ibcon#about to read 6, iclass 16, count 0 2006.285.18:36:59.39#ibcon#read 6, iclass 16, count 0 2006.285.18:36:59.39#ibcon#end of sib2, iclass 16, count 0 2006.285.18:36:59.39#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:36:59.39#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:36:59.39#ibcon#[27=USB\r\n] 2006.285.18:36:59.39#ibcon#*before write, iclass 16, count 0 2006.285.18:36:59.39#ibcon#enter sib2, iclass 16, count 0 2006.285.18:36:59.39#ibcon#flushed, iclass 16, count 0 2006.285.18:36:59.39#ibcon#about to write, iclass 16, count 0 2006.285.18:36:59.39#ibcon#wrote, iclass 16, count 0 2006.285.18:36:59.39#ibcon#about to read 3, iclass 16, count 0 2006.285.18:36:59.42#ibcon#read 3, iclass 16, count 0 2006.285.18:36:59.42#ibcon#about to read 4, iclass 16, count 0 2006.285.18:36:59.42#ibcon#read 4, iclass 16, count 0 2006.285.18:36:59.42#ibcon#about to read 5, iclass 16, count 0 2006.285.18:36:59.42#ibcon#read 5, iclass 16, count 0 2006.285.18:36:59.42#ibcon#about to read 6, iclass 16, count 0 2006.285.18:36:59.42#ibcon#read 6, iclass 16, count 0 2006.285.18:36:59.42#ibcon#end of sib2, iclass 16, count 0 2006.285.18:36:59.42#ibcon#*after write, iclass 16, count 0 2006.285.18:36:59.42#ibcon#*before return 0, iclass 16, count 0 2006.285.18:36:59.42#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:36:59.42#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:36:59.42#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:36:59.42#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:36:59.42$vck44/vblo=5,709.99 2006.285.18:36:59.42#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.18:36:59.42#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.18:36:59.42#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:59.42#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:36:59.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:36:59.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:36:59.42#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:36:59.42#ibcon#first serial, iclass 18, count 0 2006.285.18:36:59.42#ibcon#enter sib2, iclass 18, count 0 2006.285.18:36:59.42#ibcon#flushed, iclass 18, count 0 2006.285.18:36:59.42#ibcon#about to write, iclass 18, count 0 2006.285.18:36:59.42#ibcon#wrote, iclass 18, count 0 2006.285.18:36:59.42#ibcon#about to read 3, iclass 18, count 0 2006.285.18:36:59.44#ibcon#read 3, iclass 18, count 0 2006.285.18:36:59.44#ibcon#about to read 4, iclass 18, count 0 2006.285.18:36:59.44#ibcon#read 4, iclass 18, count 0 2006.285.18:36:59.44#ibcon#about to read 5, iclass 18, count 0 2006.285.18:36:59.44#ibcon#read 5, iclass 18, count 0 2006.285.18:36:59.44#ibcon#about to read 6, iclass 18, count 0 2006.285.18:36:59.44#ibcon#read 6, iclass 18, count 0 2006.285.18:36:59.44#ibcon#end of sib2, iclass 18, count 0 2006.285.18:36:59.44#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:36:59.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:36:59.44#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.18:36:59.44#ibcon#*before write, iclass 18, count 0 2006.285.18:36:59.44#ibcon#enter sib2, iclass 18, count 0 2006.285.18:36:59.44#ibcon#flushed, iclass 18, count 0 2006.285.18:36:59.44#ibcon#about to write, iclass 18, count 0 2006.285.18:36:59.44#ibcon#wrote, iclass 18, count 0 2006.285.18:36:59.44#ibcon#about to read 3, iclass 18, count 0 2006.285.18:36:59.48#ibcon#read 3, iclass 18, count 0 2006.285.18:36:59.48#ibcon#about to read 4, iclass 18, count 0 2006.285.18:36:59.48#ibcon#read 4, iclass 18, count 0 2006.285.18:36:59.48#ibcon#about to read 5, iclass 18, count 0 2006.285.18:36:59.48#ibcon#read 5, iclass 18, count 0 2006.285.18:36:59.48#ibcon#about to read 6, iclass 18, count 0 2006.285.18:36:59.48#ibcon#read 6, iclass 18, count 0 2006.285.18:36:59.48#ibcon#end of sib2, iclass 18, count 0 2006.285.18:36:59.48#ibcon#*after write, iclass 18, count 0 2006.285.18:36:59.48#ibcon#*before return 0, iclass 18, count 0 2006.285.18:36:59.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:36:59.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:36:59.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:36:59.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:36:59.48$vck44/vb=5,4 2006.285.18:36:59.48#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.18:36:59.48#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.18:36:59.48#ibcon#ireg 11 cls_cnt 2 2006.285.18:36:59.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:36:59.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:36:59.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:36:59.54#ibcon#enter wrdev, iclass 20, count 2 2006.285.18:36:59.54#ibcon#first serial, iclass 20, count 2 2006.285.18:36:59.54#ibcon#enter sib2, iclass 20, count 2 2006.285.18:36:59.54#ibcon#flushed, iclass 20, count 2 2006.285.18:36:59.54#ibcon#about to write, iclass 20, count 2 2006.285.18:36:59.54#ibcon#wrote, iclass 20, count 2 2006.285.18:36:59.54#ibcon#about to read 3, iclass 20, count 2 2006.285.18:36:59.56#ibcon#read 3, iclass 20, count 2 2006.285.18:36:59.56#ibcon#about to read 4, iclass 20, count 2 2006.285.18:36:59.56#ibcon#read 4, iclass 20, count 2 2006.285.18:36:59.56#ibcon#about to read 5, iclass 20, count 2 2006.285.18:36:59.56#ibcon#read 5, iclass 20, count 2 2006.285.18:36:59.56#ibcon#about to read 6, iclass 20, count 2 2006.285.18:36:59.56#ibcon#read 6, iclass 20, count 2 2006.285.18:36:59.56#ibcon#end of sib2, iclass 20, count 2 2006.285.18:36:59.56#ibcon#*mode == 0, iclass 20, count 2 2006.285.18:36:59.56#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.18:36:59.56#ibcon#[27=AT05-04\r\n] 2006.285.18:36:59.56#ibcon#*before write, iclass 20, count 2 2006.285.18:36:59.56#ibcon#enter sib2, iclass 20, count 2 2006.285.18:36:59.56#ibcon#flushed, iclass 20, count 2 2006.285.18:36:59.56#ibcon#about to write, iclass 20, count 2 2006.285.18:36:59.56#ibcon#wrote, iclass 20, count 2 2006.285.18:36:59.56#ibcon#about to read 3, iclass 20, count 2 2006.285.18:36:59.59#ibcon#read 3, iclass 20, count 2 2006.285.18:36:59.59#ibcon#about to read 4, iclass 20, count 2 2006.285.18:36:59.59#ibcon#read 4, iclass 20, count 2 2006.285.18:36:59.59#ibcon#about to read 5, iclass 20, count 2 2006.285.18:36:59.59#ibcon#read 5, iclass 20, count 2 2006.285.18:36:59.59#ibcon#about to read 6, iclass 20, count 2 2006.285.18:36:59.59#ibcon#read 6, iclass 20, count 2 2006.285.18:36:59.59#ibcon#end of sib2, iclass 20, count 2 2006.285.18:36:59.59#ibcon#*after write, iclass 20, count 2 2006.285.18:36:59.59#ibcon#*before return 0, iclass 20, count 2 2006.285.18:36:59.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:36:59.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:36:59.59#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.18:36:59.59#ibcon#ireg 7 cls_cnt 0 2006.285.18:36:59.59#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:36:59.71#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:36:59.71#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:36:59.71#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:36:59.71#ibcon#first serial, iclass 20, count 0 2006.285.18:36:59.71#ibcon#enter sib2, iclass 20, count 0 2006.285.18:36:59.71#ibcon#flushed, iclass 20, count 0 2006.285.18:36:59.71#ibcon#about to write, iclass 20, count 0 2006.285.18:36:59.71#ibcon#wrote, iclass 20, count 0 2006.285.18:36:59.71#ibcon#about to read 3, iclass 20, count 0 2006.285.18:36:59.73#ibcon#read 3, iclass 20, count 0 2006.285.18:36:59.73#ibcon#about to read 4, iclass 20, count 0 2006.285.18:36:59.73#ibcon#read 4, iclass 20, count 0 2006.285.18:36:59.73#ibcon#about to read 5, iclass 20, count 0 2006.285.18:36:59.73#ibcon#read 5, iclass 20, count 0 2006.285.18:36:59.73#ibcon#about to read 6, iclass 20, count 0 2006.285.18:36:59.73#ibcon#read 6, iclass 20, count 0 2006.285.18:36:59.73#ibcon#end of sib2, iclass 20, count 0 2006.285.18:36:59.73#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:36:59.73#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:36:59.73#ibcon#[27=USB\r\n] 2006.285.18:36:59.73#ibcon#*before write, iclass 20, count 0 2006.285.18:36:59.73#ibcon#enter sib2, iclass 20, count 0 2006.285.18:36:59.73#ibcon#flushed, iclass 20, count 0 2006.285.18:36:59.73#ibcon#about to write, iclass 20, count 0 2006.285.18:36:59.73#ibcon#wrote, iclass 20, count 0 2006.285.18:36:59.73#ibcon#about to read 3, iclass 20, count 0 2006.285.18:36:59.76#ibcon#read 3, iclass 20, count 0 2006.285.18:36:59.76#ibcon#about to read 4, iclass 20, count 0 2006.285.18:36:59.76#ibcon#read 4, iclass 20, count 0 2006.285.18:36:59.76#ibcon#about to read 5, iclass 20, count 0 2006.285.18:36:59.76#ibcon#read 5, iclass 20, count 0 2006.285.18:36:59.76#ibcon#about to read 6, iclass 20, count 0 2006.285.18:36:59.76#ibcon#read 6, iclass 20, count 0 2006.285.18:36:59.76#ibcon#end of sib2, iclass 20, count 0 2006.285.18:36:59.76#ibcon#*after write, iclass 20, count 0 2006.285.18:36:59.76#ibcon#*before return 0, iclass 20, count 0 2006.285.18:36:59.76#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:36:59.76#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:36:59.76#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:36:59.76#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:36:59.76$vck44/vblo=6,719.99 2006.285.18:36:59.76#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.18:36:59.76#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.18:36:59.76#ibcon#ireg 17 cls_cnt 0 2006.285.18:36:59.76#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:36:59.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:36:59.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:36:59.76#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:36:59.76#ibcon#first serial, iclass 22, count 0 2006.285.18:36:59.76#ibcon#enter sib2, iclass 22, count 0 2006.285.18:36:59.76#ibcon#flushed, iclass 22, count 0 2006.285.18:36:59.76#ibcon#about to write, iclass 22, count 0 2006.285.18:36:59.76#ibcon#wrote, iclass 22, count 0 2006.285.18:36:59.76#ibcon#about to read 3, iclass 22, count 0 2006.285.18:36:59.78#ibcon#read 3, iclass 22, count 0 2006.285.18:37:00.23#ibcon#about to read 4, iclass 22, count 0 2006.285.18:37:00.23#ibcon#read 4, iclass 22, count 0 2006.285.18:37:00.23#ibcon#about to read 5, iclass 22, count 0 2006.285.18:37:00.23#ibcon#read 5, iclass 22, count 0 2006.285.18:37:00.23#ibcon#about to read 6, iclass 22, count 0 2006.285.18:37:00.23#ibcon#read 6, iclass 22, count 0 2006.285.18:37:00.23#ibcon#end of sib2, iclass 22, count 0 2006.285.18:37:00.23#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:37:00.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:37:00.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.18:37:00.23#ibcon#*before write, iclass 22, count 0 2006.285.18:37:00.23#ibcon#enter sib2, iclass 22, count 0 2006.285.18:37:00.23#ibcon#flushed, iclass 22, count 0 2006.285.18:37:00.23#ibcon#about to write, iclass 22, count 0 2006.285.18:37:00.23#ibcon#wrote, iclass 22, count 0 2006.285.18:37:00.24#ibcon#about to read 3, iclass 22, count 0 2006.285.18:37:00.28#ibcon#read 3, iclass 22, count 0 2006.285.18:37:00.28#ibcon#about to read 4, iclass 22, count 0 2006.285.18:37:00.28#ibcon#read 4, iclass 22, count 0 2006.285.18:37:00.28#ibcon#about to read 5, iclass 22, count 0 2006.285.18:37:00.28#ibcon#read 5, iclass 22, count 0 2006.285.18:37:00.28#ibcon#about to read 6, iclass 22, count 0 2006.285.18:37:00.28#ibcon#read 6, iclass 22, count 0 2006.285.18:37:00.28#ibcon#end of sib2, iclass 22, count 0 2006.285.18:37:00.28#ibcon#*after write, iclass 22, count 0 2006.285.18:37:00.28#ibcon#*before return 0, iclass 22, count 0 2006.285.18:37:00.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:37:00.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:37:00.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:37:00.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:37:00.28$vck44/vb=6,3 2006.285.18:37:00.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.18:37:00.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.18:37:00.28#ibcon#ireg 11 cls_cnt 2 2006.285.18:37:00.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:37:00.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:37:00.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:37:00.28#ibcon#enter wrdev, iclass 24, count 2 2006.285.18:37:00.28#ibcon#first serial, iclass 24, count 2 2006.285.18:37:00.28#ibcon#enter sib2, iclass 24, count 2 2006.285.18:37:00.28#ibcon#flushed, iclass 24, count 2 2006.285.18:37:00.28#ibcon#about to write, iclass 24, count 2 2006.285.18:37:00.28#ibcon#wrote, iclass 24, count 2 2006.285.18:37:00.28#ibcon#about to read 3, iclass 24, count 2 2006.285.18:37:00.30#ibcon#read 3, iclass 24, count 2 2006.285.18:37:00.30#ibcon#about to read 4, iclass 24, count 2 2006.285.18:37:00.30#ibcon#read 4, iclass 24, count 2 2006.285.18:37:00.30#ibcon#about to read 5, iclass 24, count 2 2006.285.18:37:00.30#ibcon#read 5, iclass 24, count 2 2006.285.18:37:00.30#ibcon#about to read 6, iclass 24, count 2 2006.285.18:37:00.30#ibcon#read 6, iclass 24, count 2 2006.285.18:37:00.30#ibcon#end of sib2, iclass 24, count 2 2006.285.18:37:00.30#ibcon#*mode == 0, iclass 24, count 2 2006.285.18:37:00.30#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.18:37:00.30#ibcon#[27=AT06-03\r\n] 2006.285.18:37:00.30#ibcon#*before write, iclass 24, count 2 2006.285.18:37:00.30#ibcon#enter sib2, iclass 24, count 2 2006.285.18:37:00.30#ibcon#flushed, iclass 24, count 2 2006.285.18:37:00.30#ibcon#about to write, iclass 24, count 2 2006.285.18:37:00.30#ibcon#wrote, iclass 24, count 2 2006.285.18:37:00.30#ibcon#about to read 3, iclass 24, count 2 2006.285.18:37:00.33#ibcon#read 3, iclass 24, count 2 2006.285.18:37:00.33#ibcon#about to read 4, iclass 24, count 2 2006.285.18:37:00.33#ibcon#read 4, iclass 24, count 2 2006.285.18:37:00.33#ibcon#about to read 5, iclass 24, count 2 2006.285.18:37:00.33#ibcon#read 5, iclass 24, count 2 2006.285.18:37:00.33#ibcon#about to read 6, iclass 24, count 2 2006.285.18:37:00.33#ibcon#read 6, iclass 24, count 2 2006.285.18:37:00.33#ibcon#end of sib2, iclass 24, count 2 2006.285.18:37:00.33#ibcon#*after write, iclass 24, count 2 2006.285.18:37:00.33#ibcon#*before return 0, iclass 24, count 2 2006.285.18:37:00.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:37:00.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:37:00.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.18:37:00.33#ibcon#ireg 7 cls_cnt 0 2006.285.18:37:00.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:37:00.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:37:00.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:37:00.45#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:37:00.45#ibcon#first serial, iclass 24, count 0 2006.285.18:37:00.45#ibcon#enter sib2, iclass 24, count 0 2006.285.18:37:00.45#ibcon#flushed, iclass 24, count 0 2006.285.18:37:00.45#ibcon#about to write, iclass 24, count 0 2006.285.18:37:00.45#ibcon#wrote, iclass 24, count 0 2006.285.18:37:00.45#ibcon#about to read 3, iclass 24, count 0 2006.285.18:37:00.47#ibcon#read 3, iclass 24, count 0 2006.285.18:37:00.47#ibcon#about to read 4, iclass 24, count 0 2006.285.18:37:00.47#ibcon#read 4, iclass 24, count 0 2006.285.18:37:00.47#ibcon#about to read 5, iclass 24, count 0 2006.285.18:37:00.47#ibcon#read 5, iclass 24, count 0 2006.285.18:37:00.47#ibcon#about to read 6, iclass 24, count 0 2006.285.18:37:00.47#ibcon#read 6, iclass 24, count 0 2006.285.18:37:00.47#ibcon#end of sib2, iclass 24, count 0 2006.285.18:37:00.47#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:37:00.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:37:00.47#ibcon#[27=USB\r\n] 2006.285.18:37:00.47#ibcon#*before write, iclass 24, count 0 2006.285.18:37:00.47#ibcon#enter sib2, iclass 24, count 0 2006.285.18:37:00.47#ibcon#flushed, iclass 24, count 0 2006.285.18:37:00.47#ibcon#about to write, iclass 24, count 0 2006.285.18:37:00.47#ibcon#wrote, iclass 24, count 0 2006.285.18:37:00.47#ibcon#about to read 3, iclass 24, count 0 2006.285.18:37:00.50#ibcon#read 3, iclass 24, count 0 2006.285.18:37:00.50#ibcon#about to read 4, iclass 24, count 0 2006.285.18:37:00.50#ibcon#read 4, iclass 24, count 0 2006.285.18:37:00.50#ibcon#about to read 5, iclass 24, count 0 2006.285.18:37:00.50#ibcon#read 5, iclass 24, count 0 2006.285.18:37:00.50#ibcon#about to read 6, iclass 24, count 0 2006.285.18:37:00.50#ibcon#read 6, iclass 24, count 0 2006.285.18:37:00.50#ibcon#end of sib2, iclass 24, count 0 2006.285.18:37:00.50#ibcon#*after write, iclass 24, count 0 2006.285.18:37:00.50#ibcon#*before return 0, iclass 24, count 0 2006.285.18:37:00.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:37:00.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:37:00.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:37:00.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:37:00.50$vck44/vblo=7,734.99 2006.285.18:37:00.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.18:37:00.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.18:37:00.50#ibcon#ireg 17 cls_cnt 0 2006.285.18:37:00.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:37:00.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:37:00.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:37:00.50#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:37:00.50#ibcon#first serial, iclass 26, count 0 2006.285.18:37:00.50#ibcon#enter sib2, iclass 26, count 0 2006.285.18:37:00.50#ibcon#flushed, iclass 26, count 0 2006.285.18:37:00.50#ibcon#about to write, iclass 26, count 0 2006.285.18:37:00.50#ibcon#wrote, iclass 26, count 0 2006.285.18:37:00.50#ibcon#about to read 3, iclass 26, count 0 2006.285.18:37:00.52#ibcon#read 3, iclass 26, count 0 2006.285.18:37:00.52#ibcon#about to read 4, iclass 26, count 0 2006.285.18:37:00.52#ibcon#read 4, iclass 26, count 0 2006.285.18:37:00.52#ibcon#about to read 5, iclass 26, count 0 2006.285.18:37:00.52#ibcon#read 5, iclass 26, count 0 2006.285.18:37:00.52#ibcon#about to read 6, iclass 26, count 0 2006.285.18:37:00.52#ibcon#read 6, iclass 26, count 0 2006.285.18:37:00.52#ibcon#end of sib2, iclass 26, count 0 2006.285.18:37:00.52#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:37:00.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:37:00.52#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.18:37:00.52#ibcon#*before write, iclass 26, count 0 2006.285.18:37:00.52#ibcon#enter sib2, iclass 26, count 0 2006.285.18:37:00.52#ibcon#flushed, iclass 26, count 0 2006.285.18:37:00.52#ibcon#about to write, iclass 26, count 0 2006.285.18:37:00.52#ibcon#wrote, iclass 26, count 0 2006.285.18:37:00.52#ibcon#about to read 3, iclass 26, count 0 2006.285.18:37:00.56#ibcon#read 3, iclass 26, count 0 2006.285.18:37:00.56#ibcon#about to read 4, iclass 26, count 0 2006.285.18:37:00.56#ibcon#read 4, iclass 26, count 0 2006.285.18:37:00.56#ibcon#about to read 5, iclass 26, count 0 2006.285.18:37:00.56#ibcon#read 5, iclass 26, count 0 2006.285.18:37:00.56#ibcon#about to read 6, iclass 26, count 0 2006.285.18:37:00.56#ibcon#read 6, iclass 26, count 0 2006.285.18:37:00.56#ibcon#end of sib2, iclass 26, count 0 2006.285.18:37:00.56#ibcon#*after write, iclass 26, count 0 2006.285.18:37:00.56#ibcon#*before return 0, iclass 26, count 0 2006.285.18:37:00.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:37:00.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:37:00.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:37:00.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:37:00.56$vck44/vb=7,4 2006.285.18:37:00.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.18:37:00.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.18:37:00.56#ibcon#ireg 11 cls_cnt 2 2006.285.18:37:00.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:37:00.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:37:00.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:37:00.62#ibcon#enter wrdev, iclass 28, count 2 2006.285.18:37:00.62#ibcon#first serial, iclass 28, count 2 2006.285.18:37:00.62#ibcon#enter sib2, iclass 28, count 2 2006.285.18:37:00.62#ibcon#flushed, iclass 28, count 2 2006.285.18:37:00.62#ibcon#about to write, iclass 28, count 2 2006.285.18:37:00.62#ibcon#wrote, iclass 28, count 2 2006.285.18:37:00.62#ibcon#about to read 3, iclass 28, count 2 2006.285.18:37:00.64#ibcon#read 3, iclass 28, count 2 2006.285.18:37:00.64#ibcon#about to read 4, iclass 28, count 2 2006.285.18:37:00.64#ibcon#read 4, iclass 28, count 2 2006.285.18:37:00.64#ibcon#about to read 5, iclass 28, count 2 2006.285.18:37:00.64#ibcon#read 5, iclass 28, count 2 2006.285.18:37:00.64#ibcon#about to read 6, iclass 28, count 2 2006.285.18:37:00.64#ibcon#read 6, iclass 28, count 2 2006.285.18:37:00.64#ibcon#end of sib2, iclass 28, count 2 2006.285.18:37:00.64#ibcon#*mode == 0, iclass 28, count 2 2006.285.18:37:00.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.18:37:00.64#ibcon#[27=AT07-04\r\n] 2006.285.18:37:00.64#ibcon#*before write, iclass 28, count 2 2006.285.18:37:00.64#ibcon#enter sib2, iclass 28, count 2 2006.285.18:37:00.64#ibcon#flushed, iclass 28, count 2 2006.285.18:37:00.64#ibcon#about to write, iclass 28, count 2 2006.285.18:37:00.64#ibcon#wrote, iclass 28, count 2 2006.285.18:37:00.64#ibcon#about to read 3, iclass 28, count 2 2006.285.18:37:00.67#ibcon#read 3, iclass 28, count 2 2006.285.18:37:00.67#ibcon#about to read 4, iclass 28, count 2 2006.285.18:37:00.67#ibcon#read 4, iclass 28, count 2 2006.285.18:37:00.67#ibcon#about to read 5, iclass 28, count 2 2006.285.18:37:00.67#ibcon#read 5, iclass 28, count 2 2006.285.18:37:00.67#ibcon#about to read 6, iclass 28, count 2 2006.285.18:37:00.67#ibcon#read 6, iclass 28, count 2 2006.285.18:37:00.67#ibcon#end of sib2, iclass 28, count 2 2006.285.18:37:00.67#ibcon#*after write, iclass 28, count 2 2006.285.18:37:00.67#ibcon#*before return 0, iclass 28, count 2 2006.285.18:37:00.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:37:00.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:37:00.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.18:37:00.67#ibcon#ireg 7 cls_cnt 0 2006.285.18:37:00.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:37:00.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:37:00.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:37:00.79#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:37:00.79#ibcon#first serial, iclass 28, count 0 2006.285.18:37:00.79#ibcon#enter sib2, iclass 28, count 0 2006.285.18:37:00.79#ibcon#flushed, iclass 28, count 0 2006.285.18:37:00.79#ibcon#about to write, iclass 28, count 0 2006.285.18:37:00.79#ibcon#wrote, iclass 28, count 0 2006.285.18:37:00.79#ibcon#about to read 3, iclass 28, count 0 2006.285.18:37:00.81#ibcon#read 3, iclass 28, count 0 2006.285.18:37:00.81#ibcon#about to read 4, iclass 28, count 0 2006.285.18:37:00.81#ibcon#read 4, iclass 28, count 0 2006.285.18:37:00.81#ibcon#about to read 5, iclass 28, count 0 2006.285.18:37:00.81#ibcon#read 5, iclass 28, count 0 2006.285.18:37:00.81#ibcon#about to read 6, iclass 28, count 0 2006.285.18:37:00.81#ibcon#read 6, iclass 28, count 0 2006.285.18:37:00.81#ibcon#end of sib2, iclass 28, count 0 2006.285.18:37:00.81#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:37:00.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:37:00.81#ibcon#[27=USB\r\n] 2006.285.18:37:00.81#ibcon#*before write, iclass 28, count 0 2006.285.18:37:00.81#ibcon#enter sib2, iclass 28, count 0 2006.285.18:37:00.81#ibcon#flushed, iclass 28, count 0 2006.285.18:37:00.81#ibcon#about to write, iclass 28, count 0 2006.285.18:37:00.81#ibcon#wrote, iclass 28, count 0 2006.285.18:37:00.81#ibcon#about to read 3, iclass 28, count 0 2006.285.18:37:00.84#ibcon#read 3, iclass 28, count 0 2006.285.18:37:00.84#ibcon#about to read 4, iclass 28, count 0 2006.285.18:37:00.84#ibcon#read 4, iclass 28, count 0 2006.285.18:37:00.84#ibcon#about to read 5, iclass 28, count 0 2006.285.18:37:00.84#ibcon#read 5, iclass 28, count 0 2006.285.18:37:00.84#ibcon#about to read 6, iclass 28, count 0 2006.285.18:37:00.84#ibcon#read 6, iclass 28, count 0 2006.285.18:37:00.84#ibcon#end of sib2, iclass 28, count 0 2006.285.18:37:00.84#ibcon#*after write, iclass 28, count 0 2006.285.18:37:00.84#ibcon#*before return 0, iclass 28, count 0 2006.285.18:37:00.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:37:00.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:37:00.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:37:00.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:37:00.84$vck44/vblo=8,744.99 2006.285.18:37:00.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.18:37:00.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.18:37:00.84#ibcon#ireg 17 cls_cnt 0 2006.285.18:37:00.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:37:00.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:37:00.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:37:00.84#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:37:00.84#ibcon#first serial, iclass 30, count 0 2006.285.18:37:00.84#ibcon#enter sib2, iclass 30, count 0 2006.285.18:37:00.84#ibcon#flushed, iclass 30, count 0 2006.285.18:37:00.84#ibcon#about to write, iclass 30, count 0 2006.285.18:37:00.84#ibcon#wrote, iclass 30, count 0 2006.285.18:37:00.84#ibcon#about to read 3, iclass 30, count 0 2006.285.18:37:00.86#ibcon#read 3, iclass 30, count 0 2006.285.18:37:00.86#ibcon#about to read 4, iclass 30, count 0 2006.285.18:37:00.86#ibcon#read 4, iclass 30, count 0 2006.285.18:37:00.86#ibcon#about to read 5, iclass 30, count 0 2006.285.18:37:00.86#ibcon#read 5, iclass 30, count 0 2006.285.18:37:00.86#ibcon#about to read 6, iclass 30, count 0 2006.285.18:37:00.86#ibcon#read 6, iclass 30, count 0 2006.285.18:37:00.86#ibcon#end of sib2, iclass 30, count 0 2006.285.18:37:00.86#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:37:00.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:37:00.86#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.18:37:00.86#ibcon#*before write, iclass 30, count 0 2006.285.18:37:00.86#ibcon#enter sib2, iclass 30, count 0 2006.285.18:37:00.86#ibcon#flushed, iclass 30, count 0 2006.285.18:37:00.86#ibcon#about to write, iclass 30, count 0 2006.285.18:37:00.86#ibcon#wrote, iclass 30, count 0 2006.285.18:37:00.86#ibcon#about to read 3, iclass 30, count 0 2006.285.18:37:00.90#ibcon#read 3, iclass 30, count 0 2006.285.18:37:00.90#ibcon#about to read 4, iclass 30, count 0 2006.285.18:37:00.90#ibcon#read 4, iclass 30, count 0 2006.285.18:37:00.90#ibcon#about to read 5, iclass 30, count 0 2006.285.18:37:00.90#ibcon#read 5, iclass 30, count 0 2006.285.18:37:00.90#ibcon#about to read 6, iclass 30, count 0 2006.285.18:37:00.90#ibcon#read 6, iclass 30, count 0 2006.285.18:37:00.90#ibcon#end of sib2, iclass 30, count 0 2006.285.18:37:00.90#ibcon#*after write, iclass 30, count 0 2006.285.18:37:00.90#ibcon#*before return 0, iclass 30, count 0 2006.285.18:37:00.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:37:00.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:37:00.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:37:00.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:37:00.90$vck44/vb=8,4 2006.285.18:37:00.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.18:37:00.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.18:37:00.90#ibcon#ireg 11 cls_cnt 2 2006.285.18:37:00.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:37:00.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:37:00.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:37:00.96#ibcon#enter wrdev, iclass 32, count 2 2006.285.18:37:00.96#ibcon#first serial, iclass 32, count 2 2006.285.18:37:00.96#ibcon#enter sib2, iclass 32, count 2 2006.285.18:37:00.96#ibcon#flushed, iclass 32, count 2 2006.285.18:37:00.96#ibcon#about to write, iclass 32, count 2 2006.285.18:37:00.96#ibcon#wrote, iclass 32, count 2 2006.285.18:37:00.96#ibcon#about to read 3, iclass 32, count 2 2006.285.18:37:00.98#ibcon#read 3, iclass 32, count 2 2006.285.18:37:00.98#ibcon#about to read 4, iclass 32, count 2 2006.285.18:37:00.98#ibcon#read 4, iclass 32, count 2 2006.285.18:37:00.98#ibcon#about to read 5, iclass 32, count 2 2006.285.18:37:00.98#ibcon#read 5, iclass 32, count 2 2006.285.18:37:00.98#ibcon#about to read 6, iclass 32, count 2 2006.285.18:37:00.98#ibcon#read 6, iclass 32, count 2 2006.285.18:37:00.98#ibcon#end of sib2, iclass 32, count 2 2006.285.18:37:00.98#ibcon#*mode == 0, iclass 32, count 2 2006.285.18:37:00.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.18:37:00.98#ibcon#[27=AT08-04\r\n] 2006.285.18:37:00.98#ibcon#*before write, iclass 32, count 2 2006.285.18:37:00.98#ibcon#enter sib2, iclass 32, count 2 2006.285.18:37:00.98#ibcon#flushed, iclass 32, count 2 2006.285.18:37:00.98#ibcon#about to write, iclass 32, count 2 2006.285.18:37:00.98#ibcon#wrote, iclass 32, count 2 2006.285.18:37:00.98#ibcon#about to read 3, iclass 32, count 2 2006.285.18:37:01.01#ibcon#read 3, iclass 32, count 2 2006.285.18:37:01.01#ibcon#about to read 4, iclass 32, count 2 2006.285.18:37:01.01#ibcon#read 4, iclass 32, count 2 2006.285.18:37:01.01#ibcon#about to read 5, iclass 32, count 2 2006.285.18:37:01.01#ibcon#read 5, iclass 32, count 2 2006.285.18:37:01.01#ibcon#about to read 6, iclass 32, count 2 2006.285.18:37:01.01#ibcon#read 6, iclass 32, count 2 2006.285.18:37:01.01#ibcon#end of sib2, iclass 32, count 2 2006.285.18:37:01.01#ibcon#*after write, iclass 32, count 2 2006.285.18:37:01.01#ibcon#*before return 0, iclass 32, count 2 2006.285.18:37:01.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:37:01.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:37:01.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.18:37:01.01#ibcon#ireg 7 cls_cnt 0 2006.285.18:37:01.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:37:01.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:37:01.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:37:01.13#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:37:01.13#ibcon#first serial, iclass 32, count 0 2006.285.18:37:01.13#ibcon#enter sib2, iclass 32, count 0 2006.285.18:37:01.13#ibcon#flushed, iclass 32, count 0 2006.285.18:37:01.13#ibcon#about to write, iclass 32, count 0 2006.285.18:37:01.13#ibcon#wrote, iclass 32, count 0 2006.285.18:37:01.13#ibcon#about to read 3, iclass 32, count 0 2006.285.18:37:01.15#ibcon#read 3, iclass 32, count 0 2006.285.18:37:01.15#ibcon#about to read 4, iclass 32, count 0 2006.285.18:37:01.15#ibcon#read 4, iclass 32, count 0 2006.285.18:37:01.15#ibcon#about to read 5, iclass 32, count 0 2006.285.18:37:01.15#ibcon#read 5, iclass 32, count 0 2006.285.18:37:01.15#ibcon#about to read 6, iclass 32, count 0 2006.285.18:37:01.15#ibcon#read 6, iclass 32, count 0 2006.285.18:37:01.15#ibcon#end of sib2, iclass 32, count 0 2006.285.18:37:01.15#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:37:01.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:37:01.15#ibcon#[27=USB\r\n] 2006.285.18:37:01.15#ibcon#*before write, iclass 32, count 0 2006.285.18:37:01.15#ibcon#enter sib2, iclass 32, count 0 2006.285.18:37:01.15#ibcon#flushed, iclass 32, count 0 2006.285.18:37:01.15#ibcon#about to write, iclass 32, count 0 2006.285.18:37:01.15#ibcon#wrote, iclass 32, count 0 2006.285.18:37:01.15#ibcon#about to read 3, iclass 32, count 0 2006.285.18:37:01.18#ibcon#read 3, iclass 32, count 0 2006.285.18:37:01.18#ibcon#about to read 4, iclass 32, count 0 2006.285.18:37:01.18#ibcon#read 4, iclass 32, count 0 2006.285.18:37:01.18#ibcon#about to read 5, iclass 32, count 0 2006.285.18:37:01.18#ibcon#read 5, iclass 32, count 0 2006.285.18:37:01.18#ibcon#about to read 6, iclass 32, count 0 2006.285.18:37:01.18#ibcon#read 6, iclass 32, count 0 2006.285.18:37:01.18#ibcon#end of sib2, iclass 32, count 0 2006.285.18:37:01.18#ibcon#*after write, iclass 32, count 0 2006.285.18:37:01.18#ibcon#*before return 0, iclass 32, count 0 2006.285.18:37:01.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:37:01.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:37:01.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:37:01.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:37:01.18$vck44/vabw=wide 2006.285.18:37:01.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.18:37:01.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.18:37:01.18#ibcon#ireg 8 cls_cnt 0 2006.285.18:37:01.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:37:01.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:37:01.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:37:01.18#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:37:01.18#ibcon#first serial, iclass 34, count 0 2006.285.18:37:01.18#ibcon#enter sib2, iclass 34, count 0 2006.285.18:37:01.18#ibcon#flushed, iclass 34, count 0 2006.285.18:37:01.18#ibcon#about to write, iclass 34, count 0 2006.285.18:37:01.18#ibcon#wrote, iclass 34, count 0 2006.285.18:37:01.18#ibcon#about to read 3, iclass 34, count 0 2006.285.18:37:01.20#ibcon#read 3, iclass 34, count 0 2006.285.18:37:01.20#ibcon#about to read 4, iclass 34, count 0 2006.285.18:37:01.20#ibcon#read 4, iclass 34, count 0 2006.285.18:37:01.20#ibcon#about to read 5, iclass 34, count 0 2006.285.18:37:01.20#ibcon#read 5, iclass 34, count 0 2006.285.18:37:01.20#ibcon#about to read 6, iclass 34, count 0 2006.285.18:37:01.20#ibcon#read 6, iclass 34, count 0 2006.285.18:37:01.20#ibcon#end of sib2, iclass 34, count 0 2006.285.18:37:01.20#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:37:01.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:37:01.20#ibcon#[25=BW32\r\n] 2006.285.18:37:01.20#ibcon#*before write, iclass 34, count 0 2006.285.18:37:01.20#ibcon#enter sib2, iclass 34, count 0 2006.285.18:37:01.20#ibcon#flushed, iclass 34, count 0 2006.285.18:37:01.20#ibcon#about to write, iclass 34, count 0 2006.285.18:37:01.20#ibcon#wrote, iclass 34, count 0 2006.285.18:37:01.20#ibcon#about to read 3, iclass 34, count 0 2006.285.18:37:01.23#ibcon#read 3, iclass 34, count 0 2006.285.18:37:01.23#ibcon#about to read 4, iclass 34, count 0 2006.285.18:37:01.23#ibcon#read 4, iclass 34, count 0 2006.285.18:37:01.23#ibcon#about to read 5, iclass 34, count 0 2006.285.18:37:01.23#ibcon#read 5, iclass 34, count 0 2006.285.18:37:01.23#ibcon#about to read 6, iclass 34, count 0 2006.285.18:37:01.23#ibcon#read 6, iclass 34, count 0 2006.285.18:37:01.23#ibcon#end of sib2, iclass 34, count 0 2006.285.18:37:01.23#ibcon#*after write, iclass 34, count 0 2006.285.18:37:01.23#ibcon#*before return 0, iclass 34, count 0 2006.285.18:37:01.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:37:01.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:37:01.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:37:01.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:37:01.23$vck44/vbbw=wide 2006.285.18:37:01.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.18:37:01.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.18:37:01.23#ibcon#ireg 8 cls_cnt 0 2006.285.18:37:01.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:37:01.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:37:01.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:37:01.30#ibcon#enter wrdev, iclass 36, count 0 2006.285.18:37:01.30#ibcon#first serial, iclass 36, count 0 2006.285.18:37:01.30#ibcon#enter sib2, iclass 36, count 0 2006.285.18:37:01.30#ibcon#flushed, iclass 36, count 0 2006.285.18:37:01.30#ibcon#about to write, iclass 36, count 0 2006.285.18:37:01.30#ibcon#wrote, iclass 36, count 0 2006.285.18:37:01.30#ibcon#about to read 3, iclass 36, count 0 2006.285.18:37:01.32#ibcon#read 3, iclass 36, count 0 2006.285.18:37:01.32#ibcon#about to read 4, iclass 36, count 0 2006.285.18:37:01.32#ibcon#read 4, iclass 36, count 0 2006.285.18:37:01.32#ibcon#about to read 5, iclass 36, count 0 2006.285.18:37:01.32#ibcon#read 5, iclass 36, count 0 2006.285.18:37:01.32#ibcon#about to read 6, iclass 36, count 0 2006.285.18:37:01.32#ibcon#read 6, iclass 36, count 0 2006.285.18:37:01.32#ibcon#end of sib2, iclass 36, count 0 2006.285.18:37:01.32#ibcon#*mode == 0, iclass 36, count 0 2006.285.18:37:01.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.18:37:01.32#ibcon#[27=BW32\r\n] 2006.285.18:37:01.32#ibcon#*before write, iclass 36, count 0 2006.285.18:37:01.32#ibcon#enter sib2, iclass 36, count 0 2006.285.18:37:01.32#ibcon#flushed, iclass 36, count 0 2006.285.18:37:01.32#ibcon#about to write, iclass 36, count 0 2006.285.18:37:01.32#ibcon#wrote, iclass 36, count 0 2006.285.18:37:01.32#ibcon#about to read 3, iclass 36, count 0 2006.285.18:37:01.35#ibcon#read 3, iclass 36, count 0 2006.285.18:37:01.35#ibcon#about to read 4, iclass 36, count 0 2006.285.18:37:01.35#ibcon#read 4, iclass 36, count 0 2006.285.18:37:01.35#ibcon#about to read 5, iclass 36, count 0 2006.285.18:37:01.35#ibcon#read 5, iclass 36, count 0 2006.285.18:37:01.35#ibcon#about to read 6, iclass 36, count 0 2006.285.18:37:01.35#ibcon#read 6, iclass 36, count 0 2006.285.18:37:01.35#ibcon#end of sib2, iclass 36, count 0 2006.285.18:37:01.35#ibcon#*after write, iclass 36, count 0 2006.285.18:37:01.35#ibcon#*before return 0, iclass 36, count 0 2006.285.18:37:01.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:37:01.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:37:01.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.18:37:01.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.18:37:01.35$setupk4/ifdk4 2006.285.18:37:01.35$ifdk4/lo= 2006.285.18:37:01.35$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.18:37:01.35$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.18:37:01.35$ifdk4/patch= 2006.285.18:37:01.35$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.18:37:01.35$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.18:37:01.35$setupk4/!*+20s 2006.285.18:37:01.95#abcon#<5=/16 0.3 0.9 15.291001014.8\r\n> 2006.285.18:37:01.97#abcon#{5=INTERFACE CLEAR} 2006.285.18:37:02.03#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:37:12.12#abcon#<5=/16 0.3 0.9 15.291001014.8\r\n> 2006.285.18:37:12.14#abcon#{5=INTERFACE CLEAR} 2006.285.18:37:12.20#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:37:14.63$setupk4/"tpicd 2006.285.18:37:14.63$setupk4/echo=off 2006.285.18:37:14.63$setupk4/xlog=off 2006.285.18:37:14.63:!2006.285.18:39:29 2006.285.18:37:40.14#trakl#Source acquired 2006.285.18:37:42.14#flagr#flagr/antenna,acquired 2006.285.18:39:29.00:preob 2006.285.18:39:29.14/onsource/TRACKING 2006.285.18:39:29.14:!2006.285.18:39:39 2006.285.18:39:39.00:"tape 2006.285.18:39:39.00:"st=record 2006.285.18:39:39.00:data_valid=on 2006.285.18:39:39.00:midob 2006.285.18:39:39.14/onsource/TRACKING 2006.285.18:39:39.14/wx/15.24,1014.8,100 2006.285.18:39:39.23/cable/+6.5061E-03 2006.285.18:39:40.32/va/01,07,usb,yes,32,35 2006.285.18:39:40.32/va/02,06,usb,yes,32,33 2006.285.18:39:40.32/va/03,07,usb,yes,32,34 2006.285.18:39:40.32/va/04,06,usb,yes,33,35 2006.285.18:39:40.32/va/05,03,usb,yes,33,33 2006.285.18:39:40.32/va/06,04,usb,yes,29,29 2006.285.18:39:40.32/va/07,04,usb,yes,30,31 2006.285.18:39:40.32/va/08,03,usb,yes,31,37 2006.285.18:39:40.55/valo/01,524.99,yes,locked 2006.285.18:39:40.55/valo/02,534.99,yes,locked 2006.285.18:39:40.55/valo/03,564.99,yes,locked 2006.285.18:39:40.55/valo/04,624.99,yes,locked 2006.285.18:39:40.55/valo/05,734.99,yes,locked 2006.285.18:39:40.55/valo/06,814.99,yes,locked 2006.285.18:39:40.55/valo/07,864.99,yes,locked 2006.285.18:39:40.55/valo/08,884.99,yes,locked 2006.285.18:39:41.64/vb/01,04,usb,yes,30,28 2006.285.18:39:41.64/vb/02,05,usb,yes,28,28 2006.285.18:39:41.64/vb/03,04,usb,yes,29,32 2006.285.18:39:41.64/vb/04,05,usb,yes,30,29 2006.285.18:39:41.64/vb/05,04,usb,yes,26,29 2006.285.18:39:41.64/vb/06,03,usb,yes,38,34 2006.285.18:39:41.64/vb/07,04,usb,yes,30,30 2006.285.18:39:41.64/vb/08,04,usb,yes,28,31 2006.285.18:39:41.87/vblo/01,629.99,yes,locked 2006.285.18:39:41.87/vblo/02,634.99,yes,locked 2006.285.18:39:41.87/vblo/03,649.99,yes,locked 2006.285.18:39:41.87/vblo/04,679.99,yes,locked 2006.285.18:39:41.87/vblo/05,709.99,yes,locked 2006.285.18:39:41.87/vblo/06,719.99,yes,locked 2006.285.18:39:41.87/vblo/07,734.99,yes,locked 2006.285.18:39:41.87/vblo/08,744.99,yes,locked 2006.285.18:39:42.02/vabw/8 2006.285.18:39:42.17/vbbw/8 2006.285.18:39:42.26/xfe/off,on,12.0 2006.285.18:39:42.64/ifatt/23,28,28,28 2006.285.18:39:43.07/fmout-gps/S +2.50E-07 2006.285.18:39:43.09:!2006.285.18:43:09 2006.285.18:43:09.00:data_valid=off 2006.285.18:43:09.00:"et 2006.285.18:43:09.00:!+3s 2006.285.18:43:12.01:"tape 2006.285.18:43:12.01:postob 2006.285.18:43:12.12/cable/+6.5047E-03 2006.285.18:43:12.12/wx/15.20,1014.8,100 2006.285.18:43:13.08/fmout-gps/S +2.47E-07 2006.285.18:43:13.08:scan_name=285-1846,jd0610,300 2006.285.18:43:13.08:source=oj287,085448.87,200630.6,2000.0,cw 2006.285.18:43:13.13#flagr#flagr/antenna,new-source 2006.285.18:43:14.13:checkk5 2006.285.18:43:14.60/chk_autoobs//k5ts1/ autoobs is running! 2006.285.18:43:14.99/chk_autoobs//k5ts2/ autoobs is running! 2006.285.18:43:15.41/chk_autoobs//k5ts3/ autoobs is running! 2006.285.18:43:16.06/chk_autoobs//k5ts4/ autoobs is running! 2006.285.18:43:16.45/chk_obsdata//k5ts1/T2851839??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.285.18:43:16.88/chk_obsdata//k5ts2/T2851839??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.285.18:43:17.25/chk_obsdata//k5ts3/T2851839??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.285.18:43:17.78/chk_obsdata//k5ts4/T2851839??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.285.18:43:18.61/k5log//k5ts1_log_newline 2006.285.18:43:19.35/k5log//k5ts2_log_newline 2006.285.18:43:20.10/k5log//k5ts3_log_newline 2006.285.18:43:20.92/k5log//k5ts4_log_newline 2006.285.18:43:20.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.18:43:20.94:setupk4=1 2006.285.18:43:20.94$setupk4/echo=on 2006.285.18:43:20.94$setupk4/pcalon 2006.285.18:43:20.94$pcalon/"no phase cal control is implemented here 2006.285.18:43:20.94$setupk4/"tpicd=stop 2006.285.18:43:20.94$setupk4/"rec=synch_on 2006.285.18:43:20.94$setupk4/"rec_mode=128 2006.285.18:43:20.94$setupk4/!* 2006.285.18:43:20.94$setupk4/recpk4 2006.285.18:43:20.94$recpk4/recpatch= 2006.285.18:43:20.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.18:43:20.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.18:43:20.94$setupk4/vck44 2006.285.18:43:20.94$vck44/valo=1,524.99 2006.285.18:43:20.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.18:43:20.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.18:43:20.95#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:20.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:43:20.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:43:20.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:43:20.95#ibcon#enter wrdev, iclass 40, count 0 2006.285.18:43:20.95#ibcon#first serial, iclass 40, count 0 2006.285.18:43:20.95#ibcon#enter sib2, iclass 40, count 0 2006.285.18:43:20.95#ibcon#flushed, iclass 40, count 0 2006.285.18:43:20.95#ibcon#about to write, iclass 40, count 0 2006.285.18:43:20.95#ibcon#wrote, iclass 40, count 0 2006.285.18:43:20.95#ibcon#about to read 3, iclass 40, count 0 2006.285.18:43:20.96#ibcon#read 3, iclass 40, count 0 2006.285.18:43:20.96#ibcon#about to read 4, iclass 40, count 0 2006.285.18:43:20.96#ibcon#read 4, iclass 40, count 0 2006.285.18:43:20.96#ibcon#about to read 5, iclass 40, count 0 2006.285.18:43:20.96#ibcon#read 5, iclass 40, count 0 2006.285.18:43:20.96#ibcon#about to read 6, iclass 40, count 0 2006.285.18:43:20.96#ibcon#read 6, iclass 40, count 0 2006.285.18:43:20.96#ibcon#end of sib2, iclass 40, count 0 2006.285.18:43:20.96#ibcon#*mode == 0, iclass 40, count 0 2006.285.18:43:20.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.18:43:20.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.18:43:20.96#ibcon#*before write, iclass 40, count 0 2006.285.18:43:20.96#ibcon#enter sib2, iclass 40, count 0 2006.285.18:43:20.96#ibcon#flushed, iclass 40, count 0 2006.285.18:43:20.96#ibcon#about to write, iclass 40, count 0 2006.285.18:43:20.96#ibcon#wrote, iclass 40, count 0 2006.285.18:43:20.96#ibcon#about to read 3, iclass 40, count 0 2006.285.18:43:21.01#ibcon#read 3, iclass 40, count 0 2006.285.18:43:21.01#ibcon#about to read 4, iclass 40, count 0 2006.285.18:43:21.01#ibcon#read 4, iclass 40, count 0 2006.285.18:43:21.01#ibcon#about to read 5, iclass 40, count 0 2006.285.18:43:21.01#ibcon#read 5, iclass 40, count 0 2006.285.18:43:21.01#ibcon#about to read 6, iclass 40, count 0 2006.285.18:43:21.01#ibcon#read 6, iclass 40, count 0 2006.285.18:43:21.01#ibcon#end of sib2, iclass 40, count 0 2006.285.18:43:21.01#ibcon#*after write, iclass 40, count 0 2006.285.18:43:21.01#ibcon#*before return 0, iclass 40, count 0 2006.285.18:43:21.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:43:21.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:43:21.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.18:43:21.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.18:43:21.01$vck44/va=1,7 2006.285.18:43:21.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.18:43:21.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.18:43:21.01#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:21.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:43:21.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:43:21.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:43:21.01#ibcon#enter wrdev, iclass 4, count 2 2006.285.18:43:21.01#ibcon#first serial, iclass 4, count 2 2006.285.18:43:21.01#ibcon#enter sib2, iclass 4, count 2 2006.285.18:43:21.01#ibcon#flushed, iclass 4, count 2 2006.285.18:43:21.01#ibcon#about to write, iclass 4, count 2 2006.285.18:43:21.01#ibcon#wrote, iclass 4, count 2 2006.285.18:43:21.01#ibcon#about to read 3, iclass 4, count 2 2006.285.18:43:21.03#ibcon#read 3, iclass 4, count 2 2006.285.18:43:21.03#ibcon#about to read 4, iclass 4, count 2 2006.285.18:43:21.03#ibcon#read 4, iclass 4, count 2 2006.285.18:43:21.03#ibcon#about to read 5, iclass 4, count 2 2006.285.18:43:21.03#ibcon#read 5, iclass 4, count 2 2006.285.18:43:21.03#ibcon#about to read 6, iclass 4, count 2 2006.285.18:43:21.03#ibcon#read 6, iclass 4, count 2 2006.285.18:43:21.03#ibcon#end of sib2, iclass 4, count 2 2006.285.18:43:21.03#ibcon#*mode == 0, iclass 4, count 2 2006.285.18:43:21.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.18:43:21.03#ibcon#[25=AT01-07\r\n] 2006.285.18:43:21.03#ibcon#*before write, iclass 4, count 2 2006.285.18:43:21.03#ibcon#enter sib2, iclass 4, count 2 2006.285.18:43:21.03#ibcon#flushed, iclass 4, count 2 2006.285.18:43:21.03#ibcon#about to write, iclass 4, count 2 2006.285.18:43:21.03#ibcon#wrote, iclass 4, count 2 2006.285.18:43:21.03#ibcon#about to read 3, iclass 4, count 2 2006.285.18:43:21.06#ibcon#read 3, iclass 4, count 2 2006.285.18:43:21.06#ibcon#about to read 4, iclass 4, count 2 2006.285.18:43:21.06#ibcon#read 4, iclass 4, count 2 2006.285.18:43:21.06#ibcon#about to read 5, iclass 4, count 2 2006.285.18:43:21.06#ibcon#read 5, iclass 4, count 2 2006.285.18:43:21.06#ibcon#about to read 6, iclass 4, count 2 2006.285.18:43:21.06#ibcon#read 6, iclass 4, count 2 2006.285.18:43:21.06#ibcon#end of sib2, iclass 4, count 2 2006.285.18:43:21.06#ibcon#*after write, iclass 4, count 2 2006.285.18:43:21.06#ibcon#*before return 0, iclass 4, count 2 2006.285.18:43:21.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:43:21.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:43:21.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.18:43:21.06#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:21.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:43:21.07#abcon#<5=/15 0.5 1.6 15.201001014.8\r\n> 2006.285.18:43:21.09#abcon#{5=INTERFACE CLEAR} 2006.285.18:43:21.15#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:43:21.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:43:21.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:43:21.18#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:43:21.18#ibcon#first serial, iclass 4, count 0 2006.285.18:43:21.18#ibcon#enter sib2, iclass 4, count 0 2006.285.18:43:21.18#ibcon#flushed, iclass 4, count 0 2006.285.18:43:21.18#ibcon#about to write, iclass 4, count 0 2006.285.18:43:21.18#ibcon#wrote, iclass 4, count 0 2006.285.18:43:21.18#ibcon#about to read 3, iclass 4, count 0 2006.285.18:43:21.20#ibcon#read 3, iclass 4, count 0 2006.285.18:43:21.20#ibcon#about to read 4, iclass 4, count 0 2006.285.18:43:21.20#ibcon#read 4, iclass 4, count 0 2006.285.18:43:21.20#ibcon#about to read 5, iclass 4, count 0 2006.285.18:43:21.20#ibcon#read 5, iclass 4, count 0 2006.285.18:43:21.20#ibcon#about to read 6, iclass 4, count 0 2006.285.18:43:21.20#ibcon#read 6, iclass 4, count 0 2006.285.18:43:21.20#ibcon#end of sib2, iclass 4, count 0 2006.285.18:43:21.20#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:43:21.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:43:21.20#ibcon#[25=USB\r\n] 2006.285.18:43:21.20#ibcon#*before write, iclass 4, count 0 2006.285.18:43:21.20#ibcon#enter sib2, iclass 4, count 0 2006.285.18:43:21.20#ibcon#flushed, iclass 4, count 0 2006.285.18:43:21.20#ibcon#about to write, iclass 4, count 0 2006.285.18:43:21.20#ibcon#wrote, iclass 4, count 0 2006.285.18:43:21.20#ibcon#about to read 3, iclass 4, count 0 2006.285.18:43:21.23#ibcon#read 3, iclass 4, count 0 2006.285.18:43:21.23#ibcon#about to read 4, iclass 4, count 0 2006.285.18:43:21.23#ibcon#read 4, iclass 4, count 0 2006.285.18:43:21.23#ibcon#about to read 5, iclass 4, count 0 2006.285.18:43:21.23#ibcon#read 5, iclass 4, count 0 2006.285.18:43:21.23#ibcon#about to read 6, iclass 4, count 0 2006.285.18:43:21.23#ibcon#read 6, iclass 4, count 0 2006.285.18:43:21.23#ibcon#end of sib2, iclass 4, count 0 2006.285.18:43:21.23#ibcon#*after write, iclass 4, count 0 2006.285.18:43:21.23#ibcon#*before return 0, iclass 4, count 0 2006.285.18:43:21.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:43:21.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:43:21.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:43:21.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:43:21.23$vck44/valo=2,534.99 2006.285.18:43:21.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.18:43:21.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.18:43:21.23#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:21.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:43:21.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:43:21.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:43:21.23#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:43:21.23#ibcon#first serial, iclass 12, count 0 2006.285.18:43:21.23#ibcon#enter sib2, iclass 12, count 0 2006.285.18:43:21.23#ibcon#flushed, iclass 12, count 0 2006.285.18:43:21.23#ibcon#about to write, iclass 12, count 0 2006.285.18:43:21.23#ibcon#wrote, iclass 12, count 0 2006.285.18:43:21.23#ibcon#about to read 3, iclass 12, count 0 2006.285.18:43:21.25#ibcon#read 3, iclass 12, count 0 2006.285.18:43:21.25#ibcon#about to read 4, iclass 12, count 0 2006.285.18:43:21.25#ibcon#read 4, iclass 12, count 0 2006.285.18:43:21.25#ibcon#about to read 5, iclass 12, count 0 2006.285.18:43:21.25#ibcon#read 5, iclass 12, count 0 2006.285.18:43:21.25#ibcon#about to read 6, iclass 12, count 0 2006.285.18:43:21.25#ibcon#read 6, iclass 12, count 0 2006.285.18:43:21.25#ibcon#end of sib2, iclass 12, count 0 2006.285.18:43:21.25#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:43:21.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:43:21.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.18:43:21.25#ibcon#*before write, iclass 12, count 0 2006.285.18:43:21.25#ibcon#enter sib2, iclass 12, count 0 2006.285.18:43:21.25#ibcon#flushed, iclass 12, count 0 2006.285.18:43:21.25#ibcon#about to write, iclass 12, count 0 2006.285.18:43:21.25#ibcon#wrote, iclass 12, count 0 2006.285.18:43:21.25#ibcon#about to read 3, iclass 12, count 0 2006.285.18:43:21.29#ibcon#read 3, iclass 12, count 0 2006.285.18:43:21.29#ibcon#about to read 4, iclass 12, count 0 2006.285.18:43:21.29#ibcon#read 4, iclass 12, count 0 2006.285.18:43:21.29#ibcon#about to read 5, iclass 12, count 0 2006.285.18:43:21.29#ibcon#read 5, iclass 12, count 0 2006.285.18:43:21.29#ibcon#about to read 6, iclass 12, count 0 2006.285.18:43:21.29#ibcon#read 6, iclass 12, count 0 2006.285.18:43:21.29#ibcon#end of sib2, iclass 12, count 0 2006.285.18:43:21.29#ibcon#*after write, iclass 12, count 0 2006.285.18:43:21.29#ibcon#*before return 0, iclass 12, count 0 2006.285.18:43:21.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:43:21.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:43:21.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:43:21.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:43:21.29$vck44/va=2,6 2006.285.18:43:21.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.18:43:21.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.18:43:21.29#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:21.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:43:21.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:43:21.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:43:21.35#ibcon#enter wrdev, iclass 14, count 2 2006.285.18:43:21.35#ibcon#first serial, iclass 14, count 2 2006.285.18:43:21.35#ibcon#enter sib2, iclass 14, count 2 2006.285.18:43:21.35#ibcon#flushed, iclass 14, count 2 2006.285.18:43:21.35#ibcon#about to write, iclass 14, count 2 2006.285.18:43:21.35#ibcon#wrote, iclass 14, count 2 2006.285.18:43:21.35#ibcon#about to read 3, iclass 14, count 2 2006.285.18:43:21.37#ibcon#read 3, iclass 14, count 2 2006.285.18:43:21.37#ibcon#about to read 4, iclass 14, count 2 2006.285.18:43:21.37#ibcon#read 4, iclass 14, count 2 2006.285.18:43:21.37#ibcon#about to read 5, iclass 14, count 2 2006.285.18:43:21.37#ibcon#read 5, iclass 14, count 2 2006.285.18:43:21.37#ibcon#about to read 6, iclass 14, count 2 2006.285.18:43:21.37#ibcon#read 6, iclass 14, count 2 2006.285.18:43:21.37#ibcon#end of sib2, iclass 14, count 2 2006.285.18:43:21.37#ibcon#*mode == 0, iclass 14, count 2 2006.285.18:43:21.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.18:43:21.37#ibcon#[25=AT02-06\r\n] 2006.285.18:43:21.37#ibcon#*before write, iclass 14, count 2 2006.285.18:43:21.37#ibcon#enter sib2, iclass 14, count 2 2006.285.18:43:21.37#ibcon#flushed, iclass 14, count 2 2006.285.18:43:21.37#ibcon#about to write, iclass 14, count 2 2006.285.18:43:21.37#ibcon#wrote, iclass 14, count 2 2006.285.18:43:21.37#ibcon#about to read 3, iclass 14, count 2 2006.285.18:43:21.40#ibcon#read 3, iclass 14, count 2 2006.285.18:43:21.40#ibcon#about to read 4, iclass 14, count 2 2006.285.18:43:21.40#ibcon#read 4, iclass 14, count 2 2006.285.18:43:21.40#ibcon#about to read 5, iclass 14, count 2 2006.285.18:43:21.40#ibcon#read 5, iclass 14, count 2 2006.285.18:43:21.40#ibcon#about to read 6, iclass 14, count 2 2006.285.18:43:21.40#ibcon#read 6, iclass 14, count 2 2006.285.18:43:21.40#ibcon#end of sib2, iclass 14, count 2 2006.285.18:43:21.40#ibcon#*after write, iclass 14, count 2 2006.285.18:43:21.40#ibcon#*before return 0, iclass 14, count 2 2006.285.18:43:21.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:43:21.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:43:21.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.18:43:21.40#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:21.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:43:21.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:43:21.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:43:21.52#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:43:21.52#ibcon#first serial, iclass 14, count 0 2006.285.18:43:21.52#ibcon#enter sib2, iclass 14, count 0 2006.285.18:43:21.52#ibcon#flushed, iclass 14, count 0 2006.285.18:43:21.52#ibcon#about to write, iclass 14, count 0 2006.285.18:43:21.52#ibcon#wrote, iclass 14, count 0 2006.285.18:43:21.52#ibcon#about to read 3, iclass 14, count 0 2006.285.18:43:21.54#ibcon#read 3, iclass 14, count 0 2006.285.18:43:21.54#ibcon#about to read 4, iclass 14, count 0 2006.285.18:43:21.54#ibcon#read 4, iclass 14, count 0 2006.285.18:43:21.54#ibcon#about to read 5, iclass 14, count 0 2006.285.18:43:21.54#ibcon#read 5, iclass 14, count 0 2006.285.18:43:21.54#ibcon#about to read 6, iclass 14, count 0 2006.285.18:43:21.54#ibcon#read 6, iclass 14, count 0 2006.285.18:43:21.54#ibcon#end of sib2, iclass 14, count 0 2006.285.18:43:21.54#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:43:21.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:43:21.54#ibcon#[25=USB\r\n] 2006.285.18:43:21.54#ibcon#*before write, iclass 14, count 0 2006.285.18:43:21.54#ibcon#enter sib2, iclass 14, count 0 2006.285.18:43:21.54#ibcon#flushed, iclass 14, count 0 2006.285.18:43:21.54#ibcon#about to write, iclass 14, count 0 2006.285.18:43:21.54#ibcon#wrote, iclass 14, count 0 2006.285.18:43:21.54#ibcon#about to read 3, iclass 14, count 0 2006.285.18:43:21.57#ibcon#read 3, iclass 14, count 0 2006.285.18:43:21.57#ibcon#about to read 4, iclass 14, count 0 2006.285.18:43:21.57#ibcon#read 4, iclass 14, count 0 2006.285.18:43:21.57#ibcon#about to read 5, iclass 14, count 0 2006.285.18:43:21.57#ibcon#read 5, iclass 14, count 0 2006.285.18:43:21.57#ibcon#about to read 6, iclass 14, count 0 2006.285.18:43:21.57#ibcon#read 6, iclass 14, count 0 2006.285.18:43:21.57#ibcon#end of sib2, iclass 14, count 0 2006.285.18:43:21.57#ibcon#*after write, iclass 14, count 0 2006.285.18:43:21.57#ibcon#*before return 0, iclass 14, count 0 2006.285.18:43:21.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:43:21.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:43:21.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:43:21.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:43:21.57$vck44/valo=3,564.99 2006.285.18:43:21.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.18:43:21.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.18:43:21.57#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:21.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:43:21.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:43:21.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:43:21.57#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:43:21.57#ibcon#first serial, iclass 16, count 0 2006.285.18:43:21.57#ibcon#enter sib2, iclass 16, count 0 2006.285.18:43:21.57#ibcon#flushed, iclass 16, count 0 2006.285.18:43:21.57#ibcon#about to write, iclass 16, count 0 2006.285.18:43:21.57#ibcon#wrote, iclass 16, count 0 2006.285.18:43:21.57#ibcon#about to read 3, iclass 16, count 0 2006.285.18:43:21.59#ibcon#read 3, iclass 16, count 0 2006.285.18:43:21.96#ibcon#about to read 4, iclass 16, count 0 2006.285.18:43:21.96#ibcon#read 4, iclass 16, count 0 2006.285.18:43:21.96#ibcon#about to read 5, iclass 16, count 0 2006.285.18:43:21.96#ibcon#read 5, iclass 16, count 0 2006.285.18:43:21.96#ibcon#about to read 6, iclass 16, count 0 2006.285.18:43:21.96#ibcon#read 6, iclass 16, count 0 2006.285.18:43:21.96#ibcon#end of sib2, iclass 16, count 0 2006.285.18:43:21.96#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:43:21.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:43:21.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.18:43:21.96#ibcon#*before write, iclass 16, count 0 2006.285.18:43:21.96#ibcon#enter sib2, iclass 16, count 0 2006.285.18:43:21.96#ibcon#flushed, iclass 16, count 0 2006.285.18:43:21.96#ibcon#about to write, iclass 16, count 0 2006.285.18:43:21.96#ibcon#wrote, iclass 16, count 0 2006.285.18:43:21.96#ibcon#about to read 3, iclass 16, count 0 2006.285.18:43:22.00#ibcon#read 3, iclass 16, count 0 2006.285.18:43:22.00#ibcon#about to read 4, iclass 16, count 0 2006.285.18:43:22.00#ibcon#read 4, iclass 16, count 0 2006.285.18:43:22.00#ibcon#about to read 5, iclass 16, count 0 2006.285.18:43:22.00#ibcon#read 5, iclass 16, count 0 2006.285.18:43:22.00#ibcon#about to read 6, iclass 16, count 0 2006.285.18:43:22.00#ibcon#read 6, iclass 16, count 0 2006.285.18:43:22.00#ibcon#end of sib2, iclass 16, count 0 2006.285.18:43:22.00#ibcon#*after write, iclass 16, count 0 2006.285.18:43:22.00#ibcon#*before return 0, iclass 16, count 0 2006.285.18:43:22.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:43:22.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:43:22.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:43:22.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:43:22.00$vck44/va=3,7 2006.285.18:43:22.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.18:43:22.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.18:43:22.00#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:22.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:43:22.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:43:22.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:43:22.00#ibcon#enter wrdev, iclass 18, count 2 2006.285.18:43:22.00#ibcon#first serial, iclass 18, count 2 2006.285.18:43:22.00#ibcon#enter sib2, iclass 18, count 2 2006.285.18:43:22.00#ibcon#flushed, iclass 18, count 2 2006.285.18:43:22.00#ibcon#about to write, iclass 18, count 2 2006.285.18:43:22.00#ibcon#wrote, iclass 18, count 2 2006.285.18:43:22.00#ibcon#about to read 3, iclass 18, count 2 2006.285.18:43:22.02#ibcon#read 3, iclass 18, count 2 2006.285.18:43:22.02#ibcon#about to read 4, iclass 18, count 2 2006.285.18:43:22.02#ibcon#read 4, iclass 18, count 2 2006.285.18:43:22.02#ibcon#about to read 5, iclass 18, count 2 2006.285.18:43:22.02#ibcon#read 5, iclass 18, count 2 2006.285.18:43:22.02#ibcon#about to read 6, iclass 18, count 2 2006.285.18:43:22.02#ibcon#read 6, iclass 18, count 2 2006.285.18:43:22.02#ibcon#end of sib2, iclass 18, count 2 2006.285.18:43:22.02#ibcon#*mode == 0, iclass 18, count 2 2006.285.18:43:22.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.18:43:22.02#ibcon#[25=AT03-07\r\n] 2006.285.18:43:22.02#ibcon#*before write, iclass 18, count 2 2006.285.18:43:22.02#ibcon#enter sib2, iclass 18, count 2 2006.285.18:43:22.02#ibcon#flushed, iclass 18, count 2 2006.285.18:43:22.02#ibcon#about to write, iclass 18, count 2 2006.285.18:43:22.02#ibcon#wrote, iclass 18, count 2 2006.285.18:43:22.02#ibcon#about to read 3, iclass 18, count 2 2006.285.18:43:22.05#ibcon#read 3, iclass 18, count 2 2006.285.18:43:22.05#ibcon#about to read 4, iclass 18, count 2 2006.285.18:43:22.05#ibcon#read 4, iclass 18, count 2 2006.285.18:43:22.05#ibcon#about to read 5, iclass 18, count 2 2006.285.18:43:22.05#ibcon#read 5, iclass 18, count 2 2006.285.18:43:22.05#ibcon#about to read 6, iclass 18, count 2 2006.285.18:43:22.05#ibcon#read 6, iclass 18, count 2 2006.285.18:43:22.05#ibcon#end of sib2, iclass 18, count 2 2006.285.18:43:22.05#ibcon#*after write, iclass 18, count 2 2006.285.18:43:22.05#ibcon#*before return 0, iclass 18, count 2 2006.285.18:43:22.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:43:22.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:43:22.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.18:43:22.05#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:22.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:43:22.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:43:22.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:43:22.17#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:43:22.17#ibcon#first serial, iclass 18, count 0 2006.285.18:43:22.17#ibcon#enter sib2, iclass 18, count 0 2006.285.18:43:22.17#ibcon#flushed, iclass 18, count 0 2006.285.18:43:22.17#ibcon#about to write, iclass 18, count 0 2006.285.18:43:22.17#ibcon#wrote, iclass 18, count 0 2006.285.18:43:22.17#ibcon#about to read 3, iclass 18, count 0 2006.285.18:43:22.19#ibcon#read 3, iclass 18, count 0 2006.285.18:43:22.19#ibcon#about to read 4, iclass 18, count 0 2006.285.18:43:22.19#ibcon#read 4, iclass 18, count 0 2006.285.18:43:22.19#ibcon#about to read 5, iclass 18, count 0 2006.285.18:43:22.19#ibcon#read 5, iclass 18, count 0 2006.285.18:43:22.19#ibcon#about to read 6, iclass 18, count 0 2006.285.18:43:22.19#ibcon#read 6, iclass 18, count 0 2006.285.18:43:22.19#ibcon#end of sib2, iclass 18, count 0 2006.285.18:43:22.19#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:43:22.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:43:22.19#ibcon#[25=USB\r\n] 2006.285.18:43:22.19#ibcon#*before write, iclass 18, count 0 2006.285.18:43:22.19#ibcon#enter sib2, iclass 18, count 0 2006.285.18:43:22.19#ibcon#flushed, iclass 18, count 0 2006.285.18:43:22.19#ibcon#about to write, iclass 18, count 0 2006.285.18:43:22.19#ibcon#wrote, iclass 18, count 0 2006.285.18:43:22.19#ibcon#about to read 3, iclass 18, count 0 2006.285.18:43:22.22#ibcon#read 3, iclass 18, count 0 2006.285.18:43:22.22#ibcon#about to read 4, iclass 18, count 0 2006.285.18:43:22.22#ibcon#read 4, iclass 18, count 0 2006.285.18:43:22.22#ibcon#about to read 5, iclass 18, count 0 2006.285.18:43:22.22#ibcon#read 5, iclass 18, count 0 2006.285.18:43:22.22#ibcon#about to read 6, iclass 18, count 0 2006.285.18:43:22.22#ibcon#read 6, iclass 18, count 0 2006.285.18:43:22.22#ibcon#end of sib2, iclass 18, count 0 2006.285.18:43:22.22#ibcon#*after write, iclass 18, count 0 2006.285.18:43:22.22#ibcon#*before return 0, iclass 18, count 0 2006.285.18:43:22.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:43:22.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:43:22.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:43:22.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:43:22.22$vck44/valo=4,624.99 2006.285.18:43:22.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.18:43:22.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.18:43:22.22#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:22.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:43:22.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:43:22.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:43:22.22#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:43:22.22#ibcon#first serial, iclass 20, count 0 2006.285.18:43:22.22#ibcon#enter sib2, iclass 20, count 0 2006.285.18:43:22.22#ibcon#flushed, iclass 20, count 0 2006.285.18:43:22.22#ibcon#about to write, iclass 20, count 0 2006.285.18:43:22.22#ibcon#wrote, iclass 20, count 0 2006.285.18:43:22.22#ibcon#about to read 3, iclass 20, count 0 2006.285.18:43:22.24#ibcon#read 3, iclass 20, count 0 2006.285.18:43:22.62#ibcon#about to read 4, iclass 20, count 0 2006.285.18:43:22.62#ibcon#read 4, iclass 20, count 0 2006.285.18:43:22.62#ibcon#about to read 5, iclass 20, count 0 2006.285.18:43:22.62#ibcon#read 5, iclass 20, count 0 2006.285.18:43:22.62#ibcon#about to read 6, iclass 20, count 0 2006.285.18:43:22.62#ibcon#read 6, iclass 20, count 0 2006.285.18:43:22.62#ibcon#end of sib2, iclass 20, count 0 2006.285.18:43:22.62#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:43:22.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:43:22.62#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.18:43:22.62#ibcon#*before write, iclass 20, count 0 2006.285.18:43:22.62#ibcon#enter sib2, iclass 20, count 0 2006.285.18:43:22.62#ibcon#flushed, iclass 20, count 0 2006.285.18:43:22.62#ibcon#about to write, iclass 20, count 0 2006.285.18:43:22.62#ibcon#wrote, iclass 20, count 0 2006.285.18:43:22.62#ibcon#about to read 3, iclass 20, count 0 2006.285.18:43:22.67#ibcon#read 3, iclass 20, count 0 2006.285.18:43:22.67#ibcon#about to read 4, iclass 20, count 0 2006.285.18:43:22.67#ibcon#read 4, iclass 20, count 0 2006.285.18:43:22.67#ibcon#about to read 5, iclass 20, count 0 2006.285.18:43:22.67#ibcon#read 5, iclass 20, count 0 2006.285.18:43:22.67#ibcon#about to read 6, iclass 20, count 0 2006.285.18:43:22.67#ibcon#read 6, iclass 20, count 0 2006.285.18:43:22.67#ibcon#end of sib2, iclass 20, count 0 2006.285.18:43:22.67#ibcon#*after write, iclass 20, count 0 2006.285.18:43:22.67#ibcon#*before return 0, iclass 20, count 0 2006.285.18:43:22.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:43:22.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:43:22.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:43:22.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:43:22.67$vck44/va=4,6 2006.285.18:43:22.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.18:43:22.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.18:43:22.67#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:22.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:43:22.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:43:22.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:43:22.67#ibcon#enter wrdev, iclass 22, count 2 2006.285.18:43:22.67#ibcon#first serial, iclass 22, count 2 2006.285.18:43:22.67#ibcon#enter sib2, iclass 22, count 2 2006.285.18:43:22.67#ibcon#flushed, iclass 22, count 2 2006.285.18:43:22.67#ibcon#about to write, iclass 22, count 2 2006.285.18:43:22.67#ibcon#wrote, iclass 22, count 2 2006.285.18:43:22.67#ibcon#about to read 3, iclass 22, count 2 2006.285.18:43:22.69#ibcon#read 3, iclass 22, count 2 2006.285.18:43:22.69#ibcon#about to read 4, iclass 22, count 2 2006.285.18:43:22.69#ibcon#read 4, iclass 22, count 2 2006.285.18:43:22.69#ibcon#about to read 5, iclass 22, count 2 2006.285.18:43:22.69#ibcon#read 5, iclass 22, count 2 2006.285.18:43:22.69#ibcon#about to read 6, iclass 22, count 2 2006.285.18:43:22.69#ibcon#read 6, iclass 22, count 2 2006.285.18:43:22.69#ibcon#end of sib2, iclass 22, count 2 2006.285.18:43:22.69#ibcon#*mode == 0, iclass 22, count 2 2006.285.18:43:22.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.18:43:22.69#ibcon#[25=AT04-06\r\n] 2006.285.18:43:22.69#ibcon#*before write, iclass 22, count 2 2006.285.18:43:22.69#ibcon#enter sib2, iclass 22, count 2 2006.285.18:43:22.69#ibcon#flushed, iclass 22, count 2 2006.285.18:43:22.69#ibcon#about to write, iclass 22, count 2 2006.285.18:43:22.69#ibcon#wrote, iclass 22, count 2 2006.285.18:43:22.69#ibcon#about to read 3, iclass 22, count 2 2006.285.18:43:22.72#ibcon#read 3, iclass 22, count 2 2006.285.18:43:22.72#ibcon#about to read 4, iclass 22, count 2 2006.285.18:43:22.72#ibcon#read 4, iclass 22, count 2 2006.285.18:43:22.72#ibcon#about to read 5, iclass 22, count 2 2006.285.18:43:22.72#ibcon#read 5, iclass 22, count 2 2006.285.18:43:22.72#ibcon#about to read 6, iclass 22, count 2 2006.285.18:43:22.72#ibcon#read 6, iclass 22, count 2 2006.285.18:43:22.72#ibcon#end of sib2, iclass 22, count 2 2006.285.18:43:22.72#ibcon#*after write, iclass 22, count 2 2006.285.18:43:22.72#ibcon#*before return 0, iclass 22, count 2 2006.285.18:43:22.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:43:22.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:43:22.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.18:43:22.72#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:22.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:43:22.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:43:22.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:43:22.84#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:43:22.84#ibcon#first serial, iclass 22, count 0 2006.285.18:43:22.84#ibcon#enter sib2, iclass 22, count 0 2006.285.18:43:22.84#ibcon#flushed, iclass 22, count 0 2006.285.18:43:22.84#ibcon#about to write, iclass 22, count 0 2006.285.18:43:22.84#ibcon#wrote, iclass 22, count 0 2006.285.18:43:22.84#ibcon#about to read 3, iclass 22, count 0 2006.285.18:43:22.86#ibcon#read 3, iclass 22, count 0 2006.285.18:43:22.86#ibcon#about to read 4, iclass 22, count 0 2006.285.18:43:22.86#ibcon#read 4, iclass 22, count 0 2006.285.18:43:22.86#ibcon#about to read 5, iclass 22, count 0 2006.285.18:43:22.86#ibcon#read 5, iclass 22, count 0 2006.285.18:43:22.86#ibcon#about to read 6, iclass 22, count 0 2006.285.18:43:22.86#ibcon#read 6, iclass 22, count 0 2006.285.18:43:22.86#ibcon#end of sib2, iclass 22, count 0 2006.285.18:43:22.86#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:43:22.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:43:22.86#ibcon#[25=USB\r\n] 2006.285.18:43:22.86#ibcon#*before write, iclass 22, count 0 2006.285.18:43:22.86#ibcon#enter sib2, iclass 22, count 0 2006.285.18:43:22.86#ibcon#flushed, iclass 22, count 0 2006.285.18:43:22.86#ibcon#about to write, iclass 22, count 0 2006.285.18:43:22.86#ibcon#wrote, iclass 22, count 0 2006.285.18:43:22.86#ibcon#about to read 3, iclass 22, count 0 2006.285.18:43:22.89#ibcon#read 3, iclass 22, count 0 2006.285.18:43:22.89#ibcon#about to read 4, iclass 22, count 0 2006.285.18:43:22.89#ibcon#read 4, iclass 22, count 0 2006.285.18:43:22.89#ibcon#about to read 5, iclass 22, count 0 2006.285.18:43:22.89#ibcon#read 5, iclass 22, count 0 2006.285.18:43:22.89#ibcon#about to read 6, iclass 22, count 0 2006.285.18:43:22.89#ibcon#read 6, iclass 22, count 0 2006.285.18:43:22.89#ibcon#end of sib2, iclass 22, count 0 2006.285.18:43:22.89#ibcon#*after write, iclass 22, count 0 2006.285.18:43:22.89#ibcon#*before return 0, iclass 22, count 0 2006.285.18:43:22.89#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:43:22.89#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:43:22.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:43:22.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:43:22.89$vck44/valo=5,734.99 2006.285.18:43:22.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.18:43:22.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.18:43:22.89#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:22.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:43:22.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:43:22.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:43:22.89#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:43:22.89#ibcon#first serial, iclass 24, count 0 2006.285.18:43:22.89#ibcon#enter sib2, iclass 24, count 0 2006.285.18:43:22.89#ibcon#flushed, iclass 24, count 0 2006.285.18:43:22.89#ibcon#about to write, iclass 24, count 0 2006.285.18:43:22.89#ibcon#wrote, iclass 24, count 0 2006.285.18:43:22.89#ibcon#about to read 3, iclass 24, count 0 2006.285.18:43:22.91#ibcon#read 3, iclass 24, count 0 2006.285.18:43:22.93#ibcon#about to read 4, iclass 24, count 0 2006.285.18:43:22.93#ibcon#read 4, iclass 24, count 0 2006.285.18:43:22.93#ibcon#about to read 5, iclass 24, count 0 2006.285.18:43:22.93#ibcon#read 5, iclass 24, count 0 2006.285.18:43:22.93#ibcon#about to read 6, iclass 24, count 0 2006.285.18:43:22.93#ibcon#read 6, iclass 24, count 0 2006.285.18:43:22.93#ibcon#end of sib2, iclass 24, count 0 2006.285.18:43:22.93#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:43:22.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:43:22.93#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.18:43:22.93#ibcon#*before write, iclass 24, count 0 2006.285.18:43:22.93#ibcon#enter sib2, iclass 24, count 0 2006.285.18:43:22.93#ibcon#flushed, iclass 24, count 0 2006.285.18:43:22.93#ibcon#about to write, iclass 24, count 0 2006.285.18:43:22.93#ibcon#wrote, iclass 24, count 0 2006.285.18:43:22.93#ibcon#about to read 3, iclass 24, count 0 2006.285.18:43:22.97#ibcon#read 3, iclass 24, count 0 2006.285.18:43:22.97#ibcon#about to read 4, iclass 24, count 0 2006.285.18:43:22.97#ibcon#read 4, iclass 24, count 0 2006.285.18:43:22.97#ibcon#about to read 5, iclass 24, count 0 2006.285.18:43:22.97#ibcon#read 5, iclass 24, count 0 2006.285.18:43:22.97#ibcon#about to read 6, iclass 24, count 0 2006.285.18:43:22.97#ibcon#read 6, iclass 24, count 0 2006.285.18:43:22.97#ibcon#end of sib2, iclass 24, count 0 2006.285.18:43:22.97#ibcon#*after write, iclass 24, count 0 2006.285.18:43:22.97#ibcon#*before return 0, iclass 24, count 0 2006.285.18:43:22.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:43:22.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:43:22.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:43:22.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:43:22.97$vck44/va=5,3 2006.285.18:43:22.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.18:43:22.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.18:43:22.97#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:22.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:43:23.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:43:23.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:43:23.01#ibcon#enter wrdev, iclass 26, count 2 2006.285.18:43:23.01#ibcon#first serial, iclass 26, count 2 2006.285.18:43:23.01#ibcon#enter sib2, iclass 26, count 2 2006.285.18:43:23.01#ibcon#flushed, iclass 26, count 2 2006.285.18:43:23.01#ibcon#about to write, iclass 26, count 2 2006.285.18:43:23.01#ibcon#wrote, iclass 26, count 2 2006.285.18:43:23.01#ibcon#about to read 3, iclass 26, count 2 2006.285.18:43:23.03#ibcon#read 3, iclass 26, count 2 2006.285.18:43:23.03#ibcon#about to read 4, iclass 26, count 2 2006.285.18:43:23.03#ibcon#read 4, iclass 26, count 2 2006.285.18:43:23.03#ibcon#about to read 5, iclass 26, count 2 2006.285.18:43:23.03#ibcon#read 5, iclass 26, count 2 2006.285.18:43:23.03#ibcon#about to read 6, iclass 26, count 2 2006.285.18:43:23.03#ibcon#read 6, iclass 26, count 2 2006.285.18:43:23.03#ibcon#end of sib2, iclass 26, count 2 2006.285.18:43:23.03#ibcon#*mode == 0, iclass 26, count 2 2006.285.18:43:23.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.18:43:23.03#ibcon#[25=AT05-03\r\n] 2006.285.18:43:23.03#ibcon#*before write, iclass 26, count 2 2006.285.18:43:23.03#ibcon#enter sib2, iclass 26, count 2 2006.285.18:43:23.03#ibcon#flushed, iclass 26, count 2 2006.285.18:43:23.03#ibcon#about to write, iclass 26, count 2 2006.285.18:43:23.03#ibcon#wrote, iclass 26, count 2 2006.285.18:43:23.03#ibcon#about to read 3, iclass 26, count 2 2006.285.18:43:23.06#ibcon#read 3, iclass 26, count 2 2006.285.18:43:23.06#ibcon#about to read 4, iclass 26, count 2 2006.285.18:43:23.06#ibcon#read 4, iclass 26, count 2 2006.285.18:43:23.06#ibcon#about to read 5, iclass 26, count 2 2006.285.18:43:23.06#ibcon#read 5, iclass 26, count 2 2006.285.18:43:23.06#ibcon#about to read 6, iclass 26, count 2 2006.285.18:43:23.06#ibcon#read 6, iclass 26, count 2 2006.285.18:43:23.06#ibcon#end of sib2, iclass 26, count 2 2006.285.18:43:23.06#ibcon#*after write, iclass 26, count 2 2006.285.18:43:23.06#ibcon#*before return 0, iclass 26, count 2 2006.285.18:43:23.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:43:23.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:43:23.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.18:43:23.06#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:23.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:43:23.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:43:23.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:43:23.18#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:43:23.18#ibcon#first serial, iclass 26, count 0 2006.285.18:43:23.18#ibcon#enter sib2, iclass 26, count 0 2006.285.18:43:23.18#ibcon#flushed, iclass 26, count 0 2006.285.18:43:23.18#ibcon#about to write, iclass 26, count 0 2006.285.18:43:23.18#ibcon#wrote, iclass 26, count 0 2006.285.18:43:23.18#ibcon#about to read 3, iclass 26, count 0 2006.285.18:43:23.20#ibcon#read 3, iclass 26, count 0 2006.285.18:43:23.20#ibcon#about to read 4, iclass 26, count 0 2006.285.18:43:23.20#ibcon#read 4, iclass 26, count 0 2006.285.18:43:23.20#ibcon#about to read 5, iclass 26, count 0 2006.285.18:43:23.20#ibcon#read 5, iclass 26, count 0 2006.285.18:43:23.20#ibcon#about to read 6, iclass 26, count 0 2006.285.18:43:23.20#ibcon#read 6, iclass 26, count 0 2006.285.18:43:23.20#ibcon#end of sib2, iclass 26, count 0 2006.285.18:43:23.20#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:43:23.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:43:23.20#ibcon#[25=USB\r\n] 2006.285.18:43:23.20#ibcon#*before write, iclass 26, count 0 2006.285.18:43:23.20#ibcon#enter sib2, iclass 26, count 0 2006.285.18:43:23.20#ibcon#flushed, iclass 26, count 0 2006.285.18:43:23.20#ibcon#about to write, iclass 26, count 0 2006.285.18:43:23.20#ibcon#wrote, iclass 26, count 0 2006.285.18:43:23.20#ibcon#about to read 3, iclass 26, count 0 2006.285.18:43:23.23#ibcon#read 3, iclass 26, count 0 2006.285.18:43:23.23#ibcon#about to read 4, iclass 26, count 0 2006.285.18:43:23.23#ibcon#read 4, iclass 26, count 0 2006.285.18:43:23.23#ibcon#about to read 5, iclass 26, count 0 2006.285.18:43:23.23#ibcon#read 5, iclass 26, count 0 2006.285.18:43:23.23#ibcon#about to read 6, iclass 26, count 0 2006.285.18:43:23.23#ibcon#read 6, iclass 26, count 0 2006.285.18:43:23.23#ibcon#end of sib2, iclass 26, count 0 2006.285.18:43:23.23#ibcon#*after write, iclass 26, count 0 2006.285.18:43:23.23#ibcon#*before return 0, iclass 26, count 0 2006.285.18:43:23.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:43:23.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:43:23.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:43:23.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:43:23.23$vck44/valo=6,814.99 2006.285.18:43:23.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.18:43:23.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.18:43:23.23#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:23.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:43:23.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:43:23.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:43:23.23#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:43:23.23#ibcon#first serial, iclass 28, count 0 2006.285.18:43:23.23#ibcon#enter sib2, iclass 28, count 0 2006.285.18:43:23.23#ibcon#flushed, iclass 28, count 0 2006.285.18:43:23.23#ibcon#about to write, iclass 28, count 0 2006.285.18:43:23.23#ibcon#wrote, iclass 28, count 0 2006.285.18:43:23.23#ibcon#about to read 3, iclass 28, count 0 2006.285.18:43:23.25#ibcon#read 3, iclass 28, count 0 2006.285.18:43:23.25#ibcon#about to read 4, iclass 28, count 0 2006.285.18:43:23.25#ibcon#read 4, iclass 28, count 0 2006.285.18:43:23.25#ibcon#about to read 5, iclass 28, count 0 2006.285.18:43:23.25#ibcon#read 5, iclass 28, count 0 2006.285.18:43:23.25#ibcon#about to read 6, iclass 28, count 0 2006.285.18:43:23.25#ibcon#read 6, iclass 28, count 0 2006.285.18:43:23.25#ibcon#end of sib2, iclass 28, count 0 2006.285.18:43:23.25#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:43:23.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:43:23.25#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.18:43:23.25#ibcon#*before write, iclass 28, count 0 2006.285.18:43:23.25#ibcon#enter sib2, iclass 28, count 0 2006.285.18:43:23.25#ibcon#flushed, iclass 28, count 0 2006.285.18:43:23.25#ibcon#about to write, iclass 28, count 0 2006.285.18:43:23.25#ibcon#wrote, iclass 28, count 0 2006.285.18:43:23.25#ibcon#about to read 3, iclass 28, count 0 2006.285.18:43:23.29#ibcon#read 3, iclass 28, count 0 2006.285.18:43:23.29#ibcon#about to read 4, iclass 28, count 0 2006.285.18:43:23.29#ibcon#read 4, iclass 28, count 0 2006.285.18:43:23.29#ibcon#about to read 5, iclass 28, count 0 2006.285.18:43:23.29#ibcon#read 5, iclass 28, count 0 2006.285.18:43:23.29#ibcon#about to read 6, iclass 28, count 0 2006.285.18:43:23.29#ibcon#read 6, iclass 28, count 0 2006.285.18:43:23.29#ibcon#end of sib2, iclass 28, count 0 2006.285.18:43:23.29#ibcon#*after write, iclass 28, count 0 2006.285.18:43:23.29#ibcon#*before return 0, iclass 28, count 0 2006.285.18:43:23.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:43:23.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:43:23.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:43:23.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:43:23.29$vck44/va=6,4 2006.285.18:43:23.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.18:43:23.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.18:43:23.29#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:23.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:43:23.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:43:23.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:43:23.35#ibcon#enter wrdev, iclass 30, count 2 2006.285.18:43:23.35#ibcon#first serial, iclass 30, count 2 2006.285.18:43:23.35#ibcon#enter sib2, iclass 30, count 2 2006.285.18:43:23.35#ibcon#flushed, iclass 30, count 2 2006.285.18:43:23.35#ibcon#about to write, iclass 30, count 2 2006.285.18:43:23.35#ibcon#wrote, iclass 30, count 2 2006.285.18:43:23.35#ibcon#about to read 3, iclass 30, count 2 2006.285.18:43:23.37#ibcon#read 3, iclass 30, count 2 2006.285.18:43:23.37#ibcon#about to read 4, iclass 30, count 2 2006.285.18:43:23.37#ibcon#read 4, iclass 30, count 2 2006.285.18:43:23.37#ibcon#about to read 5, iclass 30, count 2 2006.285.18:43:23.37#ibcon#read 5, iclass 30, count 2 2006.285.18:43:23.37#ibcon#about to read 6, iclass 30, count 2 2006.285.18:43:23.37#ibcon#read 6, iclass 30, count 2 2006.285.18:43:23.37#ibcon#end of sib2, iclass 30, count 2 2006.285.18:43:23.37#ibcon#*mode == 0, iclass 30, count 2 2006.285.18:43:23.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.18:43:23.37#ibcon#[25=AT06-04\r\n] 2006.285.18:43:23.37#ibcon#*before write, iclass 30, count 2 2006.285.18:43:23.37#ibcon#enter sib2, iclass 30, count 2 2006.285.18:43:23.37#ibcon#flushed, iclass 30, count 2 2006.285.18:43:23.37#ibcon#about to write, iclass 30, count 2 2006.285.18:43:23.37#ibcon#wrote, iclass 30, count 2 2006.285.18:43:23.37#ibcon#about to read 3, iclass 30, count 2 2006.285.18:43:23.40#ibcon#read 3, iclass 30, count 2 2006.285.18:43:23.40#ibcon#about to read 4, iclass 30, count 2 2006.285.18:43:23.40#ibcon#read 4, iclass 30, count 2 2006.285.18:43:23.40#ibcon#about to read 5, iclass 30, count 2 2006.285.18:43:23.40#ibcon#read 5, iclass 30, count 2 2006.285.18:43:23.40#ibcon#about to read 6, iclass 30, count 2 2006.285.18:43:23.40#ibcon#read 6, iclass 30, count 2 2006.285.18:43:23.40#ibcon#end of sib2, iclass 30, count 2 2006.285.18:43:23.40#ibcon#*after write, iclass 30, count 2 2006.285.18:43:23.40#ibcon#*before return 0, iclass 30, count 2 2006.285.18:43:23.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:43:23.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:43:23.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.18:43:23.40#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:23.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:43:23.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:43:23.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:43:23.52#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:43:23.52#ibcon#first serial, iclass 30, count 0 2006.285.18:43:23.52#ibcon#enter sib2, iclass 30, count 0 2006.285.18:43:23.52#ibcon#flushed, iclass 30, count 0 2006.285.18:43:23.52#ibcon#about to write, iclass 30, count 0 2006.285.18:43:23.52#ibcon#wrote, iclass 30, count 0 2006.285.18:43:23.52#ibcon#about to read 3, iclass 30, count 0 2006.285.18:43:23.54#ibcon#read 3, iclass 30, count 0 2006.285.18:43:23.54#ibcon#about to read 4, iclass 30, count 0 2006.285.18:43:23.54#ibcon#read 4, iclass 30, count 0 2006.285.18:43:23.54#ibcon#about to read 5, iclass 30, count 0 2006.285.18:43:23.54#ibcon#read 5, iclass 30, count 0 2006.285.18:43:23.54#ibcon#about to read 6, iclass 30, count 0 2006.285.18:43:23.54#ibcon#read 6, iclass 30, count 0 2006.285.18:43:23.54#ibcon#end of sib2, iclass 30, count 0 2006.285.18:43:23.54#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:43:23.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:43:23.54#ibcon#[25=USB\r\n] 2006.285.18:43:23.54#ibcon#*before write, iclass 30, count 0 2006.285.18:43:23.54#ibcon#enter sib2, iclass 30, count 0 2006.285.18:43:23.54#ibcon#flushed, iclass 30, count 0 2006.285.18:43:23.54#ibcon#about to write, iclass 30, count 0 2006.285.18:43:23.54#ibcon#wrote, iclass 30, count 0 2006.285.18:43:23.54#ibcon#about to read 3, iclass 30, count 0 2006.285.18:43:23.57#ibcon#read 3, iclass 30, count 0 2006.285.18:43:23.57#ibcon#about to read 4, iclass 30, count 0 2006.285.18:43:23.57#ibcon#read 4, iclass 30, count 0 2006.285.18:43:23.57#ibcon#about to read 5, iclass 30, count 0 2006.285.18:43:23.57#ibcon#read 5, iclass 30, count 0 2006.285.18:43:23.57#ibcon#about to read 6, iclass 30, count 0 2006.285.18:43:23.57#ibcon#read 6, iclass 30, count 0 2006.285.18:43:23.57#ibcon#end of sib2, iclass 30, count 0 2006.285.18:43:23.57#ibcon#*after write, iclass 30, count 0 2006.285.18:43:23.57#ibcon#*before return 0, iclass 30, count 0 2006.285.18:43:23.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:43:23.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:43:23.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:43:23.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:43:23.57$vck44/valo=7,864.99 2006.285.18:43:23.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.18:43:23.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.18:43:23.57#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:23.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:43:23.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:43:23.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:43:23.57#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:43:23.57#ibcon#first serial, iclass 32, count 0 2006.285.18:43:23.57#ibcon#enter sib2, iclass 32, count 0 2006.285.18:43:23.57#ibcon#flushed, iclass 32, count 0 2006.285.18:43:23.57#ibcon#about to write, iclass 32, count 0 2006.285.18:43:23.57#ibcon#wrote, iclass 32, count 0 2006.285.18:43:23.57#ibcon#about to read 3, iclass 32, count 0 2006.285.18:43:23.59#ibcon#read 3, iclass 32, count 0 2006.285.18:43:23.63#ibcon#about to read 4, iclass 32, count 0 2006.285.18:43:23.63#ibcon#read 4, iclass 32, count 0 2006.285.18:43:23.63#ibcon#about to read 5, iclass 32, count 0 2006.285.18:43:23.63#ibcon#read 5, iclass 32, count 0 2006.285.18:43:23.63#ibcon#about to read 6, iclass 32, count 0 2006.285.18:43:23.63#ibcon#read 6, iclass 32, count 0 2006.285.18:43:23.63#ibcon#end of sib2, iclass 32, count 0 2006.285.18:43:23.63#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:43:23.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:43:23.63#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.18:43:23.63#ibcon#*before write, iclass 32, count 0 2006.285.18:43:23.63#ibcon#enter sib2, iclass 32, count 0 2006.285.18:43:23.63#ibcon#flushed, iclass 32, count 0 2006.285.18:43:23.63#ibcon#about to write, iclass 32, count 0 2006.285.18:43:23.63#ibcon#wrote, iclass 32, count 0 2006.285.18:43:23.63#ibcon#about to read 3, iclass 32, count 0 2006.285.18:43:23.68#ibcon#read 3, iclass 32, count 0 2006.285.18:43:23.68#ibcon#about to read 4, iclass 32, count 0 2006.285.18:43:23.68#ibcon#read 4, iclass 32, count 0 2006.285.18:43:23.68#ibcon#about to read 5, iclass 32, count 0 2006.285.18:43:23.68#ibcon#read 5, iclass 32, count 0 2006.285.18:43:23.68#ibcon#about to read 6, iclass 32, count 0 2006.285.18:43:23.68#ibcon#read 6, iclass 32, count 0 2006.285.18:43:23.68#ibcon#end of sib2, iclass 32, count 0 2006.285.18:43:23.68#ibcon#*after write, iclass 32, count 0 2006.285.18:43:23.68#ibcon#*before return 0, iclass 32, count 0 2006.285.18:43:23.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:43:23.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:43:23.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:43:23.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:43:23.68$vck44/va=7,4 2006.285.18:43:23.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.18:43:23.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.18:43:23.68#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:23.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:43:23.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:43:23.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:43:23.68#ibcon#enter wrdev, iclass 34, count 2 2006.285.18:43:23.68#ibcon#first serial, iclass 34, count 2 2006.285.18:43:23.68#ibcon#enter sib2, iclass 34, count 2 2006.285.18:43:23.68#ibcon#flushed, iclass 34, count 2 2006.285.18:43:23.68#ibcon#about to write, iclass 34, count 2 2006.285.18:43:23.68#ibcon#wrote, iclass 34, count 2 2006.285.18:43:23.68#ibcon#about to read 3, iclass 34, count 2 2006.285.18:43:23.70#ibcon#read 3, iclass 34, count 2 2006.285.18:43:23.70#ibcon#about to read 4, iclass 34, count 2 2006.285.18:43:23.70#ibcon#read 4, iclass 34, count 2 2006.285.18:43:23.70#ibcon#about to read 5, iclass 34, count 2 2006.285.18:43:23.70#ibcon#read 5, iclass 34, count 2 2006.285.18:43:23.70#ibcon#about to read 6, iclass 34, count 2 2006.285.18:43:23.70#ibcon#read 6, iclass 34, count 2 2006.285.18:43:23.70#ibcon#end of sib2, iclass 34, count 2 2006.285.18:43:23.70#ibcon#*mode == 0, iclass 34, count 2 2006.285.18:43:23.70#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.18:43:23.70#ibcon#[25=AT07-04\r\n] 2006.285.18:43:23.70#ibcon#*before write, iclass 34, count 2 2006.285.18:43:23.70#ibcon#enter sib2, iclass 34, count 2 2006.285.18:43:23.70#ibcon#flushed, iclass 34, count 2 2006.285.18:43:23.70#ibcon#about to write, iclass 34, count 2 2006.285.18:43:23.70#ibcon#wrote, iclass 34, count 2 2006.285.18:43:23.70#ibcon#about to read 3, iclass 34, count 2 2006.285.18:43:23.73#ibcon#read 3, iclass 34, count 2 2006.285.18:43:23.73#ibcon#about to read 4, iclass 34, count 2 2006.285.18:43:23.73#ibcon#read 4, iclass 34, count 2 2006.285.18:43:23.73#ibcon#about to read 5, iclass 34, count 2 2006.285.18:43:23.73#ibcon#read 5, iclass 34, count 2 2006.285.18:43:23.73#ibcon#about to read 6, iclass 34, count 2 2006.285.18:43:23.73#ibcon#read 6, iclass 34, count 2 2006.285.18:43:23.73#ibcon#end of sib2, iclass 34, count 2 2006.285.18:43:23.73#ibcon#*after write, iclass 34, count 2 2006.285.18:43:23.73#ibcon#*before return 0, iclass 34, count 2 2006.285.18:43:23.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:43:23.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:43:23.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.18:43:23.73#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:23.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:43:23.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:43:23.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:43:23.85#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:43:23.85#ibcon#first serial, iclass 34, count 0 2006.285.18:43:23.85#ibcon#enter sib2, iclass 34, count 0 2006.285.18:43:23.85#ibcon#flushed, iclass 34, count 0 2006.285.18:43:23.85#ibcon#about to write, iclass 34, count 0 2006.285.18:43:23.85#ibcon#wrote, iclass 34, count 0 2006.285.18:43:23.85#ibcon#about to read 3, iclass 34, count 0 2006.285.18:43:23.87#ibcon#read 3, iclass 34, count 0 2006.285.18:43:23.87#ibcon#about to read 4, iclass 34, count 0 2006.285.18:43:23.87#ibcon#read 4, iclass 34, count 0 2006.285.18:43:23.87#ibcon#about to read 5, iclass 34, count 0 2006.285.18:43:23.87#ibcon#read 5, iclass 34, count 0 2006.285.18:43:23.87#ibcon#about to read 6, iclass 34, count 0 2006.285.18:43:23.87#ibcon#read 6, iclass 34, count 0 2006.285.18:43:23.87#ibcon#end of sib2, iclass 34, count 0 2006.285.18:43:23.87#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:43:23.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:43:23.87#ibcon#[25=USB\r\n] 2006.285.18:43:23.87#ibcon#*before write, iclass 34, count 0 2006.285.18:43:23.87#ibcon#enter sib2, iclass 34, count 0 2006.285.18:43:23.87#ibcon#flushed, iclass 34, count 0 2006.285.18:43:23.87#ibcon#about to write, iclass 34, count 0 2006.285.18:43:23.87#ibcon#wrote, iclass 34, count 0 2006.285.18:43:23.87#ibcon#about to read 3, iclass 34, count 0 2006.285.18:43:23.90#ibcon#read 3, iclass 34, count 0 2006.285.18:43:23.90#ibcon#about to read 4, iclass 34, count 0 2006.285.18:43:23.90#ibcon#read 4, iclass 34, count 0 2006.285.18:43:23.90#ibcon#about to read 5, iclass 34, count 0 2006.285.18:43:23.90#ibcon#read 5, iclass 34, count 0 2006.285.18:43:23.90#ibcon#about to read 6, iclass 34, count 0 2006.285.18:43:23.90#ibcon#read 6, iclass 34, count 0 2006.285.18:43:23.90#ibcon#end of sib2, iclass 34, count 0 2006.285.18:43:23.90#ibcon#*after write, iclass 34, count 0 2006.285.18:43:23.90#ibcon#*before return 0, iclass 34, count 0 2006.285.18:43:23.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:43:23.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:43:23.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:43:23.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:43:23.90$vck44/valo=8,884.99 2006.285.18:43:23.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.18:43:23.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.18:43:23.90#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:23.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:43:23.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:43:23.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:43:23.90#ibcon#enter wrdev, iclass 36, count 0 2006.285.18:43:23.90#ibcon#first serial, iclass 36, count 0 2006.285.18:43:23.90#ibcon#enter sib2, iclass 36, count 0 2006.285.18:43:23.90#ibcon#flushed, iclass 36, count 0 2006.285.18:43:23.90#ibcon#about to write, iclass 36, count 0 2006.285.18:43:23.90#ibcon#wrote, iclass 36, count 0 2006.285.18:43:23.90#ibcon#about to read 3, iclass 36, count 0 2006.285.18:43:23.92#ibcon#read 3, iclass 36, count 0 2006.285.18:43:23.92#ibcon#about to read 4, iclass 36, count 0 2006.285.18:43:23.92#ibcon#read 4, iclass 36, count 0 2006.285.18:43:23.92#ibcon#about to read 5, iclass 36, count 0 2006.285.18:43:23.92#ibcon#read 5, iclass 36, count 0 2006.285.18:43:23.92#ibcon#about to read 6, iclass 36, count 0 2006.285.18:43:23.92#ibcon#read 6, iclass 36, count 0 2006.285.18:43:23.92#ibcon#end of sib2, iclass 36, count 0 2006.285.18:43:23.92#ibcon#*mode == 0, iclass 36, count 0 2006.285.18:43:23.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.18:43:23.92#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.18:43:23.92#ibcon#*before write, iclass 36, count 0 2006.285.18:43:23.92#ibcon#enter sib2, iclass 36, count 0 2006.285.18:43:23.92#ibcon#flushed, iclass 36, count 0 2006.285.18:43:23.92#ibcon#about to write, iclass 36, count 0 2006.285.18:43:23.92#ibcon#wrote, iclass 36, count 0 2006.285.18:43:23.92#ibcon#about to read 3, iclass 36, count 0 2006.285.18:43:23.96#ibcon#read 3, iclass 36, count 0 2006.285.18:43:23.96#ibcon#about to read 4, iclass 36, count 0 2006.285.18:43:23.96#ibcon#read 4, iclass 36, count 0 2006.285.18:43:23.96#ibcon#about to read 5, iclass 36, count 0 2006.285.18:43:23.96#ibcon#read 5, iclass 36, count 0 2006.285.18:43:23.96#ibcon#about to read 6, iclass 36, count 0 2006.285.18:43:23.96#ibcon#read 6, iclass 36, count 0 2006.285.18:43:23.96#ibcon#end of sib2, iclass 36, count 0 2006.285.18:43:23.96#ibcon#*after write, iclass 36, count 0 2006.285.18:43:23.96#ibcon#*before return 0, iclass 36, count 0 2006.285.18:43:23.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:43:23.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:43:23.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.18:43:23.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.18:43:23.96$vck44/va=8,3 2006.285.18:43:23.96#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.18:43:23.96#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.18:43:23.96#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:23.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:43:24.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:43:24.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:43:24.02#ibcon#enter wrdev, iclass 38, count 2 2006.285.18:43:24.02#ibcon#first serial, iclass 38, count 2 2006.285.18:43:24.02#ibcon#enter sib2, iclass 38, count 2 2006.285.18:43:24.02#ibcon#flushed, iclass 38, count 2 2006.285.18:43:24.02#ibcon#about to write, iclass 38, count 2 2006.285.18:43:24.02#ibcon#wrote, iclass 38, count 2 2006.285.18:43:24.02#ibcon#about to read 3, iclass 38, count 2 2006.285.18:43:24.04#ibcon#read 3, iclass 38, count 2 2006.285.18:43:24.04#ibcon#about to read 4, iclass 38, count 2 2006.285.18:43:24.04#ibcon#read 4, iclass 38, count 2 2006.285.18:43:24.04#ibcon#about to read 5, iclass 38, count 2 2006.285.18:43:24.04#ibcon#read 5, iclass 38, count 2 2006.285.18:43:24.04#ibcon#about to read 6, iclass 38, count 2 2006.285.18:43:24.04#ibcon#read 6, iclass 38, count 2 2006.285.18:43:24.04#ibcon#end of sib2, iclass 38, count 2 2006.285.18:43:24.04#ibcon#*mode == 0, iclass 38, count 2 2006.285.18:43:24.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.18:43:24.04#ibcon#[25=AT08-03\r\n] 2006.285.18:43:24.04#ibcon#*before write, iclass 38, count 2 2006.285.18:43:24.04#ibcon#enter sib2, iclass 38, count 2 2006.285.18:43:24.04#ibcon#flushed, iclass 38, count 2 2006.285.18:43:24.04#ibcon#about to write, iclass 38, count 2 2006.285.18:43:24.04#ibcon#wrote, iclass 38, count 2 2006.285.18:43:24.04#ibcon#about to read 3, iclass 38, count 2 2006.285.18:43:24.07#ibcon#read 3, iclass 38, count 2 2006.285.18:43:24.07#ibcon#about to read 4, iclass 38, count 2 2006.285.18:43:24.07#ibcon#read 4, iclass 38, count 2 2006.285.18:43:24.07#ibcon#about to read 5, iclass 38, count 2 2006.285.18:43:24.07#ibcon#read 5, iclass 38, count 2 2006.285.18:43:24.07#ibcon#about to read 6, iclass 38, count 2 2006.285.18:43:24.07#ibcon#read 6, iclass 38, count 2 2006.285.18:43:24.07#ibcon#end of sib2, iclass 38, count 2 2006.285.18:43:24.07#ibcon#*after write, iclass 38, count 2 2006.285.18:43:24.07#ibcon#*before return 0, iclass 38, count 2 2006.285.18:43:24.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:43:24.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.18:43:24.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.18:43:24.07#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:24.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:43:24.19#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:43:24.19#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:43:24.19#ibcon#enter wrdev, iclass 38, count 0 2006.285.18:43:24.19#ibcon#first serial, iclass 38, count 0 2006.285.18:43:24.19#ibcon#enter sib2, iclass 38, count 0 2006.285.18:43:24.19#ibcon#flushed, iclass 38, count 0 2006.285.18:43:24.19#ibcon#about to write, iclass 38, count 0 2006.285.18:43:24.19#ibcon#wrote, iclass 38, count 0 2006.285.18:43:24.19#ibcon#about to read 3, iclass 38, count 0 2006.285.18:43:24.21#ibcon#read 3, iclass 38, count 0 2006.285.18:43:24.21#ibcon#about to read 4, iclass 38, count 0 2006.285.18:43:24.21#ibcon#read 4, iclass 38, count 0 2006.285.18:43:24.21#ibcon#about to read 5, iclass 38, count 0 2006.285.18:43:24.21#ibcon#read 5, iclass 38, count 0 2006.285.18:43:24.21#ibcon#about to read 6, iclass 38, count 0 2006.285.18:43:24.21#ibcon#read 6, iclass 38, count 0 2006.285.18:43:24.21#ibcon#end of sib2, iclass 38, count 0 2006.285.18:43:24.21#ibcon#*mode == 0, iclass 38, count 0 2006.285.18:43:24.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.18:43:24.21#ibcon#[25=USB\r\n] 2006.285.18:43:24.21#ibcon#*before write, iclass 38, count 0 2006.285.18:43:24.21#ibcon#enter sib2, iclass 38, count 0 2006.285.18:43:24.21#ibcon#flushed, iclass 38, count 0 2006.285.18:43:24.21#ibcon#about to write, iclass 38, count 0 2006.285.18:43:24.21#ibcon#wrote, iclass 38, count 0 2006.285.18:43:24.21#ibcon#about to read 3, iclass 38, count 0 2006.285.18:43:24.24#ibcon#read 3, iclass 38, count 0 2006.285.18:43:24.24#ibcon#about to read 4, iclass 38, count 0 2006.285.18:43:24.24#ibcon#read 4, iclass 38, count 0 2006.285.18:43:24.24#ibcon#about to read 5, iclass 38, count 0 2006.285.18:43:24.24#ibcon#read 5, iclass 38, count 0 2006.285.18:43:24.24#ibcon#about to read 6, iclass 38, count 0 2006.285.18:43:24.24#ibcon#read 6, iclass 38, count 0 2006.285.18:43:24.24#ibcon#end of sib2, iclass 38, count 0 2006.285.18:43:24.24#ibcon#*after write, iclass 38, count 0 2006.285.18:43:24.24#ibcon#*before return 0, iclass 38, count 0 2006.285.18:43:24.24#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:43:24.24#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.18:43:24.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.18:43:24.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.18:43:24.24$vck44/vblo=1,629.99 2006.285.18:43:24.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.18:43:24.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.18:43:24.24#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:24.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:43:24.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:43:24.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:43:24.24#ibcon#enter wrdev, iclass 40, count 0 2006.285.18:43:24.24#ibcon#first serial, iclass 40, count 0 2006.285.18:43:24.24#ibcon#enter sib2, iclass 40, count 0 2006.285.18:43:24.24#ibcon#flushed, iclass 40, count 0 2006.285.18:43:24.24#ibcon#about to write, iclass 40, count 0 2006.285.18:43:24.24#ibcon#wrote, iclass 40, count 0 2006.285.18:43:24.24#ibcon#about to read 3, iclass 40, count 0 2006.285.18:43:24.26#ibcon#read 3, iclass 40, count 0 2006.285.18:43:24.26#ibcon#about to read 4, iclass 40, count 0 2006.285.18:43:24.26#ibcon#read 4, iclass 40, count 0 2006.285.18:43:24.26#ibcon#about to read 5, iclass 40, count 0 2006.285.18:43:24.26#ibcon#read 5, iclass 40, count 0 2006.285.18:43:24.26#ibcon#about to read 6, iclass 40, count 0 2006.285.18:43:24.26#ibcon#read 6, iclass 40, count 0 2006.285.18:43:24.26#ibcon#end of sib2, iclass 40, count 0 2006.285.18:43:24.26#ibcon#*mode == 0, iclass 40, count 0 2006.285.18:43:24.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.18:43:24.26#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.18:43:24.26#ibcon#*before write, iclass 40, count 0 2006.285.18:43:24.26#ibcon#enter sib2, iclass 40, count 0 2006.285.18:43:24.26#ibcon#flushed, iclass 40, count 0 2006.285.18:43:24.26#ibcon#about to write, iclass 40, count 0 2006.285.18:43:24.26#ibcon#wrote, iclass 40, count 0 2006.285.18:43:24.26#ibcon#about to read 3, iclass 40, count 0 2006.285.18:43:24.30#ibcon#read 3, iclass 40, count 0 2006.285.18:43:24.30#ibcon#about to read 4, iclass 40, count 0 2006.285.18:43:24.30#ibcon#read 4, iclass 40, count 0 2006.285.18:43:24.30#ibcon#about to read 5, iclass 40, count 0 2006.285.18:43:24.30#ibcon#read 5, iclass 40, count 0 2006.285.18:43:24.30#ibcon#about to read 6, iclass 40, count 0 2006.285.18:43:24.30#ibcon#read 6, iclass 40, count 0 2006.285.18:43:24.30#ibcon#end of sib2, iclass 40, count 0 2006.285.18:43:24.30#ibcon#*after write, iclass 40, count 0 2006.285.18:43:24.30#ibcon#*before return 0, iclass 40, count 0 2006.285.18:43:24.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:43:24.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.18:43:24.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.18:43:24.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.18:43:24.30$vck44/vb=1,4 2006.285.18:43:24.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.18:43:24.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.18:43:24.30#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:24.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:43:24.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:43:24.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:43:24.30#ibcon#enter wrdev, iclass 4, count 2 2006.285.18:43:24.30#ibcon#first serial, iclass 4, count 2 2006.285.18:43:24.30#ibcon#enter sib2, iclass 4, count 2 2006.285.18:43:24.30#ibcon#flushed, iclass 4, count 2 2006.285.18:43:24.30#ibcon#about to write, iclass 4, count 2 2006.285.18:43:24.30#ibcon#wrote, iclass 4, count 2 2006.285.18:43:24.30#ibcon#about to read 3, iclass 4, count 2 2006.285.18:43:24.32#ibcon#read 3, iclass 4, count 2 2006.285.18:43:24.32#ibcon#about to read 4, iclass 4, count 2 2006.285.18:43:24.32#ibcon#read 4, iclass 4, count 2 2006.285.18:43:24.32#ibcon#about to read 5, iclass 4, count 2 2006.285.18:43:24.32#ibcon#read 5, iclass 4, count 2 2006.285.18:43:24.32#ibcon#about to read 6, iclass 4, count 2 2006.285.18:43:24.32#ibcon#read 6, iclass 4, count 2 2006.285.18:43:24.32#ibcon#end of sib2, iclass 4, count 2 2006.285.18:43:24.32#ibcon#*mode == 0, iclass 4, count 2 2006.285.18:43:24.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.18:43:24.32#ibcon#[27=AT01-04\r\n] 2006.285.18:43:24.32#ibcon#*before write, iclass 4, count 2 2006.285.18:43:24.32#ibcon#enter sib2, iclass 4, count 2 2006.285.18:43:24.32#ibcon#flushed, iclass 4, count 2 2006.285.18:43:24.32#ibcon#about to write, iclass 4, count 2 2006.285.18:43:24.32#ibcon#wrote, iclass 4, count 2 2006.285.18:43:24.32#ibcon#about to read 3, iclass 4, count 2 2006.285.18:43:24.35#ibcon#read 3, iclass 4, count 2 2006.285.18:43:24.35#ibcon#about to read 4, iclass 4, count 2 2006.285.18:43:24.35#ibcon#read 4, iclass 4, count 2 2006.285.18:43:24.35#ibcon#about to read 5, iclass 4, count 2 2006.285.18:43:24.35#ibcon#read 5, iclass 4, count 2 2006.285.18:43:24.35#ibcon#about to read 6, iclass 4, count 2 2006.285.18:43:24.35#ibcon#read 6, iclass 4, count 2 2006.285.18:43:24.35#ibcon#end of sib2, iclass 4, count 2 2006.285.18:43:24.35#ibcon#*after write, iclass 4, count 2 2006.285.18:43:24.35#ibcon#*before return 0, iclass 4, count 2 2006.285.18:43:24.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:43:24.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.18:43:24.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.18:43:24.35#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:24.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:43:24.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:43:24.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:43:24.47#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:43:24.47#ibcon#first serial, iclass 4, count 0 2006.285.18:43:24.47#ibcon#enter sib2, iclass 4, count 0 2006.285.18:43:24.47#ibcon#flushed, iclass 4, count 0 2006.285.18:43:24.47#ibcon#about to write, iclass 4, count 0 2006.285.18:43:24.47#ibcon#wrote, iclass 4, count 0 2006.285.18:43:24.47#ibcon#about to read 3, iclass 4, count 0 2006.285.18:43:24.49#ibcon#read 3, iclass 4, count 0 2006.285.18:43:24.49#ibcon#about to read 4, iclass 4, count 0 2006.285.18:43:24.49#ibcon#read 4, iclass 4, count 0 2006.285.18:43:24.49#ibcon#about to read 5, iclass 4, count 0 2006.285.18:43:24.49#ibcon#read 5, iclass 4, count 0 2006.285.18:43:24.49#ibcon#about to read 6, iclass 4, count 0 2006.285.18:43:24.49#ibcon#read 6, iclass 4, count 0 2006.285.18:43:24.49#ibcon#end of sib2, iclass 4, count 0 2006.285.18:43:24.49#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:43:24.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:43:24.49#ibcon#[27=USB\r\n] 2006.285.18:43:24.49#ibcon#*before write, iclass 4, count 0 2006.285.18:43:24.49#ibcon#enter sib2, iclass 4, count 0 2006.285.18:43:24.49#ibcon#flushed, iclass 4, count 0 2006.285.18:43:24.49#ibcon#about to write, iclass 4, count 0 2006.285.18:43:24.49#ibcon#wrote, iclass 4, count 0 2006.285.18:43:24.49#ibcon#about to read 3, iclass 4, count 0 2006.285.18:43:24.52#ibcon#read 3, iclass 4, count 0 2006.285.18:43:24.52#ibcon#about to read 4, iclass 4, count 0 2006.285.18:43:24.52#ibcon#read 4, iclass 4, count 0 2006.285.18:43:24.52#ibcon#about to read 5, iclass 4, count 0 2006.285.18:43:24.52#ibcon#read 5, iclass 4, count 0 2006.285.18:43:24.52#ibcon#about to read 6, iclass 4, count 0 2006.285.18:43:24.52#ibcon#read 6, iclass 4, count 0 2006.285.18:43:24.52#ibcon#end of sib2, iclass 4, count 0 2006.285.18:43:24.52#ibcon#*after write, iclass 4, count 0 2006.285.18:43:24.52#ibcon#*before return 0, iclass 4, count 0 2006.285.18:43:24.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:43:24.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.18:43:24.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:43:24.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:43:24.52$vck44/vblo=2,634.99 2006.285.18:43:24.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.18:43:24.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.18:43:24.52#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:24.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:43:24.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:43:24.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:43:24.52#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:43:24.52#ibcon#first serial, iclass 6, count 0 2006.285.18:43:24.52#ibcon#enter sib2, iclass 6, count 0 2006.285.18:43:24.52#ibcon#flushed, iclass 6, count 0 2006.285.18:43:24.52#ibcon#about to write, iclass 6, count 0 2006.285.18:43:24.52#ibcon#wrote, iclass 6, count 0 2006.285.18:43:24.52#ibcon#about to read 3, iclass 6, count 0 2006.285.18:43:24.54#ibcon#read 3, iclass 6, count 0 2006.285.18:43:24.65#ibcon#about to read 4, iclass 6, count 0 2006.285.18:43:24.65#ibcon#read 4, iclass 6, count 0 2006.285.18:43:24.65#ibcon#about to read 5, iclass 6, count 0 2006.285.18:43:24.65#ibcon#read 5, iclass 6, count 0 2006.285.18:43:24.65#ibcon#about to read 6, iclass 6, count 0 2006.285.18:43:24.65#ibcon#read 6, iclass 6, count 0 2006.285.18:43:24.65#ibcon#end of sib2, iclass 6, count 0 2006.285.18:43:24.65#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:43:24.65#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:43:24.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.18:43:24.65#ibcon#*before write, iclass 6, count 0 2006.285.18:43:24.65#ibcon#enter sib2, iclass 6, count 0 2006.285.18:43:24.65#ibcon#flushed, iclass 6, count 0 2006.285.18:43:24.65#ibcon#about to write, iclass 6, count 0 2006.285.18:43:24.65#ibcon#wrote, iclass 6, count 0 2006.285.18:43:24.65#ibcon#about to read 3, iclass 6, count 0 2006.285.18:43:24.69#ibcon#read 3, iclass 6, count 0 2006.285.18:43:24.69#ibcon#about to read 4, iclass 6, count 0 2006.285.18:43:24.69#ibcon#read 4, iclass 6, count 0 2006.285.18:43:24.69#ibcon#about to read 5, iclass 6, count 0 2006.285.18:43:24.69#ibcon#read 5, iclass 6, count 0 2006.285.18:43:24.69#ibcon#about to read 6, iclass 6, count 0 2006.285.18:43:24.69#ibcon#read 6, iclass 6, count 0 2006.285.18:43:24.69#ibcon#end of sib2, iclass 6, count 0 2006.285.18:43:24.69#ibcon#*after write, iclass 6, count 0 2006.285.18:43:24.69#ibcon#*before return 0, iclass 6, count 0 2006.285.18:43:24.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:43:24.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.18:43:24.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:43:24.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:43:24.69$vck44/vb=2,5 2006.285.18:43:24.69#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.18:43:24.69#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.18:43:24.69#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:24.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:43:24.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:43:24.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:43:24.69#ibcon#enter wrdev, iclass 10, count 2 2006.285.18:43:24.69#ibcon#first serial, iclass 10, count 2 2006.285.18:43:24.69#ibcon#enter sib2, iclass 10, count 2 2006.285.18:43:24.69#ibcon#flushed, iclass 10, count 2 2006.285.18:43:24.69#ibcon#about to write, iclass 10, count 2 2006.285.18:43:24.69#ibcon#wrote, iclass 10, count 2 2006.285.18:43:24.69#ibcon#about to read 3, iclass 10, count 2 2006.285.18:43:24.71#ibcon#read 3, iclass 10, count 2 2006.285.18:43:24.71#ibcon#about to read 4, iclass 10, count 2 2006.285.18:43:24.71#ibcon#read 4, iclass 10, count 2 2006.285.18:43:24.71#ibcon#about to read 5, iclass 10, count 2 2006.285.18:43:24.71#ibcon#read 5, iclass 10, count 2 2006.285.18:43:24.71#ibcon#about to read 6, iclass 10, count 2 2006.285.18:43:24.71#ibcon#read 6, iclass 10, count 2 2006.285.18:43:24.71#ibcon#end of sib2, iclass 10, count 2 2006.285.18:43:24.71#ibcon#*mode == 0, iclass 10, count 2 2006.285.18:43:24.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.18:43:24.71#ibcon#[27=AT02-05\r\n] 2006.285.18:43:24.71#ibcon#*before write, iclass 10, count 2 2006.285.18:43:24.71#ibcon#enter sib2, iclass 10, count 2 2006.285.18:43:24.71#ibcon#flushed, iclass 10, count 2 2006.285.18:43:24.71#ibcon#about to write, iclass 10, count 2 2006.285.18:43:24.71#ibcon#wrote, iclass 10, count 2 2006.285.18:43:24.71#ibcon#about to read 3, iclass 10, count 2 2006.285.18:43:24.74#ibcon#read 3, iclass 10, count 2 2006.285.18:43:24.74#ibcon#about to read 4, iclass 10, count 2 2006.285.18:43:24.74#ibcon#read 4, iclass 10, count 2 2006.285.18:43:24.74#ibcon#about to read 5, iclass 10, count 2 2006.285.18:43:24.74#ibcon#read 5, iclass 10, count 2 2006.285.18:43:24.74#ibcon#about to read 6, iclass 10, count 2 2006.285.18:43:24.74#ibcon#read 6, iclass 10, count 2 2006.285.18:43:24.74#ibcon#end of sib2, iclass 10, count 2 2006.285.18:43:24.74#ibcon#*after write, iclass 10, count 2 2006.285.18:43:24.74#ibcon#*before return 0, iclass 10, count 2 2006.285.18:43:24.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:43:24.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.18:43:24.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.18:43:24.74#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:24.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:43:24.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:43:24.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:43:24.86#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:43:24.86#ibcon#first serial, iclass 10, count 0 2006.285.18:43:24.86#ibcon#enter sib2, iclass 10, count 0 2006.285.18:43:24.86#ibcon#flushed, iclass 10, count 0 2006.285.18:43:24.86#ibcon#about to write, iclass 10, count 0 2006.285.18:43:24.86#ibcon#wrote, iclass 10, count 0 2006.285.18:43:24.86#ibcon#about to read 3, iclass 10, count 0 2006.285.18:43:24.88#ibcon#read 3, iclass 10, count 0 2006.285.18:43:24.88#ibcon#about to read 4, iclass 10, count 0 2006.285.18:43:24.88#ibcon#read 4, iclass 10, count 0 2006.285.18:43:24.88#ibcon#about to read 5, iclass 10, count 0 2006.285.18:43:24.88#ibcon#read 5, iclass 10, count 0 2006.285.18:43:24.88#ibcon#about to read 6, iclass 10, count 0 2006.285.18:43:24.88#ibcon#read 6, iclass 10, count 0 2006.285.18:43:24.88#ibcon#end of sib2, iclass 10, count 0 2006.285.18:43:24.88#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:43:24.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:43:24.88#ibcon#[27=USB\r\n] 2006.285.18:43:24.88#ibcon#*before write, iclass 10, count 0 2006.285.18:43:24.88#ibcon#enter sib2, iclass 10, count 0 2006.285.18:43:24.88#ibcon#flushed, iclass 10, count 0 2006.285.18:43:24.88#ibcon#about to write, iclass 10, count 0 2006.285.18:43:24.88#ibcon#wrote, iclass 10, count 0 2006.285.18:43:24.88#ibcon#about to read 3, iclass 10, count 0 2006.285.18:43:24.91#ibcon#read 3, iclass 10, count 0 2006.285.18:43:24.91#ibcon#about to read 4, iclass 10, count 0 2006.285.18:43:24.91#ibcon#read 4, iclass 10, count 0 2006.285.18:43:24.91#ibcon#about to read 5, iclass 10, count 0 2006.285.18:43:24.91#ibcon#read 5, iclass 10, count 0 2006.285.18:43:24.91#ibcon#about to read 6, iclass 10, count 0 2006.285.18:43:24.91#ibcon#read 6, iclass 10, count 0 2006.285.18:43:24.91#ibcon#end of sib2, iclass 10, count 0 2006.285.18:43:24.91#ibcon#*after write, iclass 10, count 0 2006.285.18:43:24.91#ibcon#*before return 0, iclass 10, count 0 2006.285.18:43:24.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:43:24.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.18:43:24.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:43:24.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:43:24.91$vck44/vblo=3,649.99 2006.285.18:43:24.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.18:43:24.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.18:43:24.91#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:24.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:43:24.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:43:24.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:43:24.91#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:43:24.91#ibcon#first serial, iclass 12, count 0 2006.285.18:43:24.91#ibcon#enter sib2, iclass 12, count 0 2006.285.18:43:24.91#ibcon#flushed, iclass 12, count 0 2006.285.18:43:24.91#ibcon#about to write, iclass 12, count 0 2006.285.18:43:24.91#ibcon#wrote, iclass 12, count 0 2006.285.18:43:24.91#ibcon#about to read 3, iclass 12, count 0 2006.285.18:43:24.93#ibcon#read 3, iclass 12, count 0 2006.285.18:43:24.93#ibcon#about to read 4, iclass 12, count 0 2006.285.18:43:24.93#ibcon#read 4, iclass 12, count 0 2006.285.18:43:24.93#ibcon#about to read 5, iclass 12, count 0 2006.285.18:43:24.93#ibcon#read 5, iclass 12, count 0 2006.285.18:43:24.93#ibcon#about to read 6, iclass 12, count 0 2006.285.18:43:24.93#ibcon#read 6, iclass 12, count 0 2006.285.18:43:24.93#ibcon#end of sib2, iclass 12, count 0 2006.285.18:43:24.93#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:43:24.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:43:24.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.18:43:24.93#ibcon#*before write, iclass 12, count 0 2006.285.18:43:24.93#ibcon#enter sib2, iclass 12, count 0 2006.285.18:43:24.93#ibcon#flushed, iclass 12, count 0 2006.285.18:43:24.93#ibcon#about to write, iclass 12, count 0 2006.285.18:43:24.93#ibcon#wrote, iclass 12, count 0 2006.285.18:43:24.93#ibcon#about to read 3, iclass 12, count 0 2006.285.18:43:24.97#ibcon#read 3, iclass 12, count 0 2006.285.18:43:24.97#ibcon#about to read 4, iclass 12, count 0 2006.285.18:43:24.97#ibcon#read 4, iclass 12, count 0 2006.285.18:43:24.97#ibcon#about to read 5, iclass 12, count 0 2006.285.18:43:24.97#ibcon#read 5, iclass 12, count 0 2006.285.18:43:24.97#ibcon#about to read 6, iclass 12, count 0 2006.285.18:43:24.97#ibcon#read 6, iclass 12, count 0 2006.285.18:43:24.97#ibcon#end of sib2, iclass 12, count 0 2006.285.18:43:24.97#ibcon#*after write, iclass 12, count 0 2006.285.18:43:24.97#ibcon#*before return 0, iclass 12, count 0 2006.285.18:43:24.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:43:24.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.18:43:24.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:43:24.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:43:24.97$vck44/vb=3,4 2006.285.18:43:24.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.18:43:24.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.18:43:24.97#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:24.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:43:25.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:43:25.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:43:25.03#ibcon#enter wrdev, iclass 14, count 2 2006.285.18:43:25.03#ibcon#first serial, iclass 14, count 2 2006.285.18:43:25.03#ibcon#enter sib2, iclass 14, count 2 2006.285.18:43:25.03#ibcon#flushed, iclass 14, count 2 2006.285.18:43:25.03#ibcon#about to write, iclass 14, count 2 2006.285.18:43:25.03#ibcon#wrote, iclass 14, count 2 2006.285.18:43:25.03#ibcon#about to read 3, iclass 14, count 2 2006.285.18:43:25.05#ibcon#read 3, iclass 14, count 2 2006.285.18:43:25.05#ibcon#about to read 4, iclass 14, count 2 2006.285.18:43:25.05#ibcon#read 4, iclass 14, count 2 2006.285.18:43:25.05#ibcon#about to read 5, iclass 14, count 2 2006.285.18:43:25.05#ibcon#read 5, iclass 14, count 2 2006.285.18:43:25.05#ibcon#about to read 6, iclass 14, count 2 2006.285.18:43:25.05#ibcon#read 6, iclass 14, count 2 2006.285.18:43:25.05#ibcon#end of sib2, iclass 14, count 2 2006.285.18:43:25.05#ibcon#*mode == 0, iclass 14, count 2 2006.285.18:43:25.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.18:43:25.05#ibcon#[27=AT03-04\r\n] 2006.285.18:43:25.05#ibcon#*before write, iclass 14, count 2 2006.285.18:43:25.05#ibcon#enter sib2, iclass 14, count 2 2006.285.18:43:25.05#ibcon#flushed, iclass 14, count 2 2006.285.18:43:25.05#ibcon#about to write, iclass 14, count 2 2006.285.18:43:25.05#ibcon#wrote, iclass 14, count 2 2006.285.18:43:25.05#ibcon#about to read 3, iclass 14, count 2 2006.285.18:43:25.08#ibcon#read 3, iclass 14, count 2 2006.285.18:43:25.08#ibcon#about to read 4, iclass 14, count 2 2006.285.18:43:25.08#ibcon#read 4, iclass 14, count 2 2006.285.18:43:25.08#ibcon#about to read 5, iclass 14, count 2 2006.285.18:43:25.08#ibcon#read 5, iclass 14, count 2 2006.285.18:43:25.08#ibcon#about to read 6, iclass 14, count 2 2006.285.18:43:25.08#ibcon#read 6, iclass 14, count 2 2006.285.18:43:25.08#ibcon#end of sib2, iclass 14, count 2 2006.285.18:43:25.08#ibcon#*after write, iclass 14, count 2 2006.285.18:43:25.08#ibcon#*before return 0, iclass 14, count 2 2006.285.18:43:25.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:43:25.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.18:43:25.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.18:43:25.08#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:25.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:43:25.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:43:25.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:43:25.20#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:43:25.20#ibcon#first serial, iclass 14, count 0 2006.285.18:43:25.20#ibcon#enter sib2, iclass 14, count 0 2006.285.18:43:25.20#ibcon#flushed, iclass 14, count 0 2006.285.18:43:25.20#ibcon#about to write, iclass 14, count 0 2006.285.18:43:25.20#ibcon#wrote, iclass 14, count 0 2006.285.18:43:25.20#ibcon#about to read 3, iclass 14, count 0 2006.285.18:43:25.22#ibcon#read 3, iclass 14, count 0 2006.285.18:43:25.22#ibcon#about to read 4, iclass 14, count 0 2006.285.18:43:25.22#ibcon#read 4, iclass 14, count 0 2006.285.18:43:25.22#ibcon#about to read 5, iclass 14, count 0 2006.285.18:43:25.22#ibcon#read 5, iclass 14, count 0 2006.285.18:43:25.22#ibcon#about to read 6, iclass 14, count 0 2006.285.18:43:25.22#ibcon#read 6, iclass 14, count 0 2006.285.18:43:25.22#ibcon#end of sib2, iclass 14, count 0 2006.285.18:43:25.22#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:43:25.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:43:25.22#ibcon#[27=USB\r\n] 2006.285.18:43:25.22#ibcon#*before write, iclass 14, count 0 2006.285.18:43:25.22#ibcon#enter sib2, iclass 14, count 0 2006.285.18:43:25.22#ibcon#flushed, iclass 14, count 0 2006.285.18:43:25.22#ibcon#about to write, iclass 14, count 0 2006.285.18:43:25.22#ibcon#wrote, iclass 14, count 0 2006.285.18:43:25.22#ibcon#about to read 3, iclass 14, count 0 2006.285.18:43:25.25#ibcon#read 3, iclass 14, count 0 2006.285.18:43:25.25#ibcon#about to read 4, iclass 14, count 0 2006.285.18:43:25.25#ibcon#read 4, iclass 14, count 0 2006.285.18:43:25.25#ibcon#about to read 5, iclass 14, count 0 2006.285.18:43:25.25#ibcon#read 5, iclass 14, count 0 2006.285.18:43:25.25#ibcon#about to read 6, iclass 14, count 0 2006.285.18:43:25.25#ibcon#read 6, iclass 14, count 0 2006.285.18:43:25.25#ibcon#end of sib2, iclass 14, count 0 2006.285.18:43:25.25#ibcon#*after write, iclass 14, count 0 2006.285.18:43:25.25#ibcon#*before return 0, iclass 14, count 0 2006.285.18:43:25.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:43:25.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.18:43:25.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:43:25.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:43:25.25$vck44/vblo=4,679.99 2006.285.18:43:25.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.18:43:25.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.18:43:25.25#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:25.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:43:25.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:43:25.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:43:25.25#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:43:25.25#ibcon#first serial, iclass 16, count 0 2006.285.18:43:25.25#ibcon#enter sib2, iclass 16, count 0 2006.285.18:43:25.25#ibcon#flushed, iclass 16, count 0 2006.285.18:43:25.25#ibcon#about to write, iclass 16, count 0 2006.285.18:43:25.25#ibcon#wrote, iclass 16, count 0 2006.285.18:43:25.25#ibcon#about to read 3, iclass 16, count 0 2006.285.18:43:25.27#ibcon#read 3, iclass 16, count 0 2006.285.18:43:25.27#ibcon#about to read 4, iclass 16, count 0 2006.285.18:43:25.27#ibcon#read 4, iclass 16, count 0 2006.285.18:43:25.27#ibcon#about to read 5, iclass 16, count 0 2006.285.18:43:25.27#ibcon#read 5, iclass 16, count 0 2006.285.18:43:25.27#ibcon#about to read 6, iclass 16, count 0 2006.285.18:43:25.27#ibcon#read 6, iclass 16, count 0 2006.285.18:43:25.27#ibcon#end of sib2, iclass 16, count 0 2006.285.18:43:25.27#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:43:25.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:43:25.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.18:43:25.27#ibcon#*before write, iclass 16, count 0 2006.285.18:43:25.27#ibcon#enter sib2, iclass 16, count 0 2006.285.18:43:25.27#ibcon#flushed, iclass 16, count 0 2006.285.18:43:25.27#ibcon#about to write, iclass 16, count 0 2006.285.18:43:25.27#ibcon#wrote, iclass 16, count 0 2006.285.18:43:25.27#ibcon#about to read 3, iclass 16, count 0 2006.285.18:43:25.31#ibcon#read 3, iclass 16, count 0 2006.285.18:43:25.31#ibcon#about to read 4, iclass 16, count 0 2006.285.18:43:25.31#ibcon#read 4, iclass 16, count 0 2006.285.18:43:25.31#ibcon#about to read 5, iclass 16, count 0 2006.285.18:43:25.31#ibcon#read 5, iclass 16, count 0 2006.285.18:43:25.31#ibcon#about to read 6, iclass 16, count 0 2006.285.18:43:25.31#ibcon#read 6, iclass 16, count 0 2006.285.18:43:25.31#ibcon#end of sib2, iclass 16, count 0 2006.285.18:43:25.31#ibcon#*after write, iclass 16, count 0 2006.285.18:43:25.31#ibcon#*before return 0, iclass 16, count 0 2006.285.18:43:25.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:43:25.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.18:43:25.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:43:25.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:43:25.31$vck44/vb=4,5 2006.285.18:43:25.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.18:43:25.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.18:43:25.31#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:25.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:43:25.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:43:25.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:43:25.37#ibcon#enter wrdev, iclass 18, count 2 2006.285.18:43:25.37#ibcon#first serial, iclass 18, count 2 2006.285.18:43:25.37#ibcon#enter sib2, iclass 18, count 2 2006.285.18:43:25.37#ibcon#flushed, iclass 18, count 2 2006.285.18:43:25.37#ibcon#about to write, iclass 18, count 2 2006.285.18:43:25.37#ibcon#wrote, iclass 18, count 2 2006.285.18:43:25.37#ibcon#about to read 3, iclass 18, count 2 2006.285.18:43:25.39#ibcon#read 3, iclass 18, count 2 2006.285.18:43:25.39#ibcon#about to read 4, iclass 18, count 2 2006.285.18:43:25.39#ibcon#read 4, iclass 18, count 2 2006.285.18:43:25.39#ibcon#about to read 5, iclass 18, count 2 2006.285.18:43:25.39#ibcon#read 5, iclass 18, count 2 2006.285.18:43:25.39#ibcon#about to read 6, iclass 18, count 2 2006.285.18:43:25.39#ibcon#read 6, iclass 18, count 2 2006.285.18:43:25.39#ibcon#end of sib2, iclass 18, count 2 2006.285.18:43:25.39#ibcon#*mode == 0, iclass 18, count 2 2006.285.18:43:25.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.18:43:25.39#ibcon#[27=AT04-05\r\n] 2006.285.18:43:25.39#ibcon#*before write, iclass 18, count 2 2006.285.18:43:25.39#ibcon#enter sib2, iclass 18, count 2 2006.285.18:43:25.39#ibcon#flushed, iclass 18, count 2 2006.285.18:43:25.39#ibcon#about to write, iclass 18, count 2 2006.285.18:43:25.39#ibcon#wrote, iclass 18, count 2 2006.285.18:43:25.39#ibcon#about to read 3, iclass 18, count 2 2006.285.18:43:25.42#ibcon#read 3, iclass 18, count 2 2006.285.18:43:25.42#ibcon#about to read 4, iclass 18, count 2 2006.285.18:43:25.42#ibcon#read 4, iclass 18, count 2 2006.285.18:43:25.42#ibcon#about to read 5, iclass 18, count 2 2006.285.18:43:25.42#ibcon#read 5, iclass 18, count 2 2006.285.18:43:25.42#ibcon#about to read 6, iclass 18, count 2 2006.285.18:43:25.42#ibcon#read 6, iclass 18, count 2 2006.285.18:43:25.42#ibcon#end of sib2, iclass 18, count 2 2006.285.18:43:25.42#ibcon#*after write, iclass 18, count 2 2006.285.18:43:25.42#ibcon#*before return 0, iclass 18, count 2 2006.285.18:43:25.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:43:25.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.18:43:25.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.18:43:25.42#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:25.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:43:25.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:43:25.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:43:25.54#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:43:25.54#ibcon#first serial, iclass 18, count 0 2006.285.18:43:25.54#ibcon#enter sib2, iclass 18, count 0 2006.285.18:43:25.54#ibcon#flushed, iclass 18, count 0 2006.285.18:43:25.54#ibcon#about to write, iclass 18, count 0 2006.285.18:43:25.54#ibcon#wrote, iclass 18, count 0 2006.285.18:43:25.54#ibcon#about to read 3, iclass 18, count 0 2006.285.18:43:25.56#ibcon#read 3, iclass 18, count 0 2006.285.18:43:25.56#ibcon#about to read 4, iclass 18, count 0 2006.285.18:43:25.56#ibcon#read 4, iclass 18, count 0 2006.285.18:43:25.56#ibcon#about to read 5, iclass 18, count 0 2006.285.18:43:25.56#ibcon#read 5, iclass 18, count 0 2006.285.18:43:25.56#ibcon#about to read 6, iclass 18, count 0 2006.285.18:43:25.56#ibcon#read 6, iclass 18, count 0 2006.285.18:43:25.56#ibcon#end of sib2, iclass 18, count 0 2006.285.18:43:25.56#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:43:25.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:43:25.56#ibcon#[27=USB\r\n] 2006.285.18:43:25.56#ibcon#*before write, iclass 18, count 0 2006.285.18:43:25.56#ibcon#enter sib2, iclass 18, count 0 2006.285.18:43:25.56#ibcon#flushed, iclass 18, count 0 2006.285.18:43:25.56#ibcon#about to write, iclass 18, count 0 2006.285.18:43:25.56#ibcon#wrote, iclass 18, count 0 2006.285.18:43:25.56#ibcon#about to read 3, iclass 18, count 0 2006.285.18:43:25.59#ibcon#read 3, iclass 18, count 0 2006.285.18:43:25.59#ibcon#about to read 4, iclass 18, count 0 2006.285.18:43:25.59#ibcon#read 4, iclass 18, count 0 2006.285.18:43:25.59#ibcon#about to read 5, iclass 18, count 0 2006.285.18:43:25.59#ibcon#read 5, iclass 18, count 0 2006.285.18:43:25.59#ibcon#about to read 6, iclass 18, count 0 2006.285.18:43:25.59#ibcon#read 6, iclass 18, count 0 2006.285.18:43:25.59#ibcon#end of sib2, iclass 18, count 0 2006.285.18:43:25.59#ibcon#*after write, iclass 18, count 0 2006.285.18:43:25.59#ibcon#*before return 0, iclass 18, count 0 2006.285.18:43:25.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:43:25.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.18:43:25.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:43:25.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:43:25.59$vck44/vblo=5,709.99 2006.285.18:43:25.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.18:43:25.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.18:43:25.59#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:25.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:43:25.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:43:25.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:43:25.59#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:43:25.59#ibcon#first serial, iclass 20, count 0 2006.285.18:43:25.59#ibcon#enter sib2, iclass 20, count 0 2006.285.18:43:25.59#ibcon#flushed, iclass 20, count 0 2006.285.18:43:25.59#ibcon#about to write, iclass 20, count 0 2006.285.18:43:25.59#ibcon#wrote, iclass 20, count 0 2006.285.18:43:25.59#ibcon#about to read 3, iclass 20, count 0 2006.285.18:43:25.61#ibcon#read 3, iclass 20, count 0 2006.285.18:43:25.69#ibcon#about to read 4, iclass 20, count 0 2006.285.18:43:25.69#ibcon#read 4, iclass 20, count 0 2006.285.18:43:25.69#ibcon#about to read 5, iclass 20, count 0 2006.285.18:43:25.69#ibcon#read 5, iclass 20, count 0 2006.285.18:43:25.69#ibcon#about to read 6, iclass 20, count 0 2006.285.18:43:25.69#ibcon#read 6, iclass 20, count 0 2006.285.18:43:25.69#ibcon#end of sib2, iclass 20, count 0 2006.285.18:43:25.69#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:43:25.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:43:25.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.18:43:25.69#ibcon#*before write, iclass 20, count 0 2006.285.18:43:25.69#ibcon#enter sib2, iclass 20, count 0 2006.285.18:43:25.69#ibcon#flushed, iclass 20, count 0 2006.285.18:43:25.69#ibcon#about to write, iclass 20, count 0 2006.285.18:43:25.69#ibcon#wrote, iclass 20, count 0 2006.285.18:43:25.69#ibcon#about to read 3, iclass 20, count 0 2006.285.18:43:25.73#ibcon#read 3, iclass 20, count 0 2006.285.18:43:25.73#ibcon#about to read 4, iclass 20, count 0 2006.285.18:43:25.73#ibcon#read 4, iclass 20, count 0 2006.285.18:43:25.73#ibcon#about to read 5, iclass 20, count 0 2006.285.18:43:25.73#ibcon#read 5, iclass 20, count 0 2006.285.18:43:25.73#ibcon#about to read 6, iclass 20, count 0 2006.285.18:43:25.73#ibcon#read 6, iclass 20, count 0 2006.285.18:43:25.73#ibcon#end of sib2, iclass 20, count 0 2006.285.18:43:25.73#ibcon#*after write, iclass 20, count 0 2006.285.18:43:25.73#ibcon#*before return 0, iclass 20, count 0 2006.285.18:43:25.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:43:25.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.18:43:25.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:43:25.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:43:25.73$vck44/vb=5,4 2006.285.18:43:25.73#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.18:43:25.73#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.18:43:25.73#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:25.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:43:25.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:43:25.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:43:25.73#ibcon#enter wrdev, iclass 22, count 2 2006.285.18:43:25.73#ibcon#first serial, iclass 22, count 2 2006.285.18:43:25.73#ibcon#enter sib2, iclass 22, count 2 2006.285.18:43:25.73#ibcon#flushed, iclass 22, count 2 2006.285.18:43:25.73#ibcon#about to write, iclass 22, count 2 2006.285.18:43:25.73#ibcon#wrote, iclass 22, count 2 2006.285.18:43:25.73#ibcon#about to read 3, iclass 22, count 2 2006.285.18:43:25.75#ibcon#read 3, iclass 22, count 2 2006.285.18:43:25.75#ibcon#about to read 4, iclass 22, count 2 2006.285.18:43:25.75#ibcon#read 4, iclass 22, count 2 2006.285.18:43:25.75#ibcon#about to read 5, iclass 22, count 2 2006.285.18:43:25.75#ibcon#read 5, iclass 22, count 2 2006.285.18:43:25.75#ibcon#about to read 6, iclass 22, count 2 2006.285.18:43:25.75#ibcon#read 6, iclass 22, count 2 2006.285.18:43:25.75#ibcon#end of sib2, iclass 22, count 2 2006.285.18:43:25.75#ibcon#*mode == 0, iclass 22, count 2 2006.285.18:43:25.75#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.18:43:25.75#ibcon#[27=AT05-04\r\n] 2006.285.18:43:25.75#ibcon#*before write, iclass 22, count 2 2006.285.18:43:25.75#ibcon#enter sib2, iclass 22, count 2 2006.285.18:43:25.75#ibcon#flushed, iclass 22, count 2 2006.285.18:43:25.75#ibcon#about to write, iclass 22, count 2 2006.285.18:43:25.75#ibcon#wrote, iclass 22, count 2 2006.285.18:43:25.75#ibcon#about to read 3, iclass 22, count 2 2006.285.18:43:25.78#ibcon#read 3, iclass 22, count 2 2006.285.18:43:25.78#ibcon#about to read 4, iclass 22, count 2 2006.285.18:43:25.78#ibcon#read 4, iclass 22, count 2 2006.285.18:43:25.78#ibcon#about to read 5, iclass 22, count 2 2006.285.18:43:25.78#ibcon#read 5, iclass 22, count 2 2006.285.18:43:25.78#ibcon#about to read 6, iclass 22, count 2 2006.285.18:43:25.78#ibcon#read 6, iclass 22, count 2 2006.285.18:43:25.78#ibcon#end of sib2, iclass 22, count 2 2006.285.18:43:25.78#ibcon#*after write, iclass 22, count 2 2006.285.18:43:25.78#ibcon#*before return 0, iclass 22, count 2 2006.285.18:43:25.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:43:25.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.18:43:25.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.18:43:25.78#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:25.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:43:25.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:43:25.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:43:25.90#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:43:25.90#ibcon#first serial, iclass 22, count 0 2006.285.18:43:25.90#ibcon#enter sib2, iclass 22, count 0 2006.285.18:43:25.90#ibcon#flushed, iclass 22, count 0 2006.285.18:43:25.90#ibcon#about to write, iclass 22, count 0 2006.285.18:43:25.90#ibcon#wrote, iclass 22, count 0 2006.285.18:43:25.90#ibcon#about to read 3, iclass 22, count 0 2006.285.18:43:25.92#ibcon#read 3, iclass 22, count 0 2006.285.18:43:25.92#ibcon#about to read 4, iclass 22, count 0 2006.285.18:43:25.92#ibcon#read 4, iclass 22, count 0 2006.285.18:43:25.92#ibcon#about to read 5, iclass 22, count 0 2006.285.18:43:25.92#ibcon#read 5, iclass 22, count 0 2006.285.18:43:25.92#ibcon#about to read 6, iclass 22, count 0 2006.285.18:43:25.92#ibcon#read 6, iclass 22, count 0 2006.285.18:43:25.92#ibcon#end of sib2, iclass 22, count 0 2006.285.18:43:25.92#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:43:25.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:43:25.92#ibcon#[27=USB\r\n] 2006.285.18:43:25.92#ibcon#*before write, iclass 22, count 0 2006.285.18:43:25.92#ibcon#enter sib2, iclass 22, count 0 2006.285.18:43:25.92#ibcon#flushed, iclass 22, count 0 2006.285.18:43:25.92#ibcon#about to write, iclass 22, count 0 2006.285.18:43:25.92#ibcon#wrote, iclass 22, count 0 2006.285.18:43:25.92#ibcon#about to read 3, iclass 22, count 0 2006.285.18:43:25.95#ibcon#read 3, iclass 22, count 0 2006.285.18:43:25.95#ibcon#about to read 4, iclass 22, count 0 2006.285.18:43:25.95#ibcon#read 4, iclass 22, count 0 2006.285.18:43:25.95#ibcon#about to read 5, iclass 22, count 0 2006.285.18:43:25.95#ibcon#read 5, iclass 22, count 0 2006.285.18:43:25.95#ibcon#about to read 6, iclass 22, count 0 2006.285.18:43:25.95#ibcon#read 6, iclass 22, count 0 2006.285.18:43:25.95#ibcon#end of sib2, iclass 22, count 0 2006.285.18:43:25.95#ibcon#*after write, iclass 22, count 0 2006.285.18:43:25.95#ibcon#*before return 0, iclass 22, count 0 2006.285.18:43:25.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:43:25.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.18:43:25.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:43:25.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:43:25.95$vck44/vblo=6,719.99 2006.285.18:43:25.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.18:43:25.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.18:43:25.95#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:25.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:43:25.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:43:25.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:43:25.95#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:43:25.95#ibcon#first serial, iclass 24, count 0 2006.285.18:43:25.95#ibcon#enter sib2, iclass 24, count 0 2006.285.18:43:25.95#ibcon#flushed, iclass 24, count 0 2006.285.18:43:25.95#ibcon#about to write, iclass 24, count 0 2006.285.18:43:25.95#ibcon#wrote, iclass 24, count 0 2006.285.18:43:25.95#ibcon#about to read 3, iclass 24, count 0 2006.285.18:43:25.97#ibcon#read 3, iclass 24, count 0 2006.285.18:43:25.97#ibcon#about to read 4, iclass 24, count 0 2006.285.18:43:25.97#ibcon#read 4, iclass 24, count 0 2006.285.18:43:25.97#ibcon#about to read 5, iclass 24, count 0 2006.285.18:43:25.97#ibcon#read 5, iclass 24, count 0 2006.285.18:43:25.97#ibcon#about to read 6, iclass 24, count 0 2006.285.18:43:25.97#ibcon#read 6, iclass 24, count 0 2006.285.18:43:25.97#ibcon#end of sib2, iclass 24, count 0 2006.285.18:43:25.97#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:43:25.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:43:25.97#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.18:43:25.97#ibcon#*before write, iclass 24, count 0 2006.285.18:43:25.97#ibcon#enter sib2, iclass 24, count 0 2006.285.18:43:25.97#ibcon#flushed, iclass 24, count 0 2006.285.18:43:25.97#ibcon#about to write, iclass 24, count 0 2006.285.18:43:25.97#ibcon#wrote, iclass 24, count 0 2006.285.18:43:25.97#ibcon#about to read 3, iclass 24, count 0 2006.285.18:43:26.01#ibcon#read 3, iclass 24, count 0 2006.285.18:43:26.01#ibcon#about to read 4, iclass 24, count 0 2006.285.18:43:26.01#ibcon#read 4, iclass 24, count 0 2006.285.18:43:26.01#ibcon#about to read 5, iclass 24, count 0 2006.285.18:43:26.01#ibcon#read 5, iclass 24, count 0 2006.285.18:43:26.01#ibcon#about to read 6, iclass 24, count 0 2006.285.18:43:26.01#ibcon#read 6, iclass 24, count 0 2006.285.18:43:26.01#ibcon#end of sib2, iclass 24, count 0 2006.285.18:43:26.01#ibcon#*after write, iclass 24, count 0 2006.285.18:43:26.01#ibcon#*before return 0, iclass 24, count 0 2006.285.18:43:26.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:43:26.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.18:43:26.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:43:26.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:43:26.01$vck44/vb=6,3 2006.285.18:43:26.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.18:43:26.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.18:43:26.01#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:26.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:43:26.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:43:26.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:43:26.07#ibcon#enter wrdev, iclass 26, count 2 2006.285.18:43:26.07#ibcon#first serial, iclass 26, count 2 2006.285.18:43:26.07#ibcon#enter sib2, iclass 26, count 2 2006.285.18:43:26.07#ibcon#flushed, iclass 26, count 2 2006.285.18:43:26.07#ibcon#about to write, iclass 26, count 2 2006.285.18:43:26.07#ibcon#wrote, iclass 26, count 2 2006.285.18:43:26.07#ibcon#about to read 3, iclass 26, count 2 2006.285.18:43:26.09#ibcon#read 3, iclass 26, count 2 2006.285.18:43:26.09#ibcon#about to read 4, iclass 26, count 2 2006.285.18:43:26.09#ibcon#read 4, iclass 26, count 2 2006.285.18:43:26.09#ibcon#about to read 5, iclass 26, count 2 2006.285.18:43:26.09#ibcon#read 5, iclass 26, count 2 2006.285.18:43:26.09#ibcon#about to read 6, iclass 26, count 2 2006.285.18:43:26.09#ibcon#read 6, iclass 26, count 2 2006.285.18:43:26.09#ibcon#end of sib2, iclass 26, count 2 2006.285.18:43:26.09#ibcon#*mode == 0, iclass 26, count 2 2006.285.18:43:26.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.18:43:26.09#ibcon#[27=AT06-03\r\n] 2006.285.18:43:26.09#ibcon#*before write, iclass 26, count 2 2006.285.18:43:26.09#ibcon#enter sib2, iclass 26, count 2 2006.285.18:43:26.09#ibcon#flushed, iclass 26, count 2 2006.285.18:43:26.09#ibcon#about to write, iclass 26, count 2 2006.285.18:43:26.09#ibcon#wrote, iclass 26, count 2 2006.285.18:43:26.09#ibcon#about to read 3, iclass 26, count 2 2006.285.18:43:26.12#ibcon#read 3, iclass 26, count 2 2006.285.18:43:26.12#ibcon#about to read 4, iclass 26, count 2 2006.285.18:43:26.12#ibcon#read 4, iclass 26, count 2 2006.285.18:43:26.12#ibcon#about to read 5, iclass 26, count 2 2006.285.18:43:26.12#ibcon#read 5, iclass 26, count 2 2006.285.18:43:26.12#ibcon#about to read 6, iclass 26, count 2 2006.285.18:43:26.12#ibcon#read 6, iclass 26, count 2 2006.285.18:43:26.12#ibcon#end of sib2, iclass 26, count 2 2006.285.18:43:26.12#ibcon#*after write, iclass 26, count 2 2006.285.18:43:26.12#ibcon#*before return 0, iclass 26, count 2 2006.285.18:43:26.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:43:26.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.18:43:26.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.18:43:26.12#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:26.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:43:26.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:43:26.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:43:26.24#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:43:26.24#ibcon#first serial, iclass 26, count 0 2006.285.18:43:26.24#ibcon#enter sib2, iclass 26, count 0 2006.285.18:43:26.24#ibcon#flushed, iclass 26, count 0 2006.285.18:43:26.24#ibcon#about to write, iclass 26, count 0 2006.285.18:43:26.24#ibcon#wrote, iclass 26, count 0 2006.285.18:43:26.24#ibcon#about to read 3, iclass 26, count 0 2006.285.18:43:26.26#ibcon#read 3, iclass 26, count 0 2006.285.18:43:26.26#ibcon#about to read 4, iclass 26, count 0 2006.285.18:43:26.26#ibcon#read 4, iclass 26, count 0 2006.285.18:43:26.26#ibcon#about to read 5, iclass 26, count 0 2006.285.18:43:26.26#ibcon#read 5, iclass 26, count 0 2006.285.18:43:26.26#ibcon#about to read 6, iclass 26, count 0 2006.285.18:43:26.26#ibcon#read 6, iclass 26, count 0 2006.285.18:43:26.26#ibcon#end of sib2, iclass 26, count 0 2006.285.18:43:26.26#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:43:26.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:43:26.26#ibcon#[27=USB\r\n] 2006.285.18:43:26.26#ibcon#*before write, iclass 26, count 0 2006.285.18:43:26.26#ibcon#enter sib2, iclass 26, count 0 2006.285.18:43:26.26#ibcon#flushed, iclass 26, count 0 2006.285.18:43:26.26#ibcon#about to write, iclass 26, count 0 2006.285.18:43:26.26#ibcon#wrote, iclass 26, count 0 2006.285.18:43:26.26#ibcon#about to read 3, iclass 26, count 0 2006.285.18:43:26.29#ibcon#read 3, iclass 26, count 0 2006.285.18:43:26.29#ibcon#about to read 4, iclass 26, count 0 2006.285.18:43:26.29#ibcon#read 4, iclass 26, count 0 2006.285.18:43:26.29#ibcon#about to read 5, iclass 26, count 0 2006.285.18:43:26.29#ibcon#read 5, iclass 26, count 0 2006.285.18:43:26.29#ibcon#about to read 6, iclass 26, count 0 2006.285.18:43:26.29#ibcon#read 6, iclass 26, count 0 2006.285.18:43:26.29#ibcon#end of sib2, iclass 26, count 0 2006.285.18:43:26.29#ibcon#*after write, iclass 26, count 0 2006.285.18:43:26.29#ibcon#*before return 0, iclass 26, count 0 2006.285.18:43:26.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:43:26.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.18:43:26.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:43:26.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:43:26.29$vck44/vblo=7,734.99 2006.285.18:43:26.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.18:43:26.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.18:43:26.29#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:26.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:43:26.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:43:26.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:43:26.29#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:43:26.29#ibcon#first serial, iclass 28, count 0 2006.285.18:43:26.29#ibcon#enter sib2, iclass 28, count 0 2006.285.18:43:26.29#ibcon#flushed, iclass 28, count 0 2006.285.18:43:26.29#ibcon#about to write, iclass 28, count 0 2006.285.18:43:26.29#ibcon#wrote, iclass 28, count 0 2006.285.18:43:26.29#ibcon#about to read 3, iclass 28, count 0 2006.285.18:43:26.31#ibcon#read 3, iclass 28, count 0 2006.285.18:43:26.31#ibcon#about to read 4, iclass 28, count 0 2006.285.18:43:26.31#ibcon#read 4, iclass 28, count 0 2006.285.18:43:26.31#ibcon#about to read 5, iclass 28, count 0 2006.285.18:43:26.31#ibcon#read 5, iclass 28, count 0 2006.285.18:43:26.31#ibcon#about to read 6, iclass 28, count 0 2006.285.18:43:26.31#ibcon#read 6, iclass 28, count 0 2006.285.18:43:26.31#ibcon#end of sib2, iclass 28, count 0 2006.285.18:43:26.31#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:43:26.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:43:26.31#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.18:43:26.31#ibcon#*before write, iclass 28, count 0 2006.285.18:43:26.31#ibcon#enter sib2, iclass 28, count 0 2006.285.18:43:26.31#ibcon#flushed, iclass 28, count 0 2006.285.18:43:26.31#ibcon#about to write, iclass 28, count 0 2006.285.18:43:26.31#ibcon#wrote, iclass 28, count 0 2006.285.18:43:26.31#ibcon#about to read 3, iclass 28, count 0 2006.285.18:43:26.35#ibcon#read 3, iclass 28, count 0 2006.285.18:43:26.35#ibcon#about to read 4, iclass 28, count 0 2006.285.18:43:26.35#ibcon#read 4, iclass 28, count 0 2006.285.18:43:26.35#ibcon#about to read 5, iclass 28, count 0 2006.285.18:43:26.35#ibcon#read 5, iclass 28, count 0 2006.285.18:43:26.35#ibcon#about to read 6, iclass 28, count 0 2006.285.18:43:26.35#ibcon#read 6, iclass 28, count 0 2006.285.18:43:26.35#ibcon#end of sib2, iclass 28, count 0 2006.285.18:43:26.35#ibcon#*after write, iclass 28, count 0 2006.285.18:43:26.35#ibcon#*before return 0, iclass 28, count 0 2006.285.18:43:26.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:43:26.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.18:43:26.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:43:26.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:43:26.35$vck44/vb=7,4 2006.285.18:43:26.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.18:43:26.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.18:43:26.35#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:26.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:43:26.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:43:26.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:43:26.41#ibcon#enter wrdev, iclass 30, count 2 2006.285.18:43:26.41#ibcon#first serial, iclass 30, count 2 2006.285.18:43:26.41#ibcon#enter sib2, iclass 30, count 2 2006.285.18:43:26.41#ibcon#flushed, iclass 30, count 2 2006.285.18:43:26.41#ibcon#about to write, iclass 30, count 2 2006.285.18:43:26.41#ibcon#wrote, iclass 30, count 2 2006.285.18:43:26.41#ibcon#about to read 3, iclass 30, count 2 2006.285.18:43:26.43#ibcon#read 3, iclass 30, count 2 2006.285.18:43:26.43#ibcon#about to read 4, iclass 30, count 2 2006.285.18:43:26.43#ibcon#read 4, iclass 30, count 2 2006.285.18:43:26.43#ibcon#about to read 5, iclass 30, count 2 2006.285.18:43:26.43#ibcon#read 5, iclass 30, count 2 2006.285.18:43:26.43#ibcon#about to read 6, iclass 30, count 2 2006.285.18:43:26.43#ibcon#read 6, iclass 30, count 2 2006.285.18:43:26.43#ibcon#end of sib2, iclass 30, count 2 2006.285.18:43:26.43#ibcon#*mode == 0, iclass 30, count 2 2006.285.18:43:26.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.18:43:26.43#ibcon#[27=AT07-04\r\n] 2006.285.18:43:26.43#ibcon#*before write, iclass 30, count 2 2006.285.18:43:26.43#ibcon#enter sib2, iclass 30, count 2 2006.285.18:43:26.43#ibcon#flushed, iclass 30, count 2 2006.285.18:43:26.43#ibcon#about to write, iclass 30, count 2 2006.285.18:43:26.43#ibcon#wrote, iclass 30, count 2 2006.285.18:43:26.43#ibcon#about to read 3, iclass 30, count 2 2006.285.18:43:26.46#ibcon#read 3, iclass 30, count 2 2006.285.18:43:26.46#ibcon#about to read 4, iclass 30, count 2 2006.285.18:43:26.46#ibcon#read 4, iclass 30, count 2 2006.285.18:43:26.46#ibcon#about to read 5, iclass 30, count 2 2006.285.18:43:26.46#ibcon#read 5, iclass 30, count 2 2006.285.18:43:26.46#ibcon#about to read 6, iclass 30, count 2 2006.285.18:43:26.46#ibcon#read 6, iclass 30, count 2 2006.285.18:43:26.46#ibcon#end of sib2, iclass 30, count 2 2006.285.18:43:26.46#ibcon#*after write, iclass 30, count 2 2006.285.18:43:26.46#ibcon#*before return 0, iclass 30, count 2 2006.285.18:43:26.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:43:26.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.18:43:26.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.18:43:26.46#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:26.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:43:26.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:43:26.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:43:26.58#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:43:26.58#ibcon#first serial, iclass 30, count 0 2006.285.18:43:26.58#ibcon#enter sib2, iclass 30, count 0 2006.285.18:43:26.58#ibcon#flushed, iclass 30, count 0 2006.285.18:43:26.58#ibcon#about to write, iclass 30, count 0 2006.285.18:43:26.58#ibcon#wrote, iclass 30, count 0 2006.285.18:43:26.58#ibcon#about to read 3, iclass 30, count 0 2006.285.18:43:26.60#ibcon#read 3, iclass 30, count 0 2006.285.18:43:26.60#ibcon#about to read 4, iclass 30, count 0 2006.285.18:43:26.60#ibcon#read 4, iclass 30, count 0 2006.285.18:43:26.60#ibcon#about to read 5, iclass 30, count 0 2006.285.18:43:26.60#ibcon#read 5, iclass 30, count 0 2006.285.18:43:26.60#ibcon#about to read 6, iclass 30, count 0 2006.285.18:43:26.60#ibcon#read 6, iclass 30, count 0 2006.285.18:43:26.60#ibcon#end of sib2, iclass 30, count 0 2006.285.18:43:26.60#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:43:26.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:43:26.60#ibcon#[27=USB\r\n] 2006.285.18:43:26.60#ibcon#*before write, iclass 30, count 0 2006.285.18:43:26.60#ibcon#enter sib2, iclass 30, count 0 2006.285.18:43:26.60#ibcon#flushed, iclass 30, count 0 2006.285.18:43:26.60#ibcon#about to write, iclass 30, count 0 2006.285.18:43:26.60#ibcon#wrote, iclass 30, count 0 2006.285.18:43:26.60#ibcon#about to read 3, iclass 30, count 0 2006.285.18:43:26.63#ibcon#read 3, iclass 30, count 0 2006.285.18:43:26.63#ibcon#about to read 4, iclass 30, count 0 2006.285.18:43:26.63#ibcon#read 4, iclass 30, count 0 2006.285.18:43:26.63#ibcon#about to read 5, iclass 30, count 0 2006.285.18:43:26.63#ibcon#read 5, iclass 30, count 0 2006.285.18:43:26.63#ibcon#about to read 6, iclass 30, count 0 2006.285.18:43:26.63#ibcon#read 6, iclass 30, count 0 2006.285.18:43:26.63#ibcon#end of sib2, iclass 30, count 0 2006.285.18:43:26.63#ibcon#*after write, iclass 30, count 0 2006.285.18:43:26.63#ibcon#*before return 0, iclass 30, count 0 2006.285.18:43:26.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:43:26.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.18:43:26.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:43:26.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:43:26.63$vck44/vblo=8,744.99 2006.285.18:43:26.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.18:43:26.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.18:43:26.63#ibcon#ireg 17 cls_cnt 0 2006.285.18:43:26.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:43:26.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:43:26.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:43:26.63#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:43:26.63#ibcon#first serial, iclass 32, count 0 2006.285.18:43:26.63#ibcon#enter sib2, iclass 32, count 0 2006.285.18:43:26.63#ibcon#flushed, iclass 32, count 0 2006.285.18:43:26.63#ibcon#about to write, iclass 32, count 0 2006.285.18:43:26.63#ibcon#wrote, iclass 32, count 0 2006.285.18:43:26.63#ibcon#about to read 3, iclass 32, count 0 2006.285.18:43:26.65#ibcon#read 3, iclass 32, count 0 2006.285.18:43:26.75#ibcon#about to read 4, iclass 32, count 0 2006.285.18:43:26.75#ibcon#read 4, iclass 32, count 0 2006.285.18:43:26.75#ibcon#about to read 5, iclass 32, count 0 2006.285.18:43:26.75#ibcon#read 5, iclass 32, count 0 2006.285.18:43:26.75#ibcon#about to read 6, iclass 32, count 0 2006.285.18:43:26.75#ibcon#read 6, iclass 32, count 0 2006.285.18:43:26.75#ibcon#end of sib2, iclass 32, count 0 2006.285.18:43:26.75#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:43:26.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:43:26.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.18:43:26.75#ibcon#*before write, iclass 32, count 0 2006.285.18:43:26.75#ibcon#enter sib2, iclass 32, count 0 2006.285.18:43:26.75#ibcon#flushed, iclass 32, count 0 2006.285.18:43:26.75#ibcon#about to write, iclass 32, count 0 2006.285.18:43:26.75#ibcon#wrote, iclass 32, count 0 2006.285.18:43:26.75#ibcon#about to read 3, iclass 32, count 0 2006.285.18:43:26.79#ibcon#read 3, iclass 32, count 0 2006.285.18:43:26.79#ibcon#about to read 4, iclass 32, count 0 2006.285.18:43:26.79#ibcon#read 4, iclass 32, count 0 2006.285.18:43:26.79#ibcon#about to read 5, iclass 32, count 0 2006.285.18:43:26.79#ibcon#read 5, iclass 32, count 0 2006.285.18:43:26.79#ibcon#about to read 6, iclass 32, count 0 2006.285.18:43:26.79#ibcon#read 6, iclass 32, count 0 2006.285.18:43:26.79#ibcon#end of sib2, iclass 32, count 0 2006.285.18:43:26.79#ibcon#*after write, iclass 32, count 0 2006.285.18:43:26.79#ibcon#*before return 0, iclass 32, count 0 2006.285.18:43:26.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:43:26.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:43:26.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:43:26.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:43:26.79$vck44/vb=8,4 2006.285.18:43:26.79#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.18:43:26.79#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.18:43:26.79#ibcon#ireg 11 cls_cnt 2 2006.285.18:43:26.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:43:26.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:43:26.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:43:26.79#ibcon#enter wrdev, iclass 34, count 2 2006.285.18:43:26.79#ibcon#first serial, iclass 34, count 2 2006.285.18:43:26.79#ibcon#enter sib2, iclass 34, count 2 2006.285.18:43:26.79#ibcon#flushed, iclass 34, count 2 2006.285.18:43:26.79#ibcon#about to write, iclass 34, count 2 2006.285.18:43:26.79#ibcon#wrote, iclass 34, count 2 2006.285.18:43:26.79#ibcon#about to read 3, iclass 34, count 2 2006.285.18:43:26.81#ibcon#read 3, iclass 34, count 2 2006.285.18:43:26.81#ibcon#about to read 4, iclass 34, count 2 2006.285.18:43:26.81#ibcon#read 4, iclass 34, count 2 2006.285.18:43:26.81#ibcon#about to read 5, iclass 34, count 2 2006.285.18:43:26.81#ibcon#read 5, iclass 34, count 2 2006.285.18:43:26.81#ibcon#about to read 6, iclass 34, count 2 2006.285.18:43:26.81#ibcon#read 6, iclass 34, count 2 2006.285.18:43:26.81#ibcon#end of sib2, iclass 34, count 2 2006.285.18:43:26.81#ibcon#*mode == 0, iclass 34, count 2 2006.285.18:43:26.81#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.18:43:26.81#ibcon#[27=AT08-04\r\n] 2006.285.18:43:26.81#ibcon#*before write, iclass 34, count 2 2006.285.18:43:26.81#ibcon#enter sib2, iclass 34, count 2 2006.285.18:43:26.81#ibcon#flushed, iclass 34, count 2 2006.285.18:43:26.81#ibcon#about to write, iclass 34, count 2 2006.285.18:43:26.81#ibcon#wrote, iclass 34, count 2 2006.285.18:43:26.81#ibcon#about to read 3, iclass 34, count 2 2006.285.18:43:26.84#ibcon#read 3, iclass 34, count 2 2006.285.18:43:26.84#ibcon#about to read 4, iclass 34, count 2 2006.285.18:43:26.84#ibcon#read 4, iclass 34, count 2 2006.285.18:43:26.84#ibcon#about to read 5, iclass 34, count 2 2006.285.18:43:26.84#ibcon#read 5, iclass 34, count 2 2006.285.18:43:26.84#ibcon#about to read 6, iclass 34, count 2 2006.285.18:43:26.84#ibcon#read 6, iclass 34, count 2 2006.285.18:43:26.84#ibcon#end of sib2, iclass 34, count 2 2006.285.18:43:26.84#ibcon#*after write, iclass 34, count 2 2006.285.18:43:26.84#ibcon#*before return 0, iclass 34, count 2 2006.285.18:43:26.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:43:26.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.18:43:26.84#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.18:43:26.84#ibcon#ireg 7 cls_cnt 0 2006.285.18:43:26.84#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:43:26.96#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:43:26.96#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:43:26.96#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:43:26.96#ibcon#first serial, iclass 34, count 0 2006.285.18:43:26.96#ibcon#enter sib2, iclass 34, count 0 2006.285.18:43:26.96#ibcon#flushed, iclass 34, count 0 2006.285.18:43:26.96#ibcon#about to write, iclass 34, count 0 2006.285.18:43:26.96#ibcon#wrote, iclass 34, count 0 2006.285.18:43:26.96#ibcon#about to read 3, iclass 34, count 0 2006.285.18:43:26.98#ibcon#read 3, iclass 34, count 0 2006.285.18:43:26.98#ibcon#about to read 4, iclass 34, count 0 2006.285.18:43:26.98#ibcon#read 4, iclass 34, count 0 2006.285.18:43:26.98#ibcon#about to read 5, iclass 34, count 0 2006.285.18:43:26.98#ibcon#read 5, iclass 34, count 0 2006.285.18:43:26.98#ibcon#about to read 6, iclass 34, count 0 2006.285.18:43:26.98#ibcon#read 6, iclass 34, count 0 2006.285.18:43:26.98#ibcon#end of sib2, iclass 34, count 0 2006.285.18:43:26.98#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:43:26.98#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:43:26.98#ibcon#[27=USB\r\n] 2006.285.18:43:26.98#ibcon#*before write, iclass 34, count 0 2006.285.18:43:26.98#ibcon#enter sib2, iclass 34, count 0 2006.285.18:43:26.98#ibcon#flushed, iclass 34, count 0 2006.285.18:43:26.98#ibcon#about to write, iclass 34, count 0 2006.285.18:43:26.98#ibcon#wrote, iclass 34, count 0 2006.285.18:43:26.98#ibcon#about to read 3, iclass 34, count 0 2006.285.18:43:27.01#ibcon#read 3, iclass 34, count 0 2006.285.18:43:27.01#ibcon#about to read 4, iclass 34, count 0 2006.285.18:43:27.01#ibcon#read 4, iclass 34, count 0 2006.285.18:43:27.01#ibcon#about to read 5, iclass 34, count 0 2006.285.18:43:27.01#ibcon#read 5, iclass 34, count 0 2006.285.18:43:27.01#ibcon#about to read 6, iclass 34, count 0 2006.285.18:43:27.01#ibcon#read 6, iclass 34, count 0 2006.285.18:43:27.01#ibcon#end of sib2, iclass 34, count 0 2006.285.18:43:27.01#ibcon#*after write, iclass 34, count 0 2006.285.18:43:27.01#ibcon#*before return 0, iclass 34, count 0 2006.285.18:43:27.01#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:43:27.01#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.18:43:27.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:43:27.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:43:27.01$vck44/vabw=wide 2006.285.18:43:27.01#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.18:43:27.01#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.18:43:27.01#ibcon#ireg 8 cls_cnt 0 2006.285.18:43:27.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:43:27.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:43:27.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:43:27.01#ibcon#enter wrdev, iclass 36, count 0 2006.285.18:43:27.01#ibcon#first serial, iclass 36, count 0 2006.285.18:43:27.01#ibcon#enter sib2, iclass 36, count 0 2006.285.18:43:27.01#ibcon#flushed, iclass 36, count 0 2006.285.18:43:27.01#ibcon#about to write, iclass 36, count 0 2006.285.18:43:27.01#ibcon#wrote, iclass 36, count 0 2006.285.18:43:27.01#ibcon#about to read 3, iclass 36, count 0 2006.285.18:43:27.03#ibcon#read 3, iclass 36, count 0 2006.285.18:43:27.03#ibcon#about to read 4, iclass 36, count 0 2006.285.18:43:27.03#ibcon#read 4, iclass 36, count 0 2006.285.18:43:27.03#ibcon#about to read 5, iclass 36, count 0 2006.285.18:43:27.03#ibcon#read 5, iclass 36, count 0 2006.285.18:43:27.03#ibcon#about to read 6, iclass 36, count 0 2006.285.18:43:27.03#ibcon#read 6, iclass 36, count 0 2006.285.18:43:27.03#ibcon#end of sib2, iclass 36, count 0 2006.285.18:43:27.03#ibcon#*mode == 0, iclass 36, count 0 2006.285.18:43:27.03#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.18:43:27.03#ibcon#[25=BW32\r\n] 2006.285.18:43:27.03#ibcon#*before write, iclass 36, count 0 2006.285.18:43:27.03#ibcon#enter sib2, iclass 36, count 0 2006.285.18:43:27.03#ibcon#flushed, iclass 36, count 0 2006.285.18:43:27.03#ibcon#about to write, iclass 36, count 0 2006.285.18:43:27.03#ibcon#wrote, iclass 36, count 0 2006.285.18:43:27.03#ibcon#about to read 3, iclass 36, count 0 2006.285.18:43:27.06#ibcon#read 3, iclass 36, count 0 2006.285.18:43:27.06#ibcon#about to read 4, iclass 36, count 0 2006.285.18:43:27.06#ibcon#read 4, iclass 36, count 0 2006.285.18:43:27.06#ibcon#about to read 5, iclass 36, count 0 2006.285.18:43:27.06#ibcon#read 5, iclass 36, count 0 2006.285.18:43:27.06#ibcon#about to read 6, iclass 36, count 0 2006.285.18:43:27.06#ibcon#read 6, iclass 36, count 0 2006.285.18:43:27.06#ibcon#end of sib2, iclass 36, count 0 2006.285.18:43:27.06#ibcon#*after write, iclass 36, count 0 2006.285.18:43:27.06#ibcon#*before return 0, iclass 36, count 0 2006.285.18:43:27.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:43:27.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.18:43:27.06#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.18:43:27.06#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.18:43:27.06$vck44/vbbw=wide 2006.285.18:43:27.06#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.18:43:27.06#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.18:43:27.06#ibcon#ireg 8 cls_cnt 0 2006.285.18:43:27.06#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:43:27.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:43:27.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:43:27.13#ibcon#enter wrdev, iclass 38, count 0 2006.285.18:43:27.13#ibcon#first serial, iclass 38, count 0 2006.285.18:43:27.13#ibcon#enter sib2, iclass 38, count 0 2006.285.18:43:27.13#ibcon#flushed, iclass 38, count 0 2006.285.18:43:27.13#ibcon#about to write, iclass 38, count 0 2006.285.18:43:27.13#ibcon#wrote, iclass 38, count 0 2006.285.18:43:27.13#ibcon#about to read 3, iclass 38, count 0 2006.285.18:43:27.15#ibcon#read 3, iclass 38, count 0 2006.285.18:43:27.15#ibcon#about to read 4, iclass 38, count 0 2006.285.18:43:27.15#ibcon#read 4, iclass 38, count 0 2006.285.18:43:27.15#ibcon#about to read 5, iclass 38, count 0 2006.285.18:43:27.15#ibcon#read 5, iclass 38, count 0 2006.285.18:43:27.15#ibcon#about to read 6, iclass 38, count 0 2006.285.18:43:27.15#ibcon#read 6, iclass 38, count 0 2006.285.18:43:27.15#ibcon#end of sib2, iclass 38, count 0 2006.285.18:43:27.15#ibcon#*mode == 0, iclass 38, count 0 2006.285.18:43:27.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.18:43:27.15#ibcon#[27=BW32\r\n] 2006.285.18:43:27.15#ibcon#*before write, iclass 38, count 0 2006.285.18:43:27.15#ibcon#enter sib2, iclass 38, count 0 2006.285.18:43:27.15#ibcon#flushed, iclass 38, count 0 2006.285.18:43:27.15#ibcon#about to write, iclass 38, count 0 2006.285.18:43:27.15#ibcon#wrote, iclass 38, count 0 2006.285.18:43:27.15#ibcon#about to read 3, iclass 38, count 0 2006.285.18:43:27.18#ibcon#read 3, iclass 38, count 0 2006.285.18:43:27.18#ibcon#about to read 4, iclass 38, count 0 2006.285.18:43:27.18#ibcon#read 4, iclass 38, count 0 2006.285.18:43:27.18#ibcon#about to read 5, iclass 38, count 0 2006.285.18:43:27.18#ibcon#read 5, iclass 38, count 0 2006.285.18:43:27.18#ibcon#about to read 6, iclass 38, count 0 2006.285.18:43:27.18#ibcon#read 6, iclass 38, count 0 2006.285.18:43:27.18#ibcon#end of sib2, iclass 38, count 0 2006.285.18:43:27.18#ibcon#*after write, iclass 38, count 0 2006.285.18:43:27.18#ibcon#*before return 0, iclass 38, count 0 2006.285.18:43:27.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:43:27.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:43:27.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.18:43:27.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.18:43:27.18$setupk4/ifdk4 2006.285.18:43:27.18$ifdk4/lo= 2006.285.18:43:27.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.18:43:27.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.18:43:27.18$ifdk4/patch= 2006.285.18:43:27.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.18:43:27.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.18:43:27.18$setupk4/!*+20s 2006.285.18:43:31.24#abcon#<5=/15 0.4 1.6 15.201001014.8\r\n> 2006.285.18:43:31.26#abcon#{5=INTERFACE CLEAR} 2006.285.18:43:31.32#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:43:40.95$setupk4/"tpicd 2006.285.18:43:40.95$setupk4/echo=off 2006.285.18:43:40.95$setupk4/xlog=off 2006.285.18:43:40.95:!2006.285.18:46:28 2006.285.18:43:46.13#trakl#Source acquired 2006.285.18:43:46.13#flagr#flagr/antenna,acquired 2006.285.18:46:28.00:preob 2006.285.18:46:29.14/onsource/TRACKING 2006.285.18:46:29.14:!2006.285.18:46:38 2006.285.18:46:38.00:"tape 2006.285.18:46:38.00:"st=record 2006.285.18:46:38.00:data_valid=on 2006.285.18:46:38.00:midob 2006.285.18:46:38.14/onsource/TRACKING 2006.285.18:46:38.14/wx/15.14,1014.9,100 2006.285.18:46:38.26/cable/+6.5052E-03 2006.285.18:46:39.35/va/01,07,usb,yes,32,35 2006.285.18:46:39.35/va/02,06,usb,yes,32,33 2006.285.18:46:39.35/va/03,07,usb,yes,32,34 2006.285.18:46:39.35/va/04,06,usb,yes,33,35 2006.285.18:46:39.35/va/05,03,usb,yes,33,33 2006.285.18:46:39.35/va/06,04,usb,yes,29,29 2006.285.18:46:39.35/va/07,04,usb,yes,30,31 2006.285.18:46:39.35/va/08,03,usb,yes,31,37 2006.285.18:46:39.58/valo/01,524.99,yes,locked 2006.285.18:46:39.58/valo/02,534.99,yes,locked 2006.285.18:46:39.58/valo/03,564.99,yes,locked 2006.285.18:46:39.58/valo/04,624.99,yes,locked 2006.285.18:46:39.58/valo/05,734.99,yes,locked 2006.285.18:46:39.58/valo/06,814.99,yes,locked 2006.285.18:46:39.58/valo/07,864.99,yes,locked 2006.285.18:46:39.58/valo/08,884.99,yes,locked 2006.285.18:46:40.67/vb/01,04,usb,yes,30,28 2006.285.18:46:40.67/vb/02,05,usb,yes,28,28 2006.285.18:46:40.67/vb/03,04,usb,yes,29,32 2006.285.18:46:40.67/vb/04,05,usb,yes,29,28 2006.285.18:46:40.67/vb/05,04,usb,yes,26,28 2006.285.18:46:40.67/vb/06,03,usb,yes,37,33 2006.285.18:46:40.67/vb/07,04,usb,yes,30,30 2006.285.18:46:40.67/vb/08,04,usb,yes,27,31 2006.285.18:46:40.91/vblo/01,629.99,yes,locked 2006.285.18:46:40.91/vblo/02,634.99,yes,locked 2006.285.18:46:40.91/vblo/03,649.99,yes,locked 2006.285.18:46:40.91/vblo/04,679.99,yes,locked 2006.285.18:46:40.91/vblo/05,709.99,yes,locked 2006.285.18:46:40.91/vblo/06,719.99,yes,locked 2006.285.18:46:40.91/vblo/07,734.99,yes,locked 2006.285.18:46:40.91/vblo/08,744.99,yes,locked 2006.285.18:46:41.06/vabw/8 2006.285.18:46:41.21/vbbw/8 2006.285.18:46:41.33/xfe/off,on,12.0 2006.285.18:46:41.71/ifatt/23,28,28,28 2006.285.18:46:42.08/fmout-gps/S +2.49E-07 2006.285.18:46:42.10:!2006.285.18:51:38 2006.285.18:51:38.01:data_valid=off 2006.285.18:51:38.01:"et 2006.285.18:51:38.01:!+3s 2006.285.18:51:41.02:"tape 2006.285.18:51:41.02:postob 2006.285.18:51:41.18/cable/+6.5055E-03 2006.285.18:51:41.18/wx/15.07,1014.9,100 2006.285.18:51:42.08/fmout-gps/S +2.49E-07 2006.285.18:51:42.08:scan_name=285-1856,jd0610,40 2006.285.18:51:42.08:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.285.18:51:42.13#flagr#flagr/antenna,new-source 2006.285.18:51:43.13:checkk5 2006.285.18:51:43.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.18:51:44.14/chk_autoobs//k5ts2/ autoobs is running! 2006.285.18:51:44.69/chk_autoobs//k5ts3/ autoobs is running! 2006.285.18:51:45.36/chk_autoobs//k5ts4/ autoobs is running! 2006.285.18:51:45.78/chk_obsdata//k5ts1/T2851846??a.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.285.18:51:46.18/chk_obsdata//k5ts2/T2851846??b.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.285.18:51:46.70/chk_obsdata//k5ts3/T2851846??c.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.285.18:51:47.34/chk_obsdata//k5ts4/T2851846??d.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.285.18:51:48.41/k5log//k5ts1_log_newline 2006.285.18:51:49.16/k5log//k5ts2_log_newline 2006.285.18:51:49.93/k5log//k5ts3_log_newline 2006.285.18:51:50.68/k5log//k5ts4_log_newline 2006.285.18:51:50.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.18:51:50.70:setupk4=1 2006.285.18:51:50.70$setupk4/echo=on 2006.285.18:51:50.70$setupk4/pcalon 2006.285.18:51:50.70$pcalon/"no phase cal control is implemented here 2006.285.18:51:50.70$setupk4/"tpicd=stop 2006.285.18:51:50.70$setupk4/"rec=synch_on 2006.285.18:51:50.70$setupk4/"rec_mode=128 2006.285.18:51:50.70$setupk4/!* 2006.285.18:51:50.70$setupk4/recpk4 2006.285.18:51:50.70$recpk4/recpatch= 2006.285.18:51:50.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.18:51:50.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.18:51:50.70$setupk4/vck44 2006.285.18:51:50.70$vck44/valo=1,524.99 2006.285.18:51:50.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.18:51:50.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.18:51:50.70#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:50.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:51:50.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:51:50.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:51:50.70#ibcon#enter wrdev, iclass 27, count 0 2006.285.18:51:50.70#ibcon#first serial, iclass 27, count 0 2006.285.18:51:50.70#ibcon#enter sib2, iclass 27, count 0 2006.285.18:51:50.70#ibcon#flushed, iclass 27, count 0 2006.285.18:51:50.70#ibcon#about to write, iclass 27, count 0 2006.285.18:51:50.70#ibcon#wrote, iclass 27, count 0 2006.285.18:51:50.70#ibcon#about to read 3, iclass 27, count 0 2006.285.18:51:50.72#ibcon#read 3, iclass 27, count 0 2006.285.18:51:50.72#ibcon#about to read 4, iclass 27, count 0 2006.285.18:51:50.72#ibcon#read 4, iclass 27, count 0 2006.285.18:51:50.72#ibcon#about to read 5, iclass 27, count 0 2006.285.18:51:50.72#ibcon#read 5, iclass 27, count 0 2006.285.18:51:50.72#ibcon#about to read 6, iclass 27, count 0 2006.285.18:51:50.72#ibcon#read 6, iclass 27, count 0 2006.285.18:51:50.72#ibcon#end of sib2, iclass 27, count 0 2006.285.18:51:50.72#ibcon#*mode == 0, iclass 27, count 0 2006.285.18:51:50.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.18:51:50.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.18:51:50.72#ibcon#*before write, iclass 27, count 0 2006.285.18:51:50.72#ibcon#enter sib2, iclass 27, count 0 2006.285.18:51:50.72#ibcon#flushed, iclass 27, count 0 2006.285.18:51:50.72#ibcon#about to write, iclass 27, count 0 2006.285.18:51:50.72#ibcon#wrote, iclass 27, count 0 2006.285.18:51:50.72#ibcon#about to read 3, iclass 27, count 0 2006.285.18:51:50.77#ibcon#read 3, iclass 27, count 0 2006.285.18:51:50.77#ibcon#about to read 4, iclass 27, count 0 2006.285.18:51:50.77#ibcon#read 4, iclass 27, count 0 2006.285.18:51:50.77#ibcon#about to read 5, iclass 27, count 0 2006.285.18:51:50.77#ibcon#read 5, iclass 27, count 0 2006.285.18:51:50.77#ibcon#about to read 6, iclass 27, count 0 2006.285.18:51:50.77#ibcon#read 6, iclass 27, count 0 2006.285.18:51:50.77#ibcon#end of sib2, iclass 27, count 0 2006.285.18:51:50.77#ibcon#*after write, iclass 27, count 0 2006.285.18:51:50.77#ibcon#*before return 0, iclass 27, count 0 2006.285.18:51:50.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:51:50.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:51:50.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.18:51:50.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.18:51:50.77$vck44/va=1,7 2006.285.18:51:50.77#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.18:51:50.77#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.18:51:50.77#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:50.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:51:50.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:51:50.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:51:50.77#ibcon#enter wrdev, iclass 29, count 2 2006.285.18:51:50.77#ibcon#first serial, iclass 29, count 2 2006.285.18:51:50.77#ibcon#enter sib2, iclass 29, count 2 2006.285.18:51:50.77#ibcon#flushed, iclass 29, count 2 2006.285.18:51:50.77#ibcon#about to write, iclass 29, count 2 2006.285.18:51:50.77#ibcon#wrote, iclass 29, count 2 2006.285.18:51:50.77#ibcon#about to read 3, iclass 29, count 2 2006.285.18:51:50.79#ibcon#read 3, iclass 29, count 2 2006.285.18:51:50.79#ibcon#about to read 4, iclass 29, count 2 2006.285.18:51:50.79#ibcon#read 4, iclass 29, count 2 2006.285.18:51:50.79#ibcon#about to read 5, iclass 29, count 2 2006.285.18:51:50.79#ibcon#read 5, iclass 29, count 2 2006.285.18:51:50.79#ibcon#about to read 6, iclass 29, count 2 2006.285.18:51:50.79#ibcon#read 6, iclass 29, count 2 2006.285.18:51:50.79#ibcon#end of sib2, iclass 29, count 2 2006.285.18:51:50.79#ibcon#*mode == 0, iclass 29, count 2 2006.285.18:51:50.79#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.18:51:50.79#ibcon#[25=AT01-07\r\n] 2006.285.18:51:50.79#ibcon#*before write, iclass 29, count 2 2006.285.18:51:50.79#ibcon#enter sib2, iclass 29, count 2 2006.285.18:51:50.79#ibcon#flushed, iclass 29, count 2 2006.285.18:51:50.79#ibcon#about to write, iclass 29, count 2 2006.285.18:51:50.79#ibcon#wrote, iclass 29, count 2 2006.285.18:51:50.79#ibcon#about to read 3, iclass 29, count 2 2006.285.18:51:50.82#ibcon#read 3, iclass 29, count 2 2006.285.18:51:50.82#ibcon#about to read 4, iclass 29, count 2 2006.285.18:51:50.82#ibcon#read 4, iclass 29, count 2 2006.285.18:51:50.82#ibcon#about to read 5, iclass 29, count 2 2006.285.18:51:50.82#ibcon#read 5, iclass 29, count 2 2006.285.18:51:50.82#ibcon#about to read 6, iclass 29, count 2 2006.285.18:51:50.82#ibcon#read 6, iclass 29, count 2 2006.285.18:51:50.82#ibcon#end of sib2, iclass 29, count 2 2006.285.18:51:50.82#ibcon#*after write, iclass 29, count 2 2006.285.18:51:50.82#ibcon#*before return 0, iclass 29, count 2 2006.285.18:51:50.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:51:50.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:51:50.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.18:51:50.82#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:50.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:51:50.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:51:50.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:51:50.94#ibcon#enter wrdev, iclass 29, count 0 2006.285.18:51:50.94#ibcon#first serial, iclass 29, count 0 2006.285.18:51:50.94#ibcon#enter sib2, iclass 29, count 0 2006.285.18:51:50.94#ibcon#flushed, iclass 29, count 0 2006.285.18:51:50.94#ibcon#about to write, iclass 29, count 0 2006.285.18:51:50.94#ibcon#wrote, iclass 29, count 0 2006.285.18:51:50.94#ibcon#about to read 3, iclass 29, count 0 2006.285.18:51:50.96#ibcon#read 3, iclass 29, count 0 2006.285.18:51:50.96#ibcon#about to read 4, iclass 29, count 0 2006.285.18:51:50.96#ibcon#read 4, iclass 29, count 0 2006.285.18:51:50.96#ibcon#about to read 5, iclass 29, count 0 2006.285.18:51:50.96#ibcon#read 5, iclass 29, count 0 2006.285.18:51:50.96#ibcon#about to read 6, iclass 29, count 0 2006.285.18:51:50.96#ibcon#read 6, iclass 29, count 0 2006.285.18:51:50.96#ibcon#end of sib2, iclass 29, count 0 2006.285.18:51:50.96#ibcon#*mode == 0, iclass 29, count 0 2006.285.18:51:50.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.18:51:50.96#ibcon#[25=USB\r\n] 2006.285.18:51:50.96#ibcon#*before write, iclass 29, count 0 2006.285.18:51:50.96#ibcon#enter sib2, iclass 29, count 0 2006.285.18:51:50.96#ibcon#flushed, iclass 29, count 0 2006.285.18:51:50.96#ibcon#about to write, iclass 29, count 0 2006.285.18:51:50.96#ibcon#wrote, iclass 29, count 0 2006.285.18:51:50.96#ibcon#about to read 3, iclass 29, count 0 2006.285.18:51:50.99#ibcon#read 3, iclass 29, count 0 2006.285.18:51:50.99#ibcon#about to read 4, iclass 29, count 0 2006.285.18:51:50.99#ibcon#read 4, iclass 29, count 0 2006.285.18:51:50.99#ibcon#about to read 5, iclass 29, count 0 2006.285.18:51:50.99#ibcon#read 5, iclass 29, count 0 2006.285.18:51:50.99#ibcon#about to read 6, iclass 29, count 0 2006.285.18:51:50.99#ibcon#read 6, iclass 29, count 0 2006.285.18:51:50.99#ibcon#end of sib2, iclass 29, count 0 2006.285.18:51:50.99#ibcon#*after write, iclass 29, count 0 2006.285.18:51:50.99#ibcon#*before return 0, iclass 29, count 0 2006.285.18:51:50.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:51:50.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:51:50.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.18:51:50.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.18:51:50.99$vck44/valo=2,534.99 2006.285.18:51:50.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.18:51:50.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.18:51:50.99#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:50.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:51:50.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:51:50.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:51:50.99#ibcon#enter wrdev, iclass 31, count 0 2006.285.18:51:50.99#ibcon#first serial, iclass 31, count 0 2006.285.18:51:50.99#ibcon#enter sib2, iclass 31, count 0 2006.285.18:51:50.99#ibcon#flushed, iclass 31, count 0 2006.285.18:51:50.99#ibcon#about to write, iclass 31, count 0 2006.285.18:51:50.99#ibcon#wrote, iclass 31, count 0 2006.285.18:51:50.99#ibcon#about to read 3, iclass 31, count 0 2006.285.18:51:51.01#ibcon#read 3, iclass 31, count 0 2006.285.18:51:51.01#ibcon#about to read 4, iclass 31, count 0 2006.285.18:51:51.01#ibcon#read 4, iclass 31, count 0 2006.285.18:51:51.01#ibcon#about to read 5, iclass 31, count 0 2006.285.18:51:51.01#ibcon#read 5, iclass 31, count 0 2006.285.18:51:51.01#ibcon#about to read 6, iclass 31, count 0 2006.285.18:51:51.01#ibcon#read 6, iclass 31, count 0 2006.285.18:51:51.01#ibcon#end of sib2, iclass 31, count 0 2006.285.18:51:51.01#ibcon#*mode == 0, iclass 31, count 0 2006.285.18:51:51.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.18:51:51.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.18:51:51.01#ibcon#*before write, iclass 31, count 0 2006.285.18:51:51.01#ibcon#enter sib2, iclass 31, count 0 2006.285.18:51:51.01#ibcon#flushed, iclass 31, count 0 2006.285.18:51:51.01#ibcon#about to write, iclass 31, count 0 2006.285.18:51:51.01#ibcon#wrote, iclass 31, count 0 2006.285.18:51:51.01#ibcon#about to read 3, iclass 31, count 0 2006.285.18:51:51.05#ibcon#read 3, iclass 31, count 0 2006.285.18:51:51.05#ibcon#about to read 4, iclass 31, count 0 2006.285.18:51:51.05#ibcon#read 4, iclass 31, count 0 2006.285.18:51:51.05#ibcon#about to read 5, iclass 31, count 0 2006.285.18:51:51.05#ibcon#read 5, iclass 31, count 0 2006.285.18:51:51.05#ibcon#about to read 6, iclass 31, count 0 2006.285.18:51:51.05#ibcon#read 6, iclass 31, count 0 2006.285.18:51:51.05#ibcon#end of sib2, iclass 31, count 0 2006.285.18:51:51.05#ibcon#*after write, iclass 31, count 0 2006.285.18:51:51.05#ibcon#*before return 0, iclass 31, count 0 2006.285.18:51:51.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:51:51.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:51:51.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.18:51:51.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.18:51:51.05$vck44/va=2,6 2006.285.18:51:51.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.18:51:51.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.18:51:51.05#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:51.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:51:51.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:51:51.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:51:51.11#ibcon#enter wrdev, iclass 33, count 2 2006.285.18:51:51.11#ibcon#first serial, iclass 33, count 2 2006.285.18:51:51.11#ibcon#enter sib2, iclass 33, count 2 2006.285.18:51:51.11#ibcon#flushed, iclass 33, count 2 2006.285.18:51:51.11#ibcon#about to write, iclass 33, count 2 2006.285.18:51:51.11#ibcon#wrote, iclass 33, count 2 2006.285.18:51:51.11#ibcon#about to read 3, iclass 33, count 2 2006.285.18:51:51.13#ibcon#read 3, iclass 33, count 2 2006.285.18:51:51.13#ibcon#about to read 4, iclass 33, count 2 2006.285.18:51:51.13#ibcon#read 4, iclass 33, count 2 2006.285.18:51:51.13#ibcon#about to read 5, iclass 33, count 2 2006.285.18:51:51.13#ibcon#read 5, iclass 33, count 2 2006.285.18:51:51.13#ibcon#about to read 6, iclass 33, count 2 2006.285.18:51:51.13#ibcon#read 6, iclass 33, count 2 2006.285.18:51:51.13#ibcon#end of sib2, iclass 33, count 2 2006.285.18:51:51.13#ibcon#*mode == 0, iclass 33, count 2 2006.285.18:51:51.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.18:51:51.13#ibcon#[25=AT02-06\r\n] 2006.285.18:51:51.13#ibcon#*before write, iclass 33, count 2 2006.285.18:51:51.13#ibcon#enter sib2, iclass 33, count 2 2006.285.18:51:51.13#ibcon#flushed, iclass 33, count 2 2006.285.18:51:51.13#ibcon#about to write, iclass 33, count 2 2006.285.18:51:51.13#ibcon#wrote, iclass 33, count 2 2006.285.18:51:51.13#ibcon#about to read 3, iclass 33, count 2 2006.285.18:51:51.16#ibcon#read 3, iclass 33, count 2 2006.285.18:51:51.16#ibcon#about to read 4, iclass 33, count 2 2006.285.18:51:51.16#ibcon#read 4, iclass 33, count 2 2006.285.18:51:51.16#ibcon#about to read 5, iclass 33, count 2 2006.285.18:51:51.16#ibcon#read 5, iclass 33, count 2 2006.285.18:51:51.16#ibcon#about to read 6, iclass 33, count 2 2006.285.18:51:51.16#ibcon#read 6, iclass 33, count 2 2006.285.18:51:51.16#ibcon#end of sib2, iclass 33, count 2 2006.285.18:51:51.16#ibcon#*after write, iclass 33, count 2 2006.285.18:51:51.16#ibcon#*before return 0, iclass 33, count 2 2006.285.18:51:51.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:51:51.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:51:51.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.18:51:51.16#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:51.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:51:51.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:51:51.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:51:51.28#ibcon#enter wrdev, iclass 33, count 0 2006.285.18:51:51.28#ibcon#first serial, iclass 33, count 0 2006.285.18:51:51.28#ibcon#enter sib2, iclass 33, count 0 2006.285.18:51:51.28#ibcon#flushed, iclass 33, count 0 2006.285.18:51:51.28#ibcon#about to write, iclass 33, count 0 2006.285.18:51:51.28#ibcon#wrote, iclass 33, count 0 2006.285.18:51:51.28#ibcon#about to read 3, iclass 33, count 0 2006.285.18:51:51.30#ibcon#read 3, iclass 33, count 0 2006.285.18:51:51.30#ibcon#about to read 4, iclass 33, count 0 2006.285.18:51:51.30#ibcon#read 4, iclass 33, count 0 2006.285.18:51:51.30#ibcon#about to read 5, iclass 33, count 0 2006.285.18:51:51.30#ibcon#read 5, iclass 33, count 0 2006.285.18:51:51.30#ibcon#about to read 6, iclass 33, count 0 2006.285.18:51:51.30#ibcon#read 6, iclass 33, count 0 2006.285.18:51:51.30#ibcon#end of sib2, iclass 33, count 0 2006.285.18:51:51.30#ibcon#*mode == 0, iclass 33, count 0 2006.285.18:51:51.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.18:51:51.30#ibcon#[25=USB\r\n] 2006.285.18:51:51.30#ibcon#*before write, iclass 33, count 0 2006.285.18:51:51.30#ibcon#enter sib2, iclass 33, count 0 2006.285.18:51:51.30#ibcon#flushed, iclass 33, count 0 2006.285.18:51:51.30#ibcon#about to write, iclass 33, count 0 2006.285.18:51:51.30#ibcon#wrote, iclass 33, count 0 2006.285.18:51:51.30#ibcon#about to read 3, iclass 33, count 0 2006.285.18:51:51.33#ibcon#read 3, iclass 33, count 0 2006.285.18:51:51.33#ibcon#about to read 4, iclass 33, count 0 2006.285.18:51:51.33#ibcon#read 4, iclass 33, count 0 2006.285.18:51:51.33#ibcon#about to read 5, iclass 33, count 0 2006.285.18:51:51.33#ibcon#read 5, iclass 33, count 0 2006.285.18:51:51.33#ibcon#about to read 6, iclass 33, count 0 2006.285.18:51:51.33#ibcon#read 6, iclass 33, count 0 2006.285.18:51:51.33#ibcon#end of sib2, iclass 33, count 0 2006.285.18:51:51.33#ibcon#*after write, iclass 33, count 0 2006.285.18:51:51.33#ibcon#*before return 0, iclass 33, count 0 2006.285.18:51:51.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:51:51.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:51:51.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.18:51:51.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.18:51:51.33$vck44/valo=3,564.99 2006.285.18:51:51.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.18:51:51.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.18:51:51.33#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:51.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:51:51.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:51:51.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:51:51.33#ibcon#enter wrdev, iclass 35, count 0 2006.285.18:51:51.33#ibcon#first serial, iclass 35, count 0 2006.285.18:51:51.33#ibcon#enter sib2, iclass 35, count 0 2006.285.18:51:51.33#ibcon#flushed, iclass 35, count 0 2006.285.18:51:51.33#ibcon#about to write, iclass 35, count 0 2006.285.18:51:51.33#ibcon#wrote, iclass 35, count 0 2006.285.18:51:51.33#ibcon#about to read 3, iclass 35, count 0 2006.285.18:51:51.35#ibcon#read 3, iclass 35, count 0 2006.285.18:51:51.35#ibcon#about to read 4, iclass 35, count 0 2006.285.18:51:51.35#ibcon#read 4, iclass 35, count 0 2006.285.18:51:51.35#ibcon#about to read 5, iclass 35, count 0 2006.285.18:51:51.35#ibcon#read 5, iclass 35, count 0 2006.285.18:51:51.35#ibcon#about to read 6, iclass 35, count 0 2006.285.18:51:51.35#ibcon#read 6, iclass 35, count 0 2006.285.18:51:51.35#ibcon#end of sib2, iclass 35, count 0 2006.285.18:51:51.35#ibcon#*mode == 0, iclass 35, count 0 2006.285.18:51:51.35#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.18:51:51.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.18:51:51.35#ibcon#*before write, iclass 35, count 0 2006.285.18:51:51.35#ibcon#enter sib2, iclass 35, count 0 2006.285.18:51:51.35#ibcon#flushed, iclass 35, count 0 2006.285.18:51:51.35#ibcon#about to write, iclass 35, count 0 2006.285.18:51:51.35#ibcon#wrote, iclass 35, count 0 2006.285.18:51:51.35#ibcon#about to read 3, iclass 35, count 0 2006.285.18:51:51.39#ibcon#read 3, iclass 35, count 0 2006.285.18:51:51.39#ibcon#about to read 4, iclass 35, count 0 2006.285.18:51:51.39#ibcon#read 4, iclass 35, count 0 2006.285.18:51:51.39#ibcon#about to read 5, iclass 35, count 0 2006.285.18:51:51.39#ibcon#read 5, iclass 35, count 0 2006.285.18:51:51.39#ibcon#about to read 6, iclass 35, count 0 2006.285.18:51:51.39#ibcon#read 6, iclass 35, count 0 2006.285.18:51:51.39#ibcon#end of sib2, iclass 35, count 0 2006.285.18:51:51.39#ibcon#*after write, iclass 35, count 0 2006.285.18:51:51.39#ibcon#*before return 0, iclass 35, count 0 2006.285.18:51:51.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:51:51.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:51:51.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.18:51:51.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.18:51:51.39$vck44/va=3,7 2006.285.18:51:51.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.18:51:51.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.18:51:51.39#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:51.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:51:51.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:51:51.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:51:51.45#ibcon#enter wrdev, iclass 37, count 2 2006.285.18:51:51.45#ibcon#first serial, iclass 37, count 2 2006.285.18:51:51.45#ibcon#enter sib2, iclass 37, count 2 2006.285.18:51:51.45#ibcon#flushed, iclass 37, count 2 2006.285.18:51:51.45#ibcon#about to write, iclass 37, count 2 2006.285.18:51:51.45#ibcon#wrote, iclass 37, count 2 2006.285.18:51:51.45#ibcon#about to read 3, iclass 37, count 2 2006.285.18:51:51.47#ibcon#read 3, iclass 37, count 2 2006.285.18:51:51.47#ibcon#about to read 4, iclass 37, count 2 2006.285.18:51:51.47#ibcon#read 4, iclass 37, count 2 2006.285.18:51:51.47#ibcon#about to read 5, iclass 37, count 2 2006.285.18:51:51.47#ibcon#read 5, iclass 37, count 2 2006.285.18:51:51.47#ibcon#about to read 6, iclass 37, count 2 2006.285.18:51:51.47#ibcon#read 6, iclass 37, count 2 2006.285.18:51:51.47#ibcon#end of sib2, iclass 37, count 2 2006.285.18:51:51.47#ibcon#*mode == 0, iclass 37, count 2 2006.285.18:51:51.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.18:51:51.47#ibcon#[25=AT03-07\r\n] 2006.285.18:51:51.47#ibcon#*before write, iclass 37, count 2 2006.285.18:51:51.47#ibcon#enter sib2, iclass 37, count 2 2006.285.18:51:51.47#ibcon#flushed, iclass 37, count 2 2006.285.18:51:51.47#ibcon#about to write, iclass 37, count 2 2006.285.18:51:51.47#ibcon#wrote, iclass 37, count 2 2006.285.18:51:51.47#ibcon#about to read 3, iclass 37, count 2 2006.285.18:51:51.50#ibcon#read 3, iclass 37, count 2 2006.285.18:51:51.50#ibcon#about to read 4, iclass 37, count 2 2006.285.18:51:51.50#ibcon#read 4, iclass 37, count 2 2006.285.18:51:51.50#ibcon#about to read 5, iclass 37, count 2 2006.285.18:51:51.50#ibcon#read 5, iclass 37, count 2 2006.285.18:51:51.50#ibcon#about to read 6, iclass 37, count 2 2006.285.18:51:51.50#ibcon#read 6, iclass 37, count 2 2006.285.18:51:51.50#ibcon#end of sib2, iclass 37, count 2 2006.285.18:51:51.50#ibcon#*after write, iclass 37, count 2 2006.285.18:51:51.50#ibcon#*before return 0, iclass 37, count 2 2006.285.18:51:51.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:51:51.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:51:51.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.18:51:51.50#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:51.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:51:51.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:51:51.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:51:51.62#ibcon#enter wrdev, iclass 37, count 0 2006.285.18:51:51.62#ibcon#first serial, iclass 37, count 0 2006.285.18:51:51.62#ibcon#enter sib2, iclass 37, count 0 2006.285.18:51:51.62#ibcon#flushed, iclass 37, count 0 2006.285.18:51:51.62#ibcon#about to write, iclass 37, count 0 2006.285.18:51:51.62#ibcon#wrote, iclass 37, count 0 2006.285.18:51:51.62#ibcon#about to read 3, iclass 37, count 0 2006.285.18:51:51.64#ibcon#read 3, iclass 37, count 0 2006.285.18:51:51.64#ibcon#about to read 4, iclass 37, count 0 2006.285.18:51:51.64#ibcon#read 4, iclass 37, count 0 2006.285.18:51:51.90#ibcon#about to read 5, iclass 37, count 0 2006.285.18:51:51.90#ibcon#read 5, iclass 37, count 0 2006.285.18:51:51.90#ibcon#about to read 6, iclass 37, count 0 2006.285.18:51:51.90#ibcon#read 6, iclass 37, count 0 2006.285.18:51:51.90#ibcon#end of sib2, iclass 37, count 0 2006.285.18:51:51.90#ibcon#*mode == 0, iclass 37, count 0 2006.285.18:51:51.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.18:51:51.90#ibcon#[25=USB\r\n] 2006.285.18:51:51.90#ibcon#*before write, iclass 37, count 0 2006.285.18:51:51.90#ibcon#enter sib2, iclass 37, count 0 2006.285.18:51:51.90#ibcon#flushed, iclass 37, count 0 2006.285.18:51:51.90#ibcon#about to write, iclass 37, count 0 2006.285.18:51:51.90#ibcon#wrote, iclass 37, count 0 2006.285.18:51:51.90#ibcon#about to read 3, iclass 37, count 0 2006.285.18:51:51.93#ibcon#read 3, iclass 37, count 0 2006.285.18:51:51.93#ibcon#about to read 4, iclass 37, count 0 2006.285.18:51:51.93#ibcon#read 4, iclass 37, count 0 2006.285.18:51:51.93#ibcon#about to read 5, iclass 37, count 0 2006.285.18:51:51.93#ibcon#read 5, iclass 37, count 0 2006.285.18:51:51.93#ibcon#about to read 6, iclass 37, count 0 2006.285.18:51:51.93#ibcon#read 6, iclass 37, count 0 2006.285.18:51:51.93#ibcon#end of sib2, iclass 37, count 0 2006.285.18:51:51.93#ibcon#*after write, iclass 37, count 0 2006.285.18:51:51.93#ibcon#*before return 0, iclass 37, count 0 2006.285.18:51:51.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:51:51.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:51:51.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.18:51:51.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.18:51:51.93$vck44/valo=4,624.99 2006.285.18:51:51.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.18:51:51.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.18:51:51.93#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:51.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:51:51.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:51:51.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:51:51.93#ibcon#enter wrdev, iclass 39, count 0 2006.285.18:51:51.93#ibcon#first serial, iclass 39, count 0 2006.285.18:51:51.93#ibcon#enter sib2, iclass 39, count 0 2006.285.18:51:51.93#ibcon#flushed, iclass 39, count 0 2006.285.18:51:51.93#ibcon#about to write, iclass 39, count 0 2006.285.18:51:51.93#ibcon#wrote, iclass 39, count 0 2006.285.18:51:51.93#ibcon#about to read 3, iclass 39, count 0 2006.285.18:51:51.95#ibcon#read 3, iclass 39, count 0 2006.285.18:51:51.95#ibcon#about to read 4, iclass 39, count 0 2006.285.18:51:51.95#ibcon#read 4, iclass 39, count 0 2006.285.18:51:51.95#ibcon#about to read 5, iclass 39, count 0 2006.285.18:51:51.95#ibcon#read 5, iclass 39, count 0 2006.285.18:51:51.95#ibcon#about to read 6, iclass 39, count 0 2006.285.18:51:51.95#ibcon#read 6, iclass 39, count 0 2006.285.18:51:51.95#ibcon#end of sib2, iclass 39, count 0 2006.285.18:51:51.95#ibcon#*mode == 0, iclass 39, count 0 2006.285.18:51:51.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.18:51:51.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.18:51:51.95#ibcon#*before write, iclass 39, count 0 2006.285.18:51:51.95#ibcon#enter sib2, iclass 39, count 0 2006.285.18:51:51.95#ibcon#flushed, iclass 39, count 0 2006.285.18:51:51.95#ibcon#about to write, iclass 39, count 0 2006.285.18:51:51.95#ibcon#wrote, iclass 39, count 0 2006.285.18:51:51.95#ibcon#about to read 3, iclass 39, count 0 2006.285.18:51:51.99#ibcon#read 3, iclass 39, count 0 2006.285.18:51:51.99#ibcon#about to read 4, iclass 39, count 0 2006.285.18:51:51.99#ibcon#read 4, iclass 39, count 0 2006.285.18:51:51.99#ibcon#about to read 5, iclass 39, count 0 2006.285.18:51:51.99#ibcon#read 5, iclass 39, count 0 2006.285.18:51:51.99#ibcon#about to read 6, iclass 39, count 0 2006.285.18:51:51.99#ibcon#read 6, iclass 39, count 0 2006.285.18:51:51.99#ibcon#end of sib2, iclass 39, count 0 2006.285.18:51:51.99#ibcon#*after write, iclass 39, count 0 2006.285.18:51:51.99#ibcon#*before return 0, iclass 39, count 0 2006.285.18:51:51.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:51:51.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:51:51.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.18:51:51.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.18:51:51.99$vck44/va=4,6 2006.285.18:51:51.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.18:51:51.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.18:51:51.99#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:51.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:51:52.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:51:52.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:51:52.05#ibcon#enter wrdev, iclass 3, count 2 2006.285.18:51:52.05#ibcon#first serial, iclass 3, count 2 2006.285.18:51:52.05#ibcon#enter sib2, iclass 3, count 2 2006.285.18:51:52.05#ibcon#flushed, iclass 3, count 2 2006.285.18:51:52.05#ibcon#about to write, iclass 3, count 2 2006.285.18:51:52.05#ibcon#wrote, iclass 3, count 2 2006.285.18:51:52.05#ibcon#about to read 3, iclass 3, count 2 2006.285.18:51:52.07#ibcon#read 3, iclass 3, count 2 2006.285.18:51:52.07#ibcon#about to read 4, iclass 3, count 2 2006.285.18:51:52.07#ibcon#read 4, iclass 3, count 2 2006.285.18:51:52.07#ibcon#about to read 5, iclass 3, count 2 2006.285.18:51:52.07#ibcon#read 5, iclass 3, count 2 2006.285.18:51:52.07#ibcon#about to read 6, iclass 3, count 2 2006.285.18:51:52.07#ibcon#read 6, iclass 3, count 2 2006.285.18:51:52.07#ibcon#end of sib2, iclass 3, count 2 2006.285.18:51:52.07#ibcon#*mode == 0, iclass 3, count 2 2006.285.18:51:52.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.18:51:52.07#ibcon#[25=AT04-06\r\n] 2006.285.18:51:52.07#ibcon#*before write, iclass 3, count 2 2006.285.18:51:52.07#ibcon#enter sib2, iclass 3, count 2 2006.285.18:51:52.07#ibcon#flushed, iclass 3, count 2 2006.285.18:51:52.07#ibcon#about to write, iclass 3, count 2 2006.285.18:51:52.07#ibcon#wrote, iclass 3, count 2 2006.285.18:51:52.07#ibcon#about to read 3, iclass 3, count 2 2006.285.18:51:52.10#ibcon#read 3, iclass 3, count 2 2006.285.18:51:52.10#ibcon#about to read 4, iclass 3, count 2 2006.285.18:51:52.10#ibcon#read 4, iclass 3, count 2 2006.285.18:51:52.10#ibcon#about to read 5, iclass 3, count 2 2006.285.18:51:52.10#ibcon#read 5, iclass 3, count 2 2006.285.18:51:52.10#ibcon#about to read 6, iclass 3, count 2 2006.285.18:51:52.10#ibcon#read 6, iclass 3, count 2 2006.285.18:51:52.10#ibcon#end of sib2, iclass 3, count 2 2006.285.18:51:52.10#ibcon#*after write, iclass 3, count 2 2006.285.18:51:52.10#ibcon#*before return 0, iclass 3, count 2 2006.285.18:51:52.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:51:52.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:51:52.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.18:51:52.10#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:52.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:51:52.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:51:52.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:51:52.22#ibcon#enter wrdev, iclass 3, count 0 2006.285.18:51:52.22#ibcon#first serial, iclass 3, count 0 2006.285.18:51:52.22#ibcon#enter sib2, iclass 3, count 0 2006.285.18:51:52.22#ibcon#flushed, iclass 3, count 0 2006.285.18:51:52.22#ibcon#about to write, iclass 3, count 0 2006.285.18:51:52.22#ibcon#wrote, iclass 3, count 0 2006.285.18:51:52.22#ibcon#about to read 3, iclass 3, count 0 2006.285.18:51:52.24#ibcon#read 3, iclass 3, count 0 2006.285.18:51:52.24#ibcon#about to read 4, iclass 3, count 0 2006.285.18:51:52.24#ibcon#read 4, iclass 3, count 0 2006.285.18:51:52.24#ibcon#about to read 5, iclass 3, count 0 2006.285.18:51:52.24#ibcon#read 5, iclass 3, count 0 2006.285.18:51:52.24#ibcon#about to read 6, iclass 3, count 0 2006.285.18:51:52.24#ibcon#read 6, iclass 3, count 0 2006.285.18:51:52.24#ibcon#end of sib2, iclass 3, count 0 2006.285.18:51:52.24#ibcon#*mode == 0, iclass 3, count 0 2006.285.18:51:52.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.18:51:52.24#ibcon#[25=USB\r\n] 2006.285.18:51:52.24#ibcon#*before write, iclass 3, count 0 2006.285.18:51:52.24#ibcon#enter sib2, iclass 3, count 0 2006.285.18:51:52.24#ibcon#flushed, iclass 3, count 0 2006.285.18:51:52.24#ibcon#about to write, iclass 3, count 0 2006.285.18:51:52.24#ibcon#wrote, iclass 3, count 0 2006.285.18:51:52.24#ibcon#about to read 3, iclass 3, count 0 2006.285.18:51:52.27#ibcon#read 3, iclass 3, count 0 2006.285.18:51:52.27#ibcon#about to read 4, iclass 3, count 0 2006.285.18:51:52.27#ibcon#read 4, iclass 3, count 0 2006.285.18:51:52.27#ibcon#about to read 5, iclass 3, count 0 2006.285.18:51:52.27#ibcon#read 5, iclass 3, count 0 2006.285.18:51:52.27#ibcon#about to read 6, iclass 3, count 0 2006.285.18:51:52.27#ibcon#read 6, iclass 3, count 0 2006.285.18:51:52.27#ibcon#end of sib2, iclass 3, count 0 2006.285.18:51:52.27#ibcon#*after write, iclass 3, count 0 2006.285.18:51:52.27#ibcon#*before return 0, iclass 3, count 0 2006.285.18:51:52.27#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:51:52.27#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:51:52.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.18:51:52.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.18:51:52.27$vck44/valo=5,734.99 2006.285.18:51:52.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.18:51:52.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.18:51:52.27#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:52.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:51:52.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:51:52.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:51:52.27#ibcon#enter wrdev, iclass 5, count 0 2006.285.18:51:52.27#ibcon#first serial, iclass 5, count 0 2006.285.18:51:52.27#ibcon#enter sib2, iclass 5, count 0 2006.285.18:51:52.27#ibcon#flushed, iclass 5, count 0 2006.285.18:51:52.52#ibcon#about to write, iclass 5, count 0 2006.285.18:51:52.52#ibcon#wrote, iclass 5, count 0 2006.285.18:51:52.52#ibcon#about to read 3, iclass 5, count 0 2006.285.18:51:52.54#ibcon#read 3, iclass 5, count 0 2006.285.18:51:52.54#ibcon#about to read 4, iclass 5, count 0 2006.285.18:51:52.54#ibcon#read 4, iclass 5, count 0 2006.285.18:51:52.54#ibcon#about to read 5, iclass 5, count 0 2006.285.18:51:52.54#ibcon#read 5, iclass 5, count 0 2006.285.18:51:52.54#ibcon#about to read 6, iclass 5, count 0 2006.285.18:51:52.54#ibcon#read 6, iclass 5, count 0 2006.285.18:51:52.54#ibcon#end of sib2, iclass 5, count 0 2006.285.18:51:52.54#ibcon#*mode == 0, iclass 5, count 0 2006.285.18:51:52.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.18:51:52.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.18:51:52.54#ibcon#*before write, iclass 5, count 0 2006.285.18:51:52.54#ibcon#enter sib2, iclass 5, count 0 2006.285.18:51:52.54#ibcon#flushed, iclass 5, count 0 2006.285.18:51:52.54#ibcon#about to write, iclass 5, count 0 2006.285.18:51:52.54#ibcon#wrote, iclass 5, count 0 2006.285.18:51:52.54#ibcon#about to read 3, iclass 5, count 0 2006.285.18:51:52.58#ibcon#read 3, iclass 5, count 0 2006.285.18:51:52.58#ibcon#about to read 4, iclass 5, count 0 2006.285.18:51:52.58#ibcon#read 4, iclass 5, count 0 2006.285.18:51:52.58#ibcon#about to read 5, iclass 5, count 0 2006.285.18:51:52.58#ibcon#read 5, iclass 5, count 0 2006.285.18:51:52.58#ibcon#about to read 6, iclass 5, count 0 2006.285.18:51:52.58#ibcon#read 6, iclass 5, count 0 2006.285.18:51:52.58#ibcon#end of sib2, iclass 5, count 0 2006.285.18:51:52.58#ibcon#*after write, iclass 5, count 0 2006.285.18:51:52.58#ibcon#*before return 0, iclass 5, count 0 2006.285.18:51:52.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:51:52.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:51:52.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.18:51:52.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.18:51:52.58$vck44/va=5,3 2006.285.18:51:52.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.18:51:52.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.18:51:52.58#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:52.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:51:52.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:51:52.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:51:52.58#ibcon#enter wrdev, iclass 7, count 2 2006.285.18:51:52.58#ibcon#first serial, iclass 7, count 2 2006.285.18:51:52.58#ibcon#enter sib2, iclass 7, count 2 2006.285.18:51:52.58#ibcon#flushed, iclass 7, count 2 2006.285.18:51:52.58#ibcon#about to write, iclass 7, count 2 2006.285.18:51:52.58#ibcon#wrote, iclass 7, count 2 2006.285.18:51:52.58#ibcon#about to read 3, iclass 7, count 2 2006.285.18:51:52.60#ibcon#read 3, iclass 7, count 2 2006.285.18:51:52.60#ibcon#about to read 4, iclass 7, count 2 2006.285.18:51:52.60#ibcon#read 4, iclass 7, count 2 2006.285.18:51:52.60#ibcon#about to read 5, iclass 7, count 2 2006.285.18:51:52.60#ibcon#read 5, iclass 7, count 2 2006.285.18:51:52.60#ibcon#about to read 6, iclass 7, count 2 2006.285.18:51:52.60#ibcon#read 6, iclass 7, count 2 2006.285.18:51:52.60#ibcon#end of sib2, iclass 7, count 2 2006.285.18:51:52.60#ibcon#*mode == 0, iclass 7, count 2 2006.285.18:51:52.60#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.18:51:52.60#ibcon#[25=AT05-03\r\n] 2006.285.18:51:52.60#ibcon#*before write, iclass 7, count 2 2006.285.18:51:52.60#ibcon#enter sib2, iclass 7, count 2 2006.285.18:51:52.60#ibcon#flushed, iclass 7, count 2 2006.285.18:51:52.60#ibcon#about to write, iclass 7, count 2 2006.285.18:51:52.60#ibcon#wrote, iclass 7, count 2 2006.285.18:51:52.60#ibcon#about to read 3, iclass 7, count 2 2006.285.18:51:52.63#ibcon#read 3, iclass 7, count 2 2006.285.18:51:52.63#ibcon#about to read 4, iclass 7, count 2 2006.285.18:51:52.63#ibcon#read 4, iclass 7, count 2 2006.285.18:51:52.63#ibcon#about to read 5, iclass 7, count 2 2006.285.18:51:52.63#ibcon#read 5, iclass 7, count 2 2006.285.18:51:52.63#ibcon#about to read 6, iclass 7, count 2 2006.285.18:51:52.63#ibcon#read 6, iclass 7, count 2 2006.285.18:51:52.63#ibcon#end of sib2, iclass 7, count 2 2006.285.18:51:52.63#ibcon#*after write, iclass 7, count 2 2006.285.18:51:52.63#ibcon#*before return 0, iclass 7, count 2 2006.285.18:51:52.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:51:52.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:51:52.63#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.18:51:52.63#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:52.63#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:51:52.75#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:51:52.75#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:51:52.75#ibcon#enter wrdev, iclass 7, count 0 2006.285.18:51:52.75#ibcon#first serial, iclass 7, count 0 2006.285.18:51:52.75#ibcon#enter sib2, iclass 7, count 0 2006.285.18:51:52.75#ibcon#flushed, iclass 7, count 0 2006.285.18:51:52.75#ibcon#about to write, iclass 7, count 0 2006.285.18:51:52.75#ibcon#wrote, iclass 7, count 0 2006.285.18:51:52.75#ibcon#about to read 3, iclass 7, count 0 2006.285.18:51:52.77#ibcon#read 3, iclass 7, count 0 2006.285.18:51:52.77#ibcon#about to read 4, iclass 7, count 0 2006.285.18:51:52.77#ibcon#read 4, iclass 7, count 0 2006.285.18:51:52.77#ibcon#about to read 5, iclass 7, count 0 2006.285.18:51:52.77#ibcon#read 5, iclass 7, count 0 2006.285.18:51:52.77#ibcon#about to read 6, iclass 7, count 0 2006.285.18:51:52.77#ibcon#read 6, iclass 7, count 0 2006.285.18:51:52.77#ibcon#end of sib2, iclass 7, count 0 2006.285.18:51:52.77#ibcon#*mode == 0, iclass 7, count 0 2006.285.18:51:52.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.18:51:52.77#ibcon#[25=USB\r\n] 2006.285.18:51:52.77#ibcon#*before write, iclass 7, count 0 2006.285.18:51:52.77#ibcon#enter sib2, iclass 7, count 0 2006.285.18:51:52.77#ibcon#flushed, iclass 7, count 0 2006.285.18:51:52.77#ibcon#about to write, iclass 7, count 0 2006.285.18:51:52.77#ibcon#wrote, iclass 7, count 0 2006.285.18:51:52.77#ibcon#about to read 3, iclass 7, count 0 2006.285.18:51:52.80#ibcon#read 3, iclass 7, count 0 2006.285.18:51:52.80#ibcon#about to read 4, iclass 7, count 0 2006.285.18:51:52.80#ibcon#read 4, iclass 7, count 0 2006.285.18:51:52.80#ibcon#about to read 5, iclass 7, count 0 2006.285.18:51:52.80#ibcon#read 5, iclass 7, count 0 2006.285.18:51:52.80#ibcon#about to read 6, iclass 7, count 0 2006.285.18:51:52.80#ibcon#read 6, iclass 7, count 0 2006.285.18:51:52.80#ibcon#end of sib2, iclass 7, count 0 2006.285.18:51:52.80#ibcon#*after write, iclass 7, count 0 2006.285.18:51:52.80#ibcon#*before return 0, iclass 7, count 0 2006.285.18:51:52.80#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:51:52.80#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:51:52.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.18:51:52.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.18:51:52.80$vck44/valo=6,814.99 2006.285.18:51:52.80#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.18:51:52.80#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.18:51:52.80#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:52.80#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:51:52.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:51:52.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:51:52.80#ibcon#enter wrdev, iclass 11, count 0 2006.285.18:51:52.80#ibcon#first serial, iclass 11, count 0 2006.285.18:51:52.80#ibcon#enter sib2, iclass 11, count 0 2006.285.18:51:52.80#ibcon#flushed, iclass 11, count 0 2006.285.18:51:52.80#ibcon#about to write, iclass 11, count 0 2006.285.18:51:52.80#ibcon#wrote, iclass 11, count 0 2006.285.18:51:52.80#ibcon#about to read 3, iclass 11, count 0 2006.285.18:51:52.82#ibcon#read 3, iclass 11, count 0 2006.285.18:51:52.82#ibcon#about to read 4, iclass 11, count 0 2006.285.18:51:52.82#ibcon#read 4, iclass 11, count 0 2006.285.18:51:52.82#ibcon#about to read 5, iclass 11, count 0 2006.285.18:51:52.82#ibcon#read 5, iclass 11, count 0 2006.285.18:51:52.82#ibcon#about to read 6, iclass 11, count 0 2006.285.18:51:52.82#ibcon#read 6, iclass 11, count 0 2006.285.18:51:52.82#ibcon#end of sib2, iclass 11, count 0 2006.285.18:51:52.82#ibcon#*mode == 0, iclass 11, count 0 2006.285.18:51:52.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.18:51:52.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.18:51:52.82#ibcon#*before write, iclass 11, count 0 2006.285.18:51:52.82#ibcon#enter sib2, iclass 11, count 0 2006.285.18:51:52.82#ibcon#flushed, iclass 11, count 0 2006.285.18:51:52.82#ibcon#about to write, iclass 11, count 0 2006.285.18:51:52.82#ibcon#wrote, iclass 11, count 0 2006.285.18:51:52.82#ibcon#about to read 3, iclass 11, count 0 2006.285.18:51:52.86#ibcon#read 3, iclass 11, count 0 2006.285.18:51:52.86#ibcon#about to read 4, iclass 11, count 0 2006.285.18:51:52.86#ibcon#read 4, iclass 11, count 0 2006.285.18:51:52.86#ibcon#about to read 5, iclass 11, count 0 2006.285.18:51:52.86#ibcon#read 5, iclass 11, count 0 2006.285.18:51:52.86#ibcon#about to read 6, iclass 11, count 0 2006.285.18:51:52.86#ibcon#read 6, iclass 11, count 0 2006.285.18:51:52.86#ibcon#end of sib2, iclass 11, count 0 2006.285.18:51:52.86#ibcon#*after write, iclass 11, count 0 2006.285.18:51:52.86#ibcon#*before return 0, iclass 11, count 0 2006.285.18:51:52.86#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:51:52.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:51:52.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.18:51:52.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.18:51:52.86$vck44/va=6,4 2006.285.18:51:52.86#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.18:51:52.86#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.18:51:52.86#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:52.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:51:52.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:51:52.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:51:52.92#ibcon#enter wrdev, iclass 13, count 2 2006.285.18:51:52.92#ibcon#first serial, iclass 13, count 2 2006.285.18:51:52.92#ibcon#enter sib2, iclass 13, count 2 2006.285.18:51:52.92#ibcon#flushed, iclass 13, count 2 2006.285.18:51:52.92#ibcon#about to write, iclass 13, count 2 2006.285.18:51:52.92#ibcon#wrote, iclass 13, count 2 2006.285.18:51:52.92#ibcon#about to read 3, iclass 13, count 2 2006.285.18:51:52.94#ibcon#read 3, iclass 13, count 2 2006.285.18:51:52.94#ibcon#about to read 4, iclass 13, count 2 2006.285.18:51:52.94#ibcon#read 4, iclass 13, count 2 2006.285.18:51:52.94#ibcon#about to read 5, iclass 13, count 2 2006.285.18:51:52.94#ibcon#read 5, iclass 13, count 2 2006.285.18:51:52.94#ibcon#about to read 6, iclass 13, count 2 2006.285.18:51:52.94#ibcon#read 6, iclass 13, count 2 2006.285.18:51:52.94#ibcon#end of sib2, iclass 13, count 2 2006.285.18:51:52.94#ibcon#*mode == 0, iclass 13, count 2 2006.285.18:51:52.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.18:51:52.94#ibcon#[25=AT06-04\r\n] 2006.285.18:51:52.94#ibcon#*before write, iclass 13, count 2 2006.285.18:51:52.94#ibcon#enter sib2, iclass 13, count 2 2006.285.18:51:52.94#ibcon#flushed, iclass 13, count 2 2006.285.18:51:52.94#ibcon#about to write, iclass 13, count 2 2006.285.18:51:52.94#ibcon#wrote, iclass 13, count 2 2006.285.18:51:52.94#ibcon#about to read 3, iclass 13, count 2 2006.285.18:51:52.97#ibcon#read 3, iclass 13, count 2 2006.285.18:51:52.97#ibcon#about to read 4, iclass 13, count 2 2006.285.18:51:52.97#ibcon#read 4, iclass 13, count 2 2006.285.18:51:52.97#ibcon#about to read 5, iclass 13, count 2 2006.285.18:51:52.97#ibcon#read 5, iclass 13, count 2 2006.285.18:51:52.97#ibcon#about to read 6, iclass 13, count 2 2006.285.18:51:52.97#ibcon#read 6, iclass 13, count 2 2006.285.18:51:52.97#ibcon#end of sib2, iclass 13, count 2 2006.285.18:51:52.97#ibcon#*after write, iclass 13, count 2 2006.285.18:51:52.97#ibcon#*before return 0, iclass 13, count 2 2006.285.18:51:52.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:51:52.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:51:52.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.18:51:52.97#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:52.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:51:53.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:51:53.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:51:53.09#ibcon#enter wrdev, iclass 13, count 0 2006.285.18:51:53.09#ibcon#first serial, iclass 13, count 0 2006.285.18:51:53.09#ibcon#enter sib2, iclass 13, count 0 2006.285.18:51:53.09#ibcon#flushed, iclass 13, count 0 2006.285.18:51:53.09#ibcon#about to write, iclass 13, count 0 2006.285.18:51:53.09#ibcon#wrote, iclass 13, count 0 2006.285.18:51:53.09#ibcon#about to read 3, iclass 13, count 0 2006.285.18:51:53.11#ibcon#read 3, iclass 13, count 0 2006.285.18:51:53.11#ibcon#about to read 4, iclass 13, count 0 2006.285.18:51:53.11#ibcon#read 4, iclass 13, count 0 2006.285.18:51:53.11#ibcon#about to read 5, iclass 13, count 0 2006.285.18:51:53.11#ibcon#read 5, iclass 13, count 0 2006.285.18:51:53.11#ibcon#about to read 6, iclass 13, count 0 2006.285.18:51:53.11#ibcon#read 6, iclass 13, count 0 2006.285.18:51:53.11#ibcon#end of sib2, iclass 13, count 0 2006.285.18:51:53.11#ibcon#*mode == 0, iclass 13, count 0 2006.285.18:51:53.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.18:51:53.11#ibcon#[25=USB\r\n] 2006.285.18:51:53.11#ibcon#*before write, iclass 13, count 0 2006.285.18:51:53.11#ibcon#enter sib2, iclass 13, count 0 2006.285.18:51:53.11#ibcon#flushed, iclass 13, count 0 2006.285.18:51:53.11#ibcon#about to write, iclass 13, count 0 2006.285.18:51:53.11#ibcon#wrote, iclass 13, count 0 2006.285.18:51:53.11#ibcon#about to read 3, iclass 13, count 0 2006.285.18:51:53.14#ibcon#read 3, iclass 13, count 0 2006.285.18:51:53.14#ibcon#about to read 4, iclass 13, count 0 2006.285.18:51:53.14#ibcon#read 4, iclass 13, count 0 2006.285.18:51:53.14#ibcon#about to read 5, iclass 13, count 0 2006.285.18:51:53.14#ibcon#read 5, iclass 13, count 0 2006.285.18:51:53.14#ibcon#about to read 6, iclass 13, count 0 2006.285.18:51:53.14#ibcon#read 6, iclass 13, count 0 2006.285.18:51:53.14#ibcon#end of sib2, iclass 13, count 0 2006.285.18:51:53.14#ibcon#*after write, iclass 13, count 0 2006.285.18:51:53.14#ibcon#*before return 0, iclass 13, count 0 2006.285.18:51:53.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:51:53.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:51:53.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.18:51:53.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.18:51:53.14$vck44/valo=7,864.99 2006.285.18:51:53.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.18:51:53.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.18:51:53.14#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:53.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:51:53.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:51:53.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:51:53.14#ibcon#enter wrdev, iclass 15, count 0 2006.285.18:51:53.14#ibcon#first serial, iclass 15, count 0 2006.285.18:51:53.14#ibcon#enter sib2, iclass 15, count 0 2006.285.18:51:53.14#ibcon#flushed, iclass 15, count 0 2006.285.18:51:53.14#ibcon#about to write, iclass 15, count 0 2006.285.18:51:53.14#ibcon#wrote, iclass 15, count 0 2006.285.18:51:53.14#ibcon#about to read 3, iclass 15, count 0 2006.285.18:51:53.16#ibcon#read 3, iclass 15, count 0 2006.285.18:51:53.16#ibcon#about to read 4, iclass 15, count 0 2006.285.18:51:53.16#ibcon#read 4, iclass 15, count 0 2006.285.18:51:53.16#ibcon#about to read 5, iclass 15, count 0 2006.285.18:51:53.16#ibcon#read 5, iclass 15, count 0 2006.285.18:51:53.16#ibcon#about to read 6, iclass 15, count 0 2006.285.18:51:53.16#ibcon#read 6, iclass 15, count 0 2006.285.18:51:53.16#ibcon#end of sib2, iclass 15, count 0 2006.285.18:51:53.16#ibcon#*mode == 0, iclass 15, count 0 2006.285.18:51:53.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.18:51:53.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.18:51:53.16#ibcon#*before write, iclass 15, count 0 2006.285.18:51:53.16#ibcon#enter sib2, iclass 15, count 0 2006.285.18:51:53.16#ibcon#flushed, iclass 15, count 0 2006.285.18:51:53.16#ibcon#about to write, iclass 15, count 0 2006.285.18:51:53.16#ibcon#wrote, iclass 15, count 0 2006.285.18:51:53.16#ibcon#about to read 3, iclass 15, count 0 2006.285.18:51:53.20#ibcon#read 3, iclass 15, count 0 2006.285.18:51:53.20#ibcon#about to read 4, iclass 15, count 0 2006.285.18:51:53.20#ibcon#read 4, iclass 15, count 0 2006.285.18:51:53.20#ibcon#about to read 5, iclass 15, count 0 2006.285.18:51:53.20#ibcon#read 5, iclass 15, count 0 2006.285.18:51:53.20#ibcon#about to read 6, iclass 15, count 0 2006.285.18:51:53.20#ibcon#read 6, iclass 15, count 0 2006.285.18:51:53.20#ibcon#end of sib2, iclass 15, count 0 2006.285.18:51:53.20#ibcon#*after write, iclass 15, count 0 2006.285.18:51:53.20#ibcon#*before return 0, iclass 15, count 0 2006.285.18:51:53.20#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:51:53.20#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:51:53.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.18:51:53.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.18:51:53.20$vck44/va=7,4 2006.285.18:51:53.20#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.18:51:53.20#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.18:51:53.20#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:53.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:51:53.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:51:53.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:51:53.26#ibcon#enter wrdev, iclass 17, count 2 2006.285.18:51:53.26#ibcon#first serial, iclass 17, count 2 2006.285.18:51:53.26#ibcon#enter sib2, iclass 17, count 2 2006.285.18:51:53.26#ibcon#flushed, iclass 17, count 2 2006.285.18:51:53.26#ibcon#about to write, iclass 17, count 2 2006.285.18:51:53.26#ibcon#wrote, iclass 17, count 2 2006.285.18:51:53.26#ibcon#about to read 3, iclass 17, count 2 2006.285.18:51:53.28#ibcon#read 3, iclass 17, count 2 2006.285.18:51:53.28#ibcon#about to read 4, iclass 17, count 2 2006.285.18:51:53.28#ibcon#read 4, iclass 17, count 2 2006.285.18:51:53.28#ibcon#about to read 5, iclass 17, count 2 2006.285.18:51:53.28#ibcon#read 5, iclass 17, count 2 2006.285.18:51:53.28#ibcon#about to read 6, iclass 17, count 2 2006.285.18:51:53.28#ibcon#read 6, iclass 17, count 2 2006.285.18:51:53.28#ibcon#end of sib2, iclass 17, count 2 2006.285.18:51:53.28#ibcon#*mode == 0, iclass 17, count 2 2006.285.18:51:53.28#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.18:51:53.28#ibcon#[25=AT07-04\r\n] 2006.285.18:51:53.28#ibcon#*before write, iclass 17, count 2 2006.285.18:51:53.28#ibcon#enter sib2, iclass 17, count 2 2006.285.18:51:53.28#ibcon#flushed, iclass 17, count 2 2006.285.18:51:53.28#ibcon#about to write, iclass 17, count 2 2006.285.18:51:53.28#ibcon#wrote, iclass 17, count 2 2006.285.18:51:53.28#ibcon#about to read 3, iclass 17, count 2 2006.285.18:51:53.31#ibcon#read 3, iclass 17, count 2 2006.285.18:51:53.31#ibcon#about to read 4, iclass 17, count 2 2006.285.18:51:53.31#ibcon#read 4, iclass 17, count 2 2006.285.18:51:53.31#ibcon#about to read 5, iclass 17, count 2 2006.285.18:51:53.31#ibcon#read 5, iclass 17, count 2 2006.285.18:51:53.31#ibcon#about to read 6, iclass 17, count 2 2006.285.18:51:53.31#ibcon#read 6, iclass 17, count 2 2006.285.18:51:53.31#ibcon#end of sib2, iclass 17, count 2 2006.285.18:51:53.31#ibcon#*after write, iclass 17, count 2 2006.285.18:51:53.31#ibcon#*before return 0, iclass 17, count 2 2006.285.18:51:53.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:51:53.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:51:53.31#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.18:51:53.31#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:53.31#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:51:53.43#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:51:53.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:51:53.43#ibcon#enter wrdev, iclass 17, count 0 2006.285.18:51:53.43#ibcon#first serial, iclass 17, count 0 2006.285.18:51:53.43#ibcon#enter sib2, iclass 17, count 0 2006.285.18:51:53.43#ibcon#flushed, iclass 17, count 0 2006.285.18:51:53.43#ibcon#about to write, iclass 17, count 0 2006.285.18:51:53.43#ibcon#wrote, iclass 17, count 0 2006.285.18:51:53.43#ibcon#about to read 3, iclass 17, count 0 2006.285.18:51:53.45#ibcon#read 3, iclass 17, count 0 2006.285.18:51:53.45#ibcon#about to read 4, iclass 17, count 0 2006.285.18:51:53.45#ibcon#read 4, iclass 17, count 0 2006.285.18:51:53.45#ibcon#about to read 5, iclass 17, count 0 2006.285.18:51:53.45#ibcon#read 5, iclass 17, count 0 2006.285.18:51:53.45#ibcon#about to read 6, iclass 17, count 0 2006.285.18:51:53.45#ibcon#read 6, iclass 17, count 0 2006.285.18:51:53.45#ibcon#end of sib2, iclass 17, count 0 2006.285.18:51:53.45#ibcon#*mode == 0, iclass 17, count 0 2006.285.18:51:53.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.18:51:53.45#ibcon#[25=USB\r\n] 2006.285.18:51:53.45#ibcon#*before write, iclass 17, count 0 2006.285.18:51:53.45#ibcon#enter sib2, iclass 17, count 0 2006.285.18:51:53.45#ibcon#flushed, iclass 17, count 0 2006.285.18:51:53.45#ibcon#about to write, iclass 17, count 0 2006.285.18:51:53.45#ibcon#wrote, iclass 17, count 0 2006.285.18:51:53.45#ibcon#about to read 3, iclass 17, count 0 2006.285.18:51:53.48#ibcon#read 3, iclass 17, count 0 2006.285.18:51:53.48#ibcon#about to read 4, iclass 17, count 0 2006.285.18:51:53.48#ibcon#read 4, iclass 17, count 0 2006.285.18:51:53.48#ibcon#about to read 5, iclass 17, count 0 2006.285.18:51:53.48#ibcon#read 5, iclass 17, count 0 2006.285.18:51:53.48#ibcon#about to read 6, iclass 17, count 0 2006.285.18:51:53.48#ibcon#read 6, iclass 17, count 0 2006.285.18:51:53.48#ibcon#end of sib2, iclass 17, count 0 2006.285.18:51:53.48#ibcon#*after write, iclass 17, count 0 2006.285.18:51:53.48#ibcon#*before return 0, iclass 17, count 0 2006.285.18:51:53.48#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:51:53.48#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:51:53.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.18:51:53.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.18:51:53.48$vck44/valo=8,884.99 2006.285.18:51:53.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.18:51:53.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.18:51:53.48#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:53.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:51:53.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:51:53.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:51:53.48#ibcon#enter wrdev, iclass 19, count 0 2006.285.18:51:53.48#ibcon#first serial, iclass 19, count 0 2006.285.18:51:53.48#ibcon#enter sib2, iclass 19, count 0 2006.285.18:51:53.48#ibcon#flushed, iclass 19, count 0 2006.285.18:51:53.48#ibcon#about to write, iclass 19, count 0 2006.285.18:51:53.48#ibcon#wrote, iclass 19, count 0 2006.285.18:51:53.48#ibcon#about to read 3, iclass 19, count 0 2006.285.18:51:53.50#ibcon#read 3, iclass 19, count 0 2006.285.18:51:53.50#ibcon#about to read 4, iclass 19, count 0 2006.285.18:51:53.50#ibcon#read 4, iclass 19, count 0 2006.285.18:51:53.50#ibcon#about to read 5, iclass 19, count 0 2006.285.18:51:53.50#ibcon#read 5, iclass 19, count 0 2006.285.18:51:53.50#ibcon#about to read 6, iclass 19, count 0 2006.285.18:51:53.50#ibcon#read 6, iclass 19, count 0 2006.285.18:51:53.50#ibcon#end of sib2, iclass 19, count 0 2006.285.18:51:53.50#ibcon#*mode == 0, iclass 19, count 0 2006.285.18:51:53.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.18:51:53.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.18:51:53.50#ibcon#*before write, iclass 19, count 0 2006.285.18:51:53.50#ibcon#enter sib2, iclass 19, count 0 2006.285.18:51:53.50#ibcon#flushed, iclass 19, count 0 2006.285.18:51:53.50#ibcon#about to write, iclass 19, count 0 2006.285.18:51:53.50#ibcon#wrote, iclass 19, count 0 2006.285.18:51:53.50#ibcon#about to read 3, iclass 19, count 0 2006.285.18:51:53.54#ibcon#read 3, iclass 19, count 0 2006.285.18:51:53.54#ibcon#about to read 4, iclass 19, count 0 2006.285.18:51:53.54#ibcon#read 4, iclass 19, count 0 2006.285.18:51:53.54#ibcon#about to read 5, iclass 19, count 0 2006.285.18:51:53.54#ibcon#read 5, iclass 19, count 0 2006.285.18:51:53.54#ibcon#about to read 6, iclass 19, count 0 2006.285.18:51:53.54#ibcon#read 6, iclass 19, count 0 2006.285.18:51:53.54#ibcon#end of sib2, iclass 19, count 0 2006.285.18:51:53.54#ibcon#*after write, iclass 19, count 0 2006.285.18:51:53.54#ibcon#*before return 0, iclass 19, count 0 2006.285.18:51:53.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:51:53.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:51:53.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.18:51:53.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.18:51:53.54$vck44/va=8,3 2006.285.18:51:53.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.18:51:53.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.18:51:53.54#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:53.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:51:53.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:51:53.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:51:53.60#ibcon#enter wrdev, iclass 21, count 2 2006.285.18:51:53.60#ibcon#first serial, iclass 21, count 2 2006.285.18:51:53.60#ibcon#enter sib2, iclass 21, count 2 2006.285.18:51:53.60#ibcon#flushed, iclass 21, count 2 2006.285.18:51:53.60#ibcon#about to write, iclass 21, count 2 2006.285.18:51:53.60#ibcon#wrote, iclass 21, count 2 2006.285.18:51:53.60#ibcon#about to read 3, iclass 21, count 2 2006.285.18:51:53.62#ibcon#read 3, iclass 21, count 2 2006.285.18:51:53.62#ibcon#about to read 4, iclass 21, count 2 2006.285.18:51:53.62#ibcon#read 4, iclass 21, count 2 2006.285.18:51:53.62#ibcon#about to read 5, iclass 21, count 2 2006.285.18:51:53.62#ibcon#read 5, iclass 21, count 2 2006.285.18:51:53.62#ibcon#about to read 6, iclass 21, count 2 2006.285.18:51:53.62#ibcon#read 6, iclass 21, count 2 2006.285.18:51:53.62#ibcon#end of sib2, iclass 21, count 2 2006.285.18:51:53.62#ibcon#*mode == 0, iclass 21, count 2 2006.285.18:51:53.62#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.18:51:53.62#ibcon#[25=AT08-03\r\n] 2006.285.18:51:53.62#ibcon#*before write, iclass 21, count 2 2006.285.18:51:53.62#ibcon#enter sib2, iclass 21, count 2 2006.285.18:51:53.62#ibcon#flushed, iclass 21, count 2 2006.285.18:51:53.62#ibcon#about to write, iclass 21, count 2 2006.285.18:51:53.62#ibcon#wrote, iclass 21, count 2 2006.285.18:51:53.62#ibcon#about to read 3, iclass 21, count 2 2006.285.18:51:53.65#ibcon#read 3, iclass 21, count 2 2006.285.18:51:53.80#ibcon#about to read 4, iclass 21, count 2 2006.285.18:51:53.80#ibcon#read 4, iclass 21, count 2 2006.285.18:51:53.80#ibcon#about to read 5, iclass 21, count 2 2006.285.18:51:53.80#ibcon#read 5, iclass 21, count 2 2006.285.18:51:53.80#ibcon#about to read 6, iclass 21, count 2 2006.285.18:51:53.80#ibcon#read 6, iclass 21, count 2 2006.285.18:51:53.80#ibcon#end of sib2, iclass 21, count 2 2006.285.18:51:53.80#ibcon#*after write, iclass 21, count 2 2006.285.18:51:53.80#ibcon#*before return 0, iclass 21, count 2 2006.285.18:51:53.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:51:53.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.18:51:53.80#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.18:51:53.80#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:53.80#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:51:53.92#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:51:53.92#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:51:53.92#ibcon#enter wrdev, iclass 21, count 0 2006.285.18:51:53.92#ibcon#first serial, iclass 21, count 0 2006.285.18:51:53.92#ibcon#enter sib2, iclass 21, count 0 2006.285.18:51:53.92#ibcon#flushed, iclass 21, count 0 2006.285.18:51:53.92#ibcon#about to write, iclass 21, count 0 2006.285.18:51:53.92#ibcon#wrote, iclass 21, count 0 2006.285.18:51:53.92#ibcon#about to read 3, iclass 21, count 0 2006.285.18:51:53.94#ibcon#read 3, iclass 21, count 0 2006.285.18:51:53.94#ibcon#about to read 4, iclass 21, count 0 2006.285.18:51:53.94#ibcon#read 4, iclass 21, count 0 2006.285.18:51:53.94#ibcon#about to read 5, iclass 21, count 0 2006.285.18:51:53.94#ibcon#read 5, iclass 21, count 0 2006.285.18:51:53.94#ibcon#about to read 6, iclass 21, count 0 2006.285.18:51:53.94#ibcon#read 6, iclass 21, count 0 2006.285.18:51:53.94#ibcon#end of sib2, iclass 21, count 0 2006.285.18:51:53.94#ibcon#*mode == 0, iclass 21, count 0 2006.285.18:51:53.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.18:51:53.94#ibcon#[25=USB\r\n] 2006.285.18:51:53.94#ibcon#*before write, iclass 21, count 0 2006.285.18:51:53.94#ibcon#enter sib2, iclass 21, count 0 2006.285.18:51:53.94#ibcon#flushed, iclass 21, count 0 2006.285.18:51:53.94#ibcon#about to write, iclass 21, count 0 2006.285.18:51:53.94#ibcon#wrote, iclass 21, count 0 2006.285.18:51:53.94#ibcon#about to read 3, iclass 21, count 0 2006.285.18:51:53.97#ibcon#read 3, iclass 21, count 0 2006.285.18:51:53.97#ibcon#about to read 4, iclass 21, count 0 2006.285.18:51:53.97#ibcon#read 4, iclass 21, count 0 2006.285.18:51:53.97#ibcon#about to read 5, iclass 21, count 0 2006.285.18:51:53.97#ibcon#read 5, iclass 21, count 0 2006.285.18:51:53.97#ibcon#about to read 6, iclass 21, count 0 2006.285.18:51:53.97#ibcon#read 6, iclass 21, count 0 2006.285.18:51:53.97#ibcon#end of sib2, iclass 21, count 0 2006.285.18:51:53.97#ibcon#*after write, iclass 21, count 0 2006.285.18:51:53.97#ibcon#*before return 0, iclass 21, count 0 2006.285.18:51:53.97#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:51:53.97#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.18:51:53.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.18:51:53.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.18:51:53.97$vck44/vblo=1,629.99 2006.285.18:51:53.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.18:51:53.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.18:51:53.97#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:53.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:51:53.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:51:53.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:51:53.97#ibcon#enter wrdev, iclass 23, count 0 2006.285.18:51:53.97#ibcon#first serial, iclass 23, count 0 2006.285.18:51:53.97#ibcon#enter sib2, iclass 23, count 0 2006.285.18:51:53.97#ibcon#flushed, iclass 23, count 0 2006.285.18:51:53.97#ibcon#about to write, iclass 23, count 0 2006.285.18:51:53.97#ibcon#wrote, iclass 23, count 0 2006.285.18:51:53.97#ibcon#about to read 3, iclass 23, count 0 2006.285.18:51:53.99#ibcon#read 3, iclass 23, count 0 2006.285.18:51:53.99#ibcon#about to read 4, iclass 23, count 0 2006.285.18:51:53.99#ibcon#read 4, iclass 23, count 0 2006.285.18:51:53.99#ibcon#about to read 5, iclass 23, count 0 2006.285.18:51:53.99#ibcon#read 5, iclass 23, count 0 2006.285.18:51:53.99#ibcon#about to read 6, iclass 23, count 0 2006.285.18:51:53.99#ibcon#read 6, iclass 23, count 0 2006.285.18:51:53.99#ibcon#end of sib2, iclass 23, count 0 2006.285.18:51:53.99#ibcon#*mode == 0, iclass 23, count 0 2006.285.18:51:53.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.18:51:53.99#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.18:51:53.99#ibcon#*before write, iclass 23, count 0 2006.285.18:51:53.99#ibcon#enter sib2, iclass 23, count 0 2006.285.18:51:53.99#ibcon#flushed, iclass 23, count 0 2006.285.18:51:53.99#ibcon#about to write, iclass 23, count 0 2006.285.18:51:53.99#ibcon#wrote, iclass 23, count 0 2006.285.18:51:53.99#ibcon#about to read 3, iclass 23, count 0 2006.285.18:51:54.03#ibcon#read 3, iclass 23, count 0 2006.285.18:51:54.03#ibcon#about to read 4, iclass 23, count 0 2006.285.18:51:54.03#ibcon#read 4, iclass 23, count 0 2006.285.18:51:54.03#ibcon#about to read 5, iclass 23, count 0 2006.285.18:51:54.03#ibcon#read 5, iclass 23, count 0 2006.285.18:51:54.03#ibcon#about to read 6, iclass 23, count 0 2006.285.18:51:54.03#ibcon#read 6, iclass 23, count 0 2006.285.18:51:54.03#ibcon#end of sib2, iclass 23, count 0 2006.285.18:51:54.03#ibcon#*after write, iclass 23, count 0 2006.285.18:51:54.03#ibcon#*before return 0, iclass 23, count 0 2006.285.18:51:54.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:51:54.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.18:51:54.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.18:51:54.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.18:51:54.03$vck44/vb=1,4 2006.285.18:51:54.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.18:51:54.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.18:51:54.03#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:54.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:51:54.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:51:54.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:51:54.03#ibcon#enter wrdev, iclass 25, count 2 2006.285.18:51:54.03#ibcon#first serial, iclass 25, count 2 2006.285.18:51:54.03#ibcon#enter sib2, iclass 25, count 2 2006.285.18:51:54.03#ibcon#flushed, iclass 25, count 2 2006.285.18:51:54.03#ibcon#about to write, iclass 25, count 2 2006.285.18:51:54.03#ibcon#wrote, iclass 25, count 2 2006.285.18:51:54.03#ibcon#about to read 3, iclass 25, count 2 2006.285.18:51:54.05#ibcon#read 3, iclass 25, count 2 2006.285.18:51:54.05#ibcon#about to read 4, iclass 25, count 2 2006.285.18:51:54.05#ibcon#read 4, iclass 25, count 2 2006.285.18:51:54.05#ibcon#about to read 5, iclass 25, count 2 2006.285.18:51:54.05#ibcon#read 5, iclass 25, count 2 2006.285.18:51:54.05#ibcon#about to read 6, iclass 25, count 2 2006.285.18:51:54.05#ibcon#read 6, iclass 25, count 2 2006.285.18:51:54.05#ibcon#end of sib2, iclass 25, count 2 2006.285.18:51:54.05#ibcon#*mode == 0, iclass 25, count 2 2006.285.18:51:54.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.18:51:54.05#ibcon#[27=AT01-04\r\n] 2006.285.18:51:54.05#ibcon#*before write, iclass 25, count 2 2006.285.18:51:54.05#ibcon#enter sib2, iclass 25, count 2 2006.285.18:51:54.05#ibcon#flushed, iclass 25, count 2 2006.285.18:51:54.05#ibcon#about to write, iclass 25, count 2 2006.285.18:51:54.05#ibcon#wrote, iclass 25, count 2 2006.285.18:51:54.05#ibcon#about to read 3, iclass 25, count 2 2006.285.18:51:54.08#ibcon#read 3, iclass 25, count 2 2006.285.18:51:54.08#ibcon#about to read 4, iclass 25, count 2 2006.285.18:51:54.08#ibcon#read 4, iclass 25, count 2 2006.285.18:51:54.08#ibcon#about to read 5, iclass 25, count 2 2006.285.18:51:54.08#ibcon#read 5, iclass 25, count 2 2006.285.18:51:54.08#ibcon#about to read 6, iclass 25, count 2 2006.285.18:51:54.08#ibcon#read 6, iclass 25, count 2 2006.285.18:51:54.08#ibcon#end of sib2, iclass 25, count 2 2006.285.18:51:54.08#ibcon#*after write, iclass 25, count 2 2006.285.18:51:54.08#ibcon#*before return 0, iclass 25, count 2 2006.285.18:51:54.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:51:54.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.18:51:54.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.18:51:54.08#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:54.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:51:54.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:51:54.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:51:54.20#ibcon#enter wrdev, iclass 25, count 0 2006.285.18:51:54.20#ibcon#first serial, iclass 25, count 0 2006.285.18:51:54.20#ibcon#enter sib2, iclass 25, count 0 2006.285.18:51:54.20#ibcon#flushed, iclass 25, count 0 2006.285.18:51:54.20#ibcon#about to write, iclass 25, count 0 2006.285.18:51:54.20#ibcon#wrote, iclass 25, count 0 2006.285.18:51:54.20#ibcon#about to read 3, iclass 25, count 0 2006.285.18:51:54.22#ibcon#read 3, iclass 25, count 0 2006.285.18:51:54.22#ibcon#about to read 4, iclass 25, count 0 2006.285.18:51:54.22#ibcon#read 4, iclass 25, count 0 2006.285.18:51:54.22#ibcon#about to read 5, iclass 25, count 0 2006.285.18:51:54.22#ibcon#read 5, iclass 25, count 0 2006.285.18:51:54.22#ibcon#about to read 6, iclass 25, count 0 2006.285.18:51:54.22#ibcon#read 6, iclass 25, count 0 2006.285.18:51:54.22#ibcon#end of sib2, iclass 25, count 0 2006.285.18:51:54.22#ibcon#*mode == 0, iclass 25, count 0 2006.285.18:51:54.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.18:51:54.22#ibcon#[27=USB\r\n] 2006.285.18:51:54.22#ibcon#*before write, iclass 25, count 0 2006.285.18:51:54.22#ibcon#enter sib2, iclass 25, count 0 2006.285.18:51:54.22#ibcon#flushed, iclass 25, count 0 2006.285.18:51:54.22#ibcon#about to write, iclass 25, count 0 2006.285.18:51:54.22#ibcon#wrote, iclass 25, count 0 2006.285.18:51:54.22#ibcon#about to read 3, iclass 25, count 0 2006.285.18:51:54.25#ibcon#read 3, iclass 25, count 0 2006.285.18:51:54.25#ibcon#about to read 4, iclass 25, count 0 2006.285.18:51:54.25#ibcon#read 4, iclass 25, count 0 2006.285.18:51:54.25#ibcon#about to read 5, iclass 25, count 0 2006.285.18:51:54.25#ibcon#read 5, iclass 25, count 0 2006.285.18:51:54.25#ibcon#about to read 6, iclass 25, count 0 2006.285.18:51:54.25#ibcon#read 6, iclass 25, count 0 2006.285.18:51:54.25#ibcon#end of sib2, iclass 25, count 0 2006.285.18:51:54.25#ibcon#*after write, iclass 25, count 0 2006.285.18:51:54.25#ibcon#*before return 0, iclass 25, count 0 2006.285.18:51:54.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:51:54.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.18:51:54.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.18:51:54.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.18:51:54.25$vck44/vblo=2,634.99 2006.285.18:51:54.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.18:51:54.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.18:51:54.25#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:54.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:51:54.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:51:54.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:51:54.25#ibcon#enter wrdev, iclass 27, count 0 2006.285.18:51:54.25#ibcon#first serial, iclass 27, count 0 2006.285.18:51:54.25#ibcon#enter sib2, iclass 27, count 0 2006.285.18:51:54.25#ibcon#flushed, iclass 27, count 0 2006.285.18:51:54.25#ibcon#about to write, iclass 27, count 0 2006.285.18:51:54.25#ibcon#wrote, iclass 27, count 0 2006.285.18:51:54.25#ibcon#about to read 3, iclass 27, count 0 2006.285.18:51:54.27#ibcon#read 3, iclass 27, count 0 2006.285.18:51:54.27#ibcon#about to read 4, iclass 27, count 0 2006.285.18:51:54.27#ibcon#read 4, iclass 27, count 0 2006.285.18:51:54.27#ibcon#about to read 5, iclass 27, count 0 2006.285.18:51:54.27#ibcon#read 5, iclass 27, count 0 2006.285.18:51:54.27#ibcon#about to read 6, iclass 27, count 0 2006.285.18:51:54.27#ibcon#read 6, iclass 27, count 0 2006.285.18:51:54.27#ibcon#end of sib2, iclass 27, count 0 2006.285.18:51:54.27#ibcon#*mode == 0, iclass 27, count 0 2006.285.18:51:54.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.18:51:54.27#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.18:51:54.27#ibcon#*before write, iclass 27, count 0 2006.285.18:51:54.27#ibcon#enter sib2, iclass 27, count 0 2006.285.18:51:54.27#ibcon#flushed, iclass 27, count 0 2006.285.18:51:54.27#ibcon#about to write, iclass 27, count 0 2006.285.18:51:54.27#ibcon#wrote, iclass 27, count 0 2006.285.18:51:54.27#ibcon#about to read 3, iclass 27, count 0 2006.285.18:51:54.31#ibcon#read 3, iclass 27, count 0 2006.285.18:51:54.31#ibcon#about to read 4, iclass 27, count 0 2006.285.18:51:54.31#ibcon#read 4, iclass 27, count 0 2006.285.18:51:54.31#ibcon#about to read 5, iclass 27, count 0 2006.285.18:51:54.31#ibcon#read 5, iclass 27, count 0 2006.285.18:51:54.31#ibcon#about to read 6, iclass 27, count 0 2006.285.18:51:54.31#ibcon#read 6, iclass 27, count 0 2006.285.18:51:54.31#ibcon#end of sib2, iclass 27, count 0 2006.285.18:51:54.31#ibcon#*after write, iclass 27, count 0 2006.285.18:51:54.31#ibcon#*before return 0, iclass 27, count 0 2006.285.18:51:54.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:51:54.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.18:51:54.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.18:51:54.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.18:51:54.31$vck44/vb=2,5 2006.285.18:51:54.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.18:51:54.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.18:51:54.31#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:54.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:51:54.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:51:54.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:51:54.37#ibcon#enter wrdev, iclass 29, count 2 2006.285.18:51:54.37#ibcon#first serial, iclass 29, count 2 2006.285.18:51:54.37#ibcon#enter sib2, iclass 29, count 2 2006.285.18:51:54.37#ibcon#flushed, iclass 29, count 2 2006.285.18:51:54.37#ibcon#about to write, iclass 29, count 2 2006.285.18:51:54.37#ibcon#wrote, iclass 29, count 2 2006.285.18:51:54.37#ibcon#about to read 3, iclass 29, count 2 2006.285.18:51:54.39#ibcon#read 3, iclass 29, count 2 2006.285.18:51:54.39#ibcon#about to read 4, iclass 29, count 2 2006.285.18:51:54.39#ibcon#read 4, iclass 29, count 2 2006.285.18:51:54.39#ibcon#about to read 5, iclass 29, count 2 2006.285.18:51:54.39#ibcon#read 5, iclass 29, count 2 2006.285.18:51:54.39#ibcon#about to read 6, iclass 29, count 2 2006.285.18:51:54.39#ibcon#read 6, iclass 29, count 2 2006.285.18:51:54.39#ibcon#end of sib2, iclass 29, count 2 2006.285.18:51:54.39#ibcon#*mode == 0, iclass 29, count 2 2006.285.18:51:54.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.18:51:54.39#ibcon#[27=AT02-05\r\n] 2006.285.18:51:54.39#ibcon#*before write, iclass 29, count 2 2006.285.18:51:54.39#ibcon#enter sib2, iclass 29, count 2 2006.285.18:51:54.39#ibcon#flushed, iclass 29, count 2 2006.285.18:51:54.39#ibcon#about to write, iclass 29, count 2 2006.285.18:51:54.39#ibcon#wrote, iclass 29, count 2 2006.285.18:51:54.39#ibcon#about to read 3, iclass 29, count 2 2006.285.18:51:54.42#ibcon#read 3, iclass 29, count 2 2006.285.18:51:54.42#ibcon#about to read 4, iclass 29, count 2 2006.285.18:51:54.42#ibcon#read 4, iclass 29, count 2 2006.285.18:51:54.42#ibcon#about to read 5, iclass 29, count 2 2006.285.18:51:54.42#ibcon#read 5, iclass 29, count 2 2006.285.18:51:54.42#ibcon#about to read 6, iclass 29, count 2 2006.285.18:51:54.42#ibcon#read 6, iclass 29, count 2 2006.285.18:51:54.42#ibcon#end of sib2, iclass 29, count 2 2006.285.18:51:54.42#ibcon#*after write, iclass 29, count 2 2006.285.18:51:54.42#ibcon#*before return 0, iclass 29, count 2 2006.285.18:51:54.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:51:54.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.18:51:54.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.18:51:54.42#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:54.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:51:54.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:51:54.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:51:54.54#ibcon#enter wrdev, iclass 29, count 0 2006.285.18:51:54.54#ibcon#first serial, iclass 29, count 0 2006.285.18:51:54.54#ibcon#enter sib2, iclass 29, count 0 2006.285.18:51:54.54#ibcon#flushed, iclass 29, count 0 2006.285.18:51:54.54#ibcon#about to write, iclass 29, count 0 2006.285.18:51:54.54#ibcon#wrote, iclass 29, count 0 2006.285.18:51:54.54#ibcon#about to read 3, iclass 29, count 0 2006.285.18:51:54.56#ibcon#read 3, iclass 29, count 0 2006.285.18:51:54.56#ibcon#about to read 4, iclass 29, count 0 2006.285.18:51:54.56#ibcon#read 4, iclass 29, count 0 2006.285.18:51:54.56#ibcon#about to read 5, iclass 29, count 0 2006.285.18:51:54.56#ibcon#read 5, iclass 29, count 0 2006.285.18:51:54.56#ibcon#about to read 6, iclass 29, count 0 2006.285.18:51:54.56#ibcon#read 6, iclass 29, count 0 2006.285.18:51:54.56#ibcon#end of sib2, iclass 29, count 0 2006.285.18:51:54.56#ibcon#*mode == 0, iclass 29, count 0 2006.285.18:51:54.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.18:51:54.56#ibcon#[27=USB\r\n] 2006.285.18:51:54.56#ibcon#*before write, iclass 29, count 0 2006.285.18:51:54.56#ibcon#enter sib2, iclass 29, count 0 2006.285.18:51:54.56#ibcon#flushed, iclass 29, count 0 2006.285.18:51:54.56#ibcon#about to write, iclass 29, count 0 2006.285.18:51:54.56#ibcon#wrote, iclass 29, count 0 2006.285.18:51:54.56#ibcon#about to read 3, iclass 29, count 0 2006.285.18:51:54.59#ibcon#read 3, iclass 29, count 0 2006.285.18:51:54.59#ibcon#about to read 4, iclass 29, count 0 2006.285.18:51:54.59#ibcon#read 4, iclass 29, count 0 2006.285.18:51:54.59#ibcon#about to read 5, iclass 29, count 0 2006.285.18:51:54.59#ibcon#read 5, iclass 29, count 0 2006.285.18:51:54.59#ibcon#about to read 6, iclass 29, count 0 2006.285.18:51:54.59#ibcon#read 6, iclass 29, count 0 2006.285.18:51:54.59#ibcon#end of sib2, iclass 29, count 0 2006.285.18:51:54.59#ibcon#*after write, iclass 29, count 0 2006.285.18:51:54.59#ibcon#*before return 0, iclass 29, count 0 2006.285.18:51:54.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:51:54.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.18:51:54.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.18:51:54.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.18:51:54.59$vck44/vblo=3,649.99 2006.285.18:51:54.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.18:51:54.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.18:51:54.59#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:54.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:51:54.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:51:54.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:51:54.59#ibcon#enter wrdev, iclass 31, count 0 2006.285.18:51:54.59#ibcon#first serial, iclass 31, count 0 2006.285.18:51:54.59#ibcon#enter sib2, iclass 31, count 0 2006.285.18:51:54.59#ibcon#flushed, iclass 31, count 0 2006.285.18:51:54.71#ibcon#about to write, iclass 31, count 0 2006.285.18:51:54.71#ibcon#wrote, iclass 31, count 0 2006.285.18:51:54.71#ibcon#about to read 3, iclass 31, count 0 2006.285.18:51:54.73#ibcon#read 3, iclass 31, count 0 2006.285.18:51:54.73#ibcon#about to read 4, iclass 31, count 0 2006.285.18:51:54.73#ibcon#read 4, iclass 31, count 0 2006.285.18:51:54.73#ibcon#about to read 5, iclass 31, count 0 2006.285.18:51:54.73#ibcon#read 5, iclass 31, count 0 2006.285.18:51:54.73#ibcon#about to read 6, iclass 31, count 0 2006.285.18:51:54.73#ibcon#read 6, iclass 31, count 0 2006.285.18:51:54.73#ibcon#end of sib2, iclass 31, count 0 2006.285.18:51:54.73#ibcon#*mode == 0, iclass 31, count 0 2006.285.18:51:54.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.18:51:54.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.18:51:54.73#ibcon#*before write, iclass 31, count 0 2006.285.18:51:54.73#ibcon#enter sib2, iclass 31, count 0 2006.285.18:51:54.73#ibcon#flushed, iclass 31, count 0 2006.285.18:51:54.73#ibcon#about to write, iclass 31, count 0 2006.285.18:51:54.73#ibcon#wrote, iclass 31, count 0 2006.285.18:51:54.73#ibcon#about to read 3, iclass 31, count 0 2006.285.18:51:54.77#ibcon#read 3, iclass 31, count 0 2006.285.18:51:54.77#ibcon#about to read 4, iclass 31, count 0 2006.285.18:51:54.77#ibcon#read 4, iclass 31, count 0 2006.285.18:51:54.77#ibcon#about to read 5, iclass 31, count 0 2006.285.18:51:54.77#ibcon#read 5, iclass 31, count 0 2006.285.18:51:54.77#ibcon#about to read 6, iclass 31, count 0 2006.285.18:51:54.77#ibcon#read 6, iclass 31, count 0 2006.285.18:51:54.77#ibcon#end of sib2, iclass 31, count 0 2006.285.18:51:54.77#ibcon#*after write, iclass 31, count 0 2006.285.18:51:54.77#ibcon#*before return 0, iclass 31, count 0 2006.285.18:51:54.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:51:54.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.18:51:54.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.18:51:54.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.18:51:54.77$vck44/vb=3,4 2006.285.18:51:54.77#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.18:51:54.77#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.18:51:54.77#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:54.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:51:54.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:51:54.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:51:54.77#ibcon#enter wrdev, iclass 33, count 2 2006.285.18:51:54.77#ibcon#first serial, iclass 33, count 2 2006.285.18:51:54.77#ibcon#enter sib2, iclass 33, count 2 2006.285.18:51:54.77#ibcon#flushed, iclass 33, count 2 2006.285.18:51:54.77#ibcon#about to write, iclass 33, count 2 2006.285.18:51:54.77#ibcon#wrote, iclass 33, count 2 2006.285.18:51:54.77#ibcon#about to read 3, iclass 33, count 2 2006.285.18:51:54.79#ibcon#read 3, iclass 33, count 2 2006.285.18:51:54.79#ibcon#about to read 4, iclass 33, count 2 2006.285.18:51:54.79#ibcon#read 4, iclass 33, count 2 2006.285.18:51:54.79#ibcon#about to read 5, iclass 33, count 2 2006.285.18:51:54.79#ibcon#read 5, iclass 33, count 2 2006.285.18:51:54.79#ibcon#about to read 6, iclass 33, count 2 2006.285.18:51:54.79#ibcon#read 6, iclass 33, count 2 2006.285.18:51:54.79#ibcon#end of sib2, iclass 33, count 2 2006.285.18:51:54.79#ibcon#*mode == 0, iclass 33, count 2 2006.285.18:51:54.79#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.18:51:54.79#ibcon#[27=AT03-04\r\n] 2006.285.18:51:54.79#ibcon#*before write, iclass 33, count 2 2006.285.18:51:54.79#ibcon#enter sib2, iclass 33, count 2 2006.285.18:51:54.79#ibcon#flushed, iclass 33, count 2 2006.285.18:51:54.79#ibcon#about to write, iclass 33, count 2 2006.285.18:51:54.79#ibcon#wrote, iclass 33, count 2 2006.285.18:51:54.79#ibcon#about to read 3, iclass 33, count 2 2006.285.18:51:54.82#ibcon#read 3, iclass 33, count 2 2006.285.18:51:54.82#ibcon#about to read 4, iclass 33, count 2 2006.285.18:51:54.82#ibcon#read 4, iclass 33, count 2 2006.285.18:51:54.82#ibcon#about to read 5, iclass 33, count 2 2006.285.18:51:54.82#ibcon#read 5, iclass 33, count 2 2006.285.18:51:54.82#ibcon#about to read 6, iclass 33, count 2 2006.285.18:51:54.82#ibcon#read 6, iclass 33, count 2 2006.285.18:51:54.82#ibcon#end of sib2, iclass 33, count 2 2006.285.18:51:54.82#ibcon#*after write, iclass 33, count 2 2006.285.18:51:54.82#ibcon#*before return 0, iclass 33, count 2 2006.285.18:51:54.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:51:54.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.18:51:54.82#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.18:51:54.82#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:54.82#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:51:54.94#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:51:54.94#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:51:54.94#ibcon#enter wrdev, iclass 33, count 0 2006.285.18:51:54.94#ibcon#first serial, iclass 33, count 0 2006.285.18:51:54.94#ibcon#enter sib2, iclass 33, count 0 2006.285.18:51:54.94#ibcon#flushed, iclass 33, count 0 2006.285.18:51:54.94#ibcon#about to write, iclass 33, count 0 2006.285.18:51:54.94#ibcon#wrote, iclass 33, count 0 2006.285.18:51:54.94#ibcon#about to read 3, iclass 33, count 0 2006.285.18:51:54.96#ibcon#read 3, iclass 33, count 0 2006.285.18:51:54.96#ibcon#about to read 4, iclass 33, count 0 2006.285.18:51:54.96#ibcon#read 4, iclass 33, count 0 2006.285.18:51:54.96#ibcon#about to read 5, iclass 33, count 0 2006.285.18:51:54.96#ibcon#read 5, iclass 33, count 0 2006.285.18:51:54.96#ibcon#about to read 6, iclass 33, count 0 2006.285.18:51:54.96#ibcon#read 6, iclass 33, count 0 2006.285.18:51:54.96#ibcon#end of sib2, iclass 33, count 0 2006.285.18:51:54.96#ibcon#*mode == 0, iclass 33, count 0 2006.285.18:51:54.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.18:51:54.96#ibcon#[27=USB\r\n] 2006.285.18:51:54.96#ibcon#*before write, iclass 33, count 0 2006.285.18:51:54.96#ibcon#enter sib2, iclass 33, count 0 2006.285.18:51:54.96#ibcon#flushed, iclass 33, count 0 2006.285.18:51:54.96#ibcon#about to write, iclass 33, count 0 2006.285.18:51:54.96#ibcon#wrote, iclass 33, count 0 2006.285.18:51:54.96#ibcon#about to read 3, iclass 33, count 0 2006.285.18:51:54.99#ibcon#read 3, iclass 33, count 0 2006.285.18:51:54.99#ibcon#about to read 4, iclass 33, count 0 2006.285.18:51:54.99#ibcon#read 4, iclass 33, count 0 2006.285.18:51:54.99#ibcon#about to read 5, iclass 33, count 0 2006.285.18:51:54.99#ibcon#read 5, iclass 33, count 0 2006.285.18:51:54.99#ibcon#about to read 6, iclass 33, count 0 2006.285.18:51:54.99#ibcon#read 6, iclass 33, count 0 2006.285.18:51:54.99#ibcon#end of sib2, iclass 33, count 0 2006.285.18:51:54.99#ibcon#*after write, iclass 33, count 0 2006.285.18:51:54.99#ibcon#*before return 0, iclass 33, count 0 2006.285.18:51:54.99#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:51:54.99#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.18:51:54.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.18:51:54.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.18:51:54.99$vck44/vblo=4,679.99 2006.285.18:51:54.99#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.18:51:54.99#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.18:51:54.99#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:54.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:51:54.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:51:54.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:51:54.99#ibcon#enter wrdev, iclass 35, count 0 2006.285.18:51:54.99#ibcon#first serial, iclass 35, count 0 2006.285.18:51:54.99#ibcon#enter sib2, iclass 35, count 0 2006.285.18:51:54.99#ibcon#flushed, iclass 35, count 0 2006.285.18:51:54.99#ibcon#about to write, iclass 35, count 0 2006.285.18:51:54.99#ibcon#wrote, iclass 35, count 0 2006.285.18:51:54.99#ibcon#about to read 3, iclass 35, count 0 2006.285.18:51:55.01#ibcon#read 3, iclass 35, count 0 2006.285.18:51:55.01#ibcon#about to read 4, iclass 35, count 0 2006.285.18:51:55.01#ibcon#read 4, iclass 35, count 0 2006.285.18:51:55.01#ibcon#about to read 5, iclass 35, count 0 2006.285.18:51:55.01#ibcon#read 5, iclass 35, count 0 2006.285.18:51:55.01#ibcon#about to read 6, iclass 35, count 0 2006.285.18:51:55.01#ibcon#read 6, iclass 35, count 0 2006.285.18:51:55.01#ibcon#end of sib2, iclass 35, count 0 2006.285.18:51:55.01#ibcon#*mode == 0, iclass 35, count 0 2006.285.18:51:55.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.18:51:55.01#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.18:51:55.01#ibcon#*before write, iclass 35, count 0 2006.285.18:51:55.01#ibcon#enter sib2, iclass 35, count 0 2006.285.18:51:55.01#ibcon#flushed, iclass 35, count 0 2006.285.18:51:55.01#ibcon#about to write, iclass 35, count 0 2006.285.18:51:55.01#ibcon#wrote, iclass 35, count 0 2006.285.18:51:55.01#ibcon#about to read 3, iclass 35, count 0 2006.285.18:51:55.05#ibcon#read 3, iclass 35, count 0 2006.285.18:51:55.05#ibcon#about to read 4, iclass 35, count 0 2006.285.18:51:55.05#ibcon#read 4, iclass 35, count 0 2006.285.18:51:55.05#ibcon#about to read 5, iclass 35, count 0 2006.285.18:51:55.05#ibcon#read 5, iclass 35, count 0 2006.285.18:51:55.05#ibcon#about to read 6, iclass 35, count 0 2006.285.18:51:55.05#ibcon#read 6, iclass 35, count 0 2006.285.18:51:55.05#ibcon#end of sib2, iclass 35, count 0 2006.285.18:51:55.05#ibcon#*after write, iclass 35, count 0 2006.285.18:51:55.05#ibcon#*before return 0, iclass 35, count 0 2006.285.18:51:55.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:51:55.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.18:51:55.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.18:51:55.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.18:51:55.05$vck44/vb=4,5 2006.285.18:51:55.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.18:51:55.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.18:51:55.05#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:55.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:51:55.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:51:55.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:51:55.11#ibcon#enter wrdev, iclass 37, count 2 2006.285.18:51:55.11#ibcon#first serial, iclass 37, count 2 2006.285.18:51:55.11#ibcon#enter sib2, iclass 37, count 2 2006.285.18:51:55.11#ibcon#flushed, iclass 37, count 2 2006.285.18:51:55.11#ibcon#about to write, iclass 37, count 2 2006.285.18:51:55.11#ibcon#wrote, iclass 37, count 2 2006.285.18:51:55.11#ibcon#about to read 3, iclass 37, count 2 2006.285.18:51:55.13#ibcon#read 3, iclass 37, count 2 2006.285.18:51:55.13#ibcon#about to read 4, iclass 37, count 2 2006.285.18:51:55.13#ibcon#read 4, iclass 37, count 2 2006.285.18:51:55.13#ibcon#about to read 5, iclass 37, count 2 2006.285.18:51:55.13#ibcon#read 5, iclass 37, count 2 2006.285.18:51:55.13#ibcon#about to read 6, iclass 37, count 2 2006.285.18:51:55.13#ibcon#read 6, iclass 37, count 2 2006.285.18:51:55.13#ibcon#end of sib2, iclass 37, count 2 2006.285.18:51:55.13#ibcon#*mode == 0, iclass 37, count 2 2006.285.18:51:55.13#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.18:51:55.13#ibcon#[27=AT04-05\r\n] 2006.285.18:51:55.13#ibcon#*before write, iclass 37, count 2 2006.285.18:51:55.13#ibcon#enter sib2, iclass 37, count 2 2006.285.18:51:55.13#ibcon#flushed, iclass 37, count 2 2006.285.18:51:55.13#ibcon#about to write, iclass 37, count 2 2006.285.18:51:55.13#ibcon#wrote, iclass 37, count 2 2006.285.18:51:55.13#ibcon#about to read 3, iclass 37, count 2 2006.285.18:51:55.16#ibcon#read 3, iclass 37, count 2 2006.285.18:51:55.16#ibcon#about to read 4, iclass 37, count 2 2006.285.18:51:55.16#ibcon#read 4, iclass 37, count 2 2006.285.18:51:55.16#ibcon#about to read 5, iclass 37, count 2 2006.285.18:51:55.16#ibcon#read 5, iclass 37, count 2 2006.285.18:51:55.16#ibcon#about to read 6, iclass 37, count 2 2006.285.18:51:55.16#ibcon#read 6, iclass 37, count 2 2006.285.18:51:55.16#ibcon#end of sib2, iclass 37, count 2 2006.285.18:51:55.16#ibcon#*after write, iclass 37, count 2 2006.285.18:51:55.16#ibcon#*before return 0, iclass 37, count 2 2006.285.18:51:55.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:51:55.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.18:51:55.16#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.18:51:55.16#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:55.16#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:51:55.28#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:51:55.28#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:51:55.28#ibcon#enter wrdev, iclass 37, count 0 2006.285.18:51:55.28#ibcon#first serial, iclass 37, count 0 2006.285.18:51:55.28#ibcon#enter sib2, iclass 37, count 0 2006.285.18:51:55.28#ibcon#flushed, iclass 37, count 0 2006.285.18:51:55.28#ibcon#about to write, iclass 37, count 0 2006.285.18:51:55.28#ibcon#wrote, iclass 37, count 0 2006.285.18:51:55.28#ibcon#about to read 3, iclass 37, count 0 2006.285.18:51:55.30#ibcon#read 3, iclass 37, count 0 2006.285.18:51:55.30#ibcon#about to read 4, iclass 37, count 0 2006.285.18:51:55.30#ibcon#read 4, iclass 37, count 0 2006.285.18:51:55.30#ibcon#about to read 5, iclass 37, count 0 2006.285.18:51:55.30#ibcon#read 5, iclass 37, count 0 2006.285.18:51:55.30#ibcon#about to read 6, iclass 37, count 0 2006.285.18:51:55.30#ibcon#read 6, iclass 37, count 0 2006.285.18:51:55.30#ibcon#end of sib2, iclass 37, count 0 2006.285.18:51:55.30#ibcon#*mode == 0, iclass 37, count 0 2006.285.18:51:55.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.18:51:55.30#ibcon#[27=USB\r\n] 2006.285.18:51:55.30#ibcon#*before write, iclass 37, count 0 2006.285.18:51:55.30#ibcon#enter sib2, iclass 37, count 0 2006.285.18:51:55.30#ibcon#flushed, iclass 37, count 0 2006.285.18:51:55.30#ibcon#about to write, iclass 37, count 0 2006.285.18:51:55.30#ibcon#wrote, iclass 37, count 0 2006.285.18:51:55.30#ibcon#about to read 3, iclass 37, count 0 2006.285.18:51:55.33#ibcon#read 3, iclass 37, count 0 2006.285.18:51:55.33#ibcon#about to read 4, iclass 37, count 0 2006.285.18:51:55.33#ibcon#read 4, iclass 37, count 0 2006.285.18:51:55.33#ibcon#about to read 5, iclass 37, count 0 2006.285.18:51:55.33#ibcon#read 5, iclass 37, count 0 2006.285.18:51:55.33#ibcon#about to read 6, iclass 37, count 0 2006.285.18:51:55.33#ibcon#read 6, iclass 37, count 0 2006.285.18:51:55.33#ibcon#end of sib2, iclass 37, count 0 2006.285.18:51:55.33#ibcon#*after write, iclass 37, count 0 2006.285.18:51:55.33#ibcon#*before return 0, iclass 37, count 0 2006.285.18:51:55.33#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:51:55.33#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.18:51:55.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.18:51:55.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.18:51:55.33$vck44/vblo=5,709.99 2006.285.18:51:55.33#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.18:51:55.33#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.18:51:55.33#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:55.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:51:55.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:51:55.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:51:55.33#ibcon#enter wrdev, iclass 39, count 0 2006.285.18:51:55.33#ibcon#first serial, iclass 39, count 0 2006.285.18:51:55.33#ibcon#enter sib2, iclass 39, count 0 2006.285.18:51:55.33#ibcon#flushed, iclass 39, count 0 2006.285.18:51:55.33#ibcon#about to write, iclass 39, count 0 2006.285.18:51:55.33#ibcon#wrote, iclass 39, count 0 2006.285.18:51:55.33#ibcon#about to read 3, iclass 39, count 0 2006.285.18:51:55.35#ibcon#read 3, iclass 39, count 0 2006.285.18:51:55.35#ibcon#about to read 4, iclass 39, count 0 2006.285.18:51:55.35#ibcon#read 4, iclass 39, count 0 2006.285.18:51:55.35#ibcon#about to read 5, iclass 39, count 0 2006.285.18:51:55.35#ibcon#read 5, iclass 39, count 0 2006.285.18:51:55.35#ibcon#about to read 6, iclass 39, count 0 2006.285.18:51:55.35#ibcon#read 6, iclass 39, count 0 2006.285.18:51:55.35#ibcon#end of sib2, iclass 39, count 0 2006.285.18:51:55.35#ibcon#*mode == 0, iclass 39, count 0 2006.285.18:51:55.35#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.18:51:55.35#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.18:51:55.35#ibcon#*before write, iclass 39, count 0 2006.285.18:51:55.35#ibcon#enter sib2, iclass 39, count 0 2006.285.18:51:55.35#ibcon#flushed, iclass 39, count 0 2006.285.18:51:55.35#ibcon#about to write, iclass 39, count 0 2006.285.18:51:55.35#ibcon#wrote, iclass 39, count 0 2006.285.18:51:55.35#ibcon#about to read 3, iclass 39, count 0 2006.285.18:51:55.39#ibcon#read 3, iclass 39, count 0 2006.285.18:51:55.39#ibcon#about to read 4, iclass 39, count 0 2006.285.18:51:55.39#ibcon#read 4, iclass 39, count 0 2006.285.18:51:55.39#ibcon#about to read 5, iclass 39, count 0 2006.285.18:51:55.39#ibcon#read 5, iclass 39, count 0 2006.285.18:51:55.39#ibcon#about to read 6, iclass 39, count 0 2006.285.18:51:55.39#ibcon#read 6, iclass 39, count 0 2006.285.18:51:55.39#ibcon#end of sib2, iclass 39, count 0 2006.285.18:51:55.39#ibcon#*after write, iclass 39, count 0 2006.285.18:51:55.39#ibcon#*before return 0, iclass 39, count 0 2006.285.18:51:55.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:51:55.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.18:51:55.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.18:51:55.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.18:51:55.39$vck44/vb=5,4 2006.285.18:51:55.39#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.18:51:55.39#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.18:51:55.39#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:55.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:51:55.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:51:55.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:51:55.45#ibcon#enter wrdev, iclass 3, count 2 2006.285.18:51:55.45#ibcon#first serial, iclass 3, count 2 2006.285.18:51:55.45#ibcon#enter sib2, iclass 3, count 2 2006.285.18:51:55.45#ibcon#flushed, iclass 3, count 2 2006.285.18:51:55.45#ibcon#about to write, iclass 3, count 2 2006.285.18:51:55.45#ibcon#wrote, iclass 3, count 2 2006.285.18:51:55.45#ibcon#about to read 3, iclass 3, count 2 2006.285.18:51:55.47#ibcon#read 3, iclass 3, count 2 2006.285.18:51:55.47#ibcon#about to read 4, iclass 3, count 2 2006.285.18:51:55.47#ibcon#read 4, iclass 3, count 2 2006.285.18:51:55.47#ibcon#about to read 5, iclass 3, count 2 2006.285.18:51:55.47#ibcon#read 5, iclass 3, count 2 2006.285.18:51:55.47#ibcon#about to read 6, iclass 3, count 2 2006.285.18:51:55.47#ibcon#read 6, iclass 3, count 2 2006.285.18:51:55.47#ibcon#end of sib2, iclass 3, count 2 2006.285.18:51:55.47#ibcon#*mode == 0, iclass 3, count 2 2006.285.18:51:55.47#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.18:51:55.47#ibcon#[27=AT05-04\r\n] 2006.285.18:51:55.47#ibcon#*before write, iclass 3, count 2 2006.285.18:51:55.47#ibcon#enter sib2, iclass 3, count 2 2006.285.18:51:55.47#ibcon#flushed, iclass 3, count 2 2006.285.18:51:55.47#ibcon#about to write, iclass 3, count 2 2006.285.18:51:55.47#ibcon#wrote, iclass 3, count 2 2006.285.18:51:55.47#ibcon#about to read 3, iclass 3, count 2 2006.285.18:51:55.50#ibcon#read 3, iclass 3, count 2 2006.285.18:51:55.50#ibcon#about to read 4, iclass 3, count 2 2006.285.18:51:55.50#ibcon#read 4, iclass 3, count 2 2006.285.18:51:55.50#ibcon#about to read 5, iclass 3, count 2 2006.285.18:51:55.50#ibcon#read 5, iclass 3, count 2 2006.285.18:51:55.50#ibcon#about to read 6, iclass 3, count 2 2006.285.18:51:55.50#ibcon#read 6, iclass 3, count 2 2006.285.18:51:55.50#ibcon#end of sib2, iclass 3, count 2 2006.285.18:51:55.50#ibcon#*after write, iclass 3, count 2 2006.285.18:51:55.50#ibcon#*before return 0, iclass 3, count 2 2006.285.18:51:55.50#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:51:55.50#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.18:51:55.50#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.18:51:55.50#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:55.50#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:51:55.62#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:51:55.62#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:51:55.62#ibcon#enter wrdev, iclass 3, count 0 2006.285.18:51:55.62#ibcon#first serial, iclass 3, count 0 2006.285.18:51:55.62#ibcon#enter sib2, iclass 3, count 0 2006.285.18:51:55.62#ibcon#flushed, iclass 3, count 0 2006.285.18:51:55.62#ibcon#about to write, iclass 3, count 0 2006.285.18:51:55.62#ibcon#wrote, iclass 3, count 0 2006.285.18:51:55.62#ibcon#about to read 3, iclass 3, count 0 2006.285.18:51:55.64#ibcon#read 3, iclass 3, count 0 2006.285.18:51:55.64#ibcon#about to read 4, iclass 3, count 0 2006.285.18:51:55.64#ibcon#read 4, iclass 3, count 0 2006.285.18:51:55.64#ibcon#about to read 5, iclass 3, count 0 2006.285.18:51:55.64#ibcon#read 5, iclass 3, count 0 2006.285.18:51:55.64#ibcon#about to read 6, iclass 3, count 0 2006.285.18:51:55.64#ibcon#read 6, iclass 3, count 0 2006.285.18:51:55.64#ibcon#end of sib2, iclass 3, count 0 2006.285.18:51:55.64#ibcon#*mode == 0, iclass 3, count 0 2006.285.18:51:55.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.18:51:55.64#ibcon#[27=USB\r\n] 2006.285.18:51:55.64#ibcon#*before write, iclass 3, count 0 2006.285.18:51:55.64#ibcon#enter sib2, iclass 3, count 0 2006.285.18:51:55.64#ibcon#flushed, iclass 3, count 0 2006.285.18:51:55.64#ibcon#about to write, iclass 3, count 0 2006.285.18:51:55.64#ibcon#wrote, iclass 3, count 0 2006.285.18:51:55.64#ibcon#about to read 3, iclass 3, count 0 2006.285.18:51:55.67#ibcon#read 3, iclass 3, count 0 2006.285.18:51:55.67#ibcon#about to read 4, iclass 3, count 0 2006.285.18:51:55.67#ibcon#read 4, iclass 3, count 0 2006.285.18:51:55.67#ibcon#about to read 5, iclass 3, count 0 2006.285.18:51:55.67#ibcon#read 5, iclass 3, count 0 2006.285.18:51:55.67#ibcon#about to read 6, iclass 3, count 0 2006.285.18:51:55.67#ibcon#read 6, iclass 3, count 0 2006.285.18:51:55.67#ibcon#end of sib2, iclass 3, count 0 2006.285.18:51:55.67#ibcon#*after write, iclass 3, count 0 2006.285.18:51:55.67#ibcon#*before return 0, iclass 3, count 0 2006.285.18:51:55.67#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:51:55.67#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.18:51:55.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.18:51:55.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.18:51:55.67$vck44/vblo=6,719.99 2006.285.18:51:55.67#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.18:51:55.67#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.18:51:55.67#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:55.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:51:55.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:51:55.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:51:55.67#ibcon#enter wrdev, iclass 5, count 0 2006.285.18:51:55.67#ibcon#first serial, iclass 5, count 0 2006.285.18:51:55.67#ibcon#enter sib2, iclass 5, count 0 2006.285.18:51:55.67#ibcon#flushed, iclass 5, count 0 2006.285.18:51:55.93#ibcon#about to write, iclass 5, count 0 2006.285.18:51:55.93#ibcon#wrote, iclass 5, count 0 2006.285.18:51:55.93#ibcon#about to read 3, iclass 5, count 0 2006.285.18:51:55.95#ibcon#read 3, iclass 5, count 0 2006.285.18:51:55.95#ibcon#about to read 4, iclass 5, count 0 2006.285.18:51:55.95#ibcon#read 4, iclass 5, count 0 2006.285.18:51:55.95#ibcon#about to read 5, iclass 5, count 0 2006.285.18:51:55.95#ibcon#read 5, iclass 5, count 0 2006.285.18:51:55.95#ibcon#about to read 6, iclass 5, count 0 2006.285.18:51:55.95#ibcon#read 6, iclass 5, count 0 2006.285.18:51:55.95#ibcon#end of sib2, iclass 5, count 0 2006.285.18:51:55.95#ibcon#*mode == 0, iclass 5, count 0 2006.285.18:51:55.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.18:51:55.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.18:51:55.95#ibcon#*before write, iclass 5, count 0 2006.285.18:51:55.95#ibcon#enter sib2, iclass 5, count 0 2006.285.18:51:55.95#ibcon#flushed, iclass 5, count 0 2006.285.18:51:55.95#ibcon#about to write, iclass 5, count 0 2006.285.18:51:55.95#ibcon#wrote, iclass 5, count 0 2006.285.18:51:55.95#ibcon#about to read 3, iclass 5, count 0 2006.285.18:51:55.99#ibcon#read 3, iclass 5, count 0 2006.285.18:51:55.99#ibcon#about to read 4, iclass 5, count 0 2006.285.18:51:55.99#ibcon#read 4, iclass 5, count 0 2006.285.18:51:55.99#ibcon#about to read 5, iclass 5, count 0 2006.285.18:51:55.99#ibcon#read 5, iclass 5, count 0 2006.285.18:51:55.99#ibcon#about to read 6, iclass 5, count 0 2006.285.18:51:55.99#ibcon#read 6, iclass 5, count 0 2006.285.18:51:55.99#ibcon#end of sib2, iclass 5, count 0 2006.285.18:51:55.99#ibcon#*after write, iclass 5, count 0 2006.285.18:51:55.99#ibcon#*before return 0, iclass 5, count 0 2006.285.18:51:55.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:51:55.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.18:51:55.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.18:51:55.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.18:51:55.99$vck44/vb=6,3 2006.285.18:51:55.99#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.18:51:55.99#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.18:51:55.99#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:55.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:51:55.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:51:55.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:51:55.99#ibcon#enter wrdev, iclass 7, count 2 2006.285.18:51:55.99#ibcon#first serial, iclass 7, count 2 2006.285.18:51:55.99#ibcon#enter sib2, iclass 7, count 2 2006.285.18:51:55.99#ibcon#flushed, iclass 7, count 2 2006.285.18:51:55.99#ibcon#about to write, iclass 7, count 2 2006.285.18:51:55.99#ibcon#wrote, iclass 7, count 2 2006.285.18:51:55.99#ibcon#about to read 3, iclass 7, count 2 2006.285.18:51:56.01#ibcon#read 3, iclass 7, count 2 2006.285.18:51:56.01#ibcon#about to read 4, iclass 7, count 2 2006.285.18:51:56.01#ibcon#read 4, iclass 7, count 2 2006.285.18:51:56.01#ibcon#about to read 5, iclass 7, count 2 2006.285.18:51:56.01#ibcon#read 5, iclass 7, count 2 2006.285.18:51:56.01#ibcon#about to read 6, iclass 7, count 2 2006.285.18:51:56.01#ibcon#read 6, iclass 7, count 2 2006.285.18:51:56.01#ibcon#end of sib2, iclass 7, count 2 2006.285.18:51:56.01#ibcon#*mode == 0, iclass 7, count 2 2006.285.18:51:56.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.18:51:56.01#ibcon#[27=AT06-03\r\n] 2006.285.18:51:56.01#ibcon#*before write, iclass 7, count 2 2006.285.18:51:56.01#ibcon#enter sib2, iclass 7, count 2 2006.285.18:51:56.01#ibcon#flushed, iclass 7, count 2 2006.285.18:51:56.01#ibcon#about to write, iclass 7, count 2 2006.285.18:51:56.01#ibcon#wrote, iclass 7, count 2 2006.285.18:51:56.01#ibcon#about to read 3, iclass 7, count 2 2006.285.18:51:56.04#ibcon#read 3, iclass 7, count 2 2006.285.18:51:56.04#ibcon#about to read 4, iclass 7, count 2 2006.285.18:51:56.04#ibcon#read 4, iclass 7, count 2 2006.285.18:51:56.04#ibcon#about to read 5, iclass 7, count 2 2006.285.18:51:56.04#ibcon#read 5, iclass 7, count 2 2006.285.18:51:56.04#ibcon#about to read 6, iclass 7, count 2 2006.285.18:51:56.04#ibcon#read 6, iclass 7, count 2 2006.285.18:51:56.04#ibcon#end of sib2, iclass 7, count 2 2006.285.18:51:56.04#ibcon#*after write, iclass 7, count 2 2006.285.18:51:56.04#ibcon#*before return 0, iclass 7, count 2 2006.285.18:51:56.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:51:56.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.18:51:56.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.18:51:56.04#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:56.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:51:56.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:51:56.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:51:56.16#ibcon#enter wrdev, iclass 7, count 0 2006.285.18:51:56.16#ibcon#first serial, iclass 7, count 0 2006.285.18:51:56.16#ibcon#enter sib2, iclass 7, count 0 2006.285.18:51:56.16#ibcon#flushed, iclass 7, count 0 2006.285.18:51:56.16#ibcon#about to write, iclass 7, count 0 2006.285.18:51:56.16#ibcon#wrote, iclass 7, count 0 2006.285.18:51:56.16#ibcon#about to read 3, iclass 7, count 0 2006.285.18:51:56.18#ibcon#read 3, iclass 7, count 0 2006.285.18:51:56.18#ibcon#about to read 4, iclass 7, count 0 2006.285.18:51:56.18#ibcon#read 4, iclass 7, count 0 2006.285.18:51:56.18#ibcon#about to read 5, iclass 7, count 0 2006.285.18:51:56.18#ibcon#read 5, iclass 7, count 0 2006.285.18:51:56.18#ibcon#about to read 6, iclass 7, count 0 2006.285.18:51:56.18#ibcon#read 6, iclass 7, count 0 2006.285.18:51:56.18#ibcon#end of sib2, iclass 7, count 0 2006.285.18:51:56.18#ibcon#*mode == 0, iclass 7, count 0 2006.285.18:51:56.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.18:51:56.18#ibcon#[27=USB\r\n] 2006.285.18:51:56.18#ibcon#*before write, iclass 7, count 0 2006.285.18:51:56.18#ibcon#enter sib2, iclass 7, count 0 2006.285.18:51:56.18#ibcon#flushed, iclass 7, count 0 2006.285.18:51:56.18#ibcon#about to write, iclass 7, count 0 2006.285.18:51:56.18#ibcon#wrote, iclass 7, count 0 2006.285.18:51:56.18#ibcon#about to read 3, iclass 7, count 0 2006.285.18:51:56.21#ibcon#read 3, iclass 7, count 0 2006.285.18:51:56.21#ibcon#about to read 4, iclass 7, count 0 2006.285.18:51:56.21#ibcon#read 4, iclass 7, count 0 2006.285.18:51:56.21#ibcon#about to read 5, iclass 7, count 0 2006.285.18:51:56.21#ibcon#read 5, iclass 7, count 0 2006.285.18:51:56.21#ibcon#about to read 6, iclass 7, count 0 2006.285.18:51:56.21#ibcon#read 6, iclass 7, count 0 2006.285.18:51:56.21#ibcon#end of sib2, iclass 7, count 0 2006.285.18:51:56.21#ibcon#*after write, iclass 7, count 0 2006.285.18:51:56.21#ibcon#*before return 0, iclass 7, count 0 2006.285.18:51:56.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:51:56.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.18:51:56.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.18:51:56.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.18:51:56.21$vck44/vblo=7,734.99 2006.285.18:51:56.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.18:51:56.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.18:51:56.21#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:56.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:51:56.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:51:56.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:51:56.21#ibcon#enter wrdev, iclass 11, count 0 2006.285.18:51:56.21#ibcon#first serial, iclass 11, count 0 2006.285.18:51:56.21#ibcon#enter sib2, iclass 11, count 0 2006.285.18:51:56.21#ibcon#flushed, iclass 11, count 0 2006.285.18:51:56.21#ibcon#about to write, iclass 11, count 0 2006.285.18:51:56.21#ibcon#wrote, iclass 11, count 0 2006.285.18:51:56.21#ibcon#about to read 3, iclass 11, count 0 2006.285.18:51:56.23#ibcon#read 3, iclass 11, count 0 2006.285.18:51:56.23#ibcon#about to read 4, iclass 11, count 0 2006.285.18:51:56.23#ibcon#read 4, iclass 11, count 0 2006.285.18:51:56.23#ibcon#about to read 5, iclass 11, count 0 2006.285.18:51:56.23#ibcon#read 5, iclass 11, count 0 2006.285.18:51:56.23#ibcon#about to read 6, iclass 11, count 0 2006.285.18:51:56.23#ibcon#read 6, iclass 11, count 0 2006.285.18:51:56.23#ibcon#end of sib2, iclass 11, count 0 2006.285.18:51:56.23#ibcon#*mode == 0, iclass 11, count 0 2006.285.18:51:56.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.18:51:56.23#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.18:51:56.23#ibcon#*before write, iclass 11, count 0 2006.285.18:51:56.23#ibcon#enter sib2, iclass 11, count 0 2006.285.18:51:56.23#ibcon#flushed, iclass 11, count 0 2006.285.18:51:56.23#ibcon#about to write, iclass 11, count 0 2006.285.18:51:56.23#ibcon#wrote, iclass 11, count 0 2006.285.18:51:56.23#ibcon#about to read 3, iclass 11, count 0 2006.285.18:51:56.27#ibcon#read 3, iclass 11, count 0 2006.285.18:51:56.27#ibcon#about to read 4, iclass 11, count 0 2006.285.18:51:56.27#ibcon#read 4, iclass 11, count 0 2006.285.18:51:56.27#ibcon#about to read 5, iclass 11, count 0 2006.285.18:51:56.27#ibcon#read 5, iclass 11, count 0 2006.285.18:51:56.27#ibcon#about to read 6, iclass 11, count 0 2006.285.18:51:56.27#ibcon#read 6, iclass 11, count 0 2006.285.18:51:56.27#ibcon#end of sib2, iclass 11, count 0 2006.285.18:51:56.27#ibcon#*after write, iclass 11, count 0 2006.285.18:51:56.27#ibcon#*before return 0, iclass 11, count 0 2006.285.18:51:56.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:51:56.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.18:51:56.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.18:51:56.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.18:51:56.27$vck44/vb=7,4 2006.285.18:51:56.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.18:51:56.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.18:51:56.27#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:56.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:51:56.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:51:56.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:51:56.33#ibcon#enter wrdev, iclass 13, count 2 2006.285.18:51:56.33#ibcon#first serial, iclass 13, count 2 2006.285.18:51:56.33#ibcon#enter sib2, iclass 13, count 2 2006.285.18:51:56.33#ibcon#flushed, iclass 13, count 2 2006.285.18:51:56.33#ibcon#about to write, iclass 13, count 2 2006.285.18:51:56.33#ibcon#wrote, iclass 13, count 2 2006.285.18:51:56.33#ibcon#about to read 3, iclass 13, count 2 2006.285.18:51:56.35#ibcon#read 3, iclass 13, count 2 2006.285.18:51:56.35#ibcon#about to read 4, iclass 13, count 2 2006.285.18:51:56.35#ibcon#read 4, iclass 13, count 2 2006.285.18:51:56.35#ibcon#about to read 5, iclass 13, count 2 2006.285.18:51:56.35#ibcon#read 5, iclass 13, count 2 2006.285.18:51:56.35#ibcon#about to read 6, iclass 13, count 2 2006.285.18:51:56.35#ibcon#read 6, iclass 13, count 2 2006.285.18:51:56.35#ibcon#end of sib2, iclass 13, count 2 2006.285.18:51:56.35#ibcon#*mode == 0, iclass 13, count 2 2006.285.18:51:56.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.18:51:56.35#ibcon#[27=AT07-04\r\n] 2006.285.18:51:56.35#ibcon#*before write, iclass 13, count 2 2006.285.18:51:56.35#ibcon#enter sib2, iclass 13, count 2 2006.285.18:51:56.35#ibcon#flushed, iclass 13, count 2 2006.285.18:51:56.35#ibcon#about to write, iclass 13, count 2 2006.285.18:51:56.35#ibcon#wrote, iclass 13, count 2 2006.285.18:51:56.35#ibcon#about to read 3, iclass 13, count 2 2006.285.18:51:56.38#ibcon#read 3, iclass 13, count 2 2006.285.18:51:56.38#ibcon#about to read 4, iclass 13, count 2 2006.285.18:51:56.38#ibcon#read 4, iclass 13, count 2 2006.285.18:51:56.38#ibcon#about to read 5, iclass 13, count 2 2006.285.18:51:56.38#ibcon#read 5, iclass 13, count 2 2006.285.18:51:56.38#ibcon#about to read 6, iclass 13, count 2 2006.285.18:51:56.38#ibcon#read 6, iclass 13, count 2 2006.285.18:51:56.38#ibcon#end of sib2, iclass 13, count 2 2006.285.18:51:56.38#ibcon#*after write, iclass 13, count 2 2006.285.18:51:56.38#ibcon#*before return 0, iclass 13, count 2 2006.285.18:51:56.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:51:56.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.18:51:56.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.18:51:56.38#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:56.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:51:56.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:51:56.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:51:56.50#ibcon#enter wrdev, iclass 13, count 0 2006.285.18:51:56.50#ibcon#first serial, iclass 13, count 0 2006.285.18:51:56.50#ibcon#enter sib2, iclass 13, count 0 2006.285.18:51:56.50#ibcon#flushed, iclass 13, count 0 2006.285.18:51:56.50#ibcon#about to write, iclass 13, count 0 2006.285.18:51:56.50#ibcon#wrote, iclass 13, count 0 2006.285.18:51:56.50#ibcon#about to read 3, iclass 13, count 0 2006.285.18:51:56.52#ibcon#read 3, iclass 13, count 0 2006.285.18:51:56.52#ibcon#about to read 4, iclass 13, count 0 2006.285.18:51:56.52#ibcon#read 4, iclass 13, count 0 2006.285.18:51:56.52#ibcon#about to read 5, iclass 13, count 0 2006.285.18:51:56.52#ibcon#read 5, iclass 13, count 0 2006.285.18:51:56.52#ibcon#about to read 6, iclass 13, count 0 2006.285.18:51:56.52#ibcon#read 6, iclass 13, count 0 2006.285.18:51:56.52#ibcon#end of sib2, iclass 13, count 0 2006.285.18:51:56.52#ibcon#*mode == 0, iclass 13, count 0 2006.285.18:51:56.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.18:51:56.52#ibcon#[27=USB\r\n] 2006.285.18:51:56.52#ibcon#*before write, iclass 13, count 0 2006.285.18:51:56.52#ibcon#enter sib2, iclass 13, count 0 2006.285.18:51:56.52#ibcon#flushed, iclass 13, count 0 2006.285.18:51:56.52#ibcon#about to write, iclass 13, count 0 2006.285.18:51:56.52#ibcon#wrote, iclass 13, count 0 2006.285.18:51:56.52#ibcon#about to read 3, iclass 13, count 0 2006.285.18:51:56.55#ibcon#read 3, iclass 13, count 0 2006.285.18:51:56.55#ibcon#about to read 4, iclass 13, count 0 2006.285.18:51:56.55#ibcon#read 4, iclass 13, count 0 2006.285.18:51:56.55#ibcon#about to read 5, iclass 13, count 0 2006.285.18:51:56.55#ibcon#read 5, iclass 13, count 0 2006.285.18:51:56.55#ibcon#about to read 6, iclass 13, count 0 2006.285.18:51:56.55#ibcon#read 6, iclass 13, count 0 2006.285.18:51:56.55#ibcon#end of sib2, iclass 13, count 0 2006.285.18:51:56.55#ibcon#*after write, iclass 13, count 0 2006.285.18:51:56.55#ibcon#*before return 0, iclass 13, count 0 2006.285.18:51:56.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:51:56.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.18:51:56.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.18:51:56.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.18:51:56.55$vck44/vblo=8,744.99 2006.285.18:51:56.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.18:51:56.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.18:51:56.55#ibcon#ireg 17 cls_cnt 0 2006.285.18:51:56.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:51:56.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:51:56.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:51:56.55#ibcon#enter wrdev, iclass 15, count 0 2006.285.18:51:56.55#ibcon#first serial, iclass 15, count 0 2006.285.18:51:56.55#ibcon#enter sib2, iclass 15, count 0 2006.285.18:51:56.55#ibcon#flushed, iclass 15, count 0 2006.285.18:51:56.55#ibcon#about to write, iclass 15, count 0 2006.285.18:51:56.55#ibcon#wrote, iclass 15, count 0 2006.285.18:51:56.55#ibcon#about to read 3, iclass 15, count 0 2006.285.18:51:56.57#ibcon#read 3, iclass 15, count 0 2006.285.18:51:56.57#ibcon#about to read 4, iclass 15, count 0 2006.285.18:51:56.57#ibcon#read 4, iclass 15, count 0 2006.285.18:51:56.57#ibcon#about to read 5, iclass 15, count 0 2006.285.18:51:56.57#ibcon#read 5, iclass 15, count 0 2006.285.18:51:56.57#ibcon#about to read 6, iclass 15, count 0 2006.285.18:51:56.57#ibcon#read 6, iclass 15, count 0 2006.285.18:51:56.57#ibcon#end of sib2, iclass 15, count 0 2006.285.18:51:56.57#ibcon#*mode == 0, iclass 15, count 0 2006.285.18:51:56.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.18:51:56.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.18:51:56.57#ibcon#*before write, iclass 15, count 0 2006.285.18:51:56.57#ibcon#enter sib2, iclass 15, count 0 2006.285.18:51:56.57#ibcon#flushed, iclass 15, count 0 2006.285.18:51:56.57#ibcon#about to write, iclass 15, count 0 2006.285.18:51:56.57#ibcon#wrote, iclass 15, count 0 2006.285.18:51:56.57#ibcon#about to read 3, iclass 15, count 0 2006.285.18:51:56.61#ibcon#read 3, iclass 15, count 0 2006.285.18:51:56.61#ibcon#about to read 4, iclass 15, count 0 2006.285.18:51:56.61#ibcon#read 4, iclass 15, count 0 2006.285.18:51:56.61#ibcon#about to read 5, iclass 15, count 0 2006.285.18:51:56.61#ibcon#read 5, iclass 15, count 0 2006.285.18:51:56.61#ibcon#about to read 6, iclass 15, count 0 2006.285.18:51:56.61#ibcon#read 6, iclass 15, count 0 2006.285.18:51:56.61#ibcon#end of sib2, iclass 15, count 0 2006.285.18:51:56.61#ibcon#*after write, iclass 15, count 0 2006.285.18:51:56.61#ibcon#*before return 0, iclass 15, count 0 2006.285.18:51:56.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:51:56.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.18:51:56.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.18:51:56.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.18:51:56.61$vck44/vb=8,4 2006.285.18:51:56.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.18:51:56.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.18:51:56.65#ibcon#ireg 11 cls_cnt 2 2006.285.18:51:56.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:51:56.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:51:56.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:51:56.67#ibcon#enter wrdev, iclass 17, count 2 2006.285.18:51:56.67#ibcon#first serial, iclass 17, count 2 2006.285.18:51:56.67#ibcon#enter sib2, iclass 17, count 2 2006.285.18:51:56.67#ibcon#flushed, iclass 17, count 2 2006.285.18:51:56.67#ibcon#about to write, iclass 17, count 2 2006.285.18:51:56.67#ibcon#wrote, iclass 17, count 2 2006.285.18:51:56.67#ibcon#about to read 3, iclass 17, count 2 2006.285.18:51:56.69#ibcon#read 3, iclass 17, count 2 2006.285.18:51:56.69#ibcon#about to read 4, iclass 17, count 2 2006.285.18:51:56.69#ibcon#read 4, iclass 17, count 2 2006.285.18:51:56.69#ibcon#about to read 5, iclass 17, count 2 2006.285.18:51:56.69#ibcon#read 5, iclass 17, count 2 2006.285.18:51:56.69#ibcon#about to read 6, iclass 17, count 2 2006.285.18:51:56.69#ibcon#read 6, iclass 17, count 2 2006.285.18:51:56.69#ibcon#end of sib2, iclass 17, count 2 2006.285.18:51:56.69#ibcon#*mode == 0, iclass 17, count 2 2006.285.18:51:56.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.18:51:56.69#ibcon#[27=AT08-04\r\n] 2006.285.18:51:56.69#ibcon#*before write, iclass 17, count 2 2006.285.18:51:56.69#ibcon#enter sib2, iclass 17, count 2 2006.285.18:51:56.69#ibcon#flushed, iclass 17, count 2 2006.285.18:51:56.69#ibcon#about to write, iclass 17, count 2 2006.285.18:51:56.69#ibcon#wrote, iclass 17, count 2 2006.285.18:51:56.69#ibcon#about to read 3, iclass 17, count 2 2006.285.18:51:56.72#ibcon#read 3, iclass 17, count 2 2006.285.18:51:56.72#ibcon#about to read 4, iclass 17, count 2 2006.285.18:51:56.72#ibcon#read 4, iclass 17, count 2 2006.285.18:51:56.72#ibcon#about to read 5, iclass 17, count 2 2006.285.18:51:56.72#ibcon#read 5, iclass 17, count 2 2006.285.18:51:56.72#ibcon#about to read 6, iclass 17, count 2 2006.285.18:51:56.72#ibcon#read 6, iclass 17, count 2 2006.285.18:51:56.72#ibcon#end of sib2, iclass 17, count 2 2006.285.18:51:56.72#ibcon#*after write, iclass 17, count 2 2006.285.18:51:56.72#ibcon#*before return 0, iclass 17, count 2 2006.285.18:51:56.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:51:56.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.18:51:56.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.18:51:56.72#ibcon#ireg 7 cls_cnt 0 2006.285.18:51:56.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:51:56.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:51:56.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:51:56.84#ibcon#enter wrdev, iclass 17, count 0 2006.285.18:51:56.84#ibcon#first serial, iclass 17, count 0 2006.285.18:51:56.84#ibcon#enter sib2, iclass 17, count 0 2006.285.18:51:56.84#ibcon#flushed, iclass 17, count 0 2006.285.18:51:56.84#ibcon#about to write, iclass 17, count 0 2006.285.18:51:56.84#ibcon#wrote, iclass 17, count 0 2006.285.18:51:56.84#ibcon#about to read 3, iclass 17, count 0 2006.285.18:51:56.86#ibcon#read 3, iclass 17, count 0 2006.285.18:51:56.86#ibcon#about to read 4, iclass 17, count 0 2006.285.18:51:56.86#ibcon#read 4, iclass 17, count 0 2006.285.18:51:56.86#ibcon#about to read 5, iclass 17, count 0 2006.285.18:51:56.86#ibcon#read 5, iclass 17, count 0 2006.285.18:51:56.86#ibcon#about to read 6, iclass 17, count 0 2006.285.18:51:56.86#ibcon#read 6, iclass 17, count 0 2006.285.18:51:56.86#ibcon#end of sib2, iclass 17, count 0 2006.285.18:51:56.86#ibcon#*mode == 0, iclass 17, count 0 2006.285.18:51:56.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.18:51:56.86#ibcon#[27=USB\r\n] 2006.285.18:51:56.86#ibcon#*before write, iclass 17, count 0 2006.285.18:51:56.86#ibcon#enter sib2, iclass 17, count 0 2006.285.18:51:56.86#ibcon#flushed, iclass 17, count 0 2006.285.18:51:56.86#ibcon#about to write, iclass 17, count 0 2006.285.18:51:56.86#ibcon#wrote, iclass 17, count 0 2006.285.18:51:56.86#ibcon#about to read 3, iclass 17, count 0 2006.285.18:51:56.89#ibcon#read 3, iclass 17, count 0 2006.285.18:51:56.89#ibcon#about to read 4, iclass 17, count 0 2006.285.18:51:56.89#ibcon#read 4, iclass 17, count 0 2006.285.18:51:56.89#ibcon#about to read 5, iclass 17, count 0 2006.285.18:51:56.89#ibcon#read 5, iclass 17, count 0 2006.285.18:51:56.89#ibcon#about to read 6, iclass 17, count 0 2006.285.18:51:56.89#ibcon#read 6, iclass 17, count 0 2006.285.18:51:56.89#ibcon#end of sib2, iclass 17, count 0 2006.285.18:51:56.89#ibcon#*after write, iclass 17, count 0 2006.285.18:51:56.89#ibcon#*before return 0, iclass 17, count 0 2006.285.18:51:56.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:51:56.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.18:51:56.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.18:51:56.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.18:51:56.89$vck44/vabw=wide 2006.285.18:51:56.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.18:51:56.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.18:51:56.89#ibcon#ireg 8 cls_cnt 0 2006.285.18:51:56.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:51:56.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:51:56.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:51:56.89#ibcon#enter wrdev, iclass 19, count 0 2006.285.18:51:56.89#ibcon#first serial, iclass 19, count 0 2006.285.18:51:56.89#ibcon#enter sib2, iclass 19, count 0 2006.285.18:51:56.89#ibcon#flushed, iclass 19, count 0 2006.285.18:51:56.89#ibcon#about to write, iclass 19, count 0 2006.285.18:51:56.89#ibcon#wrote, iclass 19, count 0 2006.285.18:51:56.89#ibcon#about to read 3, iclass 19, count 0 2006.285.18:51:56.91#ibcon#read 3, iclass 19, count 0 2006.285.18:51:56.91#ibcon#about to read 4, iclass 19, count 0 2006.285.18:51:56.91#ibcon#read 4, iclass 19, count 0 2006.285.18:51:56.91#ibcon#about to read 5, iclass 19, count 0 2006.285.18:51:56.91#ibcon#read 5, iclass 19, count 0 2006.285.18:51:56.91#ibcon#about to read 6, iclass 19, count 0 2006.285.18:51:56.91#ibcon#read 6, iclass 19, count 0 2006.285.18:51:56.91#ibcon#end of sib2, iclass 19, count 0 2006.285.18:51:56.91#ibcon#*mode == 0, iclass 19, count 0 2006.285.18:51:56.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.18:51:56.91#ibcon#[25=BW32\r\n] 2006.285.18:51:56.91#ibcon#*before write, iclass 19, count 0 2006.285.18:51:56.91#ibcon#enter sib2, iclass 19, count 0 2006.285.18:51:56.91#ibcon#flushed, iclass 19, count 0 2006.285.18:51:56.91#ibcon#about to write, iclass 19, count 0 2006.285.18:51:56.91#ibcon#wrote, iclass 19, count 0 2006.285.18:51:56.91#ibcon#about to read 3, iclass 19, count 0 2006.285.18:51:56.94#ibcon#read 3, iclass 19, count 0 2006.285.18:51:56.94#ibcon#about to read 4, iclass 19, count 0 2006.285.18:51:56.94#ibcon#read 4, iclass 19, count 0 2006.285.18:51:56.94#ibcon#about to read 5, iclass 19, count 0 2006.285.18:51:56.94#ibcon#read 5, iclass 19, count 0 2006.285.18:51:56.94#ibcon#about to read 6, iclass 19, count 0 2006.285.18:51:56.94#ibcon#read 6, iclass 19, count 0 2006.285.18:51:56.94#ibcon#end of sib2, iclass 19, count 0 2006.285.18:51:56.94#ibcon#*after write, iclass 19, count 0 2006.285.18:51:56.94#ibcon#*before return 0, iclass 19, count 0 2006.285.18:51:56.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:51:56.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.18:51:56.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.18:51:56.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.18:51:56.94$vck44/vbbw=wide 2006.285.18:51:56.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.18:51:56.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.18:51:56.94#ibcon#ireg 8 cls_cnt 0 2006.285.18:51:56.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.18:51:57.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.18:51:57.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.18:51:57.01#ibcon#enter wrdev, iclass 21, count 0 2006.285.18:51:57.01#ibcon#first serial, iclass 21, count 0 2006.285.18:51:57.01#ibcon#enter sib2, iclass 21, count 0 2006.285.18:51:57.01#ibcon#flushed, iclass 21, count 0 2006.285.18:51:57.01#ibcon#about to write, iclass 21, count 0 2006.285.18:51:57.01#ibcon#wrote, iclass 21, count 0 2006.285.18:51:57.01#ibcon#about to read 3, iclass 21, count 0 2006.285.18:51:57.03#ibcon#read 3, iclass 21, count 0 2006.285.18:51:57.03#ibcon#about to read 4, iclass 21, count 0 2006.285.18:51:57.03#ibcon#read 4, iclass 21, count 0 2006.285.18:51:57.03#ibcon#about to read 5, iclass 21, count 0 2006.285.18:51:57.03#ibcon#read 5, iclass 21, count 0 2006.285.18:51:57.03#ibcon#about to read 6, iclass 21, count 0 2006.285.18:51:57.03#ibcon#read 6, iclass 21, count 0 2006.285.18:51:57.03#ibcon#end of sib2, iclass 21, count 0 2006.285.18:51:57.03#ibcon#*mode == 0, iclass 21, count 0 2006.285.18:51:57.03#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.18:51:57.03#ibcon#[27=BW32\r\n] 2006.285.18:51:57.03#ibcon#*before write, iclass 21, count 0 2006.285.18:51:57.03#ibcon#enter sib2, iclass 21, count 0 2006.285.18:51:57.03#ibcon#flushed, iclass 21, count 0 2006.285.18:51:57.03#ibcon#about to write, iclass 21, count 0 2006.285.18:51:57.03#ibcon#wrote, iclass 21, count 0 2006.285.18:51:57.03#ibcon#about to read 3, iclass 21, count 0 2006.285.18:51:57.06#ibcon#read 3, iclass 21, count 0 2006.285.18:51:57.06#ibcon#about to read 4, iclass 21, count 0 2006.285.18:51:57.06#ibcon#read 4, iclass 21, count 0 2006.285.18:51:57.06#ibcon#about to read 5, iclass 21, count 0 2006.285.18:51:57.06#ibcon#read 5, iclass 21, count 0 2006.285.18:51:57.06#ibcon#about to read 6, iclass 21, count 0 2006.285.18:51:57.06#ibcon#read 6, iclass 21, count 0 2006.285.18:51:57.06#ibcon#end of sib2, iclass 21, count 0 2006.285.18:51:57.06#ibcon#*after write, iclass 21, count 0 2006.285.18:51:57.06#ibcon#*before return 0, iclass 21, count 0 2006.285.18:51:57.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.18:51:57.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.18:51:57.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.18:51:57.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.18:51:57.06$setupk4/ifdk4 2006.285.18:51:57.06$ifdk4/lo= 2006.285.18:51:57.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.18:51:57.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.18:51:57.06$ifdk4/patch= 2006.285.18:51:57.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.18:51:57.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.18:51:57.06$setupk4/!*+20s 2006.285.18:51:59.99#abcon#<5=/14 0.3 1.2 15.071001014.9\r\n> 2006.285.18:52:00.01#abcon#{5=INTERFACE CLEAR} 2006.285.18:52:00.07#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:52:10.16#abcon#<5=/14 0.3 1.2 15.071001014.9\r\n> 2006.285.18:52:10.18#abcon#{5=INTERFACE CLEAR} 2006.285.18:52:10.24#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:52:10.71$setupk4/"tpicd 2006.285.18:52:10.71$setupk4/echo=off 2006.285.18:52:10.71$setupk4/xlog=off 2006.285.18:52:10.71:!2006.285.18:55:55 2006.285.18:52:18.13#trakl#Source acquired 2006.285.18:52:18.13#flagr#flagr/antenna,acquired 2006.285.18:55:55.02:preob 2006.285.18:55:56.15/onsource/TRACKING 2006.285.18:55:56.15:!2006.285.18:56:05 2006.285.18:56:05.01:"tape 2006.285.18:56:05.01:"st=record 2006.285.18:56:05.02:data_valid=on 2006.285.18:56:05.02:midob 2006.285.18:56:06.15/onsource/TRACKING 2006.285.18:56:06.15/wx/15.09,1014.9,100 2006.285.18:56:06.38/cable/+6.5062E-03 2006.285.18:56:07.47/va/01,07,usb,yes,38,41 2006.285.18:56:07.47/va/02,06,usb,yes,38,39 2006.285.18:56:07.47/va/03,07,usb,yes,38,40 2006.285.18:56:07.47/va/04,06,usb,yes,40,41 2006.285.18:56:07.47/va/05,03,usb,yes,39,40 2006.285.18:56:07.47/va/06,04,usb,yes,35,35 2006.285.18:56:07.47/va/07,04,usb,yes,36,37 2006.285.18:56:07.47/va/08,03,usb,yes,37,45 2006.285.18:56:07.70/valo/01,524.99,yes,locked 2006.285.18:56:07.70/valo/02,534.99,yes,locked 2006.285.18:56:07.70/valo/03,564.99,yes,locked 2006.285.18:56:07.70/valo/04,624.99,yes,locked 2006.285.18:56:07.70/valo/05,734.99,yes,locked 2006.285.18:56:07.70/valo/06,814.99,yes,locked 2006.285.18:56:07.70/valo/07,864.99,yes,locked 2006.285.18:56:07.70/valo/08,884.99,yes,locked 2006.285.18:56:08.79/vb/01,04,usb,yes,33,31 2006.285.18:56:08.79/vb/02,05,usb,yes,32,31 2006.285.18:56:08.79/vb/03,04,usb,yes,33,36 2006.285.18:56:08.79/vb/04,05,usb,yes,33,32 2006.285.18:56:08.79/vb/05,04,usb,yes,29,32 2006.285.18:56:08.79/vb/06,03,usb,yes,42,37 2006.285.18:56:08.79/vb/07,04,usb,yes,34,34 2006.285.18:56:08.79/vb/08,04,usb,yes,31,35 2006.285.18:56:09.02/vblo/01,629.99,yes,locked 2006.285.18:56:09.02/vblo/02,634.99,yes,locked 2006.285.18:56:09.02/vblo/03,649.99,yes,locked 2006.285.18:56:09.02/vblo/04,679.99,yes,locked 2006.285.18:56:09.02/vblo/05,709.99,yes,locked 2006.285.18:56:09.02/vblo/06,719.99,yes,locked 2006.285.18:56:09.02/vblo/07,734.99,yes,locked 2006.285.18:56:09.02/vblo/08,744.99,yes,locked 2006.285.18:56:09.17/vabw/8 2006.285.18:56:09.32/vbbw/8 2006.285.18:56:09.47/xfe/off,on,12.0 2006.285.18:56:09.84/ifatt/23,28,28,28 2006.285.18:56:10.07/fmout-gps/S +2.59E-07 2006.285.18:56:10.10:!2006.285.18:56:45 2006.285.18:56:45.02:data_valid=off 2006.285.18:56:45.02:"et 2006.285.18:56:45.02:!+3s 2006.285.18:56:48.04:"tape 2006.285.18:56:48.04:postob 2006.285.18:56:48.18/cable/+6.5062E-03 2006.285.18:56:48.19/wx/15.10,1014.9,100 2006.285.18:56:48.24/fmout-gps/S +2.59E-07 2006.285.18:56:48.25:scan_name=285-1904,jd0610,110 2006.285.18:56:48.25:source=0059+581,010245.76,582411.1,2000.0,cw 2006.285.18:56:49.15#flagr#flagr/antenna,new-source 2006.285.18:56:49.15:checkk5 2006.285.18:56:49.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.18:56:49.99/chk_autoobs//k5ts2/ autoobs is running! 2006.285.18:56:50.38/chk_autoobs//k5ts3/ autoobs is running! 2006.285.18:56:50.81/chk_autoobs//k5ts4/ autoobs is running! 2006.285.18:56:51.46/chk_obsdata//k5ts1/T2851856??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.18:56:51.88/chk_obsdata//k5ts2/T2851856??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.18:56:52.22/chk_obsdata//k5ts3/T2851856??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.18:56:52.74/chk_obsdata//k5ts4/T2851856??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.18:56:53.76/k5log//k5ts1_log_newline 2006.285.18:56:54.85/k5log//k5ts2_log_newline 2006.285.18:56:55.69/k5log//k5ts3_log_newline 2006.285.18:56:56.38/k5log//k5ts4_log_newline 2006.285.18:56:56.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.18:56:56.40:setupk4=1 2006.285.18:56:56.40$setupk4/echo=on 2006.285.18:56:56.40$setupk4/pcalon 2006.285.18:56:56.40$pcalon/"no phase cal control is implemented here 2006.285.18:56:56.40$setupk4/"tpicd=stop 2006.285.18:56:56.40$setupk4/"rec=synch_on 2006.285.18:56:56.40$setupk4/"rec_mode=128 2006.285.18:56:56.40$setupk4/!* 2006.285.18:56:56.40$setupk4/recpk4 2006.285.18:56:56.40$recpk4/recpatch= 2006.285.18:56:56.40$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.18:56:56.40$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.18:56:56.41$setupk4/vck44 2006.285.18:56:56.41$vck44/valo=1,524.99 2006.285.18:56:56.41#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.18:56:56.41#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.18:56:56.41#ibcon#ireg 17 cls_cnt 0 2006.285.18:56:56.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:56:56.41#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:56:56.41#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:56:56.41#ibcon#enter wrdev, iclass 38, count 0 2006.285.18:56:56.41#ibcon#first serial, iclass 38, count 0 2006.285.18:56:56.41#ibcon#enter sib2, iclass 38, count 0 2006.285.18:56:56.41#ibcon#flushed, iclass 38, count 0 2006.285.18:56:56.41#ibcon#about to write, iclass 38, count 0 2006.285.18:56:56.41#ibcon#wrote, iclass 38, count 0 2006.285.18:56:56.41#ibcon#about to read 3, iclass 38, count 0 2006.285.18:56:56.42#ibcon#read 3, iclass 38, count 0 2006.285.18:56:56.42#ibcon#about to read 4, iclass 38, count 0 2006.285.18:56:56.42#ibcon#read 4, iclass 38, count 0 2006.285.18:56:56.42#ibcon#about to read 5, iclass 38, count 0 2006.285.18:56:56.42#ibcon#read 5, iclass 38, count 0 2006.285.18:56:56.42#ibcon#about to read 6, iclass 38, count 0 2006.285.18:56:56.42#ibcon#read 6, iclass 38, count 0 2006.285.18:56:56.42#ibcon#end of sib2, iclass 38, count 0 2006.285.18:56:56.42#ibcon#*mode == 0, iclass 38, count 0 2006.285.18:56:56.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.18:56:56.42#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.18:56:56.42#ibcon#*before write, iclass 38, count 0 2006.285.18:56:56.42#ibcon#enter sib2, iclass 38, count 0 2006.285.18:56:56.42#ibcon#flushed, iclass 38, count 0 2006.285.18:56:56.42#ibcon#about to write, iclass 38, count 0 2006.285.18:56:56.42#ibcon#wrote, iclass 38, count 0 2006.285.18:56:56.42#ibcon#about to read 3, iclass 38, count 0 2006.285.18:56:56.47#ibcon#read 3, iclass 38, count 0 2006.285.18:56:56.47#ibcon#about to read 4, iclass 38, count 0 2006.285.18:56:56.47#ibcon#read 4, iclass 38, count 0 2006.285.18:56:56.47#ibcon#about to read 5, iclass 38, count 0 2006.285.18:56:56.47#ibcon#read 5, iclass 38, count 0 2006.285.18:56:56.47#ibcon#about to read 6, iclass 38, count 0 2006.285.18:56:56.47#ibcon#read 6, iclass 38, count 0 2006.285.18:56:56.47#ibcon#end of sib2, iclass 38, count 0 2006.285.18:56:56.47#ibcon#*after write, iclass 38, count 0 2006.285.18:56:56.47#ibcon#*before return 0, iclass 38, count 0 2006.285.18:56:56.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:56:56.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:56:56.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.18:56:56.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.18:56:56.47$vck44/va=1,7 2006.285.18:56:56.48#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.18:56:56.48#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.18:56:56.48#ibcon#ireg 11 cls_cnt 2 2006.285.18:56:56.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:56:56.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:56:56.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:56:56.48#ibcon#enter wrdev, iclass 40, count 2 2006.285.18:56:56.48#ibcon#first serial, iclass 40, count 2 2006.285.18:56:56.48#ibcon#enter sib2, iclass 40, count 2 2006.285.18:56:56.48#ibcon#flushed, iclass 40, count 2 2006.285.18:56:56.48#ibcon#about to write, iclass 40, count 2 2006.285.18:56:56.48#ibcon#wrote, iclass 40, count 2 2006.285.18:56:56.48#ibcon#about to read 3, iclass 40, count 2 2006.285.18:56:56.49#ibcon#read 3, iclass 40, count 2 2006.285.18:56:56.49#ibcon#about to read 4, iclass 40, count 2 2006.285.18:56:56.49#ibcon#read 4, iclass 40, count 2 2006.285.18:56:56.49#ibcon#about to read 5, iclass 40, count 2 2006.285.18:56:56.49#ibcon#read 5, iclass 40, count 2 2006.285.18:56:56.49#ibcon#about to read 6, iclass 40, count 2 2006.285.18:56:56.49#ibcon#read 6, iclass 40, count 2 2006.285.18:56:56.49#ibcon#end of sib2, iclass 40, count 2 2006.285.18:56:56.49#ibcon#*mode == 0, iclass 40, count 2 2006.285.18:56:56.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.18:56:56.49#ibcon#[25=AT01-07\r\n] 2006.285.18:56:56.49#ibcon#*before write, iclass 40, count 2 2006.285.18:56:56.49#ibcon#enter sib2, iclass 40, count 2 2006.285.18:56:56.49#ibcon#flushed, iclass 40, count 2 2006.285.18:56:56.49#ibcon#about to write, iclass 40, count 2 2006.285.18:56:56.49#ibcon#wrote, iclass 40, count 2 2006.285.18:56:56.49#ibcon#about to read 3, iclass 40, count 2 2006.285.18:56:56.52#ibcon#read 3, iclass 40, count 2 2006.285.18:56:56.52#ibcon#about to read 4, iclass 40, count 2 2006.285.18:56:56.52#ibcon#read 4, iclass 40, count 2 2006.285.18:56:56.52#ibcon#about to read 5, iclass 40, count 2 2006.285.18:56:56.52#ibcon#read 5, iclass 40, count 2 2006.285.18:56:56.52#ibcon#about to read 6, iclass 40, count 2 2006.285.18:56:56.52#ibcon#read 6, iclass 40, count 2 2006.285.18:56:56.52#ibcon#end of sib2, iclass 40, count 2 2006.285.18:56:56.52#ibcon#*after write, iclass 40, count 2 2006.285.18:56:56.52#ibcon#*before return 0, iclass 40, count 2 2006.285.18:56:56.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:56:56.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:56:56.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.18:56:56.52#ibcon#ireg 7 cls_cnt 0 2006.285.18:56:56.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:56:56.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:56:56.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:56:56.64#ibcon#enter wrdev, iclass 40, count 0 2006.285.18:56:56.64#ibcon#first serial, iclass 40, count 0 2006.285.18:56:56.64#ibcon#enter sib2, iclass 40, count 0 2006.285.18:56:56.64#ibcon#flushed, iclass 40, count 0 2006.285.18:56:56.64#ibcon#about to write, iclass 40, count 0 2006.285.18:56:56.64#ibcon#wrote, iclass 40, count 0 2006.285.18:56:56.64#ibcon#about to read 3, iclass 40, count 0 2006.285.18:56:56.66#ibcon#read 3, iclass 40, count 0 2006.285.18:56:56.66#ibcon#about to read 4, iclass 40, count 0 2006.285.18:56:56.66#ibcon#read 4, iclass 40, count 0 2006.285.18:56:56.66#ibcon#about to read 5, iclass 40, count 0 2006.285.18:56:56.66#ibcon#read 5, iclass 40, count 0 2006.285.18:56:56.66#ibcon#about to read 6, iclass 40, count 0 2006.285.18:56:56.66#ibcon#read 6, iclass 40, count 0 2006.285.18:56:56.66#ibcon#end of sib2, iclass 40, count 0 2006.285.18:56:56.66#ibcon#*mode == 0, iclass 40, count 0 2006.285.18:56:56.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.18:56:56.66#ibcon#[25=USB\r\n] 2006.285.18:56:56.66#ibcon#*before write, iclass 40, count 0 2006.285.18:56:56.66#ibcon#enter sib2, iclass 40, count 0 2006.285.18:56:56.66#ibcon#flushed, iclass 40, count 0 2006.285.18:56:56.66#ibcon#about to write, iclass 40, count 0 2006.285.18:56:56.66#ibcon#wrote, iclass 40, count 0 2006.285.18:56:56.66#ibcon#about to read 3, iclass 40, count 0 2006.285.18:56:56.69#ibcon#read 3, iclass 40, count 0 2006.285.18:56:56.95#ibcon#about to read 4, iclass 40, count 0 2006.285.18:56:56.95#ibcon#read 4, iclass 40, count 0 2006.285.18:56:56.95#ibcon#about to read 5, iclass 40, count 0 2006.285.18:56:56.95#ibcon#read 5, iclass 40, count 0 2006.285.18:56:56.95#ibcon#about to read 6, iclass 40, count 0 2006.285.18:56:56.95#ibcon#read 6, iclass 40, count 0 2006.285.18:56:56.95#ibcon#end of sib2, iclass 40, count 0 2006.285.18:56:56.95#ibcon#*after write, iclass 40, count 0 2006.285.18:56:56.95#ibcon#*before return 0, iclass 40, count 0 2006.285.18:56:56.95#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:56:56.95#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:56:56.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.18:56:56.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.18:56:56.95$vck44/valo=2,534.99 2006.285.18:56:56.95#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.18:56:56.95#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.18:56:56.95#ibcon#ireg 17 cls_cnt 0 2006.285.18:56:56.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:56:56.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:56:56.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:56:56.95#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:56:56.95#ibcon#first serial, iclass 4, count 0 2006.285.18:56:56.95#ibcon#enter sib2, iclass 4, count 0 2006.285.18:56:56.95#ibcon#flushed, iclass 4, count 0 2006.285.18:56:56.95#ibcon#about to write, iclass 4, count 0 2006.285.18:56:56.95#ibcon#wrote, iclass 4, count 0 2006.285.18:56:56.95#ibcon#about to read 3, iclass 4, count 0 2006.285.18:56:56.96#ibcon#read 3, iclass 4, count 0 2006.285.18:56:56.96#ibcon#about to read 4, iclass 4, count 0 2006.285.18:56:56.96#ibcon#read 4, iclass 4, count 0 2006.285.18:56:56.96#ibcon#about to read 5, iclass 4, count 0 2006.285.18:56:56.96#ibcon#read 5, iclass 4, count 0 2006.285.18:56:56.96#ibcon#about to read 6, iclass 4, count 0 2006.285.18:56:56.96#ibcon#read 6, iclass 4, count 0 2006.285.18:56:56.96#ibcon#end of sib2, iclass 4, count 0 2006.285.18:56:56.96#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:56:56.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:56:56.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.18:56:56.96#ibcon#*before write, iclass 4, count 0 2006.285.18:56:56.96#ibcon#enter sib2, iclass 4, count 0 2006.285.18:56:56.96#ibcon#flushed, iclass 4, count 0 2006.285.18:56:56.96#ibcon#about to write, iclass 4, count 0 2006.285.18:56:56.96#ibcon#wrote, iclass 4, count 0 2006.285.18:56:56.96#ibcon#about to read 3, iclass 4, count 0 2006.285.18:56:57.00#ibcon#read 3, iclass 4, count 0 2006.285.18:56:57.00#ibcon#about to read 4, iclass 4, count 0 2006.285.18:56:57.00#ibcon#read 4, iclass 4, count 0 2006.285.18:56:57.00#ibcon#about to read 5, iclass 4, count 0 2006.285.18:56:57.00#ibcon#read 5, iclass 4, count 0 2006.285.18:56:57.00#ibcon#about to read 6, iclass 4, count 0 2006.285.18:56:57.00#ibcon#read 6, iclass 4, count 0 2006.285.18:56:57.00#ibcon#end of sib2, iclass 4, count 0 2006.285.18:56:57.00#ibcon#*after write, iclass 4, count 0 2006.285.18:56:57.00#ibcon#*before return 0, iclass 4, count 0 2006.285.18:56:57.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:56:57.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:56:57.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:56:57.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:56:57.00$vck44/va=2,6 2006.285.18:56:57.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.18:56:57.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.18:56:57.00#ibcon#ireg 11 cls_cnt 2 2006.285.18:56:57.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:56:57.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:56:57.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:56:57.07#ibcon#enter wrdev, iclass 6, count 2 2006.285.18:56:57.07#ibcon#first serial, iclass 6, count 2 2006.285.18:56:57.07#ibcon#enter sib2, iclass 6, count 2 2006.285.18:56:57.07#ibcon#flushed, iclass 6, count 2 2006.285.18:56:57.07#ibcon#about to write, iclass 6, count 2 2006.285.18:56:57.07#ibcon#wrote, iclass 6, count 2 2006.285.18:56:57.07#ibcon#about to read 3, iclass 6, count 2 2006.285.18:56:57.09#ibcon#read 3, iclass 6, count 2 2006.285.18:56:57.09#ibcon#about to read 4, iclass 6, count 2 2006.285.18:56:57.09#ibcon#read 4, iclass 6, count 2 2006.285.18:56:57.09#ibcon#about to read 5, iclass 6, count 2 2006.285.18:56:57.09#ibcon#read 5, iclass 6, count 2 2006.285.18:56:57.09#ibcon#about to read 6, iclass 6, count 2 2006.285.18:56:57.09#ibcon#read 6, iclass 6, count 2 2006.285.18:56:57.09#ibcon#end of sib2, iclass 6, count 2 2006.285.18:56:57.09#ibcon#*mode == 0, iclass 6, count 2 2006.285.18:56:57.09#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.18:56:57.09#ibcon#[25=AT02-06\r\n] 2006.285.18:56:57.09#ibcon#*before write, iclass 6, count 2 2006.285.18:56:57.09#ibcon#enter sib2, iclass 6, count 2 2006.285.18:56:57.09#ibcon#flushed, iclass 6, count 2 2006.285.18:56:57.09#ibcon#about to write, iclass 6, count 2 2006.285.18:56:57.09#ibcon#wrote, iclass 6, count 2 2006.285.18:56:57.09#ibcon#about to read 3, iclass 6, count 2 2006.285.18:56:57.12#ibcon#read 3, iclass 6, count 2 2006.285.18:56:57.12#ibcon#about to read 4, iclass 6, count 2 2006.285.18:56:57.12#ibcon#read 4, iclass 6, count 2 2006.285.18:56:57.12#ibcon#about to read 5, iclass 6, count 2 2006.285.18:56:57.12#ibcon#read 5, iclass 6, count 2 2006.285.18:56:57.12#ibcon#about to read 6, iclass 6, count 2 2006.285.18:56:57.12#ibcon#read 6, iclass 6, count 2 2006.285.18:56:57.12#ibcon#end of sib2, iclass 6, count 2 2006.285.18:56:57.12#ibcon#*after write, iclass 6, count 2 2006.285.18:56:57.12#ibcon#*before return 0, iclass 6, count 2 2006.285.18:56:57.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:56:57.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:56:57.12#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.18:56:57.12#ibcon#ireg 7 cls_cnt 0 2006.285.18:56:57.12#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:56:57.24#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:56:57.24#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:56:57.24#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:56:57.24#ibcon#first serial, iclass 6, count 0 2006.285.18:56:57.24#ibcon#enter sib2, iclass 6, count 0 2006.285.18:56:57.24#ibcon#flushed, iclass 6, count 0 2006.285.18:56:57.24#ibcon#about to write, iclass 6, count 0 2006.285.18:56:57.24#ibcon#wrote, iclass 6, count 0 2006.285.18:56:57.24#ibcon#about to read 3, iclass 6, count 0 2006.285.18:56:57.26#ibcon#read 3, iclass 6, count 0 2006.285.18:56:57.26#ibcon#about to read 4, iclass 6, count 0 2006.285.18:56:57.26#ibcon#read 4, iclass 6, count 0 2006.285.18:56:57.26#ibcon#about to read 5, iclass 6, count 0 2006.285.18:56:57.26#ibcon#read 5, iclass 6, count 0 2006.285.18:56:57.26#ibcon#about to read 6, iclass 6, count 0 2006.285.18:56:57.26#ibcon#read 6, iclass 6, count 0 2006.285.18:56:57.26#ibcon#end of sib2, iclass 6, count 0 2006.285.18:56:57.26#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:56:57.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:56:57.26#ibcon#[25=USB\r\n] 2006.285.18:56:57.26#ibcon#*before write, iclass 6, count 0 2006.285.18:56:57.26#ibcon#enter sib2, iclass 6, count 0 2006.285.18:56:57.26#ibcon#flushed, iclass 6, count 0 2006.285.18:56:57.26#ibcon#about to write, iclass 6, count 0 2006.285.18:56:57.26#ibcon#wrote, iclass 6, count 0 2006.285.18:56:57.26#ibcon#about to read 3, iclass 6, count 0 2006.285.18:56:57.29#ibcon#read 3, iclass 6, count 0 2006.285.18:56:57.29#ibcon#about to read 4, iclass 6, count 0 2006.285.18:56:57.29#ibcon#read 4, iclass 6, count 0 2006.285.18:56:57.29#ibcon#about to read 5, iclass 6, count 0 2006.285.18:56:57.29#ibcon#read 5, iclass 6, count 0 2006.285.18:56:57.29#ibcon#about to read 6, iclass 6, count 0 2006.285.18:56:57.29#ibcon#read 6, iclass 6, count 0 2006.285.18:56:57.29#ibcon#end of sib2, iclass 6, count 0 2006.285.18:56:57.29#ibcon#*after write, iclass 6, count 0 2006.285.18:56:57.29#ibcon#*before return 0, iclass 6, count 0 2006.285.18:56:57.29#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:56:57.29#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:56:57.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:56:57.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:56:57.29$vck44/valo=3,564.99 2006.285.18:56:57.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.18:56:57.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.18:56:57.30#ibcon#ireg 17 cls_cnt 0 2006.285.18:56:57.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:56:57.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:56:57.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:56:57.30#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:56:57.30#ibcon#first serial, iclass 10, count 0 2006.285.18:56:57.30#ibcon#enter sib2, iclass 10, count 0 2006.285.18:56:57.30#ibcon#flushed, iclass 10, count 0 2006.285.18:56:57.30#ibcon#about to write, iclass 10, count 0 2006.285.18:56:57.30#ibcon#wrote, iclass 10, count 0 2006.285.18:56:57.30#ibcon#about to read 3, iclass 10, count 0 2006.285.18:56:57.31#ibcon#read 3, iclass 10, count 0 2006.285.18:56:57.47#ibcon#about to read 4, iclass 10, count 0 2006.285.18:56:57.47#ibcon#read 4, iclass 10, count 0 2006.285.18:56:57.47#ibcon#about to read 5, iclass 10, count 0 2006.285.18:56:57.47#ibcon#read 5, iclass 10, count 0 2006.285.18:56:57.47#ibcon#about to read 6, iclass 10, count 0 2006.285.18:56:57.47#ibcon#read 6, iclass 10, count 0 2006.285.18:56:57.47#ibcon#end of sib2, iclass 10, count 0 2006.285.18:56:57.47#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:56:57.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:56:57.47#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.18:56:57.47#ibcon#*before write, iclass 10, count 0 2006.285.18:56:57.47#ibcon#enter sib2, iclass 10, count 0 2006.285.18:56:57.47#ibcon#flushed, iclass 10, count 0 2006.285.18:56:57.47#ibcon#about to write, iclass 10, count 0 2006.285.18:56:57.47#ibcon#wrote, iclass 10, count 0 2006.285.18:56:57.47#ibcon#about to read 3, iclass 10, count 0 2006.285.18:56:57.51#ibcon#read 3, iclass 10, count 0 2006.285.18:56:57.51#ibcon#about to read 4, iclass 10, count 0 2006.285.18:56:57.51#ibcon#read 4, iclass 10, count 0 2006.285.18:56:57.51#ibcon#about to read 5, iclass 10, count 0 2006.285.18:56:57.51#ibcon#read 5, iclass 10, count 0 2006.285.18:56:57.51#ibcon#about to read 6, iclass 10, count 0 2006.285.18:56:57.51#ibcon#read 6, iclass 10, count 0 2006.285.18:56:57.51#ibcon#end of sib2, iclass 10, count 0 2006.285.18:56:57.51#ibcon#*after write, iclass 10, count 0 2006.285.18:56:57.51#ibcon#*before return 0, iclass 10, count 0 2006.285.18:56:57.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:56:57.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:56:57.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:56:57.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:56:57.51$vck44/va=3,7 2006.285.18:56:57.51#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.18:56:57.51#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.18:56:57.51#ibcon#ireg 11 cls_cnt 2 2006.285.18:56:57.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:56:57.52#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:56:57.52#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:56:57.52#ibcon#enter wrdev, iclass 12, count 2 2006.285.18:56:57.52#ibcon#first serial, iclass 12, count 2 2006.285.18:56:57.52#ibcon#enter sib2, iclass 12, count 2 2006.285.18:56:57.52#ibcon#flushed, iclass 12, count 2 2006.285.18:56:57.52#ibcon#about to write, iclass 12, count 2 2006.285.18:56:57.52#ibcon#wrote, iclass 12, count 2 2006.285.18:56:57.52#ibcon#about to read 3, iclass 12, count 2 2006.285.18:56:57.53#ibcon#read 3, iclass 12, count 2 2006.285.18:56:57.53#ibcon#about to read 4, iclass 12, count 2 2006.285.18:56:57.53#ibcon#read 4, iclass 12, count 2 2006.285.18:56:57.53#ibcon#about to read 5, iclass 12, count 2 2006.285.18:56:57.53#ibcon#read 5, iclass 12, count 2 2006.285.18:56:57.53#ibcon#about to read 6, iclass 12, count 2 2006.285.18:56:57.53#ibcon#read 6, iclass 12, count 2 2006.285.18:56:57.53#ibcon#end of sib2, iclass 12, count 2 2006.285.18:56:57.53#ibcon#*mode == 0, iclass 12, count 2 2006.285.18:56:57.53#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.18:56:57.53#ibcon#[25=AT03-07\r\n] 2006.285.18:56:57.53#ibcon#*before write, iclass 12, count 2 2006.285.18:56:57.53#ibcon#enter sib2, iclass 12, count 2 2006.285.18:56:57.53#ibcon#flushed, iclass 12, count 2 2006.285.18:56:57.53#ibcon#about to write, iclass 12, count 2 2006.285.18:56:57.53#ibcon#wrote, iclass 12, count 2 2006.285.18:56:57.53#ibcon#about to read 3, iclass 12, count 2 2006.285.18:56:57.56#ibcon#read 3, iclass 12, count 2 2006.285.18:56:57.56#ibcon#about to read 4, iclass 12, count 2 2006.285.18:56:57.56#ibcon#read 4, iclass 12, count 2 2006.285.18:56:57.56#ibcon#about to read 5, iclass 12, count 2 2006.285.18:56:57.56#ibcon#read 5, iclass 12, count 2 2006.285.18:56:57.56#ibcon#about to read 6, iclass 12, count 2 2006.285.18:56:57.56#ibcon#read 6, iclass 12, count 2 2006.285.18:56:57.56#ibcon#end of sib2, iclass 12, count 2 2006.285.18:56:57.56#ibcon#*after write, iclass 12, count 2 2006.285.18:56:57.56#ibcon#*before return 0, iclass 12, count 2 2006.285.18:56:57.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:56:57.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:56:57.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.18:56:57.56#ibcon#ireg 7 cls_cnt 0 2006.285.18:56:57.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:56:57.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:56:57.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:56:57.68#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:56:57.68#ibcon#first serial, iclass 12, count 0 2006.285.18:56:57.68#ibcon#enter sib2, iclass 12, count 0 2006.285.18:56:57.68#ibcon#flushed, iclass 12, count 0 2006.285.18:56:57.68#ibcon#about to write, iclass 12, count 0 2006.285.18:56:57.68#ibcon#wrote, iclass 12, count 0 2006.285.18:56:57.68#ibcon#about to read 3, iclass 12, count 0 2006.285.18:56:57.70#ibcon#read 3, iclass 12, count 0 2006.285.18:56:57.70#ibcon#about to read 4, iclass 12, count 0 2006.285.18:56:57.70#ibcon#read 4, iclass 12, count 0 2006.285.18:56:57.70#ibcon#about to read 5, iclass 12, count 0 2006.285.18:56:57.70#ibcon#read 5, iclass 12, count 0 2006.285.18:56:57.70#ibcon#about to read 6, iclass 12, count 0 2006.285.18:56:57.70#ibcon#read 6, iclass 12, count 0 2006.285.18:56:57.70#ibcon#end of sib2, iclass 12, count 0 2006.285.18:56:57.70#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:56:57.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:56:57.70#ibcon#[25=USB\r\n] 2006.285.18:56:57.70#ibcon#*before write, iclass 12, count 0 2006.285.18:56:57.70#ibcon#enter sib2, iclass 12, count 0 2006.285.18:56:57.70#ibcon#flushed, iclass 12, count 0 2006.285.18:56:57.70#ibcon#about to write, iclass 12, count 0 2006.285.18:56:57.70#ibcon#wrote, iclass 12, count 0 2006.285.18:56:57.70#ibcon#about to read 3, iclass 12, count 0 2006.285.18:56:57.73#ibcon#read 3, iclass 12, count 0 2006.285.18:56:57.73#ibcon#about to read 4, iclass 12, count 0 2006.285.18:56:57.73#ibcon#read 4, iclass 12, count 0 2006.285.18:56:57.73#ibcon#about to read 5, iclass 12, count 0 2006.285.18:56:57.73#ibcon#read 5, iclass 12, count 0 2006.285.18:56:57.73#ibcon#about to read 6, iclass 12, count 0 2006.285.18:56:57.73#ibcon#read 6, iclass 12, count 0 2006.285.18:56:57.73#ibcon#end of sib2, iclass 12, count 0 2006.285.18:56:57.73#ibcon#*after write, iclass 12, count 0 2006.285.18:56:57.73#ibcon#*before return 0, iclass 12, count 0 2006.285.18:56:57.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:56:57.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:56:57.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:56:57.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:56:57.73$vck44/valo=4,624.99 2006.285.18:56:57.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.18:56:57.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.18:56:57.73#ibcon#ireg 17 cls_cnt 0 2006.285.18:56:57.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:56:57.74#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:56:57.74#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:56:57.74#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:56:57.74#ibcon#first serial, iclass 14, count 0 2006.285.18:56:57.74#ibcon#enter sib2, iclass 14, count 0 2006.285.18:56:57.74#ibcon#flushed, iclass 14, count 0 2006.285.18:56:57.74#ibcon#about to write, iclass 14, count 0 2006.285.18:56:57.74#ibcon#wrote, iclass 14, count 0 2006.285.18:56:57.74#ibcon#about to read 3, iclass 14, count 0 2006.285.18:56:57.75#ibcon#read 3, iclass 14, count 0 2006.285.18:56:57.75#ibcon#about to read 4, iclass 14, count 0 2006.285.18:56:57.75#ibcon#read 4, iclass 14, count 0 2006.285.18:56:57.75#ibcon#about to read 5, iclass 14, count 0 2006.285.18:56:57.75#ibcon#read 5, iclass 14, count 0 2006.285.18:56:57.75#ibcon#about to read 6, iclass 14, count 0 2006.285.18:56:57.75#ibcon#read 6, iclass 14, count 0 2006.285.18:56:57.75#ibcon#end of sib2, iclass 14, count 0 2006.285.18:56:57.75#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:56:57.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:56:57.75#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.18:56:57.75#ibcon#*before write, iclass 14, count 0 2006.285.18:56:57.75#ibcon#enter sib2, iclass 14, count 0 2006.285.18:56:57.75#ibcon#flushed, iclass 14, count 0 2006.285.18:56:57.75#ibcon#about to write, iclass 14, count 0 2006.285.18:56:57.75#ibcon#wrote, iclass 14, count 0 2006.285.18:56:57.75#ibcon#about to read 3, iclass 14, count 0 2006.285.18:56:57.79#ibcon#read 3, iclass 14, count 0 2006.285.18:56:57.79#ibcon#about to read 4, iclass 14, count 0 2006.285.18:56:57.79#ibcon#read 4, iclass 14, count 0 2006.285.18:56:57.79#ibcon#about to read 5, iclass 14, count 0 2006.285.18:56:57.79#ibcon#read 5, iclass 14, count 0 2006.285.18:56:57.79#ibcon#about to read 6, iclass 14, count 0 2006.285.18:56:57.79#ibcon#read 6, iclass 14, count 0 2006.285.18:56:57.79#ibcon#end of sib2, iclass 14, count 0 2006.285.18:56:57.79#ibcon#*after write, iclass 14, count 0 2006.285.18:56:57.79#ibcon#*before return 0, iclass 14, count 0 2006.285.18:56:57.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:56:57.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:56:57.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:56:57.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:56:57.79$vck44/va=4,6 2006.285.18:56:57.79#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.18:56:57.79#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.18:56:57.80#ibcon#ireg 11 cls_cnt 2 2006.285.18:56:57.80#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:56:57.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:56:57.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:56:57.84#ibcon#enter wrdev, iclass 16, count 2 2006.285.18:56:57.84#ibcon#first serial, iclass 16, count 2 2006.285.18:56:57.84#ibcon#enter sib2, iclass 16, count 2 2006.285.18:56:57.84#ibcon#flushed, iclass 16, count 2 2006.285.18:56:57.84#ibcon#about to write, iclass 16, count 2 2006.285.18:56:57.84#ibcon#wrote, iclass 16, count 2 2006.285.18:56:57.84#ibcon#about to read 3, iclass 16, count 2 2006.285.18:56:57.86#ibcon#read 3, iclass 16, count 2 2006.285.18:56:57.86#ibcon#about to read 4, iclass 16, count 2 2006.285.18:56:57.86#ibcon#read 4, iclass 16, count 2 2006.285.18:56:57.86#ibcon#about to read 5, iclass 16, count 2 2006.285.18:56:57.86#ibcon#read 5, iclass 16, count 2 2006.285.18:56:57.86#ibcon#about to read 6, iclass 16, count 2 2006.285.18:56:57.86#ibcon#read 6, iclass 16, count 2 2006.285.18:56:57.86#ibcon#end of sib2, iclass 16, count 2 2006.285.18:56:57.86#ibcon#*mode == 0, iclass 16, count 2 2006.285.18:56:57.86#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.18:56:57.86#ibcon#[25=AT04-06\r\n] 2006.285.18:56:57.86#ibcon#*before write, iclass 16, count 2 2006.285.18:56:57.86#ibcon#enter sib2, iclass 16, count 2 2006.285.18:56:57.86#ibcon#flushed, iclass 16, count 2 2006.285.18:56:57.86#ibcon#about to write, iclass 16, count 2 2006.285.18:56:57.86#ibcon#wrote, iclass 16, count 2 2006.285.18:56:57.86#ibcon#about to read 3, iclass 16, count 2 2006.285.18:56:57.89#ibcon#read 3, iclass 16, count 2 2006.285.18:56:57.89#ibcon#about to read 4, iclass 16, count 2 2006.285.18:56:57.89#ibcon#read 4, iclass 16, count 2 2006.285.18:56:57.89#ibcon#about to read 5, iclass 16, count 2 2006.285.18:56:57.89#ibcon#read 5, iclass 16, count 2 2006.285.18:56:57.89#ibcon#about to read 6, iclass 16, count 2 2006.285.18:56:57.89#ibcon#read 6, iclass 16, count 2 2006.285.18:56:57.89#ibcon#end of sib2, iclass 16, count 2 2006.285.18:56:57.89#ibcon#*after write, iclass 16, count 2 2006.285.18:56:57.89#ibcon#*before return 0, iclass 16, count 2 2006.285.18:56:57.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:56:57.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:56:57.89#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.18:56:57.89#ibcon#ireg 7 cls_cnt 0 2006.285.18:56:57.89#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:56:58.01#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:56:58.01#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:56:58.01#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:56:58.01#ibcon#first serial, iclass 16, count 0 2006.285.18:56:58.01#ibcon#enter sib2, iclass 16, count 0 2006.285.18:56:58.01#ibcon#flushed, iclass 16, count 0 2006.285.18:56:58.01#ibcon#about to write, iclass 16, count 0 2006.285.18:56:58.01#ibcon#wrote, iclass 16, count 0 2006.285.18:56:58.01#ibcon#about to read 3, iclass 16, count 0 2006.285.18:56:58.03#ibcon#read 3, iclass 16, count 0 2006.285.18:56:58.03#ibcon#about to read 4, iclass 16, count 0 2006.285.18:56:58.03#ibcon#read 4, iclass 16, count 0 2006.285.18:56:58.03#ibcon#about to read 5, iclass 16, count 0 2006.285.18:56:58.03#ibcon#read 5, iclass 16, count 0 2006.285.18:56:58.03#ibcon#about to read 6, iclass 16, count 0 2006.285.18:56:58.03#ibcon#read 6, iclass 16, count 0 2006.285.18:56:58.03#ibcon#end of sib2, iclass 16, count 0 2006.285.18:56:58.03#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:56:58.03#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:56:58.03#ibcon#[25=USB\r\n] 2006.285.18:56:58.03#ibcon#*before write, iclass 16, count 0 2006.285.18:56:58.03#ibcon#enter sib2, iclass 16, count 0 2006.285.18:56:58.03#ibcon#flushed, iclass 16, count 0 2006.285.18:56:58.03#ibcon#about to write, iclass 16, count 0 2006.285.18:56:58.03#ibcon#wrote, iclass 16, count 0 2006.285.18:56:58.03#ibcon#about to read 3, iclass 16, count 0 2006.285.18:56:58.06#ibcon#read 3, iclass 16, count 0 2006.285.18:56:58.06#ibcon#about to read 4, iclass 16, count 0 2006.285.18:56:58.06#ibcon#read 4, iclass 16, count 0 2006.285.18:56:58.06#ibcon#about to read 5, iclass 16, count 0 2006.285.18:56:58.06#ibcon#read 5, iclass 16, count 0 2006.285.18:56:58.06#ibcon#about to read 6, iclass 16, count 0 2006.285.18:56:58.06#ibcon#read 6, iclass 16, count 0 2006.285.18:56:58.06#ibcon#end of sib2, iclass 16, count 0 2006.285.18:56:58.06#ibcon#*after write, iclass 16, count 0 2006.285.18:56:58.06#ibcon#*before return 0, iclass 16, count 0 2006.285.18:56:58.06#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:56:58.06#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:56:58.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:56:58.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:56:58.06$vck44/valo=5,734.99 2006.285.18:56:58.06#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.18:56:58.06#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.18:56:58.06#ibcon#ireg 17 cls_cnt 0 2006.285.18:56:58.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:56:58.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:56:58.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:56:58.07#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:56:58.07#ibcon#first serial, iclass 18, count 0 2006.285.18:56:58.07#ibcon#enter sib2, iclass 18, count 0 2006.285.18:56:58.07#ibcon#flushed, iclass 18, count 0 2006.285.18:56:58.07#ibcon#about to write, iclass 18, count 0 2006.285.18:56:58.07#ibcon#wrote, iclass 18, count 0 2006.285.18:56:58.07#ibcon#about to read 3, iclass 18, count 0 2006.285.18:56:58.08#ibcon#read 3, iclass 18, count 0 2006.285.18:56:58.08#ibcon#about to read 4, iclass 18, count 0 2006.285.18:56:58.08#ibcon#read 4, iclass 18, count 0 2006.285.18:56:58.08#ibcon#about to read 5, iclass 18, count 0 2006.285.18:56:58.08#ibcon#read 5, iclass 18, count 0 2006.285.18:56:58.08#ibcon#about to read 6, iclass 18, count 0 2006.285.18:56:58.08#ibcon#read 6, iclass 18, count 0 2006.285.18:56:58.08#ibcon#end of sib2, iclass 18, count 0 2006.285.18:56:58.08#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:56:58.08#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:56:58.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.18:56:58.08#ibcon#*before write, iclass 18, count 0 2006.285.18:56:58.08#ibcon#enter sib2, iclass 18, count 0 2006.285.18:56:58.08#ibcon#flushed, iclass 18, count 0 2006.285.18:56:58.08#ibcon#about to write, iclass 18, count 0 2006.285.18:56:58.08#ibcon#wrote, iclass 18, count 0 2006.285.18:56:58.08#ibcon#about to read 3, iclass 18, count 0 2006.285.18:56:58.12#ibcon#read 3, iclass 18, count 0 2006.285.18:56:58.12#ibcon#about to read 4, iclass 18, count 0 2006.285.18:56:58.12#ibcon#read 4, iclass 18, count 0 2006.285.18:56:58.12#ibcon#about to read 5, iclass 18, count 0 2006.285.18:56:58.12#ibcon#read 5, iclass 18, count 0 2006.285.18:56:58.12#ibcon#about to read 6, iclass 18, count 0 2006.285.18:56:58.12#ibcon#read 6, iclass 18, count 0 2006.285.18:56:58.12#ibcon#end of sib2, iclass 18, count 0 2006.285.18:56:58.12#ibcon#*after write, iclass 18, count 0 2006.285.18:56:58.12#ibcon#*before return 0, iclass 18, count 0 2006.285.18:56:58.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:56:58.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:56:58.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:56:58.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:56:58.12$vck44/va=5,3 2006.285.18:56:58.12#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.18:56:58.12#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.18:56:58.12#ibcon#ireg 11 cls_cnt 2 2006.285.18:56:58.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:56:58.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:56:58.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:56:58.18#ibcon#enter wrdev, iclass 20, count 2 2006.285.18:56:58.18#ibcon#first serial, iclass 20, count 2 2006.285.18:56:58.18#ibcon#enter sib2, iclass 20, count 2 2006.285.18:56:58.18#ibcon#flushed, iclass 20, count 2 2006.285.18:56:58.18#ibcon#about to write, iclass 20, count 2 2006.285.18:56:58.18#ibcon#wrote, iclass 20, count 2 2006.285.18:56:58.18#ibcon#about to read 3, iclass 20, count 2 2006.285.18:56:58.20#ibcon#read 3, iclass 20, count 2 2006.285.18:56:58.20#ibcon#about to read 4, iclass 20, count 2 2006.285.18:56:58.20#ibcon#read 4, iclass 20, count 2 2006.285.18:56:58.20#ibcon#about to read 5, iclass 20, count 2 2006.285.18:56:58.20#ibcon#read 5, iclass 20, count 2 2006.285.18:56:58.20#ibcon#about to read 6, iclass 20, count 2 2006.285.18:56:58.20#ibcon#read 6, iclass 20, count 2 2006.285.18:56:58.20#ibcon#end of sib2, iclass 20, count 2 2006.285.18:56:58.20#ibcon#*mode == 0, iclass 20, count 2 2006.285.18:56:58.20#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.18:56:58.20#ibcon#[25=AT05-03\r\n] 2006.285.18:56:58.20#ibcon#*before write, iclass 20, count 2 2006.285.18:56:58.20#ibcon#enter sib2, iclass 20, count 2 2006.285.18:56:58.20#ibcon#flushed, iclass 20, count 2 2006.285.18:56:58.20#ibcon#about to write, iclass 20, count 2 2006.285.18:56:58.20#ibcon#wrote, iclass 20, count 2 2006.285.18:56:58.20#ibcon#about to read 3, iclass 20, count 2 2006.285.18:56:58.23#ibcon#read 3, iclass 20, count 2 2006.285.18:56:58.23#ibcon#about to read 4, iclass 20, count 2 2006.285.18:56:58.23#ibcon#read 4, iclass 20, count 2 2006.285.18:56:58.23#ibcon#about to read 5, iclass 20, count 2 2006.285.18:56:58.23#ibcon#read 5, iclass 20, count 2 2006.285.18:56:58.23#ibcon#about to read 6, iclass 20, count 2 2006.285.18:56:58.23#ibcon#read 6, iclass 20, count 2 2006.285.18:56:58.23#ibcon#end of sib2, iclass 20, count 2 2006.285.18:56:58.23#ibcon#*after write, iclass 20, count 2 2006.285.18:56:58.23#ibcon#*before return 0, iclass 20, count 2 2006.285.18:56:58.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:56:58.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:56:58.23#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.18:56:58.23#ibcon#ireg 7 cls_cnt 0 2006.285.18:56:58.23#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:56:58.35#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:56:58.35#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:56:58.35#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:56:58.35#ibcon#first serial, iclass 20, count 0 2006.285.18:56:58.35#ibcon#enter sib2, iclass 20, count 0 2006.285.18:56:58.35#ibcon#flushed, iclass 20, count 0 2006.285.18:56:58.35#ibcon#about to write, iclass 20, count 0 2006.285.18:56:58.35#ibcon#wrote, iclass 20, count 0 2006.285.18:56:58.35#ibcon#about to read 3, iclass 20, count 0 2006.285.18:56:58.37#ibcon#read 3, iclass 20, count 0 2006.285.18:56:58.37#ibcon#about to read 4, iclass 20, count 0 2006.285.18:56:58.37#ibcon#read 4, iclass 20, count 0 2006.285.18:56:58.37#ibcon#about to read 5, iclass 20, count 0 2006.285.18:56:58.37#ibcon#read 5, iclass 20, count 0 2006.285.18:56:58.37#ibcon#about to read 6, iclass 20, count 0 2006.285.18:56:58.37#ibcon#read 6, iclass 20, count 0 2006.285.18:56:58.37#ibcon#end of sib2, iclass 20, count 0 2006.285.18:56:58.37#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:56:58.37#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:56:58.37#ibcon#[25=USB\r\n] 2006.285.18:56:58.37#ibcon#*before write, iclass 20, count 0 2006.285.18:56:58.37#ibcon#enter sib2, iclass 20, count 0 2006.285.18:56:58.37#ibcon#flushed, iclass 20, count 0 2006.285.18:56:58.37#ibcon#about to write, iclass 20, count 0 2006.285.18:56:58.37#ibcon#wrote, iclass 20, count 0 2006.285.18:56:58.37#ibcon#about to read 3, iclass 20, count 0 2006.285.18:56:58.40#ibcon#read 3, iclass 20, count 0 2006.285.18:56:58.40#ibcon#about to read 4, iclass 20, count 0 2006.285.18:56:58.40#ibcon#read 4, iclass 20, count 0 2006.285.18:56:58.40#ibcon#about to read 5, iclass 20, count 0 2006.285.18:56:58.40#ibcon#read 5, iclass 20, count 0 2006.285.18:56:58.40#ibcon#about to read 6, iclass 20, count 0 2006.285.18:56:58.40#ibcon#read 6, iclass 20, count 0 2006.285.18:56:58.40#ibcon#end of sib2, iclass 20, count 0 2006.285.18:56:58.40#ibcon#*after write, iclass 20, count 0 2006.285.18:56:58.40#ibcon#*before return 0, iclass 20, count 0 2006.285.18:56:58.40#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:56:58.40#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:56:58.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:56:58.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:56:58.40$vck44/valo=6,814.99 2006.285.18:56:58.40#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.18:56:58.40#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.18:56:58.40#ibcon#ireg 17 cls_cnt 0 2006.285.18:56:58.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:56:58.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:56:58.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:56:58.41#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:56:58.41#ibcon#first serial, iclass 22, count 0 2006.285.18:56:58.41#ibcon#enter sib2, iclass 22, count 0 2006.285.18:56:58.41#ibcon#flushed, iclass 22, count 0 2006.285.18:56:58.41#ibcon#about to write, iclass 22, count 0 2006.285.18:56:58.41#ibcon#wrote, iclass 22, count 0 2006.285.18:56:58.41#ibcon#about to read 3, iclass 22, count 0 2006.285.18:56:58.42#ibcon#read 3, iclass 22, count 0 2006.285.18:56:58.42#ibcon#about to read 4, iclass 22, count 0 2006.285.18:56:58.42#ibcon#read 4, iclass 22, count 0 2006.285.18:56:58.42#ibcon#about to read 5, iclass 22, count 0 2006.285.18:56:58.42#ibcon#read 5, iclass 22, count 0 2006.285.18:56:58.42#ibcon#about to read 6, iclass 22, count 0 2006.285.18:56:58.42#ibcon#read 6, iclass 22, count 0 2006.285.18:56:58.42#ibcon#end of sib2, iclass 22, count 0 2006.285.18:56:58.42#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:56:58.42#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:56:58.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.18:56:58.42#ibcon#*before write, iclass 22, count 0 2006.285.18:56:58.42#ibcon#enter sib2, iclass 22, count 0 2006.285.18:56:58.42#ibcon#flushed, iclass 22, count 0 2006.285.18:56:58.42#ibcon#about to write, iclass 22, count 0 2006.285.18:56:58.42#ibcon#wrote, iclass 22, count 0 2006.285.18:56:58.42#ibcon#about to read 3, iclass 22, count 0 2006.285.18:56:58.46#ibcon#read 3, iclass 22, count 0 2006.285.18:56:58.46#ibcon#about to read 4, iclass 22, count 0 2006.285.18:56:58.46#ibcon#read 4, iclass 22, count 0 2006.285.18:56:58.46#ibcon#about to read 5, iclass 22, count 0 2006.285.18:56:58.46#ibcon#read 5, iclass 22, count 0 2006.285.18:56:58.46#ibcon#about to read 6, iclass 22, count 0 2006.285.18:56:58.46#ibcon#read 6, iclass 22, count 0 2006.285.18:56:58.46#ibcon#end of sib2, iclass 22, count 0 2006.285.18:56:58.46#ibcon#*after write, iclass 22, count 0 2006.285.18:56:58.46#ibcon#*before return 0, iclass 22, count 0 2006.285.18:56:58.46#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:56:58.46#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:56:58.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:56:58.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:56:58.46$vck44/va=6,4 2006.285.18:56:58.46#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.18:56:58.46#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.18:56:58.46#ibcon#ireg 11 cls_cnt 2 2006.285.18:56:58.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:56:58.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:56:58.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:56:58.52#ibcon#enter wrdev, iclass 24, count 2 2006.285.18:56:58.52#ibcon#first serial, iclass 24, count 2 2006.285.18:56:58.52#ibcon#enter sib2, iclass 24, count 2 2006.285.18:56:58.52#ibcon#flushed, iclass 24, count 2 2006.285.18:56:58.52#ibcon#about to write, iclass 24, count 2 2006.285.18:56:58.52#ibcon#wrote, iclass 24, count 2 2006.285.18:56:58.52#ibcon#about to read 3, iclass 24, count 2 2006.285.18:56:58.54#ibcon#read 3, iclass 24, count 2 2006.285.18:56:58.54#ibcon#about to read 4, iclass 24, count 2 2006.285.18:56:58.54#ibcon#read 4, iclass 24, count 2 2006.285.18:56:58.54#ibcon#about to read 5, iclass 24, count 2 2006.285.18:56:58.54#ibcon#read 5, iclass 24, count 2 2006.285.18:56:58.54#ibcon#about to read 6, iclass 24, count 2 2006.285.18:56:58.54#ibcon#read 6, iclass 24, count 2 2006.285.18:56:58.54#ibcon#end of sib2, iclass 24, count 2 2006.285.18:56:58.54#ibcon#*mode == 0, iclass 24, count 2 2006.285.18:56:58.54#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.18:56:58.54#ibcon#[25=AT06-04\r\n] 2006.285.18:56:58.54#ibcon#*before write, iclass 24, count 2 2006.285.18:56:58.54#ibcon#enter sib2, iclass 24, count 2 2006.285.18:56:58.54#ibcon#flushed, iclass 24, count 2 2006.285.18:56:58.54#ibcon#about to write, iclass 24, count 2 2006.285.18:56:58.54#ibcon#wrote, iclass 24, count 2 2006.285.18:56:58.54#ibcon#about to read 3, iclass 24, count 2 2006.285.18:56:58.57#ibcon#read 3, iclass 24, count 2 2006.285.18:56:58.57#ibcon#about to read 4, iclass 24, count 2 2006.285.18:56:58.57#ibcon#read 4, iclass 24, count 2 2006.285.18:56:58.57#ibcon#about to read 5, iclass 24, count 2 2006.285.18:56:58.57#ibcon#read 5, iclass 24, count 2 2006.285.18:56:58.57#ibcon#about to read 6, iclass 24, count 2 2006.285.18:56:58.57#ibcon#read 6, iclass 24, count 2 2006.285.18:56:58.57#ibcon#end of sib2, iclass 24, count 2 2006.285.18:56:58.57#ibcon#*after write, iclass 24, count 2 2006.285.18:56:58.57#ibcon#*before return 0, iclass 24, count 2 2006.285.18:56:58.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:56:58.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:56:58.57#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.18:56:58.57#ibcon#ireg 7 cls_cnt 0 2006.285.18:56:58.57#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:56:58.69#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:56:58.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:56:58.84#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:56:58.84#ibcon#first serial, iclass 24, count 0 2006.285.18:56:58.84#ibcon#enter sib2, iclass 24, count 0 2006.285.18:56:58.84#ibcon#flushed, iclass 24, count 0 2006.285.18:56:58.84#ibcon#about to write, iclass 24, count 0 2006.285.18:56:58.84#ibcon#wrote, iclass 24, count 0 2006.285.18:56:58.84#ibcon#about to read 3, iclass 24, count 0 2006.285.18:56:58.85#ibcon#read 3, iclass 24, count 0 2006.285.18:56:58.85#ibcon#about to read 4, iclass 24, count 0 2006.285.18:56:58.85#ibcon#read 4, iclass 24, count 0 2006.285.18:56:58.85#ibcon#about to read 5, iclass 24, count 0 2006.285.18:56:58.85#ibcon#read 5, iclass 24, count 0 2006.285.18:56:58.85#ibcon#about to read 6, iclass 24, count 0 2006.285.18:56:58.85#ibcon#read 6, iclass 24, count 0 2006.285.18:56:58.85#ibcon#end of sib2, iclass 24, count 0 2006.285.18:56:58.85#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:56:58.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:56:58.85#ibcon#[25=USB\r\n] 2006.285.18:56:58.85#ibcon#*before write, iclass 24, count 0 2006.285.18:56:58.85#ibcon#enter sib2, iclass 24, count 0 2006.285.18:56:58.85#ibcon#flushed, iclass 24, count 0 2006.285.18:56:58.85#ibcon#about to write, iclass 24, count 0 2006.285.18:56:58.85#ibcon#wrote, iclass 24, count 0 2006.285.18:56:58.85#ibcon#about to read 3, iclass 24, count 0 2006.285.18:56:58.88#ibcon#read 3, iclass 24, count 0 2006.285.18:56:58.88#ibcon#about to read 4, iclass 24, count 0 2006.285.18:56:58.88#ibcon#read 4, iclass 24, count 0 2006.285.18:56:58.88#ibcon#about to read 5, iclass 24, count 0 2006.285.18:56:58.88#ibcon#read 5, iclass 24, count 0 2006.285.18:56:58.88#ibcon#about to read 6, iclass 24, count 0 2006.285.18:56:58.88#ibcon#read 6, iclass 24, count 0 2006.285.18:56:58.88#ibcon#end of sib2, iclass 24, count 0 2006.285.18:56:58.88#ibcon#*after write, iclass 24, count 0 2006.285.18:56:58.88#ibcon#*before return 0, iclass 24, count 0 2006.285.18:56:58.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:56:58.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:56:58.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:56:58.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:56:58.88$vck44/valo=7,864.99 2006.285.18:56:58.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.18:56:58.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.18:56:58.88#ibcon#ireg 17 cls_cnt 0 2006.285.18:56:58.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:56:58.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:56:58.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:56:58.89#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:56:58.89#ibcon#first serial, iclass 26, count 0 2006.285.18:56:58.89#ibcon#enter sib2, iclass 26, count 0 2006.285.18:56:58.89#ibcon#flushed, iclass 26, count 0 2006.285.18:56:58.89#ibcon#about to write, iclass 26, count 0 2006.285.18:56:58.89#ibcon#wrote, iclass 26, count 0 2006.285.18:56:58.89#ibcon#about to read 3, iclass 26, count 0 2006.285.18:56:58.90#ibcon#read 3, iclass 26, count 0 2006.285.18:56:58.90#ibcon#about to read 4, iclass 26, count 0 2006.285.18:56:58.90#ibcon#read 4, iclass 26, count 0 2006.285.18:56:58.90#ibcon#about to read 5, iclass 26, count 0 2006.285.18:56:58.90#ibcon#read 5, iclass 26, count 0 2006.285.18:56:58.90#ibcon#about to read 6, iclass 26, count 0 2006.285.18:56:58.90#ibcon#read 6, iclass 26, count 0 2006.285.18:56:58.90#ibcon#end of sib2, iclass 26, count 0 2006.285.18:56:58.90#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:56:58.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:56:58.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.18:56:58.90#ibcon#*before write, iclass 26, count 0 2006.285.18:56:58.90#ibcon#enter sib2, iclass 26, count 0 2006.285.18:56:58.90#ibcon#flushed, iclass 26, count 0 2006.285.18:56:58.90#ibcon#about to write, iclass 26, count 0 2006.285.18:56:58.90#ibcon#wrote, iclass 26, count 0 2006.285.18:56:58.90#ibcon#about to read 3, iclass 26, count 0 2006.285.18:56:58.94#ibcon#read 3, iclass 26, count 0 2006.285.18:56:58.94#ibcon#about to read 4, iclass 26, count 0 2006.285.18:56:58.94#ibcon#read 4, iclass 26, count 0 2006.285.18:56:58.94#ibcon#about to read 5, iclass 26, count 0 2006.285.18:56:58.94#ibcon#read 5, iclass 26, count 0 2006.285.18:56:58.94#ibcon#about to read 6, iclass 26, count 0 2006.285.18:56:58.94#ibcon#read 6, iclass 26, count 0 2006.285.18:56:58.94#ibcon#end of sib2, iclass 26, count 0 2006.285.18:56:58.94#ibcon#*after write, iclass 26, count 0 2006.285.18:56:58.94#ibcon#*before return 0, iclass 26, count 0 2006.285.18:56:58.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:56:58.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:56:58.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:56:58.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:56:58.94$vck44/va=7,4 2006.285.18:56:58.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.18:56:58.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.18:56:58.94#ibcon#ireg 11 cls_cnt 2 2006.285.18:56:58.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:56:59.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:56:59.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:56:59.00#ibcon#enter wrdev, iclass 28, count 2 2006.285.18:56:59.00#ibcon#first serial, iclass 28, count 2 2006.285.18:56:59.00#ibcon#enter sib2, iclass 28, count 2 2006.285.18:56:59.00#ibcon#flushed, iclass 28, count 2 2006.285.18:56:59.00#ibcon#about to write, iclass 28, count 2 2006.285.18:56:59.00#ibcon#wrote, iclass 28, count 2 2006.285.18:56:59.00#ibcon#about to read 3, iclass 28, count 2 2006.285.18:56:59.02#ibcon#read 3, iclass 28, count 2 2006.285.18:56:59.02#ibcon#about to read 4, iclass 28, count 2 2006.285.18:56:59.02#ibcon#read 4, iclass 28, count 2 2006.285.18:56:59.02#ibcon#about to read 5, iclass 28, count 2 2006.285.18:56:59.02#ibcon#read 5, iclass 28, count 2 2006.285.18:56:59.02#ibcon#about to read 6, iclass 28, count 2 2006.285.18:56:59.02#ibcon#read 6, iclass 28, count 2 2006.285.18:56:59.02#ibcon#end of sib2, iclass 28, count 2 2006.285.18:56:59.02#ibcon#*mode == 0, iclass 28, count 2 2006.285.18:56:59.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.18:56:59.02#ibcon#[25=AT07-04\r\n] 2006.285.18:56:59.02#ibcon#*before write, iclass 28, count 2 2006.285.18:56:59.02#ibcon#enter sib2, iclass 28, count 2 2006.285.18:56:59.02#ibcon#flushed, iclass 28, count 2 2006.285.18:56:59.02#ibcon#about to write, iclass 28, count 2 2006.285.18:56:59.02#ibcon#wrote, iclass 28, count 2 2006.285.18:56:59.02#ibcon#about to read 3, iclass 28, count 2 2006.285.18:56:59.05#ibcon#read 3, iclass 28, count 2 2006.285.18:56:59.05#ibcon#about to read 4, iclass 28, count 2 2006.285.18:56:59.05#ibcon#read 4, iclass 28, count 2 2006.285.18:56:59.05#ibcon#about to read 5, iclass 28, count 2 2006.285.18:56:59.05#ibcon#read 5, iclass 28, count 2 2006.285.18:56:59.05#ibcon#about to read 6, iclass 28, count 2 2006.285.18:56:59.05#ibcon#read 6, iclass 28, count 2 2006.285.18:56:59.05#ibcon#end of sib2, iclass 28, count 2 2006.285.18:56:59.05#ibcon#*after write, iclass 28, count 2 2006.285.18:56:59.05#ibcon#*before return 0, iclass 28, count 2 2006.285.18:56:59.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:56:59.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:56:59.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.18:56:59.05#ibcon#ireg 7 cls_cnt 0 2006.285.18:56:59.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:56:59.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:56:59.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:56:59.17#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:56:59.17#ibcon#first serial, iclass 28, count 0 2006.285.18:56:59.17#ibcon#enter sib2, iclass 28, count 0 2006.285.18:56:59.17#ibcon#flushed, iclass 28, count 0 2006.285.18:56:59.17#ibcon#about to write, iclass 28, count 0 2006.285.18:56:59.17#ibcon#wrote, iclass 28, count 0 2006.285.18:56:59.17#ibcon#about to read 3, iclass 28, count 0 2006.285.18:56:59.19#ibcon#read 3, iclass 28, count 0 2006.285.18:56:59.19#ibcon#about to read 4, iclass 28, count 0 2006.285.18:56:59.19#ibcon#read 4, iclass 28, count 0 2006.285.18:56:59.19#ibcon#about to read 5, iclass 28, count 0 2006.285.18:56:59.19#ibcon#read 5, iclass 28, count 0 2006.285.18:56:59.19#ibcon#about to read 6, iclass 28, count 0 2006.285.18:56:59.19#ibcon#read 6, iclass 28, count 0 2006.285.18:56:59.19#ibcon#end of sib2, iclass 28, count 0 2006.285.18:56:59.19#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:56:59.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:56:59.19#ibcon#[25=USB\r\n] 2006.285.18:56:59.19#ibcon#*before write, iclass 28, count 0 2006.285.18:56:59.19#ibcon#enter sib2, iclass 28, count 0 2006.285.18:56:59.19#ibcon#flushed, iclass 28, count 0 2006.285.18:56:59.19#ibcon#about to write, iclass 28, count 0 2006.285.18:56:59.19#ibcon#wrote, iclass 28, count 0 2006.285.18:56:59.19#ibcon#about to read 3, iclass 28, count 0 2006.285.18:56:59.22#ibcon#read 3, iclass 28, count 0 2006.285.18:56:59.22#ibcon#about to read 4, iclass 28, count 0 2006.285.18:56:59.22#ibcon#read 4, iclass 28, count 0 2006.285.18:56:59.22#ibcon#about to read 5, iclass 28, count 0 2006.285.18:56:59.22#ibcon#read 5, iclass 28, count 0 2006.285.18:56:59.22#ibcon#about to read 6, iclass 28, count 0 2006.285.18:56:59.22#ibcon#read 6, iclass 28, count 0 2006.285.18:56:59.22#ibcon#end of sib2, iclass 28, count 0 2006.285.18:56:59.22#ibcon#*after write, iclass 28, count 0 2006.285.18:56:59.22#ibcon#*before return 0, iclass 28, count 0 2006.285.18:56:59.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:56:59.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:56:59.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:56:59.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:56:59.22$vck44/valo=8,884.99 2006.285.18:56:59.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.18:56:59.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.18:56:59.22#ibcon#ireg 17 cls_cnt 0 2006.285.18:56:59.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:56:59.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:56:59.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:56:59.23#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:56:59.23#ibcon#first serial, iclass 30, count 0 2006.285.18:56:59.23#ibcon#enter sib2, iclass 30, count 0 2006.285.18:56:59.23#ibcon#flushed, iclass 30, count 0 2006.285.18:56:59.23#ibcon#about to write, iclass 30, count 0 2006.285.18:56:59.23#ibcon#wrote, iclass 30, count 0 2006.285.18:56:59.23#ibcon#about to read 3, iclass 30, count 0 2006.285.18:56:59.24#ibcon#read 3, iclass 30, count 0 2006.285.18:56:59.24#ibcon#about to read 4, iclass 30, count 0 2006.285.18:56:59.24#ibcon#read 4, iclass 30, count 0 2006.285.18:56:59.24#ibcon#about to read 5, iclass 30, count 0 2006.285.18:56:59.24#ibcon#read 5, iclass 30, count 0 2006.285.18:56:59.24#ibcon#about to read 6, iclass 30, count 0 2006.285.18:56:59.24#ibcon#read 6, iclass 30, count 0 2006.285.18:56:59.24#ibcon#end of sib2, iclass 30, count 0 2006.285.18:56:59.24#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:56:59.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:56:59.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.18:56:59.24#ibcon#*before write, iclass 30, count 0 2006.285.18:56:59.24#ibcon#enter sib2, iclass 30, count 0 2006.285.18:56:59.24#ibcon#flushed, iclass 30, count 0 2006.285.18:56:59.24#ibcon#about to write, iclass 30, count 0 2006.285.18:56:59.24#ibcon#wrote, iclass 30, count 0 2006.285.18:56:59.24#ibcon#about to read 3, iclass 30, count 0 2006.285.18:56:59.28#ibcon#read 3, iclass 30, count 0 2006.285.18:56:59.28#ibcon#about to read 4, iclass 30, count 0 2006.285.18:56:59.28#ibcon#read 4, iclass 30, count 0 2006.285.18:56:59.28#ibcon#about to read 5, iclass 30, count 0 2006.285.18:56:59.28#ibcon#read 5, iclass 30, count 0 2006.285.18:56:59.28#ibcon#about to read 6, iclass 30, count 0 2006.285.18:56:59.28#ibcon#read 6, iclass 30, count 0 2006.285.18:56:59.28#ibcon#end of sib2, iclass 30, count 0 2006.285.18:56:59.28#ibcon#*after write, iclass 30, count 0 2006.285.18:56:59.28#ibcon#*before return 0, iclass 30, count 0 2006.285.18:56:59.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:56:59.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:56:59.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:56:59.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:56:59.28$vck44/va=8,3 2006.285.18:56:59.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.18:56:59.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.18:56:59.28#ibcon#ireg 11 cls_cnt 2 2006.285.18:56:59.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:56:59.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:56:59.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:56:59.34#ibcon#enter wrdev, iclass 32, count 2 2006.285.18:56:59.34#ibcon#first serial, iclass 32, count 2 2006.285.18:56:59.34#ibcon#enter sib2, iclass 32, count 2 2006.285.18:56:59.34#ibcon#flushed, iclass 32, count 2 2006.285.18:56:59.34#ibcon#about to write, iclass 32, count 2 2006.285.18:56:59.34#ibcon#wrote, iclass 32, count 2 2006.285.18:56:59.34#ibcon#about to read 3, iclass 32, count 2 2006.285.18:56:59.36#ibcon#read 3, iclass 32, count 2 2006.285.18:56:59.36#ibcon#about to read 4, iclass 32, count 2 2006.285.18:56:59.36#ibcon#read 4, iclass 32, count 2 2006.285.18:56:59.36#ibcon#about to read 5, iclass 32, count 2 2006.285.18:56:59.36#ibcon#read 5, iclass 32, count 2 2006.285.18:56:59.36#ibcon#about to read 6, iclass 32, count 2 2006.285.18:56:59.36#ibcon#read 6, iclass 32, count 2 2006.285.18:56:59.36#ibcon#end of sib2, iclass 32, count 2 2006.285.18:56:59.36#ibcon#*mode == 0, iclass 32, count 2 2006.285.18:56:59.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.18:56:59.36#ibcon#[25=AT08-03\r\n] 2006.285.18:56:59.36#ibcon#*before write, iclass 32, count 2 2006.285.18:56:59.36#ibcon#enter sib2, iclass 32, count 2 2006.285.18:56:59.36#ibcon#flushed, iclass 32, count 2 2006.285.18:56:59.36#ibcon#about to write, iclass 32, count 2 2006.285.18:56:59.36#ibcon#wrote, iclass 32, count 2 2006.285.18:56:59.36#ibcon#about to read 3, iclass 32, count 2 2006.285.18:56:59.39#ibcon#read 3, iclass 32, count 2 2006.285.18:56:59.39#ibcon#about to read 4, iclass 32, count 2 2006.285.18:56:59.39#ibcon#read 4, iclass 32, count 2 2006.285.18:56:59.39#ibcon#about to read 5, iclass 32, count 2 2006.285.18:56:59.39#ibcon#read 5, iclass 32, count 2 2006.285.18:56:59.39#ibcon#about to read 6, iclass 32, count 2 2006.285.18:56:59.39#ibcon#read 6, iclass 32, count 2 2006.285.18:56:59.39#ibcon#end of sib2, iclass 32, count 2 2006.285.18:56:59.39#ibcon#*after write, iclass 32, count 2 2006.285.18:56:59.39#ibcon#*before return 0, iclass 32, count 2 2006.285.18:56:59.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:56:59.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.18:56:59.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.18:56:59.39#ibcon#ireg 7 cls_cnt 0 2006.285.18:56:59.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:56:59.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:56:59.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:56:59.51#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:56:59.51#ibcon#first serial, iclass 32, count 0 2006.285.18:56:59.51#ibcon#enter sib2, iclass 32, count 0 2006.285.18:56:59.51#ibcon#flushed, iclass 32, count 0 2006.285.18:56:59.51#ibcon#about to write, iclass 32, count 0 2006.285.18:56:59.51#ibcon#wrote, iclass 32, count 0 2006.285.18:56:59.51#ibcon#about to read 3, iclass 32, count 0 2006.285.18:56:59.53#ibcon#read 3, iclass 32, count 0 2006.285.18:56:59.53#ibcon#about to read 4, iclass 32, count 0 2006.285.18:56:59.53#ibcon#read 4, iclass 32, count 0 2006.285.18:56:59.53#ibcon#about to read 5, iclass 32, count 0 2006.285.18:56:59.53#ibcon#read 5, iclass 32, count 0 2006.285.18:56:59.53#ibcon#about to read 6, iclass 32, count 0 2006.285.18:56:59.53#ibcon#read 6, iclass 32, count 0 2006.285.18:56:59.53#ibcon#end of sib2, iclass 32, count 0 2006.285.18:56:59.53#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:56:59.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:56:59.53#ibcon#[25=USB\r\n] 2006.285.18:56:59.53#ibcon#*before write, iclass 32, count 0 2006.285.18:56:59.53#ibcon#enter sib2, iclass 32, count 0 2006.285.18:56:59.53#ibcon#flushed, iclass 32, count 0 2006.285.18:56:59.53#ibcon#about to write, iclass 32, count 0 2006.285.18:56:59.53#ibcon#wrote, iclass 32, count 0 2006.285.18:56:59.53#ibcon#about to read 3, iclass 32, count 0 2006.285.18:56:59.56#ibcon#read 3, iclass 32, count 0 2006.285.18:56:59.56#ibcon#about to read 4, iclass 32, count 0 2006.285.18:56:59.56#ibcon#read 4, iclass 32, count 0 2006.285.18:56:59.56#ibcon#about to read 5, iclass 32, count 0 2006.285.18:56:59.56#ibcon#read 5, iclass 32, count 0 2006.285.18:56:59.56#ibcon#about to read 6, iclass 32, count 0 2006.285.18:56:59.56#ibcon#read 6, iclass 32, count 0 2006.285.18:56:59.56#ibcon#end of sib2, iclass 32, count 0 2006.285.18:56:59.56#ibcon#*after write, iclass 32, count 0 2006.285.18:56:59.56#ibcon#*before return 0, iclass 32, count 0 2006.285.18:56:59.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:56:59.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.18:56:59.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:56:59.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:56:59.56$vck44/vblo=1,629.99 2006.285.18:56:59.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.18:56:59.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.18:56:59.56#ibcon#ireg 17 cls_cnt 0 2006.285.18:56:59.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:56:59.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:56:59.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:56:59.57#ibcon#enter wrdev, iclass 34, count 0 2006.285.18:56:59.57#ibcon#first serial, iclass 34, count 0 2006.285.18:56:59.57#ibcon#enter sib2, iclass 34, count 0 2006.285.18:56:59.57#ibcon#flushed, iclass 34, count 0 2006.285.18:56:59.57#ibcon#about to write, iclass 34, count 0 2006.285.18:56:59.57#ibcon#wrote, iclass 34, count 0 2006.285.18:56:59.57#ibcon#about to read 3, iclass 34, count 0 2006.285.18:56:59.58#ibcon#read 3, iclass 34, count 0 2006.285.18:56:59.70#ibcon#about to read 4, iclass 34, count 0 2006.285.18:56:59.70#ibcon#read 4, iclass 34, count 0 2006.285.18:56:59.70#ibcon#about to read 5, iclass 34, count 0 2006.285.18:56:59.70#ibcon#read 5, iclass 34, count 0 2006.285.18:56:59.70#ibcon#about to read 6, iclass 34, count 0 2006.285.18:56:59.70#ibcon#read 6, iclass 34, count 0 2006.285.18:56:59.70#ibcon#end of sib2, iclass 34, count 0 2006.285.18:56:59.70#ibcon#*mode == 0, iclass 34, count 0 2006.285.18:56:59.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.18:56:59.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.18:56:59.70#ibcon#*before write, iclass 34, count 0 2006.285.18:56:59.70#ibcon#enter sib2, iclass 34, count 0 2006.285.18:56:59.70#ibcon#flushed, iclass 34, count 0 2006.285.18:56:59.70#ibcon#about to write, iclass 34, count 0 2006.285.18:56:59.70#ibcon#wrote, iclass 34, count 0 2006.285.18:56:59.70#ibcon#about to read 3, iclass 34, count 0 2006.285.18:56:59.74#ibcon#read 3, iclass 34, count 0 2006.285.18:56:59.74#ibcon#about to read 4, iclass 34, count 0 2006.285.18:56:59.74#ibcon#read 4, iclass 34, count 0 2006.285.18:56:59.74#ibcon#about to read 5, iclass 34, count 0 2006.285.18:56:59.74#ibcon#read 5, iclass 34, count 0 2006.285.18:56:59.74#ibcon#about to read 6, iclass 34, count 0 2006.285.18:56:59.74#ibcon#read 6, iclass 34, count 0 2006.285.18:56:59.74#ibcon#end of sib2, iclass 34, count 0 2006.285.18:56:59.74#ibcon#*after write, iclass 34, count 0 2006.285.18:56:59.74#ibcon#*before return 0, iclass 34, count 0 2006.285.18:56:59.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:56:59.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.18:56:59.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.18:56:59.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.18:56:59.74$vck44/vb=1,4 2006.285.18:56:59.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.18:56:59.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.18:56:59.75#ibcon#ireg 11 cls_cnt 2 2006.285.18:56:59.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:56:59.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:56:59.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:56:59.75#ibcon#enter wrdev, iclass 36, count 2 2006.285.18:56:59.75#ibcon#first serial, iclass 36, count 2 2006.285.18:56:59.75#ibcon#enter sib2, iclass 36, count 2 2006.285.18:56:59.75#ibcon#flushed, iclass 36, count 2 2006.285.18:56:59.75#ibcon#about to write, iclass 36, count 2 2006.285.18:56:59.75#ibcon#wrote, iclass 36, count 2 2006.285.18:56:59.75#ibcon#about to read 3, iclass 36, count 2 2006.285.18:56:59.76#ibcon#read 3, iclass 36, count 2 2006.285.18:56:59.76#ibcon#about to read 4, iclass 36, count 2 2006.285.18:56:59.76#ibcon#read 4, iclass 36, count 2 2006.285.18:56:59.76#ibcon#about to read 5, iclass 36, count 2 2006.285.18:56:59.76#ibcon#read 5, iclass 36, count 2 2006.285.18:56:59.76#ibcon#about to read 6, iclass 36, count 2 2006.285.18:56:59.76#ibcon#read 6, iclass 36, count 2 2006.285.18:56:59.76#ibcon#end of sib2, iclass 36, count 2 2006.285.18:56:59.76#ibcon#*mode == 0, iclass 36, count 2 2006.285.18:56:59.76#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.18:56:59.76#ibcon#[27=AT01-04\r\n] 2006.285.18:56:59.76#ibcon#*before write, iclass 36, count 2 2006.285.18:56:59.76#ibcon#enter sib2, iclass 36, count 2 2006.285.18:56:59.76#ibcon#flushed, iclass 36, count 2 2006.285.18:56:59.76#ibcon#about to write, iclass 36, count 2 2006.285.18:56:59.76#ibcon#wrote, iclass 36, count 2 2006.285.18:56:59.76#ibcon#about to read 3, iclass 36, count 2 2006.285.18:56:59.79#ibcon#read 3, iclass 36, count 2 2006.285.18:56:59.79#ibcon#about to read 4, iclass 36, count 2 2006.285.18:56:59.79#ibcon#read 4, iclass 36, count 2 2006.285.18:56:59.79#ibcon#about to read 5, iclass 36, count 2 2006.285.18:56:59.79#ibcon#read 5, iclass 36, count 2 2006.285.18:56:59.79#ibcon#about to read 6, iclass 36, count 2 2006.285.18:56:59.79#ibcon#read 6, iclass 36, count 2 2006.285.18:56:59.79#ibcon#end of sib2, iclass 36, count 2 2006.285.18:56:59.79#ibcon#*after write, iclass 36, count 2 2006.285.18:56:59.79#ibcon#*before return 0, iclass 36, count 2 2006.285.18:56:59.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:56:59.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.18:56:59.79#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.18:56:59.79#ibcon#ireg 7 cls_cnt 0 2006.285.18:56:59.79#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:56:59.91#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:56:59.91#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:56:59.91#ibcon#enter wrdev, iclass 36, count 0 2006.285.18:56:59.91#ibcon#first serial, iclass 36, count 0 2006.285.18:56:59.91#ibcon#enter sib2, iclass 36, count 0 2006.285.18:56:59.91#ibcon#flushed, iclass 36, count 0 2006.285.18:56:59.91#ibcon#about to write, iclass 36, count 0 2006.285.18:56:59.91#ibcon#wrote, iclass 36, count 0 2006.285.18:56:59.91#ibcon#about to read 3, iclass 36, count 0 2006.285.18:56:59.93#ibcon#read 3, iclass 36, count 0 2006.285.18:56:59.93#ibcon#about to read 4, iclass 36, count 0 2006.285.18:56:59.93#ibcon#read 4, iclass 36, count 0 2006.285.18:56:59.93#ibcon#about to read 5, iclass 36, count 0 2006.285.18:56:59.93#ibcon#read 5, iclass 36, count 0 2006.285.18:56:59.93#ibcon#about to read 6, iclass 36, count 0 2006.285.18:56:59.93#ibcon#read 6, iclass 36, count 0 2006.285.18:56:59.93#ibcon#end of sib2, iclass 36, count 0 2006.285.18:56:59.93#ibcon#*mode == 0, iclass 36, count 0 2006.285.18:56:59.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.18:56:59.93#ibcon#[27=USB\r\n] 2006.285.18:56:59.93#ibcon#*before write, iclass 36, count 0 2006.285.18:56:59.93#ibcon#enter sib2, iclass 36, count 0 2006.285.18:56:59.93#ibcon#flushed, iclass 36, count 0 2006.285.18:56:59.93#ibcon#about to write, iclass 36, count 0 2006.285.18:56:59.93#ibcon#wrote, iclass 36, count 0 2006.285.18:56:59.93#ibcon#about to read 3, iclass 36, count 0 2006.285.18:56:59.96#ibcon#read 3, iclass 36, count 0 2006.285.18:56:59.96#ibcon#about to read 4, iclass 36, count 0 2006.285.18:56:59.96#ibcon#read 4, iclass 36, count 0 2006.285.18:56:59.96#ibcon#about to read 5, iclass 36, count 0 2006.285.18:56:59.96#ibcon#read 5, iclass 36, count 0 2006.285.18:56:59.96#ibcon#about to read 6, iclass 36, count 0 2006.285.18:56:59.96#ibcon#read 6, iclass 36, count 0 2006.285.18:56:59.96#ibcon#end of sib2, iclass 36, count 0 2006.285.18:56:59.96#ibcon#*after write, iclass 36, count 0 2006.285.18:56:59.96#ibcon#*before return 0, iclass 36, count 0 2006.285.18:56:59.96#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:56:59.96#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.18:56:59.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.18:56:59.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.18:56:59.96$vck44/vblo=2,634.99 2006.285.18:56:59.97#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.18:56:59.97#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.18:56:59.97#ibcon#ireg 17 cls_cnt 0 2006.285.18:56:59.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:56:59.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:56:59.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:56:59.97#ibcon#enter wrdev, iclass 38, count 0 2006.285.18:56:59.97#ibcon#first serial, iclass 38, count 0 2006.285.18:56:59.97#ibcon#enter sib2, iclass 38, count 0 2006.285.18:56:59.97#ibcon#flushed, iclass 38, count 0 2006.285.18:56:59.97#ibcon#about to write, iclass 38, count 0 2006.285.18:56:59.97#ibcon#wrote, iclass 38, count 0 2006.285.18:56:59.97#ibcon#about to read 3, iclass 38, count 0 2006.285.18:56:59.98#ibcon#read 3, iclass 38, count 0 2006.285.18:56:59.98#ibcon#about to read 4, iclass 38, count 0 2006.285.18:56:59.98#ibcon#read 4, iclass 38, count 0 2006.285.18:56:59.98#ibcon#about to read 5, iclass 38, count 0 2006.285.18:56:59.98#ibcon#read 5, iclass 38, count 0 2006.285.18:56:59.98#ibcon#about to read 6, iclass 38, count 0 2006.285.18:56:59.98#ibcon#read 6, iclass 38, count 0 2006.285.18:56:59.98#ibcon#end of sib2, iclass 38, count 0 2006.285.18:56:59.98#ibcon#*mode == 0, iclass 38, count 0 2006.285.18:56:59.98#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.18:56:59.98#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.18:56:59.98#ibcon#*before write, iclass 38, count 0 2006.285.18:56:59.98#ibcon#enter sib2, iclass 38, count 0 2006.285.18:56:59.98#ibcon#flushed, iclass 38, count 0 2006.285.18:56:59.98#ibcon#about to write, iclass 38, count 0 2006.285.18:56:59.98#ibcon#wrote, iclass 38, count 0 2006.285.18:56:59.98#ibcon#about to read 3, iclass 38, count 0 2006.285.18:57:00.02#ibcon#read 3, iclass 38, count 0 2006.285.18:57:00.02#ibcon#about to read 4, iclass 38, count 0 2006.285.18:57:00.02#ibcon#read 4, iclass 38, count 0 2006.285.18:57:00.02#ibcon#about to read 5, iclass 38, count 0 2006.285.18:57:00.02#ibcon#read 5, iclass 38, count 0 2006.285.18:57:00.02#ibcon#about to read 6, iclass 38, count 0 2006.285.18:57:00.02#ibcon#read 6, iclass 38, count 0 2006.285.18:57:00.02#ibcon#end of sib2, iclass 38, count 0 2006.285.18:57:00.02#ibcon#*after write, iclass 38, count 0 2006.285.18:57:00.02#ibcon#*before return 0, iclass 38, count 0 2006.285.18:57:00.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:57:00.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.18:57:00.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.18:57:00.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.18:57:00.02$vck44/vb=2,5 2006.285.18:57:00.03#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.18:57:00.03#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.18:57:00.03#ibcon#ireg 11 cls_cnt 2 2006.285.18:57:00.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:57:00.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:57:00.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:57:00.07#ibcon#enter wrdev, iclass 40, count 2 2006.285.18:57:00.07#ibcon#first serial, iclass 40, count 2 2006.285.18:57:00.07#ibcon#enter sib2, iclass 40, count 2 2006.285.18:57:00.07#ibcon#flushed, iclass 40, count 2 2006.285.18:57:00.07#ibcon#about to write, iclass 40, count 2 2006.285.18:57:00.07#ibcon#wrote, iclass 40, count 2 2006.285.18:57:00.07#ibcon#about to read 3, iclass 40, count 2 2006.285.18:57:00.09#ibcon#read 3, iclass 40, count 2 2006.285.18:57:00.09#ibcon#about to read 4, iclass 40, count 2 2006.285.18:57:00.09#ibcon#read 4, iclass 40, count 2 2006.285.18:57:00.09#ibcon#about to read 5, iclass 40, count 2 2006.285.18:57:00.09#ibcon#read 5, iclass 40, count 2 2006.285.18:57:00.09#ibcon#about to read 6, iclass 40, count 2 2006.285.18:57:00.09#ibcon#read 6, iclass 40, count 2 2006.285.18:57:00.09#ibcon#end of sib2, iclass 40, count 2 2006.285.18:57:00.09#ibcon#*mode == 0, iclass 40, count 2 2006.285.18:57:00.09#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.18:57:00.09#ibcon#[27=AT02-05\r\n] 2006.285.18:57:00.09#ibcon#*before write, iclass 40, count 2 2006.285.18:57:00.09#ibcon#enter sib2, iclass 40, count 2 2006.285.18:57:00.09#ibcon#flushed, iclass 40, count 2 2006.285.18:57:00.09#ibcon#about to write, iclass 40, count 2 2006.285.18:57:00.09#ibcon#wrote, iclass 40, count 2 2006.285.18:57:00.09#ibcon#about to read 3, iclass 40, count 2 2006.285.18:57:00.12#ibcon#read 3, iclass 40, count 2 2006.285.18:57:00.12#ibcon#about to read 4, iclass 40, count 2 2006.285.18:57:00.12#ibcon#read 4, iclass 40, count 2 2006.285.18:57:00.12#ibcon#about to read 5, iclass 40, count 2 2006.285.18:57:00.12#ibcon#read 5, iclass 40, count 2 2006.285.18:57:00.12#ibcon#about to read 6, iclass 40, count 2 2006.285.18:57:00.12#ibcon#read 6, iclass 40, count 2 2006.285.18:57:00.12#ibcon#end of sib2, iclass 40, count 2 2006.285.18:57:00.12#ibcon#*after write, iclass 40, count 2 2006.285.18:57:00.12#ibcon#*before return 0, iclass 40, count 2 2006.285.18:57:00.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:57:00.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.18:57:00.12#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.18:57:00.12#ibcon#ireg 7 cls_cnt 0 2006.285.18:57:00.12#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:57:00.24#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:57:00.24#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:57:00.24#ibcon#enter wrdev, iclass 40, count 0 2006.285.18:57:00.24#ibcon#first serial, iclass 40, count 0 2006.285.18:57:00.24#ibcon#enter sib2, iclass 40, count 0 2006.285.18:57:00.24#ibcon#flushed, iclass 40, count 0 2006.285.18:57:00.24#ibcon#about to write, iclass 40, count 0 2006.285.18:57:00.24#ibcon#wrote, iclass 40, count 0 2006.285.18:57:00.24#ibcon#about to read 3, iclass 40, count 0 2006.285.18:57:00.26#ibcon#read 3, iclass 40, count 0 2006.285.18:57:00.26#ibcon#about to read 4, iclass 40, count 0 2006.285.18:57:00.26#ibcon#read 4, iclass 40, count 0 2006.285.18:57:00.26#ibcon#about to read 5, iclass 40, count 0 2006.285.18:57:00.26#ibcon#read 5, iclass 40, count 0 2006.285.18:57:00.26#ibcon#about to read 6, iclass 40, count 0 2006.285.18:57:00.26#ibcon#read 6, iclass 40, count 0 2006.285.18:57:00.26#ibcon#end of sib2, iclass 40, count 0 2006.285.18:57:00.26#ibcon#*mode == 0, iclass 40, count 0 2006.285.18:57:00.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.18:57:00.26#ibcon#[27=USB\r\n] 2006.285.18:57:00.26#ibcon#*before write, iclass 40, count 0 2006.285.18:57:00.26#ibcon#enter sib2, iclass 40, count 0 2006.285.18:57:00.26#ibcon#flushed, iclass 40, count 0 2006.285.18:57:00.26#ibcon#about to write, iclass 40, count 0 2006.285.18:57:00.26#ibcon#wrote, iclass 40, count 0 2006.285.18:57:00.26#ibcon#about to read 3, iclass 40, count 0 2006.285.18:57:00.29#ibcon#read 3, iclass 40, count 0 2006.285.18:57:00.29#ibcon#about to read 4, iclass 40, count 0 2006.285.18:57:00.29#ibcon#read 4, iclass 40, count 0 2006.285.18:57:00.29#ibcon#about to read 5, iclass 40, count 0 2006.285.18:57:00.29#ibcon#read 5, iclass 40, count 0 2006.285.18:57:00.29#ibcon#about to read 6, iclass 40, count 0 2006.285.18:57:00.29#ibcon#read 6, iclass 40, count 0 2006.285.18:57:00.29#ibcon#end of sib2, iclass 40, count 0 2006.285.18:57:00.29#ibcon#*after write, iclass 40, count 0 2006.285.18:57:00.29#ibcon#*before return 0, iclass 40, count 0 2006.285.18:57:00.29#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:57:00.29#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.18:57:00.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.18:57:00.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.18:57:00.29$vck44/vblo=3,649.99 2006.285.18:57:00.30#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.18:57:00.30#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.18:57:00.30#ibcon#ireg 17 cls_cnt 0 2006.285.18:57:00.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:57:00.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:57:00.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:57:00.30#ibcon#enter wrdev, iclass 4, count 0 2006.285.18:57:00.30#ibcon#first serial, iclass 4, count 0 2006.285.18:57:00.30#ibcon#enter sib2, iclass 4, count 0 2006.285.18:57:00.30#ibcon#flushed, iclass 4, count 0 2006.285.18:57:00.30#ibcon#about to write, iclass 4, count 0 2006.285.18:57:00.30#ibcon#wrote, iclass 4, count 0 2006.285.18:57:00.30#ibcon#about to read 3, iclass 4, count 0 2006.285.18:57:00.31#ibcon#read 3, iclass 4, count 0 2006.285.18:57:00.31#ibcon#about to read 4, iclass 4, count 0 2006.285.18:57:00.31#ibcon#read 4, iclass 4, count 0 2006.285.18:57:00.31#ibcon#about to read 5, iclass 4, count 0 2006.285.18:57:00.31#ibcon#read 5, iclass 4, count 0 2006.285.18:57:00.31#ibcon#about to read 6, iclass 4, count 0 2006.285.18:57:00.31#ibcon#read 6, iclass 4, count 0 2006.285.18:57:00.31#ibcon#end of sib2, iclass 4, count 0 2006.285.18:57:00.31#ibcon#*mode == 0, iclass 4, count 0 2006.285.18:57:00.31#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.18:57:00.31#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.18:57:00.31#ibcon#*before write, iclass 4, count 0 2006.285.18:57:00.31#ibcon#enter sib2, iclass 4, count 0 2006.285.18:57:00.31#ibcon#flushed, iclass 4, count 0 2006.285.18:57:00.31#ibcon#about to write, iclass 4, count 0 2006.285.18:57:00.31#ibcon#wrote, iclass 4, count 0 2006.285.18:57:00.31#ibcon#about to read 3, iclass 4, count 0 2006.285.18:57:00.35#ibcon#read 3, iclass 4, count 0 2006.285.18:57:00.35#ibcon#about to read 4, iclass 4, count 0 2006.285.18:57:00.35#ibcon#read 4, iclass 4, count 0 2006.285.18:57:00.35#ibcon#about to read 5, iclass 4, count 0 2006.285.18:57:00.35#ibcon#read 5, iclass 4, count 0 2006.285.18:57:00.35#ibcon#about to read 6, iclass 4, count 0 2006.285.18:57:00.35#ibcon#read 6, iclass 4, count 0 2006.285.18:57:00.35#ibcon#end of sib2, iclass 4, count 0 2006.285.18:57:00.35#ibcon#*after write, iclass 4, count 0 2006.285.18:57:00.35#ibcon#*before return 0, iclass 4, count 0 2006.285.18:57:00.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:57:00.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.18:57:00.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.18:57:00.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.18:57:00.35$vck44/vb=3,4 2006.285.18:57:00.36#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.18:57:00.36#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.18:57:00.36#ibcon#ireg 11 cls_cnt 2 2006.285.18:57:00.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:57:00.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:57:00.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:57:00.40#ibcon#enter wrdev, iclass 6, count 2 2006.285.18:57:00.40#ibcon#first serial, iclass 6, count 2 2006.285.18:57:00.40#ibcon#enter sib2, iclass 6, count 2 2006.285.18:57:00.40#ibcon#flushed, iclass 6, count 2 2006.285.18:57:00.40#ibcon#about to write, iclass 6, count 2 2006.285.18:57:00.40#ibcon#wrote, iclass 6, count 2 2006.285.18:57:00.40#ibcon#about to read 3, iclass 6, count 2 2006.285.18:57:00.42#ibcon#read 3, iclass 6, count 2 2006.285.18:57:00.42#ibcon#about to read 4, iclass 6, count 2 2006.285.18:57:00.42#ibcon#read 4, iclass 6, count 2 2006.285.18:57:00.42#ibcon#about to read 5, iclass 6, count 2 2006.285.18:57:00.42#ibcon#read 5, iclass 6, count 2 2006.285.18:57:00.42#ibcon#about to read 6, iclass 6, count 2 2006.285.18:57:00.42#ibcon#read 6, iclass 6, count 2 2006.285.18:57:00.42#ibcon#end of sib2, iclass 6, count 2 2006.285.18:57:00.42#ibcon#*mode == 0, iclass 6, count 2 2006.285.18:57:00.42#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.18:57:00.42#ibcon#[27=AT03-04\r\n] 2006.285.18:57:00.42#ibcon#*before write, iclass 6, count 2 2006.285.18:57:00.42#ibcon#enter sib2, iclass 6, count 2 2006.285.18:57:00.42#ibcon#flushed, iclass 6, count 2 2006.285.18:57:00.42#ibcon#about to write, iclass 6, count 2 2006.285.18:57:00.42#ibcon#wrote, iclass 6, count 2 2006.285.18:57:00.42#ibcon#about to read 3, iclass 6, count 2 2006.285.18:57:00.45#ibcon#read 3, iclass 6, count 2 2006.285.18:57:00.45#ibcon#about to read 4, iclass 6, count 2 2006.285.18:57:00.45#ibcon#read 4, iclass 6, count 2 2006.285.18:57:00.45#ibcon#about to read 5, iclass 6, count 2 2006.285.18:57:00.45#ibcon#read 5, iclass 6, count 2 2006.285.18:57:00.45#ibcon#about to read 6, iclass 6, count 2 2006.285.18:57:00.45#ibcon#read 6, iclass 6, count 2 2006.285.18:57:00.45#ibcon#end of sib2, iclass 6, count 2 2006.285.18:57:00.45#ibcon#*after write, iclass 6, count 2 2006.285.18:57:00.45#ibcon#*before return 0, iclass 6, count 2 2006.285.18:57:00.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:57:00.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.18:57:00.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.18:57:00.45#ibcon#ireg 7 cls_cnt 0 2006.285.18:57:00.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:57:00.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:57:00.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:57:00.57#ibcon#enter wrdev, iclass 6, count 0 2006.285.18:57:00.57#ibcon#first serial, iclass 6, count 0 2006.285.18:57:00.57#ibcon#enter sib2, iclass 6, count 0 2006.285.18:57:00.57#ibcon#flushed, iclass 6, count 0 2006.285.18:57:00.57#ibcon#about to write, iclass 6, count 0 2006.285.18:57:00.57#ibcon#wrote, iclass 6, count 0 2006.285.18:57:00.57#ibcon#about to read 3, iclass 6, count 0 2006.285.18:57:00.59#ibcon#read 3, iclass 6, count 0 2006.285.18:57:00.59#ibcon#about to read 4, iclass 6, count 0 2006.285.18:57:00.59#ibcon#read 4, iclass 6, count 0 2006.285.18:57:00.59#ibcon#about to read 5, iclass 6, count 0 2006.285.18:57:00.59#ibcon#read 5, iclass 6, count 0 2006.285.18:57:00.59#ibcon#about to read 6, iclass 6, count 0 2006.285.18:57:00.59#ibcon#read 6, iclass 6, count 0 2006.285.18:57:00.59#ibcon#end of sib2, iclass 6, count 0 2006.285.18:57:00.59#ibcon#*mode == 0, iclass 6, count 0 2006.285.18:57:00.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.18:57:00.59#ibcon#[27=USB\r\n] 2006.285.18:57:00.59#ibcon#*before write, iclass 6, count 0 2006.285.18:57:00.59#ibcon#enter sib2, iclass 6, count 0 2006.285.18:57:00.59#ibcon#flushed, iclass 6, count 0 2006.285.18:57:00.59#ibcon#about to write, iclass 6, count 0 2006.285.18:57:00.59#ibcon#wrote, iclass 6, count 0 2006.285.18:57:00.59#ibcon#about to read 3, iclass 6, count 0 2006.285.18:57:00.62#ibcon#read 3, iclass 6, count 0 2006.285.18:57:00.62#ibcon#about to read 4, iclass 6, count 0 2006.285.18:57:00.62#ibcon#read 4, iclass 6, count 0 2006.285.18:57:00.62#ibcon#about to read 5, iclass 6, count 0 2006.285.18:57:00.62#ibcon#read 5, iclass 6, count 0 2006.285.18:57:00.62#ibcon#about to read 6, iclass 6, count 0 2006.285.18:57:00.62#ibcon#read 6, iclass 6, count 0 2006.285.18:57:00.62#ibcon#end of sib2, iclass 6, count 0 2006.285.18:57:00.62#ibcon#*after write, iclass 6, count 0 2006.285.18:57:00.62#ibcon#*before return 0, iclass 6, count 0 2006.285.18:57:00.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:57:00.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.18:57:00.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.18:57:00.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.18:57:00.62$vck44/vblo=4,679.99 2006.285.18:57:00.63#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.18:57:00.63#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.18:57:00.63#ibcon#ireg 17 cls_cnt 0 2006.285.18:57:00.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:57:00.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:57:00.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:57:00.63#ibcon#enter wrdev, iclass 10, count 0 2006.285.18:57:00.63#ibcon#first serial, iclass 10, count 0 2006.285.18:57:00.63#ibcon#enter sib2, iclass 10, count 0 2006.285.18:57:00.63#ibcon#flushed, iclass 10, count 0 2006.285.18:57:00.63#ibcon#about to write, iclass 10, count 0 2006.285.18:57:00.63#ibcon#wrote, iclass 10, count 0 2006.285.18:57:00.63#ibcon#about to read 3, iclass 10, count 0 2006.285.18:57:00.79#ibcon#read 3, iclass 10, count 0 2006.285.18:57:00.79#ibcon#about to read 4, iclass 10, count 0 2006.285.18:57:00.79#ibcon#read 4, iclass 10, count 0 2006.285.18:57:00.79#ibcon#about to read 5, iclass 10, count 0 2006.285.18:57:00.79#ibcon#read 5, iclass 10, count 0 2006.285.18:57:00.79#ibcon#about to read 6, iclass 10, count 0 2006.285.18:57:00.79#ibcon#read 6, iclass 10, count 0 2006.285.18:57:00.79#ibcon#end of sib2, iclass 10, count 0 2006.285.18:57:00.79#ibcon#*mode == 0, iclass 10, count 0 2006.285.18:57:00.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.18:57:00.79#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.18:57:00.79#ibcon#*before write, iclass 10, count 0 2006.285.18:57:00.79#ibcon#enter sib2, iclass 10, count 0 2006.285.18:57:00.79#ibcon#flushed, iclass 10, count 0 2006.285.18:57:00.79#ibcon#about to write, iclass 10, count 0 2006.285.18:57:00.79#ibcon#wrote, iclass 10, count 0 2006.285.18:57:00.79#ibcon#about to read 3, iclass 10, count 0 2006.285.18:57:00.82#ibcon#read 3, iclass 10, count 0 2006.285.18:57:00.82#ibcon#about to read 4, iclass 10, count 0 2006.285.18:57:00.82#ibcon#read 4, iclass 10, count 0 2006.285.18:57:00.82#ibcon#about to read 5, iclass 10, count 0 2006.285.18:57:00.82#ibcon#read 5, iclass 10, count 0 2006.285.18:57:00.82#ibcon#about to read 6, iclass 10, count 0 2006.285.18:57:00.82#ibcon#read 6, iclass 10, count 0 2006.285.18:57:00.82#ibcon#end of sib2, iclass 10, count 0 2006.285.18:57:00.82#ibcon#*after write, iclass 10, count 0 2006.285.18:57:00.82#ibcon#*before return 0, iclass 10, count 0 2006.285.18:57:00.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:57:00.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.18:57:00.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.18:57:00.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.18:57:00.82$vck44/vb=4,5 2006.285.18:57:00.83#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.18:57:00.83#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.18:57:00.83#ibcon#ireg 11 cls_cnt 2 2006.285.18:57:00.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:57:00.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:57:00.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:57:00.83#ibcon#enter wrdev, iclass 12, count 2 2006.285.18:57:00.83#ibcon#first serial, iclass 12, count 2 2006.285.18:57:00.83#ibcon#enter sib2, iclass 12, count 2 2006.285.18:57:00.83#ibcon#flushed, iclass 12, count 2 2006.285.18:57:00.83#ibcon#about to write, iclass 12, count 2 2006.285.18:57:00.83#ibcon#wrote, iclass 12, count 2 2006.285.18:57:00.83#ibcon#about to read 3, iclass 12, count 2 2006.285.18:57:00.84#ibcon#read 3, iclass 12, count 2 2006.285.18:57:00.84#ibcon#about to read 4, iclass 12, count 2 2006.285.18:57:00.84#ibcon#read 4, iclass 12, count 2 2006.285.18:57:00.84#ibcon#about to read 5, iclass 12, count 2 2006.285.18:57:00.84#ibcon#read 5, iclass 12, count 2 2006.285.18:57:00.84#ibcon#about to read 6, iclass 12, count 2 2006.285.18:57:00.84#ibcon#read 6, iclass 12, count 2 2006.285.18:57:00.84#ibcon#end of sib2, iclass 12, count 2 2006.285.18:57:00.84#ibcon#*mode == 0, iclass 12, count 2 2006.285.18:57:00.84#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.18:57:00.84#ibcon#[27=AT04-05\r\n] 2006.285.18:57:00.84#ibcon#*before write, iclass 12, count 2 2006.285.18:57:00.84#ibcon#enter sib2, iclass 12, count 2 2006.285.18:57:00.84#ibcon#flushed, iclass 12, count 2 2006.285.18:57:00.84#ibcon#about to write, iclass 12, count 2 2006.285.18:57:00.84#ibcon#wrote, iclass 12, count 2 2006.285.18:57:00.84#ibcon#about to read 3, iclass 12, count 2 2006.285.18:57:00.87#ibcon#read 3, iclass 12, count 2 2006.285.18:57:00.87#ibcon#about to read 4, iclass 12, count 2 2006.285.18:57:00.87#ibcon#read 4, iclass 12, count 2 2006.285.18:57:00.87#ibcon#about to read 5, iclass 12, count 2 2006.285.18:57:00.87#ibcon#read 5, iclass 12, count 2 2006.285.18:57:00.87#ibcon#about to read 6, iclass 12, count 2 2006.285.18:57:00.87#ibcon#read 6, iclass 12, count 2 2006.285.18:57:00.87#ibcon#end of sib2, iclass 12, count 2 2006.285.18:57:00.87#ibcon#*after write, iclass 12, count 2 2006.285.18:57:00.87#ibcon#*before return 0, iclass 12, count 2 2006.285.18:57:00.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:57:00.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.18:57:00.87#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.18:57:00.87#ibcon#ireg 7 cls_cnt 0 2006.285.18:57:00.87#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:57:00.99#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:57:00.99#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:57:00.99#ibcon#enter wrdev, iclass 12, count 0 2006.285.18:57:00.99#ibcon#first serial, iclass 12, count 0 2006.285.18:57:00.99#ibcon#enter sib2, iclass 12, count 0 2006.285.18:57:00.99#ibcon#flushed, iclass 12, count 0 2006.285.18:57:00.99#ibcon#about to write, iclass 12, count 0 2006.285.18:57:00.99#ibcon#wrote, iclass 12, count 0 2006.285.18:57:00.99#ibcon#about to read 3, iclass 12, count 0 2006.285.18:57:01.01#ibcon#read 3, iclass 12, count 0 2006.285.18:57:01.01#ibcon#about to read 4, iclass 12, count 0 2006.285.18:57:01.01#ibcon#read 4, iclass 12, count 0 2006.285.18:57:01.01#ibcon#about to read 5, iclass 12, count 0 2006.285.18:57:01.01#ibcon#read 5, iclass 12, count 0 2006.285.18:57:01.01#ibcon#about to read 6, iclass 12, count 0 2006.285.18:57:01.01#ibcon#read 6, iclass 12, count 0 2006.285.18:57:01.01#ibcon#end of sib2, iclass 12, count 0 2006.285.18:57:01.01#ibcon#*mode == 0, iclass 12, count 0 2006.285.18:57:01.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.18:57:01.01#ibcon#[27=USB\r\n] 2006.285.18:57:01.01#ibcon#*before write, iclass 12, count 0 2006.285.18:57:01.01#ibcon#enter sib2, iclass 12, count 0 2006.285.18:57:01.01#ibcon#flushed, iclass 12, count 0 2006.285.18:57:01.01#ibcon#about to write, iclass 12, count 0 2006.285.18:57:01.02#ibcon#wrote, iclass 12, count 0 2006.285.18:57:01.02#ibcon#about to read 3, iclass 12, count 0 2006.285.18:57:01.04#ibcon#read 3, iclass 12, count 0 2006.285.18:57:01.04#ibcon#about to read 4, iclass 12, count 0 2006.285.18:57:01.04#ibcon#read 4, iclass 12, count 0 2006.285.18:57:01.04#ibcon#about to read 5, iclass 12, count 0 2006.285.18:57:01.04#ibcon#read 5, iclass 12, count 0 2006.285.18:57:01.04#ibcon#about to read 6, iclass 12, count 0 2006.285.18:57:01.04#ibcon#read 6, iclass 12, count 0 2006.285.18:57:01.04#ibcon#end of sib2, iclass 12, count 0 2006.285.18:57:01.04#ibcon#*after write, iclass 12, count 0 2006.285.18:57:01.04#ibcon#*before return 0, iclass 12, count 0 2006.285.18:57:01.04#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:57:01.04#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.18:57:01.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.18:57:01.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.18:57:01.04$vck44/vblo=5,709.99 2006.285.18:57:01.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.18:57:01.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.18:57:01.05#ibcon#ireg 17 cls_cnt 0 2006.285.18:57:01.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:57:01.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:57:01.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:57:01.05#ibcon#enter wrdev, iclass 14, count 0 2006.285.18:57:01.05#ibcon#first serial, iclass 14, count 0 2006.285.18:57:01.05#ibcon#enter sib2, iclass 14, count 0 2006.285.18:57:01.05#ibcon#flushed, iclass 14, count 0 2006.285.18:57:01.05#ibcon#about to write, iclass 14, count 0 2006.285.18:57:01.05#ibcon#wrote, iclass 14, count 0 2006.285.18:57:01.05#ibcon#about to read 3, iclass 14, count 0 2006.285.18:57:01.06#ibcon#read 3, iclass 14, count 0 2006.285.18:57:01.06#ibcon#about to read 4, iclass 14, count 0 2006.285.18:57:01.06#ibcon#read 4, iclass 14, count 0 2006.285.18:57:01.06#ibcon#about to read 5, iclass 14, count 0 2006.285.18:57:01.06#ibcon#read 5, iclass 14, count 0 2006.285.18:57:01.06#ibcon#about to read 6, iclass 14, count 0 2006.285.18:57:01.06#ibcon#read 6, iclass 14, count 0 2006.285.18:57:01.06#ibcon#end of sib2, iclass 14, count 0 2006.285.18:57:01.06#ibcon#*mode == 0, iclass 14, count 0 2006.285.18:57:01.06#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.18:57:01.06#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.18:57:01.06#ibcon#*before write, iclass 14, count 0 2006.285.18:57:01.06#ibcon#enter sib2, iclass 14, count 0 2006.285.18:57:01.06#ibcon#flushed, iclass 14, count 0 2006.285.18:57:01.06#ibcon#about to write, iclass 14, count 0 2006.285.18:57:01.06#ibcon#wrote, iclass 14, count 0 2006.285.18:57:01.06#ibcon#about to read 3, iclass 14, count 0 2006.285.18:57:01.10#ibcon#read 3, iclass 14, count 0 2006.285.18:57:01.10#ibcon#about to read 4, iclass 14, count 0 2006.285.18:57:01.10#ibcon#read 4, iclass 14, count 0 2006.285.18:57:01.10#ibcon#about to read 5, iclass 14, count 0 2006.285.18:57:01.10#ibcon#read 5, iclass 14, count 0 2006.285.18:57:01.10#ibcon#about to read 6, iclass 14, count 0 2006.285.18:57:01.10#ibcon#read 6, iclass 14, count 0 2006.285.18:57:01.10#ibcon#end of sib2, iclass 14, count 0 2006.285.18:57:01.10#ibcon#*after write, iclass 14, count 0 2006.285.18:57:01.10#ibcon#*before return 0, iclass 14, count 0 2006.285.18:57:01.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:57:01.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.18:57:01.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.18:57:01.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.18:57:01.10$vck44/vb=5,4 2006.285.18:57:01.11#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.18:57:01.11#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.18:57:01.11#ibcon#ireg 11 cls_cnt 2 2006.285.18:57:01.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:57:01.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:57:01.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:57:01.15#ibcon#enter wrdev, iclass 16, count 2 2006.285.18:57:01.15#ibcon#first serial, iclass 16, count 2 2006.285.18:57:01.15#ibcon#enter sib2, iclass 16, count 2 2006.285.18:57:01.15#ibcon#flushed, iclass 16, count 2 2006.285.18:57:01.15#ibcon#about to write, iclass 16, count 2 2006.285.18:57:01.15#ibcon#wrote, iclass 16, count 2 2006.285.18:57:01.15#ibcon#about to read 3, iclass 16, count 2 2006.285.18:57:01.17#ibcon#read 3, iclass 16, count 2 2006.285.18:57:01.17#ibcon#about to read 4, iclass 16, count 2 2006.285.18:57:01.17#ibcon#read 4, iclass 16, count 2 2006.285.18:57:01.17#ibcon#about to read 5, iclass 16, count 2 2006.285.18:57:01.17#ibcon#read 5, iclass 16, count 2 2006.285.18:57:01.17#ibcon#about to read 6, iclass 16, count 2 2006.285.18:57:01.17#ibcon#read 6, iclass 16, count 2 2006.285.18:57:01.17#ibcon#end of sib2, iclass 16, count 2 2006.285.18:57:01.17#ibcon#*mode == 0, iclass 16, count 2 2006.285.18:57:01.17#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.18:57:01.17#ibcon#[27=AT05-04\r\n] 2006.285.18:57:01.17#ibcon#*before write, iclass 16, count 2 2006.285.18:57:01.17#ibcon#enter sib2, iclass 16, count 2 2006.285.18:57:01.17#ibcon#flushed, iclass 16, count 2 2006.285.18:57:01.17#ibcon#about to write, iclass 16, count 2 2006.285.18:57:01.17#ibcon#wrote, iclass 16, count 2 2006.285.18:57:01.17#ibcon#about to read 3, iclass 16, count 2 2006.285.18:57:01.20#ibcon#read 3, iclass 16, count 2 2006.285.18:57:01.20#ibcon#about to read 4, iclass 16, count 2 2006.285.18:57:01.20#ibcon#read 4, iclass 16, count 2 2006.285.18:57:01.20#ibcon#about to read 5, iclass 16, count 2 2006.285.18:57:01.20#ibcon#read 5, iclass 16, count 2 2006.285.18:57:01.20#ibcon#about to read 6, iclass 16, count 2 2006.285.18:57:01.20#ibcon#read 6, iclass 16, count 2 2006.285.18:57:01.20#ibcon#end of sib2, iclass 16, count 2 2006.285.18:57:01.20#ibcon#*after write, iclass 16, count 2 2006.285.18:57:01.20#ibcon#*before return 0, iclass 16, count 2 2006.285.18:57:01.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:57:01.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.18:57:01.20#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.18:57:01.20#ibcon#ireg 7 cls_cnt 0 2006.285.18:57:01.20#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:57:01.32#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:57:01.32#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:57:01.32#ibcon#enter wrdev, iclass 16, count 0 2006.285.18:57:01.32#ibcon#first serial, iclass 16, count 0 2006.285.18:57:01.32#ibcon#enter sib2, iclass 16, count 0 2006.285.18:57:01.32#ibcon#flushed, iclass 16, count 0 2006.285.18:57:01.32#ibcon#about to write, iclass 16, count 0 2006.285.18:57:01.32#ibcon#wrote, iclass 16, count 0 2006.285.18:57:01.32#ibcon#about to read 3, iclass 16, count 0 2006.285.18:57:01.34#ibcon#read 3, iclass 16, count 0 2006.285.18:57:01.34#ibcon#about to read 4, iclass 16, count 0 2006.285.18:57:01.34#ibcon#read 4, iclass 16, count 0 2006.285.18:57:01.34#ibcon#about to read 5, iclass 16, count 0 2006.285.18:57:01.34#ibcon#read 5, iclass 16, count 0 2006.285.18:57:01.34#ibcon#about to read 6, iclass 16, count 0 2006.285.18:57:01.34#ibcon#read 6, iclass 16, count 0 2006.285.18:57:01.34#ibcon#end of sib2, iclass 16, count 0 2006.285.18:57:01.34#ibcon#*mode == 0, iclass 16, count 0 2006.285.18:57:01.34#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.18:57:01.34#ibcon#[27=USB\r\n] 2006.285.18:57:01.34#ibcon#*before write, iclass 16, count 0 2006.285.18:57:01.34#ibcon#enter sib2, iclass 16, count 0 2006.285.18:57:01.34#ibcon#flushed, iclass 16, count 0 2006.285.18:57:01.34#ibcon#about to write, iclass 16, count 0 2006.285.18:57:01.34#ibcon#wrote, iclass 16, count 0 2006.285.18:57:01.34#ibcon#about to read 3, iclass 16, count 0 2006.285.18:57:01.37#ibcon#read 3, iclass 16, count 0 2006.285.18:57:01.37#ibcon#about to read 4, iclass 16, count 0 2006.285.18:57:01.37#ibcon#read 4, iclass 16, count 0 2006.285.18:57:01.37#ibcon#about to read 5, iclass 16, count 0 2006.285.18:57:01.37#ibcon#read 5, iclass 16, count 0 2006.285.18:57:01.37#ibcon#about to read 6, iclass 16, count 0 2006.285.18:57:01.37#ibcon#read 6, iclass 16, count 0 2006.285.18:57:01.37#ibcon#end of sib2, iclass 16, count 0 2006.285.18:57:01.37#ibcon#*after write, iclass 16, count 0 2006.285.18:57:01.37#ibcon#*before return 0, iclass 16, count 0 2006.285.18:57:01.37#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:57:01.37#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.18:57:01.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.18:57:01.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.18:57:01.37$vck44/vblo=6,719.99 2006.285.18:57:01.38#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.18:57:01.38#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.18:57:01.38#ibcon#ireg 17 cls_cnt 0 2006.285.18:57:01.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:57:01.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:57:01.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:57:01.38#ibcon#enter wrdev, iclass 18, count 0 2006.285.18:57:01.38#ibcon#first serial, iclass 18, count 0 2006.285.18:57:01.38#ibcon#enter sib2, iclass 18, count 0 2006.285.18:57:01.38#ibcon#flushed, iclass 18, count 0 2006.285.18:57:01.38#ibcon#about to write, iclass 18, count 0 2006.285.18:57:01.38#ibcon#wrote, iclass 18, count 0 2006.285.18:57:01.38#ibcon#about to read 3, iclass 18, count 0 2006.285.18:57:01.39#ibcon#read 3, iclass 18, count 0 2006.285.18:57:01.39#ibcon#about to read 4, iclass 18, count 0 2006.285.18:57:01.39#ibcon#read 4, iclass 18, count 0 2006.285.18:57:01.39#ibcon#about to read 5, iclass 18, count 0 2006.285.18:57:01.39#ibcon#read 5, iclass 18, count 0 2006.285.18:57:01.39#ibcon#about to read 6, iclass 18, count 0 2006.285.18:57:01.39#ibcon#read 6, iclass 18, count 0 2006.285.18:57:01.39#ibcon#end of sib2, iclass 18, count 0 2006.285.18:57:01.39#ibcon#*mode == 0, iclass 18, count 0 2006.285.18:57:01.39#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.18:57:01.39#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.18:57:01.39#ibcon#*before write, iclass 18, count 0 2006.285.18:57:01.39#ibcon#enter sib2, iclass 18, count 0 2006.285.18:57:01.39#ibcon#flushed, iclass 18, count 0 2006.285.18:57:01.39#ibcon#about to write, iclass 18, count 0 2006.285.18:57:01.39#ibcon#wrote, iclass 18, count 0 2006.285.18:57:01.39#ibcon#about to read 3, iclass 18, count 0 2006.285.18:57:01.43#ibcon#read 3, iclass 18, count 0 2006.285.18:57:01.43#ibcon#about to read 4, iclass 18, count 0 2006.285.18:57:01.43#ibcon#read 4, iclass 18, count 0 2006.285.18:57:01.43#ibcon#about to read 5, iclass 18, count 0 2006.285.18:57:01.43#ibcon#read 5, iclass 18, count 0 2006.285.18:57:01.43#ibcon#about to read 6, iclass 18, count 0 2006.285.18:57:01.43#ibcon#read 6, iclass 18, count 0 2006.285.18:57:01.43#ibcon#end of sib2, iclass 18, count 0 2006.285.18:57:01.43#ibcon#*after write, iclass 18, count 0 2006.285.18:57:01.43#ibcon#*before return 0, iclass 18, count 0 2006.285.18:57:01.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:57:01.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.18:57:01.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.18:57:01.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.18:57:01.43$vck44/vb=6,3 2006.285.18:57:01.44#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.18:57:01.44#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.18:57:01.44#ibcon#ireg 11 cls_cnt 2 2006.285.18:57:01.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:57:01.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:57:01.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:57:01.48#ibcon#enter wrdev, iclass 20, count 2 2006.285.18:57:01.48#ibcon#first serial, iclass 20, count 2 2006.285.18:57:01.48#ibcon#enter sib2, iclass 20, count 2 2006.285.18:57:01.48#ibcon#flushed, iclass 20, count 2 2006.285.18:57:01.48#ibcon#about to write, iclass 20, count 2 2006.285.18:57:01.48#ibcon#wrote, iclass 20, count 2 2006.285.18:57:01.48#ibcon#about to read 3, iclass 20, count 2 2006.285.18:57:01.50#ibcon#read 3, iclass 20, count 2 2006.285.18:57:01.50#ibcon#about to read 4, iclass 20, count 2 2006.285.18:57:01.50#ibcon#read 4, iclass 20, count 2 2006.285.18:57:01.50#ibcon#about to read 5, iclass 20, count 2 2006.285.18:57:01.50#ibcon#read 5, iclass 20, count 2 2006.285.18:57:01.50#ibcon#about to read 6, iclass 20, count 2 2006.285.18:57:01.50#ibcon#read 6, iclass 20, count 2 2006.285.18:57:01.50#ibcon#end of sib2, iclass 20, count 2 2006.285.18:57:01.50#ibcon#*mode == 0, iclass 20, count 2 2006.285.18:57:01.50#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.18:57:01.50#ibcon#[27=AT06-03\r\n] 2006.285.18:57:01.50#ibcon#*before write, iclass 20, count 2 2006.285.18:57:01.50#ibcon#enter sib2, iclass 20, count 2 2006.285.18:57:01.50#ibcon#flushed, iclass 20, count 2 2006.285.18:57:01.50#ibcon#about to write, iclass 20, count 2 2006.285.18:57:01.50#ibcon#wrote, iclass 20, count 2 2006.285.18:57:01.50#ibcon#about to read 3, iclass 20, count 2 2006.285.18:57:01.53#ibcon#read 3, iclass 20, count 2 2006.285.18:57:01.53#ibcon#about to read 4, iclass 20, count 2 2006.285.18:57:01.53#ibcon#read 4, iclass 20, count 2 2006.285.18:57:01.53#ibcon#about to read 5, iclass 20, count 2 2006.285.18:57:01.53#ibcon#read 5, iclass 20, count 2 2006.285.18:57:01.53#ibcon#about to read 6, iclass 20, count 2 2006.285.18:57:01.53#ibcon#read 6, iclass 20, count 2 2006.285.18:57:01.53#ibcon#end of sib2, iclass 20, count 2 2006.285.18:57:01.53#ibcon#*after write, iclass 20, count 2 2006.285.18:57:01.53#ibcon#*before return 0, iclass 20, count 2 2006.285.18:57:01.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:57:01.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.18:57:01.53#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.18:57:01.53#ibcon#ireg 7 cls_cnt 0 2006.285.18:57:01.53#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:57:01.65#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:57:01.65#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:57:01.65#ibcon#enter wrdev, iclass 20, count 0 2006.285.18:57:01.65#ibcon#first serial, iclass 20, count 0 2006.285.18:57:01.65#ibcon#enter sib2, iclass 20, count 0 2006.285.18:57:01.65#ibcon#flushed, iclass 20, count 0 2006.285.18:57:01.65#ibcon#about to write, iclass 20, count 0 2006.285.18:57:01.65#ibcon#wrote, iclass 20, count 0 2006.285.18:57:01.65#ibcon#about to read 3, iclass 20, count 0 2006.285.18:57:01.67#ibcon#read 3, iclass 20, count 0 2006.285.18:57:01.67#ibcon#about to read 4, iclass 20, count 0 2006.285.18:57:01.67#ibcon#read 4, iclass 20, count 0 2006.285.18:57:01.67#ibcon#about to read 5, iclass 20, count 0 2006.285.18:57:01.67#ibcon#read 5, iclass 20, count 0 2006.285.18:57:01.67#ibcon#about to read 6, iclass 20, count 0 2006.285.18:57:01.67#ibcon#read 6, iclass 20, count 0 2006.285.18:57:01.67#ibcon#end of sib2, iclass 20, count 0 2006.285.18:57:01.67#ibcon#*mode == 0, iclass 20, count 0 2006.285.18:57:01.67#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.18:57:01.67#ibcon#[27=USB\r\n] 2006.285.18:57:01.67#ibcon#*before write, iclass 20, count 0 2006.285.18:57:01.67#ibcon#enter sib2, iclass 20, count 0 2006.285.18:57:01.67#ibcon#flushed, iclass 20, count 0 2006.285.18:57:01.67#ibcon#about to write, iclass 20, count 0 2006.285.18:57:01.67#ibcon#wrote, iclass 20, count 0 2006.285.18:57:01.67#ibcon#about to read 3, iclass 20, count 0 2006.285.18:57:01.70#ibcon#read 3, iclass 20, count 0 2006.285.18:57:01.70#ibcon#about to read 4, iclass 20, count 0 2006.285.18:57:01.70#ibcon#read 4, iclass 20, count 0 2006.285.18:57:01.70#ibcon#about to read 5, iclass 20, count 0 2006.285.18:57:01.70#ibcon#read 5, iclass 20, count 0 2006.285.18:57:01.70#ibcon#about to read 6, iclass 20, count 0 2006.285.18:57:01.70#ibcon#read 6, iclass 20, count 0 2006.285.18:57:01.70#ibcon#end of sib2, iclass 20, count 0 2006.285.18:57:01.70#ibcon#*after write, iclass 20, count 0 2006.285.18:57:01.70#ibcon#*before return 0, iclass 20, count 0 2006.285.18:57:01.70#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:57:01.70#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.18:57:01.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.18:57:01.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.18:57:01.70$vck44/vblo=7,734.99 2006.285.18:57:01.71#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.18:57:01.71#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.18:57:01.71#ibcon#ireg 17 cls_cnt 0 2006.285.18:57:01.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:57:01.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:57:01.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:57:01.71#ibcon#enter wrdev, iclass 22, count 0 2006.285.18:57:01.71#ibcon#first serial, iclass 22, count 0 2006.285.18:57:01.71#ibcon#enter sib2, iclass 22, count 0 2006.285.18:57:01.71#ibcon#flushed, iclass 22, count 0 2006.285.18:57:01.71#ibcon#about to write, iclass 22, count 0 2006.285.18:57:01.71#ibcon#wrote, iclass 22, count 0 2006.285.18:57:01.71#ibcon#about to read 3, iclass 22, count 0 2006.285.18:57:01.72#ibcon#read 3, iclass 22, count 0 2006.285.18:57:01.74#ibcon#about to read 4, iclass 22, count 0 2006.285.18:57:01.74#ibcon#read 4, iclass 22, count 0 2006.285.18:57:01.74#ibcon#about to read 5, iclass 22, count 0 2006.285.18:57:01.74#ibcon#read 5, iclass 22, count 0 2006.285.18:57:01.74#ibcon#about to read 6, iclass 22, count 0 2006.285.18:57:01.74#ibcon#read 6, iclass 22, count 0 2006.285.18:57:01.74#ibcon#end of sib2, iclass 22, count 0 2006.285.18:57:01.74#ibcon#*mode == 0, iclass 22, count 0 2006.285.18:57:01.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.18:57:01.74#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.18:57:01.74#ibcon#*before write, iclass 22, count 0 2006.285.18:57:01.74#ibcon#enter sib2, iclass 22, count 0 2006.285.18:57:01.74#ibcon#flushed, iclass 22, count 0 2006.285.18:57:01.74#ibcon#about to write, iclass 22, count 0 2006.285.18:57:01.74#ibcon#wrote, iclass 22, count 0 2006.285.18:57:01.74#ibcon#about to read 3, iclass 22, count 0 2006.285.18:57:01.77#ibcon#read 3, iclass 22, count 0 2006.285.18:57:01.77#ibcon#about to read 4, iclass 22, count 0 2006.285.18:57:01.77#ibcon#read 4, iclass 22, count 0 2006.285.18:57:01.77#ibcon#about to read 5, iclass 22, count 0 2006.285.18:57:01.77#ibcon#read 5, iclass 22, count 0 2006.285.18:57:01.77#ibcon#about to read 6, iclass 22, count 0 2006.285.18:57:01.77#ibcon#read 6, iclass 22, count 0 2006.285.18:57:01.77#ibcon#end of sib2, iclass 22, count 0 2006.285.18:57:01.77#ibcon#*after write, iclass 22, count 0 2006.285.18:57:01.77#ibcon#*before return 0, iclass 22, count 0 2006.285.18:57:01.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:57:01.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.18:57:01.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.18:57:01.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.18:57:01.77$vck44/vb=7,4 2006.285.18:57:01.78#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.18:57:01.78#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.18:57:01.78#ibcon#ireg 11 cls_cnt 2 2006.285.18:57:01.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:57:01.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:57:01.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:57:01.81#ibcon#enter wrdev, iclass 24, count 2 2006.285.18:57:01.81#ibcon#first serial, iclass 24, count 2 2006.285.18:57:01.81#ibcon#enter sib2, iclass 24, count 2 2006.285.18:57:01.81#ibcon#flushed, iclass 24, count 2 2006.285.18:57:01.81#ibcon#about to write, iclass 24, count 2 2006.285.18:57:01.81#ibcon#wrote, iclass 24, count 2 2006.285.18:57:01.81#ibcon#about to read 3, iclass 24, count 2 2006.285.18:57:01.83#ibcon#read 3, iclass 24, count 2 2006.285.18:57:01.83#ibcon#about to read 4, iclass 24, count 2 2006.285.18:57:01.83#ibcon#read 4, iclass 24, count 2 2006.285.18:57:01.83#ibcon#about to read 5, iclass 24, count 2 2006.285.18:57:01.83#ibcon#read 5, iclass 24, count 2 2006.285.18:57:01.83#ibcon#about to read 6, iclass 24, count 2 2006.285.18:57:01.83#ibcon#read 6, iclass 24, count 2 2006.285.18:57:01.83#ibcon#end of sib2, iclass 24, count 2 2006.285.18:57:01.83#ibcon#*mode == 0, iclass 24, count 2 2006.285.18:57:01.83#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.18:57:01.83#ibcon#[27=AT07-04\r\n] 2006.285.18:57:01.83#ibcon#*before write, iclass 24, count 2 2006.285.18:57:01.83#ibcon#enter sib2, iclass 24, count 2 2006.285.18:57:01.83#ibcon#flushed, iclass 24, count 2 2006.285.18:57:01.83#ibcon#about to write, iclass 24, count 2 2006.285.18:57:01.83#ibcon#wrote, iclass 24, count 2 2006.285.18:57:01.83#ibcon#about to read 3, iclass 24, count 2 2006.285.18:57:01.86#ibcon#read 3, iclass 24, count 2 2006.285.18:57:01.86#ibcon#about to read 4, iclass 24, count 2 2006.285.18:57:01.86#ibcon#read 4, iclass 24, count 2 2006.285.18:57:01.86#ibcon#about to read 5, iclass 24, count 2 2006.285.18:57:01.86#ibcon#read 5, iclass 24, count 2 2006.285.18:57:01.86#ibcon#about to read 6, iclass 24, count 2 2006.285.18:57:01.86#ibcon#read 6, iclass 24, count 2 2006.285.18:57:01.86#ibcon#end of sib2, iclass 24, count 2 2006.285.18:57:01.86#ibcon#*after write, iclass 24, count 2 2006.285.18:57:01.86#ibcon#*before return 0, iclass 24, count 2 2006.285.18:57:01.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:57:01.86#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.18:57:01.86#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.18:57:01.86#ibcon#ireg 7 cls_cnt 0 2006.285.18:57:01.86#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:57:01.98#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:57:01.98#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:57:01.98#ibcon#enter wrdev, iclass 24, count 0 2006.285.18:57:01.98#ibcon#first serial, iclass 24, count 0 2006.285.18:57:01.98#ibcon#enter sib2, iclass 24, count 0 2006.285.18:57:01.98#ibcon#flushed, iclass 24, count 0 2006.285.18:57:01.98#ibcon#about to write, iclass 24, count 0 2006.285.18:57:01.98#ibcon#wrote, iclass 24, count 0 2006.285.18:57:01.98#ibcon#about to read 3, iclass 24, count 0 2006.285.18:57:02.00#ibcon#read 3, iclass 24, count 0 2006.285.18:57:02.00#ibcon#about to read 4, iclass 24, count 0 2006.285.18:57:02.00#ibcon#read 4, iclass 24, count 0 2006.285.18:57:02.00#ibcon#about to read 5, iclass 24, count 0 2006.285.18:57:02.00#ibcon#read 5, iclass 24, count 0 2006.285.18:57:02.00#ibcon#about to read 6, iclass 24, count 0 2006.285.18:57:02.00#ibcon#read 6, iclass 24, count 0 2006.285.18:57:02.00#ibcon#end of sib2, iclass 24, count 0 2006.285.18:57:02.00#ibcon#*mode == 0, iclass 24, count 0 2006.285.18:57:02.00#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.18:57:02.00#ibcon#[27=USB\r\n] 2006.285.18:57:02.00#ibcon#*before write, iclass 24, count 0 2006.285.18:57:02.00#ibcon#enter sib2, iclass 24, count 0 2006.285.18:57:02.00#ibcon#flushed, iclass 24, count 0 2006.285.18:57:02.00#ibcon#about to write, iclass 24, count 0 2006.285.18:57:02.00#ibcon#wrote, iclass 24, count 0 2006.285.18:57:02.00#ibcon#about to read 3, iclass 24, count 0 2006.285.18:57:02.03#ibcon#read 3, iclass 24, count 0 2006.285.18:57:02.03#ibcon#about to read 4, iclass 24, count 0 2006.285.18:57:02.03#ibcon#read 4, iclass 24, count 0 2006.285.18:57:02.03#ibcon#about to read 5, iclass 24, count 0 2006.285.18:57:02.03#ibcon#read 5, iclass 24, count 0 2006.285.18:57:02.03#ibcon#about to read 6, iclass 24, count 0 2006.285.18:57:02.03#ibcon#read 6, iclass 24, count 0 2006.285.18:57:02.03#ibcon#end of sib2, iclass 24, count 0 2006.285.18:57:02.03#ibcon#*after write, iclass 24, count 0 2006.285.18:57:02.03#ibcon#*before return 0, iclass 24, count 0 2006.285.18:57:02.03#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:57:02.03#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.18:57:02.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.18:57:02.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.18:57:02.03$vck44/vblo=8,744.99 2006.285.18:57:02.04#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.18:57:02.04#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.18:57:02.04#ibcon#ireg 17 cls_cnt 0 2006.285.18:57:02.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:57:02.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:57:02.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:57:02.04#ibcon#enter wrdev, iclass 26, count 0 2006.285.18:57:02.04#ibcon#first serial, iclass 26, count 0 2006.285.18:57:02.04#ibcon#enter sib2, iclass 26, count 0 2006.285.18:57:02.04#ibcon#flushed, iclass 26, count 0 2006.285.18:57:02.04#ibcon#about to write, iclass 26, count 0 2006.285.18:57:02.04#ibcon#wrote, iclass 26, count 0 2006.285.18:57:02.04#ibcon#about to read 3, iclass 26, count 0 2006.285.18:57:02.05#ibcon#read 3, iclass 26, count 0 2006.285.18:57:02.05#ibcon#about to read 4, iclass 26, count 0 2006.285.18:57:02.05#ibcon#read 4, iclass 26, count 0 2006.285.18:57:02.05#ibcon#about to read 5, iclass 26, count 0 2006.285.18:57:02.05#ibcon#read 5, iclass 26, count 0 2006.285.18:57:02.05#ibcon#about to read 6, iclass 26, count 0 2006.285.18:57:02.05#ibcon#read 6, iclass 26, count 0 2006.285.18:57:02.05#ibcon#end of sib2, iclass 26, count 0 2006.285.18:57:02.05#ibcon#*mode == 0, iclass 26, count 0 2006.285.18:57:02.05#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.18:57:02.05#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.18:57:02.05#ibcon#*before write, iclass 26, count 0 2006.285.18:57:02.05#ibcon#enter sib2, iclass 26, count 0 2006.285.18:57:02.05#ibcon#flushed, iclass 26, count 0 2006.285.18:57:02.05#ibcon#about to write, iclass 26, count 0 2006.285.18:57:02.05#ibcon#wrote, iclass 26, count 0 2006.285.18:57:02.05#ibcon#about to read 3, iclass 26, count 0 2006.285.18:57:02.09#ibcon#read 3, iclass 26, count 0 2006.285.18:57:02.09#ibcon#about to read 4, iclass 26, count 0 2006.285.18:57:02.09#ibcon#read 4, iclass 26, count 0 2006.285.18:57:02.09#ibcon#about to read 5, iclass 26, count 0 2006.285.18:57:02.09#ibcon#read 5, iclass 26, count 0 2006.285.18:57:02.09#ibcon#about to read 6, iclass 26, count 0 2006.285.18:57:02.09#ibcon#read 6, iclass 26, count 0 2006.285.18:57:02.09#ibcon#end of sib2, iclass 26, count 0 2006.285.18:57:02.09#ibcon#*after write, iclass 26, count 0 2006.285.18:57:02.09#ibcon#*before return 0, iclass 26, count 0 2006.285.18:57:02.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:57:02.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.18:57:02.09#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.18:57:02.09#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.18:57:02.09$vck44/vb=8,4 2006.285.18:57:02.10#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.18:57:02.10#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.18:57:02.10#ibcon#ireg 11 cls_cnt 2 2006.285.18:57:02.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:57:02.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:57:02.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:57:02.15#ibcon#enter wrdev, iclass 28, count 2 2006.285.18:57:02.15#ibcon#first serial, iclass 28, count 2 2006.285.18:57:02.15#ibcon#enter sib2, iclass 28, count 2 2006.285.18:57:02.15#ibcon#flushed, iclass 28, count 2 2006.285.18:57:02.15#ibcon#about to write, iclass 28, count 2 2006.285.18:57:02.15#ibcon#wrote, iclass 28, count 2 2006.285.18:57:02.15#ibcon#about to read 3, iclass 28, count 2 2006.285.18:57:02.16#ibcon#read 3, iclass 28, count 2 2006.285.18:57:02.16#ibcon#about to read 4, iclass 28, count 2 2006.285.18:57:02.16#ibcon#read 4, iclass 28, count 2 2006.285.18:57:02.16#ibcon#about to read 5, iclass 28, count 2 2006.285.18:57:02.16#ibcon#read 5, iclass 28, count 2 2006.285.18:57:02.16#ibcon#about to read 6, iclass 28, count 2 2006.285.18:57:02.16#ibcon#read 6, iclass 28, count 2 2006.285.18:57:02.16#ibcon#end of sib2, iclass 28, count 2 2006.285.18:57:02.16#ibcon#*mode == 0, iclass 28, count 2 2006.285.18:57:02.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.18:57:02.16#ibcon#[27=AT08-04\r\n] 2006.285.18:57:02.16#ibcon#*before write, iclass 28, count 2 2006.285.18:57:02.16#ibcon#enter sib2, iclass 28, count 2 2006.285.18:57:02.16#ibcon#flushed, iclass 28, count 2 2006.285.18:57:02.16#ibcon#about to write, iclass 28, count 2 2006.285.18:57:02.16#ibcon#wrote, iclass 28, count 2 2006.285.18:57:02.16#ibcon#about to read 3, iclass 28, count 2 2006.285.18:57:02.19#ibcon#read 3, iclass 28, count 2 2006.285.18:57:02.19#ibcon#about to read 4, iclass 28, count 2 2006.285.18:57:02.19#ibcon#read 4, iclass 28, count 2 2006.285.18:57:02.19#ibcon#about to read 5, iclass 28, count 2 2006.285.18:57:02.19#ibcon#read 5, iclass 28, count 2 2006.285.18:57:02.19#ibcon#about to read 6, iclass 28, count 2 2006.285.18:57:02.19#ibcon#read 6, iclass 28, count 2 2006.285.18:57:02.19#ibcon#end of sib2, iclass 28, count 2 2006.285.18:57:02.19#ibcon#*after write, iclass 28, count 2 2006.285.18:57:02.19#ibcon#*before return 0, iclass 28, count 2 2006.285.18:57:02.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:57:02.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.18:57:02.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.18:57:02.19#ibcon#ireg 7 cls_cnt 0 2006.285.18:57:02.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:57:02.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:57:02.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:57:02.31#ibcon#enter wrdev, iclass 28, count 0 2006.285.18:57:02.31#ibcon#first serial, iclass 28, count 0 2006.285.18:57:02.31#ibcon#enter sib2, iclass 28, count 0 2006.285.18:57:02.31#ibcon#flushed, iclass 28, count 0 2006.285.18:57:02.31#ibcon#about to write, iclass 28, count 0 2006.285.18:57:02.31#ibcon#wrote, iclass 28, count 0 2006.285.18:57:02.31#ibcon#about to read 3, iclass 28, count 0 2006.285.18:57:02.33#ibcon#read 3, iclass 28, count 0 2006.285.18:57:02.33#ibcon#about to read 4, iclass 28, count 0 2006.285.18:57:02.33#ibcon#read 4, iclass 28, count 0 2006.285.18:57:02.33#ibcon#about to read 5, iclass 28, count 0 2006.285.18:57:02.33#ibcon#read 5, iclass 28, count 0 2006.285.18:57:02.33#ibcon#about to read 6, iclass 28, count 0 2006.285.18:57:02.33#ibcon#read 6, iclass 28, count 0 2006.285.18:57:02.33#ibcon#end of sib2, iclass 28, count 0 2006.285.18:57:02.33#ibcon#*mode == 0, iclass 28, count 0 2006.285.18:57:02.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.18:57:02.33#ibcon#[27=USB\r\n] 2006.285.18:57:02.33#ibcon#*before write, iclass 28, count 0 2006.285.18:57:02.33#ibcon#enter sib2, iclass 28, count 0 2006.285.18:57:02.33#ibcon#flushed, iclass 28, count 0 2006.285.18:57:02.33#ibcon#about to write, iclass 28, count 0 2006.285.18:57:02.33#ibcon#wrote, iclass 28, count 0 2006.285.18:57:02.33#ibcon#about to read 3, iclass 28, count 0 2006.285.18:57:02.36#ibcon#read 3, iclass 28, count 0 2006.285.18:57:02.36#ibcon#about to read 4, iclass 28, count 0 2006.285.18:57:02.36#ibcon#read 4, iclass 28, count 0 2006.285.18:57:02.36#ibcon#about to read 5, iclass 28, count 0 2006.285.18:57:02.36#ibcon#read 5, iclass 28, count 0 2006.285.18:57:02.36#ibcon#about to read 6, iclass 28, count 0 2006.285.18:57:02.36#ibcon#read 6, iclass 28, count 0 2006.285.18:57:02.36#ibcon#end of sib2, iclass 28, count 0 2006.285.18:57:02.36#ibcon#*after write, iclass 28, count 0 2006.285.18:57:02.36#ibcon#*before return 0, iclass 28, count 0 2006.285.18:57:02.36#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:57:02.36#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.18:57:02.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.18:57:02.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.18:57:02.36$vck44/vabw=wide 2006.285.18:57:02.37#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.18:57:02.37#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.18:57:02.37#ibcon#ireg 8 cls_cnt 0 2006.285.18:57:02.37#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:57:02.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:57:02.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:57:02.37#ibcon#enter wrdev, iclass 30, count 0 2006.285.18:57:02.37#ibcon#first serial, iclass 30, count 0 2006.285.18:57:02.37#ibcon#enter sib2, iclass 30, count 0 2006.285.18:57:02.37#ibcon#flushed, iclass 30, count 0 2006.285.18:57:02.37#ibcon#about to write, iclass 30, count 0 2006.285.18:57:02.37#ibcon#wrote, iclass 30, count 0 2006.285.18:57:02.37#ibcon#about to read 3, iclass 30, count 0 2006.285.18:57:02.38#ibcon#read 3, iclass 30, count 0 2006.285.18:57:02.38#ibcon#about to read 4, iclass 30, count 0 2006.285.18:57:02.38#ibcon#read 4, iclass 30, count 0 2006.285.18:57:02.38#ibcon#about to read 5, iclass 30, count 0 2006.285.18:57:02.38#ibcon#read 5, iclass 30, count 0 2006.285.18:57:02.38#ibcon#about to read 6, iclass 30, count 0 2006.285.18:57:02.38#ibcon#read 6, iclass 30, count 0 2006.285.18:57:02.38#ibcon#end of sib2, iclass 30, count 0 2006.285.18:57:02.38#ibcon#*mode == 0, iclass 30, count 0 2006.285.18:57:02.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.18:57:02.38#ibcon#[25=BW32\r\n] 2006.285.18:57:02.38#ibcon#*before write, iclass 30, count 0 2006.285.18:57:02.38#ibcon#enter sib2, iclass 30, count 0 2006.285.18:57:02.38#ibcon#flushed, iclass 30, count 0 2006.285.18:57:02.38#ibcon#about to write, iclass 30, count 0 2006.285.18:57:02.38#ibcon#wrote, iclass 30, count 0 2006.285.18:57:02.38#ibcon#about to read 3, iclass 30, count 0 2006.285.18:57:02.41#ibcon#read 3, iclass 30, count 0 2006.285.18:57:02.41#ibcon#about to read 4, iclass 30, count 0 2006.285.18:57:02.41#ibcon#read 4, iclass 30, count 0 2006.285.18:57:02.41#ibcon#about to read 5, iclass 30, count 0 2006.285.18:57:02.41#ibcon#read 5, iclass 30, count 0 2006.285.18:57:02.41#ibcon#about to read 6, iclass 30, count 0 2006.285.18:57:02.41#ibcon#read 6, iclass 30, count 0 2006.285.18:57:02.41#ibcon#end of sib2, iclass 30, count 0 2006.285.18:57:02.41#ibcon#*after write, iclass 30, count 0 2006.285.18:57:02.41#ibcon#*before return 0, iclass 30, count 0 2006.285.18:57:02.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:57:02.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.18:57:02.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.18:57:02.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.18:57:02.41$vck44/vbbw=wide 2006.285.18:57:02.41#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.18:57:02.42#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.18:57:02.42#ibcon#ireg 8 cls_cnt 0 2006.285.18:57:02.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:57:02.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:57:02.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:57:02.47#ibcon#enter wrdev, iclass 32, count 0 2006.285.18:57:02.47#ibcon#first serial, iclass 32, count 0 2006.285.18:57:02.47#ibcon#enter sib2, iclass 32, count 0 2006.285.18:57:02.47#ibcon#flushed, iclass 32, count 0 2006.285.18:57:02.47#ibcon#about to write, iclass 32, count 0 2006.285.18:57:02.47#ibcon#wrote, iclass 32, count 0 2006.285.18:57:02.47#ibcon#about to read 3, iclass 32, count 0 2006.285.18:57:02.49#ibcon#read 3, iclass 32, count 0 2006.285.18:57:02.49#ibcon#about to read 4, iclass 32, count 0 2006.285.18:57:02.49#ibcon#read 4, iclass 32, count 0 2006.285.18:57:02.49#ibcon#about to read 5, iclass 32, count 0 2006.285.18:57:02.49#ibcon#read 5, iclass 32, count 0 2006.285.18:57:02.49#ibcon#about to read 6, iclass 32, count 0 2006.285.18:57:02.49#ibcon#read 6, iclass 32, count 0 2006.285.18:57:02.49#ibcon#end of sib2, iclass 32, count 0 2006.285.18:57:02.49#ibcon#*mode == 0, iclass 32, count 0 2006.285.18:57:02.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.18:57:02.49#ibcon#[27=BW32\r\n] 2006.285.18:57:02.49#ibcon#*before write, iclass 32, count 0 2006.285.18:57:02.49#ibcon#enter sib2, iclass 32, count 0 2006.285.18:57:02.49#ibcon#flushed, iclass 32, count 0 2006.285.18:57:02.49#ibcon#about to write, iclass 32, count 0 2006.285.18:57:02.49#ibcon#wrote, iclass 32, count 0 2006.285.18:57:02.49#ibcon#about to read 3, iclass 32, count 0 2006.285.18:57:02.52#ibcon#read 3, iclass 32, count 0 2006.285.18:57:02.52#ibcon#about to read 4, iclass 32, count 0 2006.285.18:57:02.52#ibcon#read 4, iclass 32, count 0 2006.285.18:57:02.52#ibcon#about to read 5, iclass 32, count 0 2006.285.18:57:02.52#ibcon#read 5, iclass 32, count 0 2006.285.18:57:02.52#ibcon#about to read 6, iclass 32, count 0 2006.285.18:57:02.52#ibcon#read 6, iclass 32, count 0 2006.285.18:57:02.52#ibcon#end of sib2, iclass 32, count 0 2006.285.18:57:02.52#ibcon#*after write, iclass 32, count 0 2006.285.18:57:02.52#ibcon#*before return 0, iclass 32, count 0 2006.285.18:57:02.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:57:02.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.18:57:02.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.18:57:02.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.18:57:02.53$setupk4/ifdk4 2006.285.18:57:02.53$ifdk4/lo= 2006.285.18:57:02.53$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.18:57:02.53$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.18:57:02.53$ifdk4/patch= 2006.285.18:57:02.53$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.18:57:02.53$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.18:57:02.53$setupk4/!*+20s 2006.285.18:57:05.08#abcon#<5=/13 0.3 1.3 15.101001014.9\r\n> 2006.285.18:57:05.10#abcon#{5=INTERFACE CLEAR} 2006.285.18:57:05.16#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:57:15.39#abcon#<5=/13 0.3 1.3 15.101001014.9\r\n> 2006.285.18:57:15.41#abcon#{5=INTERFACE CLEAR} 2006.285.18:57:15.47#abcon#[5=S1D000X0/0*\r\n] 2006.285.18:57:16.42$setupk4/"tpicd 2006.285.18:57:16.42$setupk4/echo=off 2006.285.18:57:16.42$setupk4/xlog=off 2006.285.18:57:16.42:!2006.285.19:04:01 2006.285.18:57:42.14#trakl#Source acquired 2006.285.18:57:42.14#flagr#flagr/antenna,acquired 2006.285.19:04:01.00:preob 2006.285.19:04:01.14/onsource/TRACKING 2006.285.19:04:01.14:!2006.285.19:04:11 2006.285.19:04:11.00:"tape 2006.285.19:04:11.00:"st=record 2006.285.19:04:11.00:data_valid=on 2006.285.19:04:11.00:midob 2006.285.19:04:12.14/onsource/TRACKING 2006.285.19:04:12.14/wx/15.08,1014.9,100 2006.285.19:04:12.19/cable/+6.5054E-03 2006.285.19:04:13.28/va/01,07,usb,yes,32,35 2006.285.19:04:13.28/va/02,06,usb,yes,32,33 2006.285.19:04:13.28/va/03,07,usb,yes,32,34 2006.285.19:04:13.28/va/04,06,usb,yes,33,35 2006.285.19:04:13.28/va/05,03,usb,yes,33,33 2006.285.19:04:13.28/va/06,04,usb,yes,30,29 2006.285.19:04:13.28/va/07,04,usb,yes,30,31 2006.285.19:04:13.28/va/08,03,usb,yes,31,37 2006.285.19:04:13.51/valo/01,524.99,yes,locked 2006.285.19:04:13.51/valo/02,534.99,yes,locked 2006.285.19:04:13.51/valo/03,564.99,yes,locked 2006.285.19:04:13.51/valo/04,624.99,yes,locked 2006.285.19:04:13.51/valo/05,734.99,yes,locked 2006.285.19:04:13.51/valo/06,814.99,yes,locked 2006.285.19:04:13.51/valo/07,864.99,yes,locked 2006.285.19:04:13.51/valo/08,884.99,yes,locked 2006.285.19:04:14.60/vb/01,04,usb,yes,30,28 2006.285.19:04:14.60/vb/02,05,usb,yes,28,28 2006.285.19:04:14.60/vb/03,04,usb,yes,29,32 2006.285.19:04:14.60/vb/04,05,usb,yes,30,29 2006.285.19:04:14.60/vb/05,04,usb,yes,26,29 2006.285.19:04:14.60/vb/06,03,usb,yes,38,33 2006.285.19:04:14.60/vb/07,04,usb,yes,30,30 2006.285.19:04:14.60/vb/08,04,usb,yes,28,31 2006.285.19:04:14.84/vblo/01,629.99,yes,locked 2006.285.19:04:14.84/vblo/02,634.99,yes,locked 2006.285.19:04:14.84/vblo/03,649.99,yes,locked 2006.285.19:04:14.84/vblo/04,679.99,yes,locked 2006.285.19:04:14.84/vblo/05,709.99,yes,locked 2006.285.19:04:14.84/vblo/06,719.99,yes,locked 2006.285.19:04:14.84/vblo/07,734.99,yes,locked 2006.285.19:04:14.84/vblo/08,744.99,yes,locked 2006.285.19:04:14.99/vabw/8 2006.285.19:04:15.14/vbbw/8 2006.285.19:04:15.32/xfe/off,on,12.0 2006.285.19:04:15.71/ifatt/23,28,28,28 2006.285.19:04:16.07/fmout-gps/S +2.69E-07 2006.285.19:04:16.09:!2006.285.19:06:01 2006.285.19:06:01.01:data_valid=off 2006.285.19:06:01.01:"et 2006.285.19:06:01.01:!+3s 2006.285.19:06:04.02:"tape 2006.285.19:06:04.02:postob 2006.285.19:06:04.11/cable/+6.5062E-03 2006.285.19:06:04.11/wx/15.02,1014.9,100 2006.285.19:06:04.17/fmout-gps/S +2.65E-07 2006.285.19:06:04.17:scan_name=285-1909,jd0610,60 2006.285.19:06:04.17:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.285.19:06:05.14#flagr#flagr/antenna,new-source 2006.285.19:06:05.14:checkk5 2006.285.19:06:05.68/chk_autoobs//k5ts1/ autoobs is running! 2006.285.19:06:06.18/chk_autoobs//k5ts2/ autoobs is running! 2006.285.19:06:06.67/chk_autoobs//k5ts3/ autoobs is running! 2006.285.19:06:07.12/chk_autoobs//k5ts4/ autoobs is running! 2006.285.19:06:07.49/chk_obsdata//k5ts1/T2851904??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.19:06:07.90/chk_obsdata//k5ts2/T2851904??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.19:06:08.40/chk_obsdata//k5ts3/T2851904??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.19:06:08.78/chk_obsdata//k5ts4/T2851904??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.285.19:06:09.58/k5log//k5ts1_log_newline 2006.285.19:06:10.36/k5log//k5ts2_log_newline 2006.285.19:06:11.35/k5log//k5ts3_log_newline 2006.285.19:06:12.11/k5log//k5ts4_log_newline 2006.285.19:06:12.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.19:06:12.13:setupk4=1 2006.285.19:06:12.13$setupk4/echo=on 2006.285.19:06:12.13$setupk4/pcalon 2006.285.19:06:12.13$pcalon/"no phase cal control is implemented here 2006.285.19:06:12.13$setupk4/"tpicd=stop 2006.285.19:06:12.13$setupk4/"rec=synch_on 2006.285.19:06:12.13$setupk4/"rec_mode=128 2006.285.19:06:12.13$setupk4/!* 2006.285.19:06:12.13$setupk4/recpk4 2006.285.19:06:12.13$recpk4/recpatch= 2006.285.19:06:12.13$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.19:06:12.13$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.19:06:12.13$setupk4/vck44 2006.285.19:06:12.13$vck44/valo=1,524.99 2006.285.19:06:12.13#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.19:06:12.13#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.19:06:12.13#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:12.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:06:12.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:06:12.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:06:12.13#ibcon#enter wrdev, iclass 37, count 0 2006.285.19:06:12.13#ibcon#first serial, iclass 37, count 0 2006.285.19:06:12.13#ibcon#enter sib2, iclass 37, count 0 2006.285.19:06:12.13#ibcon#flushed, iclass 37, count 0 2006.285.19:06:12.13#ibcon#about to write, iclass 37, count 0 2006.285.19:06:12.13#ibcon#wrote, iclass 37, count 0 2006.285.19:06:12.13#ibcon#about to read 3, iclass 37, count 0 2006.285.19:06:12.15#ibcon#read 3, iclass 37, count 0 2006.285.19:06:12.15#ibcon#about to read 4, iclass 37, count 0 2006.285.19:06:12.15#ibcon#read 4, iclass 37, count 0 2006.285.19:06:12.15#ibcon#about to read 5, iclass 37, count 0 2006.285.19:06:12.15#ibcon#read 5, iclass 37, count 0 2006.285.19:06:12.15#ibcon#about to read 6, iclass 37, count 0 2006.285.19:06:12.15#ibcon#read 6, iclass 37, count 0 2006.285.19:06:12.15#ibcon#end of sib2, iclass 37, count 0 2006.285.19:06:12.15#ibcon#*mode == 0, iclass 37, count 0 2006.285.19:06:12.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.19:06:12.15#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.19:06:12.15#ibcon#*before write, iclass 37, count 0 2006.285.19:06:12.15#ibcon#enter sib2, iclass 37, count 0 2006.285.19:06:12.15#ibcon#flushed, iclass 37, count 0 2006.285.19:06:12.15#ibcon#about to write, iclass 37, count 0 2006.285.19:06:12.15#ibcon#wrote, iclass 37, count 0 2006.285.19:06:12.15#ibcon#about to read 3, iclass 37, count 0 2006.285.19:06:12.20#ibcon#read 3, iclass 37, count 0 2006.285.19:06:12.20#ibcon#about to read 4, iclass 37, count 0 2006.285.19:06:12.20#ibcon#read 4, iclass 37, count 0 2006.285.19:06:12.20#ibcon#about to read 5, iclass 37, count 0 2006.285.19:06:12.20#ibcon#read 5, iclass 37, count 0 2006.285.19:06:12.20#ibcon#about to read 6, iclass 37, count 0 2006.285.19:06:12.20#ibcon#read 6, iclass 37, count 0 2006.285.19:06:12.20#ibcon#end of sib2, iclass 37, count 0 2006.285.19:06:12.20#ibcon#*after write, iclass 37, count 0 2006.285.19:06:12.20#ibcon#*before return 0, iclass 37, count 0 2006.285.19:06:12.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:06:12.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:06:12.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.19:06:12.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.19:06:12.20$vck44/va=1,7 2006.285.19:06:12.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.19:06:12.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.19:06:12.20#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:12.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:06:12.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:06:12.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:06:12.20#ibcon#enter wrdev, iclass 39, count 2 2006.285.19:06:12.20#ibcon#first serial, iclass 39, count 2 2006.285.19:06:12.20#ibcon#enter sib2, iclass 39, count 2 2006.285.19:06:12.20#ibcon#flushed, iclass 39, count 2 2006.285.19:06:12.20#ibcon#about to write, iclass 39, count 2 2006.285.19:06:12.20#ibcon#wrote, iclass 39, count 2 2006.285.19:06:12.20#ibcon#about to read 3, iclass 39, count 2 2006.285.19:06:12.22#ibcon#read 3, iclass 39, count 2 2006.285.19:06:12.22#ibcon#about to read 4, iclass 39, count 2 2006.285.19:06:12.22#ibcon#read 4, iclass 39, count 2 2006.285.19:06:12.22#ibcon#about to read 5, iclass 39, count 2 2006.285.19:06:12.22#ibcon#read 5, iclass 39, count 2 2006.285.19:06:12.22#ibcon#about to read 6, iclass 39, count 2 2006.285.19:06:12.22#ibcon#read 6, iclass 39, count 2 2006.285.19:06:12.22#ibcon#end of sib2, iclass 39, count 2 2006.285.19:06:12.22#ibcon#*mode == 0, iclass 39, count 2 2006.285.19:06:12.22#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.19:06:12.22#ibcon#[25=AT01-07\r\n] 2006.285.19:06:12.22#ibcon#*before write, iclass 39, count 2 2006.285.19:06:12.22#ibcon#enter sib2, iclass 39, count 2 2006.285.19:06:12.22#ibcon#flushed, iclass 39, count 2 2006.285.19:06:12.22#ibcon#about to write, iclass 39, count 2 2006.285.19:06:12.22#ibcon#wrote, iclass 39, count 2 2006.285.19:06:12.22#ibcon#about to read 3, iclass 39, count 2 2006.285.19:06:12.25#ibcon#read 3, iclass 39, count 2 2006.285.19:06:12.25#ibcon#about to read 4, iclass 39, count 2 2006.285.19:06:12.25#ibcon#read 4, iclass 39, count 2 2006.285.19:06:12.25#ibcon#about to read 5, iclass 39, count 2 2006.285.19:06:12.25#ibcon#read 5, iclass 39, count 2 2006.285.19:06:12.25#ibcon#about to read 6, iclass 39, count 2 2006.285.19:06:12.25#ibcon#read 6, iclass 39, count 2 2006.285.19:06:12.25#ibcon#end of sib2, iclass 39, count 2 2006.285.19:06:12.25#ibcon#*after write, iclass 39, count 2 2006.285.19:06:12.25#ibcon#*before return 0, iclass 39, count 2 2006.285.19:06:12.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:06:12.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:06:12.25#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.19:06:12.25#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:12.25#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:06:12.37#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:06:12.37#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:06:12.37#ibcon#enter wrdev, iclass 39, count 0 2006.285.19:06:12.37#ibcon#first serial, iclass 39, count 0 2006.285.19:06:12.37#ibcon#enter sib2, iclass 39, count 0 2006.285.19:06:12.37#ibcon#flushed, iclass 39, count 0 2006.285.19:06:12.37#ibcon#about to write, iclass 39, count 0 2006.285.19:06:12.37#ibcon#wrote, iclass 39, count 0 2006.285.19:06:12.37#ibcon#about to read 3, iclass 39, count 0 2006.285.19:06:12.39#ibcon#read 3, iclass 39, count 0 2006.285.19:06:12.39#ibcon#about to read 4, iclass 39, count 0 2006.285.19:06:12.39#ibcon#read 4, iclass 39, count 0 2006.285.19:06:12.39#ibcon#about to read 5, iclass 39, count 0 2006.285.19:06:12.39#ibcon#read 5, iclass 39, count 0 2006.285.19:06:12.39#ibcon#about to read 6, iclass 39, count 0 2006.285.19:06:12.39#ibcon#read 6, iclass 39, count 0 2006.285.19:06:12.39#ibcon#end of sib2, iclass 39, count 0 2006.285.19:06:12.39#ibcon#*mode == 0, iclass 39, count 0 2006.285.19:06:12.39#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.19:06:12.39#ibcon#[25=USB\r\n] 2006.285.19:06:12.39#ibcon#*before write, iclass 39, count 0 2006.285.19:06:12.39#ibcon#enter sib2, iclass 39, count 0 2006.285.19:06:12.39#ibcon#flushed, iclass 39, count 0 2006.285.19:06:12.39#ibcon#about to write, iclass 39, count 0 2006.285.19:06:12.39#ibcon#wrote, iclass 39, count 0 2006.285.19:06:12.39#ibcon#about to read 3, iclass 39, count 0 2006.285.19:06:12.42#ibcon#read 3, iclass 39, count 0 2006.285.19:06:12.42#ibcon#about to read 4, iclass 39, count 0 2006.285.19:06:12.42#ibcon#read 4, iclass 39, count 0 2006.285.19:06:12.42#ibcon#about to read 5, iclass 39, count 0 2006.285.19:06:12.42#ibcon#read 5, iclass 39, count 0 2006.285.19:06:12.42#ibcon#about to read 6, iclass 39, count 0 2006.285.19:06:12.42#ibcon#read 6, iclass 39, count 0 2006.285.19:06:12.42#ibcon#end of sib2, iclass 39, count 0 2006.285.19:06:12.42#ibcon#*after write, iclass 39, count 0 2006.285.19:06:12.42#ibcon#*before return 0, iclass 39, count 0 2006.285.19:06:12.42#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:06:12.42#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:06:12.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.19:06:12.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.19:06:12.42$vck44/valo=2,534.99 2006.285.19:06:12.42#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.19:06:12.42#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.19:06:12.42#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:12.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:06:12.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:06:12.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:06:12.42#ibcon#enter wrdev, iclass 3, count 0 2006.285.19:06:12.42#ibcon#first serial, iclass 3, count 0 2006.285.19:06:12.42#ibcon#enter sib2, iclass 3, count 0 2006.285.19:06:12.42#ibcon#flushed, iclass 3, count 0 2006.285.19:06:12.42#ibcon#about to write, iclass 3, count 0 2006.285.19:06:12.42#ibcon#wrote, iclass 3, count 0 2006.285.19:06:12.42#ibcon#about to read 3, iclass 3, count 0 2006.285.19:06:12.44#ibcon#read 3, iclass 3, count 0 2006.285.19:06:12.44#ibcon#about to read 4, iclass 3, count 0 2006.285.19:06:12.44#ibcon#read 4, iclass 3, count 0 2006.285.19:06:12.44#ibcon#about to read 5, iclass 3, count 0 2006.285.19:06:12.44#ibcon#read 5, iclass 3, count 0 2006.285.19:06:12.44#ibcon#about to read 6, iclass 3, count 0 2006.285.19:06:12.44#ibcon#read 6, iclass 3, count 0 2006.285.19:06:12.44#ibcon#end of sib2, iclass 3, count 0 2006.285.19:06:12.44#ibcon#*mode == 0, iclass 3, count 0 2006.285.19:06:12.44#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.19:06:12.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.19:06:12.44#ibcon#*before write, iclass 3, count 0 2006.285.19:06:12.44#ibcon#enter sib2, iclass 3, count 0 2006.285.19:06:12.44#ibcon#flushed, iclass 3, count 0 2006.285.19:06:12.44#ibcon#about to write, iclass 3, count 0 2006.285.19:06:12.44#ibcon#wrote, iclass 3, count 0 2006.285.19:06:12.44#ibcon#about to read 3, iclass 3, count 0 2006.285.19:06:12.48#ibcon#read 3, iclass 3, count 0 2006.285.19:06:12.48#ibcon#about to read 4, iclass 3, count 0 2006.285.19:06:12.48#ibcon#read 4, iclass 3, count 0 2006.285.19:06:12.48#ibcon#about to read 5, iclass 3, count 0 2006.285.19:06:12.48#ibcon#read 5, iclass 3, count 0 2006.285.19:06:12.48#ibcon#about to read 6, iclass 3, count 0 2006.285.19:06:12.48#ibcon#read 6, iclass 3, count 0 2006.285.19:06:12.48#ibcon#end of sib2, iclass 3, count 0 2006.285.19:06:12.48#ibcon#*after write, iclass 3, count 0 2006.285.19:06:12.48#ibcon#*before return 0, iclass 3, count 0 2006.285.19:06:12.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:06:12.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:06:12.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.19:06:12.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.19:06:12.48$vck44/va=2,6 2006.285.19:06:12.48#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.19:06:12.48#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.19:06:12.48#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:12.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:06:12.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:06:12.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:06:12.54#ibcon#enter wrdev, iclass 5, count 2 2006.285.19:06:12.54#ibcon#first serial, iclass 5, count 2 2006.285.19:06:12.54#ibcon#enter sib2, iclass 5, count 2 2006.285.19:06:12.54#ibcon#flushed, iclass 5, count 2 2006.285.19:06:12.54#ibcon#about to write, iclass 5, count 2 2006.285.19:06:12.54#ibcon#wrote, iclass 5, count 2 2006.285.19:06:12.54#ibcon#about to read 3, iclass 5, count 2 2006.285.19:06:12.56#ibcon#read 3, iclass 5, count 2 2006.285.19:06:12.56#ibcon#about to read 4, iclass 5, count 2 2006.285.19:06:12.56#ibcon#read 4, iclass 5, count 2 2006.285.19:06:12.56#ibcon#about to read 5, iclass 5, count 2 2006.285.19:06:12.56#ibcon#read 5, iclass 5, count 2 2006.285.19:06:12.56#ibcon#about to read 6, iclass 5, count 2 2006.285.19:06:12.56#ibcon#read 6, iclass 5, count 2 2006.285.19:06:12.56#ibcon#end of sib2, iclass 5, count 2 2006.285.19:06:12.56#ibcon#*mode == 0, iclass 5, count 2 2006.285.19:06:12.56#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.19:06:12.56#ibcon#[25=AT02-06\r\n] 2006.285.19:06:12.56#ibcon#*before write, iclass 5, count 2 2006.285.19:06:12.56#ibcon#enter sib2, iclass 5, count 2 2006.285.19:06:12.56#ibcon#flushed, iclass 5, count 2 2006.285.19:06:12.56#ibcon#about to write, iclass 5, count 2 2006.285.19:06:12.56#ibcon#wrote, iclass 5, count 2 2006.285.19:06:12.56#ibcon#about to read 3, iclass 5, count 2 2006.285.19:06:12.59#ibcon#read 3, iclass 5, count 2 2006.285.19:06:12.59#ibcon#about to read 4, iclass 5, count 2 2006.285.19:06:12.59#ibcon#read 4, iclass 5, count 2 2006.285.19:06:12.59#ibcon#about to read 5, iclass 5, count 2 2006.285.19:06:12.59#ibcon#read 5, iclass 5, count 2 2006.285.19:06:12.59#ibcon#about to read 6, iclass 5, count 2 2006.285.19:06:12.59#ibcon#read 6, iclass 5, count 2 2006.285.19:06:12.59#ibcon#end of sib2, iclass 5, count 2 2006.285.19:06:12.59#ibcon#*after write, iclass 5, count 2 2006.285.19:06:12.59#ibcon#*before return 0, iclass 5, count 2 2006.285.19:06:12.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:06:12.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:06:12.59#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.19:06:12.59#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:12.59#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:06:12.71#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:06:12.71#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:06:12.71#ibcon#enter wrdev, iclass 5, count 0 2006.285.19:06:12.71#ibcon#first serial, iclass 5, count 0 2006.285.19:06:12.71#ibcon#enter sib2, iclass 5, count 0 2006.285.19:06:12.71#ibcon#flushed, iclass 5, count 0 2006.285.19:06:12.71#ibcon#about to write, iclass 5, count 0 2006.285.19:06:12.71#ibcon#wrote, iclass 5, count 0 2006.285.19:06:12.71#ibcon#about to read 3, iclass 5, count 0 2006.285.19:06:12.73#ibcon#read 3, iclass 5, count 0 2006.285.19:06:12.73#ibcon#about to read 4, iclass 5, count 0 2006.285.19:06:12.73#ibcon#read 4, iclass 5, count 0 2006.285.19:06:12.73#ibcon#about to read 5, iclass 5, count 0 2006.285.19:06:12.73#ibcon#read 5, iclass 5, count 0 2006.285.19:06:12.73#ibcon#about to read 6, iclass 5, count 0 2006.285.19:06:12.73#ibcon#read 6, iclass 5, count 0 2006.285.19:06:12.73#ibcon#end of sib2, iclass 5, count 0 2006.285.19:06:12.73#ibcon#*mode == 0, iclass 5, count 0 2006.285.19:06:12.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.19:06:12.73#ibcon#[25=USB\r\n] 2006.285.19:06:12.73#ibcon#*before write, iclass 5, count 0 2006.285.19:06:12.73#ibcon#enter sib2, iclass 5, count 0 2006.285.19:06:12.73#ibcon#flushed, iclass 5, count 0 2006.285.19:06:12.73#ibcon#about to write, iclass 5, count 0 2006.285.19:06:12.73#ibcon#wrote, iclass 5, count 0 2006.285.19:06:12.73#ibcon#about to read 3, iclass 5, count 0 2006.285.19:06:12.76#ibcon#read 3, iclass 5, count 0 2006.285.19:06:12.76#ibcon#about to read 4, iclass 5, count 0 2006.285.19:06:12.76#ibcon#read 4, iclass 5, count 0 2006.285.19:06:12.76#ibcon#about to read 5, iclass 5, count 0 2006.285.19:06:12.76#ibcon#read 5, iclass 5, count 0 2006.285.19:06:12.76#ibcon#about to read 6, iclass 5, count 0 2006.285.19:06:12.76#ibcon#read 6, iclass 5, count 0 2006.285.19:06:12.76#ibcon#end of sib2, iclass 5, count 0 2006.285.19:06:12.76#ibcon#*after write, iclass 5, count 0 2006.285.19:06:12.76#ibcon#*before return 0, iclass 5, count 0 2006.285.19:06:12.76#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:06:12.76#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:06:12.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.19:06:12.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.19:06:12.76$vck44/valo=3,564.99 2006.285.19:06:12.76#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.19:06:12.76#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.19:06:12.76#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:12.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:06:12.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:06:12.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:06:12.76#ibcon#enter wrdev, iclass 7, count 0 2006.285.19:06:12.76#ibcon#first serial, iclass 7, count 0 2006.285.19:06:12.76#ibcon#enter sib2, iclass 7, count 0 2006.285.19:06:12.76#ibcon#flushed, iclass 7, count 0 2006.285.19:06:12.76#ibcon#about to write, iclass 7, count 0 2006.285.19:06:12.76#ibcon#wrote, iclass 7, count 0 2006.285.19:06:12.76#ibcon#about to read 3, iclass 7, count 0 2006.285.19:06:12.78#ibcon#read 3, iclass 7, count 0 2006.285.19:06:12.78#ibcon#about to read 4, iclass 7, count 0 2006.285.19:06:12.78#ibcon#read 4, iclass 7, count 0 2006.285.19:06:12.78#ibcon#about to read 5, iclass 7, count 0 2006.285.19:06:12.78#ibcon#read 5, iclass 7, count 0 2006.285.19:06:12.78#ibcon#about to read 6, iclass 7, count 0 2006.285.19:06:12.78#ibcon#read 6, iclass 7, count 0 2006.285.19:06:12.78#ibcon#end of sib2, iclass 7, count 0 2006.285.19:06:12.78#ibcon#*mode == 0, iclass 7, count 0 2006.285.19:06:12.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.19:06:12.78#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.19:06:12.78#ibcon#*before write, iclass 7, count 0 2006.285.19:06:12.78#ibcon#enter sib2, iclass 7, count 0 2006.285.19:06:12.78#ibcon#flushed, iclass 7, count 0 2006.285.19:06:12.78#ibcon#about to write, iclass 7, count 0 2006.285.19:06:12.78#ibcon#wrote, iclass 7, count 0 2006.285.19:06:12.78#ibcon#about to read 3, iclass 7, count 0 2006.285.19:06:12.82#ibcon#read 3, iclass 7, count 0 2006.285.19:06:12.82#ibcon#about to read 4, iclass 7, count 0 2006.285.19:06:12.82#ibcon#read 4, iclass 7, count 0 2006.285.19:06:12.82#ibcon#about to read 5, iclass 7, count 0 2006.285.19:06:12.82#ibcon#read 5, iclass 7, count 0 2006.285.19:06:12.82#ibcon#about to read 6, iclass 7, count 0 2006.285.19:06:12.82#ibcon#read 6, iclass 7, count 0 2006.285.19:06:12.82#ibcon#end of sib2, iclass 7, count 0 2006.285.19:06:12.82#ibcon#*after write, iclass 7, count 0 2006.285.19:06:12.82#ibcon#*before return 0, iclass 7, count 0 2006.285.19:06:12.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:06:12.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:06:12.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.19:06:12.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.19:06:12.82$vck44/va=3,7 2006.285.19:06:12.82#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.19:06:12.82#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.19:06:12.82#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:12.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:06:12.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:06:12.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:06:12.88#ibcon#enter wrdev, iclass 11, count 2 2006.285.19:06:12.88#ibcon#first serial, iclass 11, count 2 2006.285.19:06:12.88#ibcon#enter sib2, iclass 11, count 2 2006.285.19:06:12.88#ibcon#flushed, iclass 11, count 2 2006.285.19:06:12.88#ibcon#about to write, iclass 11, count 2 2006.285.19:06:12.88#ibcon#wrote, iclass 11, count 2 2006.285.19:06:12.88#ibcon#about to read 3, iclass 11, count 2 2006.285.19:06:12.90#ibcon#read 3, iclass 11, count 2 2006.285.19:06:12.90#ibcon#about to read 4, iclass 11, count 2 2006.285.19:06:12.90#ibcon#read 4, iclass 11, count 2 2006.285.19:06:12.90#ibcon#about to read 5, iclass 11, count 2 2006.285.19:06:12.90#ibcon#read 5, iclass 11, count 2 2006.285.19:06:12.90#ibcon#about to read 6, iclass 11, count 2 2006.285.19:06:12.90#ibcon#read 6, iclass 11, count 2 2006.285.19:06:12.90#ibcon#end of sib2, iclass 11, count 2 2006.285.19:06:12.90#ibcon#*mode == 0, iclass 11, count 2 2006.285.19:06:12.90#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.19:06:12.90#ibcon#[25=AT03-07\r\n] 2006.285.19:06:12.90#ibcon#*before write, iclass 11, count 2 2006.285.19:06:12.90#ibcon#enter sib2, iclass 11, count 2 2006.285.19:06:12.90#ibcon#flushed, iclass 11, count 2 2006.285.19:06:12.90#ibcon#about to write, iclass 11, count 2 2006.285.19:06:12.90#ibcon#wrote, iclass 11, count 2 2006.285.19:06:12.90#ibcon#about to read 3, iclass 11, count 2 2006.285.19:06:12.93#ibcon#read 3, iclass 11, count 2 2006.285.19:06:12.93#ibcon#about to read 4, iclass 11, count 2 2006.285.19:06:12.93#ibcon#read 4, iclass 11, count 2 2006.285.19:06:12.93#ibcon#about to read 5, iclass 11, count 2 2006.285.19:06:12.93#ibcon#read 5, iclass 11, count 2 2006.285.19:06:12.93#ibcon#about to read 6, iclass 11, count 2 2006.285.19:06:12.93#ibcon#read 6, iclass 11, count 2 2006.285.19:06:12.93#ibcon#end of sib2, iclass 11, count 2 2006.285.19:06:12.93#ibcon#*after write, iclass 11, count 2 2006.285.19:06:12.93#ibcon#*before return 0, iclass 11, count 2 2006.285.19:06:12.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:06:12.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:06:12.93#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.19:06:12.93#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:12.93#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:06:13.05#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:06:13.05#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:06:13.05#ibcon#enter wrdev, iclass 11, count 0 2006.285.19:06:13.05#ibcon#first serial, iclass 11, count 0 2006.285.19:06:13.05#ibcon#enter sib2, iclass 11, count 0 2006.285.19:06:13.05#ibcon#flushed, iclass 11, count 0 2006.285.19:06:13.05#ibcon#about to write, iclass 11, count 0 2006.285.19:06:13.05#ibcon#wrote, iclass 11, count 0 2006.285.19:06:13.05#ibcon#about to read 3, iclass 11, count 0 2006.285.19:06:13.07#ibcon#read 3, iclass 11, count 0 2006.285.19:06:13.07#ibcon#about to read 4, iclass 11, count 0 2006.285.19:06:13.07#ibcon#read 4, iclass 11, count 0 2006.285.19:06:13.07#ibcon#about to read 5, iclass 11, count 0 2006.285.19:06:13.07#ibcon#read 5, iclass 11, count 0 2006.285.19:06:13.07#ibcon#about to read 6, iclass 11, count 0 2006.285.19:06:13.07#ibcon#read 6, iclass 11, count 0 2006.285.19:06:13.07#ibcon#end of sib2, iclass 11, count 0 2006.285.19:06:13.07#ibcon#*mode == 0, iclass 11, count 0 2006.285.19:06:13.07#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.19:06:13.07#ibcon#[25=USB\r\n] 2006.285.19:06:13.07#ibcon#*before write, iclass 11, count 0 2006.285.19:06:13.07#ibcon#enter sib2, iclass 11, count 0 2006.285.19:06:13.07#ibcon#flushed, iclass 11, count 0 2006.285.19:06:13.07#ibcon#about to write, iclass 11, count 0 2006.285.19:06:13.07#ibcon#wrote, iclass 11, count 0 2006.285.19:06:13.07#ibcon#about to read 3, iclass 11, count 0 2006.285.19:06:13.10#ibcon#read 3, iclass 11, count 0 2006.285.19:06:13.10#ibcon#about to read 4, iclass 11, count 0 2006.285.19:06:13.10#ibcon#read 4, iclass 11, count 0 2006.285.19:06:13.10#ibcon#about to read 5, iclass 11, count 0 2006.285.19:06:13.10#ibcon#read 5, iclass 11, count 0 2006.285.19:06:13.10#ibcon#about to read 6, iclass 11, count 0 2006.285.19:06:13.10#ibcon#read 6, iclass 11, count 0 2006.285.19:06:13.10#ibcon#end of sib2, iclass 11, count 0 2006.285.19:06:13.10#ibcon#*after write, iclass 11, count 0 2006.285.19:06:13.10#ibcon#*before return 0, iclass 11, count 0 2006.285.19:06:13.10#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:06:13.10#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:06:13.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.19:06:13.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.19:06:13.10$vck44/valo=4,624.99 2006.285.19:06:13.10#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.19:06:13.10#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.19:06:13.10#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:13.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:06:13.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:06:13.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:06:13.10#ibcon#enter wrdev, iclass 13, count 0 2006.285.19:06:13.10#ibcon#first serial, iclass 13, count 0 2006.285.19:06:13.10#ibcon#enter sib2, iclass 13, count 0 2006.285.19:06:13.10#ibcon#flushed, iclass 13, count 0 2006.285.19:06:13.10#ibcon#about to write, iclass 13, count 0 2006.285.19:06:13.10#ibcon#wrote, iclass 13, count 0 2006.285.19:06:13.10#ibcon#about to read 3, iclass 13, count 0 2006.285.19:06:13.12#ibcon#read 3, iclass 13, count 0 2006.285.19:06:13.58#ibcon#about to read 4, iclass 13, count 0 2006.285.19:06:13.58#ibcon#read 4, iclass 13, count 0 2006.285.19:06:13.58#ibcon#about to read 5, iclass 13, count 0 2006.285.19:06:13.58#ibcon#read 5, iclass 13, count 0 2006.285.19:06:13.58#ibcon#about to read 6, iclass 13, count 0 2006.285.19:06:13.58#ibcon#read 6, iclass 13, count 0 2006.285.19:06:13.58#ibcon#end of sib2, iclass 13, count 0 2006.285.19:06:13.58#ibcon#*mode == 0, iclass 13, count 0 2006.285.19:06:13.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.19:06:13.58#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.19:06:13.58#ibcon#*before write, iclass 13, count 0 2006.285.19:06:13.58#ibcon#enter sib2, iclass 13, count 0 2006.285.19:06:13.58#ibcon#flushed, iclass 13, count 0 2006.285.19:06:13.58#ibcon#about to write, iclass 13, count 0 2006.285.19:06:13.58#ibcon#wrote, iclass 13, count 0 2006.285.19:06:13.58#ibcon#about to read 3, iclass 13, count 0 2006.285.19:06:13.61#ibcon#read 3, iclass 13, count 0 2006.285.19:06:13.61#ibcon#about to read 4, iclass 13, count 0 2006.285.19:06:13.61#ibcon#read 4, iclass 13, count 0 2006.285.19:06:13.61#ibcon#about to read 5, iclass 13, count 0 2006.285.19:06:13.61#ibcon#read 5, iclass 13, count 0 2006.285.19:06:13.61#ibcon#about to read 6, iclass 13, count 0 2006.285.19:06:13.61#ibcon#read 6, iclass 13, count 0 2006.285.19:06:13.61#ibcon#end of sib2, iclass 13, count 0 2006.285.19:06:13.61#ibcon#*after write, iclass 13, count 0 2006.285.19:06:13.61#ibcon#*before return 0, iclass 13, count 0 2006.285.19:06:13.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:06:13.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:06:13.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.19:06:13.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.19:06:13.61$vck44/va=4,6 2006.285.19:06:13.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.19:06:13.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.19:06:13.61#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:13.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:06:13.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:06:13.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:06:13.61#ibcon#enter wrdev, iclass 15, count 2 2006.285.19:06:13.61#ibcon#first serial, iclass 15, count 2 2006.285.19:06:13.61#ibcon#enter sib2, iclass 15, count 2 2006.285.19:06:13.61#ibcon#flushed, iclass 15, count 2 2006.285.19:06:13.61#ibcon#about to write, iclass 15, count 2 2006.285.19:06:13.61#ibcon#wrote, iclass 15, count 2 2006.285.19:06:13.61#ibcon#about to read 3, iclass 15, count 2 2006.285.19:06:13.63#ibcon#read 3, iclass 15, count 2 2006.285.19:06:13.63#ibcon#about to read 4, iclass 15, count 2 2006.285.19:06:13.63#ibcon#read 4, iclass 15, count 2 2006.285.19:06:13.63#ibcon#about to read 5, iclass 15, count 2 2006.285.19:06:13.63#ibcon#read 5, iclass 15, count 2 2006.285.19:06:13.63#ibcon#about to read 6, iclass 15, count 2 2006.285.19:06:13.63#ibcon#read 6, iclass 15, count 2 2006.285.19:06:13.63#ibcon#end of sib2, iclass 15, count 2 2006.285.19:06:13.63#ibcon#*mode == 0, iclass 15, count 2 2006.285.19:06:13.63#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.19:06:13.63#ibcon#[25=AT04-06\r\n] 2006.285.19:06:13.63#ibcon#*before write, iclass 15, count 2 2006.285.19:06:13.63#ibcon#enter sib2, iclass 15, count 2 2006.285.19:06:13.63#ibcon#flushed, iclass 15, count 2 2006.285.19:06:13.63#ibcon#about to write, iclass 15, count 2 2006.285.19:06:13.63#ibcon#wrote, iclass 15, count 2 2006.285.19:06:13.63#ibcon#about to read 3, iclass 15, count 2 2006.285.19:06:13.66#ibcon#read 3, iclass 15, count 2 2006.285.19:06:13.66#ibcon#about to read 4, iclass 15, count 2 2006.285.19:06:13.66#ibcon#read 4, iclass 15, count 2 2006.285.19:06:13.66#ibcon#about to read 5, iclass 15, count 2 2006.285.19:06:13.66#ibcon#read 5, iclass 15, count 2 2006.285.19:06:13.66#ibcon#about to read 6, iclass 15, count 2 2006.285.19:06:13.66#ibcon#read 6, iclass 15, count 2 2006.285.19:06:13.66#ibcon#end of sib2, iclass 15, count 2 2006.285.19:06:13.66#ibcon#*after write, iclass 15, count 2 2006.285.19:06:13.66#ibcon#*before return 0, iclass 15, count 2 2006.285.19:06:13.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:06:13.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:06:13.66#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.19:06:13.66#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:13.66#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:06:13.78#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:06:13.78#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:06:13.78#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:06:13.78#ibcon#first serial, iclass 15, count 0 2006.285.19:06:13.78#ibcon#enter sib2, iclass 15, count 0 2006.285.19:06:13.78#ibcon#flushed, iclass 15, count 0 2006.285.19:06:13.78#ibcon#about to write, iclass 15, count 0 2006.285.19:06:13.78#ibcon#wrote, iclass 15, count 0 2006.285.19:06:13.78#ibcon#about to read 3, iclass 15, count 0 2006.285.19:06:13.80#ibcon#read 3, iclass 15, count 0 2006.285.19:06:13.80#ibcon#about to read 4, iclass 15, count 0 2006.285.19:06:13.80#ibcon#read 4, iclass 15, count 0 2006.285.19:06:13.80#ibcon#about to read 5, iclass 15, count 0 2006.285.19:06:13.80#ibcon#read 5, iclass 15, count 0 2006.285.19:06:13.80#ibcon#about to read 6, iclass 15, count 0 2006.285.19:06:13.80#ibcon#read 6, iclass 15, count 0 2006.285.19:06:13.80#ibcon#end of sib2, iclass 15, count 0 2006.285.19:06:13.80#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:06:13.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:06:13.80#ibcon#[25=USB\r\n] 2006.285.19:06:13.80#ibcon#*before write, iclass 15, count 0 2006.285.19:06:13.80#ibcon#enter sib2, iclass 15, count 0 2006.285.19:06:13.80#ibcon#flushed, iclass 15, count 0 2006.285.19:06:13.80#ibcon#about to write, iclass 15, count 0 2006.285.19:06:13.80#ibcon#wrote, iclass 15, count 0 2006.285.19:06:13.80#ibcon#about to read 3, iclass 15, count 0 2006.285.19:06:13.83#ibcon#read 3, iclass 15, count 0 2006.285.19:06:13.83#ibcon#about to read 4, iclass 15, count 0 2006.285.19:06:13.83#ibcon#read 4, iclass 15, count 0 2006.285.19:06:13.83#ibcon#about to read 5, iclass 15, count 0 2006.285.19:06:13.83#ibcon#read 5, iclass 15, count 0 2006.285.19:06:13.83#ibcon#about to read 6, iclass 15, count 0 2006.285.19:06:13.83#ibcon#read 6, iclass 15, count 0 2006.285.19:06:13.83#ibcon#end of sib2, iclass 15, count 0 2006.285.19:06:13.83#ibcon#*after write, iclass 15, count 0 2006.285.19:06:13.83#ibcon#*before return 0, iclass 15, count 0 2006.285.19:06:13.83#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:06:13.83#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:06:13.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:06:13.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:06:13.83$vck44/valo=5,734.99 2006.285.19:06:13.83#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.19:06:13.83#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.19:06:13.83#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:13.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:06:13.83#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:06:13.83#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:06:13.83#ibcon#enter wrdev, iclass 17, count 0 2006.285.19:06:13.83#ibcon#first serial, iclass 17, count 0 2006.285.19:06:13.83#ibcon#enter sib2, iclass 17, count 0 2006.285.19:06:13.83#ibcon#flushed, iclass 17, count 0 2006.285.19:06:13.83#ibcon#about to write, iclass 17, count 0 2006.285.19:06:13.83#ibcon#wrote, iclass 17, count 0 2006.285.19:06:13.83#ibcon#about to read 3, iclass 17, count 0 2006.285.19:06:13.85#ibcon#read 3, iclass 17, count 0 2006.285.19:06:14.14#ibcon#about to read 4, iclass 17, count 0 2006.285.19:06:14.14#ibcon#read 4, iclass 17, count 0 2006.285.19:06:14.14#ibcon#about to read 5, iclass 17, count 0 2006.285.19:06:14.14#ibcon#read 5, iclass 17, count 0 2006.285.19:06:14.14#ibcon#about to read 6, iclass 17, count 0 2006.285.19:06:14.14#ibcon#read 6, iclass 17, count 0 2006.285.19:06:14.14#ibcon#end of sib2, iclass 17, count 0 2006.285.19:06:14.14#ibcon#*mode == 0, iclass 17, count 0 2006.285.19:06:14.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.19:06:14.14#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.19:06:14.14#ibcon#*before write, iclass 17, count 0 2006.285.19:06:14.14#ibcon#enter sib2, iclass 17, count 0 2006.285.19:06:14.14#ibcon#flushed, iclass 17, count 0 2006.285.19:06:14.14#ibcon#about to write, iclass 17, count 0 2006.285.19:06:14.14#ibcon#wrote, iclass 17, count 0 2006.285.19:06:14.14#ibcon#about to read 3, iclass 17, count 0 2006.285.19:06:14.18#ibcon#read 3, iclass 17, count 0 2006.285.19:06:14.18#ibcon#about to read 4, iclass 17, count 0 2006.285.19:06:14.18#ibcon#read 4, iclass 17, count 0 2006.285.19:06:14.18#ibcon#about to read 5, iclass 17, count 0 2006.285.19:06:14.18#ibcon#read 5, iclass 17, count 0 2006.285.19:06:14.18#ibcon#about to read 6, iclass 17, count 0 2006.285.19:06:14.18#ibcon#read 6, iclass 17, count 0 2006.285.19:06:14.18#ibcon#end of sib2, iclass 17, count 0 2006.285.19:06:14.18#ibcon#*after write, iclass 17, count 0 2006.285.19:06:14.18#ibcon#*before return 0, iclass 17, count 0 2006.285.19:06:14.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:06:14.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:06:14.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.19:06:14.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.19:06:14.18$vck44/va=5,3 2006.285.19:06:14.18#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.19:06:14.18#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.19:06:14.18#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:14.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:06:14.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:06:14.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:06:14.18#ibcon#enter wrdev, iclass 19, count 2 2006.285.19:06:14.18#ibcon#first serial, iclass 19, count 2 2006.285.19:06:14.18#ibcon#enter sib2, iclass 19, count 2 2006.285.19:06:14.18#ibcon#flushed, iclass 19, count 2 2006.285.19:06:14.18#ibcon#about to write, iclass 19, count 2 2006.285.19:06:14.18#ibcon#wrote, iclass 19, count 2 2006.285.19:06:14.18#ibcon#about to read 3, iclass 19, count 2 2006.285.19:06:14.20#ibcon#read 3, iclass 19, count 2 2006.285.19:06:14.20#ibcon#about to read 4, iclass 19, count 2 2006.285.19:06:14.20#ibcon#read 4, iclass 19, count 2 2006.285.19:06:14.20#ibcon#about to read 5, iclass 19, count 2 2006.285.19:06:14.20#ibcon#read 5, iclass 19, count 2 2006.285.19:06:14.20#ibcon#about to read 6, iclass 19, count 2 2006.285.19:06:14.20#ibcon#read 6, iclass 19, count 2 2006.285.19:06:14.20#ibcon#end of sib2, iclass 19, count 2 2006.285.19:06:14.20#ibcon#*mode == 0, iclass 19, count 2 2006.285.19:06:14.20#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.19:06:14.20#ibcon#[25=AT05-03\r\n] 2006.285.19:06:14.20#ibcon#*before write, iclass 19, count 2 2006.285.19:06:14.20#ibcon#enter sib2, iclass 19, count 2 2006.285.19:06:14.20#ibcon#flushed, iclass 19, count 2 2006.285.19:06:14.20#ibcon#about to write, iclass 19, count 2 2006.285.19:06:14.20#ibcon#wrote, iclass 19, count 2 2006.285.19:06:14.20#ibcon#about to read 3, iclass 19, count 2 2006.285.19:06:14.23#ibcon#read 3, iclass 19, count 2 2006.285.19:06:14.23#ibcon#about to read 4, iclass 19, count 2 2006.285.19:06:14.23#ibcon#read 4, iclass 19, count 2 2006.285.19:06:14.23#ibcon#about to read 5, iclass 19, count 2 2006.285.19:06:14.23#ibcon#read 5, iclass 19, count 2 2006.285.19:06:14.23#ibcon#about to read 6, iclass 19, count 2 2006.285.19:06:14.23#ibcon#read 6, iclass 19, count 2 2006.285.19:06:14.23#ibcon#end of sib2, iclass 19, count 2 2006.285.19:06:14.23#ibcon#*after write, iclass 19, count 2 2006.285.19:06:14.23#ibcon#*before return 0, iclass 19, count 2 2006.285.19:06:14.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:06:14.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:06:14.23#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.19:06:14.23#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:14.23#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:06:14.35#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:06:14.35#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:06:14.35#ibcon#enter wrdev, iclass 19, count 0 2006.285.19:06:14.35#ibcon#first serial, iclass 19, count 0 2006.285.19:06:14.35#ibcon#enter sib2, iclass 19, count 0 2006.285.19:06:14.35#ibcon#flushed, iclass 19, count 0 2006.285.19:06:14.35#ibcon#about to write, iclass 19, count 0 2006.285.19:06:14.35#ibcon#wrote, iclass 19, count 0 2006.285.19:06:14.35#ibcon#about to read 3, iclass 19, count 0 2006.285.19:06:14.37#ibcon#read 3, iclass 19, count 0 2006.285.19:06:14.37#ibcon#about to read 4, iclass 19, count 0 2006.285.19:06:14.37#ibcon#read 4, iclass 19, count 0 2006.285.19:06:14.37#ibcon#about to read 5, iclass 19, count 0 2006.285.19:06:14.37#ibcon#read 5, iclass 19, count 0 2006.285.19:06:14.37#ibcon#about to read 6, iclass 19, count 0 2006.285.19:06:14.37#ibcon#read 6, iclass 19, count 0 2006.285.19:06:14.37#ibcon#end of sib2, iclass 19, count 0 2006.285.19:06:14.37#ibcon#*mode == 0, iclass 19, count 0 2006.285.19:06:14.37#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.19:06:14.37#ibcon#[25=USB\r\n] 2006.285.19:06:14.37#ibcon#*before write, iclass 19, count 0 2006.285.19:06:14.37#ibcon#enter sib2, iclass 19, count 0 2006.285.19:06:14.37#ibcon#flushed, iclass 19, count 0 2006.285.19:06:14.37#ibcon#about to write, iclass 19, count 0 2006.285.19:06:14.37#ibcon#wrote, iclass 19, count 0 2006.285.19:06:14.37#ibcon#about to read 3, iclass 19, count 0 2006.285.19:06:14.40#ibcon#read 3, iclass 19, count 0 2006.285.19:06:14.40#ibcon#about to read 4, iclass 19, count 0 2006.285.19:06:14.40#ibcon#read 4, iclass 19, count 0 2006.285.19:06:14.40#ibcon#about to read 5, iclass 19, count 0 2006.285.19:06:14.40#ibcon#read 5, iclass 19, count 0 2006.285.19:06:14.40#ibcon#about to read 6, iclass 19, count 0 2006.285.19:06:14.40#ibcon#read 6, iclass 19, count 0 2006.285.19:06:14.40#ibcon#end of sib2, iclass 19, count 0 2006.285.19:06:14.40#ibcon#*after write, iclass 19, count 0 2006.285.19:06:14.40#ibcon#*before return 0, iclass 19, count 0 2006.285.19:06:14.40#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:06:14.40#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:06:14.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.19:06:14.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.19:06:14.40$vck44/valo=6,814.99 2006.285.19:06:14.40#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.19:06:14.40#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.19:06:14.40#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:14.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:06:14.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:06:14.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:06:14.40#ibcon#enter wrdev, iclass 21, count 0 2006.285.19:06:14.40#ibcon#first serial, iclass 21, count 0 2006.285.19:06:14.40#ibcon#enter sib2, iclass 21, count 0 2006.285.19:06:14.40#ibcon#flushed, iclass 21, count 0 2006.285.19:06:14.40#ibcon#about to write, iclass 21, count 0 2006.285.19:06:14.40#ibcon#wrote, iclass 21, count 0 2006.285.19:06:14.40#ibcon#about to read 3, iclass 21, count 0 2006.285.19:06:14.42#ibcon#read 3, iclass 21, count 0 2006.285.19:06:14.42#ibcon#about to read 4, iclass 21, count 0 2006.285.19:06:14.42#ibcon#read 4, iclass 21, count 0 2006.285.19:06:14.42#ibcon#about to read 5, iclass 21, count 0 2006.285.19:06:14.42#ibcon#read 5, iclass 21, count 0 2006.285.19:06:14.42#ibcon#about to read 6, iclass 21, count 0 2006.285.19:06:14.42#ibcon#read 6, iclass 21, count 0 2006.285.19:06:14.42#ibcon#end of sib2, iclass 21, count 0 2006.285.19:06:14.42#ibcon#*mode == 0, iclass 21, count 0 2006.285.19:06:14.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.19:06:14.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.19:06:14.42#ibcon#*before write, iclass 21, count 0 2006.285.19:06:14.42#ibcon#enter sib2, iclass 21, count 0 2006.285.19:06:14.42#ibcon#flushed, iclass 21, count 0 2006.285.19:06:14.42#ibcon#about to write, iclass 21, count 0 2006.285.19:06:14.42#ibcon#wrote, iclass 21, count 0 2006.285.19:06:14.42#ibcon#about to read 3, iclass 21, count 0 2006.285.19:06:14.46#ibcon#read 3, iclass 21, count 0 2006.285.19:06:14.46#ibcon#about to read 4, iclass 21, count 0 2006.285.19:06:14.46#ibcon#read 4, iclass 21, count 0 2006.285.19:06:14.46#ibcon#about to read 5, iclass 21, count 0 2006.285.19:06:14.46#ibcon#read 5, iclass 21, count 0 2006.285.19:06:14.46#ibcon#about to read 6, iclass 21, count 0 2006.285.19:06:14.46#ibcon#read 6, iclass 21, count 0 2006.285.19:06:14.46#ibcon#end of sib2, iclass 21, count 0 2006.285.19:06:14.46#ibcon#*after write, iclass 21, count 0 2006.285.19:06:14.46#ibcon#*before return 0, iclass 21, count 0 2006.285.19:06:14.46#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:06:14.46#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:06:14.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.19:06:14.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.19:06:14.46$vck44/va=6,4 2006.285.19:06:14.46#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.19:06:14.46#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.19:06:14.46#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:14.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:06:14.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:06:14.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:06:14.52#ibcon#enter wrdev, iclass 23, count 2 2006.285.19:06:14.52#ibcon#first serial, iclass 23, count 2 2006.285.19:06:14.52#ibcon#enter sib2, iclass 23, count 2 2006.285.19:06:14.52#ibcon#flushed, iclass 23, count 2 2006.285.19:06:14.52#ibcon#about to write, iclass 23, count 2 2006.285.19:06:14.52#ibcon#wrote, iclass 23, count 2 2006.285.19:06:14.52#ibcon#about to read 3, iclass 23, count 2 2006.285.19:06:14.54#ibcon#read 3, iclass 23, count 2 2006.285.19:06:14.54#ibcon#about to read 4, iclass 23, count 2 2006.285.19:06:14.54#ibcon#read 4, iclass 23, count 2 2006.285.19:06:14.54#ibcon#about to read 5, iclass 23, count 2 2006.285.19:06:14.54#ibcon#read 5, iclass 23, count 2 2006.285.19:06:14.54#ibcon#about to read 6, iclass 23, count 2 2006.285.19:06:14.54#ibcon#read 6, iclass 23, count 2 2006.285.19:06:14.54#ibcon#end of sib2, iclass 23, count 2 2006.285.19:06:14.54#ibcon#*mode == 0, iclass 23, count 2 2006.285.19:06:14.54#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.19:06:14.54#ibcon#[25=AT06-04\r\n] 2006.285.19:06:14.54#ibcon#*before write, iclass 23, count 2 2006.285.19:06:14.54#ibcon#enter sib2, iclass 23, count 2 2006.285.19:06:14.54#ibcon#flushed, iclass 23, count 2 2006.285.19:06:14.54#ibcon#about to write, iclass 23, count 2 2006.285.19:06:14.54#ibcon#wrote, iclass 23, count 2 2006.285.19:06:14.54#ibcon#about to read 3, iclass 23, count 2 2006.285.19:06:14.57#ibcon#read 3, iclass 23, count 2 2006.285.19:06:14.57#ibcon#about to read 4, iclass 23, count 2 2006.285.19:06:14.57#ibcon#read 4, iclass 23, count 2 2006.285.19:06:14.57#ibcon#about to read 5, iclass 23, count 2 2006.285.19:06:14.57#ibcon#read 5, iclass 23, count 2 2006.285.19:06:14.57#ibcon#about to read 6, iclass 23, count 2 2006.285.19:06:14.57#ibcon#read 6, iclass 23, count 2 2006.285.19:06:14.57#ibcon#end of sib2, iclass 23, count 2 2006.285.19:06:14.57#ibcon#*after write, iclass 23, count 2 2006.285.19:06:14.57#ibcon#*before return 0, iclass 23, count 2 2006.285.19:06:14.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:06:14.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:06:14.57#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.19:06:14.57#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:14.57#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:06:14.58#abcon#<5=/15 0.6 1.3 15.021001014.9\r\n> 2006.285.19:06:14.60#abcon#{5=INTERFACE CLEAR} 2006.285.19:06:14.66#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:06:14.69#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:06:14.69#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:06:14.69#ibcon#enter wrdev, iclass 23, count 0 2006.285.19:06:14.69#ibcon#first serial, iclass 23, count 0 2006.285.19:06:14.69#ibcon#enter sib2, iclass 23, count 0 2006.285.19:06:14.69#ibcon#flushed, iclass 23, count 0 2006.285.19:06:14.69#ibcon#about to write, iclass 23, count 0 2006.285.19:06:14.69#ibcon#wrote, iclass 23, count 0 2006.285.19:06:14.69#ibcon#about to read 3, iclass 23, count 0 2006.285.19:06:14.71#ibcon#read 3, iclass 23, count 0 2006.285.19:06:14.71#ibcon#about to read 4, iclass 23, count 0 2006.285.19:06:14.71#ibcon#read 4, iclass 23, count 0 2006.285.19:06:14.71#ibcon#about to read 5, iclass 23, count 0 2006.285.19:06:14.71#ibcon#read 5, iclass 23, count 0 2006.285.19:06:14.71#ibcon#about to read 6, iclass 23, count 0 2006.285.19:06:14.71#ibcon#read 6, iclass 23, count 0 2006.285.19:06:14.71#ibcon#end of sib2, iclass 23, count 0 2006.285.19:06:14.71#ibcon#*mode == 0, iclass 23, count 0 2006.285.19:06:14.71#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.19:06:14.71#ibcon#[25=USB\r\n] 2006.285.19:06:14.71#ibcon#*before write, iclass 23, count 0 2006.285.19:06:14.71#ibcon#enter sib2, iclass 23, count 0 2006.285.19:06:14.71#ibcon#flushed, iclass 23, count 0 2006.285.19:06:14.71#ibcon#about to write, iclass 23, count 0 2006.285.19:06:14.71#ibcon#wrote, iclass 23, count 0 2006.285.19:06:14.71#ibcon#about to read 3, iclass 23, count 0 2006.285.19:06:14.74#ibcon#read 3, iclass 23, count 0 2006.285.19:06:14.74#ibcon#about to read 4, iclass 23, count 0 2006.285.19:06:14.74#ibcon#read 4, iclass 23, count 0 2006.285.19:06:14.74#ibcon#about to read 5, iclass 23, count 0 2006.285.19:06:14.74#ibcon#read 5, iclass 23, count 0 2006.285.19:06:14.74#ibcon#about to read 6, iclass 23, count 0 2006.285.19:06:14.74#ibcon#read 6, iclass 23, count 0 2006.285.19:06:14.74#ibcon#end of sib2, iclass 23, count 0 2006.285.19:06:14.74#ibcon#*after write, iclass 23, count 0 2006.285.19:06:14.74#ibcon#*before return 0, iclass 23, count 0 2006.285.19:06:14.74#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:06:14.74#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:06:14.74#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.19:06:14.74#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.19:06:14.74$vck44/valo=7,864.99 2006.285.19:06:14.74#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.19:06:14.74#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.19:06:14.74#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:14.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:06:14.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:06:14.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:06:14.74#ibcon#enter wrdev, iclass 29, count 0 2006.285.19:06:14.74#ibcon#first serial, iclass 29, count 0 2006.285.19:06:14.74#ibcon#enter sib2, iclass 29, count 0 2006.285.19:06:14.74#ibcon#flushed, iclass 29, count 0 2006.285.19:06:14.74#ibcon#about to write, iclass 29, count 0 2006.285.19:06:14.74#ibcon#wrote, iclass 29, count 0 2006.285.19:06:14.74#ibcon#about to read 3, iclass 29, count 0 2006.285.19:06:14.76#ibcon#read 3, iclass 29, count 0 2006.285.19:06:14.76#ibcon#about to read 4, iclass 29, count 0 2006.285.19:06:14.76#ibcon#read 4, iclass 29, count 0 2006.285.19:06:14.76#ibcon#about to read 5, iclass 29, count 0 2006.285.19:06:14.76#ibcon#read 5, iclass 29, count 0 2006.285.19:06:14.76#ibcon#about to read 6, iclass 29, count 0 2006.285.19:06:14.76#ibcon#read 6, iclass 29, count 0 2006.285.19:06:14.76#ibcon#end of sib2, iclass 29, count 0 2006.285.19:06:14.76#ibcon#*mode == 0, iclass 29, count 0 2006.285.19:06:14.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.19:06:14.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.19:06:14.76#ibcon#*before write, iclass 29, count 0 2006.285.19:06:14.76#ibcon#enter sib2, iclass 29, count 0 2006.285.19:06:14.76#ibcon#flushed, iclass 29, count 0 2006.285.19:06:14.76#ibcon#about to write, iclass 29, count 0 2006.285.19:06:14.76#ibcon#wrote, iclass 29, count 0 2006.285.19:06:14.76#ibcon#about to read 3, iclass 29, count 0 2006.285.19:06:14.80#ibcon#read 3, iclass 29, count 0 2006.285.19:06:14.80#ibcon#about to read 4, iclass 29, count 0 2006.285.19:06:14.80#ibcon#read 4, iclass 29, count 0 2006.285.19:06:14.80#ibcon#about to read 5, iclass 29, count 0 2006.285.19:06:14.80#ibcon#read 5, iclass 29, count 0 2006.285.19:06:14.80#ibcon#about to read 6, iclass 29, count 0 2006.285.19:06:14.80#ibcon#read 6, iclass 29, count 0 2006.285.19:06:14.80#ibcon#end of sib2, iclass 29, count 0 2006.285.19:06:14.80#ibcon#*after write, iclass 29, count 0 2006.285.19:06:14.80#ibcon#*before return 0, iclass 29, count 0 2006.285.19:06:14.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:06:14.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:06:14.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.19:06:14.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.19:06:14.80$vck44/va=7,4 2006.285.19:06:14.80#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.19:06:14.80#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.19:06:14.80#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:14.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:06:14.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:06:14.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:06:14.86#ibcon#enter wrdev, iclass 31, count 2 2006.285.19:06:14.86#ibcon#first serial, iclass 31, count 2 2006.285.19:06:14.86#ibcon#enter sib2, iclass 31, count 2 2006.285.19:06:14.86#ibcon#flushed, iclass 31, count 2 2006.285.19:06:14.86#ibcon#about to write, iclass 31, count 2 2006.285.19:06:14.86#ibcon#wrote, iclass 31, count 2 2006.285.19:06:14.86#ibcon#about to read 3, iclass 31, count 2 2006.285.19:06:14.88#ibcon#read 3, iclass 31, count 2 2006.285.19:06:14.88#ibcon#about to read 4, iclass 31, count 2 2006.285.19:06:14.88#ibcon#read 4, iclass 31, count 2 2006.285.19:06:14.88#ibcon#about to read 5, iclass 31, count 2 2006.285.19:06:14.88#ibcon#read 5, iclass 31, count 2 2006.285.19:06:14.88#ibcon#about to read 6, iclass 31, count 2 2006.285.19:06:14.88#ibcon#read 6, iclass 31, count 2 2006.285.19:06:14.88#ibcon#end of sib2, iclass 31, count 2 2006.285.19:06:14.88#ibcon#*mode == 0, iclass 31, count 2 2006.285.19:06:14.88#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.19:06:14.88#ibcon#[25=AT07-04\r\n] 2006.285.19:06:14.88#ibcon#*before write, iclass 31, count 2 2006.285.19:06:14.88#ibcon#enter sib2, iclass 31, count 2 2006.285.19:06:14.88#ibcon#flushed, iclass 31, count 2 2006.285.19:06:14.88#ibcon#about to write, iclass 31, count 2 2006.285.19:06:14.88#ibcon#wrote, iclass 31, count 2 2006.285.19:06:14.88#ibcon#about to read 3, iclass 31, count 2 2006.285.19:06:14.91#ibcon#read 3, iclass 31, count 2 2006.285.19:06:14.91#ibcon#about to read 4, iclass 31, count 2 2006.285.19:06:14.91#ibcon#read 4, iclass 31, count 2 2006.285.19:06:14.91#ibcon#about to read 5, iclass 31, count 2 2006.285.19:06:14.91#ibcon#read 5, iclass 31, count 2 2006.285.19:06:14.91#ibcon#about to read 6, iclass 31, count 2 2006.285.19:06:14.91#ibcon#read 6, iclass 31, count 2 2006.285.19:06:14.91#ibcon#end of sib2, iclass 31, count 2 2006.285.19:06:14.91#ibcon#*after write, iclass 31, count 2 2006.285.19:06:14.91#ibcon#*before return 0, iclass 31, count 2 2006.285.19:06:14.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:06:14.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:06:14.91#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.19:06:14.91#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:14.91#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:06:15.03#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:06:15.03#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:06:15.03#ibcon#enter wrdev, iclass 31, count 0 2006.285.19:06:15.03#ibcon#first serial, iclass 31, count 0 2006.285.19:06:15.03#ibcon#enter sib2, iclass 31, count 0 2006.285.19:06:15.03#ibcon#flushed, iclass 31, count 0 2006.285.19:06:15.03#ibcon#about to write, iclass 31, count 0 2006.285.19:06:15.03#ibcon#wrote, iclass 31, count 0 2006.285.19:06:15.03#ibcon#about to read 3, iclass 31, count 0 2006.285.19:06:15.05#ibcon#read 3, iclass 31, count 0 2006.285.19:06:15.05#ibcon#about to read 4, iclass 31, count 0 2006.285.19:06:15.05#ibcon#read 4, iclass 31, count 0 2006.285.19:06:15.05#ibcon#about to read 5, iclass 31, count 0 2006.285.19:06:15.05#ibcon#read 5, iclass 31, count 0 2006.285.19:06:15.05#ibcon#about to read 6, iclass 31, count 0 2006.285.19:06:15.05#ibcon#read 6, iclass 31, count 0 2006.285.19:06:15.05#ibcon#end of sib2, iclass 31, count 0 2006.285.19:06:15.05#ibcon#*mode == 0, iclass 31, count 0 2006.285.19:06:15.05#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.19:06:15.05#ibcon#[25=USB\r\n] 2006.285.19:06:15.05#ibcon#*before write, iclass 31, count 0 2006.285.19:06:15.05#ibcon#enter sib2, iclass 31, count 0 2006.285.19:06:15.05#ibcon#flushed, iclass 31, count 0 2006.285.19:06:15.05#ibcon#about to write, iclass 31, count 0 2006.285.19:06:15.05#ibcon#wrote, iclass 31, count 0 2006.285.19:06:15.05#ibcon#about to read 3, iclass 31, count 0 2006.285.19:06:15.08#ibcon#read 3, iclass 31, count 0 2006.285.19:06:15.08#ibcon#about to read 4, iclass 31, count 0 2006.285.19:06:15.08#ibcon#read 4, iclass 31, count 0 2006.285.19:06:15.08#ibcon#about to read 5, iclass 31, count 0 2006.285.19:06:15.08#ibcon#read 5, iclass 31, count 0 2006.285.19:06:15.08#ibcon#about to read 6, iclass 31, count 0 2006.285.19:06:15.08#ibcon#read 6, iclass 31, count 0 2006.285.19:06:15.08#ibcon#end of sib2, iclass 31, count 0 2006.285.19:06:15.08#ibcon#*after write, iclass 31, count 0 2006.285.19:06:15.08#ibcon#*before return 0, iclass 31, count 0 2006.285.19:06:15.08#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:06:15.08#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:06:15.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.19:06:15.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.19:06:15.08$vck44/valo=8,884.99 2006.285.19:06:15.08#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.19:06:15.08#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.19:06:15.08#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:15.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:06:15.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:06:15.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:06:15.08#ibcon#enter wrdev, iclass 33, count 0 2006.285.19:06:15.08#ibcon#first serial, iclass 33, count 0 2006.285.19:06:15.08#ibcon#enter sib2, iclass 33, count 0 2006.285.19:06:15.08#ibcon#flushed, iclass 33, count 0 2006.285.19:06:15.08#ibcon#about to write, iclass 33, count 0 2006.285.19:06:15.08#ibcon#wrote, iclass 33, count 0 2006.285.19:06:15.08#ibcon#about to read 3, iclass 33, count 0 2006.285.19:06:15.10#ibcon#read 3, iclass 33, count 0 2006.285.19:06:15.57#ibcon#about to read 4, iclass 33, count 0 2006.285.19:06:15.57#ibcon#read 4, iclass 33, count 0 2006.285.19:06:15.57#ibcon#about to read 5, iclass 33, count 0 2006.285.19:06:15.57#ibcon#read 5, iclass 33, count 0 2006.285.19:06:15.57#ibcon#about to read 6, iclass 33, count 0 2006.285.19:06:15.57#ibcon#read 6, iclass 33, count 0 2006.285.19:06:15.57#ibcon#end of sib2, iclass 33, count 0 2006.285.19:06:15.57#ibcon#*mode == 0, iclass 33, count 0 2006.285.19:06:15.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.19:06:15.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.19:06:15.57#ibcon#*before write, iclass 33, count 0 2006.285.19:06:15.57#ibcon#enter sib2, iclass 33, count 0 2006.285.19:06:15.57#ibcon#flushed, iclass 33, count 0 2006.285.19:06:15.57#ibcon#about to write, iclass 33, count 0 2006.285.19:06:15.57#ibcon#wrote, iclass 33, count 0 2006.285.19:06:15.57#ibcon#about to read 3, iclass 33, count 0 2006.285.19:06:15.61#ibcon#read 3, iclass 33, count 0 2006.285.19:06:15.61#ibcon#about to read 4, iclass 33, count 0 2006.285.19:06:15.61#ibcon#read 4, iclass 33, count 0 2006.285.19:06:15.61#ibcon#about to read 5, iclass 33, count 0 2006.285.19:06:15.61#ibcon#read 5, iclass 33, count 0 2006.285.19:06:15.61#ibcon#about to read 6, iclass 33, count 0 2006.285.19:06:15.61#ibcon#read 6, iclass 33, count 0 2006.285.19:06:15.61#ibcon#end of sib2, iclass 33, count 0 2006.285.19:06:15.61#ibcon#*after write, iclass 33, count 0 2006.285.19:06:15.61#ibcon#*before return 0, iclass 33, count 0 2006.285.19:06:15.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:06:15.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:06:15.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.19:06:15.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.19:06:15.61$vck44/va=8,3 2006.285.19:06:15.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.19:06:15.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.19:06:15.61#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:15.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:06:15.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:06:15.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:06:15.61#ibcon#enter wrdev, iclass 35, count 2 2006.285.19:06:15.61#ibcon#first serial, iclass 35, count 2 2006.285.19:06:15.61#ibcon#enter sib2, iclass 35, count 2 2006.285.19:06:15.61#ibcon#flushed, iclass 35, count 2 2006.285.19:06:15.61#ibcon#about to write, iclass 35, count 2 2006.285.19:06:15.61#ibcon#wrote, iclass 35, count 2 2006.285.19:06:15.61#ibcon#about to read 3, iclass 35, count 2 2006.285.19:06:15.63#ibcon#read 3, iclass 35, count 2 2006.285.19:06:15.63#ibcon#about to read 4, iclass 35, count 2 2006.285.19:06:15.63#ibcon#read 4, iclass 35, count 2 2006.285.19:06:15.63#ibcon#about to read 5, iclass 35, count 2 2006.285.19:06:15.63#ibcon#read 5, iclass 35, count 2 2006.285.19:06:15.63#ibcon#about to read 6, iclass 35, count 2 2006.285.19:06:15.63#ibcon#read 6, iclass 35, count 2 2006.285.19:06:15.63#ibcon#end of sib2, iclass 35, count 2 2006.285.19:06:15.63#ibcon#*mode == 0, iclass 35, count 2 2006.285.19:06:15.63#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.19:06:15.63#ibcon#[25=AT08-03\r\n] 2006.285.19:06:15.63#ibcon#*before write, iclass 35, count 2 2006.285.19:06:15.63#ibcon#enter sib2, iclass 35, count 2 2006.285.19:06:15.63#ibcon#flushed, iclass 35, count 2 2006.285.19:06:15.63#ibcon#about to write, iclass 35, count 2 2006.285.19:06:15.63#ibcon#wrote, iclass 35, count 2 2006.285.19:06:15.63#ibcon#about to read 3, iclass 35, count 2 2006.285.19:06:15.66#ibcon#read 3, iclass 35, count 2 2006.285.19:06:15.66#ibcon#about to read 4, iclass 35, count 2 2006.285.19:06:15.66#ibcon#read 4, iclass 35, count 2 2006.285.19:06:15.66#ibcon#about to read 5, iclass 35, count 2 2006.285.19:06:15.66#ibcon#read 5, iclass 35, count 2 2006.285.19:06:15.66#ibcon#about to read 6, iclass 35, count 2 2006.285.19:06:15.66#ibcon#read 6, iclass 35, count 2 2006.285.19:06:15.66#ibcon#end of sib2, iclass 35, count 2 2006.285.19:06:15.66#ibcon#*after write, iclass 35, count 2 2006.285.19:06:15.66#ibcon#*before return 0, iclass 35, count 2 2006.285.19:06:15.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:06:15.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:06:15.66#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.19:06:15.66#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:15.66#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:06:15.78#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:06:15.78#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:06:15.78#ibcon#enter wrdev, iclass 35, count 0 2006.285.19:06:15.78#ibcon#first serial, iclass 35, count 0 2006.285.19:06:15.78#ibcon#enter sib2, iclass 35, count 0 2006.285.19:06:15.78#ibcon#flushed, iclass 35, count 0 2006.285.19:06:15.78#ibcon#about to write, iclass 35, count 0 2006.285.19:06:15.78#ibcon#wrote, iclass 35, count 0 2006.285.19:06:15.78#ibcon#about to read 3, iclass 35, count 0 2006.285.19:06:15.80#ibcon#read 3, iclass 35, count 0 2006.285.19:06:15.80#ibcon#about to read 4, iclass 35, count 0 2006.285.19:06:15.80#ibcon#read 4, iclass 35, count 0 2006.285.19:06:15.80#ibcon#about to read 5, iclass 35, count 0 2006.285.19:06:15.80#ibcon#read 5, iclass 35, count 0 2006.285.19:06:15.80#ibcon#about to read 6, iclass 35, count 0 2006.285.19:06:15.80#ibcon#read 6, iclass 35, count 0 2006.285.19:06:15.80#ibcon#end of sib2, iclass 35, count 0 2006.285.19:06:15.80#ibcon#*mode == 0, iclass 35, count 0 2006.285.19:06:15.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.19:06:15.80#ibcon#[25=USB\r\n] 2006.285.19:06:15.80#ibcon#*before write, iclass 35, count 0 2006.285.19:06:15.80#ibcon#enter sib2, iclass 35, count 0 2006.285.19:06:15.80#ibcon#flushed, iclass 35, count 0 2006.285.19:06:15.80#ibcon#about to write, iclass 35, count 0 2006.285.19:06:15.80#ibcon#wrote, iclass 35, count 0 2006.285.19:06:15.80#ibcon#about to read 3, iclass 35, count 0 2006.285.19:06:15.83#ibcon#read 3, iclass 35, count 0 2006.285.19:06:15.83#ibcon#about to read 4, iclass 35, count 0 2006.285.19:06:15.83#ibcon#read 4, iclass 35, count 0 2006.285.19:06:15.83#ibcon#about to read 5, iclass 35, count 0 2006.285.19:06:15.83#ibcon#read 5, iclass 35, count 0 2006.285.19:06:15.83#ibcon#about to read 6, iclass 35, count 0 2006.285.19:06:15.83#ibcon#read 6, iclass 35, count 0 2006.285.19:06:15.83#ibcon#end of sib2, iclass 35, count 0 2006.285.19:06:15.83#ibcon#*after write, iclass 35, count 0 2006.285.19:06:15.83#ibcon#*before return 0, iclass 35, count 0 2006.285.19:06:15.83#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:06:15.83#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:06:15.83#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.19:06:15.83#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.19:06:15.83$vck44/vblo=1,629.99 2006.285.19:06:15.83#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.19:06:15.83#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.19:06:15.83#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:15.83#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:06:15.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:06:15.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:06:15.83#ibcon#enter wrdev, iclass 37, count 0 2006.285.19:06:15.83#ibcon#first serial, iclass 37, count 0 2006.285.19:06:15.83#ibcon#enter sib2, iclass 37, count 0 2006.285.19:06:15.83#ibcon#flushed, iclass 37, count 0 2006.285.19:06:15.83#ibcon#about to write, iclass 37, count 0 2006.285.19:06:15.83#ibcon#wrote, iclass 37, count 0 2006.285.19:06:15.83#ibcon#about to read 3, iclass 37, count 0 2006.285.19:06:15.85#ibcon#read 3, iclass 37, count 0 2006.285.19:06:15.85#ibcon#about to read 4, iclass 37, count 0 2006.285.19:06:15.85#ibcon#read 4, iclass 37, count 0 2006.285.19:06:15.85#ibcon#about to read 5, iclass 37, count 0 2006.285.19:06:15.85#ibcon#read 5, iclass 37, count 0 2006.285.19:06:15.85#ibcon#about to read 6, iclass 37, count 0 2006.285.19:06:15.85#ibcon#read 6, iclass 37, count 0 2006.285.19:06:15.85#ibcon#end of sib2, iclass 37, count 0 2006.285.19:06:15.85#ibcon#*mode == 0, iclass 37, count 0 2006.285.19:06:15.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.19:06:15.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.19:06:15.85#ibcon#*before write, iclass 37, count 0 2006.285.19:06:15.85#ibcon#enter sib2, iclass 37, count 0 2006.285.19:06:15.85#ibcon#flushed, iclass 37, count 0 2006.285.19:06:15.85#ibcon#about to write, iclass 37, count 0 2006.285.19:06:15.85#ibcon#wrote, iclass 37, count 0 2006.285.19:06:15.85#ibcon#about to read 3, iclass 37, count 0 2006.285.19:06:15.89#ibcon#read 3, iclass 37, count 0 2006.285.19:06:15.89#ibcon#about to read 4, iclass 37, count 0 2006.285.19:06:15.89#ibcon#read 4, iclass 37, count 0 2006.285.19:06:15.89#ibcon#about to read 5, iclass 37, count 0 2006.285.19:06:15.89#ibcon#read 5, iclass 37, count 0 2006.285.19:06:15.89#ibcon#about to read 6, iclass 37, count 0 2006.285.19:06:15.89#ibcon#read 6, iclass 37, count 0 2006.285.19:06:15.89#ibcon#end of sib2, iclass 37, count 0 2006.285.19:06:15.89#ibcon#*after write, iclass 37, count 0 2006.285.19:06:15.89#ibcon#*before return 0, iclass 37, count 0 2006.285.19:06:15.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:06:15.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:06:15.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.19:06:15.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.19:06:15.89$vck44/vb=1,4 2006.285.19:06:15.89#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.19:06:15.89#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.19:06:15.89#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:15.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:06:15.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:06:15.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:06:15.89#ibcon#enter wrdev, iclass 39, count 2 2006.285.19:06:15.89#ibcon#first serial, iclass 39, count 2 2006.285.19:06:15.89#ibcon#enter sib2, iclass 39, count 2 2006.285.19:06:15.89#ibcon#flushed, iclass 39, count 2 2006.285.19:06:15.89#ibcon#about to write, iclass 39, count 2 2006.285.19:06:15.89#ibcon#wrote, iclass 39, count 2 2006.285.19:06:15.89#ibcon#about to read 3, iclass 39, count 2 2006.285.19:06:15.91#ibcon#read 3, iclass 39, count 2 2006.285.19:06:15.91#ibcon#about to read 4, iclass 39, count 2 2006.285.19:06:15.91#ibcon#read 4, iclass 39, count 2 2006.285.19:06:15.91#ibcon#about to read 5, iclass 39, count 2 2006.285.19:06:15.91#ibcon#read 5, iclass 39, count 2 2006.285.19:06:15.91#ibcon#about to read 6, iclass 39, count 2 2006.285.19:06:15.91#ibcon#read 6, iclass 39, count 2 2006.285.19:06:15.91#ibcon#end of sib2, iclass 39, count 2 2006.285.19:06:15.91#ibcon#*mode == 0, iclass 39, count 2 2006.285.19:06:15.91#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.19:06:15.91#ibcon#[27=AT01-04\r\n] 2006.285.19:06:15.91#ibcon#*before write, iclass 39, count 2 2006.285.19:06:15.91#ibcon#enter sib2, iclass 39, count 2 2006.285.19:06:15.91#ibcon#flushed, iclass 39, count 2 2006.285.19:06:15.91#ibcon#about to write, iclass 39, count 2 2006.285.19:06:15.91#ibcon#wrote, iclass 39, count 2 2006.285.19:06:15.91#ibcon#about to read 3, iclass 39, count 2 2006.285.19:06:15.94#ibcon#read 3, iclass 39, count 2 2006.285.19:06:15.94#ibcon#about to read 4, iclass 39, count 2 2006.285.19:06:15.94#ibcon#read 4, iclass 39, count 2 2006.285.19:06:15.94#ibcon#about to read 5, iclass 39, count 2 2006.285.19:06:15.94#ibcon#read 5, iclass 39, count 2 2006.285.19:06:15.94#ibcon#about to read 6, iclass 39, count 2 2006.285.19:06:15.94#ibcon#read 6, iclass 39, count 2 2006.285.19:06:15.94#ibcon#end of sib2, iclass 39, count 2 2006.285.19:06:15.94#ibcon#*after write, iclass 39, count 2 2006.285.19:06:15.94#ibcon#*before return 0, iclass 39, count 2 2006.285.19:06:15.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:06:15.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:06:15.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.19:06:15.94#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:15.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:06:16.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:06:16.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:06:16.06#ibcon#enter wrdev, iclass 39, count 0 2006.285.19:06:16.06#ibcon#first serial, iclass 39, count 0 2006.285.19:06:16.06#ibcon#enter sib2, iclass 39, count 0 2006.285.19:06:16.06#ibcon#flushed, iclass 39, count 0 2006.285.19:06:16.06#ibcon#about to write, iclass 39, count 0 2006.285.19:06:16.06#ibcon#wrote, iclass 39, count 0 2006.285.19:06:16.06#ibcon#about to read 3, iclass 39, count 0 2006.285.19:06:16.08#ibcon#read 3, iclass 39, count 0 2006.285.19:06:16.08#ibcon#about to read 4, iclass 39, count 0 2006.285.19:06:16.08#ibcon#read 4, iclass 39, count 0 2006.285.19:06:16.08#ibcon#about to read 5, iclass 39, count 0 2006.285.19:06:16.08#ibcon#read 5, iclass 39, count 0 2006.285.19:06:16.08#ibcon#about to read 6, iclass 39, count 0 2006.285.19:06:16.08#ibcon#read 6, iclass 39, count 0 2006.285.19:06:16.08#ibcon#end of sib2, iclass 39, count 0 2006.285.19:06:16.08#ibcon#*mode == 0, iclass 39, count 0 2006.285.19:06:16.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.19:06:16.08#ibcon#[27=USB\r\n] 2006.285.19:06:16.08#ibcon#*before write, iclass 39, count 0 2006.285.19:06:16.08#ibcon#enter sib2, iclass 39, count 0 2006.285.19:06:16.08#ibcon#flushed, iclass 39, count 0 2006.285.19:06:16.08#ibcon#about to write, iclass 39, count 0 2006.285.19:06:16.08#ibcon#wrote, iclass 39, count 0 2006.285.19:06:16.08#ibcon#about to read 3, iclass 39, count 0 2006.285.19:06:16.11#ibcon#read 3, iclass 39, count 0 2006.285.19:06:16.11#ibcon#about to read 4, iclass 39, count 0 2006.285.19:06:16.11#ibcon#read 4, iclass 39, count 0 2006.285.19:06:16.11#ibcon#about to read 5, iclass 39, count 0 2006.285.19:06:16.11#ibcon#read 5, iclass 39, count 0 2006.285.19:06:16.11#ibcon#about to read 6, iclass 39, count 0 2006.285.19:06:16.11#ibcon#read 6, iclass 39, count 0 2006.285.19:06:16.11#ibcon#end of sib2, iclass 39, count 0 2006.285.19:06:16.11#ibcon#*after write, iclass 39, count 0 2006.285.19:06:16.11#ibcon#*before return 0, iclass 39, count 0 2006.285.19:06:16.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:06:16.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:06:16.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.19:06:16.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.19:06:16.11$vck44/vblo=2,634.99 2006.285.19:06:16.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.19:06:16.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.19:06:16.11#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:16.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:06:16.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:06:16.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:06:16.11#ibcon#enter wrdev, iclass 3, count 0 2006.285.19:06:16.11#ibcon#first serial, iclass 3, count 0 2006.285.19:06:16.11#ibcon#enter sib2, iclass 3, count 0 2006.285.19:06:16.11#ibcon#flushed, iclass 3, count 0 2006.285.19:06:16.11#ibcon#about to write, iclass 3, count 0 2006.285.19:06:16.11#ibcon#wrote, iclass 3, count 0 2006.285.19:06:16.11#ibcon#about to read 3, iclass 3, count 0 2006.285.19:06:16.13#ibcon#read 3, iclass 3, count 0 2006.285.19:06:16.22#ibcon#about to read 4, iclass 3, count 0 2006.285.19:06:16.22#ibcon#read 4, iclass 3, count 0 2006.285.19:06:16.22#ibcon#about to read 5, iclass 3, count 0 2006.285.19:06:16.22#ibcon#read 5, iclass 3, count 0 2006.285.19:06:16.22#ibcon#about to read 6, iclass 3, count 0 2006.285.19:06:16.22#ibcon#read 6, iclass 3, count 0 2006.285.19:06:16.22#ibcon#end of sib2, iclass 3, count 0 2006.285.19:06:16.22#ibcon#*mode == 0, iclass 3, count 0 2006.285.19:06:16.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.19:06:16.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.19:06:16.22#ibcon#*before write, iclass 3, count 0 2006.285.19:06:16.22#ibcon#enter sib2, iclass 3, count 0 2006.285.19:06:16.22#ibcon#flushed, iclass 3, count 0 2006.285.19:06:16.22#ibcon#about to write, iclass 3, count 0 2006.285.19:06:16.22#ibcon#wrote, iclass 3, count 0 2006.285.19:06:16.22#ibcon#about to read 3, iclass 3, count 0 2006.285.19:06:16.26#ibcon#read 3, iclass 3, count 0 2006.285.19:06:16.26#ibcon#about to read 4, iclass 3, count 0 2006.285.19:06:16.26#ibcon#read 4, iclass 3, count 0 2006.285.19:06:16.26#ibcon#about to read 5, iclass 3, count 0 2006.285.19:06:16.26#ibcon#read 5, iclass 3, count 0 2006.285.19:06:16.26#ibcon#about to read 6, iclass 3, count 0 2006.285.19:06:16.26#ibcon#read 6, iclass 3, count 0 2006.285.19:06:16.26#ibcon#end of sib2, iclass 3, count 0 2006.285.19:06:16.26#ibcon#*after write, iclass 3, count 0 2006.285.19:06:16.26#ibcon#*before return 0, iclass 3, count 0 2006.285.19:06:16.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:06:16.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:06:16.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.19:06:16.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.19:06:16.26$vck44/vb=2,5 2006.285.19:06:16.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.19:06:16.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.19:06:16.26#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:16.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:06:16.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:06:16.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:06:16.26#ibcon#enter wrdev, iclass 5, count 2 2006.285.19:06:16.26#ibcon#first serial, iclass 5, count 2 2006.285.19:06:16.26#ibcon#enter sib2, iclass 5, count 2 2006.285.19:06:16.26#ibcon#flushed, iclass 5, count 2 2006.285.19:06:16.26#ibcon#about to write, iclass 5, count 2 2006.285.19:06:16.26#ibcon#wrote, iclass 5, count 2 2006.285.19:06:16.26#ibcon#about to read 3, iclass 5, count 2 2006.285.19:06:16.28#ibcon#read 3, iclass 5, count 2 2006.285.19:06:16.28#ibcon#about to read 4, iclass 5, count 2 2006.285.19:06:16.28#ibcon#read 4, iclass 5, count 2 2006.285.19:06:16.28#ibcon#about to read 5, iclass 5, count 2 2006.285.19:06:16.28#ibcon#read 5, iclass 5, count 2 2006.285.19:06:16.28#ibcon#about to read 6, iclass 5, count 2 2006.285.19:06:16.28#ibcon#read 6, iclass 5, count 2 2006.285.19:06:16.28#ibcon#end of sib2, iclass 5, count 2 2006.285.19:06:16.28#ibcon#*mode == 0, iclass 5, count 2 2006.285.19:06:16.28#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.19:06:16.28#ibcon#[27=AT02-05\r\n] 2006.285.19:06:16.28#ibcon#*before write, iclass 5, count 2 2006.285.19:06:16.28#ibcon#enter sib2, iclass 5, count 2 2006.285.19:06:16.28#ibcon#flushed, iclass 5, count 2 2006.285.19:06:16.28#ibcon#about to write, iclass 5, count 2 2006.285.19:06:16.28#ibcon#wrote, iclass 5, count 2 2006.285.19:06:16.28#ibcon#about to read 3, iclass 5, count 2 2006.285.19:06:16.31#ibcon#read 3, iclass 5, count 2 2006.285.19:06:16.31#ibcon#about to read 4, iclass 5, count 2 2006.285.19:06:16.31#ibcon#read 4, iclass 5, count 2 2006.285.19:06:16.31#ibcon#about to read 5, iclass 5, count 2 2006.285.19:06:16.31#ibcon#read 5, iclass 5, count 2 2006.285.19:06:16.31#ibcon#about to read 6, iclass 5, count 2 2006.285.19:06:16.31#ibcon#read 6, iclass 5, count 2 2006.285.19:06:16.31#ibcon#end of sib2, iclass 5, count 2 2006.285.19:06:16.31#ibcon#*after write, iclass 5, count 2 2006.285.19:06:16.31#ibcon#*before return 0, iclass 5, count 2 2006.285.19:06:16.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:06:16.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:06:16.31#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.19:06:16.31#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:16.31#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:06:16.43#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:06:16.43#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:06:16.43#ibcon#enter wrdev, iclass 5, count 0 2006.285.19:06:16.43#ibcon#first serial, iclass 5, count 0 2006.285.19:06:16.43#ibcon#enter sib2, iclass 5, count 0 2006.285.19:06:16.43#ibcon#flushed, iclass 5, count 0 2006.285.19:06:16.43#ibcon#about to write, iclass 5, count 0 2006.285.19:06:16.43#ibcon#wrote, iclass 5, count 0 2006.285.19:06:16.43#ibcon#about to read 3, iclass 5, count 0 2006.285.19:06:16.45#ibcon#read 3, iclass 5, count 0 2006.285.19:06:16.45#ibcon#about to read 4, iclass 5, count 0 2006.285.19:06:16.45#ibcon#read 4, iclass 5, count 0 2006.285.19:06:16.45#ibcon#about to read 5, iclass 5, count 0 2006.285.19:06:16.45#ibcon#read 5, iclass 5, count 0 2006.285.19:06:16.45#ibcon#about to read 6, iclass 5, count 0 2006.285.19:06:16.45#ibcon#read 6, iclass 5, count 0 2006.285.19:06:16.45#ibcon#end of sib2, iclass 5, count 0 2006.285.19:06:16.45#ibcon#*mode == 0, iclass 5, count 0 2006.285.19:06:16.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.19:06:16.45#ibcon#[27=USB\r\n] 2006.285.19:06:16.45#ibcon#*before write, iclass 5, count 0 2006.285.19:06:16.45#ibcon#enter sib2, iclass 5, count 0 2006.285.19:06:16.45#ibcon#flushed, iclass 5, count 0 2006.285.19:06:16.45#ibcon#about to write, iclass 5, count 0 2006.285.19:06:16.45#ibcon#wrote, iclass 5, count 0 2006.285.19:06:16.45#ibcon#about to read 3, iclass 5, count 0 2006.285.19:06:16.48#ibcon#read 3, iclass 5, count 0 2006.285.19:06:16.48#ibcon#about to read 4, iclass 5, count 0 2006.285.19:06:16.48#ibcon#read 4, iclass 5, count 0 2006.285.19:06:16.48#ibcon#about to read 5, iclass 5, count 0 2006.285.19:06:16.48#ibcon#read 5, iclass 5, count 0 2006.285.19:06:16.48#ibcon#about to read 6, iclass 5, count 0 2006.285.19:06:16.48#ibcon#read 6, iclass 5, count 0 2006.285.19:06:16.48#ibcon#end of sib2, iclass 5, count 0 2006.285.19:06:16.48#ibcon#*after write, iclass 5, count 0 2006.285.19:06:16.48#ibcon#*before return 0, iclass 5, count 0 2006.285.19:06:16.48#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:06:16.48#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:06:16.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.19:06:16.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.19:06:16.48$vck44/vblo=3,649.99 2006.285.19:06:16.48#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.19:06:16.48#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.19:06:16.48#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:16.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:06:16.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:06:16.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:06:16.48#ibcon#enter wrdev, iclass 7, count 0 2006.285.19:06:16.48#ibcon#first serial, iclass 7, count 0 2006.285.19:06:16.48#ibcon#enter sib2, iclass 7, count 0 2006.285.19:06:16.48#ibcon#flushed, iclass 7, count 0 2006.285.19:06:16.48#ibcon#about to write, iclass 7, count 0 2006.285.19:06:16.48#ibcon#wrote, iclass 7, count 0 2006.285.19:06:16.48#ibcon#about to read 3, iclass 7, count 0 2006.285.19:06:16.50#ibcon#read 3, iclass 7, count 0 2006.285.19:06:16.50#ibcon#about to read 4, iclass 7, count 0 2006.285.19:06:16.50#ibcon#read 4, iclass 7, count 0 2006.285.19:06:16.50#ibcon#about to read 5, iclass 7, count 0 2006.285.19:06:16.50#ibcon#read 5, iclass 7, count 0 2006.285.19:06:16.50#ibcon#about to read 6, iclass 7, count 0 2006.285.19:06:16.50#ibcon#read 6, iclass 7, count 0 2006.285.19:06:16.50#ibcon#end of sib2, iclass 7, count 0 2006.285.19:06:16.50#ibcon#*mode == 0, iclass 7, count 0 2006.285.19:06:16.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.19:06:16.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.19:06:16.50#ibcon#*before write, iclass 7, count 0 2006.285.19:06:16.50#ibcon#enter sib2, iclass 7, count 0 2006.285.19:06:16.50#ibcon#flushed, iclass 7, count 0 2006.285.19:06:16.50#ibcon#about to write, iclass 7, count 0 2006.285.19:06:16.50#ibcon#wrote, iclass 7, count 0 2006.285.19:06:16.50#ibcon#about to read 3, iclass 7, count 0 2006.285.19:06:16.54#ibcon#read 3, iclass 7, count 0 2006.285.19:06:16.54#ibcon#about to read 4, iclass 7, count 0 2006.285.19:06:16.54#ibcon#read 4, iclass 7, count 0 2006.285.19:06:16.54#ibcon#about to read 5, iclass 7, count 0 2006.285.19:06:16.54#ibcon#read 5, iclass 7, count 0 2006.285.19:06:16.54#ibcon#about to read 6, iclass 7, count 0 2006.285.19:06:16.54#ibcon#read 6, iclass 7, count 0 2006.285.19:06:16.54#ibcon#end of sib2, iclass 7, count 0 2006.285.19:06:16.54#ibcon#*after write, iclass 7, count 0 2006.285.19:06:16.54#ibcon#*before return 0, iclass 7, count 0 2006.285.19:06:16.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:06:16.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:06:16.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.19:06:16.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.19:06:16.54$vck44/vb=3,4 2006.285.19:06:16.54#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.19:06:16.54#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.19:06:16.54#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:16.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:06:16.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:06:16.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:06:16.60#ibcon#enter wrdev, iclass 11, count 2 2006.285.19:06:16.60#ibcon#first serial, iclass 11, count 2 2006.285.19:06:16.60#ibcon#enter sib2, iclass 11, count 2 2006.285.19:06:16.60#ibcon#flushed, iclass 11, count 2 2006.285.19:06:16.60#ibcon#about to write, iclass 11, count 2 2006.285.19:06:16.60#ibcon#wrote, iclass 11, count 2 2006.285.19:06:16.60#ibcon#about to read 3, iclass 11, count 2 2006.285.19:06:16.62#ibcon#read 3, iclass 11, count 2 2006.285.19:06:16.62#ibcon#about to read 4, iclass 11, count 2 2006.285.19:06:16.62#ibcon#read 4, iclass 11, count 2 2006.285.19:06:16.62#ibcon#about to read 5, iclass 11, count 2 2006.285.19:06:16.62#ibcon#read 5, iclass 11, count 2 2006.285.19:06:16.62#ibcon#about to read 6, iclass 11, count 2 2006.285.19:06:16.62#ibcon#read 6, iclass 11, count 2 2006.285.19:06:16.62#ibcon#end of sib2, iclass 11, count 2 2006.285.19:06:16.62#ibcon#*mode == 0, iclass 11, count 2 2006.285.19:06:16.62#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.19:06:16.62#ibcon#[27=AT03-04\r\n] 2006.285.19:06:16.62#ibcon#*before write, iclass 11, count 2 2006.285.19:06:16.62#ibcon#enter sib2, iclass 11, count 2 2006.285.19:06:16.62#ibcon#flushed, iclass 11, count 2 2006.285.19:06:16.62#ibcon#about to write, iclass 11, count 2 2006.285.19:06:16.62#ibcon#wrote, iclass 11, count 2 2006.285.19:06:16.62#ibcon#about to read 3, iclass 11, count 2 2006.285.19:06:16.65#ibcon#read 3, iclass 11, count 2 2006.285.19:06:16.65#ibcon#about to read 4, iclass 11, count 2 2006.285.19:06:16.65#ibcon#read 4, iclass 11, count 2 2006.285.19:06:16.65#ibcon#about to read 5, iclass 11, count 2 2006.285.19:06:16.65#ibcon#read 5, iclass 11, count 2 2006.285.19:06:16.65#ibcon#about to read 6, iclass 11, count 2 2006.285.19:06:16.65#ibcon#read 6, iclass 11, count 2 2006.285.19:06:16.65#ibcon#end of sib2, iclass 11, count 2 2006.285.19:06:16.65#ibcon#*after write, iclass 11, count 2 2006.285.19:06:16.65#ibcon#*before return 0, iclass 11, count 2 2006.285.19:06:16.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:06:16.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:06:16.65#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.19:06:16.65#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:16.65#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:06:16.77#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:06:16.77#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:06:16.77#ibcon#enter wrdev, iclass 11, count 0 2006.285.19:06:16.77#ibcon#first serial, iclass 11, count 0 2006.285.19:06:16.77#ibcon#enter sib2, iclass 11, count 0 2006.285.19:06:16.77#ibcon#flushed, iclass 11, count 0 2006.285.19:06:16.77#ibcon#about to write, iclass 11, count 0 2006.285.19:06:16.77#ibcon#wrote, iclass 11, count 0 2006.285.19:06:16.77#ibcon#about to read 3, iclass 11, count 0 2006.285.19:06:16.79#ibcon#read 3, iclass 11, count 0 2006.285.19:06:16.79#ibcon#about to read 4, iclass 11, count 0 2006.285.19:06:16.79#ibcon#read 4, iclass 11, count 0 2006.285.19:06:16.79#ibcon#about to read 5, iclass 11, count 0 2006.285.19:06:16.79#ibcon#read 5, iclass 11, count 0 2006.285.19:06:16.79#ibcon#about to read 6, iclass 11, count 0 2006.285.19:06:16.79#ibcon#read 6, iclass 11, count 0 2006.285.19:06:16.79#ibcon#end of sib2, iclass 11, count 0 2006.285.19:06:16.79#ibcon#*mode == 0, iclass 11, count 0 2006.285.19:06:16.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.19:06:16.79#ibcon#[27=USB\r\n] 2006.285.19:06:16.79#ibcon#*before write, iclass 11, count 0 2006.285.19:06:16.79#ibcon#enter sib2, iclass 11, count 0 2006.285.19:06:16.79#ibcon#flushed, iclass 11, count 0 2006.285.19:06:16.79#ibcon#about to write, iclass 11, count 0 2006.285.19:06:16.79#ibcon#wrote, iclass 11, count 0 2006.285.19:06:16.79#ibcon#about to read 3, iclass 11, count 0 2006.285.19:06:16.82#ibcon#read 3, iclass 11, count 0 2006.285.19:06:16.82#ibcon#about to read 4, iclass 11, count 0 2006.285.19:06:16.82#ibcon#read 4, iclass 11, count 0 2006.285.19:06:16.82#ibcon#about to read 5, iclass 11, count 0 2006.285.19:06:16.82#ibcon#read 5, iclass 11, count 0 2006.285.19:06:16.82#ibcon#about to read 6, iclass 11, count 0 2006.285.19:06:16.82#ibcon#read 6, iclass 11, count 0 2006.285.19:06:16.82#ibcon#end of sib2, iclass 11, count 0 2006.285.19:06:16.82#ibcon#*after write, iclass 11, count 0 2006.285.19:06:16.82#ibcon#*before return 0, iclass 11, count 0 2006.285.19:06:16.82#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:06:16.82#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:06:16.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.19:06:16.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.19:06:16.82$vck44/vblo=4,679.99 2006.285.19:06:16.82#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.19:06:16.82#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.19:06:16.82#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:16.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:06:16.82#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:06:16.82#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:06:16.82#ibcon#enter wrdev, iclass 13, count 0 2006.285.19:06:16.82#ibcon#first serial, iclass 13, count 0 2006.285.19:06:16.82#ibcon#enter sib2, iclass 13, count 0 2006.285.19:06:16.82#ibcon#flushed, iclass 13, count 0 2006.285.19:06:16.82#ibcon#about to write, iclass 13, count 0 2006.285.19:06:16.82#ibcon#wrote, iclass 13, count 0 2006.285.19:06:16.82#ibcon#about to read 3, iclass 13, count 0 2006.285.19:06:16.84#ibcon#read 3, iclass 13, count 0 2006.285.19:06:16.84#ibcon#about to read 4, iclass 13, count 0 2006.285.19:06:16.84#ibcon#read 4, iclass 13, count 0 2006.285.19:06:16.84#ibcon#about to read 5, iclass 13, count 0 2006.285.19:06:16.84#ibcon#read 5, iclass 13, count 0 2006.285.19:06:16.84#ibcon#about to read 6, iclass 13, count 0 2006.285.19:06:16.84#ibcon#read 6, iclass 13, count 0 2006.285.19:06:16.84#ibcon#end of sib2, iclass 13, count 0 2006.285.19:06:16.84#ibcon#*mode == 0, iclass 13, count 0 2006.285.19:06:16.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.19:06:16.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.19:06:16.84#ibcon#*before write, iclass 13, count 0 2006.285.19:06:16.84#ibcon#enter sib2, iclass 13, count 0 2006.285.19:06:16.84#ibcon#flushed, iclass 13, count 0 2006.285.19:06:16.84#ibcon#about to write, iclass 13, count 0 2006.285.19:06:16.84#ibcon#wrote, iclass 13, count 0 2006.285.19:06:16.84#ibcon#about to read 3, iclass 13, count 0 2006.285.19:06:16.88#ibcon#read 3, iclass 13, count 0 2006.285.19:06:16.88#ibcon#about to read 4, iclass 13, count 0 2006.285.19:06:16.88#ibcon#read 4, iclass 13, count 0 2006.285.19:06:16.88#ibcon#about to read 5, iclass 13, count 0 2006.285.19:06:16.88#ibcon#read 5, iclass 13, count 0 2006.285.19:06:16.88#ibcon#about to read 6, iclass 13, count 0 2006.285.19:06:16.88#ibcon#read 6, iclass 13, count 0 2006.285.19:06:16.88#ibcon#end of sib2, iclass 13, count 0 2006.285.19:06:16.88#ibcon#*after write, iclass 13, count 0 2006.285.19:06:16.88#ibcon#*before return 0, iclass 13, count 0 2006.285.19:06:16.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:06:16.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:06:16.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.19:06:16.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.19:06:16.88$vck44/vb=4,5 2006.285.19:06:16.88#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.19:06:16.88#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.19:06:16.88#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:16.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:06:16.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:06:16.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:06:16.94#ibcon#enter wrdev, iclass 15, count 2 2006.285.19:06:16.94#ibcon#first serial, iclass 15, count 2 2006.285.19:06:16.94#ibcon#enter sib2, iclass 15, count 2 2006.285.19:06:16.94#ibcon#flushed, iclass 15, count 2 2006.285.19:06:16.94#ibcon#about to write, iclass 15, count 2 2006.285.19:06:16.94#ibcon#wrote, iclass 15, count 2 2006.285.19:06:16.94#ibcon#about to read 3, iclass 15, count 2 2006.285.19:06:16.96#ibcon#read 3, iclass 15, count 2 2006.285.19:06:16.96#ibcon#about to read 4, iclass 15, count 2 2006.285.19:06:16.96#ibcon#read 4, iclass 15, count 2 2006.285.19:06:16.96#ibcon#about to read 5, iclass 15, count 2 2006.285.19:06:16.96#ibcon#read 5, iclass 15, count 2 2006.285.19:06:16.96#ibcon#about to read 6, iclass 15, count 2 2006.285.19:06:16.96#ibcon#read 6, iclass 15, count 2 2006.285.19:06:16.96#ibcon#end of sib2, iclass 15, count 2 2006.285.19:06:16.96#ibcon#*mode == 0, iclass 15, count 2 2006.285.19:06:16.96#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.19:06:16.96#ibcon#[27=AT04-05\r\n] 2006.285.19:06:16.96#ibcon#*before write, iclass 15, count 2 2006.285.19:06:16.96#ibcon#enter sib2, iclass 15, count 2 2006.285.19:06:16.96#ibcon#flushed, iclass 15, count 2 2006.285.19:06:16.96#ibcon#about to write, iclass 15, count 2 2006.285.19:06:16.96#ibcon#wrote, iclass 15, count 2 2006.285.19:06:16.96#ibcon#about to read 3, iclass 15, count 2 2006.285.19:06:16.99#ibcon#read 3, iclass 15, count 2 2006.285.19:06:16.99#ibcon#about to read 4, iclass 15, count 2 2006.285.19:06:16.99#ibcon#read 4, iclass 15, count 2 2006.285.19:06:16.99#ibcon#about to read 5, iclass 15, count 2 2006.285.19:06:16.99#ibcon#read 5, iclass 15, count 2 2006.285.19:06:16.99#ibcon#about to read 6, iclass 15, count 2 2006.285.19:06:16.99#ibcon#read 6, iclass 15, count 2 2006.285.19:06:16.99#ibcon#end of sib2, iclass 15, count 2 2006.285.19:06:16.99#ibcon#*after write, iclass 15, count 2 2006.285.19:06:16.99#ibcon#*before return 0, iclass 15, count 2 2006.285.19:06:16.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:06:16.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:06:16.99#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.19:06:16.99#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:16.99#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:06:17.11#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:06:17.11#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:06:17.11#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:06:17.11#ibcon#first serial, iclass 15, count 0 2006.285.19:06:17.11#ibcon#enter sib2, iclass 15, count 0 2006.285.19:06:17.11#ibcon#flushed, iclass 15, count 0 2006.285.19:06:17.11#ibcon#about to write, iclass 15, count 0 2006.285.19:06:17.11#ibcon#wrote, iclass 15, count 0 2006.285.19:06:17.11#ibcon#about to read 3, iclass 15, count 0 2006.285.19:06:17.13#ibcon#read 3, iclass 15, count 0 2006.285.19:06:17.13#ibcon#about to read 4, iclass 15, count 0 2006.285.19:06:17.13#ibcon#read 4, iclass 15, count 0 2006.285.19:06:17.13#ibcon#about to read 5, iclass 15, count 0 2006.285.19:06:17.13#ibcon#read 5, iclass 15, count 0 2006.285.19:06:17.13#ibcon#about to read 6, iclass 15, count 0 2006.285.19:06:17.13#ibcon#read 6, iclass 15, count 0 2006.285.19:06:17.13#ibcon#end of sib2, iclass 15, count 0 2006.285.19:06:17.13#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:06:17.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:06:17.13#ibcon#[27=USB\r\n] 2006.285.19:06:17.13#ibcon#*before write, iclass 15, count 0 2006.285.19:06:17.13#ibcon#enter sib2, iclass 15, count 0 2006.285.19:06:17.13#ibcon#flushed, iclass 15, count 0 2006.285.19:06:17.13#ibcon#about to write, iclass 15, count 0 2006.285.19:06:17.13#ibcon#wrote, iclass 15, count 0 2006.285.19:06:17.13#ibcon#about to read 3, iclass 15, count 0 2006.285.19:06:17.16#ibcon#read 3, iclass 15, count 0 2006.285.19:06:17.16#ibcon#about to read 4, iclass 15, count 0 2006.285.19:06:17.16#ibcon#read 4, iclass 15, count 0 2006.285.19:06:17.16#ibcon#about to read 5, iclass 15, count 0 2006.285.19:06:17.16#ibcon#read 5, iclass 15, count 0 2006.285.19:06:17.16#ibcon#about to read 6, iclass 15, count 0 2006.285.19:06:17.16#ibcon#read 6, iclass 15, count 0 2006.285.19:06:17.16#ibcon#end of sib2, iclass 15, count 0 2006.285.19:06:17.16#ibcon#*after write, iclass 15, count 0 2006.285.19:06:17.16#ibcon#*before return 0, iclass 15, count 0 2006.285.19:06:17.16#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:06:17.16#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:06:17.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:06:17.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:06:17.16$vck44/vblo=5,709.99 2006.285.19:06:17.16#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.19:06:17.16#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.19:06:17.16#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:17.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:06:17.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:06:17.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:06:17.16#ibcon#enter wrdev, iclass 17, count 0 2006.285.19:06:17.16#ibcon#first serial, iclass 17, count 0 2006.285.19:06:17.16#ibcon#enter sib2, iclass 17, count 0 2006.285.19:06:17.16#ibcon#flushed, iclass 17, count 0 2006.285.19:06:17.16#ibcon#about to write, iclass 17, count 0 2006.285.19:06:17.16#ibcon#wrote, iclass 17, count 0 2006.285.19:06:17.16#ibcon#about to read 3, iclass 17, count 0 2006.285.19:06:17.18#ibcon#read 3, iclass 17, count 0 2006.285.19:06:17.28#ibcon#about to read 4, iclass 17, count 0 2006.285.19:06:17.28#ibcon#read 4, iclass 17, count 0 2006.285.19:06:17.28#ibcon#about to read 5, iclass 17, count 0 2006.285.19:06:17.28#ibcon#read 5, iclass 17, count 0 2006.285.19:06:17.28#ibcon#about to read 6, iclass 17, count 0 2006.285.19:06:17.28#ibcon#read 6, iclass 17, count 0 2006.285.19:06:17.28#ibcon#end of sib2, iclass 17, count 0 2006.285.19:06:17.28#ibcon#*mode == 0, iclass 17, count 0 2006.285.19:06:17.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.19:06:17.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.19:06:17.28#ibcon#*before write, iclass 17, count 0 2006.285.19:06:17.28#ibcon#enter sib2, iclass 17, count 0 2006.285.19:06:17.28#ibcon#flushed, iclass 17, count 0 2006.285.19:06:17.28#ibcon#about to write, iclass 17, count 0 2006.285.19:06:17.28#ibcon#wrote, iclass 17, count 0 2006.285.19:06:17.28#ibcon#about to read 3, iclass 17, count 0 2006.285.19:06:17.31#ibcon#read 3, iclass 17, count 0 2006.285.19:06:17.31#ibcon#about to read 4, iclass 17, count 0 2006.285.19:06:17.31#ibcon#read 4, iclass 17, count 0 2006.285.19:06:17.31#ibcon#about to read 5, iclass 17, count 0 2006.285.19:06:17.31#ibcon#read 5, iclass 17, count 0 2006.285.19:06:17.31#ibcon#about to read 6, iclass 17, count 0 2006.285.19:06:17.31#ibcon#read 6, iclass 17, count 0 2006.285.19:06:17.31#ibcon#end of sib2, iclass 17, count 0 2006.285.19:06:17.31#ibcon#*after write, iclass 17, count 0 2006.285.19:06:17.31#ibcon#*before return 0, iclass 17, count 0 2006.285.19:06:17.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:06:17.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:06:17.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.19:06:17.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.19:06:17.31$vck44/vb=5,4 2006.285.19:06:17.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.19:06:17.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.19:06:17.31#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:17.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:06:17.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:06:17.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:06:17.31#ibcon#enter wrdev, iclass 19, count 2 2006.285.19:06:17.31#ibcon#first serial, iclass 19, count 2 2006.285.19:06:17.31#ibcon#enter sib2, iclass 19, count 2 2006.285.19:06:17.31#ibcon#flushed, iclass 19, count 2 2006.285.19:06:17.31#ibcon#about to write, iclass 19, count 2 2006.285.19:06:17.31#ibcon#wrote, iclass 19, count 2 2006.285.19:06:17.31#ibcon#about to read 3, iclass 19, count 2 2006.285.19:06:17.33#ibcon#read 3, iclass 19, count 2 2006.285.19:06:17.33#ibcon#about to read 4, iclass 19, count 2 2006.285.19:06:17.33#ibcon#read 4, iclass 19, count 2 2006.285.19:06:17.33#ibcon#about to read 5, iclass 19, count 2 2006.285.19:06:17.33#ibcon#read 5, iclass 19, count 2 2006.285.19:06:17.33#ibcon#about to read 6, iclass 19, count 2 2006.285.19:06:17.33#ibcon#read 6, iclass 19, count 2 2006.285.19:06:17.33#ibcon#end of sib2, iclass 19, count 2 2006.285.19:06:17.33#ibcon#*mode == 0, iclass 19, count 2 2006.285.19:06:17.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.19:06:17.33#ibcon#[27=AT05-04\r\n] 2006.285.19:06:17.33#ibcon#*before write, iclass 19, count 2 2006.285.19:06:17.33#ibcon#enter sib2, iclass 19, count 2 2006.285.19:06:17.33#ibcon#flushed, iclass 19, count 2 2006.285.19:06:17.33#ibcon#about to write, iclass 19, count 2 2006.285.19:06:17.33#ibcon#wrote, iclass 19, count 2 2006.285.19:06:17.33#ibcon#about to read 3, iclass 19, count 2 2006.285.19:06:17.36#ibcon#read 3, iclass 19, count 2 2006.285.19:06:17.36#ibcon#about to read 4, iclass 19, count 2 2006.285.19:06:17.36#ibcon#read 4, iclass 19, count 2 2006.285.19:06:17.36#ibcon#about to read 5, iclass 19, count 2 2006.285.19:06:17.36#ibcon#read 5, iclass 19, count 2 2006.285.19:06:17.36#ibcon#about to read 6, iclass 19, count 2 2006.285.19:06:17.36#ibcon#read 6, iclass 19, count 2 2006.285.19:06:17.36#ibcon#end of sib2, iclass 19, count 2 2006.285.19:06:17.36#ibcon#*after write, iclass 19, count 2 2006.285.19:06:17.36#ibcon#*before return 0, iclass 19, count 2 2006.285.19:06:17.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:06:17.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:06:17.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.19:06:17.36#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:17.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:06:17.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:06:17.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:06:17.48#ibcon#enter wrdev, iclass 19, count 0 2006.285.19:06:17.48#ibcon#first serial, iclass 19, count 0 2006.285.19:06:17.48#ibcon#enter sib2, iclass 19, count 0 2006.285.19:06:17.48#ibcon#flushed, iclass 19, count 0 2006.285.19:06:17.48#ibcon#about to write, iclass 19, count 0 2006.285.19:06:17.48#ibcon#wrote, iclass 19, count 0 2006.285.19:06:17.48#ibcon#about to read 3, iclass 19, count 0 2006.285.19:06:17.50#ibcon#read 3, iclass 19, count 0 2006.285.19:06:17.50#ibcon#about to read 4, iclass 19, count 0 2006.285.19:06:17.50#ibcon#read 4, iclass 19, count 0 2006.285.19:06:17.50#ibcon#about to read 5, iclass 19, count 0 2006.285.19:06:17.50#ibcon#read 5, iclass 19, count 0 2006.285.19:06:17.50#ibcon#about to read 6, iclass 19, count 0 2006.285.19:06:17.50#ibcon#read 6, iclass 19, count 0 2006.285.19:06:17.50#ibcon#end of sib2, iclass 19, count 0 2006.285.19:06:17.50#ibcon#*mode == 0, iclass 19, count 0 2006.285.19:06:17.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.19:06:17.50#ibcon#[27=USB\r\n] 2006.285.19:06:17.50#ibcon#*before write, iclass 19, count 0 2006.285.19:06:17.50#ibcon#enter sib2, iclass 19, count 0 2006.285.19:06:17.50#ibcon#flushed, iclass 19, count 0 2006.285.19:06:17.50#ibcon#about to write, iclass 19, count 0 2006.285.19:06:17.50#ibcon#wrote, iclass 19, count 0 2006.285.19:06:17.50#ibcon#about to read 3, iclass 19, count 0 2006.285.19:06:17.53#ibcon#read 3, iclass 19, count 0 2006.285.19:06:17.53#ibcon#about to read 4, iclass 19, count 0 2006.285.19:06:17.53#ibcon#read 4, iclass 19, count 0 2006.285.19:06:17.53#ibcon#about to read 5, iclass 19, count 0 2006.285.19:06:17.53#ibcon#read 5, iclass 19, count 0 2006.285.19:06:17.53#ibcon#about to read 6, iclass 19, count 0 2006.285.19:06:17.53#ibcon#read 6, iclass 19, count 0 2006.285.19:06:17.53#ibcon#end of sib2, iclass 19, count 0 2006.285.19:06:17.53#ibcon#*after write, iclass 19, count 0 2006.285.19:06:17.53#ibcon#*before return 0, iclass 19, count 0 2006.285.19:06:17.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:06:17.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:06:17.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.19:06:17.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.19:06:17.53$vck44/vblo=6,719.99 2006.285.19:06:17.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.19:06:17.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.19:06:17.53#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:17.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:06:17.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:06:17.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:06:17.53#ibcon#enter wrdev, iclass 21, count 0 2006.285.19:06:17.53#ibcon#first serial, iclass 21, count 0 2006.285.19:06:17.53#ibcon#enter sib2, iclass 21, count 0 2006.285.19:06:17.53#ibcon#flushed, iclass 21, count 0 2006.285.19:06:17.53#ibcon#about to write, iclass 21, count 0 2006.285.19:06:17.53#ibcon#wrote, iclass 21, count 0 2006.285.19:06:17.53#ibcon#about to read 3, iclass 21, count 0 2006.285.19:06:17.55#ibcon#read 3, iclass 21, count 0 2006.285.19:06:17.55#ibcon#about to read 4, iclass 21, count 0 2006.285.19:06:17.55#ibcon#read 4, iclass 21, count 0 2006.285.19:06:17.55#ibcon#about to read 5, iclass 21, count 0 2006.285.19:06:17.55#ibcon#read 5, iclass 21, count 0 2006.285.19:06:17.55#ibcon#about to read 6, iclass 21, count 0 2006.285.19:06:17.55#ibcon#read 6, iclass 21, count 0 2006.285.19:06:17.55#ibcon#end of sib2, iclass 21, count 0 2006.285.19:06:17.55#ibcon#*mode == 0, iclass 21, count 0 2006.285.19:06:17.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.19:06:17.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.19:06:17.55#ibcon#*before write, iclass 21, count 0 2006.285.19:06:17.55#ibcon#enter sib2, iclass 21, count 0 2006.285.19:06:17.55#ibcon#flushed, iclass 21, count 0 2006.285.19:06:17.55#ibcon#about to write, iclass 21, count 0 2006.285.19:06:17.55#ibcon#wrote, iclass 21, count 0 2006.285.19:06:17.55#ibcon#about to read 3, iclass 21, count 0 2006.285.19:06:17.59#ibcon#read 3, iclass 21, count 0 2006.285.19:06:17.59#ibcon#about to read 4, iclass 21, count 0 2006.285.19:06:17.59#ibcon#read 4, iclass 21, count 0 2006.285.19:06:17.59#ibcon#about to read 5, iclass 21, count 0 2006.285.19:06:17.59#ibcon#read 5, iclass 21, count 0 2006.285.19:06:17.59#ibcon#about to read 6, iclass 21, count 0 2006.285.19:06:17.59#ibcon#read 6, iclass 21, count 0 2006.285.19:06:17.59#ibcon#end of sib2, iclass 21, count 0 2006.285.19:06:17.59#ibcon#*after write, iclass 21, count 0 2006.285.19:06:17.59#ibcon#*before return 0, iclass 21, count 0 2006.285.19:06:17.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:06:17.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:06:17.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.19:06:17.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.19:06:17.59$vck44/vb=6,3 2006.285.19:06:17.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.19:06:17.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.19:06:17.59#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:17.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:06:17.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:06:17.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:06:17.65#ibcon#enter wrdev, iclass 23, count 2 2006.285.19:06:17.65#ibcon#first serial, iclass 23, count 2 2006.285.19:06:17.65#ibcon#enter sib2, iclass 23, count 2 2006.285.19:06:17.65#ibcon#flushed, iclass 23, count 2 2006.285.19:06:17.65#ibcon#about to write, iclass 23, count 2 2006.285.19:06:17.65#ibcon#wrote, iclass 23, count 2 2006.285.19:06:17.65#ibcon#about to read 3, iclass 23, count 2 2006.285.19:06:17.67#ibcon#read 3, iclass 23, count 2 2006.285.19:06:17.67#ibcon#about to read 4, iclass 23, count 2 2006.285.19:06:17.67#ibcon#read 4, iclass 23, count 2 2006.285.19:06:17.67#ibcon#about to read 5, iclass 23, count 2 2006.285.19:06:17.67#ibcon#read 5, iclass 23, count 2 2006.285.19:06:17.67#ibcon#about to read 6, iclass 23, count 2 2006.285.19:06:17.67#ibcon#read 6, iclass 23, count 2 2006.285.19:06:17.67#ibcon#end of sib2, iclass 23, count 2 2006.285.19:06:17.67#ibcon#*mode == 0, iclass 23, count 2 2006.285.19:06:17.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.19:06:17.67#ibcon#[27=AT06-03\r\n] 2006.285.19:06:17.67#ibcon#*before write, iclass 23, count 2 2006.285.19:06:17.67#ibcon#enter sib2, iclass 23, count 2 2006.285.19:06:17.67#ibcon#flushed, iclass 23, count 2 2006.285.19:06:17.67#ibcon#about to write, iclass 23, count 2 2006.285.19:06:17.67#ibcon#wrote, iclass 23, count 2 2006.285.19:06:17.67#ibcon#about to read 3, iclass 23, count 2 2006.285.19:06:17.70#ibcon#read 3, iclass 23, count 2 2006.285.19:06:17.70#ibcon#about to read 4, iclass 23, count 2 2006.285.19:06:17.70#ibcon#read 4, iclass 23, count 2 2006.285.19:06:17.70#ibcon#about to read 5, iclass 23, count 2 2006.285.19:06:17.70#ibcon#read 5, iclass 23, count 2 2006.285.19:06:17.70#ibcon#about to read 6, iclass 23, count 2 2006.285.19:06:17.70#ibcon#read 6, iclass 23, count 2 2006.285.19:06:17.70#ibcon#end of sib2, iclass 23, count 2 2006.285.19:06:17.70#ibcon#*after write, iclass 23, count 2 2006.285.19:06:17.70#ibcon#*before return 0, iclass 23, count 2 2006.285.19:06:17.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:06:17.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:06:17.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.19:06:17.70#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:17.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:06:17.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:06:17.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:06:17.82#ibcon#enter wrdev, iclass 23, count 0 2006.285.19:06:17.82#ibcon#first serial, iclass 23, count 0 2006.285.19:06:17.82#ibcon#enter sib2, iclass 23, count 0 2006.285.19:06:17.82#ibcon#flushed, iclass 23, count 0 2006.285.19:06:17.82#ibcon#about to write, iclass 23, count 0 2006.285.19:06:17.82#ibcon#wrote, iclass 23, count 0 2006.285.19:06:17.82#ibcon#about to read 3, iclass 23, count 0 2006.285.19:06:17.84#ibcon#read 3, iclass 23, count 0 2006.285.19:06:17.84#ibcon#about to read 4, iclass 23, count 0 2006.285.19:06:17.84#ibcon#read 4, iclass 23, count 0 2006.285.19:06:17.84#ibcon#about to read 5, iclass 23, count 0 2006.285.19:06:17.84#ibcon#read 5, iclass 23, count 0 2006.285.19:06:17.84#ibcon#about to read 6, iclass 23, count 0 2006.285.19:06:17.84#ibcon#read 6, iclass 23, count 0 2006.285.19:06:17.84#ibcon#end of sib2, iclass 23, count 0 2006.285.19:06:17.84#ibcon#*mode == 0, iclass 23, count 0 2006.285.19:06:17.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.19:06:17.84#ibcon#[27=USB\r\n] 2006.285.19:06:17.84#ibcon#*before write, iclass 23, count 0 2006.285.19:06:17.84#ibcon#enter sib2, iclass 23, count 0 2006.285.19:06:17.84#ibcon#flushed, iclass 23, count 0 2006.285.19:06:17.84#ibcon#about to write, iclass 23, count 0 2006.285.19:06:17.84#ibcon#wrote, iclass 23, count 0 2006.285.19:06:17.84#ibcon#about to read 3, iclass 23, count 0 2006.285.19:06:17.87#ibcon#read 3, iclass 23, count 0 2006.285.19:06:17.87#ibcon#about to read 4, iclass 23, count 0 2006.285.19:06:17.87#ibcon#read 4, iclass 23, count 0 2006.285.19:06:17.87#ibcon#about to read 5, iclass 23, count 0 2006.285.19:06:17.87#ibcon#read 5, iclass 23, count 0 2006.285.19:06:17.87#ibcon#about to read 6, iclass 23, count 0 2006.285.19:06:17.87#ibcon#read 6, iclass 23, count 0 2006.285.19:06:17.87#ibcon#end of sib2, iclass 23, count 0 2006.285.19:06:17.87#ibcon#*after write, iclass 23, count 0 2006.285.19:06:17.87#ibcon#*before return 0, iclass 23, count 0 2006.285.19:06:17.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:06:17.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:06:17.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.19:06:17.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.19:06:17.87$vck44/vblo=7,734.99 2006.285.19:06:17.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.19:06:17.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.19:06:17.87#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:17.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.19:06:17.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.19:06:17.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.19:06:17.87#ibcon#enter wrdev, iclass 25, count 0 2006.285.19:06:17.87#ibcon#first serial, iclass 25, count 0 2006.285.19:06:17.87#ibcon#enter sib2, iclass 25, count 0 2006.285.19:06:17.87#ibcon#flushed, iclass 25, count 0 2006.285.19:06:17.87#ibcon#about to write, iclass 25, count 0 2006.285.19:06:17.87#ibcon#wrote, iclass 25, count 0 2006.285.19:06:17.87#ibcon#about to read 3, iclass 25, count 0 2006.285.19:06:17.89#ibcon#read 3, iclass 25, count 0 2006.285.19:06:17.89#ibcon#about to read 4, iclass 25, count 0 2006.285.19:06:17.89#ibcon#read 4, iclass 25, count 0 2006.285.19:06:17.89#ibcon#about to read 5, iclass 25, count 0 2006.285.19:06:17.89#ibcon#read 5, iclass 25, count 0 2006.285.19:06:17.89#ibcon#about to read 6, iclass 25, count 0 2006.285.19:06:17.89#ibcon#read 6, iclass 25, count 0 2006.285.19:06:17.89#ibcon#end of sib2, iclass 25, count 0 2006.285.19:06:17.89#ibcon#*mode == 0, iclass 25, count 0 2006.285.19:06:17.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.19:06:17.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.19:06:17.89#ibcon#*before write, iclass 25, count 0 2006.285.19:06:17.89#ibcon#enter sib2, iclass 25, count 0 2006.285.19:06:17.89#ibcon#flushed, iclass 25, count 0 2006.285.19:06:17.89#ibcon#about to write, iclass 25, count 0 2006.285.19:06:17.89#ibcon#wrote, iclass 25, count 0 2006.285.19:06:17.89#ibcon#about to read 3, iclass 25, count 0 2006.285.19:06:17.93#ibcon#read 3, iclass 25, count 0 2006.285.19:06:17.93#ibcon#about to read 4, iclass 25, count 0 2006.285.19:06:17.93#ibcon#read 4, iclass 25, count 0 2006.285.19:06:17.93#ibcon#about to read 5, iclass 25, count 0 2006.285.19:06:17.93#ibcon#read 5, iclass 25, count 0 2006.285.19:06:17.93#ibcon#about to read 6, iclass 25, count 0 2006.285.19:06:17.93#ibcon#read 6, iclass 25, count 0 2006.285.19:06:17.93#ibcon#end of sib2, iclass 25, count 0 2006.285.19:06:17.93#ibcon#*after write, iclass 25, count 0 2006.285.19:06:17.93#ibcon#*before return 0, iclass 25, count 0 2006.285.19:06:17.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.19:06:17.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.19:06:17.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.19:06:17.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.19:06:17.93$vck44/vb=7,4 2006.285.19:06:17.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.19:06:17.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.19:06:17.93#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:17.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.19:06:17.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.19:06:17.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.19:06:17.99#ibcon#enter wrdev, iclass 27, count 2 2006.285.19:06:17.99#ibcon#first serial, iclass 27, count 2 2006.285.19:06:17.99#ibcon#enter sib2, iclass 27, count 2 2006.285.19:06:17.99#ibcon#flushed, iclass 27, count 2 2006.285.19:06:17.99#ibcon#about to write, iclass 27, count 2 2006.285.19:06:17.99#ibcon#wrote, iclass 27, count 2 2006.285.19:06:17.99#ibcon#about to read 3, iclass 27, count 2 2006.285.19:06:18.01#ibcon#read 3, iclass 27, count 2 2006.285.19:06:18.01#ibcon#about to read 4, iclass 27, count 2 2006.285.19:06:18.01#ibcon#read 4, iclass 27, count 2 2006.285.19:06:18.01#ibcon#about to read 5, iclass 27, count 2 2006.285.19:06:18.01#ibcon#read 5, iclass 27, count 2 2006.285.19:06:18.01#ibcon#about to read 6, iclass 27, count 2 2006.285.19:06:18.01#ibcon#read 6, iclass 27, count 2 2006.285.19:06:18.01#ibcon#end of sib2, iclass 27, count 2 2006.285.19:06:18.01#ibcon#*mode == 0, iclass 27, count 2 2006.285.19:06:18.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.19:06:18.01#ibcon#[27=AT07-04\r\n] 2006.285.19:06:18.01#ibcon#*before write, iclass 27, count 2 2006.285.19:06:18.01#ibcon#enter sib2, iclass 27, count 2 2006.285.19:06:18.01#ibcon#flushed, iclass 27, count 2 2006.285.19:06:18.01#ibcon#about to write, iclass 27, count 2 2006.285.19:06:18.01#ibcon#wrote, iclass 27, count 2 2006.285.19:06:18.01#ibcon#about to read 3, iclass 27, count 2 2006.285.19:06:18.04#ibcon#read 3, iclass 27, count 2 2006.285.19:06:18.04#ibcon#about to read 4, iclass 27, count 2 2006.285.19:06:18.04#ibcon#read 4, iclass 27, count 2 2006.285.19:06:18.04#ibcon#about to read 5, iclass 27, count 2 2006.285.19:06:18.04#ibcon#read 5, iclass 27, count 2 2006.285.19:06:18.04#ibcon#about to read 6, iclass 27, count 2 2006.285.19:06:18.04#ibcon#read 6, iclass 27, count 2 2006.285.19:06:18.04#ibcon#end of sib2, iclass 27, count 2 2006.285.19:06:18.04#ibcon#*after write, iclass 27, count 2 2006.285.19:06:18.04#ibcon#*before return 0, iclass 27, count 2 2006.285.19:06:18.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.19:06:18.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.19:06:18.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.19:06:18.04#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:18.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.19:06:18.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.19:06:18.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.19:06:18.16#ibcon#enter wrdev, iclass 27, count 0 2006.285.19:06:18.16#ibcon#first serial, iclass 27, count 0 2006.285.19:06:18.16#ibcon#enter sib2, iclass 27, count 0 2006.285.19:06:18.16#ibcon#flushed, iclass 27, count 0 2006.285.19:06:18.16#ibcon#about to write, iclass 27, count 0 2006.285.19:06:18.16#ibcon#wrote, iclass 27, count 0 2006.285.19:06:18.16#ibcon#about to read 3, iclass 27, count 0 2006.285.19:06:18.18#ibcon#read 3, iclass 27, count 0 2006.285.19:06:18.18#ibcon#about to read 4, iclass 27, count 0 2006.285.19:06:18.18#ibcon#read 4, iclass 27, count 0 2006.285.19:06:18.18#ibcon#about to read 5, iclass 27, count 0 2006.285.19:06:18.18#ibcon#read 5, iclass 27, count 0 2006.285.19:06:18.18#ibcon#about to read 6, iclass 27, count 0 2006.285.19:06:18.18#ibcon#read 6, iclass 27, count 0 2006.285.19:06:18.18#ibcon#end of sib2, iclass 27, count 0 2006.285.19:06:18.18#ibcon#*mode == 0, iclass 27, count 0 2006.285.19:06:18.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.19:06:18.18#ibcon#[27=USB\r\n] 2006.285.19:06:18.18#ibcon#*before write, iclass 27, count 0 2006.285.19:06:18.18#ibcon#enter sib2, iclass 27, count 0 2006.285.19:06:18.18#ibcon#flushed, iclass 27, count 0 2006.285.19:06:18.18#ibcon#about to write, iclass 27, count 0 2006.285.19:06:18.18#ibcon#wrote, iclass 27, count 0 2006.285.19:06:18.18#ibcon#about to read 3, iclass 27, count 0 2006.285.19:06:18.21#ibcon#read 3, iclass 27, count 0 2006.285.19:06:18.21#ibcon#about to read 4, iclass 27, count 0 2006.285.19:06:18.21#ibcon#read 4, iclass 27, count 0 2006.285.19:06:18.21#ibcon#about to read 5, iclass 27, count 0 2006.285.19:06:18.21#ibcon#read 5, iclass 27, count 0 2006.285.19:06:18.21#ibcon#about to read 6, iclass 27, count 0 2006.285.19:06:18.21#ibcon#read 6, iclass 27, count 0 2006.285.19:06:18.21#ibcon#end of sib2, iclass 27, count 0 2006.285.19:06:18.21#ibcon#*after write, iclass 27, count 0 2006.285.19:06:18.21#ibcon#*before return 0, iclass 27, count 0 2006.285.19:06:18.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.19:06:18.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.19:06:18.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.19:06:18.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.19:06:18.21$vck44/vblo=8,744.99 2006.285.19:06:18.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.19:06:18.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.19:06:18.21#ibcon#ireg 17 cls_cnt 0 2006.285.19:06:18.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:06:18.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:06:18.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:06:18.21#ibcon#enter wrdev, iclass 29, count 0 2006.285.19:06:18.21#ibcon#first serial, iclass 29, count 0 2006.285.19:06:18.21#ibcon#enter sib2, iclass 29, count 0 2006.285.19:06:18.21#ibcon#flushed, iclass 29, count 0 2006.285.19:06:18.21#ibcon#about to write, iclass 29, count 0 2006.285.19:06:18.21#ibcon#wrote, iclass 29, count 0 2006.285.19:06:18.21#ibcon#about to read 3, iclass 29, count 0 2006.285.19:06:18.23#ibcon#read 3, iclass 29, count 0 2006.285.19:06:18.23#ibcon#about to read 4, iclass 29, count 0 2006.285.19:06:18.23#ibcon#read 4, iclass 29, count 0 2006.285.19:06:18.23#ibcon#about to read 5, iclass 29, count 0 2006.285.19:06:18.23#ibcon#read 5, iclass 29, count 0 2006.285.19:06:18.23#ibcon#about to read 6, iclass 29, count 0 2006.285.19:06:18.23#ibcon#read 6, iclass 29, count 0 2006.285.19:06:18.23#ibcon#end of sib2, iclass 29, count 0 2006.285.19:06:18.23#ibcon#*mode == 0, iclass 29, count 0 2006.285.19:06:18.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.19:06:18.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.19:06:18.23#ibcon#*before write, iclass 29, count 0 2006.285.19:06:18.23#ibcon#enter sib2, iclass 29, count 0 2006.285.19:06:18.23#ibcon#flushed, iclass 29, count 0 2006.285.19:06:18.23#ibcon#about to write, iclass 29, count 0 2006.285.19:06:18.23#ibcon#wrote, iclass 29, count 0 2006.285.19:06:18.23#ibcon#about to read 3, iclass 29, count 0 2006.285.19:06:18.27#ibcon#read 3, iclass 29, count 0 2006.285.19:06:18.27#ibcon#about to read 4, iclass 29, count 0 2006.285.19:06:18.27#ibcon#read 4, iclass 29, count 0 2006.285.19:06:18.27#ibcon#about to read 5, iclass 29, count 0 2006.285.19:06:18.27#ibcon#read 5, iclass 29, count 0 2006.285.19:06:18.27#ibcon#about to read 6, iclass 29, count 0 2006.285.19:06:18.27#ibcon#read 6, iclass 29, count 0 2006.285.19:06:18.27#ibcon#end of sib2, iclass 29, count 0 2006.285.19:06:18.27#ibcon#*after write, iclass 29, count 0 2006.285.19:06:18.27#ibcon#*before return 0, iclass 29, count 0 2006.285.19:06:18.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:06:18.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:06:18.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.19:06:18.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.19:06:18.27$vck44/vb=8,4 2006.285.19:06:18.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.19:06:18.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.19:06:18.27#ibcon#ireg 11 cls_cnt 2 2006.285.19:06:18.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:06:18.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:06:18.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:06:18.33#ibcon#enter wrdev, iclass 31, count 2 2006.285.19:06:18.33#ibcon#first serial, iclass 31, count 2 2006.285.19:06:18.33#ibcon#enter sib2, iclass 31, count 2 2006.285.19:06:18.33#ibcon#flushed, iclass 31, count 2 2006.285.19:06:18.33#ibcon#about to write, iclass 31, count 2 2006.285.19:06:18.33#ibcon#wrote, iclass 31, count 2 2006.285.19:06:18.33#ibcon#about to read 3, iclass 31, count 2 2006.285.19:06:18.35#ibcon#read 3, iclass 31, count 2 2006.285.19:06:18.35#ibcon#about to read 4, iclass 31, count 2 2006.285.19:06:18.35#ibcon#read 4, iclass 31, count 2 2006.285.19:06:18.35#ibcon#about to read 5, iclass 31, count 2 2006.285.19:06:18.35#ibcon#read 5, iclass 31, count 2 2006.285.19:06:18.35#ibcon#about to read 6, iclass 31, count 2 2006.285.19:06:18.35#ibcon#read 6, iclass 31, count 2 2006.285.19:06:18.35#ibcon#end of sib2, iclass 31, count 2 2006.285.19:06:18.35#ibcon#*mode == 0, iclass 31, count 2 2006.285.19:06:18.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.19:06:18.35#ibcon#[27=AT08-04\r\n] 2006.285.19:06:18.35#ibcon#*before write, iclass 31, count 2 2006.285.19:06:18.35#ibcon#enter sib2, iclass 31, count 2 2006.285.19:06:18.35#ibcon#flushed, iclass 31, count 2 2006.285.19:06:18.35#ibcon#about to write, iclass 31, count 2 2006.285.19:06:18.35#ibcon#wrote, iclass 31, count 2 2006.285.19:06:18.35#ibcon#about to read 3, iclass 31, count 2 2006.285.19:06:18.38#ibcon#read 3, iclass 31, count 2 2006.285.19:06:18.38#ibcon#about to read 4, iclass 31, count 2 2006.285.19:06:18.38#ibcon#read 4, iclass 31, count 2 2006.285.19:06:18.38#ibcon#about to read 5, iclass 31, count 2 2006.285.19:06:18.38#ibcon#read 5, iclass 31, count 2 2006.285.19:06:18.38#ibcon#about to read 6, iclass 31, count 2 2006.285.19:06:18.38#ibcon#read 6, iclass 31, count 2 2006.285.19:06:18.38#ibcon#end of sib2, iclass 31, count 2 2006.285.19:06:18.38#ibcon#*after write, iclass 31, count 2 2006.285.19:06:18.38#ibcon#*before return 0, iclass 31, count 2 2006.285.19:06:18.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:06:18.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:06:18.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.19:06:18.38#ibcon#ireg 7 cls_cnt 0 2006.285.19:06:18.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:06:18.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:06:18.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:06:18.50#ibcon#enter wrdev, iclass 31, count 0 2006.285.19:06:18.50#ibcon#first serial, iclass 31, count 0 2006.285.19:06:18.50#ibcon#enter sib2, iclass 31, count 0 2006.285.19:06:18.50#ibcon#flushed, iclass 31, count 0 2006.285.19:06:18.50#ibcon#about to write, iclass 31, count 0 2006.285.19:06:18.50#ibcon#wrote, iclass 31, count 0 2006.285.19:06:18.50#ibcon#about to read 3, iclass 31, count 0 2006.285.19:06:18.52#ibcon#read 3, iclass 31, count 0 2006.285.19:06:18.52#ibcon#about to read 4, iclass 31, count 0 2006.285.19:06:18.52#ibcon#read 4, iclass 31, count 0 2006.285.19:06:18.52#ibcon#about to read 5, iclass 31, count 0 2006.285.19:06:18.52#ibcon#read 5, iclass 31, count 0 2006.285.19:06:18.52#ibcon#about to read 6, iclass 31, count 0 2006.285.19:06:18.52#ibcon#read 6, iclass 31, count 0 2006.285.19:06:18.52#ibcon#end of sib2, iclass 31, count 0 2006.285.19:06:18.52#ibcon#*mode == 0, iclass 31, count 0 2006.285.19:06:18.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.19:06:18.52#ibcon#[27=USB\r\n] 2006.285.19:06:18.52#ibcon#*before write, iclass 31, count 0 2006.285.19:06:18.52#ibcon#enter sib2, iclass 31, count 0 2006.285.19:06:18.52#ibcon#flushed, iclass 31, count 0 2006.285.19:06:18.52#ibcon#about to write, iclass 31, count 0 2006.285.19:06:18.52#ibcon#wrote, iclass 31, count 0 2006.285.19:06:18.52#ibcon#about to read 3, iclass 31, count 0 2006.285.19:06:18.55#ibcon#read 3, iclass 31, count 0 2006.285.19:06:18.55#ibcon#about to read 4, iclass 31, count 0 2006.285.19:06:18.55#ibcon#read 4, iclass 31, count 0 2006.285.19:06:18.55#ibcon#about to read 5, iclass 31, count 0 2006.285.19:06:18.55#ibcon#read 5, iclass 31, count 0 2006.285.19:06:18.55#ibcon#about to read 6, iclass 31, count 0 2006.285.19:06:18.55#ibcon#read 6, iclass 31, count 0 2006.285.19:06:18.55#ibcon#end of sib2, iclass 31, count 0 2006.285.19:06:18.55#ibcon#*after write, iclass 31, count 0 2006.285.19:06:18.55#ibcon#*before return 0, iclass 31, count 0 2006.285.19:06:18.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:06:18.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:06:18.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.19:06:18.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.19:06:18.55$vck44/vabw=wide 2006.285.19:06:18.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.19:06:18.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.19:06:18.55#ibcon#ireg 8 cls_cnt 0 2006.285.19:06:18.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:06:18.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:06:18.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:06:18.55#ibcon#enter wrdev, iclass 33, count 0 2006.285.19:06:18.55#ibcon#first serial, iclass 33, count 0 2006.285.19:06:18.55#ibcon#enter sib2, iclass 33, count 0 2006.285.19:06:18.55#ibcon#flushed, iclass 33, count 0 2006.285.19:06:18.55#ibcon#about to write, iclass 33, count 0 2006.285.19:06:18.55#ibcon#wrote, iclass 33, count 0 2006.285.19:06:18.55#ibcon#about to read 3, iclass 33, count 0 2006.285.19:06:18.57#ibcon#read 3, iclass 33, count 0 2006.285.19:06:18.57#ibcon#about to read 4, iclass 33, count 0 2006.285.19:06:18.57#ibcon#read 4, iclass 33, count 0 2006.285.19:06:18.57#ibcon#about to read 5, iclass 33, count 0 2006.285.19:06:18.57#ibcon#read 5, iclass 33, count 0 2006.285.19:06:18.57#ibcon#about to read 6, iclass 33, count 0 2006.285.19:06:18.57#ibcon#read 6, iclass 33, count 0 2006.285.19:06:18.57#ibcon#end of sib2, iclass 33, count 0 2006.285.19:06:18.57#ibcon#*mode == 0, iclass 33, count 0 2006.285.19:06:18.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.19:06:18.57#ibcon#[25=BW32\r\n] 2006.285.19:06:18.57#ibcon#*before write, iclass 33, count 0 2006.285.19:06:18.57#ibcon#enter sib2, iclass 33, count 0 2006.285.19:06:18.57#ibcon#flushed, iclass 33, count 0 2006.285.19:06:18.57#ibcon#about to write, iclass 33, count 0 2006.285.19:06:18.57#ibcon#wrote, iclass 33, count 0 2006.285.19:06:18.57#ibcon#about to read 3, iclass 33, count 0 2006.285.19:06:18.60#ibcon#read 3, iclass 33, count 0 2006.285.19:06:18.60#ibcon#about to read 4, iclass 33, count 0 2006.285.19:06:18.60#ibcon#read 4, iclass 33, count 0 2006.285.19:06:18.60#ibcon#about to read 5, iclass 33, count 0 2006.285.19:06:18.60#ibcon#read 5, iclass 33, count 0 2006.285.19:06:18.60#ibcon#about to read 6, iclass 33, count 0 2006.285.19:06:18.60#ibcon#read 6, iclass 33, count 0 2006.285.19:06:18.60#ibcon#end of sib2, iclass 33, count 0 2006.285.19:06:18.60#ibcon#*after write, iclass 33, count 0 2006.285.19:06:18.60#ibcon#*before return 0, iclass 33, count 0 2006.285.19:06:18.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:06:18.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:06:18.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.19:06:18.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.19:06:18.60$vck44/vbbw=wide 2006.285.19:06:18.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.19:06:18.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.19:06:18.60#ibcon#ireg 8 cls_cnt 0 2006.285.19:06:18.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:06:18.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:06:18.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:06:18.67#ibcon#enter wrdev, iclass 35, count 0 2006.285.19:06:18.67#ibcon#first serial, iclass 35, count 0 2006.285.19:06:18.67#ibcon#enter sib2, iclass 35, count 0 2006.285.19:06:18.67#ibcon#flushed, iclass 35, count 0 2006.285.19:06:18.67#ibcon#about to write, iclass 35, count 0 2006.285.19:06:18.67#ibcon#wrote, iclass 35, count 0 2006.285.19:06:18.67#ibcon#about to read 3, iclass 35, count 0 2006.285.19:06:18.69#ibcon#read 3, iclass 35, count 0 2006.285.19:06:18.69#ibcon#about to read 4, iclass 35, count 0 2006.285.19:06:18.69#ibcon#read 4, iclass 35, count 0 2006.285.19:06:18.69#ibcon#about to read 5, iclass 35, count 0 2006.285.19:06:18.69#ibcon#read 5, iclass 35, count 0 2006.285.19:06:18.69#ibcon#about to read 6, iclass 35, count 0 2006.285.19:06:18.69#ibcon#read 6, iclass 35, count 0 2006.285.19:06:18.69#ibcon#end of sib2, iclass 35, count 0 2006.285.19:06:18.69#ibcon#*mode == 0, iclass 35, count 0 2006.285.19:06:18.69#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.19:06:18.69#ibcon#[27=BW32\r\n] 2006.285.19:06:18.69#ibcon#*before write, iclass 35, count 0 2006.285.19:06:18.69#ibcon#enter sib2, iclass 35, count 0 2006.285.19:06:18.69#ibcon#flushed, iclass 35, count 0 2006.285.19:06:18.69#ibcon#about to write, iclass 35, count 0 2006.285.19:06:18.69#ibcon#wrote, iclass 35, count 0 2006.285.19:06:18.69#ibcon#about to read 3, iclass 35, count 0 2006.285.19:06:18.72#ibcon#read 3, iclass 35, count 0 2006.285.19:06:18.72#ibcon#about to read 4, iclass 35, count 0 2006.285.19:06:18.72#ibcon#read 4, iclass 35, count 0 2006.285.19:06:18.72#ibcon#about to read 5, iclass 35, count 0 2006.285.19:06:18.72#ibcon#read 5, iclass 35, count 0 2006.285.19:06:18.72#ibcon#about to read 6, iclass 35, count 0 2006.285.19:06:18.72#ibcon#read 6, iclass 35, count 0 2006.285.19:06:18.72#ibcon#end of sib2, iclass 35, count 0 2006.285.19:06:18.72#ibcon#*after write, iclass 35, count 0 2006.285.19:06:18.72#ibcon#*before return 0, iclass 35, count 0 2006.285.19:06:18.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:06:18.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:06:18.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.19:06:18.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.19:06:18.72$setupk4/ifdk4 2006.285.19:06:18.72$ifdk4/lo= 2006.285.19:06:18.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.19:06:18.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.19:06:18.72$ifdk4/patch= 2006.285.19:06:18.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.19:06:18.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.19:06:18.72$setupk4/!*+20s 2006.285.19:06:24.75#abcon#<5=/15 0.6 1.4 15.021001014.9\r\n> 2006.285.19:06:24.77#abcon#{5=INTERFACE CLEAR} 2006.285.19:06:24.83#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:06:32.14$setupk4/"tpicd 2006.285.19:06:32.14$setupk4/echo=off 2006.285.19:06:32.14$setupk4/xlog=off 2006.285.19:06:32.14:!2006.285.19:09:39 2006.285.19:07:07.14#trakl#Source acquired 2006.285.19:07:09.14#flagr#flagr/antenna,acquired 2006.285.19:09:39.00:preob 2006.285.19:09:40.13/onsource/TRACKING 2006.285.19:09:40.13:!2006.285.19:09:49 2006.285.19:09:49.00:"tape 2006.285.19:09:49.00:"st=record 2006.285.19:09:49.00:data_valid=on 2006.285.19:09:49.00:midob 2006.285.19:09:49.13/onsource/TRACKING 2006.285.19:09:49.14/wx/14.99,1014.9,100 2006.285.19:09:49.32/cable/+6.5064E-03 2006.285.19:09:50.41/va/01,07,usb,yes,32,35 2006.285.19:09:50.41/va/02,06,usb,yes,32,33 2006.285.19:09:50.41/va/03,07,usb,yes,32,34 2006.285.19:09:50.41/va/04,06,usb,yes,34,35 2006.285.19:09:50.41/va/05,03,usb,yes,33,33 2006.285.19:09:50.41/va/06,04,usb,yes,30,29 2006.285.19:09:50.41/va/07,04,usb,yes,30,31 2006.285.19:09:50.41/va/08,03,usb,yes,31,38 2006.285.19:09:50.64/valo/01,524.99,yes,locked 2006.285.19:09:50.64/valo/02,534.99,yes,locked 2006.285.19:09:50.64/valo/03,564.99,yes,locked 2006.285.19:09:50.64/valo/04,624.99,yes,locked 2006.285.19:09:50.64/valo/05,734.99,yes,locked 2006.285.19:09:50.64/valo/06,814.99,yes,locked 2006.285.19:09:50.64/valo/07,864.99,yes,locked 2006.285.19:09:50.64/valo/08,884.99,yes,locked 2006.285.19:09:51.73/vb/01,04,usb,yes,30,28 2006.285.19:09:51.73/vb/02,05,usb,yes,29,29 2006.285.19:09:51.73/vb/03,04,usb,yes,30,33 2006.285.19:09:51.73/vb/04,05,usb,yes,30,29 2006.285.19:09:51.73/vb/05,04,usb,yes,26,29 2006.285.19:09:51.73/vb/06,03,usb,yes,38,34 2006.285.19:09:51.73/vb/07,04,usb,yes,31,30 2006.285.19:09:51.73/vb/08,04,usb,yes,28,31 2006.285.19:09:51.96/vblo/01,629.99,yes,locked 2006.285.19:09:51.96/vblo/02,634.99,yes,locked 2006.285.19:09:51.96/vblo/03,649.99,yes,locked 2006.285.19:09:51.96/vblo/04,679.99,yes,locked 2006.285.19:09:51.96/vblo/05,709.99,yes,locked 2006.285.19:09:51.96/vblo/06,719.99,yes,locked 2006.285.19:09:51.96/vblo/07,734.99,yes,locked 2006.285.19:09:51.96/vblo/08,744.99,yes,locked 2006.285.19:09:52.11/vabw/8 2006.285.19:09:52.26/vbbw/8 2006.285.19:09:52.35/xfe/off,on,12.0 2006.285.19:09:52.74/ifatt/23,28,28,28 2006.285.19:09:53.07/fmout-gps/S +2.63E-07 2006.285.19:09:53.09:!2006.285.19:10:49 2006.285.19:10:49.00:data_valid=off 2006.285.19:10:49.00:"et 2006.285.19:10:49.00:!+3s 2006.285.19:10:52.01:"tape 2006.285.19:10:52.01:postob 2006.285.19:10:52.22/cable/+6.5071E-03 2006.285.19:10:52.22/wx/15.00,1014.9,100 2006.285.19:10:53.07/fmout-gps/S +2.62E-07 2006.285.19:10:53.07:scan_name=285-1912,jd0610,100 2006.285.19:10:53.07:source=0528+134,053056.42,133155.1,2000.0,cw 2006.285.19:10:53.14#flagr#flagr/antenna,new-source 2006.285.19:10:54.14:checkk5 2006.285.19:10:54.65/chk_autoobs//k5ts1/ autoobs is running! 2006.285.19:10:55.36/chk_autoobs//k5ts2/ autoobs is running! 2006.285.19:10:55.80/chk_autoobs//k5ts3/ autoobs is running! 2006.285.19:10:56.29/chk_autoobs//k5ts4/ autoobs is running! 2006.285.19:10:56.61/chk_obsdata//k5ts1/T2851909??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.19:10:57.05/chk_obsdata//k5ts2/T2851909??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.19:10:57.43/chk_obsdata//k5ts3/T2851909??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.19:10:57.79/chk_obsdata//k5ts4/T2851909??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.19:10:58.91/k5log//k5ts1_log_newline 2006.285.19:11:00.16/k5log//k5ts2_log_newline 2006.285.19:11:00.93/k5log//k5ts3_log_newline 2006.285.19:11:01.65/k5log//k5ts4_log_newline 2006.285.19:11:01.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.19:11:01.67:setupk4=1 2006.285.19:11:01.67$setupk4/echo=on 2006.285.19:11:01.67$setupk4/pcalon 2006.285.19:11:01.67$pcalon/"no phase cal control is implemented here 2006.285.19:11:01.67$setupk4/"tpicd=stop 2006.285.19:11:01.67$setupk4/"rec=synch_on 2006.285.19:11:01.67$setupk4/"rec_mode=128 2006.285.19:11:01.67$setupk4/!* 2006.285.19:11:01.67$setupk4/recpk4 2006.285.19:11:01.67$recpk4/recpatch= 2006.285.19:11:01.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.19:11:01.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.19:11:01.68$setupk4/vck44 2006.285.19:11:01.68$vck44/valo=1,524.99 2006.285.19:11:01.68#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.19:11:01.68#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.19:11:01.68#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:01.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:11:01.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:11:01.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:11:01.68#ibcon#enter wrdev, iclass 6, count 0 2006.285.19:11:01.68#ibcon#first serial, iclass 6, count 0 2006.285.19:11:01.68#ibcon#enter sib2, iclass 6, count 0 2006.285.19:11:01.68#ibcon#flushed, iclass 6, count 0 2006.285.19:11:01.68#ibcon#about to write, iclass 6, count 0 2006.285.19:11:01.68#ibcon#wrote, iclass 6, count 0 2006.285.19:11:01.68#ibcon#about to read 3, iclass 6, count 0 2006.285.19:11:01.69#ibcon#read 3, iclass 6, count 0 2006.285.19:11:01.69#ibcon#about to read 4, iclass 6, count 0 2006.285.19:11:01.69#ibcon#read 4, iclass 6, count 0 2006.285.19:11:01.69#ibcon#about to read 5, iclass 6, count 0 2006.285.19:11:01.69#ibcon#read 5, iclass 6, count 0 2006.285.19:11:01.69#ibcon#about to read 6, iclass 6, count 0 2006.285.19:11:01.69#ibcon#read 6, iclass 6, count 0 2006.285.19:11:01.69#ibcon#end of sib2, iclass 6, count 0 2006.285.19:11:01.69#ibcon#*mode == 0, iclass 6, count 0 2006.285.19:11:01.69#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.19:11:01.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.19:11:01.69#ibcon#*before write, iclass 6, count 0 2006.285.19:11:01.69#ibcon#enter sib2, iclass 6, count 0 2006.285.19:11:01.69#ibcon#flushed, iclass 6, count 0 2006.285.19:11:01.69#ibcon#about to write, iclass 6, count 0 2006.285.19:11:01.69#ibcon#wrote, iclass 6, count 0 2006.285.19:11:01.69#ibcon#about to read 3, iclass 6, count 0 2006.285.19:11:01.74#ibcon#read 3, iclass 6, count 0 2006.285.19:11:01.74#ibcon#about to read 4, iclass 6, count 0 2006.285.19:11:01.74#ibcon#read 4, iclass 6, count 0 2006.285.19:11:01.74#ibcon#about to read 5, iclass 6, count 0 2006.285.19:11:01.74#ibcon#read 5, iclass 6, count 0 2006.285.19:11:01.74#ibcon#about to read 6, iclass 6, count 0 2006.285.19:11:01.74#ibcon#read 6, iclass 6, count 0 2006.285.19:11:01.74#ibcon#end of sib2, iclass 6, count 0 2006.285.19:11:01.74#ibcon#*after write, iclass 6, count 0 2006.285.19:11:01.74#ibcon#*before return 0, iclass 6, count 0 2006.285.19:11:01.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:11:01.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:11:01.74#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.19:11:01.74#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.19:11:01.74$vck44/va=1,7 2006.285.19:11:01.74#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.19:11:01.74#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.19:11:01.74#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:01.74#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:11:01.74#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:11:01.74#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:11:01.74#ibcon#enter wrdev, iclass 10, count 2 2006.285.19:11:01.74#ibcon#first serial, iclass 10, count 2 2006.285.19:11:01.74#ibcon#enter sib2, iclass 10, count 2 2006.285.19:11:01.74#ibcon#flushed, iclass 10, count 2 2006.285.19:11:01.74#ibcon#about to write, iclass 10, count 2 2006.285.19:11:01.74#ibcon#wrote, iclass 10, count 2 2006.285.19:11:01.74#ibcon#about to read 3, iclass 10, count 2 2006.285.19:11:01.76#ibcon#read 3, iclass 10, count 2 2006.285.19:11:01.76#ibcon#about to read 4, iclass 10, count 2 2006.285.19:11:01.76#ibcon#read 4, iclass 10, count 2 2006.285.19:11:01.76#ibcon#about to read 5, iclass 10, count 2 2006.285.19:11:01.76#ibcon#read 5, iclass 10, count 2 2006.285.19:11:01.76#ibcon#about to read 6, iclass 10, count 2 2006.285.19:11:01.76#ibcon#read 6, iclass 10, count 2 2006.285.19:11:01.76#ibcon#end of sib2, iclass 10, count 2 2006.285.19:11:01.76#ibcon#*mode == 0, iclass 10, count 2 2006.285.19:11:01.76#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.19:11:01.76#ibcon#[25=AT01-07\r\n] 2006.285.19:11:01.76#ibcon#*before write, iclass 10, count 2 2006.285.19:11:01.76#ibcon#enter sib2, iclass 10, count 2 2006.285.19:11:01.76#ibcon#flushed, iclass 10, count 2 2006.285.19:11:01.76#ibcon#about to write, iclass 10, count 2 2006.285.19:11:01.76#ibcon#wrote, iclass 10, count 2 2006.285.19:11:01.76#ibcon#about to read 3, iclass 10, count 2 2006.285.19:11:01.79#ibcon#read 3, iclass 10, count 2 2006.285.19:11:01.79#ibcon#about to read 4, iclass 10, count 2 2006.285.19:11:01.79#ibcon#read 4, iclass 10, count 2 2006.285.19:11:01.79#ibcon#about to read 5, iclass 10, count 2 2006.285.19:11:01.79#ibcon#read 5, iclass 10, count 2 2006.285.19:11:01.79#ibcon#about to read 6, iclass 10, count 2 2006.285.19:11:01.79#ibcon#read 6, iclass 10, count 2 2006.285.19:11:01.79#ibcon#end of sib2, iclass 10, count 2 2006.285.19:11:01.79#ibcon#*after write, iclass 10, count 2 2006.285.19:11:01.79#ibcon#*before return 0, iclass 10, count 2 2006.285.19:11:01.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:11:01.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:11:01.79#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.19:11:01.79#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:01.79#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:11:01.91#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:11:01.91#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:11:01.91#ibcon#enter wrdev, iclass 10, count 0 2006.285.19:11:01.91#ibcon#first serial, iclass 10, count 0 2006.285.19:11:01.91#ibcon#enter sib2, iclass 10, count 0 2006.285.19:11:01.91#ibcon#flushed, iclass 10, count 0 2006.285.19:11:01.91#ibcon#about to write, iclass 10, count 0 2006.285.19:11:01.91#ibcon#wrote, iclass 10, count 0 2006.285.19:11:01.91#ibcon#about to read 3, iclass 10, count 0 2006.285.19:11:01.93#ibcon#read 3, iclass 10, count 0 2006.285.19:11:01.93#ibcon#about to read 4, iclass 10, count 0 2006.285.19:11:01.93#ibcon#read 4, iclass 10, count 0 2006.285.19:11:01.93#ibcon#about to read 5, iclass 10, count 0 2006.285.19:11:01.93#ibcon#read 5, iclass 10, count 0 2006.285.19:11:01.93#ibcon#about to read 6, iclass 10, count 0 2006.285.19:11:01.93#ibcon#read 6, iclass 10, count 0 2006.285.19:11:01.93#ibcon#end of sib2, iclass 10, count 0 2006.285.19:11:01.93#ibcon#*mode == 0, iclass 10, count 0 2006.285.19:11:01.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.19:11:01.93#ibcon#[25=USB\r\n] 2006.285.19:11:01.93#ibcon#*before write, iclass 10, count 0 2006.285.19:11:01.93#ibcon#enter sib2, iclass 10, count 0 2006.285.19:11:01.93#ibcon#flushed, iclass 10, count 0 2006.285.19:11:01.93#ibcon#about to write, iclass 10, count 0 2006.285.19:11:01.93#ibcon#wrote, iclass 10, count 0 2006.285.19:11:01.93#ibcon#about to read 3, iclass 10, count 0 2006.285.19:11:01.96#ibcon#read 3, iclass 10, count 0 2006.285.19:11:01.96#ibcon#about to read 4, iclass 10, count 0 2006.285.19:11:01.96#ibcon#read 4, iclass 10, count 0 2006.285.19:11:01.96#ibcon#about to read 5, iclass 10, count 0 2006.285.19:11:01.96#ibcon#read 5, iclass 10, count 0 2006.285.19:11:01.96#ibcon#about to read 6, iclass 10, count 0 2006.285.19:11:01.96#ibcon#read 6, iclass 10, count 0 2006.285.19:11:01.96#ibcon#end of sib2, iclass 10, count 0 2006.285.19:11:01.96#ibcon#*after write, iclass 10, count 0 2006.285.19:11:01.96#ibcon#*before return 0, iclass 10, count 0 2006.285.19:11:01.96#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:11:01.96#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:11:01.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.19:11:01.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.19:11:01.96$vck44/valo=2,534.99 2006.285.19:11:01.96#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.19:11:01.96#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.19:11:01.96#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:01.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:11:01.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:11:01.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:11:01.96#ibcon#enter wrdev, iclass 12, count 0 2006.285.19:11:01.96#ibcon#first serial, iclass 12, count 0 2006.285.19:11:01.96#ibcon#enter sib2, iclass 12, count 0 2006.285.19:11:01.96#ibcon#flushed, iclass 12, count 0 2006.285.19:11:01.96#ibcon#about to write, iclass 12, count 0 2006.285.19:11:01.96#ibcon#wrote, iclass 12, count 0 2006.285.19:11:01.96#ibcon#about to read 3, iclass 12, count 0 2006.285.19:11:02.44#ibcon#read 3, iclass 12, count 0 2006.285.19:11:02.44#ibcon#about to read 4, iclass 12, count 0 2006.285.19:11:02.44#ibcon#read 4, iclass 12, count 0 2006.285.19:11:02.44#ibcon#about to read 5, iclass 12, count 0 2006.285.19:11:02.44#ibcon#read 5, iclass 12, count 0 2006.285.19:11:02.44#ibcon#about to read 6, iclass 12, count 0 2006.285.19:11:02.44#ibcon#read 6, iclass 12, count 0 2006.285.19:11:02.44#ibcon#end of sib2, iclass 12, count 0 2006.285.19:11:02.44#ibcon#*mode == 0, iclass 12, count 0 2006.285.19:11:02.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.19:11:02.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.19:11:02.44#ibcon#*before write, iclass 12, count 0 2006.285.19:11:02.44#ibcon#enter sib2, iclass 12, count 0 2006.285.19:11:02.44#ibcon#flushed, iclass 12, count 0 2006.285.19:11:02.44#ibcon#about to write, iclass 12, count 0 2006.285.19:11:02.44#ibcon#wrote, iclass 12, count 0 2006.285.19:11:02.44#ibcon#about to read 3, iclass 12, count 0 2006.285.19:11:02.48#ibcon#read 3, iclass 12, count 0 2006.285.19:11:02.48#ibcon#about to read 4, iclass 12, count 0 2006.285.19:11:02.48#ibcon#read 4, iclass 12, count 0 2006.285.19:11:02.48#ibcon#about to read 5, iclass 12, count 0 2006.285.19:11:02.48#ibcon#read 5, iclass 12, count 0 2006.285.19:11:02.48#ibcon#about to read 6, iclass 12, count 0 2006.285.19:11:02.48#ibcon#read 6, iclass 12, count 0 2006.285.19:11:02.48#ibcon#end of sib2, iclass 12, count 0 2006.285.19:11:02.48#ibcon#*after write, iclass 12, count 0 2006.285.19:11:02.48#ibcon#*before return 0, iclass 12, count 0 2006.285.19:11:02.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:11:02.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:11:02.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.19:11:02.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.19:11:02.48$vck44/va=2,6 2006.285.19:11:02.48#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.19:11:02.48#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.19:11:02.48#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:02.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:11:02.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:11:02.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:11:02.48#ibcon#enter wrdev, iclass 14, count 2 2006.285.19:11:02.48#ibcon#first serial, iclass 14, count 2 2006.285.19:11:02.48#ibcon#enter sib2, iclass 14, count 2 2006.285.19:11:02.48#ibcon#flushed, iclass 14, count 2 2006.285.19:11:02.48#ibcon#about to write, iclass 14, count 2 2006.285.19:11:02.48#ibcon#wrote, iclass 14, count 2 2006.285.19:11:02.48#ibcon#about to read 3, iclass 14, count 2 2006.285.19:11:02.50#ibcon#read 3, iclass 14, count 2 2006.285.19:11:02.50#ibcon#about to read 4, iclass 14, count 2 2006.285.19:11:02.50#ibcon#read 4, iclass 14, count 2 2006.285.19:11:02.50#ibcon#about to read 5, iclass 14, count 2 2006.285.19:11:02.50#ibcon#read 5, iclass 14, count 2 2006.285.19:11:02.50#ibcon#about to read 6, iclass 14, count 2 2006.285.19:11:02.50#ibcon#read 6, iclass 14, count 2 2006.285.19:11:02.50#ibcon#end of sib2, iclass 14, count 2 2006.285.19:11:02.50#ibcon#*mode == 0, iclass 14, count 2 2006.285.19:11:02.50#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.19:11:02.50#ibcon#[25=AT02-06\r\n] 2006.285.19:11:02.50#ibcon#*before write, iclass 14, count 2 2006.285.19:11:02.50#ibcon#enter sib2, iclass 14, count 2 2006.285.19:11:02.50#ibcon#flushed, iclass 14, count 2 2006.285.19:11:02.50#ibcon#about to write, iclass 14, count 2 2006.285.19:11:02.50#ibcon#wrote, iclass 14, count 2 2006.285.19:11:02.50#ibcon#about to read 3, iclass 14, count 2 2006.285.19:11:02.53#ibcon#read 3, iclass 14, count 2 2006.285.19:11:02.53#ibcon#about to read 4, iclass 14, count 2 2006.285.19:11:02.53#ibcon#read 4, iclass 14, count 2 2006.285.19:11:02.53#ibcon#about to read 5, iclass 14, count 2 2006.285.19:11:02.53#ibcon#read 5, iclass 14, count 2 2006.285.19:11:02.53#ibcon#about to read 6, iclass 14, count 2 2006.285.19:11:02.53#ibcon#read 6, iclass 14, count 2 2006.285.19:11:02.53#ibcon#end of sib2, iclass 14, count 2 2006.285.19:11:02.53#ibcon#*after write, iclass 14, count 2 2006.285.19:11:02.53#ibcon#*before return 0, iclass 14, count 2 2006.285.19:11:02.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:11:02.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:11:02.53#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.19:11:02.53#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:02.53#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:11:02.65#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:11:02.65#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:11:02.65#ibcon#enter wrdev, iclass 14, count 0 2006.285.19:11:02.65#ibcon#first serial, iclass 14, count 0 2006.285.19:11:02.65#ibcon#enter sib2, iclass 14, count 0 2006.285.19:11:02.65#ibcon#flushed, iclass 14, count 0 2006.285.19:11:02.65#ibcon#about to write, iclass 14, count 0 2006.285.19:11:02.65#ibcon#wrote, iclass 14, count 0 2006.285.19:11:02.65#ibcon#about to read 3, iclass 14, count 0 2006.285.19:11:02.67#ibcon#read 3, iclass 14, count 0 2006.285.19:11:02.67#ibcon#about to read 4, iclass 14, count 0 2006.285.19:11:02.67#ibcon#read 4, iclass 14, count 0 2006.285.19:11:02.67#ibcon#about to read 5, iclass 14, count 0 2006.285.19:11:02.67#ibcon#read 5, iclass 14, count 0 2006.285.19:11:02.67#ibcon#about to read 6, iclass 14, count 0 2006.285.19:11:02.67#ibcon#read 6, iclass 14, count 0 2006.285.19:11:02.67#ibcon#end of sib2, iclass 14, count 0 2006.285.19:11:02.67#ibcon#*mode == 0, iclass 14, count 0 2006.285.19:11:02.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.19:11:02.67#ibcon#[25=USB\r\n] 2006.285.19:11:02.67#ibcon#*before write, iclass 14, count 0 2006.285.19:11:02.67#ibcon#enter sib2, iclass 14, count 0 2006.285.19:11:02.67#ibcon#flushed, iclass 14, count 0 2006.285.19:11:02.67#ibcon#about to write, iclass 14, count 0 2006.285.19:11:02.67#ibcon#wrote, iclass 14, count 0 2006.285.19:11:02.67#ibcon#about to read 3, iclass 14, count 0 2006.285.19:11:02.70#ibcon#read 3, iclass 14, count 0 2006.285.19:11:02.70#ibcon#about to read 4, iclass 14, count 0 2006.285.19:11:02.70#ibcon#read 4, iclass 14, count 0 2006.285.19:11:02.70#ibcon#about to read 5, iclass 14, count 0 2006.285.19:11:02.70#ibcon#read 5, iclass 14, count 0 2006.285.19:11:02.70#ibcon#about to read 6, iclass 14, count 0 2006.285.19:11:02.70#ibcon#read 6, iclass 14, count 0 2006.285.19:11:02.70#ibcon#end of sib2, iclass 14, count 0 2006.285.19:11:02.70#ibcon#*after write, iclass 14, count 0 2006.285.19:11:02.70#ibcon#*before return 0, iclass 14, count 0 2006.285.19:11:02.70#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:11:02.70#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:11:02.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.19:11:02.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.19:11:02.70$vck44/valo=3,564.99 2006.285.19:11:02.70#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.19:11:02.70#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.19:11:02.70#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:02.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:11:02.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:11:02.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:11:02.70#ibcon#enter wrdev, iclass 16, count 0 2006.285.19:11:02.70#ibcon#first serial, iclass 16, count 0 2006.285.19:11:02.70#ibcon#enter sib2, iclass 16, count 0 2006.285.19:11:02.70#ibcon#flushed, iclass 16, count 0 2006.285.19:11:02.70#ibcon#about to write, iclass 16, count 0 2006.285.19:11:02.70#ibcon#wrote, iclass 16, count 0 2006.285.19:11:02.70#ibcon#about to read 3, iclass 16, count 0 2006.285.19:11:02.80#ibcon#read 3, iclass 16, count 0 2006.285.19:11:02.80#ibcon#about to read 4, iclass 16, count 0 2006.285.19:11:02.80#ibcon#read 4, iclass 16, count 0 2006.285.19:11:02.80#ibcon#about to read 5, iclass 16, count 0 2006.285.19:11:02.80#ibcon#read 5, iclass 16, count 0 2006.285.19:11:02.80#ibcon#about to read 6, iclass 16, count 0 2006.285.19:11:02.80#ibcon#read 6, iclass 16, count 0 2006.285.19:11:02.80#ibcon#end of sib2, iclass 16, count 0 2006.285.19:11:02.80#ibcon#*mode == 0, iclass 16, count 0 2006.285.19:11:02.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.19:11:02.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.19:11:02.80#ibcon#*before write, iclass 16, count 0 2006.285.19:11:02.80#ibcon#enter sib2, iclass 16, count 0 2006.285.19:11:02.80#ibcon#flushed, iclass 16, count 0 2006.285.19:11:02.80#ibcon#about to write, iclass 16, count 0 2006.285.19:11:02.80#ibcon#wrote, iclass 16, count 0 2006.285.19:11:02.80#ibcon#about to read 3, iclass 16, count 0 2006.285.19:11:02.84#ibcon#read 3, iclass 16, count 0 2006.285.19:11:02.84#ibcon#about to read 4, iclass 16, count 0 2006.285.19:11:02.84#ibcon#read 4, iclass 16, count 0 2006.285.19:11:02.84#ibcon#about to read 5, iclass 16, count 0 2006.285.19:11:02.84#ibcon#read 5, iclass 16, count 0 2006.285.19:11:02.84#ibcon#about to read 6, iclass 16, count 0 2006.285.19:11:02.84#ibcon#read 6, iclass 16, count 0 2006.285.19:11:02.84#ibcon#end of sib2, iclass 16, count 0 2006.285.19:11:02.84#ibcon#*after write, iclass 16, count 0 2006.285.19:11:02.84#ibcon#*before return 0, iclass 16, count 0 2006.285.19:11:02.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:11:02.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:11:02.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.19:11:02.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.19:11:02.84$vck44/va=3,7 2006.285.19:11:02.84#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.19:11:02.84#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.19:11:02.84#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:02.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:11:02.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:11:02.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:11:02.84#ibcon#enter wrdev, iclass 18, count 2 2006.285.19:11:02.84#ibcon#first serial, iclass 18, count 2 2006.285.19:11:02.84#ibcon#enter sib2, iclass 18, count 2 2006.285.19:11:02.84#ibcon#flushed, iclass 18, count 2 2006.285.19:11:02.84#ibcon#about to write, iclass 18, count 2 2006.285.19:11:02.84#ibcon#wrote, iclass 18, count 2 2006.285.19:11:02.84#ibcon#about to read 3, iclass 18, count 2 2006.285.19:11:02.86#ibcon#read 3, iclass 18, count 2 2006.285.19:11:02.86#ibcon#about to read 4, iclass 18, count 2 2006.285.19:11:02.86#ibcon#read 4, iclass 18, count 2 2006.285.19:11:02.86#ibcon#about to read 5, iclass 18, count 2 2006.285.19:11:02.86#ibcon#read 5, iclass 18, count 2 2006.285.19:11:02.86#ibcon#about to read 6, iclass 18, count 2 2006.285.19:11:02.86#ibcon#read 6, iclass 18, count 2 2006.285.19:11:02.86#ibcon#end of sib2, iclass 18, count 2 2006.285.19:11:02.86#ibcon#*mode == 0, iclass 18, count 2 2006.285.19:11:02.86#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.19:11:02.86#ibcon#[25=AT03-07\r\n] 2006.285.19:11:02.86#ibcon#*before write, iclass 18, count 2 2006.285.19:11:02.86#ibcon#enter sib2, iclass 18, count 2 2006.285.19:11:02.86#ibcon#flushed, iclass 18, count 2 2006.285.19:11:02.86#ibcon#about to write, iclass 18, count 2 2006.285.19:11:02.86#ibcon#wrote, iclass 18, count 2 2006.285.19:11:02.86#ibcon#about to read 3, iclass 18, count 2 2006.285.19:11:02.89#ibcon#read 3, iclass 18, count 2 2006.285.19:11:02.89#ibcon#about to read 4, iclass 18, count 2 2006.285.19:11:02.89#ibcon#read 4, iclass 18, count 2 2006.285.19:11:02.89#ibcon#about to read 5, iclass 18, count 2 2006.285.19:11:02.89#ibcon#read 5, iclass 18, count 2 2006.285.19:11:02.89#ibcon#about to read 6, iclass 18, count 2 2006.285.19:11:02.89#ibcon#read 6, iclass 18, count 2 2006.285.19:11:02.89#ibcon#end of sib2, iclass 18, count 2 2006.285.19:11:02.89#ibcon#*after write, iclass 18, count 2 2006.285.19:11:02.89#ibcon#*before return 0, iclass 18, count 2 2006.285.19:11:02.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:11:02.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:11:02.89#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.19:11:02.89#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:02.89#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:11:03.01#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:11:03.01#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:11:03.01#ibcon#enter wrdev, iclass 18, count 0 2006.285.19:11:03.01#ibcon#first serial, iclass 18, count 0 2006.285.19:11:03.01#ibcon#enter sib2, iclass 18, count 0 2006.285.19:11:03.01#ibcon#flushed, iclass 18, count 0 2006.285.19:11:03.01#ibcon#about to write, iclass 18, count 0 2006.285.19:11:03.01#ibcon#wrote, iclass 18, count 0 2006.285.19:11:03.01#ibcon#about to read 3, iclass 18, count 0 2006.285.19:11:03.03#ibcon#read 3, iclass 18, count 0 2006.285.19:11:03.03#ibcon#about to read 4, iclass 18, count 0 2006.285.19:11:03.03#ibcon#read 4, iclass 18, count 0 2006.285.19:11:03.03#ibcon#about to read 5, iclass 18, count 0 2006.285.19:11:03.03#ibcon#read 5, iclass 18, count 0 2006.285.19:11:03.03#ibcon#about to read 6, iclass 18, count 0 2006.285.19:11:03.03#ibcon#read 6, iclass 18, count 0 2006.285.19:11:03.03#ibcon#end of sib2, iclass 18, count 0 2006.285.19:11:03.03#ibcon#*mode == 0, iclass 18, count 0 2006.285.19:11:03.03#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.19:11:03.03#ibcon#[25=USB\r\n] 2006.285.19:11:03.03#ibcon#*before write, iclass 18, count 0 2006.285.19:11:03.03#ibcon#enter sib2, iclass 18, count 0 2006.285.19:11:03.03#ibcon#flushed, iclass 18, count 0 2006.285.19:11:03.03#ibcon#about to write, iclass 18, count 0 2006.285.19:11:03.03#ibcon#wrote, iclass 18, count 0 2006.285.19:11:03.03#ibcon#about to read 3, iclass 18, count 0 2006.285.19:11:03.06#ibcon#read 3, iclass 18, count 0 2006.285.19:11:03.06#ibcon#about to read 4, iclass 18, count 0 2006.285.19:11:03.06#ibcon#read 4, iclass 18, count 0 2006.285.19:11:03.06#ibcon#about to read 5, iclass 18, count 0 2006.285.19:11:03.06#ibcon#read 5, iclass 18, count 0 2006.285.19:11:03.06#ibcon#about to read 6, iclass 18, count 0 2006.285.19:11:03.06#ibcon#read 6, iclass 18, count 0 2006.285.19:11:03.06#ibcon#end of sib2, iclass 18, count 0 2006.285.19:11:03.06#ibcon#*after write, iclass 18, count 0 2006.285.19:11:03.06#ibcon#*before return 0, iclass 18, count 0 2006.285.19:11:03.06#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:11:03.06#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:11:03.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.19:11:03.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.19:11:03.06$vck44/valo=4,624.99 2006.285.19:11:03.06#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.19:11:03.06#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.19:11:03.06#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:03.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:11:03.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:11:03.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:11:03.06#ibcon#enter wrdev, iclass 20, count 0 2006.285.19:11:03.06#ibcon#first serial, iclass 20, count 0 2006.285.19:11:03.06#ibcon#enter sib2, iclass 20, count 0 2006.285.19:11:03.06#ibcon#flushed, iclass 20, count 0 2006.285.19:11:03.06#ibcon#about to write, iclass 20, count 0 2006.285.19:11:03.06#ibcon#wrote, iclass 20, count 0 2006.285.19:11:03.06#ibcon#about to read 3, iclass 20, count 0 2006.285.19:11:03.08#ibcon#read 3, iclass 20, count 0 2006.285.19:11:03.08#ibcon#about to read 4, iclass 20, count 0 2006.285.19:11:03.08#ibcon#read 4, iclass 20, count 0 2006.285.19:11:03.08#ibcon#about to read 5, iclass 20, count 0 2006.285.19:11:03.08#ibcon#read 5, iclass 20, count 0 2006.285.19:11:03.08#ibcon#about to read 6, iclass 20, count 0 2006.285.19:11:03.08#ibcon#read 6, iclass 20, count 0 2006.285.19:11:03.08#ibcon#end of sib2, iclass 20, count 0 2006.285.19:11:03.08#ibcon#*mode == 0, iclass 20, count 0 2006.285.19:11:03.08#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.19:11:03.08#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.19:11:03.08#ibcon#*before write, iclass 20, count 0 2006.285.19:11:03.08#ibcon#enter sib2, iclass 20, count 0 2006.285.19:11:03.08#ibcon#flushed, iclass 20, count 0 2006.285.19:11:03.08#ibcon#about to write, iclass 20, count 0 2006.285.19:11:03.08#ibcon#wrote, iclass 20, count 0 2006.285.19:11:03.08#ibcon#about to read 3, iclass 20, count 0 2006.285.19:11:03.12#ibcon#read 3, iclass 20, count 0 2006.285.19:11:03.12#ibcon#about to read 4, iclass 20, count 0 2006.285.19:11:03.12#ibcon#read 4, iclass 20, count 0 2006.285.19:11:03.12#ibcon#about to read 5, iclass 20, count 0 2006.285.19:11:03.12#ibcon#read 5, iclass 20, count 0 2006.285.19:11:03.12#ibcon#about to read 6, iclass 20, count 0 2006.285.19:11:03.12#ibcon#read 6, iclass 20, count 0 2006.285.19:11:03.12#ibcon#end of sib2, iclass 20, count 0 2006.285.19:11:03.12#ibcon#*after write, iclass 20, count 0 2006.285.19:11:03.12#ibcon#*before return 0, iclass 20, count 0 2006.285.19:11:03.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:11:03.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:11:03.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.19:11:03.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.19:11:03.12$vck44/va=4,6 2006.285.19:11:03.12#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.19:11:03.12#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.19:11:03.12#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:03.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:11:03.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:11:03.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:11:03.18#ibcon#enter wrdev, iclass 22, count 2 2006.285.19:11:03.18#ibcon#first serial, iclass 22, count 2 2006.285.19:11:03.18#ibcon#enter sib2, iclass 22, count 2 2006.285.19:11:03.18#ibcon#flushed, iclass 22, count 2 2006.285.19:11:03.18#ibcon#about to write, iclass 22, count 2 2006.285.19:11:03.18#ibcon#wrote, iclass 22, count 2 2006.285.19:11:03.18#ibcon#about to read 3, iclass 22, count 2 2006.285.19:11:03.20#ibcon#read 3, iclass 22, count 2 2006.285.19:11:03.20#ibcon#about to read 4, iclass 22, count 2 2006.285.19:11:03.20#ibcon#read 4, iclass 22, count 2 2006.285.19:11:03.20#ibcon#about to read 5, iclass 22, count 2 2006.285.19:11:03.20#ibcon#read 5, iclass 22, count 2 2006.285.19:11:03.20#ibcon#about to read 6, iclass 22, count 2 2006.285.19:11:03.20#ibcon#read 6, iclass 22, count 2 2006.285.19:11:03.20#ibcon#end of sib2, iclass 22, count 2 2006.285.19:11:03.20#ibcon#*mode == 0, iclass 22, count 2 2006.285.19:11:03.20#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.19:11:03.20#ibcon#[25=AT04-06\r\n] 2006.285.19:11:03.20#ibcon#*before write, iclass 22, count 2 2006.285.19:11:03.20#ibcon#enter sib2, iclass 22, count 2 2006.285.19:11:03.20#ibcon#flushed, iclass 22, count 2 2006.285.19:11:03.20#ibcon#about to write, iclass 22, count 2 2006.285.19:11:03.20#ibcon#wrote, iclass 22, count 2 2006.285.19:11:03.20#ibcon#about to read 3, iclass 22, count 2 2006.285.19:11:03.23#ibcon#read 3, iclass 22, count 2 2006.285.19:11:03.23#ibcon#about to read 4, iclass 22, count 2 2006.285.19:11:03.23#ibcon#read 4, iclass 22, count 2 2006.285.19:11:03.23#ibcon#about to read 5, iclass 22, count 2 2006.285.19:11:03.23#ibcon#read 5, iclass 22, count 2 2006.285.19:11:03.23#ibcon#about to read 6, iclass 22, count 2 2006.285.19:11:03.23#ibcon#read 6, iclass 22, count 2 2006.285.19:11:03.23#ibcon#end of sib2, iclass 22, count 2 2006.285.19:11:03.23#ibcon#*after write, iclass 22, count 2 2006.285.19:11:03.23#ibcon#*before return 0, iclass 22, count 2 2006.285.19:11:03.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:11:03.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:11:03.23#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.19:11:03.23#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:03.23#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:11:03.35#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:11:03.35#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:11:03.35#ibcon#enter wrdev, iclass 22, count 0 2006.285.19:11:03.35#ibcon#first serial, iclass 22, count 0 2006.285.19:11:03.35#ibcon#enter sib2, iclass 22, count 0 2006.285.19:11:03.35#ibcon#flushed, iclass 22, count 0 2006.285.19:11:03.35#ibcon#about to write, iclass 22, count 0 2006.285.19:11:03.35#ibcon#wrote, iclass 22, count 0 2006.285.19:11:03.35#ibcon#about to read 3, iclass 22, count 0 2006.285.19:11:03.37#ibcon#read 3, iclass 22, count 0 2006.285.19:11:03.37#ibcon#about to read 4, iclass 22, count 0 2006.285.19:11:03.37#ibcon#read 4, iclass 22, count 0 2006.285.19:11:03.37#ibcon#about to read 5, iclass 22, count 0 2006.285.19:11:03.37#ibcon#read 5, iclass 22, count 0 2006.285.19:11:03.37#ibcon#about to read 6, iclass 22, count 0 2006.285.19:11:03.37#ibcon#read 6, iclass 22, count 0 2006.285.19:11:03.37#ibcon#end of sib2, iclass 22, count 0 2006.285.19:11:03.37#ibcon#*mode == 0, iclass 22, count 0 2006.285.19:11:03.37#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.19:11:03.37#ibcon#[25=USB\r\n] 2006.285.19:11:03.37#ibcon#*before write, iclass 22, count 0 2006.285.19:11:03.37#ibcon#enter sib2, iclass 22, count 0 2006.285.19:11:03.37#ibcon#flushed, iclass 22, count 0 2006.285.19:11:03.37#ibcon#about to write, iclass 22, count 0 2006.285.19:11:03.37#ibcon#wrote, iclass 22, count 0 2006.285.19:11:03.37#ibcon#about to read 3, iclass 22, count 0 2006.285.19:11:03.40#ibcon#read 3, iclass 22, count 0 2006.285.19:11:03.40#ibcon#about to read 4, iclass 22, count 0 2006.285.19:11:03.40#ibcon#read 4, iclass 22, count 0 2006.285.19:11:03.40#ibcon#about to read 5, iclass 22, count 0 2006.285.19:11:03.40#ibcon#read 5, iclass 22, count 0 2006.285.19:11:03.40#ibcon#about to read 6, iclass 22, count 0 2006.285.19:11:03.40#ibcon#read 6, iclass 22, count 0 2006.285.19:11:03.40#ibcon#end of sib2, iclass 22, count 0 2006.285.19:11:03.40#ibcon#*after write, iclass 22, count 0 2006.285.19:11:03.40#ibcon#*before return 0, iclass 22, count 0 2006.285.19:11:03.40#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:11:03.40#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:11:03.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.19:11:03.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.19:11:03.40$vck44/valo=5,734.99 2006.285.19:11:03.40#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.19:11:03.40#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.19:11:03.40#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:03.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:11:03.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:11:03.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:11:03.40#ibcon#enter wrdev, iclass 24, count 0 2006.285.19:11:03.40#ibcon#first serial, iclass 24, count 0 2006.285.19:11:03.40#ibcon#enter sib2, iclass 24, count 0 2006.285.19:11:03.40#ibcon#flushed, iclass 24, count 0 2006.285.19:11:03.40#ibcon#about to write, iclass 24, count 0 2006.285.19:11:03.40#ibcon#wrote, iclass 24, count 0 2006.285.19:11:03.40#ibcon#about to read 3, iclass 24, count 0 2006.285.19:11:03.42#ibcon#read 3, iclass 24, count 0 2006.285.19:11:03.42#ibcon#about to read 4, iclass 24, count 0 2006.285.19:11:03.42#ibcon#read 4, iclass 24, count 0 2006.285.19:11:03.42#ibcon#about to read 5, iclass 24, count 0 2006.285.19:11:03.42#ibcon#read 5, iclass 24, count 0 2006.285.19:11:03.42#ibcon#about to read 6, iclass 24, count 0 2006.285.19:11:03.42#ibcon#read 6, iclass 24, count 0 2006.285.19:11:03.42#ibcon#end of sib2, iclass 24, count 0 2006.285.19:11:03.42#ibcon#*mode == 0, iclass 24, count 0 2006.285.19:11:03.42#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.19:11:03.42#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.19:11:03.42#ibcon#*before write, iclass 24, count 0 2006.285.19:11:03.42#ibcon#enter sib2, iclass 24, count 0 2006.285.19:11:03.42#ibcon#flushed, iclass 24, count 0 2006.285.19:11:03.42#ibcon#about to write, iclass 24, count 0 2006.285.19:11:03.42#ibcon#wrote, iclass 24, count 0 2006.285.19:11:03.42#ibcon#about to read 3, iclass 24, count 0 2006.285.19:11:03.46#ibcon#read 3, iclass 24, count 0 2006.285.19:11:03.46#ibcon#about to read 4, iclass 24, count 0 2006.285.19:11:03.46#ibcon#read 4, iclass 24, count 0 2006.285.19:11:03.46#ibcon#about to read 5, iclass 24, count 0 2006.285.19:11:03.46#ibcon#read 5, iclass 24, count 0 2006.285.19:11:03.46#ibcon#about to read 6, iclass 24, count 0 2006.285.19:11:03.46#ibcon#read 6, iclass 24, count 0 2006.285.19:11:03.46#ibcon#end of sib2, iclass 24, count 0 2006.285.19:11:03.46#ibcon#*after write, iclass 24, count 0 2006.285.19:11:03.46#ibcon#*before return 0, iclass 24, count 0 2006.285.19:11:03.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:11:03.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:11:03.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.19:11:03.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.19:11:03.46$vck44/va=5,3 2006.285.19:11:03.46#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.19:11:03.46#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.19:11:03.46#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:03.46#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:11:03.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:11:03.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:11:03.52#ibcon#enter wrdev, iclass 26, count 2 2006.285.19:11:03.52#ibcon#first serial, iclass 26, count 2 2006.285.19:11:03.52#ibcon#enter sib2, iclass 26, count 2 2006.285.19:11:03.52#ibcon#flushed, iclass 26, count 2 2006.285.19:11:03.52#ibcon#about to write, iclass 26, count 2 2006.285.19:11:03.52#ibcon#wrote, iclass 26, count 2 2006.285.19:11:03.52#ibcon#about to read 3, iclass 26, count 2 2006.285.19:11:03.54#ibcon#read 3, iclass 26, count 2 2006.285.19:11:03.54#ibcon#about to read 4, iclass 26, count 2 2006.285.19:11:03.54#ibcon#read 4, iclass 26, count 2 2006.285.19:11:03.54#ibcon#about to read 5, iclass 26, count 2 2006.285.19:11:03.54#ibcon#read 5, iclass 26, count 2 2006.285.19:11:03.54#ibcon#about to read 6, iclass 26, count 2 2006.285.19:11:03.54#ibcon#read 6, iclass 26, count 2 2006.285.19:11:03.54#ibcon#end of sib2, iclass 26, count 2 2006.285.19:11:03.54#ibcon#*mode == 0, iclass 26, count 2 2006.285.19:11:03.54#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.19:11:03.54#ibcon#[25=AT05-03\r\n] 2006.285.19:11:03.54#ibcon#*before write, iclass 26, count 2 2006.285.19:11:03.54#ibcon#enter sib2, iclass 26, count 2 2006.285.19:11:03.54#ibcon#flushed, iclass 26, count 2 2006.285.19:11:03.54#ibcon#about to write, iclass 26, count 2 2006.285.19:11:03.54#ibcon#wrote, iclass 26, count 2 2006.285.19:11:03.54#ibcon#about to read 3, iclass 26, count 2 2006.285.19:11:03.57#ibcon#read 3, iclass 26, count 2 2006.285.19:11:03.57#ibcon#about to read 4, iclass 26, count 2 2006.285.19:11:03.57#ibcon#read 4, iclass 26, count 2 2006.285.19:11:03.57#ibcon#about to read 5, iclass 26, count 2 2006.285.19:11:03.57#ibcon#read 5, iclass 26, count 2 2006.285.19:11:03.57#ibcon#about to read 6, iclass 26, count 2 2006.285.19:11:03.57#ibcon#read 6, iclass 26, count 2 2006.285.19:11:03.57#ibcon#end of sib2, iclass 26, count 2 2006.285.19:11:03.57#ibcon#*after write, iclass 26, count 2 2006.285.19:11:03.57#ibcon#*before return 0, iclass 26, count 2 2006.285.19:11:03.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:11:03.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:11:03.57#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.19:11:03.57#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:03.57#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:11:03.69#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:11:03.69#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:11:03.69#ibcon#enter wrdev, iclass 26, count 0 2006.285.19:11:03.69#ibcon#first serial, iclass 26, count 0 2006.285.19:11:03.69#ibcon#enter sib2, iclass 26, count 0 2006.285.19:11:03.69#ibcon#flushed, iclass 26, count 0 2006.285.19:11:03.69#ibcon#about to write, iclass 26, count 0 2006.285.19:11:03.69#ibcon#wrote, iclass 26, count 0 2006.285.19:11:03.69#ibcon#about to read 3, iclass 26, count 0 2006.285.19:11:03.71#ibcon#read 3, iclass 26, count 0 2006.285.19:11:03.71#ibcon#about to read 4, iclass 26, count 0 2006.285.19:11:03.71#ibcon#read 4, iclass 26, count 0 2006.285.19:11:03.71#ibcon#about to read 5, iclass 26, count 0 2006.285.19:11:03.71#ibcon#read 5, iclass 26, count 0 2006.285.19:11:03.71#ibcon#about to read 6, iclass 26, count 0 2006.285.19:11:03.71#ibcon#read 6, iclass 26, count 0 2006.285.19:11:03.71#ibcon#end of sib2, iclass 26, count 0 2006.285.19:11:03.71#ibcon#*mode == 0, iclass 26, count 0 2006.285.19:11:03.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.19:11:03.71#ibcon#[25=USB\r\n] 2006.285.19:11:03.71#ibcon#*before write, iclass 26, count 0 2006.285.19:11:03.71#ibcon#enter sib2, iclass 26, count 0 2006.285.19:11:03.71#ibcon#flushed, iclass 26, count 0 2006.285.19:11:03.71#ibcon#about to write, iclass 26, count 0 2006.285.19:11:03.71#ibcon#wrote, iclass 26, count 0 2006.285.19:11:03.71#ibcon#about to read 3, iclass 26, count 0 2006.285.19:11:03.74#ibcon#read 3, iclass 26, count 0 2006.285.19:11:03.74#ibcon#about to read 4, iclass 26, count 0 2006.285.19:11:03.74#ibcon#read 4, iclass 26, count 0 2006.285.19:11:03.74#ibcon#about to read 5, iclass 26, count 0 2006.285.19:11:03.74#ibcon#read 5, iclass 26, count 0 2006.285.19:11:03.74#ibcon#about to read 6, iclass 26, count 0 2006.285.19:11:03.74#ibcon#read 6, iclass 26, count 0 2006.285.19:11:03.74#ibcon#end of sib2, iclass 26, count 0 2006.285.19:11:03.74#ibcon#*after write, iclass 26, count 0 2006.285.19:11:03.74#ibcon#*before return 0, iclass 26, count 0 2006.285.19:11:03.74#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:11:03.74#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:11:03.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.19:11:03.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.19:11:03.74$vck44/valo=6,814.99 2006.285.19:11:03.74#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.19:11:03.74#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.19:11:03.74#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:03.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:11:03.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:11:03.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:11:03.74#ibcon#enter wrdev, iclass 28, count 0 2006.285.19:11:03.74#ibcon#first serial, iclass 28, count 0 2006.285.19:11:03.74#ibcon#enter sib2, iclass 28, count 0 2006.285.19:11:03.74#ibcon#flushed, iclass 28, count 0 2006.285.19:11:03.74#ibcon#about to write, iclass 28, count 0 2006.285.19:11:03.74#ibcon#wrote, iclass 28, count 0 2006.285.19:11:03.74#ibcon#about to read 3, iclass 28, count 0 2006.285.19:11:03.76#ibcon#read 3, iclass 28, count 0 2006.285.19:11:03.76#ibcon#about to read 4, iclass 28, count 0 2006.285.19:11:03.76#ibcon#read 4, iclass 28, count 0 2006.285.19:11:03.76#ibcon#about to read 5, iclass 28, count 0 2006.285.19:11:03.76#ibcon#read 5, iclass 28, count 0 2006.285.19:11:03.76#ibcon#about to read 6, iclass 28, count 0 2006.285.19:11:03.76#ibcon#read 6, iclass 28, count 0 2006.285.19:11:03.76#ibcon#end of sib2, iclass 28, count 0 2006.285.19:11:03.76#ibcon#*mode == 0, iclass 28, count 0 2006.285.19:11:03.76#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.19:11:03.76#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.19:11:03.76#ibcon#*before write, iclass 28, count 0 2006.285.19:11:03.76#ibcon#enter sib2, iclass 28, count 0 2006.285.19:11:03.76#ibcon#flushed, iclass 28, count 0 2006.285.19:11:03.76#ibcon#about to write, iclass 28, count 0 2006.285.19:11:03.76#ibcon#wrote, iclass 28, count 0 2006.285.19:11:03.76#ibcon#about to read 3, iclass 28, count 0 2006.285.19:11:03.80#ibcon#read 3, iclass 28, count 0 2006.285.19:11:03.80#ibcon#about to read 4, iclass 28, count 0 2006.285.19:11:03.80#ibcon#read 4, iclass 28, count 0 2006.285.19:11:03.80#ibcon#about to read 5, iclass 28, count 0 2006.285.19:11:03.80#ibcon#read 5, iclass 28, count 0 2006.285.19:11:03.80#ibcon#about to read 6, iclass 28, count 0 2006.285.19:11:03.80#ibcon#read 6, iclass 28, count 0 2006.285.19:11:03.80#ibcon#end of sib2, iclass 28, count 0 2006.285.19:11:03.80#ibcon#*after write, iclass 28, count 0 2006.285.19:11:03.80#ibcon#*before return 0, iclass 28, count 0 2006.285.19:11:03.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:11:03.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:11:03.80#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.19:11:03.80#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.19:11:03.80$vck44/va=6,4 2006.285.19:11:03.80#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.19:11:03.80#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.19:11:03.80#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:03.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:11:03.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:11:03.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:11:03.86#ibcon#enter wrdev, iclass 30, count 2 2006.285.19:11:03.86#ibcon#first serial, iclass 30, count 2 2006.285.19:11:03.86#ibcon#enter sib2, iclass 30, count 2 2006.285.19:11:03.86#ibcon#flushed, iclass 30, count 2 2006.285.19:11:03.86#ibcon#about to write, iclass 30, count 2 2006.285.19:11:03.86#ibcon#wrote, iclass 30, count 2 2006.285.19:11:03.86#ibcon#about to read 3, iclass 30, count 2 2006.285.19:11:03.88#ibcon#read 3, iclass 30, count 2 2006.285.19:11:03.88#ibcon#about to read 4, iclass 30, count 2 2006.285.19:11:03.88#ibcon#read 4, iclass 30, count 2 2006.285.19:11:03.88#ibcon#about to read 5, iclass 30, count 2 2006.285.19:11:03.88#ibcon#read 5, iclass 30, count 2 2006.285.19:11:03.88#ibcon#about to read 6, iclass 30, count 2 2006.285.19:11:03.88#ibcon#read 6, iclass 30, count 2 2006.285.19:11:03.88#ibcon#end of sib2, iclass 30, count 2 2006.285.19:11:03.88#ibcon#*mode == 0, iclass 30, count 2 2006.285.19:11:03.88#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.19:11:03.88#ibcon#[25=AT06-04\r\n] 2006.285.19:11:03.88#ibcon#*before write, iclass 30, count 2 2006.285.19:11:03.88#ibcon#enter sib2, iclass 30, count 2 2006.285.19:11:03.88#ibcon#flushed, iclass 30, count 2 2006.285.19:11:03.88#ibcon#about to write, iclass 30, count 2 2006.285.19:11:03.88#ibcon#wrote, iclass 30, count 2 2006.285.19:11:03.88#ibcon#about to read 3, iclass 30, count 2 2006.285.19:11:03.91#ibcon#read 3, iclass 30, count 2 2006.285.19:11:03.91#ibcon#about to read 4, iclass 30, count 2 2006.285.19:11:03.91#ibcon#read 4, iclass 30, count 2 2006.285.19:11:03.91#ibcon#about to read 5, iclass 30, count 2 2006.285.19:11:03.91#ibcon#read 5, iclass 30, count 2 2006.285.19:11:03.91#ibcon#about to read 6, iclass 30, count 2 2006.285.19:11:03.91#ibcon#read 6, iclass 30, count 2 2006.285.19:11:03.91#ibcon#end of sib2, iclass 30, count 2 2006.285.19:11:03.91#ibcon#*after write, iclass 30, count 2 2006.285.19:11:03.91#ibcon#*before return 0, iclass 30, count 2 2006.285.19:11:03.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:11:03.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:11:03.91#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.19:11:03.91#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:03.91#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:11:04.03#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:11:04.03#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:11:04.03#ibcon#enter wrdev, iclass 30, count 0 2006.285.19:11:04.03#ibcon#first serial, iclass 30, count 0 2006.285.19:11:04.03#ibcon#enter sib2, iclass 30, count 0 2006.285.19:11:04.03#ibcon#flushed, iclass 30, count 0 2006.285.19:11:04.03#ibcon#about to write, iclass 30, count 0 2006.285.19:11:04.03#ibcon#wrote, iclass 30, count 0 2006.285.19:11:04.03#ibcon#about to read 3, iclass 30, count 0 2006.285.19:11:04.05#ibcon#read 3, iclass 30, count 0 2006.285.19:11:04.05#ibcon#about to read 4, iclass 30, count 0 2006.285.19:11:04.05#ibcon#read 4, iclass 30, count 0 2006.285.19:11:04.05#ibcon#about to read 5, iclass 30, count 0 2006.285.19:11:04.05#ibcon#read 5, iclass 30, count 0 2006.285.19:11:04.05#ibcon#about to read 6, iclass 30, count 0 2006.285.19:11:04.05#ibcon#read 6, iclass 30, count 0 2006.285.19:11:04.05#ibcon#end of sib2, iclass 30, count 0 2006.285.19:11:04.05#ibcon#*mode == 0, iclass 30, count 0 2006.285.19:11:04.05#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.19:11:04.05#ibcon#[25=USB\r\n] 2006.285.19:11:04.05#ibcon#*before write, iclass 30, count 0 2006.285.19:11:04.05#ibcon#enter sib2, iclass 30, count 0 2006.285.19:11:04.05#ibcon#flushed, iclass 30, count 0 2006.285.19:11:04.05#ibcon#about to write, iclass 30, count 0 2006.285.19:11:04.05#ibcon#wrote, iclass 30, count 0 2006.285.19:11:04.05#ibcon#about to read 3, iclass 30, count 0 2006.285.19:11:04.08#ibcon#read 3, iclass 30, count 0 2006.285.19:11:04.08#ibcon#about to read 4, iclass 30, count 0 2006.285.19:11:04.08#ibcon#read 4, iclass 30, count 0 2006.285.19:11:04.08#ibcon#about to read 5, iclass 30, count 0 2006.285.19:11:04.08#ibcon#read 5, iclass 30, count 0 2006.285.19:11:04.08#ibcon#about to read 6, iclass 30, count 0 2006.285.19:11:04.08#ibcon#read 6, iclass 30, count 0 2006.285.19:11:04.08#ibcon#end of sib2, iclass 30, count 0 2006.285.19:11:04.08#ibcon#*after write, iclass 30, count 0 2006.285.19:11:04.08#ibcon#*before return 0, iclass 30, count 0 2006.285.19:11:04.08#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:11:04.08#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:11:04.08#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.19:11:04.08#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.19:11:04.08$vck44/valo=7,864.99 2006.285.19:11:04.08#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.19:11:04.08#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.19:11:04.08#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:04.08#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:11:04.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:11:04.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:11:04.08#ibcon#enter wrdev, iclass 32, count 0 2006.285.19:11:04.08#ibcon#first serial, iclass 32, count 0 2006.285.19:11:04.08#ibcon#enter sib2, iclass 32, count 0 2006.285.19:11:04.08#ibcon#flushed, iclass 32, count 0 2006.285.19:11:04.08#ibcon#about to write, iclass 32, count 0 2006.285.19:11:04.08#ibcon#wrote, iclass 32, count 0 2006.285.19:11:04.08#ibcon#about to read 3, iclass 32, count 0 2006.285.19:11:04.10#ibcon#read 3, iclass 32, count 0 2006.285.19:11:04.10#ibcon#about to read 4, iclass 32, count 0 2006.285.19:11:04.10#ibcon#read 4, iclass 32, count 0 2006.285.19:11:04.10#ibcon#about to read 5, iclass 32, count 0 2006.285.19:11:04.10#ibcon#read 5, iclass 32, count 0 2006.285.19:11:04.10#ibcon#about to read 6, iclass 32, count 0 2006.285.19:11:04.10#ibcon#read 6, iclass 32, count 0 2006.285.19:11:04.10#ibcon#end of sib2, iclass 32, count 0 2006.285.19:11:04.10#ibcon#*mode == 0, iclass 32, count 0 2006.285.19:11:04.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.19:11:04.10#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.19:11:04.10#ibcon#*before write, iclass 32, count 0 2006.285.19:11:04.10#ibcon#enter sib2, iclass 32, count 0 2006.285.19:11:04.10#ibcon#flushed, iclass 32, count 0 2006.285.19:11:04.10#ibcon#about to write, iclass 32, count 0 2006.285.19:11:04.10#ibcon#wrote, iclass 32, count 0 2006.285.19:11:04.10#ibcon#about to read 3, iclass 32, count 0 2006.285.19:11:04.14#ibcon#read 3, iclass 32, count 0 2006.285.19:11:04.14#ibcon#about to read 4, iclass 32, count 0 2006.285.19:11:04.14#ibcon#read 4, iclass 32, count 0 2006.285.19:11:04.14#ibcon#about to read 5, iclass 32, count 0 2006.285.19:11:04.14#ibcon#read 5, iclass 32, count 0 2006.285.19:11:04.14#ibcon#about to read 6, iclass 32, count 0 2006.285.19:11:04.14#ibcon#read 6, iclass 32, count 0 2006.285.19:11:04.14#ibcon#end of sib2, iclass 32, count 0 2006.285.19:11:04.14#ibcon#*after write, iclass 32, count 0 2006.285.19:11:04.14#ibcon#*before return 0, iclass 32, count 0 2006.285.19:11:04.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:11:04.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:11:04.14#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.19:11:04.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.19:11:04.14$vck44/va=7,4 2006.285.19:11:04.14#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.19:11:04.14#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.19:11:04.14#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:04.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:11:04.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:11:04.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:11:04.20#ibcon#enter wrdev, iclass 34, count 2 2006.285.19:11:04.20#ibcon#first serial, iclass 34, count 2 2006.285.19:11:04.20#ibcon#enter sib2, iclass 34, count 2 2006.285.19:11:04.20#ibcon#flushed, iclass 34, count 2 2006.285.19:11:04.20#ibcon#about to write, iclass 34, count 2 2006.285.19:11:04.20#ibcon#wrote, iclass 34, count 2 2006.285.19:11:04.20#ibcon#about to read 3, iclass 34, count 2 2006.285.19:11:04.22#ibcon#read 3, iclass 34, count 2 2006.285.19:11:04.22#ibcon#about to read 4, iclass 34, count 2 2006.285.19:11:04.22#ibcon#read 4, iclass 34, count 2 2006.285.19:11:04.22#ibcon#about to read 5, iclass 34, count 2 2006.285.19:11:04.22#ibcon#read 5, iclass 34, count 2 2006.285.19:11:04.22#ibcon#about to read 6, iclass 34, count 2 2006.285.19:11:04.22#ibcon#read 6, iclass 34, count 2 2006.285.19:11:04.22#ibcon#end of sib2, iclass 34, count 2 2006.285.19:11:04.22#ibcon#*mode == 0, iclass 34, count 2 2006.285.19:11:04.22#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.19:11:04.22#ibcon#[25=AT07-04\r\n] 2006.285.19:11:04.22#ibcon#*before write, iclass 34, count 2 2006.285.19:11:04.22#ibcon#enter sib2, iclass 34, count 2 2006.285.19:11:04.22#ibcon#flushed, iclass 34, count 2 2006.285.19:11:04.22#ibcon#about to write, iclass 34, count 2 2006.285.19:11:04.22#ibcon#wrote, iclass 34, count 2 2006.285.19:11:04.22#ibcon#about to read 3, iclass 34, count 2 2006.285.19:11:04.25#ibcon#read 3, iclass 34, count 2 2006.285.19:11:04.25#ibcon#about to read 4, iclass 34, count 2 2006.285.19:11:04.25#ibcon#read 4, iclass 34, count 2 2006.285.19:11:04.25#ibcon#about to read 5, iclass 34, count 2 2006.285.19:11:04.25#ibcon#read 5, iclass 34, count 2 2006.285.19:11:04.25#ibcon#about to read 6, iclass 34, count 2 2006.285.19:11:04.25#ibcon#read 6, iclass 34, count 2 2006.285.19:11:04.25#ibcon#end of sib2, iclass 34, count 2 2006.285.19:11:04.25#ibcon#*after write, iclass 34, count 2 2006.285.19:11:04.25#ibcon#*before return 0, iclass 34, count 2 2006.285.19:11:04.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:11:04.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:11:04.25#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.19:11:04.25#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:04.25#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:11:04.37#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:11:04.37#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:11:04.37#ibcon#enter wrdev, iclass 34, count 0 2006.285.19:11:04.37#ibcon#first serial, iclass 34, count 0 2006.285.19:11:04.37#ibcon#enter sib2, iclass 34, count 0 2006.285.19:11:04.37#ibcon#flushed, iclass 34, count 0 2006.285.19:11:04.37#ibcon#about to write, iclass 34, count 0 2006.285.19:11:04.37#ibcon#wrote, iclass 34, count 0 2006.285.19:11:04.37#ibcon#about to read 3, iclass 34, count 0 2006.285.19:11:04.39#ibcon#read 3, iclass 34, count 0 2006.285.19:11:04.39#ibcon#about to read 4, iclass 34, count 0 2006.285.19:11:04.39#ibcon#read 4, iclass 34, count 0 2006.285.19:11:04.39#ibcon#about to read 5, iclass 34, count 0 2006.285.19:11:04.39#ibcon#read 5, iclass 34, count 0 2006.285.19:11:04.39#ibcon#about to read 6, iclass 34, count 0 2006.285.19:11:04.39#ibcon#read 6, iclass 34, count 0 2006.285.19:11:04.39#ibcon#end of sib2, iclass 34, count 0 2006.285.19:11:04.39#ibcon#*mode == 0, iclass 34, count 0 2006.285.19:11:04.39#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.19:11:04.39#ibcon#[25=USB\r\n] 2006.285.19:11:04.39#ibcon#*before write, iclass 34, count 0 2006.285.19:11:04.39#ibcon#enter sib2, iclass 34, count 0 2006.285.19:11:04.39#ibcon#flushed, iclass 34, count 0 2006.285.19:11:04.39#ibcon#about to write, iclass 34, count 0 2006.285.19:11:04.39#ibcon#wrote, iclass 34, count 0 2006.285.19:11:04.39#ibcon#about to read 3, iclass 34, count 0 2006.285.19:11:04.42#ibcon#read 3, iclass 34, count 0 2006.285.19:11:04.42#ibcon#about to read 4, iclass 34, count 0 2006.285.19:11:04.42#ibcon#read 4, iclass 34, count 0 2006.285.19:11:04.42#ibcon#about to read 5, iclass 34, count 0 2006.285.19:11:04.42#ibcon#read 5, iclass 34, count 0 2006.285.19:11:04.42#ibcon#about to read 6, iclass 34, count 0 2006.285.19:11:04.42#ibcon#read 6, iclass 34, count 0 2006.285.19:11:04.42#ibcon#end of sib2, iclass 34, count 0 2006.285.19:11:04.42#ibcon#*after write, iclass 34, count 0 2006.285.19:11:04.42#ibcon#*before return 0, iclass 34, count 0 2006.285.19:11:04.42#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:11:04.42#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:11:04.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.19:11:04.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.19:11:04.42$vck44/valo=8,884.99 2006.285.19:11:04.42#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.19:11:04.42#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.19:11:04.42#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:04.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:11:04.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:11:04.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:11:04.42#ibcon#enter wrdev, iclass 36, count 0 2006.285.19:11:04.42#ibcon#first serial, iclass 36, count 0 2006.285.19:11:04.42#ibcon#enter sib2, iclass 36, count 0 2006.285.19:11:04.42#ibcon#flushed, iclass 36, count 0 2006.285.19:11:04.42#ibcon#about to write, iclass 36, count 0 2006.285.19:11:04.42#ibcon#wrote, iclass 36, count 0 2006.285.19:11:04.42#ibcon#about to read 3, iclass 36, count 0 2006.285.19:11:04.44#ibcon#read 3, iclass 36, count 0 2006.285.19:11:04.44#ibcon#about to read 4, iclass 36, count 0 2006.285.19:11:04.44#ibcon#read 4, iclass 36, count 0 2006.285.19:11:04.44#ibcon#about to read 5, iclass 36, count 0 2006.285.19:11:04.44#ibcon#read 5, iclass 36, count 0 2006.285.19:11:04.44#ibcon#about to read 6, iclass 36, count 0 2006.285.19:11:04.44#ibcon#read 6, iclass 36, count 0 2006.285.19:11:04.44#ibcon#end of sib2, iclass 36, count 0 2006.285.19:11:04.44#ibcon#*mode == 0, iclass 36, count 0 2006.285.19:11:04.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.19:11:04.44#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.19:11:04.44#ibcon#*before write, iclass 36, count 0 2006.285.19:11:04.44#ibcon#enter sib2, iclass 36, count 0 2006.285.19:11:04.44#ibcon#flushed, iclass 36, count 0 2006.285.19:11:04.44#ibcon#about to write, iclass 36, count 0 2006.285.19:11:04.44#ibcon#wrote, iclass 36, count 0 2006.285.19:11:04.44#ibcon#about to read 3, iclass 36, count 0 2006.285.19:11:04.48#ibcon#read 3, iclass 36, count 0 2006.285.19:11:04.48#ibcon#about to read 4, iclass 36, count 0 2006.285.19:11:04.48#ibcon#read 4, iclass 36, count 0 2006.285.19:11:04.48#ibcon#about to read 5, iclass 36, count 0 2006.285.19:11:04.48#ibcon#read 5, iclass 36, count 0 2006.285.19:11:04.48#ibcon#about to read 6, iclass 36, count 0 2006.285.19:11:04.48#ibcon#read 6, iclass 36, count 0 2006.285.19:11:04.48#ibcon#end of sib2, iclass 36, count 0 2006.285.19:11:04.48#ibcon#*after write, iclass 36, count 0 2006.285.19:11:04.48#ibcon#*before return 0, iclass 36, count 0 2006.285.19:11:04.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:11:04.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:11:04.48#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.19:11:04.48#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.19:11:04.48$vck44/va=8,3 2006.285.19:11:04.48#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.19:11:04.48#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.19:11:04.48#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:04.48#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:11:04.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:11:04.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:11:04.54#ibcon#enter wrdev, iclass 38, count 2 2006.285.19:11:04.54#ibcon#first serial, iclass 38, count 2 2006.285.19:11:04.54#ibcon#enter sib2, iclass 38, count 2 2006.285.19:11:04.54#ibcon#flushed, iclass 38, count 2 2006.285.19:11:04.54#ibcon#about to write, iclass 38, count 2 2006.285.19:11:04.54#ibcon#wrote, iclass 38, count 2 2006.285.19:11:04.54#ibcon#about to read 3, iclass 38, count 2 2006.285.19:11:04.56#ibcon#read 3, iclass 38, count 2 2006.285.19:11:04.56#ibcon#about to read 4, iclass 38, count 2 2006.285.19:11:04.56#ibcon#read 4, iclass 38, count 2 2006.285.19:11:04.56#ibcon#about to read 5, iclass 38, count 2 2006.285.19:11:04.56#ibcon#read 5, iclass 38, count 2 2006.285.19:11:04.56#ibcon#about to read 6, iclass 38, count 2 2006.285.19:11:04.56#ibcon#read 6, iclass 38, count 2 2006.285.19:11:04.56#ibcon#end of sib2, iclass 38, count 2 2006.285.19:11:04.56#ibcon#*mode == 0, iclass 38, count 2 2006.285.19:11:04.56#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.19:11:04.56#ibcon#[25=AT08-03\r\n] 2006.285.19:11:04.56#ibcon#*before write, iclass 38, count 2 2006.285.19:11:04.56#ibcon#enter sib2, iclass 38, count 2 2006.285.19:11:04.56#ibcon#flushed, iclass 38, count 2 2006.285.19:11:04.56#ibcon#about to write, iclass 38, count 2 2006.285.19:11:04.56#ibcon#wrote, iclass 38, count 2 2006.285.19:11:04.56#ibcon#about to read 3, iclass 38, count 2 2006.285.19:11:04.59#ibcon#read 3, iclass 38, count 2 2006.285.19:11:04.59#ibcon#about to read 4, iclass 38, count 2 2006.285.19:11:04.59#ibcon#read 4, iclass 38, count 2 2006.285.19:11:04.59#ibcon#about to read 5, iclass 38, count 2 2006.285.19:11:04.59#ibcon#read 5, iclass 38, count 2 2006.285.19:11:04.59#ibcon#about to read 6, iclass 38, count 2 2006.285.19:11:04.59#ibcon#read 6, iclass 38, count 2 2006.285.19:11:04.59#ibcon#end of sib2, iclass 38, count 2 2006.285.19:11:04.59#ibcon#*after write, iclass 38, count 2 2006.285.19:11:04.59#ibcon#*before return 0, iclass 38, count 2 2006.285.19:11:04.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:11:04.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:11:04.59#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.19:11:04.59#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:04.59#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:11:04.71#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:11:04.71#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:11:04.71#ibcon#enter wrdev, iclass 38, count 0 2006.285.19:11:04.71#ibcon#first serial, iclass 38, count 0 2006.285.19:11:04.71#ibcon#enter sib2, iclass 38, count 0 2006.285.19:11:04.71#ibcon#flushed, iclass 38, count 0 2006.285.19:11:04.71#ibcon#about to write, iclass 38, count 0 2006.285.19:11:04.71#ibcon#wrote, iclass 38, count 0 2006.285.19:11:04.71#ibcon#about to read 3, iclass 38, count 0 2006.285.19:11:04.73#ibcon#read 3, iclass 38, count 0 2006.285.19:11:04.73#ibcon#about to read 4, iclass 38, count 0 2006.285.19:11:04.73#ibcon#read 4, iclass 38, count 0 2006.285.19:11:04.73#ibcon#about to read 5, iclass 38, count 0 2006.285.19:11:04.73#ibcon#read 5, iclass 38, count 0 2006.285.19:11:04.73#ibcon#about to read 6, iclass 38, count 0 2006.285.19:11:04.73#ibcon#read 6, iclass 38, count 0 2006.285.19:11:04.73#ibcon#end of sib2, iclass 38, count 0 2006.285.19:11:04.73#ibcon#*mode == 0, iclass 38, count 0 2006.285.19:11:04.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.19:11:04.73#ibcon#[25=USB\r\n] 2006.285.19:11:04.73#ibcon#*before write, iclass 38, count 0 2006.285.19:11:04.73#ibcon#enter sib2, iclass 38, count 0 2006.285.19:11:04.73#ibcon#flushed, iclass 38, count 0 2006.285.19:11:04.73#ibcon#about to write, iclass 38, count 0 2006.285.19:11:04.73#ibcon#wrote, iclass 38, count 0 2006.285.19:11:04.73#ibcon#about to read 3, iclass 38, count 0 2006.285.19:11:04.76#ibcon#read 3, iclass 38, count 0 2006.285.19:11:04.76#ibcon#about to read 4, iclass 38, count 0 2006.285.19:11:04.76#ibcon#read 4, iclass 38, count 0 2006.285.19:11:04.76#ibcon#about to read 5, iclass 38, count 0 2006.285.19:11:04.76#ibcon#read 5, iclass 38, count 0 2006.285.19:11:04.76#ibcon#about to read 6, iclass 38, count 0 2006.285.19:11:04.76#ibcon#read 6, iclass 38, count 0 2006.285.19:11:04.76#ibcon#end of sib2, iclass 38, count 0 2006.285.19:11:04.76#ibcon#*after write, iclass 38, count 0 2006.285.19:11:04.76#ibcon#*before return 0, iclass 38, count 0 2006.285.19:11:04.76#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:11:04.76#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:11:04.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.19:11:04.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.19:11:04.76$vck44/vblo=1,629.99 2006.285.19:11:04.76#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.19:11:04.76#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.19:11:04.76#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:04.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:11:04.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:11:04.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:11:04.76#ibcon#enter wrdev, iclass 40, count 0 2006.285.19:11:04.76#ibcon#first serial, iclass 40, count 0 2006.285.19:11:04.76#ibcon#enter sib2, iclass 40, count 0 2006.285.19:11:04.76#ibcon#flushed, iclass 40, count 0 2006.285.19:11:04.76#ibcon#about to write, iclass 40, count 0 2006.285.19:11:04.76#ibcon#wrote, iclass 40, count 0 2006.285.19:11:04.76#ibcon#about to read 3, iclass 40, count 0 2006.285.19:11:04.78#ibcon#read 3, iclass 40, count 0 2006.285.19:11:04.78#ibcon#about to read 4, iclass 40, count 0 2006.285.19:11:04.78#ibcon#read 4, iclass 40, count 0 2006.285.19:11:04.78#ibcon#about to read 5, iclass 40, count 0 2006.285.19:11:04.78#ibcon#read 5, iclass 40, count 0 2006.285.19:11:04.78#ibcon#about to read 6, iclass 40, count 0 2006.285.19:11:04.78#ibcon#read 6, iclass 40, count 0 2006.285.19:11:04.78#ibcon#end of sib2, iclass 40, count 0 2006.285.19:11:04.78#ibcon#*mode == 0, iclass 40, count 0 2006.285.19:11:04.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.19:11:04.78#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.19:11:04.78#ibcon#*before write, iclass 40, count 0 2006.285.19:11:04.78#ibcon#enter sib2, iclass 40, count 0 2006.285.19:11:04.78#ibcon#flushed, iclass 40, count 0 2006.285.19:11:04.78#ibcon#about to write, iclass 40, count 0 2006.285.19:11:04.78#ibcon#wrote, iclass 40, count 0 2006.285.19:11:04.78#ibcon#about to read 3, iclass 40, count 0 2006.285.19:11:04.82#ibcon#read 3, iclass 40, count 0 2006.285.19:11:04.82#ibcon#about to read 4, iclass 40, count 0 2006.285.19:11:04.82#ibcon#read 4, iclass 40, count 0 2006.285.19:11:04.82#ibcon#about to read 5, iclass 40, count 0 2006.285.19:11:04.82#ibcon#read 5, iclass 40, count 0 2006.285.19:11:04.82#ibcon#about to read 6, iclass 40, count 0 2006.285.19:11:04.82#ibcon#read 6, iclass 40, count 0 2006.285.19:11:04.82#ibcon#end of sib2, iclass 40, count 0 2006.285.19:11:04.82#ibcon#*after write, iclass 40, count 0 2006.285.19:11:04.82#ibcon#*before return 0, iclass 40, count 0 2006.285.19:11:04.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:11:04.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:11:04.82#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.19:11:04.82#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.19:11:04.82$vck44/vb=1,4 2006.285.19:11:04.82#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.19:11:04.82#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.19:11:04.82#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:04.82#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:11:04.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:11:04.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:11:04.82#ibcon#enter wrdev, iclass 4, count 2 2006.285.19:11:04.82#ibcon#first serial, iclass 4, count 2 2006.285.19:11:04.82#ibcon#enter sib2, iclass 4, count 2 2006.285.19:11:04.82#ibcon#flushed, iclass 4, count 2 2006.285.19:11:04.82#ibcon#about to write, iclass 4, count 2 2006.285.19:11:04.82#ibcon#wrote, iclass 4, count 2 2006.285.19:11:04.82#ibcon#about to read 3, iclass 4, count 2 2006.285.19:11:04.84#ibcon#read 3, iclass 4, count 2 2006.285.19:11:04.84#ibcon#about to read 4, iclass 4, count 2 2006.285.19:11:04.84#ibcon#read 4, iclass 4, count 2 2006.285.19:11:04.84#ibcon#about to read 5, iclass 4, count 2 2006.285.19:11:04.84#ibcon#read 5, iclass 4, count 2 2006.285.19:11:04.84#ibcon#about to read 6, iclass 4, count 2 2006.285.19:11:04.84#ibcon#read 6, iclass 4, count 2 2006.285.19:11:04.84#ibcon#end of sib2, iclass 4, count 2 2006.285.19:11:04.84#ibcon#*mode == 0, iclass 4, count 2 2006.285.19:11:04.84#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.19:11:04.84#ibcon#[27=AT01-04\r\n] 2006.285.19:11:04.84#ibcon#*before write, iclass 4, count 2 2006.285.19:11:04.84#ibcon#enter sib2, iclass 4, count 2 2006.285.19:11:04.84#ibcon#flushed, iclass 4, count 2 2006.285.19:11:04.84#ibcon#about to write, iclass 4, count 2 2006.285.19:11:04.84#ibcon#wrote, iclass 4, count 2 2006.285.19:11:04.84#ibcon#about to read 3, iclass 4, count 2 2006.285.19:11:04.87#ibcon#read 3, iclass 4, count 2 2006.285.19:11:04.87#ibcon#about to read 4, iclass 4, count 2 2006.285.19:11:04.87#ibcon#read 4, iclass 4, count 2 2006.285.19:11:04.87#ibcon#about to read 5, iclass 4, count 2 2006.285.19:11:04.87#ibcon#read 5, iclass 4, count 2 2006.285.19:11:04.87#ibcon#about to read 6, iclass 4, count 2 2006.285.19:11:04.87#ibcon#read 6, iclass 4, count 2 2006.285.19:11:04.87#ibcon#end of sib2, iclass 4, count 2 2006.285.19:11:04.87#ibcon#*after write, iclass 4, count 2 2006.285.19:11:04.87#ibcon#*before return 0, iclass 4, count 2 2006.285.19:11:04.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:11:04.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:11:04.87#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.19:11:04.87#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:04.87#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:11:04.99#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:11:04.99#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:11:04.99#ibcon#enter wrdev, iclass 4, count 0 2006.285.19:11:04.99#ibcon#first serial, iclass 4, count 0 2006.285.19:11:04.99#ibcon#enter sib2, iclass 4, count 0 2006.285.19:11:04.99#ibcon#flushed, iclass 4, count 0 2006.285.19:11:04.99#ibcon#about to write, iclass 4, count 0 2006.285.19:11:04.99#ibcon#wrote, iclass 4, count 0 2006.285.19:11:04.99#ibcon#about to read 3, iclass 4, count 0 2006.285.19:11:05.01#ibcon#read 3, iclass 4, count 0 2006.285.19:11:05.01#ibcon#about to read 4, iclass 4, count 0 2006.285.19:11:05.01#ibcon#read 4, iclass 4, count 0 2006.285.19:11:05.01#ibcon#about to read 5, iclass 4, count 0 2006.285.19:11:05.01#ibcon#read 5, iclass 4, count 0 2006.285.19:11:05.01#ibcon#about to read 6, iclass 4, count 0 2006.285.19:11:05.01#ibcon#read 6, iclass 4, count 0 2006.285.19:11:05.01#ibcon#end of sib2, iclass 4, count 0 2006.285.19:11:05.01#ibcon#*mode == 0, iclass 4, count 0 2006.285.19:11:05.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.19:11:05.01#ibcon#[27=USB\r\n] 2006.285.19:11:05.01#ibcon#*before write, iclass 4, count 0 2006.285.19:11:05.01#ibcon#enter sib2, iclass 4, count 0 2006.285.19:11:05.01#ibcon#flushed, iclass 4, count 0 2006.285.19:11:05.01#ibcon#about to write, iclass 4, count 0 2006.285.19:11:05.01#ibcon#wrote, iclass 4, count 0 2006.285.19:11:05.01#ibcon#about to read 3, iclass 4, count 0 2006.285.19:11:05.04#ibcon#read 3, iclass 4, count 0 2006.285.19:11:05.04#ibcon#about to read 4, iclass 4, count 0 2006.285.19:11:05.04#ibcon#read 4, iclass 4, count 0 2006.285.19:11:05.04#ibcon#about to read 5, iclass 4, count 0 2006.285.19:11:05.04#ibcon#read 5, iclass 4, count 0 2006.285.19:11:05.04#ibcon#about to read 6, iclass 4, count 0 2006.285.19:11:05.04#ibcon#read 6, iclass 4, count 0 2006.285.19:11:05.04#ibcon#end of sib2, iclass 4, count 0 2006.285.19:11:05.04#ibcon#*after write, iclass 4, count 0 2006.285.19:11:05.04#ibcon#*before return 0, iclass 4, count 0 2006.285.19:11:05.04#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:11:05.04#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:11:05.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.19:11:05.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.19:11:05.04$vck44/vblo=2,634.99 2006.285.19:11:05.04#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.19:11:05.04#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.19:11:05.04#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:05.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:11:05.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:11:05.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:11:05.04#ibcon#enter wrdev, iclass 6, count 0 2006.285.19:11:05.04#ibcon#first serial, iclass 6, count 0 2006.285.19:11:05.04#ibcon#enter sib2, iclass 6, count 0 2006.285.19:11:05.04#ibcon#flushed, iclass 6, count 0 2006.285.19:11:05.04#ibcon#about to write, iclass 6, count 0 2006.285.19:11:05.04#ibcon#wrote, iclass 6, count 0 2006.285.19:11:05.04#ibcon#about to read 3, iclass 6, count 0 2006.285.19:11:05.06#ibcon#read 3, iclass 6, count 0 2006.285.19:11:05.10#ibcon#about to read 4, iclass 6, count 0 2006.285.19:11:05.10#ibcon#read 4, iclass 6, count 0 2006.285.19:11:05.10#ibcon#about to read 5, iclass 6, count 0 2006.285.19:11:05.10#ibcon#read 5, iclass 6, count 0 2006.285.19:11:05.10#ibcon#about to read 6, iclass 6, count 0 2006.285.19:11:05.10#ibcon#read 6, iclass 6, count 0 2006.285.19:11:05.10#ibcon#end of sib2, iclass 6, count 0 2006.285.19:11:05.10#ibcon#*mode == 0, iclass 6, count 0 2006.285.19:11:05.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.19:11:05.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.19:11:05.10#ibcon#*before write, iclass 6, count 0 2006.285.19:11:05.10#ibcon#enter sib2, iclass 6, count 0 2006.285.19:11:05.10#ibcon#flushed, iclass 6, count 0 2006.285.19:11:05.10#ibcon#about to write, iclass 6, count 0 2006.285.19:11:05.10#ibcon#wrote, iclass 6, count 0 2006.285.19:11:05.10#ibcon#about to read 3, iclass 6, count 0 2006.285.19:11:05.14#ibcon#read 3, iclass 6, count 0 2006.285.19:11:05.14#ibcon#about to read 4, iclass 6, count 0 2006.285.19:11:05.14#ibcon#read 4, iclass 6, count 0 2006.285.19:11:05.14#ibcon#about to read 5, iclass 6, count 0 2006.285.19:11:05.14#ibcon#read 5, iclass 6, count 0 2006.285.19:11:05.14#ibcon#about to read 6, iclass 6, count 0 2006.285.19:11:05.14#ibcon#read 6, iclass 6, count 0 2006.285.19:11:05.14#ibcon#end of sib2, iclass 6, count 0 2006.285.19:11:05.14#ibcon#*after write, iclass 6, count 0 2006.285.19:11:05.14#ibcon#*before return 0, iclass 6, count 0 2006.285.19:11:05.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:11:05.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:11:05.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.19:11:05.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.19:11:05.14$vck44/vb=2,5 2006.285.19:11:05.14#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.19:11:05.14#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.19:11:05.14#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:05.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:11:05.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:11:05.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:11:05.16#ibcon#enter wrdev, iclass 10, count 2 2006.285.19:11:05.16#ibcon#first serial, iclass 10, count 2 2006.285.19:11:05.16#ibcon#enter sib2, iclass 10, count 2 2006.285.19:11:05.16#ibcon#flushed, iclass 10, count 2 2006.285.19:11:05.16#ibcon#about to write, iclass 10, count 2 2006.285.19:11:05.16#ibcon#wrote, iclass 10, count 2 2006.285.19:11:05.16#ibcon#about to read 3, iclass 10, count 2 2006.285.19:11:05.18#ibcon#read 3, iclass 10, count 2 2006.285.19:11:05.18#ibcon#about to read 4, iclass 10, count 2 2006.285.19:11:05.18#ibcon#read 4, iclass 10, count 2 2006.285.19:11:05.18#ibcon#about to read 5, iclass 10, count 2 2006.285.19:11:05.18#ibcon#read 5, iclass 10, count 2 2006.285.19:11:05.18#ibcon#about to read 6, iclass 10, count 2 2006.285.19:11:05.18#ibcon#read 6, iclass 10, count 2 2006.285.19:11:05.18#ibcon#end of sib2, iclass 10, count 2 2006.285.19:11:05.18#ibcon#*mode == 0, iclass 10, count 2 2006.285.19:11:05.18#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.19:11:05.18#ibcon#[27=AT02-05\r\n] 2006.285.19:11:05.18#ibcon#*before write, iclass 10, count 2 2006.285.19:11:05.18#ibcon#enter sib2, iclass 10, count 2 2006.285.19:11:05.18#ibcon#flushed, iclass 10, count 2 2006.285.19:11:05.18#ibcon#about to write, iclass 10, count 2 2006.285.19:11:05.18#ibcon#wrote, iclass 10, count 2 2006.285.19:11:05.18#ibcon#about to read 3, iclass 10, count 2 2006.285.19:11:05.21#ibcon#read 3, iclass 10, count 2 2006.285.19:11:05.21#ibcon#about to read 4, iclass 10, count 2 2006.285.19:11:05.21#ibcon#read 4, iclass 10, count 2 2006.285.19:11:05.21#ibcon#about to read 5, iclass 10, count 2 2006.285.19:11:05.21#ibcon#read 5, iclass 10, count 2 2006.285.19:11:05.21#ibcon#about to read 6, iclass 10, count 2 2006.285.19:11:05.21#ibcon#read 6, iclass 10, count 2 2006.285.19:11:05.21#ibcon#end of sib2, iclass 10, count 2 2006.285.19:11:05.21#ibcon#*after write, iclass 10, count 2 2006.285.19:11:05.21#ibcon#*before return 0, iclass 10, count 2 2006.285.19:11:05.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:11:05.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:11:05.21#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.19:11:05.21#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:05.21#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:11:05.33#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:11:05.33#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:11:05.33#ibcon#enter wrdev, iclass 10, count 0 2006.285.19:11:05.33#ibcon#first serial, iclass 10, count 0 2006.285.19:11:05.33#ibcon#enter sib2, iclass 10, count 0 2006.285.19:11:05.33#ibcon#flushed, iclass 10, count 0 2006.285.19:11:05.33#ibcon#about to write, iclass 10, count 0 2006.285.19:11:05.33#ibcon#wrote, iclass 10, count 0 2006.285.19:11:05.33#ibcon#about to read 3, iclass 10, count 0 2006.285.19:11:05.35#ibcon#read 3, iclass 10, count 0 2006.285.19:11:05.35#ibcon#about to read 4, iclass 10, count 0 2006.285.19:11:05.35#ibcon#read 4, iclass 10, count 0 2006.285.19:11:05.35#ibcon#about to read 5, iclass 10, count 0 2006.285.19:11:05.35#ibcon#read 5, iclass 10, count 0 2006.285.19:11:05.35#ibcon#about to read 6, iclass 10, count 0 2006.285.19:11:05.35#ibcon#read 6, iclass 10, count 0 2006.285.19:11:05.35#ibcon#end of sib2, iclass 10, count 0 2006.285.19:11:05.35#ibcon#*mode == 0, iclass 10, count 0 2006.285.19:11:05.35#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.19:11:05.35#ibcon#[27=USB\r\n] 2006.285.19:11:05.35#ibcon#*before write, iclass 10, count 0 2006.285.19:11:05.35#ibcon#enter sib2, iclass 10, count 0 2006.285.19:11:05.35#ibcon#flushed, iclass 10, count 0 2006.285.19:11:05.35#ibcon#about to write, iclass 10, count 0 2006.285.19:11:05.35#ibcon#wrote, iclass 10, count 0 2006.285.19:11:05.35#ibcon#about to read 3, iclass 10, count 0 2006.285.19:11:05.38#ibcon#read 3, iclass 10, count 0 2006.285.19:11:05.38#ibcon#about to read 4, iclass 10, count 0 2006.285.19:11:05.38#ibcon#read 4, iclass 10, count 0 2006.285.19:11:05.38#ibcon#about to read 5, iclass 10, count 0 2006.285.19:11:05.38#ibcon#read 5, iclass 10, count 0 2006.285.19:11:05.38#ibcon#about to read 6, iclass 10, count 0 2006.285.19:11:05.38#ibcon#read 6, iclass 10, count 0 2006.285.19:11:05.38#ibcon#end of sib2, iclass 10, count 0 2006.285.19:11:05.38#ibcon#*after write, iclass 10, count 0 2006.285.19:11:05.38#ibcon#*before return 0, iclass 10, count 0 2006.285.19:11:05.38#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:11:05.38#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:11:05.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.19:11:05.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.19:11:05.38$vck44/vblo=3,649.99 2006.285.19:11:05.38#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.19:11:05.38#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.19:11:05.38#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:05.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:11:05.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:11:05.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:11:05.38#ibcon#enter wrdev, iclass 12, count 0 2006.285.19:11:05.38#ibcon#first serial, iclass 12, count 0 2006.285.19:11:05.38#ibcon#enter sib2, iclass 12, count 0 2006.285.19:11:05.38#ibcon#flushed, iclass 12, count 0 2006.285.19:11:05.38#ibcon#about to write, iclass 12, count 0 2006.285.19:11:05.38#ibcon#wrote, iclass 12, count 0 2006.285.19:11:05.38#ibcon#about to read 3, iclass 12, count 0 2006.285.19:11:05.40#ibcon#read 3, iclass 12, count 0 2006.285.19:11:05.40#ibcon#about to read 4, iclass 12, count 0 2006.285.19:11:05.40#ibcon#read 4, iclass 12, count 0 2006.285.19:11:05.40#ibcon#about to read 5, iclass 12, count 0 2006.285.19:11:05.40#ibcon#read 5, iclass 12, count 0 2006.285.19:11:05.40#ibcon#about to read 6, iclass 12, count 0 2006.285.19:11:05.40#ibcon#read 6, iclass 12, count 0 2006.285.19:11:05.40#ibcon#end of sib2, iclass 12, count 0 2006.285.19:11:05.40#ibcon#*mode == 0, iclass 12, count 0 2006.285.19:11:05.40#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.19:11:05.40#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.19:11:05.40#ibcon#*before write, iclass 12, count 0 2006.285.19:11:05.40#ibcon#enter sib2, iclass 12, count 0 2006.285.19:11:05.40#ibcon#flushed, iclass 12, count 0 2006.285.19:11:05.40#ibcon#about to write, iclass 12, count 0 2006.285.19:11:05.40#ibcon#wrote, iclass 12, count 0 2006.285.19:11:05.40#ibcon#about to read 3, iclass 12, count 0 2006.285.19:11:05.44#ibcon#read 3, iclass 12, count 0 2006.285.19:11:05.44#ibcon#about to read 4, iclass 12, count 0 2006.285.19:11:05.44#ibcon#read 4, iclass 12, count 0 2006.285.19:11:05.44#ibcon#about to read 5, iclass 12, count 0 2006.285.19:11:05.44#ibcon#read 5, iclass 12, count 0 2006.285.19:11:05.44#ibcon#about to read 6, iclass 12, count 0 2006.285.19:11:05.44#ibcon#read 6, iclass 12, count 0 2006.285.19:11:05.44#ibcon#end of sib2, iclass 12, count 0 2006.285.19:11:05.44#ibcon#*after write, iclass 12, count 0 2006.285.19:11:05.44#ibcon#*before return 0, iclass 12, count 0 2006.285.19:11:05.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:11:05.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:11:05.44#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.19:11:05.44#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.19:11:05.44$vck44/vb=3,4 2006.285.19:11:05.44#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.19:11:05.44#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.19:11:05.44#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:05.44#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:11:05.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:11:05.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:11:05.50#ibcon#enter wrdev, iclass 14, count 2 2006.285.19:11:05.50#ibcon#first serial, iclass 14, count 2 2006.285.19:11:05.50#ibcon#enter sib2, iclass 14, count 2 2006.285.19:11:05.50#ibcon#flushed, iclass 14, count 2 2006.285.19:11:05.50#ibcon#about to write, iclass 14, count 2 2006.285.19:11:05.50#ibcon#wrote, iclass 14, count 2 2006.285.19:11:05.50#ibcon#about to read 3, iclass 14, count 2 2006.285.19:11:05.52#ibcon#read 3, iclass 14, count 2 2006.285.19:11:05.52#ibcon#about to read 4, iclass 14, count 2 2006.285.19:11:05.52#ibcon#read 4, iclass 14, count 2 2006.285.19:11:05.52#ibcon#about to read 5, iclass 14, count 2 2006.285.19:11:05.52#ibcon#read 5, iclass 14, count 2 2006.285.19:11:05.52#ibcon#about to read 6, iclass 14, count 2 2006.285.19:11:05.52#ibcon#read 6, iclass 14, count 2 2006.285.19:11:05.52#ibcon#end of sib2, iclass 14, count 2 2006.285.19:11:05.52#ibcon#*mode == 0, iclass 14, count 2 2006.285.19:11:05.52#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.19:11:05.52#ibcon#[27=AT03-04\r\n] 2006.285.19:11:05.52#ibcon#*before write, iclass 14, count 2 2006.285.19:11:05.52#ibcon#enter sib2, iclass 14, count 2 2006.285.19:11:05.52#ibcon#flushed, iclass 14, count 2 2006.285.19:11:05.52#ibcon#about to write, iclass 14, count 2 2006.285.19:11:05.52#ibcon#wrote, iclass 14, count 2 2006.285.19:11:05.52#ibcon#about to read 3, iclass 14, count 2 2006.285.19:11:05.55#ibcon#read 3, iclass 14, count 2 2006.285.19:11:05.55#ibcon#about to read 4, iclass 14, count 2 2006.285.19:11:05.55#ibcon#read 4, iclass 14, count 2 2006.285.19:11:05.55#ibcon#about to read 5, iclass 14, count 2 2006.285.19:11:05.55#ibcon#read 5, iclass 14, count 2 2006.285.19:11:05.55#ibcon#about to read 6, iclass 14, count 2 2006.285.19:11:05.55#ibcon#read 6, iclass 14, count 2 2006.285.19:11:05.55#ibcon#end of sib2, iclass 14, count 2 2006.285.19:11:05.55#ibcon#*after write, iclass 14, count 2 2006.285.19:11:05.55#ibcon#*before return 0, iclass 14, count 2 2006.285.19:11:05.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:11:05.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:11:05.55#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.19:11:05.55#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:05.55#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:11:05.67#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:11:05.67#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:11:05.67#ibcon#enter wrdev, iclass 14, count 0 2006.285.19:11:05.67#ibcon#first serial, iclass 14, count 0 2006.285.19:11:05.67#ibcon#enter sib2, iclass 14, count 0 2006.285.19:11:05.67#ibcon#flushed, iclass 14, count 0 2006.285.19:11:05.67#ibcon#about to write, iclass 14, count 0 2006.285.19:11:05.67#ibcon#wrote, iclass 14, count 0 2006.285.19:11:05.67#ibcon#about to read 3, iclass 14, count 0 2006.285.19:11:05.69#ibcon#read 3, iclass 14, count 0 2006.285.19:11:05.69#ibcon#about to read 4, iclass 14, count 0 2006.285.19:11:05.69#ibcon#read 4, iclass 14, count 0 2006.285.19:11:05.69#ibcon#about to read 5, iclass 14, count 0 2006.285.19:11:05.69#ibcon#read 5, iclass 14, count 0 2006.285.19:11:05.69#ibcon#about to read 6, iclass 14, count 0 2006.285.19:11:05.69#ibcon#read 6, iclass 14, count 0 2006.285.19:11:05.69#ibcon#end of sib2, iclass 14, count 0 2006.285.19:11:05.69#ibcon#*mode == 0, iclass 14, count 0 2006.285.19:11:05.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.19:11:05.69#ibcon#[27=USB\r\n] 2006.285.19:11:05.69#ibcon#*before write, iclass 14, count 0 2006.285.19:11:05.69#ibcon#enter sib2, iclass 14, count 0 2006.285.19:11:05.69#ibcon#flushed, iclass 14, count 0 2006.285.19:11:05.69#ibcon#about to write, iclass 14, count 0 2006.285.19:11:05.69#ibcon#wrote, iclass 14, count 0 2006.285.19:11:05.69#ibcon#about to read 3, iclass 14, count 0 2006.285.19:11:05.72#ibcon#read 3, iclass 14, count 0 2006.285.19:11:05.72#ibcon#about to read 4, iclass 14, count 0 2006.285.19:11:05.72#ibcon#read 4, iclass 14, count 0 2006.285.19:11:05.72#ibcon#about to read 5, iclass 14, count 0 2006.285.19:11:05.72#ibcon#read 5, iclass 14, count 0 2006.285.19:11:05.72#ibcon#about to read 6, iclass 14, count 0 2006.285.19:11:05.72#ibcon#read 6, iclass 14, count 0 2006.285.19:11:05.72#ibcon#end of sib2, iclass 14, count 0 2006.285.19:11:05.72#ibcon#*after write, iclass 14, count 0 2006.285.19:11:05.72#ibcon#*before return 0, iclass 14, count 0 2006.285.19:11:05.72#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:11:05.72#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:11:05.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.19:11:05.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.19:11:05.72$vck44/vblo=4,679.99 2006.285.19:11:05.72#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.19:11:05.72#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.19:11:05.72#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:05.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:11:05.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:11:05.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:11:05.72#ibcon#enter wrdev, iclass 16, count 0 2006.285.19:11:05.72#ibcon#first serial, iclass 16, count 0 2006.285.19:11:05.72#ibcon#enter sib2, iclass 16, count 0 2006.285.19:11:05.72#ibcon#flushed, iclass 16, count 0 2006.285.19:11:05.72#ibcon#about to write, iclass 16, count 0 2006.285.19:11:05.72#ibcon#wrote, iclass 16, count 0 2006.285.19:11:05.72#ibcon#about to read 3, iclass 16, count 0 2006.285.19:11:05.74#ibcon#read 3, iclass 16, count 0 2006.285.19:11:05.74#ibcon#about to read 4, iclass 16, count 0 2006.285.19:11:05.74#ibcon#read 4, iclass 16, count 0 2006.285.19:11:05.74#ibcon#about to read 5, iclass 16, count 0 2006.285.19:11:05.74#ibcon#read 5, iclass 16, count 0 2006.285.19:11:05.74#ibcon#about to read 6, iclass 16, count 0 2006.285.19:11:05.74#ibcon#read 6, iclass 16, count 0 2006.285.19:11:05.74#ibcon#end of sib2, iclass 16, count 0 2006.285.19:11:05.74#ibcon#*mode == 0, iclass 16, count 0 2006.285.19:11:05.74#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.19:11:05.74#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.19:11:05.74#ibcon#*before write, iclass 16, count 0 2006.285.19:11:05.74#ibcon#enter sib2, iclass 16, count 0 2006.285.19:11:05.74#ibcon#flushed, iclass 16, count 0 2006.285.19:11:05.74#ibcon#about to write, iclass 16, count 0 2006.285.19:11:05.74#ibcon#wrote, iclass 16, count 0 2006.285.19:11:05.74#ibcon#about to read 3, iclass 16, count 0 2006.285.19:11:05.78#ibcon#read 3, iclass 16, count 0 2006.285.19:11:05.78#ibcon#about to read 4, iclass 16, count 0 2006.285.19:11:05.78#ibcon#read 4, iclass 16, count 0 2006.285.19:11:05.78#ibcon#about to read 5, iclass 16, count 0 2006.285.19:11:05.78#ibcon#read 5, iclass 16, count 0 2006.285.19:11:05.78#ibcon#about to read 6, iclass 16, count 0 2006.285.19:11:05.78#ibcon#read 6, iclass 16, count 0 2006.285.19:11:05.78#ibcon#end of sib2, iclass 16, count 0 2006.285.19:11:05.78#ibcon#*after write, iclass 16, count 0 2006.285.19:11:05.78#ibcon#*before return 0, iclass 16, count 0 2006.285.19:11:05.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:11:05.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:11:05.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.19:11:05.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.19:11:05.78$vck44/vb=4,5 2006.285.19:11:05.78#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.19:11:05.78#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.19:11:05.78#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:05.78#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:11:05.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:11:05.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:11:05.84#ibcon#enter wrdev, iclass 18, count 2 2006.285.19:11:05.84#ibcon#first serial, iclass 18, count 2 2006.285.19:11:05.84#ibcon#enter sib2, iclass 18, count 2 2006.285.19:11:05.84#ibcon#flushed, iclass 18, count 2 2006.285.19:11:05.84#ibcon#about to write, iclass 18, count 2 2006.285.19:11:05.84#ibcon#wrote, iclass 18, count 2 2006.285.19:11:05.84#ibcon#about to read 3, iclass 18, count 2 2006.285.19:11:05.86#ibcon#read 3, iclass 18, count 2 2006.285.19:11:05.86#ibcon#about to read 4, iclass 18, count 2 2006.285.19:11:05.86#ibcon#read 4, iclass 18, count 2 2006.285.19:11:05.86#ibcon#about to read 5, iclass 18, count 2 2006.285.19:11:05.86#ibcon#read 5, iclass 18, count 2 2006.285.19:11:05.86#ibcon#about to read 6, iclass 18, count 2 2006.285.19:11:05.86#ibcon#read 6, iclass 18, count 2 2006.285.19:11:05.86#ibcon#end of sib2, iclass 18, count 2 2006.285.19:11:05.86#ibcon#*mode == 0, iclass 18, count 2 2006.285.19:11:05.86#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.19:11:05.86#ibcon#[27=AT04-05\r\n] 2006.285.19:11:05.86#ibcon#*before write, iclass 18, count 2 2006.285.19:11:05.86#ibcon#enter sib2, iclass 18, count 2 2006.285.19:11:05.86#ibcon#flushed, iclass 18, count 2 2006.285.19:11:05.86#ibcon#about to write, iclass 18, count 2 2006.285.19:11:05.86#ibcon#wrote, iclass 18, count 2 2006.285.19:11:05.86#ibcon#about to read 3, iclass 18, count 2 2006.285.19:11:05.89#ibcon#read 3, iclass 18, count 2 2006.285.19:11:05.89#ibcon#about to read 4, iclass 18, count 2 2006.285.19:11:05.89#ibcon#read 4, iclass 18, count 2 2006.285.19:11:05.89#ibcon#about to read 5, iclass 18, count 2 2006.285.19:11:05.89#ibcon#read 5, iclass 18, count 2 2006.285.19:11:05.89#ibcon#about to read 6, iclass 18, count 2 2006.285.19:11:05.89#ibcon#read 6, iclass 18, count 2 2006.285.19:11:05.89#ibcon#end of sib2, iclass 18, count 2 2006.285.19:11:05.89#ibcon#*after write, iclass 18, count 2 2006.285.19:11:05.89#ibcon#*before return 0, iclass 18, count 2 2006.285.19:11:05.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:11:05.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:11:05.89#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.19:11:05.89#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:05.89#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:11:06.01#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:11:06.01#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:11:06.01#ibcon#enter wrdev, iclass 18, count 0 2006.285.19:11:06.01#ibcon#first serial, iclass 18, count 0 2006.285.19:11:06.01#ibcon#enter sib2, iclass 18, count 0 2006.285.19:11:06.01#ibcon#flushed, iclass 18, count 0 2006.285.19:11:06.01#ibcon#about to write, iclass 18, count 0 2006.285.19:11:06.01#ibcon#wrote, iclass 18, count 0 2006.285.19:11:06.01#ibcon#about to read 3, iclass 18, count 0 2006.285.19:11:06.03#ibcon#read 3, iclass 18, count 0 2006.285.19:11:06.03#ibcon#about to read 4, iclass 18, count 0 2006.285.19:11:06.03#ibcon#read 4, iclass 18, count 0 2006.285.19:11:06.03#ibcon#about to read 5, iclass 18, count 0 2006.285.19:11:06.03#ibcon#read 5, iclass 18, count 0 2006.285.19:11:06.03#ibcon#about to read 6, iclass 18, count 0 2006.285.19:11:06.03#ibcon#read 6, iclass 18, count 0 2006.285.19:11:06.03#ibcon#end of sib2, iclass 18, count 0 2006.285.19:11:06.03#ibcon#*mode == 0, iclass 18, count 0 2006.285.19:11:06.03#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.19:11:06.03#ibcon#[27=USB\r\n] 2006.285.19:11:06.03#ibcon#*before write, iclass 18, count 0 2006.285.19:11:06.03#ibcon#enter sib2, iclass 18, count 0 2006.285.19:11:06.03#ibcon#flushed, iclass 18, count 0 2006.285.19:11:06.03#ibcon#about to write, iclass 18, count 0 2006.285.19:11:06.03#ibcon#wrote, iclass 18, count 0 2006.285.19:11:06.03#ibcon#about to read 3, iclass 18, count 0 2006.285.19:11:06.06#ibcon#read 3, iclass 18, count 0 2006.285.19:11:06.06#ibcon#about to read 4, iclass 18, count 0 2006.285.19:11:06.06#ibcon#read 4, iclass 18, count 0 2006.285.19:11:06.06#ibcon#about to read 5, iclass 18, count 0 2006.285.19:11:06.06#ibcon#read 5, iclass 18, count 0 2006.285.19:11:06.06#ibcon#about to read 6, iclass 18, count 0 2006.285.19:11:06.06#ibcon#read 6, iclass 18, count 0 2006.285.19:11:06.06#ibcon#end of sib2, iclass 18, count 0 2006.285.19:11:06.06#ibcon#*after write, iclass 18, count 0 2006.285.19:11:06.06#ibcon#*before return 0, iclass 18, count 0 2006.285.19:11:06.06#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:11:06.06#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:11:06.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.19:11:06.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.19:11:06.06$vck44/vblo=5,709.99 2006.285.19:11:06.06#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.19:11:06.06#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.19:11:06.06#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:06.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:11:06.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:11:06.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:11:06.06#ibcon#enter wrdev, iclass 20, count 0 2006.285.19:11:06.06#ibcon#first serial, iclass 20, count 0 2006.285.19:11:06.06#ibcon#enter sib2, iclass 20, count 0 2006.285.19:11:06.06#ibcon#flushed, iclass 20, count 0 2006.285.19:11:06.06#ibcon#about to write, iclass 20, count 0 2006.285.19:11:06.06#ibcon#wrote, iclass 20, count 0 2006.285.19:11:06.06#ibcon#about to read 3, iclass 20, count 0 2006.285.19:11:06.08#ibcon#read 3, iclass 20, count 0 2006.285.19:11:06.15#ibcon#about to read 4, iclass 20, count 0 2006.285.19:11:06.15#ibcon#read 4, iclass 20, count 0 2006.285.19:11:06.15#ibcon#about to read 5, iclass 20, count 0 2006.285.19:11:06.15#ibcon#read 5, iclass 20, count 0 2006.285.19:11:06.15#ibcon#about to read 6, iclass 20, count 0 2006.285.19:11:06.15#ibcon#read 6, iclass 20, count 0 2006.285.19:11:06.15#ibcon#end of sib2, iclass 20, count 0 2006.285.19:11:06.15#ibcon#*mode == 0, iclass 20, count 0 2006.285.19:11:06.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.19:11:06.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.19:11:06.15#ibcon#*before write, iclass 20, count 0 2006.285.19:11:06.15#ibcon#enter sib2, iclass 20, count 0 2006.285.19:11:06.15#ibcon#flushed, iclass 20, count 0 2006.285.19:11:06.15#ibcon#about to write, iclass 20, count 0 2006.285.19:11:06.15#ibcon#wrote, iclass 20, count 0 2006.285.19:11:06.15#ibcon#about to read 3, iclass 20, count 0 2006.285.19:11:06.19#ibcon#read 3, iclass 20, count 0 2006.285.19:11:06.19#ibcon#about to read 4, iclass 20, count 0 2006.285.19:11:06.19#ibcon#read 4, iclass 20, count 0 2006.285.19:11:06.19#ibcon#about to read 5, iclass 20, count 0 2006.285.19:11:06.19#ibcon#read 5, iclass 20, count 0 2006.285.19:11:06.19#ibcon#about to read 6, iclass 20, count 0 2006.285.19:11:06.19#ibcon#read 6, iclass 20, count 0 2006.285.19:11:06.19#ibcon#end of sib2, iclass 20, count 0 2006.285.19:11:06.19#ibcon#*after write, iclass 20, count 0 2006.285.19:11:06.19#ibcon#*before return 0, iclass 20, count 0 2006.285.19:11:06.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:11:06.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:11:06.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.19:11:06.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.19:11:06.19$vck44/vb=5,4 2006.285.19:11:06.19#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.19:11:06.19#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.19:11:06.19#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:06.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:11:06.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:11:06.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:11:06.19#ibcon#enter wrdev, iclass 22, count 2 2006.285.19:11:06.19#ibcon#first serial, iclass 22, count 2 2006.285.19:11:06.19#ibcon#enter sib2, iclass 22, count 2 2006.285.19:11:06.19#ibcon#flushed, iclass 22, count 2 2006.285.19:11:06.19#ibcon#about to write, iclass 22, count 2 2006.285.19:11:06.19#ibcon#wrote, iclass 22, count 2 2006.285.19:11:06.19#ibcon#about to read 3, iclass 22, count 2 2006.285.19:11:06.21#ibcon#read 3, iclass 22, count 2 2006.285.19:11:06.21#ibcon#about to read 4, iclass 22, count 2 2006.285.19:11:06.21#ibcon#read 4, iclass 22, count 2 2006.285.19:11:06.21#ibcon#about to read 5, iclass 22, count 2 2006.285.19:11:06.21#ibcon#read 5, iclass 22, count 2 2006.285.19:11:06.21#ibcon#about to read 6, iclass 22, count 2 2006.285.19:11:06.21#ibcon#read 6, iclass 22, count 2 2006.285.19:11:06.21#ibcon#end of sib2, iclass 22, count 2 2006.285.19:11:06.21#ibcon#*mode == 0, iclass 22, count 2 2006.285.19:11:06.21#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.19:11:06.21#ibcon#[27=AT05-04\r\n] 2006.285.19:11:06.21#ibcon#*before write, iclass 22, count 2 2006.285.19:11:06.21#ibcon#enter sib2, iclass 22, count 2 2006.285.19:11:06.21#ibcon#flushed, iclass 22, count 2 2006.285.19:11:06.21#ibcon#about to write, iclass 22, count 2 2006.285.19:11:06.21#ibcon#wrote, iclass 22, count 2 2006.285.19:11:06.21#ibcon#about to read 3, iclass 22, count 2 2006.285.19:11:06.24#ibcon#read 3, iclass 22, count 2 2006.285.19:11:06.24#ibcon#about to read 4, iclass 22, count 2 2006.285.19:11:06.24#ibcon#read 4, iclass 22, count 2 2006.285.19:11:06.24#ibcon#about to read 5, iclass 22, count 2 2006.285.19:11:06.24#ibcon#read 5, iclass 22, count 2 2006.285.19:11:06.24#ibcon#about to read 6, iclass 22, count 2 2006.285.19:11:06.24#ibcon#read 6, iclass 22, count 2 2006.285.19:11:06.24#ibcon#end of sib2, iclass 22, count 2 2006.285.19:11:06.24#ibcon#*after write, iclass 22, count 2 2006.285.19:11:06.24#ibcon#*before return 0, iclass 22, count 2 2006.285.19:11:06.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:11:06.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:11:06.24#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.19:11:06.24#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:06.24#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:11:06.36#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:11:06.36#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:11:06.36#ibcon#enter wrdev, iclass 22, count 0 2006.285.19:11:06.36#ibcon#first serial, iclass 22, count 0 2006.285.19:11:06.36#ibcon#enter sib2, iclass 22, count 0 2006.285.19:11:06.36#ibcon#flushed, iclass 22, count 0 2006.285.19:11:06.36#ibcon#about to write, iclass 22, count 0 2006.285.19:11:06.36#ibcon#wrote, iclass 22, count 0 2006.285.19:11:06.36#ibcon#about to read 3, iclass 22, count 0 2006.285.19:11:06.38#ibcon#read 3, iclass 22, count 0 2006.285.19:11:06.38#ibcon#about to read 4, iclass 22, count 0 2006.285.19:11:06.38#ibcon#read 4, iclass 22, count 0 2006.285.19:11:06.38#ibcon#about to read 5, iclass 22, count 0 2006.285.19:11:06.38#ibcon#read 5, iclass 22, count 0 2006.285.19:11:06.38#ibcon#about to read 6, iclass 22, count 0 2006.285.19:11:06.38#ibcon#read 6, iclass 22, count 0 2006.285.19:11:06.38#ibcon#end of sib2, iclass 22, count 0 2006.285.19:11:06.38#ibcon#*mode == 0, iclass 22, count 0 2006.285.19:11:06.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.19:11:06.38#ibcon#[27=USB\r\n] 2006.285.19:11:06.38#ibcon#*before write, iclass 22, count 0 2006.285.19:11:06.38#ibcon#enter sib2, iclass 22, count 0 2006.285.19:11:06.38#ibcon#flushed, iclass 22, count 0 2006.285.19:11:06.38#ibcon#about to write, iclass 22, count 0 2006.285.19:11:06.38#ibcon#wrote, iclass 22, count 0 2006.285.19:11:06.38#ibcon#about to read 3, iclass 22, count 0 2006.285.19:11:06.41#ibcon#read 3, iclass 22, count 0 2006.285.19:11:06.41#ibcon#about to read 4, iclass 22, count 0 2006.285.19:11:06.41#ibcon#read 4, iclass 22, count 0 2006.285.19:11:06.41#ibcon#about to read 5, iclass 22, count 0 2006.285.19:11:06.41#ibcon#read 5, iclass 22, count 0 2006.285.19:11:06.41#ibcon#about to read 6, iclass 22, count 0 2006.285.19:11:06.41#ibcon#read 6, iclass 22, count 0 2006.285.19:11:06.41#ibcon#end of sib2, iclass 22, count 0 2006.285.19:11:06.41#ibcon#*after write, iclass 22, count 0 2006.285.19:11:06.41#ibcon#*before return 0, iclass 22, count 0 2006.285.19:11:06.41#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:11:06.41#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:11:06.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.19:11:06.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.19:11:06.41$vck44/vblo=6,719.99 2006.285.19:11:06.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.19:11:06.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.19:11:06.41#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:06.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:11:06.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:11:06.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:11:06.41#ibcon#enter wrdev, iclass 24, count 0 2006.285.19:11:06.41#ibcon#first serial, iclass 24, count 0 2006.285.19:11:06.41#ibcon#enter sib2, iclass 24, count 0 2006.285.19:11:06.41#ibcon#flushed, iclass 24, count 0 2006.285.19:11:06.41#ibcon#about to write, iclass 24, count 0 2006.285.19:11:06.41#ibcon#wrote, iclass 24, count 0 2006.285.19:11:06.41#ibcon#about to read 3, iclass 24, count 0 2006.285.19:11:06.43#ibcon#read 3, iclass 24, count 0 2006.285.19:11:06.43#ibcon#about to read 4, iclass 24, count 0 2006.285.19:11:06.43#ibcon#read 4, iclass 24, count 0 2006.285.19:11:06.43#ibcon#about to read 5, iclass 24, count 0 2006.285.19:11:06.43#ibcon#read 5, iclass 24, count 0 2006.285.19:11:06.43#ibcon#about to read 6, iclass 24, count 0 2006.285.19:11:06.43#ibcon#read 6, iclass 24, count 0 2006.285.19:11:06.43#ibcon#end of sib2, iclass 24, count 0 2006.285.19:11:06.43#ibcon#*mode == 0, iclass 24, count 0 2006.285.19:11:06.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.19:11:06.43#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.19:11:06.43#ibcon#*before write, iclass 24, count 0 2006.285.19:11:06.43#ibcon#enter sib2, iclass 24, count 0 2006.285.19:11:06.43#ibcon#flushed, iclass 24, count 0 2006.285.19:11:06.43#ibcon#about to write, iclass 24, count 0 2006.285.19:11:06.43#ibcon#wrote, iclass 24, count 0 2006.285.19:11:06.43#ibcon#about to read 3, iclass 24, count 0 2006.285.19:11:06.47#ibcon#read 3, iclass 24, count 0 2006.285.19:11:06.47#ibcon#about to read 4, iclass 24, count 0 2006.285.19:11:06.47#ibcon#read 4, iclass 24, count 0 2006.285.19:11:06.47#ibcon#about to read 5, iclass 24, count 0 2006.285.19:11:06.47#ibcon#read 5, iclass 24, count 0 2006.285.19:11:06.47#ibcon#about to read 6, iclass 24, count 0 2006.285.19:11:06.47#ibcon#read 6, iclass 24, count 0 2006.285.19:11:06.47#ibcon#end of sib2, iclass 24, count 0 2006.285.19:11:06.47#ibcon#*after write, iclass 24, count 0 2006.285.19:11:06.47#ibcon#*before return 0, iclass 24, count 0 2006.285.19:11:06.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:11:06.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:11:06.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.19:11:06.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.19:11:06.47$vck44/vb=6,3 2006.285.19:11:06.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.19:11:06.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.19:11:06.47#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:06.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:11:06.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:11:06.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:11:06.53#ibcon#enter wrdev, iclass 26, count 2 2006.285.19:11:06.53#ibcon#first serial, iclass 26, count 2 2006.285.19:11:06.53#ibcon#enter sib2, iclass 26, count 2 2006.285.19:11:06.53#ibcon#flushed, iclass 26, count 2 2006.285.19:11:06.53#ibcon#about to write, iclass 26, count 2 2006.285.19:11:06.53#ibcon#wrote, iclass 26, count 2 2006.285.19:11:06.53#ibcon#about to read 3, iclass 26, count 2 2006.285.19:11:06.55#ibcon#read 3, iclass 26, count 2 2006.285.19:11:06.55#ibcon#about to read 4, iclass 26, count 2 2006.285.19:11:06.55#ibcon#read 4, iclass 26, count 2 2006.285.19:11:06.55#ibcon#about to read 5, iclass 26, count 2 2006.285.19:11:06.55#ibcon#read 5, iclass 26, count 2 2006.285.19:11:06.55#ibcon#about to read 6, iclass 26, count 2 2006.285.19:11:06.55#ibcon#read 6, iclass 26, count 2 2006.285.19:11:06.55#ibcon#end of sib2, iclass 26, count 2 2006.285.19:11:06.55#ibcon#*mode == 0, iclass 26, count 2 2006.285.19:11:06.55#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.19:11:06.55#ibcon#[27=AT06-03\r\n] 2006.285.19:11:06.55#ibcon#*before write, iclass 26, count 2 2006.285.19:11:06.55#ibcon#enter sib2, iclass 26, count 2 2006.285.19:11:06.55#ibcon#flushed, iclass 26, count 2 2006.285.19:11:06.55#ibcon#about to write, iclass 26, count 2 2006.285.19:11:06.55#ibcon#wrote, iclass 26, count 2 2006.285.19:11:06.55#ibcon#about to read 3, iclass 26, count 2 2006.285.19:11:06.58#ibcon#read 3, iclass 26, count 2 2006.285.19:11:06.58#ibcon#about to read 4, iclass 26, count 2 2006.285.19:11:06.58#ibcon#read 4, iclass 26, count 2 2006.285.19:11:06.58#ibcon#about to read 5, iclass 26, count 2 2006.285.19:11:06.58#ibcon#read 5, iclass 26, count 2 2006.285.19:11:06.58#ibcon#about to read 6, iclass 26, count 2 2006.285.19:11:06.58#ibcon#read 6, iclass 26, count 2 2006.285.19:11:06.58#ibcon#end of sib2, iclass 26, count 2 2006.285.19:11:06.58#ibcon#*after write, iclass 26, count 2 2006.285.19:11:06.58#ibcon#*before return 0, iclass 26, count 2 2006.285.19:11:06.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:11:06.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:11:06.58#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.19:11:06.58#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:06.58#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:11:06.70#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:11:06.70#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:11:06.70#ibcon#enter wrdev, iclass 26, count 0 2006.285.19:11:06.70#ibcon#first serial, iclass 26, count 0 2006.285.19:11:06.70#ibcon#enter sib2, iclass 26, count 0 2006.285.19:11:06.70#ibcon#flushed, iclass 26, count 0 2006.285.19:11:06.70#ibcon#about to write, iclass 26, count 0 2006.285.19:11:06.70#ibcon#wrote, iclass 26, count 0 2006.285.19:11:06.70#ibcon#about to read 3, iclass 26, count 0 2006.285.19:11:06.72#ibcon#read 3, iclass 26, count 0 2006.285.19:11:06.72#ibcon#about to read 4, iclass 26, count 0 2006.285.19:11:06.72#ibcon#read 4, iclass 26, count 0 2006.285.19:11:06.72#ibcon#about to read 5, iclass 26, count 0 2006.285.19:11:06.72#ibcon#read 5, iclass 26, count 0 2006.285.19:11:06.72#ibcon#about to read 6, iclass 26, count 0 2006.285.19:11:06.72#ibcon#read 6, iclass 26, count 0 2006.285.19:11:06.72#ibcon#end of sib2, iclass 26, count 0 2006.285.19:11:06.72#ibcon#*mode == 0, iclass 26, count 0 2006.285.19:11:06.72#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.19:11:06.72#ibcon#[27=USB\r\n] 2006.285.19:11:06.72#ibcon#*before write, iclass 26, count 0 2006.285.19:11:06.72#ibcon#enter sib2, iclass 26, count 0 2006.285.19:11:06.72#ibcon#flushed, iclass 26, count 0 2006.285.19:11:06.72#ibcon#about to write, iclass 26, count 0 2006.285.19:11:06.72#ibcon#wrote, iclass 26, count 0 2006.285.19:11:06.72#ibcon#about to read 3, iclass 26, count 0 2006.285.19:11:06.75#ibcon#read 3, iclass 26, count 0 2006.285.19:11:06.75#ibcon#about to read 4, iclass 26, count 0 2006.285.19:11:06.75#ibcon#read 4, iclass 26, count 0 2006.285.19:11:06.75#ibcon#about to read 5, iclass 26, count 0 2006.285.19:11:06.75#ibcon#read 5, iclass 26, count 0 2006.285.19:11:06.75#ibcon#about to read 6, iclass 26, count 0 2006.285.19:11:06.75#ibcon#read 6, iclass 26, count 0 2006.285.19:11:06.75#ibcon#end of sib2, iclass 26, count 0 2006.285.19:11:06.75#ibcon#*after write, iclass 26, count 0 2006.285.19:11:06.75#ibcon#*before return 0, iclass 26, count 0 2006.285.19:11:06.75#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:11:06.75#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:11:06.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.19:11:06.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.19:11:06.75$vck44/vblo=7,734.99 2006.285.19:11:06.75#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.19:11:06.75#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.19:11:06.75#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:06.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:11:06.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:11:06.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:11:06.75#ibcon#enter wrdev, iclass 28, count 0 2006.285.19:11:06.75#ibcon#first serial, iclass 28, count 0 2006.285.19:11:06.75#ibcon#enter sib2, iclass 28, count 0 2006.285.19:11:06.75#ibcon#flushed, iclass 28, count 0 2006.285.19:11:06.75#ibcon#about to write, iclass 28, count 0 2006.285.19:11:06.75#ibcon#wrote, iclass 28, count 0 2006.285.19:11:06.75#ibcon#about to read 3, iclass 28, count 0 2006.285.19:11:06.77#ibcon#read 3, iclass 28, count 0 2006.285.19:11:06.77#ibcon#about to read 4, iclass 28, count 0 2006.285.19:11:06.77#ibcon#read 4, iclass 28, count 0 2006.285.19:11:06.77#ibcon#about to read 5, iclass 28, count 0 2006.285.19:11:06.77#ibcon#read 5, iclass 28, count 0 2006.285.19:11:06.77#ibcon#about to read 6, iclass 28, count 0 2006.285.19:11:06.77#ibcon#read 6, iclass 28, count 0 2006.285.19:11:06.77#ibcon#end of sib2, iclass 28, count 0 2006.285.19:11:06.77#ibcon#*mode == 0, iclass 28, count 0 2006.285.19:11:06.77#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.19:11:06.77#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.19:11:06.77#ibcon#*before write, iclass 28, count 0 2006.285.19:11:06.77#ibcon#enter sib2, iclass 28, count 0 2006.285.19:11:06.77#ibcon#flushed, iclass 28, count 0 2006.285.19:11:06.77#ibcon#about to write, iclass 28, count 0 2006.285.19:11:06.77#ibcon#wrote, iclass 28, count 0 2006.285.19:11:06.77#ibcon#about to read 3, iclass 28, count 0 2006.285.19:11:06.81#ibcon#read 3, iclass 28, count 0 2006.285.19:11:06.81#ibcon#about to read 4, iclass 28, count 0 2006.285.19:11:06.81#ibcon#read 4, iclass 28, count 0 2006.285.19:11:06.81#ibcon#about to read 5, iclass 28, count 0 2006.285.19:11:06.81#ibcon#read 5, iclass 28, count 0 2006.285.19:11:06.81#ibcon#about to read 6, iclass 28, count 0 2006.285.19:11:06.81#ibcon#read 6, iclass 28, count 0 2006.285.19:11:06.81#ibcon#end of sib2, iclass 28, count 0 2006.285.19:11:06.81#ibcon#*after write, iclass 28, count 0 2006.285.19:11:06.81#ibcon#*before return 0, iclass 28, count 0 2006.285.19:11:06.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:11:06.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:11:06.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.19:11:06.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.19:11:06.81$vck44/vb=7,4 2006.285.19:11:06.81#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.19:11:06.81#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.19:11:06.81#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:06.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:11:06.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:11:06.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:11:06.87#ibcon#enter wrdev, iclass 30, count 2 2006.285.19:11:06.87#ibcon#first serial, iclass 30, count 2 2006.285.19:11:06.87#ibcon#enter sib2, iclass 30, count 2 2006.285.19:11:06.87#ibcon#flushed, iclass 30, count 2 2006.285.19:11:06.87#ibcon#about to write, iclass 30, count 2 2006.285.19:11:06.87#ibcon#wrote, iclass 30, count 2 2006.285.19:11:06.87#ibcon#about to read 3, iclass 30, count 2 2006.285.19:11:06.89#ibcon#read 3, iclass 30, count 2 2006.285.19:11:06.89#ibcon#about to read 4, iclass 30, count 2 2006.285.19:11:06.89#ibcon#read 4, iclass 30, count 2 2006.285.19:11:06.89#ibcon#about to read 5, iclass 30, count 2 2006.285.19:11:06.89#ibcon#read 5, iclass 30, count 2 2006.285.19:11:06.89#ibcon#about to read 6, iclass 30, count 2 2006.285.19:11:06.89#ibcon#read 6, iclass 30, count 2 2006.285.19:11:06.89#ibcon#end of sib2, iclass 30, count 2 2006.285.19:11:06.89#ibcon#*mode == 0, iclass 30, count 2 2006.285.19:11:06.89#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.19:11:06.89#ibcon#[27=AT07-04\r\n] 2006.285.19:11:06.89#ibcon#*before write, iclass 30, count 2 2006.285.19:11:06.89#ibcon#enter sib2, iclass 30, count 2 2006.285.19:11:06.89#ibcon#flushed, iclass 30, count 2 2006.285.19:11:06.89#ibcon#about to write, iclass 30, count 2 2006.285.19:11:06.89#ibcon#wrote, iclass 30, count 2 2006.285.19:11:06.89#ibcon#about to read 3, iclass 30, count 2 2006.285.19:11:06.92#ibcon#read 3, iclass 30, count 2 2006.285.19:11:06.92#ibcon#about to read 4, iclass 30, count 2 2006.285.19:11:06.92#ibcon#read 4, iclass 30, count 2 2006.285.19:11:06.92#ibcon#about to read 5, iclass 30, count 2 2006.285.19:11:06.92#ibcon#read 5, iclass 30, count 2 2006.285.19:11:06.92#ibcon#about to read 6, iclass 30, count 2 2006.285.19:11:06.92#ibcon#read 6, iclass 30, count 2 2006.285.19:11:06.92#ibcon#end of sib2, iclass 30, count 2 2006.285.19:11:06.92#ibcon#*after write, iclass 30, count 2 2006.285.19:11:06.92#ibcon#*before return 0, iclass 30, count 2 2006.285.19:11:06.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:11:06.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:11:06.92#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.19:11:06.92#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:06.92#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:11:07.04#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:11:07.04#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:11:07.04#ibcon#enter wrdev, iclass 30, count 0 2006.285.19:11:07.04#ibcon#first serial, iclass 30, count 0 2006.285.19:11:07.04#ibcon#enter sib2, iclass 30, count 0 2006.285.19:11:07.04#ibcon#flushed, iclass 30, count 0 2006.285.19:11:07.04#ibcon#about to write, iclass 30, count 0 2006.285.19:11:07.04#ibcon#wrote, iclass 30, count 0 2006.285.19:11:07.04#ibcon#about to read 3, iclass 30, count 0 2006.285.19:11:07.06#ibcon#read 3, iclass 30, count 0 2006.285.19:11:07.06#ibcon#about to read 4, iclass 30, count 0 2006.285.19:11:07.06#ibcon#read 4, iclass 30, count 0 2006.285.19:11:07.06#ibcon#about to read 5, iclass 30, count 0 2006.285.19:11:07.06#ibcon#read 5, iclass 30, count 0 2006.285.19:11:07.06#ibcon#about to read 6, iclass 30, count 0 2006.285.19:11:07.06#ibcon#read 6, iclass 30, count 0 2006.285.19:11:07.06#ibcon#end of sib2, iclass 30, count 0 2006.285.19:11:07.06#ibcon#*mode == 0, iclass 30, count 0 2006.285.19:11:07.06#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.19:11:07.06#ibcon#[27=USB\r\n] 2006.285.19:11:07.06#ibcon#*before write, iclass 30, count 0 2006.285.19:11:07.06#ibcon#enter sib2, iclass 30, count 0 2006.285.19:11:07.06#ibcon#flushed, iclass 30, count 0 2006.285.19:11:07.06#ibcon#about to write, iclass 30, count 0 2006.285.19:11:07.06#ibcon#wrote, iclass 30, count 0 2006.285.19:11:07.06#ibcon#about to read 3, iclass 30, count 0 2006.285.19:11:07.09#ibcon#read 3, iclass 30, count 0 2006.285.19:11:07.09#ibcon#about to read 4, iclass 30, count 0 2006.285.19:11:07.09#ibcon#read 4, iclass 30, count 0 2006.285.19:11:07.09#ibcon#about to read 5, iclass 30, count 0 2006.285.19:11:07.09#ibcon#read 5, iclass 30, count 0 2006.285.19:11:07.09#ibcon#about to read 6, iclass 30, count 0 2006.285.19:11:07.09#ibcon#read 6, iclass 30, count 0 2006.285.19:11:07.09#ibcon#end of sib2, iclass 30, count 0 2006.285.19:11:07.09#ibcon#*after write, iclass 30, count 0 2006.285.19:11:07.09#ibcon#*before return 0, iclass 30, count 0 2006.285.19:11:07.09#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:11:07.09#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:11:07.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.19:11:07.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.19:11:07.09$vck44/vblo=8,744.99 2006.285.19:11:07.09#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.19:11:07.09#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.19:11:07.09#ibcon#ireg 17 cls_cnt 0 2006.285.19:11:07.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:11:07.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:11:07.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:11:07.09#ibcon#enter wrdev, iclass 32, count 0 2006.285.19:11:07.09#ibcon#first serial, iclass 32, count 0 2006.285.19:11:07.09#ibcon#enter sib2, iclass 32, count 0 2006.285.19:11:07.09#ibcon#flushed, iclass 32, count 0 2006.285.19:11:07.09#ibcon#about to write, iclass 32, count 0 2006.285.19:11:07.09#ibcon#wrote, iclass 32, count 0 2006.285.19:11:07.09#ibcon#about to read 3, iclass 32, count 0 2006.285.19:11:07.11#ibcon#read 3, iclass 32, count 0 2006.285.19:11:07.15#ibcon#about to read 4, iclass 32, count 0 2006.285.19:11:07.15#ibcon#read 4, iclass 32, count 0 2006.285.19:11:07.15#ibcon#about to read 5, iclass 32, count 0 2006.285.19:11:07.15#ibcon#read 5, iclass 32, count 0 2006.285.19:11:07.15#ibcon#about to read 6, iclass 32, count 0 2006.285.19:11:07.15#ibcon#read 6, iclass 32, count 0 2006.285.19:11:07.15#ibcon#end of sib2, iclass 32, count 0 2006.285.19:11:07.15#ibcon#*mode == 0, iclass 32, count 0 2006.285.19:11:07.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.19:11:07.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.19:11:07.15#ibcon#*before write, iclass 32, count 0 2006.285.19:11:07.15#ibcon#enter sib2, iclass 32, count 0 2006.285.19:11:07.15#ibcon#flushed, iclass 32, count 0 2006.285.19:11:07.15#ibcon#about to write, iclass 32, count 0 2006.285.19:11:07.15#ibcon#wrote, iclass 32, count 0 2006.285.19:11:07.15#ibcon#about to read 3, iclass 32, count 0 2006.285.19:11:07.19#ibcon#read 3, iclass 32, count 0 2006.285.19:11:07.19#ibcon#about to read 4, iclass 32, count 0 2006.285.19:11:07.19#ibcon#read 4, iclass 32, count 0 2006.285.19:11:07.19#ibcon#about to read 5, iclass 32, count 0 2006.285.19:11:07.19#ibcon#read 5, iclass 32, count 0 2006.285.19:11:07.19#ibcon#about to read 6, iclass 32, count 0 2006.285.19:11:07.19#ibcon#read 6, iclass 32, count 0 2006.285.19:11:07.19#ibcon#end of sib2, iclass 32, count 0 2006.285.19:11:07.19#ibcon#*after write, iclass 32, count 0 2006.285.19:11:07.19#ibcon#*before return 0, iclass 32, count 0 2006.285.19:11:07.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:11:07.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:11:07.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.19:11:07.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.19:11:07.19$vck44/vb=8,4 2006.285.19:11:07.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.19:11:07.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.19:11:07.19#ibcon#ireg 11 cls_cnt 2 2006.285.19:11:07.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:11:07.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:11:07.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:11:07.21#ibcon#enter wrdev, iclass 34, count 2 2006.285.19:11:07.21#ibcon#first serial, iclass 34, count 2 2006.285.19:11:07.21#ibcon#enter sib2, iclass 34, count 2 2006.285.19:11:07.21#ibcon#flushed, iclass 34, count 2 2006.285.19:11:07.21#ibcon#about to write, iclass 34, count 2 2006.285.19:11:07.21#ibcon#wrote, iclass 34, count 2 2006.285.19:11:07.21#ibcon#about to read 3, iclass 34, count 2 2006.285.19:11:07.23#ibcon#read 3, iclass 34, count 2 2006.285.19:11:07.23#ibcon#about to read 4, iclass 34, count 2 2006.285.19:11:07.23#ibcon#read 4, iclass 34, count 2 2006.285.19:11:07.23#ibcon#about to read 5, iclass 34, count 2 2006.285.19:11:07.23#ibcon#read 5, iclass 34, count 2 2006.285.19:11:07.23#ibcon#about to read 6, iclass 34, count 2 2006.285.19:11:07.23#ibcon#read 6, iclass 34, count 2 2006.285.19:11:07.23#ibcon#end of sib2, iclass 34, count 2 2006.285.19:11:07.23#ibcon#*mode == 0, iclass 34, count 2 2006.285.19:11:07.23#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.19:11:07.23#ibcon#[27=AT08-04\r\n] 2006.285.19:11:07.23#ibcon#*before write, iclass 34, count 2 2006.285.19:11:07.23#ibcon#enter sib2, iclass 34, count 2 2006.285.19:11:07.23#ibcon#flushed, iclass 34, count 2 2006.285.19:11:07.23#ibcon#about to write, iclass 34, count 2 2006.285.19:11:07.23#ibcon#wrote, iclass 34, count 2 2006.285.19:11:07.23#ibcon#about to read 3, iclass 34, count 2 2006.285.19:11:07.26#ibcon#read 3, iclass 34, count 2 2006.285.19:11:07.26#ibcon#about to read 4, iclass 34, count 2 2006.285.19:11:07.26#ibcon#read 4, iclass 34, count 2 2006.285.19:11:07.26#ibcon#about to read 5, iclass 34, count 2 2006.285.19:11:07.26#ibcon#read 5, iclass 34, count 2 2006.285.19:11:07.26#ibcon#about to read 6, iclass 34, count 2 2006.285.19:11:07.26#ibcon#read 6, iclass 34, count 2 2006.285.19:11:07.26#ibcon#end of sib2, iclass 34, count 2 2006.285.19:11:07.26#ibcon#*after write, iclass 34, count 2 2006.285.19:11:07.26#ibcon#*before return 0, iclass 34, count 2 2006.285.19:11:07.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:11:07.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:11:07.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.19:11:07.26#ibcon#ireg 7 cls_cnt 0 2006.285.19:11:07.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:11:07.38#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:11:07.38#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:11:07.38#ibcon#enter wrdev, iclass 34, count 0 2006.285.19:11:07.38#ibcon#first serial, iclass 34, count 0 2006.285.19:11:07.38#ibcon#enter sib2, iclass 34, count 0 2006.285.19:11:07.38#ibcon#flushed, iclass 34, count 0 2006.285.19:11:07.38#ibcon#about to write, iclass 34, count 0 2006.285.19:11:07.38#ibcon#wrote, iclass 34, count 0 2006.285.19:11:07.38#ibcon#about to read 3, iclass 34, count 0 2006.285.19:11:07.40#ibcon#read 3, iclass 34, count 0 2006.285.19:11:07.40#ibcon#about to read 4, iclass 34, count 0 2006.285.19:11:07.40#ibcon#read 4, iclass 34, count 0 2006.285.19:11:07.40#ibcon#about to read 5, iclass 34, count 0 2006.285.19:11:07.40#ibcon#read 5, iclass 34, count 0 2006.285.19:11:07.40#ibcon#about to read 6, iclass 34, count 0 2006.285.19:11:07.40#ibcon#read 6, iclass 34, count 0 2006.285.19:11:07.40#ibcon#end of sib2, iclass 34, count 0 2006.285.19:11:07.40#ibcon#*mode == 0, iclass 34, count 0 2006.285.19:11:07.40#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.19:11:07.40#ibcon#[27=USB\r\n] 2006.285.19:11:07.40#ibcon#*before write, iclass 34, count 0 2006.285.19:11:07.40#ibcon#enter sib2, iclass 34, count 0 2006.285.19:11:07.40#ibcon#flushed, iclass 34, count 0 2006.285.19:11:07.40#ibcon#about to write, iclass 34, count 0 2006.285.19:11:07.40#ibcon#wrote, iclass 34, count 0 2006.285.19:11:07.40#ibcon#about to read 3, iclass 34, count 0 2006.285.19:11:07.43#ibcon#read 3, iclass 34, count 0 2006.285.19:11:07.43#ibcon#about to read 4, iclass 34, count 0 2006.285.19:11:07.43#ibcon#read 4, iclass 34, count 0 2006.285.19:11:07.43#ibcon#about to read 5, iclass 34, count 0 2006.285.19:11:07.43#ibcon#read 5, iclass 34, count 0 2006.285.19:11:07.43#ibcon#about to read 6, iclass 34, count 0 2006.285.19:11:07.43#ibcon#read 6, iclass 34, count 0 2006.285.19:11:07.43#ibcon#end of sib2, iclass 34, count 0 2006.285.19:11:07.43#ibcon#*after write, iclass 34, count 0 2006.285.19:11:07.43#ibcon#*before return 0, iclass 34, count 0 2006.285.19:11:07.43#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:11:07.43#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:11:07.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.19:11:07.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.19:11:07.43$vck44/vabw=wide 2006.285.19:11:07.43#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.19:11:07.43#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.19:11:07.43#ibcon#ireg 8 cls_cnt 0 2006.285.19:11:07.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:11:07.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:11:07.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:11:07.43#ibcon#enter wrdev, iclass 36, count 0 2006.285.19:11:07.43#ibcon#first serial, iclass 36, count 0 2006.285.19:11:07.43#ibcon#enter sib2, iclass 36, count 0 2006.285.19:11:07.43#ibcon#flushed, iclass 36, count 0 2006.285.19:11:07.43#ibcon#about to write, iclass 36, count 0 2006.285.19:11:07.43#ibcon#wrote, iclass 36, count 0 2006.285.19:11:07.43#ibcon#about to read 3, iclass 36, count 0 2006.285.19:11:07.45#ibcon#read 3, iclass 36, count 0 2006.285.19:11:07.45#ibcon#about to read 4, iclass 36, count 0 2006.285.19:11:07.45#ibcon#read 4, iclass 36, count 0 2006.285.19:11:07.45#ibcon#about to read 5, iclass 36, count 0 2006.285.19:11:07.45#ibcon#read 5, iclass 36, count 0 2006.285.19:11:07.45#ibcon#about to read 6, iclass 36, count 0 2006.285.19:11:07.45#ibcon#read 6, iclass 36, count 0 2006.285.19:11:07.45#ibcon#end of sib2, iclass 36, count 0 2006.285.19:11:07.45#ibcon#*mode == 0, iclass 36, count 0 2006.285.19:11:07.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.19:11:07.45#ibcon#[25=BW32\r\n] 2006.285.19:11:07.45#ibcon#*before write, iclass 36, count 0 2006.285.19:11:07.45#ibcon#enter sib2, iclass 36, count 0 2006.285.19:11:07.45#ibcon#flushed, iclass 36, count 0 2006.285.19:11:07.45#ibcon#about to write, iclass 36, count 0 2006.285.19:11:07.45#ibcon#wrote, iclass 36, count 0 2006.285.19:11:07.45#ibcon#about to read 3, iclass 36, count 0 2006.285.19:11:07.48#ibcon#read 3, iclass 36, count 0 2006.285.19:11:07.48#ibcon#about to read 4, iclass 36, count 0 2006.285.19:11:07.48#ibcon#read 4, iclass 36, count 0 2006.285.19:11:07.48#ibcon#about to read 5, iclass 36, count 0 2006.285.19:11:07.48#ibcon#read 5, iclass 36, count 0 2006.285.19:11:07.48#ibcon#about to read 6, iclass 36, count 0 2006.285.19:11:07.48#ibcon#read 6, iclass 36, count 0 2006.285.19:11:07.48#ibcon#end of sib2, iclass 36, count 0 2006.285.19:11:07.48#ibcon#*after write, iclass 36, count 0 2006.285.19:11:07.48#ibcon#*before return 0, iclass 36, count 0 2006.285.19:11:07.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:11:07.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:11:07.48#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.19:11:07.48#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.19:11:07.48$vck44/vbbw=wide 2006.285.19:11:07.48#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.19:11:07.48#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.19:11:07.48#ibcon#ireg 8 cls_cnt 0 2006.285.19:11:07.48#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:11:07.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:11:07.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:11:07.55#ibcon#enter wrdev, iclass 38, count 0 2006.285.19:11:07.55#ibcon#first serial, iclass 38, count 0 2006.285.19:11:07.55#ibcon#enter sib2, iclass 38, count 0 2006.285.19:11:07.55#ibcon#flushed, iclass 38, count 0 2006.285.19:11:07.55#ibcon#about to write, iclass 38, count 0 2006.285.19:11:07.55#ibcon#wrote, iclass 38, count 0 2006.285.19:11:07.55#ibcon#about to read 3, iclass 38, count 0 2006.285.19:11:07.57#ibcon#read 3, iclass 38, count 0 2006.285.19:11:07.57#ibcon#about to read 4, iclass 38, count 0 2006.285.19:11:07.57#ibcon#read 4, iclass 38, count 0 2006.285.19:11:07.57#ibcon#about to read 5, iclass 38, count 0 2006.285.19:11:07.57#ibcon#read 5, iclass 38, count 0 2006.285.19:11:07.57#ibcon#about to read 6, iclass 38, count 0 2006.285.19:11:07.57#ibcon#read 6, iclass 38, count 0 2006.285.19:11:07.57#ibcon#end of sib2, iclass 38, count 0 2006.285.19:11:07.57#ibcon#*mode == 0, iclass 38, count 0 2006.285.19:11:07.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.19:11:07.57#ibcon#[27=BW32\r\n] 2006.285.19:11:07.57#ibcon#*before write, iclass 38, count 0 2006.285.19:11:07.57#ibcon#enter sib2, iclass 38, count 0 2006.285.19:11:07.57#ibcon#flushed, iclass 38, count 0 2006.285.19:11:07.57#ibcon#about to write, iclass 38, count 0 2006.285.19:11:07.57#ibcon#wrote, iclass 38, count 0 2006.285.19:11:07.57#ibcon#about to read 3, iclass 38, count 0 2006.285.19:11:07.60#ibcon#read 3, iclass 38, count 0 2006.285.19:11:07.60#ibcon#about to read 4, iclass 38, count 0 2006.285.19:11:07.60#ibcon#read 4, iclass 38, count 0 2006.285.19:11:07.60#ibcon#about to read 5, iclass 38, count 0 2006.285.19:11:07.60#ibcon#read 5, iclass 38, count 0 2006.285.19:11:07.60#ibcon#about to read 6, iclass 38, count 0 2006.285.19:11:07.60#ibcon#read 6, iclass 38, count 0 2006.285.19:11:07.60#ibcon#end of sib2, iclass 38, count 0 2006.285.19:11:07.60#ibcon#*after write, iclass 38, count 0 2006.285.19:11:07.60#ibcon#*before return 0, iclass 38, count 0 2006.285.19:11:07.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:11:07.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:11:07.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.19:11:07.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.19:11:07.60$setupk4/ifdk4 2006.285.19:11:07.60$ifdk4/lo= 2006.285.19:11:07.60$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.19:11:07.60$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.19:11:07.60$ifdk4/patch= 2006.285.19:11:07.60$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.19:11:07.60$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.19:11:07.60$setupk4/!*+20s 2006.285.19:11:09.64#abcon#<5=/15 0.8 1.4 15.001001014.9\r\n> 2006.285.19:11:09.66#abcon#{5=INTERFACE CLEAR} 2006.285.19:11:09.72#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:11:17.14#trakl#Source acquired 2006.285.19:11:17.14#flagr#flagr/antenna,acquired 2006.285.19:11:19.81#abcon#<5=/15 0.8 1.3 15.001001014.9\r\n> 2006.285.19:11:19.83#abcon#{5=INTERFACE CLEAR} 2006.285.19:11:19.89#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:11:21.68$setupk4/"tpicd 2006.285.19:11:21.68$setupk4/echo=off 2006.285.19:11:21.68$setupk4/xlog=off 2006.285.19:11:21.68:!2006.285.19:12:47 2006.285.19:12:47.00:preob 2006.285.19:12:48.14/onsource/TRACKING 2006.285.19:12:48.14:!2006.285.19:12:57 2006.285.19:12:57.00:"tape 2006.285.19:12:57.00:"st=record 2006.285.19:12:57.00:data_valid=on 2006.285.19:12:57.00:midob 2006.285.19:12:57.14/onsource/TRACKING 2006.285.19:12:57.14/wx/15.01,1014.9,100 2006.285.19:12:57.26/cable/+6.5065E-03 2006.285.19:12:58.35/va/01,07,usb,yes,32,34 2006.285.19:12:58.35/va/02,06,usb,yes,32,32 2006.285.19:12:58.35/va/03,07,usb,yes,31,33 2006.285.19:12:58.35/va/04,06,usb,yes,33,34 2006.285.19:12:58.35/va/05,03,usb,yes,32,32 2006.285.19:12:58.35/va/06,04,usb,yes,29,28 2006.285.19:12:58.35/va/07,04,usb,yes,29,30 2006.285.19:12:58.35/va/08,03,usb,yes,30,37 2006.285.19:12:58.58/valo/01,524.99,yes,locked 2006.285.19:12:58.58/valo/02,534.99,yes,locked 2006.285.19:12:58.58/valo/03,564.99,yes,locked 2006.285.19:12:58.58/valo/04,624.99,yes,locked 2006.285.19:12:58.58/valo/05,734.99,yes,locked 2006.285.19:12:58.58/valo/06,814.99,yes,locked 2006.285.19:12:58.58/valo/07,864.99,yes,locked 2006.285.19:12:58.58/valo/08,884.99,yes,locked 2006.285.19:12:59.67/vb/01,04,usb,yes,30,28 2006.285.19:12:59.67/vb/02,05,usb,yes,28,28 2006.285.19:12:59.67/vb/03,04,usb,yes,29,32 2006.285.19:12:59.67/vb/04,05,usb,yes,29,28 2006.285.19:12:59.67/vb/05,04,usb,yes,26,28 2006.285.19:12:59.67/vb/06,03,usb,yes,37,33 2006.285.19:12:59.67/vb/07,04,usb,yes,30,30 2006.285.19:12:59.67/vb/08,04,usb,yes,27,30 2006.285.19:12:59.90/vblo/01,629.99,yes,locked 2006.285.19:12:59.90/vblo/02,634.99,yes,locked 2006.285.19:12:59.90/vblo/03,649.99,yes,locked 2006.285.19:12:59.90/vblo/04,679.99,yes,locked 2006.285.19:12:59.90/vblo/05,709.99,yes,locked 2006.285.19:12:59.90/vblo/06,719.99,yes,locked 2006.285.19:12:59.90/vblo/07,734.99,yes,locked 2006.285.19:12:59.90/vblo/08,744.99,yes,locked 2006.285.19:13:00.05/vabw/8 2006.285.19:13:00.20/vbbw/8 2006.285.19:13:00.29/xfe/off,on,12.0 2006.285.19:13:00.67/ifatt/23,28,28,28 2006.285.19:13:01.07/fmout-gps/S +2.66E-07 2006.285.19:13:01.09:!2006.285.19:14:37 2006.285.19:14:37.01:data_valid=off 2006.285.19:14:37.01:"et 2006.285.19:14:37.01:!+3s 2006.285.19:14:40.02:"tape 2006.285.19:14:40.02:postob 2006.285.19:14:40.18/cable/+6.5062E-03 2006.285.19:14:40.18/wx/15.01,1014.9,100 2006.285.19:14:40.24/fmout-gps/S +2.68E-07 2006.285.19:14:40.24:scan_name=285-1917,jd0610,50 2006.285.19:14:40.24:source=0552+398,055530.81,394849.2,2000.0,cw 2006.285.19:14:42.14#flagr#flagr/antenna,new-source 2006.285.19:14:42.14:checkk5 2006.285.19:14:42.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.19:14:42.92/chk_autoobs//k5ts2/ autoobs is running! 2006.285.19:14:43.42/chk_autoobs//k5ts3/ autoobs is running! 2006.285.19:14:43.87/chk_autoobs//k5ts4/ autoobs is running! 2006.285.19:14:44.28/chk_obsdata//k5ts1/T2851912??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.19:14:44.68/chk_obsdata//k5ts2/T2851912??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.19:14:45.07/chk_obsdata//k5ts3/T2851912??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.19:14:45.53/chk_obsdata//k5ts4/T2851912??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.19:14:46.99/k5log//k5ts1_log_newline 2006.285.19:14:47.84/k5log//k5ts2_log_newline 2006.285.19:14:48.59/k5log//k5ts3_log_newline 2006.285.19:14:49.39/k5log//k5ts4_log_newline 2006.285.19:14:49.41/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.19:14:49.41:setupk4=1 2006.285.19:14:49.41$setupk4/echo=on 2006.285.19:14:49.41$setupk4/pcalon 2006.285.19:14:49.41$pcalon/"no phase cal control is implemented here 2006.285.19:14:49.41$setupk4/"tpicd=stop 2006.285.19:14:49.41$setupk4/"rec=synch_on 2006.285.19:14:49.41$setupk4/"rec_mode=128 2006.285.19:14:49.41$setupk4/!* 2006.285.19:14:49.41$setupk4/recpk4 2006.285.19:14:49.41$recpk4/recpatch= 2006.285.19:14:49.41$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.19:14:49.41$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.19:14:49.42$setupk4/vck44 2006.285.19:14:49.42$vck44/valo=1,524.99 2006.285.19:14:49.42#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.19:14:49.42#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.19:14:49.42#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:49.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:14:49.42#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:14:49.42#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:14:49.42#ibcon#enter wrdev, iclass 23, count 0 2006.285.19:14:49.42#ibcon#first serial, iclass 23, count 0 2006.285.19:14:49.42#ibcon#enter sib2, iclass 23, count 0 2006.285.19:14:49.42#ibcon#flushed, iclass 23, count 0 2006.285.19:14:49.42#ibcon#about to write, iclass 23, count 0 2006.285.19:14:49.42#ibcon#wrote, iclass 23, count 0 2006.285.19:14:49.42#ibcon#about to read 3, iclass 23, count 0 2006.285.19:14:49.43#ibcon#read 3, iclass 23, count 0 2006.285.19:14:49.43#ibcon#about to read 4, iclass 23, count 0 2006.285.19:14:49.43#ibcon#read 4, iclass 23, count 0 2006.285.19:14:49.43#ibcon#about to read 5, iclass 23, count 0 2006.285.19:14:49.43#ibcon#read 5, iclass 23, count 0 2006.285.19:14:49.43#ibcon#about to read 6, iclass 23, count 0 2006.285.19:14:49.43#ibcon#read 6, iclass 23, count 0 2006.285.19:14:49.43#ibcon#end of sib2, iclass 23, count 0 2006.285.19:14:49.43#ibcon#*mode == 0, iclass 23, count 0 2006.285.19:14:49.43#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.19:14:49.43#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.19:14:49.43#ibcon#*before write, iclass 23, count 0 2006.285.19:14:49.43#ibcon#enter sib2, iclass 23, count 0 2006.285.19:14:49.43#ibcon#flushed, iclass 23, count 0 2006.285.19:14:49.43#ibcon#about to write, iclass 23, count 0 2006.285.19:14:49.43#ibcon#wrote, iclass 23, count 0 2006.285.19:14:49.43#ibcon#about to read 3, iclass 23, count 0 2006.285.19:14:49.48#ibcon#read 3, iclass 23, count 0 2006.285.19:14:49.48#ibcon#about to read 4, iclass 23, count 0 2006.285.19:14:49.48#ibcon#read 4, iclass 23, count 0 2006.285.19:14:49.48#ibcon#about to read 5, iclass 23, count 0 2006.285.19:14:49.48#ibcon#read 5, iclass 23, count 0 2006.285.19:14:49.48#ibcon#about to read 6, iclass 23, count 0 2006.285.19:14:49.48#ibcon#read 6, iclass 23, count 0 2006.285.19:14:49.48#ibcon#end of sib2, iclass 23, count 0 2006.285.19:14:49.48#ibcon#*after write, iclass 23, count 0 2006.285.19:14:49.48#ibcon#*before return 0, iclass 23, count 0 2006.285.19:14:49.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:14:49.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:14:49.48#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.19:14:49.48#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.19:14:49.48$vck44/va=1,7 2006.285.19:14:49.48#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.19:14:49.48#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.19:14:49.48#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:49.48#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:14:49.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:14:49.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:14:49.48#ibcon#enter wrdev, iclass 25, count 2 2006.285.19:14:49.48#ibcon#first serial, iclass 25, count 2 2006.285.19:14:49.48#ibcon#enter sib2, iclass 25, count 2 2006.285.19:14:49.48#ibcon#flushed, iclass 25, count 2 2006.285.19:14:49.48#ibcon#about to write, iclass 25, count 2 2006.285.19:14:49.48#ibcon#wrote, iclass 25, count 2 2006.285.19:14:49.48#ibcon#about to read 3, iclass 25, count 2 2006.285.19:14:49.50#ibcon#read 3, iclass 25, count 2 2006.285.19:14:49.50#ibcon#about to read 4, iclass 25, count 2 2006.285.19:14:49.50#ibcon#read 4, iclass 25, count 2 2006.285.19:14:49.50#ibcon#about to read 5, iclass 25, count 2 2006.285.19:14:49.50#ibcon#read 5, iclass 25, count 2 2006.285.19:14:49.50#ibcon#about to read 6, iclass 25, count 2 2006.285.19:14:49.50#ibcon#read 6, iclass 25, count 2 2006.285.19:14:49.50#ibcon#end of sib2, iclass 25, count 2 2006.285.19:14:49.50#ibcon#*mode == 0, iclass 25, count 2 2006.285.19:14:49.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.19:14:49.50#ibcon#[25=AT01-07\r\n] 2006.285.19:14:49.50#ibcon#*before write, iclass 25, count 2 2006.285.19:14:49.50#ibcon#enter sib2, iclass 25, count 2 2006.285.19:14:49.50#ibcon#flushed, iclass 25, count 2 2006.285.19:14:49.50#ibcon#about to write, iclass 25, count 2 2006.285.19:14:49.50#ibcon#wrote, iclass 25, count 2 2006.285.19:14:49.50#ibcon#about to read 3, iclass 25, count 2 2006.285.19:14:49.53#ibcon#read 3, iclass 25, count 2 2006.285.19:14:49.53#ibcon#about to read 4, iclass 25, count 2 2006.285.19:14:49.53#ibcon#read 4, iclass 25, count 2 2006.285.19:14:49.53#ibcon#about to read 5, iclass 25, count 2 2006.285.19:14:49.53#ibcon#read 5, iclass 25, count 2 2006.285.19:14:49.53#ibcon#about to read 6, iclass 25, count 2 2006.285.19:14:49.53#ibcon#read 6, iclass 25, count 2 2006.285.19:14:49.53#ibcon#end of sib2, iclass 25, count 2 2006.285.19:14:49.53#ibcon#*after write, iclass 25, count 2 2006.285.19:14:49.53#ibcon#*before return 0, iclass 25, count 2 2006.285.19:14:49.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:14:49.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:14:49.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.19:14:49.53#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:49.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:14:49.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:14:49.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:14:49.65#ibcon#enter wrdev, iclass 25, count 0 2006.285.19:14:49.65#ibcon#first serial, iclass 25, count 0 2006.285.19:14:49.65#ibcon#enter sib2, iclass 25, count 0 2006.285.19:14:49.65#ibcon#flushed, iclass 25, count 0 2006.285.19:14:49.65#ibcon#about to write, iclass 25, count 0 2006.285.19:14:49.65#ibcon#wrote, iclass 25, count 0 2006.285.19:14:49.65#ibcon#about to read 3, iclass 25, count 0 2006.285.19:14:49.67#ibcon#read 3, iclass 25, count 0 2006.285.19:14:49.67#ibcon#about to read 4, iclass 25, count 0 2006.285.19:14:49.67#ibcon#read 4, iclass 25, count 0 2006.285.19:14:49.67#ibcon#about to read 5, iclass 25, count 0 2006.285.19:14:49.67#ibcon#read 5, iclass 25, count 0 2006.285.19:14:49.67#ibcon#about to read 6, iclass 25, count 0 2006.285.19:14:49.67#ibcon#read 6, iclass 25, count 0 2006.285.19:14:49.67#ibcon#end of sib2, iclass 25, count 0 2006.285.19:14:49.67#ibcon#*mode == 0, iclass 25, count 0 2006.285.19:14:49.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.19:14:49.67#ibcon#[25=USB\r\n] 2006.285.19:14:49.67#ibcon#*before write, iclass 25, count 0 2006.285.19:14:49.67#ibcon#enter sib2, iclass 25, count 0 2006.285.19:14:49.67#ibcon#flushed, iclass 25, count 0 2006.285.19:14:49.67#ibcon#about to write, iclass 25, count 0 2006.285.19:14:49.67#ibcon#wrote, iclass 25, count 0 2006.285.19:14:49.67#ibcon#about to read 3, iclass 25, count 0 2006.285.19:14:49.70#ibcon#read 3, iclass 25, count 0 2006.285.19:14:49.70#ibcon#about to read 4, iclass 25, count 0 2006.285.19:14:49.70#ibcon#read 4, iclass 25, count 0 2006.285.19:14:49.70#ibcon#about to read 5, iclass 25, count 0 2006.285.19:14:49.70#ibcon#read 5, iclass 25, count 0 2006.285.19:14:49.70#ibcon#about to read 6, iclass 25, count 0 2006.285.19:14:49.70#ibcon#read 6, iclass 25, count 0 2006.285.19:14:49.70#ibcon#end of sib2, iclass 25, count 0 2006.285.19:14:49.70#ibcon#*after write, iclass 25, count 0 2006.285.19:14:49.70#ibcon#*before return 0, iclass 25, count 0 2006.285.19:14:49.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:14:49.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:14:49.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.19:14:49.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.19:14:49.70$vck44/valo=2,534.99 2006.285.19:14:49.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.19:14:49.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.19:14:49.70#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:49.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:14:49.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:14:49.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:14:49.70#ibcon#enter wrdev, iclass 27, count 0 2006.285.19:14:49.70#ibcon#first serial, iclass 27, count 0 2006.285.19:14:49.70#ibcon#enter sib2, iclass 27, count 0 2006.285.19:14:49.70#ibcon#flushed, iclass 27, count 0 2006.285.19:14:49.70#ibcon#about to write, iclass 27, count 0 2006.285.19:14:49.70#ibcon#wrote, iclass 27, count 0 2006.285.19:14:49.70#ibcon#about to read 3, iclass 27, count 0 2006.285.19:14:49.72#ibcon#read 3, iclass 27, count 0 2006.285.19:14:49.72#ibcon#about to read 4, iclass 27, count 0 2006.285.19:14:49.72#ibcon#read 4, iclass 27, count 0 2006.285.19:14:49.72#ibcon#about to read 5, iclass 27, count 0 2006.285.19:14:49.72#ibcon#read 5, iclass 27, count 0 2006.285.19:14:49.72#ibcon#about to read 6, iclass 27, count 0 2006.285.19:14:49.72#ibcon#read 6, iclass 27, count 0 2006.285.19:14:49.72#ibcon#end of sib2, iclass 27, count 0 2006.285.19:14:49.72#ibcon#*mode == 0, iclass 27, count 0 2006.285.19:14:49.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.19:14:49.72#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.19:14:49.72#ibcon#*before write, iclass 27, count 0 2006.285.19:14:49.72#ibcon#enter sib2, iclass 27, count 0 2006.285.19:14:49.72#ibcon#flushed, iclass 27, count 0 2006.285.19:14:49.72#ibcon#about to write, iclass 27, count 0 2006.285.19:14:49.72#ibcon#wrote, iclass 27, count 0 2006.285.19:14:49.72#ibcon#about to read 3, iclass 27, count 0 2006.285.19:14:49.76#ibcon#read 3, iclass 27, count 0 2006.285.19:14:49.76#ibcon#about to read 4, iclass 27, count 0 2006.285.19:14:49.76#ibcon#read 4, iclass 27, count 0 2006.285.19:14:49.76#ibcon#about to read 5, iclass 27, count 0 2006.285.19:14:49.76#ibcon#read 5, iclass 27, count 0 2006.285.19:14:49.76#ibcon#about to read 6, iclass 27, count 0 2006.285.19:14:49.76#ibcon#read 6, iclass 27, count 0 2006.285.19:14:49.76#ibcon#end of sib2, iclass 27, count 0 2006.285.19:14:49.76#ibcon#*after write, iclass 27, count 0 2006.285.19:14:49.76#ibcon#*before return 0, iclass 27, count 0 2006.285.19:14:49.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:14:49.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:14:49.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.19:14:49.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.19:14:49.76$vck44/va=2,6 2006.285.19:14:49.76#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.19:14:49.76#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.19:14:49.76#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:49.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:14:49.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:14:49.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:14:49.82#ibcon#enter wrdev, iclass 29, count 2 2006.285.19:14:49.82#ibcon#first serial, iclass 29, count 2 2006.285.19:14:49.82#ibcon#enter sib2, iclass 29, count 2 2006.285.19:14:49.82#ibcon#flushed, iclass 29, count 2 2006.285.19:14:49.82#ibcon#about to write, iclass 29, count 2 2006.285.19:14:49.82#ibcon#wrote, iclass 29, count 2 2006.285.19:14:49.82#ibcon#about to read 3, iclass 29, count 2 2006.285.19:14:49.84#ibcon#read 3, iclass 29, count 2 2006.285.19:14:49.84#ibcon#about to read 4, iclass 29, count 2 2006.285.19:14:49.84#ibcon#read 4, iclass 29, count 2 2006.285.19:14:49.84#ibcon#about to read 5, iclass 29, count 2 2006.285.19:14:49.84#ibcon#read 5, iclass 29, count 2 2006.285.19:14:49.84#ibcon#about to read 6, iclass 29, count 2 2006.285.19:14:49.84#ibcon#read 6, iclass 29, count 2 2006.285.19:14:49.84#ibcon#end of sib2, iclass 29, count 2 2006.285.19:14:49.84#ibcon#*mode == 0, iclass 29, count 2 2006.285.19:14:49.84#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.19:14:49.84#ibcon#[25=AT02-06\r\n] 2006.285.19:14:49.84#ibcon#*before write, iclass 29, count 2 2006.285.19:14:49.84#ibcon#enter sib2, iclass 29, count 2 2006.285.19:14:49.84#ibcon#flushed, iclass 29, count 2 2006.285.19:14:49.84#ibcon#about to write, iclass 29, count 2 2006.285.19:14:49.84#ibcon#wrote, iclass 29, count 2 2006.285.19:14:49.84#ibcon#about to read 3, iclass 29, count 2 2006.285.19:14:49.87#ibcon#read 3, iclass 29, count 2 2006.285.19:14:49.87#ibcon#about to read 4, iclass 29, count 2 2006.285.19:14:49.87#ibcon#read 4, iclass 29, count 2 2006.285.19:14:49.87#ibcon#about to read 5, iclass 29, count 2 2006.285.19:14:49.87#ibcon#read 5, iclass 29, count 2 2006.285.19:14:49.87#ibcon#about to read 6, iclass 29, count 2 2006.285.19:14:49.87#ibcon#read 6, iclass 29, count 2 2006.285.19:14:49.87#ibcon#end of sib2, iclass 29, count 2 2006.285.19:14:49.87#ibcon#*after write, iclass 29, count 2 2006.285.19:14:49.87#ibcon#*before return 0, iclass 29, count 2 2006.285.19:14:49.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:14:49.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:14:49.87#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.19:14:49.87#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:49.87#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:14:49.99#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:14:49.99#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:14:49.99#ibcon#enter wrdev, iclass 29, count 0 2006.285.19:14:49.99#ibcon#first serial, iclass 29, count 0 2006.285.19:14:49.99#ibcon#enter sib2, iclass 29, count 0 2006.285.19:14:49.99#ibcon#flushed, iclass 29, count 0 2006.285.19:14:49.99#ibcon#about to write, iclass 29, count 0 2006.285.19:14:49.99#ibcon#wrote, iclass 29, count 0 2006.285.19:14:49.99#ibcon#about to read 3, iclass 29, count 0 2006.285.19:14:50.01#ibcon#read 3, iclass 29, count 0 2006.285.19:14:50.01#ibcon#about to read 4, iclass 29, count 0 2006.285.19:14:50.01#ibcon#read 4, iclass 29, count 0 2006.285.19:14:50.01#ibcon#about to read 5, iclass 29, count 0 2006.285.19:14:50.01#ibcon#read 5, iclass 29, count 0 2006.285.19:14:50.01#ibcon#about to read 6, iclass 29, count 0 2006.285.19:14:50.01#ibcon#read 6, iclass 29, count 0 2006.285.19:14:50.01#ibcon#end of sib2, iclass 29, count 0 2006.285.19:14:50.01#ibcon#*mode == 0, iclass 29, count 0 2006.285.19:14:50.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.19:14:50.01#ibcon#[25=USB\r\n] 2006.285.19:14:50.01#ibcon#*before write, iclass 29, count 0 2006.285.19:14:50.01#ibcon#enter sib2, iclass 29, count 0 2006.285.19:14:50.01#ibcon#flushed, iclass 29, count 0 2006.285.19:14:50.01#ibcon#about to write, iclass 29, count 0 2006.285.19:14:50.01#ibcon#wrote, iclass 29, count 0 2006.285.19:14:50.01#ibcon#about to read 3, iclass 29, count 0 2006.285.19:14:50.04#ibcon#read 3, iclass 29, count 0 2006.285.19:14:50.04#ibcon#about to read 4, iclass 29, count 0 2006.285.19:14:50.04#ibcon#read 4, iclass 29, count 0 2006.285.19:14:50.04#ibcon#about to read 5, iclass 29, count 0 2006.285.19:14:50.04#ibcon#read 5, iclass 29, count 0 2006.285.19:14:50.04#ibcon#about to read 6, iclass 29, count 0 2006.285.19:14:50.04#ibcon#read 6, iclass 29, count 0 2006.285.19:14:50.04#ibcon#end of sib2, iclass 29, count 0 2006.285.19:14:50.04#ibcon#*after write, iclass 29, count 0 2006.285.19:14:50.04#ibcon#*before return 0, iclass 29, count 0 2006.285.19:14:50.04#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:14:50.04#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:14:50.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.19:14:50.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.19:14:50.04$vck44/valo=3,564.99 2006.285.19:14:50.04#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.19:14:50.04#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.19:14:50.04#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:50.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:14:50.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:14:50.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:14:50.04#ibcon#enter wrdev, iclass 31, count 0 2006.285.19:14:50.04#ibcon#first serial, iclass 31, count 0 2006.285.19:14:50.04#ibcon#enter sib2, iclass 31, count 0 2006.285.19:14:50.04#ibcon#flushed, iclass 31, count 0 2006.285.19:14:50.04#ibcon#about to write, iclass 31, count 0 2006.285.19:14:50.04#ibcon#wrote, iclass 31, count 0 2006.285.19:14:50.04#ibcon#about to read 3, iclass 31, count 0 2006.285.19:14:50.06#ibcon#read 3, iclass 31, count 0 2006.285.19:14:50.06#ibcon#about to read 4, iclass 31, count 0 2006.285.19:14:50.06#ibcon#read 4, iclass 31, count 0 2006.285.19:14:50.06#ibcon#about to read 5, iclass 31, count 0 2006.285.19:14:50.06#ibcon#read 5, iclass 31, count 0 2006.285.19:14:50.06#ibcon#about to read 6, iclass 31, count 0 2006.285.19:14:50.06#ibcon#read 6, iclass 31, count 0 2006.285.19:14:50.06#ibcon#end of sib2, iclass 31, count 0 2006.285.19:14:50.06#ibcon#*mode == 0, iclass 31, count 0 2006.285.19:14:50.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.19:14:50.06#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.19:14:50.06#ibcon#*before write, iclass 31, count 0 2006.285.19:14:50.06#ibcon#enter sib2, iclass 31, count 0 2006.285.19:14:50.06#ibcon#flushed, iclass 31, count 0 2006.285.19:14:50.06#ibcon#about to write, iclass 31, count 0 2006.285.19:14:50.06#ibcon#wrote, iclass 31, count 0 2006.285.19:14:50.06#ibcon#about to read 3, iclass 31, count 0 2006.285.19:14:50.10#ibcon#read 3, iclass 31, count 0 2006.285.19:14:50.10#ibcon#about to read 4, iclass 31, count 0 2006.285.19:14:50.10#ibcon#read 4, iclass 31, count 0 2006.285.19:14:50.10#ibcon#about to read 5, iclass 31, count 0 2006.285.19:14:50.10#ibcon#read 5, iclass 31, count 0 2006.285.19:14:50.10#ibcon#about to read 6, iclass 31, count 0 2006.285.19:14:50.10#ibcon#read 6, iclass 31, count 0 2006.285.19:14:50.10#ibcon#end of sib2, iclass 31, count 0 2006.285.19:14:50.10#ibcon#*after write, iclass 31, count 0 2006.285.19:14:50.10#ibcon#*before return 0, iclass 31, count 0 2006.285.19:14:50.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:14:50.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:14:50.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.19:14:50.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.19:14:50.10$vck44/va=3,7 2006.285.19:14:50.10#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.19:14:50.10#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.19:14:50.10#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:50.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:14:50.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:14:50.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:14:50.16#ibcon#enter wrdev, iclass 33, count 2 2006.285.19:14:50.16#ibcon#first serial, iclass 33, count 2 2006.285.19:14:50.16#ibcon#enter sib2, iclass 33, count 2 2006.285.19:14:50.16#ibcon#flushed, iclass 33, count 2 2006.285.19:14:50.16#ibcon#about to write, iclass 33, count 2 2006.285.19:14:50.16#ibcon#wrote, iclass 33, count 2 2006.285.19:14:50.16#ibcon#about to read 3, iclass 33, count 2 2006.285.19:14:50.18#ibcon#read 3, iclass 33, count 2 2006.285.19:14:50.18#ibcon#about to read 4, iclass 33, count 2 2006.285.19:14:50.18#ibcon#read 4, iclass 33, count 2 2006.285.19:14:50.18#ibcon#about to read 5, iclass 33, count 2 2006.285.19:14:50.18#ibcon#read 5, iclass 33, count 2 2006.285.19:14:50.18#ibcon#about to read 6, iclass 33, count 2 2006.285.19:14:50.18#ibcon#read 6, iclass 33, count 2 2006.285.19:14:50.18#ibcon#end of sib2, iclass 33, count 2 2006.285.19:14:50.18#ibcon#*mode == 0, iclass 33, count 2 2006.285.19:14:50.18#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.19:14:50.18#ibcon#[25=AT03-07\r\n] 2006.285.19:14:50.18#ibcon#*before write, iclass 33, count 2 2006.285.19:14:50.18#ibcon#enter sib2, iclass 33, count 2 2006.285.19:14:50.18#ibcon#flushed, iclass 33, count 2 2006.285.19:14:50.18#ibcon#about to write, iclass 33, count 2 2006.285.19:14:50.18#ibcon#wrote, iclass 33, count 2 2006.285.19:14:50.18#ibcon#about to read 3, iclass 33, count 2 2006.285.19:14:50.21#ibcon#read 3, iclass 33, count 2 2006.285.19:14:50.21#ibcon#about to read 4, iclass 33, count 2 2006.285.19:14:50.21#ibcon#read 4, iclass 33, count 2 2006.285.19:14:50.21#ibcon#about to read 5, iclass 33, count 2 2006.285.19:14:50.21#ibcon#read 5, iclass 33, count 2 2006.285.19:14:50.21#ibcon#about to read 6, iclass 33, count 2 2006.285.19:14:50.21#ibcon#read 6, iclass 33, count 2 2006.285.19:14:50.21#ibcon#end of sib2, iclass 33, count 2 2006.285.19:14:50.21#ibcon#*after write, iclass 33, count 2 2006.285.19:14:50.21#ibcon#*before return 0, iclass 33, count 2 2006.285.19:14:50.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:14:50.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:14:50.21#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.19:14:50.21#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:50.21#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:14:50.33#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:14:50.92#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:14:50.92#ibcon#enter wrdev, iclass 33, count 0 2006.285.19:14:50.92#ibcon#first serial, iclass 33, count 0 2006.285.19:14:50.92#ibcon#enter sib2, iclass 33, count 0 2006.285.19:14:50.92#ibcon#flushed, iclass 33, count 0 2006.285.19:14:50.92#ibcon#about to write, iclass 33, count 0 2006.285.19:14:50.92#ibcon#wrote, iclass 33, count 0 2006.285.19:14:50.92#ibcon#about to read 3, iclass 33, count 0 2006.285.19:14:50.94#ibcon#read 3, iclass 33, count 0 2006.285.19:14:50.94#ibcon#about to read 4, iclass 33, count 0 2006.285.19:14:50.94#ibcon#read 4, iclass 33, count 0 2006.285.19:14:50.94#ibcon#about to read 5, iclass 33, count 0 2006.285.19:14:50.94#ibcon#read 5, iclass 33, count 0 2006.285.19:14:50.94#ibcon#about to read 6, iclass 33, count 0 2006.285.19:14:50.94#ibcon#read 6, iclass 33, count 0 2006.285.19:14:50.94#ibcon#end of sib2, iclass 33, count 0 2006.285.19:14:50.94#ibcon#*mode == 0, iclass 33, count 0 2006.285.19:14:50.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.19:14:50.94#ibcon#[25=USB\r\n] 2006.285.19:14:50.94#ibcon#*before write, iclass 33, count 0 2006.285.19:14:50.94#ibcon#enter sib2, iclass 33, count 0 2006.285.19:14:50.94#ibcon#flushed, iclass 33, count 0 2006.285.19:14:50.94#ibcon#about to write, iclass 33, count 0 2006.285.19:14:50.94#ibcon#wrote, iclass 33, count 0 2006.285.19:14:50.94#ibcon#about to read 3, iclass 33, count 0 2006.285.19:14:50.97#ibcon#read 3, iclass 33, count 0 2006.285.19:14:50.97#ibcon#about to read 4, iclass 33, count 0 2006.285.19:14:50.97#ibcon#read 4, iclass 33, count 0 2006.285.19:14:50.97#ibcon#about to read 5, iclass 33, count 0 2006.285.19:14:50.97#ibcon#read 5, iclass 33, count 0 2006.285.19:14:50.97#ibcon#about to read 6, iclass 33, count 0 2006.285.19:14:50.97#ibcon#read 6, iclass 33, count 0 2006.285.19:14:50.97#ibcon#end of sib2, iclass 33, count 0 2006.285.19:14:50.97#ibcon#*after write, iclass 33, count 0 2006.285.19:14:50.97#ibcon#*before return 0, iclass 33, count 0 2006.285.19:14:50.97#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:14:50.97#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:14:50.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.19:14:50.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.19:14:50.97$vck44/valo=4,624.99 2006.285.19:14:50.97#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.19:14:50.97#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.19:14:50.97#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:50.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:14:50.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:14:50.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:14:50.97#ibcon#enter wrdev, iclass 35, count 0 2006.285.19:14:50.97#ibcon#first serial, iclass 35, count 0 2006.285.19:14:50.97#ibcon#enter sib2, iclass 35, count 0 2006.285.19:14:50.97#ibcon#flushed, iclass 35, count 0 2006.285.19:14:50.97#ibcon#about to write, iclass 35, count 0 2006.285.19:14:50.97#ibcon#wrote, iclass 35, count 0 2006.285.19:14:50.97#ibcon#about to read 3, iclass 35, count 0 2006.285.19:14:50.99#ibcon#read 3, iclass 35, count 0 2006.285.19:14:50.99#ibcon#about to read 4, iclass 35, count 0 2006.285.19:14:50.99#ibcon#read 4, iclass 35, count 0 2006.285.19:14:50.99#ibcon#about to read 5, iclass 35, count 0 2006.285.19:14:50.99#ibcon#read 5, iclass 35, count 0 2006.285.19:14:50.99#ibcon#about to read 6, iclass 35, count 0 2006.285.19:14:50.99#ibcon#read 6, iclass 35, count 0 2006.285.19:14:50.99#ibcon#end of sib2, iclass 35, count 0 2006.285.19:14:50.99#ibcon#*mode == 0, iclass 35, count 0 2006.285.19:14:50.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.19:14:50.99#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.19:14:50.99#ibcon#*before write, iclass 35, count 0 2006.285.19:14:50.99#ibcon#enter sib2, iclass 35, count 0 2006.285.19:14:50.99#ibcon#flushed, iclass 35, count 0 2006.285.19:14:50.99#ibcon#about to write, iclass 35, count 0 2006.285.19:14:50.99#ibcon#wrote, iclass 35, count 0 2006.285.19:14:50.99#ibcon#about to read 3, iclass 35, count 0 2006.285.19:14:51.03#ibcon#read 3, iclass 35, count 0 2006.285.19:14:51.03#ibcon#about to read 4, iclass 35, count 0 2006.285.19:14:51.03#ibcon#read 4, iclass 35, count 0 2006.285.19:14:51.03#ibcon#about to read 5, iclass 35, count 0 2006.285.19:14:51.03#ibcon#read 5, iclass 35, count 0 2006.285.19:14:51.03#ibcon#about to read 6, iclass 35, count 0 2006.285.19:14:51.03#ibcon#read 6, iclass 35, count 0 2006.285.19:14:51.03#ibcon#end of sib2, iclass 35, count 0 2006.285.19:14:51.03#ibcon#*after write, iclass 35, count 0 2006.285.19:14:51.03#ibcon#*before return 0, iclass 35, count 0 2006.285.19:14:51.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:14:51.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:14:51.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.19:14:51.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.19:14:51.03$vck44/va=4,6 2006.285.19:14:51.03#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.19:14:51.03#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.19:14:51.03#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:51.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:14:51.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:14:51.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:14:51.09#ibcon#enter wrdev, iclass 37, count 2 2006.285.19:14:51.09#ibcon#first serial, iclass 37, count 2 2006.285.19:14:51.09#ibcon#enter sib2, iclass 37, count 2 2006.285.19:14:51.09#ibcon#flushed, iclass 37, count 2 2006.285.19:14:51.09#ibcon#about to write, iclass 37, count 2 2006.285.19:14:51.09#ibcon#wrote, iclass 37, count 2 2006.285.19:14:51.09#ibcon#about to read 3, iclass 37, count 2 2006.285.19:14:51.11#ibcon#read 3, iclass 37, count 2 2006.285.19:14:51.11#ibcon#about to read 4, iclass 37, count 2 2006.285.19:14:51.11#ibcon#read 4, iclass 37, count 2 2006.285.19:14:51.11#ibcon#about to read 5, iclass 37, count 2 2006.285.19:14:51.11#ibcon#read 5, iclass 37, count 2 2006.285.19:14:51.11#ibcon#about to read 6, iclass 37, count 2 2006.285.19:14:51.11#ibcon#read 6, iclass 37, count 2 2006.285.19:14:51.11#ibcon#end of sib2, iclass 37, count 2 2006.285.19:14:51.11#ibcon#*mode == 0, iclass 37, count 2 2006.285.19:14:51.11#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.19:14:51.11#ibcon#[25=AT04-06\r\n] 2006.285.19:14:51.11#ibcon#*before write, iclass 37, count 2 2006.285.19:14:51.11#ibcon#enter sib2, iclass 37, count 2 2006.285.19:14:51.11#ibcon#flushed, iclass 37, count 2 2006.285.19:14:51.11#ibcon#about to write, iclass 37, count 2 2006.285.19:14:51.11#ibcon#wrote, iclass 37, count 2 2006.285.19:14:51.11#ibcon#about to read 3, iclass 37, count 2 2006.285.19:14:51.14#ibcon#read 3, iclass 37, count 2 2006.285.19:14:51.14#ibcon#about to read 4, iclass 37, count 2 2006.285.19:14:51.14#ibcon#read 4, iclass 37, count 2 2006.285.19:14:51.14#ibcon#about to read 5, iclass 37, count 2 2006.285.19:14:51.14#ibcon#read 5, iclass 37, count 2 2006.285.19:14:51.14#ibcon#about to read 6, iclass 37, count 2 2006.285.19:14:51.14#ibcon#read 6, iclass 37, count 2 2006.285.19:14:51.14#ibcon#end of sib2, iclass 37, count 2 2006.285.19:14:51.14#ibcon#*after write, iclass 37, count 2 2006.285.19:14:51.14#ibcon#*before return 0, iclass 37, count 2 2006.285.19:14:51.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:14:51.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:14:51.14#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.19:14:51.14#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:51.14#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:14:51.26#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:14:51.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:14:51.47#ibcon#enter wrdev, iclass 37, count 0 2006.285.19:14:51.47#ibcon#first serial, iclass 37, count 0 2006.285.19:14:51.47#ibcon#enter sib2, iclass 37, count 0 2006.285.19:14:51.47#ibcon#flushed, iclass 37, count 0 2006.285.19:14:51.47#ibcon#about to write, iclass 37, count 0 2006.285.19:14:51.47#ibcon#wrote, iclass 37, count 0 2006.285.19:14:51.47#ibcon#about to read 3, iclass 37, count 0 2006.285.19:14:51.49#ibcon#read 3, iclass 37, count 0 2006.285.19:14:51.49#ibcon#about to read 4, iclass 37, count 0 2006.285.19:14:51.49#ibcon#read 4, iclass 37, count 0 2006.285.19:14:51.49#ibcon#about to read 5, iclass 37, count 0 2006.285.19:14:51.49#ibcon#read 5, iclass 37, count 0 2006.285.19:14:51.49#ibcon#about to read 6, iclass 37, count 0 2006.285.19:14:51.49#ibcon#read 6, iclass 37, count 0 2006.285.19:14:51.49#ibcon#end of sib2, iclass 37, count 0 2006.285.19:14:51.49#ibcon#*mode == 0, iclass 37, count 0 2006.285.19:14:51.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.19:14:51.49#ibcon#[25=USB\r\n] 2006.285.19:14:51.49#ibcon#*before write, iclass 37, count 0 2006.285.19:14:51.49#ibcon#enter sib2, iclass 37, count 0 2006.285.19:14:51.49#ibcon#flushed, iclass 37, count 0 2006.285.19:14:51.49#ibcon#about to write, iclass 37, count 0 2006.285.19:14:51.49#ibcon#wrote, iclass 37, count 0 2006.285.19:14:51.49#ibcon#about to read 3, iclass 37, count 0 2006.285.19:14:51.52#ibcon#read 3, iclass 37, count 0 2006.285.19:14:51.52#ibcon#about to read 4, iclass 37, count 0 2006.285.19:14:51.52#ibcon#read 4, iclass 37, count 0 2006.285.19:14:51.52#ibcon#about to read 5, iclass 37, count 0 2006.285.19:14:51.52#ibcon#read 5, iclass 37, count 0 2006.285.19:14:51.52#ibcon#about to read 6, iclass 37, count 0 2006.285.19:14:51.52#ibcon#read 6, iclass 37, count 0 2006.285.19:14:51.52#ibcon#end of sib2, iclass 37, count 0 2006.285.19:14:51.52#ibcon#*after write, iclass 37, count 0 2006.285.19:14:51.52#ibcon#*before return 0, iclass 37, count 0 2006.285.19:14:51.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:14:51.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:14:51.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.19:14:51.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.19:14:51.52$vck44/valo=5,734.99 2006.285.19:14:51.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.19:14:51.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.19:14:51.52#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:51.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:14:51.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:14:51.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:14:51.52#ibcon#enter wrdev, iclass 39, count 0 2006.285.19:14:51.52#ibcon#first serial, iclass 39, count 0 2006.285.19:14:51.52#ibcon#enter sib2, iclass 39, count 0 2006.285.19:14:51.52#ibcon#flushed, iclass 39, count 0 2006.285.19:14:51.52#ibcon#about to write, iclass 39, count 0 2006.285.19:14:51.52#ibcon#wrote, iclass 39, count 0 2006.285.19:14:51.52#ibcon#about to read 3, iclass 39, count 0 2006.285.19:14:51.54#ibcon#read 3, iclass 39, count 0 2006.285.19:14:51.54#ibcon#about to read 4, iclass 39, count 0 2006.285.19:14:51.54#ibcon#read 4, iclass 39, count 0 2006.285.19:14:51.54#ibcon#about to read 5, iclass 39, count 0 2006.285.19:14:51.54#ibcon#read 5, iclass 39, count 0 2006.285.19:14:51.54#ibcon#about to read 6, iclass 39, count 0 2006.285.19:14:51.54#ibcon#read 6, iclass 39, count 0 2006.285.19:14:51.54#ibcon#end of sib2, iclass 39, count 0 2006.285.19:14:51.54#ibcon#*mode == 0, iclass 39, count 0 2006.285.19:14:51.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.19:14:51.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.19:14:51.54#ibcon#*before write, iclass 39, count 0 2006.285.19:14:51.54#ibcon#enter sib2, iclass 39, count 0 2006.285.19:14:51.54#ibcon#flushed, iclass 39, count 0 2006.285.19:14:51.54#ibcon#about to write, iclass 39, count 0 2006.285.19:14:51.54#ibcon#wrote, iclass 39, count 0 2006.285.19:14:51.54#ibcon#about to read 3, iclass 39, count 0 2006.285.19:14:51.58#ibcon#read 3, iclass 39, count 0 2006.285.19:14:51.58#ibcon#about to read 4, iclass 39, count 0 2006.285.19:14:51.58#ibcon#read 4, iclass 39, count 0 2006.285.19:14:51.58#ibcon#about to read 5, iclass 39, count 0 2006.285.19:14:51.58#ibcon#read 5, iclass 39, count 0 2006.285.19:14:51.58#ibcon#about to read 6, iclass 39, count 0 2006.285.19:14:51.58#ibcon#read 6, iclass 39, count 0 2006.285.19:14:51.58#ibcon#end of sib2, iclass 39, count 0 2006.285.19:14:51.58#ibcon#*after write, iclass 39, count 0 2006.285.19:14:51.58#ibcon#*before return 0, iclass 39, count 0 2006.285.19:14:51.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:14:51.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:14:51.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.19:14:51.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.19:14:51.58$vck44/va=5,3 2006.285.19:14:51.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.19:14:51.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.19:14:51.58#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:51.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:14:51.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:14:51.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:14:51.64#ibcon#enter wrdev, iclass 3, count 2 2006.285.19:14:51.64#ibcon#first serial, iclass 3, count 2 2006.285.19:14:51.64#ibcon#enter sib2, iclass 3, count 2 2006.285.19:14:51.64#ibcon#flushed, iclass 3, count 2 2006.285.19:14:51.64#ibcon#about to write, iclass 3, count 2 2006.285.19:14:51.64#ibcon#wrote, iclass 3, count 2 2006.285.19:14:51.64#ibcon#about to read 3, iclass 3, count 2 2006.285.19:14:51.66#ibcon#read 3, iclass 3, count 2 2006.285.19:14:51.66#ibcon#about to read 4, iclass 3, count 2 2006.285.19:14:51.66#ibcon#read 4, iclass 3, count 2 2006.285.19:14:51.66#ibcon#about to read 5, iclass 3, count 2 2006.285.19:14:51.66#ibcon#read 5, iclass 3, count 2 2006.285.19:14:51.66#ibcon#about to read 6, iclass 3, count 2 2006.285.19:14:51.66#ibcon#read 6, iclass 3, count 2 2006.285.19:14:51.66#ibcon#end of sib2, iclass 3, count 2 2006.285.19:14:51.66#ibcon#*mode == 0, iclass 3, count 2 2006.285.19:14:51.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.19:14:51.66#ibcon#[25=AT05-03\r\n] 2006.285.19:14:51.66#ibcon#*before write, iclass 3, count 2 2006.285.19:14:51.66#ibcon#enter sib2, iclass 3, count 2 2006.285.19:14:51.66#ibcon#flushed, iclass 3, count 2 2006.285.19:14:51.66#ibcon#about to write, iclass 3, count 2 2006.285.19:14:51.66#ibcon#wrote, iclass 3, count 2 2006.285.19:14:51.66#ibcon#about to read 3, iclass 3, count 2 2006.285.19:14:51.69#ibcon#read 3, iclass 3, count 2 2006.285.19:14:51.69#ibcon#about to read 4, iclass 3, count 2 2006.285.19:14:51.69#ibcon#read 4, iclass 3, count 2 2006.285.19:14:51.69#ibcon#about to read 5, iclass 3, count 2 2006.285.19:14:51.69#ibcon#read 5, iclass 3, count 2 2006.285.19:14:51.69#ibcon#about to read 6, iclass 3, count 2 2006.285.19:14:51.69#ibcon#read 6, iclass 3, count 2 2006.285.19:14:51.69#ibcon#end of sib2, iclass 3, count 2 2006.285.19:14:51.69#ibcon#*after write, iclass 3, count 2 2006.285.19:14:51.69#ibcon#*before return 0, iclass 3, count 2 2006.285.19:14:51.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:14:51.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:14:51.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.19:14:51.69#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:51.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:14:51.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:14:51.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:14:51.81#ibcon#enter wrdev, iclass 3, count 0 2006.285.19:14:51.81#ibcon#first serial, iclass 3, count 0 2006.285.19:14:51.81#ibcon#enter sib2, iclass 3, count 0 2006.285.19:14:51.81#ibcon#flushed, iclass 3, count 0 2006.285.19:14:51.81#ibcon#about to write, iclass 3, count 0 2006.285.19:14:51.81#ibcon#wrote, iclass 3, count 0 2006.285.19:14:51.81#ibcon#about to read 3, iclass 3, count 0 2006.285.19:14:51.83#ibcon#read 3, iclass 3, count 0 2006.285.19:14:51.83#ibcon#about to read 4, iclass 3, count 0 2006.285.19:14:51.83#ibcon#read 4, iclass 3, count 0 2006.285.19:14:51.83#ibcon#about to read 5, iclass 3, count 0 2006.285.19:14:51.83#ibcon#read 5, iclass 3, count 0 2006.285.19:14:51.83#ibcon#about to read 6, iclass 3, count 0 2006.285.19:14:51.83#ibcon#read 6, iclass 3, count 0 2006.285.19:14:51.83#ibcon#end of sib2, iclass 3, count 0 2006.285.19:14:51.83#ibcon#*mode == 0, iclass 3, count 0 2006.285.19:14:51.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.19:14:51.83#ibcon#[25=USB\r\n] 2006.285.19:14:51.83#ibcon#*before write, iclass 3, count 0 2006.285.19:14:51.83#ibcon#enter sib2, iclass 3, count 0 2006.285.19:14:51.83#ibcon#flushed, iclass 3, count 0 2006.285.19:14:51.83#ibcon#about to write, iclass 3, count 0 2006.285.19:14:51.83#ibcon#wrote, iclass 3, count 0 2006.285.19:14:51.83#ibcon#about to read 3, iclass 3, count 0 2006.285.19:14:51.86#ibcon#read 3, iclass 3, count 0 2006.285.19:14:51.86#ibcon#about to read 4, iclass 3, count 0 2006.285.19:14:51.86#ibcon#read 4, iclass 3, count 0 2006.285.19:14:51.86#ibcon#about to read 5, iclass 3, count 0 2006.285.19:14:51.86#ibcon#read 5, iclass 3, count 0 2006.285.19:14:51.86#ibcon#about to read 6, iclass 3, count 0 2006.285.19:14:51.86#ibcon#read 6, iclass 3, count 0 2006.285.19:14:51.86#ibcon#end of sib2, iclass 3, count 0 2006.285.19:14:51.86#ibcon#*after write, iclass 3, count 0 2006.285.19:14:51.86#ibcon#*before return 0, iclass 3, count 0 2006.285.19:14:51.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:14:51.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:14:51.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.19:14:51.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.19:14:51.86$vck44/valo=6,814.99 2006.285.19:14:51.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.19:14:51.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.19:14:51.86#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:51.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:14:51.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:14:51.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:14:51.86#ibcon#enter wrdev, iclass 5, count 0 2006.285.19:14:51.86#ibcon#first serial, iclass 5, count 0 2006.285.19:14:51.86#ibcon#enter sib2, iclass 5, count 0 2006.285.19:14:51.86#ibcon#flushed, iclass 5, count 0 2006.285.19:14:51.86#ibcon#about to write, iclass 5, count 0 2006.285.19:14:51.86#ibcon#wrote, iclass 5, count 0 2006.285.19:14:51.86#ibcon#about to read 3, iclass 5, count 0 2006.285.19:14:51.88#ibcon#read 3, iclass 5, count 0 2006.285.19:14:51.88#ibcon#about to read 4, iclass 5, count 0 2006.285.19:14:51.88#ibcon#read 4, iclass 5, count 0 2006.285.19:14:51.88#ibcon#about to read 5, iclass 5, count 0 2006.285.19:14:51.88#ibcon#read 5, iclass 5, count 0 2006.285.19:14:51.88#ibcon#about to read 6, iclass 5, count 0 2006.285.19:14:51.88#ibcon#read 6, iclass 5, count 0 2006.285.19:14:51.88#ibcon#end of sib2, iclass 5, count 0 2006.285.19:14:51.88#ibcon#*mode == 0, iclass 5, count 0 2006.285.19:14:51.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.19:14:51.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.19:14:51.88#ibcon#*before write, iclass 5, count 0 2006.285.19:14:51.88#ibcon#enter sib2, iclass 5, count 0 2006.285.19:14:51.88#ibcon#flushed, iclass 5, count 0 2006.285.19:14:51.88#ibcon#about to write, iclass 5, count 0 2006.285.19:14:51.88#ibcon#wrote, iclass 5, count 0 2006.285.19:14:51.88#ibcon#about to read 3, iclass 5, count 0 2006.285.19:14:51.92#ibcon#read 3, iclass 5, count 0 2006.285.19:14:51.92#ibcon#about to read 4, iclass 5, count 0 2006.285.19:14:51.92#ibcon#read 4, iclass 5, count 0 2006.285.19:14:51.92#ibcon#about to read 5, iclass 5, count 0 2006.285.19:14:51.92#ibcon#read 5, iclass 5, count 0 2006.285.19:14:51.92#ibcon#about to read 6, iclass 5, count 0 2006.285.19:14:51.92#ibcon#read 6, iclass 5, count 0 2006.285.19:14:51.92#ibcon#end of sib2, iclass 5, count 0 2006.285.19:14:51.92#ibcon#*after write, iclass 5, count 0 2006.285.19:14:51.92#ibcon#*before return 0, iclass 5, count 0 2006.285.19:14:51.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:14:51.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:14:51.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.19:14:51.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.19:14:51.92$vck44/va=6,4 2006.285.19:14:51.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.19:14:51.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.19:14:51.92#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:51.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:14:51.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:14:51.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:14:51.98#ibcon#enter wrdev, iclass 7, count 2 2006.285.19:14:51.98#ibcon#first serial, iclass 7, count 2 2006.285.19:14:51.98#ibcon#enter sib2, iclass 7, count 2 2006.285.19:14:51.98#ibcon#flushed, iclass 7, count 2 2006.285.19:14:51.98#ibcon#about to write, iclass 7, count 2 2006.285.19:14:51.98#ibcon#wrote, iclass 7, count 2 2006.285.19:14:51.98#ibcon#about to read 3, iclass 7, count 2 2006.285.19:14:52.00#ibcon#read 3, iclass 7, count 2 2006.285.19:14:52.00#ibcon#about to read 4, iclass 7, count 2 2006.285.19:14:52.00#ibcon#read 4, iclass 7, count 2 2006.285.19:14:52.00#ibcon#about to read 5, iclass 7, count 2 2006.285.19:14:52.00#ibcon#read 5, iclass 7, count 2 2006.285.19:14:52.00#ibcon#about to read 6, iclass 7, count 2 2006.285.19:14:52.00#ibcon#read 6, iclass 7, count 2 2006.285.19:14:52.00#ibcon#end of sib2, iclass 7, count 2 2006.285.19:14:52.00#ibcon#*mode == 0, iclass 7, count 2 2006.285.19:14:52.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.19:14:52.00#ibcon#[25=AT06-04\r\n] 2006.285.19:14:52.00#ibcon#*before write, iclass 7, count 2 2006.285.19:14:52.00#ibcon#enter sib2, iclass 7, count 2 2006.285.19:14:52.00#ibcon#flushed, iclass 7, count 2 2006.285.19:14:52.00#ibcon#about to write, iclass 7, count 2 2006.285.19:14:52.00#ibcon#wrote, iclass 7, count 2 2006.285.19:14:52.00#ibcon#about to read 3, iclass 7, count 2 2006.285.19:14:52.03#ibcon#read 3, iclass 7, count 2 2006.285.19:14:52.03#ibcon#about to read 4, iclass 7, count 2 2006.285.19:14:52.03#ibcon#read 4, iclass 7, count 2 2006.285.19:14:52.03#ibcon#about to read 5, iclass 7, count 2 2006.285.19:14:52.03#ibcon#read 5, iclass 7, count 2 2006.285.19:14:52.03#ibcon#about to read 6, iclass 7, count 2 2006.285.19:14:52.03#ibcon#read 6, iclass 7, count 2 2006.285.19:14:52.03#ibcon#end of sib2, iclass 7, count 2 2006.285.19:14:52.03#ibcon#*after write, iclass 7, count 2 2006.285.19:14:52.03#ibcon#*before return 0, iclass 7, count 2 2006.285.19:14:52.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:14:52.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:14:52.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.19:14:52.03#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:52.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:14:52.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:14:52.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:14:52.15#ibcon#enter wrdev, iclass 7, count 0 2006.285.19:14:52.15#ibcon#first serial, iclass 7, count 0 2006.285.19:14:52.15#ibcon#enter sib2, iclass 7, count 0 2006.285.19:14:52.15#ibcon#flushed, iclass 7, count 0 2006.285.19:14:52.15#ibcon#about to write, iclass 7, count 0 2006.285.19:14:52.15#ibcon#wrote, iclass 7, count 0 2006.285.19:14:52.15#ibcon#about to read 3, iclass 7, count 0 2006.285.19:14:52.17#ibcon#read 3, iclass 7, count 0 2006.285.19:14:52.17#ibcon#about to read 4, iclass 7, count 0 2006.285.19:14:52.17#ibcon#read 4, iclass 7, count 0 2006.285.19:14:52.17#ibcon#about to read 5, iclass 7, count 0 2006.285.19:14:52.17#ibcon#read 5, iclass 7, count 0 2006.285.19:14:52.17#ibcon#about to read 6, iclass 7, count 0 2006.285.19:14:52.17#ibcon#read 6, iclass 7, count 0 2006.285.19:14:52.17#ibcon#end of sib2, iclass 7, count 0 2006.285.19:14:52.17#ibcon#*mode == 0, iclass 7, count 0 2006.285.19:14:52.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.19:14:52.17#ibcon#[25=USB\r\n] 2006.285.19:14:52.17#ibcon#*before write, iclass 7, count 0 2006.285.19:14:52.17#ibcon#enter sib2, iclass 7, count 0 2006.285.19:14:52.17#ibcon#flushed, iclass 7, count 0 2006.285.19:14:52.17#ibcon#about to write, iclass 7, count 0 2006.285.19:14:52.17#ibcon#wrote, iclass 7, count 0 2006.285.19:14:52.17#ibcon#about to read 3, iclass 7, count 0 2006.285.19:14:52.20#ibcon#read 3, iclass 7, count 0 2006.285.19:14:52.20#ibcon#about to read 4, iclass 7, count 0 2006.285.19:14:52.20#ibcon#read 4, iclass 7, count 0 2006.285.19:14:52.20#ibcon#about to read 5, iclass 7, count 0 2006.285.19:14:52.20#ibcon#read 5, iclass 7, count 0 2006.285.19:14:52.20#ibcon#about to read 6, iclass 7, count 0 2006.285.19:14:52.20#ibcon#read 6, iclass 7, count 0 2006.285.19:14:52.20#ibcon#end of sib2, iclass 7, count 0 2006.285.19:14:52.20#ibcon#*after write, iclass 7, count 0 2006.285.19:14:52.20#ibcon#*before return 0, iclass 7, count 0 2006.285.19:14:52.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:14:52.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:14:52.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.19:14:52.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.19:14:52.20$vck44/valo=7,864.99 2006.285.19:14:52.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.19:14:52.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.19:14:52.20#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:52.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:14:52.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:14:52.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:14:52.20#ibcon#enter wrdev, iclass 11, count 0 2006.285.19:14:52.20#ibcon#first serial, iclass 11, count 0 2006.285.19:14:52.20#ibcon#enter sib2, iclass 11, count 0 2006.285.19:14:52.20#ibcon#flushed, iclass 11, count 0 2006.285.19:14:52.20#ibcon#about to write, iclass 11, count 0 2006.285.19:14:52.20#ibcon#wrote, iclass 11, count 0 2006.285.19:14:52.20#ibcon#about to read 3, iclass 11, count 0 2006.285.19:14:52.22#ibcon#read 3, iclass 11, count 0 2006.285.19:14:52.22#ibcon#about to read 4, iclass 11, count 0 2006.285.19:14:52.22#ibcon#read 4, iclass 11, count 0 2006.285.19:14:52.32#ibcon#about to read 5, iclass 11, count 0 2006.285.19:14:52.32#ibcon#read 5, iclass 11, count 0 2006.285.19:14:52.32#ibcon#about to read 6, iclass 11, count 0 2006.285.19:14:52.32#ibcon#read 6, iclass 11, count 0 2006.285.19:14:52.32#ibcon#end of sib2, iclass 11, count 0 2006.285.19:14:52.32#ibcon#*mode == 0, iclass 11, count 0 2006.285.19:14:52.32#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.19:14:52.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.19:14:52.32#ibcon#*before write, iclass 11, count 0 2006.285.19:14:52.32#ibcon#enter sib2, iclass 11, count 0 2006.285.19:14:52.32#ibcon#flushed, iclass 11, count 0 2006.285.19:14:52.32#ibcon#about to write, iclass 11, count 0 2006.285.19:14:52.32#ibcon#wrote, iclass 11, count 0 2006.285.19:14:52.32#ibcon#about to read 3, iclass 11, count 0 2006.285.19:14:52.36#ibcon#read 3, iclass 11, count 0 2006.285.19:14:52.36#ibcon#about to read 4, iclass 11, count 0 2006.285.19:14:52.36#ibcon#read 4, iclass 11, count 0 2006.285.19:14:52.36#ibcon#about to read 5, iclass 11, count 0 2006.285.19:14:52.36#ibcon#read 5, iclass 11, count 0 2006.285.19:14:52.36#ibcon#about to read 6, iclass 11, count 0 2006.285.19:14:52.36#ibcon#read 6, iclass 11, count 0 2006.285.19:14:52.36#ibcon#end of sib2, iclass 11, count 0 2006.285.19:14:52.36#ibcon#*after write, iclass 11, count 0 2006.285.19:14:52.36#ibcon#*before return 0, iclass 11, count 0 2006.285.19:14:52.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:14:52.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:14:52.36#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.19:14:52.36#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.19:14:52.36$vck44/va=7,4 2006.285.19:14:52.36#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.19:14:52.36#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.19:14:52.36#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:52.36#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:14:52.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:14:52.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:14:52.36#ibcon#enter wrdev, iclass 13, count 2 2006.285.19:14:52.36#ibcon#first serial, iclass 13, count 2 2006.285.19:14:52.36#ibcon#enter sib2, iclass 13, count 2 2006.285.19:14:52.36#ibcon#flushed, iclass 13, count 2 2006.285.19:14:52.36#ibcon#about to write, iclass 13, count 2 2006.285.19:14:52.36#ibcon#wrote, iclass 13, count 2 2006.285.19:14:52.36#ibcon#about to read 3, iclass 13, count 2 2006.285.19:14:52.38#ibcon#read 3, iclass 13, count 2 2006.285.19:14:52.38#ibcon#about to read 4, iclass 13, count 2 2006.285.19:14:52.38#ibcon#read 4, iclass 13, count 2 2006.285.19:14:52.38#ibcon#about to read 5, iclass 13, count 2 2006.285.19:14:52.38#ibcon#read 5, iclass 13, count 2 2006.285.19:14:52.38#ibcon#about to read 6, iclass 13, count 2 2006.285.19:14:52.38#ibcon#read 6, iclass 13, count 2 2006.285.19:14:52.38#ibcon#end of sib2, iclass 13, count 2 2006.285.19:14:52.38#ibcon#*mode == 0, iclass 13, count 2 2006.285.19:14:52.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.19:14:52.38#ibcon#[25=AT07-04\r\n] 2006.285.19:14:52.38#ibcon#*before write, iclass 13, count 2 2006.285.19:14:52.38#ibcon#enter sib2, iclass 13, count 2 2006.285.19:14:52.38#ibcon#flushed, iclass 13, count 2 2006.285.19:14:52.38#ibcon#about to write, iclass 13, count 2 2006.285.19:14:52.38#ibcon#wrote, iclass 13, count 2 2006.285.19:14:52.38#ibcon#about to read 3, iclass 13, count 2 2006.285.19:14:52.41#ibcon#read 3, iclass 13, count 2 2006.285.19:14:52.41#ibcon#about to read 4, iclass 13, count 2 2006.285.19:14:52.41#ibcon#read 4, iclass 13, count 2 2006.285.19:14:52.41#ibcon#about to read 5, iclass 13, count 2 2006.285.19:14:52.41#ibcon#read 5, iclass 13, count 2 2006.285.19:14:52.41#ibcon#about to read 6, iclass 13, count 2 2006.285.19:14:52.41#ibcon#read 6, iclass 13, count 2 2006.285.19:14:52.41#ibcon#end of sib2, iclass 13, count 2 2006.285.19:14:52.41#ibcon#*after write, iclass 13, count 2 2006.285.19:14:52.41#ibcon#*before return 0, iclass 13, count 2 2006.285.19:14:52.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:14:52.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:14:52.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.19:14:52.41#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:52.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:14:52.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:14:52.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:14:52.53#ibcon#enter wrdev, iclass 13, count 0 2006.285.19:14:52.53#ibcon#first serial, iclass 13, count 0 2006.285.19:14:52.53#ibcon#enter sib2, iclass 13, count 0 2006.285.19:14:52.53#ibcon#flushed, iclass 13, count 0 2006.285.19:14:52.53#ibcon#about to write, iclass 13, count 0 2006.285.19:14:52.53#ibcon#wrote, iclass 13, count 0 2006.285.19:14:52.53#ibcon#about to read 3, iclass 13, count 0 2006.285.19:14:52.55#ibcon#read 3, iclass 13, count 0 2006.285.19:14:52.55#ibcon#about to read 4, iclass 13, count 0 2006.285.19:14:52.55#ibcon#read 4, iclass 13, count 0 2006.285.19:14:52.55#ibcon#about to read 5, iclass 13, count 0 2006.285.19:14:52.55#ibcon#read 5, iclass 13, count 0 2006.285.19:14:52.55#ibcon#about to read 6, iclass 13, count 0 2006.285.19:14:52.55#ibcon#read 6, iclass 13, count 0 2006.285.19:14:52.55#ibcon#end of sib2, iclass 13, count 0 2006.285.19:14:52.55#ibcon#*mode == 0, iclass 13, count 0 2006.285.19:14:52.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.19:14:52.55#ibcon#[25=USB\r\n] 2006.285.19:14:52.55#ibcon#*before write, iclass 13, count 0 2006.285.19:14:52.55#ibcon#enter sib2, iclass 13, count 0 2006.285.19:14:52.55#ibcon#flushed, iclass 13, count 0 2006.285.19:14:52.55#ibcon#about to write, iclass 13, count 0 2006.285.19:14:52.55#ibcon#wrote, iclass 13, count 0 2006.285.19:14:52.55#ibcon#about to read 3, iclass 13, count 0 2006.285.19:14:52.58#ibcon#read 3, iclass 13, count 0 2006.285.19:14:52.58#ibcon#about to read 4, iclass 13, count 0 2006.285.19:14:52.58#ibcon#read 4, iclass 13, count 0 2006.285.19:14:52.58#ibcon#about to read 5, iclass 13, count 0 2006.285.19:14:52.58#ibcon#read 5, iclass 13, count 0 2006.285.19:14:52.58#ibcon#about to read 6, iclass 13, count 0 2006.285.19:14:52.58#ibcon#read 6, iclass 13, count 0 2006.285.19:14:52.58#ibcon#end of sib2, iclass 13, count 0 2006.285.19:14:52.58#ibcon#*after write, iclass 13, count 0 2006.285.19:14:52.58#ibcon#*before return 0, iclass 13, count 0 2006.285.19:14:52.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:14:52.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:14:52.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.19:14:52.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.19:14:52.58$vck44/valo=8,884.99 2006.285.19:14:52.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.19:14:52.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.19:14:52.58#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:52.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:14:52.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:14:52.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:14:52.58#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:14:52.58#ibcon#first serial, iclass 15, count 0 2006.285.19:14:52.58#ibcon#enter sib2, iclass 15, count 0 2006.285.19:14:52.58#ibcon#flushed, iclass 15, count 0 2006.285.19:14:52.58#ibcon#about to write, iclass 15, count 0 2006.285.19:14:52.58#ibcon#wrote, iclass 15, count 0 2006.285.19:14:52.58#ibcon#about to read 3, iclass 15, count 0 2006.285.19:14:52.60#ibcon#read 3, iclass 15, count 0 2006.285.19:14:52.60#ibcon#about to read 4, iclass 15, count 0 2006.285.19:14:52.60#ibcon#read 4, iclass 15, count 0 2006.285.19:14:52.60#ibcon#about to read 5, iclass 15, count 0 2006.285.19:14:52.60#ibcon#read 5, iclass 15, count 0 2006.285.19:14:52.60#ibcon#about to read 6, iclass 15, count 0 2006.285.19:14:52.60#ibcon#read 6, iclass 15, count 0 2006.285.19:14:52.60#ibcon#end of sib2, iclass 15, count 0 2006.285.19:14:52.60#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:14:52.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:14:52.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.19:14:52.60#ibcon#*before write, iclass 15, count 0 2006.285.19:14:52.60#ibcon#enter sib2, iclass 15, count 0 2006.285.19:14:52.60#ibcon#flushed, iclass 15, count 0 2006.285.19:14:52.60#ibcon#about to write, iclass 15, count 0 2006.285.19:14:52.60#ibcon#wrote, iclass 15, count 0 2006.285.19:14:52.60#ibcon#about to read 3, iclass 15, count 0 2006.285.19:14:52.64#ibcon#read 3, iclass 15, count 0 2006.285.19:14:52.64#ibcon#about to read 4, iclass 15, count 0 2006.285.19:14:52.64#ibcon#read 4, iclass 15, count 0 2006.285.19:14:52.64#ibcon#about to read 5, iclass 15, count 0 2006.285.19:14:52.64#ibcon#read 5, iclass 15, count 0 2006.285.19:14:52.64#ibcon#about to read 6, iclass 15, count 0 2006.285.19:14:52.64#ibcon#read 6, iclass 15, count 0 2006.285.19:14:52.64#ibcon#end of sib2, iclass 15, count 0 2006.285.19:14:52.64#ibcon#*after write, iclass 15, count 0 2006.285.19:14:52.64#ibcon#*before return 0, iclass 15, count 0 2006.285.19:14:52.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:14:52.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:14:52.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:14:52.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:14:52.64$vck44/va=8,3 2006.285.19:14:52.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.19:14:52.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.19:14:52.64#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:52.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:14:52.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:14:52.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:14:52.70#ibcon#enter wrdev, iclass 17, count 2 2006.285.19:14:52.70#ibcon#first serial, iclass 17, count 2 2006.285.19:14:52.70#ibcon#enter sib2, iclass 17, count 2 2006.285.19:14:52.70#ibcon#flushed, iclass 17, count 2 2006.285.19:14:52.70#ibcon#about to write, iclass 17, count 2 2006.285.19:14:52.70#ibcon#wrote, iclass 17, count 2 2006.285.19:14:52.70#ibcon#about to read 3, iclass 17, count 2 2006.285.19:14:52.72#ibcon#read 3, iclass 17, count 2 2006.285.19:14:52.72#ibcon#about to read 4, iclass 17, count 2 2006.285.19:14:52.72#ibcon#read 4, iclass 17, count 2 2006.285.19:14:52.72#ibcon#about to read 5, iclass 17, count 2 2006.285.19:14:52.72#ibcon#read 5, iclass 17, count 2 2006.285.19:14:52.72#ibcon#about to read 6, iclass 17, count 2 2006.285.19:14:52.72#ibcon#read 6, iclass 17, count 2 2006.285.19:14:52.72#ibcon#end of sib2, iclass 17, count 2 2006.285.19:14:52.72#ibcon#*mode == 0, iclass 17, count 2 2006.285.19:14:52.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.19:14:52.72#ibcon#[25=AT08-03\r\n] 2006.285.19:14:52.72#ibcon#*before write, iclass 17, count 2 2006.285.19:14:52.72#ibcon#enter sib2, iclass 17, count 2 2006.285.19:14:52.72#ibcon#flushed, iclass 17, count 2 2006.285.19:14:52.72#ibcon#about to write, iclass 17, count 2 2006.285.19:14:52.72#ibcon#wrote, iclass 17, count 2 2006.285.19:14:52.72#ibcon#about to read 3, iclass 17, count 2 2006.285.19:14:52.75#ibcon#read 3, iclass 17, count 2 2006.285.19:14:52.75#ibcon#about to read 4, iclass 17, count 2 2006.285.19:14:52.75#ibcon#read 4, iclass 17, count 2 2006.285.19:14:52.75#ibcon#about to read 5, iclass 17, count 2 2006.285.19:14:52.75#ibcon#read 5, iclass 17, count 2 2006.285.19:14:52.75#ibcon#about to read 6, iclass 17, count 2 2006.285.19:14:52.75#ibcon#read 6, iclass 17, count 2 2006.285.19:14:52.75#ibcon#end of sib2, iclass 17, count 2 2006.285.19:14:52.75#ibcon#*after write, iclass 17, count 2 2006.285.19:14:52.75#ibcon#*before return 0, iclass 17, count 2 2006.285.19:14:52.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:14:52.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:14:52.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.19:14:52.75#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:52.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:14:52.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:14:52.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:14:52.87#ibcon#enter wrdev, iclass 17, count 0 2006.285.19:14:52.87#ibcon#first serial, iclass 17, count 0 2006.285.19:14:52.87#ibcon#enter sib2, iclass 17, count 0 2006.285.19:14:52.87#ibcon#flushed, iclass 17, count 0 2006.285.19:14:52.87#ibcon#about to write, iclass 17, count 0 2006.285.19:14:52.87#ibcon#wrote, iclass 17, count 0 2006.285.19:14:52.87#ibcon#about to read 3, iclass 17, count 0 2006.285.19:14:52.89#ibcon#read 3, iclass 17, count 0 2006.285.19:14:52.89#ibcon#about to read 4, iclass 17, count 0 2006.285.19:14:52.89#ibcon#read 4, iclass 17, count 0 2006.285.19:14:52.89#ibcon#about to read 5, iclass 17, count 0 2006.285.19:14:52.89#ibcon#read 5, iclass 17, count 0 2006.285.19:14:52.89#ibcon#about to read 6, iclass 17, count 0 2006.285.19:14:52.89#ibcon#read 6, iclass 17, count 0 2006.285.19:14:52.89#ibcon#end of sib2, iclass 17, count 0 2006.285.19:14:52.89#ibcon#*mode == 0, iclass 17, count 0 2006.285.19:14:52.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.19:14:52.89#ibcon#[25=USB\r\n] 2006.285.19:14:52.89#ibcon#*before write, iclass 17, count 0 2006.285.19:14:52.89#ibcon#enter sib2, iclass 17, count 0 2006.285.19:14:52.89#ibcon#flushed, iclass 17, count 0 2006.285.19:14:52.89#ibcon#about to write, iclass 17, count 0 2006.285.19:14:52.89#ibcon#wrote, iclass 17, count 0 2006.285.19:14:52.89#ibcon#about to read 3, iclass 17, count 0 2006.285.19:14:52.92#ibcon#read 3, iclass 17, count 0 2006.285.19:14:52.92#ibcon#about to read 4, iclass 17, count 0 2006.285.19:14:52.92#ibcon#read 4, iclass 17, count 0 2006.285.19:14:52.92#ibcon#about to read 5, iclass 17, count 0 2006.285.19:14:52.92#ibcon#read 5, iclass 17, count 0 2006.285.19:14:52.92#ibcon#about to read 6, iclass 17, count 0 2006.285.19:14:52.92#ibcon#read 6, iclass 17, count 0 2006.285.19:14:52.92#ibcon#end of sib2, iclass 17, count 0 2006.285.19:14:52.92#ibcon#*after write, iclass 17, count 0 2006.285.19:14:52.92#ibcon#*before return 0, iclass 17, count 0 2006.285.19:14:52.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:14:52.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:14:52.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.19:14:52.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.19:14:52.92$vck44/vblo=1,629.99 2006.285.19:14:52.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.19:14:52.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.19:14:52.92#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:52.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:14:52.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:14:52.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:14:52.92#ibcon#enter wrdev, iclass 19, count 0 2006.285.19:14:52.92#ibcon#first serial, iclass 19, count 0 2006.285.19:14:52.92#ibcon#enter sib2, iclass 19, count 0 2006.285.19:14:52.92#ibcon#flushed, iclass 19, count 0 2006.285.19:14:52.92#ibcon#about to write, iclass 19, count 0 2006.285.19:14:52.92#ibcon#wrote, iclass 19, count 0 2006.285.19:14:52.92#ibcon#about to read 3, iclass 19, count 0 2006.285.19:14:52.94#ibcon#read 3, iclass 19, count 0 2006.285.19:14:52.94#ibcon#about to read 4, iclass 19, count 0 2006.285.19:14:52.94#ibcon#read 4, iclass 19, count 0 2006.285.19:14:52.94#ibcon#about to read 5, iclass 19, count 0 2006.285.19:14:52.94#ibcon#read 5, iclass 19, count 0 2006.285.19:14:52.94#ibcon#about to read 6, iclass 19, count 0 2006.285.19:14:52.94#ibcon#read 6, iclass 19, count 0 2006.285.19:14:52.94#ibcon#end of sib2, iclass 19, count 0 2006.285.19:14:52.94#ibcon#*mode == 0, iclass 19, count 0 2006.285.19:14:52.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.19:14:52.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.19:14:52.94#ibcon#*before write, iclass 19, count 0 2006.285.19:14:52.94#ibcon#enter sib2, iclass 19, count 0 2006.285.19:14:52.94#ibcon#flushed, iclass 19, count 0 2006.285.19:14:52.94#ibcon#about to write, iclass 19, count 0 2006.285.19:14:52.94#ibcon#wrote, iclass 19, count 0 2006.285.19:14:52.94#ibcon#about to read 3, iclass 19, count 0 2006.285.19:14:52.98#ibcon#read 3, iclass 19, count 0 2006.285.19:14:52.98#ibcon#about to read 4, iclass 19, count 0 2006.285.19:14:52.98#ibcon#read 4, iclass 19, count 0 2006.285.19:14:52.98#ibcon#about to read 5, iclass 19, count 0 2006.285.19:14:52.98#ibcon#read 5, iclass 19, count 0 2006.285.19:14:52.98#ibcon#about to read 6, iclass 19, count 0 2006.285.19:14:52.98#ibcon#read 6, iclass 19, count 0 2006.285.19:14:52.98#ibcon#end of sib2, iclass 19, count 0 2006.285.19:14:52.98#ibcon#*after write, iclass 19, count 0 2006.285.19:14:52.98#ibcon#*before return 0, iclass 19, count 0 2006.285.19:14:52.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:14:52.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:14:52.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.19:14:52.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.19:14:52.98$vck44/vb=1,4 2006.285.19:14:52.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.19:14:52.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.19:14:52.98#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:52.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:14:52.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:14:52.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:14:52.98#ibcon#enter wrdev, iclass 21, count 2 2006.285.19:14:52.98#ibcon#first serial, iclass 21, count 2 2006.285.19:14:52.98#ibcon#enter sib2, iclass 21, count 2 2006.285.19:14:52.98#ibcon#flushed, iclass 21, count 2 2006.285.19:14:52.98#ibcon#about to write, iclass 21, count 2 2006.285.19:14:52.98#ibcon#wrote, iclass 21, count 2 2006.285.19:14:52.98#ibcon#about to read 3, iclass 21, count 2 2006.285.19:14:53.00#ibcon#read 3, iclass 21, count 2 2006.285.19:14:53.00#ibcon#about to read 4, iclass 21, count 2 2006.285.19:14:53.00#ibcon#read 4, iclass 21, count 2 2006.285.19:14:53.00#ibcon#about to read 5, iclass 21, count 2 2006.285.19:14:53.00#ibcon#read 5, iclass 21, count 2 2006.285.19:14:53.00#ibcon#about to read 6, iclass 21, count 2 2006.285.19:14:53.00#ibcon#read 6, iclass 21, count 2 2006.285.19:14:53.00#ibcon#end of sib2, iclass 21, count 2 2006.285.19:14:53.00#ibcon#*mode == 0, iclass 21, count 2 2006.285.19:14:53.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.19:14:53.00#ibcon#[27=AT01-04\r\n] 2006.285.19:14:53.00#ibcon#*before write, iclass 21, count 2 2006.285.19:14:53.00#ibcon#enter sib2, iclass 21, count 2 2006.285.19:14:53.00#ibcon#flushed, iclass 21, count 2 2006.285.19:14:53.00#ibcon#about to write, iclass 21, count 2 2006.285.19:14:53.00#ibcon#wrote, iclass 21, count 2 2006.285.19:14:53.00#ibcon#about to read 3, iclass 21, count 2 2006.285.19:14:53.03#ibcon#read 3, iclass 21, count 2 2006.285.19:14:53.03#ibcon#about to read 4, iclass 21, count 2 2006.285.19:14:53.03#ibcon#read 4, iclass 21, count 2 2006.285.19:14:53.03#ibcon#about to read 5, iclass 21, count 2 2006.285.19:14:53.03#ibcon#read 5, iclass 21, count 2 2006.285.19:14:53.03#ibcon#about to read 6, iclass 21, count 2 2006.285.19:14:53.03#ibcon#read 6, iclass 21, count 2 2006.285.19:14:53.03#ibcon#end of sib2, iclass 21, count 2 2006.285.19:14:53.03#ibcon#*after write, iclass 21, count 2 2006.285.19:14:53.03#ibcon#*before return 0, iclass 21, count 2 2006.285.19:14:53.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:14:53.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:14:53.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.19:14:53.03#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:53.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:14:53.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:14:53.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:14:53.15#ibcon#enter wrdev, iclass 21, count 0 2006.285.19:14:53.15#ibcon#first serial, iclass 21, count 0 2006.285.19:14:53.15#ibcon#enter sib2, iclass 21, count 0 2006.285.19:14:53.15#ibcon#flushed, iclass 21, count 0 2006.285.19:14:53.15#ibcon#about to write, iclass 21, count 0 2006.285.19:14:53.15#ibcon#wrote, iclass 21, count 0 2006.285.19:14:53.15#ibcon#about to read 3, iclass 21, count 0 2006.285.19:14:53.17#ibcon#read 3, iclass 21, count 0 2006.285.19:14:53.17#ibcon#about to read 4, iclass 21, count 0 2006.285.19:14:53.17#ibcon#read 4, iclass 21, count 0 2006.285.19:14:53.17#ibcon#about to read 5, iclass 21, count 0 2006.285.19:14:53.17#ibcon#read 5, iclass 21, count 0 2006.285.19:14:53.17#ibcon#about to read 6, iclass 21, count 0 2006.285.19:14:53.17#ibcon#read 6, iclass 21, count 0 2006.285.19:14:53.17#ibcon#end of sib2, iclass 21, count 0 2006.285.19:14:53.17#ibcon#*mode == 0, iclass 21, count 0 2006.285.19:14:53.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.19:14:53.17#ibcon#[27=USB\r\n] 2006.285.19:14:53.17#ibcon#*before write, iclass 21, count 0 2006.285.19:14:53.17#ibcon#enter sib2, iclass 21, count 0 2006.285.19:14:53.17#ibcon#flushed, iclass 21, count 0 2006.285.19:14:53.17#ibcon#about to write, iclass 21, count 0 2006.285.19:14:53.17#ibcon#wrote, iclass 21, count 0 2006.285.19:14:53.17#ibcon#about to read 3, iclass 21, count 0 2006.285.19:14:53.20#ibcon#read 3, iclass 21, count 0 2006.285.19:14:53.20#ibcon#about to read 4, iclass 21, count 0 2006.285.19:14:53.20#ibcon#read 4, iclass 21, count 0 2006.285.19:14:53.20#ibcon#about to read 5, iclass 21, count 0 2006.285.19:14:53.20#ibcon#read 5, iclass 21, count 0 2006.285.19:14:53.20#ibcon#about to read 6, iclass 21, count 0 2006.285.19:14:53.20#ibcon#read 6, iclass 21, count 0 2006.285.19:14:53.20#ibcon#end of sib2, iclass 21, count 0 2006.285.19:14:53.20#ibcon#*after write, iclass 21, count 0 2006.285.19:14:53.20#ibcon#*before return 0, iclass 21, count 0 2006.285.19:14:53.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:14:53.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:14:53.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.19:14:53.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.19:14:53.20$vck44/vblo=2,634.99 2006.285.19:14:53.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.19:14:53.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.19:14:53.20#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:53.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:14:53.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:14:53.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:14:53.20#ibcon#enter wrdev, iclass 23, count 0 2006.285.19:14:53.20#ibcon#first serial, iclass 23, count 0 2006.285.19:14:53.20#ibcon#enter sib2, iclass 23, count 0 2006.285.19:14:53.20#ibcon#flushed, iclass 23, count 0 2006.285.19:14:53.20#ibcon#about to write, iclass 23, count 0 2006.285.19:14:53.20#ibcon#wrote, iclass 23, count 0 2006.285.19:14:53.20#ibcon#about to read 3, iclass 23, count 0 2006.285.19:14:53.22#ibcon#read 3, iclass 23, count 0 2006.285.19:14:53.22#ibcon#about to read 4, iclass 23, count 0 2006.285.19:14:53.22#ibcon#read 4, iclass 23, count 0 2006.285.19:14:53.22#ibcon#about to read 5, iclass 23, count 0 2006.285.19:14:53.22#ibcon#read 5, iclass 23, count 0 2006.285.19:14:53.22#ibcon#about to read 6, iclass 23, count 0 2006.285.19:14:53.22#ibcon#read 6, iclass 23, count 0 2006.285.19:14:53.22#ibcon#end of sib2, iclass 23, count 0 2006.285.19:14:53.22#ibcon#*mode == 0, iclass 23, count 0 2006.285.19:14:53.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.19:14:53.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.19:14:53.22#ibcon#*before write, iclass 23, count 0 2006.285.19:14:53.22#ibcon#enter sib2, iclass 23, count 0 2006.285.19:14:53.22#ibcon#flushed, iclass 23, count 0 2006.285.19:14:53.22#ibcon#about to write, iclass 23, count 0 2006.285.19:14:53.22#ibcon#wrote, iclass 23, count 0 2006.285.19:14:53.22#ibcon#about to read 3, iclass 23, count 0 2006.285.19:14:53.26#ibcon#read 3, iclass 23, count 0 2006.285.19:14:53.26#ibcon#about to read 4, iclass 23, count 0 2006.285.19:14:53.26#ibcon#read 4, iclass 23, count 0 2006.285.19:14:53.26#ibcon#about to read 5, iclass 23, count 0 2006.285.19:14:53.26#ibcon#read 5, iclass 23, count 0 2006.285.19:14:53.26#ibcon#about to read 6, iclass 23, count 0 2006.285.19:14:53.26#ibcon#read 6, iclass 23, count 0 2006.285.19:14:53.26#ibcon#end of sib2, iclass 23, count 0 2006.285.19:14:53.26#ibcon#*after write, iclass 23, count 0 2006.285.19:14:53.26#ibcon#*before return 0, iclass 23, count 0 2006.285.19:14:53.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:14:53.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:14:53.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.19:14:53.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.19:14:53.26$vck44/vb=2,5 2006.285.19:14:53.67#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.19:14:53.67#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.19:14:53.67#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:53.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:14:53.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:14:53.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:14:53.67#ibcon#enter wrdev, iclass 25, count 2 2006.285.19:14:53.67#ibcon#first serial, iclass 25, count 2 2006.285.19:14:53.67#ibcon#enter sib2, iclass 25, count 2 2006.285.19:14:53.67#ibcon#flushed, iclass 25, count 2 2006.285.19:14:53.67#ibcon#about to write, iclass 25, count 2 2006.285.19:14:53.67#ibcon#wrote, iclass 25, count 2 2006.285.19:14:53.67#ibcon#about to read 3, iclass 25, count 2 2006.285.19:14:53.69#ibcon#read 3, iclass 25, count 2 2006.285.19:14:53.69#ibcon#about to read 4, iclass 25, count 2 2006.285.19:14:53.69#ibcon#read 4, iclass 25, count 2 2006.285.19:14:53.69#ibcon#about to read 5, iclass 25, count 2 2006.285.19:14:53.69#ibcon#read 5, iclass 25, count 2 2006.285.19:14:53.69#ibcon#about to read 6, iclass 25, count 2 2006.285.19:14:53.69#ibcon#read 6, iclass 25, count 2 2006.285.19:14:53.69#ibcon#end of sib2, iclass 25, count 2 2006.285.19:14:53.69#ibcon#*mode == 0, iclass 25, count 2 2006.285.19:14:53.69#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.19:14:53.69#ibcon#[27=AT02-05\r\n] 2006.285.19:14:53.69#ibcon#*before write, iclass 25, count 2 2006.285.19:14:53.69#ibcon#enter sib2, iclass 25, count 2 2006.285.19:14:53.69#ibcon#flushed, iclass 25, count 2 2006.285.19:14:53.69#ibcon#about to write, iclass 25, count 2 2006.285.19:14:53.69#ibcon#wrote, iclass 25, count 2 2006.285.19:14:53.69#ibcon#about to read 3, iclass 25, count 2 2006.285.19:14:53.72#abcon#<5=/15 1.0 1.6 15.011001014.9\r\n> 2006.285.19:14:53.72#ibcon#read 3, iclass 25, count 2 2006.285.19:14:53.72#ibcon#about to read 4, iclass 25, count 2 2006.285.19:14:53.72#ibcon#read 4, iclass 25, count 2 2006.285.19:14:53.72#ibcon#about to read 5, iclass 25, count 2 2006.285.19:14:53.72#ibcon#read 5, iclass 25, count 2 2006.285.19:14:53.72#ibcon#about to read 6, iclass 25, count 2 2006.285.19:14:53.72#ibcon#read 6, iclass 25, count 2 2006.285.19:14:53.72#ibcon#end of sib2, iclass 25, count 2 2006.285.19:14:53.72#ibcon#*after write, iclass 25, count 2 2006.285.19:14:53.72#ibcon#*before return 0, iclass 25, count 2 2006.285.19:14:53.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:14:53.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:14:53.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.19:14:53.72#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:53.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:14:53.74#abcon#{5=INTERFACE CLEAR} 2006.285.19:14:53.80#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:14:53.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:14:53.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:14:53.84#ibcon#enter wrdev, iclass 25, count 0 2006.285.19:14:53.84#ibcon#first serial, iclass 25, count 0 2006.285.19:14:53.84#ibcon#enter sib2, iclass 25, count 0 2006.285.19:14:53.84#ibcon#flushed, iclass 25, count 0 2006.285.19:14:53.84#ibcon#about to write, iclass 25, count 0 2006.285.19:14:53.84#ibcon#wrote, iclass 25, count 0 2006.285.19:14:53.84#ibcon#about to read 3, iclass 25, count 0 2006.285.19:14:53.86#ibcon#read 3, iclass 25, count 0 2006.285.19:14:53.86#ibcon#about to read 4, iclass 25, count 0 2006.285.19:14:53.86#ibcon#read 4, iclass 25, count 0 2006.285.19:14:53.86#ibcon#about to read 5, iclass 25, count 0 2006.285.19:14:53.86#ibcon#read 5, iclass 25, count 0 2006.285.19:14:53.86#ibcon#about to read 6, iclass 25, count 0 2006.285.19:14:53.86#ibcon#read 6, iclass 25, count 0 2006.285.19:14:53.86#ibcon#end of sib2, iclass 25, count 0 2006.285.19:14:53.86#ibcon#*mode == 0, iclass 25, count 0 2006.285.19:14:53.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.19:14:53.86#ibcon#[27=USB\r\n] 2006.285.19:14:53.86#ibcon#*before write, iclass 25, count 0 2006.285.19:14:53.86#ibcon#enter sib2, iclass 25, count 0 2006.285.19:14:53.86#ibcon#flushed, iclass 25, count 0 2006.285.19:14:53.86#ibcon#about to write, iclass 25, count 0 2006.285.19:14:53.86#ibcon#wrote, iclass 25, count 0 2006.285.19:14:53.86#ibcon#about to read 3, iclass 25, count 0 2006.285.19:14:53.89#ibcon#read 3, iclass 25, count 0 2006.285.19:14:53.89#ibcon#about to read 4, iclass 25, count 0 2006.285.19:14:53.89#ibcon#read 4, iclass 25, count 0 2006.285.19:14:53.89#ibcon#about to read 5, iclass 25, count 0 2006.285.19:14:53.89#ibcon#read 5, iclass 25, count 0 2006.285.19:14:53.89#ibcon#about to read 6, iclass 25, count 0 2006.285.19:14:53.89#ibcon#read 6, iclass 25, count 0 2006.285.19:14:53.89#ibcon#end of sib2, iclass 25, count 0 2006.285.19:14:53.89#ibcon#*after write, iclass 25, count 0 2006.285.19:14:53.89#ibcon#*before return 0, iclass 25, count 0 2006.285.19:14:53.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:14:53.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:14:53.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.19:14:53.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.19:14:53.89$vck44/vblo=3,649.99 2006.285.19:14:53.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.19:14:53.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.19:14:53.89#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:53.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:14:53.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:14:53.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:14:53.89#ibcon#enter wrdev, iclass 31, count 0 2006.285.19:14:53.89#ibcon#first serial, iclass 31, count 0 2006.285.19:14:53.89#ibcon#enter sib2, iclass 31, count 0 2006.285.19:14:53.89#ibcon#flushed, iclass 31, count 0 2006.285.19:14:53.89#ibcon#about to write, iclass 31, count 0 2006.285.19:14:53.89#ibcon#wrote, iclass 31, count 0 2006.285.19:14:53.89#ibcon#about to read 3, iclass 31, count 0 2006.285.19:14:53.91#ibcon#read 3, iclass 31, count 0 2006.285.19:14:53.91#ibcon#about to read 4, iclass 31, count 0 2006.285.19:14:53.91#ibcon#read 4, iclass 31, count 0 2006.285.19:14:53.91#ibcon#about to read 5, iclass 31, count 0 2006.285.19:14:53.91#ibcon#read 5, iclass 31, count 0 2006.285.19:14:53.91#ibcon#about to read 6, iclass 31, count 0 2006.285.19:14:53.91#ibcon#read 6, iclass 31, count 0 2006.285.19:14:53.91#ibcon#end of sib2, iclass 31, count 0 2006.285.19:14:53.91#ibcon#*mode == 0, iclass 31, count 0 2006.285.19:14:53.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.19:14:53.91#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.19:14:53.91#ibcon#*before write, iclass 31, count 0 2006.285.19:14:53.91#ibcon#enter sib2, iclass 31, count 0 2006.285.19:14:53.91#ibcon#flushed, iclass 31, count 0 2006.285.19:14:53.91#ibcon#about to write, iclass 31, count 0 2006.285.19:14:53.91#ibcon#wrote, iclass 31, count 0 2006.285.19:14:53.91#ibcon#about to read 3, iclass 31, count 0 2006.285.19:14:53.95#ibcon#read 3, iclass 31, count 0 2006.285.19:14:53.95#ibcon#about to read 4, iclass 31, count 0 2006.285.19:14:53.95#ibcon#read 4, iclass 31, count 0 2006.285.19:14:53.95#ibcon#about to read 5, iclass 31, count 0 2006.285.19:14:53.95#ibcon#read 5, iclass 31, count 0 2006.285.19:14:53.95#ibcon#about to read 6, iclass 31, count 0 2006.285.19:14:53.95#ibcon#read 6, iclass 31, count 0 2006.285.19:14:53.95#ibcon#end of sib2, iclass 31, count 0 2006.285.19:14:53.95#ibcon#*after write, iclass 31, count 0 2006.285.19:14:53.95#ibcon#*before return 0, iclass 31, count 0 2006.285.19:14:53.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:14:53.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:14:53.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.19:14:53.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.19:14:53.95$vck44/vb=3,4 2006.285.19:14:53.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.19:14:53.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.19:14:53.95#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:53.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:14:54.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:14:54.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:14:54.01#ibcon#enter wrdev, iclass 33, count 2 2006.285.19:14:54.01#ibcon#first serial, iclass 33, count 2 2006.285.19:14:54.01#ibcon#enter sib2, iclass 33, count 2 2006.285.19:14:54.01#ibcon#flushed, iclass 33, count 2 2006.285.19:14:54.01#ibcon#about to write, iclass 33, count 2 2006.285.19:14:54.01#ibcon#wrote, iclass 33, count 2 2006.285.19:14:54.01#ibcon#about to read 3, iclass 33, count 2 2006.285.19:14:54.03#ibcon#read 3, iclass 33, count 2 2006.285.19:14:54.03#ibcon#about to read 4, iclass 33, count 2 2006.285.19:14:54.03#ibcon#read 4, iclass 33, count 2 2006.285.19:14:54.03#ibcon#about to read 5, iclass 33, count 2 2006.285.19:14:54.03#ibcon#read 5, iclass 33, count 2 2006.285.19:14:54.03#ibcon#about to read 6, iclass 33, count 2 2006.285.19:14:54.03#ibcon#read 6, iclass 33, count 2 2006.285.19:14:54.03#ibcon#end of sib2, iclass 33, count 2 2006.285.19:14:54.03#ibcon#*mode == 0, iclass 33, count 2 2006.285.19:14:54.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.19:14:54.03#ibcon#[27=AT03-04\r\n] 2006.285.19:14:54.03#ibcon#*before write, iclass 33, count 2 2006.285.19:14:54.03#ibcon#enter sib2, iclass 33, count 2 2006.285.19:14:54.03#ibcon#flushed, iclass 33, count 2 2006.285.19:14:54.03#ibcon#about to write, iclass 33, count 2 2006.285.19:14:54.03#ibcon#wrote, iclass 33, count 2 2006.285.19:14:54.03#ibcon#about to read 3, iclass 33, count 2 2006.285.19:14:54.06#ibcon#read 3, iclass 33, count 2 2006.285.19:14:54.06#ibcon#about to read 4, iclass 33, count 2 2006.285.19:14:54.06#ibcon#read 4, iclass 33, count 2 2006.285.19:14:54.06#ibcon#about to read 5, iclass 33, count 2 2006.285.19:14:54.06#ibcon#read 5, iclass 33, count 2 2006.285.19:14:54.06#ibcon#about to read 6, iclass 33, count 2 2006.285.19:14:54.06#ibcon#read 6, iclass 33, count 2 2006.285.19:14:54.06#ibcon#end of sib2, iclass 33, count 2 2006.285.19:14:54.06#ibcon#*after write, iclass 33, count 2 2006.285.19:14:54.06#ibcon#*before return 0, iclass 33, count 2 2006.285.19:14:54.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:14:54.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:14:54.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.19:14:54.06#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:54.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:14:54.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:14:54.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:14:54.18#ibcon#enter wrdev, iclass 33, count 0 2006.285.19:14:54.18#ibcon#first serial, iclass 33, count 0 2006.285.19:14:54.18#ibcon#enter sib2, iclass 33, count 0 2006.285.19:14:54.18#ibcon#flushed, iclass 33, count 0 2006.285.19:14:54.18#ibcon#about to write, iclass 33, count 0 2006.285.19:14:54.18#ibcon#wrote, iclass 33, count 0 2006.285.19:14:54.18#ibcon#about to read 3, iclass 33, count 0 2006.285.19:14:54.20#ibcon#read 3, iclass 33, count 0 2006.285.19:14:54.20#ibcon#about to read 4, iclass 33, count 0 2006.285.19:14:54.20#ibcon#read 4, iclass 33, count 0 2006.285.19:14:54.20#ibcon#about to read 5, iclass 33, count 0 2006.285.19:14:54.20#ibcon#read 5, iclass 33, count 0 2006.285.19:14:54.20#ibcon#about to read 6, iclass 33, count 0 2006.285.19:14:54.20#ibcon#read 6, iclass 33, count 0 2006.285.19:14:54.20#ibcon#end of sib2, iclass 33, count 0 2006.285.19:14:54.20#ibcon#*mode == 0, iclass 33, count 0 2006.285.19:14:54.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.19:14:54.20#ibcon#[27=USB\r\n] 2006.285.19:14:54.20#ibcon#*before write, iclass 33, count 0 2006.285.19:14:54.20#ibcon#enter sib2, iclass 33, count 0 2006.285.19:14:54.20#ibcon#flushed, iclass 33, count 0 2006.285.19:14:54.20#ibcon#about to write, iclass 33, count 0 2006.285.19:14:54.20#ibcon#wrote, iclass 33, count 0 2006.285.19:14:54.20#ibcon#about to read 3, iclass 33, count 0 2006.285.19:14:54.23#ibcon#read 3, iclass 33, count 0 2006.285.19:14:54.23#ibcon#about to read 4, iclass 33, count 0 2006.285.19:14:54.23#ibcon#read 4, iclass 33, count 0 2006.285.19:14:54.23#ibcon#about to read 5, iclass 33, count 0 2006.285.19:14:54.23#ibcon#read 5, iclass 33, count 0 2006.285.19:14:54.23#ibcon#about to read 6, iclass 33, count 0 2006.285.19:14:54.23#ibcon#read 6, iclass 33, count 0 2006.285.19:14:54.23#ibcon#end of sib2, iclass 33, count 0 2006.285.19:14:54.23#ibcon#*after write, iclass 33, count 0 2006.285.19:14:54.23#ibcon#*before return 0, iclass 33, count 0 2006.285.19:14:54.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:14:54.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:14:54.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.19:14:54.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.19:14:54.23$vck44/vblo=4,679.99 2006.285.19:14:54.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.19:14:54.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.19:14:54.23#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:54.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:14:54.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:14:54.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:14:54.23#ibcon#enter wrdev, iclass 35, count 0 2006.285.19:14:54.23#ibcon#first serial, iclass 35, count 0 2006.285.19:14:54.23#ibcon#enter sib2, iclass 35, count 0 2006.285.19:14:54.23#ibcon#flushed, iclass 35, count 0 2006.285.19:14:54.23#ibcon#about to write, iclass 35, count 0 2006.285.19:14:54.23#ibcon#wrote, iclass 35, count 0 2006.285.19:14:54.23#ibcon#about to read 3, iclass 35, count 0 2006.285.19:14:54.25#ibcon#read 3, iclass 35, count 0 2006.285.19:14:54.64#ibcon#about to read 4, iclass 35, count 0 2006.285.19:14:54.64#ibcon#read 4, iclass 35, count 0 2006.285.19:14:54.64#ibcon#about to read 5, iclass 35, count 0 2006.285.19:14:54.64#ibcon#read 5, iclass 35, count 0 2006.285.19:14:54.64#ibcon#about to read 6, iclass 35, count 0 2006.285.19:14:54.64#ibcon#read 6, iclass 35, count 0 2006.285.19:14:54.64#ibcon#end of sib2, iclass 35, count 0 2006.285.19:14:54.64#ibcon#*mode == 0, iclass 35, count 0 2006.285.19:14:54.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.19:14:54.64#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.19:14:54.64#ibcon#*before write, iclass 35, count 0 2006.285.19:14:54.64#ibcon#enter sib2, iclass 35, count 0 2006.285.19:14:54.64#ibcon#flushed, iclass 35, count 0 2006.285.19:14:54.64#ibcon#about to write, iclass 35, count 0 2006.285.19:14:54.64#ibcon#wrote, iclass 35, count 0 2006.285.19:14:54.64#ibcon#about to read 3, iclass 35, count 0 2006.285.19:14:54.68#ibcon#read 3, iclass 35, count 0 2006.285.19:14:54.68#ibcon#about to read 4, iclass 35, count 0 2006.285.19:14:54.68#ibcon#read 4, iclass 35, count 0 2006.285.19:14:54.68#ibcon#about to read 5, iclass 35, count 0 2006.285.19:14:54.68#ibcon#read 5, iclass 35, count 0 2006.285.19:14:54.68#ibcon#about to read 6, iclass 35, count 0 2006.285.19:14:54.68#ibcon#read 6, iclass 35, count 0 2006.285.19:14:54.68#ibcon#end of sib2, iclass 35, count 0 2006.285.19:14:54.68#ibcon#*after write, iclass 35, count 0 2006.285.19:14:54.68#ibcon#*before return 0, iclass 35, count 0 2006.285.19:14:54.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:14:54.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:14:54.68#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.19:14:54.68#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.19:14:54.68$vck44/vb=4,5 2006.285.19:14:54.68#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.19:14:54.68#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.19:14:54.68#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:54.68#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:14:54.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:14:54.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:14:54.68#ibcon#enter wrdev, iclass 37, count 2 2006.285.19:14:54.68#ibcon#first serial, iclass 37, count 2 2006.285.19:14:54.68#ibcon#enter sib2, iclass 37, count 2 2006.285.19:14:54.68#ibcon#flushed, iclass 37, count 2 2006.285.19:14:54.68#ibcon#about to write, iclass 37, count 2 2006.285.19:14:54.68#ibcon#wrote, iclass 37, count 2 2006.285.19:14:54.68#ibcon#about to read 3, iclass 37, count 2 2006.285.19:14:54.70#ibcon#read 3, iclass 37, count 2 2006.285.19:14:54.70#ibcon#about to read 4, iclass 37, count 2 2006.285.19:14:54.70#ibcon#read 4, iclass 37, count 2 2006.285.19:14:54.70#ibcon#about to read 5, iclass 37, count 2 2006.285.19:14:54.70#ibcon#read 5, iclass 37, count 2 2006.285.19:14:54.70#ibcon#about to read 6, iclass 37, count 2 2006.285.19:14:54.70#ibcon#read 6, iclass 37, count 2 2006.285.19:14:54.70#ibcon#end of sib2, iclass 37, count 2 2006.285.19:14:54.70#ibcon#*mode == 0, iclass 37, count 2 2006.285.19:14:54.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.19:14:54.70#ibcon#[27=AT04-05\r\n] 2006.285.19:14:54.70#ibcon#*before write, iclass 37, count 2 2006.285.19:14:54.70#ibcon#enter sib2, iclass 37, count 2 2006.285.19:14:54.70#ibcon#flushed, iclass 37, count 2 2006.285.19:14:54.70#ibcon#about to write, iclass 37, count 2 2006.285.19:14:54.70#ibcon#wrote, iclass 37, count 2 2006.285.19:14:54.70#ibcon#about to read 3, iclass 37, count 2 2006.285.19:14:54.73#ibcon#read 3, iclass 37, count 2 2006.285.19:14:54.73#ibcon#about to read 4, iclass 37, count 2 2006.285.19:14:54.73#ibcon#read 4, iclass 37, count 2 2006.285.19:14:54.73#ibcon#about to read 5, iclass 37, count 2 2006.285.19:14:54.73#ibcon#read 5, iclass 37, count 2 2006.285.19:14:54.73#ibcon#about to read 6, iclass 37, count 2 2006.285.19:14:54.73#ibcon#read 6, iclass 37, count 2 2006.285.19:14:54.73#ibcon#end of sib2, iclass 37, count 2 2006.285.19:14:54.73#ibcon#*after write, iclass 37, count 2 2006.285.19:14:54.73#ibcon#*before return 0, iclass 37, count 2 2006.285.19:14:54.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:14:54.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:14:54.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.19:14:54.73#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:54.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:14:54.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:14:54.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:14:54.85#ibcon#enter wrdev, iclass 37, count 0 2006.285.19:14:54.85#ibcon#first serial, iclass 37, count 0 2006.285.19:14:54.85#ibcon#enter sib2, iclass 37, count 0 2006.285.19:14:54.85#ibcon#flushed, iclass 37, count 0 2006.285.19:14:54.85#ibcon#about to write, iclass 37, count 0 2006.285.19:14:54.85#ibcon#wrote, iclass 37, count 0 2006.285.19:14:54.85#ibcon#about to read 3, iclass 37, count 0 2006.285.19:14:54.87#ibcon#read 3, iclass 37, count 0 2006.285.19:14:54.87#ibcon#about to read 4, iclass 37, count 0 2006.285.19:14:54.87#ibcon#read 4, iclass 37, count 0 2006.285.19:14:54.87#ibcon#about to read 5, iclass 37, count 0 2006.285.19:14:54.87#ibcon#read 5, iclass 37, count 0 2006.285.19:14:54.87#ibcon#about to read 6, iclass 37, count 0 2006.285.19:14:54.87#ibcon#read 6, iclass 37, count 0 2006.285.19:14:54.87#ibcon#end of sib2, iclass 37, count 0 2006.285.19:14:54.87#ibcon#*mode == 0, iclass 37, count 0 2006.285.19:14:54.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.19:14:54.87#ibcon#[27=USB\r\n] 2006.285.19:14:54.87#ibcon#*before write, iclass 37, count 0 2006.285.19:14:54.87#ibcon#enter sib2, iclass 37, count 0 2006.285.19:14:54.87#ibcon#flushed, iclass 37, count 0 2006.285.19:14:54.87#ibcon#about to write, iclass 37, count 0 2006.285.19:14:54.87#ibcon#wrote, iclass 37, count 0 2006.285.19:14:54.87#ibcon#about to read 3, iclass 37, count 0 2006.285.19:14:54.90#ibcon#read 3, iclass 37, count 0 2006.285.19:14:54.90#ibcon#about to read 4, iclass 37, count 0 2006.285.19:14:54.90#ibcon#read 4, iclass 37, count 0 2006.285.19:14:54.90#ibcon#about to read 5, iclass 37, count 0 2006.285.19:14:54.90#ibcon#read 5, iclass 37, count 0 2006.285.19:14:54.90#ibcon#about to read 6, iclass 37, count 0 2006.285.19:14:54.90#ibcon#read 6, iclass 37, count 0 2006.285.19:14:54.90#ibcon#end of sib2, iclass 37, count 0 2006.285.19:14:54.90#ibcon#*after write, iclass 37, count 0 2006.285.19:14:54.90#ibcon#*before return 0, iclass 37, count 0 2006.285.19:14:54.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:14:54.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:14:54.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.19:14:54.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.19:14:54.90$vck44/vblo=5,709.99 2006.285.19:14:54.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.19:14:54.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.19:14:54.90#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:54.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:14:54.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:14:54.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:14:54.90#ibcon#enter wrdev, iclass 39, count 0 2006.285.19:14:54.90#ibcon#first serial, iclass 39, count 0 2006.285.19:14:54.90#ibcon#enter sib2, iclass 39, count 0 2006.285.19:14:54.90#ibcon#flushed, iclass 39, count 0 2006.285.19:14:54.90#ibcon#about to write, iclass 39, count 0 2006.285.19:14:54.90#ibcon#wrote, iclass 39, count 0 2006.285.19:14:54.90#ibcon#about to read 3, iclass 39, count 0 2006.285.19:14:54.92#ibcon#read 3, iclass 39, count 0 2006.285.19:14:54.92#ibcon#about to read 4, iclass 39, count 0 2006.285.19:14:54.92#ibcon#read 4, iclass 39, count 0 2006.285.19:14:54.92#ibcon#about to read 5, iclass 39, count 0 2006.285.19:14:54.92#ibcon#read 5, iclass 39, count 0 2006.285.19:14:54.92#ibcon#about to read 6, iclass 39, count 0 2006.285.19:14:54.92#ibcon#read 6, iclass 39, count 0 2006.285.19:14:54.92#ibcon#end of sib2, iclass 39, count 0 2006.285.19:14:54.92#ibcon#*mode == 0, iclass 39, count 0 2006.285.19:14:54.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.19:14:54.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.19:14:54.92#ibcon#*before write, iclass 39, count 0 2006.285.19:14:54.92#ibcon#enter sib2, iclass 39, count 0 2006.285.19:14:54.92#ibcon#flushed, iclass 39, count 0 2006.285.19:14:54.92#ibcon#about to write, iclass 39, count 0 2006.285.19:14:54.92#ibcon#wrote, iclass 39, count 0 2006.285.19:14:54.92#ibcon#about to read 3, iclass 39, count 0 2006.285.19:14:54.96#ibcon#read 3, iclass 39, count 0 2006.285.19:14:54.96#ibcon#about to read 4, iclass 39, count 0 2006.285.19:14:54.96#ibcon#read 4, iclass 39, count 0 2006.285.19:14:54.96#ibcon#about to read 5, iclass 39, count 0 2006.285.19:14:54.96#ibcon#read 5, iclass 39, count 0 2006.285.19:14:54.96#ibcon#about to read 6, iclass 39, count 0 2006.285.19:14:54.96#ibcon#read 6, iclass 39, count 0 2006.285.19:14:54.96#ibcon#end of sib2, iclass 39, count 0 2006.285.19:14:54.96#ibcon#*after write, iclass 39, count 0 2006.285.19:14:54.96#ibcon#*before return 0, iclass 39, count 0 2006.285.19:14:54.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:14:54.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:14:54.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.19:14:54.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.19:14:54.96$vck44/vb=5,4 2006.285.19:14:54.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.19:14:54.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.19:14:54.96#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:54.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:14:55.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:14:55.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:14:55.02#ibcon#enter wrdev, iclass 3, count 2 2006.285.19:14:55.02#ibcon#first serial, iclass 3, count 2 2006.285.19:14:55.02#ibcon#enter sib2, iclass 3, count 2 2006.285.19:14:55.02#ibcon#flushed, iclass 3, count 2 2006.285.19:14:55.02#ibcon#about to write, iclass 3, count 2 2006.285.19:14:55.02#ibcon#wrote, iclass 3, count 2 2006.285.19:14:55.02#ibcon#about to read 3, iclass 3, count 2 2006.285.19:14:55.04#ibcon#read 3, iclass 3, count 2 2006.285.19:14:55.04#ibcon#about to read 4, iclass 3, count 2 2006.285.19:14:55.04#ibcon#read 4, iclass 3, count 2 2006.285.19:14:55.04#ibcon#about to read 5, iclass 3, count 2 2006.285.19:14:55.04#ibcon#read 5, iclass 3, count 2 2006.285.19:14:55.04#ibcon#about to read 6, iclass 3, count 2 2006.285.19:14:55.04#ibcon#read 6, iclass 3, count 2 2006.285.19:14:55.04#ibcon#end of sib2, iclass 3, count 2 2006.285.19:14:55.04#ibcon#*mode == 0, iclass 3, count 2 2006.285.19:14:55.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.19:14:55.04#ibcon#[27=AT05-04\r\n] 2006.285.19:14:55.04#ibcon#*before write, iclass 3, count 2 2006.285.19:14:55.04#ibcon#enter sib2, iclass 3, count 2 2006.285.19:14:55.04#ibcon#flushed, iclass 3, count 2 2006.285.19:14:55.04#ibcon#about to write, iclass 3, count 2 2006.285.19:14:55.04#ibcon#wrote, iclass 3, count 2 2006.285.19:14:55.04#ibcon#about to read 3, iclass 3, count 2 2006.285.19:14:55.07#ibcon#read 3, iclass 3, count 2 2006.285.19:14:55.07#ibcon#about to read 4, iclass 3, count 2 2006.285.19:14:55.07#ibcon#read 4, iclass 3, count 2 2006.285.19:14:55.07#ibcon#about to read 5, iclass 3, count 2 2006.285.19:14:55.07#ibcon#read 5, iclass 3, count 2 2006.285.19:14:55.07#ibcon#about to read 6, iclass 3, count 2 2006.285.19:14:55.07#ibcon#read 6, iclass 3, count 2 2006.285.19:14:55.07#ibcon#end of sib2, iclass 3, count 2 2006.285.19:14:55.07#ibcon#*after write, iclass 3, count 2 2006.285.19:14:55.07#ibcon#*before return 0, iclass 3, count 2 2006.285.19:14:55.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:14:55.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:14:55.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.19:14:55.07#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:55.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:14:55.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:14:55.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:14:55.19#ibcon#enter wrdev, iclass 3, count 0 2006.285.19:14:55.19#ibcon#first serial, iclass 3, count 0 2006.285.19:14:55.19#ibcon#enter sib2, iclass 3, count 0 2006.285.19:14:55.19#ibcon#flushed, iclass 3, count 0 2006.285.19:14:55.19#ibcon#about to write, iclass 3, count 0 2006.285.19:14:55.19#ibcon#wrote, iclass 3, count 0 2006.285.19:14:55.19#ibcon#about to read 3, iclass 3, count 0 2006.285.19:14:55.21#ibcon#read 3, iclass 3, count 0 2006.285.19:14:55.21#ibcon#about to read 4, iclass 3, count 0 2006.285.19:14:55.21#ibcon#read 4, iclass 3, count 0 2006.285.19:14:55.21#ibcon#about to read 5, iclass 3, count 0 2006.285.19:14:55.21#ibcon#read 5, iclass 3, count 0 2006.285.19:14:55.21#ibcon#about to read 6, iclass 3, count 0 2006.285.19:14:55.21#ibcon#read 6, iclass 3, count 0 2006.285.19:14:55.21#ibcon#end of sib2, iclass 3, count 0 2006.285.19:14:55.21#ibcon#*mode == 0, iclass 3, count 0 2006.285.19:14:55.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.19:14:55.21#ibcon#[27=USB\r\n] 2006.285.19:14:55.21#ibcon#*before write, iclass 3, count 0 2006.285.19:14:55.21#ibcon#enter sib2, iclass 3, count 0 2006.285.19:14:55.21#ibcon#flushed, iclass 3, count 0 2006.285.19:14:55.21#ibcon#about to write, iclass 3, count 0 2006.285.19:14:55.21#ibcon#wrote, iclass 3, count 0 2006.285.19:14:55.21#ibcon#about to read 3, iclass 3, count 0 2006.285.19:14:55.24#ibcon#read 3, iclass 3, count 0 2006.285.19:14:55.24#ibcon#about to read 4, iclass 3, count 0 2006.285.19:14:55.24#ibcon#read 4, iclass 3, count 0 2006.285.19:14:55.24#ibcon#about to read 5, iclass 3, count 0 2006.285.19:14:55.24#ibcon#read 5, iclass 3, count 0 2006.285.19:14:55.24#ibcon#about to read 6, iclass 3, count 0 2006.285.19:14:55.24#ibcon#read 6, iclass 3, count 0 2006.285.19:14:55.24#ibcon#end of sib2, iclass 3, count 0 2006.285.19:14:55.24#ibcon#*after write, iclass 3, count 0 2006.285.19:14:55.24#ibcon#*before return 0, iclass 3, count 0 2006.285.19:14:55.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:14:55.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:14:55.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.19:14:55.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.19:14:55.24$vck44/vblo=6,719.99 2006.285.19:14:55.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.19:14:55.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.19:14:55.24#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:55.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:14:55.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:14:55.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:14:55.24#ibcon#enter wrdev, iclass 5, count 0 2006.285.19:14:55.24#ibcon#first serial, iclass 5, count 0 2006.285.19:14:55.24#ibcon#enter sib2, iclass 5, count 0 2006.285.19:14:55.24#ibcon#flushed, iclass 5, count 0 2006.285.19:14:55.24#ibcon#about to write, iclass 5, count 0 2006.285.19:14:55.24#ibcon#wrote, iclass 5, count 0 2006.285.19:14:55.24#ibcon#about to read 3, iclass 5, count 0 2006.285.19:14:55.26#ibcon#read 3, iclass 5, count 0 2006.285.19:14:55.43#ibcon#about to read 4, iclass 5, count 0 2006.285.19:14:55.43#ibcon#read 4, iclass 5, count 0 2006.285.19:14:55.43#ibcon#about to read 5, iclass 5, count 0 2006.285.19:14:55.43#ibcon#read 5, iclass 5, count 0 2006.285.19:14:55.43#ibcon#about to read 6, iclass 5, count 0 2006.285.19:14:55.43#ibcon#read 6, iclass 5, count 0 2006.285.19:14:55.43#ibcon#end of sib2, iclass 5, count 0 2006.285.19:14:55.43#ibcon#*mode == 0, iclass 5, count 0 2006.285.19:14:55.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.19:14:55.43#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.19:14:55.43#ibcon#*before write, iclass 5, count 0 2006.285.19:14:55.43#ibcon#enter sib2, iclass 5, count 0 2006.285.19:14:55.43#ibcon#flushed, iclass 5, count 0 2006.285.19:14:55.43#ibcon#about to write, iclass 5, count 0 2006.285.19:14:55.43#ibcon#wrote, iclass 5, count 0 2006.285.19:14:55.43#ibcon#about to read 3, iclass 5, count 0 2006.285.19:14:55.47#ibcon#read 3, iclass 5, count 0 2006.285.19:14:55.47#ibcon#about to read 4, iclass 5, count 0 2006.285.19:14:55.47#ibcon#read 4, iclass 5, count 0 2006.285.19:14:55.47#ibcon#about to read 5, iclass 5, count 0 2006.285.19:14:55.47#ibcon#read 5, iclass 5, count 0 2006.285.19:14:55.47#ibcon#about to read 6, iclass 5, count 0 2006.285.19:14:55.47#ibcon#read 6, iclass 5, count 0 2006.285.19:14:55.47#ibcon#end of sib2, iclass 5, count 0 2006.285.19:14:55.47#ibcon#*after write, iclass 5, count 0 2006.285.19:14:55.47#ibcon#*before return 0, iclass 5, count 0 2006.285.19:14:55.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:14:55.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:14:55.47#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.19:14:55.47#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.19:14:55.47$vck44/vb=6,3 2006.285.19:14:55.47#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.19:14:55.47#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.19:14:55.47#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:55.47#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:14:55.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:14:55.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:14:55.47#ibcon#enter wrdev, iclass 7, count 2 2006.285.19:14:55.47#ibcon#first serial, iclass 7, count 2 2006.285.19:14:55.47#ibcon#enter sib2, iclass 7, count 2 2006.285.19:14:55.47#ibcon#flushed, iclass 7, count 2 2006.285.19:14:55.47#ibcon#about to write, iclass 7, count 2 2006.285.19:14:55.47#ibcon#wrote, iclass 7, count 2 2006.285.19:14:55.47#ibcon#about to read 3, iclass 7, count 2 2006.285.19:14:55.49#ibcon#read 3, iclass 7, count 2 2006.285.19:14:55.49#ibcon#about to read 4, iclass 7, count 2 2006.285.19:14:55.49#ibcon#read 4, iclass 7, count 2 2006.285.19:14:55.49#ibcon#about to read 5, iclass 7, count 2 2006.285.19:14:55.49#ibcon#read 5, iclass 7, count 2 2006.285.19:14:55.49#ibcon#about to read 6, iclass 7, count 2 2006.285.19:14:55.49#ibcon#read 6, iclass 7, count 2 2006.285.19:14:55.49#ibcon#end of sib2, iclass 7, count 2 2006.285.19:14:55.49#ibcon#*mode == 0, iclass 7, count 2 2006.285.19:14:55.49#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.19:14:55.49#ibcon#[27=AT06-03\r\n] 2006.285.19:14:55.49#ibcon#*before write, iclass 7, count 2 2006.285.19:14:55.49#ibcon#enter sib2, iclass 7, count 2 2006.285.19:14:55.49#ibcon#flushed, iclass 7, count 2 2006.285.19:14:55.49#ibcon#about to write, iclass 7, count 2 2006.285.19:14:55.49#ibcon#wrote, iclass 7, count 2 2006.285.19:14:55.49#ibcon#about to read 3, iclass 7, count 2 2006.285.19:14:55.52#ibcon#read 3, iclass 7, count 2 2006.285.19:14:55.52#ibcon#about to read 4, iclass 7, count 2 2006.285.19:14:55.52#ibcon#read 4, iclass 7, count 2 2006.285.19:14:55.52#ibcon#about to read 5, iclass 7, count 2 2006.285.19:14:55.52#ibcon#read 5, iclass 7, count 2 2006.285.19:14:55.52#ibcon#about to read 6, iclass 7, count 2 2006.285.19:14:55.52#ibcon#read 6, iclass 7, count 2 2006.285.19:14:55.52#ibcon#end of sib2, iclass 7, count 2 2006.285.19:14:55.52#ibcon#*after write, iclass 7, count 2 2006.285.19:14:55.52#ibcon#*before return 0, iclass 7, count 2 2006.285.19:14:55.52#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:14:55.52#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:14:55.52#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.19:14:55.52#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:55.52#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:14:55.64#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:14:55.64#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:14:55.64#ibcon#enter wrdev, iclass 7, count 0 2006.285.19:14:55.64#ibcon#first serial, iclass 7, count 0 2006.285.19:14:55.64#ibcon#enter sib2, iclass 7, count 0 2006.285.19:14:55.64#ibcon#flushed, iclass 7, count 0 2006.285.19:14:55.64#ibcon#about to write, iclass 7, count 0 2006.285.19:14:55.64#ibcon#wrote, iclass 7, count 0 2006.285.19:14:55.64#ibcon#about to read 3, iclass 7, count 0 2006.285.19:14:55.66#ibcon#read 3, iclass 7, count 0 2006.285.19:14:55.66#ibcon#about to read 4, iclass 7, count 0 2006.285.19:14:55.66#ibcon#read 4, iclass 7, count 0 2006.285.19:14:55.66#ibcon#about to read 5, iclass 7, count 0 2006.285.19:14:55.66#ibcon#read 5, iclass 7, count 0 2006.285.19:14:55.66#ibcon#about to read 6, iclass 7, count 0 2006.285.19:14:55.66#ibcon#read 6, iclass 7, count 0 2006.285.19:14:55.66#ibcon#end of sib2, iclass 7, count 0 2006.285.19:14:55.66#ibcon#*mode == 0, iclass 7, count 0 2006.285.19:14:55.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.19:14:55.66#ibcon#[27=USB\r\n] 2006.285.19:14:55.66#ibcon#*before write, iclass 7, count 0 2006.285.19:14:55.66#ibcon#enter sib2, iclass 7, count 0 2006.285.19:14:55.66#ibcon#flushed, iclass 7, count 0 2006.285.19:14:55.66#ibcon#about to write, iclass 7, count 0 2006.285.19:14:55.66#ibcon#wrote, iclass 7, count 0 2006.285.19:14:55.66#ibcon#about to read 3, iclass 7, count 0 2006.285.19:14:55.69#ibcon#read 3, iclass 7, count 0 2006.285.19:14:55.69#ibcon#about to read 4, iclass 7, count 0 2006.285.19:14:55.69#ibcon#read 4, iclass 7, count 0 2006.285.19:14:55.69#ibcon#about to read 5, iclass 7, count 0 2006.285.19:14:55.69#ibcon#read 5, iclass 7, count 0 2006.285.19:14:55.69#ibcon#about to read 6, iclass 7, count 0 2006.285.19:14:55.69#ibcon#read 6, iclass 7, count 0 2006.285.19:14:55.69#ibcon#end of sib2, iclass 7, count 0 2006.285.19:14:55.69#ibcon#*after write, iclass 7, count 0 2006.285.19:14:55.69#ibcon#*before return 0, iclass 7, count 0 2006.285.19:14:55.69#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:14:55.69#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:14:55.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.19:14:55.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.19:14:55.69$vck44/vblo=7,734.99 2006.285.19:14:55.69#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.19:14:55.69#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.19:14:55.69#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:55.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:14:55.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:14:55.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:14:55.69#ibcon#enter wrdev, iclass 11, count 0 2006.285.19:14:55.69#ibcon#first serial, iclass 11, count 0 2006.285.19:14:55.69#ibcon#enter sib2, iclass 11, count 0 2006.285.19:14:55.69#ibcon#flushed, iclass 11, count 0 2006.285.19:14:55.69#ibcon#about to write, iclass 11, count 0 2006.285.19:14:55.69#ibcon#wrote, iclass 11, count 0 2006.285.19:14:55.69#ibcon#about to read 3, iclass 11, count 0 2006.285.19:14:55.71#ibcon#read 3, iclass 11, count 0 2006.285.19:14:55.71#ibcon#about to read 4, iclass 11, count 0 2006.285.19:14:55.71#ibcon#read 4, iclass 11, count 0 2006.285.19:14:55.71#ibcon#about to read 5, iclass 11, count 0 2006.285.19:14:55.71#ibcon#read 5, iclass 11, count 0 2006.285.19:14:55.71#ibcon#about to read 6, iclass 11, count 0 2006.285.19:14:55.71#ibcon#read 6, iclass 11, count 0 2006.285.19:14:55.71#ibcon#end of sib2, iclass 11, count 0 2006.285.19:14:55.71#ibcon#*mode == 0, iclass 11, count 0 2006.285.19:14:55.71#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.19:14:55.71#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.19:14:55.71#ibcon#*before write, iclass 11, count 0 2006.285.19:14:55.71#ibcon#enter sib2, iclass 11, count 0 2006.285.19:14:55.71#ibcon#flushed, iclass 11, count 0 2006.285.19:14:55.71#ibcon#about to write, iclass 11, count 0 2006.285.19:14:55.71#ibcon#wrote, iclass 11, count 0 2006.285.19:14:55.71#ibcon#about to read 3, iclass 11, count 0 2006.285.19:14:55.75#ibcon#read 3, iclass 11, count 0 2006.285.19:14:55.75#ibcon#about to read 4, iclass 11, count 0 2006.285.19:14:55.75#ibcon#read 4, iclass 11, count 0 2006.285.19:14:55.75#ibcon#about to read 5, iclass 11, count 0 2006.285.19:14:55.75#ibcon#read 5, iclass 11, count 0 2006.285.19:14:55.75#ibcon#about to read 6, iclass 11, count 0 2006.285.19:14:55.75#ibcon#read 6, iclass 11, count 0 2006.285.19:14:55.75#ibcon#end of sib2, iclass 11, count 0 2006.285.19:14:55.75#ibcon#*after write, iclass 11, count 0 2006.285.19:14:55.75#ibcon#*before return 0, iclass 11, count 0 2006.285.19:14:55.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:14:55.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:14:55.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.19:14:55.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.19:14:55.75$vck44/vb=7,4 2006.285.19:14:55.75#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.19:14:55.75#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.19:14:55.75#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:55.75#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:14:55.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:14:55.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:14:55.81#ibcon#enter wrdev, iclass 13, count 2 2006.285.19:14:55.81#ibcon#first serial, iclass 13, count 2 2006.285.19:14:55.81#ibcon#enter sib2, iclass 13, count 2 2006.285.19:14:55.81#ibcon#flushed, iclass 13, count 2 2006.285.19:14:55.81#ibcon#about to write, iclass 13, count 2 2006.285.19:14:55.81#ibcon#wrote, iclass 13, count 2 2006.285.19:14:55.81#ibcon#about to read 3, iclass 13, count 2 2006.285.19:14:55.83#ibcon#read 3, iclass 13, count 2 2006.285.19:14:55.83#ibcon#about to read 4, iclass 13, count 2 2006.285.19:14:55.83#ibcon#read 4, iclass 13, count 2 2006.285.19:14:55.83#ibcon#about to read 5, iclass 13, count 2 2006.285.19:14:55.83#ibcon#read 5, iclass 13, count 2 2006.285.19:14:55.83#ibcon#about to read 6, iclass 13, count 2 2006.285.19:14:55.83#ibcon#read 6, iclass 13, count 2 2006.285.19:14:55.83#ibcon#end of sib2, iclass 13, count 2 2006.285.19:14:55.83#ibcon#*mode == 0, iclass 13, count 2 2006.285.19:14:55.83#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.19:14:55.83#ibcon#[27=AT07-04\r\n] 2006.285.19:14:55.83#ibcon#*before write, iclass 13, count 2 2006.285.19:14:55.83#ibcon#enter sib2, iclass 13, count 2 2006.285.19:14:55.83#ibcon#flushed, iclass 13, count 2 2006.285.19:14:55.83#ibcon#about to write, iclass 13, count 2 2006.285.19:14:55.83#ibcon#wrote, iclass 13, count 2 2006.285.19:14:55.83#ibcon#about to read 3, iclass 13, count 2 2006.285.19:14:55.86#ibcon#read 3, iclass 13, count 2 2006.285.19:14:55.86#ibcon#about to read 4, iclass 13, count 2 2006.285.19:14:55.86#ibcon#read 4, iclass 13, count 2 2006.285.19:14:55.86#ibcon#about to read 5, iclass 13, count 2 2006.285.19:14:55.86#ibcon#read 5, iclass 13, count 2 2006.285.19:14:55.86#ibcon#about to read 6, iclass 13, count 2 2006.285.19:14:55.86#ibcon#read 6, iclass 13, count 2 2006.285.19:14:55.86#ibcon#end of sib2, iclass 13, count 2 2006.285.19:14:55.86#ibcon#*after write, iclass 13, count 2 2006.285.19:14:55.86#ibcon#*before return 0, iclass 13, count 2 2006.285.19:14:55.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:14:55.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:14:55.86#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.19:14:55.86#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:55.86#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:14:55.98#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:14:55.98#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:14:55.98#ibcon#enter wrdev, iclass 13, count 0 2006.285.19:14:55.98#ibcon#first serial, iclass 13, count 0 2006.285.19:14:55.98#ibcon#enter sib2, iclass 13, count 0 2006.285.19:14:55.98#ibcon#flushed, iclass 13, count 0 2006.285.19:14:55.98#ibcon#about to write, iclass 13, count 0 2006.285.19:14:55.98#ibcon#wrote, iclass 13, count 0 2006.285.19:14:55.98#ibcon#about to read 3, iclass 13, count 0 2006.285.19:14:56.00#ibcon#read 3, iclass 13, count 0 2006.285.19:14:56.00#ibcon#about to read 4, iclass 13, count 0 2006.285.19:14:56.00#ibcon#read 4, iclass 13, count 0 2006.285.19:14:56.00#ibcon#about to read 5, iclass 13, count 0 2006.285.19:14:56.00#ibcon#read 5, iclass 13, count 0 2006.285.19:14:56.00#ibcon#about to read 6, iclass 13, count 0 2006.285.19:14:56.00#ibcon#read 6, iclass 13, count 0 2006.285.19:14:56.00#ibcon#end of sib2, iclass 13, count 0 2006.285.19:14:56.00#ibcon#*mode == 0, iclass 13, count 0 2006.285.19:14:56.00#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.19:14:56.00#ibcon#[27=USB\r\n] 2006.285.19:14:56.00#ibcon#*before write, iclass 13, count 0 2006.285.19:14:56.00#ibcon#enter sib2, iclass 13, count 0 2006.285.19:14:56.00#ibcon#flushed, iclass 13, count 0 2006.285.19:14:56.00#ibcon#about to write, iclass 13, count 0 2006.285.19:14:56.00#ibcon#wrote, iclass 13, count 0 2006.285.19:14:56.00#ibcon#about to read 3, iclass 13, count 0 2006.285.19:14:56.03#ibcon#read 3, iclass 13, count 0 2006.285.19:14:56.03#ibcon#about to read 4, iclass 13, count 0 2006.285.19:14:56.03#ibcon#read 4, iclass 13, count 0 2006.285.19:14:56.03#ibcon#about to read 5, iclass 13, count 0 2006.285.19:14:56.03#ibcon#read 5, iclass 13, count 0 2006.285.19:14:56.03#ibcon#about to read 6, iclass 13, count 0 2006.285.19:14:56.03#ibcon#read 6, iclass 13, count 0 2006.285.19:14:56.03#ibcon#end of sib2, iclass 13, count 0 2006.285.19:14:56.03#ibcon#*after write, iclass 13, count 0 2006.285.19:14:56.03#ibcon#*before return 0, iclass 13, count 0 2006.285.19:14:56.03#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:14:56.03#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:14:56.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.19:14:56.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.19:14:56.03$vck44/vblo=8,744.99 2006.285.19:14:56.03#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.19:14:56.03#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.19:14:56.03#ibcon#ireg 17 cls_cnt 0 2006.285.19:14:56.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:14:56.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:14:56.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:14:56.03#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:14:56.03#ibcon#first serial, iclass 15, count 0 2006.285.19:14:56.03#ibcon#enter sib2, iclass 15, count 0 2006.285.19:14:56.03#ibcon#flushed, iclass 15, count 0 2006.285.19:14:56.03#ibcon#about to write, iclass 15, count 0 2006.285.19:14:56.03#ibcon#wrote, iclass 15, count 0 2006.285.19:14:56.03#ibcon#about to read 3, iclass 15, count 0 2006.285.19:14:56.05#ibcon#read 3, iclass 15, count 0 2006.285.19:14:56.05#ibcon#about to read 4, iclass 15, count 0 2006.285.19:14:56.05#ibcon#read 4, iclass 15, count 0 2006.285.19:14:56.05#ibcon#about to read 5, iclass 15, count 0 2006.285.19:14:56.05#ibcon#read 5, iclass 15, count 0 2006.285.19:14:56.05#ibcon#about to read 6, iclass 15, count 0 2006.285.19:14:56.05#ibcon#read 6, iclass 15, count 0 2006.285.19:14:56.05#ibcon#end of sib2, iclass 15, count 0 2006.285.19:14:56.05#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:14:56.05#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:14:56.05#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.19:14:56.05#ibcon#*before write, iclass 15, count 0 2006.285.19:14:56.05#ibcon#enter sib2, iclass 15, count 0 2006.285.19:14:56.05#ibcon#flushed, iclass 15, count 0 2006.285.19:14:56.05#ibcon#about to write, iclass 15, count 0 2006.285.19:14:56.05#ibcon#wrote, iclass 15, count 0 2006.285.19:14:56.05#ibcon#about to read 3, iclass 15, count 0 2006.285.19:14:56.09#ibcon#read 3, iclass 15, count 0 2006.285.19:14:56.09#ibcon#about to read 4, iclass 15, count 0 2006.285.19:14:56.09#ibcon#read 4, iclass 15, count 0 2006.285.19:14:56.09#ibcon#about to read 5, iclass 15, count 0 2006.285.19:14:56.09#ibcon#read 5, iclass 15, count 0 2006.285.19:14:56.09#ibcon#about to read 6, iclass 15, count 0 2006.285.19:14:56.09#ibcon#read 6, iclass 15, count 0 2006.285.19:14:56.09#ibcon#end of sib2, iclass 15, count 0 2006.285.19:14:56.09#ibcon#*after write, iclass 15, count 0 2006.285.19:14:56.09#ibcon#*before return 0, iclass 15, count 0 2006.285.19:14:56.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:14:56.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:14:56.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:14:56.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:14:56.09$vck44/vb=8,4 2006.285.19:14:56.09#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.19:14:56.09#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.19:14:56.09#ibcon#ireg 11 cls_cnt 2 2006.285.19:14:56.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:14:56.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:14:56.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:14:56.15#ibcon#enter wrdev, iclass 17, count 2 2006.285.19:14:56.15#ibcon#first serial, iclass 17, count 2 2006.285.19:14:56.15#ibcon#enter sib2, iclass 17, count 2 2006.285.19:14:56.15#ibcon#flushed, iclass 17, count 2 2006.285.19:14:56.15#ibcon#about to write, iclass 17, count 2 2006.285.19:14:56.15#ibcon#wrote, iclass 17, count 2 2006.285.19:14:56.15#ibcon#about to read 3, iclass 17, count 2 2006.285.19:14:56.17#ibcon#read 3, iclass 17, count 2 2006.285.19:14:56.17#ibcon#about to read 4, iclass 17, count 2 2006.285.19:14:56.17#ibcon#read 4, iclass 17, count 2 2006.285.19:14:56.17#ibcon#about to read 5, iclass 17, count 2 2006.285.19:14:56.17#ibcon#read 5, iclass 17, count 2 2006.285.19:14:56.17#ibcon#about to read 6, iclass 17, count 2 2006.285.19:14:56.17#ibcon#read 6, iclass 17, count 2 2006.285.19:14:56.17#ibcon#end of sib2, iclass 17, count 2 2006.285.19:14:56.17#ibcon#*mode == 0, iclass 17, count 2 2006.285.19:14:56.17#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.19:14:56.17#ibcon#[27=AT08-04\r\n] 2006.285.19:14:56.17#ibcon#*before write, iclass 17, count 2 2006.285.19:14:56.17#ibcon#enter sib2, iclass 17, count 2 2006.285.19:14:56.17#ibcon#flushed, iclass 17, count 2 2006.285.19:14:56.17#ibcon#about to write, iclass 17, count 2 2006.285.19:14:56.17#ibcon#wrote, iclass 17, count 2 2006.285.19:14:56.17#ibcon#about to read 3, iclass 17, count 2 2006.285.19:14:56.20#ibcon#read 3, iclass 17, count 2 2006.285.19:14:56.20#ibcon#about to read 4, iclass 17, count 2 2006.285.19:14:56.20#ibcon#read 4, iclass 17, count 2 2006.285.19:14:56.20#ibcon#about to read 5, iclass 17, count 2 2006.285.19:14:56.20#ibcon#read 5, iclass 17, count 2 2006.285.19:14:56.20#ibcon#about to read 6, iclass 17, count 2 2006.285.19:14:56.20#ibcon#read 6, iclass 17, count 2 2006.285.19:14:56.20#ibcon#end of sib2, iclass 17, count 2 2006.285.19:14:56.20#ibcon#*after write, iclass 17, count 2 2006.285.19:14:56.20#ibcon#*before return 0, iclass 17, count 2 2006.285.19:14:56.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:14:56.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:14:56.20#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.19:14:56.20#ibcon#ireg 7 cls_cnt 0 2006.285.19:14:56.20#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:14:56.32#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:14:56.32#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:14:56.32#ibcon#enter wrdev, iclass 17, count 0 2006.285.19:14:56.32#ibcon#first serial, iclass 17, count 0 2006.285.19:14:56.32#ibcon#enter sib2, iclass 17, count 0 2006.285.19:14:56.32#ibcon#flushed, iclass 17, count 0 2006.285.19:14:56.32#ibcon#about to write, iclass 17, count 0 2006.285.19:14:56.32#ibcon#wrote, iclass 17, count 0 2006.285.19:14:56.32#ibcon#about to read 3, iclass 17, count 0 2006.285.19:14:56.34#ibcon#read 3, iclass 17, count 0 2006.285.19:14:56.34#ibcon#about to read 4, iclass 17, count 0 2006.285.19:14:56.34#ibcon#read 4, iclass 17, count 0 2006.285.19:14:56.34#ibcon#about to read 5, iclass 17, count 0 2006.285.19:14:56.34#ibcon#read 5, iclass 17, count 0 2006.285.19:14:56.34#ibcon#about to read 6, iclass 17, count 0 2006.285.19:14:56.34#ibcon#read 6, iclass 17, count 0 2006.285.19:14:56.34#ibcon#end of sib2, iclass 17, count 0 2006.285.19:14:56.34#ibcon#*mode == 0, iclass 17, count 0 2006.285.19:14:56.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.19:14:56.34#ibcon#[27=USB\r\n] 2006.285.19:14:56.34#ibcon#*before write, iclass 17, count 0 2006.285.19:14:56.34#ibcon#enter sib2, iclass 17, count 0 2006.285.19:14:56.34#ibcon#flushed, iclass 17, count 0 2006.285.19:14:56.34#ibcon#about to write, iclass 17, count 0 2006.285.19:14:56.34#ibcon#wrote, iclass 17, count 0 2006.285.19:14:56.34#ibcon#about to read 3, iclass 17, count 0 2006.285.19:14:56.37#ibcon#read 3, iclass 17, count 0 2006.285.19:14:56.37#ibcon#about to read 4, iclass 17, count 0 2006.285.19:14:56.37#ibcon#read 4, iclass 17, count 0 2006.285.19:14:56.37#ibcon#about to read 5, iclass 17, count 0 2006.285.19:14:56.37#ibcon#read 5, iclass 17, count 0 2006.285.19:14:56.37#ibcon#about to read 6, iclass 17, count 0 2006.285.19:14:56.37#ibcon#read 6, iclass 17, count 0 2006.285.19:14:56.37#ibcon#end of sib2, iclass 17, count 0 2006.285.19:14:56.37#ibcon#*after write, iclass 17, count 0 2006.285.19:14:56.37#ibcon#*before return 0, iclass 17, count 0 2006.285.19:14:56.37#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:14:56.37#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:14:56.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.19:14:56.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.19:14:56.37$vck44/vabw=wide 2006.285.19:14:56.37#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.19:14:56.37#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.19:14:56.37#ibcon#ireg 8 cls_cnt 0 2006.285.19:14:56.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:14:56.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:14:56.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:14:56.37#ibcon#enter wrdev, iclass 19, count 0 2006.285.19:14:56.37#ibcon#first serial, iclass 19, count 0 2006.285.19:14:56.37#ibcon#enter sib2, iclass 19, count 0 2006.285.19:14:56.37#ibcon#flushed, iclass 19, count 0 2006.285.19:14:56.37#ibcon#about to write, iclass 19, count 0 2006.285.19:14:56.37#ibcon#wrote, iclass 19, count 0 2006.285.19:14:56.37#ibcon#about to read 3, iclass 19, count 0 2006.285.19:14:56.39#ibcon#read 3, iclass 19, count 0 2006.285.19:14:56.43#ibcon#about to read 4, iclass 19, count 0 2006.285.19:14:56.43#ibcon#read 4, iclass 19, count 0 2006.285.19:14:56.43#ibcon#about to read 5, iclass 19, count 0 2006.285.19:14:56.43#ibcon#read 5, iclass 19, count 0 2006.285.19:14:56.43#ibcon#about to read 6, iclass 19, count 0 2006.285.19:14:56.43#ibcon#read 6, iclass 19, count 0 2006.285.19:14:56.43#ibcon#end of sib2, iclass 19, count 0 2006.285.19:14:56.43#ibcon#*mode == 0, iclass 19, count 0 2006.285.19:14:56.43#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.19:14:56.43#ibcon#[25=BW32\r\n] 2006.285.19:14:56.43#ibcon#*before write, iclass 19, count 0 2006.285.19:14:56.43#ibcon#enter sib2, iclass 19, count 0 2006.285.19:14:56.43#ibcon#flushed, iclass 19, count 0 2006.285.19:14:56.43#ibcon#about to write, iclass 19, count 0 2006.285.19:14:56.43#ibcon#wrote, iclass 19, count 0 2006.285.19:14:56.43#ibcon#about to read 3, iclass 19, count 0 2006.285.19:14:56.46#ibcon#read 3, iclass 19, count 0 2006.285.19:14:56.46#ibcon#about to read 4, iclass 19, count 0 2006.285.19:14:56.46#ibcon#read 4, iclass 19, count 0 2006.285.19:14:56.46#ibcon#about to read 5, iclass 19, count 0 2006.285.19:14:56.46#ibcon#read 5, iclass 19, count 0 2006.285.19:14:56.46#ibcon#about to read 6, iclass 19, count 0 2006.285.19:14:56.46#ibcon#read 6, iclass 19, count 0 2006.285.19:14:56.46#ibcon#end of sib2, iclass 19, count 0 2006.285.19:14:56.46#ibcon#*after write, iclass 19, count 0 2006.285.19:14:56.46#ibcon#*before return 0, iclass 19, count 0 2006.285.19:14:56.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:14:56.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:14:56.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.19:14:56.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.19:14:56.46$vck44/vbbw=wide 2006.285.19:14:56.46#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.19:14:56.46#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.19:14:56.46#ibcon#ireg 8 cls_cnt 0 2006.285.19:14:56.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:14:56.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:14:56.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:14:56.49#ibcon#enter wrdev, iclass 21, count 0 2006.285.19:14:56.49#ibcon#first serial, iclass 21, count 0 2006.285.19:14:56.49#ibcon#enter sib2, iclass 21, count 0 2006.285.19:14:56.49#ibcon#flushed, iclass 21, count 0 2006.285.19:14:56.49#ibcon#about to write, iclass 21, count 0 2006.285.19:14:56.49#ibcon#wrote, iclass 21, count 0 2006.285.19:14:56.49#ibcon#about to read 3, iclass 21, count 0 2006.285.19:14:56.51#ibcon#read 3, iclass 21, count 0 2006.285.19:14:56.51#ibcon#about to read 4, iclass 21, count 0 2006.285.19:14:56.51#ibcon#read 4, iclass 21, count 0 2006.285.19:14:56.51#ibcon#about to read 5, iclass 21, count 0 2006.285.19:14:56.51#ibcon#read 5, iclass 21, count 0 2006.285.19:14:56.51#ibcon#about to read 6, iclass 21, count 0 2006.285.19:14:56.51#ibcon#read 6, iclass 21, count 0 2006.285.19:14:56.51#ibcon#end of sib2, iclass 21, count 0 2006.285.19:14:56.51#ibcon#*mode == 0, iclass 21, count 0 2006.285.19:14:56.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.19:14:56.51#ibcon#[27=BW32\r\n] 2006.285.19:14:56.51#ibcon#*before write, iclass 21, count 0 2006.285.19:14:56.51#ibcon#enter sib2, iclass 21, count 0 2006.285.19:14:56.51#ibcon#flushed, iclass 21, count 0 2006.285.19:14:56.51#ibcon#about to write, iclass 21, count 0 2006.285.19:14:56.51#ibcon#wrote, iclass 21, count 0 2006.285.19:14:56.51#ibcon#about to read 3, iclass 21, count 0 2006.285.19:14:56.54#ibcon#read 3, iclass 21, count 0 2006.285.19:14:56.54#ibcon#about to read 4, iclass 21, count 0 2006.285.19:14:56.54#ibcon#read 4, iclass 21, count 0 2006.285.19:14:56.54#ibcon#about to read 5, iclass 21, count 0 2006.285.19:14:56.54#ibcon#read 5, iclass 21, count 0 2006.285.19:14:56.54#ibcon#about to read 6, iclass 21, count 0 2006.285.19:14:56.54#ibcon#read 6, iclass 21, count 0 2006.285.19:14:56.54#ibcon#end of sib2, iclass 21, count 0 2006.285.19:14:56.54#ibcon#*after write, iclass 21, count 0 2006.285.19:14:56.54#ibcon#*before return 0, iclass 21, count 0 2006.285.19:14:56.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:14:56.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:14:56.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.19:14:56.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.19:14:56.54$setupk4/ifdk4 2006.285.19:14:56.54$ifdk4/lo= 2006.285.19:14:56.54$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.19:14:56.54$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.19:14:56.54$ifdk4/patch= 2006.285.19:14:56.54$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.19:14:56.54$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.19:14:56.54$setupk4/!*+20s 2006.285.19:15:03.89#abcon#<5=/15 1.0 1.6 15.011001014.8\r\n> 2006.285.19:15:03.91#abcon#{5=INTERFACE CLEAR} 2006.285.19:15:03.97#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:15:09.42$setupk4/"tpicd 2006.285.19:15:09.42$setupk4/echo=off 2006.285.19:15:09.42$setupk4/xlog=off 2006.285.19:15:09.42:!2006.285.19:17:09 2006.285.19:15:37.14#trakl#Source acquired 2006.285.19:15:37.14#flagr#flagr/antenna,acquired 2006.285.19:17:09.00:preob 2006.285.19:17:09.13/onsource/TRACKING 2006.285.19:17:09.13:!2006.285.19:17:19 2006.285.19:17:19.00:"tape 2006.285.19:17:19.00:"st=record 2006.285.19:17:19.00:data_valid=on 2006.285.19:17:19.00:midob 2006.285.19:17:20.13/onsource/TRACKING 2006.285.19:17:20.13/wx/15.01,1014.9,100 2006.285.19:17:20.20/cable/+6.5062E-03 2006.285.19:17:21.29/va/01,07,usb,yes,32,34 2006.285.19:17:21.29/va/02,06,usb,yes,32,32 2006.285.19:17:21.29/va/03,07,usb,yes,31,33 2006.285.19:17:21.29/va/04,06,usb,yes,33,34 2006.285.19:17:21.29/va/05,03,usb,yes,32,33 2006.285.19:17:21.29/va/06,04,usb,yes,29,28 2006.285.19:17:21.29/va/07,04,usb,yes,30,30 2006.285.19:17:21.29/va/08,03,usb,yes,30,37 2006.285.19:17:21.52/valo/01,524.99,yes,locked 2006.285.19:17:21.52/valo/02,534.99,yes,locked 2006.285.19:17:21.52/valo/03,564.99,yes,locked 2006.285.19:17:21.52/valo/04,624.99,yes,locked 2006.285.19:17:21.52/valo/05,734.99,yes,locked 2006.285.19:17:21.52/valo/06,814.99,yes,locked 2006.285.19:17:21.52/valo/07,864.99,yes,locked 2006.285.19:17:21.52/valo/08,884.99,yes,locked 2006.285.19:17:22.61/vb/01,04,usb,yes,30,28 2006.285.19:17:22.61/vb/02,05,usb,yes,28,28 2006.285.19:17:22.61/vb/03,04,usb,yes,29,32 2006.285.19:17:22.61/vb/04,05,usb,yes,29,28 2006.285.19:17:22.61/vb/05,04,usb,yes,26,28 2006.285.19:17:22.61/vb/06,03,usb,yes,37,33 2006.285.19:17:22.61/vb/07,04,usb,yes,30,30 2006.285.19:17:22.61/vb/08,04,usb,yes,27,31 2006.285.19:17:22.85/vblo/01,629.99,yes,locked 2006.285.19:17:22.85/vblo/02,634.99,yes,locked 2006.285.19:17:22.85/vblo/03,649.99,yes,locked 2006.285.19:17:22.85/vblo/04,679.99,yes,locked 2006.285.19:17:22.85/vblo/05,709.99,yes,locked 2006.285.19:17:22.85/vblo/06,719.99,yes,locked 2006.285.19:17:22.85/vblo/07,734.99,yes,locked 2006.285.19:17:22.85/vblo/08,744.99,yes,locked 2006.285.19:17:23.00/vabw/8 2006.285.19:17:23.15/vbbw/8 2006.285.19:17:23.24/xfe/off,on,12.0 2006.285.19:17:23.62/ifatt/23,28,28,28 2006.285.19:17:24.07/fmout-gps/S +2.72E-07 2006.285.19:17:24.09:!2006.285.19:18:09 2006.285.19:18:09.01:data_valid=off 2006.285.19:18:09.01:"et 2006.285.19:18:09.01:!+3s 2006.285.19:18:12.02:"tape 2006.285.19:18:12.02:postob 2006.285.19:18:12.22/cable/+6.5063E-03 2006.285.19:18:12.22/wx/15.00,1014.9,100 2006.285.19:18:12.28/fmout-gps/S +2.72E-07 2006.285.19:18:12.28:scan_name=285-1920,jd0610,310 2006.285.19:18:12.28:source=nrao150,035929.75,505750.2,2000.0,cw 2006.285.19:18:13.13#flagr#flagr/antenna,new-source 2006.285.19:18:13.13:checkk5 2006.285.19:18:13.63/chk_autoobs//k5ts1/ autoobs is running! 2006.285.19:18:14.01/chk_autoobs//k5ts2/ autoobs is running! 2006.285.19:18:14.74/chk_autoobs//k5ts3/ autoobs is running! 2006.285.19:18:15.11/chk_autoobs//k5ts4/ autoobs is running! 2006.285.19:18:18.45/chk_obsdata//k5ts1/T2851917??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.19:18:18.83/chk_obsdata//k5ts2/T2851917??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.19:18:19.56/chk_obsdata//k5ts3/T2851917??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.19:18:19.89/chk_obsdata//k5ts4/T2851917??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.19:18:20.84/k5log//k5ts1_log_newline 2006.285.19:18:21.67/k5log//k5ts2_log_newline 2006.285.19:18:22.43/k5log//k5ts3_log_newline 2006.285.19:18:23.24/k5log//k5ts4_log_newline 2006.285.19:18:23.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.19:18:23.26:setupk4=1 2006.285.19:18:23.26$setupk4/echo=on 2006.285.19:18:23.26$setupk4/pcalon 2006.285.19:18:23.26$pcalon/"no phase cal control is implemented here 2006.285.19:18:23.26$setupk4/"tpicd=stop 2006.285.19:18:23.26$setupk4/"rec=synch_on 2006.285.19:18:23.26$setupk4/"rec_mode=128 2006.285.19:18:23.26$setupk4/!* 2006.285.19:18:23.26$setupk4/recpk4 2006.285.19:18:23.26$recpk4/recpatch= 2006.285.19:18:23.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.19:18:23.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.19:18:23.26$setupk4/vck44 2006.285.19:18:23.26$vck44/valo=1,524.99 2006.285.19:18:23.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.19:18:23.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.19:18:23.26#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:23.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:18:23.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:18:23.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:18:23.26#ibcon#enter wrdev, iclass 29, count 0 2006.285.19:18:23.26#ibcon#first serial, iclass 29, count 0 2006.285.19:18:23.26#ibcon#enter sib2, iclass 29, count 0 2006.285.19:18:23.26#ibcon#flushed, iclass 29, count 0 2006.285.19:18:23.26#ibcon#about to write, iclass 29, count 0 2006.285.19:18:23.27#ibcon#wrote, iclass 29, count 0 2006.285.19:18:23.27#ibcon#about to read 3, iclass 29, count 0 2006.285.19:18:23.28#ibcon#read 3, iclass 29, count 0 2006.285.19:18:23.28#ibcon#about to read 4, iclass 29, count 0 2006.285.19:18:23.28#ibcon#read 4, iclass 29, count 0 2006.285.19:18:23.28#ibcon#about to read 5, iclass 29, count 0 2006.285.19:18:23.28#ibcon#read 5, iclass 29, count 0 2006.285.19:18:23.28#ibcon#about to read 6, iclass 29, count 0 2006.285.19:18:23.28#ibcon#read 6, iclass 29, count 0 2006.285.19:18:23.28#ibcon#end of sib2, iclass 29, count 0 2006.285.19:18:23.28#ibcon#*mode == 0, iclass 29, count 0 2006.285.19:18:23.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.19:18:23.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.19:18:23.28#ibcon#*before write, iclass 29, count 0 2006.285.19:18:23.28#ibcon#enter sib2, iclass 29, count 0 2006.285.19:18:23.28#ibcon#flushed, iclass 29, count 0 2006.285.19:18:23.28#ibcon#about to write, iclass 29, count 0 2006.285.19:18:23.28#ibcon#wrote, iclass 29, count 0 2006.285.19:18:23.28#ibcon#about to read 3, iclass 29, count 0 2006.285.19:18:23.33#ibcon#read 3, iclass 29, count 0 2006.285.19:18:23.33#ibcon#about to read 4, iclass 29, count 0 2006.285.19:18:23.33#ibcon#read 4, iclass 29, count 0 2006.285.19:18:23.33#ibcon#about to read 5, iclass 29, count 0 2006.285.19:18:23.33#ibcon#read 5, iclass 29, count 0 2006.285.19:18:23.33#ibcon#about to read 6, iclass 29, count 0 2006.285.19:18:23.33#ibcon#read 6, iclass 29, count 0 2006.285.19:18:23.33#ibcon#end of sib2, iclass 29, count 0 2006.285.19:18:23.33#ibcon#*after write, iclass 29, count 0 2006.285.19:18:23.33#ibcon#*before return 0, iclass 29, count 0 2006.285.19:18:23.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:18:23.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:18:23.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.19:18:23.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.19:18:23.33$vck44/va=1,7 2006.285.19:18:23.33#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.19:18:23.33#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.19:18:23.33#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:23.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:18:23.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:18:23.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:18:23.33#ibcon#enter wrdev, iclass 31, count 2 2006.285.19:18:23.33#ibcon#first serial, iclass 31, count 2 2006.285.19:18:23.33#ibcon#enter sib2, iclass 31, count 2 2006.285.19:18:23.33#ibcon#flushed, iclass 31, count 2 2006.285.19:18:23.33#ibcon#about to write, iclass 31, count 2 2006.285.19:18:23.33#ibcon#wrote, iclass 31, count 2 2006.285.19:18:23.33#ibcon#about to read 3, iclass 31, count 2 2006.285.19:18:23.35#ibcon#read 3, iclass 31, count 2 2006.285.19:18:23.35#ibcon#about to read 4, iclass 31, count 2 2006.285.19:18:23.35#ibcon#read 4, iclass 31, count 2 2006.285.19:18:23.35#ibcon#about to read 5, iclass 31, count 2 2006.285.19:18:23.35#ibcon#read 5, iclass 31, count 2 2006.285.19:18:23.35#ibcon#about to read 6, iclass 31, count 2 2006.285.19:18:23.35#ibcon#read 6, iclass 31, count 2 2006.285.19:18:23.35#ibcon#end of sib2, iclass 31, count 2 2006.285.19:18:23.35#ibcon#*mode == 0, iclass 31, count 2 2006.285.19:18:23.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.19:18:23.35#ibcon#[25=AT01-07\r\n] 2006.285.19:18:23.35#ibcon#*before write, iclass 31, count 2 2006.285.19:18:23.35#ibcon#enter sib2, iclass 31, count 2 2006.285.19:18:23.35#ibcon#flushed, iclass 31, count 2 2006.285.19:18:23.35#ibcon#about to write, iclass 31, count 2 2006.285.19:18:23.35#ibcon#wrote, iclass 31, count 2 2006.285.19:18:23.35#ibcon#about to read 3, iclass 31, count 2 2006.285.19:18:23.38#ibcon#read 3, iclass 31, count 2 2006.285.19:18:23.38#ibcon#about to read 4, iclass 31, count 2 2006.285.19:18:23.38#ibcon#read 4, iclass 31, count 2 2006.285.19:18:23.38#ibcon#about to read 5, iclass 31, count 2 2006.285.19:18:23.38#ibcon#read 5, iclass 31, count 2 2006.285.19:18:23.38#ibcon#about to read 6, iclass 31, count 2 2006.285.19:18:23.38#ibcon#read 6, iclass 31, count 2 2006.285.19:18:23.38#ibcon#end of sib2, iclass 31, count 2 2006.285.19:18:23.38#ibcon#*after write, iclass 31, count 2 2006.285.19:18:23.38#ibcon#*before return 0, iclass 31, count 2 2006.285.19:18:23.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:18:23.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:18:23.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.19:18:23.38#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:23.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:18:23.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:18:23.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:18:23.50#ibcon#enter wrdev, iclass 31, count 0 2006.285.19:18:23.50#ibcon#first serial, iclass 31, count 0 2006.285.19:18:23.50#ibcon#enter sib2, iclass 31, count 0 2006.285.19:18:23.50#ibcon#flushed, iclass 31, count 0 2006.285.19:18:23.50#ibcon#about to write, iclass 31, count 0 2006.285.19:18:23.50#ibcon#wrote, iclass 31, count 0 2006.285.19:18:23.50#ibcon#about to read 3, iclass 31, count 0 2006.285.19:18:23.52#ibcon#read 3, iclass 31, count 0 2006.285.19:18:23.52#ibcon#about to read 4, iclass 31, count 0 2006.285.19:18:23.52#ibcon#read 4, iclass 31, count 0 2006.285.19:18:23.52#ibcon#about to read 5, iclass 31, count 0 2006.285.19:18:23.52#ibcon#read 5, iclass 31, count 0 2006.285.19:18:23.52#ibcon#about to read 6, iclass 31, count 0 2006.285.19:18:23.52#ibcon#read 6, iclass 31, count 0 2006.285.19:18:23.52#ibcon#end of sib2, iclass 31, count 0 2006.285.19:18:23.52#ibcon#*mode == 0, iclass 31, count 0 2006.285.19:18:23.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.19:18:23.52#ibcon#[25=USB\r\n] 2006.285.19:18:23.52#ibcon#*before write, iclass 31, count 0 2006.285.19:18:23.52#ibcon#enter sib2, iclass 31, count 0 2006.285.19:18:23.52#ibcon#flushed, iclass 31, count 0 2006.285.19:18:23.52#ibcon#about to write, iclass 31, count 0 2006.285.19:18:23.52#ibcon#wrote, iclass 31, count 0 2006.285.19:18:23.52#ibcon#about to read 3, iclass 31, count 0 2006.285.19:18:23.55#ibcon#read 3, iclass 31, count 0 2006.285.19:18:23.55#ibcon#about to read 4, iclass 31, count 0 2006.285.19:18:23.55#ibcon#read 4, iclass 31, count 0 2006.285.19:18:23.55#ibcon#about to read 5, iclass 31, count 0 2006.285.19:18:23.55#ibcon#read 5, iclass 31, count 0 2006.285.19:18:23.55#ibcon#about to read 6, iclass 31, count 0 2006.285.19:18:23.55#ibcon#read 6, iclass 31, count 0 2006.285.19:18:23.55#ibcon#end of sib2, iclass 31, count 0 2006.285.19:18:23.55#ibcon#*after write, iclass 31, count 0 2006.285.19:18:23.55#ibcon#*before return 0, iclass 31, count 0 2006.285.19:18:23.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:18:23.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:18:23.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.19:18:23.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.19:18:23.55$vck44/valo=2,534.99 2006.285.19:18:23.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.19:18:23.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.19:18:23.55#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:23.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:18:23.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:18:23.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:18:23.55#ibcon#enter wrdev, iclass 33, count 0 2006.285.19:18:23.55#ibcon#first serial, iclass 33, count 0 2006.285.19:18:23.55#ibcon#enter sib2, iclass 33, count 0 2006.285.19:18:23.55#ibcon#flushed, iclass 33, count 0 2006.285.19:18:23.55#ibcon#about to write, iclass 33, count 0 2006.285.19:18:23.55#ibcon#wrote, iclass 33, count 0 2006.285.19:18:23.55#ibcon#about to read 3, iclass 33, count 0 2006.285.19:18:23.57#ibcon#read 3, iclass 33, count 0 2006.285.19:18:23.57#ibcon#about to read 4, iclass 33, count 0 2006.285.19:18:23.57#ibcon#read 4, iclass 33, count 0 2006.285.19:18:23.57#ibcon#about to read 5, iclass 33, count 0 2006.285.19:18:23.57#ibcon#read 5, iclass 33, count 0 2006.285.19:18:23.57#ibcon#about to read 6, iclass 33, count 0 2006.285.19:18:23.57#ibcon#read 6, iclass 33, count 0 2006.285.19:18:23.57#ibcon#end of sib2, iclass 33, count 0 2006.285.19:18:23.57#ibcon#*mode == 0, iclass 33, count 0 2006.285.19:18:23.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.19:18:23.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.19:18:23.57#ibcon#*before write, iclass 33, count 0 2006.285.19:18:23.57#ibcon#enter sib2, iclass 33, count 0 2006.285.19:18:23.57#ibcon#flushed, iclass 33, count 0 2006.285.19:18:23.57#ibcon#about to write, iclass 33, count 0 2006.285.19:18:23.57#ibcon#wrote, iclass 33, count 0 2006.285.19:18:23.57#ibcon#about to read 3, iclass 33, count 0 2006.285.19:18:23.61#ibcon#read 3, iclass 33, count 0 2006.285.19:18:23.61#ibcon#about to read 4, iclass 33, count 0 2006.285.19:18:23.61#ibcon#read 4, iclass 33, count 0 2006.285.19:18:23.61#ibcon#about to read 5, iclass 33, count 0 2006.285.19:18:23.61#ibcon#read 5, iclass 33, count 0 2006.285.19:18:23.61#ibcon#about to read 6, iclass 33, count 0 2006.285.19:18:23.61#ibcon#read 6, iclass 33, count 0 2006.285.19:18:23.61#ibcon#end of sib2, iclass 33, count 0 2006.285.19:18:23.61#ibcon#*after write, iclass 33, count 0 2006.285.19:18:23.61#ibcon#*before return 0, iclass 33, count 0 2006.285.19:18:23.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:18:23.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:18:23.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.19:18:23.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.19:18:23.61$vck44/va=2,6 2006.285.19:18:23.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.19:18:23.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.19:18:23.61#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:23.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:18:23.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:18:23.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:18:23.67#ibcon#enter wrdev, iclass 35, count 2 2006.285.19:18:23.67#ibcon#first serial, iclass 35, count 2 2006.285.19:18:23.67#ibcon#enter sib2, iclass 35, count 2 2006.285.19:18:23.67#ibcon#flushed, iclass 35, count 2 2006.285.19:18:23.67#ibcon#about to write, iclass 35, count 2 2006.285.19:18:23.67#ibcon#wrote, iclass 35, count 2 2006.285.19:18:23.67#ibcon#about to read 3, iclass 35, count 2 2006.285.19:18:23.69#ibcon#read 3, iclass 35, count 2 2006.285.19:18:23.69#ibcon#about to read 4, iclass 35, count 2 2006.285.19:18:23.69#ibcon#read 4, iclass 35, count 2 2006.285.19:18:23.69#ibcon#about to read 5, iclass 35, count 2 2006.285.19:18:23.69#ibcon#read 5, iclass 35, count 2 2006.285.19:18:23.69#ibcon#about to read 6, iclass 35, count 2 2006.285.19:18:23.69#ibcon#read 6, iclass 35, count 2 2006.285.19:18:23.69#ibcon#end of sib2, iclass 35, count 2 2006.285.19:18:23.69#ibcon#*mode == 0, iclass 35, count 2 2006.285.19:18:23.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.19:18:23.69#ibcon#[25=AT02-06\r\n] 2006.285.19:18:23.69#ibcon#*before write, iclass 35, count 2 2006.285.19:18:23.69#ibcon#enter sib2, iclass 35, count 2 2006.285.19:18:23.69#ibcon#flushed, iclass 35, count 2 2006.285.19:18:23.69#ibcon#about to write, iclass 35, count 2 2006.285.19:18:23.69#ibcon#wrote, iclass 35, count 2 2006.285.19:18:23.69#ibcon#about to read 3, iclass 35, count 2 2006.285.19:18:23.72#ibcon#read 3, iclass 35, count 2 2006.285.19:18:23.72#ibcon#about to read 4, iclass 35, count 2 2006.285.19:18:23.72#ibcon#read 4, iclass 35, count 2 2006.285.19:18:23.72#ibcon#about to read 5, iclass 35, count 2 2006.285.19:18:23.72#ibcon#read 5, iclass 35, count 2 2006.285.19:18:23.72#ibcon#about to read 6, iclass 35, count 2 2006.285.19:18:23.72#ibcon#read 6, iclass 35, count 2 2006.285.19:18:23.72#ibcon#end of sib2, iclass 35, count 2 2006.285.19:18:23.72#ibcon#*after write, iclass 35, count 2 2006.285.19:18:23.72#ibcon#*before return 0, iclass 35, count 2 2006.285.19:18:23.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:18:23.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:18:23.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.19:18:23.72#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:23.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:18:23.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:18:23.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:18:23.84#ibcon#enter wrdev, iclass 35, count 0 2006.285.19:18:23.84#ibcon#first serial, iclass 35, count 0 2006.285.19:18:23.84#ibcon#enter sib2, iclass 35, count 0 2006.285.19:18:23.84#ibcon#flushed, iclass 35, count 0 2006.285.19:18:23.84#ibcon#about to write, iclass 35, count 0 2006.285.19:18:23.84#ibcon#wrote, iclass 35, count 0 2006.285.19:18:23.84#ibcon#about to read 3, iclass 35, count 0 2006.285.19:18:23.86#ibcon#read 3, iclass 35, count 0 2006.285.19:18:23.86#ibcon#about to read 4, iclass 35, count 0 2006.285.19:18:23.86#ibcon#read 4, iclass 35, count 0 2006.285.19:18:23.86#ibcon#about to read 5, iclass 35, count 0 2006.285.19:18:23.86#ibcon#read 5, iclass 35, count 0 2006.285.19:18:23.86#ibcon#about to read 6, iclass 35, count 0 2006.285.19:18:23.86#ibcon#read 6, iclass 35, count 0 2006.285.19:18:23.86#ibcon#end of sib2, iclass 35, count 0 2006.285.19:18:23.86#ibcon#*mode == 0, iclass 35, count 0 2006.285.19:18:23.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.19:18:23.86#ibcon#[25=USB\r\n] 2006.285.19:18:23.86#ibcon#*before write, iclass 35, count 0 2006.285.19:18:23.86#ibcon#enter sib2, iclass 35, count 0 2006.285.19:18:23.86#ibcon#flushed, iclass 35, count 0 2006.285.19:18:23.86#ibcon#about to write, iclass 35, count 0 2006.285.19:18:23.86#ibcon#wrote, iclass 35, count 0 2006.285.19:18:23.86#ibcon#about to read 3, iclass 35, count 0 2006.285.19:18:23.89#ibcon#read 3, iclass 35, count 0 2006.285.19:18:23.89#ibcon#about to read 4, iclass 35, count 0 2006.285.19:18:23.89#ibcon#read 4, iclass 35, count 0 2006.285.19:18:23.89#ibcon#about to read 5, iclass 35, count 0 2006.285.19:18:23.89#ibcon#read 5, iclass 35, count 0 2006.285.19:18:23.89#ibcon#about to read 6, iclass 35, count 0 2006.285.19:18:23.89#ibcon#read 6, iclass 35, count 0 2006.285.19:18:23.89#ibcon#end of sib2, iclass 35, count 0 2006.285.19:18:23.89#ibcon#*after write, iclass 35, count 0 2006.285.19:18:23.89#ibcon#*before return 0, iclass 35, count 0 2006.285.19:18:23.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:18:23.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:18:23.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.19:18:23.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.19:18:23.89$vck44/valo=3,564.99 2006.285.19:18:23.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.19:18:23.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.19:18:23.89#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:23.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:18:23.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:18:23.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:18:23.89#ibcon#enter wrdev, iclass 37, count 0 2006.285.19:18:23.89#ibcon#first serial, iclass 37, count 0 2006.285.19:18:23.89#ibcon#enter sib2, iclass 37, count 0 2006.285.19:18:23.89#ibcon#flushed, iclass 37, count 0 2006.285.19:18:23.89#ibcon#about to write, iclass 37, count 0 2006.285.19:18:23.89#ibcon#wrote, iclass 37, count 0 2006.285.19:18:23.89#ibcon#about to read 3, iclass 37, count 0 2006.285.19:18:23.91#ibcon#read 3, iclass 37, count 0 2006.285.19:18:23.91#ibcon#about to read 4, iclass 37, count 0 2006.285.19:18:23.91#ibcon#read 4, iclass 37, count 0 2006.285.19:18:23.91#ibcon#about to read 5, iclass 37, count 0 2006.285.19:18:23.91#ibcon#read 5, iclass 37, count 0 2006.285.19:18:23.91#ibcon#about to read 6, iclass 37, count 0 2006.285.19:18:23.91#ibcon#read 6, iclass 37, count 0 2006.285.19:18:23.91#ibcon#end of sib2, iclass 37, count 0 2006.285.19:18:23.91#ibcon#*mode == 0, iclass 37, count 0 2006.285.19:18:23.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.19:18:23.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.19:18:23.91#ibcon#*before write, iclass 37, count 0 2006.285.19:18:23.91#ibcon#enter sib2, iclass 37, count 0 2006.285.19:18:23.91#ibcon#flushed, iclass 37, count 0 2006.285.19:18:23.91#ibcon#about to write, iclass 37, count 0 2006.285.19:18:23.91#ibcon#wrote, iclass 37, count 0 2006.285.19:18:23.91#ibcon#about to read 3, iclass 37, count 0 2006.285.19:18:23.95#ibcon#read 3, iclass 37, count 0 2006.285.19:18:23.95#ibcon#about to read 4, iclass 37, count 0 2006.285.19:18:23.95#ibcon#read 4, iclass 37, count 0 2006.285.19:18:23.95#ibcon#about to read 5, iclass 37, count 0 2006.285.19:18:23.95#ibcon#read 5, iclass 37, count 0 2006.285.19:18:23.95#ibcon#about to read 6, iclass 37, count 0 2006.285.19:18:23.95#ibcon#read 6, iclass 37, count 0 2006.285.19:18:23.95#ibcon#end of sib2, iclass 37, count 0 2006.285.19:18:23.95#ibcon#*after write, iclass 37, count 0 2006.285.19:18:23.95#ibcon#*before return 0, iclass 37, count 0 2006.285.19:18:23.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:18:23.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:18:23.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.19:18:23.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.19:18:23.95$vck44/va=3,7 2006.285.19:18:23.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.19:18:23.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.19:18:23.95#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:23.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:18:24.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:18:24.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:18:24.01#ibcon#enter wrdev, iclass 39, count 2 2006.285.19:18:24.01#ibcon#first serial, iclass 39, count 2 2006.285.19:18:24.01#ibcon#enter sib2, iclass 39, count 2 2006.285.19:18:24.01#ibcon#flushed, iclass 39, count 2 2006.285.19:18:24.01#ibcon#about to write, iclass 39, count 2 2006.285.19:18:24.01#ibcon#wrote, iclass 39, count 2 2006.285.19:18:24.01#ibcon#about to read 3, iclass 39, count 2 2006.285.19:18:24.03#ibcon#read 3, iclass 39, count 2 2006.285.19:18:24.03#ibcon#about to read 4, iclass 39, count 2 2006.285.19:18:24.03#ibcon#read 4, iclass 39, count 2 2006.285.19:18:24.03#ibcon#about to read 5, iclass 39, count 2 2006.285.19:18:24.03#ibcon#read 5, iclass 39, count 2 2006.285.19:18:24.03#ibcon#about to read 6, iclass 39, count 2 2006.285.19:18:24.03#ibcon#read 6, iclass 39, count 2 2006.285.19:18:24.03#ibcon#end of sib2, iclass 39, count 2 2006.285.19:18:24.03#ibcon#*mode == 0, iclass 39, count 2 2006.285.19:18:24.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.19:18:24.03#ibcon#[25=AT03-07\r\n] 2006.285.19:18:24.03#ibcon#*before write, iclass 39, count 2 2006.285.19:18:24.03#ibcon#enter sib2, iclass 39, count 2 2006.285.19:18:24.03#ibcon#flushed, iclass 39, count 2 2006.285.19:18:24.03#ibcon#about to write, iclass 39, count 2 2006.285.19:18:24.03#ibcon#wrote, iclass 39, count 2 2006.285.19:18:24.03#ibcon#about to read 3, iclass 39, count 2 2006.285.19:18:24.06#ibcon#read 3, iclass 39, count 2 2006.285.19:18:24.06#ibcon#about to read 4, iclass 39, count 2 2006.285.19:18:24.06#ibcon#read 4, iclass 39, count 2 2006.285.19:18:24.06#ibcon#about to read 5, iclass 39, count 2 2006.285.19:18:24.06#ibcon#read 5, iclass 39, count 2 2006.285.19:18:24.06#ibcon#about to read 6, iclass 39, count 2 2006.285.19:18:24.06#ibcon#read 6, iclass 39, count 2 2006.285.19:18:24.06#ibcon#end of sib2, iclass 39, count 2 2006.285.19:18:24.06#ibcon#*after write, iclass 39, count 2 2006.285.19:18:24.06#ibcon#*before return 0, iclass 39, count 2 2006.285.19:18:24.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:18:24.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:18:24.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.19:18:24.06#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:24.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:18:24.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:18:24.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:18:24.18#ibcon#enter wrdev, iclass 39, count 0 2006.285.19:18:24.18#ibcon#first serial, iclass 39, count 0 2006.285.19:18:24.18#ibcon#enter sib2, iclass 39, count 0 2006.285.19:18:24.18#ibcon#flushed, iclass 39, count 0 2006.285.19:18:24.18#ibcon#about to write, iclass 39, count 0 2006.285.19:18:24.18#ibcon#wrote, iclass 39, count 0 2006.285.19:18:24.18#ibcon#about to read 3, iclass 39, count 0 2006.285.19:18:24.20#ibcon#read 3, iclass 39, count 0 2006.285.19:18:24.20#ibcon#about to read 4, iclass 39, count 0 2006.285.19:18:24.20#ibcon#read 4, iclass 39, count 0 2006.285.19:18:24.20#ibcon#about to read 5, iclass 39, count 0 2006.285.19:18:24.20#ibcon#read 5, iclass 39, count 0 2006.285.19:18:24.20#ibcon#about to read 6, iclass 39, count 0 2006.285.19:18:24.20#ibcon#read 6, iclass 39, count 0 2006.285.19:18:24.20#ibcon#end of sib2, iclass 39, count 0 2006.285.19:18:24.20#ibcon#*mode == 0, iclass 39, count 0 2006.285.19:18:24.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.19:18:24.20#ibcon#[25=USB\r\n] 2006.285.19:18:24.20#ibcon#*before write, iclass 39, count 0 2006.285.19:18:24.20#ibcon#enter sib2, iclass 39, count 0 2006.285.19:18:24.20#ibcon#flushed, iclass 39, count 0 2006.285.19:18:24.20#ibcon#about to write, iclass 39, count 0 2006.285.19:18:24.20#ibcon#wrote, iclass 39, count 0 2006.285.19:18:24.20#ibcon#about to read 3, iclass 39, count 0 2006.285.19:18:24.23#ibcon#read 3, iclass 39, count 0 2006.285.19:18:24.23#ibcon#about to read 4, iclass 39, count 0 2006.285.19:18:24.23#ibcon#read 4, iclass 39, count 0 2006.285.19:18:24.23#ibcon#about to read 5, iclass 39, count 0 2006.285.19:18:24.23#ibcon#read 5, iclass 39, count 0 2006.285.19:18:24.23#ibcon#about to read 6, iclass 39, count 0 2006.285.19:18:24.23#ibcon#read 6, iclass 39, count 0 2006.285.19:18:24.23#ibcon#end of sib2, iclass 39, count 0 2006.285.19:18:24.23#ibcon#*after write, iclass 39, count 0 2006.285.19:18:24.23#ibcon#*before return 0, iclass 39, count 0 2006.285.19:18:24.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:18:24.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:18:24.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.19:18:24.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.19:18:24.23$vck44/valo=4,624.99 2006.285.19:18:24.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.19:18:24.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.19:18:24.23#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:24.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:18:24.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:18:24.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:18:24.23#ibcon#enter wrdev, iclass 3, count 0 2006.285.19:18:24.23#ibcon#first serial, iclass 3, count 0 2006.285.19:18:24.23#ibcon#enter sib2, iclass 3, count 0 2006.285.19:18:24.23#ibcon#flushed, iclass 3, count 0 2006.285.19:18:24.23#ibcon#about to write, iclass 3, count 0 2006.285.19:18:24.23#ibcon#wrote, iclass 3, count 0 2006.285.19:18:24.23#ibcon#about to read 3, iclass 3, count 0 2006.285.19:18:24.25#ibcon#read 3, iclass 3, count 0 2006.285.19:18:24.25#ibcon#about to read 4, iclass 3, count 0 2006.285.19:18:24.25#ibcon#read 4, iclass 3, count 0 2006.285.19:18:24.25#ibcon#about to read 5, iclass 3, count 0 2006.285.19:18:24.25#ibcon#read 5, iclass 3, count 0 2006.285.19:18:24.25#ibcon#about to read 6, iclass 3, count 0 2006.285.19:18:24.25#ibcon#read 6, iclass 3, count 0 2006.285.19:18:24.25#ibcon#end of sib2, iclass 3, count 0 2006.285.19:18:24.25#ibcon#*mode == 0, iclass 3, count 0 2006.285.19:18:24.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.19:18:24.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.19:18:24.25#ibcon#*before write, iclass 3, count 0 2006.285.19:18:24.25#ibcon#enter sib2, iclass 3, count 0 2006.285.19:18:24.25#ibcon#flushed, iclass 3, count 0 2006.285.19:18:24.25#ibcon#about to write, iclass 3, count 0 2006.285.19:18:24.25#ibcon#wrote, iclass 3, count 0 2006.285.19:18:24.25#ibcon#about to read 3, iclass 3, count 0 2006.285.19:18:24.29#ibcon#read 3, iclass 3, count 0 2006.285.19:18:24.29#ibcon#about to read 4, iclass 3, count 0 2006.285.19:18:24.29#ibcon#read 4, iclass 3, count 0 2006.285.19:18:24.29#ibcon#about to read 5, iclass 3, count 0 2006.285.19:18:24.29#ibcon#read 5, iclass 3, count 0 2006.285.19:18:24.29#ibcon#about to read 6, iclass 3, count 0 2006.285.19:18:24.29#ibcon#read 6, iclass 3, count 0 2006.285.19:18:24.29#ibcon#end of sib2, iclass 3, count 0 2006.285.19:18:24.29#ibcon#*after write, iclass 3, count 0 2006.285.19:18:24.29#ibcon#*before return 0, iclass 3, count 0 2006.285.19:18:24.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:18:24.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:18:24.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.19:18:24.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.19:18:24.29$vck44/va=4,6 2006.285.19:18:24.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.19:18:24.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.19:18:24.29#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:24.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:18:24.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:18:24.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:18:24.35#ibcon#enter wrdev, iclass 5, count 2 2006.285.19:18:24.35#ibcon#first serial, iclass 5, count 2 2006.285.19:18:24.35#ibcon#enter sib2, iclass 5, count 2 2006.285.19:18:24.35#ibcon#flushed, iclass 5, count 2 2006.285.19:18:24.35#ibcon#about to write, iclass 5, count 2 2006.285.19:18:24.35#ibcon#wrote, iclass 5, count 2 2006.285.19:18:24.35#ibcon#about to read 3, iclass 5, count 2 2006.285.19:18:24.37#ibcon#read 3, iclass 5, count 2 2006.285.19:18:24.37#ibcon#about to read 4, iclass 5, count 2 2006.285.19:18:24.37#ibcon#read 4, iclass 5, count 2 2006.285.19:18:24.37#ibcon#about to read 5, iclass 5, count 2 2006.285.19:18:24.37#ibcon#read 5, iclass 5, count 2 2006.285.19:18:24.37#ibcon#about to read 6, iclass 5, count 2 2006.285.19:18:24.37#ibcon#read 6, iclass 5, count 2 2006.285.19:18:24.37#ibcon#end of sib2, iclass 5, count 2 2006.285.19:18:24.37#ibcon#*mode == 0, iclass 5, count 2 2006.285.19:18:24.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.19:18:24.37#ibcon#[25=AT04-06\r\n] 2006.285.19:18:24.37#ibcon#*before write, iclass 5, count 2 2006.285.19:18:24.37#ibcon#enter sib2, iclass 5, count 2 2006.285.19:18:24.37#ibcon#flushed, iclass 5, count 2 2006.285.19:18:24.37#ibcon#about to write, iclass 5, count 2 2006.285.19:18:24.37#ibcon#wrote, iclass 5, count 2 2006.285.19:18:24.37#ibcon#about to read 3, iclass 5, count 2 2006.285.19:18:24.40#ibcon#read 3, iclass 5, count 2 2006.285.19:18:24.77#ibcon#about to read 4, iclass 5, count 2 2006.285.19:18:24.77#ibcon#read 4, iclass 5, count 2 2006.285.19:18:24.77#ibcon#about to read 5, iclass 5, count 2 2006.285.19:18:24.77#ibcon#read 5, iclass 5, count 2 2006.285.19:18:24.77#ibcon#about to read 6, iclass 5, count 2 2006.285.19:18:24.77#ibcon#read 6, iclass 5, count 2 2006.285.19:18:24.77#ibcon#end of sib2, iclass 5, count 2 2006.285.19:18:24.77#ibcon#*after write, iclass 5, count 2 2006.285.19:18:24.77#ibcon#*before return 0, iclass 5, count 2 2006.285.19:18:24.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:18:24.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:18:24.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.19:18:24.77#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:24.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:18:24.88#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:18:24.88#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:18:24.88#ibcon#enter wrdev, iclass 5, count 0 2006.285.19:18:24.88#ibcon#first serial, iclass 5, count 0 2006.285.19:18:24.88#ibcon#enter sib2, iclass 5, count 0 2006.285.19:18:24.88#ibcon#flushed, iclass 5, count 0 2006.285.19:18:24.88#ibcon#about to write, iclass 5, count 0 2006.285.19:18:24.88#ibcon#wrote, iclass 5, count 0 2006.285.19:18:24.88#ibcon#about to read 3, iclass 5, count 0 2006.285.19:18:24.90#ibcon#read 3, iclass 5, count 0 2006.285.19:18:24.90#ibcon#about to read 4, iclass 5, count 0 2006.285.19:18:24.90#ibcon#read 4, iclass 5, count 0 2006.285.19:18:24.90#ibcon#about to read 5, iclass 5, count 0 2006.285.19:18:24.90#ibcon#read 5, iclass 5, count 0 2006.285.19:18:24.90#ibcon#about to read 6, iclass 5, count 0 2006.285.19:18:24.90#ibcon#read 6, iclass 5, count 0 2006.285.19:18:24.90#ibcon#end of sib2, iclass 5, count 0 2006.285.19:18:24.90#ibcon#*mode == 0, iclass 5, count 0 2006.285.19:18:24.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.19:18:24.90#ibcon#[25=USB\r\n] 2006.285.19:18:24.90#ibcon#*before write, iclass 5, count 0 2006.285.19:18:24.90#ibcon#enter sib2, iclass 5, count 0 2006.285.19:18:24.90#ibcon#flushed, iclass 5, count 0 2006.285.19:18:24.90#ibcon#about to write, iclass 5, count 0 2006.285.19:18:24.90#ibcon#wrote, iclass 5, count 0 2006.285.19:18:24.90#ibcon#about to read 3, iclass 5, count 0 2006.285.19:18:24.93#ibcon#read 3, iclass 5, count 0 2006.285.19:18:24.93#ibcon#about to read 4, iclass 5, count 0 2006.285.19:18:24.93#ibcon#read 4, iclass 5, count 0 2006.285.19:18:24.93#ibcon#about to read 5, iclass 5, count 0 2006.285.19:18:24.93#ibcon#read 5, iclass 5, count 0 2006.285.19:18:24.93#ibcon#about to read 6, iclass 5, count 0 2006.285.19:18:24.93#ibcon#read 6, iclass 5, count 0 2006.285.19:18:24.93#ibcon#end of sib2, iclass 5, count 0 2006.285.19:18:24.93#ibcon#*after write, iclass 5, count 0 2006.285.19:18:24.93#ibcon#*before return 0, iclass 5, count 0 2006.285.19:18:24.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:18:24.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:18:24.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.19:18:24.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.19:18:24.93$vck44/valo=5,734.99 2006.285.19:18:24.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.19:18:24.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.19:18:24.93#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:24.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:18:24.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:18:24.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:18:24.93#ibcon#enter wrdev, iclass 7, count 0 2006.285.19:18:24.93#ibcon#first serial, iclass 7, count 0 2006.285.19:18:24.93#ibcon#enter sib2, iclass 7, count 0 2006.285.19:18:24.93#ibcon#flushed, iclass 7, count 0 2006.285.19:18:24.93#ibcon#about to write, iclass 7, count 0 2006.285.19:18:24.93#ibcon#wrote, iclass 7, count 0 2006.285.19:18:24.93#ibcon#about to read 3, iclass 7, count 0 2006.285.19:18:24.95#ibcon#read 3, iclass 7, count 0 2006.285.19:18:24.95#ibcon#about to read 4, iclass 7, count 0 2006.285.19:18:24.95#ibcon#read 4, iclass 7, count 0 2006.285.19:18:24.95#ibcon#about to read 5, iclass 7, count 0 2006.285.19:18:24.95#ibcon#read 5, iclass 7, count 0 2006.285.19:18:24.95#ibcon#about to read 6, iclass 7, count 0 2006.285.19:18:24.95#ibcon#read 6, iclass 7, count 0 2006.285.19:18:24.95#ibcon#end of sib2, iclass 7, count 0 2006.285.19:18:24.95#ibcon#*mode == 0, iclass 7, count 0 2006.285.19:18:24.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.19:18:24.95#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.19:18:24.95#ibcon#*before write, iclass 7, count 0 2006.285.19:18:24.95#ibcon#enter sib2, iclass 7, count 0 2006.285.19:18:24.95#ibcon#flushed, iclass 7, count 0 2006.285.19:18:24.95#ibcon#about to write, iclass 7, count 0 2006.285.19:18:24.95#ibcon#wrote, iclass 7, count 0 2006.285.19:18:24.95#ibcon#about to read 3, iclass 7, count 0 2006.285.19:18:24.99#ibcon#read 3, iclass 7, count 0 2006.285.19:18:24.99#ibcon#about to read 4, iclass 7, count 0 2006.285.19:18:24.99#ibcon#read 4, iclass 7, count 0 2006.285.19:18:24.99#ibcon#about to read 5, iclass 7, count 0 2006.285.19:18:24.99#ibcon#read 5, iclass 7, count 0 2006.285.19:18:24.99#ibcon#about to read 6, iclass 7, count 0 2006.285.19:18:24.99#ibcon#read 6, iclass 7, count 0 2006.285.19:18:24.99#ibcon#end of sib2, iclass 7, count 0 2006.285.19:18:24.99#ibcon#*after write, iclass 7, count 0 2006.285.19:18:24.99#ibcon#*before return 0, iclass 7, count 0 2006.285.19:18:24.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:18:24.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:18:24.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.19:18:24.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.19:18:24.99$vck44/va=5,3 2006.285.19:18:24.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.19:18:24.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.19:18:24.99#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:24.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:18:25.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:18:25.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:18:25.05#ibcon#enter wrdev, iclass 11, count 2 2006.285.19:18:25.05#ibcon#first serial, iclass 11, count 2 2006.285.19:18:25.05#ibcon#enter sib2, iclass 11, count 2 2006.285.19:18:25.05#ibcon#flushed, iclass 11, count 2 2006.285.19:18:25.05#ibcon#about to write, iclass 11, count 2 2006.285.19:18:25.05#ibcon#wrote, iclass 11, count 2 2006.285.19:18:25.05#ibcon#about to read 3, iclass 11, count 2 2006.285.19:18:25.07#ibcon#read 3, iclass 11, count 2 2006.285.19:18:25.07#ibcon#about to read 4, iclass 11, count 2 2006.285.19:18:25.07#ibcon#read 4, iclass 11, count 2 2006.285.19:18:25.07#ibcon#about to read 5, iclass 11, count 2 2006.285.19:18:25.07#ibcon#read 5, iclass 11, count 2 2006.285.19:18:25.07#ibcon#about to read 6, iclass 11, count 2 2006.285.19:18:25.07#ibcon#read 6, iclass 11, count 2 2006.285.19:18:25.07#ibcon#end of sib2, iclass 11, count 2 2006.285.19:18:25.07#ibcon#*mode == 0, iclass 11, count 2 2006.285.19:18:25.07#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.19:18:25.07#ibcon#[25=AT05-03\r\n] 2006.285.19:18:25.07#ibcon#*before write, iclass 11, count 2 2006.285.19:18:25.07#ibcon#enter sib2, iclass 11, count 2 2006.285.19:18:25.07#ibcon#flushed, iclass 11, count 2 2006.285.19:18:25.07#ibcon#about to write, iclass 11, count 2 2006.285.19:18:25.07#ibcon#wrote, iclass 11, count 2 2006.285.19:18:25.07#ibcon#about to read 3, iclass 11, count 2 2006.285.19:18:25.10#ibcon#read 3, iclass 11, count 2 2006.285.19:18:25.10#ibcon#about to read 4, iclass 11, count 2 2006.285.19:18:25.10#ibcon#read 4, iclass 11, count 2 2006.285.19:18:25.10#ibcon#about to read 5, iclass 11, count 2 2006.285.19:18:25.10#ibcon#read 5, iclass 11, count 2 2006.285.19:18:25.10#ibcon#about to read 6, iclass 11, count 2 2006.285.19:18:25.10#ibcon#read 6, iclass 11, count 2 2006.285.19:18:25.10#ibcon#end of sib2, iclass 11, count 2 2006.285.19:18:25.10#ibcon#*after write, iclass 11, count 2 2006.285.19:18:25.10#ibcon#*before return 0, iclass 11, count 2 2006.285.19:18:25.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:18:25.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:18:25.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.19:18:25.10#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:25.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:18:25.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:18:25.36#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:18:25.36#ibcon#enter wrdev, iclass 11, count 0 2006.285.19:18:25.36#ibcon#first serial, iclass 11, count 0 2006.285.19:18:25.36#ibcon#enter sib2, iclass 11, count 0 2006.285.19:18:25.36#ibcon#flushed, iclass 11, count 0 2006.285.19:18:25.36#ibcon#about to write, iclass 11, count 0 2006.285.19:18:25.36#ibcon#wrote, iclass 11, count 0 2006.285.19:18:25.36#ibcon#about to read 3, iclass 11, count 0 2006.285.19:18:25.37#ibcon#read 3, iclass 11, count 0 2006.285.19:18:25.37#ibcon#about to read 4, iclass 11, count 0 2006.285.19:18:25.37#ibcon#read 4, iclass 11, count 0 2006.285.19:18:25.37#ibcon#about to read 5, iclass 11, count 0 2006.285.19:18:25.37#ibcon#read 5, iclass 11, count 0 2006.285.19:18:25.37#ibcon#about to read 6, iclass 11, count 0 2006.285.19:18:25.37#ibcon#read 6, iclass 11, count 0 2006.285.19:18:25.37#ibcon#end of sib2, iclass 11, count 0 2006.285.19:18:25.37#ibcon#*mode == 0, iclass 11, count 0 2006.285.19:18:25.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.19:18:25.37#ibcon#[25=USB\r\n] 2006.285.19:18:25.37#ibcon#*before write, iclass 11, count 0 2006.285.19:18:25.37#ibcon#enter sib2, iclass 11, count 0 2006.285.19:18:25.37#ibcon#flushed, iclass 11, count 0 2006.285.19:18:25.37#ibcon#about to write, iclass 11, count 0 2006.285.19:18:25.37#ibcon#wrote, iclass 11, count 0 2006.285.19:18:25.37#ibcon#about to read 3, iclass 11, count 0 2006.285.19:18:25.40#ibcon#read 3, iclass 11, count 0 2006.285.19:18:25.40#ibcon#about to read 4, iclass 11, count 0 2006.285.19:18:25.40#ibcon#read 4, iclass 11, count 0 2006.285.19:18:25.40#ibcon#about to read 5, iclass 11, count 0 2006.285.19:18:25.40#ibcon#read 5, iclass 11, count 0 2006.285.19:18:25.40#ibcon#about to read 6, iclass 11, count 0 2006.285.19:18:25.40#ibcon#read 6, iclass 11, count 0 2006.285.19:18:25.40#ibcon#end of sib2, iclass 11, count 0 2006.285.19:18:25.40#ibcon#*after write, iclass 11, count 0 2006.285.19:18:25.40#ibcon#*before return 0, iclass 11, count 0 2006.285.19:18:25.40#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:18:25.40#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:18:25.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.19:18:25.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.19:18:25.40$vck44/valo=6,814.99 2006.285.19:18:25.40#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.19:18:25.40#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.19:18:25.40#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:25.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:18:25.40#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:18:25.40#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:18:25.40#ibcon#enter wrdev, iclass 13, count 0 2006.285.19:18:25.40#ibcon#first serial, iclass 13, count 0 2006.285.19:18:25.40#ibcon#enter sib2, iclass 13, count 0 2006.285.19:18:25.40#ibcon#flushed, iclass 13, count 0 2006.285.19:18:25.40#ibcon#about to write, iclass 13, count 0 2006.285.19:18:25.40#ibcon#wrote, iclass 13, count 0 2006.285.19:18:25.40#ibcon#about to read 3, iclass 13, count 0 2006.285.19:18:25.42#ibcon#read 3, iclass 13, count 0 2006.285.19:18:25.42#ibcon#about to read 4, iclass 13, count 0 2006.285.19:18:25.42#ibcon#read 4, iclass 13, count 0 2006.285.19:18:25.42#ibcon#about to read 5, iclass 13, count 0 2006.285.19:18:25.42#ibcon#read 5, iclass 13, count 0 2006.285.19:18:25.42#ibcon#about to read 6, iclass 13, count 0 2006.285.19:18:25.42#ibcon#read 6, iclass 13, count 0 2006.285.19:18:25.42#ibcon#end of sib2, iclass 13, count 0 2006.285.19:18:25.42#ibcon#*mode == 0, iclass 13, count 0 2006.285.19:18:25.42#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.19:18:25.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.19:18:25.42#ibcon#*before write, iclass 13, count 0 2006.285.19:18:25.42#ibcon#enter sib2, iclass 13, count 0 2006.285.19:18:25.42#ibcon#flushed, iclass 13, count 0 2006.285.19:18:25.42#ibcon#about to write, iclass 13, count 0 2006.285.19:18:25.42#ibcon#wrote, iclass 13, count 0 2006.285.19:18:25.42#ibcon#about to read 3, iclass 13, count 0 2006.285.19:18:25.46#ibcon#read 3, iclass 13, count 0 2006.285.19:18:25.46#ibcon#about to read 4, iclass 13, count 0 2006.285.19:18:25.46#ibcon#read 4, iclass 13, count 0 2006.285.19:18:25.46#ibcon#about to read 5, iclass 13, count 0 2006.285.19:18:25.46#ibcon#read 5, iclass 13, count 0 2006.285.19:18:25.46#ibcon#about to read 6, iclass 13, count 0 2006.285.19:18:25.46#ibcon#read 6, iclass 13, count 0 2006.285.19:18:25.46#ibcon#end of sib2, iclass 13, count 0 2006.285.19:18:25.46#ibcon#*after write, iclass 13, count 0 2006.285.19:18:25.46#ibcon#*before return 0, iclass 13, count 0 2006.285.19:18:25.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:18:25.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:18:25.46#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.19:18:25.46#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.19:18:25.46$vck44/va=6,4 2006.285.19:18:25.46#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.19:18:25.46#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.19:18:25.46#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:25.46#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:18:25.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:18:25.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:18:25.52#ibcon#enter wrdev, iclass 15, count 2 2006.285.19:18:25.52#ibcon#first serial, iclass 15, count 2 2006.285.19:18:25.52#ibcon#enter sib2, iclass 15, count 2 2006.285.19:18:25.52#ibcon#flushed, iclass 15, count 2 2006.285.19:18:25.52#ibcon#about to write, iclass 15, count 2 2006.285.19:18:25.52#ibcon#wrote, iclass 15, count 2 2006.285.19:18:25.52#ibcon#about to read 3, iclass 15, count 2 2006.285.19:18:25.54#ibcon#read 3, iclass 15, count 2 2006.285.19:18:25.54#ibcon#about to read 4, iclass 15, count 2 2006.285.19:18:25.54#ibcon#read 4, iclass 15, count 2 2006.285.19:18:25.54#ibcon#about to read 5, iclass 15, count 2 2006.285.19:18:25.54#ibcon#read 5, iclass 15, count 2 2006.285.19:18:25.54#ibcon#about to read 6, iclass 15, count 2 2006.285.19:18:25.54#ibcon#read 6, iclass 15, count 2 2006.285.19:18:25.54#ibcon#end of sib2, iclass 15, count 2 2006.285.19:18:25.54#ibcon#*mode == 0, iclass 15, count 2 2006.285.19:18:25.54#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.19:18:25.54#ibcon#[25=AT06-04\r\n] 2006.285.19:18:25.54#ibcon#*before write, iclass 15, count 2 2006.285.19:18:25.54#ibcon#enter sib2, iclass 15, count 2 2006.285.19:18:25.54#ibcon#flushed, iclass 15, count 2 2006.285.19:18:25.54#ibcon#about to write, iclass 15, count 2 2006.285.19:18:25.54#ibcon#wrote, iclass 15, count 2 2006.285.19:18:25.54#ibcon#about to read 3, iclass 15, count 2 2006.285.19:18:25.57#ibcon#read 3, iclass 15, count 2 2006.285.19:18:25.57#ibcon#about to read 4, iclass 15, count 2 2006.285.19:18:25.57#ibcon#read 4, iclass 15, count 2 2006.285.19:18:25.57#ibcon#about to read 5, iclass 15, count 2 2006.285.19:18:25.57#ibcon#read 5, iclass 15, count 2 2006.285.19:18:25.57#ibcon#about to read 6, iclass 15, count 2 2006.285.19:18:25.57#ibcon#read 6, iclass 15, count 2 2006.285.19:18:25.57#ibcon#end of sib2, iclass 15, count 2 2006.285.19:18:25.57#ibcon#*after write, iclass 15, count 2 2006.285.19:18:25.57#ibcon#*before return 0, iclass 15, count 2 2006.285.19:18:25.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:18:25.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:18:25.57#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.19:18:25.57#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:25.57#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:18:25.69#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:18:25.69#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:18:25.69#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:18:25.69#ibcon#first serial, iclass 15, count 0 2006.285.19:18:25.69#ibcon#enter sib2, iclass 15, count 0 2006.285.19:18:25.69#ibcon#flushed, iclass 15, count 0 2006.285.19:18:25.69#ibcon#about to write, iclass 15, count 0 2006.285.19:18:25.69#ibcon#wrote, iclass 15, count 0 2006.285.19:18:25.69#ibcon#about to read 3, iclass 15, count 0 2006.285.19:18:25.71#ibcon#read 3, iclass 15, count 0 2006.285.19:18:25.71#ibcon#about to read 4, iclass 15, count 0 2006.285.19:18:25.71#ibcon#read 4, iclass 15, count 0 2006.285.19:18:25.71#ibcon#about to read 5, iclass 15, count 0 2006.285.19:18:25.71#ibcon#read 5, iclass 15, count 0 2006.285.19:18:25.71#ibcon#about to read 6, iclass 15, count 0 2006.285.19:18:25.71#ibcon#read 6, iclass 15, count 0 2006.285.19:18:25.71#ibcon#end of sib2, iclass 15, count 0 2006.285.19:18:25.71#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:18:25.71#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:18:25.71#ibcon#[25=USB\r\n] 2006.285.19:18:25.71#ibcon#*before write, iclass 15, count 0 2006.285.19:18:25.71#ibcon#enter sib2, iclass 15, count 0 2006.285.19:18:25.71#ibcon#flushed, iclass 15, count 0 2006.285.19:18:25.71#ibcon#about to write, iclass 15, count 0 2006.285.19:18:25.71#ibcon#wrote, iclass 15, count 0 2006.285.19:18:25.71#ibcon#about to read 3, iclass 15, count 0 2006.285.19:18:25.74#ibcon#read 3, iclass 15, count 0 2006.285.19:18:25.74#ibcon#about to read 4, iclass 15, count 0 2006.285.19:18:25.74#ibcon#read 4, iclass 15, count 0 2006.285.19:18:25.74#ibcon#about to read 5, iclass 15, count 0 2006.285.19:18:25.74#ibcon#read 5, iclass 15, count 0 2006.285.19:18:25.74#ibcon#about to read 6, iclass 15, count 0 2006.285.19:18:25.74#ibcon#read 6, iclass 15, count 0 2006.285.19:18:25.74#ibcon#end of sib2, iclass 15, count 0 2006.285.19:18:25.74#ibcon#*after write, iclass 15, count 0 2006.285.19:18:25.74#ibcon#*before return 0, iclass 15, count 0 2006.285.19:18:25.74#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:18:25.74#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:18:25.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:18:25.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:18:25.74$vck44/valo=7,864.99 2006.285.19:18:25.74#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.19:18:25.74#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.19:18:25.74#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:25.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:18:25.74#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:18:25.74#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:18:25.74#ibcon#enter wrdev, iclass 17, count 0 2006.285.19:18:25.74#ibcon#first serial, iclass 17, count 0 2006.285.19:18:25.74#ibcon#enter sib2, iclass 17, count 0 2006.285.19:18:25.74#ibcon#flushed, iclass 17, count 0 2006.285.19:18:25.74#ibcon#about to write, iclass 17, count 0 2006.285.19:18:25.74#ibcon#wrote, iclass 17, count 0 2006.285.19:18:25.74#ibcon#about to read 3, iclass 17, count 0 2006.285.19:18:25.76#ibcon#read 3, iclass 17, count 0 2006.285.19:18:25.76#ibcon#about to read 4, iclass 17, count 0 2006.285.19:18:25.76#ibcon#read 4, iclass 17, count 0 2006.285.19:18:25.76#ibcon#about to read 5, iclass 17, count 0 2006.285.19:18:25.76#ibcon#read 5, iclass 17, count 0 2006.285.19:18:25.76#ibcon#about to read 6, iclass 17, count 0 2006.285.19:18:25.76#ibcon#read 6, iclass 17, count 0 2006.285.19:18:25.76#ibcon#end of sib2, iclass 17, count 0 2006.285.19:18:25.76#ibcon#*mode == 0, iclass 17, count 0 2006.285.19:18:25.76#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.19:18:25.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.19:18:25.76#ibcon#*before write, iclass 17, count 0 2006.285.19:18:25.76#ibcon#enter sib2, iclass 17, count 0 2006.285.19:18:25.76#ibcon#flushed, iclass 17, count 0 2006.285.19:18:25.76#ibcon#about to write, iclass 17, count 0 2006.285.19:18:25.76#ibcon#wrote, iclass 17, count 0 2006.285.19:18:25.76#ibcon#about to read 3, iclass 17, count 0 2006.285.19:18:25.80#ibcon#read 3, iclass 17, count 0 2006.285.19:18:25.80#ibcon#about to read 4, iclass 17, count 0 2006.285.19:18:25.80#ibcon#read 4, iclass 17, count 0 2006.285.19:18:25.80#ibcon#about to read 5, iclass 17, count 0 2006.285.19:18:25.80#ibcon#read 5, iclass 17, count 0 2006.285.19:18:25.80#ibcon#about to read 6, iclass 17, count 0 2006.285.19:18:25.80#ibcon#read 6, iclass 17, count 0 2006.285.19:18:25.80#ibcon#end of sib2, iclass 17, count 0 2006.285.19:18:25.80#ibcon#*after write, iclass 17, count 0 2006.285.19:18:25.80#ibcon#*before return 0, iclass 17, count 0 2006.285.19:18:25.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:18:25.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:18:25.80#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.19:18:25.80#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.19:18:25.80$vck44/va=7,4 2006.285.19:18:25.80#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.19:18:25.80#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.19:18:25.80#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:25.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:18:25.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:18:25.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:18:25.86#ibcon#enter wrdev, iclass 19, count 2 2006.285.19:18:25.86#ibcon#first serial, iclass 19, count 2 2006.285.19:18:25.86#ibcon#enter sib2, iclass 19, count 2 2006.285.19:18:25.86#ibcon#flushed, iclass 19, count 2 2006.285.19:18:25.86#ibcon#about to write, iclass 19, count 2 2006.285.19:18:25.86#ibcon#wrote, iclass 19, count 2 2006.285.19:18:25.86#ibcon#about to read 3, iclass 19, count 2 2006.285.19:18:25.88#ibcon#read 3, iclass 19, count 2 2006.285.19:18:25.88#ibcon#about to read 4, iclass 19, count 2 2006.285.19:18:25.88#ibcon#read 4, iclass 19, count 2 2006.285.19:18:25.88#ibcon#about to read 5, iclass 19, count 2 2006.285.19:18:25.88#ibcon#read 5, iclass 19, count 2 2006.285.19:18:25.88#ibcon#about to read 6, iclass 19, count 2 2006.285.19:18:25.88#ibcon#read 6, iclass 19, count 2 2006.285.19:18:25.88#ibcon#end of sib2, iclass 19, count 2 2006.285.19:18:25.88#ibcon#*mode == 0, iclass 19, count 2 2006.285.19:18:25.88#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.19:18:25.88#ibcon#[25=AT07-04\r\n] 2006.285.19:18:25.88#ibcon#*before write, iclass 19, count 2 2006.285.19:18:25.88#ibcon#enter sib2, iclass 19, count 2 2006.285.19:18:25.88#ibcon#flushed, iclass 19, count 2 2006.285.19:18:25.88#ibcon#about to write, iclass 19, count 2 2006.285.19:18:25.88#ibcon#wrote, iclass 19, count 2 2006.285.19:18:25.88#ibcon#about to read 3, iclass 19, count 2 2006.285.19:18:25.91#ibcon#read 3, iclass 19, count 2 2006.285.19:18:25.91#ibcon#about to read 4, iclass 19, count 2 2006.285.19:18:25.91#ibcon#read 4, iclass 19, count 2 2006.285.19:18:25.91#ibcon#about to read 5, iclass 19, count 2 2006.285.19:18:25.91#ibcon#read 5, iclass 19, count 2 2006.285.19:18:25.91#ibcon#about to read 6, iclass 19, count 2 2006.285.19:18:25.91#ibcon#read 6, iclass 19, count 2 2006.285.19:18:25.91#ibcon#end of sib2, iclass 19, count 2 2006.285.19:18:25.91#ibcon#*after write, iclass 19, count 2 2006.285.19:18:25.91#ibcon#*before return 0, iclass 19, count 2 2006.285.19:18:25.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:18:25.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:18:25.91#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.19:18:25.91#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:25.91#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:18:26.03#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:18:26.03#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:18:26.03#ibcon#enter wrdev, iclass 19, count 0 2006.285.19:18:26.03#ibcon#first serial, iclass 19, count 0 2006.285.19:18:26.03#ibcon#enter sib2, iclass 19, count 0 2006.285.19:18:26.03#ibcon#flushed, iclass 19, count 0 2006.285.19:18:26.03#ibcon#about to write, iclass 19, count 0 2006.285.19:18:26.03#ibcon#wrote, iclass 19, count 0 2006.285.19:18:26.03#ibcon#about to read 3, iclass 19, count 0 2006.285.19:18:26.05#ibcon#read 3, iclass 19, count 0 2006.285.19:18:26.05#ibcon#about to read 4, iclass 19, count 0 2006.285.19:18:26.05#ibcon#read 4, iclass 19, count 0 2006.285.19:18:26.05#ibcon#about to read 5, iclass 19, count 0 2006.285.19:18:26.05#ibcon#read 5, iclass 19, count 0 2006.285.19:18:26.05#ibcon#about to read 6, iclass 19, count 0 2006.285.19:18:26.05#ibcon#read 6, iclass 19, count 0 2006.285.19:18:26.05#ibcon#end of sib2, iclass 19, count 0 2006.285.19:18:26.05#ibcon#*mode == 0, iclass 19, count 0 2006.285.19:18:26.05#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.19:18:26.05#ibcon#[25=USB\r\n] 2006.285.19:18:26.05#ibcon#*before write, iclass 19, count 0 2006.285.19:18:26.05#ibcon#enter sib2, iclass 19, count 0 2006.285.19:18:26.05#ibcon#flushed, iclass 19, count 0 2006.285.19:18:26.05#ibcon#about to write, iclass 19, count 0 2006.285.19:18:26.05#ibcon#wrote, iclass 19, count 0 2006.285.19:18:26.05#ibcon#about to read 3, iclass 19, count 0 2006.285.19:18:26.08#ibcon#read 3, iclass 19, count 0 2006.285.19:18:26.08#ibcon#about to read 4, iclass 19, count 0 2006.285.19:18:26.08#ibcon#read 4, iclass 19, count 0 2006.285.19:18:26.08#ibcon#about to read 5, iclass 19, count 0 2006.285.19:18:26.08#ibcon#read 5, iclass 19, count 0 2006.285.19:18:26.08#ibcon#about to read 6, iclass 19, count 0 2006.285.19:18:26.08#ibcon#read 6, iclass 19, count 0 2006.285.19:18:26.08#ibcon#end of sib2, iclass 19, count 0 2006.285.19:18:26.08#ibcon#*after write, iclass 19, count 0 2006.285.19:18:26.08#ibcon#*before return 0, iclass 19, count 0 2006.285.19:18:26.08#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:18:26.08#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:18:26.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.19:18:26.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.19:18:26.08$vck44/valo=8,884.99 2006.285.19:18:26.08#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.19:18:26.08#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.19:18:26.08#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:26.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:18:26.08#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:18:26.08#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:18:26.08#ibcon#enter wrdev, iclass 21, count 0 2006.285.19:18:26.08#ibcon#first serial, iclass 21, count 0 2006.285.19:18:26.08#ibcon#enter sib2, iclass 21, count 0 2006.285.19:18:26.08#ibcon#flushed, iclass 21, count 0 2006.285.19:18:26.08#ibcon#about to write, iclass 21, count 0 2006.285.19:18:26.08#ibcon#wrote, iclass 21, count 0 2006.285.19:18:26.08#ibcon#about to read 3, iclass 21, count 0 2006.285.19:18:26.10#ibcon#read 3, iclass 21, count 0 2006.285.19:18:26.10#ibcon#about to read 4, iclass 21, count 0 2006.285.19:18:26.10#ibcon#read 4, iclass 21, count 0 2006.285.19:18:26.10#ibcon#about to read 5, iclass 21, count 0 2006.285.19:18:26.10#ibcon#read 5, iclass 21, count 0 2006.285.19:18:26.10#ibcon#about to read 6, iclass 21, count 0 2006.285.19:18:26.10#ibcon#read 6, iclass 21, count 0 2006.285.19:18:26.10#ibcon#end of sib2, iclass 21, count 0 2006.285.19:18:26.10#ibcon#*mode == 0, iclass 21, count 0 2006.285.19:18:26.10#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.19:18:26.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.19:18:26.10#ibcon#*before write, iclass 21, count 0 2006.285.19:18:26.10#ibcon#enter sib2, iclass 21, count 0 2006.285.19:18:26.10#ibcon#flushed, iclass 21, count 0 2006.285.19:18:26.10#ibcon#about to write, iclass 21, count 0 2006.285.19:18:26.10#ibcon#wrote, iclass 21, count 0 2006.285.19:18:26.10#ibcon#about to read 3, iclass 21, count 0 2006.285.19:18:26.14#ibcon#read 3, iclass 21, count 0 2006.285.19:18:26.14#ibcon#about to read 4, iclass 21, count 0 2006.285.19:18:26.14#ibcon#read 4, iclass 21, count 0 2006.285.19:18:26.14#ibcon#about to read 5, iclass 21, count 0 2006.285.19:18:26.14#ibcon#read 5, iclass 21, count 0 2006.285.19:18:26.14#ibcon#about to read 6, iclass 21, count 0 2006.285.19:18:26.14#ibcon#read 6, iclass 21, count 0 2006.285.19:18:26.14#ibcon#end of sib2, iclass 21, count 0 2006.285.19:18:26.14#ibcon#*after write, iclass 21, count 0 2006.285.19:18:26.14#ibcon#*before return 0, iclass 21, count 0 2006.285.19:18:26.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:18:26.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:18:26.14#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.19:18:26.14#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.19:18:26.14$vck44/va=8,3 2006.285.19:18:26.14#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.19:18:26.14#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.19:18:26.14#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:26.14#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:18:26.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:18:26.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:18:26.20#ibcon#enter wrdev, iclass 23, count 2 2006.285.19:18:26.20#ibcon#first serial, iclass 23, count 2 2006.285.19:18:26.20#ibcon#enter sib2, iclass 23, count 2 2006.285.19:18:26.20#ibcon#flushed, iclass 23, count 2 2006.285.19:18:26.20#ibcon#about to write, iclass 23, count 2 2006.285.19:18:26.20#ibcon#wrote, iclass 23, count 2 2006.285.19:18:26.20#ibcon#about to read 3, iclass 23, count 2 2006.285.19:18:26.22#ibcon#read 3, iclass 23, count 2 2006.285.19:18:26.22#ibcon#about to read 4, iclass 23, count 2 2006.285.19:18:26.22#ibcon#read 4, iclass 23, count 2 2006.285.19:18:26.22#ibcon#about to read 5, iclass 23, count 2 2006.285.19:18:26.22#ibcon#read 5, iclass 23, count 2 2006.285.19:18:26.22#ibcon#about to read 6, iclass 23, count 2 2006.285.19:18:26.22#ibcon#read 6, iclass 23, count 2 2006.285.19:18:26.22#ibcon#end of sib2, iclass 23, count 2 2006.285.19:18:26.22#ibcon#*mode == 0, iclass 23, count 2 2006.285.19:18:26.22#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.19:18:26.22#ibcon#[25=AT08-03\r\n] 2006.285.19:18:26.22#ibcon#*before write, iclass 23, count 2 2006.285.19:18:26.22#ibcon#enter sib2, iclass 23, count 2 2006.285.19:18:26.22#ibcon#flushed, iclass 23, count 2 2006.285.19:18:26.22#ibcon#about to write, iclass 23, count 2 2006.285.19:18:26.22#ibcon#wrote, iclass 23, count 2 2006.285.19:18:26.22#ibcon#about to read 3, iclass 23, count 2 2006.285.19:18:26.25#ibcon#read 3, iclass 23, count 2 2006.285.19:18:26.25#ibcon#about to read 4, iclass 23, count 2 2006.285.19:18:26.25#ibcon#read 4, iclass 23, count 2 2006.285.19:18:26.25#ibcon#about to read 5, iclass 23, count 2 2006.285.19:18:26.25#ibcon#read 5, iclass 23, count 2 2006.285.19:18:26.25#ibcon#about to read 6, iclass 23, count 2 2006.285.19:18:26.25#ibcon#read 6, iclass 23, count 2 2006.285.19:18:26.25#ibcon#end of sib2, iclass 23, count 2 2006.285.19:18:26.25#ibcon#*after write, iclass 23, count 2 2006.285.19:18:26.25#ibcon#*before return 0, iclass 23, count 2 2006.285.19:18:26.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:18:26.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.19:18:26.25#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.19:18:26.25#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:26.25#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:18:26.37#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:18:26.37#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:18:26.37#ibcon#enter wrdev, iclass 23, count 0 2006.285.19:18:26.37#ibcon#first serial, iclass 23, count 0 2006.285.19:18:26.37#ibcon#enter sib2, iclass 23, count 0 2006.285.19:18:26.37#ibcon#flushed, iclass 23, count 0 2006.285.19:18:26.37#ibcon#about to write, iclass 23, count 0 2006.285.19:18:26.37#ibcon#wrote, iclass 23, count 0 2006.285.19:18:26.37#ibcon#about to read 3, iclass 23, count 0 2006.285.19:18:26.39#ibcon#read 3, iclass 23, count 0 2006.285.19:18:26.39#ibcon#about to read 4, iclass 23, count 0 2006.285.19:18:26.39#ibcon#read 4, iclass 23, count 0 2006.285.19:18:26.39#ibcon#about to read 5, iclass 23, count 0 2006.285.19:18:26.39#ibcon#read 5, iclass 23, count 0 2006.285.19:18:26.39#ibcon#about to read 6, iclass 23, count 0 2006.285.19:18:26.39#ibcon#read 6, iclass 23, count 0 2006.285.19:18:26.39#ibcon#end of sib2, iclass 23, count 0 2006.285.19:18:26.39#ibcon#*mode == 0, iclass 23, count 0 2006.285.19:18:26.39#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.19:18:26.39#ibcon#[25=USB\r\n] 2006.285.19:18:26.39#ibcon#*before write, iclass 23, count 0 2006.285.19:18:26.39#ibcon#enter sib2, iclass 23, count 0 2006.285.19:18:26.39#ibcon#flushed, iclass 23, count 0 2006.285.19:18:26.39#ibcon#about to write, iclass 23, count 0 2006.285.19:18:26.39#ibcon#wrote, iclass 23, count 0 2006.285.19:18:26.39#ibcon#about to read 3, iclass 23, count 0 2006.285.19:18:26.42#ibcon#read 3, iclass 23, count 0 2006.285.19:18:26.42#ibcon#about to read 4, iclass 23, count 0 2006.285.19:18:26.42#ibcon#read 4, iclass 23, count 0 2006.285.19:18:26.42#ibcon#about to read 5, iclass 23, count 0 2006.285.19:18:26.42#ibcon#read 5, iclass 23, count 0 2006.285.19:18:26.42#ibcon#about to read 6, iclass 23, count 0 2006.285.19:18:26.42#ibcon#read 6, iclass 23, count 0 2006.285.19:18:26.42#ibcon#end of sib2, iclass 23, count 0 2006.285.19:18:26.42#ibcon#*after write, iclass 23, count 0 2006.285.19:18:26.42#ibcon#*before return 0, iclass 23, count 0 2006.285.19:18:26.42#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:18:26.42#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.19:18:26.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.19:18:26.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.19:18:26.42$vck44/vblo=1,629.99 2006.285.19:18:26.42#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.19:18:26.42#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.19:18:26.42#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:26.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.19:18:26.42#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.19:18:26.42#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.19:18:26.42#ibcon#enter wrdev, iclass 25, count 0 2006.285.19:18:26.42#ibcon#first serial, iclass 25, count 0 2006.285.19:18:26.42#ibcon#enter sib2, iclass 25, count 0 2006.285.19:18:26.42#ibcon#flushed, iclass 25, count 0 2006.285.19:18:26.42#ibcon#about to write, iclass 25, count 0 2006.285.19:18:26.42#ibcon#wrote, iclass 25, count 0 2006.285.19:18:26.42#ibcon#about to read 3, iclass 25, count 0 2006.285.19:18:26.48#ibcon#read 3, iclass 25, count 0 2006.285.19:18:26.48#ibcon#about to read 4, iclass 25, count 0 2006.285.19:18:26.48#ibcon#read 4, iclass 25, count 0 2006.285.19:18:26.48#ibcon#about to read 5, iclass 25, count 0 2006.285.19:18:26.48#ibcon#read 5, iclass 25, count 0 2006.285.19:18:26.48#ibcon#about to read 6, iclass 25, count 0 2006.285.19:18:26.48#ibcon#read 6, iclass 25, count 0 2006.285.19:18:26.48#ibcon#end of sib2, iclass 25, count 0 2006.285.19:18:26.48#ibcon#*mode == 0, iclass 25, count 0 2006.285.19:18:26.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.19:18:26.48#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.19:18:26.48#ibcon#*before write, iclass 25, count 0 2006.285.19:18:26.48#ibcon#enter sib2, iclass 25, count 0 2006.285.19:18:26.48#ibcon#flushed, iclass 25, count 0 2006.285.19:18:26.48#ibcon#about to write, iclass 25, count 0 2006.285.19:18:26.48#ibcon#wrote, iclass 25, count 0 2006.285.19:18:26.48#ibcon#about to read 3, iclass 25, count 0 2006.285.19:18:26.52#ibcon#read 3, iclass 25, count 0 2006.285.19:18:26.52#ibcon#about to read 4, iclass 25, count 0 2006.285.19:18:26.52#ibcon#read 4, iclass 25, count 0 2006.285.19:18:26.52#ibcon#about to read 5, iclass 25, count 0 2006.285.19:18:26.52#ibcon#read 5, iclass 25, count 0 2006.285.19:18:26.52#ibcon#about to read 6, iclass 25, count 0 2006.285.19:18:26.52#ibcon#read 6, iclass 25, count 0 2006.285.19:18:26.52#ibcon#end of sib2, iclass 25, count 0 2006.285.19:18:26.52#ibcon#*after write, iclass 25, count 0 2006.285.19:18:26.52#ibcon#*before return 0, iclass 25, count 0 2006.285.19:18:26.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.19:18:26.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.19:18:26.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.19:18:26.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.19:18:26.52$vck44/vb=1,4 2006.285.19:18:26.52#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.19:18:26.52#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.19:18:26.52#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:26.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.19:18:26.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.19:18:26.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.19:18:26.52#ibcon#enter wrdev, iclass 27, count 2 2006.285.19:18:26.52#ibcon#first serial, iclass 27, count 2 2006.285.19:18:26.52#ibcon#enter sib2, iclass 27, count 2 2006.285.19:18:26.52#ibcon#flushed, iclass 27, count 2 2006.285.19:18:26.52#ibcon#about to write, iclass 27, count 2 2006.285.19:18:26.52#ibcon#wrote, iclass 27, count 2 2006.285.19:18:26.52#ibcon#about to read 3, iclass 27, count 2 2006.285.19:18:26.54#ibcon#read 3, iclass 27, count 2 2006.285.19:18:26.54#ibcon#about to read 4, iclass 27, count 2 2006.285.19:18:26.54#ibcon#read 4, iclass 27, count 2 2006.285.19:18:26.54#ibcon#about to read 5, iclass 27, count 2 2006.285.19:18:26.54#ibcon#read 5, iclass 27, count 2 2006.285.19:18:26.54#ibcon#about to read 6, iclass 27, count 2 2006.285.19:18:26.54#ibcon#read 6, iclass 27, count 2 2006.285.19:18:26.54#ibcon#end of sib2, iclass 27, count 2 2006.285.19:18:26.54#ibcon#*mode == 0, iclass 27, count 2 2006.285.19:18:26.54#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.19:18:26.54#ibcon#[27=AT01-04\r\n] 2006.285.19:18:26.54#ibcon#*before write, iclass 27, count 2 2006.285.19:18:26.54#ibcon#enter sib2, iclass 27, count 2 2006.285.19:18:26.54#ibcon#flushed, iclass 27, count 2 2006.285.19:18:26.54#ibcon#about to write, iclass 27, count 2 2006.285.19:18:26.54#ibcon#wrote, iclass 27, count 2 2006.285.19:18:26.54#ibcon#about to read 3, iclass 27, count 2 2006.285.19:18:26.57#ibcon#read 3, iclass 27, count 2 2006.285.19:18:26.57#ibcon#about to read 4, iclass 27, count 2 2006.285.19:18:26.57#ibcon#read 4, iclass 27, count 2 2006.285.19:18:26.57#ibcon#about to read 5, iclass 27, count 2 2006.285.19:18:26.57#ibcon#read 5, iclass 27, count 2 2006.285.19:18:26.57#ibcon#about to read 6, iclass 27, count 2 2006.285.19:18:26.57#ibcon#read 6, iclass 27, count 2 2006.285.19:18:26.57#ibcon#end of sib2, iclass 27, count 2 2006.285.19:18:26.57#ibcon#*after write, iclass 27, count 2 2006.285.19:18:26.57#ibcon#*before return 0, iclass 27, count 2 2006.285.19:18:26.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.19:18:26.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.19:18:26.57#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.19:18:26.57#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:26.57#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.19:18:26.69#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.19:18:26.69#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.19:18:26.69#ibcon#enter wrdev, iclass 27, count 0 2006.285.19:18:26.69#ibcon#first serial, iclass 27, count 0 2006.285.19:18:26.69#ibcon#enter sib2, iclass 27, count 0 2006.285.19:18:26.69#ibcon#flushed, iclass 27, count 0 2006.285.19:18:26.69#ibcon#about to write, iclass 27, count 0 2006.285.19:18:26.69#ibcon#wrote, iclass 27, count 0 2006.285.19:18:26.69#ibcon#about to read 3, iclass 27, count 0 2006.285.19:18:26.71#ibcon#read 3, iclass 27, count 0 2006.285.19:18:26.71#ibcon#about to read 4, iclass 27, count 0 2006.285.19:18:26.71#ibcon#read 4, iclass 27, count 0 2006.285.19:18:26.71#ibcon#about to read 5, iclass 27, count 0 2006.285.19:18:26.71#ibcon#read 5, iclass 27, count 0 2006.285.19:18:26.71#ibcon#about to read 6, iclass 27, count 0 2006.285.19:18:26.71#ibcon#read 6, iclass 27, count 0 2006.285.19:18:26.71#ibcon#end of sib2, iclass 27, count 0 2006.285.19:18:26.71#ibcon#*mode == 0, iclass 27, count 0 2006.285.19:18:26.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.19:18:26.71#ibcon#[27=USB\r\n] 2006.285.19:18:26.71#ibcon#*before write, iclass 27, count 0 2006.285.19:18:26.71#ibcon#enter sib2, iclass 27, count 0 2006.285.19:18:26.71#ibcon#flushed, iclass 27, count 0 2006.285.19:18:26.71#ibcon#about to write, iclass 27, count 0 2006.285.19:18:26.71#ibcon#wrote, iclass 27, count 0 2006.285.19:18:26.71#ibcon#about to read 3, iclass 27, count 0 2006.285.19:18:26.74#ibcon#read 3, iclass 27, count 0 2006.285.19:18:26.74#ibcon#about to read 4, iclass 27, count 0 2006.285.19:18:26.74#ibcon#read 4, iclass 27, count 0 2006.285.19:18:26.74#ibcon#about to read 5, iclass 27, count 0 2006.285.19:18:26.74#ibcon#read 5, iclass 27, count 0 2006.285.19:18:26.74#ibcon#about to read 6, iclass 27, count 0 2006.285.19:18:26.74#ibcon#read 6, iclass 27, count 0 2006.285.19:18:26.74#ibcon#end of sib2, iclass 27, count 0 2006.285.19:18:26.74#ibcon#*after write, iclass 27, count 0 2006.285.19:18:26.74#ibcon#*before return 0, iclass 27, count 0 2006.285.19:18:26.74#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.19:18:26.74#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.19:18:26.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.19:18:26.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.19:18:26.74$vck44/vblo=2,634.99 2006.285.19:18:26.74#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.19:18:26.74#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.19:18:26.74#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:26.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:18:26.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:18:26.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:18:26.74#ibcon#enter wrdev, iclass 29, count 0 2006.285.19:18:26.74#ibcon#first serial, iclass 29, count 0 2006.285.19:18:26.74#ibcon#enter sib2, iclass 29, count 0 2006.285.19:18:26.74#ibcon#flushed, iclass 29, count 0 2006.285.19:18:26.74#ibcon#about to write, iclass 29, count 0 2006.285.19:18:26.74#ibcon#wrote, iclass 29, count 0 2006.285.19:18:26.74#ibcon#about to read 3, iclass 29, count 0 2006.285.19:18:26.76#ibcon#read 3, iclass 29, count 0 2006.285.19:18:26.76#ibcon#about to read 4, iclass 29, count 0 2006.285.19:18:26.76#ibcon#read 4, iclass 29, count 0 2006.285.19:18:26.76#ibcon#about to read 5, iclass 29, count 0 2006.285.19:18:26.76#ibcon#read 5, iclass 29, count 0 2006.285.19:18:26.76#ibcon#about to read 6, iclass 29, count 0 2006.285.19:18:26.76#ibcon#read 6, iclass 29, count 0 2006.285.19:18:26.76#ibcon#end of sib2, iclass 29, count 0 2006.285.19:18:26.76#ibcon#*mode == 0, iclass 29, count 0 2006.285.19:18:26.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.19:18:26.76#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.19:18:26.76#ibcon#*before write, iclass 29, count 0 2006.285.19:18:26.76#ibcon#enter sib2, iclass 29, count 0 2006.285.19:18:26.76#ibcon#flushed, iclass 29, count 0 2006.285.19:18:26.76#ibcon#about to write, iclass 29, count 0 2006.285.19:18:26.76#ibcon#wrote, iclass 29, count 0 2006.285.19:18:26.76#ibcon#about to read 3, iclass 29, count 0 2006.285.19:18:26.80#ibcon#read 3, iclass 29, count 0 2006.285.19:18:26.80#ibcon#about to read 4, iclass 29, count 0 2006.285.19:18:26.80#ibcon#read 4, iclass 29, count 0 2006.285.19:18:26.80#ibcon#about to read 5, iclass 29, count 0 2006.285.19:18:26.80#ibcon#read 5, iclass 29, count 0 2006.285.19:18:26.80#ibcon#about to read 6, iclass 29, count 0 2006.285.19:18:26.80#ibcon#read 6, iclass 29, count 0 2006.285.19:18:26.80#ibcon#end of sib2, iclass 29, count 0 2006.285.19:18:26.80#ibcon#*after write, iclass 29, count 0 2006.285.19:18:26.80#ibcon#*before return 0, iclass 29, count 0 2006.285.19:18:26.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:18:26.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.19:18:26.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.19:18:26.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.19:18:26.80$vck44/vb=2,5 2006.285.19:18:26.80#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.19:18:26.80#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.19:18:26.80#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:26.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:18:26.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:18:26.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:18:26.86#ibcon#enter wrdev, iclass 31, count 2 2006.285.19:18:26.86#ibcon#first serial, iclass 31, count 2 2006.285.19:18:26.86#ibcon#enter sib2, iclass 31, count 2 2006.285.19:18:26.86#ibcon#flushed, iclass 31, count 2 2006.285.19:18:26.86#ibcon#about to write, iclass 31, count 2 2006.285.19:18:26.86#ibcon#wrote, iclass 31, count 2 2006.285.19:18:26.86#ibcon#about to read 3, iclass 31, count 2 2006.285.19:18:26.88#ibcon#read 3, iclass 31, count 2 2006.285.19:18:26.88#ibcon#about to read 4, iclass 31, count 2 2006.285.19:18:26.88#ibcon#read 4, iclass 31, count 2 2006.285.19:18:26.88#ibcon#about to read 5, iclass 31, count 2 2006.285.19:18:26.88#ibcon#read 5, iclass 31, count 2 2006.285.19:18:26.88#ibcon#about to read 6, iclass 31, count 2 2006.285.19:18:26.88#ibcon#read 6, iclass 31, count 2 2006.285.19:18:26.88#ibcon#end of sib2, iclass 31, count 2 2006.285.19:18:26.88#ibcon#*mode == 0, iclass 31, count 2 2006.285.19:18:26.88#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.19:18:26.88#ibcon#[27=AT02-05\r\n] 2006.285.19:18:26.88#ibcon#*before write, iclass 31, count 2 2006.285.19:18:26.88#ibcon#enter sib2, iclass 31, count 2 2006.285.19:18:26.88#ibcon#flushed, iclass 31, count 2 2006.285.19:18:26.88#ibcon#about to write, iclass 31, count 2 2006.285.19:18:26.88#ibcon#wrote, iclass 31, count 2 2006.285.19:18:26.88#ibcon#about to read 3, iclass 31, count 2 2006.285.19:18:26.91#ibcon#read 3, iclass 31, count 2 2006.285.19:18:26.91#ibcon#about to read 4, iclass 31, count 2 2006.285.19:18:26.91#ibcon#read 4, iclass 31, count 2 2006.285.19:18:26.91#ibcon#about to read 5, iclass 31, count 2 2006.285.19:18:26.91#ibcon#read 5, iclass 31, count 2 2006.285.19:18:26.91#ibcon#about to read 6, iclass 31, count 2 2006.285.19:18:26.91#ibcon#read 6, iclass 31, count 2 2006.285.19:18:26.91#ibcon#end of sib2, iclass 31, count 2 2006.285.19:18:26.91#ibcon#*after write, iclass 31, count 2 2006.285.19:18:26.91#ibcon#*before return 0, iclass 31, count 2 2006.285.19:18:26.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:18:26.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.19:18:26.91#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.19:18:26.91#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:26.91#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:18:27.03#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:18:27.03#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:18:27.03#ibcon#enter wrdev, iclass 31, count 0 2006.285.19:18:27.03#ibcon#first serial, iclass 31, count 0 2006.285.19:18:27.03#ibcon#enter sib2, iclass 31, count 0 2006.285.19:18:27.03#ibcon#flushed, iclass 31, count 0 2006.285.19:18:27.03#ibcon#about to write, iclass 31, count 0 2006.285.19:18:27.03#ibcon#wrote, iclass 31, count 0 2006.285.19:18:27.03#ibcon#about to read 3, iclass 31, count 0 2006.285.19:18:27.05#ibcon#read 3, iclass 31, count 0 2006.285.19:18:27.05#ibcon#about to read 4, iclass 31, count 0 2006.285.19:18:27.05#ibcon#read 4, iclass 31, count 0 2006.285.19:18:27.05#ibcon#about to read 5, iclass 31, count 0 2006.285.19:18:27.05#ibcon#read 5, iclass 31, count 0 2006.285.19:18:27.05#ibcon#about to read 6, iclass 31, count 0 2006.285.19:18:27.05#ibcon#read 6, iclass 31, count 0 2006.285.19:18:27.05#ibcon#end of sib2, iclass 31, count 0 2006.285.19:18:27.05#ibcon#*mode == 0, iclass 31, count 0 2006.285.19:18:27.05#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.19:18:27.05#ibcon#[27=USB\r\n] 2006.285.19:18:27.05#ibcon#*before write, iclass 31, count 0 2006.285.19:18:27.05#ibcon#enter sib2, iclass 31, count 0 2006.285.19:18:27.05#ibcon#flushed, iclass 31, count 0 2006.285.19:18:27.05#ibcon#about to write, iclass 31, count 0 2006.285.19:18:27.05#ibcon#wrote, iclass 31, count 0 2006.285.19:18:27.05#ibcon#about to read 3, iclass 31, count 0 2006.285.19:18:27.08#ibcon#read 3, iclass 31, count 0 2006.285.19:18:27.08#ibcon#about to read 4, iclass 31, count 0 2006.285.19:18:27.08#ibcon#read 4, iclass 31, count 0 2006.285.19:18:27.08#ibcon#about to read 5, iclass 31, count 0 2006.285.19:18:27.08#ibcon#read 5, iclass 31, count 0 2006.285.19:18:27.08#ibcon#about to read 6, iclass 31, count 0 2006.285.19:18:27.08#ibcon#read 6, iclass 31, count 0 2006.285.19:18:27.08#ibcon#end of sib2, iclass 31, count 0 2006.285.19:18:27.08#ibcon#*after write, iclass 31, count 0 2006.285.19:18:27.08#ibcon#*before return 0, iclass 31, count 0 2006.285.19:18:27.08#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:18:27.08#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.19:18:27.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.19:18:27.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.19:18:27.08$vck44/vblo=3,649.99 2006.285.19:18:27.08#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.19:18:27.08#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.19:18:27.08#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:27.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:18:27.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:18:27.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:18:27.08#ibcon#enter wrdev, iclass 33, count 0 2006.285.19:18:27.08#ibcon#first serial, iclass 33, count 0 2006.285.19:18:27.08#ibcon#enter sib2, iclass 33, count 0 2006.285.19:18:27.08#ibcon#flushed, iclass 33, count 0 2006.285.19:18:27.08#ibcon#about to write, iclass 33, count 0 2006.285.19:18:27.08#ibcon#wrote, iclass 33, count 0 2006.285.19:18:27.08#ibcon#about to read 3, iclass 33, count 0 2006.285.19:18:27.10#ibcon#read 3, iclass 33, count 0 2006.285.19:18:27.10#ibcon#about to read 4, iclass 33, count 0 2006.285.19:18:27.10#ibcon#read 4, iclass 33, count 0 2006.285.19:18:27.10#ibcon#about to read 5, iclass 33, count 0 2006.285.19:18:27.10#ibcon#read 5, iclass 33, count 0 2006.285.19:18:27.10#ibcon#about to read 6, iclass 33, count 0 2006.285.19:18:27.10#ibcon#read 6, iclass 33, count 0 2006.285.19:18:27.10#ibcon#end of sib2, iclass 33, count 0 2006.285.19:18:27.10#ibcon#*mode == 0, iclass 33, count 0 2006.285.19:18:27.10#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.19:18:27.10#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.19:18:27.10#ibcon#*before write, iclass 33, count 0 2006.285.19:18:27.10#ibcon#enter sib2, iclass 33, count 0 2006.285.19:18:27.10#ibcon#flushed, iclass 33, count 0 2006.285.19:18:27.10#ibcon#about to write, iclass 33, count 0 2006.285.19:18:27.10#ibcon#wrote, iclass 33, count 0 2006.285.19:18:27.10#ibcon#about to read 3, iclass 33, count 0 2006.285.19:18:27.14#ibcon#read 3, iclass 33, count 0 2006.285.19:18:27.14#ibcon#about to read 4, iclass 33, count 0 2006.285.19:18:27.14#ibcon#read 4, iclass 33, count 0 2006.285.19:18:27.14#ibcon#about to read 5, iclass 33, count 0 2006.285.19:18:27.14#ibcon#read 5, iclass 33, count 0 2006.285.19:18:27.14#ibcon#about to read 6, iclass 33, count 0 2006.285.19:18:27.14#ibcon#read 6, iclass 33, count 0 2006.285.19:18:27.14#ibcon#end of sib2, iclass 33, count 0 2006.285.19:18:27.14#ibcon#*after write, iclass 33, count 0 2006.285.19:18:27.14#ibcon#*before return 0, iclass 33, count 0 2006.285.19:18:27.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:18:27.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.19:18:27.14#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.19:18:27.14#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.19:18:27.14$vck44/vb=3,4 2006.285.19:18:27.14#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.19:18:27.14#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.19:18:27.14#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:27.14#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:18:27.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:18:27.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:18:27.20#ibcon#enter wrdev, iclass 35, count 2 2006.285.19:18:27.20#ibcon#first serial, iclass 35, count 2 2006.285.19:18:27.20#ibcon#enter sib2, iclass 35, count 2 2006.285.19:18:27.20#ibcon#flushed, iclass 35, count 2 2006.285.19:18:27.20#ibcon#about to write, iclass 35, count 2 2006.285.19:18:27.20#ibcon#wrote, iclass 35, count 2 2006.285.19:18:27.20#ibcon#about to read 3, iclass 35, count 2 2006.285.19:18:27.22#ibcon#read 3, iclass 35, count 2 2006.285.19:18:27.22#ibcon#about to read 4, iclass 35, count 2 2006.285.19:18:27.22#ibcon#read 4, iclass 35, count 2 2006.285.19:18:27.22#ibcon#about to read 5, iclass 35, count 2 2006.285.19:18:27.22#ibcon#read 5, iclass 35, count 2 2006.285.19:18:27.22#ibcon#about to read 6, iclass 35, count 2 2006.285.19:18:27.22#ibcon#read 6, iclass 35, count 2 2006.285.19:18:27.22#ibcon#end of sib2, iclass 35, count 2 2006.285.19:18:27.22#ibcon#*mode == 0, iclass 35, count 2 2006.285.19:18:27.22#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.19:18:27.22#ibcon#[27=AT03-04\r\n] 2006.285.19:18:27.22#ibcon#*before write, iclass 35, count 2 2006.285.19:18:27.22#ibcon#enter sib2, iclass 35, count 2 2006.285.19:18:27.22#ibcon#flushed, iclass 35, count 2 2006.285.19:18:27.22#ibcon#about to write, iclass 35, count 2 2006.285.19:18:27.22#ibcon#wrote, iclass 35, count 2 2006.285.19:18:27.22#ibcon#about to read 3, iclass 35, count 2 2006.285.19:18:27.25#ibcon#read 3, iclass 35, count 2 2006.285.19:18:27.25#ibcon#about to read 4, iclass 35, count 2 2006.285.19:18:27.25#ibcon#read 4, iclass 35, count 2 2006.285.19:18:27.25#ibcon#about to read 5, iclass 35, count 2 2006.285.19:18:27.25#ibcon#read 5, iclass 35, count 2 2006.285.19:18:27.25#ibcon#about to read 6, iclass 35, count 2 2006.285.19:18:27.25#ibcon#read 6, iclass 35, count 2 2006.285.19:18:27.25#ibcon#end of sib2, iclass 35, count 2 2006.285.19:18:27.25#ibcon#*after write, iclass 35, count 2 2006.285.19:18:27.25#ibcon#*before return 0, iclass 35, count 2 2006.285.19:18:27.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:18:27.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.19:18:27.25#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.19:18:27.25#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:27.25#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:18:27.37#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:18:27.37#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:18:27.37#ibcon#enter wrdev, iclass 35, count 0 2006.285.19:18:27.37#ibcon#first serial, iclass 35, count 0 2006.285.19:18:27.37#ibcon#enter sib2, iclass 35, count 0 2006.285.19:18:27.37#ibcon#flushed, iclass 35, count 0 2006.285.19:18:27.37#ibcon#about to write, iclass 35, count 0 2006.285.19:18:27.37#ibcon#wrote, iclass 35, count 0 2006.285.19:18:27.37#ibcon#about to read 3, iclass 35, count 0 2006.285.19:18:27.39#ibcon#read 3, iclass 35, count 0 2006.285.19:18:27.39#ibcon#about to read 4, iclass 35, count 0 2006.285.19:18:27.39#ibcon#read 4, iclass 35, count 0 2006.285.19:18:27.39#ibcon#about to read 5, iclass 35, count 0 2006.285.19:18:27.39#ibcon#read 5, iclass 35, count 0 2006.285.19:18:27.39#ibcon#about to read 6, iclass 35, count 0 2006.285.19:18:27.39#ibcon#read 6, iclass 35, count 0 2006.285.19:18:27.39#ibcon#end of sib2, iclass 35, count 0 2006.285.19:18:27.39#ibcon#*mode == 0, iclass 35, count 0 2006.285.19:18:27.39#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.19:18:27.39#ibcon#[27=USB\r\n] 2006.285.19:18:27.39#ibcon#*before write, iclass 35, count 0 2006.285.19:18:27.39#ibcon#enter sib2, iclass 35, count 0 2006.285.19:18:27.39#ibcon#flushed, iclass 35, count 0 2006.285.19:18:27.39#ibcon#about to write, iclass 35, count 0 2006.285.19:18:27.39#ibcon#wrote, iclass 35, count 0 2006.285.19:18:27.39#ibcon#about to read 3, iclass 35, count 0 2006.285.19:18:27.42#ibcon#read 3, iclass 35, count 0 2006.285.19:18:27.42#ibcon#about to read 4, iclass 35, count 0 2006.285.19:18:27.42#ibcon#read 4, iclass 35, count 0 2006.285.19:18:27.42#ibcon#about to read 5, iclass 35, count 0 2006.285.19:18:27.42#ibcon#read 5, iclass 35, count 0 2006.285.19:18:27.42#ibcon#about to read 6, iclass 35, count 0 2006.285.19:18:27.42#ibcon#read 6, iclass 35, count 0 2006.285.19:18:27.42#ibcon#end of sib2, iclass 35, count 0 2006.285.19:18:27.42#ibcon#*after write, iclass 35, count 0 2006.285.19:18:27.42#ibcon#*before return 0, iclass 35, count 0 2006.285.19:18:27.42#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:18:27.42#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.19:18:27.42#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.19:18:27.42#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.19:18:27.42$vck44/vblo=4,679.99 2006.285.19:18:27.42#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.19:18:27.42#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.19:18:27.42#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:27.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:18:27.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:18:27.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:18:27.42#ibcon#enter wrdev, iclass 37, count 0 2006.285.19:18:27.42#ibcon#first serial, iclass 37, count 0 2006.285.19:18:27.42#ibcon#enter sib2, iclass 37, count 0 2006.285.19:18:27.42#ibcon#flushed, iclass 37, count 0 2006.285.19:18:27.42#ibcon#about to write, iclass 37, count 0 2006.285.19:18:27.42#ibcon#wrote, iclass 37, count 0 2006.285.19:18:27.42#ibcon#about to read 3, iclass 37, count 0 2006.285.19:18:27.44#ibcon#read 3, iclass 37, count 0 2006.285.19:18:27.52#ibcon#about to read 4, iclass 37, count 0 2006.285.19:18:27.52#ibcon#read 4, iclass 37, count 0 2006.285.19:18:27.52#ibcon#about to read 5, iclass 37, count 0 2006.285.19:18:27.52#ibcon#read 5, iclass 37, count 0 2006.285.19:18:27.52#ibcon#about to read 6, iclass 37, count 0 2006.285.19:18:27.52#ibcon#read 6, iclass 37, count 0 2006.285.19:18:27.52#ibcon#end of sib2, iclass 37, count 0 2006.285.19:18:27.52#ibcon#*mode == 0, iclass 37, count 0 2006.285.19:18:27.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.19:18:27.52#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.19:18:27.52#ibcon#*before write, iclass 37, count 0 2006.285.19:18:27.52#ibcon#enter sib2, iclass 37, count 0 2006.285.19:18:27.52#ibcon#flushed, iclass 37, count 0 2006.285.19:18:27.52#ibcon#about to write, iclass 37, count 0 2006.285.19:18:27.52#ibcon#wrote, iclass 37, count 0 2006.285.19:18:27.52#ibcon#about to read 3, iclass 37, count 0 2006.285.19:18:27.57#ibcon#read 3, iclass 37, count 0 2006.285.19:18:27.57#ibcon#about to read 4, iclass 37, count 0 2006.285.19:18:27.57#ibcon#read 4, iclass 37, count 0 2006.285.19:18:27.57#ibcon#about to read 5, iclass 37, count 0 2006.285.19:18:27.57#ibcon#read 5, iclass 37, count 0 2006.285.19:18:27.57#ibcon#about to read 6, iclass 37, count 0 2006.285.19:18:27.57#ibcon#read 6, iclass 37, count 0 2006.285.19:18:27.57#ibcon#end of sib2, iclass 37, count 0 2006.285.19:18:27.57#ibcon#*after write, iclass 37, count 0 2006.285.19:18:27.57#ibcon#*before return 0, iclass 37, count 0 2006.285.19:18:27.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:18:27.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.19:18:27.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.19:18:27.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.19:18:27.57$vck44/vb=4,5 2006.285.19:18:27.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.19:18:27.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.19:18:27.57#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:27.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:18:27.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:18:27.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:18:27.57#ibcon#enter wrdev, iclass 39, count 2 2006.285.19:18:27.57#ibcon#first serial, iclass 39, count 2 2006.285.19:18:27.57#ibcon#enter sib2, iclass 39, count 2 2006.285.19:18:27.57#ibcon#flushed, iclass 39, count 2 2006.285.19:18:27.57#ibcon#about to write, iclass 39, count 2 2006.285.19:18:27.57#ibcon#wrote, iclass 39, count 2 2006.285.19:18:27.57#ibcon#about to read 3, iclass 39, count 2 2006.285.19:18:27.59#ibcon#read 3, iclass 39, count 2 2006.285.19:18:27.59#ibcon#about to read 4, iclass 39, count 2 2006.285.19:18:27.59#ibcon#read 4, iclass 39, count 2 2006.285.19:18:27.59#ibcon#about to read 5, iclass 39, count 2 2006.285.19:18:27.59#ibcon#read 5, iclass 39, count 2 2006.285.19:18:27.59#ibcon#about to read 6, iclass 39, count 2 2006.285.19:18:27.59#ibcon#read 6, iclass 39, count 2 2006.285.19:18:27.59#ibcon#end of sib2, iclass 39, count 2 2006.285.19:18:27.59#ibcon#*mode == 0, iclass 39, count 2 2006.285.19:18:27.59#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.19:18:27.59#ibcon#[27=AT04-05\r\n] 2006.285.19:18:27.59#ibcon#*before write, iclass 39, count 2 2006.285.19:18:27.59#ibcon#enter sib2, iclass 39, count 2 2006.285.19:18:27.59#ibcon#flushed, iclass 39, count 2 2006.285.19:18:27.59#ibcon#about to write, iclass 39, count 2 2006.285.19:18:27.59#ibcon#wrote, iclass 39, count 2 2006.285.19:18:27.59#ibcon#about to read 3, iclass 39, count 2 2006.285.19:18:27.62#ibcon#read 3, iclass 39, count 2 2006.285.19:18:27.62#ibcon#about to read 4, iclass 39, count 2 2006.285.19:18:27.62#ibcon#read 4, iclass 39, count 2 2006.285.19:18:27.62#ibcon#about to read 5, iclass 39, count 2 2006.285.19:18:27.62#ibcon#read 5, iclass 39, count 2 2006.285.19:18:27.62#ibcon#about to read 6, iclass 39, count 2 2006.285.19:18:27.62#ibcon#read 6, iclass 39, count 2 2006.285.19:18:27.62#ibcon#end of sib2, iclass 39, count 2 2006.285.19:18:27.62#ibcon#*after write, iclass 39, count 2 2006.285.19:18:27.62#ibcon#*before return 0, iclass 39, count 2 2006.285.19:18:27.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:18:27.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.19:18:27.62#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.19:18:27.62#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:27.62#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:18:27.74#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:18:27.74#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:18:27.74#ibcon#enter wrdev, iclass 39, count 0 2006.285.19:18:27.74#ibcon#first serial, iclass 39, count 0 2006.285.19:18:27.74#ibcon#enter sib2, iclass 39, count 0 2006.285.19:18:27.74#ibcon#flushed, iclass 39, count 0 2006.285.19:18:27.74#ibcon#about to write, iclass 39, count 0 2006.285.19:18:27.74#ibcon#wrote, iclass 39, count 0 2006.285.19:18:27.74#ibcon#about to read 3, iclass 39, count 0 2006.285.19:18:27.76#ibcon#read 3, iclass 39, count 0 2006.285.19:18:27.76#ibcon#about to read 4, iclass 39, count 0 2006.285.19:18:27.76#ibcon#read 4, iclass 39, count 0 2006.285.19:18:27.76#ibcon#about to read 5, iclass 39, count 0 2006.285.19:18:27.76#ibcon#read 5, iclass 39, count 0 2006.285.19:18:27.76#ibcon#about to read 6, iclass 39, count 0 2006.285.19:18:27.76#ibcon#read 6, iclass 39, count 0 2006.285.19:18:27.76#ibcon#end of sib2, iclass 39, count 0 2006.285.19:18:27.76#ibcon#*mode == 0, iclass 39, count 0 2006.285.19:18:27.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.19:18:27.76#ibcon#[27=USB\r\n] 2006.285.19:18:27.76#ibcon#*before write, iclass 39, count 0 2006.285.19:18:27.76#ibcon#enter sib2, iclass 39, count 0 2006.285.19:18:27.76#ibcon#flushed, iclass 39, count 0 2006.285.19:18:27.76#ibcon#about to write, iclass 39, count 0 2006.285.19:18:27.76#ibcon#wrote, iclass 39, count 0 2006.285.19:18:27.76#ibcon#about to read 3, iclass 39, count 0 2006.285.19:18:27.79#ibcon#read 3, iclass 39, count 0 2006.285.19:18:27.79#ibcon#about to read 4, iclass 39, count 0 2006.285.19:18:27.79#ibcon#read 4, iclass 39, count 0 2006.285.19:18:27.79#ibcon#about to read 5, iclass 39, count 0 2006.285.19:18:27.79#ibcon#read 5, iclass 39, count 0 2006.285.19:18:27.79#ibcon#about to read 6, iclass 39, count 0 2006.285.19:18:27.79#ibcon#read 6, iclass 39, count 0 2006.285.19:18:27.79#ibcon#end of sib2, iclass 39, count 0 2006.285.19:18:27.79#ibcon#*after write, iclass 39, count 0 2006.285.19:18:27.79#ibcon#*before return 0, iclass 39, count 0 2006.285.19:18:27.79#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:18:27.79#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.19:18:27.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.19:18:27.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.19:18:27.79$vck44/vblo=5,709.99 2006.285.19:18:27.79#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.19:18:27.79#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.19:18:27.79#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:27.79#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:18:27.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:18:27.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:18:27.79#ibcon#enter wrdev, iclass 3, count 0 2006.285.19:18:27.79#ibcon#first serial, iclass 3, count 0 2006.285.19:18:27.79#ibcon#enter sib2, iclass 3, count 0 2006.285.19:18:27.79#ibcon#flushed, iclass 3, count 0 2006.285.19:18:27.79#ibcon#about to write, iclass 3, count 0 2006.285.19:18:27.79#ibcon#wrote, iclass 3, count 0 2006.285.19:18:27.79#ibcon#about to read 3, iclass 3, count 0 2006.285.19:18:27.81#ibcon#read 3, iclass 3, count 0 2006.285.19:18:27.81#ibcon#about to read 4, iclass 3, count 0 2006.285.19:18:27.81#ibcon#read 4, iclass 3, count 0 2006.285.19:18:27.81#ibcon#about to read 5, iclass 3, count 0 2006.285.19:18:27.81#ibcon#read 5, iclass 3, count 0 2006.285.19:18:27.81#ibcon#about to read 6, iclass 3, count 0 2006.285.19:18:27.81#ibcon#read 6, iclass 3, count 0 2006.285.19:18:27.81#ibcon#end of sib2, iclass 3, count 0 2006.285.19:18:27.81#ibcon#*mode == 0, iclass 3, count 0 2006.285.19:18:27.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.19:18:27.81#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.19:18:27.81#ibcon#*before write, iclass 3, count 0 2006.285.19:18:27.81#ibcon#enter sib2, iclass 3, count 0 2006.285.19:18:27.81#ibcon#flushed, iclass 3, count 0 2006.285.19:18:27.81#ibcon#about to write, iclass 3, count 0 2006.285.19:18:27.81#ibcon#wrote, iclass 3, count 0 2006.285.19:18:27.81#ibcon#about to read 3, iclass 3, count 0 2006.285.19:18:27.85#ibcon#read 3, iclass 3, count 0 2006.285.19:18:27.85#ibcon#about to read 4, iclass 3, count 0 2006.285.19:18:27.85#ibcon#read 4, iclass 3, count 0 2006.285.19:18:27.85#ibcon#about to read 5, iclass 3, count 0 2006.285.19:18:27.85#ibcon#read 5, iclass 3, count 0 2006.285.19:18:27.85#ibcon#about to read 6, iclass 3, count 0 2006.285.19:18:27.85#ibcon#read 6, iclass 3, count 0 2006.285.19:18:27.85#ibcon#end of sib2, iclass 3, count 0 2006.285.19:18:27.85#ibcon#*after write, iclass 3, count 0 2006.285.19:18:27.85#ibcon#*before return 0, iclass 3, count 0 2006.285.19:18:27.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:18:27.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:18:27.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.19:18:27.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.19:18:27.85$vck44/vb=5,4 2006.285.19:18:27.85#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.19:18:27.85#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.19:18:27.85#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:27.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:18:27.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:18:27.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:18:27.91#ibcon#enter wrdev, iclass 5, count 2 2006.285.19:18:27.91#ibcon#first serial, iclass 5, count 2 2006.285.19:18:27.91#ibcon#enter sib2, iclass 5, count 2 2006.285.19:18:27.91#ibcon#flushed, iclass 5, count 2 2006.285.19:18:27.91#ibcon#about to write, iclass 5, count 2 2006.285.19:18:27.91#ibcon#wrote, iclass 5, count 2 2006.285.19:18:27.91#ibcon#about to read 3, iclass 5, count 2 2006.285.19:18:27.93#ibcon#read 3, iclass 5, count 2 2006.285.19:18:27.93#ibcon#about to read 4, iclass 5, count 2 2006.285.19:18:27.93#ibcon#read 4, iclass 5, count 2 2006.285.19:18:27.93#ibcon#about to read 5, iclass 5, count 2 2006.285.19:18:27.93#ibcon#read 5, iclass 5, count 2 2006.285.19:18:27.93#ibcon#about to read 6, iclass 5, count 2 2006.285.19:18:27.93#ibcon#read 6, iclass 5, count 2 2006.285.19:18:27.93#ibcon#end of sib2, iclass 5, count 2 2006.285.19:18:27.93#ibcon#*mode == 0, iclass 5, count 2 2006.285.19:18:27.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.19:18:27.93#ibcon#[27=AT05-04\r\n] 2006.285.19:18:27.93#ibcon#*before write, iclass 5, count 2 2006.285.19:18:27.93#ibcon#enter sib2, iclass 5, count 2 2006.285.19:18:27.93#ibcon#flushed, iclass 5, count 2 2006.285.19:18:27.93#ibcon#about to write, iclass 5, count 2 2006.285.19:18:27.93#ibcon#wrote, iclass 5, count 2 2006.285.19:18:27.93#ibcon#about to read 3, iclass 5, count 2 2006.285.19:18:27.96#ibcon#read 3, iclass 5, count 2 2006.285.19:18:27.96#ibcon#about to read 4, iclass 5, count 2 2006.285.19:18:27.96#ibcon#read 4, iclass 5, count 2 2006.285.19:18:27.96#ibcon#about to read 5, iclass 5, count 2 2006.285.19:18:27.96#ibcon#read 5, iclass 5, count 2 2006.285.19:18:27.96#ibcon#about to read 6, iclass 5, count 2 2006.285.19:18:27.96#ibcon#read 6, iclass 5, count 2 2006.285.19:18:27.96#ibcon#end of sib2, iclass 5, count 2 2006.285.19:18:27.96#ibcon#*after write, iclass 5, count 2 2006.285.19:18:27.96#ibcon#*before return 0, iclass 5, count 2 2006.285.19:18:27.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:18:27.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.19:18:27.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.19:18:27.96#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:27.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:18:28.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:18:28.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:18:28.08#ibcon#enter wrdev, iclass 5, count 0 2006.285.19:18:28.08#ibcon#first serial, iclass 5, count 0 2006.285.19:18:28.08#ibcon#enter sib2, iclass 5, count 0 2006.285.19:18:28.08#ibcon#flushed, iclass 5, count 0 2006.285.19:18:28.08#ibcon#about to write, iclass 5, count 0 2006.285.19:18:28.08#ibcon#wrote, iclass 5, count 0 2006.285.19:18:28.08#ibcon#about to read 3, iclass 5, count 0 2006.285.19:18:28.10#ibcon#read 3, iclass 5, count 0 2006.285.19:18:28.10#ibcon#about to read 4, iclass 5, count 0 2006.285.19:18:28.10#ibcon#read 4, iclass 5, count 0 2006.285.19:18:28.10#ibcon#about to read 5, iclass 5, count 0 2006.285.19:18:28.10#ibcon#read 5, iclass 5, count 0 2006.285.19:18:28.10#ibcon#about to read 6, iclass 5, count 0 2006.285.19:18:28.10#ibcon#read 6, iclass 5, count 0 2006.285.19:18:28.10#ibcon#end of sib2, iclass 5, count 0 2006.285.19:18:28.10#ibcon#*mode == 0, iclass 5, count 0 2006.285.19:18:28.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.19:18:28.10#ibcon#[27=USB\r\n] 2006.285.19:18:28.10#ibcon#*before write, iclass 5, count 0 2006.285.19:18:28.10#ibcon#enter sib2, iclass 5, count 0 2006.285.19:18:28.10#ibcon#flushed, iclass 5, count 0 2006.285.19:18:28.10#ibcon#about to write, iclass 5, count 0 2006.285.19:18:28.10#ibcon#wrote, iclass 5, count 0 2006.285.19:18:28.10#ibcon#about to read 3, iclass 5, count 0 2006.285.19:18:28.13#ibcon#read 3, iclass 5, count 0 2006.285.19:18:28.13#ibcon#about to read 4, iclass 5, count 0 2006.285.19:18:28.13#ibcon#read 4, iclass 5, count 0 2006.285.19:18:28.13#ibcon#about to read 5, iclass 5, count 0 2006.285.19:18:28.13#ibcon#read 5, iclass 5, count 0 2006.285.19:18:28.13#ibcon#about to read 6, iclass 5, count 0 2006.285.19:18:28.13#ibcon#read 6, iclass 5, count 0 2006.285.19:18:28.13#ibcon#end of sib2, iclass 5, count 0 2006.285.19:18:28.13#ibcon#*after write, iclass 5, count 0 2006.285.19:18:28.13#ibcon#*before return 0, iclass 5, count 0 2006.285.19:18:28.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:18:28.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.19:18:28.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.19:18:28.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.19:18:28.13$vck44/vblo=6,719.99 2006.285.19:18:28.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.19:18:28.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.19:18:28.13#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:28.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:18:28.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:18:28.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:18:28.13#ibcon#enter wrdev, iclass 7, count 0 2006.285.19:18:28.13#ibcon#first serial, iclass 7, count 0 2006.285.19:18:28.13#ibcon#enter sib2, iclass 7, count 0 2006.285.19:18:28.13#ibcon#flushed, iclass 7, count 0 2006.285.19:18:28.13#ibcon#about to write, iclass 7, count 0 2006.285.19:18:28.13#ibcon#wrote, iclass 7, count 0 2006.285.19:18:28.13#ibcon#about to read 3, iclass 7, count 0 2006.285.19:18:28.15#ibcon#read 3, iclass 7, count 0 2006.285.19:18:28.15#ibcon#about to read 4, iclass 7, count 0 2006.285.19:18:28.15#ibcon#read 4, iclass 7, count 0 2006.285.19:18:28.15#ibcon#about to read 5, iclass 7, count 0 2006.285.19:18:28.15#ibcon#read 5, iclass 7, count 0 2006.285.19:18:28.15#ibcon#about to read 6, iclass 7, count 0 2006.285.19:18:28.15#ibcon#read 6, iclass 7, count 0 2006.285.19:18:28.15#ibcon#end of sib2, iclass 7, count 0 2006.285.19:18:28.15#ibcon#*mode == 0, iclass 7, count 0 2006.285.19:18:28.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.19:18:28.15#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.19:18:28.15#ibcon#*before write, iclass 7, count 0 2006.285.19:18:28.15#ibcon#enter sib2, iclass 7, count 0 2006.285.19:18:28.15#ibcon#flushed, iclass 7, count 0 2006.285.19:18:28.15#ibcon#about to write, iclass 7, count 0 2006.285.19:18:28.15#ibcon#wrote, iclass 7, count 0 2006.285.19:18:28.15#ibcon#about to read 3, iclass 7, count 0 2006.285.19:18:28.19#ibcon#read 3, iclass 7, count 0 2006.285.19:18:28.19#ibcon#about to read 4, iclass 7, count 0 2006.285.19:18:28.19#ibcon#read 4, iclass 7, count 0 2006.285.19:18:28.19#ibcon#about to read 5, iclass 7, count 0 2006.285.19:18:28.19#ibcon#read 5, iclass 7, count 0 2006.285.19:18:28.19#ibcon#about to read 6, iclass 7, count 0 2006.285.19:18:28.19#ibcon#read 6, iclass 7, count 0 2006.285.19:18:28.19#ibcon#end of sib2, iclass 7, count 0 2006.285.19:18:28.19#ibcon#*after write, iclass 7, count 0 2006.285.19:18:28.19#ibcon#*before return 0, iclass 7, count 0 2006.285.19:18:28.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:18:28.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.19:18:28.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.19:18:28.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.19:18:28.19$vck44/vb=6,3 2006.285.19:18:28.19#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.19:18:28.19#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.19:18:28.19#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:28.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:18:28.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:18:28.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:18:28.25#ibcon#enter wrdev, iclass 11, count 2 2006.285.19:18:28.25#ibcon#first serial, iclass 11, count 2 2006.285.19:18:28.25#ibcon#enter sib2, iclass 11, count 2 2006.285.19:18:28.25#ibcon#flushed, iclass 11, count 2 2006.285.19:18:28.25#ibcon#about to write, iclass 11, count 2 2006.285.19:18:28.25#ibcon#wrote, iclass 11, count 2 2006.285.19:18:28.25#ibcon#about to read 3, iclass 11, count 2 2006.285.19:18:28.27#ibcon#read 3, iclass 11, count 2 2006.285.19:18:28.27#ibcon#about to read 4, iclass 11, count 2 2006.285.19:18:28.27#ibcon#read 4, iclass 11, count 2 2006.285.19:18:28.27#ibcon#about to read 5, iclass 11, count 2 2006.285.19:18:28.27#ibcon#read 5, iclass 11, count 2 2006.285.19:18:28.27#ibcon#about to read 6, iclass 11, count 2 2006.285.19:18:28.27#ibcon#read 6, iclass 11, count 2 2006.285.19:18:28.27#ibcon#end of sib2, iclass 11, count 2 2006.285.19:18:28.27#ibcon#*mode == 0, iclass 11, count 2 2006.285.19:18:28.27#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.19:18:28.27#ibcon#[27=AT06-03\r\n] 2006.285.19:18:28.27#ibcon#*before write, iclass 11, count 2 2006.285.19:18:28.27#ibcon#enter sib2, iclass 11, count 2 2006.285.19:18:28.27#ibcon#flushed, iclass 11, count 2 2006.285.19:18:28.27#ibcon#about to write, iclass 11, count 2 2006.285.19:18:28.27#ibcon#wrote, iclass 11, count 2 2006.285.19:18:28.27#ibcon#about to read 3, iclass 11, count 2 2006.285.19:18:28.30#ibcon#read 3, iclass 11, count 2 2006.285.19:18:28.30#ibcon#about to read 4, iclass 11, count 2 2006.285.19:18:28.30#ibcon#read 4, iclass 11, count 2 2006.285.19:18:28.30#ibcon#about to read 5, iclass 11, count 2 2006.285.19:18:28.30#ibcon#read 5, iclass 11, count 2 2006.285.19:18:28.30#ibcon#about to read 6, iclass 11, count 2 2006.285.19:18:28.30#ibcon#read 6, iclass 11, count 2 2006.285.19:18:28.30#ibcon#end of sib2, iclass 11, count 2 2006.285.19:18:28.30#ibcon#*after write, iclass 11, count 2 2006.285.19:18:28.30#ibcon#*before return 0, iclass 11, count 2 2006.285.19:18:28.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:18:28.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.19:18:28.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.19:18:28.30#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:28.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:18:28.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:18:28.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:18:28.42#ibcon#enter wrdev, iclass 11, count 0 2006.285.19:18:28.42#ibcon#first serial, iclass 11, count 0 2006.285.19:18:28.42#ibcon#enter sib2, iclass 11, count 0 2006.285.19:18:28.42#ibcon#flushed, iclass 11, count 0 2006.285.19:18:28.42#ibcon#about to write, iclass 11, count 0 2006.285.19:18:28.42#ibcon#wrote, iclass 11, count 0 2006.285.19:18:28.42#ibcon#about to read 3, iclass 11, count 0 2006.285.19:18:28.44#ibcon#read 3, iclass 11, count 0 2006.285.19:18:28.44#ibcon#about to read 4, iclass 11, count 0 2006.285.19:18:28.44#ibcon#read 4, iclass 11, count 0 2006.285.19:18:28.44#ibcon#about to read 5, iclass 11, count 0 2006.285.19:18:28.44#ibcon#read 5, iclass 11, count 0 2006.285.19:18:28.44#ibcon#about to read 6, iclass 11, count 0 2006.285.19:18:28.44#ibcon#read 6, iclass 11, count 0 2006.285.19:18:28.44#ibcon#end of sib2, iclass 11, count 0 2006.285.19:18:28.44#ibcon#*mode == 0, iclass 11, count 0 2006.285.19:18:28.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.19:18:28.44#ibcon#[27=USB\r\n] 2006.285.19:18:28.44#ibcon#*before write, iclass 11, count 0 2006.285.19:18:28.44#ibcon#enter sib2, iclass 11, count 0 2006.285.19:18:28.44#ibcon#flushed, iclass 11, count 0 2006.285.19:18:28.44#ibcon#about to write, iclass 11, count 0 2006.285.19:18:28.44#ibcon#wrote, iclass 11, count 0 2006.285.19:18:28.44#ibcon#about to read 3, iclass 11, count 0 2006.285.19:18:28.47#ibcon#read 3, iclass 11, count 0 2006.285.19:18:28.47#ibcon#about to read 4, iclass 11, count 0 2006.285.19:18:28.47#ibcon#read 4, iclass 11, count 0 2006.285.19:18:28.47#ibcon#about to read 5, iclass 11, count 0 2006.285.19:18:28.47#ibcon#read 5, iclass 11, count 0 2006.285.19:18:28.47#ibcon#about to read 6, iclass 11, count 0 2006.285.19:18:28.47#ibcon#read 6, iclass 11, count 0 2006.285.19:18:28.47#ibcon#end of sib2, iclass 11, count 0 2006.285.19:18:28.47#ibcon#*after write, iclass 11, count 0 2006.285.19:18:28.47#ibcon#*before return 0, iclass 11, count 0 2006.285.19:18:28.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:18:28.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.19:18:28.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.19:18:28.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.19:18:28.47$vck44/vblo=7,734.99 2006.285.19:18:28.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.19:18:28.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.19:18:28.47#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:28.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:18:28.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:18:28.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:18:28.47#ibcon#enter wrdev, iclass 13, count 0 2006.285.19:18:28.47#ibcon#first serial, iclass 13, count 0 2006.285.19:18:28.47#ibcon#enter sib2, iclass 13, count 0 2006.285.19:18:28.47#ibcon#flushed, iclass 13, count 0 2006.285.19:18:28.47#ibcon#about to write, iclass 13, count 0 2006.285.19:18:28.47#ibcon#wrote, iclass 13, count 0 2006.285.19:18:28.47#ibcon#about to read 3, iclass 13, count 0 2006.285.19:18:28.49#ibcon#read 3, iclass 13, count 0 2006.285.19:18:28.58#ibcon#about to read 4, iclass 13, count 0 2006.285.19:18:28.58#ibcon#read 4, iclass 13, count 0 2006.285.19:18:28.58#ibcon#about to read 5, iclass 13, count 0 2006.285.19:18:28.58#ibcon#read 5, iclass 13, count 0 2006.285.19:18:28.58#ibcon#about to read 6, iclass 13, count 0 2006.285.19:18:28.58#ibcon#read 6, iclass 13, count 0 2006.285.19:18:28.58#ibcon#end of sib2, iclass 13, count 0 2006.285.19:18:28.58#ibcon#*mode == 0, iclass 13, count 0 2006.285.19:18:28.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.19:18:28.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.19:18:28.58#ibcon#*before write, iclass 13, count 0 2006.285.19:18:28.58#ibcon#enter sib2, iclass 13, count 0 2006.285.19:18:28.58#ibcon#flushed, iclass 13, count 0 2006.285.19:18:28.58#ibcon#about to write, iclass 13, count 0 2006.285.19:18:28.58#ibcon#wrote, iclass 13, count 0 2006.285.19:18:28.58#ibcon#about to read 3, iclass 13, count 0 2006.285.19:18:28.62#ibcon#read 3, iclass 13, count 0 2006.285.19:18:28.62#ibcon#about to read 4, iclass 13, count 0 2006.285.19:18:28.62#ibcon#read 4, iclass 13, count 0 2006.285.19:18:28.62#ibcon#about to read 5, iclass 13, count 0 2006.285.19:18:28.62#ibcon#read 5, iclass 13, count 0 2006.285.19:18:28.62#ibcon#about to read 6, iclass 13, count 0 2006.285.19:18:28.62#ibcon#read 6, iclass 13, count 0 2006.285.19:18:28.62#ibcon#end of sib2, iclass 13, count 0 2006.285.19:18:28.62#ibcon#*after write, iclass 13, count 0 2006.285.19:18:28.62#ibcon#*before return 0, iclass 13, count 0 2006.285.19:18:28.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:18:28.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.19:18:28.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.19:18:28.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.19:18:28.62$vck44/vb=7,4 2006.285.19:18:28.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.19:18:28.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.19:18:28.62#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:28.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:18:28.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:18:28.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:18:28.62#ibcon#enter wrdev, iclass 15, count 2 2006.285.19:18:28.62#ibcon#first serial, iclass 15, count 2 2006.285.19:18:28.62#ibcon#enter sib2, iclass 15, count 2 2006.285.19:18:28.62#ibcon#flushed, iclass 15, count 2 2006.285.19:18:28.62#ibcon#about to write, iclass 15, count 2 2006.285.19:18:28.62#ibcon#wrote, iclass 15, count 2 2006.285.19:18:28.62#ibcon#about to read 3, iclass 15, count 2 2006.285.19:18:28.64#ibcon#read 3, iclass 15, count 2 2006.285.19:18:28.64#ibcon#about to read 4, iclass 15, count 2 2006.285.19:18:28.64#ibcon#read 4, iclass 15, count 2 2006.285.19:18:28.64#ibcon#about to read 5, iclass 15, count 2 2006.285.19:18:28.64#ibcon#read 5, iclass 15, count 2 2006.285.19:18:28.64#ibcon#about to read 6, iclass 15, count 2 2006.285.19:18:28.64#ibcon#read 6, iclass 15, count 2 2006.285.19:18:28.64#ibcon#end of sib2, iclass 15, count 2 2006.285.19:18:28.64#ibcon#*mode == 0, iclass 15, count 2 2006.285.19:18:28.64#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.19:18:28.64#ibcon#[27=AT07-04\r\n] 2006.285.19:18:28.64#ibcon#*before write, iclass 15, count 2 2006.285.19:18:28.64#ibcon#enter sib2, iclass 15, count 2 2006.285.19:18:28.64#ibcon#flushed, iclass 15, count 2 2006.285.19:18:28.64#ibcon#about to write, iclass 15, count 2 2006.285.19:18:28.64#ibcon#wrote, iclass 15, count 2 2006.285.19:18:28.64#ibcon#about to read 3, iclass 15, count 2 2006.285.19:18:28.67#ibcon#read 3, iclass 15, count 2 2006.285.19:18:28.67#ibcon#about to read 4, iclass 15, count 2 2006.285.19:18:28.67#ibcon#read 4, iclass 15, count 2 2006.285.19:18:28.67#ibcon#about to read 5, iclass 15, count 2 2006.285.19:18:28.67#ibcon#read 5, iclass 15, count 2 2006.285.19:18:28.67#ibcon#about to read 6, iclass 15, count 2 2006.285.19:18:28.67#ibcon#read 6, iclass 15, count 2 2006.285.19:18:28.67#ibcon#end of sib2, iclass 15, count 2 2006.285.19:18:28.67#ibcon#*after write, iclass 15, count 2 2006.285.19:18:28.67#ibcon#*before return 0, iclass 15, count 2 2006.285.19:18:28.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:18:28.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.19:18:28.67#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.19:18:28.67#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:28.67#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:18:28.79#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:18:28.79#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:18:28.79#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:18:28.79#ibcon#first serial, iclass 15, count 0 2006.285.19:18:28.79#ibcon#enter sib2, iclass 15, count 0 2006.285.19:18:28.79#ibcon#flushed, iclass 15, count 0 2006.285.19:18:28.79#ibcon#about to write, iclass 15, count 0 2006.285.19:18:28.79#ibcon#wrote, iclass 15, count 0 2006.285.19:18:28.79#ibcon#about to read 3, iclass 15, count 0 2006.285.19:18:28.81#ibcon#read 3, iclass 15, count 0 2006.285.19:18:28.81#ibcon#about to read 4, iclass 15, count 0 2006.285.19:18:28.81#ibcon#read 4, iclass 15, count 0 2006.285.19:18:28.81#ibcon#about to read 5, iclass 15, count 0 2006.285.19:18:28.81#ibcon#read 5, iclass 15, count 0 2006.285.19:18:28.81#ibcon#about to read 6, iclass 15, count 0 2006.285.19:18:28.81#ibcon#read 6, iclass 15, count 0 2006.285.19:18:28.81#ibcon#end of sib2, iclass 15, count 0 2006.285.19:18:28.81#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:18:28.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:18:28.81#ibcon#[27=USB\r\n] 2006.285.19:18:28.81#ibcon#*before write, iclass 15, count 0 2006.285.19:18:28.81#ibcon#enter sib2, iclass 15, count 0 2006.285.19:18:28.81#ibcon#flushed, iclass 15, count 0 2006.285.19:18:28.81#ibcon#about to write, iclass 15, count 0 2006.285.19:18:28.81#ibcon#wrote, iclass 15, count 0 2006.285.19:18:28.81#ibcon#about to read 3, iclass 15, count 0 2006.285.19:18:28.84#ibcon#read 3, iclass 15, count 0 2006.285.19:18:28.84#ibcon#about to read 4, iclass 15, count 0 2006.285.19:18:28.84#ibcon#read 4, iclass 15, count 0 2006.285.19:18:28.84#ibcon#about to read 5, iclass 15, count 0 2006.285.19:18:28.84#ibcon#read 5, iclass 15, count 0 2006.285.19:18:28.84#ibcon#about to read 6, iclass 15, count 0 2006.285.19:18:28.84#ibcon#read 6, iclass 15, count 0 2006.285.19:18:28.84#ibcon#end of sib2, iclass 15, count 0 2006.285.19:18:28.84#ibcon#*after write, iclass 15, count 0 2006.285.19:18:28.84#ibcon#*before return 0, iclass 15, count 0 2006.285.19:18:28.84#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:18:28.84#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.19:18:28.84#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:18:28.84#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:18:28.84$vck44/vblo=8,744.99 2006.285.19:18:28.84#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.19:18:28.84#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.19:18:28.84#ibcon#ireg 17 cls_cnt 0 2006.285.19:18:28.84#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:18:28.84#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:18:28.84#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:18:28.84#ibcon#enter wrdev, iclass 17, count 0 2006.285.19:18:28.84#ibcon#first serial, iclass 17, count 0 2006.285.19:18:28.84#ibcon#enter sib2, iclass 17, count 0 2006.285.19:18:28.84#ibcon#flushed, iclass 17, count 0 2006.285.19:18:28.84#ibcon#about to write, iclass 17, count 0 2006.285.19:18:28.84#ibcon#wrote, iclass 17, count 0 2006.285.19:18:28.84#ibcon#about to read 3, iclass 17, count 0 2006.285.19:18:28.86#ibcon#read 3, iclass 17, count 0 2006.285.19:18:28.86#ibcon#about to read 4, iclass 17, count 0 2006.285.19:18:28.86#ibcon#read 4, iclass 17, count 0 2006.285.19:18:28.86#ibcon#about to read 5, iclass 17, count 0 2006.285.19:18:28.86#ibcon#read 5, iclass 17, count 0 2006.285.19:18:28.86#ibcon#about to read 6, iclass 17, count 0 2006.285.19:18:28.86#ibcon#read 6, iclass 17, count 0 2006.285.19:18:28.86#ibcon#end of sib2, iclass 17, count 0 2006.285.19:18:28.86#ibcon#*mode == 0, iclass 17, count 0 2006.285.19:18:28.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.19:18:28.86#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.19:18:28.86#ibcon#*before write, iclass 17, count 0 2006.285.19:18:28.86#ibcon#enter sib2, iclass 17, count 0 2006.285.19:18:28.86#ibcon#flushed, iclass 17, count 0 2006.285.19:18:28.86#ibcon#about to write, iclass 17, count 0 2006.285.19:18:28.86#ibcon#wrote, iclass 17, count 0 2006.285.19:18:28.86#ibcon#about to read 3, iclass 17, count 0 2006.285.19:18:28.90#ibcon#read 3, iclass 17, count 0 2006.285.19:18:28.90#ibcon#about to read 4, iclass 17, count 0 2006.285.19:18:28.90#ibcon#read 4, iclass 17, count 0 2006.285.19:18:28.90#ibcon#about to read 5, iclass 17, count 0 2006.285.19:18:28.90#ibcon#read 5, iclass 17, count 0 2006.285.19:18:28.90#ibcon#about to read 6, iclass 17, count 0 2006.285.19:18:28.90#ibcon#read 6, iclass 17, count 0 2006.285.19:18:28.90#ibcon#end of sib2, iclass 17, count 0 2006.285.19:18:28.90#ibcon#*after write, iclass 17, count 0 2006.285.19:18:28.90#ibcon#*before return 0, iclass 17, count 0 2006.285.19:18:28.90#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:18:28.90#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:18:28.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.19:18:28.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.19:18:28.90$vck44/vb=8,4 2006.285.19:18:28.90#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.19:18:28.90#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.19:18:28.90#ibcon#ireg 11 cls_cnt 2 2006.285.19:18:28.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:18:28.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:18:28.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:18:28.96#ibcon#enter wrdev, iclass 19, count 2 2006.285.19:18:28.96#ibcon#first serial, iclass 19, count 2 2006.285.19:18:28.96#ibcon#enter sib2, iclass 19, count 2 2006.285.19:18:28.96#ibcon#flushed, iclass 19, count 2 2006.285.19:18:28.96#ibcon#about to write, iclass 19, count 2 2006.285.19:18:28.96#ibcon#wrote, iclass 19, count 2 2006.285.19:18:28.96#ibcon#about to read 3, iclass 19, count 2 2006.285.19:18:28.98#ibcon#read 3, iclass 19, count 2 2006.285.19:18:28.98#ibcon#about to read 4, iclass 19, count 2 2006.285.19:18:28.98#ibcon#read 4, iclass 19, count 2 2006.285.19:18:28.98#ibcon#about to read 5, iclass 19, count 2 2006.285.19:18:28.98#ibcon#read 5, iclass 19, count 2 2006.285.19:18:28.98#ibcon#about to read 6, iclass 19, count 2 2006.285.19:18:28.98#ibcon#read 6, iclass 19, count 2 2006.285.19:18:28.98#ibcon#end of sib2, iclass 19, count 2 2006.285.19:18:28.98#ibcon#*mode == 0, iclass 19, count 2 2006.285.19:18:28.98#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.19:18:28.98#ibcon#[27=AT08-04\r\n] 2006.285.19:18:28.98#ibcon#*before write, iclass 19, count 2 2006.285.19:18:28.98#ibcon#enter sib2, iclass 19, count 2 2006.285.19:18:28.98#ibcon#flushed, iclass 19, count 2 2006.285.19:18:28.98#ibcon#about to write, iclass 19, count 2 2006.285.19:18:28.98#ibcon#wrote, iclass 19, count 2 2006.285.19:18:28.98#ibcon#about to read 3, iclass 19, count 2 2006.285.19:18:29.01#ibcon#read 3, iclass 19, count 2 2006.285.19:18:29.01#ibcon#about to read 4, iclass 19, count 2 2006.285.19:18:29.01#ibcon#read 4, iclass 19, count 2 2006.285.19:18:29.01#ibcon#about to read 5, iclass 19, count 2 2006.285.19:18:29.01#ibcon#read 5, iclass 19, count 2 2006.285.19:18:29.01#ibcon#about to read 6, iclass 19, count 2 2006.285.19:18:29.01#ibcon#read 6, iclass 19, count 2 2006.285.19:18:29.01#ibcon#end of sib2, iclass 19, count 2 2006.285.19:18:29.01#ibcon#*after write, iclass 19, count 2 2006.285.19:18:29.01#ibcon#*before return 0, iclass 19, count 2 2006.285.19:18:29.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:18:29.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.19:18:29.01#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.19:18:29.01#ibcon#ireg 7 cls_cnt 0 2006.285.19:18:29.01#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:18:29.13#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:18:29.13#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:18:29.13#ibcon#enter wrdev, iclass 19, count 0 2006.285.19:18:29.13#ibcon#first serial, iclass 19, count 0 2006.285.19:18:29.13#ibcon#enter sib2, iclass 19, count 0 2006.285.19:18:29.13#ibcon#flushed, iclass 19, count 0 2006.285.19:18:29.13#ibcon#about to write, iclass 19, count 0 2006.285.19:18:29.13#ibcon#wrote, iclass 19, count 0 2006.285.19:18:29.13#ibcon#about to read 3, iclass 19, count 0 2006.285.19:18:29.15#ibcon#read 3, iclass 19, count 0 2006.285.19:18:29.15#ibcon#about to read 4, iclass 19, count 0 2006.285.19:18:29.15#ibcon#read 4, iclass 19, count 0 2006.285.19:18:29.15#ibcon#about to read 5, iclass 19, count 0 2006.285.19:18:29.15#ibcon#read 5, iclass 19, count 0 2006.285.19:18:29.15#ibcon#about to read 6, iclass 19, count 0 2006.285.19:18:29.15#ibcon#read 6, iclass 19, count 0 2006.285.19:18:29.15#ibcon#end of sib2, iclass 19, count 0 2006.285.19:18:29.15#ibcon#*mode == 0, iclass 19, count 0 2006.285.19:18:29.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.19:18:29.15#ibcon#[27=USB\r\n] 2006.285.19:18:29.15#ibcon#*before write, iclass 19, count 0 2006.285.19:18:29.15#ibcon#enter sib2, iclass 19, count 0 2006.285.19:18:29.15#ibcon#flushed, iclass 19, count 0 2006.285.19:18:29.15#ibcon#about to write, iclass 19, count 0 2006.285.19:18:29.15#ibcon#wrote, iclass 19, count 0 2006.285.19:18:29.15#ibcon#about to read 3, iclass 19, count 0 2006.285.19:18:29.18#ibcon#read 3, iclass 19, count 0 2006.285.19:18:29.18#ibcon#about to read 4, iclass 19, count 0 2006.285.19:18:29.18#ibcon#read 4, iclass 19, count 0 2006.285.19:18:29.18#ibcon#about to read 5, iclass 19, count 0 2006.285.19:18:29.18#ibcon#read 5, iclass 19, count 0 2006.285.19:18:29.18#ibcon#about to read 6, iclass 19, count 0 2006.285.19:18:29.18#ibcon#read 6, iclass 19, count 0 2006.285.19:18:29.18#ibcon#end of sib2, iclass 19, count 0 2006.285.19:18:29.18#ibcon#*after write, iclass 19, count 0 2006.285.19:18:29.18#ibcon#*before return 0, iclass 19, count 0 2006.285.19:18:29.18#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:18:29.18#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.19:18:29.18#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.19:18:29.18#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.19:18:29.18$vck44/vabw=wide 2006.285.19:18:29.18#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.19:18:29.18#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.19:18:29.18#ibcon#ireg 8 cls_cnt 0 2006.285.19:18:29.18#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:18:29.18#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:18:29.18#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:18:29.18#ibcon#enter wrdev, iclass 21, count 0 2006.285.19:18:29.18#ibcon#first serial, iclass 21, count 0 2006.285.19:18:29.18#ibcon#enter sib2, iclass 21, count 0 2006.285.19:18:29.18#ibcon#flushed, iclass 21, count 0 2006.285.19:18:29.18#ibcon#about to write, iclass 21, count 0 2006.285.19:18:29.18#ibcon#wrote, iclass 21, count 0 2006.285.19:18:29.18#ibcon#about to read 3, iclass 21, count 0 2006.285.19:18:29.20#ibcon#read 3, iclass 21, count 0 2006.285.19:18:29.20#ibcon#about to read 4, iclass 21, count 0 2006.285.19:18:29.20#ibcon#read 4, iclass 21, count 0 2006.285.19:18:29.20#ibcon#about to read 5, iclass 21, count 0 2006.285.19:18:29.20#ibcon#read 5, iclass 21, count 0 2006.285.19:18:29.20#ibcon#about to read 6, iclass 21, count 0 2006.285.19:18:29.20#ibcon#read 6, iclass 21, count 0 2006.285.19:18:29.20#ibcon#end of sib2, iclass 21, count 0 2006.285.19:18:29.20#ibcon#*mode == 0, iclass 21, count 0 2006.285.19:18:29.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.19:18:29.20#ibcon#[25=BW32\r\n] 2006.285.19:18:29.20#ibcon#*before write, iclass 21, count 0 2006.285.19:18:29.20#ibcon#enter sib2, iclass 21, count 0 2006.285.19:18:29.20#ibcon#flushed, iclass 21, count 0 2006.285.19:18:29.20#ibcon#about to write, iclass 21, count 0 2006.285.19:18:29.20#ibcon#wrote, iclass 21, count 0 2006.285.19:18:29.20#ibcon#about to read 3, iclass 21, count 0 2006.285.19:18:29.23#ibcon#read 3, iclass 21, count 0 2006.285.19:18:29.23#ibcon#about to read 4, iclass 21, count 0 2006.285.19:18:29.23#ibcon#read 4, iclass 21, count 0 2006.285.19:18:29.23#ibcon#about to read 5, iclass 21, count 0 2006.285.19:18:29.23#ibcon#read 5, iclass 21, count 0 2006.285.19:18:29.23#ibcon#about to read 6, iclass 21, count 0 2006.285.19:18:29.23#ibcon#read 6, iclass 21, count 0 2006.285.19:18:29.23#ibcon#end of sib2, iclass 21, count 0 2006.285.19:18:29.23#ibcon#*after write, iclass 21, count 0 2006.285.19:18:29.23#ibcon#*before return 0, iclass 21, count 0 2006.285.19:18:29.23#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:18:29.23#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.19:18:29.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.19:18:29.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.19:18:29.23$vck44/vbbw=wide 2006.285.19:18:29.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.19:18:29.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.19:18:29.23#ibcon#ireg 8 cls_cnt 0 2006.285.19:18:29.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:18:29.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:18:29.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:18:29.30#ibcon#enter wrdev, iclass 23, count 0 2006.285.19:18:29.30#ibcon#first serial, iclass 23, count 0 2006.285.19:18:29.30#ibcon#enter sib2, iclass 23, count 0 2006.285.19:18:29.30#ibcon#flushed, iclass 23, count 0 2006.285.19:18:29.30#ibcon#about to write, iclass 23, count 0 2006.285.19:18:29.30#ibcon#wrote, iclass 23, count 0 2006.285.19:18:29.30#ibcon#about to read 3, iclass 23, count 0 2006.285.19:18:29.32#ibcon#read 3, iclass 23, count 0 2006.285.19:18:29.32#ibcon#about to read 4, iclass 23, count 0 2006.285.19:18:29.32#ibcon#read 4, iclass 23, count 0 2006.285.19:18:29.32#ibcon#about to read 5, iclass 23, count 0 2006.285.19:18:29.32#ibcon#read 5, iclass 23, count 0 2006.285.19:18:29.32#ibcon#about to read 6, iclass 23, count 0 2006.285.19:18:29.32#ibcon#read 6, iclass 23, count 0 2006.285.19:18:29.32#ibcon#end of sib2, iclass 23, count 0 2006.285.19:18:29.32#ibcon#*mode == 0, iclass 23, count 0 2006.285.19:18:29.32#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.19:18:29.32#ibcon#[27=BW32\r\n] 2006.285.19:18:29.32#ibcon#*before write, iclass 23, count 0 2006.285.19:18:29.32#ibcon#enter sib2, iclass 23, count 0 2006.285.19:18:29.32#ibcon#flushed, iclass 23, count 0 2006.285.19:18:29.32#ibcon#about to write, iclass 23, count 0 2006.285.19:18:29.32#ibcon#wrote, iclass 23, count 0 2006.285.19:18:29.32#ibcon#about to read 3, iclass 23, count 0 2006.285.19:18:29.35#ibcon#read 3, iclass 23, count 0 2006.285.19:18:29.35#ibcon#about to read 4, iclass 23, count 0 2006.285.19:18:29.35#ibcon#read 4, iclass 23, count 0 2006.285.19:18:29.35#ibcon#about to read 5, iclass 23, count 0 2006.285.19:18:29.35#ibcon#read 5, iclass 23, count 0 2006.285.19:18:29.35#ibcon#about to read 6, iclass 23, count 0 2006.285.19:18:29.35#ibcon#read 6, iclass 23, count 0 2006.285.19:18:29.35#ibcon#end of sib2, iclass 23, count 0 2006.285.19:18:29.35#ibcon#*after write, iclass 23, count 0 2006.285.19:18:29.35#ibcon#*before return 0, iclass 23, count 0 2006.285.19:18:29.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:18:29.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:18:29.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.19:18:29.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.19:18:29.35$setupk4/ifdk4 2006.285.19:18:29.35$ifdk4/lo= 2006.285.19:18:29.35$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.19:18:29.35$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.19:18:29.35$ifdk4/patch= 2006.285.19:18:29.35$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.19:18:29.35$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.19:18:29.35$setupk4/!*+20s 2006.285.19:18:30.21#abcon#<5=/15 1.0 1.6 15.001001014.9\r\n> 2006.285.19:18:30.23#abcon#{5=INTERFACE CLEAR} 2006.285.19:18:30.29#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:18:31.13#trakl#Source acquired 2006.285.19:18:32.13#flagr#flagr/antenna,acquired 2006.285.19:18:40.38#abcon#<5=/15 0.9 1.6 15.001001014.9\r\n> 2006.285.19:18:40.40#abcon#{5=INTERFACE CLEAR} 2006.285.19:18:40.46#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:18:43.27$setupk4/"tpicd 2006.285.19:18:43.27$setupk4/echo=off 2006.285.19:18:43.27$setupk4/xlog=off 2006.285.19:18:43.27:!2006.285.19:20:28 2006.285.19:20:28.00:preob 2006.285.19:20:28.14/onsource/TRACKING 2006.285.19:20:28.14:!2006.285.19:20:38 2006.285.19:20:38.00:"tape 2006.285.19:20:38.00:"st=record 2006.285.19:20:38.00:data_valid=on 2006.285.19:20:38.00:midob 2006.285.19:20:38.14/onsource/TRACKING 2006.285.19:20:38.14/wx/14.98,1015.0,100 2006.285.19:20:38.35/cable/+6.5073E-03 2006.285.19:20:39.44/va/01,07,usb,yes,32,35 2006.285.19:20:39.44/va/02,06,usb,yes,32,33 2006.285.19:20:39.44/va/03,07,usb,yes,32,34 2006.285.19:20:39.44/va/04,06,usb,yes,33,34 2006.285.19:20:39.44/va/05,03,usb,yes,33,33 2006.285.19:20:39.44/va/06,04,usb,yes,29,29 2006.285.19:20:39.44/va/07,04,usb,yes,30,30 2006.285.19:20:39.44/va/08,03,usb,yes,31,37 2006.285.19:20:39.67/valo/01,524.99,yes,locked 2006.285.19:20:39.67/valo/02,534.99,yes,locked 2006.285.19:20:39.67/valo/03,564.99,yes,locked 2006.285.19:20:39.67/valo/04,624.99,yes,locked 2006.285.19:20:39.67/valo/05,734.99,yes,locked 2006.285.19:20:39.67/valo/06,814.99,yes,locked 2006.285.19:20:39.67/valo/07,864.99,yes,locked 2006.285.19:20:39.67/valo/08,884.99,yes,locked 2006.285.19:20:40.76/vb/01,04,usb,yes,30,28 2006.285.19:20:40.76/vb/02,05,usb,yes,28,28 2006.285.19:20:40.76/vb/03,04,usb,yes,29,32 2006.285.19:20:40.76/vb/04,05,usb,yes,29,28 2006.285.19:20:40.76/vb/05,04,usb,yes,26,28 2006.285.19:20:40.76/vb/06,03,usb,yes,37,33 2006.285.19:20:40.76/vb/07,04,usb,yes,30,30 2006.285.19:20:40.76/vb/08,04,usb,yes,27,31 2006.285.19:20:40.99/vblo/01,629.99,yes,locked 2006.285.19:20:40.99/vblo/02,634.99,yes,locked 2006.285.19:20:40.99/vblo/03,649.99,yes,locked 2006.285.19:20:40.99/vblo/04,679.99,yes,locked 2006.285.19:20:40.99/vblo/05,709.99,yes,locked 2006.285.19:20:40.99/vblo/06,719.99,yes,locked 2006.285.19:20:40.99/vblo/07,734.99,yes,locked 2006.285.19:20:40.99/vblo/08,744.99,yes,locked 2006.285.19:20:41.14/vabw/8 2006.285.19:20:41.29/vbbw/8 2006.285.19:20:41.38/xfe/off,on,12.0 2006.285.19:20:41.75/ifatt/23,28,28,28 2006.285.19:20:42.08/fmout-gps/S +2.73E-07 2006.285.19:20:42.10:!2006.285.19:25:48 2006.285.19:25:48.00:data_valid=off 2006.285.19:25:48.00:"et 2006.285.19:25:48.00:!+3s 2006.285.19:25:51.01:"tape 2006.285.19:25:51.01:postob 2006.285.19:25:51.19/cable/+6.5074E-03 2006.285.19:25:51.19/wx/14.91,1015.1,100 2006.285.19:25:52.07/fmout-gps/S +2.74E-07 2006.285.19:25:52.07:scan_name=285-1930,jd0610,210 2006.285.19:25:52.07:source=0014+813,001708.47,813508.1,2000.0,cw 2006.285.19:25:53.13#flagr#flagr/antenna,new-source 2006.285.19:25:53.13:checkk5 2006.285.19:25:53.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.19:25:54.23/chk_autoobs//k5ts2/ autoobs is running! 2006.285.19:25:54.62/chk_autoobs//k5ts3/ autoobs is running! 2006.285.19:25:55.08/chk_autoobs//k5ts4/ autoobs is running! 2006.285.19:25:55.45/chk_obsdata//k5ts1/T2851920??a.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.285.19:25:55.87/chk_obsdata//k5ts2/T2851920??b.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.285.19:25:56.41/chk_obsdata//k5ts3/T2851920??c.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.285.19:25:56.76/chk_obsdata//k5ts4/T2851920??d.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.285.19:25:57.94/k5log//k5ts1_log_newline 2006.285.19:25:58.71/k5log//k5ts2_log_newline 2006.285.19:25:59.56/k5log//k5ts3_log_newline 2006.285.19:26:00.36/k5log//k5ts4_log_newline 2006.285.19:26:00.38/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.19:26:00.38:setupk4=1 2006.285.19:26:00.38$setupk4/echo=on 2006.285.19:26:00.38$setupk4/pcalon 2006.285.19:26:00.38$pcalon/"no phase cal control is implemented here 2006.285.19:26:00.38$setupk4/"tpicd=stop 2006.285.19:26:00.38$setupk4/"rec=synch_on 2006.285.19:26:00.38$setupk4/"rec_mode=128 2006.285.19:26:00.38$setupk4/!* 2006.285.19:26:00.38$setupk4/recpk4 2006.285.19:26:00.38$recpk4/recpatch= 2006.285.19:26:00.38$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.19:26:00.38$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.19:26:00.38$setupk4/vck44 2006.285.19:26:00.38$vck44/valo=1,524.99 2006.285.19:26:00.39#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.19:26:00.39#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.19:26:00.39#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:00.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:26:00.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:26:00.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:26:00.39#ibcon#enter wrdev, iclass 19, count 0 2006.285.19:26:00.39#ibcon#first serial, iclass 19, count 0 2006.285.19:26:00.39#ibcon#enter sib2, iclass 19, count 0 2006.285.19:26:00.39#ibcon#flushed, iclass 19, count 0 2006.285.19:26:00.39#ibcon#about to write, iclass 19, count 0 2006.285.19:26:00.39#ibcon#wrote, iclass 19, count 0 2006.285.19:26:00.39#ibcon#about to read 3, iclass 19, count 0 2006.285.19:26:00.41#ibcon#read 3, iclass 19, count 0 2006.285.19:26:00.41#ibcon#about to read 4, iclass 19, count 0 2006.285.19:26:00.41#ibcon#read 4, iclass 19, count 0 2006.285.19:26:00.41#ibcon#about to read 5, iclass 19, count 0 2006.285.19:26:00.41#ibcon#read 5, iclass 19, count 0 2006.285.19:26:00.41#ibcon#about to read 6, iclass 19, count 0 2006.285.19:26:00.41#ibcon#read 6, iclass 19, count 0 2006.285.19:26:00.41#ibcon#end of sib2, iclass 19, count 0 2006.285.19:26:00.41#ibcon#*mode == 0, iclass 19, count 0 2006.285.19:26:00.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.19:26:00.41#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.19:26:00.41#ibcon#*before write, iclass 19, count 0 2006.285.19:26:00.41#ibcon#enter sib2, iclass 19, count 0 2006.285.19:26:00.41#ibcon#flushed, iclass 19, count 0 2006.285.19:26:00.41#ibcon#about to write, iclass 19, count 0 2006.285.19:26:00.41#ibcon#wrote, iclass 19, count 0 2006.285.19:26:00.41#ibcon#about to read 3, iclass 19, count 0 2006.285.19:26:00.46#ibcon#read 3, iclass 19, count 0 2006.285.19:26:00.46#ibcon#about to read 4, iclass 19, count 0 2006.285.19:26:00.46#ibcon#read 4, iclass 19, count 0 2006.285.19:26:00.46#ibcon#about to read 5, iclass 19, count 0 2006.285.19:26:00.46#ibcon#read 5, iclass 19, count 0 2006.285.19:26:00.46#ibcon#about to read 6, iclass 19, count 0 2006.285.19:26:00.46#ibcon#read 6, iclass 19, count 0 2006.285.19:26:00.46#ibcon#end of sib2, iclass 19, count 0 2006.285.19:26:00.46#ibcon#*after write, iclass 19, count 0 2006.285.19:26:00.46#ibcon#*before return 0, iclass 19, count 0 2006.285.19:26:00.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:26:00.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:26:00.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.19:26:00.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.19:26:00.46$vck44/va=1,7 2006.285.19:26:00.46#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.19:26:00.46#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.19:26:00.46#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:00.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:26:00.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:26:00.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:26:00.46#ibcon#enter wrdev, iclass 21, count 2 2006.285.19:26:00.46#ibcon#first serial, iclass 21, count 2 2006.285.19:26:00.46#ibcon#enter sib2, iclass 21, count 2 2006.285.19:26:00.46#ibcon#flushed, iclass 21, count 2 2006.285.19:26:00.46#ibcon#about to write, iclass 21, count 2 2006.285.19:26:00.46#ibcon#wrote, iclass 21, count 2 2006.285.19:26:00.46#ibcon#about to read 3, iclass 21, count 2 2006.285.19:26:00.48#ibcon#read 3, iclass 21, count 2 2006.285.19:26:00.48#ibcon#about to read 4, iclass 21, count 2 2006.285.19:26:00.48#ibcon#read 4, iclass 21, count 2 2006.285.19:26:00.48#ibcon#about to read 5, iclass 21, count 2 2006.285.19:26:00.48#ibcon#read 5, iclass 21, count 2 2006.285.19:26:00.48#ibcon#about to read 6, iclass 21, count 2 2006.285.19:26:00.48#ibcon#read 6, iclass 21, count 2 2006.285.19:26:00.48#ibcon#end of sib2, iclass 21, count 2 2006.285.19:26:00.48#ibcon#*mode == 0, iclass 21, count 2 2006.285.19:26:00.48#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.19:26:00.48#ibcon#[25=AT01-07\r\n] 2006.285.19:26:00.48#ibcon#*before write, iclass 21, count 2 2006.285.19:26:00.48#ibcon#enter sib2, iclass 21, count 2 2006.285.19:26:00.48#ibcon#flushed, iclass 21, count 2 2006.285.19:26:00.48#ibcon#about to write, iclass 21, count 2 2006.285.19:26:00.48#ibcon#wrote, iclass 21, count 2 2006.285.19:26:00.48#ibcon#about to read 3, iclass 21, count 2 2006.285.19:26:00.51#ibcon#read 3, iclass 21, count 2 2006.285.19:26:00.51#ibcon#about to read 4, iclass 21, count 2 2006.285.19:26:00.51#ibcon#read 4, iclass 21, count 2 2006.285.19:26:00.51#ibcon#about to read 5, iclass 21, count 2 2006.285.19:26:00.51#ibcon#read 5, iclass 21, count 2 2006.285.19:26:00.51#ibcon#about to read 6, iclass 21, count 2 2006.285.19:26:00.51#ibcon#read 6, iclass 21, count 2 2006.285.19:26:00.51#ibcon#end of sib2, iclass 21, count 2 2006.285.19:26:00.51#ibcon#*after write, iclass 21, count 2 2006.285.19:26:00.51#ibcon#*before return 0, iclass 21, count 2 2006.285.19:26:00.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:26:00.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:26:00.51#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.19:26:00.51#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:00.51#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:26:00.52#abcon#<5=/14 0.7 1.3 14.911001015.1\r\n> 2006.285.19:26:00.54#abcon#{5=INTERFACE CLEAR} 2006.285.19:26:00.60#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:26:00.63#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:26:00.63#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:26:00.63#ibcon#enter wrdev, iclass 21, count 0 2006.285.19:26:00.63#ibcon#first serial, iclass 21, count 0 2006.285.19:26:00.63#ibcon#enter sib2, iclass 21, count 0 2006.285.19:26:00.63#ibcon#flushed, iclass 21, count 0 2006.285.19:26:00.63#ibcon#about to write, iclass 21, count 0 2006.285.19:26:00.63#ibcon#wrote, iclass 21, count 0 2006.285.19:26:00.63#ibcon#about to read 3, iclass 21, count 0 2006.285.19:26:00.65#ibcon#read 3, iclass 21, count 0 2006.285.19:26:00.65#ibcon#about to read 4, iclass 21, count 0 2006.285.19:26:00.65#ibcon#read 4, iclass 21, count 0 2006.285.19:26:00.65#ibcon#about to read 5, iclass 21, count 0 2006.285.19:26:00.65#ibcon#read 5, iclass 21, count 0 2006.285.19:26:00.65#ibcon#about to read 6, iclass 21, count 0 2006.285.19:26:00.65#ibcon#read 6, iclass 21, count 0 2006.285.19:26:00.65#ibcon#end of sib2, iclass 21, count 0 2006.285.19:26:00.65#ibcon#*mode == 0, iclass 21, count 0 2006.285.19:26:00.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.19:26:00.65#ibcon#[25=USB\r\n] 2006.285.19:26:00.65#ibcon#*before write, iclass 21, count 0 2006.285.19:26:00.65#ibcon#enter sib2, iclass 21, count 0 2006.285.19:26:00.65#ibcon#flushed, iclass 21, count 0 2006.285.19:26:00.65#ibcon#about to write, iclass 21, count 0 2006.285.19:26:00.65#ibcon#wrote, iclass 21, count 0 2006.285.19:26:00.65#ibcon#about to read 3, iclass 21, count 0 2006.285.19:26:00.68#ibcon#read 3, iclass 21, count 0 2006.285.19:26:00.68#ibcon#about to read 4, iclass 21, count 0 2006.285.19:26:00.68#ibcon#read 4, iclass 21, count 0 2006.285.19:26:00.68#ibcon#about to read 5, iclass 21, count 0 2006.285.19:26:00.68#ibcon#read 5, iclass 21, count 0 2006.285.19:26:00.68#ibcon#about to read 6, iclass 21, count 0 2006.285.19:26:00.68#ibcon#read 6, iclass 21, count 0 2006.285.19:26:00.68#ibcon#end of sib2, iclass 21, count 0 2006.285.19:26:00.68#ibcon#*after write, iclass 21, count 0 2006.285.19:26:00.68#ibcon#*before return 0, iclass 21, count 0 2006.285.19:26:00.68#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:26:00.68#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:26:00.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.19:26:00.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.19:26:00.68$vck44/valo=2,534.99 2006.285.19:26:00.68#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.19:26:00.68#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.19:26:00.68#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:00.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:26:00.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:26:00.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:26:00.68#ibcon#enter wrdev, iclass 27, count 0 2006.285.19:26:00.68#ibcon#first serial, iclass 27, count 0 2006.285.19:26:00.68#ibcon#enter sib2, iclass 27, count 0 2006.285.19:26:00.68#ibcon#flushed, iclass 27, count 0 2006.285.19:26:00.68#ibcon#about to write, iclass 27, count 0 2006.285.19:26:00.68#ibcon#wrote, iclass 27, count 0 2006.285.19:26:00.68#ibcon#about to read 3, iclass 27, count 0 2006.285.19:26:00.70#ibcon#read 3, iclass 27, count 0 2006.285.19:26:00.70#ibcon#about to read 4, iclass 27, count 0 2006.285.19:26:00.70#ibcon#read 4, iclass 27, count 0 2006.285.19:26:00.70#ibcon#about to read 5, iclass 27, count 0 2006.285.19:26:00.70#ibcon#read 5, iclass 27, count 0 2006.285.19:26:00.70#ibcon#about to read 6, iclass 27, count 0 2006.285.19:26:00.70#ibcon#read 6, iclass 27, count 0 2006.285.19:26:00.70#ibcon#end of sib2, iclass 27, count 0 2006.285.19:26:00.70#ibcon#*mode == 0, iclass 27, count 0 2006.285.19:26:00.70#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.19:26:00.70#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.19:26:00.70#ibcon#*before write, iclass 27, count 0 2006.285.19:26:00.70#ibcon#enter sib2, iclass 27, count 0 2006.285.19:26:00.70#ibcon#flushed, iclass 27, count 0 2006.285.19:26:00.70#ibcon#about to write, iclass 27, count 0 2006.285.19:26:00.70#ibcon#wrote, iclass 27, count 0 2006.285.19:26:00.70#ibcon#about to read 3, iclass 27, count 0 2006.285.19:26:00.74#ibcon#read 3, iclass 27, count 0 2006.285.19:26:00.74#ibcon#about to read 4, iclass 27, count 0 2006.285.19:26:00.74#ibcon#read 4, iclass 27, count 0 2006.285.19:26:00.74#ibcon#about to read 5, iclass 27, count 0 2006.285.19:26:00.74#ibcon#read 5, iclass 27, count 0 2006.285.19:26:00.74#ibcon#about to read 6, iclass 27, count 0 2006.285.19:26:00.74#ibcon#read 6, iclass 27, count 0 2006.285.19:26:00.74#ibcon#end of sib2, iclass 27, count 0 2006.285.19:26:00.74#ibcon#*after write, iclass 27, count 0 2006.285.19:26:00.74#ibcon#*before return 0, iclass 27, count 0 2006.285.19:26:00.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:26:00.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:26:00.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.19:26:00.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.19:26:00.74$vck44/va=2,6 2006.285.19:26:00.74#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.19:26:00.74#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.19:26:00.74#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:00.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:26:00.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:26:00.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:26:00.80#ibcon#enter wrdev, iclass 29, count 2 2006.285.19:26:00.80#ibcon#first serial, iclass 29, count 2 2006.285.19:26:00.80#ibcon#enter sib2, iclass 29, count 2 2006.285.19:26:00.80#ibcon#flushed, iclass 29, count 2 2006.285.19:26:00.80#ibcon#about to write, iclass 29, count 2 2006.285.19:26:00.80#ibcon#wrote, iclass 29, count 2 2006.285.19:26:00.80#ibcon#about to read 3, iclass 29, count 2 2006.285.19:26:00.82#ibcon#read 3, iclass 29, count 2 2006.285.19:26:00.82#ibcon#about to read 4, iclass 29, count 2 2006.285.19:26:00.82#ibcon#read 4, iclass 29, count 2 2006.285.19:26:00.82#ibcon#about to read 5, iclass 29, count 2 2006.285.19:26:00.82#ibcon#read 5, iclass 29, count 2 2006.285.19:26:00.82#ibcon#about to read 6, iclass 29, count 2 2006.285.19:26:00.82#ibcon#read 6, iclass 29, count 2 2006.285.19:26:00.82#ibcon#end of sib2, iclass 29, count 2 2006.285.19:26:00.82#ibcon#*mode == 0, iclass 29, count 2 2006.285.19:26:00.82#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.19:26:00.82#ibcon#[25=AT02-06\r\n] 2006.285.19:26:00.82#ibcon#*before write, iclass 29, count 2 2006.285.19:26:00.82#ibcon#enter sib2, iclass 29, count 2 2006.285.19:26:00.82#ibcon#flushed, iclass 29, count 2 2006.285.19:26:00.82#ibcon#about to write, iclass 29, count 2 2006.285.19:26:00.82#ibcon#wrote, iclass 29, count 2 2006.285.19:26:00.82#ibcon#about to read 3, iclass 29, count 2 2006.285.19:26:00.85#ibcon#read 3, iclass 29, count 2 2006.285.19:26:00.85#ibcon#about to read 4, iclass 29, count 2 2006.285.19:26:00.85#ibcon#read 4, iclass 29, count 2 2006.285.19:26:00.85#ibcon#about to read 5, iclass 29, count 2 2006.285.19:26:00.85#ibcon#read 5, iclass 29, count 2 2006.285.19:26:00.85#ibcon#about to read 6, iclass 29, count 2 2006.285.19:26:00.85#ibcon#read 6, iclass 29, count 2 2006.285.19:26:00.85#ibcon#end of sib2, iclass 29, count 2 2006.285.19:26:00.85#ibcon#*after write, iclass 29, count 2 2006.285.19:26:00.85#ibcon#*before return 0, iclass 29, count 2 2006.285.19:26:00.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:26:00.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:26:00.85#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.19:26:00.85#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:00.85#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:26:00.97#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:26:01.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:26:01.53#ibcon#enter wrdev, iclass 29, count 0 2006.285.19:26:01.53#ibcon#first serial, iclass 29, count 0 2006.285.19:26:01.53#ibcon#enter sib2, iclass 29, count 0 2006.285.19:26:01.53#ibcon#flushed, iclass 29, count 0 2006.285.19:26:01.53#ibcon#about to write, iclass 29, count 0 2006.285.19:26:01.53#ibcon#wrote, iclass 29, count 0 2006.285.19:26:01.53#ibcon#about to read 3, iclass 29, count 0 2006.285.19:26:01.55#ibcon#read 3, iclass 29, count 0 2006.285.19:26:01.55#ibcon#about to read 4, iclass 29, count 0 2006.285.19:26:01.55#ibcon#read 4, iclass 29, count 0 2006.285.19:26:01.55#ibcon#about to read 5, iclass 29, count 0 2006.285.19:26:01.55#ibcon#read 5, iclass 29, count 0 2006.285.19:26:01.55#ibcon#about to read 6, iclass 29, count 0 2006.285.19:26:01.55#ibcon#read 6, iclass 29, count 0 2006.285.19:26:01.55#ibcon#end of sib2, iclass 29, count 0 2006.285.19:26:01.55#ibcon#*mode == 0, iclass 29, count 0 2006.285.19:26:01.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.19:26:01.55#ibcon#[25=USB\r\n] 2006.285.19:26:01.55#ibcon#*before write, iclass 29, count 0 2006.285.19:26:01.55#ibcon#enter sib2, iclass 29, count 0 2006.285.19:26:01.55#ibcon#flushed, iclass 29, count 0 2006.285.19:26:01.55#ibcon#about to write, iclass 29, count 0 2006.285.19:26:01.55#ibcon#wrote, iclass 29, count 0 2006.285.19:26:01.55#ibcon#about to read 3, iclass 29, count 0 2006.285.19:26:01.58#ibcon#read 3, iclass 29, count 0 2006.285.19:26:01.58#ibcon#about to read 4, iclass 29, count 0 2006.285.19:26:01.58#ibcon#read 4, iclass 29, count 0 2006.285.19:26:01.58#ibcon#about to read 5, iclass 29, count 0 2006.285.19:26:01.58#ibcon#read 5, iclass 29, count 0 2006.285.19:26:01.58#ibcon#about to read 6, iclass 29, count 0 2006.285.19:26:01.58#ibcon#read 6, iclass 29, count 0 2006.285.19:26:01.58#ibcon#end of sib2, iclass 29, count 0 2006.285.19:26:01.58#ibcon#*after write, iclass 29, count 0 2006.285.19:26:01.58#ibcon#*before return 0, iclass 29, count 0 2006.285.19:26:01.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:26:01.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:26:01.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.19:26:01.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.19:26:01.58$vck44/valo=3,564.99 2006.285.19:26:01.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.19:26:01.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.19:26:01.58#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:01.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:26:01.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:26:01.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:26:01.58#ibcon#enter wrdev, iclass 31, count 0 2006.285.19:26:01.58#ibcon#first serial, iclass 31, count 0 2006.285.19:26:01.58#ibcon#enter sib2, iclass 31, count 0 2006.285.19:26:01.58#ibcon#flushed, iclass 31, count 0 2006.285.19:26:01.58#ibcon#about to write, iclass 31, count 0 2006.285.19:26:01.58#ibcon#wrote, iclass 31, count 0 2006.285.19:26:01.58#ibcon#about to read 3, iclass 31, count 0 2006.285.19:26:01.60#ibcon#read 3, iclass 31, count 0 2006.285.19:26:01.60#ibcon#about to read 4, iclass 31, count 0 2006.285.19:26:01.60#ibcon#read 4, iclass 31, count 0 2006.285.19:26:01.60#ibcon#about to read 5, iclass 31, count 0 2006.285.19:26:01.60#ibcon#read 5, iclass 31, count 0 2006.285.19:26:01.60#ibcon#about to read 6, iclass 31, count 0 2006.285.19:26:01.60#ibcon#read 6, iclass 31, count 0 2006.285.19:26:01.60#ibcon#end of sib2, iclass 31, count 0 2006.285.19:26:01.60#ibcon#*mode == 0, iclass 31, count 0 2006.285.19:26:01.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.19:26:01.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.19:26:01.60#ibcon#*before write, iclass 31, count 0 2006.285.19:26:01.60#ibcon#enter sib2, iclass 31, count 0 2006.285.19:26:01.60#ibcon#flushed, iclass 31, count 0 2006.285.19:26:01.60#ibcon#about to write, iclass 31, count 0 2006.285.19:26:01.60#ibcon#wrote, iclass 31, count 0 2006.285.19:26:01.60#ibcon#about to read 3, iclass 31, count 0 2006.285.19:26:01.64#ibcon#read 3, iclass 31, count 0 2006.285.19:26:01.64#ibcon#about to read 4, iclass 31, count 0 2006.285.19:26:01.64#ibcon#read 4, iclass 31, count 0 2006.285.19:26:01.64#ibcon#about to read 5, iclass 31, count 0 2006.285.19:26:01.64#ibcon#read 5, iclass 31, count 0 2006.285.19:26:01.64#ibcon#about to read 6, iclass 31, count 0 2006.285.19:26:01.64#ibcon#read 6, iclass 31, count 0 2006.285.19:26:01.64#ibcon#end of sib2, iclass 31, count 0 2006.285.19:26:01.64#ibcon#*after write, iclass 31, count 0 2006.285.19:26:01.64#ibcon#*before return 0, iclass 31, count 0 2006.285.19:26:01.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:26:01.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:26:01.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.19:26:01.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.19:26:01.64$vck44/va=3,7 2006.285.19:26:01.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.19:26:01.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.19:26:01.64#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:01.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:26:01.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:26:01.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:26:01.70#ibcon#enter wrdev, iclass 33, count 2 2006.285.19:26:01.70#ibcon#first serial, iclass 33, count 2 2006.285.19:26:01.70#ibcon#enter sib2, iclass 33, count 2 2006.285.19:26:01.70#ibcon#flushed, iclass 33, count 2 2006.285.19:26:01.70#ibcon#about to write, iclass 33, count 2 2006.285.19:26:01.70#ibcon#wrote, iclass 33, count 2 2006.285.19:26:01.70#ibcon#about to read 3, iclass 33, count 2 2006.285.19:26:01.72#ibcon#read 3, iclass 33, count 2 2006.285.19:26:01.72#ibcon#about to read 4, iclass 33, count 2 2006.285.19:26:01.72#ibcon#read 4, iclass 33, count 2 2006.285.19:26:01.72#ibcon#about to read 5, iclass 33, count 2 2006.285.19:26:01.72#ibcon#read 5, iclass 33, count 2 2006.285.19:26:01.72#ibcon#about to read 6, iclass 33, count 2 2006.285.19:26:01.72#ibcon#read 6, iclass 33, count 2 2006.285.19:26:01.72#ibcon#end of sib2, iclass 33, count 2 2006.285.19:26:01.72#ibcon#*mode == 0, iclass 33, count 2 2006.285.19:26:01.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.19:26:01.72#ibcon#[25=AT03-07\r\n] 2006.285.19:26:01.72#ibcon#*before write, iclass 33, count 2 2006.285.19:26:01.72#ibcon#enter sib2, iclass 33, count 2 2006.285.19:26:01.72#ibcon#flushed, iclass 33, count 2 2006.285.19:26:01.72#ibcon#about to write, iclass 33, count 2 2006.285.19:26:01.72#ibcon#wrote, iclass 33, count 2 2006.285.19:26:01.72#ibcon#about to read 3, iclass 33, count 2 2006.285.19:26:01.75#ibcon#read 3, iclass 33, count 2 2006.285.19:26:01.75#ibcon#about to read 4, iclass 33, count 2 2006.285.19:26:01.75#ibcon#read 4, iclass 33, count 2 2006.285.19:26:01.75#ibcon#about to read 5, iclass 33, count 2 2006.285.19:26:01.75#ibcon#read 5, iclass 33, count 2 2006.285.19:26:01.75#ibcon#about to read 6, iclass 33, count 2 2006.285.19:26:01.75#ibcon#read 6, iclass 33, count 2 2006.285.19:26:01.75#ibcon#end of sib2, iclass 33, count 2 2006.285.19:26:01.75#ibcon#*after write, iclass 33, count 2 2006.285.19:26:01.75#ibcon#*before return 0, iclass 33, count 2 2006.285.19:26:01.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:26:01.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:26:01.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.19:26:01.75#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:01.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:26:01.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:26:02.02#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:26:02.02#ibcon#enter wrdev, iclass 33, count 0 2006.285.19:26:02.02#ibcon#first serial, iclass 33, count 0 2006.285.19:26:02.02#ibcon#enter sib2, iclass 33, count 0 2006.285.19:26:02.02#ibcon#flushed, iclass 33, count 0 2006.285.19:26:02.02#ibcon#about to write, iclass 33, count 0 2006.285.19:26:02.02#ibcon#wrote, iclass 33, count 0 2006.285.19:26:02.02#ibcon#about to read 3, iclass 33, count 0 2006.285.19:26:02.04#ibcon#read 3, iclass 33, count 0 2006.285.19:26:02.04#ibcon#about to read 4, iclass 33, count 0 2006.285.19:26:02.04#ibcon#read 4, iclass 33, count 0 2006.285.19:26:02.04#ibcon#about to read 5, iclass 33, count 0 2006.285.19:26:02.04#ibcon#read 5, iclass 33, count 0 2006.285.19:26:02.04#ibcon#about to read 6, iclass 33, count 0 2006.285.19:26:02.04#ibcon#read 6, iclass 33, count 0 2006.285.19:26:02.04#ibcon#end of sib2, iclass 33, count 0 2006.285.19:26:02.04#ibcon#*mode == 0, iclass 33, count 0 2006.285.19:26:02.04#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.19:26:02.04#ibcon#[25=USB\r\n] 2006.285.19:26:02.04#ibcon#*before write, iclass 33, count 0 2006.285.19:26:02.04#ibcon#enter sib2, iclass 33, count 0 2006.285.19:26:02.04#ibcon#flushed, iclass 33, count 0 2006.285.19:26:02.04#ibcon#about to write, iclass 33, count 0 2006.285.19:26:02.04#ibcon#wrote, iclass 33, count 0 2006.285.19:26:02.04#ibcon#about to read 3, iclass 33, count 0 2006.285.19:26:02.07#ibcon#read 3, iclass 33, count 0 2006.285.19:26:02.07#ibcon#about to read 4, iclass 33, count 0 2006.285.19:26:02.07#ibcon#read 4, iclass 33, count 0 2006.285.19:26:02.07#ibcon#about to read 5, iclass 33, count 0 2006.285.19:26:02.07#ibcon#read 5, iclass 33, count 0 2006.285.19:26:02.07#ibcon#about to read 6, iclass 33, count 0 2006.285.19:26:02.07#ibcon#read 6, iclass 33, count 0 2006.285.19:26:02.07#ibcon#end of sib2, iclass 33, count 0 2006.285.19:26:02.07#ibcon#*after write, iclass 33, count 0 2006.285.19:26:02.07#ibcon#*before return 0, iclass 33, count 0 2006.285.19:26:02.07#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:26:02.07#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:26:02.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.19:26:02.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.19:26:02.07$vck44/valo=4,624.99 2006.285.19:26:02.07#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.19:26:02.07#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.19:26:02.07#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:02.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:26:02.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:26:02.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:26:02.07#ibcon#enter wrdev, iclass 35, count 0 2006.285.19:26:02.07#ibcon#first serial, iclass 35, count 0 2006.285.19:26:02.07#ibcon#enter sib2, iclass 35, count 0 2006.285.19:26:02.07#ibcon#flushed, iclass 35, count 0 2006.285.19:26:02.07#ibcon#about to write, iclass 35, count 0 2006.285.19:26:02.07#ibcon#wrote, iclass 35, count 0 2006.285.19:26:02.07#ibcon#about to read 3, iclass 35, count 0 2006.285.19:26:02.09#ibcon#read 3, iclass 35, count 0 2006.285.19:26:02.09#ibcon#about to read 4, iclass 35, count 0 2006.285.19:26:02.09#ibcon#read 4, iclass 35, count 0 2006.285.19:26:02.09#ibcon#about to read 5, iclass 35, count 0 2006.285.19:26:02.09#ibcon#read 5, iclass 35, count 0 2006.285.19:26:02.09#ibcon#about to read 6, iclass 35, count 0 2006.285.19:26:02.09#ibcon#read 6, iclass 35, count 0 2006.285.19:26:02.09#ibcon#end of sib2, iclass 35, count 0 2006.285.19:26:02.09#ibcon#*mode == 0, iclass 35, count 0 2006.285.19:26:02.09#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.19:26:02.09#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.19:26:02.09#ibcon#*before write, iclass 35, count 0 2006.285.19:26:02.09#ibcon#enter sib2, iclass 35, count 0 2006.285.19:26:02.09#ibcon#flushed, iclass 35, count 0 2006.285.19:26:02.09#ibcon#about to write, iclass 35, count 0 2006.285.19:26:02.09#ibcon#wrote, iclass 35, count 0 2006.285.19:26:02.09#ibcon#about to read 3, iclass 35, count 0 2006.285.19:26:02.13#ibcon#read 3, iclass 35, count 0 2006.285.19:26:02.13#ibcon#about to read 4, iclass 35, count 0 2006.285.19:26:02.13#ibcon#read 4, iclass 35, count 0 2006.285.19:26:02.13#ibcon#about to read 5, iclass 35, count 0 2006.285.19:26:02.13#ibcon#read 5, iclass 35, count 0 2006.285.19:26:02.13#ibcon#about to read 6, iclass 35, count 0 2006.285.19:26:02.13#ibcon#read 6, iclass 35, count 0 2006.285.19:26:02.13#ibcon#end of sib2, iclass 35, count 0 2006.285.19:26:02.13#ibcon#*after write, iclass 35, count 0 2006.285.19:26:02.13#ibcon#*before return 0, iclass 35, count 0 2006.285.19:26:02.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:26:02.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:26:02.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.19:26:02.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.19:26:02.13$vck44/va=4,6 2006.285.19:26:02.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.19:26:02.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.19:26:02.13#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:02.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:26:02.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:26:02.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:26:02.19#ibcon#enter wrdev, iclass 37, count 2 2006.285.19:26:02.19#ibcon#first serial, iclass 37, count 2 2006.285.19:26:02.19#ibcon#enter sib2, iclass 37, count 2 2006.285.19:26:02.19#ibcon#flushed, iclass 37, count 2 2006.285.19:26:02.19#ibcon#about to write, iclass 37, count 2 2006.285.19:26:02.19#ibcon#wrote, iclass 37, count 2 2006.285.19:26:02.19#ibcon#about to read 3, iclass 37, count 2 2006.285.19:26:02.21#ibcon#read 3, iclass 37, count 2 2006.285.19:26:02.21#ibcon#about to read 4, iclass 37, count 2 2006.285.19:26:02.21#ibcon#read 4, iclass 37, count 2 2006.285.19:26:02.21#ibcon#about to read 5, iclass 37, count 2 2006.285.19:26:02.21#ibcon#read 5, iclass 37, count 2 2006.285.19:26:02.21#ibcon#about to read 6, iclass 37, count 2 2006.285.19:26:02.21#ibcon#read 6, iclass 37, count 2 2006.285.19:26:02.21#ibcon#end of sib2, iclass 37, count 2 2006.285.19:26:02.21#ibcon#*mode == 0, iclass 37, count 2 2006.285.19:26:02.21#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.19:26:02.21#ibcon#[25=AT04-06\r\n] 2006.285.19:26:02.21#ibcon#*before write, iclass 37, count 2 2006.285.19:26:02.21#ibcon#enter sib2, iclass 37, count 2 2006.285.19:26:02.21#ibcon#flushed, iclass 37, count 2 2006.285.19:26:02.21#ibcon#about to write, iclass 37, count 2 2006.285.19:26:02.21#ibcon#wrote, iclass 37, count 2 2006.285.19:26:02.21#ibcon#about to read 3, iclass 37, count 2 2006.285.19:26:02.24#ibcon#read 3, iclass 37, count 2 2006.285.19:26:02.24#ibcon#about to read 4, iclass 37, count 2 2006.285.19:26:02.24#ibcon#read 4, iclass 37, count 2 2006.285.19:26:02.24#ibcon#about to read 5, iclass 37, count 2 2006.285.19:26:02.24#ibcon#read 5, iclass 37, count 2 2006.285.19:26:02.24#ibcon#about to read 6, iclass 37, count 2 2006.285.19:26:02.24#ibcon#read 6, iclass 37, count 2 2006.285.19:26:02.24#ibcon#end of sib2, iclass 37, count 2 2006.285.19:26:02.24#ibcon#*after write, iclass 37, count 2 2006.285.19:26:02.24#ibcon#*before return 0, iclass 37, count 2 2006.285.19:26:02.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:26:02.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:26:02.24#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.19:26:02.24#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:02.24#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:26:02.36#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:26:02.36#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:26:02.36#ibcon#enter wrdev, iclass 37, count 0 2006.285.19:26:02.36#ibcon#first serial, iclass 37, count 0 2006.285.19:26:02.36#ibcon#enter sib2, iclass 37, count 0 2006.285.19:26:02.36#ibcon#flushed, iclass 37, count 0 2006.285.19:26:02.36#ibcon#about to write, iclass 37, count 0 2006.285.19:26:02.36#ibcon#wrote, iclass 37, count 0 2006.285.19:26:02.36#ibcon#about to read 3, iclass 37, count 0 2006.285.19:26:02.38#ibcon#read 3, iclass 37, count 0 2006.285.19:26:02.38#ibcon#about to read 4, iclass 37, count 0 2006.285.19:26:02.38#ibcon#read 4, iclass 37, count 0 2006.285.19:26:02.38#ibcon#about to read 5, iclass 37, count 0 2006.285.19:26:02.38#ibcon#read 5, iclass 37, count 0 2006.285.19:26:02.38#ibcon#about to read 6, iclass 37, count 0 2006.285.19:26:02.38#ibcon#read 6, iclass 37, count 0 2006.285.19:26:02.38#ibcon#end of sib2, iclass 37, count 0 2006.285.19:26:02.38#ibcon#*mode == 0, iclass 37, count 0 2006.285.19:26:02.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.19:26:02.38#ibcon#[25=USB\r\n] 2006.285.19:26:02.38#ibcon#*before write, iclass 37, count 0 2006.285.19:26:02.38#ibcon#enter sib2, iclass 37, count 0 2006.285.19:26:02.38#ibcon#flushed, iclass 37, count 0 2006.285.19:26:02.38#ibcon#about to write, iclass 37, count 0 2006.285.19:26:02.38#ibcon#wrote, iclass 37, count 0 2006.285.19:26:02.38#ibcon#about to read 3, iclass 37, count 0 2006.285.19:26:02.41#ibcon#read 3, iclass 37, count 0 2006.285.19:26:02.41#ibcon#about to read 4, iclass 37, count 0 2006.285.19:26:02.41#ibcon#read 4, iclass 37, count 0 2006.285.19:26:02.41#ibcon#about to read 5, iclass 37, count 0 2006.285.19:26:02.41#ibcon#read 5, iclass 37, count 0 2006.285.19:26:02.41#ibcon#about to read 6, iclass 37, count 0 2006.285.19:26:02.41#ibcon#read 6, iclass 37, count 0 2006.285.19:26:02.41#ibcon#end of sib2, iclass 37, count 0 2006.285.19:26:02.41#ibcon#*after write, iclass 37, count 0 2006.285.19:26:02.41#ibcon#*before return 0, iclass 37, count 0 2006.285.19:26:02.41#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:26:02.41#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:26:02.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.19:26:02.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.19:26:02.41$vck44/valo=5,734.99 2006.285.19:26:02.41#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.19:26:02.41#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.19:26:02.41#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:02.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:26:02.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:26:02.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:26:02.41#ibcon#enter wrdev, iclass 39, count 0 2006.285.19:26:02.41#ibcon#first serial, iclass 39, count 0 2006.285.19:26:02.41#ibcon#enter sib2, iclass 39, count 0 2006.285.19:26:02.41#ibcon#flushed, iclass 39, count 0 2006.285.19:26:02.41#ibcon#about to write, iclass 39, count 0 2006.285.19:26:02.41#ibcon#wrote, iclass 39, count 0 2006.285.19:26:02.41#ibcon#about to read 3, iclass 39, count 0 2006.285.19:26:02.43#ibcon#read 3, iclass 39, count 0 2006.285.19:26:02.43#ibcon#about to read 4, iclass 39, count 0 2006.285.19:26:02.43#ibcon#read 4, iclass 39, count 0 2006.285.19:26:02.43#ibcon#about to read 5, iclass 39, count 0 2006.285.19:26:02.43#ibcon#read 5, iclass 39, count 0 2006.285.19:26:02.43#ibcon#about to read 6, iclass 39, count 0 2006.285.19:26:02.43#ibcon#read 6, iclass 39, count 0 2006.285.19:26:02.43#ibcon#end of sib2, iclass 39, count 0 2006.285.19:26:02.43#ibcon#*mode == 0, iclass 39, count 0 2006.285.19:26:02.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.19:26:02.43#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.19:26:02.43#ibcon#*before write, iclass 39, count 0 2006.285.19:26:02.43#ibcon#enter sib2, iclass 39, count 0 2006.285.19:26:02.43#ibcon#flushed, iclass 39, count 0 2006.285.19:26:02.43#ibcon#about to write, iclass 39, count 0 2006.285.19:26:02.43#ibcon#wrote, iclass 39, count 0 2006.285.19:26:02.43#ibcon#about to read 3, iclass 39, count 0 2006.285.19:26:02.47#ibcon#read 3, iclass 39, count 0 2006.285.19:26:02.47#ibcon#about to read 4, iclass 39, count 0 2006.285.19:26:02.47#ibcon#read 4, iclass 39, count 0 2006.285.19:26:02.47#ibcon#about to read 5, iclass 39, count 0 2006.285.19:26:02.47#ibcon#read 5, iclass 39, count 0 2006.285.19:26:02.47#ibcon#about to read 6, iclass 39, count 0 2006.285.19:26:02.47#ibcon#read 6, iclass 39, count 0 2006.285.19:26:02.47#ibcon#end of sib2, iclass 39, count 0 2006.285.19:26:02.47#ibcon#*after write, iclass 39, count 0 2006.285.19:26:02.47#ibcon#*before return 0, iclass 39, count 0 2006.285.19:26:02.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:26:02.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:26:02.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.19:26:02.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.19:26:02.47$vck44/va=5,3 2006.285.19:26:02.47#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.19:26:02.47#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.19:26:02.47#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:02.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:26:02.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:26:02.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:26:02.53#ibcon#enter wrdev, iclass 3, count 2 2006.285.19:26:02.53#ibcon#first serial, iclass 3, count 2 2006.285.19:26:02.53#ibcon#enter sib2, iclass 3, count 2 2006.285.19:26:02.53#ibcon#flushed, iclass 3, count 2 2006.285.19:26:02.53#ibcon#about to write, iclass 3, count 2 2006.285.19:26:02.53#ibcon#wrote, iclass 3, count 2 2006.285.19:26:02.53#ibcon#about to read 3, iclass 3, count 2 2006.285.19:26:02.55#ibcon#read 3, iclass 3, count 2 2006.285.19:26:02.55#ibcon#about to read 4, iclass 3, count 2 2006.285.19:26:02.55#ibcon#read 4, iclass 3, count 2 2006.285.19:26:02.55#ibcon#about to read 5, iclass 3, count 2 2006.285.19:26:02.55#ibcon#read 5, iclass 3, count 2 2006.285.19:26:02.55#ibcon#about to read 6, iclass 3, count 2 2006.285.19:26:02.55#ibcon#read 6, iclass 3, count 2 2006.285.19:26:02.55#ibcon#end of sib2, iclass 3, count 2 2006.285.19:26:02.55#ibcon#*mode == 0, iclass 3, count 2 2006.285.19:26:02.55#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.19:26:02.55#ibcon#[25=AT05-03\r\n] 2006.285.19:26:02.55#ibcon#*before write, iclass 3, count 2 2006.285.19:26:02.55#ibcon#enter sib2, iclass 3, count 2 2006.285.19:26:02.55#ibcon#flushed, iclass 3, count 2 2006.285.19:26:02.55#ibcon#about to write, iclass 3, count 2 2006.285.19:26:02.55#ibcon#wrote, iclass 3, count 2 2006.285.19:26:02.55#ibcon#about to read 3, iclass 3, count 2 2006.285.19:26:02.58#ibcon#read 3, iclass 3, count 2 2006.285.19:26:02.58#ibcon#about to read 4, iclass 3, count 2 2006.285.19:26:02.58#ibcon#read 4, iclass 3, count 2 2006.285.19:26:02.58#ibcon#about to read 5, iclass 3, count 2 2006.285.19:26:02.58#ibcon#read 5, iclass 3, count 2 2006.285.19:26:02.58#ibcon#about to read 6, iclass 3, count 2 2006.285.19:26:02.58#ibcon#read 6, iclass 3, count 2 2006.285.19:26:02.58#ibcon#end of sib2, iclass 3, count 2 2006.285.19:26:02.58#ibcon#*after write, iclass 3, count 2 2006.285.19:26:02.58#ibcon#*before return 0, iclass 3, count 2 2006.285.19:26:02.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:26:02.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:26:02.58#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.19:26:02.58#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:02.58#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:26:02.70#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:26:02.70#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:26:02.70#ibcon#enter wrdev, iclass 3, count 0 2006.285.19:26:02.70#ibcon#first serial, iclass 3, count 0 2006.285.19:26:02.70#ibcon#enter sib2, iclass 3, count 0 2006.285.19:26:02.70#ibcon#flushed, iclass 3, count 0 2006.285.19:26:02.70#ibcon#about to write, iclass 3, count 0 2006.285.19:26:02.70#ibcon#wrote, iclass 3, count 0 2006.285.19:26:02.70#ibcon#about to read 3, iclass 3, count 0 2006.285.19:26:02.72#ibcon#read 3, iclass 3, count 0 2006.285.19:26:02.72#ibcon#about to read 4, iclass 3, count 0 2006.285.19:26:02.72#ibcon#read 4, iclass 3, count 0 2006.285.19:26:02.72#ibcon#about to read 5, iclass 3, count 0 2006.285.19:26:02.72#ibcon#read 5, iclass 3, count 0 2006.285.19:26:02.72#ibcon#about to read 6, iclass 3, count 0 2006.285.19:26:02.72#ibcon#read 6, iclass 3, count 0 2006.285.19:26:02.72#ibcon#end of sib2, iclass 3, count 0 2006.285.19:26:02.72#ibcon#*mode == 0, iclass 3, count 0 2006.285.19:26:02.72#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.19:26:02.72#ibcon#[25=USB\r\n] 2006.285.19:26:02.72#ibcon#*before write, iclass 3, count 0 2006.285.19:26:02.72#ibcon#enter sib2, iclass 3, count 0 2006.285.19:26:02.72#ibcon#flushed, iclass 3, count 0 2006.285.19:26:02.72#ibcon#about to write, iclass 3, count 0 2006.285.19:26:02.72#ibcon#wrote, iclass 3, count 0 2006.285.19:26:02.72#ibcon#about to read 3, iclass 3, count 0 2006.285.19:26:02.75#ibcon#read 3, iclass 3, count 0 2006.285.19:26:02.75#ibcon#about to read 4, iclass 3, count 0 2006.285.19:26:02.75#ibcon#read 4, iclass 3, count 0 2006.285.19:26:02.75#ibcon#about to read 5, iclass 3, count 0 2006.285.19:26:02.75#ibcon#read 5, iclass 3, count 0 2006.285.19:26:02.75#ibcon#about to read 6, iclass 3, count 0 2006.285.19:26:02.75#ibcon#read 6, iclass 3, count 0 2006.285.19:26:02.75#ibcon#end of sib2, iclass 3, count 0 2006.285.19:26:02.75#ibcon#*after write, iclass 3, count 0 2006.285.19:26:02.75#ibcon#*before return 0, iclass 3, count 0 2006.285.19:26:02.75#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:26:02.75#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:26:02.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.19:26:02.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.19:26:02.75$vck44/valo=6,814.99 2006.285.19:26:02.75#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.19:26:02.75#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.19:26:02.75#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:02.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:26:02.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:26:02.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:26:02.75#ibcon#enter wrdev, iclass 5, count 0 2006.285.19:26:02.75#ibcon#first serial, iclass 5, count 0 2006.285.19:26:02.75#ibcon#enter sib2, iclass 5, count 0 2006.285.19:26:02.75#ibcon#flushed, iclass 5, count 0 2006.285.19:26:02.75#ibcon#about to write, iclass 5, count 0 2006.285.19:26:02.75#ibcon#wrote, iclass 5, count 0 2006.285.19:26:02.75#ibcon#about to read 3, iclass 5, count 0 2006.285.19:26:02.77#ibcon#read 3, iclass 5, count 0 2006.285.19:26:02.77#ibcon#about to read 4, iclass 5, count 0 2006.285.19:26:02.77#ibcon#read 4, iclass 5, count 0 2006.285.19:26:02.77#ibcon#about to read 5, iclass 5, count 0 2006.285.19:26:02.77#ibcon#read 5, iclass 5, count 0 2006.285.19:26:02.77#ibcon#about to read 6, iclass 5, count 0 2006.285.19:26:02.77#ibcon#read 6, iclass 5, count 0 2006.285.19:26:02.77#ibcon#end of sib2, iclass 5, count 0 2006.285.19:26:02.77#ibcon#*mode == 0, iclass 5, count 0 2006.285.19:26:02.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.19:26:02.77#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.19:26:02.77#ibcon#*before write, iclass 5, count 0 2006.285.19:26:02.77#ibcon#enter sib2, iclass 5, count 0 2006.285.19:26:02.77#ibcon#flushed, iclass 5, count 0 2006.285.19:26:02.77#ibcon#about to write, iclass 5, count 0 2006.285.19:26:02.77#ibcon#wrote, iclass 5, count 0 2006.285.19:26:02.77#ibcon#about to read 3, iclass 5, count 0 2006.285.19:26:02.81#ibcon#read 3, iclass 5, count 0 2006.285.19:26:02.81#ibcon#about to read 4, iclass 5, count 0 2006.285.19:26:02.81#ibcon#read 4, iclass 5, count 0 2006.285.19:26:02.81#ibcon#about to read 5, iclass 5, count 0 2006.285.19:26:02.81#ibcon#read 5, iclass 5, count 0 2006.285.19:26:02.81#ibcon#about to read 6, iclass 5, count 0 2006.285.19:26:02.81#ibcon#read 6, iclass 5, count 0 2006.285.19:26:02.81#ibcon#end of sib2, iclass 5, count 0 2006.285.19:26:02.81#ibcon#*after write, iclass 5, count 0 2006.285.19:26:02.81#ibcon#*before return 0, iclass 5, count 0 2006.285.19:26:02.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:26:02.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:26:02.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.19:26:02.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.19:26:02.81$vck44/va=6,4 2006.285.19:26:02.81#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.19:26:02.81#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.19:26:02.81#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:02.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:26:02.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:26:02.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:26:02.87#ibcon#enter wrdev, iclass 7, count 2 2006.285.19:26:02.87#ibcon#first serial, iclass 7, count 2 2006.285.19:26:02.87#ibcon#enter sib2, iclass 7, count 2 2006.285.19:26:02.87#ibcon#flushed, iclass 7, count 2 2006.285.19:26:02.87#ibcon#about to write, iclass 7, count 2 2006.285.19:26:02.87#ibcon#wrote, iclass 7, count 2 2006.285.19:26:02.87#ibcon#about to read 3, iclass 7, count 2 2006.285.19:26:02.89#ibcon#read 3, iclass 7, count 2 2006.285.19:26:02.89#ibcon#about to read 4, iclass 7, count 2 2006.285.19:26:02.89#ibcon#read 4, iclass 7, count 2 2006.285.19:26:02.89#ibcon#about to read 5, iclass 7, count 2 2006.285.19:26:02.89#ibcon#read 5, iclass 7, count 2 2006.285.19:26:02.89#ibcon#about to read 6, iclass 7, count 2 2006.285.19:26:02.89#ibcon#read 6, iclass 7, count 2 2006.285.19:26:02.89#ibcon#end of sib2, iclass 7, count 2 2006.285.19:26:02.89#ibcon#*mode == 0, iclass 7, count 2 2006.285.19:26:02.89#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.19:26:02.89#ibcon#[25=AT06-04\r\n] 2006.285.19:26:02.89#ibcon#*before write, iclass 7, count 2 2006.285.19:26:02.89#ibcon#enter sib2, iclass 7, count 2 2006.285.19:26:02.89#ibcon#flushed, iclass 7, count 2 2006.285.19:26:02.89#ibcon#about to write, iclass 7, count 2 2006.285.19:26:02.89#ibcon#wrote, iclass 7, count 2 2006.285.19:26:02.89#ibcon#about to read 3, iclass 7, count 2 2006.285.19:26:02.92#ibcon#read 3, iclass 7, count 2 2006.285.19:26:02.92#ibcon#about to read 4, iclass 7, count 2 2006.285.19:26:02.92#ibcon#read 4, iclass 7, count 2 2006.285.19:26:02.92#ibcon#about to read 5, iclass 7, count 2 2006.285.19:26:02.92#ibcon#read 5, iclass 7, count 2 2006.285.19:26:02.92#ibcon#about to read 6, iclass 7, count 2 2006.285.19:26:02.92#ibcon#read 6, iclass 7, count 2 2006.285.19:26:02.92#ibcon#end of sib2, iclass 7, count 2 2006.285.19:26:02.92#ibcon#*after write, iclass 7, count 2 2006.285.19:26:02.92#ibcon#*before return 0, iclass 7, count 2 2006.285.19:26:02.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:26:02.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:26:02.92#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.19:26:02.92#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:02.92#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:26:03.04#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:26:03.09#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:26:03.09#ibcon#enter wrdev, iclass 7, count 0 2006.285.19:26:03.09#ibcon#first serial, iclass 7, count 0 2006.285.19:26:03.09#ibcon#enter sib2, iclass 7, count 0 2006.285.19:26:03.09#ibcon#flushed, iclass 7, count 0 2006.285.19:26:03.09#ibcon#about to write, iclass 7, count 0 2006.285.19:26:03.09#ibcon#wrote, iclass 7, count 0 2006.285.19:26:03.09#ibcon#about to read 3, iclass 7, count 0 2006.285.19:26:03.11#ibcon#read 3, iclass 7, count 0 2006.285.19:26:03.11#ibcon#about to read 4, iclass 7, count 0 2006.285.19:26:03.11#ibcon#read 4, iclass 7, count 0 2006.285.19:26:03.11#ibcon#about to read 5, iclass 7, count 0 2006.285.19:26:03.11#ibcon#read 5, iclass 7, count 0 2006.285.19:26:03.11#ibcon#about to read 6, iclass 7, count 0 2006.285.19:26:03.11#ibcon#read 6, iclass 7, count 0 2006.285.19:26:03.11#ibcon#end of sib2, iclass 7, count 0 2006.285.19:26:03.11#ibcon#*mode == 0, iclass 7, count 0 2006.285.19:26:03.11#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.19:26:03.11#ibcon#[25=USB\r\n] 2006.285.19:26:03.11#ibcon#*before write, iclass 7, count 0 2006.285.19:26:03.11#ibcon#enter sib2, iclass 7, count 0 2006.285.19:26:03.11#ibcon#flushed, iclass 7, count 0 2006.285.19:26:03.11#ibcon#about to write, iclass 7, count 0 2006.285.19:26:03.11#ibcon#wrote, iclass 7, count 0 2006.285.19:26:03.11#ibcon#about to read 3, iclass 7, count 0 2006.285.19:26:03.14#ibcon#read 3, iclass 7, count 0 2006.285.19:26:03.14#ibcon#about to read 4, iclass 7, count 0 2006.285.19:26:03.14#ibcon#read 4, iclass 7, count 0 2006.285.19:26:03.14#ibcon#about to read 5, iclass 7, count 0 2006.285.19:26:03.14#ibcon#read 5, iclass 7, count 0 2006.285.19:26:03.14#ibcon#about to read 6, iclass 7, count 0 2006.285.19:26:03.14#ibcon#read 6, iclass 7, count 0 2006.285.19:26:03.14#ibcon#end of sib2, iclass 7, count 0 2006.285.19:26:03.14#ibcon#*after write, iclass 7, count 0 2006.285.19:26:03.14#ibcon#*before return 0, iclass 7, count 0 2006.285.19:26:03.14#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:26:03.14#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:26:03.14#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.19:26:03.14#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.19:26:03.14$vck44/valo=7,864.99 2006.285.19:26:03.14#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.19:26:03.14#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.19:26:03.14#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:03.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:26:03.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:26:03.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:26:03.14#ibcon#enter wrdev, iclass 11, count 0 2006.285.19:26:03.14#ibcon#first serial, iclass 11, count 0 2006.285.19:26:03.14#ibcon#enter sib2, iclass 11, count 0 2006.285.19:26:03.14#ibcon#flushed, iclass 11, count 0 2006.285.19:26:03.14#ibcon#about to write, iclass 11, count 0 2006.285.19:26:03.14#ibcon#wrote, iclass 11, count 0 2006.285.19:26:03.14#ibcon#about to read 3, iclass 11, count 0 2006.285.19:26:03.16#ibcon#read 3, iclass 11, count 0 2006.285.19:26:03.16#ibcon#about to read 4, iclass 11, count 0 2006.285.19:26:03.16#ibcon#read 4, iclass 11, count 0 2006.285.19:26:03.16#ibcon#about to read 5, iclass 11, count 0 2006.285.19:26:03.16#ibcon#read 5, iclass 11, count 0 2006.285.19:26:03.16#ibcon#about to read 6, iclass 11, count 0 2006.285.19:26:03.16#ibcon#read 6, iclass 11, count 0 2006.285.19:26:03.16#ibcon#end of sib2, iclass 11, count 0 2006.285.19:26:03.16#ibcon#*mode == 0, iclass 11, count 0 2006.285.19:26:03.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.19:26:03.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.19:26:03.16#ibcon#*before write, iclass 11, count 0 2006.285.19:26:03.16#ibcon#enter sib2, iclass 11, count 0 2006.285.19:26:03.16#ibcon#flushed, iclass 11, count 0 2006.285.19:26:03.16#ibcon#about to write, iclass 11, count 0 2006.285.19:26:03.16#ibcon#wrote, iclass 11, count 0 2006.285.19:26:03.16#ibcon#about to read 3, iclass 11, count 0 2006.285.19:26:03.20#ibcon#read 3, iclass 11, count 0 2006.285.19:26:03.20#ibcon#about to read 4, iclass 11, count 0 2006.285.19:26:03.20#ibcon#read 4, iclass 11, count 0 2006.285.19:26:03.20#ibcon#about to read 5, iclass 11, count 0 2006.285.19:26:03.20#ibcon#read 5, iclass 11, count 0 2006.285.19:26:03.20#ibcon#about to read 6, iclass 11, count 0 2006.285.19:26:03.20#ibcon#read 6, iclass 11, count 0 2006.285.19:26:03.20#ibcon#end of sib2, iclass 11, count 0 2006.285.19:26:03.20#ibcon#*after write, iclass 11, count 0 2006.285.19:26:03.20#ibcon#*before return 0, iclass 11, count 0 2006.285.19:26:03.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:26:03.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:26:03.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.19:26:03.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.19:26:03.20$vck44/va=7,4 2006.285.19:26:03.20#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.19:26:03.20#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.19:26:03.20#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:03.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:26:03.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:26:03.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:26:03.26#ibcon#enter wrdev, iclass 13, count 2 2006.285.19:26:03.26#ibcon#first serial, iclass 13, count 2 2006.285.19:26:03.26#ibcon#enter sib2, iclass 13, count 2 2006.285.19:26:03.26#ibcon#flushed, iclass 13, count 2 2006.285.19:26:03.26#ibcon#about to write, iclass 13, count 2 2006.285.19:26:03.26#ibcon#wrote, iclass 13, count 2 2006.285.19:26:03.26#ibcon#about to read 3, iclass 13, count 2 2006.285.19:26:03.28#ibcon#read 3, iclass 13, count 2 2006.285.19:26:03.28#ibcon#about to read 4, iclass 13, count 2 2006.285.19:26:03.28#ibcon#read 4, iclass 13, count 2 2006.285.19:26:03.28#ibcon#about to read 5, iclass 13, count 2 2006.285.19:26:03.28#ibcon#read 5, iclass 13, count 2 2006.285.19:26:03.28#ibcon#about to read 6, iclass 13, count 2 2006.285.19:26:03.28#ibcon#read 6, iclass 13, count 2 2006.285.19:26:03.28#ibcon#end of sib2, iclass 13, count 2 2006.285.19:26:03.28#ibcon#*mode == 0, iclass 13, count 2 2006.285.19:26:03.28#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.19:26:03.28#ibcon#[25=AT07-04\r\n] 2006.285.19:26:03.28#ibcon#*before write, iclass 13, count 2 2006.285.19:26:03.28#ibcon#enter sib2, iclass 13, count 2 2006.285.19:26:03.28#ibcon#flushed, iclass 13, count 2 2006.285.19:26:03.28#ibcon#about to write, iclass 13, count 2 2006.285.19:26:03.28#ibcon#wrote, iclass 13, count 2 2006.285.19:26:03.28#ibcon#about to read 3, iclass 13, count 2 2006.285.19:26:03.31#ibcon#read 3, iclass 13, count 2 2006.285.19:26:03.31#ibcon#about to read 4, iclass 13, count 2 2006.285.19:26:03.31#ibcon#read 4, iclass 13, count 2 2006.285.19:26:03.31#ibcon#about to read 5, iclass 13, count 2 2006.285.19:26:03.31#ibcon#read 5, iclass 13, count 2 2006.285.19:26:03.31#ibcon#about to read 6, iclass 13, count 2 2006.285.19:26:03.31#ibcon#read 6, iclass 13, count 2 2006.285.19:26:03.31#ibcon#end of sib2, iclass 13, count 2 2006.285.19:26:03.31#ibcon#*after write, iclass 13, count 2 2006.285.19:26:03.31#ibcon#*before return 0, iclass 13, count 2 2006.285.19:26:03.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:26:03.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:26:03.31#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.19:26:03.31#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:03.31#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:26:03.43#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:26:03.43#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:26:03.43#ibcon#enter wrdev, iclass 13, count 0 2006.285.19:26:03.43#ibcon#first serial, iclass 13, count 0 2006.285.19:26:03.43#ibcon#enter sib2, iclass 13, count 0 2006.285.19:26:03.43#ibcon#flushed, iclass 13, count 0 2006.285.19:26:03.43#ibcon#about to write, iclass 13, count 0 2006.285.19:26:03.43#ibcon#wrote, iclass 13, count 0 2006.285.19:26:03.43#ibcon#about to read 3, iclass 13, count 0 2006.285.19:26:03.45#ibcon#read 3, iclass 13, count 0 2006.285.19:26:03.45#ibcon#about to read 4, iclass 13, count 0 2006.285.19:26:03.45#ibcon#read 4, iclass 13, count 0 2006.285.19:26:03.45#ibcon#about to read 5, iclass 13, count 0 2006.285.19:26:03.45#ibcon#read 5, iclass 13, count 0 2006.285.19:26:03.45#ibcon#about to read 6, iclass 13, count 0 2006.285.19:26:03.45#ibcon#read 6, iclass 13, count 0 2006.285.19:26:03.45#ibcon#end of sib2, iclass 13, count 0 2006.285.19:26:03.45#ibcon#*mode == 0, iclass 13, count 0 2006.285.19:26:03.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.19:26:03.45#ibcon#[25=USB\r\n] 2006.285.19:26:03.45#ibcon#*before write, iclass 13, count 0 2006.285.19:26:03.45#ibcon#enter sib2, iclass 13, count 0 2006.285.19:26:03.45#ibcon#flushed, iclass 13, count 0 2006.285.19:26:03.45#ibcon#about to write, iclass 13, count 0 2006.285.19:26:03.45#ibcon#wrote, iclass 13, count 0 2006.285.19:26:03.45#ibcon#about to read 3, iclass 13, count 0 2006.285.19:26:03.48#ibcon#read 3, iclass 13, count 0 2006.285.19:26:03.48#ibcon#about to read 4, iclass 13, count 0 2006.285.19:26:03.48#ibcon#read 4, iclass 13, count 0 2006.285.19:26:03.48#ibcon#about to read 5, iclass 13, count 0 2006.285.19:26:03.48#ibcon#read 5, iclass 13, count 0 2006.285.19:26:03.48#ibcon#about to read 6, iclass 13, count 0 2006.285.19:26:03.48#ibcon#read 6, iclass 13, count 0 2006.285.19:26:03.48#ibcon#end of sib2, iclass 13, count 0 2006.285.19:26:03.48#ibcon#*after write, iclass 13, count 0 2006.285.19:26:03.48#ibcon#*before return 0, iclass 13, count 0 2006.285.19:26:03.48#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:26:03.48#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:26:03.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.19:26:03.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.19:26:03.48$vck44/valo=8,884.99 2006.285.19:26:03.48#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.19:26:03.48#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.19:26:03.48#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:03.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:26:03.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:26:03.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:26:03.48#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:26:03.48#ibcon#first serial, iclass 15, count 0 2006.285.19:26:03.48#ibcon#enter sib2, iclass 15, count 0 2006.285.19:26:03.48#ibcon#flushed, iclass 15, count 0 2006.285.19:26:03.48#ibcon#about to write, iclass 15, count 0 2006.285.19:26:03.48#ibcon#wrote, iclass 15, count 0 2006.285.19:26:03.48#ibcon#about to read 3, iclass 15, count 0 2006.285.19:26:03.50#ibcon#read 3, iclass 15, count 0 2006.285.19:26:03.50#ibcon#about to read 4, iclass 15, count 0 2006.285.19:26:03.50#ibcon#read 4, iclass 15, count 0 2006.285.19:26:03.50#ibcon#about to read 5, iclass 15, count 0 2006.285.19:26:03.50#ibcon#read 5, iclass 15, count 0 2006.285.19:26:03.50#ibcon#about to read 6, iclass 15, count 0 2006.285.19:26:03.50#ibcon#read 6, iclass 15, count 0 2006.285.19:26:03.50#ibcon#end of sib2, iclass 15, count 0 2006.285.19:26:03.50#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:26:03.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:26:03.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.19:26:03.50#ibcon#*before write, iclass 15, count 0 2006.285.19:26:03.50#ibcon#enter sib2, iclass 15, count 0 2006.285.19:26:03.50#ibcon#flushed, iclass 15, count 0 2006.285.19:26:03.50#ibcon#about to write, iclass 15, count 0 2006.285.19:26:03.50#ibcon#wrote, iclass 15, count 0 2006.285.19:26:03.50#ibcon#about to read 3, iclass 15, count 0 2006.285.19:26:03.54#ibcon#read 3, iclass 15, count 0 2006.285.19:26:03.54#ibcon#about to read 4, iclass 15, count 0 2006.285.19:26:03.54#ibcon#read 4, iclass 15, count 0 2006.285.19:26:03.54#ibcon#about to read 5, iclass 15, count 0 2006.285.19:26:03.54#ibcon#read 5, iclass 15, count 0 2006.285.19:26:03.54#ibcon#about to read 6, iclass 15, count 0 2006.285.19:26:03.54#ibcon#read 6, iclass 15, count 0 2006.285.19:26:03.54#ibcon#end of sib2, iclass 15, count 0 2006.285.19:26:03.54#ibcon#*after write, iclass 15, count 0 2006.285.19:26:03.54#ibcon#*before return 0, iclass 15, count 0 2006.285.19:26:03.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:26:03.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:26:03.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:26:03.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:26:03.54$vck44/va=8,3 2006.285.19:26:03.54#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.19:26:03.54#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.19:26:03.54#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:03.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:26:03.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:26:03.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:26:03.60#ibcon#enter wrdev, iclass 17, count 2 2006.285.19:26:03.60#ibcon#first serial, iclass 17, count 2 2006.285.19:26:03.60#ibcon#enter sib2, iclass 17, count 2 2006.285.19:26:03.60#ibcon#flushed, iclass 17, count 2 2006.285.19:26:03.60#ibcon#about to write, iclass 17, count 2 2006.285.19:26:03.60#ibcon#wrote, iclass 17, count 2 2006.285.19:26:03.60#ibcon#about to read 3, iclass 17, count 2 2006.285.19:26:03.62#ibcon#read 3, iclass 17, count 2 2006.285.19:26:03.62#ibcon#about to read 4, iclass 17, count 2 2006.285.19:26:03.62#ibcon#read 4, iclass 17, count 2 2006.285.19:26:03.62#ibcon#about to read 5, iclass 17, count 2 2006.285.19:26:03.62#ibcon#read 5, iclass 17, count 2 2006.285.19:26:03.62#ibcon#about to read 6, iclass 17, count 2 2006.285.19:26:03.62#ibcon#read 6, iclass 17, count 2 2006.285.19:26:03.62#ibcon#end of sib2, iclass 17, count 2 2006.285.19:26:03.62#ibcon#*mode == 0, iclass 17, count 2 2006.285.19:26:03.62#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.19:26:03.62#ibcon#[25=AT08-03\r\n] 2006.285.19:26:03.62#ibcon#*before write, iclass 17, count 2 2006.285.19:26:03.62#ibcon#enter sib2, iclass 17, count 2 2006.285.19:26:03.62#ibcon#flushed, iclass 17, count 2 2006.285.19:26:03.62#ibcon#about to write, iclass 17, count 2 2006.285.19:26:03.62#ibcon#wrote, iclass 17, count 2 2006.285.19:26:03.62#ibcon#about to read 3, iclass 17, count 2 2006.285.19:26:03.65#ibcon#read 3, iclass 17, count 2 2006.285.19:26:03.65#ibcon#about to read 4, iclass 17, count 2 2006.285.19:26:03.65#ibcon#read 4, iclass 17, count 2 2006.285.19:26:03.65#ibcon#about to read 5, iclass 17, count 2 2006.285.19:26:03.65#ibcon#read 5, iclass 17, count 2 2006.285.19:26:03.65#ibcon#about to read 6, iclass 17, count 2 2006.285.19:26:03.65#ibcon#read 6, iclass 17, count 2 2006.285.19:26:03.65#ibcon#end of sib2, iclass 17, count 2 2006.285.19:26:03.65#ibcon#*after write, iclass 17, count 2 2006.285.19:26:03.65#ibcon#*before return 0, iclass 17, count 2 2006.285.19:26:03.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:26:03.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:26:03.65#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.19:26:03.65#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:03.65#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:26:03.77#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:26:03.77#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:26:03.77#ibcon#enter wrdev, iclass 17, count 0 2006.285.19:26:03.77#ibcon#first serial, iclass 17, count 0 2006.285.19:26:03.77#ibcon#enter sib2, iclass 17, count 0 2006.285.19:26:03.77#ibcon#flushed, iclass 17, count 0 2006.285.19:26:03.77#ibcon#about to write, iclass 17, count 0 2006.285.19:26:03.77#ibcon#wrote, iclass 17, count 0 2006.285.19:26:03.77#ibcon#about to read 3, iclass 17, count 0 2006.285.19:26:03.79#ibcon#read 3, iclass 17, count 0 2006.285.19:26:03.79#ibcon#about to read 4, iclass 17, count 0 2006.285.19:26:03.79#ibcon#read 4, iclass 17, count 0 2006.285.19:26:03.79#ibcon#about to read 5, iclass 17, count 0 2006.285.19:26:03.79#ibcon#read 5, iclass 17, count 0 2006.285.19:26:03.79#ibcon#about to read 6, iclass 17, count 0 2006.285.19:26:03.79#ibcon#read 6, iclass 17, count 0 2006.285.19:26:03.79#ibcon#end of sib2, iclass 17, count 0 2006.285.19:26:03.79#ibcon#*mode == 0, iclass 17, count 0 2006.285.19:26:03.79#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.19:26:03.79#ibcon#[25=USB\r\n] 2006.285.19:26:03.79#ibcon#*before write, iclass 17, count 0 2006.285.19:26:03.79#ibcon#enter sib2, iclass 17, count 0 2006.285.19:26:03.79#ibcon#flushed, iclass 17, count 0 2006.285.19:26:03.79#ibcon#about to write, iclass 17, count 0 2006.285.19:26:03.79#ibcon#wrote, iclass 17, count 0 2006.285.19:26:03.79#ibcon#about to read 3, iclass 17, count 0 2006.285.19:26:03.82#ibcon#read 3, iclass 17, count 0 2006.285.19:26:03.82#ibcon#about to read 4, iclass 17, count 0 2006.285.19:26:03.82#ibcon#read 4, iclass 17, count 0 2006.285.19:26:03.82#ibcon#about to read 5, iclass 17, count 0 2006.285.19:26:03.82#ibcon#read 5, iclass 17, count 0 2006.285.19:26:03.82#ibcon#about to read 6, iclass 17, count 0 2006.285.19:26:03.82#ibcon#read 6, iclass 17, count 0 2006.285.19:26:03.82#ibcon#end of sib2, iclass 17, count 0 2006.285.19:26:03.82#ibcon#*after write, iclass 17, count 0 2006.285.19:26:03.82#ibcon#*before return 0, iclass 17, count 0 2006.285.19:26:03.82#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:26:03.82#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:26:03.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.19:26:03.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.19:26:03.82$vck44/vblo=1,629.99 2006.285.19:26:03.82#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.19:26:03.82#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.19:26:03.82#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:03.82#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:26:03.82#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:26:03.82#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:26:03.82#ibcon#enter wrdev, iclass 19, count 0 2006.285.19:26:03.82#ibcon#first serial, iclass 19, count 0 2006.285.19:26:03.82#ibcon#enter sib2, iclass 19, count 0 2006.285.19:26:03.82#ibcon#flushed, iclass 19, count 0 2006.285.19:26:03.82#ibcon#about to write, iclass 19, count 0 2006.285.19:26:03.82#ibcon#wrote, iclass 19, count 0 2006.285.19:26:03.82#ibcon#about to read 3, iclass 19, count 0 2006.285.19:26:03.84#ibcon#read 3, iclass 19, count 0 2006.285.19:26:03.84#ibcon#about to read 4, iclass 19, count 0 2006.285.19:26:03.84#ibcon#read 4, iclass 19, count 0 2006.285.19:26:03.84#ibcon#about to read 5, iclass 19, count 0 2006.285.19:26:03.84#ibcon#read 5, iclass 19, count 0 2006.285.19:26:03.84#ibcon#about to read 6, iclass 19, count 0 2006.285.19:26:03.84#ibcon#read 6, iclass 19, count 0 2006.285.19:26:03.84#ibcon#end of sib2, iclass 19, count 0 2006.285.19:26:03.84#ibcon#*mode == 0, iclass 19, count 0 2006.285.19:26:03.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.19:26:03.84#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.19:26:03.84#ibcon#*before write, iclass 19, count 0 2006.285.19:26:03.84#ibcon#enter sib2, iclass 19, count 0 2006.285.19:26:03.84#ibcon#flushed, iclass 19, count 0 2006.285.19:26:03.84#ibcon#about to write, iclass 19, count 0 2006.285.19:26:03.84#ibcon#wrote, iclass 19, count 0 2006.285.19:26:03.84#ibcon#about to read 3, iclass 19, count 0 2006.285.19:26:03.88#ibcon#read 3, iclass 19, count 0 2006.285.19:26:03.88#ibcon#about to read 4, iclass 19, count 0 2006.285.19:26:03.88#ibcon#read 4, iclass 19, count 0 2006.285.19:26:03.88#ibcon#about to read 5, iclass 19, count 0 2006.285.19:26:03.88#ibcon#read 5, iclass 19, count 0 2006.285.19:26:03.88#ibcon#about to read 6, iclass 19, count 0 2006.285.19:26:03.88#ibcon#read 6, iclass 19, count 0 2006.285.19:26:03.88#ibcon#end of sib2, iclass 19, count 0 2006.285.19:26:03.88#ibcon#*after write, iclass 19, count 0 2006.285.19:26:03.88#ibcon#*before return 0, iclass 19, count 0 2006.285.19:26:03.88#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:26:03.88#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:26:03.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.19:26:03.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.19:26:03.88$vck44/vb=1,4 2006.285.19:26:03.88#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.19:26:03.88#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.19:26:03.88#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:03.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:26:03.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:26:03.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:26:03.88#ibcon#enter wrdev, iclass 21, count 2 2006.285.19:26:03.88#ibcon#first serial, iclass 21, count 2 2006.285.19:26:03.88#ibcon#enter sib2, iclass 21, count 2 2006.285.19:26:03.88#ibcon#flushed, iclass 21, count 2 2006.285.19:26:03.88#ibcon#about to write, iclass 21, count 2 2006.285.19:26:03.88#ibcon#wrote, iclass 21, count 2 2006.285.19:26:03.88#ibcon#about to read 3, iclass 21, count 2 2006.285.19:26:03.90#ibcon#read 3, iclass 21, count 2 2006.285.19:26:03.90#ibcon#about to read 4, iclass 21, count 2 2006.285.19:26:03.90#ibcon#read 4, iclass 21, count 2 2006.285.19:26:04.05#ibcon#about to read 5, iclass 21, count 2 2006.285.19:26:04.05#ibcon#read 5, iclass 21, count 2 2006.285.19:26:04.05#ibcon#about to read 6, iclass 21, count 2 2006.285.19:26:04.05#ibcon#read 6, iclass 21, count 2 2006.285.19:26:04.05#ibcon#end of sib2, iclass 21, count 2 2006.285.19:26:04.05#ibcon#*mode == 0, iclass 21, count 2 2006.285.19:26:04.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.19:26:04.05#ibcon#[27=AT01-04\r\n] 2006.285.19:26:04.05#ibcon#*before write, iclass 21, count 2 2006.285.19:26:04.05#ibcon#enter sib2, iclass 21, count 2 2006.285.19:26:04.05#ibcon#flushed, iclass 21, count 2 2006.285.19:26:04.05#ibcon#about to write, iclass 21, count 2 2006.285.19:26:04.05#ibcon#wrote, iclass 21, count 2 2006.285.19:26:04.05#ibcon#about to read 3, iclass 21, count 2 2006.285.19:26:04.08#ibcon#read 3, iclass 21, count 2 2006.285.19:26:04.08#ibcon#about to read 4, iclass 21, count 2 2006.285.19:26:04.08#ibcon#read 4, iclass 21, count 2 2006.285.19:26:04.08#ibcon#about to read 5, iclass 21, count 2 2006.285.19:26:04.08#ibcon#read 5, iclass 21, count 2 2006.285.19:26:04.08#ibcon#about to read 6, iclass 21, count 2 2006.285.19:26:04.08#ibcon#read 6, iclass 21, count 2 2006.285.19:26:04.08#ibcon#end of sib2, iclass 21, count 2 2006.285.19:26:04.08#ibcon#*after write, iclass 21, count 2 2006.285.19:26:04.08#ibcon#*before return 0, iclass 21, count 2 2006.285.19:26:04.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:26:04.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:26:04.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.19:26:04.08#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:04.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:26:04.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:26:04.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:26:04.20#ibcon#enter wrdev, iclass 21, count 0 2006.285.19:26:04.20#ibcon#first serial, iclass 21, count 0 2006.285.19:26:04.20#ibcon#enter sib2, iclass 21, count 0 2006.285.19:26:04.20#ibcon#flushed, iclass 21, count 0 2006.285.19:26:04.20#ibcon#about to write, iclass 21, count 0 2006.285.19:26:04.20#ibcon#wrote, iclass 21, count 0 2006.285.19:26:04.20#ibcon#about to read 3, iclass 21, count 0 2006.285.19:26:04.22#ibcon#read 3, iclass 21, count 0 2006.285.19:26:04.22#ibcon#about to read 4, iclass 21, count 0 2006.285.19:26:04.22#ibcon#read 4, iclass 21, count 0 2006.285.19:26:04.22#ibcon#about to read 5, iclass 21, count 0 2006.285.19:26:04.22#ibcon#read 5, iclass 21, count 0 2006.285.19:26:04.22#ibcon#about to read 6, iclass 21, count 0 2006.285.19:26:04.22#ibcon#read 6, iclass 21, count 0 2006.285.19:26:04.22#ibcon#end of sib2, iclass 21, count 0 2006.285.19:26:04.22#ibcon#*mode == 0, iclass 21, count 0 2006.285.19:26:04.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.19:26:04.22#ibcon#[27=USB\r\n] 2006.285.19:26:04.22#ibcon#*before write, iclass 21, count 0 2006.285.19:26:04.22#ibcon#enter sib2, iclass 21, count 0 2006.285.19:26:04.22#ibcon#flushed, iclass 21, count 0 2006.285.19:26:04.22#ibcon#about to write, iclass 21, count 0 2006.285.19:26:04.22#ibcon#wrote, iclass 21, count 0 2006.285.19:26:04.22#ibcon#about to read 3, iclass 21, count 0 2006.285.19:26:04.25#ibcon#read 3, iclass 21, count 0 2006.285.19:26:04.25#ibcon#about to read 4, iclass 21, count 0 2006.285.19:26:04.25#ibcon#read 4, iclass 21, count 0 2006.285.19:26:04.25#ibcon#about to read 5, iclass 21, count 0 2006.285.19:26:04.25#ibcon#read 5, iclass 21, count 0 2006.285.19:26:04.25#ibcon#about to read 6, iclass 21, count 0 2006.285.19:26:04.25#ibcon#read 6, iclass 21, count 0 2006.285.19:26:04.25#ibcon#end of sib2, iclass 21, count 0 2006.285.19:26:04.25#ibcon#*after write, iclass 21, count 0 2006.285.19:26:04.25#ibcon#*before return 0, iclass 21, count 0 2006.285.19:26:04.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:26:04.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:26:04.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.19:26:04.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.19:26:04.25$vck44/vblo=2,634.99 2006.285.19:26:04.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.19:26:04.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.19:26:04.25#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:04.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:26:04.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:26:04.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:26:04.25#ibcon#enter wrdev, iclass 23, count 0 2006.285.19:26:04.25#ibcon#first serial, iclass 23, count 0 2006.285.19:26:04.25#ibcon#enter sib2, iclass 23, count 0 2006.285.19:26:04.25#ibcon#flushed, iclass 23, count 0 2006.285.19:26:04.25#ibcon#about to write, iclass 23, count 0 2006.285.19:26:04.25#ibcon#wrote, iclass 23, count 0 2006.285.19:26:04.25#ibcon#about to read 3, iclass 23, count 0 2006.285.19:26:04.27#ibcon#read 3, iclass 23, count 0 2006.285.19:26:04.27#ibcon#about to read 4, iclass 23, count 0 2006.285.19:26:04.27#ibcon#read 4, iclass 23, count 0 2006.285.19:26:04.27#ibcon#about to read 5, iclass 23, count 0 2006.285.19:26:04.27#ibcon#read 5, iclass 23, count 0 2006.285.19:26:04.27#ibcon#about to read 6, iclass 23, count 0 2006.285.19:26:04.27#ibcon#read 6, iclass 23, count 0 2006.285.19:26:04.27#ibcon#end of sib2, iclass 23, count 0 2006.285.19:26:04.27#ibcon#*mode == 0, iclass 23, count 0 2006.285.19:26:04.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.19:26:04.27#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.19:26:04.27#ibcon#*before write, iclass 23, count 0 2006.285.19:26:04.27#ibcon#enter sib2, iclass 23, count 0 2006.285.19:26:04.27#ibcon#flushed, iclass 23, count 0 2006.285.19:26:04.27#ibcon#about to write, iclass 23, count 0 2006.285.19:26:04.27#ibcon#wrote, iclass 23, count 0 2006.285.19:26:04.27#ibcon#about to read 3, iclass 23, count 0 2006.285.19:26:04.31#ibcon#read 3, iclass 23, count 0 2006.285.19:26:04.31#ibcon#about to read 4, iclass 23, count 0 2006.285.19:26:04.31#ibcon#read 4, iclass 23, count 0 2006.285.19:26:04.31#ibcon#about to read 5, iclass 23, count 0 2006.285.19:26:04.31#ibcon#read 5, iclass 23, count 0 2006.285.19:26:04.31#ibcon#about to read 6, iclass 23, count 0 2006.285.19:26:04.31#ibcon#read 6, iclass 23, count 0 2006.285.19:26:04.31#ibcon#end of sib2, iclass 23, count 0 2006.285.19:26:04.31#ibcon#*after write, iclass 23, count 0 2006.285.19:26:04.31#ibcon#*before return 0, iclass 23, count 0 2006.285.19:26:04.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:26:04.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:26:04.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.19:26:04.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.19:26:04.31$vck44/vb=2,5 2006.285.19:26:04.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.19:26:04.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.19:26:04.31#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:04.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:26:04.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:26:04.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:26:04.37#ibcon#enter wrdev, iclass 25, count 2 2006.285.19:26:04.37#ibcon#first serial, iclass 25, count 2 2006.285.19:26:04.37#ibcon#enter sib2, iclass 25, count 2 2006.285.19:26:04.37#ibcon#flushed, iclass 25, count 2 2006.285.19:26:04.37#ibcon#about to write, iclass 25, count 2 2006.285.19:26:04.37#ibcon#wrote, iclass 25, count 2 2006.285.19:26:04.37#ibcon#about to read 3, iclass 25, count 2 2006.285.19:26:04.39#ibcon#read 3, iclass 25, count 2 2006.285.19:26:04.39#ibcon#about to read 4, iclass 25, count 2 2006.285.19:26:04.39#ibcon#read 4, iclass 25, count 2 2006.285.19:26:04.39#ibcon#about to read 5, iclass 25, count 2 2006.285.19:26:04.39#ibcon#read 5, iclass 25, count 2 2006.285.19:26:04.39#ibcon#about to read 6, iclass 25, count 2 2006.285.19:26:04.39#ibcon#read 6, iclass 25, count 2 2006.285.19:26:04.39#ibcon#end of sib2, iclass 25, count 2 2006.285.19:26:04.39#ibcon#*mode == 0, iclass 25, count 2 2006.285.19:26:04.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.19:26:04.39#ibcon#[27=AT02-05\r\n] 2006.285.19:26:04.39#ibcon#*before write, iclass 25, count 2 2006.285.19:26:04.39#ibcon#enter sib2, iclass 25, count 2 2006.285.19:26:04.39#ibcon#flushed, iclass 25, count 2 2006.285.19:26:04.39#ibcon#about to write, iclass 25, count 2 2006.285.19:26:04.39#ibcon#wrote, iclass 25, count 2 2006.285.19:26:04.39#ibcon#about to read 3, iclass 25, count 2 2006.285.19:26:04.42#ibcon#read 3, iclass 25, count 2 2006.285.19:26:04.42#ibcon#about to read 4, iclass 25, count 2 2006.285.19:26:04.42#ibcon#read 4, iclass 25, count 2 2006.285.19:26:04.42#ibcon#about to read 5, iclass 25, count 2 2006.285.19:26:04.42#ibcon#read 5, iclass 25, count 2 2006.285.19:26:04.42#ibcon#about to read 6, iclass 25, count 2 2006.285.19:26:04.42#ibcon#read 6, iclass 25, count 2 2006.285.19:26:04.42#ibcon#end of sib2, iclass 25, count 2 2006.285.19:26:04.42#ibcon#*after write, iclass 25, count 2 2006.285.19:26:04.42#ibcon#*before return 0, iclass 25, count 2 2006.285.19:26:04.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:26:04.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:26:04.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.19:26:04.42#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:04.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:26:04.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:26:04.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:26:04.54#ibcon#enter wrdev, iclass 25, count 0 2006.285.19:26:04.54#ibcon#first serial, iclass 25, count 0 2006.285.19:26:04.54#ibcon#enter sib2, iclass 25, count 0 2006.285.19:26:04.54#ibcon#flushed, iclass 25, count 0 2006.285.19:26:04.54#ibcon#about to write, iclass 25, count 0 2006.285.19:26:04.54#ibcon#wrote, iclass 25, count 0 2006.285.19:26:04.54#ibcon#about to read 3, iclass 25, count 0 2006.285.19:26:04.56#ibcon#read 3, iclass 25, count 0 2006.285.19:26:04.56#ibcon#about to read 4, iclass 25, count 0 2006.285.19:26:04.56#ibcon#read 4, iclass 25, count 0 2006.285.19:26:04.56#ibcon#about to read 5, iclass 25, count 0 2006.285.19:26:04.56#ibcon#read 5, iclass 25, count 0 2006.285.19:26:04.56#ibcon#about to read 6, iclass 25, count 0 2006.285.19:26:04.56#ibcon#read 6, iclass 25, count 0 2006.285.19:26:04.56#ibcon#end of sib2, iclass 25, count 0 2006.285.19:26:04.56#ibcon#*mode == 0, iclass 25, count 0 2006.285.19:26:04.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.19:26:04.56#ibcon#[27=USB\r\n] 2006.285.19:26:04.56#ibcon#*before write, iclass 25, count 0 2006.285.19:26:04.56#ibcon#enter sib2, iclass 25, count 0 2006.285.19:26:04.56#ibcon#flushed, iclass 25, count 0 2006.285.19:26:04.56#ibcon#about to write, iclass 25, count 0 2006.285.19:26:04.56#ibcon#wrote, iclass 25, count 0 2006.285.19:26:04.56#ibcon#about to read 3, iclass 25, count 0 2006.285.19:26:04.59#ibcon#read 3, iclass 25, count 0 2006.285.19:26:04.59#ibcon#about to read 4, iclass 25, count 0 2006.285.19:26:04.59#ibcon#read 4, iclass 25, count 0 2006.285.19:26:04.59#ibcon#about to read 5, iclass 25, count 0 2006.285.19:26:04.59#ibcon#read 5, iclass 25, count 0 2006.285.19:26:04.59#ibcon#about to read 6, iclass 25, count 0 2006.285.19:26:04.59#ibcon#read 6, iclass 25, count 0 2006.285.19:26:04.59#ibcon#end of sib2, iclass 25, count 0 2006.285.19:26:04.59#ibcon#*after write, iclass 25, count 0 2006.285.19:26:04.59#ibcon#*before return 0, iclass 25, count 0 2006.285.19:26:04.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:26:04.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:26:04.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.19:26:04.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.19:26:04.59$vck44/vblo=3,649.99 2006.285.19:26:04.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.19:26:04.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.19:26:04.59#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:04.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:26:04.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:26:04.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:26:04.59#ibcon#enter wrdev, iclass 27, count 0 2006.285.19:26:04.59#ibcon#first serial, iclass 27, count 0 2006.285.19:26:04.59#ibcon#enter sib2, iclass 27, count 0 2006.285.19:26:04.59#ibcon#flushed, iclass 27, count 0 2006.285.19:26:04.59#ibcon#about to write, iclass 27, count 0 2006.285.19:26:04.59#ibcon#wrote, iclass 27, count 0 2006.285.19:26:04.59#ibcon#about to read 3, iclass 27, count 0 2006.285.19:26:04.61#ibcon#read 3, iclass 27, count 0 2006.285.19:26:04.61#ibcon#about to read 4, iclass 27, count 0 2006.285.19:26:04.61#ibcon#read 4, iclass 27, count 0 2006.285.19:26:04.61#ibcon#about to read 5, iclass 27, count 0 2006.285.19:26:04.61#ibcon#read 5, iclass 27, count 0 2006.285.19:26:04.61#ibcon#about to read 6, iclass 27, count 0 2006.285.19:26:04.61#ibcon#read 6, iclass 27, count 0 2006.285.19:26:04.61#ibcon#end of sib2, iclass 27, count 0 2006.285.19:26:04.61#ibcon#*mode == 0, iclass 27, count 0 2006.285.19:26:04.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.19:26:04.61#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.19:26:04.61#ibcon#*before write, iclass 27, count 0 2006.285.19:26:04.61#ibcon#enter sib2, iclass 27, count 0 2006.285.19:26:04.61#ibcon#flushed, iclass 27, count 0 2006.285.19:26:04.61#ibcon#about to write, iclass 27, count 0 2006.285.19:26:04.61#ibcon#wrote, iclass 27, count 0 2006.285.19:26:04.61#ibcon#about to read 3, iclass 27, count 0 2006.285.19:26:04.65#ibcon#read 3, iclass 27, count 0 2006.285.19:26:04.65#ibcon#about to read 4, iclass 27, count 0 2006.285.19:26:04.65#ibcon#read 4, iclass 27, count 0 2006.285.19:26:04.65#ibcon#about to read 5, iclass 27, count 0 2006.285.19:26:04.65#ibcon#read 5, iclass 27, count 0 2006.285.19:26:04.65#ibcon#about to read 6, iclass 27, count 0 2006.285.19:26:04.65#ibcon#read 6, iclass 27, count 0 2006.285.19:26:04.65#ibcon#end of sib2, iclass 27, count 0 2006.285.19:26:04.65#ibcon#*after write, iclass 27, count 0 2006.285.19:26:04.65#ibcon#*before return 0, iclass 27, count 0 2006.285.19:26:04.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:26:04.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:26:04.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.19:26:04.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.19:26:04.65$vck44/vb=3,4 2006.285.19:26:04.65#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.19:26:04.65#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.19:26:04.65#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:04.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:26:04.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:26:04.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:26:04.71#ibcon#enter wrdev, iclass 29, count 2 2006.285.19:26:04.71#ibcon#first serial, iclass 29, count 2 2006.285.19:26:04.71#ibcon#enter sib2, iclass 29, count 2 2006.285.19:26:04.71#ibcon#flushed, iclass 29, count 2 2006.285.19:26:04.71#ibcon#about to write, iclass 29, count 2 2006.285.19:26:04.71#ibcon#wrote, iclass 29, count 2 2006.285.19:26:04.71#ibcon#about to read 3, iclass 29, count 2 2006.285.19:26:04.73#ibcon#read 3, iclass 29, count 2 2006.285.19:26:04.73#ibcon#about to read 4, iclass 29, count 2 2006.285.19:26:04.73#ibcon#read 4, iclass 29, count 2 2006.285.19:26:04.73#ibcon#about to read 5, iclass 29, count 2 2006.285.19:26:04.73#ibcon#read 5, iclass 29, count 2 2006.285.19:26:04.73#ibcon#about to read 6, iclass 29, count 2 2006.285.19:26:04.73#ibcon#read 6, iclass 29, count 2 2006.285.19:26:04.73#ibcon#end of sib2, iclass 29, count 2 2006.285.19:26:04.73#ibcon#*mode == 0, iclass 29, count 2 2006.285.19:26:04.73#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.19:26:04.73#ibcon#[27=AT03-04\r\n] 2006.285.19:26:04.73#ibcon#*before write, iclass 29, count 2 2006.285.19:26:04.73#ibcon#enter sib2, iclass 29, count 2 2006.285.19:26:04.73#ibcon#flushed, iclass 29, count 2 2006.285.19:26:04.73#ibcon#about to write, iclass 29, count 2 2006.285.19:26:04.73#ibcon#wrote, iclass 29, count 2 2006.285.19:26:04.73#ibcon#about to read 3, iclass 29, count 2 2006.285.19:26:04.76#ibcon#read 3, iclass 29, count 2 2006.285.19:26:04.76#ibcon#about to read 4, iclass 29, count 2 2006.285.19:26:04.76#ibcon#read 4, iclass 29, count 2 2006.285.19:26:04.76#ibcon#about to read 5, iclass 29, count 2 2006.285.19:26:04.76#ibcon#read 5, iclass 29, count 2 2006.285.19:26:04.76#ibcon#about to read 6, iclass 29, count 2 2006.285.19:26:04.76#ibcon#read 6, iclass 29, count 2 2006.285.19:26:04.76#ibcon#end of sib2, iclass 29, count 2 2006.285.19:26:04.76#ibcon#*after write, iclass 29, count 2 2006.285.19:26:04.76#ibcon#*before return 0, iclass 29, count 2 2006.285.19:26:04.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:26:04.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:26:04.76#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.19:26:04.76#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:04.76#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:26:04.88#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:26:04.88#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:26:04.88#ibcon#enter wrdev, iclass 29, count 0 2006.285.19:26:04.88#ibcon#first serial, iclass 29, count 0 2006.285.19:26:04.88#ibcon#enter sib2, iclass 29, count 0 2006.285.19:26:04.88#ibcon#flushed, iclass 29, count 0 2006.285.19:26:04.88#ibcon#about to write, iclass 29, count 0 2006.285.19:26:04.88#ibcon#wrote, iclass 29, count 0 2006.285.19:26:04.88#ibcon#about to read 3, iclass 29, count 0 2006.285.19:26:04.90#ibcon#read 3, iclass 29, count 0 2006.285.19:26:04.90#ibcon#about to read 4, iclass 29, count 0 2006.285.19:26:04.90#ibcon#read 4, iclass 29, count 0 2006.285.19:26:04.90#ibcon#about to read 5, iclass 29, count 0 2006.285.19:26:04.90#ibcon#read 5, iclass 29, count 0 2006.285.19:26:04.90#ibcon#about to read 6, iclass 29, count 0 2006.285.19:26:04.90#ibcon#read 6, iclass 29, count 0 2006.285.19:26:04.90#ibcon#end of sib2, iclass 29, count 0 2006.285.19:26:04.90#ibcon#*mode == 0, iclass 29, count 0 2006.285.19:26:04.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.19:26:04.90#ibcon#[27=USB\r\n] 2006.285.19:26:04.90#ibcon#*before write, iclass 29, count 0 2006.285.19:26:04.90#ibcon#enter sib2, iclass 29, count 0 2006.285.19:26:04.90#ibcon#flushed, iclass 29, count 0 2006.285.19:26:04.90#ibcon#about to write, iclass 29, count 0 2006.285.19:26:04.90#ibcon#wrote, iclass 29, count 0 2006.285.19:26:04.90#ibcon#about to read 3, iclass 29, count 0 2006.285.19:26:04.93#ibcon#read 3, iclass 29, count 0 2006.285.19:26:04.93#ibcon#about to read 4, iclass 29, count 0 2006.285.19:26:04.93#ibcon#read 4, iclass 29, count 0 2006.285.19:26:04.93#ibcon#about to read 5, iclass 29, count 0 2006.285.19:26:04.93#ibcon#read 5, iclass 29, count 0 2006.285.19:26:04.93#ibcon#about to read 6, iclass 29, count 0 2006.285.19:26:04.93#ibcon#read 6, iclass 29, count 0 2006.285.19:26:04.93#ibcon#end of sib2, iclass 29, count 0 2006.285.19:26:04.93#ibcon#*after write, iclass 29, count 0 2006.285.19:26:04.93#ibcon#*before return 0, iclass 29, count 0 2006.285.19:26:04.93#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:26:04.93#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:26:04.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.19:26:04.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.19:26:04.93$vck44/vblo=4,679.99 2006.285.19:26:04.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.19:26:04.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.19:26:04.93#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:04.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:26:04.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:26:04.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:26:04.93#ibcon#enter wrdev, iclass 31, count 0 2006.285.19:26:04.93#ibcon#first serial, iclass 31, count 0 2006.285.19:26:04.93#ibcon#enter sib2, iclass 31, count 0 2006.285.19:26:04.93#ibcon#flushed, iclass 31, count 0 2006.285.19:26:04.93#ibcon#about to write, iclass 31, count 0 2006.285.19:26:04.93#ibcon#wrote, iclass 31, count 0 2006.285.19:26:04.93#ibcon#about to read 3, iclass 31, count 0 2006.285.19:26:05.04#ibcon#read 3, iclass 31, count 0 2006.285.19:26:05.04#ibcon#about to read 4, iclass 31, count 0 2006.285.19:26:05.04#ibcon#read 4, iclass 31, count 0 2006.285.19:26:05.04#ibcon#about to read 5, iclass 31, count 0 2006.285.19:26:05.04#ibcon#read 5, iclass 31, count 0 2006.285.19:26:05.04#ibcon#about to read 6, iclass 31, count 0 2006.285.19:26:05.04#ibcon#read 6, iclass 31, count 0 2006.285.19:26:05.04#ibcon#end of sib2, iclass 31, count 0 2006.285.19:26:05.04#ibcon#*mode == 0, iclass 31, count 0 2006.285.19:26:05.04#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.19:26:05.04#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.19:26:05.04#ibcon#*before write, iclass 31, count 0 2006.285.19:26:05.04#ibcon#enter sib2, iclass 31, count 0 2006.285.19:26:05.04#ibcon#flushed, iclass 31, count 0 2006.285.19:26:05.04#ibcon#about to write, iclass 31, count 0 2006.285.19:26:05.04#ibcon#wrote, iclass 31, count 0 2006.285.19:26:05.04#ibcon#about to read 3, iclass 31, count 0 2006.285.19:26:05.08#ibcon#read 3, iclass 31, count 0 2006.285.19:26:05.08#ibcon#about to read 4, iclass 31, count 0 2006.285.19:26:05.08#ibcon#read 4, iclass 31, count 0 2006.285.19:26:05.08#ibcon#about to read 5, iclass 31, count 0 2006.285.19:26:05.08#ibcon#read 5, iclass 31, count 0 2006.285.19:26:05.08#ibcon#about to read 6, iclass 31, count 0 2006.285.19:26:05.08#ibcon#read 6, iclass 31, count 0 2006.285.19:26:05.08#ibcon#end of sib2, iclass 31, count 0 2006.285.19:26:05.08#ibcon#*after write, iclass 31, count 0 2006.285.19:26:05.08#ibcon#*before return 0, iclass 31, count 0 2006.285.19:26:05.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:26:05.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:26:05.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.19:26:05.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.19:26:05.08$vck44/vb=4,5 2006.285.19:26:05.08#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.19:26:05.08#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.19:26:05.08#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:05.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:26:05.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:26:05.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:26:05.08#ibcon#enter wrdev, iclass 33, count 2 2006.285.19:26:05.08#ibcon#first serial, iclass 33, count 2 2006.285.19:26:05.08#ibcon#enter sib2, iclass 33, count 2 2006.285.19:26:05.08#ibcon#flushed, iclass 33, count 2 2006.285.19:26:05.08#ibcon#about to write, iclass 33, count 2 2006.285.19:26:05.08#ibcon#wrote, iclass 33, count 2 2006.285.19:26:05.08#ibcon#about to read 3, iclass 33, count 2 2006.285.19:26:05.10#ibcon#read 3, iclass 33, count 2 2006.285.19:26:05.10#ibcon#about to read 4, iclass 33, count 2 2006.285.19:26:05.10#ibcon#read 4, iclass 33, count 2 2006.285.19:26:05.10#ibcon#about to read 5, iclass 33, count 2 2006.285.19:26:05.10#ibcon#read 5, iclass 33, count 2 2006.285.19:26:05.10#ibcon#about to read 6, iclass 33, count 2 2006.285.19:26:05.10#ibcon#read 6, iclass 33, count 2 2006.285.19:26:05.10#ibcon#end of sib2, iclass 33, count 2 2006.285.19:26:05.10#ibcon#*mode == 0, iclass 33, count 2 2006.285.19:26:05.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.19:26:05.10#ibcon#[27=AT04-05\r\n] 2006.285.19:26:05.10#ibcon#*before write, iclass 33, count 2 2006.285.19:26:05.10#ibcon#enter sib2, iclass 33, count 2 2006.285.19:26:05.10#ibcon#flushed, iclass 33, count 2 2006.285.19:26:05.10#ibcon#about to write, iclass 33, count 2 2006.285.19:26:05.10#ibcon#wrote, iclass 33, count 2 2006.285.19:26:05.10#ibcon#about to read 3, iclass 33, count 2 2006.285.19:26:05.13#ibcon#read 3, iclass 33, count 2 2006.285.19:26:05.13#ibcon#about to read 4, iclass 33, count 2 2006.285.19:26:05.13#ibcon#read 4, iclass 33, count 2 2006.285.19:26:05.13#ibcon#about to read 5, iclass 33, count 2 2006.285.19:26:05.13#ibcon#read 5, iclass 33, count 2 2006.285.19:26:05.13#ibcon#about to read 6, iclass 33, count 2 2006.285.19:26:05.13#ibcon#read 6, iclass 33, count 2 2006.285.19:26:05.13#ibcon#end of sib2, iclass 33, count 2 2006.285.19:26:05.13#ibcon#*after write, iclass 33, count 2 2006.285.19:26:05.13#ibcon#*before return 0, iclass 33, count 2 2006.285.19:26:05.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:26:05.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:26:05.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.19:26:05.13#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:05.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:26:05.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:26:05.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:26:05.25#ibcon#enter wrdev, iclass 33, count 0 2006.285.19:26:05.25#ibcon#first serial, iclass 33, count 0 2006.285.19:26:05.25#ibcon#enter sib2, iclass 33, count 0 2006.285.19:26:05.25#ibcon#flushed, iclass 33, count 0 2006.285.19:26:05.25#ibcon#about to write, iclass 33, count 0 2006.285.19:26:05.25#ibcon#wrote, iclass 33, count 0 2006.285.19:26:05.25#ibcon#about to read 3, iclass 33, count 0 2006.285.19:26:05.27#ibcon#read 3, iclass 33, count 0 2006.285.19:26:05.27#ibcon#about to read 4, iclass 33, count 0 2006.285.19:26:05.27#ibcon#read 4, iclass 33, count 0 2006.285.19:26:05.27#ibcon#about to read 5, iclass 33, count 0 2006.285.19:26:05.27#ibcon#read 5, iclass 33, count 0 2006.285.19:26:05.27#ibcon#about to read 6, iclass 33, count 0 2006.285.19:26:05.27#ibcon#read 6, iclass 33, count 0 2006.285.19:26:05.27#ibcon#end of sib2, iclass 33, count 0 2006.285.19:26:05.27#ibcon#*mode == 0, iclass 33, count 0 2006.285.19:26:05.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.19:26:05.27#ibcon#[27=USB\r\n] 2006.285.19:26:05.27#ibcon#*before write, iclass 33, count 0 2006.285.19:26:05.27#ibcon#enter sib2, iclass 33, count 0 2006.285.19:26:05.27#ibcon#flushed, iclass 33, count 0 2006.285.19:26:05.27#ibcon#about to write, iclass 33, count 0 2006.285.19:26:05.27#ibcon#wrote, iclass 33, count 0 2006.285.19:26:05.27#ibcon#about to read 3, iclass 33, count 0 2006.285.19:26:05.30#ibcon#read 3, iclass 33, count 0 2006.285.19:26:05.30#ibcon#about to read 4, iclass 33, count 0 2006.285.19:26:05.30#ibcon#read 4, iclass 33, count 0 2006.285.19:26:05.30#ibcon#about to read 5, iclass 33, count 0 2006.285.19:26:05.30#ibcon#read 5, iclass 33, count 0 2006.285.19:26:05.30#ibcon#about to read 6, iclass 33, count 0 2006.285.19:26:05.30#ibcon#read 6, iclass 33, count 0 2006.285.19:26:05.30#ibcon#end of sib2, iclass 33, count 0 2006.285.19:26:05.30#ibcon#*after write, iclass 33, count 0 2006.285.19:26:05.30#ibcon#*before return 0, iclass 33, count 0 2006.285.19:26:05.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:26:05.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:26:05.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.19:26:05.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.19:26:05.30$vck44/vblo=5,709.99 2006.285.19:26:05.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.19:26:05.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.19:26:05.30#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:05.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:26:05.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:26:05.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:26:05.30#ibcon#enter wrdev, iclass 35, count 0 2006.285.19:26:05.30#ibcon#first serial, iclass 35, count 0 2006.285.19:26:05.30#ibcon#enter sib2, iclass 35, count 0 2006.285.19:26:05.30#ibcon#flushed, iclass 35, count 0 2006.285.19:26:05.30#ibcon#about to write, iclass 35, count 0 2006.285.19:26:05.30#ibcon#wrote, iclass 35, count 0 2006.285.19:26:05.30#ibcon#about to read 3, iclass 35, count 0 2006.285.19:26:05.32#ibcon#read 3, iclass 35, count 0 2006.285.19:26:05.32#ibcon#about to read 4, iclass 35, count 0 2006.285.19:26:05.32#ibcon#read 4, iclass 35, count 0 2006.285.19:26:05.32#ibcon#about to read 5, iclass 35, count 0 2006.285.19:26:05.32#ibcon#read 5, iclass 35, count 0 2006.285.19:26:05.32#ibcon#about to read 6, iclass 35, count 0 2006.285.19:26:05.32#ibcon#read 6, iclass 35, count 0 2006.285.19:26:05.32#ibcon#end of sib2, iclass 35, count 0 2006.285.19:26:05.32#ibcon#*mode == 0, iclass 35, count 0 2006.285.19:26:05.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.19:26:05.32#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.19:26:05.32#ibcon#*before write, iclass 35, count 0 2006.285.19:26:05.32#ibcon#enter sib2, iclass 35, count 0 2006.285.19:26:05.32#ibcon#flushed, iclass 35, count 0 2006.285.19:26:05.32#ibcon#about to write, iclass 35, count 0 2006.285.19:26:05.32#ibcon#wrote, iclass 35, count 0 2006.285.19:26:05.32#ibcon#about to read 3, iclass 35, count 0 2006.285.19:26:05.36#ibcon#read 3, iclass 35, count 0 2006.285.19:26:05.36#ibcon#about to read 4, iclass 35, count 0 2006.285.19:26:05.36#ibcon#read 4, iclass 35, count 0 2006.285.19:26:05.36#ibcon#about to read 5, iclass 35, count 0 2006.285.19:26:05.36#ibcon#read 5, iclass 35, count 0 2006.285.19:26:05.36#ibcon#about to read 6, iclass 35, count 0 2006.285.19:26:05.36#ibcon#read 6, iclass 35, count 0 2006.285.19:26:05.36#ibcon#end of sib2, iclass 35, count 0 2006.285.19:26:05.36#ibcon#*after write, iclass 35, count 0 2006.285.19:26:05.36#ibcon#*before return 0, iclass 35, count 0 2006.285.19:26:05.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:26:05.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:26:05.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.19:26:05.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.19:26:05.36$vck44/vb=5,4 2006.285.19:26:05.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.19:26:05.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.19:26:05.36#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:05.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:26:05.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:26:05.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:26:05.42#ibcon#enter wrdev, iclass 37, count 2 2006.285.19:26:05.42#ibcon#first serial, iclass 37, count 2 2006.285.19:26:05.42#ibcon#enter sib2, iclass 37, count 2 2006.285.19:26:05.42#ibcon#flushed, iclass 37, count 2 2006.285.19:26:05.42#ibcon#about to write, iclass 37, count 2 2006.285.19:26:05.42#ibcon#wrote, iclass 37, count 2 2006.285.19:26:05.42#ibcon#about to read 3, iclass 37, count 2 2006.285.19:26:05.44#ibcon#read 3, iclass 37, count 2 2006.285.19:26:05.44#ibcon#about to read 4, iclass 37, count 2 2006.285.19:26:05.44#ibcon#read 4, iclass 37, count 2 2006.285.19:26:05.44#ibcon#about to read 5, iclass 37, count 2 2006.285.19:26:05.44#ibcon#read 5, iclass 37, count 2 2006.285.19:26:05.44#ibcon#about to read 6, iclass 37, count 2 2006.285.19:26:05.44#ibcon#read 6, iclass 37, count 2 2006.285.19:26:05.44#ibcon#end of sib2, iclass 37, count 2 2006.285.19:26:05.44#ibcon#*mode == 0, iclass 37, count 2 2006.285.19:26:05.44#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.19:26:05.44#ibcon#[27=AT05-04\r\n] 2006.285.19:26:05.44#ibcon#*before write, iclass 37, count 2 2006.285.19:26:05.44#ibcon#enter sib2, iclass 37, count 2 2006.285.19:26:05.44#ibcon#flushed, iclass 37, count 2 2006.285.19:26:05.44#ibcon#about to write, iclass 37, count 2 2006.285.19:26:05.44#ibcon#wrote, iclass 37, count 2 2006.285.19:26:05.44#ibcon#about to read 3, iclass 37, count 2 2006.285.19:26:05.47#ibcon#read 3, iclass 37, count 2 2006.285.19:26:05.47#ibcon#about to read 4, iclass 37, count 2 2006.285.19:26:05.47#ibcon#read 4, iclass 37, count 2 2006.285.19:26:05.47#ibcon#about to read 5, iclass 37, count 2 2006.285.19:26:05.47#ibcon#read 5, iclass 37, count 2 2006.285.19:26:05.47#ibcon#about to read 6, iclass 37, count 2 2006.285.19:26:05.47#ibcon#read 6, iclass 37, count 2 2006.285.19:26:05.47#ibcon#end of sib2, iclass 37, count 2 2006.285.19:26:05.47#ibcon#*after write, iclass 37, count 2 2006.285.19:26:05.47#ibcon#*before return 0, iclass 37, count 2 2006.285.19:26:05.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:26:05.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:26:05.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.19:26:05.47#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:05.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:26:05.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:26:05.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:26:05.59#ibcon#enter wrdev, iclass 37, count 0 2006.285.19:26:05.59#ibcon#first serial, iclass 37, count 0 2006.285.19:26:05.59#ibcon#enter sib2, iclass 37, count 0 2006.285.19:26:05.59#ibcon#flushed, iclass 37, count 0 2006.285.19:26:05.59#ibcon#about to write, iclass 37, count 0 2006.285.19:26:05.59#ibcon#wrote, iclass 37, count 0 2006.285.19:26:05.59#ibcon#about to read 3, iclass 37, count 0 2006.285.19:26:05.61#ibcon#read 3, iclass 37, count 0 2006.285.19:26:05.61#ibcon#about to read 4, iclass 37, count 0 2006.285.19:26:05.61#ibcon#read 4, iclass 37, count 0 2006.285.19:26:05.61#ibcon#about to read 5, iclass 37, count 0 2006.285.19:26:05.61#ibcon#read 5, iclass 37, count 0 2006.285.19:26:05.61#ibcon#about to read 6, iclass 37, count 0 2006.285.19:26:05.61#ibcon#read 6, iclass 37, count 0 2006.285.19:26:05.61#ibcon#end of sib2, iclass 37, count 0 2006.285.19:26:05.61#ibcon#*mode == 0, iclass 37, count 0 2006.285.19:26:05.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.19:26:05.61#ibcon#[27=USB\r\n] 2006.285.19:26:05.61#ibcon#*before write, iclass 37, count 0 2006.285.19:26:05.61#ibcon#enter sib2, iclass 37, count 0 2006.285.19:26:05.61#ibcon#flushed, iclass 37, count 0 2006.285.19:26:05.61#ibcon#about to write, iclass 37, count 0 2006.285.19:26:05.61#ibcon#wrote, iclass 37, count 0 2006.285.19:26:05.61#ibcon#about to read 3, iclass 37, count 0 2006.285.19:26:05.64#ibcon#read 3, iclass 37, count 0 2006.285.19:26:05.64#ibcon#about to read 4, iclass 37, count 0 2006.285.19:26:05.64#ibcon#read 4, iclass 37, count 0 2006.285.19:26:05.64#ibcon#about to read 5, iclass 37, count 0 2006.285.19:26:05.64#ibcon#read 5, iclass 37, count 0 2006.285.19:26:05.64#ibcon#about to read 6, iclass 37, count 0 2006.285.19:26:05.64#ibcon#read 6, iclass 37, count 0 2006.285.19:26:05.64#ibcon#end of sib2, iclass 37, count 0 2006.285.19:26:05.64#ibcon#*after write, iclass 37, count 0 2006.285.19:26:05.64#ibcon#*before return 0, iclass 37, count 0 2006.285.19:26:05.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:26:05.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:26:05.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.19:26:05.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.19:26:05.64$vck44/vblo=6,719.99 2006.285.19:26:05.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.19:26:05.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.19:26:05.64#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:05.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:26:05.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:26:05.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:26:05.64#ibcon#enter wrdev, iclass 39, count 0 2006.285.19:26:05.64#ibcon#first serial, iclass 39, count 0 2006.285.19:26:05.64#ibcon#enter sib2, iclass 39, count 0 2006.285.19:26:05.64#ibcon#flushed, iclass 39, count 0 2006.285.19:26:05.64#ibcon#about to write, iclass 39, count 0 2006.285.19:26:05.64#ibcon#wrote, iclass 39, count 0 2006.285.19:26:05.64#ibcon#about to read 3, iclass 39, count 0 2006.285.19:26:05.66#ibcon#read 3, iclass 39, count 0 2006.285.19:26:05.66#ibcon#about to read 4, iclass 39, count 0 2006.285.19:26:05.66#ibcon#read 4, iclass 39, count 0 2006.285.19:26:05.66#ibcon#about to read 5, iclass 39, count 0 2006.285.19:26:05.66#ibcon#read 5, iclass 39, count 0 2006.285.19:26:05.66#ibcon#about to read 6, iclass 39, count 0 2006.285.19:26:05.66#ibcon#read 6, iclass 39, count 0 2006.285.19:26:05.66#ibcon#end of sib2, iclass 39, count 0 2006.285.19:26:05.66#ibcon#*mode == 0, iclass 39, count 0 2006.285.19:26:05.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.19:26:05.66#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.19:26:05.66#ibcon#*before write, iclass 39, count 0 2006.285.19:26:05.66#ibcon#enter sib2, iclass 39, count 0 2006.285.19:26:05.66#ibcon#flushed, iclass 39, count 0 2006.285.19:26:05.66#ibcon#about to write, iclass 39, count 0 2006.285.19:26:05.66#ibcon#wrote, iclass 39, count 0 2006.285.19:26:05.66#ibcon#about to read 3, iclass 39, count 0 2006.285.19:26:05.70#ibcon#read 3, iclass 39, count 0 2006.285.19:26:05.70#ibcon#about to read 4, iclass 39, count 0 2006.285.19:26:05.70#ibcon#read 4, iclass 39, count 0 2006.285.19:26:05.70#ibcon#about to read 5, iclass 39, count 0 2006.285.19:26:05.70#ibcon#read 5, iclass 39, count 0 2006.285.19:26:05.70#ibcon#about to read 6, iclass 39, count 0 2006.285.19:26:05.70#ibcon#read 6, iclass 39, count 0 2006.285.19:26:05.70#ibcon#end of sib2, iclass 39, count 0 2006.285.19:26:05.70#ibcon#*after write, iclass 39, count 0 2006.285.19:26:05.70#ibcon#*before return 0, iclass 39, count 0 2006.285.19:26:05.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:26:05.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:26:05.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.19:26:05.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.19:26:05.70$vck44/vb=6,3 2006.285.19:26:05.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.19:26:05.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.19:26:05.70#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:05.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:26:05.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:26:05.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:26:05.76#ibcon#enter wrdev, iclass 3, count 2 2006.285.19:26:05.76#ibcon#first serial, iclass 3, count 2 2006.285.19:26:05.76#ibcon#enter sib2, iclass 3, count 2 2006.285.19:26:05.76#ibcon#flushed, iclass 3, count 2 2006.285.19:26:05.76#ibcon#about to write, iclass 3, count 2 2006.285.19:26:05.76#ibcon#wrote, iclass 3, count 2 2006.285.19:26:05.76#ibcon#about to read 3, iclass 3, count 2 2006.285.19:26:05.78#ibcon#read 3, iclass 3, count 2 2006.285.19:26:05.78#ibcon#about to read 4, iclass 3, count 2 2006.285.19:26:05.78#ibcon#read 4, iclass 3, count 2 2006.285.19:26:05.78#ibcon#about to read 5, iclass 3, count 2 2006.285.19:26:05.78#ibcon#read 5, iclass 3, count 2 2006.285.19:26:05.78#ibcon#about to read 6, iclass 3, count 2 2006.285.19:26:05.78#ibcon#read 6, iclass 3, count 2 2006.285.19:26:05.78#ibcon#end of sib2, iclass 3, count 2 2006.285.19:26:05.78#ibcon#*mode == 0, iclass 3, count 2 2006.285.19:26:05.78#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.19:26:05.78#ibcon#[27=AT06-03\r\n] 2006.285.19:26:05.78#ibcon#*before write, iclass 3, count 2 2006.285.19:26:05.78#ibcon#enter sib2, iclass 3, count 2 2006.285.19:26:05.78#ibcon#flushed, iclass 3, count 2 2006.285.19:26:05.78#ibcon#about to write, iclass 3, count 2 2006.285.19:26:05.78#ibcon#wrote, iclass 3, count 2 2006.285.19:26:05.78#ibcon#about to read 3, iclass 3, count 2 2006.285.19:26:05.81#ibcon#read 3, iclass 3, count 2 2006.285.19:26:05.81#ibcon#about to read 4, iclass 3, count 2 2006.285.19:26:05.81#ibcon#read 4, iclass 3, count 2 2006.285.19:26:05.81#ibcon#about to read 5, iclass 3, count 2 2006.285.19:26:05.81#ibcon#read 5, iclass 3, count 2 2006.285.19:26:05.81#ibcon#about to read 6, iclass 3, count 2 2006.285.19:26:05.81#ibcon#read 6, iclass 3, count 2 2006.285.19:26:05.81#ibcon#end of sib2, iclass 3, count 2 2006.285.19:26:05.81#ibcon#*after write, iclass 3, count 2 2006.285.19:26:05.81#ibcon#*before return 0, iclass 3, count 2 2006.285.19:26:05.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:26:05.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:26:05.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.19:26:05.81#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:05.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:26:05.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:26:05.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:26:05.93#ibcon#enter wrdev, iclass 3, count 0 2006.285.19:26:05.93#ibcon#first serial, iclass 3, count 0 2006.285.19:26:05.93#ibcon#enter sib2, iclass 3, count 0 2006.285.19:26:05.93#ibcon#flushed, iclass 3, count 0 2006.285.19:26:05.93#ibcon#about to write, iclass 3, count 0 2006.285.19:26:05.93#ibcon#wrote, iclass 3, count 0 2006.285.19:26:05.93#ibcon#about to read 3, iclass 3, count 0 2006.285.19:26:05.95#ibcon#read 3, iclass 3, count 0 2006.285.19:26:05.95#ibcon#about to read 4, iclass 3, count 0 2006.285.19:26:05.95#ibcon#read 4, iclass 3, count 0 2006.285.19:26:05.95#ibcon#about to read 5, iclass 3, count 0 2006.285.19:26:05.95#ibcon#read 5, iclass 3, count 0 2006.285.19:26:05.95#ibcon#about to read 6, iclass 3, count 0 2006.285.19:26:05.95#ibcon#read 6, iclass 3, count 0 2006.285.19:26:05.95#ibcon#end of sib2, iclass 3, count 0 2006.285.19:26:05.95#ibcon#*mode == 0, iclass 3, count 0 2006.285.19:26:05.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.19:26:05.95#ibcon#[27=USB\r\n] 2006.285.19:26:05.95#ibcon#*before write, iclass 3, count 0 2006.285.19:26:05.95#ibcon#enter sib2, iclass 3, count 0 2006.285.19:26:05.95#ibcon#flushed, iclass 3, count 0 2006.285.19:26:05.95#ibcon#about to write, iclass 3, count 0 2006.285.19:26:05.95#ibcon#wrote, iclass 3, count 0 2006.285.19:26:05.95#ibcon#about to read 3, iclass 3, count 0 2006.285.19:26:05.98#ibcon#read 3, iclass 3, count 0 2006.285.19:26:05.98#ibcon#about to read 4, iclass 3, count 0 2006.285.19:26:05.98#ibcon#read 4, iclass 3, count 0 2006.285.19:26:05.98#ibcon#about to read 5, iclass 3, count 0 2006.285.19:26:05.98#ibcon#read 5, iclass 3, count 0 2006.285.19:26:05.98#ibcon#about to read 6, iclass 3, count 0 2006.285.19:26:05.98#ibcon#read 6, iclass 3, count 0 2006.285.19:26:05.98#ibcon#end of sib2, iclass 3, count 0 2006.285.19:26:05.98#ibcon#*after write, iclass 3, count 0 2006.285.19:26:05.98#ibcon#*before return 0, iclass 3, count 0 2006.285.19:26:05.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:26:05.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:26:05.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.19:26:05.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.19:26:05.98$vck44/vblo=7,734.99 2006.285.19:26:05.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.19:26:05.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.19:26:05.98#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:05.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:26:05.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:26:05.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:26:05.98#ibcon#enter wrdev, iclass 5, count 0 2006.285.19:26:05.98#ibcon#first serial, iclass 5, count 0 2006.285.19:26:05.98#ibcon#enter sib2, iclass 5, count 0 2006.285.19:26:05.98#ibcon#flushed, iclass 5, count 0 2006.285.19:26:05.98#ibcon#about to write, iclass 5, count 0 2006.285.19:26:05.98#ibcon#wrote, iclass 5, count 0 2006.285.19:26:05.98#ibcon#about to read 3, iclass 5, count 0 2006.285.19:26:06.00#ibcon#read 3, iclass 5, count 0 2006.285.19:26:06.05#ibcon#about to read 4, iclass 5, count 0 2006.285.19:26:06.05#ibcon#read 4, iclass 5, count 0 2006.285.19:26:06.05#ibcon#about to read 5, iclass 5, count 0 2006.285.19:26:06.05#ibcon#read 5, iclass 5, count 0 2006.285.19:26:06.05#ibcon#about to read 6, iclass 5, count 0 2006.285.19:26:06.05#ibcon#read 6, iclass 5, count 0 2006.285.19:26:06.05#ibcon#end of sib2, iclass 5, count 0 2006.285.19:26:06.05#ibcon#*mode == 0, iclass 5, count 0 2006.285.19:26:06.05#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.19:26:06.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.19:26:06.05#ibcon#*before write, iclass 5, count 0 2006.285.19:26:06.05#ibcon#enter sib2, iclass 5, count 0 2006.285.19:26:06.05#ibcon#flushed, iclass 5, count 0 2006.285.19:26:06.05#ibcon#about to write, iclass 5, count 0 2006.285.19:26:06.05#ibcon#wrote, iclass 5, count 0 2006.285.19:26:06.05#ibcon#about to read 3, iclass 5, count 0 2006.285.19:26:06.10#ibcon#read 3, iclass 5, count 0 2006.285.19:26:06.10#ibcon#about to read 4, iclass 5, count 0 2006.285.19:26:06.10#ibcon#read 4, iclass 5, count 0 2006.285.19:26:06.10#ibcon#about to read 5, iclass 5, count 0 2006.285.19:26:06.10#ibcon#read 5, iclass 5, count 0 2006.285.19:26:06.10#ibcon#about to read 6, iclass 5, count 0 2006.285.19:26:06.10#ibcon#read 6, iclass 5, count 0 2006.285.19:26:06.10#ibcon#end of sib2, iclass 5, count 0 2006.285.19:26:06.10#ibcon#*after write, iclass 5, count 0 2006.285.19:26:06.10#ibcon#*before return 0, iclass 5, count 0 2006.285.19:26:06.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:26:06.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:26:06.10#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.19:26:06.10#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.19:26:06.10$vck44/vb=7,4 2006.285.19:26:06.10#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.19:26:06.10#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.19:26:06.10#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:06.10#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:26:06.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:26:06.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:26:06.10#ibcon#enter wrdev, iclass 7, count 2 2006.285.19:26:06.10#ibcon#first serial, iclass 7, count 2 2006.285.19:26:06.10#ibcon#enter sib2, iclass 7, count 2 2006.285.19:26:06.10#ibcon#flushed, iclass 7, count 2 2006.285.19:26:06.10#ibcon#about to write, iclass 7, count 2 2006.285.19:26:06.10#ibcon#wrote, iclass 7, count 2 2006.285.19:26:06.10#ibcon#about to read 3, iclass 7, count 2 2006.285.19:26:06.12#ibcon#read 3, iclass 7, count 2 2006.285.19:26:06.12#ibcon#about to read 4, iclass 7, count 2 2006.285.19:26:06.12#ibcon#read 4, iclass 7, count 2 2006.285.19:26:06.12#ibcon#about to read 5, iclass 7, count 2 2006.285.19:26:06.12#ibcon#read 5, iclass 7, count 2 2006.285.19:26:06.12#ibcon#about to read 6, iclass 7, count 2 2006.285.19:26:06.12#ibcon#read 6, iclass 7, count 2 2006.285.19:26:06.12#ibcon#end of sib2, iclass 7, count 2 2006.285.19:26:06.12#ibcon#*mode == 0, iclass 7, count 2 2006.285.19:26:06.12#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.19:26:06.12#ibcon#[27=AT07-04\r\n] 2006.285.19:26:06.12#ibcon#*before write, iclass 7, count 2 2006.285.19:26:06.12#ibcon#enter sib2, iclass 7, count 2 2006.285.19:26:06.12#ibcon#flushed, iclass 7, count 2 2006.285.19:26:06.12#ibcon#about to write, iclass 7, count 2 2006.285.19:26:06.12#ibcon#wrote, iclass 7, count 2 2006.285.19:26:06.12#ibcon#about to read 3, iclass 7, count 2 2006.285.19:26:06.15#ibcon#read 3, iclass 7, count 2 2006.285.19:26:06.15#ibcon#about to read 4, iclass 7, count 2 2006.285.19:26:06.15#ibcon#read 4, iclass 7, count 2 2006.285.19:26:06.15#ibcon#about to read 5, iclass 7, count 2 2006.285.19:26:06.15#ibcon#read 5, iclass 7, count 2 2006.285.19:26:06.15#ibcon#about to read 6, iclass 7, count 2 2006.285.19:26:06.15#ibcon#read 6, iclass 7, count 2 2006.285.19:26:06.15#ibcon#end of sib2, iclass 7, count 2 2006.285.19:26:06.15#ibcon#*after write, iclass 7, count 2 2006.285.19:26:06.15#ibcon#*before return 0, iclass 7, count 2 2006.285.19:26:06.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:26:06.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:26:06.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.19:26:06.15#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:06.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:26:06.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:26:06.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:26:06.27#ibcon#enter wrdev, iclass 7, count 0 2006.285.19:26:06.27#ibcon#first serial, iclass 7, count 0 2006.285.19:26:06.27#ibcon#enter sib2, iclass 7, count 0 2006.285.19:26:06.27#ibcon#flushed, iclass 7, count 0 2006.285.19:26:06.27#ibcon#about to write, iclass 7, count 0 2006.285.19:26:06.27#ibcon#wrote, iclass 7, count 0 2006.285.19:26:06.27#ibcon#about to read 3, iclass 7, count 0 2006.285.19:26:06.29#ibcon#read 3, iclass 7, count 0 2006.285.19:26:06.29#ibcon#about to read 4, iclass 7, count 0 2006.285.19:26:06.29#ibcon#read 4, iclass 7, count 0 2006.285.19:26:06.29#ibcon#about to read 5, iclass 7, count 0 2006.285.19:26:06.29#ibcon#read 5, iclass 7, count 0 2006.285.19:26:06.29#ibcon#about to read 6, iclass 7, count 0 2006.285.19:26:06.29#ibcon#read 6, iclass 7, count 0 2006.285.19:26:06.29#ibcon#end of sib2, iclass 7, count 0 2006.285.19:26:06.29#ibcon#*mode == 0, iclass 7, count 0 2006.285.19:26:06.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.19:26:06.29#ibcon#[27=USB\r\n] 2006.285.19:26:06.29#ibcon#*before write, iclass 7, count 0 2006.285.19:26:06.29#ibcon#enter sib2, iclass 7, count 0 2006.285.19:26:06.29#ibcon#flushed, iclass 7, count 0 2006.285.19:26:06.29#ibcon#about to write, iclass 7, count 0 2006.285.19:26:06.29#ibcon#wrote, iclass 7, count 0 2006.285.19:26:06.29#ibcon#about to read 3, iclass 7, count 0 2006.285.19:26:06.32#ibcon#read 3, iclass 7, count 0 2006.285.19:26:06.32#ibcon#about to read 4, iclass 7, count 0 2006.285.19:26:06.32#ibcon#read 4, iclass 7, count 0 2006.285.19:26:06.32#ibcon#about to read 5, iclass 7, count 0 2006.285.19:26:06.32#ibcon#read 5, iclass 7, count 0 2006.285.19:26:06.32#ibcon#about to read 6, iclass 7, count 0 2006.285.19:26:06.32#ibcon#read 6, iclass 7, count 0 2006.285.19:26:06.32#ibcon#end of sib2, iclass 7, count 0 2006.285.19:26:06.32#ibcon#*after write, iclass 7, count 0 2006.285.19:26:06.32#ibcon#*before return 0, iclass 7, count 0 2006.285.19:26:06.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:26:06.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:26:06.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.19:26:06.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.19:26:06.32$vck44/vblo=8,744.99 2006.285.19:26:06.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.19:26:06.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.19:26:06.32#ibcon#ireg 17 cls_cnt 0 2006.285.19:26:06.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:26:06.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:26:06.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:26:06.32#ibcon#enter wrdev, iclass 11, count 0 2006.285.19:26:06.32#ibcon#first serial, iclass 11, count 0 2006.285.19:26:06.32#ibcon#enter sib2, iclass 11, count 0 2006.285.19:26:06.32#ibcon#flushed, iclass 11, count 0 2006.285.19:26:06.32#ibcon#about to write, iclass 11, count 0 2006.285.19:26:06.32#ibcon#wrote, iclass 11, count 0 2006.285.19:26:06.32#ibcon#about to read 3, iclass 11, count 0 2006.285.19:26:06.34#ibcon#read 3, iclass 11, count 0 2006.285.19:26:06.34#ibcon#about to read 4, iclass 11, count 0 2006.285.19:26:06.34#ibcon#read 4, iclass 11, count 0 2006.285.19:26:06.34#ibcon#about to read 5, iclass 11, count 0 2006.285.19:26:06.34#ibcon#read 5, iclass 11, count 0 2006.285.19:26:06.34#ibcon#about to read 6, iclass 11, count 0 2006.285.19:26:06.34#ibcon#read 6, iclass 11, count 0 2006.285.19:26:06.34#ibcon#end of sib2, iclass 11, count 0 2006.285.19:26:06.34#ibcon#*mode == 0, iclass 11, count 0 2006.285.19:26:06.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.19:26:06.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.19:26:06.34#ibcon#*before write, iclass 11, count 0 2006.285.19:26:06.34#ibcon#enter sib2, iclass 11, count 0 2006.285.19:26:06.34#ibcon#flushed, iclass 11, count 0 2006.285.19:26:06.34#ibcon#about to write, iclass 11, count 0 2006.285.19:26:06.34#ibcon#wrote, iclass 11, count 0 2006.285.19:26:06.34#ibcon#about to read 3, iclass 11, count 0 2006.285.19:26:06.38#ibcon#read 3, iclass 11, count 0 2006.285.19:26:06.38#ibcon#about to read 4, iclass 11, count 0 2006.285.19:26:06.38#ibcon#read 4, iclass 11, count 0 2006.285.19:26:06.38#ibcon#about to read 5, iclass 11, count 0 2006.285.19:26:06.38#ibcon#read 5, iclass 11, count 0 2006.285.19:26:06.38#ibcon#about to read 6, iclass 11, count 0 2006.285.19:26:06.38#ibcon#read 6, iclass 11, count 0 2006.285.19:26:06.38#ibcon#end of sib2, iclass 11, count 0 2006.285.19:26:06.38#ibcon#*after write, iclass 11, count 0 2006.285.19:26:06.38#ibcon#*before return 0, iclass 11, count 0 2006.285.19:26:06.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:26:06.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:26:06.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.19:26:06.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.19:26:06.38$vck44/vb=8,4 2006.285.19:26:06.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.19:26:06.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.19:26:06.38#ibcon#ireg 11 cls_cnt 2 2006.285.19:26:06.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:26:06.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:26:06.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:26:06.44#ibcon#enter wrdev, iclass 13, count 2 2006.285.19:26:06.44#ibcon#first serial, iclass 13, count 2 2006.285.19:26:06.44#ibcon#enter sib2, iclass 13, count 2 2006.285.19:26:06.44#ibcon#flushed, iclass 13, count 2 2006.285.19:26:06.44#ibcon#about to write, iclass 13, count 2 2006.285.19:26:06.44#ibcon#wrote, iclass 13, count 2 2006.285.19:26:06.44#ibcon#about to read 3, iclass 13, count 2 2006.285.19:26:06.46#ibcon#read 3, iclass 13, count 2 2006.285.19:26:06.46#ibcon#about to read 4, iclass 13, count 2 2006.285.19:26:06.46#ibcon#read 4, iclass 13, count 2 2006.285.19:26:06.46#ibcon#about to read 5, iclass 13, count 2 2006.285.19:26:06.46#ibcon#read 5, iclass 13, count 2 2006.285.19:26:06.46#ibcon#about to read 6, iclass 13, count 2 2006.285.19:26:06.46#ibcon#read 6, iclass 13, count 2 2006.285.19:26:06.46#ibcon#end of sib2, iclass 13, count 2 2006.285.19:26:06.46#ibcon#*mode == 0, iclass 13, count 2 2006.285.19:26:06.46#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.19:26:06.46#ibcon#[27=AT08-04\r\n] 2006.285.19:26:06.46#ibcon#*before write, iclass 13, count 2 2006.285.19:26:06.46#ibcon#enter sib2, iclass 13, count 2 2006.285.19:26:06.46#ibcon#flushed, iclass 13, count 2 2006.285.19:26:06.46#ibcon#about to write, iclass 13, count 2 2006.285.19:26:06.46#ibcon#wrote, iclass 13, count 2 2006.285.19:26:06.46#ibcon#about to read 3, iclass 13, count 2 2006.285.19:26:06.49#ibcon#read 3, iclass 13, count 2 2006.285.19:26:06.49#ibcon#about to read 4, iclass 13, count 2 2006.285.19:26:06.49#ibcon#read 4, iclass 13, count 2 2006.285.19:26:06.49#ibcon#about to read 5, iclass 13, count 2 2006.285.19:26:06.49#ibcon#read 5, iclass 13, count 2 2006.285.19:26:06.49#ibcon#about to read 6, iclass 13, count 2 2006.285.19:26:06.49#ibcon#read 6, iclass 13, count 2 2006.285.19:26:06.49#ibcon#end of sib2, iclass 13, count 2 2006.285.19:26:06.49#ibcon#*after write, iclass 13, count 2 2006.285.19:26:06.49#ibcon#*before return 0, iclass 13, count 2 2006.285.19:26:06.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:26:06.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:26:06.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.19:26:06.49#ibcon#ireg 7 cls_cnt 0 2006.285.19:26:06.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:26:06.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:26:06.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:26:06.61#ibcon#enter wrdev, iclass 13, count 0 2006.285.19:26:06.61#ibcon#first serial, iclass 13, count 0 2006.285.19:26:06.61#ibcon#enter sib2, iclass 13, count 0 2006.285.19:26:06.61#ibcon#flushed, iclass 13, count 0 2006.285.19:26:06.61#ibcon#about to write, iclass 13, count 0 2006.285.19:26:06.61#ibcon#wrote, iclass 13, count 0 2006.285.19:26:06.61#ibcon#about to read 3, iclass 13, count 0 2006.285.19:26:06.63#ibcon#read 3, iclass 13, count 0 2006.285.19:26:06.63#ibcon#about to read 4, iclass 13, count 0 2006.285.19:26:06.63#ibcon#read 4, iclass 13, count 0 2006.285.19:26:06.63#ibcon#about to read 5, iclass 13, count 0 2006.285.19:26:06.63#ibcon#read 5, iclass 13, count 0 2006.285.19:26:06.63#ibcon#about to read 6, iclass 13, count 0 2006.285.19:26:06.63#ibcon#read 6, iclass 13, count 0 2006.285.19:26:06.63#ibcon#end of sib2, iclass 13, count 0 2006.285.19:26:06.63#ibcon#*mode == 0, iclass 13, count 0 2006.285.19:26:06.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.19:26:06.63#ibcon#[27=USB\r\n] 2006.285.19:26:06.63#ibcon#*before write, iclass 13, count 0 2006.285.19:26:06.63#ibcon#enter sib2, iclass 13, count 0 2006.285.19:26:06.63#ibcon#flushed, iclass 13, count 0 2006.285.19:26:06.63#ibcon#about to write, iclass 13, count 0 2006.285.19:26:06.63#ibcon#wrote, iclass 13, count 0 2006.285.19:26:06.63#ibcon#about to read 3, iclass 13, count 0 2006.285.19:26:06.66#ibcon#read 3, iclass 13, count 0 2006.285.19:26:06.66#ibcon#about to read 4, iclass 13, count 0 2006.285.19:26:06.66#ibcon#read 4, iclass 13, count 0 2006.285.19:26:06.66#ibcon#about to read 5, iclass 13, count 0 2006.285.19:26:06.66#ibcon#read 5, iclass 13, count 0 2006.285.19:26:06.66#ibcon#about to read 6, iclass 13, count 0 2006.285.19:26:06.66#ibcon#read 6, iclass 13, count 0 2006.285.19:26:06.66#ibcon#end of sib2, iclass 13, count 0 2006.285.19:26:06.66#ibcon#*after write, iclass 13, count 0 2006.285.19:26:06.66#ibcon#*before return 0, iclass 13, count 0 2006.285.19:26:06.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:26:06.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:26:06.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.19:26:06.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.19:26:06.66$vck44/vabw=wide 2006.285.19:26:06.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.19:26:06.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.19:26:06.66#ibcon#ireg 8 cls_cnt 0 2006.285.19:26:06.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:26:06.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:26:06.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:26:06.66#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:26:06.66#ibcon#first serial, iclass 15, count 0 2006.285.19:26:06.66#ibcon#enter sib2, iclass 15, count 0 2006.285.19:26:06.66#ibcon#flushed, iclass 15, count 0 2006.285.19:26:06.66#ibcon#about to write, iclass 15, count 0 2006.285.19:26:06.66#ibcon#wrote, iclass 15, count 0 2006.285.19:26:06.66#ibcon#about to read 3, iclass 15, count 0 2006.285.19:26:06.68#ibcon#read 3, iclass 15, count 0 2006.285.19:26:06.68#ibcon#about to read 4, iclass 15, count 0 2006.285.19:26:06.68#ibcon#read 4, iclass 15, count 0 2006.285.19:26:06.68#ibcon#about to read 5, iclass 15, count 0 2006.285.19:26:06.68#ibcon#read 5, iclass 15, count 0 2006.285.19:26:06.68#ibcon#about to read 6, iclass 15, count 0 2006.285.19:26:06.68#ibcon#read 6, iclass 15, count 0 2006.285.19:26:06.68#ibcon#end of sib2, iclass 15, count 0 2006.285.19:26:06.68#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:26:06.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:26:06.68#ibcon#[25=BW32\r\n] 2006.285.19:26:06.68#ibcon#*before write, iclass 15, count 0 2006.285.19:26:06.68#ibcon#enter sib2, iclass 15, count 0 2006.285.19:26:06.68#ibcon#flushed, iclass 15, count 0 2006.285.19:26:06.68#ibcon#about to write, iclass 15, count 0 2006.285.19:26:06.68#ibcon#wrote, iclass 15, count 0 2006.285.19:26:06.68#ibcon#about to read 3, iclass 15, count 0 2006.285.19:26:06.71#ibcon#read 3, iclass 15, count 0 2006.285.19:26:06.71#ibcon#about to read 4, iclass 15, count 0 2006.285.19:26:06.71#ibcon#read 4, iclass 15, count 0 2006.285.19:26:06.71#ibcon#about to read 5, iclass 15, count 0 2006.285.19:26:06.71#ibcon#read 5, iclass 15, count 0 2006.285.19:26:06.71#ibcon#about to read 6, iclass 15, count 0 2006.285.19:26:06.71#ibcon#read 6, iclass 15, count 0 2006.285.19:26:06.71#ibcon#end of sib2, iclass 15, count 0 2006.285.19:26:06.71#ibcon#*after write, iclass 15, count 0 2006.285.19:26:06.71#ibcon#*before return 0, iclass 15, count 0 2006.285.19:26:06.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:26:06.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:26:06.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:26:06.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:26:06.71$vck44/vbbw=wide 2006.285.19:26:06.71#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.19:26:06.71#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.19:26:06.71#ibcon#ireg 8 cls_cnt 0 2006.285.19:26:06.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:26:06.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:26:06.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:26:06.78#ibcon#enter wrdev, iclass 17, count 0 2006.285.19:26:06.78#ibcon#first serial, iclass 17, count 0 2006.285.19:26:06.78#ibcon#enter sib2, iclass 17, count 0 2006.285.19:26:06.78#ibcon#flushed, iclass 17, count 0 2006.285.19:26:06.78#ibcon#about to write, iclass 17, count 0 2006.285.19:26:06.78#ibcon#wrote, iclass 17, count 0 2006.285.19:26:06.78#ibcon#about to read 3, iclass 17, count 0 2006.285.19:26:06.80#ibcon#read 3, iclass 17, count 0 2006.285.19:26:06.80#ibcon#about to read 4, iclass 17, count 0 2006.285.19:26:06.80#ibcon#read 4, iclass 17, count 0 2006.285.19:26:06.80#ibcon#about to read 5, iclass 17, count 0 2006.285.19:26:06.80#ibcon#read 5, iclass 17, count 0 2006.285.19:26:06.80#ibcon#about to read 6, iclass 17, count 0 2006.285.19:26:06.80#ibcon#read 6, iclass 17, count 0 2006.285.19:26:06.80#ibcon#end of sib2, iclass 17, count 0 2006.285.19:26:06.80#ibcon#*mode == 0, iclass 17, count 0 2006.285.19:26:06.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.19:26:06.80#ibcon#[27=BW32\r\n] 2006.285.19:26:06.80#ibcon#*before write, iclass 17, count 0 2006.285.19:26:06.80#ibcon#enter sib2, iclass 17, count 0 2006.285.19:26:06.80#ibcon#flushed, iclass 17, count 0 2006.285.19:26:06.80#ibcon#about to write, iclass 17, count 0 2006.285.19:26:06.80#ibcon#wrote, iclass 17, count 0 2006.285.19:26:06.80#ibcon#about to read 3, iclass 17, count 0 2006.285.19:26:06.83#ibcon#read 3, iclass 17, count 0 2006.285.19:26:06.83#ibcon#about to read 4, iclass 17, count 0 2006.285.19:26:06.83#ibcon#read 4, iclass 17, count 0 2006.285.19:26:06.83#ibcon#about to read 5, iclass 17, count 0 2006.285.19:26:06.83#ibcon#read 5, iclass 17, count 0 2006.285.19:26:06.83#ibcon#about to read 6, iclass 17, count 0 2006.285.19:26:06.83#ibcon#read 6, iclass 17, count 0 2006.285.19:26:06.83#ibcon#end of sib2, iclass 17, count 0 2006.285.19:26:06.83#ibcon#*after write, iclass 17, count 0 2006.285.19:26:06.83#ibcon#*before return 0, iclass 17, count 0 2006.285.19:26:06.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:26:06.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.19:26:06.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.19:26:06.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.19:26:06.83$setupk4/ifdk4 2006.285.19:26:06.83$ifdk4/lo= 2006.285.19:26:06.83$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.19:26:06.83$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.19:26:06.83$ifdk4/patch= 2006.285.19:26:06.83$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.19:26:06.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.19:26:06.83$setupk4/!*+20s 2006.285.19:26:10.78#abcon#<5=/14 0.6 1.3 14.911001015.1\r\n> 2006.285.19:26:10.80#abcon#{5=INTERFACE CLEAR} 2006.285.19:26:10.86#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:26:14.13#trakl#Source acquired 2006.285.19:26:15.13#flagr#flagr/antenna,acquired 2006.285.19:26:20.39$setupk4/"tpicd 2006.285.19:26:20.39$setupk4/echo=off 2006.285.19:26:20.39$setupk4/xlog=off 2006.285.19:26:20.39:!2006.285.19:30:15 2006.285.19:30:15.02:preob 2006.285.19:30:16.14/onsource/TRACKING 2006.285.19:30:16.14:!2006.285.19:30:25 2006.285.19:30:25.02:"tape 2006.285.19:30:25.02:"st=record 2006.285.19:30:25.02:data_valid=on 2006.285.19:30:25.02:midob 2006.285.19:30:26.15/onsource/TRACKING 2006.285.19:30:26.15/wx/14.89,1015.1,100 2006.285.19:30:26.35/cable/+6.5064E-03 2006.285.19:30:27.44/va/01,07,usb,yes,32,35 2006.285.19:30:27.44/va/02,06,usb,yes,32,33 2006.285.19:30:27.44/va/03,07,usb,yes,32,34 2006.285.19:30:27.44/va/04,06,usb,yes,33,35 2006.285.19:30:27.44/va/05,03,usb,yes,33,33 2006.285.19:30:27.44/va/06,04,usb,yes,30,29 2006.285.19:30:27.44/va/07,04,usb,yes,30,31 2006.285.19:30:27.44/va/08,03,usb,yes,31,38 2006.285.19:30:27.67/valo/01,524.99,yes,locked 2006.285.19:30:27.67/valo/02,534.99,yes,locked 2006.285.19:30:27.67/valo/03,564.99,yes,locked 2006.285.19:30:27.67/valo/04,624.99,yes,locked 2006.285.19:30:27.67/valo/05,734.99,yes,locked 2006.285.19:30:27.67/valo/06,814.99,yes,locked 2006.285.19:30:27.67/valo/07,864.99,yes,locked 2006.285.19:30:27.67/valo/08,884.99,yes,locked 2006.285.19:30:28.76/vb/01,04,usb,yes,30,28 2006.285.19:30:28.76/vb/02,05,usb,yes,29,29 2006.285.19:30:28.76/vb/03,04,usb,yes,30,33 2006.285.19:30:28.76/vb/04,05,usb,yes,30,29 2006.285.19:30:28.76/vb/05,04,usb,yes,26,29 2006.285.19:30:28.76/vb/06,03,usb,yes,38,34 2006.285.19:30:28.76/vb/07,04,usb,yes,30,30 2006.285.19:30:28.76/vb/08,04,usb,yes,28,31 2006.285.19:30:28.99/vblo/01,629.99,yes,locked 2006.285.19:30:28.99/vblo/02,634.99,yes,locked 2006.285.19:30:28.99/vblo/03,649.99,yes,locked 2006.285.19:30:28.99/vblo/04,679.99,yes,locked 2006.285.19:30:28.99/vblo/05,709.99,yes,locked 2006.285.19:30:28.99/vblo/06,719.99,yes,locked 2006.285.19:30:28.99/vblo/07,734.99,yes,locked 2006.285.19:30:28.99/vblo/08,744.99,yes,locked 2006.285.19:30:29.13/vabw/8 2006.285.19:30:29.28/vbbw/8 2006.285.19:30:29.37/xfe/off,on,12.0 2006.285.19:30:29.75/ifatt/23,28,28,28 2006.285.19:30:30.08/fmout-gps/S +2.68E-07 2006.285.19:30:30.09:!2006.285.19:33:55 2006.285.19:33:55.01:data_valid=off 2006.285.19:33:55.02:"et 2006.285.19:33:55.02:!+3s 2006.285.19:33:58.04:"tape 2006.285.19:33:58.04:postob 2006.285.19:33:58.23/cable/+6.5058E-03 2006.285.19:33:58.23/wx/14.90,1015.1,100 2006.285.19:33:58.29/fmout-gps/S +2.68E-07 2006.285.19:33:58.29:scan_name=285-1944,jd0610,290 2006.285.19:33:58.29:source=oj287,085448.87,200630.6,2000.0,cw 2006.285.19:33:59.14#flagr#flagr/antenna,new-source 2006.285.19:33:59.15:checkk5 2006.285.19:33:59.81/chk_autoobs//k5ts1/ autoobs is running! 2006.285.19:34:00.20/chk_autoobs//k5ts2/ autoobs is running! 2006.285.19:34:00.67/chk_autoobs//k5ts3/ autoobs is running! 2006.285.19:34:01.48/chk_autoobs//k5ts4/ autoobs is running! 2006.285.19:34:02.09/chk_obsdata//k5ts1/T2851930??a.dat file size is correct (nominal:840MB, actual:840MB). 2006.285.19:34:02.49/chk_obsdata//k5ts2/T2851930??b.dat file size is correct (nominal:840MB, actual:840MB). 2006.285.19:34:03.13/chk_obsdata//k5ts3/T2851930??c.dat file size is correct (nominal:840MB, actual:840MB). 2006.285.19:34:03.48/chk_obsdata//k5ts4/T2851930??d.dat file size is correct (nominal:840MB, actual:840MB). 2006.285.19:34:04.54/k5log//k5ts1_log_newline 2006.285.19:34:05.31/k5log//k5ts2_log_newline 2006.285.19:34:06.07/k5log//k5ts3_log_newline 2006.285.19:34:07.46/k5log//k5ts4_log_newline 2006.285.19:34:07.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.19:34:07.48:setupk4=1 2006.285.19:34:07.48$setupk4/echo=on 2006.285.19:34:07.48$setupk4/pcalon 2006.285.19:34:07.48$pcalon/"no phase cal control is implemented here 2006.285.19:34:07.48$setupk4/"tpicd=stop 2006.285.19:34:07.48$setupk4/"rec=synch_on 2006.285.19:34:07.48$setupk4/"rec_mode=128 2006.285.19:34:07.48$setupk4/!* 2006.285.19:34:07.48$setupk4/recpk4 2006.285.19:34:07.48$recpk4/recpatch= 2006.285.19:34:07.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.19:34:07.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.19:34:07.48$setupk4/vck44 2006.285.19:34:07.48$vck44/valo=1,524.99 2006.285.19:34:07.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.19:34:07.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.19:34:07.49#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:07.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:34:07.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:34:07.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:34:07.49#ibcon#enter wrdev, iclass 30, count 0 2006.285.19:34:07.49#ibcon#first serial, iclass 30, count 0 2006.285.19:34:07.49#ibcon#enter sib2, iclass 30, count 0 2006.285.19:34:07.49#ibcon#flushed, iclass 30, count 0 2006.285.19:34:07.49#ibcon#about to write, iclass 30, count 0 2006.285.19:34:07.49#ibcon#wrote, iclass 30, count 0 2006.285.19:34:07.49#ibcon#about to read 3, iclass 30, count 0 2006.285.19:34:07.50#ibcon#read 3, iclass 30, count 0 2006.285.19:34:07.50#ibcon#about to read 4, iclass 30, count 0 2006.285.19:34:07.50#ibcon#read 4, iclass 30, count 0 2006.285.19:34:07.50#ibcon#about to read 5, iclass 30, count 0 2006.285.19:34:07.50#ibcon#read 5, iclass 30, count 0 2006.285.19:34:07.50#ibcon#about to read 6, iclass 30, count 0 2006.285.19:34:07.50#ibcon#read 6, iclass 30, count 0 2006.285.19:34:07.50#ibcon#end of sib2, iclass 30, count 0 2006.285.19:34:07.50#ibcon#*mode == 0, iclass 30, count 0 2006.285.19:34:07.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.19:34:07.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.19:34:07.50#ibcon#*before write, iclass 30, count 0 2006.285.19:34:07.50#ibcon#enter sib2, iclass 30, count 0 2006.285.19:34:07.50#ibcon#flushed, iclass 30, count 0 2006.285.19:34:07.50#ibcon#about to write, iclass 30, count 0 2006.285.19:34:07.50#ibcon#wrote, iclass 30, count 0 2006.285.19:34:07.50#ibcon#about to read 3, iclass 30, count 0 2006.285.19:34:07.55#ibcon#read 3, iclass 30, count 0 2006.285.19:34:07.55#ibcon#about to read 4, iclass 30, count 0 2006.285.19:34:07.55#ibcon#read 4, iclass 30, count 0 2006.285.19:34:07.55#ibcon#about to read 5, iclass 30, count 0 2006.285.19:34:07.55#ibcon#read 5, iclass 30, count 0 2006.285.19:34:07.55#ibcon#about to read 6, iclass 30, count 0 2006.285.19:34:07.55#ibcon#read 6, iclass 30, count 0 2006.285.19:34:07.55#ibcon#end of sib2, iclass 30, count 0 2006.285.19:34:07.55#ibcon#*after write, iclass 30, count 0 2006.285.19:34:07.55#ibcon#*before return 0, iclass 30, count 0 2006.285.19:34:07.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:34:07.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:34:07.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.19:34:07.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.19:34:07.56$vck44/va=1,7 2006.285.19:34:07.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.19:34:07.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.19:34:07.56#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:07.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:34:07.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:34:07.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:34:07.56#ibcon#enter wrdev, iclass 32, count 2 2006.285.19:34:07.56#ibcon#first serial, iclass 32, count 2 2006.285.19:34:07.56#ibcon#enter sib2, iclass 32, count 2 2006.285.19:34:07.56#ibcon#flushed, iclass 32, count 2 2006.285.19:34:07.56#ibcon#about to write, iclass 32, count 2 2006.285.19:34:07.56#ibcon#wrote, iclass 32, count 2 2006.285.19:34:07.56#ibcon#about to read 3, iclass 32, count 2 2006.285.19:34:07.57#ibcon#read 3, iclass 32, count 2 2006.285.19:34:07.57#ibcon#about to read 4, iclass 32, count 2 2006.285.19:34:07.57#ibcon#read 4, iclass 32, count 2 2006.285.19:34:07.57#ibcon#about to read 5, iclass 32, count 2 2006.285.19:34:07.57#ibcon#read 5, iclass 32, count 2 2006.285.19:34:07.57#ibcon#about to read 6, iclass 32, count 2 2006.285.19:34:07.57#ibcon#read 6, iclass 32, count 2 2006.285.19:34:07.57#ibcon#end of sib2, iclass 32, count 2 2006.285.19:34:07.57#ibcon#*mode == 0, iclass 32, count 2 2006.285.19:34:07.57#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.19:34:07.57#ibcon#[25=AT01-07\r\n] 2006.285.19:34:07.57#ibcon#*before write, iclass 32, count 2 2006.285.19:34:07.57#ibcon#enter sib2, iclass 32, count 2 2006.285.19:34:07.57#ibcon#flushed, iclass 32, count 2 2006.285.19:34:07.57#ibcon#about to write, iclass 32, count 2 2006.285.19:34:07.57#ibcon#wrote, iclass 32, count 2 2006.285.19:34:07.57#ibcon#about to read 3, iclass 32, count 2 2006.285.19:34:07.60#ibcon#read 3, iclass 32, count 2 2006.285.19:34:07.60#ibcon#about to read 4, iclass 32, count 2 2006.285.19:34:07.60#ibcon#read 4, iclass 32, count 2 2006.285.19:34:07.60#ibcon#about to read 5, iclass 32, count 2 2006.285.19:34:07.60#ibcon#read 5, iclass 32, count 2 2006.285.19:34:07.60#ibcon#about to read 6, iclass 32, count 2 2006.285.19:34:07.60#ibcon#read 6, iclass 32, count 2 2006.285.19:34:07.60#ibcon#end of sib2, iclass 32, count 2 2006.285.19:34:07.60#ibcon#*after write, iclass 32, count 2 2006.285.19:34:07.60#ibcon#*before return 0, iclass 32, count 2 2006.285.19:34:07.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:34:07.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:34:07.60#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.19:34:07.60#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:07.60#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:34:07.72#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:34:07.72#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:34:07.72#ibcon#enter wrdev, iclass 32, count 0 2006.285.19:34:07.72#ibcon#first serial, iclass 32, count 0 2006.285.19:34:07.72#ibcon#enter sib2, iclass 32, count 0 2006.285.19:34:07.72#ibcon#flushed, iclass 32, count 0 2006.285.19:34:07.72#ibcon#about to write, iclass 32, count 0 2006.285.19:34:07.72#ibcon#wrote, iclass 32, count 0 2006.285.19:34:07.72#ibcon#about to read 3, iclass 32, count 0 2006.285.19:34:07.74#ibcon#read 3, iclass 32, count 0 2006.285.19:34:07.74#ibcon#about to read 4, iclass 32, count 0 2006.285.19:34:07.74#ibcon#read 4, iclass 32, count 0 2006.285.19:34:07.74#ibcon#about to read 5, iclass 32, count 0 2006.285.19:34:07.74#ibcon#read 5, iclass 32, count 0 2006.285.19:34:07.74#ibcon#about to read 6, iclass 32, count 0 2006.285.19:34:07.74#ibcon#read 6, iclass 32, count 0 2006.285.19:34:07.74#ibcon#end of sib2, iclass 32, count 0 2006.285.19:34:07.74#ibcon#*mode == 0, iclass 32, count 0 2006.285.19:34:07.74#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.19:34:07.74#ibcon#[25=USB\r\n] 2006.285.19:34:07.74#ibcon#*before write, iclass 32, count 0 2006.285.19:34:07.74#ibcon#enter sib2, iclass 32, count 0 2006.285.19:34:07.74#ibcon#flushed, iclass 32, count 0 2006.285.19:34:07.74#ibcon#about to write, iclass 32, count 0 2006.285.19:34:07.74#ibcon#wrote, iclass 32, count 0 2006.285.19:34:07.74#ibcon#about to read 3, iclass 32, count 0 2006.285.19:34:07.77#ibcon#read 3, iclass 32, count 0 2006.285.19:34:07.77#ibcon#about to read 4, iclass 32, count 0 2006.285.19:34:07.77#ibcon#read 4, iclass 32, count 0 2006.285.19:34:07.77#ibcon#about to read 5, iclass 32, count 0 2006.285.19:34:07.77#ibcon#read 5, iclass 32, count 0 2006.285.19:34:07.77#ibcon#about to read 6, iclass 32, count 0 2006.285.19:34:07.77#ibcon#read 6, iclass 32, count 0 2006.285.19:34:07.77#ibcon#end of sib2, iclass 32, count 0 2006.285.19:34:07.77#ibcon#*after write, iclass 32, count 0 2006.285.19:34:07.77#ibcon#*before return 0, iclass 32, count 0 2006.285.19:34:07.77#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:34:07.77#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:34:07.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.19:34:07.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.19:34:07.77$vck44/valo=2,534.99 2006.285.19:34:07.77#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.19:34:07.77#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.19:34:07.77#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:07.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:34:07.77#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:34:07.77#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:34:07.77#ibcon#enter wrdev, iclass 34, count 0 2006.285.19:34:07.77#ibcon#first serial, iclass 34, count 0 2006.285.19:34:07.77#ibcon#enter sib2, iclass 34, count 0 2006.285.19:34:07.77#ibcon#flushed, iclass 34, count 0 2006.285.19:34:07.77#ibcon#about to write, iclass 34, count 0 2006.285.19:34:07.78#ibcon#wrote, iclass 34, count 0 2006.285.19:34:07.78#ibcon#about to read 3, iclass 34, count 0 2006.285.19:34:08.32#ibcon#read 3, iclass 34, count 0 2006.285.19:34:08.32#ibcon#about to read 4, iclass 34, count 0 2006.285.19:34:08.32#ibcon#read 4, iclass 34, count 0 2006.285.19:34:08.32#ibcon#about to read 5, iclass 34, count 0 2006.285.19:34:08.32#ibcon#read 5, iclass 34, count 0 2006.285.19:34:08.32#ibcon#about to read 6, iclass 34, count 0 2006.285.19:34:08.32#ibcon#read 6, iclass 34, count 0 2006.285.19:34:08.32#ibcon#end of sib2, iclass 34, count 0 2006.285.19:34:08.32#ibcon#*mode == 0, iclass 34, count 0 2006.285.19:34:08.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.19:34:08.32#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.19:34:08.32#ibcon#*before write, iclass 34, count 0 2006.285.19:34:08.32#ibcon#enter sib2, iclass 34, count 0 2006.285.19:34:08.32#ibcon#flushed, iclass 34, count 0 2006.285.19:34:08.32#ibcon#about to write, iclass 34, count 0 2006.285.19:34:08.32#ibcon#wrote, iclass 34, count 0 2006.285.19:34:08.32#ibcon#about to read 3, iclass 34, count 0 2006.285.19:34:08.36#ibcon#read 3, iclass 34, count 0 2006.285.19:34:08.36#ibcon#about to read 4, iclass 34, count 0 2006.285.19:34:08.36#ibcon#read 4, iclass 34, count 0 2006.285.19:34:08.36#ibcon#about to read 5, iclass 34, count 0 2006.285.19:34:08.36#ibcon#read 5, iclass 34, count 0 2006.285.19:34:08.36#ibcon#about to read 6, iclass 34, count 0 2006.285.19:34:08.36#ibcon#read 6, iclass 34, count 0 2006.285.19:34:08.36#ibcon#end of sib2, iclass 34, count 0 2006.285.19:34:08.36#ibcon#*after write, iclass 34, count 0 2006.285.19:34:08.36#ibcon#*before return 0, iclass 34, count 0 2006.285.19:34:08.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:34:08.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:34:08.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.19:34:08.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.19:34:08.36$vck44/va=2,6 2006.285.19:34:08.36#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.19:34:08.36#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.19:34:08.36#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:08.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:34:08.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:34:08.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:34:08.36#ibcon#enter wrdev, iclass 36, count 2 2006.285.19:34:08.36#ibcon#first serial, iclass 36, count 2 2006.285.19:34:08.36#ibcon#enter sib2, iclass 36, count 2 2006.285.19:34:08.37#ibcon#flushed, iclass 36, count 2 2006.285.19:34:08.37#ibcon#about to write, iclass 36, count 2 2006.285.19:34:08.37#ibcon#wrote, iclass 36, count 2 2006.285.19:34:08.37#ibcon#about to read 3, iclass 36, count 2 2006.285.19:34:08.38#ibcon#read 3, iclass 36, count 2 2006.285.19:34:08.38#ibcon#about to read 4, iclass 36, count 2 2006.285.19:34:08.38#ibcon#read 4, iclass 36, count 2 2006.285.19:34:08.38#ibcon#about to read 5, iclass 36, count 2 2006.285.19:34:08.38#ibcon#read 5, iclass 36, count 2 2006.285.19:34:08.38#ibcon#about to read 6, iclass 36, count 2 2006.285.19:34:08.38#ibcon#read 6, iclass 36, count 2 2006.285.19:34:08.38#ibcon#end of sib2, iclass 36, count 2 2006.285.19:34:08.38#ibcon#*mode == 0, iclass 36, count 2 2006.285.19:34:08.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.19:34:08.38#ibcon#[25=AT02-06\r\n] 2006.285.19:34:08.38#ibcon#*before write, iclass 36, count 2 2006.285.19:34:08.38#ibcon#enter sib2, iclass 36, count 2 2006.285.19:34:08.38#ibcon#flushed, iclass 36, count 2 2006.285.19:34:08.38#ibcon#about to write, iclass 36, count 2 2006.285.19:34:08.38#ibcon#wrote, iclass 36, count 2 2006.285.19:34:08.38#ibcon#about to read 3, iclass 36, count 2 2006.285.19:34:08.41#ibcon#read 3, iclass 36, count 2 2006.285.19:34:08.41#ibcon#about to read 4, iclass 36, count 2 2006.285.19:34:08.41#ibcon#read 4, iclass 36, count 2 2006.285.19:34:08.41#ibcon#about to read 5, iclass 36, count 2 2006.285.19:34:08.41#ibcon#read 5, iclass 36, count 2 2006.285.19:34:08.41#ibcon#about to read 6, iclass 36, count 2 2006.285.19:34:08.41#ibcon#read 6, iclass 36, count 2 2006.285.19:34:08.41#ibcon#end of sib2, iclass 36, count 2 2006.285.19:34:08.41#ibcon#*after write, iclass 36, count 2 2006.285.19:34:08.41#ibcon#*before return 0, iclass 36, count 2 2006.285.19:34:08.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:34:08.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:34:08.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.19:34:08.41#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:08.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:34:08.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:34:08.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:34:08.53#ibcon#enter wrdev, iclass 36, count 0 2006.285.19:34:08.53#ibcon#first serial, iclass 36, count 0 2006.285.19:34:08.53#ibcon#enter sib2, iclass 36, count 0 2006.285.19:34:08.53#ibcon#flushed, iclass 36, count 0 2006.285.19:34:08.53#ibcon#about to write, iclass 36, count 0 2006.285.19:34:08.53#ibcon#wrote, iclass 36, count 0 2006.285.19:34:08.53#ibcon#about to read 3, iclass 36, count 0 2006.285.19:34:08.55#ibcon#read 3, iclass 36, count 0 2006.285.19:34:08.55#ibcon#about to read 4, iclass 36, count 0 2006.285.19:34:08.55#ibcon#read 4, iclass 36, count 0 2006.285.19:34:08.55#ibcon#about to read 5, iclass 36, count 0 2006.285.19:34:08.55#ibcon#read 5, iclass 36, count 0 2006.285.19:34:08.55#ibcon#about to read 6, iclass 36, count 0 2006.285.19:34:08.55#ibcon#read 6, iclass 36, count 0 2006.285.19:34:08.55#ibcon#end of sib2, iclass 36, count 0 2006.285.19:34:08.55#ibcon#*mode == 0, iclass 36, count 0 2006.285.19:34:08.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.19:34:08.55#ibcon#[25=USB\r\n] 2006.285.19:34:08.55#ibcon#*before write, iclass 36, count 0 2006.285.19:34:08.55#ibcon#enter sib2, iclass 36, count 0 2006.285.19:34:08.55#ibcon#flushed, iclass 36, count 0 2006.285.19:34:08.55#ibcon#about to write, iclass 36, count 0 2006.285.19:34:08.55#ibcon#wrote, iclass 36, count 0 2006.285.19:34:08.55#ibcon#about to read 3, iclass 36, count 0 2006.285.19:34:08.58#ibcon#read 3, iclass 36, count 0 2006.285.19:34:08.58#ibcon#about to read 4, iclass 36, count 0 2006.285.19:34:08.58#ibcon#read 4, iclass 36, count 0 2006.285.19:34:08.58#ibcon#about to read 5, iclass 36, count 0 2006.285.19:34:08.58#ibcon#read 5, iclass 36, count 0 2006.285.19:34:08.58#ibcon#about to read 6, iclass 36, count 0 2006.285.19:34:08.58#ibcon#read 6, iclass 36, count 0 2006.285.19:34:08.58#ibcon#end of sib2, iclass 36, count 0 2006.285.19:34:08.58#ibcon#*after write, iclass 36, count 0 2006.285.19:34:08.58#ibcon#*before return 0, iclass 36, count 0 2006.285.19:34:08.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:34:08.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:34:08.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.19:34:08.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.19:34:08.58$vck44/valo=3,564.99 2006.285.19:34:08.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.19:34:08.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.19:34:08.58#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:08.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:34:08.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:34:08.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:34:08.58#ibcon#enter wrdev, iclass 38, count 0 2006.285.19:34:08.58#ibcon#first serial, iclass 38, count 0 2006.285.19:34:08.58#ibcon#enter sib2, iclass 38, count 0 2006.285.19:34:08.59#ibcon#flushed, iclass 38, count 0 2006.285.19:34:08.59#ibcon#about to write, iclass 38, count 0 2006.285.19:34:08.59#ibcon#wrote, iclass 38, count 0 2006.285.19:34:08.59#ibcon#about to read 3, iclass 38, count 0 2006.285.19:34:08.60#ibcon#read 3, iclass 38, count 0 2006.285.19:34:08.60#ibcon#about to read 4, iclass 38, count 0 2006.285.19:34:08.60#ibcon#read 4, iclass 38, count 0 2006.285.19:34:08.60#ibcon#about to read 5, iclass 38, count 0 2006.285.19:34:08.60#ibcon#read 5, iclass 38, count 0 2006.285.19:34:08.60#ibcon#about to read 6, iclass 38, count 0 2006.285.19:34:08.60#ibcon#read 6, iclass 38, count 0 2006.285.19:34:08.60#ibcon#end of sib2, iclass 38, count 0 2006.285.19:34:08.60#ibcon#*mode == 0, iclass 38, count 0 2006.285.19:34:08.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.19:34:08.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.19:34:08.60#ibcon#*before write, iclass 38, count 0 2006.285.19:34:08.60#ibcon#enter sib2, iclass 38, count 0 2006.285.19:34:08.60#ibcon#flushed, iclass 38, count 0 2006.285.19:34:08.60#ibcon#about to write, iclass 38, count 0 2006.285.19:34:08.60#ibcon#wrote, iclass 38, count 0 2006.285.19:34:08.60#ibcon#about to read 3, iclass 38, count 0 2006.285.19:34:08.64#ibcon#read 3, iclass 38, count 0 2006.285.19:34:08.64#ibcon#about to read 4, iclass 38, count 0 2006.285.19:34:08.64#ibcon#read 4, iclass 38, count 0 2006.285.19:34:08.64#ibcon#about to read 5, iclass 38, count 0 2006.285.19:34:08.64#ibcon#read 5, iclass 38, count 0 2006.285.19:34:08.64#ibcon#about to read 6, iclass 38, count 0 2006.285.19:34:08.64#ibcon#read 6, iclass 38, count 0 2006.285.19:34:08.64#ibcon#end of sib2, iclass 38, count 0 2006.285.19:34:08.64#ibcon#*after write, iclass 38, count 0 2006.285.19:34:08.64#ibcon#*before return 0, iclass 38, count 0 2006.285.19:34:08.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:34:08.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:34:08.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.19:34:08.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.19:34:08.64$vck44/va=3,7 2006.285.19:34:08.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.19:34:08.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.19:34:08.64#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:08.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:34:08.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:34:08.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:34:08.70#ibcon#enter wrdev, iclass 40, count 2 2006.285.19:34:08.70#ibcon#first serial, iclass 40, count 2 2006.285.19:34:08.70#ibcon#enter sib2, iclass 40, count 2 2006.285.19:34:08.70#ibcon#flushed, iclass 40, count 2 2006.285.19:34:08.70#ibcon#about to write, iclass 40, count 2 2006.285.19:34:08.70#ibcon#wrote, iclass 40, count 2 2006.285.19:34:08.70#ibcon#about to read 3, iclass 40, count 2 2006.285.19:34:08.72#ibcon#read 3, iclass 40, count 2 2006.285.19:34:08.72#ibcon#about to read 4, iclass 40, count 2 2006.285.19:34:08.72#ibcon#read 4, iclass 40, count 2 2006.285.19:34:08.72#ibcon#about to read 5, iclass 40, count 2 2006.285.19:34:08.72#ibcon#read 5, iclass 40, count 2 2006.285.19:34:08.72#ibcon#about to read 6, iclass 40, count 2 2006.285.19:34:08.72#ibcon#read 6, iclass 40, count 2 2006.285.19:34:08.72#ibcon#end of sib2, iclass 40, count 2 2006.285.19:34:08.72#ibcon#*mode == 0, iclass 40, count 2 2006.285.19:34:08.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.19:34:08.90#ibcon#[25=AT03-07\r\n] 2006.285.19:34:08.90#ibcon#*before write, iclass 40, count 2 2006.285.19:34:08.90#ibcon#enter sib2, iclass 40, count 2 2006.285.19:34:08.90#ibcon#flushed, iclass 40, count 2 2006.285.19:34:08.90#ibcon#about to write, iclass 40, count 2 2006.285.19:34:08.90#ibcon#wrote, iclass 40, count 2 2006.285.19:34:08.90#ibcon#about to read 3, iclass 40, count 2 2006.285.19:34:08.92#ibcon#read 3, iclass 40, count 2 2006.285.19:34:08.92#ibcon#about to read 4, iclass 40, count 2 2006.285.19:34:08.92#ibcon#read 4, iclass 40, count 2 2006.285.19:34:08.92#ibcon#about to read 5, iclass 40, count 2 2006.285.19:34:08.92#ibcon#read 5, iclass 40, count 2 2006.285.19:34:08.92#ibcon#about to read 6, iclass 40, count 2 2006.285.19:34:08.92#ibcon#read 6, iclass 40, count 2 2006.285.19:34:08.92#ibcon#end of sib2, iclass 40, count 2 2006.285.19:34:08.92#ibcon#*after write, iclass 40, count 2 2006.285.19:34:08.92#ibcon#*before return 0, iclass 40, count 2 2006.285.19:34:08.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:34:08.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:34:08.92#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.19:34:08.92#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:08.92#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:34:08.96#abcon#<5=/00 0.2 1.0 14.901001015.1\r\n> 2006.285.19:34:08.98#abcon#{5=INTERFACE CLEAR} 2006.285.19:34:09.04#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:34:09.04#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:34:09.04#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:34:09.04#ibcon#enter wrdev, iclass 40, count 0 2006.285.19:34:09.04#ibcon#first serial, iclass 40, count 0 2006.285.19:34:09.04#ibcon#enter sib2, iclass 40, count 0 2006.285.19:34:09.04#ibcon#flushed, iclass 40, count 0 2006.285.19:34:09.04#ibcon#about to write, iclass 40, count 0 2006.285.19:34:09.04#ibcon#wrote, iclass 40, count 0 2006.285.19:34:09.04#ibcon#about to read 3, iclass 40, count 0 2006.285.19:34:09.06#ibcon#read 3, iclass 40, count 0 2006.285.19:34:09.06#ibcon#about to read 4, iclass 40, count 0 2006.285.19:34:09.06#ibcon#read 4, iclass 40, count 0 2006.285.19:34:09.06#ibcon#about to read 5, iclass 40, count 0 2006.285.19:34:09.06#ibcon#read 5, iclass 40, count 0 2006.285.19:34:09.06#ibcon#about to read 6, iclass 40, count 0 2006.285.19:34:09.06#ibcon#read 6, iclass 40, count 0 2006.285.19:34:09.06#ibcon#end of sib2, iclass 40, count 0 2006.285.19:34:09.06#ibcon#*mode == 0, iclass 40, count 0 2006.285.19:34:09.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.19:34:09.06#ibcon#[25=USB\r\n] 2006.285.19:34:09.06#ibcon#*before write, iclass 40, count 0 2006.285.19:34:09.06#ibcon#enter sib2, iclass 40, count 0 2006.285.19:34:09.06#ibcon#flushed, iclass 40, count 0 2006.285.19:34:09.06#ibcon#about to write, iclass 40, count 0 2006.285.19:34:09.06#ibcon#wrote, iclass 40, count 0 2006.285.19:34:09.06#ibcon#about to read 3, iclass 40, count 0 2006.285.19:34:09.09#ibcon#read 3, iclass 40, count 0 2006.285.19:34:09.09#ibcon#about to read 4, iclass 40, count 0 2006.285.19:34:09.09#ibcon#read 4, iclass 40, count 0 2006.285.19:34:09.09#ibcon#about to read 5, iclass 40, count 0 2006.285.19:34:09.09#ibcon#read 5, iclass 40, count 0 2006.285.19:34:09.09#ibcon#about to read 6, iclass 40, count 0 2006.285.19:34:09.09#ibcon#read 6, iclass 40, count 0 2006.285.19:34:09.09#ibcon#end of sib2, iclass 40, count 0 2006.285.19:34:09.09#ibcon#*after write, iclass 40, count 0 2006.285.19:34:09.09#ibcon#*before return 0, iclass 40, count 0 2006.285.19:34:09.09#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:34:09.09#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:34:09.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.19:34:09.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.19:34:09.09$vck44/valo=4,624.99 2006.285.19:34:09.09#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.19:34:09.09#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.19:34:09.09#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:09.09#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:34:09.09#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:34:09.09#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:34:09.09#ibcon#enter wrdev, iclass 10, count 0 2006.285.19:34:09.09#ibcon#first serial, iclass 10, count 0 2006.285.19:34:09.09#ibcon#enter sib2, iclass 10, count 0 2006.285.19:34:09.09#ibcon#flushed, iclass 10, count 0 2006.285.19:34:09.09#ibcon#about to write, iclass 10, count 0 2006.285.19:34:09.09#ibcon#wrote, iclass 10, count 0 2006.285.19:34:09.10#ibcon#about to read 3, iclass 10, count 0 2006.285.19:34:09.11#ibcon#read 3, iclass 10, count 0 2006.285.19:34:09.11#ibcon#about to read 4, iclass 10, count 0 2006.285.19:34:09.11#ibcon#read 4, iclass 10, count 0 2006.285.19:34:09.11#ibcon#about to read 5, iclass 10, count 0 2006.285.19:34:09.11#ibcon#read 5, iclass 10, count 0 2006.285.19:34:09.11#ibcon#about to read 6, iclass 10, count 0 2006.285.19:34:09.11#ibcon#read 6, iclass 10, count 0 2006.285.19:34:09.11#ibcon#end of sib2, iclass 10, count 0 2006.285.19:34:09.11#ibcon#*mode == 0, iclass 10, count 0 2006.285.19:34:09.11#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.19:34:09.11#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.19:34:09.11#ibcon#*before write, iclass 10, count 0 2006.285.19:34:09.11#ibcon#enter sib2, iclass 10, count 0 2006.285.19:34:09.11#ibcon#flushed, iclass 10, count 0 2006.285.19:34:09.11#ibcon#about to write, iclass 10, count 0 2006.285.19:34:09.11#ibcon#wrote, iclass 10, count 0 2006.285.19:34:09.11#ibcon#about to read 3, iclass 10, count 0 2006.285.19:34:09.15#ibcon#read 3, iclass 10, count 0 2006.285.19:34:09.15#ibcon#about to read 4, iclass 10, count 0 2006.285.19:34:09.15#ibcon#read 4, iclass 10, count 0 2006.285.19:34:09.15#ibcon#about to read 5, iclass 10, count 0 2006.285.19:34:09.15#ibcon#read 5, iclass 10, count 0 2006.285.19:34:09.15#ibcon#about to read 6, iclass 10, count 0 2006.285.19:34:09.15#ibcon#read 6, iclass 10, count 0 2006.285.19:34:09.15#ibcon#end of sib2, iclass 10, count 0 2006.285.19:34:09.15#ibcon#*after write, iclass 10, count 0 2006.285.19:34:09.15#ibcon#*before return 0, iclass 10, count 0 2006.285.19:34:09.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:34:09.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:34:09.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.19:34:09.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.19:34:09.15$vck44/va=4,6 2006.285.19:34:09.20#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.19:34:09.20#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.19:34:09.20#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:09.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:34:09.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:34:09.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:34:09.20#ibcon#enter wrdev, iclass 12, count 2 2006.285.19:34:09.20#ibcon#first serial, iclass 12, count 2 2006.285.19:34:09.20#ibcon#enter sib2, iclass 12, count 2 2006.285.19:34:09.20#ibcon#flushed, iclass 12, count 2 2006.285.19:34:09.20#ibcon#about to write, iclass 12, count 2 2006.285.19:34:09.20#ibcon#wrote, iclass 12, count 2 2006.285.19:34:09.20#ibcon#about to read 3, iclass 12, count 2 2006.285.19:34:09.21#ibcon#read 3, iclass 12, count 2 2006.285.19:34:09.21#ibcon#about to read 4, iclass 12, count 2 2006.285.19:34:09.21#ibcon#read 4, iclass 12, count 2 2006.285.19:34:09.21#ibcon#about to read 5, iclass 12, count 2 2006.285.19:34:09.21#ibcon#read 5, iclass 12, count 2 2006.285.19:34:09.21#ibcon#about to read 6, iclass 12, count 2 2006.285.19:34:09.21#ibcon#read 6, iclass 12, count 2 2006.285.19:34:09.21#ibcon#end of sib2, iclass 12, count 2 2006.285.19:34:09.21#ibcon#*mode == 0, iclass 12, count 2 2006.285.19:34:09.21#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.19:34:09.21#ibcon#[25=AT04-06\r\n] 2006.285.19:34:09.21#ibcon#*before write, iclass 12, count 2 2006.285.19:34:09.21#ibcon#enter sib2, iclass 12, count 2 2006.285.19:34:09.21#ibcon#flushed, iclass 12, count 2 2006.285.19:34:09.21#ibcon#about to write, iclass 12, count 2 2006.285.19:34:09.21#ibcon#wrote, iclass 12, count 2 2006.285.19:34:09.21#ibcon#about to read 3, iclass 12, count 2 2006.285.19:34:09.24#ibcon#read 3, iclass 12, count 2 2006.285.19:34:09.24#ibcon#about to read 4, iclass 12, count 2 2006.285.19:34:09.24#ibcon#read 4, iclass 12, count 2 2006.285.19:34:09.24#ibcon#about to read 5, iclass 12, count 2 2006.285.19:34:09.24#ibcon#read 5, iclass 12, count 2 2006.285.19:34:09.24#ibcon#about to read 6, iclass 12, count 2 2006.285.19:34:09.24#ibcon#read 6, iclass 12, count 2 2006.285.19:34:09.24#ibcon#end of sib2, iclass 12, count 2 2006.285.19:34:09.24#ibcon#*after write, iclass 12, count 2 2006.285.19:34:09.24#ibcon#*before return 0, iclass 12, count 2 2006.285.19:34:09.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:34:09.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:34:09.24#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.19:34:09.24#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:09.24#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:34:09.36#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:34:09.36#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:34:09.36#ibcon#enter wrdev, iclass 12, count 0 2006.285.19:34:09.36#ibcon#first serial, iclass 12, count 0 2006.285.19:34:09.36#ibcon#enter sib2, iclass 12, count 0 2006.285.19:34:09.36#ibcon#flushed, iclass 12, count 0 2006.285.19:34:09.36#ibcon#about to write, iclass 12, count 0 2006.285.19:34:09.36#ibcon#wrote, iclass 12, count 0 2006.285.19:34:09.36#ibcon#about to read 3, iclass 12, count 0 2006.285.19:34:09.38#ibcon#read 3, iclass 12, count 0 2006.285.19:34:09.38#ibcon#about to read 4, iclass 12, count 0 2006.285.19:34:09.38#ibcon#read 4, iclass 12, count 0 2006.285.19:34:09.38#ibcon#about to read 5, iclass 12, count 0 2006.285.19:34:09.38#ibcon#read 5, iclass 12, count 0 2006.285.19:34:09.38#ibcon#about to read 6, iclass 12, count 0 2006.285.19:34:09.38#ibcon#read 6, iclass 12, count 0 2006.285.19:34:09.38#ibcon#end of sib2, iclass 12, count 0 2006.285.19:34:09.38#ibcon#*mode == 0, iclass 12, count 0 2006.285.19:34:09.38#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.19:34:09.38#ibcon#[25=USB\r\n] 2006.285.19:34:09.38#ibcon#*before write, iclass 12, count 0 2006.285.19:34:09.38#ibcon#enter sib2, iclass 12, count 0 2006.285.19:34:09.38#ibcon#flushed, iclass 12, count 0 2006.285.19:34:09.38#ibcon#about to write, iclass 12, count 0 2006.285.19:34:09.38#ibcon#wrote, iclass 12, count 0 2006.285.19:34:09.38#ibcon#about to read 3, iclass 12, count 0 2006.285.19:34:09.41#ibcon#read 3, iclass 12, count 0 2006.285.19:34:09.41#ibcon#about to read 4, iclass 12, count 0 2006.285.19:34:09.41#ibcon#read 4, iclass 12, count 0 2006.285.19:34:09.41#ibcon#about to read 5, iclass 12, count 0 2006.285.19:34:09.41#ibcon#read 5, iclass 12, count 0 2006.285.19:34:09.41#ibcon#about to read 6, iclass 12, count 0 2006.285.19:34:09.41#ibcon#read 6, iclass 12, count 0 2006.285.19:34:09.41#ibcon#end of sib2, iclass 12, count 0 2006.285.19:34:09.41#ibcon#*after write, iclass 12, count 0 2006.285.19:34:09.41#ibcon#*before return 0, iclass 12, count 0 2006.285.19:34:09.41#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:34:09.41#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:34:09.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.19:34:09.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.19:34:09.41$vck44/valo=5,734.99 2006.285.19:34:09.41#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.19:34:09.41#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.19:34:09.41#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:09.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:34:09.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:34:09.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:34:09.41#ibcon#enter wrdev, iclass 14, count 0 2006.285.19:34:09.41#ibcon#first serial, iclass 14, count 0 2006.285.19:34:09.41#ibcon#enter sib2, iclass 14, count 0 2006.285.19:34:09.41#ibcon#flushed, iclass 14, count 0 2006.285.19:34:09.41#ibcon#about to write, iclass 14, count 0 2006.285.19:34:09.41#ibcon#wrote, iclass 14, count 0 2006.285.19:34:09.41#ibcon#about to read 3, iclass 14, count 0 2006.285.19:34:09.43#ibcon#read 3, iclass 14, count 0 2006.285.19:34:09.43#ibcon#about to read 4, iclass 14, count 0 2006.285.19:34:09.43#ibcon#read 4, iclass 14, count 0 2006.285.19:34:09.43#ibcon#about to read 5, iclass 14, count 0 2006.285.19:34:09.43#ibcon#read 5, iclass 14, count 0 2006.285.19:34:09.43#ibcon#about to read 6, iclass 14, count 0 2006.285.19:34:09.43#ibcon#read 6, iclass 14, count 0 2006.285.19:34:09.43#ibcon#end of sib2, iclass 14, count 0 2006.285.19:34:09.43#ibcon#*mode == 0, iclass 14, count 0 2006.285.19:34:09.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.19:34:09.43#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.19:34:09.43#ibcon#*before write, iclass 14, count 0 2006.285.19:34:09.43#ibcon#enter sib2, iclass 14, count 0 2006.285.19:34:09.43#ibcon#flushed, iclass 14, count 0 2006.285.19:34:09.43#ibcon#about to write, iclass 14, count 0 2006.285.19:34:09.43#ibcon#wrote, iclass 14, count 0 2006.285.19:34:09.43#ibcon#about to read 3, iclass 14, count 0 2006.285.19:34:09.47#ibcon#read 3, iclass 14, count 0 2006.285.19:34:09.47#ibcon#about to read 4, iclass 14, count 0 2006.285.19:34:09.47#ibcon#read 4, iclass 14, count 0 2006.285.19:34:09.47#ibcon#about to read 5, iclass 14, count 0 2006.285.19:34:09.47#ibcon#read 5, iclass 14, count 0 2006.285.19:34:09.47#ibcon#about to read 6, iclass 14, count 0 2006.285.19:34:09.47#ibcon#read 6, iclass 14, count 0 2006.285.19:34:09.47#ibcon#end of sib2, iclass 14, count 0 2006.285.19:34:09.47#ibcon#*after write, iclass 14, count 0 2006.285.19:34:09.47#ibcon#*before return 0, iclass 14, count 0 2006.285.19:34:09.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:34:09.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:34:09.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.19:34:09.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.19:34:09.47$vck44/va=5,3 2006.285.19:34:09.47#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.19:34:09.47#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.19:34:09.47#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:09.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:34:09.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:34:09.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:34:09.53#ibcon#enter wrdev, iclass 16, count 2 2006.285.19:34:09.53#ibcon#first serial, iclass 16, count 2 2006.285.19:34:09.53#ibcon#enter sib2, iclass 16, count 2 2006.285.19:34:09.53#ibcon#flushed, iclass 16, count 2 2006.285.19:34:09.53#ibcon#about to write, iclass 16, count 2 2006.285.19:34:09.53#ibcon#wrote, iclass 16, count 2 2006.285.19:34:09.53#ibcon#about to read 3, iclass 16, count 2 2006.285.19:34:09.55#ibcon#read 3, iclass 16, count 2 2006.285.19:34:09.55#ibcon#about to read 4, iclass 16, count 2 2006.285.19:34:09.55#ibcon#read 4, iclass 16, count 2 2006.285.19:34:09.55#ibcon#about to read 5, iclass 16, count 2 2006.285.19:34:09.55#ibcon#read 5, iclass 16, count 2 2006.285.19:34:09.55#ibcon#about to read 6, iclass 16, count 2 2006.285.19:34:09.55#ibcon#read 6, iclass 16, count 2 2006.285.19:34:09.55#ibcon#end of sib2, iclass 16, count 2 2006.285.19:34:09.55#ibcon#*mode == 0, iclass 16, count 2 2006.285.19:34:09.55#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.19:34:09.55#ibcon#[25=AT05-03\r\n] 2006.285.19:34:09.55#ibcon#*before write, iclass 16, count 2 2006.285.19:34:09.55#ibcon#enter sib2, iclass 16, count 2 2006.285.19:34:09.55#ibcon#flushed, iclass 16, count 2 2006.285.19:34:09.55#ibcon#about to write, iclass 16, count 2 2006.285.19:34:09.55#ibcon#wrote, iclass 16, count 2 2006.285.19:34:09.55#ibcon#about to read 3, iclass 16, count 2 2006.285.19:34:09.58#ibcon#read 3, iclass 16, count 2 2006.285.19:34:09.58#ibcon#about to read 4, iclass 16, count 2 2006.285.19:34:09.58#ibcon#read 4, iclass 16, count 2 2006.285.19:34:09.58#ibcon#about to read 5, iclass 16, count 2 2006.285.19:34:09.58#ibcon#read 5, iclass 16, count 2 2006.285.19:34:09.58#ibcon#about to read 6, iclass 16, count 2 2006.285.19:34:09.58#ibcon#read 6, iclass 16, count 2 2006.285.19:34:09.58#ibcon#end of sib2, iclass 16, count 2 2006.285.19:34:09.58#ibcon#*after write, iclass 16, count 2 2006.285.19:34:09.58#ibcon#*before return 0, iclass 16, count 2 2006.285.19:34:09.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:34:09.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:34:09.58#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.19:34:09.58#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:09.58#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:34:09.70#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:34:09.70#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:34:09.70#ibcon#enter wrdev, iclass 16, count 0 2006.285.19:34:09.70#ibcon#first serial, iclass 16, count 0 2006.285.19:34:09.70#ibcon#enter sib2, iclass 16, count 0 2006.285.19:34:09.70#ibcon#flushed, iclass 16, count 0 2006.285.19:34:09.70#ibcon#about to write, iclass 16, count 0 2006.285.19:34:09.70#ibcon#wrote, iclass 16, count 0 2006.285.19:34:09.70#ibcon#about to read 3, iclass 16, count 0 2006.285.19:34:09.72#ibcon#read 3, iclass 16, count 0 2006.285.19:34:09.72#ibcon#about to read 4, iclass 16, count 0 2006.285.19:34:09.72#ibcon#read 4, iclass 16, count 0 2006.285.19:34:09.72#ibcon#about to read 5, iclass 16, count 0 2006.285.19:34:09.72#ibcon#read 5, iclass 16, count 0 2006.285.19:34:09.72#ibcon#about to read 6, iclass 16, count 0 2006.285.19:34:09.72#ibcon#read 6, iclass 16, count 0 2006.285.19:34:09.72#ibcon#end of sib2, iclass 16, count 0 2006.285.19:34:09.72#ibcon#*mode == 0, iclass 16, count 0 2006.285.19:34:09.72#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.19:34:09.72#ibcon#[25=USB\r\n] 2006.285.19:34:09.72#ibcon#*before write, iclass 16, count 0 2006.285.19:34:09.72#ibcon#enter sib2, iclass 16, count 0 2006.285.19:34:09.72#ibcon#flushed, iclass 16, count 0 2006.285.19:34:09.72#ibcon#about to write, iclass 16, count 0 2006.285.19:34:09.72#ibcon#wrote, iclass 16, count 0 2006.285.19:34:09.72#ibcon#about to read 3, iclass 16, count 0 2006.285.19:34:09.75#ibcon#read 3, iclass 16, count 0 2006.285.19:34:09.75#ibcon#about to read 4, iclass 16, count 0 2006.285.19:34:09.75#ibcon#read 4, iclass 16, count 0 2006.285.19:34:09.75#ibcon#about to read 5, iclass 16, count 0 2006.285.19:34:09.75#ibcon#read 5, iclass 16, count 0 2006.285.19:34:09.75#ibcon#about to read 6, iclass 16, count 0 2006.285.19:34:09.75#ibcon#read 6, iclass 16, count 0 2006.285.19:34:09.75#ibcon#end of sib2, iclass 16, count 0 2006.285.19:34:09.75#ibcon#*after write, iclass 16, count 0 2006.285.19:34:09.75#ibcon#*before return 0, iclass 16, count 0 2006.285.19:34:09.75#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:34:09.75#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:34:09.75#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.19:34:09.75#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.19:34:09.75$vck44/valo=6,814.99 2006.285.19:34:09.75#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.19:34:09.75#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.19:34:09.75#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:09.75#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:34:09.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:34:09.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:34:09.75#ibcon#enter wrdev, iclass 18, count 0 2006.285.19:34:09.75#ibcon#first serial, iclass 18, count 0 2006.285.19:34:09.75#ibcon#enter sib2, iclass 18, count 0 2006.285.19:34:09.75#ibcon#flushed, iclass 18, count 0 2006.285.19:34:09.75#ibcon#about to write, iclass 18, count 0 2006.285.19:34:09.75#ibcon#wrote, iclass 18, count 0 2006.285.19:34:09.75#ibcon#about to read 3, iclass 18, count 0 2006.285.19:34:09.77#ibcon#read 3, iclass 18, count 0 2006.285.19:34:09.89#ibcon#about to read 4, iclass 18, count 0 2006.285.19:34:09.89#ibcon#read 4, iclass 18, count 0 2006.285.19:34:09.89#ibcon#about to read 5, iclass 18, count 0 2006.285.19:34:09.89#ibcon#read 5, iclass 18, count 0 2006.285.19:34:09.89#ibcon#about to read 6, iclass 18, count 0 2006.285.19:34:09.89#ibcon#read 6, iclass 18, count 0 2006.285.19:34:09.89#ibcon#end of sib2, iclass 18, count 0 2006.285.19:34:09.89#ibcon#*mode == 0, iclass 18, count 0 2006.285.19:34:09.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.19:34:09.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.19:34:09.89#ibcon#*before write, iclass 18, count 0 2006.285.19:34:09.89#ibcon#enter sib2, iclass 18, count 0 2006.285.19:34:09.89#ibcon#flushed, iclass 18, count 0 2006.285.19:34:09.89#ibcon#about to write, iclass 18, count 0 2006.285.19:34:09.89#ibcon#wrote, iclass 18, count 0 2006.285.19:34:09.89#ibcon#about to read 3, iclass 18, count 0 2006.285.19:34:09.92#ibcon#read 3, iclass 18, count 0 2006.285.19:34:09.92#ibcon#about to read 4, iclass 18, count 0 2006.285.19:34:09.92#ibcon#read 4, iclass 18, count 0 2006.285.19:34:09.92#ibcon#about to read 5, iclass 18, count 0 2006.285.19:34:09.92#ibcon#read 5, iclass 18, count 0 2006.285.19:34:09.92#ibcon#about to read 6, iclass 18, count 0 2006.285.19:34:09.92#ibcon#read 6, iclass 18, count 0 2006.285.19:34:09.92#ibcon#end of sib2, iclass 18, count 0 2006.285.19:34:09.92#ibcon#*after write, iclass 18, count 0 2006.285.19:34:09.92#ibcon#*before return 0, iclass 18, count 0 2006.285.19:34:09.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:34:09.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:34:09.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.19:34:09.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.19:34:09.92$vck44/va=6,4 2006.285.19:34:09.92#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.19:34:09.92#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.19:34:09.92#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:09.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:34:09.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:34:09.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:34:09.92#ibcon#enter wrdev, iclass 20, count 2 2006.285.19:34:09.92#ibcon#first serial, iclass 20, count 2 2006.285.19:34:09.92#ibcon#enter sib2, iclass 20, count 2 2006.285.19:34:09.92#ibcon#flushed, iclass 20, count 2 2006.285.19:34:09.92#ibcon#about to write, iclass 20, count 2 2006.285.19:34:09.93#ibcon#wrote, iclass 20, count 2 2006.285.19:34:09.93#ibcon#about to read 3, iclass 20, count 2 2006.285.19:34:09.94#ibcon#read 3, iclass 20, count 2 2006.285.19:34:09.94#ibcon#about to read 4, iclass 20, count 2 2006.285.19:34:09.94#ibcon#read 4, iclass 20, count 2 2006.285.19:34:09.94#ibcon#about to read 5, iclass 20, count 2 2006.285.19:34:09.94#ibcon#read 5, iclass 20, count 2 2006.285.19:34:09.94#ibcon#about to read 6, iclass 20, count 2 2006.285.19:34:09.94#ibcon#read 6, iclass 20, count 2 2006.285.19:34:09.94#ibcon#end of sib2, iclass 20, count 2 2006.285.19:34:09.94#ibcon#*mode == 0, iclass 20, count 2 2006.285.19:34:09.94#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.19:34:09.94#ibcon#[25=AT06-04\r\n] 2006.285.19:34:09.94#ibcon#*before write, iclass 20, count 2 2006.285.19:34:09.94#ibcon#enter sib2, iclass 20, count 2 2006.285.19:34:09.94#ibcon#flushed, iclass 20, count 2 2006.285.19:34:09.94#ibcon#about to write, iclass 20, count 2 2006.285.19:34:09.94#ibcon#wrote, iclass 20, count 2 2006.285.19:34:09.94#ibcon#about to read 3, iclass 20, count 2 2006.285.19:34:09.97#ibcon#read 3, iclass 20, count 2 2006.285.19:34:09.97#ibcon#about to read 4, iclass 20, count 2 2006.285.19:34:09.97#ibcon#read 4, iclass 20, count 2 2006.285.19:34:09.97#ibcon#about to read 5, iclass 20, count 2 2006.285.19:34:09.97#ibcon#read 5, iclass 20, count 2 2006.285.19:34:09.97#ibcon#about to read 6, iclass 20, count 2 2006.285.19:34:09.97#ibcon#read 6, iclass 20, count 2 2006.285.19:34:09.97#ibcon#end of sib2, iclass 20, count 2 2006.285.19:34:09.97#ibcon#*after write, iclass 20, count 2 2006.285.19:34:09.97#ibcon#*before return 0, iclass 20, count 2 2006.285.19:34:09.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:34:09.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:34:09.97#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.19:34:09.97#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:09.97#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:34:10.09#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:34:10.09#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:34:10.09#ibcon#enter wrdev, iclass 20, count 0 2006.285.19:34:10.09#ibcon#first serial, iclass 20, count 0 2006.285.19:34:10.09#ibcon#enter sib2, iclass 20, count 0 2006.285.19:34:10.09#ibcon#flushed, iclass 20, count 0 2006.285.19:34:10.09#ibcon#about to write, iclass 20, count 0 2006.285.19:34:10.09#ibcon#wrote, iclass 20, count 0 2006.285.19:34:10.09#ibcon#about to read 3, iclass 20, count 0 2006.285.19:34:10.11#ibcon#read 3, iclass 20, count 0 2006.285.19:34:10.11#ibcon#about to read 4, iclass 20, count 0 2006.285.19:34:10.11#ibcon#read 4, iclass 20, count 0 2006.285.19:34:10.11#ibcon#about to read 5, iclass 20, count 0 2006.285.19:34:10.11#ibcon#read 5, iclass 20, count 0 2006.285.19:34:10.11#ibcon#about to read 6, iclass 20, count 0 2006.285.19:34:10.11#ibcon#read 6, iclass 20, count 0 2006.285.19:34:10.11#ibcon#end of sib2, iclass 20, count 0 2006.285.19:34:10.11#ibcon#*mode == 0, iclass 20, count 0 2006.285.19:34:10.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.19:34:10.11#ibcon#[25=USB\r\n] 2006.285.19:34:10.11#ibcon#*before write, iclass 20, count 0 2006.285.19:34:10.11#ibcon#enter sib2, iclass 20, count 0 2006.285.19:34:10.11#ibcon#flushed, iclass 20, count 0 2006.285.19:34:10.11#ibcon#about to write, iclass 20, count 0 2006.285.19:34:10.11#ibcon#wrote, iclass 20, count 0 2006.285.19:34:10.11#ibcon#about to read 3, iclass 20, count 0 2006.285.19:34:10.14#ibcon#read 3, iclass 20, count 0 2006.285.19:34:10.14#ibcon#about to read 4, iclass 20, count 0 2006.285.19:34:10.14#ibcon#read 4, iclass 20, count 0 2006.285.19:34:10.14#ibcon#about to read 5, iclass 20, count 0 2006.285.19:34:10.14#ibcon#read 5, iclass 20, count 0 2006.285.19:34:10.14#ibcon#about to read 6, iclass 20, count 0 2006.285.19:34:10.14#ibcon#read 6, iclass 20, count 0 2006.285.19:34:10.14#ibcon#end of sib2, iclass 20, count 0 2006.285.19:34:10.14#ibcon#*after write, iclass 20, count 0 2006.285.19:34:10.14#ibcon#*before return 0, iclass 20, count 0 2006.285.19:34:10.14#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:34:10.14#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:34:10.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.19:34:10.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.19:34:10.14$vck44/valo=7,864.99 2006.285.19:34:10.14#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.19:34:10.14#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.19:34:10.14#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:10.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:34:10.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:34:10.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:34:10.14#ibcon#enter wrdev, iclass 22, count 0 2006.285.19:34:10.14#ibcon#first serial, iclass 22, count 0 2006.285.19:34:10.14#ibcon#enter sib2, iclass 22, count 0 2006.285.19:34:10.14#ibcon#flushed, iclass 22, count 0 2006.285.19:34:10.14#ibcon#about to write, iclass 22, count 0 2006.285.19:34:10.14#ibcon#wrote, iclass 22, count 0 2006.285.19:34:10.14#ibcon#about to read 3, iclass 22, count 0 2006.285.19:34:10.16#ibcon#read 3, iclass 22, count 0 2006.285.19:34:10.16#ibcon#about to read 4, iclass 22, count 0 2006.285.19:34:10.16#ibcon#read 4, iclass 22, count 0 2006.285.19:34:10.16#ibcon#about to read 5, iclass 22, count 0 2006.285.19:34:10.16#ibcon#read 5, iclass 22, count 0 2006.285.19:34:10.16#ibcon#about to read 6, iclass 22, count 0 2006.285.19:34:10.16#ibcon#read 6, iclass 22, count 0 2006.285.19:34:10.16#ibcon#end of sib2, iclass 22, count 0 2006.285.19:34:10.16#ibcon#*mode == 0, iclass 22, count 0 2006.285.19:34:10.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.19:34:10.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.19:34:10.16#ibcon#*before write, iclass 22, count 0 2006.285.19:34:10.16#ibcon#enter sib2, iclass 22, count 0 2006.285.19:34:10.16#ibcon#flushed, iclass 22, count 0 2006.285.19:34:10.16#ibcon#about to write, iclass 22, count 0 2006.285.19:34:10.16#ibcon#wrote, iclass 22, count 0 2006.285.19:34:10.16#ibcon#about to read 3, iclass 22, count 0 2006.285.19:34:10.20#ibcon#read 3, iclass 22, count 0 2006.285.19:34:10.20#ibcon#about to read 4, iclass 22, count 0 2006.285.19:34:10.20#ibcon#read 4, iclass 22, count 0 2006.285.19:34:10.20#ibcon#about to read 5, iclass 22, count 0 2006.285.19:34:10.20#ibcon#read 5, iclass 22, count 0 2006.285.19:34:10.20#ibcon#about to read 6, iclass 22, count 0 2006.285.19:34:10.20#ibcon#read 6, iclass 22, count 0 2006.285.19:34:10.20#ibcon#end of sib2, iclass 22, count 0 2006.285.19:34:10.20#ibcon#*after write, iclass 22, count 0 2006.285.19:34:10.20#ibcon#*before return 0, iclass 22, count 0 2006.285.19:34:10.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:34:10.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:34:10.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.19:34:10.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.19:34:10.20$vck44/va=7,4 2006.285.19:34:10.20#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.19:34:10.20#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.19:34:10.20#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:10.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:34:10.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:34:10.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:34:10.26#ibcon#enter wrdev, iclass 24, count 2 2006.285.19:34:10.26#ibcon#first serial, iclass 24, count 2 2006.285.19:34:10.26#ibcon#enter sib2, iclass 24, count 2 2006.285.19:34:10.26#ibcon#flushed, iclass 24, count 2 2006.285.19:34:10.26#ibcon#about to write, iclass 24, count 2 2006.285.19:34:10.26#ibcon#wrote, iclass 24, count 2 2006.285.19:34:10.26#ibcon#about to read 3, iclass 24, count 2 2006.285.19:34:10.28#ibcon#read 3, iclass 24, count 2 2006.285.19:34:10.28#ibcon#about to read 4, iclass 24, count 2 2006.285.19:34:10.28#ibcon#read 4, iclass 24, count 2 2006.285.19:34:10.28#ibcon#about to read 5, iclass 24, count 2 2006.285.19:34:10.28#ibcon#read 5, iclass 24, count 2 2006.285.19:34:10.28#ibcon#about to read 6, iclass 24, count 2 2006.285.19:34:10.28#ibcon#read 6, iclass 24, count 2 2006.285.19:34:10.28#ibcon#end of sib2, iclass 24, count 2 2006.285.19:34:10.28#ibcon#*mode == 0, iclass 24, count 2 2006.285.19:34:10.28#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.19:34:10.28#ibcon#[25=AT07-04\r\n] 2006.285.19:34:10.28#ibcon#*before write, iclass 24, count 2 2006.285.19:34:10.28#ibcon#enter sib2, iclass 24, count 2 2006.285.19:34:10.28#ibcon#flushed, iclass 24, count 2 2006.285.19:34:10.28#ibcon#about to write, iclass 24, count 2 2006.285.19:34:10.28#ibcon#wrote, iclass 24, count 2 2006.285.19:34:10.28#ibcon#about to read 3, iclass 24, count 2 2006.285.19:34:10.31#ibcon#read 3, iclass 24, count 2 2006.285.19:34:10.31#ibcon#about to read 4, iclass 24, count 2 2006.285.19:34:10.31#ibcon#read 4, iclass 24, count 2 2006.285.19:34:10.31#ibcon#about to read 5, iclass 24, count 2 2006.285.19:34:10.31#ibcon#read 5, iclass 24, count 2 2006.285.19:34:10.31#ibcon#about to read 6, iclass 24, count 2 2006.285.19:34:10.31#ibcon#read 6, iclass 24, count 2 2006.285.19:34:10.31#ibcon#end of sib2, iclass 24, count 2 2006.285.19:34:10.31#ibcon#*after write, iclass 24, count 2 2006.285.19:34:10.31#ibcon#*before return 0, iclass 24, count 2 2006.285.19:34:10.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:34:10.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:34:10.31#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.19:34:10.31#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:10.31#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:34:10.43#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:34:10.43#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:34:10.43#ibcon#enter wrdev, iclass 24, count 0 2006.285.19:34:10.43#ibcon#first serial, iclass 24, count 0 2006.285.19:34:10.43#ibcon#enter sib2, iclass 24, count 0 2006.285.19:34:10.43#ibcon#flushed, iclass 24, count 0 2006.285.19:34:10.43#ibcon#about to write, iclass 24, count 0 2006.285.19:34:10.43#ibcon#wrote, iclass 24, count 0 2006.285.19:34:10.43#ibcon#about to read 3, iclass 24, count 0 2006.285.19:34:10.45#ibcon#read 3, iclass 24, count 0 2006.285.19:34:10.45#ibcon#about to read 4, iclass 24, count 0 2006.285.19:34:10.45#ibcon#read 4, iclass 24, count 0 2006.285.19:34:10.45#ibcon#about to read 5, iclass 24, count 0 2006.285.19:34:10.45#ibcon#read 5, iclass 24, count 0 2006.285.19:34:10.45#ibcon#about to read 6, iclass 24, count 0 2006.285.19:34:10.45#ibcon#read 6, iclass 24, count 0 2006.285.19:34:10.45#ibcon#end of sib2, iclass 24, count 0 2006.285.19:34:10.45#ibcon#*mode == 0, iclass 24, count 0 2006.285.19:34:10.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.19:34:10.45#ibcon#[25=USB\r\n] 2006.285.19:34:10.45#ibcon#*before write, iclass 24, count 0 2006.285.19:34:10.45#ibcon#enter sib2, iclass 24, count 0 2006.285.19:34:10.45#ibcon#flushed, iclass 24, count 0 2006.285.19:34:10.45#ibcon#about to write, iclass 24, count 0 2006.285.19:34:10.45#ibcon#wrote, iclass 24, count 0 2006.285.19:34:10.45#ibcon#about to read 3, iclass 24, count 0 2006.285.19:34:10.48#ibcon#read 3, iclass 24, count 0 2006.285.19:34:10.48#ibcon#about to read 4, iclass 24, count 0 2006.285.19:34:10.48#ibcon#read 4, iclass 24, count 0 2006.285.19:34:10.48#ibcon#about to read 5, iclass 24, count 0 2006.285.19:34:10.48#ibcon#read 5, iclass 24, count 0 2006.285.19:34:10.48#ibcon#about to read 6, iclass 24, count 0 2006.285.19:34:10.48#ibcon#read 6, iclass 24, count 0 2006.285.19:34:10.48#ibcon#end of sib2, iclass 24, count 0 2006.285.19:34:10.48#ibcon#*after write, iclass 24, count 0 2006.285.19:34:10.48#ibcon#*before return 0, iclass 24, count 0 2006.285.19:34:10.48#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:34:10.48#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:34:10.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.19:34:10.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.19:34:10.48$vck44/valo=8,884.99 2006.285.19:34:10.48#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.19:34:10.48#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.19:34:10.48#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:10.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:34:10.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:34:10.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:34:10.48#ibcon#enter wrdev, iclass 26, count 0 2006.285.19:34:10.48#ibcon#first serial, iclass 26, count 0 2006.285.19:34:10.48#ibcon#enter sib2, iclass 26, count 0 2006.285.19:34:10.48#ibcon#flushed, iclass 26, count 0 2006.285.19:34:10.48#ibcon#about to write, iclass 26, count 0 2006.285.19:34:10.48#ibcon#wrote, iclass 26, count 0 2006.285.19:34:10.48#ibcon#about to read 3, iclass 26, count 0 2006.285.19:34:10.50#ibcon#read 3, iclass 26, count 0 2006.285.19:34:10.50#ibcon#about to read 4, iclass 26, count 0 2006.285.19:34:10.50#ibcon#read 4, iclass 26, count 0 2006.285.19:34:10.50#ibcon#about to read 5, iclass 26, count 0 2006.285.19:34:10.50#ibcon#read 5, iclass 26, count 0 2006.285.19:34:10.50#ibcon#about to read 6, iclass 26, count 0 2006.285.19:34:10.50#ibcon#read 6, iclass 26, count 0 2006.285.19:34:10.50#ibcon#end of sib2, iclass 26, count 0 2006.285.19:34:10.50#ibcon#*mode == 0, iclass 26, count 0 2006.285.19:34:10.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.19:34:10.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.19:34:10.50#ibcon#*before write, iclass 26, count 0 2006.285.19:34:10.50#ibcon#enter sib2, iclass 26, count 0 2006.285.19:34:10.50#ibcon#flushed, iclass 26, count 0 2006.285.19:34:10.50#ibcon#about to write, iclass 26, count 0 2006.285.19:34:10.50#ibcon#wrote, iclass 26, count 0 2006.285.19:34:10.50#ibcon#about to read 3, iclass 26, count 0 2006.285.19:34:10.54#ibcon#read 3, iclass 26, count 0 2006.285.19:34:10.54#ibcon#about to read 4, iclass 26, count 0 2006.285.19:34:10.54#ibcon#read 4, iclass 26, count 0 2006.285.19:34:10.54#ibcon#about to read 5, iclass 26, count 0 2006.285.19:34:10.54#ibcon#read 5, iclass 26, count 0 2006.285.19:34:10.54#ibcon#about to read 6, iclass 26, count 0 2006.285.19:34:10.54#ibcon#read 6, iclass 26, count 0 2006.285.19:34:10.54#ibcon#end of sib2, iclass 26, count 0 2006.285.19:34:10.54#ibcon#*after write, iclass 26, count 0 2006.285.19:34:10.54#ibcon#*before return 0, iclass 26, count 0 2006.285.19:34:10.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:34:10.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:34:10.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.19:34:10.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.19:34:10.54$vck44/va=8,3 2006.285.19:34:10.54#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.19:34:10.54#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.19:34:10.54#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:10.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:34:10.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:34:10.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:34:10.60#ibcon#enter wrdev, iclass 28, count 2 2006.285.19:34:10.60#ibcon#first serial, iclass 28, count 2 2006.285.19:34:10.60#ibcon#enter sib2, iclass 28, count 2 2006.285.19:34:10.60#ibcon#flushed, iclass 28, count 2 2006.285.19:34:10.60#ibcon#about to write, iclass 28, count 2 2006.285.19:34:10.60#ibcon#wrote, iclass 28, count 2 2006.285.19:34:10.60#ibcon#about to read 3, iclass 28, count 2 2006.285.19:34:10.62#ibcon#read 3, iclass 28, count 2 2006.285.19:34:10.62#ibcon#about to read 4, iclass 28, count 2 2006.285.19:34:10.62#ibcon#read 4, iclass 28, count 2 2006.285.19:34:10.62#ibcon#about to read 5, iclass 28, count 2 2006.285.19:34:10.62#ibcon#read 5, iclass 28, count 2 2006.285.19:34:10.62#ibcon#about to read 6, iclass 28, count 2 2006.285.19:34:10.62#ibcon#read 6, iclass 28, count 2 2006.285.19:34:10.62#ibcon#end of sib2, iclass 28, count 2 2006.285.19:34:10.62#ibcon#*mode == 0, iclass 28, count 2 2006.285.19:34:10.62#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.19:34:10.62#ibcon#[25=AT08-03\r\n] 2006.285.19:34:10.62#ibcon#*before write, iclass 28, count 2 2006.285.19:34:10.62#ibcon#enter sib2, iclass 28, count 2 2006.285.19:34:10.62#ibcon#flushed, iclass 28, count 2 2006.285.19:34:10.62#ibcon#about to write, iclass 28, count 2 2006.285.19:34:10.62#ibcon#wrote, iclass 28, count 2 2006.285.19:34:10.62#ibcon#about to read 3, iclass 28, count 2 2006.285.19:34:10.65#ibcon#read 3, iclass 28, count 2 2006.285.19:34:10.65#ibcon#about to read 4, iclass 28, count 2 2006.285.19:34:10.65#ibcon#read 4, iclass 28, count 2 2006.285.19:34:10.65#ibcon#about to read 5, iclass 28, count 2 2006.285.19:34:10.65#ibcon#read 5, iclass 28, count 2 2006.285.19:34:10.65#ibcon#about to read 6, iclass 28, count 2 2006.285.19:34:10.65#ibcon#read 6, iclass 28, count 2 2006.285.19:34:10.65#ibcon#end of sib2, iclass 28, count 2 2006.285.19:34:10.65#ibcon#*after write, iclass 28, count 2 2006.285.19:34:10.65#ibcon#*before return 0, iclass 28, count 2 2006.285.19:34:10.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:34:10.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:34:10.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.19:34:10.65#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:10.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:34:10.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:34:10.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:34:10.77#ibcon#enter wrdev, iclass 28, count 0 2006.285.19:34:10.77#ibcon#first serial, iclass 28, count 0 2006.285.19:34:10.77#ibcon#enter sib2, iclass 28, count 0 2006.285.19:34:10.77#ibcon#flushed, iclass 28, count 0 2006.285.19:34:10.77#ibcon#about to write, iclass 28, count 0 2006.285.19:34:10.77#ibcon#wrote, iclass 28, count 0 2006.285.19:34:10.77#ibcon#about to read 3, iclass 28, count 0 2006.285.19:34:10.79#ibcon#read 3, iclass 28, count 0 2006.285.19:34:10.79#ibcon#about to read 4, iclass 28, count 0 2006.285.19:34:10.79#ibcon#read 4, iclass 28, count 0 2006.285.19:34:10.79#ibcon#about to read 5, iclass 28, count 0 2006.285.19:34:10.79#ibcon#read 5, iclass 28, count 0 2006.285.19:34:10.79#ibcon#about to read 6, iclass 28, count 0 2006.285.19:34:10.79#ibcon#read 6, iclass 28, count 0 2006.285.19:34:10.79#ibcon#end of sib2, iclass 28, count 0 2006.285.19:34:10.79#ibcon#*mode == 0, iclass 28, count 0 2006.285.19:34:10.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.19:34:10.79#ibcon#[25=USB\r\n] 2006.285.19:34:10.79#ibcon#*before write, iclass 28, count 0 2006.285.19:34:10.79#ibcon#enter sib2, iclass 28, count 0 2006.285.19:34:10.79#ibcon#flushed, iclass 28, count 0 2006.285.19:34:10.79#ibcon#about to write, iclass 28, count 0 2006.285.19:34:10.79#ibcon#wrote, iclass 28, count 0 2006.285.19:34:10.79#ibcon#about to read 3, iclass 28, count 0 2006.285.19:34:10.82#ibcon#read 3, iclass 28, count 0 2006.285.19:34:10.82#ibcon#about to read 4, iclass 28, count 0 2006.285.19:34:10.82#ibcon#read 4, iclass 28, count 0 2006.285.19:34:10.82#ibcon#about to read 5, iclass 28, count 0 2006.285.19:34:10.82#ibcon#read 5, iclass 28, count 0 2006.285.19:34:10.82#ibcon#about to read 6, iclass 28, count 0 2006.285.19:34:10.82#ibcon#read 6, iclass 28, count 0 2006.285.19:34:10.82#ibcon#end of sib2, iclass 28, count 0 2006.285.19:34:10.82#ibcon#*after write, iclass 28, count 0 2006.285.19:34:10.82#ibcon#*before return 0, iclass 28, count 0 2006.285.19:34:10.82#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:34:10.82#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:34:10.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.19:34:10.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.19:34:10.82$vck44/vblo=1,629.99 2006.285.19:34:10.82#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.19:34:10.82#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.19:34:10.82#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:10.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:34:10.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:34:10.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:34:10.82#ibcon#enter wrdev, iclass 30, count 0 2006.285.19:34:10.82#ibcon#first serial, iclass 30, count 0 2006.285.19:34:10.82#ibcon#enter sib2, iclass 30, count 0 2006.285.19:34:10.82#ibcon#flushed, iclass 30, count 0 2006.285.19:34:10.82#ibcon#about to write, iclass 30, count 0 2006.285.19:34:10.82#ibcon#wrote, iclass 30, count 0 2006.285.19:34:10.82#ibcon#about to read 3, iclass 30, count 0 2006.285.19:34:10.84#ibcon#read 3, iclass 30, count 0 2006.285.19:34:10.88#ibcon#about to read 4, iclass 30, count 0 2006.285.19:34:10.88#ibcon#read 4, iclass 30, count 0 2006.285.19:34:10.88#ibcon#about to read 5, iclass 30, count 0 2006.285.19:34:10.88#ibcon#read 5, iclass 30, count 0 2006.285.19:34:10.88#ibcon#about to read 6, iclass 30, count 0 2006.285.19:34:10.88#ibcon#read 6, iclass 30, count 0 2006.285.19:34:10.88#ibcon#end of sib2, iclass 30, count 0 2006.285.19:34:10.88#ibcon#*mode == 0, iclass 30, count 0 2006.285.19:34:10.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.19:34:10.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.19:34:10.88#ibcon#*before write, iclass 30, count 0 2006.285.19:34:10.88#ibcon#enter sib2, iclass 30, count 0 2006.285.19:34:10.88#ibcon#flushed, iclass 30, count 0 2006.285.19:34:10.88#ibcon#about to write, iclass 30, count 0 2006.285.19:34:10.88#ibcon#wrote, iclass 30, count 0 2006.285.19:34:10.88#ibcon#about to read 3, iclass 30, count 0 2006.285.19:34:10.91#ibcon#read 3, iclass 30, count 0 2006.285.19:34:10.91#ibcon#about to read 4, iclass 30, count 0 2006.285.19:34:10.91#ibcon#read 4, iclass 30, count 0 2006.285.19:34:10.91#ibcon#about to read 5, iclass 30, count 0 2006.285.19:34:10.91#ibcon#read 5, iclass 30, count 0 2006.285.19:34:10.91#ibcon#about to read 6, iclass 30, count 0 2006.285.19:34:10.91#ibcon#read 6, iclass 30, count 0 2006.285.19:34:10.91#ibcon#end of sib2, iclass 30, count 0 2006.285.19:34:10.91#ibcon#*after write, iclass 30, count 0 2006.285.19:34:10.91#ibcon#*before return 0, iclass 30, count 0 2006.285.19:34:10.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:34:10.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:34:10.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.19:34:10.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.19:34:10.91$vck44/vb=1,4 2006.285.19:34:10.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.19:34:10.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.19:34:10.91#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:10.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:34:10.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:34:10.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:34:10.91#ibcon#enter wrdev, iclass 32, count 2 2006.285.19:34:10.91#ibcon#first serial, iclass 32, count 2 2006.285.19:34:10.91#ibcon#enter sib2, iclass 32, count 2 2006.285.19:34:10.91#ibcon#flushed, iclass 32, count 2 2006.285.19:34:10.91#ibcon#about to write, iclass 32, count 2 2006.285.19:34:10.91#ibcon#wrote, iclass 32, count 2 2006.285.19:34:10.91#ibcon#about to read 3, iclass 32, count 2 2006.285.19:34:10.93#ibcon#read 3, iclass 32, count 2 2006.285.19:34:10.93#ibcon#about to read 4, iclass 32, count 2 2006.285.19:34:10.93#ibcon#read 4, iclass 32, count 2 2006.285.19:34:10.93#ibcon#about to read 5, iclass 32, count 2 2006.285.19:34:10.93#ibcon#read 5, iclass 32, count 2 2006.285.19:34:10.93#ibcon#about to read 6, iclass 32, count 2 2006.285.19:34:10.93#ibcon#read 6, iclass 32, count 2 2006.285.19:34:10.93#ibcon#end of sib2, iclass 32, count 2 2006.285.19:34:10.93#ibcon#*mode == 0, iclass 32, count 2 2006.285.19:34:10.93#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.19:34:10.93#ibcon#[27=AT01-04\r\n] 2006.285.19:34:10.93#ibcon#*before write, iclass 32, count 2 2006.285.19:34:10.93#ibcon#enter sib2, iclass 32, count 2 2006.285.19:34:10.93#ibcon#flushed, iclass 32, count 2 2006.285.19:34:10.93#ibcon#about to write, iclass 32, count 2 2006.285.19:34:10.93#ibcon#wrote, iclass 32, count 2 2006.285.19:34:10.93#ibcon#about to read 3, iclass 32, count 2 2006.285.19:34:10.96#ibcon#read 3, iclass 32, count 2 2006.285.19:34:10.96#ibcon#about to read 4, iclass 32, count 2 2006.285.19:34:10.96#ibcon#read 4, iclass 32, count 2 2006.285.19:34:10.96#ibcon#about to read 5, iclass 32, count 2 2006.285.19:34:10.96#ibcon#read 5, iclass 32, count 2 2006.285.19:34:10.96#ibcon#about to read 6, iclass 32, count 2 2006.285.19:34:10.96#ibcon#read 6, iclass 32, count 2 2006.285.19:34:10.96#ibcon#end of sib2, iclass 32, count 2 2006.285.19:34:10.96#ibcon#*after write, iclass 32, count 2 2006.285.19:34:10.96#ibcon#*before return 0, iclass 32, count 2 2006.285.19:34:10.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:34:10.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:34:10.96#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.19:34:10.96#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:10.96#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:34:11.08#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:34:11.08#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:34:11.08#ibcon#enter wrdev, iclass 32, count 0 2006.285.19:34:11.08#ibcon#first serial, iclass 32, count 0 2006.285.19:34:11.08#ibcon#enter sib2, iclass 32, count 0 2006.285.19:34:11.08#ibcon#flushed, iclass 32, count 0 2006.285.19:34:11.08#ibcon#about to write, iclass 32, count 0 2006.285.19:34:11.08#ibcon#wrote, iclass 32, count 0 2006.285.19:34:11.08#ibcon#about to read 3, iclass 32, count 0 2006.285.19:34:11.10#ibcon#read 3, iclass 32, count 0 2006.285.19:34:11.10#ibcon#about to read 4, iclass 32, count 0 2006.285.19:34:11.10#ibcon#read 4, iclass 32, count 0 2006.285.19:34:11.10#ibcon#about to read 5, iclass 32, count 0 2006.285.19:34:11.10#ibcon#read 5, iclass 32, count 0 2006.285.19:34:11.10#ibcon#about to read 6, iclass 32, count 0 2006.285.19:34:11.10#ibcon#read 6, iclass 32, count 0 2006.285.19:34:11.10#ibcon#end of sib2, iclass 32, count 0 2006.285.19:34:11.10#ibcon#*mode == 0, iclass 32, count 0 2006.285.19:34:11.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.19:34:11.10#ibcon#[27=USB\r\n] 2006.285.19:34:11.10#ibcon#*before write, iclass 32, count 0 2006.285.19:34:11.10#ibcon#enter sib2, iclass 32, count 0 2006.285.19:34:11.10#ibcon#flushed, iclass 32, count 0 2006.285.19:34:11.10#ibcon#about to write, iclass 32, count 0 2006.285.19:34:11.10#ibcon#wrote, iclass 32, count 0 2006.285.19:34:11.10#ibcon#about to read 3, iclass 32, count 0 2006.285.19:34:11.13#ibcon#read 3, iclass 32, count 0 2006.285.19:34:11.13#ibcon#about to read 4, iclass 32, count 0 2006.285.19:34:11.13#ibcon#read 4, iclass 32, count 0 2006.285.19:34:11.13#ibcon#about to read 5, iclass 32, count 0 2006.285.19:34:11.13#ibcon#read 5, iclass 32, count 0 2006.285.19:34:11.13#ibcon#about to read 6, iclass 32, count 0 2006.285.19:34:11.13#ibcon#read 6, iclass 32, count 0 2006.285.19:34:11.13#ibcon#end of sib2, iclass 32, count 0 2006.285.19:34:11.13#ibcon#*after write, iclass 32, count 0 2006.285.19:34:11.13#ibcon#*before return 0, iclass 32, count 0 2006.285.19:34:11.13#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:34:11.13#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:34:11.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.19:34:11.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.19:34:11.14$vck44/vblo=2,634.99 2006.285.19:34:11.14#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.19:34:11.14#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.19:34:11.14#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:11.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:34:11.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:34:11.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:34:11.14#ibcon#enter wrdev, iclass 34, count 0 2006.285.19:34:11.14#ibcon#first serial, iclass 34, count 0 2006.285.19:34:11.14#ibcon#enter sib2, iclass 34, count 0 2006.285.19:34:11.14#ibcon#flushed, iclass 34, count 0 2006.285.19:34:11.14#ibcon#about to write, iclass 34, count 0 2006.285.19:34:11.14#ibcon#wrote, iclass 34, count 0 2006.285.19:34:11.14#ibcon#about to read 3, iclass 34, count 0 2006.285.19:34:11.15#ibcon#read 3, iclass 34, count 0 2006.285.19:34:11.15#ibcon#about to read 4, iclass 34, count 0 2006.285.19:34:11.15#ibcon#read 4, iclass 34, count 0 2006.285.19:34:11.15#ibcon#about to read 5, iclass 34, count 0 2006.285.19:34:11.15#ibcon#read 5, iclass 34, count 0 2006.285.19:34:11.15#ibcon#about to read 6, iclass 34, count 0 2006.285.19:34:11.15#ibcon#read 6, iclass 34, count 0 2006.285.19:34:11.15#ibcon#end of sib2, iclass 34, count 0 2006.285.19:34:11.15#ibcon#*mode == 0, iclass 34, count 0 2006.285.19:34:11.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.19:34:11.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.19:34:11.15#ibcon#*before write, iclass 34, count 0 2006.285.19:34:11.15#ibcon#enter sib2, iclass 34, count 0 2006.285.19:34:11.15#ibcon#flushed, iclass 34, count 0 2006.285.19:34:11.15#ibcon#about to write, iclass 34, count 0 2006.285.19:34:11.15#ibcon#wrote, iclass 34, count 0 2006.285.19:34:11.15#ibcon#about to read 3, iclass 34, count 0 2006.285.19:34:11.19#ibcon#read 3, iclass 34, count 0 2006.285.19:34:11.19#ibcon#about to read 4, iclass 34, count 0 2006.285.19:34:11.19#ibcon#read 4, iclass 34, count 0 2006.285.19:34:11.19#ibcon#about to read 5, iclass 34, count 0 2006.285.19:34:11.19#ibcon#read 5, iclass 34, count 0 2006.285.19:34:11.19#ibcon#about to read 6, iclass 34, count 0 2006.285.19:34:11.19#ibcon#read 6, iclass 34, count 0 2006.285.19:34:11.19#ibcon#end of sib2, iclass 34, count 0 2006.285.19:34:11.19#ibcon#*after write, iclass 34, count 0 2006.285.19:34:11.19#ibcon#*before return 0, iclass 34, count 0 2006.285.19:34:11.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:34:11.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:34:11.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.19:34:11.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.19:34:11.19$vck44/vb=2,5 2006.285.19:34:11.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.19:34:11.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.19:34:11.19#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:11.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:34:11.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:34:11.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:34:11.25#ibcon#enter wrdev, iclass 36, count 2 2006.285.19:34:11.25#ibcon#first serial, iclass 36, count 2 2006.285.19:34:11.25#ibcon#enter sib2, iclass 36, count 2 2006.285.19:34:11.25#ibcon#flushed, iclass 36, count 2 2006.285.19:34:11.25#ibcon#about to write, iclass 36, count 2 2006.285.19:34:11.25#ibcon#wrote, iclass 36, count 2 2006.285.19:34:11.25#ibcon#about to read 3, iclass 36, count 2 2006.285.19:34:11.27#ibcon#read 3, iclass 36, count 2 2006.285.19:34:11.27#ibcon#about to read 4, iclass 36, count 2 2006.285.19:34:11.27#ibcon#read 4, iclass 36, count 2 2006.285.19:34:11.27#ibcon#about to read 5, iclass 36, count 2 2006.285.19:34:11.27#ibcon#read 5, iclass 36, count 2 2006.285.19:34:11.27#ibcon#about to read 6, iclass 36, count 2 2006.285.19:34:11.27#ibcon#read 6, iclass 36, count 2 2006.285.19:34:11.27#ibcon#end of sib2, iclass 36, count 2 2006.285.19:34:11.27#ibcon#*mode == 0, iclass 36, count 2 2006.285.19:34:11.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.19:34:11.27#ibcon#[27=AT02-05\r\n] 2006.285.19:34:11.27#ibcon#*before write, iclass 36, count 2 2006.285.19:34:11.27#ibcon#enter sib2, iclass 36, count 2 2006.285.19:34:11.27#ibcon#flushed, iclass 36, count 2 2006.285.19:34:11.27#ibcon#about to write, iclass 36, count 2 2006.285.19:34:11.27#ibcon#wrote, iclass 36, count 2 2006.285.19:34:11.27#ibcon#about to read 3, iclass 36, count 2 2006.285.19:34:11.30#ibcon#read 3, iclass 36, count 2 2006.285.19:34:11.30#ibcon#about to read 4, iclass 36, count 2 2006.285.19:34:11.30#ibcon#read 4, iclass 36, count 2 2006.285.19:34:11.30#ibcon#about to read 5, iclass 36, count 2 2006.285.19:34:11.30#ibcon#read 5, iclass 36, count 2 2006.285.19:34:11.30#ibcon#about to read 6, iclass 36, count 2 2006.285.19:34:11.30#ibcon#read 6, iclass 36, count 2 2006.285.19:34:11.30#ibcon#end of sib2, iclass 36, count 2 2006.285.19:34:11.30#ibcon#*after write, iclass 36, count 2 2006.285.19:34:11.30#ibcon#*before return 0, iclass 36, count 2 2006.285.19:34:11.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:34:11.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:34:11.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.19:34:11.30#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:11.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:34:11.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:34:11.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:34:11.42#ibcon#enter wrdev, iclass 36, count 0 2006.285.19:34:11.42#ibcon#first serial, iclass 36, count 0 2006.285.19:34:11.42#ibcon#enter sib2, iclass 36, count 0 2006.285.19:34:11.42#ibcon#flushed, iclass 36, count 0 2006.285.19:34:11.42#ibcon#about to write, iclass 36, count 0 2006.285.19:34:11.42#ibcon#wrote, iclass 36, count 0 2006.285.19:34:11.42#ibcon#about to read 3, iclass 36, count 0 2006.285.19:34:11.44#ibcon#read 3, iclass 36, count 0 2006.285.19:34:11.44#ibcon#about to read 4, iclass 36, count 0 2006.285.19:34:11.44#ibcon#read 4, iclass 36, count 0 2006.285.19:34:11.44#ibcon#about to read 5, iclass 36, count 0 2006.285.19:34:11.44#ibcon#read 5, iclass 36, count 0 2006.285.19:34:11.44#ibcon#about to read 6, iclass 36, count 0 2006.285.19:34:11.44#ibcon#read 6, iclass 36, count 0 2006.285.19:34:11.44#ibcon#end of sib2, iclass 36, count 0 2006.285.19:34:11.44#ibcon#*mode == 0, iclass 36, count 0 2006.285.19:34:11.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.19:34:11.44#ibcon#[27=USB\r\n] 2006.285.19:34:11.44#ibcon#*before write, iclass 36, count 0 2006.285.19:34:11.44#ibcon#enter sib2, iclass 36, count 0 2006.285.19:34:11.44#ibcon#flushed, iclass 36, count 0 2006.285.19:34:11.44#ibcon#about to write, iclass 36, count 0 2006.285.19:34:11.44#ibcon#wrote, iclass 36, count 0 2006.285.19:34:11.44#ibcon#about to read 3, iclass 36, count 0 2006.285.19:34:11.47#ibcon#read 3, iclass 36, count 0 2006.285.19:34:11.47#ibcon#about to read 4, iclass 36, count 0 2006.285.19:34:11.47#ibcon#read 4, iclass 36, count 0 2006.285.19:34:11.47#ibcon#about to read 5, iclass 36, count 0 2006.285.19:34:11.47#ibcon#read 5, iclass 36, count 0 2006.285.19:34:11.47#ibcon#about to read 6, iclass 36, count 0 2006.285.19:34:11.47#ibcon#read 6, iclass 36, count 0 2006.285.19:34:11.47#ibcon#end of sib2, iclass 36, count 0 2006.285.19:34:11.47#ibcon#*after write, iclass 36, count 0 2006.285.19:34:11.47#ibcon#*before return 0, iclass 36, count 0 2006.285.19:34:11.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:34:11.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:34:11.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.19:34:11.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.19:34:11.47$vck44/vblo=3,649.99 2006.285.19:34:11.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.19:34:11.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.19:34:11.47#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:11.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:34:11.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:34:11.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:34:11.47#ibcon#enter wrdev, iclass 38, count 0 2006.285.19:34:11.47#ibcon#first serial, iclass 38, count 0 2006.285.19:34:11.47#ibcon#enter sib2, iclass 38, count 0 2006.285.19:34:11.47#ibcon#flushed, iclass 38, count 0 2006.285.19:34:11.47#ibcon#about to write, iclass 38, count 0 2006.285.19:34:11.47#ibcon#wrote, iclass 38, count 0 2006.285.19:34:11.47#ibcon#about to read 3, iclass 38, count 0 2006.285.19:34:11.49#ibcon#read 3, iclass 38, count 0 2006.285.19:34:11.49#ibcon#about to read 4, iclass 38, count 0 2006.285.19:34:11.49#ibcon#read 4, iclass 38, count 0 2006.285.19:34:11.49#ibcon#about to read 5, iclass 38, count 0 2006.285.19:34:11.49#ibcon#read 5, iclass 38, count 0 2006.285.19:34:11.49#ibcon#about to read 6, iclass 38, count 0 2006.285.19:34:11.49#ibcon#read 6, iclass 38, count 0 2006.285.19:34:11.49#ibcon#end of sib2, iclass 38, count 0 2006.285.19:34:11.49#ibcon#*mode == 0, iclass 38, count 0 2006.285.19:34:11.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.19:34:11.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.19:34:11.49#ibcon#*before write, iclass 38, count 0 2006.285.19:34:11.49#ibcon#enter sib2, iclass 38, count 0 2006.285.19:34:11.49#ibcon#flushed, iclass 38, count 0 2006.285.19:34:11.49#ibcon#about to write, iclass 38, count 0 2006.285.19:34:11.49#ibcon#wrote, iclass 38, count 0 2006.285.19:34:11.49#ibcon#about to read 3, iclass 38, count 0 2006.285.19:34:11.53#ibcon#read 3, iclass 38, count 0 2006.285.19:34:11.53#ibcon#about to read 4, iclass 38, count 0 2006.285.19:34:11.53#ibcon#read 4, iclass 38, count 0 2006.285.19:34:11.53#ibcon#about to read 5, iclass 38, count 0 2006.285.19:34:11.53#ibcon#read 5, iclass 38, count 0 2006.285.19:34:11.53#ibcon#about to read 6, iclass 38, count 0 2006.285.19:34:11.53#ibcon#read 6, iclass 38, count 0 2006.285.19:34:11.53#ibcon#end of sib2, iclass 38, count 0 2006.285.19:34:11.53#ibcon#*after write, iclass 38, count 0 2006.285.19:34:11.53#ibcon#*before return 0, iclass 38, count 0 2006.285.19:34:11.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:34:11.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:34:11.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.19:34:11.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.19:34:11.53$vck44/vb=3,4 2006.285.19:34:11.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.19:34:11.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.19:34:11.53#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:11.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:34:11.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:34:11.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:34:11.59#ibcon#enter wrdev, iclass 40, count 2 2006.285.19:34:11.59#ibcon#first serial, iclass 40, count 2 2006.285.19:34:11.59#ibcon#enter sib2, iclass 40, count 2 2006.285.19:34:11.59#ibcon#flushed, iclass 40, count 2 2006.285.19:34:11.59#ibcon#about to write, iclass 40, count 2 2006.285.19:34:11.59#ibcon#wrote, iclass 40, count 2 2006.285.19:34:11.59#ibcon#about to read 3, iclass 40, count 2 2006.285.19:34:11.61#ibcon#read 3, iclass 40, count 2 2006.285.19:34:11.61#ibcon#about to read 4, iclass 40, count 2 2006.285.19:34:11.61#ibcon#read 4, iclass 40, count 2 2006.285.19:34:11.61#ibcon#about to read 5, iclass 40, count 2 2006.285.19:34:11.61#ibcon#read 5, iclass 40, count 2 2006.285.19:34:11.61#ibcon#about to read 6, iclass 40, count 2 2006.285.19:34:11.61#ibcon#read 6, iclass 40, count 2 2006.285.19:34:11.61#ibcon#end of sib2, iclass 40, count 2 2006.285.19:34:11.61#ibcon#*mode == 0, iclass 40, count 2 2006.285.19:34:11.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.19:34:11.61#ibcon#[27=AT03-04\r\n] 2006.285.19:34:11.61#ibcon#*before write, iclass 40, count 2 2006.285.19:34:11.61#ibcon#enter sib2, iclass 40, count 2 2006.285.19:34:11.61#ibcon#flushed, iclass 40, count 2 2006.285.19:34:11.61#ibcon#about to write, iclass 40, count 2 2006.285.19:34:11.61#ibcon#wrote, iclass 40, count 2 2006.285.19:34:11.61#ibcon#about to read 3, iclass 40, count 2 2006.285.19:34:11.64#ibcon#read 3, iclass 40, count 2 2006.285.19:34:11.64#ibcon#about to read 4, iclass 40, count 2 2006.285.19:34:11.64#ibcon#read 4, iclass 40, count 2 2006.285.19:34:11.64#ibcon#about to read 5, iclass 40, count 2 2006.285.19:34:11.64#ibcon#read 5, iclass 40, count 2 2006.285.19:34:11.64#ibcon#about to read 6, iclass 40, count 2 2006.285.19:34:11.64#ibcon#read 6, iclass 40, count 2 2006.285.19:34:11.64#ibcon#end of sib2, iclass 40, count 2 2006.285.19:34:11.64#ibcon#*after write, iclass 40, count 2 2006.285.19:34:11.64#ibcon#*before return 0, iclass 40, count 2 2006.285.19:34:11.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:34:11.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:34:11.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.19:34:11.64#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:11.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:34:11.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:34:11.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:34:11.76#ibcon#enter wrdev, iclass 40, count 0 2006.285.19:34:11.76#ibcon#first serial, iclass 40, count 0 2006.285.19:34:11.76#ibcon#enter sib2, iclass 40, count 0 2006.285.19:34:11.76#ibcon#flushed, iclass 40, count 0 2006.285.19:34:11.76#ibcon#about to write, iclass 40, count 0 2006.285.19:34:11.76#ibcon#wrote, iclass 40, count 0 2006.285.19:34:11.76#ibcon#about to read 3, iclass 40, count 0 2006.285.19:34:11.78#ibcon#read 3, iclass 40, count 0 2006.285.19:34:11.78#ibcon#about to read 4, iclass 40, count 0 2006.285.19:34:11.78#ibcon#read 4, iclass 40, count 0 2006.285.19:34:11.78#ibcon#about to read 5, iclass 40, count 0 2006.285.19:34:11.78#ibcon#read 5, iclass 40, count 0 2006.285.19:34:11.78#ibcon#about to read 6, iclass 40, count 0 2006.285.19:34:11.78#ibcon#read 6, iclass 40, count 0 2006.285.19:34:11.78#ibcon#end of sib2, iclass 40, count 0 2006.285.19:34:11.78#ibcon#*mode == 0, iclass 40, count 0 2006.285.19:34:11.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.19:34:11.78#ibcon#[27=USB\r\n] 2006.285.19:34:11.78#ibcon#*before write, iclass 40, count 0 2006.285.19:34:11.78#ibcon#enter sib2, iclass 40, count 0 2006.285.19:34:11.78#ibcon#flushed, iclass 40, count 0 2006.285.19:34:11.78#ibcon#about to write, iclass 40, count 0 2006.285.19:34:11.78#ibcon#wrote, iclass 40, count 0 2006.285.19:34:11.78#ibcon#about to read 3, iclass 40, count 0 2006.285.19:34:11.81#ibcon#read 3, iclass 40, count 0 2006.285.19:34:11.81#ibcon#about to read 4, iclass 40, count 0 2006.285.19:34:11.81#ibcon#read 4, iclass 40, count 0 2006.285.19:34:11.81#ibcon#about to read 5, iclass 40, count 0 2006.285.19:34:11.81#ibcon#read 5, iclass 40, count 0 2006.285.19:34:11.81#ibcon#about to read 6, iclass 40, count 0 2006.285.19:34:11.81#ibcon#read 6, iclass 40, count 0 2006.285.19:34:11.81#ibcon#end of sib2, iclass 40, count 0 2006.285.19:34:11.81#ibcon#*after write, iclass 40, count 0 2006.285.19:34:11.81#ibcon#*before return 0, iclass 40, count 0 2006.285.19:34:11.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:34:11.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:34:11.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.19:34:11.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.19:34:11.81$vck44/vblo=4,679.99 2006.285.19:34:11.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.19:34:11.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.19:34:11.81#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:11.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:34:11.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:34:11.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:34:11.81#ibcon#enter wrdev, iclass 4, count 0 2006.285.19:34:11.81#ibcon#first serial, iclass 4, count 0 2006.285.19:34:11.81#ibcon#enter sib2, iclass 4, count 0 2006.285.19:34:11.81#ibcon#flushed, iclass 4, count 0 2006.285.19:34:11.81#ibcon#about to write, iclass 4, count 0 2006.285.19:34:11.81#ibcon#wrote, iclass 4, count 0 2006.285.19:34:11.81#ibcon#about to read 3, iclass 4, count 0 2006.285.19:34:11.83#ibcon#read 3, iclass 4, count 0 2006.285.19:34:11.94#ibcon#about to read 4, iclass 4, count 0 2006.285.19:34:11.94#ibcon#read 4, iclass 4, count 0 2006.285.19:34:11.94#ibcon#about to read 5, iclass 4, count 0 2006.285.19:34:11.94#ibcon#read 5, iclass 4, count 0 2006.285.19:34:11.94#ibcon#about to read 6, iclass 4, count 0 2006.285.19:34:11.94#ibcon#read 6, iclass 4, count 0 2006.285.19:34:11.94#ibcon#end of sib2, iclass 4, count 0 2006.285.19:34:11.94#ibcon#*mode == 0, iclass 4, count 0 2006.285.19:34:11.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.19:34:11.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.19:34:11.94#ibcon#*before write, iclass 4, count 0 2006.285.19:34:11.94#ibcon#enter sib2, iclass 4, count 0 2006.285.19:34:11.94#ibcon#flushed, iclass 4, count 0 2006.285.19:34:11.94#ibcon#about to write, iclass 4, count 0 2006.285.19:34:11.94#ibcon#wrote, iclass 4, count 0 2006.285.19:34:11.94#ibcon#about to read 3, iclass 4, count 0 2006.285.19:34:11.97#ibcon#read 3, iclass 4, count 0 2006.285.19:34:11.97#ibcon#about to read 4, iclass 4, count 0 2006.285.19:34:11.97#ibcon#read 4, iclass 4, count 0 2006.285.19:34:11.97#ibcon#about to read 5, iclass 4, count 0 2006.285.19:34:11.97#ibcon#read 5, iclass 4, count 0 2006.285.19:34:11.97#ibcon#about to read 6, iclass 4, count 0 2006.285.19:34:11.97#ibcon#read 6, iclass 4, count 0 2006.285.19:34:11.97#ibcon#end of sib2, iclass 4, count 0 2006.285.19:34:11.97#ibcon#*after write, iclass 4, count 0 2006.285.19:34:11.97#ibcon#*before return 0, iclass 4, count 0 2006.285.19:34:11.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:34:11.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:34:11.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.19:34:11.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.19:34:11.97$vck44/vb=4,5 2006.285.19:34:11.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.19:34:11.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.19:34:11.97#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:11.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:34:11.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:34:11.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:34:11.97#ibcon#enter wrdev, iclass 6, count 2 2006.285.19:34:11.97#ibcon#first serial, iclass 6, count 2 2006.285.19:34:11.97#ibcon#enter sib2, iclass 6, count 2 2006.285.19:34:11.97#ibcon#flushed, iclass 6, count 2 2006.285.19:34:11.97#ibcon#about to write, iclass 6, count 2 2006.285.19:34:11.97#ibcon#wrote, iclass 6, count 2 2006.285.19:34:11.97#ibcon#about to read 3, iclass 6, count 2 2006.285.19:34:11.99#ibcon#read 3, iclass 6, count 2 2006.285.19:34:11.99#ibcon#about to read 4, iclass 6, count 2 2006.285.19:34:11.99#ibcon#read 4, iclass 6, count 2 2006.285.19:34:11.99#ibcon#about to read 5, iclass 6, count 2 2006.285.19:34:11.99#ibcon#read 5, iclass 6, count 2 2006.285.19:34:11.99#ibcon#about to read 6, iclass 6, count 2 2006.285.19:34:11.99#ibcon#read 6, iclass 6, count 2 2006.285.19:34:11.99#ibcon#end of sib2, iclass 6, count 2 2006.285.19:34:11.99#ibcon#*mode == 0, iclass 6, count 2 2006.285.19:34:11.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.19:34:11.99#ibcon#[27=AT04-05\r\n] 2006.285.19:34:11.99#ibcon#*before write, iclass 6, count 2 2006.285.19:34:11.99#ibcon#enter sib2, iclass 6, count 2 2006.285.19:34:11.99#ibcon#flushed, iclass 6, count 2 2006.285.19:34:11.99#ibcon#about to write, iclass 6, count 2 2006.285.19:34:11.99#ibcon#wrote, iclass 6, count 2 2006.285.19:34:11.99#ibcon#about to read 3, iclass 6, count 2 2006.285.19:34:12.02#ibcon#read 3, iclass 6, count 2 2006.285.19:34:12.02#ibcon#about to read 4, iclass 6, count 2 2006.285.19:34:12.02#ibcon#read 4, iclass 6, count 2 2006.285.19:34:12.02#ibcon#about to read 5, iclass 6, count 2 2006.285.19:34:12.02#ibcon#read 5, iclass 6, count 2 2006.285.19:34:12.02#ibcon#about to read 6, iclass 6, count 2 2006.285.19:34:12.02#ibcon#read 6, iclass 6, count 2 2006.285.19:34:12.02#ibcon#end of sib2, iclass 6, count 2 2006.285.19:34:12.02#ibcon#*after write, iclass 6, count 2 2006.285.19:34:12.02#ibcon#*before return 0, iclass 6, count 2 2006.285.19:34:12.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:34:12.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:34:12.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.19:34:12.02#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:12.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:34:12.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:34:12.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:34:12.14#ibcon#enter wrdev, iclass 6, count 0 2006.285.19:34:12.14#ibcon#first serial, iclass 6, count 0 2006.285.19:34:12.14#ibcon#enter sib2, iclass 6, count 0 2006.285.19:34:12.14#ibcon#flushed, iclass 6, count 0 2006.285.19:34:12.14#ibcon#about to write, iclass 6, count 0 2006.285.19:34:12.14#ibcon#wrote, iclass 6, count 0 2006.285.19:34:12.14#ibcon#about to read 3, iclass 6, count 0 2006.285.19:34:12.16#ibcon#read 3, iclass 6, count 0 2006.285.19:34:12.16#ibcon#about to read 4, iclass 6, count 0 2006.285.19:34:12.16#ibcon#read 4, iclass 6, count 0 2006.285.19:34:12.16#ibcon#about to read 5, iclass 6, count 0 2006.285.19:34:12.16#ibcon#read 5, iclass 6, count 0 2006.285.19:34:12.16#ibcon#about to read 6, iclass 6, count 0 2006.285.19:34:12.16#ibcon#read 6, iclass 6, count 0 2006.285.19:34:12.16#ibcon#end of sib2, iclass 6, count 0 2006.285.19:34:12.16#ibcon#*mode == 0, iclass 6, count 0 2006.285.19:34:12.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.19:34:12.16#ibcon#[27=USB\r\n] 2006.285.19:34:12.16#ibcon#*before write, iclass 6, count 0 2006.285.19:34:12.16#ibcon#enter sib2, iclass 6, count 0 2006.285.19:34:12.16#ibcon#flushed, iclass 6, count 0 2006.285.19:34:12.16#ibcon#about to write, iclass 6, count 0 2006.285.19:34:12.16#ibcon#wrote, iclass 6, count 0 2006.285.19:34:12.16#ibcon#about to read 3, iclass 6, count 0 2006.285.19:34:12.19#ibcon#read 3, iclass 6, count 0 2006.285.19:34:12.19#ibcon#about to read 4, iclass 6, count 0 2006.285.19:34:12.19#ibcon#read 4, iclass 6, count 0 2006.285.19:34:12.19#ibcon#about to read 5, iclass 6, count 0 2006.285.19:34:12.19#ibcon#read 5, iclass 6, count 0 2006.285.19:34:12.19#ibcon#about to read 6, iclass 6, count 0 2006.285.19:34:12.19#ibcon#read 6, iclass 6, count 0 2006.285.19:34:12.19#ibcon#end of sib2, iclass 6, count 0 2006.285.19:34:12.19#ibcon#*after write, iclass 6, count 0 2006.285.19:34:12.19#ibcon#*before return 0, iclass 6, count 0 2006.285.19:34:12.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:34:12.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:34:12.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.19:34:12.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.19:34:12.19$vck44/vblo=5,709.99 2006.285.19:34:12.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.19:34:12.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.19:34:12.19#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:12.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:34:12.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:34:12.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:34:12.19#ibcon#enter wrdev, iclass 10, count 0 2006.285.19:34:12.19#ibcon#first serial, iclass 10, count 0 2006.285.19:34:12.19#ibcon#enter sib2, iclass 10, count 0 2006.285.19:34:12.19#ibcon#flushed, iclass 10, count 0 2006.285.19:34:12.19#ibcon#about to write, iclass 10, count 0 2006.285.19:34:12.19#ibcon#wrote, iclass 10, count 0 2006.285.19:34:12.19#ibcon#about to read 3, iclass 10, count 0 2006.285.19:34:12.21#ibcon#read 3, iclass 10, count 0 2006.285.19:34:12.21#ibcon#about to read 4, iclass 10, count 0 2006.285.19:34:12.21#ibcon#read 4, iclass 10, count 0 2006.285.19:34:12.21#ibcon#about to read 5, iclass 10, count 0 2006.285.19:34:12.21#ibcon#read 5, iclass 10, count 0 2006.285.19:34:12.21#ibcon#about to read 6, iclass 10, count 0 2006.285.19:34:12.21#ibcon#read 6, iclass 10, count 0 2006.285.19:34:12.21#ibcon#end of sib2, iclass 10, count 0 2006.285.19:34:12.21#ibcon#*mode == 0, iclass 10, count 0 2006.285.19:34:12.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.19:34:12.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.19:34:12.21#ibcon#*before write, iclass 10, count 0 2006.285.19:34:12.21#ibcon#enter sib2, iclass 10, count 0 2006.285.19:34:12.21#ibcon#flushed, iclass 10, count 0 2006.285.19:34:12.21#ibcon#about to write, iclass 10, count 0 2006.285.19:34:12.21#ibcon#wrote, iclass 10, count 0 2006.285.19:34:12.21#ibcon#about to read 3, iclass 10, count 0 2006.285.19:34:12.25#ibcon#read 3, iclass 10, count 0 2006.285.19:34:12.25#ibcon#about to read 4, iclass 10, count 0 2006.285.19:34:12.25#ibcon#read 4, iclass 10, count 0 2006.285.19:34:12.25#ibcon#about to read 5, iclass 10, count 0 2006.285.19:34:12.25#ibcon#read 5, iclass 10, count 0 2006.285.19:34:12.25#ibcon#about to read 6, iclass 10, count 0 2006.285.19:34:12.25#ibcon#read 6, iclass 10, count 0 2006.285.19:34:12.25#ibcon#end of sib2, iclass 10, count 0 2006.285.19:34:12.25#ibcon#*after write, iclass 10, count 0 2006.285.19:34:12.25#ibcon#*before return 0, iclass 10, count 0 2006.285.19:34:12.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:34:12.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:34:12.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.19:34:12.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.19:34:12.25$vck44/vb=5,4 2006.285.19:34:12.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.19:34:12.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.19:34:12.25#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:12.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:34:12.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:34:12.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:34:12.31#ibcon#enter wrdev, iclass 12, count 2 2006.285.19:34:12.31#ibcon#first serial, iclass 12, count 2 2006.285.19:34:12.31#ibcon#enter sib2, iclass 12, count 2 2006.285.19:34:12.31#ibcon#flushed, iclass 12, count 2 2006.285.19:34:12.31#ibcon#about to write, iclass 12, count 2 2006.285.19:34:12.31#ibcon#wrote, iclass 12, count 2 2006.285.19:34:12.31#ibcon#about to read 3, iclass 12, count 2 2006.285.19:34:12.33#ibcon#read 3, iclass 12, count 2 2006.285.19:34:12.33#ibcon#about to read 4, iclass 12, count 2 2006.285.19:34:12.33#ibcon#read 4, iclass 12, count 2 2006.285.19:34:12.33#ibcon#about to read 5, iclass 12, count 2 2006.285.19:34:12.33#ibcon#read 5, iclass 12, count 2 2006.285.19:34:12.33#ibcon#about to read 6, iclass 12, count 2 2006.285.19:34:12.33#ibcon#read 6, iclass 12, count 2 2006.285.19:34:12.33#ibcon#end of sib2, iclass 12, count 2 2006.285.19:34:12.33#ibcon#*mode == 0, iclass 12, count 2 2006.285.19:34:12.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.19:34:12.33#ibcon#[27=AT05-04\r\n] 2006.285.19:34:12.33#ibcon#*before write, iclass 12, count 2 2006.285.19:34:12.33#ibcon#enter sib2, iclass 12, count 2 2006.285.19:34:12.33#ibcon#flushed, iclass 12, count 2 2006.285.19:34:12.33#ibcon#about to write, iclass 12, count 2 2006.285.19:34:12.33#ibcon#wrote, iclass 12, count 2 2006.285.19:34:12.33#ibcon#about to read 3, iclass 12, count 2 2006.285.19:34:12.36#ibcon#read 3, iclass 12, count 2 2006.285.19:34:12.36#ibcon#about to read 4, iclass 12, count 2 2006.285.19:34:12.36#ibcon#read 4, iclass 12, count 2 2006.285.19:34:12.36#ibcon#about to read 5, iclass 12, count 2 2006.285.19:34:12.36#ibcon#read 5, iclass 12, count 2 2006.285.19:34:12.36#ibcon#about to read 6, iclass 12, count 2 2006.285.19:34:12.36#ibcon#read 6, iclass 12, count 2 2006.285.19:34:12.36#ibcon#end of sib2, iclass 12, count 2 2006.285.19:34:12.36#ibcon#*after write, iclass 12, count 2 2006.285.19:34:12.36#ibcon#*before return 0, iclass 12, count 2 2006.285.19:34:12.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:34:12.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:34:12.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.19:34:12.36#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:12.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:34:12.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:34:12.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:34:12.48#ibcon#enter wrdev, iclass 12, count 0 2006.285.19:34:12.48#ibcon#first serial, iclass 12, count 0 2006.285.19:34:12.48#ibcon#enter sib2, iclass 12, count 0 2006.285.19:34:12.48#ibcon#flushed, iclass 12, count 0 2006.285.19:34:12.48#ibcon#about to write, iclass 12, count 0 2006.285.19:34:12.48#ibcon#wrote, iclass 12, count 0 2006.285.19:34:12.48#ibcon#about to read 3, iclass 12, count 0 2006.285.19:34:12.50#ibcon#read 3, iclass 12, count 0 2006.285.19:34:12.50#ibcon#about to read 4, iclass 12, count 0 2006.285.19:34:12.50#ibcon#read 4, iclass 12, count 0 2006.285.19:34:12.50#ibcon#about to read 5, iclass 12, count 0 2006.285.19:34:12.50#ibcon#read 5, iclass 12, count 0 2006.285.19:34:12.50#ibcon#about to read 6, iclass 12, count 0 2006.285.19:34:12.50#ibcon#read 6, iclass 12, count 0 2006.285.19:34:12.50#ibcon#end of sib2, iclass 12, count 0 2006.285.19:34:12.50#ibcon#*mode == 0, iclass 12, count 0 2006.285.19:34:12.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.19:34:12.50#ibcon#[27=USB\r\n] 2006.285.19:34:12.50#ibcon#*before write, iclass 12, count 0 2006.285.19:34:12.50#ibcon#enter sib2, iclass 12, count 0 2006.285.19:34:12.50#ibcon#flushed, iclass 12, count 0 2006.285.19:34:12.50#ibcon#about to write, iclass 12, count 0 2006.285.19:34:12.50#ibcon#wrote, iclass 12, count 0 2006.285.19:34:12.50#ibcon#about to read 3, iclass 12, count 0 2006.285.19:34:12.53#ibcon#read 3, iclass 12, count 0 2006.285.19:34:12.53#ibcon#about to read 4, iclass 12, count 0 2006.285.19:34:12.53#ibcon#read 4, iclass 12, count 0 2006.285.19:34:12.53#ibcon#about to read 5, iclass 12, count 0 2006.285.19:34:12.53#ibcon#read 5, iclass 12, count 0 2006.285.19:34:12.53#ibcon#about to read 6, iclass 12, count 0 2006.285.19:34:12.53#ibcon#read 6, iclass 12, count 0 2006.285.19:34:12.53#ibcon#end of sib2, iclass 12, count 0 2006.285.19:34:12.53#ibcon#*after write, iclass 12, count 0 2006.285.19:34:12.53#ibcon#*before return 0, iclass 12, count 0 2006.285.19:34:12.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:34:12.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:34:12.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.19:34:12.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.19:34:12.53$vck44/vblo=6,719.99 2006.285.19:34:12.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.19:34:12.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.19:34:12.53#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:12.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:34:12.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:34:12.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:34:12.53#ibcon#enter wrdev, iclass 14, count 0 2006.285.19:34:12.53#ibcon#first serial, iclass 14, count 0 2006.285.19:34:12.53#ibcon#enter sib2, iclass 14, count 0 2006.285.19:34:12.53#ibcon#flushed, iclass 14, count 0 2006.285.19:34:12.53#ibcon#about to write, iclass 14, count 0 2006.285.19:34:12.53#ibcon#wrote, iclass 14, count 0 2006.285.19:34:12.53#ibcon#about to read 3, iclass 14, count 0 2006.285.19:34:12.55#ibcon#read 3, iclass 14, count 0 2006.285.19:34:12.55#ibcon#about to read 4, iclass 14, count 0 2006.285.19:34:12.55#ibcon#read 4, iclass 14, count 0 2006.285.19:34:12.55#ibcon#about to read 5, iclass 14, count 0 2006.285.19:34:12.55#ibcon#read 5, iclass 14, count 0 2006.285.19:34:12.55#ibcon#about to read 6, iclass 14, count 0 2006.285.19:34:12.55#ibcon#read 6, iclass 14, count 0 2006.285.19:34:12.55#ibcon#end of sib2, iclass 14, count 0 2006.285.19:34:12.55#ibcon#*mode == 0, iclass 14, count 0 2006.285.19:34:12.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.19:34:12.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.19:34:12.55#ibcon#*before write, iclass 14, count 0 2006.285.19:34:12.55#ibcon#enter sib2, iclass 14, count 0 2006.285.19:34:12.55#ibcon#flushed, iclass 14, count 0 2006.285.19:34:12.55#ibcon#about to write, iclass 14, count 0 2006.285.19:34:12.55#ibcon#wrote, iclass 14, count 0 2006.285.19:34:12.55#ibcon#about to read 3, iclass 14, count 0 2006.285.19:34:12.59#ibcon#read 3, iclass 14, count 0 2006.285.19:34:12.59#ibcon#about to read 4, iclass 14, count 0 2006.285.19:34:12.59#ibcon#read 4, iclass 14, count 0 2006.285.19:34:12.59#ibcon#about to read 5, iclass 14, count 0 2006.285.19:34:12.59#ibcon#read 5, iclass 14, count 0 2006.285.19:34:12.59#ibcon#about to read 6, iclass 14, count 0 2006.285.19:34:12.59#ibcon#read 6, iclass 14, count 0 2006.285.19:34:12.59#ibcon#end of sib2, iclass 14, count 0 2006.285.19:34:12.59#ibcon#*after write, iclass 14, count 0 2006.285.19:34:12.59#ibcon#*before return 0, iclass 14, count 0 2006.285.19:34:12.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:34:12.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:34:12.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.19:34:12.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.19:34:12.59$vck44/vb=6,3 2006.285.19:34:12.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.19:34:12.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.19:34:12.59#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:12.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:34:12.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:34:12.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:34:12.65#ibcon#enter wrdev, iclass 16, count 2 2006.285.19:34:12.65#ibcon#first serial, iclass 16, count 2 2006.285.19:34:12.65#ibcon#enter sib2, iclass 16, count 2 2006.285.19:34:12.65#ibcon#flushed, iclass 16, count 2 2006.285.19:34:12.65#ibcon#about to write, iclass 16, count 2 2006.285.19:34:12.65#ibcon#wrote, iclass 16, count 2 2006.285.19:34:12.65#ibcon#about to read 3, iclass 16, count 2 2006.285.19:34:12.67#ibcon#read 3, iclass 16, count 2 2006.285.19:34:12.67#ibcon#about to read 4, iclass 16, count 2 2006.285.19:34:12.67#ibcon#read 4, iclass 16, count 2 2006.285.19:34:12.67#ibcon#about to read 5, iclass 16, count 2 2006.285.19:34:12.67#ibcon#read 5, iclass 16, count 2 2006.285.19:34:12.67#ibcon#about to read 6, iclass 16, count 2 2006.285.19:34:12.67#ibcon#read 6, iclass 16, count 2 2006.285.19:34:12.67#ibcon#end of sib2, iclass 16, count 2 2006.285.19:34:12.67#ibcon#*mode == 0, iclass 16, count 2 2006.285.19:34:12.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.19:34:12.67#ibcon#[27=AT06-03\r\n] 2006.285.19:34:12.67#ibcon#*before write, iclass 16, count 2 2006.285.19:34:12.67#ibcon#enter sib2, iclass 16, count 2 2006.285.19:34:12.67#ibcon#flushed, iclass 16, count 2 2006.285.19:34:12.67#ibcon#about to write, iclass 16, count 2 2006.285.19:34:12.67#ibcon#wrote, iclass 16, count 2 2006.285.19:34:12.67#ibcon#about to read 3, iclass 16, count 2 2006.285.19:34:12.70#ibcon#read 3, iclass 16, count 2 2006.285.19:34:12.70#ibcon#about to read 4, iclass 16, count 2 2006.285.19:34:12.70#ibcon#read 4, iclass 16, count 2 2006.285.19:34:12.70#ibcon#about to read 5, iclass 16, count 2 2006.285.19:34:12.70#ibcon#read 5, iclass 16, count 2 2006.285.19:34:12.70#ibcon#about to read 6, iclass 16, count 2 2006.285.19:34:12.70#ibcon#read 6, iclass 16, count 2 2006.285.19:34:12.70#ibcon#end of sib2, iclass 16, count 2 2006.285.19:34:12.70#ibcon#*after write, iclass 16, count 2 2006.285.19:34:12.70#ibcon#*before return 0, iclass 16, count 2 2006.285.19:34:12.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:34:12.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:34:12.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.19:34:12.70#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:12.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:34:12.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:34:12.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:34:12.82#ibcon#enter wrdev, iclass 16, count 0 2006.285.19:34:12.82#ibcon#first serial, iclass 16, count 0 2006.285.19:34:12.82#ibcon#enter sib2, iclass 16, count 0 2006.285.19:34:12.82#ibcon#flushed, iclass 16, count 0 2006.285.19:34:12.82#ibcon#about to write, iclass 16, count 0 2006.285.19:34:12.82#ibcon#wrote, iclass 16, count 0 2006.285.19:34:12.82#ibcon#about to read 3, iclass 16, count 0 2006.285.19:34:12.84#ibcon#read 3, iclass 16, count 0 2006.285.19:34:12.84#ibcon#about to read 4, iclass 16, count 0 2006.285.19:34:12.84#ibcon#read 4, iclass 16, count 0 2006.285.19:34:12.84#ibcon#about to read 5, iclass 16, count 0 2006.285.19:34:12.84#ibcon#read 5, iclass 16, count 0 2006.285.19:34:12.84#ibcon#about to read 6, iclass 16, count 0 2006.285.19:34:12.84#ibcon#read 6, iclass 16, count 0 2006.285.19:34:12.84#ibcon#end of sib2, iclass 16, count 0 2006.285.19:34:12.84#ibcon#*mode == 0, iclass 16, count 0 2006.285.19:34:12.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.19:34:12.84#ibcon#[27=USB\r\n] 2006.285.19:34:12.84#ibcon#*before write, iclass 16, count 0 2006.285.19:34:12.84#ibcon#enter sib2, iclass 16, count 0 2006.285.19:34:12.84#ibcon#flushed, iclass 16, count 0 2006.285.19:34:12.84#ibcon#about to write, iclass 16, count 0 2006.285.19:34:12.84#ibcon#wrote, iclass 16, count 0 2006.285.19:34:12.84#ibcon#about to read 3, iclass 16, count 0 2006.285.19:34:12.87#ibcon#read 3, iclass 16, count 0 2006.285.19:34:12.87#ibcon#about to read 4, iclass 16, count 0 2006.285.19:34:12.87#ibcon#read 4, iclass 16, count 0 2006.285.19:34:12.87#ibcon#about to read 5, iclass 16, count 0 2006.285.19:34:12.87#ibcon#read 5, iclass 16, count 0 2006.285.19:34:12.87#ibcon#about to read 6, iclass 16, count 0 2006.285.19:34:12.87#ibcon#read 6, iclass 16, count 0 2006.285.19:34:12.87#ibcon#end of sib2, iclass 16, count 0 2006.285.19:34:12.87#ibcon#*after write, iclass 16, count 0 2006.285.19:34:12.87#ibcon#*before return 0, iclass 16, count 0 2006.285.19:34:12.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:34:12.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:34:12.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.19:34:12.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.19:34:12.87$vck44/vblo=7,734.99 2006.285.19:34:12.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.19:34:12.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.19:34:12.89#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:12.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:34:12.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:34:12.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:34:12.89#ibcon#enter wrdev, iclass 18, count 0 2006.285.19:34:12.89#ibcon#first serial, iclass 18, count 0 2006.285.19:34:12.89#ibcon#enter sib2, iclass 18, count 0 2006.285.19:34:12.89#ibcon#flushed, iclass 18, count 0 2006.285.19:34:12.89#ibcon#about to write, iclass 18, count 0 2006.285.19:34:12.89#ibcon#wrote, iclass 18, count 0 2006.285.19:34:12.89#ibcon#about to read 3, iclass 18, count 0 2006.285.19:34:12.90#ibcon#read 3, iclass 18, count 0 2006.285.19:34:12.90#ibcon#about to read 4, iclass 18, count 0 2006.285.19:34:12.90#ibcon#read 4, iclass 18, count 0 2006.285.19:34:12.90#ibcon#about to read 5, iclass 18, count 0 2006.285.19:34:12.90#ibcon#read 5, iclass 18, count 0 2006.285.19:34:12.90#ibcon#about to read 6, iclass 18, count 0 2006.285.19:34:12.90#ibcon#read 6, iclass 18, count 0 2006.285.19:34:12.90#ibcon#end of sib2, iclass 18, count 0 2006.285.19:34:12.90#ibcon#*mode == 0, iclass 18, count 0 2006.285.19:34:12.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.19:34:12.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.19:34:12.90#ibcon#*before write, iclass 18, count 0 2006.285.19:34:12.90#ibcon#enter sib2, iclass 18, count 0 2006.285.19:34:12.90#ibcon#flushed, iclass 18, count 0 2006.285.19:34:12.90#ibcon#about to write, iclass 18, count 0 2006.285.19:34:12.90#ibcon#wrote, iclass 18, count 0 2006.285.19:34:12.90#ibcon#about to read 3, iclass 18, count 0 2006.285.19:34:12.94#ibcon#read 3, iclass 18, count 0 2006.285.19:34:12.94#ibcon#about to read 4, iclass 18, count 0 2006.285.19:34:12.94#ibcon#read 4, iclass 18, count 0 2006.285.19:34:12.94#ibcon#about to read 5, iclass 18, count 0 2006.285.19:34:12.94#ibcon#read 5, iclass 18, count 0 2006.285.19:34:12.94#ibcon#about to read 6, iclass 18, count 0 2006.285.19:34:12.94#ibcon#read 6, iclass 18, count 0 2006.285.19:34:12.94#ibcon#end of sib2, iclass 18, count 0 2006.285.19:34:12.94#ibcon#*after write, iclass 18, count 0 2006.285.19:34:12.94#ibcon#*before return 0, iclass 18, count 0 2006.285.19:34:12.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:34:12.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:34:12.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.19:34:12.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.19:34:12.94$vck44/vb=7,4 2006.285.19:34:12.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.19:34:12.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.19:34:12.94#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:12.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:34:12.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:34:12.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:34:12.99#ibcon#enter wrdev, iclass 20, count 2 2006.285.19:34:12.99#ibcon#first serial, iclass 20, count 2 2006.285.19:34:12.99#ibcon#enter sib2, iclass 20, count 2 2006.285.19:34:12.99#ibcon#flushed, iclass 20, count 2 2006.285.19:34:12.99#ibcon#about to write, iclass 20, count 2 2006.285.19:34:12.99#ibcon#wrote, iclass 20, count 2 2006.285.19:34:12.99#ibcon#about to read 3, iclass 20, count 2 2006.285.19:34:13.01#ibcon#read 3, iclass 20, count 2 2006.285.19:34:13.01#ibcon#about to read 4, iclass 20, count 2 2006.285.19:34:13.01#ibcon#read 4, iclass 20, count 2 2006.285.19:34:13.01#ibcon#about to read 5, iclass 20, count 2 2006.285.19:34:13.01#ibcon#read 5, iclass 20, count 2 2006.285.19:34:13.01#ibcon#about to read 6, iclass 20, count 2 2006.285.19:34:13.01#ibcon#read 6, iclass 20, count 2 2006.285.19:34:13.01#ibcon#end of sib2, iclass 20, count 2 2006.285.19:34:13.01#ibcon#*mode == 0, iclass 20, count 2 2006.285.19:34:13.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.19:34:13.01#ibcon#[27=AT07-04\r\n] 2006.285.19:34:13.01#ibcon#*before write, iclass 20, count 2 2006.285.19:34:13.01#ibcon#enter sib2, iclass 20, count 2 2006.285.19:34:13.01#ibcon#flushed, iclass 20, count 2 2006.285.19:34:13.01#ibcon#about to write, iclass 20, count 2 2006.285.19:34:13.01#ibcon#wrote, iclass 20, count 2 2006.285.19:34:13.01#ibcon#about to read 3, iclass 20, count 2 2006.285.19:34:13.04#ibcon#read 3, iclass 20, count 2 2006.285.19:34:13.04#ibcon#about to read 4, iclass 20, count 2 2006.285.19:34:13.04#ibcon#read 4, iclass 20, count 2 2006.285.19:34:13.04#ibcon#about to read 5, iclass 20, count 2 2006.285.19:34:13.04#ibcon#read 5, iclass 20, count 2 2006.285.19:34:13.04#ibcon#about to read 6, iclass 20, count 2 2006.285.19:34:13.04#ibcon#read 6, iclass 20, count 2 2006.285.19:34:13.04#ibcon#end of sib2, iclass 20, count 2 2006.285.19:34:13.04#ibcon#*after write, iclass 20, count 2 2006.285.19:34:13.04#ibcon#*before return 0, iclass 20, count 2 2006.285.19:34:13.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:34:13.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:34:13.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.19:34:13.04#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:13.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:34:13.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:34:13.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:34:13.16#ibcon#enter wrdev, iclass 20, count 0 2006.285.19:34:13.16#ibcon#first serial, iclass 20, count 0 2006.285.19:34:13.16#ibcon#enter sib2, iclass 20, count 0 2006.285.19:34:13.16#ibcon#flushed, iclass 20, count 0 2006.285.19:34:13.16#ibcon#about to write, iclass 20, count 0 2006.285.19:34:13.16#ibcon#wrote, iclass 20, count 0 2006.285.19:34:13.16#ibcon#about to read 3, iclass 20, count 0 2006.285.19:34:13.18#ibcon#read 3, iclass 20, count 0 2006.285.19:34:13.18#ibcon#about to read 4, iclass 20, count 0 2006.285.19:34:13.18#ibcon#read 4, iclass 20, count 0 2006.285.19:34:13.18#ibcon#about to read 5, iclass 20, count 0 2006.285.19:34:13.18#ibcon#read 5, iclass 20, count 0 2006.285.19:34:13.18#ibcon#about to read 6, iclass 20, count 0 2006.285.19:34:13.18#ibcon#read 6, iclass 20, count 0 2006.285.19:34:13.18#ibcon#end of sib2, iclass 20, count 0 2006.285.19:34:13.18#ibcon#*mode == 0, iclass 20, count 0 2006.285.19:34:13.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.19:34:13.18#ibcon#[27=USB\r\n] 2006.285.19:34:13.18#ibcon#*before write, iclass 20, count 0 2006.285.19:34:13.18#ibcon#enter sib2, iclass 20, count 0 2006.285.19:34:13.18#ibcon#flushed, iclass 20, count 0 2006.285.19:34:13.18#ibcon#about to write, iclass 20, count 0 2006.285.19:34:13.18#ibcon#wrote, iclass 20, count 0 2006.285.19:34:13.18#ibcon#about to read 3, iclass 20, count 0 2006.285.19:34:13.21#ibcon#read 3, iclass 20, count 0 2006.285.19:34:13.21#ibcon#about to read 4, iclass 20, count 0 2006.285.19:34:13.21#ibcon#read 4, iclass 20, count 0 2006.285.19:34:13.21#ibcon#about to read 5, iclass 20, count 0 2006.285.19:34:13.21#ibcon#read 5, iclass 20, count 0 2006.285.19:34:13.21#ibcon#about to read 6, iclass 20, count 0 2006.285.19:34:13.21#ibcon#read 6, iclass 20, count 0 2006.285.19:34:13.21#ibcon#end of sib2, iclass 20, count 0 2006.285.19:34:13.21#ibcon#*after write, iclass 20, count 0 2006.285.19:34:13.21#ibcon#*before return 0, iclass 20, count 0 2006.285.19:34:13.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:34:13.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:34:13.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.19:34:13.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.19:34:13.21$vck44/vblo=8,744.99 2006.285.19:34:13.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.19:34:13.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.19:34:13.21#ibcon#ireg 17 cls_cnt 0 2006.285.19:34:13.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:34:13.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:34:13.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:34:13.21#ibcon#enter wrdev, iclass 22, count 0 2006.285.19:34:13.21#ibcon#first serial, iclass 22, count 0 2006.285.19:34:13.21#ibcon#enter sib2, iclass 22, count 0 2006.285.19:34:13.21#ibcon#flushed, iclass 22, count 0 2006.285.19:34:13.21#ibcon#about to write, iclass 22, count 0 2006.285.19:34:13.21#ibcon#wrote, iclass 22, count 0 2006.285.19:34:13.21#ibcon#about to read 3, iclass 22, count 0 2006.285.19:34:13.23#ibcon#read 3, iclass 22, count 0 2006.285.19:34:13.23#ibcon#about to read 4, iclass 22, count 0 2006.285.19:34:13.23#ibcon#read 4, iclass 22, count 0 2006.285.19:34:13.23#ibcon#about to read 5, iclass 22, count 0 2006.285.19:34:13.23#ibcon#read 5, iclass 22, count 0 2006.285.19:34:13.23#ibcon#about to read 6, iclass 22, count 0 2006.285.19:34:13.23#ibcon#read 6, iclass 22, count 0 2006.285.19:34:13.23#ibcon#end of sib2, iclass 22, count 0 2006.285.19:34:13.23#ibcon#*mode == 0, iclass 22, count 0 2006.285.19:34:13.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.19:34:13.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.19:34:13.23#ibcon#*before write, iclass 22, count 0 2006.285.19:34:13.23#ibcon#enter sib2, iclass 22, count 0 2006.285.19:34:13.23#ibcon#flushed, iclass 22, count 0 2006.285.19:34:13.23#ibcon#about to write, iclass 22, count 0 2006.285.19:34:13.23#ibcon#wrote, iclass 22, count 0 2006.285.19:34:13.23#ibcon#about to read 3, iclass 22, count 0 2006.285.19:34:13.27#ibcon#read 3, iclass 22, count 0 2006.285.19:34:13.27#ibcon#about to read 4, iclass 22, count 0 2006.285.19:34:13.27#ibcon#read 4, iclass 22, count 0 2006.285.19:34:13.27#ibcon#about to read 5, iclass 22, count 0 2006.285.19:34:13.27#ibcon#read 5, iclass 22, count 0 2006.285.19:34:13.27#ibcon#about to read 6, iclass 22, count 0 2006.285.19:34:13.27#ibcon#read 6, iclass 22, count 0 2006.285.19:34:13.27#ibcon#end of sib2, iclass 22, count 0 2006.285.19:34:13.27#ibcon#*after write, iclass 22, count 0 2006.285.19:34:13.27#ibcon#*before return 0, iclass 22, count 0 2006.285.19:34:13.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:34:13.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:34:13.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.19:34:13.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.19:34:13.27$vck44/vb=8,4 2006.285.19:34:13.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.19:34:13.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.19:34:13.27#ibcon#ireg 11 cls_cnt 2 2006.285.19:34:13.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:34:13.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:34:13.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:34:13.33#ibcon#enter wrdev, iclass 24, count 2 2006.285.19:34:13.33#ibcon#first serial, iclass 24, count 2 2006.285.19:34:13.33#ibcon#enter sib2, iclass 24, count 2 2006.285.19:34:13.33#ibcon#flushed, iclass 24, count 2 2006.285.19:34:13.33#ibcon#about to write, iclass 24, count 2 2006.285.19:34:13.33#ibcon#wrote, iclass 24, count 2 2006.285.19:34:13.33#ibcon#about to read 3, iclass 24, count 2 2006.285.19:34:13.35#ibcon#read 3, iclass 24, count 2 2006.285.19:34:13.35#ibcon#about to read 4, iclass 24, count 2 2006.285.19:34:13.35#ibcon#read 4, iclass 24, count 2 2006.285.19:34:13.35#ibcon#about to read 5, iclass 24, count 2 2006.285.19:34:13.35#ibcon#read 5, iclass 24, count 2 2006.285.19:34:13.35#ibcon#about to read 6, iclass 24, count 2 2006.285.19:34:13.35#ibcon#read 6, iclass 24, count 2 2006.285.19:34:13.35#ibcon#end of sib2, iclass 24, count 2 2006.285.19:34:13.35#ibcon#*mode == 0, iclass 24, count 2 2006.285.19:34:13.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.19:34:13.35#ibcon#[27=AT08-04\r\n] 2006.285.19:34:13.35#ibcon#*before write, iclass 24, count 2 2006.285.19:34:13.35#ibcon#enter sib2, iclass 24, count 2 2006.285.19:34:13.35#ibcon#flushed, iclass 24, count 2 2006.285.19:34:13.35#ibcon#about to write, iclass 24, count 2 2006.285.19:34:13.35#ibcon#wrote, iclass 24, count 2 2006.285.19:34:13.35#ibcon#about to read 3, iclass 24, count 2 2006.285.19:34:13.38#ibcon#read 3, iclass 24, count 2 2006.285.19:34:13.38#ibcon#about to read 4, iclass 24, count 2 2006.285.19:34:13.38#ibcon#read 4, iclass 24, count 2 2006.285.19:34:13.38#ibcon#about to read 5, iclass 24, count 2 2006.285.19:34:13.38#ibcon#read 5, iclass 24, count 2 2006.285.19:34:13.38#ibcon#about to read 6, iclass 24, count 2 2006.285.19:34:13.38#ibcon#read 6, iclass 24, count 2 2006.285.19:34:13.38#ibcon#end of sib2, iclass 24, count 2 2006.285.19:34:13.38#ibcon#*after write, iclass 24, count 2 2006.285.19:34:13.38#ibcon#*before return 0, iclass 24, count 2 2006.285.19:34:13.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:34:13.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:34:13.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.19:34:13.38#ibcon#ireg 7 cls_cnt 0 2006.285.19:34:13.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:34:13.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:34:13.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:34:13.50#ibcon#enter wrdev, iclass 24, count 0 2006.285.19:34:13.50#ibcon#first serial, iclass 24, count 0 2006.285.19:34:13.50#ibcon#enter sib2, iclass 24, count 0 2006.285.19:34:13.50#ibcon#flushed, iclass 24, count 0 2006.285.19:34:13.50#ibcon#about to write, iclass 24, count 0 2006.285.19:34:13.50#ibcon#wrote, iclass 24, count 0 2006.285.19:34:13.50#ibcon#about to read 3, iclass 24, count 0 2006.285.19:34:13.52#ibcon#read 3, iclass 24, count 0 2006.285.19:34:13.52#ibcon#about to read 4, iclass 24, count 0 2006.285.19:34:13.52#ibcon#read 4, iclass 24, count 0 2006.285.19:34:13.52#ibcon#about to read 5, iclass 24, count 0 2006.285.19:34:13.52#ibcon#read 5, iclass 24, count 0 2006.285.19:34:13.52#ibcon#about to read 6, iclass 24, count 0 2006.285.19:34:13.52#ibcon#read 6, iclass 24, count 0 2006.285.19:34:13.52#ibcon#end of sib2, iclass 24, count 0 2006.285.19:34:13.52#ibcon#*mode == 0, iclass 24, count 0 2006.285.19:34:13.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.19:34:13.52#ibcon#[27=USB\r\n] 2006.285.19:34:13.52#ibcon#*before write, iclass 24, count 0 2006.285.19:34:13.52#ibcon#enter sib2, iclass 24, count 0 2006.285.19:34:13.52#ibcon#flushed, iclass 24, count 0 2006.285.19:34:13.52#ibcon#about to write, iclass 24, count 0 2006.285.19:34:13.52#ibcon#wrote, iclass 24, count 0 2006.285.19:34:13.52#ibcon#about to read 3, iclass 24, count 0 2006.285.19:34:13.55#ibcon#read 3, iclass 24, count 0 2006.285.19:34:13.55#ibcon#about to read 4, iclass 24, count 0 2006.285.19:34:13.55#ibcon#read 4, iclass 24, count 0 2006.285.19:34:13.55#ibcon#about to read 5, iclass 24, count 0 2006.285.19:34:13.55#ibcon#read 5, iclass 24, count 0 2006.285.19:34:13.55#ibcon#about to read 6, iclass 24, count 0 2006.285.19:34:13.55#ibcon#read 6, iclass 24, count 0 2006.285.19:34:13.55#ibcon#end of sib2, iclass 24, count 0 2006.285.19:34:13.55#ibcon#*after write, iclass 24, count 0 2006.285.19:34:13.55#ibcon#*before return 0, iclass 24, count 0 2006.285.19:34:13.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:34:13.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:34:13.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.19:34:13.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.19:34:13.55$vck44/vabw=wide 2006.285.19:34:13.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.19:34:13.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.19:34:13.55#ibcon#ireg 8 cls_cnt 0 2006.285.19:34:13.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:34:13.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:34:13.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:34:13.55#ibcon#enter wrdev, iclass 26, count 0 2006.285.19:34:13.55#ibcon#first serial, iclass 26, count 0 2006.285.19:34:13.55#ibcon#enter sib2, iclass 26, count 0 2006.285.19:34:13.55#ibcon#flushed, iclass 26, count 0 2006.285.19:34:13.55#ibcon#about to write, iclass 26, count 0 2006.285.19:34:13.55#ibcon#wrote, iclass 26, count 0 2006.285.19:34:13.55#ibcon#about to read 3, iclass 26, count 0 2006.285.19:34:13.57#ibcon#read 3, iclass 26, count 0 2006.285.19:34:13.57#ibcon#about to read 4, iclass 26, count 0 2006.285.19:34:13.57#ibcon#read 4, iclass 26, count 0 2006.285.19:34:13.57#ibcon#about to read 5, iclass 26, count 0 2006.285.19:34:13.57#ibcon#read 5, iclass 26, count 0 2006.285.19:34:13.57#ibcon#about to read 6, iclass 26, count 0 2006.285.19:34:13.57#ibcon#read 6, iclass 26, count 0 2006.285.19:34:13.57#ibcon#end of sib2, iclass 26, count 0 2006.285.19:34:13.57#ibcon#*mode == 0, iclass 26, count 0 2006.285.19:34:13.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.19:34:13.57#ibcon#[25=BW32\r\n] 2006.285.19:34:13.57#ibcon#*before write, iclass 26, count 0 2006.285.19:34:13.57#ibcon#enter sib2, iclass 26, count 0 2006.285.19:34:13.57#ibcon#flushed, iclass 26, count 0 2006.285.19:34:13.57#ibcon#about to write, iclass 26, count 0 2006.285.19:34:13.57#ibcon#wrote, iclass 26, count 0 2006.285.19:34:13.57#ibcon#about to read 3, iclass 26, count 0 2006.285.19:34:13.60#ibcon#read 3, iclass 26, count 0 2006.285.19:34:13.60#ibcon#about to read 4, iclass 26, count 0 2006.285.19:34:13.60#ibcon#read 4, iclass 26, count 0 2006.285.19:34:13.60#ibcon#about to read 5, iclass 26, count 0 2006.285.19:34:13.60#ibcon#read 5, iclass 26, count 0 2006.285.19:34:13.60#ibcon#about to read 6, iclass 26, count 0 2006.285.19:34:13.60#ibcon#read 6, iclass 26, count 0 2006.285.19:34:13.60#ibcon#end of sib2, iclass 26, count 0 2006.285.19:34:13.60#ibcon#*after write, iclass 26, count 0 2006.285.19:34:13.60#ibcon#*before return 0, iclass 26, count 0 2006.285.19:34:13.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:34:13.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:34:13.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.19:34:13.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.19:34:13.60$vck44/vbbw=wide 2006.285.19:34:13.60#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.19:34:13.60#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.19:34:13.60#ibcon#ireg 8 cls_cnt 0 2006.285.19:34:13.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:34:13.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:34:13.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:34:13.67#ibcon#enter wrdev, iclass 28, count 0 2006.285.19:34:13.67#ibcon#first serial, iclass 28, count 0 2006.285.19:34:13.67#ibcon#enter sib2, iclass 28, count 0 2006.285.19:34:13.67#ibcon#flushed, iclass 28, count 0 2006.285.19:34:13.67#ibcon#about to write, iclass 28, count 0 2006.285.19:34:13.67#ibcon#wrote, iclass 28, count 0 2006.285.19:34:13.67#ibcon#about to read 3, iclass 28, count 0 2006.285.19:34:13.69#ibcon#read 3, iclass 28, count 0 2006.285.19:34:13.69#ibcon#about to read 4, iclass 28, count 0 2006.285.19:34:13.69#ibcon#read 4, iclass 28, count 0 2006.285.19:34:13.69#ibcon#about to read 5, iclass 28, count 0 2006.285.19:34:13.69#ibcon#read 5, iclass 28, count 0 2006.285.19:34:13.69#ibcon#about to read 6, iclass 28, count 0 2006.285.19:34:13.69#ibcon#read 6, iclass 28, count 0 2006.285.19:34:13.69#ibcon#end of sib2, iclass 28, count 0 2006.285.19:34:13.69#ibcon#*mode == 0, iclass 28, count 0 2006.285.19:34:13.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.19:34:13.69#ibcon#[27=BW32\r\n] 2006.285.19:34:13.69#ibcon#*before write, iclass 28, count 0 2006.285.19:34:13.69#ibcon#enter sib2, iclass 28, count 0 2006.285.19:34:13.69#ibcon#flushed, iclass 28, count 0 2006.285.19:34:13.69#ibcon#about to write, iclass 28, count 0 2006.285.19:34:13.69#ibcon#wrote, iclass 28, count 0 2006.285.19:34:13.69#ibcon#about to read 3, iclass 28, count 0 2006.285.19:34:13.72#ibcon#read 3, iclass 28, count 0 2006.285.19:34:13.72#ibcon#about to read 4, iclass 28, count 0 2006.285.19:34:13.72#ibcon#read 4, iclass 28, count 0 2006.285.19:34:13.72#ibcon#about to read 5, iclass 28, count 0 2006.285.19:34:13.72#ibcon#read 5, iclass 28, count 0 2006.285.19:34:13.72#ibcon#about to read 6, iclass 28, count 0 2006.285.19:34:13.72#ibcon#read 6, iclass 28, count 0 2006.285.19:34:13.72#ibcon#end of sib2, iclass 28, count 0 2006.285.19:34:13.72#ibcon#*after write, iclass 28, count 0 2006.285.19:34:13.72#ibcon#*before return 0, iclass 28, count 0 2006.285.19:34:13.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:34:13.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:34:13.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.19:34:13.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.19:34:13.72$setupk4/ifdk4 2006.285.19:34:13.72$ifdk4/lo= 2006.285.19:34:13.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.19:34:13.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.19:34:13.73$ifdk4/patch= 2006.285.19:34:13.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.19:34:13.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.19:34:13.73$setupk4/!*+20s 2006.285.19:34:19.13#abcon#<5=/00 0.2 0.9 14.891001015.1\r\n> 2006.285.19:34:19.15#abcon#{5=INTERFACE CLEAR} 2006.285.19:34:19.21#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:34:27.50$setupk4/"tpicd 2006.285.19:34:27.50$setupk4/echo=off 2006.285.19:34:27.50$setupk4/xlog=off 2006.285.19:34:27.50:!2006.285.19:44:20 2006.285.19:35:24.13#trakl#Source acquired 2006.285.19:35:24.13#flagr#flagr/antenna,acquired 2006.285.19:44:20.00:preob 2006.285.19:44:20.13/onsource/TRACKING 2006.285.19:44:20.13:!2006.285.19:44:30 2006.285.19:44:30.00:"tape 2006.285.19:44:30.00:"st=record 2006.285.19:44:30.00:data_valid=on 2006.285.19:44:30.00:midob 2006.285.19:44:30.13/onsource/TRACKING 2006.285.19:44:30.13/wx/14.88,1015.2,100 2006.285.19:44:30.18/cable/+6.5068E-03 2006.285.19:44:31.27/va/01,07,usb,yes,32,34 2006.285.19:44:31.27/va/02,06,usb,yes,32,32 2006.285.19:44:31.27/va/03,07,usb,yes,31,33 2006.285.19:44:31.27/va/04,06,usb,yes,33,34 2006.285.19:44:31.27/va/05,03,usb,yes,32,33 2006.285.19:44:31.27/va/06,04,usb,yes,29,29 2006.285.19:44:31.27/va/07,04,usb,yes,30,30 2006.285.19:44:31.27/va/08,03,usb,yes,30,37 2006.285.19:44:31.50/valo/01,524.99,yes,locked 2006.285.19:44:31.50/valo/02,534.99,yes,locked 2006.285.19:44:31.50/valo/03,564.99,yes,locked 2006.285.19:44:31.50/valo/04,624.99,yes,locked 2006.285.19:44:31.50/valo/05,734.99,yes,locked 2006.285.19:44:31.50/valo/06,814.99,yes,locked 2006.285.19:44:31.50/valo/07,864.99,yes,locked 2006.285.19:44:31.50/valo/08,884.99,yes,locked 2006.285.19:44:32.59/vb/01,04,usb,yes,30,28 2006.285.19:44:32.59/vb/02,05,usb,yes,28,28 2006.285.19:44:32.59/vb/03,04,usb,yes,29,32 2006.285.19:44:32.59/vb/04,05,usb,yes,29,28 2006.285.19:44:32.59/vb/05,04,usb,yes,26,28 2006.285.19:44:32.59/vb/06,03,usb,yes,37,33 2006.285.19:44:32.59/vb/07,04,usb,yes,30,30 2006.285.19:44:32.59/vb/08,04,usb,yes,27,31 2006.285.19:44:32.82/vblo/01,629.99,yes,locked 2006.285.19:44:32.82/vblo/02,634.99,yes,locked 2006.285.19:44:32.82/vblo/03,649.99,yes,locked 2006.285.19:44:32.82/vblo/04,679.99,yes,locked 2006.285.19:44:32.82/vblo/05,709.99,yes,locked 2006.285.19:44:32.82/vblo/06,719.99,yes,locked 2006.285.19:44:32.82/vblo/07,734.99,yes,locked 2006.285.19:44:32.82/vblo/08,744.99,yes,locked 2006.285.19:44:32.97/vabw/8 2006.285.19:44:33.12/vbbw/8 2006.285.19:44:33.23/xfe/off,on,12.0 2006.285.19:44:33.60/ifatt/23,28,28,28 2006.285.19:44:34.07/fmout-gps/S +2.69E-07 2006.285.19:44:34.09:!2006.285.19:49:20 2006.285.19:49:20.01:data_valid=off 2006.285.19:49:20.01:"et 2006.285.19:49:20.01:!+3s 2006.285.19:49:23.02:"tape 2006.285.19:49:23.02:postob 2006.285.19:49:23.11/cable/+6.5061E-03 2006.285.19:49:23.11/wx/14.74,1015.2,100 2006.285.19:49:23.17/fmout-gps/S +2.72E-07 2006.285.19:49:23.17:scan_name=285-1953,jd0610,60 2006.285.19:49:23.17:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.285.19:49:24.14#flagr#flagr/antenna,new-source 2006.285.19:49:24.14:checkk5 2006.285.19:49:24.60/chk_autoobs//k5ts1/ autoobs is running! 2006.285.19:49:25.05/chk_autoobs//k5ts2/ autoobs is running! 2006.285.19:49:25.44/chk_autoobs//k5ts3/ autoobs is running! 2006.285.19:49:25.85/chk_autoobs//k5ts4/ autoobs is running! 2006.285.19:49:26.67/chk_obsdata//k5ts1/T2851944??a.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.19:49:27.30/chk_obsdata//k5ts2/T2851944??b.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.19:49:27.68/chk_obsdata//k5ts3/T2851944??c.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.19:49:28.24/chk_obsdata//k5ts4/T2851944??d.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.19:49:29.14/k5log//k5ts1_log_newline 2006.285.19:49:29.92/k5log//k5ts2_log_newline 2006.285.19:49:31.11/k5log//k5ts3_log_newline 2006.285.19:49:35.16/k5log//k5ts4_log_newline 2006.285.19:49:35.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.19:49:35.18:setupk4=1 2006.285.19:49:35.18$setupk4/echo=on 2006.285.19:49:35.18$setupk4/pcalon 2006.285.19:49:35.18$pcalon/"no phase cal control is implemented here 2006.285.19:49:35.18$setupk4/"tpicd=stop 2006.285.19:49:35.18$setupk4/"rec=synch_on 2006.285.19:49:35.18$setupk4/"rec_mode=128 2006.285.19:49:35.18$setupk4/!* 2006.285.19:49:35.18$setupk4/recpk4 2006.285.19:49:35.18$recpk4/recpatch= 2006.285.19:49:35.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.19:49:35.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.19:49:35.18$setupk4/vck44 2006.285.19:49:35.18$vck44/valo=1,524.99 2006.285.19:49:35.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.19:49:35.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.19:49:35.19#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:35.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:49:35.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:49:35.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:49:35.19#ibcon#enter wrdev, iclass 28, count 0 2006.285.19:49:35.19#ibcon#first serial, iclass 28, count 0 2006.285.19:49:35.19#ibcon#enter sib2, iclass 28, count 0 2006.285.19:49:35.19#ibcon#flushed, iclass 28, count 0 2006.285.19:49:35.19#ibcon#about to write, iclass 28, count 0 2006.285.19:49:35.19#ibcon#wrote, iclass 28, count 0 2006.285.19:49:35.19#ibcon#about to read 3, iclass 28, count 0 2006.285.19:49:35.20#ibcon#read 3, iclass 28, count 0 2006.285.19:49:35.20#ibcon#about to read 4, iclass 28, count 0 2006.285.19:49:35.20#ibcon#read 4, iclass 28, count 0 2006.285.19:49:35.20#ibcon#about to read 5, iclass 28, count 0 2006.285.19:49:35.20#ibcon#read 5, iclass 28, count 0 2006.285.19:49:35.20#ibcon#about to read 6, iclass 28, count 0 2006.285.19:49:35.20#ibcon#read 6, iclass 28, count 0 2006.285.19:49:35.20#ibcon#end of sib2, iclass 28, count 0 2006.285.19:49:35.20#ibcon#*mode == 0, iclass 28, count 0 2006.285.19:49:35.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.19:49:35.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.19:49:35.20#ibcon#*before write, iclass 28, count 0 2006.285.19:49:35.20#ibcon#enter sib2, iclass 28, count 0 2006.285.19:49:35.20#ibcon#flushed, iclass 28, count 0 2006.285.19:49:35.20#ibcon#about to write, iclass 28, count 0 2006.285.19:49:35.20#ibcon#wrote, iclass 28, count 0 2006.285.19:49:35.20#ibcon#about to read 3, iclass 28, count 0 2006.285.19:49:35.25#ibcon#read 3, iclass 28, count 0 2006.285.19:49:35.25#ibcon#about to read 4, iclass 28, count 0 2006.285.19:49:35.25#ibcon#read 4, iclass 28, count 0 2006.285.19:49:35.25#ibcon#about to read 5, iclass 28, count 0 2006.285.19:49:35.25#ibcon#read 5, iclass 28, count 0 2006.285.19:49:35.25#ibcon#about to read 6, iclass 28, count 0 2006.285.19:49:35.25#ibcon#read 6, iclass 28, count 0 2006.285.19:49:35.25#ibcon#end of sib2, iclass 28, count 0 2006.285.19:49:35.25#ibcon#*after write, iclass 28, count 0 2006.285.19:49:35.25#ibcon#*before return 0, iclass 28, count 0 2006.285.19:49:35.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:49:35.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:49:35.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.19:49:35.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.19:49:35.25$vck44/va=1,7 2006.285.19:49:35.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.19:49:35.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.19:49:35.25#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:35.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:49:35.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:49:35.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:49:35.25#ibcon#enter wrdev, iclass 30, count 2 2006.285.19:49:35.25#ibcon#first serial, iclass 30, count 2 2006.285.19:49:35.25#ibcon#enter sib2, iclass 30, count 2 2006.285.19:49:35.25#ibcon#flushed, iclass 30, count 2 2006.285.19:49:35.25#ibcon#about to write, iclass 30, count 2 2006.285.19:49:35.25#ibcon#wrote, iclass 30, count 2 2006.285.19:49:35.25#ibcon#about to read 3, iclass 30, count 2 2006.285.19:49:35.27#ibcon#read 3, iclass 30, count 2 2006.285.19:49:35.27#ibcon#about to read 4, iclass 30, count 2 2006.285.19:49:35.27#ibcon#read 4, iclass 30, count 2 2006.285.19:49:35.27#ibcon#about to read 5, iclass 30, count 2 2006.285.19:49:35.27#ibcon#read 5, iclass 30, count 2 2006.285.19:49:35.27#ibcon#about to read 6, iclass 30, count 2 2006.285.19:49:35.27#ibcon#read 6, iclass 30, count 2 2006.285.19:49:35.27#ibcon#end of sib2, iclass 30, count 2 2006.285.19:49:35.27#ibcon#*mode == 0, iclass 30, count 2 2006.285.19:49:35.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.19:49:35.27#ibcon#[25=AT01-07\r\n] 2006.285.19:49:35.27#ibcon#*before write, iclass 30, count 2 2006.285.19:49:35.27#ibcon#enter sib2, iclass 30, count 2 2006.285.19:49:35.27#ibcon#flushed, iclass 30, count 2 2006.285.19:49:35.27#ibcon#about to write, iclass 30, count 2 2006.285.19:49:35.27#ibcon#wrote, iclass 30, count 2 2006.285.19:49:35.27#ibcon#about to read 3, iclass 30, count 2 2006.285.19:49:35.30#ibcon#read 3, iclass 30, count 2 2006.285.19:49:35.30#ibcon#about to read 4, iclass 30, count 2 2006.285.19:49:35.30#ibcon#read 4, iclass 30, count 2 2006.285.19:49:35.30#ibcon#about to read 5, iclass 30, count 2 2006.285.19:49:35.30#ibcon#read 5, iclass 30, count 2 2006.285.19:49:35.30#ibcon#about to read 6, iclass 30, count 2 2006.285.19:49:35.30#ibcon#read 6, iclass 30, count 2 2006.285.19:49:35.30#ibcon#end of sib2, iclass 30, count 2 2006.285.19:49:35.30#ibcon#*after write, iclass 30, count 2 2006.285.19:49:35.30#ibcon#*before return 0, iclass 30, count 2 2006.285.19:49:35.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:49:35.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:49:35.30#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.19:49:35.30#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:35.30#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:49:35.42#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:49:35.42#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:49:35.42#ibcon#enter wrdev, iclass 30, count 0 2006.285.19:49:35.42#ibcon#first serial, iclass 30, count 0 2006.285.19:49:35.42#ibcon#enter sib2, iclass 30, count 0 2006.285.19:49:35.42#ibcon#flushed, iclass 30, count 0 2006.285.19:49:35.42#ibcon#about to write, iclass 30, count 0 2006.285.19:49:35.42#ibcon#wrote, iclass 30, count 0 2006.285.19:49:35.42#ibcon#about to read 3, iclass 30, count 0 2006.285.19:49:35.44#ibcon#read 3, iclass 30, count 0 2006.285.19:49:35.44#ibcon#about to read 4, iclass 30, count 0 2006.285.19:49:35.44#ibcon#read 4, iclass 30, count 0 2006.285.19:49:35.44#ibcon#about to read 5, iclass 30, count 0 2006.285.19:49:35.44#ibcon#read 5, iclass 30, count 0 2006.285.19:49:35.44#ibcon#about to read 6, iclass 30, count 0 2006.285.19:49:35.44#ibcon#read 6, iclass 30, count 0 2006.285.19:49:35.44#ibcon#end of sib2, iclass 30, count 0 2006.285.19:49:35.44#ibcon#*mode == 0, iclass 30, count 0 2006.285.19:49:35.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.19:49:35.44#ibcon#[25=USB\r\n] 2006.285.19:49:35.44#ibcon#*before write, iclass 30, count 0 2006.285.19:49:35.44#ibcon#enter sib2, iclass 30, count 0 2006.285.19:49:35.44#ibcon#flushed, iclass 30, count 0 2006.285.19:49:35.44#ibcon#about to write, iclass 30, count 0 2006.285.19:49:35.44#ibcon#wrote, iclass 30, count 0 2006.285.19:49:35.44#ibcon#about to read 3, iclass 30, count 0 2006.285.19:49:35.47#ibcon#read 3, iclass 30, count 0 2006.285.19:49:35.47#ibcon#about to read 4, iclass 30, count 0 2006.285.19:49:35.47#ibcon#read 4, iclass 30, count 0 2006.285.19:49:35.47#ibcon#about to read 5, iclass 30, count 0 2006.285.19:49:35.47#ibcon#read 5, iclass 30, count 0 2006.285.19:49:35.47#ibcon#about to read 6, iclass 30, count 0 2006.285.19:49:35.47#ibcon#read 6, iclass 30, count 0 2006.285.19:49:35.47#ibcon#end of sib2, iclass 30, count 0 2006.285.19:49:35.47#ibcon#*after write, iclass 30, count 0 2006.285.19:49:35.47#ibcon#*before return 0, iclass 30, count 0 2006.285.19:49:35.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:49:35.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:49:35.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.19:49:35.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.19:49:35.47$vck44/valo=2,534.99 2006.285.19:49:35.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.19:49:35.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.19:49:35.47#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:35.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:49:35.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:49:35.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:49:35.47#ibcon#enter wrdev, iclass 32, count 0 2006.285.19:49:35.47#ibcon#first serial, iclass 32, count 0 2006.285.19:49:35.47#ibcon#enter sib2, iclass 32, count 0 2006.285.19:49:35.47#ibcon#flushed, iclass 32, count 0 2006.285.19:49:35.47#ibcon#about to write, iclass 32, count 0 2006.285.19:49:35.47#ibcon#wrote, iclass 32, count 0 2006.285.19:49:35.47#ibcon#about to read 3, iclass 32, count 0 2006.285.19:49:35.49#ibcon#read 3, iclass 32, count 0 2006.285.19:49:35.49#ibcon#about to read 4, iclass 32, count 0 2006.285.19:49:35.49#ibcon#read 4, iclass 32, count 0 2006.285.19:49:35.49#ibcon#about to read 5, iclass 32, count 0 2006.285.19:49:35.49#ibcon#read 5, iclass 32, count 0 2006.285.19:49:35.49#ibcon#about to read 6, iclass 32, count 0 2006.285.19:49:35.49#ibcon#read 6, iclass 32, count 0 2006.285.19:49:35.49#ibcon#end of sib2, iclass 32, count 0 2006.285.19:49:35.49#ibcon#*mode == 0, iclass 32, count 0 2006.285.19:49:35.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.19:49:35.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.19:49:35.49#ibcon#*before write, iclass 32, count 0 2006.285.19:49:35.49#ibcon#enter sib2, iclass 32, count 0 2006.285.19:49:35.49#ibcon#flushed, iclass 32, count 0 2006.285.19:49:35.49#ibcon#about to write, iclass 32, count 0 2006.285.19:49:35.49#ibcon#wrote, iclass 32, count 0 2006.285.19:49:35.49#ibcon#about to read 3, iclass 32, count 0 2006.285.19:49:35.53#ibcon#read 3, iclass 32, count 0 2006.285.19:49:35.53#ibcon#about to read 4, iclass 32, count 0 2006.285.19:49:35.53#ibcon#read 4, iclass 32, count 0 2006.285.19:49:35.53#ibcon#about to read 5, iclass 32, count 0 2006.285.19:49:35.53#ibcon#read 5, iclass 32, count 0 2006.285.19:49:35.53#ibcon#about to read 6, iclass 32, count 0 2006.285.19:49:35.53#ibcon#read 6, iclass 32, count 0 2006.285.19:49:35.53#ibcon#end of sib2, iclass 32, count 0 2006.285.19:49:35.53#ibcon#*after write, iclass 32, count 0 2006.285.19:49:35.53#ibcon#*before return 0, iclass 32, count 0 2006.285.19:49:35.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:49:35.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:49:35.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.19:49:35.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.19:49:35.53$vck44/va=2,6 2006.285.19:49:35.53#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.19:49:35.53#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.19:49:35.53#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:35.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:49:35.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:49:35.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:49:35.59#ibcon#enter wrdev, iclass 34, count 2 2006.285.19:49:35.59#ibcon#first serial, iclass 34, count 2 2006.285.19:49:35.59#ibcon#enter sib2, iclass 34, count 2 2006.285.19:49:35.59#ibcon#flushed, iclass 34, count 2 2006.285.19:49:35.59#ibcon#about to write, iclass 34, count 2 2006.285.19:49:35.59#ibcon#wrote, iclass 34, count 2 2006.285.19:49:35.59#ibcon#about to read 3, iclass 34, count 2 2006.285.19:49:35.61#ibcon#read 3, iclass 34, count 2 2006.285.19:49:35.61#ibcon#about to read 4, iclass 34, count 2 2006.285.19:49:35.61#ibcon#read 4, iclass 34, count 2 2006.285.19:49:35.61#ibcon#about to read 5, iclass 34, count 2 2006.285.19:49:35.61#ibcon#read 5, iclass 34, count 2 2006.285.19:49:35.61#ibcon#about to read 6, iclass 34, count 2 2006.285.19:49:35.61#ibcon#read 6, iclass 34, count 2 2006.285.19:49:35.61#ibcon#end of sib2, iclass 34, count 2 2006.285.19:49:35.61#ibcon#*mode == 0, iclass 34, count 2 2006.285.19:49:35.61#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.19:49:35.61#ibcon#[25=AT02-06\r\n] 2006.285.19:49:35.61#ibcon#*before write, iclass 34, count 2 2006.285.19:49:35.61#ibcon#enter sib2, iclass 34, count 2 2006.285.19:49:35.61#ibcon#flushed, iclass 34, count 2 2006.285.19:49:35.61#ibcon#about to write, iclass 34, count 2 2006.285.19:49:35.61#ibcon#wrote, iclass 34, count 2 2006.285.19:49:35.61#ibcon#about to read 3, iclass 34, count 2 2006.285.19:49:35.64#ibcon#read 3, iclass 34, count 2 2006.285.19:49:35.64#ibcon#about to read 4, iclass 34, count 2 2006.285.19:49:35.64#ibcon#read 4, iclass 34, count 2 2006.285.19:49:35.64#ibcon#about to read 5, iclass 34, count 2 2006.285.19:49:35.64#ibcon#read 5, iclass 34, count 2 2006.285.19:49:35.64#ibcon#about to read 6, iclass 34, count 2 2006.285.19:49:35.64#ibcon#read 6, iclass 34, count 2 2006.285.19:49:35.64#ibcon#end of sib2, iclass 34, count 2 2006.285.19:49:35.64#ibcon#*after write, iclass 34, count 2 2006.285.19:49:35.64#ibcon#*before return 0, iclass 34, count 2 2006.285.19:49:35.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:49:35.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:49:35.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.19:49:35.64#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:35.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:49:35.76#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:49:35.76#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:49:35.76#ibcon#enter wrdev, iclass 34, count 0 2006.285.19:49:35.76#ibcon#first serial, iclass 34, count 0 2006.285.19:49:35.76#ibcon#enter sib2, iclass 34, count 0 2006.285.19:49:35.76#ibcon#flushed, iclass 34, count 0 2006.285.19:49:35.76#ibcon#about to write, iclass 34, count 0 2006.285.19:49:35.76#ibcon#wrote, iclass 34, count 0 2006.285.19:49:35.76#ibcon#about to read 3, iclass 34, count 0 2006.285.19:49:35.78#ibcon#read 3, iclass 34, count 0 2006.285.19:49:35.78#ibcon#about to read 4, iclass 34, count 0 2006.285.19:49:35.78#ibcon#read 4, iclass 34, count 0 2006.285.19:49:35.78#ibcon#about to read 5, iclass 34, count 0 2006.285.19:49:35.78#ibcon#read 5, iclass 34, count 0 2006.285.19:49:35.78#ibcon#about to read 6, iclass 34, count 0 2006.285.19:49:35.78#ibcon#read 6, iclass 34, count 0 2006.285.19:49:35.78#ibcon#end of sib2, iclass 34, count 0 2006.285.19:49:35.78#ibcon#*mode == 0, iclass 34, count 0 2006.285.19:49:35.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.19:49:35.78#ibcon#[25=USB\r\n] 2006.285.19:49:35.78#ibcon#*before write, iclass 34, count 0 2006.285.19:49:35.78#ibcon#enter sib2, iclass 34, count 0 2006.285.19:49:35.78#ibcon#flushed, iclass 34, count 0 2006.285.19:49:35.78#ibcon#about to write, iclass 34, count 0 2006.285.19:49:35.78#ibcon#wrote, iclass 34, count 0 2006.285.19:49:35.78#ibcon#about to read 3, iclass 34, count 0 2006.285.19:49:35.81#ibcon#read 3, iclass 34, count 0 2006.285.19:49:35.81#ibcon#about to read 4, iclass 34, count 0 2006.285.19:49:35.81#ibcon#read 4, iclass 34, count 0 2006.285.19:49:35.81#ibcon#about to read 5, iclass 34, count 0 2006.285.19:49:35.81#ibcon#read 5, iclass 34, count 0 2006.285.19:49:35.81#ibcon#about to read 6, iclass 34, count 0 2006.285.19:49:35.81#ibcon#read 6, iclass 34, count 0 2006.285.19:49:35.81#ibcon#end of sib2, iclass 34, count 0 2006.285.19:49:35.81#ibcon#*after write, iclass 34, count 0 2006.285.19:49:35.81#ibcon#*before return 0, iclass 34, count 0 2006.285.19:49:35.81#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:49:35.81#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:49:35.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.19:49:35.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.19:49:35.81$vck44/valo=3,564.99 2006.285.19:49:35.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.19:49:35.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.19:49:35.81#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:35.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:49:35.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:49:35.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:49:35.81#ibcon#enter wrdev, iclass 36, count 0 2006.285.19:49:35.81#ibcon#first serial, iclass 36, count 0 2006.285.19:49:35.81#ibcon#enter sib2, iclass 36, count 0 2006.285.19:49:35.81#ibcon#flushed, iclass 36, count 0 2006.285.19:49:35.81#ibcon#about to write, iclass 36, count 0 2006.285.19:49:35.81#ibcon#wrote, iclass 36, count 0 2006.285.19:49:35.81#ibcon#about to read 3, iclass 36, count 0 2006.285.19:49:35.83#ibcon#read 3, iclass 36, count 0 2006.285.19:49:35.83#ibcon#about to read 4, iclass 36, count 0 2006.285.19:49:35.83#ibcon#read 4, iclass 36, count 0 2006.285.19:49:35.83#ibcon#about to read 5, iclass 36, count 0 2006.285.19:49:35.83#ibcon#read 5, iclass 36, count 0 2006.285.19:49:35.83#ibcon#about to read 6, iclass 36, count 0 2006.285.19:49:35.83#ibcon#read 6, iclass 36, count 0 2006.285.19:49:35.83#ibcon#end of sib2, iclass 36, count 0 2006.285.19:49:35.83#ibcon#*mode == 0, iclass 36, count 0 2006.285.19:49:35.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.19:49:35.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.19:49:35.83#ibcon#*before write, iclass 36, count 0 2006.285.19:49:35.83#ibcon#enter sib2, iclass 36, count 0 2006.285.19:49:35.83#ibcon#flushed, iclass 36, count 0 2006.285.19:49:35.83#ibcon#about to write, iclass 36, count 0 2006.285.19:49:35.83#ibcon#wrote, iclass 36, count 0 2006.285.19:49:35.83#ibcon#about to read 3, iclass 36, count 0 2006.285.19:49:35.87#ibcon#read 3, iclass 36, count 0 2006.285.19:49:35.87#ibcon#about to read 4, iclass 36, count 0 2006.285.19:49:35.87#ibcon#read 4, iclass 36, count 0 2006.285.19:49:35.87#ibcon#about to read 5, iclass 36, count 0 2006.285.19:49:35.87#ibcon#read 5, iclass 36, count 0 2006.285.19:49:35.87#ibcon#about to read 6, iclass 36, count 0 2006.285.19:49:35.87#ibcon#read 6, iclass 36, count 0 2006.285.19:49:35.87#ibcon#end of sib2, iclass 36, count 0 2006.285.19:49:35.87#ibcon#*after write, iclass 36, count 0 2006.285.19:49:35.87#ibcon#*before return 0, iclass 36, count 0 2006.285.19:49:35.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:49:35.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:49:35.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.19:49:35.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.19:49:35.87$vck44/va=3,7 2006.285.19:49:35.87#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.19:49:35.87#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.19:49:35.87#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:35.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:49:35.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:49:36.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:49:36.26#ibcon#enter wrdev, iclass 38, count 2 2006.285.19:49:36.26#ibcon#first serial, iclass 38, count 2 2006.285.19:49:36.26#ibcon#enter sib2, iclass 38, count 2 2006.285.19:49:36.26#ibcon#flushed, iclass 38, count 2 2006.285.19:49:36.26#ibcon#about to write, iclass 38, count 2 2006.285.19:49:36.26#ibcon#wrote, iclass 38, count 2 2006.285.19:49:36.26#ibcon#about to read 3, iclass 38, count 2 2006.285.19:49:36.28#ibcon#read 3, iclass 38, count 2 2006.285.19:49:36.28#ibcon#about to read 4, iclass 38, count 2 2006.285.19:49:36.28#ibcon#read 4, iclass 38, count 2 2006.285.19:49:36.28#ibcon#about to read 5, iclass 38, count 2 2006.285.19:49:36.28#ibcon#read 5, iclass 38, count 2 2006.285.19:49:36.28#ibcon#about to read 6, iclass 38, count 2 2006.285.19:49:36.28#ibcon#read 6, iclass 38, count 2 2006.285.19:49:36.28#ibcon#end of sib2, iclass 38, count 2 2006.285.19:49:36.28#ibcon#*mode == 0, iclass 38, count 2 2006.285.19:49:36.28#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.19:49:36.28#ibcon#[25=AT03-07\r\n] 2006.285.19:49:36.28#ibcon#*before write, iclass 38, count 2 2006.285.19:49:36.28#ibcon#enter sib2, iclass 38, count 2 2006.285.19:49:36.28#ibcon#flushed, iclass 38, count 2 2006.285.19:49:36.28#ibcon#about to write, iclass 38, count 2 2006.285.19:49:36.28#ibcon#wrote, iclass 38, count 2 2006.285.19:49:36.28#ibcon#about to read 3, iclass 38, count 2 2006.285.19:49:36.31#ibcon#read 3, iclass 38, count 2 2006.285.19:49:36.31#ibcon#about to read 4, iclass 38, count 2 2006.285.19:49:36.31#ibcon#read 4, iclass 38, count 2 2006.285.19:49:36.31#ibcon#about to read 5, iclass 38, count 2 2006.285.19:49:36.31#ibcon#read 5, iclass 38, count 2 2006.285.19:49:36.31#ibcon#about to read 6, iclass 38, count 2 2006.285.19:49:36.31#ibcon#read 6, iclass 38, count 2 2006.285.19:49:36.31#ibcon#end of sib2, iclass 38, count 2 2006.285.19:49:36.31#ibcon#*after write, iclass 38, count 2 2006.285.19:49:36.31#ibcon#*before return 0, iclass 38, count 2 2006.285.19:49:36.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:49:36.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:49:36.31#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.19:49:36.31#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:36.31#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:49:36.43#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:49:36.43#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:49:36.43#ibcon#enter wrdev, iclass 38, count 0 2006.285.19:49:36.43#ibcon#first serial, iclass 38, count 0 2006.285.19:49:36.43#ibcon#enter sib2, iclass 38, count 0 2006.285.19:49:36.43#ibcon#flushed, iclass 38, count 0 2006.285.19:49:36.43#ibcon#about to write, iclass 38, count 0 2006.285.19:49:36.43#ibcon#wrote, iclass 38, count 0 2006.285.19:49:36.43#ibcon#about to read 3, iclass 38, count 0 2006.285.19:49:36.45#ibcon#read 3, iclass 38, count 0 2006.285.19:49:36.45#ibcon#about to read 4, iclass 38, count 0 2006.285.19:49:36.45#ibcon#read 4, iclass 38, count 0 2006.285.19:49:36.45#ibcon#about to read 5, iclass 38, count 0 2006.285.19:49:36.45#ibcon#read 5, iclass 38, count 0 2006.285.19:49:36.45#ibcon#about to read 6, iclass 38, count 0 2006.285.19:49:36.45#ibcon#read 6, iclass 38, count 0 2006.285.19:49:36.45#ibcon#end of sib2, iclass 38, count 0 2006.285.19:49:36.45#ibcon#*mode == 0, iclass 38, count 0 2006.285.19:49:36.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.19:49:36.45#ibcon#[25=USB\r\n] 2006.285.19:49:36.45#ibcon#*before write, iclass 38, count 0 2006.285.19:49:36.45#ibcon#enter sib2, iclass 38, count 0 2006.285.19:49:36.45#ibcon#flushed, iclass 38, count 0 2006.285.19:49:36.45#ibcon#about to write, iclass 38, count 0 2006.285.19:49:36.45#ibcon#wrote, iclass 38, count 0 2006.285.19:49:36.45#ibcon#about to read 3, iclass 38, count 0 2006.285.19:49:36.48#ibcon#read 3, iclass 38, count 0 2006.285.19:49:36.48#ibcon#about to read 4, iclass 38, count 0 2006.285.19:49:36.48#ibcon#read 4, iclass 38, count 0 2006.285.19:49:36.48#ibcon#about to read 5, iclass 38, count 0 2006.285.19:49:36.48#ibcon#read 5, iclass 38, count 0 2006.285.19:49:36.48#ibcon#about to read 6, iclass 38, count 0 2006.285.19:49:36.48#ibcon#read 6, iclass 38, count 0 2006.285.19:49:36.48#ibcon#end of sib2, iclass 38, count 0 2006.285.19:49:36.48#ibcon#*after write, iclass 38, count 0 2006.285.19:49:36.48#ibcon#*before return 0, iclass 38, count 0 2006.285.19:49:36.48#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:49:36.48#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:49:36.48#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.19:49:36.48#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.19:49:36.48$vck44/valo=4,624.99 2006.285.19:49:36.48#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.19:49:36.48#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.19:49:36.48#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:36.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:49:36.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:49:36.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:49:36.48#ibcon#enter wrdev, iclass 40, count 0 2006.285.19:49:36.48#ibcon#first serial, iclass 40, count 0 2006.285.19:49:36.48#ibcon#enter sib2, iclass 40, count 0 2006.285.19:49:36.48#ibcon#flushed, iclass 40, count 0 2006.285.19:49:36.48#ibcon#about to write, iclass 40, count 0 2006.285.19:49:36.48#ibcon#wrote, iclass 40, count 0 2006.285.19:49:36.48#ibcon#about to read 3, iclass 40, count 0 2006.285.19:49:36.50#ibcon#read 3, iclass 40, count 0 2006.285.19:49:36.50#ibcon#about to read 4, iclass 40, count 0 2006.285.19:49:36.50#ibcon#read 4, iclass 40, count 0 2006.285.19:49:36.50#ibcon#about to read 5, iclass 40, count 0 2006.285.19:49:36.50#ibcon#read 5, iclass 40, count 0 2006.285.19:49:36.50#ibcon#about to read 6, iclass 40, count 0 2006.285.19:49:36.50#ibcon#read 6, iclass 40, count 0 2006.285.19:49:36.50#ibcon#end of sib2, iclass 40, count 0 2006.285.19:49:36.50#ibcon#*mode == 0, iclass 40, count 0 2006.285.19:49:36.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.19:49:36.50#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.19:49:36.50#ibcon#*before write, iclass 40, count 0 2006.285.19:49:36.50#ibcon#enter sib2, iclass 40, count 0 2006.285.19:49:36.50#ibcon#flushed, iclass 40, count 0 2006.285.19:49:36.50#ibcon#about to write, iclass 40, count 0 2006.285.19:49:36.50#ibcon#wrote, iclass 40, count 0 2006.285.19:49:36.50#ibcon#about to read 3, iclass 40, count 0 2006.285.19:49:36.54#ibcon#read 3, iclass 40, count 0 2006.285.19:49:36.54#ibcon#about to read 4, iclass 40, count 0 2006.285.19:49:36.54#ibcon#read 4, iclass 40, count 0 2006.285.19:49:36.54#ibcon#about to read 5, iclass 40, count 0 2006.285.19:49:36.54#ibcon#read 5, iclass 40, count 0 2006.285.19:49:36.54#ibcon#about to read 6, iclass 40, count 0 2006.285.19:49:36.54#ibcon#read 6, iclass 40, count 0 2006.285.19:49:36.54#ibcon#end of sib2, iclass 40, count 0 2006.285.19:49:36.54#ibcon#*after write, iclass 40, count 0 2006.285.19:49:36.54#ibcon#*before return 0, iclass 40, count 0 2006.285.19:49:36.54#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:49:36.54#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:49:36.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.19:49:36.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.19:49:36.54$vck44/va=4,6 2006.285.19:49:36.90#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.19:49:36.90#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.19:49:36.90#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:36.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:49:36.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:49:36.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:49:36.90#ibcon#enter wrdev, iclass 4, count 2 2006.285.19:49:36.90#ibcon#first serial, iclass 4, count 2 2006.285.19:49:36.90#ibcon#enter sib2, iclass 4, count 2 2006.285.19:49:36.90#ibcon#flushed, iclass 4, count 2 2006.285.19:49:36.90#ibcon#about to write, iclass 4, count 2 2006.285.19:49:36.90#ibcon#wrote, iclass 4, count 2 2006.285.19:49:36.90#ibcon#about to read 3, iclass 4, count 2 2006.285.19:49:36.92#ibcon#read 3, iclass 4, count 2 2006.285.19:49:36.92#ibcon#about to read 4, iclass 4, count 2 2006.285.19:49:36.92#ibcon#read 4, iclass 4, count 2 2006.285.19:49:36.92#ibcon#about to read 5, iclass 4, count 2 2006.285.19:49:36.92#ibcon#read 5, iclass 4, count 2 2006.285.19:49:36.92#ibcon#about to read 6, iclass 4, count 2 2006.285.19:49:36.92#ibcon#read 6, iclass 4, count 2 2006.285.19:49:36.92#ibcon#end of sib2, iclass 4, count 2 2006.285.19:49:36.92#ibcon#*mode == 0, iclass 4, count 2 2006.285.19:49:36.92#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.19:49:36.92#ibcon#[25=AT04-06\r\n] 2006.285.19:49:36.92#ibcon#*before write, iclass 4, count 2 2006.285.19:49:36.92#ibcon#enter sib2, iclass 4, count 2 2006.285.19:49:36.92#ibcon#flushed, iclass 4, count 2 2006.285.19:49:36.92#ibcon#about to write, iclass 4, count 2 2006.285.19:49:36.92#ibcon#wrote, iclass 4, count 2 2006.285.19:49:36.92#ibcon#about to read 3, iclass 4, count 2 2006.285.19:49:36.95#ibcon#read 3, iclass 4, count 2 2006.285.19:49:36.95#ibcon#about to read 4, iclass 4, count 2 2006.285.19:49:36.95#ibcon#read 4, iclass 4, count 2 2006.285.19:49:36.95#ibcon#about to read 5, iclass 4, count 2 2006.285.19:49:36.95#ibcon#read 5, iclass 4, count 2 2006.285.19:49:36.95#ibcon#about to read 6, iclass 4, count 2 2006.285.19:49:36.95#ibcon#read 6, iclass 4, count 2 2006.285.19:49:36.95#ibcon#end of sib2, iclass 4, count 2 2006.285.19:49:36.95#ibcon#*after write, iclass 4, count 2 2006.285.19:49:36.95#ibcon#*before return 0, iclass 4, count 2 2006.285.19:49:36.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:49:36.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:49:36.95#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.19:49:36.95#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:36.95#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:49:37.07#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:49:37.07#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:49:37.07#ibcon#enter wrdev, iclass 4, count 0 2006.285.19:49:37.07#ibcon#first serial, iclass 4, count 0 2006.285.19:49:37.07#ibcon#enter sib2, iclass 4, count 0 2006.285.19:49:37.07#ibcon#flushed, iclass 4, count 0 2006.285.19:49:37.07#ibcon#about to write, iclass 4, count 0 2006.285.19:49:37.07#ibcon#wrote, iclass 4, count 0 2006.285.19:49:37.07#ibcon#about to read 3, iclass 4, count 0 2006.285.19:49:37.09#ibcon#read 3, iclass 4, count 0 2006.285.19:49:37.09#ibcon#about to read 4, iclass 4, count 0 2006.285.19:49:37.09#ibcon#read 4, iclass 4, count 0 2006.285.19:49:37.09#ibcon#about to read 5, iclass 4, count 0 2006.285.19:49:37.09#ibcon#read 5, iclass 4, count 0 2006.285.19:49:37.09#ibcon#about to read 6, iclass 4, count 0 2006.285.19:49:37.09#ibcon#read 6, iclass 4, count 0 2006.285.19:49:37.09#ibcon#end of sib2, iclass 4, count 0 2006.285.19:49:37.09#ibcon#*mode == 0, iclass 4, count 0 2006.285.19:49:37.09#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.19:49:37.09#ibcon#[25=USB\r\n] 2006.285.19:49:37.09#ibcon#*before write, iclass 4, count 0 2006.285.19:49:37.09#ibcon#enter sib2, iclass 4, count 0 2006.285.19:49:37.09#ibcon#flushed, iclass 4, count 0 2006.285.19:49:37.09#ibcon#about to write, iclass 4, count 0 2006.285.19:49:37.09#ibcon#wrote, iclass 4, count 0 2006.285.19:49:37.09#ibcon#about to read 3, iclass 4, count 0 2006.285.19:49:37.12#ibcon#read 3, iclass 4, count 0 2006.285.19:49:37.12#ibcon#about to read 4, iclass 4, count 0 2006.285.19:49:37.12#ibcon#read 4, iclass 4, count 0 2006.285.19:49:37.12#ibcon#about to read 5, iclass 4, count 0 2006.285.19:49:37.12#ibcon#read 5, iclass 4, count 0 2006.285.19:49:37.12#ibcon#about to read 6, iclass 4, count 0 2006.285.19:49:37.12#ibcon#read 6, iclass 4, count 0 2006.285.19:49:37.12#ibcon#end of sib2, iclass 4, count 0 2006.285.19:49:37.12#ibcon#*after write, iclass 4, count 0 2006.285.19:49:37.12#ibcon#*before return 0, iclass 4, count 0 2006.285.19:49:37.12#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:49:37.12#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:49:37.12#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.19:49:37.12#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.19:49:37.12$vck44/valo=5,734.99 2006.285.19:49:37.12#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.19:49:37.12#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.19:49:37.12#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:37.12#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:49:37.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:49:37.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:49:37.12#ibcon#enter wrdev, iclass 6, count 0 2006.285.19:49:37.12#ibcon#first serial, iclass 6, count 0 2006.285.19:49:37.12#ibcon#enter sib2, iclass 6, count 0 2006.285.19:49:37.12#ibcon#flushed, iclass 6, count 0 2006.285.19:49:37.12#ibcon#about to write, iclass 6, count 0 2006.285.19:49:37.12#ibcon#wrote, iclass 6, count 0 2006.285.19:49:37.12#ibcon#about to read 3, iclass 6, count 0 2006.285.19:49:37.14#ibcon#read 3, iclass 6, count 0 2006.285.19:49:37.14#ibcon#about to read 4, iclass 6, count 0 2006.285.19:49:37.14#ibcon#read 4, iclass 6, count 0 2006.285.19:49:37.14#ibcon#about to read 5, iclass 6, count 0 2006.285.19:49:37.14#ibcon#read 5, iclass 6, count 0 2006.285.19:49:37.14#ibcon#about to read 6, iclass 6, count 0 2006.285.19:49:37.14#ibcon#read 6, iclass 6, count 0 2006.285.19:49:37.14#ibcon#end of sib2, iclass 6, count 0 2006.285.19:49:37.14#ibcon#*mode == 0, iclass 6, count 0 2006.285.19:49:37.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.19:49:37.14#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.19:49:37.14#ibcon#*before write, iclass 6, count 0 2006.285.19:49:37.14#ibcon#enter sib2, iclass 6, count 0 2006.285.19:49:37.14#ibcon#flushed, iclass 6, count 0 2006.285.19:49:37.14#ibcon#about to write, iclass 6, count 0 2006.285.19:49:37.14#ibcon#wrote, iclass 6, count 0 2006.285.19:49:37.14#ibcon#about to read 3, iclass 6, count 0 2006.285.19:49:37.18#ibcon#read 3, iclass 6, count 0 2006.285.19:49:37.18#ibcon#about to read 4, iclass 6, count 0 2006.285.19:49:37.18#ibcon#read 4, iclass 6, count 0 2006.285.19:49:37.18#ibcon#about to read 5, iclass 6, count 0 2006.285.19:49:37.18#ibcon#read 5, iclass 6, count 0 2006.285.19:49:37.18#ibcon#about to read 6, iclass 6, count 0 2006.285.19:49:37.18#ibcon#read 6, iclass 6, count 0 2006.285.19:49:37.18#ibcon#end of sib2, iclass 6, count 0 2006.285.19:49:37.18#ibcon#*after write, iclass 6, count 0 2006.285.19:49:37.18#ibcon#*before return 0, iclass 6, count 0 2006.285.19:49:37.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:49:37.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:49:37.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.19:49:37.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.19:49:37.18$vck44/va=5,3 2006.285.19:49:37.18#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.19:49:37.18#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.19:49:37.18#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:37.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:49:37.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:49:37.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:49:37.24#ibcon#enter wrdev, iclass 10, count 2 2006.285.19:49:37.24#ibcon#first serial, iclass 10, count 2 2006.285.19:49:37.24#ibcon#enter sib2, iclass 10, count 2 2006.285.19:49:37.24#ibcon#flushed, iclass 10, count 2 2006.285.19:49:37.24#ibcon#about to write, iclass 10, count 2 2006.285.19:49:37.24#ibcon#wrote, iclass 10, count 2 2006.285.19:49:37.24#ibcon#about to read 3, iclass 10, count 2 2006.285.19:49:37.26#ibcon#read 3, iclass 10, count 2 2006.285.19:49:37.26#ibcon#about to read 4, iclass 10, count 2 2006.285.19:49:37.26#ibcon#read 4, iclass 10, count 2 2006.285.19:49:37.26#ibcon#about to read 5, iclass 10, count 2 2006.285.19:49:37.26#ibcon#read 5, iclass 10, count 2 2006.285.19:49:37.26#ibcon#about to read 6, iclass 10, count 2 2006.285.19:49:37.26#ibcon#read 6, iclass 10, count 2 2006.285.19:49:37.26#ibcon#end of sib2, iclass 10, count 2 2006.285.19:49:37.26#ibcon#*mode == 0, iclass 10, count 2 2006.285.19:49:37.26#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.19:49:37.26#ibcon#[25=AT05-03\r\n] 2006.285.19:49:37.26#ibcon#*before write, iclass 10, count 2 2006.285.19:49:37.26#ibcon#enter sib2, iclass 10, count 2 2006.285.19:49:37.26#ibcon#flushed, iclass 10, count 2 2006.285.19:49:37.26#ibcon#about to write, iclass 10, count 2 2006.285.19:49:37.26#ibcon#wrote, iclass 10, count 2 2006.285.19:49:37.26#ibcon#about to read 3, iclass 10, count 2 2006.285.19:49:37.29#ibcon#read 3, iclass 10, count 2 2006.285.19:49:37.29#ibcon#about to read 4, iclass 10, count 2 2006.285.19:49:37.29#ibcon#read 4, iclass 10, count 2 2006.285.19:49:37.29#ibcon#about to read 5, iclass 10, count 2 2006.285.19:49:37.29#ibcon#read 5, iclass 10, count 2 2006.285.19:49:37.29#ibcon#about to read 6, iclass 10, count 2 2006.285.19:49:37.29#ibcon#read 6, iclass 10, count 2 2006.285.19:49:37.29#ibcon#end of sib2, iclass 10, count 2 2006.285.19:49:37.29#ibcon#*after write, iclass 10, count 2 2006.285.19:49:37.29#ibcon#*before return 0, iclass 10, count 2 2006.285.19:49:37.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:49:37.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:49:37.29#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.19:49:37.29#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:37.29#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:49:37.41#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:49:37.41#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:49:37.41#ibcon#enter wrdev, iclass 10, count 0 2006.285.19:49:37.41#ibcon#first serial, iclass 10, count 0 2006.285.19:49:37.41#ibcon#enter sib2, iclass 10, count 0 2006.285.19:49:37.41#ibcon#flushed, iclass 10, count 0 2006.285.19:49:37.41#ibcon#about to write, iclass 10, count 0 2006.285.19:49:37.41#ibcon#wrote, iclass 10, count 0 2006.285.19:49:37.41#ibcon#about to read 3, iclass 10, count 0 2006.285.19:49:37.43#ibcon#read 3, iclass 10, count 0 2006.285.19:49:37.43#ibcon#about to read 4, iclass 10, count 0 2006.285.19:49:37.43#ibcon#read 4, iclass 10, count 0 2006.285.19:49:37.43#ibcon#about to read 5, iclass 10, count 0 2006.285.19:49:37.43#ibcon#read 5, iclass 10, count 0 2006.285.19:49:37.43#ibcon#about to read 6, iclass 10, count 0 2006.285.19:49:37.43#ibcon#read 6, iclass 10, count 0 2006.285.19:49:37.43#ibcon#end of sib2, iclass 10, count 0 2006.285.19:49:37.43#ibcon#*mode == 0, iclass 10, count 0 2006.285.19:49:37.43#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.19:49:37.43#ibcon#[25=USB\r\n] 2006.285.19:49:37.43#ibcon#*before write, iclass 10, count 0 2006.285.19:49:37.43#ibcon#enter sib2, iclass 10, count 0 2006.285.19:49:37.43#ibcon#flushed, iclass 10, count 0 2006.285.19:49:37.43#ibcon#about to write, iclass 10, count 0 2006.285.19:49:37.43#ibcon#wrote, iclass 10, count 0 2006.285.19:49:37.43#ibcon#about to read 3, iclass 10, count 0 2006.285.19:49:37.43#abcon#<5=/13 0.4 0.8 14.731001015.2\r\n> 2006.285.19:49:37.45#abcon#{5=INTERFACE CLEAR} 2006.285.19:49:37.46#ibcon#read 3, iclass 10, count 0 2006.285.19:49:37.46#ibcon#about to read 4, iclass 10, count 0 2006.285.19:49:37.46#ibcon#read 4, iclass 10, count 0 2006.285.19:49:37.46#ibcon#about to read 5, iclass 10, count 0 2006.285.19:49:37.46#ibcon#read 5, iclass 10, count 0 2006.285.19:49:37.46#ibcon#about to read 6, iclass 10, count 0 2006.285.19:49:37.46#ibcon#read 6, iclass 10, count 0 2006.285.19:49:37.46#ibcon#end of sib2, iclass 10, count 0 2006.285.19:49:37.46#ibcon#*after write, iclass 10, count 0 2006.285.19:49:37.46#ibcon#*before return 0, iclass 10, count 0 2006.285.19:49:37.46#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:49:37.46#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:49:37.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.19:49:37.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.19:49:37.46$vck44/valo=6,814.99 2006.285.19:49:37.46#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.19:49:37.46#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.19:49:37.46#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:37.46#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:49:37.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:49:37.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:49:37.46#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:49:37.46#ibcon#first serial, iclass 15, count 0 2006.285.19:49:37.46#ibcon#enter sib2, iclass 15, count 0 2006.285.19:49:37.46#ibcon#flushed, iclass 15, count 0 2006.285.19:49:37.46#ibcon#about to write, iclass 15, count 0 2006.285.19:49:37.46#ibcon#wrote, iclass 15, count 0 2006.285.19:49:37.46#ibcon#about to read 3, iclass 15, count 0 2006.285.19:49:37.48#ibcon#read 3, iclass 15, count 0 2006.285.19:49:37.48#ibcon#about to read 4, iclass 15, count 0 2006.285.19:49:37.48#ibcon#read 4, iclass 15, count 0 2006.285.19:49:37.48#ibcon#about to read 5, iclass 15, count 0 2006.285.19:49:37.48#ibcon#read 5, iclass 15, count 0 2006.285.19:49:37.48#ibcon#about to read 6, iclass 15, count 0 2006.285.19:49:37.48#ibcon#read 6, iclass 15, count 0 2006.285.19:49:37.48#ibcon#end of sib2, iclass 15, count 0 2006.285.19:49:37.48#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:49:37.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:49:37.48#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.19:49:37.48#ibcon#*before write, iclass 15, count 0 2006.285.19:49:37.48#ibcon#enter sib2, iclass 15, count 0 2006.285.19:49:37.48#ibcon#flushed, iclass 15, count 0 2006.285.19:49:37.48#ibcon#about to write, iclass 15, count 0 2006.285.19:49:37.48#ibcon#wrote, iclass 15, count 0 2006.285.19:49:37.48#ibcon#about to read 3, iclass 15, count 0 2006.285.19:49:37.51#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:49:37.52#ibcon#read 3, iclass 15, count 0 2006.285.19:49:37.52#ibcon#about to read 4, iclass 15, count 0 2006.285.19:49:37.52#ibcon#read 4, iclass 15, count 0 2006.285.19:49:37.52#ibcon#about to read 5, iclass 15, count 0 2006.285.19:49:37.52#ibcon#read 5, iclass 15, count 0 2006.285.19:49:37.52#ibcon#about to read 6, iclass 15, count 0 2006.285.19:49:37.52#ibcon#read 6, iclass 15, count 0 2006.285.19:49:37.52#ibcon#end of sib2, iclass 15, count 0 2006.285.19:49:37.52#ibcon#*after write, iclass 15, count 0 2006.285.19:49:37.52#ibcon#*before return 0, iclass 15, count 0 2006.285.19:49:37.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:49:37.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:49:37.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:49:37.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:49:37.52$vck44/va=6,4 2006.285.19:49:37.52#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.19:49:37.52#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.19:49:37.52#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:37.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:49:37.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:49:37.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:49:37.58#ibcon#enter wrdev, iclass 18, count 2 2006.285.19:49:37.58#ibcon#first serial, iclass 18, count 2 2006.285.19:49:37.58#ibcon#enter sib2, iclass 18, count 2 2006.285.19:49:37.58#ibcon#flushed, iclass 18, count 2 2006.285.19:49:37.58#ibcon#about to write, iclass 18, count 2 2006.285.19:49:37.58#ibcon#wrote, iclass 18, count 2 2006.285.19:49:37.58#ibcon#about to read 3, iclass 18, count 2 2006.285.19:49:37.60#ibcon#read 3, iclass 18, count 2 2006.285.19:49:37.60#ibcon#about to read 4, iclass 18, count 2 2006.285.19:49:37.60#ibcon#read 4, iclass 18, count 2 2006.285.19:49:37.60#ibcon#about to read 5, iclass 18, count 2 2006.285.19:49:37.60#ibcon#read 5, iclass 18, count 2 2006.285.19:49:37.60#ibcon#about to read 6, iclass 18, count 2 2006.285.19:49:37.60#ibcon#read 6, iclass 18, count 2 2006.285.19:49:37.60#ibcon#end of sib2, iclass 18, count 2 2006.285.19:49:37.60#ibcon#*mode == 0, iclass 18, count 2 2006.285.19:49:37.60#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.19:49:37.60#ibcon#[25=AT06-04\r\n] 2006.285.19:49:37.60#ibcon#*before write, iclass 18, count 2 2006.285.19:49:37.60#ibcon#enter sib2, iclass 18, count 2 2006.285.19:49:37.60#ibcon#flushed, iclass 18, count 2 2006.285.19:49:37.60#ibcon#about to write, iclass 18, count 2 2006.285.19:49:37.60#ibcon#wrote, iclass 18, count 2 2006.285.19:49:37.60#ibcon#about to read 3, iclass 18, count 2 2006.285.19:49:37.63#ibcon#read 3, iclass 18, count 2 2006.285.19:49:37.63#ibcon#about to read 4, iclass 18, count 2 2006.285.19:49:37.63#ibcon#read 4, iclass 18, count 2 2006.285.19:49:37.63#ibcon#about to read 5, iclass 18, count 2 2006.285.19:49:37.63#ibcon#read 5, iclass 18, count 2 2006.285.19:49:37.63#ibcon#about to read 6, iclass 18, count 2 2006.285.19:49:37.63#ibcon#read 6, iclass 18, count 2 2006.285.19:49:37.63#ibcon#end of sib2, iclass 18, count 2 2006.285.19:49:37.63#ibcon#*after write, iclass 18, count 2 2006.285.19:49:37.63#ibcon#*before return 0, iclass 18, count 2 2006.285.19:49:37.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:49:37.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:49:37.63#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.19:49:37.63#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:37.63#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:49:37.75#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:49:37.75#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:49:37.75#ibcon#enter wrdev, iclass 18, count 0 2006.285.19:49:37.75#ibcon#first serial, iclass 18, count 0 2006.285.19:49:37.75#ibcon#enter sib2, iclass 18, count 0 2006.285.19:49:37.75#ibcon#flushed, iclass 18, count 0 2006.285.19:49:37.75#ibcon#about to write, iclass 18, count 0 2006.285.19:49:37.75#ibcon#wrote, iclass 18, count 0 2006.285.19:49:37.75#ibcon#about to read 3, iclass 18, count 0 2006.285.19:49:37.77#ibcon#read 3, iclass 18, count 0 2006.285.19:49:37.77#ibcon#about to read 4, iclass 18, count 0 2006.285.19:49:37.77#ibcon#read 4, iclass 18, count 0 2006.285.19:49:37.77#ibcon#about to read 5, iclass 18, count 0 2006.285.19:49:37.77#ibcon#read 5, iclass 18, count 0 2006.285.19:49:37.77#ibcon#about to read 6, iclass 18, count 0 2006.285.19:49:37.77#ibcon#read 6, iclass 18, count 0 2006.285.19:49:37.77#ibcon#end of sib2, iclass 18, count 0 2006.285.19:49:37.77#ibcon#*mode == 0, iclass 18, count 0 2006.285.19:49:37.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.19:49:37.77#ibcon#[25=USB\r\n] 2006.285.19:49:37.77#ibcon#*before write, iclass 18, count 0 2006.285.19:49:37.77#ibcon#enter sib2, iclass 18, count 0 2006.285.19:49:37.77#ibcon#flushed, iclass 18, count 0 2006.285.19:49:37.77#ibcon#about to write, iclass 18, count 0 2006.285.19:49:37.77#ibcon#wrote, iclass 18, count 0 2006.285.19:49:37.77#ibcon#about to read 3, iclass 18, count 0 2006.285.19:49:37.80#ibcon#read 3, iclass 18, count 0 2006.285.19:49:37.80#ibcon#about to read 4, iclass 18, count 0 2006.285.19:49:37.80#ibcon#read 4, iclass 18, count 0 2006.285.19:49:37.80#ibcon#about to read 5, iclass 18, count 0 2006.285.19:49:37.80#ibcon#read 5, iclass 18, count 0 2006.285.19:49:37.80#ibcon#about to read 6, iclass 18, count 0 2006.285.19:49:37.80#ibcon#read 6, iclass 18, count 0 2006.285.19:49:37.80#ibcon#end of sib2, iclass 18, count 0 2006.285.19:49:37.80#ibcon#*after write, iclass 18, count 0 2006.285.19:49:37.80#ibcon#*before return 0, iclass 18, count 0 2006.285.19:49:37.80#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:49:37.80#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:49:37.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.19:49:37.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.19:49:37.80$vck44/valo=7,864.99 2006.285.19:49:37.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.19:49:37.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.19:49:37.80#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:37.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:49:37.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:49:37.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:49:37.80#ibcon#enter wrdev, iclass 20, count 0 2006.285.19:49:37.80#ibcon#first serial, iclass 20, count 0 2006.285.19:49:37.80#ibcon#enter sib2, iclass 20, count 0 2006.285.19:49:37.80#ibcon#flushed, iclass 20, count 0 2006.285.19:49:37.80#ibcon#about to write, iclass 20, count 0 2006.285.19:49:37.80#ibcon#wrote, iclass 20, count 0 2006.285.19:49:37.80#ibcon#about to read 3, iclass 20, count 0 2006.285.19:49:37.82#ibcon#read 3, iclass 20, count 0 2006.285.19:49:37.82#ibcon#about to read 4, iclass 20, count 0 2006.285.19:49:37.82#ibcon#read 4, iclass 20, count 0 2006.285.19:49:37.82#ibcon#about to read 5, iclass 20, count 0 2006.285.19:49:37.82#ibcon#read 5, iclass 20, count 0 2006.285.19:49:37.82#ibcon#about to read 6, iclass 20, count 0 2006.285.19:49:37.82#ibcon#read 6, iclass 20, count 0 2006.285.19:49:37.82#ibcon#end of sib2, iclass 20, count 0 2006.285.19:49:37.82#ibcon#*mode == 0, iclass 20, count 0 2006.285.19:49:37.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.19:49:37.82#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.19:49:37.82#ibcon#*before write, iclass 20, count 0 2006.285.19:49:37.82#ibcon#enter sib2, iclass 20, count 0 2006.285.19:49:37.82#ibcon#flushed, iclass 20, count 0 2006.285.19:49:37.82#ibcon#about to write, iclass 20, count 0 2006.285.19:49:37.82#ibcon#wrote, iclass 20, count 0 2006.285.19:49:37.82#ibcon#about to read 3, iclass 20, count 0 2006.285.19:49:37.86#ibcon#read 3, iclass 20, count 0 2006.285.19:49:37.86#ibcon#about to read 4, iclass 20, count 0 2006.285.19:49:37.86#ibcon#read 4, iclass 20, count 0 2006.285.19:49:37.86#ibcon#about to read 5, iclass 20, count 0 2006.285.19:49:37.86#ibcon#read 5, iclass 20, count 0 2006.285.19:49:37.86#ibcon#about to read 6, iclass 20, count 0 2006.285.19:49:37.86#ibcon#read 6, iclass 20, count 0 2006.285.19:49:37.86#ibcon#end of sib2, iclass 20, count 0 2006.285.19:49:37.86#ibcon#*after write, iclass 20, count 0 2006.285.19:49:37.86#ibcon#*before return 0, iclass 20, count 0 2006.285.19:49:37.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:49:37.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:49:37.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.19:49:37.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.19:49:37.86$vck44/va=7,4 2006.285.19:49:37.86#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.19:49:37.86#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.19:49:37.86#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:37.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:49:37.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:49:37.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:49:37.92#ibcon#enter wrdev, iclass 22, count 2 2006.285.19:49:37.92#ibcon#first serial, iclass 22, count 2 2006.285.19:49:37.92#ibcon#enter sib2, iclass 22, count 2 2006.285.19:49:37.92#ibcon#flushed, iclass 22, count 2 2006.285.19:49:37.92#ibcon#about to write, iclass 22, count 2 2006.285.19:49:37.92#ibcon#wrote, iclass 22, count 2 2006.285.19:49:37.92#ibcon#about to read 3, iclass 22, count 2 2006.285.19:49:37.94#ibcon#read 3, iclass 22, count 2 2006.285.19:49:37.94#ibcon#about to read 4, iclass 22, count 2 2006.285.19:49:37.94#ibcon#read 4, iclass 22, count 2 2006.285.19:49:37.94#ibcon#about to read 5, iclass 22, count 2 2006.285.19:49:37.94#ibcon#read 5, iclass 22, count 2 2006.285.19:49:37.94#ibcon#about to read 6, iclass 22, count 2 2006.285.19:49:37.94#ibcon#read 6, iclass 22, count 2 2006.285.19:49:37.94#ibcon#end of sib2, iclass 22, count 2 2006.285.19:49:37.94#ibcon#*mode == 0, iclass 22, count 2 2006.285.19:49:37.94#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.19:49:37.94#ibcon#[25=AT07-04\r\n] 2006.285.19:49:37.94#ibcon#*before write, iclass 22, count 2 2006.285.19:49:37.94#ibcon#enter sib2, iclass 22, count 2 2006.285.19:49:37.94#ibcon#flushed, iclass 22, count 2 2006.285.19:49:37.94#ibcon#about to write, iclass 22, count 2 2006.285.19:49:37.94#ibcon#wrote, iclass 22, count 2 2006.285.19:49:37.94#ibcon#about to read 3, iclass 22, count 2 2006.285.19:49:37.97#ibcon#read 3, iclass 22, count 2 2006.285.19:49:37.97#ibcon#about to read 4, iclass 22, count 2 2006.285.19:49:38.08#ibcon#read 4, iclass 22, count 2 2006.285.19:49:38.08#ibcon#about to read 5, iclass 22, count 2 2006.285.19:49:38.08#ibcon#read 5, iclass 22, count 2 2006.285.19:49:38.08#ibcon#about to read 6, iclass 22, count 2 2006.285.19:49:38.08#ibcon#read 6, iclass 22, count 2 2006.285.19:49:38.08#ibcon#end of sib2, iclass 22, count 2 2006.285.19:49:38.08#ibcon#*after write, iclass 22, count 2 2006.285.19:49:38.08#ibcon#*before return 0, iclass 22, count 2 2006.285.19:49:38.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:49:38.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:49:38.08#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.19:49:38.08#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:38.08#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:49:38.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:49:38.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:49:38.20#ibcon#enter wrdev, iclass 22, count 0 2006.285.19:49:38.20#ibcon#first serial, iclass 22, count 0 2006.285.19:49:38.20#ibcon#enter sib2, iclass 22, count 0 2006.285.19:49:38.20#ibcon#flushed, iclass 22, count 0 2006.285.19:49:38.20#ibcon#about to write, iclass 22, count 0 2006.285.19:49:38.20#ibcon#wrote, iclass 22, count 0 2006.285.19:49:38.20#ibcon#about to read 3, iclass 22, count 0 2006.285.19:49:38.22#ibcon#read 3, iclass 22, count 0 2006.285.19:49:38.22#ibcon#about to read 4, iclass 22, count 0 2006.285.19:49:38.22#ibcon#read 4, iclass 22, count 0 2006.285.19:49:38.22#ibcon#about to read 5, iclass 22, count 0 2006.285.19:49:38.22#ibcon#read 5, iclass 22, count 0 2006.285.19:49:38.22#ibcon#about to read 6, iclass 22, count 0 2006.285.19:49:38.22#ibcon#read 6, iclass 22, count 0 2006.285.19:49:38.22#ibcon#end of sib2, iclass 22, count 0 2006.285.19:49:38.22#ibcon#*mode == 0, iclass 22, count 0 2006.285.19:49:38.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.19:49:38.22#ibcon#[25=USB\r\n] 2006.285.19:49:38.22#ibcon#*before write, iclass 22, count 0 2006.285.19:49:38.22#ibcon#enter sib2, iclass 22, count 0 2006.285.19:49:38.22#ibcon#flushed, iclass 22, count 0 2006.285.19:49:38.22#ibcon#about to write, iclass 22, count 0 2006.285.19:49:38.22#ibcon#wrote, iclass 22, count 0 2006.285.19:49:38.22#ibcon#about to read 3, iclass 22, count 0 2006.285.19:49:38.25#ibcon#read 3, iclass 22, count 0 2006.285.19:49:38.25#ibcon#about to read 4, iclass 22, count 0 2006.285.19:49:38.25#ibcon#read 4, iclass 22, count 0 2006.285.19:49:38.25#ibcon#about to read 5, iclass 22, count 0 2006.285.19:49:38.25#ibcon#read 5, iclass 22, count 0 2006.285.19:49:38.25#ibcon#about to read 6, iclass 22, count 0 2006.285.19:49:38.25#ibcon#read 6, iclass 22, count 0 2006.285.19:49:38.25#ibcon#end of sib2, iclass 22, count 0 2006.285.19:49:38.25#ibcon#*after write, iclass 22, count 0 2006.285.19:49:38.25#ibcon#*before return 0, iclass 22, count 0 2006.285.19:49:38.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:49:38.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:49:38.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.19:49:38.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.19:49:38.25$vck44/valo=8,884.99 2006.285.19:49:38.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.19:49:38.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.19:49:38.25#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:38.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:49:38.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:49:38.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:49:38.25#ibcon#enter wrdev, iclass 24, count 0 2006.285.19:49:38.25#ibcon#first serial, iclass 24, count 0 2006.285.19:49:38.25#ibcon#enter sib2, iclass 24, count 0 2006.285.19:49:38.25#ibcon#flushed, iclass 24, count 0 2006.285.19:49:38.25#ibcon#about to write, iclass 24, count 0 2006.285.19:49:38.25#ibcon#wrote, iclass 24, count 0 2006.285.19:49:38.25#ibcon#about to read 3, iclass 24, count 0 2006.285.19:49:38.27#ibcon#read 3, iclass 24, count 0 2006.285.19:49:38.27#ibcon#about to read 4, iclass 24, count 0 2006.285.19:49:38.27#ibcon#read 4, iclass 24, count 0 2006.285.19:49:38.27#ibcon#about to read 5, iclass 24, count 0 2006.285.19:49:38.27#ibcon#read 5, iclass 24, count 0 2006.285.19:49:38.27#ibcon#about to read 6, iclass 24, count 0 2006.285.19:49:38.27#ibcon#read 6, iclass 24, count 0 2006.285.19:49:38.27#ibcon#end of sib2, iclass 24, count 0 2006.285.19:49:38.27#ibcon#*mode == 0, iclass 24, count 0 2006.285.19:49:38.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.19:49:38.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.19:49:38.27#ibcon#*before write, iclass 24, count 0 2006.285.19:49:38.27#ibcon#enter sib2, iclass 24, count 0 2006.285.19:49:38.27#ibcon#flushed, iclass 24, count 0 2006.285.19:49:38.27#ibcon#about to write, iclass 24, count 0 2006.285.19:49:38.27#ibcon#wrote, iclass 24, count 0 2006.285.19:49:38.27#ibcon#about to read 3, iclass 24, count 0 2006.285.19:49:38.31#ibcon#read 3, iclass 24, count 0 2006.285.19:49:38.31#ibcon#about to read 4, iclass 24, count 0 2006.285.19:49:38.31#ibcon#read 4, iclass 24, count 0 2006.285.19:49:38.31#ibcon#about to read 5, iclass 24, count 0 2006.285.19:49:38.31#ibcon#read 5, iclass 24, count 0 2006.285.19:49:38.31#ibcon#about to read 6, iclass 24, count 0 2006.285.19:49:38.31#ibcon#read 6, iclass 24, count 0 2006.285.19:49:38.31#ibcon#end of sib2, iclass 24, count 0 2006.285.19:49:38.31#ibcon#*after write, iclass 24, count 0 2006.285.19:49:38.31#ibcon#*before return 0, iclass 24, count 0 2006.285.19:49:38.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:49:38.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:49:38.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.19:49:38.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.19:49:38.31$vck44/va=8,3 2006.285.19:49:38.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.19:49:38.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.19:49:38.31#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:38.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:49:38.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:49:38.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:49:38.37#ibcon#enter wrdev, iclass 26, count 2 2006.285.19:49:38.37#ibcon#first serial, iclass 26, count 2 2006.285.19:49:38.37#ibcon#enter sib2, iclass 26, count 2 2006.285.19:49:38.37#ibcon#flushed, iclass 26, count 2 2006.285.19:49:38.37#ibcon#about to write, iclass 26, count 2 2006.285.19:49:38.37#ibcon#wrote, iclass 26, count 2 2006.285.19:49:38.37#ibcon#about to read 3, iclass 26, count 2 2006.285.19:49:38.39#ibcon#read 3, iclass 26, count 2 2006.285.19:49:38.39#ibcon#about to read 4, iclass 26, count 2 2006.285.19:49:38.39#ibcon#read 4, iclass 26, count 2 2006.285.19:49:38.39#ibcon#about to read 5, iclass 26, count 2 2006.285.19:49:38.39#ibcon#read 5, iclass 26, count 2 2006.285.19:49:38.39#ibcon#about to read 6, iclass 26, count 2 2006.285.19:49:38.39#ibcon#read 6, iclass 26, count 2 2006.285.19:49:38.39#ibcon#end of sib2, iclass 26, count 2 2006.285.19:49:38.39#ibcon#*mode == 0, iclass 26, count 2 2006.285.19:49:38.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.19:49:38.39#ibcon#[25=AT08-03\r\n] 2006.285.19:49:38.39#ibcon#*before write, iclass 26, count 2 2006.285.19:49:38.39#ibcon#enter sib2, iclass 26, count 2 2006.285.19:49:38.39#ibcon#flushed, iclass 26, count 2 2006.285.19:49:38.39#ibcon#about to write, iclass 26, count 2 2006.285.19:49:38.39#ibcon#wrote, iclass 26, count 2 2006.285.19:49:38.39#ibcon#about to read 3, iclass 26, count 2 2006.285.19:49:38.42#ibcon#read 3, iclass 26, count 2 2006.285.19:49:38.42#ibcon#about to read 4, iclass 26, count 2 2006.285.19:49:38.42#ibcon#read 4, iclass 26, count 2 2006.285.19:49:38.42#ibcon#about to read 5, iclass 26, count 2 2006.285.19:49:38.42#ibcon#read 5, iclass 26, count 2 2006.285.19:49:38.42#ibcon#about to read 6, iclass 26, count 2 2006.285.19:49:38.42#ibcon#read 6, iclass 26, count 2 2006.285.19:49:38.42#ibcon#end of sib2, iclass 26, count 2 2006.285.19:49:38.42#ibcon#*after write, iclass 26, count 2 2006.285.19:49:38.42#ibcon#*before return 0, iclass 26, count 2 2006.285.19:49:38.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:49:38.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.19:49:38.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.19:49:38.42#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:38.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:49:38.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:49:38.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:49:38.54#ibcon#enter wrdev, iclass 26, count 0 2006.285.19:49:38.54#ibcon#first serial, iclass 26, count 0 2006.285.19:49:38.54#ibcon#enter sib2, iclass 26, count 0 2006.285.19:49:38.54#ibcon#flushed, iclass 26, count 0 2006.285.19:49:38.54#ibcon#about to write, iclass 26, count 0 2006.285.19:49:38.54#ibcon#wrote, iclass 26, count 0 2006.285.19:49:38.54#ibcon#about to read 3, iclass 26, count 0 2006.285.19:49:38.56#ibcon#read 3, iclass 26, count 0 2006.285.19:49:38.56#ibcon#about to read 4, iclass 26, count 0 2006.285.19:49:38.56#ibcon#read 4, iclass 26, count 0 2006.285.19:49:38.56#ibcon#about to read 5, iclass 26, count 0 2006.285.19:49:38.56#ibcon#read 5, iclass 26, count 0 2006.285.19:49:38.56#ibcon#about to read 6, iclass 26, count 0 2006.285.19:49:38.56#ibcon#read 6, iclass 26, count 0 2006.285.19:49:38.56#ibcon#end of sib2, iclass 26, count 0 2006.285.19:49:38.56#ibcon#*mode == 0, iclass 26, count 0 2006.285.19:49:38.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.19:49:38.56#ibcon#[25=USB\r\n] 2006.285.19:49:38.56#ibcon#*before write, iclass 26, count 0 2006.285.19:49:38.56#ibcon#enter sib2, iclass 26, count 0 2006.285.19:49:38.56#ibcon#flushed, iclass 26, count 0 2006.285.19:49:38.56#ibcon#about to write, iclass 26, count 0 2006.285.19:49:38.56#ibcon#wrote, iclass 26, count 0 2006.285.19:49:38.56#ibcon#about to read 3, iclass 26, count 0 2006.285.19:49:38.59#ibcon#read 3, iclass 26, count 0 2006.285.19:49:38.59#ibcon#about to read 4, iclass 26, count 0 2006.285.19:49:38.59#ibcon#read 4, iclass 26, count 0 2006.285.19:49:38.59#ibcon#about to read 5, iclass 26, count 0 2006.285.19:49:38.59#ibcon#read 5, iclass 26, count 0 2006.285.19:49:38.59#ibcon#about to read 6, iclass 26, count 0 2006.285.19:49:38.59#ibcon#read 6, iclass 26, count 0 2006.285.19:49:38.59#ibcon#end of sib2, iclass 26, count 0 2006.285.19:49:38.59#ibcon#*after write, iclass 26, count 0 2006.285.19:49:38.59#ibcon#*before return 0, iclass 26, count 0 2006.285.19:49:38.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:49:38.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.19:49:38.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.19:49:38.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.19:49:38.59$vck44/vblo=1,629.99 2006.285.19:49:38.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.19:49:38.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.19:49:38.59#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:38.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:49:38.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:49:38.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:49:38.59#ibcon#enter wrdev, iclass 28, count 0 2006.285.19:49:38.59#ibcon#first serial, iclass 28, count 0 2006.285.19:49:38.59#ibcon#enter sib2, iclass 28, count 0 2006.285.19:49:38.59#ibcon#flushed, iclass 28, count 0 2006.285.19:49:38.59#ibcon#about to write, iclass 28, count 0 2006.285.19:49:38.59#ibcon#wrote, iclass 28, count 0 2006.285.19:49:38.59#ibcon#about to read 3, iclass 28, count 0 2006.285.19:49:38.61#ibcon#read 3, iclass 28, count 0 2006.285.19:49:38.61#ibcon#about to read 4, iclass 28, count 0 2006.285.19:49:38.61#ibcon#read 4, iclass 28, count 0 2006.285.19:49:38.61#ibcon#about to read 5, iclass 28, count 0 2006.285.19:49:38.61#ibcon#read 5, iclass 28, count 0 2006.285.19:49:38.61#ibcon#about to read 6, iclass 28, count 0 2006.285.19:49:38.61#ibcon#read 6, iclass 28, count 0 2006.285.19:49:38.61#ibcon#end of sib2, iclass 28, count 0 2006.285.19:49:38.61#ibcon#*mode == 0, iclass 28, count 0 2006.285.19:49:38.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.19:49:38.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.19:49:38.61#ibcon#*before write, iclass 28, count 0 2006.285.19:49:38.61#ibcon#enter sib2, iclass 28, count 0 2006.285.19:49:38.61#ibcon#flushed, iclass 28, count 0 2006.285.19:49:38.61#ibcon#about to write, iclass 28, count 0 2006.285.19:49:38.61#ibcon#wrote, iclass 28, count 0 2006.285.19:49:38.61#ibcon#about to read 3, iclass 28, count 0 2006.285.19:49:38.65#ibcon#read 3, iclass 28, count 0 2006.285.19:49:38.65#ibcon#about to read 4, iclass 28, count 0 2006.285.19:49:38.65#ibcon#read 4, iclass 28, count 0 2006.285.19:49:38.65#ibcon#about to read 5, iclass 28, count 0 2006.285.19:49:38.65#ibcon#read 5, iclass 28, count 0 2006.285.19:49:38.65#ibcon#about to read 6, iclass 28, count 0 2006.285.19:49:38.65#ibcon#read 6, iclass 28, count 0 2006.285.19:49:38.65#ibcon#end of sib2, iclass 28, count 0 2006.285.19:49:38.65#ibcon#*after write, iclass 28, count 0 2006.285.19:49:38.65#ibcon#*before return 0, iclass 28, count 0 2006.285.19:49:38.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:49:38.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.19:49:38.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.19:49:38.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.19:49:38.65$vck44/vb=1,4 2006.285.19:49:38.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.19:49:38.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.19:49:38.65#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:38.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:49:38.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:49:38.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:49:38.65#ibcon#enter wrdev, iclass 30, count 2 2006.285.19:49:38.65#ibcon#first serial, iclass 30, count 2 2006.285.19:49:38.65#ibcon#enter sib2, iclass 30, count 2 2006.285.19:49:38.65#ibcon#flushed, iclass 30, count 2 2006.285.19:49:38.65#ibcon#about to write, iclass 30, count 2 2006.285.19:49:38.65#ibcon#wrote, iclass 30, count 2 2006.285.19:49:38.65#ibcon#about to read 3, iclass 30, count 2 2006.285.19:49:38.67#ibcon#read 3, iclass 30, count 2 2006.285.19:49:38.67#ibcon#about to read 4, iclass 30, count 2 2006.285.19:49:38.67#ibcon#read 4, iclass 30, count 2 2006.285.19:49:38.67#ibcon#about to read 5, iclass 30, count 2 2006.285.19:49:38.67#ibcon#read 5, iclass 30, count 2 2006.285.19:49:38.67#ibcon#about to read 6, iclass 30, count 2 2006.285.19:49:38.67#ibcon#read 6, iclass 30, count 2 2006.285.19:49:38.67#ibcon#end of sib2, iclass 30, count 2 2006.285.19:49:38.67#ibcon#*mode == 0, iclass 30, count 2 2006.285.19:49:38.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.19:49:38.67#ibcon#[27=AT01-04\r\n] 2006.285.19:49:38.67#ibcon#*before write, iclass 30, count 2 2006.285.19:49:38.67#ibcon#enter sib2, iclass 30, count 2 2006.285.19:49:38.67#ibcon#flushed, iclass 30, count 2 2006.285.19:49:38.67#ibcon#about to write, iclass 30, count 2 2006.285.19:49:38.67#ibcon#wrote, iclass 30, count 2 2006.285.19:49:38.67#ibcon#about to read 3, iclass 30, count 2 2006.285.19:49:38.70#ibcon#read 3, iclass 30, count 2 2006.285.19:49:38.70#ibcon#about to read 4, iclass 30, count 2 2006.285.19:49:38.70#ibcon#read 4, iclass 30, count 2 2006.285.19:49:38.70#ibcon#about to read 5, iclass 30, count 2 2006.285.19:49:38.70#ibcon#read 5, iclass 30, count 2 2006.285.19:49:38.70#ibcon#about to read 6, iclass 30, count 2 2006.285.19:49:38.70#ibcon#read 6, iclass 30, count 2 2006.285.19:49:38.70#ibcon#end of sib2, iclass 30, count 2 2006.285.19:49:38.70#ibcon#*after write, iclass 30, count 2 2006.285.19:49:38.70#ibcon#*before return 0, iclass 30, count 2 2006.285.19:49:38.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:49:38.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.19:49:38.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.19:49:38.70#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:38.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:49:38.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:49:38.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:49:38.82#ibcon#enter wrdev, iclass 30, count 0 2006.285.19:49:38.82#ibcon#first serial, iclass 30, count 0 2006.285.19:49:38.82#ibcon#enter sib2, iclass 30, count 0 2006.285.19:49:38.82#ibcon#flushed, iclass 30, count 0 2006.285.19:49:38.82#ibcon#about to write, iclass 30, count 0 2006.285.19:49:38.82#ibcon#wrote, iclass 30, count 0 2006.285.19:49:38.82#ibcon#about to read 3, iclass 30, count 0 2006.285.19:49:38.84#ibcon#read 3, iclass 30, count 0 2006.285.19:49:38.84#ibcon#about to read 4, iclass 30, count 0 2006.285.19:49:38.84#ibcon#read 4, iclass 30, count 0 2006.285.19:49:38.84#ibcon#about to read 5, iclass 30, count 0 2006.285.19:49:38.84#ibcon#read 5, iclass 30, count 0 2006.285.19:49:38.84#ibcon#about to read 6, iclass 30, count 0 2006.285.19:49:38.84#ibcon#read 6, iclass 30, count 0 2006.285.19:49:38.84#ibcon#end of sib2, iclass 30, count 0 2006.285.19:49:38.84#ibcon#*mode == 0, iclass 30, count 0 2006.285.19:49:38.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.19:49:38.84#ibcon#[27=USB\r\n] 2006.285.19:49:38.84#ibcon#*before write, iclass 30, count 0 2006.285.19:49:38.84#ibcon#enter sib2, iclass 30, count 0 2006.285.19:49:38.84#ibcon#flushed, iclass 30, count 0 2006.285.19:49:38.84#ibcon#about to write, iclass 30, count 0 2006.285.19:49:38.84#ibcon#wrote, iclass 30, count 0 2006.285.19:49:38.84#ibcon#about to read 3, iclass 30, count 0 2006.285.19:49:38.87#ibcon#read 3, iclass 30, count 0 2006.285.19:49:38.87#ibcon#about to read 4, iclass 30, count 0 2006.285.19:49:38.87#ibcon#read 4, iclass 30, count 0 2006.285.19:49:38.87#ibcon#about to read 5, iclass 30, count 0 2006.285.19:49:38.87#ibcon#read 5, iclass 30, count 0 2006.285.19:49:38.87#ibcon#about to read 6, iclass 30, count 0 2006.285.19:49:38.87#ibcon#read 6, iclass 30, count 0 2006.285.19:49:38.87#ibcon#end of sib2, iclass 30, count 0 2006.285.19:49:38.87#ibcon#*after write, iclass 30, count 0 2006.285.19:49:38.87#ibcon#*before return 0, iclass 30, count 0 2006.285.19:49:38.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:49:38.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.19:49:38.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.19:49:38.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.19:49:38.87$vck44/vblo=2,634.99 2006.285.19:49:38.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.19:49:38.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.19:49:38.87#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:38.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:49:38.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:49:38.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:49:38.87#ibcon#enter wrdev, iclass 32, count 0 2006.285.19:49:38.87#ibcon#first serial, iclass 32, count 0 2006.285.19:49:38.87#ibcon#enter sib2, iclass 32, count 0 2006.285.19:49:38.87#ibcon#flushed, iclass 32, count 0 2006.285.19:49:38.87#ibcon#about to write, iclass 32, count 0 2006.285.19:49:38.87#ibcon#wrote, iclass 32, count 0 2006.285.19:49:38.87#ibcon#about to read 3, iclass 32, count 0 2006.285.19:49:38.89#ibcon#read 3, iclass 32, count 0 2006.285.19:49:38.89#ibcon#about to read 4, iclass 32, count 0 2006.285.19:49:38.89#ibcon#read 4, iclass 32, count 0 2006.285.19:49:38.89#ibcon#about to read 5, iclass 32, count 0 2006.285.19:49:38.89#ibcon#read 5, iclass 32, count 0 2006.285.19:49:38.89#ibcon#about to read 6, iclass 32, count 0 2006.285.19:49:38.89#ibcon#read 6, iclass 32, count 0 2006.285.19:49:38.89#ibcon#end of sib2, iclass 32, count 0 2006.285.19:49:38.89#ibcon#*mode == 0, iclass 32, count 0 2006.285.19:49:38.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.19:49:38.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.19:49:38.89#ibcon#*before write, iclass 32, count 0 2006.285.19:49:38.89#ibcon#enter sib2, iclass 32, count 0 2006.285.19:49:38.89#ibcon#flushed, iclass 32, count 0 2006.285.19:49:38.89#ibcon#about to write, iclass 32, count 0 2006.285.19:49:38.89#ibcon#wrote, iclass 32, count 0 2006.285.19:49:38.89#ibcon#about to read 3, iclass 32, count 0 2006.285.19:49:38.93#ibcon#read 3, iclass 32, count 0 2006.285.19:49:38.93#ibcon#about to read 4, iclass 32, count 0 2006.285.19:49:38.93#ibcon#read 4, iclass 32, count 0 2006.285.19:49:38.93#ibcon#about to read 5, iclass 32, count 0 2006.285.19:49:38.93#ibcon#read 5, iclass 32, count 0 2006.285.19:49:38.93#ibcon#about to read 6, iclass 32, count 0 2006.285.19:49:38.93#ibcon#read 6, iclass 32, count 0 2006.285.19:49:38.93#ibcon#end of sib2, iclass 32, count 0 2006.285.19:49:38.93#ibcon#*after write, iclass 32, count 0 2006.285.19:49:38.93#ibcon#*before return 0, iclass 32, count 0 2006.285.19:49:38.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:49:38.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.19:49:38.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.19:49:38.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.19:49:38.93$vck44/vb=2,5 2006.285.19:49:39.05#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.19:49:39.05#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.19:49:39.05#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:39.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:49:39.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:49:39.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:49:39.05#ibcon#enter wrdev, iclass 34, count 2 2006.285.19:49:39.05#ibcon#first serial, iclass 34, count 2 2006.285.19:49:39.05#ibcon#enter sib2, iclass 34, count 2 2006.285.19:49:39.05#ibcon#flushed, iclass 34, count 2 2006.285.19:49:39.05#ibcon#about to write, iclass 34, count 2 2006.285.19:49:39.05#ibcon#wrote, iclass 34, count 2 2006.285.19:49:39.05#ibcon#about to read 3, iclass 34, count 2 2006.285.19:49:39.06#ibcon#read 3, iclass 34, count 2 2006.285.19:49:39.06#ibcon#about to read 4, iclass 34, count 2 2006.285.19:49:39.06#ibcon#read 4, iclass 34, count 2 2006.285.19:49:39.06#ibcon#about to read 5, iclass 34, count 2 2006.285.19:49:39.06#ibcon#read 5, iclass 34, count 2 2006.285.19:49:39.06#ibcon#about to read 6, iclass 34, count 2 2006.285.19:49:39.06#ibcon#read 6, iclass 34, count 2 2006.285.19:49:39.06#ibcon#end of sib2, iclass 34, count 2 2006.285.19:49:39.06#ibcon#*mode == 0, iclass 34, count 2 2006.285.19:49:39.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.19:49:39.06#ibcon#[27=AT02-05\r\n] 2006.285.19:49:39.06#ibcon#*before write, iclass 34, count 2 2006.285.19:49:39.06#ibcon#enter sib2, iclass 34, count 2 2006.285.19:49:39.06#ibcon#flushed, iclass 34, count 2 2006.285.19:49:39.06#ibcon#about to write, iclass 34, count 2 2006.285.19:49:39.06#ibcon#wrote, iclass 34, count 2 2006.285.19:49:39.06#ibcon#about to read 3, iclass 34, count 2 2006.285.19:49:39.09#ibcon#read 3, iclass 34, count 2 2006.285.19:49:39.09#ibcon#about to read 4, iclass 34, count 2 2006.285.19:49:39.09#ibcon#read 4, iclass 34, count 2 2006.285.19:49:39.09#ibcon#about to read 5, iclass 34, count 2 2006.285.19:49:39.09#ibcon#read 5, iclass 34, count 2 2006.285.19:49:39.09#ibcon#about to read 6, iclass 34, count 2 2006.285.19:49:39.09#ibcon#read 6, iclass 34, count 2 2006.285.19:49:39.09#ibcon#end of sib2, iclass 34, count 2 2006.285.19:49:39.09#ibcon#*after write, iclass 34, count 2 2006.285.19:49:39.09#ibcon#*before return 0, iclass 34, count 2 2006.285.19:49:39.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:49:39.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.19:49:39.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.19:49:39.09#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:39.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:49:39.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:49:39.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:49:39.21#ibcon#enter wrdev, iclass 34, count 0 2006.285.19:49:39.21#ibcon#first serial, iclass 34, count 0 2006.285.19:49:39.21#ibcon#enter sib2, iclass 34, count 0 2006.285.19:49:39.21#ibcon#flushed, iclass 34, count 0 2006.285.19:49:39.21#ibcon#about to write, iclass 34, count 0 2006.285.19:49:39.21#ibcon#wrote, iclass 34, count 0 2006.285.19:49:39.21#ibcon#about to read 3, iclass 34, count 0 2006.285.19:49:39.23#ibcon#read 3, iclass 34, count 0 2006.285.19:49:39.23#ibcon#about to read 4, iclass 34, count 0 2006.285.19:49:39.23#ibcon#read 4, iclass 34, count 0 2006.285.19:49:39.23#ibcon#about to read 5, iclass 34, count 0 2006.285.19:49:39.23#ibcon#read 5, iclass 34, count 0 2006.285.19:49:39.23#ibcon#about to read 6, iclass 34, count 0 2006.285.19:49:39.23#ibcon#read 6, iclass 34, count 0 2006.285.19:49:39.23#ibcon#end of sib2, iclass 34, count 0 2006.285.19:49:39.23#ibcon#*mode == 0, iclass 34, count 0 2006.285.19:49:39.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.19:49:39.23#ibcon#[27=USB\r\n] 2006.285.19:49:39.23#ibcon#*before write, iclass 34, count 0 2006.285.19:49:39.23#ibcon#enter sib2, iclass 34, count 0 2006.285.19:49:39.23#ibcon#flushed, iclass 34, count 0 2006.285.19:49:39.23#ibcon#about to write, iclass 34, count 0 2006.285.19:49:39.23#ibcon#wrote, iclass 34, count 0 2006.285.19:49:39.23#ibcon#about to read 3, iclass 34, count 0 2006.285.19:49:39.26#ibcon#read 3, iclass 34, count 0 2006.285.19:49:39.26#ibcon#about to read 4, iclass 34, count 0 2006.285.19:49:39.26#ibcon#read 4, iclass 34, count 0 2006.285.19:49:39.26#ibcon#about to read 5, iclass 34, count 0 2006.285.19:49:39.26#ibcon#read 5, iclass 34, count 0 2006.285.19:49:39.26#ibcon#about to read 6, iclass 34, count 0 2006.285.19:49:39.26#ibcon#read 6, iclass 34, count 0 2006.285.19:49:39.26#ibcon#end of sib2, iclass 34, count 0 2006.285.19:49:39.26#ibcon#*after write, iclass 34, count 0 2006.285.19:49:39.26#ibcon#*before return 0, iclass 34, count 0 2006.285.19:49:39.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:49:39.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.19:49:39.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.19:49:39.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.19:49:39.26$vck44/vblo=3,649.99 2006.285.19:49:39.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.19:49:39.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.19:49:39.26#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:39.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:49:39.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:49:39.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:49:39.26#ibcon#enter wrdev, iclass 36, count 0 2006.285.19:49:39.26#ibcon#first serial, iclass 36, count 0 2006.285.19:49:39.26#ibcon#enter sib2, iclass 36, count 0 2006.285.19:49:39.26#ibcon#flushed, iclass 36, count 0 2006.285.19:49:39.26#ibcon#about to write, iclass 36, count 0 2006.285.19:49:39.26#ibcon#wrote, iclass 36, count 0 2006.285.19:49:39.26#ibcon#about to read 3, iclass 36, count 0 2006.285.19:49:39.28#ibcon#read 3, iclass 36, count 0 2006.285.19:49:39.28#ibcon#about to read 4, iclass 36, count 0 2006.285.19:49:39.28#ibcon#read 4, iclass 36, count 0 2006.285.19:49:39.28#ibcon#about to read 5, iclass 36, count 0 2006.285.19:49:39.28#ibcon#read 5, iclass 36, count 0 2006.285.19:49:39.28#ibcon#about to read 6, iclass 36, count 0 2006.285.19:49:39.28#ibcon#read 6, iclass 36, count 0 2006.285.19:49:39.28#ibcon#end of sib2, iclass 36, count 0 2006.285.19:49:39.28#ibcon#*mode == 0, iclass 36, count 0 2006.285.19:49:39.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.19:49:39.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.19:49:39.28#ibcon#*before write, iclass 36, count 0 2006.285.19:49:39.28#ibcon#enter sib2, iclass 36, count 0 2006.285.19:49:39.28#ibcon#flushed, iclass 36, count 0 2006.285.19:49:39.28#ibcon#about to write, iclass 36, count 0 2006.285.19:49:39.28#ibcon#wrote, iclass 36, count 0 2006.285.19:49:39.28#ibcon#about to read 3, iclass 36, count 0 2006.285.19:49:39.32#ibcon#read 3, iclass 36, count 0 2006.285.19:49:39.32#ibcon#about to read 4, iclass 36, count 0 2006.285.19:49:39.32#ibcon#read 4, iclass 36, count 0 2006.285.19:49:39.32#ibcon#about to read 5, iclass 36, count 0 2006.285.19:49:39.32#ibcon#read 5, iclass 36, count 0 2006.285.19:49:39.32#ibcon#about to read 6, iclass 36, count 0 2006.285.19:49:39.32#ibcon#read 6, iclass 36, count 0 2006.285.19:49:39.32#ibcon#end of sib2, iclass 36, count 0 2006.285.19:49:39.32#ibcon#*after write, iclass 36, count 0 2006.285.19:49:39.32#ibcon#*before return 0, iclass 36, count 0 2006.285.19:49:39.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:49:39.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.19:49:39.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.19:49:39.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.19:49:39.32$vck44/vb=3,4 2006.285.19:49:39.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.19:49:39.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.19:49:39.32#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:39.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:49:39.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:49:39.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:49:39.38#ibcon#enter wrdev, iclass 38, count 2 2006.285.19:49:39.38#ibcon#first serial, iclass 38, count 2 2006.285.19:49:39.38#ibcon#enter sib2, iclass 38, count 2 2006.285.19:49:39.38#ibcon#flushed, iclass 38, count 2 2006.285.19:49:39.38#ibcon#about to write, iclass 38, count 2 2006.285.19:49:39.38#ibcon#wrote, iclass 38, count 2 2006.285.19:49:39.38#ibcon#about to read 3, iclass 38, count 2 2006.285.19:49:39.40#ibcon#read 3, iclass 38, count 2 2006.285.19:49:39.40#ibcon#about to read 4, iclass 38, count 2 2006.285.19:49:39.40#ibcon#read 4, iclass 38, count 2 2006.285.19:49:39.40#ibcon#about to read 5, iclass 38, count 2 2006.285.19:49:39.40#ibcon#read 5, iclass 38, count 2 2006.285.19:49:39.40#ibcon#about to read 6, iclass 38, count 2 2006.285.19:49:39.40#ibcon#read 6, iclass 38, count 2 2006.285.19:49:39.40#ibcon#end of sib2, iclass 38, count 2 2006.285.19:49:39.40#ibcon#*mode == 0, iclass 38, count 2 2006.285.19:49:39.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.19:49:39.40#ibcon#[27=AT03-04\r\n] 2006.285.19:49:39.40#ibcon#*before write, iclass 38, count 2 2006.285.19:49:39.40#ibcon#enter sib2, iclass 38, count 2 2006.285.19:49:39.40#ibcon#flushed, iclass 38, count 2 2006.285.19:49:39.40#ibcon#about to write, iclass 38, count 2 2006.285.19:49:39.40#ibcon#wrote, iclass 38, count 2 2006.285.19:49:39.40#ibcon#about to read 3, iclass 38, count 2 2006.285.19:49:39.43#ibcon#read 3, iclass 38, count 2 2006.285.19:49:39.43#ibcon#about to read 4, iclass 38, count 2 2006.285.19:49:39.43#ibcon#read 4, iclass 38, count 2 2006.285.19:49:39.43#ibcon#about to read 5, iclass 38, count 2 2006.285.19:49:39.43#ibcon#read 5, iclass 38, count 2 2006.285.19:49:39.43#ibcon#about to read 6, iclass 38, count 2 2006.285.19:49:39.43#ibcon#read 6, iclass 38, count 2 2006.285.19:49:39.43#ibcon#end of sib2, iclass 38, count 2 2006.285.19:49:39.43#ibcon#*after write, iclass 38, count 2 2006.285.19:49:39.43#ibcon#*before return 0, iclass 38, count 2 2006.285.19:49:39.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:49:39.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.19:49:39.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.19:49:39.43#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:39.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:49:39.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:49:39.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:49:39.55#ibcon#enter wrdev, iclass 38, count 0 2006.285.19:49:39.55#ibcon#first serial, iclass 38, count 0 2006.285.19:49:39.55#ibcon#enter sib2, iclass 38, count 0 2006.285.19:49:39.55#ibcon#flushed, iclass 38, count 0 2006.285.19:49:39.55#ibcon#about to write, iclass 38, count 0 2006.285.19:49:39.55#ibcon#wrote, iclass 38, count 0 2006.285.19:49:39.55#ibcon#about to read 3, iclass 38, count 0 2006.285.19:49:39.57#ibcon#read 3, iclass 38, count 0 2006.285.19:49:39.57#ibcon#about to read 4, iclass 38, count 0 2006.285.19:49:39.57#ibcon#read 4, iclass 38, count 0 2006.285.19:49:39.57#ibcon#about to read 5, iclass 38, count 0 2006.285.19:49:39.57#ibcon#read 5, iclass 38, count 0 2006.285.19:49:39.57#ibcon#about to read 6, iclass 38, count 0 2006.285.19:49:39.57#ibcon#read 6, iclass 38, count 0 2006.285.19:49:39.57#ibcon#end of sib2, iclass 38, count 0 2006.285.19:49:39.57#ibcon#*mode == 0, iclass 38, count 0 2006.285.19:49:39.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.19:49:39.57#ibcon#[27=USB\r\n] 2006.285.19:49:39.57#ibcon#*before write, iclass 38, count 0 2006.285.19:49:39.57#ibcon#enter sib2, iclass 38, count 0 2006.285.19:49:39.57#ibcon#flushed, iclass 38, count 0 2006.285.19:49:39.57#ibcon#about to write, iclass 38, count 0 2006.285.19:49:39.57#ibcon#wrote, iclass 38, count 0 2006.285.19:49:39.57#ibcon#about to read 3, iclass 38, count 0 2006.285.19:49:39.60#ibcon#read 3, iclass 38, count 0 2006.285.19:49:39.60#ibcon#about to read 4, iclass 38, count 0 2006.285.19:49:39.60#ibcon#read 4, iclass 38, count 0 2006.285.19:49:39.60#ibcon#about to read 5, iclass 38, count 0 2006.285.19:49:39.60#ibcon#read 5, iclass 38, count 0 2006.285.19:49:39.60#ibcon#about to read 6, iclass 38, count 0 2006.285.19:49:39.60#ibcon#read 6, iclass 38, count 0 2006.285.19:49:39.60#ibcon#end of sib2, iclass 38, count 0 2006.285.19:49:39.60#ibcon#*after write, iclass 38, count 0 2006.285.19:49:39.60#ibcon#*before return 0, iclass 38, count 0 2006.285.19:49:39.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:49:39.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.19:49:39.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.19:49:39.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.19:49:39.60$vck44/vblo=4,679.99 2006.285.19:49:39.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.19:49:39.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.19:49:39.60#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:39.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:49:39.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:49:39.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:49:39.60#ibcon#enter wrdev, iclass 40, count 0 2006.285.19:49:39.60#ibcon#first serial, iclass 40, count 0 2006.285.19:49:39.60#ibcon#enter sib2, iclass 40, count 0 2006.285.19:49:39.60#ibcon#flushed, iclass 40, count 0 2006.285.19:49:39.60#ibcon#about to write, iclass 40, count 0 2006.285.19:49:39.60#ibcon#wrote, iclass 40, count 0 2006.285.19:49:39.60#ibcon#about to read 3, iclass 40, count 0 2006.285.19:49:39.62#ibcon#read 3, iclass 40, count 0 2006.285.19:49:39.62#ibcon#about to read 4, iclass 40, count 0 2006.285.19:49:39.62#ibcon#read 4, iclass 40, count 0 2006.285.19:49:39.62#ibcon#about to read 5, iclass 40, count 0 2006.285.19:49:39.62#ibcon#read 5, iclass 40, count 0 2006.285.19:49:39.62#ibcon#about to read 6, iclass 40, count 0 2006.285.19:49:39.62#ibcon#read 6, iclass 40, count 0 2006.285.19:49:39.62#ibcon#end of sib2, iclass 40, count 0 2006.285.19:49:39.62#ibcon#*mode == 0, iclass 40, count 0 2006.285.19:49:39.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.19:49:39.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.19:49:39.62#ibcon#*before write, iclass 40, count 0 2006.285.19:49:39.62#ibcon#enter sib2, iclass 40, count 0 2006.285.19:49:39.62#ibcon#flushed, iclass 40, count 0 2006.285.19:49:39.62#ibcon#about to write, iclass 40, count 0 2006.285.19:49:39.62#ibcon#wrote, iclass 40, count 0 2006.285.19:49:39.62#ibcon#about to read 3, iclass 40, count 0 2006.285.19:49:39.66#ibcon#read 3, iclass 40, count 0 2006.285.19:49:39.66#ibcon#about to read 4, iclass 40, count 0 2006.285.19:49:39.66#ibcon#read 4, iclass 40, count 0 2006.285.19:49:39.66#ibcon#about to read 5, iclass 40, count 0 2006.285.19:49:39.66#ibcon#read 5, iclass 40, count 0 2006.285.19:49:39.66#ibcon#about to read 6, iclass 40, count 0 2006.285.19:49:39.66#ibcon#read 6, iclass 40, count 0 2006.285.19:49:39.66#ibcon#end of sib2, iclass 40, count 0 2006.285.19:49:39.66#ibcon#*after write, iclass 40, count 0 2006.285.19:49:39.66#ibcon#*before return 0, iclass 40, count 0 2006.285.19:49:39.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:49:39.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.19:49:39.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.19:49:39.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.19:49:39.66$vck44/vb=4,5 2006.285.19:49:39.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.19:49:39.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.19:49:39.66#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:39.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:49:39.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:49:39.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:49:39.72#ibcon#enter wrdev, iclass 4, count 2 2006.285.19:49:39.72#ibcon#first serial, iclass 4, count 2 2006.285.19:49:39.72#ibcon#enter sib2, iclass 4, count 2 2006.285.19:49:39.72#ibcon#flushed, iclass 4, count 2 2006.285.19:49:39.72#ibcon#about to write, iclass 4, count 2 2006.285.19:49:39.72#ibcon#wrote, iclass 4, count 2 2006.285.19:49:39.72#ibcon#about to read 3, iclass 4, count 2 2006.285.19:49:39.74#ibcon#read 3, iclass 4, count 2 2006.285.19:49:39.74#ibcon#about to read 4, iclass 4, count 2 2006.285.19:49:39.74#ibcon#read 4, iclass 4, count 2 2006.285.19:49:39.74#ibcon#about to read 5, iclass 4, count 2 2006.285.19:49:39.74#ibcon#read 5, iclass 4, count 2 2006.285.19:49:39.74#ibcon#about to read 6, iclass 4, count 2 2006.285.19:49:39.74#ibcon#read 6, iclass 4, count 2 2006.285.19:49:39.74#ibcon#end of sib2, iclass 4, count 2 2006.285.19:49:39.74#ibcon#*mode == 0, iclass 4, count 2 2006.285.19:49:39.74#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.19:49:39.74#ibcon#[27=AT04-05\r\n] 2006.285.19:49:39.74#ibcon#*before write, iclass 4, count 2 2006.285.19:49:39.74#ibcon#enter sib2, iclass 4, count 2 2006.285.19:49:39.74#ibcon#flushed, iclass 4, count 2 2006.285.19:49:39.74#ibcon#about to write, iclass 4, count 2 2006.285.19:49:39.74#ibcon#wrote, iclass 4, count 2 2006.285.19:49:39.74#ibcon#about to read 3, iclass 4, count 2 2006.285.19:49:39.77#ibcon#read 3, iclass 4, count 2 2006.285.19:49:39.77#ibcon#about to read 4, iclass 4, count 2 2006.285.19:49:39.77#ibcon#read 4, iclass 4, count 2 2006.285.19:49:39.77#ibcon#about to read 5, iclass 4, count 2 2006.285.19:49:39.77#ibcon#read 5, iclass 4, count 2 2006.285.19:49:39.77#ibcon#about to read 6, iclass 4, count 2 2006.285.19:49:39.77#ibcon#read 6, iclass 4, count 2 2006.285.19:49:39.77#ibcon#end of sib2, iclass 4, count 2 2006.285.19:49:39.77#ibcon#*after write, iclass 4, count 2 2006.285.19:49:39.77#ibcon#*before return 0, iclass 4, count 2 2006.285.19:49:39.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:49:39.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.19:49:39.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.19:49:39.77#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:39.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:49:39.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:49:39.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:49:39.89#ibcon#enter wrdev, iclass 4, count 0 2006.285.19:49:39.89#ibcon#first serial, iclass 4, count 0 2006.285.19:49:39.89#ibcon#enter sib2, iclass 4, count 0 2006.285.19:49:39.89#ibcon#flushed, iclass 4, count 0 2006.285.19:49:39.89#ibcon#about to write, iclass 4, count 0 2006.285.19:49:39.89#ibcon#wrote, iclass 4, count 0 2006.285.19:49:39.89#ibcon#about to read 3, iclass 4, count 0 2006.285.19:49:39.91#ibcon#read 3, iclass 4, count 0 2006.285.19:49:39.91#ibcon#about to read 4, iclass 4, count 0 2006.285.19:49:39.91#ibcon#read 4, iclass 4, count 0 2006.285.19:49:39.91#ibcon#about to read 5, iclass 4, count 0 2006.285.19:49:39.91#ibcon#read 5, iclass 4, count 0 2006.285.19:49:39.91#ibcon#about to read 6, iclass 4, count 0 2006.285.19:49:39.91#ibcon#read 6, iclass 4, count 0 2006.285.19:49:39.91#ibcon#end of sib2, iclass 4, count 0 2006.285.19:49:39.91#ibcon#*mode == 0, iclass 4, count 0 2006.285.19:49:39.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.19:49:39.91#ibcon#[27=USB\r\n] 2006.285.19:49:39.91#ibcon#*before write, iclass 4, count 0 2006.285.19:49:39.91#ibcon#enter sib2, iclass 4, count 0 2006.285.19:49:39.91#ibcon#flushed, iclass 4, count 0 2006.285.19:49:39.91#ibcon#about to write, iclass 4, count 0 2006.285.19:49:39.91#ibcon#wrote, iclass 4, count 0 2006.285.19:49:39.91#ibcon#about to read 3, iclass 4, count 0 2006.285.19:49:39.94#ibcon#read 3, iclass 4, count 0 2006.285.19:49:39.94#ibcon#about to read 4, iclass 4, count 0 2006.285.19:49:39.94#ibcon#read 4, iclass 4, count 0 2006.285.19:49:39.94#ibcon#about to read 5, iclass 4, count 0 2006.285.19:49:39.94#ibcon#read 5, iclass 4, count 0 2006.285.19:49:39.94#ibcon#about to read 6, iclass 4, count 0 2006.285.19:49:39.94#ibcon#read 6, iclass 4, count 0 2006.285.19:49:39.94#ibcon#end of sib2, iclass 4, count 0 2006.285.19:49:39.94#ibcon#*after write, iclass 4, count 0 2006.285.19:49:39.94#ibcon#*before return 0, iclass 4, count 0 2006.285.19:49:39.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:49:39.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.19:49:39.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.19:49:39.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.19:49:39.94$vck44/vblo=5,709.99 2006.285.19:49:39.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.19:49:39.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.19:49:39.94#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:39.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:49:39.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:49:39.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:49:39.94#ibcon#enter wrdev, iclass 6, count 0 2006.285.19:49:39.94#ibcon#first serial, iclass 6, count 0 2006.285.19:49:39.94#ibcon#enter sib2, iclass 6, count 0 2006.285.19:49:39.94#ibcon#flushed, iclass 6, count 0 2006.285.19:49:39.94#ibcon#about to write, iclass 6, count 0 2006.285.19:49:39.94#ibcon#wrote, iclass 6, count 0 2006.285.19:49:39.94#ibcon#about to read 3, iclass 6, count 0 2006.285.19:49:39.96#ibcon#read 3, iclass 6, count 0 2006.285.19:49:40.14#ibcon#about to read 4, iclass 6, count 0 2006.285.19:49:40.14#ibcon#read 4, iclass 6, count 0 2006.285.19:49:40.14#ibcon#about to read 5, iclass 6, count 0 2006.285.19:49:40.14#ibcon#read 5, iclass 6, count 0 2006.285.19:49:40.14#ibcon#about to read 6, iclass 6, count 0 2006.285.19:49:40.14#ibcon#read 6, iclass 6, count 0 2006.285.19:49:40.14#ibcon#end of sib2, iclass 6, count 0 2006.285.19:49:40.14#ibcon#*mode == 0, iclass 6, count 0 2006.285.19:49:40.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.19:49:40.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.19:49:40.14#ibcon#*before write, iclass 6, count 0 2006.285.19:49:40.14#ibcon#enter sib2, iclass 6, count 0 2006.285.19:49:40.14#ibcon#flushed, iclass 6, count 0 2006.285.19:49:40.14#ibcon#about to write, iclass 6, count 0 2006.285.19:49:40.14#ibcon#wrote, iclass 6, count 0 2006.285.19:49:40.14#ibcon#about to read 3, iclass 6, count 0 2006.285.19:49:40.18#ibcon#read 3, iclass 6, count 0 2006.285.19:49:40.18#ibcon#about to read 4, iclass 6, count 0 2006.285.19:49:40.18#ibcon#read 4, iclass 6, count 0 2006.285.19:49:40.18#ibcon#about to read 5, iclass 6, count 0 2006.285.19:49:40.18#ibcon#read 5, iclass 6, count 0 2006.285.19:49:40.18#ibcon#about to read 6, iclass 6, count 0 2006.285.19:49:40.18#ibcon#read 6, iclass 6, count 0 2006.285.19:49:40.18#ibcon#end of sib2, iclass 6, count 0 2006.285.19:49:40.18#ibcon#*after write, iclass 6, count 0 2006.285.19:49:40.18#ibcon#*before return 0, iclass 6, count 0 2006.285.19:49:40.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:49:40.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.19:49:40.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.19:49:40.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.19:49:40.18$vck44/vb=5,4 2006.285.19:49:40.18#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.19:49:40.18#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.19:49:40.18#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:40.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:49:40.18#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:49:40.18#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:49:40.18#ibcon#enter wrdev, iclass 10, count 2 2006.285.19:49:40.18#ibcon#first serial, iclass 10, count 2 2006.285.19:49:40.18#ibcon#enter sib2, iclass 10, count 2 2006.285.19:49:40.18#ibcon#flushed, iclass 10, count 2 2006.285.19:49:40.18#ibcon#about to write, iclass 10, count 2 2006.285.19:49:40.18#ibcon#wrote, iclass 10, count 2 2006.285.19:49:40.18#ibcon#about to read 3, iclass 10, count 2 2006.285.19:49:40.20#ibcon#read 3, iclass 10, count 2 2006.285.19:49:40.20#ibcon#about to read 4, iclass 10, count 2 2006.285.19:49:40.20#ibcon#read 4, iclass 10, count 2 2006.285.19:49:40.20#ibcon#about to read 5, iclass 10, count 2 2006.285.19:49:40.20#ibcon#read 5, iclass 10, count 2 2006.285.19:49:40.20#ibcon#about to read 6, iclass 10, count 2 2006.285.19:49:40.20#ibcon#read 6, iclass 10, count 2 2006.285.19:49:40.20#ibcon#end of sib2, iclass 10, count 2 2006.285.19:49:40.20#ibcon#*mode == 0, iclass 10, count 2 2006.285.19:49:40.20#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.19:49:40.20#ibcon#[27=AT05-04\r\n] 2006.285.19:49:40.20#ibcon#*before write, iclass 10, count 2 2006.285.19:49:40.20#ibcon#enter sib2, iclass 10, count 2 2006.285.19:49:40.20#ibcon#flushed, iclass 10, count 2 2006.285.19:49:40.20#ibcon#about to write, iclass 10, count 2 2006.285.19:49:40.20#ibcon#wrote, iclass 10, count 2 2006.285.19:49:40.20#ibcon#about to read 3, iclass 10, count 2 2006.285.19:49:40.23#ibcon#read 3, iclass 10, count 2 2006.285.19:49:40.23#ibcon#about to read 4, iclass 10, count 2 2006.285.19:49:40.23#ibcon#read 4, iclass 10, count 2 2006.285.19:49:40.23#ibcon#about to read 5, iclass 10, count 2 2006.285.19:49:40.23#ibcon#read 5, iclass 10, count 2 2006.285.19:49:40.23#ibcon#about to read 6, iclass 10, count 2 2006.285.19:49:40.23#ibcon#read 6, iclass 10, count 2 2006.285.19:49:40.23#ibcon#end of sib2, iclass 10, count 2 2006.285.19:49:40.23#ibcon#*after write, iclass 10, count 2 2006.285.19:49:40.23#ibcon#*before return 0, iclass 10, count 2 2006.285.19:49:40.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:49:40.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.19:49:40.23#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.19:49:40.23#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:40.23#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:49:40.35#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:49:40.35#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:49:40.35#ibcon#enter wrdev, iclass 10, count 0 2006.285.19:49:40.35#ibcon#first serial, iclass 10, count 0 2006.285.19:49:40.35#ibcon#enter sib2, iclass 10, count 0 2006.285.19:49:40.35#ibcon#flushed, iclass 10, count 0 2006.285.19:49:40.35#ibcon#about to write, iclass 10, count 0 2006.285.19:49:40.35#ibcon#wrote, iclass 10, count 0 2006.285.19:49:40.35#ibcon#about to read 3, iclass 10, count 0 2006.285.19:49:40.37#ibcon#read 3, iclass 10, count 0 2006.285.19:49:40.37#ibcon#about to read 4, iclass 10, count 0 2006.285.19:49:40.37#ibcon#read 4, iclass 10, count 0 2006.285.19:49:40.37#ibcon#about to read 5, iclass 10, count 0 2006.285.19:49:40.37#ibcon#read 5, iclass 10, count 0 2006.285.19:49:40.37#ibcon#about to read 6, iclass 10, count 0 2006.285.19:49:40.37#ibcon#read 6, iclass 10, count 0 2006.285.19:49:40.37#ibcon#end of sib2, iclass 10, count 0 2006.285.19:49:40.37#ibcon#*mode == 0, iclass 10, count 0 2006.285.19:49:40.37#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.19:49:40.37#ibcon#[27=USB\r\n] 2006.285.19:49:40.37#ibcon#*before write, iclass 10, count 0 2006.285.19:49:40.37#ibcon#enter sib2, iclass 10, count 0 2006.285.19:49:40.37#ibcon#flushed, iclass 10, count 0 2006.285.19:49:40.37#ibcon#about to write, iclass 10, count 0 2006.285.19:49:40.37#ibcon#wrote, iclass 10, count 0 2006.285.19:49:40.37#ibcon#about to read 3, iclass 10, count 0 2006.285.19:49:40.40#ibcon#read 3, iclass 10, count 0 2006.285.19:49:40.40#ibcon#about to read 4, iclass 10, count 0 2006.285.19:49:40.40#ibcon#read 4, iclass 10, count 0 2006.285.19:49:40.40#ibcon#about to read 5, iclass 10, count 0 2006.285.19:49:40.40#ibcon#read 5, iclass 10, count 0 2006.285.19:49:40.40#ibcon#about to read 6, iclass 10, count 0 2006.285.19:49:40.40#ibcon#read 6, iclass 10, count 0 2006.285.19:49:40.40#ibcon#end of sib2, iclass 10, count 0 2006.285.19:49:40.40#ibcon#*after write, iclass 10, count 0 2006.285.19:49:40.40#ibcon#*before return 0, iclass 10, count 0 2006.285.19:49:40.40#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:49:40.40#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.19:49:40.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.19:49:40.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.19:49:40.40$vck44/vblo=6,719.99 2006.285.19:49:40.40#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.19:49:40.40#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.19:49:40.40#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:40.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:49:40.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:49:40.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:49:40.40#ibcon#enter wrdev, iclass 12, count 0 2006.285.19:49:40.40#ibcon#first serial, iclass 12, count 0 2006.285.19:49:40.40#ibcon#enter sib2, iclass 12, count 0 2006.285.19:49:40.40#ibcon#flushed, iclass 12, count 0 2006.285.19:49:40.40#ibcon#about to write, iclass 12, count 0 2006.285.19:49:40.40#ibcon#wrote, iclass 12, count 0 2006.285.19:49:40.40#ibcon#about to read 3, iclass 12, count 0 2006.285.19:49:40.42#ibcon#read 3, iclass 12, count 0 2006.285.19:49:40.42#ibcon#about to read 4, iclass 12, count 0 2006.285.19:49:40.42#ibcon#read 4, iclass 12, count 0 2006.285.19:49:40.42#ibcon#about to read 5, iclass 12, count 0 2006.285.19:49:40.42#ibcon#read 5, iclass 12, count 0 2006.285.19:49:40.42#ibcon#about to read 6, iclass 12, count 0 2006.285.19:49:40.42#ibcon#read 6, iclass 12, count 0 2006.285.19:49:40.42#ibcon#end of sib2, iclass 12, count 0 2006.285.19:49:40.42#ibcon#*mode == 0, iclass 12, count 0 2006.285.19:49:40.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.19:49:40.42#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.19:49:40.42#ibcon#*before write, iclass 12, count 0 2006.285.19:49:40.42#ibcon#enter sib2, iclass 12, count 0 2006.285.19:49:40.42#ibcon#flushed, iclass 12, count 0 2006.285.19:49:40.42#ibcon#about to write, iclass 12, count 0 2006.285.19:49:40.42#ibcon#wrote, iclass 12, count 0 2006.285.19:49:40.42#ibcon#about to read 3, iclass 12, count 0 2006.285.19:49:40.46#ibcon#read 3, iclass 12, count 0 2006.285.19:49:40.46#ibcon#about to read 4, iclass 12, count 0 2006.285.19:49:40.46#ibcon#read 4, iclass 12, count 0 2006.285.19:49:40.46#ibcon#about to read 5, iclass 12, count 0 2006.285.19:49:40.46#ibcon#read 5, iclass 12, count 0 2006.285.19:49:40.46#ibcon#about to read 6, iclass 12, count 0 2006.285.19:49:40.46#ibcon#read 6, iclass 12, count 0 2006.285.19:49:40.46#ibcon#end of sib2, iclass 12, count 0 2006.285.19:49:40.46#ibcon#*after write, iclass 12, count 0 2006.285.19:49:40.46#ibcon#*before return 0, iclass 12, count 0 2006.285.19:49:40.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:49:40.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.19:49:40.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.19:49:40.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.19:49:40.46$vck44/vb=6,3 2006.285.19:49:40.46#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.19:49:40.46#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.19:49:40.46#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:40.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:49:40.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:49:40.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:49:40.52#ibcon#enter wrdev, iclass 14, count 2 2006.285.19:49:40.52#ibcon#first serial, iclass 14, count 2 2006.285.19:49:40.52#ibcon#enter sib2, iclass 14, count 2 2006.285.19:49:40.52#ibcon#flushed, iclass 14, count 2 2006.285.19:49:40.52#ibcon#about to write, iclass 14, count 2 2006.285.19:49:40.52#ibcon#wrote, iclass 14, count 2 2006.285.19:49:40.52#ibcon#about to read 3, iclass 14, count 2 2006.285.19:49:40.54#ibcon#read 3, iclass 14, count 2 2006.285.19:49:40.54#ibcon#about to read 4, iclass 14, count 2 2006.285.19:49:40.54#ibcon#read 4, iclass 14, count 2 2006.285.19:49:40.54#ibcon#about to read 5, iclass 14, count 2 2006.285.19:49:40.54#ibcon#read 5, iclass 14, count 2 2006.285.19:49:40.54#ibcon#about to read 6, iclass 14, count 2 2006.285.19:49:40.54#ibcon#read 6, iclass 14, count 2 2006.285.19:49:40.54#ibcon#end of sib2, iclass 14, count 2 2006.285.19:49:40.54#ibcon#*mode == 0, iclass 14, count 2 2006.285.19:49:40.54#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.19:49:40.54#ibcon#[27=AT06-03\r\n] 2006.285.19:49:40.54#ibcon#*before write, iclass 14, count 2 2006.285.19:49:40.54#ibcon#enter sib2, iclass 14, count 2 2006.285.19:49:40.54#ibcon#flushed, iclass 14, count 2 2006.285.19:49:40.54#ibcon#about to write, iclass 14, count 2 2006.285.19:49:40.54#ibcon#wrote, iclass 14, count 2 2006.285.19:49:40.54#ibcon#about to read 3, iclass 14, count 2 2006.285.19:49:40.57#ibcon#read 3, iclass 14, count 2 2006.285.19:49:40.57#ibcon#about to read 4, iclass 14, count 2 2006.285.19:49:40.57#ibcon#read 4, iclass 14, count 2 2006.285.19:49:40.57#ibcon#about to read 5, iclass 14, count 2 2006.285.19:49:40.57#ibcon#read 5, iclass 14, count 2 2006.285.19:49:40.57#ibcon#about to read 6, iclass 14, count 2 2006.285.19:49:40.57#ibcon#read 6, iclass 14, count 2 2006.285.19:49:40.57#ibcon#end of sib2, iclass 14, count 2 2006.285.19:49:40.57#ibcon#*after write, iclass 14, count 2 2006.285.19:49:40.57#ibcon#*before return 0, iclass 14, count 2 2006.285.19:49:40.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:49:40.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.19:49:40.57#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.19:49:40.57#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:40.57#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:49:40.69#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:49:40.69#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:49:40.69#ibcon#enter wrdev, iclass 14, count 0 2006.285.19:49:40.69#ibcon#first serial, iclass 14, count 0 2006.285.19:49:40.69#ibcon#enter sib2, iclass 14, count 0 2006.285.19:49:40.69#ibcon#flushed, iclass 14, count 0 2006.285.19:49:40.69#ibcon#about to write, iclass 14, count 0 2006.285.19:49:40.69#ibcon#wrote, iclass 14, count 0 2006.285.19:49:40.69#ibcon#about to read 3, iclass 14, count 0 2006.285.19:49:40.71#ibcon#read 3, iclass 14, count 0 2006.285.19:49:40.71#ibcon#about to read 4, iclass 14, count 0 2006.285.19:49:40.71#ibcon#read 4, iclass 14, count 0 2006.285.19:49:40.71#ibcon#about to read 5, iclass 14, count 0 2006.285.19:49:40.71#ibcon#read 5, iclass 14, count 0 2006.285.19:49:40.71#ibcon#about to read 6, iclass 14, count 0 2006.285.19:49:40.71#ibcon#read 6, iclass 14, count 0 2006.285.19:49:40.71#ibcon#end of sib2, iclass 14, count 0 2006.285.19:49:40.71#ibcon#*mode == 0, iclass 14, count 0 2006.285.19:49:40.71#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.19:49:40.71#ibcon#[27=USB\r\n] 2006.285.19:49:40.71#ibcon#*before write, iclass 14, count 0 2006.285.19:49:40.71#ibcon#enter sib2, iclass 14, count 0 2006.285.19:49:40.71#ibcon#flushed, iclass 14, count 0 2006.285.19:49:40.71#ibcon#about to write, iclass 14, count 0 2006.285.19:49:40.71#ibcon#wrote, iclass 14, count 0 2006.285.19:49:40.71#ibcon#about to read 3, iclass 14, count 0 2006.285.19:49:40.74#ibcon#read 3, iclass 14, count 0 2006.285.19:49:40.74#ibcon#about to read 4, iclass 14, count 0 2006.285.19:49:40.74#ibcon#read 4, iclass 14, count 0 2006.285.19:49:40.74#ibcon#about to read 5, iclass 14, count 0 2006.285.19:49:40.74#ibcon#read 5, iclass 14, count 0 2006.285.19:49:40.74#ibcon#about to read 6, iclass 14, count 0 2006.285.19:49:40.74#ibcon#read 6, iclass 14, count 0 2006.285.19:49:40.74#ibcon#end of sib2, iclass 14, count 0 2006.285.19:49:40.74#ibcon#*after write, iclass 14, count 0 2006.285.19:49:40.74#ibcon#*before return 0, iclass 14, count 0 2006.285.19:49:40.74#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:49:40.74#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.19:49:40.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.19:49:40.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.19:49:40.74$vck44/vblo=7,734.99 2006.285.19:49:40.74#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.19:49:40.74#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.19:49:40.74#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:40.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:49:40.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:49:40.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:49:40.74#ibcon#enter wrdev, iclass 16, count 0 2006.285.19:49:40.74#ibcon#first serial, iclass 16, count 0 2006.285.19:49:40.74#ibcon#enter sib2, iclass 16, count 0 2006.285.19:49:40.74#ibcon#flushed, iclass 16, count 0 2006.285.19:49:40.74#ibcon#about to write, iclass 16, count 0 2006.285.19:49:40.74#ibcon#wrote, iclass 16, count 0 2006.285.19:49:40.74#ibcon#about to read 3, iclass 16, count 0 2006.285.19:49:40.76#ibcon#read 3, iclass 16, count 0 2006.285.19:49:40.76#ibcon#about to read 4, iclass 16, count 0 2006.285.19:49:40.76#ibcon#read 4, iclass 16, count 0 2006.285.19:49:40.76#ibcon#about to read 5, iclass 16, count 0 2006.285.19:49:40.76#ibcon#read 5, iclass 16, count 0 2006.285.19:49:40.76#ibcon#about to read 6, iclass 16, count 0 2006.285.19:49:40.76#ibcon#read 6, iclass 16, count 0 2006.285.19:49:40.76#ibcon#end of sib2, iclass 16, count 0 2006.285.19:49:40.76#ibcon#*mode == 0, iclass 16, count 0 2006.285.19:49:40.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.19:49:40.76#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.19:49:40.76#ibcon#*before write, iclass 16, count 0 2006.285.19:49:40.76#ibcon#enter sib2, iclass 16, count 0 2006.285.19:49:40.76#ibcon#flushed, iclass 16, count 0 2006.285.19:49:40.76#ibcon#about to write, iclass 16, count 0 2006.285.19:49:40.76#ibcon#wrote, iclass 16, count 0 2006.285.19:49:40.76#ibcon#about to read 3, iclass 16, count 0 2006.285.19:49:40.80#ibcon#read 3, iclass 16, count 0 2006.285.19:49:40.80#ibcon#about to read 4, iclass 16, count 0 2006.285.19:49:40.80#ibcon#read 4, iclass 16, count 0 2006.285.19:49:40.80#ibcon#about to read 5, iclass 16, count 0 2006.285.19:49:40.80#ibcon#read 5, iclass 16, count 0 2006.285.19:49:40.80#ibcon#about to read 6, iclass 16, count 0 2006.285.19:49:40.80#ibcon#read 6, iclass 16, count 0 2006.285.19:49:40.80#ibcon#end of sib2, iclass 16, count 0 2006.285.19:49:40.80#ibcon#*after write, iclass 16, count 0 2006.285.19:49:40.80#ibcon#*before return 0, iclass 16, count 0 2006.285.19:49:40.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:49:40.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.19:49:40.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.19:49:40.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.19:49:40.80$vck44/vb=7,4 2006.285.19:49:40.80#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.19:49:40.80#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.19:49:40.80#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:40.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:49:40.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:49:40.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:49:40.86#ibcon#enter wrdev, iclass 18, count 2 2006.285.19:49:40.86#ibcon#first serial, iclass 18, count 2 2006.285.19:49:40.86#ibcon#enter sib2, iclass 18, count 2 2006.285.19:49:40.86#ibcon#flushed, iclass 18, count 2 2006.285.19:49:40.86#ibcon#about to write, iclass 18, count 2 2006.285.19:49:40.86#ibcon#wrote, iclass 18, count 2 2006.285.19:49:40.86#ibcon#about to read 3, iclass 18, count 2 2006.285.19:49:40.88#ibcon#read 3, iclass 18, count 2 2006.285.19:49:40.88#ibcon#about to read 4, iclass 18, count 2 2006.285.19:49:40.88#ibcon#read 4, iclass 18, count 2 2006.285.19:49:40.88#ibcon#about to read 5, iclass 18, count 2 2006.285.19:49:40.88#ibcon#read 5, iclass 18, count 2 2006.285.19:49:40.88#ibcon#about to read 6, iclass 18, count 2 2006.285.19:49:40.88#ibcon#read 6, iclass 18, count 2 2006.285.19:49:40.88#ibcon#end of sib2, iclass 18, count 2 2006.285.19:49:40.88#ibcon#*mode == 0, iclass 18, count 2 2006.285.19:49:40.88#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.19:49:40.88#ibcon#[27=AT07-04\r\n] 2006.285.19:49:40.88#ibcon#*before write, iclass 18, count 2 2006.285.19:49:40.88#ibcon#enter sib2, iclass 18, count 2 2006.285.19:49:40.88#ibcon#flushed, iclass 18, count 2 2006.285.19:49:40.88#ibcon#about to write, iclass 18, count 2 2006.285.19:49:40.88#ibcon#wrote, iclass 18, count 2 2006.285.19:49:40.88#ibcon#about to read 3, iclass 18, count 2 2006.285.19:49:40.91#ibcon#read 3, iclass 18, count 2 2006.285.19:49:40.91#ibcon#about to read 4, iclass 18, count 2 2006.285.19:49:40.91#ibcon#read 4, iclass 18, count 2 2006.285.19:49:40.91#ibcon#about to read 5, iclass 18, count 2 2006.285.19:49:40.91#ibcon#read 5, iclass 18, count 2 2006.285.19:49:40.91#ibcon#about to read 6, iclass 18, count 2 2006.285.19:49:40.91#ibcon#read 6, iclass 18, count 2 2006.285.19:49:40.91#ibcon#end of sib2, iclass 18, count 2 2006.285.19:49:40.91#ibcon#*after write, iclass 18, count 2 2006.285.19:49:40.91#ibcon#*before return 0, iclass 18, count 2 2006.285.19:49:40.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:49:40.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.19:49:40.91#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.19:49:40.91#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:40.91#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:49:41.03#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:49:41.03#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:49:41.03#ibcon#enter wrdev, iclass 18, count 0 2006.285.19:49:41.03#ibcon#first serial, iclass 18, count 0 2006.285.19:49:41.03#ibcon#enter sib2, iclass 18, count 0 2006.285.19:49:41.03#ibcon#flushed, iclass 18, count 0 2006.285.19:49:41.03#ibcon#about to write, iclass 18, count 0 2006.285.19:49:41.03#ibcon#wrote, iclass 18, count 0 2006.285.19:49:41.03#ibcon#about to read 3, iclass 18, count 0 2006.285.19:49:41.05#ibcon#read 3, iclass 18, count 0 2006.285.19:49:41.05#ibcon#about to read 4, iclass 18, count 0 2006.285.19:49:41.05#ibcon#read 4, iclass 18, count 0 2006.285.19:49:41.05#ibcon#about to read 5, iclass 18, count 0 2006.285.19:49:41.05#ibcon#read 5, iclass 18, count 0 2006.285.19:49:41.05#ibcon#about to read 6, iclass 18, count 0 2006.285.19:49:41.05#ibcon#read 6, iclass 18, count 0 2006.285.19:49:41.10#ibcon#end of sib2, iclass 18, count 0 2006.285.19:49:41.10#ibcon#*mode == 0, iclass 18, count 0 2006.285.19:49:41.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.19:49:41.10#ibcon#[27=USB\r\n] 2006.285.19:49:41.10#ibcon#*before write, iclass 18, count 0 2006.285.19:49:41.10#ibcon#enter sib2, iclass 18, count 0 2006.285.19:49:41.10#ibcon#flushed, iclass 18, count 0 2006.285.19:49:41.10#ibcon#about to write, iclass 18, count 0 2006.285.19:49:41.10#ibcon#wrote, iclass 18, count 0 2006.285.19:49:41.10#ibcon#about to read 3, iclass 18, count 0 2006.285.19:49:41.12#ibcon#read 3, iclass 18, count 0 2006.285.19:49:41.12#ibcon#about to read 4, iclass 18, count 0 2006.285.19:49:41.12#ibcon#read 4, iclass 18, count 0 2006.285.19:49:41.12#ibcon#about to read 5, iclass 18, count 0 2006.285.19:49:41.12#ibcon#read 5, iclass 18, count 0 2006.285.19:49:41.12#ibcon#about to read 6, iclass 18, count 0 2006.285.19:49:41.12#ibcon#read 6, iclass 18, count 0 2006.285.19:49:41.12#ibcon#end of sib2, iclass 18, count 0 2006.285.19:49:41.12#ibcon#*after write, iclass 18, count 0 2006.285.19:49:41.12#ibcon#*before return 0, iclass 18, count 0 2006.285.19:49:41.12#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:49:41.12#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.19:49:41.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.19:49:41.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.19:49:41.12$vck44/vblo=8,744.99 2006.285.19:49:41.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.19:49:41.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.19:49:41.12#ibcon#ireg 17 cls_cnt 0 2006.285.19:49:41.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:49:41.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:49:41.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:49:41.12#ibcon#enter wrdev, iclass 20, count 0 2006.285.19:49:41.12#ibcon#first serial, iclass 20, count 0 2006.285.19:49:41.12#ibcon#enter sib2, iclass 20, count 0 2006.285.19:49:41.12#ibcon#flushed, iclass 20, count 0 2006.285.19:49:41.12#ibcon#about to write, iclass 20, count 0 2006.285.19:49:41.12#ibcon#wrote, iclass 20, count 0 2006.285.19:49:41.12#ibcon#about to read 3, iclass 20, count 0 2006.285.19:49:41.14#ibcon#read 3, iclass 20, count 0 2006.285.19:49:41.14#ibcon#about to read 4, iclass 20, count 0 2006.285.19:49:41.14#ibcon#read 4, iclass 20, count 0 2006.285.19:49:41.14#ibcon#about to read 5, iclass 20, count 0 2006.285.19:49:41.14#ibcon#read 5, iclass 20, count 0 2006.285.19:49:41.14#ibcon#about to read 6, iclass 20, count 0 2006.285.19:49:41.14#ibcon#read 6, iclass 20, count 0 2006.285.19:49:41.14#ibcon#end of sib2, iclass 20, count 0 2006.285.19:49:41.14#ibcon#*mode == 0, iclass 20, count 0 2006.285.19:49:41.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.19:49:41.14#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.19:49:41.14#ibcon#*before write, iclass 20, count 0 2006.285.19:49:41.14#ibcon#enter sib2, iclass 20, count 0 2006.285.19:49:41.14#ibcon#flushed, iclass 20, count 0 2006.285.19:49:41.14#ibcon#about to write, iclass 20, count 0 2006.285.19:49:41.14#ibcon#wrote, iclass 20, count 0 2006.285.19:49:41.14#ibcon#about to read 3, iclass 20, count 0 2006.285.19:49:41.18#ibcon#read 3, iclass 20, count 0 2006.285.19:49:41.18#ibcon#about to read 4, iclass 20, count 0 2006.285.19:49:41.18#ibcon#read 4, iclass 20, count 0 2006.285.19:49:41.18#ibcon#about to read 5, iclass 20, count 0 2006.285.19:49:41.18#ibcon#read 5, iclass 20, count 0 2006.285.19:49:41.18#ibcon#about to read 6, iclass 20, count 0 2006.285.19:49:41.18#ibcon#read 6, iclass 20, count 0 2006.285.19:49:41.18#ibcon#end of sib2, iclass 20, count 0 2006.285.19:49:41.18#ibcon#*after write, iclass 20, count 0 2006.285.19:49:41.18#ibcon#*before return 0, iclass 20, count 0 2006.285.19:49:41.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:49:41.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.19:49:41.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.19:49:41.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.19:49:41.18$vck44/vb=8,4 2006.285.19:49:41.18#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.19:49:41.18#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.19:49:41.18#ibcon#ireg 11 cls_cnt 2 2006.285.19:49:41.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:49:41.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:49:41.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:49:41.24#ibcon#enter wrdev, iclass 22, count 2 2006.285.19:49:41.24#ibcon#first serial, iclass 22, count 2 2006.285.19:49:41.24#ibcon#enter sib2, iclass 22, count 2 2006.285.19:49:41.24#ibcon#flushed, iclass 22, count 2 2006.285.19:49:41.24#ibcon#about to write, iclass 22, count 2 2006.285.19:49:41.24#ibcon#wrote, iclass 22, count 2 2006.285.19:49:41.24#ibcon#about to read 3, iclass 22, count 2 2006.285.19:49:41.26#ibcon#read 3, iclass 22, count 2 2006.285.19:49:41.26#ibcon#about to read 4, iclass 22, count 2 2006.285.19:49:41.26#ibcon#read 4, iclass 22, count 2 2006.285.19:49:41.26#ibcon#about to read 5, iclass 22, count 2 2006.285.19:49:41.26#ibcon#read 5, iclass 22, count 2 2006.285.19:49:41.26#ibcon#about to read 6, iclass 22, count 2 2006.285.19:49:41.26#ibcon#read 6, iclass 22, count 2 2006.285.19:49:41.26#ibcon#end of sib2, iclass 22, count 2 2006.285.19:49:41.26#ibcon#*mode == 0, iclass 22, count 2 2006.285.19:49:41.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.19:49:41.26#ibcon#[27=AT08-04\r\n] 2006.285.19:49:41.26#ibcon#*before write, iclass 22, count 2 2006.285.19:49:41.26#ibcon#enter sib2, iclass 22, count 2 2006.285.19:49:41.26#ibcon#flushed, iclass 22, count 2 2006.285.19:49:41.26#ibcon#about to write, iclass 22, count 2 2006.285.19:49:41.26#ibcon#wrote, iclass 22, count 2 2006.285.19:49:41.26#ibcon#about to read 3, iclass 22, count 2 2006.285.19:49:41.29#ibcon#read 3, iclass 22, count 2 2006.285.19:49:41.29#ibcon#about to read 4, iclass 22, count 2 2006.285.19:49:41.29#ibcon#read 4, iclass 22, count 2 2006.285.19:49:41.29#ibcon#about to read 5, iclass 22, count 2 2006.285.19:49:41.29#ibcon#read 5, iclass 22, count 2 2006.285.19:49:41.29#ibcon#about to read 6, iclass 22, count 2 2006.285.19:49:41.29#ibcon#read 6, iclass 22, count 2 2006.285.19:49:41.29#ibcon#end of sib2, iclass 22, count 2 2006.285.19:49:41.29#ibcon#*after write, iclass 22, count 2 2006.285.19:49:41.29#ibcon#*before return 0, iclass 22, count 2 2006.285.19:49:41.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:49:41.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.19:49:41.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.19:49:41.29#ibcon#ireg 7 cls_cnt 0 2006.285.19:49:41.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:49:41.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:49:41.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:49:41.41#ibcon#enter wrdev, iclass 22, count 0 2006.285.19:49:41.41#ibcon#first serial, iclass 22, count 0 2006.285.19:49:41.41#ibcon#enter sib2, iclass 22, count 0 2006.285.19:49:41.41#ibcon#flushed, iclass 22, count 0 2006.285.19:49:41.41#ibcon#about to write, iclass 22, count 0 2006.285.19:49:41.41#ibcon#wrote, iclass 22, count 0 2006.285.19:49:41.41#ibcon#about to read 3, iclass 22, count 0 2006.285.19:49:41.43#ibcon#read 3, iclass 22, count 0 2006.285.19:49:41.43#ibcon#about to read 4, iclass 22, count 0 2006.285.19:49:41.43#ibcon#read 4, iclass 22, count 0 2006.285.19:49:41.43#ibcon#about to read 5, iclass 22, count 0 2006.285.19:49:41.43#ibcon#read 5, iclass 22, count 0 2006.285.19:49:41.43#ibcon#about to read 6, iclass 22, count 0 2006.285.19:49:41.43#ibcon#read 6, iclass 22, count 0 2006.285.19:49:41.43#ibcon#end of sib2, iclass 22, count 0 2006.285.19:49:41.43#ibcon#*mode == 0, iclass 22, count 0 2006.285.19:49:41.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.19:49:41.43#ibcon#[27=USB\r\n] 2006.285.19:49:41.43#ibcon#*before write, iclass 22, count 0 2006.285.19:49:41.43#ibcon#enter sib2, iclass 22, count 0 2006.285.19:49:41.43#ibcon#flushed, iclass 22, count 0 2006.285.19:49:41.43#ibcon#about to write, iclass 22, count 0 2006.285.19:49:41.43#ibcon#wrote, iclass 22, count 0 2006.285.19:49:41.43#ibcon#about to read 3, iclass 22, count 0 2006.285.19:49:41.46#ibcon#read 3, iclass 22, count 0 2006.285.19:49:41.46#ibcon#about to read 4, iclass 22, count 0 2006.285.19:49:41.46#ibcon#read 4, iclass 22, count 0 2006.285.19:49:41.46#ibcon#about to read 5, iclass 22, count 0 2006.285.19:49:41.46#ibcon#read 5, iclass 22, count 0 2006.285.19:49:41.46#ibcon#about to read 6, iclass 22, count 0 2006.285.19:49:41.46#ibcon#read 6, iclass 22, count 0 2006.285.19:49:41.46#ibcon#end of sib2, iclass 22, count 0 2006.285.19:49:41.46#ibcon#*after write, iclass 22, count 0 2006.285.19:49:41.46#ibcon#*before return 0, iclass 22, count 0 2006.285.19:49:41.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:49:41.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.19:49:41.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.19:49:41.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.19:49:41.46$vck44/vabw=wide 2006.285.19:49:41.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.19:49:41.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.19:49:41.46#ibcon#ireg 8 cls_cnt 0 2006.285.19:49:41.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:49:41.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:49:41.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:49:41.46#ibcon#enter wrdev, iclass 24, count 0 2006.285.19:49:41.46#ibcon#first serial, iclass 24, count 0 2006.285.19:49:41.46#ibcon#enter sib2, iclass 24, count 0 2006.285.19:49:41.46#ibcon#flushed, iclass 24, count 0 2006.285.19:49:41.46#ibcon#about to write, iclass 24, count 0 2006.285.19:49:41.46#ibcon#wrote, iclass 24, count 0 2006.285.19:49:41.46#ibcon#about to read 3, iclass 24, count 0 2006.285.19:49:41.48#ibcon#read 3, iclass 24, count 0 2006.285.19:49:41.48#ibcon#about to read 4, iclass 24, count 0 2006.285.19:49:41.48#ibcon#read 4, iclass 24, count 0 2006.285.19:49:41.48#ibcon#about to read 5, iclass 24, count 0 2006.285.19:49:41.48#ibcon#read 5, iclass 24, count 0 2006.285.19:49:41.48#ibcon#about to read 6, iclass 24, count 0 2006.285.19:49:41.48#ibcon#read 6, iclass 24, count 0 2006.285.19:49:41.48#ibcon#end of sib2, iclass 24, count 0 2006.285.19:49:41.48#ibcon#*mode == 0, iclass 24, count 0 2006.285.19:49:41.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.19:49:41.48#ibcon#[25=BW32\r\n] 2006.285.19:49:41.48#ibcon#*before write, iclass 24, count 0 2006.285.19:49:41.48#ibcon#enter sib2, iclass 24, count 0 2006.285.19:49:41.48#ibcon#flushed, iclass 24, count 0 2006.285.19:49:41.48#ibcon#about to write, iclass 24, count 0 2006.285.19:49:41.48#ibcon#wrote, iclass 24, count 0 2006.285.19:49:41.48#ibcon#about to read 3, iclass 24, count 0 2006.285.19:49:41.51#ibcon#read 3, iclass 24, count 0 2006.285.19:49:41.51#ibcon#about to read 4, iclass 24, count 0 2006.285.19:49:41.51#ibcon#read 4, iclass 24, count 0 2006.285.19:49:41.51#ibcon#about to read 5, iclass 24, count 0 2006.285.19:49:41.51#ibcon#read 5, iclass 24, count 0 2006.285.19:49:41.51#ibcon#about to read 6, iclass 24, count 0 2006.285.19:49:41.51#ibcon#read 6, iclass 24, count 0 2006.285.19:49:41.51#ibcon#end of sib2, iclass 24, count 0 2006.285.19:49:41.51#ibcon#*after write, iclass 24, count 0 2006.285.19:49:41.51#ibcon#*before return 0, iclass 24, count 0 2006.285.19:49:41.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:49:41.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:49:41.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.19:49:41.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.19:49:41.51$vck44/vbbw=wide 2006.285.19:49:41.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.19:49:41.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.19:49:41.51#ibcon#ireg 8 cls_cnt 0 2006.285.19:49:41.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:49:41.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:49:41.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:49:41.58#ibcon#enter wrdev, iclass 26, count 0 2006.285.19:49:41.58#ibcon#first serial, iclass 26, count 0 2006.285.19:49:41.58#ibcon#enter sib2, iclass 26, count 0 2006.285.19:49:41.58#ibcon#flushed, iclass 26, count 0 2006.285.19:49:41.58#ibcon#about to write, iclass 26, count 0 2006.285.19:49:41.58#ibcon#wrote, iclass 26, count 0 2006.285.19:49:41.58#ibcon#about to read 3, iclass 26, count 0 2006.285.19:49:41.60#ibcon#read 3, iclass 26, count 0 2006.285.19:49:41.60#ibcon#about to read 4, iclass 26, count 0 2006.285.19:49:41.60#ibcon#read 4, iclass 26, count 0 2006.285.19:49:41.60#ibcon#about to read 5, iclass 26, count 0 2006.285.19:49:41.60#ibcon#read 5, iclass 26, count 0 2006.285.19:49:41.60#ibcon#about to read 6, iclass 26, count 0 2006.285.19:49:41.60#ibcon#read 6, iclass 26, count 0 2006.285.19:49:41.60#ibcon#end of sib2, iclass 26, count 0 2006.285.19:49:41.60#ibcon#*mode == 0, iclass 26, count 0 2006.285.19:49:41.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.19:49:41.60#ibcon#[27=BW32\r\n] 2006.285.19:49:41.60#ibcon#*before write, iclass 26, count 0 2006.285.19:49:41.60#ibcon#enter sib2, iclass 26, count 0 2006.285.19:49:41.60#ibcon#flushed, iclass 26, count 0 2006.285.19:49:41.60#ibcon#about to write, iclass 26, count 0 2006.285.19:49:41.60#ibcon#wrote, iclass 26, count 0 2006.285.19:49:41.60#ibcon#about to read 3, iclass 26, count 0 2006.285.19:49:41.63#ibcon#read 3, iclass 26, count 0 2006.285.19:49:41.63#ibcon#about to read 4, iclass 26, count 0 2006.285.19:49:41.63#ibcon#read 4, iclass 26, count 0 2006.285.19:49:41.63#ibcon#about to read 5, iclass 26, count 0 2006.285.19:49:41.63#ibcon#read 5, iclass 26, count 0 2006.285.19:49:41.63#ibcon#about to read 6, iclass 26, count 0 2006.285.19:49:41.63#ibcon#read 6, iclass 26, count 0 2006.285.19:49:41.63#ibcon#end of sib2, iclass 26, count 0 2006.285.19:49:41.63#ibcon#*after write, iclass 26, count 0 2006.285.19:49:41.63#ibcon#*before return 0, iclass 26, count 0 2006.285.19:49:41.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:49:41.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:49:41.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.19:49:41.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.19:49:41.63$setupk4/ifdk4 2006.285.19:49:41.63$ifdk4/lo= 2006.285.19:49:41.63$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.19:49:41.63$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.19:49:41.63$ifdk4/patch= 2006.285.19:49:41.63$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.19:49:41.63$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.19:49:41.63$setupk4/!*+20s 2006.285.19:49:47.60#abcon#<5=/13 0.4 0.8 14.721001015.2\r\n> 2006.285.19:49:47.62#abcon#{5=INTERFACE CLEAR} 2006.285.19:49:47.68#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:49:50.14#trakl#Source acquired 2006.285.19:49:52.14#flagr#flagr/antenna,acquired 2006.285.19:49:55.19$setupk4/"tpicd 2006.285.19:49:55.19$setupk4/echo=off 2006.285.19:49:55.19$setupk4/xlog=off 2006.285.19:49:55.19:!2006.285.19:53:29 2006.285.19:53:29.00:preob 2006.285.19:53:29.14/onsource/TRACKING 2006.285.19:53:29.14:!2006.285.19:53:39 2006.285.19:53:39.00:"tape 2006.285.19:53:39.00:"st=record 2006.285.19:53:39.00:data_valid=on 2006.285.19:53:39.00:midob 2006.285.19:53:40.14/onsource/TRACKING 2006.285.19:53:40.14/wx/14.65,1015.2,100 2006.285.19:53:40.28/cable/+6.5087E-03 2006.285.19:53:41.37/va/01,07,usb,yes,32,35 2006.285.19:53:41.37/va/02,06,usb,yes,33,33 2006.285.19:53:41.37/va/03,07,usb,yes,32,34 2006.285.19:53:41.37/va/04,06,usb,yes,34,35 2006.285.19:53:41.37/va/05,03,usb,yes,33,33 2006.285.19:53:41.37/va/06,04,usb,yes,30,29 2006.285.19:53:41.37/va/07,04,usb,yes,30,31 2006.285.19:53:41.37/va/08,03,usb,yes,31,38 2006.285.19:53:41.60/valo/01,524.99,yes,locked 2006.285.19:53:41.60/valo/02,534.99,yes,locked 2006.285.19:53:41.60/valo/03,564.99,yes,locked 2006.285.19:53:41.60/valo/04,624.99,yes,locked 2006.285.19:53:41.60/valo/05,734.99,yes,locked 2006.285.19:53:41.60/valo/06,814.99,yes,locked 2006.285.19:53:41.60/valo/07,864.99,yes,locked 2006.285.19:53:41.60/valo/08,884.99,yes,locked 2006.285.19:53:42.69/vb/01,04,usb,yes,31,28 2006.285.19:53:42.69/vb/02,05,usb,yes,28,29 2006.285.19:53:42.69/vb/03,04,usb,yes,29,32 2006.285.19:53:42.69/vb/04,05,usb,yes,30,29 2006.285.19:53:42.69/vb/05,04,usb,yes,26,28 2006.285.19:53:42.69/vb/06,03,usb,yes,37,33 2006.285.19:53:42.69/vb/07,04,usb,yes,30,30 2006.285.19:53:42.69/vb/08,04,usb,yes,27,31 2006.285.19:53:42.93/vblo/01,629.99,yes,locked 2006.285.19:53:42.93/vblo/02,634.99,yes,locked 2006.285.19:53:42.93/vblo/03,649.99,yes,locked 2006.285.19:53:42.93/vblo/04,679.99,yes,locked 2006.285.19:53:42.93/vblo/05,709.99,yes,locked 2006.285.19:53:42.93/vblo/06,719.99,yes,locked 2006.285.19:53:42.93/vblo/07,734.99,yes,locked 2006.285.19:53:42.93/vblo/08,744.99,yes,locked 2006.285.19:53:43.08/vabw/8 2006.285.19:53:43.23/vbbw/8 2006.285.19:53:43.32/xfe/off,on,12.0 2006.285.19:53:43.69/ifatt/23,28,28,28 2006.285.19:53:44.07/fmout-gps/S +2.73E-07 2006.285.19:53:44.09:!2006.285.19:54:39 2006.285.19:54:39.00:data_valid=off 2006.285.19:54:39.00:"et 2006.285.19:54:39.00:!+3s 2006.285.19:54:42.01:"tape 2006.285.19:54:42.01:postob 2006.285.19:54:42.12/cable/+6.5070E-03 2006.285.19:54:42.12/wx/14.63,1015.2,100 2006.285.19:54:43.08/fmout-gps/S +2.72E-07 2006.285.19:54:43.08:scan_name=285-1956,jd0610,100 2006.285.19:54:43.08:source=0528+134,053056.42,133155.1,2000.0,cw 2006.285.19:54:43.14#flagr#flagr/antenna,new-source 2006.285.19:54:44.14:checkk5 2006.285.19:54:44.61/chk_autoobs//k5ts1/ autoobs is running! 2006.285.19:54:45.18/chk_autoobs//k5ts2/ autoobs is running! 2006.285.19:54:45.53/chk_autoobs//k5ts3/ autoobs is running! 2006.285.19:54:45.98/chk_autoobs//k5ts4/ autoobs is running! 2006.285.19:54:46.54/chk_obsdata//k5ts1/T2851953??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.19:54:46.87/chk_obsdata//k5ts2/T2851953??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.19:54:47.34/chk_obsdata//k5ts3/T2851953??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.19:54:47.89/chk_obsdata//k5ts4/T2851953??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.19:54:48.80/k5log//k5ts1_log_newline 2006.285.19:54:49.80/k5log//k5ts2_log_newline 2006.285.19:54:50.50/k5log//k5ts3_log_newline 2006.285.19:54:51.21/k5log//k5ts4_log_newline 2006.285.19:54:51.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.19:54:51.23:setupk4=1 2006.285.19:54:51.23$setupk4/echo=on 2006.285.19:54:51.23$setupk4/pcalon 2006.285.19:54:51.23$pcalon/"no phase cal control is implemented here 2006.285.19:54:51.23$setupk4/"tpicd=stop 2006.285.19:54:51.23$setupk4/"rec=synch_on 2006.285.19:54:51.23$setupk4/"rec_mode=128 2006.285.19:54:51.23$setupk4/!* 2006.285.19:54:51.23$setupk4/recpk4 2006.285.19:54:51.23$recpk4/recpatch= 2006.285.19:54:51.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.19:54:51.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.19:54:51.23$setupk4/vck44 2006.285.19:54:51.23$vck44/valo=1,524.99 2006.285.19:54:51.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.19:54:51.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.19:54:51.23#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:51.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:54:51.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:54:51.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:54:51.23#ibcon#enter wrdev, iclass 5, count 0 2006.285.19:54:51.23#ibcon#first serial, iclass 5, count 0 2006.285.19:54:51.23#ibcon#enter sib2, iclass 5, count 0 2006.285.19:54:51.23#ibcon#flushed, iclass 5, count 0 2006.285.19:54:51.23#ibcon#about to write, iclass 5, count 0 2006.285.19:54:51.23#ibcon#wrote, iclass 5, count 0 2006.285.19:54:51.23#ibcon#about to read 3, iclass 5, count 0 2006.285.19:54:51.25#ibcon#read 3, iclass 5, count 0 2006.285.19:54:51.25#ibcon#about to read 4, iclass 5, count 0 2006.285.19:54:51.25#ibcon#read 4, iclass 5, count 0 2006.285.19:54:51.25#ibcon#about to read 5, iclass 5, count 0 2006.285.19:54:51.25#ibcon#read 5, iclass 5, count 0 2006.285.19:54:51.25#ibcon#about to read 6, iclass 5, count 0 2006.285.19:54:51.25#ibcon#read 6, iclass 5, count 0 2006.285.19:54:51.25#ibcon#end of sib2, iclass 5, count 0 2006.285.19:54:51.25#ibcon#*mode == 0, iclass 5, count 0 2006.285.19:54:51.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.19:54:51.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.19:54:51.25#ibcon#*before write, iclass 5, count 0 2006.285.19:54:51.25#ibcon#enter sib2, iclass 5, count 0 2006.285.19:54:51.25#ibcon#flushed, iclass 5, count 0 2006.285.19:54:51.25#ibcon#about to write, iclass 5, count 0 2006.285.19:54:51.25#ibcon#wrote, iclass 5, count 0 2006.285.19:54:51.25#ibcon#about to read 3, iclass 5, count 0 2006.285.19:54:51.30#ibcon#read 3, iclass 5, count 0 2006.285.19:54:51.30#ibcon#about to read 4, iclass 5, count 0 2006.285.19:54:51.30#ibcon#read 4, iclass 5, count 0 2006.285.19:54:51.30#ibcon#about to read 5, iclass 5, count 0 2006.285.19:54:51.30#ibcon#read 5, iclass 5, count 0 2006.285.19:54:51.30#ibcon#about to read 6, iclass 5, count 0 2006.285.19:54:51.30#ibcon#read 6, iclass 5, count 0 2006.285.19:54:51.30#ibcon#end of sib2, iclass 5, count 0 2006.285.19:54:51.30#ibcon#*after write, iclass 5, count 0 2006.285.19:54:51.30#ibcon#*before return 0, iclass 5, count 0 2006.285.19:54:51.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:54:51.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:54:51.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.19:54:51.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.19:54:51.30$vck44/va=1,7 2006.285.19:54:51.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.19:54:51.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.19:54:51.30#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:51.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:54:51.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:54:51.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:54:51.30#ibcon#enter wrdev, iclass 7, count 2 2006.285.19:54:51.30#ibcon#first serial, iclass 7, count 2 2006.285.19:54:51.30#ibcon#enter sib2, iclass 7, count 2 2006.285.19:54:51.30#ibcon#flushed, iclass 7, count 2 2006.285.19:54:51.30#ibcon#about to write, iclass 7, count 2 2006.285.19:54:51.30#ibcon#wrote, iclass 7, count 2 2006.285.19:54:51.30#ibcon#about to read 3, iclass 7, count 2 2006.285.19:54:51.32#ibcon#read 3, iclass 7, count 2 2006.285.19:54:51.32#ibcon#about to read 4, iclass 7, count 2 2006.285.19:54:51.32#ibcon#read 4, iclass 7, count 2 2006.285.19:54:51.32#ibcon#about to read 5, iclass 7, count 2 2006.285.19:54:51.32#ibcon#read 5, iclass 7, count 2 2006.285.19:54:51.32#ibcon#about to read 6, iclass 7, count 2 2006.285.19:54:51.32#ibcon#read 6, iclass 7, count 2 2006.285.19:54:51.32#ibcon#end of sib2, iclass 7, count 2 2006.285.19:54:51.32#ibcon#*mode == 0, iclass 7, count 2 2006.285.19:54:51.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.19:54:51.32#ibcon#[25=AT01-07\r\n] 2006.285.19:54:51.32#ibcon#*before write, iclass 7, count 2 2006.285.19:54:51.32#ibcon#enter sib2, iclass 7, count 2 2006.285.19:54:51.32#ibcon#flushed, iclass 7, count 2 2006.285.19:54:51.32#ibcon#about to write, iclass 7, count 2 2006.285.19:54:51.32#ibcon#wrote, iclass 7, count 2 2006.285.19:54:51.32#ibcon#about to read 3, iclass 7, count 2 2006.285.19:54:51.35#ibcon#read 3, iclass 7, count 2 2006.285.19:54:51.35#ibcon#about to read 4, iclass 7, count 2 2006.285.19:54:51.35#ibcon#read 4, iclass 7, count 2 2006.285.19:54:51.35#ibcon#about to read 5, iclass 7, count 2 2006.285.19:54:51.35#ibcon#read 5, iclass 7, count 2 2006.285.19:54:51.35#ibcon#about to read 6, iclass 7, count 2 2006.285.19:54:51.35#ibcon#read 6, iclass 7, count 2 2006.285.19:54:51.35#ibcon#end of sib2, iclass 7, count 2 2006.285.19:54:51.35#ibcon#*after write, iclass 7, count 2 2006.285.19:54:51.35#ibcon#*before return 0, iclass 7, count 2 2006.285.19:54:51.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:54:51.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:54:51.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.19:54:51.35#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:51.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:54:51.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:54:51.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:54:51.47#ibcon#enter wrdev, iclass 7, count 0 2006.285.19:54:51.47#ibcon#first serial, iclass 7, count 0 2006.285.19:54:51.47#ibcon#enter sib2, iclass 7, count 0 2006.285.19:54:51.47#ibcon#flushed, iclass 7, count 0 2006.285.19:54:51.47#ibcon#about to write, iclass 7, count 0 2006.285.19:54:51.47#ibcon#wrote, iclass 7, count 0 2006.285.19:54:51.47#ibcon#about to read 3, iclass 7, count 0 2006.285.19:54:51.49#ibcon#read 3, iclass 7, count 0 2006.285.19:54:51.49#ibcon#about to read 4, iclass 7, count 0 2006.285.19:54:51.49#ibcon#read 4, iclass 7, count 0 2006.285.19:54:51.49#ibcon#about to read 5, iclass 7, count 0 2006.285.19:54:51.49#ibcon#read 5, iclass 7, count 0 2006.285.19:54:51.49#ibcon#about to read 6, iclass 7, count 0 2006.285.19:54:51.49#ibcon#read 6, iclass 7, count 0 2006.285.19:54:51.49#ibcon#end of sib2, iclass 7, count 0 2006.285.19:54:51.49#ibcon#*mode == 0, iclass 7, count 0 2006.285.19:54:51.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.19:54:51.49#ibcon#[25=USB\r\n] 2006.285.19:54:51.49#ibcon#*before write, iclass 7, count 0 2006.285.19:54:51.49#ibcon#enter sib2, iclass 7, count 0 2006.285.19:54:51.49#ibcon#flushed, iclass 7, count 0 2006.285.19:54:51.49#ibcon#about to write, iclass 7, count 0 2006.285.19:54:51.49#ibcon#wrote, iclass 7, count 0 2006.285.19:54:51.49#ibcon#about to read 3, iclass 7, count 0 2006.285.19:54:51.52#ibcon#read 3, iclass 7, count 0 2006.285.19:54:51.52#ibcon#about to read 4, iclass 7, count 0 2006.285.19:54:51.52#ibcon#read 4, iclass 7, count 0 2006.285.19:54:51.52#ibcon#about to read 5, iclass 7, count 0 2006.285.19:54:51.52#ibcon#read 5, iclass 7, count 0 2006.285.19:54:51.52#ibcon#about to read 6, iclass 7, count 0 2006.285.19:54:51.52#ibcon#read 6, iclass 7, count 0 2006.285.19:54:51.52#ibcon#end of sib2, iclass 7, count 0 2006.285.19:54:51.52#ibcon#*after write, iclass 7, count 0 2006.285.19:54:51.52#ibcon#*before return 0, iclass 7, count 0 2006.285.19:54:51.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:54:51.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:54:51.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.19:54:51.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.19:54:51.52$vck44/valo=2,534.99 2006.285.19:54:51.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.19:54:51.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.19:54:51.52#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:51.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:54:51.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:54:51.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:54:51.52#ibcon#enter wrdev, iclass 11, count 0 2006.285.19:54:51.52#ibcon#first serial, iclass 11, count 0 2006.285.19:54:51.52#ibcon#enter sib2, iclass 11, count 0 2006.285.19:54:51.52#ibcon#flushed, iclass 11, count 0 2006.285.19:54:51.52#ibcon#about to write, iclass 11, count 0 2006.285.19:54:51.52#ibcon#wrote, iclass 11, count 0 2006.285.19:54:51.52#ibcon#about to read 3, iclass 11, count 0 2006.285.19:54:51.54#ibcon#read 3, iclass 11, count 0 2006.285.19:54:51.54#ibcon#about to read 4, iclass 11, count 0 2006.285.19:54:51.54#ibcon#read 4, iclass 11, count 0 2006.285.19:54:51.54#ibcon#about to read 5, iclass 11, count 0 2006.285.19:54:51.54#ibcon#read 5, iclass 11, count 0 2006.285.19:54:51.54#ibcon#about to read 6, iclass 11, count 0 2006.285.19:54:51.54#ibcon#read 6, iclass 11, count 0 2006.285.19:54:51.54#ibcon#end of sib2, iclass 11, count 0 2006.285.19:54:51.54#ibcon#*mode == 0, iclass 11, count 0 2006.285.19:54:51.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.19:54:51.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.19:54:51.54#ibcon#*before write, iclass 11, count 0 2006.285.19:54:51.54#ibcon#enter sib2, iclass 11, count 0 2006.285.19:54:51.54#ibcon#flushed, iclass 11, count 0 2006.285.19:54:51.54#ibcon#about to write, iclass 11, count 0 2006.285.19:54:51.54#ibcon#wrote, iclass 11, count 0 2006.285.19:54:51.54#ibcon#about to read 3, iclass 11, count 0 2006.285.19:54:51.58#ibcon#read 3, iclass 11, count 0 2006.285.19:54:51.58#ibcon#about to read 4, iclass 11, count 0 2006.285.19:54:51.58#ibcon#read 4, iclass 11, count 0 2006.285.19:54:51.58#ibcon#about to read 5, iclass 11, count 0 2006.285.19:54:51.58#ibcon#read 5, iclass 11, count 0 2006.285.19:54:51.58#ibcon#about to read 6, iclass 11, count 0 2006.285.19:54:51.58#ibcon#read 6, iclass 11, count 0 2006.285.19:54:51.58#ibcon#end of sib2, iclass 11, count 0 2006.285.19:54:51.58#ibcon#*after write, iclass 11, count 0 2006.285.19:54:51.58#ibcon#*before return 0, iclass 11, count 0 2006.285.19:54:51.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:54:51.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:54:51.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.19:54:51.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.19:54:51.58$vck44/va=2,6 2006.285.19:54:51.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.19:54:51.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.19:54:51.58#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:51.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:54:51.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:54:51.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:54:51.64#ibcon#enter wrdev, iclass 13, count 2 2006.285.19:54:51.64#ibcon#first serial, iclass 13, count 2 2006.285.19:54:51.64#ibcon#enter sib2, iclass 13, count 2 2006.285.19:54:51.64#ibcon#flushed, iclass 13, count 2 2006.285.19:54:51.64#ibcon#about to write, iclass 13, count 2 2006.285.19:54:51.64#ibcon#wrote, iclass 13, count 2 2006.285.19:54:51.64#ibcon#about to read 3, iclass 13, count 2 2006.285.19:54:51.66#ibcon#read 3, iclass 13, count 2 2006.285.19:54:51.66#ibcon#about to read 4, iclass 13, count 2 2006.285.19:54:51.66#ibcon#read 4, iclass 13, count 2 2006.285.19:54:51.66#ibcon#about to read 5, iclass 13, count 2 2006.285.19:54:51.66#ibcon#read 5, iclass 13, count 2 2006.285.19:54:51.66#ibcon#about to read 6, iclass 13, count 2 2006.285.19:54:51.66#ibcon#read 6, iclass 13, count 2 2006.285.19:54:51.66#ibcon#end of sib2, iclass 13, count 2 2006.285.19:54:51.66#ibcon#*mode == 0, iclass 13, count 2 2006.285.19:54:51.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.19:54:51.66#ibcon#[25=AT02-06\r\n] 2006.285.19:54:51.66#ibcon#*before write, iclass 13, count 2 2006.285.19:54:51.66#ibcon#enter sib2, iclass 13, count 2 2006.285.19:54:51.66#ibcon#flushed, iclass 13, count 2 2006.285.19:54:51.66#ibcon#about to write, iclass 13, count 2 2006.285.19:54:51.66#ibcon#wrote, iclass 13, count 2 2006.285.19:54:51.66#ibcon#about to read 3, iclass 13, count 2 2006.285.19:54:51.69#ibcon#read 3, iclass 13, count 2 2006.285.19:54:51.69#ibcon#about to read 4, iclass 13, count 2 2006.285.19:54:51.69#ibcon#read 4, iclass 13, count 2 2006.285.19:54:51.69#ibcon#about to read 5, iclass 13, count 2 2006.285.19:54:51.69#ibcon#read 5, iclass 13, count 2 2006.285.19:54:51.69#ibcon#about to read 6, iclass 13, count 2 2006.285.19:54:51.69#ibcon#read 6, iclass 13, count 2 2006.285.19:54:51.69#ibcon#end of sib2, iclass 13, count 2 2006.285.19:54:51.69#ibcon#*after write, iclass 13, count 2 2006.285.19:54:51.69#ibcon#*before return 0, iclass 13, count 2 2006.285.19:54:51.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:54:51.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:54:51.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.19:54:51.69#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:51.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:54:51.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:54:51.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:54:51.81#ibcon#enter wrdev, iclass 13, count 0 2006.285.19:54:51.81#ibcon#first serial, iclass 13, count 0 2006.285.19:54:51.81#ibcon#enter sib2, iclass 13, count 0 2006.285.19:54:51.81#ibcon#flushed, iclass 13, count 0 2006.285.19:54:51.81#ibcon#about to write, iclass 13, count 0 2006.285.19:54:51.81#ibcon#wrote, iclass 13, count 0 2006.285.19:54:51.81#ibcon#about to read 3, iclass 13, count 0 2006.285.19:54:51.83#ibcon#read 3, iclass 13, count 0 2006.285.19:54:51.83#ibcon#about to read 4, iclass 13, count 0 2006.285.19:54:51.83#ibcon#read 4, iclass 13, count 0 2006.285.19:54:51.83#ibcon#about to read 5, iclass 13, count 0 2006.285.19:54:51.83#ibcon#read 5, iclass 13, count 0 2006.285.19:54:51.83#ibcon#about to read 6, iclass 13, count 0 2006.285.19:54:51.83#ibcon#read 6, iclass 13, count 0 2006.285.19:54:51.83#ibcon#end of sib2, iclass 13, count 0 2006.285.19:54:51.83#ibcon#*mode == 0, iclass 13, count 0 2006.285.19:54:51.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.19:54:51.83#ibcon#[25=USB\r\n] 2006.285.19:54:51.83#ibcon#*before write, iclass 13, count 0 2006.285.19:54:51.83#ibcon#enter sib2, iclass 13, count 0 2006.285.19:54:51.83#ibcon#flushed, iclass 13, count 0 2006.285.19:54:51.83#ibcon#about to write, iclass 13, count 0 2006.285.19:54:51.83#ibcon#wrote, iclass 13, count 0 2006.285.19:54:51.83#ibcon#about to read 3, iclass 13, count 0 2006.285.19:54:51.86#ibcon#read 3, iclass 13, count 0 2006.285.19:54:51.86#ibcon#about to read 4, iclass 13, count 0 2006.285.19:54:51.86#ibcon#read 4, iclass 13, count 0 2006.285.19:54:51.86#ibcon#about to read 5, iclass 13, count 0 2006.285.19:54:51.86#ibcon#read 5, iclass 13, count 0 2006.285.19:54:51.86#ibcon#about to read 6, iclass 13, count 0 2006.285.19:54:51.86#ibcon#read 6, iclass 13, count 0 2006.285.19:54:51.86#ibcon#end of sib2, iclass 13, count 0 2006.285.19:54:51.86#ibcon#*after write, iclass 13, count 0 2006.285.19:54:51.86#ibcon#*before return 0, iclass 13, count 0 2006.285.19:54:51.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:54:51.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:54:51.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.19:54:51.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.19:54:51.86$vck44/valo=3,564.99 2006.285.19:54:51.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.19:54:51.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.19:54:51.86#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:51.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:54:51.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:54:51.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:54:51.86#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:54:51.86#ibcon#first serial, iclass 15, count 0 2006.285.19:54:51.86#ibcon#enter sib2, iclass 15, count 0 2006.285.19:54:51.86#ibcon#flushed, iclass 15, count 0 2006.285.19:54:51.86#ibcon#about to write, iclass 15, count 0 2006.285.19:54:51.86#ibcon#wrote, iclass 15, count 0 2006.285.19:54:51.86#ibcon#about to read 3, iclass 15, count 0 2006.285.19:54:51.88#ibcon#read 3, iclass 15, count 0 2006.285.19:54:51.88#ibcon#about to read 4, iclass 15, count 0 2006.285.19:54:51.88#ibcon#read 4, iclass 15, count 0 2006.285.19:54:51.88#ibcon#about to read 5, iclass 15, count 0 2006.285.19:54:51.88#ibcon#read 5, iclass 15, count 0 2006.285.19:54:51.88#ibcon#about to read 6, iclass 15, count 0 2006.285.19:54:51.88#ibcon#read 6, iclass 15, count 0 2006.285.19:54:51.88#ibcon#end of sib2, iclass 15, count 0 2006.285.19:54:51.88#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:54:51.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:54:51.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.19:54:51.88#ibcon#*before write, iclass 15, count 0 2006.285.19:54:51.88#ibcon#enter sib2, iclass 15, count 0 2006.285.19:54:51.88#ibcon#flushed, iclass 15, count 0 2006.285.19:54:51.88#ibcon#about to write, iclass 15, count 0 2006.285.19:54:51.88#ibcon#wrote, iclass 15, count 0 2006.285.19:54:51.88#ibcon#about to read 3, iclass 15, count 0 2006.285.19:54:51.92#ibcon#read 3, iclass 15, count 0 2006.285.19:54:51.92#ibcon#about to read 4, iclass 15, count 0 2006.285.19:54:51.92#ibcon#read 4, iclass 15, count 0 2006.285.19:54:51.92#ibcon#about to read 5, iclass 15, count 0 2006.285.19:54:51.92#ibcon#read 5, iclass 15, count 0 2006.285.19:54:51.92#ibcon#about to read 6, iclass 15, count 0 2006.285.19:54:51.92#ibcon#read 6, iclass 15, count 0 2006.285.19:54:51.92#ibcon#end of sib2, iclass 15, count 0 2006.285.19:54:51.92#ibcon#*after write, iclass 15, count 0 2006.285.19:54:51.92#ibcon#*before return 0, iclass 15, count 0 2006.285.19:54:51.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:54:51.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:54:51.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:54:51.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:54:51.92$vck44/va=3,7 2006.285.19:54:51.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.19:54:51.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.19:54:51.92#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:51.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:54:51.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:54:51.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:54:51.98#ibcon#enter wrdev, iclass 17, count 2 2006.285.19:54:51.98#ibcon#first serial, iclass 17, count 2 2006.285.19:54:51.98#ibcon#enter sib2, iclass 17, count 2 2006.285.19:54:51.98#ibcon#flushed, iclass 17, count 2 2006.285.19:54:51.98#ibcon#about to write, iclass 17, count 2 2006.285.19:54:51.98#ibcon#wrote, iclass 17, count 2 2006.285.19:54:51.98#ibcon#about to read 3, iclass 17, count 2 2006.285.19:54:52.00#ibcon#read 3, iclass 17, count 2 2006.285.19:54:52.00#ibcon#about to read 4, iclass 17, count 2 2006.285.19:54:52.00#ibcon#read 4, iclass 17, count 2 2006.285.19:54:52.00#ibcon#about to read 5, iclass 17, count 2 2006.285.19:54:52.00#ibcon#read 5, iclass 17, count 2 2006.285.19:54:52.00#ibcon#about to read 6, iclass 17, count 2 2006.285.19:54:52.00#ibcon#read 6, iclass 17, count 2 2006.285.19:54:52.00#ibcon#end of sib2, iclass 17, count 2 2006.285.19:54:52.00#ibcon#*mode == 0, iclass 17, count 2 2006.285.19:54:52.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.19:54:52.00#ibcon#[25=AT03-07\r\n] 2006.285.19:54:52.00#ibcon#*before write, iclass 17, count 2 2006.285.19:54:52.00#ibcon#enter sib2, iclass 17, count 2 2006.285.19:54:52.00#ibcon#flushed, iclass 17, count 2 2006.285.19:54:52.00#ibcon#about to write, iclass 17, count 2 2006.285.19:54:52.00#ibcon#wrote, iclass 17, count 2 2006.285.19:54:52.00#ibcon#about to read 3, iclass 17, count 2 2006.285.19:54:52.03#ibcon#read 3, iclass 17, count 2 2006.285.19:54:52.03#ibcon#about to read 4, iclass 17, count 2 2006.285.19:54:52.03#ibcon#read 4, iclass 17, count 2 2006.285.19:54:52.03#ibcon#about to read 5, iclass 17, count 2 2006.285.19:54:52.03#ibcon#read 5, iclass 17, count 2 2006.285.19:54:52.03#ibcon#about to read 6, iclass 17, count 2 2006.285.19:54:52.03#ibcon#read 6, iclass 17, count 2 2006.285.19:54:52.03#ibcon#end of sib2, iclass 17, count 2 2006.285.19:54:52.03#ibcon#*after write, iclass 17, count 2 2006.285.19:54:52.03#ibcon#*before return 0, iclass 17, count 2 2006.285.19:54:52.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:54:52.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:54:52.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.19:54:52.03#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:52.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:54:52.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:54:52.40#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:54:52.40#ibcon#enter wrdev, iclass 17, count 0 2006.285.19:54:52.40#ibcon#first serial, iclass 17, count 0 2006.285.19:54:52.40#ibcon#enter sib2, iclass 17, count 0 2006.285.19:54:52.40#ibcon#flushed, iclass 17, count 0 2006.285.19:54:52.40#ibcon#about to write, iclass 17, count 0 2006.285.19:54:52.40#ibcon#wrote, iclass 17, count 0 2006.285.19:54:52.40#ibcon#about to read 3, iclass 17, count 0 2006.285.19:54:52.42#ibcon#read 3, iclass 17, count 0 2006.285.19:54:52.42#ibcon#about to read 4, iclass 17, count 0 2006.285.19:54:52.42#ibcon#read 4, iclass 17, count 0 2006.285.19:54:52.42#ibcon#about to read 5, iclass 17, count 0 2006.285.19:54:52.42#ibcon#read 5, iclass 17, count 0 2006.285.19:54:52.42#ibcon#about to read 6, iclass 17, count 0 2006.285.19:54:52.42#ibcon#read 6, iclass 17, count 0 2006.285.19:54:52.42#ibcon#end of sib2, iclass 17, count 0 2006.285.19:54:52.42#ibcon#*mode == 0, iclass 17, count 0 2006.285.19:54:52.42#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.19:54:52.42#ibcon#[25=USB\r\n] 2006.285.19:54:52.42#ibcon#*before write, iclass 17, count 0 2006.285.19:54:52.42#ibcon#enter sib2, iclass 17, count 0 2006.285.19:54:52.42#ibcon#flushed, iclass 17, count 0 2006.285.19:54:52.42#ibcon#about to write, iclass 17, count 0 2006.285.19:54:52.42#ibcon#wrote, iclass 17, count 0 2006.285.19:54:52.42#ibcon#about to read 3, iclass 17, count 0 2006.285.19:54:52.45#ibcon#read 3, iclass 17, count 0 2006.285.19:54:52.45#ibcon#about to read 4, iclass 17, count 0 2006.285.19:54:52.45#ibcon#read 4, iclass 17, count 0 2006.285.19:54:52.45#ibcon#about to read 5, iclass 17, count 0 2006.285.19:54:52.45#ibcon#read 5, iclass 17, count 0 2006.285.19:54:52.45#ibcon#about to read 6, iclass 17, count 0 2006.285.19:54:52.45#ibcon#read 6, iclass 17, count 0 2006.285.19:54:52.45#ibcon#end of sib2, iclass 17, count 0 2006.285.19:54:52.45#ibcon#*after write, iclass 17, count 0 2006.285.19:54:52.45#ibcon#*before return 0, iclass 17, count 0 2006.285.19:54:52.45#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:54:52.45#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:54:52.45#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.19:54:52.45#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.19:54:52.45$vck44/valo=4,624.99 2006.285.19:54:52.45#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.19:54:52.45#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.19:54:52.45#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:52.45#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:54:52.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:54:52.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:54:52.45#ibcon#enter wrdev, iclass 19, count 0 2006.285.19:54:52.45#ibcon#first serial, iclass 19, count 0 2006.285.19:54:52.45#ibcon#enter sib2, iclass 19, count 0 2006.285.19:54:52.45#ibcon#flushed, iclass 19, count 0 2006.285.19:54:52.45#ibcon#about to write, iclass 19, count 0 2006.285.19:54:52.45#ibcon#wrote, iclass 19, count 0 2006.285.19:54:52.45#ibcon#about to read 3, iclass 19, count 0 2006.285.19:54:52.47#ibcon#read 3, iclass 19, count 0 2006.285.19:54:52.47#ibcon#about to read 4, iclass 19, count 0 2006.285.19:54:52.47#ibcon#read 4, iclass 19, count 0 2006.285.19:54:52.47#ibcon#about to read 5, iclass 19, count 0 2006.285.19:54:52.47#ibcon#read 5, iclass 19, count 0 2006.285.19:54:52.47#ibcon#about to read 6, iclass 19, count 0 2006.285.19:54:52.47#ibcon#read 6, iclass 19, count 0 2006.285.19:54:52.47#ibcon#end of sib2, iclass 19, count 0 2006.285.19:54:52.47#ibcon#*mode == 0, iclass 19, count 0 2006.285.19:54:52.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.19:54:52.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.19:54:52.47#ibcon#*before write, iclass 19, count 0 2006.285.19:54:52.47#ibcon#enter sib2, iclass 19, count 0 2006.285.19:54:52.47#ibcon#flushed, iclass 19, count 0 2006.285.19:54:52.47#ibcon#about to write, iclass 19, count 0 2006.285.19:54:52.47#ibcon#wrote, iclass 19, count 0 2006.285.19:54:52.47#ibcon#about to read 3, iclass 19, count 0 2006.285.19:54:52.51#ibcon#read 3, iclass 19, count 0 2006.285.19:54:52.51#ibcon#about to read 4, iclass 19, count 0 2006.285.19:54:52.51#ibcon#read 4, iclass 19, count 0 2006.285.19:54:52.51#ibcon#about to read 5, iclass 19, count 0 2006.285.19:54:52.51#ibcon#read 5, iclass 19, count 0 2006.285.19:54:52.51#ibcon#about to read 6, iclass 19, count 0 2006.285.19:54:52.51#ibcon#read 6, iclass 19, count 0 2006.285.19:54:52.51#ibcon#end of sib2, iclass 19, count 0 2006.285.19:54:52.51#ibcon#*after write, iclass 19, count 0 2006.285.19:54:52.51#ibcon#*before return 0, iclass 19, count 0 2006.285.19:54:52.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:54:52.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:54:52.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.19:54:52.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.19:54:52.51$vck44/va=4,6 2006.285.19:54:52.51#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.19:54:52.51#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.19:54:52.51#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:52.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:54:52.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:54:52.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:54:52.57#ibcon#enter wrdev, iclass 21, count 2 2006.285.19:54:52.57#ibcon#first serial, iclass 21, count 2 2006.285.19:54:52.57#ibcon#enter sib2, iclass 21, count 2 2006.285.19:54:52.57#ibcon#flushed, iclass 21, count 2 2006.285.19:54:52.57#ibcon#about to write, iclass 21, count 2 2006.285.19:54:52.57#ibcon#wrote, iclass 21, count 2 2006.285.19:54:52.57#ibcon#about to read 3, iclass 21, count 2 2006.285.19:54:52.59#ibcon#read 3, iclass 21, count 2 2006.285.19:54:52.59#ibcon#about to read 4, iclass 21, count 2 2006.285.19:54:52.59#ibcon#read 4, iclass 21, count 2 2006.285.19:54:52.59#ibcon#about to read 5, iclass 21, count 2 2006.285.19:54:52.59#ibcon#read 5, iclass 21, count 2 2006.285.19:54:52.59#ibcon#about to read 6, iclass 21, count 2 2006.285.19:54:52.59#ibcon#read 6, iclass 21, count 2 2006.285.19:54:52.59#ibcon#end of sib2, iclass 21, count 2 2006.285.19:54:52.59#ibcon#*mode == 0, iclass 21, count 2 2006.285.19:54:52.59#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.19:54:52.59#ibcon#[25=AT04-06\r\n] 2006.285.19:54:52.59#ibcon#*before write, iclass 21, count 2 2006.285.19:54:52.59#ibcon#enter sib2, iclass 21, count 2 2006.285.19:54:52.59#ibcon#flushed, iclass 21, count 2 2006.285.19:54:52.59#ibcon#about to write, iclass 21, count 2 2006.285.19:54:52.59#ibcon#wrote, iclass 21, count 2 2006.285.19:54:52.59#ibcon#about to read 3, iclass 21, count 2 2006.285.19:54:52.62#ibcon#read 3, iclass 21, count 2 2006.285.19:54:52.62#ibcon#about to read 4, iclass 21, count 2 2006.285.19:54:52.62#ibcon#read 4, iclass 21, count 2 2006.285.19:54:52.62#ibcon#about to read 5, iclass 21, count 2 2006.285.19:54:52.62#ibcon#read 5, iclass 21, count 2 2006.285.19:54:52.62#ibcon#about to read 6, iclass 21, count 2 2006.285.19:54:52.62#ibcon#read 6, iclass 21, count 2 2006.285.19:54:52.62#ibcon#end of sib2, iclass 21, count 2 2006.285.19:54:52.62#ibcon#*after write, iclass 21, count 2 2006.285.19:54:52.62#ibcon#*before return 0, iclass 21, count 2 2006.285.19:54:52.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:54:52.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:54:52.62#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.19:54:52.62#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:52.62#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:54:52.74#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:54:52.74#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:54:52.74#ibcon#enter wrdev, iclass 21, count 0 2006.285.19:54:52.74#ibcon#first serial, iclass 21, count 0 2006.285.19:54:52.74#ibcon#enter sib2, iclass 21, count 0 2006.285.19:54:52.74#ibcon#flushed, iclass 21, count 0 2006.285.19:54:52.74#ibcon#about to write, iclass 21, count 0 2006.285.19:54:52.74#ibcon#wrote, iclass 21, count 0 2006.285.19:54:52.74#ibcon#about to read 3, iclass 21, count 0 2006.285.19:54:52.76#ibcon#read 3, iclass 21, count 0 2006.285.19:54:52.76#ibcon#about to read 4, iclass 21, count 0 2006.285.19:54:52.76#ibcon#read 4, iclass 21, count 0 2006.285.19:54:52.76#ibcon#about to read 5, iclass 21, count 0 2006.285.19:54:52.76#ibcon#read 5, iclass 21, count 0 2006.285.19:54:53.11#ibcon#about to read 6, iclass 21, count 0 2006.285.19:54:53.11#ibcon#read 6, iclass 21, count 0 2006.285.19:54:53.11#ibcon#end of sib2, iclass 21, count 0 2006.285.19:54:53.11#ibcon#*mode == 0, iclass 21, count 0 2006.285.19:54:53.11#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.19:54:53.11#ibcon#[25=USB\r\n] 2006.285.19:54:53.11#ibcon#*before write, iclass 21, count 0 2006.285.19:54:53.11#ibcon#enter sib2, iclass 21, count 0 2006.285.19:54:53.11#ibcon#flushed, iclass 21, count 0 2006.285.19:54:53.11#ibcon#about to write, iclass 21, count 0 2006.285.19:54:53.11#ibcon#wrote, iclass 21, count 0 2006.285.19:54:53.11#ibcon#about to read 3, iclass 21, count 0 2006.285.19:54:52.79#abcon#<5=/14 0.5 1.2 14.631001015.2\r\n> 2006.285.19:54:53.13#abcon#{5=INTERFACE CLEAR} 2006.285.19:54:53.14#ibcon#read 3, iclass 21, count 0 2006.285.19:54:53.14#ibcon#about to read 4, iclass 21, count 0 2006.285.19:54:53.14#ibcon#read 4, iclass 21, count 0 2006.285.19:54:53.14#ibcon#about to read 5, iclass 21, count 0 2006.285.19:54:53.14#ibcon#read 5, iclass 21, count 0 2006.285.19:54:53.14#ibcon#about to read 6, iclass 21, count 0 2006.285.19:54:53.14#ibcon#read 6, iclass 21, count 0 2006.285.19:54:53.14#ibcon#end of sib2, iclass 21, count 0 2006.285.19:54:53.14#ibcon#*after write, iclass 21, count 0 2006.285.19:54:53.14#ibcon#*before return 0, iclass 21, count 0 2006.285.19:54:53.14#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:54:53.14#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:54:53.14#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.19:54:53.14#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.19:54:53.14$vck44/valo=5,734.99 2006.285.19:54:53.14#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.19:54:53.14#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.19:54:53.14#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:53.14#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:54:53.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:54:53.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:54:53.14#ibcon#enter wrdev, iclass 26, count 0 2006.285.19:54:53.14#ibcon#first serial, iclass 26, count 0 2006.285.19:54:53.14#ibcon#enter sib2, iclass 26, count 0 2006.285.19:54:53.14#ibcon#flushed, iclass 26, count 0 2006.285.19:54:53.14#ibcon#about to write, iclass 26, count 0 2006.285.19:54:53.14#ibcon#wrote, iclass 26, count 0 2006.285.19:54:53.14#ibcon#about to read 3, iclass 26, count 0 2006.285.19:54:53.16#ibcon#read 3, iclass 26, count 0 2006.285.19:54:53.16#ibcon#about to read 4, iclass 26, count 0 2006.285.19:54:53.16#ibcon#read 4, iclass 26, count 0 2006.285.19:54:53.16#ibcon#about to read 5, iclass 26, count 0 2006.285.19:54:53.16#ibcon#read 5, iclass 26, count 0 2006.285.19:54:53.16#ibcon#about to read 6, iclass 26, count 0 2006.285.19:54:53.16#ibcon#read 6, iclass 26, count 0 2006.285.19:54:53.16#ibcon#end of sib2, iclass 26, count 0 2006.285.19:54:53.16#ibcon#*mode == 0, iclass 26, count 0 2006.285.19:54:53.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.19:54:53.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.19:54:53.16#ibcon#*before write, iclass 26, count 0 2006.285.19:54:53.16#ibcon#enter sib2, iclass 26, count 0 2006.285.19:54:53.16#ibcon#flushed, iclass 26, count 0 2006.285.19:54:53.16#ibcon#about to write, iclass 26, count 0 2006.285.19:54:53.16#ibcon#wrote, iclass 26, count 0 2006.285.19:54:53.16#ibcon#about to read 3, iclass 26, count 0 2006.285.19:54:53.19#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:54:53.20#ibcon#read 3, iclass 26, count 0 2006.285.19:54:53.20#ibcon#about to read 4, iclass 26, count 0 2006.285.19:54:53.20#ibcon#read 4, iclass 26, count 0 2006.285.19:54:53.20#ibcon#about to read 5, iclass 26, count 0 2006.285.19:54:53.20#ibcon#read 5, iclass 26, count 0 2006.285.19:54:53.20#ibcon#about to read 6, iclass 26, count 0 2006.285.19:54:53.20#ibcon#read 6, iclass 26, count 0 2006.285.19:54:53.20#ibcon#end of sib2, iclass 26, count 0 2006.285.19:54:53.20#ibcon#*after write, iclass 26, count 0 2006.285.19:54:53.20#ibcon#*before return 0, iclass 26, count 0 2006.285.19:54:53.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:54:53.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:54:53.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.19:54:53.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.19:54:53.20$vck44/va=5,3 2006.285.19:54:53.20#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.19:54:53.20#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.19:54:53.20#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:53.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:54:53.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:54:53.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:54:53.26#ibcon#enter wrdev, iclass 29, count 2 2006.285.19:54:53.26#ibcon#first serial, iclass 29, count 2 2006.285.19:54:53.26#ibcon#enter sib2, iclass 29, count 2 2006.285.19:54:53.26#ibcon#flushed, iclass 29, count 2 2006.285.19:54:53.26#ibcon#about to write, iclass 29, count 2 2006.285.19:54:53.26#ibcon#wrote, iclass 29, count 2 2006.285.19:54:53.26#ibcon#about to read 3, iclass 29, count 2 2006.285.19:54:53.28#ibcon#read 3, iclass 29, count 2 2006.285.19:54:53.28#ibcon#about to read 4, iclass 29, count 2 2006.285.19:54:53.28#ibcon#read 4, iclass 29, count 2 2006.285.19:54:53.28#ibcon#about to read 5, iclass 29, count 2 2006.285.19:54:53.28#ibcon#read 5, iclass 29, count 2 2006.285.19:54:53.28#ibcon#about to read 6, iclass 29, count 2 2006.285.19:54:53.28#ibcon#read 6, iclass 29, count 2 2006.285.19:54:53.28#ibcon#end of sib2, iclass 29, count 2 2006.285.19:54:53.28#ibcon#*mode == 0, iclass 29, count 2 2006.285.19:54:53.28#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.19:54:53.28#ibcon#[25=AT05-03\r\n] 2006.285.19:54:53.28#ibcon#*before write, iclass 29, count 2 2006.285.19:54:53.28#ibcon#enter sib2, iclass 29, count 2 2006.285.19:54:53.28#ibcon#flushed, iclass 29, count 2 2006.285.19:54:53.28#ibcon#about to write, iclass 29, count 2 2006.285.19:54:53.28#ibcon#wrote, iclass 29, count 2 2006.285.19:54:53.28#ibcon#about to read 3, iclass 29, count 2 2006.285.19:54:53.31#ibcon#read 3, iclass 29, count 2 2006.285.19:54:53.31#ibcon#about to read 4, iclass 29, count 2 2006.285.19:54:53.31#ibcon#read 4, iclass 29, count 2 2006.285.19:54:53.31#ibcon#about to read 5, iclass 29, count 2 2006.285.19:54:53.31#ibcon#read 5, iclass 29, count 2 2006.285.19:54:53.31#ibcon#about to read 6, iclass 29, count 2 2006.285.19:54:53.31#ibcon#read 6, iclass 29, count 2 2006.285.19:54:53.31#ibcon#end of sib2, iclass 29, count 2 2006.285.19:54:53.31#ibcon#*after write, iclass 29, count 2 2006.285.19:54:53.31#ibcon#*before return 0, iclass 29, count 2 2006.285.19:54:53.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:54:53.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:54:53.31#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.19:54:53.31#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:53.31#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:54:53.43#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:54:53.43#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:54:53.43#ibcon#enter wrdev, iclass 29, count 0 2006.285.19:54:53.43#ibcon#first serial, iclass 29, count 0 2006.285.19:54:53.43#ibcon#enter sib2, iclass 29, count 0 2006.285.19:54:53.43#ibcon#flushed, iclass 29, count 0 2006.285.19:54:53.43#ibcon#about to write, iclass 29, count 0 2006.285.19:54:53.43#ibcon#wrote, iclass 29, count 0 2006.285.19:54:53.43#ibcon#about to read 3, iclass 29, count 0 2006.285.19:54:53.45#ibcon#read 3, iclass 29, count 0 2006.285.19:54:53.45#ibcon#about to read 4, iclass 29, count 0 2006.285.19:54:53.45#ibcon#read 4, iclass 29, count 0 2006.285.19:54:53.45#ibcon#about to read 5, iclass 29, count 0 2006.285.19:54:53.45#ibcon#read 5, iclass 29, count 0 2006.285.19:54:53.45#ibcon#about to read 6, iclass 29, count 0 2006.285.19:54:53.45#ibcon#read 6, iclass 29, count 0 2006.285.19:54:53.45#ibcon#end of sib2, iclass 29, count 0 2006.285.19:54:53.45#ibcon#*mode == 0, iclass 29, count 0 2006.285.19:54:53.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.19:54:53.45#ibcon#[25=USB\r\n] 2006.285.19:54:53.45#ibcon#*before write, iclass 29, count 0 2006.285.19:54:53.45#ibcon#enter sib2, iclass 29, count 0 2006.285.19:54:53.45#ibcon#flushed, iclass 29, count 0 2006.285.19:54:53.45#ibcon#about to write, iclass 29, count 0 2006.285.19:54:53.45#ibcon#wrote, iclass 29, count 0 2006.285.19:54:53.45#ibcon#about to read 3, iclass 29, count 0 2006.285.19:54:53.48#ibcon#read 3, iclass 29, count 0 2006.285.19:54:53.48#ibcon#about to read 4, iclass 29, count 0 2006.285.19:54:53.48#ibcon#read 4, iclass 29, count 0 2006.285.19:54:53.48#ibcon#about to read 5, iclass 29, count 0 2006.285.19:54:53.48#ibcon#read 5, iclass 29, count 0 2006.285.19:54:53.48#ibcon#about to read 6, iclass 29, count 0 2006.285.19:54:53.48#ibcon#read 6, iclass 29, count 0 2006.285.19:54:53.48#ibcon#end of sib2, iclass 29, count 0 2006.285.19:54:53.48#ibcon#*after write, iclass 29, count 0 2006.285.19:54:53.48#ibcon#*before return 0, iclass 29, count 0 2006.285.19:54:53.48#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:54:53.48#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:54:53.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.19:54:53.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.19:54:53.48$vck44/valo=6,814.99 2006.285.19:54:53.48#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.19:54:53.48#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.19:54:53.48#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:53.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:54:53.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:54:53.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:54:53.48#ibcon#enter wrdev, iclass 31, count 0 2006.285.19:54:53.48#ibcon#first serial, iclass 31, count 0 2006.285.19:54:53.48#ibcon#enter sib2, iclass 31, count 0 2006.285.19:54:53.48#ibcon#flushed, iclass 31, count 0 2006.285.19:54:53.48#ibcon#about to write, iclass 31, count 0 2006.285.19:54:53.48#ibcon#wrote, iclass 31, count 0 2006.285.19:54:53.48#ibcon#about to read 3, iclass 31, count 0 2006.285.19:54:53.50#ibcon#read 3, iclass 31, count 0 2006.285.19:54:53.54#ibcon#about to read 4, iclass 31, count 0 2006.285.19:54:53.54#ibcon#read 4, iclass 31, count 0 2006.285.19:54:53.54#ibcon#about to read 5, iclass 31, count 0 2006.285.19:54:53.54#ibcon#read 5, iclass 31, count 0 2006.285.19:54:53.54#ibcon#about to read 6, iclass 31, count 0 2006.285.19:54:53.54#ibcon#read 6, iclass 31, count 0 2006.285.19:54:53.54#ibcon#end of sib2, iclass 31, count 0 2006.285.19:54:53.54#ibcon#*mode == 0, iclass 31, count 0 2006.285.19:54:53.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.19:54:53.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.19:54:53.54#ibcon#*before write, iclass 31, count 0 2006.285.19:54:53.54#ibcon#enter sib2, iclass 31, count 0 2006.285.19:54:53.54#ibcon#flushed, iclass 31, count 0 2006.285.19:54:53.54#ibcon#about to write, iclass 31, count 0 2006.285.19:54:53.54#ibcon#wrote, iclass 31, count 0 2006.285.19:54:53.54#ibcon#about to read 3, iclass 31, count 0 2006.285.19:54:53.58#ibcon#read 3, iclass 31, count 0 2006.285.19:54:53.58#ibcon#about to read 4, iclass 31, count 0 2006.285.19:54:53.58#ibcon#read 4, iclass 31, count 0 2006.285.19:54:53.58#ibcon#about to read 5, iclass 31, count 0 2006.285.19:54:53.58#ibcon#read 5, iclass 31, count 0 2006.285.19:54:53.58#ibcon#about to read 6, iclass 31, count 0 2006.285.19:54:53.58#ibcon#read 6, iclass 31, count 0 2006.285.19:54:53.58#ibcon#end of sib2, iclass 31, count 0 2006.285.19:54:53.58#ibcon#*after write, iclass 31, count 0 2006.285.19:54:53.58#ibcon#*before return 0, iclass 31, count 0 2006.285.19:54:53.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:54:53.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:54:53.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.19:54:53.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.19:54:53.58$vck44/va=6,4 2006.285.19:54:53.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.19:54:53.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.19:54:53.58#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:53.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:54:53.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:54:53.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:54:53.60#ibcon#enter wrdev, iclass 33, count 2 2006.285.19:54:53.60#ibcon#first serial, iclass 33, count 2 2006.285.19:54:53.60#ibcon#enter sib2, iclass 33, count 2 2006.285.19:54:53.60#ibcon#flushed, iclass 33, count 2 2006.285.19:54:53.60#ibcon#about to write, iclass 33, count 2 2006.285.19:54:53.60#ibcon#wrote, iclass 33, count 2 2006.285.19:54:53.60#ibcon#about to read 3, iclass 33, count 2 2006.285.19:54:53.62#ibcon#read 3, iclass 33, count 2 2006.285.19:54:53.62#ibcon#about to read 4, iclass 33, count 2 2006.285.19:54:53.62#ibcon#read 4, iclass 33, count 2 2006.285.19:54:53.62#ibcon#about to read 5, iclass 33, count 2 2006.285.19:54:53.62#ibcon#read 5, iclass 33, count 2 2006.285.19:54:53.62#ibcon#about to read 6, iclass 33, count 2 2006.285.19:54:53.62#ibcon#read 6, iclass 33, count 2 2006.285.19:54:53.62#ibcon#end of sib2, iclass 33, count 2 2006.285.19:54:53.62#ibcon#*mode == 0, iclass 33, count 2 2006.285.19:54:53.62#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.19:54:53.62#ibcon#[25=AT06-04\r\n] 2006.285.19:54:53.62#ibcon#*before write, iclass 33, count 2 2006.285.19:54:53.62#ibcon#enter sib2, iclass 33, count 2 2006.285.19:54:53.62#ibcon#flushed, iclass 33, count 2 2006.285.19:54:53.62#ibcon#about to write, iclass 33, count 2 2006.285.19:54:53.62#ibcon#wrote, iclass 33, count 2 2006.285.19:54:53.62#ibcon#about to read 3, iclass 33, count 2 2006.285.19:54:53.65#ibcon#read 3, iclass 33, count 2 2006.285.19:54:53.65#ibcon#about to read 4, iclass 33, count 2 2006.285.19:54:53.65#ibcon#read 4, iclass 33, count 2 2006.285.19:54:53.65#ibcon#about to read 5, iclass 33, count 2 2006.285.19:54:53.65#ibcon#read 5, iclass 33, count 2 2006.285.19:54:53.65#ibcon#about to read 6, iclass 33, count 2 2006.285.19:54:53.65#ibcon#read 6, iclass 33, count 2 2006.285.19:54:53.65#ibcon#end of sib2, iclass 33, count 2 2006.285.19:54:53.65#ibcon#*after write, iclass 33, count 2 2006.285.19:54:53.65#ibcon#*before return 0, iclass 33, count 2 2006.285.19:54:53.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:54:53.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:54:53.65#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.19:54:53.65#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:53.65#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:54:53.77#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:54:53.77#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:54:53.77#ibcon#enter wrdev, iclass 33, count 0 2006.285.19:54:53.77#ibcon#first serial, iclass 33, count 0 2006.285.19:54:53.77#ibcon#enter sib2, iclass 33, count 0 2006.285.19:54:53.77#ibcon#flushed, iclass 33, count 0 2006.285.19:54:53.77#ibcon#about to write, iclass 33, count 0 2006.285.19:54:53.77#ibcon#wrote, iclass 33, count 0 2006.285.19:54:53.77#ibcon#about to read 3, iclass 33, count 0 2006.285.19:54:53.79#ibcon#read 3, iclass 33, count 0 2006.285.19:54:53.79#ibcon#about to read 4, iclass 33, count 0 2006.285.19:54:53.79#ibcon#read 4, iclass 33, count 0 2006.285.19:54:53.79#ibcon#about to read 5, iclass 33, count 0 2006.285.19:54:53.79#ibcon#read 5, iclass 33, count 0 2006.285.19:54:53.79#ibcon#about to read 6, iclass 33, count 0 2006.285.19:54:53.79#ibcon#read 6, iclass 33, count 0 2006.285.19:54:53.79#ibcon#end of sib2, iclass 33, count 0 2006.285.19:54:53.79#ibcon#*mode == 0, iclass 33, count 0 2006.285.19:54:53.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.19:54:53.79#ibcon#[25=USB\r\n] 2006.285.19:54:53.79#ibcon#*before write, iclass 33, count 0 2006.285.19:54:53.79#ibcon#enter sib2, iclass 33, count 0 2006.285.19:54:53.79#ibcon#flushed, iclass 33, count 0 2006.285.19:54:53.79#ibcon#about to write, iclass 33, count 0 2006.285.19:54:53.79#ibcon#wrote, iclass 33, count 0 2006.285.19:54:53.79#ibcon#about to read 3, iclass 33, count 0 2006.285.19:54:53.82#ibcon#read 3, iclass 33, count 0 2006.285.19:54:53.82#ibcon#about to read 4, iclass 33, count 0 2006.285.19:54:53.82#ibcon#read 4, iclass 33, count 0 2006.285.19:54:53.82#ibcon#about to read 5, iclass 33, count 0 2006.285.19:54:53.82#ibcon#read 5, iclass 33, count 0 2006.285.19:54:53.82#ibcon#about to read 6, iclass 33, count 0 2006.285.19:54:53.82#ibcon#read 6, iclass 33, count 0 2006.285.19:54:53.82#ibcon#end of sib2, iclass 33, count 0 2006.285.19:54:53.82#ibcon#*after write, iclass 33, count 0 2006.285.19:54:53.82#ibcon#*before return 0, iclass 33, count 0 2006.285.19:54:53.82#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:54:53.82#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:54:53.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.19:54:53.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.19:54:53.82$vck44/valo=7,864.99 2006.285.19:54:53.82#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.19:54:53.82#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.19:54:53.82#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:53.82#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:54:53.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:54:53.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:54:53.82#ibcon#enter wrdev, iclass 35, count 0 2006.285.19:54:53.82#ibcon#first serial, iclass 35, count 0 2006.285.19:54:53.82#ibcon#enter sib2, iclass 35, count 0 2006.285.19:54:53.82#ibcon#flushed, iclass 35, count 0 2006.285.19:54:53.82#ibcon#about to write, iclass 35, count 0 2006.285.19:54:53.82#ibcon#wrote, iclass 35, count 0 2006.285.19:54:53.82#ibcon#about to read 3, iclass 35, count 0 2006.285.19:54:53.84#ibcon#read 3, iclass 35, count 0 2006.285.19:54:53.84#ibcon#about to read 4, iclass 35, count 0 2006.285.19:54:53.84#ibcon#read 4, iclass 35, count 0 2006.285.19:54:53.84#ibcon#about to read 5, iclass 35, count 0 2006.285.19:54:53.84#ibcon#read 5, iclass 35, count 0 2006.285.19:54:53.84#ibcon#about to read 6, iclass 35, count 0 2006.285.19:54:53.84#ibcon#read 6, iclass 35, count 0 2006.285.19:54:53.84#ibcon#end of sib2, iclass 35, count 0 2006.285.19:54:53.84#ibcon#*mode == 0, iclass 35, count 0 2006.285.19:54:53.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.19:54:53.84#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.19:54:53.84#ibcon#*before write, iclass 35, count 0 2006.285.19:54:53.84#ibcon#enter sib2, iclass 35, count 0 2006.285.19:54:53.84#ibcon#flushed, iclass 35, count 0 2006.285.19:54:53.84#ibcon#about to write, iclass 35, count 0 2006.285.19:54:53.84#ibcon#wrote, iclass 35, count 0 2006.285.19:54:53.84#ibcon#about to read 3, iclass 35, count 0 2006.285.19:54:53.88#ibcon#read 3, iclass 35, count 0 2006.285.19:54:53.88#ibcon#about to read 4, iclass 35, count 0 2006.285.19:54:53.88#ibcon#read 4, iclass 35, count 0 2006.285.19:54:53.88#ibcon#about to read 5, iclass 35, count 0 2006.285.19:54:53.88#ibcon#read 5, iclass 35, count 0 2006.285.19:54:53.88#ibcon#about to read 6, iclass 35, count 0 2006.285.19:54:53.88#ibcon#read 6, iclass 35, count 0 2006.285.19:54:53.88#ibcon#end of sib2, iclass 35, count 0 2006.285.19:54:53.88#ibcon#*after write, iclass 35, count 0 2006.285.19:54:53.88#ibcon#*before return 0, iclass 35, count 0 2006.285.19:54:53.88#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:54:53.88#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:54:53.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.19:54:53.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.19:54:53.88$vck44/va=7,4 2006.285.19:54:53.88#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.19:54:53.88#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.19:54:53.88#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:53.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:54:53.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:54:53.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:54:53.94#ibcon#enter wrdev, iclass 37, count 2 2006.285.19:54:53.94#ibcon#first serial, iclass 37, count 2 2006.285.19:54:53.94#ibcon#enter sib2, iclass 37, count 2 2006.285.19:54:53.94#ibcon#flushed, iclass 37, count 2 2006.285.19:54:53.94#ibcon#about to write, iclass 37, count 2 2006.285.19:54:53.94#ibcon#wrote, iclass 37, count 2 2006.285.19:54:53.94#ibcon#about to read 3, iclass 37, count 2 2006.285.19:54:53.96#ibcon#read 3, iclass 37, count 2 2006.285.19:54:53.96#ibcon#about to read 4, iclass 37, count 2 2006.285.19:54:53.96#ibcon#read 4, iclass 37, count 2 2006.285.19:54:53.96#ibcon#about to read 5, iclass 37, count 2 2006.285.19:54:53.96#ibcon#read 5, iclass 37, count 2 2006.285.19:54:53.96#ibcon#about to read 6, iclass 37, count 2 2006.285.19:54:53.96#ibcon#read 6, iclass 37, count 2 2006.285.19:54:53.96#ibcon#end of sib2, iclass 37, count 2 2006.285.19:54:53.96#ibcon#*mode == 0, iclass 37, count 2 2006.285.19:54:53.96#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.19:54:53.96#ibcon#[25=AT07-04\r\n] 2006.285.19:54:53.96#ibcon#*before write, iclass 37, count 2 2006.285.19:54:53.96#ibcon#enter sib2, iclass 37, count 2 2006.285.19:54:53.96#ibcon#flushed, iclass 37, count 2 2006.285.19:54:53.96#ibcon#about to write, iclass 37, count 2 2006.285.19:54:53.96#ibcon#wrote, iclass 37, count 2 2006.285.19:54:53.96#ibcon#about to read 3, iclass 37, count 2 2006.285.19:54:53.99#ibcon#read 3, iclass 37, count 2 2006.285.19:54:53.99#ibcon#about to read 4, iclass 37, count 2 2006.285.19:54:53.99#ibcon#read 4, iclass 37, count 2 2006.285.19:54:53.99#ibcon#about to read 5, iclass 37, count 2 2006.285.19:54:53.99#ibcon#read 5, iclass 37, count 2 2006.285.19:54:53.99#ibcon#about to read 6, iclass 37, count 2 2006.285.19:54:53.99#ibcon#read 6, iclass 37, count 2 2006.285.19:54:53.99#ibcon#end of sib2, iclass 37, count 2 2006.285.19:54:53.99#ibcon#*after write, iclass 37, count 2 2006.285.19:54:53.99#ibcon#*before return 0, iclass 37, count 2 2006.285.19:54:53.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:54:53.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:54:53.99#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.19:54:53.99#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:53.99#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:54:54.11#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:54:54.11#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:54:54.11#ibcon#enter wrdev, iclass 37, count 0 2006.285.19:54:54.11#ibcon#first serial, iclass 37, count 0 2006.285.19:54:54.11#ibcon#enter sib2, iclass 37, count 0 2006.285.19:54:54.11#ibcon#flushed, iclass 37, count 0 2006.285.19:54:54.11#ibcon#about to write, iclass 37, count 0 2006.285.19:54:54.11#ibcon#wrote, iclass 37, count 0 2006.285.19:54:54.11#ibcon#about to read 3, iclass 37, count 0 2006.285.19:54:54.13#ibcon#read 3, iclass 37, count 0 2006.285.19:54:54.13#ibcon#about to read 4, iclass 37, count 0 2006.285.19:54:54.13#ibcon#read 4, iclass 37, count 0 2006.285.19:54:54.13#ibcon#about to read 5, iclass 37, count 0 2006.285.19:54:54.13#ibcon#read 5, iclass 37, count 0 2006.285.19:54:54.13#ibcon#about to read 6, iclass 37, count 0 2006.285.19:54:54.13#ibcon#read 6, iclass 37, count 0 2006.285.19:54:54.13#ibcon#end of sib2, iclass 37, count 0 2006.285.19:54:54.13#ibcon#*mode == 0, iclass 37, count 0 2006.285.19:54:54.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.19:54:54.13#ibcon#[25=USB\r\n] 2006.285.19:54:54.13#ibcon#*before write, iclass 37, count 0 2006.285.19:54:54.13#ibcon#enter sib2, iclass 37, count 0 2006.285.19:54:54.13#ibcon#flushed, iclass 37, count 0 2006.285.19:54:54.13#ibcon#about to write, iclass 37, count 0 2006.285.19:54:54.13#ibcon#wrote, iclass 37, count 0 2006.285.19:54:54.13#ibcon#about to read 3, iclass 37, count 0 2006.285.19:54:54.16#ibcon#read 3, iclass 37, count 0 2006.285.19:54:54.16#ibcon#about to read 4, iclass 37, count 0 2006.285.19:54:54.24#ibcon#read 4, iclass 37, count 0 2006.285.19:54:54.24#ibcon#about to read 5, iclass 37, count 0 2006.285.19:54:54.24#ibcon#read 5, iclass 37, count 0 2006.285.19:54:54.24#ibcon#about to read 6, iclass 37, count 0 2006.285.19:54:54.24#ibcon#read 6, iclass 37, count 0 2006.285.19:54:54.24#ibcon#end of sib2, iclass 37, count 0 2006.285.19:54:54.24#ibcon#*after write, iclass 37, count 0 2006.285.19:54:54.24#ibcon#*before return 0, iclass 37, count 0 2006.285.19:54:54.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:54:54.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:54:54.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.19:54:54.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.19:54:54.24$vck44/valo=8,884.99 2006.285.19:54:54.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.19:54:54.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.19:54:54.24#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:54.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:54:54.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:54:54.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:54:54.24#ibcon#enter wrdev, iclass 39, count 0 2006.285.19:54:54.24#ibcon#first serial, iclass 39, count 0 2006.285.19:54:54.24#ibcon#enter sib2, iclass 39, count 0 2006.285.19:54:54.24#ibcon#flushed, iclass 39, count 0 2006.285.19:54:54.24#ibcon#about to write, iclass 39, count 0 2006.285.19:54:54.24#ibcon#wrote, iclass 39, count 0 2006.285.19:54:54.24#ibcon#about to read 3, iclass 39, count 0 2006.285.19:54:54.25#ibcon#read 3, iclass 39, count 0 2006.285.19:54:54.25#ibcon#about to read 4, iclass 39, count 0 2006.285.19:54:54.25#ibcon#read 4, iclass 39, count 0 2006.285.19:54:54.25#ibcon#about to read 5, iclass 39, count 0 2006.285.19:54:54.25#ibcon#read 5, iclass 39, count 0 2006.285.19:54:54.25#ibcon#about to read 6, iclass 39, count 0 2006.285.19:54:54.25#ibcon#read 6, iclass 39, count 0 2006.285.19:54:54.25#ibcon#end of sib2, iclass 39, count 0 2006.285.19:54:54.25#ibcon#*mode == 0, iclass 39, count 0 2006.285.19:54:54.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.19:54:54.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.19:54:54.25#ibcon#*before write, iclass 39, count 0 2006.285.19:54:54.25#ibcon#enter sib2, iclass 39, count 0 2006.285.19:54:54.25#ibcon#flushed, iclass 39, count 0 2006.285.19:54:54.25#ibcon#about to write, iclass 39, count 0 2006.285.19:54:54.25#ibcon#wrote, iclass 39, count 0 2006.285.19:54:54.25#ibcon#about to read 3, iclass 39, count 0 2006.285.19:54:54.29#ibcon#read 3, iclass 39, count 0 2006.285.19:54:54.29#ibcon#about to read 4, iclass 39, count 0 2006.285.19:54:54.29#ibcon#read 4, iclass 39, count 0 2006.285.19:54:54.29#ibcon#about to read 5, iclass 39, count 0 2006.285.19:54:54.29#ibcon#read 5, iclass 39, count 0 2006.285.19:54:54.29#ibcon#about to read 6, iclass 39, count 0 2006.285.19:54:54.29#ibcon#read 6, iclass 39, count 0 2006.285.19:54:54.29#ibcon#end of sib2, iclass 39, count 0 2006.285.19:54:54.29#ibcon#*after write, iclass 39, count 0 2006.285.19:54:54.29#ibcon#*before return 0, iclass 39, count 0 2006.285.19:54:54.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:54:54.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:54:54.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.19:54:54.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.19:54:54.29$vck44/va=8,3 2006.285.19:54:54.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.19:54:54.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.19:54:54.29#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:54.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:54:54.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:54:54.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:54:54.36#ibcon#enter wrdev, iclass 3, count 2 2006.285.19:54:54.36#ibcon#first serial, iclass 3, count 2 2006.285.19:54:54.36#ibcon#enter sib2, iclass 3, count 2 2006.285.19:54:54.36#ibcon#flushed, iclass 3, count 2 2006.285.19:54:54.36#ibcon#about to write, iclass 3, count 2 2006.285.19:54:54.36#ibcon#wrote, iclass 3, count 2 2006.285.19:54:54.36#ibcon#about to read 3, iclass 3, count 2 2006.285.19:54:54.38#ibcon#read 3, iclass 3, count 2 2006.285.19:54:54.38#ibcon#about to read 4, iclass 3, count 2 2006.285.19:54:54.38#ibcon#read 4, iclass 3, count 2 2006.285.19:54:54.38#ibcon#about to read 5, iclass 3, count 2 2006.285.19:54:54.38#ibcon#read 5, iclass 3, count 2 2006.285.19:54:54.38#ibcon#about to read 6, iclass 3, count 2 2006.285.19:54:54.38#ibcon#read 6, iclass 3, count 2 2006.285.19:54:54.38#ibcon#end of sib2, iclass 3, count 2 2006.285.19:54:54.38#ibcon#*mode == 0, iclass 3, count 2 2006.285.19:54:54.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.19:54:54.38#ibcon#[25=AT08-03\r\n] 2006.285.19:54:54.38#ibcon#*before write, iclass 3, count 2 2006.285.19:54:54.38#ibcon#enter sib2, iclass 3, count 2 2006.285.19:54:54.38#ibcon#flushed, iclass 3, count 2 2006.285.19:54:54.38#ibcon#about to write, iclass 3, count 2 2006.285.19:54:54.38#ibcon#wrote, iclass 3, count 2 2006.285.19:54:54.38#ibcon#about to read 3, iclass 3, count 2 2006.285.19:54:54.41#ibcon#read 3, iclass 3, count 2 2006.285.19:54:54.41#ibcon#about to read 4, iclass 3, count 2 2006.285.19:54:54.41#ibcon#read 4, iclass 3, count 2 2006.285.19:54:54.41#ibcon#about to read 5, iclass 3, count 2 2006.285.19:54:54.41#ibcon#read 5, iclass 3, count 2 2006.285.19:54:54.41#ibcon#about to read 6, iclass 3, count 2 2006.285.19:54:54.41#ibcon#read 6, iclass 3, count 2 2006.285.19:54:54.41#ibcon#end of sib2, iclass 3, count 2 2006.285.19:54:54.41#ibcon#*after write, iclass 3, count 2 2006.285.19:54:54.41#ibcon#*before return 0, iclass 3, count 2 2006.285.19:54:54.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:54:54.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.19:54:54.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.19:54:54.41#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:54.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:54:54.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:54:54.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:54:54.53#ibcon#enter wrdev, iclass 3, count 0 2006.285.19:54:54.53#ibcon#first serial, iclass 3, count 0 2006.285.19:54:54.53#ibcon#enter sib2, iclass 3, count 0 2006.285.19:54:54.53#ibcon#flushed, iclass 3, count 0 2006.285.19:54:54.53#ibcon#about to write, iclass 3, count 0 2006.285.19:54:54.53#ibcon#wrote, iclass 3, count 0 2006.285.19:54:54.53#ibcon#about to read 3, iclass 3, count 0 2006.285.19:54:54.55#ibcon#read 3, iclass 3, count 0 2006.285.19:54:54.55#ibcon#about to read 4, iclass 3, count 0 2006.285.19:54:54.55#ibcon#read 4, iclass 3, count 0 2006.285.19:54:54.55#ibcon#about to read 5, iclass 3, count 0 2006.285.19:54:54.55#ibcon#read 5, iclass 3, count 0 2006.285.19:54:54.55#ibcon#about to read 6, iclass 3, count 0 2006.285.19:54:54.55#ibcon#read 6, iclass 3, count 0 2006.285.19:54:54.55#ibcon#end of sib2, iclass 3, count 0 2006.285.19:54:54.55#ibcon#*mode == 0, iclass 3, count 0 2006.285.19:54:54.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.19:54:54.55#ibcon#[25=USB\r\n] 2006.285.19:54:54.55#ibcon#*before write, iclass 3, count 0 2006.285.19:54:54.55#ibcon#enter sib2, iclass 3, count 0 2006.285.19:54:54.55#ibcon#flushed, iclass 3, count 0 2006.285.19:54:54.55#ibcon#about to write, iclass 3, count 0 2006.285.19:54:54.55#ibcon#wrote, iclass 3, count 0 2006.285.19:54:54.55#ibcon#about to read 3, iclass 3, count 0 2006.285.19:54:54.58#ibcon#read 3, iclass 3, count 0 2006.285.19:54:54.58#ibcon#about to read 4, iclass 3, count 0 2006.285.19:54:54.58#ibcon#read 4, iclass 3, count 0 2006.285.19:54:54.58#ibcon#about to read 5, iclass 3, count 0 2006.285.19:54:54.58#ibcon#read 5, iclass 3, count 0 2006.285.19:54:54.58#ibcon#about to read 6, iclass 3, count 0 2006.285.19:54:54.58#ibcon#read 6, iclass 3, count 0 2006.285.19:54:54.58#ibcon#end of sib2, iclass 3, count 0 2006.285.19:54:54.58#ibcon#*after write, iclass 3, count 0 2006.285.19:54:54.58#ibcon#*before return 0, iclass 3, count 0 2006.285.19:54:54.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:54:54.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.19:54:54.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.19:54:54.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.19:54:54.58$vck44/vblo=1,629.99 2006.285.19:54:54.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.19:54:54.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.19:54:54.58#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:54.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:54:54.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:54:54.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:54:54.58#ibcon#enter wrdev, iclass 5, count 0 2006.285.19:54:54.58#ibcon#first serial, iclass 5, count 0 2006.285.19:54:54.58#ibcon#enter sib2, iclass 5, count 0 2006.285.19:54:54.58#ibcon#flushed, iclass 5, count 0 2006.285.19:54:54.58#ibcon#about to write, iclass 5, count 0 2006.285.19:54:54.58#ibcon#wrote, iclass 5, count 0 2006.285.19:54:54.58#ibcon#about to read 3, iclass 5, count 0 2006.285.19:54:54.60#ibcon#read 3, iclass 5, count 0 2006.285.19:54:54.60#ibcon#about to read 4, iclass 5, count 0 2006.285.19:54:54.60#ibcon#read 4, iclass 5, count 0 2006.285.19:54:54.60#ibcon#about to read 5, iclass 5, count 0 2006.285.19:54:54.60#ibcon#read 5, iclass 5, count 0 2006.285.19:54:54.60#ibcon#about to read 6, iclass 5, count 0 2006.285.19:54:54.60#ibcon#read 6, iclass 5, count 0 2006.285.19:54:54.60#ibcon#end of sib2, iclass 5, count 0 2006.285.19:54:54.60#ibcon#*mode == 0, iclass 5, count 0 2006.285.19:54:54.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.19:54:54.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.19:54:54.60#ibcon#*before write, iclass 5, count 0 2006.285.19:54:54.60#ibcon#enter sib2, iclass 5, count 0 2006.285.19:54:54.60#ibcon#flushed, iclass 5, count 0 2006.285.19:54:54.60#ibcon#about to write, iclass 5, count 0 2006.285.19:54:54.60#ibcon#wrote, iclass 5, count 0 2006.285.19:54:54.60#ibcon#about to read 3, iclass 5, count 0 2006.285.19:54:54.64#ibcon#read 3, iclass 5, count 0 2006.285.19:54:54.64#ibcon#about to read 4, iclass 5, count 0 2006.285.19:54:54.64#ibcon#read 4, iclass 5, count 0 2006.285.19:54:54.64#ibcon#about to read 5, iclass 5, count 0 2006.285.19:54:54.64#ibcon#read 5, iclass 5, count 0 2006.285.19:54:54.64#ibcon#about to read 6, iclass 5, count 0 2006.285.19:54:54.64#ibcon#read 6, iclass 5, count 0 2006.285.19:54:54.64#ibcon#end of sib2, iclass 5, count 0 2006.285.19:54:54.64#ibcon#*after write, iclass 5, count 0 2006.285.19:54:54.64#ibcon#*before return 0, iclass 5, count 0 2006.285.19:54:54.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:54:54.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.19:54:54.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.19:54:54.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.19:54:54.64$vck44/vb=1,4 2006.285.19:54:54.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.19:54:54.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.19:54:54.64#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:54.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:54:54.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:54:54.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:54:54.64#ibcon#enter wrdev, iclass 7, count 2 2006.285.19:54:54.64#ibcon#first serial, iclass 7, count 2 2006.285.19:54:54.64#ibcon#enter sib2, iclass 7, count 2 2006.285.19:54:54.64#ibcon#flushed, iclass 7, count 2 2006.285.19:54:54.64#ibcon#about to write, iclass 7, count 2 2006.285.19:54:54.64#ibcon#wrote, iclass 7, count 2 2006.285.19:54:54.64#ibcon#about to read 3, iclass 7, count 2 2006.285.19:54:54.66#ibcon#read 3, iclass 7, count 2 2006.285.19:54:54.66#ibcon#about to read 4, iclass 7, count 2 2006.285.19:54:54.66#ibcon#read 4, iclass 7, count 2 2006.285.19:54:54.66#ibcon#about to read 5, iclass 7, count 2 2006.285.19:54:54.66#ibcon#read 5, iclass 7, count 2 2006.285.19:54:54.66#ibcon#about to read 6, iclass 7, count 2 2006.285.19:54:54.66#ibcon#read 6, iclass 7, count 2 2006.285.19:54:54.66#ibcon#end of sib2, iclass 7, count 2 2006.285.19:54:54.66#ibcon#*mode == 0, iclass 7, count 2 2006.285.19:54:54.66#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.19:54:54.66#ibcon#[27=AT01-04\r\n] 2006.285.19:54:54.66#ibcon#*before write, iclass 7, count 2 2006.285.19:54:54.66#ibcon#enter sib2, iclass 7, count 2 2006.285.19:54:54.66#ibcon#flushed, iclass 7, count 2 2006.285.19:54:54.66#ibcon#about to write, iclass 7, count 2 2006.285.19:54:54.66#ibcon#wrote, iclass 7, count 2 2006.285.19:54:54.66#ibcon#about to read 3, iclass 7, count 2 2006.285.19:54:54.69#ibcon#read 3, iclass 7, count 2 2006.285.19:54:54.69#ibcon#about to read 4, iclass 7, count 2 2006.285.19:54:54.69#ibcon#read 4, iclass 7, count 2 2006.285.19:54:54.69#ibcon#about to read 5, iclass 7, count 2 2006.285.19:54:54.69#ibcon#read 5, iclass 7, count 2 2006.285.19:54:54.69#ibcon#about to read 6, iclass 7, count 2 2006.285.19:54:54.69#ibcon#read 6, iclass 7, count 2 2006.285.19:54:54.69#ibcon#end of sib2, iclass 7, count 2 2006.285.19:54:54.69#ibcon#*after write, iclass 7, count 2 2006.285.19:54:54.69#ibcon#*before return 0, iclass 7, count 2 2006.285.19:54:54.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:54:54.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.19:54:54.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.19:54:54.69#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:54.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:54:54.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:54:54.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:54:54.81#ibcon#enter wrdev, iclass 7, count 0 2006.285.19:54:54.81#ibcon#first serial, iclass 7, count 0 2006.285.19:54:54.81#ibcon#enter sib2, iclass 7, count 0 2006.285.19:54:54.81#ibcon#flushed, iclass 7, count 0 2006.285.19:54:54.81#ibcon#about to write, iclass 7, count 0 2006.285.19:54:54.81#ibcon#wrote, iclass 7, count 0 2006.285.19:54:54.81#ibcon#about to read 3, iclass 7, count 0 2006.285.19:54:54.83#ibcon#read 3, iclass 7, count 0 2006.285.19:54:54.83#ibcon#about to read 4, iclass 7, count 0 2006.285.19:54:54.83#ibcon#read 4, iclass 7, count 0 2006.285.19:54:54.83#ibcon#about to read 5, iclass 7, count 0 2006.285.19:54:54.83#ibcon#read 5, iclass 7, count 0 2006.285.19:54:54.83#ibcon#about to read 6, iclass 7, count 0 2006.285.19:54:54.83#ibcon#read 6, iclass 7, count 0 2006.285.19:54:54.83#ibcon#end of sib2, iclass 7, count 0 2006.285.19:54:54.83#ibcon#*mode == 0, iclass 7, count 0 2006.285.19:54:54.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.19:54:54.83#ibcon#[27=USB\r\n] 2006.285.19:54:54.83#ibcon#*before write, iclass 7, count 0 2006.285.19:54:54.83#ibcon#enter sib2, iclass 7, count 0 2006.285.19:54:54.83#ibcon#flushed, iclass 7, count 0 2006.285.19:54:54.83#ibcon#about to write, iclass 7, count 0 2006.285.19:54:54.83#ibcon#wrote, iclass 7, count 0 2006.285.19:54:54.83#ibcon#about to read 3, iclass 7, count 0 2006.285.19:54:54.86#ibcon#read 3, iclass 7, count 0 2006.285.19:54:54.86#ibcon#about to read 4, iclass 7, count 0 2006.285.19:54:54.86#ibcon#read 4, iclass 7, count 0 2006.285.19:54:54.86#ibcon#about to read 5, iclass 7, count 0 2006.285.19:54:54.86#ibcon#read 5, iclass 7, count 0 2006.285.19:54:54.86#ibcon#about to read 6, iclass 7, count 0 2006.285.19:54:54.86#ibcon#read 6, iclass 7, count 0 2006.285.19:54:54.86#ibcon#end of sib2, iclass 7, count 0 2006.285.19:54:54.86#ibcon#*after write, iclass 7, count 0 2006.285.19:54:54.86#ibcon#*before return 0, iclass 7, count 0 2006.285.19:54:54.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:54:54.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.19:54:54.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.19:54:54.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.19:54:54.86$vck44/vblo=2,634.99 2006.285.19:54:54.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.19:54:54.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.19:54:54.86#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:54.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:54:54.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:54:54.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:54:54.86#ibcon#enter wrdev, iclass 11, count 0 2006.285.19:54:54.86#ibcon#first serial, iclass 11, count 0 2006.285.19:54:54.86#ibcon#enter sib2, iclass 11, count 0 2006.285.19:54:54.86#ibcon#flushed, iclass 11, count 0 2006.285.19:54:54.86#ibcon#about to write, iclass 11, count 0 2006.285.19:54:54.86#ibcon#wrote, iclass 11, count 0 2006.285.19:54:54.86#ibcon#about to read 3, iclass 11, count 0 2006.285.19:54:54.88#ibcon#read 3, iclass 11, count 0 2006.285.19:54:54.88#ibcon#about to read 4, iclass 11, count 0 2006.285.19:54:54.88#ibcon#read 4, iclass 11, count 0 2006.285.19:54:54.88#ibcon#about to read 5, iclass 11, count 0 2006.285.19:54:54.88#ibcon#read 5, iclass 11, count 0 2006.285.19:54:54.88#ibcon#about to read 6, iclass 11, count 0 2006.285.19:54:54.88#ibcon#read 6, iclass 11, count 0 2006.285.19:54:54.88#ibcon#end of sib2, iclass 11, count 0 2006.285.19:54:54.88#ibcon#*mode == 0, iclass 11, count 0 2006.285.19:54:54.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.19:54:54.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.19:54:54.88#ibcon#*before write, iclass 11, count 0 2006.285.19:54:54.88#ibcon#enter sib2, iclass 11, count 0 2006.285.19:54:54.88#ibcon#flushed, iclass 11, count 0 2006.285.19:54:54.88#ibcon#about to write, iclass 11, count 0 2006.285.19:54:54.88#ibcon#wrote, iclass 11, count 0 2006.285.19:54:54.88#ibcon#about to read 3, iclass 11, count 0 2006.285.19:54:54.92#ibcon#read 3, iclass 11, count 0 2006.285.19:54:54.92#ibcon#about to read 4, iclass 11, count 0 2006.285.19:54:54.92#ibcon#read 4, iclass 11, count 0 2006.285.19:54:54.92#ibcon#about to read 5, iclass 11, count 0 2006.285.19:54:54.92#ibcon#read 5, iclass 11, count 0 2006.285.19:54:54.92#ibcon#about to read 6, iclass 11, count 0 2006.285.19:54:54.92#ibcon#read 6, iclass 11, count 0 2006.285.19:54:54.92#ibcon#end of sib2, iclass 11, count 0 2006.285.19:54:54.92#ibcon#*after write, iclass 11, count 0 2006.285.19:54:54.92#ibcon#*before return 0, iclass 11, count 0 2006.285.19:54:54.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:54:54.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.19:54:54.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.19:54:54.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.19:54:54.92$vck44/vb=2,5 2006.285.19:54:54.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.19:54:54.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.19:54:54.92#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:54.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:54:54.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:54:54.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:54:54.98#ibcon#enter wrdev, iclass 13, count 2 2006.285.19:54:54.98#ibcon#first serial, iclass 13, count 2 2006.285.19:54:54.98#ibcon#enter sib2, iclass 13, count 2 2006.285.19:54:54.98#ibcon#flushed, iclass 13, count 2 2006.285.19:54:54.98#ibcon#about to write, iclass 13, count 2 2006.285.19:54:54.98#ibcon#wrote, iclass 13, count 2 2006.285.19:54:54.98#ibcon#about to read 3, iclass 13, count 2 2006.285.19:54:55.00#ibcon#read 3, iclass 13, count 2 2006.285.19:54:55.00#ibcon#about to read 4, iclass 13, count 2 2006.285.19:54:55.00#ibcon#read 4, iclass 13, count 2 2006.285.19:54:55.00#ibcon#about to read 5, iclass 13, count 2 2006.285.19:54:55.00#ibcon#read 5, iclass 13, count 2 2006.285.19:54:55.00#ibcon#about to read 6, iclass 13, count 2 2006.285.19:54:55.00#ibcon#read 6, iclass 13, count 2 2006.285.19:54:55.00#ibcon#end of sib2, iclass 13, count 2 2006.285.19:54:55.00#ibcon#*mode == 0, iclass 13, count 2 2006.285.19:54:55.00#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.19:54:55.00#ibcon#[27=AT02-05\r\n] 2006.285.19:54:55.00#ibcon#*before write, iclass 13, count 2 2006.285.19:54:55.00#ibcon#enter sib2, iclass 13, count 2 2006.285.19:54:55.00#ibcon#flushed, iclass 13, count 2 2006.285.19:54:55.00#ibcon#about to write, iclass 13, count 2 2006.285.19:54:55.00#ibcon#wrote, iclass 13, count 2 2006.285.19:54:55.00#ibcon#about to read 3, iclass 13, count 2 2006.285.19:54:55.03#ibcon#read 3, iclass 13, count 2 2006.285.19:54:55.03#ibcon#about to read 4, iclass 13, count 2 2006.285.19:54:55.03#ibcon#read 4, iclass 13, count 2 2006.285.19:54:55.03#ibcon#about to read 5, iclass 13, count 2 2006.285.19:54:55.03#ibcon#read 5, iclass 13, count 2 2006.285.19:54:55.03#ibcon#about to read 6, iclass 13, count 2 2006.285.19:54:55.03#ibcon#read 6, iclass 13, count 2 2006.285.19:54:55.03#ibcon#end of sib2, iclass 13, count 2 2006.285.19:54:55.03#ibcon#*after write, iclass 13, count 2 2006.285.19:54:55.03#ibcon#*before return 0, iclass 13, count 2 2006.285.19:54:55.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:54:55.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.19:54:55.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.19:54:55.03#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:55.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:54:55.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:54:55.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:54:55.15#ibcon#enter wrdev, iclass 13, count 0 2006.285.19:54:55.15#ibcon#first serial, iclass 13, count 0 2006.285.19:54:55.15#ibcon#enter sib2, iclass 13, count 0 2006.285.19:54:55.15#ibcon#flushed, iclass 13, count 0 2006.285.19:54:55.15#ibcon#about to write, iclass 13, count 0 2006.285.19:54:55.15#ibcon#wrote, iclass 13, count 0 2006.285.19:54:55.15#ibcon#about to read 3, iclass 13, count 0 2006.285.19:54:55.17#ibcon#read 3, iclass 13, count 0 2006.285.19:54:55.17#ibcon#about to read 4, iclass 13, count 0 2006.285.19:54:55.17#ibcon#read 4, iclass 13, count 0 2006.285.19:54:55.17#ibcon#about to read 5, iclass 13, count 0 2006.285.19:54:55.17#ibcon#read 5, iclass 13, count 0 2006.285.19:54:55.17#ibcon#about to read 6, iclass 13, count 0 2006.285.19:54:55.17#ibcon#read 6, iclass 13, count 0 2006.285.19:54:55.17#ibcon#end of sib2, iclass 13, count 0 2006.285.19:54:55.17#ibcon#*mode == 0, iclass 13, count 0 2006.285.19:54:55.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.19:54:55.17#ibcon#[27=USB\r\n] 2006.285.19:54:55.17#ibcon#*before write, iclass 13, count 0 2006.285.19:54:55.17#ibcon#enter sib2, iclass 13, count 0 2006.285.19:54:55.17#ibcon#flushed, iclass 13, count 0 2006.285.19:54:55.17#ibcon#about to write, iclass 13, count 0 2006.285.19:54:55.17#ibcon#wrote, iclass 13, count 0 2006.285.19:54:55.17#ibcon#about to read 3, iclass 13, count 0 2006.285.19:54:55.20#ibcon#read 3, iclass 13, count 0 2006.285.19:54:55.20#ibcon#about to read 4, iclass 13, count 0 2006.285.19:54:55.20#ibcon#read 4, iclass 13, count 0 2006.285.19:54:55.20#ibcon#about to read 5, iclass 13, count 0 2006.285.19:54:55.20#ibcon#read 5, iclass 13, count 0 2006.285.19:54:55.20#ibcon#about to read 6, iclass 13, count 0 2006.285.19:54:55.20#ibcon#read 6, iclass 13, count 0 2006.285.19:54:55.20#ibcon#end of sib2, iclass 13, count 0 2006.285.19:54:55.20#ibcon#*after write, iclass 13, count 0 2006.285.19:54:55.20#ibcon#*before return 0, iclass 13, count 0 2006.285.19:54:55.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:54:55.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.19:54:55.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.19:54:55.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.19:54:55.20$vck44/vblo=3,649.99 2006.285.19:54:55.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.19:54:55.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.19:54:55.20#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:55.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:54:55.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:54:55.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:54:55.20#ibcon#enter wrdev, iclass 15, count 0 2006.285.19:54:55.20#ibcon#first serial, iclass 15, count 0 2006.285.19:54:55.20#ibcon#enter sib2, iclass 15, count 0 2006.285.19:54:55.20#ibcon#flushed, iclass 15, count 0 2006.285.19:54:55.20#ibcon#about to write, iclass 15, count 0 2006.285.19:54:55.20#ibcon#wrote, iclass 15, count 0 2006.285.19:54:55.20#ibcon#about to read 3, iclass 15, count 0 2006.285.19:54:55.22#ibcon#read 3, iclass 15, count 0 2006.285.19:54:55.22#ibcon#about to read 4, iclass 15, count 0 2006.285.19:54:55.22#ibcon#read 4, iclass 15, count 0 2006.285.19:54:55.22#ibcon#about to read 5, iclass 15, count 0 2006.285.19:54:55.22#ibcon#read 5, iclass 15, count 0 2006.285.19:54:55.22#ibcon#about to read 6, iclass 15, count 0 2006.285.19:54:55.22#ibcon#read 6, iclass 15, count 0 2006.285.19:54:55.22#ibcon#end of sib2, iclass 15, count 0 2006.285.19:54:55.22#ibcon#*mode == 0, iclass 15, count 0 2006.285.19:54:55.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.19:54:55.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.19:54:55.22#ibcon#*before write, iclass 15, count 0 2006.285.19:54:55.22#ibcon#enter sib2, iclass 15, count 0 2006.285.19:54:55.22#ibcon#flushed, iclass 15, count 0 2006.285.19:54:55.22#ibcon#about to write, iclass 15, count 0 2006.285.19:54:55.22#ibcon#wrote, iclass 15, count 0 2006.285.19:54:55.22#ibcon#about to read 3, iclass 15, count 0 2006.285.19:54:55.26#ibcon#read 3, iclass 15, count 0 2006.285.19:54:55.26#ibcon#about to read 4, iclass 15, count 0 2006.285.19:54:55.26#ibcon#read 4, iclass 15, count 0 2006.285.19:54:55.26#ibcon#about to read 5, iclass 15, count 0 2006.285.19:54:55.26#ibcon#read 5, iclass 15, count 0 2006.285.19:54:55.26#ibcon#about to read 6, iclass 15, count 0 2006.285.19:54:55.26#ibcon#read 6, iclass 15, count 0 2006.285.19:54:55.26#ibcon#end of sib2, iclass 15, count 0 2006.285.19:54:55.26#ibcon#*after write, iclass 15, count 0 2006.285.19:54:55.26#ibcon#*before return 0, iclass 15, count 0 2006.285.19:54:55.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:54:55.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.19:54:55.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.19:54:55.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.19:54:55.26$vck44/vb=3,4 2006.285.19:54:55.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.19:54:55.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.19:54:55.26#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:55.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:54:55.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:54:55.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:54:55.32#ibcon#enter wrdev, iclass 17, count 2 2006.285.19:54:55.32#ibcon#first serial, iclass 17, count 2 2006.285.19:54:55.32#ibcon#enter sib2, iclass 17, count 2 2006.285.19:54:55.32#ibcon#flushed, iclass 17, count 2 2006.285.19:54:55.32#ibcon#about to write, iclass 17, count 2 2006.285.19:54:55.32#ibcon#wrote, iclass 17, count 2 2006.285.19:54:55.32#ibcon#about to read 3, iclass 17, count 2 2006.285.19:54:55.34#ibcon#read 3, iclass 17, count 2 2006.285.19:54:55.34#ibcon#about to read 4, iclass 17, count 2 2006.285.19:54:55.34#ibcon#read 4, iclass 17, count 2 2006.285.19:54:55.34#ibcon#about to read 5, iclass 17, count 2 2006.285.19:54:55.34#ibcon#read 5, iclass 17, count 2 2006.285.19:54:55.34#ibcon#about to read 6, iclass 17, count 2 2006.285.19:54:55.34#ibcon#read 6, iclass 17, count 2 2006.285.19:54:55.34#ibcon#end of sib2, iclass 17, count 2 2006.285.19:54:55.34#ibcon#*mode == 0, iclass 17, count 2 2006.285.19:54:55.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.19:54:55.34#ibcon#[27=AT03-04\r\n] 2006.285.19:54:55.34#ibcon#*before write, iclass 17, count 2 2006.285.19:54:55.34#ibcon#enter sib2, iclass 17, count 2 2006.285.19:54:55.34#ibcon#flushed, iclass 17, count 2 2006.285.19:54:55.34#ibcon#about to write, iclass 17, count 2 2006.285.19:54:55.34#ibcon#wrote, iclass 17, count 2 2006.285.19:54:55.34#ibcon#about to read 3, iclass 17, count 2 2006.285.19:54:55.37#ibcon#read 3, iclass 17, count 2 2006.285.19:54:55.37#ibcon#about to read 4, iclass 17, count 2 2006.285.19:54:55.37#ibcon#read 4, iclass 17, count 2 2006.285.19:54:55.37#ibcon#about to read 5, iclass 17, count 2 2006.285.19:54:55.37#ibcon#read 5, iclass 17, count 2 2006.285.19:54:55.37#ibcon#about to read 6, iclass 17, count 2 2006.285.19:54:55.37#ibcon#read 6, iclass 17, count 2 2006.285.19:54:55.37#ibcon#end of sib2, iclass 17, count 2 2006.285.19:54:55.37#ibcon#*after write, iclass 17, count 2 2006.285.19:54:55.37#ibcon#*before return 0, iclass 17, count 2 2006.285.19:54:55.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:54:55.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.19:54:55.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.19:54:55.37#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:55.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:54:55.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:54:55.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:54:55.49#ibcon#enter wrdev, iclass 17, count 0 2006.285.19:54:55.49#ibcon#first serial, iclass 17, count 0 2006.285.19:54:55.49#ibcon#enter sib2, iclass 17, count 0 2006.285.19:54:55.49#ibcon#flushed, iclass 17, count 0 2006.285.19:54:55.49#ibcon#about to write, iclass 17, count 0 2006.285.19:54:55.49#ibcon#wrote, iclass 17, count 0 2006.285.19:54:55.49#ibcon#about to read 3, iclass 17, count 0 2006.285.19:54:55.51#ibcon#read 3, iclass 17, count 0 2006.285.19:54:55.51#ibcon#about to read 4, iclass 17, count 0 2006.285.19:54:55.51#ibcon#read 4, iclass 17, count 0 2006.285.19:54:55.51#ibcon#about to read 5, iclass 17, count 0 2006.285.19:54:55.51#ibcon#read 5, iclass 17, count 0 2006.285.19:54:55.51#ibcon#about to read 6, iclass 17, count 0 2006.285.19:54:55.51#ibcon#read 6, iclass 17, count 0 2006.285.19:54:55.51#ibcon#end of sib2, iclass 17, count 0 2006.285.19:54:55.51#ibcon#*mode == 0, iclass 17, count 0 2006.285.19:54:55.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.19:54:55.51#ibcon#[27=USB\r\n] 2006.285.19:54:55.51#ibcon#*before write, iclass 17, count 0 2006.285.19:54:55.51#ibcon#enter sib2, iclass 17, count 0 2006.285.19:54:55.51#ibcon#flushed, iclass 17, count 0 2006.285.19:54:55.51#ibcon#about to write, iclass 17, count 0 2006.285.19:54:55.51#ibcon#wrote, iclass 17, count 0 2006.285.19:54:55.51#ibcon#about to read 3, iclass 17, count 0 2006.285.19:54:55.54#ibcon#read 3, iclass 17, count 0 2006.285.19:54:55.54#ibcon#about to read 4, iclass 17, count 0 2006.285.19:54:55.54#ibcon#read 4, iclass 17, count 0 2006.285.19:54:55.54#ibcon#about to read 5, iclass 17, count 0 2006.285.19:54:55.54#ibcon#read 5, iclass 17, count 0 2006.285.19:54:55.54#ibcon#about to read 6, iclass 17, count 0 2006.285.19:54:55.54#ibcon#read 6, iclass 17, count 0 2006.285.19:54:55.54#ibcon#end of sib2, iclass 17, count 0 2006.285.19:54:55.54#ibcon#*after write, iclass 17, count 0 2006.285.19:54:55.54#ibcon#*before return 0, iclass 17, count 0 2006.285.19:54:55.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:54:55.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.19:54:55.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.19:54:55.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.19:54:55.54$vck44/vblo=4,679.99 2006.285.19:54:55.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.19:54:55.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.19:54:55.54#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:55.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:54:55.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:54:55.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:54:55.54#ibcon#enter wrdev, iclass 19, count 0 2006.285.19:54:55.54#ibcon#first serial, iclass 19, count 0 2006.285.19:54:55.54#ibcon#enter sib2, iclass 19, count 0 2006.285.19:54:55.54#ibcon#flushed, iclass 19, count 0 2006.285.19:54:55.54#ibcon#about to write, iclass 19, count 0 2006.285.19:54:55.54#ibcon#wrote, iclass 19, count 0 2006.285.19:54:55.54#ibcon#about to read 3, iclass 19, count 0 2006.285.19:54:55.56#ibcon#read 3, iclass 19, count 0 2006.285.19:54:55.56#ibcon#about to read 4, iclass 19, count 0 2006.285.19:54:55.56#ibcon#read 4, iclass 19, count 0 2006.285.19:54:55.56#ibcon#about to read 5, iclass 19, count 0 2006.285.19:54:55.56#ibcon#read 5, iclass 19, count 0 2006.285.19:54:55.56#ibcon#about to read 6, iclass 19, count 0 2006.285.19:54:55.56#ibcon#read 6, iclass 19, count 0 2006.285.19:54:55.56#ibcon#end of sib2, iclass 19, count 0 2006.285.19:54:55.56#ibcon#*mode == 0, iclass 19, count 0 2006.285.19:54:55.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.19:54:55.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.19:54:55.56#ibcon#*before write, iclass 19, count 0 2006.285.19:54:55.56#ibcon#enter sib2, iclass 19, count 0 2006.285.19:54:55.56#ibcon#flushed, iclass 19, count 0 2006.285.19:54:55.56#ibcon#about to write, iclass 19, count 0 2006.285.19:54:55.56#ibcon#wrote, iclass 19, count 0 2006.285.19:54:55.56#ibcon#about to read 3, iclass 19, count 0 2006.285.19:54:55.60#ibcon#read 3, iclass 19, count 0 2006.285.19:54:55.60#ibcon#about to read 4, iclass 19, count 0 2006.285.19:54:55.60#ibcon#read 4, iclass 19, count 0 2006.285.19:54:55.60#ibcon#about to read 5, iclass 19, count 0 2006.285.19:54:55.60#ibcon#read 5, iclass 19, count 0 2006.285.19:54:55.60#ibcon#about to read 6, iclass 19, count 0 2006.285.19:54:55.60#ibcon#read 6, iclass 19, count 0 2006.285.19:54:55.60#ibcon#end of sib2, iclass 19, count 0 2006.285.19:54:55.60#ibcon#*after write, iclass 19, count 0 2006.285.19:54:55.60#ibcon#*before return 0, iclass 19, count 0 2006.285.19:54:55.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:54:55.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.19:54:55.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.19:54:55.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.19:54:55.60$vck44/vb=4,5 2006.285.19:54:55.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.19:54:55.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.19:54:55.60#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:55.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:54:55.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:54:55.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:54:55.66#ibcon#enter wrdev, iclass 21, count 2 2006.285.19:54:55.66#ibcon#first serial, iclass 21, count 2 2006.285.19:54:55.66#ibcon#enter sib2, iclass 21, count 2 2006.285.19:54:55.66#ibcon#flushed, iclass 21, count 2 2006.285.19:54:55.66#ibcon#about to write, iclass 21, count 2 2006.285.19:54:55.66#ibcon#wrote, iclass 21, count 2 2006.285.19:54:55.66#ibcon#about to read 3, iclass 21, count 2 2006.285.19:54:55.68#ibcon#read 3, iclass 21, count 2 2006.285.19:54:55.68#ibcon#about to read 4, iclass 21, count 2 2006.285.19:54:55.68#ibcon#read 4, iclass 21, count 2 2006.285.19:54:55.68#ibcon#about to read 5, iclass 21, count 2 2006.285.19:54:55.68#ibcon#read 5, iclass 21, count 2 2006.285.19:54:55.68#ibcon#about to read 6, iclass 21, count 2 2006.285.19:54:55.68#ibcon#read 6, iclass 21, count 2 2006.285.19:54:55.68#ibcon#end of sib2, iclass 21, count 2 2006.285.19:54:55.68#ibcon#*mode == 0, iclass 21, count 2 2006.285.19:54:55.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.19:54:55.68#ibcon#[27=AT04-05\r\n] 2006.285.19:54:55.68#ibcon#*before write, iclass 21, count 2 2006.285.19:54:55.68#ibcon#enter sib2, iclass 21, count 2 2006.285.19:54:55.68#ibcon#flushed, iclass 21, count 2 2006.285.19:54:55.68#ibcon#about to write, iclass 21, count 2 2006.285.19:54:55.68#ibcon#wrote, iclass 21, count 2 2006.285.19:54:55.68#ibcon#about to read 3, iclass 21, count 2 2006.285.19:54:55.71#ibcon#read 3, iclass 21, count 2 2006.285.19:54:55.71#ibcon#about to read 4, iclass 21, count 2 2006.285.19:54:55.71#ibcon#read 4, iclass 21, count 2 2006.285.19:54:55.71#ibcon#about to read 5, iclass 21, count 2 2006.285.19:54:55.71#ibcon#read 5, iclass 21, count 2 2006.285.19:54:55.71#ibcon#about to read 6, iclass 21, count 2 2006.285.19:54:55.71#ibcon#read 6, iclass 21, count 2 2006.285.19:54:55.71#ibcon#end of sib2, iclass 21, count 2 2006.285.19:54:55.71#ibcon#*after write, iclass 21, count 2 2006.285.19:54:55.71#ibcon#*before return 0, iclass 21, count 2 2006.285.19:54:55.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:54:55.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.19:54:55.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.19:54:55.71#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:55.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:54:55.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:54:55.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:54:55.83#ibcon#enter wrdev, iclass 21, count 0 2006.285.19:54:55.83#ibcon#first serial, iclass 21, count 0 2006.285.19:54:55.83#ibcon#enter sib2, iclass 21, count 0 2006.285.19:54:55.83#ibcon#flushed, iclass 21, count 0 2006.285.19:54:55.83#ibcon#about to write, iclass 21, count 0 2006.285.19:54:55.83#ibcon#wrote, iclass 21, count 0 2006.285.19:54:55.83#ibcon#about to read 3, iclass 21, count 0 2006.285.19:54:55.85#ibcon#read 3, iclass 21, count 0 2006.285.19:54:55.85#ibcon#about to read 4, iclass 21, count 0 2006.285.19:54:55.85#ibcon#read 4, iclass 21, count 0 2006.285.19:54:55.85#ibcon#about to read 5, iclass 21, count 0 2006.285.19:54:55.85#ibcon#read 5, iclass 21, count 0 2006.285.19:54:55.85#ibcon#about to read 6, iclass 21, count 0 2006.285.19:54:55.85#ibcon#read 6, iclass 21, count 0 2006.285.19:54:55.85#ibcon#end of sib2, iclass 21, count 0 2006.285.19:54:55.85#ibcon#*mode == 0, iclass 21, count 0 2006.285.19:54:55.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.19:54:55.85#ibcon#[27=USB\r\n] 2006.285.19:54:55.85#ibcon#*before write, iclass 21, count 0 2006.285.19:54:55.85#ibcon#enter sib2, iclass 21, count 0 2006.285.19:54:55.85#ibcon#flushed, iclass 21, count 0 2006.285.19:54:55.85#ibcon#about to write, iclass 21, count 0 2006.285.19:54:55.85#ibcon#wrote, iclass 21, count 0 2006.285.19:54:55.85#ibcon#about to read 3, iclass 21, count 0 2006.285.19:54:55.88#ibcon#read 3, iclass 21, count 0 2006.285.19:54:55.88#ibcon#about to read 4, iclass 21, count 0 2006.285.19:54:55.88#ibcon#read 4, iclass 21, count 0 2006.285.19:54:55.88#ibcon#about to read 5, iclass 21, count 0 2006.285.19:54:55.88#ibcon#read 5, iclass 21, count 0 2006.285.19:54:55.88#ibcon#about to read 6, iclass 21, count 0 2006.285.19:54:55.88#ibcon#read 6, iclass 21, count 0 2006.285.19:54:55.88#ibcon#end of sib2, iclass 21, count 0 2006.285.19:54:55.88#ibcon#*after write, iclass 21, count 0 2006.285.19:54:55.88#ibcon#*before return 0, iclass 21, count 0 2006.285.19:54:55.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:54:55.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.19:54:55.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.19:54:55.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.19:54:55.88$vck44/vblo=5,709.99 2006.285.19:54:55.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.19:54:55.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.19:54:55.88#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:55.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:54:55.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:54:55.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:54:55.88#ibcon#enter wrdev, iclass 23, count 0 2006.285.19:54:55.88#ibcon#first serial, iclass 23, count 0 2006.285.19:54:55.88#ibcon#enter sib2, iclass 23, count 0 2006.285.19:54:55.88#ibcon#flushed, iclass 23, count 0 2006.285.19:54:55.88#ibcon#about to write, iclass 23, count 0 2006.285.19:54:55.88#ibcon#wrote, iclass 23, count 0 2006.285.19:54:55.88#ibcon#about to read 3, iclass 23, count 0 2006.285.19:54:55.90#ibcon#read 3, iclass 23, count 0 2006.285.19:54:55.90#ibcon#about to read 4, iclass 23, count 0 2006.285.19:54:55.90#ibcon#read 4, iclass 23, count 0 2006.285.19:54:55.90#ibcon#about to read 5, iclass 23, count 0 2006.285.19:54:55.90#ibcon#read 5, iclass 23, count 0 2006.285.19:54:55.90#ibcon#about to read 6, iclass 23, count 0 2006.285.19:54:55.90#ibcon#read 6, iclass 23, count 0 2006.285.19:54:55.90#ibcon#end of sib2, iclass 23, count 0 2006.285.19:54:55.90#ibcon#*mode == 0, iclass 23, count 0 2006.285.19:54:55.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.19:54:55.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.19:54:55.90#ibcon#*before write, iclass 23, count 0 2006.285.19:54:55.90#ibcon#enter sib2, iclass 23, count 0 2006.285.19:54:55.90#ibcon#flushed, iclass 23, count 0 2006.285.19:54:55.90#ibcon#about to write, iclass 23, count 0 2006.285.19:54:55.90#ibcon#wrote, iclass 23, count 0 2006.285.19:54:55.90#ibcon#about to read 3, iclass 23, count 0 2006.285.19:54:55.94#ibcon#read 3, iclass 23, count 0 2006.285.19:54:55.94#ibcon#about to read 4, iclass 23, count 0 2006.285.19:54:55.94#ibcon#read 4, iclass 23, count 0 2006.285.19:54:55.94#ibcon#about to read 5, iclass 23, count 0 2006.285.19:54:55.94#ibcon#read 5, iclass 23, count 0 2006.285.19:54:55.94#ibcon#about to read 6, iclass 23, count 0 2006.285.19:54:55.94#ibcon#read 6, iclass 23, count 0 2006.285.19:54:55.94#ibcon#end of sib2, iclass 23, count 0 2006.285.19:54:55.94#ibcon#*after write, iclass 23, count 0 2006.285.19:54:55.94#ibcon#*before return 0, iclass 23, count 0 2006.285.19:54:55.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:54:55.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.19:54:55.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.19:54:55.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.19:54:55.94$vck44/vb=5,4 2006.285.19:54:55.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.19:54:55.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.19:54:55.94#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:55.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:54:56.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:54:56.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:54:56.00#ibcon#enter wrdev, iclass 25, count 2 2006.285.19:54:56.00#ibcon#first serial, iclass 25, count 2 2006.285.19:54:56.00#ibcon#enter sib2, iclass 25, count 2 2006.285.19:54:56.00#ibcon#flushed, iclass 25, count 2 2006.285.19:54:56.00#ibcon#about to write, iclass 25, count 2 2006.285.19:54:56.00#ibcon#wrote, iclass 25, count 2 2006.285.19:54:56.00#ibcon#about to read 3, iclass 25, count 2 2006.285.19:54:56.02#ibcon#read 3, iclass 25, count 2 2006.285.19:54:56.02#ibcon#about to read 4, iclass 25, count 2 2006.285.19:54:56.02#ibcon#read 4, iclass 25, count 2 2006.285.19:54:56.02#ibcon#about to read 5, iclass 25, count 2 2006.285.19:54:56.02#ibcon#read 5, iclass 25, count 2 2006.285.19:54:56.02#ibcon#about to read 6, iclass 25, count 2 2006.285.19:54:56.02#ibcon#read 6, iclass 25, count 2 2006.285.19:54:56.02#ibcon#end of sib2, iclass 25, count 2 2006.285.19:54:56.02#ibcon#*mode == 0, iclass 25, count 2 2006.285.19:54:56.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.19:54:56.02#ibcon#[27=AT05-04\r\n] 2006.285.19:54:56.02#ibcon#*before write, iclass 25, count 2 2006.285.19:54:56.02#ibcon#enter sib2, iclass 25, count 2 2006.285.19:54:56.02#ibcon#flushed, iclass 25, count 2 2006.285.19:54:56.02#ibcon#about to write, iclass 25, count 2 2006.285.19:54:56.02#ibcon#wrote, iclass 25, count 2 2006.285.19:54:56.02#ibcon#about to read 3, iclass 25, count 2 2006.285.19:54:56.05#ibcon#read 3, iclass 25, count 2 2006.285.19:54:56.05#ibcon#about to read 4, iclass 25, count 2 2006.285.19:54:56.05#ibcon#read 4, iclass 25, count 2 2006.285.19:54:56.05#ibcon#about to read 5, iclass 25, count 2 2006.285.19:54:56.05#ibcon#read 5, iclass 25, count 2 2006.285.19:54:56.05#ibcon#about to read 6, iclass 25, count 2 2006.285.19:54:56.05#ibcon#read 6, iclass 25, count 2 2006.285.19:54:56.05#ibcon#end of sib2, iclass 25, count 2 2006.285.19:54:56.05#ibcon#*after write, iclass 25, count 2 2006.285.19:54:56.05#ibcon#*before return 0, iclass 25, count 2 2006.285.19:54:56.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:54:56.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.19:54:56.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.19:54:56.05#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:56.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:54:56.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:54:56.31#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:54:56.31#ibcon#enter wrdev, iclass 25, count 0 2006.285.19:54:56.31#ibcon#first serial, iclass 25, count 0 2006.285.19:54:56.31#ibcon#enter sib2, iclass 25, count 0 2006.285.19:54:56.31#ibcon#flushed, iclass 25, count 0 2006.285.19:54:56.31#ibcon#about to write, iclass 25, count 0 2006.285.19:54:56.31#ibcon#wrote, iclass 25, count 0 2006.285.19:54:56.31#ibcon#about to read 3, iclass 25, count 0 2006.285.19:54:56.32#ibcon#read 3, iclass 25, count 0 2006.285.19:54:56.32#ibcon#about to read 4, iclass 25, count 0 2006.285.19:54:56.32#ibcon#read 4, iclass 25, count 0 2006.285.19:54:56.32#ibcon#about to read 5, iclass 25, count 0 2006.285.19:54:56.32#ibcon#read 5, iclass 25, count 0 2006.285.19:54:56.32#ibcon#about to read 6, iclass 25, count 0 2006.285.19:54:56.32#ibcon#read 6, iclass 25, count 0 2006.285.19:54:56.32#ibcon#end of sib2, iclass 25, count 0 2006.285.19:54:56.32#ibcon#*mode == 0, iclass 25, count 0 2006.285.19:54:56.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.19:54:56.32#ibcon#[27=USB\r\n] 2006.285.19:54:56.32#ibcon#*before write, iclass 25, count 0 2006.285.19:54:56.32#ibcon#enter sib2, iclass 25, count 0 2006.285.19:54:56.32#ibcon#flushed, iclass 25, count 0 2006.285.19:54:56.32#ibcon#about to write, iclass 25, count 0 2006.285.19:54:56.32#ibcon#wrote, iclass 25, count 0 2006.285.19:54:56.32#ibcon#about to read 3, iclass 25, count 0 2006.285.19:54:56.35#ibcon#read 3, iclass 25, count 0 2006.285.19:54:56.35#ibcon#about to read 4, iclass 25, count 0 2006.285.19:54:56.35#ibcon#read 4, iclass 25, count 0 2006.285.19:54:56.35#ibcon#about to read 5, iclass 25, count 0 2006.285.19:54:56.35#ibcon#read 5, iclass 25, count 0 2006.285.19:54:56.35#ibcon#about to read 6, iclass 25, count 0 2006.285.19:54:56.35#ibcon#read 6, iclass 25, count 0 2006.285.19:54:56.35#ibcon#end of sib2, iclass 25, count 0 2006.285.19:54:56.35#ibcon#*after write, iclass 25, count 0 2006.285.19:54:56.35#ibcon#*before return 0, iclass 25, count 0 2006.285.19:54:56.35#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:54:56.35#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.19:54:56.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.19:54:56.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.19:54:56.35$vck44/vblo=6,719.99 2006.285.19:54:56.35#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.19:54:56.35#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.19:54:56.35#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:56.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:54:56.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:54:56.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:54:56.35#ibcon#enter wrdev, iclass 27, count 0 2006.285.19:54:56.35#ibcon#first serial, iclass 27, count 0 2006.285.19:54:56.35#ibcon#enter sib2, iclass 27, count 0 2006.285.19:54:56.35#ibcon#flushed, iclass 27, count 0 2006.285.19:54:56.35#ibcon#about to write, iclass 27, count 0 2006.285.19:54:56.35#ibcon#wrote, iclass 27, count 0 2006.285.19:54:56.35#ibcon#about to read 3, iclass 27, count 0 2006.285.19:54:56.37#ibcon#read 3, iclass 27, count 0 2006.285.19:54:56.37#ibcon#about to read 4, iclass 27, count 0 2006.285.19:54:56.37#ibcon#read 4, iclass 27, count 0 2006.285.19:54:56.37#ibcon#about to read 5, iclass 27, count 0 2006.285.19:54:56.37#ibcon#read 5, iclass 27, count 0 2006.285.19:54:56.37#ibcon#about to read 6, iclass 27, count 0 2006.285.19:54:56.37#ibcon#read 6, iclass 27, count 0 2006.285.19:54:56.37#ibcon#end of sib2, iclass 27, count 0 2006.285.19:54:56.37#ibcon#*mode == 0, iclass 27, count 0 2006.285.19:54:56.37#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.19:54:56.37#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.19:54:56.37#ibcon#*before write, iclass 27, count 0 2006.285.19:54:56.37#ibcon#enter sib2, iclass 27, count 0 2006.285.19:54:56.37#ibcon#flushed, iclass 27, count 0 2006.285.19:54:56.37#ibcon#about to write, iclass 27, count 0 2006.285.19:54:56.37#ibcon#wrote, iclass 27, count 0 2006.285.19:54:56.37#ibcon#about to read 3, iclass 27, count 0 2006.285.19:54:56.41#ibcon#read 3, iclass 27, count 0 2006.285.19:54:56.41#ibcon#about to read 4, iclass 27, count 0 2006.285.19:54:56.41#ibcon#read 4, iclass 27, count 0 2006.285.19:54:56.41#ibcon#about to read 5, iclass 27, count 0 2006.285.19:54:56.41#ibcon#read 5, iclass 27, count 0 2006.285.19:54:56.41#ibcon#about to read 6, iclass 27, count 0 2006.285.19:54:56.41#ibcon#read 6, iclass 27, count 0 2006.285.19:54:56.41#ibcon#end of sib2, iclass 27, count 0 2006.285.19:54:56.41#ibcon#*after write, iclass 27, count 0 2006.285.19:54:56.41#ibcon#*before return 0, iclass 27, count 0 2006.285.19:54:56.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:54:56.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.19:54:56.41#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.19:54:56.41#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.19:54:56.41$vck44/vb=6,3 2006.285.19:54:56.41#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.19:54:56.41#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.19:54:56.41#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:56.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:54:56.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:54:56.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:54:56.47#ibcon#enter wrdev, iclass 29, count 2 2006.285.19:54:56.47#ibcon#first serial, iclass 29, count 2 2006.285.19:54:56.47#ibcon#enter sib2, iclass 29, count 2 2006.285.19:54:56.47#ibcon#flushed, iclass 29, count 2 2006.285.19:54:56.47#ibcon#about to write, iclass 29, count 2 2006.285.19:54:56.47#ibcon#wrote, iclass 29, count 2 2006.285.19:54:56.47#ibcon#about to read 3, iclass 29, count 2 2006.285.19:54:56.49#ibcon#read 3, iclass 29, count 2 2006.285.19:54:56.49#ibcon#about to read 4, iclass 29, count 2 2006.285.19:54:56.49#ibcon#read 4, iclass 29, count 2 2006.285.19:54:56.49#ibcon#about to read 5, iclass 29, count 2 2006.285.19:54:56.49#ibcon#read 5, iclass 29, count 2 2006.285.19:54:56.49#ibcon#about to read 6, iclass 29, count 2 2006.285.19:54:56.49#ibcon#read 6, iclass 29, count 2 2006.285.19:54:56.49#ibcon#end of sib2, iclass 29, count 2 2006.285.19:54:56.49#ibcon#*mode == 0, iclass 29, count 2 2006.285.19:54:56.49#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.19:54:56.49#ibcon#[27=AT06-03\r\n] 2006.285.19:54:56.49#ibcon#*before write, iclass 29, count 2 2006.285.19:54:56.49#ibcon#enter sib2, iclass 29, count 2 2006.285.19:54:56.49#ibcon#flushed, iclass 29, count 2 2006.285.19:54:56.49#ibcon#about to write, iclass 29, count 2 2006.285.19:54:56.49#ibcon#wrote, iclass 29, count 2 2006.285.19:54:56.49#ibcon#about to read 3, iclass 29, count 2 2006.285.19:54:56.52#ibcon#read 3, iclass 29, count 2 2006.285.19:54:56.52#ibcon#about to read 4, iclass 29, count 2 2006.285.19:54:56.52#ibcon#read 4, iclass 29, count 2 2006.285.19:54:56.52#ibcon#about to read 5, iclass 29, count 2 2006.285.19:54:56.52#ibcon#read 5, iclass 29, count 2 2006.285.19:54:56.52#ibcon#about to read 6, iclass 29, count 2 2006.285.19:54:56.52#ibcon#read 6, iclass 29, count 2 2006.285.19:54:56.52#ibcon#end of sib2, iclass 29, count 2 2006.285.19:54:56.52#ibcon#*after write, iclass 29, count 2 2006.285.19:54:56.52#ibcon#*before return 0, iclass 29, count 2 2006.285.19:54:56.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:54:56.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.19:54:56.52#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.19:54:56.52#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:56.52#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:54:56.64#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:54:56.64#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:54:56.64#ibcon#enter wrdev, iclass 29, count 0 2006.285.19:54:56.64#ibcon#first serial, iclass 29, count 0 2006.285.19:54:56.64#ibcon#enter sib2, iclass 29, count 0 2006.285.19:54:56.64#ibcon#flushed, iclass 29, count 0 2006.285.19:54:56.64#ibcon#about to write, iclass 29, count 0 2006.285.19:54:56.64#ibcon#wrote, iclass 29, count 0 2006.285.19:54:56.64#ibcon#about to read 3, iclass 29, count 0 2006.285.19:54:56.66#ibcon#read 3, iclass 29, count 0 2006.285.19:54:56.66#ibcon#about to read 4, iclass 29, count 0 2006.285.19:54:56.66#ibcon#read 4, iclass 29, count 0 2006.285.19:54:56.66#ibcon#about to read 5, iclass 29, count 0 2006.285.19:54:56.66#ibcon#read 5, iclass 29, count 0 2006.285.19:54:56.66#ibcon#about to read 6, iclass 29, count 0 2006.285.19:54:56.66#ibcon#read 6, iclass 29, count 0 2006.285.19:54:56.66#ibcon#end of sib2, iclass 29, count 0 2006.285.19:54:56.66#ibcon#*mode == 0, iclass 29, count 0 2006.285.19:54:56.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.19:54:56.66#ibcon#[27=USB\r\n] 2006.285.19:54:56.66#ibcon#*before write, iclass 29, count 0 2006.285.19:54:56.66#ibcon#enter sib2, iclass 29, count 0 2006.285.19:54:56.66#ibcon#flushed, iclass 29, count 0 2006.285.19:54:56.66#ibcon#about to write, iclass 29, count 0 2006.285.19:54:56.66#ibcon#wrote, iclass 29, count 0 2006.285.19:54:56.66#ibcon#about to read 3, iclass 29, count 0 2006.285.19:54:56.69#ibcon#read 3, iclass 29, count 0 2006.285.19:54:56.69#ibcon#about to read 4, iclass 29, count 0 2006.285.19:54:56.69#ibcon#read 4, iclass 29, count 0 2006.285.19:54:56.69#ibcon#about to read 5, iclass 29, count 0 2006.285.19:54:56.69#ibcon#read 5, iclass 29, count 0 2006.285.19:54:56.69#ibcon#about to read 6, iclass 29, count 0 2006.285.19:54:56.69#ibcon#read 6, iclass 29, count 0 2006.285.19:54:56.69#ibcon#end of sib2, iclass 29, count 0 2006.285.19:54:56.69#ibcon#*after write, iclass 29, count 0 2006.285.19:54:56.69#ibcon#*before return 0, iclass 29, count 0 2006.285.19:54:56.69#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:54:56.69#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.19:54:56.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.19:54:56.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.19:54:56.69$vck44/vblo=7,734.99 2006.285.19:54:56.69#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.19:54:56.69#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.19:54:56.69#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:56.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:54:56.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:54:56.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:54:56.69#ibcon#enter wrdev, iclass 31, count 0 2006.285.19:54:56.69#ibcon#first serial, iclass 31, count 0 2006.285.19:54:56.69#ibcon#enter sib2, iclass 31, count 0 2006.285.19:54:56.69#ibcon#flushed, iclass 31, count 0 2006.285.19:54:56.69#ibcon#about to write, iclass 31, count 0 2006.285.19:54:56.69#ibcon#wrote, iclass 31, count 0 2006.285.19:54:56.69#ibcon#about to read 3, iclass 31, count 0 2006.285.19:54:56.71#ibcon#read 3, iclass 31, count 0 2006.285.19:54:56.71#ibcon#about to read 4, iclass 31, count 0 2006.285.19:54:56.71#ibcon#read 4, iclass 31, count 0 2006.285.19:54:56.71#ibcon#about to read 5, iclass 31, count 0 2006.285.19:54:56.71#ibcon#read 5, iclass 31, count 0 2006.285.19:54:56.71#ibcon#about to read 6, iclass 31, count 0 2006.285.19:54:56.71#ibcon#read 6, iclass 31, count 0 2006.285.19:54:56.71#ibcon#end of sib2, iclass 31, count 0 2006.285.19:54:56.71#ibcon#*mode == 0, iclass 31, count 0 2006.285.19:54:56.71#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.19:54:56.71#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.19:54:56.71#ibcon#*before write, iclass 31, count 0 2006.285.19:54:56.71#ibcon#enter sib2, iclass 31, count 0 2006.285.19:54:56.71#ibcon#flushed, iclass 31, count 0 2006.285.19:54:56.71#ibcon#about to write, iclass 31, count 0 2006.285.19:54:56.71#ibcon#wrote, iclass 31, count 0 2006.285.19:54:56.71#ibcon#about to read 3, iclass 31, count 0 2006.285.19:54:56.75#ibcon#read 3, iclass 31, count 0 2006.285.19:54:56.75#ibcon#about to read 4, iclass 31, count 0 2006.285.19:54:56.75#ibcon#read 4, iclass 31, count 0 2006.285.19:54:56.75#ibcon#about to read 5, iclass 31, count 0 2006.285.19:54:56.75#ibcon#read 5, iclass 31, count 0 2006.285.19:54:56.75#ibcon#about to read 6, iclass 31, count 0 2006.285.19:54:56.75#ibcon#read 6, iclass 31, count 0 2006.285.19:54:56.75#ibcon#end of sib2, iclass 31, count 0 2006.285.19:54:56.75#ibcon#*after write, iclass 31, count 0 2006.285.19:54:56.75#ibcon#*before return 0, iclass 31, count 0 2006.285.19:54:56.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:54:56.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.19:54:56.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.19:54:56.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.19:54:56.75$vck44/vb=7,4 2006.285.19:54:56.75#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.19:54:56.75#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.19:54:56.75#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:56.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:54:56.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:54:56.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:54:56.81#ibcon#enter wrdev, iclass 33, count 2 2006.285.19:54:56.81#ibcon#first serial, iclass 33, count 2 2006.285.19:54:56.81#ibcon#enter sib2, iclass 33, count 2 2006.285.19:54:56.81#ibcon#flushed, iclass 33, count 2 2006.285.19:54:56.81#ibcon#about to write, iclass 33, count 2 2006.285.19:54:56.81#ibcon#wrote, iclass 33, count 2 2006.285.19:54:56.81#ibcon#about to read 3, iclass 33, count 2 2006.285.19:54:56.83#ibcon#read 3, iclass 33, count 2 2006.285.19:54:56.83#ibcon#about to read 4, iclass 33, count 2 2006.285.19:54:56.83#ibcon#read 4, iclass 33, count 2 2006.285.19:54:56.83#ibcon#about to read 5, iclass 33, count 2 2006.285.19:54:56.83#ibcon#read 5, iclass 33, count 2 2006.285.19:54:56.83#ibcon#about to read 6, iclass 33, count 2 2006.285.19:54:56.83#ibcon#read 6, iclass 33, count 2 2006.285.19:54:56.83#ibcon#end of sib2, iclass 33, count 2 2006.285.19:54:56.83#ibcon#*mode == 0, iclass 33, count 2 2006.285.19:54:56.83#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.19:54:56.83#ibcon#[27=AT07-04\r\n] 2006.285.19:54:56.83#ibcon#*before write, iclass 33, count 2 2006.285.19:54:56.83#ibcon#enter sib2, iclass 33, count 2 2006.285.19:54:56.83#ibcon#flushed, iclass 33, count 2 2006.285.19:54:56.83#ibcon#about to write, iclass 33, count 2 2006.285.19:54:56.83#ibcon#wrote, iclass 33, count 2 2006.285.19:54:56.83#ibcon#about to read 3, iclass 33, count 2 2006.285.19:54:56.86#ibcon#read 3, iclass 33, count 2 2006.285.19:54:56.86#ibcon#about to read 4, iclass 33, count 2 2006.285.19:54:56.86#ibcon#read 4, iclass 33, count 2 2006.285.19:54:56.86#ibcon#about to read 5, iclass 33, count 2 2006.285.19:54:56.86#ibcon#read 5, iclass 33, count 2 2006.285.19:54:56.86#ibcon#about to read 6, iclass 33, count 2 2006.285.19:54:56.86#ibcon#read 6, iclass 33, count 2 2006.285.19:54:56.86#ibcon#end of sib2, iclass 33, count 2 2006.285.19:54:56.86#ibcon#*after write, iclass 33, count 2 2006.285.19:54:56.86#ibcon#*before return 0, iclass 33, count 2 2006.285.19:54:56.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:54:56.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.19:54:56.86#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.19:54:56.86#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:56.86#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:54:56.98#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:54:56.98#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:54:56.98#ibcon#enter wrdev, iclass 33, count 0 2006.285.19:54:56.98#ibcon#first serial, iclass 33, count 0 2006.285.19:54:56.98#ibcon#enter sib2, iclass 33, count 0 2006.285.19:54:56.98#ibcon#flushed, iclass 33, count 0 2006.285.19:54:56.98#ibcon#about to write, iclass 33, count 0 2006.285.19:54:56.98#ibcon#wrote, iclass 33, count 0 2006.285.19:54:56.98#ibcon#about to read 3, iclass 33, count 0 2006.285.19:54:57.00#ibcon#read 3, iclass 33, count 0 2006.285.19:54:57.00#ibcon#about to read 4, iclass 33, count 0 2006.285.19:54:57.00#ibcon#read 4, iclass 33, count 0 2006.285.19:54:57.00#ibcon#about to read 5, iclass 33, count 0 2006.285.19:54:57.00#ibcon#read 5, iclass 33, count 0 2006.285.19:54:57.00#ibcon#about to read 6, iclass 33, count 0 2006.285.19:54:57.00#ibcon#read 6, iclass 33, count 0 2006.285.19:54:57.00#ibcon#end of sib2, iclass 33, count 0 2006.285.19:54:57.00#ibcon#*mode == 0, iclass 33, count 0 2006.285.19:54:57.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.19:54:57.00#ibcon#[27=USB\r\n] 2006.285.19:54:57.00#ibcon#*before write, iclass 33, count 0 2006.285.19:54:57.00#ibcon#enter sib2, iclass 33, count 0 2006.285.19:54:57.00#ibcon#flushed, iclass 33, count 0 2006.285.19:54:57.00#ibcon#about to write, iclass 33, count 0 2006.285.19:54:57.00#ibcon#wrote, iclass 33, count 0 2006.285.19:54:57.00#ibcon#about to read 3, iclass 33, count 0 2006.285.19:54:57.03#ibcon#read 3, iclass 33, count 0 2006.285.19:54:57.03#ibcon#about to read 4, iclass 33, count 0 2006.285.19:54:57.03#ibcon#read 4, iclass 33, count 0 2006.285.19:54:57.03#ibcon#about to read 5, iclass 33, count 0 2006.285.19:54:57.03#ibcon#read 5, iclass 33, count 0 2006.285.19:54:57.03#ibcon#about to read 6, iclass 33, count 0 2006.285.19:54:57.03#ibcon#read 6, iclass 33, count 0 2006.285.19:54:57.03#ibcon#end of sib2, iclass 33, count 0 2006.285.19:54:57.03#ibcon#*after write, iclass 33, count 0 2006.285.19:54:57.03#ibcon#*before return 0, iclass 33, count 0 2006.285.19:54:57.03#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:54:57.03#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.19:54:57.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.19:54:57.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.19:54:57.03$vck44/vblo=8,744.99 2006.285.19:54:57.03#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.19:54:57.03#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.19:54:57.03#ibcon#ireg 17 cls_cnt 0 2006.285.19:54:57.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:54:57.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:54:57.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:54:57.03#ibcon#enter wrdev, iclass 35, count 0 2006.285.19:54:57.03#ibcon#first serial, iclass 35, count 0 2006.285.19:54:57.03#ibcon#enter sib2, iclass 35, count 0 2006.285.19:54:57.03#ibcon#flushed, iclass 35, count 0 2006.285.19:54:57.03#ibcon#about to write, iclass 35, count 0 2006.285.19:54:57.03#ibcon#wrote, iclass 35, count 0 2006.285.19:54:57.03#ibcon#about to read 3, iclass 35, count 0 2006.285.19:54:57.05#ibcon#read 3, iclass 35, count 0 2006.285.19:54:57.05#ibcon#about to read 4, iclass 35, count 0 2006.285.19:54:57.05#ibcon#read 4, iclass 35, count 0 2006.285.19:54:57.05#ibcon#about to read 5, iclass 35, count 0 2006.285.19:54:57.05#ibcon#read 5, iclass 35, count 0 2006.285.19:54:57.05#ibcon#about to read 6, iclass 35, count 0 2006.285.19:54:57.05#ibcon#read 6, iclass 35, count 0 2006.285.19:54:57.05#ibcon#end of sib2, iclass 35, count 0 2006.285.19:54:57.05#ibcon#*mode == 0, iclass 35, count 0 2006.285.19:54:57.05#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.19:54:57.05#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.19:54:57.05#ibcon#*before write, iclass 35, count 0 2006.285.19:54:57.05#ibcon#enter sib2, iclass 35, count 0 2006.285.19:54:57.05#ibcon#flushed, iclass 35, count 0 2006.285.19:54:57.05#ibcon#about to write, iclass 35, count 0 2006.285.19:54:57.05#ibcon#wrote, iclass 35, count 0 2006.285.19:54:57.05#ibcon#about to read 3, iclass 35, count 0 2006.285.19:54:57.09#ibcon#read 3, iclass 35, count 0 2006.285.19:54:57.09#ibcon#about to read 4, iclass 35, count 0 2006.285.19:54:57.09#ibcon#read 4, iclass 35, count 0 2006.285.19:54:57.09#ibcon#about to read 5, iclass 35, count 0 2006.285.19:54:57.09#ibcon#read 5, iclass 35, count 0 2006.285.19:54:57.09#ibcon#about to read 6, iclass 35, count 0 2006.285.19:54:57.09#ibcon#read 6, iclass 35, count 0 2006.285.19:54:57.09#ibcon#end of sib2, iclass 35, count 0 2006.285.19:54:57.09#ibcon#*after write, iclass 35, count 0 2006.285.19:54:57.09#ibcon#*before return 0, iclass 35, count 0 2006.285.19:54:57.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:54:57.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.19:54:57.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.19:54:57.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.19:54:57.09$vck44/vb=8,4 2006.285.19:54:57.17#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.19:54:57.17#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.19:54:57.17#ibcon#ireg 11 cls_cnt 2 2006.285.19:54:57.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:54:57.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:54:57.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:54:57.17#ibcon#enter wrdev, iclass 37, count 2 2006.285.19:54:57.17#ibcon#first serial, iclass 37, count 2 2006.285.19:54:57.17#ibcon#enter sib2, iclass 37, count 2 2006.285.19:54:57.17#ibcon#flushed, iclass 37, count 2 2006.285.19:54:57.17#ibcon#about to write, iclass 37, count 2 2006.285.19:54:57.17#ibcon#wrote, iclass 37, count 2 2006.285.19:54:57.17#ibcon#about to read 3, iclass 37, count 2 2006.285.19:54:57.19#ibcon#read 3, iclass 37, count 2 2006.285.19:54:57.19#ibcon#about to read 4, iclass 37, count 2 2006.285.19:54:57.19#ibcon#read 4, iclass 37, count 2 2006.285.19:54:57.19#ibcon#about to read 5, iclass 37, count 2 2006.285.19:54:57.19#ibcon#read 5, iclass 37, count 2 2006.285.19:54:57.19#ibcon#about to read 6, iclass 37, count 2 2006.285.19:54:57.19#ibcon#read 6, iclass 37, count 2 2006.285.19:54:57.19#ibcon#end of sib2, iclass 37, count 2 2006.285.19:54:57.19#ibcon#*mode == 0, iclass 37, count 2 2006.285.19:54:57.19#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.19:54:57.19#ibcon#[27=AT08-04\r\n] 2006.285.19:54:57.19#ibcon#*before write, iclass 37, count 2 2006.285.19:54:57.19#ibcon#enter sib2, iclass 37, count 2 2006.285.19:54:57.19#ibcon#flushed, iclass 37, count 2 2006.285.19:54:57.19#ibcon#about to write, iclass 37, count 2 2006.285.19:54:57.19#ibcon#wrote, iclass 37, count 2 2006.285.19:54:57.19#ibcon#about to read 3, iclass 37, count 2 2006.285.19:54:57.22#ibcon#read 3, iclass 37, count 2 2006.285.19:54:57.22#ibcon#about to read 4, iclass 37, count 2 2006.285.19:54:57.22#ibcon#read 4, iclass 37, count 2 2006.285.19:54:57.22#ibcon#about to read 5, iclass 37, count 2 2006.285.19:54:57.22#ibcon#read 5, iclass 37, count 2 2006.285.19:54:57.22#ibcon#about to read 6, iclass 37, count 2 2006.285.19:54:57.22#ibcon#read 6, iclass 37, count 2 2006.285.19:54:57.22#ibcon#end of sib2, iclass 37, count 2 2006.285.19:54:57.22#ibcon#*after write, iclass 37, count 2 2006.285.19:54:57.22#ibcon#*before return 0, iclass 37, count 2 2006.285.19:54:57.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:54:57.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.19:54:57.22#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.19:54:57.22#ibcon#ireg 7 cls_cnt 0 2006.285.19:54:57.22#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:54:57.34#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:54:57.34#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:54:57.34#ibcon#enter wrdev, iclass 37, count 0 2006.285.19:54:57.34#ibcon#first serial, iclass 37, count 0 2006.285.19:54:57.34#ibcon#enter sib2, iclass 37, count 0 2006.285.19:54:57.34#ibcon#flushed, iclass 37, count 0 2006.285.19:54:57.34#ibcon#about to write, iclass 37, count 0 2006.285.19:54:57.34#ibcon#wrote, iclass 37, count 0 2006.285.19:54:57.34#ibcon#about to read 3, iclass 37, count 0 2006.285.19:54:57.36#ibcon#read 3, iclass 37, count 0 2006.285.19:54:57.36#ibcon#about to read 4, iclass 37, count 0 2006.285.19:54:57.36#ibcon#read 4, iclass 37, count 0 2006.285.19:54:57.36#ibcon#about to read 5, iclass 37, count 0 2006.285.19:54:57.36#ibcon#read 5, iclass 37, count 0 2006.285.19:54:57.36#ibcon#about to read 6, iclass 37, count 0 2006.285.19:54:57.36#ibcon#read 6, iclass 37, count 0 2006.285.19:54:57.36#ibcon#end of sib2, iclass 37, count 0 2006.285.19:54:57.36#ibcon#*mode == 0, iclass 37, count 0 2006.285.19:54:57.36#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.19:54:57.36#ibcon#[27=USB\r\n] 2006.285.19:54:57.36#ibcon#*before write, iclass 37, count 0 2006.285.19:54:57.36#ibcon#enter sib2, iclass 37, count 0 2006.285.19:54:57.36#ibcon#flushed, iclass 37, count 0 2006.285.19:54:57.36#ibcon#about to write, iclass 37, count 0 2006.285.19:54:57.36#ibcon#wrote, iclass 37, count 0 2006.285.19:54:57.36#ibcon#about to read 3, iclass 37, count 0 2006.285.19:54:57.39#ibcon#read 3, iclass 37, count 0 2006.285.19:54:57.39#ibcon#about to read 4, iclass 37, count 0 2006.285.19:54:57.39#ibcon#read 4, iclass 37, count 0 2006.285.19:54:57.39#ibcon#about to read 5, iclass 37, count 0 2006.285.19:54:57.39#ibcon#read 5, iclass 37, count 0 2006.285.19:54:57.39#ibcon#about to read 6, iclass 37, count 0 2006.285.19:54:57.39#ibcon#read 6, iclass 37, count 0 2006.285.19:54:57.39#ibcon#end of sib2, iclass 37, count 0 2006.285.19:54:57.39#ibcon#*after write, iclass 37, count 0 2006.285.19:54:57.39#ibcon#*before return 0, iclass 37, count 0 2006.285.19:54:57.39#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:54:57.39#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.19:54:57.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.19:54:57.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.19:54:57.39$vck44/vabw=wide 2006.285.19:54:57.39#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.19:54:57.39#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.19:54:57.39#ibcon#ireg 8 cls_cnt 0 2006.285.19:54:57.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:54:57.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:54:57.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:54:57.39#ibcon#enter wrdev, iclass 39, count 0 2006.285.19:54:57.39#ibcon#first serial, iclass 39, count 0 2006.285.19:54:57.39#ibcon#enter sib2, iclass 39, count 0 2006.285.19:54:57.39#ibcon#flushed, iclass 39, count 0 2006.285.19:54:57.39#ibcon#about to write, iclass 39, count 0 2006.285.19:54:57.39#ibcon#wrote, iclass 39, count 0 2006.285.19:54:57.39#ibcon#about to read 3, iclass 39, count 0 2006.285.19:54:57.41#ibcon#read 3, iclass 39, count 0 2006.285.19:54:57.41#ibcon#about to read 4, iclass 39, count 0 2006.285.19:54:57.41#ibcon#read 4, iclass 39, count 0 2006.285.19:54:57.41#ibcon#about to read 5, iclass 39, count 0 2006.285.19:54:57.41#ibcon#read 5, iclass 39, count 0 2006.285.19:54:57.41#ibcon#about to read 6, iclass 39, count 0 2006.285.19:54:57.41#ibcon#read 6, iclass 39, count 0 2006.285.19:54:57.41#ibcon#end of sib2, iclass 39, count 0 2006.285.19:54:57.41#ibcon#*mode == 0, iclass 39, count 0 2006.285.19:54:57.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.19:54:57.41#ibcon#[25=BW32\r\n] 2006.285.19:54:57.41#ibcon#*before write, iclass 39, count 0 2006.285.19:54:57.41#ibcon#enter sib2, iclass 39, count 0 2006.285.19:54:57.41#ibcon#flushed, iclass 39, count 0 2006.285.19:54:57.41#ibcon#about to write, iclass 39, count 0 2006.285.19:54:57.41#ibcon#wrote, iclass 39, count 0 2006.285.19:54:57.41#ibcon#about to read 3, iclass 39, count 0 2006.285.19:54:57.44#ibcon#read 3, iclass 39, count 0 2006.285.19:54:57.44#ibcon#about to read 4, iclass 39, count 0 2006.285.19:54:57.44#ibcon#read 4, iclass 39, count 0 2006.285.19:54:57.44#ibcon#about to read 5, iclass 39, count 0 2006.285.19:54:57.44#ibcon#read 5, iclass 39, count 0 2006.285.19:54:57.44#ibcon#about to read 6, iclass 39, count 0 2006.285.19:54:57.44#ibcon#read 6, iclass 39, count 0 2006.285.19:54:57.44#ibcon#end of sib2, iclass 39, count 0 2006.285.19:54:57.44#ibcon#*after write, iclass 39, count 0 2006.285.19:54:57.44#ibcon#*before return 0, iclass 39, count 0 2006.285.19:54:57.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:54:57.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.19:54:57.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.19:54:57.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.19:54:57.44$vck44/vbbw=wide 2006.285.19:54:57.44#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.19:54:57.44#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.19:54:57.44#ibcon#ireg 8 cls_cnt 0 2006.285.19:54:57.44#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:54:57.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:54:57.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:54:57.51#ibcon#enter wrdev, iclass 3, count 0 2006.285.19:54:57.51#ibcon#first serial, iclass 3, count 0 2006.285.19:54:57.51#ibcon#enter sib2, iclass 3, count 0 2006.285.19:54:57.51#ibcon#flushed, iclass 3, count 0 2006.285.19:54:57.51#ibcon#about to write, iclass 3, count 0 2006.285.19:54:57.51#ibcon#wrote, iclass 3, count 0 2006.285.19:54:57.51#ibcon#about to read 3, iclass 3, count 0 2006.285.19:54:57.53#ibcon#read 3, iclass 3, count 0 2006.285.19:54:57.53#ibcon#about to read 4, iclass 3, count 0 2006.285.19:54:57.53#ibcon#read 4, iclass 3, count 0 2006.285.19:54:57.53#ibcon#about to read 5, iclass 3, count 0 2006.285.19:54:57.53#ibcon#read 5, iclass 3, count 0 2006.285.19:54:57.53#ibcon#about to read 6, iclass 3, count 0 2006.285.19:54:57.53#ibcon#read 6, iclass 3, count 0 2006.285.19:54:57.53#ibcon#end of sib2, iclass 3, count 0 2006.285.19:54:57.53#ibcon#*mode == 0, iclass 3, count 0 2006.285.19:54:57.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.19:54:57.53#ibcon#[27=BW32\r\n] 2006.285.19:54:57.53#ibcon#*before write, iclass 3, count 0 2006.285.19:54:57.53#ibcon#enter sib2, iclass 3, count 0 2006.285.19:54:57.53#ibcon#flushed, iclass 3, count 0 2006.285.19:54:57.53#ibcon#about to write, iclass 3, count 0 2006.285.19:54:57.53#ibcon#wrote, iclass 3, count 0 2006.285.19:54:57.53#ibcon#about to read 3, iclass 3, count 0 2006.285.19:54:57.56#ibcon#read 3, iclass 3, count 0 2006.285.19:54:57.56#ibcon#about to read 4, iclass 3, count 0 2006.285.19:54:57.56#ibcon#read 4, iclass 3, count 0 2006.285.19:54:57.56#ibcon#about to read 5, iclass 3, count 0 2006.285.19:54:57.56#ibcon#read 5, iclass 3, count 0 2006.285.19:54:57.56#ibcon#about to read 6, iclass 3, count 0 2006.285.19:54:57.56#ibcon#read 6, iclass 3, count 0 2006.285.19:54:57.56#ibcon#end of sib2, iclass 3, count 0 2006.285.19:54:57.56#ibcon#*after write, iclass 3, count 0 2006.285.19:54:57.56#ibcon#*before return 0, iclass 3, count 0 2006.285.19:54:57.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:54:57.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.19:54:57.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.19:54:57.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.19:54:57.56$setupk4/ifdk4 2006.285.19:54:57.56$ifdk4/lo= 2006.285.19:54:57.56$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.19:54:57.56$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.19:54:57.56$ifdk4/patch= 2006.285.19:54:57.56$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.19:54:57.56$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.19:54:57.56$setupk4/!*+20s 2006.285.19:55:03.28#abcon#<5=/14 0.5 1.2 14.631001015.2\r\n> 2006.285.19:55:03.30#abcon#{5=INTERFACE CLEAR} 2006.285.19:55:03.36#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:55:11.14#trakl#Source acquired 2006.285.19:55:11.24$setupk4/"tpicd 2006.285.19:55:11.24$setupk4/echo=off 2006.285.19:55:11.24$setupk4/xlog=off 2006.285.19:55:11.24:!2006.285.19:56:40 2006.285.19:55:13.14#flagr#flagr/antenna,acquired 2006.285.19:56:40.00:preob 2006.285.19:56:41.14/onsource/TRACKING 2006.285.19:56:41.14:!2006.285.19:56:50 2006.285.19:56:50.00:"tape 2006.285.19:56:50.00:"st=record 2006.285.19:56:50.00:data_valid=on 2006.285.19:56:50.00:midob 2006.285.19:56:50.14/onsource/TRACKING 2006.285.19:56:50.14/wx/14.60,1015.2,100 2006.285.19:56:50.35/cable/+6.5073E-03 2006.285.19:56:51.44/va/01,07,usb,yes,32,35 2006.285.19:56:51.44/va/02,06,usb,yes,32,32 2006.285.19:56:51.44/va/03,07,usb,yes,32,33 2006.285.19:56:51.44/va/04,06,usb,yes,33,34 2006.285.19:56:51.44/va/05,03,usb,yes,33,33 2006.285.19:56:51.44/va/06,04,usb,yes,29,29 2006.285.19:56:51.44/va/07,04,usb,yes,30,30 2006.285.19:56:51.44/va/08,03,usb,yes,31,37 2006.285.19:56:51.67/valo/01,524.99,yes,locked 2006.285.19:56:51.67/valo/02,534.99,yes,locked 2006.285.19:56:51.67/valo/03,564.99,yes,locked 2006.285.19:56:51.67/valo/04,624.99,yes,locked 2006.285.19:56:51.67/valo/05,734.99,yes,locked 2006.285.19:56:51.67/valo/06,814.99,yes,locked 2006.285.19:56:51.67/valo/07,864.99,yes,locked 2006.285.19:56:51.67/valo/08,884.99,yes,locked 2006.285.19:56:52.76/vb/01,04,usb,yes,30,28 2006.285.19:56:52.76/vb/02,05,usb,yes,28,28 2006.285.19:56:52.76/vb/03,04,usb,yes,29,32 2006.285.19:56:52.76/vb/04,05,usb,yes,29,28 2006.285.19:56:52.76/vb/05,04,usb,yes,26,28 2006.285.19:56:52.76/vb/06,03,usb,yes,37,33 2006.285.19:56:52.76/vb/07,04,usb,yes,30,30 2006.285.19:56:52.76/vb/08,04,usb,yes,27,30 2006.285.19:56:53.00/vblo/01,629.99,yes,locked 2006.285.19:56:53.00/vblo/02,634.99,yes,locked 2006.285.19:56:53.00/vblo/03,649.99,yes,locked 2006.285.19:56:53.00/vblo/04,679.99,yes,locked 2006.285.19:56:53.00/vblo/05,709.99,yes,locked 2006.285.19:56:53.00/vblo/06,719.99,yes,locked 2006.285.19:56:53.00/vblo/07,734.99,yes,locked 2006.285.19:56:53.00/vblo/08,744.99,yes,locked 2006.285.19:56:53.15/vabw/8 2006.285.19:56:53.30/vbbw/8 2006.285.19:56:53.39/xfe/off,on,12.0 2006.285.19:56:53.77/ifatt/23,28,28,28 2006.285.19:56:54.07/fmout-gps/S +2.74E-07 2006.285.19:56:54.09:!2006.285.19:58:30 2006.285.19:58:30.01:data_valid=off 2006.285.19:58:30.01:"et 2006.285.19:58:30.01:!+3s 2006.285.19:58:33.02:"tape 2006.285.19:58:33.02:postob 2006.285.19:58:33.15/cable/+6.5090E-03 2006.285.19:58:33.15/wx/14.57,1015.2,100 2006.285.19:58:34.08/fmout-gps/S +2.73E-07 2006.285.19:58:34.08:scan_name=285-2001,jd0610,50 2006.285.19:58:34.08:source=0552+398,055530.81,394849.2,2000.0,cw 2006.285.19:58:35.14#flagr#flagr/antenna,new-source 2006.285.19:58:35.14:checkk5 2006.285.19:58:35.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.19:58:35.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.19:58:36.38/chk_autoobs//k5ts3/ autoobs is running! 2006.285.19:58:36.81/chk_autoobs//k5ts4/ autoobs is running! 2006.285.19:58:37.27/chk_obsdata//k5ts1/T2851956??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.19:58:37.68/chk_obsdata//k5ts2/T2851956??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.19:58:38.03/chk_obsdata//k5ts3/T2851956??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.19:58:38.83/chk_obsdata//k5ts4/T2851956??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.19:58:39.66/k5log//k5ts1_log_newline 2006.285.19:58:40.74/k5log//k5ts2_log_newline 2006.285.19:58:41.79/k5log//k5ts3_log_newline 2006.285.19:58:42.67/k5log//k5ts4_log_newline 2006.285.19:58:42.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.19:58:42.69:setupk4=1 2006.285.19:58:42.69$setupk4/echo=on 2006.285.19:58:42.69$setupk4/pcalon 2006.285.19:58:42.69$pcalon/"no phase cal control is implemented here 2006.285.19:58:42.69$setupk4/"tpicd=stop 2006.285.19:58:42.69$setupk4/"rec=synch_on 2006.285.19:58:42.69$setupk4/"rec_mode=128 2006.285.19:58:42.69$setupk4/!* 2006.285.19:58:42.69$setupk4/recpk4 2006.285.19:58:42.69$recpk4/recpatch= 2006.285.19:58:42.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.19:58:42.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.19:58:42.69$setupk4/vck44 2006.285.19:58:42.69$vck44/valo=1,524.99 2006.285.19:58:42.69#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.19:58:42.69#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.19:58:42.69#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:42.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:58:42.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:58:42.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:58:42.69#ibcon#enter wrdev, iclass 26, count 0 2006.285.19:58:42.69#ibcon#first serial, iclass 26, count 0 2006.285.19:58:42.69#ibcon#enter sib2, iclass 26, count 0 2006.285.19:58:42.69#ibcon#flushed, iclass 26, count 0 2006.285.19:58:42.69#ibcon#about to write, iclass 26, count 0 2006.285.19:58:42.69#ibcon#wrote, iclass 26, count 0 2006.285.19:58:42.69#ibcon#about to read 3, iclass 26, count 0 2006.285.19:58:42.71#ibcon#read 3, iclass 26, count 0 2006.285.19:58:42.71#ibcon#about to read 4, iclass 26, count 0 2006.285.19:58:42.71#ibcon#read 4, iclass 26, count 0 2006.285.19:58:42.71#ibcon#about to read 5, iclass 26, count 0 2006.285.19:58:42.71#ibcon#read 5, iclass 26, count 0 2006.285.19:58:42.71#ibcon#about to read 6, iclass 26, count 0 2006.285.19:58:42.71#ibcon#read 6, iclass 26, count 0 2006.285.19:58:42.71#ibcon#end of sib2, iclass 26, count 0 2006.285.19:58:42.71#ibcon#*mode == 0, iclass 26, count 0 2006.285.19:58:42.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.19:58:42.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.19:58:42.71#ibcon#*before write, iclass 26, count 0 2006.285.19:58:42.71#ibcon#enter sib2, iclass 26, count 0 2006.285.19:58:42.71#ibcon#flushed, iclass 26, count 0 2006.285.19:58:42.71#ibcon#about to write, iclass 26, count 0 2006.285.19:58:42.71#ibcon#wrote, iclass 26, count 0 2006.285.19:58:42.71#ibcon#about to read 3, iclass 26, count 0 2006.285.19:58:42.76#ibcon#read 3, iclass 26, count 0 2006.285.19:58:42.76#ibcon#about to read 4, iclass 26, count 0 2006.285.19:58:42.76#ibcon#read 4, iclass 26, count 0 2006.285.19:58:42.76#ibcon#about to read 5, iclass 26, count 0 2006.285.19:58:42.76#ibcon#read 5, iclass 26, count 0 2006.285.19:58:42.76#ibcon#about to read 6, iclass 26, count 0 2006.285.19:58:42.76#ibcon#read 6, iclass 26, count 0 2006.285.19:58:42.76#ibcon#end of sib2, iclass 26, count 0 2006.285.19:58:42.76#ibcon#*after write, iclass 26, count 0 2006.285.19:58:42.76#ibcon#*before return 0, iclass 26, count 0 2006.285.19:58:42.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:58:42.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:58:42.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.19:58:42.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.19:58:42.76$vck44/va=1,7 2006.285.19:58:42.76#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.19:58:42.76#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.19:58:42.76#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:42.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:58:42.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:58:42.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:58:42.76#ibcon#enter wrdev, iclass 28, count 2 2006.285.19:58:42.76#ibcon#first serial, iclass 28, count 2 2006.285.19:58:42.76#ibcon#enter sib2, iclass 28, count 2 2006.285.19:58:42.76#ibcon#flushed, iclass 28, count 2 2006.285.19:58:42.76#ibcon#about to write, iclass 28, count 2 2006.285.19:58:42.76#ibcon#wrote, iclass 28, count 2 2006.285.19:58:42.76#ibcon#about to read 3, iclass 28, count 2 2006.285.19:58:42.78#ibcon#read 3, iclass 28, count 2 2006.285.19:58:42.78#ibcon#about to read 4, iclass 28, count 2 2006.285.19:58:42.78#ibcon#read 4, iclass 28, count 2 2006.285.19:58:42.78#ibcon#about to read 5, iclass 28, count 2 2006.285.19:58:42.78#ibcon#read 5, iclass 28, count 2 2006.285.19:58:42.78#ibcon#about to read 6, iclass 28, count 2 2006.285.19:58:42.78#ibcon#read 6, iclass 28, count 2 2006.285.19:58:42.78#ibcon#end of sib2, iclass 28, count 2 2006.285.19:58:42.78#ibcon#*mode == 0, iclass 28, count 2 2006.285.19:58:42.78#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.19:58:42.78#ibcon#[25=AT01-07\r\n] 2006.285.19:58:42.78#ibcon#*before write, iclass 28, count 2 2006.285.19:58:42.78#ibcon#enter sib2, iclass 28, count 2 2006.285.19:58:42.78#ibcon#flushed, iclass 28, count 2 2006.285.19:58:42.78#ibcon#about to write, iclass 28, count 2 2006.285.19:58:42.78#ibcon#wrote, iclass 28, count 2 2006.285.19:58:42.78#ibcon#about to read 3, iclass 28, count 2 2006.285.19:58:42.81#ibcon#read 3, iclass 28, count 2 2006.285.19:58:42.81#ibcon#about to read 4, iclass 28, count 2 2006.285.19:58:42.81#ibcon#read 4, iclass 28, count 2 2006.285.19:58:42.81#ibcon#about to read 5, iclass 28, count 2 2006.285.19:58:42.81#ibcon#read 5, iclass 28, count 2 2006.285.19:58:42.81#ibcon#about to read 6, iclass 28, count 2 2006.285.19:58:42.81#ibcon#read 6, iclass 28, count 2 2006.285.19:58:42.81#ibcon#end of sib2, iclass 28, count 2 2006.285.19:58:42.81#ibcon#*after write, iclass 28, count 2 2006.285.19:58:42.81#ibcon#*before return 0, iclass 28, count 2 2006.285.19:58:42.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:58:42.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:58:42.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.19:58:42.81#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:42.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:58:42.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:58:42.93#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:58:42.93#ibcon#enter wrdev, iclass 28, count 0 2006.285.19:58:42.93#ibcon#first serial, iclass 28, count 0 2006.285.19:58:42.93#ibcon#enter sib2, iclass 28, count 0 2006.285.19:58:42.93#ibcon#flushed, iclass 28, count 0 2006.285.19:58:42.93#ibcon#about to write, iclass 28, count 0 2006.285.19:58:42.93#ibcon#wrote, iclass 28, count 0 2006.285.19:58:42.93#ibcon#about to read 3, iclass 28, count 0 2006.285.19:58:42.95#ibcon#read 3, iclass 28, count 0 2006.285.19:58:42.95#ibcon#about to read 4, iclass 28, count 0 2006.285.19:58:42.95#ibcon#read 4, iclass 28, count 0 2006.285.19:58:42.95#ibcon#about to read 5, iclass 28, count 0 2006.285.19:58:42.95#ibcon#read 5, iclass 28, count 0 2006.285.19:58:42.95#ibcon#about to read 6, iclass 28, count 0 2006.285.19:58:42.95#ibcon#read 6, iclass 28, count 0 2006.285.19:58:42.95#ibcon#end of sib2, iclass 28, count 0 2006.285.19:58:42.95#ibcon#*mode == 0, iclass 28, count 0 2006.285.19:58:42.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.19:58:42.95#ibcon#[25=USB\r\n] 2006.285.19:58:42.95#ibcon#*before write, iclass 28, count 0 2006.285.19:58:42.95#ibcon#enter sib2, iclass 28, count 0 2006.285.19:58:42.95#ibcon#flushed, iclass 28, count 0 2006.285.19:58:42.95#ibcon#about to write, iclass 28, count 0 2006.285.19:58:42.95#ibcon#wrote, iclass 28, count 0 2006.285.19:58:42.95#ibcon#about to read 3, iclass 28, count 0 2006.285.19:58:42.98#ibcon#read 3, iclass 28, count 0 2006.285.19:58:42.98#ibcon#about to read 4, iclass 28, count 0 2006.285.19:58:42.98#ibcon#read 4, iclass 28, count 0 2006.285.19:58:42.98#ibcon#about to read 5, iclass 28, count 0 2006.285.19:58:42.98#ibcon#read 5, iclass 28, count 0 2006.285.19:58:42.98#ibcon#about to read 6, iclass 28, count 0 2006.285.19:58:42.98#ibcon#read 6, iclass 28, count 0 2006.285.19:58:42.98#ibcon#end of sib2, iclass 28, count 0 2006.285.19:58:42.98#ibcon#*after write, iclass 28, count 0 2006.285.19:58:42.98#ibcon#*before return 0, iclass 28, count 0 2006.285.19:58:42.98#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:58:42.98#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:58:42.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.19:58:42.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.19:58:42.98$vck44/valo=2,534.99 2006.285.19:58:42.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.19:58:42.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.19:58:42.98#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:42.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:58:42.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:58:42.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:58:42.98#ibcon#enter wrdev, iclass 30, count 0 2006.285.19:58:42.98#ibcon#first serial, iclass 30, count 0 2006.285.19:58:42.98#ibcon#enter sib2, iclass 30, count 0 2006.285.19:58:42.98#ibcon#flushed, iclass 30, count 0 2006.285.19:58:42.98#ibcon#about to write, iclass 30, count 0 2006.285.19:58:42.98#ibcon#wrote, iclass 30, count 0 2006.285.19:58:42.98#ibcon#about to read 3, iclass 30, count 0 2006.285.19:58:43.00#ibcon#read 3, iclass 30, count 0 2006.285.19:58:43.00#ibcon#about to read 4, iclass 30, count 0 2006.285.19:58:43.00#ibcon#read 4, iclass 30, count 0 2006.285.19:58:43.00#ibcon#about to read 5, iclass 30, count 0 2006.285.19:58:43.00#ibcon#read 5, iclass 30, count 0 2006.285.19:58:43.00#ibcon#about to read 6, iclass 30, count 0 2006.285.19:58:43.00#ibcon#read 6, iclass 30, count 0 2006.285.19:58:43.00#ibcon#end of sib2, iclass 30, count 0 2006.285.19:58:43.00#ibcon#*mode == 0, iclass 30, count 0 2006.285.19:58:43.00#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.19:58:43.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.19:58:43.00#ibcon#*before write, iclass 30, count 0 2006.285.19:58:43.00#ibcon#enter sib2, iclass 30, count 0 2006.285.19:58:43.00#ibcon#flushed, iclass 30, count 0 2006.285.19:58:43.00#ibcon#about to write, iclass 30, count 0 2006.285.19:58:43.00#ibcon#wrote, iclass 30, count 0 2006.285.19:58:43.00#ibcon#about to read 3, iclass 30, count 0 2006.285.19:58:43.04#ibcon#read 3, iclass 30, count 0 2006.285.19:58:43.04#ibcon#about to read 4, iclass 30, count 0 2006.285.19:58:43.04#ibcon#read 4, iclass 30, count 0 2006.285.19:58:43.04#ibcon#about to read 5, iclass 30, count 0 2006.285.19:58:43.04#ibcon#read 5, iclass 30, count 0 2006.285.19:58:43.04#ibcon#about to read 6, iclass 30, count 0 2006.285.19:58:43.04#ibcon#read 6, iclass 30, count 0 2006.285.19:58:43.04#ibcon#end of sib2, iclass 30, count 0 2006.285.19:58:43.04#ibcon#*after write, iclass 30, count 0 2006.285.19:58:43.04#ibcon#*before return 0, iclass 30, count 0 2006.285.19:58:43.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:58:43.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:58:43.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.19:58:43.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.19:58:43.04$vck44/va=2,6 2006.285.19:58:43.04#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.19:58:43.04#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.19:58:43.04#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:43.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:58:43.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:58:43.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:58:43.10#ibcon#enter wrdev, iclass 32, count 2 2006.285.19:58:43.10#ibcon#first serial, iclass 32, count 2 2006.285.19:58:43.10#ibcon#enter sib2, iclass 32, count 2 2006.285.19:58:43.10#ibcon#flushed, iclass 32, count 2 2006.285.19:58:43.10#ibcon#about to write, iclass 32, count 2 2006.285.19:58:43.10#ibcon#wrote, iclass 32, count 2 2006.285.19:58:43.10#ibcon#about to read 3, iclass 32, count 2 2006.285.19:58:43.12#ibcon#read 3, iclass 32, count 2 2006.285.19:58:43.12#ibcon#about to read 4, iclass 32, count 2 2006.285.19:58:43.12#ibcon#read 4, iclass 32, count 2 2006.285.19:58:43.12#ibcon#about to read 5, iclass 32, count 2 2006.285.19:58:43.12#ibcon#read 5, iclass 32, count 2 2006.285.19:58:43.12#ibcon#about to read 6, iclass 32, count 2 2006.285.19:58:43.12#ibcon#read 6, iclass 32, count 2 2006.285.19:58:43.12#ibcon#end of sib2, iclass 32, count 2 2006.285.19:58:43.12#ibcon#*mode == 0, iclass 32, count 2 2006.285.19:58:43.12#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.19:58:43.12#ibcon#[25=AT02-06\r\n] 2006.285.19:58:43.12#ibcon#*before write, iclass 32, count 2 2006.285.19:58:43.12#ibcon#enter sib2, iclass 32, count 2 2006.285.19:58:43.12#ibcon#flushed, iclass 32, count 2 2006.285.19:58:43.12#ibcon#about to write, iclass 32, count 2 2006.285.19:58:43.12#ibcon#wrote, iclass 32, count 2 2006.285.19:58:43.12#ibcon#about to read 3, iclass 32, count 2 2006.285.19:58:43.15#ibcon#read 3, iclass 32, count 2 2006.285.19:58:43.15#ibcon#about to read 4, iclass 32, count 2 2006.285.19:58:43.15#ibcon#read 4, iclass 32, count 2 2006.285.19:58:43.15#ibcon#about to read 5, iclass 32, count 2 2006.285.19:58:43.15#ibcon#read 5, iclass 32, count 2 2006.285.19:58:43.15#ibcon#about to read 6, iclass 32, count 2 2006.285.19:58:43.15#ibcon#read 6, iclass 32, count 2 2006.285.19:58:43.15#ibcon#end of sib2, iclass 32, count 2 2006.285.19:58:43.15#ibcon#*after write, iclass 32, count 2 2006.285.19:58:43.15#ibcon#*before return 0, iclass 32, count 2 2006.285.19:58:43.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:58:43.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:58:43.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.19:58:43.15#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:43.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:58:43.27#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:58:43.27#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:58:43.27#ibcon#enter wrdev, iclass 32, count 0 2006.285.19:58:43.27#ibcon#first serial, iclass 32, count 0 2006.285.19:58:43.27#ibcon#enter sib2, iclass 32, count 0 2006.285.19:58:43.27#ibcon#flushed, iclass 32, count 0 2006.285.19:58:43.27#ibcon#about to write, iclass 32, count 0 2006.285.19:58:43.27#ibcon#wrote, iclass 32, count 0 2006.285.19:58:43.27#ibcon#about to read 3, iclass 32, count 0 2006.285.19:58:43.29#ibcon#read 3, iclass 32, count 0 2006.285.19:58:43.29#ibcon#about to read 4, iclass 32, count 0 2006.285.19:58:43.29#ibcon#read 4, iclass 32, count 0 2006.285.19:58:43.29#ibcon#about to read 5, iclass 32, count 0 2006.285.19:58:43.29#ibcon#read 5, iclass 32, count 0 2006.285.19:58:43.29#ibcon#about to read 6, iclass 32, count 0 2006.285.19:58:43.29#ibcon#read 6, iclass 32, count 0 2006.285.19:58:43.29#ibcon#end of sib2, iclass 32, count 0 2006.285.19:58:43.29#ibcon#*mode == 0, iclass 32, count 0 2006.285.19:58:43.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.19:58:43.29#ibcon#[25=USB\r\n] 2006.285.19:58:43.29#ibcon#*before write, iclass 32, count 0 2006.285.19:58:43.29#ibcon#enter sib2, iclass 32, count 0 2006.285.19:58:43.29#ibcon#flushed, iclass 32, count 0 2006.285.19:58:43.29#ibcon#about to write, iclass 32, count 0 2006.285.19:58:43.29#ibcon#wrote, iclass 32, count 0 2006.285.19:58:43.29#ibcon#about to read 3, iclass 32, count 0 2006.285.19:58:43.32#ibcon#read 3, iclass 32, count 0 2006.285.19:58:43.32#ibcon#about to read 4, iclass 32, count 0 2006.285.19:58:43.32#ibcon#read 4, iclass 32, count 0 2006.285.19:58:43.32#ibcon#about to read 5, iclass 32, count 0 2006.285.19:58:43.32#ibcon#read 5, iclass 32, count 0 2006.285.19:58:43.32#ibcon#about to read 6, iclass 32, count 0 2006.285.19:58:43.32#ibcon#read 6, iclass 32, count 0 2006.285.19:58:43.32#ibcon#end of sib2, iclass 32, count 0 2006.285.19:58:43.32#ibcon#*after write, iclass 32, count 0 2006.285.19:58:43.32#ibcon#*before return 0, iclass 32, count 0 2006.285.19:58:43.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:58:43.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:58:43.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.19:58:43.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.19:58:43.32$vck44/valo=3,564.99 2006.285.19:58:43.32#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.19:58:43.32#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.19:58:43.32#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:43.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:58:43.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:58:43.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:58:43.32#ibcon#enter wrdev, iclass 34, count 0 2006.285.19:58:43.32#ibcon#first serial, iclass 34, count 0 2006.285.19:58:43.32#ibcon#enter sib2, iclass 34, count 0 2006.285.19:58:43.32#ibcon#flushed, iclass 34, count 0 2006.285.19:58:43.32#ibcon#about to write, iclass 34, count 0 2006.285.19:58:43.32#ibcon#wrote, iclass 34, count 0 2006.285.19:58:43.32#ibcon#about to read 3, iclass 34, count 0 2006.285.19:58:43.90#ibcon#read 3, iclass 34, count 0 2006.285.19:58:43.90#ibcon#about to read 4, iclass 34, count 0 2006.285.19:58:43.90#ibcon#read 4, iclass 34, count 0 2006.285.19:58:43.90#ibcon#about to read 5, iclass 34, count 0 2006.285.19:58:43.90#ibcon#read 5, iclass 34, count 0 2006.285.19:58:43.90#ibcon#about to read 6, iclass 34, count 0 2006.285.19:58:43.90#ibcon#read 6, iclass 34, count 0 2006.285.19:58:43.90#ibcon#end of sib2, iclass 34, count 0 2006.285.19:58:43.90#ibcon#*mode == 0, iclass 34, count 0 2006.285.19:58:43.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.19:58:43.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.19:58:43.90#ibcon#*before write, iclass 34, count 0 2006.285.19:58:43.90#ibcon#enter sib2, iclass 34, count 0 2006.285.19:58:43.90#ibcon#flushed, iclass 34, count 0 2006.285.19:58:43.90#ibcon#about to write, iclass 34, count 0 2006.285.19:58:43.90#ibcon#wrote, iclass 34, count 0 2006.285.19:58:43.90#ibcon#about to read 3, iclass 34, count 0 2006.285.19:58:43.94#ibcon#read 3, iclass 34, count 0 2006.285.19:58:43.94#ibcon#about to read 4, iclass 34, count 0 2006.285.19:58:43.94#ibcon#read 4, iclass 34, count 0 2006.285.19:58:43.94#ibcon#about to read 5, iclass 34, count 0 2006.285.19:58:43.94#ibcon#read 5, iclass 34, count 0 2006.285.19:58:43.94#ibcon#about to read 6, iclass 34, count 0 2006.285.19:58:43.94#ibcon#read 6, iclass 34, count 0 2006.285.19:58:43.94#ibcon#end of sib2, iclass 34, count 0 2006.285.19:58:43.94#ibcon#*after write, iclass 34, count 0 2006.285.19:58:43.94#ibcon#*before return 0, iclass 34, count 0 2006.285.19:58:43.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:58:43.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.19:58:43.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.19:58:43.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.19:58:43.94$vck44/va=3,7 2006.285.19:58:43.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.19:58:43.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.19:58:43.94#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:43.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:58:43.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:58:43.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:58:43.94#ibcon#enter wrdev, iclass 36, count 2 2006.285.19:58:43.94#ibcon#first serial, iclass 36, count 2 2006.285.19:58:43.94#ibcon#enter sib2, iclass 36, count 2 2006.285.19:58:43.94#ibcon#flushed, iclass 36, count 2 2006.285.19:58:43.94#ibcon#about to write, iclass 36, count 2 2006.285.19:58:43.94#ibcon#wrote, iclass 36, count 2 2006.285.19:58:43.94#ibcon#about to read 3, iclass 36, count 2 2006.285.19:58:43.96#ibcon#read 3, iclass 36, count 2 2006.285.19:58:43.96#ibcon#about to read 4, iclass 36, count 2 2006.285.19:58:43.96#ibcon#read 4, iclass 36, count 2 2006.285.19:58:43.96#ibcon#about to read 5, iclass 36, count 2 2006.285.19:58:43.96#ibcon#read 5, iclass 36, count 2 2006.285.19:58:43.96#ibcon#about to read 6, iclass 36, count 2 2006.285.19:58:43.96#ibcon#read 6, iclass 36, count 2 2006.285.19:58:43.96#ibcon#end of sib2, iclass 36, count 2 2006.285.19:58:43.96#ibcon#*mode == 0, iclass 36, count 2 2006.285.19:58:43.96#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.19:58:43.96#ibcon#[25=AT03-07\r\n] 2006.285.19:58:43.96#ibcon#*before write, iclass 36, count 2 2006.285.19:58:43.96#ibcon#enter sib2, iclass 36, count 2 2006.285.19:58:43.96#ibcon#flushed, iclass 36, count 2 2006.285.19:58:43.96#ibcon#about to write, iclass 36, count 2 2006.285.19:58:43.96#ibcon#wrote, iclass 36, count 2 2006.285.19:58:43.96#ibcon#about to read 3, iclass 36, count 2 2006.285.19:58:43.99#ibcon#read 3, iclass 36, count 2 2006.285.19:58:43.99#ibcon#about to read 4, iclass 36, count 2 2006.285.19:58:43.99#ibcon#read 4, iclass 36, count 2 2006.285.19:58:43.99#ibcon#about to read 5, iclass 36, count 2 2006.285.19:58:43.99#ibcon#read 5, iclass 36, count 2 2006.285.19:58:43.99#ibcon#about to read 6, iclass 36, count 2 2006.285.19:58:43.99#ibcon#read 6, iclass 36, count 2 2006.285.19:58:43.99#ibcon#end of sib2, iclass 36, count 2 2006.285.19:58:43.99#ibcon#*after write, iclass 36, count 2 2006.285.19:58:43.99#ibcon#*before return 0, iclass 36, count 2 2006.285.19:58:43.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:58:43.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.19:58:43.99#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.19:58:43.99#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:43.99#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:58:44.11#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:58:44.11#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:58:44.11#ibcon#enter wrdev, iclass 36, count 0 2006.285.19:58:44.11#ibcon#first serial, iclass 36, count 0 2006.285.19:58:44.11#ibcon#enter sib2, iclass 36, count 0 2006.285.19:58:44.11#ibcon#flushed, iclass 36, count 0 2006.285.19:58:44.11#ibcon#about to write, iclass 36, count 0 2006.285.19:58:44.11#ibcon#wrote, iclass 36, count 0 2006.285.19:58:44.11#ibcon#about to read 3, iclass 36, count 0 2006.285.19:58:44.13#ibcon#read 3, iclass 36, count 0 2006.285.19:58:44.13#ibcon#about to read 4, iclass 36, count 0 2006.285.19:58:44.13#ibcon#read 4, iclass 36, count 0 2006.285.19:58:44.13#ibcon#about to read 5, iclass 36, count 0 2006.285.19:58:44.13#ibcon#read 5, iclass 36, count 0 2006.285.19:58:44.13#ibcon#about to read 6, iclass 36, count 0 2006.285.19:58:44.13#ibcon#read 6, iclass 36, count 0 2006.285.19:58:44.13#ibcon#end of sib2, iclass 36, count 0 2006.285.19:58:44.13#ibcon#*mode == 0, iclass 36, count 0 2006.285.19:58:44.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.19:58:44.13#ibcon#[25=USB\r\n] 2006.285.19:58:44.13#ibcon#*before write, iclass 36, count 0 2006.285.19:58:44.13#ibcon#enter sib2, iclass 36, count 0 2006.285.19:58:44.13#ibcon#flushed, iclass 36, count 0 2006.285.19:58:44.13#ibcon#about to write, iclass 36, count 0 2006.285.19:58:44.13#ibcon#wrote, iclass 36, count 0 2006.285.19:58:44.13#ibcon#about to read 3, iclass 36, count 0 2006.285.19:58:44.16#ibcon#read 3, iclass 36, count 0 2006.285.19:58:44.16#ibcon#about to read 4, iclass 36, count 0 2006.285.19:58:44.16#ibcon#read 4, iclass 36, count 0 2006.285.19:58:44.16#ibcon#about to read 5, iclass 36, count 0 2006.285.19:58:44.16#ibcon#read 5, iclass 36, count 0 2006.285.19:58:44.16#ibcon#about to read 6, iclass 36, count 0 2006.285.19:58:44.16#ibcon#read 6, iclass 36, count 0 2006.285.19:58:44.16#ibcon#end of sib2, iclass 36, count 0 2006.285.19:58:44.16#ibcon#*after write, iclass 36, count 0 2006.285.19:58:44.16#ibcon#*before return 0, iclass 36, count 0 2006.285.19:58:44.16#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:58:44.16#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.19:58:44.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.19:58:44.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.19:58:44.16$vck44/valo=4,624.99 2006.285.19:58:44.16#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.19:58:44.16#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.19:58:44.16#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:44.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:58:44.16#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:58:44.16#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:58:44.16#ibcon#enter wrdev, iclass 38, count 0 2006.285.19:58:44.16#ibcon#first serial, iclass 38, count 0 2006.285.19:58:44.16#ibcon#enter sib2, iclass 38, count 0 2006.285.19:58:44.16#ibcon#flushed, iclass 38, count 0 2006.285.19:58:44.16#ibcon#about to write, iclass 38, count 0 2006.285.19:58:44.16#ibcon#wrote, iclass 38, count 0 2006.285.19:58:44.16#ibcon#about to read 3, iclass 38, count 0 2006.285.19:58:44.18#ibcon#read 3, iclass 38, count 0 2006.285.19:58:44.56#ibcon#about to read 4, iclass 38, count 0 2006.285.19:58:44.56#ibcon#read 4, iclass 38, count 0 2006.285.19:58:44.56#ibcon#about to read 5, iclass 38, count 0 2006.285.19:58:44.56#ibcon#read 5, iclass 38, count 0 2006.285.19:58:44.56#ibcon#about to read 6, iclass 38, count 0 2006.285.19:58:44.56#ibcon#read 6, iclass 38, count 0 2006.285.19:58:44.56#ibcon#end of sib2, iclass 38, count 0 2006.285.19:58:44.56#ibcon#*mode == 0, iclass 38, count 0 2006.285.19:58:44.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.19:58:44.56#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.19:58:44.56#ibcon#*before write, iclass 38, count 0 2006.285.19:58:44.56#ibcon#enter sib2, iclass 38, count 0 2006.285.19:58:44.56#ibcon#flushed, iclass 38, count 0 2006.285.19:58:44.56#ibcon#about to write, iclass 38, count 0 2006.285.19:58:44.56#ibcon#wrote, iclass 38, count 0 2006.285.19:58:44.56#ibcon#about to read 3, iclass 38, count 0 2006.285.19:58:44.60#ibcon#read 3, iclass 38, count 0 2006.285.19:58:44.60#ibcon#about to read 4, iclass 38, count 0 2006.285.19:58:44.60#ibcon#read 4, iclass 38, count 0 2006.285.19:58:44.60#ibcon#about to read 5, iclass 38, count 0 2006.285.19:58:44.60#ibcon#read 5, iclass 38, count 0 2006.285.19:58:44.60#ibcon#about to read 6, iclass 38, count 0 2006.285.19:58:44.60#ibcon#read 6, iclass 38, count 0 2006.285.19:58:44.60#ibcon#end of sib2, iclass 38, count 0 2006.285.19:58:44.60#ibcon#*after write, iclass 38, count 0 2006.285.19:58:44.60#ibcon#*before return 0, iclass 38, count 0 2006.285.19:58:44.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:58:44.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:58:44.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.19:58:44.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.19:58:44.60$vck44/va=4,6 2006.285.19:58:44.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.19:58:44.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.19:58:44.60#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:44.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:58:44.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:58:44.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:58:44.60#ibcon#enter wrdev, iclass 40, count 2 2006.285.19:58:44.60#ibcon#first serial, iclass 40, count 2 2006.285.19:58:44.60#ibcon#enter sib2, iclass 40, count 2 2006.285.19:58:44.60#ibcon#flushed, iclass 40, count 2 2006.285.19:58:44.60#ibcon#about to write, iclass 40, count 2 2006.285.19:58:44.60#ibcon#wrote, iclass 40, count 2 2006.285.19:58:44.60#ibcon#about to read 3, iclass 40, count 2 2006.285.19:58:44.62#ibcon#read 3, iclass 40, count 2 2006.285.19:58:44.62#ibcon#about to read 4, iclass 40, count 2 2006.285.19:58:44.62#ibcon#read 4, iclass 40, count 2 2006.285.19:58:44.62#ibcon#about to read 5, iclass 40, count 2 2006.285.19:58:44.62#ibcon#read 5, iclass 40, count 2 2006.285.19:58:44.62#ibcon#about to read 6, iclass 40, count 2 2006.285.19:58:44.62#ibcon#read 6, iclass 40, count 2 2006.285.19:58:44.62#ibcon#end of sib2, iclass 40, count 2 2006.285.19:58:44.62#ibcon#*mode == 0, iclass 40, count 2 2006.285.19:58:44.62#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.19:58:44.62#ibcon#[25=AT04-06\r\n] 2006.285.19:58:44.62#ibcon#*before write, iclass 40, count 2 2006.285.19:58:44.62#ibcon#enter sib2, iclass 40, count 2 2006.285.19:58:44.62#ibcon#flushed, iclass 40, count 2 2006.285.19:58:44.62#ibcon#about to write, iclass 40, count 2 2006.285.19:58:44.62#ibcon#wrote, iclass 40, count 2 2006.285.19:58:44.62#ibcon#about to read 3, iclass 40, count 2 2006.285.19:58:44.65#ibcon#read 3, iclass 40, count 2 2006.285.19:58:44.65#ibcon#about to read 4, iclass 40, count 2 2006.285.19:58:44.65#ibcon#read 4, iclass 40, count 2 2006.285.19:58:44.65#ibcon#about to read 5, iclass 40, count 2 2006.285.19:58:44.65#ibcon#read 5, iclass 40, count 2 2006.285.19:58:44.65#ibcon#about to read 6, iclass 40, count 2 2006.285.19:58:44.65#ibcon#read 6, iclass 40, count 2 2006.285.19:58:44.65#ibcon#end of sib2, iclass 40, count 2 2006.285.19:58:44.65#ibcon#*after write, iclass 40, count 2 2006.285.19:58:44.65#ibcon#*before return 0, iclass 40, count 2 2006.285.19:58:44.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:58:44.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:58:44.65#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.19:58:44.65#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:44.65#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:58:44.77#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:58:44.77#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:58:44.77#ibcon#enter wrdev, iclass 40, count 0 2006.285.19:58:44.77#ibcon#first serial, iclass 40, count 0 2006.285.19:58:44.77#ibcon#enter sib2, iclass 40, count 0 2006.285.19:58:44.77#ibcon#flushed, iclass 40, count 0 2006.285.19:58:44.77#ibcon#about to write, iclass 40, count 0 2006.285.19:58:44.77#ibcon#wrote, iclass 40, count 0 2006.285.19:58:44.77#ibcon#about to read 3, iclass 40, count 0 2006.285.19:58:44.79#ibcon#read 3, iclass 40, count 0 2006.285.19:58:44.79#ibcon#about to read 4, iclass 40, count 0 2006.285.19:58:44.79#ibcon#read 4, iclass 40, count 0 2006.285.19:58:44.79#ibcon#about to read 5, iclass 40, count 0 2006.285.19:58:44.79#ibcon#read 5, iclass 40, count 0 2006.285.19:58:44.79#ibcon#about to read 6, iclass 40, count 0 2006.285.19:58:44.79#ibcon#read 6, iclass 40, count 0 2006.285.19:58:44.79#ibcon#end of sib2, iclass 40, count 0 2006.285.19:58:44.79#ibcon#*mode == 0, iclass 40, count 0 2006.285.19:58:44.79#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.19:58:44.79#ibcon#[25=USB\r\n] 2006.285.19:58:44.79#ibcon#*before write, iclass 40, count 0 2006.285.19:58:44.79#ibcon#enter sib2, iclass 40, count 0 2006.285.19:58:44.79#ibcon#flushed, iclass 40, count 0 2006.285.19:58:44.79#ibcon#about to write, iclass 40, count 0 2006.285.19:58:44.79#ibcon#wrote, iclass 40, count 0 2006.285.19:58:44.79#ibcon#about to read 3, iclass 40, count 0 2006.285.19:58:44.82#ibcon#read 3, iclass 40, count 0 2006.285.19:58:44.82#ibcon#about to read 4, iclass 40, count 0 2006.285.19:58:44.82#ibcon#read 4, iclass 40, count 0 2006.285.19:58:44.82#ibcon#about to read 5, iclass 40, count 0 2006.285.19:58:44.82#ibcon#read 5, iclass 40, count 0 2006.285.19:58:44.82#ibcon#about to read 6, iclass 40, count 0 2006.285.19:58:44.82#ibcon#read 6, iclass 40, count 0 2006.285.19:58:44.82#ibcon#end of sib2, iclass 40, count 0 2006.285.19:58:44.82#ibcon#*after write, iclass 40, count 0 2006.285.19:58:44.82#ibcon#*before return 0, iclass 40, count 0 2006.285.19:58:44.82#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:58:44.82#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:58:44.82#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.19:58:44.82#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.19:58:44.82$vck44/valo=5,734.99 2006.285.19:58:44.82#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.19:58:44.82#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.19:58:44.82#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:44.82#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:58:44.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:58:44.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:58:44.82#ibcon#enter wrdev, iclass 4, count 0 2006.285.19:58:44.82#ibcon#first serial, iclass 4, count 0 2006.285.19:58:44.82#ibcon#enter sib2, iclass 4, count 0 2006.285.19:58:44.82#ibcon#flushed, iclass 4, count 0 2006.285.19:58:44.82#ibcon#about to write, iclass 4, count 0 2006.285.19:58:44.82#ibcon#wrote, iclass 4, count 0 2006.285.19:58:44.82#ibcon#about to read 3, iclass 4, count 0 2006.285.19:58:44.84#ibcon#read 3, iclass 4, count 0 2006.285.19:58:44.84#ibcon#about to read 4, iclass 4, count 0 2006.285.19:58:44.84#ibcon#read 4, iclass 4, count 0 2006.285.19:58:44.84#ibcon#about to read 5, iclass 4, count 0 2006.285.19:58:44.84#ibcon#read 5, iclass 4, count 0 2006.285.19:58:44.84#ibcon#about to read 6, iclass 4, count 0 2006.285.19:58:44.84#ibcon#read 6, iclass 4, count 0 2006.285.19:58:44.84#ibcon#end of sib2, iclass 4, count 0 2006.285.19:58:44.84#ibcon#*mode == 0, iclass 4, count 0 2006.285.19:58:44.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.19:58:44.84#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.19:58:44.84#ibcon#*before write, iclass 4, count 0 2006.285.19:58:44.84#ibcon#enter sib2, iclass 4, count 0 2006.285.19:58:44.84#ibcon#flushed, iclass 4, count 0 2006.285.19:58:44.84#ibcon#about to write, iclass 4, count 0 2006.285.19:58:44.84#ibcon#wrote, iclass 4, count 0 2006.285.19:58:44.84#ibcon#about to read 3, iclass 4, count 0 2006.285.19:58:44.88#ibcon#read 3, iclass 4, count 0 2006.285.19:58:44.88#ibcon#about to read 4, iclass 4, count 0 2006.285.19:58:44.88#ibcon#read 4, iclass 4, count 0 2006.285.19:58:44.88#ibcon#about to read 5, iclass 4, count 0 2006.285.19:58:44.88#ibcon#read 5, iclass 4, count 0 2006.285.19:58:44.88#ibcon#about to read 6, iclass 4, count 0 2006.285.19:58:44.88#ibcon#read 6, iclass 4, count 0 2006.285.19:58:44.88#ibcon#end of sib2, iclass 4, count 0 2006.285.19:58:44.88#ibcon#*after write, iclass 4, count 0 2006.285.19:58:44.88#ibcon#*before return 0, iclass 4, count 0 2006.285.19:58:44.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:58:44.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:58:44.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.19:58:44.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.19:58:44.88$vck44/va=5,3 2006.285.19:58:44.88#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.19:58:44.88#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.19:58:44.88#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:44.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:58:44.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:58:44.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:58:44.94#ibcon#enter wrdev, iclass 6, count 2 2006.285.19:58:44.94#ibcon#first serial, iclass 6, count 2 2006.285.19:58:44.94#ibcon#enter sib2, iclass 6, count 2 2006.285.19:58:44.94#ibcon#flushed, iclass 6, count 2 2006.285.19:58:44.94#ibcon#about to write, iclass 6, count 2 2006.285.19:58:44.94#ibcon#wrote, iclass 6, count 2 2006.285.19:58:44.94#ibcon#about to read 3, iclass 6, count 2 2006.285.19:58:44.96#ibcon#read 3, iclass 6, count 2 2006.285.19:58:44.96#ibcon#about to read 4, iclass 6, count 2 2006.285.19:58:44.96#ibcon#read 4, iclass 6, count 2 2006.285.19:58:44.96#ibcon#about to read 5, iclass 6, count 2 2006.285.19:58:44.96#ibcon#read 5, iclass 6, count 2 2006.285.19:58:44.96#ibcon#about to read 6, iclass 6, count 2 2006.285.19:58:44.96#ibcon#read 6, iclass 6, count 2 2006.285.19:58:44.96#ibcon#end of sib2, iclass 6, count 2 2006.285.19:58:44.96#ibcon#*mode == 0, iclass 6, count 2 2006.285.19:58:44.96#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.19:58:44.96#ibcon#[25=AT05-03\r\n] 2006.285.19:58:44.96#ibcon#*before write, iclass 6, count 2 2006.285.19:58:44.96#ibcon#enter sib2, iclass 6, count 2 2006.285.19:58:44.96#ibcon#flushed, iclass 6, count 2 2006.285.19:58:44.96#ibcon#about to write, iclass 6, count 2 2006.285.19:58:44.96#ibcon#wrote, iclass 6, count 2 2006.285.19:58:44.96#ibcon#about to read 3, iclass 6, count 2 2006.285.19:58:44.99#ibcon#read 3, iclass 6, count 2 2006.285.19:58:44.99#ibcon#about to read 4, iclass 6, count 2 2006.285.19:58:44.99#ibcon#read 4, iclass 6, count 2 2006.285.19:58:44.99#ibcon#about to read 5, iclass 6, count 2 2006.285.19:58:44.99#ibcon#read 5, iclass 6, count 2 2006.285.19:58:44.99#ibcon#about to read 6, iclass 6, count 2 2006.285.19:58:44.99#ibcon#read 6, iclass 6, count 2 2006.285.19:58:44.99#ibcon#end of sib2, iclass 6, count 2 2006.285.19:58:44.99#ibcon#*after write, iclass 6, count 2 2006.285.19:58:44.99#ibcon#*before return 0, iclass 6, count 2 2006.285.19:58:44.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:58:44.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:58:44.99#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.19:58:44.99#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:44.99#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:58:45.11#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:58:45.11#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:58:45.11#ibcon#enter wrdev, iclass 6, count 0 2006.285.19:58:45.11#ibcon#first serial, iclass 6, count 0 2006.285.19:58:45.11#ibcon#enter sib2, iclass 6, count 0 2006.285.19:58:45.11#ibcon#flushed, iclass 6, count 0 2006.285.19:58:45.11#ibcon#about to write, iclass 6, count 0 2006.285.19:58:45.11#ibcon#wrote, iclass 6, count 0 2006.285.19:58:45.11#ibcon#about to read 3, iclass 6, count 0 2006.285.19:58:45.13#ibcon#read 3, iclass 6, count 0 2006.285.19:58:45.13#ibcon#about to read 4, iclass 6, count 0 2006.285.19:58:45.13#ibcon#read 4, iclass 6, count 0 2006.285.19:58:45.13#ibcon#about to read 5, iclass 6, count 0 2006.285.19:58:45.13#ibcon#read 5, iclass 6, count 0 2006.285.19:58:45.13#ibcon#about to read 6, iclass 6, count 0 2006.285.19:58:45.13#ibcon#read 6, iclass 6, count 0 2006.285.19:58:45.13#ibcon#end of sib2, iclass 6, count 0 2006.285.19:58:45.13#ibcon#*mode == 0, iclass 6, count 0 2006.285.19:58:45.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.19:58:45.13#ibcon#[25=USB\r\n] 2006.285.19:58:45.13#ibcon#*before write, iclass 6, count 0 2006.285.19:58:45.13#ibcon#enter sib2, iclass 6, count 0 2006.285.19:58:45.13#ibcon#flushed, iclass 6, count 0 2006.285.19:58:45.13#ibcon#about to write, iclass 6, count 0 2006.285.19:58:45.13#ibcon#wrote, iclass 6, count 0 2006.285.19:58:45.13#ibcon#about to read 3, iclass 6, count 0 2006.285.19:58:45.16#ibcon#read 3, iclass 6, count 0 2006.285.19:58:45.16#ibcon#about to read 4, iclass 6, count 0 2006.285.19:58:45.16#ibcon#read 4, iclass 6, count 0 2006.285.19:58:45.16#ibcon#about to read 5, iclass 6, count 0 2006.285.19:58:45.16#ibcon#read 5, iclass 6, count 0 2006.285.19:58:45.16#ibcon#about to read 6, iclass 6, count 0 2006.285.19:58:45.16#ibcon#read 6, iclass 6, count 0 2006.285.19:58:45.16#ibcon#end of sib2, iclass 6, count 0 2006.285.19:58:45.16#ibcon#*after write, iclass 6, count 0 2006.285.19:58:45.16#ibcon#*before return 0, iclass 6, count 0 2006.285.19:58:45.16#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:58:45.16#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:58:45.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.19:58:45.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.19:58:45.16$vck44/valo=6,814.99 2006.285.19:58:45.16#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.19:58:45.16#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.19:58:45.16#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:45.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:58:45.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:58:45.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:58:45.16#ibcon#enter wrdev, iclass 10, count 0 2006.285.19:58:45.16#ibcon#first serial, iclass 10, count 0 2006.285.19:58:45.16#ibcon#enter sib2, iclass 10, count 0 2006.285.19:58:45.16#ibcon#flushed, iclass 10, count 0 2006.285.19:58:45.16#ibcon#about to write, iclass 10, count 0 2006.285.19:58:45.16#ibcon#wrote, iclass 10, count 0 2006.285.19:58:45.16#ibcon#about to read 3, iclass 10, count 0 2006.285.19:58:45.18#ibcon#read 3, iclass 10, count 0 2006.285.19:58:45.18#ibcon#about to read 4, iclass 10, count 0 2006.285.19:58:45.18#ibcon#read 4, iclass 10, count 0 2006.285.19:58:45.18#ibcon#about to read 5, iclass 10, count 0 2006.285.19:58:45.18#ibcon#read 5, iclass 10, count 0 2006.285.19:58:45.18#ibcon#about to read 6, iclass 10, count 0 2006.285.19:58:45.18#ibcon#read 6, iclass 10, count 0 2006.285.19:58:45.18#ibcon#end of sib2, iclass 10, count 0 2006.285.19:58:45.18#ibcon#*mode == 0, iclass 10, count 0 2006.285.19:58:45.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.19:58:45.18#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.19:58:45.18#ibcon#*before write, iclass 10, count 0 2006.285.19:58:45.18#ibcon#enter sib2, iclass 10, count 0 2006.285.19:58:45.18#ibcon#flushed, iclass 10, count 0 2006.285.19:58:45.18#ibcon#about to write, iclass 10, count 0 2006.285.19:58:45.18#ibcon#wrote, iclass 10, count 0 2006.285.19:58:45.18#ibcon#about to read 3, iclass 10, count 0 2006.285.19:58:45.22#ibcon#read 3, iclass 10, count 0 2006.285.19:58:45.22#ibcon#about to read 4, iclass 10, count 0 2006.285.19:58:45.22#ibcon#read 4, iclass 10, count 0 2006.285.19:58:45.22#ibcon#about to read 5, iclass 10, count 0 2006.285.19:58:45.22#ibcon#read 5, iclass 10, count 0 2006.285.19:58:45.22#ibcon#about to read 6, iclass 10, count 0 2006.285.19:58:45.22#ibcon#read 6, iclass 10, count 0 2006.285.19:58:45.22#ibcon#end of sib2, iclass 10, count 0 2006.285.19:58:45.22#ibcon#*after write, iclass 10, count 0 2006.285.19:58:45.22#ibcon#*before return 0, iclass 10, count 0 2006.285.19:58:45.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:58:45.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:58:45.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.19:58:45.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.19:58:45.22$vck44/va=6,4 2006.285.19:58:45.22#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.19:58:45.22#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.19:58:45.22#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:45.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:58:45.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:58:45.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:58:45.28#ibcon#enter wrdev, iclass 12, count 2 2006.285.19:58:45.28#ibcon#first serial, iclass 12, count 2 2006.285.19:58:45.28#ibcon#enter sib2, iclass 12, count 2 2006.285.19:58:45.28#ibcon#flushed, iclass 12, count 2 2006.285.19:58:45.28#ibcon#about to write, iclass 12, count 2 2006.285.19:58:45.28#ibcon#wrote, iclass 12, count 2 2006.285.19:58:45.28#ibcon#about to read 3, iclass 12, count 2 2006.285.19:58:45.30#ibcon#read 3, iclass 12, count 2 2006.285.19:58:45.30#ibcon#about to read 4, iclass 12, count 2 2006.285.19:58:45.30#ibcon#read 4, iclass 12, count 2 2006.285.19:58:45.30#ibcon#about to read 5, iclass 12, count 2 2006.285.19:58:45.30#ibcon#read 5, iclass 12, count 2 2006.285.19:58:45.30#ibcon#about to read 6, iclass 12, count 2 2006.285.19:58:45.30#ibcon#read 6, iclass 12, count 2 2006.285.19:58:45.30#ibcon#end of sib2, iclass 12, count 2 2006.285.19:58:45.30#ibcon#*mode == 0, iclass 12, count 2 2006.285.19:58:45.30#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.19:58:45.30#ibcon#[25=AT06-04\r\n] 2006.285.19:58:45.30#ibcon#*before write, iclass 12, count 2 2006.285.19:58:45.30#ibcon#enter sib2, iclass 12, count 2 2006.285.19:58:45.30#ibcon#flushed, iclass 12, count 2 2006.285.19:58:45.30#ibcon#about to write, iclass 12, count 2 2006.285.19:58:45.30#ibcon#wrote, iclass 12, count 2 2006.285.19:58:45.30#ibcon#about to read 3, iclass 12, count 2 2006.285.19:58:45.33#ibcon#read 3, iclass 12, count 2 2006.285.19:58:45.33#ibcon#about to read 4, iclass 12, count 2 2006.285.19:58:45.33#ibcon#read 4, iclass 12, count 2 2006.285.19:58:45.33#ibcon#about to read 5, iclass 12, count 2 2006.285.19:58:45.33#ibcon#read 5, iclass 12, count 2 2006.285.19:58:45.33#ibcon#about to read 6, iclass 12, count 2 2006.285.19:58:45.33#ibcon#read 6, iclass 12, count 2 2006.285.19:58:45.33#ibcon#end of sib2, iclass 12, count 2 2006.285.19:58:45.33#ibcon#*after write, iclass 12, count 2 2006.285.19:58:45.33#ibcon#*before return 0, iclass 12, count 2 2006.285.19:58:45.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:58:45.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:58:45.33#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.19:58:45.33#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:45.33#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:58:45.45#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:58:45.45#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:58:45.45#ibcon#enter wrdev, iclass 12, count 0 2006.285.19:58:45.45#ibcon#first serial, iclass 12, count 0 2006.285.19:58:45.45#ibcon#enter sib2, iclass 12, count 0 2006.285.19:58:45.45#ibcon#flushed, iclass 12, count 0 2006.285.19:58:45.45#ibcon#about to write, iclass 12, count 0 2006.285.19:58:45.45#ibcon#wrote, iclass 12, count 0 2006.285.19:58:45.45#ibcon#about to read 3, iclass 12, count 0 2006.285.19:58:45.47#ibcon#read 3, iclass 12, count 0 2006.285.19:58:45.47#ibcon#about to read 4, iclass 12, count 0 2006.285.19:58:45.47#ibcon#read 4, iclass 12, count 0 2006.285.19:58:45.47#ibcon#about to read 5, iclass 12, count 0 2006.285.19:58:45.47#ibcon#read 5, iclass 12, count 0 2006.285.19:58:45.47#ibcon#about to read 6, iclass 12, count 0 2006.285.19:58:45.47#ibcon#read 6, iclass 12, count 0 2006.285.19:58:45.47#ibcon#end of sib2, iclass 12, count 0 2006.285.19:58:45.47#ibcon#*mode == 0, iclass 12, count 0 2006.285.19:58:45.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.19:58:45.47#ibcon#[25=USB\r\n] 2006.285.19:58:45.47#ibcon#*before write, iclass 12, count 0 2006.285.19:58:45.47#ibcon#enter sib2, iclass 12, count 0 2006.285.19:58:45.47#ibcon#flushed, iclass 12, count 0 2006.285.19:58:45.47#ibcon#about to write, iclass 12, count 0 2006.285.19:58:45.47#ibcon#wrote, iclass 12, count 0 2006.285.19:58:45.47#ibcon#about to read 3, iclass 12, count 0 2006.285.19:58:45.50#ibcon#read 3, iclass 12, count 0 2006.285.19:58:45.50#ibcon#about to read 4, iclass 12, count 0 2006.285.19:58:45.50#ibcon#read 4, iclass 12, count 0 2006.285.19:58:45.50#ibcon#about to read 5, iclass 12, count 0 2006.285.19:58:45.50#ibcon#read 5, iclass 12, count 0 2006.285.19:58:45.50#ibcon#about to read 6, iclass 12, count 0 2006.285.19:58:45.50#ibcon#read 6, iclass 12, count 0 2006.285.19:58:45.50#ibcon#end of sib2, iclass 12, count 0 2006.285.19:58:45.50#ibcon#*after write, iclass 12, count 0 2006.285.19:58:45.50#ibcon#*before return 0, iclass 12, count 0 2006.285.19:58:45.50#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:58:45.50#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:58:45.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.19:58:45.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.19:58:45.50$vck44/valo=7,864.99 2006.285.19:58:45.50#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.19:58:45.50#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.19:58:45.50#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:45.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:58:45.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:58:45.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:58:45.50#ibcon#enter wrdev, iclass 14, count 0 2006.285.19:58:45.50#ibcon#first serial, iclass 14, count 0 2006.285.19:58:45.50#ibcon#enter sib2, iclass 14, count 0 2006.285.19:58:45.50#ibcon#flushed, iclass 14, count 0 2006.285.19:58:45.50#ibcon#about to write, iclass 14, count 0 2006.285.19:58:45.50#ibcon#wrote, iclass 14, count 0 2006.285.19:58:45.50#ibcon#about to read 3, iclass 14, count 0 2006.285.19:58:45.52#ibcon#read 3, iclass 14, count 0 2006.285.19:58:45.52#ibcon#about to read 4, iclass 14, count 0 2006.285.19:58:45.52#ibcon#read 4, iclass 14, count 0 2006.285.19:58:45.52#ibcon#about to read 5, iclass 14, count 0 2006.285.19:58:45.52#ibcon#read 5, iclass 14, count 0 2006.285.19:58:45.52#ibcon#about to read 6, iclass 14, count 0 2006.285.19:58:45.52#ibcon#read 6, iclass 14, count 0 2006.285.19:58:45.52#ibcon#end of sib2, iclass 14, count 0 2006.285.19:58:45.52#ibcon#*mode == 0, iclass 14, count 0 2006.285.19:58:45.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.19:58:45.52#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.19:58:45.52#ibcon#*before write, iclass 14, count 0 2006.285.19:58:45.52#ibcon#enter sib2, iclass 14, count 0 2006.285.19:58:45.52#ibcon#flushed, iclass 14, count 0 2006.285.19:58:45.52#ibcon#about to write, iclass 14, count 0 2006.285.19:58:45.52#ibcon#wrote, iclass 14, count 0 2006.285.19:58:45.52#ibcon#about to read 3, iclass 14, count 0 2006.285.19:58:45.56#ibcon#read 3, iclass 14, count 0 2006.285.19:58:45.56#ibcon#about to read 4, iclass 14, count 0 2006.285.19:58:45.56#ibcon#read 4, iclass 14, count 0 2006.285.19:58:45.56#ibcon#about to read 5, iclass 14, count 0 2006.285.19:58:45.56#ibcon#read 5, iclass 14, count 0 2006.285.19:58:45.56#ibcon#about to read 6, iclass 14, count 0 2006.285.19:58:45.56#ibcon#read 6, iclass 14, count 0 2006.285.19:58:45.56#ibcon#end of sib2, iclass 14, count 0 2006.285.19:58:45.56#ibcon#*after write, iclass 14, count 0 2006.285.19:58:45.56#ibcon#*before return 0, iclass 14, count 0 2006.285.19:58:45.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:58:45.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:58:45.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.19:58:45.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.19:58:45.56$vck44/va=7,4 2006.285.19:58:45.56#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.19:58:45.56#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.19:58:45.56#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:45.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:58:45.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:58:45.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:58:45.62#ibcon#enter wrdev, iclass 16, count 2 2006.285.19:58:45.62#ibcon#first serial, iclass 16, count 2 2006.285.19:58:45.62#ibcon#enter sib2, iclass 16, count 2 2006.285.19:58:45.62#ibcon#flushed, iclass 16, count 2 2006.285.19:58:45.62#ibcon#about to write, iclass 16, count 2 2006.285.19:58:45.62#ibcon#wrote, iclass 16, count 2 2006.285.19:58:45.62#ibcon#about to read 3, iclass 16, count 2 2006.285.19:58:45.64#ibcon#read 3, iclass 16, count 2 2006.285.19:58:45.64#ibcon#about to read 4, iclass 16, count 2 2006.285.19:58:45.64#ibcon#read 4, iclass 16, count 2 2006.285.19:58:45.64#ibcon#about to read 5, iclass 16, count 2 2006.285.19:58:45.64#ibcon#read 5, iclass 16, count 2 2006.285.19:58:45.64#ibcon#about to read 6, iclass 16, count 2 2006.285.19:58:45.64#ibcon#read 6, iclass 16, count 2 2006.285.19:58:45.64#ibcon#end of sib2, iclass 16, count 2 2006.285.19:58:45.64#ibcon#*mode == 0, iclass 16, count 2 2006.285.19:58:45.64#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.19:58:45.64#ibcon#[25=AT07-04\r\n] 2006.285.19:58:45.64#ibcon#*before write, iclass 16, count 2 2006.285.19:58:45.64#ibcon#enter sib2, iclass 16, count 2 2006.285.19:58:45.64#ibcon#flushed, iclass 16, count 2 2006.285.19:58:45.64#ibcon#about to write, iclass 16, count 2 2006.285.19:58:45.64#ibcon#wrote, iclass 16, count 2 2006.285.19:58:45.64#ibcon#about to read 3, iclass 16, count 2 2006.285.19:58:45.67#ibcon#read 3, iclass 16, count 2 2006.285.19:58:45.67#ibcon#about to read 4, iclass 16, count 2 2006.285.19:58:45.67#ibcon#read 4, iclass 16, count 2 2006.285.19:58:45.67#ibcon#about to read 5, iclass 16, count 2 2006.285.19:58:45.67#ibcon#read 5, iclass 16, count 2 2006.285.19:58:45.67#ibcon#about to read 6, iclass 16, count 2 2006.285.19:58:45.67#ibcon#read 6, iclass 16, count 2 2006.285.19:58:45.67#ibcon#end of sib2, iclass 16, count 2 2006.285.19:58:45.67#ibcon#*after write, iclass 16, count 2 2006.285.19:58:45.67#ibcon#*before return 0, iclass 16, count 2 2006.285.19:58:45.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:58:45.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:58:45.67#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.19:58:45.67#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:45.67#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:58:45.79#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:58:45.79#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:58:45.79#ibcon#enter wrdev, iclass 16, count 0 2006.285.19:58:45.79#ibcon#first serial, iclass 16, count 0 2006.285.19:58:45.79#ibcon#enter sib2, iclass 16, count 0 2006.285.19:58:45.79#ibcon#flushed, iclass 16, count 0 2006.285.19:58:45.79#ibcon#about to write, iclass 16, count 0 2006.285.19:58:45.79#ibcon#wrote, iclass 16, count 0 2006.285.19:58:45.79#ibcon#about to read 3, iclass 16, count 0 2006.285.19:58:45.81#ibcon#read 3, iclass 16, count 0 2006.285.19:58:45.81#ibcon#about to read 4, iclass 16, count 0 2006.285.19:58:45.81#ibcon#read 4, iclass 16, count 0 2006.285.19:58:45.81#ibcon#about to read 5, iclass 16, count 0 2006.285.19:58:45.81#ibcon#read 5, iclass 16, count 0 2006.285.19:58:45.81#ibcon#about to read 6, iclass 16, count 0 2006.285.19:58:45.81#ibcon#read 6, iclass 16, count 0 2006.285.19:58:45.81#ibcon#end of sib2, iclass 16, count 0 2006.285.19:58:45.81#ibcon#*mode == 0, iclass 16, count 0 2006.285.19:58:45.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.19:58:45.81#ibcon#[25=USB\r\n] 2006.285.19:58:45.81#ibcon#*before write, iclass 16, count 0 2006.285.19:58:45.81#ibcon#enter sib2, iclass 16, count 0 2006.285.19:58:45.81#ibcon#flushed, iclass 16, count 0 2006.285.19:58:45.81#ibcon#about to write, iclass 16, count 0 2006.285.19:58:45.81#ibcon#wrote, iclass 16, count 0 2006.285.19:58:45.81#ibcon#about to read 3, iclass 16, count 0 2006.285.19:58:45.84#ibcon#read 3, iclass 16, count 0 2006.285.19:58:45.84#ibcon#about to read 4, iclass 16, count 0 2006.285.19:58:45.84#ibcon#read 4, iclass 16, count 0 2006.285.19:58:45.84#ibcon#about to read 5, iclass 16, count 0 2006.285.19:58:45.84#ibcon#read 5, iclass 16, count 0 2006.285.19:58:45.84#ibcon#about to read 6, iclass 16, count 0 2006.285.19:58:45.84#ibcon#read 6, iclass 16, count 0 2006.285.19:58:45.84#ibcon#end of sib2, iclass 16, count 0 2006.285.19:58:45.84#ibcon#*after write, iclass 16, count 0 2006.285.19:58:45.84#ibcon#*before return 0, iclass 16, count 0 2006.285.19:58:45.84#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:58:45.84#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:58:45.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.19:58:45.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.19:58:45.84$vck44/valo=8,884.99 2006.285.19:58:45.84#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.19:58:45.84#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.19:58:45.84#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:45.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:58:45.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:58:45.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:58:45.84#ibcon#enter wrdev, iclass 18, count 0 2006.285.19:58:45.84#ibcon#first serial, iclass 18, count 0 2006.285.19:58:45.84#ibcon#enter sib2, iclass 18, count 0 2006.285.19:58:45.84#ibcon#flushed, iclass 18, count 0 2006.285.19:58:45.84#ibcon#about to write, iclass 18, count 0 2006.285.19:58:45.84#ibcon#wrote, iclass 18, count 0 2006.285.19:58:45.84#ibcon#about to read 3, iclass 18, count 0 2006.285.19:58:45.86#ibcon#read 3, iclass 18, count 0 2006.285.19:58:45.86#ibcon#about to read 4, iclass 18, count 0 2006.285.19:58:45.86#ibcon#read 4, iclass 18, count 0 2006.285.19:58:45.86#ibcon#about to read 5, iclass 18, count 0 2006.285.19:58:45.86#ibcon#read 5, iclass 18, count 0 2006.285.19:58:45.86#ibcon#about to read 6, iclass 18, count 0 2006.285.19:58:45.86#ibcon#read 6, iclass 18, count 0 2006.285.19:58:45.86#ibcon#end of sib2, iclass 18, count 0 2006.285.19:58:45.86#ibcon#*mode == 0, iclass 18, count 0 2006.285.19:58:45.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.19:58:45.86#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.19:58:45.86#ibcon#*before write, iclass 18, count 0 2006.285.19:58:45.86#ibcon#enter sib2, iclass 18, count 0 2006.285.19:58:45.86#ibcon#flushed, iclass 18, count 0 2006.285.19:58:45.86#ibcon#about to write, iclass 18, count 0 2006.285.19:58:45.86#ibcon#wrote, iclass 18, count 0 2006.285.19:58:45.86#ibcon#about to read 3, iclass 18, count 0 2006.285.19:58:45.90#ibcon#read 3, iclass 18, count 0 2006.285.19:58:45.90#ibcon#about to read 4, iclass 18, count 0 2006.285.19:58:45.90#ibcon#read 4, iclass 18, count 0 2006.285.19:58:45.90#ibcon#about to read 5, iclass 18, count 0 2006.285.19:58:45.90#ibcon#read 5, iclass 18, count 0 2006.285.19:58:45.90#ibcon#about to read 6, iclass 18, count 0 2006.285.19:58:45.90#ibcon#read 6, iclass 18, count 0 2006.285.19:58:45.90#ibcon#end of sib2, iclass 18, count 0 2006.285.19:58:45.90#ibcon#*after write, iclass 18, count 0 2006.285.19:58:45.90#ibcon#*before return 0, iclass 18, count 0 2006.285.19:58:45.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:58:45.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:58:45.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.19:58:45.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.19:58:45.90$vck44/va=8,3 2006.285.19:58:45.90#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.19:58:45.90#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.19:58:45.90#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:45.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:58:45.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:58:45.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:58:45.96#ibcon#enter wrdev, iclass 20, count 2 2006.285.19:58:45.96#ibcon#first serial, iclass 20, count 2 2006.285.19:58:45.96#ibcon#enter sib2, iclass 20, count 2 2006.285.19:58:45.96#ibcon#flushed, iclass 20, count 2 2006.285.19:58:45.96#ibcon#about to write, iclass 20, count 2 2006.285.19:58:45.96#ibcon#wrote, iclass 20, count 2 2006.285.19:58:45.96#ibcon#about to read 3, iclass 20, count 2 2006.285.19:58:45.98#ibcon#read 3, iclass 20, count 2 2006.285.19:58:45.98#ibcon#about to read 4, iclass 20, count 2 2006.285.19:58:45.98#ibcon#read 4, iclass 20, count 2 2006.285.19:58:45.98#ibcon#about to read 5, iclass 20, count 2 2006.285.19:58:45.98#ibcon#read 5, iclass 20, count 2 2006.285.19:58:45.98#ibcon#about to read 6, iclass 20, count 2 2006.285.19:58:45.98#ibcon#read 6, iclass 20, count 2 2006.285.19:58:45.98#ibcon#end of sib2, iclass 20, count 2 2006.285.19:58:45.98#ibcon#*mode == 0, iclass 20, count 2 2006.285.19:58:45.98#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.19:58:45.98#ibcon#[25=AT08-03\r\n] 2006.285.19:58:45.98#ibcon#*before write, iclass 20, count 2 2006.285.19:58:45.98#ibcon#enter sib2, iclass 20, count 2 2006.285.19:58:45.98#ibcon#flushed, iclass 20, count 2 2006.285.19:58:45.98#ibcon#about to write, iclass 20, count 2 2006.285.19:58:45.98#ibcon#wrote, iclass 20, count 2 2006.285.19:58:45.98#ibcon#about to read 3, iclass 20, count 2 2006.285.19:58:46.01#ibcon#read 3, iclass 20, count 2 2006.285.19:58:46.01#ibcon#about to read 4, iclass 20, count 2 2006.285.19:58:46.01#ibcon#read 4, iclass 20, count 2 2006.285.19:58:46.01#ibcon#about to read 5, iclass 20, count 2 2006.285.19:58:46.01#ibcon#read 5, iclass 20, count 2 2006.285.19:58:46.01#ibcon#about to read 6, iclass 20, count 2 2006.285.19:58:46.01#ibcon#read 6, iclass 20, count 2 2006.285.19:58:46.01#ibcon#end of sib2, iclass 20, count 2 2006.285.19:58:46.01#ibcon#*after write, iclass 20, count 2 2006.285.19:58:46.01#ibcon#*before return 0, iclass 20, count 2 2006.285.19:58:46.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:58:46.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:58:46.01#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.19:58:46.01#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:46.01#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:58:46.13#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:58:46.13#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:58:46.13#ibcon#enter wrdev, iclass 20, count 0 2006.285.19:58:46.13#ibcon#first serial, iclass 20, count 0 2006.285.19:58:46.13#ibcon#enter sib2, iclass 20, count 0 2006.285.19:58:46.13#ibcon#flushed, iclass 20, count 0 2006.285.19:58:46.13#ibcon#about to write, iclass 20, count 0 2006.285.19:58:46.13#ibcon#wrote, iclass 20, count 0 2006.285.19:58:46.13#ibcon#about to read 3, iclass 20, count 0 2006.285.19:58:46.15#ibcon#read 3, iclass 20, count 0 2006.285.19:58:46.15#ibcon#about to read 4, iclass 20, count 0 2006.285.19:58:46.15#ibcon#read 4, iclass 20, count 0 2006.285.19:58:46.15#ibcon#about to read 5, iclass 20, count 0 2006.285.19:58:46.15#ibcon#read 5, iclass 20, count 0 2006.285.19:58:46.15#ibcon#about to read 6, iclass 20, count 0 2006.285.19:58:46.15#ibcon#read 6, iclass 20, count 0 2006.285.19:58:46.15#ibcon#end of sib2, iclass 20, count 0 2006.285.19:58:46.15#ibcon#*mode == 0, iclass 20, count 0 2006.285.19:58:46.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.19:58:46.15#ibcon#[25=USB\r\n] 2006.285.19:58:46.15#ibcon#*before write, iclass 20, count 0 2006.285.19:58:46.15#ibcon#enter sib2, iclass 20, count 0 2006.285.19:58:46.15#ibcon#flushed, iclass 20, count 0 2006.285.19:58:46.15#ibcon#about to write, iclass 20, count 0 2006.285.19:58:46.15#ibcon#wrote, iclass 20, count 0 2006.285.19:58:46.15#ibcon#about to read 3, iclass 20, count 0 2006.285.19:58:46.18#ibcon#read 3, iclass 20, count 0 2006.285.19:58:46.18#ibcon#about to read 4, iclass 20, count 0 2006.285.19:58:46.18#ibcon#read 4, iclass 20, count 0 2006.285.19:58:46.18#ibcon#about to read 5, iclass 20, count 0 2006.285.19:58:46.18#ibcon#read 5, iclass 20, count 0 2006.285.19:58:46.18#ibcon#about to read 6, iclass 20, count 0 2006.285.19:58:46.18#ibcon#read 6, iclass 20, count 0 2006.285.19:58:46.18#ibcon#end of sib2, iclass 20, count 0 2006.285.19:58:46.18#ibcon#*after write, iclass 20, count 0 2006.285.19:58:46.18#ibcon#*before return 0, iclass 20, count 0 2006.285.19:58:46.18#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:58:46.18#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:58:46.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.19:58:46.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.19:58:46.18$vck44/vblo=1,629.99 2006.285.19:58:46.18#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.19:58:46.18#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.19:58:46.18#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:46.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:58:46.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:58:46.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:58:46.18#ibcon#enter wrdev, iclass 22, count 0 2006.285.19:58:46.18#ibcon#first serial, iclass 22, count 0 2006.285.19:58:46.18#ibcon#enter sib2, iclass 22, count 0 2006.285.19:58:46.18#ibcon#flushed, iclass 22, count 0 2006.285.19:58:46.18#ibcon#about to write, iclass 22, count 0 2006.285.19:58:46.18#ibcon#wrote, iclass 22, count 0 2006.285.19:58:46.18#ibcon#about to read 3, iclass 22, count 0 2006.285.19:58:46.20#ibcon#read 3, iclass 22, count 0 2006.285.19:58:46.20#ibcon#about to read 4, iclass 22, count 0 2006.285.19:58:46.20#ibcon#read 4, iclass 22, count 0 2006.285.19:58:46.20#ibcon#about to read 5, iclass 22, count 0 2006.285.19:58:46.20#ibcon#read 5, iclass 22, count 0 2006.285.19:58:46.20#ibcon#about to read 6, iclass 22, count 0 2006.285.19:58:46.20#ibcon#read 6, iclass 22, count 0 2006.285.19:58:46.20#ibcon#end of sib2, iclass 22, count 0 2006.285.19:58:46.20#ibcon#*mode == 0, iclass 22, count 0 2006.285.19:58:46.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.19:58:46.20#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.19:58:46.20#ibcon#*before write, iclass 22, count 0 2006.285.19:58:46.20#ibcon#enter sib2, iclass 22, count 0 2006.285.19:58:46.20#ibcon#flushed, iclass 22, count 0 2006.285.19:58:46.20#ibcon#about to write, iclass 22, count 0 2006.285.19:58:46.20#ibcon#wrote, iclass 22, count 0 2006.285.19:58:46.20#ibcon#about to read 3, iclass 22, count 0 2006.285.19:58:46.24#ibcon#read 3, iclass 22, count 0 2006.285.19:58:46.24#ibcon#about to read 4, iclass 22, count 0 2006.285.19:58:46.24#ibcon#read 4, iclass 22, count 0 2006.285.19:58:46.24#ibcon#about to read 5, iclass 22, count 0 2006.285.19:58:46.24#ibcon#read 5, iclass 22, count 0 2006.285.19:58:46.24#ibcon#about to read 6, iclass 22, count 0 2006.285.19:58:46.24#ibcon#read 6, iclass 22, count 0 2006.285.19:58:46.24#ibcon#end of sib2, iclass 22, count 0 2006.285.19:58:46.24#ibcon#*after write, iclass 22, count 0 2006.285.19:58:46.24#ibcon#*before return 0, iclass 22, count 0 2006.285.19:58:46.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:58:46.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:58:46.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.19:58:46.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.19:58:46.24$vck44/vb=1,4 2006.285.19:58:46.24#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.19:58:46.24#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.19:58:46.24#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:46.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:58:46.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:58:46.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:58:46.24#ibcon#enter wrdev, iclass 24, count 2 2006.285.19:58:46.24#ibcon#first serial, iclass 24, count 2 2006.285.19:58:46.24#ibcon#enter sib2, iclass 24, count 2 2006.285.19:58:46.24#ibcon#flushed, iclass 24, count 2 2006.285.19:58:46.24#ibcon#about to write, iclass 24, count 2 2006.285.19:58:46.24#ibcon#wrote, iclass 24, count 2 2006.285.19:58:46.24#ibcon#about to read 3, iclass 24, count 2 2006.285.19:58:46.26#ibcon#read 3, iclass 24, count 2 2006.285.19:58:46.26#ibcon#about to read 4, iclass 24, count 2 2006.285.19:58:46.26#ibcon#read 4, iclass 24, count 2 2006.285.19:58:46.26#ibcon#about to read 5, iclass 24, count 2 2006.285.19:58:46.26#ibcon#read 5, iclass 24, count 2 2006.285.19:58:46.26#ibcon#about to read 6, iclass 24, count 2 2006.285.19:58:46.26#ibcon#read 6, iclass 24, count 2 2006.285.19:58:46.26#ibcon#end of sib2, iclass 24, count 2 2006.285.19:58:46.26#ibcon#*mode == 0, iclass 24, count 2 2006.285.19:58:46.26#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.19:58:46.26#ibcon#[27=AT01-04\r\n] 2006.285.19:58:46.26#ibcon#*before write, iclass 24, count 2 2006.285.19:58:46.26#ibcon#enter sib2, iclass 24, count 2 2006.285.19:58:46.26#ibcon#flushed, iclass 24, count 2 2006.285.19:58:46.26#ibcon#about to write, iclass 24, count 2 2006.285.19:58:46.26#ibcon#wrote, iclass 24, count 2 2006.285.19:58:46.26#ibcon#about to read 3, iclass 24, count 2 2006.285.19:58:46.29#ibcon#read 3, iclass 24, count 2 2006.285.19:58:46.29#ibcon#about to read 4, iclass 24, count 2 2006.285.19:58:46.29#ibcon#read 4, iclass 24, count 2 2006.285.19:58:46.29#ibcon#about to read 5, iclass 24, count 2 2006.285.19:58:46.29#ibcon#read 5, iclass 24, count 2 2006.285.19:58:46.29#ibcon#about to read 6, iclass 24, count 2 2006.285.19:58:46.29#ibcon#read 6, iclass 24, count 2 2006.285.19:58:46.29#ibcon#end of sib2, iclass 24, count 2 2006.285.19:58:46.29#ibcon#*after write, iclass 24, count 2 2006.285.19:58:46.29#ibcon#*before return 0, iclass 24, count 2 2006.285.19:58:46.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:58:46.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.19:58:46.29#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.19:58:46.29#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:46.29#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:58:46.41#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:58:46.41#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:58:46.41#ibcon#enter wrdev, iclass 24, count 0 2006.285.19:58:46.41#ibcon#first serial, iclass 24, count 0 2006.285.19:58:46.41#ibcon#enter sib2, iclass 24, count 0 2006.285.19:58:46.41#ibcon#flushed, iclass 24, count 0 2006.285.19:58:46.41#ibcon#about to write, iclass 24, count 0 2006.285.19:58:46.41#ibcon#wrote, iclass 24, count 0 2006.285.19:58:46.41#ibcon#about to read 3, iclass 24, count 0 2006.285.19:58:46.43#ibcon#read 3, iclass 24, count 0 2006.285.19:58:46.43#ibcon#about to read 4, iclass 24, count 0 2006.285.19:58:46.43#ibcon#read 4, iclass 24, count 0 2006.285.19:58:46.43#ibcon#about to read 5, iclass 24, count 0 2006.285.19:58:46.43#ibcon#read 5, iclass 24, count 0 2006.285.19:58:46.43#ibcon#about to read 6, iclass 24, count 0 2006.285.19:58:46.43#ibcon#read 6, iclass 24, count 0 2006.285.19:58:46.43#ibcon#end of sib2, iclass 24, count 0 2006.285.19:58:46.43#ibcon#*mode == 0, iclass 24, count 0 2006.285.19:58:46.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.19:58:46.43#ibcon#[27=USB\r\n] 2006.285.19:58:46.43#ibcon#*before write, iclass 24, count 0 2006.285.19:58:46.43#ibcon#enter sib2, iclass 24, count 0 2006.285.19:58:46.43#ibcon#flushed, iclass 24, count 0 2006.285.19:58:46.43#ibcon#about to write, iclass 24, count 0 2006.285.19:58:46.43#ibcon#wrote, iclass 24, count 0 2006.285.19:58:46.43#ibcon#about to read 3, iclass 24, count 0 2006.285.19:58:46.46#ibcon#read 3, iclass 24, count 0 2006.285.19:58:46.49#ibcon#about to read 4, iclass 24, count 0 2006.285.19:58:46.49#ibcon#read 4, iclass 24, count 0 2006.285.19:58:46.49#ibcon#about to read 5, iclass 24, count 0 2006.285.19:58:46.49#ibcon#read 5, iclass 24, count 0 2006.285.19:58:46.49#ibcon#about to read 6, iclass 24, count 0 2006.285.19:58:46.49#ibcon#read 6, iclass 24, count 0 2006.285.19:58:46.49#ibcon#end of sib2, iclass 24, count 0 2006.285.19:58:46.49#ibcon#*after write, iclass 24, count 0 2006.285.19:58:46.49#ibcon#*before return 0, iclass 24, count 0 2006.285.19:58:46.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:58:46.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.19:58:46.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.19:58:46.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.19:58:46.49$vck44/vblo=2,634.99 2006.285.19:58:46.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.19:58:46.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.19:58:46.49#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:46.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:58:46.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:58:46.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:58:46.49#ibcon#enter wrdev, iclass 26, count 0 2006.285.19:58:46.49#ibcon#first serial, iclass 26, count 0 2006.285.19:58:46.49#ibcon#enter sib2, iclass 26, count 0 2006.285.19:58:46.49#ibcon#flushed, iclass 26, count 0 2006.285.19:58:46.49#ibcon#about to write, iclass 26, count 0 2006.285.19:58:46.49#ibcon#wrote, iclass 26, count 0 2006.285.19:58:46.49#ibcon#about to read 3, iclass 26, count 0 2006.285.19:58:46.51#ibcon#read 3, iclass 26, count 0 2006.285.19:58:46.51#ibcon#about to read 4, iclass 26, count 0 2006.285.19:58:46.51#ibcon#read 4, iclass 26, count 0 2006.285.19:58:46.51#ibcon#about to read 5, iclass 26, count 0 2006.285.19:58:46.51#ibcon#read 5, iclass 26, count 0 2006.285.19:58:46.51#ibcon#about to read 6, iclass 26, count 0 2006.285.19:58:46.51#ibcon#read 6, iclass 26, count 0 2006.285.19:58:46.51#ibcon#end of sib2, iclass 26, count 0 2006.285.19:58:46.51#ibcon#*mode == 0, iclass 26, count 0 2006.285.19:58:46.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.19:58:46.51#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.19:58:46.51#ibcon#*before write, iclass 26, count 0 2006.285.19:58:46.51#ibcon#enter sib2, iclass 26, count 0 2006.285.19:58:46.51#ibcon#flushed, iclass 26, count 0 2006.285.19:58:46.51#ibcon#about to write, iclass 26, count 0 2006.285.19:58:46.51#ibcon#wrote, iclass 26, count 0 2006.285.19:58:46.51#ibcon#about to read 3, iclass 26, count 0 2006.285.19:58:46.55#ibcon#read 3, iclass 26, count 0 2006.285.19:58:46.55#ibcon#about to read 4, iclass 26, count 0 2006.285.19:58:46.55#ibcon#read 4, iclass 26, count 0 2006.285.19:58:46.55#ibcon#about to read 5, iclass 26, count 0 2006.285.19:58:46.55#ibcon#read 5, iclass 26, count 0 2006.285.19:58:46.55#ibcon#about to read 6, iclass 26, count 0 2006.285.19:58:46.55#ibcon#read 6, iclass 26, count 0 2006.285.19:58:46.55#ibcon#end of sib2, iclass 26, count 0 2006.285.19:58:46.55#ibcon#*after write, iclass 26, count 0 2006.285.19:58:46.55#ibcon#*before return 0, iclass 26, count 0 2006.285.19:58:46.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:58:46.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.19:58:46.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.19:58:46.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.19:58:46.55$vck44/vb=2,5 2006.285.19:58:46.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.19:58:46.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.19:58:46.55#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:46.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:58:46.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:58:46.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:58:46.61#ibcon#enter wrdev, iclass 28, count 2 2006.285.19:58:46.61#ibcon#first serial, iclass 28, count 2 2006.285.19:58:46.61#ibcon#enter sib2, iclass 28, count 2 2006.285.19:58:46.61#ibcon#flushed, iclass 28, count 2 2006.285.19:58:46.61#ibcon#about to write, iclass 28, count 2 2006.285.19:58:46.61#ibcon#wrote, iclass 28, count 2 2006.285.19:58:46.61#ibcon#about to read 3, iclass 28, count 2 2006.285.19:58:46.63#ibcon#read 3, iclass 28, count 2 2006.285.19:58:46.63#ibcon#about to read 4, iclass 28, count 2 2006.285.19:58:46.63#ibcon#read 4, iclass 28, count 2 2006.285.19:58:46.63#ibcon#about to read 5, iclass 28, count 2 2006.285.19:58:46.63#ibcon#read 5, iclass 28, count 2 2006.285.19:58:46.63#ibcon#about to read 6, iclass 28, count 2 2006.285.19:58:46.63#ibcon#read 6, iclass 28, count 2 2006.285.19:58:46.63#ibcon#end of sib2, iclass 28, count 2 2006.285.19:58:46.63#ibcon#*mode == 0, iclass 28, count 2 2006.285.19:58:46.63#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.19:58:46.63#ibcon#[27=AT02-05\r\n] 2006.285.19:58:46.63#ibcon#*before write, iclass 28, count 2 2006.285.19:58:46.63#ibcon#enter sib2, iclass 28, count 2 2006.285.19:58:46.63#ibcon#flushed, iclass 28, count 2 2006.285.19:58:46.63#ibcon#about to write, iclass 28, count 2 2006.285.19:58:46.63#ibcon#wrote, iclass 28, count 2 2006.285.19:58:46.63#ibcon#about to read 3, iclass 28, count 2 2006.285.19:58:46.66#ibcon#read 3, iclass 28, count 2 2006.285.19:58:46.66#ibcon#about to read 4, iclass 28, count 2 2006.285.19:58:46.66#ibcon#read 4, iclass 28, count 2 2006.285.19:58:46.66#ibcon#about to read 5, iclass 28, count 2 2006.285.19:58:46.66#ibcon#read 5, iclass 28, count 2 2006.285.19:58:46.66#ibcon#about to read 6, iclass 28, count 2 2006.285.19:58:46.66#ibcon#read 6, iclass 28, count 2 2006.285.19:58:46.66#ibcon#end of sib2, iclass 28, count 2 2006.285.19:58:46.66#ibcon#*after write, iclass 28, count 2 2006.285.19:58:46.66#ibcon#*before return 0, iclass 28, count 2 2006.285.19:58:46.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:58:46.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.19:58:46.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.19:58:46.66#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:46.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:58:46.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:58:46.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:58:46.78#ibcon#enter wrdev, iclass 28, count 0 2006.285.19:58:46.78#ibcon#first serial, iclass 28, count 0 2006.285.19:58:46.78#ibcon#enter sib2, iclass 28, count 0 2006.285.19:58:46.78#ibcon#flushed, iclass 28, count 0 2006.285.19:58:46.78#ibcon#about to write, iclass 28, count 0 2006.285.19:58:46.78#ibcon#wrote, iclass 28, count 0 2006.285.19:58:46.78#ibcon#about to read 3, iclass 28, count 0 2006.285.19:58:46.80#ibcon#read 3, iclass 28, count 0 2006.285.19:58:46.80#ibcon#about to read 4, iclass 28, count 0 2006.285.19:58:46.80#ibcon#read 4, iclass 28, count 0 2006.285.19:58:46.80#ibcon#about to read 5, iclass 28, count 0 2006.285.19:58:46.80#ibcon#read 5, iclass 28, count 0 2006.285.19:58:46.80#ibcon#about to read 6, iclass 28, count 0 2006.285.19:58:46.80#ibcon#read 6, iclass 28, count 0 2006.285.19:58:46.80#ibcon#end of sib2, iclass 28, count 0 2006.285.19:58:46.80#ibcon#*mode == 0, iclass 28, count 0 2006.285.19:58:46.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.19:58:46.80#ibcon#[27=USB\r\n] 2006.285.19:58:46.80#ibcon#*before write, iclass 28, count 0 2006.285.19:58:46.80#ibcon#enter sib2, iclass 28, count 0 2006.285.19:58:46.80#ibcon#flushed, iclass 28, count 0 2006.285.19:58:46.80#ibcon#about to write, iclass 28, count 0 2006.285.19:58:46.80#ibcon#wrote, iclass 28, count 0 2006.285.19:58:46.80#ibcon#about to read 3, iclass 28, count 0 2006.285.19:58:46.83#ibcon#read 3, iclass 28, count 0 2006.285.19:58:46.83#ibcon#about to read 4, iclass 28, count 0 2006.285.19:58:46.83#ibcon#read 4, iclass 28, count 0 2006.285.19:58:46.83#ibcon#about to read 5, iclass 28, count 0 2006.285.19:58:46.83#ibcon#read 5, iclass 28, count 0 2006.285.19:58:46.83#ibcon#about to read 6, iclass 28, count 0 2006.285.19:58:46.83#ibcon#read 6, iclass 28, count 0 2006.285.19:58:46.83#ibcon#end of sib2, iclass 28, count 0 2006.285.19:58:46.83#ibcon#*after write, iclass 28, count 0 2006.285.19:58:46.83#ibcon#*before return 0, iclass 28, count 0 2006.285.19:58:46.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:58:46.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.19:58:46.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.19:58:46.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.19:58:46.83$vck44/vblo=3,649.99 2006.285.19:58:46.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.19:58:46.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.19:58:46.83#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:46.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:58:46.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:58:46.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:58:46.83#ibcon#enter wrdev, iclass 30, count 0 2006.285.19:58:46.83#ibcon#first serial, iclass 30, count 0 2006.285.19:58:46.83#ibcon#enter sib2, iclass 30, count 0 2006.285.19:58:46.83#ibcon#flushed, iclass 30, count 0 2006.285.19:58:46.83#ibcon#about to write, iclass 30, count 0 2006.285.19:58:46.83#ibcon#wrote, iclass 30, count 0 2006.285.19:58:46.83#ibcon#about to read 3, iclass 30, count 0 2006.285.19:58:46.85#ibcon#read 3, iclass 30, count 0 2006.285.19:58:46.85#ibcon#about to read 4, iclass 30, count 0 2006.285.19:58:46.85#ibcon#read 4, iclass 30, count 0 2006.285.19:58:46.85#ibcon#about to read 5, iclass 30, count 0 2006.285.19:58:46.85#ibcon#read 5, iclass 30, count 0 2006.285.19:58:46.85#ibcon#about to read 6, iclass 30, count 0 2006.285.19:58:46.85#ibcon#read 6, iclass 30, count 0 2006.285.19:58:46.85#ibcon#end of sib2, iclass 30, count 0 2006.285.19:58:46.85#ibcon#*mode == 0, iclass 30, count 0 2006.285.19:58:46.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.19:58:46.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.19:58:46.85#ibcon#*before write, iclass 30, count 0 2006.285.19:58:46.85#ibcon#enter sib2, iclass 30, count 0 2006.285.19:58:46.85#ibcon#flushed, iclass 30, count 0 2006.285.19:58:46.85#ibcon#about to write, iclass 30, count 0 2006.285.19:58:46.85#ibcon#wrote, iclass 30, count 0 2006.285.19:58:46.85#ibcon#about to read 3, iclass 30, count 0 2006.285.19:58:46.89#ibcon#read 3, iclass 30, count 0 2006.285.19:58:46.89#ibcon#about to read 4, iclass 30, count 0 2006.285.19:58:46.89#ibcon#read 4, iclass 30, count 0 2006.285.19:58:46.89#ibcon#about to read 5, iclass 30, count 0 2006.285.19:58:46.89#ibcon#read 5, iclass 30, count 0 2006.285.19:58:46.89#ibcon#about to read 6, iclass 30, count 0 2006.285.19:58:46.89#ibcon#read 6, iclass 30, count 0 2006.285.19:58:46.89#ibcon#end of sib2, iclass 30, count 0 2006.285.19:58:46.89#ibcon#*after write, iclass 30, count 0 2006.285.19:58:46.89#ibcon#*before return 0, iclass 30, count 0 2006.285.19:58:46.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:58:46.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.19:58:46.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.19:58:46.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.19:58:46.89$vck44/vb=3,4 2006.285.19:58:46.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.19:58:46.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.19:58:46.89#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:46.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:58:46.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:58:46.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:58:46.95#ibcon#enter wrdev, iclass 32, count 2 2006.285.19:58:46.95#ibcon#first serial, iclass 32, count 2 2006.285.19:58:46.95#ibcon#enter sib2, iclass 32, count 2 2006.285.19:58:46.95#ibcon#flushed, iclass 32, count 2 2006.285.19:58:46.95#ibcon#about to write, iclass 32, count 2 2006.285.19:58:46.95#ibcon#wrote, iclass 32, count 2 2006.285.19:58:46.95#ibcon#about to read 3, iclass 32, count 2 2006.285.19:58:46.97#ibcon#read 3, iclass 32, count 2 2006.285.19:58:46.97#ibcon#about to read 4, iclass 32, count 2 2006.285.19:58:46.97#ibcon#read 4, iclass 32, count 2 2006.285.19:58:46.97#ibcon#about to read 5, iclass 32, count 2 2006.285.19:58:46.97#ibcon#read 5, iclass 32, count 2 2006.285.19:58:46.97#ibcon#about to read 6, iclass 32, count 2 2006.285.19:58:46.97#ibcon#read 6, iclass 32, count 2 2006.285.19:58:46.97#ibcon#end of sib2, iclass 32, count 2 2006.285.19:58:46.97#ibcon#*mode == 0, iclass 32, count 2 2006.285.19:58:46.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.19:58:46.97#ibcon#[27=AT03-04\r\n] 2006.285.19:58:46.97#ibcon#*before write, iclass 32, count 2 2006.285.19:58:46.97#ibcon#enter sib2, iclass 32, count 2 2006.285.19:58:46.97#ibcon#flushed, iclass 32, count 2 2006.285.19:58:46.97#ibcon#about to write, iclass 32, count 2 2006.285.19:58:46.97#ibcon#wrote, iclass 32, count 2 2006.285.19:58:46.97#ibcon#about to read 3, iclass 32, count 2 2006.285.19:58:47.00#ibcon#read 3, iclass 32, count 2 2006.285.19:58:47.00#ibcon#about to read 4, iclass 32, count 2 2006.285.19:58:47.00#ibcon#read 4, iclass 32, count 2 2006.285.19:58:47.00#ibcon#about to read 5, iclass 32, count 2 2006.285.19:58:47.00#ibcon#read 5, iclass 32, count 2 2006.285.19:58:47.00#ibcon#about to read 6, iclass 32, count 2 2006.285.19:58:47.00#ibcon#read 6, iclass 32, count 2 2006.285.19:58:47.00#ibcon#end of sib2, iclass 32, count 2 2006.285.19:58:47.00#ibcon#*after write, iclass 32, count 2 2006.285.19:58:47.00#ibcon#*before return 0, iclass 32, count 2 2006.285.19:58:47.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:58:47.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.19:58:47.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.19:58:47.00#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:47.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:58:47.09#abcon#<5=/14 0.6 1.2 14.571001015.2\r\n> 2006.285.19:58:47.11#abcon#{5=INTERFACE CLEAR} 2006.285.19:58:47.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:58:47.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:58:47.12#ibcon#enter wrdev, iclass 32, count 0 2006.285.19:58:47.12#ibcon#first serial, iclass 32, count 0 2006.285.19:58:47.12#ibcon#enter sib2, iclass 32, count 0 2006.285.19:58:47.12#ibcon#flushed, iclass 32, count 0 2006.285.19:58:47.12#ibcon#about to write, iclass 32, count 0 2006.285.19:58:47.12#ibcon#wrote, iclass 32, count 0 2006.285.19:58:47.12#ibcon#about to read 3, iclass 32, count 0 2006.285.19:58:47.14#ibcon#read 3, iclass 32, count 0 2006.285.19:58:47.14#ibcon#about to read 4, iclass 32, count 0 2006.285.19:58:47.14#ibcon#read 4, iclass 32, count 0 2006.285.19:58:47.14#ibcon#about to read 5, iclass 32, count 0 2006.285.19:58:47.14#ibcon#read 5, iclass 32, count 0 2006.285.19:58:47.14#ibcon#about to read 6, iclass 32, count 0 2006.285.19:58:47.14#ibcon#read 6, iclass 32, count 0 2006.285.19:58:47.14#ibcon#end of sib2, iclass 32, count 0 2006.285.19:58:47.14#ibcon#*mode == 0, iclass 32, count 0 2006.285.19:58:47.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.19:58:47.14#ibcon#[27=USB\r\n] 2006.285.19:58:47.14#ibcon#*before write, iclass 32, count 0 2006.285.19:58:47.14#ibcon#enter sib2, iclass 32, count 0 2006.285.19:58:47.14#ibcon#flushed, iclass 32, count 0 2006.285.19:58:47.14#ibcon#about to write, iclass 32, count 0 2006.285.19:58:47.14#ibcon#wrote, iclass 32, count 0 2006.285.19:58:47.14#ibcon#about to read 3, iclass 32, count 0 2006.285.19:58:47.17#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:58:47.17#ibcon#read 3, iclass 32, count 0 2006.285.19:58:47.17#ibcon#about to read 4, iclass 32, count 0 2006.285.19:58:47.17#ibcon#read 4, iclass 32, count 0 2006.285.19:58:47.17#ibcon#about to read 5, iclass 32, count 0 2006.285.19:58:47.17#ibcon#read 5, iclass 32, count 0 2006.285.19:58:47.17#ibcon#about to read 6, iclass 32, count 0 2006.285.19:58:47.17#ibcon#read 6, iclass 32, count 0 2006.285.19:58:47.17#ibcon#end of sib2, iclass 32, count 0 2006.285.19:58:47.17#ibcon#*after write, iclass 32, count 0 2006.285.19:58:47.17#ibcon#*before return 0, iclass 32, count 0 2006.285.19:58:47.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:58:47.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.19:58:47.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.19:58:47.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.19:58:47.17$vck44/vblo=4,679.99 2006.285.19:58:47.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.19:58:47.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.19:58:47.17#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:47.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:58:47.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:58:47.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:58:47.17#ibcon#enter wrdev, iclass 38, count 0 2006.285.19:58:47.17#ibcon#first serial, iclass 38, count 0 2006.285.19:58:47.17#ibcon#enter sib2, iclass 38, count 0 2006.285.19:58:47.17#ibcon#flushed, iclass 38, count 0 2006.285.19:58:47.17#ibcon#about to write, iclass 38, count 0 2006.285.19:58:47.17#ibcon#wrote, iclass 38, count 0 2006.285.19:58:47.17#ibcon#about to read 3, iclass 38, count 0 2006.285.19:58:47.19#ibcon#read 3, iclass 38, count 0 2006.285.19:58:47.19#ibcon#about to read 4, iclass 38, count 0 2006.285.19:58:47.19#ibcon#read 4, iclass 38, count 0 2006.285.19:58:47.19#ibcon#about to read 5, iclass 38, count 0 2006.285.19:58:47.19#ibcon#read 5, iclass 38, count 0 2006.285.19:58:47.19#ibcon#about to read 6, iclass 38, count 0 2006.285.19:58:47.19#ibcon#read 6, iclass 38, count 0 2006.285.19:58:47.19#ibcon#end of sib2, iclass 38, count 0 2006.285.19:58:47.19#ibcon#*mode == 0, iclass 38, count 0 2006.285.19:58:47.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.19:58:47.19#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.19:58:47.19#ibcon#*before write, iclass 38, count 0 2006.285.19:58:47.19#ibcon#enter sib2, iclass 38, count 0 2006.285.19:58:47.19#ibcon#flushed, iclass 38, count 0 2006.285.19:58:47.19#ibcon#about to write, iclass 38, count 0 2006.285.19:58:47.19#ibcon#wrote, iclass 38, count 0 2006.285.19:58:47.19#ibcon#about to read 3, iclass 38, count 0 2006.285.19:58:47.23#ibcon#read 3, iclass 38, count 0 2006.285.19:58:47.23#ibcon#about to read 4, iclass 38, count 0 2006.285.19:58:47.23#ibcon#read 4, iclass 38, count 0 2006.285.19:58:47.23#ibcon#about to read 5, iclass 38, count 0 2006.285.19:58:47.23#ibcon#read 5, iclass 38, count 0 2006.285.19:58:47.23#ibcon#about to read 6, iclass 38, count 0 2006.285.19:58:47.23#ibcon#read 6, iclass 38, count 0 2006.285.19:58:47.23#ibcon#end of sib2, iclass 38, count 0 2006.285.19:58:47.23#ibcon#*after write, iclass 38, count 0 2006.285.19:58:47.23#ibcon#*before return 0, iclass 38, count 0 2006.285.19:58:47.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:58:47.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.19:58:47.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.19:58:47.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.19:58:47.23$vck44/vb=4,5 2006.285.19:58:47.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.19:58:47.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.19:58:47.23#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:47.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:58:47.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:58:47.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:58:47.29#ibcon#enter wrdev, iclass 40, count 2 2006.285.19:58:47.29#ibcon#first serial, iclass 40, count 2 2006.285.19:58:47.29#ibcon#enter sib2, iclass 40, count 2 2006.285.19:58:47.29#ibcon#flushed, iclass 40, count 2 2006.285.19:58:47.29#ibcon#about to write, iclass 40, count 2 2006.285.19:58:47.29#ibcon#wrote, iclass 40, count 2 2006.285.19:58:47.29#ibcon#about to read 3, iclass 40, count 2 2006.285.19:58:47.31#ibcon#read 3, iclass 40, count 2 2006.285.19:58:47.31#ibcon#about to read 4, iclass 40, count 2 2006.285.19:58:47.31#ibcon#read 4, iclass 40, count 2 2006.285.19:58:47.31#ibcon#about to read 5, iclass 40, count 2 2006.285.19:58:47.31#ibcon#read 5, iclass 40, count 2 2006.285.19:58:47.31#ibcon#about to read 6, iclass 40, count 2 2006.285.19:58:47.31#ibcon#read 6, iclass 40, count 2 2006.285.19:58:47.31#ibcon#end of sib2, iclass 40, count 2 2006.285.19:58:47.31#ibcon#*mode == 0, iclass 40, count 2 2006.285.19:58:47.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.19:58:47.31#ibcon#[27=AT04-05\r\n] 2006.285.19:58:47.31#ibcon#*before write, iclass 40, count 2 2006.285.19:58:47.31#ibcon#enter sib2, iclass 40, count 2 2006.285.19:58:47.31#ibcon#flushed, iclass 40, count 2 2006.285.19:58:47.31#ibcon#about to write, iclass 40, count 2 2006.285.19:58:47.31#ibcon#wrote, iclass 40, count 2 2006.285.19:58:47.31#ibcon#about to read 3, iclass 40, count 2 2006.285.19:58:47.34#ibcon#read 3, iclass 40, count 2 2006.285.19:58:47.34#ibcon#about to read 4, iclass 40, count 2 2006.285.19:58:47.34#ibcon#read 4, iclass 40, count 2 2006.285.19:58:47.34#ibcon#about to read 5, iclass 40, count 2 2006.285.19:58:47.34#ibcon#read 5, iclass 40, count 2 2006.285.19:58:47.34#ibcon#about to read 6, iclass 40, count 2 2006.285.19:58:47.34#ibcon#read 6, iclass 40, count 2 2006.285.19:58:47.34#ibcon#end of sib2, iclass 40, count 2 2006.285.19:58:47.34#ibcon#*after write, iclass 40, count 2 2006.285.19:58:47.34#ibcon#*before return 0, iclass 40, count 2 2006.285.19:58:47.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:58:47.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.19:58:47.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.19:58:47.34#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:47.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:58:47.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:58:47.60#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:58:47.60#ibcon#enter wrdev, iclass 40, count 0 2006.285.19:58:47.60#ibcon#first serial, iclass 40, count 0 2006.285.19:58:47.60#ibcon#enter sib2, iclass 40, count 0 2006.285.19:58:47.60#ibcon#flushed, iclass 40, count 0 2006.285.19:58:47.60#ibcon#about to write, iclass 40, count 0 2006.285.19:58:47.60#ibcon#wrote, iclass 40, count 0 2006.285.19:58:47.60#ibcon#about to read 3, iclass 40, count 0 2006.285.19:58:47.62#ibcon#read 3, iclass 40, count 0 2006.285.19:58:47.62#ibcon#about to read 4, iclass 40, count 0 2006.285.19:58:47.62#ibcon#read 4, iclass 40, count 0 2006.285.19:58:47.62#ibcon#about to read 5, iclass 40, count 0 2006.285.19:58:47.62#ibcon#read 5, iclass 40, count 0 2006.285.19:58:47.62#ibcon#about to read 6, iclass 40, count 0 2006.285.19:58:47.62#ibcon#read 6, iclass 40, count 0 2006.285.19:58:47.62#ibcon#end of sib2, iclass 40, count 0 2006.285.19:58:47.62#ibcon#*mode == 0, iclass 40, count 0 2006.285.19:58:47.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.19:58:47.62#ibcon#[27=USB\r\n] 2006.285.19:58:47.62#ibcon#*before write, iclass 40, count 0 2006.285.19:58:47.62#ibcon#enter sib2, iclass 40, count 0 2006.285.19:58:47.62#ibcon#flushed, iclass 40, count 0 2006.285.19:58:47.62#ibcon#about to write, iclass 40, count 0 2006.285.19:58:47.62#ibcon#wrote, iclass 40, count 0 2006.285.19:58:47.62#ibcon#about to read 3, iclass 40, count 0 2006.285.19:58:47.65#ibcon#read 3, iclass 40, count 0 2006.285.19:58:47.65#ibcon#about to read 4, iclass 40, count 0 2006.285.19:58:47.65#ibcon#read 4, iclass 40, count 0 2006.285.19:58:47.65#ibcon#about to read 5, iclass 40, count 0 2006.285.19:58:47.65#ibcon#read 5, iclass 40, count 0 2006.285.19:58:47.65#ibcon#about to read 6, iclass 40, count 0 2006.285.19:58:47.65#ibcon#read 6, iclass 40, count 0 2006.285.19:58:47.65#ibcon#end of sib2, iclass 40, count 0 2006.285.19:58:47.65#ibcon#*after write, iclass 40, count 0 2006.285.19:58:47.65#ibcon#*before return 0, iclass 40, count 0 2006.285.19:58:47.65#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:58:47.65#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.19:58:47.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.19:58:47.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.19:58:47.65$vck44/vblo=5,709.99 2006.285.19:58:47.65#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.19:58:47.65#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.19:58:47.65#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:47.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:58:47.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:58:47.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:58:47.65#ibcon#enter wrdev, iclass 4, count 0 2006.285.19:58:47.65#ibcon#first serial, iclass 4, count 0 2006.285.19:58:47.65#ibcon#enter sib2, iclass 4, count 0 2006.285.19:58:47.65#ibcon#flushed, iclass 4, count 0 2006.285.19:58:47.65#ibcon#about to write, iclass 4, count 0 2006.285.19:58:47.65#ibcon#wrote, iclass 4, count 0 2006.285.19:58:47.65#ibcon#about to read 3, iclass 4, count 0 2006.285.19:58:47.67#ibcon#read 3, iclass 4, count 0 2006.285.19:58:47.67#ibcon#about to read 4, iclass 4, count 0 2006.285.19:58:47.67#ibcon#read 4, iclass 4, count 0 2006.285.19:58:47.67#ibcon#about to read 5, iclass 4, count 0 2006.285.19:58:47.67#ibcon#read 5, iclass 4, count 0 2006.285.19:58:47.67#ibcon#about to read 6, iclass 4, count 0 2006.285.19:58:47.67#ibcon#read 6, iclass 4, count 0 2006.285.19:58:47.67#ibcon#end of sib2, iclass 4, count 0 2006.285.19:58:47.67#ibcon#*mode == 0, iclass 4, count 0 2006.285.19:58:47.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.19:58:47.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.19:58:47.67#ibcon#*before write, iclass 4, count 0 2006.285.19:58:47.67#ibcon#enter sib2, iclass 4, count 0 2006.285.19:58:47.67#ibcon#flushed, iclass 4, count 0 2006.285.19:58:47.67#ibcon#about to write, iclass 4, count 0 2006.285.19:58:47.67#ibcon#wrote, iclass 4, count 0 2006.285.19:58:47.67#ibcon#about to read 3, iclass 4, count 0 2006.285.19:58:47.71#ibcon#read 3, iclass 4, count 0 2006.285.19:58:47.71#ibcon#about to read 4, iclass 4, count 0 2006.285.19:58:47.71#ibcon#read 4, iclass 4, count 0 2006.285.19:58:47.71#ibcon#about to read 5, iclass 4, count 0 2006.285.19:58:47.71#ibcon#read 5, iclass 4, count 0 2006.285.19:58:47.71#ibcon#about to read 6, iclass 4, count 0 2006.285.19:58:47.71#ibcon#read 6, iclass 4, count 0 2006.285.19:58:47.71#ibcon#end of sib2, iclass 4, count 0 2006.285.19:58:47.71#ibcon#*after write, iclass 4, count 0 2006.285.19:58:47.71#ibcon#*before return 0, iclass 4, count 0 2006.285.19:58:47.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:58:47.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.19:58:47.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.19:58:47.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.19:58:47.71$vck44/vb=5,4 2006.285.19:58:47.71#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.19:58:47.71#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.19:58:47.71#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:47.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:58:47.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:58:47.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:58:47.77#ibcon#enter wrdev, iclass 6, count 2 2006.285.19:58:47.77#ibcon#first serial, iclass 6, count 2 2006.285.19:58:47.77#ibcon#enter sib2, iclass 6, count 2 2006.285.19:58:47.77#ibcon#flushed, iclass 6, count 2 2006.285.19:58:47.77#ibcon#about to write, iclass 6, count 2 2006.285.19:58:47.77#ibcon#wrote, iclass 6, count 2 2006.285.19:58:47.77#ibcon#about to read 3, iclass 6, count 2 2006.285.19:58:47.79#ibcon#read 3, iclass 6, count 2 2006.285.19:58:47.79#ibcon#about to read 4, iclass 6, count 2 2006.285.19:58:47.79#ibcon#read 4, iclass 6, count 2 2006.285.19:58:47.79#ibcon#about to read 5, iclass 6, count 2 2006.285.19:58:47.79#ibcon#read 5, iclass 6, count 2 2006.285.19:58:47.79#ibcon#about to read 6, iclass 6, count 2 2006.285.19:58:47.79#ibcon#read 6, iclass 6, count 2 2006.285.19:58:47.79#ibcon#end of sib2, iclass 6, count 2 2006.285.19:58:47.79#ibcon#*mode == 0, iclass 6, count 2 2006.285.19:58:47.79#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.19:58:47.79#ibcon#[27=AT05-04\r\n] 2006.285.19:58:47.79#ibcon#*before write, iclass 6, count 2 2006.285.19:58:47.79#ibcon#enter sib2, iclass 6, count 2 2006.285.19:58:47.79#ibcon#flushed, iclass 6, count 2 2006.285.19:58:47.79#ibcon#about to write, iclass 6, count 2 2006.285.19:58:47.79#ibcon#wrote, iclass 6, count 2 2006.285.19:58:47.79#ibcon#about to read 3, iclass 6, count 2 2006.285.19:58:47.82#ibcon#read 3, iclass 6, count 2 2006.285.19:58:47.82#ibcon#about to read 4, iclass 6, count 2 2006.285.19:58:47.82#ibcon#read 4, iclass 6, count 2 2006.285.19:58:47.82#ibcon#about to read 5, iclass 6, count 2 2006.285.19:58:47.82#ibcon#read 5, iclass 6, count 2 2006.285.19:58:47.82#ibcon#about to read 6, iclass 6, count 2 2006.285.19:58:47.82#ibcon#read 6, iclass 6, count 2 2006.285.19:58:47.82#ibcon#end of sib2, iclass 6, count 2 2006.285.19:58:47.82#ibcon#*after write, iclass 6, count 2 2006.285.19:58:47.82#ibcon#*before return 0, iclass 6, count 2 2006.285.19:58:47.82#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:58:47.82#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.19:58:47.82#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.19:58:47.82#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:47.82#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:58:47.94#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:58:47.94#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:58:47.94#ibcon#enter wrdev, iclass 6, count 0 2006.285.19:58:47.94#ibcon#first serial, iclass 6, count 0 2006.285.19:58:47.94#ibcon#enter sib2, iclass 6, count 0 2006.285.19:58:47.94#ibcon#flushed, iclass 6, count 0 2006.285.19:58:47.94#ibcon#about to write, iclass 6, count 0 2006.285.19:58:47.94#ibcon#wrote, iclass 6, count 0 2006.285.19:58:47.94#ibcon#about to read 3, iclass 6, count 0 2006.285.19:58:47.96#ibcon#read 3, iclass 6, count 0 2006.285.19:58:47.96#ibcon#about to read 4, iclass 6, count 0 2006.285.19:58:47.96#ibcon#read 4, iclass 6, count 0 2006.285.19:58:47.96#ibcon#about to read 5, iclass 6, count 0 2006.285.19:58:47.96#ibcon#read 5, iclass 6, count 0 2006.285.19:58:47.96#ibcon#about to read 6, iclass 6, count 0 2006.285.19:58:47.96#ibcon#read 6, iclass 6, count 0 2006.285.19:58:47.96#ibcon#end of sib2, iclass 6, count 0 2006.285.19:58:47.96#ibcon#*mode == 0, iclass 6, count 0 2006.285.19:58:47.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.19:58:47.96#ibcon#[27=USB\r\n] 2006.285.19:58:47.96#ibcon#*before write, iclass 6, count 0 2006.285.19:58:47.96#ibcon#enter sib2, iclass 6, count 0 2006.285.19:58:47.96#ibcon#flushed, iclass 6, count 0 2006.285.19:58:47.96#ibcon#about to write, iclass 6, count 0 2006.285.19:58:47.96#ibcon#wrote, iclass 6, count 0 2006.285.19:58:47.96#ibcon#about to read 3, iclass 6, count 0 2006.285.19:58:47.99#ibcon#read 3, iclass 6, count 0 2006.285.19:58:47.99#ibcon#about to read 4, iclass 6, count 0 2006.285.19:58:47.99#ibcon#read 4, iclass 6, count 0 2006.285.19:58:47.99#ibcon#about to read 5, iclass 6, count 0 2006.285.19:58:47.99#ibcon#read 5, iclass 6, count 0 2006.285.19:58:47.99#ibcon#about to read 6, iclass 6, count 0 2006.285.19:58:47.99#ibcon#read 6, iclass 6, count 0 2006.285.19:58:47.99#ibcon#end of sib2, iclass 6, count 0 2006.285.19:58:47.99#ibcon#*after write, iclass 6, count 0 2006.285.19:58:47.99#ibcon#*before return 0, iclass 6, count 0 2006.285.19:58:47.99#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:58:47.99#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.19:58:47.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.19:58:47.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.19:58:47.99$vck44/vblo=6,719.99 2006.285.19:58:47.99#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.19:58:47.99#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.19:58:47.99#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:47.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:58:47.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:58:47.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:58:47.99#ibcon#enter wrdev, iclass 10, count 0 2006.285.19:58:47.99#ibcon#first serial, iclass 10, count 0 2006.285.19:58:47.99#ibcon#enter sib2, iclass 10, count 0 2006.285.19:58:47.99#ibcon#flushed, iclass 10, count 0 2006.285.19:58:47.99#ibcon#about to write, iclass 10, count 0 2006.285.19:58:47.99#ibcon#wrote, iclass 10, count 0 2006.285.19:58:47.99#ibcon#about to read 3, iclass 10, count 0 2006.285.19:58:48.01#ibcon#read 3, iclass 10, count 0 2006.285.19:58:48.01#ibcon#about to read 4, iclass 10, count 0 2006.285.19:58:48.01#ibcon#read 4, iclass 10, count 0 2006.285.19:58:48.01#ibcon#about to read 5, iclass 10, count 0 2006.285.19:58:48.01#ibcon#read 5, iclass 10, count 0 2006.285.19:58:48.01#ibcon#about to read 6, iclass 10, count 0 2006.285.19:58:48.01#ibcon#read 6, iclass 10, count 0 2006.285.19:58:48.01#ibcon#end of sib2, iclass 10, count 0 2006.285.19:58:48.01#ibcon#*mode == 0, iclass 10, count 0 2006.285.19:58:48.01#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.19:58:48.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.19:58:48.01#ibcon#*before write, iclass 10, count 0 2006.285.19:58:48.01#ibcon#enter sib2, iclass 10, count 0 2006.285.19:58:48.01#ibcon#flushed, iclass 10, count 0 2006.285.19:58:48.01#ibcon#about to write, iclass 10, count 0 2006.285.19:58:48.01#ibcon#wrote, iclass 10, count 0 2006.285.19:58:48.01#ibcon#about to read 3, iclass 10, count 0 2006.285.19:58:48.05#ibcon#read 3, iclass 10, count 0 2006.285.19:58:48.05#ibcon#about to read 4, iclass 10, count 0 2006.285.19:58:48.05#ibcon#read 4, iclass 10, count 0 2006.285.19:58:48.05#ibcon#about to read 5, iclass 10, count 0 2006.285.19:58:48.05#ibcon#read 5, iclass 10, count 0 2006.285.19:58:48.05#ibcon#about to read 6, iclass 10, count 0 2006.285.19:58:48.05#ibcon#read 6, iclass 10, count 0 2006.285.19:58:48.05#ibcon#end of sib2, iclass 10, count 0 2006.285.19:58:48.05#ibcon#*after write, iclass 10, count 0 2006.285.19:58:48.05#ibcon#*before return 0, iclass 10, count 0 2006.285.19:58:48.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:58:48.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.19:58:48.05#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.19:58:48.05#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.19:58:48.05$vck44/vb=6,3 2006.285.19:58:48.05#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.19:58:48.05#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.19:58:48.05#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:48.05#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:58:48.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:58:48.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:58:48.11#ibcon#enter wrdev, iclass 12, count 2 2006.285.19:58:48.11#ibcon#first serial, iclass 12, count 2 2006.285.19:58:48.11#ibcon#enter sib2, iclass 12, count 2 2006.285.19:58:48.11#ibcon#flushed, iclass 12, count 2 2006.285.19:58:48.11#ibcon#about to write, iclass 12, count 2 2006.285.19:58:48.11#ibcon#wrote, iclass 12, count 2 2006.285.19:58:48.11#ibcon#about to read 3, iclass 12, count 2 2006.285.19:58:48.13#ibcon#read 3, iclass 12, count 2 2006.285.19:58:48.13#ibcon#about to read 4, iclass 12, count 2 2006.285.19:58:48.13#ibcon#read 4, iclass 12, count 2 2006.285.19:58:48.13#ibcon#about to read 5, iclass 12, count 2 2006.285.19:58:48.13#ibcon#read 5, iclass 12, count 2 2006.285.19:58:48.13#ibcon#about to read 6, iclass 12, count 2 2006.285.19:58:48.13#ibcon#read 6, iclass 12, count 2 2006.285.19:58:48.13#ibcon#end of sib2, iclass 12, count 2 2006.285.19:58:48.13#ibcon#*mode == 0, iclass 12, count 2 2006.285.19:58:48.13#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.19:58:48.13#ibcon#[27=AT06-03\r\n] 2006.285.19:58:48.13#ibcon#*before write, iclass 12, count 2 2006.285.19:58:48.13#ibcon#enter sib2, iclass 12, count 2 2006.285.19:58:48.13#ibcon#flushed, iclass 12, count 2 2006.285.19:58:48.13#ibcon#about to write, iclass 12, count 2 2006.285.19:58:48.13#ibcon#wrote, iclass 12, count 2 2006.285.19:58:48.13#ibcon#about to read 3, iclass 12, count 2 2006.285.19:58:48.16#ibcon#read 3, iclass 12, count 2 2006.285.19:58:48.16#ibcon#about to read 4, iclass 12, count 2 2006.285.19:58:48.16#ibcon#read 4, iclass 12, count 2 2006.285.19:58:48.16#ibcon#about to read 5, iclass 12, count 2 2006.285.19:58:48.16#ibcon#read 5, iclass 12, count 2 2006.285.19:58:48.16#ibcon#about to read 6, iclass 12, count 2 2006.285.19:58:48.16#ibcon#read 6, iclass 12, count 2 2006.285.19:58:48.16#ibcon#end of sib2, iclass 12, count 2 2006.285.19:58:48.16#ibcon#*after write, iclass 12, count 2 2006.285.19:58:48.16#ibcon#*before return 0, iclass 12, count 2 2006.285.19:58:48.16#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:58:48.16#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.19:58:48.16#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.19:58:48.16#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:48.16#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:58:48.28#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:58:48.28#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:58:48.28#ibcon#enter wrdev, iclass 12, count 0 2006.285.19:58:48.28#ibcon#first serial, iclass 12, count 0 2006.285.19:58:48.28#ibcon#enter sib2, iclass 12, count 0 2006.285.19:58:48.28#ibcon#flushed, iclass 12, count 0 2006.285.19:58:48.28#ibcon#about to write, iclass 12, count 0 2006.285.19:58:48.28#ibcon#wrote, iclass 12, count 0 2006.285.19:58:48.28#ibcon#about to read 3, iclass 12, count 0 2006.285.19:58:48.30#ibcon#read 3, iclass 12, count 0 2006.285.19:58:48.30#ibcon#about to read 4, iclass 12, count 0 2006.285.19:58:48.30#ibcon#read 4, iclass 12, count 0 2006.285.19:58:48.30#ibcon#about to read 5, iclass 12, count 0 2006.285.19:58:48.30#ibcon#read 5, iclass 12, count 0 2006.285.19:58:48.30#ibcon#about to read 6, iclass 12, count 0 2006.285.19:58:48.30#ibcon#read 6, iclass 12, count 0 2006.285.19:58:48.30#ibcon#end of sib2, iclass 12, count 0 2006.285.19:58:48.30#ibcon#*mode == 0, iclass 12, count 0 2006.285.19:58:48.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.19:58:48.30#ibcon#[27=USB\r\n] 2006.285.19:58:48.30#ibcon#*before write, iclass 12, count 0 2006.285.19:58:48.30#ibcon#enter sib2, iclass 12, count 0 2006.285.19:58:48.30#ibcon#flushed, iclass 12, count 0 2006.285.19:58:48.30#ibcon#about to write, iclass 12, count 0 2006.285.19:58:48.30#ibcon#wrote, iclass 12, count 0 2006.285.19:58:48.30#ibcon#about to read 3, iclass 12, count 0 2006.285.19:58:48.33#ibcon#read 3, iclass 12, count 0 2006.285.19:58:48.33#ibcon#about to read 4, iclass 12, count 0 2006.285.19:58:48.33#ibcon#read 4, iclass 12, count 0 2006.285.19:58:48.33#ibcon#about to read 5, iclass 12, count 0 2006.285.19:58:48.33#ibcon#read 5, iclass 12, count 0 2006.285.19:58:48.33#ibcon#about to read 6, iclass 12, count 0 2006.285.19:58:48.33#ibcon#read 6, iclass 12, count 0 2006.285.19:58:48.33#ibcon#end of sib2, iclass 12, count 0 2006.285.19:58:48.33#ibcon#*after write, iclass 12, count 0 2006.285.19:58:48.33#ibcon#*before return 0, iclass 12, count 0 2006.285.19:58:48.33#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:58:48.33#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.19:58:48.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.19:58:48.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.19:58:48.33$vck44/vblo=7,734.99 2006.285.19:58:48.33#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.19:58:48.33#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.19:58:48.33#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:48.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:58:48.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:58:48.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:58:48.33#ibcon#enter wrdev, iclass 14, count 0 2006.285.19:58:48.33#ibcon#first serial, iclass 14, count 0 2006.285.19:58:48.33#ibcon#enter sib2, iclass 14, count 0 2006.285.19:58:48.33#ibcon#flushed, iclass 14, count 0 2006.285.19:58:48.33#ibcon#about to write, iclass 14, count 0 2006.285.19:58:48.33#ibcon#wrote, iclass 14, count 0 2006.285.19:58:48.33#ibcon#about to read 3, iclass 14, count 0 2006.285.19:58:48.35#ibcon#read 3, iclass 14, count 0 2006.285.19:58:48.63#ibcon#about to read 4, iclass 14, count 0 2006.285.19:58:48.63#ibcon#read 4, iclass 14, count 0 2006.285.19:58:48.63#ibcon#about to read 5, iclass 14, count 0 2006.285.19:58:48.63#ibcon#read 5, iclass 14, count 0 2006.285.19:58:48.63#ibcon#about to read 6, iclass 14, count 0 2006.285.19:58:48.63#ibcon#read 6, iclass 14, count 0 2006.285.19:58:48.63#ibcon#end of sib2, iclass 14, count 0 2006.285.19:58:48.63#ibcon#*mode == 0, iclass 14, count 0 2006.285.19:58:48.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.19:58:48.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.19:58:48.63#ibcon#*before write, iclass 14, count 0 2006.285.19:58:48.63#ibcon#enter sib2, iclass 14, count 0 2006.285.19:58:48.63#ibcon#flushed, iclass 14, count 0 2006.285.19:58:48.63#ibcon#about to write, iclass 14, count 0 2006.285.19:58:48.63#ibcon#wrote, iclass 14, count 0 2006.285.19:58:48.63#ibcon#about to read 3, iclass 14, count 0 2006.285.19:58:48.67#ibcon#read 3, iclass 14, count 0 2006.285.19:58:48.67#ibcon#about to read 4, iclass 14, count 0 2006.285.19:58:48.67#ibcon#read 4, iclass 14, count 0 2006.285.19:58:48.67#ibcon#about to read 5, iclass 14, count 0 2006.285.19:58:48.67#ibcon#read 5, iclass 14, count 0 2006.285.19:58:48.67#ibcon#about to read 6, iclass 14, count 0 2006.285.19:58:48.67#ibcon#read 6, iclass 14, count 0 2006.285.19:58:48.67#ibcon#end of sib2, iclass 14, count 0 2006.285.19:58:48.67#ibcon#*after write, iclass 14, count 0 2006.285.19:58:48.67#ibcon#*before return 0, iclass 14, count 0 2006.285.19:58:48.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:58:48.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.19:58:48.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.19:58:48.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.19:58:48.67$vck44/vb=7,4 2006.285.19:58:48.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.19:58:48.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.19:58:48.67#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:48.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:58:48.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:58:48.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:58:48.67#ibcon#enter wrdev, iclass 16, count 2 2006.285.19:58:48.67#ibcon#first serial, iclass 16, count 2 2006.285.19:58:48.67#ibcon#enter sib2, iclass 16, count 2 2006.285.19:58:48.67#ibcon#flushed, iclass 16, count 2 2006.285.19:58:48.67#ibcon#about to write, iclass 16, count 2 2006.285.19:58:48.67#ibcon#wrote, iclass 16, count 2 2006.285.19:58:48.67#ibcon#about to read 3, iclass 16, count 2 2006.285.19:58:48.69#ibcon#read 3, iclass 16, count 2 2006.285.19:58:48.69#ibcon#about to read 4, iclass 16, count 2 2006.285.19:58:48.69#ibcon#read 4, iclass 16, count 2 2006.285.19:58:48.69#ibcon#about to read 5, iclass 16, count 2 2006.285.19:58:48.69#ibcon#read 5, iclass 16, count 2 2006.285.19:58:48.69#ibcon#about to read 6, iclass 16, count 2 2006.285.19:58:48.69#ibcon#read 6, iclass 16, count 2 2006.285.19:58:48.69#ibcon#end of sib2, iclass 16, count 2 2006.285.19:58:48.69#ibcon#*mode == 0, iclass 16, count 2 2006.285.19:58:48.69#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.19:58:48.69#ibcon#[27=AT07-04\r\n] 2006.285.19:58:48.69#ibcon#*before write, iclass 16, count 2 2006.285.19:58:48.69#ibcon#enter sib2, iclass 16, count 2 2006.285.19:58:48.69#ibcon#flushed, iclass 16, count 2 2006.285.19:58:48.69#ibcon#about to write, iclass 16, count 2 2006.285.19:58:48.69#ibcon#wrote, iclass 16, count 2 2006.285.19:58:48.69#ibcon#about to read 3, iclass 16, count 2 2006.285.19:58:48.72#ibcon#read 3, iclass 16, count 2 2006.285.19:58:48.72#ibcon#about to read 4, iclass 16, count 2 2006.285.19:58:48.72#ibcon#read 4, iclass 16, count 2 2006.285.19:58:48.72#ibcon#about to read 5, iclass 16, count 2 2006.285.19:58:48.72#ibcon#read 5, iclass 16, count 2 2006.285.19:58:48.72#ibcon#about to read 6, iclass 16, count 2 2006.285.19:58:48.72#ibcon#read 6, iclass 16, count 2 2006.285.19:58:48.72#ibcon#end of sib2, iclass 16, count 2 2006.285.19:58:48.72#ibcon#*after write, iclass 16, count 2 2006.285.19:58:48.72#ibcon#*before return 0, iclass 16, count 2 2006.285.19:58:48.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:58:48.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.19:58:48.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.19:58:48.72#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:48.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:58:48.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:58:48.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:58:48.84#ibcon#enter wrdev, iclass 16, count 0 2006.285.19:58:48.84#ibcon#first serial, iclass 16, count 0 2006.285.19:58:48.84#ibcon#enter sib2, iclass 16, count 0 2006.285.19:58:48.84#ibcon#flushed, iclass 16, count 0 2006.285.19:58:48.84#ibcon#about to write, iclass 16, count 0 2006.285.19:58:48.84#ibcon#wrote, iclass 16, count 0 2006.285.19:58:48.84#ibcon#about to read 3, iclass 16, count 0 2006.285.19:58:48.86#ibcon#read 3, iclass 16, count 0 2006.285.19:58:48.86#ibcon#about to read 4, iclass 16, count 0 2006.285.19:58:48.86#ibcon#read 4, iclass 16, count 0 2006.285.19:58:48.86#ibcon#about to read 5, iclass 16, count 0 2006.285.19:58:48.86#ibcon#read 5, iclass 16, count 0 2006.285.19:58:48.86#ibcon#about to read 6, iclass 16, count 0 2006.285.19:58:48.86#ibcon#read 6, iclass 16, count 0 2006.285.19:58:48.86#ibcon#end of sib2, iclass 16, count 0 2006.285.19:58:48.86#ibcon#*mode == 0, iclass 16, count 0 2006.285.19:58:48.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.19:58:48.86#ibcon#[27=USB\r\n] 2006.285.19:58:48.86#ibcon#*before write, iclass 16, count 0 2006.285.19:58:48.86#ibcon#enter sib2, iclass 16, count 0 2006.285.19:58:48.86#ibcon#flushed, iclass 16, count 0 2006.285.19:58:48.86#ibcon#about to write, iclass 16, count 0 2006.285.19:58:48.86#ibcon#wrote, iclass 16, count 0 2006.285.19:58:48.86#ibcon#about to read 3, iclass 16, count 0 2006.285.19:58:48.89#ibcon#read 3, iclass 16, count 0 2006.285.19:58:48.89#ibcon#about to read 4, iclass 16, count 0 2006.285.19:58:48.89#ibcon#read 4, iclass 16, count 0 2006.285.19:58:48.89#ibcon#about to read 5, iclass 16, count 0 2006.285.19:58:48.89#ibcon#read 5, iclass 16, count 0 2006.285.19:58:48.89#ibcon#about to read 6, iclass 16, count 0 2006.285.19:58:48.89#ibcon#read 6, iclass 16, count 0 2006.285.19:58:48.89#ibcon#end of sib2, iclass 16, count 0 2006.285.19:58:48.89#ibcon#*after write, iclass 16, count 0 2006.285.19:58:48.89#ibcon#*before return 0, iclass 16, count 0 2006.285.19:58:48.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:58:48.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.19:58:48.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.19:58:48.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.19:58:48.89$vck44/vblo=8,744.99 2006.285.19:58:48.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.19:58:48.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.19:58:48.89#ibcon#ireg 17 cls_cnt 0 2006.285.19:58:48.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:58:48.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:58:48.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:58:48.89#ibcon#enter wrdev, iclass 18, count 0 2006.285.19:58:48.89#ibcon#first serial, iclass 18, count 0 2006.285.19:58:48.89#ibcon#enter sib2, iclass 18, count 0 2006.285.19:58:48.89#ibcon#flushed, iclass 18, count 0 2006.285.19:58:48.89#ibcon#about to write, iclass 18, count 0 2006.285.19:58:48.89#ibcon#wrote, iclass 18, count 0 2006.285.19:58:48.89#ibcon#about to read 3, iclass 18, count 0 2006.285.19:58:48.91#ibcon#read 3, iclass 18, count 0 2006.285.19:58:48.91#ibcon#about to read 4, iclass 18, count 0 2006.285.19:58:48.91#ibcon#read 4, iclass 18, count 0 2006.285.19:58:48.91#ibcon#about to read 5, iclass 18, count 0 2006.285.19:58:48.91#ibcon#read 5, iclass 18, count 0 2006.285.19:58:48.91#ibcon#about to read 6, iclass 18, count 0 2006.285.19:58:48.91#ibcon#read 6, iclass 18, count 0 2006.285.19:58:48.91#ibcon#end of sib2, iclass 18, count 0 2006.285.19:58:48.91#ibcon#*mode == 0, iclass 18, count 0 2006.285.19:58:48.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.19:58:48.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.19:58:48.91#ibcon#*before write, iclass 18, count 0 2006.285.19:58:48.91#ibcon#enter sib2, iclass 18, count 0 2006.285.19:58:48.91#ibcon#flushed, iclass 18, count 0 2006.285.19:58:48.91#ibcon#about to write, iclass 18, count 0 2006.285.19:58:48.91#ibcon#wrote, iclass 18, count 0 2006.285.19:58:48.91#ibcon#about to read 3, iclass 18, count 0 2006.285.19:58:48.95#ibcon#read 3, iclass 18, count 0 2006.285.19:58:48.95#ibcon#about to read 4, iclass 18, count 0 2006.285.19:58:48.95#ibcon#read 4, iclass 18, count 0 2006.285.19:58:48.95#ibcon#about to read 5, iclass 18, count 0 2006.285.19:58:48.95#ibcon#read 5, iclass 18, count 0 2006.285.19:58:48.95#ibcon#about to read 6, iclass 18, count 0 2006.285.19:58:48.95#ibcon#read 6, iclass 18, count 0 2006.285.19:58:48.95#ibcon#end of sib2, iclass 18, count 0 2006.285.19:58:48.95#ibcon#*after write, iclass 18, count 0 2006.285.19:58:48.95#ibcon#*before return 0, iclass 18, count 0 2006.285.19:58:48.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:58:48.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.19:58:48.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.19:58:48.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.19:58:48.95$vck44/vb=8,4 2006.285.19:58:48.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.19:58:48.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.19:58:48.95#ibcon#ireg 11 cls_cnt 2 2006.285.19:58:48.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:58:49.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:58:49.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:58:49.01#ibcon#enter wrdev, iclass 20, count 2 2006.285.19:58:49.01#ibcon#first serial, iclass 20, count 2 2006.285.19:58:49.01#ibcon#enter sib2, iclass 20, count 2 2006.285.19:58:49.01#ibcon#flushed, iclass 20, count 2 2006.285.19:58:49.01#ibcon#about to write, iclass 20, count 2 2006.285.19:58:49.01#ibcon#wrote, iclass 20, count 2 2006.285.19:58:49.01#ibcon#about to read 3, iclass 20, count 2 2006.285.19:58:49.03#ibcon#read 3, iclass 20, count 2 2006.285.19:58:49.03#ibcon#about to read 4, iclass 20, count 2 2006.285.19:58:49.03#ibcon#read 4, iclass 20, count 2 2006.285.19:58:49.03#ibcon#about to read 5, iclass 20, count 2 2006.285.19:58:49.03#ibcon#read 5, iclass 20, count 2 2006.285.19:58:49.03#ibcon#about to read 6, iclass 20, count 2 2006.285.19:58:49.03#ibcon#read 6, iclass 20, count 2 2006.285.19:58:49.03#ibcon#end of sib2, iclass 20, count 2 2006.285.19:58:49.03#ibcon#*mode == 0, iclass 20, count 2 2006.285.19:58:49.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.19:58:49.03#ibcon#[27=AT08-04\r\n] 2006.285.19:58:49.03#ibcon#*before write, iclass 20, count 2 2006.285.19:58:49.03#ibcon#enter sib2, iclass 20, count 2 2006.285.19:58:49.03#ibcon#flushed, iclass 20, count 2 2006.285.19:58:49.03#ibcon#about to write, iclass 20, count 2 2006.285.19:58:49.03#ibcon#wrote, iclass 20, count 2 2006.285.19:58:49.03#ibcon#about to read 3, iclass 20, count 2 2006.285.19:58:49.06#ibcon#read 3, iclass 20, count 2 2006.285.19:58:49.06#ibcon#about to read 4, iclass 20, count 2 2006.285.19:58:49.06#ibcon#read 4, iclass 20, count 2 2006.285.19:58:49.06#ibcon#about to read 5, iclass 20, count 2 2006.285.19:58:49.06#ibcon#read 5, iclass 20, count 2 2006.285.19:58:49.06#ibcon#about to read 6, iclass 20, count 2 2006.285.19:58:49.06#ibcon#read 6, iclass 20, count 2 2006.285.19:58:49.06#ibcon#end of sib2, iclass 20, count 2 2006.285.19:58:49.06#ibcon#*after write, iclass 20, count 2 2006.285.19:58:49.06#ibcon#*before return 0, iclass 20, count 2 2006.285.19:58:49.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:58:49.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.19:58:49.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.19:58:49.06#ibcon#ireg 7 cls_cnt 0 2006.285.19:58:49.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:58:49.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:58:49.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:58:49.18#ibcon#enter wrdev, iclass 20, count 0 2006.285.19:58:49.18#ibcon#first serial, iclass 20, count 0 2006.285.19:58:49.18#ibcon#enter sib2, iclass 20, count 0 2006.285.19:58:49.18#ibcon#flushed, iclass 20, count 0 2006.285.19:58:49.18#ibcon#about to write, iclass 20, count 0 2006.285.19:58:49.18#ibcon#wrote, iclass 20, count 0 2006.285.19:58:49.18#ibcon#about to read 3, iclass 20, count 0 2006.285.19:58:49.20#ibcon#read 3, iclass 20, count 0 2006.285.19:58:49.20#ibcon#about to read 4, iclass 20, count 0 2006.285.19:58:49.20#ibcon#read 4, iclass 20, count 0 2006.285.19:58:49.20#ibcon#about to read 5, iclass 20, count 0 2006.285.19:58:49.20#ibcon#read 5, iclass 20, count 0 2006.285.19:58:49.20#ibcon#about to read 6, iclass 20, count 0 2006.285.19:58:49.20#ibcon#read 6, iclass 20, count 0 2006.285.19:58:49.20#ibcon#end of sib2, iclass 20, count 0 2006.285.19:58:49.20#ibcon#*mode == 0, iclass 20, count 0 2006.285.19:58:49.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.19:58:49.20#ibcon#[27=USB\r\n] 2006.285.19:58:49.20#ibcon#*before write, iclass 20, count 0 2006.285.19:58:49.20#ibcon#enter sib2, iclass 20, count 0 2006.285.19:58:49.20#ibcon#flushed, iclass 20, count 0 2006.285.19:58:49.20#ibcon#about to write, iclass 20, count 0 2006.285.19:58:49.20#ibcon#wrote, iclass 20, count 0 2006.285.19:58:49.20#ibcon#about to read 3, iclass 20, count 0 2006.285.19:58:49.23#ibcon#read 3, iclass 20, count 0 2006.285.19:58:49.23#ibcon#about to read 4, iclass 20, count 0 2006.285.19:58:49.23#ibcon#read 4, iclass 20, count 0 2006.285.19:58:49.23#ibcon#about to read 5, iclass 20, count 0 2006.285.19:58:49.23#ibcon#read 5, iclass 20, count 0 2006.285.19:58:49.23#ibcon#about to read 6, iclass 20, count 0 2006.285.19:58:49.23#ibcon#read 6, iclass 20, count 0 2006.285.19:58:49.23#ibcon#end of sib2, iclass 20, count 0 2006.285.19:58:49.23#ibcon#*after write, iclass 20, count 0 2006.285.19:58:49.23#ibcon#*before return 0, iclass 20, count 0 2006.285.19:58:49.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:58:49.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.19:58:49.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.19:58:49.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.19:58:49.23$vck44/vabw=wide 2006.285.19:58:49.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.19:58:49.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.19:58:49.23#ibcon#ireg 8 cls_cnt 0 2006.285.19:58:49.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:58:49.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:58:49.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:58:49.23#ibcon#enter wrdev, iclass 22, count 0 2006.285.19:58:49.23#ibcon#first serial, iclass 22, count 0 2006.285.19:58:49.23#ibcon#enter sib2, iclass 22, count 0 2006.285.19:58:49.23#ibcon#flushed, iclass 22, count 0 2006.285.19:58:49.23#ibcon#about to write, iclass 22, count 0 2006.285.19:58:49.23#ibcon#wrote, iclass 22, count 0 2006.285.19:58:49.23#ibcon#about to read 3, iclass 22, count 0 2006.285.19:58:49.25#ibcon#read 3, iclass 22, count 0 2006.285.19:58:49.25#ibcon#about to read 4, iclass 22, count 0 2006.285.19:58:49.25#ibcon#read 4, iclass 22, count 0 2006.285.19:58:49.25#ibcon#about to read 5, iclass 22, count 0 2006.285.19:58:49.25#ibcon#read 5, iclass 22, count 0 2006.285.19:58:49.25#ibcon#about to read 6, iclass 22, count 0 2006.285.19:58:49.25#ibcon#read 6, iclass 22, count 0 2006.285.19:58:49.25#ibcon#end of sib2, iclass 22, count 0 2006.285.19:58:49.25#ibcon#*mode == 0, iclass 22, count 0 2006.285.19:58:49.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.19:58:49.25#ibcon#[25=BW32\r\n] 2006.285.19:58:49.25#ibcon#*before write, iclass 22, count 0 2006.285.19:58:49.25#ibcon#enter sib2, iclass 22, count 0 2006.285.19:58:49.25#ibcon#flushed, iclass 22, count 0 2006.285.19:58:49.25#ibcon#about to write, iclass 22, count 0 2006.285.19:58:49.25#ibcon#wrote, iclass 22, count 0 2006.285.19:58:49.25#ibcon#about to read 3, iclass 22, count 0 2006.285.19:58:49.28#ibcon#read 3, iclass 22, count 0 2006.285.19:58:49.28#ibcon#about to read 4, iclass 22, count 0 2006.285.19:58:49.28#ibcon#read 4, iclass 22, count 0 2006.285.19:58:49.28#ibcon#about to read 5, iclass 22, count 0 2006.285.19:58:49.28#ibcon#read 5, iclass 22, count 0 2006.285.19:58:49.28#ibcon#about to read 6, iclass 22, count 0 2006.285.19:58:49.28#ibcon#read 6, iclass 22, count 0 2006.285.19:58:49.28#ibcon#end of sib2, iclass 22, count 0 2006.285.19:58:49.28#ibcon#*after write, iclass 22, count 0 2006.285.19:58:49.28#ibcon#*before return 0, iclass 22, count 0 2006.285.19:58:49.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:58:49.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.19:58:49.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.19:58:49.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.19:58:49.28$vck44/vbbw=wide 2006.285.19:58:49.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.19:58:49.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.19:58:49.28#ibcon#ireg 8 cls_cnt 0 2006.285.19:58:49.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:58:49.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:58:49.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:58:49.35#ibcon#enter wrdev, iclass 24, count 0 2006.285.19:58:49.35#ibcon#first serial, iclass 24, count 0 2006.285.19:58:49.35#ibcon#enter sib2, iclass 24, count 0 2006.285.19:58:49.35#ibcon#flushed, iclass 24, count 0 2006.285.19:58:49.35#ibcon#about to write, iclass 24, count 0 2006.285.19:58:49.35#ibcon#wrote, iclass 24, count 0 2006.285.19:58:49.35#ibcon#about to read 3, iclass 24, count 0 2006.285.19:58:49.37#ibcon#read 3, iclass 24, count 0 2006.285.19:58:49.37#ibcon#about to read 4, iclass 24, count 0 2006.285.19:58:49.37#ibcon#read 4, iclass 24, count 0 2006.285.19:58:49.37#ibcon#about to read 5, iclass 24, count 0 2006.285.19:58:49.37#ibcon#read 5, iclass 24, count 0 2006.285.19:58:49.37#ibcon#about to read 6, iclass 24, count 0 2006.285.19:58:49.37#ibcon#read 6, iclass 24, count 0 2006.285.19:58:49.37#ibcon#end of sib2, iclass 24, count 0 2006.285.19:58:49.37#ibcon#*mode == 0, iclass 24, count 0 2006.285.19:58:49.37#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.19:58:49.37#ibcon#[27=BW32\r\n] 2006.285.19:58:49.37#ibcon#*before write, iclass 24, count 0 2006.285.19:58:49.37#ibcon#enter sib2, iclass 24, count 0 2006.285.19:58:49.37#ibcon#flushed, iclass 24, count 0 2006.285.19:58:49.37#ibcon#about to write, iclass 24, count 0 2006.285.19:58:49.37#ibcon#wrote, iclass 24, count 0 2006.285.19:58:49.37#ibcon#about to read 3, iclass 24, count 0 2006.285.19:58:49.40#ibcon#read 3, iclass 24, count 0 2006.285.19:58:49.40#ibcon#about to read 4, iclass 24, count 0 2006.285.19:58:49.40#ibcon#read 4, iclass 24, count 0 2006.285.19:58:49.40#ibcon#about to read 5, iclass 24, count 0 2006.285.19:58:49.40#ibcon#read 5, iclass 24, count 0 2006.285.19:58:49.40#ibcon#about to read 6, iclass 24, count 0 2006.285.19:58:49.40#ibcon#read 6, iclass 24, count 0 2006.285.19:58:49.40#ibcon#end of sib2, iclass 24, count 0 2006.285.19:58:49.40#ibcon#*after write, iclass 24, count 0 2006.285.19:58:49.40#ibcon#*before return 0, iclass 24, count 0 2006.285.19:58:49.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:58:49.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.19:58:49.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.19:58:49.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.19:58:49.40$setupk4/ifdk4 2006.285.19:58:49.40$ifdk4/lo= 2006.285.19:58:49.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.19:58:49.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.19:58:49.40$ifdk4/patch= 2006.285.19:58:49.59$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.19:58:49.59$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.19:58:49.59$setupk4/!*+20s 2006.285.19:58:57.26#abcon#<5=/14 0.5 1.2 14.571001015.2\r\n> 2006.285.19:58:57.28#abcon#{5=INTERFACE CLEAR} 2006.285.19:58:57.34#abcon#[5=S1D000X0/0*\r\n] 2006.285.19:59:02.70$setupk4/"tpicd 2006.285.19:59:02.70$setupk4/echo=off 2006.285.19:59:02.70$setupk4/xlog=off 2006.285.19:59:02.70:!2006.285.20:01:01 2006.285.19:59:07.14#trakl#Source acquired 2006.285.19:59:09.14#flagr#flagr/antenna,acquired 2006.285.20:01:01.00:preob 2006.285.20:01:01.13/onsource/TRACKING 2006.285.20:01:01.13:!2006.285.20:01:11 2006.285.20:01:11.00:"tape 2006.285.20:01:11.00:"st=record 2006.285.20:01:11.00:data_valid=on 2006.285.20:01:11.00:midob 2006.285.20:01:12.13/onsource/TRACKING 2006.285.20:01:12.13/wx/14.58,1015.2,100 2006.285.20:01:12.23/cable/+6.5093E-03 2006.285.20:01:13.32/va/01,07,usb,yes,32,35 2006.285.20:01:13.32/va/02,06,usb,yes,32,32 2006.285.20:01:13.32/va/03,07,usb,yes,32,33 2006.285.20:01:13.32/va/04,06,usb,yes,33,34 2006.285.20:01:13.32/va/05,03,usb,yes,33,33 2006.285.20:01:13.32/va/06,04,usb,yes,29,29 2006.285.20:01:13.32/va/07,04,usb,yes,30,30 2006.285.20:01:13.32/va/08,03,usb,yes,31,37 2006.285.20:01:13.55/valo/01,524.99,yes,locked 2006.285.20:01:13.55/valo/02,534.99,yes,locked 2006.285.20:01:13.55/valo/03,564.99,yes,locked 2006.285.20:01:13.55/valo/04,624.99,yes,locked 2006.285.20:01:13.55/valo/05,734.99,yes,locked 2006.285.20:01:13.55/valo/06,814.99,yes,locked 2006.285.20:01:13.55/valo/07,864.99,yes,locked 2006.285.20:01:13.55/valo/08,884.99,yes,locked 2006.285.20:01:14.64/vb/01,04,usb,yes,30,28 2006.285.20:01:14.64/vb/02,05,usb,yes,28,28 2006.285.20:01:14.64/vb/03,04,usb,yes,29,32 2006.285.20:01:14.64/vb/04,05,usb,yes,29,28 2006.285.20:01:14.64/vb/05,04,usb,yes,26,28 2006.285.20:01:14.64/vb/06,03,usb,yes,37,33 2006.285.20:01:14.64/vb/07,04,usb,yes,30,30 2006.285.20:01:14.64/vb/08,04,usb,yes,27,31 2006.285.20:01:14.88/vblo/01,629.99,yes,locked 2006.285.20:01:14.88/vblo/02,634.99,yes,locked 2006.285.20:01:14.88/vblo/03,649.99,yes,locked 2006.285.20:01:14.88/vblo/04,679.99,yes,locked 2006.285.20:01:14.88/vblo/05,709.99,yes,locked 2006.285.20:01:14.88/vblo/06,719.99,yes,locked 2006.285.20:01:14.88/vblo/07,734.99,yes,locked 2006.285.20:01:14.88/vblo/08,744.99,yes,locked 2006.285.20:01:15.03/vabw/8 2006.285.20:01:15.18/vbbw/8 2006.285.20:01:15.27/xfe/off,on,12.0 2006.285.20:01:15.66/ifatt/23,28,28,28 2006.285.20:01:16.08/fmout-gps/S +2.73E-07 2006.285.20:01:16.10:!2006.285.20:02:01 2006.285.20:02:01.01:data_valid=off 2006.285.20:02:01.01:"et 2006.285.20:02:01.01:!+3s 2006.285.20:02:04.02:"tape 2006.285.20:02:04.02:postob 2006.285.20:02:04.08/cable/+6.5084E-03 2006.285.20:02:04.08/wx/14.55,1015.2,100 2006.285.20:02:05.08/fmout-gps/S +2.73E-07 2006.285.20:02:05.08:scan_name=285-2004,jd0610,120 2006.285.20:02:05.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.285.20:02:06.14#flagr#flagr/antenna,new-source 2006.285.20:02:06.14:checkk5 2006.285.20:02:06.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.20:02:06.95/chk_autoobs//k5ts2/ autoobs is running! 2006.285.20:02:07.37/chk_autoobs//k5ts3/ autoobs is running! 2006.285.20:02:07.74/chk_autoobs//k5ts4/ autoobs is running! 2006.285.20:02:08.09/chk_obsdata//k5ts1/T2852001??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.20:02:08.63/chk_obsdata//k5ts2/T2852001??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.20:02:09.25/chk_obsdata//k5ts3/T2852001??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.20:02:09.89/chk_obsdata//k5ts4/T2852001??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.20:02:10.89/k5log//k5ts1_log_newline 2006.285.20:02:11.63/k5log//k5ts2_log_newline 2006.285.20:02:12.38/k5log//k5ts3_log_newline 2006.285.20:02:13.26/k5log//k5ts4_log_newline 2006.285.20:02:13.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.20:02:13.29:setupk4=1 2006.285.20:02:13.29$setupk4/echo=on 2006.285.20:02:13.29$setupk4/pcalon 2006.285.20:02:13.29$pcalon/"no phase cal control is implemented here 2006.285.20:02:13.29$setupk4/"tpicd=stop 2006.285.20:02:13.29$setupk4/"rec=synch_on 2006.285.20:02:13.29$setupk4/"rec_mode=128 2006.285.20:02:13.29$setupk4/!* 2006.285.20:02:13.29$setupk4/recpk4 2006.285.20:02:13.29$recpk4/recpatch= 2006.285.20:02:13.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.20:02:13.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.20:02:13.29$setupk4/vck44 2006.285.20:02:13.29$vck44/valo=1,524.99 2006.285.20:02:13.29#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.20:02:13.29#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.20:02:13.29#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:13.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:02:13.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:02:13.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:02:13.29#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:02:13.29#ibcon#first serial, iclass 37, count 0 2006.285.20:02:13.29#ibcon#enter sib2, iclass 37, count 0 2006.285.20:02:13.29#ibcon#flushed, iclass 37, count 0 2006.285.20:02:13.29#ibcon#about to write, iclass 37, count 0 2006.285.20:02:13.29#ibcon#wrote, iclass 37, count 0 2006.285.20:02:13.29#ibcon#about to read 3, iclass 37, count 0 2006.285.20:02:13.31#ibcon#read 3, iclass 37, count 0 2006.285.20:02:13.31#ibcon#about to read 4, iclass 37, count 0 2006.285.20:02:13.31#ibcon#read 4, iclass 37, count 0 2006.285.20:02:13.31#ibcon#about to read 5, iclass 37, count 0 2006.285.20:02:13.31#ibcon#read 5, iclass 37, count 0 2006.285.20:02:13.31#ibcon#about to read 6, iclass 37, count 0 2006.285.20:02:13.31#ibcon#read 6, iclass 37, count 0 2006.285.20:02:13.31#ibcon#end of sib2, iclass 37, count 0 2006.285.20:02:13.31#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:02:13.31#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:02:13.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.20:02:13.31#ibcon#*before write, iclass 37, count 0 2006.285.20:02:13.31#ibcon#enter sib2, iclass 37, count 0 2006.285.20:02:13.31#ibcon#flushed, iclass 37, count 0 2006.285.20:02:13.31#ibcon#about to write, iclass 37, count 0 2006.285.20:02:13.31#ibcon#wrote, iclass 37, count 0 2006.285.20:02:13.31#ibcon#about to read 3, iclass 37, count 0 2006.285.20:02:13.36#ibcon#read 3, iclass 37, count 0 2006.285.20:02:13.36#ibcon#about to read 4, iclass 37, count 0 2006.285.20:02:13.36#ibcon#read 4, iclass 37, count 0 2006.285.20:02:13.36#ibcon#about to read 5, iclass 37, count 0 2006.285.20:02:13.36#ibcon#read 5, iclass 37, count 0 2006.285.20:02:13.36#ibcon#about to read 6, iclass 37, count 0 2006.285.20:02:13.36#ibcon#read 6, iclass 37, count 0 2006.285.20:02:13.36#ibcon#end of sib2, iclass 37, count 0 2006.285.20:02:13.36#ibcon#*after write, iclass 37, count 0 2006.285.20:02:13.36#ibcon#*before return 0, iclass 37, count 0 2006.285.20:02:13.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:02:13.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:02:13.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:02:13.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:02:13.36$vck44/va=1,7 2006.285.20:02:13.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.20:02:13.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.20:02:13.36#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:13.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:02:13.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:02:13.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:02:13.36#ibcon#enter wrdev, iclass 39, count 2 2006.285.20:02:13.36#ibcon#first serial, iclass 39, count 2 2006.285.20:02:13.36#ibcon#enter sib2, iclass 39, count 2 2006.285.20:02:13.36#ibcon#flushed, iclass 39, count 2 2006.285.20:02:13.36#ibcon#about to write, iclass 39, count 2 2006.285.20:02:13.36#ibcon#wrote, iclass 39, count 2 2006.285.20:02:13.36#ibcon#about to read 3, iclass 39, count 2 2006.285.20:02:13.38#ibcon#read 3, iclass 39, count 2 2006.285.20:02:13.38#ibcon#about to read 4, iclass 39, count 2 2006.285.20:02:13.38#ibcon#read 4, iclass 39, count 2 2006.285.20:02:13.38#ibcon#about to read 5, iclass 39, count 2 2006.285.20:02:13.38#ibcon#read 5, iclass 39, count 2 2006.285.20:02:13.38#ibcon#about to read 6, iclass 39, count 2 2006.285.20:02:13.38#ibcon#read 6, iclass 39, count 2 2006.285.20:02:13.38#ibcon#end of sib2, iclass 39, count 2 2006.285.20:02:13.38#ibcon#*mode == 0, iclass 39, count 2 2006.285.20:02:13.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.20:02:13.38#ibcon#[25=AT01-07\r\n] 2006.285.20:02:13.38#ibcon#*before write, iclass 39, count 2 2006.285.20:02:13.38#ibcon#enter sib2, iclass 39, count 2 2006.285.20:02:13.38#ibcon#flushed, iclass 39, count 2 2006.285.20:02:13.38#ibcon#about to write, iclass 39, count 2 2006.285.20:02:13.38#ibcon#wrote, iclass 39, count 2 2006.285.20:02:13.38#ibcon#about to read 3, iclass 39, count 2 2006.285.20:02:13.41#ibcon#read 3, iclass 39, count 2 2006.285.20:02:14.00#ibcon#about to read 4, iclass 39, count 2 2006.285.20:02:14.00#ibcon#read 4, iclass 39, count 2 2006.285.20:02:14.00#ibcon#about to read 5, iclass 39, count 2 2006.285.20:02:14.00#ibcon#read 5, iclass 39, count 2 2006.285.20:02:14.00#ibcon#about to read 6, iclass 39, count 2 2006.285.20:02:14.00#ibcon#read 6, iclass 39, count 2 2006.285.20:02:14.00#ibcon#end of sib2, iclass 39, count 2 2006.285.20:02:14.00#ibcon#*after write, iclass 39, count 2 2006.285.20:02:14.00#ibcon#*before return 0, iclass 39, count 2 2006.285.20:02:14.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:02:14.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:02:14.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.20:02:14.00#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:14.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:02:14.12#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:02:14.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:02:14.12#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:02:14.12#ibcon#first serial, iclass 39, count 0 2006.285.20:02:14.12#ibcon#enter sib2, iclass 39, count 0 2006.285.20:02:14.12#ibcon#flushed, iclass 39, count 0 2006.285.20:02:14.12#ibcon#about to write, iclass 39, count 0 2006.285.20:02:14.12#ibcon#wrote, iclass 39, count 0 2006.285.20:02:14.12#ibcon#about to read 3, iclass 39, count 0 2006.285.20:02:14.14#ibcon#read 3, iclass 39, count 0 2006.285.20:02:14.14#ibcon#about to read 4, iclass 39, count 0 2006.285.20:02:14.14#ibcon#read 4, iclass 39, count 0 2006.285.20:02:14.14#ibcon#about to read 5, iclass 39, count 0 2006.285.20:02:14.14#ibcon#read 5, iclass 39, count 0 2006.285.20:02:14.14#ibcon#about to read 6, iclass 39, count 0 2006.285.20:02:14.14#ibcon#read 6, iclass 39, count 0 2006.285.20:02:14.14#ibcon#end of sib2, iclass 39, count 0 2006.285.20:02:14.14#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:02:14.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:02:14.14#ibcon#[25=USB\r\n] 2006.285.20:02:14.14#ibcon#*before write, iclass 39, count 0 2006.285.20:02:14.14#ibcon#enter sib2, iclass 39, count 0 2006.285.20:02:14.14#ibcon#flushed, iclass 39, count 0 2006.285.20:02:14.14#ibcon#about to write, iclass 39, count 0 2006.285.20:02:14.14#ibcon#wrote, iclass 39, count 0 2006.285.20:02:14.14#ibcon#about to read 3, iclass 39, count 0 2006.285.20:02:14.17#ibcon#read 3, iclass 39, count 0 2006.285.20:02:14.17#ibcon#about to read 4, iclass 39, count 0 2006.285.20:02:14.17#ibcon#read 4, iclass 39, count 0 2006.285.20:02:14.17#ibcon#about to read 5, iclass 39, count 0 2006.285.20:02:14.17#ibcon#read 5, iclass 39, count 0 2006.285.20:02:14.17#ibcon#about to read 6, iclass 39, count 0 2006.285.20:02:14.17#ibcon#read 6, iclass 39, count 0 2006.285.20:02:14.17#ibcon#end of sib2, iclass 39, count 0 2006.285.20:02:14.17#ibcon#*after write, iclass 39, count 0 2006.285.20:02:14.17#ibcon#*before return 0, iclass 39, count 0 2006.285.20:02:14.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:02:14.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:02:14.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:02:14.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:02:14.17$vck44/valo=2,534.99 2006.285.20:02:14.17#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.20:02:14.17#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.20:02:14.17#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:14.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:02:14.17#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:02:14.17#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:02:14.17#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:02:14.17#ibcon#first serial, iclass 3, count 0 2006.285.20:02:14.17#ibcon#enter sib2, iclass 3, count 0 2006.285.20:02:14.17#ibcon#flushed, iclass 3, count 0 2006.285.20:02:14.17#ibcon#about to write, iclass 3, count 0 2006.285.20:02:14.17#ibcon#wrote, iclass 3, count 0 2006.285.20:02:14.17#ibcon#about to read 3, iclass 3, count 0 2006.285.20:02:14.19#ibcon#read 3, iclass 3, count 0 2006.285.20:02:14.19#ibcon#about to read 4, iclass 3, count 0 2006.285.20:02:14.19#ibcon#read 4, iclass 3, count 0 2006.285.20:02:14.19#ibcon#about to read 5, iclass 3, count 0 2006.285.20:02:14.19#ibcon#read 5, iclass 3, count 0 2006.285.20:02:14.19#ibcon#about to read 6, iclass 3, count 0 2006.285.20:02:14.19#ibcon#read 6, iclass 3, count 0 2006.285.20:02:14.19#ibcon#end of sib2, iclass 3, count 0 2006.285.20:02:14.19#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:02:14.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:02:14.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.20:02:14.19#ibcon#*before write, iclass 3, count 0 2006.285.20:02:14.19#ibcon#enter sib2, iclass 3, count 0 2006.285.20:02:14.19#ibcon#flushed, iclass 3, count 0 2006.285.20:02:14.19#ibcon#about to write, iclass 3, count 0 2006.285.20:02:14.19#ibcon#wrote, iclass 3, count 0 2006.285.20:02:14.19#ibcon#about to read 3, iclass 3, count 0 2006.285.20:02:14.23#ibcon#read 3, iclass 3, count 0 2006.285.20:02:14.23#ibcon#about to read 4, iclass 3, count 0 2006.285.20:02:14.23#ibcon#read 4, iclass 3, count 0 2006.285.20:02:14.23#ibcon#about to read 5, iclass 3, count 0 2006.285.20:02:14.23#ibcon#read 5, iclass 3, count 0 2006.285.20:02:14.23#ibcon#about to read 6, iclass 3, count 0 2006.285.20:02:14.23#ibcon#read 6, iclass 3, count 0 2006.285.20:02:14.23#ibcon#end of sib2, iclass 3, count 0 2006.285.20:02:14.23#ibcon#*after write, iclass 3, count 0 2006.285.20:02:14.23#ibcon#*before return 0, iclass 3, count 0 2006.285.20:02:14.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:02:14.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:02:14.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:02:14.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:02:14.23$vck44/va=2,6 2006.285.20:02:14.23#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.20:02:14.23#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.20:02:14.23#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:14.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:02:14.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:02:14.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:02:14.29#ibcon#enter wrdev, iclass 5, count 2 2006.285.20:02:14.29#ibcon#first serial, iclass 5, count 2 2006.285.20:02:14.29#ibcon#enter sib2, iclass 5, count 2 2006.285.20:02:14.29#ibcon#flushed, iclass 5, count 2 2006.285.20:02:14.29#ibcon#about to write, iclass 5, count 2 2006.285.20:02:14.29#ibcon#wrote, iclass 5, count 2 2006.285.20:02:14.29#ibcon#about to read 3, iclass 5, count 2 2006.285.20:02:14.31#ibcon#read 3, iclass 5, count 2 2006.285.20:02:14.31#ibcon#about to read 4, iclass 5, count 2 2006.285.20:02:14.31#ibcon#read 4, iclass 5, count 2 2006.285.20:02:14.31#ibcon#about to read 5, iclass 5, count 2 2006.285.20:02:14.31#ibcon#read 5, iclass 5, count 2 2006.285.20:02:14.31#ibcon#about to read 6, iclass 5, count 2 2006.285.20:02:14.31#ibcon#read 6, iclass 5, count 2 2006.285.20:02:14.31#ibcon#end of sib2, iclass 5, count 2 2006.285.20:02:14.31#ibcon#*mode == 0, iclass 5, count 2 2006.285.20:02:14.31#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.20:02:14.31#ibcon#[25=AT02-06\r\n] 2006.285.20:02:14.31#ibcon#*before write, iclass 5, count 2 2006.285.20:02:14.31#ibcon#enter sib2, iclass 5, count 2 2006.285.20:02:14.31#ibcon#flushed, iclass 5, count 2 2006.285.20:02:14.31#ibcon#about to write, iclass 5, count 2 2006.285.20:02:14.31#ibcon#wrote, iclass 5, count 2 2006.285.20:02:14.31#ibcon#about to read 3, iclass 5, count 2 2006.285.20:02:14.34#ibcon#read 3, iclass 5, count 2 2006.285.20:02:14.34#ibcon#about to read 4, iclass 5, count 2 2006.285.20:02:14.34#ibcon#read 4, iclass 5, count 2 2006.285.20:02:14.34#ibcon#about to read 5, iclass 5, count 2 2006.285.20:02:14.34#ibcon#read 5, iclass 5, count 2 2006.285.20:02:14.34#ibcon#about to read 6, iclass 5, count 2 2006.285.20:02:14.34#ibcon#read 6, iclass 5, count 2 2006.285.20:02:14.34#ibcon#end of sib2, iclass 5, count 2 2006.285.20:02:14.34#ibcon#*after write, iclass 5, count 2 2006.285.20:02:14.34#ibcon#*before return 0, iclass 5, count 2 2006.285.20:02:14.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:02:14.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:02:14.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.20:02:14.34#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:14.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:02:14.46#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:02:14.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:02:14.50#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:02:14.50#ibcon#first serial, iclass 5, count 0 2006.285.20:02:14.50#ibcon#enter sib2, iclass 5, count 0 2006.285.20:02:14.50#ibcon#flushed, iclass 5, count 0 2006.285.20:02:14.50#ibcon#about to write, iclass 5, count 0 2006.285.20:02:14.50#ibcon#wrote, iclass 5, count 0 2006.285.20:02:14.50#ibcon#about to read 3, iclass 5, count 0 2006.285.20:02:14.52#ibcon#read 3, iclass 5, count 0 2006.285.20:02:14.52#ibcon#about to read 4, iclass 5, count 0 2006.285.20:02:14.52#ibcon#read 4, iclass 5, count 0 2006.285.20:02:14.52#ibcon#about to read 5, iclass 5, count 0 2006.285.20:02:14.52#ibcon#read 5, iclass 5, count 0 2006.285.20:02:14.52#ibcon#about to read 6, iclass 5, count 0 2006.285.20:02:14.52#ibcon#read 6, iclass 5, count 0 2006.285.20:02:14.52#ibcon#end of sib2, iclass 5, count 0 2006.285.20:02:14.52#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:02:14.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:02:14.52#ibcon#[25=USB\r\n] 2006.285.20:02:14.52#ibcon#*before write, iclass 5, count 0 2006.285.20:02:14.52#ibcon#enter sib2, iclass 5, count 0 2006.285.20:02:14.52#ibcon#flushed, iclass 5, count 0 2006.285.20:02:14.52#ibcon#about to write, iclass 5, count 0 2006.285.20:02:14.52#ibcon#wrote, iclass 5, count 0 2006.285.20:02:14.52#ibcon#about to read 3, iclass 5, count 0 2006.285.20:02:14.55#ibcon#read 3, iclass 5, count 0 2006.285.20:02:14.55#ibcon#about to read 4, iclass 5, count 0 2006.285.20:02:14.55#ibcon#read 4, iclass 5, count 0 2006.285.20:02:14.55#ibcon#about to read 5, iclass 5, count 0 2006.285.20:02:14.55#ibcon#read 5, iclass 5, count 0 2006.285.20:02:14.55#ibcon#about to read 6, iclass 5, count 0 2006.285.20:02:14.55#ibcon#read 6, iclass 5, count 0 2006.285.20:02:14.55#ibcon#end of sib2, iclass 5, count 0 2006.285.20:02:14.55#ibcon#*after write, iclass 5, count 0 2006.285.20:02:14.55#ibcon#*before return 0, iclass 5, count 0 2006.285.20:02:14.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:02:14.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:02:14.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:02:14.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:02:14.55$vck44/valo=3,564.99 2006.285.20:02:14.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.20:02:14.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.20:02:14.55#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:14.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:02:14.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:02:14.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:02:14.55#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:02:14.55#ibcon#first serial, iclass 7, count 0 2006.285.20:02:14.55#ibcon#enter sib2, iclass 7, count 0 2006.285.20:02:14.55#ibcon#flushed, iclass 7, count 0 2006.285.20:02:14.55#ibcon#about to write, iclass 7, count 0 2006.285.20:02:14.55#ibcon#wrote, iclass 7, count 0 2006.285.20:02:14.55#ibcon#about to read 3, iclass 7, count 0 2006.285.20:02:14.57#ibcon#read 3, iclass 7, count 0 2006.285.20:02:14.57#ibcon#about to read 4, iclass 7, count 0 2006.285.20:02:14.57#ibcon#read 4, iclass 7, count 0 2006.285.20:02:14.57#ibcon#about to read 5, iclass 7, count 0 2006.285.20:02:14.57#ibcon#read 5, iclass 7, count 0 2006.285.20:02:14.57#ibcon#about to read 6, iclass 7, count 0 2006.285.20:02:14.57#ibcon#read 6, iclass 7, count 0 2006.285.20:02:14.57#ibcon#end of sib2, iclass 7, count 0 2006.285.20:02:14.57#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:02:14.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:02:14.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.20:02:14.57#ibcon#*before write, iclass 7, count 0 2006.285.20:02:14.57#ibcon#enter sib2, iclass 7, count 0 2006.285.20:02:14.57#ibcon#flushed, iclass 7, count 0 2006.285.20:02:14.57#ibcon#about to write, iclass 7, count 0 2006.285.20:02:14.57#ibcon#wrote, iclass 7, count 0 2006.285.20:02:14.57#ibcon#about to read 3, iclass 7, count 0 2006.285.20:02:14.61#ibcon#read 3, iclass 7, count 0 2006.285.20:02:14.61#ibcon#about to read 4, iclass 7, count 0 2006.285.20:02:14.61#ibcon#read 4, iclass 7, count 0 2006.285.20:02:14.61#ibcon#about to read 5, iclass 7, count 0 2006.285.20:02:14.61#ibcon#read 5, iclass 7, count 0 2006.285.20:02:14.61#ibcon#about to read 6, iclass 7, count 0 2006.285.20:02:14.61#ibcon#read 6, iclass 7, count 0 2006.285.20:02:14.61#ibcon#end of sib2, iclass 7, count 0 2006.285.20:02:14.61#ibcon#*after write, iclass 7, count 0 2006.285.20:02:14.61#ibcon#*before return 0, iclass 7, count 0 2006.285.20:02:14.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:02:14.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:02:14.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:02:14.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:02:14.61$vck44/va=3,7 2006.285.20:02:14.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.20:02:14.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.20:02:14.61#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:14.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:02:14.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:02:14.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:02:14.67#ibcon#enter wrdev, iclass 11, count 2 2006.285.20:02:14.67#ibcon#first serial, iclass 11, count 2 2006.285.20:02:14.67#ibcon#enter sib2, iclass 11, count 2 2006.285.20:02:14.67#ibcon#flushed, iclass 11, count 2 2006.285.20:02:14.67#ibcon#about to write, iclass 11, count 2 2006.285.20:02:14.67#ibcon#wrote, iclass 11, count 2 2006.285.20:02:14.67#ibcon#about to read 3, iclass 11, count 2 2006.285.20:02:14.69#ibcon#read 3, iclass 11, count 2 2006.285.20:02:14.69#ibcon#about to read 4, iclass 11, count 2 2006.285.20:02:14.69#ibcon#read 4, iclass 11, count 2 2006.285.20:02:14.69#ibcon#about to read 5, iclass 11, count 2 2006.285.20:02:14.69#ibcon#read 5, iclass 11, count 2 2006.285.20:02:14.69#ibcon#about to read 6, iclass 11, count 2 2006.285.20:02:14.69#ibcon#read 6, iclass 11, count 2 2006.285.20:02:14.69#ibcon#end of sib2, iclass 11, count 2 2006.285.20:02:14.69#ibcon#*mode == 0, iclass 11, count 2 2006.285.20:02:14.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.20:02:14.69#ibcon#[25=AT03-07\r\n] 2006.285.20:02:14.69#ibcon#*before write, iclass 11, count 2 2006.285.20:02:14.69#ibcon#enter sib2, iclass 11, count 2 2006.285.20:02:14.69#ibcon#flushed, iclass 11, count 2 2006.285.20:02:14.69#ibcon#about to write, iclass 11, count 2 2006.285.20:02:14.69#ibcon#wrote, iclass 11, count 2 2006.285.20:02:14.69#ibcon#about to read 3, iclass 11, count 2 2006.285.20:02:14.72#ibcon#read 3, iclass 11, count 2 2006.285.20:02:14.72#ibcon#about to read 4, iclass 11, count 2 2006.285.20:02:14.72#ibcon#read 4, iclass 11, count 2 2006.285.20:02:14.72#ibcon#about to read 5, iclass 11, count 2 2006.285.20:02:14.72#ibcon#read 5, iclass 11, count 2 2006.285.20:02:14.72#ibcon#about to read 6, iclass 11, count 2 2006.285.20:02:14.72#ibcon#read 6, iclass 11, count 2 2006.285.20:02:14.72#ibcon#end of sib2, iclass 11, count 2 2006.285.20:02:14.72#ibcon#*after write, iclass 11, count 2 2006.285.20:02:14.72#ibcon#*before return 0, iclass 11, count 2 2006.285.20:02:14.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:02:14.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:02:14.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.20:02:14.72#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:14.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:02:14.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:02:14.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:02:14.84#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:02:14.84#ibcon#first serial, iclass 11, count 0 2006.285.20:02:14.84#ibcon#enter sib2, iclass 11, count 0 2006.285.20:02:14.84#ibcon#flushed, iclass 11, count 0 2006.285.20:02:14.84#ibcon#about to write, iclass 11, count 0 2006.285.20:02:14.84#ibcon#wrote, iclass 11, count 0 2006.285.20:02:14.84#ibcon#about to read 3, iclass 11, count 0 2006.285.20:02:14.86#ibcon#read 3, iclass 11, count 0 2006.285.20:02:14.86#ibcon#about to read 4, iclass 11, count 0 2006.285.20:02:14.86#ibcon#read 4, iclass 11, count 0 2006.285.20:02:14.86#ibcon#about to read 5, iclass 11, count 0 2006.285.20:02:14.86#ibcon#read 5, iclass 11, count 0 2006.285.20:02:14.86#ibcon#about to read 6, iclass 11, count 0 2006.285.20:02:14.86#ibcon#read 6, iclass 11, count 0 2006.285.20:02:14.86#ibcon#end of sib2, iclass 11, count 0 2006.285.20:02:14.86#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:02:14.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:02:14.86#ibcon#[25=USB\r\n] 2006.285.20:02:14.86#ibcon#*before write, iclass 11, count 0 2006.285.20:02:14.86#ibcon#enter sib2, iclass 11, count 0 2006.285.20:02:14.86#ibcon#flushed, iclass 11, count 0 2006.285.20:02:14.86#ibcon#about to write, iclass 11, count 0 2006.285.20:02:14.86#ibcon#wrote, iclass 11, count 0 2006.285.20:02:14.86#ibcon#about to read 3, iclass 11, count 0 2006.285.20:02:14.89#ibcon#read 3, iclass 11, count 0 2006.285.20:02:14.89#ibcon#about to read 4, iclass 11, count 0 2006.285.20:02:14.89#ibcon#read 4, iclass 11, count 0 2006.285.20:02:14.89#ibcon#about to read 5, iclass 11, count 0 2006.285.20:02:14.89#ibcon#read 5, iclass 11, count 0 2006.285.20:02:14.89#ibcon#about to read 6, iclass 11, count 0 2006.285.20:02:14.89#ibcon#read 6, iclass 11, count 0 2006.285.20:02:14.89#ibcon#end of sib2, iclass 11, count 0 2006.285.20:02:14.89#ibcon#*after write, iclass 11, count 0 2006.285.20:02:14.89#ibcon#*before return 0, iclass 11, count 0 2006.285.20:02:14.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:02:14.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:02:14.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:02:14.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:02:14.89$vck44/valo=4,624.99 2006.285.20:02:14.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.20:02:14.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.20:02:14.89#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:14.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:02:14.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:02:14.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:02:14.89#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:02:14.89#ibcon#first serial, iclass 13, count 0 2006.285.20:02:14.89#ibcon#enter sib2, iclass 13, count 0 2006.285.20:02:14.89#ibcon#flushed, iclass 13, count 0 2006.285.20:02:14.89#ibcon#about to write, iclass 13, count 0 2006.285.20:02:14.89#ibcon#wrote, iclass 13, count 0 2006.285.20:02:14.89#ibcon#about to read 3, iclass 13, count 0 2006.285.20:02:14.91#ibcon#read 3, iclass 13, count 0 2006.285.20:02:14.91#ibcon#about to read 4, iclass 13, count 0 2006.285.20:02:14.91#ibcon#read 4, iclass 13, count 0 2006.285.20:02:14.91#ibcon#about to read 5, iclass 13, count 0 2006.285.20:02:14.91#ibcon#read 5, iclass 13, count 0 2006.285.20:02:14.91#ibcon#about to read 6, iclass 13, count 0 2006.285.20:02:14.91#ibcon#read 6, iclass 13, count 0 2006.285.20:02:14.91#ibcon#end of sib2, iclass 13, count 0 2006.285.20:02:14.91#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:02:14.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:02:14.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.20:02:14.91#ibcon#*before write, iclass 13, count 0 2006.285.20:02:14.91#ibcon#enter sib2, iclass 13, count 0 2006.285.20:02:14.91#ibcon#flushed, iclass 13, count 0 2006.285.20:02:14.91#ibcon#about to write, iclass 13, count 0 2006.285.20:02:14.91#ibcon#wrote, iclass 13, count 0 2006.285.20:02:14.91#ibcon#about to read 3, iclass 13, count 0 2006.285.20:02:14.95#ibcon#read 3, iclass 13, count 0 2006.285.20:02:14.95#ibcon#about to read 4, iclass 13, count 0 2006.285.20:02:14.95#ibcon#read 4, iclass 13, count 0 2006.285.20:02:14.95#ibcon#about to read 5, iclass 13, count 0 2006.285.20:02:14.95#ibcon#read 5, iclass 13, count 0 2006.285.20:02:14.95#ibcon#about to read 6, iclass 13, count 0 2006.285.20:02:14.95#ibcon#read 6, iclass 13, count 0 2006.285.20:02:14.95#ibcon#end of sib2, iclass 13, count 0 2006.285.20:02:14.95#ibcon#*after write, iclass 13, count 0 2006.285.20:02:14.95#ibcon#*before return 0, iclass 13, count 0 2006.285.20:02:14.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:02:14.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:02:14.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:02:14.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:02:14.95$vck44/va=4,6 2006.285.20:02:14.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.20:02:14.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.20:02:14.95#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:14.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:02:15.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:02:15.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:02:15.01#ibcon#enter wrdev, iclass 15, count 2 2006.285.20:02:15.01#ibcon#first serial, iclass 15, count 2 2006.285.20:02:15.01#ibcon#enter sib2, iclass 15, count 2 2006.285.20:02:15.01#ibcon#flushed, iclass 15, count 2 2006.285.20:02:15.01#ibcon#about to write, iclass 15, count 2 2006.285.20:02:15.01#ibcon#wrote, iclass 15, count 2 2006.285.20:02:15.01#ibcon#about to read 3, iclass 15, count 2 2006.285.20:02:15.03#ibcon#read 3, iclass 15, count 2 2006.285.20:02:15.03#ibcon#about to read 4, iclass 15, count 2 2006.285.20:02:15.03#ibcon#read 4, iclass 15, count 2 2006.285.20:02:15.03#ibcon#about to read 5, iclass 15, count 2 2006.285.20:02:15.03#ibcon#read 5, iclass 15, count 2 2006.285.20:02:15.03#ibcon#about to read 6, iclass 15, count 2 2006.285.20:02:15.03#ibcon#read 6, iclass 15, count 2 2006.285.20:02:15.03#ibcon#end of sib2, iclass 15, count 2 2006.285.20:02:15.03#ibcon#*mode == 0, iclass 15, count 2 2006.285.20:02:15.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.20:02:15.03#ibcon#[25=AT04-06\r\n] 2006.285.20:02:15.03#ibcon#*before write, iclass 15, count 2 2006.285.20:02:15.03#ibcon#enter sib2, iclass 15, count 2 2006.285.20:02:15.03#ibcon#flushed, iclass 15, count 2 2006.285.20:02:15.03#ibcon#about to write, iclass 15, count 2 2006.285.20:02:15.03#ibcon#wrote, iclass 15, count 2 2006.285.20:02:15.03#ibcon#about to read 3, iclass 15, count 2 2006.285.20:02:15.06#ibcon#read 3, iclass 15, count 2 2006.285.20:02:15.06#ibcon#about to read 4, iclass 15, count 2 2006.285.20:02:15.06#ibcon#read 4, iclass 15, count 2 2006.285.20:02:15.06#ibcon#about to read 5, iclass 15, count 2 2006.285.20:02:15.06#ibcon#read 5, iclass 15, count 2 2006.285.20:02:15.06#ibcon#about to read 6, iclass 15, count 2 2006.285.20:02:15.06#ibcon#read 6, iclass 15, count 2 2006.285.20:02:15.06#ibcon#end of sib2, iclass 15, count 2 2006.285.20:02:15.06#ibcon#*after write, iclass 15, count 2 2006.285.20:02:15.06#ibcon#*before return 0, iclass 15, count 2 2006.285.20:02:15.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:02:15.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:02:15.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.20:02:15.06#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:15.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:02:15.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:02:15.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:02:15.18#ibcon#enter wrdev, iclass 15, count 0 2006.285.20:02:15.18#ibcon#first serial, iclass 15, count 0 2006.285.20:02:15.18#ibcon#enter sib2, iclass 15, count 0 2006.285.20:02:15.18#ibcon#flushed, iclass 15, count 0 2006.285.20:02:15.18#ibcon#about to write, iclass 15, count 0 2006.285.20:02:15.18#ibcon#wrote, iclass 15, count 0 2006.285.20:02:15.18#ibcon#about to read 3, iclass 15, count 0 2006.285.20:02:15.20#ibcon#read 3, iclass 15, count 0 2006.285.20:02:15.20#ibcon#about to read 4, iclass 15, count 0 2006.285.20:02:15.20#ibcon#read 4, iclass 15, count 0 2006.285.20:02:15.20#ibcon#about to read 5, iclass 15, count 0 2006.285.20:02:15.20#ibcon#read 5, iclass 15, count 0 2006.285.20:02:15.20#ibcon#about to read 6, iclass 15, count 0 2006.285.20:02:15.20#ibcon#read 6, iclass 15, count 0 2006.285.20:02:15.20#ibcon#end of sib2, iclass 15, count 0 2006.285.20:02:15.20#ibcon#*mode == 0, iclass 15, count 0 2006.285.20:02:15.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.20:02:15.20#ibcon#[25=USB\r\n] 2006.285.20:02:15.20#ibcon#*before write, iclass 15, count 0 2006.285.20:02:15.20#ibcon#enter sib2, iclass 15, count 0 2006.285.20:02:15.20#ibcon#flushed, iclass 15, count 0 2006.285.20:02:15.20#ibcon#about to write, iclass 15, count 0 2006.285.20:02:15.20#ibcon#wrote, iclass 15, count 0 2006.285.20:02:15.20#ibcon#about to read 3, iclass 15, count 0 2006.285.20:02:15.23#ibcon#read 3, iclass 15, count 0 2006.285.20:02:15.23#ibcon#about to read 4, iclass 15, count 0 2006.285.20:02:15.23#ibcon#read 4, iclass 15, count 0 2006.285.20:02:15.23#ibcon#about to read 5, iclass 15, count 0 2006.285.20:02:15.23#ibcon#read 5, iclass 15, count 0 2006.285.20:02:15.23#ibcon#about to read 6, iclass 15, count 0 2006.285.20:02:15.23#ibcon#read 6, iclass 15, count 0 2006.285.20:02:15.23#ibcon#end of sib2, iclass 15, count 0 2006.285.20:02:15.23#ibcon#*after write, iclass 15, count 0 2006.285.20:02:15.23#ibcon#*before return 0, iclass 15, count 0 2006.285.20:02:15.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:02:15.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:02:15.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.20:02:15.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.20:02:15.23$vck44/valo=5,734.99 2006.285.20:02:15.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.20:02:15.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.20:02:15.23#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:15.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:02:15.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:02:15.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:02:15.23#ibcon#enter wrdev, iclass 17, count 0 2006.285.20:02:15.23#ibcon#first serial, iclass 17, count 0 2006.285.20:02:15.23#ibcon#enter sib2, iclass 17, count 0 2006.285.20:02:15.23#ibcon#flushed, iclass 17, count 0 2006.285.20:02:15.23#ibcon#about to write, iclass 17, count 0 2006.285.20:02:15.23#ibcon#wrote, iclass 17, count 0 2006.285.20:02:15.23#ibcon#about to read 3, iclass 17, count 0 2006.285.20:02:15.25#ibcon#read 3, iclass 17, count 0 2006.285.20:02:15.25#ibcon#about to read 4, iclass 17, count 0 2006.285.20:02:15.25#ibcon#read 4, iclass 17, count 0 2006.285.20:02:15.25#ibcon#about to read 5, iclass 17, count 0 2006.285.20:02:15.25#ibcon#read 5, iclass 17, count 0 2006.285.20:02:15.25#ibcon#about to read 6, iclass 17, count 0 2006.285.20:02:15.25#ibcon#read 6, iclass 17, count 0 2006.285.20:02:15.25#ibcon#end of sib2, iclass 17, count 0 2006.285.20:02:15.25#ibcon#*mode == 0, iclass 17, count 0 2006.285.20:02:15.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.20:02:15.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.20:02:15.25#ibcon#*before write, iclass 17, count 0 2006.285.20:02:15.25#ibcon#enter sib2, iclass 17, count 0 2006.285.20:02:15.25#ibcon#flushed, iclass 17, count 0 2006.285.20:02:15.25#ibcon#about to write, iclass 17, count 0 2006.285.20:02:15.25#ibcon#wrote, iclass 17, count 0 2006.285.20:02:15.25#ibcon#about to read 3, iclass 17, count 0 2006.285.20:02:15.29#ibcon#read 3, iclass 17, count 0 2006.285.20:02:15.29#ibcon#about to read 4, iclass 17, count 0 2006.285.20:02:15.29#ibcon#read 4, iclass 17, count 0 2006.285.20:02:15.29#ibcon#about to read 5, iclass 17, count 0 2006.285.20:02:15.29#ibcon#read 5, iclass 17, count 0 2006.285.20:02:15.29#ibcon#about to read 6, iclass 17, count 0 2006.285.20:02:15.29#ibcon#read 6, iclass 17, count 0 2006.285.20:02:15.29#ibcon#end of sib2, iclass 17, count 0 2006.285.20:02:15.29#ibcon#*after write, iclass 17, count 0 2006.285.20:02:15.29#ibcon#*before return 0, iclass 17, count 0 2006.285.20:02:15.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:02:15.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:02:15.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.20:02:15.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.20:02:15.29$vck44/va=5,3 2006.285.20:02:15.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.20:02:15.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.20:02:15.29#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:15.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:02:15.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:02:15.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:02:15.35#ibcon#enter wrdev, iclass 19, count 2 2006.285.20:02:15.35#ibcon#first serial, iclass 19, count 2 2006.285.20:02:15.35#ibcon#enter sib2, iclass 19, count 2 2006.285.20:02:15.35#ibcon#flushed, iclass 19, count 2 2006.285.20:02:15.35#ibcon#about to write, iclass 19, count 2 2006.285.20:02:15.35#ibcon#wrote, iclass 19, count 2 2006.285.20:02:15.35#ibcon#about to read 3, iclass 19, count 2 2006.285.20:02:15.37#ibcon#read 3, iclass 19, count 2 2006.285.20:02:15.37#ibcon#about to read 4, iclass 19, count 2 2006.285.20:02:15.37#ibcon#read 4, iclass 19, count 2 2006.285.20:02:15.37#ibcon#about to read 5, iclass 19, count 2 2006.285.20:02:15.37#ibcon#read 5, iclass 19, count 2 2006.285.20:02:15.37#ibcon#about to read 6, iclass 19, count 2 2006.285.20:02:15.37#ibcon#read 6, iclass 19, count 2 2006.285.20:02:15.37#ibcon#end of sib2, iclass 19, count 2 2006.285.20:02:15.37#ibcon#*mode == 0, iclass 19, count 2 2006.285.20:02:15.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.20:02:15.37#ibcon#[25=AT05-03\r\n] 2006.285.20:02:15.37#ibcon#*before write, iclass 19, count 2 2006.285.20:02:15.37#ibcon#enter sib2, iclass 19, count 2 2006.285.20:02:15.37#ibcon#flushed, iclass 19, count 2 2006.285.20:02:15.37#ibcon#about to write, iclass 19, count 2 2006.285.20:02:15.37#ibcon#wrote, iclass 19, count 2 2006.285.20:02:15.37#ibcon#about to read 3, iclass 19, count 2 2006.285.20:02:15.40#ibcon#read 3, iclass 19, count 2 2006.285.20:02:15.40#ibcon#about to read 4, iclass 19, count 2 2006.285.20:02:15.40#ibcon#read 4, iclass 19, count 2 2006.285.20:02:15.40#ibcon#about to read 5, iclass 19, count 2 2006.285.20:02:15.40#ibcon#read 5, iclass 19, count 2 2006.285.20:02:15.40#ibcon#about to read 6, iclass 19, count 2 2006.285.20:02:15.40#ibcon#read 6, iclass 19, count 2 2006.285.20:02:15.40#ibcon#end of sib2, iclass 19, count 2 2006.285.20:02:15.40#ibcon#*after write, iclass 19, count 2 2006.285.20:02:15.40#ibcon#*before return 0, iclass 19, count 2 2006.285.20:02:15.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:02:15.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:02:15.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.20:02:15.40#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:15.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:02:15.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:02:15.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:02:15.52#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:02:15.52#ibcon#first serial, iclass 19, count 0 2006.285.20:02:15.52#ibcon#enter sib2, iclass 19, count 0 2006.285.20:02:15.52#ibcon#flushed, iclass 19, count 0 2006.285.20:02:15.52#ibcon#about to write, iclass 19, count 0 2006.285.20:02:15.52#ibcon#wrote, iclass 19, count 0 2006.285.20:02:15.52#ibcon#about to read 3, iclass 19, count 0 2006.285.20:02:15.54#ibcon#read 3, iclass 19, count 0 2006.285.20:02:15.54#ibcon#about to read 4, iclass 19, count 0 2006.285.20:02:15.54#ibcon#read 4, iclass 19, count 0 2006.285.20:02:15.54#ibcon#about to read 5, iclass 19, count 0 2006.285.20:02:15.54#ibcon#read 5, iclass 19, count 0 2006.285.20:02:15.54#ibcon#about to read 6, iclass 19, count 0 2006.285.20:02:15.54#ibcon#read 6, iclass 19, count 0 2006.285.20:02:15.62#ibcon#end of sib2, iclass 19, count 0 2006.285.20:02:15.62#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:02:15.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:02:15.62#ibcon#[25=USB\r\n] 2006.285.20:02:15.62#ibcon#*before write, iclass 19, count 0 2006.285.20:02:15.62#ibcon#enter sib2, iclass 19, count 0 2006.285.20:02:15.62#ibcon#flushed, iclass 19, count 0 2006.285.20:02:15.62#ibcon#about to write, iclass 19, count 0 2006.285.20:02:15.62#ibcon#wrote, iclass 19, count 0 2006.285.20:02:15.62#ibcon#about to read 3, iclass 19, count 0 2006.285.20:02:15.65#ibcon#read 3, iclass 19, count 0 2006.285.20:02:15.65#ibcon#about to read 4, iclass 19, count 0 2006.285.20:02:15.65#ibcon#read 4, iclass 19, count 0 2006.285.20:02:15.65#ibcon#about to read 5, iclass 19, count 0 2006.285.20:02:15.65#ibcon#read 5, iclass 19, count 0 2006.285.20:02:15.65#ibcon#about to read 6, iclass 19, count 0 2006.285.20:02:15.65#ibcon#read 6, iclass 19, count 0 2006.285.20:02:15.65#ibcon#end of sib2, iclass 19, count 0 2006.285.20:02:15.65#ibcon#*after write, iclass 19, count 0 2006.285.20:02:15.65#ibcon#*before return 0, iclass 19, count 0 2006.285.20:02:15.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:02:15.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:02:15.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:02:15.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:02:15.65$vck44/valo=6,814.99 2006.285.20:02:15.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.20:02:15.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.20:02:15.65#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:15.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:02:15.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:02:15.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:02:15.65#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:02:15.65#ibcon#first serial, iclass 21, count 0 2006.285.20:02:15.65#ibcon#enter sib2, iclass 21, count 0 2006.285.20:02:15.65#ibcon#flushed, iclass 21, count 0 2006.285.20:02:15.65#ibcon#about to write, iclass 21, count 0 2006.285.20:02:15.65#ibcon#wrote, iclass 21, count 0 2006.285.20:02:15.65#ibcon#about to read 3, iclass 21, count 0 2006.285.20:02:15.67#ibcon#read 3, iclass 21, count 0 2006.285.20:02:15.67#ibcon#about to read 4, iclass 21, count 0 2006.285.20:02:15.67#ibcon#read 4, iclass 21, count 0 2006.285.20:02:15.67#ibcon#about to read 5, iclass 21, count 0 2006.285.20:02:15.67#ibcon#read 5, iclass 21, count 0 2006.285.20:02:15.67#ibcon#about to read 6, iclass 21, count 0 2006.285.20:02:15.67#ibcon#read 6, iclass 21, count 0 2006.285.20:02:15.67#ibcon#end of sib2, iclass 21, count 0 2006.285.20:02:15.67#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:02:15.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:02:15.67#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.20:02:15.67#ibcon#*before write, iclass 21, count 0 2006.285.20:02:15.67#ibcon#enter sib2, iclass 21, count 0 2006.285.20:02:15.67#ibcon#flushed, iclass 21, count 0 2006.285.20:02:15.67#ibcon#about to write, iclass 21, count 0 2006.285.20:02:15.67#ibcon#wrote, iclass 21, count 0 2006.285.20:02:15.67#ibcon#about to read 3, iclass 21, count 0 2006.285.20:02:15.71#ibcon#read 3, iclass 21, count 0 2006.285.20:02:15.71#ibcon#about to read 4, iclass 21, count 0 2006.285.20:02:15.71#ibcon#read 4, iclass 21, count 0 2006.285.20:02:15.71#ibcon#about to read 5, iclass 21, count 0 2006.285.20:02:15.71#ibcon#read 5, iclass 21, count 0 2006.285.20:02:15.71#ibcon#about to read 6, iclass 21, count 0 2006.285.20:02:15.71#ibcon#read 6, iclass 21, count 0 2006.285.20:02:15.71#ibcon#end of sib2, iclass 21, count 0 2006.285.20:02:15.71#ibcon#*after write, iclass 21, count 0 2006.285.20:02:15.71#ibcon#*before return 0, iclass 21, count 0 2006.285.20:02:15.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:02:15.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:02:15.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:02:15.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:02:15.71$vck44/va=6,4 2006.285.20:02:15.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.20:02:15.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.20:02:15.71#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:15.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:02:15.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:02:15.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:02:15.77#ibcon#enter wrdev, iclass 23, count 2 2006.285.20:02:15.77#ibcon#first serial, iclass 23, count 2 2006.285.20:02:15.77#ibcon#enter sib2, iclass 23, count 2 2006.285.20:02:15.77#ibcon#flushed, iclass 23, count 2 2006.285.20:02:15.77#ibcon#about to write, iclass 23, count 2 2006.285.20:02:15.77#ibcon#wrote, iclass 23, count 2 2006.285.20:02:15.77#ibcon#about to read 3, iclass 23, count 2 2006.285.20:02:15.79#ibcon#read 3, iclass 23, count 2 2006.285.20:02:15.79#ibcon#about to read 4, iclass 23, count 2 2006.285.20:02:15.79#ibcon#read 4, iclass 23, count 2 2006.285.20:02:15.79#ibcon#about to read 5, iclass 23, count 2 2006.285.20:02:15.79#ibcon#read 5, iclass 23, count 2 2006.285.20:02:15.79#ibcon#about to read 6, iclass 23, count 2 2006.285.20:02:15.79#ibcon#read 6, iclass 23, count 2 2006.285.20:02:15.79#ibcon#end of sib2, iclass 23, count 2 2006.285.20:02:15.79#ibcon#*mode == 0, iclass 23, count 2 2006.285.20:02:15.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.20:02:15.79#ibcon#[25=AT06-04\r\n] 2006.285.20:02:15.79#ibcon#*before write, iclass 23, count 2 2006.285.20:02:15.79#ibcon#enter sib2, iclass 23, count 2 2006.285.20:02:15.79#ibcon#flushed, iclass 23, count 2 2006.285.20:02:15.79#ibcon#about to write, iclass 23, count 2 2006.285.20:02:15.79#ibcon#wrote, iclass 23, count 2 2006.285.20:02:15.79#ibcon#about to read 3, iclass 23, count 2 2006.285.20:02:15.82#ibcon#read 3, iclass 23, count 2 2006.285.20:02:15.82#ibcon#about to read 4, iclass 23, count 2 2006.285.20:02:15.82#ibcon#read 4, iclass 23, count 2 2006.285.20:02:15.82#ibcon#about to read 5, iclass 23, count 2 2006.285.20:02:15.82#ibcon#read 5, iclass 23, count 2 2006.285.20:02:15.82#ibcon#about to read 6, iclass 23, count 2 2006.285.20:02:15.82#ibcon#read 6, iclass 23, count 2 2006.285.20:02:15.82#ibcon#end of sib2, iclass 23, count 2 2006.285.20:02:15.82#ibcon#*after write, iclass 23, count 2 2006.285.20:02:15.82#ibcon#*before return 0, iclass 23, count 2 2006.285.20:02:15.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:02:15.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:02:15.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.20:02:15.82#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:15.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:02:15.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:02:15.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:02:15.94#ibcon#enter wrdev, iclass 23, count 0 2006.285.20:02:15.94#ibcon#first serial, iclass 23, count 0 2006.285.20:02:15.94#ibcon#enter sib2, iclass 23, count 0 2006.285.20:02:15.94#ibcon#flushed, iclass 23, count 0 2006.285.20:02:15.94#ibcon#about to write, iclass 23, count 0 2006.285.20:02:15.94#ibcon#wrote, iclass 23, count 0 2006.285.20:02:15.94#ibcon#about to read 3, iclass 23, count 0 2006.285.20:02:15.96#ibcon#read 3, iclass 23, count 0 2006.285.20:02:15.96#ibcon#about to read 4, iclass 23, count 0 2006.285.20:02:15.96#ibcon#read 4, iclass 23, count 0 2006.285.20:02:15.96#ibcon#about to read 5, iclass 23, count 0 2006.285.20:02:15.96#ibcon#read 5, iclass 23, count 0 2006.285.20:02:15.96#ibcon#about to read 6, iclass 23, count 0 2006.285.20:02:15.96#ibcon#read 6, iclass 23, count 0 2006.285.20:02:15.96#ibcon#end of sib2, iclass 23, count 0 2006.285.20:02:15.96#ibcon#*mode == 0, iclass 23, count 0 2006.285.20:02:15.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.20:02:15.96#ibcon#[25=USB\r\n] 2006.285.20:02:15.96#ibcon#*before write, iclass 23, count 0 2006.285.20:02:15.96#ibcon#enter sib2, iclass 23, count 0 2006.285.20:02:15.96#ibcon#flushed, iclass 23, count 0 2006.285.20:02:15.96#ibcon#about to write, iclass 23, count 0 2006.285.20:02:15.96#ibcon#wrote, iclass 23, count 0 2006.285.20:02:15.96#ibcon#about to read 3, iclass 23, count 0 2006.285.20:02:15.99#ibcon#read 3, iclass 23, count 0 2006.285.20:02:15.99#ibcon#about to read 4, iclass 23, count 0 2006.285.20:02:15.99#ibcon#read 4, iclass 23, count 0 2006.285.20:02:15.99#ibcon#about to read 5, iclass 23, count 0 2006.285.20:02:15.99#ibcon#read 5, iclass 23, count 0 2006.285.20:02:15.99#ibcon#about to read 6, iclass 23, count 0 2006.285.20:02:15.99#ibcon#read 6, iclass 23, count 0 2006.285.20:02:15.99#ibcon#end of sib2, iclass 23, count 0 2006.285.20:02:15.99#ibcon#*after write, iclass 23, count 0 2006.285.20:02:15.99#ibcon#*before return 0, iclass 23, count 0 2006.285.20:02:15.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:02:15.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:02:15.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.20:02:15.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.20:02:15.99$vck44/valo=7,864.99 2006.285.20:02:15.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.20:02:15.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.20:02:15.99#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:15.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:02:15.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:02:15.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:02:15.99#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:02:15.99#ibcon#first serial, iclass 25, count 0 2006.285.20:02:15.99#ibcon#enter sib2, iclass 25, count 0 2006.285.20:02:15.99#ibcon#flushed, iclass 25, count 0 2006.285.20:02:15.99#ibcon#about to write, iclass 25, count 0 2006.285.20:02:15.99#ibcon#wrote, iclass 25, count 0 2006.285.20:02:15.99#ibcon#about to read 3, iclass 25, count 0 2006.285.20:02:16.01#ibcon#read 3, iclass 25, count 0 2006.285.20:02:16.01#ibcon#about to read 4, iclass 25, count 0 2006.285.20:02:16.01#ibcon#read 4, iclass 25, count 0 2006.285.20:02:16.01#ibcon#about to read 5, iclass 25, count 0 2006.285.20:02:16.01#ibcon#read 5, iclass 25, count 0 2006.285.20:02:16.01#ibcon#about to read 6, iclass 25, count 0 2006.285.20:02:16.01#ibcon#read 6, iclass 25, count 0 2006.285.20:02:16.01#ibcon#end of sib2, iclass 25, count 0 2006.285.20:02:16.01#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:02:16.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:02:16.01#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.20:02:16.01#ibcon#*before write, iclass 25, count 0 2006.285.20:02:16.01#ibcon#enter sib2, iclass 25, count 0 2006.285.20:02:16.01#ibcon#flushed, iclass 25, count 0 2006.285.20:02:16.01#ibcon#about to write, iclass 25, count 0 2006.285.20:02:16.01#ibcon#wrote, iclass 25, count 0 2006.285.20:02:16.01#ibcon#about to read 3, iclass 25, count 0 2006.285.20:02:16.05#ibcon#read 3, iclass 25, count 0 2006.285.20:02:16.05#ibcon#about to read 4, iclass 25, count 0 2006.285.20:02:16.05#ibcon#read 4, iclass 25, count 0 2006.285.20:02:16.05#ibcon#about to read 5, iclass 25, count 0 2006.285.20:02:16.05#ibcon#read 5, iclass 25, count 0 2006.285.20:02:16.05#ibcon#about to read 6, iclass 25, count 0 2006.285.20:02:16.05#ibcon#read 6, iclass 25, count 0 2006.285.20:02:16.05#ibcon#end of sib2, iclass 25, count 0 2006.285.20:02:16.05#ibcon#*after write, iclass 25, count 0 2006.285.20:02:16.05#ibcon#*before return 0, iclass 25, count 0 2006.285.20:02:16.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:02:16.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:02:16.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:02:16.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:02:16.05$vck44/va=7,4 2006.285.20:02:16.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.20:02:16.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.20:02:16.05#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:16.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:02:16.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:02:16.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:02:16.11#ibcon#enter wrdev, iclass 27, count 2 2006.285.20:02:16.11#ibcon#first serial, iclass 27, count 2 2006.285.20:02:16.11#ibcon#enter sib2, iclass 27, count 2 2006.285.20:02:16.11#ibcon#flushed, iclass 27, count 2 2006.285.20:02:16.11#ibcon#about to write, iclass 27, count 2 2006.285.20:02:16.11#ibcon#wrote, iclass 27, count 2 2006.285.20:02:16.11#ibcon#about to read 3, iclass 27, count 2 2006.285.20:02:16.13#ibcon#read 3, iclass 27, count 2 2006.285.20:02:16.13#ibcon#about to read 4, iclass 27, count 2 2006.285.20:02:16.13#ibcon#read 4, iclass 27, count 2 2006.285.20:02:16.13#ibcon#about to read 5, iclass 27, count 2 2006.285.20:02:16.13#ibcon#read 5, iclass 27, count 2 2006.285.20:02:16.13#ibcon#about to read 6, iclass 27, count 2 2006.285.20:02:16.13#ibcon#read 6, iclass 27, count 2 2006.285.20:02:16.13#ibcon#end of sib2, iclass 27, count 2 2006.285.20:02:16.13#ibcon#*mode == 0, iclass 27, count 2 2006.285.20:02:16.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.20:02:16.13#ibcon#[25=AT07-04\r\n] 2006.285.20:02:16.13#ibcon#*before write, iclass 27, count 2 2006.285.20:02:16.13#ibcon#enter sib2, iclass 27, count 2 2006.285.20:02:16.13#ibcon#flushed, iclass 27, count 2 2006.285.20:02:16.13#ibcon#about to write, iclass 27, count 2 2006.285.20:02:16.13#ibcon#wrote, iclass 27, count 2 2006.285.20:02:16.13#ibcon#about to read 3, iclass 27, count 2 2006.285.20:02:16.16#ibcon#read 3, iclass 27, count 2 2006.285.20:02:16.16#ibcon#about to read 4, iclass 27, count 2 2006.285.20:02:16.16#ibcon#read 4, iclass 27, count 2 2006.285.20:02:16.16#ibcon#about to read 5, iclass 27, count 2 2006.285.20:02:16.16#ibcon#read 5, iclass 27, count 2 2006.285.20:02:16.16#ibcon#about to read 6, iclass 27, count 2 2006.285.20:02:16.16#ibcon#read 6, iclass 27, count 2 2006.285.20:02:16.16#ibcon#end of sib2, iclass 27, count 2 2006.285.20:02:16.16#ibcon#*after write, iclass 27, count 2 2006.285.20:02:16.16#ibcon#*before return 0, iclass 27, count 2 2006.285.20:02:16.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:02:16.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:02:16.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.20:02:16.16#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:16.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:02:16.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:02:16.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:02:16.28#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:02:16.28#ibcon#first serial, iclass 27, count 0 2006.285.20:02:16.28#ibcon#enter sib2, iclass 27, count 0 2006.285.20:02:16.28#ibcon#flushed, iclass 27, count 0 2006.285.20:02:16.28#ibcon#about to write, iclass 27, count 0 2006.285.20:02:16.28#ibcon#wrote, iclass 27, count 0 2006.285.20:02:16.28#ibcon#about to read 3, iclass 27, count 0 2006.285.20:02:16.30#ibcon#read 3, iclass 27, count 0 2006.285.20:02:16.30#ibcon#about to read 4, iclass 27, count 0 2006.285.20:02:16.30#ibcon#read 4, iclass 27, count 0 2006.285.20:02:16.30#ibcon#about to read 5, iclass 27, count 0 2006.285.20:02:16.30#ibcon#read 5, iclass 27, count 0 2006.285.20:02:16.30#ibcon#about to read 6, iclass 27, count 0 2006.285.20:02:16.30#ibcon#read 6, iclass 27, count 0 2006.285.20:02:16.30#ibcon#end of sib2, iclass 27, count 0 2006.285.20:02:16.30#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:02:16.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:02:16.30#ibcon#[25=USB\r\n] 2006.285.20:02:16.30#ibcon#*before write, iclass 27, count 0 2006.285.20:02:16.30#ibcon#enter sib2, iclass 27, count 0 2006.285.20:02:16.30#ibcon#flushed, iclass 27, count 0 2006.285.20:02:16.30#ibcon#about to write, iclass 27, count 0 2006.285.20:02:16.30#ibcon#wrote, iclass 27, count 0 2006.285.20:02:16.30#ibcon#about to read 3, iclass 27, count 0 2006.285.20:02:16.33#ibcon#read 3, iclass 27, count 0 2006.285.20:02:16.33#ibcon#about to read 4, iclass 27, count 0 2006.285.20:02:16.33#ibcon#read 4, iclass 27, count 0 2006.285.20:02:16.33#ibcon#about to read 5, iclass 27, count 0 2006.285.20:02:16.33#ibcon#read 5, iclass 27, count 0 2006.285.20:02:16.33#ibcon#about to read 6, iclass 27, count 0 2006.285.20:02:16.33#ibcon#read 6, iclass 27, count 0 2006.285.20:02:16.33#ibcon#end of sib2, iclass 27, count 0 2006.285.20:02:16.33#ibcon#*after write, iclass 27, count 0 2006.285.20:02:16.33#ibcon#*before return 0, iclass 27, count 0 2006.285.20:02:16.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:02:16.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:02:16.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:02:16.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:02:16.33$vck44/valo=8,884.99 2006.285.20:02:16.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.20:02:16.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.20:02:16.33#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:16.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:02:16.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:02:16.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:02:16.33#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:02:16.33#ibcon#first serial, iclass 29, count 0 2006.285.20:02:16.33#ibcon#enter sib2, iclass 29, count 0 2006.285.20:02:16.33#ibcon#flushed, iclass 29, count 0 2006.285.20:02:16.33#ibcon#about to write, iclass 29, count 0 2006.285.20:02:16.33#ibcon#wrote, iclass 29, count 0 2006.285.20:02:16.33#ibcon#about to read 3, iclass 29, count 0 2006.285.20:02:16.35#ibcon#read 3, iclass 29, count 0 2006.285.20:02:16.35#ibcon#about to read 4, iclass 29, count 0 2006.285.20:02:16.35#ibcon#read 4, iclass 29, count 0 2006.285.20:02:16.35#ibcon#about to read 5, iclass 29, count 0 2006.285.20:02:16.35#ibcon#read 5, iclass 29, count 0 2006.285.20:02:16.35#ibcon#about to read 6, iclass 29, count 0 2006.285.20:02:16.35#ibcon#read 6, iclass 29, count 0 2006.285.20:02:16.35#ibcon#end of sib2, iclass 29, count 0 2006.285.20:02:16.35#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:02:16.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:02:16.35#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.20:02:16.35#ibcon#*before write, iclass 29, count 0 2006.285.20:02:16.35#ibcon#enter sib2, iclass 29, count 0 2006.285.20:02:16.35#ibcon#flushed, iclass 29, count 0 2006.285.20:02:16.35#ibcon#about to write, iclass 29, count 0 2006.285.20:02:16.35#ibcon#wrote, iclass 29, count 0 2006.285.20:02:16.35#ibcon#about to read 3, iclass 29, count 0 2006.285.20:02:16.39#ibcon#read 3, iclass 29, count 0 2006.285.20:02:16.39#ibcon#about to read 4, iclass 29, count 0 2006.285.20:02:16.39#ibcon#read 4, iclass 29, count 0 2006.285.20:02:16.39#ibcon#about to read 5, iclass 29, count 0 2006.285.20:02:16.39#ibcon#read 5, iclass 29, count 0 2006.285.20:02:16.39#ibcon#about to read 6, iclass 29, count 0 2006.285.20:02:16.39#ibcon#read 6, iclass 29, count 0 2006.285.20:02:16.39#ibcon#end of sib2, iclass 29, count 0 2006.285.20:02:16.39#ibcon#*after write, iclass 29, count 0 2006.285.20:02:16.39#ibcon#*before return 0, iclass 29, count 0 2006.285.20:02:16.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:02:16.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:02:16.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:02:16.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:02:16.39$vck44/va=8,3 2006.285.20:02:16.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.20:02:16.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.20:02:16.39#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:16.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:02:16.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:02:16.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:02:16.45#ibcon#enter wrdev, iclass 31, count 2 2006.285.20:02:16.45#ibcon#first serial, iclass 31, count 2 2006.285.20:02:16.45#ibcon#enter sib2, iclass 31, count 2 2006.285.20:02:16.45#ibcon#flushed, iclass 31, count 2 2006.285.20:02:16.45#ibcon#about to write, iclass 31, count 2 2006.285.20:02:16.45#ibcon#wrote, iclass 31, count 2 2006.285.20:02:16.45#ibcon#about to read 3, iclass 31, count 2 2006.285.20:02:16.47#ibcon#read 3, iclass 31, count 2 2006.285.20:02:16.47#ibcon#about to read 4, iclass 31, count 2 2006.285.20:02:16.47#ibcon#read 4, iclass 31, count 2 2006.285.20:02:16.47#ibcon#about to read 5, iclass 31, count 2 2006.285.20:02:16.47#ibcon#read 5, iclass 31, count 2 2006.285.20:02:16.47#ibcon#about to read 6, iclass 31, count 2 2006.285.20:02:16.47#ibcon#read 6, iclass 31, count 2 2006.285.20:02:16.47#ibcon#end of sib2, iclass 31, count 2 2006.285.20:02:16.47#ibcon#*mode == 0, iclass 31, count 2 2006.285.20:02:16.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.20:02:16.47#ibcon#[25=AT08-03\r\n] 2006.285.20:02:16.47#ibcon#*before write, iclass 31, count 2 2006.285.20:02:16.47#ibcon#enter sib2, iclass 31, count 2 2006.285.20:02:16.47#ibcon#flushed, iclass 31, count 2 2006.285.20:02:16.47#ibcon#about to write, iclass 31, count 2 2006.285.20:02:16.47#ibcon#wrote, iclass 31, count 2 2006.285.20:02:16.47#ibcon#about to read 3, iclass 31, count 2 2006.285.20:02:16.50#ibcon#read 3, iclass 31, count 2 2006.285.20:02:16.50#ibcon#about to read 4, iclass 31, count 2 2006.285.20:02:16.50#ibcon#read 4, iclass 31, count 2 2006.285.20:02:16.50#ibcon#about to read 5, iclass 31, count 2 2006.285.20:02:16.50#ibcon#read 5, iclass 31, count 2 2006.285.20:02:16.50#ibcon#about to read 6, iclass 31, count 2 2006.285.20:02:16.50#ibcon#read 6, iclass 31, count 2 2006.285.20:02:16.50#ibcon#end of sib2, iclass 31, count 2 2006.285.20:02:16.50#ibcon#*after write, iclass 31, count 2 2006.285.20:02:16.50#ibcon#*before return 0, iclass 31, count 2 2006.285.20:02:16.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:02:16.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:02:16.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.20:02:16.50#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:16.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:02:16.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:02:16.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:02:16.62#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:02:16.62#ibcon#first serial, iclass 31, count 0 2006.285.20:02:16.62#ibcon#enter sib2, iclass 31, count 0 2006.285.20:02:16.62#ibcon#flushed, iclass 31, count 0 2006.285.20:02:16.62#ibcon#about to write, iclass 31, count 0 2006.285.20:02:16.62#ibcon#wrote, iclass 31, count 0 2006.285.20:02:16.62#ibcon#about to read 3, iclass 31, count 0 2006.285.20:02:16.64#ibcon#read 3, iclass 31, count 0 2006.285.20:02:16.64#ibcon#about to read 4, iclass 31, count 0 2006.285.20:02:16.64#ibcon#read 4, iclass 31, count 0 2006.285.20:02:16.64#ibcon#about to read 5, iclass 31, count 0 2006.285.20:02:16.64#ibcon#read 5, iclass 31, count 0 2006.285.20:02:16.64#ibcon#about to read 6, iclass 31, count 0 2006.285.20:02:16.64#ibcon#read 6, iclass 31, count 0 2006.285.20:02:16.64#ibcon#end of sib2, iclass 31, count 0 2006.285.20:02:16.64#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:02:16.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:02:16.64#ibcon#[25=USB\r\n] 2006.285.20:02:16.64#ibcon#*before write, iclass 31, count 0 2006.285.20:02:16.64#ibcon#enter sib2, iclass 31, count 0 2006.285.20:02:16.64#ibcon#flushed, iclass 31, count 0 2006.285.20:02:16.64#ibcon#about to write, iclass 31, count 0 2006.285.20:02:16.64#ibcon#wrote, iclass 31, count 0 2006.285.20:02:16.64#ibcon#about to read 3, iclass 31, count 0 2006.285.20:02:16.67#ibcon#read 3, iclass 31, count 0 2006.285.20:02:16.67#ibcon#about to read 4, iclass 31, count 0 2006.285.20:02:16.67#ibcon#read 4, iclass 31, count 0 2006.285.20:02:16.67#ibcon#about to read 5, iclass 31, count 0 2006.285.20:02:16.67#ibcon#read 5, iclass 31, count 0 2006.285.20:02:16.67#ibcon#about to read 6, iclass 31, count 0 2006.285.20:02:16.67#ibcon#read 6, iclass 31, count 0 2006.285.20:02:16.67#ibcon#end of sib2, iclass 31, count 0 2006.285.20:02:16.67#ibcon#*after write, iclass 31, count 0 2006.285.20:02:16.67#ibcon#*before return 0, iclass 31, count 0 2006.285.20:02:16.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:02:16.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:02:16.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:02:16.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:02:16.67$vck44/vblo=1,629.99 2006.285.20:02:16.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.20:02:16.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.20:02:16.67#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:16.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:02:16.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:02:16.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:02:16.67#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:02:16.67#ibcon#first serial, iclass 33, count 0 2006.285.20:02:16.67#ibcon#enter sib2, iclass 33, count 0 2006.285.20:02:16.67#ibcon#flushed, iclass 33, count 0 2006.285.20:02:16.67#ibcon#about to write, iclass 33, count 0 2006.285.20:02:16.67#ibcon#wrote, iclass 33, count 0 2006.285.20:02:16.67#ibcon#about to read 3, iclass 33, count 0 2006.285.20:02:16.69#ibcon#read 3, iclass 33, count 0 2006.285.20:02:16.69#ibcon#about to read 4, iclass 33, count 0 2006.285.20:02:16.69#ibcon#read 4, iclass 33, count 0 2006.285.20:02:16.69#ibcon#about to read 5, iclass 33, count 0 2006.285.20:02:16.69#ibcon#read 5, iclass 33, count 0 2006.285.20:02:16.69#ibcon#about to read 6, iclass 33, count 0 2006.285.20:02:16.69#ibcon#read 6, iclass 33, count 0 2006.285.20:02:16.69#ibcon#end of sib2, iclass 33, count 0 2006.285.20:02:16.69#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:02:16.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:02:16.69#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.20:02:16.69#ibcon#*before write, iclass 33, count 0 2006.285.20:02:16.69#ibcon#enter sib2, iclass 33, count 0 2006.285.20:02:16.69#ibcon#flushed, iclass 33, count 0 2006.285.20:02:16.69#ibcon#about to write, iclass 33, count 0 2006.285.20:02:16.69#ibcon#wrote, iclass 33, count 0 2006.285.20:02:16.69#ibcon#about to read 3, iclass 33, count 0 2006.285.20:02:16.73#ibcon#read 3, iclass 33, count 0 2006.285.20:02:16.73#ibcon#about to read 4, iclass 33, count 0 2006.285.20:02:16.73#ibcon#read 4, iclass 33, count 0 2006.285.20:02:16.73#ibcon#about to read 5, iclass 33, count 0 2006.285.20:02:16.73#ibcon#read 5, iclass 33, count 0 2006.285.20:02:16.73#ibcon#about to read 6, iclass 33, count 0 2006.285.20:02:16.73#ibcon#read 6, iclass 33, count 0 2006.285.20:02:16.73#ibcon#end of sib2, iclass 33, count 0 2006.285.20:02:16.73#ibcon#*after write, iclass 33, count 0 2006.285.20:02:16.73#ibcon#*before return 0, iclass 33, count 0 2006.285.20:02:16.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:02:16.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:02:16.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:02:16.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:02:16.73$vck44/vb=1,4 2006.285.20:02:16.73#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.20:02:16.73#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.20:02:16.73#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:16.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:02:16.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:02:16.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:02:16.73#ibcon#enter wrdev, iclass 35, count 2 2006.285.20:02:16.73#ibcon#first serial, iclass 35, count 2 2006.285.20:02:16.73#ibcon#enter sib2, iclass 35, count 2 2006.285.20:02:16.73#ibcon#flushed, iclass 35, count 2 2006.285.20:02:16.73#ibcon#about to write, iclass 35, count 2 2006.285.20:02:16.73#ibcon#wrote, iclass 35, count 2 2006.285.20:02:16.73#ibcon#about to read 3, iclass 35, count 2 2006.285.20:02:16.75#ibcon#read 3, iclass 35, count 2 2006.285.20:02:16.75#ibcon#about to read 4, iclass 35, count 2 2006.285.20:02:16.75#ibcon#read 4, iclass 35, count 2 2006.285.20:02:16.75#ibcon#about to read 5, iclass 35, count 2 2006.285.20:02:16.75#ibcon#read 5, iclass 35, count 2 2006.285.20:02:16.75#ibcon#about to read 6, iclass 35, count 2 2006.285.20:02:16.75#ibcon#read 6, iclass 35, count 2 2006.285.20:02:16.75#ibcon#end of sib2, iclass 35, count 2 2006.285.20:02:16.75#ibcon#*mode == 0, iclass 35, count 2 2006.285.20:02:16.75#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.20:02:16.75#ibcon#[27=AT01-04\r\n] 2006.285.20:02:16.75#ibcon#*before write, iclass 35, count 2 2006.285.20:02:16.75#ibcon#enter sib2, iclass 35, count 2 2006.285.20:02:16.75#ibcon#flushed, iclass 35, count 2 2006.285.20:02:16.75#ibcon#about to write, iclass 35, count 2 2006.285.20:02:16.75#ibcon#wrote, iclass 35, count 2 2006.285.20:02:16.75#ibcon#about to read 3, iclass 35, count 2 2006.285.20:02:16.78#ibcon#read 3, iclass 35, count 2 2006.285.20:02:16.78#ibcon#about to read 4, iclass 35, count 2 2006.285.20:02:16.78#ibcon#read 4, iclass 35, count 2 2006.285.20:02:16.78#ibcon#about to read 5, iclass 35, count 2 2006.285.20:02:16.78#ibcon#read 5, iclass 35, count 2 2006.285.20:02:16.78#ibcon#about to read 6, iclass 35, count 2 2006.285.20:02:16.78#ibcon#read 6, iclass 35, count 2 2006.285.20:02:16.78#ibcon#end of sib2, iclass 35, count 2 2006.285.20:02:16.78#ibcon#*after write, iclass 35, count 2 2006.285.20:02:16.78#ibcon#*before return 0, iclass 35, count 2 2006.285.20:02:16.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:02:16.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:02:16.78#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.20:02:16.78#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:16.78#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:02:16.90#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:02:16.90#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:02:16.90#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:02:16.90#ibcon#first serial, iclass 35, count 0 2006.285.20:02:16.90#ibcon#enter sib2, iclass 35, count 0 2006.285.20:02:16.90#ibcon#flushed, iclass 35, count 0 2006.285.20:02:16.90#ibcon#about to write, iclass 35, count 0 2006.285.20:02:16.90#ibcon#wrote, iclass 35, count 0 2006.285.20:02:16.90#ibcon#about to read 3, iclass 35, count 0 2006.285.20:02:16.92#ibcon#read 3, iclass 35, count 0 2006.285.20:02:16.92#ibcon#about to read 4, iclass 35, count 0 2006.285.20:02:16.92#ibcon#read 4, iclass 35, count 0 2006.285.20:02:16.92#ibcon#about to read 5, iclass 35, count 0 2006.285.20:02:16.92#ibcon#read 5, iclass 35, count 0 2006.285.20:02:16.92#ibcon#about to read 6, iclass 35, count 0 2006.285.20:02:16.92#ibcon#read 6, iclass 35, count 0 2006.285.20:02:16.92#ibcon#end of sib2, iclass 35, count 0 2006.285.20:02:16.92#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:02:16.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:02:16.92#ibcon#[27=USB\r\n] 2006.285.20:02:16.92#ibcon#*before write, iclass 35, count 0 2006.285.20:02:16.92#ibcon#enter sib2, iclass 35, count 0 2006.285.20:02:16.92#ibcon#flushed, iclass 35, count 0 2006.285.20:02:16.92#ibcon#about to write, iclass 35, count 0 2006.285.20:02:16.92#ibcon#wrote, iclass 35, count 0 2006.285.20:02:16.92#ibcon#about to read 3, iclass 35, count 0 2006.285.20:02:16.95#ibcon#read 3, iclass 35, count 0 2006.285.20:02:16.95#ibcon#about to read 4, iclass 35, count 0 2006.285.20:02:16.95#ibcon#read 4, iclass 35, count 0 2006.285.20:02:16.95#ibcon#about to read 5, iclass 35, count 0 2006.285.20:02:16.95#ibcon#read 5, iclass 35, count 0 2006.285.20:02:16.95#ibcon#about to read 6, iclass 35, count 0 2006.285.20:02:16.95#ibcon#read 6, iclass 35, count 0 2006.285.20:02:16.95#ibcon#end of sib2, iclass 35, count 0 2006.285.20:02:16.95#ibcon#*after write, iclass 35, count 0 2006.285.20:02:16.95#ibcon#*before return 0, iclass 35, count 0 2006.285.20:02:16.95#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:02:16.95#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:02:16.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:02:16.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:02:16.95$vck44/vblo=2,634.99 2006.285.20:02:16.95#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.20:02:16.95#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.20:02:16.95#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:16.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:02:16.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:02:16.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:02:16.95#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:02:16.95#ibcon#first serial, iclass 37, count 0 2006.285.20:02:16.95#ibcon#enter sib2, iclass 37, count 0 2006.285.20:02:16.95#ibcon#flushed, iclass 37, count 0 2006.285.20:02:16.95#ibcon#about to write, iclass 37, count 0 2006.285.20:02:16.95#ibcon#wrote, iclass 37, count 0 2006.285.20:02:16.95#ibcon#about to read 3, iclass 37, count 0 2006.285.20:02:16.97#ibcon#read 3, iclass 37, count 0 2006.285.20:02:16.97#ibcon#about to read 4, iclass 37, count 0 2006.285.20:02:16.97#ibcon#read 4, iclass 37, count 0 2006.285.20:02:16.97#ibcon#about to read 5, iclass 37, count 0 2006.285.20:02:16.97#ibcon#read 5, iclass 37, count 0 2006.285.20:02:16.97#ibcon#about to read 6, iclass 37, count 0 2006.285.20:02:16.97#ibcon#read 6, iclass 37, count 0 2006.285.20:02:16.97#ibcon#end of sib2, iclass 37, count 0 2006.285.20:02:16.97#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:02:16.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:02:16.97#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.20:02:16.97#ibcon#*before write, iclass 37, count 0 2006.285.20:02:16.97#ibcon#enter sib2, iclass 37, count 0 2006.285.20:02:16.97#ibcon#flushed, iclass 37, count 0 2006.285.20:02:16.97#ibcon#about to write, iclass 37, count 0 2006.285.20:02:16.97#ibcon#wrote, iclass 37, count 0 2006.285.20:02:16.97#ibcon#about to read 3, iclass 37, count 0 2006.285.20:02:17.01#ibcon#read 3, iclass 37, count 0 2006.285.20:02:17.01#ibcon#about to read 4, iclass 37, count 0 2006.285.20:02:17.01#ibcon#read 4, iclass 37, count 0 2006.285.20:02:17.01#ibcon#about to read 5, iclass 37, count 0 2006.285.20:02:17.01#ibcon#read 5, iclass 37, count 0 2006.285.20:02:17.01#ibcon#about to read 6, iclass 37, count 0 2006.285.20:02:17.01#ibcon#read 6, iclass 37, count 0 2006.285.20:02:17.01#ibcon#end of sib2, iclass 37, count 0 2006.285.20:02:17.01#ibcon#*after write, iclass 37, count 0 2006.285.20:02:17.01#ibcon#*before return 0, iclass 37, count 0 2006.285.20:02:17.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:02:17.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:02:17.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:02:17.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:02:17.01$vck44/vb=2,5 2006.285.20:02:17.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.20:02:17.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.20:02:17.01#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:17.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:02:17.07#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:02:17.07#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:02:17.07#ibcon#enter wrdev, iclass 39, count 2 2006.285.20:02:17.07#ibcon#first serial, iclass 39, count 2 2006.285.20:02:17.07#ibcon#enter sib2, iclass 39, count 2 2006.285.20:02:17.07#ibcon#flushed, iclass 39, count 2 2006.285.20:02:17.07#ibcon#about to write, iclass 39, count 2 2006.285.20:02:17.07#ibcon#wrote, iclass 39, count 2 2006.285.20:02:17.07#ibcon#about to read 3, iclass 39, count 2 2006.285.20:02:17.09#ibcon#read 3, iclass 39, count 2 2006.285.20:02:17.09#ibcon#about to read 4, iclass 39, count 2 2006.285.20:02:17.09#ibcon#read 4, iclass 39, count 2 2006.285.20:02:17.09#ibcon#about to read 5, iclass 39, count 2 2006.285.20:02:17.09#ibcon#read 5, iclass 39, count 2 2006.285.20:02:17.09#ibcon#about to read 6, iclass 39, count 2 2006.285.20:02:17.09#ibcon#read 6, iclass 39, count 2 2006.285.20:02:17.09#ibcon#end of sib2, iclass 39, count 2 2006.285.20:02:17.09#ibcon#*mode == 0, iclass 39, count 2 2006.285.20:02:17.09#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.20:02:17.09#ibcon#[27=AT02-05\r\n] 2006.285.20:02:17.09#ibcon#*before write, iclass 39, count 2 2006.285.20:02:17.09#ibcon#enter sib2, iclass 39, count 2 2006.285.20:02:17.09#ibcon#flushed, iclass 39, count 2 2006.285.20:02:17.09#ibcon#about to write, iclass 39, count 2 2006.285.20:02:17.09#ibcon#wrote, iclass 39, count 2 2006.285.20:02:17.09#ibcon#about to read 3, iclass 39, count 2 2006.285.20:02:17.12#ibcon#read 3, iclass 39, count 2 2006.285.20:02:17.12#ibcon#about to read 4, iclass 39, count 2 2006.285.20:02:17.12#ibcon#read 4, iclass 39, count 2 2006.285.20:02:17.12#ibcon#about to read 5, iclass 39, count 2 2006.285.20:02:17.12#ibcon#read 5, iclass 39, count 2 2006.285.20:02:17.12#ibcon#about to read 6, iclass 39, count 2 2006.285.20:02:17.12#ibcon#read 6, iclass 39, count 2 2006.285.20:02:17.12#ibcon#end of sib2, iclass 39, count 2 2006.285.20:02:17.12#ibcon#*after write, iclass 39, count 2 2006.285.20:02:17.12#ibcon#*before return 0, iclass 39, count 2 2006.285.20:02:17.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:02:17.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:02:17.12#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.20:02:17.12#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:17.12#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:02:17.24#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:02:17.24#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:02:17.24#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:02:17.24#ibcon#first serial, iclass 39, count 0 2006.285.20:02:17.24#ibcon#enter sib2, iclass 39, count 0 2006.285.20:02:17.24#ibcon#flushed, iclass 39, count 0 2006.285.20:02:17.24#ibcon#about to write, iclass 39, count 0 2006.285.20:02:17.24#ibcon#wrote, iclass 39, count 0 2006.285.20:02:17.24#ibcon#about to read 3, iclass 39, count 0 2006.285.20:02:17.26#ibcon#read 3, iclass 39, count 0 2006.285.20:02:17.26#ibcon#about to read 4, iclass 39, count 0 2006.285.20:02:17.26#ibcon#read 4, iclass 39, count 0 2006.285.20:02:17.26#ibcon#about to read 5, iclass 39, count 0 2006.285.20:02:17.26#ibcon#read 5, iclass 39, count 0 2006.285.20:02:17.26#ibcon#about to read 6, iclass 39, count 0 2006.285.20:02:17.26#ibcon#read 6, iclass 39, count 0 2006.285.20:02:17.26#ibcon#end of sib2, iclass 39, count 0 2006.285.20:02:17.26#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:02:17.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:02:17.26#ibcon#[27=USB\r\n] 2006.285.20:02:17.26#ibcon#*before write, iclass 39, count 0 2006.285.20:02:17.26#ibcon#enter sib2, iclass 39, count 0 2006.285.20:02:17.26#ibcon#flushed, iclass 39, count 0 2006.285.20:02:17.26#ibcon#about to write, iclass 39, count 0 2006.285.20:02:17.26#ibcon#wrote, iclass 39, count 0 2006.285.20:02:17.26#ibcon#about to read 3, iclass 39, count 0 2006.285.20:02:17.29#ibcon#read 3, iclass 39, count 0 2006.285.20:02:17.29#ibcon#about to read 4, iclass 39, count 0 2006.285.20:02:17.29#ibcon#read 4, iclass 39, count 0 2006.285.20:02:17.29#ibcon#about to read 5, iclass 39, count 0 2006.285.20:02:17.29#ibcon#read 5, iclass 39, count 0 2006.285.20:02:17.29#ibcon#about to read 6, iclass 39, count 0 2006.285.20:02:17.29#ibcon#read 6, iclass 39, count 0 2006.285.20:02:17.29#ibcon#end of sib2, iclass 39, count 0 2006.285.20:02:17.29#ibcon#*after write, iclass 39, count 0 2006.285.20:02:17.29#ibcon#*before return 0, iclass 39, count 0 2006.285.20:02:17.29#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:02:17.29#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:02:17.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:02:17.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:02:17.29$vck44/vblo=3,649.99 2006.285.20:02:17.29#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.20:02:17.29#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.20:02:17.29#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:17.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:02:17.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:02:17.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:02:17.29#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:02:17.29#ibcon#first serial, iclass 3, count 0 2006.285.20:02:17.29#ibcon#enter sib2, iclass 3, count 0 2006.285.20:02:17.29#ibcon#flushed, iclass 3, count 0 2006.285.20:02:17.29#ibcon#about to write, iclass 3, count 0 2006.285.20:02:17.29#ibcon#wrote, iclass 3, count 0 2006.285.20:02:17.29#ibcon#about to read 3, iclass 3, count 0 2006.285.20:02:17.31#ibcon#read 3, iclass 3, count 0 2006.285.20:02:17.31#ibcon#about to read 4, iclass 3, count 0 2006.285.20:02:17.31#ibcon#read 4, iclass 3, count 0 2006.285.20:02:17.31#ibcon#about to read 5, iclass 3, count 0 2006.285.20:02:17.31#ibcon#read 5, iclass 3, count 0 2006.285.20:02:17.31#ibcon#about to read 6, iclass 3, count 0 2006.285.20:02:17.31#ibcon#read 6, iclass 3, count 0 2006.285.20:02:17.31#ibcon#end of sib2, iclass 3, count 0 2006.285.20:02:17.31#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:02:17.31#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:02:17.31#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.20:02:17.31#ibcon#*before write, iclass 3, count 0 2006.285.20:02:17.31#ibcon#enter sib2, iclass 3, count 0 2006.285.20:02:17.31#ibcon#flushed, iclass 3, count 0 2006.285.20:02:17.31#ibcon#about to write, iclass 3, count 0 2006.285.20:02:17.31#ibcon#wrote, iclass 3, count 0 2006.285.20:02:17.31#ibcon#about to read 3, iclass 3, count 0 2006.285.20:02:17.35#ibcon#read 3, iclass 3, count 0 2006.285.20:02:17.35#ibcon#about to read 4, iclass 3, count 0 2006.285.20:02:17.35#ibcon#read 4, iclass 3, count 0 2006.285.20:02:17.35#ibcon#about to read 5, iclass 3, count 0 2006.285.20:02:17.35#ibcon#read 5, iclass 3, count 0 2006.285.20:02:17.35#ibcon#about to read 6, iclass 3, count 0 2006.285.20:02:17.35#ibcon#read 6, iclass 3, count 0 2006.285.20:02:17.35#ibcon#end of sib2, iclass 3, count 0 2006.285.20:02:17.35#ibcon#*after write, iclass 3, count 0 2006.285.20:02:17.35#ibcon#*before return 0, iclass 3, count 0 2006.285.20:02:17.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:02:17.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:02:17.35#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:02:17.35#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:02:17.35$vck44/vb=3,4 2006.285.20:02:17.35#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.20:02:17.35#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.20:02:17.35#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:17.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:02:17.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:02:17.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:02:17.41#ibcon#enter wrdev, iclass 5, count 2 2006.285.20:02:17.41#ibcon#first serial, iclass 5, count 2 2006.285.20:02:17.41#ibcon#enter sib2, iclass 5, count 2 2006.285.20:02:17.41#ibcon#flushed, iclass 5, count 2 2006.285.20:02:17.41#ibcon#about to write, iclass 5, count 2 2006.285.20:02:17.41#ibcon#wrote, iclass 5, count 2 2006.285.20:02:17.41#ibcon#about to read 3, iclass 5, count 2 2006.285.20:02:17.43#ibcon#read 3, iclass 5, count 2 2006.285.20:02:17.43#ibcon#about to read 4, iclass 5, count 2 2006.285.20:02:17.43#ibcon#read 4, iclass 5, count 2 2006.285.20:02:17.43#ibcon#about to read 5, iclass 5, count 2 2006.285.20:02:17.43#ibcon#read 5, iclass 5, count 2 2006.285.20:02:17.43#ibcon#about to read 6, iclass 5, count 2 2006.285.20:02:17.43#ibcon#read 6, iclass 5, count 2 2006.285.20:02:17.43#ibcon#end of sib2, iclass 5, count 2 2006.285.20:02:17.43#ibcon#*mode == 0, iclass 5, count 2 2006.285.20:02:17.43#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.20:02:17.43#ibcon#[27=AT03-04\r\n] 2006.285.20:02:17.43#ibcon#*before write, iclass 5, count 2 2006.285.20:02:17.43#ibcon#enter sib2, iclass 5, count 2 2006.285.20:02:17.43#ibcon#flushed, iclass 5, count 2 2006.285.20:02:17.43#ibcon#about to write, iclass 5, count 2 2006.285.20:02:17.43#ibcon#wrote, iclass 5, count 2 2006.285.20:02:17.43#ibcon#about to read 3, iclass 5, count 2 2006.285.20:02:17.46#ibcon#read 3, iclass 5, count 2 2006.285.20:02:17.46#ibcon#about to read 4, iclass 5, count 2 2006.285.20:02:17.46#ibcon#read 4, iclass 5, count 2 2006.285.20:02:17.46#ibcon#about to read 5, iclass 5, count 2 2006.285.20:02:17.46#ibcon#read 5, iclass 5, count 2 2006.285.20:02:17.46#ibcon#about to read 6, iclass 5, count 2 2006.285.20:02:17.46#ibcon#read 6, iclass 5, count 2 2006.285.20:02:17.46#ibcon#end of sib2, iclass 5, count 2 2006.285.20:02:17.46#ibcon#*after write, iclass 5, count 2 2006.285.20:02:17.46#ibcon#*before return 0, iclass 5, count 2 2006.285.20:02:17.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:02:17.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:02:17.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.20:02:17.46#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:17.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:02:17.58#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:02:17.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:02:17.59#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:02:17.59#ibcon#first serial, iclass 5, count 0 2006.285.20:02:17.59#ibcon#enter sib2, iclass 5, count 0 2006.285.20:02:17.59#ibcon#flushed, iclass 5, count 0 2006.285.20:02:17.59#ibcon#about to write, iclass 5, count 0 2006.285.20:02:17.59#ibcon#wrote, iclass 5, count 0 2006.285.20:02:17.59#ibcon#about to read 3, iclass 5, count 0 2006.285.20:02:17.60#ibcon#read 3, iclass 5, count 0 2006.285.20:02:17.60#ibcon#about to read 4, iclass 5, count 0 2006.285.20:02:17.60#ibcon#read 4, iclass 5, count 0 2006.285.20:02:17.60#ibcon#about to read 5, iclass 5, count 0 2006.285.20:02:17.60#ibcon#read 5, iclass 5, count 0 2006.285.20:02:17.60#ibcon#about to read 6, iclass 5, count 0 2006.285.20:02:17.60#ibcon#read 6, iclass 5, count 0 2006.285.20:02:17.60#ibcon#end of sib2, iclass 5, count 0 2006.285.20:02:17.60#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:02:17.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:02:17.60#ibcon#[27=USB\r\n] 2006.285.20:02:17.60#ibcon#*before write, iclass 5, count 0 2006.285.20:02:17.60#ibcon#enter sib2, iclass 5, count 0 2006.285.20:02:17.60#ibcon#flushed, iclass 5, count 0 2006.285.20:02:17.60#ibcon#about to write, iclass 5, count 0 2006.285.20:02:17.60#ibcon#wrote, iclass 5, count 0 2006.285.20:02:17.60#ibcon#about to read 3, iclass 5, count 0 2006.285.20:02:17.63#ibcon#read 3, iclass 5, count 0 2006.285.20:02:17.63#ibcon#about to read 4, iclass 5, count 0 2006.285.20:02:17.63#ibcon#read 4, iclass 5, count 0 2006.285.20:02:17.63#ibcon#about to read 5, iclass 5, count 0 2006.285.20:02:17.63#ibcon#read 5, iclass 5, count 0 2006.285.20:02:17.63#ibcon#about to read 6, iclass 5, count 0 2006.285.20:02:17.63#ibcon#read 6, iclass 5, count 0 2006.285.20:02:17.63#ibcon#end of sib2, iclass 5, count 0 2006.285.20:02:17.63#ibcon#*after write, iclass 5, count 0 2006.285.20:02:17.63#ibcon#*before return 0, iclass 5, count 0 2006.285.20:02:17.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:02:17.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:02:17.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:02:17.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:02:17.63$vck44/vblo=4,679.99 2006.285.20:02:17.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.20:02:17.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.20:02:17.63#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:17.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:02:17.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:02:17.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:02:17.63#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:02:17.63#ibcon#first serial, iclass 7, count 0 2006.285.20:02:17.63#ibcon#enter sib2, iclass 7, count 0 2006.285.20:02:17.63#ibcon#flushed, iclass 7, count 0 2006.285.20:02:17.63#ibcon#about to write, iclass 7, count 0 2006.285.20:02:17.63#ibcon#wrote, iclass 7, count 0 2006.285.20:02:17.63#ibcon#about to read 3, iclass 7, count 0 2006.285.20:02:17.65#ibcon#read 3, iclass 7, count 0 2006.285.20:02:17.65#ibcon#about to read 4, iclass 7, count 0 2006.285.20:02:17.65#ibcon#read 4, iclass 7, count 0 2006.285.20:02:17.65#ibcon#about to read 5, iclass 7, count 0 2006.285.20:02:17.65#ibcon#read 5, iclass 7, count 0 2006.285.20:02:17.65#ibcon#about to read 6, iclass 7, count 0 2006.285.20:02:17.65#ibcon#read 6, iclass 7, count 0 2006.285.20:02:17.65#ibcon#end of sib2, iclass 7, count 0 2006.285.20:02:17.65#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:02:17.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:02:17.65#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.20:02:17.65#ibcon#*before write, iclass 7, count 0 2006.285.20:02:17.65#ibcon#enter sib2, iclass 7, count 0 2006.285.20:02:17.65#ibcon#flushed, iclass 7, count 0 2006.285.20:02:17.65#ibcon#about to write, iclass 7, count 0 2006.285.20:02:17.65#ibcon#wrote, iclass 7, count 0 2006.285.20:02:17.65#ibcon#about to read 3, iclass 7, count 0 2006.285.20:02:17.69#ibcon#read 3, iclass 7, count 0 2006.285.20:02:17.69#ibcon#about to read 4, iclass 7, count 0 2006.285.20:02:17.69#ibcon#read 4, iclass 7, count 0 2006.285.20:02:17.69#ibcon#about to read 5, iclass 7, count 0 2006.285.20:02:17.69#ibcon#read 5, iclass 7, count 0 2006.285.20:02:17.69#ibcon#about to read 6, iclass 7, count 0 2006.285.20:02:17.69#ibcon#read 6, iclass 7, count 0 2006.285.20:02:17.69#ibcon#end of sib2, iclass 7, count 0 2006.285.20:02:17.69#ibcon#*after write, iclass 7, count 0 2006.285.20:02:17.69#ibcon#*before return 0, iclass 7, count 0 2006.285.20:02:17.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:02:17.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:02:17.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:02:17.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:02:17.69$vck44/vb=4,5 2006.285.20:02:17.69#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.20:02:17.69#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.20:02:17.69#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:17.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:02:17.75#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:02:17.75#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:02:17.75#ibcon#enter wrdev, iclass 11, count 2 2006.285.20:02:17.75#ibcon#first serial, iclass 11, count 2 2006.285.20:02:17.75#ibcon#enter sib2, iclass 11, count 2 2006.285.20:02:17.75#ibcon#flushed, iclass 11, count 2 2006.285.20:02:17.75#ibcon#about to write, iclass 11, count 2 2006.285.20:02:17.75#ibcon#wrote, iclass 11, count 2 2006.285.20:02:17.75#ibcon#about to read 3, iclass 11, count 2 2006.285.20:02:17.77#ibcon#read 3, iclass 11, count 2 2006.285.20:02:17.77#ibcon#about to read 4, iclass 11, count 2 2006.285.20:02:17.77#ibcon#read 4, iclass 11, count 2 2006.285.20:02:17.77#ibcon#about to read 5, iclass 11, count 2 2006.285.20:02:17.77#ibcon#read 5, iclass 11, count 2 2006.285.20:02:17.77#ibcon#about to read 6, iclass 11, count 2 2006.285.20:02:17.77#ibcon#read 6, iclass 11, count 2 2006.285.20:02:17.77#ibcon#end of sib2, iclass 11, count 2 2006.285.20:02:17.77#ibcon#*mode == 0, iclass 11, count 2 2006.285.20:02:17.77#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.20:02:17.77#ibcon#[27=AT04-05\r\n] 2006.285.20:02:17.77#ibcon#*before write, iclass 11, count 2 2006.285.20:02:17.77#ibcon#enter sib2, iclass 11, count 2 2006.285.20:02:17.77#ibcon#flushed, iclass 11, count 2 2006.285.20:02:17.77#ibcon#about to write, iclass 11, count 2 2006.285.20:02:17.77#ibcon#wrote, iclass 11, count 2 2006.285.20:02:17.77#ibcon#about to read 3, iclass 11, count 2 2006.285.20:02:17.80#ibcon#read 3, iclass 11, count 2 2006.285.20:02:17.80#ibcon#about to read 4, iclass 11, count 2 2006.285.20:02:17.80#ibcon#read 4, iclass 11, count 2 2006.285.20:02:17.80#ibcon#about to read 5, iclass 11, count 2 2006.285.20:02:17.80#ibcon#read 5, iclass 11, count 2 2006.285.20:02:17.80#ibcon#about to read 6, iclass 11, count 2 2006.285.20:02:17.80#ibcon#read 6, iclass 11, count 2 2006.285.20:02:17.80#ibcon#end of sib2, iclass 11, count 2 2006.285.20:02:17.80#ibcon#*after write, iclass 11, count 2 2006.285.20:02:17.80#ibcon#*before return 0, iclass 11, count 2 2006.285.20:02:17.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:02:17.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:02:17.80#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.20:02:17.80#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:17.80#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:02:17.92#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:02:17.92#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:02:17.92#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:02:17.92#ibcon#first serial, iclass 11, count 0 2006.285.20:02:17.92#ibcon#enter sib2, iclass 11, count 0 2006.285.20:02:17.92#ibcon#flushed, iclass 11, count 0 2006.285.20:02:17.92#ibcon#about to write, iclass 11, count 0 2006.285.20:02:17.92#ibcon#wrote, iclass 11, count 0 2006.285.20:02:17.92#ibcon#about to read 3, iclass 11, count 0 2006.285.20:02:17.94#ibcon#read 3, iclass 11, count 0 2006.285.20:02:17.94#ibcon#about to read 4, iclass 11, count 0 2006.285.20:02:17.94#ibcon#read 4, iclass 11, count 0 2006.285.20:02:17.94#ibcon#about to read 5, iclass 11, count 0 2006.285.20:02:17.94#ibcon#read 5, iclass 11, count 0 2006.285.20:02:17.94#ibcon#about to read 6, iclass 11, count 0 2006.285.20:02:17.94#ibcon#read 6, iclass 11, count 0 2006.285.20:02:17.94#ibcon#end of sib2, iclass 11, count 0 2006.285.20:02:17.94#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:02:17.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:02:17.94#ibcon#[27=USB\r\n] 2006.285.20:02:17.94#ibcon#*before write, iclass 11, count 0 2006.285.20:02:17.94#ibcon#enter sib2, iclass 11, count 0 2006.285.20:02:17.94#ibcon#flushed, iclass 11, count 0 2006.285.20:02:17.94#ibcon#about to write, iclass 11, count 0 2006.285.20:02:17.94#ibcon#wrote, iclass 11, count 0 2006.285.20:02:17.94#ibcon#about to read 3, iclass 11, count 0 2006.285.20:02:17.97#ibcon#read 3, iclass 11, count 0 2006.285.20:02:17.97#ibcon#about to read 4, iclass 11, count 0 2006.285.20:02:17.97#ibcon#read 4, iclass 11, count 0 2006.285.20:02:17.97#ibcon#about to read 5, iclass 11, count 0 2006.285.20:02:17.97#ibcon#read 5, iclass 11, count 0 2006.285.20:02:17.97#ibcon#about to read 6, iclass 11, count 0 2006.285.20:02:17.97#ibcon#read 6, iclass 11, count 0 2006.285.20:02:17.97#ibcon#end of sib2, iclass 11, count 0 2006.285.20:02:17.97#ibcon#*after write, iclass 11, count 0 2006.285.20:02:17.97#ibcon#*before return 0, iclass 11, count 0 2006.285.20:02:17.97#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:02:17.97#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:02:17.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:02:17.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:02:17.97$vck44/vblo=5,709.99 2006.285.20:02:17.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.20:02:17.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.20:02:17.97#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:17.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:02:17.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:02:17.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:02:17.97#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:02:17.97#ibcon#first serial, iclass 13, count 0 2006.285.20:02:17.97#ibcon#enter sib2, iclass 13, count 0 2006.285.20:02:17.97#ibcon#flushed, iclass 13, count 0 2006.285.20:02:17.97#ibcon#about to write, iclass 13, count 0 2006.285.20:02:17.97#ibcon#wrote, iclass 13, count 0 2006.285.20:02:17.97#ibcon#about to read 3, iclass 13, count 0 2006.285.20:02:17.99#ibcon#read 3, iclass 13, count 0 2006.285.20:02:17.99#ibcon#about to read 4, iclass 13, count 0 2006.285.20:02:17.99#ibcon#read 4, iclass 13, count 0 2006.285.20:02:17.99#ibcon#about to read 5, iclass 13, count 0 2006.285.20:02:17.99#ibcon#read 5, iclass 13, count 0 2006.285.20:02:17.99#ibcon#about to read 6, iclass 13, count 0 2006.285.20:02:17.99#ibcon#read 6, iclass 13, count 0 2006.285.20:02:17.99#ibcon#end of sib2, iclass 13, count 0 2006.285.20:02:17.99#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:02:17.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:02:17.99#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.20:02:17.99#ibcon#*before write, iclass 13, count 0 2006.285.20:02:17.99#ibcon#enter sib2, iclass 13, count 0 2006.285.20:02:17.99#ibcon#flushed, iclass 13, count 0 2006.285.20:02:17.99#ibcon#about to write, iclass 13, count 0 2006.285.20:02:17.99#ibcon#wrote, iclass 13, count 0 2006.285.20:02:17.99#ibcon#about to read 3, iclass 13, count 0 2006.285.20:02:18.03#ibcon#read 3, iclass 13, count 0 2006.285.20:02:18.03#ibcon#about to read 4, iclass 13, count 0 2006.285.20:02:18.03#ibcon#read 4, iclass 13, count 0 2006.285.20:02:18.03#ibcon#about to read 5, iclass 13, count 0 2006.285.20:02:18.03#ibcon#read 5, iclass 13, count 0 2006.285.20:02:18.03#ibcon#about to read 6, iclass 13, count 0 2006.285.20:02:18.03#ibcon#read 6, iclass 13, count 0 2006.285.20:02:18.03#ibcon#end of sib2, iclass 13, count 0 2006.285.20:02:18.03#ibcon#*after write, iclass 13, count 0 2006.285.20:02:18.03#ibcon#*before return 0, iclass 13, count 0 2006.285.20:02:18.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:02:18.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:02:18.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:02:18.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:02:18.03$vck44/vb=5,4 2006.285.20:02:18.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.20:02:18.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.20:02:18.03#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:18.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:02:18.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:02:18.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:02:18.09#ibcon#enter wrdev, iclass 15, count 2 2006.285.20:02:18.09#ibcon#first serial, iclass 15, count 2 2006.285.20:02:18.09#ibcon#enter sib2, iclass 15, count 2 2006.285.20:02:18.09#ibcon#flushed, iclass 15, count 2 2006.285.20:02:18.09#ibcon#about to write, iclass 15, count 2 2006.285.20:02:18.09#ibcon#wrote, iclass 15, count 2 2006.285.20:02:18.09#ibcon#about to read 3, iclass 15, count 2 2006.285.20:02:18.11#ibcon#read 3, iclass 15, count 2 2006.285.20:02:18.11#ibcon#about to read 4, iclass 15, count 2 2006.285.20:02:18.11#ibcon#read 4, iclass 15, count 2 2006.285.20:02:18.11#ibcon#about to read 5, iclass 15, count 2 2006.285.20:02:18.11#ibcon#read 5, iclass 15, count 2 2006.285.20:02:18.11#ibcon#about to read 6, iclass 15, count 2 2006.285.20:02:18.11#ibcon#read 6, iclass 15, count 2 2006.285.20:02:18.11#ibcon#end of sib2, iclass 15, count 2 2006.285.20:02:18.11#ibcon#*mode == 0, iclass 15, count 2 2006.285.20:02:18.11#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.20:02:18.11#ibcon#[27=AT05-04\r\n] 2006.285.20:02:18.11#ibcon#*before write, iclass 15, count 2 2006.285.20:02:18.11#ibcon#enter sib2, iclass 15, count 2 2006.285.20:02:18.11#ibcon#flushed, iclass 15, count 2 2006.285.20:02:18.11#ibcon#about to write, iclass 15, count 2 2006.285.20:02:18.11#ibcon#wrote, iclass 15, count 2 2006.285.20:02:18.11#ibcon#about to read 3, iclass 15, count 2 2006.285.20:02:18.14#ibcon#read 3, iclass 15, count 2 2006.285.20:02:18.14#ibcon#about to read 4, iclass 15, count 2 2006.285.20:02:18.14#ibcon#read 4, iclass 15, count 2 2006.285.20:02:18.14#ibcon#about to read 5, iclass 15, count 2 2006.285.20:02:18.14#ibcon#read 5, iclass 15, count 2 2006.285.20:02:18.14#ibcon#about to read 6, iclass 15, count 2 2006.285.20:02:18.14#ibcon#read 6, iclass 15, count 2 2006.285.20:02:18.14#ibcon#end of sib2, iclass 15, count 2 2006.285.20:02:18.14#ibcon#*after write, iclass 15, count 2 2006.285.20:02:18.14#ibcon#*before return 0, iclass 15, count 2 2006.285.20:02:18.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:02:18.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:02:18.14#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.20:02:18.14#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:18.14#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:02:18.26#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:02:18.26#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:02:18.26#ibcon#enter wrdev, iclass 15, count 0 2006.285.20:02:18.26#ibcon#first serial, iclass 15, count 0 2006.285.20:02:18.26#ibcon#enter sib2, iclass 15, count 0 2006.285.20:02:18.26#ibcon#flushed, iclass 15, count 0 2006.285.20:02:18.26#ibcon#about to write, iclass 15, count 0 2006.285.20:02:18.26#ibcon#wrote, iclass 15, count 0 2006.285.20:02:18.26#ibcon#about to read 3, iclass 15, count 0 2006.285.20:02:18.28#ibcon#read 3, iclass 15, count 0 2006.285.20:02:18.28#ibcon#about to read 4, iclass 15, count 0 2006.285.20:02:18.28#ibcon#read 4, iclass 15, count 0 2006.285.20:02:18.28#ibcon#about to read 5, iclass 15, count 0 2006.285.20:02:18.28#ibcon#read 5, iclass 15, count 0 2006.285.20:02:18.28#ibcon#about to read 6, iclass 15, count 0 2006.285.20:02:18.28#ibcon#read 6, iclass 15, count 0 2006.285.20:02:18.28#ibcon#end of sib2, iclass 15, count 0 2006.285.20:02:18.28#ibcon#*mode == 0, iclass 15, count 0 2006.285.20:02:18.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.20:02:18.28#ibcon#[27=USB\r\n] 2006.285.20:02:18.28#ibcon#*before write, iclass 15, count 0 2006.285.20:02:18.28#ibcon#enter sib2, iclass 15, count 0 2006.285.20:02:18.28#ibcon#flushed, iclass 15, count 0 2006.285.20:02:18.28#ibcon#about to write, iclass 15, count 0 2006.285.20:02:18.28#ibcon#wrote, iclass 15, count 0 2006.285.20:02:18.28#ibcon#about to read 3, iclass 15, count 0 2006.285.20:02:18.31#ibcon#read 3, iclass 15, count 0 2006.285.20:02:18.31#ibcon#about to read 4, iclass 15, count 0 2006.285.20:02:18.31#ibcon#read 4, iclass 15, count 0 2006.285.20:02:18.31#ibcon#about to read 5, iclass 15, count 0 2006.285.20:02:18.31#ibcon#read 5, iclass 15, count 0 2006.285.20:02:18.31#ibcon#about to read 6, iclass 15, count 0 2006.285.20:02:18.31#ibcon#read 6, iclass 15, count 0 2006.285.20:02:18.31#ibcon#end of sib2, iclass 15, count 0 2006.285.20:02:18.31#ibcon#*after write, iclass 15, count 0 2006.285.20:02:18.31#ibcon#*before return 0, iclass 15, count 0 2006.285.20:02:18.31#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:02:18.31#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:02:18.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.20:02:18.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.20:02:18.31$vck44/vblo=6,719.99 2006.285.20:02:18.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.20:02:18.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.20:02:18.31#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:18.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:02:18.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:02:18.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:02:18.31#ibcon#enter wrdev, iclass 17, count 0 2006.285.20:02:18.31#ibcon#first serial, iclass 17, count 0 2006.285.20:02:18.31#ibcon#enter sib2, iclass 17, count 0 2006.285.20:02:18.31#ibcon#flushed, iclass 17, count 0 2006.285.20:02:18.31#ibcon#about to write, iclass 17, count 0 2006.285.20:02:18.31#ibcon#wrote, iclass 17, count 0 2006.285.20:02:18.31#ibcon#about to read 3, iclass 17, count 0 2006.285.20:02:18.33#ibcon#read 3, iclass 17, count 0 2006.285.20:02:18.33#ibcon#about to read 4, iclass 17, count 0 2006.285.20:02:18.33#ibcon#read 4, iclass 17, count 0 2006.285.20:02:18.33#ibcon#about to read 5, iclass 17, count 0 2006.285.20:02:18.33#ibcon#read 5, iclass 17, count 0 2006.285.20:02:18.33#ibcon#about to read 6, iclass 17, count 0 2006.285.20:02:18.33#ibcon#read 6, iclass 17, count 0 2006.285.20:02:18.33#ibcon#end of sib2, iclass 17, count 0 2006.285.20:02:18.33#ibcon#*mode == 0, iclass 17, count 0 2006.285.20:02:18.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.20:02:18.33#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.20:02:18.33#ibcon#*before write, iclass 17, count 0 2006.285.20:02:18.33#ibcon#enter sib2, iclass 17, count 0 2006.285.20:02:18.33#ibcon#flushed, iclass 17, count 0 2006.285.20:02:18.33#ibcon#about to write, iclass 17, count 0 2006.285.20:02:18.33#ibcon#wrote, iclass 17, count 0 2006.285.20:02:18.33#ibcon#about to read 3, iclass 17, count 0 2006.285.20:02:18.37#ibcon#read 3, iclass 17, count 0 2006.285.20:02:18.37#ibcon#about to read 4, iclass 17, count 0 2006.285.20:02:18.37#ibcon#read 4, iclass 17, count 0 2006.285.20:02:18.37#ibcon#about to read 5, iclass 17, count 0 2006.285.20:02:18.37#ibcon#read 5, iclass 17, count 0 2006.285.20:02:18.37#ibcon#about to read 6, iclass 17, count 0 2006.285.20:02:18.37#ibcon#read 6, iclass 17, count 0 2006.285.20:02:18.37#ibcon#end of sib2, iclass 17, count 0 2006.285.20:02:18.37#ibcon#*after write, iclass 17, count 0 2006.285.20:02:18.37#ibcon#*before return 0, iclass 17, count 0 2006.285.20:02:18.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:02:18.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:02:18.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.20:02:18.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.20:02:18.37$vck44/vb=6,3 2006.285.20:02:18.37#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.20:02:18.37#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.20:02:18.37#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:18.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:02:18.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:02:18.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:02:18.43#ibcon#enter wrdev, iclass 19, count 2 2006.285.20:02:18.43#ibcon#first serial, iclass 19, count 2 2006.285.20:02:18.43#ibcon#enter sib2, iclass 19, count 2 2006.285.20:02:18.43#ibcon#flushed, iclass 19, count 2 2006.285.20:02:18.43#ibcon#about to write, iclass 19, count 2 2006.285.20:02:18.43#ibcon#wrote, iclass 19, count 2 2006.285.20:02:18.43#ibcon#about to read 3, iclass 19, count 2 2006.285.20:02:18.45#ibcon#read 3, iclass 19, count 2 2006.285.20:02:18.45#ibcon#about to read 4, iclass 19, count 2 2006.285.20:02:18.45#ibcon#read 4, iclass 19, count 2 2006.285.20:02:18.45#ibcon#about to read 5, iclass 19, count 2 2006.285.20:02:18.45#ibcon#read 5, iclass 19, count 2 2006.285.20:02:18.45#ibcon#about to read 6, iclass 19, count 2 2006.285.20:02:18.45#ibcon#read 6, iclass 19, count 2 2006.285.20:02:18.45#ibcon#end of sib2, iclass 19, count 2 2006.285.20:02:18.45#ibcon#*mode == 0, iclass 19, count 2 2006.285.20:02:18.45#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.20:02:18.45#ibcon#[27=AT06-03\r\n] 2006.285.20:02:18.45#ibcon#*before write, iclass 19, count 2 2006.285.20:02:18.45#ibcon#enter sib2, iclass 19, count 2 2006.285.20:02:18.45#ibcon#flushed, iclass 19, count 2 2006.285.20:02:18.45#ibcon#about to write, iclass 19, count 2 2006.285.20:02:18.45#ibcon#wrote, iclass 19, count 2 2006.285.20:02:18.45#ibcon#about to read 3, iclass 19, count 2 2006.285.20:02:18.48#ibcon#read 3, iclass 19, count 2 2006.285.20:02:18.48#ibcon#about to read 4, iclass 19, count 2 2006.285.20:02:18.48#ibcon#read 4, iclass 19, count 2 2006.285.20:02:18.48#ibcon#about to read 5, iclass 19, count 2 2006.285.20:02:18.48#ibcon#read 5, iclass 19, count 2 2006.285.20:02:18.48#ibcon#about to read 6, iclass 19, count 2 2006.285.20:02:18.48#ibcon#read 6, iclass 19, count 2 2006.285.20:02:18.48#ibcon#end of sib2, iclass 19, count 2 2006.285.20:02:18.48#ibcon#*after write, iclass 19, count 2 2006.285.20:02:18.48#ibcon#*before return 0, iclass 19, count 2 2006.285.20:02:18.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:02:18.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:02:18.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.20:02:18.48#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:18.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:02:18.60#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:02:18.60#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:02:18.60#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:02:18.60#ibcon#first serial, iclass 19, count 0 2006.285.20:02:18.60#ibcon#enter sib2, iclass 19, count 0 2006.285.20:02:18.60#ibcon#flushed, iclass 19, count 0 2006.285.20:02:18.60#ibcon#about to write, iclass 19, count 0 2006.285.20:02:18.60#ibcon#wrote, iclass 19, count 0 2006.285.20:02:18.60#ibcon#about to read 3, iclass 19, count 0 2006.285.20:02:18.62#ibcon#read 3, iclass 19, count 0 2006.285.20:02:18.62#ibcon#about to read 4, iclass 19, count 0 2006.285.20:02:18.62#ibcon#read 4, iclass 19, count 0 2006.285.20:02:18.62#ibcon#about to read 5, iclass 19, count 0 2006.285.20:02:18.62#ibcon#read 5, iclass 19, count 0 2006.285.20:02:18.62#ibcon#about to read 6, iclass 19, count 0 2006.285.20:02:18.62#ibcon#read 6, iclass 19, count 0 2006.285.20:02:18.62#ibcon#end of sib2, iclass 19, count 0 2006.285.20:02:18.62#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:02:18.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:02:18.62#ibcon#[27=USB\r\n] 2006.285.20:02:18.62#ibcon#*before write, iclass 19, count 0 2006.285.20:02:18.62#ibcon#enter sib2, iclass 19, count 0 2006.285.20:02:18.62#ibcon#flushed, iclass 19, count 0 2006.285.20:02:18.62#ibcon#about to write, iclass 19, count 0 2006.285.20:02:18.62#ibcon#wrote, iclass 19, count 0 2006.285.20:02:18.62#ibcon#about to read 3, iclass 19, count 0 2006.285.20:02:18.65#ibcon#read 3, iclass 19, count 0 2006.285.20:02:18.65#ibcon#about to read 4, iclass 19, count 0 2006.285.20:02:18.65#ibcon#read 4, iclass 19, count 0 2006.285.20:02:18.65#ibcon#about to read 5, iclass 19, count 0 2006.285.20:02:18.65#ibcon#read 5, iclass 19, count 0 2006.285.20:02:18.65#ibcon#about to read 6, iclass 19, count 0 2006.285.20:02:18.65#ibcon#read 6, iclass 19, count 0 2006.285.20:02:18.65#ibcon#end of sib2, iclass 19, count 0 2006.285.20:02:18.65#ibcon#*after write, iclass 19, count 0 2006.285.20:02:18.65#ibcon#*before return 0, iclass 19, count 0 2006.285.20:02:18.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:02:18.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:02:18.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:02:18.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:02:18.65$vck44/vblo=7,734.99 2006.285.20:02:18.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.20:02:18.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.20:02:18.65#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:18.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:02:18.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:02:18.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:02:18.65#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:02:18.65#ibcon#first serial, iclass 21, count 0 2006.285.20:02:18.65#ibcon#enter sib2, iclass 21, count 0 2006.285.20:02:18.65#ibcon#flushed, iclass 21, count 0 2006.285.20:02:18.65#ibcon#about to write, iclass 21, count 0 2006.285.20:02:18.65#ibcon#wrote, iclass 21, count 0 2006.285.20:02:18.65#ibcon#about to read 3, iclass 21, count 0 2006.285.20:02:18.67#ibcon#read 3, iclass 21, count 0 2006.285.20:02:18.67#ibcon#about to read 4, iclass 21, count 0 2006.285.20:02:18.67#ibcon#read 4, iclass 21, count 0 2006.285.20:02:18.67#ibcon#about to read 5, iclass 21, count 0 2006.285.20:02:18.67#ibcon#read 5, iclass 21, count 0 2006.285.20:02:18.67#ibcon#about to read 6, iclass 21, count 0 2006.285.20:02:18.67#ibcon#read 6, iclass 21, count 0 2006.285.20:02:18.67#ibcon#end of sib2, iclass 21, count 0 2006.285.20:02:18.67#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:02:18.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:02:18.67#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.20:02:18.67#ibcon#*before write, iclass 21, count 0 2006.285.20:02:18.67#ibcon#enter sib2, iclass 21, count 0 2006.285.20:02:18.67#ibcon#flushed, iclass 21, count 0 2006.285.20:02:18.67#ibcon#about to write, iclass 21, count 0 2006.285.20:02:18.67#ibcon#wrote, iclass 21, count 0 2006.285.20:02:18.67#ibcon#about to read 3, iclass 21, count 0 2006.285.20:02:18.71#ibcon#read 3, iclass 21, count 0 2006.285.20:02:18.71#ibcon#about to read 4, iclass 21, count 0 2006.285.20:02:18.71#ibcon#read 4, iclass 21, count 0 2006.285.20:02:18.71#ibcon#about to read 5, iclass 21, count 0 2006.285.20:02:18.71#ibcon#read 5, iclass 21, count 0 2006.285.20:02:18.71#ibcon#about to read 6, iclass 21, count 0 2006.285.20:02:18.71#ibcon#read 6, iclass 21, count 0 2006.285.20:02:18.71#ibcon#end of sib2, iclass 21, count 0 2006.285.20:02:18.71#ibcon#*after write, iclass 21, count 0 2006.285.20:02:18.71#ibcon#*before return 0, iclass 21, count 0 2006.285.20:02:18.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:02:18.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:02:18.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:02:18.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:02:18.71$vck44/vb=7,4 2006.285.20:02:18.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.20:02:18.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.20:02:18.71#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:18.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:02:18.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:02:18.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:02:18.77#ibcon#enter wrdev, iclass 23, count 2 2006.285.20:02:18.77#ibcon#first serial, iclass 23, count 2 2006.285.20:02:18.77#ibcon#enter sib2, iclass 23, count 2 2006.285.20:02:18.77#ibcon#flushed, iclass 23, count 2 2006.285.20:02:18.77#ibcon#about to write, iclass 23, count 2 2006.285.20:02:18.77#ibcon#wrote, iclass 23, count 2 2006.285.20:02:18.77#ibcon#about to read 3, iclass 23, count 2 2006.285.20:02:18.79#ibcon#read 3, iclass 23, count 2 2006.285.20:02:18.79#ibcon#about to read 4, iclass 23, count 2 2006.285.20:02:18.79#ibcon#read 4, iclass 23, count 2 2006.285.20:02:18.79#ibcon#about to read 5, iclass 23, count 2 2006.285.20:02:18.79#ibcon#read 5, iclass 23, count 2 2006.285.20:02:18.79#ibcon#about to read 6, iclass 23, count 2 2006.285.20:02:18.79#ibcon#read 6, iclass 23, count 2 2006.285.20:02:18.79#ibcon#end of sib2, iclass 23, count 2 2006.285.20:02:18.79#ibcon#*mode == 0, iclass 23, count 2 2006.285.20:02:18.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.20:02:18.79#ibcon#[27=AT07-04\r\n] 2006.285.20:02:18.79#ibcon#*before write, iclass 23, count 2 2006.285.20:02:18.79#ibcon#enter sib2, iclass 23, count 2 2006.285.20:02:18.79#ibcon#flushed, iclass 23, count 2 2006.285.20:02:18.79#ibcon#about to write, iclass 23, count 2 2006.285.20:02:18.79#ibcon#wrote, iclass 23, count 2 2006.285.20:02:18.79#ibcon#about to read 3, iclass 23, count 2 2006.285.20:02:18.82#ibcon#read 3, iclass 23, count 2 2006.285.20:02:18.82#ibcon#about to read 4, iclass 23, count 2 2006.285.20:02:18.82#ibcon#read 4, iclass 23, count 2 2006.285.20:02:18.82#ibcon#about to read 5, iclass 23, count 2 2006.285.20:02:18.82#ibcon#read 5, iclass 23, count 2 2006.285.20:02:18.82#ibcon#about to read 6, iclass 23, count 2 2006.285.20:02:18.82#ibcon#read 6, iclass 23, count 2 2006.285.20:02:18.82#ibcon#end of sib2, iclass 23, count 2 2006.285.20:02:18.82#ibcon#*after write, iclass 23, count 2 2006.285.20:02:18.82#ibcon#*before return 0, iclass 23, count 2 2006.285.20:02:18.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:02:18.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:02:18.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.20:02:18.82#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:18.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:02:18.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:02:18.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:02:18.94#ibcon#enter wrdev, iclass 23, count 0 2006.285.20:02:18.94#ibcon#first serial, iclass 23, count 0 2006.285.20:02:18.94#ibcon#enter sib2, iclass 23, count 0 2006.285.20:02:18.94#ibcon#flushed, iclass 23, count 0 2006.285.20:02:18.94#ibcon#about to write, iclass 23, count 0 2006.285.20:02:18.94#ibcon#wrote, iclass 23, count 0 2006.285.20:02:18.94#ibcon#about to read 3, iclass 23, count 0 2006.285.20:02:18.96#ibcon#read 3, iclass 23, count 0 2006.285.20:02:18.96#ibcon#about to read 4, iclass 23, count 0 2006.285.20:02:18.96#ibcon#read 4, iclass 23, count 0 2006.285.20:02:18.96#ibcon#about to read 5, iclass 23, count 0 2006.285.20:02:18.96#ibcon#read 5, iclass 23, count 0 2006.285.20:02:18.96#ibcon#about to read 6, iclass 23, count 0 2006.285.20:02:18.96#ibcon#read 6, iclass 23, count 0 2006.285.20:02:18.96#ibcon#end of sib2, iclass 23, count 0 2006.285.20:02:18.96#ibcon#*mode == 0, iclass 23, count 0 2006.285.20:02:18.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.20:02:18.96#ibcon#[27=USB\r\n] 2006.285.20:02:18.96#ibcon#*before write, iclass 23, count 0 2006.285.20:02:18.96#ibcon#enter sib2, iclass 23, count 0 2006.285.20:02:18.96#ibcon#flushed, iclass 23, count 0 2006.285.20:02:18.96#ibcon#about to write, iclass 23, count 0 2006.285.20:02:18.96#ibcon#wrote, iclass 23, count 0 2006.285.20:02:18.96#ibcon#about to read 3, iclass 23, count 0 2006.285.20:02:18.99#ibcon#read 3, iclass 23, count 0 2006.285.20:02:18.99#ibcon#about to read 4, iclass 23, count 0 2006.285.20:02:18.99#ibcon#read 4, iclass 23, count 0 2006.285.20:02:18.99#ibcon#about to read 5, iclass 23, count 0 2006.285.20:02:18.99#ibcon#read 5, iclass 23, count 0 2006.285.20:02:18.99#ibcon#about to read 6, iclass 23, count 0 2006.285.20:02:18.99#ibcon#read 6, iclass 23, count 0 2006.285.20:02:18.99#ibcon#end of sib2, iclass 23, count 0 2006.285.20:02:18.99#ibcon#*after write, iclass 23, count 0 2006.285.20:02:18.99#ibcon#*before return 0, iclass 23, count 0 2006.285.20:02:18.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:02:18.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:02:18.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.20:02:18.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.20:02:18.99$vck44/vblo=8,744.99 2006.285.20:02:18.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.20:02:18.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.20:02:18.99#ibcon#ireg 17 cls_cnt 0 2006.285.20:02:18.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:02:18.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:02:18.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:02:18.99#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:02:18.99#ibcon#first serial, iclass 25, count 0 2006.285.20:02:18.99#ibcon#enter sib2, iclass 25, count 0 2006.285.20:02:18.99#ibcon#flushed, iclass 25, count 0 2006.285.20:02:18.99#ibcon#about to write, iclass 25, count 0 2006.285.20:02:18.99#ibcon#wrote, iclass 25, count 0 2006.285.20:02:18.99#ibcon#about to read 3, iclass 25, count 0 2006.285.20:02:19.01#ibcon#read 3, iclass 25, count 0 2006.285.20:02:19.01#ibcon#about to read 4, iclass 25, count 0 2006.285.20:02:19.01#ibcon#read 4, iclass 25, count 0 2006.285.20:02:19.01#ibcon#about to read 5, iclass 25, count 0 2006.285.20:02:19.01#ibcon#read 5, iclass 25, count 0 2006.285.20:02:19.01#ibcon#about to read 6, iclass 25, count 0 2006.285.20:02:19.01#ibcon#read 6, iclass 25, count 0 2006.285.20:02:19.01#ibcon#end of sib2, iclass 25, count 0 2006.285.20:02:19.01#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:02:19.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:02:19.01#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.20:02:19.01#ibcon#*before write, iclass 25, count 0 2006.285.20:02:19.01#ibcon#enter sib2, iclass 25, count 0 2006.285.20:02:19.01#ibcon#flushed, iclass 25, count 0 2006.285.20:02:19.01#ibcon#about to write, iclass 25, count 0 2006.285.20:02:19.01#ibcon#wrote, iclass 25, count 0 2006.285.20:02:19.01#ibcon#about to read 3, iclass 25, count 0 2006.285.20:02:19.05#ibcon#read 3, iclass 25, count 0 2006.285.20:02:19.05#ibcon#about to read 4, iclass 25, count 0 2006.285.20:02:19.05#ibcon#read 4, iclass 25, count 0 2006.285.20:02:19.05#ibcon#about to read 5, iclass 25, count 0 2006.285.20:02:19.05#ibcon#read 5, iclass 25, count 0 2006.285.20:02:19.05#ibcon#about to read 6, iclass 25, count 0 2006.285.20:02:19.05#ibcon#read 6, iclass 25, count 0 2006.285.20:02:19.05#ibcon#end of sib2, iclass 25, count 0 2006.285.20:02:19.05#ibcon#*after write, iclass 25, count 0 2006.285.20:02:19.05#ibcon#*before return 0, iclass 25, count 0 2006.285.20:02:19.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:02:19.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:02:19.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:02:19.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:02:19.05$vck44/vb=8,4 2006.285.20:02:19.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.20:02:19.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.20:02:19.05#ibcon#ireg 11 cls_cnt 2 2006.285.20:02:19.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:02:19.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:02:19.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:02:19.11#ibcon#enter wrdev, iclass 27, count 2 2006.285.20:02:19.11#ibcon#first serial, iclass 27, count 2 2006.285.20:02:19.11#ibcon#enter sib2, iclass 27, count 2 2006.285.20:02:19.11#ibcon#flushed, iclass 27, count 2 2006.285.20:02:19.11#ibcon#about to write, iclass 27, count 2 2006.285.20:02:19.11#ibcon#wrote, iclass 27, count 2 2006.285.20:02:19.11#ibcon#about to read 3, iclass 27, count 2 2006.285.20:02:19.13#ibcon#read 3, iclass 27, count 2 2006.285.20:02:19.13#ibcon#about to read 4, iclass 27, count 2 2006.285.20:02:19.13#ibcon#read 4, iclass 27, count 2 2006.285.20:02:19.13#ibcon#about to read 5, iclass 27, count 2 2006.285.20:02:19.13#ibcon#read 5, iclass 27, count 2 2006.285.20:02:19.13#ibcon#about to read 6, iclass 27, count 2 2006.285.20:02:19.13#ibcon#read 6, iclass 27, count 2 2006.285.20:02:19.13#ibcon#end of sib2, iclass 27, count 2 2006.285.20:02:19.13#ibcon#*mode == 0, iclass 27, count 2 2006.285.20:02:19.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.20:02:19.13#ibcon#[27=AT08-04\r\n] 2006.285.20:02:19.13#ibcon#*before write, iclass 27, count 2 2006.285.20:02:19.13#ibcon#enter sib2, iclass 27, count 2 2006.285.20:02:19.13#ibcon#flushed, iclass 27, count 2 2006.285.20:02:19.13#ibcon#about to write, iclass 27, count 2 2006.285.20:02:19.13#ibcon#wrote, iclass 27, count 2 2006.285.20:02:19.13#ibcon#about to read 3, iclass 27, count 2 2006.285.20:02:19.16#ibcon#read 3, iclass 27, count 2 2006.285.20:02:19.16#ibcon#about to read 4, iclass 27, count 2 2006.285.20:02:19.16#ibcon#read 4, iclass 27, count 2 2006.285.20:02:19.16#ibcon#about to read 5, iclass 27, count 2 2006.285.20:02:19.16#ibcon#read 5, iclass 27, count 2 2006.285.20:02:19.16#ibcon#about to read 6, iclass 27, count 2 2006.285.20:02:19.16#ibcon#read 6, iclass 27, count 2 2006.285.20:02:19.16#ibcon#end of sib2, iclass 27, count 2 2006.285.20:02:19.16#ibcon#*after write, iclass 27, count 2 2006.285.20:02:19.16#ibcon#*before return 0, iclass 27, count 2 2006.285.20:02:19.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:02:19.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:02:19.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.20:02:19.16#ibcon#ireg 7 cls_cnt 0 2006.285.20:02:19.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:02:19.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:02:19.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:02:19.28#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:02:19.28#ibcon#first serial, iclass 27, count 0 2006.285.20:02:19.28#ibcon#enter sib2, iclass 27, count 0 2006.285.20:02:19.28#ibcon#flushed, iclass 27, count 0 2006.285.20:02:19.28#ibcon#about to write, iclass 27, count 0 2006.285.20:02:19.28#ibcon#wrote, iclass 27, count 0 2006.285.20:02:19.28#ibcon#about to read 3, iclass 27, count 0 2006.285.20:02:19.30#ibcon#read 3, iclass 27, count 0 2006.285.20:02:19.30#ibcon#about to read 4, iclass 27, count 0 2006.285.20:02:19.30#ibcon#read 4, iclass 27, count 0 2006.285.20:02:19.30#ibcon#about to read 5, iclass 27, count 0 2006.285.20:02:19.30#ibcon#read 5, iclass 27, count 0 2006.285.20:02:19.30#ibcon#about to read 6, iclass 27, count 0 2006.285.20:02:19.30#ibcon#read 6, iclass 27, count 0 2006.285.20:02:19.30#ibcon#end of sib2, iclass 27, count 0 2006.285.20:02:19.30#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:02:19.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:02:19.30#ibcon#[27=USB\r\n] 2006.285.20:02:19.30#ibcon#*before write, iclass 27, count 0 2006.285.20:02:19.30#ibcon#enter sib2, iclass 27, count 0 2006.285.20:02:19.30#ibcon#flushed, iclass 27, count 0 2006.285.20:02:19.30#ibcon#about to write, iclass 27, count 0 2006.285.20:02:19.30#ibcon#wrote, iclass 27, count 0 2006.285.20:02:19.30#ibcon#about to read 3, iclass 27, count 0 2006.285.20:02:19.33#ibcon#read 3, iclass 27, count 0 2006.285.20:02:19.33#ibcon#about to read 4, iclass 27, count 0 2006.285.20:02:19.33#ibcon#read 4, iclass 27, count 0 2006.285.20:02:19.33#ibcon#about to read 5, iclass 27, count 0 2006.285.20:02:19.33#ibcon#read 5, iclass 27, count 0 2006.285.20:02:19.33#ibcon#about to read 6, iclass 27, count 0 2006.285.20:02:19.33#ibcon#read 6, iclass 27, count 0 2006.285.20:02:19.33#ibcon#end of sib2, iclass 27, count 0 2006.285.20:02:19.33#ibcon#*after write, iclass 27, count 0 2006.285.20:02:19.33#ibcon#*before return 0, iclass 27, count 0 2006.285.20:02:19.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:02:19.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:02:19.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:02:19.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:02:19.33$vck44/vabw=wide 2006.285.20:02:19.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.20:02:19.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.20:02:19.33#ibcon#ireg 8 cls_cnt 0 2006.285.20:02:19.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:02:19.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:02:19.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:02:19.33#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:02:19.33#ibcon#first serial, iclass 29, count 0 2006.285.20:02:19.33#ibcon#enter sib2, iclass 29, count 0 2006.285.20:02:19.33#ibcon#flushed, iclass 29, count 0 2006.285.20:02:19.33#ibcon#about to write, iclass 29, count 0 2006.285.20:02:19.33#ibcon#wrote, iclass 29, count 0 2006.285.20:02:19.33#ibcon#about to read 3, iclass 29, count 0 2006.285.20:02:19.35#ibcon#read 3, iclass 29, count 0 2006.285.20:02:19.35#ibcon#about to read 4, iclass 29, count 0 2006.285.20:02:19.35#ibcon#read 4, iclass 29, count 0 2006.285.20:02:19.35#ibcon#about to read 5, iclass 29, count 0 2006.285.20:02:19.35#ibcon#read 5, iclass 29, count 0 2006.285.20:02:19.35#ibcon#about to read 6, iclass 29, count 0 2006.285.20:02:19.35#ibcon#read 6, iclass 29, count 0 2006.285.20:02:19.35#ibcon#end of sib2, iclass 29, count 0 2006.285.20:02:19.35#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:02:19.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:02:19.35#ibcon#[25=BW32\r\n] 2006.285.20:02:19.35#ibcon#*before write, iclass 29, count 0 2006.285.20:02:19.35#ibcon#enter sib2, iclass 29, count 0 2006.285.20:02:19.35#ibcon#flushed, iclass 29, count 0 2006.285.20:02:19.35#ibcon#about to write, iclass 29, count 0 2006.285.20:02:19.35#ibcon#wrote, iclass 29, count 0 2006.285.20:02:19.35#ibcon#about to read 3, iclass 29, count 0 2006.285.20:02:19.38#ibcon#read 3, iclass 29, count 0 2006.285.20:02:19.38#ibcon#about to read 4, iclass 29, count 0 2006.285.20:02:19.38#ibcon#read 4, iclass 29, count 0 2006.285.20:02:19.38#ibcon#about to read 5, iclass 29, count 0 2006.285.20:02:19.38#ibcon#read 5, iclass 29, count 0 2006.285.20:02:19.38#ibcon#about to read 6, iclass 29, count 0 2006.285.20:02:19.38#ibcon#read 6, iclass 29, count 0 2006.285.20:02:19.38#ibcon#end of sib2, iclass 29, count 0 2006.285.20:02:19.38#ibcon#*after write, iclass 29, count 0 2006.285.20:02:19.38#ibcon#*before return 0, iclass 29, count 0 2006.285.20:02:19.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:02:19.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:02:19.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:02:19.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:02:19.38$vck44/vbbw=wide 2006.285.20:02:19.38#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.20:02:19.38#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.20:02:19.38#ibcon#ireg 8 cls_cnt 0 2006.285.20:02:19.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:02:19.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:02:19.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:02:19.45#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:02:19.45#ibcon#first serial, iclass 31, count 0 2006.285.20:02:19.45#ibcon#enter sib2, iclass 31, count 0 2006.285.20:02:19.45#ibcon#flushed, iclass 31, count 0 2006.285.20:02:19.45#ibcon#about to write, iclass 31, count 0 2006.285.20:02:19.45#ibcon#wrote, iclass 31, count 0 2006.285.20:02:19.45#ibcon#about to read 3, iclass 31, count 0 2006.285.20:02:19.47#ibcon#read 3, iclass 31, count 0 2006.285.20:02:19.47#ibcon#about to read 4, iclass 31, count 0 2006.285.20:02:19.47#ibcon#read 4, iclass 31, count 0 2006.285.20:02:19.47#ibcon#about to read 5, iclass 31, count 0 2006.285.20:02:19.47#ibcon#read 5, iclass 31, count 0 2006.285.20:02:19.47#ibcon#about to read 6, iclass 31, count 0 2006.285.20:02:19.47#ibcon#read 6, iclass 31, count 0 2006.285.20:02:19.47#ibcon#end of sib2, iclass 31, count 0 2006.285.20:02:19.47#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:02:19.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:02:19.47#ibcon#[27=BW32\r\n] 2006.285.20:02:19.47#ibcon#*before write, iclass 31, count 0 2006.285.20:02:19.47#ibcon#enter sib2, iclass 31, count 0 2006.285.20:02:19.47#ibcon#flushed, iclass 31, count 0 2006.285.20:02:19.47#ibcon#about to write, iclass 31, count 0 2006.285.20:02:19.47#ibcon#wrote, iclass 31, count 0 2006.285.20:02:19.47#ibcon#about to read 3, iclass 31, count 0 2006.285.20:02:19.50#ibcon#read 3, iclass 31, count 0 2006.285.20:02:19.50#ibcon#about to read 4, iclass 31, count 0 2006.285.20:02:19.50#ibcon#read 4, iclass 31, count 0 2006.285.20:02:19.50#ibcon#about to read 5, iclass 31, count 0 2006.285.20:02:19.50#ibcon#read 5, iclass 31, count 0 2006.285.20:02:19.50#ibcon#about to read 6, iclass 31, count 0 2006.285.20:02:19.50#ibcon#read 6, iclass 31, count 0 2006.285.20:02:19.50#ibcon#end of sib2, iclass 31, count 0 2006.285.20:02:19.50#ibcon#*after write, iclass 31, count 0 2006.285.20:02:19.50#ibcon#*before return 0, iclass 31, count 0 2006.285.20:02:19.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:02:19.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:02:19.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:02:19.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:02:19.50$setupk4/ifdk4 2006.285.20:02:19.50$ifdk4/lo= 2006.285.20:02:19.50$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.20:02:19.50$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.20:02:19.50$ifdk4/patch= 2006.285.20:02:19.62$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.20:02:19.62$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.20:02:19.63$setupk4/!*+20s 2006.285.20:02:20.66#abcon#<5=/14 0.4 1.1 14.541001015.3\r\n> 2006.285.20:02:20.68#abcon#{5=INTERFACE CLEAR} 2006.285.20:02:20.74#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:02:30.83#abcon#<5=/14 0.4 1.2 14.541001015.2\r\n> 2006.285.20:02:30.85#abcon#{5=INTERFACE CLEAR} 2006.285.20:02:30.91#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:02:33.14#trakl#Source acquired 2006.285.20:02:33.31$setupk4/"tpicd 2006.285.20:02:33.31$setupk4/echo=off 2006.285.20:02:33.31$setupk4/xlog=off 2006.285.20:02:33.31:!2006.285.20:04:18 2006.285.20:02:35.14#flagr#flagr/antenna,acquired 2006.285.20:04:18.00:preob 2006.285.20:04:18.14/onsource/TRACKING 2006.285.20:04:18.14:!2006.285.20:04:28 2006.285.20:04:28.00:"tape 2006.285.20:04:28.00:"st=record 2006.285.20:04:28.00:data_valid=on 2006.285.20:04:28.00:midob 2006.285.20:04:29.14/onsource/TRACKING 2006.285.20:04:29.14/wx/14.51,1015.2,100 2006.285.20:04:29.27/cable/+6.5083E-03 2006.285.20:04:30.36/va/01,07,usb,yes,33,36 2006.285.20:04:30.36/va/02,06,usb,yes,33,34 2006.285.20:04:30.36/va/03,07,usb,yes,33,35 2006.285.20:04:30.36/va/04,06,usb,yes,34,36 2006.285.20:04:30.36/va/05,03,usb,yes,34,34 2006.285.20:04:30.36/va/06,04,usb,yes,30,30 2006.285.20:04:30.36/va/07,04,usb,yes,31,32 2006.285.20:04:30.36/va/08,03,usb,yes,32,38 2006.285.20:04:30.59/valo/01,524.99,yes,locked 2006.285.20:04:30.59/valo/02,534.99,yes,locked 2006.285.20:04:30.59/valo/03,564.99,yes,locked 2006.285.20:04:30.59/valo/04,624.99,yes,locked 2006.285.20:04:30.59/valo/05,734.99,yes,locked 2006.285.20:04:30.59/valo/06,814.99,yes,locked 2006.285.20:04:30.59/valo/07,864.99,yes,locked 2006.285.20:04:30.59/valo/08,884.99,yes,locked 2006.285.20:04:31.68/vb/01,04,usb,yes,30,28 2006.285.20:04:31.68/vb/02,05,usb,yes,29,29 2006.285.20:04:31.68/vb/03,04,usb,yes,30,33 2006.285.20:04:31.68/vb/04,05,usb,yes,30,29 2006.285.20:04:31.68/vb/05,04,usb,yes,26,29 2006.285.20:04:31.68/vb/06,03,usb,yes,38,34 2006.285.20:04:31.68/vb/07,04,usb,yes,31,31 2006.285.20:04:31.68/vb/08,04,usb,yes,28,31 2006.285.20:04:31.91/vblo/01,629.99,yes,locked 2006.285.20:04:31.91/vblo/02,634.99,yes,locked 2006.285.20:04:31.91/vblo/03,649.99,yes,locked 2006.285.20:04:31.91/vblo/04,679.99,yes,locked 2006.285.20:04:31.91/vblo/05,709.99,yes,locked 2006.285.20:04:31.91/vblo/06,719.99,yes,locked 2006.285.20:04:31.91/vblo/07,734.99,yes,locked 2006.285.20:04:31.91/vblo/08,744.99,yes,locked 2006.285.20:04:32.06/vabw/8 2006.285.20:04:32.21/vbbw/8 2006.285.20:04:32.30/xfe/off,on,12.0 2006.285.20:04:32.72/ifatt/23,28,28,28 2006.285.20:04:33.08/fmout-gps/S +2.73E-07 2006.285.20:04:33.09:!2006.285.20:06:28 2006.285.20:06:28.02:data_valid=off 2006.285.20:06:28.02:"et 2006.285.20:06:28.02:!+3s 2006.285.20:06:31.03:"tape 2006.285.20:06:31.03:postob 2006.285.20:06:31.12/cable/+6.5076E-03 2006.285.20:06:31.12/wx/14.55,1015.2,100 2006.285.20:06:31.18/fmout-gps/S +2.71E-07 2006.285.20:06:31.18:scan_name=285-2010,jd0610,120 2006.285.20:06:31.18:source=3c274,123049.42,122328.0,2000.0,cw 2006.285.20:06:32.14#flagr#flagr/antenna,new-source 2006.285.20:06:32.14:checkk5 2006.285.20:06:32.59/chk_autoobs//k5ts1/ autoobs is running! 2006.285.20:06:33.16/chk_autoobs//k5ts2/ autoobs is running! 2006.285.20:06:33.54/chk_autoobs//k5ts3/ autoobs is running! 2006.285.20:06:33.93/chk_autoobs//k5ts4/ autoobs is running! 2006.285.20:06:34.31/chk_obsdata//k5ts1/T2852004??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.20:06:34.68/chk_obsdata//k5ts2/T2852004??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.20:06:35.16/chk_obsdata//k5ts3/T2852004??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.20:06:35.61/chk_obsdata//k5ts4/T2852004??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.20:06:36.96/k5log//k5ts1_log_newline 2006.285.20:06:37.79/k5log//k5ts2_log_newline 2006.285.20:06:38.68/k5log//k5ts3_log_newline 2006.285.20:06:39.49/k5log//k5ts4_log_newline 2006.285.20:06:39.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.20:06:39.52:setupk4=1 2006.285.20:06:39.52$setupk4/echo=on 2006.285.20:06:39.52$setupk4/pcalon 2006.285.20:06:39.52$pcalon/"no phase cal control is implemented here 2006.285.20:06:39.52$setupk4/"tpicd=stop 2006.285.20:06:39.52$setupk4/"rec=synch_on 2006.285.20:06:39.52$setupk4/"rec_mode=128 2006.285.20:06:39.52$setupk4/!* 2006.285.20:06:39.52$setupk4/recpk4 2006.285.20:06:39.52$recpk4/recpatch= 2006.285.20:06:39.52$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.20:06:39.52$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.20:06:39.52$setupk4/vck44 2006.285.20:06:39.52$vck44/valo=1,524.99 2006.285.20:06:39.52#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.20:06:39.52#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.20:06:39.52#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:39.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:06:39.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:06:39.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:06:39.52#ibcon#enter wrdev, iclass 32, count 0 2006.285.20:06:39.52#ibcon#first serial, iclass 32, count 0 2006.285.20:06:39.52#ibcon#enter sib2, iclass 32, count 0 2006.285.20:06:39.52#ibcon#flushed, iclass 32, count 0 2006.285.20:06:39.52#ibcon#about to write, iclass 32, count 0 2006.285.20:06:39.52#ibcon#wrote, iclass 32, count 0 2006.285.20:06:39.52#ibcon#about to read 3, iclass 32, count 0 2006.285.20:06:39.53#ibcon#read 3, iclass 32, count 0 2006.285.20:06:39.53#ibcon#about to read 4, iclass 32, count 0 2006.285.20:06:39.53#ibcon#read 4, iclass 32, count 0 2006.285.20:06:39.53#ibcon#about to read 5, iclass 32, count 0 2006.285.20:06:39.54#ibcon#read 5, iclass 32, count 0 2006.285.20:06:39.54#ibcon#about to read 6, iclass 32, count 0 2006.285.20:06:39.54#ibcon#read 6, iclass 32, count 0 2006.285.20:06:39.54#ibcon#end of sib2, iclass 32, count 0 2006.285.20:06:39.54#ibcon#*mode == 0, iclass 32, count 0 2006.285.20:06:39.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.20:06:39.54#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.20:06:39.54#ibcon#*before write, iclass 32, count 0 2006.285.20:06:39.54#ibcon#enter sib2, iclass 32, count 0 2006.285.20:06:39.54#ibcon#flushed, iclass 32, count 0 2006.285.20:06:39.54#ibcon#about to write, iclass 32, count 0 2006.285.20:06:39.54#ibcon#wrote, iclass 32, count 0 2006.285.20:06:39.54#ibcon#about to read 3, iclass 32, count 0 2006.285.20:06:39.58#ibcon#read 3, iclass 32, count 0 2006.285.20:06:39.58#ibcon#about to read 4, iclass 32, count 0 2006.285.20:06:39.58#ibcon#read 4, iclass 32, count 0 2006.285.20:06:39.58#ibcon#about to read 5, iclass 32, count 0 2006.285.20:06:39.58#ibcon#read 5, iclass 32, count 0 2006.285.20:06:39.59#ibcon#about to read 6, iclass 32, count 0 2006.285.20:06:39.59#ibcon#read 6, iclass 32, count 0 2006.285.20:06:39.59#ibcon#end of sib2, iclass 32, count 0 2006.285.20:06:39.59#ibcon#*after write, iclass 32, count 0 2006.285.20:06:39.59#ibcon#*before return 0, iclass 32, count 0 2006.285.20:06:39.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:06:39.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:06:39.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.20:06:39.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.20:06:39.59$vck44/va=1,7 2006.285.20:06:39.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.20:06:39.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.20:06:39.59#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:39.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:06:39.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:06:39.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:06:39.59#ibcon#enter wrdev, iclass 34, count 2 2006.285.20:06:39.59#ibcon#first serial, iclass 34, count 2 2006.285.20:06:39.59#ibcon#enter sib2, iclass 34, count 2 2006.285.20:06:39.59#ibcon#flushed, iclass 34, count 2 2006.285.20:06:39.59#ibcon#about to write, iclass 34, count 2 2006.285.20:06:39.59#ibcon#wrote, iclass 34, count 2 2006.285.20:06:39.59#ibcon#about to read 3, iclass 34, count 2 2006.285.20:06:39.60#ibcon#read 3, iclass 34, count 2 2006.285.20:06:39.60#ibcon#about to read 4, iclass 34, count 2 2006.285.20:06:39.60#ibcon#read 4, iclass 34, count 2 2006.285.20:06:39.60#ibcon#about to read 5, iclass 34, count 2 2006.285.20:06:39.61#ibcon#read 5, iclass 34, count 2 2006.285.20:06:39.61#ibcon#about to read 6, iclass 34, count 2 2006.285.20:06:39.61#ibcon#read 6, iclass 34, count 2 2006.285.20:06:39.61#ibcon#end of sib2, iclass 34, count 2 2006.285.20:06:39.61#ibcon#*mode == 0, iclass 34, count 2 2006.285.20:06:39.61#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.20:06:39.61#ibcon#[25=AT01-07\r\n] 2006.285.20:06:39.61#ibcon#*before write, iclass 34, count 2 2006.285.20:06:39.61#ibcon#enter sib2, iclass 34, count 2 2006.285.20:06:39.61#ibcon#flushed, iclass 34, count 2 2006.285.20:06:39.61#ibcon#about to write, iclass 34, count 2 2006.285.20:06:39.61#ibcon#wrote, iclass 34, count 2 2006.285.20:06:39.61#ibcon#about to read 3, iclass 34, count 2 2006.285.20:06:39.63#ibcon#read 3, iclass 34, count 2 2006.285.20:06:39.63#ibcon#about to read 4, iclass 34, count 2 2006.285.20:06:39.63#ibcon#read 4, iclass 34, count 2 2006.285.20:06:39.63#ibcon#about to read 5, iclass 34, count 2 2006.285.20:06:39.63#ibcon#read 5, iclass 34, count 2 2006.285.20:06:39.64#ibcon#about to read 6, iclass 34, count 2 2006.285.20:06:39.64#ibcon#read 6, iclass 34, count 2 2006.285.20:06:39.64#ibcon#end of sib2, iclass 34, count 2 2006.285.20:06:39.64#ibcon#*after write, iclass 34, count 2 2006.285.20:06:39.64#ibcon#*before return 0, iclass 34, count 2 2006.285.20:06:39.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:06:39.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:06:39.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.20:06:39.64#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:39.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:06:39.75#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:06:39.75#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:06:39.75#ibcon#enter wrdev, iclass 34, count 0 2006.285.20:06:39.75#ibcon#first serial, iclass 34, count 0 2006.285.20:06:39.75#ibcon#enter sib2, iclass 34, count 0 2006.285.20:06:39.76#ibcon#flushed, iclass 34, count 0 2006.285.20:06:39.76#ibcon#about to write, iclass 34, count 0 2006.285.20:06:39.76#ibcon#wrote, iclass 34, count 0 2006.285.20:06:39.76#ibcon#about to read 3, iclass 34, count 0 2006.285.20:06:39.77#ibcon#read 3, iclass 34, count 0 2006.285.20:06:39.77#ibcon#about to read 4, iclass 34, count 0 2006.285.20:06:39.77#ibcon#read 4, iclass 34, count 0 2006.285.20:06:39.77#ibcon#about to read 5, iclass 34, count 0 2006.285.20:06:39.77#ibcon#read 5, iclass 34, count 0 2006.285.20:06:39.78#ibcon#about to read 6, iclass 34, count 0 2006.285.20:06:39.78#ibcon#read 6, iclass 34, count 0 2006.285.20:06:39.78#ibcon#end of sib2, iclass 34, count 0 2006.285.20:06:39.78#ibcon#*mode == 0, iclass 34, count 0 2006.285.20:06:39.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.20:06:39.78#ibcon#[25=USB\r\n] 2006.285.20:06:39.78#ibcon#*before write, iclass 34, count 0 2006.285.20:06:39.78#ibcon#enter sib2, iclass 34, count 0 2006.285.20:06:39.78#ibcon#flushed, iclass 34, count 0 2006.285.20:06:39.78#ibcon#about to write, iclass 34, count 0 2006.285.20:06:39.78#ibcon#wrote, iclass 34, count 0 2006.285.20:06:39.78#ibcon#about to read 3, iclass 34, count 0 2006.285.20:06:39.80#ibcon#read 3, iclass 34, count 0 2006.285.20:06:39.80#ibcon#about to read 4, iclass 34, count 0 2006.285.20:06:39.80#ibcon#read 4, iclass 34, count 0 2006.285.20:06:39.80#ibcon#about to read 5, iclass 34, count 0 2006.285.20:06:39.80#ibcon#read 5, iclass 34, count 0 2006.285.20:06:39.81#ibcon#about to read 6, iclass 34, count 0 2006.285.20:06:39.81#ibcon#read 6, iclass 34, count 0 2006.285.20:06:39.81#ibcon#end of sib2, iclass 34, count 0 2006.285.20:06:39.81#ibcon#*after write, iclass 34, count 0 2006.285.20:06:39.81#ibcon#*before return 0, iclass 34, count 0 2006.285.20:06:39.81#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:06:39.81#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:06:39.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.20:06:39.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.20:06:39.81$vck44/valo=2,534.99 2006.285.20:06:39.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.20:06:39.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.20:06:39.81#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:39.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:06:39.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:06:39.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:06:39.81#ibcon#enter wrdev, iclass 36, count 0 2006.285.20:06:39.81#ibcon#first serial, iclass 36, count 0 2006.285.20:06:39.81#ibcon#enter sib2, iclass 36, count 0 2006.285.20:06:39.81#ibcon#flushed, iclass 36, count 0 2006.285.20:06:39.81#ibcon#about to write, iclass 36, count 0 2006.285.20:06:39.81#ibcon#wrote, iclass 36, count 0 2006.285.20:06:39.81#ibcon#about to read 3, iclass 36, count 0 2006.285.20:06:39.82#ibcon#read 3, iclass 36, count 0 2006.285.20:06:39.82#ibcon#about to read 4, iclass 36, count 0 2006.285.20:06:39.82#ibcon#read 4, iclass 36, count 0 2006.285.20:06:39.82#ibcon#about to read 5, iclass 36, count 0 2006.285.20:06:39.83#ibcon#read 5, iclass 36, count 0 2006.285.20:06:39.83#ibcon#about to read 6, iclass 36, count 0 2006.285.20:06:39.83#ibcon#read 6, iclass 36, count 0 2006.285.20:06:39.83#ibcon#end of sib2, iclass 36, count 0 2006.285.20:06:39.83#ibcon#*mode == 0, iclass 36, count 0 2006.285.20:06:39.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.20:06:39.83#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.20:06:39.83#ibcon#*before write, iclass 36, count 0 2006.285.20:06:39.83#ibcon#enter sib2, iclass 36, count 0 2006.285.20:06:39.83#ibcon#flushed, iclass 36, count 0 2006.285.20:06:39.83#ibcon#about to write, iclass 36, count 0 2006.285.20:06:39.83#ibcon#wrote, iclass 36, count 0 2006.285.20:06:39.83#ibcon#about to read 3, iclass 36, count 0 2006.285.20:06:39.86#ibcon#read 3, iclass 36, count 0 2006.285.20:06:39.86#ibcon#about to read 4, iclass 36, count 0 2006.285.20:06:39.86#ibcon#read 4, iclass 36, count 0 2006.285.20:06:39.86#ibcon#about to read 5, iclass 36, count 0 2006.285.20:06:39.86#ibcon#read 5, iclass 36, count 0 2006.285.20:06:39.87#ibcon#about to read 6, iclass 36, count 0 2006.285.20:06:39.87#ibcon#read 6, iclass 36, count 0 2006.285.20:06:39.87#ibcon#end of sib2, iclass 36, count 0 2006.285.20:06:39.87#ibcon#*after write, iclass 36, count 0 2006.285.20:06:39.87#ibcon#*before return 0, iclass 36, count 0 2006.285.20:06:39.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:06:39.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:06:39.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.20:06:39.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.20:06:39.87$vck44/va=2,6 2006.285.20:06:39.87#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.20:06:39.87#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.20:06:39.87#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:39.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:06:39.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:06:39.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:06:39.93#ibcon#enter wrdev, iclass 38, count 2 2006.285.20:06:39.93#ibcon#first serial, iclass 38, count 2 2006.285.20:06:39.93#ibcon#enter sib2, iclass 38, count 2 2006.285.20:06:39.93#ibcon#flushed, iclass 38, count 2 2006.285.20:06:39.93#ibcon#about to write, iclass 38, count 2 2006.285.20:06:39.93#ibcon#wrote, iclass 38, count 2 2006.285.20:06:39.93#ibcon#about to read 3, iclass 38, count 2 2006.285.20:06:39.94#ibcon#read 3, iclass 38, count 2 2006.285.20:06:39.95#ibcon#about to read 4, iclass 38, count 2 2006.285.20:06:39.95#ibcon#read 4, iclass 38, count 2 2006.285.20:06:39.95#ibcon#about to read 5, iclass 38, count 2 2006.285.20:06:39.95#ibcon#read 5, iclass 38, count 2 2006.285.20:06:39.95#ibcon#about to read 6, iclass 38, count 2 2006.285.20:06:39.95#ibcon#read 6, iclass 38, count 2 2006.285.20:06:39.95#ibcon#end of sib2, iclass 38, count 2 2006.285.20:06:39.95#ibcon#*mode == 0, iclass 38, count 2 2006.285.20:06:39.95#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.20:06:39.95#ibcon#[25=AT02-06\r\n] 2006.285.20:06:39.95#ibcon#*before write, iclass 38, count 2 2006.285.20:06:39.95#ibcon#enter sib2, iclass 38, count 2 2006.285.20:06:39.95#ibcon#flushed, iclass 38, count 2 2006.285.20:06:39.95#ibcon#about to write, iclass 38, count 2 2006.285.20:06:39.95#ibcon#wrote, iclass 38, count 2 2006.285.20:06:39.95#ibcon#about to read 3, iclass 38, count 2 2006.285.20:06:39.97#ibcon#read 3, iclass 38, count 2 2006.285.20:06:39.97#ibcon#about to read 4, iclass 38, count 2 2006.285.20:06:39.98#ibcon#read 4, iclass 38, count 2 2006.285.20:06:39.98#ibcon#about to read 5, iclass 38, count 2 2006.285.20:06:39.98#ibcon#read 5, iclass 38, count 2 2006.285.20:06:39.98#ibcon#about to read 6, iclass 38, count 2 2006.285.20:06:39.98#ibcon#read 6, iclass 38, count 2 2006.285.20:06:39.98#ibcon#end of sib2, iclass 38, count 2 2006.285.20:06:39.98#ibcon#*after write, iclass 38, count 2 2006.285.20:06:39.98#ibcon#*before return 0, iclass 38, count 2 2006.285.20:06:39.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:06:39.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:06:39.98#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.20:06:39.98#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:39.98#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:06:40.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:06:40.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:06:40.09#ibcon#enter wrdev, iclass 38, count 0 2006.285.20:06:40.10#ibcon#first serial, iclass 38, count 0 2006.285.20:06:40.10#ibcon#enter sib2, iclass 38, count 0 2006.285.20:06:40.10#ibcon#flushed, iclass 38, count 0 2006.285.20:06:40.10#ibcon#about to write, iclass 38, count 0 2006.285.20:06:40.10#ibcon#wrote, iclass 38, count 0 2006.285.20:06:40.10#ibcon#about to read 3, iclass 38, count 0 2006.285.20:06:40.11#ibcon#read 3, iclass 38, count 0 2006.285.20:06:40.11#ibcon#about to read 4, iclass 38, count 0 2006.285.20:06:40.11#ibcon#read 4, iclass 38, count 0 2006.285.20:06:40.11#ibcon#about to read 5, iclass 38, count 0 2006.285.20:06:40.12#ibcon#read 5, iclass 38, count 0 2006.285.20:06:40.12#ibcon#about to read 6, iclass 38, count 0 2006.285.20:06:40.12#ibcon#read 6, iclass 38, count 0 2006.285.20:06:40.12#ibcon#end of sib2, iclass 38, count 0 2006.285.20:06:40.12#ibcon#*mode == 0, iclass 38, count 0 2006.285.20:06:40.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.20:06:40.12#ibcon#[25=USB\r\n] 2006.285.20:06:40.12#ibcon#*before write, iclass 38, count 0 2006.285.20:06:40.12#ibcon#enter sib2, iclass 38, count 0 2006.285.20:06:40.12#ibcon#flushed, iclass 38, count 0 2006.285.20:06:40.12#ibcon#about to write, iclass 38, count 0 2006.285.20:06:40.12#ibcon#wrote, iclass 38, count 0 2006.285.20:06:40.12#ibcon#about to read 3, iclass 38, count 0 2006.285.20:06:40.14#ibcon#read 3, iclass 38, count 0 2006.285.20:06:40.41#ibcon#about to read 4, iclass 38, count 0 2006.285.20:06:40.41#ibcon#read 4, iclass 38, count 0 2006.285.20:06:40.41#ibcon#about to read 5, iclass 38, count 0 2006.285.20:06:40.41#ibcon#read 5, iclass 38, count 0 2006.285.20:06:40.41#ibcon#about to read 6, iclass 38, count 0 2006.285.20:06:40.41#ibcon#read 6, iclass 38, count 0 2006.285.20:06:40.41#ibcon#end of sib2, iclass 38, count 0 2006.285.20:06:40.41#ibcon#*after write, iclass 38, count 0 2006.285.20:06:40.41#ibcon#*before return 0, iclass 38, count 0 2006.285.20:06:40.41#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:06:40.41#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:06:40.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.20:06:40.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.20:06:40.41$vck44/valo=3,564.99 2006.285.20:06:40.41#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.20:06:40.41#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.20:06:40.41#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:40.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:06:40.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:06:40.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:06:40.41#ibcon#enter wrdev, iclass 40, count 0 2006.285.20:06:40.41#ibcon#first serial, iclass 40, count 0 2006.285.20:06:40.41#ibcon#enter sib2, iclass 40, count 0 2006.285.20:06:40.41#ibcon#flushed, iclass 40, count 0 2006.285.20:06:40.41#ibcon#about to write, iclass 40, count 0 2006.285.20:06:40.41#ibcon#wrote, iclass 40, count 0 2006.285.20:06:40.41#ibcon#about to read 3, iclass 40, count 0 2006.285.20:06:40.42#ibcon#read 3, iclass 40, count 0 2006.285.20:06:40.43#ibcon#about to read 4, iclass 40, count 0 2006.285.20:06:40.43#ibcon#read 4, iclass 40, count 0 2006.285.20:06:40.43#ibcon#about to read 5, iclass 40, count 0 2006.285.20:06:40.43#ibcon#read 5, iclass 40, count 0 2006.285.20:06:40.43#ibcon#about to read 6, iclass 40, count 0 2006.285.20:06:40.43#ibcon#read 6, iclass 40, count 0 2006.285.20:06:40.43#ibcon#end of sib2, iclass 40, count 0 2006.285.20:06:40.43#ibcon#*mode == 0, iclass 40, count 0 2006.285.20:06:40.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.20:06:40.43#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.20:06:40.43#ibcon#*before write, iclass 40, count 0 2006.285.20:06:40.43#ibcon#enter sib2, iclass 40, count 0 2006.285.20:06:40.43#ibcon#flushed, iclass 40, count 0 2006.285.20:06:40.43#ibcon#about to write, iclass 40, count 0 2006.285.20:06:40.43#ibcon#wrote, iclass 40, count 0 2006.285.20:06:40.43#ibcon#about to read 3, iclass 40, count 0 2006.285.20:06:40.46#ibcon#read 3, iclass 40, count 0 2006.285.20:06:40.46#ibcon#about to read 4, iclass 40, count 0 2006.285.20:06:40.46#ibcon#read 4, iclass 40, count 0 2006.285.20:06:40.47#ibcon#about to read 5, iclass 40, count 0 2006.285.20:06:40.47#ibcon#read 5, iclass 40, count 0 2006.285.20:06:40.47#ibcon#about to read 6, iclass 40, count 0 2006.285.20:06:40.47#ibcon#read 6, iclass 40, count 0 2006.285.20:06:40.47#ibcon#end of sib2, iclass 40, count 0 2006.285.20:06:40.47#ibcon#*after write, iclass 40, count 0 2006.285.20:06:40.47#ibcon#*before return 0, iclass 40, count 0 2006.285.20:06:40.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:06:40.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:06:40.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.20:06:40.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.20:06:40.47$vck44/va=3,7 2006.285.20:06:40.47#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.20:06:40.47#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.20:06:40.47#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:40.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:06:40.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:06:40.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:06:40.53#ibcon#enter wrdev, iclass 4, count 2 2006.285.20:06:40.53#ibcon#first serial, iclass 4, count 2 2006.285.20:06:40.53#ibcon#enter sib2, iclass 4, count 2 2006.285.20:06:40.53#ibcon#flushed, iclass 4, count 2 2006.285.20:06:40.53#ibcon#about to write, iclass 4, count 2 2006.285.20:06:40.53#ibcon#wrote, iclass 4, count 2 2006.285.20:06:40.53#ibcon#about to read 3, iclass 4, count 2 2006.285.20:06:40.54#ibcon#read 3, iclass 4, count 2 2006.285.20:06:40.54#ibcon#about to read 4, iclass 4, count 2 2006.285.20:06:40.54#ibcon#read 4, iclass 4, count 2 2006.285.20:06:40.55#ibcon#about to read 5, iclass 4, count 2 2006.285.20:06:40.55#ibcon#read 5, iclass 4, count 2 2006.285.20:06:40.55#ibcon#about to read 6, iclass 4, count 2 2006.285.20:06:40.55#ibcon#read 6, iclass 4, count 2 2006.285.20:06:40.55#ibcon#end of sib2, iclass 4, count 2 2006.285.20:06:40.55#ibcon#*mode == 0, iclass 4, count 2 2006.285.20:06:40.55#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.20:06:40.55#ibcon#[25=AT03-07\r\n] 2006.285.20:06:40.55#ibcon#*before write, iclass 4, count 2 2006.285.20:06:40.55#ibcon#enter sib2, iclass 4, count 2 2006.285.20:06:40.55#ibcon#flushed, iclass 4, count 2 2006.285.20:06:40.55#ibcon#about to write, iclass 4, count 2 2006.285.20:06:40.55#ibcon#wrote, iclass 4, count 2 2006.285.20:06:40.55#ibcon#about to read 3, iclass 4, count 2 2006.285.20:06:40.57#ibcon#read 3, iclass 4, count 2 2006.285.20:06:40.57#ibcon#about to read 4, iclass 4, count 2 2006.285.20:06:40.57#ibcon#read 4, iclass 4, count 2 2006.285.20:06:40.58#ibcon#about to read 5, iclass 4, count 2 2006.285.20:06:40.58#ibcon#read 5, iclass 4, count 2 2006.285.20:06:40.58#ibcon#about to read 6, iclass 4, count 2 2006.285.20:06:40.58#ibcon#read 6, iclass 4, count 2 2006.285.20:06:40.58#ibcon#end of sib2, iclass 4, count 2 2006.285.20:06:40.58#ibcon#*after write, iclass 4, count 2 2006.285.20:06:40.58#ibcon#*before return 0, iclass 4, count 2 2006.285.20:06:40.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:06:40.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:06:40.58#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.20:06:40.58#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:40.58#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:06:40.69#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:06:40.69#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:06:40.69#ibcon#enter wrdev, iclass 4, count 0 2006.285.20:06:40.70#ibcon#first serial, iclass 4, count 0 2006.285.20:06:40.70#ibcon#enter sib2, iclass 4, count 0 2006.285.20:06:40.70#ibcon#flushed, iclass 4, count 0 2006.285.20:06:40.70#ibcon#about to write, iclass 4, count 0 2006.285.20:06:40.70#ibcon#wrote, iclass 4, count 0 2006.285.20:06:40.70#ibcon#about to read 3, iclass 4, count 0 2006.285.20:06:40.71#ibcon#read 3, iclass 4, count 0 2006.285.20:06:40.71#ibcon#about to read 4, iclass 4, count 0 2006.285.20:06:40.72#ibcon#read 4, iclass 4, count 0 2006.285.20:06:40.72#ibcon#about to read 5, iclass 4, count 0 2006.285.20:06:40.72#ibcon#read 5, iclass 4, count 0 2006.285.20:06:40.72#ibcon#about to read 6, iclass 4, count 0 2006.285.20:06:40.72#ibcon#read 6, iclass 4, count 0 2006.285.20:06:40.72#ibcon#end of sib2, iclass 4, count 0 2006.285.20:06:40.72#ibcon#*mode == 0, iclass 4, count 0 2006.285.20:06:40.72#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.20:06:40.72#ibcon#[25=USB\r\n] 2006.285.20:06:40.72#ibcon#*before write, iclass 4, count 0 2006.285.20:06:40.72#ibcon#enter sib2, iclass 4, count 0 2006.285.20:06:40.72#ibcon#flushed, iclass 4, count 0 2006.285.20:06:40.72#ibcon#about to write, iclass 4, count 0 2006.285.20:06:40.72#ibcon#wrote, iclass 4, count 0 2006.285.20:06:40.72#ibcon#about to read 3, iclass 4, count 0 2006.285.20:06:40.74#ibcon#read 3, iclass 4, count 0 2006.285.20:06:40.74#ibcon#about to read 4, iclass 4, count 0 2006.285.20:06:40.74#ibcon#read 4, iclass 4, count 0 2006.285.20:06:40.75#ibcon#about to read 5, iclass 4, count 0 2006.285.20:06:40.75#ibcon#read 5, iclass 4, count 0 2006.285.20:06:40.75#ibcon#about to read 6, iclass 4, count 0 2006.285.20:06:40.75#ibcon#read 6, iclass 4, count 0 2006.285.20:06:40.75#ibcon#end of sib2, iclass 4, count 0 2006.285.20:06:40.75#ibcon#*after write, iclass 4, count 0 2006.285.20:06:40.75#ibcon#*before return 0, iclass 4, count 0 2006.285.20:06:40.75#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:06:40.75#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:06:40.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.20:06:40.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.20:06:40.75$vck44/valo=4,624.99 2006.285.20:06:40.75#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.20:06:40.75#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.20:06:40.75#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:40.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:06:40.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:06:40.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:06:40.75#ibcon#enter wrdev, iclass 6, count 0 2006.285.20:06:40.75#ibcon#first serial, iclass 6, count 0 2006.285.20:06:40.75#ibcon#enter sib2, iclass 6, count 0 2006.285.20:06:40.75#ibcon#flushed, iclass 6, count 0 2006.285.20:06:40.75#ibcon#about to write, iclass 6, count 0 2006.285.20:06:40.75#ibcon#wrote, iclass 6, count 0 2006.285.20:06:40.75#ibcon#about to read 3, iclass 6, count 0 2006.285.20:06:40.86#ibcon#read 3, iclass 6, count 0 2006.285.20:06:40.86#ibcon#about to read 4, iclass 6, count 0 2006.285.20:06:40.86#ibcon#read 4, iclass 6, count 0 2006.285.20:06:40.86#ibcon#about to read 5, iclass 6, count 0 2006.285.20:06:40.86#ibcon#read 5, iclass 6, count 0 2006.285.20:06:40.86#ibcon#about to read 6, iclass 6, count 0 2006.285.20:06:40.86#ibcon#read 6, iclass 6, count 0 2006.285.20:06:40.86#ibcon#end of sib2, iclass 6, count 0 2006.285.20:06:40.86#ibcon#*mode == 0, iclass 6, count 0 2006.285.20:06:40.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.20:06:40.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.20:06:40.86#ibcon#*before write, iclass 6, count 0 2006.285.20:06:40.86#ibcon#enter sib2, iclass 6, count 0 2006.285.20:06:40.86#ibcon#flushed, iclass 6, count 0 2006.285.20:06:40.86#ibcon#about to write, iclass 6, count 0 2006.285.20:06:40.86#ibcon#wrote, iclass 6, count 0 2006.285.20:06:40.86#ibcon#about to read 3, iclass 6, count 0 2006.285.20:06:40.89#ibcon#read 3, iclass 6, count 0 2006.285.20:06:40.89#ibcon#about to read 4, iclass 6, count 0 2006.285.20:06:40.89#ibcon#read 4, iclass 6, count 0 2006.285.20:06:40.90#ibcon#about to read 5, iclass 6, count 0 2006.285.20:06:40.90#ibcon#read 5, iclass 6, count 0 2006.285.20:06:40.90#ibcon#about to read 6, iclass 6, count 0 2006.285.20:06:40.90#ibcon#read 6, iclass 6, count 0 2006.285.20:06:40.90#ibcon#end of sib2, iclass 6, count 0 2006.285.20:06:40.90#ibcon#*after write, iclass 6, count 0 2006.285.20:06:40.90#ibcon#*before return 0, iclass 6, count 0 2006.285.20:06:40.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:06:40.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:06:40.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.20:06:40.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.20:06:40.90$vck44/va=4,6 2006.285.20:06:40.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.20:06:40.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.20:06:40.90#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:40.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:06:40.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:06:40.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:06:40.90#ibcon#enter wrdev, iclass 10, count 2 2006.285.20:06:40.90#ibcon#first serial, iclass 10, count 2 2006.285.20:06:40.90#ibcon#enter sib2, iclass 10, count 2 2006.285.20:06:40.90#ibcon#flushed, iclass 10, count 2 2006.285.20:06:40.90#ibcon#about to write, iclass 10, count 2 2006.285.20:06:40.90#ibcon#wrote, iclass 10, count 2 2006.285.20:06:40.90#ibcon#about to read 3, iclass 10, count 2 2006.285.20:06:40.91#ibcon#read 3, iclass 10, count 2 2006.285.20:06:40.91#ibcon#about to read 4, iclass 10, count 2 2006.285.20:06:40.91#ibcon#read 4, iclass 10, count 2 2006.285.20:06:40.92#ibcon#about to read 5, iclass 10, count 2 2006.285.20:06:40.92#ibcon#read 5, iclass 10, count 2 2006.285.20:06:40.92#ibcon#about to read 6, iclass 10, count 2 2006.285.20:06:40.92#ibcon#read 6, iclass 10, count 2 2006.285.20:06:40.92#ibcon#end of sib2, iclass 10, count 2 2006.285.20:06:40.92#ibcon#*mode == 0, iclass 10, count 2 2006.285.20:06:40.92#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.20:06:40.92#ibcon#[25=AT04-06\r\n] 2006.285.20:06:40.92#ibcon#*before write, iclass 10, count 2 2006.285.20:06:40.92#ibcon#enter sib2, iclass 10, count 2 2006.285.20:06:40.92#ibcon#flushed, iclass 10, count 2 2006.285.20:06:40.92#ibcon#about to write, iclass 10, count 2 2006.285.20:06:40.92#ibcon#wrote, iclass 10, count 2 2006.285.20:06:40.92#ibcon#about to read 3, iclass 10, count 2 2006.285.20:06:40.94#ibcon#read 3, iclass 10, count 2 2006.285.20:06:40.94#ibcon#about to read 4, iclass 10, count 2 2006.285.20:06:40.94#ibcon#read 4, iclass 10, count 2 2006.285.20:06:40.95#ibcon#about to read 5, iclass 10, count 2 2006.285.20:06:40.95#ibcon#read 5, iclass 10, count 2 2006.285.20:06:40.95#ibcon#about to read 6, iclass 10, count 2 2006.285.20:06:40.95#ibcon#read 6, iclass 10, count 2 2006.285.20:06:40.95#ibcon#end of sib2, iclass 10, count 2 2006.285.20:06:40.95#ibcon#*after write, iclass 10, count 2 2006.285.20:06:40.95#ibcon#*before return 0, iclass 10, count 2 2006.285.20:06:40.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:06:40.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:06:40.95#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.20:06:40.95#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:40.95#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:06:41.06#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:06:41.06#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:06:41.06#ibcon#enter wrdev, iclass 10, count 0 2006.285.20:06:41.07#ibcon#first serial, iclass 10, count 0 2006.285.20:06:41.07#ibcon#enter sib2, iclass 10, count 0 2006.285.20:06:41.07#ibcon#flushed, iclass 10, count 0 2006.285.20:06:41.07#ibcon#about to write, iclass 10, count 0 2006.285.20:06:41.07#ibcon#wrote, iclass 10, count 0 2006.285.20:06:41.07#ibcon#about to read 3, iclass 10, count 0 2006.285.20:06:41.08#ibcon#read 3, iclass 10, count 0 2006.285.20:06:41.08#ibcon#about to read 4, iclass 10, count 0 2006.285.20:06:41.08#ibcon#read 4, iclass 10, count 0 2006.285.20:06:41.08#ibcon#about to read 5, iclass 10, count 0 2006.285.20:06:41.08#ibcon#read 5, iclass 10, count 0 2006.285.20:06:41.09#ibcon#about to read 6, iclass 10, count 0 2006.285.20:06:41.09#ibcon#read 6, iclass 10, count 0 2006.285.20:06:41.09#ibcon#end of sib2, iclass 10, count 0 2006.285.20:06:41.09#ibcon#*mode == 0, iclass 10, count 0 2006.285.20:06:41.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.20:06:41.09#ibcon#[25=USB\r\n] 2006.285.20:06:41.09#ibcon#*before write, iclass 10, count 0 2006.285.20:06:41.09#ibcon#enter sib2, iclass 10, count 0 2006.285.20:06:41.09#ibcon#flushed, iclass 10, count 0 2006.285.20:06:41.09#ibcon#about to write, iclass 10, count 0 2006.285.20:06:41.09#ibcon#wrote, iclass 10, count 0 2006.285.20:06:41.09#ibcon#about to read 3, iclass 10, count 0 2006.285.20:06:41.11#ibcon#read 3, iclass 10, count 0 2006.285.20:06:41.11#ibcon#about to read 4, iclass 10, count 0 2006.285.20:06:41.11#ibcon#read 4, iclass 10, count 0 2006.285.20:06:41.11#ibcon#about to read 5, iclass 10, count 0 2006.285.20:06:41.11#ibcon#read 5, iclass 10, count 0 2006.285.20:06:41.12#ibcon#about to read 6, iclass 10, count 0 2006.285.20:06:41.12#ibcon#read 6, iclass 10, count 0 2006.285.20:06:41.12#ibcon#end of sib2, iclass 10, count 0 2006.285.20:06:41.12#ibcon#*after write, iclass 10, count 0 2006.285.20:06:41.12#ibcon#*before return 0, iclass 10, count 0 2006.285.20:06:41.12#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:06:41.12#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:06:41.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.20:06:41.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.20:06:41.12$vck44/valo=5,734.99 2006.285.20:06:41.12#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.20:06:41.12#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.20:06:41.12#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:41.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:06:41.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:06:41.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:06:41.12#ibcon#enter wrdev, iclass 12, count 0 2006.285.20:06:41.12#ibcon#first serial, iclass 12, count 0 2006.285.20:06:41.12#ibcon#enter sib2, iclass 12, count 0 2006.285.20:06:41.12#ibcon#flushed, iclass 12, count 0 2006.285.20:06:41.12#ibcon#about to write, iclass 12, count 0 2006.285.20:06:41.12#ibcon#wrote, iclass 12, count 0 2006.285.20:06:41.12#ibcon#about to read 3, iclass 12, count 0 2006.285.20:06:41.13#ibcon#read 3, iclass 12, count 0 2006.285.20:06:41.32#ibcon#about to read 4, iclass 12, count 0 2006.285.20:06:41.32#ibcon#read 4, iclass 12, count 0 2006.285.20:06:41.32#ibcon#about to read 5, iclass 12, count 0 2006.285.20:06:41.32#ibcon#read 5, iclass 12, count 0 2006.285.20:06:41.32#ibcon#about to read 6, iclass 12, count 0 2006.285.20:06:41.32#ibcon#read 6, iclass 12, count 0 2006.285.20:06:41.32#ibcon#end of sib2, iclass 12, count 0 2006.285.20:06:41.32#ibcon#*mode == 0, iclass 12, count 0 2006.285.20:06:41.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.20:06:41.32#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.20:06:41.32#ibcon#*before write, iclass 12, count 0 2006.285.20:06:41.32#ibcon#enter sib2, iclass 12, count 0 2006.285.20:06:41.32#ibcon#flushed, iclass 12, count 0 2006.285.20:06:41.32#ibcon#about to write, iclass 12, count 0 2006.285.20:06:41.32#ibcon#wrote, iclass 12, count 0 2006.285.20:06:41.32#ibcon#about to read 3, iclass 12, count 0 2006.285.20:06:41.35#ibcon#read 3, iclass 12, count 0 2006.285.20:06:41.35#ibcon#about to read 4, iclass 12, count 0 2006.285.20:06:41.35#ibcon#read 4, iclass 12, count 0 2006.285.20:06:41.35#ibcon#about to read 5, iclass 12, count 0 2006.285.20:06:41.36#ibcon#read 5, iclass 12, count 0 2006.285.20:06:41.36#ibcon#about to read 6, iclass 12, count 0 2006.285.20:06:41.36#ibcon#read 6, iclass 12, count 0 2006.285.20:06:41.36#ibcon#end of sib2, iclass 12, count 0 2006.285.20:06:41.36#ibcon#*after write, iclass 12, count 0 2006.285.20:06:41.36#ibcon#*before return 0, iclass 12, count 0 2006.285.20:06:41.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:06:41.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:06:41.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.20:06:41.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.20:06:41.36$vck44/va=5,3 2006.285.20:06:41.36#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.20:06:41.36#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.20:06:41.36#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:41.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:06:41.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:06:41.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:06:41.36#ibcon#enter wrdev, iclass 14, count 2 2006.285.20:06:41.36#ibcon#first serial, iclass 14, count 2 2006.285.20:06:41.36#ibcon#enter sib2, iclass 14, count 2 2006.285.20:06:41.36#ibcon#flushed, iclass 14, count 2 2006.285.20:06:41.36#ibcon#about to write, iclass 14, count 2 2006.285.20:06:41.36#ibcon#wrote, iclass 14, count 2 2006.285.20:06:41.36#ibcon#about to read 3, iclass 14, count 2 2006.285.20:06:41.37#ibcon#read 3, iclass 14, count 2 2006.285.20:06:41.37#ibcon#about to read 4, iclass 14, count 2 2006.285.20:06:41.37#ibcon#read 4, iclass 14, count 2 2006.285.20:06:41.38#ibcon#about to read 5, iclass 14, count 2 2006.285.20:06:41.38#ibcon#read 5, iclass 14, count 2 2006.285.20:06:41.38#ibcon#about to read 6, iclass 14, count 2 2006.285.20:06:41.38#ibcon#read 6, iclass 14, count 2 2006.285.20:06:41.38#ibcon#end of sib2, iclass 14, count 2 2006.285.20:06:41.38#ibcon#*mode == 0, iclass 14, count 2 2006.285.20:06:41.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.20:06:41.38#ibcon#[25=AT05-03\r\n] 2006.285.20:06:41.38#ibcon#*before write, iclass 14, count 2 2006.285.20:06:41.38#ibcon#enter sib2, iclass 14, count 2 2006.285.20:06:41.38#ibcon#flushed, iclass 14, count 2 2006.285.20:06:41.38#ibcon#about to write, iclass 14, count 2 2006.285.20:06:41.38#ibcon#wrote, iclass 14, count 2 2006.285.20:06:41.38#ibcon#about to read 3, iclass 14, count 2 2006.285.20:06:41.40#ibcon#read 3, iclass 14, count 2 2006.285.20:06:41.40#ibcon#about to read 4, iclass 14, count 2 2006.285.20:06:41.40#ibcon#read 4, iclass 14, count 2 2006.285.20:06:41.41#ibcon#about to read 5, iclass 14, count 2 2006.285.20:06:41.41#ibcon#read 5, iclass 14, count 2 2006.285.20:06:41.41#ibcon#about to read 6, iclass 14, count 2 2006.285.20:06:41.41#ibcon#read 6, iclass 14, count 2 2006.285.20:06:41.41#ibcon#end of sib2, iclass 14, count 2 2006.285.20:06:41.41#ibcon#*after write, iclass 14, count 2 2006.285.20:06:41.41#ibcon#*before return 0, iclass 14, count 2 2006.285.20:06:41.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:06:41.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:06:41.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.20:06:41.41#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:41.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:06:41.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:06:41.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:06:41.53#ibcon#enter wrdev, iclass 14, count 0 2006.285.20:06:41.53#ibcon#first serial, iclass 14, count 0 2006.285.20:06:41.53#ibcon#enter sib2, iclass 14, count 0 2006.285.20:06:41.53#ibcon#flushed, iclass 14, count 0 2006.285.20:06:41.53#ibcon#about to write, iclass 14, count 0 2006.285.20:06:41.53#ibcon#wrote, iclass 14, count 0 2006.285.20:06:41.53#ibcon#about to read 3, iclass 14, count 0 2006.285.20:06:41.54#ibcon#read 3, iclass 14, count 0 2006.285.20:06:41.54#ibcon#about to read 4, iclass 14, count 0 2006.285.20:06:41.54#ibcon#read 4, iclass 14, count 0 2006.285.20:06:41.54#ibcon#about to read 5, iclass 14, count 0 2006.285.20:06:41.54#ibcon#read 5, iclass 14, count 0 2006.285.20:06:41.55#ibcon#about to read 6, iclass 14, count 0 2006.285.20:06:41.55#ibcon#read 6, iclass 14, count 0 2006.285.20:06:41.55#ibcon#end of sib2, iclass 14, count 0 2006.285.20:06:41.55#ibcon#*mode == 0, iclass 14, count 0 2006.285.20:06:41.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.20:06:41.55#ibcon#[25=USB\r\n] 2006.285.20:06:41.55#ibcon#*before write, iclass 14, count 0 2006.285.20:06:41.55#ibcon#enter sib2, iclass 14, count 0 2006.285.20:06:41.55#ibcon#flushed, iclass 14, count 0 2006.285.20:06:41.55#ibcon#about to write, iclass 14, count 0 2006.285.20:06:41.55#ibcon#wrote, iclass 14, count 0 2006.285.20:06:41.55#ibcon#about to read 3, iclass 14, count 0 2006.285.20:06:41.57#ibcon#read 3, iclass 14, count 0 2006.285.20:06:41.57#ibcon#about to read 4, iclass 14, count 0 2006.285.20:06:41.57#ibcon#read 4, iclass 14, count 0 2006.285.20:06:41.57#ibcon#about to read 5, iclass 14, count 0 2006.285.20:06:41.57#ibcon#read 5, iclass 14, count 0 2006.285.20:06:41.58#ibcon#about to read 6, iclass 14, count 0 2006.285.20:06:41.58#ibcon#read 6, iclass 14, count 0 2006.285.20:06:41.58#ibcon#end of sib2, iclass 14, count 0 2006.285.20:06:41.58#ibcon#*after write, iclass 14, count 0 2006.285.20:06:41.58#ibcon#*before return 0, iclass 14, count 0 2006.285.20:06:41.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:06:41.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:06:41.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.20:06:41.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.20:06:41.58$vck44/valo=6,814.99 2006.285.20:06:41.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.20:06:41.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.20:06:41.58#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:41.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:06:41.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:06:41.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:06:41.58#ibcon#enter wrdev, iclass 16, count 0 2006.285.20:06:41.58#ibcon#first serial, iclass 16, count 0 2006.285.20:06:41.58#ibcon#enter sib2, iclass 16, count 0 2006.285.20:06:41.58#ibcon#flushed, iclass 16, count 0 2006.285.20:06:41.58#ibcon#about to write, iclass 16, count 0 2006.285.20:06:41.58#ibcon#wrote, iclass 16, count 0 2006.285.20:06:41.58#ibcon#about to read 3, iclass 16, count 0 2006.285.20:06:41.59#ibcon#read 3, iclass 16, count 0 2006.285.20:06:41.59#ibcon#about to read 4, iclass 16, count 0 2006.285.20:06:41.59#ibcon#read 4, iclass 16, count 0 2006.285.20:06:41.59#ibcon#about to read 5, iclass 16, count 0 2006.285.20:06:41.60#ibcon#read 5, iclass 16, count 0 2006.285.20:06:41.60#ibcon#about to read 6, iclass 16, count 0 2006.285.20:06:41.60#ibcon#read 6, iclass 16, count 0 2006.285.20:06:41.60#ibcon#end of sib2, iclass 16, count 0 2006.285.20:06:41.60#ibcon#*mode == 0, iclass 16, count 0 2006.285.20:06:41.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.20:06:41.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.20:06:41.60#ibcon#*before write, iclass 16, count 0 2006.285.20:06:41.60#ibcon#enter sib2, iclass 16, count 0 2006.285.20:06:41.60#ibcon#flushed, iclass 16, count 0 2006.285.20:06:41.60#ibcon#about to write, iclass 16, count 0 2006.285.20:06:41.60#ibcon#wrote, iclass 16, count 0 2006.285.20:06:41.60#ibcon#about to read 3, iclass 16, count 0 2006.285.20:06:41.63#ibcon#read 3, iclass 16, count 0 2006.285.20:06:41.63#ibcon#about to read 4, iclass 16, count 0 2006.285.20:06:41.63#ibcon#read 4, iclass 16, count 0 2006.285.20:06:41.63#ibcon#about to read 5, iclass 16, count 0 2006.285.20:06:41.63#ibcon#read 5, iclass 16, count 0 2006.285.20:06:41.64#ibcon#about to read 6, iclass 16, count 0 2006.285.20:06:41.64#ibcon#read 6, iclass 16, count 0 2006.285.20:06:41.64#ibcon#end of sib2, iclass 16, count 0 2006.285.20:06:41.64#ibcon#*after write, iclass 16, count 0 2006.285.20:06:41.64#ibcon#*before return 0, iclass 16, count 0 2006.285.20:06:41.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:06:41.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:06:41.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.20:06:41.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.20:06:41.64$vck44/va=6,4 2006.285.20:06:41.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.20:06:41.64#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.20:06:41.64#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:41.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:06:41.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:06:41.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:06:41.69#ibcon#enter wrdev, iclass 18, count 2 2006.285.20:06:41.69#ibcon#first serial, iclass 18, count 2 2006.285.20:06:41.69#ibcon#enter sib2, iclass 18, count 2 2006.285.20:06:41.70#ibcon#flushed, iclass 18, count 2 2006.285.20:06:41.70#ibcon#about to write, iclass 18, count 2 2006.285.20:06:41.70#ibcon#wrote, iclass 18, count 2 2006.285.20:06:41.70#ibcon#about to read 3, iclass 18, count 2 2006.285.20:06:41.71#ibcon#read 3, iclass 18, count 2 2006.285.20:06:41.71#ibcon#about to read 4, iclass 18, count 2 2006.285.20:06:41.71#ibcon#read 4, iclass 18, count 2 2006.285.20:06:41.71#ibcon#about to read 5, iclass 18, count 2 2006.285.20:06:41.71#ibcon#read 5, iclass 18, count 2 2006.285.20:06:41.71#ibcon#about to read 6, iclass 18, count 2 2006.285.20:06:41.72#ibcon#read 6, iclass 18, count 2 2006.285.20:06:41.72#ibcon#end of sib2, iclass 18, count 2 2006.285.20:06:41.72#ibcon#*mode == 0, iclass 18, count 2 2006.285.20:06:41.72#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.20:06:41.72#ibcon#[25=AT06-04\r\n] 2006.285.20:06:41.72#ibcon#*before write, iclass 18, count 2 2006.285.20:06:41.72#ibcon#enter sib2, iclass 18, count 2 2006.285.20:06:41.72#ibcon#flushed, iclass 18, count 2 2006.285.20:06:41.72#ibcon#about to write, iclass 18, count 2 2006.285.20:06:41.72#ibcon#wrote, iclass 18, count 2 2006.285.20:06:41.72#ibcon#about to read 3, iclass 18, count 2 2006.285.20:06:41.74#ibcon#read 3, iclass 18, count 2 2006.285.20:06:41.74#ibcon#about to read 4, iclass 18, count 2 2006.285.20:06:41.74#ibcon#read 4, iclass 18, count 2 2006.285.20:06:41.74#ibcon#about to read 5, iclass 18, count 2 2006.285.20:06:41.75#ibcon#read 5, iclass 18, count 2 2006.285.20:06:41.75#ibcon#about to read 6, iclass 18, count 2 2006.285.20:06:41.75#ibcon#read 6, iclass 18, count 2 2006.285.20:06:41.75#ibcon#end of sib2, iclass 18, count 2 2006.285.20:06:41.75#ibcon#*after write, iclass 18, count 2 2006.285.20:06:41.75#ibcon#*before return 0, iclass 18, count 2 2006.285.20:06:41.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:06:41.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:06:41.75#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.20:06:41.75#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:41.75#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:06:41.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:06:41.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:06:41.86#ibcon#enter wrdev, iclass 18, count 0 2006.285.20:06:41.86#ibcon#first serial, iclass 18, count 0 2006.285.20:06:41.86#ibcon#enter sib2, iclass 18, count 0 2006.285.20:06:41.87#ibcon#flushed, iclass 18, count 0 2006.285.20:06:41.87#ibcon#about to write, iclass 18, count 0 2006.285.20:06:41.87#ibcon#wrote, iclass 18, count 0 2006.285.20:06:41.87#ibcon#about to read 3, iclass 18, count 0 2006.285.20:06:41.88#ibcon#read 3, iclass 18, count 0 2006.285.20:06:41.88#ibcon#about to read 4, iclass 18, count 0 2006.285.20:06:41.88#ibcon#read 4, iclass 18, count 0 2006.285.20:06:41.88#ibcon#about to read 5, iclass 18, count 0 2006.285.20:06:41.88#ibcon#read 5, iclass 18, count 0 2006.285.20:06:41.88#ibcon#about to read 6, iclass 18, count 0 2006.285.20:06:41.89#ibcon#read 6, iclass 18, count 0 2006.285.20:06:41.89#ibcon#end of sib2, iclass 18, count 0 2006.285.20:06:41.89#ibcon#*mode == 0, iclass 18, count 0 2006.285.20:06:41.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.20:06:41.89#ibcon#[25=USB\r\n] 2006.285.20:06:41.89#ibcon#*before write, iclass 18, count 0 2006.285.20:06:41.89#ibcon#enter sib2, iclass 18, count 0 2006.285.20:06:41.89#ibcon#flushed, iclass 18, count 0 2006.285.20:06:41.89#ibcon#about to write, iclass 18, count 0 2006.285.20:06:41.89#ibcon#wrote, iclass 18, count 0 2006.285.20:06:41.89#ibcon#about to read 3, iclass 18, count 0 2006.285.20:06:41.91#ibcon#read 3, iclass 18, count 0 2006.285.20:06:41.91#ibcon#about to read 4, iclass 18, count 0 2006.285.20:06:41.91#ibcon#read 4, iclass 18, count 0 2006.285.20:06:41.91#ibcon#about to read 5, iclass 18, count 0 2006.285.20:06:41.91#ibcon#read 5, iclass 18, count 0 2006.285.20:06:41.92#ibcon#about to read 6, iclass 18, count 0 2006.285.20:06:41.92#ibcon#read 6, iclass 18, count 0 2006.285.20:06:41.92#ibcon#end of sib2, iclass 18, count 0 2006.285.20:06:41.92#ibcon#*after write, iclass 18, count 0 2006.285.20:06:41.92#ibcon#*before return 0, iclass 18, count 0 2006.285.20:06:41.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:06:41.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:06:41.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.20:06:41.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.20:06:41.92$vck44/valo=7,864.99 2006.285.20:06:41.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.20:06:41.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.20:06:41.92#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:41.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:06:41.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:06:41.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:06:41.92#ibcon#enter wrdev, iclass 20, count 0 2006.285.20:06:41.92#ibcon#first serial, iclass 20, count 0 2006.285.20:06:41.92#ibcon#enter sib2, iclass 20, count 0 2006.285.20:06:41.92#ibcon#flushed, iclass 20, count 0 2006.285.20:06:41.92#ibcon#about to write, iclass 20, count 0 2006.285.20:06:41.92#ibcon#wrote, iclass 20, count 0 2006.285.20:06:41.92#ibcon#about to read 3, iclass 20, count 0 2006.285.20:06:41.93#ibcon#read 3, iclass 20, count 0 2006.285.20:06:41.93#ibcon#about to read 4, iclass 20, count 0 2006.285.20:06:41.93#ibcon#read 4, iclass 20, count 0 2006.285.20:06:41.93#ibcon#about to read 5, iclass 20, count 0 2006.285.20:06:41.94#ibcon#read 5, iclass 20, count 0 2006.285.20:06:41.94#ibcon#about to read 6, iclass 20, count 0 2006.285.20:06:41.94#ibcon#read 6, iclass 20, count 0 2006.285.20:06:41.94#ibcon#end of sib2, iclass 20, count 0 2006.285.20:06:41.94#ibcon#*mode == 0, iclass 20, count 0 2006.285.20:06:41.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.20:06:41.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.20:06:41.94#ibcon#*before write, iclass 20, count 0 2006.285.20:06:41.94#ibcon#enter sib2, iclass 20, count 0 2006.285.20:06:41.94#ibcon#flushed, iclass 20, count 0 2006.285.20:06:41.94#ibcon#about to write, iclass 20, count 0 2006.285.20:06:41.94#ibcon#wrote, iclass 20, count 0 2006.285.20:06:41.94#ibcon#about to read 3, iclass 20, count 0 2006.285.20:06:41.97#ibcon#read 3, iclass 20, count 0 2006.285.20:06:41.97#ibcon#about to read 4, iclass 20, count 0 2006.285.20:06:41.98#ibcon#read 4, iclass 20, count 0 2006.285.20:06:41.98#ibcon#about to read 5, iclass 20, count 0 2006.285.20:06:41.98#ibcon#read 5, iclass 20, count 0 2006.285.20:06:41.98#ibcon#about to read 6, iclass 20, count 0 2006.285.20:06:41.98#ibcon#read 6, iclass 20, count 0 2006.285.20:06:41.98#ibcon#end of sib2, iclass 20, count 0 2006.285.20:06:41.98#ibcon#*after write, iclass 20, count 0 2006.285.20:06:41.98#ibcon#*before return 0, iclass 20, count 0 2006.285.20:06:41.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:06:41.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:06:41.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.20:06:41.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.20:06:41.98$vck44/va=7,4 2006.285.20:06:41.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.20:06:41.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.20:06:41.98#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:41.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:06:42.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:06:42.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:06:42.03#ibcon#enter wrdev, iclass 22, count 2 2006.285.20:06:42.04#ibcon#first serial, iclass 22, count 2 2006.285.20:06:42.04#ibcon#enter sib2, iclass 22, count 2 2006.285.20:06:42.04#ibcon#flushed, iclass 22, count 2 2006.285.20:06:42.04#ibcon#about to write, iclass 22, count 2 2006.285.20:06:42.04#ibcon#wrote, iclass 22, count 2 2006.285.20:06:42.04#ibcon#about to read 3, iclass 22, count 2 2006.285.20:06:42.05#ibcon#read 3, iclass 22, count 2 2006.285.20:06:42.05#ibcon#about to read 4, iclass 22, count 2 2006.285.20:06:42.06#ibcon#read 4, iclass 22, count 2 2006.285.20:06:42.06#ibcon#about to read 5, iclass 22, count 2 2006.285.20:06:42.06#ibcon#read 5, iclass 22, count 2 2006.285.20:06:42.06#ibcon#about to read 6, iclass 22, count 2 2006.285.20:06:42.06#ibcon#read 6, iclass 22, count 2 2006.285.20:06:42.06#ibcon#end of sib2, iclass 22, count 2 2006.285.20:06:42.06#ibcon#*mode == 0, iclass 22, count 2 2006.285.20:06:42.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.20:06:42.06#ibcon#[25=AT07-04\r\n] 2006.285.20:06:42.06#ibcon#*before write, iclass 22, count 2 2006.285.20:06:42.06#ibcon#enter sib2, iclass 22, count 2 2006.285.20:06:42.06#ibcon#flushed, iclass 22, count 2 2006.285.20:06:42.06#ibcon#about to write, iclass 22, count 2 2006.285.20:06:42.06#ibcon#wrote, iclass 22, count 2 2006.285.20:06:42.06#ibcon#about to read 3, iclass 22, count 2 2006.285.20:06:42.08#ibcon#read 3, iclass 22, count 2 2006.285.20:06:42.08#ibcon#about to read 4, iclass 22, count 2 2006.285.20:06:42.08#ibcon#read 4, iclass 22, count 2 2006.285.20:06:42.08#ibcon#about to read 5, iclass 22, count 2 2006.285.20:06:42.08#ibcon#read 5, iclass 22, count 2 2006.285.20:06:42.08#ibcon#about to read 6, iclass 22, count 2 2006.285.20:06:42.08#ibcon#read 6, iclass 22, count 2 2006.285.20:06:42.09#ibcon#end of sib2, iclass 22, count 2 2006.285.20:06:42.09#ibcon#*after write, iclass 22, count 2 2006.285.20:06:42.09#ibcon#*before return 0, iclass 22, count 2 2006.285.20:06:42.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:06:42.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:06:42.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.20:06:42.09#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:42.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:06:42.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:06:42.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:06:42.25#ibcon#enter wrdev, iclass 22, count 0 2006.285.20:06:42.25#ibcon#first serial, iclass 22, count 0 2006.285.20:06:42.25#ibcon#enter sib2, iclass 22, count 0 2006.285.20:06:42.25#ibcon#flushed, iclass 22, count 0 2006.285.20:06:42.25#ibcon#about to write, iclass 22, count 0 2006.285.20:06:42.25#ibcon#wrote, iclass 22, count 0 2006.285.20:06:42.25#ibcon#about to read 3, iclass 22, count 0 2006.285.20:06:42.26#ibcon#read 3, iclass 22, count 0 2006.285.20:06:42.26#ibcon#about to read 4, iclass 22, count 0 2006.285.20:06:42.26#ibcon#read 4, iclass 22, count 0 2006.285.20:06:42.27#ibcon#about to read 5, iclass 22, count 0 2006.285.20:06:42.27#ibcon#read 5, iclass 22, count 0 2006.285.20:06:42.27#ibcon#about to read 6, iclass 22, count 0 2006.285.20:06:42.27#ibcon#read 6, iclass 22, count 0 2006.285.20:06:42.27#ibcon#end of sib2, iclass 22, count 0 2006.285.20:06:42.27#ibcon#*mode == 0, iclass 22, count 0 2006.285.20:06:42.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.20:06:42.27#ibcon#[25=USB\r\n] 2006.285.20:06:42.27#ibcon#*before write, iclass 22, count 0 2006.285.20:06:42.27#ibcon#enter sib2, iclass 22, count 0 2006.285.20:06:42.27#ibcon#flushed, iclass 22, count 0 2006.285.20:06:42.27#ibcon#about to write, iclass 22, count 0 2006.285.20:06:42.27#ibcon#wrote, iclass 22, count 0 2006.285.20:06:42.27#ibcon#about to read 3, iclass 22, count 0 2006.285.20:06:42.29#ibcon#read 3, iclass 22, count 0 2006.285.20:06:42.29#ibcon#about to read 4, iclass 22, count 0 2006.285.20:06:42.29#ibcon#read 4, iclass 22, count 0 2006.285.20:06:42.30#ibcon#about to read 5, iclass 22, count 0 2006.285.20:06:42.30#ibcon#read 5, iclass 22, count 0 2006.285.20:06:42.30#ibcon#about to read 6, iclass 22, count 0 2006.285.20:06:42.30#ibcon#read 6, iclass 22, count 0 2006.285.20:06:42.30#ibcon#end of sib2, iclass 22, count 0 2006.285.20:06:42.30#ibcon#*after write, iclass 22, count 0 2006.285.20:06:42.30#ibcon#*before return 0, iclass 22, count 0 2006.285.20:06:42.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:06:42.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:06:42.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.20:06:42.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.20:06:42.30$vck44/valo=8,884.99 2006.285.20:06:42.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.20:06:42.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.20:06:42.30#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:42.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:06:42.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:06:42.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:06:42.30#ibcon#enter wrdev, iclass 24, count 0 2006.285.20:06:42.30#ibcon#first serial, iclass 24, count 0 2006.285.20:06:42.30#ibcon#enter sib2, iclass 24, count 0 2006.285.20:06:42.30#ibcon#flushed, iclass 24, count 0 2006.285.20:06:42.30#ibcon#about to write, iclass 24, count 0 2006.285.20:06:42.30#ibcon#wrote, iclass 24, count 0 2006.285.20:06:42.30#ibcon#about to read 3, iclass 24, count 0 2006.285.20:06:42.31#ibcon#read 3, iclass 24, count 0 2006.285.20:06:42.31#ibcon#about to read 4, iclass 24, count 0 2006.285.20:06:42.31#ibcon#read 4, iclass 24, count 0 2006.285.20:06:42.32#ibcon#about to read 5, iclass 24, count 0 2006.285.20:06:42.32#ibcon#read 5, iclass 24, count 0 2006.285.20:06:42.32#ibcon#about to read 6, iclass 24, count 0 2006.285.20:06:42.32#ibcon#read 6, iclass 24, count 0 2006.285.20:06:42.32#ibcon#end of sib2, iclass 24, count 0 2006.285.20:06:42.32#ibcon#*mode == 0, iclass 24, count 0 2006.285.20:06:42.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.20:06:42.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.20:06:42.32#ibcon#*before write, iclass 24, count 0 2006.285.20:06:42.32#ibcon#enter sib2, iclass 24, count 0 2006.285.20:06:42.32#ibcon#flushed, iclass 24, count 0 2006.285.20:06:42.32#ibcon#about to write, iclass 24, count 0 2006.285.20:06:42.32#ibcon#wrote, iclass 24, count 0 2006.285.20:06:42.32#ibcon#about to read 3, iclass 24, count 0 2006.285.20:06:42.35#ibcon#read 3, iclass 24, count 0 2006.285.20:06:42.35#ibcon#about to read 4, iclass 24, count 0 2006.285.20:06:42.35#ibcon#read 4, iclass 24, count 0 2006.285.20:06:42.36#ibcon#about to read 5, iclass 24, count 0 2006.285.20:06:42.36#ibcon#read 5, iclass 24, count 0 2006.285.20:06:42.36#ibcon#about to read 6, iclass 24, count 0 2006.285.20:06:42.36#ibcon#read 6, iclass 24, count 0 2006.285.20:06:42.36#ibcon#end of sib2, iclass 24, count 0 2006.285.20:06:42.36#ibcon#*after write, iclass 24, count 0 2006.285.20:06:42.36#ibcon#*before return 0, iclass 24, count 0 2006.285.20:06:42.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:06:42.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:06:42.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.20:06:42.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.20:06:42.36$vck44/va=8,3 2006.285.20:06:42.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.20:06:42.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.20:06:42.36#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:42.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:06:42.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:06:42.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:06:42.41#ibcon#enter wrdev, iclass 26, count 2 2006.285.20:06:42.41#ibcon#first serial, iclass 26, count 2 2006.285.20:06:42.41#ibcon#enter sib2, iclass 26, count 2 2006.285.20:06:42.42#ibcon#flushed, iclass 26, count 2 2006.285.20:06:42.42#ibcon#about to write, iclass 26, count 2 2006.285.20:06:42.42#ibcon#wrote, iclass 26, count 2 2006.285.20:06:42.42#ibcon#about to read 3, iclass 26, count 2 2006.285.20:06:42.43#ibcon#read 3, iclass 26, count 2 2006.285.20:06:42.43#ibcon#about to read 4, iclass 26, count 2 2006.285.20:06:42.43#ibcon#read 4, iclass 26, count 2 2006.285.20:06:42.43#ibcon#about to read 5, iclass 26, count 2 2006.285.20:06:42.43#ibcon#read 5, iclass 26, count 2 2006.285.20:06:42.44#ibcon#about to read 6, iclass 26, count 2 2006.285.20:06:42.44#ibcon#read 6, iclass 26, count 2 2006.285.20:06:42.44#ibcon#end of sib2, iclass 26, count 2 2006.285.20:06:42.44#ibcon#*mode == 0, iclass 26, count 2 2006.285.20:06:42.44#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.20:06:42.44#ibcon#[25=AT08-03\r\n] 2006.285.20:06:42.44#ibcon#*before write, iclass 26, count 2 2006.285.20:06:42.44#ibcon#enter sib2, iclass 26, count 2 2006.285.20:06:42.44#ibcon#flushed, iclass 26, count 2 2006.285.20:06:42.44#ibcon#about to write, iclass 26, count 2 2006.285.20:06:42.44#ibcon#wrote, iclass 26, count 2 2006.285.20:06:42.44#ibcon#about to read 3, iclass 26, count 2 2006.285.20:06:42.46#ibcon#read 3, iclass 26, count 2 2006.285.20:06:42.46#ibcon#about to read 4, iclass 26, count 2 2006.285.20:06:42.46#ibcon#read 4, iclass 26, count 2 2006.285.20:06:42.46#ibcon#about to read 5, iclass 26, count 2 2006.285.20:06:42.46#ibcon#read 5, iclass 26, count 2 2006.285.20:06:42.47#ibcon#about to read 6, iclass 26, count 2 2006.285.20:06:42.47#ibcon#read 6, iclass 26, count 2 2006.285.20:06:42.47#ibcon#end of sib2, iclass 26, count 2 2006.285.20:06:42.47#ibcon#*after write, iclass 26, count 2 2006.285.20:06:42.47#ibcon#*before return 0, iclass 26, count 2 2006.285.20:06:42.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:06:42.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:06:42.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.20:06:42.47#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:42.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:06:42.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:06:42.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:06:42.58#ibcon#enter wrdev, iclass 26, count 0 2006.285.20:06:42.58#ibcon#first serial, iclass 26, count 0 2006.285.20:06:42.58#ibcon#enter sib2, iclass 26, count 0 2006.285.20:06:42.58#ibcon#flushed, iclass 26, count 0 2006.285.20:06:42.59#ibcon#about to write, iclass 26, count 0 2006.285.20:06:42.59#ibcon#wrote, iclass 26, count 0 2006.285.20:06:42.59#ibcon#about to read 3, iclass 26, count 0 2006.285.20:06:42.60#ibcon#read 3, iclass 26, count 0 2006.285.20:06:42.60#ibcon#about to read 4, iclass 26, count 0 2006.285.20:06:42.60#ibcon#read 4, iclass 26, count 0 2006.285.20:06:42.60#ibcon#about to read 5, iclass 26, count 0 2006.285.20:06:42.60#ibcon#read 5, iclass 26, count 0 2006.285.20:06:42.60#ibcon#about to read 6, iclass 26, count 0 2006.285.20:06:42.61#ibcon#read 6, iclass 26, count 0 2006.285.20:06:42.61#ibcon#end of sib2, iclass 26, count 0 2006.285.20:06:42.61#ibcon#*mode == 0, iclass 26, count 0 2006.285.20:06:42.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.20:06:42.61#ibcon#[25=USB\r\n] 2006.285.20:06:42.61#ibcon#*before write, iclass 26, count 0 2006.285.20:06:42.61#ibcon#enter sib2, iclass 26, count 0 2006.285.20:06:42.61#ibcon#flushed, iclass 26, count 0 2006.285.20:06:42.61#ibcon#about to write, iclass 26, count 0 2006.285.20:06:42.61#ibcon#wrote, iclass 26, count 0 2006.285.20:06:42.61#ibcon#about to read 3, iclass 26, count 0 2006.285.20:06:42.63#ibcon#read 3, iclass 26, count 0 2006.285.20:06:42.63#ibcon#about to read 4, iclass 26, count 0 2006.285.20:06:42.63#ibcon#read 4, iclass 26, count 0 2006.285.20:06:42.63#ibcon#about to read 5, iclass 26, count 0 2006.285.20:06:42.63#ibcon#read 5, iclass 26, count 0 2006.285.20:06:42.63#ibcon#about to read 6, iclass 26, count 0 2006.285.20:06:42.64#ibcon#read 6, iclass 26, count 0 2006.285.20:06:42.64#ibcon#end of sib2, iclass 26, count 0 2006.285.20:06:42.64#ibcon#*after write, iclass 26, count 0 2006.285.20:06:42.64#ibcon#*before return 0, iclass 26, count 0 2006.285.20:06:42.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:06:42.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:06:42.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.20:06:42.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.20:06:42.64$vck44/vblo=1,629.99 2006.285.20:06:42.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.20:06:42.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.20:06:42.64#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:42.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.20:06:42.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.20:06:42.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.20:06:42.64#ibcon#enter wrdev, iclass 28, count 0 2006.285.20:06:42.64#ibcon#first serial, iclass 28, count 0 2006.285.20:06:42.64#ibcon#enter sib2, iclass 28, count 0 2006.285.20:06:42.64#ibcon#flushed, iclass 28, count 0 2006.285.20:06:42.64#ibcon#about to write, iclass 28, count 0 2006.285.20:06:42.64#ibcon#wrote, iclass 28, count 0 2006.285.20:06:42.64#ibcon#about to read 3, iclass 28, count 0 2006.285.20:06:42.65#ibcon#read 3, iclass 28, count 0 2006.285.20:06:42.65#ibcon#about to read 4, iclass 28, count 0 2006.285.20:06:42.65#ibcon#read 4, iclass 28, count 0 2006.285.20:06:42.65#ibcon#about to read 5, iclass 28, count 0 2006.285.20:06:42.65#ibcon#read 5, iclass 28, count 0 2006.285.20:06:42.66#ibcon#about to read 6, iclass 28, count 0 2006.285.20:06:42.66#ibcon#read 6, iclass 28, count 0 2006.285.20:06:42.66#ibcon#end of sib2, iclass 28, count 0 2006.285.20:06:42.66#ibcon#*mode == 0, iclass 28, count 0 2006.285.20:06:42.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.20:06:42.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.20:06:42.66#ibcon#*before write, iclass 28, count 0 2006.285.20:06:42.66#ibcon#enter sib2, iclass 28, count 0 2006.285.20:06:42.66#ibcon#flushed, iclass 28, count 0 2006.285.20:06:42.66#ibcon#about to write, iclass 28, count 0 2006.285.20:06:42.66#ibcon#wrote, iclass 28, count 0 2006.285.20:06:42.66#ibcon#about to read 3, iclass 28, count 0 2006.285.20:06:42.69#ibcon#read 3, iclass 28, count 0 2006.285.20:06:42.69#ibcon#about to read 4, iclass 28, count 0 2006.285.20:06:42.69#ibcon#read 4, iclass 28, count 0 2006.285.20:06:42.69#ibcon#about to read 5, iclass 28, count 0 2006.285.20:06:42.69#ibcon#read 5, iclass 28, count 0 2006.285.20:06:42.70#ibcon#about to read 6, iclass 28, count 0 2006.285.20:06:42.70#ibcon#read 6, iclass 28, count 0 2006.285.20:06:42.70#ibcon#end of sib2, iclass 28, count 0 2006.285.20:06:42.70#ibcon#*after write, iclass 28, count 0 2006.285.20:06:42.70#ibcon#*before return 0, iclass 28, count 0 2006.285.20:06:42.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.20:06:42.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.20:06:42.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.20:06:42.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.20:06:42.70$vck44/vb=1,4 2006.285.20:06:42.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.20:06:42.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.20:06:42.70#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:42.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.20:06:42.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.20:06:42.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.20:06:42.70#ibcon#enter wrdev, iclass 30, count 2 2006.285.20:06:42.70#ibcon#first serial, iclass 30, count 2 2006.285.20:06:42.70#ibcon#enter sib2, iclass 30, count 2 2006.285.20:06:42.70#ibcon#flushed, iclass 30, count 2 2006.285.20:06:42.70#ibcon#about to write, iclass 30, count 2 2006.285.20:06:42.70#ibcon#wrote, iclass 30, count 2 2006.285.20:06:42.70#ibcon#about to read 3, iclass 30, count 2 2006.285.20:06:42.71#ibcon#read 3, iclass 30, count 2 2006.285.20:06:42.71#ibcon#about to read 4, iclass 30, count 2 2006.285.20:06:42.71#ibcon#read 4, iclass 30, count 2 2006.285.20:06:42.71#ibcon#about to read 5, iclass 30, count 2 2006.285.20:06:42.71#ibcon#read 5, iclass 30, count 2 2006.285.20:06:42.72#ibcon#about to read 6, iclass 30, count 2 2006.285.20:06:42.72#ibcon#read 6, iclass 30, count 2 2006.285.20:06:42.72#ibcon#end of sib2, iclass 30, count 2 2006.285.20:06:42.72#ibcon#*mode == 0, iclass 30, count 2 2006.285.20:06:42.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.20:06:42.72#ibcon#[27=AT01-04\r\n] 2006.285.20:06:42.72#ibcon#*before write, iclass 30, count 2 2006.285.20:06:42.72#ibcon#enter sib2, iclass 30, count 2 2006.285.20:06:42.72#ibcon#flushed, iclass 30, count 2 2006.285.20:06:42.72#ibcon#about to write, iclass 30, count 2 2006.285.20:06:42.72#ibcon#wrote, iclass 30, count 2 2006.285.20:06:42.72#ibcon#about to read 3, iclass 30, count 2 2006.285.20:06:42.74#ibcon#read 3, iclass 30, count 2 2006.285.20:06:42.74#ibcon#about to read 4, iclass 30, count 2 2006.285.20:06:42.74#ibcon#read 4, iclass 30, count 2 2006.285.20:06:42.74#ibcon#about to read 5, iclass 30, count 2 2006.285.20:06:42.75#ibcon#read 5, iclass 30, count 2 2006.285.20:06:42.75#ibcon#about to read 6, iclass 30, count 2 2006.285.20:06:42.75#ibcon#read 6, iclass 30, count 2 2006.285.20:06:42.75#ibcon#end of sib2, iclass 30, count 2 2006.285.20:06:42.75#ibcon#*after write, iclass 30, count 2 2006.285.20:06:42.75#ibcon#*before return 0, iclass 30, count 2 2006.285.20:06:42.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.20:06:42.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.20:06:42.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.20:06:42.75#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:42.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.20:06:42.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.20:06:42.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.20:06:42.86#ibcon#enter wrdev, iclass 30, count 0 2006.285.20:06:42.86#ibcon#first serial, iclass 30, count 0 2006.285.20:06:42.86#ibcon#enter sib2, iclass 30, count 0 2006.285.20:06:42.86#ibcon#flushed, iclass 30, count 0 2006.285.20:06:42.87#ibcon#about to write, iclass 30, count 0 2006.285.20:06:42.87#ibcon#wrote, iclass 30, count 0 2006.285.20:06:42.87#ibcon#about to read 3, iclass 30, count 0 2006.285.20:06:42.88#ibcon#read 3, iclass 30, count 0 2006.285.20:06:42.88#ibcon#about to read 4, iclass 30, count 0 2006.285.20:06:42.88#ibcon#read 4, iclass 30, count 0 2006.285.20:06:42.88#ibcon#about to read 5, iclass 30, count 0 2006.285.20:06:42.88#ibcon#read 5, iclass 30, count 0 2006.285.20:06:42.88#ibcon#about to read 6, iclass 30, count 0 2006.285.20:06:42.89#ibcon#read 6, iclass 30, count 0 2006.285.20:06:42.89#ibcon#end of sib2, iclass 30, count 0 2006.285.20:06:42.89#ibcon#*mode == 0, iclass 30, count 0 2006.285.20:06:42.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.20:06:42.89#ibcon#[27=USB\r\n] 2006.285.20:06:42.89#ibcon#*before write, iclass 30, count 0 2006.285.20:06:42.89#ibcon#enter sib2, iclass 30, count 0 2006.285.20:06:42.89#ibcon#flushed, iclass 30, count 0 2006.285.20:06:42.89#ibcon#about to write, iclass 30, count 0 2006.285.20:06:42.89#ibcon#wrote, iclass 30, count 0 2006.285.20:06:42.89#ibcon#about to read 3, iclass 30, count 0 2006.285.20:06:42.91#ibcon#read 3, iclass 30, count 0 2006.285.20:06:42.91#ibcon#about to read 4, iclass 30, count 0 2006.285.20:06:42.91#ibcon#read 4, iclass 30, count 0 2006.285.20:06:42.91#ibcon#about to read 5, iclass 30, count 0 2006.285.20:06:42.91#ibcon#read 5, iclass 30, count 0 2006.285.20:06:42.92#ibcon#about to read 6, iclass 30, count 0 2006.285.20:06:42.92#ibcon#read 6, iclass 30, count 0 2006.285.20:06:42.92#ibcon#end of sib2, iclass 30, count 0 2006.285.20:06:42.92#ibcon#*after write, iclass 30, count 0 2006.285.20:06:42.92#ibcon#*before return 0, iclass 30, count 0 2006.285.20:06:42.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.20:06:42.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.20:06:42.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.20:06:42.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.20:06:42.92$vck44/vblo=2,634.99 2006.285.20:06:42.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.20:06:42.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.20:06:42.92#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:42.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:06:42.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:06:42.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:06:42.92#ibcon#enter wrdev, iclass 32, count 0 2006.285.20:06:42.92#ibcon#first serial, iclass 32, count 0 2006.285.20:06:42.92#ibcon#enter sib2, iclass 32, count 0 2006.285.20:06:42.92#ibcon#flushed, iclass 32, count 0 2006.285.20:06:42.92#ibcon#about to write, iclass 32, count 0 2006.285.20:06:42.92#ibcon#wrote, iclass 32, count 0 2006.285.20:06:42.92#ibcon#about to read 3, iclass 32, count 0 2006.285.20:06:42.93#ibcon#read 3, iclass 32, count 0 2006.285.20:06:42.93#ibcon#about to read 4, iclass 32, count 0 2006.285.20:06:42.93#ibcon#read 4, iclass 32, count 0 2006.285.20:06:42.93#ibcon#about to read 5, iclass 32, count 0 2006.285.20:06:42.94#ibcon#read 5, iclass 32, count 0 2006.285.20:06:42.94#ibcon#about to read 6, iclass 32, count 0 2006.285.20:06:42.94#ibcon#read 6, iclass 32, count 0 2006.285.20:06:42.94#ibcon#end of sib2, iclass 32, count 0 2006.285.20:06:42.94#ibcon#*mode == 0, iclass 32, count 0 2006.285.20:06:42.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.20:06:42.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.20:06:42.94#ibcon#*before write, iclass 32, count 0 2006.285.20:06:42.94#ibcon#enter sib2, iclass 32, count 0 2006.285.20:06:42.94#ibcon#flushed, iclass 32, count 0 2006.285.20:06:42.94#ibcon#about to write, iclass 32, count 0 2006.285.20:06:42.94#ibcon#wrote, iclass 32, count 0 2006.285.20:06:42.94#ibcon#about to read 3, iclass 32, count 0 2006.285.20:06:42.97#ibcon#read 3, iclass 32, count 0 2006.285.20:06:42.97#ibcon#about to read 4, iclass 32, count 0 2006.285.20:06:42.97#ibcon#read 4, iclass 32, count 0 2006.285.20:06:42.97#ibcon#about to read 5, iclass 32, count 0 2006.285.20:06:42.97#ibcon#read 5, iclass 32, count 0 2006.285.20:06:42.97#ibcon#about to read 6, iclass 32, count 0 2006.285.20:06:42.98#ibcon#read 6, iclass 32, count 0 2006.285.20:06:42.98#ibcon#end of sib2, iclass 32, count 0 2006.285.20:06:42.98#ibcon#*after write, iclass 32, count 0 2006.285.20:06:42.98#ibcon#*before return 0, iclass 32, count 0 2006.285.20:06:42.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:06:42.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:06:42.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.20:06:42.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.20:06:42.98$vck44/vb=2,5 2006.285.20:06:42.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.20:06:42.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.20:06:42.98#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:42.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:06:43.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:06:43.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:06:43.03#ibcon#enter wrdev, iclass 34, count 2 2006.285.20:06:43.04#ibcon#first serial, iclass 34, count 2 2006.285.20:06:43.04#ibcon#enter sib2, iclass 34, count 2 2006.285.20:06:43.04#ibcon#flushed, iclass 34, count 2 2006.285.20:06:43.04#ibcon#about to write, iclass 34, count 2 2006.285.20:06:43.04#ibcon#wrote, iclass 34, count 2 2006.285.20:06:43.04#ibcon#about to read 3, iclass 34, count 2 2006.285.20:06:43.05#ibcon#read 3, iclass 34, count 2 2006.285.20:06:43.05#ibcon#about to read 4, iclass 34, count 2 2006.285.20:06:43.05#ibcon#read 4, iclass 34, count 2 2006.285.20:06:43.05#ibcon#about to read 5, iclass 34, count 2 2006.285.20:06:43.05#ibcon#read 5, iclass 34, count 2 2006.285.20:06:43.05#ibcon#about to read 6, iclass 34, count 2 2006.285.20:06:43.06#ibcon#read 6, iclass 34, count 2 2006.285.20:06:43.06#ibcon#end of sib2, iclass 34, count 2 2006.285.20:06:43.06#ibcon#*mode == 0, iclass 34, count 2 2006.285.20:06:43.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.20:06:43.06#ibcon#[27=AT02-05\r\n] 2006.285.20:06:43.06#ibcon#*before write, iclass 34, count 2 2006.285.20:06:43.06#ibcon#enter sib2, iclass 34, count 2 2006.285.20:06:43.06#ibcon#flushed, iclass 34, count 2 2006.285.20:06:43.06#ibcon#about to write, iclass 34, count 2 2006.285.20:06:43.06#ibcon#wrote, iclass 34, count 2 2006.285.20:06:43.06#ibcon#about to read 3, iclass 34, count 2 2006.285.20:06:43.08#ibcon#read 3, iclass 34, count 2 2006.285.20:06:43.08#ibcon#about to read 4, iclass 34, count 2 2006.285.20:06:43.08#ibcon#read 4, iclass 34, count 2 2006.285.20:06:43.08#ibcon#about to read 5, iclass 34, count 2 2006.285.20:06:43.09#ibcon#read 5, iclass 34, count 2 2006.285.20:06:43.09#ibcon#about to read 6, iclass 34, count 2 2006.285.20:06:43.09#ibcon#read 6, iclass 34, count 2 2006.285.20:06:43.09#ibcon#end of sib2, iclass 34, count 2 2006.285.20:06:43.09#ibcon#*after write, iclass 34, count 2 2006.285.20:06:43.09#ibcon#*before return 0, iclass 34, count 2 2006.285.20:06:43.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:06:43.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:06:43.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.20:06:43.09#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:43.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:06:43.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:06:43.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:06:43.22#ibcon#enter wrdev, iclass 34, count 0 2006.285.20:06:43.22#ibcon#first serial, iclass 34, count 0 2006.285.20:06:43.22#ibcon#enter sib2, iclass 34, count 0 2006.285.20:06:43.22#ibcon#flushed, iclass 34, count 0 2006.285.20:06:43.22#ibcon#about to write, iclass 34, count 0 2006.285.20:06:43.22#ibcon#wrote, iclass 34, count 0 2006.285.20:06:43.22#ibcon#about to read 3, iclass 34, count 0 2006.285.20:06:43.23#ibcon#read 3, iclass 34, count 0 2006.285.20:06:43.23#ibcon#about to read 4, iclass 34, count 0 2006.285.20:06:43.24#ibcon#read 4, iclass 34, count 0 2006.285.20:06:43.24#ibcon#about to read 5, iclass 34, count 0 2006.285.20:06:43.24#ibcon#read 5, iclass 34, count 0 2006.285.20:06:43.24#ibcon#about to read 6, iclass 34, count 0 2006.285.20:06:43.24#ibcon#read 6, iclass 34, count 0 2006.285.20:06:43.24#ibcon#end of sib2, iclass 34, count 0 2006.285.20:06:43.24#ibcon#*mode == 0, iclass 34, count 0 2006.285.20:06:43.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.20:06:43.24#ibcon#[27=USB\r\n] 2006.285.20:06:43.24#ibcon#*before write, iclass 34, count 0 2006.285.20:06:43.24#ibcon#enter sib2, iclass 34, count 0 2006.285.20:06:43.24#ibcon#flushed, iclass 34, count 0 2006.285.20:06:43.24#ibcon#about to write, iclass 34, count 0 2006.285.20:06:43.24#ibcon#wrote, iclass 34, count 0 2006.285.20:06:43.24#ibcon#about to read 3, iclass 34, count 0 2006.285.20:06:43.26#ibcon#read 3, iclass 34, count 0 2006.285.20:06:43.26#ibcon#about to read 4, iclass 34, count 0 2006.285.20:06:43.26#ibcon#read 4, iclass 34, count 0 2006.285.20:06:43.27#ibcon#about to read 5, iclass 34, count 0 2006.285.20:06:43.27#ibcon#read 5, iclass 34, count 0 2006.285.20:06:43.27#ibcon#about to read 6, iclass 34, count 0 2006.285.20:06:43.27#ibcon#read 6, iclass 34, count 0 2006.285.20:06:43.27#ibcon#end of sib2, iclass 34, count 0 2006.285.20:06:43.27#ibcon#*after write, iclass 34, count 0 2006.285.20:06:43.27#ibcon#*before return 0, iclass 34, count 0 2006.285.20:06:43.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:06:43.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:06:43.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.20:06:43.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.20:06:43.27$vck44/vblo=3,649.99 2006.285.20:06:43.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.20:06:43.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.20:06:43.27#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:43.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:06:43.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:06:43.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:06:43.27#ibcon#enter wrdev, iclass 36, count 0 2006.285.20:06:43.27#ibcon#first serial, iclass 36, count 0 2006.285.20:06:43.27#ibcon#enter sib2, iclass 36, count 0 2006.285.20:06:43.27#ibcon#flushed, iclass 36, count 0 2006.285.20:06:43.27#ibcon#about to write, iclass 36, count 0 2006.285.20:06:43.27#ibcon#wrote, iclass 36, count 0 2006.285.20:06:43.27#ibcon#about to read 3, iclass 36, count 0 2006.285.20:06:43.28#ibcon#read 3, iclass 36, count 0 2006.285.20:06:43.28#ibcon#about to read 4, iclass 36, count 0 2006.285.20:06:43.28#ibcon#read 4, iclass 36, count 0 2006.285.20:06:43.28#ibcon#about to read 5, iclass 36, count 0 2006.285.20:06:43.29#ibcon#read 5, iclass 36, count 0 2006.285.20:06:43.29#ibcon#about to read 6, iclass 36, count 0 2006.285.20:06:43.29#ibcon#read 6, iclass 36, count 0 2006.285.20:06:43.29#ibcon#end of sib2, iclass 36, count 0 2006.285.20:06:43.29#ibcon#*mode == 0, iclass 36, count 0 2006.285.20:06:43.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.20:06:43.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.20:06:43.29#ibcon#*before write, iclass 36, count 0 2006.285.20:06:43.29#ibcon#enter sib2, iclass 36, count 0 2006.285.20:06:43.29#ibcon#flushed, iclass 36, count 0 2006.285.20:06:43.29#ibcon#about to write, iclass 36, count 0 2006.285.20:06:43.29#ibcon#wrote, iclass 36, count 0 2006.285.20:06:43.29#ibcon#about to read 3, iclass 36, count 0 2006.285.20:06:43.32#ibcon#read 3, iclass 36, count 0 2006.285.20:06:43.32#ibcon#about to read 4, iclass 36, count 0 2006.285.20:06:43.32#ibcon#read 4, iclass 36, count 0 2006.285.20:06:43.33#ibcon#about to read 5, iclass 36, count 0 2006.285.20:06:43.33#ibcon#read 5, iclass 36, count 0 2006.285.20:06:43.33#ibcon#about to read 6, iclass 36, count 0 2006.285.20:06:43.33#ibcon#read 6, iclass 36, count 0 2006.285.20:06:43.33#ibcon#end of sib2, iclass 36, count 0 2006.285.20:06:43.33#ibcon#*after write, iclass 36, count 0 2006.285.20:06:43.33#ibcon#*before return 0, iclass 36, count 0 2006.285.20:06:43.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:06:43.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:06:43.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.20:06:43.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.20:06:43.33$vck44/vb=3,4 2006.285.20:06:43.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.20:06:43.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.20:06:43.33#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:43.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:06:43.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:06:43.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:06:43.38#ibcon#enter wrdev, iclass 38, count 2 2006.285.20:06:43.38#ibcon#first serial, iclass 38, count 2 2006.285.20:06:43.38#ibcon#enter sib2, iclass 38, count 2 2006.285.20:06:43.39#ibcon#flushed, iclass 38, count 2 2006.285.20:06:43.39#ibcon#about to write, iclass 38, count 2 2006.285.20:06:43.39#ibcon#wrote, iclass 38, count 2 2006.285.20:06:43.39#ibcon#about to read 3, iclass 38, count 2 2006.285.20:06:43.40#ibcon#read 3, iclass 38, count 2 2006.285.20:06:43.40#ibcon#about to read 4, iclass 38, count 2 2006.285.20:06:43.40#ibcon#read 4, iclass 38, count 2 2006.285.20:06:43.40#ibcon#about to read 5, iclass 38, count 2 2006.285.20:06:43.41#ibcon#read 5, iclass 38, count 2 2006.285.20:06:43.41#ibcon#about to read 6, iclass 38, count 2 2006.285.20:06:43.41#ibcon#read 6, iclass 38, count 2 2006.285.20:06:43.41#ibcon#end of sib2, iclass 38, count 2 2006.285.20:06:43.41#ibcon#*mode == 0, iclass 38, count 2 2006.285.20:06:43.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.20:06:43.41#ibcon#[27=AT03-04\r\n] 2006.285.20:06:43.41#ibcon#*before write, iclass 38, count 2 2006.285.20:06:43.41#ibcon#enter sib2, iclass 38, count 2 2006.285.20:06:43.41#ibcon#flushed, iclass 38, count 2 2006.285.20:06:43.41#ibcon#about to write, iclass 38, count 2 2006.285.20:06:43.41#ibcon#wrote, iclass 38, count 2 2006.285.20:06:43.41#ibcon#about to read 3, iclass 38, count 2 2006.285.20:06:43.43#ibcon#read 3, iclass 38, count 2 2006.285.20:06:43.43#ibcon#about to read 4, iclass 38, count 2 2006.285.20:06:43.43#ibcon#read 4, iclass 38, count 2 2006.285.20:06:43.43#ibcon#about to read 5, iclass 38, count 2 2006.285.20:06:43.44#ibcon#read 5, iclass 38, count 2 2006.285.20:06:43.44#ibcon#about to read 6, iclass 38, count 2 2006.285.20:06:43.44#ibcon#read 6, iclass 38, count 2 2006.285.20:06:43.44#ibcon#end of sib2, iclass 38, count 2 2006.285.20:06:43.44#ibcon#*after write, iclass 38, count 2 2006.285.20:06:43.44#ibcon#*before return 0, iclass 38, count 2 2006.285.20:06:43.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:06:43.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:06:43.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.20:06:43.44#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:43.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:06:43.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:06:43.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:06:43.55#ibcon#enter wrdev, iclass 38, count 0 2006.285.20:06:43.55#ibcon#first serial, iclass 38, count 0 2006.285.20:06:43.55#ibcon#enter sib2, iclass 38, count 0 2006.285.20:06:43.56#ibcon#flushed, iclass 38, count 0 2006.285.20:06:43.56#ibcon#about to write, iclass 38, count 0 2006.285.20:06:43.56#ibcon#wrote, iclass 38, count 0 2006.285.20:06:43.56#ibcon#about to read 3, iclass 38, count 0 2006.285.20:06:43.57#ibcon#read 3, iclass 38, count 0 2006.285.20:06:43.57#ibcon#about to read 4, iclass 38, count 0 2006.285.20:06:43.57#ibcon#read 4, iclass 38, count 0 2006.285.20:06:43.57#ibcon#about to read 5, iclass 38, count 0 2006.285.20:06:43.57#ibcon#read 5, iclass 38, count 0 2006.285.20:06:43.57#ibcon#about to read 6, iclass 38, count 0 2006.285.20:06:43.58#ibcon#read 6, iclass 38, count 0 2006.285.20:06:43.58#ibcon#end of sib2, iclass 38, count 0 2006.285.20:06:43.58#ibcon#*mode == 0, iclass 38, count 0 2006.285.20:06:43.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.20:06:43.58#ibcon#[27=USB\r\n] 2006.285.20:06:43.58#ibcon#*before write, iclass 38, count 0 2006.285.20:06:43.58#ibcon#enter sib2, iclass 38, count 0 2006.285.20:06:43.58#ibcon#flushed, iclass 38, count 0 2006.285.20:06:43.58#ibcon#about to write, iclass 38, count 0 2006.285.20:06:43.58#ibcon#wrote, iclass 38, count 0 2006.285.20:06:43.58#ibcon#about to read 3, iclass 38, count 0 2006.285.20:06:43.60#ibcon#read 3, iclass 38, count 0 2006.285.20:06:43.60#ibcon#about to read 4, iclass 38, count 0 2006.285.20:06:43.60#ibcon#read 4, iclass 38, count 0 2006.285.20:06:43.60#ibcon#about to read 5, iclass 38, count 0 2006.285.20:06:43.60#ibcon#read 5, iclass 38, count 0 2006.285.20:06:43.60#ibcon#about to read 6, iclass 38, count 0 2006.285.20:06:43.61#ibcon#read 6, iclass 38, count 0 2006.285.20:06:43.61#ibcon#end of sib2, iclass 38, count 0 2006.285.20:06:43.61#ibcon#*after write, iclass 38, count 0 2006.285.20:06:43.61#ibcon#*before return 0, iclass 38, count 0 2006.285.20:06:43.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:06:43.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:06:43.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.20:06:43.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.20:06:43.61$vck44/vblo=4,679.99 2006.285.20:06:43.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.20:06:43.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.20:06:43.61#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:43.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:06:43.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:06:43.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:06:43.61#ibcon#enter wrdev, iclass 40, count 0 2006.285.20:06:43.61#ibcon#first serial, iclass 40, count 0 2006.285.20:06:43.61#ibcon#enter sib2, iclass 40, count 0 2006.285.20:06:43.61#ibcon#flushed, iclass 40, count 0 2006.285.20:06:43.61#ibcon#about to write, iclass 40, count 0 2006.285.20:06:43.61#ibcon#wrote, iclass 40, count 0 2006.285.20:06:43.61#ibcon#about to read 3, iclass 40, count 0 2006.285.20:06:43.62#ibcon#read 3, iclass 40, count 0 2006.285.20:06:43.62#ibcon#about to read 4, iclass 40, count 0 2006.285.20:06:43.62#ibcon#read 4, iclass 40, count 0 2006.285.20:06:43.62#ibcon#about to read 5, iclass 40, count 0 2006.285.20:06:43.62#ibcon#read 5, iclass 40, count 0 2006.285.20:06:43.63#ibcon#about to read 6, iclass 40, count 0 2006.285.20:06:43.63#ibcon#read 6, iclass 40, count 0 2006.285.20:06:43.63#ibcon#end of sib2, iclass 40, count 0 2006.285.20:06:43.63#ibcon#*mode == 0, iclass 40, count 0 2006.285.20:06:43.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.20:06:43.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.20:06:43.63#ibcon#*before write, iclass 40, count 0 2006.285.20:06:43.63#ibcon#enter sib2, iclass 40, count 0 2006.285.20:06:43.63#ibcon#flushed, iclass 40, count 0 2006.285.20:06:43.63#ibcon#about to write, iclass 40, count 0 2006.285.20:06:43.63#ibcon#wrote, iclass 40, count 0 2006.285.20:06:43.63#ibcon#about to read 3, iclass 40, count 0 2006.285.20:06:43.66#ibcon#read 3, iclass 40, count 0 2006.285.20:06:43.66#ibcon#about to read 4, iclass 40, count 0 2006.285.20:06:43.66#ibcon#read 4, iclass 40, count 0 2006.285.20:06:43.66#ibcon#about to read 5, iclass 40, count 0 2006.285.20:06:43.66#ibcon#read 5, iclass 40, count 0 2006.285.20:06:43.66#ibcon#about to read 6, iclass 40, count 0 2006.285.20:06:43.67#ibcon#read 6, iclass 40, count 0 2006.285.20:06:43.67#ibcon#end of sib2, iclass 40, count 0 2006.285.20:06:43.67#ibcon#*after write, iclass 40, count 0 2006.285.20:06:43.67#ibcon#*before return 0, iclass 40, count 0 2006.285.20:06:43.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:06:43.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:06:43.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.20:06:43.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.20:06:43.67$vck44/vb=4,5 2006.285.20:06:43.67#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.20:06:43.67#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.20:06:43.67#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:43.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:06:43.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:06:43.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:06:43.72#ibcon#enter wrdev, iclass 4, count 2 2006.285.20:06:43.72#ibcon#first serial, iclass 4, count 2 2006.285.20:06:43.72#ibcon#enter sib2, iclass 4, count 2 2006.285.20:06:43.72#ibcon#flushed, iclass 4, count 2 2006.285.20:06:43.73#ibcon#about to write, iclass 4, count 2 2006.285.20:06:43.73#ibcon#wrote, iclass 4, count 2 2006.285.20:06:43.73#ibcon#about to read 3, iclass 4, count 2 2006.285.20:06:43.74#ibcon#read 3, iclass 4, count 2 2006.285.20:06:43.74#ibcon#about to read 4, iclass 4, count 2 2006.285.20:06:43.74#ibcon#read 4, iclass 4, count 2 2006.285.20:06:43.74#ibcon#about to read 5, iclass 4, count 2 2006.285.20:06:43.74#ibcon#read 5, iclass 4, count 2 2006.285.20:06:43.74#ibcon#about to read 6, iclass 4, count 2 2006.285.20:06:43.75#ibcon#read 6, iclass 4, count 2 2006.285.20:06:43.75#ibcon#end of sib2, iclass 4, count 2 2006.285.20:06:43.75#ibcon#*mode == 0, iclass 4, count 2 2006.285.20:06:43.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.20:06:43.75#ibcon#[27=AT04-05\r\n] 2006.285.20:06:43.75#ibcon#*before write, iclass 4, count 2 2006.285.20:06:43.75#ibcon#enter sib2, iclass 4, count 2 2006.285.20:06:43.75#ibcon#flushed, iclass 4, count 2 2006.285.20:06:43.75#ibcon#about to write, iclass 4, count 2 2006.285.20:06:43.75#ibcon#wrote, iclass 4, count 2 2006.285.20:06:43.75#ibcon#about to read 3, iclass 4, count 2 2006.285.20:06:43.77#ibcon#read 3, iclass 4, count 2 2006.285.20:06:43.77#ibcon#about to read 4, iclass 4, count 2 2006.285.20:06:43.77#ibcon#read 4, iclass 4, count 2 2006.285.20:06:43.77#ibcon#about to read 5, iclass 4, count 2 2006.285.20:06:43.77#ibcon#read 5, iclass 4, count 2 2006.285.20:06:43.78#ibcon#about to read 6, iclass 4, count 2 2006.285.20:06:43.78#ibcon#read 6, iclass 4, count 2 2006.285.20:06:43.78#ibcon#end of sib2, iclass 4, count 2 2006.285.20:06:43.78#ibcon#*after write, iclass 4, count 2 2006.285.20:06:43.78#ibcon#*before return 0, iclass 4, count 2 2006.285.20:06:43.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:06:43.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:06:43.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.20:06:43.78#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:43.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:06:43.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:06:43.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:06:43.89#ibcon#enter wrdev, iclass 4, count 0 2006.285.20:06:43.89#ibcon#first serial, iclass 4, count 0 2006.285.20:06:43.89#ibcon#enter sib2, iclass 4, count 0 2006.285.20:06:43.89#ibcon#flushed, iclass 4, count 0 2006.285.20:06:43.89#ibcon#about to write, iclass 4, count 0 2006.285.20:06:43.90#ibcon#wrote, iclass 4, count 0 2006.285.20:06:43.90#ibcon#about to read 3, iclass 4, count 0 2006.285.20:06:43.91#ibcon#read 3, iclass 4, count 0 2006.285.20:06:43.91#ibcon#about to read 4, iclass 4, count 0 2006.285.20:06:43.91#ibcon#read 4, iclass 4, count 0 2006.285.20:06:43.91#ibcon#about to read 5, iclass 4, count 0 2006.285.20:06:43.91#ibcon#read 5, iclass 4, count 0 2006.285.20:06:43.91#ibcon#about to read 6, iclass 4, count 0 2006.285.20:06:43.92#ibcon#read 6, iclass 4, count 0 2006.285.20:06:43.92#ibcon#end of sib2, iclass 4, count 0 2006.285.20:06:43.92#ibcon#*mode == 0, iclass 4, count 0 2006.285.20:06:43.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.20:06:43.92#ibcon#[27=USB\r\n] 2006.285.20:06:43.92#ibcon#*before write, iclass 4, count 0 2006.285.20:06:43.92#ibcon#enter sib2, iclass 4, count 0 2006.285.20:06:43.92#ibcon#flushed, iclass 4, count 0 2006.285.20:06:43.92#ibcon#about to write, iclass 4, count 0 2006.285.20:06:43.92#ibcon#wrote, iclass 4, count 0 2006.285.20:06:43.92#ibcon#about to read 3, iclass 4, count 0 2006.285.20:06:43.94#ibcon#read 3, iclass 4, count 0 2006.285.20:06:43.94#ibcon#about to read 4, iclass 4, count 0 2006.285.20:06:43.94#ibcon#read 4, iclass 4, count 0 2006.285.20:06:43.94#ibcon#about to read 5, iclass 4, count 0 2006.285.20:06:43.94#ibcon#read 5, iclass 4, count 0 2006.285.20:06:43.95#ibcon#about to read 6, iclass 4, count 0 2006.285.20:06:43.95#ibcon#read 6, iclass 4, count 0 2006.285.20:06:43.95#ibcon#end of sib2, iclass 4, count 0 2006.285.20:06:43.95#ibcon#*after write, iclass 4, count 0 2006.285.20:06:43.95#ibcon#*before return 0, iclass 4, count 0 2006.285.20:06:43.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:06:43.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:06:43.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.20:06:43.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.20:06:43.95$vck44/vblo=5,709.99 2006.285.20:06:43.95#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.20:06:43.95#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.20:06:43.95#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:43.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:06:43.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:06:43.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:06:43.95#ibcon#enter wrdev, iclass 6, count 0 2006.285.20:06:43.95#ibcon#first serial, iclass 6, count 0 2006.285.20:06:43.95#ibcon#enter sib2, iclass 6, count 0 2006.285.20:06:43.95#ibcon#flushed, iclass 6, count 0 2006.285.20:06:43.95#ibcon#about to write, iclass 6, count 0 2006.285.20:06:43.95#ibcon#wrote, iclass 6, count 0 2006.285.20:06:43.95#ibcon#about to read 3, iclass 6, count 0 2006.285.20:06:43.96#ibcon#read 3, iclass 6, count 0 2006.285.20:06:43.96#ibcon#about to read 4, iclass 6, count 0 2006.285.20:06:43.96#ibcon#read 4, iclass 6, count 0 2006.285.20:06:43.96#ibcon#about to read 5, iclass 6, count 0 2006.285.20:06:43.96#ibcon#read 5, iclass 6, count 0 2006.285.20:06:43.97#ibcon#about to read 6, iclass 6, count 0 2006.285.20:06:43.97#ibcon#read 6, iclass 6, count 0 2006.285.20:06:43.97#ibcon#end of sib2, iclass 6, count 0 2006.285.20:06:43.97#ibcon#*mode == 0, iclass 6, count 0 2006.285.20:06:43.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.20:06:43.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.20:06:43.97#ibcon#*before write, iclass 6, count 0 2006.285.20:06:43.97#ibcon#enter sib2, iclass 6, count 0 2006.285.20:06:43.97#ibcon#flushed, iclass 6, count 0 2006.285.20:06:43.97#ibcon#about to write, iclass 6, count 0 2006.285.20:06:43.97#ibcon#wrote, iclass 6, count 0 2006.285.20:06:43.97#ibcon#about to read 3, iclass 6, count 0 2006.285.20:06:44.00#ibcon#read 3, iclass 6, count 0 2006.285.20:06:44.00#ibcon#about to read 4, iclass 6, count 0 2006.285.20:06:44.01#ibcon#read 4, iclass 6, count 0 2006.285.20:06:44.01#ibcon#about to read 5, iclass 6, count 0 2006.285.20:06:44.01#ibcon#read 5, iclass 6, count 0 2006.285.20:06:44.01#ibcon#about to read 6, iclass 6, count 0 2006.285.20:06:44.01#ibcon#read 6, iclass 6, count 0 2006.285.20:06:44.01#ibcon#end of sib2, iclass 6, count 0 2006.285.20:06:44.01#ibcon#*after write, iclass 6, count 0 2006.285.20:06:44.01#ibcon#*before return 0, iclass 6, count 0 2006.285.20:06:44.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:06:44.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:06:44.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.20:06:44.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.20:06:44.01$vck44/vb=5,4 2006.285.20:06:44.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.20:06:44.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.20:06:44.01#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:44.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:06:44.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:06:44.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:06:44.06#ibcon#enter wrdev, iclass 10, count 2 2006.285.20:06:44.06#ibcon#first serial, iclass 10, count 2 2006.285.20:06:44.06#ibcon#enter sib2, iclass 10, count 2 2006.285.20:06:44.07#ibcon#flushed, iclass 10, count 2 2006.285.20:06:44.07#ibcon#about to write, iclass 10, count 2 2006.285.20:06:44.07#ibcon#wrote, iclass 10, count 2 2006.285.20:06:44.07#ibcon#about to read 3, iclass 10, count 2 2006.285.20:06:44.08#ibcon#read 3, iclass 10, count 2 2006.285.20:06:44.08#ibcon#about to read 4, iclass 10, count 2 2006.285.20:06:44.09#ibcon#read 4, iclass 10, count 2 2006.285.20:06:44.09#ibcon#about to read 5, iclass 10, count 2 2006.285.20:06:44.09#ibcon#read 5, iclass 10, count 2 2006.285.20:06:44.09#ibcon#about to read 6, iclass 10, count 2 2006.285.20:06:44.09#ibcon#read 6, iclass 10, count 2 2006.285.20:06:44.09#ibcon#end of sib2, iclass 10, count 2 2006.285.20:06:44.09#ibcon#*mode == 0, iclass 10, count 2 2006.285.20:06:44.09#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.20:06:44.09#ibcon#[27=AT05-04\r\n] 2006.285.20:06:44.09#ibcon#*before write, iclass 10, count 2 2006.285.20:06:44.09#ibcon#enter sib2, iclass 10, count 2 2006.285.20:06:44.09#ibcon#flushed, iclass 10, count 2 2006.285.20:06:44.09#ibcon#about to write, iclass 10, count 2 2006.285.20:06:44.09#ibcon#wrote, iclass 10, count 2 2006.285.20:06:44.09#ibcon#about to read 3, iclass 10, count 2 2006.285.20:06:44.11#ibcon#read 3, iclass 10, count 2 2006.285.20:06:44.11#ibcon#about to read 4, iclass 10, count 2 2006.285.20:06:44.11#ibcon#read 4, iclass 10, count 2 2006.285.20:06:44.11#ibcon#about to read 5, iclass 10, count 2 2006.285.20:06:44.12#ibcon#read 5, iclass 10, count 2 2006.285.20:06:44.12#ibcon#about to read 6, iclass 10, count 2 2006.285.20:06:44.12#ibcon#read 6, iclass 10, count 2 2006.285.20:06:44.12#ibcon#end of sib2, iclass 10, count 2 2006.285.20:06:44.12#ibcon#*after write, iclass 10, count 2 2006.285.20:06:44.12#ibcon#*before return 0, iclass 10, count 2 2006.285.20:06:44.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:06:44.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:06:44.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.20:06:44.12#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:44.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:06:44.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:06:44.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:06:44.23#ibcon#enter wrdev, iclass 10, count 0 2006.285.20:06:44.23#ibcon#first serial, iclass 10, count 0 2006.285.20:06:44.23#ibcon#enter sib2, iclass 10, count 0 2006.285.20:06:44.24#ibcon#flushed, iclass 10, count 0 2006.285.20:06:44.24#ibcon#about to write, iclass 10, count 0 2006.285.20:06:44.24#ibcon#wrote, iclass 10, count 0 2006.285.20:06:44.24#ibcon#about to read 3, iclass 10, count 0 2006.285.20:06:44.25#ibcon#read 3, iclass 10, count 0 2006.285.20:06:44.25#ibcon#about to read 4, iclass 10, count 0 2006.285.20:06:44.25#ibcon#read 4, iclass 10, count 0 2006.285.20:06:44.25#ibcon#about to read 5, iclass 10, count 0 2006.285.20:06:44.25#ibcon#read 5, iclass 10, count 0 2006.285.20:06:44.26#ibcon#about to read 6, iclass 10, count 0 2006.285.20:06:44.26#ibcon#read 6, iclass 10, count 0 2006.285.20:06:44.26#ibcon#end of sib2, iclass 10, count 0 2006.285.20:06:44.26#ibcon#*mode == 0, iclass 10, count 0 2006.285.20:06:44.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.20:06:44.26#ibcon#[27=USB\r\n] 2006.285.20:06:44.26#ibcon#*before write, iclass 10, count 0 2006.285.20:06:44.26#ibcon#enter sib2, iclass 10, count 0 2006.285.20:06:44.26#ibcon#flushed, iclass 10, count 0 2006.285.20:06:44.26#ibcon#about to write, iclass 10, count 0 2006.285.20:06:44.26#ibcon#wrote, iclass 10, count 0 2006.285.20:06:44.26#ibcon#about to read 3, iclass 10, count 0 2006.285.20:06:44.28#ibcon#read 3, iclass 10, count 0 2006.285.20:06:44.28#ibcon#about to read 4, iclass 10, count 0 2006.285.20:06:44.28#ibcon#read 4, iclass 10, count 0 2006.285.20:06:44.28#ibcon#about to read 5, iclass 10, count 0 2006.285.20:06:44.29#ibcon#read 5, iclass 10, count 0 2006.285.20:06:44.29#ibcon#about to read 6, iclass 10, count 0 2006.285.20:06:44.29#ibcon#read 6, iclass 10, count 0 2006.285.20:06:44.29#ibcon#end of sib2, iclass 10, count 0 2006.285.20:06:44.29#ibcon#*after write, iclass 10, count 0 2006.285.20:06:44.29#ibcon#*before return 0, iclass 10, count 0 2006.285.20:06:44.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:06:44.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:06:44.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.20:06:44.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.20:06:44.29$vck44/vblo=6,719.99 2006.285.20:06:44.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.20:06:44.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.20:06:44.29#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:44.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:06:44.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:06:44.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:06:44.29#ibcon#enter wrdev, iclass 12, count 0 2006.285.20:06:44.29#ibcon#first serial, iclass 12, count 0 2006.285.20:06:44.29#ibcon#enter sib2, iclass 12, count 0 2006.285.20:06:44.29#ibcon#flushed, iclass 12, count 0 2006.285.20:06:44.29#ibcon#about to write, iclass 12, count 0 2006.285.20:06:44.29#ibcon#wrote, iclass 12, count 0 2006.285.20:06:44.29#ibcon#about to read 3, iclass 12, count 0 2006.285.20:06:44.30#ibcon#read 3, iclass 12, count 0 2006.285.20:06:44.30#ibcon#about to read 4, iclass 12, count 0 2006.285.20:06:44.30#ibcon#read 4, iclass 12, count 0 2006.285.20:06:44.30#ibcon#about to read 5, iclass 12, count 0 2006.285.20:06:44.30#ibcon#read 5, iclass 12, count 0 2006.285.20:06:44.31#ibcon#about to read 6, iclass 12, count 0 2006.285.20:06:44.31#ibcon#read 6, iclass 12, count 0 2006.285.20:06:44.31#ibcon#end of sib2, iclass 12, count 0 2006.285.20:06:44.31#ibcon#*mode == 0, iclass 12, count 0 2006.285.20:06:44.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.20:06:44.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.20:06:44.31#ibcon#*before write, iclass 12, count 0 2006.285.20:06:44.31#ibcon#enter sib2, iclass 12, count 0 2006.285.20:06:44.31#ibcon#flushed, iclass 12, count 0 2006.285.20:06:44.31#ibcon#about to write, iclass 12, count 0 2006.285.20:06:44.31#ibcon#wrote, iclass 12, count 0 2006.285.20:06:44.31#ibcon#about to read 3, iclass 12, count 0 2006.285.20:06:44.34#ibcon#read 3, iclass 12, count 0 2006.285.20:06:44.34#ibcon#about to read 4, iclass 12, count 0 2006.285.20:06:44.34#ibcon#read 4, iclass 12, count 0 2006.285.20:06:44.35#ibcon#about to read 5, iclass 12, count 0 2006.285.20:06:44.35#ibcon#read 5, iclass 12, count 0 2006.285.20:06:44.35#ibcon#about to read 6, iclass 12, count 0 2006.285.20:06:44.35#ibcon#read 6, iclass 12, count 0 2006.285.20:06:44.35#ibcon#end of sib2, iclass 12, count 0 2006.285.20:06:44.35#ibcon#*after write, iclass 12, count 0 2006.285.20:06:44.35#ibcon#*before return 0, iclass 12, count 0 2006.285.20:06:44.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:06:44.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:06:44.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.20:06:44.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.20:06:44.35$vck44/vb=6,3 2006.285.20:06:44.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.20:06:44.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.20:06:44.35#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:44.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:06:44.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:06:44.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:06:44.40#ibcon#enter wrdev, iclass 14, count 2 2006.285.20:06:44.40#ibcon#first serial, iclass 14, count 2 2006.285.20:06:44.40#ibcon#enter sib2, iclass 14, count 2 2006.285.20:06:44.41#ibcon#flushed, iclass 14, count 2 2006.285.20:06:44.41#ibcon#about to write, iclass 14, count 2 2006.285.20:06:44.41#ibcon#wrote, iclass 14, count 2 2006.285.20:06:44.41#ibcon#about to read 3, iclass 14, count 2 2006.285.20:06:44.42#ibcon#read 3, iclass 14, count 2 2006.285.20:06:44.42#ibcon#about to read 4, iclass 14, count 2 2006.285.20:06:44.42#ibcon#read 4, iclass 14, count 2 2006.285.20:06:44.42#ibcon#about to read 5, iclass 14, count 2 2006.285.20:06:44.43#ibcon#read 5, iclass 14, count 2 2006.285.20:06:44.43#ibcon#about to read 6, iclass 14, count 2 2006.285.20:06:44.43#ibcon#read 6, iclass 14, count 2 2006.285.20:06:44.43#ibcon#end of sib2, iclass 14, count 2 2006.285.20:06:44.43#ibcon#*mode == 0, iclass 14, count 2 2006.285.20:06:44.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.20:06:44.43#ibcon#[27=AT06-03\r\n] 2006.285.20:06:44.43#ibcon#*before write, iclass 14, count 2 2006.285.20:06:44.43#ibcon#enter sib2, iclass 14, count 2 2006.285.20:06:44.43#ibcon#flushed, iclass 14, count 2 2006.285.20:06:44.43#ibcon#about to write, iclass 14, count 2 2006.285.20:06:44.43#ibcon#wrote, iclass 14, count 2 2006.285.20:06:44.43#ibcon#about to read 3, iclass 14, count 2 2006.285.20:06:44.45#ibcon#read 3, iclass 14, count 2 2006.285.20:06:44.45#ibcon#about to read 4, iclass 14, count 2 2006.285.20:06:44.45#ibcon#read 4, iclass 14, count 2 2006.285.20:06:44.45#ibcon#about to read 5, iclass 14, count 2 2006.285.20:06:44.46#ibcon#read 5, iclass 14, count 2 2006.285.20:06:44.46#ibcon#about to read 6, iclass 14, count 2 2006.285.20:06:44.46#ibcon#read 6, iclass 14, count 2 2006.285.20:06:44.46#ibcon#end of sib2, iclass 14, count 2 2006.285.20:06:44.46#ibcon#*after write, iclass 14, count 2 2006.285.20:06:44.46#ibcon#*before return 0, iclass 14, count 2 2006.285.20:06:44.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:06:44.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:06:44.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.20:06:44.46#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:44.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:06:44.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:06:44.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:06:44.57#ibcon#enter wrdev, iclass 14, count 0 2006.285.20:06:44.57#ibcon#first serial, iclass 14, count 0 2006.285.20:06:44.57#ibcon#enter sib2, iclass 14, count 0 2006.285.20:06:44.57#ibcon#flushed, iclass 14, count 0 2006.285.20:06:44.58#ibcon#about to write, iclass 14, count 0 2006.285.20:06:44.58#ibcon#wrote, iclass 14, count 0 2006.285.20:06:44.58#ibcon#about to read 3, iclass 14, count 0 2006.285.20:06:44.59#ibcon#read 3, iclass 14, count 0 2006.285.20:06:44.59#ibcon#about to read 4, iclass 14, count 0 2006.285.20:06:44.59#ibcon#read 4, iclass 14, count 0 2006.285.20:06:44.59#ibcon#about to read 5, iclass 14, count 0 2006.285.20:06:44.59#ibcon#read 5, iclass 14, count 0 2006.285.20:06:44.59#ibcon#about to read 6, iclass 14, count 0 2006.285.20:06:44.60#ibcon#read 6, iclass 14, count 0 2006.285.20:06:44.60#ibcon#end of sib2, iclass 14, count 0 2006.285.20:06:44.60#ibcon#*mode == 0, iclass 14, count 0 2006.285.20:06:44.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.20:06:44.60#ibcon#[27=USB\r\n] 2006.285.20:06:44.60#ibcon#*before write, iclass 14, count 0 2006.285.20:06:44.60#ibcon#enter sib2, iclass 14, count 0 2006.285.20:06:44.60#ibcon#flushed, iclass 14, count 0 2006.285.20:06:44.60#ibcon#about to write, iclass 14, count 0 2006.285.20:06:44.60#ibcon#wrote, iclass 14, count 0 2006.285.20:06:44.60#ibcon#about to read 3, iclass 14, count 0 2006.285.20:06:44.62#ibcon#read 3, iclass 14, count 0 2006.285.20:06:44.62#ibcon#about to read 4, iclass 14, count 0 2006.285.20:06:44.62#ibcon#read 4, iclass 14, count 0 2006.285.20:06:44.62#ibcon#about to read 5, iclass 14, count 0 2006.285.20:06:44.62#ibcon#read 5, iclass 14, count 0 2006.285.20:06:44.62#ibcon#about to read 6, iclass 14, count 0 2006.285.20:06:44.63#ibcon#read 6, iclass 14, count 0 2006.285.20:06:44.63#ibcon#end of sib2, iclass 14, count 0 2006.285.20:06:44.63#ibcon#*after write, iclass 14, count 0 2006.285.20:06:44.63#ibcon#*before return 0, iclass 14, count 0 2006.285.20:06:44.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:06:44.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:06:44.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.20:06:44.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.20:06:44.63$vck44/vblo=7,734.99 2006.285.20:06:44.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.20:06:44.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.20:06:44.63#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:44.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:06:44.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:06:44.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:06:44.63#ibcon#enter wrdev, iclass 16, count 0 2006.285.20:06:44.63#ibcon#first serial, iclass 16, count 0 2006.285.20:06:44.63#ibcon#enter sib2, iclass 16, count 0 2006.285.20:06:44.63#ibcon#flushed, iclass 16, count 0 2006.285.20:06:44.63#ibcon#about to write, iclass 16, count 0 2006.285.20:06:44.63#ibcon#wrote, iclass 16, count 0 2006.285.20:06:44.63#ibcon#about to read 3, iclass 16, count 0 2006.285.20:06:44.64#ibcon#read 3, iclass 16, count 0 2006.285.20:06:44.64#ibcon#about to read 4, iclass 16, count 0 2006.285.20:06:44.64#ibcon#read 4, iclass 16, count 0 2006.285.20:06:44.64#ibcon#about to read 5, iclass 16, count 0 2006.285.20:06:44.64#ibcon#read 5, iclass 16, count 0 2006.285.20:06:44.65#ibcon#about to read 6, iclass 16, count 0 2006.285.20:06:44.65#ibcon#read 6, iclass 16, count 0 2006.285.20:06:44.65#ibcon#end of sib2, iclass 16, count 0 2006.285.20:06:44.65#ibcon#*mode == 0, iclass 16, count 0 2006.285.20:06:44.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.20:06:44.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.20:06:44.65#ibcon#*before write, iclass 16, count 0 2006.285.20:06:44.65#ibcon#enter sib2, iclass 16, count 0 2006.285.20:06:44.65#ibcon#flushed, iclass 16, count 0 2006.285.20:06:44.65#ibcon#about to write, iclass 16, count 0 2006.285.20:06:44.65#ibcon#wrote, iclass 16, count 0 2006.285.20:06:44.65#ibcon#about to read 3, iclass 16, count 0 2006.285.20:06:44.68#ibcon#read 3, iclass 16, count 0 2006.285.20:06:44.68#ibcon#about to read 4, iclass 16, count 0 2006.285.20:06:44.68#ibcon#read 4, iclass 16, count 0 2006.285.20:06:44.68#ibcon#about to read 5, iclass 16, count 0 2006.285.20:06:44.68#ibcon#read 5, iclass 16, count 0 2006.285.20:06:44.68#ibcon#about to read 6, iclass 16, count 0 2006.285.20:06:44.69#ibcon#read 6, iclass 16, count 0 2006.285.20:06:44.69#ibcon#end of sib2, iclass 16, count 0 2006.285.20:06:44.69#ibcon#*after write, iclass 16, count 0 2006.285.20:06:44.69#ibcon#*before return 0, iclass 16, count 0 2006.285.20:06:44.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:06:44.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:06:44.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.20:06:44.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.20:06:44.69$vck44/vb=7,4 2006.285.20:06:44.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.20:06:44.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.20:06:44.69#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:44.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:06:44.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:06:44.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:06:44.74#ibcon#enter wrdev, iclass 18, count 2 2006.285.20:06:44.74#ibcon#first serial, iclass 18, count 2 2006.285.20:06:44.74#ibcon#enter sib2, iclass 18, count 2 2006.285.20:06:44.74#ibcon#flushed, iclass 18, count 2 2006.285.20:06:44.75#ibcon#about to write, iclass 18, count 2 2006.285.20:06:44.75#ibcon#wrote, iclass 18, count 2 2006.285.20:06:44.75#ibcon#about to read 3, iclass 18, count 2 2006.285.20:06:44.76#ibcon#read 3, iclass 18, count 2 2006.285.20:06:44.76#ibcon#about to read 4, iclass 18, count 2 2006.285.20:06:44.76#ibcon#read 4, iclass 18, count 2 2006.285.20:06:44.76#ibcon#about to read 5, iclass 18, count 2 2006.285.20:06:44.76#ibcon#read 5, iclass 18, count 2 2006.285.20:06:44.77#ibcon#about to read 6, iclass 18, count 2 2006.285.20:06:44.77#ibcon#read 6, iclass 18, count 2 2006.285.20:06:44.77#ibcon#end of sib2, iclass 18, count 2 2006.285.20:06:44.77#ibcon#*mode == 0, iclass 18, count 2 2006.285.20:06:44.77#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.20:06:44.77#ibcon#[27=AT07-04\r\n] 2006.285.20:06:44.77#ibcon#*before write, iclass 18, count 2 2006.285.20:06:44.77#ibcon#enter sib2, iclass 18, count 2 2006.285.20:06:44.77#ibcon#flushed, iclass 18, count 2 2006.285.20:06:44.77#ibcon#about to write, iclass 18, count 2 2006.285.20:06:44.77#ibcon#wrote, iclass 18, count 2 2006.285.20:06:44.77#ibcon#about to read 3, iclass 18, count 2 2006.285.20:06:44.79#ibcon#read 3, iclass 18, count 2 2006.285.20:06:44.79#ibcon#about to read 4, iclass 18, count 2 2006.285.20:06:44.79#ibcon#read 4, iclass 18, count 2 2006.285.20:06:44.79#ibcon#about to read 5, iclass 18, count 2 2006.285.20:06:44.79#ibcon#read 5, iclass 18, count 2 2006.285.20:06:44.79#ibcon#about to read 6, iclass 18, count 2 2006.285.20:06:44.80#ibcon#read 6, iclass 18, count 2 2006.285.20:06:44.80#ibcon#end of sib2, iclass 18, count 2 2006.285.20:06:44.80#ibcon#*after write, iclass 18, count 2 2006.285.20:06:44.80#ibcon#*before return 0, iclass 18, count 2 2006.285.20:06:44.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:06:44.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:06:44.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.20:06:44.80#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:44.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:06:44.91#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:06:44.91#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:06:44.91#ibcon#enter wrdev, iclass 18, count 0 2006.285.20:06:44.91#ibcon#first serial, iclass 18, count 0 2006.285.20:06:44.91#ibcon#enter sib2, iclass 18, count 0 2006.285.20:06:44.91#ibcon#flushed, iclass 18, count 0 2006.285.20:06:44.91#ibcon#about to write, iclass 18, count 0 2006.285.20:06:44.92#ibcon#wrote, iclass 18, count 0 2006.285.20:06:44.92#ibcon#about to read 3, iclass 18, count 0 2006.285.20:06:44.93#ibcon#read 3, iclass 18, count 0 2006.285.20:06:44.93#ibcon#about to read 4, iclass 18, count 0 2006.285.20:06:44.93#ibcon#read 4, iclass 18, count 0 2006.285.20:06:44.93#ibcon#about to read 5, iclass 18, count 0 2006.285.20:06:44.93#ibcon#read 5, iclass 18, count 0 2006.285.20:06:44.93#ibcon#about to read 6, iclass 18, count 0 2006.285.20:06:44.94#ibcon#read 6, iclass 18, count 0 2006.285.20:06:44.94#ibcon#end of sib2, iclass 18, count 0 2006.285.20:06:44.94#ibcon#*mode == 0, iclass 18, count 0 2006.285.20:06:44.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.20:06:44.94#ibcon#[27=USB\r\n] 2006.285.20:06:44.94#ibcon#*before write, iclass 18, count 0 2006.285.20:06:44.94#ibcon#enter sib2, iclass 18, count 0 2006.285.20:06:44.94#ibcon#flushed, iclass 18, count 0 2006.285.20:06:44.94#ibcon#about to write, iclass 18, count 0 2006.285.20:06:44.94#ibcon#wrote, iclass 18, count 0 2006.285.20:06:44.94#ibcon#about to read 3, iclass 18, count 0 2006.285.20:06:44.96#ibcon#read 3, iclass 18, count 0 2006.285.20:06:44.96#ibcon#about to read 4, iclass 18, count 0 2006.285.20:06:44.96#ibcon#read 4, iclass 18, count 0 2006.285.20:06:44.96#ibcon#about to read 5, iclass 18, count 0 2006.285.20:06:44.96#ibcon#read 5, iclass 18, count 0 2006.285.20:06:44.96#ibcon#about to read 6, iclass 18, count 0 2006.285.20:06:44.97#ibcon#read 6, iclass 18, count 0 2006.285.20:06:44.97#ibcon#end of sib2, iclass 18, count 0 2006.285.20:06:44.97#ibcon#*after write, iclass 18, count 0 2006.285.20:06:44.97#ibcon#*before return 0, iclass 18, count 0 2006.285.20:06:44.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:06:44.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:06:44.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.20:06:44.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.20:06:44.97$vck44/vblo=8,744.99 2006.285.20:06:44.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.20:06:44.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.20:06:44.97#ibcon#ireg 17 cls_cnt 0 2006.285.20:06:44.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:06:44.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:06:44.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:06:44.97#ibcon#enter wrdev, iclass 20, count 0 2006.285.20:06:44.97#ibcon#first serial, iclass 20, count 0 2006.285.20:06:44.97#ibcon#enter sib2, iclass 20, count 0 2006.285.20:06:44.97#ibcon#flushed, iclass 20, count 0 2006.285.20:06:44.97#ibcon#about to write, iclass 20, count 0 2006.285.20:06:44.97#ibcon#wrote, iclass 20, count 0 2006.285.20:06:44.97#ibcon#about to read 3, iclass 20, count 0 2006.285.20:06:44.98#ibcon#read 3, iclass 20, count 0 2006.285.20:06:44.98#ibcon#about to read 4, iclass 20, count 0 2006.285.20:06:44.98#ibcon#read 4, iclass 20, count 0 2006.285.20:06:44.98#ibcon#about to read 5, iclass 20, count 0 2006.285.20:06:44.98#ibcon#read 5, iclass 20, count 0 2006.285.20:06:44.99#ibcon#about to read 6, iclass 20, count 0 2006.285.20:06:44.99#ibcon#read 6, iclass 20, count 0 2006.285.20:06:44.99#ibcon#end of sib2, iclass 20, count 0 2006.285.20:06:44.99#ibcon#*mode == 0, iclass 20, count 0 2006.285.20:06:44.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.20:06:44.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.20:06:44.99#ibcon#*before write, iclass 20, count 0 2006.285.20:06:44.99#ibcon#enter sib2, iclass 20, count 0 2006.285.20:06:44.99#ibcon#flushed, iclass 20, count 0 2006.285.20:06:44.99#ibcon#about to write, iclass 20, count 0 2006.285.20:06:44.99#ibcon#wrote, iclass 20, count 0 2006.285.20:06:44.99#ibcon#about to read 3, iclass 20, count 0 2006.285.20:06:45.02#ibcon#read 3, iclass 20, count 0 2006.285.20:06:45.02#ibcon#about to read 4, iclass 20, count 0 2006.285.20:06:45.02#ibcon#read 4, iclass 20, count 0 2006.285.20:06:45.03#ibcon#about to read 5, iclass 20, count 0 2006.285.20:06:45.03#ibcon#read 5, iclass 20, count 0 2006.285.20:06:45.03#ibcon#about to read 6, iclass 20, count 0 2006.285.20:06:45.03#ibcon#read 6, iclass 20, count 0 2006.285.20:06:45.03#ibcon#end of sib2, iclass 20, count 0 2006.285.20:06:45.03#ibcon#*after write, iclass 20, count 0 2006.285.20:06:45.03#ibcon#*before return 0, iclass 20, count 0 2006.285.20:06:45.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:06:45.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:06:45.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.20:06:45.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.20:06:45.03$vck44/vb=8,4 2006.285.20:06:45.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.20:06:45.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.20:06:45.03#ibcon#ireg 11 cls_cnt 2 2006.285.20:06:45.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:06:45.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:06:45.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:06:45.08#ibcon#enter wrdev, iclass 22, count 2 2006.285.20:06:45.08#ibcon#first serial, iclass 22, count 2 2006.285.20:06:45.09#ibcon#enter sib2, iclass 22, count 2 2006.285.20:06:45.09#ibcon#flushed, iclass 22, count 2 2006.285.20:06:45.09#ibcon#about to write, iclass 22, count 2 2006.285.20:06:45.09#ibcon#wrote, iclass 22, count 2 2006.285.20:06:45.09#ibcon#about to read 3, iclass 22, count 2 2006.285.20:06:45.10#ibcon#read 3, iclass 22, count 2 2006.285.20:06:45.10#ibcon#about to read 4, iclass 22, count 2 2006.285.20:06:45.10#ibcon#read 4, iclass 22, count 2 2006.285.20:06:45.10#ibcon#about to read 5, iclass 22, count 2 2006.285.20:06:45.11#ibcon#read 5, iclass 22, count 2 2006.285.20:06:45.11#ibcon#about to read 6, iclass 22, count 2 2006.285.20:06:45.11#ibcon#read 6, iclass 22, count 2 2006.285.20:06:45.11#ibcon#end of sib2, iclass 22, count 2 2006.285.20:06:45.11#ibcon#*mode == 0, iclass 22, count 2 2006.285.20:06:45.11#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.20:06:45.11#ibcon#[27=AT08-04\r\n] 2006.285.20:06:45.11#ibcon#*before write, iclass 22, count 2 2006.285.20:06:45.11#ibcon#enter sib2, iclass 22, count 2 2006.285.20:06:45.11#ibcon#flushed, iclass 22, count 2 2006.285.20:06:45.11#ibcon#about to write, iclass 22, count 2 2006.285.20:06:45.11#ibcon#wrote, iclass 22, count 2 2006.285.20:06:45.11#ibcon#about to read 3, iclass 22, count 2 2006.285.20:06:45.14#ibcon#read 3, iclass 22, count 2 2006.285.20:06:45.14#ibcon#about to read 4, iclass 22, count 2 2006.285.20:06:45.14#ibcon#read 4, iclass 22, count 2 2006.285.20:06:45.14#ibcon#about to read 5, iclass 22, count 2 2006.285.20:06:45.14#ibcon#read 5, iclass 22, count 2 2006.285.20:06:45.14#ibcon#about to read 6, iclass 22, count 2 2006.285.20:06:45.14#ibcon#read 6, iclass 22, count 2 2006.285.20:06:45.14#ibcon#end of sib2, iclass 22, count 2 2006.285.20:06:45.14#ibcon#*after write, iclass 22, count 2 2006.285.20:06:45.14#ibcon#*before return 0, iclass 22, count 2 2006.285.20:06:45.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:06:45.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:06:45.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.20:06:45.14#ibcon#ireg 7 cls_cnt 0 2006.285.20:06:45.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:06:45.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:06:45.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:06:45.25#ibcon#enter wrdev, iclass 22, count 0 2006.285.20:06:45.25#ibcon#first serial, iclass 22, count 0 2006.285.20:06:45.25#ibcon#enter sib2, iclass 22, count 0 2006.285.20:06:45.26#ibcon#flushed, iclass 22, count 0 2006.285.20:06:45.26#ibcon#about to write, iclass 22, count 0 2006.285.20:06:45.26#ibcon#wrote, iclass 22, count 0 2006.285.20:06:45.26#ibcon#about to read 3, iclass 22, count 0 2006.285.20:06:45.27#ibcon#read 3, iclass 22, count 0 2006.285.20:06:45.27#ibcon#about to read 4, iclass 22, count 0 2006.285.20:06:45.27#ibcon#read 4, iclass 22, count 0 2006.285.20:06:45.27#ibcon#about to read 5, iclass 22, count 0 2006.285.20:06:45.27#ibcon#read 5, iclass 22, count 0 2006.285.20:06:45.28#ibcon#about to read 6, iclass 22, count 0 2006.285.20:06:45.28#ibcon#read 6, iclass 22, count 0 2006.285.20:06:45.28#ibcon#end of sib2, iclass 22, count 0 2006.285.20:06:45.28#ibcon#*mode == 0, iclass 22, count 0 2006.285.20:06:45.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.20:06:45.28#ibcon#[27=USB\r\n] 2006.285.20:06:45.28#ibcon#*before write, iclass 22, count 0 2006.285.20:06:45.28#ibcon#enter sib2, iclass 22, count 0 2006.285.20:06:45.28#ibcon#flushed, iclass 22, count 0 2006.285.20:06:45.28#ibcon#about to write, iclass 22, count 0 2006.285.20:06:45.28#ibcon#wrote, iclass 22, count 0 2006.285.20:06:45.28#ibcon#about to read 3, iclass 22, count 0 2006.285.20:06:45.30#ibcon#read 3, iclass 22, count 0 2006.285.20:06:45.30#ibcon#about to read 4, iclass 22, count 0 2006.285.20:06:45.30#ibcon#read 4, iclass 22, count 0 2006.285.20:06:45.30#ibcon#about to read 5, iclass 22, count 0 2006.285.20:06:45.31#ibcon#read 5, iclass 22, count 0 2006.285.20:06:45.31#ibcon#about to read 6, iclass 22, count 0 2006.285.20:06:45.31#ibcon#read 6, iclass 22, count 0 2006.285.20:06:45.31#ibcon#end of sib2, iclass 22, count 0 2006.285.20:06:45.31#ibcon#*after write, iclass 22, count 0 2006.285.20:06:45.31#ibcon#*before return 0, iclass 22, count 0 2006.285.20:06:45.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:06:45.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:06:45.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.20:06:45.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.20:06:45.31$vck44/vabw=wide 2006.285.20:06:45.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.20:06:45.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.20:06:45.31#ibcon#ireg 8 cls_cnt 0 2006.285.20:06:45.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:06:45.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:06:45.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:06:45.31#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:06:45.31#ibcon#first serial, iclass 25, count 0 2006.285.20:06:45.31#ibcon#enter sib2, iclass 25, count 0 2006.285.20:06:45.31#ibcon#flushed, iclass 25, count 0 2006.285.20:06:45.31#ibcon#about to write, iclass 25, count 0 2006.285.20:06:45.31#ibcon#wrote, iclass 25, count 0 2006.285.20:06:45.31#ibcon#about to read 3, iclass 25, count 0 2006.285.20:06:45.32#ibcon#read 3, iclass 25, count 0 2006.285.20:06:45.32#ibcon#about to read 4, iclass 25, count 0 2006.285.20:06:45.32#ibcon#read 4, iclass 25, count 0 2006.285.20:06:45.33#ibcon#about to read 5, iclass 25, count 0 2006.285.20:06:45.33#ibcon#read 5, iclass 25, count 0 2006.285.20:06:45.33#ibcon#about to read 6, iclass 25, count 0 2006.285.20:06:45.33#ibcon#read 6, iclass 25, count 0 2006.285.20:06:45.33#ibcon#end of sib2, iclass 25, count 0 2006.285.20:06:45.33#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:06:45.33#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:06:45.33#ibcon#[25=BW32\r\n] 2006.285.20:06:45.33#ibcon#*before write, iclass 25, count 0 2006.285.20:06:45.33#ibcon#enter sib2, iclass 25, count 0 2006.285.20:06:45.33#ibcon#flushed, iclass 25, count 0 2006.285.20:06:45.33#ibcon#about to write, iclass 25, count 0 2006.285.20:06:45.33#ibcon#wrote, iclass 25, count 0 2006.285.20:06:45.33#ibcon#about to read 3, iclass 25, count 0 2006.285.20:06:45.35#ibcon#read 3, iclass 25, count 0 2006.285.20:06:45.35#ibcon#about to read 4, iclass 25, count 0 2006.285.20:06:45.35#ibcon#read 4, iclass 25, count 0 2006.285.20:06:45.35#ibcon#about to read 5, iclass 25, count 0 2006.285.20:06:45.36#ibcon#read 5, iclass 25, count 0 2006.285.20:06:45.36#ibcon#about to read 6, iclass 25, count 0 2006.285.20:06:45.36#ibcon#read 6, iclass 25, count 0 2006.285.20:06:45.36#ibcon#end of sib2, iclass 25, count 0 2006.285.20:06:45.36#ibcon#*after write, iclass 25, count 0 2006.285.20:06:45.36#ibcon#*before return 0, iclass 25, count 0 2006.285.20:06:45.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:06:45.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:06:45.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:06:45.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:06:45.36$vck44/vbbw=wide 2006.285.20:06:45.36#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.20:06:45.36#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.20:06:45.36#ibcon#ireg 8 cls_cnt 0 2006.285.20:06:45.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:06:45.38#abcon#<5=/13 0.3 1.2 14.551001015.2\r\n> 2006.285.20:06:45.40#abcon#{5=INTERFACE CLEAR} 2006.285.20:06:45.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:06:45.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:06:45.42#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:06:45.42#ibcon#first serial, iclass 27, count 0 2006.285.20:06:45.42#ibcon#enter sib2, iclass 27, count 0 2006.285.20:06:45.43#ibcon#flushed, iclass 27, count 0 2006.285.20:06:45.43#ibcon#about to write, iclass 27, count 0 2006.285.20:06:45.43#ibcon#wrote, iclass 27, count 0 2006.285.20:06:45.43#ibcon#about to read 3, iclass 27, count 0 2006.285.20:06:45.44#ibcon#read 3, iclass 27, count 0 2006.285.20:06:45.44#ibcon#about to read 4, iclass 27, count 0 2006.285.20:06:45.44#ibcon#read 4, iclass 27, count 0 2006.285.20:06:45.44#ibcon#about to read 5, iclass 27, count 0 2006.285.20:06:45.44#ibcon#read 5, iclass 27, count 0 2006.285.20:06:45.44#ibcon#about to read 6, iclass 27, count 0 2006.285.20:06:45.45#ibcon#read 6, iclass 27, count 0 2006.285.20:06:45.45#ibcon#end of sib2, iclass 27, count 0 2006.285.20:06:45.45#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:06:45.45#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:06:45.45#ibcon#[27=BW32\r\n] 2006.285.20:06:45.45#ibcon#*before write, iclass 27, count 0 2006.285.20:06:45.45#ibcon#enter sib2, iclass 27, count 0 2006.285.20:06:45.45#ibcon#flushed, iclass 27, count 0 2006.285.20:06:45.45#ibcon#about to write, iclass 27, count 0 2006.285.20:06:45.45#ibcon#wrote, iclass 27, count 0 2006.285.20:06:45.45#ibcon#about to read 3, iclass 27, count 0 2006.285.20:06:45.46#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:06:45.47#ibcon#read 3, iclass 27, count 0 2006.285.20:06:45.47#ibcon#about to read 4, iclass 27, count 0 2006.285.20:06:45.47#ibcon#read 4, iclass 27, count 0 2006.285.20:06:45.47#ibcon#about to read 5, iclass 27, count 0 2006.285.20:06:45.47#ibcon#read 5, iclass 27, count 0 2006.285.20:06:45.47#ibcon#about to read 6, iclass 27, count 0 2006.285.20:06:45.48#ibcon#read 6, iclass 27, count 0 2006.285.20:06:45.48#ibcon#end of sib2, iclass 27, count 0 2006.285.20:06:45.48#ibcon#*after write, iclass 27, count 0 2006.285.20:06:45.48#ibcon#*before return 0, iclass 27, count 0 2006.285.20:06:45.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:06:45.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:06:45.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:06:45.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:06:45.48$setupk4/ifdk4 2006.285.20:06:45.48$ifdk4/lo= 2006.285.20:06:45.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.20:06:45.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.20:06:45.48$ifdk4/patch= 2006.285.20:06:45.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.20:06:45.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.20:06:45.48$setupk4/!*+20s 2006.285.20:06:55.55#abcon#<5=/13 0.3 1.2 14.551001015.2\r\n> 2006.285.20:06:55.57#abcon#{5=INTERFACE CLEAR} 2006.285.20:06:55.63#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:06:59.54$setupk4/"tpicd 2006.285.20:06:59.55$setupk4/echo=off 2006.285.20:06:59.55$setupk4/xlog=off 2006.285.20:06:59.55:!2006.285.20:10:45 2006.285.20:07:55.14#trakl#Source acquired 2006.285.20:07:55.15#flagr#flagr/antenna,acquired 2006.285.20:10:45.01:preob 2006.285.20:10:46.14/onsource/TRACKING 2006.285.20:10:46.14:!2006.285.20:10:55 2006.285.20:10:55.00:"tape 2006.285.20:10:55.00:"st=record 2006.285.20:10:55.00:data_valid=on 2006.285.20:10:55.00:midob 2006.285.20:10:55.14/onsource/TRACKING 2006.285.20:10:55.15/wx/14.55,1015.2,100 2006.285.20:10:55.26/cable/+6.5074E-03 2006.285.20:10:56.35/va/01,07,usb,yes,39,42 2006.285.20:10:56.35/va/02,06,usb,yes,39,40 2006.285.20:10:56.35/va/03,07,usb,yes,39,41 2006.285.20:10:56.35/va/04,06,usb,yes,41,42 2006.285.20:10:56.35/va/05,03,usb,yes,40,40 2006.285.20:10:56.35/va/06,04,usb,yes,36,35 2006.285.20:10:56.35/va/07,04,usb,yes,37,37 2006.285.20:10:56.35/va/08,03,usb,yes,38,45 2006.285.20:10:56.58/valo/01,524.99,yes,locked 2006.285.20:10:56.58/valo/02,534.99,yes,locked 2006.285.20:10:56.58/valo/03,564.99,yes,locked 2006.285.20:10:56.58/valo/04,624.99,yes,locked 2006.285.20:10:56.58/valo/05,734.99,yes,locked 2006.285.20:10:56.58/valo/06,814.99,yes,locked 2006.285.20:10:56.58/valo/07,864.99,yes,locked 2006.285.20:10:56.58/valo/08,884.99,yes,locked 2006.285.20:10:57.67/vb/01,04,usb,yes,38,66 2006.285.20:10:57.67/vb/02,05,usb,yes,36,62 2006.285.20:10:57.67/vb/03,04,usb,yes,37,46 2006.285.20:10:57.67/vb/04,05,usb,yes,37,36 2006.285.20:10:57.67/vb/05,04,usb,yes,34,37 2006.285.20:10:57.67/vb/06,03,usb,yes,48,43 2006.285.20:10:57.67/vb/07,04,usb,yes,38,38 2006.285.20:10:57.67/vb/08,04,usb,yes,34,39 2006.285.20:10:57.90/vblo/01,629.99,yes,locked 2006.285.20:10:57.90/vblo/02,634.99,yes,locked 2006.285.20:10:57.90/vblo/03,649.99,yes,locked 2006.285.20:10:57.90/vblo/04,679.99,yes,locked 2006.285.20:10:57.90/vblo/05,709.99,yes,locked 2006.285.20:10:57.90/vblo/06,719.99,yes,locked 2006.285.20:10:57.90/vblo/07,734.99,yes,locked 2006.285.20:10:57.90/vblo/08,744.99,yes,locked 2006.285.20:10:58.05/vabw/8 2006.285.20:10:58.20/vbbw/8 2006.285.20:10:58.29/xfe/off,on,12.0 2006.285.20:10:58.67/ifatt/23,28,28,28 2006.285.20:10:59.07/fmout-gps/S +2.73E-07 2006.285.20:10:59.09:!2006.285.20:12:55 2006.285.20:12:55.01:data_valid=off 2006.285.20:12:55.01:"et 2006.285.20:12:55.02:!+3s 2006.285.20:12:58.04:"tape 2006.285.20:12:58.04:postob 2006.285.20:12:58.15/cable/+6.5084E-03 2006.285.20:12:58.15/wx/14.53,1015.2,100 2006.285.20:12:58.21/fmout-gps/S +2.72E-07 2006.285.20:12:58.21:scan_name=285-2014,jd0610,40 2006.285.20:12:58.21:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.285.20:13:00.14#flagr#flagr/antenna,new-source 2006.285.20:13:00.14:checkk5 2006.285.20:13:00.60/chk_autoobs//k5ts1/ autoobs is running! 2006.285.20:13:01.11/chk_autoobs//k5ts2/ autoobs is running! 2006.285.20:13:01.57/chk_autoobs//k5ts3/ autoobs is running! 2006.285.20:13:02.06/chk_autoobs//k5ts4/ autoobs is running! 2006.285.20:13:02.45/chk_obsdata//k5ts1/T2852010??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.20:13:02.90/chk_obsdata//k5ts2/T2852010??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.20:13:03.40/chk_obsdata//k5ts3/T2852010??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.20:13:03.97/chk_obsdata//k5ts4/T2852010??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.20:13:04.71/k5log//k5ts1_log_newline 2006.285.20:13:05.51/k5log//k5ts2_log_newline 2006.285.20:13:06.44/k5log//k5ts3_log_newline 2006.285.20:13:07.27/k5log//k5ts4_log_newline 2006.285.20:13:07.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.20:13:07.29:setupk4=1 2006.285.20:13:07.29$setupk4/echo=on 2006.285.20:13:07.29$setupk4/pcalon 2006.285.20:13:07.29$pcalon/"no phase cal control is implemented here 2006.285.20:13:07.29$setupk4/"tpicd=stop 2006.285.20:13:07.29$setupk4/"rec=synch_on 2006.285.20:13:07.29$setupk4/"rec_mode=128 2006.285.20:13:07.29$setupk4/!* 2006.285.20:13:07.29$setupk4/recpk4 2006.285.20:13:07.29$recpk4/recpatch= 2006.285.20:13:07.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.20:13:07.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.20:13:07.29$setupk4/vck44 2006.285.20:13:07.29$vck44/valo=1,524.99 2006.285.20:13:07.29#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.20:13:07.29#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.20:13:07.29#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:07.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:13:07.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:13:07.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:13:07.29#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:13:07.29#ibcon#first serial, iclass 39, count 0 2006.285.20:13:07.29#ibcon#enter sib2, iclass 39, count 0 2006.285.20:13:07.30#ibcon#flushed, iclass 39, count 0 2006.285.20:13:07.30#ibcon#about to write, iclass 39, count 0 2006.285.20:13:07.30#ibcon#wrote, iclass 39, count 0 2006.285.20:13:07.30#ibcon#about to read 3, iclass 39, count 0 2006.285.20:13:07.31#ibcon#read 3, iclass 39, count 0 2006.285.20:13:07.31#ibcon#about to read 4, iclass 39, count 0 2006.285.20:13:07.31#ibcon#read 4, iclass 39, count 0 2006.285.20:13:07.31#ibcon#about to read 5, iclass 39, count 0 2006.285.20:13:07.31#ibcon#read 5, iclass 39, count 0 2006.285.20:13:07.31#ibcon#about to read 6, iclass 39, count 0 2006.285.20:13:07.31#ibcon#read 6, iclass 39, count 0 2006.285.20:13:07.31#ibcon#end of sib2, iclass 39, count 0 2006.285.20:13:07.31#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:13:07.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:13:07.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.20:13:07.31#ibcon#*before write, iclass 39, count 0 2006.285.20:13:07.31#ibcon#enter sib2, iclass 39, count 0 2006.285.20:13:07.31#ibcon#flushed, iclass 39, count 0 2006.285.20:13:07.31#ibcon#about to write, iclass 39, count 0 2006.285.20:13:07.31#ibcon#wrote, iclass 39, count 0 2006.285.20:13:07.31#ibcon#about to read 3, iclass 39, count 0 2006.285.20:13:07.36#ibcon#read 3, iclass 39, count 0 2006.285.20:13:07.36#ibcon#about to read 4, iclass 39, count 0 2006.285.20:13:07.36#ibcon#read 4, iclass 39, count 0 2006.285.20:13:07.36#ibcon#about to read 5, iclass 39, count 0 2006.285.20:13:07.36#ibcon#read 5, iclass 39, count 0 2006.285.20:13:07.36#ibcon#about to read 6, iclass 39, count 0 2006.285.20:13:07.36#ibcon#read 6, iclass 39, count 0 2006.285.20:13:07.36#ibcon#end of sib2, iclass 39, count 0 2006.285.20:13:07.36#ibcon#*after write, iclass 39, count 0 2006.285.20:13:07.36#ibcon#*before return 0, iclass 39, count 0 2006.285.20:13:07.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:13:07.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:13:07.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:13:07.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:13:07.36$vck44/va=1,7 2006.285.20:13:07.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.20:13:07.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.20:13:07.36#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:07.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:13:07.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:13:07.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:13:07.36#ibcon#enter wrdev, iclass 3, count 2 2006.285.20:13:07.36#ibcon#first serial, iclass 3, count 2 2006.285.20:13:07.36#ibcon#enter sib2, iclass 3, count 2 2006.285.20:13:07.36#ibcon#flushed, iclass 3, count 2 2006.285.20:13:07.36#ibcon#about to write, iclass 3, count 2 2006.285.20:13:07.36#ibcon#wrote, iclass 3, count 2 2006.285.20:13:07.36#ibcon#about to read 3, iclass 3, count 2 2006.285.20:13:07.38#ibcon#read 3, iclass 3, count 2 2006.285.20:13:07.38#ibcon#about to read 4, iclass 3, count 2 2006.285.20:13:07.38#ibcon#read 4, iclass 3, count 2 2006.285.20:13:07.38#ibcon#about to read 5, iclass 3, count 2 2006.285.20:13:07.38#ibcon#read 5, iclass 3, count 2 2006.285.20:13:07.38#ibcon#about to read 6, iclass 3, count 2 2006.285.20:13:07.38#ibcon#read 6, iclass 3, count 2 2006.285.20:13:07.38#ibcon#end of sib2, iclass 3, count 2 2006.285.20:13:07.38#ibcon#*mode == 0, iclass 3, count 2 2006.285.20:13:07.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.20:13:07.38#ibcon#[25=AT01-07\r\n] 2006.285.20:13:07.38#ibcon#*before write, iclass 3, count 2 2006.285.20:13:07.38#ibcon#enter sib2, iclass 3, count 2 2006.285.20:13:07.38#ibcon#flushed, iclass 3, count 2 2006.285.20:13:07.38#ibcon#about to write, iclass 3, count 2 2006.285.20:13:07.38#ibcon#wrote, iclass 3, count 2 2006.285.20:13:07.38#ibcon#about to read 3, iclass 3, count 2 2006.285.20:13:07.41#ibcon#read 3, iclass 3, count 2 2006.285.20:13:07.41#ibcon#about to read 4, iclass 3, count 2 2006.285.20:13:07.41#ibcon#read 4, iclass 3, count 2 2006.285.20:13:07.41#ibcon#about to read 5, iclass 3, count 2 2006.285.20:13:07.41#ibcon#read 5, iclass 3, count 2 2006.285.20:13:07.41#ibcon#about to read 6, iclass 3, count 2 2006.285.20:13:07.41#ibcon#read 6, iclass 3, count 2 2006.285.20:13:07.41#ibcon#end of sib2, iclass 3, count 2 2006.285.20:13:07.41#ibcon#*after write, iclass 3, count 2 2006.285.20:13:07.41#ibcon#*before return 0, iclass 3, count 2 2006.285.20:13:07.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:13:07.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:13:07.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.20:13:07.41#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:07.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:13:07.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:13:07.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:13:07.53#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:13:07.53#ibcon#first serial, iclass 3, count 0 2006.285.20:13:07.53#ibcon#enter sib2, iclass 3, count 0 2006.285.20:13:07.53#ibcon#flushed, iclass 3, count 0 2006.285.20:13:07.53#ibcon#about to write, iclass 3, count 0 2006.285.20:13:07.53#ibcon#wrote, iclass 3, count 0 2006.285.20:13:07.53#ibcon#about to read 3, iclass 3, count 0 2006.285.20:13:07.55#ibcon#read 3, iclass 3, count 0 2006.285.20:13:07.55#ibcon#about to read 4, iclass 3, count 0 2006.285.20:13:07.55#ibcon#read 4, iclass 3, count 0 2006.285.20:13:07.55#ibcon#about to read 5, iclass 3, count 0 2006.285.20:13:07.55#ibcon#read 5, iclass 3, count 0 2006.285.20:13:07.55#ibcon#about to read 6, iclass 3, count 0 2006.285.20:13:07.55#ibcon#read 6, iclass 3, count 0 2006.285.20:13:07.55#ibcon#end of sib2, iclass 3, count 0 2006.285.20:13:07.55#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:13:07.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:13:07.55#ibcon#[25=USB\r\n] 2006.285.20:13:07.55#ibcon#*before write, iclass 3, count 0 2006.285.20:13:07.55#ibcon#enter sib2, iclass 3, count 0 2006.285.20:13:07.55#ibcon#flushed, iclass 3, count 0 2006.285.20:13:07.55#ibcon#about to write, iclass 3, count 0 2006.285.20:13:07.55#ibcon#wrote, iclass 3, count 0 2006.285.20:13:07.55#ibcon#about to read 3, iclass 3, count 0 2006.285.20:13:07.58#ibcon#read 3, iclass 3, count 0 2006.285.20:13:07.58#ibcon#about to read 4, iclass 3, count 0 2006.285.20:13:07.58#ibcon#read 4, iclass 3, count 0 2006.285.20:13:07.58#ibcon#about to read 5, iclass 3, count 0 2006.285.20:13:07.58#ibcon#read 5, iclass 3, count 0 2006.285.20:13:07.58#ibcon#about to read 6, iclass 3, count 0 2006.285.20:13:07.58#ibcon#read 6, iclass 3, count 0 2006.285.20:13:07.58#ibcon#end of sib2, iclass 3, count 0 2006.285.20:13:07.58#ibcon#*after write, iclass 3, count 0 2006.285.20:13:07.58#ibcon#*before return 0, iclass 3, count 0 2006.285.20:13:07.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:13:07.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:13:07.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:13:07.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:13:07.58$vck44/valo=2,534.99 2006.285.20:13:07.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.20:13:07.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.20:13:07.58#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:07.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:13:07.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:13:07.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:13:07.58#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:13:07.58#ibcon#first serial, iclass 5, count 0 2006.285.20:13:07.58#ibcon#enter sib2, iclass 5, count 0 2006.285.20:13:07.58#ibcon#flushed, iclass 5, count 0 2006.285.20:13:07.58#ibcon#about to write, iclass 5, count 0 2006.285.20:13:07.58#ibcon#wrote, iclass 5, count 0 2006.285.20:13:07.58#ibcon#about to read 3, iclass 5, count 0 2006.285.20:13:07.60#ibcon#read 3, iclass 5, count 0 2006.285.20:13:07.60#ibcon#about to read 4, iclass 5, count 0 2006.285.20:13:07.60#ibcon#read 4, iclass 5, count 0 2006.285.20:13:07.60#ibcon#about to read 5, iclass 5, count 0 2006.285.20:13:07.60#ibcon#read 5, iclass 5, count 0 2006.285.20:13:07.60#ibcon#about to read 6, iclass 5, count 0 2006.285.20:13:07.60#ibcon#read 6, iclass 5, count 0 2006.285.20:13:07.60#ibcon#end of sib2, iclass 5, count 0 2006.285.20:13:07.60#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:13:07.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:13:07.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.20:13:07.60#ibcon#*before write, iclass 5, count 0 2006.285.20:13:07.60#ibcon#enter sib2, iclass 5, count 0 2006.285.20:13:07.60#ibcon#flushed, iclass 5, count 0 2006.285.20:13:07.60#ibcon#about to write, iclass 5, count 0 2006.285.20:13:07.60#ibcon#wrote, iclass 5, count 0 2006.285.20:13:07.60#ibcon#about to read 3, iclass 5, count 0 2006.285.20:13:07.64#ibcon#read 3, iclass 5, count 0 2006.285.20:13:07.64#ibcon#about to read 4, iclass 5, count 0 2006.285.20:13:07.64#ibcon#read 4, iclass 5, count 0 2006.285.20:13:07.64#ibcon#about to read 5, iclass 5, count 0 2006.285.20:13:07.64#ibcon#read 5, iclass 5, count 0 2006.285.20:13:07.64#ibcon#about to read 6, iclass 5, count 0 2006.285.20:13:07.64#ibcon#read 6, iclass 5, count 0 2006.285.20:13:07.64#ibcon#end of sib2, iclass 5, count 0 2006.285.20:13:07.64#ibcon#*after write, iclass 5, count 0 2006.285.20:13:07.64#ibcon#*before return 0, iclass 5, count 0 2006.285.20:13:07.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:13:07.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:13:07.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:13:07.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:13:07.64$vck44/va=2,6 2006.285.20:13:07.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.20:13:07.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.20:13:07.64#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:07.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:13:07.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:13:07.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:13:07.70#ibcon#enter wrdev, iclass 7, count 2 2006.285.20:13:07.70#ibcon#first serial, iclass 7, count 2 2006.285.20:13:07.70#ibcon#enter sib2, iclass 7, count 2 2006.285.20:13:07.70#ibcon#flushed, iclass 7, count 2 2006.285.20:13:07.70#ibcon#about to write, iclass 7, count 2 2006.285.20:13:07.70#ibcon#wrote, iclass 7, count 2 2006.285.20:13:07.70#ibcon#about to read 3, iclass 7, count 2 2006.285.20:13:07.72#ibcon#read 3, iclass 7, count 2 2006.285.20:13:07.72#ibcon#about to read 4, iclass 7, count 2 2006.285.20:13:07.72#ibcon#read 4, iclass 7, count 2 2006.285.20:13:07.72#ibcon#about to read 5, iclass 7, count 2 2006.285.20:13:07.72#ibcon#read 5, iclass 7, count 2 2006.285.20:13:07.72#ibcon#about to read 6, iclass 7, count 2 2006.285.20:13:07.72#ibcon#read 6, iclass 7, count 2 2006.285.20:13:07.72#ibcon#end of sib2, iclass 7, count 2 2006.285.20:13:07.72#ibcon#*mode == 0, iclass 7, count 2 2006.285.20:13:07.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.20:13:07.72#ibcon#[25=AT02-06\r\n] 2006.285.20:13:07.72#ibcon#*before write, iclass 7, count 2 2006.285.20:13:07.72#ibcon#enter sib2, iclass 7, count 2 2006.285.20:13:07.72#ibcon#flushed, iclass 7, count 2 2006.285.20:13:07.72#ibcon#about to write, iclass 7, count 2 2006.285.20:13:07.72#ibcon#wrote, iclass 7, count 2 2006.285.20:13:07.72#ibcon#about to read 3, iclass 7, count 2 2006.285.20:13:07.75#ibcon#read 3, iclass 7, count 2 2006.285.20:13:07.75#ibcon#about to read 4, iclass 7, count 2 2006.285.20:13:07.75#ibcon#read 4, iclass 7, count 2 2006.285.20:13:07.75#ibcon#about to read 5, iclass 7, count 2 2006.285.20:13:07.75#ibcon#read 5, iclass 7, count 2 2006.285.20:13:07.75#ibcon#about to read 6, iclass 7, count 2 2006.285.20:13:07.75#ibcon#read 6, iclass 7, count 2 2006.285.20:13:07.75#ibcon#end of sib2, iclass 7, count 2 2006.285.20:13:07.75#ibcon#*after write, iclass 7, count 2 2006.285.20:13:07.75#ibcon#*before return 0, iclass 7, count 2 2006.285.20:13:07.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:13:07.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:13:07.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.20:13:07.75#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:07.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:13:07.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:13:07.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:13:07.87#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:13:07.87#ibcon#first serial, iclass 7, count 0 2006.285.20:13:07.87#ibcon#enter sib2, iclass 7, count 0 2006.285.20:13:07.87#ibcon#flushed, iclass 7, count 0 2006.285.20:13:07.87#ibcon#about to write, iclass 7, count 0 2006.285.20:13:07.87#ibcon#wrote, iclass 7, count 0 2006.285.20:13:07.87#ibcon#about to read 3, iclass 7, count 0 2006.285.20:13:07.89#ibcon#read 3, iclass 7, count 0 2006.285.20:13:07.89#ibcon#about to read 4, iclass 7, count 0 2006.285.20:13:07.89#ibcon#read 4, iclass 7, count 0 2006.285.20:13:07.89#ibcon#about to read 5, iclass 7, count 0 2006.285.20:13:07.89#ibcon#read 5, iclass 7, count 0 2006.285.20:13:07.89#ibcon#about to read 6, iclass 7, count 0 2006.285.20:13:07.89#ibcon#read 6, iclass 7, count 0 2006.285.20:13:07.89#ibcon#end of sib2, iclass 7, count 0 2006.285.20:13:07.89#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:13:07.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:13:07.89#ibcon#[25=USB\r\n] 2006.285.20:13:07.89#ibcon#*before write, iclass 7, count 0 2006.285.20:13:07.89#ibcon#enter sib2, iclass 7, count 0 2006.285.20:13:07.89#ibcon#flushed, iclass 7, count 0 2006.285.20:13:07.89#ibcon#about to write, iclass 7, count 0 2006.285.20:13:07.89#ibcon#wrote, iclass 7, count 0 2006.285.20:13:07.89#ibcon#about to read 3, iclass 7, count 0 2006.285.20:13:07.92#ibcon#read 3, iclass 7, count 0 2006.285.20:13:07.92#ibcon#about to read 4, iclass 7, count 0 2006.285.20:13:07.92#ibcon#read 4, iclass 7, count 0 2006.285.20:13:07.92#ibcon#about to read 5, iclass 7, count 0 2006.285.20:13:07.92#ibcon#read 5, iclass 7, count 0 2006.285.20:13:07.92#ibcon#about to read 6, iclass 7, count 0 2006.285.20:13:07.92#ibcon#read 6, iclass 7, count 0 2006.285.20:13:07.92#ibcon#end of sib2, iclass 7, count 0 2006.285.20:13:07.92#ibcon#*after write, iclass 7, count 0 2006.285.20:13:07.92#ibcon#*before return 0, iclass 7, count 0 2006.285.20:13:07.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:13:07.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:13:07.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:13:07.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:13:07.92$vck44/valo=3,564.99 2006.285.20:13:07.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.20:13:07.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.20:13:07.92#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:07.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:13:07.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:13:07.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:13:07.92#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:13:07.92#ibcon#first serial, iclass 11, count 0 2006.285.20:13:07.92#ibcon#enter sib2, iclass 11, count 0 2006.285.20:13:07.92#ibcon#flushed, iclass 11, count 0 2006.285.20:13:07.92#ibcon#about to write, iclass 11, count 0 2006.285.20:13:07.92#ibcon#wrote, iclass 11, count 0 2006.285.20:13:07.92#ibcon#about to read 3, iclass 11, count 0 2006.285.20:13:07.94#ibcon#read 3, iclass 11, count 0 2006.285.20:13:08.52#ibcon#about to read 4, iclass 11, count 0 2006.285.20:13:08.52#ibcon#read 4, iclass 11, count 0 2006.285.20:13:08.52#ibcon#about to read 5, iclass 11, count 0 2006.285.20:13:08.52#ibcon#read 5, iclass 11, count 0 2006.285.20:13:08.52#ibcon#about to read 6, iclass 11, count 0 2006.285.20:13:08.52#ibcon#read 6, iclass 11, count 0 2006.285.20:13:08.52#ibcon#end of sib2, iclass 11, count 0 2006.285.20:13:08.52#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:13:08.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:13:08.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.20:13:08.52#ibcon#*before write, iclass 11, count 0 2006.285.20:13:08.52#ibcon#enter sib2, iclass 11, count 0 2006.285.20:13:08.52#ibcon#flushed, iclass 11, count 0 2006.285.20:13:08.52#ibcon#about to write, iclass 11, count 0 2006.285.20:13:08.52#ibcon#wrote, iclass 11, count 0 2006.285.20:13:08.52#ibcon#about to read 3, iclass 11, count 0 2006.285.20:13:08.55#ibcon#read 3, iclass 11, count 0 2006.285.20:13:08.55#ibcon#about to read 4, iclass 11, count 0 2006.285.20:13:08.55#ibcon#read 4, iclass 11, count 0 2006.285.20:13:08.55#ibcon#about to read 5, iclass 11, count 0 2006.285.20:13:08.55#ibcon#read 5, iclass 11, count 0 2006.285.20:13:08.55#ibcon#about to read 6, iclass 11, count 0 2006.285.20:13:08.55#ibcon#read 6, iclass 11, count 0 2006.285.20:13:08.55#ibcon#end of sib2, iclass 11, count 0 2006.285.20:13:08.55#ibcon#*after write, iclass 11, count 0 2006.285.20:13:08.55#ibcon#*before return 0, iclass 11, count 0 2006.285.20:13:08.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:13:08.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:13:08.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:13:08.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:13:08.55$vck44/va=3,7 2006.285.20:13:08.55#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.20:13:08.55#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.20:13:08.55#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:08.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:13:08.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:13:08.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:13:08.55#ibcon#enter wrdev, iclass 13, count 2 2006.285.20:13:08.55#ibcon#first serial, iclass 13, count 2 2006.285.20:13:08.55#ibcon#enter sib2, iclass 13, count 2 2006.285.20:13:08.55#ibcon#flushed, iclass 13, count 2 2006.285.20:13:08.55#ibcon#about to write, iclass 13, count 2 2006.285.20:13:08.55#ibcon#wrote, iclass 13, count 2 2006.285.20:13:08.55#ibcon#about to read 3, iclass 13, count 2 2006.285.20:13:08.57#ibcon#read 3, iclass 13, count 2 2006.285.20:13:08.57#ibcon#about to read 4, iclass 13, count 2 2006.285.20:13:08.57#ibcon#read 4, iclass 13, count 2 2006.285.20:13:08.57#ibcon#about to read 5, iclass 13, count 2 2006.285.20:13:08.57#ibcon#read 5, iclass 13, count 2 2006.285.20:13:08.57#ibcon#about to read 6, iclass 13, count 2 2006.285.20:13:08.57#ibcon#read 6, iclass 13, count 2 2006.285.20:13:08.57#ibcon#end of sib2, iclass 13, count 2 2006.285.20:13:08.57#ibcon#*mode == 0, iclass 13, count 2 2006.285.20:13:08.57#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.20:13:08.57#ibcon#[25=AT03-07\r\n] 2006.285.20:13:08.57#ibcon#*before write, iclass 13, count 2 2006.285.20:13:08.57#ibcon#enter sib2, iclass 13, count 2 2006.285.20:13:08.57#ibcon#flushed, iclass 13, count 2 2006.285.20:13:08.57#ibcon#about to write, iclass 13, count 2 2006.285.20:13:08.57#ibcon#wrote, iclass 13, count 2 2006.285.20:13:08.57#ibcon#about to read 3, iclass 13, count 2 2006.285.20:13:08.60#ibcon#read 3, iclass 13, count 2 2006.285.20:13:08.60#ibcon#about to read 4, iclass 13, count 2 2006.285.20:13:08.60#ibcon#read 4, iclass 13, count 2 2006.285.20:13:08.60#ibcon#about to read 5, iclass 13, count 2 2006.285.20:13:08.60#ibcon#read 5, iclass 13, count 2 2006.285.20:13:08.60#ibcon#about to read 6, iclass 13, count 2 2006.285.20:13:08.60#ibcon#read 6, iclass 13, count 2 2006.285.20:13:08.60#ibcon#end of sib2, iclass 13, count 2 2006.285.20:13:08.60#ibcon#*after write, iclass 13, count 2 2006.285.20:13:08.60#ibcon#*before return 0, iclass 13, count 2 2006.285.20:13:08.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:13:08.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:13:08.60#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.20:13:08.60#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:08.60#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:13:08.72#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:13:08.72#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:13:08.72#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:13:08.72#ibcon#first serial, iclass 13, count 0 2006.285.20:13:08.72#ibcon#enter sib2, iclass 13, count 0 2006.285.20:13:08.72#ibcon#flushed, iclass 13, count 0 2006.285.20:13:08.72#ibcon#about to write, iclass 13, count 0 2006.285.20:13:08.72#ibcon#wrote, iclass 13, count 0 2006.285.20:13:08.72#ibcon#about to read 3, iclass 13, count 0 2006.285.20:13:08.74#ibcon#read 3, iclass 13, count 0 2006.285.20:13:08.74#ibcon#about to read 4, iclass 13, count 0 2006.285.20:13:08.74#ibcon#read 4, iclass 13, count 0 2006.285.20:13:08.74#ibcon#about to read 5, iclass 13, count 0 2006.285.20:13:08.74#ibcon#read 5, iclass 13, count 0 2006.285.20:13:08.74#ibcon#about to read 6, iclass 13, count 0 2006.285.20:13:08.74#ibcon#read 6, iclass 13, count 0 2006.285.20:13:08.74#ibcon#end of sib2, iclass 13, count 0 2006.285.20:13:08.74#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:13:08.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:13:08.74#ibcon#[25=USB\r\n] 2006.285.20:13:08.74#ibcon#*before write, iclass 13, count 0 2006.285.20:13:08.74#ibcon#enter sib2, iclass 13, count 0 2006.285.20:13:08.74#ibcon#flushed, iclass 13, count 0 2006.285.20:13:08.74#ibcon#about to write, iclass 13, count 0 2006.285.20:13:08.74#ibcon#wrote, iclass 13, count 0 2006.285.20:13:08.74#ibcon#about to read 3, iclass 13, count 0 2006.285.20:13:08.77#ibcon#read 3, iclass 13, count 0 2006.285.20:13:08.77#ibcon#about to read 4, iclass 13, count 0 2006.285.20:13:08.77#ibcon#read 4, iclass 13, count 0 2006.285.20:13:08.77#ibcon#about to read 5, iclass 13, count 0 2006.285.20:13:08.77#ibcon#read 5, iclass 13, count 0 2006.285.20:13:08.77#ibcon#about to read 6, iclass 13, count 0 2006.285.20:13:08.77#ibcon#read 6, iclass 13, count 0 2006.285.20:13:08.77#ibcon#end of sib2, iclass 13, count 0 2006.285.20:13:08.77#ibcon#*after write, iclass 13, count 0 2006.285.20:13:08.77#ibcon#*before return 0, iclass 13, count 0 2006.285.20:13:08.77#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:13:08.77#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:13:08.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:13:08.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:13:08.77$vck44/valo=4,624.99 2006.285.20:13:08.77#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.20:13:08.77#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.20:13:08.77#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:08.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:13:08.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:13:08.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:13:08.77#ibcon#enter wrdev, iclass 15, count 0 2006.285.20:13:08.77#ibcon#first serial, iclass 15, count 0 2006.285.20:13:08.77#ibcon#enter sib2, iclass 15, count 0 2006.285.20:13:08.77#ibcon#flushed, iclass 15, count 0 2006.285.20:13:08.77#ibcon#about to write, iclass 15, count 0 2006.285.20:13:08.77#ibcon#wrote, iclass 15, count 0 2006.285.20:13:08.77#ibcon#about to read 3, iclass 15, count 0 2006.285.20:13:08.79#ibcon#read 3, iclass 15, count 0 2006.285.20:13:08.95#ibcon#about to read 4, iclass 15, count 0 2006.285.20:13:08.95#ibcon#read 4, iclass 15, count 0 2006.285.20:13:08.95#ibcon#about to read 5, iclass 15, count 0 2006.285.20:13:08.95#ibcon#read 5, iclass 15, count 0 2006.285.20:13:08.95#ibcon#about to read 6, iclass 15, count 0 2006.285.20:13:08.95#ibcon#read 6, iclass 15, count 0 2006.285.20:13:08.95#ibcon#end of sib2, iclass 15, count 0 2006.285.20:13:08.95#ibcon#*mode == 0, iclass 15, count 0 2006.285.20:13:08.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.20:13:08.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.20:13:08.95#ibcon#*before write, iclass 15, count 0 2006.285.20:13:08.95#ibcon#enter sib2, iclass 15, count 0 2006.285.20:13:08.95#ibcon#flushed, iclass 15, count 0 2006.285.20:13:08.95#ibcon#about to write, iclass 15, count 0 2006.285.20:13:08.95#ibcon#wrote, iclass 15, count 0 2006.285.20:13:08.95#ibcon#about to read 3, iclass 15, count 0 2006.285.20:13:08.99#ibcon#read 3, iclass 15, count 0 2006.285.20:13:08.99#ibcon#about to read 4, iclass 15, count 0 2006.285.20:13:08.99#ibcon#read 4, iclass 15, count 0 2006.285.20:13:08.99#ibcon#about to read 5, iclass 15, count 0 2006.285.20:13:08.99#ibcon#read 5, iclass 15, count 0 2006.285.20:13:08.99#ibcon#about to read 6, iclass 15, count 0 2006.285.20:13:08.99#ibcon#read 6, iclass 15, count 0 2006.285.20:13:08.99#ibcon#end of sib2, iclass 15, count 0 2006.285.20:13:08.99#ibcon#*after write, iclass 15, count 0 2006.285.20:13:08.99#ibcon#*before return 0, iclass 15, count 0 2006.285.20:13:08.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:13:08.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:13:08.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.20:13:08.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.20:13:08.99$vck44/va=4,6 2006.285.20:13:08.99#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.20:13:08.99#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.20:13:08.99#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:08.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:13:08.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:13:08.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:13:08.99#ibcon#enter wrdev, iclass 17, count 2 2006.285.20:13:08.99#ibcon#first serial, iclass 17, count 2 2006.285.20:13:08.99#ibcon#enter sib2, iclass 17, count 2 2006.285.20:13:08.99#ibcon#flushed, iclass 17, count 2 2006.285.20:13:08.99#ibcon#about to write, iclass 17, count 2 2006.285.20:13:08.99#ibcon#wrote, iclass 17, count 2 2006.285.20:13:08.99#ibcon#about to read 3, iclass 17, count 2 2006.285.20:13:09.01#ibcon#read 3, iclass 17, count 2 2006.285.20:13:09.01#ibcon#about to read 4, iclass 17, count 2 2006.285.20:13:09.01#ibcon#read 4, iclass 17, count 2 2006.285.20:13:09.01#ibcon#about to read 5, iclass 17, count 2 2006.285.20:13:09.01#ibcon#read 5, iclass 17, count 2 2006.285.20:13:09.01#ibcon#about to read 6, iclass 17, count 2 2006.285.20:13:09.01#ibcon#read 6, iclass 17, count 2 2006.285.20:13:09.01#ibcon#end of sib2, iclass 17, count 2 2006.285.20:13:09.01#ibcon#*mode == 0, iclass 17, count 2 2006.285.20:13:09.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.20:13:09.01#ibcon#[25=AT04-06\r\n] 2006.285.20:13:09.01#ibcon#*before write, iclass 17, count 2 2006.285.20:13:09.01#ibcon#enter sib2, iclass 17, count 2 2006.285.20:13:09.01#ibcon#flushed, iclass 17, count 2 2006.285.20:13:09.01#ibcon#about to write, iclass 17, count 2 2006.285.20:13:09.01#ibcon#wrote, iclass 17, count 2 2006.285.20:13:09.01#ibcon#about to read 3, iclass 17, count 2 2006.285.20:13:09.04#ibcon#read 3, iclass 17, count 2 2006.285.20:13:09.04#ibcon#about to read 4, iclass 17, count 2 2006.285.20:13:09.04#ibcon#read 4, iclass 17, count 2 2006.285.20:13:09.04#ibcon#about to read 5, iclass 17, count 2 2006.285.20:13:09.04#ibcon#read 5, iclass 17, count 2 2006.285.20:13:09.04#ibcon#about to read 6, iclass 17, count 2 2006.285.20:13:09.04#ibcon#read 6, iclass 17, count 2 2006.285.20:13:09.04#ibcon#end of sib2, iclass 17, count 2 2006.285.20:13:09.04#ibcon#*after write, iclass 17, count 2 2006.285.20:13:09.04#ibcon#*before return 0, iclass 17, count 2 2006.285.20:13:09.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:13:09.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:13:09.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.20:13:09.04#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:09.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:13:09.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:13:09.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:13:09.16#ibcon#enter wrdev, iclass 17, count 0 2006.285.20:13:09.16#ibcon#first serial, iclass 17, count 0 2006.285.20:13:09.16#ibcon#enter sib2, iclass 17, count 0 2006.285.20:13:09.16#ibcon#flushed, iclass 17, count 0 2006.285.20:13:09.16#ibcon#about to write, iclass 17, count 0 2006.285.20:13:09.16#ibcon#wrote, iclass 17, count 0 2006.285.20:13:09.16#ibcon#about to read 3, iclass 17, count 0 2006.285.20:13:09.18#ibcon#read 3, iclass 17, count 0 2006.285.20:13:09.18#ibcon#about to read 4, iclass 17, count 0 2006.285.20:13:09.18#ibcon#read 4, iclass 17, count 0 2006.285.20:13:09.18#ibcon#about to read 5, iclass 17, count 0 2006.285.20:13:09.18#ibcon#read 5, iclass 17, count 0 2006.285.20:13:09.18#ibcon#about to read 6, iclass 17, count 0 2006.285.20:13:09.18#ibcon#read 6, iclass 17, count 0 2006.285.20:13:09.18#ibcon#end of sib2, iclass 17, count 0 2006.285.20:13:09.18#ibcon#*mode == 0, iclass 17, count 0 2006.285.20:13:09.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.20:13:09.18#ibcon#[25=USB\r\n] 2006.285.20:13:09.18#ibcon#*before write, iclass 17, count 0 2006.285.20:13:09.18#ibcon#enter sib2, iclass 17, count 0 2006.285.20:13:09.18#ibcon#flushed, iclass 17, count 0 2006.285.20:13:09.18#ibcon#about to write, iclass 17, count 0 2006.285.20:13:09.18#ibcon#wrote, iclass 17, count 0 2006.285.20:13:09.18#ibcon#about to read 3, iclass 17, count 0 2006.285.20:13:09.21#ibcon#read 3, iclass 17, count 0 2006.285.20:13:09.21#ibcon#about to read 4, iclass 17, count 0 2006.285.20:13:09.21#ibcon#read 4, iclass 17, count 0 2006.285.20:13:09.21#ibcon#about to read 5, iclass 17, count 0 2006.285.20:13:09.21#ibcon#read 5, iclass 17, count 0 2006.285.20:13:09.21#ibcon#about to read 6, iclass 17, count 0 2006.285.20:13:09.21#ibcon#read 6, iclass 17, count 0 2006.285.20:13:09.21#ibcon#end of sib2, iclass 17, count 0 2006.285.20:13:09.21#ibcon#*after write, iclass 17, count 0 2006.285.20:13:09.21#ibcon#*before return 0, iclass 17, count 0 2006.285.20:13:09.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:13:09.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:13:09.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.20:13:09.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.20:13:09.21$vck44/valo=5,734.99 2006.285.20:13:09.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.20:13:09.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.20:13:09.21#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:09.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:13:09.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:13:09.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:13:09.21#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:13:09.21#ibcon#first serial, iclass 19, count 0 2006.285.20:13:09.21#ibcon#enter sib2, iclass 19, count 0 2006.285.20:13:09.21#ibcon#flushed, iclass 19, count 0 2006.285.20:13:09.21#ibcon#about to write, iclass 19, count 0 2006.285.20:13:09.21#ibcon#wrote, iclass 19, count 0 2006.285.20:13:09.21#ibcon#about to read 3, iclass 19, count 0 2006.285.20:13:09.23#ibcon#read 3, iclass 19, count 0 2006.285.20:13:09.23#ibcon#about to read 4, iclass 19, count 0 2006.285.20:13:09.23#ibcon#read 4, iclass 19, count 0 2006.285.20:13:09.23#ibcon#about to read 5, iclass 19, count 0 2006.285.20:13:09.23#ibcon#read 5, iclass 19, count 0 2006.285.20:13:09.23#ibcon#about to read 6, iclass 19, count 0 2006.285.20:13:09.23#ibcon#read 6, iclass 19, count 0 2006.285.20:13:09.23#ibcon#end of sib2, iclass 19, count 0 2006.285.20:13:09.23#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:13:09.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:13:09.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.20:13:09.23#ibcon#*before write, iclass 19, count 0 2006.285.20:13:09.23#ibcon#enter sib2, iclass 19, count 0 2006.285.20:13:09.23#ibcon#flushed, iclass 19, count 0 2006.285.20:13:09.23#ibcon#about to write, iclass 19, count 0 2006.285.20:13:09.23#ibcon#wrote, iclass 19, count 0 2006.285.20:13:09.23#ibcon#about to read 3, iclass 19, count 0 2006.285.20:13:09.27#ibcon#read 3, iclass 19, count 0 2006.285.20:13:09.27#ibcon#about to read 4, iclass 19, count 0 2006.285.20:13:09.27#ibcon#read 4, iclass 19, count 0 2006.285.20:13:09.27#ibcon#about to read 5, iclass 19, count 0 2006.285.20:13:09.27#ibcon#read 5, iclass 19, count 0 2006.285.20:13:09.27#ibcon#about to read 6, iclass 19, count 0 2006.285.20:13:09.27#ibcon#read 6, iclass 19, count 0 2006.285.20:13:09.27#ibcon#end of sib2, iclass 19, count 0 2006.285.20:13:09.27#ibcon#*after write, iclass 19, count 0 2006.285.20:13:09.27#ibcon#*before return 0, iclass 19, count 0 2006.285.20:13:09.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:13:09.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:13:09.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:13:09.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:13:09.27$vck44/va=5,3 2006.285.20:13:09.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.20:13:09.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.20:13:09.27#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:09.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:13:09.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:13:09.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:13:09.33#ibcon#enter wrdev, iclass 21, count 2 2006.285.20:13:09.33#ibcon#first serial, iclass 21, count 2 2006.285.20:13:09.33#ibcon#enter sib2, iclass 21, count 2 2006.285.20:13:09.33#ibcon#flushed, iclass 21, count 2 2006.285.20:13:09.33#ibcon#about to write, iclass 21, count 2 2006.285.20:13:09.33#ibcon#wrote, iclass 21, count 2 2006.285.20:13:09.33#ibcon#about to read 3, iclass 21, count 2 2006.285.20:13:09.35#ibcon#read 3, iclass 21, count 2 2006.285.20:13:09.35#ibcon#about to read 4, iclass 21, count 2 2006.285.20:13:09.35#ibcon#read 4, iclass 21, count 2 2006.285.20:13:09.35#ibcon#about to read 5, iclass 21, count 2 2006.285.20:13:09.35#ibcon#read 5, iclass 21, count 2 2006.285.20:13:09.35#ibcon#about to read 6, iclass 21, count 2 2006.285.20:13:09.35#ibcon#read 6, iclass 21, count 2 2006.285.20:13:09.35#ibcon#end of sib2, iclass 21, count 2 2006.285.20:13:09.35#ibcon#*mode == 0, iclass 21, count 2 2006.285.20:13:09.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.20:13:09.35#ibcon#[25=AT05-03\r\n] 2006.285.20:13:09.35#ibcon#*before write, iclass 21, count 2 2006.285.20:13:09.35#ibcon#enter sib2, iclass 21, count 2 2006.285.20:13:09.35#ibcon#flushed, iclass 21, count 2 2006.285.20:13:09.35#ibcon#about to write, iclass 21, count 2 2006.285.20:13:09.35#ibcon#wrote, iclass 21, count 2 2006.285.20:13:09.35#ibcon#about to read 3, iclass 21, count 2 2006.285.20:13:09.38#ibcon#read 3, iclass 21, count 2 2006.285.20:13:09.38#ibcon#about to read 4, iclass 21, count 2 2006.285.20:13:09.38#ibcon#read 4, iclass 21, count 2 2006.285.20:13:09.38#ibcon#about to read 5, iclass 21, count 2 2006.285.20:13:09.38#ibcon#read 5, iclass 21, count 2 2006.285.20:13:09.38#ibcon#about to read 6, iclass 21, count 2 2006.285.20:13:09.38#ibcon#read 6, iclass 21, count 2 2006.285.20:13:09.38#ibcon#end of sib2, iclass 21, count 2 2006.285.20:13:09.38#ibcon#*after write, iclass 21, count 2 2006.285.20:13:09.38#ibcon#*before return 0, iclass 21, count 2 2006.285.20:13:09.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:13:09.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:13:09.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.20:13:09.38#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:09.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:13:09.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:13:09.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:13:09.50#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:13:09.50#ibcon#first serial, iclass 21, count 0 2006.285.20:13:09.50#ibcon#enter sib2, iclass 21, count 0 2006.285.20:13:09.50#ibcon#flushed, iclass 21, count 0 2006.285.20:13:09.50#ibcon#about to write, iclass 21, count 0 2006.285.20:13:09.50#ibcon#wrote, iclass 21, count 0 2006.285.20:13:09.50#ibcon#about to read 3, iclass 21, count 0 2006.285.20:13:09.52#ibcon#read 3, iclass 21, count 0 2006.285.20:13:09.52#ibcon#about to read 4, iclass 21, count 0 2006.285.20:13:09.52#ibcon#read 4, iclass 21, count 0 2006.285.20:13:09.52#ibcon#about to read 5, iclass 21, count 0 2006.285.20:13:09.52#ibcon#read 5, iclass 21, count 0 2006.285.20:13:09.52#ibcon#about to read 6, iclass 21, count 0 2006.285.20:13:09.52#ibcon#read 6, iclass 21, count 0 2006.285.20:13:09.52#ibcon#end of sib2, iclass 21, count 0 2006.285.20:13:09.52#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:13:09.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:13:09.52#ibcon#[25=USB\r\n] 2006.285.20:13:09.52#ibcon#*before write, iclass 21, count 0 2006.285.20:13:09.52#ibcon#enter sib2, iclass 21, count 0 2006.285.20:13:09.52#ibcon#flushed, iclass 21, count 0 2006.285.20:13:09.52#ibcon#about to write, iclass 21, count 0 2006.285.20:13:09.52#ibcon#wrote, iclass 21, count 0 2006.285.20:13:09.52#ibcon#about to read 3, iclass 21, count 0 2006.285.20:13:09.55#ibcon#read 3, iclass 21, count 0 2006.285.20:13:09.55#ibcon#about to read 4, iclass 21, count 0 2006.285.20:13:09.55#ibcon#read 4, iclass 21, count 0 2006.285.20:13:09.55#ibcon#about to read 5, iclass 21, count 0 2006.285.20:13:09.55#ibcon#read 5, iclass 21, count 0 2006.285.20:13:09.55#ibcon#about to read 6, iclass 21, count 0 2006.285.20:13:09.55#ibcon#read 6, iclass 21, count 0 2006.285.20:13:09.55#ibcon#end of sib2, iclass 21, count 0 2006.285.20:13:09.55#ibcon#*after write, iclass 21, count 0 2006.285.20:13:09.55#ibcon#*before return 0, iclass 21, count 0 2006.285.20:13:09.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:13:09.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:13:09.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:13:09.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:13:09.55$vck44/valo=6,814.99 2006.285.20:13:09.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.20:13:09.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.20:13:09.55#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:09.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:13:09.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:13:09.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:13:09.55#ibcon#enter wrdev, iclass 23, count 0 2006.285.20:13:09.55#ibcon#first serial, iclass 23, count 0 2006.285.20:13:09.55#ibcon#enter sib2, iclass 23, count 0 2006.285.20:13:09.55#ibcon#flushed, iclass 23, count 0 2006.285.20:13:09.55#ibcon#about to write, iclass 23, count 0 2006.285.20:13:09.55#ibcon#wrote, iclass 23, count 0 2006.285.20:13:09.55#ibcon#about to read 3, iclass 23, count 0 2006.285.20:13:09.57#ibcon#read 3, iclass 23, count 0 2006.285.20:13:09.57#ibcon#about to read 4, iclass 23, count 0 2006.285.20:13:09.57#ibcon#read 4, iclass 23, count 0 2006.285.20:13:09.57#ibcon#about to read 5, iclass 23, count 0 2006.285.20:13:09.57#ibcon#read 5, iclass 23, count 0 2006.285.20:13:09.57#ibcon#about to read 6, iclass 23, count 0 2006.285.20:13:09.57#ibcon#read 6, iclass 23, count 0 2006.285.20:13:09.57#ibcon#end of sib2, iclass 23, count 0 2006.285.20:13:09.57#ibcon#*mode == 0, iclass 23, count 0 2006.285.20:13:09.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.20:13:09.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.20:13:09.57#ibcon#*before write, iclass 23, count 0 2006.285.20:13:09.57#ibcon#enter sib2, iclass 23, count 0 2006.285.20:13:09.57#ibcon#flushed, iclass 23, count 0 2006.285.20:13:09.57#ibcon#about to write, iclass 23, count 0 2006.285.20:13:09.57#ibcon#wrote, iclass 23, count 0 2006.285.20:13:09.57#ibcon#about to read 3, iclass 23, count 0 2006.285.20:13:09.61#ibcon#read 3, iclass 23, count 0 2006.285.20:13:09.61#ibcon#about to read 4, iclass 23, count 0 2006.285.20:13:09.61#ibcon#read 4, iclass 23, count 0 2006.285.20:13:09.61#ibcon#about to read 5, iclass 23, count 0 2006.285.20:13:09.61#ibcon#read 5, iclass 23, count 0 2006.285.20:13:09.61#ibcon#about to read 6, iclass 23, count 0 2006.285.20:13:09.61#ibcon#read 6, iclass 23, count 0 2006.285.20:13:09.61#ibcon#end of sib2, iclass 23, count 0 2006.285.20:13:09.61#ibcon#*after write, iclass 23, count 0 2006.285.20:13:09.61#ibcon#*before return 0, iclass 23, count 0 2006.285.20:13:09.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:13:09.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:13:09.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.20:13:09.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.20:13:09.61$vck44/va=6,4 2006.285.20:13:09.61#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.20:13:09.61#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.20:13:09.61#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:09.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:13:09.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:13:09.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:13:09.67#ibcon#enter wrdev, iclass 25, count 2 2006.285.20:13:09.67#ibcon#first serial, iclass 25, count 2 2006.285.20:13:09.67#ibcon#enter sib2, iclass 25, count 2 2006.285.20:13:09.67#ibcon#flushed, iclass 25, count 2 2006.285.20:13:09.67#ibcon#about to write, iclass 25, count 2 2006.285.20:13:09.67#ibcon#wrote, iclass 25, count 2 2006.285.20:13:09.67#ibcon#about to read 3, iclass 25, count 2 2006.285.20:13:09.69#ibcon#read 3, iclass 25, count 2 2006.285.20:13:09.69#ibcon#about to read 4, iclass 25, count 2 2006.285.20:13:09.69#ibcon#read 4, iclass 25, count 2 2006.285.20:13:09.69#ibcon#about to read 5, iclass 25, count 2 2006.285.20:13:09.69#ibcon#read 5, iclass 25, count 2 2006.285.20:13:09.69#ibcon#about to read 6, iclass 25, count 2 2006.285.20:13:09.69#ibcon#read 6, iclass 25, count 2 2006.285.20:13:09.69#ibcon#end of sib2, iclass 25, count 2 2006.285.20:13:09.69#ibcon#*mode == 0, iclass 25, count 2 2006.285.20:13:09.69#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.20:13:09.69#ibcon#[25=AT06-04\r\n] 2006.285.20:13:09.69#ibcon#*before write, iclass 25, count 2 2006.285.20:13:09.69#ibcon#enter sib2, iclass 25, count 2 2006.285.20:13:09.69#ibcon#flushed, iclass 25, count 2 2006.285.20:13:09.69#ibcon#about to write, iclass 25, count 2 2006.285.20:13:09.69#ibcon#wrote, iclass 25, count 2 2006.285.20:13:09.69#ibcon#about to read 3, iclass 25, count 2 2006.285.20:13:09.72#ibcon#read 3, iclass 25, count 2 2006.285.20:13:09.72#ibcon#about to read 4, iclass 25, count 2 2006.285.20:13:09.72#ibcon#read 4, iclass 25, count 2 2006.285.20:13:09.72#ibcon#about to read 5, iclass 25, count 2 2006.285.20:13:09.72#ibcon#read 5, iclass 25, count 2 2006.285.20:13:09.72#ibcon#about to read 6, iclass 25, count 2 2006.285.20:13:09.72#ibcon#read 6, iclass 25, count 2 2006.285.20:13:09.72#ibcon#end of sib2, iclass 25, count 2 2006.285.20:13:09.72#ibcon#*after write, iclass 25, count 2 2006.285.20:13:09.72#ibcon#*before return 0, iclass 25, count 2 2006.285.20:13:09.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:13:09.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:13:09.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.20:13:09.72#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:09.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:13:09.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:13:09.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:13:09.84#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:13:09.84#ibcon#first serial, iclass 25, count 0 2006.285.20:13:09.84#ibcon#enter sib2, iclass 25, count 0 2006.285.20:13:09.84#ibcon#flushed, iclass 25, count 0 2006.285.20:13:09.84#ibcon#about to write, iclass 25, count 0 2006.285.20:13:09.84#ibcon#wrote, iclass 25, count 0 2006.285.20:13:09.84#ibcon#about to read 3, iclass 25, count 0 2006.285.20:13:09.86#ibcon#read 3, iclass 25, count 0 2006.285.20:13:09.86#ibcon#about to read 4, iclass 25, count 0 2006.285.20:13:09.86#ibcon#read 4, iclass 25, count 0 2006.285.20:13:09.86#ibcon#about to read 5, iclass 25, count 0 2006.285.20:13:09.86#ibcon#read 5, iclass 25, count 0 2006.285.20:13:09.86#ibcon#about to read 6, iclass 25, count 0 2006.285.20:13:09.86#ibcon#read 6, iclass 25, count 0 2006.285.20:13:09.86#ibcon#end of sib2, iclass 25, count 0 2006.285.20:13:09.86#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:13:09.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:13:09.86#ibcon#[25=USB\r\n] 2006.285.20:13:09.86#ibcon#*before write, iclass 25, count 0 2006.285.20:13:09.86#ibcon#enter sib2, iclass 25, count 0 2006.285.20:13:09.86#ibcon#flushed, iclass 25, count 0 2006.285.20:13:09.86#ibcon#about to write, iclass 25, count 0 2006.285.20:13:09.86#ibcon#wrote, iclass 25, count 0 2006.285.20:13:09.86#ibcon#about to read 3, iclass 25, count 0 2006.285.20:13:09.89#ibcon#read 3, iclass 25, count 0 2006.285.20:13:09.89#ibcon#about to read 4, iclass 25, count 0 2006.285.20:13:09.89#ibcon#read 4, iclass 25, count 0 2006.285.20:13:09.89#ibcon#about to read 5, iclass 25, count 0 2006.285.20:13:09.89#ibcon#read 5, iclass 25, count 0 2006.285.20:13:09.89#ibcon#about to read 6, iclass 25, count 0 2006.285.20:13:09.89#ibcon#read 6, iclass 25, count 0 2006.285.20:13:09.89#ibcon#end of sib2, iclass 25, count 0 2006.285.20:13:09.89#ibcon#*after write, iclass 25, count 0 2006.285.20:13:09.89#ibcon#*before return 0, iclass 25, count 0 2006.285.20:13:09.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:13:09.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:13:09.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:13:09.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:13:09.89$vck44/valo=7,864.99 2006.285.20:13:09.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.20:13:09.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.20:13:09.89#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:09.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:13:09.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:13:09.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:13:09.89#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:13:09.89#ibcon#first serial, iclass 27, count 0 2006.285.20:13:09.89#ibcon#enter sib2, iclass 27, count 0 2006.285.20:13:09.89#ibcon#flushed, iclass 27, count 0 2006.285.20:13:09.89#ibcon#about to write, iclass 27, count 0 2006.285.20:13:09.89#ibcon#wrote, iclass 27, count 0 2006.285.20:13:09.89#ibcon#about to read 3, iclass 27, count 0 2006.285.20:13:09.91#ibcon#read 3, iclass 27, count 0 2006.285.20:13:10.13#ibcon#about to read 4, iclass 27, count 0 2006.285.20:13:10.13#ibcon#read 4, iclass 27, count 0 2006.285.20:13:10.13#ibcon#about to read 5, iclass 27, count 0 2006.285.20:13:10.13#ibcon#read 5, iclass 27, count 0 2006.285.20:13:10.13#ibcon#about to read 6, iclass 27, count 0 2006.285.20:13:10.13#ibcon#read 6, iclass 27, count 0 2006.285.20:13:10.13#ibcon#end of sib2, iclass 27, count 0 2006.285.20:13:10.13#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:13:10.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:13:10.13#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.20:13:10.13#ibcon#*before write, iclass 27, count 0 2006.285.20:13:10.13#ibcon#enter sib2, iclass 27, count 0 2006.285.20:13:10.13#ibcon#flushed, iclass 27, count 0 2006.285.20:13:10.13#ibcon#about to write, iclass 27, count 0 2006.285.20:13:10.13#ibcon#wrote, iclass 27, count 0 2006.285.20:13:10.13#ibcon#about to read 3, iclass 27, count 0 2006.285.20:13:10.16#ibcon#read 3, iclass 27, count 0 2006.285.20:13:10.16#ibcon#about to read 4, iclass 27, count 0 2006.285.20:13:10.16#ibcon#read 4, iclass 27, count 0 2006.285.20:13:10.16#ibcon#about to read 5, iclass 27, count 0 2006.285.20:13:10.16#ibcon#read 5, iclass 27, count 0 2006.285.20:13:10.16#ibcon#about to read 6, iclass 27, count 0 2006.285.20:13:10.16#ibcon#read 6, iclass 27, count 0 2006.285.20:13:10.16#ibcon#end of sib2, iclass 27, count 0 2006.285.20:13:10.16#ibcon#*after write, iclass 27, count 0 2006.285.20:13:10.16#ibcon#*before return 0, iclass 27, count 0 2006.285.20:13:10.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:13:10.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:13:10.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:13:10.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:13:10.16$vck44/va=7,4 2006.285.20:13:10.16#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.20:13:10.16#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.20:13:10.16#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:10.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:13:10.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:13:10.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:13:10.16#ibcon#enter wrdev, iclass 29, count 2 2006.285.20:13:10.16#ibcon#first serial, iclass 29, count 2 2006.285.20:13:10.16#ibcon#enter sib2, iclass 29, count 2 2006.285.20:13:10.16#ibcon#flushed, iclass 29, count 2 2006.285.20:13:10.16#ibcon#about to write, iclass 29, count 2 2006.285.20:13:10.16#ibcon#wrote, iclass 29, count 2 2006.285.20:13:10.16#ibcon#about to read 3, iclass 29, count 2 2006.285.20:13:10.18#ibcon#read 3, iclass 29, count 2 2006.285.20:13:10.18#ibcon#about to read 4, iclass 29, count 2 2006.285.20:13:10.18#ibcon#read 4, iclass 29, count 2 2006.285.20:13:10.18#ibcon#about to read 5, iclass 29, count 2 2006.285.20:13:10.18#ibcon#read 5, iclass 29, count 2 2006.285.20:13:10.18#ibcon#about to read 6, iclass 29, count 2 2006.285.20:13:10.18#ibcon#read 6, iclass 29, count 2 2006.285.20:13:10.18#ibcon#end of sib2, iclass 29, count 2 2006.285.20:13:10.18#ibcon#*mode == 0, iclass 29, count 2 2006.285.20:13:10.18#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.20:13:10.18#ibcon#[25=AT07-04\r\n] 2006.285.20:13:10.18#ibcon#*before write, iclass 29, count 2 2006.285.20:13:10.18#ibcon#enter sib2, iclass 29, count 2 2006.285.20:13:10.18#ibcon#flushed, iclass 29, count 2 2006.285.20:13:10.18#ibcon#about to write, iclass 29, count 2 2006.285.20:13:10.18#ibcon#wrote, iclass 29, count 2 2006.285.20:13:10.18#ibcon#about to read 3, iclass 29, count 2 2006.285.20:13:10.21#ibcon#read 3, iclass 29, count 2 2006.285.20:13:10.21#ibcon#about to read 4, iclass 29, count 2 2006.285.20:13:10.21#ibcon#read 4, iclass 29, count 2 2006.285.20:13:10.21#ibcon#about to read 5, iclass 29, count 2 2006.285.20:13:10.21#ibcon#read 5, iclass 29, count 2 2006.285.20:13:10.21#ibcon#about to read 6, iclass 29, count 2 2006.285.20:13:10.21#ibcon#read 6, iclass 29, count 2 2006.285.20:13:10.21#ibcon#end of sib2, iclass 29, count 2 2006.285.20:13:10.21#ibcon#*after write, iclass 29, count 2 2006.285.20:13:10.21#ibcon#*before return 0, iclass 29, count 2 2006.285.20:13:10.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:13:10.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:13:10.21#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.20:13:10.21#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:10.21#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:13:10.33#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:13:10.33#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:13:10.33#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:13:10.33#ibcon#first serial, iclass 29, count 0 2006.285.20:13:10.33#ibcon#enter sib2, iclass 29, count 0 2006.285.20:13:10.33#ibcon#flushed, iclass 29, count 0 2006.285.20:13:10.33#ibcon#about to write, iclass 29, count 0 2006.285.20:13:10.33#ibcon#wrote, iclass 29, count 0 2006.285.20:13:10.33#ibcon#about to read 3, iclass 29, count 0 2006.285.20:13:10.35#ibcon#read 3, iclass 29, count 0 2006.285.20:13:10.35#ibcon#about to read 4, iclass 29, count 0 2006.285.20:13:10.35#ibcon#read 4, iclass 29, count 0 2006.285.20:13:10.35#ibcon#about to read 5, iclass 29, count 0 2006.285.20:13:10.35#ibcon#read 5, iclass 29, count 0 2006.285.20:13:10.35#ibcon#about to read 6, iclass 29, count 0 2006.285.20:13:10.35#ibcon#read 6, iclass 29, count 0 2006.285.20:13:10.35#ibcon#end of sib2, iclass 29, count 0 2006.285.20:13:10.35#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:13:10.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:13:10.35#ibcon#[25=USB\r\n] 2006.285.20:13:10.35#ibcon#*before write, iclass 29, count 0 2006.285.20:13:10.35#ibcon#enter sib2, iclass 29, count 0 2006.285.20:13:10.35#ibcon#flushed, iclass 29, count 0 2006.285.20:13:10.35#ibcon#about to write, iclass 29, count 0 2006.285.20:13:10.35#ibcon#wrote, iclass 29, count 0 2006.285.20:13:10.35#ibcon#about to read 3, iclass 29, count 0 2006.285.20:13:10.38#ibcon#read 3, iclass 29, count 0 2006.285.20:13:10.38#ibcon#about to read 4, iclass 29, count 0 2006.285.20:13:10.38#ibcon#read 4, iclass 29, count 0 2006.285.20:13:10.38#ibcon#about to read 5, iclass 29, count 0 2006.285.20:13:10.38#ibcon#read 5, iclass 29, count 0 2006.285.20:13:10.38#ibcon#about to read 6, iclass 29, count 0 2006.285.20:13:10.38#ibcon#read 6, iclass 29, count 0 2006.285.20:13:10.38#ibcon#end of sib2, iclass 29, count 0 2006.285.20:13:10.38#ibcon#*after write, iclass 29, count 0 2006.285.20:13:10.38#ibcon#*before return 0, iclass 29, count 0 2006.285.20:13:10.38#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:13:10.38#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:13:10.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:13:10.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:13:10.38$vck44/valo=8,884.99 2006.285.20:13:10.38#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.20:13:10.38#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.20:13:10.38#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:10.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:13:10.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:13:10.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:13:10.38#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:13:10.38#ibcon#first serial, iclass 31, count 0 2006.285.20:13:10.38#ibcon#enter sib2, iclass 31, count 0 2006.285.20:13:10.38#ibcon#flushed, iclass 31, count 0 2006.285.20:13:10.38#ibcon#about to write, iclass 31, count 0 2006.285.20:13:10.38#ibcon#wrote, iclass 31, count 0 2006.285.20:13:10.38#ibcon#about to read 3, iclass 31, count 0 2006.285.20:13:10.40#ibcon#read 3, iclass 31, count 0 2006.285.20:13:10.40#ibcon#about to read 4, iclass 31, count 0 2006.285.20:13:10.40#ibcon#read 4, iclass 31, count 0 2006.285.20:13:10.40#ibcon#about to read 5, iclass 31, count 0 2006.285.20:13:10.40#ibcon#read 5, iclass 31, count 0 2006.285.20:13:10.40#ibcon#about to read 6, iclass 31, count 0 2006.285.20:13:10.40#ibcon#read 6, iclass 31, count 0 2006.285.20:13:10.40#ibcon#end of sib2, iclass 31, count 0 2006.285.20:13:10.40#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:13:10.40#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:13:10.40#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.20:13:10.40#ibcon#*before write, iclass 31, count 0 2006.285.20:13:10.40#ibcon#enter sib2, iclass 31, count 0 2006.285.20:13:10.40#ibcon#flushed, iclass 31, count 0 2006.285.20:13:10.40#ibcon#about to write, iclass 31, count 0 2006.285.20:13:10.40#ibcon#wrote, iclass 31, count 0 2006.285.20:13:10.40#ibcon#about to read 3, iclass 31, count 0 2006.285.20:13:10.44#ibcon#read 3, iclass 31, count 0 2006.285.20:13:10.44#ibcon#about to read 4, iclass 31, count 0 2006.285.20:13:10.44#ibcon#read 4, iclass 31, count 0 2006.285.20:13:10.44#ibcon#about to read 5, iclass 31, count 0 2006.285.20:13:10.44#ibcon#read 5, iclass 31, count 0 2006.285.20:13:10.44#ibcon#about to read 6, iclass 31, count 0 2006.285.20:13:10.44#ibcon#read 6, iclass 31, count 0 2006.285.20:13:10.44#ibcon#end of sib2, iclass 31, count 0 2006.285.20:13:10.44#ibcon#*after write, iclass 31, count 0 2006.285.20:13:10.44#ibcon#*before return 0, iclass 31, count 0 2006.285.20:13:10.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:13:10.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:13:10.44#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:13:10.44#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:13:10.44$vck44/va=8,3 2006.285.20:13:10.44#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.20:13:10.44#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.20:13:10.44#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:10.44#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:13:10.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:13:10.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:13:10.50#ibcon#enter wrdev, iclass 33, count 2 2006.285.20:13:10.50#ibcon#first serial, iclass 33, count 2 2006.285.20:13:10.50#ibcon#enter sib2, iclass 33, count 2 2006.285.20:13:10.50#ibcon#flushed, iclass 33, count 2 2006.285.20:13:10.50#ibcon#about to write, iclass 33, count 2 2006.285.20:13:10.50#ibcon#wrote, iclass 33, count 2 2006.285.20:13:10.50#ibcon#about to read 3, iclass 33, count 2 2006.285.20:13:10.52#ibcon#read 3, iclass 33, count 2 2006.285.20:13:10.52#ibcon#about to read 4, iclass 33, count 2 2006.285.20:13:10.52#ibcon#read 4, iclass 33, count 2 2006.285.20:13:10.52#ibcon#about to read 5, iclass 33, count 2 2006.285.20:13:10.52#ibcon#read 5, iclass 33, count 2 2006.285.20:13:10.52#ibcon#about to read 6, iclass 33, count 2 2006.285.20:13:10.52#ibcon#read 6, iclass 33, count 2 2006.285.20:13:10.52#ibcon#end of sib2, iclass 33, count 2 2006.285.20:13:10.52#ibcon#*mode == 0, iclass 33, count 2 2006.285.20:13:10.52#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.20:13:10.52#ibcon#[25=AT08-03\r\n] 2006.285.20:13:10.52#ibcon#*before write, iclass 33, count 2 2006.285.20:13:10.52#ibcon#enter sib2, iclass 33, count 2 2006.285.20:13:10.52#ibcon#flushed, iclass 33, count 2 2006.285.20:13:10.52#ibcon#about to write, iclass 33, count 2 2006.285.20:13:10.52#ibcon#wrote, iclass 33, count 2 2006.285.20:13:10.52#ibcon#about to read 3, iclass 33, count 2 2006.285.20:13:10.55#ibcon#read 3, iclass 33, count 2 2006.285.20:13:10.55#ibcon#about to read 4, iclass 33, count 2 2006.285.20:13:10.55#ibcon#read 4, iclass 33, count 2 2006.285.20:13:10.55#ibcon#about to read 5, iclass 33, count 2 2006.285.20:13:10.55#ibcon#read 5, iclass 33, count 2 2006.285.20:13:10.55#ibcon#about to read 6, iclass 33, count 2 2006.285.20:13:10.55#ibcon#read 6, iclass 33, count 2 2006.285.20:13:10.55#ibcon#end of sib2, iclass 33, count 2 2006.285.20:13:10.55#ibcon#*after write, iclass 33, count 2 2006.285.20:13:10.55#ibcon#*before return 0, iclass 33, count 2 2006.285.20:13:10.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:13:10.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:13:10.55#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.20:13:10.55#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:10.55#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:13:10.67#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:13:10.67#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:13:10.67#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:13:10.67#ibcon#first serial, iclass 33, count 0 2006.285.20:13:10.67#ibcon#enter sib2, iclass 33, count 0 2006.285.20:13:10.67#ibcon#flushed, iclass 33, count 0 2006.285.20:13:10.67#ibcon#about to write, iclass 33, count 0 2006.285.20:13:10.67#ibcon#wrote, iclass 33, count 0 2006.285.20:13:10.67#ibcon#about to read 3, iclass 33, count 0 2006.285.20:13:10.69#ibcon#read 3, iclass 33, count 0 2006.285.20:13:10.69#ibcon#about to read 4, iclass 33, count 0 2006.285.20:13:10.69#ibcon#read 4, iclass 33, count 0 2006.285.20:13:10.69#ibcon#about to read 5, iclass 33, count 0 2006.285.20:13:10.69#ibcon#read 5, iclass 33, count 0 2006.285.20:13:10.69#ibcon#about to read 6, iclass 33, count 0 2006.285.20:13:10.69#ibcon#read 6, iclass 33, count 0 2006.285.20:13:10.69#ibcon#end of sib2, iclass 33, count 0 2006.285.20:13:10.69#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:13:10.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:13:10.69#ibcon#[25=USB\r\n] 2006.285.20:13:10.69#ibcon#*before write, iclass 33, count 0 2006.285.20:13:10.69#ibcon#enter sib2, iclass 33, count 0 2006.285.20:13:10.69#ibcon#flushed, iclass 33, count 0 2006.285.20:13:10.69#ibcon#about to write, iclass 33, count 0 2006.285.20:13:10.69#ibcon#wrote, iclass 33, count 0 2006.285.20:13:10.69#ibcon#about to read 3, iclass 33, count 0 2006.285.20:13:10.72#ibcon#read 3, iclass 33, count 0 2006.285.20:13:10.72#ibcon#about to read 4, iclass 33, count 0 2006.285.20:13:10.72#ibcon#read 4, iclass 33, count 0 2006.285.20:13:10.72#ibcon#about to read 5, iclass 33, count 0 2006.285.20:13:10.72#ibcon#read 5, iclass 33, count 0 2006.285.20:13:10.72#ibcon#about to read 6, iclass 33, count 0 2006.285.20:13:10.72#ibcon#read 6, iclass 33, count 0 2006.285.20:13:10.72#ibcon#end of sib2, iclass 33, count 0 2006.285.20:13:10.72#ibcon#*after write, iclass 33, count 0 2006.285.20:13:10.72#ibcon#*before return 0, iclass 33, count 0 2006.285.20:13:10.72#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:13:10.72#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:13:10.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:13:10.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:13:10.72$vck44/vblo=1,629.99 2006.285.20:13:10.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.20:13:10.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.20:13:10.72#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:10.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:13:10.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:13:10.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:13:10.72#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:13:10.72#ibcon#first serial, iclass 35, count 0 2006.285.20:13:10.72#ibcon#enter sib2, iclass 35, count 0 2006.285.20:13:10.72#ibcon#flushed, iclass 35, count 0 2006.285.20:13:10.72#ibcon#about to write, iclass 35, count 0 2006.285.20:13:10.72#ibcon#wrote, iclass 35, count 0 2006.285.20:13:10.72#ibcon#about to read 3, iclass 35, count 0 2006.285.20:13:10.74#ibcon#read 3, iclass 35, count 0 2006.285.20:13:10.74#ibcon#about to read 4, iclass 35, count 0 2006.285.20:13:10.74#ibcon#read 4, iclass 35, count 0 2006.285.20:13:10.74#ibcon#about to read 5, iclass 35, count 0 2006.285.20:13:10.74#ibcon#read 5, iclass 35, count 0 2006.285.20:13:10.74#ibcon#about to read 6, iclass 35, count 0 2006.285.20:13:10.74#ibcon#read 6, iclass 35, count 0 2006.285.20:13:10.74#ibcon#end of sib2, iclass 35, count 0 2006.285.20:13:10.74#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:13:10.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:13:10.74#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.20:13:10.74#ibcon#*before write, iclass 35, count 0 2006.285.20:13:10.74#ibcon#enter sib2, iclass 35, count 0 2006.285.20:13:10.74#ibcon#flushed, iclass 35, count 0 2006.285.20:13:10.74#ibcon#about to write, iclass 35, count 0 2006.285.20:13:10.74#ibcon#wrote, iclass 35, count 0 2006.285.20:13:10.74#ibcon#about to read 3, iclass 35, count 0 2006.285.20:13:10.78#ibcon#read 3, iclass 35, count 0 2006.285.20:13:10.78#ibcon#about to read 4, iclass 35, count 0 2006.285.20:13:10.78#ibcon#read 4, iclass 35, count 0 2006.285.20:13:10.78#ibcon#about to read 5, iclass 35, count 0 2006.285.20:13:10.78#ibcon#read 5, iclass 35, count 0 2006.285.20:13:10.78#ibcon#about to read 6, iclass 35, count 0 2006.285.20:13:10.78#ibcon#read 6, iclass 35, count 0 2006.285.20:13:10.78#ibcon#end of sib2, iclass 35, count 0 2006.285.20:13:10.78#ibcon#*after write, iclass 35, count 0 2006.285.20:13:10.78#ibcon#*before return 0, iclass 35, count 0 2006.285.20:13:10.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:13:10.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:13:10.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:13:10.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:13:10.78$vck44/vb=1,4 2006.285.20:13:10.78#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.20:13:10.78#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.20:13:10.78#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:10.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:13:10.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:13:10.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:13:10.78#ibcon#enter wrdev, iclass 37, count 2 2006.285.20:13:10.78#ibcon#first serial, iclass 37, count 2 2006.285.20:13:10.78#ibcon#enter sib2, iclass 37, count 2 2006.285.20:13:10.78#ibcon#flushed, iclass 37, count 2 2006.285.20:13:10.78#ibcon#about to write, iclass 37, count 2 2006.285.20:13:10.78#ibcon#wrote, iclass 37, count 2 2006.285.20:13:10.78#ibcon#about to read 3, iclass 37, count 2 2006.285.20:13:10.80#ibcon#read 3, iclass 37, count 2 2006.285.20:13:10.80#ibcon#about to read 4, iclass 37, count 2 2006.285.20:13:10.80#ibcon#read 4, iclass 37, count 2 2006.285.20:13:10.80#ibcon#about to read 5, iclass 37, count 2 2006.285.20:13:10.80#ibcon#read 5, iclass 37, count 2 2006.285.20:13:10.80#ibcon#about to read 6, iclass 37, count 2 2006.285.20:13:10.80#ibcon#read 6, iclass 37, count 2 2006.285.20:13:10.80#ibcon#end of sib2, iclass 37, count 2 2006.285.20:13:10.80#ibcon#*mode == 0, iclass 37, count 2 2006.285.20:13:10.80#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.20:13:10.80#ibcon#[27=AT01-04\r\n] 2006.285.20:13:10.80#ibcon#*before write, iclass 37, count 2 2006.285.20:13:10.80#ibcon#enter sib2, iclass 37, count 2 2006.285.20:13:10.80#ibcon#flushed, iclass 37, count 2 2006.285.20:13:10.80#ibcon#about to write, iclass 37, count 2 2006.285.20:13:10.80#ibcon#wrote, iclass 37, count 2 2006.285.20:13:10.80#ibcon#about to read 3, iclass 37, count 2 2006.285.20:13:10.83#ibcon#read 3, iclass 37, count 2 2006.285.20:13:10.83#ibcon#about to read 4, iclass 37, count 2 2006.285.20:13:10.83#ibcon#read 4, iclass 37, count 2 2006.285.20:13:10.83#ibcon#about to read 5, iclass 37, count 2 2006.285.20:13:10.83#ibcon#read 5, iclass 37, count 2 2006.285.20:13:10.83#ibcon#about to read 6, iclass 37, count 2 2006.285.20:13:10.83#ibcon#read 6, iclass 37, count 2 2006.285.20:13:10.83#ibcon#end of sib2, iclass 37, count 2 2006.285.20:13:10.83#ibcon#*after write, iclass 37, count 2 2006.285.20:13:10.83#ibcon#*before return 0, iclass 37, count 2 2006.285.20:13:10.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:13:10.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:13:10.83#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.20:13:10.83#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:10.83#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:13:10.95#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:13:10.95#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:13:10.95#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:13:10.95#ibcon#first serial, iclass 37, count 0 2006.285.20:13:10.95#ibcon#enter sib2, iclass 37, count 0 2006.285.20:13:10.95#ibcon#flushed, iclass 37, count 0 2006.285.20:13:10.95#ibcon#about to write, iclass 37, count 0 2006.285.20:13:10.95#ibcon#wrote, iclass 37, count 0 2006.285.20:13:10.95#ibcon#about to read 3, iclass 37, count 0 2006.285.20:13:10.97#ibcon#read 3, iclass 37, count 0 2006.285.20:13:10.97#ibcon#about to read 4, iclass 37, count 0 2006.285.20:13:10.97#ibcon#read 4, iclass 37, count 0 2006.285.20:13:10.97#ibcon#about to read 5, iclass 37, count 0 2006.285.20:13:10.97#ibcon#read 5, iclass 37, count 0 2006.285.20:13:10.97#ibcon#about to read 6, iclass 37, count 0 2006.285.20:13:10.97#ibcon#read 6, iclass 37, count 0 2006.285.20:13:10.97#ibcon#end of sib2, iclass 37, count 0 2006.285.20:13:10.97#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:13:10.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:13:10.97#ibcon#[27=USB\r\n] 2006.285.20:13:10.97#ibcon#*before write, iclass 37, count 0 2006.285.20:13:10.97#ibcon#enter sib2, iclass 37, count 0 2006.285.20:13:10.97#ibcon#flushed, iclass 37, count 0 2006.285.20:13:10.97#ibcon#about to write, iclass 37, count 0 2006.285.20:13:10.97#ibcon#wrote, iclass 37, count 0 2006.285.20:13:10.97#ibcon#about to read 3, iclass 37, count 0 2006.285.20:13:11.00#ibcon#read 3, iclass 37, count 0 2006.285.20:13:11.00#ibcon#about to read 4, iclass 37, count 0 2006.285.20:13:11.00#ibcon#read 4, iclass 37, count 0 2006.285.20:13:11.00#ibcon#about to read 5, iclass 37, count 0 2006.285.20:13:11.00#ibcon#read 5, iclass 37, count 0 2006.285.20:13:11.00#ibcon#about to read 6, iclass 37, count 0 2006.285.20:13:11.00#ibcon#read 6, iclass 37, count 0 2006.285.20:13:11.00#ibcon#end of sib2, iclass 37, count 0 2006.285.20:13:11.00#ibcon#*after write, iclass 37, count 0 2006.285.20:13:11.00#ibcon#*before return 0, iclass 37, count 0 2006.285.20:13:11.00#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:13:11.00#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:13:11.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:13:11.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:13:11.00$vck44/vblo=2,634.99 2006.285.20:13:11.00#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.20:13:11.00#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.20:13:11.00#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:11.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:13:11.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:13:11.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:13:11.00#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:13:11.00#ibcon#first serial, iclass 39, count 0 2006.285.20:13:11.00#ibcon#enter sib2, iclass 39, count 0 2006.285.20:13:11.00#ibcon#flushed, iclass 39, count 0 2006.285.20:13:11.00#ibcon#about to write, iclass 39, count 0 2006.285.20:13:11.00#ibcon#wrote, iclass 39, count 0 2006.285.20:13:11.00#ibcon#about to read 3, iclass 39, count 0 2006.285.20:13:11.02#ibcon#read 3, iclass 39, count 0 2006.285.20:13:11.07#ibcon#about to read 4, iclass 39, count 0 2006.285.20:13:11.07#ibcon#read 4, iclass 39, count 0 2006.285.20:13:11.07#ibcon#about to read 5, iclass 39, count 0 2006.285.20:13:11.07#ibcon#read 5, iclass 39, count 0 2006.285.20:13:11.07#ibcon#about to read 6, iclass 39, count 0 2006.285.20:13:11.07#ibcon#read 6, iclass 39, count 0 2006.285.20:13:11.07#ibcon#end of sib2, iclass 39, count 0 2006.285.20:13:11.07#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:13:11.07#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:13:11.07#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.20:13:11.07#ibcon#*before write, iclass 39, count 0 2006.285.20:13:11.07#ibcon#enter sib2, iclass 39, count 0 2006.285.20:13:11.07#ibcon#flushed, iclass 39, count 0 2006.285.20:13:11.07#ibcon#about to write, iclass 39, count 0 2006.285.20:13:11.07#ibcon#wrote, iclass 39, count 0 2006.285.20:13:11.07#ibcon#about to read 3, iclass 39, count 0 2006.285.20:13:11.11#ibcon#read 3, iclass 39, count 0 2006.285.20:13:11.11#ibcon#about to read 4, iclass 39, count 0 2006.285.20:13:11.11#ibcon#read 4, iclass 39, count 0 2006.285.20:13:11.11#ibcon#about to read 5, iclass 39, count 0 2006.285.20:13:11.11#ibcon#read 5, iclass 39, count 0 2006.285.20:13:11.11#ibcon#about to read 6, iclass 39, count 0 2006.285.20:13:11.11#ibcon#read 6, iclass 39, count 0 2006.285.20:13:11.11#ibcon#end of sib2, iclass 39, count 0 2006.285.20:13:11.11#ibcon#*after write, iclass 39, count 0 2006.285.20:13:11.11#ibcon#*before return 0, iclass 39, count 0 2006.285.20:13:11.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:13:11.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:13:11.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:13:11.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:13:11.11$vck44/vb=2,5 2006.285.20:13:11.11#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.20:13:11.11#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.20:13:11.11#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:11.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:13:11.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:13:11.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:13:11.11#ibcon#enter wrdev, iclass 3, count 2 2006.285.20:13:11.11#ibcon#first serial, iclass 3, count 2 2006.285.20:13:11.11#ibcon#enter sib2, iclass 3, count 2 2006.285.20:13:11.11#ibcon#flushed, iclass 3, count 2 2006.285.20:13:11.11#ibcon#about to write, iclass 3, count 2 2006.285.20:13:11.11#ibcon#wrote, iclass 3, count 2 2006.285.20:13:11.11#ibcon#about to read 3, iclass 3, count 2 2006.285.20:13:11.13#ibcon#read 3, iclass 3, count 2 2006.285.20:13:11.13#ibcon#about to read 4, iclass 3, count 2 2006.285.20:13:11.13#ibcon#read 4, iclass 3, count 2 2006.285.20:13:11.13#ibcon#about to read 5, iclass 3, count 2 2006.285.20:13:11.13#ibcon#read 5, iclass 3, count 2 2006.285.20:13:11.13#ibcon#about to read 6, iclass 3, count 2 2006.285.20:13:11.13#ibcon#read 6, iclass 3, count 2 2006.285.20:13:11.13#ibcon#end of sib2, iclass 3, count 2 2006.285.20:13:11.13#ibcon#*mode == 0, iclass 3, count 2 2006.285.20:13:11.13#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.20:13:11.13#ibcon#[27=AT02-05\r\n] 2006.285.20:13:11.13#ibcon#*before write, iclass 3, count 2 2006.285.20:13:11.13#ibcon#enter sib2, iclass 3, count 2 2006.285.20:13:11.13#ibcon#flushed, iclass 3, count 2 2006.285.20:13:11.13#ibcon#about to write, iclass 3, count 2 2006.285.20:13:11.13#ibcon#wrote, iclass 3, count 2 2006.285.20:13:11.13#ibcon#about to read 3, iclass 3, count 2 2006.285.20:13:11.16#ibcon#read 3, iclass 3, count 2 2006.285.20:13:11.16#ibcon#about to read 4, iclass 3, count 2 2006.285.20:13:11.16#ibcon#read 4, iclass 3, count 2 2006.285.20:13:11.16#ibcon#about to read 5, iclass 3, count 2 2006.285.20:13:11.16#ibcon#read 5, iclass 3, count 2 2006.285.20:13:11.16#ibcon#about to read 6, iclass 3, count 2 2006.285.20:13:11.16#ibcon#read 6, iclass 3, count 2 2006.285.20:13:11.16#ibcon#end of sib2, iclass 3, count 2 2006.285.20:13:11.16#ibcon#*after write, iclass 3, count 2 2006.285.20:13:11.16#ibcon#*before return 0, iclass 3, count 2 2006.285.20:13:11.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:13:11.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:13:11.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.20:13:11.16#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:11.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:13:11.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:13:11.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:13:11.28#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:13:11.28#ibcon#first serial, iclass 3, count 0 2006.285.20:13:11.28#ibcon#enter sib2, iclass 3, count 0 2006.285.20:13:11.28#ibcon#flushed, iclass 3, count 0 2006.285.20:13:11.28#ibcon#about to write, iclass 3, count 0 2006.285.20:13:11.28#ibcon#wrote, iclass 3, count 0 2006.285.20:13:11.28#ibcon#about to read 3, iclass 3, count 0 2006.285.20:13:11.30#ibcon#read 3, iclass 3, count 0 2006.285.20:13:11.30#ibcon#about to read 4, iclass 3, count 0 2006.285.20:13:11.30#ibcon#read 4, iclass 3, count 0 2006.285.20:13:11.30#ibcon#about to read 5, iclass 3, count 0 2006.285.20:13:11.30#ibcon#read 5, iclass 3, count 0 2006.285.20:13:11.30#ibcon#about to read 6, iclass 3, count 0 2006.285.20:13:11.30#ibcon#read 6, iclass 3, count 0 2006.285.20:13:11.30#ibcon#end of sib2, iclass 3, count 0 2006.285.20:13:11.30#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:13:11.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:13:11.30#ibcon#[27=USB\r\n] 2006.285.20:13:11.30#ibcon#*before write, iclass 3, count 0 2006.285.20:13:11.30#ibcon#enter sib2, iclass 3, count 0 2006.285.20:13:11.30#ibcon#flushed, iclass 3, count 0 2006.285.20:13:11.30#ibcon#about to write, iclass 3, count 0 2006.285.20:13:11.30#ibcon#wrote, iclass 3, count 0 2006.285.20:13:11.30#ibcon#about to read 3, iclass 3, count 0 2006.285.20:13:11.33#ibcon#read 3, iclass 3, count 0 2006.285.20:13:11.33#ibcon#about to read 4, iclass 3, count 0 2006.285.20:13:11.33#ibcon#read 4, iclass 3, count 0 2006.285.20:13:11.33#ibcon#about to read 5, iclass 3, count 0 2006.285.20:13:11.33#ibcon#read 5, iclass 3, count 0 2006.285.20:13:11.33#ibcon#about to read 6, iclass 3, count 0 2006.285.20:13:11.33#ibcon#read 6, iclass 3, count 0 2006.285.20:13:11.33#ibcon#end of sib2, iclass 3, count 0 2006.285.20:13:11.33#ibcon#*after write, iclass 3, count 0 2006.285.20:13:11.33#ibcon#*before return 0, iclass 3, count 0 2006.285.20:13:11.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:13:11.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:13:11.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:13:11.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:13:11.33$vck44/vblo=3,649.99 2006.285.20:13:11.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.20:13:11.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.20:13:11.33#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:11.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:13:11.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:13:11.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:13:11.33#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:13:11.33#ibcon#first serial, iclass 5, count 0 2006.285.20:13:11.33#ibcon#enter sib2, iclass 5, count 0 2006.285.20:13:11.33#ibcon#flushed, iclass 5, count 0 2006.285.20:13:11.33#ibcon#about to write, iclass 5, count 0 2006.285.20:13:11.33#ibcon#wrote, iclass 5, count 0 2006.285.20:13:11.33#ibcon#about to read 3, iclass 5, count 0 2006.285.20:13:11.35#ibcon#read 3, iclass 5, count 0 2006.285.20:13:11.35#ibcon#about to read 4, iclass 5, count 0 2006.285.20:13:11.35#ibcon#read 4, iclass 5, count 0 2006.285.20:13:11.35#ibcon#about to read 5, iclass 5, count 0 2006.285.20:13:11.35#ibcon#read 5, iclass 5, count 0 2006.285.20:13:11.35#ibcon#about to read 6, iclass 5, count 0 2006.285.20:13:11.35#ibcon#read 6, iclass 5, count 0 2006.285.20:13:11.35#ibcon#end of sib2, iclass 5, count 0 2006.285.20:13:11.35#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:13:11.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:13:11.35#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.20:13:11.35#ibcon#*before write, iclass 5, count 0 2006.285.20:13:11.35#ibcon#enter sib2, iclass 5, count 0 2006.285.20:13:11.35#ibcon#flushed, iclass 5, count 0 2006.285.20:13:11.35#ibcon#about to write, iclass 5, count 0 2006.285.20:13:11.35#ibcon#wrote, iclass 5, count 0 2006.285.20:13:11.35#ibcon#about to read 3, iclass 5, count 0 2006.285.20:13:11.39#ibcon#read 3, iclass 5, count 0 2006.285.20:13:11.39#ibcon#about to read 4, iclass 5, count 0 2006.285.20:13:11.39#ibcon#read 4, iclass 5, count 0 2006.285.20:13:11.39#ibcon#about to read 5, iclass 5, count 0 2006.285.20:13:11.39#ibcon#read 5, iclass 5, count 0 2006.285.20:13:11.39#ibcon#about to read 6, iclass 5, count 0 2006.285.20:13:11.39#ibcon#read 6, iclass 5, count 0 2006.285.20:13:11.39#ibcon#end of sib2, iclass 5, count 0 2006.285.20:13:11.39#ibcon#*after write, iclass 5, count 0 2006.285.20:13:11.39#ibcon#*before return 0, iclass 5, count 0 2006.285.20:13:11.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:13:11.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:13:11.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:13:11.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:13:11.39$vck44/vb=3,4 2006.285.20:13:11.39#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.20:13:11.39#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.20:13:11.39#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:11.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:13:11.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:13:11.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:13:11.45#ibcon#enter wrdev, iclass 7, count 2 2006.285.20:13:11.45#ibcon#first serial, iclass 7, count 2 2006.285.20:13:11.45#ibcon#enter sib2, iclass 7, count 2 2006.285.20:13:11.45#ibcon#flushed, iclass 7, count 2 2006.285.20:13:11.45#ibcon#about to write, iclass 7, count 2 2006.285.20:13:11.45#ibcon#wrote, iclass 7, count 2 2006.285.20:13:11.45#ibcon#about to read 3, iclass 7, count 2 2006.285.20:13:11.47#ibcon#read 3, iclass 7, count 2 2006.285.20:13:11.47#ibcon#about to read 4, iclass 7, count 2 2006.285.20:13:11.47#ibcon#read 4, iclass 7, count 2 2006.285.20:13:11.47#ibcon#about to read 5, iclass 7, count 2 2006.285.20:13:11.47#ibcon#read 5, iclass 7, count 2 2006.285.20:13:11.47#ibcon#about to read 6, iclass 7, count 2 2006.285.20:13:11.47#ibcon#read 6, iclass 7, count 2 2006.285.20:13:11.47#ibcon#end of sib2, iclass 7, count 2 2006.285.20:13:11.47#ibcon#*mode == 0, iclass 7, count 2 2006.285.20:13:11.47#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.20:13:11.47#ibcon#[27=AT03-04\r\n] 2006.285.20:13:11.47#ibcon#*before write, iclass 7, count 2 2006.285.20:13:11.47#ibcon#enter sib2, iclass 7, count 2 2006.285.20:13:11.47#ibcon#flushed, iclass 7, count 2 2006.285.20:13:11.47#ibcon#about to write, iclass 7, count 2 2006.285.20:13:11.47#ibcon#wrote, iclass 7, count 2 2006.285.20:13:11.47#ibcon#about to read 3, iclass 7, count 2 2006.285.20:13:11.50#ibcon#read 3, iclass 7, count 2 2006.285.20:13:11.50#ibcon#about to read 4, iclass 7, count 2 2006.285.20:13:11.50#ibcon#read 4, iclass 7, count 2 2006.285.20:13:11.50#ibcon#about to read 5, iclass 7, count 2 2006.285.20:13:11.50#ibcon#read 5, iclass 7, count 2 2006.285.20:13:11.50#ibcon#about to read 6, iclass 7, count 2 2006.285.20:13:11.50#ibcon#read 6, iclass 7, count 2 2006.285.20:13:11.50#ibcon#end of sib2, iclass 7, count 2 2006.285.20:13:11.50#ibcon#*after write, iclass 7, count 2 2006.285.20:13:11.50#ibcon#*before return 0, iclass 7, count 2 2006.285.20:13:11.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:13:11.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:13:11.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.20:13:11.50#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:11.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:13:11.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:13:11.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:13:11.62#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:13:11.62#ibcon#first serial, iclass 7, count 0 2006.285.20:13:11.62#ibcon#enter sib2, iclass 7, count 0 2006.285.20:13:11.62#ibcon#flushed, iclass 7, count 0 2006.285.20:13:11.62#ibcon#about to write, iclass 7, count 0 2006.285.20:13:11.62#ibcon#wrote, iclass 7, count 0 2006.285.20:13:11.62#ibcon#about to read 3, iclass 7, count 0 2006.285.20:13:11.64#ibcon#read 3, iclass 7, count 0 2006.285.20:13:11.64#ibcon#about to read 4, iclass 7, count 0 2006.285.20:13:11.64#ibcon#read 4, iclass 7, count 0 2006.285.20:13:11.64#ibcon#about to read 5, iclass 7, count 0 2006.285.20:13:11.64#ibcon#read 5, iclass 7, count 0 2006.285.20:13:11.64#ibcon#about to read 6, iclass 7, count 0 2006.285.20:13:11.64#ibcon#read 6, iclass 7, count 0 2006.285.20:13:11.64#ibcon#end of sib2, iclass 7, count 0 2006.285.20:13:11.64#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:13:11.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:13:11.64#ibcon#[27=USB\r\n] 2006.285.20:13:11.64#ibcon#*before write, iclass 7, count 0 2006.285.20:13:11.64#ibcon#enter sib2, iclass 7, count 0 2006.285.20:13:11.64#ibcon#flushed, iclass 7, count 0 2006.285.20:13:11.64#ibcon#about to write, iclass 7, count 0 2006.285.20:13:11.64#ibcon#wrote, iclass 7, count 0 2006.285.20:13:11.64#ibcon#about to read 3, iclass 7, count 0 2006.285.20:13:11.67#ibcon#read 3, iclass 7, count 0 2006.285.20:13:11.67#ibcon#about to read 4, iclass 7, count 0 2006.285.20:13:11.67#ibcon#read 4, iclass 7, count 0 2006.285.20:13:11.67#ibcon#about to read 5, iclass 7, count 0 2006.285.20:13:11.67#ibcon#read 5, iclass 7, count 0 2006.285.20:13:11.67#ibcon#about to read 6, iclass 7, count 0 2006.285.20:13:11.67#ibcon#read 6, iclass 7, count 0 2006.285.20:13:11.67#ibcon#end of sib2, iclass 7, count 0 2006.285.20:13:11.67#ibcon#*after write, iclass 7, count 0 2006.285.20:13:11.67#ibcon#*before return 0, iclass 7, count 0 2006.285.20:13:11.67#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:13:11.67#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:13:11.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:13:11.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:13:11.67$vck44/vblo=4,679.99 2006.285.20:13:11.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.20:13:11.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.20:13:11.67#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:11.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:13:11.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:13:11.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:13:11.67#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:13:11.67#ibcon#first serial, iclass 11, count 0 2006.285.20:13:11.67#ibcon#enter sib2, iclass 11, count 0 2006.285.20:13:11.67#ibcon#flushed, iclass 11, count 0 2006.285.20:13:11.67#ibcon#about to write, iclass 11, count 0 2006.285.20:13:11.67#ibcon#wrote, iclass 11, count 0 2006.285.20:13:11.67#ibcon#about to read 3, iclass 11, count 0 2006.285.20:13:11.69#ibcon#read 3, iclass 11, count 0 2006.285.20:13:11.69#ibcon#about to read 4, iclass 11, count 0 2006.285.20:13:11.69#ibcon#read 4, iclass 11, count 0 2006.285.20:13:11.69#ibcon#about to read 5, iclass 11, count 0 2006.285.20:13:11.69#ibcon#read 5, iclass 11, count 0 2006.285.20:13:11.69#ibcon#about to read 6, iclass 11, count 0 2006.285.20:13:11.69#ibcon#read 6, iclass 11, count 0 2006.285.20:13:11.69#ibcon#end of sib2, iclass 11, count 0 2006.285.20:13:11.69#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:13:11.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:13:11.69#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.20:13:11.69#ibcon#*before write, iclass 11, count 0 2006.285.20:13:11.69#ibcon#enter sib2, iclass 11, count 0 2006.285.20:13:11.69#ibcon#flushed, iclass 11, count 0 2006.285.20:13:11.69#ibcon#about to write, iclass 11, count 0 2006.285.20:13:11.69#ibcon#wrote, iclass 11, count 0 2006.285.20:13:11.69#ibcon#about to read 3, iclass 11, count 0 2006.285.20:13:11.73#ibcon#read 3, iclass 11, count 0 2006.285.20:13:11.73#ibcon#about to read 4, iclass 11, count 0 2006.285.20:13:11.73#ibcon#read 4, iclass 11, count 0 2006.285.20:13:11.73#ibcon#about to read 5, iclass 11, count 0 2006.285.20:13:11.73#ibcon#read 5, iclass 11, count 0 2006.285.20:13:11.73#ibcon#about to read 6, iclass 11, count 0 2006.285.20:13:11.73#ibcon#read 6, iclass 11, count 0 2006.285.20:13:11.73#ibcon#end of sib2, iclass 11, count 0 2006.285.20:13:11.73#ibcon#*after write, iclass 11, count 0 2006.285.20:13:11.73#ibcon#*before return 0, iclass 11, count 0 2006.285.20:13:11.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:13:11.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:13:11.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:13:11.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:13:11.73$vck44/vb=4,5 2006.285.20:13:11.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.20:13:11.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.20:13:11.73#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:11.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:13:11.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:13:11.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:13:11.79#ibcon#enter wrdev, iclass 13, count 2 2006.285.20:13:11.79#ibcon#first serial, iclass 13, count 2 2006.285.20:13:11.79#ibcon#enter sib2, iclass 13, count 2 2006.285.20:13:11.79#ibcon#flushed, iclass 13, count 2 2006.285.20:13:11.79#ibcon#about to write, iclass 13, count 2 2006.285.20:13:11.79#ibcon#wrote, iclass 13, count 2 2006.285.20:13:11.79#ibcon#about to read 3, iclass 13, count 2 2006.285.20:13:11.81#ibcon#read 3, iclass 13, count 2 2006.285.20:13:11.81#ibcon#about to read 4, iclass 13, count 2 2006.285.20:13:11.81#ibcon#read 4, iclass 13, count 2 2006.285.20:13:11.81#ibcon#about to read 5, iclass 13, count 2 2006.285.20:13:11.81#ibcon#read 5, iclass 13, count 2 2006.285.20:13:11.81#ibcon#about to read 6, iclass 13, count 2 2006.285.20:13:11.81#ibcon#read 6, iclass 13, count 2 2006.285.20:13:11.81#ibcon#end of sib2, iclass 13, count 2 2006.285.20:13:11.81#ibcon#*mode == 0, iclass 13, count 2 2006.285.20:13:11.81#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.20:13:11.81#ibcon#[27=AT04-05\r\n] 2006.285.20:13:11.81#ibcon#*before write, iclass 13, count 2 2006.285.20:13:11.81#ibcon#enter sib2, iclass 13, count 2 2006.285.20:13:11.81#ibcon#flushed, iclass 13, count 2 2006.285.20:13:11.81#ibcon#about to write, iclass 13, count 2 2006.285.20:13:11.81#ibcon#wrote, iclass 13, count 2 2006.285.20:13:11.81#ibcon#about to read 3, iclass 13, count 2 2006.285.20:13:11.84#abcon#<5=/09 0.5 1.2 14.531001015.2\r\n> 2006.285.20:13:11.84#ibcon#read 3, iclass 13, count 2 2006.285.20:13:11.84#ibcon#about to read 4, iclass 13, count 2 2006.285.20:13:11.84#ibcon#read 4, iclass 13, count 2 2006.285.20:13:11.84#ibcon#about to read 5, iclass 13, count 2 2006.285.20:13:11.84#ibcon#read 5, iclass 13, count 2 2006.285.20:13:11.84#ibcon#about to read 6, iclass 13, count 2 2006.285.20:13:11.84#ibcon#read 6, iclass 13, count 2 2006.285.20:13:11.84#ibcon#end of sib2, iclass 13, count 2 2006.285.20:13:11.84#ibcon#*after write, iclass 13, count 2 2006.285.20:13:11.84#ibcon#*before return 0, iclass 13, count 2 2006.285.20:13:11.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:13:11.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:13:11.84#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.20:13:11.84#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:11.84#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:13:11.86#abcon#{5=INTERFACE CLEAR} 2006.285.20:13:11.92#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:13:11.96#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:13:11.96#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:13:11.96#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:13:11.96#ibcon#first serial, iclass 13, count 0 2006.285.20:13:11.96#ibcon#enter sib2, iclass 13, count 0 2006.285.20:13:11.96#ibcon#flushed, iclass 13, count 0 2006.285.20:13:11.96#ibcon#about to write, iclass 13, count 0 2006.285.20:13:11.96#ibcon#wrote, iclass 13, count 0 2006.285.20:13:11.96#ibcon#about to read 3, iclass 13, count 0 2006.285.20:13:11.98#ibcon#read 3, iclass 13, count 0 2006.285.20:13:11.98#ibcon#about to read 4, iclass 13, count 0 2006.285.20:13:11.98#ibcon#read 4, iclass 13, count 0 2006.285.20:13:11.98#ibcon#about to read 5, iclass 13, count 0 2006.285.20:13:11.98#ibcon#read 5, iclass 13, count 0 2006.285.20:13:11.98#ibcon#about to read 6, iclass 13, count 0 2006.285.20:13:11.98#ibcon#read 6, iclass 13, count 0 2006.285.20:13:11.98#ibcon#end of sib2, iclass 13, count 0 2006.285.20:13:11.98#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:13:11.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:13:11.98#ibcon#[27=USB\r\n] 2006.285.20:13:11.98#ibcon#*before write, iclass 13, count 0 2006.285.20:13:11.98#ibcon#enter sib2, iclass 13, count 0 2006.285.20:13:11.98#ibcon#flushed, iclass 13, count 0 2006.285.20:13:11.98#ibcon#about to write, iclass 13, count 0 2006.285.20:13:11.98#ibcon#wrote, iclass 13, count 0 2006.285.20:13:11.98#ibcon#about to read 3, iclass 13, count 0 2006.285.20:13:12.01#ibcon#read 3, iclass 13, count 0 2006.285.20:13:12.01#ibcon#about to read 4, iclass 13, count 0 2006.285.20:13:12.01#ibcon#read 4, iclass 13, count 0 2006.285.20:13:12.01#ibcon#about to read 5, iclass 13, count 0 2006.285.20:13:12.01#ibcon#read 5, iclass 13, count 0 2006.285.20:13:12.01#ibcon#about to read 6, iclass 13, count 0 2006.285.20:13:12.01#ibcon#read 6, iclass 13, count 0 2006.285.20:13:12.01#ibcon#end of sib2, iclass 13, count 0 2006.285.20:13:12.01#ibcon#*after write, iclass 13, count 0 2006.285.20:13:12.01#ibcon#*before return 0, iclass 13, count 0 2006.285.20:13:12.01#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:13:12.01#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:13:12.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:13:12.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:13:12.01$vck44/vblo=5,709.99 2006.285.20:13:12.01#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.20:13:12.07#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.20:13:12.07#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:12.07#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:13:12.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:13:12.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:13:12.07#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:13:12.07#ibcon#first serial, iclass 19, count 0 2006.285.20:13:12.07#ibcon#enter sib2, iclass 19, count 0 2006.285.20:13:12.07#ibcon#flushed, iclass 19, count 0 2006.285.20:13:12.07#ibcon#about to write, iclass 19, count 0 2006.285.20:13:12.07#ibcon#wrote, iclass 19, count 0 2006.285.20:13:12.07#ibcon#about to read 3, iclass 19, count 0 2006.285.20:13:12.09#ibcon#read 3, iclass 19, count 0 2006.285.20:13:12.09#ibcon#about to read 4, iclass 19, count 0 2006.285.20:13:12.09#ibcon#read 4, iclass 19, count 0 2006.285.20:13:12.09#ibcon#about to read 5, iclass 19, count 0 2006.285.20:13:12.09#ibcon#read 5, iclass 19, count 0 2006.285.20:13:12.09#ibcon#about to read 6, iclass 19, count 0 2006.285.20:13:12.09#ibcon#read 6, iclass 19, count 0 2006.285.20:13:12.09#ibcon#end of sib2, iclass 19, count 0 2006.285.20:13:12.09#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:13:12.09#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:13:12.09#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.20:13:12.09#ibcon#*before write, iclass 19, count 0 2006.285.20:13:12.09#ibcon#enter sib2, iclass 19, count 0 2006.285.20:13:12.09#ibcon#flushed, iclass 19, count 0 2006.285.20:13:12.09#ibcon#about to write, iclass 19, count 0 2006.285.20:13:12.09#ibcon#wrote, iclass 19, count 0 2006.285.20:13:12.09#ibcon#about to read 3, iclass 19, count 0 2006.285.20:13:12.13#ibcon#read 3, iclass 19, count 0 2006.285.20:13:12.13#ibcon#about to read 4, iclass 19, count 0 2006.285.20:13:12.13#ibcon#read 4, iclass 19, count 0 2006.285.20:13:12.13#ibcon#about to read 5, iclass 19, count 0 2006.285.20:13:12.13#ibcon#read 5, iclass 19, count 0 2006.285.20:13:12.13#ibcon#about to read 6, iclass 19, count 0 2006.285.20:13:12.13#ibcon#read 6, iclass 19, count 0 2006.285.20:13:12.13#ibcon#end of sib2, iclass 19, count 0 2006.285.20:13:12.13#ibcon#*after write, iclass 19, count 0 2006.285.20:13:12.13#ibcon#*before return 0, iclass 19, count 0 2006.285.20:13:12.13#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:13:12.13#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:13:12.13#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:13:12.13#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:13:12.13$vck44/vb=5,4 2006.285.20:13:12.13#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.20:13:12.13#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.20:13:12.13#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:12.13#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:13:12.13#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:13:12.13#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:13:12.13#ibcon#enter wrdev, iclass 21, count 2 2006.285.20:13:12.13#ibcon#first serial, iclass 21, count 2 2006.285.20:13:12.13#ibcon#enter sib2, iclass 21, count 2 2006.285.20:13:12.13#ibcon#flushed, iclass 21, count 2 2006.285.20:13:12.13#ibcon#about to write, iclass 21, count 2 2006.285.20:13:12.13#ibcon#wrote, iclass 21, count 2 2006.285.20:13:12.13#ibcon#about to read 3, iclass 21, count 2 2006.285.20:13:12.15#ibcon#read 3, iclass 21, count 2 2006.285.20:13:12.15#ibcon#about to read 4, iclass 21, count 2 2006.285.20:13:12.15#ibcon#read 4, iclass 21, count 2 2006.285.20:13:12.15#ibcon#about to read 5, iclass 21, count 2 2006.285.20:13:12.15#ibcon#read 5, iclass 21, count 2 2006.285.20:13:12.15#ibcon#about to read 6, iclass 21, count 2 2006.285.20:13:12.15#ibcon#read 6, iclass 21, count 2 2006.285.20:13:12.15#ibcon#end of sib2, iclass 21, count 2 2006.285.20:13:12.15#ibcon#*mode == 0, iclass 21, count 2 2006.285.20:13:12.15#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.20:13:12.15#ibcon#[27=AT05-04\r\n] 2006.285.20:13:12.15#ibcon#*before write, iclass 21, count 2 2006.285.20:13:12.15#ibcon#enter sib2, iclass 21, count 2 2006.285.20:13:12.15#ibcon#flushed, iclass 21, count 2 2006.285.20:13:12.15#ibcon#about to write, iclass 21, count 2 2006.285.20:13:12.15#ibcon#wrote, iclass 21, count 2 2006.285.20:13:12.15#ibcon#about to read 3, iclass 21, count 2 2006.285.20:13:12.18#ibcon#read 3, iclass 21, count 2 2006.285.20:13:12.18#ibcon#about to read 4, iclass 21, count 2 2006.285.20:13:12.18#ibcon#read 4, iclass 21, count 2 2006.285.20:13:12.18#ibcon#about to read 5, iclass 21, count 2 2006.285.20:13:12.18#ibcon#read 5, iclass 21, count 2 2006.285.20:13:12.18#ibcon#about to read 6, iclass 21, count 2 2006.285.20:13:12.18#ibcon#read 6, iclass 21, count 2 2006.285.20:13:12.18#ibcon#end of sib2, iclass 21, count 2 2006.285.20:13:12.18#ibcon#*after write, iclass 21, count 2 2006.285.20:13:12.18#ibcon#*before return 0, iclass 21, count 2 2006.285.20:13:12.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:13:12.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:13:12.18#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.20:13:12.18#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:12.18#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:13:12.30#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:13:12.30#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:13:12.30#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:13:12.30#ibcon#first serial, iclass 21, count 0 2006.285.20:13:12.30#ibcon#enter sib2, iclass 21, count 0 2006.285.20:13:12.30#ibcon#flushed, iclass 21, count 0 2006.285.20:13:12.30#ibcon#about to write, iclass 21, count 0 2006.285.20:13:12.30#ibcon#wrote, iclass 21, count 0 2006.285.20:13:12.30#ibcon#about to read 3, iclass 21, count 0 2006.285.20:13:12.32#ibcon#read 3, iclass 21, count 0 2006.285.20:13:12.32#ibcon#about to read 4, iclass 21, count 0 2006.285.20:13:12.32#ibcon#read 4, iclass 21, count 0 2006.285.20:13:12.32#ibcon#about to read 5, iclass 21, count 0 2006.285.20:13:12.32#ibcon#read 5, iclass 21, count 0 2006.285.20:13:12.32#ibcon#about to read 6, iclass 21, count 0 2006.285.20:13:12.32#ibcon#read 6, iclass 21, count 0 2006.285.20:13:12.32#ibcon#end of sib2, iclass 21, count 0 2006.285.20:13:12.32#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:13:12.32#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:13:12.32#ibcon#[27=USB\r\n] 2006.285.20:13:12.32#ibcon#*before write, iclass 21, count 0 2006.285.20:13:12.32#ibcon#enter sib2, iclass 21, count 0 2006.285.20:13:12.32#ibcon#flushed, iclass 21, count 0 2006.285.20:13:12.32#ibcon#about to write, iclass 21, count 0 2006.285.20:13:12.32#ibcon#wrote, iclass 21, count 0 2006.285.20:13:12.32#ibcon#about to read 3, iclass 21, count 0 2006.285.20:13:12.35#ibcon#read 3, iclass 21, count 0 2006.285.20:13:12.35#ibcon#about to read 4, iclass 21, count 0 2006.285.20:13:12.35#ibcon#read 4, iclass 21, count 0 2006.285.20:13:12.35#ibcon#about to read 5, iclass 21, count 0 2006.285.20:13:12.35#ibcon#read 5, iclass 21, count 0 2006.285.20:13:12.35#ibcon#about to read 6, iclass 21, count 0 2006.285.20:13:12.35#ibcon#read 6, iclass 21, count 0 2006.285.20:13:12.35#ibcon#end of sib2, iclass 21, count 0 2006.285.20:13:12.35#ibcon#*after write, iclass 21, count 0 2006.285.20:13:12.35#ibcon#*before return 0, iclass 21, count 0 2006.285.20:13:12.35#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:13:12.35#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:13:12.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:13:12.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:13:12.35$vck44/vblo=6,719.99 2006.285.20:13:12.35#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.20:13:12.35#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.20:13:12.35#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:12.35#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:13:12.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:13:12.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:13:12.35#ibcon#enter wrdev, iclass 23, count 0 2006.285.20:13:12.35#ibcon#first serial, iclass 23, count 0 2006.285.20:13:12.35#ibcon#enter sib2, iclass 23, count 0 2006.285.20:13:12.35#ibcon#flushed, iclass 23, count 0 2006.285.20:13:12.35#ibcon#about to write, iclass 23, count 0 2006.285.20:13:12.35#ibcon#wrote, iclass 23, count 0 2006.285.20:13:12.35#ibcon#about to read 3, iclass 23, count 0 2006.285.20:13:12.37#ibcon#read 3, iclass 23, count 0 2006.285.20:13:12.37#ibcon#about to read 4, iclass 23, count 0 2006.285.20:13:12.37#ibcon#read 4, iclass 23, count 0 2006.285.20:13:12.37#ibcon#about to read 5, iclass 23, count 0 2006.285.20:13:12.37#ibcon#read 5, iclass 23, count 0 2006.285.20:13:12.37#ibcon#about to read 6, iclass 23, count 0 2006.285.20:13:12.37#ibcon#read 6, iclass 23, count 0 2006.285.20:13:12.37#ibcon#end of sib2, iclass 23, count 0 2006.285.20:13:12.37#ibcon#*mode == 0, iclass 23, count 0 2006.285.20:13:12.37#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.20:13:12.37#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.20:13:12.37#ibcon#*before write, iclass 23, count 0 2006.285.20:13:12.37#ibcon#enter sib2, iclass 23, count 0 2006.285.20:13:12.37#ibcon#flushed, iclass 23, count 0 2006.285.20:13:12.37#ibcon#about to write, iclass 23, count 0 2006.285.20:13:12.37#ibcon#wrote, iclass 23, count 0 2006.285.20:13:12.37#ibcon#about to read 3, iclass 23, count 0 2006.285.20:13:12.41#ibcon#read 3, iclass 23, count 0 2006.285.20:13:12.41#ibcon#about to read 4, iclass 23, count 0 2006.285.20:13:12.41#ibcon#read 4, iclass 23, count 0 2006.285.20:13:12.41#ibcon#about to read 5, iclass 23, count 0 2006.285.20:13:12.41#ibcon#read 5, iclass 23, count 0 2006.285.20:13:12.41#ibcon#about to read 6, iclass 23, count 0 2006.285.20:13:12.41#ibcon#read 6, iclass 23, count 0 2006.285.20:13:12.41#ibcon#end of sib2, iclass 23, count 0 2006.285.20:13:12.41#ibcon#*after write, iclass 23, count 0 2006.285.20:13:12.41#ibcon#*before return 0, iclass 23, count 0 2006.285.20:13:12.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:13:12.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:13:12.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.20:13:12.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.20:13:12.41$vck44/vb=6,3 2006.285.20:13:12.41#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.20:13:12.41#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.20:13:12.41#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:12.41#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:13:12.47#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:13:12.47#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:13:12.47#ibcon#enter wrdev, iclass 25, count 2 2006.285.20:13:12.47#ibcon#first serial, iclass 25, count 2 2006.285.20:13:12.47#ibcon#enter sib2, iclass 25, count 2 2006.285.20:13:12.47#ibcon#flushed, iclass 25, count 2 2006.285.20:13:12.47#ibcon#about to write, iclass 25, count 2 2006.285.20:13:12.47#ibcon#wrote, iclass 25, count 2 2006.285.20:13:12.47#ibcon#about to read 3, iclass 25, count 2 2006.285.20:13:12.49#ibcon#read 3, iclass 25, count 2 2006.285.20:13:12.49#ibcon#about to read 4, iclass 25, count 2 2006.285.20:13:12.49#ibcon#read 4, iclass 25, count 2 2006.285.20:13:12.49#ibcon#about to read 5, iclass 25, count 2 2006.285.20:13:12.49#ibcon#read 5, iclass 25, count 2 2006.285.20:13:12.49#ibcon#about to read 6, iclass 25, count 2 2006.285.20:13:12.49#ibcon#read 6, iclass 25, count 2 2006.285.20:13:12.49#ibcon#end of sib2, iclass 25, count 2 2006.285.20:13:12.49#ibcon#*mode == 0, iclass 25, count 2 2006.285.20:13:12.49#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.20:13:12.49#ibcon#[27=AT06-03\r\n] 2006.285.20:13:12.49#ibcon#*before write, iclass 25, count 2 2006.285.20:13:12.49#ibcon#enter sib2, iclass 25, count 2 2006.285.20:13:12.49#ibcon#flushed, iclass 25, count 2 2006.285.20:13:12.49#ibcon#about to write, iclass 25, count 2 2006.285.20:13:12.49#ibcon#wrote, iclass 25, count 2 2006.285.20:13:12.49#ibcon#about to read 3, iclass 25, count 2 2006.285.20:13:12.52#ibcon#read 3, iclass 25, count 2 2006.285.20:13:12.52#ibcon#about to read 4, iclass 25, count 2 2006.285.20:13:12.52#ibcon#read 4, iclass 25, count 2 2006.285.20:13:12.52#ibcon#about to read 5, iclass 25, count 2 2006.285.20:13:12.52#ibcon#read 5, iclass 25, count 2 2006.285.20:13:12.52#ibcon#about to read 6, iclass 25, count 2 2006.285.20:13:12.52#ibcon#read 6, iclass 25, count 2 2006.285.20:13:12.52#ibcon#end of sib2, iclass 25, count 2 2006.285.20:13:12.52#ibcon#*after write, iclass 25, count 2 2006.285.20:13:12.52#ibcon#*before return 0, iclass 25, count 2 2006.285.20:13:12.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:13:12.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:13:12.52#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.20:13:12.52#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:12.52#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:13:12.64#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:13:12.64#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:13:12.64#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:13:12.64#ibcon#first serial, iclass 25, count 0 2006.285.20:13:12.64#ibcon#enter sib2, iclass 25, count 0 2006.285.20:13:12.64#ibcon#flushed, iclass 25, count 0 2006.285.20:13:12.64#ibcon#about to write, iclass 25, count 0 2006.285.20:13:12.64#ibcon#wrote, iclass 25, count 0 2006.285.20:13:12.64#ibcon#about to read 3, iclass 25, count 0 2006.285.20:13:12.66#ibcon#read 3, iclass 25, count 0 2006.285.20:13:12.66#ibcon#about to read 4, iclass 25, count 0 2006.285.20:13:12.66#ibcon#read 4, iclass 25, count 0 2006.285.20:13:12.66#ibcon#about to read 5, iclass 25, count 0 2006.285.20:13:12.66#ibcon#read 5, iclass 25, count 0 2006.285.20:13:12.66#ibcon#about to read 6, iclass 25, count 0 2006.285.20:13:12.66#ibcon#read 6, iclass 25, count 0 2006.285.20:13:12.66#ibcon#end of sib2, iclass 25, count 0 2006.285.20:13:12.66#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:13:12.66#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:13:12.66#ibcon#[27=USB\r\n] 2006.285.20:13:12.66#ibcon#*before write, iclass 25, count 0 2006.285.20:13:12.66#ibcon#enter sib2, iclass 25, count 0 2006.285.20:13:12.66#ibcon#flushed, iclass 25, count 0 2006.285.20:13:12.66#ibcon#about to write, iclass 25, count 0 2006.285.20:13:12.66#ibcon#wrote, iclass 25, count 0 2006.285.20:13:12.66#ibcon#about to read 3, iclass 25, count 0 2006.285.20:13:12.69#ibcon#read 3, iclass 25, count 0 2006.285.20:13:12.69#ibcon#about to read 4, iclass 25, count 0 2006.285.20:13:12.69#ibcon#read 4, iclass 25, count 0 2006.285.20:13:12.69#ibcon#about to read 5, iclass 25, count 0 2006.285.20:13:12.69#ibcon#read 5, iclass 25, count 0 2006.285.20:13:12.69#ibcon#about to read 6, iclass 25, count 0 2006.285.20:13:12.69#ibcon#read 6, iclass 25, count 0 2006.285.20:13:12.69#ibcon#end of sib2, iclass 25, count 0 2006.285.20:13:12.69#ibcon#*after write, iclass 25, count 0 2006.285.20:13:12.69#ibcon#*before return 0, iclass 25, count 0 2006.285.20:13:12.69#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:13:12.69#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:13:12.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:13:12.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:13:12.69$vck44/vblo=7,734.99 2006.285.20:13:12.69#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.20:13:12.69#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.20:13:12.69#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:12.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:13:12.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:13:12.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:13:12.69#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:13:12.69#ibcon#first serial, iclass 27, count 0 2006.285.20:13:12.69#ibcon#enter sib2, iclass 27, count 0 2006.285.20:13:12.69#ibcon#flushed, iclass 27, count 0 2006.285.20:13:12.69#ibcon#about to write, iclass 27, count 0 2006.285.20:13:12.69#ibcon#wrote, iclass 27, count 0 2006.285.20:13:12.69#ibcon#about to read 3, iclass 27, count 0 2006.285.20:13:12.71#ibcon#read 3, iclass 27, count 0 2006.285.20:13:12.71#ibcon#about to read 4, iclass 27, count 0 2006.285.20:13:12.71#ibcon#read 4, iclass 27, count 0 2006.285.20:13:12.71#ibcon#about to read 5, iclass 27, count 0 2006.285.20:13:12.71#ibcon#read 5, iclass 27, count 0 2006.285.20:13:12.71#ibcon#about to read 6, iclass 27, count 0 2006.285.20:13:12.71#ibcon#read 6, iclass 27, count 0 2006.285.20:13:12.71#ibcon#end of sib2, iclass 27, count 0 2006.285.20:13:12.71#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:13:12.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:13:12.71#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.20:13:12.71#ibcon#*before write, iclass 27, count 0 2006.285.20:13:12.71#ibcon#enter sib2, iclass 27, count 0 2006.285.20:13:12.71#ibcon#flushed, iclass 27, count 0 2006.285.20:13:12.71#ibcon#about to write, iclass 27, count 0 2006.285.20:13:12.71#ibcon#wrote, iclass 27, count 0 2006.285.20:13:12.71#ibcon#about to read 3, iclass 27, count 0 2006.285.20:13:12.75#ibcon#read 3, iclass 27, count 0 2006.285.20:13:12.75#ibcon#about to read 4, iclass 27, count 0 2006.285.20:13:12.75#ibcon#read 4, iclass 27, count 0 2006.285.20:13:12.75#ibcon#about to read 5, iclass 27, count 0 2006.285.20:13:12.75#ibcon#read 5, iclass 27, count 0 2006.285.20:13:12.75#ibcon#about to read 6, iclass 27, count 0 2006.285.20:13:12.75#ibcon#read 6, iclass 27, count 0 2006.285.20:13:12.75#ibcon#end of sib2, iclass 27, count 0 2006.285.20:13:12.75#ibcon#*after write, iclass 27, count 0 2006.285.20:13:12.75#ibcon#*before return 0, iclass 27, count 0 2006.285.20:13:12.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:13:12.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:13:12.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:13:12.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:13:12.75$vck44/vb=7,4 2006.285.20:13:12.75#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.20:13:12.75#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.20:13:12.75#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:12.75#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:13:12.81#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:13:12.81#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:13:12.81#ibcon#enter wrdev, iclass 29, count 2 2006.285.20:13:12.81#ibcon#first serial, iclass 29, count 2 2006.285.20:13:12.81#ibcon#enter sib2, iclass 29, count 2 2006.285.20:13:12.81#ibcon#flushed, iclass 29, count 2 2006.285.20:13:12.81#ibcon#about to write, iclass 29, count 2 2006.285.20:13:12.81#ibcon#wrote, iclass 29, count 2 2006.285.20:13:12.81#ibcon#about to read 3, iclass 29, count 2 2006.285.20:13:12.83#ibcon#read 3, iclass 29, count 2 2006.285.20:13:12.83#ibcon#about to read 4, iclass 29, count 2 2006.285.20:13:12.83#ibcon#read 4, iclass 29, count 2 2006.285.20:13:12.83#ibcon#about to read 5, iclass 29, count 2 2006.285.20:13:12.83#ibcon#read 5, iclass 29, count 2 2006.285.20:13:12.83#ibcon#about to read 6, iclass 29, count 2 2006.285.20:13:12.83#ibcon#read 6, iclass 29, count 2 2006.285.20:13:12.83#ibcon#end of sib2, iclass 29, count 2 2006.285.20:13:12.83#ibcon#*mode == 0, iclass 29, count 2 2006.285.20:13:12.83#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.20:13:12.83#ibcon#[27=AT07-04\r\n] 2006.285.20:13:12.83#ibcon#*before write, iclass 29, count 2 2006.285.20:13:12.83#ibcon#enter sib2, iclass 29, count 2 2006.285.20:13:12.83#ibcon#flushed, iclass 29, count 2 2006.285.20:13:12.83#ibcon#about to write, iclass 29, count 2 2006.285.20:13:12.83#ibcon#wrote, iclass 29, count 2 2006.285.20:13:12.83#ibcon#about to read 3, iclass 29, count 2 2006.285.20:13:12.86#ibcon#read 3, iclass 29, count 2 2006.285.20:13:12.86#ibcon#about to read 4, iclass 29, count 2 2006.285.20:13:12.86#ibcon#read 4, iclass 29, count 2 2006.285.20:13:12.86#ibcon#about to read 5, iclass 29, count 2 2006.285.20:13:12.86#ibcon#read 5, iclass 29, count 2 2006.285.20:13:12.86#ibcon#about to read 6, iclass 29, count 2 2006.285.20:13:12.86#ibcon#read 6, iclass 29, count 2 2006.285.20:13:12.86#ibcon#end of sib2, iclass 29, count 2 2006.285.20:13:12.86#ibcon#*after write, iclass 29, count 2 2006.285.20:13:12.86#ibcon#*before return 0, iclass 29, count 2 2006.285.20:13:12.86#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:13:12.86#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:13:12.86#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.20:13:12.86#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:12.86#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:13:12.98#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:13:12.98#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:13:12.98#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:13:12.98#ibcon#first serial, iclass 29, count 0 2006.285.20:13:12.98#ibcon#enter sib2, iclass 29, count 0 2006.285.20:13:12.98#ibcon#flushed, iclass 29, count 0 2006.285.20:13:12.98#ibcon#about to write, iclass 29, count 0 2006.285.20:13:12.98#ibcon#wrote, iclass 29, count 0 2006.285.20:13:12.98#ibcon#about to read 3, iclass 29, count 0 2006.285.20:13:13.00#ibcon#read 3, iclass 29, count 0 2006.285.20:13:13.00#ibcon#about to read 4, iclass 29, count 0 2006.285.20:13:13.00#ibcon#read 4, iclass 29, count 0 2006.285.20:13:13.00#ibcon#about to read 5, iclass 29, count 0 2006.285.20:13:13.00#ibcon#read 5, iclass 29, count 0 2006.285.20:13:13.00#ibcon#about to read 6, iclass 29, count 0 2006.285.20:13:13.00#ibcon#read 6, iclass 29, count 0 2006.285.20:13:13.00#ibcon#end of sib2, iclass 29, count 0 2006.285.20:13:13.00#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:13:13.00#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:13:13.00#ibcon#[27=USB\r\n] 2006.285.20:13:13.00#ibcon#*before write, iclass 29, count 0 2006.285.20:13:13.00#ibcon#enter sib2, iclass 29, count 0 2006.285.20:13:13.00#ibcon#flushed, iclass 29, count 0 2006.285.20:13:13.00#ibcon#about to write, iclass 29, count 0 2006.285.20:13:13.00#ibcon#wrote, iclass 29, count 0 2006.285.20:13:13.00#ibcon#about to read 3, iclass 29, count 0 2006.285.20:13:13.03#ibcon#read 3, iclass 29, count 0 2006.285.20:13:13.03#ibcon#about to read 4, iclass 29, count 0 2006.285.20:13:13.03#ibcon#read 4, iclass 29, count 0 2006.285.20:13:13.03#ibcon#about to read 5, iclass 29, count 0 2006.285.20:13:13.03#ibcon#read 5, iclass 29, count 0 2006.285.20:13:13.03#ibcon#about to read 6, iclass 29, count 0 2006.285.20:13:13.03#ibcon#read 6, iclass 29, count 0 2006.285.20:13:13.03#ibcon#end of sib2, iclass 29, count 0 2006.285.20:13:13.03#ibcon#*after write, iclass 29, count 0 2006.285.20:13:13.03#ibcon#*before return 0, iclass 29, count 0 2006.285.20:13:13.03#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:13:13.03#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:13:13.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:13:13.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:13:13.03$vck44/vblo=8,744.99 2006.285.20:13:13.03#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.20:13:13.03#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.20:13:13.03#ibcon#ireg 17 cls_cnt 0 2006.285.20:13:13.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:13:13.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:13:13.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:13:13.03#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:13:13.03#ibcon#first serial, iclass 31, count 0 2006.285.20:13:13.03#ibcon#enter sib2, iclass 31, count 0 2006.285.20:13:13.03#ibcon#flushed, iclass 31, count 0 2006.285.20:13:13.03#ibcon#about to write, iclass 31, count 0 2006.285.20:13:13.03#ibcon#wrote, iclass 31, count 0 2006.285.20:13:13.03#ibcon#about to read 3, iclass 31, count 0 2006.285.20:13:13.05#ibcon#read 3, iclass 31, count 0 2006.285.20:13:13.15#ibcon#about to read 4, iclass 31, count 0 2006.285.20:13:13.15#ibcon#read 4, iclass 31, count 0 2006.285.20:13:13.15#ibcon#about to read 5, iclass 31, count 0 2006.285.20:13:13.15#ibcon#read 5, iclass 31, count 0 2006.285.20:13:13.15#ibcon#about to read 6, iclass 31, count 0 2006.285.20:13:13.15#ibcon#read 6, iclass 31, count 0 2006.285.20:13:13.15#ibcon#end of sib2, iclass 31, count 0 2006.285.20:13:13.15#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:13:13.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:13:13.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.20:13:13.15#ibcon#*before write, iclass 31, count 0 2006.285.20:13:13.15#ibcon#enter sib2, iclass 31, count 0 2006.285.20:13:13.15#ibcon#flushed, iclass 31, count 0 2006.285.20:13:13.15#ibcon#about to write, iclass 31, count 0 2006.285.20:13:13.15#ibcon#wrote, iclass 31, count 0 2006.285.20:13:13.15#ibcon#about to read 3, iclass 31, count 0 2006.285.20:13:13.19#ibcon#read 3, iclass 31, count 0 2006.285.20:13:13.19#ibcon#about to read 4, iclass 31, count 0 2006.285.20:13:13.19#ibcon#read 4, iclass 31, count 0 2006.285.20:13:13.19#ibcon#about to read 5, iclass 31, count 0 2006.285.20:13:13.19#ibcon#read 5, iclass 31, count 0 2006.285.20:13:13.19#ibcon#about to read 6, iclass 31, count 0 2006.285.20:13:13.19#ibcon#read 6, iclass 31, count 0 2006.285.20:13:13.19#ibcon#end of sib2, iclass 31, count 0 2006.285.20:13:13.19#ibcon#*after write, iclass 31, count 0 2006.285.20:13:13.19#ibcon#*before return 0, iclass 31, count 0 2006.285.20:13:13.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:13:13.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:13:13.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:13:13.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:13:13.19$vck44/vb=8,4 2006.285.20:13:13.19#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.20:13:13.19#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.20:13:13.19#ibcon#ireg 11 cls_cnt 2 2006.285.20:13:13.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:13:13.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:13:13.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:13:13.19#ibcon#enter wrdev, iclass 33, count 2 2006.285.20:13:13.19#ibcon#first serial, iclass 33, count 2 2006.285.20:13:13.19#ibcon#enter sib2, iclass 33, count 2 2006.285.20:13:13.19#ibcon#flushed, iclass 33, count 2 2006.285.20:13:13.19#ibcon#about to write, iclass 33, count 2 2006.285.20:13:13.19#ibcon#wrote, iclass 33, count 2 2006.285.20:13:13.19#ibcon#about to read 3, iclass 33, count 2 2006.285.20:13:13.21#ibcon#read 3, iclass 33, count 2 2006.285.20:13:13.21#ibcon#about to read 4, iclass 33, count 2 2006.285.20:13:13.21#ibcon#read 4, iclass 33, count 2 2006.285.20:13:13.21#ibcon#about to read 5, iclass 33, count 2 2006.285.20:13:13.21#ibcon#read 5, iclass 33, count 2 2006.285.20:13:13.21#ibcon#about to read 6, iclass 33, count 2 2006.285.20:13:13.21#ibcon#read 6, iclass 33, count 2 2006.285.20:13:13.21#ibcon#end of sib2, iclass 33, count 2 2006.285.20:13:13.21#ibcon#*mode == 0, iclass 33, count 2 2006.285.20:13:13.21#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.20:13:13.21#ibcon#[27=AT08-04\r\n] 2006.285.20:13:13.21#ibcon#*before write, iclass 33, count 2 2006.285.20:13:13.21#ibcon#enter sib2, iclass 33, count 2 2006.285.20:13:13.21#ibcon#flushed, iclass 33, count 2 2006.285.20:13:13.21#ibcon#about to write, iclass 33, count 2 2006.285.20:13:13.21#ibcon#wrote, iclass 33, count 2 2006.285.20:13:13.21#ibcon#about to read 3, iclass 33, count 2 2006.285.20:13:13.24#ibcon#read 3, iclass 33, count 2 2006.285.20:13:13.24#ibcon#about to read 4, iclass 33, count 2 2006.285.20:13:13.24#ibcon#read 4, iclass 33, count 2 2006.285.20:13:13.24#ibcon#about to read 5, iclass 33, count 2 2006.285.20:13:13.24#ibcon#read 5, iclass 33, count 2 2006.285.20:13:13.24#ibcon#about to read 6, iclass 33, count 2 2006.285.20:13:13.24#ibcon#read 6, iclass 33, count 2 2006.285.20:13:13.24#ibcon#end of sib2, iclass 33, count 2 2006.285.20:13:13.24#ibcon#*after write, iclass 33, count 2 2006.285.20:13:13.24#ibcon#*before return 0, iclass 33, count 2 2006.285.20:13:13.24#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:13:13.24#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:13:13.24#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.20:13:13.24#ibcon#ireg 7 cls_cnt 0 2006.285.20:13:13.24#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:13:13.36#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:13:13.36#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:13:13.36#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:13:13.36#ibcon#first serial, iclass 33, count 0 2006.285.20:13:13.36#ibcon#enter sib2, iclass 33, count 0 2006.285.20:13:13.36#ibcon#flushed, iclass 33, count 0 2006.285.20:13:13.36#ibcon#about to write, iclass 33, count 0 2006.285.20:13:13.36#ibcon#wrote, iclass 33, count 0 2006.285.20:13:13.36#ibcon#about to read 3, iclass 33, count 0 2006.285.20:13:13.38#ibcon#read 3, iclass 33, count 0 2006.285.20:13:13.38#ibcon#about to read 4, iclass 33, count 0 2006.285.20:13:13.38#ibcon#read 4, iclass 33, count 0 2006.285.20:13:13.38#ibcon#about to read 5, iclass 33, count 0 2006.285.20:13:13.38#ibcon#read 5, iclass 33, count 0 2006.285.20:13:13.38#ibcon#about to read 6, iclass 33, count 0 2006.285.20:13:13.38#ibcon#read 6, iclass 33, count 0 2006.285.20:13:13.38#ibcon#end of sib2, iclass 33, count 0 2006.285.20:13:13.38#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:13:13.38#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:13:13.38#ibcon#[27=USB\r\n] 2006.285.20:13:13.38#ibcon#*before write, iclass 33, count 0 2006.285.20:13:13.38#ibcon#enter sib2, iclass 33, count 0 2006.285.20:13:13.38#ibcon#flushed, iclass 33, count 0 2006.285.20:13:13.38#ibcon#about to write, iclass 33, count 0 2006.285.20:13:13.38#ibcon#wrote, iclass 33, count 0 2006.285.20:13:13.38#ibcon#about to read 3, iclass 33, count 0 2006.285.20:13:13.41#ibcon#read 3, iclass 33, count 0 2006.285.20:13:13.41#ibcon#about to read 4, iclass 33, count 0 2006.285.20:13:13.41#ibcon#read 4, iclass 33, count 0 2006.285.20:13:13.41#ibcon#about to read 5, iclass 33, count 0 2006.285.20:13:13.41#ibcon#read 5, iclass 33, count 0 2006.285.20:13:13.41#ibcon#about to read 6, iclass 33, count 0 2006.285.20:13:13.41#ibcon#read 6, iclass 33, count 0 2006.285.20:13:13.41#ibcon#end of sib2, iclass 33, count 0 2006.285.20:13:13.41#ibcon#*after write, iclass 33, count 0 2006.285.20:13:13.41#ibcon#*before return 0, iclass 33, count 0 2006.285.20:13:13.41#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:13:13.41#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:13:13.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:13:13.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:13:13.41$vck44/vabw=wide 2006.285.20:13:13.41#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.20:13:13.41#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.20:13:13.41#ibcon#ireg 8 cls_cnt 0 2006.285.20:13:13.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:13:13.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:13:13.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:13:13.41#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:13:13.41#ibcon#first serial, iclass 35, count 0 2006.285.20:13:13.41#ibcon#enter sib2, iclass 35, count 0 2006.285.20:13:13.41#ibcon#flushed, iclass 35, count 0 2006.285.20:13:13.41#ibcon#about to write, iclass 35, count 0 2006.285.20:13:13.41#ibcon#wrote, iclass 35, count 0 2006.285.20:13:13.41#ibcon#about to read 3, iclass 35, count 0 2006.285.20:13:13.43#ibcon#read 3, iclass 35, count 0 2006.285.20:13:13.43#ibcon#about to read 4, iclass 35, count 0 2006.285.20:13:13.43#ibcon#read 4, iclass 35, count 0 2006.285.20:13:13.43#ibcon#about to read 5, iclass 35, count 0 2006.285.20:13:13.43#ibcon#read 5, iclass 35, count 0 2006.285.20:13:13.43#ibcon#about to read 6, iclass 35, count 0 2006.285.20:13:13.43#ibcon#read 6, iclass 35, count 0 2006.285.20:13:13.43#ibcon#end of sib2, iclass 35, count 0 2006.285.20:13:13.43#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:13:13.43#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:13:13.43#ibcon#[25=BW32\r\n] 2006.285.20:13:13.43#ibcon#*before write, iclass 35, count 0 2006.285.20:13:13.43#ibcon#enter sib2, iclass 35, count 0 2006.285.20:13:13.43#ibcon#flushed, iclass 35, count 0 2006.285.20:13:13.43#ibcon#about to write, iclass 35, count 0 2006.285.20:13:13.43#ibcon#wrote, iclass 35, count 0 2006.285.20:13:13.43#ibcon#about to read 3, iclass 35, count 0 2006.285.20:13:13.46#ibcon#read 3, iclass 35, count 0 2006.285.20:13:13.46#ibcon#about to read 4, iclass 35, count 0 2006.285.20:13:13.46#ibcon#read 4, iclass 35, count 0 2006.285.20:13:13.46#ibcon#about to read 5, iclass 35, count 0 2006.285.20:13:13.46#ibcon#read 5, iclass 35, count 0 2006.285.20:13:13.46#ibcon#about to read 6, iclass 35, count 0 2006.285.20:13:13.46#ibcon#read 6, iclass 35, count 0 2006.285.20:13:13.46#ibcon#end of sib2, iclass 35, count 0 2006.285.20:13:13.46#ibcon#*after write, iclass 35, count 0 2006.285.20:13:13.46#ibcon#*before return 0, iclass 35, count 0 2006.285.20:13:13.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:13:13.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:13:13.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:13:13.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:13:13.46$vck44/vbbw=wide 2006.285.20:13:13.46#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.20:13:13.46#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.20:13:13.46#ibcon#ireg 8 cls_cnt 0 2006.285.20:13:13.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:13:13.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:13:13.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:13:13.53#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:13:13.53#ibcon#first serial, iclass 37, count 0 2006.285.20:13:13.53#ibcon#enter sib2, iclass 37, count 0 2006.285.20:13:13.53#ibcon#flushed, iclass 37, count 0 2006.285.20:13:13.53#ibcon#about to write, iclass 37, count 0 2006.285.20:13:13.53#ibcon#wrote, iclass 37, count 0 2006.285.20:13:13.53#ibcon#about to read 3, iclass 37, count 0 2006.285.20:13:13.55#ibcon#read 3, iclass 37, count 0 2006.285.20:13:13.55#ibcon#about to read 4, iclass 37, count 0 2006.285.20:13:13.55#ibcon#read 4, iclass 37, count 0 2006.285.20:13:13.55#ibcon#about to read 5, iclass 37, count 0 2006.285.20:13:13.55#ibcon#read 5, iclass 37, count 0 2006.285.20:13:13.55#ibcon#about to read 6, iclass 37, count 0 2006.285.20:13:13.55#ibcon#read 6, iclass 37, count 0 2006.285.20:13:13.55#ibcon#end of sib2, iclass 37, count 0 2006.285.20:13:13.55#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:13:13.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:13:13.55#ibcon#[27=BW32\r\n] 2006.285.20:13:13.55#ibcon#*before write, iclass 37, count 0 2006.285.20:13:13.55#ibcon#enter sib2, iclass 37, count 0 2006.285.20:13:13.55#ibcon#flushed, iclass 37, count 0 2006.285.20:13:13.55#ibcon#about to write, iclass 37, count 0 2006.285.20:13:13.55#ibcon#wrote, iclass 37, count 0 2006.285.20:13:13.55#ibcon#about to read 3, iclass 37, count 0 2006.285.20:13:13.58#ibcon#read 3, iclass 37, count 0 2006.285.20:13:13.58#ibcon#about to read 4, iclass 37, count 0 2006.285.20:13:13.58#ibcon#read 4, iclass 37, count 0 2006.285.20:13:13.58#ibcon#about to read 5, iclass 37, count 0 2006.285.20:13:13.58#ibcon#read 5, iclass 37, count 0 2006.285.20:13:13.58#ibcon#about to read 6, iclass 37, count 0 2006.285.20:13:13.58#ibcon#read 6, iclass 37, count 0 2006.285.20:13:13.58#ibcon#end of sib2, iclass 37, count 0 2006.285.20:13:13.58#ibcon#*after write, iclass 37, count 0 2006.285.20:13:13.58#ibcon#*before return 0, iclass 37, count 0 2006.285.20:13:13.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:13:13.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:13:13.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:13:13.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:13:13.58$setupk4/ifdk4 2006.285.20:13:13.58$ifdk4/lo= 2006.285.20:13:13.58$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.20:13:13.58$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.20:13:13.58$ifdk4/patch= 2006.285.20:13:13.58$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.20:13:13.58$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.20:13:13.59$setupk4/!*+20s 2006.285.20:13:22.01#abcon#<5=/09 0.5 1.1 14.521001015.3\r\n> 2006.285.20:13:22.03#abcon#{5=INTERFACE CLEAR} 2006.285.20:13:22.09#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:13:27.31$setupk4/"tpicd 2006.285.20:13:27.31$setupk4/echo=off 2006.285.20:13:27.31$setupk4/xlog=off 2006.285.20:13:27.31:!2006.285.20:14:02 2006.285.20:13:44.14#trakl#Source acquired 2006.285.20:13:46.14#flagr#flagr/antenna,acquired 2006.285.20:14:02.00:preob 2006.285.20:14:02.14/onsource/TRACKING 2006.285.20:14:02.14:!2006.285.20:14:12 2006.285.20:14:12.00:"tape 2006.285.20:14:12.00:"st=record 2006.285.20:14:12.00:data_valid=on 2006.285.20:14:12.00:midob 2006.285.20:14:13.14/onsource/TRACKING 2006.285.20:14:13.14/wx/14.51,1015.3,100 2006.285.20:14:13.23/cable/+6.5096E-03 2006.285.20:14:14.32/va/01,07,usb,yes,41,44 2006.285.20:14:14.32/va/02,06,usb,yes,41,41 2006.285.20:14:14.32/va/03,07,usb,yes,40,42 2006.285.20:14:14.32/va/04,06,usb,yes,42,44 2006.285.20:14:14.32/va/05,03,usb,yes,42,42 2006.285.20:14:14.32/va/06,04,usb,yes,38,37 2006.285.20:14:14.32/va/07,04,usb,yes,38,39 2006.285.20:14:14.32/va/08,03,usb,yes,39,47 2006.285.20:14:14.55/valo/01,524.99,yes,locked 2006.285.20:14:14.55/valo/02,534.99,yes,locked 2006.285.20:14:14.55/valo/03,564.99,yes,locked 2006.285.20:14:14.55/valo/04,624.99,yes,locked 2006.285.20:14:14.55/valo/05,734.99,yes,locked 2006.285.20:14:14.55/valo/06,814.99,yes,locked 2006.285.20:14:14.55/valo/07,864.99,yes,locked 2006.285.20:14:14.55/valo/08,884.99,yes,locked 2006.285.20:14:15.64/vb/01,04,usb,yes,35,32 2006.285.20:14:15.64/vb/02,05,usb,yes,33,33 2006.285.20:14:15.64/vb/03,04,usb,yes,34,37 2006.285.20:14:15.64/vb/04,05,usb,yes,34,33 2006.285.20:14:15.64/vb/05,04,usb,yes,30,33 2006.285.20:14:15.64/vb/06,03,usb,yes,43,39 2006.285.20:14:15.64/vb/07,04,usb,yes,35,35 2006.285.20:14:15.64/vb/08,04,usb,yes,32,36 2006.285.20:14:15.87/vblo/01,629.99,yes,locked 2006.285.20:14:15.87/vblo/02,634.99,yes,locked 2006.285.20:14:15.87/vblo/03,649.99,yes,locked 2006.285.20:14:15.87/vblo/04,679.99,yes,locked 2006.285.20:14:15.87/vblo/05,709.99,yes,locked 2006.285.20:14:15.87/vblo/06,719.99,yes,locked 2006.285.20:14:15.87/vblo/07,734.99,yes,locked 2006.285.20:14:15.87/vblo/08,744.99,yes,locked 2006.285.20:14:16.02/vabw/8 2006.285.20:14:16.17/vbbw/8 2006.285.20:14:16.26/xfe/off,on,12.0 2006.285.20:14:16.64/ifatt/23,28,28,28 2006.285.20:14:17.07/fmout-gps/S +2.72E-07 2006.285.20:14:17.10:!2006.285.20:14:52 2006.285.20:14:52.00:data_valid=off 2006.285.20:14:52.00:"et 2006.285.20:14:52.00:!+3s 2006.285.20:14:55.01:"tape 2006.285.20:14:55.01:postob 2006.285.20:14:55.15/cable/+6.5105E-03 2006.285.20:14:55.15/wx/14.50,1015.3,100 2006.285.20:14:56.07/fmout-gps/S +2.70E-07 2006.285.20:14:56.07:scan_name=285-2022,jd0610,320 2006.285.20:14:56.07:source=nrao150,035929.75,505750.2,2000.0,cw 2006.285.20:14:57.14#flagr#flagr/antenna,new-source 2006.285.20:14:57.14:checkk5 2006.285.20:14:57.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.20:14:57.96/chk_autoobs//k5ts2/ autoobs is running! 2006.285.20:14:58.40/chk_autoobs//k5ts3/ autoobs is running! 2006.285.20:14:58.81/chk_autoobs//k5ts4/ autoobs is running! 2006.285.20:14:59.29/chk_obsdata//k5ts1/T2852014??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.20:14:59.68/chk_obsdata//k5ts2/T2852014??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.20:15:00.22/chk_obsdata//k5ts3/T2852014??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.20:15:00.78/chk_obsdata//k5ts4/T2852014??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.285.20:15:01.64/k5log//k5ts1_log_newline 2006.285.20:15:02.65/k5log//k5ts2_log_newline 2006.285.20:15:03.41/k5log//k5ts3_log_newline 2006.285.20:15:04.29/k5log//k5ts4_log_newline 2006.285.20:15:04.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.20:15:04.31:setupk4=1 2006.285.20:15:04.31$setupk4/echo=on 2006.285.20:15:04.31$setupk4/pcalon 2006.285.20:15:04.31$pcalon/"no phase cal control is implemented here 2006.285.20:15:04.31$setupk4/"tpicd=stop 2006.285.20:15:04.31$setupk4/"rec=synch_on 2006.285.20:15:04.31$setupk4/"rec_mode=128 2006.285.20:15:04.31$setupk4/!* 2006.285.20:15:04.31$setupk4/recpk4 2006.285.20:15:04.32$recpk4/recpatch= 2006.285.20:15:04.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.20:15:04.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.20:15:04.32$setupk4/vck44 2006.285.20:15:04.32$vck44/valo=1,524.99 2006.285.20:15:04.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.20:15:04.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.20:15:04.32#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:04.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:15:04.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:15:04.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:15:04.32#ibcon#enter wrdev, iclass 14, count 0 2006.285.20:15:04.32#ibcon#first serial, iclass 14, count 0 2006.285.20:15:04.32#ibcon#enter sib2, iclass 14, count 0 2006.285.20:15:04.32#ibcon#flushed, iclass 14, count 0 2006.285.20:15:04.32#ibcon#about to write, iclass 14, count 0 2006.285.20:15:04.32#ibcon#wrote, iclass 14, count 0 2006.285.20:15:04.32#ibcon#about to read 3, iclass 14, count 0 2006.285.20:15:04.33#ibcon#read 3, iclass 14, count 0 2006.285.20:15:04.33#ibcon#about to read 4, iclass 14, count 0 2006.285.20:15:04.33#ibcon#read 4, iclass 14, count 0 2006.285.20:15:04.33#ibcon#about to read 5, iclass 14, count 0 2006.285.20:15:04.33#ibcon#read 5, iclass 14, count 0 2006.285.20:15:04.33#ibcon#about to read 6, iclass 14, count 0 2006.285.20:15:04.33#ibcon#read 6, iclass 14, count 0 2006.285.20:15:04.33#ibcon#end of sib2, iclass 14, count 0 2006.285.20:15:04.33#ibcon#*mode == 0, iclass 14, count 0 2006.285.20:15:04.33#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.20:15:04.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.20:15:04.33#ibcon#*before write, iclass 14, count 0 2006.285.20:15:04.33#ibcon#enter sib2, iclass 14, count 0 2006.285.20:15:04.33#ibcon#flushed, iclass 14, count 0 2006.285.20:15:04.33#ibcon#about to write, iclass 14, count 0 2006.285.20:15:04.33#ibcon#wrote, iclass 14, count 0 2006.285.20:15:04.33#ibcon#about to read 3, iclass 14, count 0 2006.285.20:15:04.38#ibcon#read 3, iclass 14, count 0 2006.285.20:15:04.38#ibcon#about to read 4, iclass 14, count 0 2006.285.20:15:04.38#ibcon#read 4, iclass 14, count 0 2006.285.20:15:04.38#ibcon#about to read 5, iclass 14, count 0 2006.285.20:15:04.38#ibcon#read 5, iclass 14, count 0 2006.285.20:15:04.38#ibcon#about to read 6, iclass 14, count 0 2006.285.20:15:04.38#ibcon#read 6, iclass 14, count 0 2006.285.20:15:04.38#ibcon#end of sib2, iclass 14, count 0 2006.285.20:15:04.38#ibcon#*after write, iclass 14, count 0 2006.285.20:15:04.38#ibcon#*before return 0, iclass 14, count 0 2006.285.20:15:04.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:15:04.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:15:04.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.20:15:04.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.20:15:04.38$vck44/va=1,7 2006.285.20:15:04.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.20:15:04.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.20:15:04.38#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:04.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:15:04.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:15:04.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:15:04.38#ibcon#enter wrdev, iclass 16, count 2 2006.285.20:15:04.38#ibcon#first serial, iclass 16, count 2 2006.285.20:15:04.38#ibcon#enter sib2, iclass 16, count 2 2006.285.20:15:04.38#ibcon#flushed, iclass 16, count 2 2006.285.20:15:04.38#ibcon#about to write, iclass 16, count 2 2006.285.20:15:04.38#ibcon#wrote, iclass 16, count 2 2006.285.20:15:04.38#ibcon#about to read 3, iclass 16, count 2 2006.285.20:15:04.40#ibcon#read 3, iclass 16, count 2 2006.285.20:15:04.40#ibcon#about to read 4, iclass 16, count 2 2006.285.20:15:04.40#ibcon#read 4, iclass 16, count 2 2006.285.20:15:04.40#ibcon#about to read 5, iclass 16, count 2 2006.285.20:15:04.40#ibcon#read 5, iclass 16, count 2 2006.285.20:15:04.40#ibcon#about to read 6, iclass 16, count 2 2006.285.20:15:04.40#ibcon#read 6, iclass 16, count 2 2006.285.20:15:04.40#ibcon#end of sib2, iclass 16, count 2 2006.285.20:15:04.40#ibcon#*mode == 0, iclass 16, count 2 2006.285.20:15:04.40#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.20:15:04.40#ibcon#[25=AT01-07\r\n] 2006.285.20:15:04.40#ibcon#*before write, iclass 16, count 2 2006.285.20:15:04.40#ibcon#enter sib2, iclass 16, count 2 2006.285.20:15:04.40#ibcon#flushed, iclass 16, count 2 2006.285.20:15:04.40#ibcon#about to write, iclass 16, count 2 2006.285.20:15:04.40#ibcon#wrote, iclass 16, count 2 2006.285.20:15:04.40#ibcon#about to read 3, iclass 16, count 2 2006.285.20:15:04.43#ibcon#read 3, iclass 16, count 2 2006.285.20:15:04.43#ibcon#about to read 4, iclass 16, count 2 2006.285.20:15:04.43#ibcon#read 4, iclass 16, count 2 2006.285.20:15:04.43#ibcon#about to read 5, iclass 16, count 2 2006.285.20:15:04.43#ibcon#read 5, iclass 16, count 2 2006.285.20:15:04.43#ibcon#about to read 6, iclass 16, count 2 2006.285.20:15:04.43#ibcon#read 6, iclass 16, count 2 2006.285.20:15:04.43#ibcon#end of sib2, iclass 16, count 2 2006.285.20:15:04.43#ibcon#*after write, iclass 16, count 2 2006.285.20:15:04.43#ibcon#*before return 0, iclass 16, count 2 2006.285.20:15:04.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:15:04.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:15:04.43#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.20:15:04.43#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:04.43#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:15:04.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:15:04.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:15:04.55#ibcon#enter wrdev, iclass 16, count 0 2006.285.20:15:04.55#ibcon#first serial, iclass 16, count 0 2006.285.20:15:04.55#ibcon#enter sib2, iclass 16, count 0 2006.285.20:15:04.55#ibcon#flushed, iclass 16, count 0 2006.285.20:15:04.55#ibcon#about to write, iclass 16, count 0 2006.285.20:15:04.55#ibcon#wrote, iclass 16, count 0 2006.285.20:15:04.55#ibcon#about to read 3, iclass 16, count 0 2006.285.20:15:04.57#ibcon#read 3, iclass 16, count 0 2006.285.20:15:04.57#ibcon#about to read 4, iclass 16, count 0 2006.285.20:15:04.57#ibcon#read 4, iclass 16, count 0 2006.285.20:15:04.57#ibcon#about to read 5, iclass 16, count 0 2006.285.20:15:04.57#ibcon#read 5, iclass 16, count 0 2006.285.20:15:04.57#ibcon#about to read 6, iclass 16, count 0 2006.285.20:15:04.57#ibcon#read 6, iclass 16, count 0 2006.285.20:15:04.57#ibcon#end of sib2, iclass 16, count 0 2006.285.20:15:04.57#ibcon#*mode == 0, iclass 16, count 0 2006.285.20:15:04.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.20:15:04.57#ibcon#[25=USB\r\n] 2006.285.20:15:04.57#ibcon#*before write, iclass 16, count 0 2006.285.20:15:04.57#ibcon#enter sib2, iclass 16, count 0 2006.285.20:15:04.57#ibcon#flushed, iclass 16, count 0 2006.285.20:15:04.57#ibcon#about to write, iclass 16, count 0 2006.285.20:15:04.57#ibcon#wrote, iclass 16, count 0 2006.285.20:15:04.57#ibcon#about to read 3, iclass 16, count 0 2006.285.20:15:04.60#ibcon#read 3, iclass 16, count 0 2006.285.20:15:04.60#ibcon#about to read 4, iclass 16, count 0 2006.285.20:15:04.60#ibcon#read 4, iclass 16, count 0 2006.285.20:15:04.60#ibcon#about to read 5, iclass 16, count 0 2006.285.20:15:04.60#ibcon#read 5, iclass 16, count 0 2006.285.20:15:04.60#ibcon#about to read 6, iclass 16, count 0 2006.285.20:15:04.60#ibcon#read 6, iclass 16, count 0 2006.285.20:15:04.60#ibcon#end of sib2, iclass 16, count 0 2006.285.20:15:04.60#ibcon#*after write, iclass 16, count 0 2006.285.20:15:04.60#ibcon#*before return 0, iclass 16, count 0 2006.285.20:15:04.60#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:15:04.60#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:15:04.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.20:15:04.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.20:15:04.60$vck44/valo=2,534.99 2006.285.20:15:04.60#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.20:15:04.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.20:15:04.60#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:04.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:15:04.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:15:04.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:15:04.60#ibcon#enter wrdev, iclass 18, count 0 2006.285.20:15:04.60#ibcon#first serial, iclass 18, count 0 2006.285.20:15:04.60#ibcon#enter sib2, iclass 18, count 0 2006.285.20:15:04.60#ibcon#flushed, iclass 18, count 0 2006.285.20:15:04.60#ibcon#about to write, iclass 18, count 0 2006.285.20:15:04.60#ibcon#wrote, iclass 18, count 0 2006.285.20:15:04.60#ibcon#about to read 3, iclass 18, count 0 2006.285.20:15:04.62#ibcon#read 3, iclass 18, count 0 2006.285.20:15:04.62#ibcon#about to read 4, iclass 18, count 0 2006.285.20:15:04.62#ibcon#read 4, iclass 18, count 0 2006.285.20:15:04.62#ibcon#about to read 5, iclass 18, count 0 2006.285.20:15:04.62#ibcon#read 5, iclass 18, count 0 2006.285.20:15:04.62#ibcon#about to read 6, iclass 18, count 0 2006.285.20:15:04.62#ibcon#read 6, iclass 18, count 0 2006.285.20:15:04.62#ibcon#end of sib2, iclass 18, count 0 2006.285.20:15:04.62#ibcon#*mode == 0, iclass 18, count 0 2006.285.20:15:04.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.20:15:04.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.20:15:04.62#ibcon#*before write, iclass 18, count 0 2006.285.20:15:04.62#ibcon#enter sib2, iclass 18, count 0 2006.285.20:15:04.62#ibcon#flushed, iclass 18, count 0 2006.285.20:15:04.62#ibcon#about to write, iclass 18, count 0 2006.285.20:15:04.62#ibcon#wrote, iclass 18, count 0 2006.285.20:15:04.62#ibcon#about to read 3, iclass 18, count 0 2006.285.20:15:04.66#ibcon#read 3, iclass 18, count 0 2006.285.20:15:04.66#ibcon#about to read 4, iclass 18, count 0 2006.285.20:15:04.66#ibcon#read 4, iclass 18, count 0 2006.285.20:15:04.66#ibcon#about to read 5, iclass 18, count 0 2006.285.20:15:04.66#ibcon#read 5, iclass 18, count 0 2006.285.20:15:04.66#ibcon#about to read 6, iclass 18, count 0 2006.285.20:15:04.66#ibcon#read 6, iclass 18, count 0 2006.285.20:15:04.66#ibcon#end of sib2, iclass 18, count 0 2006.285.20:15:04.66#ibcon#*after write, iclass 18, count 0 2006.285.20:15:04.66#ibcon#*before return 0, iclass 18, count 0 2006.285.20:15:04.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:15:04.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:15:04.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.20:15:04.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.20:15:04.66$vck44/va=2,6 2006.285.20:15:04.66#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.20:15:04.66#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.20:15:04.66#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:04.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:15:04.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:15:04.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:15:04.72#ibcon#enter wrdev, iclass 20, count 2 2006.285.20:15:04.72#ibcon#first serial, iclass 20, count 2 2006.285.20:15:04.72#ibcon#enter sib2, iclass 20, count 2 2006.285.20:15:04.72#ibcon#flushed, iclass 20, count 2 2006.285.20:15:04.72#ibcon#about to write, iclass 20, count 2 2006.285.20:15:04.72#ibcon#wrote, iclass 20, count 2 2006.285.20:15:04.72#ibcon#about to read 3, iclass 20, count 2 2006.285.20:15:04.74#ibcon#read 3, iclass 20, count 2 2006.285.20:15:04.74#ibcon#about to read 4, iclass 20, count 2 2006.285.20:15:04.74#ibcon#read 4, iclass 20, count 2 2006.285.20:15:04.74#ibcon#about to read 5, iclass 20, count 2 2006.285.20:15:04.74#ibcon#read 5, iclass 20, count 2 2006.285.20:15:04.74#ibcon#about to read 6, iclass 20, count 2 2006.285.20:15:04.74#ibcon#read 6, iclass 20, count 2 2006.285.20:15:04.74#ibcon#end of sib2, iclass 20, count 2 2006.285.20:15:04.74#ibcon#*mode == 0, iclass 20, count 2 2006.285.20:15:04.74#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.20:15:04.74#ibcon#[25=AT02-06\r\n] 2006.285.20:15:04.74#ibcon#*before write, iclass 20, count 2 2006.285.20:15:04.74#ibcon#enter sib2, iclass 20, count 2 2006.285.20:15:04.74#ibcon#flushed, iclass 20, count 2 2006.285.20:15:04.74#ibcon#about to write, iclass 20, count 2 2006.285.20:15:04.74#ibcon#wrote, iclass 20, count 2 2006.285.20:15:04.74#ibcon#about to read 3, iclass 20, count 2 2006.285.20:15:04.77#ibcon#read 3, iclass 20, count 2 2006.285.20:15:04.77#ibcon#about to read 4, iclass 20, count 2 2006.285.20:15:04.77#ibcon#read 4, iclass 20, count 2 2006.285.20:15:04.77#ibcon#about to read 5, iclass 20, count 2 2006.285.20:15:04.77#ibcon#read 5, iclass 20, count 2 2006.285.20:15:04.77#ibcon#about to read 6, iclass 20, count 2 2006.285.20:15:04.77#ibcon#read 6, iclass 20, count 2 2006.285.20:15:04.77#ibcon#end of sib2, iclass 20, count 2 2006.285.20:15:04.77#ibcon#*after write, iclass 20, count 2 2006.285.20:15:04.77#ibcon#*before return 0, iclass 20, count 2 2006.285.20:15:04.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:15:04.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:15:04.77#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.20:15:04.77#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:04.77#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:15:04.89#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:15:04.89#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:15:04.89#ibcon#enter wrdev, iclass 20, count 0 2006.285.20:15:04.89#ibcon#first serial, iclass 20, count 0 2006.285.20:15:04.89#ibcon#enter sib2, iclass 20, count 0 2006.285.20:15:04.89#ibcon#flushed, iclass 20, count 0 2006.285.20:15:04.89#ibcon#about to write, iclass 20, count 0 2006.285.20:15:04.89#ibcon#wrote, iclass 20, count 0 2006.285.20:15:04.89#ibcon#about to read 3, iclass 20, count 0 2006.285.20:15:04.91#ibcon#read 3, iclass 20, count 0 2006.285.20:15:04.91#ibcon#about to read 4, iclass 20, count 0 2006.285.20:15:04.91#ibcon#read 4, iclass 20, count 0 2006.285.20:15:04.91#ibcon#about to read 5, iclass 20, count 0 2006.285.20:15:04.91#ibcon#read 5, iclass 20, count 0 2006.285.20:15:04.91#ibcon#about to read 6, iclass 20, count 0 2006.285.20:15:04.91#ibcon#read 6, iclass 20, count 0 2006.285.20:15:04.91#ibcon#end of sib2, iclass 20, count 0 2006.285.20:15:04.91#ibcon#*mode == 0, iclass 20, count 0 2006.285.20:15:04.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.20:15:04.91#ibcon#[25=USB\r\n] 2006.285.20:15:04.91#ibcon#*before write, iclass 20, count 0 2006.285.20:15:04.91#ibcon#enter sib2, iclass 20, count 0 2006.285.20:15:04.91#ibcon#flushed, iclass 20, count 0 2006.285.20:15:04.91#ibcon#about to write, iclass 20, count 0 2006.285.20:15:04.91#ibcon#wrote, iclass 20, count 0 2006.285.20:15:04.91#ibcon#about to read 3, iclass 20, count 0 2006.285.20:15:04.94#ibcon#read 3, iclass 20, count 0 2006.285.20:15:04.94#ibcon#about to read 4, iclass 20, count 0 2006.285.20:15:04.94#ibcon#read 4, iclass 20, count 0 2006.285.20:15:04.94#ibcon#about to read 5, iclass 20, count 0 2006.285.20:15:04.94#ibcon#read 5, iclass 20, count 0 2006.285.20:15:04.94#ibcon#about to read 6, iclass 20, count 0 2006.285.20:15:04.94#ibcon#read 6, iclass 20, count 0 2006.285.20:15:04.94#ibcon#end of sib2, iclass 20, count 0 2006.285.20:15:04.94#ibcon#*after write, iclass 20, count 0 2006.285.20:15:04.94#ibcon#*before return 0, iclass 20, count 0 2006.285.20:15:04.94#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:15:04.94#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:15:04.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.20:15:04.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.20:15:04.94$vck44/valo=3,564.99 2006.285.20:15:04.94#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.20:15:04.94#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.20:15:04.94#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:04.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:15:04.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:15:04.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:15:04.94#ibcon#enter wrdev, iclass 22, count 0 2006.285.20:15:04.94#ibcon#first serial, iclass 22, count 0 2006.285.20:15:04.94#ibcon#enter sib2, iclass 22, count 0 2006.285.20:15:04.94#ibcon#flushed, iclass 22, count 0 2006.285.20:15:04.94#ibcon#about to write, iclass 22, count 0 2006.285.20:15:04.94#ibcon#wrote, iclass 22, count 0 2006.285.20:15:04.94#ibcon#about to read 3, iclass 22, count 0 2006.285.20:15:04.96#ibcon#read 3, iclass 22, count 0 2006.285.20:15:04.96#ibcon#about to read 4, iclass 22, count 0 2006.285.20:15:04.96#ibcon#read 4, iclass 22, count 0 2006.285.20:15:04.96#ibcon#about to read 5, iclass 22, count 0 2006.285.20:15:04.96#ibcon#read 5, iclass 22, count 0 2006.285.20:15:04.96#ibcon#about to read 6, iclass 22, count 0 2006.285.20:15:04.96#ibcon#read 6, iclass 22, count 0 2006.285.20:15:04.96#ibcon#end of sib2, iclass 22, count 0 2006.285.20:15:04.96#ibcon#*mode == 0, iclass 22, count 0 2006.285.20:15:04.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.20:15:04.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.20:15:04.96#ibcon#*before write, iclass 22, count 0 2006.285.20:15:04.96#ibcon#enter sib2, iclass 22, count 0 2006.285.20:15:04.96#ibcon#flushed, iclass 22, count 0 2006.285.20:15:04.96#ibcon#about to write, iclass 22, count 0 2006.285.20:15:04.96#ibcon#wrote, iclass 22, count 0 2006.285.20:15:04.96#ibcon#about to read 3, iclass 22, count 0 2006.285.20:15:05.00#ibcon#read 3, iclass 22, count 0 2006.285.20:15:05.00#ibcon#about to read 4, iclass 22, count 0 2006.285.20:15:05.00#ibcon#read 4, iclass 22, count 0 2006.285.20:15:05.00#ibcon#about to read 5, iclass 22, count 0 2006.285.20:15:05.00#ibcon#read 5, iclass 22, count 0 2006.285.20:15:05.00#ibcon#about to read 6, iclass 22, count 0 2006.285.20:15:05.00#ibcon#read 6, iclass 22, count 0 2006.285.20:15:05.00#ibcon#end of sib2, iclass 22, count 0 2006.285.20:15:05.00#ibcon#*after write, iclass 22, count 0 2006.285.20:15:05.00#ibcon#*before return 0, iclass 22, count 0 2006.285.20:15:05.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:15:05.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:15:05.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.20:15:05.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.20:15:05.00$vck44/va=3,7 2006.285.20:15:05.00#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.20:15:05.00#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.20:15:05.00#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:05.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:15:05.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:15:05.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:15:05.06#ibcon#enter wrdev, iclass 24, count 2 2006.285.20:15:05.06#ibcon#first serial, iclass 24, count 2 2006.285.20:15:05.06#ibcon#enter sib2, iclass 24, count 2 2006.285.20:15:05.06#ibcon#flushed, iclass 24, count 2 2006.285.20:15:05.06#ibcon#about to write, iclass 24, count 2 2006.285.20:15:05.06#ibcon#wrote, iclass 24, count 2 2006.285.20:15:05.06#ibcon#about to read 3, iclass 24, count 2 2006.285.20:15:05.08#ibcon#read 3, iclass 24, count 2 2006.285.20:15:05.08#ibcon#about to read 4, iclass 24, count 2 2006.285.20:15:05.08#ibcon#read 4, iclass 24, count 2 2006.285.20:15:05.08#ibcon#about to read 5, iclass 24, count 2 2006.285.20:15:05.08#ibcon#read 5, iclass 24, count 2 2006.285.20:15:05.08#ibcon#about to read 6, iclass 24, count 2 2006.285.20:15:05.08#ibcon#read 6, iclass 24, count 2 2006.285.20:15:05.08#ibcon#end of sib2, iclass 24, count 2 2006.285.20:15:05.08#ibcon#*mode == 0, iclass 24, count 2 2006.285.20:15:05.08#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.20:15:05.08#ibcon#[25=AT03-07\r\n] 2006.285.20:15:05.08#ibcon#*before write, iclass 24, count 2 2006.285.20:15:05.08#ibcon#enter sib2, iclass 24, count 2 2006.285.20:15:05.08#ibcon#flushed, iclass 24, count 2 2006.285.20:15:05.08#ibcon#about to write, iclass 24, count 2 2006.285.20:15:05.08#ibcon#wrote, iclass 24, count 2 2006.285.20:15:05.08#ibcon#about to read 3, iclass 24, count 2 2006.285.20:15:05.11#ibcon#read 3, iclass 24, count 2 2006.285.20:15:05.45#ibcon#about to read 4, iclass 24, count 2 2006.285.20:15:05.45#ibcon#read 4, iclass 24, count 2 2006.285.20:15:05.45#ibcon#about to read 5, iclass 24, count 2 2006.285.20:15:05.45#ibcon#read 5, iclass 24, count 2 2006.285.20:15:05.45#ibcon#about to read 6, iclass 24, count 2 2006.285.20:15:05.45#ibcon#read 6, iclass 24, count 2 2006.285.20:15:05.45#ibcon#end of sib2, iclass 24, count 2 2006.285.20:15:05.45#ibcon#*after write, iclass 24, count 2 2006.285.20:15:05.45#ibcon#*before return 0, iclass 24, count 2 2006.285.20:15:05.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:15:05.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:15:05.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.20:15:05.45#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:05.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:15:05.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:15:05.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:15:05.57#ibcon#enter wrdev, iclass 24, count 0 2006.285.20:15:05.57#ibcon#first serial, iclass 24, count 0 2006.285.20:15:05.57#ibcon#enter sib2, iclass 24, count 0 2006.285.20:15:05.57#ibcon#flushed, iclass 24, count 0 2006.285.20:15:05.57#ibcon#about to write, iclass 24, count 0 2006.285.20:15:05.57#ibcon#wrote, iclass 24, count 0 2006.285.20:15:05.57#ibcon#about to read 3, iclass 24, count 0 2006.285.20:15:05.59#ibcon#read 3, iclass 24, count 0 2006.285.20:15:05.59#ibcon#about to read 4, iclass 24, count 0 2006.285.20:15:05.59#ibcon#read 4, iclass 24, count 0 2006.285.20:15:05.59#ibcon#about to read 5, iclass 24, count 0 2006.285.20:15:05.59#ibcon#read 5, iclass 24, count 0 2006.285.20:15:05.59#ibcon#about to read 6, iclass 24, count 0 2006.285.20:15:05.59#ibcon#read 6, iclass 24, count 0 2006.285.20:15:05.59#ibcon#end of sib2, iclass 24, count 0 2006.285.20:15:05.59#ibcon#*mode == 0, iclass 24, count 0 2006.285.20:15:05.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.20:15:05.59#ibcon#[25=USB\r\n] 2006.285.20:15:05.59#ibcon#*before write, iclass 24, count 0 2006.285.20:15:05.59#ibcon#enter sib2, iclass 24, count 0 2006.285.20:15:05.59#ibcon#flushed, iclass 24, count 0 2006.285.20:15:05.59#ibcon#about to write, iclass 24, count 0 2006.285.20:15:05.59#ibcon#wrote, iclass 24, count 0 2006.285.20:15:05.59#ibcon#about to read 3, iclass 24, count 0 2006.285.20:15:05.62#ibcon#read 3, iclass 24, count 0 2006.285.20:15:05.62#ibcon#about to read 4, iclass 24, count 0 2006.285.20:15:05.62#ibcon#read 4, iclass 24, count 0 2006.285.20:15:05.62#ibcon#about to read 5, iclass 24, count 0 2006.285.20:15:05.62#ibcon#read 5, iclass 24, count 0 2006.285.20:15:05.62#ibcon#about to read 6, iclass 24, count 0 2006.285.20:15:05.62#ibcon#read 6, iclass 24, count 0 2006.285.20:15:05.62#ibcon#end of sib2, iclass 24, count 0 2006.285.20:15:05.62#ibcon#*after write, iclass 24, count 0 2006.285.20:15:05.62#ibcon#*before return 0, iclass 24, count 0 2006.285.20:15:05.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:15:05.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:15:05.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.20:15:05.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.20:15:05.62$vck44/valo=4,624.99 2006.285.20:15:05.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.20:15:05.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.20:15:05.62#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:05.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:15:05.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:15:05.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:15:05.62#ibcon#enter wrdev, iclass 26, count 0 2006.285.20:15:05.62#ibcon#first serial, iclass 26, count 0 2006.285.20:15:05.62#ibcon#enter sib2, iclass 26, count 0 2006.285.20:15:05.62#ibcon#flushed, iclass 26, count 0 2006.285.20:15:05.62#ibcon#about to write, iclass 26, count 0 2006.285.20:15:05.62#ibcon#wrote, iclass 26, count 0 2006.285.20:15:05.62#ibcon#about to read 3, iclass 26, count 0 2006.285.20:15:05.64#ibcon#read 3, iclass 26, count 0 2006.285.20:15:05.64#ibcon#about to read 4, iclass 26, count 0 2006.285.20:15:05.64#ibcon#read 4, iclass 26, count 0 2006.285.20:15:05.64#ibcon#about to read 5, iclass 26, count 0 2006.285.20:15:05.64#ibcon#read 5, iclass 26, count 0 2006.285.20:15:05.64#ibcon#about to read 6, iclass 26, count 0 2006.285.20:15:05.64#ibcon#read 6, iclass 26, count 0 2006.285.20:15:05.64#ibcon#end of sib2, iclass 26, count 0 2006.285.20:15:05.64#ibcon#*mode == 0, iclass 26, count 0 2006.285.20:15:05.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.20:15:05.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.20:15:05.64#ibcon#*before write, iclass 26, count 0 2006.285.20:15:05.64#ibcon#enter sib2, iclass 26, count 0 2006.285.20:15:05.64#ibcon#flushed, iclass 26, count 0 2006.285.20:15:05.64#ibcon#about to write, iclass 26, count 0 2006.285.20:15:05.64#ibcon#wrote, iclass 26, count 0 2006.285.20:15:05.64#ibcon#about to read 3, iclass 26, count 0 2006.285.20:15:05.68#ibcon#read 3, iclass 26, count 0 2006.285.20:15:05.68#ibcon#about to read 4, iclass 26, count 0 2006.285.20:15:05.68#ibcon#read 4, iclass 26, count 0 2006.285.20:15:05.68#ibcon#about to read 5, iclass 26, count 0 2006.285.20:15:05.68#ibcon#read 5, iclass 26, count 0 2006.285.20:15:05.68#ibcon#about to read 6, iclass 26, count 0 2006.285.20:15:05.68#ibcon#read 6, iclass 26, count 0 2006.285.20:15:05.68#ibcon#end of sib2, iclass 26, count 0 2006.285.20:15:05.68#ibcon#*after write, iclass 26, count 0 2006.285.20:15:05.68#ibcon#*before return 0, iclass 26, count 0 2006.285.20:15:05.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:15:05.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:15:05.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.20:15:05.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.20:15:05.68$vck44/va=4,6 2006.285.20:15:05.68#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.20:15:05.68#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.20:15:05.68#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:05.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:15:05.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:15:05.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:15:05.74#ibcon#enter wrdev, iclass 28, count 2 2006.285.20:15:05.74#ibcon#first serial, iclass 28, count 2 2006.285.20:15:05.74#ibcon#enter sib2, iclass 28, count 2 2006.285.20:15:05.74#ibcon#flushed, iclass 28, count 2 2006.285.20:15:05.74#ibcon#about to write, iclass 28, count 2 2006.285.20:15:05.74#ibcon#wrote, iclass 28, count 2 2006.285.20:15:05.74#ibcon#about to read 3, iclass 28, count 2 2006.285.20:15:05.76#ibcon#read 3, iclass 28, count 2 2006.285.20:15:05.76#ibcon#about to read 4, iclass 28, count 2 2006.285.20:15:05.76#ibcon#read 4, iclass 28, count 2 2006.285.20:15:05.76#ibcon#about to read 5, iclass 28, count 2 2006.285.20:15:05.76#ibcon#read 5, iclass 28, count 2 2006.285.20:15:05.76#ibcon#about to read 6, iclass 28, count 2 2006.285.20:15:05.76#ibcon#read 6, iclass 28, count 2 2006.285.20:15:05.76#ibcon#end of sib2, iclass 28, count 2 2006.285.20:15:05.76#ibcon#*mode == 0, iclass 28, count 2 2006.285.20:15:05.76#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.20:15:05.76#ibcon#[25=AT04-06\r\n] 2006.285.20:15:05.76#ibcon#*before write, iclass 28, count 2 2006.285.20:15:05.76#ibcon#enter sib2, iclass 28, count 2 2006.285.20:15:05.76#ibcon#flushed, iclass 28, count 2 2006.285.20:15:05.76#ibcon#about to write, iclass 28, count 2 2006.285.20:15:05.76#ibcon#wrote, iclass 28, count 2 2006.285.20:15:05.76#ibcon#about to read 3, iclass 28, count 2 2006.285.20:15:05.79#ibcon#read 3, iclass 28, count 2 2006.285.20:15:05.79#ibcon#about to read 4, iclass 28, count 2 2006.285.20:15:05.79#ibcon#read 4, iclass 28, count 2 2006.285.20:15:05.79#ibcon#about to read 5, iclass 28, count 2 2006.285.20:15:05.79#ibcon#read 5, iclass 28, count 2 2006.285.20:15:05.79#ibcon#about to read 6, iclass 28, count 2 2006.285.20:15:05.79#ibcon#read 6, iclass 28, count 2 2006.285.20:15:05.79#ibcon#end of sib2, iclass 28, count 2 2006.285.20:15:05.79#ibcon#*after write, iclass 28, count 2 2006.285.20:15:05.79#ibcon#*before return 0, iclass 28, count 2 2006.285.20:15:05.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:15:05.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:15:05.79#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.20:15:05.79#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:05.79#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:15:05.91#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:15:06.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:15:06.10#ibcon#enter wrdev, iclass 28, count 0 2006.285.20:15:06.10#ibcon#first serial, iclass 28, count 0 2006.285.20:15:06.10#ibcon#enter sib2, iclass 28, count 0 2006.285.20:15:06.10#ibcon#flushed, iclass 28, count 0 2006.285.20:15:06.10#ibcon#about to write, iclass 28, count 0 2006.285.20:15:06.10#ibcon#wrote, iclass 28, count 0 2006.285.20:15:06.10#ibcon#about to read 3, iclass 28, count 0 2006.285.20:15:06.11#ibcon#read 3, iclass 28, count 0 2006.285.20:15:06.11#ibcon#about to read 4, iclass 28, count 0 2006.285.20:15:06.11#ibcon#read 4, iclass 28, count 0 2006.285.20:15:06.11#ibcon#about to read 5, iclass 28, count 0 2006.285.20:15:06.11#ibcon#read 5, iclass 28, count 0 2006.285.20:15:06.11#ibcon#about to read 6, iclass 28, count 0 2006.285.20:15:06.11#ibcon#read 6, iclass 28, count 0 2006.285.20:15:06.11#ibcon#end of sib2, iclass 28, count 0 2006.285.20:15:06.11#ibcon#*mode == 0, iclass 28, count 0 2006.285.20:15:06.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.20:15:06.11#ibcon#[25=USB\r\n] 2006.285.20:15:06.11#ibcon#*before write, iclass 28, count 0 2006.285.20:15:06.11#ibcon#enter sib2, iclass 28, count 0 2006.285.20:15:06.11#ibcon#flushed, iclass 28, count 0 2006.285.20:15:06.11#ibcon#about to write, iclass 28, count 0 2006.285.20:15:06.11#ibcon#wrote, iclass 28, count 0 2006.285.20:15:06.11#ibcon#about to read 3, iclass 28, count 0 2006.285.20:15:06.14#ibcon#read 3, iclass 28, count 0 2006.285.20:15:06.14#ibcon#about to read 4, iclass 28, count 0 2006.285.20:15:06.14#ibcon#read 4, iclass 28, count 0 2006.285.20:15:06.14#ibcon#about to read 5, iclass 28, count 0 2006.285.20:15:06.14#ibcon#read 5, iclass 28, count 0 2006.285.20:15:06.14#ibcon#about to read 6, iclass 28, count 0 2006.285.20:15:06.14#ibcon#read 6, iclass 28, count 0 2006.285.20:15:06.14#ibcon#end of sib2, iclass 28, count 0 2006.285.20:15:06.14#ibcon#*after write, iclass 28, count 0 2006.285.20:15:06.14#ibcon#*before return 0, iclass 28, count 0 2006.285.20:15:06.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:15:06.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:15:06.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.20:15:06.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.20:15:06.14$vck44/valo=5,734.99 2006.285.20:15:06.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.20:15:06.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.20:15:06.14#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:06.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:15:06.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:15:06.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:15:06.14#ibcon#enter wrdev, iclass 30, count 0 2006.285.20:15:06.14#ibcon#first serial, iclass 30, count 0 2006.285.20:15:06.14#ibcon#enter sib2, iclass 30, count 0 2006.285.20:15:06.14#ibcon#flushed, iclass 30, count 0 2006.285.20:15:06.14#ibcon#about to write, iclass 30, count 0 2006.285.20:15:06.14#ibcon#wrote, iclass 30, count 0 2006.285.20:15:06.14#ibcon#about to read 3, iclass 30, count 0 2006.285.20:15:06.16#ibcon#read 3, iclass 30, count 0 2006.285.20:15:06.16#ibcon#about to read 4, iclass 30, count 0 2006.285.20:15:06.16#ibcon#read 4, iclass 30, count 0 2006.285.20:15:06.16#ibcon#about to read 5, iclass 30, count 0 2006.285.20:15:06.16#ibcon#read 5, iclass 30, count 0 2006.285.20:15:06.16#ibcon#about to read 6, iclass 30, count 0 2006.285.20:15:06.16#ibcon#read 6, iclass 30, count 0 2006.285.20:15:06.16#ibcon#end of sib2, iclass 30, count 0 2006.285.20:15:06.16#ibcon#*mode == 0, iclass 30, count 0 2006.285.20:15:06.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.20:15:06.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.20:15:06.16#ibcon#*before write, iclass 30, count 0 2006.285.20:15:06.16#ibcon#enter sib2, iclass 30, count 0 2006.285.20:15:06.16#ibcon#flushed, iclass 30, count 0 2006.285.20:15:06.16#ibcon#about to write, iclass 30, count 0 2006.285.20:15:06.16#ibcon#wrote, iclass 30, count 0 2006.285.20:15:06.16#ibcon#about to read 3, iclass 30, count 0 2006.285.20:15:06.20#ibcon#read 3, iclass 30, count 0 2006.285.20:15:06.20#ibcon#about to read 4, iclass 30, count 0 2006.285.20:15:06.20#ibcon#read 4, iclass 30, count 0 2006.285.20:15:06.20#ibcon#about to read 5, iclass 30, count 0 2006.285.20:15:06.20#ibcon#read 5, iclass 30, count 0 2006.285.20:15:06.20#ibcon#about to read 6, iclass 30, count 0 2006.285.20:15:06.20#ibcon#read 6, iclass 30, count 0 2006.285.20:15:06.20#ibcon#end of sib2, iclass 30, count 0 2006.285.20:15:06.20#ibcon#*after write, iclass 30, count 0 2006.285.20:15:06.20#ibcon#*before return 0, iclass 30, count 0 2006.285.20:15:06.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:15:06.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:15:06.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.20:15:06.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.20:15:06.20$vck44/va=5,3 2006.285.20:15:06.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.20:15:06.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.20:15:06.20#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:06.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:15:06.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:15:06.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:15:06.26#ibcon#enter wrdev, iclass 32, count 2 2006.285.20:15:06.26#ibcon#first serial, iclass 32, count 2 2006.285.20:15:06.26#ibcon#enter sib2, iclass 32, count 2 2006.285.20:15:06.26#ibcon#flushed, iclass 32, count 2 2006.285.20:15:06.26#ibcon#about to write, iclass 32, count 2 2006.285.20:15:06.26#ibcon#wrote, iclass 32, count 2 2006.285.20:15:06.26#ibcon#about to read 3, iclass 32, count 2 2006.285.20:15:06.28#ibcon#read 3, iclass 32, count 2 2006.285.20:15:06.28#ibcon#about to read 4, iclass 32, count 2 2006.285.20:15:06.28#ibcon#read 4, iclass 32, count 2 2006.285.20:15:06.28#ibcon#about to read 5, iclass 32, count 2 2006.285.20:15:06.28#ibcon#read 5, iclass 32, count 2 2006.285.20:15:06.28#ibcon#about to read 6, iclass 32, count 2 2006.285.20:15:06.28#ibcon#read 6, iclass 32, count 2 2006.285.20:15:06.28#ibcon#end of sib2, iclass 32, count 2 2006.285.20:15:06.28#ibcon#*mode == 0, iclass 32, count 2 2006.285.20:15:06.28#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.20:15:06.28#ibcon#[25=AT05-03\r\n] 2006.285.20:15:06.28#ibcon#*before write, iclass 32, count 2 2006.285.20:15:06.28#ibcon#enter sib2, iclass 32, count 2 2006.285.20:15:06.28#ibcon#flushed, iclass 32, count 2 2006.285.20:15:06.28#ibcon#about to write, iclass 32, count 2 2006.285.20:15:06.28#ibcon#wrote, iclass 32, count 2 2006.285.20:15:06.28#ibcon#about to read 3, iclass 32, count 2 2006.285.20:15:06.31#ibcon#read 3, iclass 32, count 2 2006.285.20:15:06.31#ibcon#about to read 4, iclass 32, count 2 2006.285.20:15:06.31#ibcon#read 4, iclass 32, count 2 2006.285.20:15:06.31#ibcon#about to read 5, iclass 32, count 2 2006.285.20:15:06.31#ibcon#read 5, iclass 32, count 2 2006.285.20:15:06.31#ibcon#about to read 6, iclass 32, count 2 2006.285.20:15:06.31#ibcon#read 6, iclass 32, count 2 2006.285.20:15:06.31#ibcon#end of sib2, iclass 32, count 2 2006.285.20:15:06.31#ibcon#*after write, iclass 32, count 2 2006.285.20:15:06.31#ibcon#*before return 0, iclass 32, count 2 2006.285.20:15:06.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:15:06.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:15:06.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.20:15:06.31#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:06.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:15:06.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:15:06.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:15:06.43#ibcon#enter wrdev, iclass 32, count 0 2006.285.20:15:06.43#ibcon#first serial, iclass 32, count 0 2006.285.20:15:06.43#ibcon#enter sib2, iclass 32, count 0 2006.285.20:15:06.43#ibcon#flushed, iclass 32, count 0 2006.285.20:15:06.43#ibcon#about to write, iclass 32, count 0 2006.285.20:15:06.43#ibcon#wrote, iclass 32, count 0 2006.285.20:15:06.43#ibcon#about to read 3, iclass 32, count 0 2006.285.20:15:06.45#ibcon#read 3, iclass 32, count 0 2006.285.20:15:06.45#ibcon#about to read 4, iclass 32, count 0 2006.285.20:15:06.45#ibcon#read 4, iclass 32, count 0 2006.285.20:15:06.45#ibcon#about to read 5, iclass 32, count 0 2006.285.20:15:06.45#ibcon#read 5, iclass 32, count 0 2006.285.20:15:06.45#ibcon#about to read 6, iclass 32, count 0 2006.285.20:15:06.45#ibcon#read 6, iclass 32, count 0 2006.285.20:15:06.45#ibcon#end of sib2, iclass 32, count 0 2006.285.20:15:06.45#ibcon#*mode == 0, iclass 32, count 0 2006.285.20:15:06.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.20:15:06.45#ibcon#[25=USB\r\n] 2006.285.20:15:06.45#ibcon#*before write, iclass 32, count 0 2006.285.20:15:06.45#ibcon#enter sib2, iclass 32, count 0 2006.285.20:15:06.45#ibcon#flushed, iclass 32, count 0 2006.285.20:15:06.45#ibcon#about to write, iclass 32, count 0 2006.285.20:15:06.45#ibcon#wrote, iclass 32, count 0 2006.285.20:15:06.45#ibcon#about to read 3, iclass 32, count 0 2006.285.20:15:06.48#ibcon#read 3, iclass 32, count 0 2006.285.20:15:06.48#ibcon#about to read 4, iclass 32, count 0 2006.285.20:15:06.48#ibcon#read 4, iclass 32, count 0 2006.285.20:15:06.48#ibcon#about to read 5, iclass 32, count 0 2006.285.20:15:06.48#ibcon#read 5, iclass 32, count 0 2006.285.20:15:06.48#ibcon#about to read 6, iclass 32, count 0 2006.285.20:15:06.48#ibcon#read 6, iclass 32, count 0 2006.285.20:15:06.48#ibcon#end of sib2, iclass 32, count 0 2006.285.20:15:06.48#ibcon#*after write, iclass 32, count 0 2006.285.20:15:06.48#ibcon#*before return 0, iclass 32, count 0 2006.285.20:15:06.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:15:06.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:15:06.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.20:15:06.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.20:15:06.48$vck44/valo=6,814.99 2006.285.20:15:06.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.20:15:06.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.20:15:06.48#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:06.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:15:06.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:15:06.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:15:06.48#ibcon#enter wrdev, iclass 34, count 0 2006.285.20:15:06.48#ibcon#first serial, iclass 34, count 0 2006.285.20:15:06.48#ibcon#enter sib2, iclass 34, count 0 2006.285.20:15:06.48#ibcon#flushed, iclass 34, count 0 2006.285.20:15:06.48#ibcon#about to write, iclass 34, count 0 2006.285.20:15:06.48#ibcon#wrote, iclass 34, count 0 2006.285.20:15:06.48#ibcon#about to read 3, iclass 34, count 0 2006.285.20:15:06.50#ibcon#read 3, iclass 34, count 0 2006.285.20:15:06.50#ibcon#about to read 4, iclass 34, count 0 2006.285.20:15:06.50#ibcon#read 4, iclass 34, count 0 2006.285.20:15:06.50#ibcon#about to read 5, iclass 34, count 0 2006.285.20:15:06.50#ibcon#read 5, iclass 34, count 0 2006.285.20:15:06.50#ibcon#about to read 6, iclass 34, count 0 2006.285.20:15:06.50#ibcon#read 6, iclass 34, count 0 2006.285.20:15:06.50#ibcon#end of sib2, iclass 34, count 0 2006.285.20:15:06.50#ibcon#*mode == 0, iclass 34, count 0 2006.285.20:15:06.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.20:15:06.50#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.20:15:06.50#ibcon#*before write, iclass 34, count 0 2006.285.20:15:06.50#ibcon#enter sib2, iclass 34, count 0 2006.285.20:15:06.50#ibcon#flushed, iclass 34, count 0 2006.285.20:15:06.50#ibcon#about to write, iclass 34, count 0 2006.285.20:15:06.50#ibcon#wrote, iclass 34, count 0 2006.285.20:15:06.50#ibcon#about to read 3, iclass 34, count 0 2006.285.20:15:06.54#ibcon#read 3, iclass 34, count 0 2006.285.20:15:06.54#ibcon#about to read 4, iclass 34, count 0 2006.285.20:15:06.54#ibcon#read 4, iclass 34, count 0 2006.285.20:15:06.54#ibcon#about to read 5, iclass 34, count 0 2006.285.20:15:06.54#ibcon#read 5, iclass 34, count 0 2006.285.20:15:06.54#ibcon#about to read 6, iclass 34, count 0 2006.285.20:15:06.54#ibcon#read 6, iclass 34, count 0 2006.285.20:15:06.54#ibcon#end of sib2, iclass 34, count 0 2006.285.20:15:06.54#ibcon#*after write, iclass 34, count 0 2006.285.20:15:06.54#ibcon#*before return 0, iclass 34, count 0 2006.285.20:15:06.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:15:06.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:15:06.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.20:15:06.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.20:15:06.54$vck44/va=6,4 2006.285.20:15:06.54#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.20:15:06.54#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.20:15:06.54#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:06.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:15:06.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:15:06.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:15:06.60#ibcon#enter wrdev, iclass 36, count 2 2006.285.20:15:06.60#ibcon#first serial, iclass 36, count 2 2006.285.20:15:06.60#ibcon#enter sib2, iclass 36, count 2 2006.285.20:15:06.60#ibcon#flushed, iclass 36, count 2 2006.285.20:15:06.60#ibcon#about to write, iclass 36, count 2 2006.285.20:15:06.60#ibcon#wrote, iclass 36, count 2 2006.285.20:15:06.60#ibcon#about to read 3, iclass 36, count 2 2006.285.20:15:06.62#ibcon#read 3, iclass 36, count 2 2006.285.20:15:06.62#ibcon#about to read 4, iclass 36, count 2 2006.285.20:15:06.62#ibcon#read 4, iclass 36, count 2 2006.285.20:15:06.62#ibcon#about to read 5, iclass 36, count 2 2006.285.20:15:06.62#ibcon#read 5, iclass 36, count 2 2006.285.20:15:06.62#ibcon#about to read 6, iclass 36, count 2 2006.285.20:15:06.62#ibcon#read 6, iclass 36, count 2 2006.285.20:15:06.62#ibcon#end of sib2, iclass 36, count 2 2006.285.20:15:06.62#ibcon#*mode == 0, iclass 36, count 2 2006.285.20:15:06.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.20:15:06.62#ibcon#[25=AT06-04\r\n] 2006.285.20:15:06.62#ibcon#*before write, iclass 36, count 2 2006.285.20:15:06.62#ibcon#enter sib2, iclass 36, count 2 2006.285.20:15:06.62#ibcon#flushed, iclass 36, count 2 2006.285.20:15:06.62#ibcon#about to write, iclass 36, count 2 2006.285.20:15:06.62#ibcon#wrote, iclass 36, count 2 2006.285.20:15:06.62#ibcon#about to read 3, iclass 36, count 2 2006.285.20:15:06.65#ibcon#read 3, iclass 36, count 2 2006.285.20:15:06.65#ibcon#about to read 4, iclass 36, count 2 2006.285.20:15:06.65#ibcon#read 4, iclass 36, count 2 2006.285.20:15:06.65#ibcon#about to read 5, iclass 36, count 2 2006.285.20:15:06.65#ibcon#read 5, iclass 36, count 2 2006.285.20:15:06.65#ibcon#about to read 6, iclass 36, count 2 2006.285.20:15:06.65#ibcon#read 6, iclass 36, count 2 2006.285.20:15:06.65#ibcon#end of sib2, iclass 36, count 2 2006.285.20:15:06.65#ibcon#*after write, iclass 36, count 2 2006.285.20:15:06.65#ibcon#*before return 0, iclass 36, count 2 2006.285.20:15:06.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:15:06.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:15:06.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.20:15:06.65#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:06.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:15:06.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:15:06.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:15:06.77#ibcon#enter wrdev, iclass 36, count 0 2006.285.20:15:06.77#ibcon#first serial, iclass 36, count 0 2006.285.20:15:06.77#ibcon#enter sib2, iclass 36, count 0 2006.285.20:15:06.77#ibcon#flushed, iclass 36, count 0 2006.285.20:15:06.77#ibcon#about to write, iclass 36, count 0 2006.285.20:15:06.77#ibcon#wrote, iclass 36, count 0 2006.285.20:15:06.77#ibcon#about to read 3, iclass 36, count 0 2006.285.20:15:06.79#ibcon#read 3, iclass 36, count 0 2006.285.20:15:06.79#ibcon#about to read 4, iclass 36, count 0 2006.285.20:15:06.79#ibcon#read 4, iclass 36, count 0 2006.285.20:15:06.79#ibcon#about to read 5, iclass 36, count 0 2006.285.20:15:06.79#ibcon#read 5, iclass 36, count 0 2006.285.20:15:06.79#ibcon#about to read 6, iclass 36, count 0 2006.285.20:15:06.79#ibcon#read 6, iclass 36, count 0 2006.285.20:15:06.79#ibcon#end of sib2, iclass 36, count 0 2006.285.20:15:06.79#ibcon#*mode == 0, iclass 36, count 0 2006.285.20:15:06.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.20:15:06.79#ibcon#[25=USB\r\n] 2006.285.20:15:06.79#ibcon#*before write, iclass 36, count 0 2006.285.20:15:06.79#ibcon#enter sib2, iclass 36, count 0 2006.285.20:15:06.79#ibcon#flushed, iclass 36, count 0 2006.285.20:15:06.79#ibcon#about to write, iclass 36, count 0 2006.285.20:15:06.79#ibcon#wrote, iclass 36, count 0 2006.285.20:15:06.79#ibcon#about to read 3, iclass 36, count 0 2006.285.20:15:06.82#ibcon#read 3, iclass 36, count 0 2006.285.20:15:06.82#ibcon#about to read 4, iclass 36, count 0 2006.285.20:15:06.82#ibcon#read 4, iclass 36, count 0 2006.285.20:15:06.82#ibcon#about to read 5, iclass 36, count 0 2006.285.20:15:06.82#ibcon#read 5, iclass 36, count 0 2006.285.20:15:06.82#ibcon#about to read 6, iclass 36, count 0 2006.285.20:15:06.82#ibcon#read 6, iclass 36, count 0 2006.285.20:15:06.82#ibcon#end of sib2, iclass 36, count 0 2006.285.20:15:06.82#ibcon#*after write, iclass 36, count 0 2006.285.20:15:06.82#ibcon#*before return 0, iclass 36, count 0 2006.285.20:15:06.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:15:06.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:15:06.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.20:15:06.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.20:15:06.82$vck44/valo=7,864.99 2006.285.20:15:06.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.20:15:06.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.20:15:06.82#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:06.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:15:06.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:15:06.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:15:06.82#ibcon#enter wrdev, iclass 38, count 0 2006.285.20:15:06.82#ibcon#first serial, iclass 38, count 0 2006.285.20:15:06.82#ibcon#enter sib2, iclass 38, count 0 2006.285.20:15:06.82#ibcon#flushed, iclass 38, count 0 2006.285.20:15:06.82#ibcon#about to write, iclass 38, count 0 2006.285.20:15:06.82#ibcon#wrote, iclass 38, count 0 2006.285.20:15:06.82#ibcon#about to read 3, iclass 38, count 0 2006.285.20:15:06.84#ibcon#read 3, iclass 38, count 0 2006.285.20:15:06.84#ibcon#about to read 4, iclass 38, count 0 2006.285.20:15:06.84#ibcon#read 4, iclass 38, count 0 2006.285.20:15:06.84#ibcon#about to read 5, iclass 38, count 0 2006.285.20:15:06.84#ibcon#read 5, iclass 38, count 0 2006.285.20:15:06.84#ibcon#about to read 6, iclass 38, count 0 2006.285.20:15:06.84#ibcon#read 6, iclass 38, count 0 2006.285.20:15:06.84#ibcon#end of sib2, iclass 38, count 0 2006.285.20:15:06.84#ibcon#*mode == 0, iclass 38, count 0 2006.285.20:15:06.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.20:15:06.84#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.20:15:06.84#ibcon#*before write, iclass 38, count 0 2006.285.20:15:06.84#ibcon#enter sib2, iclass 38, count 0 2006.285.20:15:06.84#ibcon#flushed, iclass 38, count 0 2006.285.20:15:06.84#ibcon#about to write, iclass 38, count 0 2006.285.20:15:06.84#ibcon#wrote, iclass 38, count 0 2006.285.20:15:06.84#ibcon#about to read 3, iclass 38, count 0 2006.285.20:15:06.88#ibcon#read 3, iclass 38, count 0 2006.285.20:15:06.88#ibcon#about to read 4, iclass 38, count 0 2006.285.20:15:06.88#ibcon#read 4, iclass 38, count 0 2006.285.20:15:06.88#ibcon#about to read 5, iclass 38, count 0 2006.285.20:15:06.88#ibcon#read 5, iclass 38, count 0 2006.285.20:15:06.88#ibcon#about to read 6, iclass 38, count 0 2006.285.20:15:06.88#ibcon#read 6, iclass 38, count 0 2006.285.20:15:06.88#ibcon#end of sib2, iclass 38, count 0 2006.285.20:15:06.88#ibcon#*after write, iclass 38, count 0 2006.285.20:15:06.88#ibcon#*before return 0, iclass 38, count 0 2006.285.20:15:06.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:15:06.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:15:06.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.20:15:06.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.20:15:06.88$vck44/va=7,4 2006.285.20:15:06.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.20:15:06.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.20:15:06.88#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:06.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:15:06.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:15:06.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:15:06.94#ibcon#enter wrdev, iclass 40, count 2 2006.285.20:15:06.94#ibcon#first serial, iclass 40, count 2 2006.285.20:15:06.94#ibcon#enter sib2, iclass 40, count 2 2006.285.20:15:06.94#ibcon#flushed, iclass 40, count 2 2006.285.20:15:06.94#ibcon#about to write, iclass 40, count 2 2006.285.20:15:06.94#ibcon#wrote, iclass 40, count 2 2006.285.20:15:06.94#ibcon#about to read 3, iclass 40, count 2 2006.285.20:15:06.96#ibcon#read 3, iclass 40, count 2 2006.285.20:15:06.96#ibcon#about to read 4, iclass 40, count 2 2006.285.20:15:06.96#ibcon#read 4, iclass 40, count 2 2006.285.20:15:06.96#ibcon#about to read 5, iclass 40, count 2 2006.285.20:15:06.96#ibcon#read 5, iclass 40, count 2 2006.285.20:15:06.96#ibcon#about to read 6, iclass 40, count 2 2006.285.20:15:06.96#ibcon#read 6, iclass 40, count 2 2006.285.20:15:06.96#ibcon#end of sib2, iclass 40, count 2 2006.285.20:15:06.96#ibcon#*mode == 0, iclass 40, count 2 2006.285.20:15:06.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.20:15:06.96#ibcon#[25=AT07-04\r\n] 2006.285.20:15:06.96#ibcon#*before write, iclass 40, count 2 2006.285.20:15:06.96#ibcon#enter sib2, iclass 40, count 2 2006.285.20:15:06.96#ibcon#flushed, iclass 40, count 2 2006.285.20:15:06.96#ibcon#about to write, iclass 40, count 2 2006.285.20:15:06.96#ibcon#wrote, iclass 40, count 2 2006.285.20:15:06.96#ibcon#about to read 3, iclass 40, count 2 2006.285.20:15:06.99#ibcon#read 3, iclass 40, count 2 2006.285.20:15:06.99#ibcon#about to read 4, iclass 40, count 2 2006.285.20:15:06.99#ibcon#read 4, iclass 40, count 2 2006.285.20:15:06.99#ibcon#about to read 5, iclass 40, count 2 2006.285.20:15:06.99#ibcon#read 5, iclass 40, count 2 2006.285.20:15:06.99#ibcon#about to read 6, iclass 40, count 2 2006.285.20:15:06.99#ibcon#read 6, iclass 40, count 2 2006.285.20:15:06.99#ibcon#end of sib2, iclass 40, count 2 2006.285.20:15:06.99#ibcon#*after write, iclass 40, count 2 2006.285.20:15:06.99#ibcon#*before return 0, iclass 40, count 2 2006.285.20:15:06.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:15:06.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:15:06.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.20:15:06.99#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:06.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:15:07.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:15:07.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:15:07.11#ibcon#enter wrdev, iclass 40, count 0 2006.285.20:15:07.11#ibcon#first serial, iclass 40, count 0 2006.285.20:15:07.11#ibcon#enter sib2, iclass 40, count 0 2006.285.20:15:07.11#ibcon#flushed, iclass 40, count 0 2006.285.20:15:07.11#ibcon#about to write, iclass 40, count 0 2006.285.20:15:07.11#ibcon#wrote, iclass 40, count 0 2006.285.20:15:07.11#ibcon#about to read 3, iclass 40, count 0 2006.285.20:15:07.13#ibcon#read 3, iclass 40, count 0 2006.285.20:15:07.13#ibcon#about to read 4, iclass 40, count 0 2006.285.20:15:07.13#ibcon#read 4, iclass 40, count 0 2006.285.20:15:07.13#ibcon#about to read 5, iclass 40, count 0 2006.285.20:15:07.13#ibcon#read 5, iclass 40, count 0 2006.285.20:15:07.13#ibcon#about to read 6, iclass 40, count 0 2006.285.20:15:07.13#ibcon#read 6, iclass 40, count 0 2006.285.20:15:07.13#ibcon#end of sib2, iclass 40, count 0 2006.285.20:15:07.13#ibcon#*mode == 0, iclass 40, count 0 2006.285.20:15:07.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.20:15:07.13#ibcon#[25=USB\r\n] 2006.285.20:15:07.13#ibcon#*before write, iclass 40, count 0 2006.285.20:15:07.13#ibcon#enter sib2, iclass 40, count 0 2006.285.20:15:07.13#ibcon#flushed, iclass 40, count 0 2006.285.20:15:07.13#ibcon#about to write, iclass 40, count 0 2006.285.20:15:07.13#ibcon#wrote, iclass 40, count 0 2006.285.20:15:07.13#ibcon#about to read 3, iclass 40, count 0 2006.285.20:15:07.16#ibcon#read 3, iclass 40, count 0 2006.285.20:15:07.16#ibcon#about to read 4, iclass 40, count 0 2006.285.20:15:07.16#ibcon#read 4, iclass 40, count 0 2006.285.20:15:07.16#ibcon#about to read 5, iclass 40, count 0 2006.285.20:15:07.16#ibcon#read 5, iclass 40, count 0 2006.285.20:15:07.16#ibcon#about to read 6, iclass 40, count 0 2006.285.20:15:07.16#ibcon#read 6, iclass 40, count 0 2006.285.20:15:07.16#ibcon#end of sib2, iclass 40, count 0 2006.285.20:15:07.16#ibcon#*after write, iclass 40, count 0 2006.285.20:15:07.16#ibcon#*before return 0, iclass 40, count 0 2006.285.20:15:07.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:15:07.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:15:07.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.20:15:07.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.20:15:07.16$vck44/valo=8,884.99 2006.285.20:15:07.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.20:15:07.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.20:15:07.16#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:07.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:15:07.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:15:07.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:15:07.16#ibcon#enter wrdev, iclass 4, count 0 2006.285.20:15:07.16#ibcon#first serial, iclass 4, count 0 2006.285.20:15:07.16#ibcon#enter sib2, iclass 4, count 0 2006.285.20:15:07.16#ibcon#flushed, iclass 4, count 0 2006.285.20:15:07.16#ibcon#about to write, iclass 4, count 0 2006.285.20:15:07.16#ibcon#wrote, iclass 4, count 0 2006.285.20:15:07.16#ibcon#about to read 3, iclass 4, count 0 2006.285.20:15:07.18#ibcon#read 3, iclass 4, count 0 2006.285.20:15:07.51#ibcon#about to read 4, iclass 4, count 0 2006.285.20:15:07.51#ibcon#read 4, iclass 4, count 0 2006.285.20:15:07.51#ibcon#about to read 5, iclass 4, count 0 2006.285.20:15:07.51#ibcon#read 5, iclass 4, count 0 2006.285.20:15:07.51#ibcon#about to read 6, iclass 4, count 0 2006.285.20:15:07.51#ibcon#read 6, iclass 4, count 0 2006.285.20:15:07.51#ibcon#end of sib2, iclass 4, count 0 2006.285.20:15:07.51#ibcon#*mode == 0, iclass 4, count 0 2006.285.20:15:07.51#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.20:15:07.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.20:15:07.51#ibcon#*before write, iclass 4, count 0 2006.285.20:15:07.51#ibcon#enter sib2, iclass 4, count 0 2006.285.20:15:07.51#ibcon#flushed, iclass 4, count 0 2006.285.20:15:07.51#ibcon#about to write, iclass 4, count 0 2006.285.20:15:07.51#ibcon#wrote, iclass 4, count 0 2006.285.20:15:07.51#ibcon#about to read 3, iclass 4, count 0 2006.285.20:15:07.54#ibcon#read 3, iclass 4, count 0 2006.285.20:15:07.54#ibcon#about to read 4, iclass 4, count 0 2006.285.20:15:07.54#ibcon#read 4, iclass 4, count 0 2006.285.20:15:07.54#ibcon#about to read 5, iclass 4, count 0 2006.285.20:15:07.54#ibcon#read 5, iclass 4, count 0 2006.285.20:15:07.54#ibcon#about to read 6, iclass 4, count 0 2006.285.20:15:07.54#ibcon#read 6, iclass 4, count 0 2006.285.20:15:07.54#ibcon#end of sib2, iclass 4, count 0 2006.285.20:15:07.54#ibcon#*after write, iclass 4, count 0 2006.285.20:15:07.54#ibcon#*before return 0, iclass 4, count 0 2006.285.20:15:07.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:15:07.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:15:07.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.20:15:07.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.20:15:07.54$vck44/va=8,3 2006.285.20:15:07.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.20:15:07.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.20:15:07.54#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:07.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:15:07.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:15:07.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:15:07.54#ibcon#enter wrdev, iclass 6, count 2 2006.285.20:15:07.54#ibcon#first serial, iclass 6, count 2 2006.285.20:15:07.54#ibcon#enter sib2, iclass 6, count 2 2006.285.20:15:07.54#ibcon#flushed, iclass 6, count 2 2006.285.20:15:07.54#ibcon#about to write, iclass 6, count 2 2006.285.20:15:07.54#ibcon#wrote, iclass 6, count 2 2006.285.20:15:07.54#ibcon#about to read 3, iclass 6, count 2 2006.285.20:15:07.56#ibcon#read 3, iclass 6, count 2 2006.285.20:15:07.56#ibcon#about to read 4, iclass 6, count 2 2006.285.20:15:07.56#ibcon#read 4, iclass 6, count 2 2006.285.20:15:07.56#ibcon#about to read 5, iclass 6, count 2 2006.285.20:15:07.56#ibcon#read 5, iclass 6, count 2 2006.285.20:15:07.56#ibcon#about to read 6, iclass 6, count 2 2006.285.20:15:07.56#ibcon#read 6, iclass 6, count 2 2006.285.20:15:07.56#ibcon#end of sib2, iclass 6, count 2 2006.285.20:15:07.56#ibcon#*mode == 0, iclass 6, count 2 2006.285.20:15:07.56#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.20:15:07.56#ibcon#[25=AT08-03\r\n] 2006.285.20:15:07.56#ibcon#*before write, iclass 6, count 2 2006.285.20:15:07.56#ibcon#enter sib2, iclass 6, count 2 2006.285.20:15:07.56#ibcon#flushed, iclass 6, count 2 2006.285.20:15:07.56#ibcon#about to write, iclass 6, count 2 2006.285.20:15:07.56#ibcon#wrote, iclass 6, count 2 2006.285.20:15:07.56#ibcon#about to read 3, iclass 6, count 2 2006.285.20:15:07.59#ibcon#read 3, iclass 6, count 2 2006.285.20:15:07.59#ibcon#about to read 4, iclass 6, count 2 2006.285.20:15:07.59#ibcon#read 4, iclass 6, count 2 2006.285.20:15:07.59#ibcon#about to read 5, iclass 6, count 2 2006.285.20:15:07.59#ibcon#read 5, iclass 6, count 2 2006.285.20:15:07.59#ibcon#about to read 6, iclass 6, count 2 2006.285.20:15:07.59#ibcon#read 6, iclass 6, count 2 2006.285.20:15:07.59#ibcon#end of sib2, iclass 6, count 2 2006.285.20:15:07.59#ibcon#*after write, iclass 6, count 2 2006.285.20:15:07.59#ibcon#*before return 0, iclass 6, count 2 2006.285.20:15:07.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:15:07.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:15:07.59#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.20:15:07.59#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:07.59#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:15:07.71#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:15:07.71#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:15:07.71#ibcon#enter wrdev, iclass 6, count 0 2006.285.20:15:07.71#ibcon#first serial, iclass 6, count 0 2006.285.20:15:07.71#ibcon#enter sib2, iclass 6, count 0 2006.285.20:15:07.71#ibcon#flushed, iclass 6, count 0 2006.285.20:15:07.71#ibcon#about to write, iclass 6, count 0 2006.285.20:15:07.71#ibcon#wrote, iclass 6, count 0 2006.285.20:15:07.71#ibcon#about to read 3, iclass 6, count 0 2006.285.20:15:07.73#ibcon#read 3, iclass 6, count 0 2006.285.20:15:07.73#ibcon#about to read 4, iclass 6, count 0 2006.285.20:15:07.73#ibcon#read 4, iclass 6, count 0 2006.285.20:15:07.73#ibcon#about to read 5, iclass 6, count 0 2006.285.20:15:07.73#ibcon#read 5, iclass 6, count 0 2006.285.20:15:07.73#ibcon#about to read 6, iclass 6, count 0 2006.285.20:15:07.73#ibcon#read 6, iclass 6, count 0 2006.285.20:15:07.73#ibcon#end of sib2, iclass 6, count 0 2006.285.20:15:07.73#ibcon#*mode == 0, iclass 6, count 0 2006.285.20:15:07.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.20:15:07.73#ibcon#[25=USB\r\n] 2006.285.20:15:07.73#ibcon#*before write, iclass 6, count 0 2006.285.20:15:07.73#ibcon#enter sib2, iclass 6, count 0 2006.285.20:15:07.73#ibcon#flushed, iclass 6, count 0 2006.285.20:15:07.73#ibcon#about to write, iclass 6, count 0 2006.285.20:15:07.73#ibcon#wrote, iclass 6, count 0 2006.285.20:15:07.73#ibcon#about to read 3, iclass 6, count 0 2006.285.20:15:07.76#ibcon#read 3, iclass 6, count 0 2006.285.20:15:07.76#ibcon#about to read 4, iclass 6, count 0 2006.285.20:15:07.76#ibcon#read 4, iclass 6, count 0 2006.285.20:15:07.76#ibcon#about to read 5, iclass 6, count 0 2006.285.20:15:07.76#ibcon#read 5, iclass 6, count 0 2006.285.20:15:07.76#ibcon#about to read 6, iclass 6, count 0 2006.285.20:15:07.76#ibcon#read 6, iclass 6, count 0 2006.285.20:15:07.76#ibcon#end of sib2, iclass 6, count 0 2006.285.20:15:07.76#ibcon#*after write, iclass 6, count 0 2006.285.20:15:07.76#ibcon#*before return 0, iclass 6, count 0 2006.285.20:15:07.76#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:15:07.76#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:15:07.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.20:15:07.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.20:15:07.76$vck44/vblo=1,629.99 2006.285.20:15:07.76#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.20:15:07.76#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.20:15:07.76#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:07.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:15:07.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:15:07.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:15:07.76#ibcon#enter wrdev, iclass 10, count 0 2006.285.20:15:07.76#ibcon#first serial, iclass 10, count 0 2006.285.20:15:07.76#ibcon#enter sib2, iclass 10, count 0 2006.285.20:15:07.76#ibcon#flushed, iclass 10, count 0 2006.285.20:15:07.76#ibcon#about to write, iclass 10, count 0 2006.285.20:15:07.76#ibcon#wrote, iclass 10, count 0 2006.285.20:15:07.76#ibcon#about to read 3, iclass 10, count 0 2006.285.20:15:07.78#ibcon#read 3, iclass 10, count 0 2006.285.20:15:07.78#ibcon#about to read 4, iclass 10, count 0 2006.285.20:15:07.78#ibcon#read 4, iclass 10, count 0 2006.285.20:15:07.78#ibcon#about to read 5, iclass 10, count 0 2006.285.20:15:07.78#ibcon#read 5, iclass 10, count 0 2006.285.20:15:07.78#ibcon#about to read 6, iclass 10, count 0 2006.285.20:15:07.78#ibcon#read 6, iclass 10, count 0 2006.285.20:15:07.78#ibcon#end of sib2, iclass 10, count 0 2006.285.20:15:07.78#ibcon#*mode == 0, iclass 10, count 0 2006.285.20:15:07.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.20:15:07.78#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.20:15:07.78#ibcon#*before write, iclass 10, count 0 2006.285.20:15:07.78#ibcon#enter sib2, iclass 10, count 0 2006.285.20:15:07.78#ibcon#flushed, iclass 10, count 0 2006.285.20:15:07.78#ibcon#about to write, iclass 10, count 0 2006.285.20:15:07.78#ibcon#wrote, iclass 10, count 0 2006.285.20:15:07.78#ibcon#about to read 3, iclass 10, count 0 2006.285.20:15:07.82#ibcon#read 3, iclass 10, count 0 2006.285.20:15:07.82#ibcon#about to read 4, iclass 10, count 0 2006.285.20:15:07.82#ibcon#read 4, iclass 10, count 0 2006.285.20:15:07.82#ibcon#about to read 5, iclass 10, count 0 2006.285.20:15:07.82#ibcon#read 5, iclass 10, count 0 2006.285.20:15:07.82#ibcon#about to read 6, iclass 10, count 0 2006.285.20:15:07.82#ibcon#read 6, iclass 10, count 0 2006.285.20:15:07.82#ibcon#end of sib2, iclass 10, count 0 2006.285.20:15:07.82#ibcon#*after write, iclass 10, count 0 2006.285.20:15:07.82#ibcon#*before return 0, iclass 10, count 0 2006.285.20:15:07.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:15:07.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:15:07.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.20:15:07.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.20:15:07.82$vck44/vb=1,4 2006.285.20:15:07.82#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.20:15:07.82#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.20:15:07.82#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:07.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.20:15:07.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.20:15:07.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.20:15:07.82#ibcon#enter wrdev, iclass 12, count 2 2006.285.20:15:07.82#ibcon#first serial, iclass 12, count 2 2006.285.20:15:07.82#ibcon#enter sib2, iclass 12, count 2 2006.285.20:15:07.82#ibcon#flushed, iclass 12, count 2 2006.285.20:15:07.82#ibcon#about to write, iclass 12, count 2 2006.285.20:15:07.82#ibcon#wrote, iclass 12, count 2 2006.285.20:15:07.82#ibcon#about to read 3, iclass 12, count 2 2006.285.20:15:07.84#ibcon#read 3, iclass 12, count 2 2006.285.20:15:07.84#ibcon#about to read 4, iclass 12, count 2 2006.285.20:15:07.84#ibcon#read 4, iclass 12, count 2 2006.285.20:15:07.84#ibcon#about to read 5, iclass 12, count 2 2006.285.20:15:07.84#ibcon#read 5, iclass 12, count 2 2006.285.20:15:07.84#ibcon#about to read 6, iclass 12, count 2 2006.285.20:15:07.84#ibcon#read 6, iclass 12, count 2 2006.285.20:15:07.84#ibcon#end of sib2, iclass 12, count 2 2006.285.20:15:07.84#ibcon#*mode == 0, iclass 12, count 2 2006.285.20:15:07.84#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.20:15:07.84#ibcon#[27=AT01-04\r\n] 2006.285.20:15:07.84#ibcon#*before write, iclass 12, count 2 2006.285.20:15:07.84#ibcon#enter sib2, iclass 12, count 2 2006.285.20:15:07.84#ibcon#flushed, iclass 12, count 2 2006.285.20:15:07.84#ibcon#about to write, iclass 12, count 2 2006.285.20:15:07.84#ibcon#wrote, iclass 12, count 2 2006.285.20:15:07.84#ibcon#about to read 3, iclass 12, count 2 2006.285.20:15:07.87#ibcon#read 3, iclass 12, count 2 2006.285.20:15:07.87#ibcon#about to read 4, iclass 12, count 2 2006.285.20:15:07.87#ibcon#read 4, iclass 12, count 2 2006.285.20:15:07.87#ibcon#about to read 5, iclass 12, count 2 2006.285.20:15:07.87#ibcon#read 5, iclass 12, count 2 2006.285.20:15:07.87#ibcon#about to read 6, iclass 12, count 2 2006.285.20:15:07.87#ibcon#read 6, iclass 12, count 2 2006.285.20:15:07.87#ibcon#end of sib2, iclass 12, count 2 2006.285.20:15:07.87#ibcon#*after write, iclass 12, count 2 2006.285.20:15:07.87#ibcon#*before return 0, iclass 12, count 2 2006.285.20:15:07.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.20:15:07.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.20:15:07.87#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.20:15:07.87#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:07.87#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.20:15:07.99#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.20:15:07.99#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.20:15:07.99#ibcon#enter wrdev, iclass 12, count 0 2006.285.20:15:07.99#ibcon#first serial, iclass 12, count 0 2006.285.20:15:07.99#ibcon#enter sib2, iclass 12, count 0 2006.285.20:15:07.99#ibcon#flushed, iclass 12, count 0 2006.285.20:15:07.99#ibcon#about to write, iclass 12, count 0 2006.285.20:15:07.99#ibcon#wrote, iclass 12, count 0 2006.285.20:15:07.99#ibcon#about to read 3, iclass 12, count 0 2006.285.20:15:08.01#ibcon#read 3, iclass 12, count 0 2006.285.20:15:08.01#ibcon#about to read 4, iclass 12, count 0 2006.285.20:15:08.01#ibcon#read 4, iclass 12, count 0 2006.285.20:15:08.01#ibcon#about to read 5, iclass 12, count 0 2006.285.20:15:08.01#ibcon#read 5, iclass 12, count 0 2006.285.20:15:08.01#ibcon#about to read 6, iclass 12, count 0 2006.285.20:15:08.01#ibcon#read 6, iclass 12, count 0 2006.285.20:15:08.01#ibcon#end of sib2, iclass 12, count 0 2006.285.20:15:08.01#ibcon#*mode == 0, iclass 12, count 0 2006.285.20:15:08.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.20:15:08.01#ibcon#[27=USB\r\n] 2006.285.20:15:08.01#ibcon#*before write, iclass 12, count 0 2006.285.20:15:08.01#ibcon#enter sib2, iclass 12, count 0 2006.285.20:15:08.01#ibcon#flushed, iclass 12, count 0 2006.285.20:15:08.01#ibcon#about to write, iclass 12, count 0 2006.285.20:15:08.01#ibcon#wrote, iclass 12, count 0 2006.285.20:15:08.01#ibcon#about to read 3, iclass 12, count 0 2006.285.20:15:08.04#ibcon#read 3, iclass 12, count 0 2006.285.20:15:08.04#ibcon#about to read 4, iclass 12, count 0 2006.285.20:15:08.04#ibcon#read 4, iclass 12, count 0 2006.285.20:15:08.04#ibcon#about to read 5, iclass 12, count 0 2006.285.20:15:08.04#ibcon#read 5, iclass 12, count 0 2006.285.20:15:08.04#ibcon#about to read 6, iclass 12, count 0 2006.285.20:15:08.04#ibcon#read 6, iclass 12, count 0 2006.285.20:15:08.04#ibcon#end of sib2, iclass 12, count 0 2006.285.20:15:08.04#ibcon#*after write, iclass 12, count 0 2006.285.20:15:08.04#ibcon#*before return 0, iclass 12, count 0 2006.285.20:15:08.04#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.20:15:08.04#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.20:15:08.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.20:15:08.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.20:15:08.04$vck44/vblo=2,634.99 2006.285.20:15:08.04#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.20:15:08.04#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.20:15:08.04#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:08.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:15:08.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:15:08.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:15:08.04#ibcon#enter wrdev, iclass 14, count 0 2006.285.20:15:08.04#ibcon#first serial, iclass 14, count 0 2006.285.20:15:08.04#ibcon#enter sib2, iclass 14, count 0 2006.285.20:15:08.04#ibcon#flushed, iclass 14, count 0 2006.285.20:15:08.04#ibcon#about to write, iclass 14, count 0 2006.285.20:15:08.04#ibcon#wrote, iclass 14, count 0 2006.285.20:15:08.04#ibcon#about to read 3, iclass 14, count 0 2006.285.20:15:08.06#ibcon#read 3, iclass 14, count 0 2006.285.20:15:08.06#ibcon#about to read 4, iclass 14, count 0 2006.285.20:15:08.06#ibcon#read 4, iclass 14, count 0 2006.285.20:15:08.06#ibcon#about to read 5, iclass 14, count 0 2006.285.20:15:08.06#ibcon#read 5, iclass 14, count 0 2006.285.20:15:08.06#ibcon#about to read 6, iclass 14, count 0 2006.285.20:15:08.06#ibcon#read 6, iclass 14, count 0 2006.285.20:15:08.06#ibcon#end of sib2, iclass 14, count 0 2006.285.20:15:08.06#ibcon#*mode == 0, iclass 14, count 0 2006.285.20:15:08.06#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.20:15:08.06#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.20:15:08.06#ibcon#*before write, iclass 14, count 0 2006.285.20:15:08.06#ibcon#enter sib2, iclass 14, count 0 2006.285.20:15:08.06#ibcon#flushed, iclass 14, count 0 2006.285.20:15:08.06#ibcon#about to write, iclass 14, count 0 2006.285.20:15:08.06#ibcon#wrote, iclass 14, count 0 2006.285.20:15:08.06#ibcon#about to read 3, iclass 14, count 0 2006.285.20:15:08.10#ibcon#read 3, iclass 14, count 0 2006.285.20:15:08.10#ibcon#about to read 4, iclass 14, count 0 2006.285.20:15:08.10#ibcon#read 4, iclass 14, count 0 2006.285.20:15:08.10#ibcon#about to read 5, iclass 14, count 0 2006.285.20:15:08.10#ibcon#read 5, iclass 14, count 0 2006.285.20:15:08.10#ibcon#about to read 6, iclass 14, count 0 2006.285.20:15:08.10#ibcon#read 6, iclass 14, count 0 2006.285.20:15:08.10#ibcon#end of sib2, iclass 14, count 0 2006.285.20:15:08.10#ibcon#*after write, iclass 14, count 0 2006.285.20:15:08.10#ibcon#*before return 0, iclass 14, count 0 2006.285.20:15:08.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:15:08.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:15:08.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.20:15:08.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.20:15:08.10$vck44/vb=2,5 2006.285.20:15:08.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.20:15:08.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.20:15:08.21#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:08.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:15:08.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:15:08.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:15:08.21#ibcon#enter wrdev, iclass 16, count 2 2006.285.20:15:08.21#ibcon#first serial, iclass 16, count 2 2006.285.20:15:08.21#ibcon#enter sib2, iclass 16, count 2 2006.285.20:15:08.21#ibcon#flushed, iclass 16, count 2 2006.285.20:15:08.21#ibcon#about to write, iclass 16, count 2 2006.285.20:15:08.21#ibcon#wrote, iclass 16, count 2 2006.285.20:15:08.21#ibcon#about to read 3, iclass 16, count 2 2006.285.20:15:08.22#ibcon#read 3, iclass 16, count 2 2006.285.20:15:08.22#ibcon#about to read 4, iclass 16, count 2 2006.285.20:15:08.22#ibcon#read 4, iclass 16, count 2 2006.285.20:15:08.22#ibcon#about to read 5, iclass 16, count 2 2006.285.20:15:08.22#ibcon#read 5, iclass 16, count 2 2006.285.20:15:08.22#ibcon#about to read 6, iclass 16, count 2 2006.285.20:15:08.22#ibcon#read 6, iclass 16, count 2 2006.285.20:15:08.22#ibcon#end of sib2, iclass 16, count 2 2006.285.20:15:08.22#ibcon#*mode == 0, iclass 16, count 2 2006.285.20:15:08.22#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.20:15:08.22#ibcon#[27=AT02-05\r\n] 2006.285.20:15:08.22#ibcon#*before write, iclass 16, count 2 2006.285.20:15:08.22#ibcon#enter sib2, iclass 16, count 2 2006.285.20:15:08.22#ibcon#flushed, iclass 16, count 2 2006.285.20:15:08.22#ibcon#about to write, iclass 16, count 2 2006.285.20:15:08.22#ibcon#wrote, iclass 16, count 2 2006.285.20:15:08.22#ibcon#about to read 3, iclass 16, count 2 2006.285.20:15:08.25#ibcon#read 3, iclass 16, count 2 2006.285.20:15:08.25#ibcon#about to read 4, iclass 16, count 2 2006.285.20:15:08.25#ibcon#read 4, iclass 16, count 2 2006.285.20:15:08.25#ibcon#about to read 5, iclass 16, count 2 2006.285.20:15:08.25#ibcon#read 5, iclass 16, count 2 2006.285.20:15:08.25#ibcon#about to read 6, iclass 16, count 2 2006.285.20:15:08.25#ibcon#read 6, iclass 16, count 2 2006.285.20:15:08.25#ibcon#end of sib2, iclass 16, count 2 2006.285.20:15:08.25#ibcon#*after write, iclass 16, count 2 2006.285.20:15:08.25#ibcon#*before return 0, iclass 16, count 2 2006.285.20:15:08.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:15:08.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:15:08.25#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.20:15:08.25#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:08.25#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:15:08.37#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:15:08.37#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:15:08.37#ibcon#enter wrdev, iclass 16, count 0 2006.285.20:15:08.37#ibcon#first serial, iclass 16, count 0 2006.285.20:15:08.37#ibcon#enter sib2, iclass 16, count 0 2006.285.20:15:08.37#ibcon#flushed, iclass 16, count 0 2006.285.20:15:08.37#ibcon#about to write, iclass 16, count 0 2006.285.20:15:08.37#ibcon#wrote, iclass 16, count 0 2006.285.20:15:08.37#ibcon#about to read 3, iclass 16, count 0 2006.285.20:15:08.39#ibcon#read 3, iclass 16, count 0 2006.285.20:15:08.39#ibcon#about to read 4, iclass 16, count 0 2006.285.20:15:08.39#ibcon#read 4, iclass 16, count 0 2006.285.20:15:08.39#ibcon#about to read 5, iclass 16, count 0 2006.285.20:15:08.39#ibcon#read 5, iclass 16, count 0 2006.285.20:15:08.39#ibcon#about to read 6, iclass 16, count 0 2006.285.20:15:08.39#ibcon#read 6, iclass 16, count 0 2006.285.20:15:08.39#ibcon#end of sib2, iclass 16, count 0 2006.285.20:15:08.39#ibcon#*mode == 0, iclass 16, count 0 2006.285.20:15:08.39#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.20:15:08.39#ibcon#[27=USB\r\n] 2006.285.20:15:08.39#ibcon#*before write, iclass 16, count 0 2006.285.20:15:08.39#ibcon#enter sib2, iclass 16, count 0 2006.285.20:15:08.39#ibcon#flushed, iclass 16, count 0 2006.285.20:15:08.39#ibcon#about to write, iclass 16, count 0 2006.285.20:15:08.39#ibcon#wrote, iclass 16, count 0 2006.285.20:15:08.39#ibcon#about to read 3, iclass 16, count 0 2006.285.20:15:08.42#ibcon#read 3, iclass 16, count 0 2006.285.20:15:08.42#ibcon#about to read 4, iclass 16, count 0 2006.285.20:15:08.42#ibcon#read 4, iclass 16, count 0 2006.285.20:15:08.42#ibcon#about to read 5, iclass 16, count 0 2006.285.20:15:08.42#ibcon#read 5, iclass 16, count 0 2006.285.20:15:08.42#ibcon#about to read 6, iclass 16, count 0 2006.285.20:15:08.42#ibcon#read 6, iclass 16, count 0 2006.285.20:15:08.42#ibcon#end of sib2, iclass 16, count 0 2006.285.20:15:08.42#ibcon#*after write, iclass 16, count 0 2006.285.20:15:08.42#ibcon#*before return 0, iclass 16, count 0 2006.285.20:15:08.42#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:15:08.42#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:15:08.42#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.20:15:08.42#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.20:15:08.42$vck44/vblo=3,649.99 2006.285.20:15:08.42#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.20:15:08.42#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.20:15:08.42#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:08.42#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:15:08.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:15:08.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:15:08.42#ibcon#enter wrdev, iclass 18, count 0 2006.285.20:15:08.42#ibcon#first serial, iclass 18, count 0 2006.285.20:15:08.42#ibcon#enter sib2, iclass 18, count 0 2006.285.20:15:08.42#ibcon#flushed, iclass 18, count 0 2006.285.20:15:08.42#ibcon#about to write, iclass 18, count 0 2006.285.20:15:08.42#ibcon#wrote, iclass 18, count 0 2006.285.20:15:08.42#ibcon#about to read 3, iclass 18, count 0 2006.285.20:15:08.44#ibcon#read 3, iclass 18, count 0 2006.285.20:15:08.44#ibcon#about to read 4, iclass 18, count 0 2006.285.20:15:08.44#ibcon#read 4, iclass 18, count 0 2006.285.20:15:08.44#ibcon#about to read 5, iclass 18, count 0 2006.285.20:15:08.44#ibcon#read 5, iclass 18, count 0 2006.285.20:15:08.44#ibcon#about to read 6, iclass 18, count 0 2006.285.20:15:08.44#ibcon#read 6, iclass 18, count 0 2006.285.20:15:08.44#ibcon#end of sib2, iclass 18, count 0 2006.285.20:15:08.44#ibcon#*mode == 0, iclass 18, count 0 2006.285.20:15:08.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.20:15:08.44#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.20:15:08.44#ibcon#*before write, iclass 18, count 0 2006.285.20:15:08.44#ibcon#enter sib2, iclass 18, count 0 2006.285.20:15:08.44#ibcon#flushed, iclass 18, count 0 2006.285.20:15:08.44#ibcon#about to write, iclass 18, count 0 2006.285.20:15:08.44#ibcon#wrote, iclass 18, count 0 2006.285.20:15:08.44#ibcon#about to read 3, iclass 18, count 0 2006.285.20:15:08.48#ibcon#read 3, iclass 18, count 0 2006.285.20:15:08.48#ibcon#about to read 4, iclass 18, count 0 2006.285.20:15:08.48#ibcon#read 4, iclass 18, count 0 2006.285.20:15:08.48#ibcon#about to read 5, iclass 18, count 0 2006.285.20:15:08.48#ibcon#read 5, iclass 18, count 0 2006.285.20:15:08.48#ibcon#about to read 6, iclass 18, count 0 2006.285.20:15:08.48#ibcon#read 6, iclass 18, count 0 2006.285.20:15:08.48#ibcon#end of sib2, iclass 18, count 0 2006.285.20:15:08.48#ibcon#*after write, iclass 18, count 0 2006.285.20:15:08.48#ibcon#*before return 0, iclass 18, count 0 2006.285.20:15:08.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:15:08.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:15:08.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.20:15:08.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.20:15:08.48$vck44/vb=3,4 2006.285.20:15:08.48#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.20:15:08.48#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.20:15:08.48#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:08.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:15:08.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:15:08.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:15:08.54#ibcon#enter wrdev, iclass 20, count 2 2006.285.20:15:08.54#ibcon#first serial, iclass 20, count 2 2006.285.20:15:08.54#ibcon#enter sib2, iclass 20, count 2 2006.285.20:15:08.54#ibcon#flushed, iclass 20, count 2 2006.285.20:15:08.54#ibcon#about to write, iclass 20, count 2 2006.285.20:15:08.54#ibcon#wrote, iclass 20, count 2 2006.285.20:15:08.54#ibcon#about to read 3, iclass 20, count 2 2006.285.20:15:08.56#ibcon#read 3, iclass 20, count 2 2006.285.20:15:08.56#ibcon#about to read 4, iclass 20, count 2 2006.285.20:15:08.56#ibcon#read 4, iclass 20, count 2 2006.285.20:15:08.56#ibcon#about to read 5, iclass 20, count 2 2006.285.20:15:08.56#ibcon#read 5, iclass 20, count 2 2006.285.20:15:08.56#ibcon#about to read 6, iclass 20, count 2 2006.285.20:15:08.56#ibcon#read 6, iclass 20, count 2 2006.285.20:15:08.56#ibcon#end of sib2, iclass 20, count 2 2006.285.20:15:08.56#ibcon#*mode == 0, iclass 20, count 2 2006.285.20:15:08.56#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.20:15:08.56#ibcon#[27=AT03-04\r\n] 2006.285.20:15:08.56#ibcon#*before write, iclass 20, count 2 2006.285.20:15:08.56#ibcon#enter sib2, iclass 20, count 2 2006.285.20:15:08.56#ibcon#flushed, iclass 20, count 2 2006.285.20:15:08.56#ibcon#about to write, iclass 20, count 2 2006.285.20:15:08.56#ibcon#wrote, iclass 20, count 2 2006.285.20:15:08.56#ibcon#about to read 3, iclass 20, count 2 2006.285.20:15:08.59#ibcon#read 3, iclass 20, count 2 2006.285.20:15:08.59#ibcon#about to read 4, iclass 20, count 2 2006.285.20:15:08.59#ibcon#read 4, iclass 20, count 2 2006.285.20:15:08.59#ibcon#about to read 5, iclass 20, count 2 2006.285.20:15:08.59#ibcon#read 5, iclass 20, count 2 2006.285.20:15:08.59#ibcon#about to read 6, iclass 20, count 2 2006.285.20:15:08.59#ibcon#read 6, iclass 20, count 2 2006.285.20:15:08.59#ibcon#end of sib2, iclass 20, count 2 2006.285.20:15:08.59#ibcon#*after write, iclass 20, count 2 2006.285.20:15:08.59#ibcon#*before return 0, iclass 20, count 2 2006.285.20:15:08.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:15:08.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:15:08.59#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.20:15:08.59#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:08.59#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:15:08.71#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:15:08.71#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:15:08.71#ibcon#enter wrdev, iclass 20, count 0 2006.285.20:15:08.71#ibcon#first serial, iclass 20, count 0 2006.285.20:15:08.71#ibcon#enter sib2, iclass 20, count 0 2006.285.20:15:08.71#ibcon#flushed, iclass 20, count 0 2006.285.20:15:08.71#ibcon#about to write, iclass 20, count 0 2006.285.20:15:08.71#ibcon#wrote, iclass 20, count 0 2006.285.20:15:08.71#ibcon#about to read 3, iclass 20, count 0 2006.285.20:15:08.73#ibcon#read 3, iclass 20, count 0 2006.285.20:15:08.73#ibcon#about to read 4, iclass 20, count 0 2006.285.20:15:08.73#ibcon#read 4, iclass 20, count 0 2006.285.20:15:08.73#ibcon#about to read 5, iclass 20, count 0 2006.285.20:15:08.73#ibcon#read 5, iclass 20, count 0 2006.285.20:15:08.73#ibcon#about to read 6, iclass 20, count 0 2006.285.20:15:08.73#ibcon#read 6, iclass 20, count 0 2006.285.20:15:08.73#ibcon#end of sib2, iclass 20, count 0 2006.285.20:15:08.73#ibcon#*mode == 0, iclass 20, count 0 2006.285.20:15:08.73#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.20:15:08.73#ibcon#[27=USB\r\n] 2006.285.20:15:08.73#ibcon#*before write, iclass 20, count 0 2006.285.20:15:08.73#ibcon#enter sib2, iclass 20, count 0 2006.285.20:15:08.73#ibcon#flushed, iclass 20, count 0 2006.285.20:15:08.73#ibcon#about to write, iclass 20, count 0 2006.285.20:15:08.73#ibcon#wrote, iclass 20, count 0 2006.285.20:15:08.73#ibcon#about to read 3, iclass 20, count 0 2006.285.20:15:08.76#ibcon#read 3, iclass 20, count 0 2006.285.20:15:08.76#ibcon#about to read 4, iclass 20, count 0 2006.285.20:15:08.76#ibcon#read 4, iclass 20, count 0 2006.285.20:15:08.76#ibcon#about to read 5, iclass 20, count 0 2006.285.20:15:08.76#ibcon#read 5, iclass 20, count 0 2006.285.20:15:08.76#ibcon#about to read 6, iclass 20, count 0 2006.285.20:15:08.76#ibcon#read 6, iclass 20, count 0 2006.285.20:15:08.76#ibcon#end of sib2, iclass 20, count 0 2006.285.20:15:08.76#ibcon#*after write, iclass 20, count 0 2006.285.20:15:08.76#ibcon#*before return 0, iclass 20, count 0 2006.285.20:15:08.76#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:15:08.76#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:15:08.76#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.20:15:08.76#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.20:15:08.76$vck44/vblo=4,679.99 2006.285.20:15:08.76#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.20:15:08.76#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.20:15:08.76#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:08.76#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:15:08.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:15:08.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:15:08.76#ibcon#enter wrdev, iclass 22, count 0 2006.285.20:15:08.76#ibcon#first serial, iclass 22, count 0 2006.285.20:15:08.76#ibcon#enter sib2, iclass 22, count 0 2006.285.20:15:08.76#ibcon#flushed, iclass 22, count 0 2006.285.20:15:08.76#ibcon#about to write, iclass 22, count 0 2006.285.20:15:08.76#ibcon#wrote, iclass 22, count 0 2006.285.20:15:08.76#ibcon#about to read 3, iclass 22, count 0 2006.285.20:15:08.78#ibcon#read 3, iclass 22, count 0 2006.285.20:15:08.78#ibcon#about to read 4, iclass 22, count 0 2006.285.20:15:08.78#ibcon#read 4, iclass 22, count 0 2006.285.20:15:08.78#ibcon#about to read 5, iclass 22, count 0 2006.285.20:15:08.78#ibcon#read 5, iclass 22, count 0 2006.285.20:15:08.78#ibcon#about to read 6, iclass 22, count 0 2006.285.20:15:08.78#ibcon#read 6, iclass 22, count 0 2006.285.20:15:08.78#ibcon#end of sib2, iclass 22, count 0 2006.285.20:15:08.78#ibcon#*mode == 0, iclass 22, count 0 2006.285.20:15:08.78#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.20:15:08.78#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.20:15:08.78#ibcon#*before write, iclass 22, count 0 2006.285.20:15:08.78#ibcon#enter sib2, iclass 22, count 0 2006.285.20:15:08.78#ibcon#flushed, iclass 22, count 0 2006.285.20:15:08.78#ibcon#about to write, iclass 22, count 0 2006.285.20:15:08.78#ibcon#wrote, iclass 22, count 0 2006.285.20:15:08.78#ibcon#about to read 3, iclass 22, count 0 2006.285.20:15:08.82#ibcon#read 3, iclass 22, count 0 2006.285.20:15:08.82#ibcon#about to read 4, iclass 22, count 0 2006.285.20:15:08.82#ibcon#read 4, iclass 22, count 0 2006.285.20:15:08.82#ibcon#about to read 5, iclass 22, count 0 2006.285.20:15:08.82#ibcon#read 5, iclass 22, count 0 2006.285.20:15:08.82#ibcon#about to read 6, iclass 22, count 0 2006.285.20:15:08.82#ibcon#read 6, iclass 22, count 0 2006.285.20:15:08.82#ibcon#end of sib2, iclass 22, count 0 2006.285.20:15:08.82#ibcon#*after write, iclass 22, count 0 2006.285.20:15:08.82#ibcon#*before return 0, iclass 22, count 0 2006.285.20:15:08.82#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:15:08.82#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:15:08.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.20:15:08.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.20:15:08.82$vck44/vb=4,5 2006.285.20:15:08.82#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.20:15:08.82#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.20:15:08.82#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:08.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:15:08.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:15:08.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:15:08.88#ibcon#enter wrdev, iclass 24, count 2 2006.285.20:15:08.88#ibcon#first serial, iclass 24, count 2 2006.285.20:15:08.88#ibcon#enter sib2, iclass 24, count 2 2006.285.20:15:08.88#ibcon#flushed, iclass 24, count 2 2006.285.20:15:08.88#ibcon#about to write, iclass 24, count 2 2006.285.20:15:08.88#ibcon#wrote, iclass 24, count 2 2006.285.20:15:08.88#ibcon#about to read 3, iclass 24, count 2 2006.285.20:15:08.90#ibcon#read 3, iclass 24, count 2 2006.285.20:15:08.90#ibcon#about to read 4, iclass 24, count 2 2006.285.20:15:08.90#ibcon#read 4, iclass 24, count 2 2006.285.20:15:08.90#ibcon#about to read 5, iclass 24, count 2 2006.285.20:15:08.90#ibcon#read 5, iclass 24, count 2 2006.285.20:15:08.90#ibcon#about to read 6, iclass 24, count 2 2006.285.20:15:08.90#ibcon#read 6, iclass 24, count 2 2006.285.20:15:08.90#ibcon#end of sib2, iclass 24, count 2 2006.285.20:15:08.90#ibcon#*mode == 0, iclass 24, count 2 2006.285.20:15:08.90#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.20:15:08.90#ibcon#[27=AT04-05\r\n] 2006.285.20:15:08.90#ibcon#*before write, iclass 24, count 2 2006.285.20:15:08.90#ibcon#enter sib2, iclass 24, count 2 2006.285.20:15:08.90#ibcon#flushed, iclass 24, count 2 2006.285.20:15:08.90#ibcon#about to write, iclass 24, count 2 2006.285.20:15:08.90#ibcon#wrote, iclass 24, count 2 2006.285.20:15:08.90#ibcon#about to read 3, iclass 24, count 2 2006.285.20:15:08.93#ibcon#read 3, iclass 24, count 2 2006.285.20:15:08.93#ibcon#about to read 4, iclass 24, count 2 2006.285.20:15:08.93#ibcon#read 4, iclass 24, count 2 2006.285.20:15:08.93#ibcon#about to read 5, iclass 24, count 2 2006.285.20:15:08.93#ibcon#read 5, iclass 24, count 2 2006.285.20:15:08.93#ibcon#about to read 6, iclass 24, count 2 2006.285.20:15:08.93#ibcon#read 6, iclass 24, count 2 2006.285.20:15:08.93#ibcon#end of sib2, iclass 24, count 2 2006.285.20:15:08.93#ibcon#*after write, iclass 24, count 2 2006.285.20:15:08.93#ibcon#*before return 0, iclass 24, count 2 2006.285.20:15:08.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:15:08.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:15:08.93#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.20:15:08.93#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:08.93#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:15:09.05#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:15:09.05#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:15:09.05#ibcon#enter wrdev, iclass 24, count 0 2006.285.20:15:09.05#ibcon#first serial, iclass 24, count 0 2006.285.20:15:09.05#ibcon#enter sib2, iclass 24, count 0 2006.285.20:15:09.05#ibcon#flushed, iclass 24, count 0 2006.285.20:15:09.05#ibcon#about to write, iclass 24, count 0 2006.285.20:15:09.05#ibcon#wrote, iclass 24, count 0 2006.285.20:15:09.05#ibcon#about to read 3, iclass 24, count 0 2006.285.20:15:09.07#ibcon#read 3, iclass 24, count 0 2006.285.20:15:09.07#ibcon#about to read 4, iclass 24, count 0 2006.285.20:15:09.07#ibcon#read 4, iclass 24, count 0 2006.285.20:15:09.07#ibcon#about to read 5, iclass 24, count 0 2006.285.20:15:09.07#ibcon#read 5, iclass 24, count 0 2006.285.20:15:09.07#ibcon#about to read 6, iclass 24, count 0 2006.285.20:15:09.07#ibcon#read 6, iclass 24, count 0 2006.285.20:15:09.07#ibcon#end of sib2, iclass 24, count 0 2006.285.20:15:09.07#ibcon#*mode == 0, iclass 24, count 0 2006.285.20:15:09.07#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.20:15:09.07#ibcon#[27=USB\r\n] 2006.285.20:15:09.07#ibcon#*before write, iclass 24, count 0 2006.285.20:15:09.07#ibcon#enter sib2, iclass 24, count 0 2006.285.20:15:09.07#ibcon#flushed, iclass 24, count 0 2006.285.20:15:09.07#ibcon#about to write, iclass 24, count 0 2006.285.20:15:09.07#ibcon#wrote, iclass 24, count 0 2006.285.20:15:09.07#ibcon#about to read 3, iclass 24, count 0 2006.285.20:15:09.10#ibcon#read 3, iclass 24, count 0 2006.285.20:15:09.10#ibcon#about to read 4, iclass 24, count 0 2006.285.20:15:09.10#ibcon#read 4, iclass 24, count 0 2006.285.20:15:09.10#ibcon#about to read 5, iclass 24, count 0 2006.285.20:15:09.10#ibcon#read 5, iclass 24, count 0 2006.285.20:15:09.10#ibcon#about to read 6, iclass 24, count 0 2006.285.20:15:09.10#ibcon#read 6, iclass 24, count 0 2006.285.20:15:09.10#ibcon#end of sib2, iclass 24, count 0 2006.285.20:15:09.10#ibcon#*after write, iclass 24, count 0 2006.285.20:15:09.10#ibcon#*before return 0, iclass 24, count 0 2006.285.20:15:09.10#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:15:09.10#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:15:09.10#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.20:15:09.10#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.20:15:09.10$vck44/vblo=5,709.99 2006.285.20:15:09.10#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.20:15:09.10#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.20:15:09.10#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:09.10#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:15:09.10#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:15:09.10#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:15:09.10#ibcon#enter wrdev, iclass 26, count 0 2006.285.20:15:09.10#ibcon#first serial, iclass 26, count 0 2006.285.20:15:09.10#ibcon#enter sib2, iclass 26, count 0 2006.285.20:15:09.10#ibcon#flushed, iclass 26, count 0 2006.285.20:15:09.10#ibcon#about to write, iclass 26, count 0 2006.285.20:15:09.10#ibcon#wrote, iclass 26, count 0 2006.285.20:15:09.10#ibcon#about to read 3, iclass 26, count 0 2006.285.20:15:09.12#ibcon#read 3, iclass 26, count 0 2006.285.20:15:09.39#ibcon#about to read 4, iclass 26, count 0 2006.285.20:15:09.39#ibcon#read 4, iclass 26, count 0 2006.285.20:15:09.39#ibcon#about to read 5, iclass 26, count 0 2006.285.20:15:09.39#ibcon#read 5, iclass 26, count 0 2006.285.20:15:09.39#ibcon#about to read 6, iclass 26, count 0 2006.285.20:15:09.39#ibcon#read 6, iclass 26, count 0 2006.285.20:15:09.39#ibcon#end of sib2, iclass 26, count 0 2006.285.20:15:09.39#ibcon#*mode == 0, iclass 26, count 0 2006.285.20:15:09.39#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.20:15:09.39#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.20:15:09.39#ibcon#*before write, iclass 26, count 0 2006.285.20:15:09.39#ibcon#enter sib2, iclass 26, count 0 2006.285.20:15:09.39#ibcon#flushed, iclass 26, count 0 2006.285.20:15:09.39#ibcon#about to write, iclass 26, count 0 2006.285.20:15:09.39#ibcon#wrote, iclass 26, count 0 2006.285.20:15:09.39#ibcon#about to read 3, iclass 26, count 0 2006.285.20:15:09.42#ibcon#read 3, iclass 26, count 0 2006.285.20:15:09.42#ibcon#about to read 4, iclass 26, count 0 2006.285.20:15:09.42#ibcon#read 4, iclass 26, count 0 2006.285.20:15:09.42#ibcon#about to read 5, iclass 26, count 0 2006.285.20:15:09.42#ibcon#read 5, iclass 26, count 0 2006.285.20:15:09.42#ibcon#about to read 6, iclass 26, count 0 2006.285.20:15:09.42#ibcon#read 6, iclass 26, count 0 2006.285.20:15:09.42#ibcon#end of sib2, iclass 26, count 0 2006.285.20:15:09.42#ibcon#*after write, iclass 26, count 0 2006.285.20:15:09.42#ibcon#*before return 0, iclass 26, count 0 2006.285.20:15:09.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:15:09.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:15:09.42#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.20:15:09.42#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.20:15:09.42$vck44/vb=5,4 2006.285.20:15:09.42#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.20:15:09.42#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.20:15:09.42#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:09.42#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:15:09.42#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:15:09.42#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:15:09.42#ibcon#enter wrdev, iclass 28, count 2 2006.285.20:15:09.42#ibcon#first serial, iclass 28, count 2 2006.285.20:15:09.42#ibcon#enter sib2, iclass 28, count 2 2006.285.20:15:09.42#ibcon#flushed, iclass 28, count 2 2006.285.20:15:09.42#ibcon#about to write, iclass 28, count 2 2006.285.20:15:09.42#ibcon#wrote, iclass 28, count 2 2006.285.20:15:09.42#ibcon#about to read 3, iclass 28, count 2 2006.285.20:15:09.44#ibcon#read 3, iclass 28, count 2 2006.285.20:15:09.44#ibcon#about to read 4, iclass 28, count 2 2006.285.20:15:09.44#ibcon#read 4, iclass 28, count 2 2006.285.20:15:09.44#ibcon#about to read 5, iclass 28, count 2 2006.285.20:15:09.44#ibcon#read 5, iclass 28, count 2 2006.285.20:15:09.44#ibcon#about to read 6, iclass 28, count 2 2006.285.20:15:09.44#ibcon#read 6, iclass 28, count 2 2006.285.20:15:09.44#ibcon#end of sib2, iclass 28, count 2 2006.285.20:15:09.44#ibcon#*mode == 0, iclass 28, count 2 2006.285.20:15:09.44#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.20:15:09.44#ibcon#[27=AT05-04\r\n] 2006.285.20:15:09.44#ibcon#*before write, iclass 28, count 2 2006.285.20:15:09.44#ibcon#enter sib2, iclass 28, count 2 2006.285.20:15:09.44#ibcon#flushed, iclass 28, count 2 2006.285.20:15:09.44#ibcon#about to write, iclass 28, count 2 2006.285.20:15:09.44#ibcon#wrote, iclass 28, count 2 2006.285.20:15:09.44#ibcon#about to read 3, iclass 28, count 2 2006.285.20:15:09.47#ibcon#read 3, iclass 28, count 2 2006.285.20:15:09.47#ibcon#about to read 4, iclass 28, count 2 2006.285.20:15:09.47#ibcon#read 4, iclass 28, count 2 2006.285.20:15:09.47#ibcon#about to read 5, iclass 28, count 2 2006.285.20:15:09.47#ibcon#read 5, iclass 28, count 2 2006.285.20:15:09.47#ibcon#about to read 6, iclass 28, count 2 2006.285.20:15:09.47#ibcon#read 6, iclass 28, count 2 2006.285.20:15:09.47#ibcon#end of sib2, iclass 28, count 2 2006.285.20:15:09.47#ibcon#*after write, iclass 28, count 2 2006.285.20:15:09.47#ibcon#*before return 0, iclass 28, count 2 2006.285.20:15:09.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:15:09.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:15:09.47#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.20:15:09.47#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:09.47#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:15:09.59#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:15:09.59#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:15:09.59#ibcon#enter wrdev, iclass 28, count 0 2006.285.20:15:09.59#ibcon#first serial, iclass 28, count 0 2006.285.20:15:09.59#ibcon#enter sib2, iclass 28, count 0 2006.285.20:15:09.59#ibcon#flushed, iclass 28, count 0 2006.285.20:15:09.59#ibcon#about to write, iclass 28, count 0 2006.285.20:15:09.59#ibcon#wrote, iclass 28, count 0 2006.285.20:15:09.59#ibcon#about to read 3, iclass 28, count 0 2006.285.20:15:09.61#ibcon#read 3, iclass 28, count 0 2006.285.20:15:09.61#ibcon#about to read 4, iclass 28, count 0 2006.285.20:15:09.61#ibcon#read 4, iclass 28, count 0 2006.285.20:15:09.61#ibcon#about to read 5, iclass 28, count 0 2006.285.20:15:09.61#ibcon#read 5, iclass 28, count 0 2006.285.20:15:09.61#ibcon#about to read 6, iclass 28, count 0 2006.285.20:15:09.61#ibcon#read 6, iclass 28, count 0 2006.285.20:15:09.61#ibcon#end of sib2, iclass 28, count 0 2006.285.20:15:09.61#ibcon#*mode == 0, iclass 28, count 0 2006.285.20:15:09.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.20:15:09.61#ibcon#[27=USB\r\n] 2006.285.20:15:09.61#ibcon#*before write, iclass 28, count 0 2006.285.20:15:09.61#ibcon#enter sib2, iclass 28, count 0 2006.285.20:15:09.61#ibcon#flushed, iclass 28, count 0 2006.285.20:15:09.61#ibcon#about to write, iclass 28, count 0 2006.285.20:15:09.61#ibcon#wrote, iclass 28, count 0 2006.285.20:15:09.61#ibcon#about to read 3, iclass 28, count 0 2006.285.20:15:09.64#ibcon#read 3, iclass 28, count 0 2006.285.20:15:09.64#ibcon#about to read 4, iclass 28, count 0 2006.285.20:15:09.64#ibcon#read 4, iclass 28, count 0 2006.285.20:15:09.64#ibcon#about to read 5, iclass 28, count 0 2006.285.20:15:09.64#ibcon#read 5, iclass 28, count 0 2006.285.20:15:09.64#ibcon#about to read 6, iclass 28, count 0 2006.285.20:15:09.64#ibcon#read 6, iclass 28, count 0 2006.285.20:15:09.64#ibcon#end of sib2, iclass 28, count 0 2006.285.20:15:09.64#ibcon#*after write, iclass 28, count 0 2006.285.20:15:09.64#ibcon#*before return 0, iclass 28, count 0 2006.285.20:15:09.64#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:15:09.64#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:15:09.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.20:15:09.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.20:15:09.64$vck44/vblo=6,719.99 2006.285.20:15:09.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.20:15:09.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.20:15:09.64#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:09.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:15:09.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:15:09.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:15:09.64#ibcon#enter wrdev, iclass 30, count 0 2006.285.20:15:09.64#ibcon#first serial, iclass 30, count 0 2006.285.20:15:09.64#ibcon#enter sib2, iclass 30, count 0 2006.285.20:15:09.64#ibcon#flushed, iclass 30, count 0 2006.285.20:15:09.64#ibcon#about to write, iclass 30, count 0 2006.285.20:15:09.64#ibcon#wrote, iclass 30, count 0 2006.285.20:15:09.64#ibcon#about to read 3, iclass 30, count 0 2006.285.20:15:09.66#ibcon#read 3, iclass 30, count 0 2006.285.20:15:09.66#ibcon#about to read 4, iclass 30, count 0 2006.285.20:15:09.66#ibcon#read 4, iclass 30, count 0 2006.285.20:15:09.66#ibcon#about to read 5, iclass 30, count 0 2006.285.20:15:09.66#ibcon#read 5, iclass 30, count 0 2006.285.20:15:09.66#ibcon#about to read 6, iclass 30, count 0 2006.285.20:15:09.66#ibcon#read 6, iclass 30, count 0 2006.285.20:15:09.66#ibcon#end of sib2, iclass 30, count 0 2006.285.20:15:09.66#ibcon#*mode == 0, iclass 30, count 0 2006.285.20:15:09.66#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.20:15:09.66#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.20:15:09.66#ibcon#*before write, iclass 30, count 0 2006.285.20:15:09.66#ibcon#enter sib2, iclass 30, count 0 2006.285.20:15:09.66#ibcon#flushed, iclass 30, count 0 2006.285.20:15:09.66#ibcon#about to write, iclass 30, count 0 2006.285.20:15:09.66#ibcon#wrote, iclass 30, count 0 2006.285.20:15:09.66#ibcon#about to read 3, iclass 30, count 0 2006.285.20:15:09.70#ibcon#read 3, iclass 30, count 0 2006.285.20:15:09.70#ibcon#about to read 4, iclass 30, count 0 2006.285.20:15:09.70#ibcon#read 4, iclass 30, count 0 2006.285.20:15:09.70#ibcon#about to read 5, iclass 30, count 0 2006.285.20:15:09.70#ibcon#read 5, iclass 30, count 0 2006.285.20:15:09.70#ibcon#about to read 6, iclass 30, count 0 2006.285.20:15:09.70#ibcon#read 6, iclass 30, count 0 2006.285.20:15:09.70#ibcon#end of sib2, iclass 30, count 0 2006.285.20:15:09.70#ibcon#*after write, iclass 30, count 0 2006.285.20:15:09.70#ibcon#*before return 0, iclass 30, count 0 2006.285.20:15:09.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:15:09.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:15:09.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.20:15:09.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.20:15:09.70$vck44/vb=6,3 2006.285.20:15:09.70#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.20:15:09.70#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.20:15:09.70#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:09.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:15:09.76#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:15:09.76#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:15:09.76#ibcon#enter wrdev, iclass 32, count 2 2006.285.20:15:09.76#ibcon#first serial, iclass 32, count 2 2006.285.20:15:09.76#ibcon#enter sib2, iclass 32, count 2 2006.285.20:15:09.76#ibcon#flushed, iclass 32, count 2 2006.285.20:15:09.76#ibcon#about to write, iclass 32, count 2 2006.285.20:15:09.76#ibcon#wrote, iclass 32, count 2 2006.285.20:15:09.76#ibcon#about to read 3, iclass 32, count 2 2006.285.20:15:09.78#ibcon#read 3, iclass 32, count 2 2006.285.20:15:09.78#ibcon#about to read 4, iclass 32, count 2 2006.285.20:15:09.78#ibcon#read 4, iclass 32, count 2 2006.285.20:15:09.78#ibcon#about to read 5, iclass 32, count 2 2006.285.20:15:09.78#ibcon#read 5, iclass 32, count 2 2006.285.20:15:09.78#ibcon#about to read 6, iclass 32, count 2 2006.285.20:15:09.78#ibcon#read 6, iclass 32, count 2 2006.285.20:15:09.78#ibcon#end of sib2, iclass 32, count 2 2006.285.20:15:09.78#ibcon#*mode == 0, iclass 32, count 2 2006.285.20:15:09.78#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.20:15:09.78#ibcon#[27=AT06-03\r\n] 2006.285.20:15:09.78#ibcon#*before write, iclass 32, count 2 2006.285.20:15:09.78#ibcon#enter sib2, iclass 32, count 2 2006.285.20:15:09.78#ibcon#flushed, iclass 32, count 2 2006.285.20:15:09.78#ibcon#about to write, iclass 32, count 2 2006.285.20:15:09.78#ibcon#wrote, iclass 32, count 2 2006.285.20:15:09.78#ibcon#about to read 3, iclass 32, count 2 2006.285.20:15:09.81#ibcon#read 3, iclass 32, count 2 2006.285.20:15:09.81#ibcon#about to read 4, iclass 32, count 2 2006.285.20:15:09.81#ibcon#read 4, iclass 32, count 2 2006.285.20:15:09.81#ibcon#about to read 5, iclass 32, count 2 2006.285.20:15:09.81#ibcon#read 5, iclass 32, count 2 2006.285.20:15:09.81#ibcon#about to read 6, iclass 32, count 2 2006.285.20:15:09.81#ibcon#read 6, iclass 32, count 2 2006.285.20:15:09.81#ibcon#end of sib2, iclass 32, count 2 2006.285.20:15:09.81#ibcon#*after write, iclass 32, count 2 2006.285.20:15:09.81#ibcon#*before return 0, iclass 32, count 2 2006.285.20:15:09.81#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:15:09.81#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:15:09.81#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.20:15:09.81#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:09.81#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:15:09.93#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:15:09.93#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:15:09.93#ibcon#enter wrdev, iclass 32, count 0 2006.285.20:15:09.93#ibcon#first serial, iclass 32, count 0 2006.285.20:15:09.93#ibcon#enter sib2, iclass 32, count 0 2006.285.20:15:09.93#ibcon#flushed, iclass 32, count 0 2006.285.20:15:09.93#ibcon#about to write, iclass 32, count 0 2006.285.20:15:09.93#ibcon#wrote, iclass 32, count 0 2006.285.20:15:09.93#ibcon#about to read 3, iclass 32, count 0 2006.285.20:15:09.95#ibcon#read 3, iclass 32, count 0 2006.285.20:15:09.95#ibcon#about to read 4, iclass 32, count 0 2006.285.20:15:09.95#ibcon#read 4, iclass 32, count 0 2006.285.20:15:09.95#ibcon#about to read 5, iclass 32, count 0 2006.285.20:15:09.95#ibcon#read 5, iclass 32, count 0 2006.285.20:15:09.95#ibcon#about to read 6, iclass 32, count 0 2006.285.20:15:09.95#ibcon#read 6, iclass 32, count 0 2006.285.20:15:09.95#ibcon#end of sib2, iclass 32, count 0 2006.285.20:15:09.95#ibcon#*mode == 0, iclass 32, count 0 2006.285.20:15:09.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.20:15:09.95#ibcon#[27=USB\r\n] 2006.285.20:15:09.95#ibcon#*before write, iclass 32, count 0 2006.285.20:15:09.95#ibcon#enter sib2, iclass 32, count 0 2006.285.20:15:09.95#ibcon#flushed, iclass 32, count 0 2006.285.20:15:09.95#ibcon#about to write, iclass 32, count 0 2006.285.20:15:09.95#ibcon#wrote, iclass 32, count 0 2006.285.20:15:09.95#ibcon#about to read 3, iclass 32, count 0 2006.285.20:15:09.98#ibcon#read 3, iclass 32, count 0 2006.285.20:15:09.98#ibcon#about to read 4, iclass 32, count 0 2006.285.20:15:09.98#ibcon#read 4, iclass 32, count 0 2006.285.20:15:09.98#ibcon#about to read 5, iclass 32, count 0 2006.285.20:15:09.98#ibcon#read 5, iclass 32, count 0 2006.285.20:15:09.98#ibcon#about to read 6, iclass 32, count 0 2006.285.20:15:09.98#ibcon#read 6, iclass 32, count 0 2006.285.20:15:09.98#ibcon#end of sib2, iclass 32, count 0 2006.285.20:15:09.98#ibcon#*after write, iclass 32, count 0 2006.285.20:15:09.98#ibcon#*before return 0, iclass 32, count 0 2006.285.20:15:09.98#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:15:09.98#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:15:09.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.20:15:09.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.20:15:09.98$vck44/vblo=7,734.99 2006.285.20:15:09.98#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.20:15:09.98#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.20:15:09.98#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:09.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:15:09.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:15:09.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:15:09.98#ibcon#enter wrdev, iclass 34, count 0 2006.285.20:15:09.98#ibcon#first serial, iclass 34, count 0 2006.285.20:15:09.98#ibcon#enter sib2, iclass 34, count 0 2006.285.20:15:09.98#ibcon#flushed, iclass 34, count 0 2006.285.20:15:09.98#ibcon#about to write, iclass 34, count 0 2006.285.20:15:09.98#ibcon#wrote, iclass 34, count 0 2006.285.20:15:09.98#ibcon#about to read 3, iclass 34, count 0 2006.285.20:15:10.00#ibcon#read 3, iclass 34, count 0 2006.285.20:15:10.00#ibcon#about to read 4, iclass 34, count 0 2006.285.20:15:10.00#ibcon#read 4, iclass 34, count 0 2006.285.20:15:10.00#ibcon#about to read 5, iclass 34, count 0 2006.285.20:15:10.00#ibcon#read 5, iclass 34, count 0 2006.285.20:15:10.00#ibcon#about to read 6, iclass 34, count 0 2006.285.20:15:10.00#ibcon#read 6, iclass 34, count 0 2006.285.20:15:10.00#ibcon#end of sib2, iclass 34, count 0 2006.285.20:15:10.00#ibcon#*mode == 0, iclass 34, count 0 2006.285.20:15:10.00#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.20:15:10.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.20:15:10.00#ibcon#*before write, iclass 34, count 0 2006.285.20:15:10.00#ibcon#enter sib2, iclass 34, count 0 2006.285.20:15:10.00#ibcon#flushed, iclass 34, count 0 2006.285.20:15:10.00#ibcon#about to write, iclass 34, count 0 2006.285.20:15:10.00#ibcon#wrote, iclass 34, count 0 2006.285.20:15:10.00#ibcon#about to read 3, iclass 34, count 0 2006.285.20:15:10.04#ibcon#read 3, iclass 34, count 0 2006.285.20:15:10.04#ibcon#about to read 4, iclass 34, count 0 2006.285.20:15:10.04#ibcon#read 4, iclass 34, count 0 2006.285.20:15:10.04#ibcon#about to read 5, iclass 34, count 0 2006.285.20:15:10.04#ibcon#read 5, iclass 34, count 0 2006.285.20:15:10.04#ibcon#about to read 6, iclass 34, count 0 2006.285.20:15:10.04#ibcon#read 6, iclass 34, count 0 2006.285.20:15:10.04#ibcon#end of sib2, iclass 34, count 0 2006.285.20:15:10.04#ibcon#*after write, iclass 34, count 0 2006.285.20:15:10.04#ibcon#*before return 0, iclass 34, count 0 2006.285.20:15:10.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:15:10.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:15:10.04#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.20:15:10.04#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.20:15:10.04$vck44/vb=7,4 2006.285.20:15:10.04#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.20:15:10.04#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.20:15:10.04#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:10.04#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:15:10.10#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:15:10.10#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:15:10.10#ibcon#enter wrdev, iclass 36, count 2 2006.285.20:15:10.10#ibcon#first serial, iclass 36, count 2 2006.285.20:15:10.10#ibcon#enter sib2, iclass 36, count 2 2006.285.20:15:10.10#ibcon#flushed, iclass 36, count 2 2006.285.20:15:10.10#ibcon#about to write, iclass 36, count 2 2006.285.20:15:10.10#ibcon#wrote, iclass 36, count 2 2006.285.20:15:10.10#ibcon#about to read 3, iclass 36, count 2 2006.285.20:15:10.12#ibcon#read 3, iclass 36, count 2 2006.285.20:15:10.12#ibcon#about to read 4, iclass 36, count 2 2006.285.20:15:10.12#ibcon#read 4, iclass 36, count 2 2006.285.20:15:10.12#ibcon#about to read 5, iclass 36, count 2 2006.285.20:15:10.12#ibcon#read 5, iclass 36, count 2 2006.285.20:15:10.12#ibcon#about to read 6, iclass 36, count 2 2006.285.20:15:10.12#ibcon#read 6, iclass 36, count 2 2006.285.20:15:10.12#ibcon#end of sib2, iclass 36, count 2 2006.285.20:15:10.12#ibcon#*mode == 0, iclass 36, count 2 2006.285.20:15:10.12#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.20:15:10.12#ibcon#[27=AT07-04\r\n] 2006.285.20:15:10.12#ibcon#*before write, iclass 36, count 2 2006.285.20:15:10.12#ibcon#enter sib2, iclass 36, count 2 2006.285.20:15:10.12#ibcon#flushed, iclass 36, count 2 2006.285.20:15:10.12#ibcon#about to write, iclass 36, count 2 2006.285.20:15:10.12#ibcon#wrote, iclass 36, count 2 2006.285.20:15:10.12#ibcon#about to read 3, iclass 36, count 2 2006.285.20:15:10.15#ibcon#read 3, iclass 36, count 2 2006.285.20:15:10.15#ibcon#about to read 4, iclass 36, count 2 2006.285.20:15:10.15#ibcon#read 4, iclass 36, count 2 2006.285.20:15:10.15#ibcon#about to read 5, iclass 36, count 2 2006.285.20:15:10.15#ibcon#read 5, iclass 36, count 2 2006.285.20:15:10.15#ibcon#about to read 6, iclass 36, count 2 2006.285.20:15:10.15#ibcon#read 6, iclass 36, count 2 2006.285.20:15:10.15#ibcon#end of sib2, iclass 36, count 2 2006.285.20:15:10.15#ibcon#*after write, iclass 36, count 2 2006.285.20:15:10.15#ibcon#*before return 0, iclass 36, count 2 2006.285.20:15:10.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:15:10.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:15:10.15#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.20:15:10.15#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:10.15#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:15:10.27#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:15:10.28#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:15:10.28#ibcon#enter wrdev, iclass 36, count 0 2006.285.20:15:10.28#ibcon#first serial, iclass 36, count 0 2006.285.20:15:10.28#ibcon#enter sib2, iclass 36, count 0 2006.285.20:15:10.28#ibcon#flushed, iclass 36, count 0 2006.285.20:15:10.28#ibcon#about to write, iclass 36, count 0 2006.285.20:15:10.28#ibcon#wrote, iclass 36, count 0 2006.285.20:15:10.28#ibcon#about to read 3, iclass 36, count 0 2006.285.20:15:10.29#ibcon#read 3, iclass 36, count 0 2006.285.20:15:10.29#ibcon#about to read 4, iclass 36, count 0 2006.285.20:15:10.29#ibcon#read 4, iclass 36, count 0 2006.285.20:15:10.29#ibcon#about to read 5, iclass 36, count 0 2006.285.20:15:10.29#ibcon#read 5, iclass 36, count 0 2006.285.20:15:10.29#ibcon#about to read 6, iclass 36, count 0 2006.285.20:15:10.29#ibcon#read 6, iclass 36, count 0 2006.285.20:15:10.29#ibcon#end of sib2, iclass 36, count 0 2006.285.20:15:10.29#ibcon#*mode == 0, iclass 36, count 0 2006.285.20:15:10.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.20:15:10.29#ibcon#[27=USB\r\n] 2006.285.20:15:10.29#ibcon#*before write, iclass 36, count 0 2006.285.20:15:10.29#ibcon#enter sib2, iclass 36, count 0 2006.285.20:15:10.29#ibcon#flushed, iclass 36, count 0 2006.285.20:15:10.29#ibcon#about to write, iclass 36, count 0 2006.285.20:15:10.29#ibcon#wrote, iclass 36, count 0 2006.285.20:15:10.29#ibcon#about to read 3, iclass 36, count 0 2006.285.20:15:10.32#ibcon#read 3, iclass 36, count 0 2006.285.20:15:10.32#ibcon#about to read 4, iclass 36, count 0 2006.285.20:15:10.32#ibcon#read 4, iclass 36, count 0 2006.285.20:15:10.32#ibcon#about to read 5, iclass 36, count 0 2006.285.20:15:10.32#ibcon#read 5, iclass 36, count 0 2006.285.20:15:10.32#ibcon#about to read 6, iclass 36, count 0 2006.285.20:15:10.32#ibcon#read 6, iclass 36, count 0 2006.285.20:15:10.32#ibcon#end of sib2, iclass 36, count 0 2006.285.20:15:10.32#ibcon#*after write, iclass 36, count 0 2006.285.20:15:10.32#ibcon#*before return 0, iclass 36, count 0 2006.285.20:15:10.32#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:15:10.32#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:15:10.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.20:15:10.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.20:15:10.32$vck44/vblo=8,744.99 2006.285.20:15:10.32#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.20:15:10.32#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.20:15:10.32#ibcon#ireg 17 cls_cnt 0 2006.285.20:15:10.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:15:10.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:15:10.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:15:10.32#ibcon#enter wrdev, iclass 38, count 0 2006.285.20:15:10.32#ibcon#first serial, iclass 38, count 0 2006.285.20:15:10.32#ibcon#enter sib2, iclass 38, count 0 2006.285.20:15:10.32#ibcon#flushed, iclass 38, count 0 2006.285.20:15:10.32#ibcon#about to write, iclass 38, count 0 2006.285.20:15:10.32#ibcon#wrote, iclass 38, count 0 2006.285.20:15:10.32#ibcon#about to read 3, iclass 38, count 0 2006.285.20:15:10.34#ibcon#read 3, iclass 38, count 0 2006.285.20:15:10.34#ibcon#about to read 4, iclass 38, count 0 2006.285.20:15:10.34#ibcon#read 4, iclass 38, count 0 2006.285.20:15:10.34#ibcon#about to read 5, iclass 38, count 0 2006.285.20:15:10.34#ibcon#read 5, iclass 38, count 0 2006.285.20:15:10.34#ibcon#about to read 6, iclass 38, count 0 2006.285.20:15:10.34#ibcon#read 6, iclass 38, count 0 2006.285.20:15:10.34#ibcon#end of sib2, iclass 38, count 0 2006.285.20:15:10.34#ibcon#*mode == 0, iclass 38, count 0 2006.285.20:15:10.34#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.20:15:10.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.20:15:10.34#ibcon#*before write, iclass 38, count 0 2006.285.20:15:10.34#ibcon#enter sib2, iclass 38, count 0 2006.285.20:15:10.34#ibcon#flushed, iclass 38, count 0 2006.285.20:15:10.34#ibcon#about to write, iclass 38, count 0 2006.285.20:15:10.34#ibcon#wrote, iclass 38, count 0 2006.285.20:15:10.34#ibcon#about to read 3, iclass 38, count 0 2006.285.20:15:10.38#ibcon#read 3, iclass 38, count 0 2006.285.20:15:10.38#ibcon#about to read 4, iclass 38, count 0 2006.285.20:15:10.38#ibcon#read 4, iclass 38, count 0 2006.285.20:15:10.38#ibcon#about to read 5, iclass 38, count 0 2006.285.20:15:10.38#ibcon#read 5, iclass 38, count 0 2006.285.20:15:10.38#ibcon#about to read 6, iclass 38, count 0 2006.285.20:15:10.38#ibcon#read 6, iclass 38, count 0 2006.285.20:15:10.38#ibcon#end of sib2, iclass 38, count 0 2006.285.20:15:10.38#ibcon#*after write, iclass 38, count 0 2006.285.20:15:10.38#ibcon#*before return 0, iclass 38, count 0 2006.285.20:15:10.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:15:10.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:15:10.38#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.20:15:10.38#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.20:15:10.38$vck44/vb=8,4 2006.285.20:15:10.38#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.20:15:10.38#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.20:15:10.38#ibcon#ireg 11 cls_cnt 2 2006.285.20:15:10.38#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:15:10.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:15:10.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:15:10.44#ibcon#enter wrdev, iclass 40, count 2 2006.285.20:15:10.44#ibcon#first serial, iclass 40, count 2 2006.285.20:15:10.44#ibcon#enter sib2, iclass 40, count 2 2006.285.20:15:10.44#ibcon#flushed, iclass 40, count 2 2006.285.20:15:10.44#ibcon#about to write, iclass 40, count 2 2006.285.20:15:10.44#ibcon#wrote, iclass 40, count 2 2006.285.20:15:10.44#ibcon#about to read 3, iclass 40, count 2 2006.285.20:15:10.46#ibcon#read 3, iclass 40, count 2 2006.285.20:15:10.46#ibcon#about to read 4, iclass 40, count 2 2006.285.20:15:10.46#ibcon#read 4, iclass 40, count 2 2006.285.20:15:10.46#ibcon#about to read 5, iclass 40, count 2 2006.285.20:15:10.46#ibcon#read 5, iclass 40, count 2 2006.285.20:15:10.46#ibcon#about to read 6, iclass 40, count 2 2006.285.20:15:10.46#ibcon#read 6, iclass 40, count 2 2006.285.20:15:10.46#ibcon#end of sib2, iclass 40, count 2 2006.285.20:15:10.46#ibcon#*mode == 0, iclass 40, count 2 2006.285.20:15:10.46#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.20:15:10.46#ibcon#[27=AT08-04\r\n] 2006.285.20:15:10.46#ibcon#*before write, iclass 40, count 2 2006.285.20:15:10.46#ibcon#enter sib2, iclass 40, count 2 2006.285.20:15:10.46#ibcon#flushed, iclass 40, count 2 2006.285.20:15:10.46#ibcon#about to write, iclass 40, count 2 2006.285.20:15:10.46#ibcon#wrote, iclass 40, count 2 2006.285.20:15:10.46#ibcon#about to read 3, iclass 40, count 2 2006.285.20:15:10.49#ibcon#read 3, iclass 40, count 2 2006.285.20:15:10.49#ibcon#about to read 4, iclass 40, count 2 2006.285.20:15:10.49#ibcon#read 4, iclass 40, count 2 2006.285.20:15:10.49#ibcon#about to read 5, iclass 40, count 2 2006.285.20:15:10.49#ibcon#read 5, iclass 40, count 2 2006.285.20:15:10.49#ibcon#about to read 6, iclass 40, count 2 2006.285.20:15:10.49#ibcon#read 6, iclass 40, count 2 2006.285.20:15:10.49#ibcon#end of sib2, iclass 40, count 2 2006.285.20:15:10.49#ibcon#*after write, iclass 40, count 2 2006.285.20:15:10.49#ibcon#*before return 0, iclass 40, count 2 2006.285.20:15:10.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:15:10.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:15:10.49#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.20:15:10.49#ibcon#ireg 7 cls_cnt 0 2006.285.20:15:10.49#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:15:10.61#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:15:10.61#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:15:10.61#ibcon#enter wrdev, iclass 40, count 0 2006.285.20:15:10.61#ibcon#first serial, iclass 40, count 0 2006.285.20:15:10.61#ibcon#enter sib2, iclass 40, count 0 2006.285.20:15:10.61#ibcon#flushed, iclass 40, count 0 2006.285.20:15:10.61#ibcon#about to write, iclass 40, count 0 2006.285.20:15:10.61#ibcon#wrote, iclass 40, count 0 2006.285.20:15:10.61#ibcon#about to read 3, iclass 40, count 0 2006.285.20:15:10.63#ibcon#read 3, iclass 40, count 0 2006.285.20:15:10.63#ibcon#about to read 4, iclass 40, count 0 2006.285.20:15:10.63#ibcon#read 4, iclass 40, count 0 2006.285.20:15:10.63#ibcon#about to read 5, iclass 40, count 0 2006.285.20:15:10.63#ibcon#read 5, iclass 40, count 0 2006.285.20:15:10.63#ibcon#about to read 6, iclass 40, count 0 2006.285.20:15:10.63#ibcon#read 6, iclass 40, count 0 2006.285.20:15:10.63#ibcon#end of sib2, iclass 40, count 0 2006.285.20:15:10.63#ibcon#*mode == 0, iclass 40, count 0 2006.285.20:15:10.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.20:15:10.63#ibcon#[27=USB\r\n] 2006.285.20:15:10.63#ibcon#*before write, iclass 40, count 0 2006.285.20:15:10.63#ibcon#enter sib2, iclass 40, count 0 2006.285.20:15:10.63#ibcon#flushed, iclass 40, count 0 2006.285.20:15:10.63#ibcon#about to write, iclass 40, count 0 2006.285.20:15:10.63#ibcon#wrote, iclass 40, count 0 2006.285.20:15:10.63#ibcon#about to read 3, iclass 40, count 0 2006.285.20:15:10.66#ibcon#read 3, iclass 40, count 0 2006.285.20:15:10.66#ibcon#about to read 4, iclass 40, count 0 2006.285.20:15:10.66#ibcon#read 4, iclass 40, count 0 2006.285.20:15:10.66#ibcon#about to read 5, iclass 40, count 0 2006.285.20:15:10.66#ibcon#read 5, iclass 40, count 0 2006.285.20:15:10.66#ibcon#about to read 6, iclass 40, count 0 2006.285.20:15:10.66#ibcon#read 6, iclass 40, count 0 2006.285.20:15:10.66#ibcon#end of sib2, iclass 40, count 0 2006.285.20:15:10.66#ibcon#*after write, iclass 40, count 0 2006.285.20:15:10.66#ibcon#*before return 0, iclass 40, count 0 2006.285.20:15:10.66#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:15:10.66#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:15:10.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.20:15:10.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.20:15:10.66$vck44/vabw=wide 2006.285.20:15:10.66#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.20:15:10.66#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.20:15:10.66#ibcon#ireg 8 cls_cnt 0 2006.285.20:15:10.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:15:10.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:15:10.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:15:10.66#ibcon#enter wrdev, iclass 4, count 0 2006.285.20:15:10.66#ibcon#first serial, iclass 4, count 0 2006.285.20:15:10.66#ibcon#enter sib2, iclass 4, count 0 2006.285.20:15:10.66#ibcon#flushed, iclass 4, count 0 2006.285.20:15:10.66#ibcon#about to write, iclass 4, count 0 2006.285.20:15:10.66#ibcon#wrote, iclass 4, count 0 2006.285.20:15:10.66#ibcon#about to read 3, iclass 4, count 0 2006.285.20:15:10.68#ibcon#read 3, iclass 4, count 0 2006.285.20:15:10.68#ibcon#about to read 4, iclass 4, count 0 2006.285.20:15:10.68#ibcon#read 4, iclass 4, count 0 2006.285.20:15:10.68#ibcon#about to read 5, iclass 4, count 0 2006.285.20:15:10.68#ibcon#read 5, iclass 4, count 0 2006.285.20:15:10.68#ibcon#about to read 6, iclass 4, count 0 2006.285.20:15:10.68#ibcon#read 6, iclass 4, count 0 2006.285.20:15:10.68#ibcon#end of sib2, iclass 4, count 0 2006.285.20:15:10.68#ibcon#*mode == 0, iclass 4, count 0 2006.285.20:15:10.68#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.20:15:10.68#ibcon#[25=BW32\r\n] 2006.285.20:15:10.68#ibcon#*before write, iclass 4, count 0 2006.285.20:15:10.68#ibcon#enter sib2, iclass 4, count 0 2006.285.20:15:10.68#ibcon#flushed, iclass 4, count 0 2006.285.20:15:10.68#ibcon#about to write, iclass 4, count 0 2006.285.20:15:10.68#ibcon#wrote, iclass 4, count 0 2006.285.20:15:10.68#ibcon#about to read 3, iclass 4, count 0 2006.285.20:15:10.71#ibcon#read 3, iclass 4, count 0 2006.285.20:15:10.71#ibcon#about to read 4, iclass 4, count 0 2006.285.20:15:10.71#ibcon#read 4, iclass 4, count 0 2006.285.20:15:10.71#ibcon#about to read 5, iclass 4, count 0 2006.285.20:15:10.71#ibcon#read 5, iclass 4, count 0 2006.285.20:15:10.71#ibcon#about to read 6, iclass 4, count 0 2006.285.20:15:10.71#ibcon#read 6, iclass 4, count 0 2006.285.20:15:10.71#ibcon#end of sib2, iclass 4, count 0 2006.285.20:15:10.71#ibcon#*after write, iclass 4, count 0 2006.285.20:15:10.71#ibcon#*before return 0, iclass 4, count 0 2006.285.20:15:10.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:15:10.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:15:10.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.20:15:10.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.20:15:10.71$vck44/vbbw=wide 2006.285.20:15:10.71#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.20:15:10.71#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.20:15:10.71#ibcon#ireg 8 cls_cnt 0 2006.285.20:15:10.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:15:10.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:15:10.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:15:10.78#ibcon#enter wrdev, iclass 6, count 0 2006.285.20:15:10.78#ibcon#first serial, iclass 6, count 0 2006.285.20:15:10.78#ibcon#enter sib2, iclass 6, count 0 2006.285.20:15:10.78#ibcon#flushed, iclass 6, count 0 2006.285.20:15:10.78#ibcon#about to write, iclass 6, count 0 2006.285.20:15:10.78#ibcon#wrote, iclass 6, count 0 2006.285.20:15:10.78#ibcon#about to read 3, iclass 6, count 0 2006.285.20:15:10.80#ibcon#read 3, iclass 6, count 0 2006.285.20:15:10.80#ibcon#about to read 4, iclass 6, count 0 2006.285.20:15:10.80#ibcon#read 4, iclass 6, count 0 2006.285.20:15:10.80#ibcon#about to read 5, iclass 6, count 0 2006.285.20:15:10.80#ibcon#read 5, iclass 6, count 0 2006.285.20:15:10.80#ibcon#about to read 6, iclass 6, count 0 2006.285.20:15:10.80#ibcon#read 6, iclass 6, count 0 2006.285.20:15:10.80#ibcon#end of sib2, iclass 6, count 0 2006.285.20:15:10.80#ibcon#*mode == 0, iclass 6, count 0 2006.285.20:15:10.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.20:15:10.80#ibcon#[27=BW32\r\n] 2006.285.20:15:10.80#ibcon#*before write, iclass 6, count 0 2006.285.20:15:10.80#ibcon#enter sib2, iclass 6, count 0 2006.285.20:15:10.80#ibcon#flushed, iclass 6, count 0 2006.285.20:15:10.80#ibcon#about to write, iclass 6, count 0 2006.285.20:15:10.80#ibcon#wrote, iclass 6, count 0 2006.285.20:15:10.80#ibcon#about to read 3, iclass 6, count 0 2006.285.20:15:10.83#ibcon#read 3, iclass 6, count 0 2006.285.20:15:10.83#ibcon#about to read 4, iclass 6, count 0 2006.285.20:15:10.83#ibcon#read 4, iclass 6, count 0 2006.285.20:15:10.83#ibcon#about to read 5, iclass 6, count 0 2006.285.20:15:10.83#ibcon#read 5, iclass 6, count 0 2006.285.20:15:10.83#ibcon#about to read 6, iclass 6, count 0 2006.285.20:15:10.83#ibcon#read 6, iclass 6, count 0 2006.285.20:15:10.83#ibcon#end of sib2, iclass 6, count 0 2006.285.20:15:10.83#ibcon#*after write, iclass 6, count 0 2006.285.20:15:10.83#ibcon#*before return 0, iclass 6, count 0 2006.285.20:15:10.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:15:10.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:15:10.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.20:15:10.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.20:15:10.83$setupk4/ifdk4 2006.285.20:15:10.83$ifdk4/lo= 2006.285.20:15:10.83$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.20:15:10.83$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.20:15:10.83$ifdk4/patch= 2006.285.20:15:10.83$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.20:15:10.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.20:15:10.83$setupk4/!*+20s 2006.285.20:15:13.97#abcon#<5=/07 0.4 1.2 14.491001015.3\r\n> 2006.285.20:15:13.99#abcon#{5=INTERFACE CLEAR} 2006.285.20:15:14.05#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:15:24.14#abcon#<5=/06 0.4 1.2 14.491001015.3\r\n> 2006.285.20:15:24.16#abcon#{5=INTERFACE CLEAR} 2006.285.20:15:24.22#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:15:24.32$setupk4/"tpicd 2006.285.20:15:24.32$setupk4/echo=off 2006.285.20:15:24.32$setupk4/xlog=off 2006.285.20:15:24.32:!2006.285.20:22:21 2006.285.20:15:42.14#trakl#Source acquired 2006.285.20:15:43.14#flagr#flagr/antenna,acquired 2006.285.20:22:21.00:preob 2006.285.20:22:21.14/onsource/TRACKING 2006.285.20:22:21.14:!2006.285.20:22:31 2006.285.20:22:31.00:"tape 2006.285.20:22:31.00:"st=record 2006.285.20:22:31.00:data_valid=on 2006.285.20:22:31.00:midob 2006.285.20:22:31.14/onsource/TRACKING 2006.285.20:22:31.14/wx/14.46,1015.3,100 2006.285.20:22:31.30/cable/+6.5087E-03 2006.285.20:22:32.39/va/01,07,usb,yes,32,35 2006.285.20:22:32.39/va/02,06,usb,yes,33,33 2006.285.20:22:32.39/va/03,07,usb,yes,32,34 2006.285.20:22:32.39/va/04,06,usb,yes,34,35 2006.285.20:22:32.39/va/05,03,usb,yes,33,33 2006.285.20:22:32.39/va/06,04,usb,yes,30,29 2006.285.20:22:32.39/va/07,04,usb,yes,30,31 2006.285.20:22:32.39/va/08,03,usb,yes,31,38 2006.285.20:22:32.62/valo/01,524.99,yes,locked 2006.285.20:22:32.62/valo/02,534.99,yes,locked 2006.285.20:22:32.62/valo/03,564.99,yes,locked 2006.285.20:22:32.62/valo/04,624.99,yes,locked 2006.285.20:22:32.62/valo/05,734.99,yes,locked 2006.285.20:22:32.62/valo/06,814.99,yes,locked 2006.285.20:22:32.62/valo/07,864.99,yes,locked 2006.285.20:22:32.62/valo/08,884.99,yes,locked 2006.285.20:22:33.71/vb/01,04,usb,yes,30,28 2006.285.20:22:33.71/vb/02,05,usb,yes,28,28 2006.285.20:22:33.71/vb/03,04,usb,yes,29,32 2006.285.20:22:33.71/vb/04,05,usb,yes,29,28 2006.285.20:22:33.71/vb/05,04,usb,yes,26,28 2006.285.20:22:33.71/vb/06,03,usb,yes,37,33 2006.285.20:22:33.71/vb/07,04,usb,yes,30,30 2006.285.20:22:33.71/vb/08,04,usb,yes,27,31 2006.285.20:22:33.94/vblo/01,629.99,yes,locked 2006.285.20:22:33.94/vblo/02,634.99,yes,locked 2006.285.20:22:33.94/vblo/03,649.99,yes,locked 2006.285.20:22:33.94/vblo/04,679.99,yes,locked 2006.285.20:22:33.94/vblo/05,709.99,yes,locked 2006.285.20:22:33.94/vblo/06,719.99,yes,locked 2006.285.20:22:33.94/vblo/07,734.99,yes,locked 2006.285.20:22:33.94/vblo/08,744.99,yes,locked 2006.285.20:22:34.09/vabw/8 2006.285.20:22:34.24/vbbw/8 2006.285.20:22:34.33/xfe/off,on,12.0 2006.285.20:22:34.70/ifatt/23,28,28,28 2006.285.20:22:35.07/fmout-gps/S +2.66E-07 2006.285.20:22:35.09:!2006.285.20:27:51 2006.285.20:27:51.00:data_valid=off 2006.285.20:27:51.00:"et 2006.285.20:27:51.00:!+3s 2006.285.20:27:54.01:"tape 2006.285.20:27:54.01:postob 2006.285.20:27:54.07/cable/+6.5101E-03 2006.285.20:27:54.07/wx/14.41,1015.3,100 2006.285.20:27:55.07/fmout-gps/S +2.60E-07 2006.285.20:27:55.07:scan_name=285-2033,jd0610,200 2006.285.20:27:55.07:source=1044+719,104827.62,714335.9,2000.0,cw 2006.285.20:27:56.14#flagr#flagr/antenna,new-source 2006.285.20:27:56.14:checkk5 2006.285.20:27:56.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.20:27:57.00/chk_autoobs//k5ts2/ autoobs is running! 2006.285.20:27:57.61/chk_autoobs//k5ts3/ autoobs is running! 2006.285.20:27:58.21/chk_autoobs//k5ts4/ autoobs is running! 2006.285.20:27:58.59/chk_obsdata//k5ts1/T2852022??a.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.285.20:27:59.05/chk_obsdata//k5ts2/T2852022??b.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.285.20:27:59.42/chk_obsdata//k5ts3/T2852022??c.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.285.20:28:00.10/chk_obsdata//k5ts4/T2852022??d.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.285.20:28:00.98/k5log//k5ts1_log_newline 2006.285.20:28:01.79/k5log//k5ts2_log_newline 2006.285.20:28:02.78/k5log//k5ts3_log_newline 2006.285.20:28:03.95/k5log//k5ts4_log_newline 2006.285.20:28:03.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.20:28:03.97:setupk4=1 2006.285.20:28:03.97$setupk4/echo=on 2006.285.20:28:03.97$setupk4/pcalon 2006.285.20:28:03.97$pcalon/"no phase cal control is implemented here 2006.285.20:28:03.97$setupk4/"tpicd=stop 2006.285.20:28:03.97$setupk4/"rec=synch_on 2006.285.20:28:03.97$setupk4/"rec_mode=128 2006.285.20:28:03.97$setupk4/!* 2006.285.20:28:03.97$setupk4/recpk4 2006.285.20:28:03.97$recpk4/recpatch= 2006.285.20:28:03.98$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.20:28:03.98$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.20:28:03.98$setupk4/vck44 2006.285.20:28:03.98$vck44/valo=1,524.99 2006.285.20:28:03.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.20:28:03.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.20:28:03.98#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:03.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:28:03.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:28:03.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:28:03.98#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:28:03.98#ibcon#first serial, iclass 29, count 0 2006.285.20:28:03.98#ibcon#enter sib2, iclass 29, count 0 2006.285.20:28:03.98#ibcon#flushed, iclass 29, count 0 2006.285.20:28:03.98#ibcon#about to write, iclass 29, count 0 2006.285.20:28:03.98#ibcon#wrote, iclass 29, count 0 2006.285.20:28:03.98#ibcon#about to read 3, iclass 29, count 0 2006.285.20:28:03.99#ibcon#read 3, iclass 29, count 0 2006.285.20:28:03.99#ibcon#about to read 4, iclass 29, count 0 2006.285.20:28:03.99#ibcon#read 4, iclass 29, count 0 2006.285.20:28:03.99#ibcon#about to read 5, iclass 29, count 0 2006.285.20:28:03.99#ibcon#read 5, iclass 29, count 0 2006.285.20:28:03.99#ibcon#about to read 6, iclass 29, count 0 2006.285.20:28:03.99#ibcon#read 6, iclass 29, count 0 2006.285.20:28:03.99#ibcon#end of sib2, iclass 29, count 0 2006.285.20:28:03.99#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:28:03.99#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:28:03.99#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.20:28:03.99#ibcon#*before write, iclass 29, count 0 2006.285.20:28:03.99#ibcon#enter sib2, iclass 29, count 0 2006.285.20:28:03.99#ibcon#flushed, iclass 29, count 0 2006.285.20:28:03.99#ibcon#about to write, iclass 29, count 0 2006.285.20:28:03.99#ibcon#wrote, iclass 29, count 0 2006.285.20:28:03.99#ibcon#about to read 3, iclass 29, count 0 2006.285.20:28:04.04#ibcon#read 3, iclass 29, count 0 2006.285.20:28:04.04#ibcon#about to read 4, iclass 29, count 0 2006.285.20:28:04.04#ibcon#read 4, iclass 29, count 0 2006.285.20:28:04.04#ibcon#about to read 5, iclass 29, count 0 2006.285.20:28:04.04#ibcon#read 5, iclass 29, count 0 2006.285.20:28:04.04#ibcon#about to read 6, iclass 29, count 0 2006.285.20:28:04.04#ibcon#read 6, iclass 29, count 0 2006.285.20:28:04.04#ibcon#end of sib2, iclass 29, count 0 2006.285.20:28:04.04#ibcon#*after write, iclass 29, count 0 2006.285.20:28:04.04#ibcon#*before return 0, iclass 29, count 0 2006.285.20:28:04.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:28:04.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:28:04.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:28:04.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:28:04.04$vck44/va=1,7 2006.285.20:28:04.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.20:28:04.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.20:28:04.04#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:04.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:28:04.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:28:04.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:28:04.04#ibcon#enter wrdev, iclass 31, count 2 2006.285.20:28:04.04#ibcon#first serial, iclass 31, count 2 2006.285.20:28:04.04#ibcon#enter sib2, iclass 31, count 2 2006.285.20:28:04.04#ibcon#flushed, iclass 31, count 2 2006.285.20:28:04.04#ibcon#about to write, iclass 31, count 2 2006.285.20:28:04.04#ibcon#wrote, iclass 31, count 2 2006.285.20:28:04.04#ibcon#about to read 3, iclass 31, count 2 2006.285.20:28:04.06#ibcon#read 3, iclass 31, count 2 2006.285.20:28:04.06#ibcon#about to read 4, iclass 31, count 2 2006.285.20:28:04.06#ibcon#read 4, iclass 31, count 2 2006.285.20:28:04.06#ibcon#about to read 5, iclass 31, count 2 2006.285.20:28:04.06#ibcon#read 5, iclass 31, count 2 2006.285.20:28:04.06#ibcon#about to read 6, iclass 31, count 2 2006.285.20:28:04.06#ibcon#read 6, iclass 31, count 2 2006.285.20:28:04.06#ibcon#end of sib2, iclass 31, count 2 2006.285.20:28:04.06#ibcon#*mode == 0, iclass 31, count 2 2006.285.20:28:04.06#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.20:28:04.06#ibcon#[25=AT01-07\r\n] 2006.285.20:28:04.06#ibcon#*before write, iclass 31, count 2 2006.285.20:28:04.06#ibcon#enter sib2, iclass 31, count 2 2006.285.20:28:04.06#ibcon#flushed, iclass 31, count 2 2006.285.20:28:04.06#ibcon#about to write, iclass 31, count 2 2006.285.20:28:04.06#ibcon#wrote, iclass 31, count 2 2006.285.20:28:04.06#ibcon#about to read 3, iclass 31, count 2 2006.285.20:28:04.09#ibcon#read 3, iclass 31, count 2 2006.285.20:28:04.09#ibcon#about to read 4, iclass 31, count 2 2006.285.20:28:04.09#ibcon#read 4, iclass 31, count 2 2006.285.20:28:04.09#ibcon#about to read 5, iclass 31, count 2 2006.285.20:28:04.09#ibcon#read 5, iclass 31, count 2 2006.285.20:28:04.09#ibcon#about to read 6, iclass 31, count 2 2006.285.20:28:04.09#ibcon#read 6, iclass 31, count 2 2006.285.20:28:04.09#ibcon#end of sib2, iclass 31, count 2 2006.285.20:28:04.09#ibcon#*after write, iclass 31, count 2 2006.285.20:28:04.09#ibcon#*before return 0, iclass 31, count 2 2006.285.20:28:04.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:28:04.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:28:04.09#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.20:28:04.09#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:04.09#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:28:04.21#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:28:04.21#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:28:04.21#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:28:04.21#ibcon#first serial, iclass 31, count 0 2006.285.20:28:04.21#ibcon#enter sib2, iclass 31, count 0 2006.285.20:28:04.21#ibcon#flushed, iclass 31, count 0 2006.285.20:28:04.21#ibcon#about to write, iclass 31, count 0 2006.285.20:28:04.21#ibcon#wrote, iclass 31, count 0 2006.285.20:28:04.21#ibcon#about to read 3, iclass 31, count 0 2006.285.20:28:04.23#ibcon#read 3, iclass 31, count 0 2006.285.20:28:04.23#ibcon#about to read 4, iclass 31, count 0 2006.285.20:28:04.23#ibcon#read 4, iclass 31, count 0 2006.285.20:28:04.23#ibcon#about to read 5, iclass 31, count 0 2006.285.20:28:04.23#ibcon#read 5, iclass 31, count 0 2006.285.20:28:04.23#ibcon#about to read 6, iclass 31, count 0 2006.285.20:28:04.23#ibcon#read 6, iclass 31, count 0 2006.285.20:28:04.23#ibcon#end of sib2, iclass 31, count 0 2006.285.20:28:04.23#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:28:04.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:28:04.23#ibcon#[25=USB\r\n] 2006.285.20:28:04.23#ibcon#*before write, iclass 31, count 0 2006.285.20:28:04.23#ibcon#enter sib2, iclass 31, count 0 2006.285.20:28:04.23#ibcon#flushed, iclass 31, count 0 2006.285.20:28:04.23#ibcon#about to write, iclass 31, count 0 2006.285.20:28:04.23#ibcon#wrote, iclass 31, count 0 2006.285.20:28:04.23#ibcon#about to read 3, iclass 31, count 0 2006.285.20:28:04.26#ibcon#read 3, iclass 31, count 0 2006.285.20:28:04.26#ibcon#about to read 4, iclass 31, count 0 2006.285.20:28:04.26#ibcon#read 4, iclass 31, count 0 2006.285.20:28:04.26#ibcon#about to read 5, iclass 31, count 0 2006.285.20:28:04.26#ibcon#read 5, iclass 31, count 0 2006.285.20:28:04.26#ibcon#about to read 6, iclass 31, count 0 2006.285.20:28:04.26#ibcon#read 6, iclass 31, count 0 2006.285.20:28:04.26#ibcon#end of sib2, iclass 31, count 0 2006.285.20:28:04.26#ibcon#*after write, iclass 31, count 0 2006.285.20:28:04.26#ibcon#*before return 0, iclass 31, count 0 2006.285.20:28:04.26#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:28:04.26#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:28:04.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:28:04.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:28:04.26$vck44/valo=2,534.99 2006.285.20:28:04.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.20:28:04.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.20:28:04.26#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:04.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:28:04.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:28:04.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:28:04.26#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:28:04.26#ibcon#first serial, iclass 33, count 0 2006.285.20:28:04.26#ibcon#enter sib2, iclass 33, count 0 2006.285.20:28:04.26#ibcon#flushed, iclass 33, count 0 2006.285.20:28:04.26#ibcon#about to write, iclass 33, count 0 2006.285.20:28:04.26#ibcon#wrote, iclass 33, count 0 2006.285.20:28:04.26#ibcon#about to read 3, iclass 33, count 0 2006.285.20:28:04.28#ibcon#read 3, iclass 33, count 0 2006.285.20:28:04.28#ibcon#about to read 4, iclass 33, count 0 2006.285.20:28:04.28#ibcon#read 4, iclass 33, count 0 2006.285.20:28:04.28#ibcon#about to read 5, iclass 33, count 0 2006.285.20:28:04.28#ibcon#read 5, iclass 33, count 0 2006.285.20:28:04.28#ibcon#about to read 6, iclass 33, count 0 2006.285.20:28:04.28#ibcon#read 6, iclass 33, count 0 2006.285.20:28:04.28#ibcon#end of sib2, iclass 33, count 0 2006.285.20:28:04.28#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:28:04.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:28:04.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.20:28:04.28#ibcon#*before write, iclass 33, count 0 2006.285.20:28:04.28#ibcon#enter sib2, iclass 33, count 0 2006.285.20:28:04.28#ibcon#flushed, iclass 33, count 0 2006.285.20:28:04.28#ibcon#about to write, iclass 33, count 0 2006.285.20:28:04.28#ibcon#wrote, iclass 33, count 0 2006.285.20:28:04.28#ibcon#about to read 3, iclass 33, count 0 2006.285.20:28:04.32#ibcon#read 3, iclass 33, count 0 2006.285.20:28:04.32#ibcon#about to read 4, iclass 33, count 0 2006.285.20:28:04.32#ibcon#read 4, iclass 33, count 0 2006.285.20:28:04.32#ibcon#about to read 5, iclass 33, count 0 2006.285.20:28:04.32#ibcon#read 5, iclass 33, count 0 2006.285.20:28:04.32#ibcon#about to read 6, iclass 33, count 0 2006.285.20:28:04.32#ibcon#read 6, iclass 33, count 0 2006.285.20:28:04.32#ibcon#end of sib2, iclass 33, count 0 2006.285.20:28:04.32#ibcon#*after write, iclass 33, count 0 2006.285.20:28:04.32#ibcon#*before return 0, iclass 33, count 0 2006.285.20:28:04.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:28:04.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:28:04.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:28:04.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:28:04.32$vck44/va=2,6 2006.285.20:28:04.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.20:28:04.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.20:28:04.32#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:04.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:28:04.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:28:04.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:28:04.38#ibcon#enter wrdev, iclass 35, count 2 2006.285.20:28:04.38#ibcon#first serial, iclass 35, count 2 2006.285.20:28:04.38#ibcon#enter sib2, iclass 35, count 2 2006.285.20:28:04.38#ibcon#flushed, iclass 35, count 2 2006.285.20:28:04.38#ibcon#about to write, iclass 35, count 2 2006.285.20:28:04.38#ibcon#wrote, iclass 35, count 2 2006.285.20:28:04.38#ibcon#about to read 3, iclass 35, count 2 2006.285.20:28:04.40#ibcon#read 3, iclass 35, count 2 2006.285.20:28:04.40#ibcon#about to read 4, iclass 35, count 2 2006.285.20:28:04.40#ibcon#read 4, iclass 35, count 2 2006.285.20:28:04.40#ibcon#about to read 5, iclass 35, count 2 2006.285.20:28:04.40#ibcon#read 5, iclass 35, count 2 2006.285.20:28:04.40#ibcon#about to read 6, iclass 35, count 2 2006.285.20:28:04.40#ibcon#read 6, iclass 35, count 2 2006.285.20:28:04.40#ibcon#end of sib2, iclass 35, count 2 2006.285.20:28:04.40#ibcon#*mode == 0, iclass 35, count 2 2006.285.20:28:04.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.20:28:04.40#ibcon#[25=AT02-06\r\n] 2006.285.20:28:04.40#ibcon#*before write, iclass 35, count 2 2006.285.20:28:04.40#ibcon#enter sib2, iclass 35, count 2 2006.285.20:28:04.40#ibcon#flushed, iclass 35, count 2 2006.285.20:28:04.40#ibcon#about to write, iclass 35, count 2 2006.285.20:28:04.40#ibcon#wrote, iclass 35, count 2 2006.285.20:28:04.40#ibcon#about to read 3, iclass 35, count 2 2006.285.20:28:04.43#ibcon#read 3, iclass 35, count 2 2006.285.20:28:04.43#ibcon#about to read 4, iclass 35, count 2 2006.285.20:28:04.43#ibcon#read 4, iclass 35, count 2 2006.285.20:28:04.43#ibcon#about to read 5, iclass 35, count 2 2006.285.20:28:04.43#ibcon#read 5, iclass 35, count 2 2006.285.20:28:04.43#ibcon#about to read 6, iclass 35, count 2 2006.285.20:28:04.43#ibcon#read 6, iclass 35, count 2 2006.285.20:28:04.43#ibcon#end of sib2, iclass 35, count 2 2006.285.20:28:04.43#ibcon#*after write, iclass 35, count 2 2006.285.20:28:04.43#ibcon#*before return 0, iclass 35, count 2 2006.285.20:28:04.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:28:04.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:28:04.43#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.20:28:04.43#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:04.43#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:28:04.55#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:28:04.55#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:28:04.55#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:28:04.55#ibcon#first serial, iclass 35, count 0 2006.285.20:28:04.55#ibcon#enter sib2, iclass 35, count 0 2006.285.20:28:04.55#ibcon#flushed, iclass 35, count 0 2006.285.20:28:04.55#ibcon#about to write, iclass 35, count 0 2006.285.20:28:04.55#ibcon#wrote, iclass 35, count 0 2006.285.20:28:04.55#ibcon#about to read 3, iclass 35, count 0 2006.285.20:28:04.57#ibcon#read 3, iclass 35, count 0 2006.285.20:28:04.57#ibcon#about to read 4, iclass 35, count 0 2006.285.20:28:04.57#ibcon#read 4, iclass 35, count 0 2006.285.20:28:04.57#ibcon#about to read 5, iclass 35, count 0 2006.285.20:28:04.57#ibcon#read 5, iclass 35, count 0 2006.285.20:28:04.57#ibcon#about to read 6, iclass 35, count 0 2006.285.20:28:04.57#ibcon#read 6, iclass 35, count 0 2006.285.20:28:04.57#ibcon#end of sib2, iclass 35, count 0 2006.285.20:28:04.57#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:28:04.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:28:04.57#ibcon#[25=USB\r\n] 2006.285.20:28:04.57#ibcon#*before write, iclass 35, count 0 2006.285.20:28:04.57#ibcon#enter sib2, iclass 35, count 0 2006.285.20:28:04.57#ibcon#flushed, iclass 35, count 0 2006.285.20:28:04.57#ibcon#about to write, iclass 35, count 0 2006.285.20:28:04.57#ibcon#wrote, iclass 35, count 0 2006.285.20:28:04.57#ibcon#about to read 3, iclass 35, count 0 2006.285.20:28:04.60#ibcon#read 3, iclass 35, count 0 2006.285.20:28:04.60#ibcon#about to read 4, iclass 35, count 0 2006.285.20:28:04.60#ibcon#read 4, iclass 35, count 0 2006.285.20:28:04.60#ibcon#about to read 5, iclass 35, count 0 2006.285.20:28:04.60#ibcon#read 5, iclass 35, count 0 2006.285.20:28:04.60#ibcon#about to read 6, iclass 35, count 0 2006.285.20:28:04.60#ibcon#read 6, iclass 35, count 0 2006.285.20:28:04.60#ibcon#end of sib2, iclass 35, count 0 2006.285.20:28:04.60#ibcon#*after write, iclass 35, count 0 2006.285.20:28:04.60#ibcon#*before return 0, iclass 35, count 0 2006.285.20:28:04.60#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:28:04.60#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:28:04.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:28:04.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:28:04.60$vck44/valo=3,564.99 2006.285.20:28:04.60#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.20:28:04.60#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.20:28:04.60#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:04.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:28:04.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:28:04.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:28:04.60#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:28:04.60#ibcon#first serial, iclass 37, count 0 2006.285.20:28:04.60#ibcon#enter sib2, iclass 37, count 0 2006.285.20:28:04.60#ibcon#flushed, iclass 37, count 0 2006.285.20:28:04.60#ibcon#about to write, iclass 37, count 0 2006.285.20:28:04.60#ibcon#wrote, iclass 37, count 0 2006.285.20:28:04.60#ibcon#about to read 3, iclass 37, count 0 2006.285.20:28:04.62#ibcon#read 3, iclass 37, count 0 2006.285.20:28:04.62#ibcon#about to read 4, iclass 37, count 0 2006.285.20:28:04.62#ibcon#read 4, iclass 37, count 0 2006.285.20:28:04.62#ibcon#about to read 5, iclass 37, count 0 2006.285.20:28:04.62#ibcon#read 5, iclass 37, count 0 2006.285.20:28:04.62#ibcon#about to read 6, iclass 37, count 0 2006.285.20:28:04.62#ibcon#read 6, iclass 37, count 0 2006.285.20:28:04.62#ibcon#end of sib2, iclass 37, count 0 2006.285.20:28:04.62#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:28:04.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:28:04.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.20:28:04.62#ibcon#*before write, iclass 37, count 0 2006.285.20:28:04.62#ibcon#enter sib2, iclass 37, count 0 2006.285.20:28:04.62#ibcon#flushed, iclass 37, count 0 2006.285.20:28:04.62#ibcon#about to write, iclass 37, count 0 2006.285.20:28:04.62#ibcon#wrote, iclass 37, count 0 2006.285.20:28:04.62#ibcon#about to read 3, iclass 37, count 0 2006.285.20:28:04.66#ibcon#read 3, iclass 37, count 0 2006.285.20:28:04.66#ibcon#about to read 4, iclass 37, count 0 2006.285.20:28:04.66#ibcon#read 4, iclass 37, count 0 2006.285.20:28:04.66#ibcon#about to read 5, iclass 37, count 0 2006.285.20:28:04.66#ibcon#read 5, iclass 37, count 0 2006.285.20:28:04.66#ibcon#about to read 6, iclass 37, count 0 2006.285.20:28:04.66#ibcon#read 6, iclass 37, count 0 2006.285.20:28:04.66#ibcon#end of sib2, iclass 37, count 0 2006.285.20:28:04.66#ibcon#*after write, iclass 37, count 0 2006.285.20:28:04.66#ibcon#*before return 0, iclass 37, count 0 2006.285.20:28:04.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:28:04.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:28:04.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:28:04.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:28:04.66$vck44/va=3,7 2006.285.20:28:04.66#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.20:28:04.66#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.20:28:04.66#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:04.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:28:04.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:28:04.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:28:04.72#ibcon#enter wrdev, iclass 39, count 2 2006.285.20:28:04.72#ibcon#first serial, iclass 39, count 2 2006.285.20:28:04.72#ibcon#enter sib2, iclass 39, count 2 2006.285.20:28:04.72#ibcon#flushed, iclass 39, count 2 2006.285.20:28:04.72#ibcon#about to write, iclass 39, count 2 2006.285.20:28:04.72#ibcon#wrote, iclass 39, count 2 2006.285.20:28:04.72#ibcon#about to read 3, iclass 39, count 2 2006.285.20:28:04.74#ibcon#read 3, iclass 39, count 2 2006.285.20:28:04.74#ibcon#about to read 4, iclass 39, count 2 2006.285.20:28:04.74#ibcon#read 4, iclass 39, count 2 2006.285.20:28:04.74#ibcon#about to read 5, iclass 39, count 2 2006.285.20:28:04.74#ibcon#read 5, iclass 39, count 2 2006.285.20:28:04.74#ibcon#about to read 6, iclass 39, count 2 2006.285.20:28:04.74#ibcon#read 6, iclass 39, count 2 2006.285.20:28:04.74#ibcon#end of sib2, iclass 39, count 2 2006.285.20:28:04.74#ibcon#*mode == 0, iclass 39, count 2 2006.285.20:28:04.74#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.20:28:04.74#ibcon#[25=AT03-07\r\n] 2006.285.20:28:04.74#ibcon#*before write, iclass 39, count 2 2006.285.20:28:04.74#ibcon#enter sib2, iclass 39, count 2 2006.285.20:28:04.74#ibcon#flushed, iclass 39, count 2 2006.285.20:28:04.74#ibcon#about to write, iclass 39, count 2 2006.285.20:28:04.74#ibcon#wrote, iclass 39, count 2 2006.285.20:28:04.74#ibcon#about to read 3, iclass 39, count 2 2006.285.20:28:04.77#ibcon#read 3, iclass 39, count 2 2006.285.20:28:04.77#ibcon#about to read 4, iclass 39, count 2 2006.285.20:28:04.77#ibcon#read 4, iclass 39, count 2 2006.285.20:28:04.77#ibcon#about to read 5, iclass 39, count 2 2006.285.20:28:04.77#ibcon#read 5, iclass 39, count 2 2006.285.20:28:04.77#ibcon#about to read 6, iclass 39, count 2 2006.285.20:28:04.77#ibcon#read 6, iclass 39, count 2 2006.285.20:28:04.77#ibcon#end of sib2, iclass 39, count 2 2006.285.20:28:04.77#ibcon#*after write, iclass 39, count 2 2006.285.20:28:04.77#ibcon#*before return 0, iclass 39, count 2 2006.285.20:28:04.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:28:04.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:28:04.77#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.20:28:04.77#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:04.77#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:28:04.89#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:28:05.30#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:28:05.30#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:28:05.30#ibcon#first serial, iclass 39, count 0 2006.285.20:28:05.30#ibcon#enter sib2, iclass 39, count 0 2006.285.20:28:05.30#ibcon#flushed, iclass 39, count 0 2006.285.20:28:05.30#ibcon#about to write, iclass 39, count 0 2006.285.20:28:05.30#ibcon#wrote, iclass 39, count 0 2006.285.20:28:05.30#ibcon#about to read 3, iclass 39, count 0 2006.285.20:28:05.32#ibcon#read 3, iclass 39, count 0 2006.285.20:28:05.32#ibcon#about to read 4, iclass 39, count 0 2006.285.20:28:05.32#ibcon#read 4, iclass 39, count 0 2006.285.20:28:05.32#ibcon#about to read 5, iclass 39, count 0 2006.285.20:28:05.32#ibcon#read 5, iclass 39, count 0 2006.285.20:28:05.32#ibcon#about to read 6, iclass 39, count 0 2006.285.20:28:05.32#ibcon#read 6, iclass 39, count 0 2006.285.20:28:05.32#ibcon#end of sib2, iclass 39, count 0 2006.285.20:28:05.32#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:28:05.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:28:05.32#ibcon#[25=USB\r\n] 2006.285.20:28:05.32#ibcon#*before write, iclass 39, count 0 2006.285.20:28:05.32#ibcon#enter sib2, iclass 39, count 0 2006.285.20:28:05.32#ibcon#flushed, iclass 39, count 0 2006.285.20:28:05.32#ibcon#about to write, iclass 39, count 0 2006.285.20:28:05.32#ibcon#wrote, iclass 39, count 0 2006.285.20:28:05.32#ibcon#about to read 3, iclass 39, count 0 2006.285.20:28:05.35#ibcon#read 3, iclass 39, count 0 2006.285.20:28:05.35#ibcon#about to read 4, iclass 39, count 0 2006.285.20:28:05.35#ibcon#read 4, iclass 39, count 0 2006.285.20:28:05.35#ibcon#about to read 5, iclass 39, count 0 2006.285.20:28:05.35#ibcon#read 5, iclass 39, count 0 2006.285.20:28:05.35#ibcon#about to read 6, iclass 39, count 0 2006.285.20:28:05.35#ibcon#read 6, iclass 39, count 0 2006.285.20:28:05.35#ibcon#end of sib2, iclass 39, count 0 2006.285.20:28:05.35#ibcon#*after write, iclass 39, count 0 2006.285.20:28:05.35#ibcon#*before return 0, iclass 39, count 0 2006.285.20:28:05.35#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:28:05.35#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:28:05.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:28:05.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:28:05.35$vck44/valo=4,624.99 2006.285.20:28:05.35#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.20:28:05.35#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.20:28:05.35#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:05.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:28:05.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:28:05.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:28:05.35#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:28:05.35#ibcon#first serial, iclass 3, count 0 2006.285.20:28:05.35#ibcon#enter sib2, iclass 3, count 0 2006.285.20:28:05.35#ibcon#flushed, iclass 3, count 0 2006.285.20:28:05.35#ibcon#about to write, iclass 3, count 0 2006.285.20:28:05.35#ibcon#wrote, iclass 3, count 0 2006.285.20:28:05.35#ibcon#about to read 3, iclass 3, count 0 2006.285.20:28:05.37#ibcon#read 3, iclass 3, count 0 2006.285.20:28:05.37#ibcon#about to read 4, iclass 3, count 0 2006.285.20:28:05.37#ibcon#read 4, iclass 3, count 0 2006.285.20:28:05.37#ibcon#about to read 5, iclass 3, count 0 2006.285.20:28:05.37#ibcon#read 5, iclass 3, count 0 2006.285.20:28:05.37#ibcon#about to read 6, iclass 3, count 0 2006.285.20:28:05.37#ibcon#read 6, iclass 3, count 0 2006.285.20:28:05.37#ibcon#end of sib2, iclass 3, count 0 2006.285.20:28:05.37#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:28:05.37#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:28:05.37#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.20:28:05.37#ibcon#*before write, iclass 3, count 0 2006.285.20:28:05.37#ibcon#enter sib2, iclass 3, count 0 2006.285.20:28:05.37#ibcon#flushed, iclass 3, count 0 2006.285.20:28:05.37#ibcon#about to write, iclass 3, count 0 2006.285.20:28:05.37#ibcon#wrote, iclass 3, count 0 2006.285.20:28:05.37#ibcon#about to read 3, iclass 3, count 0 2006.285.20:28:05.41#ibcon#read 3, iclass 3, count 0 2006.285.20:28:05.41#ibcon#about to read 4, iclass 3, count 0 2006.285.20:28:05.41#ibcon#read 4, iclass 3, count 0 2006.285.20:28:05.41#ibcon#about to read 5, iclass 3, count 0 2006.285.20:28:05.41#ibcon#read 5, iclass 3, count 0 2006.285.20:28:05.41#ibcon#about to read 6, iclass 3, count 0 2006.285.20:28:05.41#ibcon#read 6, iclass 3, count 0 2006.285.20:28:05.41#ibcon#end of sib2, iclass 3, count 0 2006.285.20:28:05.41#ibcon#*after write, iclass 3, count 0 2006.285.20:28:05.41#ibcon#*before return 0, iclass 3, count 0 2006.285.20:28:05.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:28:05.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:28:05.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:28:05.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:28:05.41$vck44/va=4,6 2006.285.20:28:05.41#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.20:28:05.41#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.20:28:05.41#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:05.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:28:05.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:28:05.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:28:05.47#ibcon#enter wrdev, iclass 5, count 2 2006.285.20:28:05.47#ibcon#first serial, iclass 5, count 2 2006.285.20:28:05.47#ibcon#enter sib2, iclass 5, count 2 2006.285.20:28:05.47#ibcon#flushed, iclass 5, count 2 2006.285.20:28:05.47#ibcon#about to write, iclass 5, count 2 2006.285.20:28:05.47#ibcon#wrote, iclass 5, count 2 2006.285.20:28:05.47#ibcon#about to read 3, iclass 5, count 2 2006.285.20:28:05.49#ibcon#read 3, iclass 5, count 2 2006.285.20:28:05.49#ibcon#about to read 4, iclass 5, count 2 2006.285.20:28:05.49#ibcon#read 4, iclass 5, count 2 2006.285.20:28:05.49#ibcon#about to read 5, iclass 5, count 2 2006.285.20:28:05.49#ibcon#read 5, iclass 5, count 2 2006.285.20:28:05.49#ibcon#about to read 6, iclass 5, count 2 2006.285.20:28:05.49#ibcon#read 6, iclass 5, count 2 2006.285.20:28:05.49#ibcon#end of sib2, iclass 5, count 2 2006.285.20:28:05.49#ibcon#*mode == 0, iclass 5, count 2 2006.285.20:28:05.49#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.20:28:05.49#ibcon#[25=AT04-06\r\n] 2006.285.20:28:05.49#ibcon#*before write, iclass 5, count 2 2006.285.20:28:05.49#ibcon#enter sib2, iclass 5, count 2 2006.285.20:28:05.49#ibcon#flushed, iclass 5, count 2 2006.285.20:28:05.49#ibcon#about to write, iclass 5, count 2 2006.285.20:28:05.49#ibcon#wrote, iclass 5, count 2 2006.285.20:28:05.49#ibcon#about to read 3, iclass 5, count 2 2006.285.20:28:05.52#ibcon#read 3, iclass 5, count 2 2006.285.20:28:05.52#ibcon#about to read 4, iclass 5, count 2 2006.285.20:28:05.52#ibcon#read 4, iclass 5, count 2 2006.285.20:28:05.52#ibcon#about to read 5, iclass 5, count 2 2006.285.20:28:05.52#ibcon#read 5, iclass 5, count 2 2006.285.20:28:05.52#ibcon#about to read 6, iclass 5, count 2 2006.285.20:28:05.52#ibcon#read 6, iclass 5, count 2 2006.285.20:28:05.52#ibcon#end of sib2, iclass 5, count 2 2006.285.20:28:05.52#ibcon#*after write, iclass 5, count 2 2006.285.20:28:05.52#ibcon#*before return 0, iclass 5, count 2 2006.285.20:28:05.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:28:05.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:28:05.52#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.20:28:05.52#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:05.52#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:28:05.64#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:28:05.64#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:28:05.64#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:28:05.64#ibcon#first serial, iclass 5, count 0 2006.285.20:28:05.64#ibcon#enter sib2, iclass 5, count 0 2006.285.20:28:05.64#ibcon#flushed, iclass 5, count 0 2006.285.20:28:05.64#ibcon#about to write, iclass 5, count 0 2006.285.20:28:05.64#ibcon#wrote, iclass 5, count 0 2006.285.20:28:05.64#ibcon#about to read 3, iclass 5, count 0 2006.285.20:28:05.66#ibcon#read 3, iclass 5, count 0 2006.285.20:28:05.66#ibcon#about to read 4, iclass 5, count 0 2006.285.20:28:05.66#ibcon#read 4, iclass 5, count 0 2006.285.20:28:05.81#ibcon#about to read 5, iclass 5, count 0 2006.285.20:28:05.81#ibcon#read 5, iclass 5, count 0 2006.285.20:28:05.81#ibcon#about to read 6, iclass 5, count 0 2006.285.20:28:05.81#ibcon#read 6, iclass 5, count 0 2006.285.20:28:05.81#ibcon#end of sib2, iclass 5, count 0 2006.285.20:28:05.81#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:28:05.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:28:05.81#ibcon#[25=USB\r\n] 2006.285.20:28:05.81#ibcon#*before write, iclass 5, count 0 2006.285.20:28:05.81#ibcon#enter sib2, iclass 5, count 0 2006.285.20:28:05.81#ibcon#flushed, iclass 5, count 0 2006.285.20:28:05.81#ibcon#about to write, iclass 5, count 0 2006.285.20:28:05.81#ibcon#wrote, iclass 5, count 0 2006.285.20:28:05.81#ibcon#about to read 3, iclass 5, count 0 2006.285.20:28:05.84#ibcon#read 3, iclass 5, count 0 2006.285.20:28:05.84#ibcon#about to read 4, iclass 5, count 0 2006.285.20:28:05.84#ibcon#read 4, iclass 5, count 0 2006.285.20:28:05.84#ibcon#about to read 5, iclass 5, count 0 2006.285.20:28:05.84#ibcon#read 5, iclass 5, count 0 2006.285.20:28:05.84#ibcon#about to read 6, iclass 5, count 0 2006.285.20:28:05.84#ibcon#read 6, iclass 5, count 0 2006.285.20:28:05.84#ibcon#end of sib2, iclass 5, count 0 2006.285.20:28:05.84#ibcon#*after write, iclass 5, count 0 2006.285.20:28:05.84#ibcon#*before return 0, iclass 5, count 0 2006.285.20:28:05.84#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:28:05.84#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:28:05.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:28:05.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:28:05.84$vck44/valo=5,734.99 2006.285.20:28:05.84#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.20:28:05.84#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.20:28:05.84#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:05.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:28:05.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:28:05.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:28:05.84#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:28:05.84#ibcon#first serial, iclass 7, count 0 2006.285.20:28:05.84#ibcon#enter sib2, iclass 7, count 0 2006.285.20:28:05.84#ibcon#flushed, iclass 7, count 0 2006.285.20:28:05.84#ibcon#about to write, iclass 7, count 0 2006.285.20:28:05.84#ibcon#wrote, iclass 7, count 0 2006.285.20:28:05.84#ibcon#about to read 3, iclass 7, count 0 2006.285.20:28:05.86#ibcon#read 3, iclass 7, count 0 2006.285.20:28:05.86#ibcon#about to read 4, iclass 7, count 0 2006.285.20:28:05.86#ibcon#read 4, iclass 7, count 0 2006.285.20:28:05.86#ibcon#about to read 5, iclass 7, count 0 2006.285.20:28:05.86#ibcon#read 5, iclass 7, count 0 2006.285.20:28:05.86#ibcon#about to read 6, iclass 7, count 0 2006.285.20:28:05.86#ibcon#read 6, iclass 7, count 0 2006.285.20:28:05.86#ibcon#end of sib2, iclass 7, count 0 2006.285.20:28:05.86#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:28:05.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:28:05.86#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.20:28:05.86#ibcon#*before write, iclass 7, count 0 2006.285.20:28:05.86#ibcon#enter sib2, iclass 7, count 0 2006.285.20:28:05.86#ibcon#flushed, iclass 7, count 0 2006.285.20:28:05.86#ibcon#about to write, iclass 7, count 0 2006.285.20:28:05.86#ibcon#wrote, iclass 7, count 0 2006.285.20:28:05.86#ibcon#about to read 3, iclass 7, count 0 2006.285.20:28:05.90#ibcon#read 3, iclass 7, count 0 2006.285.20:28:05.90#ibcon#about to read 4, iclass 7, count 0 2006.285.20:28:05.90#ibcon#read 4, iclass 7, count 0 2006.285.20:28:05.90#ibcon#about to read 5, iclass 7, count 0 2006.285.20:28:05.90#ibcon#read 5, iclass 7, count 0 2006.285.20:28:05.90#ibcon#about to read 6, iclass 7, count 0 2006.285.20:28:05.90#ibcon#read 6, iclass 7, count 0 2006.285.20:28:05.90#ibcon#end of sib2, iclass 7, count 0 2006.285.20:28:05.90#ibcon#*after write, iclass 7, count 0 2006.285.20:28:05.90#ibcon#*before return 0, iclass 7, count 0 2006.285.20:28:05.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:28:05.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:28:05.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:28:05.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:28:05.90$vck44/va=5,3 2006.285.20:28:05.90#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.20:28:05.90#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.20:28:05.90#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:05.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:28:05.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:28:05.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:28:05.96#ibcon#enter wrdev, iclass 11, count 2 2006.285.20:28:05.96#ibcon#first serial, iclass 11, count 2 2006.285.20:28:05.96#ibcon#enter sib2, iclass 11, count 2 2006.285.20:28:05.96#ibcon#flushed, iclass 11, count 2 2006.285.20:28:05.96#ibcon#about to write, iclass 11, count 2 2006.285.20:28:05.96#ibcon#wrote, iclass 11, count 2 2006.285.20:28:05.96#ibcon#about to read 3, iclass 11, count 2 2006.285.20:28:05.98#ibcon#read 3, iclass 11, count 2 2006.285.20:28:05.98#ibcon#about to read 4, iclass 11, count 2 2006.285.20:28:05.98#ibcon#read 4, iclass 11, count 2 2006.285.20:28:05.98#ibcon#about to read 5, iclass 11, count 2 2006.285.20:28:05.98#ibcon#read 5, iclass 11, count 2 2006.285.20:28:05.98#ibcon#about to read 6, iclass 11, count 2 2006.285.20:28:05.98#ibcon#read 6, iclass 11, count 2 2006.285.20:28:05.98#ibcon#end of sib2, iclass 11, count 2 2006.285.20:28:05.98#ibcon#*mode == 0, iclass 11, count 2 2006.285.20:28:05.98#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.20:28:05.98#ibcon#[25=AT05-03\r\n] 2006.285.20:28:05.98#ibcon#*before write, iclass 11, count 2 2006.285.20:28:05.98#ibcon#enter sib2, iclass 11, count 2 2006.285.20:28:05.98#ibcon#flushed, iclass 11, count 2 2006.285.20:28:05.98#ibcon#about to write, iclass 11, count 2 2006.285.20:28:05.98#ibcon#wrote, iclass 11, count 2 2006.285.20:28:05.98#ibcon#about to read 3, iclass 11, count 2 2006.285.20:28:06.01#ibcon#read 3, iclass 11, count 2 2006.285.20:28:06.01#ibcon#about to read 4, iclass 11, count 2 2006.285.20:28:06.01#ibcon#read 4, iclass 11, count 2 2006.285.20:28:06.01#ibcon#about to read 5, iclass 11, count 2 2006.285.20:28:06.01#ibcon#read 5, iclass 11, count 2 2006.285.20:28:06.01#ibcon#about to read 6, iclass 11, count 2 2006.285.20:28:06.01#ibcon#read 6, iclass 11, count 2 2006.285.20:28:06.01#ibcon#end of sib2, iclass 11, count 2 2006.285.20:28:06.01#ibcon#*after write, iclass 11, count 2 2006.285.20:28:06.01#ibcon#*before return 0, iclass 11, count 2 2006.285.20:28:06.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:28:06.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:28:06.01#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.20:28:06.01#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:06.01#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:28:06.13#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:28:06.13#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:28:06.13#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:28:06.13#ibcon#first serial, iclass 11, count 0 2006.285.20:28:06.13#ibcon#enter sib2, iclass 11, count 0 2006.285.20:28:06.13#ibcon#flushed, iclass 11, count 0 2006.285.20:28:06.13#ibcon#about to write, iclass 11, count 0 2006.285.20:28:06.13#ibcon#wrote, iclass 11, count 0 2006.285.20:28:06.13#ibcon#about to read 3, iclass 11, count 0 2006.285.20:28:06.15#ibcon#read 3, iclass 11, count 0 2006.285.20:28:06.15#ibcon#about to read 4, iclass 11, count 0 2006.285.20:28:06.15#ibcon#read 4, iclass 11, count 0 2006.285.20:28:06.15#ibcon#about to read 5, iclass 11, count 0 2006.285.20:28:06.15#ibcon#read 5, iclass 11, count 0 2006.285.20:28:06.15#ibcon#about to read 6, iclass 11, count 0 2006.285.20:28:06.15#ibcon#read 6, iclass 11, count 0 2006.285.20:28:06.15#ibcon#end of sib2, iclass 11, count 0 2006.285.20:28:06.15#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:28:06.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:28:06.15#ibcon#[25=USB\r\n] 2006.285.20:28:06.15#ibcon#*before write, iclass 11, count 0 2006.285.20:28:06.15#ibcon#enter sib2, iclass 11, count 0 2006.285.20:28:06.15#ibcon#flushed, iclass 11, count 0 2006.285.20:28:06.15#ibcon#about to write, iclass 11, count 0 2006.285.20:28:06.15#ibcon#wrote, iclass 11, count 0 2006.285.20:28:06.15#ibcon#about to read 3, iclass 11, count 0 2006.285.20:28:06.18#ibcon#read 3, iclass 11, count 0 2006.285.20:28:06.18#ibcon#about to read 4, iclass 11, count 0 2006.285.20:28:06.18#ibcon#read 4, iclass 11, count 0 2006.285.20:28:06.18#ibcon#about to read 5, iclass 11, count 0 2006.285.20:28:06.18#ibcon#read 5, iclass 11, count 0 2006.285.20:28:06.18#ibcon#about to read 6, iclass 11, count 0 2006.285.20:28:06.18#ibcon#read 6, iclass 11, count 0 2006.285.20:28:06.18#ibcon#end of sib2, iclass 11, count 0 2006.285.20:28:06.18#ibcon#*after write, iclass 11, count 0 2006.285.20:28:06.18#ibcon#*before return 0, iclass 11, count 0 2006.285.20:28:06.18#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:28:06.18#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:28:06.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:28:06.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:28:06.18$vck44/valo=6,814.99 2006.285.20:28:06.18#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.20:28:06.18#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.20:28:06.18#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:06.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:28:06.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:28:06.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:28:06.18#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:28:06.18#ibcon#first serial, iclass 13, count 0 2006.285.20:28:06.18#ibcon#enter sib2, iclass 13, count 0 2006.285.20:28:06.18#ibcon#flushed, iclass 13, count 0 2006.285.20:28:06.18#ibcon#about to write, iclass 13, count 0 2006.285.20:28:06.18#ibcon#wrote, iclass 13, count 0 2006.285.20:28:06.18#ibcon#about to read 3, iclass 13, count 0 2006.285.20:28:06.20#ibcon#read 3, iclass 13, count 0 2006.285.20:28:06.20#ibcon#about to read 4, iclass 13, count 0 2006.285.20:28:06.20#ibcon#read 4, iclass 13, count 0 2006.285.20:28:06.20#ibcon#about to read 5, iclass 13, count 0 2006.285.20:28:06.20#ibcon#read 5, iclass 13, count 0 2006.285.20:28:06.20#ibcon#about to read 6, iclass 13, count 0 2006.285.20:28:06.20#ibcon#read 6, iclass 13, count 0 2006.285.20:28:06.20#ibcon#end of sib2, iclass 13, count 0 2006.285.20:28:06.20#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:28:06.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:28:06.20#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.20:28:06.20#ibcon#*before write, iclass 13, count 0 2006.285.20:28:06.20#ibcon#enter sib2, iclass 13, count 0 2006.285.20:28:06.20#ibcon#flushed, iclass 13, count 0 2006.285.20:28:06.20#ibcon#about to write, iclass 13, count 0 2006.285.20:28:06.20#ibcon#wrote, iclass 13, count 0 2006.285.20:28:06.20#ibcon#about to read 3, iclass 13, count 0 2006.285.20:28:06.24#ibcon#read 3, iclass 13, count 0 2006.285.20:28:06.24#ibcon#about to read 4, iclass 13, count 0 2006.285.20:28:06.24#ibcon#read 4, iclass 13, count 0 2006.285.20:28:06.24#ibcon#about to read 5, iclass 13, count 0 2006.285.20:28:06.24#ibcon#read 5, iclass 13, count 0 2006.285.20:28:06.24#ibcon#about to read 6, iclass 13, count 0 2006.285.20:28:06.24#ibcon#read 6, iclass 13, count 0 2006.285.20:28:06.24#ibcon#end of sib2, iclass 13, count 0 2006.285.20:28:06.24#ibcon#*after write, iclass 13, count 0 2006.285.20:28:06.24#ibcon#*before return 0, iclass 13, count 0 2006.285.20:28:06.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:28:06.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:28:06.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:28:06.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:28:06.24$vck44/va=6,4 2006.285.20:28:06.24#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.20:28:06.24#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.20:28:06.24#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:06.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:28:06.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:28:06.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:28:06.30#ibcon#enter wrdev, iclass 15, count 2 2006.285.20:28:06.30#ibcon#first serial, iclass 15, count 2 2006.285.20:28:06.30#ibcon#enter sib2, iclass 15, count 2 2006.285.20:28:06.30#ibcon#flushed, iclass 15, count 2 2006.285.20:28:06.30#ibcon#about to write, iclass 15, count 2 2006.285.20:28:06.30#ibcon#wrote, iclass 15, count 2 2006.285.20:28:06.30#ibcon#about to read 3, iclass 15, count 2 2006.285.20:28:06.32#ibcon#read 3, iclass 15, count 2 2006.285.20:28:06.32#ibcon#about to read 4, iclass 15, count 2 2006.285.20:28:06.32#ibcon#read 4, iclass 15, count 2 2006.285.20:28:06.32#ibcon#about to read 5, iclass 15, count 2 2006.285.20:28:06.32#ibcon#read 5, iclass 15, count 2 2006.285.20:28:06.32#ibcon#about to read 6, iclass 15, count 2 2006.285.20:28:06.32#ibcon#read 6, iclass 15, count 2 2006.285.20:28:06.32#ibcon#end of sib2, iclass 15, count 2 2006.285.20:28:06.32#ibcon#*mode == 0, iclass 15, count 2 2006.285.20:28:06.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.20:28:06.32#ibcon#[25=AT06-04\r\n] 2006.285.20:28:06.32#ibcon#*before write, iclass 15, count 2 2006.285.20:28:06.32#ibcon#enter sib2, iclass 15, count 2 2006.285.20:28:06.32#ibcon#flushed, iclass 15, count 2 2006.285.20:28:06.32#ibcon#about to write, iclass 15, count 2 2006.285.20:28:06.32#ibcon#wrote, iclass 15, count 2 2006.285.20:28:06.32#ibcon#about to read 3, iclass 15, count 2 2006.285.20:28:06.35#ibcon#read 3, iclass 15, count 2 2006.285.20:28:06.35#ibcon#about to read 4, iclass 15, count 2 2006.285.20:28:06.35#ibcon#read 4, iclass 15, count 2 2006.285.20:28:06.35#ibcon#about to read 5, iclass 15, count 2 2006.285.20:28:06.35#ibcon#read 5, iclass 15, count 2 2006.285.20:28:06.35#ibcon#about to read 6, iclass 15, count 2 2006.285.20:28:06.35#ibcon#read 6, iclass 15, count 2 2006.285.20:28:06.35#ibcon#end of sib2, iclass 15, count 2 2006.285.20:28:06.35#ibcon#*after write, iclass 15, count 2 2006.285.20:28:06.35#ibcon#*before return 0, iclass 15, count 2 2006.285.20:28:06.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:28:06.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:28:06.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.20:28:06.35#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:06.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:28:06.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:28:06.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:28:06.47#ibcon#enter wrdev, iclass 15, count 0 2006.285.20:28:06.47#ibcon#first serial, iclass 15, count 0 2006.285.20:28:06.47#ibcon#enter sib2, iclass 15, count 0 2006.285.20:28:06.47#ibcon#flushed, iclass 15, count 0 2006.285.20:28:06.47#ibcon#about to write, iclass 15, count 0 2006.285.20:28:06.47#ibcon#wrote, iclass 15, count 0 2006.285.20:28:06.47#ibcon#about to read 3, iclass 15, count 0 2006.285.20:28:06.49#ibcon#read 3, iclass 15, count 0 2006.285.20:28:06.49#ibcon#about to read 4, iclass 15, count 0 2006.285.20:28:06.49#ibcon#read 4, iclass 15, count 0 2006.285.20:28:06.49#ibcon#about to read 5, iclass 15, count 0 2006.285.20:28:06.49#ibcon#read 5, iclass 15, count 0 2006.285.20:28:06.49#ibcon#about to read 6, iclass 15, count 0 2006.285.20:28:06.49#ibcon#read 6, iclass 15, count 0 2006.285.20:28:06.49#ibcon#end of sib2, iclass 15, count 0 2006.285.20:28:06.49#ibcon#*mode == 0, iclass 15, count 0 2006.285.20:28:06.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.20:28:06.49#ibcon#[25=USB\r\n] 2006.285.20:28:06.49#ibcon#*before write, iclass 15, count 0 2006.285.20:28:06.49#ibcon#enter sib2, iclass 15, count 0 2006.285.20:28:06.49#ibcon#flushed, iclass 15, count 0 2006.285.20:28:06.49#ibcon#about to write, iclass 15, count 0 2006.285.20:28:06.49#ibcon#wrote, iclass 15, count 0 2006.285.20:28:06.49#ibcon#about to read 3, iclass 15, count 0 2006.285.20:28:06.52#ibcon#read 3, iclass 15, count 0 2006.285.20:28:06.52#ibcon#about to read 4, iclass 15, count 0 2006.285.20:28:06.52#ibcon#read 4, iclass 15, count 0 2006.285.20:28:06.52#ibcon#about to read 5, iclass 15, count 0 2006.285.20:28:06.52#ibcon#read 5, iclass 15, count 0 2006.285.20:28:06.52#ibcon#about to read 6, iclass 15, count 0 2006.285.20:28:06.52#ibcon#read 6, iclass 15, count 0 2006.285.20:28:06.52#ibcon#end of sib2, iclass 15, count 0 2006.285.20:28:06.52#ibcon#*after write, iclass 15, count 0 2006.285.20:28:06.52#ibcon#*before return 0, iclass 15, count 0 2006.285.20:28:06.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:28:06.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:28:06.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.20:28:06.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.20:28:06.52$vck44/valo=7,864.99 2006.285.20:28:06.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.20:28:06.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.20:28:06.52#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:06.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:28:06.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:28:06.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:28:06.52#ibcon#enter wrdev, iclass 17, count 0 2006.285.20:28:06.52#ibcon#first serial, iclass 17, count 0 2006.285.20:28:06.52#ibcon#enter sib2, iclass 17, count 0 2006.285.20:28:06.52#ibcon#flushed, iclass 17, count 0 2006.285.20:28:06.52#ibcon#about to write, iclass 17, count 0 2006.285.20:28:06.52#ibcon#wrote, iclass 17, count 0 2006.285.20:28:06.52#ibcon#about to read 3, iclass 17, count 0 2006.285.20:28:06.54#ibcon#read 3, iclass 17, count 0 2006.285.20:28:06.54#ibcon#about to read 4, iclass 17, count 0 2006.285.20:28:06.54#ibcon#read 4, iclass 17, count 0 2006.285.20:28:06.54#ibcon#about to read 5, iclass 17, count 0 2006.285.20:28:06.54#ibcon#read 5, iclass 17, count 0 2006.285.20:28:06.54#ibcon#about to read 6, iclass 17, count 0 2006.285.20:28:06.54#ibcon#read 6, iclass 17, count 0 2006.285.20:28:06.54#ibcon#end of sib2, iclass 17, count 0 2006.285.20:28:06.54#ibcon#*mode == 0, iclass 17, count 0 2006.285.20:28:06.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.20:28:06.54#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.20:28:06.54#ibcon#*before write, iclass 17, count 0 2006.285.20:28:06.54#ibcon#enter sib2, iclass 17, count 0 2006.285.20:28:06.54#ibcon#flushed, iclass 17, count 0 2006.285.20:28:06.54#ibcon#about to write, iclass 17, count 0 2006.285.20:28:06.54#ibcon#wrote, iclass 17, count 0 2006.285.20:28:06.54#ibcon#about to read 3, iclass 17, count 0 2006.285.20:28:06.58#ibcon#read 3, iclass 17, count 0 2006.285.20:28:06.58#ibcon#about to read 4, iclass 17, count 0 2006.285.20:28:06.58#ibcon#read 4, iclass 17, count 0 2006.285.20:28:06.58#ibcon#about to read 5, iclass 17, count 0 2006.285.20:28:06.58#ibcon#read 5, iclass 17, count 0 2006.285.20:28:06.58#ibcon#about to read 6, iclass 17, count 0 2006.285.20:28:06.58#ibcon#read 6, iclass 17, count 0 2006.285.20:28:06.58#ibcon#end of sib2, iclass 17, count 0 2006.285.20:28:06.58#ibcon#*after write, iclass 17, count 0 2006.285.20:28:06.58#ibcon#*before return 0, iclass 17, count 0 2006.285.20:28:06.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:28:06.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:28:06.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.20:28:06.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.20:28:06.58$vck44/va=7,4 2006.285.20:28:06.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.20:28:06.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.20:28:06.58#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:06.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:28:06.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:28:06.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:28:06.64#ibcon#enter wrdev, iclass 19, count 2 2006.285.20:28:06.64#ibcon#first serial, iclass 19, count 2 2006.285.20:28:06.64#ibcon#enter sib2, iclass 19, count 2 2006.285.20:28:06.64#ibcon#flushed, iclass 19, count 2 2006.285.20:28:06.64#ibcon#about to write, iclass 19, count 2 2006.285.20:28:06.64#ibcon#wrote, iclass 19, count 2 2006.285.20:28:06.64#ibcon#about to read 3, iclass 19, count 2 2006.285.20:28:06.66#ibcon#read 3, iclass 19, count 2 2006.285.20:28:06.66#ibcon#about to read 4, iclass 19, count 2 2006.285.20:28:06.66#ibcon#read 4, iclass 19, count 2 2006.285.20:28:06.66#ibcon#about to read 5, iclass 19, count 2 2006.285.20:28:06.66#ibcon#read 5, iclass 19, count 2 2006.285.20:28:06.66#ibcon#about to read 6, iclass 19, count 2 2006.285.20:28:06.66#ibcon#read 6, iclass 19, count 2 2006.285.20:28:06.66#ibcon#end of sib2, iclass 19, count 2 2006.285.20:28:06.66#ibcon#*mode == 0, iclass 19, count 2 2006.285.20:28:06.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.20:28:06.66#ibcon#[25=AT07-04\r\n] 2006.285.20:28:06.66#ibcon#*before write, iclass 19, count 2 2006.285.20:28:06.66#ibcon#enter sib2, iclass 19, count 2 2006.285.20:28:06.66#ibcon#flushed, iclass 19, count 2 2006.285.20:28:06.66#ibcon#about to write, iclass 19, count 2 2006.285.20:28:06.66#ibcon#wrote, iclass 19, count 2 2006.285.20:28:06.66#ibcon#about to read 3, iclass 19, count 2 2006.285.20:28:06.69#ibcon#read 3, iclass 19, count 2 2006.285.20:28:06.69#ibcon#about to read 4, iclass 19, count 2 2006.285.20:28:06.69#ibcon#read 4, iclass 19, count 2 2006.285.20:28:06.69#ibcon#about to read 5, iclass 19, count 2 2006.285.20:28:06.69#ibcon#read 5, iclass 19, count 2 2006.285.20:28:06.69#ibcon#about to read 6, iclass 19, count 2 2006.285.20:28:06.69#ibcon#read 6, iclass 19, count 2 2006.285.20:28:06.69#ibcon#end of sib2, iclass 19, count 2 2006.285.20:28:06.69#ibcon#*after write, iclass 19, count 2 2006.285.20:28:06.69#ibcon#*before return 0, iclass 19, count 2 2006.285.20:28:06.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:28:06.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:28:06.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.20:28:06.69#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:06.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:28:06.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:28:06.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:28:06.81#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:28:06.81#ibcon#first serial, iclass 19, count 0 2006.285.20:28:06.81#ibcon#enter sib2, iclass 19, count 0 2006.285.20:28:06.81#ibcon#flushed, iclass 19, count 0 2006.285.20:28:06.81#ibcon#about to write, iclass 19, count 0 2006.285.20:28:06.81#ibcon#wrote, iclass 19, count 0 2006.285.20:28:06.81#ibcon#about to read 3, iclass 19, count 0 2006.285.20:28:06.83#ibcon#read 3, iclass 19, count 0 2006.285.20:28:06.83#ibcon#about to read 4, iclass 19, count 0 2006.285.20:28:06.83#ibcon#read 4, iclass 19, count 0 2006.285.20:28:06.83#ibcon#about to read 5, iclass 19, count 0 2006.285.20:28:06.83#ibcon#read 5, iclass 19, count 0 2006.285.20:28:06.83#ibcon#about to read 6, iclass 19, count 0 2006.285.20:28:06.83#ibcon#read 6, iclass 19, count 0 2006.285.20:28:06.83#ibcon#end of sib2, iclass 19, count 0 2006.285.20:28:06.83#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:28:06.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:28:06.83#ibcon#[25=USB\r\n] 2006.285.20:28:06.83#ibcon#*before write, iclass 19, count 0 2006.285.20:28:06.83#ibcon#enter sib2, iclass 19, count 0 2006.285.20:28:06.83#ibcon#flushed, iclass 19, count 0 2006.285.20:28:06.83#ibcon#about to write, iclass 19, count 0 2006.285.20:28:06.83#ibcon#wrote, iclass 19, count 0 2006.285.20:28:06.83#ibcon#about to read 3, iclass 19, count 0 2006.285.20:28:06.86#ibcon#read 3, iclass 19, count 0 2006.285.20:28:06.86#ibcon#about to read 4, iclass 19, count 0 2006.285.20:28:06.86#ibcon#read 4, iclass 19, count 0 2006.285.20:28:06.86#ibcon#about to read 5, iclass 19, count 0 2006.285.20:28:06.86#ibcon#read 5, iclass 19, count 0 2006.285.20:28:06.86#ibcon#about to read 6, iclass 19, count 0 2006.285.20:28:06.86#ibcon#read 6, iclass 19, count 0 2006.285.20:28:06.86#ibcon#end of sib2, iclass 19, count 0 2006.285.20:28:06.86#ibcon#*after write, iclass 19, count 0 2006.285.20:28:06.86#ibcon#*before return 0, iclass 19, count 0 2006.285.20:28:06.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:28:06.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:28:06.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:28:06.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:28:06.86$vck44/valo=8,884.99 2006.285.20:28:06.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.20:28:06.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.20:28:06.86#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:06.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:28:06.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:28:06.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:28:06.86#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:28:06.86#ibcon#first serial, iclass 21, count 0 2006.285.20:28:06.86#ibcon#enter sib2, iclass 21, count 0 2006.285.20:28:06.86#ibcon#flushed, iclass 21, count 0 2006.285.20:28:06.86#ibcon#about to write, iclass 21, count 0 2006.285.20:28:06.86#ibcon#wrote, iclass 21, count 0 2006.285.20:28:06.86#ibcon#about to read 3, iclass 21, count 0 2006.285.20:28:06.88#ibcon#read 3, iclass 21, count 0 2006.285.20:28:07.30#ibcon#about to read 4, iclass 21, count 0 2006.285.20:28:07.30#ibcon#read 4, iclass 21, count 0 2006.285.20:28:07.30#ibcon#about to read 5, iclass 21, count 0 2006.285.20:28:07.30#ibcon#read 5, iclass 21, count 0 2006.285.20:28:07.30#ibcon#about to read 6, iclass 21, count 0 2006.285.20:28:07.30#ibcon#read 6, iclass 21, count 0 2006.285.20:28:07.30#ibcon#end of sib2, iclass 21, count 0 2006.285.20:28:07.30#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:28:07.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:28:07.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.20:28:07.30#ibcon#*before write, iclass 21, count 0 2006.285.20:28:07.30#ibcon#enter sib2, iclass 21, count 0 2006.285.20:28:07.30#ibcon#flushed, iclass 21, count 0 2006.285.20:28:07.30#ibcon#about to write, iclass 21, count 0 2006.285.20:28:07.30#ibcon#wrote, iclass 21, count 0 2006.285.20:28:07.30#ibcon#about to read 3, iclass 21, count 0 2006.285.20:28:07.34#abcon#<5=/06 0.3 1.2 14.411001015.4\r\n> 2006.285.20:28:07.34#ibcon#read 3, iclass 21, count 0 2006.285.20:28:07.34#ibcon#about to read 4, iclass 21, count 0 2006.285.20:28:07.34#ibcon#read 4, iclass 21, count 0 2006.285.20:28:07.34#ibcon#about to read 5, iclass 21, count 0 2006.285.20:28:07.34#ibcon#read 5, iclass 21, count 0 2006.285.20:28:07.34#ibcon#about to read 6, iclass 21, count 0 2006.285.20:28:07.34#ibcon#read 6, iclass 21, count 0 2006.285.20:28:07.34#ibcon#end of sib2, iclass 21, count 0 2006.285.20:28:07.34#ibcon#*after write, iclass 21, count 0 2006.285.20:28:07.34#ibcon#*before return 0, iclass 21, count 0 2006.285.20:28:07.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:28:07.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:28:07.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:28:07.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:28:07.34$vck44/va=8,3 2006.285.20:28:07.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.20:28:07.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.20:28:07.34#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:07.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:28:07.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:28:07.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:28:07.34#ibcon#enter wrdev, iclass 26, count 2 2006.285.20:28:07.34#ibcon#first serial, iclass 26, count 2 2006.285.20:28:07.34#ibcon#enter sib2, iclass 26, count 2 2006.285.20:28:07.34#ibcon#flushed, iclass 26, count 2 2006.285.20:28:07.34#ibcon#about to write, iclass 26, count 2 2006.285.20:28:07.34#ibcon#wrote, iclass 26, count 2 2006.285.20:28:07.34#ibcon#about to read 3, iclass 26, count 2 2006.285.20:28:07.36#abcon#{5=INTERFACE CLEAR} 2006.285.20:28:07.36#ibcon#read 3, iclass 26, count 2 2006.285.20:28:07.36#ibcon#about to read 4, iclass 26, count 2 2006.285.20:28:07.36#ibcon#read 4, iclass 26, count 2 2006.285.20:28:07.36#ibcon#about to read 5, iclass 26, count 2 2006.285.20:28:07.36#ibcon#read 5, iclass 26, count 2 2006.285.20:28:07.36#ibcon#about to read 6, iclass 26, count 2 2006.285.20:28:07.36#ibcon#read 6, iclass 26, count 2 2006.285.20:28:07.36#ibcon#end of sib2, iclass 26, count 2 2006.285.20:28:07.36#ibcon#*mode == 0, iclass 26, count 2 2006.285.20:28:07.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.20:28:07.36#ibcon#[25=AT08-03\r\n] 2006.285.20:28:07.36#ibcon#*before write, iclass 26, count 2 2006.285.20:28:07.36#ibcon#enter sib2, iclass 26, count 2 2006.285.20:28:07.36#ibcon#flushed, iclass 26, count 2 2006.285.20:28:07.36#ibcon#about to write, iclass 26, count 2 2006.285.20:28:07.36#ibcon#wrote, iclass 26, count 2 2006.285.20:28:07.36#ibcon#about to read 3, iclass 26, count 2 2006.285.20:28:07.39#ibcon#read 3, iclass 26, count 2 2006.285.20:28:07.39#ibcon#about to read 4, iclass 26, count 2 2006.285.20:28:07.39#ibcon#read 4, iclass 26, count 2 2006.285.20:28:07.39#ibcon#about to read 5, iclass 26, count 2 2006.285.20:28:07.39#ibcon#read 5, iclass 26, count 2 2006.285.20:28:07.39#ibcon#about to read 6, iclass 26, count 2 2006.285.20:28:07.39#ibcon#read 6, iclass 26, count 2 2006.285.20:28:07.39#ibcon#end of sib2, iclass 26, count 2 2006.285.20:28:07.39#ibcon#*after write, iclass 26, count 2 2006.285.20:28:07.39#ibcon#*before return 0, iclass 26, count 2 2006.285.20:28:07.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:28:07.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:28:07.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.20:28:07.39#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:07.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:28:07.42#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:28:07.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:28:07.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:28:07.51#ibcon#enter wrdev, iclass 26, count 0 2006.285.20:28:07.51#ibcon#first serial, iclass 26, count 0 2006.285.20:28:07.51#ibcon#enter sib2, iclass 26, count 0 2006.285.20:28:07.51#ibcon#flushed, iclass 26, count 0 2006.285.20:28:07.51#ibcon#about to write, iclass 26, count 0 2006.285.20:28:07.51#ibcon#wrote, iclass 26, count 0 2006.285.20:28:07.51#ibcon#about to read 3, iclass 26, count 0 2006.285.20:28:07.53#ibcon#read 3, iclass 26, count 0 2006.285.20:28:07.53#ibcon#about to read 4, iclass 26, count 0 2006.285.20:28:07.53#ibcon#read 4, iclass 26, count 0 2006.285.20:28:07.53#ibcon#about to read 5, iclass 26, count 0 2006.285.20:28:07.53#ibcon#read 5, iclass 26, count 0 2006.285.20:28:07.53#ibcon#about to read 6, iclass 26, count 0 2006.285.20:28:07.53#ibcon#read 6, iclass 26, count 0 2006.285.20:28:07.53#ibcon#end of sib2, iclass 26, count 0 2006.285.20:28:07.53#ibcon#*mode == 0, iclass 26, count 0 2006.285.20:28:07.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.20:28:07.53#ibcon#[25=USB\r\n] 2006.285.20:28:07.53#ibcon#*before write, iclass 26, count 0 2006.285.20:28:07.53#ibcon#enter sib2, iclass 26, count 0 2006.285.20:28:07.53#ibcon#flushed, iclass 26, count 0 2006.285.20:28:07.53#ibcon#about to write, iclass 26, count 0 2006.285.20:28:07.53#ibcon#wrote, iclass 26, count 0 2006.285.20:28:07.53#ibcon#about to read 3, iclass 26, count 0 2006.285.20:28:07.56#ibcon#read 3, iclass 26, count 0 2006.285.20:28:07.56#ibcon#about to read 4, iclass 26, count 0 2006.285.20:28:07.56#ibcon#read 4, iclass 26, count 0 2006.285.20:28:07.56#ibcon#about to read 5, iclass 26, count 0 2006.285.20:28:07.56#ibcon#read 5, iclass 26, count 0 2006.285.20:28:07.56#ibcon#about to read 6, iclass 26, count 0 2006.285.20:28:07.56#ibcon#read 6, iclass 26, count 0 2006.285.20:28:07.56#ibcon#end of sib2, iclass 26, count 0 2006.285.20:28:07.56#ibcon#*after write, iclass 26, count 0 2006.285.20:28:07.56#ibcon#*before return 0, iclass 26, count 0 2006.285.20:28:07.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:28:07.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:28:07.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.20:28:07.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.20:28:07.56$vck44/vblo=1,629.99 2006.285.20:28:07.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.20:28:07.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.20:28:07.56#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:07.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:28:07.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:28:07.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:28:07.56#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:28:07.56#ibcon#first serial, iclass 29, count 0 2006.285.20:28:07.56#ibcon#enter sib2, iclass 29, count 0 2006.285.20:28:07.56#ibcon#flushed, iclass 29, count 0 2006.285.20:28:07.56#ibcon#about to write, iclass 29, count 0 2006.285.20:28:07.56#ibcon#wrote, iclass 29, count 0 2006.285.20:28:07.56#ibcon#about to read 3, iclass 29, count 0 2006.285.20:28:07.58#ibcon#read 3, iclass 29, count 0 2006.285.20:28:07.58#ibcon#about to read 4, iclass 29, count 0 2006.285.20:28:07.58#ibcon#read 4, iclass 29, count 0 2006.285.20:28:07.58#ibcon#about to read 5, iclass 29, count 0 2006.285.20:28:07.58#ibcon#read 5, iclass 29, count 0 2006.285.20:28:07.58#ibcon#about to read 6, iclass 29, count 0 2006.285.20:28:07.58#ibcon#read 6, iclass 29, count 0 2006.285.20:28:07.58#ibcon#end of sib2, iclass 29, count 0 2006.285.20:28:07.58#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:28:07.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:28:07.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.20:28:07.58#ibcon#*before write, iclass 29, count 0 2006.285.20:28:07.58#ibcon#enter sib2, iclass 29, count 0 2006.285.20:28:07.58#ibcon#flushed, iclass 29, count 0 2006.285.20:28:07.58#ibcon#about to write, iclass 29, count 0 2006.285.20:28:07.58#ibcon#wrote, iclass 29, count 0 2006.285.20:28:07.58#ibcon#about to read 3, iclass 29, count 0 2006.285.20:28:07.62#ibcon#read 3, iclass 29, count 0 2006.285.20:28:07.62#ibcon#about to read 4, iclass 29, count 0 2006.285.20:28:07.62#ibcon#read 4, iclass 29, count 0 2006.285.20:28:07.62#ibcon#about to read 5, iclass 29, count 0 2006.285.20:28:07.62#ibcon#read 5, iclass 29, count 0 2006.285.20:28:07.62#ibcon#about to read 6, iclass 29, count 0 2006.285.20:28:07.62#ibcon#read 6, iclass 29, count 0 2006.285.20:28:07.62#ibcon#end of sib2, iclass 29, count 0 2006.285.20:28:07.62#ibcon#*after write, iclass 29, count 0 2006.285.20:28:07.62#ibcon#*before return 0, iclass 29, count 0 2006.285.20:28:07.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:28:07.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:28:07.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:28:07.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:28:07.62$vck44/vb=1,4 2006.285.20:28:07.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.20:28:07.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.20:28:07.62#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:07.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:28:07.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:28:07.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:28:07.62#ibcon#enter wrdev, iclass 31, count 2 2006.285.20:28:07.62#ibcon#first serial, iclass 31, count 2 2006.285.20:28:07.62#ibcon#enter sib2, iclass 31, count 2 2006.285.20:28:07.62#ibcon#flushed, iclass 31, count 2 2006.285.20:28:07.62#ibcon#about to write, iclass 31, count 2 2006.285.20:28:07.62#ibcon#wrote, iclass 31, count 2 2006.285.20:28:07.62#ibcon#about to read 3, iclass 31, count 2 2006.285.20:28:07.64#ibcon#read 3, iclass 31, count 2 2006.285.20:28:07.64#ibcon#about to read 4, iclass 31, count 2 2006.285.20:28:07.64#ibcon#read 4, iclass 31, count 2 2006.285.20:28:07.64#ibcon#about to read 5, iclass 31, count 2 2006.285.20:28:07.64#ibcon#read 5, iclass 31, count 2 2006.285.20:28:07.64#ibcon#about to read 6, iclass 31, count 2 2006.285.20:28:07.64#ibcon#read 6, iclass 31, count 2 2006.285.20:28:07.64#ibcon#end of sib2, iclass 31, count 2 2006.285.20:28:07.64#ibcon#*mode == 0, iclass 31, count 2 2006.285.20:28:07.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.20:28:07.64#ibcon#[27=AT01-04\r\n] 2006.285.20:28:07.64#ibcon#*before write, iclass 31, count 2 2006.285.20:28:07.64#ibcon#enter sib2, iclass 31, count 2 2006.285.20:28:07.64#ibcon#flushed, iclass 31, count 2 2006.285.20:28:07.64#ibcon#about to write, iclass 31, count 2 2006.285.20:28:07.64#ibcon#wrote, iclass 31, count 2 2006.285.20:28:07.64#ibcon#about to read 3, iclass 31, count 2 2006.285.20:28:07.67#ibcon#read 3, iclass 31, count 2 2006.285.20:28:07.67#ibcon#about to read 4, iclass 31, count 2 2006.285.20:28:07.67#ibcon#read 4, iclass 31, count 2 2006.285.20:28:07.67#ibcon#about to read 5, iclass 31, count 2 2006.285.20:28:07.67#ibcon#read 5, iclass 31, count 2 2006.285.20:28:07.67#ibcon#about to read 6, iclass 31, count 2 2006.285.20:28:07.67#ibcon#read 6, iclass 31, count 2 2006.285.20:28:07.67#ibcon#end of sib2, iclass 31, count 2 2006.285.20:28:07.67#ibcon#*after write, iclass 31, count 2 2006.285.20:28:07.67#ibcon#*before return 0, iclass 31, count 2 2006.285.20:28:07.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:28:07.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:28:07.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.20:28:07.67#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:07.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:28:07.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:28:07.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:28:07.79#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:28:07.79#ibcon#first serial, iclass 31, count 0 2006.285.20:28:07.79#ibcon#enter sib2, iclass 31, count 0 2006.285.20:28:07.79#ibcon#flushed, iclass 31, count 0 2006.285.20:28:07.79#ibcon#about to write, iclass 31, count 0 2006.285.20:28:07.79#ibcon#wrote, iclass 31, count 0 2006.285.20:28:07.79#ibcon#about to read 3, iclass 31, count 0 2006.285.20:28:07.81#ibcon#read 3, iclass 31, count 0 2006.285.20:28:07.81#ibcon#about to read 4, iclass 31, count 0 2006.285.20:28:07.81#ibcon#read 4, iclass 31, count 0 2006.285.20:28:07.81#ibcon#about to read 5, iclass 31, count 0 2006.285.20:28:07.81#ibcon#read 5, iclass 31, count 0 2006.285.20:28:07.81#ibcon#about to read 6, iclass 31, count 0 2006.285.20:28:07.81#ibcon#read 6, iclass 31, count 0 2006.285.20:28:07.81#ibcon#end of sib2, iclass 31, count 0 2006.285.20:28:07.81#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:28:07.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:28:07.81#ibcon#[27=USB\r\n] 2006.285.20:28:07.81#ibcon#*before write, iclass 31, count 0 2006.285.20:28:07.81#ibcon#enter sib2, iclass 31, count 0 2006.285.20:28:07.81#ibcon#flushed, iclass 31, count 0 2006.285.20:28:07.81#ibcon#about to write, iclass 31, count 0 2006.285.20:28:07.81#ibcon#wrote, iclass 31, count 0 2006.285.20:28:07.81#ibcon#about to read 3, iclass 31, count 0 2006.285.20:28:07.84#ibcon#read 3, iclass 31, count 0 2006.285.20:28:07.84#ibcon#about to read 4, iclass 31, count 0 2006.285.20:28:07.84#ibcon#read 4, iclass 31, count 0 2006.285.20:28:07.84#ibcon#about to read 5, iclass 31, count 0 2006.285.20:28:07.84#ibcon#read 5, iclass 31, count 0 2006.285.20:28:07.84#ibcon#about to read 6, iclass 31, count 0 2006.285.20:28:07.84#ibcon#read 6, iclass 31, count 0 2006.285.20:28:07.84#ibcon#end of sib2, iclass 31, count 0 2006.285.20:28:07.84#ibcon#*after write, iclass 31, count 0 2006.285.20:28:07.84#ibcon#*before return 0, iclass 31, count 0 2006.285.20:28:07.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:28:07.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:28:07.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:28:07.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:28:07.84$vck44/vblo=2,634.99 2006.285.20:28:07.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.20:28:07.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.20:28:07.84#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:07.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:28:07.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:28:07.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:28:07.84#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:28:07.84#ibcon#first serial, iclass 33, count 0 2006.285.20:28:07.84#ibcon#enter sib2, iclass 33, count 0 2006.285.20:28:07.84#ibcon#flushed, iclass 33, count 0 2006.285.20:28:07.84#ibcon#about to write, iclass 33, count 0 2006.285.20:28:07.84#ibcon#wrote, iclass 33, count 0 2006.285.20:28:07.84#ibcon#about to read 3, iclass 33, count 0 2006.285.20:28:07.86#ibcon#read 3, iclass 33, count 0 2006.285.20:28:08.01#ibcon#about to read 4, iclass 33, count 0 2006.285.20:28:08.01#ibcon#read 4, iclass 33, count 0 2006.285.20:28:08.01#ibcon#about to read 5, iclass 33, count 0 2006.285.20:28:08.01#ibcon#read 5, iclass 33, count 0 2006.285.20:28:08.01#ibcon#about to read 6, iclass 33, count 0 2006.285.20:28:08.01#ibcon#read 6, iclass 33, count 0 2006.285.20:28:08.01#ibcon#end of sib2, iclass 33, count 0 2006.285.20:28:08.01#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:28:08.01#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:28:08.01#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.20:28:08.01#ibcon#*before write, iclass 33, count 0 2006.285.20:28:08.01#ibcon#enter sib2, iclass 33, count 0 2006.285.20:28:08.01#ibcon#flushed, iclass 33, count 0 2006.285.20:28:08.01#ibcon#about to write, iclass 33, count 0 2006.285.20:28:08.01#ibcon#wrote, iclass 33, count 0 2006.285.20:28:08.01#ibcon#about to read 3, iclass 33, count 0 2006.285.20:28:08.05#ibcon#read 3, iclass 33, count 0 2006.285.20:28:08.05#ibcon#about to read 4, iclass 33, count 0 2006.285.20:28:08.05#ibcon#read 4, iclass 33, count 0 2006.285.20:28:08.05#ibcon#about to read 5, iclass 33, count 0 2006.285.20:28:08.05#ibcon#read 5, iclass 33, count 0 2006.285.20:28:08.05#ibcon#about to read 6, iclass 33, count 0 2006.285.20:28:08.05#ibcon#read 6, iclass 33, count 0 2006.285.20:28:08.05#ibcon#end of sib2, iclass 33, count 0 2006.285.20:28:08.05#ibcon#*after write, iclass 33, count 0 2006.285.20:28:08.05#ibcon#*before return 0, iclass 33, count 0 2006.285.20:28:08.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:28:08.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:28:08.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:28:08.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:28:08.05$vck44/vb=2,5 2006.285.20:28:08.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.20:28:08.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.20:28:08.05#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:08.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:28:08.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:28:08.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:28:08.05#ibcon#enter wrdev, iclass 35, count 2 2006.285.20:28:08.05#ibcon#first serial, iclass 35, count 2 2006.285.20:28:08.05#ibcon#enter sib2, iclass 35, count 2 2006.285.20:28:08.05#ibcon#flushed, iclass 35, count 2 2006.285.20:28:08.05#ibcon#about to write, iclass 35, count 2 2006.285.20:28:08.05#ibcon#wrote, iclass 35, count 2 2006.285.20:28:08.05#ibcon#about to read 3, iclass 35, count 2 2006.285.20:28:08.07#ibcon#read 3, iclass 35, count 2 2006.285.20:28:08.07#ibcon#about to read 4, iclass 35, count 2 2006.285.20:28:08.07#ibcon#read 4, iclass 35, count 2 2006.285.20:28:08.07#ibcon#about to read 5, iclass 35, count 2 2006.285.20:28:08.07#ibcon#read 5, iclass 35, count 2 2006.285.20:28:08.07#ibcon#about to read 6, iclass 35, count 2 2006.285.20:28:08.07#ibcon#read 6, iclass 35, count 2 2006.285.20:28:08.07#ibcon#end of sib2, iclass 35, count 2 2006.285.20:28:08.07#ibcon#*mode == 0, iclass 35, count 2 2006.285.20:28:08.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.20:28:08.07#ibcon#[27=AT02-05\r\n] 2006.285.20:28:08.07#ibcon#*before write, iclass 35, count 2 2006.285.20:28:08.07#ibcon#enter sib2, iclass 35, count 2 2006.285.20:28:08.07#ibcon#flushed, iclass 35, count 2 2006.285.20:28:08.07#ibcon#about to write, iclass 35, count 2 2006.285.20:28:08.07#ibcon#wrote, iclass 35, count 2 2006.285.20:28:08.07#ibcon#about to read 3, iclass 35, count 2 2006.285.20:28:08.10#ibcon#read 3, iclass 35, count 2 2006.285.20:28:08.10#ibcon#about to read 4, iclass 35, count 2 2006.285.20:28:08.10#ibcon#read 4, iclass 35, count 2 2006.285.20:28:08.10#ibcon#about to read 5, iclass 35, count 2 2006.285.20:28:08.10#ibcon#read 5, iclass 35, count 2 2006.285.20:28:08.10#ibcon#about to read 6, iclass 35, count 2 2006.285.20:28:08.10#ibcon#read 6, iclass 35, count 2 2006.285.20:28:08.10#ibcon#end of sib2, iclass 35, count 2 2006.285.20:28:08.10#ibcon#*after write, iclass 35, count 2 2006.285.20:28:08.10#ibcon#*before return 0, iclass 35, count 2 2006.285.20:28:08.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:28:08.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:28:08.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.20:28:08.10#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:08.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:28:08.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:28:08.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:28:08.22#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:28:08.22#ibcon#first serial, iclass 35, count 0 2006.285.20:28:08.22#ibcon#enter sib2, iclass 35, count 0 2006.285.20:28:08.22#ibcon#flushed, iclass 35, count 0 2006.285.20:28:08.22#ibcon#about to write, iclass 35, count 0 2006.285.20:28:08.22#ibcon#wrote, iclass 35, count 0 2006.285.20:28:08.22#ibcon#about to read 3, iclass 35, count 0 2006.285.20:28:08.24#ibcon#read 3, iclass 35, count 0 2006.285.20:28:08.24#ibcon#about to read 4, iclass 35, count 0 2006.285.20:28:08.24#ibcon#read 4, iclass 35, count 0 2006.285.20:28:08.24#ibcon#about to read 5, iclass 35, count 0 2006.285.20:28:08.24#ibcon#read 5, iclass 35, count 0 2006.285.20:28:08.24#ibcon#about to read 6, iclass 35, count 0 2006.285.20:28:08.24#ibcon#read 6, iclass 35, count 0 2006.285.20:28:08.24#ibcon#end of sib2, iclass 35, count 0 2006.285.20:28:08.24#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:28:08.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:28:08.24#ibcon#[27=USB\r\n] 2006.285.20:28:08.24#ibcon#*before write, iclass 35, count 0 2006.285.20:28:08.24#ibcon#enter sib2, iclass 35, count 0 2006.285.20:28:08.24#ibcon#flushed, iclass 35, count 0 2006.285.20:28:08.24#ibcon#about to write, iclass 35, count 0 2006.285.20:28:08.24#ibcon#wrote, iclass 35, count 0 2006.285.20:28:08.24#ibcon#about to read 3, iclass 35, count 0 2006.285.20:28:08.27#ibcon#read 3, iclass 35, count 0 2006.285.20:28:08.27#ibcon#about to read 4, iclass 35, count 0 2006.285.20:28:08.27#ibcon#read 4, iclass 35, count 0 2006.285.20:28:08.27#ibcon#about to read 5, iclass 35, count 0 2006.285.20:28:08.27#ibcon#read 5, iclass 35, count 0 2006.285.20:28:08.27#ibcon#about to read 6, iclass 35, count 0 2006.285.20:28:08.27#ibcon#read 6, iclass 35, count 0 2006.285.20:28:08.27#ibcon#end of sib2, iclass 35, count 0 2006.285.20:28:08.27#ibcon#*after write, iclass 35, count 0 2006.285.20:28:08.27#ibcon#*before return 0, iclass 35, count 0 2006.285.20:28:08.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:28:08.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:28:08.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:28:08.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:28:08.27$vck44/vblo=3,649.99 2006.285.20:28:08.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.20:28:08.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.20:28:08.27#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:08.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:28:08.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:28:08.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:28:08.27#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:28:08.27#ibcon#first serial, iclass 37, count 0 2006.285.20:28:08.27#ibcon#enter sib2, iclass 37, count 0 2006.285.20:28:08.27#ibcon#flushed, iclass 37, count 0 2006.285.20:28:08.27#ibcon#about to write, iclass 37, count 0 2006.285.20:28:08.27#ibcon#wrote, iclass 37, count 0 2006.285.20:28:08.27#ibcon#about to read 3, iclass 37, count 0 2006.285.20:28:08.29#ibcon#read 3, iclass 37, count 0 2006.285.20:28:08.29#ibcon#about to read 4, iclass 37, count 0 2006.285.20:28:08.29#ibcon#read 4, iclass 37, count 0 2006.285.20:28:08.29#ibcon#about to read 5, iclass 37, count 0 2006.285.20:28:08.29#ibcon#read 5, iclass 37, count 0 2006.285.20:28:08.29#ibcon#about to read 6, iclass 37, count 0 2006.285.20:28:08.29#ibcon#read 6, iclass 37, count 0 2006.285.20:28:08.29#ibcon#end of sib2, iclass 37, count 0 2006.285.20:28:08.29#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:28:08.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:28:08.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.20:28:08.29#ibcon#*before write, iclass 37, count 0 2006.285.20:28:08.29#ibcon#enter sib2, iclass 37, count 0 2006.285.20:28:08.29#ibcon#flushed, iclass 37, count 0 2006.285.20:28:08.29#ibcon#about to write, iclass 37, count 0 2006.285.20:28:08.29#ibcon#wrote, iclass 37, count 0 2006.285.20:28:08.29#ibcon#about to read 3, iclass 37, count 0 2006.285.20:28:08.33#ibcon#read 3, iclass 37, count 0 2006.285.20:28:08.33#ibcon#about to read 4, iclass 37, count 0 2006.285.20:28:08.33#ibcon#read 4, iclass 37, count 0 2006.285.20:28:08.33#ibcon#about to read 5, iclass 37, count 0 2006.285.20:28:08.33#ibcon#read 5, iclass 37, count 0 2006.285.20:28:08.33#ibcon#about to read 6, iclass 37, count 0 2006.285.20:28:08.33#ibcon#read 6, iclass 37, count 0 2006.285.20:28:08.33#ibcon#end of sib2, iclass 37, count 0 2006.285.20:28:08.33#ibcon#*after write, iclass 37, count 0 2006.285.20:28:08.33#ibcon#*before return 0, iclass 37, count 0 2006.285.20:28:08.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:28:08.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:28:08.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:28:08.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:28:08.33$vck44/vb=3,4 2006.285.20:28:08.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.20:28:08.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.20:28:08.33#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:08.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:28:08.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:28:08.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:28:08.39#ibcon#enter wrdev, iclass 39, count 2 2006.285.20:28:08.39#ibcon#first serial, iclass 39, count 2 2006.285.20:28:08.39#ibcon#enter sib2, iclass 39, count 2 2006.285.20:28:08.39#ibcon#flushed, iclass 39, count 2 2006.285.20:28:08.39#ibcon#about to write, iclass 39, count 2 2006.285.20:28:08.39#ibcon#wrote, iclass 39, count 2 2006.285.20:28:08.39#ibcon#about to read 3, iclass 39, count 2 2006.285.20:28:08.41#ibcon#read 3, iclass 39, count 2 2006.285.20:28:08.41#ibcon#about to read 4, iclass 39, count 2 2006.285.20:28:08.41#ibcon#read 4, iclass 39, count 2 2006.285.20:28:08.41#ibcon#about to read 5, iclass 39, count 2 2006.285.20:28:08.41#ibcon#read 5, iclass 39, count 2 2006.285.20:28:08.41#ibcon#about to read 6, iclass 39, count 2 2006.285.20:28:08.41#ibcon#read 6, iclass 39, count 2 2006.285.20:28:08.41#ibcon#end of sib2, iclass 39, count 2 2006.285.20:28:08.41#ibcon#*mode == 0, iclass 39, count 2 2006.285.20:28:08.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.20:28:08.41#ibcon#[27=AT03-04\r\n] 2006.285.20:28:08.41#ibcon#*before write, iclass 39, count 2 2006.285.20:28:08.41#ibcon#enter sib2, iclass 39, count 2 2006.285.20:28:08.41#ibcon#flushed, iclass 39, count 2 2006.285.20:28:08.41#ibcon#about to write, iclass 39, count 2 2006.285.20:28:08.41#ibcon#wrote, iclass 39, count 2 2006.285.20:28:08.41#ibcon#about to read 3, iclass 39, count 2 2006.285.20:28:08.44#ibcon#read 3, iclass 39, count 2 2006.285.20:28:08.44#ibcon#about to read 4, iclass 39, count 2 2006.285.20:28:08.44#ibcon#read 4, iclass 39, count 2 2006.285.20:28:08.44#ibcon#about to read 5, iclass 39, count 2 2006.285.20:28:08.44#ibcon#read 5, iclass 39, count 2 2006.285.20:28:08.44#ibcon#about to read 6, iclass 39, count 2 2006.285.20:28:08.44#ibcon#read 6, iclass 39, count 2 2006.285.20:28:08.44#ibcon#end of sib2, iclass 39, count 2 2006.285.20:28:08.44#ibcon#*after write, iclass 39, count 2 2006.285.20:28:08.44#ibcon#*before return 0, iclass 39, count 2 2006.285.20:28:08.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:28:08.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:28:08.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.20:28:08.44#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:08.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:28:08.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:28:08.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:28:08.56#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:28:08.56#ibcon#first serial, iclass 39, count 0 2006.285.20:28:08.56#ibcon#enter sib2, iclass 39, count 0 2006.285.20:28:08.56#ibcon#flushed, iclass 39, count 0 2006.285.20:28:08.56#ibcon#about to write, iclass 39, count 0 2006.285.20:28:08.56#ibcon#wrote, iclass 39, count 0 2006.285.20:28:08.56#ibcon#about to read 3, iclass 39, count 0 2006.285.20:28:08.58#ibcon#read 3, iclass 39, count 0 2006.285.20:28:08.58#ibcon#about to read 4, iclass 39, count 0 2006.285.20:28:08.58#ibcon#read 4, iclass 39, count 0 2006.285.20:28:08.58#ibcon#about to read 5, iclass 39, count 0 2006.285.20:28:08.58#ibcon#read 5, iclass 39, count 0 2006.285.20:28:08.58#ibcon#about to read 6, iclass 39, count 0 2006.285.20:28:08.58#ibcon#read 6, iclass 39, count 0 2006.285.20:28:08.58#ibcon#end of sib2, iclass 39, count 0 2006.285.20:28:08.58#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:28:08.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:28:08.58#ibcon#[27=USB\r\n] 2006.285.20:28:08.58#ibcon#*before write, iclass 39, count 0 2006.285.20:28:08.58#ibcon#enter sib2, iclass 39, count 0 2006.285.20:28:08.58#ibcon#flushed, iclass 39, count 0 2006.285.20:28:08.58#ibcon#about to write, iclass 39, count 0 2006.285.20:28:08.58#ibcon#wrote, iclass 39, count 0 2006.285.20:28:08.58#ibcon#about to read 3, iclass 39, count 0 2006.285.20:28:08.61#ibcon#read 3, iclass 39, count 0 2006.285.20:28:08.61#ibcon#about to read 4, iclass 39, count 0 2006.285.20:28:08.61#ibcon#read 4, iclass 39, count 0 2006.285.20:28:08.61#ibcon#about to read 5, iclass 39, count 0 2006.285.20:28:08.61#ibcon#read 5, iclass 39, count 0 2006.285.20:28:08.61#ibcon#about to read 6, iclass 39, count 0 2006.285.20:28:08.61#ibcon#read 6, iclass 39, count 0 2006.285.20:28:08.61#ibcon#end of sib2, iclass 39, count 0 2006.285.20:28:08.61#ibcon#*after write, iclass 39, count 0 2006.285.20:28:08.61#ibcon#*before return 0, iclass 39, count 0 2006.285.20:28:08.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:28:08.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:28:08.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:28:08.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:28:08.61$vck44/vblo=4,679.99 2006.285.20:28:08.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.20:28:08.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.20:28:08.61#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:08.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:28:08.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:28:08.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:28:08.61#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:28:08.61#ibcon#first serial, iclass 3, count 0 2006.285.20:28:08.61#ibcon#enter sib2, iclass 3, count 0 2006.285.20:28:08.61#ibcon#flushed, iclass 3, count 0 2006.285.20:28:08.61#ibcon#about to write, iclass 3, count 0 2006.285.20:28:08.61#ibcon#wrote, iclass 3, count 0 2006.285.20:28:08.61#ibcon#about to read 3, iclass 3, count 0 2006.285.20:28:08.63#ibcon#read 3, iclass 3, count 0 2006.285.20:28:08.63#ibcon#about to read 4, iclass 3, count 0 2006.285.20:28:08.63#ibcon#read 4, iclass 3, count 0 2006.285.20:28:08.63#ibcon#about to read 5, iclass 3, count 0 2006.285.20:28:08.63#ibcon#read 5, iclass 3, count 0 2006.285.20:28:08.63#ibcon#about to read 6, iclass 3, count 0 2006.285.20:28:08.63#ibcon#read 6, iclass 3, count 0 2006.285.20:28:08.63#ibcon#end of sib2, iclass 3, count 0 2006.285.20:28:08.63#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:28:08.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:28:08.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.20:28:08.63#ibcon#*before write, iclass 3, count 0 2006.285.20:28:08.63#ibcon#enter sib2, iclass 3, count 0 2006.285.20:28:08.63#ibcon#flushed, iclass 3, count 0 2006.285.20:28:08.63#ibcon#about to write, iclass 3, count 0 2006.285.20:28:08.63#ibcon#wrote, iclass 3, count 0 2006.285.20:28:08.63#ibcon#about to read 3, iclass 3, count 0 2006.285.20:28:08.67#ibcon#read 3, iclass 3, count 0 2006.285.20:28:08.67#ibcon#about to read 4, iclass 3, count 0 2006.285.20:28:08.67#ibcon#read 4, iclass 3, count 0 2006.285.20:28:08.67#ibcon#about to read 5, iclass 3, count 0 2006.285.20:28:08.67#ibcon#read 5, iclass 3, count 0 2006.285.20:28:08.67#ibcon#about to read 6, iclass 3, count 0 2006.285.20:28:08.67#ibcon#read 6, iclass 3, count 0 2006.285.20:28:08.67#ibcon#end of sib2, iclass 3, count 0 2006.285.20:28:08.67#ibcon#*after write, iclass 3, count 0 2006.285.20:28:08.67#ibcon#*before return 0, iclass 3, count 0 2006.285.20:28:08.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:28:08.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:28:08.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:28:08.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:28:08.67$vck44/vb=4,5 2006.285.20:28:08.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.20:28:08.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.20:28:08.67#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:08.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:28:08.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:28:08.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:28:08.73#ibcon#enter wrdev, iclass 5, count 2 2006.285.20:28:08.73#ibcon#first serial, iclass 5, count 2 2006.285.20:28:08.73#ibcon#enter sib2, iclass 5, count 2 2006.285.20:28:08.73#ibcon#flushed, iclass 5, count 2 2006.285.20:28:08.73#ibcon#about to write, iclass 5, count 2 2006.285.20:28:08.73#ibcon#wrote, iclass 5, count 2 2006.285.20:28:08.73#ibcon#about to read 3, iclass 5, count 2 2006.285.20:28:08.75#ibcon#read 3, iclass 5, count 2 2006.285.20:28:08.75#ibcon#about to read 4, iclass 5, count 2 2006.285.20:28:08.75#ibcon#read 4, iclass 5, count 2 2006.285.20:28:08.75#ibcon#about to read 5, iclass 5, count 2 2006.285.20:28:08.75#ibcon#read 5, iclass 5, count 2 2006.285.20:28:08.75#ibcon#about to read 6, iclass 5, count 2 2006.285.20:28:08.75#ibcon#read 6, iclass 5, count 2 2006.285.20:28:08.75#ibcon#end of sib2, iclass 5, count 2 2006.285.20:28:08.75#ibcon#*mode == 0, iclass 5, count 2 2006.285.20:28:08.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.20:28:08.75#ibcon#[27=AT04-05\r\n] 2006.285.20:28:08.75#ibcon#*before write, iclass 5, count 2 2006.285.20:28:08.75#ibcon#enter sib2, iclass 5, count 2 2006.285.20:28:08.75#ibcon#flushed, iclass 5, count 2 2006.285.20:28:08.75#ibcon#about to write, iclass 5, count 2 2006.285.20:28:08.75#ibcon#wrote, iclass 5, count 2 2006.285.20:28:08.75#ibcon#about to read 3, iclass 5, count 2 2006.285.20:28:08.78#ibcon#read 3, iclass 5, count 2 2006.285.20:28:08.78#ibcon#about to read 4, iclass 5, count 2 2006.285.20:28:08.78#ibcon#read 4, iclass 5, count 2 2006.285.20:28:08.78#ibcon#about to read 5, iclass 5, count 2 2006.285.20:28:08.78#ibcon#read 5, iclass 5, count 2 2006.285.20:28:08.78#ibcon#about to read 6, iclass 5, count 2 2006.285.20:28:08.78#ibcon#read 6, iclass 5, count 2 2006.285.20:28:08.78#ibcon#end of sib2, iclass 5, count 2 2006.285.20:28:08.78#ibcon#*after write, iclass 5, count 2 2006.285.20:28:08.78#ibcon#*before return 0, iclass 5, count 2 2006.285.20:28:08.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:28:08.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:28:08.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.20:28:08.78#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:08.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:28:08.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:28:08.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:28:08.90#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:28:08.90#ibcon#first serial, iclass 5, count 0 2006.285.20:28:08.90#ibcon#enter sib2, iclass 5, count 0 2006.285.20:28:08.90#ibcon#flushed, iclass 5, count 0 2006.285.20:28:08.90#ibcon#about to write, iclass 5, count 0 2006.285.20:28:08.90#ibcon#wrote, iclass 5, count 0 2006.285.20:28:08.90#ibcon#about to read 3, iclass 5, count 0 2006.285.20:28:08.92#ibcon#read 3, iclass 5, count 0 2006.285.20:28:08.92#ibcon#about to read 4, iclass 5, count 0 2006.285.20:28:08.92#ibcon#read 4, iclass 5, count 0 2006.285.20:28:08.92#ibcon#about to read 5, iclass 5, count 0 2006.285.20:28:08.92#ibcon#read 5, iclass 5, count 0 2006.285.20:28:08.92#ibcon#about to read 6, iclass 5, count 0 2006.285.20:28:08.92#ibcon#read 6, iclass 5, count 0 2006.285.20:28:08.92#ibcon#end of sib2, iclass 5, count 0 2006.285.20:28:08.92#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:28:08.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:28:08.92#ibcon#[27=USB\r\n] 2006.285.20:28:08.92#ibcon#*before write, iclass 5, count 0 2006.285.20:28:08.92#ibcon#enter sib2, iclass 5, count 0 2006.285.20:28:08.92#ibcon#flushed, iclass 5, count 0 2006.285.20:28:08.92#ibcon#about to write, iclass 5, count 0 2006.285.20:28:08.92#ibcon#wrote, iclass 5, count 0 2006.285.20:28:08.92#ibcon#about to read 3, iclass 5, count 0 2006.285.20:28:08.95#ibcon#read 3, iclass 5, count 0 2006.285.20:28:08.95#ibcon#about to read 4, iclass 5, count 0 2006.285.20:28:08.95#ibcon#read 4, iclass 5, count 0 2006.285.20:28:08.95#ibcon#about to read 5, iclass 5, count 0 2006.285.20:28:08.95#ibcon#read 5, iclass 5, count 0 2006.285.20:28:08.95#ibcon#about to read 6, iclass 5, count 0 2006.285.20:28:08.95#ibcon#read 6, iclass 5, count 0 2006.285.20:28:08.95#ibcon#end of sib2, iclass 5, count 0 2006.285.20:28:08.95#ibcon#*after write, iclass 5, count 0 2006.285.20:28:08.95#ibcon#*before return 0, iclass 5, count 0 2006.285.20:28:08.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:28:08.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:28:08.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:28:08.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:28:08.95$vck44/vblo=5,709.99 2006.285.20:28:09.02#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.20:28:09.02#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.20:28:09.02#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:09.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:28:09.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:28:09.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:28:09.02#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:28:09.02#ibcon#first serial, iclass 7, count 0 2006.285.20:28:09.02#ibcon#enter sib2, iclass 7, count 0 2006.285.20:28:09.02#ibcon#flushed, iclass 7, count 0 2006.285.20:28:09.02#ibcon#about to write, iclass 7, count 0 2006.285.20:28:09.02#ibcon#wrote, iclass 7, count 0 2006.285.20:28:09.02#ibcon#about to read 3, iclass 7, count 0 2006.285.20:28:09.03#ibcon#read 3, iclass 7, count 0 2006.285.20:28:09.03#ibcon#about to read 4, iclass 7, count 0 2006.285.20:28:09.03#ibcon#read 4, iclass 7, count 0 2006.285.20:28:09.03#ibcon#about to read 5, iclass 7, count 0 2006.285.20:28:09.03#ibcon#read 5, iclass 7, count 0 2006.285.20:28:09.03#ibcon#about to read 6, iclass 7, count 0 2006.285.20:28:09.03#ibcon#read 6, iclass 7, count 0 2006.285.20:28:09.03#ibcon#end of sib2, iclass 7, count 0 2006.285.20:28:09.03#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:28:09.03#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:28:09.03#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.20:28:09.03#ibcon#*before write, iclass 7, count 0 2006.285.20:28:09.03#ibcon#enter sib2, iclass 7, count 0 2006.285.20:28:09.03#ibcon#flushed, iclass 7, count 0 2006.285.20:28:09.03#ibcon#about to write, iclass 7, count 0 2006.285.20:28:09.03#ibcon#wrote, iclass 7, count 0 2006.285.20:28:09.03#ibcon#about to read 3, iclass 7, count 0 2006.285.20:28:09.07#ibcon#read 3, iclass 7, count 0 2006.285.20:28:09.07#ibcon#about to read 4, iclass 7, count 0 2006.285.20:28:09.07#ibcon#read 4, iclass 7, count 0 2006.285.20:28:09.07#ibcon#about to read 5, iclass 7, count 0 2006.285.20:28:09.07#ibcon#read 5, iclass 7, count 0 2006.285.20:28:09.07#ibcon#about to read 6, iclass 7, count 0 2006.285.20:28:09.07#ibcon#read 6, iclass 7, count 0 2006.285.20:28:09.07#ibcon#end of sib2, iclass 7, count 0 2006.285.20:28:09.07#ibcon#*after write, iclass 7, count 0 2006.285.20:28:09.07#ibcon#*before return 0, iclass 7, count 0 2006.285.20:28:09.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:28:09.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:28:09.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:28:09.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:28:09.07$vck44/vb=5,4 2006.285.20:28:09.07#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.20:28:09.07#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.20:28:09.07#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:09.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:28:09.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:28:09.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:28:09.07#ibcon#enter wrdev, iclass 11, count 2 2006.285.20:28:09.07#ibcon#first serial, iclass 11, count 2 2006.285.20:28:09.07#ibcon#enter sib2, iclass 11, count 2 2006.285.20:28:09.07#ibcon#flushed, iclass 11, count 2 2006.285.20:28:09.07#ibcon#about to write, iclass 11, count 2 2006.285.20:28:09.07#ibcon#wrote, iclass 11, count 2 2006.285.20:28:09.07#ibcon#about to read 3, iclass 11, count 2 2006.285.20:28:09.09#ibcon#read 3, iclass 11, count 2 2006.285.20:28:09.09#ibcon#about to read 4, iclass 11, count 2 2006.285.20:28:09.09#ibcon#read 4, iclass 11, count 2 2006.285.20:28:09.09#ibcon#about to read 5, iclass 11, count 2 2006.285.20:28:09.09#ibcon#read 5, iclass 11, count 2 2006.285.20:28:09.09#ibcon#about to read 6, iclass 11, count 2 2006.285.20:28:09.09#ibcon#read 6, iclass 11, count 2 2006.285.20:28:09.09#ibcon#end of sib2, iclass 11, count 2 2006.285.20:28:09.09#ibcon#*mode == 0, iclass 11, count 2 2006.285.20:28:09.09#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.20:28:09.09#ibcon#[27=AT05-04\r\n] 2006.285.20:28:09.09#ibcon#*before write, iclass 11, count 2 2006.285.20:28:09.09#ibcon#enter sib2, iclass 11, count 2 2006.285.20:28:09.09#ibcon#flushed, iclass 11, count 2 2006.285.20:28:09.09#ibcon#about to write, iclass 11, count 2 2006.285.20:28:09.09#ibcon#wrote, iclass 11, count 2 2006.285.20:28:09.09#ibcon#about to read 3, iclass 11, count 2 2006.285.20:28:09.12#ibcon#read 3, iclass 11, count 2 2006.285.20:28:09.12#ibcon#about to read 4, iclass 11, count 2 2006.285.20:28:09.12#ibcon#read 4, iclass 11, count 2 2006.285.20:28:09.12#ibcon#about to read 5, iclass 11, count 2 2006.285.20:28:09.12#ibcon#read 5, iclass 11, count 2 2006.285.20:28:09.12#ibcon#about to read 6, iclass 11, count 2 2006.285.20:28:09.12#ibcon#read 6, iclass 11, count 2 2006.285.20:28:09.12#ibcon#end of sib2, iclass 11, count 2 2006.285.20:28:09.12#ibcon#*after write, iclass 11, count 2 2006.285.20:28:09.12#ibcon#*before return 0, iclass 11, count 2 2006.285.20:28:09.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:28:09.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:28:09.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.20:28:09.12#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:09.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:28:09.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:28:09.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:28:09.24#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:28:09.24#ibcon#first serial, iclass 11, count 0 2006.285.20:28:09.24#ibcon#enter sib2, iclass 11, count 0 2006.285.20:28:09.24#ibcon#flushed, iclass 11, count 0 2006.285.20:28:09.24#ibcon#about to write, iclass 11, count 0 2006.285.20:28:09.24#ibcon#wrote, iclass 11, count 0 2006.285.20:28:09.24#ibcon#about to read 3, iclass 11, count 0 2006.285.20:28:09.26#ibcon#read 3, iclass 11, count 0 2006.285.20:28:09.26#ibcon#about to read 4, iclass 11, count 0 2006.285.20:28:09.26#ibcon#read 4, iclass 11, count 0 2006.285.20:28:09.26#ibcon#about to read 5, iclass 11, count 0 2006.285.20:28:09.26#ibcon#read 5, iclass 11, count 0 2006.285.20:28:09.26#ibcon#about to read 6, iclass 11, count 0 2006.285.20:28:09.26#ibcon#read 6, iclass 11, count 0 2006.285.20:28:09.26#ibcon#end of sib2, iclass 11, count 0 2006.285.20:28:09.26#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:28:09.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:28:09.26#ibcon#[27=USB\r\n] 2006.285.20:28:09.26#ibcon#*before write, iclass 11, count 0 2006.285.20:28:09.26#ibcon#enter sib2, iclass 11, count 0 2006.285.20:28:09.26#ibcon#flushed, iclass 11, count 0 2006.285.20:28:09.26#ibcon#about to write, iclass 11, count 0 2006.285.20:28:09.26#ibcon#wrote, iclass 11, count 0 2006.285.20:28:09.26#ibcon#about to read 3, iclass 11, count 0 2006.285.20:28:09.29#ibcon#read 3, iclass 11, count 0 2006.285.20:28:09.29#ibcon#about to read 4, iclass 11, count 0 2006.285.20:28:09.29#ibcon#read 4, iclass 11, count 0 2006.285.20:28:09.29#ibcon#about to read 5, iclass 11, count 0 2006.285.20:28:09.29#ibcon#read 5, iclass 11, count 0 2006.285.20:28:09.29#ibcon#about to read 6, iclass 11, count 0 2006.285.20:28:09.29#ibcon#read 6, iclass 11, count 0 2006.285.20:28:09.29#ibcon#end of sib2, iclass 11, count 0 2006.285.20:28:09.29#ibcon#*after write, iclass 11, count 0 2006.285.20:28:09.29#ibcon#*before return 0, iclass 11, count 0 2006.285.20:28:09.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:28:09.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:28:09.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:28:09.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:28:09.29$vck44/vblo=6,719.99 2006.285.20:28:09.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.20:28:09.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.20:28:09.29#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:09.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:28:09.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:28:09.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:28:09.29#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:28:09.29#ibcon#first serial, iclass 13, count 0 2006.285.20:28:09.29#ibcon#enter sib2, iclass 13, count 0 2006.285.20:28:09.29#ibcon#flushed, iclass 13, count 0 2006.285.20:28:09.29#ibcon#about to write, iclass 13, count 0 2006.285.20:28:09.29#ibcon#wrote, iclass 13, count 0 2006.285.20:28:09.29#ibcon#about to read 3, iclass 13, count 0 2006.285.20:28:09.31#ibcon#read 3, iclass 13, count 0 2006.285.20:28:09.31#ibcon#about to read 4, iclass 13, count 0 2006.285.20:28:09.31#ibcon#read 4, iclass 13, count 0 2006.285.20:28:09.31#ibcon#about to read 5, iclass 13, count 0 2006.285.20:28:09.31#ibcon#read 5, iclass 13, count 0 2006.285.20:28:09.31#ibcon#about to read 6, iclass 13, count 0 2006.285.20:28:09.31#ibcon#read 6, iclass 13, count 0 2006.285.20:28:09.31#ibcon#end of sib2, iclass 13, count 0 2006.285.20:28:09.31#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:28:09.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:28:09.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.20:28:09.31#ibcon#*before write, iclass 13, count 0 2006.285.20:28:09.31#ibcon#enter sib2, iclass 13, count 0 2006.285.20:28:09.31#ibcon#flushed, iclass 13, count 0 2006.285.20:28:09.31#ibcon#about to write, iclass 13, count 0 2006.285.20:28:09.31#ibcon#wrote, iclass 13, count 0 2006.285.20:28:09.31#ibcon#about to read 3, iclass 13, count 0 2006.285.20:28:09.35#ibcon#read 3, iclass 13, count 0 2006.285.20:28:09.35#ibcon#about to read 4, iclass 13, count 0 2006.285.20:28:09.35#ibcon#read 4, iclass 13, count 0 2006.285.20:28:09.35#ibcon#about to read 5, iclass 13, count 0 2006.285.20:28:09.35#ibcon#read 5, iclass 13, count 0 2006.285.20:28:09.35#ibcon#about to read 6, iclass 13, count 0 2006.285.20:28:09.35#ibcon#read 6, iclass 13, count 0 2006.285.20:28:09.35#ibcon#end of sib2, iclass 13, count 0 2006.285.20:28:09.35#ibcon#*after write, iclass 13, count 0 2006.285.20:28:09.35#ibcon#*before return 0, iclass 13, count 0 2006.285.20:28:09.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:28:09.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:28:09.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:28:09.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:28:09.35$vck44/vb=6,3 2006.285.20:28:09.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.20:28:09.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.20:28:09.35#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:09.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:28:09.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:28:09.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:28:09.41#ibcon#enter wrdev, iclass 15, count 2 2006.285.20:28:09.41#ibcon#first serial, iclass 15, count 2 2006.285.20:28:09.41#ibcon#enter sib2, iclass 15, count 2 2006.285.20:28:09.41#ibcon#flushed, iclass 15, count 2 2006.285.20:28:09.41#ibcon#about to write, iclass 15, count 2 2006.285.20:28:09.41#ibcon#wrote, iclass 15, count 2 2006.285.20:28:09.41#ibcon#about to read 3, iclass 15, count 2 2006.285.20:28:09.43#ibcon#read 3, iclass 15, count 2 2006.285.20:28:09.43#ibcon#about to read 4, iclass 15, count 2 2006.285.20:28:09.43#ibcon#read 4, iclass 15, count 2 2006.285.20:28:09.43#ibcon#about to read 5, iclass 15, count 2 2006.285.20:28:09.43#ibcon#read 5, iclass 15, count 2 2006.285.20:28:09.43#ibcon#about to read 6, iclass 15, count 2 2006.285.20:28:09.43#ibcon#read 6, iclass 15, count 2 2006.285.20:28:09.43#ibcon#end of sib2, iclass 15, count 2 2006.285.20:28:09.43#ibcon#*mode == 0, iclass 15, count 2 2006.285.20:28:09.43#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.20:28:09.43#ibcon#[27=AT06-03\r\n] 2006.285.20:28:09.43#ibcon#*before write, iclass 15, count 2 2006.285.20:28:09.43#ibcon#enter sib2, iclass 15, count 2 2006.285.20:28:09.43#ibcon#flushed, iclass 15, count 2 2006.285.20:28:09.43#ibcon#about to write, iclass 15, count 2 2006.285.20:28:09.43#ibcon#wrote, iclass 15, count 2 2006.285.20:28:09.43#ibcon#about to read 3, iclass 15, count 2 2006.285.20:28:09.46#ibcon#read 3, iclass 15, count 2 2006.285.20:28:09.46#ibcon#about to read 4, iclass 15, count 2 2006.285.20:28:09.46#ibcon#read 4, iclass 15, count 2 2006.285.20:28:09.46#ibcon#about to read 5, iclass 15, count 2 2006.285.20:28:09.46#ibcon#read 5, iclass 15, count 2 2006.285.20:28:09.46#ibcon#about to read 6, iclass 15, count 2 2006.285.20:28:09.46#ibcon#read 6, iclass 15, count 2 2006.285.20:28:09.46#ibcon#end of sib2, iclass 15, count 2 2006.285.20:28:09.46#ibcon#*after write, iclass 15, count 2 2006.285.20:28:09.46#ibcon#*before return 0, iclass 15, count 2 2006.285.20:28:09.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:28:09.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:28:09.46#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.20:28:09.46#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:09.46#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:28:09.58#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:28:09.58#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:28:09.58#ibcon#enter wrdev, iclass 15, count 0 2006.285.20:28:09.58#ibcon#first serial, iclass 15, count 0 2006.285.20:28:09.58#ibcon#enter sib2, iclass 15, count 0 2006.285.20:28:09.58#ibcon#flushed, iclass 15, count 0 2006.285.20:28:09.58#ibcon#about to write, iclass 15, count 0 2006.285.20:28:09.58#ibcon#wrote, iclass 15, count 0 2006.285.20:28:09.58#ibcon#about to read 3, iclass 15, count 0 2006.285.20:28:09.60#ibcon#read 3, iclass 15, count 0 2006.285.20:28:09.60#ibcon#about to read 4, iclass 15, count 0 2006.285.20:28:09.60#ibcon#read 4, iclass 15, count 0 2006.285.20:28:09.60#ibcon#about to read 5, iclass 15, count 0 2006.285.20:28:09.60#ibcon#read 5, iclass 15, count 0 2006.285.20:28:09.60#ibcon#about to read 6, iclass 15, count 0 2006.285.20:28:09.60#ibcon#read 6, iclass 15, count 0 2006.285.20:28:09.60#ibcon#end of sib2, iclass 15, count 0 2006.285.20:28:09.60#ibcon#*mode == 0, iclass 15, count 0 2006.285.20:28:09.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.20:28:09.60#ibcon#[27=USB\r\n] 2006.285.20:28:09.60#ibcon#*before write, iclass 15, count 0 2006.285.20:28:09.60#ibcon#enter sib2, iclass 15, count 0 2006.285.20:28:09.60#ibcon#flushed, iclass 15, count 0 2006.285.20:28:09.60#ibcon#about to write, iclass 15, count 0 2006.285.20:28:09.60#ibcon#wrote, iclass 15, count 0 2006.285.20:28:09.60#ibcon#about to read 3, iclass 15, count 0 2006.285.20:28:09.63#ibcon#read 3, iclass 15, count 0 2006.285.20:28:09.63#ibcon#about to read 4, iclass 15, count 0 2006.285.20:28:09.63#ibcon#read 4, iclass 15, count 0 2006.285.20:28:09.63#ibcon#about to read 5, iclass 15, count 0 2006.285.20:28:09.63#ibcon#read 5, iclass 15, count 0 2006.285.20:28:09.63#ibcon#about to read 6, iclass 15, count 0 2006.285.20:28:09.63#ibcon#read 6, iclass 15, count 0 2006.285.20:28:09.63#ibcon#end of sib2, iclass 15, count 0 2006.285.20:28:09.63#ibcon#*after write, iclass 15, count 0 2006.285.20:28:09.63#ibcon#*before return 0, iclass 15, count 0 2006.285.20:28:09.63#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:28:09.63#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:28:09.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.20:28:09.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.20:28:09.63$vck44/vblo=7,734.99 2006.285.20:28:09.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.20:28:09.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.20:28:09.63#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:09.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:28:09.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:28:09.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:28:09.63#ibcon#enter wrdev, iclass 17, count 0 2006.285.20:28:09.63#ibcon#first serial, iclass 17, count 0 2006.285.20:28:09.63#ibcon#enter sib2, iclass 17, count 0 2006.285.20:28:09.63#ibcon#flushed, iclass 17, count 0 2006.285.20:28:09.63#ibcon#about to write, iclass 17, count 0 2006.285.20:28:09.63#ibcon#wrote, iclass 17, count 0 2006.285.20:28:09.63#ibcon#about to read 3, iclass 17, count 0 2006.285.20:28:09.65#ibcon#read 3, iclass 17, count 0 2006.285.20:28:09.65#ibcon#about to read 4, iclass 17, count 0 2006.285.20:28:09.65#ibcon#read 4, iclass 17, count 0 2006.285.20:28:09.65#ibcon#about to read 5, iclass 17, count 0 2006.285.20:28:09.65#ibcon#read 5, iclass 17, count 0 2006.285.20:28:09.65#ibcon#about to read 6, iclass 17, count 0 2006.285.20:28:09.65#ibcon#read 6, iclass 17, count 0 2006.285.20:28:09.65#ibcon#end of sib2, iclass 17, count 0 2006.285.20:28:09.65#ibcon#*mode == 0, iclass 17, count 0 2006.285.20:28:09.65#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.20:28:09.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.20:28:09.65#ibcon#*before write, iclass 17, count 0 2006.285.20:28:09.65#ibcon#enter sib2, iclass 17, count 0 2006.285.20:28:09.65#ibcon#flushed, iclass 17, count 0 2006.285.20:28:09.65#ibcon#about to write, iclass 17, count 0 2006.285.20:28:09.65#ibcon#wrote, iclass 17, count 0 2006.285.20:28:09.65#ibcon#about to read 3, iclass 17, count 0 2006.285.20:28:09.69#ibcon#read 3, iclass 17, count 0 2006.285.20:28:09.69#ibcon#about to read 4, iclass 17, count 0 2006.285.20:28:09.69#ibcon#read 4, iclass 17, count 0 2006.285.20:28:09.69#ibcon#about to read 5, iclass 17, count 0 2006.285.20:28:09.69#ibcon#read 5, iclass 17, count 0 2006.285.20:28:09.69#ibcon#about to read 6, iclass 17, count 0 2006.285.20:28:09.69#ibcon#read 6, iclass 17, count 0 2006.285.20:28:09.69#ibcon#end of sib2, iclass 17, count 0 2006.285.20:28:09.69#ibcon#*after write, iclass 17, count 0 2006.285.20:28:09.69#ibcon#*before return 0, iclass 17, count 0 2006.285.20:28:09.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:28:09.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:28:09.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.20:28:09.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.20:28:09.69$vck44/vb=7,4 2006.285.20:28:09.69#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.20:28:09.69#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.20:28:09.69#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:09.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:28:09.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:28:09.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:28:09.75#ibcon#enter wrdev, iclass 19, count 2 2006.285.20:28:09.75#ibcon#first serial, iclass 19, count 2 2006.285.20:28:09.75#ibcon#enter sib2, iclass 19, count 2 2006.285.20:28:09.75#ibcon#flushed, iclass 19, count 2 2006.285.20:28:09.75#ibcon#about to write, iclass 19, count 2 2006.285.20:28:09.75#ibcon#wrote, iclass 19, count 2 2006.285.20:28:09.75#ibcon#about to read 3, iclass 19, count 2 2006.285.20:28:09.77#ibcon#read 3, iclass 19, count 2 2006.285.20:28:09.77#ibcon#about to read 4, iclass 19, count 2 2006.285.20:28:09.77#ibcon#read 4, iclass 19, count 2 2006.285.20:28:09.77#ibcon#about to read 5, iclass 19, count 2 2006.285.20:28:09.77#ibcon#read 5, iclass 19, count 2 2006.285.20:28:09.77#ibcon#about to read 6, iclass 19, count 2 2006.285.20:28:09.77#ibcon#read 6, iclass 19, count 2 2006.285.20:28:09.77#ibcon#end of sib2, iclass 19, count 2 2006.285.20:28:09.77#ibcon#*mode == 0, iclass 19, count 2 2006.285.20:28:09.77#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.20:28:09.77#ibcon#[27=AT07-04\r\n] 2006.285.20:28:09.77#ibcon#*before write, iclass 19, count 2 2006.285.20:28:09.77#ibcon#enter sib2, iclass 19, count 2 2006.285.20:28:09.77#ibcon#flushed, iclass 19, count 2 2006.285.20:28:09.77#ibcon#about to write, iclass 19, count 2 2006.285.20:28:09.77#ibcon#wrote, iclass 19, count 2 2006.285.20:28:09.77#ibcon#about to read 3, iclass 19, count 2 2006.285.20:28:09.80#ibcon#read 3, iclass 19, count 2 2006.285.20:28:09.80#ibcon#about to read 4, iclass 19, count 2 2006.285.20:28:09.80#ibcon#read 4, iclass 19, count 2 2006.285.20:28:09.80#ibcon#about to read 5, iclass 19, count 2 2006.285.20:28:09.80#ibcon#read 5, iclass 19, count 2 2006.285.20:28:09.80#ibcon#about to read 6, iclass 19, count 2 2006.285.20:28:09.80#ibcon#read 6, iclass 19, count 2 2006.285.20:28:09.80#ibcon#end of sib2, iclass 19, count 2 2006.285.20:28:09.80#ibcon#*after write, iclass 19, count 2 2006.285.20:28:09.80#ibcon#*before return 0, iclass 19, count 2 2006.285.20:28:09.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:28:09.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:28:09.80#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.20:28:09.80#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:09.80#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:28:09.92#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:28:09.92#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:28:09.92#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:28:09.92#ibcon#first serial, iclass 19, count 0 2006.285.20:28:09.92#ibcon#enter sib2, iclass 19, count 0 2006.285.20:28:09.92#ibcon#flushed, iclass 19, count 0 2006.285.20:28:09.92#ibcon#about to write, iclass 19, count 0 2006.285.20:28:09.92#ibcon#wrote, iclass 19, count 0 2006.285.20:28:09.92#ibcon#about to read 3, iclass 19, count 0 2006.285.20:28:09.94#ibcon#read 3, iclass 19, count 0 2006.285.20:28:09.94#ibcon#about to read 4, iclass 19, count 0 2006.285.20:28:09.94#ibcon#read 4, iclass 19, count 0 2006.285.20:28:09.94#ibcon#about to read 5, iclass 19, count 0 2006.285.20:28:09.94#ibcon#read 5, iclass 19, count 0 2006.285.20:28:09.94#ibcon#about to read 6, iclass 19, count 0 2006.285.20:28:09.94#ibcon#read 6, iclass 19, count 0 2006.285.20:28:09.94#ibcon#end of sib2, iclass 19, count 0 2006.285.20:28:09.94#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:28:09.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:28:09.94#ibcon#[27=USB\r\n] 2006.285.20:28:09.94#ibcon#*before write, iclass 19, count 0 2006.285.20:28:09.94#ibcon#enter sib2, iclass 19, count 0 2006.285.20:28:09.94#ibcon#flushed, iclass 19, count 0 2006.285.20:28:09.94#ibcon#about to write, iclass 19, count 0 2006.285.20:28:09.94#ibcon#wrote, iclass 19, count 0 2006.285.20:28:09.94#ibcon#about to read 3, iclass 19, count 0 2006.285.20:28:09.97#ibcon#read 3, iclass 19, count 0 2006.285.20:28:09.97#ibcon#about to read 4, iclass 19, count 0 2006.285.20:28:09.97#ibcon#read 4, iclass 19, count 0 2006.285.20:28:09.97#ibcon#about to read 5, iclass 19, count 0 2006.285.20:28:09.97#ibcon#read 5, iclass 19, count 0 2006.285.20:28:09.97#ibcon#about to read 6, iclass 19, count 0 2006.285.20:28:09.97#ibcon#read 6, iclass 19, count 0 2006.285.20:28:09.97#ibcon#end of sib2, iclass 19, count 0 2006.285.20:28:09.97#ibcon#*after write, iclass 19, count 0 2006.285.20:28:09.97#ibcon#*before return 0, iclass 19, count 0 2006.285.20:28:09.97#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:28:09.97#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:28:09.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:28:09.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:28:09.97$vck44/vblo=8,744.99 2006.285.20:28:09.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.20:28:09.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.20:28:09.99#ibcon#ireg 17 cls_cnt 0 2006.285.20:28:09.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:28:09.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:28:09.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:28:09.99#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:28:09.99#ibcon#first serial, iclass 21, count 0 2006.285.20:28:09.99#ibcon#enter sib2, iclass 21, count 0 2006.285.20:28:09.99#ibcon#flushed, iclass 21, count 0 2006.285.20:28:09.99#ibcon#about to write, iclass 21, count 0 2006.285.20:28:09.99#ibcon#wrote, iclass 21, count 0 2006.285.20:28:09.99#ibcon#about to read 3, iclass 21, count 0 2006.285.20:28:10.01#ibcon#read 3, iclass 21, count 0 2006.285.20:28:10.01#ibcon#about to read 4, iclass 21, count 0 2006.285.20:28:10.01#ibcon#read 4, iclass 21, count 0 2006.285.20:28:10.01#ibcon#about to read 5, iclass 21, count 0 2006.285.20:28:10.01#ibcon#read 5, iclass 21, count 0 2006.285.20:28:10.01#ibcon#about to read 6, iclass 21, count 0 2006.285.20:28:10.01#ibcon#read 6, iclass 21, count 0 2006.285.20:28:10.01#ibcon#end of sib2, iclass 21, count 0 2006.285.20:28:10.01#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:28:10.01#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:28:10.01#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.20:28:10.01#ibcon#*before write, iclass 21, count 0 2006.285.20:28:10.01#ibcon#enter sib2, iclass 21, count 0 2006.285.20:28:10.01#ibcon#flushed, iclass 21, count 0 2006.285.20:28:10.01#ibcon#about to write, iclass 21, count 0 2006.285.20:28:10.01#ibcon#wrote, iclass 21, count 0 2006.285.20:28:10.01#ibcon#about to read 3, iclass 21, count 0 2006.285.20:28:10.05#ibcon#read 3, iclass 21, count 0 2006.285.20:28:10.05#ibcon#about to read 4, iclass 21, count 0 2006.285.20:28:10.05#ibcon#read 4, iclass 21, count 0 2006.285.20:28:10.05#ibcon#about to read 5, iclass 21, count 0 2006.285.20:28:10.05#ibcon#read 5, iclass 21, count 0 2006.285.20:28:10.05#ibcon#about to read 6, iclass 21, count 0 2006.285.20:28:10.05#ibcon#read 6, iclass 21, count 0 2006.285.20:28:10.05#ibcon#end of sib2, iclass 21, count 0 2006.285.20:28:10.05#ibcon#*after write, iclass 21, count 0 2006.285.20:28:10.05#ibcon#*before return 0, iclass 21, count 0 2006.285.20:28:10.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:28:10.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:28:10.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:28:10.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:28:10.05$vck44/vb=8,4 2006.285.20:28:10.05#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.20:28:10.05#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.20:28:10.05#ibcon#ireg 11 cls_cnt 2 2006.285.20:28:10.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:28:10.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:28:10.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:28:10.09#ibcon#enter wrdev, iclass 23, count 2 2006.285.20:28:10.09#ibcon#first serial, iclass 23, count 2 2006.285.20:28:10.09#ibcon#enter sib2, iclass 23, count 2 2006.285.20:28:10.09#ibcon#flushed, iclass 23, count 2 2006.285.20:28:10.09#ibcon#about to write, iclass 23, count 2 2006.285.20:28:10.09#ibcon#wrote, iclass 23, count 2 2006.285.20:28:10.09#ibcon#about to read 3, iclass 23, count 2 2006.285.20:28:10.11#ibcon#read 3, iclass 23, count 2 2006.285.20:28:10.11#ibcon#about to read 4, iclass 23, count 2 2006.285.20:28:10.11#ibcon#read 4, iclass 23, count 2 2006.285.20:28:10.11#ibcon#about to read 5, iclass 23, count 2 2006.285.20:28:10.11#ibcon#read 5, iclass 23, count 2 2006.285.20:28:10.11#ibcon#about to read 6, iclass 23, count 2 2006.285.20:28:10.11#ibcon#read 6, iclass 23, count 2 2006.285.20:28:10.11#ibcon#end of sib2, iclass 23, count 2 2006.285.20:28:10.11#ibcon#*mode == 0, iclass 23, count 2 2006.285.20:28:10.11#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.20:28:10.11#ibcon#[27=AT08-04\r\n] 2006.285.20:28:10.11#ibcon#*before write, iclass 23, count 2 2006.285.20:28:10.11#ibcon#enter sib2, iclass 23, count 2 2006.285.20:28:10.11#ibcon#flushed, iclass 23, count 2 2006.285.20:28:10.11#ibcon#about to write, iclass 23, count 2 2006.285.20:28:10.11#ibcon#wrote, iclass 23, count 2 2006.285.20:28:10.11#ibcon#about to read 3, iclass 23, count 2 2006.285.20:28:10.14#ibcon#read 3, iclass 23, count 2 2006.285.20:28:10.14#ibcon#about to read 4, iclass 23, count 2 2006.285.20:28:10.14#ibcon#read 4, iclass 23, count 2 2006.285.20:28:10.14#ibcon#about to read 5, iclass 23, count 2 2006.285.20:28:10.14#ibcon#read 5, iclass 23, count 2 2006.285.20:28:10.14#ibcon#about to read 6, iclass 23, count 2 2006.285.20:28:10.14#ibcon#read 6, iclass 23, count 2 2006.285.20:28:10.14#ibcon#end of sib2, iclass 23, count 2 2006.285.20:28:10.14#ibcon#*after write, iclass 23, count 2 2006.285.20:28:10.14#ibcon#*before return 0, iclass 23, count 2 2006.285.20:28:10.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:28:10.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:28:10.14#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.20:28:10.14#ibcon#ireg 7 cls_cnt 0 2006.285.20:28:10.14#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:28:10.26#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:28:10.26#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:28:10.26#ibcon#enter wrdev, iclass 23, count 0 2006.285.20:28:10.26#ibcon#first serial, iclass 23, count 0 2006.285.20:28:10.26#ibcon#enter sib2, iclass 23, count 0 2006.285.20:28:10.26#ibcon#flushed, iclass 23, count 0 2006.285.20:28:10.26#ibcon#about to write, iclass 23, count 0 2006.285.20:28:10.26#ibcon#wrote, iclass 23, count 0 2006.285.20:28:10.26#ibcon#about to read 3, iclass 23, count 0 2006.285.20:28:10.28#ibcon#read 3, iclass 23, count 0 2006.285.20:28:10.28#ibcon#about to read 4, iclass 23, count 0 2006.285.20:28:10.28#ibcon#read 4, iclass 23, count 0 2006.285.20:28:10.28#ibcon#about to read 5, iclass 23, count 0 2006.285.20:28:10.28#ibcon#read 5, iclass 23, count 0 2006.285.20:28:10.28#ibcon#about to read 6, iclass 23, count 0 2006.285.20:28:10.28#ibcon#read 6, iclass 23, count 0 2006.285.20:28:10.28#ibcon#end of sib2, iclass 23, count 0 2006.285.20:28:10.28#ibcon#*mode == 0, iclass 23, count 0 2006.285.20:28:10.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.20:28:10.28#ibcon#[27=USB\r\n] 2006.285.20:28:10.28#ibcon#*before write, iclass 23, count 0 2006.285.20:28:10.28#ibcon#enter sib2, iclass 23, count 0 2006.285.20:28:10.28#ibcon#flushed, iclass 23, count 0 2006.285.20:28:10.28#ibcon#about to write, iclass 23, count 0 2006.285.20:28:10.28#ibcon#wrote, iclass 23, count 0 2006.285.20:28:10.28#ibcon#about to read 3, iclass 23, count 0 2006.285.20:28:10.31#ibcon#read 3, iclass 23, count 0 2006.285.20:28:10.31#ibcon#about to read 4, iclass 23, count 0 2006.285.20:28:10.31#ibcon#read 4, iclass 23, count 0 2006.285.20:28:10.31#ibcon#about to read 5, iclass 23, count 0 2006.285.20:28:10.31#ibcon#read 5, iclass 23, count 0 2006.285.20:28:10.31#ibcon#about to read 6, iclass 23, count 0 2006.285.20:28:10.31#ibcon#read 6, iclass 23, count 0 2006.285.20:28:10.31#ibcon#end of sib2, iclass 23, count 0 2006.285.20:28:10.31#ibcon#*after write, iclass 23, count 0 2006.285.20:28:10.31#ibcon#*before return 0, iclass 23, count 0 2006.285.20:28:10.31#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:28:10.31#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:28:10.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.20:28:10.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.20:28:10.31$vck44/vabw=wide 2006.285.20:28:10.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.20:28:10.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.20:28:10.31#ibcon#ireg 8 cls_cnt 0 2006.285.20:28:10.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:28:10.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:28:10.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:28:10.31#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:28:10.31#ibcon#first serial, iclass 25, count 0 2006.285.20:28:10.31#ibcon#enter sib2, iclass 25, count 0 2006.285.20:28:10.31#ibcon#flushed, iclass 25, count 0 2006.285.20:28:10.31#ibcon#about to write, iclass 25, count 0 2006.285.20:28:10.31#ibcon#wrote, iclass 25, count 0 2006.285.20:28:10.31#ibcon#about to read 3, iclass 25, count 0 2006.285.20:28:10.33#ibcon#read 3, iclass 25, count 0 2006.285.20:28:10.33#ibcon#about to read 4, iclass 25, count 0 2006.285.20:28:10.33#ibcon#read 4, iclass 25, count 0 2006.285.20:28:10.33#ibcon#about to read 5, iclass 25, count 0 2006.285.20:28:10.33#ibcon#read 5, iclass 25, count 0 2006.285.20:28:10.33#ibcon#about to read 6, iclass 25, count 0 2006.285.20:28:10.33#ibcon#read 6, iclass 25, count 0 2006.285.20:28:10.33#ibcon#end of sib2, iclass 25, count 0 2006.285.20:28:10.33#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:28:10.33#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:28:10.33#ibcon#[25=BW32\r\n] 2006.285.20:28:10.33#ibcon#*before write, iclass 25, count 0 2006.285.20:28:10.33#ibcon#enter sib2, iclass 25, count 0 2006.285.20:28:10.33#ibcon#flushed, iclass 25, count 0 2006.285.20:28:10.33#ibcon#about to write, iclass 25, count 0 2006.285.20:28:10.33#ibcon#wrote, iclass 25, count 0 2006.285.20:28:10.33#ibcon#about to read 3, iclass 25, count 0 2006.285.20:28:10.36#ibcon#read 3, iclass 25, count 0 2006.285.20:28:10.36#ibcon#about to read 4, iclass 25, count 0 2006.285.20:28:10.36#ibcon#read 4, iclass 25, count 0 2006.285.20:28:10.36#ibcon#about to read 5, iclass 25, count 0 2006.285.20:28:10.36#ibcon#read 5, iclass 25, count 0 2006.285.20:28:10.36#ibcon#about to read 6, iclass 25, count 0 2006.285.20:28:10.36#ibcon#read 6, iclass 25, count 0 2006.285.20:28:10.36#ibcon#end of sib2, iclass 25, count 0 2006.285.20:28:10.36#ibcon#*after write, iclass 25, count 0 2006.285.20:28:10.36#ibcon#*before return 0, iclass 25, count 0 2006.285.20:28:10.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:28:10.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:28:10.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:28:10.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:28:10.36$vck44/vbbw=wide 2006.285.20:28:10.36#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.20:28:10.36#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.20:28:10.36#ibcon#ireg 8 cls_cnt 0 2006.285.20:28:10.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:28:10.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:28:10.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:28:10.43#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:28:10.43#ibcon#first serial, iclass 27, count 0 2006.285.20:28:10.43#ibcon#enter sib2, iclass 27, count 0 2006.285.20:28:10.43#ibcon#flushed, iclass 27, count 0 2006.285.20:28:10.43#ibcon#about to write, iclass 27, count 0 2006.285.20:28:10.43#ibcon#wrote, iclass 27, count 0 2006.285.20:28:10.43#ibcon#about to read 3, iclass 27, count 0 2006.285.20:28:10.45#ibcon#read 3, iclass 27, count 0 2006.285.20:28:10.45#ibcon#about to read 4, iclass 27, count 0 2006.285.20:28:10.45#ibcon#read 4, iclass 27, count 0 2006.285.20:28:10.45#ibcon#about to read 5, iclass 27, count 0 2006.285.20:28:10.45#ibcon#read 5, iclass 27, count 0 2006.285.20:28:10.45#ibcon#about to read 6, iclass 27, count 0 2006.285.20:28:10.45#ibcon#read 6, iclass 27, count 0 2006.285.20:28:10.45#ibcon#end of sib2, iclass 27, count 0 2006.285.20:28:10.45#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:28:10.45#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:28:10.45#ibcon#[27=BW32\r\n] 2006.285.20:28:10.45#ibcon#*before write, iclass 27, count 0 2006.285.20:28:10.45#ibcon#enter sib2, iclass 27, count 0 2006.285.20:28:10.45#ibcon#flushed, iclass 27, count 0 2006.285.20:28:10.45#ibcon#about to write, iclass 27, count 0 2006.285.20:28:10.45#ibcon#wrote, iclass 27, count 0 2006.285.20:28:10.45#ibcon#about to read 3, iclass 27, count 0 2006.285.20:28:10.48#ibcon#read 3, iclass 27, count 0 2006.285.20:28:10.48#ibcon#about to read 4, iclass 27, count 0 2006.285.20:28:10.48#ibcon#read 4, iclass 27, count 0 2006.285.20:28:10.48#ibcon#about to read 5, iclass 27, count 0 2006.285.20:28:10.48#ibcon#read 5, iclass 27, count 0 2006.285.20:28:10.48#ibcon#about to read 6, iclass 27, count 0 2006.285.20:28:10.48#ibcon#read 6, iclass 27, count 0 2006.285.20:28:10.48#ibcon#end of sib2, iclass 27, count 0 2006.285.20:28:10.48#ibcon#*after write, iclass 27, count 0 2006.285.20:28:10.48#ibcon#*before return 0, iclass 27, count 0 2006.285.20:28:10.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:28:10.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:28:10.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:28:10.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:28:10.48$setupk4/ifdk4 2006.285.20:28:10.48$ifdk4/lo= 2006.285.20:28:10.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.20:28:10.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.20:28:10.48$ifdk4/patch= 2006.285.20:28:10.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.20:28:10.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.20:28:10.48$setupk4/!*+20s 2006.285.20:28:17.51#abcon#<5=/06 0.3 1.2 14.411001015.4\r\n> 2006.285.20:28:17.53#abcon#{5=INTERFACE CLEAR} 2006.285.20:28:17.59#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:28:23.98$setupk4/"tpicd 2006.285.20:28:23.98$setupk4/echo=off 2006.285.20:28:23.98$setupk4/xlog=off 2006.285.20:28:23.98:!2006.285.20:33:37 2006.285.20:29:34.14#trakl#Source acquired 2006.285.20:29:34.14#flagr#flagr/antenna,acquired 2006.285.20:33:37.00:preob 2006.285.20:33:38.14/onsource/TRACKING 2006.285.20:33:38.14:!2006.285.20:33:47 2006.285.20:33:47.00:"tape 2006.285.20:33:47.00:"st=record 2006.285.20:33:47.00:data_valid=on 2006.285.20:33:47.00:midob 2006.285.20:33:47.13/onsource/TRACKING 2006.285.20:33:47.13/wx/14.31,1015.4,100 2006.285.20:33:47.23/cable/+6.5089E-03 2006.285.20:33:48.32/va/01,07,usb,yes,32,35 2006.285.20:33:48.32/va/02,06,usb,yes,32,33 2006.285.20:33:48.32/va/03,07,usb,yes,32,34 2006.285.20:33:48.32/va/04,06,usb,yes,33,35 2006.285.20:33:48.32/va/05,03,usb,yes,33,33 2006.285.20:33:48.32/va/06,04,usb,yes,30,29 2006.285.20:33:48.32/va/07,04,usb,yes,30,31 2006.285.20:33:48.32/va/08,03,usb,yes,31,37 2006.285.20:33:48.55/valo/01,524.99,yes,locked 2006.285.20:33:48.55/valo/02,534.99,yes,locked 2006.285.20:33:48.55/valo/03,564.99,yes,locked 2006.285.20:33:48.55/valo/04,624.99,yes,locked 2006.285.20:33:48.55/valo/05,734.99,yes,locked 2006.285.20:33:48.55/valo/06,814.99,yes,locked 2006.285.20:33:48.55/valo/07,864.99,yes,locked 2006.285.20:33:48.55/valo/08,884.99,yes,locked 2006.285.20:33:49.64/vb/01,04,usb,yes,30,28 2006.285.20:33:49.64/vb/02,05,usb,yes,28,28 2006.285.20:33:49.64/vb/03,04,usb,yes,29,32 2006.285.20:33:49.64/vb/04,05,usb,yes,30,29 2006.285.20:33:49.64/vb/05,04,usb,yes,26,28 2006.285.20:33:49.64/vb/06,03,usb,yes,38,33 2006.285.20:33:49.64/vb/07,04,usb,yes,30,30 2006.285.20:33:49.64/vb/08,04,usb,yes,27,31 2006.285.20:33:49.88/vblo/01,629.99,yes,locked 2006.285.20:33:49.88/vblo/02,634.99,yes,locked 2006.285.20:33:49.88/vblo/03,649.99,yes,locked 2006.285.20:33:49.88/vblo/04,679.99,yes,locked 2006.285.20:33:49.88/vblo/05,709.99,yes,locked 2006.285.20:33:49.88/vblo/06,719.99,yes,locked 2006.285.20:33:49.88/vblo/07,734.99,yes,locked 2006.285.20:33:49.88/vblo/08,744.99,yes,locked 2006.285.20:33:50.03/vabw/8 2006.285.20:33:50.18/vbbw/8 2006.285.20:33:50.27/xfe/off,on,12.0 2006.285.20:33:50.64/ifatt/23,28,28,28 2006.285.20:33:51.07/fmout-gps/S +2.72E-07 2006.285.20:33:51.09:!2006.285.20:37:07 2006.285.20:37:07.01:data_valid=off 2006.285.20:37:07.01:"et 2006.285.20:37:07.01:!+3s 2006.285.20:37:10.02:"tape 2006.285.20:37:10.02:postob 2006.285.20:37:10.19/cable/+6.5117E-03 2006.285.20:37:10.19/wx/14.27,1015.4,100 2006.285.20:37:11.08/fmout-gps/S +2.77E-07 2006.285.20:37:11.08:scan_name=285-2041,jd0610,100 2006.285.20:37:11.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.285.20:37:11.14#flagr#flagr/antenna,new-source 2006.285.20:37:12.14:checkk5 2006.285.20:37:12.59/chk_autoobs//k5ts1/ autoobs is running! 2006.285.20:37:12.98/chk_autoobs//k5ts2/ autoobs is running! 2006.285.20:37:13.61/chk_autoobs//k5ts3/ autoobs is running! 2006.285.20:37:13.99/chk_autoobs//k5ts4/ autoobs is running! 2006.285.20:37:14.54/chk_obsdata//k5ts1/T2852033??a.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.20:37:14.92/chk_obsdata//k5ts2/T2852033??b.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.20:37:15.44/chk_obsdata//k5ts3/T2852033??c.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.20:37:16.04/chk_obsdata//k5ts4/T2852033??d.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.20:37:16.91/k5log//k5ts1_log_newline 2006.285.20:37:17.88/k5log//k5ts2_log_newline 2006.285.20:37:18.71/k5log//k5ts3_log_newline 2006.285.20:37:19.48/k5log//k5ts4_log_newline 2006.285.20:37:19.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.20:37:19.50:setupk4=1 2006.285.20:37:19.50$setupk4/echo=on 2006.285.20:37:19.50$setupk4/pcalon 2006.285.20:37:19.50$pcalon/"no phase cal control is implemented here 2006.285.20:37:19.50$setupk4/"tpicd=stop 2006.285.20:37:19.50$setupk4/"rec=synch_on 2006.285.20:37:19.50$setupk4/"rec_mode=128 2006.285.20:37:19.50$setupk4/!* 2006.285.20:37:19.50$setupk4/recpk4 2006.285.20:37:19.50$recpk4/recpatch= 2006.285.20:37:19.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.20:37:19.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.20:37:19.50$setupk4/vck44 2006.285.20:37:19.50$vck44/valo=1,524.99 2006.285.20:37:19.51#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.20:37:19.51#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.20:37:19.51#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:19.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:37:19.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:37:19.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:37:19.51#ibcon#enter wrdev, iclass 32, count 0 2006.285.20:37:19.51#ibcon#first serial, iclass 32, count 0 2006.285.20:37:19.51#ibcon#enter sib2, iclass 32, count 0 2006.285.20:37:19.51#ibcon#flushed, iclass 32, count 0 2006.285.20:37:19.51#ibcon#about to write, iclass 32, count 0 2006.285.20:37:19.51#ibcon#wrote, iclass 32, count 0 2006.285.20:37:19.51#ibcon#about to read 3, iclass 32, count 0 2006.285.20:37:19.53#ibcon#read 3, iclass 32, count 0 2006.285.20:37:19.53#ibcon#about to read 4, iclass 32, count 0 2006.285.20:37:19.53#ibcon#read 4, iclass 32, count 0 2006.285.20:37:19.53#ibcon#about to read 5, iclass 32, count 0 2006.285.20:37:19.53#ibcon#read 5, iclass 32, count 0 2006.285.20:37:19.53#ibcon#about to read 6, iclass 32, count 0 2006.285.20:37:19.53#ibcon#read 6, iclass 32, count 0 2006.285.20:37:19.53#ibcon#end of sib2, iclass 32, count 0 2006.285.20:37:19.53#ibcon#*mode == 0, iclass 32, count 0 2006.285.20:37:19.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.20:37:19.53#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.20:37:19.53#ibcon#*before write, iclass 32, count 0 2006.285.20:37:19.53#ibcon#enter sib2, iclass 32, count 0 2006.285.20:37:19.53#ibcon#flushed, iclass 32, count 0 2006.285.20:37:19.53#ibcon#about to write, iclass 32, count 0 2006.285.20:37:19.53#ibcon#wrote, iclass 32, count 0 2006.285.20:37:19.53#ibcon#about to read 3, iclass 32, count 0 2006.285.20:37:19.58#ibcon#read 3, iclass 32, count 0 2006.285.20:37:19.58#ibcon#about to read 4, iclass 32, count 0 2006.285.20:37:19.58#ibcon#read 4, iclass 32, count 0 2006.285.20:37:19.58#ibcon#about to read 5, iclass 32, count 0 2006.285.20:37:19.58#ibcon#read 5, iclass 32, count 0 2006.285.20:37:19.58#ibcon#about to read 6, iclass 32, count 0 2006.285.20:37:19.58#ibcon#read 6, iclass 32, count 0 2006.285.20:37:19.58#ibcon#end of sib2, iclass 32, count 0 2006.285.20:37:19.58#ibcon#*after write, iclass 32, count 0 2006.285.20:37:19.58#ibcon#*before return 0, iclass 32, count 0 2006.285.20:37:19.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:37:19.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:37:19.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.20:37:19.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.20:37:19.58$vck44/va=1,7 2006.285.20:37:19.58#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.20:37:19.58#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.20:37:19.58#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:19.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:37:19.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:37:19.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:37:19.58#ibcon#enter wrdev, iclass 34, count 2 2006.285.20:37:19.58#ibcon#first serial, iclass 34, count 2 2006.285.20:37:19.58#ibcon#enter sib2, iclass 34, count 2 2006.285.20:37:19.58#ibcon#flushed, iclass 34, count 2 2006.285.20:37:19.58#ibcon#about to write, iclass 34, count 2 2006.285.20:37:19.58#ibcon#wrote, iclass 34, count 2 2006.285.20:37:19.58#ibcon#about to read 3, iclass 34, count 2 2006.285.20:37:19.60#ibcon#read 3, iclass 34, count 2 2006.285.20:37:19.60#ibcon#about to read 4, iclass 34, count 2 2006.285.20:37:19.60#ibcon#read 4, iclass 34, count 2 2006.285.20:37:19.60#ibcon#about to read 5, iclass 34, count 2 2006.285.20:37:19.60#ibcon#read 5, iclass 34, count 2 2006.285.20:37:19.60#ibcon#about to read 6, iclass 34, count 2 2006.285.20:37:19.60#ibcon#read 6, iclass 34, count 2 2006.285.20:37:19.60#ibcon#end of sib2, iclass 34, count 2 2006.285.20:37:19.60#ibcon#*mode == 0, iclass 34, count 2 2006.285.20:37:19.60#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.20:37:19.60#ibcon#[25=AT01-07\r\n] 2006.285.20:37:19.60#ibcon#*before write, iclass 34, count 2 2006.285.20:37:19.60#ibcon#enter sib2, iclass 34, count 2 2006.285.20:37:19.60#ibcon#flushed, iclass 34, count 2 2006.285.20:37:19.60#ibcon#about to write, iclass 34, count 2 2006.285.20:37:19.60#ibcon#wrote, iclass 34, count 2 2006.285.20:37:19.60#ibcon#about to read 3, iclass 34, count 2 2006.285.20:37:19.63#ibcon#read 3, iclass 34, count 2 2006.285.20:37:19.63#ibcon#about to read 4, iclass 34, count 2 2006.285.20:37:19.63#ibcon#read 4, iclass 34, count 2 2006.285.20:37:19.63#ibcon#about to read 5, iclass 34, count 2 2006.285.20:37:19.63#ibcon#read 5, iclass 34, count 2 2006.285.20:37:19.63#ibcon#about to read 6, iclass 34, count 2 2006.285.20:37:19.63#ibcon#read 6, iclass 34, count 2 2006.285.20:37:19.63#ibcon#end of sib2, iclass 34, count 2 2006.285.20:37:19.63#ibcon#*after write, iclass 34, count 2 2006.285.20:37:19.63#ibcon#*before return 0, iclass 34, count 2 2006.285.20:37:19.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:37:19.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:37:19.63#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.20:37:19.63#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:19.63#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:37:19.75#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:37:19.75#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:37:19.75#ibcon#enter wrdev, iclass 34, count 0 2006.285.20:37:19.75#ibcon#first serial, iclass 34, count 0 2006.285.20:37:19.75#ibcon#enter sib2, iclass 34, count 0 2006.285.20:37:19.75#ibcon#flushed, iclass 34, count 0 2006.285.20:37:19.75#ibcon#about to write, iclass 34, count 0 2006.285.20:37:19.75#ibcon#wrote, iclass 34, count 0 2006.285.20:37:19.75#ibcon#about to read 3, iclass 34, count 0 2006.285.20:37:19.77#ibcon#read 3, iclass 34, count 0 2006.285.20:37:19.77#ibcon#about to read 4, iclass 34, count 0 2006.285.20:37:19.77#ibcon#read 4, iclass 34, count 0 2006.285.20:37:19.77#ibcon#about to read 5, iclass 34, count 0 2006.285.20:37:19.77#ibcon#read 5, iclass 34, count 0 2006.285.20:37:19.77#ibcon#about to read 6, iclass 34, count 0 2006.285.20:37:19.77#ibcon#read 6, iclass 34, count 0 2006.285.20:37:19.77#ibcon#end of sib2, iclass 34, count 0 2006.285.20:37:19.77#ibcon#*mode == 0, iclass 34, count 0 2006.285.20:37:19.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.20:37:19.77#ibcon#[25=USB\r\n] 2006.285.20:37:19.77#ibcon#*before write, iclass 34, count 0 2006.285.20:37:19.77#ibcon#enter sib2, iclass 34, count 0 2006.285.20:37:19.77#ibcon#flushed, iclass 34, count 0 2006.285.20:37:19.77#ibcon#about to write, iclass 34, count 0 2006.285.20:37:19.77#ibcon#wrote, iclass 34, count 0 2006.285.20:37:19.77#ibcon#about to read 3, iclass 34, count 0 2006.285.20:37:19.80#ibcon#read 3, iclass 34, count 0 2006.285.20:37:19.80#ibcon#about to read 4, iclass 34, count 0 2006.285.20:37:19.80#ibcon#read 4, iclass 34, count 0 2006.285.20:37:19.80#ibcon#about to read 5, iclass 34, count 0 2006.285.20:37:19.80#ibcon#read 5, iclass 34, count 0 2006.285.20:37:19.80#ibcon#about to read 6, iclass 34, count 0 2006.285.20:37:19.80#ibcon#read 6, iclass 34, count 0 2006.285.20:37:19.80#ibcon#end of sib2, iclass 34, count 0 2006.285.20:37:19.80#ibcon#*after write, iclass 34, count 0 2006.285.20:37:19.80#ibcon#*before return 0, iclass 34, count 0 2006.285.20:37:19.80#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:37:19.80#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:37:19.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.20:37:19.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.20:37:19.80$vck44/valo=2,534.99 2006.285.20:37:19.80#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.20:37:19.80#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.20:37:19.80#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:19.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:37:19.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:37:19.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:37:19.80#ibcon#enter wrdev, iclass 36, count 0 2006.285.20:37:19.80#ibcon#first serial, iclass 36, count 0 2006.285.20:37:19.80#ibcon#enter sib2, iclass 36, count 0 2006.285.20:37:19.80#ibcon#flushed, iclass 36, count 0 2006.285.20:37:19.80#ibcon#about to write, iclass 36, count 0 2006.285.20:37:19.80#ibcon#wrote, iclass 36, count 0 2006.285.20:37:19.80#ibcon#about to read 3, iclass 36, count 0 2006.285.20:37:19.82#ibcon#read 3, iclass 36, count 0 2006.285.20:37:19.82#ibcon#about to read 4, iclass 36, count 0 2006.285.20:37:19.82#ibcon#read 4, iclass 36, count 0 2006.285.20:37:19.82#ibcon#about to read 5, iclass 36, count 0 2006.285.20:37:19.82#ibcon#read 5, iclass 36, count 0 2006.285.20:37:19.82#ibcon#about to read 6, iclass 36, count 0 2006.285.20:37:19.82#ibcon#read 6, iclass 36, count 0 2006.285.20:37:19.82#ibcon#end of sib2, iclass 36, count 0 2006.285.20:37:19.82#ibcon#*mode == 0, iclass 36, count 0 2006.285.20:37:19.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.20:37:19.82#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.20:37:19.82#ibcon#*before write, iclass 36, count 0 2006.285.20:37:19.82#ibcon#enter sib2, iclass 36, count 0 2006.285.20:37:19.82#ibcon#flushed, iclass 36, count 0 2006.285.20:37:19.82#ibcon#about to write, iclass 36, count 0 2006.285.20:37:19.82#ibcon#wrote, iclass 36, count 0 2006.285.20:37:19.82#ibcon#about to read 3, iclass 36, count 0 2006.285.20:37:19.86#ibcon#read 3, iclass 36, count 0 2006.285.20:37:19.86#ibcon#about to read 4, iclass 36, count 0 2006.285.20:37:19.86#ibcon#read 4, iclass 36, count 0 2006.285.20:37:19.86#ibcon#about to read 5, iclass 36, count 0 2006.285.20:37:19.86#ibcon#read 5, iclass 36, count 0 2006.285.20:37:19.86#ibcon#about to read 6, iclass 36, count 0 2006.285.20:37:19.86#ibcon#read 6, iclass 36, count 0 2006.285.20:37:19.86#ibcon#end of sib2, iclass 36, count 0 2006.285.20:37:19.86#ibcon#*after write, iclass 36, count 0 2006.285.20:37:19.86#ibcon#*before return 0, iclass 36, count 0 2006.285.20:37:19.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:37:19.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:37:19.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.20:37:19.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.20:37:19.86$vck44/va=2,6 2006.285.20:37:19.86#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.20:37:19.86#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.20:37:19.86#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:19.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:37:19.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:37:19.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:37:19.92#ibcon#enter wrdev, iclass 38, count 2 2006.285.20:37:19.92#ibcon#first serial, iclass 38, count 2 2006.285.20:37:19.92#ibcon#enter sib2, iclass 38, count 2 2006.285.20:37:19.92#ibcon#flushed, iclass 38, count 2 2006.285.20:37:19.92#ibcon#about to write, iclass 38, count 2 2006.285.20:37:19.92#ibcon#wrote, iclass 38, count 2 2006.285.20:37:19.92#ibcon#about to read 3, iclass 38, count 2 2006.285.20:37:19.94#ibcon#read 3, iclass 38, count 2 2006.285.20:37:19.94#ibcon#about to read 4, iclass 38, count 2 2006.285.20:37:19.94#ibcon#read 4, iclass 38, count 2 2006.285.20:37:19.94#ibcon#about to read 5, iclass 38, count 2 2006.285.20:37:19.94#ibcon#read 5, iclass 38, count 2 2006.285.20:37:19.94#ibcon#about to read 6, iclass 38, count 2 2006.285.20:37:19.94#ibcon#read 6, iclass 38, count 2 2006.285.20:37:19.94#ibcon#end of sib2, iclass 38, count 2 2006.285.20:37:19.94#ibcon#*mode == 0, iclass 38, count 2 2006.285.20:37:19.94#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.20:37:19.94#ibcon#[25=AT02-06\r\n] 2006.285.20:37:19.94#ibcon#*before write, iclass 38, count 2 2006.285.20:37:19.94#ibcon#enter sib2, iclass 38, count 2 2006.285.20:37:19.94#ibcon#flushed, iclass 38, count 2 2006.285.20:37:19.94#ibcon#about to write, iclass 38, count 2 2006.285.20:37:19.94#ibcon#wrote, iclass 38, count 2 2006.285.20:37:19.94#ibcon#about to read 3, iclass 38, count 2 2006.285.20:37:19.97#ibcon#read 3, iclass 38, count 2 2006.285.20:37:19.97#ibcon#about to read 4, iclass 38, count 2 2006.285.20:37:19.97#ibcon#read 4, iclass 38, count 2 2006.285.20:37:19.97#ibcon#about to read 5, iclass 38, count 2 2006.285.20:37:19.97#ibcon#read 5, iclass 38, count 2 2006.285.20:37:19.97#ibcon#about to read 6, iclass 38, count 2 2006.285.20:37:19.97#ibcon#read 6, iclass 38, count 2 2006.285.20:37:19.97#ibcon#end of sib2, iclass 38, count 2 2006.285.20:37:19.97#ibcon#*after write, iclass 38, count 2 2006.285.20:37:19.97#ibcon#*before return 0, iclass 38, count 2 2006.285.20:37:19.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:37:19.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:37:19.97#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.20:37:19.97#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:19.97#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:37:20.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:37:20.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:37:20.09#ibcon#enter wrdev, iclass 38, count 0 2006.285.20:37:20.09#ibcon#first serial, iclass 38, count 0 2006.285.20:37:20.09#ibcon#enter sib2, iclass 38, count 0 2006.285.20:37:20.09#ibcon#flushed, iclass 38, count 0 2006.285.20:37:20.09#ibcon#about to write, iclass 38, count 0 2006.285.20:37:20.09#ibcon#wrote, iclass 38, count 0 2006.285.20:37:20.09#ibcon#about to read 3, iclass 38, count 0 2006.285.20:37:20.11#ibcon#read 3, iclass 38, count 0 2006.285.20:37:20.11#ibcon#about to read 4, iclass 38, count 0 2006.285.20:37:20.11#ibcon#read 4, iclass 38, count 0 2006.285.20:37:20.11#ibcon#about to read 5, iclass 38, count 0 2006.285.20:37:20.11#ibcon#read 5, iclass 38, count 0 2006.285.20:37:20.11#ibcon#about to read 6, iclass 38, count 0 2006.285.20:37:20.11#ibcon#read 6, iclass 38, count 0 2006.285.20:37:20.11#ibcon#end of sib2, iclass 38, count 0 2006.285.20:37:20.11#ibcon#*mode == 0, iclass 38, count 0 2006.285.20:37:20.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.20:37:20.11#ibcon#[25=USB\r\n] 2006.285.20:37:20.11#ibcon#*before write, iclass 38, count 0 2006.285.20:37:20.11#ibcon#enter sib2, iclass 38, count 0 2006.285.20:37:20.11#ibcon#flushed, iclass 38, count 0 2006.285.20:37:20.11#ibcon#about to write, iclass 38, count 0 2006.285.20:37:20.11#ibcon#wrote, iclass 38, count 0 2006.285.20:37:20.11#ibcon#about to read 3, iclass 38, count 0 2006.285.20:37:20.14#ibcon#read 3, iclass 38, count 0 2006.285.20:37:20.14#ibcon#about to read 4, iclass 38, count 0 2006.285.20:37:20.14#ibcon#read 4, iclass 38, count 0 2006.285.20:37:20.14#ibcon#about to read 5, iclass 38, count 0 2006.285.20:37:20.14#ibcon#read 5, iclass 38, count 0 2006.285.20:37:20.14#ibcon#about to read 6, iclass 38, count 0 2006.285.20:37:20.14#ibcon#read 6, iclass 38, count 0 2006.285.20:37:20.14#ibcon#end of sib2, iclass 38, count 0 2006.285.20:37:20.14#ibcon#*after write, iclass 38, count 0 2006.285.20:37:20.14#ibcon#*before return 0, iclass 38, count 0 2006.285.20:37:20.14#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:37:20.14#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:37:20.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.20:37:20.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.20:37:20.14$vck44/valo=3,564.99 2006.285.20:37:20.14#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.20:37:20.14#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.20:37:20.14#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:20.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:37:20.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:37:20.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:37:20.14#ibcon#enter wrdev, iclass 40, count 0 2006.285.20:37:20.14#ibcon#first serial, iclass 40, count 0 2006.285.20:37:20.14#ibcon#enter sib2, iclass 40, count 0 2006.285.20:37:20.14#ibcon#flushed, iclass 40, count 0 2006.285.20:37:20.14#ibcon#about to write, iclass 40, count 0 2006.285.20:37:20.14#ibcon#wrote, iclass 40, count 0 2006.285.20:37:20.14#ibcon#about to read 3, iclass 40, count 0 2006.285.20:37:20.16#ibcon#read 3, iclass 40, count 0 2006.285.20:37:20.16#ibcon#about to read 4, iclass 40, count 0 2006.285.20:37:20.16#ibcon#read 4, iclass 40, count 0 2006.285.20:37:20.16#ibcon#about to read 5, iclass 40, count 0 2006.285.20:37:20.16#ibcon#read 5, iclass 40, count 0 2006.285.20:37:20.16#ibcon#about to read 6, iclass 40, count 0 2006.285.20:37:20.16#ibcon#read 6, iclass 40, count 0 2006.285.20:37:20.16#ibcon#end of sib2, iclass 40, count 0 2006.285.20:37:20.16#ibcon#*mode == 0, iclass 40, count 0 2006.285.20:37:20.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.20:37:20.16#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.20:37:20.16#ibcon#*before write, iclass 40, count 0 2006.285.20:37:20.16#ibcon#enter sib2, iclass 40, count 0 2006.285.20:37:20.16#ibcon#flushed, iclass 40, count 0 2006.285.20:37:20.16#ibcon#about to write, iclass 40, count 0 2006.285.20:37:20.16#ibcon#wrote, iclass 40, count 0 2006.285.20:37:20.16#ibcon#about to read 3, iclass 40, count 0 2006.285.20:37:20.20#ibcon#read 3, iclass 40, count 0 2006.285.20:37:20.20#ibcon#about to read 4, iclass 40, count 0 2006.285.20:37:20.20#ibcon#read 4, iclass 40, count 0 2006.285.20:37:20.20#ibcon#about to read 5, iclass 40, count 0 2006.285.20:37:20.20#ibcon#read 5, iclass 40, count 0 2006.285.20:37:20.20#ibcon#about to read 6, iclass 40, count 0 2006.285.20:37:20.20#ibcon#read 6, iclass 40, count 0 2006.285.20:37:20.20#ibcon#end of sib2, iclass 40, count 0 2006.285.20:37:20.20#ibcon#*after write, iclass 40, count 0 2006.285.20:37:20.20#ibcon#*before return 0, iclass 40, count 0 2006.285.20:37:20.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:37:20.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:37:20.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.20:37:20.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.20:37:20.20$vck44/va=3,7 2006.285.20:37:20.20#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.20:37:20.20#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.20:37:20.20#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:20.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:37:20.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:37:20.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:37:20.26#ibcon#enter wrdev, iclass 4, count 2 2006.285.20:37:20.26#ibcon#first serial, iclass 4, count 2 2006.285.20:37:20.26#ibcon#enter sib2, iclass 4, count 2 2006.285.20:37:20.26#ibcon#flushed, iclass 4, count 2 2006.285.20:37:20.26#ibcon#about to write, iclass 4, count 2 2006.285.20:37:20.26#ibcon#wrote, iclass 4, count 2 2006.285.20:37:20.26#ibcon#about to read 3, iclass 4, count 2 2006.285.20:37:20.28#ibcon#read 3, iclass 4, count 2 2006.285.20:37:20.28#ibcon#about to read 4, iclass 4, count 2 2006.285.20:37:20.28#ibcon#read 4, iclass 4, count 2 2006.285.20:37:20.28#ibcon#about to read 5, iclass 4, count 2 2006.285.20:37:20.28#ibcon#read 5, iclass 4, count 2 2006.285.20:37:20.28#ibcon#about to read 6, iclass 4, count 2 2006.285.20:37:20.28#ibcon#read 6, iclass 4, count 2 2006.285.20:37:20.28#ibcon#end of sib2, iclass 4, count 2 2006.285.20:37:20.28#ibcon#*mode == 0, iclass 4, count 2 2006.285.20:37:20.28#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.20:37:20.28#ibcon#[25=AT03-07\r\n] 2006.285.20:37:20.28#ibcon#*before write, iclass 4, count 2 2006.285.20:37:20.28#ibcon#enter sib2, iclass 4, count 2 2006.285.20:37:20.28#ibcon#flushed, iclass 4, count 2 2006.285.20:37:20.28#ibcon#about to write, iclass 4, count 2 2006.285.20:37:20.28#ibcon#wrote, iclass 4, count 2 2006.285.20:37:20.28#ibcon#about to read 3, iclass 4, count 2 2006.285.20:37:20.31#ibcon#read 3, iclass 4, count 2 2006.285.20:37:20.31#ibcon#about to read 4, iclass 4, count 2 2006.285.20:37:20.31#ibcon#read 4, iclass 4, count 2 2006.285.20:37:20.31#ibcon#about to read 5, iclass 4, count 2 2006.285.20:37:20.31#ibcon#read 5, iclass 4, count 2 2006.285.20:37:20.31#ibcon#about to read 6, iclass 4, count 2 2006.285.20:37:20.31#ibcon#read 6, iclass 4, count 2 2006.285.20:37:20.31#ibcon#end of sib2, iclass 4, count 2 2006.285.20:37:20.31#ibcon#*after write, iclass 4, count 2 2006.285.20:37:20.31#ibcon#*before return 0, iclass 4, count 2 2006.285.20:37:20.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:37:20.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:37:20.31#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.20:37:20.31#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:20.31#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:37:20.43#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:37:20.73#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:37:20.73#ibcon#enter wrdev, iclass 4, count 0 2006.285.20:37:20.73#ibcon#first serial, iclass 4, count 0 2006.285.20:37:20.73#ibcon#enter sib2, iclass 4, count 0 2006.285.20:37:20.73#ibcon#flushed, iclass 4, count 0 2006.285.20:37:20.73#ibcon#about to write, iclass 4, count 0 2006.285.20:37:20.73#ibcon#wrote, iclass 4, count 0 2006.285.20:37:20.73#ibcon#about to read 3, iclass 4, count 0 2006.285.20:37:20.75#ibcon#read 3, iclass 4, count 0 2006.285.20:37:20.75#ibcon#about to read 4, iclass 4, count 0 2006.285.20:37:20.75#ibcon#read 4, iclass 4, count 0 2006.285.20:37:20.75#ibcon#about to read 5, iclass 4, count 0 2006.285.20:37:20.75#ibcon#read 5, iclass 4, count 0 2006.285.20:37:20.75#ibcon#about to read 6, iclass 4, count 0 2006.285.20:37:20.75#ibcon#read 6, iclass 4, count 0 2006.285.20:37:20.75#ibcon#end of sib2, iclass 4, count 0 2006.285.20:37:20.75#ibcon#*mode == 0, iclass 4, count 0 2006.285.20:37:20.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.20:37:20.75#ibcon#[25=USB\r\n] 2006.285.20:37:20.75#ibcon#*before write, iclass 4, count 0 2006.285.20:37:20.75#ibcon#enter sib2, iclass 4, count 0 2006.285.20:37:20.75#ibcon#flushed, iclass 4, count 0 2006.285.20:37:20.75#ibcon#about to write, iclass 4, count 0 2006.285.20:37:20.75#ibcon#wrote, iclass 4, count 0 2006.285.20:37:20.75#ibcon#about to read 3, iclass 4, count 0 2006.285.20:37:20.78#ibcon#read 3, iclass 4, count 0 2006.285.20:37:20.78#ibcon#about to read 4, iclass 4, count 0 2006.285.20:37:20.78#ibcon#read 4, iclass 4, count 0 2006.285.20:37:20.78#ibcon#about to read 5, iclass 4, count 0 2006.285.20:37:20.78#ibcon#read 5, iclass 4, count 0 2006.285.20:37:20.78#ibcon#about to read 6, iclass 4, count 0 2006.285.20:37:20.78#ibcon#read 6, iclass 4, count 0 2006.285.20:37:20.78#ibcon#end of sib2, iclass 4, count 0 2006.285.20:37:20.78#ibcon#*after write, iclass 4, count 0 2006.285.20:37:20.78#ibcon#*before return 0, iclass 4, count 0 2006.285.20:37:20.78#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:37:20.78#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:37:20.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.20:37:20.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.20:37:20.78$vck44/valo=4,624.99 2006.285.20:37:20.78#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.20:37:20.78#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.20:37:20.78#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:20.78#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:37:20.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:37:20.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:37:20.78#ibcon#enter wrdev, iclass 6, count 0 2006.285.20:37:20.78#ibcon#first serial, iclass 6, count 0 2006.285.20:37:20.78#ibcon#enter sib2, iclass 6, count 0 2006.285.20:37:20.78#ibcon#flushed, iclass 6, count 0 2006.285.20:37:20.78#ibcon#about to write, iclass 6, count 0 2006.285.20:37:20.78#ibcon#wrote, iclass 6, count 0 2006.285.20:37:20.78#ibcon#about to read 3, iclass 6, count 0 2006.285.20:37:20.80#ibcon#read 3, iclass 6, count 0 2006.285.20:37:20.80#ibcon#about to read 4, iclass 6, count 0 2006.285.20:37:20.80#ibcon#read 4, iclass 6, count 0 2006.285.20:37:20.80#ibcon#about to read 5, iclass 6, count 0 2006.285.20:37:20.80#ibcon#read 5, iclass 6, count 0 2006.285.20:37:20.80#ibcon#about to read 6, iclass 6, count 0 2006.285.20:37:20.80#ibcon#read 6, iclass 6, count 0 2006.285.20:37:20.80#ibcon#end of sib2, iclass 6, count 0 2006.285.20:37:20.80#ibcon#*mode == 0, iclass 6, count 0 2006.285.20:37:20.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.20:37:20.80#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.20:37:20.80#ibcon#*before write, iclass 6, count 0 2006.285.20:37:20.80#ibcon#enter sib2, iclass 6, count 0 2006.285.20:37:20.80#ibcon#flushed, iclass 6, count 0 2006.285.20:37:20.80#ibcon#about to write, iclass 6, count 0 2006.285.20:37:20.80#ibcon#wrote, iclass 6, count 0 2006.285.20:37:20.80#ibcon#about to read 3, iclass 6, count 0 2006.285.20:37:20.84#ibcon#read 3, iclass 6, count 0 2006.285.20:37:20.84#ibcon#about to read 4, iclass 6, count 0 2006.285.20:37:20.84#ibcon#read 4, iclass 6, count 0 2006.285.20:37:20.84#ibcon#about to read 5, iclass 6, count 0 2006.285.20:37:20.84#ibcon#read 5, iclass 6, count 0 2006.285.20:37:20.84#ibcon#about to read 6, iclass 6, count 0 2006.285.20:37:20.84#ibcon#read 6, iclass 6, count 0 2006.285.20:37:20.84#ibcon#end of sib2, iclass 6, count 0 2006.285.20:37:20.84#ibcon#*after write, iclass 6, count 0 2006.285.20:37:20.84#ibcon#*before return 0, iclass 6, count 0 2006.285.20:37:20.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:37:20.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:37:20.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.20:37:20.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.20:37:20.84$vck44/va=4,6 2006.285.20:37:20.84#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.20:37:20.84#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.20:37:20.84#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:20.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:37:20.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:37:20.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:37:20.90#ibcon#enter wrdev, iclass 10, count 2 2006.285.20:37:20.90#ibcon#first serial, iclass 10, count 2 2006.285.20:37:20.90#ibcon#enter sib2, iclass 10, count 2 2006.285.20:37:20.90#ibcon#flushed, iclass 10, count 2 2006.285.20:37:20.90#ibcon#about to write, iclass 10, count 2 2006.285.20:37:20.90#ibcon#wrote, iclass 10, count 2 2006.285.20:37:20.90#ibcon#about to read 3, iclass 10, count 2 2006.285.20:37:20.92#ibcon#read 3, iclass 10, count 2 2006.285.20:37:20.92#ibcon#about to read 4, iclass 10, count 2 2006.285.20:37:20.92#ibcon#read 4, iclass 10, count 2 2006.285.20:37:20.92#ibcon#about to read 5, iclass 10, count 2 2006.285.20:37:20.92#ibcon#read 5, iclass 10, count 2 2006.285.20:37:20.92#ibcon#about to read 6, iclass 10, count 2 2006.285.20:37:20.92#ibcon#read 6, iclass 10, count 2 2006.285.20:37:20.92#ibcon#end of sib2, iclass 10, count 2 2006.285.20:37:20.92#ibcon#*mode == 0, iclass 10, count 2 2006.285.20:37:20.92#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.20:37:20.92#ibcon#[25=AT04-06\r\n] 2006.285.20:37:20.92#ibcon#*before write, iclass 10, count 2 2006.285.20:37:20.92#ibcon#enter sib2, iclass 10, count 2 2006.285.20:37:20.92#ibcon#flushed, iclass 10, count 2 2006.285.20:37:20.92#ibcon#about to write, iclass 10, count 2 2006.285.20:37:20.92#ibcon#wrote, iclass 10, count 2 2006.285.20:37:20.92#ibcon#about to read 3, iclass 10, count 2 2006.285.20:37:20.95#ibcon#read 3, iclass 10, count 2 2006.285.20:37:20.95#ibcon#about to read 4, iclass 10, count 2 2006.285.20:37:20.95#ibcon#read 4, iclass 10, count 2 2006.285.20:37:20.95#ibcon#about to read 5, iclass 10, count 2 2006.285.20:37:20.95#ibcon#read 5, iclass 10, count 2 2006.285.20:37:20.95#ibcon#about to read 6, iclass 10, count 2 2006.285.20:37:20.95#ibcon#read 6, iclass 10, count 2 2006.285.20:37:20.95#ibcon#end of sib2, iclass 10, count 2 2006.285.20:37:20.95#ibcon#*after write, iclass 10, count 2 2006.285.20:37:20.95#ibcon#*before return 0, iclass 10, count 2 2006.285.20:37:20.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:37:20.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:37:20.95#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.20:37:20.95#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:20.95#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:37:21.07#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:37:21.07#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:37:21.07#ibcon#enter wrdev, iclass 10, count 0 2006.285.20:37:21.07#ibcon#first serial, iclass 10, count 0 2006.285.20:37:21.07#ibcon#enter sib2, iclass 10, count 0 2006.285.20:37:21.07#ibcon#flushed, iclass 10, count 0 2006.285.20:37:21.07#ibcon#about to write, iclass 10, count 0 2006.285.20:37:21.07#ibcon#wrote, iclass 10, count 0 2006.285.20:37:21.07#ibcon#about to read 3, iclass 10, count 0 2006.285.20:37:21.09#ibcon#read 3, iclass 10, count 0 2006.285.20:37:21.09#ibcon#about to read 4, iclass 10, count 0 2006.285.20:37:21.09#ibcon#read 4, iclass 10, count 0 2006.285.20:37:21.09#ibcon#about to read 5, iclass 10, count 0 2006.285.20:37:21.09#ibcon#read 5, iclass 10, count 0 2006.285.20:37:21.09#ibcon#about to read 6, iclass 10, count 0 2006.285.20:37:21.09#ibcon#read 6, iclass 10, count 0 2006.285.20:37:21.09#ibcon#end of sib2, iclass 10, count 0 2006.285.20:37:21.09#ibcon#*mode == 0, iclass 10, count 0 2006.285.20:37:21.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.20:37:21.09#ibcon#[25=USB\r\n] 2006.285.20:37:21.09#ibcon#*before write, iclass 10, count 0 2006.285.20:37:21.09#ibcon#enter sib2, iclass 10, count 0 2006.285.20:37:21.09#ibcon#flushed, iclass 10, count 0 2006.285.20:37:21.09#ibcon#about to write, iclass 10, count 0 2006.285.20:37:21.09#ibcon#wrote, iclass 10, count 0 2006.285.20:37:21.09#ibcon#about to read 3, iclass 10, count 0 2006.285.20:37:21.12#ibcon#read 3, iclass 10, count 0 2006.285.20:37:21.19#ibcon#about to read 4, iclass 10, count 0 2006.285.20:37:21.19#ibcon#read 4, iclass 10, count 0 2006.285.20:37:21.19#ibcon#about to read 5, iclass 10, count 0 2006.285.20:37:21.19#ibcon#read 5, iclass 10, count 0 2006.285.20:37:21.19#ibcon#about to read 6, iclass 10, count 0 2006.285.20:37:21.19#ibcon#read 6, iclass 10, count 0 2006.285.20:37:21.19#ibcon#end of sib2, iclass 10, count 0 2006.285.20:37:21.19#ibcon#*after write, iclass 10, count 0 2006.285.20:37:21.19#ibcon#*before return 0, iclass 10, count 0 2006.285.20:37:21.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:37:21.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:37:21.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.20:37:21.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.20:37:21.19$vck44/valo=5,734.99 2006.285.20:37:21.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.20:37:21.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.20:37:21.19#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:21.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:37:21.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:37:21.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:37:21.19#ibcon#enter wrdev, iclass 12, count 0 2006.285.20:37:21.19#ibcon#first serial, iclass 12, count 0 2006.285.20:37:21.19#ibcon#enter sib2, iclass 12, count 0 2006.285.20:37:21.19#ibcon#flushed, iclass 12, count 0 2006.285.20:37:21.19#ibcon#about to write, iclass 12, count 0 2006.285.20:37:21.20#ibcon#wrote, iclass 12, count 0 2006.285.20:37:21.20#ibcon#about to read 3, iclass 12, count 0 2006.285.20:37:21.21#ibcon#read 3, iclass 12, count 0 2006.285.20:37:21.21#ibcon#about to read 4, iclass 12, count 0 2006.285.20:37:21.21#ibcon#read 4, iclass 12, count 0 2006.285.20:37:21.21#ibcon#about to read 5, iclass 12, count 0 2006.285.20:37:21.21#ibcon#read 5, iclass 12, count 0 2006.285.20:37:21.21#ibcon#about to read 6, iclass 12, count 0 2006.285.20:37:21.21#ibcon#read 6, iclass 12, count 0 2006.285.20:37:21.21#ibcon#end of sib2, iclass 12, count 0 2006.285.20:37:21.21#ibcon#*mode == 0, iclass 12, count 0 2006.285.20:37:21.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.20:37:21.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.20:37:21.21#ibcon#*before write, iclass 12, count 0 2006.285.20:37:21.21#ibcon#enter sib2, iclass 12, count 0 2006.285.20:37:21.21#ibcon#flushed, iclass 12, count 0 2006.285.20:37:21.21#ibcon#about to write, iclass 12, count 0 2006.285.20:37:21.21#ibcon#wrote, iclass 12, count 0 2006.285.20:37:21.21#ibcon#about to read 3, iclass 12, count 0 2006.285.20:37:21.25#ibcon#read 3, iclass 12, count 0 2006.285.20:37:21.25#ibcon#about to read 4, iclass 12, count 0 2006.285.20:37:21.25#ibcon#read 4, iclass 12, count 0 2006.285.20:37:21.25#ibcon#about to read 5, iclass 12, count 0 2006.285.20:37:21.25#ibcon#read 5, iclass 12, count 0 2006.285.20:37:21.25#ibcon#about to read 6, iclass 12, count 0 2006.285.20:37:21.25#ibcon#read 6, iclass 12, count 0 2006.285.20:37:21.25#ibcon#end of sib2, iclass 12, count 0 2006.285.20:37:21.25#ibcon#*after write, iclass 12, count 0 2006.285.20:37:21.25#ibcon#*before return 0, iclass 12, count 0 2006.285.20:37:21.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:37:21.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:37:21.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.20:37:21.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.20:37:21.25$vck44/va=5,3 2006.285.20:37:21.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.20:37:21.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.20:37:21.25#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:21.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:37:21.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:37:21.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:37:21.31#ibcon#enter wrdev, iclass 14, count 2 2006.285.20:37:21.31#ibcon#first serial, iclass 14, count 2 2006.285.20:37:21.31#ibcon#enter sib2, iclass 14, count 2 2006.285.20:37:21.31#ibcon#flushed, iclass 14, count 2 2006.285.20:37:21.31#ibcon#about to write, iclass 14, count 2 2006.285.20:37:21.31#ibcon#wrote, iclass 14, count 2 2006.285.20:37:21.31#ibcon#about to read 3, iclass 14, count 2 2006.285.20:37:21.33#ibcon#read 3, iclass 14, count 2 2006.285.20:37:21.33#ibcon#about to read 4, iclass 14, count 2 2006.285.20:37:21.33#ibcon#read 4, iclass 14, count 2 2006.285.20:37:21.33#ibcon#about to read 5, iclass 14, count 2 2006.285.20:37:21.33#ibcon#read 5, iclass 14, count 2 2006.285.20:37:21.33#ibcon#about to read 6, iclass 14, count 2 2006.285.20:37:21.33#ibcon#read 6, iclass 14, count 2 2006.285.20:37:21.33#ibcon#end of sib2, iclass 14, count 2 2006.285.20:37:21.33#ibcon#*mode == 0, iclass 14, count 2 2006.285.20:37:21.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.20:37:21.33#ibcon#[25=AT05-03\r\n] 2006.285.20:37:21.33#ibcon#*before write, iclass 14, count 2 2006.285.20:37:21.33#ibcon#enter sib2, iclass 14, count 2 2006.285.20:37:21.33#ibcon#flushed, iclass 14, count 2 2006.285.20:37:21.33#ibcon#about to write, iclass 14, count 2 2006.285.20:37:21.33#ibcon#wrote, iclass 14, count 2 2006.285.20:37:21.33#ibcon#about to read 3, iclass 14, count 2 2006.285.20:37:21.36#ibcon#read 3, iclass 14, count 2 2006.285.20:37:21.36#ibcon#about to read 4, iclass 14, count 2 2006.285.20:37:21.36#ibcon#read 4, iclass 14, count 2 2006.285.20:37:21.36#ibcon#about to read 5, iclass 14, count 2 2006.285.20:37:21.36#ibcon#read 5, iclass 14, count 2 2006.285.20:37:21.36#ibcon#about to read 6, iclass 14, count 2 2006.285.20:37:21.36#ibcon#read 6, iclass 14, count 2 2006.285.20:37:21.36#ibcon#end of sib2, iclass 14, count 2 2006.285.20:37:21.36#ibcon#*after write, iclass 14, count 2 2006.285.20:37:21.36#ibcon#*before return 0, iclass 14, count 2 2006.285.20:37:21.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:37:21.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:37:21.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.20:37:21.36#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:21.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:37:21.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:37:21.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:37:21.48#ibcon#enter wrdev, iclass 14, count 0 2006.285.20:37:21.48#ibcon#first serial, iclass 14, count 0 2006.285.20:37:21.48#ibcon#enter sib2, iclass 14, count 0 2006.285.20:37:21.48#ibcon#flushed, iclass 14, count 0 2006.285.20:37:21.48#ibcon#about to write, iclass 14, count 0 2006.285.20:37:21.48#ibcon#wrote, iclass 14, count 0 2006.285.20:37:21.48#ibcon#about to read 3, iclass 14, count 0 2006.285.20:37:21.50#ibcon#read 3, iclass 14, count 0 2006.285.20:37:21.50#ibcon#about to read 4, iclass 14, count 0 2006.285.20:37:21.50#ibcon#read 4, iclass 14, count 0 2006.285.20:37:21.50#ibcon#about to read 5, iclass 14, count 0 2006.285.20:37:21.50#ibcon#read 5, iclass 14, count 0 2006.285.20:37:21.50#ibcon#about to read 6, iclass 14, count 0 2006.285.20:37:21.50#ibcon#read 6, iclass 14, count 0 2006.285.20:37:21.50#ibcon#end of sib2, iclass 14, count 0 2006.285.20:37:21.50#ibcon#*mode == 0, iclass 14, count 0 2006.285.20:37:21.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.20:37:21.50#ibcon#[25=USB\r\n] 2006.285.20:37:21.50#ibcon#*before write, iclass 14, count 0 2006.285.20:37:21.50#ibcon#enter sib2, iclass 14, count 0 2006.285.20:37:21.50#ibcon#flushed, iclass 14, count 0 2006.285.20:37:21.50#ibcon#about to write, iclass 14, count 0 2006.285.20:37:21.50#ibcon#wrote, iclass 14, count 0 2006.285.20:37:21.50#ibcon#about to read 3, iclass 14, count 0 2006.285.20:37:21.53#ibcon#read 3, iclass 14, count 0 2006.285.20:37:21.59#ibcon#about to read 4, iclass 14, count 0 2006.285.20:37:21.59#ibcon#read 4, iclass 14, count 0 2006.285.20:37:21.59#ibcon#about to read 5, iclass 14, count 0 2006.285.20:37:21.59#ibcon#read 5, iclass 14, count 0 2006.285.20:37:21.59#ibcon#about to read 6, iclass 14, count 0 2006.285.20:37:21.59#ibcon#read 6, iclass 14, count 0 2006.285.20:37:21.59#ibcon#end of sib2, iclass 14, count 0 2006.285.20:37:21.59#ibcon#*after write, iclass 14, count 0 2006.285.20:37:21.59#ibcon#*before return 0, iclass 14, count 0 2006.285.20:37:21.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:37:21.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:37:21.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.20:37:21.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.20:37:21.60$vck44/valo=6,814.99 2006.285.20:37:21.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.20:37:21.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.20:37:21.60#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:21.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:37:21.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:37:21.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:37:21.60#ibcon#enter wrdev, iclass 16, count 0 2006.285.20:37:21.60#ibcon#first serial, iclass 16, count 0 2006.285.20:37:21.60#ibcon#enter sib2, iclass 16, count 0 2006.285.20:37:21.60#ibcon#flushed, iclass 16, count 0 2006.285.20:37:21.60#ibcon#about to write, iclass 16, count 0 2006.285.20:37:21.60#ibcon#wrote, iclass 16, count 0 2006.285.20:37:21.60#ibcon#about to read 3, iclass 16, count 0 2006.285.20:37:21.61#ibcon#read 3, iclass 16, count 0 2006.285.20:37:21.61#ibcon#about to read 4, iclass 16, count 0 2006.285.20:37:21.61#ibcon#read 4, iclass 16, count 0 2006.285.20:37:21.61#ibcon#about to read 5, iclass 16, count 0 2006.285.20:37:21.61#ibcon#read 5, iclass 16, count 0 2006.285.20:37:21.61#ibcon#about to read 6, iclass 16, count 0 2006.285.20:37:21.61#ibcon#read 6, iclass 16, count 0 2006.285.20:37:21.61#ibcon#end of sib2, iclass 16, count 0 2006.285.20:37:21.61#ibcon#*mode == 0, iclass 16, count 0 2006.285.20:37:21.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.20:37:21.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.20:37:21.61#ibcon#*before write, iclass 16, count 0 2006.285.20:37:21.61#ibcon#enter sib2, iclass 16, count 0 2006.285.20:37:21.61#ibcon#flushed, iclass 16, count 0 2006.285.20:37:21.61#ibcon#about to write, iclass 16, count 0 2006.285.20:37:21.61#ibcon#wrote, iclass 16, count 0 2006.285.20:37:21.61#ibcon#about to read 3, iclass 16, count 0 2006.285.20:37:21.65#ibcon#read 3, iclass 16, count 0 2006.285.20:37:21.65#ibcon#about to read 4, iclass 16, count 0 2006.285.20:37:21.65#ibcon#read 4, iclass 16, count 0 2006.285.20:37:21.65#ibcon#about to read 5, iclass 16, count 0 2006.285.20:37:21.65#ibcon#read 5, iclass 16, count 0 2006.285.20:37:21.65#ibcon#about to read 6, iclass 16, count 0 2006.285.20:37:21.65#ibcon#read 6, iclass 16, count 0 2006.285.20:37:21.65#ibcon#end of sib2, iclass 16, count 0 2006.285.20:37:21.65#ibcon#*after write, iclass 16, count 0 2006.285.20:37:21.65#ibcon#*before return 0, iclass 16, count 0 2006.285.20:37:21.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:37:21.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:37:21.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.20:37:21.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.20:37:21.65$vck44/va=6,4 2006.285.20:37:21.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.20:37:21.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.20:37:21.65#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:21.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:37:21.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:37:21.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:37:21.71#ibcon#enter wrdev, iclass 18, count 2 2006.285.20:37:21.71#ibcon#first serial, iclass 18, count 2 2006.285.20:37:21.71#ibcon#enter sib2, iclass 18, count 2 2006.285.20:37:21.71#ibcon#flushed, iclass 18, count 2 2006.285.20:37:21.71#ibcon#about to write, iclass 18, count 2 2006.285.20:37:21.71#ibcon#wrote, iclass 18, count 2 2006.285.20:37:21.71#ibcon#about to read 3, iclass 18, count 2 2006.285.20:37:21.73#ibcon#read 3, iclass 18, count 2 2006.285.20:37:21.73#ibcon#about to read 4, iclass 18, count 2 2006.285.20:37:21.73#ibcon#read 4, iclass 18, count 2 2006.285.20:37:21.73#ibcon#about to read 5, iclass 18, count 2 2006.285.20:37:21.73#ibcon#read 5, iclass 18, count 2 2006.285.20:37:21.73#ibcon#about to read 6, iclass 18, count 2 2006.285.20:37:21.73#ibcon#read 6, iclass 18, count 2 2006.285.20:37:21.73#ibcon#end of sib2, iclass 18, count 2 2006.285.20:37:21.73#ibcon#*mode == 0, iclass 18, count 2 2006.285.20:37:21.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.20:37:21.73#ibcon#[25=AT06-04\r\n] 2006.285.20:37:21.73#ibcon#*before write, iclass 18, count 2 2006.285.20:37:21.73#ibcon#enter sib2, iclass 18, count 2 2006.285.20:37:21.73#ibcon#flushed, iclass 18, count 2 2006.285.20:37:21.73#ibcon#about to write, iclass 18, count 2 2006.285.20:37:21.73#ibcon#wrote, iclass 18, count 2 2006.285.20:37:21.73#ibcon#about to read 3, iclass 18, count 2 2006.285.20:37:21.76#ibcon#read 3, iclass 18, count 2 2006.285.20:37:21.76#ibcon#about to read 4, iclass 18, count 2 2006.285.20:37:21.76#ibcon#read 4, iclass 18, count 2 2006.285.20:37:21.76#ibcon#about to read 5, iclass 18, count 2 2006.285.20:37:21.76#ibcon#read 5, iclass 18, count 2 2006.285.20:37:21.76#ibcon#about to read 6, iclass 18, count 2 2006.285.20:37:21.76#ibcon#read 6, iclass 18, count 2 2006.285.20:37:21.76#ibcon#end of sib2, iclass 18, count 2 2006.285.20:37:21.76#ibcon#*after write, iclass 18, count 2 2006.285.20:37:21.76#ibcon#*before return 0, iclass 18, count 2 2006.285.20:37:21.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:37:21.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:37:21.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.20:37:21.76#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:21.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:37:21.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:37:21.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:37:21.88#ibcon#enter wrdev, iclass 18, count 0 2006.285.20:37:21.88#ibcon#first serial, iclass 18, count 0 2006.285.20:37:21.88#ibcon#enter sib2, iclass 18, count 0 2006.285.20:37:21.88#ibcon#flushed, iclass 18, count 0 2006.285.20:37:21.88#ibcon#about to write, iclass 18, count 0 2006.285.20:37:21.88#ibcon#wrote, iclass 18, count 0 2006.285.20:37:21.88#ibcon#about to read 3, iclass 18, count 0 2006.285.20:37:21.90#ibcon#read 3, iclass 18, count 0 2006.285.20:37:21.90#ibcon#about to read 4, iclass 18, count 0 2006.285.20:37:21.90#ibcon#read 4, iclass 18, count 0 2006.285.20:37:21.90#ibcon#about to read 5, iclass 18, count 0 2006.285.20:37:21.90#ibcon#read 5, iclass 18, count 0 2006.285.20:37:21.90#ibcon#about to read 6, iclass 18, count 0 2006.285.20:37:21.90#ibcon#read 6, iclass 18, count 0 2006.285.20:37:21.90#ibcon#end of sib2, iclass 18, count 0 2006.285.20:37:21.90#ibcon#*mode == 0, iclass 18, count 0 2006.285.20:37:21.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.20:37:21.90#ibcon#[25=USB\r\n] 2006.285.20:37:21.90#ibcon#*before write, iclass 18, count 0 2006.285.20:37:21.90#ibcon#enter sib2, iclass 18, count 0 2006.285.20:37:21.90#ibcon#flushed, iclass 18, count 0 2006.285.20:37:21.90#ibcon#about to write, iclass 18, count 0 2006.285.20:37:21.90#ibcon#wrote, iclass 18, count 0 2006.285.20:37:21.90#ibcon#about to read 3, iclass 18, count 0 2006.285.20:37:21.93#ibcon#read 3, iclass 18, count 0 2006.285.20:37:21.93#ibcon#about to read 4, iclass 18, count 0 2006.285.20:37:21.93#ibcon#read 4, iclass 18, count 0 2006.285.20:37:21.93#ibcon#about to read 5, iclass 18, count 0 2006.285.20:37:21.93#ibcon#read 5, iclass 18, count 0 2006.285.20:37:21.93#ibcon#about to read 6, iclass 18, count 0 2006.285.20:37:21.93#ibcon#read 6, iclass 18, count 0 2006.285.20:37:21.93#ibcon#end of sib2, iclass 18, count 0 2006.285.20:37:21.93#ibcon#*after write, iclass 18, count 0 2006.285.20:37:21.93#ibcon#*before return 0, iclass 18, count 0 2006.285.20:37:21.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:37:21.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:37:21.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.20:37:21.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.20:37:21.93$vck44/valo=7,864.99 2006.285.20:37:21.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.20:37:21.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.20:37:21.93#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:21.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:37:21.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:37:21.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:37:21.93#ibcon#enter wrdev, iclass 20, count 0 2006.285.20:37:21.93#ibcon#first serial, iclass 20, count 0 2006.285.20:37:21.93#ibcon#enter sib2, iclass 20, count 0 2006.285.20:37:21.93#ibcon#flushed, iclass 20, count 0 2006.285.20:37:21.93#ibcon#about to write, iclass 20, count 0 2006.285.20:37:21.93#ibcon#wrote, iclass 20, count 0 2006.285.20:37:21.93#ibcon#about to read 3, iclass 20, count 0 2006.285.20:37:21.95#ibcon#read 3, iclass 20, count 0 2006.285.20:37:21.95#ibcon#about to read 4, iclass 20, count 0 2006.285.20:37:21.95#ibcon#read 4, iclass 20, count 0 2006.285.20:37:21.95#ibcon#about to read 5, iclass 20, count 0 2006.285.20:37:21.95#ibcon#read 5, iclass 20, count 0 2006.285.20:37:21.95#ibcon#about to read 6, iclass 20, count 0 2006.285.20:37:21.95#ibcon#read 6, iclass 20, count 0 2006.285.20:37:21.95#ibcon#end of sib2, iclass 20, count 0 2006.285.20:37:21.95#ibcon#*mode == 0, iclass 20, count 0 2006.285.20:37:21.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.20:37:21.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.20:37:21.95#ibcon#*before write, iclass 20, count 0 2006.285.20:37:21.95#ibcon#enter sib2, iclass 20, count 0 2006.285.20:37:21.95#ibcon#flushed, iclass 20, count 0 2006.285.20:37:21.95#ibcon#about to write, iclass 20, count 0 2006.285.20:37:21.95#ibcon#wrote, iclass 20, count 0 2006.285.20:37:21.95#ibcon#about to read 3, iclass 20, count 0 2006.285.20:37:21.99#ibcon#read 3, iclass 20, count 0 2006.285.20:37:21.99#ibcon#about to read 4, iclass 20, count 0 2006.285.20:37:21.99#ibcon#read 4, iclass 20, count 0 2006.285.20:37:21.99#ibcon#about to read 5, iclass 20, count 0 2006.285.20:37:21.99#ibcon#read 5, iclass 20, count 0 2006.285.20:37:21.99#ibcon#about to read 6, iclass 20, count 0 2006.285.20:37:21.99#ibcon#read 6, iclass 20, count 0 2006.285.20:37:21.99#ibcon#end of sib2, iclass 20, count 0 2006.285.20:37:21.99#ibcon#*after write, iclass 20, count 0 2006.285.20:37:21.99#ibcon#*before return 0, iclass 20, count 0 2006.285.20:37:21.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:37:21.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:37:21.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.20:37:21.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.20:37:21.99$vck44/va=7,4 2006.285.20:37:21.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.20:37:21.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.20:37:21.99#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:21.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:37:22.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:37:22.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:37:22.05#ibcon#enter wrdev, iclass 22, count 2 2006.285.20:37:22.05#ibcon#first serial, iclass 22, count 2 2006.285.20:37:22.05#ibcon#enter sib2, iclass 22, count 2 2006.285.20:37:22.05#ibcon#flushed, iclass 22, count 2 2006.285.20:37:22.05#ibcon#about to write, iclass 22, count 2 2006.285.20:37:22.05#ibcon#wrote, iclass 22, count 2 2006.285.20:37:22.05#ibcon#about to read 3, iclass 22, count 2 2006.285.20:37:22.07#ibcon#read 3, iclass 22, count 2 2006.285.20:37:22.07#ibcon#about to read 4, iclass 22, count 2 2006.285.20:37:22.07#ibcon#read 4, iclass 22, count 2 2006.285.20:37:22.07#ibcon#about to read 5, iclass 22, count 2 2006.285.20:37:22.07#ibcon#read 5, iclass 22, count 2 2006.285.20:37:22.07#ibcon#about to read 6, iclass 22, count 2 2006.285.20:37:22.07#ibcon#read 6, iclass 22, count 2 2006.285.20:37:22.07#ibcon#end of sib2, iclass 22, count 2 2006.285.20:37:22.07#ibcon#*mode == 0, iclass 22, count 2 2006.285.20:37:22.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.20:37:22.07#ibcon#[25=AT07-04\r\n] 2006.285.20:37:22.07#ibcon#*before write, iclass 22, count 2 2006.285.20:37:22.07#ibcon#enter sib2, iclass 22, count 2 2006.285.20:37:22.07#ibcon#flushed, iclass 22, count 2 2006.285.20:37:22.07#ibcon#about to write, iclass 22, count 2 2006.285.20:37:22.07#ibcon#wrote, iclass 22, count 2 2006.285.20:37:22.07#ibcon#about to read 3, iclass 22, count 2 2006.285.20:37:22.10#ibcon#read 3, iclass 22, count 2 2006.285.20:37:22.10#ibcon#about to read 4, iclass 22, count 2 2006.285.20:37:22.10#ibcon#read 4, iclass 22, count 2 2006.285.20:37:22.10#ibcon#about to read 5, iclass 22, count 2 2006.285.20:37:22.10#ibcon#read 5, iclass 22, count 2 2006.285.20:37:22.10#ibcon#about to read 6, iclass 22, count 2 2006.285.20:37:22.10#ibcon#read 6, iclass 22, count 2 2006.285.20:37:22.10#ibcon#end of sib2, iclass 22, count 2 2006.285.20:37:22.10#ibcon#*after write, iclass 22, count 2 2006.285.20:37:22.10#ibcon#*before return 0, iclass 22, count 2 2006.285.20:37:22.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:37:22.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:37:22.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.20:37:22.10#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:22.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:37:22.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:37:22.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:37:22.22#ibcon#enter wrdev, iclass 22, count 0 2006.285.20:37:22.22#ibcon#first serial, iclass 22, count 0 2006.285.20:37:22.22#ibcon#enter sib2, iclass 22, count 0 2006.285.20:37:22.22#ibcon#flushed, iclass 22, count 0 2006.285.20:37:22.22#ibcon#about to write, iclass 22, count 0 2006.285.20:37:22.22#ibcon#wrote, iclass 22, count 0 2006.285.20:37:22.22#ibcon#about to read 3, iclass 22, count 0 2006.285.20:37:22.24#ibcon#read 3, iclass 22, count 0 2006.285.20:37:22.24#ibcon#about to read 4, iclass 22, count 0 2006.285.20:37:22.24#ibcon#read 4, iclass 22, count 0 2006.285.20:37:22.24#ibcon#about to read 5, iclass 22, count 0 2006.285.20:37:22.24#ibcon#read 5, iclass 22, count 0 2006.285.20:37:22.24#ibcon#about to read 6, iclass 22, count 0 2006.285.20:37:22.24#ibcon#read 6, iclass 22, count 0 2006.285.20:37:22.24#ibcon#end of sib2, iclass 22, count 0 2006.285.20:37:22.24#ibcon#*mode == 0, iclass 22, count 0 2006.285.20:37:22.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.20:37:22.24#ibcon#[25=USB\r\n] 2006.285.20:37:22.24#ibcon#*before write, iclass 22, count 0 2006.285.20:37:22.24#ibcon#enter sib2, iclass 22, count 0 2006.285.20:37:22.24#ibcon#flushed, iclass 22, count 0 2006.285.20:37:22.24#ibcon#about to write, iclass 22, count 0 2006.285.20:37:22.24#ibcon#wrote, iclass 22, count 0 2006.285.20:37:22.24#ibcon#about to read 3, iclass 22, count 0 2006.285.20:37:22.27#ibcon#read 3, iclass 22, count 0 2006.285.20:37:22.27#ibcon#about to read 4, iclass 22, count 0 2006.285.20:37:22.27#ibcon#read 4, iclass 22, count 0 2006.285.20:37:22.27#ibcon#about to read 5, iclass 22, count 0 2006.285.20:37:22.27#ibcon#read 5, iclass 22, count 0 2006.285.20:37:22.27#ibcon#about to read 6, iclass 22, count 0 2006.285.20:37:22.27#ibcon#read 6, iclass 22, count 0 2006.285.20:37:22.27#ibcon#end of sib2, iclass 22, count 0 2006.285.20:37:22.27#ibcon#*after write, iclass 22, count 0 2006.285.20:37:22.27#ibcon#*before return 0, iclass 22, count 0 2006.285.20:37:22.27#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:37:22.27#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:37:22.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.20:37:22.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.20:37:22.27$vck44/valo=8,884.99 2006.285.20:37:22.27#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.20:37:22.27#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.20:37:22.27#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:22.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:37:22.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:37:22.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:37:22.27#ibcon#enter wrdev, iclass 24, count 0 2006.285.20:37:22.27#ibcon#first serial, iclass 24, count 0 2006.285.20:37:22.27#ibcon#enter sib2, iclass 24, count 0 2006.285.20:37:22.27#ibcon#flushed, iclass 24, count 0 2006.285.20:37:22.27#ibcon#about to write, iclass 24, count 0 2006.285.20:37:22.27#ibcon#wrote, iclass 24, count 0 2006.285.20:37:22.27#ibcon#about to read 3, iclass 24, count 0 2006.285.20:37:22.29#ibcon#read 3, iclass 24, count 0 2006.285.20:37:22.29#ibcon#about to read 4, iclass 24, count 0 2006.285.20:37:22.29#ibcon#read 4, iclass 24, count 0 2006.285.20:37:22.29#ibcon#about to read 5, iclass 24, count 0 2006.285.20:37:22.29#ibcon#read 5, iclass 24, count 0 2006.285.20:37:22.29#ibcon#about to read 6, iclass 24, count 0 2006.285.20:37:22.29#ibcon#read 6, iclass 24, count 0 2006.285.20:37:22.29#ibcon#end of sib2, iclass 24, count 0 2006.285.20:37:22.29#ibcon#*mode == 0, iclass 24, count 0 2006.285.20:37:22.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.20:37:22.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.20:37:22.29#ibcon#*before write, iclass 24, count 0 2006.285.20:37:22.29#ibcon#enter sib2, iclass 24, count 0 2006.285.20:37:22.29#ibcon#flushed, iclass 24, count 0 2006.285.20:37:22.29#ibcon#about to write, iclass 24, count 0 2006.285.20:37:22.29#ibcon#wrote, iclass 24, count 0 2006.285.20:37:22.29#ibcon#about to read 3, iclass 24, count 0 2006.285.20:37:22.33#ibcon#read 3, iclass 24, count 0 2006.285.20:37:22.33#ibcon#about to read 4, iclass 24, count 0 2006.285.20:37:22.33#ibcon#read 4, iclass 24, count 0 2006.285.20:37:22.33#ibcon#about to read 5, iclass 24, count 0 2006.285.20:37:22.33#ibcon#read 5, iclass 24, count 0 2006.285.20:37:22.33#ibcon#about to read 6, iclass 24, count 0 2006.285.20:37:22.33#ibcon#read 6, iclass 24, count 0 2006.285.20:37:22.33#ibcon#end of sib2, iclass 24, count 0 2006.285.20:37:22.33#ibcon#*after write, iclass 24, count 0 2006.285.20:37:22.33#ibcon#*before return 0, iclass 24, count 0 2006.285.20:37:22.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:37:22.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:37:22.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.20:37:22.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.20:37:22.33$vck44/va=8,3 2006.285.20:37:22.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.20:37:22.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.20:37:22.47#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:22.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:37:22.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:37:22.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:37:22.47#ibcon#enter wrdev, iclass 26, count 2 2006.285.20:37:22.47#ibcon#first serial, iclass 26, count 2 2006.285.20:37:22.47#ibcon#enter sib2, iclass 26, count 2 2006.285.20:37:22.47#ibcon#flushed, iclass 26, count 2 2006.285.20:37:22.47#ibcon#about to write, iclass 26, count 2 2006.285.20:37:22.47#ibcon#wrote, iclass 26, count 2 2006.285.20:37:22.47#ibcon#about to read 3, iclass 26, count 2 2006.285.20:37:22.49#ibcon#read 3, iclass 26, count 2 2006.285.20:37:22.49#ibcon#about to read 4, iclass 26, count 2 2006.285.20:37:22.49#ibcon#read 4, iclass 26, count 2 2006.285.20:37:22.49#ibcon#about to read 5, iclass 26, count 2 2006.285.20:37:22.49#ibcon#read 5, iclass 26, count 2 2006.285.20:37:22.49#ibcon#about to read 6, iclass 26, count 2 2006.285.20:37:22.49#ibcon#read 6, iclass 26, count 2 2006.285.20:37:22.49#ibcon#end of sib2, iclass 26, count 2 2006.285.20:37:22.49#ibcon#*mode == 0, iclass 26, count 2 2006.285.20:37:22.49#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.20:37:22.49#ibcon#[25=AT08-03\r\n] 2006.285.20:37:22.49#ibcon#*before write, iclass 26, count 2 2006.285.20:37:22.49#ibcon#enter sib2, iclass 26, count 2 2006.285.20:37:22.49#ibcon#flushed, iclass 26, count 2 2006.285.20:37:22.49#ibcon#about to write, iclass 26, count 2 2006.285.20:37:22.49#ibcon#wrote, iclass 26, count 2 2006.285.20:37:22.49#ibcon#about to read 3, iclass 26, count 2 2006.285.20:37:22.52#ibcon#read 3, iclass 26, count 2 2006.285.20:37:22.52#ibcon#about to read 4, iclass 26, count 2 2006.285.20:37:22.52#ibcon#read 4, iclass 26, count 2 2006.285.20:37:22.52#ibcon#about to read 5, iclass 26, count 2 2006.285.20:37:22.52#ibcon#read 5, iclass 26, count 2 2006.285.20:37:22.52#ibcon#about to read 6, iclass 26, count 2 2006.285.20:37:22.52#ibcon#read 6, iclass 26, count 2 2006.285.20:37:22.52#ibcon#end of sib2, iclass 26, count 2 2006.285.20:37:22.52#ibcon#*after write, iclass 26, count 2 2006.285.20:37:22.52#ibcon#*before return 0, iclass 26, count 2 2006.285.20:37:22.52#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:37:22.52#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.20:37:22.52#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.20:37:22.52#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:22.52#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:37:22.64#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:37:22.64#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:37:22.64#ibcon#enter wrdev, iclass 26, count 0 2006.285.20:37:22.64#ibcon#first serial, iclass 26, count 0 2006.285.20:37:22.64#ibcon#enter sib2, iclass 26, count 0 2006.285.20:37:22.64#ibcon#flushed, iclass 26, count 0 2006.285.20:37:22.64#ibcon#about to write, iclass 26, count 0 2006.285.20:37:22.64#ibcon#wrote, iclass 26, count 0 2006.285.20:37:22.64#ibcon#about to read 3, iclass 26, count 0 2006.285.20:37:22.66#ibcon#read 3, iclass 26, count 0 2006.285.20:37:22.66#ibcon#about to read 4, iclass 26, count 0 2006.285.20:37:22.66#ibcon#read 4, iclass 26, count 0 2006.285.20:37:22.66#ibcon#about to read 5, iclass 26, count 0 2006.285.20:37:22.66#ibcon#read 5, iclass 26, count 0 2006.285.20:37:22.66#ibcon#about to read 6, iclass 26, count 0 2006.285.20:37:22.66#ibcon#read 6, iclass 26, count 0 2006.285.20:37:22.66#ibcon#end of sib2, iclass 26, count 0 2006.285.20:37:22.66#ibcon#*mode == 0, iclass 26, count 0 2006.285.20:37:22.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.20:37:22.66#ibcon#[25=USB\r\n] 2006.285.20:37:22.66#ibcon#*before write, iclass 26, count 0 2006.285.20:37:22.66#ibcon#enter sib2, iclass 26, count 0 2006.285.20:37:22.66#ibcon#flushed, iclass 26, count 0 2006.285.20:37:22.66#ibcon#about to write, iclass 26, count 0 2006.285.20:37:22.66#ibcon#wrote, iclass 26, count 0 2006.285.20:37:22.66#ibcon#about to read 3, iclass 26, count 0 2006.285.20:37:22.69#ibcon#read 3, iclass 26, count 0 2006.285.20:37:22.69#ibcon#about to read 4, iclass 26, count 0 2006.285.20:37:22.69#ibcon#read 4, iclass 26, count 0 2006.285.20:37:22.69#ibcon#about to read 5, iclass 26, count 0 2006.285.20:37:22.69#ibcon#read 5, iclass 26, count 0 2006.285.20:37:22.69#ibcon#about to read 6, iclass 26, count 0 2006.285.20:37:22.69#ibcon#read 6, iclass 26, count 0 2006.285.20:37:22.69#ibcon#end of sib2, iclass 26, count 0 2006.285.20:37:22.69#ibcon#*after write, iclass 26, count 0 2006.285.20:37:22.69#ibcon#*before return 0, iclass 26, count 0 2006.285.20:37:22.69#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:37:22.69#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.20:37:22.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.20:37:22.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.20:37:22.69$vck44/vblo=1,629.99 2006.285.20:37:22.69#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.20:37:22.69#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.20:37:22.69#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:22.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.20:37:22.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.20:37:22.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.20:37:22.69#ibcon#enter wrdev, iclass 28, count 0 2006.285.20:37:22.69#ibcon#first serial, iclass 28, count 0 2006.285.20:37:22.69#ibcon#enter sib2, iclass 28, count 0 2006.285.20:37:22.69#ibcon#flushed, iclass 28, count 0 2006.285.20:37:22.69#ibcon#about to write, iclass 28, count 0 2006.285.20:37:22.69#ibcon#wrote, iclass 28, count 0 2006.285.20:37:22.69#ibcon#about to read 3, iclass 28, count 0 2006.285.20:37:22.71#ibcon#read 3, iclass 28, count 0 2006.285.20:37:22.71#ibcon#about to read 4, iclass 28, count 0 2006.285.20:37:22.71#ibcon#read 4, iclass 28, count 0 2006.285.20:37:22.71#ibcon#about to read 5, iclass 28, count 0 2006.285.20:37:22.71#ibcon#read 5, iclass 28, count 0 2006.285.20:37:22.71#ibcon#about to read 6, iclass 28, count 0 2006.285.20:37:22.71#ibcon#read 6, iclass 28, count 0 2006.285.20:37:22.71#ibcon#end of sib2, iclass 28, count 0 2006.285.20:37:22.71#ibcon#*mode == 0, iclass 28, count 0 2006.285.20:37:22.71#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.20:37:22.71#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.20:37:22.71#ibcon#*before write, iclass 28, count 0 2006.285.20:37:22.71#ibcon#enter sib2, iclass 28, count 0 2006.285.20:37:22.71#ibcon#flushed, iclass 28, count 0 2006.285.20:37:22.71#ibcon#about to write, iclass 28, count 0 2006.285.20:37:22.71#ibcon#wrote, iclass 28, count 0 2006.285.20:37:22.71#ibcon#about to read 3, iclass 28, count 0 2006.285.20:37:22.75#ibcon#read 3, iclass 28, count 0 2006.285.20:37:22.75#ibcon#about to read 4, iclass 28, count 0 2006.285.20:37:22.75#ibcon#read 4, iclass 28, count 0 2006.285.20:37:22.75#ibcon#about to read 5, iclass 28, count 0 2006.285.20:37:22.75#ibcon#read 5, iclass 28, count 0 2006.285.20:37:22.75#ibcon#about to read 6, iclass 28, count 0 2006.285.20:37:22.75#ibcon#read 6, iclass 28, count 0 2006.285.20:37:22.75#ibcon#end of sib2, iclass 28, count 0 2006.285.20:37:22.75#ibcon#*after write, iclass 28, count 0 2006.285.20:37:22.75#ibcon#*before return 0, iclass 28, count 0 2006.285.20:37:22.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.20:37:22.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.20:37:22.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.20:37:22.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.20:37:22.75$vck44/vb=1,4 2006.285.20:37:22.75#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.20:37:22.75#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.20:37:22.75#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:22.75#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.20:37:22.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.20:37:22.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.20:37:22.75#ibcon#enter wrdev, iclass 30, count 2 2006.285.20:37:22.75#ibcon#first serial, iclass 30, count 2 2006.285.20:37:22.75#ibcon#enter sib2, iclass 30, count 2 2006.285.20:37:22.75#ibcon#flushed, iclass 30, count 2 2006.285.20:37:22.75#ibcon#about to write, iclass 30, count 2 2006.285.20:37:22.75#ibcon#wrote, iclass 30, count 2 2006.285.20:37:22.75#ibcon#about to read 3, iclass 30, count 2 2006.285.20:37:22.77#ibcon#read 3, iclass 30, count 2 2006.285.20:37:22.77#ibcon#about to read 4, iclass 30, count 2 2006.285.20:37:22.77#ibcon#read 4, iclass 30, count 2 2006.285.20:37:22.77#ibcon#about to read 5, iclass 30, count 2 2006.285.20:37:22.77#ibcon#read 5, iclass 30, count 2 2006.285.20:37:22.77#ibcon#about to read 6, iclass 30, count 2 2006.285.20:37:22.77#ibcon#read 6, iclass 30, count 2 2006.285.20:37:22.77#ibcon#end of sib2, iclass 30, count 2 2006.285.20:37:22.77#ibcon#*mode == 0, iclass 30, count 2 2006.285.20:37:22.77#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.20:37:22.77#ibcon#[27=AT01-04\r\n] 2006.285.20:37:22.77#ibcon#*before write, iclass 30, count 2 2006.285.20:37:22.77#ibcon#enter sib2, iclass 30, count 2 2006.285.20:37:22.77#ibcon#flushed, iclass 30, count 2 2006.285.20:37:22.77#ibcon#about to write, iclass 30, count 2 2006.285.20:37:22.77#ibcon#wrote, iclass 30, count 2 2006.285.20:37:22.77#ibcon#about to read 3, iclass 30, count 2 2006.285.20:37:22.80#ibcon#read 3, iclass 30, count 2 2006.285.20:37:22.80#ibcon#about to read 4, iclass 30, count 2 2006.285.20:37:22.80#ibcon#read 4, iclass 30, count 2 2006.285.20:37:22.80#ibcon#about to read 5, iclass 30, count 2 2006.285.20:37:22.80#ibcon#read 5, iclass 30, count 2 2006.285.20:37:22.80#ibcon#about to read 6, iclass 30, count 2 2006.285.20:37:22.80#ibcon#read 6, iclass 30, count 2 2006.285.20:37:22.80#ibcon#end of sib2, iclass 30, count 2 2006.285.20:37:22.80#ibcon#*after write, iclass 30, count 2 2006.285.20:37:22.80#ibcon#*before return 0, iclass 30, count 2 2006.285.20:37:22.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.20:37:22.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.20:37:22.80#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.20:37:22.80#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:22.80#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.20:37:22.92#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.20:37:22.92#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.20:37:22.92#ibcon#enter wrdev, iclass 30, count 0 2006.285.20:37:22.92#ibcon#first serial, iclass 30, count 0 2006.285.20:37:22.92#ibcon#enter sib2, iclass 30, count 0 2006.285.20:37:22.92#ibcon#flushed, iclass 30, count 0 2006.285.20:37:22.92#ibcon#about to write, iclass 30, count 0 2006.285.20:37:22.92#ibcon#wrote, iclass 30, count 0 2006.285.20:37:22.92#ibcon#about to read 3, iclass 30, count 0 2006.285.20:37:22.94#ibcon#read 3, iclass 30, count 0 2006.285.20:37:22.94#ibcon#about to read 4, iclass 30, count 0 2006.285.20:37:22.94#ibcon#read 4, iclass 30, count 0 2006.285.20:37:22.94#ibcon#about to read 5, iclass 30, count 0 2006.285.20:37:22.94#ibcon#read 5, iclass 30, count 0 2006.285.20:37:22.94#ibcon#about to read 6, iclass 30, count 0 2006.285.20:37:22.94#ibcon#read 6, iclass 30, count 0 2006.285.20:37:22.94#ibcon#end of sib2, iclass 30, count 0 2006.285.20:37:22.94#ibcon#*mode == 0, iclass 30, count 0 2006.285.20:37:22.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.20:37:22.94#ibcon#[27=USB\r\n] 2006.285.20:37:22.94#ibcon#*before write, iclass 30, count 0 2006.285.20:37:22.94#ibcon#enter sib2, iclass 30, count 0 2006.285.20:37:22.94#ibcon#flushed, iclass 30, count 0 2006.285.20:37:22.94#ibcon#about to write, iclass 30, count 0 2006.285.20:37:22.94#ibcon#wrote, iclass 30, count 0 2006.285.20:37:22.94#ibcon#about to read 3, iclass 30, count 0 2006.285.20:37:22.97#ibcon#read 3, iclass 30, count 0 2006.285.20:37:22.97#ibcon#about to read 4, iclass 30, count 0 2006.285.20:37:22.97#ibcon#read 4, iclass 30, count 0 2006.285.20:37:22.97#ibcon#about to read 5, iclass 30, count 0 2006.285.20:37:22.97#ibcon#read 5, iclass 30, count 0 2006.285.20:37:22.97#ibcon#about to read 6, iclass 30, count 0 2006.285.20:37:22.97#ibcon#read 6, iclass 30, count 0 2006.285.20:37:22.97#ibcon#end of sib2, iclass 30, count 0 2006.285.20:37:22.97#ibcon#*after write, iclass 30, count 0 2006.285.20:37:22.97#ibcon#*before return 0, iclass 30, count 0 2006.285.20:37:22.97#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.20:37:22.97#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.20:37:22.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.20:37:22.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.20:37:22.97$vck44/vblo=2,634.99 2006.285.20:37:22.97#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.20:37:22.97#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.20:37:22.97#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:22.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:37:22.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:37:22.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:37:22.97#ibcon#enter wrdev, iclass 32, count 0 2006.285.20:37:22.97#ibcon#first serial, iclass 32, count 0 2006.285.20:37:22.97#ibcon#enter sib2, iclass 32, count 0 2006.285.20:37:22.97#ibcon#flushed, iclass 32, count 0 2006.285.20:37:22.97#ibcon#about to write, iclass 32, count 0 2006.285.20:37:22.97#ibcon#wrote, iclass 32, count 0 2006.285.20:37:22.97#ibcon#about to read 3, iclass 32, count 0 2006.285.20:37:22.99#ibcon#read 3, iclass 32, count 0 2006.285.20:37:22.99#ibcon#about to read 4, iclass 32, count 0 2006.285.20:37:22.99#ibcon#read 4, iclass 32, count 0 2006.285.20:37:22.99#ibcon#about to read 5, iclass 32, count 0 2006.285.20:37:22.99#ibcon#read 5, iclass 32, count 0 2006.285.20:37:22.99#ibcon#about to read 6, iclass 32, count 0 2006.285.20:37:22.99#ibcon#read 6, iclass 32, count 0 2006.285.20:37:22.99#ibcon#end of sib2, iclass 32, count 0 2006.285.20:37:22.99#ibcon#*mode == 0, iclass 32, count 0 2006.285.20:37:22.99#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.20:37:22.99#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.20:37:22.99#ibcon#*before write, iclass 32, count 0 2006.285.20:37:22.99#ibcon#enter sib2, iclass 32, count 0 2006.285.20:37:22.99#ibcon#flushed, iclass 32, count 0 2006.285.20:37:22.99#ibcon#about to write, iclass 32, count 0 2006.285.20:37:22.99#ibcon#wrote, iclass 32, count 0 2006.285.20:37:22.99#ibcon#about to read 3, iclass 32, count 0 2006.285.20:37:23.03#ibcon#read 3, iclass 32, count 0 2006.285.20:37:23.03#ibcon#about to read 4, iclass 32, count 0 2006.285.20:37:23.03#ibcon#read 4, iclass 32, count 0 2006.285.20:37:23.03#ibcon#about to read 5, iclass 32, count 0 2006.285.20:37:23.03#ibcon#read 5, iclass 32, count 0 2006.285.20:37:23.03#ibcon#about to read 6, iclass 32, count 0 2006.285.20:37:23.03#ibcon#read 6, iclass 32, count 0 2006.285.20:37:23.03#ibcon#end of sib2, iclass 32, count 0 2006.285.20:37:23.03#ibcon#*after write, iclass 32, count 0 2006.285.20:37:23.03#ibcon#*before return 0, iclass 32, count 0 2006.285.20:37:23.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:37:23.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.20:37:23.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.20:37:23.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.20:37:23.03$vck44/vb=2,5 2006.285.20:37:23.03#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.20:37:23.03#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.20:37:23.03#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:23.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:37:23.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:37:23.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:37:23.09#ibcon#enter wrdev, iclass 34, count 2 2006.285.20:37:23.09#ibcon#first serial, iclass 34, count 2 2006.285.20:37:23.09#ibcon#enter sib2, iclass 34, count 2 2006.285.20:37:23.09#ibcon#flushed, iclass 34, count 2 2006.285.20:37:23.09#ibcon#about to write, iclass 34, count 2 2006.285.20:37:23.09#ibcon#wrote, iclass 34, count 2 2006.285.20:37:23.09#ibcon#about to read 3, iclass 34, count 2 2006.285.20:37:23.11#ibcon#read 3, iclass 34, count 2 2006.285.20:37:23.11#ibcon#about to read 4, iclass 34, count 2 2006.285.20:37:23.11#ibcon#read 4, iclass 34, count 2 2006.285.20:37:23.11#ibcon#about to read 5, iclass 34, count 2 2006.285.20:37:23.11#ibcon#read 5, iclass 34, count 2 2006.285.20:37:23.11#ibcon#about to read 6, iclass 34, count 2 2006.285.20:37:23.11#ibcon#read 6, iclass 34, count 2 2006.285.20:37:23.11#ibcon#end of sib2, iclass 34, count 2 2006.285.20:37:23.11#ibcon#*mode == 0, iclass 34, count 2 2006.285.20:37:23.11#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.20:37:23.11#ibcon#[27=AT02-05\r\n] 2006.285.20:37:23.11#ibcon#*before write, iclass 34, count 2 2006.285.20:37:23.11#ibcon#enter sib2, iclass 34, count 2 2006.285.20:37:23.11#ibcon#flushed, iclass 34, count 2 2006.285.20:37:23.11#ibcon#about to write, iclass 34, count 2 2006.285.20:37:23.11#ibcon#wrote, iclass 34, count 2 2006.285.20:37:23.11#ibcon#about to read 3, iclass 34, count 2 2006.285.20:37:23.14#ibcon#read 3, iclass 34, count 2 2006.285.20:37:23.14#ibcon#about to read 4, iclass 34, count 2 2006.285.20:37:23.14#ibcon#read 4, iclass 34, count 2 2006.285.20:37:23.14#ibcon#about to read 5, iclass 34, count 2 2006.285.20:37:23.14#ibcon#read 5, iclass 34, count 2 2006.285.20:37:23.14#ibcon#about to read 6, iclass 34, count 2 2006.285.20:37:23.14#ibcon#read 6, iclass 34, count 2 2006.285.20:37:23.14#ibcon#end of sib2, iclass 34, count 2 2006.285.20:37:23.14#ibcon#*after write, iclass 34, count 2 2006.285.20:37:23.14#ibcon#*before return 0, iclass 34, count 2 2006.285.20:37:23.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:37:23.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.20:37:23.14#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.20:37:23.14#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:23.14#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:37:23.26#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:37:23.26#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:37:23.26#ibcon#enter wrdev, iclass 34, count 0 2006.285.20:37:23.26#ibcon#first serial, iclass 34, count 0 2006.285.20:37:23.26#ibcon#enter sib2, iclass 34, count 0 2006.285.20:37:23.26#ibcon#flushed, iclass 34, count 0 2006.285.20:37:23.26#ibcon#about to write, iclass 34, count 0 2006.285.20:37:23.26#ibcon#wrote, iclass 34, count 0 2006.285.20:37:23.26#ibcon#about to read 3, iclass 34, count 0 2006.285.20:37:23.28#ibcon#read 3, iclass 34, count 0 2006.285.20:37:23.28#ibcon#about to read 4, iclass 34, count 0 2006.285.20:37:23.28#ibcon#read 4, iclass 34, count 0 2006.285.20:37:23.28#ibcon#about to read 5, iclass 34, count 0 2006.285.20:37:23.28#ibcon#read 5, iclass 34, count 0 2006.285.20:37:23.28#ibcon#about to read 6, iclass 34, count 0 2006.285.20:37:23.28#ibcon#read 6, iclass 34, count 0 2006.285.20:37:23.28#ibcon#end of sib2, iclass 34, count 0 2006.285.20:37:23.28#ibcon#*mode == 0, iclass 34, count 0 2006.285.20:37:23.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.20:37:23.28#ibcon#[27=USB\r\n] 2006.285.20:37:23.28#ibcon#*before write, iclass 34, count 0 2006.285.20:37:23.28#ibcon#enter sib2, iclass 34, count 0 2006.285.20:37:23.28#ibcon#flushed, iclass 34, count 0 2006.285.20:37:23.28#ibcon#about to write, iclass 34, count 0 2006.285.20:37:23.28#ibcon#wrote, iclass 34, count 0 2006.285.20:37:23.28#ibcon#about to read 3, iclass 34, count 0 2006.285.20:37:23.31#ibcon#read 3, iclass 34, count 0 2006.285.20:37:23.31#ibcon#about to read 4, iclass 34, count 0 2006.285.20:37:23.31#ibcon#read 4, iclass 34, count 0 2006.285.20:37:23.31#ibcon#about to read 5, iclass 34, count 0 2006.285.20:37:23.31#ibcon#read 5, iclass 34, count 0 2006.285.20:37:23.31#ibcon#about to read 6, iclass 34, count 0 2006.285.20:37:23.31#ibcon#read 6, iclass 34, count 0 2006.285.20:37:23.31#ibcon#end of sib2, iclass 34, count 0 2006.285.20:37:23.31#ibcon#*after write, iclass 34, count 0 2006.285.20:37:23.31#ibcon#*before return 0, iclass 34, count 0 2006.285.20:37:23.31#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:37:23.31#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.20:37:23.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.20:37:23.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.20:37:23.31$vck44/vblo=3,649.99 2006.285.20:37:23.31#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.20:37:23.31#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.20:37:23.31#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:23.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:37:23.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:37:23.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:37:23.31#ibcon#enter wrdev, iclass 36, count 0 2006.285.20:37:23.31#ibcon#first serial, iclass 36, count 0 2006.285.20:37:23.31#ibcon#enter sib2, iclass 36, count 0 2006.285.20:37:23.31#ibcon#flushed, iclass 36, count 0 2006.285.20:37:23.31#ibcon#about to write, iclass 36, count 0 2006.285.20:37:23.31#ibcon#wrote, iclass 36, count 0 2006.285.20:37:23.31#ibcon#about to read 3, iclass 36, count 0 2006.285.20:37:23.33#ibcon#read 3, iclass 36, count 0 2006.285.20:37:23.45#ibcon#about to read 4, iclass 36, count 0 2006.285.20:37:23.45#ibcon#read 4, iclass 36, count 0 2006.285.20:37:23.45#ibcon#about to read 5, iclass 36, count 0 2006.285.20:37:23.45#ibcon#read 5, iclass 36, count 0 2006.285.20:37:23.45#ibcon#about to read 6, iclass 36, count 0 2006.285.20:37:23.45#ibcon#read 6, iclass 36, count 0 2006.285.20:37:23.45#ibcon#end of sib2, iclass 36, count 0 2006.285.20:37:23.45#ibcon#*mode == 0, iclass 36, count 0 2006.285.20:37:23.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.20:37:23.45#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.20:37:23.45#ibcon#*before write, iclass 36, count 0 2006.285.20:37:23.45#ibcon#enter sib2, iclass 36, count 0 2006.285.20:37:23.45#ibcon#flushed, iclass 36, count 0 2006.285.20:37:23.45#ibcon#about to write, iclass 36, count 0 2006.285.20:37:23.45#ibcon#wrote, iclass 36, count 0 2006.285.20:37:23.45#ibcon#about to read 3, iclass 36, count 0 2006.285.20:37:23.50#ibcon#read 3, iclass 36, count 0 2006.285.20:37:23.50#ibcon#about to read 4, iclass 36, count 0 2006.285.20:37:23.50#ibcon#read 4, iclass 36, count 0 2006.285.20:37:23.50#ibcon#about to read 5, iclass 36, count 0 2006.285.20:37:23.50#ibcon#read 5, iclass 36, count 0 2006.285.20:37:23.50#ibcon#about to read 6, iclass 36, count 0 2006.285.20:37:23.50#ibcon#read 6, iclass 36, count 0 2006.285.20:37:23.50#ibcon#end of sib2, iclass 36, count 0 2006.285.20:37:23.50#ibcon#*after write, iclass 36, count 0 2006.285.20:37:23.50#ibcon#*before return 0, iclass 36, count 0 2006.285.20:37:23.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:37:23.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.20:37:23.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.20:37:23.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.20:37:23.50$vck44/vb=3,4 2006.285.20:37:23.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.20:37:23.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.20:37:23.50#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:23.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:37:23.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:37:23.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:37:23.50#ibcon#enter wrdev, iclass 38, count 2 2006.285.20:37:23.50#ibcon#first serial, iclass 38, count 2 2006.285.20:37:23.50#ibcon#enter sib2, iclass 38, count 2 2006.285.20:37:23.50#ibcon#flushed, iclass 38, count 2 2006.285.20:37:23.50#ibcon#about to write, iclass 38, count 2 2006.285.20:37:23.50#ibcon#wrote, iclass 38, count 2 2006.285.20:37:23.50#ibcon#about to read 3, iclass 38, count 2 2006.285.20:37:23.52#ibcon#read 3, iclass 38, count 2 2006.285.20:37:23.52#ibcon#about to read 4, iclass 38, count 2 2006.285.20:37:23.52#ibcon#read 4, iclass 38, count 2 2006.285.20:37:23.52#ibcon#about to read 5, iclass 38, count 2 2006.285.20:37:23.52#ibcon#read 5, iclass 38, count 2 2006.285.20:37:23.52#ibcon#about to read 6, iclass 38, count 2 2006.285.20:37:23.52#ibcon#read 6, iclass 38, count 2 2006.285.20:37:23.52#ibcon#end of sib2, iclass 38, count 2 2006.285.20:37:23.52#ibcon#*mode == 0, iclass 38, count 2 2006.285.20:37:23.52#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.20:37:23.52#ibcon#[27=AT03-04\r\n] 2006.285.20:37:23.52#ibcon#*before write, iclass 38, count 2 2006.285.20:37:23.52#ibcon#enter sib2, iclass 38, count 2 2006.285.20:37:23.52#ibcon#flushed, iclass 38, count 2 2006.285.20:37:23.52#ibcon#about to write, iclass 38, count 2 2006.285.20:37:23.52#ibcon#wrote, iclass 38, count 2 2006.285.20:37:23.52#ibcon#about to read 3, iclass 38, count 2 2006.285.20:37:23.55#ibcon#read 3, iclass 38, count 2 2006.285.20:37:23.55#ibcon#about to read 4, iclass 38, count 2 2006.285.20:37:23.55#ibcon#read 4, iclass 38, count 2 2006.285.20:37:23.55#ibcon#about to read 5, iclass 38, count 2 2006.285.20:37:23.55#ibcon#read 5, iclass 38, count 2 2006.285.20:37:23.55#ibcon#about to read 6, iclass 38, count 2 2006.285.20:37:23.55#ibcon#read 6, iclass 38, count 2 2006.285.20:37:23.55#ibcon#end of sib2, iclass 38, count 2 2006.285.20:37:23.55#ibcon#*after write, iclass 38, count 2 2006.285.20:37:23.55#ibcon#*before return 0, iclass 38, count 2 2006.285.20:37:23.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:37:23.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.20:37:23.55#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.20:37:23.55#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:23.55#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:37:23.67#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:37:23.67#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:37:23.67#ibcon#enter wrdev, iclass 38, count 0 2006.285.20:37:23.67#ibcon#first serial, iclass 38, count 0 2006.285.20:37:23.67#ibcon#enter sib2, iclass 38, count 0 2006.285.20:37:23.67#ibcon#flushed, iclass 38, count 0 2006.285.20:37:23.67#ibcon#about to write, iclass 38, count 0 2006.285.20:37:23.67#ibcon#wrote, iclass 38, count 0 2006.285.20:37:23.67#ibcon#about to read 3, iclass 38, count 0 2006.285.20:37:23.69#ibcon#read 3, iclass 38, count 0 2006.285.20:37:23.69#ibcon#about to read 4, iclass 38, count 0 2006.285.20:37:23.69#ibcon#read 4, iclass 38, count 0 2006.285.20:37:23.69#ibcon#about to read 5, iclass 38, count 0 2006.285.20:37:23.69#ibcon#read 5, iclass 38, count 0 2006.285.20:37:23.69#ibcon#about to read 6, iclass 38, count 0 2006.285.20:37:23.69#ibcon#read 6, iclass 38, count 0 2006.285.20:37:23.69#ibcon#end of sib2, iclass 38, count 0 2006.285.20:37:23.69#ibcon#*mode == 0, iclass 38, count 0 2006.285.20:37:23.69#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.20:37:23.69#ibcon#[27=USB\r\n] 2006.285.20:37:23.69#ibcon#*before write, iclass 38, count 0 2006.285.20:37:23.69#ibcon#enter sib2, iclass 38, count 0 2006.285.20:37:23.69#ibcon#flushed, iclass 38, count 0 2006.285.20:37:23.69#ibcon#about to write, iclass 38, count 0 2006.285.20:37:23.69#ibcon#wrote, iclass 38, count 0 2006.285.20:37:23.69#ibcon#about to read 3, iclass 38, count 0 2006.285.20:37:23.72#ibcon#read 3, iclass 38, count 0 2006.285.20:37:23.72#ibcon#about to read 4, iclass 38, count 0 2006.285.20:37:23.72#ibcon#read 4, iclass 38, count 0 2006.285.20:37:23.72#ibcon#about to read 5, iclass 38, count 0 2006.285.20:37:23.72#ibcon#read 5, iclass 38, count 0 2006.285.20:37:23.72#ibcon#about to read 6, iclass 38, count 0 2006.285.20:37:23.72#ibcon#read 6, iclass 38, count 0 2006.285.20:37:23.72#ibcon#end of sib2, iclass 38, count 0 2006.285.20:37:23.72#ibcon#*after write, iclass 38, count 0 2006.285.20:37:23.72#ibcon#*before return 0, iclass 38, count 0 2006.285.20:37:23.72#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:37:23.72#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.20:37:23.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.20:37:23.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.20:37:23.72$vck44/vblo=4,679.99 2006.285.20:37:23.72#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.20:37:23.72#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.20:37:23.72#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:23.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:37:23.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:37:23.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:37:23.72#ibcon#enter wrdev, iclass 40, count 0 2006.285.20:37:23.72#ibcon#first serial, iclass 40, count 0 2006.285.20:37:23.72#ibcon#enter sib2, iclass 40, count 0 2006.285.20:37:23.72#ibcon#flushed, iclass 40, count 0 2006.285.20:37:23.72#ibcon#about to write, iclass 40, count 0 2006.285.20:37:23.72#ibcon#wrote, iclass 40, count 0 2006.285.20:37:23.72#ibcon#about to read 3, iclass 40, count 0 2006.285.20:37:23.74#ibcon#read 3, iclass 40, count 0 2006.285.20:37:23.74#ibcon#about to read 4, iclass 40, count 0 2006.285.20:37:23.74#ibcon#read 4, iclass 40, count 0 2006.285.20:37:23.74#ibcon#about to read 5, iclass 40, count 0 2006.285.20:37:23.74#ibcon#read 5, iclass 40, count 0 2006.285.20:37:23.74#ibcon#about to read 6, iclass 40, count 0 2006.285.20:37:23.74#ibcon#read 6, iclass 40, count 0 2006.285.20:37:23.74#ibcon#end of sib2, iclass 40, count 0 2006.285.20:37:23.74#ibcon#*mode == 0, iclass 40, count 0 2006.285.20:37:23.74#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.20:37:23.74#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.20:37:23.74#ibcon#*before write, iclass 40, count 0 2006.285.20:37:23.74#ibcon#enter sib2, iclass 40, count 0 2006.285.20:37:23.74#ibcon#flushed, iclass 40, count 0 2006.285.20:37:23.74#ibcon#about to write, iclass 40, count 0 2006.285.20:37:23.74#ibcon#wrote, iclass 40, count 0 2006.285.20:37:23.74#ibcon#about to read 3, iclass 40, count 0 2006.285.20:37:23.78#ibcon#read 3, iclass 40, count 0 2006.285.20:37:23.78#ibcon#about to read 4, iclass 40, count 0 2006.285.20:37:23.78#ibcon#read 4, iclass 40, count 0 2006.285.20:37:23.78#ibcon#about to read 5, iclass 40, count 0 2006.285.20:37:23.78#ibcon#read 5, iclass 40, count 0 2006.285.20:37:23.78#ibcon#about to read 6, iclass 40, count 0 2006.285.20:37:23.78#ibcon#read 6, iclass 40, count 0 2006.285.20:37:23.78#ibcon#end of sib2, iclass 40, count 0 2006.285.20:37:23.78#ibcon#*after write, iclass 40, count 0 2006.285.20:37:23.78#ibcon#*before return 0, iclass 40, count 0 2006.285.20:37:23.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:37:23.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.20:37:23.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.20:37:23.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.20:37:23.78$vck44/vb=4,5 2006.285.20:37:23.78#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.20:37:23.78#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.20:37:23.78#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:23.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:37:23.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:37:23.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:37:23.84#ibcon#enter wrdev, iclass 4, count 2 2006.285.20:37:23.84#ibcon#first serial, iclass 4, count 2 2006.285.20:37:23.84#ibcon#enter sib2, iclass 4, count 2 2006.285.20:37:23.84#ibcon#flushed, iclass 4, count 2 2006.285.20:37:23.84#ibcon#about to write, iclass 4, count 2 2006.285.20:37:23.84#ibcon#wrote, iclass 4, count 2 2006.285.20:37:23.84#ibcon#about to read 3, iclass 4, count 2 2006.285.20:37:23.86#ibcon#read 3, iclass 4, count 2 2006.285.20:37:23.86#ibcon#about to read 4, iclass 4, count 2 2006.285.20:37:23.86#ibcon#read 4, iclass 4, count 2 2006.285.20:37:23.86#ibcon#about to read 5, iclass 4, count 2 2006.285.20:37:23.86#ibcon#read 5, iclass 4, count 2 2006.285.20:37:23.86#ibcon#about to read 6, iclass 4, count 2 2006.285.20:37:23.86#ibcon#read 6, iclass 4, count 2 2006.285.20:37:23.86#ibcon#end of sib2, iclass 4, count 2 2006.285.20:37:23.86#ibcon#*mode == 0, iclass 4, count 2 2006.285.20:37:23.86#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.20:37:23.86#ibcon#[27=AT04-05\r\n] 2006.285.20:37:23.86#ibcon#*before write, iclass 4, count 2 2006.285.20:37:23.86#ibcon#enter sib2, iclass 4, count 2 2006.285.20:37:23.86#ibcon#flushed, iclass 4, count 2 2006.285.20:37:23.86#ibcon#about to write, iclass 4, count 2 2006.285.20:37:23.86#ibcon#wrote, iclass 4, count 2 2006.285.20:37:23.86#ibcon#about to read 3, iclass 4, count 2 2006.285.20:37:23.89#ibcon#read 3, iclass 4, count 2 2006.285.20:37:23.89#ibcon#about to read 4, iclass 4, count 2 2006.285.20:37:23.89#ibcon#read 4, iclass 4, count 2 2006.285.20:37:23.89#ibcon#about to read 5, iclass 4, count 2 2006.285.20:37:23.89#ibcon#read 5, iclass 4, count 2 2006.285.20:37:23.89#ibcon#about to read 6, iclass 4, count 2 2006.285.20:37:23.89#ibcon#read 6, iclass 4, count 2 2006.285.20:37:23.89#ibcon#end of sib2, iclass 4, count 2 2006.285.20:37:23.89#ibcon#*after write, iclass 4, count 2 2006.285.20:37:23.89#ibcon#*before return 0, iclass 4, count 2 2006.285.20:37:23.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:37:23.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.20:37:23.89#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.20:37:23.89#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:23.89#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:37:24.01#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:37:24.01#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:37:24.01#ibcon#enter wrdev, iclass 4, count 0 2006.285.20:37:24.01#ibcon#first serial, iclass 4, count 0 2006.285.20:37:24.01#ibcon#enter sib2, iclass 4, count 0 2006.285.20:37:24.01#ibcon#flushed, iclass 4, count 0 2006.285.20:37:24.01#ibcon#about to write, iclass 4, count 0 2006.285.20:37:24.01#ibcon#wrote, iclass 4, count 0 2006.285.20:37:24.01#ibcon#about to read 3, iclass 4, count 0 2006.285.20:37:24.03#ibcon#read 3, iclass 4, count 0 2006.285.20:37:24.03#ibcon#about to read 4, iclass 4, count 0 2006.285.20:37:24.03#ibcon#read 4, iclass 4, count 0 2006.285.20:37:24.03#ibcon#about to read 5, iclass 4, count 0 2006.285.20:37:24.03#ibcon#read 5, iclass 4, count 0 2006.285.20:37:24.03#ibcon#about to read 6, iclass 4, count 0 2006.285.20:37:24.03#ibcon#read 6, iclass 4, count 0 2006.285.20:37:24.03#ibcon#end of sib2, iclass 4, count 0 2006.285.20:37:24.03#ibcon#*mode == 0, iclass 4, count 0 2006.285.20:37:24.03#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.20:37:24.03#ibcon#[27=USB\r\n] 2006.285.20:37:24.03#ibcon#*before write, iclass 4, count 0 2006.285.20:37:24.03#ibcon#enter sib2, iclass 4, count 0 2006.285.20:37:24.03#ibcon#flushed, iclass 4, count 0 2006.285.20:37:24.03#ibcon#about to write, iclass 4, count 0 2006.285.20:37:24.03#ibcon#wrote, iclass 4, count 0 2006.285.20:37:24.03#ibcon#about to read 3, iclass 4, count 0 2006.285.20:37:24.06#ibcon#read 3, iclass 4, count 0 2006.285.20:37:24.06#ibcon#about to read 4, iclass 4, count 0 2006.285.20:37:24.06#ibcon#read 4, iclass 4, count 0 2006.285.20:37:24.06#ibcon#about to read 5, iclass 4, count 0 2006.285.20:37:24.06#ibcon#read 5, iclass 4, count 0 2006.285.20:37:24.06#ibcon#about to read 6, iclass 4, count 0 2006.285.20:37:24.06#ibcon#read 6, iclass 4, count 0 2006.285.20:37:24.06#ibcon#end of sib2, iclass 4, count 0 2006.285.20:37:24.06#ibcon#*after write, iclass 4, count 0 2006.285.20:37:24.06#ibcon#*before return 0, iclass 4, count 0 2006.285.20:37:24.06#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:37:24.06#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.20:37:24.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.20:37:24.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.20:37:24.06$vck44/vblo=5,709.99 2006.285.20:37:24.06#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.20:37:24.06#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.20:37:24.06#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:24.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:37:24.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:37:24.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:37:24.06#ibcon#enter wrdev, iclass 6, count 0 2006.285.20:37:24.06#ibcon#first serial, iclass 6, count 0 2006.285.20:37:24.06#ibcon#enter sib2, iclass 6, count 0 2006.285.20:37:24.06#ibcon#flushed, iclass 6, count 0 2006.285.20:37:24.06#ibcon#about to write, iclass 6, count 0 2006.285.20:37:24.06#ibcon#wrote, iclass 6, count 0 2006.285.20:37:24.06#ibcon#about to read 3, iclass 6, count 0 2006.285.20:37:24.08#ibcon#read 3, iclass 6, count 0 2006.285.20:37:24.08#ibcon#about to read 4, iclass 6, count 0 2006.285.20:37:24.08#ibcon#read 4, iclass 6, count 0 2006.285.20:37:24.08#ibcon#about to read 5, iclass 6, count 0 2006.285.20:37:24.08#ibcon#read 5, iclass 6, count 0 2006.285.20:37:24.08#ibcon#about to read 6, iclass 6, count 0 2006.285.20:37:24.08#ibcon#read 6, iclass 6, count 0 2006.285.20:37:24.08#ibcon#end of sib2, iclass 6, count 0 2006.285.20:37:24.08#ibcon#*mode == 0, iclass 6, count 0 2006.285.20:37:24.08#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.20:37:24.08#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.20:37:24.08#ibcon#*before write, iclass 6, count 0 2006.285.20:37:24.08#ibcon#enter sib2, iclass 6, count 0 2006.285.20:37:24.08#ibcon#flushed, iclass 6, count 0 2006.285.20:37:24.08#ibcon#about to write, iclass 6, count 0 2006.285.20:37:24.08#ibcon#wrote, iclass 6, count 0 2006.285.20:37:24.08#ibcon#about to read 3, iclass 6, count 0 2006.285.20:37:24.12#ibcon#read 3, iclass 6, count 0 2006.285.20:37:24.12#ibcon#about to read 4, iclass 6, count 0 2006.285.20:37:24.12#ibcon#read 4, iclass 6, count 0 2006.285.20:37:24.12#ibcon#about to read 5, iclass 6, count 0 2006.285.20:37:24.12#ibcon#read 5, iclass 6, count 0 2006.285.20:37:24.12#ibcon#about to read 6, iclass 6, count 0 2006.285.20:37:24.12#ibcon#read 6, iclass 6, count 0 2006.285.20:37:24.12#ibcon#end of sib2, iclass 6, count 0 2006.285.20:37:24.12#ibcon#*after write, iclass 6, count 0 2006.285.20:37:24.12#ibcon#*before return 0, iclass 6, count 0 2006.285.20:37:24.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:37:24.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.20:37:24.12#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.20:37:24.12#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.20:37:24.12$vck44/vb=5,4 2006.285.20:37:24.12#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.20:37:24.12#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.20:37:24.12#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:24.12#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:37:24.18#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:37:24.18#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:37:24.18#ibcon#enter wrdev, iclass 10, count 2 2006.285.20:37:24.18#ibcon#first serial, iclass 10, count 2 2006.285.20:37:24.18#ibcon#enter sib2, iclass 10, count 2 2006.285.20:37:24.18#ibcon#flushed, iclass 10, count 2 2006.285.20:37:24.18#ibcon#about to write, iclass 10, count 2 2006.285.20:37:24.18#ibcon#wrote, iclass 10, count 2 2006.285.20:37:24.18#ibcon#about to read 3, iclass 10, count 2 2006.285.20:37:24.20#ibcon#read 3, iclass 10, count 2 2006.285.20:37:24.20#ibcon#about to read 4, iclass 10, count 2 2006.285.20:37:24.20#ibcon#read 4, iclass 10, count 2 2006.285.20:37:24.20#ibcon#about to read 5, iclass 10, count 2 2006.285.20:37:24.20#ibcon#read 5, iclass 10, count 2 2006.285.20:37:24.20#ibcon#about to read 6, iclass 10, count 2 2006.285.20:37:24.20#ibcon#read 6, iclass 10, count 2 2006.285.20:37:24.20#ibcon#end of sib2, iclass 10, count 2 2006.285.20:37:24.20#ibcon#*mode == 0, iclass 10, count 2 2006.285.20:37:24.20#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.20:37:24.20#ibcon#[27=AT05-04\r\n] 2006.285.20:37:24.20#ibcon#*before write, iclass 10, count 2 2006.285.20:37:24.20#ibcon#enter sib2, iclass 10, count 2 2006.285.20:37:24.20#ibcon#flushed, iclass 10, count 2 2006.285.20:37:24.20#ibcon#about to write, iclass 10, count 2 2006.285.20:37:24.20#ibcon#wrote, iclass 10, count 2 2006.285.20:37:24.20#ibcon#about to read 3, iclass 10, count 2 2006.285.20:37:24.23#ibcon#read 3, iclass 10, count 2 2006.285.20:37:24.23#ibcon#about to read 4, iclass 10, count 2 2006.285.20:37:24.23#ibcon#read 4, iclass 10, count 2 2006.285.20:37:24.23#ibcon#about to read 5, iclass 10, count 2 2006.285.20:37:24.23#ibcon#read 5, iclass 10, count 2 2006.285.20:37:24.23#ibcon#about to read 6, iclass 10, count 2 2006.285.20:37:24.23#ibcon#read 6, iclass 10, count 2 2006.285.20:37:24.23#ibcon#end of sib2, iclass 10, count 2 2006.285.20:37:24.23#ibcon#*after write, iclass 10, count 2 2006.285.20:37:24.23#ibcon#*before return 0, iclass 10, count 2 2006.285.20:37:24.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:37:24.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.20:37:24.23#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.20:37:24.23#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:24.23#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:37:24.35#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:37:24.35#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:37:24.35#ibcon#enter wrdev, iclass 10, count 0 2006.285.20:37:24.35#ibcon#first serial, iclass 10, count 0 2006.285.20:37:24.35#ibcon#enter sib2, iclass 10, count 0 2006.285.20:37:24.35#ibcon#flushed, iclass 10, count 0 2006.285.20:37:24.35#ibcon#about to write, iclass 10, count 0 2006.285.20:37:24.35#ibcon#wrote, iclass 10, count 0 2006.285.20:37:24.35#ibcon#about to read 3, iclass 10, count 0 2006.285.20:37:24.37#ibcon#read 3, iclass 10, count 0 2006.285.20:37:24.37#ibcon#about to read 4, iclass 10, count 0 2006.285.20:37:24.37#ibcon#read 4, iclass 10, count 0 2006.285.20:37:24.37#ibcon#about to read 5, iclass 10, count 0 2006.285.20:37:24.37#ibcon#read 5, iclass 10, count 0 2006.285.20:37:24.37#ibcon#about to read 6, iclass 10, count 0 2006.285.20:37:24.37#ibcon#read 6, iclass 10, count 0 2006.285.20:37:24.37#ibcon#end of sib2, iclass 10, count 0 2006.285.20:37:24.37#ibcon#*mode == 0, iclass 10, count 0 2006.285.20:37:24.37#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.20:37:24.37#ibcon#[27=USB\r\n] 2006.285.20:37:24.37#ibcon#*before write, iclass 10, count 0 2006.285.20:37:24.37#ibcon#enter sib2, iclass 10, count 0 2006.285.20:37:24.37#ibcon#flushed, iclass 10, count 0 2006.285.20:37:24.37#ibcon#about to write, iclass 10, count 0 2006.285.20:37:24.37#ibcon#wrote, iclass 10, count 0 2006.285.20:37:24.37#ibcon#about to read 3, iclass 10, count 0 2006.285.20:37:24.40#ibcon#read 3, iclass 10, count 0 2006.285.20:37:24.40#ibcon#about to read 4, iclass 10, count 0 2006.285.20:37:24.40#ibcon#read 4, iclass 10, count 0 2006.285.20:37:24.40#ibcon#about to read 5, iclass 10, count 0 2006.285.20:37:24.40#ibcon#read 5, iclass 10, count 0 2006.285.20:37:24.40#ibcon#about to read 6, iclass 10, count 0 2006.285.20:37:24.40#ibcon#read 6, iclass 10, count 0 2006.285.20:37:24.40#ibcon#end of sib2, iclass 10, count 0 2006.285.20:37:24.40#ibcon#*after write, iclass 10, count 0 2006.285.20:37:24.40#ibcon#*before return 0, iclass 10, count 0 2006.285.20:37:24.40#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:37:24.40#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.20:37:24.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.20:37:24.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.20:37:24.40$vck44/vblo=6,719.99 2006.285.20:37:24.40#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.20:37:24.40#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.20:37:24.40#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:24.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:37:24.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:37:24.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:37:24.40#ibcon#enter wrdev, iclass 12, count 0 2006.285.20:37:24.40#ibcon#first serial, iclass 12, count 0 2006.285.20:37:24.40#ibcon#enter sib2, iclass 12, count 0 2006.285.20:37:24.40#ibcon#flushed, iclass 12, count 0 2006.285.20:37:24.40#ibcon#about to write, iclass 12, count 0 2006.285.20:37:24.40#ibcon#wrote, iclass 12, count 0 2006.285.20:37:24.40#ibcon#about to read 3, iclass 12, count 0 2006.285.20:37:24.42#ibcon#read 3, iclass 12, count 0 2006.285.20:37:24.53#ibcon#about to read 4, iclass 12, count 0 2006.285.20:37:24.53#ibcon#read 4, iclass 12, count 0 2006.285.20:37:24.53#ibcon#about to read 5, iclass 12, count 0 2006.285.20:37:24.53#ibcon#read 5, iclass 12, count 0 2006.285.20:37:24.53#ibcon#about to read 6, iclass 12, count 0 2006.285.20:37:24.53#ibcon#read 6, iclass 12, count 0 2006.285.20:37:24.53#ibcon#end of sib2, iclass 12, count 0 2006.285.20:37:24.53#ibcon#*mode == 0, iclass 12, count 0 2006.285.20:37:24.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.20:37:24.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.20:37:24.53#ibcon#*before write, iclass 12, count 0 2006.285.20:37:24.53#ibcon#enter sib2, iclass 12, count 0 2006.285.20:37:24.53#ibcon#flushed, iclass 12, count 0 2006.285.20:37:24.53#ibcon#about to write, iclass 12, count 0 2006.285.20:37:24.53#ibcon#wrote, iclass 12, count 0 2006.285.20:37:24.53#ibcon#about to read 3, iclass 12, count 0 2006.285.20:37:24.57#ibcon#read 3, iclass 12, count 0 2006.285.20:37:24.57#ibcon#about to read 4, iclass 12, count 0 2006.285.20:37:24.57#ibcon#read 4, iclass 12, count 0 2006.285.20:37:24.57#ibcon#about to read 5, iclass 12, count 0 2006.285.20:37:24.57#ibcon#read 5, iclass 12, count 0 2006.285.20:37:24.57#ibcon#about to read 6, iclass 12, count 0 2006.285.20:37:24.57#ibcon#read 6, iclass 12, count 0 2006.285.20:37:24.57#ibcon#end of sib2, iclass 12, count 0 2006.285.20:37:24.57#ibcon#*after write, iclass 12, count 0 2006.285.20:37:24.57#ibcon#*before return 0, iclass 12, count 0 2006.285.20:37:24.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:37:24.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:37:24.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.20:37:24.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.20:37:24.57$vck44/vb=6,3 2006.285.20:37:24.57#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.20:37:24.57#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.20:37:24.57#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:24.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:37:24.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:37:24.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:37:24.57#ibcon#enter wrdev, iclass 14, count 2 2006.285.20:37:24.57#ibcon#first serial, iclass 14, count 2 2006.285.20:37:24.57#ibcon#enter sib2, iclass 14, count 2 2006.285.20:37:24.57#ibcon#flushed, iclass 14, count 2 2006.285.20:37:24.57#ibcon#about to write, iclass 14, count 2 2006.285.20:37:24.57#ibcon#wrote, iclass 14, count 2 2006.285.20:37:24.57#ibcon#about to read 3, iclass 14, count 2 2006.285.20:37:24.59#ibcon#read 3, iclass 14, count 2 2006.285.20:37:24.59#ibcon#about to read 4, iclass 14, count 2 2006.285.20:37:24.59#ibcon#read 4, iclass 14, count 2 2006.285.20:37:24.59#ibcon#about to read 5, iclass 14, count 2 2006.285.20:37:24.59#ibcon#read 5, iclass 14, count 2 2006.285.20:37:24.59#ibcon#about to read 6, iclass 14, count 2 2006.285.20:37:24.59#ibcon#read 6, iclass 14, count 2 2006.285.20:37:24.59#ibcon#end of sib2, iclass 14, count 2 2006.285.20:37:24.59#ibcon#*mode == 0, iclass 14, count 2 2006.285.20:37:24.59#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.20:37:24.59#ibcon#[27=AT06-03\r\n] 2006.285.20:37:24.59#ibcon#*before write, iclass 14, count 2 2006.285.20:37:24.59#ibcon#enter sib2, iclass 14, count 2 2006.285.20:37:24.59#ibcon#flushed, iclass 14, count 2 2006.285.20:37:24.59#ibcon#about to write, iclass 14, count 2 2006.285.20:37:24.59#ibcon#wrote, iclass 14, count 2 2006.285.20:37:24.59#ibcon#about to read 3, iclass 14, count 2 2006.285.20:37:24.62#ibcon#read 3, iclass 14, count 2 2006.285.20:37:24.62#ibcon#about to read 4, iclass 14, count 2 2006.285.20:37:24.62#ibcon#read 4, iclass 14, count 2 2006.285.20:37:24.62#ibcon#about to read 5, iclass 14, count 2 2006.285.20:37:24.62#ibcon#read 5, iclass 14, count 2 2006.285.20:37:24.62#ibcon#about to read 6, iclass 14, count 2 2006.285.20:37:24.62#ibcon#read 6, iclass 14, count 2 2006.285.20:37:24.62#ibcon#end of sib2, iclass 14, count 2 2006.285.20:37:24.62#ibcon#*after write, iclass 14, count 2 2006.285.20:37:24.62#ibcon#*before return 0, iclass 14, count 2 2006.285.20:37:24.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:37:24.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.20:37:24.62#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.20:37:24.62#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:24.62#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:37:24.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:37:24.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:37:24.74#ibcon#enter wrdev, iclass 14, count 0 2006.285.20:37:24.74#ibcon#first serial, iclass 14, count 0 2006.285.20:37:24.74#ibcon#enter sib2, iclass 14, count 0 2006.285.20:37:24.74#ibcon#flushed, iclass 14, count 0 2006.285.20:37:24.74#ibcon#about to write, iclass 14, count 0 2006.285.20:37:24.74#ibcon#wrote, iclass 14, count 0 2006.285.20:37:24.74#ibcon#about to read 3, iclass 14, count 0 2006.285.20:37:24.76#ibcon#read 3, iclass 14, count 0 2006.285.20:37:24.76#ibcon#about to read 4, iclass 14, count 0 2006.285.20:37:24.76#ibcon#read 4, iclass 14, count 0 2006.285.20:37:24.76#ibcon#about to read 5, iclass 14, count 0 2006.285.20:37:24.76#ibcon#read 5, iclass 14, count 0 2006.285.20:37:24.76#ibcon#about to read 6, iclass 14, count 0 2006.285.20:37:24.76#ibcon#read 6, iclass 14, count 0 2006.285.20:37:24.76#ibcon#end of sib2, iclass 14, count 0 2006.285.20:37:24.76#ibcon#*mode == 0, iclass 14, count 0 2006.285.20:37:24.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.20:37:24.76#ibcon#[27=USB\r\n] 2006.285.20:37:24.76#ibcon#*before write, iclass 14, count 0 2006.285.20:37:24.76#ibcon#enter sib2, iclass 14, count 0 2006.285.20:37:24.76#ibcon#flushed, iclass 14, count 0 2006.285.20:37:24.76#ibcon#about to write, iclass 14, count 0 2006.285.20:37:24.76#ibcon#wrote, iclass 14, count 0 2006.285.20:37:24.76#ibcon#about to read 3, iclass 14, count 0 2006.285.20:37:24.79#ibcon#read 3, iclass 14, count 0 2006.285.20:37:24.79#ibcon#about to read 4, iclass 14, count 0 2006.285.20:37:24.79#ibcon#read 4, iclass 14, count 0 2006.285.20:37:24.79#ibcon#about to read 5, iclass 14, count 0 2006.285.20:37:24.79#ibcon#read 5, iclass 14, count 0 2006.285.20:37:24.79#ibcon#about to read 6, iclass 14, count 0 2006.285.20:37:24.79#ibcon#read 6, iclass 14, count 0 2006.285.20:37:24.79#ibcon#end of sib2, iclass 14, count 0 2006.285.20:37:24.79#ibcon#*after write, iclass 14, count 0 2006.285.20:37:24.79#ibcon#*before return 0, iclass 14, count 0 2006.285.20:37:24.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:37:24.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.20:37:24.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.20:37:24.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.20:37:24.79$vck44/vblo=7,734.99 2006.285.20:37:24.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.20:37:24.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.20:37:24.79#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:24.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:37:24.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:37:24.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:37:24.79#ibcon#enter wrdev, iclass 16, count 0 2006.285.20:37:24.79#ibcon#first serial, iclass 16, count 0 2006.285.20:37:24.79#ibcon#enter sib2, iclass 16, count 0 2006.285.20:37:24.79#ibcon#flushed, iclass 16, count 0 2006.285.20:37:24.79#ibcon#about to write, iclass 16, count 0 2006.285.20:37:24.79#ibcon#wrote, iclass 16, count 0 2006.285.20:37:24.79#ibcon#about to read 3, iclass 16, count 0 2006.285.20:37:24.81#ibcon#read 3, iclass 16, count 0 2006.285.20:37:24.81#ibcon#about to read 4, iclass 16, count 0 2006.285.20:37:24.81#ibcon#read 4, iclass 16, count 0 2006.285.20:37:24.81#ibcon#about to read 5, iclass 16, count 0 2006.285.20:37:24.81#ibcon#read 5, iclass 16, count 0 2006.285.20:37:24.81#ibcon#about to read 6, iclass 16, count 0 2006.285.20:37:24.81#ibcon#read 6, iclass 16, count 0 2006.285.20:37:24.81#ibcon#end of sib2, iclass 16, count 0 2006.285.20:37:24.81#ibcon#*mode == 0, iclass 16, count 0 2006.285.20:37:24.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.20:37:24.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.20:37:24.81#ibcon#*before write, iclass 16, count 0 2006.285.20:37:24.81#ibcon#enter sib2, iclass 16, count 0 2006.285.20:37:24.81#ibcon#flushed, iclass 16, count 0 2006.285.20:37:24.81#ibcon#about to write, iclass 16, count 0 2006.285.20:37:24.81#ibcon#wrote, iclass 16, count 0 2006.285.20:37:24.81#ibcon#about to read 3, iclass 16, count 0 2006.285.20:37:24.85#ibcon#read 3, iclass 16, count 0 2006.285.20:37:24.85#ibcon#about to read 4, iclass 16, count 0 2006.285.20:37:24.85#ibcon#read 4, iclass 16, count 0 2006.285.20:37:24.85#ibcon#about to read 5, iclass 16, count 0 2006.285.20:37:24.85#ibcon#read 5, iclass 16, count 0 2006.285.20:37:24.85#ibcon#about to read 6, iclass 16, count 0 2006.285.20:37:24.85#ibcon#read 6, iclass 16, count 0 2006.285.20:37:24.85#ibcon#end of sib2, iclass 16, count 0 2006.285.20:37:24.85#ibcon#*after write, iclass 16, count 0 2006.285.20:37:24.85#ibcon#*before return 0, iclass 16, count 0 2006.285.20:37:24.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:37:24.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.20:37:24.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.20:37:24.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.20:37:24.85$vck44/vb=7,4 2006.285.20:37:24.85#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.20:37:24.85#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.20:37:24.85#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:24.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:37:24.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:37:24.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:37:24.91#ibcon#enter wrdev, iclass 18, count 2 2006.285.20:37:24.91#ibcon#first serial, iclass 18, count 2 2006.285.20:37:24.91#ibcon#enter sib2, iclass 18, count 2 2006.285.20:37:24.91#ibcon#flushed, iclass 18, count 2 2006.285.20:37:24.91#ibcon#about to write, iclass 18, count 2 2006.285.20:37:24.91#ibcon#wrote, iclass 18, count 2 2006.285.20:37:24.91#ibcon#about to read 3, iclass 18, count 2 2006.285.20:37:24.93#ibcon#read 3, iclass 18, count 2 2006.285.20:37:24.93#ibcon#about to read 4, iclass 18, count 2 2006.285.20:37:24.93#ibcon#read 4, iclass 18, count 2 2006.285.20:37:24.93#ibcon#about to read 5, iclass 18, count 2 2006.285.20:37:24.93#ibcon#read 5, iclass 18, count 2 2006.285.20:37:24.93#ibcon#about to read 6, iclass 18, count 2 2006.285.20:37:24.93#ibcon#read 6, iclass 18, count 2 2006.285.20:37:24.93#ibcon#end of sib2, iclass 18, count 2 2006.285.20:37:24.93#ibcon#*mode == 0, iclass 18, count 2 2006.285.20:37:24.93#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.20:37:24.93#ibcon#[27=AT07-04\r\n] 2006.285.20:37:24.93#ibcon#*before write, iclass 18, count 2 2006.285.20:37:24.93#ibcon#enter sib2, iclass 18, count 2 2006.285.20:37:24.93#ibcon#flushed, iclass 18, count 2 2006.285.20:37:24.93#ibcon#about to write, iclass 18, count 2 2006.285.20:37:24.93#ibcon#wrote, iclass 18, count 2 2006.285.20:37:24.93#ibcon#about to read 3, iclass 18, count 2 2006.285.20:37:24.96#ibcon#read 3, iclass 18, count 2 2006.285.20:37:24.96#ibcon#about to read 4, iclass 18, count 2 2006.285.20:37:24.96#ibcon#read 4, iclass 18, count 2 2006.285.20:37:24.96#ibcon#about to read 5, iclass 18, count 2 2006.285.20:37:24.96#ibcon#read 5, iclass 18, count 2 2006.285.20:37:24.96#ibcon#about to read 6, iclass 18, count 2 2006.285.20:37:24.96#ibcon#read 6, iclass 18, count 2 2006.285.20:37:24.96#ibcon#end of sib2, iclass 18, count 2 2006.285.20:37:24.96#ibcon#*after write, iclass 18, count 2 2006.285.20:37:24.96#ibcon#*before return 0, iclass 18, count 2 2006.285.20:37:24.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:37:24.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.20:37:24.96#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.20:37:24.96#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:24.96#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:37:25.08#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:37:25.08#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:37:25.08#ibcon#enter wrdev, iclass 18, count 0 2006.285.20:37:25.08#ibcon#first serial, iclass 18, count 0 2006.285.20:37:25.08#ibcon#enter sib2, iclass 18, count 0 2006.285.20:37:25.08#ibcon#flushed, iclass 18, count 0 2006.285.20:37:25.08#ibcon#about to write, iclass 18, count 0 2006.285.20:37:25.08#ibcon#wrote, iclass 18, count 0 2006.285.20:37:25.08#ibcon#about to read 3, iclass 18, count 0 2006.285.20:37:25.10#ibcon#read 3, iclass 18, count 0 2006.285.20:37:25.10#ibcon#about to read 4, iclass 18, count 0 2006.285.20:37:25.10#ibcon#read 4, iclass 18, count 0 2006.285.20:37:25.10#ibcon#about to read 5, iclass 18, count 0 2006.285.20:37:25.10#ibcon#read 5, iclass 18, count 0 2006.285.20:37:25.10#ibcon#about to read 6, iclass 18, count 0 2006.285.20:37:25.10#ibcon#read 6, iclass 18, count 0 2006.285.20:37:25.10#ibcon#end of sib2, iclass 18, count 0 2006.285.20:37:25.10#ibcon#*mode == 0, iclass 18, count 0 2006.285.20:37:25.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.20:37:25.10#ibcon#[27=USB\r\n] 2006.285.20:37:25.10#ibcon#*before write, iclass 18, count 0 2006.285.20:37:25.10#ibcon#enter sib2, iclass 18, count 0 2006.285.20:37:25.10#ibcon#flushed, iclass 18, count 0 2006.285.20:37:25.10#ibcon#about to write, iclass 18, count 0 2006.285.20:37:25.10#ibcon#wrote, iclass 18, count 0 2006.285.20:37:25.10#ibcon#about to read 3, iclass 18, count 0 2006.285.20:37:25.13#ibcon#read 3, iclass 18, count 0 2006.285.20:37:25.13#ibcon#about to read 4, iclass 18, count 0 2006.285.20:37:25.13#ibcon#read 4, iclass 18, count 0 2006.285.20:37:25.13#ibcon#about to read 5, iclass 18, count 0 2006.285.20:37:25.13#ibcon#read 5, iclass 18, count 0 2006.285.20:37:25.13#ibcon#about to read 6, iclass 18, count 0 2006.285.20:37:25.13#ibcon#read 6, iclass 18, count 0 2006.285.20:37:25.13#ibcon#end of sib2, iclass 18, count 0 2006.285.20:37:25.13#ibcon#*after write, iclass 18, count 0 2006.285.20:37:25.13#ibcon#*before return 0, iclass 18, count 0 2006.285.20:37:25.13#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:37:25.13#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.20:37:25.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.20:37:25.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.20:37:25.13$vck44/vblo=8,744.99 2006.285.20:37:25.13#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.20:37:25.13#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.20:37:25.13#ibcon#ireg 17 cls_cnt 0 2006.285.20:37:25.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:37:25.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:37:25.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:37:25.13#ibcon#enter wrdev, iclass 20, count 0 2006.285.20:37:25.13#ibcon#first serial, iclass 20, count 0 2006.285.20:37:25.13#ibcon#enter sib2, iclass 20, count 0 2006.285.20:37:25.13#ibcon#flushed, iclass 20, count 0 2006.285.20:37:25.13#ibcon#about to write, iclass 20, count 0 2006.285.20:37:25.13#ibcon#wrote, iclass 20, count 0 2006.285.20:37:25.13#ibcon#about to read 3, iclass 20, count 0 2006.285.20:37:25.15#ibcon#read 3, iclass 20, count 0 2006.285.20:37:25.15#ibcon#about to read 4, iclass 20, count 0 2006.285.20:37:25.15#ibcon#read 4, iclass 20, count 0 2006.285.20:37:25.15#ibcon#about to read 5, iclass 20, count 0 2006.285.20:37:25.15#ibcon#read 5, iclass 20, count 0 2006.285.20:37:25.15#ibcon#about to read 6, iclass 20, count 0 2006.285.20:37:25.15#ibcon#read 6, iclass 20, count 0 2006.285.20:37:25.15#ibcon#end of sib2, iclass 20, count 0 2006.285.20:37:25.15#ibcon#*mode == 0, iclass 20, count 0 2006.285.20:37:25.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.20:37:25.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.20:37:25.15#ibcon#*before write, iclass 20, count 0 2006.285.20:37:25.15#ibcon#enter sib2, iclass 20, count 0 2006.285.20:37:25.15#ibcon#flushed, iclass 20, count 0 2006.285.20:37:25.15#ibcon#about to write, iclass 20, count 0 2006.285.20:37:25.15#ibcon#wrote, iclass 20, count 0 2006.285.20:37:25.15#ibcon#about to read 3, iclass 20, count 0 2006.285.20:37:25.19#ibcon#read 3, iclass 20, count 0 2006.285.20:37:25.19#ibcon#about to read 4, iclass 20, count 0 2006.285.20:37:25.19#ibcon#read 4, iclass 20, count 0 2006.285.20:37:25.19#ibcon#about to read 5, iclass 20, count 0 2006.285.20:37:25.19#ibcon#read 5, iclass 20, count 0 2006.285.20:37:25.19#ibcon#about to read 6, iclass 20, count 0 2006.285.20:37:25.19#ibcon#read 6, iclass 20, count 0 2006.285.20:37:25.19#ibcon#end of sib2, iclass 20, count 0 2006.285.20:37:25.19#ibcon#*after write, iclass 20, count 0 2006.285.20:37:25.19#ibcon#*before return 0, iclass 20, count 0 2006.285.20:37:25.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:37:25.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.20:37:25.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.20:37:25.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.20:37:25.19$vck44/vb=8,4 2006.285.20:37:25.19#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.20:37:25.19#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.20:37:25.19#ibcon#ireg 11 cls_cnt 2 2006.285.20:37:25.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:37:25.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:37:25.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:37:25.25#ibcon#enter wrdev, iclass 22, count 2 2006.285.20:37:25.25#ibcon#first serial, iclass 22, count 2 2006.285.20:37:25.25#ibcon#enter sib2, iclass 22, count 2 2006.285.20:37:25.25#ibcon#flushed, iclass 22, count 2 2006.285.20:37:25.25#ibcon#about to write, iclass 22, count 2 2006.285.20:37:25.25#ibcon#wrote, iclass 22, count 2 2006.285.20:37:25.25#ibcon#about to read 3, iclass 22, count 2 2006.285.20:37:25.27#ibcon#read 3, iclass 22, count 2 2006.285.20:37:25.27#ibcon#about to read 4, iclass 22, count 2 2006.285.20:37:25.27#ibcon#read 4, iclass 22, count 2 2006.285.20:37:25.27#ibcon#about to read 5, iclass 22, count 2 2006.285.20:37:25.27#ibcon#read 5, iclass 22, count 2 2006.285.20:37:25.27#ibcon#about to read 6, iclass 22, count 2 2006.285.20:37:25.27#ibcon#read 6, iclass 22, count 2 2006.285.20:37:25.27#ibcon#end of sib2, iclass 22, count 2 2006.285.20:37:25.27#ibcon#*mode == 0, iclass 22, count 2 2006.285.20:37:25.27#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.20:37:25.27#ibcon#[27=AT08-04\r\n] 2006.285.20:37:25.27#ibcon#*before write, iclass 22, count 2 2006.285.20:37:25.27#ibcon#enter sib2, iclass 22, count 2 2006.285.20:37:25.27#ibcon#flushed, iclass 22, count 2 2006.285.20:37:25.27#ibcon#about to write, iclass 22, count 2 2006.285.20:37:25.27#ibcon#wrote, iclass 22, count 2 2006.285.20:37:25.27#ibcon#about to read 3, iclass 22, count 2 2006.285.20:37:25.30#ibcon#read 3, iclass 22, count 2 2006.285.20:37:25.30#ibcon#about to read 4, iclass 22, count 2 2006.285.20:37:25.30#ibcon#read 4, iclass 22, count 2 2006.285.20:37:25.30#ibcon#about to read 5, iclass 22, count 2 2006.285.20:37:25.30#ibcon#read 5, iclass 22, count 2 2006.285.20:37:25.30#ibcon#about to read 6, iclass 22, count 2 2006.285.20:37:25.30#ibcon#read 6, iclass 22, count 2 2006.285.20:37:25.30#ibcon#end of sib2, iclass 22, count 2 2006.285.20:37:25.30#ibcon#*after write, iclass 22, count 2 2006.285.20:37:25.30#ibcon#*before return 0, iclass 22, count 2 2006.285.20:37:25.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:37:25.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.20:37:25.30#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.20:37:25.30#ibcon#ireg 7 cls_cnt 0 2006.285.20:37:25.30#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:37:25.42#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:37:25.42#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:37:25.42#ibcon#enter wrdev, iclass 22, count 0 2006.285.20:37:25.42#ibcon#first serial, iclass 22, count 0 2006.285.20:37:25.42#ibcon#enter sib2, iclass 22, count 0 2006.285.20:37:25.42#ibcon#flushed, iclass 22, count 0 2006.285.20:37:25.42#ibcon#about to write, iclass 22, count 0 2006.285.20:37:25.42#ibcon#wrote, iclass 22, count 0 2006.285.20:37:25.42#ibcon#about to read 3, iclass 22, count 0 2006.285.20:37:25.44#ibcon#read 3, iclass 22, count 0 2006.285.20:37:25.44#ibcon#about to read 4, iclass 22, count 0 2006.285.20:37:25.44#ibcon#read 4, iclass 22, count 0 2006.285.20:37:25.44#ibcon#about to read 5, iclass 22, count 0 2006.285.20:37:25.44#ibcon#read 5, iclass 22, count 0 2006.285.20:37:25.44#ibcon#about to read 6, iclass 22, count 0 2006.285.20:37:25.44#ibcon#read 6, iclass 22, count 0 2006.285.20:37:25.44#ibcon#end of sib2, iclass 22, count 0 2006.285.20:37:25.44#ibcon#*mode == 0, iclass 22, count 0 2006.285.20:37:25.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.20:37:25.44#ibcon#[27=USB\r\n] 2006.285.20:37:25.44#ibcon#*before write, iclass 22, count 0 2006.285.20:37:25.44#ibcon#enter sib2, iclass 22, count 0 2006.285.20:37:25.44#ibcon#flushed, iclass 22, count 0 2006.285.20:37:25.44#ibcon#about to write, iclass 22, count 0 2006.285.20:37:25.44#ibcon#wrote, iclass 22, count 0 2006.285.20:37:25.44#ibcon#about to read 3, iclass 22, count 0 2006.285.20:37:25.47#ibcon#read 3, iclass 22, count 0 2006.285.20:37:25.47#ibcon#about to read 4, iclass 22, count 0 2006.285.20:37:25.47#ibcon#read 4, iclass 22, count 0 2006.285.20:37:25.47#ibcon#about to read 5, iclass 22, count 0 2006.285.20:37:25.47#ibcon#read 5, iclass 22, count 0 2006.285.20:37:25.47#ibcon#about to read 6, iclass 22, count 0 2006.285.20:37:25.47#ibcon#read 6, iclass 22, count 0 2006.285.20:37:25.47#ibcon#end of sib2, iclass 22, count 0 2006.285.20:37:25.47#ibcon#*after write, iclass 22, count 0 2006.285.20:37:25.47#ibcon#*before return 0, iclass 22, count 0 2006.285.20:37:25.47#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:37:25.47#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.20:37:25.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.20:37:25.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.20:37:25.47$vck44/vabw=wide 2006.285.20:37:25.47#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.20:37:25.47#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.20:37:25.47#ibcon#ireg 8 cls_cnt 0 2006.285.20:37:25.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:37:25.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:37:25.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:37:25.47#ibcon#enter wrdev, iclass 24, count 0 2006.285.20:37:25.47#ibcon#first serial, iclass 24, count 0 2006.285.20:37:25.47#ibcon#enter sib2, iclass 24, count 0 2006.285.20:37:25.47#ibcon#flushed, iclass 24, count 0 2006.285.20:37:25.47#ibcon#about to write, iclass 24, count 0 2006.285.20:37:25.47#ibcon#wrote, iclass 24, count 0 2006.285.20:37:25.47#ibcon#about to read 3, iclass 24, count 0 2006.285.20:37:25.49#ibcon#read 3, iclass 24, count 0 2006.285.20:37:25.49#ibcon#about to read 4, iclass 24, count 0 2006.285.20:37:25.49#ibcon#read 4, iclass 24, count 0 2006.285.20:37:25.49#ibcon#about to read 5, iclass 24, count 0 2006.285.20:37:25.49#ibcon#read 5, iclass 24, count 0 2006.285.20:37:25.49#ibcon#about to read 6, iclass 24, count 0 2006.285.20:37:25.49#ibcon#read 6, iclass 24, count 0 2006.285.20:37:25.49#ibcon#end of sib2, iclass 24, count 0 2006.285.20:37:25.49#ibcon#*mode == 0, iclass 24, count 0 2006.285.20:37:25.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.20:37:25.49#ibcon#[25=BW32\r\n] 2006.285.20:37:25.49#ibcon#*before write, iclass 24, count 0 2006.285.20:37:25.49#ibcon#enter sib2, iclass 24, count 0 2006.285.20:37:25.49#ibcon#flushed, iclass 24, count 0 2006.285.20:37:25.49#ibcon#about to write, iclass 24, count 0 2006.285.20:37:25.49#ibcon#wrote, iclass 24, count 0 2006.285.20:37:25.49#ibcon#about to read 3, iclass 24, count 0 2006.285.20:37:25.52#ibcon#read 3, iclass 24, count 0 2006.285.20:37:25.52#ibcon#about to read 4, iclass 24, count 0 2006.285.20:37:25.52#ibcon#read 4, iclass 24, count 0 2006.285.20:37:25.52#ibcon#about to read 5, iclass 24, count 0 2006.285.20:37:25.52#ibcon#read 5, iclass 24, count 0 2006.285.20:37:25.52#ibcon#about to read 6, iclass 24, count 0 2006.285.20:37:25.52#ibcon#read 6, iclass 24, count 0 2006.285.20:37:25.52#ibcon#end of sib2, iclass 24, count 0 2006.285.20:37:25.52#ibcon#*after write, iclass 24, count 0 2006.285.20:37:25.52#ibcon#*before return 0, iclass 24, count 0 2006.285.20:37:25.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:37:25.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.20:37:25.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.20:37:25.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.20:37:25.52$vck44/vbbw=wide 2006.285.20:37:25.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.20:37:25.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.20:37:25.52#ibcon#ireg 8 cls_cnt 0 2006.285.20:37:25.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:37:25.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:37:25.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:37:25.59#ibcon#enter wrdev, iclass 26, count 0 2006.285.20:37:25.59#ibcon#first serial, iclass 26, count 0 2006.285.20:37:25.59#ibcon#enter sib2, iclass 26, count 0 2006.285.20:37:25.59#ibcon#flushed, iclass 26, count 0 2006.285.20:37:25.59#ibcon#about to write, iclass 26, count 0 2006.285.20:37:25.59#ibcon#wrote, iclass 26, count 0 2006.285.20:37:25.59#ibcon#about to read 3, iclass 26, count 0 2006.285.20:37:25.61#ibcon#read 3, iclass 26, count 0 2006.285.20:37:25.61#ibcon#about to read 4, iclass 26, count 0 2006.285.20:37:25.61#ibcon#read 4, iclass 26, count 0 2006.285.20:37:25.61#ibcon#about to read 5, iclass 26, count 0 2006.285.20:37:25.61#ibcon#read 5, iclass 26, count 0 2006.285.20:37:25.61#ibcon#about to read 6, iclass 26, count 0 2006.285.20:37:25.61#ibcon#read 6, iclass 26, count 0 2006.285.20:37:25.61#ibcon#end of sib2, iclass 26, count 0 2006.285.20:37:25.61#ibcon#*mode == 0, iclass 26, count 0 2006.285.20:37:25.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.20:37:25.61#ibcon#[27=BW32\r\n] 2006.285.20:37:25.61#ibcon#*before write, iclass 26, count 0 2006.285.20:37:25.61#ibcon#enter sib2, iclass 26, count 0 2006.285.20:37:25.61#ibcon#flushed, iclass 26, count 0 2006.285.20:37:25.61#ibcon#about to write, iclass 26, count 0 2006.285.20:37:25.61#ibcon#wrote, iclass 26, count 0 2006.285.20:37:25.61#ibcon#about to read 3, iclass 26, count 0 2006.285.20:37:25.64#ibcon#read 3, iclass 26, count 0 2006.285.20:37:25.64#ibcon#about to read 4, iclass 26, count 0 2006.285.20:37:25.64#ibcon#read 4, iclass 26, count 0 2006.285.20:37:25.64#ibcon#about to read 5, iclass 26, count 0 2006.285.20:37:25.64#ibcon#read 5, iclass 26, count 0 2006.285.20:37:25.64#ibcon#about to read 6, iclass 26, count 0 2006.285.20:37:25.64#ibcon#read 6, iclass 26, count 0 2006.285.20:37:25.64#ibcon#end of sib2, iclass 26, count 0 2006.285.20:37:25.64#ibcon#*after write, iclass 26, count 0 2006.285.20:37:25.64#ibcon#*before return 0, iclass 26, count 0 2006.285.20:37:25.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:37:25.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:37:25.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.20:37:25.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.20:37:25.64$setupk4/ifdk4 2006.285.20:37:25.64$ifdk4/lo= 2006.285.20:37:25.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.20:37:25.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.20:37:25.64$ifdk4/patch= 2006.285.20:37:25.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.20:37:25.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.20:37:25.64$setupk4/!*+20s 2006.285.20:37:26.93#abcon#<5=/12 0.3 0.8 14.261001015.4\r\n> 2006.285.20:37:26.95#abcon#{5=INTERFACE CLEAR} 2006.285.20:37:27.01#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:37:37.10#abcon#<5=/12 0.3 0.8 14.261001015.4\r\n> 2006.285.20:37:37.12#abcon#{5=INTERFACE CLEAR} 2006.285.20:37:37.18#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:37:39.51$setupk4/"tpicd 2006.285.20:37:39.51$setupk4/echo=off 2006.285.20:37:39.51$setupk4/xlog=off 2006.285.20:37:39.51:!2006.285.20:40:54 2006.285.20:38:06.14#trakl#Source acquired 2006.285.20:38:08.14#flagr#flagr/antenna,acquired 2006.285.20:40:54.00:preob 2006.285.20:40:54.14/onsource/TRACKING 2006.285.20:40:54.14:!2006.285.20:41:04 2006.285.20:41:04.00:"tape 2006.285.20:41:04.00:"st=record 2006.285.20:41:04.00:data_valid=on 2006.285.20:41:04.00:midob 2006.285.20:41:05.14/onsource/TRACKING 2006.285.20:41:05.14/wx/14.22,1015.4,100 2006.285.20:41:05.24/cable/+6.5112E-03 2006.285.20:41:06.33/va/01,07,usb,yes,32,35 2006.285.20:41:06.33/va/02,06,usb,yes,32,33 2006.285.20:41:06.33/va/03,07,usb,yes,32,34 2006.285.20:41:06.33/va/04,06,usb,yes,33,35 2006.285.20:41:06.33/va/05,03,usb,yes,33,33 2006.285.20:41:06.33/va/06,04,usb,yes,30,29 2006.285.20:41:06.33/va/07,04,usb,yes,30,31 2006.285.20:41:06.33/va/08,03,usb,yes,31,37 2006.285.20:41:06.56/valo/01,524.99,yes,locked 2006.285.20:41:06.56/valo/02,534.99,yes,locked 2006.285.20:41:06.56/valo/03,564.99,yes,locked 2006.285.20:41:06.56/valo/04,624.99,yes,locked 2006.285.20:41:06.56/valo/05,734.99,yes,locked 2006.285.20:41:06.56/valo/06,814.99,yes,locked 2006.285.20:41:06.56/valo/07,864.99,yes,locked 2006.285.20:41:06.56/valo/08,884.99,yes,locked 2006.285.20:41:07.65/vb/01,04,usb,yes,29,27 2006.285.20:41:07.65/vb/02,05,usb,yes,28,28 2006.285.20:41:07.65/vb/03,04,usb,yes,29,32 2006.285.20:41:07.65/vb/04,05,usb,yes,29,28 2006.285.20:41:07.65/vb/05,04,usb,yes,25,28 2006.285.20:41:07.65/vb/06,03,usb,yes,37,32 2006.285.20:41:07.65/vb/07,04,usb,yes,29,29 2006.285.20:41:07.65/vb/08,04,usb,yes,27,30 2006.285.20:41:07.88/vblo/01,629.99,yes,locked 2006.285.20:41:07.88/vblo/02,634.99,yes,locked 2006.285.20:41:07.88/vblo/03,649.99,yes,locked 2006.285.20:41:07.88/vblo/04,679.99,yes,locked 2006.285.20:41:07.88/vblo/05,709.99,yes,locked 2006.285.20:41:07.88/vblo/06,719.99,yes,locked 2006.285.20:41:07.88/vblo/07,734.99,yes,locked 2006.285.20:41:07.88/vblo/08,744.99,yes,locked 2006.285.20:41:08.03/vabw/8 2006.285.20:41:08.18/vbbw/8 2006.285.20:41:08.27/xfe/off,on,12.0 2006.285.20:41:08.65/ifatt/23,28,28,28 2006.285.20:41:09.08/fmout-gps/S +2.82E-07 2006.285.20:41:09.09:!2006.285.20:42:44 2006.285.20:42:44.02:data_valid=off 2006.285.20:42:44.02:"et 2006.285.20:42:44.02:!+3s 2006.285.20:42:47.04:"tape 2006.285.20:42:47.05:postob 2006.285.20:42:47.19/cable/+6.5101E-03 2006.285.20:42:47.19/wx/14.22,1015.4,100 2006.285.20:42:47.24/fmout-gps/S +2.87E-07 2006.285.20:42:47.25:scan_name=285-2044,jd0610,60 2006.285.20:42:47.25:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.285.20:42:49.14#flagr#flagr/antenna,new-source 2006.285.20:42:49.14:checkk5 2006.285.20:42:49.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.20:42:49.99/chk_autoobs//k5ts2/ autoobs is running! 2006.285.20:42:50.36/chk_autoobs//k5ts3/ autoobs is running! 2006.285.20:42:50.82/chk_autoobs//k5ts4/ autoobs is running! 2006.285.20:42:51.21/chk_obsdata//k5ts1/T2852041??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.20:42:51.69/chk_obsdata//k5ts2/T2852041??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.20:42:52.08/chk_obsdata//k5ts3/T2852041??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.20:42:52.42/chk_obsdata//k5ts4/T2852041??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.20:42:53.36/k5log//k5ts1_log_newline 2006.285.20:42:54.16/k5log//k5ts2_log_newline 2006.285.20:42:54.93/k5log//k5ts3_log_newline 2006.285.20:42:55.70/k5log//k5ts4_log_newline 2006.285.20:42:55.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.20:42:55.73:setupk4=1 2006.285.20:42:55.73$setupk4/echo=on 2006.285.20:42:55.73$setupk4/pcalon 2006.285.20:42:55.73$pcalon/"no phase cal control is implemented here 2006.285.20:42:55.73$setupk4/"tpicd=stop 2006.285.20:42:55.73$setupk4/"rec=synch_on 2006.285.20:42:55.73$setupk4/"rec_mode=128 2006.285.20:42:55.73$setupk4/!* 2006.285.20:42:55.73$setupk4/recpk4 2006.285.20:42:55.73$recpk4/recpatch= 2006.285.20:42:55.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.20:42:55.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.20:42:55.73$setupk4/vck44 2006.285.20:42:55.73$vck44/valo=1,524.99 2006.285.20:42:55.73#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.20:42:55.73#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.20:42:55.73#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:55.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:42:55.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:42:55.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:42:55.73#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:42:55.73#ibcon#first serial, iclass 19, count 0 2006.285.20:42:55.73#ibcon#enter sib2, iclass 19, count 0 2006.285.20:42:55.73#ibcon#flushed, iclass 19, count 0 2006.285.20:42:55.73#ibcon#about to write, iclass 19, count 0 2006.285.20:42:55.73#ibcon#wrote, iclass 19, count 0 2006.285.20:42:55.73#ibcon#about to read 3, iclass 19, count 0 2006.285.20:42:55.74#ibcon#read 3, iclass 19, count 0 2006.285.20:42:55.74#ibcon#about to read 4, iclass 19, count 0 2006.285.20:42:55.74#ibcon#read 4, iclass 19, count 0 2006.285.20:42:55.74#ibcon#about to read 5, iclass 19, count 0 2006.285.20:42:55.74#ibcon#read 5, iclass 19, count 0 2006.285.20:42:55.74#ibcon#about to read 6, iclass 19, count 0 2006.285.20:42:55.74#ibcon#read 6, iclass 19, count 0 2006.285.20:42:55.74#ibcon#end of sib2, iclass 19, count 0 2006.285.20:42:55.74#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:42:55.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:42:55.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.20:42:55.74#ibcon#*before write, iclass 19, count 0 2006.285.20:42:55.74#ibcon#enter sib2, iclass 19, count 0 2006.285.20:42:55.74#ibcon#flushed, iclass 19, count 0 2006.285.20:42:55.74#ibcon#about to write, iclass 19, count 0 2006.285.20:42:55.74#ibcon#wrote, iclass 19, count 0 2006.285.20:42:55.74#ibcon#about to read 3, iclass 19, count 0 2006.285.20:42:55.79#ibcon#read 3, iclass 19, count 0 2006.285.20:42:55.79#ibcon#about to read 4, iclass 19, count 0 2006.285.20:42:55.79#ibcon#read 4, iclass 19, count 0 2006.285.20:42:55.79#ibcon#about to read 5, iclass 19, count 0 2006.285.20:42:55.79#ibcon#read 5, iclass 19, count 0 2006.285.20:42:55.79#ibcon#about to read 6, iclass 19, count 0 2006.285.20:42:55.79#ibcon#read 6, iclass 19, count 0 2006.285.20:42:55.79#ibcon#end of sib2, iclass 19, count 0 2006.285.20:42:55.79#ibcon#*after write, iclass 19, count 0 2006.285.20:42:55.79#ibcon#*before return 0, iclass 19, count 0 2006.285.20:42:55.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:42:55.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:42:55.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:42:55.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:42:55.80$vck44/va=1,7 2006.285.20:42:55.80#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.20:42:55.80#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.20:42:55.80#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:55.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:42:55.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:42:55.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:42:55.80#ibcon#enter wrdev, iclass 21, count 2 2006.285.20:42:55.80#ibcon#first serial, iclass 21, count 2 2006.285.20:42:55.80#ibcon#enter sib2, iclass 21, count 2 2006.285.20:42:55.80#ibcon#flushed, iclass 21, count 2 2006.285.20:42:55.80#ibcon#about to write, iclass 21, count 2 2006.285.20:42:55.80#ibcon#wrote, iclass 21, count 2 2006.285.20:42:55.80#ibcon#about to read 3, iclass 21, count 2 2006.285.20:42:55.81#ibcon#read 3, iclass 21, count 2 2006.285.20:42:55.81#ibcon#about to read 4, iclass 21, count 2 2006.285.20:42:55.81#ibcon#read 4, iclass 21, count 2 2006.285.20:42:55.81#ibcon#about to read 5, iclass 21, count 2 2006.285.20:42:55.81#ibcon#read 5, iclass 21, count 2 2006.285.20:42:55.81#ibcon#about to read 6, iclass 21, count 2 2006.285.20:42:55.81#ibcon#read 6, iclass 21, count 2 2006.285.20:42:55.81#ibcon#end of sib2, iclass 21, count 2 2006.285.20:42:55.81#ibcon#*mode == 0, iclass 21, count 2 2006.285.20:42:55.81#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.20:42:55.81#ibcon#[25=AT01-07\r\n] 2006.285.20:42:55.81#ibcon#*before write, iclass 21, count 2 2006.285.20:42:55.81#ibcon#enter sib2, iclass 21, count 2 2006.285.20:42:55.81#ibcon#flushed, iclass 21, count 2 2006.285.20:42:55.81#ibcon#about to write, iclass 21, count 2 2006.285.20:42:55.81#ibcon#wrote, iclass 21, count 2 2006.285.20:42:55.81#ibcon#about to read 3, iclass 21, count 2 2006.285.20:42:55.84#ibcon#read 3, iclass 21, count 2 2006.285.20:42:55.84#ibcon#about to read 4, iclass 21, count 2 2006.285.20:42:55.84#ibcon#read 4, iclass 21, count 2 2006.285.20:42:55.84#ibcon#about to read 5, iclass 21, count 2 2006.285.20:42:55.84#ibcon#read 5, iclass 21, count 2 2006.285.20:42:55.84#ibcon#about to read 6, iclass 21, count 2 2006.285.20:42:55.84#ibcon#read 6, iclass 21, count 2 2006.285.20:42:55.84#ibcon#end of sib2, iclass 21, count 2 2006.285.20:42:55.84#ibcon#*after write, iclass 21, count 2 2006.285.20:42:55.84#ibcon#*before return 0, iclass 21, count 2 2006.285.20:42:55.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:42:55.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:42:55.84#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.20:42:55.84#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:55.84#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:42:55.96#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:42:55.96#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:42:55.96#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:42:55.96#ibcon#first serial, iclass 21, count 0 2006.285.20:42:55.96#ibcon#enter sib2, iclass 21, count 0 2006.285.20:42:55.96#ibcon#flushed, iclass 21, count 0 2006.285.20:42:55.96#ibcon#about to write, iclass 21, count 0 2006.285.20:42:55.96#ibcon#wrote, iclass 21, count 0 2006.285.20:42:55.96#ibcon#about to read 3, iclass 21, count 0 2006.285.20:42:55.98#ibcon#read 3, iclass 21, count 0 2006.285.20:42:55.98#ibcon#about to read 4, iclass 21, count 0 2006.285.20:42:55.98#ibcon#read 4, iclass 21, count 0 2006.285.20:42:55.98#ibcon#about to read 5, iclass 21, count 0 2006.285.20:42:55.98#ibcon#read 5, iclass 21, count 0 2006.285.20:42:55.98#ibcon#about to read 6, iclass 21, count 0 2006.285.20:42:55.98#ibcon#read 6, iclass 21, count 0 2006.285.20:42:55.98#ibcon#end of sib2, iclass 21, count 0 2006.285.20:42:55.98#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:42:55.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:42:55.98#ibcon#[25=USB\r\n] 2006.285.20:42:55.98#ibcon#*before write, iclass 21, count 0 2006.285.20:42:55.98#ibcon#enter sib2, iclass 21, count 0 2006.285.20:42:55.98#ibcon#flushed, iclass 21, count 0 2006.285.20:42:55.98#ibcon#about to write, iclass 21, count 0 2006.285.20:42:55.98#ibcon#wrote, iclass 21, count 0 2006.285.20:42:55.98#ibcon#about to read 3, iclass 21, count 0 2006.285.20:42:56.01#ibcon#read 3, iclass 21, count 0 2006.285.20:42:56.01#ibcon#about to read 4, iclass 21, count 0 2006.285.20:42:56.01#ibcon#read 4, iclass 21, count 0 2006.285.20:42:56.01#ibcon#about to read 5, iclass 21, count 0 2006.285.20:42:56.01#ibcon#read 5, iclass 21, count 0 2006.285.20:42:56.01#ibcon#about to read 6, iclass 21, count 0 2006.285.20:42:56.01#ibcon#read 6, iclass 21, count 0 2006.285.20:42:56.01#ibcon#end of sib2, iclass 21, count 0 2006.285.20:42:56.01#ibcon#*after write, iclass 21, count 0 2006.285.20:42:56.01#ibcon#*before return 0, iclass 21, count 0 2006.285.20:42:56.01#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:42:56.01#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:42:56.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:42:56.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:42:56.02$vck44/valo=2,534.99 2006.285.20:42:56.02#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.20:42:56.02#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.20:42:56.02#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:56.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:42:56.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:42:56.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:42:56.02#ibcon#enter wrdev, iclass 23, count 0 2006.285.20:42:56.02#ibcon#first serial, iclass 23, count 0 2006.285.20:42:56.02#ibcon#enter sib2, iclass 23, count 0 2006.285.20:42:56.02#ibcon#flushed, iclass 23, count 0 2006.285.20:42:56.02#ibcon#about to write, iclass 23, count 0 2006.285.20:42:56.02#ibcon#wrote, iclass 23, count 0 2006.285.20:42:56.02#ibcon#about to read 3, iclass 23, count 0 2006.285.20:42:56.03#ibcon#read 3, iclass 23, count 0 2006.285.20:42:56.03#ibcon#about to read 4, iclass 23, count 0 2006.285.20:42:56.03#ibcon#read 4, iclass 23, count 0 2006.285.20:42:56.03#ibcon#about to read 5, iclass 23, count 0 2006.285.20:42:56.03#ibcon#read 5, iclass 23, count 0 2006.285.20:42:56.03#ibcon#about to read 6, iclass 23, count 0 2006.285.20:42:56.03#ibcon#read 6, iclass 23, count 0 2006.285.20:42:56.03#ibcon#end of sib2, iclass 23, count 0 2006.285.20:42:56.03#ibcon#*mode == 0, iclass 23, count 0 2006.285.20:42:56.03#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.20:42:56.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.20:42:56.03#ibcon#*before write, iclass 23, count 0 2006.285.20:42:56.03#ibcon#enter sib2, iclass 23, count 0 2006.285.20:42:56.03#ibcon#flushed, iclass 23, count 0 2006.285.20:42:56.03#ibcon#about to write, iclass 23, count 0 2006.285.20:42:56.03#ibcon#wrote, iclass 23, count 0 2006.285.20:42:56.03#ibcon#about to read 3, iclass 23, count 0 2006.285.20:42:56.07#ibcon#read 3, iclass 23, count 0 2006.285.20:42:56.07#ibcon#about to read 4, iclass 23, count 0 2006.285.20:42:56.07#ibcon#read 4, iclass 23, count 0 2006.285.20:42:56.07#ibcon#about to read 5, iclass 23, count 0 2006.285.20:42:56.07#ibcon#read 5, iclass 23, count 0 2006.285.20:42:56.07#ibcon#about to read 6, iclass 23, count 0 2006.285.20:42:56.07#ibcon#read 6, iclass 23, count 0 2006.285.20:42:56.07#ibcon#end of sib2, iclass 23, count 0 2006.285.20:42:56.07#ibcon#*after write, iclass 23, count 0 2006.285.20:42:56.07#ibcon#*before return 0, iclass 23, count 0 2006.285.20:42:56.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:42:56.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:42:56.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.20:42:56.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.20:42:56.08$vck44/va=2,6 2006.285.20:42:56.08#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.20:42:56.08#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.20:42:56.08#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:56.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:42:56.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:42:56.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:42:56.12#ibcon#enter wrdev, iclass 25, count 2 2006.285.20:42:56.12#ibcon#first serial, iclass 25, count 2 2006.285.20:42:56.12#ibcon#enter sib2, iclass 25, count 2 2006.285.20:42:56.12#ibcon#flushed, iclass 25, count 2 2006.285.20:42:56.12#ibcon#about to write, iclass 25, count 2 2006.285.20:42:56.12#ibcon#wrote, iclass 25, count 2 2006.285.20:42:56.12#ibcon#about to read 3, iclass 25, count 2 2006.285.20:42:56.14#ibcon#read 3, iclass 25, count 2 2006.285.20:42:56.14#ibcon#about to read 4, iclass 25, count 2 2006.285.20:42:56.14#ibcon#read 4, iclass 25, count 2 2006.285.20:42:56.14#ibcon#about to read 5, iclass 25, count 2 2006.285.20:42:56.14#ibcon#read 5, iclass 25, count 2 2006.285.20:42:56.14#ibcon#about to read 6, iclass 25, count 2 2006.285.20:42:56.14#ibcon#read 6, iclass 25, count 2 2006.285.20:42:56.14#ibcon#end of sib2, iclass 25, count 2 2006.285.20:42:56.14#ibcon#*mode == 0, iclass 25, count 2 2006.285.20:42:56.14#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.20:42:56.14#ibcon#[25=AT02-06\r\n] 2006.285.20:42:56.14#ibcon#*before write, iclass 25, count 2 2006.285.20:42:56.14#ibcon#enter sib2, iclass 25, count 2 2006.285.20:42:56.14#ibcon#flushed, iclass 25, count 2 2006.285.20:42:56.14#ibcon#about to write, iclass 25, count 2 2006.285.20:42:56.14#ibcon#wrote, iclass 25, count 2 2006.285.20:42:56.14#ibcon#about to read 3, iclass 25, count 2 2006.285.20:42:56.17#ibcon#read 3, iclass 25, count 2 2006.285.20:42:56.17#ibcon#about to read 4, iclass 25, count 2 2006.285.20:42:56.17#ibcon#read 4, iclass 25, count 2 2006.285.20:42:56.17#ibcon#about to read 5, iclass 25, count 2 2006.285.20:42:56.17#ibcon#read 5, iclass 25, count 2 2006.285.20:42:56.17#ibcon#about to read 6, iclass 25, count 2 2006.285.20:42:56.17#ibcon#read 6, iclass 25, count 2 2006.285.20:42:56.17#ibcon#end of sib2, iclass 25, count 2 2006.285.20:42:56.17#ibcon#*after write, iclass 25, count 2 2006.285.20:42:56.17#ibcon#*before return 0, iclass 25, count 2 2006.285.20:42:56.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:42:56.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:42:56.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.20:42:56.17#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:56.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:42:56.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:42:56.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:42:56.29#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:42:56.29#ibcon#first serial, iclass 25, count 0 2006.285.20:42:56.29#ibcon#enter sib2, iclass 25, count 0 2006.285.20:42:56.29#ibcon#flushed, iclass 25, count 0 2006.285.20:42:56.29#ibcon#about to write, iclass 25, count 0 2006.285.20:42:56.29#ibcon#wrote, iclass 25, count 0 2006.285.20:42:56.29#ibcon#about to read 3, iclass 25, count 0 2006.285.20:42:56.31#ibcon#read 3, iclass 25, count 0 2006.285.20:42:56.31#ibcon#about to read 4, iclass 25, count 0 2006.285.20:42:56.31#ibcon#read 4, iclass 25, count 0 2006.285.20:42:56.31#ibcon#about to read 5, iclass 25, count 0 2006.285.20:42:56.31#ibcon#read 5, iclass 25, count 0 2006.285.20:42:56.31#ibcon#about to read 6, iclass 25, count 0 2006.285.20:42:56.31#ibcon#read 6, iclass 25, count 0 2006.285.20:42:56.31#ibcon#end of sib2, iclass 25, count 0 2006.285.20:42:56.31#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:42:56.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:42:56.31#ibcon#[25=USB\r\n] 2006.285.20:42:56.31#ibcon#*before write, iclass 25, count 0 2006.285.20:42:56.31#ibcon#enter sib2, iclass 25, count 0 2006.285.20:42:56.31#ibcon#flushed, iclass 25, count 0 2006.285.20:42:56.31#ibcon#about to write, iclass 25, count 0 2006.285.20:42:56.31#ibcon#wrote, iclass 25, count 0 2006.285.20:42:56.31#ibcon#about to read 3, iclass 25, count 0 2006.285.20:42:56.34#ibcon#read 3, iclass 25, count 0 2006.285.20:42:56.34#ibcon#about to read 4, iclass 25, count 0 2006.285.20:42:56.34#ibcon#read 4, iclass 25, count 0 2006.285.20:42:56.34#ibcon#about to read 5, iclass 25, count 0 2006.285.20:42:56.34#ibcon#read 5, iclass 25, count 0 2006.285.20:42:56.34#ibcon#about to read 6, iclass 25, count 0 2006.285.20:42:56.34#ibcon#read 6, iclass 25, count 0 2006.285.20:42:56.34#ibcon#end of sib2, iclass 25, count 0 2006.285.20:42:56.34#ibcon#*after write, iclass 25, count 0 2006.285.20:42:56.34#ibcon#*before return 0, iclass 25, count 0 2006.285.20:42:56.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:42:56.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:42:56.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:42:56.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:42:56.35$vck44/valo=3,564.99 2006.285.20:42:56.35#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.20:42:56.35#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.20:42:56.35#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:56.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:42:56.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:42:56.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:42:56.35#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:42:56.35#ibcon#first serial, iclass 27, count 0 2006.285.20:42:56.35#ibcon#enter sib2, iclass 27, count 0 2006.285.20:42:56.35#ibcon#flushed, iclass 27, count 0 2006.285.20:42:56.35#ibcon#about to write, iclass 27, count 0 2006.285.20:42:56.35#ibcon#wrote, iclass 27, count 0 2006.285.20:42:56.35#ibcon#about to read 3, iclass 27, count 0 2006.285.20:42:56.36#ibcon#read 3, iclass 27, count 0 2006.285.20:42:56.36#ibcon#about to read 4, iclass 27, count 0 2006.285.20:42:56.36#ibcon#read 4, iclass 27, count 0 2006.285.20:42:56.36#ibcon#about to read 5, iclass 27, count 0 2006.285.20:42:56.36#ibcon#read 5, iclass 27, count 0 2006.285.20:42:56.36#ibcon#about to read 6, iclass 27, count 0 2006.285.20:42:56.36#ibcon#read 6, iclass 27, count 0 2006.285.20:42:56.36#ibcon#end of sib2, iclass 27, count 0 2006.285.20:42:56.36#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:42:56.36#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:42:56.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.20:42:56.36#ibcon#*before write, iclass 27, count 0 2006.285.20:42:56.36#ibcon#enter sib2, iclass 27, count 0 2006.285.20:42:56.36#ibcon#flushed, iclass 27, count 0 2006.285.20:42:56.36#ibcon#about to write, iclass 27, count 0 2006.285.20:42:56.36#ibcon#wrote, iclass 27, count 0 2006.285.20:42:56.36#ibcon#about to read 3, iclass 27, count 0 2006.285.20:42:56.40#ibcon#read 3, iclass 27, count 0 2006.285.20:42:56.40#ibcon#about to read 4, iclass 27, count 0 2006.285.20:42:56.40#ibcon#read 4, iclass 27, count 0 2006.285.20:42:56.40#ibcon#about to read 5, iclass 27, count 0 2006.285.20:42:56.40#ibcon#read 5, iclass 27, count 0 2006.285.20:42:56.40#ibcon#about to read 6, iclass 27, count 0 2006.285.20:42:56.40#ibcon#read 6, iclass 27, count 0 2006.285.20:42:56.40#ibcon#end of sib2, iclass 27, count 0 2006.285.20:42:56.40#ibcon#*after write, iclass 27, count 0 2006.285.20:42:56.40#ibcon#*before return 0, iclass 27, count 0 2006.285.20:42:56.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:42:56.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:42:56.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:42:56.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:42:56.41$vck44/va=3,7 2006.285.20:42:56.41#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.20:42:56.41#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.20:42:56.41#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:56.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:42:56.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:42:56.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:42:56.45#ibcon#enter wrdev, iclass 29, count 2 2006.285.20:42:56.45#ibcon#first serial, iclass 29, count 2 2006.285.20:42:56.45#ibcon#enter sib2, iclass 29, count 2 2006.285.20:42:56.45#ibcon#flushed, iclass 29, count 2 2006.285.20:42:56.45#ibcon#about to write, iclass 29, count 2 2006.285.20:42:56.45#ibcon#wrote, iclass 29, count 2 2006.285.20:42:56.45#ibcon#about to read 3, iclass 29, count 2 2006.285.20:42:56.47#ibcon#read 3, iclass 29, count 2 2006.285.20:42:56.47#ibcon#about to read 4, iclass 29, count 2 2006.285.20:42:56.47#ibcon#read 4, iclass 29, count 2 2006.285.20:42:56.47#ibcon#about to read 5, iclass 29, count 2 2006.285.20:42:56.47#ibcon#read 5, iclass 29, count 2 2006.285.20:42:56.47#ibcon#about to read 6, iclass 29, count 2 2006.285.20:42:56.47#ibcon#read 6, iclass 29, count 2 2006.285.20:42:56.47#ibcon#end of sib2, iclass 29, count 2 2006.285.20:42:56.47#ibcon#*mode == 0, iclass 29, count 2 2006.285.20:42:56.47#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.20:42:56.47#ibcon#[25=AT03-07\r\n] 2006.285.20:42:56.47#ibcon#*before write, iclass 29, count 2 2006.285.20:42:56.47#ibcon#enter sib2, iclass 29, count 2 2006.285.20:42:56.47#ibcon#flushed, iclass 29, count 2 2006.285.20:42:56.47#ibcon#about to write, iclass 29, count 2 2006.285.20:42:56.47#ibcon#wrote, iclass 29, count 2 2006.285.20:42:56.47#ibcon#about to read 3, iclass 29, count 2 2006.285.20:42:56.50#ibcon#read 3, iclass 29, count 2 2006.285.20:42:56.50#ibcon#about to read 4, iclass 29, count 2 2006.285.20:42:56.50#ibcon#read 4, iclass 29, count 2 2006.285.20:42:56.50#ibcon#about to read 5, iclass 29, count 2 2006.285.20:42:56.50#ibcon#read 5, iclass 29, count 2 2006.285.20:42:56.50#ibcon#about to read 6, iclass 29, count 2 2006.285.20:42:56.50#ibcon#read 6, iclass 29, count 2 2006.285.20:42:56.50#ibcon#end of sib2, iclass 29, count 2 2006.285.20:42:56.50#ibcon#*after write, iclass 29, count 2 2006.285.20:42:56.50#ibcon#*before return 0, iclass 29, count 2 2006.285.20:42:56.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:42:56.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:42:56.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.20:42:56.50#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:56.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:42:56.62#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:42:56.62#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:42:56.62#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:42:56.62#ibcon#first serial, iclass 29, count 0 2006.285.20:42:56.62#ibcon#enter sib2, iclass 29, count 0 2006.285.20:42:56.62#ibcon#flushed, iclass 29, count 0 2006.285.20:42:56.62#ibcon#about to write, iclass 29, count 0 2006.285.20:42:56.62#ibcon#wrote, iclass 29, count 0 2006.285.20:42:56.62#ibcon#about to read 3, iclass 29, count 0 2006.285.20:42:56.64#ibcon#read 3, iclass 29, count 0 2006.285.20:42:56.64#ibcon#about to read 4, iclass 29, count 0 2006.285.20:42:56.64#ibcon#read 4, iclass 29, count 0 2006.285.20:42:56.64#ibcon#about to read 5, iclass 29, count 0 2006.285.20:42:56.64#ibcon#read 5, iclass 29, count 0 2006.285.20:42:56.64#ibcon#about to read 6, iclass 29, count 0 2006.285.20:42:56.64#ibcon#read 6, iclass 29, count 0 2006.285.20:42:56.64#ibcon#end of sib2, iclass 29, count 0 2006.285.20:42:56.64#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:42:56.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:42:56.64#ibcon#[25=USB\r\n] 2006.285.20:42:56.64#ibcon#*before write, iclass 29, count 0 2006.285.20:42:56.64#ibcon#enter sib2, iclass 29, count 0 2006.285.20:42:56.64#ibcon#flushed, iclass 29, count 0 2006.285.20:42:56.64#ibcon#about to write, iclass 29, count 0 2006.285.20:42:56.64#ibcon#wrote, iclass 29, count 0 2006.285.20:42:56.64#ibcon#about to read 3, iclass 29, count 0 2006.285.20:42:56.67#ibcon#read 3, iclass 29, count 0 2006.285.20:42:56.67#ibcon#about to read 4, iclass 29, count 0 2006.285.20:42:56.67#ibcon#read 4, iclass 29, count 0 2006.285.20:42:56.67#ibcon#about to read 5, iclass 29, count 0 2006.285.20:42:56.67#ibcon#read 5, iclass 29, count 0 2006.285.20:42:56.67#ibcon#about to read 6, iclass 29, count 0 2006.285.20:42:56.67#ibcon#read 6, iclass 29, count 0 2006.285.20:42:56.67#ibcon#end of sib2, iclass 29, count 0 2006.285.20:42:56.67#ibcon#*after write, iclass 29, count 0 2006.285.20:42:56.67#ibcon#*before return 0, iclass 29, count 0 2006.285.20:42:56.67#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:42:56.67#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:42:56.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:42:56.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:42:56.68$vck44/valo=4,624.99 2006.285.20:42:56.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.20:42:56.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.20:42:56.68#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:56.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:42:56.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:42:56.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:42:56.68#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:42:56.68#ibcon#first serial, iclass 31, count 0 2006.285.20:42:56.68#ibcon#enter sib2, iclass 31, count 0 2006.285.20:42:56.68#ibcon#flushed, iclass 31, count 0 2006.285.20:42:56.68#ibcon#about to write, iclass 31, count 0 2006.285.20:42:57.05#ibcon#wrote, iclass 31, count 0 2006.285.20:42:57.05#ibcon#about to read 3, iclass 31, count 0 2006.285.20:42:57.06#ibcon#read 3, iclass 31, count 0 2006.285.20:42:57.06#ibcon#about to read 4, iclass 31, count 0 2006.285.20:42:57.06#ibcon#read 4, iclass 31, count 0 2006.285.20:42:57.06#ibcon#about to read 5, iclass 31, count 0 2006.285.20:42:57.06#ibcon#read 5, iclass 31, count 0 2006.285.20:42:57.06#ibcon#about to read 6, iclass 31, count 0 2006.285.20:42:57.06#ibcon#read 6, iclass 31, count 0 2006.285.20:42:57.06#ibcon#end of sib2, iclass 31, count 0 2006.285.20:42:57.06#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:42:57.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:42:57.06#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.20:42:57.06#ibcon#*before write, iclass 31, count 0 2006.285.20:42:57.06#ibcon#enter sib2, iclass 31, count 0 2006.285.20:42:57.07#ibcon#flushed, iclass 31, count 0 2006.285.20:42:57.07#ibcon#about to write, iclass 31, count 0 2006.285.20:42:57.07#ibcon#wrote, iclass 31, count 0 2006.285.20:42:57.07#ibcon#about to read 3, iclass 31, count 0 2006.285.20:42:57.10#ibcon#read 3, iclass 31, count 0 2006.285.20:42:57.10#ibcon#about to read 4, iclass 31, count 0 2006.285.20:42:57.10#ibcon#read 4, iclass 31, count 0 2006.285.20:42:57.10#ibcon#about to read 5, iclass 31, count 0 2006.285.20:42:57.10#ibcon#read 5, iclass 31, count 0 2006.285.20:42:57.10#ibcon#about to read 6, iclass 31, count 0 2006.285.20:42:57.10#ibcon#read 6, iclass 31, count 0 2006.285.20:42:57.10#ibcon#end of sib2, iclass 31, count 0 2006.285.20:42:57.10#ibcon#*after write, iclass 31, count 0 2006.285.20:42:57.10#ibcon#*before return 0, iclass 31, count 0 2006.285.20:42:57.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:42:57.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:42:57.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:42:57.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:42:57.11$vck44/va=4,6 2006.285.20:42:57.11#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.20:42:57.11#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.20:42:57.11#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:57.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:42:57.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:42:57.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:42:57.11#ibcon#enter wrdev, iclass 33, count 2 2006.285.20:42:57.11#ibcon#first serial, iclass 33, count 2 2006.285.20:42:57.11#ibcon#enter sib2, iclass 33, count 2 2006.285.20:42:57.11#ibcon#flushed, iclass 33, count 2 2006.285.20:42:57.11#ibcon#about to write, iclass 33, count 2 2006.285.20:42:57.11#ibcon#wrote, iclass 33, count 2 2006.285.20:42:57.11#ibcon#about to read 3, iclass 33, count 2 2006.285.20:42:57.12#ibcon#read 3, iclass 33, count 2 2006.285.20:42:57.12#ibcon#about to read 4, iclass 33, count 2 2006.285.20:42:57.12#ibcon#read 4, iclass 33, count 2 2006.285.20:42:57.12#ibcon#about to read 5, iclass 33, count 2 2006.285.20:42:57.12#ibcon#read 5, iclass 33, count 2 2006.285.20:42:57.12#ibcon#about to read 6, iclass 33, count 2 2006.285.20:42:57.12#ibcon#read 6, iclass 33, count 2 2006.285.20:42:57.12#ibcon#end of sib2, iclass 33, count 2 2006.285.20:42:57.12#ibcon#*mode == 0, iclass 33, count 2 2006.285.20:42:57.12#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.20:42:57.12#ibcon#[25=AT04-06\r\n] 2006.285.20:42:57.12#ibcon#*before write, iclass 33, count 2 2006.285.20:42:57.12#ibcon#enter sib2, iclass 33, count 2 2006.285.20:42:57.12#ibcon#flushed, iclass 33, count 2 2006.285.20:42:57.12#ibcon#about to write, iclass 33, count 2 2006.285.20:42:57.12#ibcon#wrote, iclass 33, count 2 2006.285.20:42:57.12#ibcon#about to read 3, iclass 33, count 2 2006.285.20:42:57.15#ibcon#read 3, iclass 33, count 2 2006.285.20:42:57.15#ibcon#about to read 4, iclass 33, count 2 2006.285.20:42:57.15#ibcon#read 4, iclass 33, count 2 2006.285.20:42:57.15#ibcon#about to read 5, iclass 33, count 2 2006.285.20:42:57.15#ibcon#read 5, iclass 33, count 2 2006.285.20:42:57.15#ibcon#about to read 6, iclass 33, count 2 2006.285.20:42:57.15#ibcon#read 6, iclass 33, count 2 2006.285.20:42:57.15#ibcon#end of sib2, iclass 33, count 2 2006.285.20:42:57.15#ibcon#*after write, iclass 33, count 2 2006.285.20:42:57.15#ibcon#*before return 0, iclass 33, count 2 2006.285.20:42:57.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:42:57.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:42:57.15#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.20:42:57.15#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:57.15#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:42:57.27#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:42:57.27#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:42:57.27#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:42:57.27#ibcon#first serial, iclass 33, count 0 2006.285.20:42:57.27#ibcon#enter sib2, iclass 33, count 0 2006.285.20:42:57.27#ibcon#flushed, iclass 33, count 0 2006.285.20:42:57.27#ibcon#about to write, iclass 33, count 0 2006.285.20:42:57.27#ibcon#wrote, iclass 33, count 0 2006.285.20:42:57.27#ibcon#about to read 3, iclass 33, count 0 2006.285.20:42:57.29#ibcon#read 3, iclass 33, count 0 2006.285.20:42:57.29#ibcon#about to read 4, iclass 33, count 0 2006.285.20:42:57.29#ibcon#read 4, iclass 33, count 0 2006.285.20:42:57.29#ibcon#about to read 5, iclass 33, count 0 2006.285.20:42:57.29#ibcon#read 5, iclass 33, count 0 2006.285.20:42:57.29#ibcon#about to read 6, iclass 33, count 0 2006.285.20:42:57.29#ibcon#read 6, iclass 33, count 0 2006.285.20:42:57.29#ibcon#end of sib2, iclass 33, count 0 2006.285.20:42:57.29#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:42:57.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:42:57.29#ibcon#[25=USB\r\n] 2006.285.20:42:57.29#ibcon#*before write, iclass 33, count 0 2006.285.20:42:57.29#ibcon#enter sib2, iclass 33, count 0 2006.285.20:42:57.29#ibcon#flushed, iclass 33, count 0 2006.285.20:42:57.29#ibcon#about to write, iclass 33, count 0 2006.285.20:42:57.29#ibcon#wrote, iclass 33, count 0 2006.285.20:42:57.29#ibcon#about to read 3, iclass 33, count 0 2006.285.20:42:57.32#ibcon#read 3, iclass 33, count 0 2006.285.20:42:57.32#ibcon#about to read 4, iclass 33, count 0 2006.285.20:42:57.32#ibcon#read 4, iclass 33, count 0 2006.285.20:42:57.32#ibcon#about to read 5, iclass 33, count 0 2006.285.20:42:57.32#ibcon#read 5, iclass 33, count 0 2006.285.20:42:57.32#ibcon#about to read 6, iclass 33, count 0 2006.285.20:42:57.32#ibcon#read 6, iclass 33, count 0 2006.285.20:42:57.32#ibcon#end of sib2, iclass 33, count 0 2006.285.20:42:57.32#ibcon#*after write, iclass 33, count 0 2006.285.20:42:57.32#ibcon#*before return 0, iclass 33, count 0 2006.285.20:42:57.32#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:42:57.32#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:42:57.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:42:57.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:42:57.33$vck44/valo=5,734.99 2006.285.20:42:57.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.20:42:57.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.20:42:57.33#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:57.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:42:57.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:42:57.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:42:57.33#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:42:57.33#ibcon#first serial, iclass 35, count 0 2006.285.20:42:57.33#ibcon#enter sib2, iclass 35, count 0 2006.285.20:42:57.33#ibcon#flushed, iclass 35, count 0 2006.285.20:42:57.70#ibcon#about to write, iclass 35, count 0 2006.285.20:42:57.70#ibcon#wrote, iclass 35, count 0 2006.285.20:42:57.70#ibcon#about to read 3, iclass 35, count 0 2006.285.20:42:57.71#ibcon#read 3, iclass 35, count 0 2006.285.20:42:57.71#ibcon#about to read 4, iclass 35, count 0 2006.285.20:42:57.71#ibcon#read 4, iclass 35, count 0 2006.285.20:42:57.71#ibcon#about to read 5, iclass 35, count 0 2006.285.20:42:57.71#ibcon#read 5, iclass 35, count 0 2006.285.20:42:57.71#ibcon#about to read 6, iclass 35, count 0 2006.285.20:42:57.71#ibcon#read 6, iclass 35, count 0 2006.285.20:42:57.71#ibcon#end of sib2, iclass 35, count 0 2006.285.20:42:57.71#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:42:57.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:42:57.71#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.20:42:57.71#ibcon#*before write, iclass 35, count 0 2006.285.20:42:57.71#ibcon#enter sib2, iclass 35, count 0 2006.285.20:42:57.71#ibcon#flushed, iclass 35, count 0 2006.285.20:42:57.71#ibcon#about to write, iclass 35, count 0 2006.285.20:42:57.71#ibcon#wrote, iclass 35, count 0 2006.285.20:42:57.71#ibcon#about to read 3, iclass 35, count 0 2006.285.20:42:57.75#ibcon#read 3, iclass 35, count 0 2006.285.20:42:57.75#ibcon#about to read 4, iclass 35, count 0 2006.285.20:42:57.75#ibcon#read 4, iclass 35, count 0 2006.285.20:42:57.75#ibcon#about to read 5, iclass 35, count 0 2006.285.20:42:57.75#ibcon#read 5, iclass 35, count 0 2006.285.20:42:57.75#ibcon#about to read 6, iclass 35, count 0 2006.285.20:42:57.75#ibcon#read 6, iclass 35, count 0 2006.285.20:42:57.75#ibcon#end of sib2, iclass 35, count 0 2006.285.20:42:57.75#ibcon#*after write, iclass 35, count 0 2006.285.20:42:57.75#ibcon#*before return 0, iclass 35, count 0 2006.285.20:42:57.75#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:42:57.75#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:42:57.75#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:42:57.75#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:42:57.76$vck44/va=5,3 2006.285.20:42:57.76#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.20:42:57.76#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.20:42:57.76#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:57.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:42:57.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:42:57.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:42:57.76#ibcon#enter wrdev, iclass 37, count 2 2006.285.20:42:57.76#ibcon#first serial, iclass 37, count 2 2006.285.20:42:57.76#ibcon#enter sib2, iclass 37, count 2 2006.285.20:42:57.76#ibcon#flushed, iclass 37, count 2 2006.285.20:42:57.76#ibcon#about to write, iclass 37, count 2 2006.285.20:42:57.76#ibcon#wrote, iclass 37, count 2 2006.285.20:42:57.76#ibcon#about to read 3, iclass 37, count 2 2006.285.20:42:57.77#ibcon#read 3, iclass 37, count 2 2006.285.20:42:57.77#ibcon#about to read 4, iclass 37, count 2 2006.285.20:42:57.77#ibcon#read 4, iclass 37, count 2 2006.285.20:42:57.77#ibcon#about to read 5, iclass 37, count 2 2006.285.20:42:57.77#ibcon#read 5, iclass 37, count 2 2006.285.20:42:57.77#ibcon#about to read 6, iclass 37, count 2 2006.285.20:42:57.77#ibcon#read 6, iclass 37, count 2 2006.285.20:42:57.77#ibcon#end of sib2, iclass 37, count 2 2006.285.20:42:57.77#ibcon#*mode == 0, iclass 37, count 2 2006.285.20:42:57.77#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.20:42:57.77#ibcon#[25=AT05-03\r\n] 2006.285.20:42:57.77#ibcon#*before write, iclass 37, count 2 2006.285.20:42:57.77#ibcon#enter sib2, iclass 37, count 2 2006.285.20:42:57.77#ibcon#flushed, iclass 37, count 2 2006.285.20:42:57.77#ibcon#about to write, iclass 37, count 2 2006.285.20:42:57.77#ibcon#wrote, iclass 37, count 2 2006.285.20:42:57.77#ibcon#about to read 3, iclass 37, count 2 2006.285.20:42:57.80#ibcon#read 3, iclass 37, count 2 2006.285.20:42:57.80#ibcon#about to read 4, iclass 37, count 2 2006.285.20:42:57.80#ibcon#read 4, iclass 37, count 2 2006.285.20:42:57.80#ibcon#about to read 5, iclass 37, count 2 2006.285.20:42:57.80#ibcon#read 5, iclass 37, count 2 2006.285.20:42:57.80#ibcon#about to read 6, iclass 37, count 2 2006.285.20:42:57.80#ibcon#read 6, iclass 37, count 2 2006.285.20:42:57.80#ibcon#end of sib2, iclass 37, count 2 2006.285.20:42:57.80#ibcon#*after write, iclass 37, count 2 2006.285.20:42:57.80#ibcon#*before return 0, iclass 37, count 2 2006.285.20:42:57.80#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:42:57.80#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:42:57.80#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.20:42:57.80#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:57.80#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:42:57.92#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:42:57.92#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:42:57.92#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:42:57.92#ibcon#first serial, iclass 37, count 0 2006.285.20:42:57.92#ibcon#enter sib2, iclass 37, count 0 2006.285.20:42:57.92#ibcon#flushed, iclass 37, count 0 2006.285.20:42:57.92#ibcon#about to write, iclass 37, count 0 2006.285.20:42:57.92#ibcon#wrote, iclass 37, count 0 2006.285.20:42:57.92#ibcon#about to read 3, iclass 37, count 0 2006.285.20:42:57.94#ibcon#read 3, iclass 37, count 0 2006.285.20:42:57.94#ibcon#about to read 4, iclass 37, count 0 2006.285.20:42:57.94#ibcon#read 4, iclass 37, count 0 2006.285.20:42:57.94#ibcon#about to read 5, iclass 37, count 0 2006.285.20:42:57.94#ibcon#read 5, iclass 37, count 0 2006.285.20:42:57.94#ibcon#about to read 6, iclass 37, count 0 2006.285.20:42:57.94#ibcon#read 6, iclass 37, count 0 2006.285.20:42:57.94#ibcon#end of sib2, iclass 37, count 0 2006.285.20:42:57.94#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:42:57.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:42:57.94#ibcon#[25=USB\r\n] 2006.285.20:42:57.94#ibcon#*before write, iclass 37, count 0 2006.285.20:42:57.94#ibcon#enter sib2, iclass 37, count 0 2006.285.20:42:57.94#ibcon#flushed, iclass 37, count 0 2006.285.20:42:57.94#ibcon#about to write, iclass 37, count 0 2006.285.20:42:57.94#ibcon#wrote, iclass 37, count 0 2006.285.20:42:57.95#ibcon#about to read 3, iclass 37, count 0 2006.285.20:42:57.97#ibcon#read 3, iclass 37, count 0 2006.285.20:42:57.97#ibcon#about to read 4, iclass 37, count 0 2006.285.20:42:57.97#ibcon#read 4, iclass 37, count 0 2006.285.20:42:57.97#ibcon#about to read 5, iclass 37, count 0 2006.285.20:42:57.97#ibcon#read 5, iclass 37, count 0 2006.285.20:42:57.97#ibcon#about to read 6, iclass 37, count 0 2006.285.20:42:57.97#ibcon#read 6, iclass 37, count 0 2006.285.20:42:57.97#ibcon#end of sib2, iclass 37, count 0 2006.285.20:42:57.97#ibcon#*after write, iclass 37, count 0 2006.285.20:42:57.97#ibcon#*before return 0, iclass 37, count 0 2006.285.20:42:57.97#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:42:57.97#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:42:57.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:42:57.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:42:57.98$vck44/valo=6,814.99 2006.285.20:42:57.98#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.20:42:57.98#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.20:42:57.98#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:57.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:42:57.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:42:57.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:42:57.98#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:42:57.98#ibcon#first serial, iclass 39, count 0 2006.285.20:42:57.98#ibcon#enter sib2, iclass 39, count 0 2006.285.20:42:57.98#ibcon#flushed, iclass 39, count 0 2006.285.20:42:57.98#ibcon#about to write, iclass 39, count 0 2006.285.20:42:57.98#ibcon#wrote, iclass 39, count 0 2006.285.20:42:57.98#ibcon#about to read 3, iclass 39, count 0 2006.285.20:42:57.99#ibcon#read 3, iclass 39, count 0 2006.285.20:42:57.99#ibcon#about to read 4, iclass 39, count 0 2006.285.20:42:57.99#ibcon#read 4, iclass 39, count 0 2006.285.20:42:57.99#ibcon#about to read 5, iclass 39, count 0 2006.285.20:42:57.99#ibcon#read 5, iclass 39, count 0 2006.285.20:42:57.99#ibcon#about to read 6, iclass 39, count 0 2006.285.20:42:57.99#ibcon#read 6, iclass 39, count 0 2006.285.20:42:57.99#ibcon#end of sib2, iclass 39, count 0 2006.285.20:42:57.99#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:42:57.99#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:42:57.99#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.20:42:57.99#ibcon#*before write, iclass 39, count 0 2006.285.20:42:57.99#ibcon#enter sib2, iclass 39, count 0 2006.285.20:42:57.99#ibcon#flushed, iclass 39, count 0 2006.285.20:42:57.99#ibcon#about to write, iclass 39, count 0 2006.285.20:42:57.99#ibcon#wrote, iclass 39, count 0 2006.285.20:42:57.99#ibcon#about to read 3, iclass 39, count 0 2006.285.20:42:58.03#ibcon#read 3, iclass 39, count 0 2006.285.20:42:58.03#ibcon#about to read 4, iclass 39, count 0 2006.285.20:42:58.03#ibcon#read 4, iclass 39, count 0 2006.285.20:42:58.03#ibcon#about to read 5, iclass 39, count 0 2006.285.20:42:58.03#ibcon#read 5, iclass 39, count 0 2006.285.20:42:58.03#ibcon#about to read 6, iclass 39, count 0 2006.285.20:42:58.03#ibcon#read 6, iclass 39, count 0 2006.285.20:42:58.03#ibcon#end of sib2, iclass 39, count 0 2006.285.20:42:58.03#ibcon#*after write, iclass 39, count 0 2006.285.20:42:58.03#ibcon#*before return 0, iclass 39, count 0 2006.285.20:42:58.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:42:58.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:42:58.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:42:58.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:42:58.04$vck44/va=6,4 2006.285.20:42:58.04#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.20:42:58.04#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.20:42:58.04#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:58.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:42:58.08#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:42:58.08#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:42:58.08#ibcon#enter wrdev, iclass 3, count 2 2006.285.20:42:58.08#ibcon#first serial, iclass 3, count 2 2006.285.20:42:58.08#ibcon#enter sib2, iclass 3, count 2 2006.285.20:42:58.08#ibcon#flushed, iclass 3, count 2 2006.285.20:42:58.08#ibcon#about to write, iclass 3, count 2 2006.285.20:42:58.08#ibcon#wrote, iclass 3, count 2 2006.285.20:42:58.08#ibcon#about to read 3, iclass 3, count 2 2006.285.20:42:58.10#ibcon#read 3, iclass 3, count 2 2006.285.20:42:58.10#ibcon#about to read 4, iclass 3, count 2 2006.285.20:42:58.10#ibcon#read 4, iclass 3, count 2 2006.285.20:42:58.10#ibcon#about to read 5, iclass 3, count 2 2006.285.20:42:58.10#ibcon#read 5, iclass 3, count 2 2006.285.20:42:58.10#ibcon#about to read 6, iclass 3, count 2 2006.285.20:42:58.10#ibcon#read 6, iclass 3, count 2 2006.285.20:42:58.10#ibcon#end of sib2, iclass 3, count 2 2006.285.20:42:58.10#ibcon#*mode == 0, iclass 3, count 2 2006.285.20:42:58.10#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.20:42:58.10#ibcon#[25=AT06-04\r\n] 2006.285.20:42:58.10#ibcon#*before write, iclass 3, count 2 2006.285.20:42:58.10#ibcon#enter sib2, iclass 3, count 2 2006.285.20:42:58.10#ibcon#flushed, iclass 3, count 2 2006.285.20:42:58.10#ibcon#about to write, iclass 3, count 2 2006.285.20:42:58.10#ibcon#wrote, iclass 3, count 2 2006.285.20:42:58.10#ibcon#about to read 3, iclass 3, count 2 2006.285.20:42:58.13#ibcon#read 3, iclass 3, count 2 2006.285.20:42:58.13#ibcon#about to read 4, iclass 3, count 2 2006.285.20:42:58.13#ibcon#read 4, iclass 3, count 2 2006.285.20:42:58.13#ibcon#about to read 5, iclass 3, count 2 2006.285.20:42:58.13#ibcon#read 5, iclass 3, count 2 2006.285.20:42:58.13#ibcon#about to read 6, iclass 3, count 2 2006.285.20:42:58.13#ibcon#read 6, iclass 3, count 2 2006.285.20:42:58.13#ibcon#end of sib2, iclass 3, count 2 2006.285.20:42:58.13#ibcon#*after write, iclass 3, count 2 2006.285.20:42:58.13#ibcon#*before return 0, iclass 3, count 2 2006.285.20:42:58.13#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:42:58.13#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:42:58.13#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.20:42:58.13#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:58.13#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:42:58.25#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:42:58.25#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:42:58.25#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:42:58.25#ibcon#first serial, iclass 3, count 0 2006.285.20:42:58.25#ibcon#enter sib2, iclass 3, count 0 2006.285.20:42:58.25#ibcon#flushed, iclass 3, count 0 2006.285.20:42:58.25#ibcon#about to write, iclass 3, count 0 2006.285.20:42:58.25#ibcon#wrote, iclass 3, count 0 2006.285.20:42:58.25#ibcon#about to read 3, iclass 3, count 0 2006.285.20:42:58.27#ibcon#read 3, iclass 3, count 0 2006.285.20:42:58.27#ibcon#about to read 4, iclass 3, count 0 2006.285.20:42:58.27#ibcon#read 4, iclass 3, count 0 2006.285.20:42:58.27#ibcon#about to read 5, iclass 3, count 0 2006.285.20:42:58.27#ibcon#read 5, iclass 3, count 0 2006.285.20:42:58.27#ibcon#about to read 6, iclass 3, count 0 2006.285.20:42:58.27#ibcon#read 6, iclass 3, count 0 2006.285.20:42:58.27#ibcon#end of sib2, iclass 3, count 0 2006.285.20:42:58.27#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:42:58.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:42:58.27#ibcon#[25=USB\r\n] 2006.285.20:42:58.27#ibcon#*before write, iclass 3, count 0 2006.285.20:42:58.27#ibcon#enter sib2, iclass 3, count 0 2006.285.20:42:58.27#ibcon#flushed, iclass 3, count 0 2006.285.20:42:58.27#ibcon#about to write, iclass 3, count 0 2006.285.20:42:58.27#ibcon#wrote, iclass 3, count 0 2006.285.20:42:58.27#ibcon#about to read 3, iclass 3, count 0 2006.285.20:42:58.30#ibcon#read 3, iclass 3, count 0 2006.285.20:42:58.30#ibcon#about to read 4, iclass 3, count 0 2006.285.20:42:58.30#ibcon#read 4, iclass 3, count 0 2006.285.20:42:58.30#ibcon#about to read 5, iclass 3, count 0 2006.285.20:42:58.30#ibcon#read 5, iclass 3, count 0 2006.285.20:42:58.30#ibcon#about to read 6, iclass 3, count 0 2006.285.20:42:58.30#ibcon#read 6, iclass 3, count 0 2006.285.20:42:58.30#ibcon#end of sib2, iclass 3, count 0 2006.285.20:42:58.30#ibcon#*after write, iclass 3, count 0 2006.285.20:42:58.30#ibcon#*before return 0, iclass 3, count 0 2006.285.20:42:58.30#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:42:58.30#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:42:58.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:42:58.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:42:58.31$vck44/valo=7,864.99 2006.285.20:42:58.31#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.20:42:58.31#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.20:42:58.31#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:58.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:42:58.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:42:58.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:42:58.31#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:42:58.31#ibcon#first serial, iclass 5, count 0 2006.285.20:42:58.31#ibcon#enter sib2, iclass 5, count 0 2006.285.20:42:58.31#ibcon#flushed, iclass 5, count 0 2006.285.20:42:58.31#ibcon#about to write, iclass 5, count 0 2006.285.20:42:58.31#ibcon#wrote, iclass 5, count 0 2006.285.20:42:58.31#ibcon#about to read 3, iclass 5, count 0 2006.285.20:42:58.32#ibcon#read 3, iclass 5, count 0 2006.285.20:42:58.32#ibcon#about to read 4, iclass 5, count 0 2006.285.20:42:58.32#ibcon#read 4, iclass 5, count 0 2006.285.20:42:58.32#ibcon#about to read 5, iclass 5, count 0 2006.285.20:42:58.32#ibcon#read 5, iclass 5, count 0 2006.285.20:42:58.32#ibcon#about to read 6, iclass 5, count 0 2006.285.20:42:58.32#ibcon#read 6, iclass 5, count 0 2006.285.20:42:58.32#ibcon#end of sib2, iclass 5, count 0 2006.285.20:42:58.32#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:42:58.32#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:42:58.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.20:42:58.32#ibcon#*before write, iclass 5, count 0 2006.285.20:42:58.32#ibcon#enter sib2, iclass 5, count 0 2006.285.20:42:58.32#ibcon#flushed, iclass 5, count 0 2006.285.20:42:58.32#ibcon#about to write, iclass 5, count 0 2006.285.20:42:58.32#ibcon#wrote, iclass 5, count 0 2006.285.20:42:58.32#ibcon#about to read 3, iclass 5, count 0 2006.285.20:42:58.36#ibcon#read 3, iclass 5, count 0 2006.285.20:42:58.36#ibcon#about to read 4, iclass 5, count 0 2006.285.20:42:58.36#ibcon#read 4, iclass 5, count 0 2006.285.20:42:58.36#ibcon#about to read 5, iclass 5, count 0 2006.285.20:42:58.36#ibcon#read 5, iclass 5, count 0 2006.285.20:42:58.36#ibcon#about to read 6, iclass 5, count 0 2006.285.20:42:58.36#ibcon#read 6, iclass 5, count 0 2006.285.20:42:58.36#ibcon#end of sib2, iclass 5, count 0 2006.285.20:42:58.36#ibcon#*after write, iclass 5, count 0 2006.285.20:42:58.36#ibcon#*before return 0, iclass 5, count 0 2006.285.20:42:58.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:42:58.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:42:58.36#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:42:58.36#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:42:58.37$vck44/va=7,4 2006.285.20:42:58.37#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.20:42:58.37#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.20:42:58.37#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:58.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:42:58.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:42:58.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:42:58.41#ibcon#enter wrdev, iclass 7, count 2 2006.285.20:42:58.41#ibcon#first serial, iclass 7, count 2 2006.285.20:42:58.41#ibcon#enter sib2, iclass 7, count 2 2006.285.20:42:58.41#ibcon#flushed, iclass 7, count 2 2006.285.20:42:58.41#ibcon#about to write, iclass 7, count 2 2006.285.20:42:58.41#ibcon#wrote, iclass 7, count 2 2006.285.20:42:58.41#ibcon#about to read 3, iclass 7, count 2 2006.285.20:42:58.43#ibcon#read 3, iclass 7, count 2 2006.285.20:42:58.43#ibcon#about to read 4, iclass 7, count 2 2006.285.20:42:58.43#ibcon#read 4, iclass 7, count 2 2006.285.20:42:58.43#ibcon#about to read 5, iclass 7, count 2 2006.285.20:42:58.43#ibcon#read 5, iclass 7, count 2 2006.285.20:42:58.43#ibcon#about to read 6, iclass 7, count 2 2006.285.20:42:58.43#ibcon#read 6, iclass 7, count 2 2006.285.20:42:58.43#ibcon#end of sib2, iclass 7, count 2 2006.285.20:42:58.43#ibcon#*mode == 0, iclass 7, count 2 2006.285.20:42:58.43#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.20:42:58.43#ibcon#[25=AT07-04\r\n] 2006.285.20:42:58.43#ibcon#*before write, iclass 7, count 2 2006.285.20:42:58.43#ibcon#enter sib2, iclass 7, count 2 2006.285.20:42:58.43#ibcon#flushed, iclass 7, count 2 2006.285.20:42:58.43#ibcon#about to write, iclass 7, count 2 2006.285.20:42:58.43#ibcon#wrote, iclass 7, count 2 2006.285.20:42:58.43#ibcon#about to read 3, iclass 7, count 2 2006.285.20:42:58.46#ibcon#read 3, iclass 7, count 2 2006.285.20:42:58.46#ibcon#about to read 4, iclass 7, count 2 2006.285.20:42:58.46#ibcon#read 4, iclass 7, count 2 2006.285.20:42:58.46#ibcon#about to read 5, iclass 7, count 2 2006.285.20:42:58.46#ibcon#read 5, iclass 7, count 2 2006.285.20:42:58.46#ibcon#about to read 6, iclass 7, count 2 2006.285.20:42:58.46#ibcon#read 6, iclass 7, count 2 2006.285.20:42:58.46#ibcon#end of sib2, iclass 7, count 2 2006.285.20:42:58.46#ibcon#*after write, iclass 7, count 2 2006.285.20:42:58.46#ibcon#*before return 0, iclass 7, count 2 2006.285.20:42:58.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:42:58.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:42:58.46#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.20:42:58.46#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:58.46#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:42:58.58#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:42:58.58#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:42:58.58#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:42:58.58#ibcon#first serial, iclass 7, count 0 2006.285.20:42:58.58#ibcon#enter sib2, iclass 7, count 0 2006.285.20:42:58.58#ibcon#flushed, iclass 7, count 0 2006.285.20:42:58.58#ibcon#about to write, iclass 7, count 0 2006.285.20:42:58.58#ibcon#wrote, iclass 7, count 0 2006.285.20:42:58.58#ibcon#about to read 3, iclass 7, count 0 2006.285.20:42:58.60#ibcon#read 3, iclass 7, count 0 2006.285.20:42:58.60#ibcon#about to read 4, iclass 7, count 0 2006.285.20:42:58.60#ibcon#read 4, iclass 7, count 0 2006.285.20:42:58.60#ibcon#about to read 5, iclass 7, count 0 2006.285.20:42:58.60#ibcon#read 5, iclass 7, count 0 2006.285.20:42:58.60#ibcon#about to read 6, iclass 7, count 0 2006.285.20:42:58.60#ibcon#read 6, iclass 7, count 0 2006.285.20:42:58.60#ibcon#end of sib2, iclass 7, count 0 2006.285.20:42:58.60#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:42:58.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:42:58.60#ibcon#[25=USB\r\n] 2006.285.20:42:58.60#ibcon#*before write, iclass 7, count 0 2006.285.20:42:58.60#ibcon#enter sib2, iclass 7, count 0 2006.285.20:42:58.60#ibcon#flushed, iclass 7, count 0 2006.285.20:42:58.60#ibcon#about to write, iclass 7, count 0 2006.285.20:42:58.60#ibcon#wrote, iclass 7, count 0 2006.285.20:42:58.60#ibcon#about to read 3, iclass 7, count 0 2006.285.20:42:58.63#ibcon#read 3, iclass 7, count 0 2006.285.20:42:58.63#ibcon#about to read 4, iclass 7, count 0 2006.285.20:42:58.63#ibcon#read 4, iclass 7, count 0 2006.285.20:42:58.63#ibcon#about to read 5, iclass 7, count 0 2006.285.20:42:58.63#ibcon#read 5, iclass 7, count 0 2006.285.20:42:58.63#ibcon#about to read 6, iclass 7, count 0 2006.285.20:42:58.63#ibcon#read 6, iclass 7, count 0 2006.285.20:42:58.63#ibcon#end of sib2, iclass 7, count 0 2006.285.20:42:58.63#ibcon#*after write, iclass 7, count 0 2006.285.20:42:58.63#ibcon#*before return 0, iclass 7, count 0 2006.285.20:42:58.63#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:42:58.63#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:42:58.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:42:58.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:42:58.64$vck44/valo=8,884.99 2006.285.20:42:58.64#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.20:42:58.64#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.20:42:58.64#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:58.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:42:58.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:42:58.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:42:58.64#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:42:58.64#ibcon#first serial, iclass 11, count 0 2006.285.20:42:58.64#ibcon#enter sib2, iclass 11, count 0 2006.285.20:42:58.64#ibcon#flushed, iclass 11, count 0 2006.285.20:42:58.64#ibcon#about to write, iclass 11, count 0 2006.285.20:42:58.79#ibcon#wrote, iclass 11, count 0 2006.285.20:42:58.79#ibcon#about to read 3, iclass 11, count 0 2006.285.20:42:58.80#ibcon#read 3, iclass 11, count 0 2006.285.20:42:58.80#ibcon#about to read 4, iclass 11, count 0 2006.285.20:42:58.80#ibcon#read 4, iclass 11, count 0 2006.285.20:42:58.80#ibcon#about to read 5, iclass 11, count 0 2006.285.20:42:58.80#ibcon#read 5, iclass 11, count 0 2006.285.20:42:58.80#ibcon#about to read 6, iclass 11, count 0 2006.285.20:42:58.80#ibcon#read 6, iclass 11, count 0 2006.285.20:42:58.80#ibcon#end of sib2, iclass 11, count 0 2006.285.20:42:58.80#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:42:58.80#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:42:58.80#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.20:42:58.80#ibcon#*before write, iclass 11, count 0 2006.285.20:42:58.80#ibcon#enter sib2, iclass 11, count 0 2006.285.20:42:58.80#ibcon#flushed, iclass 11, count 0 2006.285.20:42:58.80#ibcon#about to write, iclass 11, count 0 2006.285.20:42:58.80#ibcon#wrote, iclass 11, count 0 2006.285.20:42:58.80#ibcon#about to read 3, iclass 11, count 0 2006.285.20:42:58.84#ibcon#read 3, iclass 11, count 0 2006.285.20:42:58.84#ibcon#about to read 4, iclass 11, count 0 2006.285.20:42:58.84#ibcon#read 4, iclass 11, count 0 2006.285.20:42:58.84#ibcon#about to read 5, iclass 11, count 0 2006.285.20:42:58.84#ibcon#read 5, iclass 11, count 0 2006.285.20:42:58.84#ibcon#about to read 6, iclass 11, count 0 2006.285.20:42:58.84#ibcon#read 6, iclass 11, count 0 2006.285.20:42:58.84#ibcon#end of sib2, iclass 11, count 0 2006.285.20:42:58.84#ibcon#*after write, iclass 11, count 0 2006.285.20:42:58.84#ibcon#*before return 0, iclass 11, count 0 2006.285.20:42:58.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:42:58.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:42:58.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:42:58.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:42:58.85$vck44/va=8,3 2006.285.20:42:58.85#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.20:42:58.85#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.20:42:58.85#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:58.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:42:58.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:42:58.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:42:58.85#ibcon#enter wrdev, iclass 13, count 2 2006.285.20:42:58.85#ibcon#first serial, iclass 13, count 2 2006.285.20:42:58.85#ibcon#enter sib2, iclass 13, count 2 2006.285.20:42:58.85#ibcon#flushed, iclass 13, count 2 2006.285.20:42:58.85#ibcon#about to write, iclass 13, count 2 2006.285.20:42:58.85#ibcon#wrote, iclass 13, count 2 2006.285.20:42:58.85#ibcon#about to read 3, iclass 13, count 2 2006.285.20:42:58.86#ibcon#read 3, iclass 13, count 2 2006.285.20:42:58.86#ibcon#about to read 4, iclass 13, count 2 2006.285.20:42:58.86#ibcon#read 4, iclass 13, count 2 2006.285.20:42:58.86#ibcon#about to read 5, iclass 13, count 2 2006.285.20:42:58.86#ibcon#read 5, iclass 13, count 2 2006.285.20:42:58.86#ibcon#about to read 6, iclass 13, count 2 2006.285.20:42:58.86#ibcon#read 6, iclass 13, count 2 2006.285.20:42:58.86#ibcon#end of sib2, iclass 13, count 2 2006.285.20:42:58.86#ibcon#*mode == 0, iclass 13, count 2 2006.285.20:42:58.86#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.20:42:58.86#ibcon#[25=AT08-03\r\n] 2006.285.20:42:58.86#ibcon#*before write, iclass 13, count 2 2006.285.20:42:58.86#ibcon#enter sib2, iclass 13, count 2 2006.285.20:42:58.86#ibcon#flushed, iclass 13, count 2 2006.285.20:42:58.86#ibcon#about to write, iclass 13, count 2 2006.285.20:42:58.86#ibcon#wrote, iclass 13, count 2 2006.285.20:42:58.86#ibcon#about to read 3, iclass 13, count 2 2006.285.20:42:58.89#ibcon#read 3, iclass 13, count 2 2006.285.20:42:58.89#ibcon#about to read 4, iclass 13, count 2 2006.285.20:42:58.89#ibcon#read 4, iclass 13, count 2 2006.285.20:42:58.89#ibcon#about to read 5, iclass 13, count 2 2006.285.20:42:58.89#ibcon#read 5, iclass 13, count 2 2006.285.20:42:58.89#ibcon#about to read 6, iclass 13, count 2 2006.285.20:42:58.89#ibcon#read 6, iclass 13, count 2 2006.285.20:42:58.89#ibcon#end of sib2, iclass 13, count 2 2006.285.20:42:58.89#ibcon#*after write, iclass 13, count 2 2006.285.20:42:58.89#ibcon#*before return 0, iclass 13, count 2 2006.285.20:42:58.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:42:58.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:42:58.89#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.20:42:58.89#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:58.89#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:42:59.02#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:42:59.02#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:42:59.02#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:42:59.02#ibcon#first serial, iclass 13, count 0 2006.285.20:42:59.02#ibcon#enter sib2, iclass 13, count 0 2006.285.20:42:59.02#ibcon#flushed, iclass 13, count 0 2006.285.20:42:59.02#ibcon#about to write, iclass 13, count 0 2006.285.20:42:59.02#ibcon#wrote, iclass 13, count 0 2006.285.20:42:59.02#ibcon#about to read 3, iclass 13, count 0 2006.285.20:42:59.03#ibcon#read 3, iclass 13, count 0 2006.285.20:42:59.03#ibcon#about to read 4, iclass 13, count 0 2006.285.20:42:59.03#ibcon#read 4, iclass 13, count 0 2006.285.20:42:59.03#ibcon#about to read 5, iclass 13, count 0 2006.285.20:42:59.03#ibcon#read 5, iclass 13, count 0 2006.285.20:42:59.03#ibcon#about to read 6, iclass 13, count 0 2006.285.20:42:59.03#ibcon#read 6, iclass 13, count 0 2006.285.20:42:59.03#ibcon#end of sib2, iclass 13, count 0 2006.285.20:42:59.03#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:42:59.03#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:42:59.03#ibcon#[25=USB\r\n] 2006.285.20:42:59.03#ibcon#*before write, iclass 13, count 0 2006.285.20:42:59.03#ibcon#enter sib2, iclass 13, count 0 2006.285.20:42:59.03#ibcon#flushed, iclass 13, count 0 2006.285.20:42:59.03#ibcon#about to write, iclass 13, count 0 2006.285.20:42:59.03#ibcon#wrote, iclass 13, count 0 2006.285.20:42:59.03#ibcon#about to read 3, iclass 13, count 0 2006.285.20:42:59.06#ibcon#read 3, iclass 13, count 0 2006.285.20:42:59.06#ibcon#about to read 4, iclass 13, count 0 2006.285.20:42:59.06#ibcon#read 4, iclass 13, count 0 2006.285.20:42:59.06#ibcon#about to read 5, iclass 13, count 0 2006.285.20:42:59.06#ibcon#read 5, iclass 13, count 0 2006.285.20:42:59.06#ibcon#about to read 6, iclass 13, count 0 2006.285.20:42:59.06#ibcon#read 6, iclass 13, count 0 2006.285.20:42:59.06#ibcon#end of sib2, iclass 13, count 0 2006.285.20:42:59.06#ibcon#*after write, iclass 13, count 0 2006.285.20:42:59.06#ibcon#*before return 0, iclass 13, count 0 2006.285.20:42:59.06#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:42:59.06#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:42:59.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:42:59.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:42:59.07$vck44/vblo=1,629.99 2006.285.20:42:59.07#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.20:42:59.07#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.20:42:59.07#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:59.07#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:42:59.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:42:59.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:42:59.07#ibcon#enter wrdev, iclass 15, count 0 2006.285.20:42:59.07#ibcon#first serial, iclass 15, count 0 2006.285.20:42:59.07#ibcon#enter sib2, iclass 15, count 0 2006.285.20:42:59.07#ibcon#flushed, iclass 15, count 0 2006.285.20:42:59.07#ibcon#about to write, iclass 15, count 0 2006.285.20:42:59.07#ibcon#wrote, iclass 15, count 0 2006.285.20:42:59.07#ibcon#about to read 3, iclass 15, count 0 2006.285.20:42:59.08#ibcon#read 3, iclass 15, count 0 2006.285.20:42:59.08#ibcon#about to read 4, iclass 15, count 0 2006.285.20:42:59.08#ibcon#read 4, iclass 15, count 0 2006.285.20:42:59.08#ibcon#about to read 5, iclass 15, count 0 2006.285.20:42:59.08#ibcon#read 5, iclass 15, count 0 2006.285.20:42:59.08#ibcon#about to read 6, iclass 15, count 0 2006.285.20:42:59.08#ibcon#read 6, iclass 15, count 0 2006.285.20:42:59.08#ibcon#end of sib2, iclass 15, count 0 2006.285.20:42:59.08#ibcon#*mode == 0, iclass 15, count 0 2006.285.20:42:59.08#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.20:42:59.08#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.20:42:59.08#ibcon#*before write, iclass 15, count 0 2006.285.20:42:59.08#ibcon#enter sib2, iclass 15, count 0 2006.285.20:42:59.08#ibcon#flushed, iclass 15, count 0 2006.285.20:42:59.08#ibcon#about to write, iclass 15, count 0 2006.285.20:42:59.08#ibcon#wrote, iclass 15, count 0 2006.285.20:42:59.08#ibcon#about to read 3, iclass 15, count 0 2006.285.20:42:59.12#ibcon#read 3, iclass 15, count 0 2006.285.20:42:59.12#ibcon#about to read 4, iclass 15, count 0 2006.285.20:42:59.12#ibcon#read 4, iclass 15, count 0 2006.285.20:42:59.12#ibcon#about to read 5, iclass 15, count 0 2006.285.20:42:59.12#ibcon#read 5, iclass 15, count 0 2006.285.20:42:59.12#ibcon#about to read 6, iclass 15, count 0 2006.285.20:42:59.12#ibcon#read 6, iclass 15, count 0 2006.285.20:42:59.12#ibcon#end of sib2, iclass 15, count 0 2006.285.20:42:59.12#ibcon#*after write, iclass 15, count 0 2006.285.20:42:59.12#ibcon#*before return 0, iclass 15, count 0 2006.285.20:42:59.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:42:59.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:42:59.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.20:42:59.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.20:42:59.13$vck44/vb=1,4 2006.285.20:42:59.13#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.20:42:59.13#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.20:42:59.13#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:59.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:42:59.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:42:59.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:42:59.13#ibcon#enter wrdev, iclass 17, count 2 2006.285.20:42:59.13#ibcon#first serial, iclass 17, count 2 2006.285.20:42:59.13#ibcon#enter sib2, iclass 17, count 2 2006.285.20:42:59.13#ibcon#flushed, iclass 17, count 2 2006.285.20:42:59.13#ibcon#about to write, iclass 17, count 2 2006.285.20:42:59.13#ibcon#wrote, iclass 17, count 2 2006.285.20:42:59.13#ibcon#about to read 3, iclass 17, count 2 2006.285.20:42:59.14#ibcon#read 3, iclass 17, count 2 2006.285.20:42:59.14#ibcon#about to read 4, iclass 17, count 2 2006.285.20:42:59.14#ibcon#read 4, iclass 17, count 2 2006.285.20:42:59.14#ibcon#about to read 5, iclass 17, count 2 2006.285.20:42:59.14#ibcon#read 5, iclass 17, count 2 2006.285.20:42:59.14#ibcon#about to read 6, iclass 17, count 2 2006.285.20:42:59.14#ibcon#read 6, iclass 17, count 2 2006.285.20:42:59.14#ibcon#end of sib2, iclass 17, count 2 2006.285.20:42:59.14#ibcon#*mode == 0, iclass 17, count 2 2006.285.20:42:59.14#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.20:42:59.14#ibcon#[27=AT01-04\r\n] 2006.285.20:42:59.14#ibcon#*before write, iclass 17, count 2 2006.285.20:42:59.14#ibcon#enter sib2, iclass 17, count 2 2006.285.20:42:59.14#ibcon#flushed, iclass 17, count 2 2006.285.20:42:59.14#ibcon#about to write, iclass 17, count 2 2006.285.20:42:59.14#ibcon#wrote, iclass 17, count 2 2006.285.20:42:59.14#ibcon#about to read 3, iclass 17, count 2 2006.285.20:42:59.17#ibcon#read 3, iclass 17, count 2 2006.285.20:42:59.17#ibcon#about to read 4, iclass 17, count 2 2006.285.20:42:59.17#ibcon#read 4, iclass 17, count 2 2006.285.20:42:59.17#ibcon#about to read 5, iclass 17, count 2 2006.285.20:42:59.17#ibcon#read 5, iclass 17, count 2 2006.285.20:42:59.17#ibcon#about to read 6, iclass 17, count 2 2006.285.20:42:59.17#ibcon#read 6, iclass 17, count 2 2006.285.20:42:59.17#ibcon#end of sib2, iclass 17, count 2 2006.285.20:42:59.17#ibcon#*after write, iclass 17, count 2 2006.285.20:42:59.17#ibcon#*before return 0, iclass 17, count 2 2006.285.20:42:59.17#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:42:59.17#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:42:59.17#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.20:42:59.17#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:59.17#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:42:59.29#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:42:59.29#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:42:59.29#ibcon#enter wrdev, iclass 17, count 0 2006.285.20:42:59.29#ibcon#first serial, iclass 17, count 0 2006.285.20:42:59.29#ibcon#enter sib2, iclass 17, count 0 2006.285.20:42:59.29#ibcon#flushed, iclass 17, count 0 2006.285.20:42:59.29#ibcon#about to write, iclass 17, count 0 2006.285.20:42:59.29#ibcon#wrote, iclass 17, count 0 2006.285.20:42:59.29#ibcon#about to read 3, iclass 17, count 0 2006.285.20:42:59.31#ibcon#read 3, iclass 17, count 0 2006.285.20:42:59.31#ibcon#about to read 4, iclass 17, count 0 2006.285.20:42:59.31#ibcon#read 4, iclass 17, count 0 2006.285.20:42:59.31#ibcon#about to read 5, iclass 17, count 0 2006.285.20:42:59.31#ibcon#read 5, iclass 17, count 0 2006.285.20:42:59.31#ibcon#about to read 6, iclass 17, count 0 2006.285.20:42:59.31#ibcon#read 6, iclass 17, count 0 2006.285.20:42:59.31#ibcon#end of sib2, iclass 17, count 0 2006.285.20:42:59.31#ibcon#*mode == 0, iclass 17, count 0 2006.285.20:42:59.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.20:42:59.31#ibcon#[27=USB\r\n] 2006.285.20:42:59.31#ibcon#*before write, iclass 17, count 0 2006.285.20:42:59.31#ibcon#enter sib2, iclass 17, count 0 2006.285.20:42:59.31#ibcon#flushed, iclass 17, count 0 2006.285.20:42:59.31#ibcon#about to write, iclass 17, count 0 2006.285.20:42:59.31#ibcon#wrote, iclass 17, count 0 2006.285.20:42:59.31#ibcon#about to read 3, iclass 17, count 0 2006.285.20:42:59.34#ibcon#read 3, iclass 17, count 0 2006.285.20:42:59.34#ibcon#about to read 4, iclass 17, count 0 2006.285.20:42:59.34#ibcon#read 4, iclass 17, count 0 2006.285.20:42:59.34#ibcon#about to read 5, iclass 17, count 0 2006.285.20:42:59.34#ibcon#read 5, iclass 17, count 0 2006.285.20:42:59.34#ibcon#about to read 6, iclass 17, count 0 2006.285.20:42:59.34#ibcon#read 6, iclass 17, count 0 2006.285.20:42:59.34#ibcon#end of sib2, iclass 17, count 0 2006.285.20:42:59.34#ibcon#*after write, iclass 17, count 0 2006.285.20:42:59.34#ibcon#*before return 0, iclass 17, count 0 2006.285.20:42:59.34#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:42:59.34#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:42:59.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.20:42:59.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.20:42:59.35$vck44/vblo=2,634.99 2006.285.20:42:59.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.20:42:59.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.20:42:59.35#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:59.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:42:59.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:42:59.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:42:59.35#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:42:59.35#ibcon#first serial, iclass 19, count 0 2006.285.20:42:59.35#ibcon#enter sib2, iclass 19, count 0 2006.285.20:42:59.35#ibcon#flushed, iclass 19, count 0 2006.285.20:42:59.35#ibcon#about to write, iclass 19, count 0 2006.285.20:42:59.35#ibcon#wrote, iclass 19, count 0 2006.285.20:42:59.35#ibcon#about to read 3, iclass 19, count 0 2006.285.20:42:59.36#ibcon#read 3, iclass 19, count 0 2006.285.20:42:59.36#ibcon#about to read 4, iclass 19, count 0 2006.285.20:42:59.36#ibcon#read 4, iclass 19, count 0 2006.285.20:42:59.36#ibcon#about to read 5, iclass 19, count 0 2006.285.20:42:59.36#ibcon#read 5, iclass 19, count 0 2006.285.20:42:59.36#ibcon#about to read 6, iclass 19, count 0 2006.285.20:42:59.36#ibcon#read 6, iclass 19, count 0 2006.285.20:42:59.36#ibcon#end of sib2, iclass 19, count 0 2006.285.20:42:59.36#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:42:59.36#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:42:59.36#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.20:42:59.36#ibcon#*before write, iclass 19, count 0 2006.285.20:42:59.36#ibcon#enter sib2, iclass 19, count 0 2006.285.20:42:59.36#ibcon#flushed, iclass 19, count 0 2006.285.20:42:59.36#ibcon#about to write, iclass 19, count 0 2006.285.20:42:59.36#ibcon#wrote, iclass 19, count 0 2006.285.20:42:59.36#ibcon#about to read 3, iclass 19, count 0 2006.285.20:42:59.40#ibcon#read 3, iclass 19, count 0 2006.285.20:42:59.40#ibcon#about to read 4, iclass 19, count 0 2006.285.20:42:59.40#ibcon#read 4, iclass 19, count 0 2006.285.20:42:59.40#ibcon#about to read 5, iclass 19, count 0 2006.285.20:42:59.40#ibcon#read 5, iclass 19, count 0 2006.285.20:42:59.40#ibcon#about to read 6, iclass 19, count 0 2006.285.20:42:59.40#ibcon#read 6, iclass 19, count 0 2006.285.20:42:59.40#ibcon#end of sib2, iclass 19, count 0 2006.285.20:42:59.40#ibcon#*after write, iclass 19, count 0 2006.285.20:42:59.40#ibcon#*before return 0, iclass 19, count 0 2006.285.20:42:59.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:42:59.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:42:59.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:42:59.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:42:59.41$vck44/vb=2,5 2006.285.20:42:59.41#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.20:42:59.41#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.20:42:59.41#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:59.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:42:59.45#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:42:59.45#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:42:59.45#ibcon#enter wrdev, iclass 21, count 2 2006.285.20:42:59.45#ibcon#first serial, iclass 21, count 2 2006.285.20:42:59.45#ibcon#enter sib2, iclass 21, count 2 2006.285.20:42:59.45#ibcon#flushed, iclass 21, count 2 2006.285.20:42:59.45#ibcon#about to write, iclass 21, count 2 2006.285.20:42:59.45#ibcon#wrote, iclass 21, count 2 2006.285.20:42:59.45#ibcon#about to read 3, iclass 21, count 2 2006.285.20:42:59.47#ibcon#read 3, iclass 21, count 2 2006.285.20:42:59.47#ibcon#about to read 4, iclass 21, count 2 2006.285.20:42:59.47#ibcon#read 4, iclass 21, count 2 2006.285.20:42:59.47#ibcon#about to read 5, iclass 21, count 2 2006.285.20:42:59.47#ibcon#read 5, iclass 21, count 2 2006.285.20:42:59.47#ibcon#about to read 6, iclass 21, count 2 2006.285.20:42:59.47#ibcon#read 6, iclass 21, count 2 2006.285.20:42:59.47#ibcon#end of sib2, iclass 21, count 2 2006.285.20:42:59.47#ibcon#*mode == 0, iclass 21, count 2 2006.285.20:42:59.47#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.20:42:59.47#ibcon#[27=AT02-05\r\n] 2006.285.20:42:59.47#ibcon#*before write, iclass 21, count 2 2006.285.20:42:59.47#ibcon#enter sib2, iclass 21, count 2 2006.285.20:42:59.47#ibcon#flushed, iclass 21, count 2 2006.285.20:42:59.47#ibcon#about to write, iclass 21, count 2 2006.285.20:42:59.47#ibcon#wrote, iclass 21, count 2 2006.285.20:42:59.47#ibcon#about to read 3, iclass 21, count 2 2006.285.20:42:59.50#ibcon#read 3, iclass 21, count 2 2006.285.20:42:59.50#ibcon#about to read 4, iclass 21, count 2 2006.285.20:42:59.50#ibcon#read 4, iclass 21, count 2 2006.285.20:42:59.50#ibcon#about to read 5, iclass 21, count 2 2006.285.20:42:59.50#ibcon#read 5, iclass 21, count 2 2006.285.20:42:59.50#ibcon#about to read 6, iclass 21, count 2 2006.285.20:42:59.50#ibcon#read 6, iclass 21, count 2 2006.285.20:42:59.50#ibcon#end of sib2, iclass 21, count 2 2006.285.20:42:59.50#ibcon#*after write, iclass 21, count 2 2006.285.20:42:59.50#ibcon#*before return 0, iclass 21, count 2 2006.285.20:42:59.50#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:42:59.50#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:42:59.50#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.20:42:59.50#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:59.50#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:42:59.62#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:42:59.62#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:42:59.62#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:42:59.62#ibcon#first serial, iclass 21, count 0 2006.285.20:42:59.62#ibcon#enter sib2, iclass 21, count 0 2006.285.20:42:59.62#ibcon#flushed, iclass 21, count 0 2006.285.20:42:59.62#ibcon#about to write, iclass 21, count 0 2006.285.20:42:59.62#ibcon#wrote, iclass 21, count 0 2006.285.20:42:59.62#ibcon#about to read 3, iclass 21, count 0 2006.285.20:42:59.64#ibcon#read 3, iclass 21, count 0 2006.285.20:42:59.64#ibcon#about to read 4, iclass 21, count 0 2006.285.20:42:59.64#ibcon#read 4, iclass 21, count 0 2006.285.20:42:59.64#ibcon#about to read 5, iclass 21, count 0 2006.285.20:42:59.64#ibcon#read 5, iclass 21, count 0 2006.285.20:42:59.64#ibcon#about to read 6, iclass 21, count 0 2006.285.20:42:59.64#ibcon#read 6, iclass 21, count 0 2006.285.20:42:59.64#ibcon#end of sib2, iclass 21, count 0 2006.285.20:42:59.64#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:42:59.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:42:59.64#ibcon#[27=USB\r\n] 2006.285.20:42:59.64#ibcon#*before write, iclass 21, count 0 2006.285.20:42:59.64#ibcon#enter sib2, iclass 21, count 0 2006.285.20:42:59.64#ibcon#flushed, iclass 21, count 0 2006.285.20:42:59.64#ibcon#about to write, iclass 21, count 0 2006.285.20:42:59.64#ibcon#wrote, iclass 21, count 0 2006.285.20:42:59.64#ibcon#about to read 3, iclass 21, count 0 2006.285.20:42:59.67#ibcon#read 3, iclass 21, count 0 2006.285.20:42:59.67#ibcon#about to read 4, iclass 21, count 0 2006.285.20:42:59.67#ibcon#read 4, iclass 21, count 0 2006.285.20:42:59.67#ibcon#about to read 5, iclass 21, count 0 2006.285.20:42:59.67#ibcon#read 5, iclass 21, count 0 2006.285.20:42:59.67#ibcon#about to read 6, iclass 21, count 0 2006.285.20:42:59.67#ibcon#read 6, iclass 21, count 0 2006.285.20:42:59.67#ibcon#end of sib2, iclass 21, count 0 2006.285.20:42:59.67#ibcon#*after write, iclass 21, count 0 2006.285.20:42:59.67#ibcon#*before return 0, iclass 21, count 0 2006.285.20:42:59.67#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:42:59.67#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:42:59.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:42:59.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:42:59.68$vck44/vblo=3,649.99 2006.285.20:42:59.68#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.20:42:59.68#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.20:42:59.68#ibcon#ireg 17 cls_cnt 0 2006.285.20:42:59.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:42:59.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:42:59.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:42:59.68#ibcon#enter wrdev, iclass 23, count 0 2006.285.20:42:59.68#ibcon#first serial, iclass 23, count 0 2006.285.20:42:59.68#ibcon#enter sib2, iclass 23, count 0 2006.285.20:42:59.68#ibcon#flushed, iclass 23, count 0 2006.285.20:42:59.68#ibcon#about to write, iclass 23, count 0 2006.285.20:42:59.68#ibcon#wrote, iclass 23, count 0 2006.285.20:42:59.68#ibcon#about to read 3, iclass 23, count 0 2006.285.20:42:59.69#ibcon#read 3, iclass 23, count 0 2006.285.20:42:59.78#ibcon#about to read 4, iclass 23, count 0 2006.285.20:42:59.78#ibcon#read 4, iclass 23, count 0 2006.285.20:42:59.78#ibcon#about to read 5, iclass 23, count 0 2006.285.20:42:59.78#ibcon#read 5, iclass 23, count 0 2006.285.20:42:59.78#ibcon#about to read 6, iclass 23, count 0 2006.285.20:42:59.78#ibcon#read 6, iclass 23, count 0 2006.285.20:42:59.78#ibcon#end of sib2, iclass 23, count 0 2006.285.20:42:59.78#ibcon#*mode == 0, iclass 23, count 0 2006.285.20:42:59.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.20:42:59.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.20:42:59.78#ibcon#*before write, iclass 23, count 0 2006.285.20:42:59.78#ibcon#enter sib2, iclass 23, count 0 2006.285.20:42:59.78#ibcon#flushed, iclass 23, count 0 2006.285.20:42:59.78#ibcon#about to write, iclass 23, count 0 2006.285.20:42:59.78#ibcon#wrote, iclass 23, count 0 2006.285.20:42:59.78#ibcon#about to read 3, iclass 23, count 0 2006.285.20:42:59.82#ibcon#read 3, iclass 23, count 0 2006.285.20:42:59.82#ibcon#about to read 4, iclass 23, count 0 2006.285.20:42:59.82#ibcon#read 4, iclass 23, count 0 2006.285.20:42:59.82#ibcon#about to read 5, iclass 23, count 0 2006.285.20:42:59.82#ibcon#read 5, iclass 23, count 0 2006.285.20:42:59.82#ibcon#about to read 6, iclass 23, count 0 2006.285.20:42:59.82#ibcon#read 6, iclass 23, count 0 2006.285.20:42:59.82#ibcon#end of sib2, iclass 23, count 0 2006.285.20:42:59.82#ibcon#*after write, iclass 23, count 0 2006.285.20:42:59.82#ibcon#*before return 0, iclass 23, count 0 2006.285.20:42:59.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:42:59.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:42:59.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.20:42:59.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.20:42:59.83$vck44/vb=3,4 2006.285.20:42:59.83#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.20:42:59.83#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.20:42:59.83#ibcon#ireg 11 cls_cnt 2 2006.285.20:42:59.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:42:59.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:42:59.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:42:59.83#ibcon#enter wrdev, iclass 25, count 2 2006.285.20:42:59.83#ibcon#first serial, iclass 25, count 2 2006.285.20:42:59.83#ibcon#enter sib2, iclass 25, count 2 2006.285.20:42:59.83#ibcon#flushed, iclass 25, count 2 2006.285.20:42:59.83#ibcon#about to write, iclass 25, count 2 2006.285.20:42:59.83#ibcon#wrote, iclass 25, count 2 2006.285.20:42:59.83#ibcon#about to read 3, iclass 25, count 2 2006.285.20:42:59.84#ibcon#read 3, iclass 25, count 2 2006.285.20:42:59.84#ibcon#about to read 4, iclass 25, count 2 2006.285.20:42:59.84#ibcon#read 4, iclass 25, count 2 2006.285.20:42:59.84#ibcon#about to read 5, iclass 25, count 2 2006.285.20:42:59.84#ibcon#read 5, iclass 25, count 2 2006.285.20:42:59.84#ibcon#about to read 6, iclass 25, count 2 2006.285.20:42:59.84#ibcon#read 6, iclass 25, count 2 2006.285.20:42:59.84#ibcon#end of sib2, iclass 25, count 2 2006.285.20:42:59.84#ibcon#*mode == 0, iclass 25, count 2 2006.285.20:42:59.84#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.20:42:59.84#ibcon#[27=AT03-04\r\n] 2006.285.20:42:59.84#ibcon#*before write, iclass 25, count 2 2006.285.20:42:59.84#ibcon#enter sib2, iclass 25, count 2 2006.285.20:42:59.84#ibcon#flushed, iclass 25, count 2 2006.285.20:42:59.84#ibcon#about to write, iclass 25, count 2 2006.285.20:42:59.84#ibcon#wrote, iclass 25, count 2 2006.285.20:42:59.84#ibcon#about to read 3, iclass 25, count 2 2006.285.20:42:59.87#ibcon#read 3, iclass 25, count 2 2006.285.20:42:59.87#ibcon#about to read 4, iclass 25, count 2 2006.285.20:42:59.87#ibcon#read 4, iclass 25, count 2 2006.285.20:42:59.87#ibcon#about to read 5, iclass 25, count 2 2006.285.20:42:59.87#ibcon#read 5, iclass 25, count 2 2006.285.20:42:59.87#ibcon#about to read 6, iclass 25, count 2 2006.285.20:42:59.87#ibcon#read 6, iclass 25, count 2 2006.285.20:42:59.87#ibcon#end of sib2, iclass 25, count 2 2006.285.20:42:59.87#ibcon#*after write, iclass 25, count 2 2006.285.20:42:59.87#ibcon#*before return 0, iclass 25, count 2 2006.285.20:42:59.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:42:59.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:42:59.87#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.20:42:59.87#ibcon#ireg 7 cls_cnt 0 2006.285.20:42:59.87#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:42:59.99#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:42:59.99#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:42:59.99#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:42:59.99#ibcon#first serial, iclass 25, count 0 2006.285.20:42:59.99#ibcon#enter sib2, iclass 25, count 0 2006.285.20:42:59.99#ibcon#flushed, iclass 25, count 0 2006.285.20:42:59.99#ibcon#about to write, iclass 25, count 0 2006.285.20:42:59.99#ibcon#wrote, iclass 25, count 0 2006.285.20:42:59.99#ibcon#about to read 3, iclass 25, count 0 2006.285.20:43:00.01#ibcon#read 3, iclass 25, count 0 2006.285.20:43:00.01#ibcon#about to read 4, iclass 25, count 0 2006.285.20:43:00.01#ibcon#read 4, iclass 25, count 0 2006.285.20:43:00.01#ibcon#about to read 5, iclass 25, count 0 2006.285.20:43:00.01#ibcon#read 5, iclass 25, count 0 2006.285.20:43:00.01#ibcon#about to read 6, iclass 25, count 0 2006.285.20:43:00.01#ibcon#read 6, iclass 25, count 0 2006.285.20:43:00.01#ibcon#end of sib2, iclass 25, count 0 2006.285.20:43:00.01#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:43:00.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:43:00.01#ibcon#[27=USB\r\n] 2006.285.20:43:00.01#ibcon#*before write, iclass 25, count 0 2006.285.20:43:00.01#ibcon#enter sib2, iclass 25, count 0 2006.285.20:43:00.01#ibcon#flushed, iclass 25, count 0 2006.285.20:43:00.01#ibcon#about to write, iclass 25, count 0 2006.285.20:43:00.01#ibcon#wrote, iclass 25, count 0 2006.285.20:43:00.01#ibcon#about to read 3, iclass 25, count 0 2006.285.20:43:00.04#ibcon#read 3, iclass 25, count 0 2006.285.20:43:00.04#ibcon#about to read 4, iclass 25, count 0 2006.285.20:43:00.04#ibcon#read 4, iclass 25, count 0 2006.285.20:43:00.04#ibcon#about to read 5, iclass 25, count 0 2006.285.20:43:00.04#ibcon#read 5, iclass 25, count 0 2006.285.20:43:00.04#ibcon#about to read 6, iclass 25, count 0 2006.285.20:43:00.04#ibcon#read 6, iclass 25, count 0 2006.285.20:43:00.04#ibcon#end of sib2, iclass 25, count 0 2006.285.20:43:00.04#ibcon#*after write, iclass 25, count 0 2006.285.20:43:00.04#ibcon#*before return 0, iclass 25, count 0 2006.285.20:43:00.04#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:43:00.04#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:43:00.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:43:00.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:43:00.05$vck44/vblo=4,679.99 2006.285.20:43:00.05#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.20:43:00.05#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.20:43:00.05#ibcon#ireg 17 cls_cnt 0 2006.285.20:43:00.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:43:00.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:43:00.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:43:00.05#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:43:00.05#ibcon#first serial, iclass 27, count 0 2006.285.20:43:00.05#ibcon#enter sib2, iclass 27, count 0 2006.285.20:43:00.05#ibcon#flushed, iclass 27, count 0 2006.285.20:43:00.05#ibcon#about to write, iclass 27, count 0 2006.285.20:43:00.05#ibcon#wrote, iclass 27, count 0 2006.285.20:43:00.05#ibcon#about to read 3, iclass 27, count 0 2006.285.20:43:00.06#ibcon#read 3, iclass 27, count 0 2006.285.20:43:00.06#ibcon#about to read 4, iclass 27, count 0 2006.285.20:43:00.06#ibcon#read 4, iclass 27, count 0 2006.285.20:43:00.06#ibcon#about to read 5, iclass 27, count 0 2006.285.20:43:00.06#ibcon#read 5, iclass 27, count 0 2006.285.20:43:00.06#ibcon#about to read 6, iclass 27, count 0 2006.285.20:43:00.06#ibcon#read 6, iclass 27, count 0 2006.285.20:43:00.06#ibcon#end of sib2, iclass 27, count 0 2006.285.20:43:00.06#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:43:00.06#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:43:00.06#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.20:43:00.06#ibcon#*before write, iclass 27, count 0 2006.285.20:43:00.06#ibcon#enter sib2, iclass 27, count 0 2006.285.20:43:00.06#ibcon#flushed, iclass 27, count 0 2006.285.20:43:00.06#ibcon#about to write, iclass 27, count 0 2006.285.20:43:00.06#ibcon#wrote, iclass 27, count 0 2006.285.20:43:00.06#ibcon#about to read 3, iclass 27, count 0 2006.285.20:43:00.10#ibcon#read 3, iclass 27, count 0 2006.285.20:43:00.10#ibcon#about to read 4, iclass 27, count 0 2006.285.20:43:00.10#ibcon#read 4, iclass 27, count 0 2006.285.20:43:00.10#ibcon#about to read 5, iclass 27, count 0 2006.285.20:43:00.10#ibcon#read 5, iclass 27, count 0 2006.285.20:43:00.10#ibcon#about to read 6, iclass 27, count 0 2006.285.20:43:00.10#ibcon#read 6, iclass 27, count 0 2006.285.20:43:00.10#ibcon#end of sib2, iclass 27, count 0 2006.285.20:43:00.10#ibcon#*after write, iclass 27, count 0 2006.285.20:43:00.10#ibcon#*before return 0, iclass 27, count 0 2006.285.20:43:00.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:43:00.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:43:00.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:43:00.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:43:00.11$vck44/vb=4,5 2006.285.20:43:00.11#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.20:43:00.11#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.20:43:00.11#ibcon#ireg 11 cls_cnt 2 2006.285.20:43:00.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:43:00.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:43:00.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:43:00.15#ibcon#enter wrdev, iclass 29, count 2 2006.285.20:43:00.15#ibcon#first serial, iclass 29, count 2 2006.285.20:43:00.15#ibcon#enter sib2, iclass 29, count 2 2006.285.20:43:00.15#ibcon#flushed, iclass 29, count 2 2006.285.20:43:00.15#ibcon#about to write, iclass 29, count 2 2006.285.20:43:00.15#ibcon#wrote, iclass 29, count 2 2006.285.20:43:00.15#ibcon#about to read 3, iclass 29, count 2 2006.285.20:43:00.17#ibcon#read 3, iclass 29, count 2 2006.285.20:43:00.17#ibcon#about to read 4, iclass 29, count 2 2006.285.20:43:00.17#ibcon#read 4, iclass 29, count 2 2006.285.20:43:00.17#ibcon#about to read 5, iclass 29, count 2 2006.285.20:43:00.17#ibcon#read 5, iclass 29, count 2 2006.285.20:43:00.17#ibcon#about to read 6, iclass 29, count 2 2006.285.20:43:00.17#ibcon#read 6, iclass 29, count 2 2006.285.20:43:00.17#ibcon#end of sib2, iclass 29, count 2 2006.285.20:43:00.17#ibcon#*mode == 0, iclass 29, count 2 2006.285.20:43:00.17#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.20:43:00.17#ibcon#[27=AT04-05\r\n] 2006.285.20:43:00.17#ibcon#*before write, iclass 29, count 2 2006.285.20:43:00.17#ibcon#enter sib2, iclass 29, count 2 2006.285.20:43:00.17#ibcon#flushed, iclass 29, count 2 2006.285.20:43:00.17#ibcon#about to write, iclass 29, count 2 2006.285.20:43:00.17#ibcon#wrote, iclass 29, count 2 2006.285.20:43:00.17#ibcon#about to read 3, iclass 29, count 2 2006.285.20:43:00.20#ibcon#read 3, iclass 29, count 2 2006.285.20:43:00.20#ibcon#about to read 4, iclass 29, count 2 2006.285.20:43:00.20#ibcon#read 4, iclass 29, count 2 2006.285.20:43:00.20#ibcon#about to read 5, iclass 29, count 2 2006.285.20:43:00.20#ibcon#read 5, iclass 29, count 2 2006.285.20:43:00.20#ibcon#about to read 6, iclass 29, count 2 2006.285.20:43:00.20#ibcon#read 6, iclass 29, count 2 2006.285.20:43:00.20#ibcon#end of sib2, iclass 29, count 2 2006.285.20:43:00.20#ibcon#*after write, iclass 29, count 2 2006.285.20:43:00.20#ibcon#*before return 0, iclass 29, count 2 2006.285.20:43:00.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:43:00.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:43:00.20#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.20:43:00.20#ibcon#ireg 7 cls_cnt 0 2006.285.20:43:00.20#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:43:00.32#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:43:00.32#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:43:00.32#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:43:00.32#ibcon#first serial, iclass 29, count 0 2006.285.20:43:00.32#ibcon#enter sib2, iclass 29, count 0 2006.285.20:43:00.32#ibcon#flushed, iclass 29, count 0 2006.285.20:43:00.32#ibcon#about to write, iclass 29, count 0 2006.285.20:43:00.32#ibcon#wrote, iclass 29, count 0 2006.285.20:43:00.32#ibcon#about to read 3, iclass 29, count 0 2006.285.20:43:00.34#ibcon#read 3, iclass 29, count 0 2006.285.20:43:00.34#ibcon#about to read 4, iclass 29, count 0 2006.285.20:43:00.34#ibcon#read 4, iclass 29, count 0 2006.285.20:43:00.34#ibcon#about to read 5, iclass 29, count 0 2006.285.20:43:00.34#ibcon#read 5, iclass 29, count 0 2006.285.20:43:00.34#ibcon#about to read 6, iclass 29, count 0 2006.285.20:43:00.34#ibcon#read 6, iclass 29, count 0 2006.285.20:43:00.34#ibcon#end of sib2, iclass 29, count 0 2006.285.20:43:00.34#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:43:00.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:43:00.34#ibcon#[27=USB\r\n] 2006.285.20:43:00.34#ibcon#*before write, iclass 29, count 0 2006.285.20:43:00.34#ibcon#enter sib2, iclass 29, count 0 2006.285.20:43:00.34#ibcon#flushed, iclass 29, count 0 2006.285.20:43:00.34#ibcon#about to write, iclass 29, count 0 2006.285.20:43:00.34#ibcon#wrote, iclass 29, count 0 2006.285.20:43:00.34#ibcon#about to read 3, iclass 29, count 0 2006.285.20:43:00.37#ibcon#read 3, iclass 29, count 0 2006.285.20:43:00.37#ibcon#about to read 4, iclass 29, count 0 2006.285.20:43:00.37#ibcon#read 4, iclass 29, count 0 2006.285.20:43:00.37#ibcon#about to read 5, iclass 29, count 0 2006.285.20:43:00.37#ibcon#read 5, iclass 29, count 0 2006.285.20:43:00.37#ibcon#about to read 6, iclass 29, count 0 2006.285.20:43:00.37#ibcon#read 6, iclass 29, count 0 2006.285.20:43:00.37#ibcon#end of sib2, iclass 29, count 0 2006.285.20:43:00.37#ibcon#*after write, iclass 29, count 0 2006.285.20:43:00.37#ibcon#*before return 0, iclass 29, count 0 2006.285.20:43:00.37#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:43:00.37#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:43:00.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:43:00.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:43:00.38$vck44/vblo=5,709.99 2006.285.20:43:00.38#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.20:43:00.38#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.20:43:00.38#ibcon#ireg 17 cls_cnt 0 2006.285.20:43:00.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:43:00.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:43:00.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:43:00.38#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:43:00.38#ibcon#first serial, iclass 31, count 0 2006.285.20:43:00.38#ibcon#enter sib2, iclass 31, count 0 2006.285.20:43:00.38#ibcon#flushed, iclass 31, count 0 2006.285.20:43:00.38#ibcon#about to write, iclass 31, count 0 2006.285.20:43:00.38#ibcon#wrote, iclass 31, count 0 2006.285.20:43:00.38#ibcon#about to read 3, iclass 31, count 0 2006.285.20:43:00.39#ibcon#read 3, iclass 31, count 0 2006.285.20:43:00.39#ibcon#about to read 4, iclass 31, count 0 2006.285.20:43:00.39#ibcon#read 4, iclass 31, count 0 2006.285.20:43:00.39#ibcon#about to read 5, iclass 31, count 0 2006.285.20:43:00.39#ibcon#read 5, iclass 31, count 0 2006.285.20:43:00.39#ibcon#about to read 6, iclass 31, count 0 2006.285.20:43:00.39#ibcon#read 6, iclass 31, count 0 2006.285.20:43:00.39#ibcon#end of sib2, iclass 31, count 0 2006.285.20:43:00.39#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:43:00.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:43:00.39#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.20:43:00.39#ibcon#*before write, iclass 31, count 0 2006.285.20:43:00.39#ibcon#enter sib2, iclass 31, count 0 2006.285.20:43:00.39#ibcon#flushed, iclass 31, count 0 2006.285.20:43:00.39#ibcon#about to write, iclass 31, count 0 2006.285.20:43:00.39#ibcon#wrote, iclass 31, count 0 2006.285.20:43:00.39#ibcon#about to read 3, iclass 31, count 0 2006.285.20:43:00.43#ibcon#read 3, iclass 31, count 0 2006.285.20:43:00.43#ibcon#about to read 4, iclass 31, count 0 2006.285.20:43:00.43#ibcon#read 4, iclass 31, count 0 2006.285.20:43:00.43#ibcon#about to read 5, iclass 31, count 0 2006.285.20:43:00.43#ibcon#read 5, iclass 31, count 0 2006.285.20:43:00.43#ibcon#about to read 6, iclass 31, count 0 2006.285.20:43:00.43#ibcon#read 6, iclass 31, count 0 2006.285.20:43:00.43#ibcon#end of sib2, iclass 31, count 0 2006.285.20:43:00.43#ibcon#*after write, iclass 31, count 0 2006.285.20:43:00.43#ibcon#*before return 0, iclass 31, count 0 2006.285.20:43:00.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:43:00.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:43:00.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:43:00.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:43:00.44$vck44/vb=5,4 2006.285.20:43:00.44#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.20:43:00.44#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.20:43:00.44#ibcon#ireg 11 cls_cnt 2 2006.285.20:43:00.44#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:43:00.48#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:43:00.48#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:43:00.48#ibcon#enter wrdev, iclass 33, count 2 2006.285.20:43:00.48#ibcon#first serial, iclass 33, count 2 2006.285.20:43:00.48#ibcon#enter sib2, iclass 33, count 2 2006.285.20:43:00.48#ibcon#flushed, iclass 33, count 2 2006.285.20:43:00.48#ibcon#about to write, iclass 33, count 2 2006.285.20:43:00.48#ibcon#wrote, iclass 33, count 2 2006.285.20:43:00.48#ibcon#about to read 3, iclass 33, count 2 2006.285.20:43:00.50#ibcon#read 3, iclass 33, count 2 2006.285.20:43:00.50#ibcon#about to read 4, iclass 33, count 2 2006.285.20:43:00.50#ibcon#read 4, iclass 33, count 2 2006.285.20:43:00.50#ibcon#about to read 5, iclass 33, count 2 2006.285.20:43:00.50#ibcon#read 5, iclass 33, count 2 2006.285.20:43:00.50#ibcon#about to read 6, iclass 33, count 2 2006.285.20:43:00.50#ibcon#read 6, iclass 33, count 2 2006.285.20:43:00.50#ibcon#end of sib2, iclass 33, count 2 2006.285.20:43:00.50#ibcon#*mode == 0, iclass 33, count 2 2006.285.20:43:00.50#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.20:43:00.50#ibcon#[27=AT05-04\r\n] 2006.285.20:43:00.50#ibcon#*before write, iclass 33, count 2 2006.285.20:43:00.50#ibcon#enter sib2, iclass 33, count 2 2006.285.20:43:00.50#ibcon#flushed, iclass 33, count 2 2006.285.20:43:00.50#ibcon#about to write, iclass 33, count 2 2006.285.20:43:00.50#ibcon#wrote, iclass 33, count 2 2006.285.20:43:00.50#ibcon#about to read 3, iclass 33, count 2 2006.285.20:43:00.53#ibcon#read 3, iclass 33, count 2 2006.285.20:43:00.53#ibcon#about to read 4, iclass 33, count 2 2006.285.20:43:00.53#ibcon#read 4, iclass 33, count 2 2006.285.20:43:00.53#ibcon#about to read 5, iclass 33, count 2 2006.285.20:43:00.53#ibcon#read 5, iclass 33, count 2 2006.285.20:43:00.53#ibcon#about to read 6, iclass 33, count 2 2006.285.20:43:00.53#ibcon#read 6, iclass 33, count 2 2006.285.20:43:00.53#ibcon#end of sib2, iclass 33, count 2 2006.285.20:43:00.53#ibcon#*after write, iclass 33, count 2 2006.285.20:43:00.53#ibcon#*before return 0, iclass 33, count 2 2006.285.20:43:00.53#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:43:00.53#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:43:00.53#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.20:43:00.53#ibcon#ireg 7 cls_cnt 0 2006.285.20:43:00.53#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:43:00.65#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:43:00.65#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:43:00.65#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:43:00.65#ibcon#first serial, iclass 33, count 0 2006.285.20:43:00.65#ibcon#enter sib2, iclass 33, count 0 2006.285.20:43:00.65#ibcon#flushed, iclass 33, count 0 2006.285.20:43:00.65#ibcon#about to write, iclass 33, count 0 2006.285.20:43:00.65#ibcon#wrote, iclass 33, count 0 2006.285.20:43:00.65#ibcon#about to read 3, iclass 33, count 0 2006.285.20:43:00.67#ibcon#read 3, iclass 33, count 0 2006.285.20:43:00.67#ibcon#about to read 4, iclass 33, count 0 2006.285.20:43:00.67#ibcon#read 4, iclass 33, count 0 2006.285.20:43:00.67#ibcon#about to read 5, iclass 33, count 0 2006.285.20:43:00.67#ibcon#read 5, iclass 33, count 0 2006.285.20:43:00.67#ibcon#about to read 6, iclass 33, count 0 2006.285.20:43:00.67#ibcon#read 6, iclass 33, count 0 2006.285.20:43:00.67#ibcon#end of sib2, iclass 33, count 0 2006.285.20:43:00.67#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:43:00.67#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:43:00.67#ibcon#[27=USB\r\n] 2006.285.20:43:00.67#ibcon#*before write, iclass 33, count 0 2006.285.20:43:00.67#ibcon#enter sib2, iclass 33, count 0 2006.285.20:43:00.67#ibcon#flushed, iclass 33, count 0 2006.285.20:43:00.67#ibcon#about to write, iclass 33, count 0 2006.285.20:43:00.67#ibcon#wrote, iclass 33, count 0 2006.285.20:43:00.67#ibcon#about to read 3, iclass 33, count 0 2006.285.20:43:00.70#ibcon#read 3, iclass 33, count 0 2006.285.20:43:00.70#ibcon#about to read 4, iclass 33, count 0 2006.285.20:43:00.70#ibcon#read 4, iclass 33, count 0 2006.285.20:43:00.70#ibcon#about to read 5, iclass 33, count 0 2006.285.20:43:00.70#ibcon#read 5, iclass 33, count 0 2006.285.20:43:00.70#ibcon#about to read 6, iclass 33, count 0 2006.285.20:43:00.70#ibcon#read 6, iclass 33, count 0 2006.285.20:43:00.70#ibcon#end of sib2, iclass 33, count 0 2006.285.20:43:00.70#ibcon#*after write, iclass 33, count 0 2006.285.20:43:00.70#ibcon#*before return 0, iclass 33, count 0 2006.285.20:43:00.70#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:43:00.70#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:43:00.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:43:00.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:43:00.71$vck44/vblo=6,719.99 2006.285.20:43:00.71#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.20:43:00.71#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.20:43:00.71#ibcon#ireg 17 cls_cnt 0 2006.285.20:43:00.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:43:00.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:43:00.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:43:00.71#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:43:00.71#ibcon#first serial, iclass 35, count 0 2006.285.20:43:00.71#ibcon#enter sib2, iclass 35, count 0 2006.285.20:43:00.71#ibcon#flushed, iclass 35, count 0 2006.285.20:43:00.71#ibcon#about to write, iclass 35, count 0 2006.285.20:43:00.71#ibcon#wrote, iclass 35, count 0 2006.285.20:43:00.71#ibcon#about to read 3, iclass 35, count 0 2006.285.20:43:00.72#ibcon#read 3, iclass 35, count 0 2006.285.20:43:00.86#ibcon#about to read 4, iclass 35, count 0 2006.285.20:43:00.86#ibcon#read 4, iclass 35, count 0 2006.285.20:43:00.86#ibcon#about to read 5, iclass 35, count 0 2006.285.20:43:00.86#ibcon#read 5, iclass 35, count 0 2006.285.20:43:00.86#ibcon#about to read 6, iclass 35, count 0 2006.285.20:43:00.86#ibcon#read 6, iclass 35, count 0 2006.285.20:43:00.86#ibcon#end of sib2, iclass 35, count 0 2006.285.20:43:00.86#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:43:00.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:43:00.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.20:43:00.86#ibcon#*before write, iclass 35, count 0 2006.285.20:43:00.86#ibcon#enter sib2, iclass 35, count 0 2006.285.20:43:00.86#ibcon#flushed, iclass 35, count 0 2006.285.20:43:00.86#ibcon#about to write, iclass 35, count 0 2006.285.20:43:00.86#ibcon#wrote, iclass 35, count 0 2006.285.20:43:00.86#ibcon#about to read 3, iclass 35, count 0 2006.285.20:43:00.90#ibcon#read 3, iclass 35, count 0 2006.285.20:43:00.90#ibcon#about to read 4, iclass 35, count 0 2006.285.20:43:00.90#ibcon#read 4, iclass 35, count 0 2006.285.20:43:00.90#ibcon#about to read 5, iclass 35, count 0 2006.285.20:43:00.90#ibcon#read 5, iclass 35, count 0 2006.285.20:43:00.90#ibcon#about to read 6, iclass 35, count 0 2006.285.20:43:00.90#ibcon#read 6, iclass 35, count 0 2006.285.20:43:00.90#ibcon#end of sib2, iclass 35, count 0 2006.285.20:43:00.90#ibcon#*after write, iclass 35, count 0 2006.285.20:43:00.90#ibcon#*before return 0, iclass 35, count 0 2006.285.20:43:00.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:43:00.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:43:00.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:43:00.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:43:00.91$vck44/vb=6,3 2006.285.20:43:00.91#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.20:43:00.91#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.20:43:00.91#ibcon#ireg 11 cls_cnt 2 2006.285.20:43:00.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:43:00.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:43:00.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:43:00.91#ibcon#enter wrdev, iclass 37, count 2 2006.285.20:43:00.91#ibcon#first serial, iclass 37, count 2 2006.285.20:43:00.91#ibcon#enter sib2, iclass 37, count 2 2006.285.20:43:00.91#ibcon#flushed, iclass 37, count 2 2006.285.20:43:00.91#ibcon#about to write, iclass 37, count 2 2006.285.20:43:00.91#ibcon#wrote, iclass 37, count 2 2006.285.20:43:00.91#ibcon#about to read 3, iclass 37, count 2 2006.285.20:43:00.92#ibcon#read 3, iclass 37, count 2 2006.285.20:43:00.92#ibcon#about to read 4, iclass 37, count 2 2006.285.20:43:00.92#ibcon#read 4, iclass 37, count 2 2006.285.20:43:00.92#ibcon#about to read 5, iclass 37, count 2 2006.285.20:43:00.92#ibcon#read 5, iclass 37, count 2 2006.285.20:43:00.92#ibcon#about to read 6, iclass 37, count 2 2006.285.20:43:00.92#ibcon#read 6, iclass 37, count 2 2006.285.20:43:00.92#ibcon#end of sib2, iclass 37, count 2 2006.285.20:43:00.92#ibcon#*mode == 0, iclass 37, count 2 2006.285.20:43:00.92#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.20:43:00.92#ibcon#[27=AT06-03\r\n] 2006.285.20:43:00.92#ibcon#*before write, iclass 37, count 2 2006.285.20:43:00.92#ibcon#enter sib2, iclass 37, count 2 2006.285.20:43:00.92#ibcon#flushed, iclass 37, count 2 2006.285.20:43:00.92#ibcon#about to write, iclass 37, count 2 2006.285.20:43:00.92#ibcon#wrote, iclass 37, count 2 2006.285.20:43:00.92#ibcon#about to read 3, iclass 37, count 2 2006.285.20:43:00.95#ibcon#read 3, iclass 37, count 2 2006.285.20:43:00.95#ibcon#about to read 4, iclass 37, count 2 2006.285.20:43:00.95#ibcon#read 4, iclass 37, count 2 2006.285.20:43:00.95#ibcon#about to read 5, iclass 37, count 2 2006.285.20:43:00.95#ibcon#read 5, iclass 37, count 2 2006.285.20:43:00.95#ibcon#about to read 6, iclass 37, count 2 2006.285.20:43:00.95#ibcon#read 6, iclass 37, count 2 2006.285.20:43:00.95#ibcon#end of sib2, iclass 37, count 2 2006.285.20:43:00.95#ibcon#*after write, iclass 37, count 2 2006.285.20:43:00.95#ibcon#*before return 0, iclass 37, count 2 2006.285.20:43:00.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:43:00.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:43:00.95#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.20:43:00.95#ibcon#ireg 7 cls_cnt 0 2006.285.20:43:00.95#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:43:01.07#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:43:01.07#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:43:01.07#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:43:01.07#ibcon#first serial, iclass 37, count 0 2006.285.20:43:01.07#ibcon#enter sib2, iclass 37, count 0 2006.285.20:43:01.07#ibcon#flushed, iclass 37, count 0 2006.285.20:43:01.07#ibcon#about to write, iclass 37, count 0 2006.285.20:43:01.07#ibcon#wrote, iclass 37, count 0 2006.285.20:43:01.07#ibcon#about to read 3, iclass 37, count 0 2006.285.20:43:01.09#ibcon#read 3, iclass 37, count 0 2006.285.20:43:01.09#ibcon#about to read 4, iclass 37, count 0 2006.285.20:43:01.09#ibcon#read 4, iclass 37, count 0 2006.285.20:43:01.09#ibcon#about to read 5, iclass 37, count 0 2006.285.20:43:01.09#ibcon#read 5, iclass 37, count 0 2006.285.20:43:01.09#ibcon#about to read 6, iclass 37, count 0 2006.285.20:43:01.09#ibcon#read 6, iclass 37, count 0 2006.285.20:43:01.09#ibcon#end of sib2, iclass 37, count 0 2006.285.20:43:01.09#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:43:01.09#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:43:01.09#ibcon#[27=USB\r\n] 2006.285.20:43:01.09#ibcon#*before write, iclass 37, count 0 2006.285.20:43:01.09#ibcon#enter sib2, iclass 37, count 0 2006.285.20:43:01.09#ibcon#flushed, iclass 37, count 0 2006.285.20:43:01.09#ibcon#about to write, iclass 37, count 0 2006.285.20:43:01.09#ibcon#wrote, iclass 37, count 0 2006.285.20:43:01.09#ibcon#about to read 3, iclass 37, count 0 2006.285.20:43:01.12#ibcon#read 3, iclass 37, count 0 2006.285.20:43:01.12#ibcon#about to read 4, iclass 37, count 0 2006.285.20:43:01.12#ibcon#read 4, iclass 37, count 0 2006.285.20:43:01.12#ibcon#about to read 5, iclass 37, count 0 2006.285.20:43:01.12#ibcon#read 5, iclass 37, count 0 2006.285.20:43:01.12#ibcon#about to read 6, iclass 37, count 0 2006.285.20:43:01.12#ibcon#read 6, iclass 37, count 0 2006.285.20:43:01.12#ibcon#end of sib2, iclass 37, count 0 2006.285.20:43:01.12#ibcon#*after write, iclass 37, count 0 2006.285.20:43:01.12#ibcon#*before return 0, iclass 37, count 0 2006.285.20:43:01.12#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:43:01.12#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:43:01.12#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:43:01.12#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:43:01.13$vck44/vblo=7,734.99 2006.285.20:43:01.13#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.20:43:01.13#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.20:43:01.13#ibcon#ireg 17 cls_cnt 0 2006.285.20:43:01.13#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:43:01.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:43:01.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:43:01.13#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:43:01.13#ibcon#first serial, iclass 39, count 0 2006.285.20:43:01.13#ibcon#enter sib2, iclass 39, count 0 2006.285.20:43:01.13#ibcon#flushed, iclass 39, count 0 2006.285.20:43:01.13#ibcon#about to write, iclass 39, count 0 2006.285.20:43:01.13#ibcon#wrote, iclass 39, count 0 2006.285.20:43:01.13#ibcon#about to read 3, iclass 39, count 0 2006.285.20:43:01.14#ibcon#read 3, iclass 39, count 0 2006.285.20:43:01.14#ibcon#about to read 4, iclass 39, count 0 2006.285.20:43:01.14#ibcon#read 4, iclass 39, count 0 2006.285.20:43:01.14#ibcon#about to read 5, iclass 39, count 0 2006.285.20:43:01.14#ibcon#read 5, iclass 39, count 0 2006.285.20:43:01.14#ibcon#about to read 6, iclass 39, count 0 2006.285.20:43:01.14#ibcon#read 6, iclass 39, count 0 2006.285.20:43:01.14#ibcon#end of sib2, iclass 39, count 0 2006.285.20:43:01.14#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:43:01.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:43:01.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.20:43:01.14#ibcon#*before write, iclass 39, count 0 2006.285.20:43:01.14#ibcon#enter sib2, iclass 39, count 0 2006.285.20:43:01.14#ibcon#flushed, iclass 39, count 0 2006.285.20:43:01.14#ibcon#about to write, iclass 39, count 0 2006.285.20:43:01.14#ibcon#wrote, iclass 39, count 0 2006.285.20:43:01.14#ibcon#about to read 3, iclass 39, count 0 2006.285.20:43:01.18#ibcon#read 3, iclass 39, count 0 2006.285.20:43:01.18#ibcon#about to read 4, iclass 39, count 0 2006.285.20:43:01.18#ibcon#read 4, iclass 39, count 0 2006.285.20:43:01.18#ibcon#about to read 5, iclass 39, count 0 2006.285.20:43:01.18#ibcon#read 5, iclass 39, count 0 2006.285.20:43:01.18#ibcon#about to read 6, iclass 39, count 0 2006.285.20:43:01.18#ibcon#read 6, iclass 39, count 0 2006.285.20:43:01.18#ibcon#end of sib2, iclass 39, count 0 2006.285.20:43:01.18#ibcon#*after write, iclass 39, count 0 2006.285.20:43:01.18#ibcon#*before return 0, iclass 39, count 0 2006.285.20:43:01.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:43:01.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:43:01.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:43:01.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:43:01.19$vck44/vb=7,4 2006.285.20:43:01.19#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.20:43:01.19#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.20:43:01.19#ibcon#ireg 11 cls_cnt 2 2006.285.20:43:01.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:43:01.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:43:01.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:43:01.23#ibcon#enter wrdev, iclass 3, count 2 2006.285.20:43:01.23#ibcon#first serial, iclass 3, count 2 2006.285.20:43:01.23#ibcon#enter sib2, iclass 3, count 2 2006.285.20:43:01.23#ibcon#flushed, iclass 3, count 2 2006.285.20:43:01.23#ibcon#about to write, iclass 3, count 2 2006.285.20:43:01.23#ibcon#wrote, iclass 3, count 2 2006.285.20:43:01.23#ibcon#about to read 3, iclass 3, count 2 2006.285.20:43:01.25#ibcon#read 3, iclass 3, count 2 2006.285.20:43:01.25#ibcon#about to read 4, iclass 3, count 2 2006.285.20:43:01.25#ibcon#read 4, iclass 3, count 2 2006.285.20:43:01.25#ibcon#about to read 5, iclass 3, count 2 2006.285.20:43:01.25#ibcon#read 5, iclass 3, count 2 2006.285.20:43:01.25#ibcon#about to read 6, iclass 3, count 2 2006.285.20:43:01.25#ibcon#read 6, iclass 3, count 2 2006.285.20:43:01.25#ibcon#end of sib2, iclass 3, count 2 2006.285.20:43:01.25#ibcon#*mode == 0, iclass 3, count 2 2006.285.20:43:01.25#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.20:43:01.25#ibcon#[27=AT07-04\r\n] 2006.285.20:43:01.25#ibcon#*before write, iclass 3, count 2 2006.285.20:43:01.25#ibcon#enter sib2, iclass 3, count 2 2006.285.20:43:01.25#ibcon#flushed, iclass 3, count 2 2006.285.20:43:01.25#ibcon#about to write, iclass 3, count 2 2006.285.20:43:01.25#ibcon#wrote, iclass 3, count 2 2006.285.20:43:01.25#ibcon#about to read 3, iclass 3, count 2 2006.285.20:43:01.28#ibcon#read 3, iclass 3, count 2 2006.285.20:43:01.28#ibcon#about to read 4, iclass 3, count 2 2006.285.20:43:01.28#ibcon#read 4, iclass 3, count 2 2006.285.20:43:01.28#ibcon#about to read 5, iclass 3, count 2 2006.285.20:43:01.28#ibcon#read 5, iclass 3, count 2 2006.285.20:43:01.28#ibcon#about to read 6, iclass 3, count 2 2006.285.20:43:01.28#ibcon#read 6, iclass 3, count 2 2006.285.20:43:01.28#ibcon#end of sib2, iclass 3, count 2 2006.285.20:43:01.28#ibcon#*after write, iclass 3, count 2 2006.285.20:43:01.28#ibcon#*before return 0, iclass 3, count 2 2006.285.20:43:01.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:43:01.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:43:01.28#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.20:43:01.28#ibcon#ireg 7 cls_cnt 0 2006.285.20:43:01.28#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:43:01.40#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:43:01.40#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:43:01.40#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:43:01.40#ibcon#first serial, iclass 3, count 0 2006.285.20:43:01.40#ibcon#enter sib2, iclass 3, count 0 2006.285.20:43:01.40#ibcon#flushed, iclass 3, count 0 2006.285.20:43:01.40#ibcon#about to write, iclass 3, count 0 2006.285.20:43:01.40#ibcon#wrote, iclass 3, count 0 2006.285.20:43:01.40#ibcon#about to read 3, iclass 3, count 0 2006.285.20:43:01.42#ibcon#read 3, iclass 3, count 0 2006.285.20:43:01.42#ibcon#about to read 4, iclass 3, count 0 2006.285.20:43:01.42#ibcon#read 4, iclass 3, count 0 2006.285.20:43:01.42#ibcon#about to read 5, iclass 3, count 0 2006.285.20:43:01.42#ibcon#read 5, iclass 3, count 0 2006.285.20:43:01.42#ibcon#about to read 6, iclass 3, count 0 2006.285.20:43:01.42#ibcon#read 6, iclass 3, count 0 2006.285.20:43:01.42#ibcon#end of sib2, iclass 3, count 0 2006.285.20:43:01.42#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:43:01.42#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:43:01.42#ibcon#[27=USB\r\n] 2006.285.20:43:01.42#ibcon#*before write, iclass 3, count 0 2006.285.20:43:01.42#ibcon#enter sib2, iclass 3, count 0 2006.285.20:43:01.42#ibcon#flushed, iclass 3, count 0 2006.285.20:43:01.42#ibcon#about to write, iclass 3, count 0 2006.285.20:43:01.42#ibcon#wrote, iclass 3, count 0 2006.285.20:43:01.42#ibcon#about to read 3, iclass 3, count 0 2006.285.20:43:01.45#ibcon#read 3, iclass 3, count 0 2006.285.20:43:01.45#ibcon#about to read 4, iclass 3, count 0 2006.285.20:43:01.45#ibcon#read 4, iclass 3, count 0 2006.285.20:43:01.45#ibcon#about to read 5, iclass 3, count 0 2006.285.20:43:01.45#ibcon#read 5, iclass 3, count 0 2006.285.20:43:01.45#ibcon#about to read 6, iclass 3, count 0 2006.285.20:43:01.45#ibcon#read 6, iclass 3, count 0 2006.285.20:43:01.45#ibcon#end of sib2, iclass 3, count 0 2006.285.20:43:01.45#ibcon#*after write, iclass 3, count 0 2006.285.20:43:01.45#ibcon#*before return 0, iclass 3, count 0 2006.285.20:43:01.45#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:43:01.45#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:43:01.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:43:01.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:43:01.46$vck44/vblo=8,744.99 2006.285.20:43:01.46#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.20:43:01.46#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.20:43:01.46#ibcon#ireg 17 cls_cnt 0 2006.285.20:43:01.46#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:43:01.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:43:01.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:43:01.46#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:43:01.46#ibcon#first serial, iclass 5, count 0 2006.285.20:43:01.46#ibcon#enter sib2, iclass 5, count 0 2006.285.20:43:01.46#ibcon#flushed, iclass 5, count 0 2006.285.20:43:01.46#ibcon#about to write, iclass 5, count 0 2006.285.20:43:01.46#ibcon#wrote, iclass 5, count 0 2006.285.20:43:01.46#ibcon#about to read 3, iclass 5, count 0 2006.285.20:43:01.47#ibcon#read 3, iclass 5, count 0 2006.285.20:43:01.47#ibcon#about to read 4, iclass 5, count 0 2006.285.20:43:01.47#ibcon#read 4, iclass 5, count 0 2006.285.20:43:01.47#ibcon#about to read 5, iclass 5, count 0 2006.285.20:43:01.47#ibcon#read 5, iclass 5, count 0 2006.285.20:43:01.47#ibcon#about to read 6, iclass 5, count 0 2006.285.20:43:01.47#ibcon#read 6, iclass 5, count 0 2006.285.20:43:01.47#ibcon#end of sib2, iclass 5, count 0 2006.285.20:43:01.47#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:43:01.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:43:01.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.20:43:01.47#ibcon#*before write, iclass 5, count 0 2006.285.20:43:01.47#ibcon#enter sib2, iclass 5, count 0 2006.285.20:43:01.47#ibcon#flushed, iclass 5, count 0 2006.285.20:43:01.47#ibcon#about to write, iclass 5, count 0 2006.285.20:43:01.47#ibcon#wrote, iclass 5, count 0 2006.285.20:43:01.47#ibcon#about to read 3, iclass 5, count 0 2006.285.20:43:01.51#ibcon#read 3, iclass 5, count 0 2006.285.20:43:01.51#ibcon#about to read 4, iclass 5, count 0 2006.285.20:43:01.51#ibcon#read 4, iclass 5, count 0 2006.285.20:43:01.51#ibcon#about to read 5, iclass 5, count 0 2006.285.20:43:01.51#ibcon#read 5, iclass 5, count 0 2006.285.20:43:01.51#ibcon#about to read 6, iclass 5, count 0 2006.285.20:43:01.51#ibcon#read 6, iclass 5, count 0 2006.285.20:43:01.51#ibcon#end of sib2, iclass 5, count 0 2006.285.20:43:01.51#ibcon#*after write, iclass 5, count 0 2006.285.20:43:01.51#ibcon#*before return 0, iclass 5, count 0 2006.285.20:43:01.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:43:01.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:43:01.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:43:01.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:43:01.52$vck44/vb=8,4 2006.285.20:43:01.52#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.20:43:01.52#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.20:43:01.52#ibcon#ireg 11 cls_cnt 2 2006.285.20:43:01.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:43:01.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:43:01.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:43:01.56#ibcon#enter wrdev, iclass 7, count 2 2006.285.20:43:01.56#ibcon#first serial, iclass 7, count 2 2006.285.20:43:01.56#ibcon#enter sib2, iclass 7, count 2 2006.285.20:43:01.56#ibcon#flushed, iclass 7, count 2 2006.285.20:43:01.56#ibcon#about to write, iclass 7, count 2 2006.285.20:43:01.56#ibcon#wrote, iclass 7, count 2 2006.285.20:43:01.56#ibcon#about to read 3, iclass 7, count 2 2006.285.20:43:01.58#ibcon#read 3, iclass 7, count 2 2006.285.20:43:01.58#ibcon#about to read 4, iclass 7, count 2 2006.285.20:43:01.58#ibcon#read 4, iclass 7, count 2 2006.285.20:43:01.58#ibcon#about to read 5, iclass 7, count 2 2006.285.20:43:01.58#ibcon#read 5, iclass 7, count 2 2006.285.20:43:01.58#ibcon#about to read 6, iclass 7, count 2 2006.285.20:43:01.58#ibcon#read 6, iclass 7, count 2 2006.285.20:43:01.58#ibcon#end of sib2, iclass 7, count 2 2006.285.20:43:01.58#ibcon#*mode == 0, iclass 7, count 2 2006.285.20:43:01.58#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.20:43:01.58#ibcon#[27=AT08-04\r\n] 2006.285.20:43:01.58#ibcon#*before write, iclass 7, count 2 2006.285.20:43:01.58#ibcon#enter sib2, iclass 7, count 2 2006.285.20:43:01.58#ibcon#flushed, iclass 7, count 2 2006.285.20:43:01.58#ibcon#about to write, iclass 7, count 2 2006.285.20:43:01.58#ibcon#wrote, iclass 7, count 2 2006.285.20:43:01.59#ibcon#about to read 3, iclass 7, count 2 2006.285.20:43:01.61#ibcon#read 3, iclass 7, count 2 2006.285.20:43:01.61#ibcon#about to read 4, iclass 7, count 2 2006.285.20:43:01.61#ibcon#read 4, iclass 7, count 2 2006.285.20:43:01.61#ibcon#about to read 5, iclass 7, count 2 2006.285.20:43:01.61#ibcon#read 5, iclass 7, count 2 2006.285.20:43:01.61#ibcon#about to read 6, iclass 7, count 2 2006.285.20:43:01.61#ibcon#read 6, iclass 7, count 2 2006.285.20:43:01.61#ibcon#end of sib2, iclass 7, count 2 2006.285.20:43:01.61#ibcon#*after write, iclass 7, count 2 2006.285.20:43:01.61#ibcon#*before return 0, iclass 7, count 2 2006.285.20:43:01.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:43:01.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:43:01.61#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.20:43:01.61#ibcon#ireg 7 cls_cnt 0 2006.285.20:43:01.61#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:43:01.73#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:43:01.73#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:43:01.73#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:43:01.73#ibcon#first serial, iclass 7, count 0 2006.285.20:43:01.73#ibcon#enter sib2, iclass 7, count 0 2006.285.20:43:01.73#ibcon#flushed, iclass 7, count 0 2006.285.20:43:01.73#ibcon#about to write, iclass 7, count 0 2006.285.20:43:01.73#ibcon#wrote, iclass 7, count 0 2006.285.20:43:01.73#ibcon#about to read 3, iclass 7, count 0 2006.285.20:43:01.75#ibcon#read 3, iclass 7, count 0 2006.285.20:43:01.75#ibcon#about to read 4, iclass 7, count 0 2006.285.20:43:01.75#ibcon#read 4, iclass 7, count 0 2006.285.20:43:01.75#ibcon#about to read 5, iclass 7, count 0 2006.285.20:43:01.75#ibcon#read 5, iclass 7, count 0 2006.285.20:43:01.75#ibcon#about to read 6, iclass 7, count 0 2006.285.20:43:01.75#ibcon#read 6, iclass 7, count 0 2006.285.20:43:01.75#ibcon#end of sib2, iclass 7, count 0 2006.285.20:43:01.75#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:43:01.75#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:43:01.75#ibcon#[27=USB\r\n] 2006.285.20:43:01.75#ibcon#*before write, iclass 7, count 0 2006.285.20:43:01.75#ibcon#enter sib2, iclass 7, count 0 2006.285.20:43:01.75#ibcon#flushed, iclass 7, count 0 2006.285.20:43:01.75#ibcon#about to write, iclass 7, count 0 2006.285.20:43:01.75#ibcon#wrote, iclass 7, count 0 2006.285.20:43:01.75#ibcon#about to read 3, iclass 7, count 0 2006.285.20:43:01.78#ibcon#read 3, iclass 7, count 0 2006.285.20:43:01.78#ibcon#about to read 4, iclass 7, count 0 2006.285.20:43:01.78#ibcon#read 4, iclass 7, count 0 2006.285.20:43:01.78#ibcon#about to read 5, iclass 7, count 0 2006.285.20:43:01.78#ibcon#read 5, iclass 7, count 0 2006.285.20:43:01.78#ibcon#about to read 6, iclass 7, count 0 2006.285.20:43:01.78#ibcon#read 6, iclass 7, count 0 2006.285.20:43:01.78#ibcon#end of sib2, iclass 7, count 0 2006.285.20:43:01.78#ibcon#*after write, iclass 7, count 0 2006.285.20:43:01.78#ibcon#*before return 0, iclass 7, count 0 2006.285.20:43:01.78#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:43:01.78#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:43:01.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:43:01.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:43:01.79$vck44/vabw=wide 2006.285.20:43:01.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.20:43:01.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.20:43:01.88#ibcon#ireg 8 cls_cnt 0 2006.285.20:43:01.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:43:01.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:43:01.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:43:01.88#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:43:01.88#ibcon#first serial, iclass 11, count 0 2006.285.20:43:01.88#ibcon#enter sib2, iclass 11, count 0 2006.285.20:43:01.88#ibcon#flushed, iclass 11, count 0 2006.285.20:43:01.88#ibcon#about to write, iclass 11, count 0 2006.285.20:43:01.88#ibcon#wrote, iclass 11, count 0 2006.285.20:43:01.88#ibcon#about to read 3, iclass 11, count 0 2006.285.20:43:01.90#ibcon#read 3, iclass 11, count 0 2006.285.20:43:01.90#ibcon#about to read 4, iclass 11, count 0 2006.285.20:43:01.90#ibcon#read 4, iclass 11, count 0 2006.285.20:43:01.90#ibcon#about to read 5, iclass 11, count 0 2006.285.20:43:01.90#ibcon#read 5, iclass 11, count 0 2006.285.20:43:01.90#ibcon#about to read 6, iclass 11, count 0 2006.285.20:43:01.90#ibcon#read 6, iclass 11, count 0 2006.285.20:43:01.90#ibcon#end of sib2, iclass 11, count 0 2006.285.20:43:01.90#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:43:01.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:43:01.90#ibcon#[25=BW32\r\n] 2006.285.20:43:01.90#ibcon#*before write, iclass 11, count 0 2006.285.20:43:01.90#ibcon#enter sib2, iclass 11, count 0 2006.285.20:43:01.90#ibcon#flushed, iclass 11, count 0 2006.285.20:43:01.90#ibcon#about to write, iclass 11, count 0 2006.285.20:43:01.90#ibcon#wrote, iclass 11, count 0 2006.285.20:43:01.90#ibcon#about to read 3, iclass 11, count 0 2006.285.20:43:01.93#ibcon#read 3, iclass 11, count 0 2006.285.20:43:01.93#ibcon#about to read 4, iclass 11, count 0 2006.285.20:43:01.93#ibcon#read 4, iclass 11, count 0 2006.285.20:43:01.93#ibcon#about to read 5, iclass 11, count 0 2006.285.20:43:01.93#ibcon#read 5, iclass 11, count 0 2006.285.20:43:01.93#ibcon#about to read 6, iclass 11, count 0 2006.285.20:43:01.93#ibcon#read 6, iclass 11, count 0 2006.285.20:43:01.93#ibcon#end of sib2, iclass 11, count 0 2006.285.20:43:01.93#ibcon#*after write, iclass 11, count 0 2006.285.20:43:01.93#ibcon#*before return 0, iclass 11, count 0 2006.285.20:43:01.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:43:01.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:43:01.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:43:01.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:43:01.94$vck44/vbbw=wide 2006.285.20:43:01.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.20:43:01.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.20:43:01.94#ibcon#ireg 8 cls_cnt 0 2006.285.20:43:01.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:43:01.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:43:01.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:43:01.94#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:43:01.94#ibcon#first serial, iclass 13, count 0 2006.285.20:43:01.94#ibcon#enter sib2, iclass 13, count 0 2006.285.20:43:01.94#ibcon#flushed, iclass 13, count 0 2006.285.20:43:01.94#ibcon#about to write, iclass 13, count 0 2006.285.20:43:01.94#ibcon#wrote, iclass 13, count 0 2006.285.20:43:01.94#ibcon#about to read 3, iclass 13, count 0 2006.285.20:43:01.95#ibcon#read 3, iclass 13, count 0 2006.285.20:43:01.95#ibcon#about to read 4, iclass 13, count 0 2006.285.20:43:01.95#ibcon#read 4, iclass 13, count 0 2006.285.20:43:01.95#ibcon#about to read 5, iclass 13, count 0 2006.285.20:43:01.95#ibcon#read 5, iclass 13, count 0 2006.285.20:43:01.95#ibcon#about to read 6, iclass 13, count 0 2006.285.20:43:01.95#ibcon#read 6, iclass 13, count 0 2006.285.20:43:01.95#ibcon#end of sib2, iclass 13, count 0 2006.285.20:43:01.95#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:43:01.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:43:01.95#ibcon#[27=BW32\r\n] 2006.285.20:43:01.95#ibcon#*before write, iclass 13, count 0 2006.285.20:43:01.95#ibcon#enter sib2, iclass 13, count 0 2006.285.20:43:01.95#ibcon#flushed, iclass 13, count 0 2006.285.20:43:01.95#ibcon#about to write, iclass 13, count 0 2006.285.20:43:01.95#ibcon#wrote, iclass 13, count 0 2006.285.20:43:01.95#ibcon#about to read 3, iclass 13, count 0 2006.285.20:43:01.98#ibcon#read 3, iclass 13, count 0 2006.285.20:43:01.98#ibcon#about to read 4, iclass 13, count 0 2006.285.20:43:01.98#ibcon#read 4, iclass 13, count 0 2006.285.20:43:01.98#ibcon#about to read 5, iclass 13, count 0 2006.285.20:43:01.98#ibcon#read 5, iclass 13, count 0 2006.285.20:43:01.98#ibcon#about to read 6, iclass 13, count 0 2006.285.20:43:01.98#ibcon#read 6, iclass 13, count 0 2006.285.20:43:01.98#ibcon#end of sib2, iclass 13, count 0 2006.285.20:43:01.98#ibcon#*after write, iclass 13, count 0 2006.285.20:43:01.98#ibcon#*before return 0, iclass 13, count 0 2006.285.20:43:01.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:43:01.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:43:01.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:43:01.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:43:01.99$setupk4/ifdk4 2006.285.20:43:01.99$ifdk4/lo= 2006.285.20:43:01.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.20:43:01.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.20:43:01.99$ifdk4/patch= 2006.285.20:43:01.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.20:43:01.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.20:43:01.99$setupk4/!*+20s 2006.285.20:43:02.62#abcon#<5=/13 0.3 0.7 14.221001015.4\r\n> 2006.285.20:43:02.64#abcon#{5=INTERFACE CLEAR} 2006.285.20:43:02.70#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:43:12.79#abcon#<5=/00 0.2 0.7 14.221001015.4\r\n> 2006.285.20:43:12.81#abcon#{5=INTERFACE CLEAR} 2006.285.20:43:12.87#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:43:15.75$setupk4/"tpicd 2006.285.20:43:15.75$setupk4/echo=off 2006.285.20:43:15.75$setupk4/xlog=off 2006.285.20:43:15.76:!2006.285.20:44:33 2006.285.20:43:16.13#trakl#Source acquired 2006.285.20:43:17.14#flagr#flagr/antenna,acquired 2006.285.20:44:33.01:preob 2006.285.20:44:34.14/onsource/TRACKING 2006.285.20:44:34.15:!2006.285.20:44:43 2006.285.20:44:43.01:"tape 2006.285.20:44:43.01:"st=record 2006.285.20:44:43.01:data_valid=on 2006.285.20:44:43.02:midob 2006.285.20:44:44.14/onsource/TRACKING 2006.285.20:44:44.15/wx/14.20,1015.4,100 2006.285.20:44:44.31/cable/+6.5103E-03 2006.285.20:44:45.40/va/01,07,usb,yes,33,35 2006.285.20:44:45.40/va/02,06,usb,yes,33,33 2006.285.20:44:45.40/va/03,07,usb,yes,32,34 2006.285.20:44:45.40/va/04,06,usb,yes,34,35 2006.285.20:44:45.40/va/05,03,usb,yes,33,34 2006.285.20:44:45.40/va/06,04,usb,yes,30,29 2006.285.20:44:45.40/va/07,04,usb,yes,31,31 2006.285.20:44:45.40/va/08,03,usb,yes,31,38 2006.285.20:44:45.63/valo/01,524.99,yes,locked 2006.285.20:44:45.63/valo/02,534.99,yes,locked 2006.285.20:44:45.63/valo/03,564.99,yes,locked 2006.285.20:44:45.63/valo/04,624.99,yes,locked 2006.285.20:44:45.63/valo/05,734.99,yes,locked 2006.285.20:44:45.63/valo/06,814.99,yes,locked 2006.285.20:44:45.63/valo/07,864.99,yes,locked 2006.285.20:44:45.63/valo/08,884.99,yes,locked 2006.285.20:44:46.72/vb/01,04,usb,yes,30,28 2006.285.20:44:46.72/vb/02,05,usb,yes,28,29 2006.285.20:44:46.72/vb/03,04,usb,yes,29,32 2006.285.20:44:46.72/vb/04,05,usb,yes,30,29 2006.285.20:44:46.72/vb/05,04,usb,yes,26,28 2006.285.20:44:46.72/vb/06,03,usb,yes,37,33 2006.285.20:44:46.72/vb/07,04,usb,yes,30,30 2006.285.20:44:46.72/vb/08,04,usb,yes,27,31 2006.285.20:44:46.95/vblo/01,629.99,yes,locked 2006.285.20:44:46.95/vblo/02,634.99,yes,locked 2006.285.20:44:46.95/vblo/03,649.99,yes,locked 2006.285.20:44:46.95/vblo/04,679.99,yes,locked 2006.285.20:44:46.95/vblo/05,709.99,yes,locked 2006.285.20:44:46.95/vblo/06,719.99,yes,locked 2006.285.20:44:46.95/vblo/07,734.99,yes,locked 2006.285.20:44:46.95/vblo/08,744.99,yes,locked 2006.285.20:44:47.10/vabw/8 2006.285.20:44:47.25/vbbw/8 2006.285.20:44:47.34/xfe/off,on,12.0 2006.285.20:44:47.72/ifatt/23,28,28,28 2006.285.20:44:48.07/fmout-gps/S +2.88E-07 2006.285.20:44:48.09:!2006.285.20:45:43 2006.285.20:45:43.01:data_valid=off 2006.285.20:45:43.02:"et 2006.285.20:45:43.02:!+3s 2006.285.20:45:46.04:"tape 2006.285.20:45:46.04:postob 2006.285.20:45:46.18/cable/+6.5086E-03 2006.285.20:45:46.18/wx/14.18,1015.4,100 2006.285.20:45:46.24/fmout-gps/S +2.88E-07 2006.285.20:45:46.24:scan_name=285-2047,jd0610,100 2006.285.20:45:46.25:source=3c274,123049.42,122328.0,2000.0,ccw 2006.285.20:45:47.14#flagr#flagr/antenna,new-source 2006.285.20:45:47.15:checkk5 2006.285.20:45:47.81/chk_autoobs//k5ts1/ autoobs is running! 2006.285.20:45:48.18/chk_autoobs//k5ts2/ autoobs is running! 2006.285.20:45:48.62/chk_autoobs//k5ts3/ autoobs is running! 2006.285.20:45:48.99/chk_autoobs//k5ts4/ autoobs is running! 2006.285.20:45:49.49/chk_obsdata//k5ts1/T2852044??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.20:45:49.89/chk_obsdata//k5ts2/T2852044??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.20:45:50.37/chk_obsdata//k5ts3/T2852044??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.20:45:53.77/chk_obsdata//k5ts4/T2852044??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.20:45:54.55/k5log//k5ts1_log_newline 2006.285.20:45:55.32/k5log//k5ts2_log_newline 2006.285.20:45:56.24/k5log//k5ts3_log_newline 2006.285.20:45:57.36/k5log//k5ts4_log_newline 2006.285.20:45:57.38/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.20:45:57.38:setupk4=1 2006.285.20:45:57.38$setupk4/echo=on 2006.285.20:45:57.38$setupk4/pcalon 2006.285.20:45:57.38$pcalon/"no phase cal control is implemented here 2006.285.20:45:57.38$setupk4/"tpicd=stop 2006.285.20:45:57.38$setupk4/"rec=synch_on 2006.285.20:45:57.38$setupk4/"rec_mode=128 2006.285.20:45:57.38$setupk4/!* 2006.285.20:45:57.38$setupk4/recpk4 2006.285.20:45:57.38$recpk4/recpatch= 2006.285.20:45:57.38$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.20:45:57.38$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.20:45:57.38$setupk4/vck44 2006.285.20:45:57.38$vck44/valo=1,524.99 2006.285.20:45:57.38#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.20:45:57.38#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.20:45:57.38#ibcon#ireg 17 cls_cnt 0 2006.285.20:45:57.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:45:57.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:45:57.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:45:57.38#ibcon#enter wrdev, iclass 18, count 0 2006.285.20:45:57.38#ibcon#first serial, iclass 18, count 0 2006.285.20:45:57.38#ibcon#enter sib2, iclass 18, count 0 2006.285.20:45:57.38#ibcon#flushed, iclass 18, count 0 2006.285.20:45:57.38#ibcon#about to write, iclass 18, count 0 2006.285.20:45:57.38#ibcon#wrote, iclass 18, count 0 2006.285.20:45:57.38#ibcon#about to read 3, iclass 18, count 0 2006.285.20:45:57.39#ibcon#read 3, iclass 18, count 0 2006.285.20:45:57.39#ibcon#about to read 4, iclass 18, count 0 2006.285.20:45:57.39#ibcon#read 4, iclass 18, count 0 2006.285.20:45:57.39#ibcon#about to read 5, iclass 18, count 0 2006.285.20:45:57.39#ibcon#read 5, iclass 18, count 0 2006.285.20:45:57.39#ibcon#about to read 6, iclass 18, count 0 2006.285.20:45:57.39#ibcon#read 6, iclass 18, count 0 2006.285.20:45:57.39#ibcon#end of sib2, iclass 18, count 0 2006.285.20:45:57.39#ibcon#*mode == 0, iclass 18, count 0 2006.285.20:45:57.39#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.20:45:57.39#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.20:45:57.39#ibcon#*before write, iclass 18, count 0 2006.285.20:45:57.39#ibcon#enter sib2, iclass 18, count 0 2006.285.20:45:57.39#ibcon#flushed, iclass 18, count 0 2006.285.20:45:57.39#ibcon#about to write, iclass 18, count 0 2006.285.20:45:57.39#ibcon#wrote, iclass 18, count 0 2006.285.20:45:57.39#ibcon#about to read 3, iclass 18, count 0 2006.285.20:45:57.44#ibcon#read 3, iclass 18, count 0 2006.285.20:45:57.44#ibcon#about to read 4, iclass 18, count 0 2006.285.20:45:57.44#ibcon#read 4, iclass 18, count 0 2006.285.20:45:57.44#ibcon#about to read 5, iclass 18, count 0 2006.285.20:45:57.44#ibcon#read 5, iclass 18, count 0 2006.285.20:45:57.44#ibcon#about to read 6, iclass 18, count 0 2006.285.20:45:57.44#ibcon#read 6, iclass 18, count 0 2006.285.20:45:57.44#ibcon#end of sib2, iclass 18, count 0 2006.285.20:45:57.44#ibcon#*after write, iclass 18, count 0 2006.285.20:45:57.44#ibcon#*before return 0, iclass 18, count 0 2006.285.20:45:57.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:45:57.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:45:57.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.20:45:57.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.20:45:57.44$vck44/va=1,7 2006.285.20:45:57.44#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.20:45:57.44#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.20:45:57.44#ibcon#ireg 11 cls_cnt 2 2006.285.20:45:57.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:45:57.44#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:45:57.44#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:45:57.44#ibcon#enter wrdev, iclass 20, count 2 2006.285.20:45:57.44#ibcon#first serial, iclass 20, count 2 2006.285.20:45:57.44#ibcon#enter sib2, iclass 20, count 2 2006.285.20:45:57.44#ibcon#flushed, iclass 20, count 2 2006.285.20:45:57.44#ibcon#about to write, iclass 20, count 2 2006.285.20:45:57.44#ibcon#wrote, iclass 20, count 2 2006.285.20:45:57.44#ibcon#about to read 3, iclass 20, count 2 2006.285.20:45:57.46#ibcon#read 3, iclass 20, count 2 2006.285.20:45:57.46#ibcon#about to read 4, iclass 20, count 2 2006.285.20:45:57.46#ibcon#read 4, iclass 20, count 2 2006.285.20:45:57.46#ibcon#about to read 5, iclass 20, count 2 2006.285.20:45:57.46#ibcon#read 5, iclass 20, count 2 2006.285.20:45:57.46#ibcon#about to read 6, iclass 20, count 2 2006.285.20:45:57.46#ibcon#read 6, iclass 20, count 2 2006.285.20:45:57.46#ibcon#end of sib2, iclass 20, count 2 2006.285.20:45:57.46#ibcon#*mode == 0, iclass 20, count 2 2006.285.20:45:57.46#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.20:45:57.46#ibcon#[25=AT01-07\r\n] 2006.285.20:45:57.46#ibcon#*before write, iclass 20, count 2 2006.285.20:45:57.46#ibcon#enter sib2, iclass 20, count 2 2006.285.20:45:57.46#ibcon#flushed, iclass 20, count 2 2006.285.20:45:57.46#ibcon#about to write, iclass 20, count 2 2006.285.20:45:57.46#ibcon#wrote, iclass 20, count 2 2006.285.20:45:57.46#ibcon#about to read 3, iclass 20, count 2 2006.285.20:45:57.49#ibcon#read 3, iclass 20, count 2 2006.285.20:45:57.49#ibcon#about to read 4, iclass 20, count 2 2006.285.20:45:57.49#ibcon#read 4, iclass 20, count 2 2006.285.20:45:57.49#ibcon#about to read 5, iclass 20, count 2 2006.285.20:45:57.49#ibcon#read 5, iclass 20, count 2 2006.285.20:45:57.49#ibcon#about to read 6, iclass 20, count 2 2006.285.20:45:57.49#ibcon#read 6, iclass 20, count 2 2006.285.20:45:57.49#ibcon#end of sib2, iclass 20, count 2 2006.285.20:45:57.49#ibcon#*after write, iclass 20, count 2 2006.285.20:45:57.49#ibcon#*before return 0, iclass 20, count 2 2006.285.20:45:57.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:45:57.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:45:57.49#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.20:45:57.49#ibcon#ireg 7 cls_cnt 0 2006.285.20:45:57.49#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:45:57.61#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:45:57.61#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:45:57.61#ibcon#enter wrdev, iclass 20, count 0 2006.285.20:45:57.61#ibcon#first serial, iclass 20, count 0 2006.285.20:45:57.61#ibcon#enter sib2, iclass 20, count 0 2006.285.20:45:57.61#ibcon#flushed, iclass 20, count 0 2006.285.20:45:57.61#ibcon#about to write, iclass 20, count 0 2006.285.20:45:57.61#ibcon#wrote, iclass 20, count 0 2006.285.20:45:57.61#ibcon#about to read 3, iclass 20, count 0 2006.285.20:45:57.63#ibcon#read 3, iclass 20, count 0 2006.285.20:45:57.63#ibcon#about to read 4, iclass 20, count 0 2006.285.20:45:57.63#ibcon#read 4, iclass 20, count 0 2006.285.20:45:57.63#ibcon#about to read 5, iclass 20, count 0 2006.285.20:45:57.63#ibcon#read 5, iclass 20, count 0 2006.285.20:45:57.63#ibcon#about to read 6, iclass 20, count 0 2006.285.20:45:57.63#ibcon#read 6, iclass 20, count 0 2006.285.20:45:57.63#ibcon#end of sib2, iclass 20, count 0 2006.285.20:45:57.63#ibcon#*mode == 0, iclass 20, count 0 2006.285.20:45:57.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.20:45:57.63#ibcon#[25=USB\r\n] 2006.285.20:45:57.63#ibcon#*before write, iclass 20, count 0 2006.285.20:45:57.63#ibcon#enter sib2, iclass 20, count 0 2006.285.20:45:57.63#ibcon#flushed, iclass 20, count 0 2006.285.20:45:57.63#ibcon#about to write, iclass 20, count 0 2006.285.20:45:57.63#ibcon#wrote, iclass 20, count 0 2006.285.20:45:57.63#ibcon#about to read 3, iclass 20, count 0 2006.285.20:45:57.66#ibcon#read 3, iclass 20, count 0 2006.285.20:45:57.66#ibcon#about to read 4, iclass 20, count 0 2006.285.20:45:57.66#ibcon#read 4, iclass 20, count 0 2006.285.20:45:57.66#ibcon#about to read 5, iclass 20, count 0 2006.285.20:45:57.66#ibcon#read 5, iclass 20, count 0 2006.285.20:45:57.66#ibcon#about to read 6, iclass 20, count 0 2006.285.20:45:57.66#ibcon#read 6, iclass 20, count 0 2006.285.20:45:57.66#ibcon#end of sib2, iclass 20, count 0 2006.285.20:45:57.66#ibcon#*after write, iclass 20, count 0 2006.285.20:45:57.66#ibcon#*before return 0, iclass 20, count 0 2006.285.20:45:57.66#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:45:57.66#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:45:57.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.20:45:57.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.20:45:57.66$vck44/valo=2,534.99 2006.285.20:45:57.66#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.20:45:57.66#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.20:45:57.66#ibcon#ireg 17 cls_cnt 0 2006.285.20:45:57.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:45:57.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:45:57.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:45:57.66#ibcon#enter wrdev, iclass 22, count 0 2006.285.20:45:57.66#ibcon#first serial, iclass 22, count 0 2006.285.20:45:57.66#ibcon#enter sib2, iclass 22, count 0 2006.285.20:45:57.66#ibcon#flushed, iclass 22, count 0 2006.285.20:45:57.66#ibcon#about to write, iclass 22, count 0 2006.285.20:45:57.66#ibcon#wrote, iclass 22, count 0 2006.285.20:45:57.66#ibcon#about to read 3, iclass 22, count 0 2006.285.20:45:57.68#ibcon#read 3, iclass 22, count 0 2006.285.20:45:57.68#ibcon#about to read 4, iclass 22, count 0 2006.285.20:45:57.68#ibcon#read 4, iclass 22, count 0 2006.285.20:45:57.68#ibcon#about to read 5, iclass 22, count 0 2006.285.20:45:57.68#ibcon#read 5, iclass 22, count 0 2006.285.20:45:57.68#ibcon#about to read 6, iclass 22, count 0 2006.285.20:45:57.68#ibcon#read 6, iclass 22, count 0 2006.285.20:45:57.68#ibcon#end of sib2, iclass 22, count 0 2006.285.20:45:57.68#ibcon#*mode == 0, iclass 22, count 0 2006.285.20:45:57.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.20:45:57.68#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.20:45:57.68#ibcon#*before write, iclass 22, count 0 2006.285.20:45:57.68#ibcon#enter sib2, iclass 22, count 0 2006.285.20:45:57.68#ibcon#flushed, iclass 22, count 0 2006.285.20:45:57.68#ibcon#about to write, iclass 22, count 0 2006.285.20:45:57.68#ibcon#wrote, iclass 22, count 0 2006.285.20:45:57.68#ibcon#about to read 3, iclass 22, count 0 2006.285.20:45:57.72#ibcon#read 3, iclass 22, count 0 2006.285.20:45:57.72#ibcon#about to read 4, iclass 22, count 0 2006.285.20:45:57.72#ibcon#read 4, iclass 22, count 0 2006.285.20:45:57.72#ibcon#about to read 5, iclass 22, count 0 2006.285.20:45:57.72#ibcon#read 5, iclass 22, count 0 2006.285.20:45:57.72#ibcon#about to read 6, iclass 22, count 0 2006.285.20:45:57.72#ibcon#read 6, iclass 22, count 0 2006.285.20:45:57.72#ibcon#end of sib2, iclass 22, count 0 2006.285.20:45:57.72#ibcon#*after write, iclass 22, count 0 2006.285.20:45:57.72#ibcon#*before return 0, iclass 22, count 0 2006.285.20:45:57.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:45:57.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:45:57.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.20:45:57.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.20:45:57.72$vck44/va=2,6 2006.285.20:45:57.72#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.20:45:57.72#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.20:45:57.72#ibcon#ireg 11 cls_cnt 2 2006.285.20:45:57.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:45:57.78#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:45:57.78#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:45:57.78#ibcon#enter wrdev, iclass 24, count 2 2006.285.20:45:57.78#ibcon#first serial, iclass 24, count 2 2006.285.20:45:57.78#ibcon#enter sib2, iclass 24, count 2 2006.285.20:45:57.78#ibcon#flushed, iclass 24, count 2 2006.285.20:45:57.78#ibcon#about to write, iclass 24, count 2 2006.285.20:45:57.78#ibcon#wrote, iclass 24, count 2 2006.285.20:45:57.78#ibcon#about to read 3, iclass 24, count 2 2006.285.20:45:57.80#ibcon#read 3, iclass 24, count 2 2006.285.20:45:57.80#ibcon#about to read 4, iclass 24, count 2 2006.285.20:45:57.80#ibcon#read 4, iclass 24, count 2 2006.285.20:45:57.80#ibcon#about to read 5, iclass 24, count 2 2006.285.20:45:57.80#ibcon#read 5, iclass 24, count 2 2006.285.20:45:57.80#ibcon#about to read 6, iclass 24, count 2 2006.285.20:45:57.80#ibcon#read 6, iclass 24, count 2 2006.285.20:45:57.80#ibcon#end of sib2, iclass 24, count 2 2006.285.20:45:57.80#ibcon#*mode == 0, iclass 24, count 2 2006.285.20:45:57.80#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.20:45:57.80#ibcon#[25=AT02-06\r\n] 2006.285.20:45:57.80#ibcon#*before write, iclass 24, count 2 2006.285.20:45:57.80#ibcon#enter sib2, iclass 24, count 2 2006.285.20:45:57.80#ibcon#flushed, iclass 24, count 2 2006.285.20:45:57.80#ibcon#about to write, iclass 24, count 2 2006.285.20:45:57.80#ibcon#wrote, iclass 24, count 2 2006.285.20:45:57.80#ibcon#about to read 3, iclass 24, count 2 2006.285.20:45:57.83#ibcon#read 3, iclass 24, count 2 2006.285.20:45:57.83#ibcon#about to read 4, iclass 24, count 2 2006.285.20:45:57.83#ibcon#read 4, iclass 24, count 2 2006.285.20:45:57.83#ibcon#about to read 5, iclass 24, count 2 2006.285.20:45:57.83#ibcon#read 5, iclass 24, count 2 2006.285.20:45:57.83#ibcon#about to read 6, iclass 24, count 2 2006.285.20:45:57.83#ibcon#read 6, iclass 24, count 2 2006.285.20:45:57.83#ibcon#end of sib2, iclass 24, count 2 2006.285.20:45:57.83#ibcon#*after write, iclass 24, count 2 2006.285.20:45:57.83#ibcon#*before return 0, iclass 24, count 2 2006.285.20:45:57.83#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:45:57.83#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:45:57.83#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.20:45:57.83#ibcon#ireg 7 cls_cnt 0 2006.285.20:45:57.83#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:45:57.95#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:45:57.95#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:45:57.95#ibcon#enter wrdev, iclass 24, count 0 2006.285.20:45:57.95#ibcon#first serial, iclass 24, count 0 2006.285.20:45:57.95#ibcon#enter sib2, iclass 24, count 0 2006.285.20:45:57.95#ibcon#flushed, iclass 24, count 0 2006.285.20:45:57.95#ibcon#about to write, iclass 24, count 0 2006.285.20:45:57.95#ibcon#wrote, iclass 24, count 0 2006.285.20:45:57.95#ibcon#about to read 3, iclass 24, count 0 2006.285.20:45:57.97#ibcon#read 3, iclass 24, count 0 2006.285.20:45:57.97#ibcon#about to read 4, iclass 24, count 0 2006.285.20:45:57.97#ibcon#read 4, iclass 24, count 0 2006.285.20:45:57.97#ibcon#about to read 5, iclass 24, count 0 2006.285.20:45:57.97#ibcon#read 5, iclass 24, count 0 2006.285.20:45:57.97#ibcon#about to read 6, iclass 24, count 0 2006.285.20:45:57.97#ibcon#read 6, iclass 24, count 0 2006.285.20:45:57.97#ibcon#end of sib2, iclass 24, count 0 2006.285.20:45:57.97#ibcon#*mode == 0, iclass 24, count 0 2006.285.20:45:57.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.20:45:57.97#ibcon#[25=USB\r\n] 2006.285.20:45:57.97#ibcon#*before write, iclass 24, count 0 2006.285.20:45:57.97#ibcon#enter sib2, iclass 24, count 0 2006.285.20:45:57.97#ibcon#flushed, iclass 24, count 0 2006.285.20:45:57.97#ibcon#about to write, iclass 24, count 0 2006.285.20:45:57.97#ibcon#wrote, iclass 24, count 0 2006.285.20:45:57.97#ibcon#about to read 3, iclass 24, count 0 2006.285.20:45:58.00#ibcon#read 3, iclass 24, count 0 2006.285.20:45:58.00#ibcon#about to read 4, iclass 24, count 0 2006.285.20:45:58.00#ibcon#read 4, iclass 24, count 0 2006.285.20:45:58.00#ibcon#about to read 5, iclass 24, count 0 2006.285.20:45:58.00#ibcon#read 5, iclass 24, count 0 2006.285.20:45:58.00#ibcon#about to read 6, iclass 24, count 0 2006.285.20:45:58.00#ibcon#read 6, iclass 24, count 0 2006.285.20:45:58.00#ibcon#end of sib2, iclass 24, count 0 2006.285.20:45:58.00#ibcon#*after write, iclass 24, count 0 2006.285.20:45:58.00#ibcon#*before return 0, iclass 24, count 0 2006.285.20:45:58.00#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:45:58.00#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:45:58.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.20:45:58.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.20:45:58.00$vck44/valo=3,564.99 2006.285.20:45:58.00#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.20:45:58.00#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.20:45:58.00#ibcon#ireg 17 cls_cnt 0 2006.285.20:45:58.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:45:58.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:45:58.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:45:58.00#ibcon#enter wrdev, iclass 26, count 0 2006.285.20:45:58.00#ibcon#first serial, iclass 26, count 0 2006.285.20:45:58.00#ibcon#enter sib2, iclass 26, count 0 2006.285.20:45:58.00#ibcon#flushed, iclass 26, count 0 2006.285.20:45:58.00#ibcon#about to write, iclass 26, count 0 2006.285.20:45:58.00#ibcon#wrote, iclass 26, count 0 2006.285.20:45:58.00#ibcon#about to read 3, iclass 26, count 0 2006.285.20:45:58.02#ibcon#read 3, iclass 26, count 0 2006.285.20:45:58.02#ibcon#about to read 4, iclass 26, count 0 2006.285.20:45:58.02#ibcon#read 4, iclass 26, count 0 2006.285.20:45:58.02#ibcon#about to read 5, iclass 26, count 0 2006.285.20:45:58.02#ibcon#read 5, iclass 26, count 0 2006.285.20:45:58.02#ibcon#about to read 6, iclass 26, count 0 2006.285.20:45:58.02#ibcon#read 6, iclass 26, count 0 2006.285.20:45:58.02#ibcon#end of sib2, iclass 26, count 0 2006.285.20:45:58.02#ibcon#*mode == 0, iclass 26, count 0 2006.285.20:45:58.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.20:45:58.02#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.20:45:58.02#ibcon#*before write, iclass 26, count 0 2006.285.20:45:58.02#ibcon#enter sib2, iclass 26, count 0 2006.285.20:45:58.02#ibcon#flushed, iclass 26, count 0 2006.285.20:45:58.02#ibcon#about to write, iclass 26, count 0 2006.285.20:45:58.02#ibcon#wrote, iclass 26, count 0 2006.285.20:45:58.02#ibcon#about to read 3, iclass 26, count 0 2006.285.20:45:58.06#ibcon#read 3, iclass 26, count 0 2006.285.20:45:58.06#ibcon#about to read 4, iclass 26, count 0 2006.285.20:45:58.06#ibcon#read 4, iclass 26, count 0 2006.285.20:45:58.06#ibcon#about to read 5, iclass 26, count 0 2006.285.20:45:58.06#ibcon#read 5, iclass 26, count 0 2006.285.20:45:58.06#ibcon#about to read 6, iclass 26, count 0 2006.285.20:45:58.06#ibcon#read 6, iclass 26, count 0 2006.285.20:45:58.06#ibcon#end of sib2, iclass 26, count 0 2006.285.20:45:58.06#ibcon#*after write, iclass 26, count 0 2006.285.20:45:58.06#ibcon#*before return 0, iclass 26, count 0 2006.285.20:45:58.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:45:58.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:45:58.06#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.20:45:58.06#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.20:45:58.06$vck44/va=3,7 2006.285.20:45:58.06#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.20:45:58.06#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.20:45:58.06#ibcon#ireg 11 cls_cnt 2 2006.285.20:45:58.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:45:58.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:45:58.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:45:58.12#ibcon#enter wrdev, iclass 28, count 2 2006.285.20:45:58.12#ibcon#first serial, iclass 28, count 2 2006.285.20:45:58.12#ibcon#enter sib2, iclass 28, count 2 2006.285.20:45:58.12#ibcon#flushed, iclass 28, count 2 2006.285.20:45:58.12#ibcon#about to write, iclass 28, count 2 2006.285.20:45:58.12#ibcon#wrote, iclass 28, count 2 2006.285.20:45:58.12#ibcon#about to read 3, iclass 28, count 2 2006.285.20:45:58.14#ibcon#read 3, iclass 28, count 2 2006.285.20:45:58.14#ibcon#about to read 4, iclass 28, count 2 2006.285.20:45:58.14#ibcon#read 4, iclass 28, count 2 2006.285.20:45:58.14#ibcon#about to read 5, iclass 28, count 2 2006.285.20:45:58.14#ibcon#read 5, iclass 28, count 2 2006.285.20:45:58.14#ibcon#about to read 6, iclass 28, count 2 2006.285.20:45:58.14#ibcon#read 6, iclass 28, count 2 2006.285.20:45:58.14#ibcon#end of sib2, iclass 28, count 2 2006.285.20:45:58.14#ibcon#*mode == 0, iclass 28, count 2 2006.285.20:45:58.14#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.20:45:58.14#ibcon#[25=AT03-07\r\n] 2006.285.20:45:58.14#ibcon#*before write, iclass 28, count 2 2006.285.20:45:58.14#ibcon#enter sib2, iclass 28, count 2 2006.285.20:45:58.14#ibcon#flushed, iclass 28, count 2 2006.285.20:45:58.14#ibcon#about to write, iclass 28, count 2 2006.285.20:45:58.14#ibcon#wrote, iclass 28, count 2 2006.285.20:45:58.14#ibcon#about to read 3, iclass 28, count 2 2006.285.20:45:58.17#ibcon#read 3, iclass 28, count 2 2006.285.20:45:58.17#ibcon#about to read 4, iclass 28, count 2 2006.285.20:45:58.17#ibcon#read 4, iclass 28, count 2 2006.285.20:45:58.17#ibcon#about to read 5, iclass 28, count 2 2006.285.20:45:58.17#ibcon#read 5, iclass 28, count 2 2006.285.20:45:58.17#ibcon#about to read 6, iclass 28, count 2 2006.285.20:45:58.17#ibcon#read 6, iclass 28, count 2 2006.285.20:45:58.17#ibcon#end of sib2, iclass 28, count 2 2006.285.20:45:58.17#ibcon#*after write, iclass 28, count 2 2006.285.20:45:58.17#ibcon#*before return 0, iclass 28, count 2 2006.285.20:45:58.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:45:58.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:45:58.17#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.20:45:58.17#ibcon#ireg 7 cls_cnt 0 2006.285.20:45:58.17#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:45:58.29#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:45:58.29#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:45:58.29#ibcon#enter wrdev, iclass 28, count 0 2006.285.20:45:58.29#ibcon#first serial, iclass 28, count 0 2006.285.20:45:58.29#ibcon#enter sib2, iclass 28, count 0 2006.285.20:45:58.29#ibcon#flushed, iclass 28, count 0 2006.285.20:45:58.29#ibcon#about to write, iclass 28, count 0 2006.285.20:45:58.29#ibcon#wrote, iclass 28, count 0 2006.285.20:45:58.29#ibcon#about to read 3, iclass 28, count 0 2006.285.20:45:58.31#ibcon#read 3, iclass 28, count 0 2006.285.20:45:58.31#ibcon#about to read 4, iclass 28, count 0 2006.285.20:45:58.31#ibcon#read 4, iclass 28, count 0 2006.285.20:45:58.31#ibcon#about to read 5, iclass 28, count 0 2006.285.20:45:58.31#ibcon#read 5, iclass 28, count 0 2006.285.20:45:58.31#ibcon#about to read 6, iclass 28, count 0 2006.285.20:45:58.31#ibcon#read 6, iclass 28, count 0 2006.285.20:45:58.31#ibcon#end of sib2, iclass 28, count 0 2006.285.20:45:58.31#ibcon#*mode == 0, iclass 28, count 0 2006.285.20:45:58.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.20:45:58.31#ibcon#[25=USB\r\n] 2006.285.20:45:58.31#ibcon#*before write, iclass 28, count 0 2006.285.20:45:58.31#ibcon#enter sib2, iclass 28, count 0 2006.285.20:45:58.31#ibcon#flushed, iclass 28, count 0 2006.285.20:45:58.31#ibcon#about to write, iclass 28, count 0 2006.285.20:45:58.31#ibcon#wrote, iclass 28, count 0 2006.285.20:45:58.31#ibcon#about to read 3, iclass 28, count 0 2006.285.20:45:58.34#ibcon#read 3, iclass 28, count 0 2006.285.20:45:58.34#ibcon#about to read 4, iclass 28, count 0 2006.285.20:45:58.34#ibcon#read 4, iclass 28, count 0 2006.285.20:45:58.34#ibcon#about to read 5, iclass 28, count 0 2006.285.20:45:58.34#ibcon#read 5, iclass 28, count 0 2006.285.20:45:58.34#ibcon#about to read 6, iclass 28, count 0 2006.285.20:45:58.34#ibcon#read 6, iclass 28, count 0 2006.285.20:45:58.34#ibcon#end of sib2, iclass 28, count 0 2006.285.20:45:58.34#ibcon#*after write, iclass 28, count 0 2006.285.20:45:58.34#ibcon#*before return 0, iclass 28, count 0 2006.285.20:45:58.34#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:45:58.34#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:45:58.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.20:45:58.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.20:45:58.34$vck44/valo=4,624.99 2006.285.20:45:58.34#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.20:45:58.34#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.20:45:58.34#ibcon#ireg 17 cls_cnt 0 2006.285.20:45:58.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:45:58.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:45:58.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:45:58.34#ibcon#enter wrdev, iclass 30, count 0 2006.285.20:45:58.34#ibcon#first serial, iclass 30, count 0 2006.285.20:45:58.34#ibcon#enter sib2, iclass 30, count 0 2006.285.20:45:58.34#ibcon#flushed, iclass 30, count 0 2006.285.20:45:58.34#ibcon#about to write, iclass 30, count 0 2006.285.20:45:58.34#ibcon#wrote, iclass 30, count 0 2006.285.20:45:58.34#ibcon#about to read 3, iclass 30, count 0 2006.285.20:45:58.36#ibcon#read 3, iclass 30, count 0 2006.285.20:45:58.36#ibcon#about to read 4, iclass 30, count 0 2006.285.20:45:58.36#ibcon#read 4, iclass 30, count 0 2006.285.20:45:58.36#ibcon#about to read 5, iclass 30, count 0 2006.285.20:45:58.36#ibcon#read 5, iclass 30, count 0 2006.285.20:45:58.36#ibcon#about to read 6, iclass 30, count 0 2006.285.20:45:58.36#ibcon#read 6, iclass 30, count 0 2006.285.20:45:58.36#ibcon#end of sib2, iclass 30, count 0 2006.285.20:45:58.36#ibcon#*mode == 0, iclass 30, count 0 2006.285.20:45:58.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.20:45:58.36#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.20:45:58.36#ibcon#*before write, iclass 30, count 0 2006.285.20:45:58.36#ibcon#enter sib2, iclass 30, count 0 2006.285.20:45:58.36#ibcon#flushed, iclass 30, count 0 2006.285.20:45:58.36#ibcon#about to write, iclass 30, count 0 2006.285.20:45:58.36#ibcon#wrote, iclass 30, count 0 2006.285.20:45:58.36#ibcon#about to read 3, iclass 30, count 0 2006.285.20:45:58.40#ibcon#read 3, iclass 30, count 0 2006.285.20:45:58.40#ibcon#about to read 4, iclass 30, count 0 2006.285.20:45:58.40#ibcon#read 4, iclass 30, count 0 2006.285.20:45:58.40#ibcon#about to read 5, iclass 30, count 0 2006.285.20:45:58.40#ibcon#read 5, iclass 30, count 0 2006.285.20:45:58.40#ibcon#about to read 6, iclass 30, count 0 2006.285.20:45:58.40#ibcon#read 6, iclass 30, count 0 2006.285.20:45:58.40#ibcon#end of sib2, iclass 30, count 0 2006.285.20:45:58.40#ibcon#*after write, iclass 30, count 0 2006.285.20:45:58.40#ibcon#*before return 0, iclass 30, count 0 2006.285.20:45:58.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:45:58.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:45:58.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.20:45:58.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.20:45:58.40$vck44/va=4,6 2006.285.20:45:58.40#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.20:45:58.40#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.20:45:58.40#ibcon#ireg 11 cls_cnt 2 2006.285.20:45:58.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:45:58.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:45:58.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:45:58.46#ibcon#enter wrdev, iclass 32, count 2 2006.285.20:45:58.46#ibcon#first serial, iclass 32, count 2 2006.285.20:45:58.46#ibcon#enter sib2, iclass 32, count 2 2006.285.20:45:58.46#ibcon#flushed, iclass 32, count 2 2006.285.20:45:58.46#ibcon#about to write, iclass 32, count 2 2006.285.20:45:58.46#ibcon#wrote, iclass 32, count 2 2006.285.20:45:58.46#ibcon#about to read 3, iclass 32, count 2 2006.285.20:45:58.48#ibcon#read 3, iclass 32, count 2 2006.285.20:45:58.48#ibcon#about to read 4, iclass 32, count 2 2006.285.20:45:58.48#ibcon#read 4, iclass 32, count 2 2006.285.20:45:58.48#ibcon#about to read 5, iclass 32, count 2 2006.285.20:45:58.48#ibcon#read 5, iclass 32, count 2 2006.285.20:45:58.48#ibcon#about to read 6, iclass 32, count 2 2006.285.20:45:58.48#ibcon#read 6, iclass 32, count 2 2006.285.20:45:58.48#ibcon#end of sib2, iclass 32, count 2 2006.285.20:45:58.48#ibcon#*mode == 0, iclass 32, count 2 2006.285.20:45:58.48#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.20:45:58.48#ibcon#[25=AT04-06\r\n] 2006.285.20:45:58.48#ibcon#*before write, iclass 32, count 2 2006.285.20:45:58.48#ibcon#enter sib2, iclass 32, count 2 2006.285.20:45:58.48#ibcon#flushed, iclass 32, count 2 2006.285.20:45:58.48#ibcon#about to write, iclass 32, count 2 2006.285.20:45:58.48#ibcon#wrote, iclass 32, count 2 2006.285.20:45:58.48#ibcon#about to read 3, iclass 32, count 2 2006.285.20:45:58.51#ibcon#read 3, iclass 32, count 2 2006.285.20:45:58.78#ibcon#about to read 4, iclass 32, count 2 2006.285.20:45:58.78#ibcon#read 4, iclass 32, count 2 2006.285.20:45:58.78#ibcon#about to read 5, iclass 32, count 2 2006.285.20:45:58.78#ibcon#read 5, iclass 32, count 2 2006.285.20:45:58.78#ibcon#about to read 6, iclass 32, count 2 2006.285.20:45:58.78#ibcon#read 6, iclass 32, count 2 2006.285.20:45:58.78#ibcon#end of sib2, iclass 32, count 2 2006.285.20:45:58.78#ibcon#*after write, iclass 32, count 2 2006.285.20:45:58.78#ibcon#*before return 0, iclass 32, count 2 2006.285.20:45:58.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:45:58.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:45:58.78#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.20:45:58.78#ibcon#ireg 7 cls_cnt 0 2006.285.20:45:58.78#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:45:58.89#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:45:58.89#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:45:58.89#ibcon#enter wrdev, iclass 32, count 0 2006.285.20:45:58.89#ibcon#first serial, iclass 32, count 0 2006.285.20:45:58.89#ibcon#enter sib2, iclass 32, count 0 2006.285.20:45:58.89#ibcon#flushed, iclass 32, count 0 2006.285.20:45:58.89#ibcon#about to write, iclass 32, count 0 2006.285.20:45:58.89#ibcon#wrote, iclass 32, count 0 2006.285.20:45:58.89#ibcon#about to read 3, iclass 32, count 0 2006.285.20:45:58.91#ibcon#read 3, iclass 32, count 0 2006.285.20:45:58.91#ibcon#about to read 4, iclass 32, count 0 2006.285.20:45:58.91#ibcon#read 4, iclass 32, count 0 2006.285.20:45:58.91#ibcon#about to read 5, iclass 32, count 0 2006.285.20:45:58.91#ibcon#read 5, iclass 32, count 0 2006.285.20:45:58.91#ibcon#about to read 6, iclass 32, count 0 2006.285.20:45:58.91#ibcon#read 6, iclass 32, count 0 2006.285.20:45:58.91#ibcon#end of sib2, iclass 32, count 0 2006.285.20:45:58.91#ibcon#*mode == 0, iclass 32, count 0 2006.285.20:45:58.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.20:45:58.91#ibcon#[25=USB\r\n] 2006.285.20:45:58.91#ibcon#*before write, iclass 32, count 0 2006.285.20:45:58.91#ibcon#enter sib2, iclass 32, count 0 2006.285.20:45:58.91#ibcon#flushed, iclass 32, count 0 2006.285.20:45:58.91#ibcon#about to write, iclass 32, count 0 2006.285.20:45:58.91#ibcon#wrote, iclass 32, count 0 2006.285.20:45:58.91#ibcon#about to read 3, iclass 32, count 0 2006.285.20:45:58.94#ibcon#read 3, iclass 32, count 0 2006.285.20:45:58.94#ibcon#about to read 4, iclass 32, count 0 2006.285.20:45:58.94#ibcon#read 4, iclass 32, count 0 2006.285.20:45:58.94#ibcon#about to read 5, iclass 32, count 0 2006.285.20:45:58.94#ibcon#read 5, iclass 32, count 0 2006.285.20:45:58.94#ibcon#about to read 6, iclass 32, count 0 2006.285.20:45:58.94#ibcon#read 6, iclass 32, count 0 2006.285.20:45:58.94#ibcon#end of sib2, iclass 32, count 0 2006.285.20:45:58.94#ibcon#*after write, iclass 32, count 0 2006.285.20:45:58.94#ibcon#*before return 0, iclass 32, count 0 2006.285.20:45:58.94#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:45:58.94#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:45:58.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.20:45:58.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.20:45:58.94$vck44/valo=5,734.99 2006.285.20:45:58.94#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.20:45:58.94#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.20:45:58.94#ibcon#ireg 17 cls_cnt 0 2006.285.20:45:58.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:45:58.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:45:58.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:45:58.94#ibcon#enter wrdev, iclass 34, count 0 2006.285.20:45:58.94#ibcon#first serial, iclass 34, count 0 2006.285.20:45:58.94#ibcon#enter sib2, iclass 34, count 0 2006.285.20:45:58.94#ibcon#flushed, iclass 34, count 0 2006.285.20:45:58.94#ibcon#about to write, iclass 34, count 0 2006.285.20:45:58.94#ibcon#wrote, iclass 34, count 0 2006.285.20:45:58.94#ibcon#about to read 3, iclass 34, count 0 2006.285.20:45:58.96#ibcon#read 3, iclass 34, count 0 2006.285.20:45:58.96#ibcon#about to read 4, iclass 34, count 0 2006.285.20:45:58.96#ibcon#read 4, iclass 34, count 0 2006.285.20:45:58.96#ibcon#about to read 5, iclass 34, count 0 2006.285.20:45:58.96#ibcon#read 5, iclass 34, count 0 2006.285.20:45:58.96#ibcon#about to read 6, iclass 34, count 0 2006.285.20:45:58.96#ibcon#read 6, iclass 34, count 0 2006.285.20:45:58.96#ibcon#end of sib2, iclass 34, count 0 2006.285.20:45:58.96#ibcon#*mode == 0, iclass 34, count 0 2006.285.20:45:58.96#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.20:45:58.96#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.20:45:58.96#ibcon#*before write, iclass 34, count 0 2006.285.20:45:58.96#ibcon#enter sib2, iclass 34, count 0 2006.285.20:45:58.96#ibcon#flushed, iclass 34, count 0 2006.285.20:45:58.96#ibcon#about to write, iclass 34, count 0 2006.285.20:45:58.96#ibcon#wrote, iclass 34, count 0 2006.285.20:45:58.96#ibcon#about to read 3, iclass 34, count 0 2006.285.20:45:59.00#ibcon#read 3, iclass 34, count 0 2006.285.20:45:59.00#ibcon#about to read 4, iclass 34, count 0 2006.285.20:45:59.00#ibcon#read 4, iclass 34, count 0 2006.285.20:45:59.00#ibcon#about to read 5, iclass 34, count 0 2006.285.20:45:59.00#ibcon#read 5, iclass 34, count 0 2006.285.20:45:59.00#ibcon#about to read 6, iclass 34, count 0 2006.285.20:45:59.00#ibcon#read 6, iclass 34, count 0 2006.285.20:45:59.00#ibcon#end of sib2, iclass 34, count 0 2006.285.20:45:59.00#ibcon#*after write, iclass 34, count 0 2006.285.20:45:59.00#ibcon#*before return 0, iclass 34, count 0 2006.285.20:45:59.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:45:59.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:45:59.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.20:45:59.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.20:45:59.00$vck44/va=5,3 2006.285.20:45:59.00#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.20:45:59.00#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.20:45:59.00#ibcon#ireg 11 cls_cnt 2 2006.285.20:45:59.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:45:59.06#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:45:59.06#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:45:59.06#ibcon#enter wrdev, iclass 36, count 2 2006.285.20:45:59.06#ibcon#first serial, iclass 36, count 2 2006.285.20:45:59.06#ibcon#enter sib2, iclass 36, count 2 2006.285.20:45:59.06#ibcon#flushed, iclass 36, count 2 2006.285.20:45:59.06#ibcon#about to write, iclass 36, count 2 2006.285.20:45:59.06#ibcon#wrote, iclass 36, count 2 2006.285.20:45:59.06#ibcon#about to read 3, iclass 36, count 2 2006.285.20:45:59.08#ibcon#read 3, iclass 36, count 2 2006.285.20:45:59.08#ibcon#about to read 4, iclass 36, count 2 2006.285.20:45:59.08#ibcon#read 4, iclass 36, count 2 2006.285.20:45:59.08#ibcon#about to read 5, iclass 36, count 2 2006.285.20:45:59.08#ibcon#read 5, iclass 36, count 2 2006.285.20:45:59.08#ibcon#about to read 6, iclass 36, count 2 2006.285.20:45:59.08#ibcon#read 6, iclass 36, count 2 2006.285.20:45:59.08#ibcon#end of sib2, iclass 36, count 2 2006.285.20:45:59.08#ibcon#*mode == 0, iclass 36, count 2 2006.285.20:45:59.08#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.20:45:59.08#ibcon#[25=AT05-03\r\n] 2006.285.20:45:59.08#ibcon#*before write, iclass 36, count 2 2006.285.20:45:59.08#ibcon#enter sib2, iclass 36, count 2 2006.285.20:45:59.08#ibcon#flushed, iclass 36, count 2 2006.285.20:45:59.08#ibcon#about to write, iclass 36, count 2 2006.285.20:45:59.08#ibcon#wrote, iclass 36, count 2 2006.285.20:45:59.08#ibcon#about to read 3, iclass 36, count 2 2006.285.20:45:59.11#ibcon#read 3, iclass 36, count 2 2006.285.20:45:59.11#ibcon#about to read 4, iclass 36, count 2 2006.285.20:45:59.11#ibcon#read 4, iclass 36, count 2 2006.285.20:45:59.11#ibcon#about to read 5, iclass 36, count 2 2006.285.20:45:59.11#ibcon#read 5, iclass 36, count 2 2006.285.20:45:59.11#ibcon#about to read 6, iclass 36, count 2 2006.285.20:45:59.11#ibcon#read 6, iclass 36, count 2 2006.285.20:45:59.11#ibcon#end of sib2, iclass 36, count 2 2006.285.20:45:59.11#ibcon#*after write, iclass 36, count 2 2006.285.20:45:59.11#ibcon#*before return 0, iclass 36, count 2 2006.285.20:45:59.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:45:59.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:45:59.11#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.20:45:59.11#ibcon#ireg 7 cls_cnt 0 2006.285.20:45:59.11#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:45:59.23#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:45:59.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:45:59.47#ibcon#enter wrdev, iclass 36, count 0 2006.285.20:45:59.47#ibcon#first serial, iclass 36, count 0 2006.285.20:45:59.47#ibcon#enter sib2, iclass 36, count 0 2006.285.20:45:59.47#ibcon#flushed, iclass 36, count 0 2006.285.20:45:59.47#ibcon#about to write, iclass 36, count 0 2006.285.20:45:59.47#ibcon#wrote, iclass 36, count 0 2006.285.20:45:59.47#ibcon#about to read 3, iclass 36, count 0 2006.285.20:45:59.48#ibcon#read 3, iclass 36, count 0 2006.285.20:45:59.48#ibcon#about to read 4, iclass 36, count 0 2006.285.20:45:59.48#ibcon#read 4, iclass 36, count 0 2006.285.20:45:59.48#ibcon#about to read 5, iclass 36, count 0 2006.285.20:45:59.48#ibcon#read 5, iclass 36, count 0 2006.285.20:45:59.48#ibcon#about to read 6, iclass 36, count 0 2006.285.20:45:59.48#ibcon#read 6, iclass 36, count 0 2006.285.20:45:59.48#ibcon#end of sib2, iclass 36, count 0 2006.285.20:45:59.48#ibcon#*mode == 0, iclass 36, count 0 2006.285.20:45:59.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.20:45:59.48#ibcon#[25=USB\r\n] 2006.285.20:45:59.48#ibcon#*before write, iclass 36, count 0 2006.285.20:45:59.48#ibcon#enter sib2, iclass 36, count 0 2006.285.20:45:59.48#ibcon#flushed, iclass 36, count 0 2006.285.20:45:59.48#ibcon#about to write, iclass 36, count 0 2006.285.20:45:59.48#ibcon#wrote, iclass 36, count 0 2006.285.20:45:59.48#ibcon#about to read 3, iclass 36, count 0 2006.285.20:45:59.51#ibcon#read 3, iclass 36, count 0 2006.285.20:45:59.51#ibcon#about to read 4, iclass 36, count 0 2006.285.20:45:59.51#ibcon#read 4, iclass 36, count 0 2006.285.20:45:59.51#ibcon#about to read 5, iclass 36, count 0 2006.285.20:45:59.51#ibcon#read 5, iclass 36, count 0 2006.285.20:45:59.51#ibcon#about to read 6, iclass 36, count 0 2006.285.20:45:59.51#ibcon#read 6, iclass 36, count 0 2006.285.20:45:59.51#ibcon#end of sib2, iclass 36, count 0 2006.285.20:45:59.51#ibcon#*after write, iclass 36, count 0 2006.285.20:45:59.51#ibcon#*before return 0, iclass 36, count 0 2006.285.20:45:59.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:45:59.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:45:59.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.20:45:59.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.20:45:59.51$vck44/valo=6,814.99 2006.285.20:45:59.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.20:45:59.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.20:45:59.51#ibcon#ireg 17 cls_cnt 0 2006.285.20:45:59.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:45:59.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:45:59.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:45:59.51#ibcon#enter wrdev, iclass 38, count 0 2006.285.20:45:59.51#ibcon#first serial, iclass 38, count 0 2006.285.20:45:59.51#ibcon#enter sib2, iclass 38, count 0 2006.285.20:45:59.51#ibcon#flushed, iclass 38, count 0 2006.285.20:45:59.51#ibcon#about to write, iclass 38, count 0 2006.285.20:45:59.51#ibcon#wrote, iclass 38, count 0 2006.285.20:45:59.51#ibcon#about to read 3, iclass 38, count 0 2006.285.20:45:59.53#ibcon#read 3, iclass 38, count 0 2006.285.20:45:59.53#ibcon#about to read 4, iclass 38, count 0 2006.285.20:45:59.53#ibcon#read 4, iclass 38, count 0 2006.285.20:45:59.53#ibcon#about to read 5, iclass 38, count 0 2006.285.20:45:59.53#ibcon#read 5, iclass 38, count 0 2006.285.20:45:59.53#ibcon#about to read 6, iclass 38, count 0 2006.285.20:45:59.53#ibcon#read 6, iclass 38, count 0 2006.285.20:45:59.53#ibcon#end of sib2, iclass 38, count 0 2006.285.20:45:59.53#ibcon#*mode == 0, iclass 38, count 0 2006.285.20:45:59.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.20:45:59.53#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.20:45:59.53#ibcon#*before write, iclass 38, count 0 2006.285.20:45:59.53#ibcon#enter sib2, iclass 38, count 0 2006.285.20:45:59.53#ibcon#flushed, iclass 38, count 0 2006.285.20:45:59.53#ibcon#about to write, iclass 38, count 0 2006.285.20:45:59.53#ibcon#wrote, iclass 38, count 0 2006.285.20:45:59.53#ibcon#about to read 3, iclass 38, count 0 2006.285.20:45:59.57#ibcon#read 3, iclass 38, count 0 2006.285.20:45:59.57#ibcon#about to read 4, iclass 38, count 0 2006.285.20:45:59.57#ibcon#read 4, iclass 38, count 0 2006.285.20:45:59.57#ibcon#about to read 5, iclass 38, count 0 2006.285.20:45:59.57#ibcon#read 5, iclass 38, count 0 2006.285.20:45:59.57#ibcon#about to read 6, iclass 38, count 0 2006.285.20:45:59.57#ibcon#read 6, iclass 38, count 0 2006.285.20:45:59.57#ibcon#end of sib2, iclass 38, count 0 2006.285.20:45:59.57#ibcon#*after write, iclass 38, count 0 2006.285.20:45:59.57#ibcon#*before return 0, iclass 38, count 0 2006.285.20:45:59.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:45:59.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:45:59.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.20:45:59.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.20:45:59.57$vck44/va=6,4 2006.285.20:45:59.57#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.20:45:59.57#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.20:45:59.57#ibcon#ireg 11 cls_cnt 2 2006.285.20:45:59.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:45:59.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:45:59.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:45:59.63#ibcon#enter wrdev, iclass 40, count 2 2006.285.20:45:59.63#ibcon#first serial, iclass 40, count 2 2006.285.20:45:59.63#ibcon#enter sib2, iclass 40, count 2 2006.285.20:45:59.63#ibcon#flushed, iclass 40, count 2 2006.285.20:45:59.63#ibcon#about to write, iclass 40, count 2 2006.285.20:45:59.63#ibcon#wrote, iclass 40, count 2 2006.285.20:45:59.63#ibcon#about to read 3, iclass 40, count 2 2006.285.20:45:59.65#ibcon#read 3, iclass 40, count 2 2006.285.20:45:59.65#ibcon#about to read 4, iclass 40, count 2 2006.285.20:45:59.65#ibcon#read 4, iclass 40, count 2 2006.285.20:45:59.65#ibcon#about to read 5, iclass 40, count 2 2006.285.20:45:59.65#ibcon#read 5, iclass 40, count 2 2006.285.20:45:59.65#ibcon#about to read 6, iclass 40, count 2 2006.285.20:45:59.65#ibcon#read 6, iclass 40, count 2 2006.285.20:45:59.65#ibcon#end of sib2, iclass 40, count 2 2006.285.20:45:59.65#ibcon#*mode == 0, iclass 40, count 2 2006.285.20:45:59.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.20:45:59.65#ibcon#[25=AT06-04\r\n] 2006.285.20:45:59.65#ibcon#*before write, iclass 40, count 2 2006.285.20:45:59.65#ibcon#enter sib2, iclass 40, count 2 2006.285.20:45:59.65#ibcon#flushed, iclass 40, count 2 2006.285.20:45:59.65#ibcon#about to write, iclass 40, count 2 2006.285.20:45:59.65#ibcon#wrote, iclass 40, count 2 2006.285.20:45:59.65#ibcon#about to read 3, iclass 40, count 2 2006.285.20:45:59.68#ibcon#read 3, iclass 40, count 2 2006.285.20:45:59.68#ibcon#about to read 4, iclass 40, count 2 2006.285.20:45:59.68#ibcon#read 4, iclass 40, count 2 2006.285.20:45:59.68#ibcon#about to read 5, iclass 40, count 2 2006.285.20:45:59.68#ibcon#read 5, iclass 40, count 2 2006.285.20:45:59.68#ibcon#about to read 6, iclass 40, count 2 2006.285.20:45:59.68#ibcon#read 6, iclass 40, count 2 2006.285.20:45:59.68#ibcon#end of sib2, iclass 40, count 2 2006.285.20:45:59.68#ibcon#*after write, iclass 40, count 2 2006.285.20:45:59.68#ibcon#*before return 0, iclass 40, count 2 2006.285.20:45:59.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:45:59.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:45:59.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.20:45:59.68#ibcon#ireg 7 cls_cnt 0 2006.285.20:45:59.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:45:59.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:45:59.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:45:59.80#ibcon#enter wrdev, iclass 40, count 0 2006.285.20:45:59.80#ibcon#first serial, iclass 40, count 0 2006.285.20:45:59.80#ibcon#enter sib2, iclass 40, count 0 2006.285.20:45:59.80#ibcon#flushed, iclass 40, count 0 2006.285.20:45:59.80#ibcon#about to write, iclass 40, count 0 2006.285.20:45:59.80#ibcon#wrote, iclass 40, count 0 2006.285.20:45:59.80#ibcon#about to read 3, iclass 40, count 0 2006.285.20:45:59.82#ibcon#read 3, iclass 40, count 0 2006.285.20:45:59.82#ibcon#about to read 4, iclass 40, count 0 2006.285.20:45:59.82#ibcon#read 4, iclass 40, count 0 2006.285.20:45:59.82#ibcon#about to read 5, iclass 40, count 0 2006.285.20:45:59.82#ibcon#read 5, iclass 40, count 0 2006.285.20:45:59.82#ibcon#about to read 6, iclass 40, count 0 2006.285.20:45:59.82#ibcon#read 6, iclass 40, count 0 2006.285.20:45:59.84#ibcon#end of sib2, iclass 40, count 0 2006.285.20:45:59.84#ibcon#*mode == 0, iclass 40, count 0 2006.285.20:45:59.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.20:45:59.84#ibcon#[25=USB\r\n] 2006.285.20:45:59.84#ibcon#*before write, iclass 40, count 0 2006.285.20:45:59.84#ibcon#enter sib2, iclass 40, count 0 2006.285.20:45:59.84#ibcon#flushed, iclass 40, count 0 2006.285.20:45:59.84#ibcon#about to write, iclass 40, count 0 2006.285.20:45:59.84#ibcon#wrote, iclass 40, count 0 2006.285.20:45:59.84#ibcon#about to read 3, iclass 40, count 0 2006.285.20:45:59.87#ibcon#read 3, iclass 40, count 0 2006.285.20:45:59.87#ibcon#about to read 4, iclass 40, count 0 2006.285.20:45:59.87#ibcon#read 4, iclass 40, count 0 2006.285.20:45:59.87#ibcon#about to read 5, iclass 40, count 0 2006.285.20:45:59.87#ibcon#read 5, iclass 40, count 0 2006.285.20:45:59.87#ibcon#about to read 6, iclass 40, count 0 2006.285.20:45:59.87#ibcon#read 6, iclass 40, count 0 2006.285.20:45:59.87#ibcon#end of sib2, iclass 40, count 0 2006.285.20:45:59.87#ibcon#*after write, iclass 40, count 0 2006.285.20:45:59.87#ibcon#*before return 0, iclass 40, count 0 2006.285.20:45:59.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:45:59.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:45:59.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.20:45:59.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.20:45:59.87$vck44/valo=7,864.99 2006.285.20:45:59.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.20:45:59.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.20:45:59.87#ibcon#ireg 17 cls_cnt 0 2006.285.20:45:59.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:45:59.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:45:59.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:45:59.87#ibcon#enter wrdev, iclass 4, count 0 2006.285.20:45:59.87#ibcon#first serial, iclass 4, count 0 2006.285.20:45:59.87#ibcon#enter sib2, iclass 4, count 0 2006.285.20:45:59.87#ibcon#flushed, iclass 4, count 0 2006.285.20:45:59.87#ibcon#about to write, iclass 4, count 0 2006.285.20:45:59.87#ibcon#wrote, iclass 4, count 0 2006.285.20:45:59.87#ibcon#about to read 3, iclass 4, count 0 2006.285.20:45:59.89#ibcon#read 3, iclass 4, count 0 2006.285.20:45:59.89#ibcon#about to read 4, iclass 4, count 0 2006.285.20:45:59.89#ibcon#read 4, iclass 4, count 0 2006.285.20:45:59.89#ibcon#about to read 5, iclass 4, count 0 2006.285.20:45:59.89#ibcon#read 5, iclass 4, count 0 2006.285.20:45:59.89#ibcon#about to read 6, iclass 4, count 0 2006.285.20:45:59.89#ibcon#read 6, iclass 4, count 0 2006.285.20:45:59.89#ibcon#end of sib2, iclass 4, count 0 2006.285.20:45:59.89#ibcon#*mode == 0, iclass 4, count 0 2006.285.20:45:59.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.20:45:59.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.20:45:59.89#ibcon#*before write, iclass 4, count 0 2006.285.20:45:59.89#ibcon#enter sib2, iclass 4, count 0 2006.285.20:45:59.89#ibcon#flushed, iclass 4, count 0 2006.285.20:45:59.89#ibcon#about to write, iclass 4, count 0 2006.285.20:45:59.89#ibcon#wrote, iclass 4, count 0 2006.285.20:45:59.89#ibcon#about to read 3, iclass 4, count 0 2006.285.20:45:59.93#ibcon#read 3, iclass 4, count 0 2006.285.20:45:59.93#ibcon#about to read 4, iclass 4, count 0 2006.285.20:45:59.93#ibcon#read 4, iclass 4, count 0 2006.285.20:45:59.93#ibcon#about to read 5, iclass 4, count 0 2006.285.20:45:59.93#ibcon#read 5, iclass 4, count 0 2006.285.20:45:59.93#ibcon#about to read 6, iclass 4, count 0 2006.285.20:45:59.93#ibcon#read 6, iclass 4, count 0 2006.285.20:45:59.93#ibcon#end of sib2, iclass 4, count 0 2006.285.20:45:59.93#ibcon#*after write, iclass 4, count 0 2006.285.20:45:59.93#ibcon#*before return 0, iclass 4, count 0 2006.285.20:45:59.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:45:59.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:45:59.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.20:45:59.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.20:45:59.93$vck44/va=7,4 2006.285.20:45:59.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.20:45:59.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.20:45:59.93#ibcon#ireg 11 cls_cnt 2 2006.285.20:45:59.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:45:59.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:45:59.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:45:59.99#ibcon#enter wrdev, iclass 6, count 2 2006.285.20:45:59.99#ibcon#first serial, iclass 6, count 2 2006.285.20:45:59.99#ibcon#enter sib2, iclass 6, count 2 2006.285.20:45:59.99#ibcon#flushed, iclass 6, count 2 2006.285.20:45:59.99#ibcon#about to write, iclass 6, count 2 2006.285.20:45:59.99#ibcon#wrote, iclass 6, count 2 2006.285.20:45:59.99#ibcon#about to read 3, iclass 6, count 2 2006.285.20:46:00.01#ibcon#read 3, iclass 6, count 2 2006.285.20:46:00.01#ibcon#about to read 4, iclass 6, count 2 2006.285.20:46:00.01#ibcon#read 4, iclass 6, count 2 2006.285.20:46:00.01#ibcon#about to read 5, iclass 6, count 2 2006.285.20:46:00.01#ibcon#read 5, iclass 6, count 2 2006.285.20:46:00.01#ibcon#about to read 6, iclass 6, count 2 2006.285.20:46:00.01#ibcon#read 6, iclass 6, count 2 2006.285.20:46:00.01#ibcon#end of sib2, iclass 6, count 2 2006.285.20:46:00.01#ibcon#*mode == 0, iclass 6, count 2 2006.285.20:46:00.01#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.20:46:00.01#ibcon#[25=AT07-04\r\n] 2006.285.20:46:00.01#ibcon#*before write, iclass 6, count 2 2006.285.20:46:00.01#ibcon#enter sib2, iclass 6, count 2 2006.285.20:46:00.01#ibcon#flushed, iclass 6, count 2 2006.285.20:46:00.01#ibcon#about to write, iclass 6, count 2 2006.285.20:46:00.01#ibcon#wrote, iclass 6, count 2 2006.285.20:46:00.01#ibcon#about to read 3, iclass 6, count 2 2006.285.20:46:00.04#ibcon#read 3, iclass 6, count 2 2006.285.20:46:00.04#ibcon#about to read 4, iclass 6, count 2 2006.285.20:46:00.04#ibcon#read 4, iclass 6, count 2 2006.285.20:46:00.04#ibcon#about to read 5, iclass 6, count 2 2006.285.20:46:00.04#ibcon#read 5, iclass 6, count 2 2006.285.20:46:00.04#ibcon#about to read 6, iclass 6, count 2 2006.285.20:46:00.04#ibcon#read 6, iclass 6, count 2 2006.285.20:46:00.04#ibcon#end of sib2, iclass 6, count 2 2006.285.20:46:00.04#ibcon#*after write, iclass 6, count 2 2006.285.20:46:00.04#ibcon#*before return 0, iclass 6, count 2 2006.285.20:46:00.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:46:00.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:46:00.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.20:46:00.04#ibcon#ireg 7 cls_cnt 0 2006.285.20:46:00.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:46:00.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:46:00.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:46:00.16#ibcon#enter wrdev, iclass 6, count 0 2006.285.20:46:00.16#ibcon#first serial, iclass 6, count 0 2006.285.20:46:00.16#ibcon#enter sib2, iclass 6, count 0 2006.285.20:46:00.16#ibcon#flushed, iclass 6, count 0 2006.285.20:46:00.16#ibcon#about to write, iclass 6, count 0 2006.285.20:46:00.16#ibcon#wrote, iclass 6, count 0 2006.285.20:46:00.16#ibcon#about to read 3, iclass 6, count 0 2006.285.20:46:00.18#ibcon#read 3, iclass 6, count 0 2006.285.20:46:00.18#ibcon#about to read 4, iclass 6, count 0 2006.285.20:46:00.18#ibcon#read 4, iclass 6, count 0 2006.285.20:46:00.18#ibcon#about to read 5, iclass 6, count 0 2006.285.20:46:00.18#ibcon#read 5, iclass 6, count 0 2006.285.20:46:00.18#ibcon#about to read 6, iclass 6, count 0 2006.285.20:46:00.18#ibcon#read 6, iclass 6, count 0 2006.285.20:46:00.18#ibcon#end of sib2, iclass 6, count 0 2006.285.20:46:00.18#ibcon#*mode == 0, iclass 6, count 0 2006.285.20:46:00.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.20:46:00.18#ibcon#[25=USB\r\n] 2006.285.20:46:00.18#ibcon#*before write, iclass 6, count 0 2006.285.20:46:00.18#ibcon#enter sib2, iclass 6, count 0 2006.285.20:46:00.18#ibcon#flushed, iclass 6, count 0 2006.285.20:46:00.18#ibcon#about to write, iclass 6, count 0 2006.285.20:46:00.18#ibcon#wrote, iclass 6, count 0 2006.285.20:46:00.18#ibcon#about to read 3, iclass 6, count 0 2006.285.20:46:00.21#ibcon#read 3, iclass 6, count 0 2006.285.20:46:00.21#ibcon#about to read 4, iclass 6, count 0 2006.285.20:46:00.21#ibcon#read 4, iclass 6, count 0 2006.285.20:46:00.21#ibcon#about to read 5, iclass 6, count 0 2006.285.20:46:00.21#ibcon#read 5, iclass 6, count 0 2006.285.20:46:00.21#ibcon#about to read 6, iclass 6, count 0 2006.285.20:46:00.21#ibcon#read 6, iclass 6, count 0 2006.285.20:46:00.21#ibcon#end of sib2, iclass 6, count 0 2006.285.20:46:00.21#ibcon#*after write, iclass 6, count 0 2006.285.20:46:00.21#ibcon#*before return 0, iclass 6, count 0 2006.285.20:46:00.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:46:00.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:46:00.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.20:46:00.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.20:46:00.21$vck44/valo=8,884.99 2006.285.20:46:00.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.20:46:00.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.20:46:00.21#ibcon#ireg 17 cls_cnt 0 2006.285.20:46:00.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:46:00.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:46:00.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:46:00.21#ibcon#enter wrdev, iclass 10, count 0 2006.285.20:46:00.21#ibcon#first serial, iclass 10, count 0 2006.285.20:46:00.21#ibcon#enter sib2, iclass 10, count 0 2006.285.20:46:00.21#ibcon#flushed, iclass 10, count 0 2006.285.20:46:00.21#ibcon#about to write, iclass 10, count 0 2006.285.20:46:00.21#ibcon#wrote, iclass 10, count 0 2006.285.20:46:00.21#ibcon#about to read 3, iclass 10, count 0 2006.285.20:46:00.23#ibcon#read 3, iclass 10, count 0 2006.285.20:46:00.23#ibcon#about to read 4, iclass 10, count 0 2006.285.20:46:00.23#ibcon#read 4, iclass 10, count 0 2006.285.20:46:00.23#ibcon#about to read 5, iclass 10, count 0 2006.285.20:46:00.23#ibcon#read 5, iclass 10, count 0 2006.285.20:46:00.23#ibcon#about to read 6, iclass 10, count 0 2006.285.20:46:00.23#ibcon#read 6, iclass 10, count 0 2006.285.20:46:00.23#ibcon#end of sib2, iclass 10, count 0 2006.285.20:46:00.23#ibcon#*mode == 0, iclass 10, count 0 2006.285.20:46:00.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.20:46:00.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.20:46:00.23#ibcon#*before write, iclass 10, count 0 2006.285.20:46:00.23#ibcon#enter sib2, iclass 10, count 0 2006.285.20:46:00.23#ibcon#flushed, iclass 10, count 0 2006.285.20:46:00.23#ibcon#about to write, iclass 10, count 0 2006.285.20:46:00.23#ibcon#wrote, iclass 10, count 0 2006.285.20:46:00.23#ibcon#about to read 3, iclass 10, count 0 2006.285.20:46:00.27#ibcon#read 3, iclass 10, count 0 2006.285.20:46:00.27#ibcon#about to read 4, iclass 10, count 0 2006.285.20:46:00.27#ibcon#read 4, iclass 10, count 0 2006.285.20:46:00.27#ibcon#about to read 5, iclass 10, count 0 2006.285.20:46:00.27#ibcon#read 5, iclass 10, count 0 2006.285.20:46:00.27#ibcon#about to read 6, iclass 10, count 0 2006.285.20:46:00.27#ibcon#read 6, iclass 10, count 0 2006.285.20:46:00.27#ibcon#end of sib2, iclass 10, count 0 2006.285.20:46:00.27#ibcon#*after write, iclass 10, count 0 2006.285.20:46:00.27#ibcon#*before return 0, iclass 10, count 0 2006.285.20:46:00.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:46:00.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:46:00.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.20:46:00.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.20:46:00.27$vck44/va=8,3 2006.285.20:46:00.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.20:46:00.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.20:46:00.27#ibcon#ireg 11 cls_cnt 2 2006.285.20:46:00.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.20:46:00.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.20:46:00.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.20:46:00.33#ibcon#enter wrdev, iclass 12, count 2 2006.285.20:46:00.33#ibcon#first serial, iclass 12, count 2 2006.285.20:46:00.33#ibcon#enter sib2, iclass 12, count 2 2006.285.20:46:00.33#ibcon#flushed, iclass 12, count 2 2006.285.20:46:00.33#ibcon#about to write, iclass 12, count 2 2006.285.20:46:00.33#ibcon#wrote, iclass 12, count 2 2006.285.20:46:00.33#ibcon#about to read 3, iclass 12, count 2 2006.285.20:46:00.35#ibcon#read 3, iclass 12, count 2 2006.285.20:46:00.35#ibcon#about to read 4, iclass 12, count 2 2006.285.20:46:00.35#ibcon#read 4, iclass 12, count 2 2006.285.20:46:00.35#ibcon#about to read 5, iclass 12, count 2 2006.285.20:46:00.35#ibcon#read 5, iclass 12, count 2 2006.285.20:46:00.35#ibcon#about to read 6, iclass 12, count 2 2006.285.20:46:00.35#ibcon#read 6, iclass 12, count 2 2006.285.20:46:00.35#ibcon#end of sib2, iclass 12, count 2 2006.285.20:46:00.35#ibcon#*mode == 0, iclass 12, count 2 2006.285.20:46:00.35#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.20:46:00.35#ibcon#[25=AT08-03\r\n] 2006.285.20:46:00.35#ibcon#*before write, iclass 12, count 2 2006.285.20:46:00.35#ibcon#enter sib2, iclass 12, count 2 2006.285.20:46:00.35#ibcon#flushed, iclass 12, count 2 2006.285.20:46:00.35#ibcon#about to write, iclass 12, count 2 2006.285.20:46:00.35#ibcon#wrote, iclass 12, count 2 2006.285.20:46:00.35#ibcon#about to read 3, iclass 12, count 2 2006.285.20:46:00.38#ibcon#read 3, iclass 12, count 2 2006.285.20:46:00.38#ibcon#about to read 4, iclass 12, count 2 2006.285.20:46:00.38#ibcon#read 4, iclass 12, count 2 2006.285.20:46:00.38#ibcon#about to read 5, iclass 12, count 2 2006.285.20:46:00.38#ibcon#read 5, iclass 12, count 2 2006.285.20:46:00.38#ibcon#about to read 6, iclass 12, count 2 2006.285.20:46:00.38#ibcon#read 6, iclass 12, count 2 2006.285.20:46:00.38#ibcon#end of sib2, iclass 12, count 2 2006.285.20:46:00.38#ibcon#*after write, iclass 12, count 2 2006.285.20:46:00.38#ibcon#*before return 0, iclass 12, count 2 2006.285.20:46:00.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.20:46:00.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.20:46:00.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.20:46:00.38#ibcon#ireg 7 cls_cnt 0 2006.285.20:46:00.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.20:46:00.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.20:46:00.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.20:46:00.50#ibcon#enter wrdev, iclass 12, count 0 2006.285.20:46:00.50#ibcon#first serial, iclass 12, count 0 2006.285.20:46:00.50#ibcon#enter sib2, iclass 12, count 0 2006.285.20:46:00.50#ibcon#flushed, iclass 12, count 0 2006.285.20:46:00.50#ibcon#about to write, iclass 12, count 0 2006.285.20:46:00.50#ibcon#wrote, iclass 12, count 0 2006.285.20:46:00.50#ibcon#about to read 3, iclass 12, count 0 2006.285.20:46:00.52#ibcon#read 3, iclass 12, count 0 2006.285.20:46:00.52#ibcon#about to read 4, iclass 12, count 0 2006.285.20:46:00.52#ibcon#read 4, iclass 12, count 0 2006.285.20:46:00.52#ibcon#about to read 5, iclass 12, count 0 2006.285.20:46:00.52#ibcon#read 5, iclass 12, count 0 2006.285.20:46:00.52#ibcon#about to read 6, iclass 12, count 0 2006.285.20:46:00.52#ibcon#read 6, iclass 12, count 0 2006.285.20:46:00.52#ibcon#end of sib2, iclass 12, count 0 2006.285.20:46:00.52#ibcon#*mode == 0, iclass 12, count 0 2006.285.20:46:00.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.20:46:00.52#ibcon#[25=USB\r\n] 2006.285.20:46:00.52#ibcon#*before write, iclass 12, count 0 2006.285.20:46:00.52#ibcon#enter sib2, iclass 12, count 0 2006.285.20:46:00.52#ibcon#flushed, iclass 12, count 0 2006.285.20:46:00.52#ibcon#about to write, iclass 12, count 0 2006.285.20:46:00.52#ibcon#wrote, iclass 12, count 0 2006.285.20:46:00.52#ibcon#about to read 3, iclass 12, count 0 2006.285.20:46:00.55#ibcon#read 3, iclass 12, count 0 2006.285.20:46:00.55#ibcon#about to read 4, iclass 12, count 0 2006.285.20:46:00.55#ibcon#read 4, iclass 12, count 0 2006.285.20:46:00.55#ibcon#about to read 5, iclass 12, count 0 2006.285.20:46:00.55#ibcon#read 5, iclass 12, count 0 2006.285.20:46:00.55#ibcon#about to read 6, iclass 12, count 0 2006.285.20:46:00.55#ibcon#read 6, iclass 12, count 0 2006.285.20:46:00.55#ibcon#end of sib2, iclass 12, count 0 2006.285.20:46:00.55#ibcon#*after write, iclass 12, count 0 2006.285.20:46:00.55#ibcon#*before return 0, iclass 12, count 0 2006.285.20:46:00.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.20:46:00.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.20:46:00.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.20:46:00.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.20:46:00.55$vck44/vblo=1,629.99 2006.285.20:46:00.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.20:46:00.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.20:46:00.55#ibcon#ireg 17 cls_cnt 0 2006.285.20:46:00.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:46:00.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:46:00.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:46:00.55#ibcon#enter wrdev, iclass 14, count 0 2006.285.20:46:00.55#ibcon#first serial, iclass 14, count 0 2006.285.20:46:00.55#ibcon#enter sib2, iclass 14, count 0 2006.285.20:46:00.55#ibcon#flushed, iclass 14, count 0 2006.285.20:46:00.55#ibcon#about to write, iclass 14, count 0 2006.285.20:46:00.55#ibcon#wrote, iclass 14, count 0 2006.285.20:46:00.55#ibcon#about to read 3, iclass 14, count 0 2006.285.20:46:00.57#ibcon#read 3, iclass 14, count 0 2006.285.20:46:00.62#ibcon#about to read 4, iclass 14, count 0 2006.285.20:46:00.62#ibcon#read 4, iclass 14, count 0 2006.285.20:46:00.62#ibcon#about to read 5, iclass 14, count 0 2006.285.20:46:00.62#ibcon#read 5, iclass 14, count 0 2006.285.20:46:00.62#ibcon#about to read 6, iclass 14, count 0 2006.285.20:46:00.62#ibcon#read 6, iclass 14, count 0 2006.285.20:46:00.62#ibcon#end of sib2, iclass 14, count 0 2006.285.20:46:00.62#ibcon#*mode == 0, iclass 14, count 0 2006.285.20:46:00.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.20:46:00.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.20:46:00.62#ibcon#*before write, iclass 14, count 0 2006.285.20:46:00.62#ibcon#enter sib2, iclass 14, count 0 2006.285.20:46:00.62#ibcon#flushed, iclass 14, count 0 2006.285.20:46:00.62#ibcon#about to write, iclass 14, count 0 2006.285.20:46:00.62#ibcon#wrote, iclass 14, count 0 2006.285.20:46:00.62#ibcon#about to read 3, iclass 14, count 0 2006.285.20:46:00.66#ibcon#read 3, iclass 14, count 0 2006.285.20:46:00.66#ibcon#about to read 4, iclass 14, count 0 2006.285.20:46:00.66#ibcon#read 4, iclass 14, count 0 2006.285.20:46:00.66#ibcon#about to read 5, iclass 14, count 0 2006.285.20:46:00.66#ibcon#read 5, iclass 14, count 0 2006.285.20:46:00.66#ibcon#about to read 6, iclass 14, count 0 2006.285.20:46:00.66#ibcon#read 6, iclass 14, count 0 2006.285.20:46:00.66#ibcon#end of sib2, iclass 14, count 0 2006.285.20:46:00.66#ibcon#*after write, iclass 14, count 0 2006.285.20:46:00.66#ibcon#*before return 0, iclass 14, count 0 2006.285.20:46:00.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:46:00.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.20:46:00.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.20:46:00.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.20:46:00.66$vck44/vb=1,4 2006.285.20:46:00.66#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.20:46:00.66#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.20:46:00.66#ibcon#ireg 11 cls_cnt 2 2006.285.20:46:00.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:46:00.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:46:00.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:46:00.66#ibcon#enter wrdev, iclass 16, count 2 2006.285.20:46:00.66#ibcon#first serial, iclass 16, count 2 2006.285.20:46:00.66#ibcon#enter sib2, iclass 16, count 2 2006.285.20:46:00.66#ibcon#flushed, iclass 16, count 2 2006.285.20:46:00.66#ibcon#about to write, iclass 16, count 2 2006.285.20:46:00.67#ibcon#wrote, iclass 16, count 2 2006.285.20:46:00.67#ibcon#about to read 3, iclass 16, count 2 2006.285.20:46:00.68#ibcon#read 3, iclass 16, count 2 2006.285.20:46:00.68#ibcon#about to read 4, iclass 16, count 2 2006.285.20:46:00.68#ibcon#read 4, iclass 16, count 2 2006.285.20:46:00.68#ibcon#about to read 5, iclass 16, count 2 2006.285.20:46:00.68#ibcon#read 5, iclass 16, count 2 2006.285.20:46:00.68#ibcon#about to read 6, iclass 16, count 2 2006.285.20:46:00.68#ibcon#read 6, iclass 16, count 2 2006.285.20:46:00.68#ibcon#end of sib2, iclass 16, count 2 2006.285.20:46:00.68#ibcon#*mode == 0, iclass 16, count 2 2006.285.20:46:00.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.20:46:00.68#ibcon#[27=AT01-04\r\n] 2006.285.20:46:00.68#ibcon#*before write, iclass 16, count 2 2006.285.20:46:00.68#ibcon#enter sib2, iclass 16, count 2 2006.285.20:46:00.68#ibcon#flushed, iclass 16, count 2 2006.285.20:46:00.68#ibcon#about to write, iclass 16, count 2 2006.285.20:46:00.68#ibcon#wrote, iclass 16, count 2 2006.285.20:46:00.68#ibcon#about to read 3, iclass 16, count 2 2006.285.20:46:00.71#ibcon#read 3, iclass 16, count 2 2006.285.20:46:00.71#ibcon#about to read 4, iclass 16, count 2 2006.285.20:46:00.71#ibcon#read 4, iclass 16, count 2 2006.285.20:46:00.71#ibcon#about to read 5, iclass 16, count 2 2006.285.20:46:00.71#ibcon#read 5, iclass 16, count 2 2006.285.20:46:00.71#ibcon#about to read 6, iclass 16, count 2 2006.285.20:46:00.71#ibcon#read 6, iclass 16, count 2 2006.285.20:46:00.71#ibcon#end of sib2, iclass 16, count 2 2006.285.20:46:00.71#ibcon#*after write, iclass 16, count 2 2006.285.20:46:00.71#ibcon#*before return 0, iclass 16, count 2 2006.285.20:46:00.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:46:00.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.20:46:00.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.20:46:00.71#ibcon#ireg 7 cls_cnt 0 2006.285.20:46:00.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:46:00.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:46:00.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:46:00.83#ibcon#enter wrdev, iclass 16, count 0 2006.285.20:46:00.83#ibcon#first serial, iclass 16, count 0 2006.285.20:46:00.83#ibcon#enter sib2, iclass 16, count 0 2006.285.20:46:00.83#ibcon#flushed, iclass 16, count 0 2006.285.20:46:00.83#ibcon#about to write, iclass 16, count 0 2006.285.20:46:00.83#ibcon#wrote, iclass 16, count 0 2006.285.20:46:00.83#ibcon#about to read 3, iclass 16, count 0 2006.285.20:46:00.85#ibcon#read 3, iclass 16, count 0 2006.285.20:46:00.85#ibcon#about to read 4, iclass 16, count 0 2006.285.20:46:00.85#ibcon#read 4, iclass 16, count 0 2006.285.20:46:00.85#ibcon#about to read 5, iclass 16, count 0 2006.285.20:46:00.85#ibcon#read 5, iclass 16, count 0 2006.285.20:46:00.85#ibcon#about to read 6, iclass 16, count 0 2006.285.20:46:00.85#ibcon#read 6, iclass 16, count 0 2006.285.20:46:00.85#ibcon#end of sib2, iclass 16, count 0 2006.285.20:46:00.85#ibcon#*mode == 0, iclass 16, count 0 2006.285.20:46:00.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.20:46:00.85#ibcon#[27=USB\r\n] 2006.285.20:46:00.85#ibcon#*before write, iclass 16, count 0 2006.285.20:46:00.85#ibcon#enter sib2, iclass 16, count 0 2006.285.20:46:00.85#ibcon#flushed, iclass 16, count 0 2006.285.20:46:00.85#ibcon#about to write, iclass 16, count 0 2006.285.20:46:00.85#ibcon#wrote, iclass 16, count 0 2006.285.20:46:00.85#ibcon#about to read 3, iclass 16, count 0 2006.285.20:46:00.88#ibcon#read 3, iclass 16, count 0 2006.285.20:46:00.88#ibcon#about to read 4, iclass 16, count 0 2006.285.20:46:00.88#ibcon#read 4, iclass 16, count 0 2006.285.20:46:00.88#ibcon#about to read 5, iclass 16, count 0 2006.285.20:46:00.88#ibcon#read 5, iclass 16, count 0 2006.285.20:46:00.88#ibcon#about to read 6, iclass 16, count 0 2006.285.20:46:00.88#ibcon#read 6, iclass 16, count 0 2006.285.20:46:00.88#ibcon#end of sib2, iclass 16, count 0 2006.285.20:46:00.88#ibcon#*after write, iclass 16, count 0 2006.285.20:46:00.88#ibcon#*before return 0, iclass 16, count 0 2006.285.20:46:00.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:46:00.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.20:46:00.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.20:46:00.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.20:46:00.88$vck44/vblo=2,634.99 2006.285.20:46:00.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.20:46:00.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.20:46:00.88#ibcon#ireg 17 cls_cnt 0 2006.285.20:46:00.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:46:00.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:46:00.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:46:00.88#ibcon#enter wrdev, iclass 18, count 0 2006.285.20:46:00.88#ibcon#first serial, iclass 18, count 0 2006.285.20:46:00.88#ibcon#enter sib2, iclass 18, count 0 2006.285.20:46:00.88#ibcon#flushed, iclass 18, count 0 2006.285.20:46:00.88#ibcon#about to write, iclass 18, count 0 2006.285.20:46:00.88#ibcon#wrote, iclass 18, count 0 2006.285.20:46:00.88#ibcon#about to read 3, iclass 18, count 0 2006.285.20:46:00.90#ibcon#read 3, iclass 18, count 0 2006.285.20:46:00.90#ibcon#about to read 4, iclass 18, count 0 2006.285.20:46:00.90#ibcon#read 4, iclass 18, count 0 2006.285.20:46:00.90#ibcon#about to read 5, iclass 18, count 0 2006.285.20:46:00.90#ibcon#read 5, iclass 18, count 0 2006.285.20:46:00.90#ibcon#about to read 6, iclass 18, count 0 2006.285.20:46:00.90#ibcon#read 6, iclass 18, count 0 2006.285.20:46:00.90#ibcon#end of sib2, iclass 18, count 0 2006.285.20:46:00.90#ibcon#*mode == 0, iclass 18, count 0 2006.285.20:46:00.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.20:46:00.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.20:46:00.90#ibcon#*before write, iclass 18, count 0 2006.285.20:46:00.90#ibcon#enter sib2, iclass 18, count 0 2006.285.20:46:00.90#ibcon#flushed, iclass 18, count 0 2006.285.20:46:00.90#ibcon#about to write, iclass 18, count 0 2006.285.20:46:00.90#ibcon#wrote, iclass 18, count 0 2006.285.20:46:00.90#ibcon#about to read 3, iclass 18, count 0 2006.285.20:46:00.94#ibcon#read 3, iclass 18, count 0 2006.285.20:46:00.94#ibcon#about to read 4, iclass 18, count 0 2006.285.20:46:00.94#ibcon#read 4, iclass 18, count 0 2006.285.20:46:00.94#ibcon#about to read 5, iclass 18, count 0 2006.285.20:46:00.94#ibcon#read 5, iclass 18, count 0 2006.285.20:46:00.94#ibcon#about to read 6, iclass 18, count 0 2006.285.20:46:00.94#ibcon#read 6, iclass 18, count 0 2006.285.20:46:00.94#ibcon#end of sib2, iclass 18, count 0 2006.285.20:46:00.94#ibcon#*after write, iclass 18, count 0 2006.285.20:46:00.94#ibcon#*before return 0, iclass 18, count 0 2006.285.20:46:00.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:46:00.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.20:46:00.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.20:46:00.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.20:46:00.94$vck44/vb=2,5 2006.285.20:46:00.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.20:46:00.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.20:46:00.94#ibcon#ireg 11 cls_cnt 2 2006.285.20:46:00.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:46:01.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:46:01.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:46:01.00#ibcon#enter wrdev, iclass 20, count 2 2006.285.20:46:01.00#ibcon#first serial, iclass 20, count 2 2006.285.20:46:01.00#ibcon#enter sib2, iclass 20, count 2 2006.285.20:46:01.00#ibcon#flushed, iclass 20, count 2 2006.285.20:46:01.00#ibcon#about to write, iclass 20, count 2 2006.285.20:46:01.00#ibcon#wrote, iclass 20, count 2 2006.285.20:46:01.00#ibcon#about to read 3, iclass 20, count 2 2006.285.20:46:01.02#ibcon#read 3, iclass 20, count 2 2006.285.20:46:01.02#ibcon#about to read 4, iclass 20, count 2 2006.285.20:46:01.02#ibcon#read 4, iclass 20, count 2 2006.285.20:46:01.02#ibcon#about to read 5, iclass 20, count 2 2006.285.20:46:01.02#ibcon#read 5, iclass 20, count 2 2006.285.20:46:01.02#ibcon#about to read 6, iclass 20, count 2 2006.285.20:46:01.02#ibcon#read 6, iclass 20, count 2 2006.285.20:46:01.02#ibcon#end of sib2, iclass 20, count 2 2006.285.20:46:01.02#ibcon#*mode == 0, iclass 20, count 2 2006.285.20:46:01.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.20:46:01.02#ibcon#[27=AT02-05\r\n] 2006.285.20:46:01.02#ibcon#*before write, iclass 20, count 2 2006.285.20:46:01.02#ibcon#enter sib2, iclass 20, count 2 2006.285.20:46:01.02#ibcon#flushed, iclass 20, count 2 2006.285.20:46:01.02#ibcon#about to write, iclass 20, count 2 2006.285.20:46:01.02#ibcon#wrote, iclass 20, count 2 2006.285.20:46:01.02#ibcon#about to read 3, iclass 20, count 2 2006.285.20:46:01.05#ibcon#read 3, iclass 20, count 2 2006.285.20:46:01.05#ibcon#about to read 4, iclass 20, count 2 2006.285.20:46:01.05#ibcon#read 4, iclass 20, count 2 2006.285.20:46:01.05#ibcon#about to read 5, iclass 20, count 2 2006.285.20:46:01.05#ibcon#read 5, iclass 20, count 2 2006.285.20:46:01.05#ibcon#about to read 6, iclass 20, count 2 2006.285.20:46:01.05#ibcon#read 6, iclass 20, count 2 2006.285.20:46:01.05#ibcon#end of sib2, iclass 20, count 2 2006.285.20:46:01.05#ibcon#*after write, iclass 20, count 2 2006.285.20:46:01.05#ibcon#*before return 0, iclass 20, count 2 2006.285.20:46:01.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:46:01.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.20:46:01.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.20:46:01.05#ibcon#ireg 7 cls_cnt 0 2006.285.20:46:01.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:46:01.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:46:01.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:46:01.17#ibcon#enter wrdev, iclass 20, count 0 2006.285.20:46:01.17#ibcon#first serial, iclass 20, count 0 2006.285.20:46:01.17#ibcon#enter sib2, iclass 20, count 0 2006.285.20:46:01.17#ibcon#flushed, iclass 20, count 0 2006.285.20:46:01.17#ibcon#about to write, iclass 20, count 0 2006.285.20:46:01.17#ibcon#wrote, iclass 20, count 0 2006.285.20:46:01.17#ibcon#about to read 3, iclass 20, count 0 2006.285.20:46:01.19#ibcon#read 3, iclass 20, count 0 2006.285.20:46:01.19#ibcon#about to read 4, iclass 20, count 0 2006.285.20:46:01.19#ibcon#read 4, iclass 20, count 0 2006.285.20:46:01.19#ibcon#about to read 5, iclass 20, count 0 2006.285.20:46:01.19#ibcon#read 5, iclass 20, count 0 2006.285.20:46:01.19#ibcon#about to read 6, iclass 20, count 0 2006.285.20:46:01.19#ibcon#read 6, iclass 20, count 0 2006.285.20:46:01.19#ibcon#end of sib2, iclass 20, count 0 2006.285.20:46:01.19#ibcon#*mode == 0, iclass 20, count 0 2006.285.20:46:01.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.20:46:01.19#ibcon#[27=USB\r\n] 2006.285.20:46:01.19#ibcon#*before write, iclass 20, count 0 2006.285.20:46:01.19#ibcon#enter sib2, iclass 20, count 0 2006.285.20:46:01.19#ibcon#flushed, iclass 20, count 0 2006.285.20:46:01.19#ibcon#about to write, iclass 20, count 0 2006.285.20:46:01.19#ibcon#wrote, iclass 20, count 0 2006.285.20:46:01.19#ibcon#about to read 3, iclass 20, count 0 2006.285.20:46:01.22#ibcon#read 3, iclass 20, count 0 2006.285.20:46:01.22#ibcon#about to read 4, iclass 20, count 0 2006.285.20:46:01.22#ibcon#read 4, iclass 20, count 0 2006.285.20:46:01.22#ibcon#about to read 5, iclass 20, count 0 2006.285.20:46:01.22#ibcon#read 5, iclass 20, count 0 2006.285.20:46:01.22#ibcon#about to read 6, iclass 20, count 0 2006.285.20:46:01.22#ibcon#read 6, iclass 20, count 0 2006.285.20:46:01.22#ibcon#end of sib2, iclass 20, count 0 2006.285.20:46:01.22#ibcon#*after write, iclass 20, count 0 2006.285.20:46:01.22#ibcon#*before return 0, iclass 20, count 0 2006.285.20:46:01.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:46:01.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.20:46:01.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.20:46:01.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.20:46:01.22$vck44/vblo=3,649.99 2006.285.20:46:01.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.20:46:01.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.20:46:01.22#ibcon#ireg 17 cls_cnt 0 2006.285.20:46:01.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:46:01.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:46:01.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:46:01.22#ibcon#enter wrdev, iclass 22, count 0 2006.285.20:46:01.22#ibcon#first serial, iclass 22, count 0 2006.285.20:46:01.22#ibcon#enter sib2, iclass 22, count 0 2006.285.20:46:01.22#ibcon#flushed, iclass 22, count 0 2006.285.20:46:01.22#ibcon#about to write, iclass 22, count 0 2006.285.20:46:01.22#ibcon#wrote, iclass 22, count 0 2006.285.20:46:01.22#ibcon#about to read 3, iclass 22, count 0 2006.285.20:46:01.24#ibcon#read 3, iclass 22, count 0 2006.285.20:46:01.24#ibcon#about to read 4, iclass 22, count 0 2006.285.20:46:01.24#ibcon#read 4, iclass 22, count 0 2006.285.20:46:01.24#ibcon#about to read 5, iclass 22, count 0 2006.285.20:46:01.24#ibcon#read 5, iclass 22, count 0 2006.285.20:46:01.24#ibcon#about to read 6, iclass 22, count 0 2006.285.20:46:01.24#ibcon#read 6, iclass 22, count 0 2006.285.20:46:01.24#ibcon#end of sib2, iclass 22, count 0 2006.285.20:46:01.24#ibcon#*mode == 0, iclass 22, count 0 2006.285.20:46:01.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.20:46:01.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.20:46:01.24#ibcon#*before write, iclass 22, count 0 2006.285.20:46:01.24#ibcon#enter sib2, iclass 22, count 0 2006.285.20:46:01.24#ibcon#flushed, iclass 22, count 0 2006.285.20:46:01.24#ibcon#about to write, iclass 22, count 0 2006.285.20:46:01.24#ibcon#wrote, iclass 22, count 0 2006.285.20:46:01.24#ibcon#about to read 3, iclass 22, count 0 2006.285.20:46:01.28#ibcon#read 3, iclass 22, count 0 2006.285.20:46:01.28#ibcon#about to read 4, iclass 22, count 0 2006.285.20:46:01.28#ibcon#read 4, iclass 22, count 0 2006.285.20:46:01.28#ibcon#about to read 5, iclass 22, count 0 2006.285.20:46:01.28#ibcon#read 5, iclass 22, count 0 2006.285.20:46:01.28#ibcon#about to read 6, iclass 22, count 0 2006.285.20:46:01.28#ibcon#read 6, iclass 22, count 0 2006.285.20:46:01.28#ibcon#end of sib2, iclass 22, count 0 2006.285.20:46:01.28#ibcon#*after write, iclass 22, count 0 2006.285.20:46:01.28#ibcon#*before return 0, iclass 22, count 0 2006.285.20:46:01.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:46:01.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.20:46:01.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.20:46:01.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.20:46:01.28$vck44/vb=3,4 2006.285.20:46:01.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.20:46:01.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.20:46:01.28#ibcon#ireg 11 cls_cnt 2 2006.285.20:46:01.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:46:01.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:46:01.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:46:01.34#ibcon#enter wrdev, iclass 24, count 2 2006.285.20:46:01.34#ibcon#first serial, iclass 24, count 2 2006.285.20:46:01.34#ibcon#enter sib2, iclass 24, count 2 2006.285.20:46:01.34#ibcon#flushed, iclass 24, count 2 2006.285.20:46:01.34#ibcon#about to write, iclass 24, count 2 2006.285.20:46:01.34#ibcon#wrote, iclass 24, count 2 2006.285.20:46:01.34#ibcon#about to read 3, iclass 24, count 2 2006.285.20:46:01.36#ibcon#read 3, iclass 24, count 2 2006.285.20:46:01.36#ibcon#about to read 4, iclass 24, count 2 2006.285.20:46:01.36#ibcon#read 4, iclass 24, count 2 2006.285.20:46:01.36#ibcon#about to read 5, iclass 24, count 2 2006.285.20:46:01.36#ibcon#read 5, iclass 24, count 2 2006.285.20:46:01.36#ibcon#about to read 6, iclass 24, count 2 2006.285.20:46:01.36#ibcon#read 6, iclass 24, count 2 2006.285.20:46:01.36#ibcon#end of sib2, iclass 24, count 2 2006.285.20:46:01.36#ibcon#*mode == 0, iclass 24, count 2 2006.285.20:46:01.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.20:46:01.36#ibcon#[27=AT03-04\r\n] 2006.285.20:46:01.36#ibcon#*before write, iclass 24, count 2 2006.285.20:46:01.36#ibcon#enter sib2, iclass 24, count 2 2006.285.20:46:01.36#ibcon#flushed, iclass 24, count 2 2006.285.20:46:01.36#ibcon#about to write, iclass 24, count 2 2006.285.20:46:01.36#ibcon#wrote, iclass 24, count 2 2006.285.20:46:01.36#ibcon#about to read 3, iclass 24, count 2 2006.285.20:46:01.39#ibcon#read 3, iclass 24, count 2 2006.285.20:46:01.39#ibcon#about to read 4, iclass 24, count 2 2006.285.20:46:01.39#ibcon#read 4, iclass 24, count 2 2006.285.20:46:01.39#ibcon#about to read 5, iclass 24, count 2 2006.285.20:46:01.39#ibcon#read 5, iclass 24, count 2 2006.285.20:46:01.39#ibcon#about to read 6, iclass 24, count 2 2006.285.20:46:01.39#ibcon#read 6, iclass 24, count 2 2006.285.20:46:01.39#ibcon#end of sib2, iclass 24, count 2 2006.285.20:46:01.39#ibcon#*after write, iclass 24, count 2 2006.285.20:46:01.39#ibcon#*before return 0, iclass 24, count 2 2006.285.20:46:01.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:46:01.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.20:46:01.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.20:46:01.39#ibcon#ireg 7 cls_cnt 0 2006.285.20:46:01.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:46:01.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:46:01.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:46:01.51#ibcon#enter wrdev, iclass 24, count 0 2006.285.20:46:01.51#ibcon#first serial, iclass 24, count 0 2006.285.20:46:01.51#ibcon#enter sib2, iclass 24, count 0 2006.285.20:46:01.51#ibcon#flushed, iclass 24, count 0 2006.285.20:46:01.51#ibcon#about to write, iclass 24, count 0 2006.285.20:46:01.51#ibcon#wrote, iclass 24, count 0 2006.285.20:46:01.51#ibcon#about to read 3, iclass 24, count 0 2006.285.20:46:01.53#ibcon#read 3, iclass 24, count 0 2006.285.20:46:01.53#ibcon#about to read 4, iclass 24, count 0 2006.285.20:46:01.53#ibcon#read 4, iclass 24, count 0 2006.285.20:46:01.53#ibcon#about to read 5, iclass 24, count 0 2006.285.20:46:01.53#ibcon#read 5, iclass 24, count 0 2006.285.20:46:01.53#ibcon#about to read 6, iclass 24, count 0 2006.285.20:46:01.53#ibcon#read 6, iclass 24, count 0 2006.285.20:46:01.53#ibcon#end of sib2, iclass 24, count 0 2006.285.20:46:01.53#ibcon#*mode == 0, iclass 24, count 0 2006.285.20:46:01.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.20:46:01.53#ibcon#[27=USB\r\n] 2006.285.20:46:01.53#ibcon#*before write, iclass 24, count 0 2006.285.20:46:01.53#ibcon#enter sib2, iclass 24, count 0 2006.285.20:46:01.53#ibcon#flushed, iclass 24, count 0 2006.285.20:46:01.53#ibcon#about to write, iclass 24, count 0 2006.285.20:46:01.53#ibcon#wrote, iclass 24, count 0 2006.285.20:46:01.53#ibcon#about to read 3, iclass 24, count 0 2006.285.20:46:01.56#ibcon#read 3, iclass 24, count 0 2006.285.20:46:01.56#ibcon#about to read 4, iclass 24, count 0 2006.285.20:46:01.56#ibcon#read 4, iclass 24, count 0 2006.285.20:46:01.56#ibcon#about to read 5, iclass 24, count 0 2006.285.20:46:01.56#ibcon#read 5, iclass 24, count 0 2006.285.20:46:01.56#ibcon#about to read 6, iclass 24, count 0 2006.285.20:46:01.56#ibcon#read 6, iclass 24, count 0 2006.285.20:46:01.56#ibcon#end of sib2, iclass 24, count 0 2006.285.20:46:01.56#ibcon#*after write, iclass 24, count 0 2006.285.20:46:01.56#ibcon#*before return 0, iclass 24, count 0 2006.285.20:46:01.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:46:01.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.20:46:01.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.20:46:01.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.20:46:01.56$vck44/vblo=4,679.99 2006.285.20:46:01.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.20:46:01.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.20:46:01.56#ibcon#ireg 17 cls_cnt 0 2006.285.20:46:01.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:46:01.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:46:01.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:46:01.56#ibcon#enter wrdev, iclass 26, count 0 2006.285.20:46:01.56#ibcon#first serial, iclass 26, count 0 2006.285.20:46:01.56#ibcon#enter sib2, iclass 26, count 0 2006.285.20:46:01.56#ibcon#flushed, iclass 26, count 0 2006.285.20:46:01.56#ibcon#about to write, iclass 26, count 0 2006.285.20:46:01.56#ibcon#wrote, iclass 26, count 0 2006.285.20:46:01.56#ibcon#about to read 3, iclass 26, count 0 2006.285.20:46:01.58#ibcon#read 3, iclass 26, count 0 2006.285.20:46:01.59#ibcon#about to read 4, iclass 26, count 0 2006.285.20:46:01.59#ibcon#read 4, iclass 26, count 0 2006.285.20:46:01.59#ibcon#about to read 5, iclass 26, count 0 2006.285.20:46:01.59#ibcon#read 5, iclass 26, count 0 2006.285.20:46:01.59#ibcon#about to read 6, iclass 26, count 0 2006.285.20:46:01.59#ibcon#read 6, iclass 26, count 0 2006.285.20:46:01.59#ibcon#end of sib2, iclass 26, count 0 2006.285.20:46:01.59#ibcon#*mode == 0, iclass 26, count 0 2006.285.20:46:01.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.20:46:01.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.20:46:01.59#ibcon#*before write, iclass 26, count 0 2006.285.20:46:01.59#ibcon#enter sib2, iclass 26, count 0 2006.285.20:46:01.59#ibcon#flushed, iclass 26, count 0 2006.285.20:46:01.59#ibcon#about to write, iclass 26, count 0 2006.285.20:46:01.59#ibcon#wrote, iclass 26, count 0 2006.285.20:46:01.59#ibcon#about to read 3, iclass 26, count 0 2006.285.20:46:01.63#ibcon#read 3, iclass 26, count 0 2006.285.20:46:01.63#ibcon#about to read 4, iclass 26, count 0 2006.285.20:46:01.63#ibcon#read 4, iclass 26, count 0 2006.285.20:46:01.63#ibcon#about to read 5, iclass 26, count 0 2006.285.20:46:01.63#ibcon#read 5, iclass 26, count 0 2006.285.20:46:01.63#ibcon#about to read 6, iclass 26, count 0 2006.285.20:46:01.63#ibcon#read 6, iclass 26, count 0 2006.285.20:46:01.63#ibcon#end of sib2, iclass 26, count 0 2006.285.20:46:01.63#ibcon#*after write, iclass 26, count 0 2006.285.20:46:01.63#ibcon#*before return 0, iclass 26, count 0 2006.285.20:46:01.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:46:01.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.20:46:01.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.20:46:01.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.20:46:01.63$vck44/vb=4,5 2006.285.20:46:01.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.20:46:01.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.20:46:01.63#ibcon#ireg 11 cls_cnt 2 2006.285.20:46:01.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:46:01.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:46:01.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:46:01.68#ibcon#enter wrdev, iclass 28, count 2 2006.285.20:46:01.68#ibcon#first serial, iclass 28, count 2 2006.285.20:46:01.68#ibcon#enter sib2, iclass 28, count 2 2006.285.20:46:01.68#ibcon#flushed, iclass 28, count 2 2006.285.20:46:01.68#ibcon#about to write, iclass 28, count 2 2006.285.20:46:01.68#ibcon#wrote, iclass 28, count 2 2006.285.20:46:01.68#ibcon#about to read 3, iclass 28, count 2 2006.285.20:46:01.70#ibcon#read 3, iclass 28, count 2 2006.285.20:46:01.70#ibcon#about to read 4, iclass 28, count 2 2006.285.20:46:01.70#ibcon#read 4, iclass 28, count 2 2006.285.20:46:01.70#ibcon#about to read 5, iclass 28, count 2 2006.285.20:46:01.70#ibcon#read 5, iclass 28, count 2 2006.285.20:46:01.70#ibcon#about to read 6, iclass 28, count 2 2006.285.20:46:01.70#ibcon#read 6, iclass 28, count 2 2006.285.20:46:01.70#ibcon#end of sib2, iclass 28, count 2 2006.285.20:46:01.70#ibcon#*mode == 0, iclass 28, count 2 2006.285.20:46:01.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.20:46:01.70#ibcon#[27=AT04-05\r\n] 2006.285.20:46:01.70#ibcon#*before write, iclass 28, count 2 2006.285.20:46:01.70#ibcon#enter sib2, iclass 28, count 2 2006.285.20:46:01.70#ibcon#flushed, iclass 28, count 2 2006.285.20:46:01.70#ibcon#about to write, iclass 28, count 2 2006.285.20:46:01.70#ibcon#wrote, iclass 28, count 2 2006.285.20:46:01.70#ibcon#about to read 3, iclass 28, count 2 2006.285.20:46:01.73#ibcon#read 3, iclass 28, count 2 2006.285.20:46:01.73#ibcon#about to read 4, iclass 28, count 2 2006.285.20:46:01.73#ibcon#read 4, iclass 28, count 2 2006.285.20:46:01.73#ibcon#about to read 5, iclass 28, count 2 2006.285.20:46:01.73#ibcon#read 5, iclass 28, count 2 2006.285.20:46:01.73#ibcon#about to read 6, iclass 28, count 2 2006.285.20:46:01.73#ibcon#read 6, iclass 28, count 2 2006.285.20:46:01.73#ibcon#end of sib2, iclass 28, count 2 2006.285.20:46:01.73#ibcon#*after write, iclass 28, count 2 2006.285.20:46:01.73#ibcon#*before return 0, iclass 28, count 2 2006.285.20:46:01.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:46:01.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.20:46:01.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.20:46:01.73#ibcon#ireg 7 cls_cnt 0 2006.285.20:46:01.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:46:01.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:46:01.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:46:01.85#ibcon#enter wrdev, iclass 28, count 0 2006.285.20:46:01.85#ibcon#first serial, iclass 28, count 0 2006.285.20:46:01.85#ibcon#enter sib2, iclass 28, count 0 2006.285.20:46:01.85#ibcon#flushed, iclass 28, count 0 2006.285.20:46:01.85#ibcon#about to write, iclass 28, count 0 2006.285.20:46:01.85#ibcon#wrote, iclass 28, count 0 2006.285.20:46:01.85#ibcon#about to read 3, iclass 28, count 0 2006.285.20:46:01.87#ibcon#read 3, iclass 28, count 0 2006.285.20:46:01.87#ibcon#about to read 4, iclass 28, count 0 2006.285.20:46:01.87#ibcon#read 4, iclass 28, count 0 2006.285.20:46:01.87#ibcon#about to read 5, iclass 28, count 0 2006.285.20:46:01.87#ibcon#read 5, iclass 28, count 0 2006.285.20:46:01.87#ibcon#about to read 6, iclass 28, count 0 2006.285.20:46:01.87#ibcon#read 6, iclass 28, count 0 2006.285.20:46:01.87#ibcon#end of sib2, iclass 28, count 0 2006.285.20:46:01.87#ibcon#*mode == 0, iclass 28, count 0 2006.285.20:46:01.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.20:46:01.87#ibcon#[27=USB\r\n] 2006.285.20:46:01.87#ibcon#*before write, iclass 28, count 0 2006.285.20:46:01.87#ibcon#enter sib2, iclass 28, count 0 2006.285.20:46:01.87#ibcon#flushed, iclass 28, count 0 2006.285.20:46:01.87#ibcon#about to write, iclass 28, count 0 2006.285.20:46:01.87#ibcon#wrote, iclass 28, count 0 2006.285.20:46:01.87#ibcon#about to read 3, iclass 28, count 0 2006.285.20:46:01.90#ibcon#read 3, iclass 28, count 0 2006.285.20:46:01.90#ibcon#about to read 4, iclass 28, count 0 2006.285.20:46:01.90#ibcon#read 4, iclass 28, count 0 2006.285.20:46:01.90#ibcon#about to read 5, iclass 28, count 0 2006.285.20:46:01.90#ibcon#read 5, iclass 28, count 0 2006.285.20:46:01.90#ibcon#about to read 6, iclass 28, count 0 2006.285.20:46:01.90#ibcon#read 6, iclass 28, count 0 2006.285.20:46:01.90#ibcon#end of sib2, iclass 28, count 0 2006.285.20:46:01.90#ibcon#*after write, iclass 28, count 0 2006.285.20:46:01.90#ibcon#*before return 0, iclass 28, count 0 2006.285.20:46:01.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:46:01.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.20:46:01.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.20:46:01.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.20:46:01.90$vck44/vblo=5,709.99 2006.285.20:46:01.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.20:46:01.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.20:46:01.90#ibcon#ireg 17 cls_cnt 0 2006.285.20:46:01.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:46:01.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:46:01.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:46:01.90#ibcon#enter wrdev, iclass 30, count 0 2006.285.20:46:01.90#ibcon#first serial, iclass 30, count 0 2006.285.20:46:01.90#ibcon#enter sib2, iclass 30, count 0 2006.285.20:46:01.90#ibcon#flushed, iclass 30, count 0 2006.285.20:46:01.90#ibcon#about to write, iclass 30, count 0 2006.285.20:46:01.90#ibcon#wrote, iclass 30, count 0 2006.285.20:46:01.90#ibcon#about to read 3, iclass 30, count 0 2006.285.20:46:01.92#ibcon#read 3, iclass 30, count 0 2006.285.20:46:01.92#ibcon#about to read 4, iclass 30, count 0 2006.285.20:46:01.92#ibcon#read 4, iclass 30, count 0 2006.285.20:46:01.92#ibcon#about to read 5, iclass 30, count 0 2006.285.20:46:01.92#ibcon#read 5, iclass 30, count 0 2006.285.20:46:01.92#ibcon#about to read 6, iclass 30, count 0 2006.285.20:46:01.92#ibcon#read 6, iclass 30, count 0 2006.285.20:46:01.92#ibcon#end of sib2, iclass 30, count 0 2006.285.20:46:01.92#ibcon#*mode == 0, iclass 30, count 0 2006.285.20:46:01.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.20:46:01.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.20:46:01.92#ibcon#*before write, iclass 30, count 0 2006.285.20:46:01.92#ibcon#enter sib2, iclass 30, count 0 2006.285.20:46:01.92#ibcon#flushed, iclass 30, count 0 2006.285.20:46:01.92#ibcon#about to write, iclass 30, count 0 2006.285.20:46:01.92#ibcon#wrote, iclass 30, count 0 2006.285.20:46:01.92#ibcon#about to read 3, iclass 30, count 0 2006.285.20:46:01.96#ibcon#read 3, iclass 30, count 0 2006.285.20:46:01.96#ibcon#about to read 4, iclass 30, count 0 2006.285.20:46:01.96#ibcon#read 4, iclass 30, count 0 2006.285.20:46:01.96#ibcon#about to read 5, iclass 30, count 0 2006.285.20:46:01.96#ibcon#read 5, iclass 30, count 0 2006.285.20:46:01.96#ibcon#about to read 6, iclass 30, count 0 2006.285.20:46:01.96#ibcon#read 6, iclass 30, count 0 2006.285.20:46:01.96#ibcon#end of sib2, iclass 30, count 0 2006.285.20:46:01.96#ibcon#*after write, iclass 30, count 0 2006.285.20:46:01.96#ibcon#*before return 0, iclass 30, count 0 2006.285.20:46:01.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:46:01.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.20:46:01.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.20:46:01.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.20:46:01.96$vck44/vb=5,4 2006.285.20:46:01.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.20:46:01.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.20:46:01.96#ibcon#ireg 11 cls_cnt 2 2006.285.20:46:01.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:46:02.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:46:02.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:46:02.02#ibcon#enter wrdev, iclass 32, count 2 2006.285.20:46:02.02#ibcon#first serial, iclass 32, count 2 2006.285.20:46:02.02#ibcon#enter sib2, iclass 32, count 2 2006.285.20:46:02.02#ibcon#flushed, iclass 32, count 2 2006.285.20:46:02.02#ibcon#about to write, iclass 32, count 2 2006.285.20:46:02.02#ibcon#wrote, iclass 32, count 2 2006.285.20:46:02.02#ibcon#about to read 3, iclass 32, count 2 2006.285.20:46:02.04#ibcon#read 3, iclass 32, count 2 2006.285.20:46:02.04#ibcon#about to read 4, iclass 32, count 2 2006.285.20:46:02.04#ibcon#read 4, iclass 32, count 2 2006.285.20:46:02.04#ibcon#about to read 5, iclass 32, count 2 2006.285.20:46:02.04#ibcon#read 5, iclass 32, count 2 2006.285.20:46:02.04#ibcon#about to read 6, iclass 32, count 2 2006.285.20:46:02.04#ibcon#read 6, iclass 32, count 2 2006.285.20:46:02.04#ibcon#end of sib2, iclass 32, count 2 2006.285.20:46:02.04#ibcon#*mode == 0, iclass 32, count 2 2006.285.20:46:02.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.20:46:02.04#ibcon#[27=AT05-04\r\n] 2006.285.20:46:02.04#ibcon#*before write, iclass 32, count 2 2006.285.20:46:02.04#ibcon#enter sib2, iclass 32, count 2 2006.285.20:46:02.04#ibcon#flushed, iclass 32, count 2 2006.285.20:46:02.04#ibcon#about to write, iclass 32, count 2 2006.285.20:46:02.04#ibcon#wrote, iclass 32, count 2 2006.285.20:46:02.04#ibcon#about to read 3, iclass 32, count 2 2006.285.20:46:02.07#ibcon#read 3, iclass 32, count 2 2006.285.20:46:02.07#ibcon#about to read 4, iclass 32, count 2 2006.285.20:46:02.07#ibcon#read 4, iclass 32, count 2 2006.285.20:46:02.07#ibcon#about to read 5, iclass 32, count 2 2006.285.20:46:02.07#ibcon#read 5, iclass 32, count 2 2006.285.20:46:02.07#ibcon#about to read 6, iclass 32, count 2 2006.285.20:46:02.07#ibcon#read 6, iclass 32, count 2 2006.285.20:46:02.07#ibcon#end of sib2, iclass 32, count 2 2006.285.20:46:02.07#ibcon#*after write, iclass 32, count 2 2006.285.20:46:02.07#ibcon#*before return 0, iclass 32, count 2 2006.285.20:46:02.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:46:02.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.20:46:02.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.20:46:02.07#ibcon#ireg 7 cls_cnt 0 2006.285.20:46:02.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:46:02.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:46:02.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:46:02.19#ibcon#enter wrdev, iclass 32, count 0 2006.285.20:46:02.19#ibcon#first serial, iclass 32, count 0 2006.285.20:46:02.19#ibcon#enter sib2, iclass 32, count 0 2006.285.20:46:02.19#ibcon#flushed, iclass 32, count 0 2006.285.20:46:02.19#ibcon#about to write, iclass 32, count 0 2006.285.20:46:02.19#ibcon#wrote, iclass 32, count 0 2006.285.20:46:02.19#ibcon#about to read 3, iclass 32, count 0 2006.285.20:46:02.21#ibcon#read 3, iclass 32, count 0 2006.285.20:46:02.21#ibcon#about to read 4, iclass 32, count 0 2006.285.20:46:02.21#ibcon#read 4, iclass 32, count 0 2006.285.20:46:02.21#ibcon#about to read 5, iclass 32, count 0 2006.285.20:46:02.21#ibcon#read 5, iclass 32, count 0 2006.285.20:46:02.21#ibcon#about to read 6, iclass 32, count 0 2006.285.20:46:02.21#ibcon#read 6, iclass 32, count 0 2006.285.20:46:02.21#ibcon#end of sib2, iclass 32, count 0 2006.285.20:46:02.21#ibcon#*mode == 0, iclass 32, count 0 2006.285.20:46:02.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.20:46:02.21#ibcon#[27=USB\r\n] 2006.285.20:46:02.21#ibcon#*before write, iclass 32, count 0 2006.285.20:46:02.21#ibcon#enter sib2, iclass 32, count 0 2006.285.20:46:02.21#ibcon#flushed, iclass 32, count 0 2006.285.20:46:02.21#ibcon#about to write, iclass 32, count 0 2006.285.20:46:02.21#ibcon#wrote, iclass 32, count 0 2006.285.20:46:02.21#ibcon#about to read 3, iclass 32, count 0 2006.285.20:46:02.24#ibcon#read 3, iclass 32, count 0 2006.285.20:46:02.24#ibcon#about to read 4, iclass 32, count 0 2006.285.20:46:02.24#ibcon#read 4, iclass 32, count 0 2006.285.20:46:02.24#ibcon#about to read 5, iclass 32, count 0 2006.285.20:46:02.24#ibcon#read 5, iclass 32, count 0 2006.285.20:46:02.24#ibcon#about to read 6, iclass 32, count 0 2006.285.20:46:02.24#ibcon#read 6, iclass 32, count 0 2006.285.20:46:02.24#ibcon#end of sib2, iclass 32, count 0 2006.285.20:46:02.24#ibcon#*after write, iclass 32, count 0 2006.285.20:46:02.24#ibcon#*before return 0, iclass 32, count 0 2006.285.20:46:02.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:46:02.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.20:46:02.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.20:46:02.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.20:46:02.24$vck44/vblo=6,719.99 2006.285.20:46:02.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.20:46:02.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.20:46:02.24#ibcon#ireg 17 cls_cnt 0 2006.285.20:46:02.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:46:02.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:46:02.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:46:02.24#ibcon#enter wrdev, iclass 34, count 0 2006.285.20:46:02.24#ibcon#first serial, iclass 34, count 0 2006.285.20:46:02.24#ibcon#enter sib2, iclass 34, count 0 2006.285.20:46:02.24#ibcon#flushed, iclass 34, count 0 2006.285.20:46:02.24#ibcon#about to write, iclass 34, count 0 2006.285.20:46:02.24#ibcon#wrote, iclass 34, count 0 2006.285.20:46:02.24#ibcon#about to read 3, iclass 34, count 0 2006.285.20:46:02.26#ibcon#read 3, iclass 34, count 0 2006.285.20:46:02.26#ibcon#about to read 4, iclass 34, count 0 2006.285.20:46:02.26#ibcon#read 4, iclass 34, count 0 2006.285.20:46:02.26#ibcon#about to read 5, iclass 34, count 0 2006.285.20:46:02.26#ibcon#read 5, iclass 34, count 0 2006.285.20:46:02.26#ibcon#about to read 6, iclass 34, count 0 2006.285.20:46:02.26#ibcon#read 6, iclass 34, count 0 2006.285.20:46:02.26#ibcon#end of sib2, iclass 34, count 0 2006.285.20:46:02.26#ibcon#*mode == 0, iclass 34, count 0 2006.285.20:46:02.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.20:46:02.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.20:46:02.26#ibcon#*before write, iclass 34, count 0 2006.285.20:46:02.26#ibcon#enter sib2, iclass 34, count 0 2006.285.20:46:02.26#ibcon#flushed, iclass 34, count 0 2006.285.20:46:02.26#ibcon#about to write, iclass 34, count 0 2006.285.20:46:02.26#ibcon#wrote, iclass 34, count 0 2006.285.20:46:02.26#ibcon#about to read 3, iclass 34, count 0 2006.285.20:46:02.30#ibcon#read 3, iclass 34, count 0 2006.285.20:46:02.30#ibcon#about to read 4, iclass 34, count 0 2006.285.20:46:02.30#ibcon#read 4, iclass 34, count 0 2006.285.20:46:02.30#ibcon#about to read 5, iclass 34, count 0 2006.285.20:46:02.30#ibcon#read 5, iclass 34, count 0 2006.285.20:46:02.30#ibcon#about to read 6, iclass 34, count 0 2006.285.20:46:02.30#ibcon#read 6, iclass 34, count 0 2006.285.20:46:02.30#ibcon#end of sib2, iclass 34, count 0 2006.285.20:46:02.30#ibcon#*after write, iclass 34, count 0 2006.285.20:46:02.30#ibcon#*before return 0, iclass 34, count 0 2006.285.20:46:02.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:46:02.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.20:46:02.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.20:46:02.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.20:46:02.30$vck44/vb=6,3 2006.285.20:46:02.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.20:46:02.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.20:46:02.30#ibcon#ireg 11 cls_cnt 2 2006.285.20:46:02.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:46:02.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:46:02.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:46:02.36#ibcon#enter wrdev, iclass 36, count 2 2006.285.20:46:02.36#ibcon#first serial, iclass 36, count 2 2006.285.20:46:02.36#ibcon#enter sib2, iclass 36, count 2 2006.285.20:46:02.36#ibcon#flushed, iclass 36, count 2 2006.285.20:46:02.36#ibcon#about to write, iclass 36, count 2 2006.285.20:46:02.36#ibcon#wrote, iclass 36, count 2 2006.285.20:46:02.36#ibcon#about to read 3, iclass 36, count 2 2006.285.20:46:02.38#ibcon#read 3, iclass 36, count 2 2006.285.20:46:02.38#ibcon#about to read 4, iclass 36, count 2 2006.285.20:46:02.38#ibcon#read 4, iclass 36, count 2 2006.285.20:46:02.38#ibcon#about to read 5, iclass 36, count 2 2006.285.20:46:02.38#ibcon#read 5, iclass 36, count 2 2006.285.20:46:02.38#ibcon#about to read 6, iclass 36, count 2 2006.285.20:46:02.38#ibcon#read 6, iclass 36, count 2 2006.285.20:46:02.38#ibcon#end of sib2, iclass 36, count 2 2006.285.20:46:02.38#ibcon#*mode == 0, iclass 36, count 2 2006.285.20:46:02.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.20:46:02.38#ibcon#[27=AT06-03\r\n] 2006.285.20:46:02.38#ibcon#*before write, iclass 36, count 2 2006.285.20:46:02.38#ibcon#enter sib2, iclass 36, count 2 2006.285.20:46:02.38#ibcon#flushed, iclass 36, count 2 2006.285.20:46:02.38#ibcon#about to write, iclass 36, count 2 2006.285.20:46:02.38#ibcon#wrote, iclass 36, count 2 2006.285.20:46:02.38#ibcon#about to read 3, iclass 36, count 2 2006.285.20:46:02.41#ibcon#read 3, iclass 36, count 2 2006.285.20:46:02.41#ibcon#about to read 4, iclass 36, count 2 2006.285.20:46:02.41#ibcon#read 4, iclass 36, count 2 2006.285.20:46:02.41#ibcon#about to read 5, iclass 36, count 2 2006.285.20:46:02.41#ibcon#read 5, iclass 36, count 2 2006.285.20:46:02.41#ibcon#about to read 6, iclass 36, count 2 2006.285.20:46:02.41#ibcon#read 6, iclass 36, count 2 2006.285.20:46:02.41#ibcon#end of sib2, iclass 36, count 2 2006.285.20:46:02.41#ibcon#*after write, iclass 36, count 2 2006.285.20:46:02.41#ibcon#*before return 0, iclass 36, count 2 2006.285.20:46:02.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:46:02.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.20:46:02.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.20:46:02.41#ibcon#ireg 7 cls_cnt 0 2006.285.20:46:02.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:46:02.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:46:02.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:46:02.53#ibcon#enter wrdev, iclass 36, count 0 2006.285.20:46:02.53#ibcon#first serial, iclass 36, count 0 2006.285.20:46:02.53#ibcon#enter sib2, iclass 36, count 0 2006.285.20:46:02.53#ibcon#flushed, iclass 36, count 0 2006.285.20:46:02.53#ibcon#about to write, iclass 36, count 0 2006.285.20:46:02.53#ibcon#wrote, iclass 36, count 0 2006.285.20:46:02.53#ibcon#about to read 3, iclass 36, count 0 2006.285.20:46:02.55#ibcon#read 3, iclass 36, count 0 2006.285.20:46:02.55#ibcon#about to read 4, iclass 36, count 0 2006.285.20:46:02.55#ibcon#read 4, iclass 36, count 0 2006.285.20:46:02.55#ibcon#about to read 5, iclass 36, count 0 2006.285.20:46:02.55#ibcon#read 5, iclass 36, count 0 2006.285.20:46:02.55#ibcon#about to read 6, iclass 36, count 0 2006.285.20:46:02.55#ibcon#read 6, iclass 36, count 0 2006.285.20:46:02.55#ibcon#end of sib2, iclass 36, count 0 2006.285.20:46:02.55#ibcon#*mode == 0, iclass 36, count 0 2006.285.20:46:02.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.20:46:02.55#ibcon#[27=USB\r\n] 2006.285.20:46:02.55#ibcon#*before write, iclass 36, count 0 2006.285.20:46:02.55#ibcon#enter sib2, iclass 36, count 0 2006.285.20:46:02.55#ibcon#flushed, iclass 36, count 0 2006.285.20:46:02.55#ibcon#about to write, iclass 36, count 0 2006.285.20:46:02.55#ibcon#wrote, iclass 36, count 0 2006.285.20:46:02.55#ibcon#about to read 3, iclass 36, count 0 2006.285.20:46:02.58#ibcon#read 3, iclass 36, count 0 2006.285.20:46:02.58#ibcon#about to read 4, iclass 36, count 0 2006.285.20:46:02.58#ibcon#read 4, iclass 36, count 0 2006.285.20:46:02.58#ibcon#about to read 5, iclass 36, count 0 2006.285.20:46:02.58#ibcon#read 5, iclass 36, count 0 2006.285.20:46:02.58#ibcon#about to read 6, iclass 36, count 0 2006.285.20:46:02.58#ibcon#read 6, iclass 36, count 0 2006.285.20:46:02.58#ibcon#end of sib2, iclass 36, count 0 2006.285.20:46:02.58#ibcon#*after write, iclass 36, count 0 2006.285.20:46:02.58#ibcon#*before return 0, iclass 36, count 0 2006.285.20:46:02.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:46:02.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.20:46:02.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.20:46:02.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.20:46:02.58$vck44/vblo=7,734.99 2006.285.20:46:02.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.20:46:02.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.20:46:02.65#ibcon#ireg 17 cls_cnt 0 2006.285.20:46:02.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:46:02.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:46:02.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:46:02.65#ibcon#enter wrdev, iclass 38, count 0 2006.285.20:46:02.65#ibcon#first serial, iclass 38, count 0 2006.285.20:46:02.65#ibcon#enter sib2, iclass 38, count 0 2006.285.20:46:02.65#ibcon#flushed, iclass 38, count 0 2006.285.20:46:02.65#ibcon#about to write, iclass 38, count 0 2006.285.20:46:02.65#ibcon#wrote, iclass 38, count 0 2006.285.20:46:02.65#ibcon#about to read 3, iclass 38, count 0 2006.285.20:46:02.66#ibcon#read 3, iclass 38, count 0 2006.285.20:46:02.66#ibcon#about to read 4, iclass 38, count 0 2006.285.20:46:02.66#ibcon#read 4, iclass 38, count 0 2006.285.20:46:02.66#ibcon#about to read 5, iclass 38, count 0 2006.285.20:46:02.66#ibcon#read 5, iclass 38, count 0 2006.285.20:46:02.66#ibcon#about to read 6, iclass 38, count 0 2006.285.20:46:02.66#ibcon#read 6, iclass 38, count 0 2006.285.20:46:02.66#ibcon#end of sib2, iclass 38, count 0 2006.285.20:46:02.66#ibcon#*mode == 0, iclass 38, count 0 2006.285.20:46:02.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.20:46:02.66#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.20:46:02.66#ibcon#*before write, iclass 38, count 0 2006.285.20:46:02.66#ibcon#enter sib2, iclass 38, count 0 2006.285.20:46:02.66#ibcon#flushed, iclass 38, count 0 2006.285.20:46:02.66#ibcon#about to write, iclass 38, count 0 2006.285.20:46:02.66#ibcon#wrote, iclass 38, count 0 2006.285.20:46:02.66#ibcon#about to read 3, iclass 38, count 0 2006.285.20:46:02.70#ibcon#read 3, iclass 38, count 0 2006.285.20:46:02.70#ibcon#about to read 4, iclass 38, count 0 2006.285.20:46:02.70#ibcon#read 4, iclass 38, count 0 2006.285.20:46:02.70#ibcon#about to read 5, iclass 38, count 0 2006.285.20:46:02.70#ibcon#read 5, iclass 38, count 0 2006.285.20:46:02.70#ibcon#about to read 6, iclass 38, count 0 2006.285.20:46:02.70#ibcon#read 6, iclass 38, count 0 2006.285.20:46:02.70#ibcon#end of sib2, iclass 38, count 0 2006.285.20:46:02.70#ibcon#*after write, iclass 38, count 0 2006.285.20:46:02.70#ibcon#*before return 0, iclass 38, count 0 2006.285.20:46:02.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:46:02.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.20:46:02.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.20:46:02.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.20:46:02.70$vck44/vb=7,4 2006.285.20:46:02.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.20:46:02.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.20:46:02.70#ibcon#ireg 11 cls_cnt 2 2006.285.20:46:02.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:46:02.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:46:02.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:46:02.70#ibcon#enter wrdev, iclass 40, count 2 2006.285.20:46:02.70#ibcon#first serial, iclass 40, count 2 2006.285.20:46:02.70#ibcon#enter sib2, iclass 40, count 2 2006.285.20:46:02.70#ibcon#flushed, iclass 40, count 2 2006.285.20:46:02.71#ibcon#about to write, iclass 40, count 2 2006.285.20:46:02.71#ibcon#wrote, iclass 40, count 2 2006.285.20:46:02.71#ibcon#about to read 3, iclass 40, count 2 2006.285.20:46:02.72#ibcon#read 3, iclass 40, count 2 2006.285.20:46:02.72#ibcon#about to read 4, iclass 40, count 2 2006.285.20:46:02.72#ibcon#read 4, iclass 40, count 2 2006.285.20:46:02.72#ibcon#about to read 5, iclass 40, count 2 2006.285.20:46:02.72#ibcon#read 5, iclass 40, count 2 2006.285.20:46:02.72#ibcon#about to read 6, iclass 40, count 2 2006.285.20:46:02.72#ibcon#read 6, iclass 40, count 2 2006.285.20:46:02.72#ibcon#end of sib2, iclass 40, count 2 2006.285.20:46:02.72#ibcon#*mode == 0, iclass 40, count 2 2006.285.20:46:02.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.20:46:02.72#ibcon#[27=AT07-04\r\n] 2006.285.20:46:02.72#ibcon#*before write, iclass 40, count 2 2006.285.20:46:02.72#ibcon#enter sib2, iclass 40, count 2 2006.285.20:46:02.72#ibcon#flushed, iclass 40, count 2 2006.285.20:46:02.72#ibcon#about to write, iclass 40, count 2 2006.285.20:46:02.72#ibcon#wrote, iclass 40, count 2 2006.285.20:46:02.72#ibcon#about to read 3, iclass 40, count 2 2006.285.20:46:02.75#ibcon#read 3, iclass 40, count 2 2006.285.20:46:02.75#ibcon#about to read 4, iclass 40, count 2 2006.285.20:46:02.75#ibcon#read 4, iclass 40, count 2 2006.285.20:46:02.75#ibcon#about to read 5, iclass 40, count 2 2006.285.20:46:02.75#ibcon#read 5, iclass 40, count 2 2006.285.20:46:02.75#ibcon#about to read 6, iclass 40, count 2 2006.285.20:46:02.75#ibcon#read 6, iclass 40, count 2 2006.285.20:46:02.75#ibcon#end of sib2, iclass 40, count 2 2006.285.20:46:02.75#ibcon#*after write, iclass 40, count 2 2006.285.20:46:02.75#ibcon#*before return 0, iclass 40, count 2 2006.285.20:46:02.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:46:02.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.20:46:02.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.20:46:02.75#ibcon#ireg 7 cls_cnt 0 2006.285.20:46:02.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:46:02.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:46:02.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:46:02.87#ibcon#enter wrdev, iclass 40, count 0 2006.285.20:46:02.87#ibcon#first serial, iclass 40, count 0 2006.285.20:46:02.87#ibcon#enter sib2, iclass 40, count 0 2006.285.20:46:02.87#ibcon#flushed, iclass 40, count 0 2006.285.20:46:02.87#ibcon#about to write, iclass 40, count 0 2006.285.20:46:02.87#ibcon#wrote, iclass 40, count 0 2006.285.20:46:02.87#ibcon#about to read 3, iclass 40, count 0 2006.285.20:46:02.89#ibcon#read 3, iclass 40, count 0 2006.285.20:46:02.89#ibcon#about to read 4, iclass 40, count 0 2006.285.20:46:02.89#ibcon#read 4, iclass 40, count 0 2006.285.20:46:02.89#ibcon#about to read 5, iclass 40, count 0 2006.285.20:46:02.89#ibcon#read 5, iclass 40, count 0 2006.285.20:46:02.89#ibcon#about to read 6, iclass 40, count 0 2006.285.20:46:02.89#ibcon#read 6, iclass 40, count 0 2006.285.20:46:02.89#ibcon#end of sib2, iclass 40, count 0 2006.285.20:46:02.89#ibcon#*mode == 0, iclass 40, count 0 2006.285.20:46:02.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.20:46:02.89#ibcon#[27=USB\r\n] 2006.285.20:46:02.89#ibcon#*before write, iclass 40, count 0 2006.285.20:46:02.89#ibcon#enter sib2, iclass 40, count 0 2006.285.20:46:02.89#ibcon#flushed, iclass 40, count 0 2006.285.20:46:02.89#ibcon#about to write, iclass 40, count 0 2006.285.20:46:02.89#ibcon#wrote, iclass 40, count 0 2006.285.20:46:02.89#ibcon#about to read 3, iclass 40, count 0 2006.285.20:46:02.92#ibcon#read 3, iclass 40, count 0 2006.285.20:46:02.92#ibcon#about to read 4, iclass 40, count 0 2006.285.20:46:02.92#ibcon#read 4, iclass 40, count 0 2006.285.20:46:02.92#ibcon#about to read 5, iclass 40, count 0 2006.285.20:46:02.92#ibcon#read 5, iclass 40, count 0 2006.285.20:46:02.92#ibcon#about to read 6, iclass 40, count 0 2006.285.20:46:02.92#ibcon#read 6, iclass 40, count 0 2006.285.20:46:02.92#ibcon#end of sib2, iclass 40, count 0 2006.285.20:46:02.92#ibcon#*after write, iclass 40, count 0 2006.285.20:46:02.92#ibcon#*before return 0, iclass 40, count 0 2006.285.20:46:02.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:46:02.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.20:46:02.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.20:46:02.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.20:46:02.92$vck44/vblo=8,744.99 2006.285.20:46:02.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.20:46:02.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.20:46:02.92#ibcon#ireg 17 cls_cnt 0 2006.285.20:46:02.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:46:02.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:46:02.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:46:02.92#ibcon#enter wrdev, iclass 4, count 0 2006.285.20:46:02.92#ibcon#first serial, iclass 4, count 0 2006.285.20:46:02.92#ibcon#enter sib2, iclass 4, count 0 2006.285.20:46:02.92#ibcon#flushed, iclass 4, count 0 2006.285.20:46:02.92#ibcon#about to write, iclass 4, count 0 2006.285.20:46:02.92#ibcon#wrote, iclass 4, count 0 2006.285.20:46:02.92#ibcon#about to read 3, iclass 4, count 0 2006.285.20:46:02.94#ibcon#read 3, iclass 4, count 0 2006.285.20:46:02.94#ibcon#about to read 4, iclass 4, count 0 2006.285.20:46:02.94#ibcon#read 4, iclass 4, count 0 2006.285.20:46:02.94#ibcon#about to read 5, iclass 4, count 0 2006.285.20:46:02.94#ibcon#read 5, iclass 4, count 0 2006.285.20:46:02.94#ibcon#about to read 6, iclass 4, count 0 2006.285.20:46:02.94#ibcon#read 6, iclass 4, count 0 2006.285.20:46:02.94#ibcon#end of sib2, iclass 4, count 0 2006.285.20:46:02.94#ibcon#*mode == 0, iclass 4, count 0 2006.285.20:46:02.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.20:46:02.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.20:46:02.94#ibcon#*before write, iclass 4, count 0 2006.285.20:46:02.94#ibcon#enter sib2, iclass 4, count 0 2006.285.20:46:02.94#ibcon#flushed, iclass 4, count 0 2006.285.20:46:02.94#ibcon#about to write, iclass 4, count 0 2006.285.20:46:02.94#ibcon#wrote, iclass 4, count 0 2006.285.20:46:02.94#ibcon#about to read 3, iclass 4, count 0 2006.285.20:46:02.98#ibcon#read 3, iclass 4, count 0 2006.285.20:46:02.98#ibcon#about to read 4, iclass 4, count 0 2006.285.20:46:02.98#ibcon#read 4, iclass 4, count 0 2006.285.20:46:02.98#ibcon#about to read 5, iclass 4, count 0 2006.285.20:46:02.98#ibcon#read 5, iclass 4, count 0 2006.285.20:46:02.98#ibcon#about to read 6, iclass 4, count 0 2006.285.20:46:02.98#ibcon#read 6, iclass 4, count 0 2006.285.20:46:02.98#ibcon#end of sib2, iclass 4, count 0 2006.285.20:46:02.98#ibcon#*after write, iclass 4, count 0 2006.285.20:46:02.98#ibcon#*before return 0, iclass 4, count 0 2006.285.20:46:02.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:46:02.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.20:46:02.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.20:46:02.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.20:46:02.98$vck44/vb=8,4 2006.285.20:46:02.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.20:46:02.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.20:46:02.98#ibcon#ireg 11 cls_cnt 2 2006.285.20:46:02.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:46:03.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:46:03.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:46:03.04#ibcon#enter wrdev, iclass 6, count 2 2006.285.20:46:03.04#ibcon#first serial, iclass 6, count 2 2006.285.20:46:03.04#ibcon#enter sib2, iclass 6, count 2 2006.285.20:46:03.04#ibcon#flushed, iclass 6, count 2 2006.285.20:46:03.04#ibcon#about to write, iclass 6, count 2 2006.285.20:46:03.04#ibcon#wrote, iclass 6, count 2 2006.285.20:46:03.04#ibcon#about to read 3, iclass 6, count 2 2006.285.20:46:03.06#ibcon#read 3, iclass 6, count 2 2006.285.20:46:03.06#ibcon#about to read 4, iclass 6, count 2 2006.285.20:46:03.06#ibcon#read 4, iclass 6, count 2 2006.285.20:46:03.06#ibcon#about to read 5, iclass 6, count 2 2006.285.20:46:03.06#ibcon#read 5, iclass 6, count 2 2006.285.20:46:03.06#ibcon#about to read 6, iclass 6, count 2 2006.285.20:46:03.06#ibcon#read 6, iclass 6, count 2 2006.285.20:46:03.06#ibcon#end of sib2, iclass 6, count 2 2006.285.20:46:03.06#ibcon#*mode == 0, iclass 6, count 2 2006.285.20:46:03.06#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.20:46:03.06#ibcon#[27=AT08-04\r\n] 2006.285.20:46:03.06#ibcon#*before write, iclass 6, count 2 2006.285.20:46:03.06#ibcon#enter sib2, iclass 6, count 2 2006.285.20:46:03.06#ibcon#flushed, iclass 6, count 2 2006.285.20:46:03.06#ibcon#about to write, iclass 6, count 2 2006.285.20:46:03.06#ibcon#wrote, iclass 6, count 2 2006.285.20:46:03.06#ibcon#about to read 3, iclass 6, count 2 2006.285.20:46:03.09#ibcon#read 3, iclass 6, count 2 2006.285.20:46:03.09#ibcon#about to read 4, iclass 6, count 2 2006.285.20:46:03.09#ibcon#read 4, iclass 6, count 2 2006.285.20:46:03.09#ibcon#about to read 5, iclass 6, count 2 2006.285.20:46:03.09#ibcon#read 5, iclass 6, count 2 2006.285.20:46:03.09#ibcon#about to read 6, iclass 6, count 2 2006.285.20:46:03.09#ibcon#read 6, iclass 6, count 2 2006.285.20:46:03.09#ibcon#end of sib2, iclass 6, count 2 2006.285.20:46:03.09#ibcon#*after write, iclass 6, count 2 2006.285.20:46:03.09#ibcon#*before return 0, iclass 6, count 2 2006.285.20:46:03.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:46:03.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.20:46:03.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.20:46:03.09#ibcon#ireg 7 cls_cnt 0 2006.285.20:46:03.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:46:03.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:46:03.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:46:03.21#ibcon#enter wrdev, iclass 6, count 0 2006.285.20:46:03.21#ibcon#first serial, iclass 6, count 0 2006.285.20:46:03.21#ibcon#enter sib2, iclass 6, count 0 2006.285.20:46:03.21#ibcon#flushed, iclass 6, count 0 2006.285.20:46:03.21#ibcon#about to write, iclass 6, count 0 2006.285.20:46:03.21#ibcon#wrote, iclass 6, count 0 2006.285.20:46:03.21#ibcon#about to read 3, iclass 6, count 0 2006.285.20:46:03.23#ibcon#read 3, iclass 6, count 0 2006.285.20:46:03.23#ibcon#about to read 4, iclass 6, count 0 2006.285.20:46:03.23#ibcon#read 4, iclass 6, count 0 2006.285.20:46:03.23#ibcon#about to read 5, iclass 6, count 0 2006.285.20:46:03.23#ibcon#read 5, iclass 6, count 0 2006.285.20:46:03.23#ibcon#about to read 6, iclass 6, count 0 2006.285.20:46:03.23#ibcon#read 6, iclass 6, count 0 2006.285.20:46:03.23#ibcon#end of sib2, iclass 6, count 0 2006.285.20:46:03.23#ibcon#*mode == 0, iclass 6, count 0 2006.285.20:46:03.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.20:46:03.23#ibcon#[27=USB\r\n] 2006.285.20:46:03.23#ibcon#*before write, iclass 6, count 0 2006.285.20:46:03.23#ibcon#enter sib2, iclass 6, count 0 2006.285.20:46:03.23#ibcon#flushed, iclass 6, count 0 2006.285.20:46:03.23#ibcon#about to write, iclass 6, count 0 2006.285.20:46:03.23#ibcon#wrote, iclass 6, count 0 2006.285.20:46:03.23#ibcon#about to read 3, iclass 6, count 0 2006.285.20:46:03.26#ibcon#read 3, iclass 6, count 0 2006.285.20:46:03.26#ibcon#about to read 4, iclass 6, count 0 2006.285.20:46:03.26#ibcon#read 4, iclass 6, count 0 2006.285.20:46:03.26#ibcon#about to read 5, iclass 6, count 0 2006.285.20:46:03.26#ibcon#read 5, iclass 6, count 0 2006.285.20:46:03.26#ibcon#about to read 6, iclass 6, count 0 2006.285.20:46:03.26#ibcon#read 6, iclass 6, count 0 2006.285.20:46:03.26#ibcon#end of sib2, iclass 6, count 0 2006.285.20:46:03.26#ibcon#*after write, iclass 6, count 0 2006.285.20:46:03.26#ibcon#*before return 0, iclass 6, count 0 2006.285.20:46:03.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:46:03.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.20:46:03.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.20:46:03.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.20:46:03.26$vck44/vabw=wide 2006.285.20:46:03.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.20:46:03.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.20:46:03.26#ibcon#ireg 8 cls_cnt 0 2006.285.20:46:03.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:46:03.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:46:03.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:46:03.26#ibcon#enter wrdev, iclass 10, count 0 2006.285.20:46:03.26#ibcon#first serial, iclass 10, count 0 2006.285.20:46:03.26#ibcon#enter sib2, iclass 10, count 0 2006.285.20:46:03.26#ibcon#flushed, iclass 10, count 0 2006.285.20:46:03.26#ibcon#about to write, iclass 10, count 0 2006.285.20:46:03.26#ibcon#wrote, iclass 10, count 0 2006.285.20:46:03.26#ibcon#about to read 3, iclass 10, count 0 2006.285.20:46:03.28#ibcon#read 3, iclass 10, count 0 2006.285.20:46:03.28#ibcon#about to read 4, iclass 10, count 0 2006.285.20:46:03.28#ibcon#read 4, iclass 10, count 0 2006.285.20:46:03.28#ibcon#about to read 5, iclass 10, count 0 2006.285.20:46:03.28#ibcon#read 5, iclass 10, count 0 2006.285.20:46:03.28#ibcon#about to read 6, iclass 10, count 0 2006.285.20:46:03.28#ibcon#read 6, iclass 10, count 0 2006.285.20:46:03.28#ibcon#end of sib2, iclass 10, count 0 2006.285.20:46:03.28#ibcon#*mode == 0, iclass 10, count 0 2006.285.20:46:03.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.20:46:03.28#ibcon#[25=BW32\r\n] 2006.285.20:46:03.28#ibcon#*before write, iclass 10, count 0 2006.285.20:46:03.28#ibcon#enter sib2, iclass 10, count 0 2006.285.20:46:03.28#ibcon#flushed, iclass 10, count 0 2006.285.20:46:03.28#ibcon#about to write, iclass 10, count 0 2006.285.20:46:03.28#ibcon#wrote, iclass 10, count 0 2006.285.20:46:03.28#ibcon#about to read 3, iclass 10, count 0 2006.285.20:46:03.31#ibcon#read 3, iclass 10, count 0 2006.285.20:46:03.31#ibcon#about to read 4, iclass 10, count 0 2006.285.20:46:03.31#ibcon#read 4, iclass 10, count 0 2006.285.20:46:03.31#ibcon#about to read 5, iclass 10, count 0 2006.285.20:46:03.31#ibcon#read 5, iclass 10, count 0 2006.285.20:46:03.31#ibcon#about to read 6, iclass 10, count 0 2006.285.20:46:03.31#ibcon#read 6, iclass 10, count 0 2006.285.20:46:03.31#ibcon#end of sib2, iclass 10, count 0 2006.285.20:46:03.31#ibcon#*after write, iclass 10, count 0 2006.285.20:46:03.31#ibcon#*before return 0, iclass 10, count 0 2006.285.20:46:03.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:46:03.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.20:46:03.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.20:46:03.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.20:46:03.31$vck44/vbbw=wide 2006.285.20:46:03.31#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.20:46:03.31#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.20:46:03.31#ibcon#ireg 8 cls_cnt 0 2006.285.20:46:03.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:46:03.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:46:03.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:46:03.38#ibcon#enter wrdev, iclass 12, count 0 2006.285.20:46:03.38#ibcon#first serial, iclass 12, count 0 2006.285.20:46:03.38#ibcon#enter sib2, iclass 12, count 0 2006.285.20:46:03.38#ibcon#flushed, iclass 12, count 0 2006.285.20:46:03.38#ibcon#about to write, iclass 12, count 0 2006.285.20:46:03.38#ibcon#wrote, iclass 12, count 0 2006.285.20:46:03.38#ibcon#about to read 3, iclass 12, count 0 2006.285.20:46:03.40#ibcon#read 3, iclass 12, count 0 2006.285.20:46:03.40#ibcon#about to read 4, iclass 12, count 0 2006.285.20:46:03.40#ibcon#read 4, iclass 12, count 0 2006.285.20:46:03.40#ibcon#about to read 5, iclass 12, count 0 2006.285.20:46:03.40#ibcon#read 5, iclass 12, count 0 2006.285.20:46:03.40#ibcon#about to read 6, iclass 12, count 0 2006.285.20:46:03.40#ibcon#read 6, iclass 12, count 0 2006.285.20:46:03.40#ibcon#end of sib2, iclass 12, count 0 2006.285.20:46:03.40#ibcon#*mode == 0, iclass 12, count 0 2006.285.20:46:03.40#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.20:46:03.40#ibcon#[27=BW32\r\n] 2006.285.20:46:03.40#ibcon#*before write, iclass 12, count 0 2006.285.20:46:03.40#ibcon#enter sib2, iclass 12, count 0 2006.285.20:46:03.40#ibcon#flushed, iclass 12, count 0 2006.285.20:46:03.40#ibcon#about to write, iclass 12, count 0 2006.285.20:46:03.40#ibcon#wrote, iclass 12, count 0 2006.285.20:46:03.40#ibcon#about to read 3, iclass 12, count 0 2006.285.20:46:03.43#ibcon#read 3, iclass 12, count 0 2006.285.20:46:03.43#ibcon#about to read 4, iclass 12, count 0 2006.285.20:46:03.43#ibcon#read 4, iclass 12, count 0 2006.285.20:46:03.43#ibcon#about to read 5, iclass 12, count 0 2006.285.20:46:03.43#ibcon#read 5, iclass 12, count 0 2006.285.20:46:03.43#ibcon#about to read 6, iclass 12, count 0 2006.285.20:46:03.43#ibcon#read 6, iclass 12, count 0 2006.285.20:46:03.43#ibcon#end of sib2, iclass 12, count 0 2006.285.20:46:03.43#ibcon#*after write, iclass 12, count 0 2006.285.20:46:03.43#ibcon#*before return 0, iclass 12, count 0 2006.285.20:46:03.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:46:03.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.20:46:03.43#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.20:46:03.43#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.20:46:03.43$setupk4/ifdk4 2006.285.20:46:03.43$ifdk4/lo= 2006.285.20:46:03.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.20:46:03.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.20:46:03.44$ifdk4/patch= 2006.285.20:46:03.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.20:46:03.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.20:46:03.44$setupk4/!*+20s 2006.285.20:46:05.90#abcon#<5=/00 0.2 0.7 14.171001015.4\r\n> 2006.285.20:46:05.92#abcon#{5=INTERFACE CLEAR} 2006.285.20:46:05.98#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:46:16.07#abcon#<5=/00 0.2 0.7 14.171001015.4\r\n> 2006.285.20:46:16.09#abcon#{5=INTERFACE CLEAR} 2006.285.20:46:16.15#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:46:17.40$setupk4/"tpicd 2006.285.20:46:17.40$setupk4/echo=off 2006.285.20:46:17.40$setupk4/xlog=off 2006.285.20:46:17.40:!2006.285.20:47:42 2006.285.20:46:25.14#trakl#Source acquired 2006.285.20:46:27.14#flagr#flagr/antenna,acquired 2006.285.20:47:42.00:preob 2006.285.20:47:43.14/onsource/TRACKING 2006.285.20:47:43.14:!2006.285.20:47:52 2006.285.20:47:52.00:"tape 2006.285.20:47:52.00:"st=record 2006.285.20:47:52.00:data_valid=on 2006.285.20:47:52.00:midob 2006.285.20:47:52.14/onsource/TRACKING 2006.285.20:47:52.14/wx/14.17,1015.4,100 2006.285.20:47:52.31/cable/+6.5077E-03 2006.285.20:47:53.40/va/01,07,usb,yes,37,40 2006.285.20:47:53.40/va/02,06,usb,yes,37,38 2006.285.20:47:53.40/va/03,07,usb,yes,37,39 2006.285.20:47:53.40/va/04,06,usb,yes,39,40 2006.285.20:47:53.40/va/05,03,usb,yes,38,38 2006.285.20:47:53.40/va/06,04,usb,yes,34,34 2006.285.20:47:53.40/va/07,04,usb,yes,35,35 2006.285.20:47:53.40/va/08,03,usb,yes,36,43 2006.285.20:47:53.63/valo/01,524.99,yes,locked 2006.285.20:47:53.63/valo/02,534.99,yes,locked 2006.285.20:47:53.63/valo/03,564.99,yes,locked 2006.285.20:47:53.63/valo/04,624.99,yes,locked 2006.285.20:47:53.63/valo/05,734.99,yes,locked 2006.285.20:47:53.63/valo/06,814.99,yes,locked 2006.285.20:47:53.63/valo/07,864.99,yes,locked 2006.285.20:47:53.63/valo/08,884.99,yes,locked 2006.285.20:47:54.72/vb/01,04,usb,yes,39,36 2006.285.20:47:54.72/vb/02,05,usb,yes,36,36 2006.285.20:47:54.72/vb/03,04,usb,yes,38,41 2006.285.20:47:54.72/vb/04,05,usb,yes,38,37 2006.285.20:47:54.72/vb/05,04,usb,yes,33,36 2006.285.20:47:54.72/vb/06,03,usb,yes,47,42 2006.285.20:47:54.72/vb/07,04,usb,yes,38,38 2006.285.20:47:54.72/vb/08,04,usb,yes,35,39 2006.285.20:47:54.95/vblo/01,629.99,yes,locked 2006.285.20:47:54.95/vblo/02,634.99,yes,locked 2006.285.20:47:54.95/vblo/03,649.99,yes,locked 2006.285.20:47:54.95/vblo/04,679.99,yes,locked 2006.285.20:47:54.95/vblo/05,709.99,yes,locked 2006.285.20:47:54.95/vblo/06,719.99,yes,locked 2006.285.20:47:54.95/vblo/07,734.99,yes,locked 2006.285.20:47:54.95/vblo/08,744.99,yes,locked 2006.285.20:47:55.10/vabw/8 2006.285.20:47:55.25/vbbw/8 2006.285.20:47:55.34/xfe/off,on,12.0 2006.285.20:47:55.71/ifatt/23,28,28,28 2006.285.20:47:56.07/fmout-gps/S +2.91E-07 2006.285.20:47:56.09:!2006.285.20:49:32 2006.285.20:49:32.01:data_valid=off 2006.285.20:49:32.01:"et 2006.285.20:49:32.01:!+3s 2006.285.20:49:35.02:"tape 2006.285.20:49:35.02:postob 2006.285.20:49:35.22/cable/+6.5085E-03 2006.285.20:49:35.22/wx/14.18,1015.4,100 2006.285.20:49:35.28/fmout-gps/S +2.90E-07 2006.285.20:49:35.28:scan_name=285-2052,jd0610,290 2006.285.20:49:35.28:source=oj287,085448.87,200630.6,2000.0,ccw 2006.285.20:49:37.14#flagr#flagr/antenna,new-source 2006.285.20:49:37.14:checkk5 2006.285.20:49:37.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.20:49:38.04/chk_autoobs//k5ts2/ autoobs is running! 2006.285.20:49:38.55/chk_autoobs//k5ts3/ autoobs is running! 2006.285.20:49:39.02/chk_autoobs//k5ts4/ autoobs is running! 2006.285.20:49:39.36/chk_obsdata//k5ts1/T2852047??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.20:49:40.07/chk_obsdata//k5ts2/T2852047??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.20:49:40.56/chk_obsdata//k5ts3/T2852047??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.20:49:41.00/chk_obsdata//k5ts4/T2852047??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.285.20:49:41.91/k5log//k5ts1_log_newline 2006.285.20:49:42.78/k5log//k5ts2_log_newline 2006.285.20:49:43.51/k5log//k5ts3_log_newline 2006.285.20:49:44.30/k5log//k5ts4_log_newline 2006.285.20:49:44.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.20:49:44.32:setupk4=1 2006.285.20:49:44.32$setupk4/echo=on 2006.285.20:49:44.32$setupk4/pcalon 2006.285.20:49:44.32$pcalon/"no phase cal control is implemented here 2006.285.20:49:44.32$setupk4/"tpicd=stop 2006.285.20:49:44.32$setupk4/"rec=synch_on 2006.285.20:49:44.32$setupk4/"rec_mode=128 2006.285.20:49:44.32$setupk4/!* 2006.285.20:49:44.32$setupk4/recpk4 2006.285.20:49:44.32$recpk4/recpatch= 2006.285.20:49:44.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.20:49:44.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.20:49:44.32$setupk4/vck44 2006.285.20:49:44.32$vck44/valo=1,524.99 2006.285.20:49:44.32#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.20:49:44.32#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.20:49:44.32#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:44.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:49:44.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:49:44.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:49:44.33#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:49:44.33#ibcon#first serial, iclass 33, count 0 2006.285.20:49:44.33#ibcon#enter sib2, iclass 33, count 0 2006.285.20:49:44.33#ibcon#flushed, iclass 33, count 0 2006.285.20:49:44.33#ibcon#about to write, iclass 33, count 0 2006.285.20:49:44.33#ibcon#wrote, iclass 33, count 0 2006.285.20:49:44.33#ibcon#about to read 3, iclass 33, count 0 2006.285.20:49:44.34#ibcon#read 3, iclass 33, count 0 2006.285.20:49:44.34#ibcon#about to read 4, iclass 33, count 0 2006.285.20:49:44.34#ibcon#read 4, iclass 33, count 0 2006.285.20:49:44.34#ibcon#about to read 5, iclass 33, count 0 2006.285.20:49:44.34#ibcon#read 5, iclass 33, count 0 2006.285.20:49:44.34#ibcon#about to read 6, iclass 33, count 0 2006.285.20:49:44.34#ibcon#read 6, iclass 33, count 0 2006.285.20:49:44.34#ibcon#end of sib2, iclass 33, count 0 2006.285.20:49:44.34#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:49:44.34#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:49:44.34#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.20:49:44.34#ibcon#*before write, iclass 33, count 0 2006.285.20:49:44.34#ibcon#enter sib2, iclass 33, count 0 2006.285.20:49:44.34#ibcon#flushed, iclass 33, count 0 2006.285.20:49:44.34#ibcon#about to write, iclass 33, count 0 2006.285.20:49:44.34#ibcon#wrote, iclass 33, count 0 2006.285.20:49:44.34#ibcon#about to read 3, iclass 33, count 0 2006.285.20:49:44.39#ibcon#read 3, iclass 33, count 0 2006.285.20:49:44.39#ibcon#about to read 4, iclass 33, count 0 2006.285.20:49:44.39#ibcon#read 4, iclass 33, count 0 2006.285.20:49:44.39#ibcon#about to read 5, iclass 33, count 0 2006.285.20:49:44.39#ibcon#read 5, iclass 33, count 0 2006.285.20:49:44.39#ibcon#about to read 6, iclass 33, count 0 2006.285.20:49:44.39#ibcon#read 6, iclass 33, count 0 2006.285.20:49:44.39#ibcon#end of sib2, iclass 33, count 0 2006.285.20:49:44.39#ibcon#*after write, iclass 33, count 0 2006.285.20:49:44.39#ibcon#*before return 0, iclass 33, count 0 2006.285.20:49:44.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:49:44.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:49:44.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:49:44.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:49:44.39$vck44/va=1,7 2006.285.20:49:44.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.20:49:44.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.20:49:44.39#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:44.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:49:44.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:49:44.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:49:44.39#ibcon#enter wrdev, iclass 35, count 2 2006.285.20:49:44.39#ibcon#first serial, iclass 35, count 2 2006.285.20:49:44.39#ibcon#enter sib2, iclass 35, count 2 2006.285.20:49:44.39#ibcon#flushed, iclass 35, count 2 2006.285.20:49:44.39#ibcon#about to write, iclass 35, count 2 2006.285.20:49:44.39#ibcon#wrote, iclass 35, count 2 2006.285.20:49:44.39#ibcon#about to read 3, iclass 35, count 2 2006.285.20:49:44.41#ibcon#read 3, iclass 35, count 2 2006.285.20:49:44.41#ibcon#about to read 4, iclass 35, count 2 2006.285.20:49:44.41#ibcon#read 4, iclass 35, count 2 2006.285.20:49:44.41#ibcon#about to read 5, iclass 35, count 2 2006.285.20:49:44.41#ibcon#read 5, iclass 35, count 2 2006.285.20:49:44.41#ibcon#about to read 6, iclass 35, count 2 2006.285.20:49:44.41#ibcon#read 6, iclass 35, count 2 2006.285.20:49:44.41#ibcon#end of sib2, iclass 35, count 2 2006.285.20:49:44.41#ibcon#*mode == 0, iclass 35, count 2 2006.285.20:49:44.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.20:49:44.41#ibcon#[25=AT01-07\r\n] 2006.285.20:49:44.41#ibcon#*before write, iclass 35, count 2 2006.285.20:49:44.41#ibcon#enter sib2, iclass 35, count 2 2006.285.20:49:44.41#ibcon#flushed, iclass 35, count 2 2006.285.20:49:44.41#ibcon#about to write, iclass 35, count 2 2006.285.20:49:44.41#ibcon#wrote, iclass 35, count 2 2006.285.20:49:44.41#ibcon#about to read 3, iclass 35, count 2 2006.285.20:49:44.44#ibcon#read 3, iclass 35, count 2 2006.285.20:49:44.44#ibcon#about to read 4, iclass 35, count 2 2006.285.20:49:44.44#ibcon#read 4, iclass 35, count 2 2006.285.20:49:44.44#ibcon#about to read 5, iclass 35, count 2 2006.285.20:49:44.44#ibcon#read 5, iclass 35, count 2 2006.285.20:49:44.44#ibcon#about to read 6, iclass 35, count 2 2006.285.20:49:44.44#ibcon#read 6, iclass 35, count 2 2006.285.20:49:44.44#ibcon#end of sib2, iclass 35, count 2 2006.285.20:49:44.44#ibcon#*after write, iclass 35, count 2 2006.285.20:49:44.44#ibcon#*before return 0, iclass 35, count 2 2006.285.20:49:44.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:49:44.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:49:44.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.20:49:44.44#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:44.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:49:44.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:49:44.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:49:44.56#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:49:44.56#ibcon#first serial, iclass 35, count 0 2006.285.20:49:44.56#ibcon#enter sib2, iclass 35, count 0 2006.285.20:49:44.56#ibcon#flushed, iclass 35, count 0 2006.285.20:49:44.56#ibcon#about to write, iclass 35, count 0 2006.285.20:49:44.56#ibcon#wrote, iclass 35, count 0 2006.285.20:49:44.56#ibcon#about to read 3, iclass 35, count 0 2006.285.20:49:44.58#ibcon#read 3, iclass 35, count 0 2006.285.20:49:44.58#ibcon#about to read 4, iclass 35, count 0 2006.285.20:49:44.58#ibcon#read 4, iclass 35, count 0 2006.285.20:49:44.58#ibcon#about to read 5, iclass 35, count 0 2006.285.20:49:44.58#ibcon#read 5, iclass 35, count 0 2006.285.20:49:44.58#ibcon#about to read 6, iclass 35, count 0 2006.285.20:49:44.58#ibcon#read 6, iclass 35, count 0 2006.285.20:49:44.58#ibcon#end of sib2, iclass 35, count 0 2006.285.20:49:44.58#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:49:44.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:49:44.58#ibcon#[25=USB\r\n] 2006.285.20:49:44.58#ibcon#*before write, iclass 35, count 0 2006.285.20:49:44.58#ibcon#enter sib2, iclass 35, count 0 2006.285.20:49:44.58#ibcon#flushed, iclass 35, count 0 2006.285.20:49:44.58#ibcon#about to write, iclass 35, count 0 2006.285.20:49:44.58#ibcon#wrote, iclass 35, count 0 2006.285.20:49:44.58#ibcon#about to read 3, iclass 35, count 0 2006.285.20:49:44.61#ibcon#read 3, iclass 35, count 0 2006.285.20:49:44.61#ibcon#about to read 4, iclass 35, count 0 2006.285.20:49:44.61#ibcon#read 4, iclass 35, count 0 2006.285.20:49:44.61#ibcon#about to read 5, iclass 35, count 0 2006.285.20:49:44.61#ibcon#read 5, iclass 35, count 0 2006.285.20:49:44.61#ibcon#about to read 6, iclass 35, count 0 2006.285.20:49:44.61#ibcon#read 6, iclass 35, count 0 2006.285.20:49:44.61#ibcon#end of sib2, iclass 35, count 0 2006.285.20:49:44.61#ibcon#*after write, iclass 35, count 0 2006.285.20:49:44.61#ibcon#*before return 0, iclass 35, count 0 2006.285.20:49:44.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:49:44.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:49:44.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:49:44.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:49:44.61$vck44/valo=2,534.99 2006.285.20:49:44.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.20:49:44.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.20:49:44.61#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:44.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:49:44.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:49:44.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:49:44.61#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:49:44.61#ibcon#first serial, iclass 37, count 0 2006.285.20:49:44.61#ibcon#enter sib2, iclass 37, count 0 2006.285.20:49:44.61#ibcon#flushed, iclass 37, count 0 2006.285.20:49:44.61#ibcon#about to write, iclass 37, count 0 2006.285.20:49:44.61#ibcon#wrote, iclass 37, count 0 2006.285.20:49:44.61#ibcon#about to read 3, iclass 37, count 0 2006.285.20:49:44.63#ibcon#read 3, iclass 37, count 0 2006.285.20:49:44.63#ibcon#about to read 4, iclass 37, count 0 2006.285.20:49:44.63#ibcon#read 4, iclass 37, count 0 2006.285.20:49:44.63#ibcon#about to read 5, iclass 37, count 0 2006.285.20:49:44.63#ibcon#read 5, iclass 37, count 0 2006.285.20:49:44.63#ibcon#about to read 6, iclass 37, count 0 2006.285.20:49:44.63#ibcon#read 6, iclass 37, count 0 2006.285.20:49:44.63#ibcon#end of sib2, iclass 37, count 0 2006.285.20:49:44.63#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:49:44.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:49:44.63#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.20:49:44.63#ibcon#*before write, iclass 37, count 0 2006.285.20:49:44.63#ibcon#enter sib2, iclass 37, count 0 2006.285.20:49:44.63#ibcon#flushed, iclass 37, count 0 2006.285.20:49:44.63#ibcon#about to write, iclass 37, count 0 2006.285.20:49:44.63#ibcon#wrote, iclass 37, count 0 2006.285.20:49:44.63#ibcon#about to read 3, iclass 37, count 0 2006.285.20:49:44.67#ibcon#read 3, iclass 37, count 0 2006.285.20:49:44.67#ibcon#about to read 4, iclass 37, count 0 2006.285.20:49:44.67#ibcon#read 4, iclass 37, count 0 2006.285.20:49:44.67#ibcon#about to read 5, iclass 37, count 0 2006.285.20:49:44.67#ibcon#read 5, iclass 37, count 0 2006.285.20:49:44.67#ibcon#about to read 6, iclass 37, count 0 2006.285.20:49:44.67#ibcon#read 6, iclass 37, count 0 2006.285.20:49:44.67#ibcon#end of sib2, iclass 37, count 0 2006.285.20:49:44.67#ibcon#*after write, iclass 37, count 0 2006.285.20:49:44.67#ibcon#*before return 0, iclass 37, count 0 2006.285.20:49:44.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:49:44.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:49:44.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:49:44.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:49:44.67$vck44/va=2,6 2006.285.20:49:45.12#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.20:49:45.12#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.20:49:45.12#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:45.12#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:49:45.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:49:45.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:49:45.12#ibcon#enter wrdev, iclass 39, count 2 2006.285.20:49:45.12#ibcon#first serial, iclass 39, count 2 2006.285.20:49:45.12#ibcon#enter sib2, iclass 39, count 2 2006.285.20:49:45.12#ibcon#flushed, iclass 39, count 2 2006.285.20:49:45.12#ibcon#about to write, iclass 39, count 2 2006.285.20:49:45.12#ibcon#wrote, iclass 39, count 2 2006.285.20:49:45.12#ibcon#about to read 3, iclass 39, count 2 2006.285.20:49:45.14#ibcon#read 3, iclass 39, count 2 2006.285.20:49:45.14#ibcon#about to read 4, iclass 39, count 2 2006.285.20:49:45.14#ibcon#read 4, iclass 39, count 2 2006.285.20:49:45.14#ibcon#about to read 5, iclass 39, count 2 2006.285.20:49:45.14#ibcon#read 5, iclass 39, count 2 2006.285.20:49:45.14#ibcon#about to read 6, iclass 39, count 2 2006.285.20:49:45.14#ibcon#read 6, iclass 39, count 2 2006.285.20:49:45.14#ibcon#end of sib2, iclass 39, count 2 2006.285.20:49:45.14#ibcon#*mode == 0, iclass 39, count 2 2006.285.20:49:45.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.20:49:45.14#ibcon#[25=AT02-06\r\n] 2006.285.20:49:45.14#ibcon#*before write, iclass 39, count 2 2006.285.20:49:45.14#ibcon#enter sib2, iclass 39, count 2 2006.285.20:49:45.14#ibcon#flushed, iclass 39, count 2 2006.285.20:49:45.14#ibcon#about to write, iclass 39, count 2 2006.285.20:49:45.14#ibcon#wrote, iclass 39, count 2 2006.285.20:49:45.14#ibcon#about to read 3, iclass 39, count 2 2006.285.20:49:45.17#ibcon#read 3, iclass 39, count 2 2006.285.20:49:45.17#ibcon#about to read 4, iclass 39, count 2 2006.285.20:49:45.17#ibcon#read 4, iclass 39, count 2 2006.285.20:49:45.17#ibcon#about to read 5, iclass 39, count 2 2006.285.20:49:45.17#ibcon#read 5, iclass 39, count 2 2006.285.20:49:45.17#ibcon#about to read 6, iclass 39, count 2 2006.285.20:49:45.17#ibcon#read 6, iclass 39, count 2 2006.285.20:49:45.17#ibcon#end of sib2, iclass 39, count 2 2006.285.20:49:45.17#ibcon#*after write, iclass 39, count 2 2006.285.20:49:45.17#ibcon#*before return 0, iclass 39, count 2 2006.285.20:49:45.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:49:45.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:49:45.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.20:49:45.17#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:45.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:49:45.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:49:45.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:49:45.29#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:49:45.29#ibcon#first serial, iclass 39, count 0 2006.285.20:49:45.29#ibcon#enter sib2, iclass 39, count 0 2006.285.20:49:45.29#ibcon#flushed, iclass 39, count 0 2006.285.20:49:45.29#ibcon#about to write, iclass 39, count 0 2006.285.20:49:45.29#ibcon#wrote, iclass 39, count 0 2006.285.20:49:45.29#ibcon#about to read 3, iclass 39, count 0 2006.285.20:49:45.31#ibcon#read 3, iclass 39, count 0 2006.285.20:49:45.31#ibcon#about to read 4, iclass 39, count 0 2006.285.20:49:45.31#ibcon#read 4, iclass 39, count 0 2006.285.20:49:45.31#ibcon#about to read 5, iclass 39, count 0 2006.285.20:49:45.31#ibcon#read 5, iclass 39, count 0 2006.285.20:49:45.31#ibcon#about to read 6, iclass 39, count 0 2006.285.20:49:45.31#ibcon#read 6, iclass 39, count 0 2006.285.20:49:45.31#ibcon#end of sib2, iclass 39, count 0 2006.285.20:49:45.31#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:49:45.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:49:45.31#ibcon#[25=USB\r\n] 2006.285.20:49:45.31#ibcon#*before write, iclass 39, count 0 2006.285.20:49:45.31#ibcon#enter sib2, iclass 39, count 0 2006.285.20:49:45.31#ibcon#flushed, iclass 39, count 0 2006.285.20:49:45.31#ibcon#about to write, iclass 39, count 0 2006.285.20:49:45.31#ibcon#wrote, iclass 39, count 0 2006.285.20:49:45.31#ibcon#about to read 3, iclass 39, count 0 2006.285.20:49:45.34#ibcon#read 3, iclass 39, count 0 2006.285.20:49:45.34#ibcon#about to read 4, iclass 39, count 0 2006.285.20:49:45.34#ibcon#read 4, iclass 39, count 0 2006.285.20:49:45.34#ibcon#about to read 5, iclass 39, count 0 2006.285.20:49:45.34#ibcon#read 5, iclass 39, count 0 2006.285.20:49:45.34#ibcon#about to read 6, iclass 39, count 0 2006.285.20:49:45.34#ibcon#read 6, iclass 39, count 0 2006.285.20:49:45.34#ibcon#end of sib2, iclass 39, count 0 2006.285.20:49:45.34#ibcon#*after write, iclass 39, count 0 2006.285.20:49:45.34#ibcon#*before return 0, iclass 39, count 0 2006.285.20:49:45.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:49:45.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:49:45.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:49:45.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:49:45.34$vck44/valo=3,564.99 2006.285.20:49:45.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.20:49:45.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.20:49:45.34#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:45.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:49:45.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:49:45.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:49:45.34#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:49:45.34#ibcon#first serial, iclass 3, count 0 2006.285.20:49:45.34#ibcon#enter sib2, iclass 3, count 0 2006.285.20:49:45.34#ibcon#flushed, iclass 3, count 0 2006.285.20:49:45.34#ibcon#about to write, iclass 3, count 0 2006.285.20:49:45.34#ibcon#wrote, iclass 3, count 0 2006.285.20:49:45.34#ibcon#about to read 3, iclass 3, count 0 2006.285.20:49:45.36#ibcon#read 3, iclass 3, count 0 2006.285.20:49:45.36#ibcon#about to read 4, iclass 3, count 0 2006.285.20:49:45.36#ibcon#read 4, iclass 3, count 0 2006.285.20:49:45.51#ibcon#about to read 5, iclass 3, count 0 2006.285.20:49:45.51#ibcon#read 5, iclass 3, count 0 2006.285.20:49:45.51#ibcon#about to read 6, iclass 3, count 0 2006.285.20:49:45.51#ibcon#read 6, iclass 3, count 0 2006.285.20:49:45.51#ibcon#end of sib2, iclass 3, count 0 2006.285.20:49:45.51#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:49:45.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:49:45.51#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.20:49:45.51#ibcon#*before write, iclass 3, count 0 2006.285.20:49:45.51#ibcon#enter sib2, iclass 3, count 0 2006.285.20:49:45.51#ibcon#flushed, iclass 3, count 0 2006.285.20:49:45.51#ibcon#about to write, iclass 3, count 0 2006.285.20:49:45.51#ibcon#wrote, iclass 3, count 0 2006.285.20:49:45.51#ibcon#about to read 3, iclass 3, count 0 2006.285.20:49:45.55#ibcon#read 3, iclass 3, count 0 2006.285.20:49:45.55#ibcon#about to read 4, iclass 3, count 0 2006.285.20:49:45.55#ibcon#read 4, iclass 3, count 0 2006.285.20:49:45.55#ibcon#about to read 5, iclass 3, count 0 2006.285.20:49:45.55#ibcon#read 5, iclass 3, count 0 2006.285.20:49:45.55#ibcon#about to read 6, iclass 3, count 0 2006.285.20:49:45.55#ibcon#read 6, iclass 3, count 0 2006.285.20:49:45.55#ibcon#end of sib2, iclass 3, count 0 2006.285.20:49:45.55#ibcon#*after write, iclass 3, count 0 2006.285.20:49:45.55#ibcon#*before return 0, iclass 3, count 0 2006.285.20:49:45.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:49:45.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:49:45.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:49:45.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:49:45.55$vck44/va=3,7 2006.285.20:49:45.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.20:49:45.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.20:49:45.55#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:45.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:49:45.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:49:45.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:49:45.55#ibcon#enter wrdev, iclass 5, count 2 2006.285.20:49:45.55#ibcon#first serial, iclass 5, count 2 2006.285.20:49:45.55#ibcon#enter sib2, iclass 5, count 2 2006.285.20:49:45.55#ibcon#flushed, iclass 5, count 2 2006.285.20:49:45.55#ibcon#about to write, iclass 5, count 2 2006.285.20:49:45.55#ibcon#wrote, iclass 5, count 2 2006.285.20:49:45.55#ibcon#about to read 3, iclass 5, count 2 2006.285.20:49:45.57#ibcon#read 3, iclass 5, count 2 2006.285.20:49:45.57#ibcon#about to read 4, iclass 5, count 2 2006.285.20:49:45.57#ibcon#read 4, iclass 5, count 2 2006.285.20:49:45.57#ibcon#about to read 5, iclass 5, count 2 2006.285.20:49:45.57#ibcon#read 5, iclass 5, count 2 2006.285.20:49:45.57#ibcon#about to read 6, iclass 5, count 2 2006.285.20:49:45.57#ibcon#read 6, iclass 5, count 2 2006.285.20:49:45.57#ibcon#end of sib2, iclass 5, count 2 2006.285.20:49:45.57#ibcon#*mode == 0, iclass 5, count 2 2006.285.20:49:45.57#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.20:49:45.57#ibcon#[25=AT03-07\r\n] 2006.285.20:49:45.57#ibcon#*before write, iclass 5, count 2 2006.285.20:49:45.57#ibcon#enter sib2, iclass 5, count 2 2006.285.20:49:45.57#ibcon#flushed, iclass 5, count 2 2006.285.20:49:45.57#ibcon#about to write, iclass 5, count 2 2006.285.20:49:45.57#ibcon#wrote, iclass 5, count 2 2006.285.20:49:45.57#ibcon#about to read 3, iclass 5, count 2 2006.285.20:49:45.60#ibcon#read 3, iclass 5, count 2 2006.285.20:49:45.60#ibcon#about to read 4, iclass 5, count 2 2006.285.20:49:45.60#ibcon#read 4, iclass 5, count 2 2006.285.20:49:45.60#ibcon#about to read 5, iclass 5, count 2 2006.285.20:49:45.60#ibcon#read 5, iclass 5, count 2 2006.285.20:49:45.60#ibcon#about to read 6, iclass 5, count 2 2006.285.20:49:45.60#ibcon#read 6, iclass 5, count 2 2006.285.20:49:45.60#ibcon#end of sib2, iclass 5, count 2 2006.285.20:49:45.60#ibcon#*after write, iclass 5, count 2 2006.285.20:49:45.60#ibcon#*before return 0, iclass 5, count 2 2006.285.20:49:45.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:49:45.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:49:45.60#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.20:49:45.60#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:45.60#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:49:45.72#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:49:45.72#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:49:45.72#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:49:45.72#ibcon#first serial, iclass 5, count 0 2006.285.20:49:45.72#ibcon#enter sib2, iclass 5, count 0 2006.285.20:49:45.72#ibcon#flushed, iclass 5, count 0 2006.285.20:49:45.72#ibcon#about to write, iclass 5, count 0 2006.285.20:49:45.72#ibcon#wrote, iclass 5, count 0 2006.285.20:49:45.72#ibcon#about to read 3, iclass 5, count 0 2006.285.20:49:45.74#ibcon#read 3, iclass 5, count 0 2006.285.20:49:45.74#ibcon#about to read 4, iclass 5, count 0 2006.285.20:49:45.74#ibcon#read 4, iclass 5, count 0 2006.285.20:49:45.74#ibcon#about to read 5, iclass 5, count 0 2006.285.20:49:45.74#ibcon#read 5, iclass 5, count 0 2006.285.20:49:45.74#ibcon#about to read 6, iclass 5, count 0 2006.285.20:49:45.74#ibcon#read 6, iclass 5, count 0 2006.285.20:49:45.74#ibcon#end of sib2, iclass 5, count 0 2006.285.20:49:45.74#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:49:45.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:49:45.74#ibcon#[25=USB\r\n] 2006.285.20:49:45.74#ibcon#*before write, iclass 5, count 0 2006.285.20:49:45.74#ibcon#enter sib2, iclass 5, count 0 2006.285.20:49:45.74#ibcon#flushed, iclass 5, count 0 2006.285.20:49:45.74#ibcon#about to write, iclass 5, count 0 2006.285.20:49:45.74#ibcon#wrote, iclass 5, count 0 2006.285.20:49:45.74#ibcon#about to read 3, iclass 5, count 0 2006.285.20:49:45.77#ibcon#read 3, iclass 5, count 0 2006.285.20:49:45.77#ibcon#about to read 4, iclass 5, count 0 2006.285.20:49:45.77#ibcon#read 4, iclass 5, count 0 2006.285.20:49:45.77#ibcon#about to read 5, iclass 5, count 0 2006.285.20:49:45.77#ibcon#read 5, iclass 5, count 0 2006.285.20:49:45.77#ibcon#about to read 6, iclass 5, count 0 2006.285.20:49:45.77#ibcon#read 6, iclass 5, count 0 2006.285.20:49:45.77#ibcon#end of sib2, iclass 5, count 0 2006.285.20:49:45.77#ibcon#*after write, iclass 5, count 0 2006.285.20:49:45.77#ibcon#*before return 0, iclass 5, count 0 2006.285.20:49:45.77#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:49:45.77#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:49:45.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:49:45.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:49:45.77$vck44/valo=4,624.99 2006.285.20:49:45.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.20:49:45.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.20:49:45.77#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:45.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:49:45.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:49:45.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:49:45.77#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:49:45.77#ibcon#first serial, iclass 7, count 0 2006.285.20:49:45.77#ibcon#enter sib2, iclass 7, count 0 2006.285.20:49:45.77#ibcon#flushed, iclass 7, count 0 2006.285.20:49:45.77#ibcon#about to write, iclass 7, count 0 2006.285.20:49:45.77#ibcon#wrote, iclass 7, count 0 2006.285.20:49:45.77#ibcon#about to read 3, iclass 7, count 0 2006.285.20:49:45.79#ibcon#read 3, iclass 7, count 0 2006.285.20:49:45.79#ibcon#about to read 4, iclass 7, count 0 2006.285.20:49:45.79#ibcon#read 4, iclass 7, count 0 2006.285.20:49:45.79#ibcon#about to read 5, iclass 7, count 0 2006.285.20:49:45.79#ibcon#read 5, iclass 7, count 0 2006.285.20:49:45.79#ibcon#about to read 6, iclass 7, count 0 2006.285.20:49:45.79#ibcon#read 6, iclass 7, count 0 2006.285.20:49:45.79#ibcon#end of sib2, iclass 7, count 0 2006.285.20:49:45.79#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:49:45.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:49:45.79#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.20:49:45.79#ibcon#*before write, iclass 7, count 0 2006.285.20:49:45.79#ibcon#enter sib2, iclass 7, count 0 2006.285.20:49:45.79#ibcon#flushed, iclass 7, count 0 2006.285.20:49:45.79#ibcon#about to write, iclass 7, count 0 2006.285.20:49:45.79#ibcon#wrote, iclass 7, count 0 2006.285.20:49:45.79#ibcon#about to read 3, iclass 7, count 0 2006.285.20:49:45.83#ibcon#read 3, iclass 7, count 0 2006.285.20:49:45.83#ibcon#about to read 4, iclass 7, count 0 2006.285.20:49:45.83#ibcon#read 4, iclass 7, count 0 2006.285.20:49:45.83#ibcon#about to read 5, iclass 7, count 0 2006.285.20:49:45.83#ibcon#read 5, iclass 7, count 0 2006.285.20:49:45.83#ibcon#about to read 6, iclass 7, count 0 2006.285.20:49:45.83#ibcon#read 6, iclass 7, count 0 2006.285.20:49:45.83#ibcon#end of sib2, iclass 7, count 0 2006.285.20:49:45.83#ibcon#*after write, iclass 7, count 0 2006.285.20:49:45.83#ibcon#*before return 0, iclass 7, count 0 2006.285.20:49:45.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:49:45.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:49:45.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:49:45.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:49:45.83$vck44/va=4,6 2006.285.20:49:45.83#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.20:49:45.83#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.20:49:45.83#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:45.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:49:45.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:49:45.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:49:45.89#ibcon#enter wrdev, iclass 11, count 2 2006.285.20:49:45.89#ibcon#first serial, iclass 11, count 2 2006.285.20:49:45.89#ibcon#enter sib2, iclass 11, count 2 2006.285.20:49:45.89#ibcon#flushed, iclass 11, count 2 2006.285.20:49:45.89#ibcon#about to write, iclass 11, count 2 2006.285.20:49:45.89#ibcon#wrote, iclass 11, count 2 2006.285.20:49:45.89#ibcon#about to read 3, iclass 11, count 2 2006.285.20:49:45.91#ibcon#read 3, iclass 11, count 2 2006.285.20:49:45.91#ibcon#about to read 4, iclass 11, count 2 2006.285.20:49:45.91#ibcon#read 4, iclass 11, count 2 2006.285.20:49:45.91#ibcon#about to read 5, iclass 11, count 2 2006.285.20:49:45.91#ibcon#read 5, iclass 11, count 2 2006.285.20:49:45.91#ibcon#about to read 6, iclass 11, count 2 2006.285.20:49:45.91#ibcon#read 6, iclass 11, count 2 2006.285.20:49:45.91#ibcon#end of sib2, iclass 11, count 2 2006.285.20:49:45.91#ibcon#*mode == 0, iclass 11, count 2 2006.285.20:49:45.91#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.20:49:45.91#ibcon#[25=AT04-06\r\n] 2006.285.20:49:45.91#ibcon#*before write, iclass 11, count 2 2006.285.20:49:45.91#ibcon#enter sib2, iclass 11, count 2 2006.285.20:49:45.91#ibcon#flushed, iclass 11, count 2 2006.285.20:49:45.91#ibcon#about to write, iclass 11, count 2 2006.285.20:49:45.91#ibcon#wrote, iclass 11, count 2 2006.285.20:49:45.91#ibcon#about to read 3, iclass 11, count 2 2006.285.20:49:45.94#ibcon#read 3, iclass 11, count 2 2006.285.20:49:45.94#ibcon#about to read 4, iclass 11, count 2 2006.285.20:49:45.94#ibcon#read 4, iclass 11, count 2 2006.285.20:49:45.94#ibcon#about to read 5, iclass 11, count 2 2006.285.20:49:45.94#ibcon#read 5, iclass 11, count 2 2006.285.20:49:45.94#ibcon#about to read 6, iclass 11, count 2 2006.285.20:49:45.94#ibcon#read 6, iclass 11, count 2 2006.285.20:49:45.94#ibcon#end of sib2, iclass 11, count 2 2006.285.20:49:45.94#ibcon#*after write, iclass 11, count 2 2006.285.20:49:45.94#ibcon#*before return 0, iclass 11, count 2 2006.285.20:49:45.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:49:45.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:49:45.94#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.20:49:45.94#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:45.94#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:49:46.06#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:49:46.06#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:49:46.06#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:49:46.06#ibcon#first serial, iclass 11, count 0 2006.285.20:49:46.06#ibcon#enter sib2, iclass 11, count 0 2006.285.20:49:46.06#ibcon#flushed, iclass 11, count 0 2006.285.20:49:46.06#ibcon#about to write, iclass 11, count 0 2006.285.20:49:46.06#ibcon#wrote, iclass 11, count 0 2006.285.20:49:46.06#ibcon#about to read 3, iclass 11, count 0 2006.285.20:49:46.08#ibcon#read 3, iclass 11, count 0 2006.285.20:49:46.08#ibcon#about to read 4, iclass 11, count 0 2006.285.20:49:46.08#ibcon#read 4, iclass 11, count 0 2006.285.20:49:46.08#ibcon#about to read 5, iclass 11, count 0 2006.285.20:49:46.08#ibcon#read 5, iclass 11, count 0 2006.285.20:49:46.08#ibcon#about to read 6, iclass 11, count 0 2006.285.20:49:46.08#ibcon#read 6, iclass 11, count 0 2006.285.20:49:46.08#ibcon#end of sib2, iclass 11, count 0 2006.285.20:49:46.08#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:49:46.08#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:49:46.08#ibcon#[25=USB\r\n] 2006.285.20:49:46.08#ibcon#*before write, iclass 11, count 0 2006.285.20:49:46.08#ibcon#enter sib2, iclass 11, count 0 2006.285.20:49:46.08#ibcon#flushed, iclass 11, count 0 2006.285.20:49:46.08#ibcon#about to write, iclass 11, count 0 2006.285.20:49:46.08#ibcon#wrote, iclass 11, count 0 2006.285.20:49:46.08#ibcon#about to read 3, iclass 11, count 0 2006.285.20:49:46.11#ibcon#read 3, iclass 11, count 0 2006.285.20:49:46.11#ibcon#about to read 4, iclass 11, count 0 2006.285.20:49:46.11#ibcon#read 4, iclass 11, count 0 2006.285.20:49:46.11#ibcon#about to read 5, iclass 11, count 0 2006.285.20:49:46.11#ibcon#read 5, iclass 11, count 0 2006.285.20:49:46.11#ibcon#about to read 6, iclass 11, count 0 2006.285.20:49:46.11#ibcon#read 6, iclass 11, count 0 2006.285.20:49:46.11#ibcon#end of sib2, iclass 11, count 0 2006.285.20:49:46.11#ibcon#*after write, iclass 11, count 0 2006.285.20:49:46.11#ibcon#*before return 0, iclass 11, count 0 2006.285.20:49:46.11#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:49:46.11#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:49:46.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:49:46.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:49:46.11$vck44/valo=5,734.99 2006.285.20:49:46.11#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.20:49:46.11#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.20:49:46.11#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:46.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:49:46.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:49:46.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:49:46.11#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:49:46.11#ibcon#first serial, iclass 13, count 0 2006.285.20:49:46.11#ibcon#enter sib2, iclass 13, count 0 2006.285.20:49:46.11#ibcon#flushed, iclass 13, count 0 2006.285.20:49:46.11#ibcon#about to write, iclass 13, count 0 2006.285.20:49:46.11#ibcon#wrote, iclass 13, count 0 2006.285.20:49:46.11#ibcon#about to read 3, iclass 13, count 0 2006.285.20:49:46.13#ibcon#read 3, iclass 13, count 0 2006.285.20:49:46.13#ibcon#about to read 4, iclass 13, count 0 2006.285.20:49:46.13#ibcon#read 4, iclass 13, count 0 2006.285.20:49:46.13#ibcon#about to read 5, iclass 13, count 0 2006.285.20:49:46.13#ibcon#read 5, iclass 13, count 0 2006.285.20:49:46.13#ibcon#about to read 6, iclass 13, count 0 2006.285.20:49:46.13#ibcon#read 6, iclass 13, count 0 2006.285.20:49:46.13#ibcon#end of sib2, iclass 13, count 0 2006.285.20:49:46.13#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:49:46.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:49:46.13#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.20:49:46.13#ibcon#*before write, iclass 13, count 0 2006.285.20:49:46.13#ibcon#enter sib2, iclass 13, count 0 2006.285.20:49:46.13#ibcon#flushed, iclass 13, count 0 2006.285.20:49:46.13#ibcon#about to write, iclass 13, count 0 2006.285.20:49:46.13#ibcon#wrote, iclass 13, count 0 2006.285.20:49:46.13#ibcon#about to read 3, iclass 13, count 0 2006.285.20:49:46.17#ibcon#read 3, iclass 13, count 0 2006.285.20:49:46.17#ibcon#about to read 4, iclass 13, count 0 2006.285.20:49:46.17#ibcon#read 4, iclass 13, count 0 2006.285.20:49:46.17#ibcon#about to read 5, iclass 13, count 0 2006.285.20:49:46.17#ibcon#read 5, iclass 13, count 0 2006.285.20:49:46.17#ibcon#about to read 6, iclass 13, count 0 2006.285.20:49:46.17#ibcon#read 6, iclass 13, count 0 2006.285.20:49:46.17#ibcon#end of sib2, iclass 13, count 0 2006.285.20:49:46.17#ibcon#*after write, iclass 13, count 0 2006.285.20:49:46.17#ibcon#*before return 0, iclass 13, count 0 2006.285.20:49:46.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:49:46.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:49:46.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:49:46.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:49:46.17$vck44/va=5,3 2006.285.20:49:46.17#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.20:49:46.17#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.20:49:46.17#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:46.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:49:46.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:49:46.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:49:46.23#ibcon#enter wrdev, iclass 15, count 2 2006.285.20:49:46.23#ibcon#first serial, iclass 15, count 2 2006.285.20:49:46.23#ibcon#enter sib2, iclass 15, count 2 2006.285.20:49:46.23#ibcon#flushed, iclass 15, count 2 2006.285.20:49:46.23#ibcon#about to write, iclass 15, count 2 2006.285.20:49:46.23#ibcon#wrote, iclass 15, count 2 2006.285.20:49:46.23#ibcon#about to read 3, iclass 15, count 2 2006.285.20:49:46.25#ibcon#read 3, iclass 15, count 2 2006.285.20:49:46.25#ibcon#about to read 4, iclass 15, count 2 2006.285.20:49:46.25#ibcon#read 4, iclass 15, count 2 2006.285.20:49:46.25#ibcon#about to read 5, iclass 15, count 2 2006.285.20:49:46.25#ibcon#read 5, iclass 15, count 2 2006.285.20:49:46.25#ibcon#about to read 6, iclass 15, count 2 2006.285.20:49:46.25#ibcon#read 6, iclass 15, count 2 2006.285.20:49:46.25#ibcon#end of sib2, iclass 15, count 2 2006.285.20:49:46.25#ibcon#*mode == 0, iclass 15, count 2 2006.285.20:49:46.25#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.20:49:46.25#ibcon#[25=AT05-03\r\n] 2006.285.20:49:46.25#ibcon#*before write, iclass 15, count 2 2006.285.20:49:46.25#ibcon#enter sib2, iclass 15, count 2 2006.285.20:49:46.25#ibcon#flushed, iclass 15, count 2 2006.285.20:49:46.25#ibcon#about to write, iclass 15, count 2 2006.285.20:49:46.25#ibcon#wrote, iclass 15, count 2 2006.285.20:49:46.25#ibcon#about to read 3, iclass 15, count 2 2006.285.20:49:46.28#ibcon#read 3, iclass 15, count 2 2006.285.20:49:46.28#ibcon#about to read 4, iclass 15, count 2 2006.285.20:49:46.28#ibcon#read 4, iclass 15, count 2 2006.285.20:49:46.28#ibcon#about to read 5, iclass 15, count 2 2006.285.20:49:46.28#ibcon#read 5, iclass 15, count 2 2006.285.20:49:46.28#ibcon#about to read 6, iclass 15, count 2 2006.285.20:49:46.28#ibcon#read 6, iclass 15, count 2 2006.285.20:49:46.28#ibcon#end of sib2, iclass 15, count 2 2006.285.20:49:46.28#ibcon#*after write, iclass 15, count 2 2006.285.20:49:46.28#ibcon#*before return 0, iclass 15, count 2 2006.285.20:49:46.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:49:46.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:49:46.28#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.20:49:46.28#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:46.28#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:49:46.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:49:46.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:49:46.40#ibcon#enter wrdev, iclass 15, count 0 2006.285.20:49:46.40#ibcon#first serial, iclass 15, count 0 2006.285.20:49:46.40#ibcon#enter sib2, iclass 15, count 0 2006.285.20:49:46.40#ibcon#flushed, iclass 15, count 0 2006.285.20:49:46.40#ibcon#about to write, iclass 15, count 0 2006.285.20:49:46.40#ibcon#wrote, iclass 15, count 0 2006.285.20:49:46.40#ibcon#about to read 3, iclass 15, count 0 2006.285.20:49:46.42#ibcon#read 3, iclass 15, count 0 2006.285.20:49:46.42#ibcon#about to read 4, iclass 15, count 0 2006.285.20:49:46.42#ibcon#read 4, iclass 15, count 0 2006.285.20:49:46.42#ibcon#about to read 5, iclass 15, count 0 2006.285.20:49:46.42#ibcon#read 5, iclass 15, count 0 2006.285.20:49:46.42#ibcon#about to read 6, iclass 15, count 0 2006.285.20:49:46.42#ibcon#read 6, iclass 15, count 0 2006.285.20:49:46.42#ibcon#end of sib2, iclass 15, count 0 2006.285.20:49:46.42#ibcon#*mode == 0, iclass 15, count 0 2006.285.20:49:46.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.20:49:46.42#ibcon#[25=USB\r\n] 2006.285.20:49:46.42#ibcon#*before write, iclass 15, count 0 2006.285.20:49:46.42#ibcon#enter sib2, iclass 15, count 0 2006.285.20:49:46.42#ibcon#flushed, iclass 15, count 0 2006.285.20:49:46.42#ibcon#about to write, iclass 15, count 0 2006.285.20:49:46.42#ibcon#wrote, iclass 15, count 0 2006.285.20:49:46.42#ibcon#about to read 3, iclass 15, count 0 2006.285.20:49:46.45#ibcon#read 3, iclass 15, count 0 2006.285.20:49:46.45#ibcon#about to read 4, iclass 15, count 0 2006.285.20:49:46.45#ibcon#read 4, iclass 15, count 0 2006.285.20:49:46.45#ibcon#about to read 5, iclass 15, count 0 2006.285.20:49:46.45#ibcon#read 5, iclass 15, count 0 2006.285.20:49:46.45#ibcon#about to read 6, iclass 15, count 0 2006.285.20:49:46.45#ibcon#read 6, iclass 15, count 0 2006.285.20:49:46.45#ibcon#end of sib2, iclass 15, count 0 2006.285.20:49:46.45#ibcon#*after write, iclass 15, count 0 2006.285.20:49:46.45#ibcon#*before return 0, iclass 15, count 0 2006.285.20:49:46.45#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:49:46.45#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:49:46.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.20:49:46.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.20:49:46.45$vck44/valo=6,814.99 2006.285.20:49:46.45#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.20:49:46.45#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.20:49:46.45#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:46.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:49:46.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:49:46.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:49:46.45#ibcon#enter wrdev, iclass 17, count 0 2006.285.20:49:46.45#ibcon#first serial, iclass 17, count 0 2006.285.20:49:46.45#ibcon#enter sib2, iclass 17, count 0 2006.285.20:49:46.45#ibcon#flushed, iclass 17, count 0 2006.285.20:49:46.45#ibcon#about to write, iclass 17, count 0 2006.285.20:49:46.45#ibcon#wrote, iclass 17, count 0 2006.285.20:49:46.45#ibcon#about to read 3, iclass 17, count 0 2006.285.20:49:46.47#ibcon#read 3, iclass 17, count 0 2006.285.20:49:46.47#ibcon#about to read 4, iclass 17, count 0 2006.285.20:49:46.47#ibcon#read 4, iclass 17, count 0 2006.285.20:49:46.47#ibcon#about to read 5, iclass 17, count 0 2006.285.20:49:46.47#ibcon#read 5, iclass 17, count 0 2006.285.20:49:46.47#ibcon#about to read 6, iclass 17, count 0 2006.285.20:49:46.47#ibcon#read 6, iclass 17, count 0 2006.285.20:49:46.47#ibcon#end of sib2, iclass 17, count 0 2006.285.20:49:46.47#ibcon#*mode == 0, iclass 17, count 0 2006.285.20:49:46.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.20:49:46.47#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.20:49:46.47#ibcon#*before write, iclass 17, count 0 2006.285.20:49:46.47#ibcon#enter sib2, iclass 17, count 0 2006.285.20:49:46.47#ibcon#flushed, iclass 17, count 0 2006.285.20:49:46.47#ibcon#about to write, iclass 17, count 0 2006.285.20:49:46.47#ibcon#wrote, iclass 17, count 0 2006.285.20:49:46.47#ibcon#about to read 3, iclass 17, count 0 2006.285.20:49:46.51#ibcon#read 3, iclass 17, count 0 2006.285.20:49:46.51#ibcon#about to read 4, iclass 17, count 0 2006.285.20:49:46.51#ibcon#read 4, iclass 17, count 0 2006.285.20:49:46.51#ibcon#about to read 5, iclass 17, count 0 2006.285.20:49:46.51#ibcon#read 5, iclass 17, count 0 2006.285.20:49:46.51#ibcon#about to read 6, iclass 17, count 0 2006.285.20:49:46.51#ibcon#read 6, iclass 17, count 0 2006.285.20:49:46.51#ibcon#end of sib2, iclass 17, count 0 2006.285.20:49:46.51#ibcon#*after write, iclass 17, count 0 2006.285.20:49:46.51#ibcon#*before return 0, iclass 17, count 0 2006.285.20:49:46.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:49:46.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:49:46.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.20:49:46.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.20:49:46.51$vck44/va=6,4 2006.285.20:49:46.51#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.20:49:46.51#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.20:49:46.51#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:46.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:49:46.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:49:46.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:49:46.57#ibcon#enter wrdev, iclass 19, count 2 2006.285.20:49:46.57#ibcon#first serial, iclass 19, count 2 2006.285.20:49:46.57#ibcon#enter sib2, iclass 19, count 2 2006.285.20:49:46.57#ibcon#flushed, iclass 19, count 2 2006.285.20:49:46.57#ibcon#about to write, iclass 19, count 2 2006.285.20:49:46.57#ibcon#wrote, iclass 19, count 2 2006.285.20:49:46.57#ibcon#about to read 3, iclass 19, count 2 2006.285.20:49:46.59#ibcon#read 3, iclass 19, count 2 2006.285.20:49:46.59#ibcon#about to read 4, iclass 19, count 2 2006.285.20:49:46.59#ibcon#read 4, iclass 19, count 2 2006.285.20:49:46.59#ibcon#about to read 5, iclass 19, count 2 2006.285.20:49:46.59#ibcon#read 5, iclass 19, count 2 2006.285.20:49:46.59#ibcon#about to read 6, iclass 19, count 2 2006.285.20:49:46.59#ibcon#read 6, iclass 19, count 2 2006.285.20:49:46.59#ibcon#end of sib2, iclass 19, count 2 2006.285.20:49:46.59#ibcon#*mode == 0, iclass 19, count 2 2006.285.20:49:46.59#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.20:49:46.59#ibcon#[25=AT06-04\r\n] 2006.285.20:49:46.59#ibcon#*before write, iclass 19, count 2 2006.285.20:49:46.59#ibcon#enter sib2, iclass 19, count 2 2006.285.20:49:46.59#ibcon#flushed, iclass 19, count 2 2006.285.20:49:46.59#ibcon#about to write, iclass 19, count 2 2006.285.20:49:46.59#ibcon#wrote, iclass 19, count 2 2006.285.20:49:46.59#ibcon#about to read 3, iclass 19, count 2 2006.285.20:49:46.62#ibcon#read 3, iclass 19, count 2 2006.285.20:49:46.62#ibcon#about to read 4, iclass 19, count 2 2006.285.20:49:46.62#ibcon#read 4, iclass 19, count 2 2006.285.20:49:46.62#ibcon#about to read 5, iclass 19, count 2 2006.285.20:49:46.62#ibcon#read 5, iclass 19, count 2 2006.285.20:49:46.62#ibcon#about to read 6, iclass 19, count 2 2006.285.20:49:46.62#ibcon#read 6, iclass 19, count 2 2006.285.20:49:46.62#ibcon#end of sib2, iclass 19, count 2 2006.285.20:49:46.62#ibcon#*after write, iclass 19, count 2 2006.285.20:49:46.62#ibcon#*before return 0, iclass 19, count 2 2006.285.20:49:46.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:49:46.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:49:46.62#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.20:49:46.62#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:46.62#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:49:46.74#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:49:46.74#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:49:46.74#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:49:46.74#ibcon#first serial, iclass 19, count 0 2006.285.20:49:46.74#ibcon#enter sib2, iclass 19, count 0 2006.285.20:49:46.74#ibcon#flushed, iclass 19, count 0 2006.285.20:49:46.74#ibcon#about to write, iclass 19, count 0 2006.285.20:49:46.74#ibcon#wrote, iclass 19, count 0 2006.285.20:49:46.74#ibcon#about to read 3, iclass 19, count 0 2006.285.20:49:46.76#ibcon#read 3, iclass 19, count 0 2006.285.20:49:46.76#ibcon#about to read 4, iclass 19, count 0 2006.285.20:49:46.76#ibcon#read 4, iclass 19, count 0 2006.285.20:49:46.76#ibcon#about to read 5, iclass 19, count 0 2006.285.20:49:46.76#ibcon#read 5, iclass 19, count 0 2006.285.20:49:46.76#ibcon#about to read 6, iclass 19, count 0 2006.285.20:49:46.76#ibcon#read 6, iclass 19, count 0 2006.285.20:49:46.76#ibcon#end of sib2, iclass 19, count 0 2006.285.20:49:46.76#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:49:46.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:49:46.76#ibcon#[25=USB\r\n] 2006.285.20:49:46.76#ibcon#*before write, iclass 19, count 0 2006.285.20:49:46.76#ibcon#enter sib2, iclass 19, count 0 2006.285.20:49:46.76#ibcon#flushed, iclass 19, count 0 2006.285.20:49:46.76#ibcon#about to write, iclass 19, count 0 2006.285.20:49:46.76#ibcon#wrote, iclass 19, count 0 2006.285.20:49:46.76#ibcon#about to read 3, iclass 19, count 0 2006.285.20:49:46.79#ibcon#read 3, iclass 19, count 0 2006.285.20:49:46.79#ibcon#about to read 4, iclass 19, count 0 2006.285.20:49:46.79#ibcon#read 4, iclass 19, count 0 2006.285.20:49:46.79#ibcon#about to read 5, iclass 19, count 0 2006.285.20:49:46.79#ibcon#read 5, iclass 19, count 0 2006.285.20:49:46.79#ibcon#about to read 6, iclass 19, count 0 2006.285.20:49:46.79#ibcon#read 6, iclass 19, count 0 2006.285.20:49:46.79#ibcon#end of sib2, iclass 19, count 0 2006.285.20:49:46.79#ibcon#*after write, iclass 19, count 0 2006.285.20:49:46.79#ibcon#*before return 0, iclass 19, count 0 2006.285.20:49:46.79#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:49:46.79#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:49:46.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:49:46.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:49:46.79$vck44/valo=7,864.99 2006.285.20:49:46.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.20:49:46.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.20:49:46.79#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:46.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:49:46.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:49:46.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:49:46.79#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:49:46.79#ibcon#first serial, iclass 21, count 0 2006.285.20:49:46.79#ibcon#enter sib2, iclass 21, count 0 2006.285.20:49:46.79#ibcon#flushed, iclass 21, count 0 2006.285.20:49:46.79#ibcon#about to write, iclass 21, count 0 2006.285.20:49:46.79#ibcon#wrote, iclass 21, count 0 2006.285.20:49:46.79#ibcon#about to read 3, iclass 21, count 0 2006.285.20:49:46.81#ibcon#read 3, iclass 21, count 0 2006.285.20:49:46.89#ibcon#about to read 4, iclass 21, count 0 2006.285.20:49:46.89#ibcon#read 4, iclass 21, count 0 2006.285.20:49:46.89#ibcon#about to read 5, iclass 21, count 0 2006.285.20:49:46.89#ibcon#read 5, iclass 21, count 0 2006.285.20:49:46.89#ibcon#about to read 6, iclass 21, count 0 2006.285.20:49:46.89#ibcon#read 6, iclass 21, count 0 2006.285.20:49:46.89#ibcon#end of sib2, iclass 21, count 0 2006.285.20:49:46.89#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:49:46.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:49:46.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.20:49:46.89#ibcon#*before write, iclass 21, count 0 2006.285.20:49:46.89#ibcon#enter sib2, iclass 21, count 0 2006.285.20:49:46.89#ibcon#flushed, iclass 21, count 0 2006.285.20:49:46.89#ibcon#about to write, iclass 21, count 0 2006.285.20:49:46.89#ibcon#wrote, iclass 21, count 0 2006.285.20:49:46.89#ibcon#about to read 3, iclass 21, count 0 2006.285.20:49:46.92#ibcon#read 3, iclass 21, count 0 2006.285.20:49:46.92#ibcon#about to read 4, iclass 21, count 0 2006.285.20:49:46.92#ibcon#read 4, iclass 21, count 0 2006.285.20:49:46.92#ibcon#about to read 5, iclass 21, count 0 2006.285.20:49:46.92#ibcon#read 5, iclass 21, count 0 2006.285.20:49:46.92#ibcon#about to read 6, iclass 21, count 0 2006.285.20:49:46.92#ibcon#read 6, iclass 21, count 0 2006.285.20:49:46.92#ibcon#end of sib2, iclass 21, count 0 2006.285.20:49:46.92#ibcon#*after write, iclass 21, count 0 2006.285.20:49:46.92#ibcon#*before return 0, iclass 21, count 0 2006.285.20:49:46.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:49:46.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.20:49:46.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:49:46.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:49:46.92$vck44/va=7,4 2006.285.20:49:46.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.20:49:46.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.20:49:46.92#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:46.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:49:46.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:49:46.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:49:46.92#ibcon#enter wrdev, iclass 23, count 2 2006.285.20:49:46.92#ibcon#first serial, iclass 23, count 2 2006.285.20:49:46.92#ibcon#enter sib2, iclass 23, count 2 2006.285.20:49:46.92#ibcon#flushed, iclass 23, count 2 2006.285.20:49:46.92#ibcon#about to write, iclass 23, count 2 2006.285.20:49:46.92#ibcon#wrote, iclass 23, count 2 2006.285.20:49:46.92#ibcon#about to read 3, iclass 23, count 2 2006.285.20:49:46.94#ibcon#read 3, iclass 23, count 2 2006.285.20:49:46.94#ibcon#about to read 4, iclass 23, count 2 2006.285.20:49:46.94#ibcon#read 4, iclass 23, count 2 2006.285.20:49:46.94#ibcon#about to read 5, iclass 23, count 2 2006.285.20:49:46.94#ibcon#read 5, iclass 23, count 2 2006.285.20:49:46.94#ibcon#about to read 6, iclass 23, count 2 2006.285.20:49:46.94#ibcon#read 6, iclass 23, count 2 2006.285.20:49:46.94#ibcon#end of sib2, iclass 23, count 2 2006.285.20:49:46.94#ibcon#*mode == 0, iclass 23, count 2 2006.285.20:49:46.94#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.20:49:46.94#ibcon#[25=AT07-04\r\n] 2006.285.20:49:46.94#ibcon#*before write, iclass 23, count 2 2006.285.20:49:46.94#ibcon#enter sib2, iclass 23, count 2 2006.285.20:49:46.94#ibcon#flushed, iclass 23, count 2 2006.285.20:49:46.94#ibcon#about to write, iclass 23, count 2 2006.285.20:49:46.94#ibcon#wrote, iclass 23, count 2 2006.285.20:49:46.94#ibcon#about to read 3, iclass 23, count 2 2006.285.20:49:46.97#ibcon#read 3, iclass 23, count 2 2006.285.20:49:46.97#ibcon#about to read 4, iclass 23, count 2 2006.285.20:49:46.97#ibcon#read 4, iclass 23, count 2 2006.285.20:49:46.97#ibcon#about to read 5, iclass 23, count 2 2006.285.20:49:46.97#ibcon#read 5, iclass 23, count 2 2006.285.20:49:46.97#ibcon#about to read 6, iclass 23, count 2 2006.285.20:49:46.97#ibcon#read 6, iclass 23, count 2 2006.285.20:49:46.97#ibcon#end of sib2, iclass 23, count 2 2006.285.20:49:46.97#ibcon#*after write, iclass 23, count 2 2006.285.20:49:46.97#ibcon#*before return 0, iclass 23, count 2 2006.285.20:49:46.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:49:46.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.20:49:46.97#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.20:49:46.97#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:46.97#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:49:47.09#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:49:47.09#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:49:47.09#ibcon#enter wrdev, iclass 23, count 0 2006.285.20:49:47.09#ibcon#first serial, iclass 23, count 0 2006.285.20:49:47.09#ibcon#enter sib2, iclass 23, count 0 2006.285.20:49:47.09#ibcon#flushed, iclass 23, count 0 2006.285.20:49:47.09#ibcon#about to write, iclass 23, count 0 2006.285.20:49:47.09#ibcon#wrote, iclass 23, count 0 2006.285.20:49:47.09#ibcon#about to read 3, iclass 23, count 0 2006.285.20:49:47.11#ibcon#read 3, iclass 23, count 0 2006.285.20:49:47.11#ibcon#about to read 4, iclass 23, count 0 2006.285.20:49:47.11#ibcon#read 4, iclass 23, count 0 2006.285.20:49:47.11#ibcon#about to read 5, iclass 23, count 0 2006.285.20:49:47.11#ibcon#read 5, iclass 23, count 0 2006.285.20:49:47.11#ibcon#about to read 6, iclass 23, count 0 2006.285.20:49:47.11#ibcon#read 6, iclass 23, count 0 2006.285.20:49:47.11#ibcon#end of sib2, iclass 23, count 0 2006.285.20:49:47.11#ibcon#*mode == 0, iclass 23, count 0 2006.285.20:49:47.11#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.20:49:47.11#ibcon#[25=USB\r\n] 2006.285.20:49:47.11#ibcon#*before write, iclass 23, count 0 2006.285.20:49:47.11#ibcon#enter sib2, iclass 23, count 0 2006.285.20:49:47.11#ibcon#flushed, iclass 23, count 0 2006.285.20:49:47.11#ibcon#about to write, iclass 23, count 0 2006.285.20:49:47.11#ibcon#wrote, iclass 23, count 0 2006.285.20:49:47.11#ibcon#about to read 3, iclass 23, count 0 2006.285.20:49:47.14#ibcon#read 3, iclass 23, count 0 2006.285.20:49:47.14#ibcon#about to read 4, iclass 23, count 0 2006.285.20:49:47.14#ibcon#read 4, iclass 23, count 0 2006.285.20:49:47.14#ibcon#about to read 5, iclass 23, count 0 2006.285.20:49:47.14#ibcon#read 5, iclass 23, count 0 2006.285.20:49:47.14#ibcon#about to read 6, iclass 23, count 0 2006.285.20:49:47.14#ibcon#read 6, iclass 23, count 0 2006.285.20:49:47.14#ibcon#end of sib2, iclass 23, count 0 2006.285.20:49:47.14#ibcon#*after write, iclass 23, count 0 2006.285.20:49:47.14#ibcon#*before return 0, iclass 23, count 0 2006.285.20:49:47.14#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:49:47.14#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.20:49:47.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.20:49:47.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.20:49:47.14$vck44/valo=8,884.99 2006.285.20:49:47.14#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.20:49:47.14#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.20:49:47.14#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:47.14#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:49:47.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:49:47.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:49:47.14#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:49:47.14#ibcon#first serial, iclass 25, count 0 2006.285.20:49:47.14#ibcon#enter sib2, iclass 25, count 0 2006.285.20:49:47.14#ibcon#flushed, iclass 25, count 0 2006.285.20:49:47.14#ibcon#about to write, iclass 25, count 0 2006.285.20:49:47.14#ibcon#wrote, iclass 25, count 0 2006.285.20:49:47.14#ibcon#about to read 3, iclass 25, count 0 2006.285.20:49:47.16#ibcon#read 3, iclass 25, count 0 2006.285.20:49:47.16#ibcon#about to read 4, iclass 25, count 0 2006.285.20:49:47.16#ibcon#read 4, iclass 25, count 0 2006.285.20:49:47.16#ibcon#about to read 5, iclass 25, count 0 2006.285.20:49:47.16#ibcon#read 5, iclass 25, count 0 2006.285.20:49:47.16#ibcon#about to read 6, iclass 25, count 0 2006.285.20:49:47.16#ibcon#read 6, iclass 25, count 0 2006.285.20:49:47.16#ibcon#end of sib2, iclass 25, count 0 2006.285.20:49:47.16#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:49:47.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:49:47.16#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.20:49:47.16#ibcon#*before write, iclass 25, count 0 2006.285.20:49:47.16#ibcon#enter sib2, iclass 25, count 0 2006.285.20:49:47.16#ibcon#flushed, iclass 25, count 0 2006.285.20:49:47.16#ibcon#about to write, iclass 25, count 0 2006.285.20:49:47.16#ibcon#wrote, iclass 25, count 0 2006.285.20:49:47.16#ibcon#about to read 3, iclass 25, count 0 2006.285.20:49:47.20#ibcon#read 3, iclass 25, count 0 2006.285.20:49:47.20#ibcon#about to read 4, iclass 25, count 0 2006.285.20:49:47.20#ibcon#read 4, iclass 25, count 0 2006.285.20:49:47.20#ibcon#about to read 5, iclass 25, count 0 2006.285.20:49:47.20#ibcon#read 5, iclass 25, count 0 2006.285.20:49:47.20#ibcon#about to read 6, iclass 25, count 0 2006.285.20:49:47.20#ibcon#read 6, iclass 25, count 0 2006.285.20:49:47.20#ibcon#end of sib2, iclass 25, count 0 2006.285.20:49:47.20#ibcon#*after write, iclass 25, count 0 2006.285.20:49:47.20#ibcon#*before return 0, iclass 25, count 0 2006.285.20:49:47.20#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:49:47.20#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:49:47.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:49:47.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:49:47.20$vck44/va=8,3 2006.285.20:49:47.20#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.20:49:47.20#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.20:49:47.20#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:47.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:49:47.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:49:47.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:49:47.26#ibcon#enter wrdev, iclass 27, count 2 2006.285.20:49:47.26#ibcon#first serial, iclass 27, count 2 2006.285.20:49:47.26#ibcon#enter sib2, iclass 27, count 2 2006.285.20:49:47.26#ibcon#flushed, iclass 27, count 2 2006.285.20:49:47.26#ibcon#about to write, iclass 27, count 2 2006.285.20:49:47.26#ibcon#wrote, iclass 27, count 2 2006.285.20:49:47.26#ibcon#about to read 3, iclass 27, count 2 2006.285.20:49:47.28#ibcon#read 3, iclass 27, count 2 2006.285.20:49:47.28#ibcon#about to read 4, iclass 27, count 2 2006.285.20:49:47.28#ibcon#read 4, iclass 27, count 2 2006.285.20:49:47.28#ibcon#about to read 5, iclass 27, count 2 2006.285.20:49:47.28#ibcon#read 5, iclass 27, count 2 2006.285.20:49:47.28#ibcon#about to read 6, iclass 27, count 2 2006.285.20:49:47.28#ibcon#read 6, iclass 27, count 2 2006.285.20:49:47.28#ibcon#end of sib2, iclass 27, count 2 2006.285.20:49:47.28#ibcon#*mode == 0, iclass 27, count 2 2006.285.20:49:47.28#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.20:49:47.28#ibcon#[25=AT08-03\r\n] 2006.285.20:49:47.28#ibcon#*before write, iclass 27, count 2 2006.285.20:49:47.28#ibcon#enter sib2, iclass 27, count 2 2006.285.20:49:47.28#ibcon#flushed, iclass 27, count 2 2006.285.20:49:47.28#ibcon#about to write, iclass 27, count 2 2006.285.20:49:47.28#ibcon#wrote, iclass 27, count 2 2006.285.20:49:47.28#ibcon#about to read 3, iclass 27, count 2 2006.285.20:49:47.31#ibcon#read 3, iclass 27, count 2 2006.285.20:49:47.31#ibcon#about to read 4, iclass 27, count 2 2006.285.20:49:47.31#ibcon#read 4, iclass 27, count 2 2006.285.20:49:47.31#ibcon#about to read 5, iclass 27, count 2 2006.285.20:49:47.31#ibcon#read 5, iclass 27, count 2 2006.285.20:49:47.31#ibcon#about to read 6, iclass 27, count 2 2006.285.20:49:47.31#ibcon#read 6, iclass 27, count 2 2006.285.20:49:47.31#ibcon#end of sib2, iclass 27, count 2 2006.285.20:49:47.31#ibcon#*after write, iclass 27, count 2 2006.285.20:49:47.31#ibcon#*before return 0, iclass 27, count 2 2006.285.20:49:47.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:49:47.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:49:47.31#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.20:49:47.31#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:47.31#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:49:47.43#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:49:47.43#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:49:47.43#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:49:47.43#ibcon#first serial, iclass 27, count 0 2006.285.20:49:47.43#ibcon#enter sib2, iclass 27, count 0 2006.285.20:49:47.43#ibcon#flushed, iclass 27, count 0 2006.285.20:49:47.43#ibcon#about to write, iclass 27, count 0 2006.285.20:49:47.43#ibcon#wrote, iclass 27, count 0 2006.285.20:49:47.43#ibcon#about to read 3, iclass 27, count 0 2006.285.20:49:47.45#ibcon#read 3, iclass 27, count 0 2006.285.20:49:47.45#ibcon#about to read 4, iclass 27, count 0 2006.285.20:49:47.45#ibcon#read 4, iclass 27, count 0 2006.285.20:49:47.45#ibcon#about to read 5, iclass 27, count 0 2006.285.20:49:47.45#ibcon#read 5, iclass 27, count 0 2006.285.20:49:47.45#ibcon#about to read 6, iclass 27, count 0 2006.285.20:49:47.45#ibcon#read 6, iclass 27, count 0 2006.285.20:49:47.45#ibcon#end of sib2, iclass 27, count 0 2006.285.20:49:47.45#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:49:47.45#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:49:47.45#ibcon#[25=USB\r\n] 2006.285.20:49:47.45#ibcon#*before write, iclass 27, count 0 2006.285.20:49:47.45#ibcon#enter sib2, iclass 27, count 0 2006.285.20:49:47.45#ibcon#flushed, iclass 27, count 0 2006.285.20:49:47.45#ibcon#about to write, iclass 27, count 0 2006.285.20:49:47.45#ibcon#wrote, iclass 27, count 0 2006.285.20:49:47.45#ibcon#about to read 3, iclass 27, count 0 2006.285.20:49:47.48#ibcon#read 3, iclass 27, count 0 2006.285.20:49:47.48#ibcon#about to read 4, iclass 27, count 0 2006.285.20:49:47.48#ibcon#read 4, iclass 27, count 0 2006.285.20:49:47.48#ibcon#about to read 5, iclass 27, count 0 2006.285.20:49:47.48#ibcon#read 5, iclass 27, count 0 2006.285.20:49:47.48#ibcon#about to read 6, iclass 27, count 0 2006.285.20:49:47.48#ibcon#read 6, iclass 27, count 0 2006.285.20:49:47.48#ibcon#end of sib2, iclass 27, count 0 2006.285.20:49:47.48#ibcon#*after write, iclass 27, count 0 2006.285.20:49:47.48#ibcon#*before return 0, iclass 27, count 0 2006.285.20:49:47.48#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:49:47.48#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:49:47.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:49:47.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:49:47.48$vck44/vblo=1,629.99 2006.285.20:49:47.48#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.20:49:47.48#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.20:49:47.48#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:47.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:49:47.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:49:47.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:49:47.48#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:49:47.48#ibcon#first serial, iclass 29, count 0 2006.285.20:49:47.48#ibcon#enter sib2, iclass 29, count 0 2006.285.20:49:47.48#ibcon#flushed, iclass 29, count 0 2006.285.20:49:47.48#ibcon#about to write, iclass 29, count 0 2006.285.20:49:47.48#ibcon#wrote, iclass 29, count 0 2006.285.20:49:47.48#ibcon#about to read 3, iclass 29, count 0 2006.285.20:49:47.50#ibcon#read 3, iclass 29, count 0 2006.285.20:49:47.50#ibcon#about to read 4, iclass 29, count 0 2006.285.20:49:47.50#ibcon#read 4, iclass 29, count 0 2006.285.20:49:47.50#ibcon#about to read 5, iclass 29, count 0 2006.285.20:49:47.50#ibcon#read 5, iclass 29, count 0 2006.285.20:49:47.50#ibcon#about to read 6, iclass 29, count 0 2006.285.20:49:47.50#ibcon#read 6, iclass 29, count 0 2006.285.20:49:47.50#ibcon#end of sib2, iclass 29, count 0 2006.285.20:49:47.50#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:49:47.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:49:47.50#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.20:49:47.50#ibcon#*before write, iclass 29, count 0 2006.285.20:49:47.50#ibcon#enter sib2, iclass 29, count 0 2006.285.20:49:47.50#ibcon#flushed, iclass 29, count 0 2006.285.20:49:47.50#ibcon#about to write, iclass 29, count 0 2006.285.20:49:47.50#ibcon#wrote, iclass 29, count 0 2006.285.20:49:47.50#ibcon#about to read 3, iclass 29, count 0 2006.285.20:49:47.54#ibcon#read 3, iclass 29, count 0 2006.285.20:49:47.54#ibcon#about to read 4, iclass 29, count 0 2006.285.20:49:47.54#ibcon#read 4, iclass 29, count 0 2006.285.20:49:47.54#ibcon#about to read 5, iclass 29, count 0 2006.285.20:49:47.54#ibcon#read 5, iclass 29, count 0 2006.285.20:49:47.54#ibcon#about to read 6, iclass 29, count 0 2006.285.20:49:47.54#ibcon#read 6, iclass 29, count 0 2006.285.20:49:47.54#ibcon#end of sib2, iclass 29, count 0 2006.285.20:49:47.54#ibcon#*after write, iclass 29, count 0 2006.285.20:49:47.54#ibcon#*before return 0, iclass 29, count 0 2006.285.20:49:47.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:49:47.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:49:47.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:49:47.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:49:47.54$vck44/vb=1,4 2006.285.20:49:47.54#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.20:49:47.54#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.20:49:47.54#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:47.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:49:47.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:49:47.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:49:47.54#ibcon#enter wrdev, iclass 31, count 2 2006.285.20:49:47.54#ibcon#first serial, iclass 31, count 2 2006.285.20:49:47.54#ibcon#enter sib2, iclass 31, count 2 2006.285.20:49:47.54#ibcon#flushed, iclass 31, count 2 2006.285.20:49:47.54#ibcon#about to write, iclass 31, count 2 2006.285.20:49:47.54#ibcon#wrote, iclass 31, count 2 2006.285.20:49:47.54#ibcon#about to read 3, iclass 31, count 2 2006.285.20:49:47.56#ibcon#read 3, iclass 31, count 2 2006.285.20:49:47.56#ibcon#about to read 4, iclass 31, count 2 2006.285.20:49:47.56#ibcon#read 4, iclass 31, count 2 2006.285.20:49:47.56#ibcon#about to read 5, iclass 31, count 2 2006.285.20:49:47.56#ibcon#read 5, iclass 31, count 2 2006.285.20:49:47.56#ibcon#about to read 6, iclass 31, count 2 2006.285.20:49:47.56#ibcon#read 6, iclass 31, count 2 2006.285.20:49:47.56#ibcon#end of sib2, iclass 31, count 2 2006.285.20:49:47.56#ibcon#*mode == 0, iclass 31, count 2 2006.285.20:49:47.56#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.20:49:47.56#ibcon#[27=AT01-04\r\n] 2006.285.20:49:47.56#ibcon#*before write, iclass 31, count 2 2006.285.20:49:47.56#ibcon#enter sib2, iclass 31, count 2 2006.285.20:49:47.56#ibcon#flushed, iclass 31, count 2 2006.285.20:49:47.56#ibcon#about to write, iclass 31, count 2 2006.285.20:49:47.56#ibcon#wrote, iclass 31, count 2 2006.285.20:49:47.56#ibcon#about to read 3, iclass 31, count 2 2006.285.20:49:47.59#ibcon#read 3, iclass 31, count 2 2006.285.20:49:47.59#ibcon#about to read 4, iclass 31, count 2 2006.285.20:49:47.59#ibcon#read 4, iclass 31, count 2 2006.285.20:49:47.59#ibcon#about to read 5, iclass 31, count 2 2006.285.20:49:47.59#ibcon#read 5, iclass 31, count 2 2006.285.20:49:47.59#ibcon#about to read 6, iclass 31, count 2 2006.285.20:49:47.59#ibcon#read 6, iclass 31, count 2 2006.285.20:49:47.59#ibcon#end of sib2, iclass 31, count 2 2006.285.20:49:47.59#ibcon#*after write, iclass 31, count 2 2006.285.20:49:47.59#ibcon#*before return 0, iclass 31, count 2 2006.285.20:49:47.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:49:47.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.20:49:47.59#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.20:49:47.59#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:47.59#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:49:47.71#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:49:47.71#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:49:47.71#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:49:47.71#ibcon#first serial, iclass 31, count 0 2006.285.20:49:47.71#ibcon#enter sib2, iclass 31, count 0 2006.285.20:49:47.71#ibcon#flushed, iclass 31, count 0 2006.285.20:49:47.71#ibcon#about to write, iclass 31, count 0 2006.285.20:49:47.71#ibcon#wrote, iclass 31, count 0 2006.285.20:49:47.71#ibcon#about to read 3, iclass 31, count 0 2006.285.20:49:47.73#ibcon#read 3, iclass 31, count 0 2006.285.20:49:47.73#ibcon#about to read 4, iclass 31, count 0 2006.285.20:49:47.73#ibcon#read 4, iclass 31, count 0 2006.285.20:49:47.73#ibcon#about to read 5, iclass 31, count 0 2006.285.20:49:47.73#ibcon#read 5, iclass 31, count 0 2006.285.20:49:47.73#ibcon#about to read 6, iclass 31, count 0 2006.285.20:49:47.73#ibcon#read 6, iclass 31, count 0 2006.285.20:49:47.73#ibcon#end of sib2, iclass 31, count 0 2006.285.20:49:47.73#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:49:47.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:49:47.73#ibcon#[27=USB\r\n] 2006.285.20:49:47.73#ibcon#*before write, iclass 31, count 0 2006.285.20:49:47.73#ibcon#enter sib2, iclass 31, count 0 2006.285.20:49:47.73#ibcon#flushed, iclass 31, count 0 2006.285.20:49:47.73#ibcon#about to write, iclass 31, count 0 2006.285.20:49:47.73#ibcon#wrote, iclass 31, count 0 2006.285.20:49:47.73#ibcon#about to read 3, iclass 31, count 0 2006.285.20:49:47.76#ibcon#read 3, iclass 31, count 0 2006.285.20:49:47.76#ibcon#about to read 4, iclass 31, count 0 2006.285.20:49:47.76#ibcon#read 4, iclass 31, count 0 2006.285.20:49:47.76#ibcon#about to read 5, iclass 31, count 0 2006.285.20:49:47.76#ibcon#read 5, iclass 31, count 0 2006.285.20:49:47.76#ibcon#about to read 6, iclass 31, count 0 2006.285.20:49:47.76#ibcon#read 6, iclass 31, count 0 2006.285.20:49:47.76#ibcon#end of sib2, iclass 31, count 0 2006.285.20:49:47.76#ibcon#*after write, iclass 31, count 0 2006.285.20:49:47.76#ibcon#*before return 0, iclass 31, count 0 2006.285.20:49:47.76#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:49:47.76#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.20:49:47.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:49:47.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:49:47.76$vck44/vblo=2,634.99 2006.285.20:49:47.76#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.20:49:47.76#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.20:49:47.76#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:47.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:49:47.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:49:47.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:49:47.76#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:49:47.76#ibcon#first serial, iclass 33, count 0 2006.285.20:49:47.76#ibcon#enter sib2, iclass 33, count 0 2006.285.20:49:47.76#ibcon#flushed, iclass 33, count 0 2006.285.20:49:47.76#ibcon#about to write, iclass 33, count 0 2006.285.20:49:47.76#ibcon#wrote, iclass 33, count 0 2006.285.20:49:47.76#ibcon#about to read 3, iclass 33, count 0 2006.285.20:49:47.78#ibcon#read 3, iclass 33, count 0 2006.285.20:49:47.86#ibcon#about to read 4, iclass 33, count 0 2006.285.20:49:47.86#ibcon#read 4, iclass 33, count 0 2006.285.20:49:47.86#ibcon#about to read 5, iclass 33, count 0 2006.285.20:49:47.86#ibcon#read 5, iclass 33, count 0 2006.285.20:49:47.86#ibcon#about to read 6, iclass 33, count 0 2006.285.20:49:47.86#ibcon#read 6, iclass 33, count 0 2006.285.20:49:47.86#ibcon#end of sib2, iclass 33, count 0 2006.285.20:49:47.86#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:49:47.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:49:47.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.20:49:47.86#ibcon#*before write, iclass 33, count 0 2006.285.20:49:47.86#ibcon#enter sib2, iclass 33, count 0 2006.285.20:49:47.86#ibcon#flushed, iclass 33, count 0 2006.285.20:49:47.86#ibcon#about to write, iclass 33, count 0 2006.285.20:49:47.86#ibcon#wrote, iclass 33, count 0 2006.285.20:49:47.86#ibcon#about to read 3, iclass 33, count 0 2006.285.20:49:47.89#ibcon#read 3, iclass 33, count 0 2006.285.20:49:47.89#ibcon#about to read 4, iclass 33, count 0 2006.285.20:49:47.89#ibcon#read 4, iclass 33, count 0 2006.285.20:49:47.89#ibcon#about to read 5, iclass 33, count 0 2006.285.20:49:47.89#ibcon#read 5, iclass 33, count 0 2006.285.20:49:47.89#ibcon#about to read 6, iclass 33, count 0 2006.285.20:49:47.89#ibcon#read 6, iclass 33, count 0 2006.285.20:49:47.89#ibcon#end of sib2, iclass 33, count 0 2006.285.20:49:47.89#ibcon#*after write, iclass 33, count 0 2006.285.20:49:47.89#ibcon#*before return 0, iclass 33, count 0 2006.285.20:49:47.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:49:47.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.20:49:47.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:49:47.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:49:47.89$vck44/vb=2,5 2006.285.20:49:47.89#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.20:49:47.89#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.20:49:47.89#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:47.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:49:47.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:49:47.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:49:47.89#ibcon#enter wrdev, iclass 35, count 2 2006.285.20:49:47.89#ibcon#first serial, iclass 35, count 2 2006.285.20:49:47.89#ibcon#enter sib2, iclass 35, count 2 2006.285.20:49:47.89#ibcon#flushed, iclass 35, count 2 2006.285.20:49:47.89#ibcon#about to write, iclass 35, count 2 2006.285.20:49:47.89#ibcon#wrote, iclass 35, count 2 2006.285.20:49:47.89#ibcon#about to read 3, iclass 35, count 2 2006.285.20:49:47.91#ibcon#read 3, iclass 35, count 2 2006.285.20:49:47.91#ibcon#about to read 4, iclass 35, count 2 2006.285.20:49:47.91#ibcon#read 4, iclass 35, count 2 2006.285.20:49:47.91#ibcon#about to read 5, iclass 35, count 2 2006.285.20:49:47.91#ibcon#read 5, iclass 35, count 2 2006.285.20:49:47.91#ibcon#about to read 6, iclass 35, count 2 2006.285.20:49:47.91#ibcon#read 6, iclass 35, count 2 2006.285.20:49:47.91#ibcon#end of sib2, iclass 35, count 2 2006.285.20:49:47.91#ibcon#*mode == 0, iclass 35, count 2 2006.285.20:49:47.91#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.20:49:47.91#ibcon#[27=AT02-05\r\n] 2006.285.20:49:47.91#ibcon#*before write, iclass 35, count 2 2006.285.20:49:47.91#ibcon#enter sib2, iclass 35, count 2 2006.285.20:49:47.91#ibcon#flushed, iclass 35, count 2 2006.285.20:49:47.91#ibcon#about to write, iclass 35, count 2 2006.285.20:49:47.91#ibcon#wrote, iclass 35, count 2 2006.285.20:49:47.91#ibcon#about to read 3, iclass 35, count 2 2006.285.20:49:47.94#ibcon#read 3, iclass 35, count 2 2006.285.20:49:47.94#ibcon#about to read 4, iclass 35, count 2 2006.285.20:49:47.94#ibcon#read 4, iclass 35, count 2 2006.285.20:49:47.94#ibcon#about to read 5, iclass 35, count 2 2006.285.20:49:47.94#ibcon#read 5, iclass 35, count 2 2006.285.20:49:47.94#ibcon#about to read 6, iclass 35, count 2 2006.285.20:49:47.94#ibcon#read 6, iclass 35, count 2 2006.285.20:49:47.94#ibcon#end of sib2, iclass 35, count 2 2006.285.20:49:47.94#ibcon#*after write, iclass 35, count 2 2006.285.20:49:47.94#ibcon#*before return 0, iclass 35, count 2 2006.285.20:49:47.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:49:47.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.20:49:47.94#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.20:49:47.94#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:47.94#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:49:48.06#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:49:48.06#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:49:48.06#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:49:48.06#ibcon#first serial, iclass 35, count 0 2006.285.20:49:48.06#ibcon#enter sib2, iclass 35, count 0 2006.285.20:49:48.06#ibcon#flushed, iclass 35, count 0 2006.285.20:49:48.06#ibcon#about to write, iclass 35, count 0 2006.285.20:49:48.06#ibcon#wrote, iclass 35, count 0 2006.285.20:49:48.06#ibcon#about to read 3, iclass 35, count 0 2006.285.20:49:48.08#ibcon#read 3, iclass 35, count 0 2006.285.20:49:48.08#ibcon#about to read 4, iclass 35, count 0 2006.285.20:49:48.08#ibcon#read 4, iclass 35, count 0 2006.285.20:49:48.08#ibcon#about to read 5, iclass 35, count 0 2006.285.20:49:48.08#ibcon#read 5, iclass 35, count 0 2006.285.20:49:48.08#ibcon#about to read 6, iclass 35, count 0 2006.285.20:49:48.08#ibcon#read 6, iclass 35, count 0 2006.285.20:49:48.08#ibcon#end of sib2, iclass 35, count 0 2006.285.20:49:48.08#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:49:48.08#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:49:48.08#ibcon#[27=USB\r\n] 2006.285.20:49:48.08#ibcon#*before write, iclass 35, count 0 2006.285.20:49:48.08#ibcon#enter sib2, iclass 35, count 0 2006.285.20:49:48.08#ibcon#flushed, iclass 35, count 0 2006.285.20:49:48.08#ibcon#about to write, iclass 35, count 0 2006.285.20:49:48.08#ibcon#wrote, iclass 35, count 0 2006.285.20:49:48.08#ibcon#about to read 3, iclass 35, count 0 2006.285.20:49:48.11#ibcon#read 3, iclass 35, count 0 2006.285.20:49:48.11#ibcon#about to read 4, iclass 35, count 0 2006.285.20:49:48.11#ibcon#read 4, iclass 35, count 0 2006.285.20:49:48.11#ibcon#about to read 5, iclass 35, count 0 2006.285.20:49:48.11#ibcon#read 5, iclass 35, count 0 2006.285.20:49:48.11#ibcon#about to read 6, iclass 35, count 0 2006.285.20:49:48.11#ibcon#read 6, iclass 35, count 0 2006.285.20:49:48.11#ibcon#end of sib2, iclass 35, count 0 2006.285.20:49:48.11#ibcon#*after write, iclass 35, count 0 2006.285.20:49:48.11#ibcon#*before return 0, iclass 35, count 0 2006.285.20:49:48.11#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:49:48.11#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.20:49:48.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:49:48.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:49:48.11$vck44/vblo=3,649.99 2006.285.20:49:48.11#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.20:49:48.11#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.20:49:48.11#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:48.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:49:48.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:49:48.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:49:48.11#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:49:48.11#ibcon#first serial, iclass 37, count 0 2006.285.20:49:48.11#ibcon#enter sib2, iclass 37, count 0 2006.285.20:49:48.11#ibcon#flushed, iclass 37, count 0 2006.285.20:49:48.11#ibcon#about to write, iclass 37, count 0 2006.285.20:49:48.11#ibcon#wrote, iclass 37, count 0 2006.285.20:49:48.11#ibcon#about to read 3, iclass 37, count 0 2006.285.20:49:48.13#ibcon#read 3, iclass 37, count 0 2006.285.20:49:48.13#ibcon#about to read 4, iclass 37, count 0 2006.285.20:49:48.13#ibcon#read 4, iclass 37, count 0 2006.285.20:49:48.13#ibcon#about to read 5, iclass 37, count 0 2006.285.20:49:48.13#ibcon#read 5, iclass 37, count 0 2006.285.20:49:48.13#ibcon#about to read 6, iclass 37, count 0 2006.285.20:49:48.13#ibcon#read 6, iclass 37, count 0 2006.285.20:49:48.13#ibcon#end of sib2, iclass 37, count 0 2006.285.20:49:48.13#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:49:48.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:49:48.13#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.20:49:48.13#ibcon#*before write, iclass 37, count 0 2006.285.20:49:48.13#ibcon#enter sib2, iclass 37, count 0 2006.285.20:49:48.13#ibcon#flushed, iclass 37, count 0 2006.285.20:49:48.13#ibcon#about to write, iclass 37, count 0 2006.285.20:49:48.13#ibcon#wrote, iclass 37, count 0 2006.285.20:49:48.13#ibcon#about to read 3, iclass 37, count 0 2006.285.20:49:48.17#ibcon#read 3, iclass 37, count 0 2006.285.20:49:48.17#ibcon#about to read 4, iclass 37, count 0 2006.285.20:49:48.17#ibcon#read 4, iclass 37, count 0 2006.285.20:49:48.17#ibcon#about to read 5, iclass 37, count 0 2006.285.20:49:48.17#ibcon#read 5, iclass 37, count 0 2006.285.20:49:48.17#ibcon#about to read 6, iclass 37, count 0 2006.285.20:49:48.17#ibcon#read 6, iclass 37, count 0 2006.285.20:49:48.17#ibcon#end of sib2, iclass 37, count 0 2006.285.20:49:48.17#ibcon#*after write, iclass 37, count 0 2006.285.20:49:48.17#ibcon#*before return 0, iclass 37, count 0 2006.285.20:49:48.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:49:48.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:49:48.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:49:48.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:49:48.17$vck44/vb=3,4 2006.285.20:49:48.17#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.20:49:48.17#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.20:49:48.17#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:48.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:49:48.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:49:48.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:49:48.23#ibcon#enter wrdev, iclass 39, count 2 2006.285.20:49:48.23#ibcon#first serial, iclass 39, count 2 2006.285.20:49:48.23#ibcon#enter sib2, iclass 39, count 2 2006.285.20:49:48.23#ibcon#flushed, iclass 39, count 2 2006.285.20:49:48.23#ibcon#about to write, iclass 39, count 2 2006.285.20:49:48.23#ibcon#wrote, iclass 39, count 2 2006.285.20:49:48.23#ibcon#about to read 3, iclass 39, count 2 2006.285.20:49:48.25#ibcon#read 3, iclass 39, count 2 2006.285.20:49:48.25#ibcon#about to read 4, iclass 39, count 2 2006.285.20:49:48.25#ibcon#read 4, iclass 39, count 2 2006.285.20:49:48.25#ibcon#about to read 5, iclass 39, count 2 2006.285.20:49:48.25#ibcon#read 5, iclass 39, count 2 2006.285.20:49:48.25#ibcon#about to read 6, iclass 39, count 2 2006.285.20:49:48.25#ibcon#read 6, iclass 39, count 2 2006.285.20:49:48.25#ibcon#end of sib2, iclass 39, count 2 2006.285.20:49:48.25#ibcon#*mode == 0, iclass 39, count 2 2006.285.20:49:48.25#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.20:49:48.25#ibcon#[27=AT03-04\r\n] 2006.285.20:49:48.25#ibcon#*before write, iclass 39, count 2 2006.285.20:49:48.25#ibcon#enter sib2, iclass 39, count 2 2006.285.20:49:48.25#ibcon#flushed, iclass 39, count 2 2006.285.20:49:48.25#ibcon#about to write, iclass 39, count 2 2006.285.20:49:48.25#ibcon#wrote, iclass 39, count 2 2006.285.20:49:48.25#ibcon#about to read 3, iclass 39, count 2 2006.285.20:49:48.28#ibcon#read 3, iclass 39, count 2 2006.285.20:49:48.28#ibcon#about to read 4, iclass 39, count 2 2006.285.20:49:48.28#ibcon#read 4, iclass 39, count 2 2006.285.20:49:48.28#ibcon#about to read 5, iclass 39, count 2 2006.285.20:49:48.28#ibcon#read 5, iclass 39, count 2 2006.285.20:49:48.28#ibcon#about to read 6, iclass 39, count 2 2006.285.20:49:48.28#ibcon#read 6, iclass 39, count 2 2006.285.20:49:48.28#ibcon#end of sib2, iclass 39, count 2 2006.285.20:49:48.28#ibcon#*after write, iclass 39, count 2 2006.285.20:49:48.28#ibcon#*before return 0, iclass 39, count 2 2006.285.20:49:48.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:49:48.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.20:49:48.28#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.20:49:48.28#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:48.28#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:49:48.40#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:49:48.40#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:49:48.40#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:49:48.40#ibcon#first serial, iclass 39, count 0 2006.285.20:49:48.40#ibcon#enter sib2, iclass 39, count 0 2006.285.20:49:48.40#ibcon#flushed, iclass 39, count 0 2006.285.20:49:48.40#ibcon#about to write, iclass 39, count 0 2006.285.20:49:48.40#ibcon#wrote, iclass 39, count 0 2006.285.20:49:48.40#ibcon#about to read 3, iclass 39, count 0 2006.285.20:49:48.42#ibcon#read 3, iclass 39, count 0 2006.285.20:49:48.42#ibcon#about to read 4, iclass 39, count 0 2006.285.20:49:48.42#ibcon#read 4, iclass 39, count 0 2006.285.20:49:48.42#ibcon#about to read 5, iclass 39, count 0 2006.285.20:49:48.42#ibcon#read 5, iclass 39, count 0 2006.285.20:49:48.42#ibcon#about to read 6, iclass 39, count 0 2006.285.20:49:48.42#ibcon#read 6, iclass 39, count 0 2006.285.20:49:48.42#ibcon#end of sib2, iclass 39, count 0 2006.285.20:49:48.42#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:49:48.42#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:49:48.42#ibcon#[27=USB\r\n] 2006.285.20:49:48.42#ibcon#*before write, iclass 39, count 0 2006.285.20:49:48.42#ibcon#enter sib2, iclass 39, count 0 2006.285.20:49:48.42#ibcon#flushed, iclass 39, count 0 2006.285.20:49:48.42#ibcon#about to write, iclass 39, count 0 2006.285.20:49:48.42#ibcon#wrote, iclass 39, count 0 2006.285.20:49:48.42#ibcon#about to read 3, iclass 39, count 0 2006.285.20:49:48.45#ibcon#read 3, iclass 39, count 0 2006.285.20:49:48.45#ibcon#about to read 4, iclass 39, count 0 2006.285.20:49:48.45#ibcon#read 4, iclass 39, count 0 2006.285.20:49:48.45#ibcon#about to read 5, iclass 39, count 0 2006.285.20:49:48.45#ibcon#read 5, iclass 39, count 0 2006.285.20:49:48.45#ibcon#about to read 6, iclass 39, count 0 2006.285.20:49:48.45#ibcon#read 6, iclass 39, count 0 2006.285.20:49:48.45#ibcon#end of sib2, iclass 39, count 0 2006.285.20:49:48.45#ibcon#*after write, iclass 39, count 0 2006.285.20:49:48.45#ibcon#*before return 0, iclass 39, count 0 2006.285.20:49:48.45#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:49:48.45#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.20:49:48.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:49:48.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:49:48.45$vck44/vblo=4,679.99 2006.285.20:49:48.45#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.20:49:48.45#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.20:49:48.45#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:48.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:49:48.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:49:48.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:49:48.45#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:49:48.45#ibcon#first serial, iclass 3, count 0 2006.285.20:49:48.45#ibcon#enter sib2, iclass 3, count 0 2006.285.20:49:48.45#ibcon#flushed, iclass 3, count 0 2006.285.20:49:48.45#ibcon#about to write, iclass 3, count 0 2006.285.20:49:48.45#ibcon#wrote, iclass 3, count 0 2006.285.20:49:48.45#ibcon#about to read 3, iclass 3, count 0 2006.285.20:49:48.47#ibcon#read 3, iclass 3, count 0 2006.285.20:49:48.47#ibcon#about to read 4, iclass 3, count 0 2006.285.20:49:48.47#ibcon#read 4, iclass 3, count 0 2006.285.20:49:48.47#ibcon#about to read 5, iclass 3, count 0 2006.285.20:49:48.47#ibcon#read 5, iclass 3, count 0 2006.285.20:49:48.47#ibcon#about to read 6, iclass 3, count 0 2006.285.20:49:48.47#ibcon#read 6, iclass 3, count 0 2006.285.20:49:48.47#ibcon#end of sib2, iclass 3, count 0 2006.285.20:49:48.47#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:49:48.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:49:48.47#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.20:49:48.47#ibcon#*before write, iclass 3, count 0 2006.285.20:49:48.47#ibcon#enter sib2, iclass 3, count 0 2006.285.20:49:48.47#ibcon#flushed, iclass 3, count 0 2006.285.20:49:48.47#ibcon#about to write, iclass 3, count 0 2006.285.20:49:48.47#ibcon#wrote, iclass 3, count 0 2006.285.20:49:48.47#ibcon#about to read 3, iclass 3, count 0 2006.285.20:49:48.51#ibcon#read 3, iclass 3, count 0 2006.285.20:49:48.51#ibcon#about to read 4, iclass 3, count 0 2006.285.20:49:48.51#ibcon#read 4, iclass 3, count 0 2006.285.20:49:48.51#ibcon#about to read 5, iclass 3, count 0 2006.285.20:49:48.51#ibcon#read 5, iclass 3, count 0 2006.285.20:49:48.51#ibcon#about to read 6, iclass 3, count 0 2006.285.20:49:48.51#ibcon#read 6, iclass 3, count 0 2006.285.20:49:48.51#ibcon#end of sib2, iclass 3, count 0 2006.285.20:49:48.51#ibcon#*after write, iclass 3, count 0 2006.285.20:49:48.51#ibcon#*before return 0, iclass 3, count 0 2006.285.20:49:48.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:49:48.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.20:49:48.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:49:48.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:49:48.51$vck44/vb=4,5 2006.285.20:49:48.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.20:49:48.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.20:49:48.51#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:48.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:49:48.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:49:48.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:49:48.57#ibcon#enter wrdev, iclass 5, count 2 2006.285.20:49:48.57#ibcon#first serial, iclass 5, count 2 2006.285.20:49:48.57#ibcon#enter sib2, iclass 5, count 2 2006.285.20:49:48.57#ibcon#flushed, iclass 5, count 2 2006.285.20:49:48.57#ibcon#about to write, iclass 5, count 2 2006.285.20:49:48.57#ibcon#wrote, iclass 5, count 2 2006.285.20:49:48.57#ibcon#about to read 3, iclass 5, count 2 2006.285.20:49:48.59#ibcon#read 3, iclass 5, count 2 2006.285.20:49:48.59#ibcon#about to read 4, iclass 5, count 2 2006.285.20:49:48.59#ibcon#read 4, iclass 5, count 2 2006.285.20:49:48.59#ibcon#about to read 5, iclass 5, count 2 2006.285.20:49:48.59#ibcon#read 5, iclass 5, count 2 2006.285.20:49:48.59#ibcon#about to read 6, iclass 5, count 2 2006.285.20:49:48.59#ibcon#read 6, iclass 5, count 2 2006.285.20:49:48.59#ibcon#end of sib2, iclass 5, count 2 2006.285.20:49:48.59#ibcon#*mode == 0, iclass 5, count 2 2006.285.20:49:48.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.20:49:48.59#ibcon#[27=AT04-05\r\n] 2006.285.20:49:48.59#ibcon#*before write, iclass 5, count 2 2006.285.20:49:48.59#ibcon#enter sib2, iclass 5, count 2 2006.285.20:49:48.59#ibcon#flushed, iclass 5, count 2 2006.285.20:49:48.59#ibcon#about to write, iclass 5, count 2 2006.285.20:49:48.59#ibcon#wrote, iclass 5, count 2 2006.285.20:49:48.59#ibcon#about to read 3, iclass 5, count 2 2006.285.20:49:48.62#ibcon#read 3, iclass 5, count 2 2006.285.20:49:48.62#ibcon#about to read 4, iclass 5, count 2 2006.285.20:49:48.62#ibcon#read 4, iclass 5, count 2 2006.285.20:49:48.62#ibcon#about to read 5, iclass 5, count 2 2006.285.20:49:48.62#ibcon#read 5, iclass 5, count 2 2006.285.20:49:48.62#ibcon#about to read 6, iclass 5, count 2 2006.285.20:49:48.62#ibcon#read 6, iclass 5, count 2 2006.285.20:49:48.62#ibcon#end of sib2, iclass 5, count 2 2006.285.20:49:48.62#ibcon#*after write, iclass 5, count 2 2006.285.20:49:48.62#ibcon#*before return 0, iclass 5, count 2 2006.285.20:49:48.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:49:48.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.20:49:48.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.20:49:48.62#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:48.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:49:48.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:49:48.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:49:48.74#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:49:48.74#ibcon#first serial, iclass 5, count 0 2006.285.20:49:48.74#ibcon#enter sib2, iclass 5, count 0 2006.285.20:49:48.74#ibcon#flushed, iclass 5, count 0 2006.285.20:49:48.74#ibcon#about to write, iclass 5, count 0 2006.285.20:49:48.74#ibcon#wrote, iclass 5, count 0 2006.285.20:49:48.74#ibcon#about to read 3, iclass 5, count 0 2006.285.20:49:48.76#ibcon#read 3, iclass 5, count 0 2006.285.20:49:48.76#ibcon#about to read 4, iclass 5, count 0 2006.285.20:49:48.76#ibcon#read 4, iclass 5, count 0 2006.285.20:49:48.76#ibcon#about to read 5, iclass 5, count 0 2006.285.20:49:48.76#ibcon#read 5, iclass 5, count 0 2006.285.20:49:48.76#ibcon#about to read 6, iclass 5, count 0 2006.285.20:49:48.76#ibcon#read 6, iclass 5, count 0 2006.285.20:49:48.76#ibcon#end of sib2, iclass 5, count 0 2006.285.20:49:48.76#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:49:48.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:49:48.76#ibcon#[27=USB\r\n] 2006.285.20:49:48.76#ibcon#*before write, iclass 5, count 0 2006.285.20:49:48.76#ibcon#enter sib2, iclass 5, count 0 2006.285.20:49:48.76#ibcon#flushed, iclass 5, count 0 2006.285.20:49:48.76#ibcon#about to write, iclass 5, count 0 2006.285.20:49:48.76#ibcon#wrote, iclass 5, count 0 2006.285.20:49:48.76#ibcon#about to read 3, iclass 5, count 0 2006.285.20:49:48.79#ibcon#read 3, iclass 5, count 0 2006.285.20:49:48.79#ibcon#about to read 4, iclass 5, count 0 2006.285.20:49:48.79#ibcon#read 4, iclass 5, count 0 2006.285.20:49:48.79#ibcon#about to read 5, iclass 5, count 0 2006.285.20:49:48.79#ibcon#read 5, iclass 5, count 0 2006.285.20:49:48.79#ibcon#about to read 6, iclass 5, count 0 2006.285.20:49:48.79#ibcon#read 6, iclass 5, count 0 2006.285.20:49:48.79#ibcon#end of sib2, iclass 5, count 0 2006.285.20:49:48.79#ibcon#*after write, iclass 5, count 0 2006.285.20:49:48.79#ibcon#*before return 0, iclass 5, count 0 2006.285.20:49:48.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:49:48.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.20:49:48.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:49:48.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:49:48.79$vck44/vblo=5,709.99 2006.285.20:49:48.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.20:49:48.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.20:49:48.79#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:48.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:49:48.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:49:48.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:49:48.79#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:49:48.79#ibcon#first serial, iclass 7, count 0 2006.285.20:49:48.79#ibcon#enter sib2, iclass 7, count 0 2006.285.20:49:48.79#ibcon#flushed, iclass 7, count 0 2006.285.20:49:48.79#ibcon#about to write, iclass 7, count 0 2006.285.20:49:48.79#ibcon#wrote, iclass 7, count 0 2006.285.20:49:48.79#ibcon#about to read 3, iclass 7, count 0 2006.285.20:49:48.81#ibcon#read 3, iclass 7, count 0 2006.285.20:49:48.85#ibcon#about to read 4, iclass 7, count 0 2006.285.20:49:48.85#ibcon#read 4, iclass 7, count 0 2006.285.20:49:48.85#ibcon#about to read 5, iclass 7, count 0 2006.285.20:49:48.85#ibcon#read 5, iclass 7, count 0 2006.285.20:49:48.85#ibcon#about to read 6, iclass 7, count 0 2006.285.20:49:48.85#ibcon#read 6, iclass 7, count 0 2006.285.20:49:48.85#ibcon#end of sib2, iclass 7, count 0 2006.285.20:49:48.85#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:49:48.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:49:48.85#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.20:49:48.85#ibcon#*before write, iclass 7, count 0 2006.285.20:49:48.85#ibcon#enter sib2, iclass 7, count 0 2006.285.20:49:48.85#ibcon#flushed, iclass 7, count 0 2006.285.20:49:48.85#ibcon#about to write, iclass 7, count 0 2006.285.20:49:48.85#ibcon#wrote, iclass 7, count 0 2006.285.20:49:48.85#ibcon#about to read 3, iclass 7, count 0 2006.285.20:49:48.89#ibcon#read 3, iclass 7, count 0 2006.285.20:49:48.89#ibcon#about to read 4, iclass 7, count 0 2006.285.20:49:48.89#ibcon#read 4, iclass 7, count 0 2006.285.20:49:48.89#ibcon#about to read 5, iclass 7, count 0 2006.285.20:49:48.89#ibcon#read 5, iclass 7, count 0 2006.285.20:49:48.89#ibcon#about to read 6, iclass 7, count 0 2006.285.20:49:48.89#ibcon#read 6, iclass 7, count 0 2006.285.20:49:48.89#ibcon#end of sib2, iclass 7, count 0 2006.285.20:49:48.89#ibcon#*after write, iclass 7, count 0 2006.285.20:49:48.89#ibcon#*before return 0, iclass 7, count 0 2006.285.20:49:48.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:49:48.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.20:49:48.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:49:48.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:49:48.89$vck44/vb=5,4 2006.285.20:49:48.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.20:49:48.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.20:49:48.89#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:48.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:49:48.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:49:48.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:49:48.91#ibcon#enter wrdev, iclass 11, count 2 2006.285.20:49:48.91#ibcon#first serial, iclass 11, count 2 2006.285.20:49:48.91#ibcon#enter sib2, iclass 11, count 2 2006.285.20:49:48.91#ibcon#flushed, iclass 11, count 2 2006.285.20:49:48.91#ibcon#about to write, iclass 11, count 2 2006.285.20:49:48.91#ibcon#wrote, iclass 11, count 2 2006.285.20:49:48.91#ibcon#about to read 3, iclass 11, count 2 2006.285.20:49:48.93#ibcon#read 3, iclass 11, count 2 2006.285.20:49:48.93#ibcon#about to read 4, iclass 11, count 2 2006.285.20:49:48.93#ibcon#read 4, iclass 11, count 2 2006.285.20:49:48.93#ibcon#about to read 5, iclass 11, count 2 2006.285.20:49:48.93#ibcon#read 5, iclass 11, count 2 2006.285.20:49:48.93#ibcon#about to read 6, iclass 11, count 2 2006.285.20:49:48.93#ibcon#read 6, iclass 11, count 2 2006.285.20:49:48.93#ibcon#end of sib2, iclass 11, count 2 2006.285.20:49:48.93#ibcon#*mode == 0, iclass 11, count 2 2006.285.20:49:48.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.20:49:48.93#ibcon#[27=AT05-04\r\n] 2006.285.20:49:48.93#ibcon#*before write, iclass 11, count 2 2006.285.20:49:48.93#ibcon#enter sib2, iclass 11, count 2 2006.285.20:49:48.93#ibcon#flushed, iclass 11, count 2 2006.285.20:49:48.93#ibcon#about to write, iclass 11, count 2 2006.285.20:49:48.93#ibcon#wrote, iclass 11, count 2 2006.285.20:49:48.93#ibcon#about to read 3, iclass 11, count 2 2006.285.20:49:48.96#ibcon#read 3, iclass 11, count 2 2006.285.20:49:48.96#ibcon#about to read 4, iclass 11, count 2 2006.285.20:49:48.96#ibcon#read 4, iclass 11, count 2 2006.285.20:49:48.96#ibcon#about to read 5, iclass 11, count 2 2006.285.20:49:48.96#ibcon#read 5, iclass 11, count 2 2006.285.20:49:48.96#ibcon#about to read 6, iclass 11, count 2 2006.285.20:49:48.96#ibcon#read 6, iclass 11, count 2 2006.285.20:49:48.96#ibcon#end of sib2, iclass 11, count 2 2006.285.20:49:48.96#ibcon#*after write, iclass 11, count 2 2006.285.20:49:48.96#ibcon#*before return 0, iclass 11, count 2 2006.285.20:49:48.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:49:48.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.20:49:48.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.20:49:48.96#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:48.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:49:49.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:49:49.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:49:49.08#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:49:49.08#ibcon#first serial, iclass 11, count 0 2006.285.20:49:49.08#ibcon#enter sib2, iclass 11, count 0 2006.285.20:49:49.08#ibcon#flushed, iclass 11, count 0 2006.285.20:49:49.08#ibcon#about to write, iclass 11, count 0 2006.285.20:49:49.08#ibcon#wrote, iclass 11, count 0 2006.285.20:49:49.08#ibcon#about to read 3, iclass 11, count 0 2006.285.20:49:49.10#ibcon#read 3, iclass 11, count 0 2006.285.20:49:49.10#ibcon#about to read 4, iclass 11, count 0 2006.285.20:49:49.10#ibcon#read 4, iclass 11, count 0 2006.285.20:49:49.10#ibcon#about to read 5, iclass 11, count 0 2006.285.20:49:49.10#ibcon#read 5, iclass 11, count 0 2006.285.20:49:49.10#ibcon#about to read 6, iclass 11, count 0 2006.285.20:49:49.10#ibcon#read 6, iclass 11, count 0 2006.285.20:49:49.10#ibcon#end of sib2, iclass 11, count 0 2006.285.20:49:49.10#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:49:49.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:49:49.10#ibcon#[27=USB\r\n] 2006.285.20:49:49.10#ibcon#*before write, iclass 11, count 0 2006.285.20:49:49.10#ibcon#enter sib2, iclass 11, count 0 2006.285.20:49:49.10#ibcon#flushed, iclass 11, count 0 2006.285.20:49:49.10#ibcon#about to write, iclass 11, count 0 2006.285.20:49:49.10#ibcon#wrote, iclass 11, count 0 2006.285.20:49:49.10#ibcon#about to read 3, iclass 11, count 0 2006.285.20:49:49.13#ibcon#read 3, iclass 11, count 0 2006.285.20:49:49.13#ibcon#about to read 4, iclass 11, count 0 2006.285.20:49:49.13#ibcon#read 4, iclass 11, count 0 2006.285.20:49:49.13#ibcon#about to read 5, iclass 11, count 0 2006.285.20:49:49.13#ibcon#read 5, iclass 11, count 0 2006.285.20:49:49.13#ibcon#about to read 6, iclass 11, count 0 2006.285.20:49:49.13#ibcon#read 6, iclass 11, count 0 2006.285.20:49:49.13#ibcon#end of sib2, iclass 11, count 0 2006.285.20:49:49.13#ibcon#*after write, iclass 11, count 0 2006.285.20:49:49.13#ibcon#*before return 0, iclass 11, count 0 2006.285.20:49:49.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:49:49.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.20:49:49.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:49:49.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:49:49.13$vck44/vblo=6,719.99 2006.285.20:49:49.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.20:49:49.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.20:49:49.13#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:49.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:49:49.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:49:49.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:49:49.13#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:49:49.13#ibcon#first serial, iclass 13, count 0 2006.285.20:49:49.13#ibcon#enter sib2, iclass 13, count 0 2006.285.20:49:49.13#ibcon#flushed, iclass 13, count 0 2006.285.20:49:49.13#ibcon#about to write, iclass 13, count 0 2006.285.20:49:49.13#ibcon#wrote, iclass 13, count 0 2006.285.20:49:49.13#ibcon#about to read 3, iclass 13, count 0 2006.285.20:49:49.15#ibcon#read 3, iclass 13, count 0 2006.285.20:49:49.15#ibcon#about to read 4, iclass 13, count 0 2006.285.20:49:49.15#ibcon#read 4, iclass 13, count 0 2006.285.20:49:49.15#ibcon#about to read 5, iclass 13, count 0 2006.285.20:49:49.15#ibcon#read 5, iclass 13, count 0 2006.285.20:49:49.15#ibcon#about to read 6, iclass 13, count 0 2006.285.20:49:49.15#ibcon#read 6, iclass 13, count 0 2006.285.20:49:49.15#ibcon#end of sib2, iclass 13, count 0 2006.285.20:49:49.15#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:49:49.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:49:49.15#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.20:49:49.15#ibcon#*before write, iclass 13, count 0 2006.285.20:49:49.15#ibcon#enter sib2, iclass 13, count 0 2006.285.20:49:49.15#ibcon#flushed, iclass 13, count 0 2006.285.20:49:49.15#ibcon#about to write, iclass 13, count 0 2006.285.20:49:49.15#ibcon#wrote, iclass 13, count 0 2006.285.20:49:49.15#ibcon#about to read 3, iclass 13, count 0 2006.285.20:49:49.19#ibcon#read 3, iclass 13, count 0 2006.285.20:49:49.19#ibcon#about to read 4, iclass 13, count 0 2006.285.20:49:49.19#ibcon#read 4, iclass 13, count 0 2006.285.20:49:49.19#ibcon#about to read 5, iclass 13, count 0 2006.285.20:49:49.19#ibcon#read 5, iclass 13, count 0 2006.285.20:49:49.19#ibcon#about to read 6, iclass 13, count 0 2006.285.20:49:49.19#ibcon#read 6, iclass 13, count 0 2006.285.20:49:49.19#ibcon#end of sib2, iclass 13, count 0 2006.285.20:49:49.19#ibcon#*after write, iclass 13, count 0 2006.285.20:49:49.19#ibcon#*before return 0, iclass 13, count 0 2006.285.20:49:49.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:49:49.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.20:49:49.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:49:49.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:49:49.19$vck44/vb=6,3 2006.285.20:49:49.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.20:49:49.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.20:49:49.19#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:49.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:49:49.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:49:49.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:49:49.25#ibcon#enter wrdev, iclass 15, count 2 2006.285.20:49:49.25#ibcon#first serial, iclass 15, count 2 2006.285.20:49:49.25#ibcon#enter sib2, iclass 15, count 2 2006.285.20:49:49.25#ibcon#flushed, iclass 15, count 2 2006.285.20:49:49.25#ibcon#about to write, iclass 15, count 2 2006.285.20:49:49.25#ibcon#wrote, iclass 15, count 2 2006.285.20:49:49.25#ibcon#about to read 3, iclass 15, count 2 2006.285.20:49:49.27#ibcon#read 3, iclass 15, count 2 2006.285.20:49:49.27#ibcon#about to read 4, iclass 15, count 2 2006.285.20:49:49.27#ibcon#read 4, iclass 15, count 2 2006.285.20:49:49.27#ibcon#about to read 5, iclass 15, count 2 2006.285.20:49:49.27#ibcon#read 5, iclass 15, count 2 2006.285.20:49:49.27#ibcon#about to read 6, iclass 15, count 2 2006.285.20:49:49.27#ibcon#read 6, iclass 15, count 2 2006.285.20:49:49.27#ibcon#end of sib2, iclass 15, count 2 2006.285.20:49:49.27#ibcon#*mode == 0, iclass 15, count 2 2006.285.20:49:49.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.20:49:49.27#ibcon#[27=AT06-03\r\n] 2006.285.20:49:49.27#ibcon#*before write, iclass 15, count 2 2006.285.20:49:49.27#ibcon#enter sib2, iclass 15, count 2 2006.285.20:49:49.27#ibcon#flushed, iclass 15, count 2 2006.285.20:49:49.27#ibcon#about to write, iclass 15, count 2 2006.285.20:49:49.27#ibcon#wrote, iclass 15, count 2 2006.285.20:49:49.27#ibcon#about to read 3, iclass 15, count 2 2006.285.20:49:49.30#ibcon#read 3, iclass 15, count 2 2006.285.20:49:49.30#ibcon#about to read 4, iclass 15, count 2 2006.285.20:49:49.30#ibcon#read 4, iclass 15, count 2 2006.285.20:49:49.30#ibcon#about to read 5, iclass 15, count 2 2006.285.20:49:49.30#ibcon#read 5, iclass 15, count 2 2006.285.20:49:49.30#ibcon#about to read 6, iclass 15, count 2 2006.285.20:49:49.30#ibcon#read 6, iclass 15, count 2 2006.285.20:49:49.30#ibcon#end of sib2, iclass 15, count 2 2006.285.20:49:49.30#ibcon#*after write, iclass 15, count 2 2006.285.20:49:49.30#ibcon#*before return 0, iclass 15, count 2 2006.285.20:49:49.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:49:49.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.20:49:49.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.20:49:49.30#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:49.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:49:49.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:49:49.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:49:49.42#ibcon#enter wrdev, iclass 15, count 0 2006.285.20:49:49.42#ibcon#first serial, iclass 15, count 0 2006.285.20:49:49.42#ibcon#enter sib2, iclass 15, count 0 2006.285.20:49:49.42#ibcon#flushed, iclass 15, count 0 2006.285.20:49:49.42#ibcon#about to write, iclass 15, count 0 2006.285.20:49:49.42#ibcon#wrote, iclass 15, count 0 2006.285.20:49:49.42#ibcon#about to read 3, iclass 15, count 0 2006.285.20:49:49.44#ibcon#read 3, iclass 15, count 0 2006.285.20:49:49.44#ibcon#about to read 4, iclass 15, count 0 2006.285.20:49:49.44#ibcon#read 4, iclass 15, count 0 2006.285.20:49:49.44#ibcon#about to read 5, iclass 15, count 0 2006.285.20:49:49.44#ibcon#read 5, iclass 15, count 0 2006.285.20:49:49.44#ibcon#about to read 6, iclass 15, count 0 2006.285.20:49:49.44#ibcon#read 6, iclass 15, count 0 2006.285.20:49:49.44#ibcon#end of sib2, iclass 15, count 0 2006.285.20:49:49.44#ibcon#*mode == 0, iclass 15, count 0 2006.285.20:49:49.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.20:49:49.44#ibcon#[27=USB\r\n] 2006.285.20:49:49.44#ibcon#*before write, iclass 15, count 0 2006.285.20:49:49.44#ibcon#enter sib2, iclass 15, count 0 2006.285.20:49:49.44#ibcon#flushed, iclass 15, count 0 2006.285.20:49:49.44#ibcon#about to write, iclass 15, count 0 2006.285.20:49:49.44#ibcon#wrote, iclass 15, count 0 2006.285.20:49:49.44#ibcon#about to read 3, iclass 15, count 0 2006.285.20:49:49.47#ibcon#read 3, iclass 15, count 0 2006.285.20:49:49.47#ibcon#about to read 4, iclass 15, count 0 2006.285.20:49:49.47#ibcon#read 4, iclass 15, count 0 2006.285.20:49:49.47#ibcon#about to read 5, iclass 15, count 0 2006.285.20:49:49.47#ibcon#read 5, iclass 15, count 0 2006.285.20:49:49.47#ibcon#about to read 6, iclass 15, count 0 2006.285.20:49:49.47#ibcon#read 6, iclass 15, count 0 2006.285.20:49:49.47#ibcon#end of sib2, iclass 15, count 0 2006.285.20:49:49.47#ibcon#*after write, iclass 15, count 0 2006.285.20:49:49.47#ibcon#*before return 0, iclass 15, count 0 2006.285.20:49:49.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:49:49.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.20:49:49.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.20:49:49.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.20:49:49.47$vck44/vblo=7,734.99 2006.285.20:49:49.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.20:49:49.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.20:49:49.47#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:49.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:49:49.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:49:49.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:49:49.47#ibcon#enter wrdev, iclass 17, count 0 2006.285.20:49:49.47#ibcon#first serial, iclass 17, count 0 2006.285.20:49:49.47#ibcon#enter sib2, iclass 17, count 0 2006.285.20:49:49.47#ibcon#flushed, iclass 17, count 0 2006.285.20:49:49.47#ibcon#about to write, iclass 17, count 0 2006.285.20:49:49.47#ibcon#wrote, iclass 17, count 0 2006.285.20:49:49.47#ibcon#about to read 3, iclass 17, count 0 2006.285.20:49:49.49#ibcon#read 3, iclass 17, count 0 2006.285.20:49:49.49#ibcon#about to read 4, iclass 17, count 0 2006.285.20:49:49.49#ibcon#read 4, iclass 17, count 0 2006.285.20:49:49.49#ibcon#about to read 5, iclass 17, count 0 2006.285.20:49:49.49#ibcon#read 5, iclass 17, count 0 2006.285.20:49:49.49#ibcon#about to read 6, iclass 17, count 0 2006.285.20:49:49.49#ibcon#read 6, iclass 17, count 0 2006.285.20:49:49.49#ibcon#end of sib2, iclass 17, count 0 2006.285.20:49:49.49#ibcon#*mode == 0, iclass 17, count 0 2006.285.20:49:49.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.20:49:49.49#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.20:49:49.49#ibcon#*before write, iclass 17, count 0 2006.285.20:49:49.49#ibcon#enter sib2, iclass 17, count 0 2006.285.20:49:49.49#ibcon#flushed, iclass 17, count 0 2006.285.20:49:49.49#ibcon#about to write, iclass 17, count 0 2006.285.20:49:49.49#ibcon#wrote, iclass 17, count 0 2006.285.20:49:49.49#ibcon#about to read 3, iclass 17, count 0 2006.285.20:49:49.53#ibcon#read 3, iclass 17, count 0 2006.285.20:49:49.53#ibcon#about to read 4, iclass 17, count 0 2006.285.20:49:49.53#ibcon#read 4, iclass 17, count 0 2006.285.20:49:49.53#ibcon#about to read 5, iclass 17, count 0 2006.285.20:49:49.53#ibcon#read 5, iclass 17, count 0 2006.285.20:49:49.53#ibcon#about to read 6, iclass 17, count 0 2006.285.20:49:49.53#ibcon#read 6, iclass 17, count 0 2006.285.20:49:49.53#ibcon#end of sib2, iclass 17, count 0 2006.285.20:49:49.53#ibcon#*after write, iclass 17, count 0 2006.285.20:49:49.53#ibcon#*before return 0, iclass 17, count 0 2006.285.20:49:49.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:49:49.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.20:49:49.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.20:49:49.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.20:49:49.53$vck44/vb=7,4 2006.285.20:49:49.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.20:49:49.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.20:49:49.53#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:49.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:49:49.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:49:49.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:49:49.59#ibcon#enter wrdev, iclass 19, count 2 2006.285.20:49:49.59#ibcon#first serial, iclass 19, count 2 2006.285.20:49:49.59#ibcon#enter sib2, iclass 19, count 2 2006.285.20:49:49.59#ibcon#flushed, iclass 19, count 2 2006.285.20:49:49.59#ibcon#about to write, iclass 19, count 2 2006.285.20:49:49.59#ibcon#wrote, iclass 19, count 2 2006.285.20:49:49.59#ibcon#about to read 3, iclass 19, count 2 2006.285.20:49:49.61#ibcon#read 3, iclass 19, count 2 2006.285.20:49:49.61#ibcon#about to read 4, iclass 19, count 2 2006.285.20:49:49.61#ibcon#read 4, iclass 19, count 2 2006.285.20:49:49.61#ibcon#about to read 5, iclass 19, count 2 2006.285.20:49:49.61#ibcon#read 5, iclass 19, count 2 2006.285.20:49:49.61#ibcon#about to read 6, iclass 19, count 2 2006.285.20:49:49.61#ibcon#read 6, iclass 19, count 2 2006.285.20:49:49.61#ibcon#end of sib2, iclass 19, count 2 2006.285.20:49:49.61#ibcon#*mode == 0, iclass 19, count 2 2006.285.20:49:49.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.20:49:49.61#ibcon#[27=AT07-04\r\n] 2006.285.20:49:49.61#ibcon#*before write, iclass 19, count 2 2006.285.20:49:49.61#ibcon#enter sib2, iclass 19, count 2 2006.285.20:49:49.61#ibcon#flushed, iclass 19, count 2 2006.285.20:49:49.61#ibcon#about to write, iclass 19, count 2 2006.285.20:49:49.61#ibcon#wrote, iclass 19, count 2 2006.285.20:49:49.61#ibcon#about to read 3, iclass 19, count 2 2006.285.20:49:49.64#abcon#<5=/00 0.2 0.7 14.171001015.4\r\n> 2006.285.20:49:49.64#ibcon#read 3, iclass 19, count 2 2006.285.20:49:49.64#ibcon#about to read 4, iclass 19, count 2 2006.285.20:49:49.64#ibcon#read 4, iclass 19, count 2 2006.285.20:49:49.64#ibcon#about to read 5, iclass 19, count 2 2006.285.20:49:49.64#ibcon#read 5, iclass 19, count 2 2006.285.20:49:49.64#ibcon#about to read 6, iclass 19, count 2 2006.285.20:49:49.64#ibcon#read 6, iclass 19, count 2 2006.285.20:49:49.64#ibcon#end of sib2, iclass 19, count 2 2006.285.20:49:49.64#ibcon#*after write, iclass 19, count 2 2006.285.20:49:49.64#ibcon#*before return 0, iclass 19, count 2 2006.285.20:49:49.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:49:49.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.20:49:49.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.20:49:49.64#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:49.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:49:49.66#abcon#{5=INTERFACE CLEAR} 2006.285.20:49:49.72#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:49:49.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:49:49.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:49:49.76#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:49:49.76#ibcon#first serial, iclass 19, count 0 2006.285.20:49:49.76#ibcon#enter sib2, iclass 19, count 0 2006.285.20:49:49.76#ibcon#flushed, iclass 19, count 0 2006.285.20:49:49.76#ibcon#about to write, iclass 19, count 0 2006.285.20:49:49.76#ibcon#wrote, iclass 19, count 0 2006.285.20:49:49.76#ibcon#about to read 3, iclass 19, count 0 2006.285.20:49:49.78#ibcon#read 3, iclass 19, count 0 2006.285.20:49:49.78#ibcon#about to read 4, iclass 19, count 0 2006.285.20:49:49.78#ibcon#read 4, iclass 19, count 0 2006.285.20:49:49.78#ibcon#about to read 5, iclass 19, count 0 2006.285.20:49:49.78#ibcon#read 5, iclass 19, count 0 2006.285.20:49:49.78#ibcon#about to read 6, iclass 19, count 0 2006.285.20:49:49.78#ibcon#read 6, iclass 19, count 0 2006.285.20:49:49.78#ibcon#end of sib2, iclass 19, count 0 2006.285.20:49:49.78#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:49:49.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:49:49.78#ibcon#[27=USB\r\n] 2006.285.20:49:49.78#ibcon#*before write, iclass 19, count 0 2006.285.20:49:49.78#ibcon#enter sib2, iclass 19, count 0 2006.285.20:49:49.78#ibcon#flushed, iclass 19, count 0 2006.285.20:49:49.78#ibcon#about to write, iclass 19, count 0 2006.285.20:49:49.78#ibcon#wrote, iclass 19, count 0 2006.285.20:49:49.78#ibcon#about to read 3, iclass 19, count 0 2006.285.20:49:49.81#ibcon#read 3, iclass 19, count 0 2006.285.20:49:49.81#ibcon#about to read 4, iclass 19, count 0 2006.285.20:49:49.81#ibcon#read 4, iclass 19, count 0 2006.285.20:49:49.81#ibcon#about to read 5, iclass 19, count 0 2006.285.20:49:49.81#ibcon#read 5, iclass 19, count 0 2006.285.20:49:49.81#ibcon#about to read 6, iclass 19, count 0 2006.285.20:49:49.81#ibcon#read 6, iclass 19, count 0 2006.285.20:49:49.81#ibcon#end of sib2, iclass 19, count 0 2006.285.20:49:49.81#ibcon#*after write, iclass 19, count 0 2006.285.20:49:49.81#ibcon#*before return 0, iclass 19, count 0 2006.285.20:49:49.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:49:49.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.20:49:49.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:49:49.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:49:49.81$vck44/vblo=8,744.99 2006.285.20:49:49.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.20:49:49.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.20:49:49.85#ibcon#ireg 17 cls_cnt 0 2006.285.20:49:49.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:49:49.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:49:49.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:49:49.85#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:49:49.85#ibcon#first serial, iclass 25, count 0 2006.285.20:49:49.85#ibcon#enter sib2, iclass 25, count 0 2006.285.20:49:49.85#ibcon#flushed, iclass 25, count 0 2006.285.20:49:49.85#ibcon#about to write, iclass 25, count 0 2006.285.20:49:49.85#ibcon#wrote, iclass 25, count 0 2006.285.20:49:49.85#ibcon#about to read 3, iclass 25, count 0 2006.285.20:49:49.86#ibcon#read 3, iclass 25, count 0 2006.285.20:49:49.86#ibcon#about to read 4, iclass 25, count 0 2006.285.20:49:49.86#ibcon#read 4, iclass 25, count 0 2006.285.20:49:49.86#ibcon#about to read 5, iclass 25, count 0 2006.285.20:49:49.86#ibcon#read 5, iclass 25, count 0 2006.285.20:49:49.86#ibcon#about to read 6, iclass 25, count 0 2006.285.20:49:49.86#ibcon#read 6, iclass 25, count 0 2006.285.20:49:49.86#ibcon#end of sib2, iclass 25, count 0 2006.285.20:49:49.86#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:49:49.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:49:49.86#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.20:49:49.86#ibcon#*before write, iclass 25, count 0 2006.285.20:49:49.86#ibcon#enter sib2, iclass 25, count 0 2006.285.20:49:49.86#ibcon#flushed, iclass 25, count 0 2006.285.20:49:49.86#ibcon#about to write, iclass 25, count 0 2006.285.20:49:49.86#ibcon#wrote, iclass 25, count 0 2006.285.20:49:49.86#ibcon#about to read 3, iclass 25, count 0 2006.285.20:49:49.90#ibcon#read 3, iclass 25, count 0 2006.285.20:49:49.90#ibcon#about to read 4, iclass 25, count 0 2006.285.20:49:49.90#ibcon#read 4, iclass 25, count 0 2006.285.20:49:49.90#ibcon#about to read 5, iclass 25, count 0 2006.285.20:49:49.90#ibcon#read 5, iclass 25, count 0 2006.285.20:49:49.90#ibcon#about to read 6, iclass 25, count 0 2006.285.20:49:49.90#ibcon#read 6, iclass 25, count 0 2006.285.20:49:49.90#ibcon#end of sib2, iclass 25, count 0 2006.285.20:49:49.90#ibcon#*after write, iclass 25, count 0 2006.285.20:49:49.90#ibcon#*before return 0, iclass 25, count 0 2006.285.20:49:49.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:49:49.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.20:49:49.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:49:49.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:49:49.90$vck44/vb=8,4 2006.285.20:49:49.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.20:49:49.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.20:49:49.90#ibcon#ireg 11 cls_cnt 2 2006.285.20:49:49.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:49:49.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:49:49.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:49:49.93#ibcon#enter wrdev, iclass 27, count 2 2006.285.20:49:49.93#ibcon#first serial, iclass 27, count 2 2006.285.20:49:49.93#ibcon#enter sib2, iclass 27, count 2 2006.285.20:49:49.93#ibcon#flushed, iclass 27, count 2 2006.285.20:49:49.93#ibcon#about to write, iclass 27, count 2 2006.285.20:49:49.93#ibcon#wrote, iclass 27, count 2 2006.285.20:49:49.93#ibcon#about to read 3, iclass 27, count 2 2006.285.20:49:49.95#ibcon#read 3, iclass 27, count 2 2006.285.20:49:49.95#ibcon#about to read 4, iclass 27, count 2 2006.285.20:49:49.95#ibcon#read 4, iclass 27, count 2 2006.285.20:49:49.95#ibcon#about to read 5, iclass 27, count 2 2006.285.20:49:49.95#ibcon#read 5, iclass 27, count 2 2006.285.20:49:49.95#ibcon#about to read 6, iclass 27, count 2 2006.285.20:49:49.95#ibcon#read 6, iclass 27, count 2 2006.285.20:49:49.95#ibcon#end of sib2, iclass 27, count 2 2006.285.20:49:49.95#ibcon#*mode == 0, iclass 27, count 2 2006.285.20:49:49.95#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.20:49:49.95#ibcon#[27=AT08-04\r\n] 2006.285.20:49:49.95#ibcon#*before write, iclass 27, count 2 2006.285.20:49:49.95#ibcon#enter sib2, iclass 27, count 2 2006.285.20:49:49.95#ibcon#flushed, iclass 27, count 2 2006.285.20:49:49.95#ibcon#about to write, iclass 27, count 2 2006.285.20:49:49.95#ibcon#wrote, iclass 27, count 2 2006.285.20:49:49.95#ibcon#about to read 3, iclass 27, count 2 2006.285.20:49:49.98#ibcon#read 3, iclass 27, count 2 2006.285.20:49:49.98#ibcon#about to read 4, iclass 27, count 2 2006.285.20:49:49.98#ibcon#read 4, iclass 27, count 2 2006.285.20:49:49.98#ibcon#about to read 5, iclass 27, count 2 2006.285.20:49:49.98#ibcon#read 5, iclass 27, count 2 2006.285.20:49:49.98#ibcon#about to read 6, iclass 27, count 2 2006.285.20:49:49.98#ibcon#read 6, iclass 27, count 2 2006.285.20:49:49.98#ibcon#end of sib2, iclass 27, count 2 2006.285.20:49:49.98#ibcon#*after write, iclass 27, count 2 2006.285.20:49:49.98#ibcon#*before return 0, iclass 27, count 2 2006.285.20:49:49.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:49:49.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.20:49:49.98#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.20:49:49.98#ibcon#ireg 7 cls_cnt 0 2006.285.20:49:49.98#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:49:50.10#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:49:50.10#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:49:50.10#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:49:50.10#ibcon#first serial, iclass 27, count 0 2006.285.20:49:50.10#ibcon#enter sib2, iclass 27, count 0 2006.285.20:49:50.10#ibcon#flushed, iclass 27, count 0 2006.285.20:49:50.10#ibcon#about to write, iclass 27, count 0 2006.285.20:49:50.10#ibcon#wrote, iclass 27, count 0 2006.285.20:49:50.10#ibcon#about to read 3, iclass 27, count 0 2006.285.20:49:50.12#ibcon#read 3, iclass 27, count 0 2006.285.20:49:50.12#ibcon#about to read 4, iclass 27, count 0 2006.285.20:49:50.12#ibcon#read 4, iclass 27, count 0 2006.285.20:49:50.12#ibcon#about to read 5, iclass 27, count 0 2006.285.20:49:50.12#ibcon#read 5, iclass 27, count 0 2006.285.20:49:50.12#ibcon#about to read 6, iclass 27, count 0 2006.285.20:49:50.12#ibcon#read 6, iclass 27, count 0 2006.285.20:49:50.12#ibcon#end of sib2, iclass 27, count 0 2006.285.20:49:50.12#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:49:50.12#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:49:50.12#ibcon#[27=USB\r\n] 2006.285.20:49:50.12#ibcon#*before write, iclass 27, count 0 2006.285.20:49:50.12#ibcon#enter sib2, iclass 27, count 0 2006.285.20:49:50.12#ibcon#flushed, iclass 27, count 0 2006.285.20:49:50.12#ibcon#about to write, iclass 27, count 0 2006.285.20:49:50.12#ibcon#wrote, iclass 27, count 0 2006.285.20:49:50.12#ibcon#about to read 3, iclass 27, count 0 2006.285.20:49:50.15#ibcon#read 3, iclass 27, count 0 2006.285.20:49:50.15#ibcon#about to read 4, iclass 27, count 0 2006.285.20:49:50.15#ibcon#read 4, iclass 27, count 0 2006.285.20:49:50.15#ibcon#about to read 5, iclass 27, count 0 2006.285.20:49:50.15#ibcon#read 5, iclass 27, count 0 2006.285.20:49:50.15#ibcon#about to read 6, iclass 27, count 0 2006.285.20:49:50.15#ibcon#read 6, iclass 27, count 0 2006.285.20:49:50.15#ibcon#end of sib2, iclass 27, count 0 2006.285.20:49:50.15#ibcon#*after write, iclass 27, count 0 2006.285.20:49:50.15#ibcon#*before return 0, iclass 27, count 0 2006.285.20:49:50.15#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:49:50.15#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.20:49:50.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:49:50.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:49:50.15$vck44/vabw=wide 2006.285.20:49:50.15#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.20:49:50.15#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.20:49:50.15#ibcon#ireg 8 cls_cnt 0 2006.285.20:49:50.15#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:49:50.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:49:50.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:49:50.15#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:49:50.15#ibcon#first serial, iclass 29, count 0 2006.285.20:49:50.15#ibcon#enter sib2, iclass 29, count 0 2006.285.20:49:50.15#ibcon#flushed, iclass 29, count 0 2006.285.20:49:50.15#ibcon#about to write, iclass 29, count 0 2006.285.20:49:50.15#ibcon#wrote, iclass 29, count 0 2006.285.20:49:50.15#ibcon#about to read 3, iclass 29, count 0 2006.285.20:49:50.17#ibcon#read 3, iclass 29, count 0 2006.285.20:49:50.17#ibcon#about to read 4, iclass 29, count 0 2006.285.20:49:50.17#ibcon#read 4, iclass 29, count 0 2006.285.20:49:50.17#ibcon#about to read 5, iclass 29, count 0 2006.285.20:49:50.17#ibcon#read 5, iclass 29, count 0 2006.285.20:49:50.17#ibcon#about to read 6, iclass 29, count 0 2006.285.20:49:50.17#ibcon#read 6, iclass 29, count 0 2006.285.20:49:50.17#ibcon#end of sib2, iclass 29, count 0 2006.285.20:49:50.17#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:49:50.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:49:50.17#ibcon#[25=BW32\r\n] 2006.285.20:49:50.17#ibcon#*before write, iclass 29, count 0 2006.285.20:49:50.17#ibcon#enter sib2, iclass 29, count 0 2006.285.20:49:50.17#ibcon#flushed, iclass 29, count 0 2006.285.20:49:50.17#ibcon#about to write, iclass 29, count 0 2006.285.20:49:50.17#ibcon#wrote, iclass 29, count 0 2006.285.20:49:50.17#ibcon#about to read 3, iclass 29, count 0 2006.285.20:49:50.20#ibcon#read 3, iclass 29, count 0 2006.285.20:49:50.20#ibcon#about to read 4, iclass 29, count 0 2006.285.20:49:50.20#ibcon#read 4, iclass 29, count 0 2006.285.20:49:50.20#ibcon#about to read 5, iclass 29, count 0 2006.285.20:49:50.20#ibcon#read 5, iclass 29, count 0 2006.285.20:49:50.20#ibcon#about to read 6, iclass 29, count 0 2006.285.20:49:50.20#ibcon#read 6, iclass 29, count 0 2006.285.20:49:50.20#ibcon#end of sib2, iclass 29, count 0 2006.285.20:49:50.20#ibcon#*after write, iclass 29, count 0 2006.285.20:49:50.20#ibcon#*before return 0, iclass 29, count 0 2006.285.20:49:50.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:49:50.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.20:49:50.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:49:50.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:49:50.20$vck44/vbbw=wide 2006.285.20:49:50.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.20:49:50.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.20:49:50.20#ibcon#ireg 8 cls_cnt 0 2006.285.20:49:50.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:49:50.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:49:50.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:49:50.27#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:49:50.27#ibcon#first serial, iclass 31, count 0 2006.285.20:49:50.27#ibcon#enter sib2, iclass 31, count 0 2006.285.20:49:50.27#ibcon#flushed, iclass 31, count 0 2006.285.20:49:50.27#ibcon#about to write, iclass 31, count 0 2006.285.20:49:50.27#ibcon#wrote, iclass 31, count 0 2006.285.20:49:50.27#ibcon#about to read 3, iclass 31, count 0 2006.285.20:49:50.29#ibcon#read 3, iclass 31, count 0 2006.285.20:49:50.29#ibcon#about to read 4, iclass 31, count 0 2006.285.20:49:50.29#ibcon#read 4, iclass 31, count 0 2006.285.20:49:50.29#ibcon#about to read 5, iclass 31, count 0 2006.285.20:49:50.29#ibcon#read 5, iclass 31, count 0 2006.285.20:49:50.29#ibcon#about to read 6, iclass 31, count 0 2006.285.20:49:50.29#ibcon#read 6, iclass 31, count 0 2006.285.20:49:50.29#ibcon#end of sib2, iclass 31, count 0 2006.285.20:49:50.29#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:49:50.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:49:50.29#ibcon#[27=BW32\r\n] 2006.285.20:49:50.29#ibcon#*before write, iclass 31, count 0 2006.285.20:49:50.29#ibcon#enter sib2, iclass 31, count 0 2006.285.20:49:50.29#ibcon#flushed, iclass 31, count 0 2006.285.20:49:50.29#ibcon#about to write, iclass 31, count 0 2006.285.20:49:50.29#ibcon#wrote, iclass 31, count 0 2006.285.20:49:50.29#ibcon#about to read 3, iclass 31, count 0 2006.285.20:49:50.32#ibcon#read 3, iclass 31, count 0 2006.285.20:49:50.32#ibcon#about to read 4, iclass 31, count 0 2006.285.20:49:50.32#ibcon#read 4, iclass 31, count 0 2006.285.20:49:50.32#ibcon#about to read 5, iclass 31, count 0 2006.285.20:49:50.32#ibcon#read 5, iclass 31, count 0 2006.285.20:49:50.32#ibcon#about to read 6, iclass 31, count 0 2006.285.20:49:50.32#ibcon#read 6, iclass 31, count 0 2006.285.20:49:50.32#ibcon#end of sib2, iclass 31, count 0 2006.285.20:49:50.32#ibcon#*after write, iclass 31, count 0 2006.285.20:49:50.32#ibcon#*before return 0, iclass 31, count 0 2006.285.20:49:50.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:49:50.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:49:50.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:49:50.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:49:50.32$setupk4/ifdk4 2006.285.20:49:50.32$ifdk4/lo= 2006.285.20:49:50.32$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.20:49:50.32$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.20:49:50.32$ifdk4/patch= 2006.285.20:49:50.32$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.20:49:50.32$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.20:49:50.32$setupk4/!*+20s 2006.285.20:49:59.81#abcon#<5=/00 0.2 0.7 14.181001015.3\r\n> 2006.285.20:49:59.83#abcon#{5=INTERFACE CLEAR} 2006.285.20:49:59.89#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:50:02.14#trakl#Source acquired 2006.285.20:50:02.14#flagr#flagr/antenna,acquired 2006.285.20:50:04.33$setupk4/"tpicd 2006.285.20:50:04.33$setupk4/echo=off 2006.285.20:50:04.33$setupk4/xlog=off 2006.285.20:50:04.33:!2006.285.20:52:49 2006.285.20:52:49.00:preob 2006.285.20:52:49.13/onsource/TRACKING 2006.285.20:52:49.13:!2006.285.20:52:59 2006.285.20:52:59.00:"tape 2006.285.20:52:59.00:"st=record 2006.285.20:52:59.00:data_valid=on 2006.285.20:52:59.00:midob 2006.285.20:52:59.13/onsource/TRACKING 2006.285.20:52:59.13/wx/14.21,1015.4,100 2006.285.20:52:59.19/cable/+6.5091E-03 2006.285.20:53:00.28/va/01,07,usb,yes,32,35 2006.285.20:53:00.28/va/02,06,usb,yes,32,33 2006.285.20:53:00.28/va/03,07,usb,yes,32,34 2006.285.20:53:00.28/va/04,06,usb,yes,33,35 2006.285.20:53:00.28/va/05,03,usb,yes,33,33 2006.285.20:53:00.28/va/06,04,usb,yes,30,29 2006.285.20:53:00.28/va/07,04,usb,yes,30,31 2006.285.20:53:00.28/va/08,03,usb,yes,31,37 2006.285.20:53:00.51/valo/01,524.99,yes,locked 2006.285.20:53:00.51/valo/02,534.99,yes,locked 2006.285.20:53:00.51/valo/03,564.99,yes,locked 2006.285.20:53:00.51/valo/04,624.99,yes,locked 2006.285.20:53:00.51/valo/05,734.99,yes,locked 2006.285.20:53:00.51/valo/06,814.99,yes,locked 2006.285.20:53:00.51/valo/07,864.99,yes,locked 2006.285.20:53:00.51/valo/08,884.99,yes,locked 2006.285.20:53:01.60/vb/01,04,usb,yes,29,27 2006.285.20:53:01.60/vb/02,05,usb,yes,28,27 2006.285.20:53:01.60/vb/03,04,usb,yes,29,32 2006.285.20:53:01.60/vb/04,05,usb,yes,29,28 2006.285.20:53:01.60/vb/05,04,usb,yes,25,28 2006.285.20:53:01.60/vb/06,03,usb,yes,37,33 2006.285.20:53:01.60/vb/07,04,usb,yes,29,29 2006.285.20:53:01.60/vb/08,04,usb,yes,27,30 2006.285.20:53:01.83/vblo/01,629.99,yes,locked 2006.285.20:53:01.83/vblo/02,634.99,yes,locked 2006.285.20:53:01.83/vblo/03,649.99,yes,locked 2006.285.20:53:01.83/vblo/04,679.99,yes,locked 2006.285.20:53:01.83/vblo/05,709.99,yes,locked 2006.285.20:53:01.83/vblo/06,719.99,yes,locked 2006.285.20:53:01.83/vblo/07,734.99,yes,locked 2006.285.20:53:01.83/vblo/08,744.99,yes,locked 2006.285.20:53:01.98/vabw/8 2006.285.20:53:02.13/vbbw/8 2006.285.20:53:02.31/xfe/off,on,12.0 2006.285.20:53:02.68/ifatt/23,28,28,28 2006.285.20:53:03.07/fmout-gps/S +2.81E-07 2006.285.20:53:03.09:!2006.285.20:57:49 2006.285.20:57:49.00:data_valid=off 2006.285.20:57:49.00:"et 2006.285.20:57:49.00:!+3s 2006.285.20:57:52.01:"tape 2006.285.20:57:52.01:postob 2006.285.20:57:52.22/cable/+6.5108E-03 2006.285.20:57:52.22/wx/14.21,1015.4,100 2006.285.20:57:53.07/fmout-gps/S +2.78E-07 2006.285.20:57:53.07:scan_name=285-2102,jd0610,50 2006.285.20:57:53.07:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.285.20:57:54.14#flagr#flagr/antenna,new-source 2006.285.20:57:54.14:checkk5 2006.285.20:57:54.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.20:57:55.01/chk_autoobs//k5ts2/ autoobs is running! 2006.285.20:57:55.42/chk_autoobs//k5ts3/ autoobs is running! 2006.285.20:57:56.10/chk_autoobs//k5ts4/ autoobs is running! 2006.285.20:57:56.54/chk_obsdata//k5ts1/T2852052??a.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.285.20:57:56.96/chk_obsdata//k5ts2/T2852052??b.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.285.20:57:57.35/chk_obsdata//k5ts3/T2852052??c.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.285.20:57:57.77/chk_obsdata//k5ts4/T2852052??d.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.285.20:57:58.76/k5log//k5ts1_log_newline 2006.285.20:57:59.47/k5log//k5ts2_log_newline 2006.285.20:58:00.28/k5log//k5ts3_log_newline 2006.285.20:58:01.25/k5log//k5ts4_log_newline 2006.285.20:58:01.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.20:58:01.27:setupk4=1 2006.285.20:58:01.28$setupk4/echo=on 2006.285.20:58:01.28$setupk4/pcalon 2006.285.20:58:01.28$pcalon/"no phase cal control is implemented here 2006.285.20:58:01.28$setupk4/"tpicd=stop 2006.285.20:58:01.28$setupk4/"rec=synch_on 2006.285.20:58:01.28$setupk4/"rec_mode=128 2006.285.20:58:01.28$setupk4/!* 2006.285.20:58:01.28$setupk4/recpk4 2006.285.20:58:01.28$recpk4/recpatch= 2006.285.20:58:01.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.20:58:01.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.20:58:01.28$setupk4/vck44 2006.285.20:58:01.28$vck44/valo=1,524.99 2006.285.20:58:01.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.20:58:01.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.20:58:01.28#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:01.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:58:01.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:58:01.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:58:01.28#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:58:01.28#ibcon#first serial, iclass 5, count 0 2006.285.20:58:01.28#ibcon#enter sib2, iclass 5, count 0 2006.285.20:58:01.28#ibcon#flushed, iclass 5, count 0 2006.285.20:58:01.28#ibcon#about to write, iclass 5, count 0 2006.285.20:58:01.28#ibcon#wrote, iclass 5, count 0 2006.285.20:58:01.28#ibcon#about to read 3, iclass 5, count 0 2006.285.20:58:01.30#ibcon#read 3, iclass 5, count 0 2006.285.20:58:01.30#ibcon#about to read 4, iclass 5, count 0 2006.285.20:58:01.30#ibcon#read 4, iclass 5, count 0 2006.285.20:58:01.30#ibcon#about to read 5, iclass 5, count 0 2006.285.20:58:01.30#ibcon#read 5, iclass 5, count 0 2006.285.20:58:01.30#ibcon#about to read 6, iclass 5, count 0 2006.285.20:58:01.30#ibcon#read 6, iclass 5, count 0 2006.285.20:58:01.30#ibcon#end of sib2, iclass 5, count 0 2006.285.20:58:01.30#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:58:01.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:58:01.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.20:58:01.30#ibcon#*before write, iclass 5, count 0 2006.285.20:58:01.30#ibcon#enter sib2, iclass 5, count 0 2006.285.20:58:01.30#ibcon#flushed, iclass 5, count 0 2006.285.20:58:01.30#ibcon#about to write, iclass 5, count 0 2006.285.20:58:01.30#ibcon#wrote, iclass 5, count 0 2006.285.20:58:01.30#ibcon#about to read 3, iclass 5, count 0 2006.285.20:58:01.35#ibcon#read 3, iclass 5, count 0 2006.285.20:58:01.35#ibcon#about to read 4, iclass 5, count 0 2006.285.20:58:01.35#ibcon#read 4, iclass 5, count 0 2006.285.20:58:01.35#ibcon#about to read 5, iclass 5, count 0 2006.285.20:58:01.35#ibcon#read 5, iclass 5, count 0 2006.285.20:58:01.35#ibcon#about to read 6, iclass 5, count 0 2006.285.20:58:01.35#ibcon#read 6, iclass 5, count 0 2006.285.20:58:01.35#ibcon#end of sib2, iclass 5, count 0 2006.285.20:58:01.35#ibcon#*after write, iclass 5, count 0 2006.285.20:58:01.35#ibcon#*before return 0, iclass 5, count 0 2006.285.20:58:01.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:58:01.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:58:01.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:58:01.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:58:01.35$vck44/va=1,7 2006.285.20:58:01.35#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.20:58:01.35#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.20:58:01.35#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:01.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:58:01.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:58:01.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:58:01.35#ibcon#enter wrdev, iclass 7, count 2 2006.285.20:58:01.35#ibcon#first serial, iclass 7, count 2 2006.285.20:58:01.35#ibcon#enter sib2, iclass 7, count 2 2006.285.20:58:01.35#ibcon#flushed, iclass 7, count 2 2006.285.20:58:01.35#ibcon#about to write, iclass 7, count 2 2006.285.20:58:01.35#ibcon#wrote, iclass 7, count 2 2006.285.20:58:01.35#ibcon#about to read 3, iclass 7, count 2 2006.285.20:58:01.37#ibcon#read 3, iclass 7, count 2 2006.285.20:58:01.37#ibcon#about to read 4, iclass 7, count 2 2006.285.20:58:01.37#ibcon#read 4, iclass 7, count 2 2006.285.20:58:01.37#ibcon#about to read 5, iclass 7, count 2 2006.285.20:58:01.37#ibcon#read 5, iclass 7, count 2 2006.285.20:58:01.37#ibcon#about to read 6, iclass 7, count 2 2006.285.20:58:01.37#ibcon#read 6, iclass 7, count 2 2006.285.20:58:01.37#ibcon#end of sib2, iclass 7, count 2 2006.285.20:58:01.37#ibcon#*mode == 0, iclass 7, count 2 2006.285.20:58:01.37#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.20:58:01.37#ibcon#[25=AT01-07\r\n] 2006.285.20:58:01.37#ibcon#*before write, iclass 7, count 2 2006.285.20:58:01.37#ibcon#enter sib2, iclass 7, count 2 2006.285.20:58:01.37#ibcon#flushed, iclass 7, count 2 2006.285.20:58:01.37#ibcon#about to write, iclass 7, count 2 2006.285.20:58:01.37#ibcon#wrote, iclass 7, count 2 2006.285.20:58:01.37#ibcon#about to read 3, iclass 7, count 2 2006.285.20:58:01.40#ibcon#read 3, iclass 7, count 2 2006.285.20:58:01.40#ibcon#about to read 4, iclass 7, count 2 2006.285.20:58:01.40#ibcon#read 4, iclass 7, count 2 2006.285.20:58:01.40#ibcon#about to read 5, iclass 7, count 2 2006.285.20:58:01.40#ibcon#read 5, iclass 7, count 2 2006.285.20:58:01.40#ibcon#about to read 6, iclass 7, count 2 2006.285.20:58:01.40#ibcon#read 6, iclass 7, count 2 2006.285.20:58:01.40#ibcon#end of sib2, iclass 7, count 2 2006.285.20:58:01.40#ibcon#*after write, iclass 7, count 2 2006.285.20:58:01.40#ibcon#*before return 0, iclass 7, count 2 2006.285.20:58:01.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:58:01.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:58:01.40#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.20:58:01.40#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:01.40#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:58:01.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:58:01.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:58:01.52#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:58:01.52#ibcon#first serial, iclass 7, count 0 2006.285.20:58:01.52#ibcon#enter sib2, iclass 7, count 0 2006.285.20:58:01.52#ibcon#flushed, iclass 7, count 0 2006.285.20:58:01.52#ibcon#about to write, iclass 7, count 0 2006.285.20:58:01.52#ibcon#wrote, iclass 7, count 0 2006.285.20:58:01.52#ibcon#about to read 3, iclass 7, count 0 2006.285.20:58:01.54#ibcon#read 3, iclass 7, count 0 2006.285.20:58:01.54#ibcon#about to read 4, iclass 7, count 0 2006.285.20:58:01.54#ibcon#read 4, iclass 7, count 0 2006.285.20:58:01.54#ibcon#about to read 5, iclass 7, count 0 2006.285.20:58:01.54#ibcon#read 5, iclass 7, count 0 2006.285.20:58:01.54#ibcon#about to read 6, iclass 7, count 0 2006.285.20:58:01.54#ibcon#read 6, iclass 7, count 0 2006.285.20:58:01.54#ibcon#end of sib2, iclass 7, count 0 2006.285.20:58:01.54#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:58:01.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:58:01.54#ibcon#[25=USB\r\n] 2006.285.20:58:01.54#ibcon#*before write, iclass 7, count 0 2006.285.20:58:01.54#ibcon#enter sib2, iclass 7, count 0 2006.285.20:58:01.54#ibcon#flushed, iclass 7, count 0 2006.285.20:58:01.54#ibcon#about to write, iclass 7, count 0 2006.285.20:58:01.54#ibcon#wrote, iclass 7, count 0 2006.285.20:58:01.54#ibcon#about to read 3, iclass 7, count 0 2006.285.20:58:01.57#ibcon#read 3, iclass 7, count 0 2006.285.20:58:01.57#ibcon#about to read 4, iclass 7, count 0 2006.285.20:58:01.57#ibcon#read 4, iclass 7, count 0 2006.285.20:58:01.57#ibcon#about to read 5, iclass 7, count 0 2006.285.20:58:01.57#ibcon#read 5, iclass 7, count 0 2006.285.20:58:01.57#ibcon#about to read 6, iclass 7, count 0 2006.285.20:58:01.57#ibcon#read 6, iclass 7, count 0 2006.285.20:58:01.57#ibcon#end of sib2, iclass 7, count 0 2006.285.20:58:01.57#ibcon#*after write, iclass 7, count 0 2006.285.20:58:01.57#ibcon#*before return 0, iclass 7, count 0 2006.285.20:58:01.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:58:01.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:58:01.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:58:01.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:58:01.57$vck44/valo=2,534.99 2006.285.20:58:01.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.20:58:01.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.20:58:01.57#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:01.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:58:01.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:58:01.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:58:01.57#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:58:01.57#ibcon#first serial, iclass 11, count 0 2006.285.20:58:01.57#ibcon#enter sib2, iclass 11, count 0 2006.285.20:58:01.57#ibcon#flushed, iclass 11, count 0 2006.285.20:58:01.57#ibcon#about to write, iclass 11, count 0 2006.285.20:58:01.57#ibcon#wrote, iclass 11, count 0 2006.285.20:58:01.57#ibcon#about to read 3, iclass 11, count 0 2006.285.20:58:01.59#ibcon#read 3, iclass 11, count 0 2006.285.20:58:02.47#ibcon#about to read 4, iclass 11, count 0 2006.285.20:58:02.47#ibcon#read 4, iclass 11, count 0 2006.285.20:58:02.47#ibcon#about to read 5, iclass 11, count 0 2006.285.20:58:02.47#ibcon#read 5, iclass 11, count 0 2006.285.20:58:02.47#ibcon#about to read 6, iclass 11, count 0 2006.285.20:58:02.47#ibcon#read 6, iclass 11, count 0 2006.285.20:58:02.47#ibcon#end of sib2, iclass 11, count 0 2006.285.20:58:02.47#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:58:02.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:58:02.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.20:58:02.47#ibcon#*before write, iclass 11, count 0 2006.285.20:58:02.47#ibcon#enter sib2, iclass 11, count 0 2006.285.20:58:02.47#ibcon#flushed, iclass 11, count 0 2006.285.20:58:02.47#ibcon#about to write, iclass 11, count 0 2006.285.20:58:02.47#ibcon#wrote, iclass 11, count 0 2006.285.20:58:02.47#ibcon#about to read 3, iclass 11, count 0 2006.285.20:58:02.51#ibcon#read 3, iclass 11, count 0 2006.285.20:58:02.51#ibcon#about to read 4, iclass 11, count 0 2006.285.20:58:02.51#ibcon#read 4, iclass 11, count 0 2006.285.20:58:02.51#ibcon#about to read 5, iclass 11, count 0 2006.285.20:58:02.51#ibcon#read 5, iclass 11, count 0 2006.285.20:58:02.51#ibcon#about to read 6, iclass 11, count 0 2006.285.20:58:02.51#ibcon#read 6, iclass 11, count 0 2006.285.20:58:02.51#ibcon#end of sib2, iclass 11, count 0 2006.285.20:58:02.51#ibcon#*after write, iclass 11, count 0 2006.285.20:58:02.51#ibcon#*before return 0, iclass 11, count 0 2006.285.20:58:02.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:58:02.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:58:02.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:58:02.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:58:02.51$vck44/va=2,6 2006.285.20:58:02.51#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.20:58:02.51#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.20:58:02.51#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:02.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:58:02.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:58:02.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:58:02.51#ibcon#enter wrdev, iclass 13, count 2 2006.285.20:58:02.51#ibcon#first serial, iclass 13, count 2 2006.285.20:58:02.51#ibcon#enter sib2, iclass 13, count 2 2006.285.20:58:02.51#ibcon#flushed, iclass 13, count 2 2006.285.20:58:02.51#ibcon#about to write, iclass 13, count 2 2006.285.20:58:02.51#ibcon#wrote, iclass 13, count 2 2006.285.20:58:02.51#ibcon#about to read 3, iclass 13, count 2 2006.285.20:58:02.53#ibcon#read 3, iclass 13, count 2 2006.285.20:58:02.53#ibcon#about to read 4, iclass 13, count 2 2006.285.20:58:02.53#ibcon#read 4, iclass 13, count 2 2006.285.20:58:02.53#ibcon#about to read 5, iclass 13, count 2 2006.285.20:58:02.53#ibcon#read 5, iclass 13, count 2 2006.285.20:58:02.53#ibcon#about to read 6, iclass 13, count 2 2006.285.20:58:02.53#ibcon#read 6, iclass 13, count 2 2006.285.20:58:02.53#ibcon#end of sib2, iclass 13, count 2 2006.285.20:58:02.53#ibcon#*mode == 0, iclass 13, count 2 2006.285.20:58:02.53#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.20:58:02.53#ibcon#[25=AT02-06\r\n] 2006.285.20:58:02.53#ibcon#*before write, iclass 13, count 2 2006.285.20:58:02.53#ibcon#enter sib2, iclass 13, count 2 2006.285.20:58:02.53#ibcon#flushed, iclass 13, count 2 2006.285.20:58:02.53#ibcon#about to write, iclass 13, count 2 2006.285.20:58:02.53#ibcon#wrote, iclass 13, count 2 2006.285.20:58:02.53#ibcon#about to read 3, iclass 13, count 2 2006.285.20:58:02.56#ibcon#read 3, iclass 13, count 2 2006.285.20:58:02.56#ibcon#about to read 4, iclass 13, count 2 2006.285.20:58:02.56#ibcon#read 4, iclass 13, count 2 2006.285.20:58:02.56#ibcon#about to read 5, iclass 13, count 2 2006.285.20:58:02.56#ibcon#read 5, iclass 13, count 2 2006.285.20:58:02.56#ibcon#about to read 6, iclass 13, count 2 2006.285.20:58:02.56#ibcon#read 6, iclass 13, count 2 2006.285.20:58:02.56#ibcon#end of sib2, iclass 13, count 2 2006.285.20:58:02.56#ibcon#*after write, iclass 13, count 2 2006.285.20:58:02.56#ibcon#*before return 0, iclass 13, count 2 2006.285.20:58:02.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:58:02.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:58:02.56#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.20:58:02.56#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:02.56#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:58:02.68#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:58:02.68#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:58:02.68#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:58:02.68#ibcon#first serial, iclass 13, count 0 2006.285.20:58:02.68#ibcon#enter sib2, iclass 13, count 0 2006.285.20:58:02.68#ibcon#flushed, iclass 13, count 0 2006.285.20:58:02.68#ibcon#about to write, iclass 13, count 0 2006.285.20:58:02.68#ibcon#wrote, iclass 13, count 0 2006.285.20:58:02.68#ibcon#about to read 3, iclass 13, count 0 2006.285.20:58:02.70#ibcon#read 3, iclass 13, count 0 2006.285.20:58:02.70#ibcon#about to read 4, iclass 13, count 0 2006.285.20:58:02.70#ibcon#read 4, iclass 13, count 0 2006.285.20:58:02.70#ibcon#about to read 5, iclass 13, count 0 2006.285.20:58:02.70#ibcon#read 5, iclass 13, count 0 2006.285.20:58:02.70#ibcon#about to read 6, iclass 13, count 0 2006.285.20:58:02.70#ibcon#read 6, iclass 13, count 0 2006.285.20:58:02.70#ibcon#end of sib2, iclass 13, count 0 2006.285.20:58:02.70#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:58:02.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:58:02.70#ibcon#[25=USB\r\n] 2006.285.20:58:02.70#ibcon#*before write, iclass 13, count 0 2006.285.20:58:02.70#ibcon#enter sib2, iclass 13, count 0 2006.285.20:58:02.70#ibcon#flushed, iclass 13, count 0 2006.285.20:58:02.70#ibcon#about to write, iclass 13, count 0 2006.285.20:58:02.70#ibcon#wrote, iclass 13, count 0 2006.285.20:58:02.70#ibcon#about to read 3, iclass 13, count 0 2006.285.20:58:02.73#ibcon#read 3, iclass 13, count 0 2006.285.20:58:02.73#ibcon#about to read 4, iclass 13, count 0 2006.285.20:58:02.73#ibcon#read 4, iclass 13, count 0 2006.285.20:58:02.73#ibcon#about to read 5, iclass 13, count 0 2006.285.20:58:02.73#ibcon#read 5, iclass 13, count 0 2006.285.20:58:02.73#ibcon#about to read 6, iclass 13, count 0 2006.285.20:58:02.73#ibcon#read 6, iclass 13, count 0 2006.285.20:58:02.73#ibcon#end of sib2, iclass 13, count 0 2006.285.20:58:02.73#ibcon#*after write, iclass 13, count 0 2006.285.20:58:02.73#ibcon#*before return 0, iclass 13, count 0 2006.285.20:58:02.73#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:58:02.73#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:58:02.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:58:02.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:58:02.73$vck44/valo=3,564.99 2006.285.20:58:02.73#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.20:58:02.73#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.20:58:02.73#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:02.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:58:02.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:58:02.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:58:02.73#ibcon#enter wrdev, iclass 15, count 0 2006.285.20:58:02.73#ibcon#first serial, iclass 15, count 0 2006.285.20:58:02.73#ibcon#enter sib2, iclass 15, count 0 2006.285.20:58:02.73#ibcon#flushed, iclass 15, count 0 2006.285.20:58:02.73#ibcon#about to write, iclass 15, count 0 2006.285.20:58:02.73#ibcon#wrote, iclass 15, count 0 2006.285.20:58:02.73#ibcon#about to read 3, iclass 15, count 0 2006.285.20:58:02.75#ibcon#read 3, iclass 15, count 0 2006.285.20:58:02.75#ibcon#about to read 4, iclass 15, count 0 2006.285.20:58:02.75#ibcon#read 4, iclass 15, count 0 2006.285.20:58:02.75#ibcon#about to read 5, iclass 15, count 0 2006.285.20:58:02.75#ibcon#read 5, iclass 15, count 0 2006.285.20:58:02.75#ibcon#about to read 6, iclass 15, count 0 2006.285.20:58:02.75#ibcon#read 6, iclass 15, count 0 2006.285.20:58:02.75#ibcon#end of sib2, iclass 15, count 0 2006.285.20:58:02.75#ibcon#*mode == 0, iclass 15, count 0 2006.285.20:58:02.75#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.20:58:02.75#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.20:58:02.75#ibcon#*before write, iclass 15, count 0 2006.285.20:58:02.75#ibcon#enter sib2, iclass 15, count 0 2006.285.20:58:02.75#ibcon#flushed, iclass 15, count 0 2006.285.20:58:02.75#ibcon#about to write, iclass 15, count 0 2006.285.20:58:02.75#ibcon#wrote, iclass 15, count 0 2006.285.20:58:02.75#ibcon#about to read 3, iclass 15, count 0 2006.285.20:58:02.79#ibcon#read 3, iclass 15, count 0 2006.285.20:58:02.79#ibcon#about to read 4, iclass 15, count 0 2006.285.20:58:02.79#ibcon#read 4, iclass 15, count 0 2006.285.20:58:02.79#ibcon#about to read 5, iclass 15, count 0 2006.285.20:58:02.79#ibcon#read 5, iclass 15, count 0 2006.285.20:58:02.79#ibcon#about to read 6, iclass 15, count 0 2006.285.20:58:02.79#ibcon#read 6, iclass 15, count 0 2006.285.20:58:02.79#ibcon#end of sib2, iclass 15, count 0 2006.285.20:58:02.79#ibcon#*after write, iclass 15, count 0 2006.285.20:58:02.79#ibcon#*before return 0, iclass 15, count 0 2006.285.20:58:02.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:58:02.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:58:02.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.20:58:02.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.20:58:02.79$vck44/va=3,7 2006.285.20:58:02.79#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.20:58:02.79#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.20:58:02.79#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:02.79#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:58:02.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:58:02.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:58:02.85#ibcon#enter wrdev, iclass 17, count 2 2006.285.20:58:02.85#ibcon#first serial, iclass 17, count 2 2006.285.20:58:02.85#ibcon#enter sib2, iclass 17, count 2 2006.285.20:58:02.85#ibcon#flushed, iclass 17, count 2 2006.285.20:58:02.85#ibcon#about to write, iclass 17, count 2 2006.285.20:58:02.85#ibcon#wrote, iclass 17, count 2 2006.285.20:58:02.85#ibcon#about to read 3, iclass 17, count 2 2006.285.20:58:02.87#ibcon#read 3, iclass 17, count 2 2006.285.20:58:02.87#ibcon#about to read 4, iclass 17, count 2 2006.285.20:58:02.87#ibcon#read 4, iclass 17, count 2 2006.285.20:58:02.87#ibcon#about to read 5, iclass 17, count 2 2006.285.20:58:02.87#ibcon#read 5, iclass 17, count 2 2006.285.20:58:02.87#ibcon#about to read 6, iclass 17, count 2 2006.285.20:58:02.87#ibcon#read 6, iclass 17, count 2 2006.285.20:58:02.87#ibcon#end of sib2, iclass 17, count 2 2006.285.20:58:02.87#ibcon#*mode == 0, iclass 17, count 2 2006.285.20:58:02.87#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.20:58:02.87#ibcon#[25=AT03-07\r\n] 2006.285.20:58:02.87#ibcon#*before write, iclass 17, count 2 2006.285.20:58:02.87#ibcon#enter sib2, iclass 17, count 2 2006.285.20:58:02.87#ibcon#flushed, iclass 17, count 2 2006.285.20:58:02.87#ibcon#about to write, iclass 17, count 2 2006.285.20:58:02.87#ibcon#wrote, iclass 17, count 2 2006.285.20:58:02.87#ibcon#about to read 3, iclass 17, count 2 2006.285.20:58:02.90#ibcon#read 3, iclass 17, count 2 2006.285.20:58:02.90#ibcon#about to read 4, iclass 17, count 2 2006.285.20:58:02.90#ibcon#read 4, iclass 17, count 2 2006.285.20:58:02.90#ibcon#about to read 5, iclass 17, count 2 2006.285.20:58:02.90#ibcon#read 5, iclass 17, count 2 2006.285.20:58:02.90#ibcon#about to read 6, iclass 17, count 2 2006.285.20:58:02.90#ibcon#read 6, iclass 17, count 2 2006.285.20:58:02.90#ibcon#end of sib2, iclass 17, count 2 2006.285.20:58:02.90#ibcon#*after write, iclass 17, count 2 2006.285.20:58:02.90#ibcon#*before return 0, iclass 17, count 2 2006.285.20:58:02.90#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:58:02.90#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:58:02.90#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.20:58:02.90#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:02.90#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:58:03.02#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:58:03.02#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:58:03.02#ibcon#enter wrdev, iclass 17, count 0 2006.285.20:58:03.02#ibcon#first serial, iclass 17, count 0 2006.285.20:58:03.02#ibcon#enter sib2, iclass 17, count 0 2006.285.20:58:03.02#ibcon#flushed, iclass 17, count 0 2006.285.20:58:03.02#ibcon#about to write, iclass 17, count 0 2006.285.20:58:03.02#ibcon#wrote, iclass 17, count 0 2006.285.20:58:03.02#ibcon#about to read 3, iclass 17, count 0 2006.285.20:58:03.04#ibcon#read 3, iclass 17, count 0 2006.285.20:58:03.35#ibcon#about to read 4, iclass 17, count 0 2006.285.20:58:03.35#ibcon#read 4, iclass 17, count 0 2006.285.20:58:03.35#ibcon#about to read 5, iclass 17, count 0 2006.285.20:58:03.35#ibcon#read 5, iclass 17, count 0 2006.285.20:58:03.35#ibcon#about to read 6, iclass 17, count 0 2006.285.20:58:03.35#ibcon#read 6, iclass 17, count 0 2006.285.20:58:03.35#ibcon#end of sib2, iclass 17, count 0 2006.285.20:58:03.35#ibcon#*mode == 0, iclass 17, count 0 2006.285.20:58:03.35#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.20:58:03.35#ibcon#[25=USB\r\n] 2006.285.20:58:03.35#ibcon#*before write, iclass 17, count 0 2006.285.20:58:03.35#ibcon#enter sib2, iclass 17, count 0 2006.285.20:58:03.35#ibcon#flushed, iclass 17, count 0 2006.285.20:58:03.35#ibcon#about to write, iclass 17, count 0 2006.285.20:58:03.35#ibcon#wrote, iclass 17, count 0 2006.285.20:58:03.35#ibcon#about to read 3, iclass 17, count 0 2006.285.20:58:03.38#ibcon#read 3, iclass 17, count 0 2006.285.20:58:03.38#ibcon#about to read 4, iclass 17, count 0 2006.285.20:58:03.38#ibcon#read 4, iclass 17, count 0 2006.285.20:58:03.38#ibcon#about to read 5, iclass 17, count 0 2006.285.20:58:03.38#ibcon#read 5, iclass 17, count 0 2006.285.20:58:03.38#ibcon#about to read 6, iclass 17, count 0 2006.285.20:58:03.38#ibcon#read 6, iclass 17, count 0 2006.285.20:58:03.38#ibcon#end of sib2, iclass 17, count 0 2006.285.20:58:03.38#ibcon#*after write, iclass 17, count 0 2006.285.20:58:03.38#ibcon#*before return 0, iclass 17, count 0 2006.285.20:58:03.38#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:58:03.38#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:58:03.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.20:58:03.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.20:58:03.38$vck44/valo=4,624.99 2006.285.20:58:03.38#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.20:58:03.38#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.20:58:03.38#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:03.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:58:03.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:58:03.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:58:03.38#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:58:03.38#ibcon#first serial, iclass 19, count 0 2006.285.20:58:03.38#ibcon#enter sib2, iclass 19, count 0 2006.285.20:58:03.38#ibcon#flushed, iclass 19, count 0 2006.285.20:58:03.38#ibcon#about to write, iclass 19, count 0 2006.285.20:58:03.38#ibcon#wrote, iclass 19, count 0 2006.285.20:58:03.38#ibcon#about to read 3, iclass 19, count 0 2006.285.20:58:03.40#ibcon#read 3, iclass 19, count 0 2006.285.20:58:03.40#ibcon#about to read 4, iclass 19, count 0 2006.285.20:58:03.40#ibcon#read 4, iclass 19, count 0 2006.285.20:58:03.40#ibcon#about to read 5, iclass 19, count 0 2006.285.20:58:03.40#ibcon#read 5, iclass 19, count 0 2006.285.20:58:03.40#ibcon#about to read 6, iclass 19, count 0 2006.285.20:58:03.40#ibcon#read 6, iclass 19, count 0 2006.285.20:58:03.40#ibcon#end of sib2, iclass 19, count 0 2006.285.20:58:03.40#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:58:03.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:58:03.40#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.20:58:03.40#ibcon#*before write, iclass 19, count 0 2006.285.20:58:03.40#ibcon#enter sib2, iclass 19, count 0 2006.285.20:58:03.40#ibcon#flushed, iclass 19, count 0 2006.285.20:58:03.40#ibcon#about to write, iclass 19, count 0 2006.285.20:58:03.40#ibcon#wrote, iclass 19, count 0 2006.285.20:58:03.40#ibcon#about to read 3, iclass 19, count 0 2006.285.20:58:03.44#ibcon#read 3, iclass 19, count 0 2006.285.20:58:03.44#ibcon#about to read 4, iclass 19, count 0 2006.285.20:58:03.44#ibcon#read 4, iclass 19, count 0 2006.285.20:58:03.44#ibcon#about to read 5, iclass 19, count 0 2006.285.20:58:03.44#ibcon#read 5, iclass 19, count 0 2006.285.20:58:03.44#ibcon#about to read 6, iclass 19, count 0 2006.285.20:58:03.44#ibcon#read 6, iclass 19, count 0 2006.285.20:58:03.44#ibcon#end of sib2, iclass 19, count 0 2006.285.20:58:03.44#ibcon#*after write, iclass 19, count 0 2006.285.20:58:03.44#ibcon#*before return 0, iclass 19, count 0 2006.285.20:58:03.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:58:03.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:58:03.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:58:03.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:58:03.44$vck44/va=4,6 2006.285.20:58:03.44#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.20:58:03.44#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.20:58:03.44#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:03.44#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:58:03.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:58:03.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:58:03.50#ibcon#enter wrdev, iclass 21, count 2 2006.285.20:58:03.50#ibcon#first serial, iclass 21, count 2 2006.285.20:58:03.50#ibcon#enter sib2, iclass 21, count 2 2006.285.20:58:03.50#ibcon#flushed, iclass 21, count 2 2006.285.20:58:03.50#ibcon#about to write, iclass 21, count 2 2006.285.20:58:03.50#ibcon#wrote, iclass 21, count 2 2006.285.20:58:03.50#ibcon#about to read 3, iclass 21, count 2 2006.285.20:58:03.52#ibcon#read 3, iclass 21, count 2 2006.285.20:58:03.52#ibcon#about to read 4, iclass 21, count 2 2006.285.20:58:03.52#ibcon#read 4, iclass 21, count 2 2006.285.20:58:03.52#ibcon#about to read 5, iclass 21, count 2 2006.285.20:58:03.52#ibcon#read 5, iclass 21, count 2 2006.285.20:58:03.52#ibcon#about to read 6, iclass 21, count 2 2006.285.20:58:03.52#ibcon#read 6, iclass 21, count 2 2006.285.20:58:03.52#ibcon#end of sib2, iclass 21, count 2 2006.285.20:58:03.52#ibcon#*mode == 0, iclass 21, count 2 2006.285.20:58:03.52#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.20:58:03.52#ibcon#[25=AT04-06\r\n] 2006.285.20:58:03.52#ibcon#*before write, iclass 21, count 2 2006.285.20:58:03.52#ibcon#enter sib2, iclass 21, count 2 2006.285.20:58:03.52#ibcon#flushed, iclass 21, count 2 2006.285.20:58:03.52#ibcon#about to write, iclass 21, count 2 2006.285.20:58:03.52#ibcon#wrote, iclass 21, count 2 2006.285.20:58:03.52#ibcon#about to read 3, iclass 21, count 2 2006.285.20:58:03.55#ibcon#read 3, iclass 21, count 2 2006.285.20:58:03.55#ibcon#about to read 4, iclass 21, count 2 2006.285.20:58:03.55#ibcon#read 4, iclass 21, count 2 2006.285.20:58:03.55#ibcon#about to read 5, iclass 21, count 2 2006.285.20:58:03.55#ibcon#read 5, iclass 21, count 2 2006.285.20:58:03.55#ibcon#about to read 6, iclass 21, count 2 2006.285.20:58:03.55#ibcon#read 6, iclass 21, count 2 2006.285.20:58:03.55#ibcon#end of sib2, iclass 21, count 2 2006.285.20:58:03.55#ibcon#*after write, iclass 21, count 2 2006.285.20:58:03.55#ibcon#*before return 0, iclass 21, count 2 2006.285.20:58:03.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:58:03.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:58:03.55#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.20:58:03.55#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:03.55#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:58:03.67#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:58:03.67#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:58:03.67#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:58:03.67#ibcon#first serial, iclass 21, count 0 2006.285.20:58:03.67#ibcon#enter sib2, iclass 21, count 0 2006.285.20:58:03.67#ibcon#flushed, iclass 21, count 0 2006.285.20:58:03.67#ibcon#about to write, iclass 21, count 0 2006.285.20:58:03.67#ibcon#wrote, iclass 21, count 0 2006.285.20:58:03.67#ibcon#about to read 3, iclass 21, count 0 2006.285.20:58:03.69#ibcon#read 3, iclass 21, count 0 2006.285.20:58:03.69#ibcon#about to read 4, iclass 21, count 0 2006.285.20:58:03.69#ibcon#read 4, iclass 21, count 0 2006.285.20:58:03.69#ibcon#about to read 5, iclass 21, count 0 2006.285.20:58:03.69#ibcon#read 5, iclass 21, count 0 2006.285.20:58:03.69#ibcon#about to read 6, iclass 21, count 0 2006.285.20:58:03.69#ibcon#read 6, iclass 21, count 0 2006.285.20:58:03.69#ibcon#end of sib2, iclass 21, count 0 2006.285.20:58:03.69#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:58:03.69#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:58:03.69#ibcon#[25=USB\r\n] 2006.285.20:58:03.69#ibcon#*before write, iclass 21, count 0 2006.285.20:58:03.69#ibcon#enter sib2, iclass 21, count 0 2006.285.20:58:03.69#ibcon#flushed, iclass 21, count 0 2006.285.20:58:03.69#ibcon#about to write, iclass 21, count 0 2006.285.20:58:03.69#ibcon#wrote, iclass 21, count 0 2006.285.20:58:03.69#ibcon#about to read 3, iclass 21, count 0 2006.285.20:58:03.72#ibcon#read 3, iclass 21, count 0 2006.285.20:58:03.72#ibcon#about to read 4, iclass 21, count 0 2006.285.20:58:03.72#ibcon#read 4, iclass 21, count 0 2006.285.20:58:03.72#ibcon#about to read 5, iclass 21, count 0 2006.285.20:58:03.72#ibcon#read 5, iclass 21, count 0 2006.285.20:58:03.72#ibcon#about to read 6, iclass 21, count 0 2006.285.20:58:03.72#ibcon#read 6, iclass 21, count 0 2006.285.20:58:03.72#ibcon#end of sib2, iclass 21, count 0 2006.285.20:58:03.72#ibcon#*after write, iclass 21, count 0 2006.285.20:58:03.72#ibcon#*before return 0, iclass 21, count 0 2006.285.20:58:03.72#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:58:03.72#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:58:03.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:58:03.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:58:03.72$vck44/valo=5,734.99 2006.285.20:58:03.72#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.20:58:03.72#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.20:58:03.72#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:03.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:58:03.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:58:03.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:58:03.72#ibcon#enter wrdev, iclass 23, count 0 2006.285.20:58:03.72#ibcon#first serial, iclass 23, count 0 2006.285.20:58:03.72#ibcon#enter sib2, iclass 23, count 0 2006.285.20:58:03.72#ibcon#flushed, iclass 23, count 0 2006.285.20:58:03.72#ibcon#about to write, iclass 23, count 0 2006.285.20:58:03.72#ibcon#wrote, iclass 23, count 0 2006.285.20:58:03.72#ibcon#about to read 3, iclass 23, count 0 2006.285.20:58:03.74#ibcon#read 3, iclass 23, count 0 2006.285.20:58:03.97#ibcon#about to read 4, iclass 23, count 0 2006.285.20:58:03.97#ibcon#read 4, iclass 23, count 0 2006.285.20:58:03.97#ibcon#about to read 5, iclass 23, count 0 2006.285.20:58:03.97#ibcon#read 5, iclass 23, count 0 2006.285.20:58:03.97#ibcon#about to read 6, iclass 23, count 0 2006.285.20:58:03.97#ibcon#read 6, iclass 23, count 0 2006.285.20:58:03.97#ibcon#end of sib2, iclass 23, count 0 2006.285.20:58:03.97#ibcon#*mode == 0, iclass 23, count 0 2006.285.20:58:03.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.20:58:03.97#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.20:58:03.97#ibcon#*before write, iclass 23, count 0 2006.285.20:58:03.97#ibcon#enter sib2, iclass 23, count 0 2006.285.20:58:03.97#ibcon#flushed, iclass 23, count 0 2006.285.20:58:03.97#ibcon#about to write, iclass 23, count 0 2006.285.20:58:03.97#ibcon#wrote, iclass 23, count 0 2006.285.20:58:03.97#ibcon#about to read 3, iclass 23, count 0 2006.285.20:58:04.01#ibcon#read 3, iclass 23, count 0 2006.285.20:58:04.01#ibcon#about to read 4, iclass 23, count 0 2006.285.20:58:04.01#ibcon#read 4, iclass 23, count 0 2006.285.20:58:04.01#ibcon#about to read 5, iclass 23, count 0 2006.285.20:58:04.01#ibcon#read 5, iclass 23, count 0 2006.285.20:58:04.01#ibcon#about to read 6, iclass 23, count 0 2006.285.20:58:04.01#ibcon#read 6, iclass 23, count 0 2006.285.20:58:04.01#ibcon#end of sib2, iclass 23, count 0 2006.285.20:58:04.01#ibcon#*after write, iclass 23, count 0 2006.285.20:58:04.01#ibcon#*before return 0, iclass 23, count 0 2006.285.20:58:04.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:58:04.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:58:04.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.20:58:04.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.20:58:04.01$vck44/va=5,3 2006.285.20:58:04.01#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.20:58:04.01#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.20:58:04.01#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:04.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:58:04.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:58:04.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:58:04.01#ibcon#enter wrdev, iclass 25, count 2 2006.285.20:58:04.01#ibcon#first serial, iclass 25, count 2 2006.285.20:58:04.01#ibcon#enter sib2, iclass 25, count 2 2006.285.20:58:04.01#ibcon#flushed, iclass 25, count 2 2006.285.20:58:04.01#ibcon#about to write, iclass 25, count 2 2006.285.20:58:04.01#ibcon#wrote, iclass 25, count 2 2006.285.20:58:04.01#ibcon#about to read 3, iclass 25, count 2 2006.285.20:58:04.03#ibcon#read 3, iclass 25, count 2 2006.285.20:58:04.03#ibcon#about to read 4, iclass 25, count 2 2006.285.20:58:04.03#ibcon#read 4, iclass 25, count 2 2006.285.20:58:04.03#ibcon#about to read 5, iclass 25, count 2 2006.285.20:58:04.03#ibcon#read 5, iclass 25, count 2 2006.285.20:58:04.03#ibcon#about to read 6, iclass 25, count 2 2006.285.20:58:04.03#ibcon#read 6, iclass 25, count 2 2006.285.20:58:04.03#ibcon#end of sib2, iclass 25, count 2 2006.285.20:58:04.03#ibcon#*mode == 0, iclass 25, count 2 2006.285.20:58:04.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.20:58:04.03#ibcon#[25=AT05-03\r\n] 2006.285.20:58:04.03#ibcon#*before write, iclass 25, count 2 2006.285.20:58:04.03#ibcon#enter sib2, iclass 25, count 2 2006.285.20:58:04.03#ibcon#flushed, iclass 25, count 2 2006.285.20:58:04.03#ibcon#about to write, iclass 25, count 2 2006.285.20:58:04.03#ibcon#wrote, iclass 25, count 2 2006.285.20:58:04.03#ibcon#about to read 3, iclass 25, count 2 2006.285.20:58:04.06#ibcon#read 3, iclass 25, count 2 2006.285.20:58:04.06#ibcon#about to read 4, iclass 25, count 2 2006.285.20:58:04.06#ibcon#read 4, iclass 25, count 2 2006.285.20:58:04.06#ibcon#about to read 5, iclass 25, count 2 2006.285.20:58:04.06#ibcon#read 5, iclass 25, count 2 2006.285.20:58:04.06#ibcon#about to read 6, iclass 25, count 2 2006.285.20:58:04.06#ibcon#read 6, iclass 25, count 2 2006.285.20:58:04.06#ibcon#end of sib2, iclass 25, count 2 2006.285.20:58:04.06#ibcon#*after write, iclass 25, count 2 2006.285.20:58:04.06#ibcon#*before return 0, iclass 25, count 2 2006.285.20:58:04.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:58:04.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:58:04.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.20:58:04.06#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:04.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:58:04.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:58:04.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:58:04.18#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:58:04.18#ibcon#first serial, iclass 25, count 0 2006.285.20:58:04.18#ibcon#enter sib2, iclass 25, count 0 2006.285.20:58:04.18#ibcon#flushed, iclass 25, count 0 2006.285.20:58:04.18#ibcon#about to write, iclass 25, count 0 2006.285.20:58:04.18#ibcon#wrote, iclass 25, count 0 2006.285.20:58:04.18#ibcon#about to read 3, iclass 25, count 0 2006.285.20:58:04.20#ibcon#read 3, iclass 25, count 0 2006.285.20:58:04.20#ibcon#about to read 4, iclass 25, count 0 2006.285.20:58:04.20#ibcon#read 4, iclass 25, count 0 2006.285.20:58:04.20#ibcon#about to read 5, iclass 25, count 0 2006.285.20:58:04.20#ibcon#read 5, iclass 25, count 0 2006.285.20:58:04.20#ibcon#about to read 6, iclass 25, count 0 2006.285.20:58:04.20#ibcon#read 6, iclass 25, count 0 2006.285.20:58:04.20#ibcon#end of sib2, iclass 25, count 0 2006.285.20:58:04.20#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:58:04.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:58:04.20#ibcon#[25=USB\r\n] 2006.285.20:58:04.20#ibcon#*before write, iclass 25, count 0 2006.285.20:58:04.20#ibcon#enter sib2, iclass 25, count 0 2006.285.20:58:04.20#ibcon#flushed, iclass 25, count 0 2006.285.20:58:04.20#ibcon#about to write, iclass 25, count 0 2006.285.20:58:04.20#ibcon#wrote, iclass 25, count 0 2006.285.20:58:04.20#ibcon#about to read 3, iclass 25, count 0 2006.285.20:58:04.23#ibcon#read 3, iclass 25, count 0 2006.285.20:58:04.23#ibcon#about to read 4, iclass 25, count 0 2006.285.20:58:04.23#ibcon#read 4, iclass 25, count 0 2006.285.20:58:04.23#ibcon#about to read 5, iclass 25, count 0 2006.285.20:58:04.23#ibcon#read 5, iclass 25, count 0 2006.285.20:58:04.23#ibcon#about to read 6, iclass 25, count 0 2006.285.20:58:04.23#ibcon#read 6, iclass 25, count 0 2006.285.20:58:04.23#ibcon#end of sib2, iclass 25, count 0 2006.285.20:58:04.23#ibcon#*after write, iclass 25, count 0 2006.285.20:58:04.23#ibcon#*before return 0, iclass 25, count 0 2006.285.20:58:04.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:58:04.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:58:04.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:58:04.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:58:04.23$vck44/valo=6,814.99 2006.285.20:58:04.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.20:58:04.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.20:58:04.23#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:04.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:58:04.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:58:04.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:58:04.23#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:58:04.23#ibcon#first serial, iclass 27, count 0 2006.285.20:58:04.23#ibcon#enter sib2, iclass 27, count 0 2006.285.20:58:04.23#ibcon#flushed, iclass 27, count 0 2006.285.20:58:04.23#ibcon#about to write, iclass 27, count 0 2006.285.20:58:04.23#ibcon#wrote, iclass 27, count 0 2006.285.20:58:04.23#ibcon#about to read 3, iclass 27, count 0 2006.285.20:58:04.25#ibcon#read 3, iclass 27, count 0 2006.285.20:58:04.25#ibcon#about to read 4, iclass 27, count 0 2006.285.20:58:04.25#ibcon#read 4, iclass 27, count 0 2006.285.20:58:04.25#ibcon#about to read 5, iclass 27, count 0 2006.285.20:58:04.25#ibcon#read 5, iclass 27, count 0 2006.285.20:58:04.25#ibcon#about to read 6, iclass 27, count 0 2006.285.20:58:04.25#ibcon#read 6, iclass 27, count 0 2006.285.20:58:04.25#ibcon#end of sib2, iclass 27, count 0 2006.285.20:58:04.25#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:58:04.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:58:04.25#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.20:58:04.25#ibcon#*before write, iclass 27, count 0 2006.285.20:58:04.25#ibcon#enter sib2, iclass 27, count 0 2006.285.20:58:04.25#ibcon#flushed, iclass 27, count 0 2006.285.20:58:04.25#ibcon#about to write, iclass 27, count 0 2006.285.20:58:04.25#ibcon#wrote, iclass 27, count 0 2006.285.20:58:04.25#ibcon#about to read 3, iclass 27, count 0 2006.285.20:58:04.29#ibcon#read 3, iclass 27, count 0 2006.285.20:58:04.29#ibcon#about to read 4, iclass 27, count 0 2006.285.20:58:04.29#ibcon#read 4, iclass 27, count 0 2006.285.20:58:04.29#ibcon#about to read 5, iclass 27, count 0 2006.285.20:58:04.29#ibcon#read 5, iclass 27, count 0 2006.285.20:58:04.29#ibcon#about to read 6, iclass 27, count 0 2006.285.20:58:04.29#ibcon#read 6, iclass 27, count 0 2006.285.20:58:04.29#ibcon#end of sib2, iclass 27, count 0 2006.285.20:58:04.29#ibcon#*after write, iclass 27, count 0 2006.285.20:58:04.29#ibcon#*before return 0, iclass 27, count 0 2006.285.20:58:04.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:58:04.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:58:04.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:58:04.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:58:04.29$vck44/va=6,4 2006.285.20:58:04.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.20:58:04.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.20:58:04.29#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:04.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:58:04.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:58:04.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:58:04.35#ibcon#enter wrdev, iclass 29, count 2 2006.285.20:58:04.35#ibcon#first serial, iclass 29, count 2 2006.285.20:58:04.35#ibcon#enter sib2, iclass 29, count 2 2006.285.20:58:04.35#ibcon#flushed, iclass 29, count 2 2006.285.20:58:04.35#ibcon#about to write, iclass 29, count 2 2006.285.20:58:04.35#ibcon#wrote, iclass 29, count 2 2006.285.20:58:04.35#ibcon#about to read 3, iclass 29, count 2 2006.285.20:58:04.37#ibcon#read 3, iclass 29, count 2 2006.285.20:58:04.37#ibcon#about to read 4, iclass 29, count 2 2006.285.20:58:04.37#ibcon#read 4, iclass 29, count 2 2006.285.20:58:04.37#ibcon#about to read 5, iclass 29, count 2 2006.285.20:58:04.37#ibcon#read 5, iclass 29, count 2 2006.285.20:58:04.37#ibcon#about to read 6, iclass 29, count 2 2006.285.20:58:04.37#ibcon#read 6, iclass 29, count 2 2006.285.20:58:04.37#ibcon#end of sib2, iclass 29, count 2 2006.285.20:58:04.37#ibcon#*mode == 0, iclass 29, count 2 2006.285.20:58:04.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.20:58:04.37#ibcon#[25=AT06-04\r\n] 2006.285.20:58:04.37#ibcon#*before write, iclass 29, count 2 2006.285.20:58:04.37#ibcon#enter sib2, iclass 29, count 2 2006.285.20:58:04.37#ibcon#flushed, iclass 29, count 2 2006.285.20:58:04.37#ibcon#about to write, iclass 29, count 2 2006.285.20:58:04.37#ibcon#wrote, iclass 29, count 2 2006.285.20:58:04.37#ibcon#about to read 3, iclass 29, count 2 2006.285.20:58:04.40#ibcon#read 3, iclass 29, count 2 2006.285.20:58:04.40#ibcon#about to read 4, iclass 29, count 2 2006.285.20:58:04.40#ibcon#read 4, iclass 29, count 2 2006.285.20:58:04.40#ibcon#about to read 5, iclass 29, count 2 2006.285.20:58:04.40#ibcon#read 5, iclass 29, count 2 2006.285.20:58:04.40#ibcon#about to read 6, iclass 29, count 2 2006.285.20:58:04.40#ibcon#read 6, iclass 29, count 2 2006.285.20:58:04.40#ibcon#end of sib2, iclass 29, count 2 2006.285.20:58:04.40#ibcon#*after write, iclass 29, count 2 2006.285.20:58:04.40#ibcon#*before return 0, iclass 29, count 2 2006.285.20:58:04.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:58:04.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:58:04.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.20:58:04.40#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:04.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:58:04.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:58:04.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:58:04.52#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:58:04.52#ibcon#first serial, iclass 29, count 0 2006.285.20:58:04.52#ibcon#enter sib2, iclass 29, count 0 2006.285.20:58:04.52#ibcon#flushed, iclass 29, count 0 2006.285.20:58:04.52#ibcon#about to write, iclass 29, count 0 2006.285.20:58:04.52#ibcon#wrote, iclass 29, count 0 2006.285.20:58:04.52#ibcon#about to read 3, iclass 29, count 0 2006.285.20:58:04.54#ibcon#read 3, iclass 29, count 0 2006.285.20:58:04.54#ibcon#about to read 4, iclass 29, count 0 2006.285.20:58:04.54#ibcon#read 4, iclass 29, count 0 2006.285.20:58:04.54#ibcon#about to read 5, iclass 29, count 0 2006.285.20:58:04.54#ibcon#read 5, iclass 29, count 0 2006.285.20:58:04.54#ibcon#about to read 6, iclass 29, count 0 2006.285.20:58:04.54#ibcon#read 6, iclass 29, count 0 2006.285.20:58:04.54#ibcon#end of sib2, iclass 29, count 0 2006.285.20:58:04.54#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:58:04.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:58:04.54#ibcon#[25=USB\r\n] 2006.285.20:58:04.54#ibcon#*before write, iclass 29, count 0 2006.285.20:58:04.54#ibcon#enter sib2, iclass 29, count 0 2006.285.20:58:04.54#ibcon#flushed, iclass 29, count 0 2006.285.20:58:04.54#ibcon#about to write, iclass 29, count 0 2006.285.20:58:04.54#ibcon#wrote, iclass 29, count 0 2006.285.20:58:04.54#ibcon#about to read 3, iclass 29, count 0 2006.285.20:58:04.57#ibcon#read 3, iclass 29, count 0 2006.285.20:58:04.57#ibcon#about to read 4, iclass 29, count 0 2006.285.20:58:04.57#ibcon#read 4, iclass 29, count 0 2006.285.20:58:04.57#ibcon#about to read 5, iclass 29, count 0 2006.285.20:58:04.57#ibcon#read 5, iclass 29, count 0 2006.285.20:58:04.57#ibcon#about to read 6, iclass 29, count 0 2006.285.20:58:04.57#ibcon#read 6, iclass 29, count 0 2006.285.20:58:04.57#ibcon#end of sib2, iclass 29, count 0 2006.285.20:58:04.57#ibcon#*after write, iclass 29, count 0 2006.285.20:58:04.57#ibcon#*before return 0, iclass 29, count 0 2006.285.20:58:04.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:58:04.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:58:04.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:58:04.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:58:04.57$vck44/valo=7,864.99 2006.285.20:58:04.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.20:58:04.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.20:58:04.57#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:04.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:58:04.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:58:04.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:58:04.57#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:58:04.57#ibcon#first serial, iclass 31, count 0 2006.285.20:58:04.57#ibcon#enter sib2, iclass 31, count 0 2006.285.20:58:04.57#ibcon#flushed, iclass 31, count 0 2006.285.20:58:04.57#ibcon#about to write, iclass 31, count 0 2006.285.20:58:04.57#ibcon#wrote, iclass 31, count 0 2006.285.20:58:04.57#ibcon#about to read 3, iclass 31, count 0 2006.285.20:58:04.59#ibcon#read 3, iclass 31, count 0 2006.285.20:58:04.59#ibcon#about to read 4, iclass 31, count 0 2006.285.20:58:04.59#ibcon#read 4, iclass 31, count 0 2006.285.20:58:04.59#ibcon#about to read 5, iclass 31, count 0 2006.285.20:58:04.59#ibcon#read 5, iclass 31, count 0 2006.285.20:58:04.59#ibcon#about to read 6, iclass 31, count 0 2006.285.20:58:04.59#ibcon#read 6, iclass 31, count 0 2006.285.20:58:04.59#ibcon#end of sib2, iclass 31, count 0 2006.285.20:58:04.59#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:58:04.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:58:04.59#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.20:58:04.59#ibcon#*before write, iclass 31, count 0 2006.285.20:58:04.59#ibcon#enter sib2, iclass 31, count 0 2006.285.20:58:04.59#ibcon#flushed, iclass 31, count 0 2006.285.20:58:04.59#ibcon#about to write, iclass 31, count 0 2006.285.20:58:04.59#ibcon#wrote, iclass 31, count 0 2006.285.20:58:04.59#ibcon#about to read 3, iclass 31, count 0 2006.285.20:58:04.63#ibcon#read 3, iclass 31, count 0 2006.285.20:58:04.63#ibcon#about to read 4, iclass 31, count 0 2006.285.20:58:04.63#ibcon#read 4, iclass 31, count 0 2006.285.20:58:04.63#ibcon#about to read 5, iclass 31, count 0 2006.285.20:58:04.63#ibcon#read 5, iclass 31, count 0 2006.285.20:58:04.63#ibcon#about to read 6, iclass 31, count 0 2006.285.20:58:04.63#ibcon#read 6, iclass 31, count 0 2006.285.20:58:04.63#ibcon#end of sib2, iclass 31, count 0 2006.285.20:58:04.63#ibcon#*after write, iclass 31, count 0 2006.285.20:58:04.63#ibcon#*before return 0, iclass 31, count 0 2006.285.20:58:04.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:58:04.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:58:04.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:58:04.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:58:04.63$vck44/va=7,4 2006.285.20:58:04.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.20:58:04.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.20:58:04.95#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:04.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:58:04.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:58:04.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:58:04.95#ibcon#enter wrdev, iclass 33, count 2 2006.285.20:58:04.95#ibcon#first serial, iclass 33, count 2 2006.285.20:58:04.95#ibcon#enter sib2, iclass 33, count 2 2006.285.20:58:04.95#ibcon#flushed, iclass 33, count 2 2006.285.20:58:04.95#ibcon#about to write, iclass 33, count 2 2006.285.20:58:04.95#ibcon#wrote, iclass 33, count 2 2006.285.20:58:04.95#ibcon#about to read 3, iclass 33, count 2 2006.285.20:58:04.97#ibcon#read 3, iclass 33, count 2 2006.285.20:58:04.97#ibcon#about to read 4, iclass 33, count 2 2006.285.20:58:04.97#ibcon#read 4, iclass 33, count 2 2006.285.20:58:04.97#ibcon#about to read 5, iclass 33, count 2 2006.285.20:58:04.97#ibcon#read 5, iclass 33, count 2 2006.285.20:58:04.97#ibcon#about to read 6, iclass 33, count 2 2006.285.20:58:04.97#ibcon#read 6, iclass 33, count 2 2006.285.20:58:04.97#ibcon#end of sib2, iclass 33, count 2 2006.285.20:58:04.97#ibcon#*mode == 0, iclass 33, count 2 2006.285.20:58:04.97#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.20:58:04.97#ibcon#[25=AT07-04\r\n] 2006.285.20:58:04.97#ibcon#*before write, iclass 33, count 2 2006.285.20:58:04.97#ibcon#enter sib2, iclass 33, count 2 2006.285.20:58:04.97#ibcon#flushed, iclass 33, count 2 2006.285.20:58:04.97#ibcon#about to write, iclass 33, count 2 2006.285.20:58:04.97#ibcon#wrote, iclass 33, count 2 2006.285.20:58:04.97#ibcon#about to read 3, iclass 33, count 2 2006.285.20:58:05.00#ibcon#read 3, iclass 33, count 2 2006.285.20:58:05.00#ibcon#about to read 4, iclass 33, count 2 2006.285.20:58:05.00#ibcon#read 4, iclass 33, count 2 2006.285.20:58:05.00#ibcon#about to read 5, iclass 33, count 2 2006.285.20:58:05.00#ibcon#read 5, iclass 33, count 2 2006.285.20:58:05.00#ibcon#about to read 6, iclass 33, count 2 2006.285.20:58:05.00#ibcon#read 6, iclass 33, count 2 2006.285.20:58:05.00#ibcon#end of sib2, iclass 33, count 2 2006.285.20:58:05.00#ibcon#*after write, iclass 33, count 2 2006.285.20:58:05.00#ibcon#*before return 0, iclass 33, count 2 2006.285.20:58:05.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:58:05.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:58:05.00#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.20:58:05.00#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:05.00#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:58:05.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:58:05.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:58:05.12#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:58:05.12#ibcon#first serial, iclass 33, count 0 2006.285.20:58:05.12#ibcon#enter sib2, iclass 33, count 0 2006.285.20:58:05.12#ibcon#flushed, iclass 33, count 0 2006.285.20:58:05.12#ibcon#about to write, iclass 33, count 0 2006.285.20:58:05.12#ibcon#wrote, iclass 33, count 0 2006.285.20:58:05.12#ibcon#about to read 3, iclass 33, count 0 2006.285.20:58:05.14#ibcon#read 3, iclass 33, count 0 2006.285.20:58:05.14#ibcon#about to read 4, iclass 33, count 0 2006.285.20:58:05.14#ibcon#read 4, iclass 33, count 0 2006.285.20:58:05.14#ibcon#about to read 5, iclass 33, count 0 2006.285.20:58:05.14#ibcon#read 5, iclass 33, count 0 2006.285.20:58:05.14#ibcon#about to read 6, iclass 33, count 0 2006.285.20:58:05.14#ibcon#read 6, iclass 33, count 0 2006.285.20:58:05.14#ibcon#end of sib2, iclass 33, count 0 2006.285.20:58:05.14#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:58:05.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:58:05.14#ibcon#[25=USB\r\n] 2006.285.20:58:05.14#ibcon#*before write, iclass 33, count 0 2006.285.20:58:05.14#ibcon#enter sib2, iclass 33, count 0 2006.285.20:58:05.14#ibcon#flushed, iclass 33, count 0 2006.285.20:58:05.14#ibcon#about to write, iclass 33, count 0 2006.285.20:58:05.14#ibcon#wrote, iclass 33, count 0 2006.285.20:58:05.14#ibcon#about to read 3, iclass 33, count 0 2006.285.20:58:05.17#ibcon#read 3, iclass 33, count 0 2006.285.20:58:05.17#ibcon#about to read 4, iclass 33, count 0 2006.285.20:58:05.17#ibcon#read 4, iclass 33, count 0 2006.285.20:58:05.17#ibcon#about to read 5, iclass 33, count 0 2006.285.20:58:05.17#ibcon#read 5, iclass 33, count 0 2006.285.20:58:05.17#ibcon#about to read 6, iclass 33, count 0 2006.285.20:58:05.17#ibcon#read 6, iclass 33, count 0 2006.285.20:58:05.17#ibcon#end of sib2, iclass 33, count 0 2006.285.20:58:05.17#ibcon#*after write, iclass 33, count 0 2006.285.20:58:05.17#ibcon#*before return 0, iclass 33, count 0 2006.285.20:58:05.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:58:05.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:58:05.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:58:05.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:58:05.17$vck44/valo=8,884.99 2006.285.20:58:05.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.20:58:05.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.20:58:05.17#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:05.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:58:05.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:58:05.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:58:05.17#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:58:05.17#ibcon#first serial, iclass 35, count 0 2006.285.20:58:05.17#ibcon#enter sib2, iclass 35, count 0 2006.285.20:58:05.17#ibcon#flushed, iclass 35, count 0 2006.285.20:58:05.17#ibcon#about to write, iclass 35, count 0 2006.285.20:58:05.17#ibcon#wrote, iclass 35, count 0 2006.285.20:58:05.17#ibcon#about to read 3, iclass 35, count 0 2006.285.20:58:05.19#ibcon#read 3, iclass 35, count 0 2006.285.20:58:05.19#ibcon#about to read 4, iclass 35, count 0 2006.285.20:58:05.19#ibcon#read 4, iclass 35, count 0 2006.285.20:58:05.19#ibcon#about to read 5, iclass 35, count 0 2006.285.20:58:05.19#ibcon#read 5, iclass 35, count 0 2006.285.20:58:05.19#ibcon#about to read 6, iclass 35, count 0 2006.285.20:58:05.19#ibcon#read 6, iclass 35, count 0 2006.285.20:58:05.19#ibcon#end of sib2, iclass 35, count 0 2006.285.20:58:05.19#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:58:05.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:58:05.19#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.20:58:05.19#ibcon#*before write, iclass 35, count 0 2006.285.20:58:05.19#ibcon#enter sib2, iclass 35, count 0 2006.285.20:58:05.19#ibcon#flushed, iclass 35, count 0 2006.285.20:58:05.19#ibcon#about to write, iclass 35, count 0 2006.285.20:58:05.19#ibcon#wrote, iclass 35, count 0 2006.285.20:58:05.19#ibcon#about to read 3, iclass 35, count 0 2006.285.20:58:05.23#ibcon#read 3, iclass 35, count 0 2006.285.20:58:05.23#ibcon#about to read 4, iclass 35, count 0 2006.285.20:58:05.23#ibcon#read 4, iclass 35, count 0 2006.285.20:58:05.23#ibcon#about to read 5, iclass 35, count 0 2006.285.20:58:05.23#ibcon#read 5, iclass 35, count 0 2006.285.20:58:05.23#ibcon#about to read 6, iclass 35, count 0 2006.285.20:58:05.23#ibcon#read 6, iclass 35, count 0 2006.285.20:58:05.23#ibcon#end of sib2, iclass 35, count 0 2006.285.20:58:05.23#ibcon#*after write, iclass 35, count 0 2006.285.20:58:05.23#ibcon#*before return 0, iclass 35, count 0 2006.285.20:58:05.23#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:58:05.23#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:58:05.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:58:05.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:58:05.23$vck44/va=8,3 2006.285.20:58:05.23#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.20:58:05.23#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.20:58:05.23#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:05.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:58:05.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:58:05.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:58:05.29#ibcon#enter wrdev, iclass 37, count 2 2006.285.20:58:05.29#ibcon#first serial, iclass 37, count 2 2006.285.20:58:05.29#ibcon#enter sib2, iclass 37, count 2 2006.285.20:58:05.29#ibcon#flushed, iclass 37, count 2 2006.285.20:58:05.29#ibcon#about to write, iclass 37, count 2 2006.285.20:58:05.29#ibcon#wrote, iclass 37, count 2 2006.285.20:58:05.29#ibcon#about to read 3, iclass 37, count 2 2006.285.20:58:05.31#ibcon#read 3, iclass 37, count 2 2006.285.20:58:05.31#ibcon#about to read 4, iclass 37, count 2 2006.285.20:58:05.31#ibcon#read 4, iclass 37, count 2 2006.285.20:58:05.31#ibcon#about to read 5, iclass 37, count 2 2006.285.20:58:05.31#ibcon#read 5, iclass 37, count 2 2006.285.20:58:05.31#ibcon#about to read 6, iclass 37, count 2 2006.285.20:58:05.31#ibcon#read 6, iclass 37, count 2 2006.285.20:58:05.31#ibcon#end of sib2, iclass 37, count 2 2006.285.20:58:05.31#ibcon#*mode == 0, iclass 37, count 2 2006.285.20:58:05.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.20:58:05.31#ibcon#[25=AT08-03\r\n] 2006.285.20:58:05.31#ibcon#*before write, iclass 37, count 2 2006.285.20:58:05.31#ibcon#enter sib2, iclass 37, count 2 2006.285.20:58:05.31#ibcon#flushed, iclass 37, count 2 2006.285.20:58:05.31#ibcon#about to write, iclass 37, count 2 2006.285.20:58:05.31#ibcon#wrote, iclass 37, count 2 2006.285.20:58:05.31#ibcon#about to read 3, iclass 37, count 2 2006.285.20:58:05.34#ibcon#read 3, iclass 37, count 2 2006.285.20:58:05.34#ibcon#about to read 4, iclass 37, count 2 2006.285.20:58:05.34#ibcon#read 4, iclass 37, count 2 2006.285.20:58:05.34#ibcon#about to read 5, iclass 37, count 2 2006.285.20:58:05.34#ibcon#read 5, iclass 37, count 2 2006.285.20:58:05.34#ibcon#about to read 6, iclass 37, count 2 2006.285.20:58:05.34#ibcon#read 6, iclass 37, count 2 2006.285.20:58:05.34#ibcon#end of sib2, iclass 37, count 2 2006.285.20:58:05.34#ibcon#*after write, iclass 37, count 2 2006.285.20:58:05.34#ibcon#*before return 0, iclass 37, count 2 2006.285.20:58:05.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:58:05.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.20:58:05.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.20:58:05.34#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:05.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:58:05.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:58:05.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:58:05.46#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:58:05.46#ibcon#first serial, iclass 37, count 0 2006.285.20:58:05.46#ibcon#enter sib2, iclass 37, count 0 2006.285.20:58:05.46#ibcon#flushed, iclass 37, count 0 2006.285.20:58:05.46#ibcon#about to write, iclass 37, count 0 2006.285.20:58:05.46#ibcon#wrote, iclass 37, count 0 2006.285.20:58:05.46#ibcon#about to read 3, iclass 37, count 0 2006.285.20:58:05.48#ibcon#read 3, iclass 37, count 0 2006.285.20:58:05.48#ibcon#about to read 4, iclass 37, count 0 2006.285.20:58:05.48#ibcon#read 4, iclass 37, count 0 2006.285.20:58:05.48#ibcon#about to read 5, iclass 37, count 0 2006.285.20:58:05.48#ibcon#read 5, iclass 37, count 0 2006.285.20:58:05.48#ibcon#about to read 6, iclass 37, count 0 2006.285.20:58:05.48#ibcon#read 6, iclass 37, count 0 2006.285.20:58:05.48#ibcon#end of sib2, iclass 37, count 0 2006.285.20:58:05.48#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:58:05.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:58:05.48#ibcon#[25=USB\r\n] 2006.285.20:58:05.48#ibcon#*before write, iclass 37, count 0 2006.285.20:58:05.48#ibcon#enter sib2, iclass 37, count 0 2006.285.20:58:05.48#ibcon#flushed, iclass 37, count 0 2006.285.20:58:05.48#ibcon#about to write, iclass 37, count 0 2006.285.20:58:05.48#ibcon#wrote, iclass 37, count 0 2006.285.20:58:05.48#ibcon#about to read 3, iclass 37, count 0 2006.285.20:58:05.51#ibcon#read 3, iclass 37, count 0 2006.285.20:58:05.51#ibcon#about to read 4, iclass 37, count 0 2006.285.20:58:05.51#ibcon#read 4, iclass 37, count 0 2006.285.20:58:05.51#ibcon#about to read 5, iclass 37, count 0 2006.285.20:58:05.51#ibcon#read 5, iclass 37, count 0 2006.285.20:58:05.51#ibcon#about to read 6, iclass 37, count 0 2006.285.20:58:05.51#ibcon#read 6, iclass 37, count 0 2006.285.20:58:05.51#ibcon#end of sib2, iclass 37, count 0 2006.285.20:58:05.51#ibcon#*after write, iclass 37, count 0 2006.285.20:58:05.51#ibcon#*before return 0, iclass 37, count 0 2006.285.20:58:05.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:58:05.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.20:58:05.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:58:05.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:58:05.51$vck44/vblo=1,629.99 2006.285.20:58:05.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.20:58:05.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.20:58:05.51#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:05.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:58:05.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:58:05.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:58:05.51#ibcon#enter wrdev, iclass 39, count 0 2006.285.20:58:05.51#ibcon#first serial, iclass 39, count 0 2006.285.20:58:05.51#ibcon#enter sib2, iclass 39, count 0 2006.285.20:58:05.51#ibcon#flushed, iclass 39, count 0 2006.285.20:58:05.51#ibcon#about to write, iclass 39, count 0 2006.285.20:58:05.51#ibcon#wrote, iclass 39, count 0 2006.285.20:58:05.51#ibcon#about to read 3, iclass 39, count 0 2006.285.20:58:05.53#ibcon#read 3, iclass 39, count 0 2006.285.20:58:05.53#ibcon#about to read 4, iclass 39, count 0 2006.285.20:58:05.53#ibcon#read 4, iclass 39, count 0 2006.285.20:58:05.53#ibcon#about to read 5, iclass 39, count 0 2006.285.20:58:05.53#ibcon#read 5, iclass 39, count 0 2006.285.20:58:05.53#ibcon#about to read 6, iclass 39, count 0 2006.285.20:58:05.53#ibcon#read 6, iclass 39, count 0 2006.285.20:58:05.53#ibcon#end of sib2, iclass 39, count 0 2006.285.20:58:05.53#ibcon#*mode == 0, iclass 39, count 0 2006.285.20:58:05.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.20:58:05.53#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.20:58:05.53#ibcon#*before write, iclass 39, count 0 2006.285.20:58:05.53#ibcon#enter sib2, iclass 39, count 0 2006.285.20:58:05.53#ibcon#flushed, iclass 39, count 0 2006.285.20:58:05.53#ibcon#about to write, iclass 39, count 0 2006.285.20:58:05.53#ibcon#wrote, iclass 39, count 0 2006.285.20:58:05.53#ibcon#about to read 3, iclass 39, count 0 2006.285.20:58:05.57#ibcon#read 3, iclass 39, count 0 2006.285.20:58:05.57#ibcon#about to read 4, iclass 39, count 0 2006.285.20:58:05.57#ibcon#read 4, iclass 39, count 0 2006.285.20:58:05.57#ibcon#about to read 5, iclass 39, count 0 2006.285.20:58:05.57#ibcon#read 5, iclass 39, count 0 2006.285.20:58:05.57#ibcon#about to read 6, iclass 39, count 0 2006.285.20:58:05.57#ibcon#read 6, iclass 39, count 0 2006.285.20:58:05.57#ibcon#end of sib2, iclass 39, count 0 2006.285.20:58:05.57#ibcon#*after write, iclass 39, count 0 2006.285.20:58:05.57#ibcon#*before return 0, iclass 39, count 0 2006.285.20:58:05.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:58:05.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.20:58:05.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.20:58:05.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.20:58:05.57$vck44/vb=1,4 2006.285.20:58:05.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.20:58:05.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.20:58:05.57#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:05.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:58:05.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:58:05.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:58:05.57#ibcon#enter wrdev, iclass 3, count 2 2006.285.20:58:05.57#ibcon#first serial, iclass 3, count 2 2006.285.20:58:05.57#ibcon#enter sib2, iclass 3, count 2 2006.285.20:58:05.57#ibcon#flushed, iclass 3, count 2 2006.285.20:58:05.57#ibcon#about to write, iclass 3, count 2 2006.285.20:58:05.57#ibcon#wrote, iclass 3, count 2 2006.285.20:58:05.57#ibcon#about to read 3, iclass 3, count 2 2006.285.20:58:05.59#ibcon#read 3, iclass 3, count 2 2006.285.20:58:05.59#ibcon#about to read 4, iclass 3, count 2 2006.285.20:58:05.59#ibcon#read 4, iclass 3, count 2 2006.285.20:58:05.59#ibcon#about to read 5, iclass 3, count 2 2006.285.20:58:05.59#ibcon#read 5, iclass 3, count 2 2006.285.20:58:05.59#ibcon#about to read 6, iclass 3, count 2 2006.285.20:58:05.59#ibcon#read 6, iclass 3, count 2 2006.285.20:58:05.59#ibcon#end of sib2, iclass 3, count 2 2006.285.20:58:05.59#ibcon#*mode == 0, iclass 3, count 2 2006.285.20:58:05.59#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.20:58:05.59#ibcon#[27=AT01-04\r\n] 2006.285.20:58:05.59#ibcon#*before write, iclass 3, count 2 2006.285.20:58:05.59#ibcon#enter sib2, iclass 3, count 2 2006.285.20:58:05.59#ibcon#flushed, iclass 3, count 2 2006.285.20:58:05.59#ibcon#about to write, iclass 3, count 2 2006.285.20:58:05.59#ibcon#wrote, iclass 3, count 2 2006.285.20:58:05.59#ibcon#about to read 3, iclass 3, count 2 2006.285.20:58:05.62#ibcon#read 3, iclass 3, count 2 2006.285.20:58:05.62#ibcon#about to read 4, iclass 3, count 2 2006.285.20:58:05.62#ibcon#read 4, iclass 3, count 2 2006.285.20:58:05.62#ibcon#about to read 5, iclass 3, count 2 2006.285.20:58:05.62#ibcon#read 5, iclass 3, count 2 2006.285.20:58:05.62#ibcon#about to read 6, iclass 3, count 2 2006.285.20:58:05.62#ibcon#read 6, iclass 3, count 2 2006.285.20:58:05.62#ibcon#end of sib2, iclass 3, count 2 2006.285.20:58:05.62#ibcon#*after write, iclass 3, count 2 2006.285.20:58:05.62#ibcon#*before return 0, iclass 3, count 2 2006.285.20:58:05.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:58:05.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.20:58:05.62#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.20:58:05.62#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:05.62#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:58:05.74#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:58:05.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:58:05.87#ibcon#enter wrdev, iclass 3, count 0 2006.285.20:58:05.87#ibcon#first serial, iclass 3, count 0 2006.285.20:58:05.87#ibcon#enter sib2, iclass 3, count 0 2006.285.20:58:05.87#ibcon#flushed, iclass 3, count 0 2006.285.20:58:05.87#ibcon#about to write, iclass 3, count 0 2006.285.20:58:05.88#ibcon#wrote, iclass 3, count 0 2006.285.20:58:05.88#ibcon#about to read 3, iclass 3, count 0 2006.285.20:58:05.89#ibcon#read 3, iclass 3, count 0 2006.285.20:58:05.89#ibcon#about to read 4, iclass 3, count 0 2006.285.20:58:05.89#ibcon#read 4, iclass 3, count 0 2006.285.20:58:05.89#ibcon#about to read 5, iclass 3, count 0 2006.285.20:58:05.89#ibcon#read 5, iclass 3, count 0 2006.285.20:58:05.89#ibcon#about to read 6, iclass 3, count 0 2006.285.20:58:05.89#ibcon#read 6, iclass 3, count 0 2006.285.20:58:05.89#ibcon#end of sib2, iclass 3, count 0 2006.285.20:58:05.89#ibcon#*mode == 0, iclass 3, count 0 2006.285.20:58:05.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.20:58:05.89#ibcon#[27=USB\r\n] 2006.285.20:58:05.89#ibcon#*before write, iclass 3, count 0 2006.285.20:58:05.89#ibcon#enter sib2, iclass 3, count 0 2006.285.20:58:05.89#ibcon#flushed, iclass 3, count 0 2006.285.20:58:05.89#ibcon#about to write, iclass 3, count 0 2006.285.20:58:05.89#ibcon#wrote, iclass 3, count 0 2006.285.20:58:05.89#ibcon#about to read 3, iclass 3, count 0 2006.285.20:58:05.92#ibcon#read 3, iclass 3, count 0 2006.285.20:58:05.92#ibcon#about to read 4, iclass 3, count 0 2006.285.20:58:05.92#ibcon#read 4, iclass 3, count 0 2006.285.20:58:05.92#ibcon#about to read 5, iclass 3, count 0 2006.285.20:58:05.92#ibcon#read 5, iclass 3, count 0 2006.285.20:58:05.92#ibcon#about to read 6, iclass 3, count 0 2006.285.20:58:05.92#ibcon#read 6, iclass 3, count 0 2006.285.20:58:05.92#ibcon#end of sib2, iclass 3, count 0 2006.285.20:58:05.92#ibcon#*after write, iclass 3, count 0 2006.285.20:58:05.92#ibcon#*before return 0, iclass 3, count 0 2006.285.20:58:05.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:58:05.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.20:58:05.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.20:58:05.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.20:58:05.92$vck44/vblo=2,634.99 2006.285.20:58:05.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.20:58:05.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.20:58:05.92#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:05.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:58:05.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:58:05.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:58:05.92#ibcon#enter wrdev, iclass 5, count 0 2006.285.20:58:05.92#ibcon#first serial, iclass 5, count 0 2006.285.20:58:05.92#ibcon#enter sib2, iclass 5, count 0 2006.285.20:58:05.92#ibcon#flushed, iclass 5, count 0 2006.285.20:58:05.92#ibcon#about to write, iclass 5, count 0 2006.285.20:58:05.92#ibcon#wrote, iclass 5, count 0 2006.285.20:58:05.92#ibcon#about to read 3, iclass 5, count 0 2006.285.20:58:05.94#ibcon#read 3, iclass 5, count 0 2006.285.20:58:05.94#ibcon#about to read 4, iclass 5, count 0 2006.285.20:58:05.94#ibcon#read 4, iclass 5, count 0 2006.285.20:58:05.94#ibcon#about to read 5, iclass 5, count 0 2006.285.20:58:05.94#ibcon#read 5, iclass 5, count 0 2006.285.20:58:05.94#ibcon#about to read 6, iclass 5, count 0 2006.285.20:58:05.94#ibcon#read 6, iclass 5, count 0 2006.285.20:58:05.94#ibcon#end of sib2, iclass 5, count 0 2006.285.20:58:05.94#ibcon#*mode == 0, iclass 5, count 0 2006.285.20:58:05.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.20:58:05.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.20:58:05.94#ibcon#*before write, iclass 5, count 0 2006.285.20:58:05.94#ibcon#enter sib2, iclass 5, count 0 2006.285.20:58:05.94#ibcon#flushed, iclass 5, count 0 2006.285.20:58:05.94#ibcon#about to write, iclass 5, count 0 2006.285.20:58:05.94#ibcon#wrote, iclass 5, count 0 2006.285.20:58:05.94#ibcon#about to read 3, iclass 5, count 0 2006.285.20:58:05.98#ibcon#read 3, iclass 5, count 0 2006.285.20:58:05.98#ibcon#about to read 4, iclass 5, count 0 2006.285.20:58:05.98#ibcon#read 4, iclass 5, count 0 2006.285.20:58:05.98#ibcon#about to read 5, iclass 5, count 0 2006.285.20:58:05.98#ibcon#read 5, iclass 5, count 0 2006.285.20:58:05.98#ibcon#about to read 6, iclass 5, count 0 2006.285.20:58:05.98#ibcon#read 6, iclass 5, count 0 2006.285.20:58:05.98#ibcon#end of sib2, iclass 5, count 0 2006.285.20:58:05.98#ibcon#*after write, iclass 5, count 0 2006.285.20:58:05.98#ibcon#*before return 0, iclass 5, count 0 2006.285.20:58:05.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:58:05.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.20:58:05.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.20:58:05.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.20:58:05.98$vck44/vb=2,5 2006.285.20:58:05.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.20:58:05.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.20:58:05.98#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:05.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:58:06.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:58:06.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:58:06.04#ibcon#enter wrdev, iclass 7, count 2 2006.285.20:58:06.04#ibcon#first serial, iclass 7, count 2 2006.285.20:58:06.04#ibcon#enter sib2, iclass 7, count 2 2006.285.20:58:06.04#ibcon#flushed, iclass 7, count 2 2006.285.20:58:06.04#ibcon#about to write, iclass 7, count 2 2006.285.20:58:06.04#ibcon#wrote, iclass 7, count 2 2006.285.20:58:06.04#ibcon#about to read 3, iclass 7, count 2 2006.285.20:58:06.06#ibcon#read 3, iclass 7, count 2 2006.285.20:58:06.06#ibcon#about to read 4, iclass 7, count 2 2006.285.20:58:06.06#ibcon#read 4, iclass 7, count 2 2006.285.20:58:06.06#ibcon#about to read 5, iclass 7, count 2 2006.285.20:58:06.06#ibcon#read 5, iclass 7, count 2 2006.285.20:58:06.06#ibcon#about to read 6, iclass 7, count 2 2006.285.20:58:06.06#ibcon#read 6, iclass 7, count 2 2006.285.20:58:06.06#ibcon#end of sib2, iclass 7, count 2 2006.285.20:58:06.06#ibcon#*mode == 0, iclass 7, count 2 2006.285.20:58:06.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.20:58:06.06#ibcon#[27=AT02-05\r\n] 2006.285.20:58:06.06#ibcon#*before write, iclass 7, count 2 2006.285.20:58:06.06#ibcon#enter sib2, iclass 7, count 2 2006.285.20:58:06.06#ibcon#flushed, iclass 7, count 2 2006.285.20:58:06.06#ibcon#about to write, iclass 7, count 2 2006.285.20:58:06.06#ibcon#wrote, iclass 7, count 2 2006.285.20:58:06.06#ibcon#about to read 3, iclass 7, count 2 2006.285.20:58:06.09#ibcon#read 3, iclass 7, count 2 2006.285.20:58:06.09#ibcon#about to read 4, iclass 7, count 2 2006.285.20:58:06.09#ibcon#read 4, iclass 7, count 2 2006.285.20:58:06.09#ibcon#about to read 5, iclass 7, count 2 2006.285.20:58:06.09#ibcon#read 5, iclass 7, count 2 2006.285.20:58:06.09#ibcon#about to read 6, iclass 7, count 2 2006.285.20:58:06.09#ibcon#read 6, iclass 7, count 2 2006.285.20:58:06.09#ibcon#end of sib2, iclass 7, count 2 2006.285.20:58:06.09#ibcon#*after write, iclass 7, count 2 2006.285.20:58:06.09#ibcon#*before return 0, iclass 7, count 2 2006.285.20:58:06.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:58:06.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.20:58:06.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.20:58:06.09#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:06.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:58:06.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:58:06.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:58:06.21#ibcon#enter wrdev, iclass 7, count 0 2006.285.20:58:06.21#ibcon#first serial, iclass 7, count 0 2006.285.20:58:06.21#ibcon#enter sib2, iclass 7, count 0 2006.285.20:58:06.21#ibcon#flushed, iclass 7, count 0 2006.285.20:58:06.21#ibcon#about to write, iclass 7, count 0 2006.285.20:58:06.21#ibcon#wrote, iclass 7, count 0 2006.285.20:58:06.21#ibcon#about to read 3, iclass 7, count 0 2006.285.20:58:06.23#ibcon#read 3, iclass 7, count 0 2006.285.20:58:06.23#ibcon#about to read 4, iclass 7, count 0 2006.285.20:58:06.23#ibcon#read 4, iclass 7, count 0 2006.285.20:58:06.23#ibcon#about to read 5, iclass 7, count 0 2006.285.20:58:06.23#ibcon#read 5, iclass 7, count 0 2006.285.20:58:06.23#ibcon#about to read 6, iclass 7, count 0 2006.285.20:58:06.23#ibcon#read 6, iclass 7, count 0 2006.285.20:58:06.23#ibcon#end of sib2, iclass 7, count 0 2006.285.20:58:06.23#ibcon#*mode == 0, iclass 7, count 0 2006.285.20:58:06.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.20:58:06.23#ibcon#[27=USB\r\n] 2006.285.20:58:06.23#ibcon#*before write, iclass 7, count 0 2006.285.20:58:06.23#ibcon#enter sib2, iclass 7, count 0 2006.285.20:58:06.23#ibcon#flushed, iclass 7, count 0 2006.285.20:58:06.23#ibcon#about to write, iclass 7, count 0 2006.285.20:58:06.23#ibcon#wrote, iclass 7, count 0 2006.285.20:58:06.23#ibcon#about to read 3, iclass 7, count 0 2006.285.20:58:06.26#ibcon#read 3, iclass 7, count 0 2006.285.20:58:06.26#ibcon#about to read 4, iclass 7, count 0 2006.285.20:58:06.26#ibcon#read 4, iclass 7, count 0 2006.285.20:58:06.26#ibcon#about to read 5, iclass 7, count 0 2006.285.20:58:06.26#ibcon#read 5, iclass 7, count 0 2006.285.20:58:06.26#ibcon#about to read 6, iclass 7, count 0 2006.285.20:58:06.26#ibcon#read 6, iclass 7, count 0 2006.285.20:58:06.26#ibcon#end of sib2, iclass 7, count 0 2006.285.20:58:06.26#ibcon#*after write, iclass 7, count 0 2006.285.20:58:06.26#ibcon#*before return 0, iclass 7, count 0 2006.285.20:58:06.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:58:06.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.20:58:06.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.20:58:06.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.20:58:06.26$vck44/vblo=3,649.99 2006.285.20:58:06.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.20:58:06.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.20:58:06.26#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:06.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:58:06.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:58:06.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:58:06.26#ibcon#enter wrdev, iclass 11, count 0 2006.285.20:58:06.26#ibcon#first serial, iclass 11, count 0 2006.285.20:58:06.26#ibcon#enter sib2, iclass 11, count 0 2006.285.20:58:06.26#ibcon#flushed, iclass 11, count 0 2006.285.20:58:06.26#ibcon#about to write, iclass 11, count 0 2006.285.20:58:06.26#ibcon#wrote, iclass 11, count 0 2006.285.20:58:06.26#ibcon#about to read 3, iclass 11, count 0 2006.285.20:58:06.28#ibcon#read 3, iclass 11, count 0 2006.285.20:58:06.28#ibcon#about to read 4, iclass 11, count 0 2006.285.20:58:06.28#ibcon#read 4, iclass 11, count 0 2006.285.20:58:06.28#ibcon#about to read 5, iclass 11, count 0 2006.285.20:58:06.28#ibcon#read 5, iclass 11, count 0 2006.285.20:58:06.28#ibcon#about to read 6, iclass 11, count 0 2006.285.20:58:06.28#ibcon#read 6, iclass 11, count 0 2006.285.20:58:06.28#ibcon#end of sib2, iclass 11, count 0 2006.285.20:58:06.28#ibcon#*mode == 0, iclass 11, count 0 2006.285.20:58:06.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.20:58:06.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.20:58:06.28#ibcon#*before write, iclass 11, count 0 2006.285.20:58:06.28#ibcon#enter sib2, iclass 11, count 0 2006.285.20:58:06.28#ibcon#flushed, iclass 11, count 0 2006.285.20:58:06.28#ibcon#about to write, iclass 11, count 0 2006.285.20:58:06.28#ibcon#wrote, iclass 11, count 0 2006.285.20:58:06.28#ibcon#about to read 3, iclass 11, count 0 2006.285.20:58:06.32#ibcon#read 3, iclass 11, count 0 2006.285.20:58:06.32#ibcon#about to read 4, iclass 11, count 0 2006.285.20:58:06.32#ibcon#read 4, iclass 11, count 0 2006.285.20:58:06.32#ibcon#about to read 5, iclass 11, count 0 2006.285.20:58:06.32#ibcon#read 5, iclass 11, count 0 2006.285.20:58:06.32#ibcon#about to read 6, iclass 11, count 0 2006.285.20:58:06.32#ibcon#read 6, iclass 11, count 0 2006.285.20:58:06.32#ibcon#end of sib2, iclass 11, count 0 2006.285.20:58:06.32#ibcon#*after write, iclass 11, count 0 2006.285.20:58:06.32#ibcon#*before return 0, iclass 11, count 0 2006.285.20:58:06.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:58:06.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.20:58:06.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.20:58:06.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.20:58:06.32$vck44/vb=3,4 2006.285.20:58:06.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.20:58:06.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.20:58:06.32#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:06.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:58:06.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:58:06.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:58:06.38#ibcon#enter wrdev, iclass 13, count 2 2006.285.20:58:06.38#ibcon#first serial, iclass 13, count 2 2006.285.20:58:06.38#ibcon#enter sib2, iclass 13, count 2 2006.285.20:58:06.38#ibcon#flushed, iclass 13, count 2 2006.285.20:58:06.38#ibcon#about to write, iclass 13, count 2 2006.285.20:58:06.38#ibcon#wrote, iclass 13, count 2 2006.285.20:58:06.38#ibcon#about to read 3, iclass 13, count 2 2006.285.20:58:06.40#ibcon#read 3, iclass 13, count 2 2006.285.20:58:06.40#ibcon#about to read 4, iclass 13, count 2 2006.285.20:58:06.40#ibcon#read 4, iclass 13, count 2 2006.285.20:58:06.40#ibcon#about to read 5, iclass 13, count 2 2006.285.20:58:06.40#ibcon#read 5, iclass 13, count 2 2006.285.20:58:06.40#ibcon#about to read 6, iclass 13, count 2 2006.285.20:58:06.40#ibcon#read 6, iclass 13, count 2 2006.285.20:58:06.40#ibcon#end of sib2, iclass 13, count 2 2006.285.20:58:06.40#ibcon#*mode == 0, iclass 13, count 2 2006.285.20:58:06.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.20:58:06.40#ibcon#[27=AT03-04\r\n] 2006.285.20:58:06.40#ibcon#*before write, iclass 13, count 2 2006.285.20:58:06.40#ibcon#enter sib2, iclass 13, count 2 2006.285.20:58:06.40#ibcon#flushed, iclass 13, count 2 2006.285.20:58:06.40#ibcon#about to write, iclass 13, count 2 2006.285.20:58:06.40#ibcon#wrote, iclass 13, count 2 2006.285.20:58:06.40#ibcon#about to read 3, iclass 13, count 2 2006.285.20:58:06.43#ibcon#read 3, iclass 13, count 2 2006.285.20:58:06.43#ibcon#about to read 4, iclass 13, count 2 2006.285.20:58:06.43#ibcon#read 4, iclass 13, count 2 2006.285.20:58:06.43#ibcon#about to read 5, iclass 13, count 2 2006.285.20:58:06.43#ibcon#read 5, iclass 13, count 2 2006.285.20:58:06.43#ibcon#about to read 6, iclass 13, count 2 2006.285.20:58:06.43#ibcon#read 6, iclass 13, count 2 2006.285.20:58:06.43#ibcon#end of sib2, iclass 13, count 2 2006.285.20:58:06.43#ibcon#*after write, iclass 13, count 2 2006.285.20:58:06.43#ibcon#*before return 0, iclass 13, count 2 2006.285.20:58:06.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:58:06.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.20:58:06.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.20:58:06.43#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:06.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:58:06.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:58:06.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:58:06.55#ibcon#enter wrdev, iclass 13, count 0 2006.285.20:58:06.55#ibcon#first serial, iclass 13, count 0 2006.285.20:58:06.55#ibcon#enter sib2, iclass 13, count 0 2006.285.20:58:06.55#ibcon#flushed, iclass 13, count 0 2006.285.20:58:06.55#ibcon#about to write, iclass 13, count 0 2006.285.20:58:06.55#ibcon#wrote, iclass 13, count 0 2006.285.20:58:06.55#ibcon#about to read 3, iclass 13, count 0 2006.285.20:58:06.57#ibcon#read 3, iclass 13, count 0 2006.285.20:58:06.57#ibcon#about to read 4, iclass 13, count 0 2006.285.20:58:06.57#ibcon#read 4, iclass 13, count 0 2006.285.20:58:06.57#ibcon#about to read 5, iclass 13, count 0 2006.285.20:58:06.57#ibcon#read 5, iclass 13, count 0 2006.285.20:58:06.57#ibcon#about to read 6, iclass 13, count 0 2006.285.20:58:06.57#ibcon#read 6, iclass 13, count 0 2006.285.20:58:06.57#ibcon#end of sib2, iclass 13, count 0 2006.285.20:58:06.57#ibcon#*mode == 0, iclass 13, count 0 2006.285.20:58:06.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.20:58:06.57#ibcon#[27=USB\r\n] 2006.285.20:58:06.57#ibcon#*before write, iclass 13, count 0 2006.285.20:58:06.57#ibcon#enter sib2, iclass 13, count 0 2006.285.20:58:06.57#ibcon#flushed, iclass 13, count 0 2006.285.20:58:06.57#ibcon#about to write, iclass 13, count 0 2006.285.20:58:06.57#ibcon#wrote, iclass 13, count 0 2006.285.20:58:06.57#ibcon#about to read 3, iclass 13, count 0 2006.285.20:58:06.60#ibcon#read 3, iclass 13, count 0 2006.285.20:58:06.60#ibcon#about to read 4, iclass 13, count 0 2006.285.20:58:06.60#ibcon#read 4, iclass 13, count 0 2006.285.20:58:06.60#ibcon#about to read 5, iclass 13, count 0 2006.285.20:58:06.60#ibcon#read 5, iclass 13, count 0 2006.285.20:58:06.60#ibcon#about to read 6, iclass 13, count 0 2006.285.20:58:06.60#ibcon#read 6, iclass 13, count 0 2006.285.20:58:06.60#ibcon#end of sib2, iclass 13, count 0 2006.285.20:58:06.60#ibcon#*after write, iclass 13, count 0 2006.285.20:58:06.60#ibcon#*before return 0, iclass 13, count 0 2006.285.20:58:06.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:58:06.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.20:58:06.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.20:58:06.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.20:58:06.60$vck44/vblo=4,679.99 2006.285.20:58:06.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.20:58:06.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.20:58:06.60#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:06.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:58:06.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:58:06.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:58:06.60#ibcon#enter wrdev, iclass 15, count 0 2006.285.20:58:06.60#ibcon#first serial, iclass 15, count 0 2006.285.20:58:06.60#ibcon#enter sib2, iclass 15, count 0 2006.285.20:58:06.60#ibcon#flushed, iclass 15, count 0 2006.285.20:58:06.60#ibcon#about to write, iclass 15, count 0 2006.285.20:58:06.60#ibcon#wrote, iclass 15, count 0 2006.285.20:58:06.60#ibcon#about to read 3, iclass 15, count 0 2006.285.20:58:06.62#ibcon#read 3, iclass 15, count 0 2006.285.20:58:06.62#ibcon#about to read 4, iclass 15, count 0 2006.285.20:58:06.62#ibcon#read 4, iclass 15, count 0 2006.285.20:58:06.62#ibcon#about to read 5, iclass 15, count 0 2006.285.20:58:06.62#ibcon#read 5, iclass 15, count 0 2006.285.20:58:06.62#ibcon#about to read 6, iclass 15, count 0 2006.285.20:58:06.62#ibcon#read 6, iclass 15, count 0 2006.285.20:58:06.62#ibcon#end of sib2, iclass 15, count 0 2006.285.20:58:06.62#ibcon#*mode == 0, iclass 15, count 0 2006.285.20:58:06.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.20:58:06.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.20:58:06.62#ibcon#*before write, iclass 15, count 0 2006.285.20:58:06.62#ibcon#enter sib2, iclass 15, count 0 2006.285.20:58:06.62#ibcon#flushed, iclass 15, count 0 2006.285.20:58:06.62#ibcon#about to write, iclass 15, count 0 2006.285.20:58:06.62#ibcon#wrote, iclass 15, count 0 2006.285.20:58:06.62#ibcon#about to read 3, iclass 15, count 0 2006.285.20:58:06.66#ibcon#read 3, iclass 15, count 0 2006.285.20:58:06.66#ibcon#about to read 4, iclass 15, count 0 2006.285.20:58:06.66#ibcon#read 4, iclass 15, count 0 2006.285.20:58:06.66#ibcon#about to read 5, iclass 15, count 0 2006.285.20:58:06.66#ibcon#read 5, iclass 15, count 0 2006.285.20:58:06.66#ibcon#about to read 6, iclass 15, count 0 2006.285.20:58:06.66#ibcon#read 6, iclass 15, count 0 2006.285.20:58:06.66#ibcon#end of sib2, iclass 15, count 0 2006.285.20:58:06.66#ibcon#*after write, iclass 15, count 0 2006.285.20:58:06.66#ibcon#*before return 0, iclass 15, count 0 2006.285.20:58:06.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:58:06.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.20:58:06.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.20:58:06.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.20:58:06.66$vck44/vb=4,5 2006.285.20:58:06.90#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.20:58:06.90#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.20:58:06.90#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:06.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:58:06.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:58:06.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:58:06.90#ibcon#enter wrdev, iclass 17, count 2 2006.285.20:58:06.90#ibcon#first serial, iclass 17, count 2 2006.285.20:58:06.90#ibcon#enter sib2, iclass 17, count 2 2006.285.20:58:06.90#ibcon#flushed, iclass 17, count 2 2006.285.20:58:06.90#ibcon#about to write, iclass 17, count 2 2006.285.20:58:06.90#ibcon#wrote, iclass 17, count 2 2006.285.20:58:06.90#ibcon#about to read 3, iclass 17, count 2 2006.285.20:58:06.91#ibcon#read 3, iclass 17, count 2 2006.285.20:58:06.91#ibcon#about to read 4, iclass 17, count 2 2006.285.20:58:06.91#ibcon#read 4, iclass 17, count 2 2006.285.20:58:06.91#ibcon#about to read 5, iclass 17, count 2 2006.285.20:58:06.91#ibcon#read 5, iclass 17, count 2 2006.285.20:58:06.91#ibcon#about to read 6, iclass 17, count 2 2006.285.20:58:06.91#ibcon#read 6, iclass 17, count 2 2006.285.20:58:06.91#ibcon#end of sib2, iclass 17, count 2 2006.285.20:58:06.91#ibcon#*mode == 0, iclass 17, count 2 2006.285.20:58:06.91#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.20:58:06.91#ibcon#[27=AT04-05\r\n] 2006.285.20:58:06.91#ibcon#*before write, iclass 17, count 2 2006.285.20:58:06.91#ibcon#enter sib2, iclass 17, count 2 2006.285.20:58:06.91#ibcon#flushed, iclass 17, count 2 2006.285.20:58:06.91#ibcon#about to write, iclass 17, count 2 2006.285.20:58:06.91#ibcon#wrote, iclass 17, count 2 2006.285.20:58:06.91#ibcon#about to read 3, iclass 17, count 2 2006.285.20:58:06.94#ibcon#read 3, iclass 17, count 2 2006.285.20:58:06.94#ibcon#about to read 4, iclass 17, count 2 2006.285.20:58:06.94#ibcon#read 4, iclass 17, count 2 2006.285.20:58:06.94#ibcon#about to read 5, iclass 17, count 2 2006.285.20:58:06.94#ibcon#read 5, iclass 17, count 2 2006.285.20:58:06.94#ibcon#about to read 6, iclass 17, count 2 2006.285.20:58:06.94#ibcon#read 6, iclass 17, count 2 2006.285.20:58:06.94#ibcon#end of sib2, iclass 17, count 2 2006.285.20:58:06.94#ibcon#*after write, iclass 17, count 2 2006.285.20:58:06.94#ibcon#*before return 0, iclass 17, count 2 2006.285.20:58:06.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:58:06.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.20:58:06.94#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.20:58:06.94#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:06.94#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:58:07.06#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:58:07.06#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:58:07.06#ibcon#enter wrdev, iclass 17, count 0 2006.285.20:58:07.06#ibcon#first serial, iclass 17, count 0 2006.285.20:58:07.06#ibcon#enter sib2, iclass 17, count 0 2006.285.20:58:07.06#ibcon#flushed, iclass 17, count 0 2006.285.20:58:07.06#ibcon#about to write, iclass 17, count 0 2006.285.20:58:07.06#ibcon#wrote, iclass 17, count 0 2006.285.20:58:07.06#ibcon#about to read 3, iclass 17, count 0 2006.285.20:58:07.08#ibcon#read 3, iclass 17, count 0 2006.285.20:58:07.08#ibcon#about to read 4, iclass 17, count 0 2006.285.20:58:07.08#ibcon#read 4, iclass 17, count 0 2006.285.20:58:07.08#ibcon#about to read 5, iclass 17, count 0 2006.285.20:58:07.08#ibcon#read 5, iclass 17, count 0 2006.285.20:58:07.08#ibcon#about to read 6, iclass 17, count 0 2006.285.20:58:07.08#ibcon#read 6, iclass 17, count 0 2006.285.20:58:07.08#ibcon#end of sib2, iclass 17, count 0 2006.285.20:58:07.08#ibcon#*mode == 0, iclass 17, count 0 2006.285.20:58:07.08#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.20:58:07.08#ibcon#[27=USB\r\n] 2006.285.20:58:07.08#ibcon#*before write, iclass 17, count 0 2006.285.20:58:07.08#ibcon#enter sib2, iclass 17, count 0 2006.285.20:58:07.08#ibcon#flushed, iclass 17, count 0 2006.285.20:58:07.08#ibcon#about to write, iclass 17, count 0 2006.285.20:58:07.08#ibcon#wrote, iclass 17, count 0 2006.285.20:58:07.08#ibcon#about to read 3, iclass 17, count 0 2006.285.20:58:07.11#ibcon#read 3, iclass 17, count 0 2006.285.20:58:07.11#ibcon#about to read 4, iclass 17, count 0 2006.285.20:58:07.11#ibcon#read 4, iclass 17, count 0 2006.285.20:58:07.11#ibcon#about to read 5, iclass 17, count 0 2006.285.20:58:07.11#ibcon#read 5, iclass 17, count 0 2006.285.20:58:07.11#ibcon#about to read 6, iclass 17, count 0 2006.285.20:58:07.11#ibcon#read 6, iclass 17, count 0 2006.285.20:58:07.11#ibcon#end of sib2, iclass 17, count 0 2006.285.20:58:07.11#ibcon#*after write, iclass 17, count 0 2006.285.20:58:07.11#ibcon#*before return 0, iclass 17, count 0 2006.285.20:58:07.11#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:58:07.11#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.20:58:07.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.20:58:07.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.20:58:07.11$vck44/vblo=5,709.99 2006.285.20:58:07.11#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.20:58:07.11#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.20:58:07.11#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:07.11#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:58:07.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:58:07.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:58:07.11#ibcon#enter wrdev, iclass 19, count 0 2006.285.20:58:07.11#ibcon#first serial, iclass 19, count 0 2006.285.20:58:07.11#ibcon#enter sib2, iclass 19, count 0 2006.285.20:58:07.11#ibcon#flushed, iclass 19, count 0 2006.285.20:58:07.11#ibcon#about to write, iclass 19, count 0 2006.285.20:58:07.11#ibcon#wrote, iclass 19, count 0 2006.285.20:58:07.11#ibcon#about to read 3, iclass 19, count 0 2006.285.20:58:07.13#ibcon#read 3, iclass 19, count 0 2006.285.20:58:07.13#ibcon#about to read 4, iclass 19, count 0 2006.285.20:58:07.13#ibcon#read 4, iclass 19, count 0 2006.285.20:58:07.13#ibcon#about to read 5, iclass 19, count 0 2006.285.20:58:07.13#ibcon#read 5, iclass 19, count 0 2006.285.20:58:07.13#ibcon#about to read 6, iclass 19, count 0 2006.285.20:58:07.13#ibcon#read 6, iclass 19, count 0 2006.285.20:58:07.13#ibcon#end of sib2, iclass 19, count 0 2006.285.20:58:07.13#ibcon#*mode == 0, iclass 19, count 0 2006.285.20:58:07.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.20:58:07.13#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.20:58:07.13#ibcon#*before write, iclass 19, count 0 2006.285.20:58:07.13#ibcon#enter sib2, iclass 19, count 0 2006.285.20:58:07.13#ibcon#flushed, iclass 19, count 0 2006.285.20:58:07.13#ibcon#about to write, iclass 19, count 0 2006.285.20:58:07.13#ibcon#wrote, iclass 19, count 0 2006.285.20:58:07.13#ibcon#about to read 3, iclass 19, count 0 2006.285.20:58:07.17#ibcon#read 3, iclass 19, count 0 2006.285.20:58:07.17#ibcon#about to read 4, iclass 19, count 0 2006.285.20:58:07.17#ibcon#read 4, iclass 19, count 0 2006.285.20:58:07.17#ibcon#about to read 5, iclass 19, count 0 2006.285.20:58:07.17#ibcon#read 5, iclass 19, count 0 2006.285.20:58:07.17#ibcon#about to read 6, iclass 19, count 0 2006.285.20:58:07.17#ibcon#read 6, iclass 19, count 0 2006.285.20:58:07.17#ibcon#end of sib2, iclass 19, count 0 2006.285.20:58:07.17#ibcon#*after write, iclass 19, count 0 2006.285.20:58:07.17#ibcon#*before return 0, iclass 19, count 0 2006.285.20:58:07.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:58:07.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.20:58:07.17#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.20:58:07.17#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.20:58:07.17$vck44/vb=5,4 2006.285.20:58:07.17#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.20:58:07.17#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.20:58:07.17#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:07.17#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:58:07.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:58:07.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:58:07.23#ibcon#enter wrdev, iclass 21, count 2 2006.285.20:58:07.23#ibcon#first serial, iclass 21, count 2 2006.285.20:58:07.23#ibcon#enter sib2, iclass 21, count 2 2006.285.20:58:07.23#ibcon#flushed, iclass 21, count 2 2006.285.20:58:07.23#ibcon#about to write, iclass 21, count 2 2006.285.20:58:07.23#ibcon#wrote, iclass 21, count 2 2006.285.20:58:07.23#ibcon#about to read 3, iclass 21, count 2 2006.285.20:58:07.25#ibcon#read 3, iclass 21, count 2 2006.285.20:58:07.25#ibcon#about to read 4, iclass 21, count 2 2006.285.20:58:07.25#ibcon#read 4, iclass 21, count 2 2006.285.20:58:07.25#ibcon#about to read 5, iclass 21, count 2 2006.285.20:58:07.25#ibcon#read 5, iclass 21, count 2 2006.285.20:58:07.25#ibcon#about to read 6, iclass 21, count 2 2006.285.20:58:07.25#ibcon#read 6, iclass 21, count 2 2006.285.20:58:07.25#ibcon#end of sib2, iclass 21, count 2 2006.285.20:58:07.25#ibcon#*mode == 0, iclass 21, count 2 2006.285.20:58:07.25#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.20:58:07.25#ibcon#[27=AT05-04\r\n] 2006.285.20:58:07.25#ibcon#*before write, iclass 21, count 2 2006.285.20:58:07.25#ibcon#enter sib2, iclass 21, count 2 2006.285.20:58:07.25#ibcon#flushed, iclass 21, count 2 2006.285.20:58:07.25#ibcon#about to write, iclass 21, count 2 2006.285.20:58:07.25#ibcon#wrote, iclass 21, count 2 2006.285.20:58:07.25#ibcon#about to read 3, iclass 21, count 2 2006.285.20:58:07.28#ibcon#read 3, iclass 21, count 2 2006.285.20:58:07.28#ibcon#about to read 4, iclass 21, count 2 2006.285.20:58:07.28#ibcon#read 4, iclass 21, count 2 2006.285.20:58:07.28#ibcon#about to read 5, iclass 21, count 2 2006.285.20:58:07.28#ibcon#read 5, iclass 21, count 2 2006.285.20:58:07.28#ibcon#about to read 6, iclass 21, count 2 2006.285.20:58:07.28#ibcon#read 6, iclass 21, count 2 2006.285.20:58:07.28#ibcon#end of sib2, iclass 21, count 2 2006.285.20:58:07.28#ibcon#*after write, iclass 21, count 2 2006.285.20:58:07.28#ibcon#*before return 0, iclass 21, count 2 2006.285.20:58:07.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:58:07.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.20:58:07.28#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.20:58:07.28#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:07.28#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:58:07.40#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:58:07.40#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:58:07.40#ibcon#enter wrdev, iclass 21, count 0 2006.285.20:58:07.40#ibcon#first serial, iclass 21, count 0 2006.285.20:58:07.40#ibcon#enter sib2, iclass 21, count 0 2006.285.20:58:07.40#ibcon#flushed, iclass 21, count 0 2006.285.20:58:07.40#ibcon#about to write, iclass 21, count 0 2006.285.20:58:07.40#ibcon#wrote, iclass 21, count 0 2006.285.20:58:07.40#ibcon#about to read 3, iclass 21, count 0 2006.285.20:58:07.42#ibcon#read 3, iclass 21, count 0 2006.285.20:58:07.42#ibcon#about to read 4, iclass 21, count 0 2006.285.20:58:07.42#ibcon#read 4, iclass 21, count 0 2006.285.20:58:07.42#ibcon#about to read 5, iclass 21, count 0 2006.285.20:58:07.42#ibcon#read 5, iclass 21, count 0 2006.285.20:58:07.42#ibcon#about to read 6, iclass 21, count 0 2006.285.20:58:07.42#ibcon#read 6, iclass 21, count 0 2006.285.20:58:07.42#ibcon#end of sib2, iclass 21, count 0 2006.285.20:58:07.42#ibcon#*mode == 0, iclass 21, count 0 2006.285.20:58:07.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.20:58:07.42#ibcon#[27=USB\r\n] 2006.285.20:58:07.42#ibcon#*before write, iclass 21, count 0 2006.285.20:58:07.42#ibcon#enter sib2, iclass 21, count 0 2006.285.20:58:07.42#ibcon#flushed, iclass 21, count 0 2006.285.20:58:07.42#ibcon#about to write, iclass 21, count 0 2006.285.20:58:07.42#ibcon#wrote, iclass 21, count 0 2006.285.20:58:07.42#ibcon#about to read 3, iclass 21, count 0 2006.285.20:58:07.45#ibcon#read 3, iclass 21, count 0 2006.285.20:58:07.45#ibcon#about to read 4, iclass 21, count 0 2006.285.20:58:07.45#ibcon#read 4, iclass 21, count 0 2006.285.20:58:07.45#ibcon#about to read 5, iclass 21, count 0 2006.285.20:58:07.45#ibcon#read 5, iclass 21, count 0 2006.285.20:58:07.45#ibcon#about to read 6, iclass 21, count 0 2006.285.20:58:07.45#ibcon#read 6, iclass 21, count 0 2006.285.20:58:07.45#ibcon#end of sib2, iclass 21, count 0 2006.285.20:58:07.45#ibcon#*after write, iclass 21, count 0 2006.285.20:58:07.45#ibcon#*before return 0, iclass 21, count 0 2006.285.20:58:07.45#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:58:07.45#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.20:58:07.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.20:58:07.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.20:58:07.45$vck44/vblo=6,719.99 2006.285.20:58:07.45#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.20:58:07.45#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.20:58:07.45#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:07.45#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:58:07.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:58:07.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:58:07.45#ibcon#enter wrdev, iclass 23, count 0 2006.285.20:58:07.45#ibcon#first serial, iclass 23, count 0 2006.285.20:58:07.45#ibcon#enter sib2, iclass 23, count 0 2006.285.20:58:07.45#ibcon#flushed, iclass 23, count 0 2006.285.20:58:07.45#ibcon#about to write, iclass 23, count 0 2006.285.20:58:07.45#ibcon#wrote, iclass 23, count 0 2006.285.20:58:07.45#ibcon#about to read 3, iclass 23, count 0 2006.285.20:58:07.47#ibcon#read 3, iclass 23, count 0 2006.285.20:58:07.47#ibcon#about to read 4, iclass 23, count 0 2006.285.20:58:07.47#ibcon#read 4, iclass 23, count 0 2006.285.20:58:07.47#ibcon#about to read 5, iclass 23, count 0 2006.285.20:58:07.47#ibcon#read 5, iclass 23, count 0 2006.285.20:58:07.47#ibcon#about to read 6, iclass 23, count 0 2006.285.20:58:07.47#ibcon#read 6, iclass 23, count 0 2006.285.20:58:07.47#ibcon#end of sib2, iclass 23, count 0 2006.285.20:58:07.47#ibcon#*mode == 0, iclass 23, count 0 2006.285.20:58:07.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.20:58:07.47#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.20:58:07.47#ibcon#*before write, iclass 23, count 0 2006.285.20:58:07.47#ibcon#enter sib2, iclass 23, count 0 2006.285.20:58:07.47#ibcon#flushed, iclass 23, count 0 2006.285.20:58:07.47#ibcon#about to write, iclass 23, count 0 2006.285.20:58:07.47#ibcon#wrote, iclass 23, count 0 2006.285.20:58:07.47#ibcon#about to read 3, iclass 23, count 0 2006.285.20:58:07.51#ibcon#read 3, iclass 23, count 0 2006.285.20:58:07.51#ibcon#about to read 4, iclass 23, count 0 2006.285.20:58:07.51#ibcon#read 4, iclass 23, count 0 2006.285.20:58:07.51#ibcon#about to read 5, iclass 23, count 0 2006.285.20:58:07.51#ibcon#read 5, iclass 23, count 0 2006.285.20:58:07.51#ibcon#about to read 6, iclass 23, count 0 2006.285.20:58:07.51#ibcon#read 6, iclass 23, count 0 2006.285.20:58:07.51#ibcon#end of sib2, iclass 23, count 0 2006.285.20:58:07.51#ibcon#*after write, iclass 23, count 0 2006.285.20:58:07.51#ibcon#*before return 0, iclass 23, count 0 2006.285.20:58:07.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:58:07.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.20:58:07.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.20:58:07.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.20:58:07.51$vck44/vb=6,3 2006.285.20:58:07.51#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.20:58:07.51#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.20:58:07.51#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:07.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:58:07.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:58:07.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:58:07.57#ibcon#enter wrdev, iclass 25, count 2 2006.285.20:58:07.57#ibcon#first serial, iclass 25, count 2 2006.285.20:58:07.57#ibcon#enter sib2, iclass 25, count 2 2006.285.20:58:07.57#ibcon#flushed, iclass 25, count 2 2006.285.20:58:07.57#ibcon#about to write, iclass 25, count 2 2006.285.20:58:07.57#ibcon#wrote, iclass 25, count 2 2006.285.20:58:07.57#ibcon#about to read 3, iclass 25, count 2 2006.285.20:58:07.59#ibcon#read 3, iclass 25, count 2 2006.285.20:58:07.59#ibcon#about to read 4, iclass 25, count 2 2006.285.20:58:07.59#ibcon#read 4, iclass 25, count 2 2006.285.20:58:07.59#ibcon#about to read 5, iclass 25, count 2 2006.285.20:58:07.59#ibcon#read 5, iclass 25, count 2 2006.285.20:58:07.59#ibcon#about to read 6, iclass 25, count 2 2006.285.20:58:07.59#ibcon#read 6, iclass 25, count 2 2006.285.20:58:07.59#ibcon#end of sib2, iclass 25, count 2 2006.285.20:58:07.59#ibcon#*mode == 0, iclass 25, count 2 2006.285.20:58:07.59#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.20:58:07.59#ibcon#[27=AT06-03\r\n] 2006.285.20:58:07.59#ibcon#*before write, iclass 25, count 2 2006.285.20:58:07.59#ibcon#enter sib2, iclass 25, count 2 2006.285.20:58:07.59#ibcon#flushed, iclass 25, count 2 2006.285.20:58:07.59#ibcon#about to write, iclass 25, count 2 2006.285.20:58:07.59#ibcon#wrote, iclass 25, count 2 2006.285.20:58:07.59#ibcon#about to read 3, iclass 25, count 2 2006.285.20:58:07.62#ibcon#read 3, iclass 25, count 2 2006.285.20:58:07.62#ibcon#about to read 4, iclass 25, count 2 2006.285.20:58:07.62#ibcon#read 4, iclass 25, count 2 2006.285.20:58:07.62#ibcon#about to read 5, iclass 25, count 2 2006.285.20:58:07.62#ibcon#read 5, iclass 25, count 2 2006.285.20:58:07.62#ibcon#about to read 6, iclass 25, count 2 2006.285.20:58:07.62#ibcon#read 6, iclass 25, count 2 2006.285.20:58:07.62#ibcon#end of sib2, iclass 25, count 2 2006.285.20:58:07.62#ibcon#*after write, iclass 25, count 2 2006.285.20:58:07.62#ibcon#*before return 0, iclass 25, count 2 2006.285.20:58:07.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:58:07.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.20:58:07.62#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.20:58:07.62#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:07.62#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:58:07.74#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:58:07.74#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:58:07.74#ibcon#enter wrdev, iclass 25, count 0 2006.285.20:58:07.74#ibcon#first serial, iclass 25, count 0 2006.285.20:58:07.74#ibcon#enter sib2, iclass 25, count 0 2006.285.20:58:07.74#ibcon#flushed, iclass 25, count 0 2006.285.20:58:07.74#ibcon#about to write, iclass 25, count 0 2006.285.20:58:07.74#ibcon#wrote, iclass 25, count 0 2006.285.20:58:07.74#ibcon#about to read 3, iclass 25, count 0 2006.285.20:58:07.76#ibcon#read 3, iclass 25, count 0 2006.285.20:58:07.76#ibcon#about to read 4, iclass 25, count 0 2006.285.20:58:07.76#ibcon#read 4, iclass 25, count 0 2006.285.20:58:07.76#ibcon#about to read 5, iclass 25, count 0 2006.285.20:58:07.76#ibcon#read 5, iclass 25, count 0 2006.285.20:58:07.76#ibcon#about to read 6, iclass 25, count 0 2006.285.20:58:07.76#ibcon#read 6, iclass 25, count 0 2006.285.20:58:07.76#ibcon#end of sib2, iclass 25, count 0 2006.285.20:58:07.76#ibcon#*mode == 0, iclass 25, count 0 2006.285.20:58:08.00#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.20:58:08.00#ibcon#[27=USB\r\n] 2006.285.20:58:08.00#ibcon#*before write, iclass 25, count 0 2006.285.20:58:08.00#ibcon#enter sib2, iclass 25, count 0 2006.285.20:58:08.00#ibcon#flushed, iclass 25, count 0 2006.285.20:58:08.00#ibcon#about to write, iclass 25, count 0 2006.285.20:58:08.00#ibcon#wrote, iclass 25, count 0 2006.285.20:58:08.00#ibcon#about to read 3, iclass 25, count 0 2006.285.20:58:08.03#ibcon#read 3, iclass 25, count 0 2006.285.20:58:08.03#ibcon#about to read 4, iclass 25, count 0 2006.285.20:58:08.03#ibcon#read 4, iclass 25, count 0 2006.285.20:58:08.03#ibcon#about to read 5, iclass 25, count 0 2006.285.20:58:08.03#ibcon#read 5, iclass 25, count 0 2006.285.20:58:08.03#ibcon#about to read 6, iclass 25, count 0 2006.285.20:58:08.03#ibcon#read 6, iclass 25, count 0 2006.285.20:58:08.03#ibcon#end of sib2, iclass 25, count 0 2006.285.20:58:08.03#ibcon#*after write, iclass 25, count 0 2006.285.20:58:08.03#ibcon#*before return 0, iclass 25, count 0 2006.285.20:58:08.03#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:58:08.03#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.20:58:08.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.20:58:08.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.20:58:08.03$vck44/vblo=7,734.99 2006.285.20:58:08.03#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.20:58:08.03#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.20:58:08.03#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:08.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:58:08.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:58:08.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:58:08.03#ibcon#enter wrdev, iclass 27, count 0 2006.285.20:58:08.03#ibcon#first serial, iclass 27, count 0 2006.285.20:58:08.03#ibcon#enter sib2, iclass 27, count 0 2006.285.20:58:08.03#ibcon#flushed, iclass 27, count 0 2006.285.20:58:08.03#ibcon#about to write, iclass 27, count 0 2006.285.20:58:08.03#ibcon#wrote, iclass 27, count 0 2006.285.20:58:08.03#ibcon#about to read 3, iclass 27, count 0 2006.285.20:58:08.05#ibcon#read 3, iclass 27, count 0 2006.285.20:58:08.05#ibcon#about to read 4, iclass 27, count 0 2006.285.20:58:08.05#ibcon#read 4, iclass 27, count 0 2006.285.20:58:08.05#ibcon#about to read 5, iclass 27, count 0 2006.285.20:58:08.05#ibcon#read 5, iclass 27, count 0 2006.285.20:58:08.05#ibcon#about to read 6, iclass 27, count 0 2006.285.20:58:08.05#ibcon#read 6, iclass 27, count 0 2006.285.20:58:08.05#ibcon#end of sib2, iclass 27, count 0 2006.285.20:58:08.05#ibcon#*mode == 0, iclass 27, count 0 2006.285.20:58:08.05#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.20:58:08.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.20:58:08.05#ibcon#*before write, iclass 27, count 0 2006.285.20:58:08.05#ibcon#enter sib2, iclass 27, count 0 2006.285.20:58:08.05#ibcon#flushed, iclass 27, count 0 2006.285.20:58:08.05#ibcon#about to write, iclass 27, count 0 2006.285.20:58:08.05#ibcon#wrote, iclass 27, count 0 2006.285.20:58:08.05#ibcon#about to read 3, iclass 27, count 0 2006.285.20:58:08.09#ibcon#read 3, iclass 27, count 0 2006.285.20:58:08.09#ibcon#about to read 4, iclass 27, count 0 2006.285.20:58:08.09#ibcon#read 4, iclass 27, count 0 2006.285.20:58:08.09#ibcon#about to read 5, iclass 27, count 0 2006.285.20:58:08.09#ibcon#read 5, iclass 27, count 0 2006.285.20:58:08.09#ibcon#about to read 6, iclass 27, count 0 2006.285.20:58:08.09#ibcon#read 6, iclass 27, count 0 2006.285.20:58:08.09#ibcon#end of sib2, iclass 27, count 0 2006.285.20:58:08.09#ibcon#*after write, iclass 27, count 0 2006.285.20:58:08.09#ibcon#*before return 0, iclass 27, count 0 2006.285.20:58:08.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:58:08.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.20:58:08.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.20:58:08.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.20:58:08.09$vck44/vb=7,4 2006.285.20:58:08.09#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.20:58:08.09#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.20:58:08.09#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:08.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:58:08.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:58:08.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:58:08.15#ibcon#enter wrdev, iclass 29, count 2 2006.285.20:58:08.15#ibcon#first serial, iclass 29, count 2 2006.285.20:58:08.15#ibcon#enter sib2, iclass 29, count 2 2006.285.20:58:08.15#ibcon#flushed, iclass 29, count 2 2006.285.20:58:08.15#ibcon#about to write, iclass 29, count 2 2006.285.20:58:08.15#ibcon#wrote, iclass 29, count 2 2006.285.20:58:08.15#ibcon#about to read 3, iclass 29, count 2 2006.285.20:58:08.17#ibcon#read 3, iclass 29, count 2 2006.285.20:58:08.17#ibcon#about to read 4, iclass 29, count 2 2006.285.20:58:08.17#ibcon#read 4, iclass 29, count 2 2006.285.20:58:08.17#ibcon#about to read 5, iclass 29, count 2 2006.285.20:58:08.17#ibcon#read 5, iclass 29, count 2 2006.285.20:58:08.17#ibcon#about to read 6, iclass 29, count 2 2006.285.20:58:08.17#ibcon#read 6, iclass 29, count 2 2006.285.20:58:08.17#ibcon#end of sib2, iclass 29, count 2 2006.285.20:58:08.17#ibcon#*mode == 0, iclass 29, count 2 2006.285.20:58:08.17#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.20:58:08.17#ibcon#[27=AT07-04\r\n] 2006.285.20:58:08.17#ibcon#*before write, iclass 29, count 2 2006.285.20:58:08.17#ibcon#enter sib2, iclass 29, count 2 2006.285.20:58:08.17#ibcon#flushed, iclass 29, count 2 2006.285.20:58:08.17#ibcon#about to write, iclass 29, count 2 2006.285.20:58:08.17#ibcon#wrote, iclass 29, count 2 2006.285.20:58:08.17#ibcon#about to read 3, iclass 29, count 2 2006.285.20:58:08.20#ibcon#read 3, iclass 29, count 2 2006.285.20:58:08.20#ibcon#about to read 4, iclass 29, count 2 2006.285.20:58:08.20#ibcon#read 4, iclass 29, count 2 2006.285.20:58:08.20#ibcon#about to read 5, iclass 29, count 2 2006.285.20:58:08.20#ibcon#read 5, iclass 29, count 2 2006.285.20:58:08.20#ibcon#about to read 6, iclass 29, count 2 2006.285.20:58:08.20#ibcon#read 6, iclass 29, count 2 2006.285.20:58:08.20#ibcon#end of sib2, iclass 29, count 2 2006.285.20:58:08.20#ibcon#*after write, iclass 29, count 2 2006.285.20:58:08.20#ibcon#*before return 0, iclass 29, count 2 2006.285.20:58:08.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:58:08.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.20:58:08.20#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.20:58:08.20#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:08.20#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:58:08.32#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:58:08.32#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:58:08.32#ibcon#enter wrdev, iclass 29, count 0 2006.285.20:58:08.32#ibcon#first serial, iclass 29, count 0 2006.285.20:58:08.32#ibcon#enter sib2, iclass 29, count 0 2006.285.20:58:08.32#ibcon#flushed, iclass 29, count 0 2006.285.20:58:08.32#ibcon#about to write, iclass 29, count 0 2006.285.20:58:08.32#ibcon#wrote, iclass 29, count 0 2006.285.20:58:08.32#ibcon#about to read 3, iclass 29, count 0 2006.285.20:58:08.34#ibcon#read 3, iclass 29, count 0 2006.285.20:58:08.34#ibcon#about to read 4, iclass 29, count 0 2006.285.20:58:08.34#ibcon#read 4, iclass 29, count 0 2006.285.20:58:08.34#ibcon#about to read 5, iclass 29, count 0 2006.285.20:58:08.34#ibcon#read 5, iclass 29, count 0 2006.285.20:58:08.34#ibcon#about to read 6, iclass 29, count 0 2006.285.20:58:08.34#ibcon#read 6, iclass 29, count 0 2006.285.20:58:08.34#ibcon#end of sib2, iclass 29, count 0 2006.285.20:58:08.34#ibcon#*mode == 0, iclass 29, count 0 2006.285.20:58:08.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.20:58:08.34#ibcon#[27=USB\r\n] 2006.285.20:58:08.34#ibcon#*before write, iclass 29, count 0 2006.285.20:58:08.34#ibcon#enter sib2, iclass 29, count 0 2006.285.20:58:08.34#ibcon#flushed, iclass 29, count 0 2006.285.20:58:08.34#ibcon#about to write, iclass 29, count 0 2006.285.20:58:08.34#ibcon#wrote, iclass 29, count 0 2006.285.20:58:08.34#ibcon#about to read 3, iclass 29, count 0 2006.285.20:58:08.37#ibcon#read 3, iclass 29, count 0 2006.285.20:58:08.37#ibcon#about to read 4, iclass 29, count 0 2006.285.20:58:08.37#ibcon#read 4, iclass 29, count 0 2006.285.20:58:08.37#ibcon#about to read 5, iclass 29, count 0 2006.285.20:58:08.37#ibcon#read 5, iclass 29, count 0 2006.285.20:58:08.37#ibcon#about to read 6, iclass 29, count 0 2006.285.20:58:08.37#ibcon#read 6, iclass 29, count 0 2006.285.20:58:08.37#ibcon#end of sib2, iclass 29, count 0 2006.285.20:58:08.37#ibcon#*after write, iclass 29, count 0 2006.285.20:58:08.37#ibcon#*before return 0, iclass 29, count 0 2006.285.20:58:08.37#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:58:08.37#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.20:58:08.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.20:58:08.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.20:58:08.37$vck44/vblo=8,744.99 2006.285.20:58:08.37#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.20:58:08.37#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.20:58:08.37#ibcon#ireg 17 cls_cnt 0 2006.285.20:58:08.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:58:08.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:58:08.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:58:08.37#ibcon#enter wrdev, iclass 31, count 0 2006.285.20:58:08.37#ibcon#first serial, iclass 31, count 0 2006.285.20:58:08.37#ibcon#enter sib2, iclass 31, count 0 2006.285.20:58:08.37#ibcon#flushed, iclass 31, count 0 2006.285.20:58:08.37#ibcon#about to write, iclass 31, count 0 2006.285.20:58:08.37#ibcon#wrote, iclass 31, count 0 2006.285.20:58:08.37#ibcon#about to read 3, iclass 31, count 0 2006.285.20:58:08.39#ibcon#read 3, iclass 31, count 0 2006.285.20:58:08.39#ibcon#about to read 4, iclass 31, count 0 2006.285.20:58:08.39#ibcon#read 4, iclass 31, count 0 2006.285.20:58:08.39#ibcon#about to read 5, iclass 31, count 0 2006.285.20:58:08.39#ibcon#read 5, iclass 31, count 0 2006.285.20:58:08.39#ibcon#about to read 6, iclass 31, count 0 2006.285.20:58:08.39#ibcon#read 6, iclass 31, count 0 2006.285.20:58:08.39#ibcon#end of sib2, iclass 31, count 0 2006.285.20:58:08.39#ibcon#*mode == 0, iclass 31, count 0 2006.285.20:58:08.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.20:58:08.39#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.20:58:08.39#ibcon#*before write, iclass 31, count 0 2006.285.20:58:08.39#ibcon#enter sib2, iclass 31, count 0 2006.285.20:58:08.39#ibcon#flushed, iclass 31, count 0 2006.285.20:58:08.39#ibcon#about to write, iclass 31, count 0 2006.285.20:58:08.39#ibcon#wrote, iclass 31, count 0 2006.285.20:58:08.39#ibcon#about to read 3, iclass 31, count 0 2006.285.20:58:08.43#ibcon#read 3, iclass 31, count 0 2006.285.20:58:08.43#ibcon#about to read 4, iclass 31, count 0 2006.285.20:58:08.43#ibcon#read 4, iclass 31, count 0 2006.285.20:58:08.43#ibcon#about to read 5, iclass 31, count 0 2006.285.20:58:08.43#ibcon#read 5, iclass 31, count 0 2006.285.20:58:08.43#ibcon#about to read 6, iclass 31, count 0 2006.285.20:58:08.43#ibcon#read 6, iclass 31, count 0 2006.285.20:58:08.43#ibcon#end of sib2, iclass 31, count 0 2006.285.20:58:08.43#ibcon#*after write, iclass 31, count 0 2006.285.20:58:08.43#ibcon#*before return 0, iclass 31, count 0 2006.285.20:58:08.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:58:08.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.20:58:08.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.20:58:08.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.20:58:08.43$vck44/vb=8,4 2006.285.20:58:08.43#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.20:58:08.43#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.20:58:08.43#ibcon#ireg 11 cls_cnt 2 2006.285.20:58:08.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:58:08.49#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:58:08.49#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:58:08.49#ibcon#enter wrdev, iclass 33, count 2 2006.285.20:58:08.49#ibcon#first serial, iclass 33, count 2 2006.285.20:58:08.49#ibcon#enter sib2, iclass 33, count 2 2006.285.20:58:08.49#ibcon#flushed, iclass 33, count 2 2006.285.20:58:08.49#ibcon#about to write, iclass 33, count 2 2006.285.20:58:08.49#ibcon#wrote, iclass 33, count 2 2006.285.20:58:08.49#ibcon#about to read 3, iclass 33, count 2 2006.285.20:58:08.51#ibcon#read 3, iclass 33, count 2 2006.285.20:58:08.51#ibcon#about to read 4, iclass 33, count 2 2006.285.20:58:08.51#ibcon#read 4, iclass 33, count 2 2006.285.20:58:08.51#ibcon#about to read 5, iclass 33, count 2 2006.285.20:58:08.51#ibcon#read 5, iclass 33, count 2 2006.285.20:58:08.51#ibcon#about to read 6, iclass 33, count 2 2006.285.20:58:08.51#ibcon#read 6, iclass 33, count 2 2006.285.20:58:08.51#ibcon#end of sib2, iclass 33, count 2 2006.285.20:58:08.51#ibcon#*mode == 0, iclass 33, count 2 2006.285.20:58:08.51#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.20:58:08.51#ibcon#[27=AT08-04\r\n] 2006.285.20:58:08.51#ibcon#*before write, iclass 33, count 2 2006.285.20:58:08.51#ibcon#enter sib2, iclass 33, count 2 2006.285.20:58:08.51#ibcon#flushed, iclass 33, count 2 2006.285.20:58:08.51#ibcon#about to write, iclass 33, count 2 2006.285.20:58:08.51#ibcon#wrote, iclass 33, count 2 2006.285.20:58:08.51#ibcon#about to read 3, iclass 33, count 2 2006.285.20:58:08.54#ibcon#read 3, iclass 33, count 2 2006.285.20:58:08.54#ibcon#about to read 4, iclass 33, count 2 2006.285.20:58:08.54#ibcon#read 4, iclass 33, count 2 2006.285.20:58:08.54#ibcon#about to read 5, iclass 33, count 2 2006.285.20:58:08.54#ibcon#read 5, iclass 33, count 2 2006.285.20:58:08.54#ibcon#about to read 6, iclass 33, count 2 2006.285.20:58:08.54#ibcon#read 6, iclass 33, count 2 2006.285.20:58:08.54#ibcon#end of sib2, iclass 33, count 2 2006.285.20:58:08.54#ibcon#*after write, iclass 33, count 2 2006.285.20:58:08.54#ibcon#*before return 0, iclass 33, count 2 2006.285.20:58:08.54#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:58:08.54#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.20:58:08.54#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.20:58:08.54#ibcon#ireg 7 cls_cnt 0 2006.285.20:58:08.54#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:58:08.66#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:58:08.66#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:58:08.66#ibcon#enter wrdev, iclass 33, count 0 2006.285.20:58:08.66#ibcon#first serial, iclass 33, count 0 2006.285.20:58:08.66#ibcon#enter sib2, iclass 33, count 0 2006.285.20:58:08.66#ibcon#flushed, iclass 33, count 0 2006.285.20:58:08.66#ibcon#about to write, iclass 33, count 0 2006.285.20:58:08.66#ibcon#wrote, iclass 33, count 0 2006.285.20:58:08.66#ibcon#about to read 3, iclass 33, count 0 2006.285.20:58:08.68#ibcon#read 3, iclass 33, count 0 2006.285.20:58:08.68#ibcon#about to read 4, iclass 33, count 0 2006.285.20:58:08.68#ibcon#read 4, iclass 33, count 0 2006.285.20:58:08.68#ibcon#about to read 5, iclass 33, count 0 2006.285.20:58:08.68#ibcon#read 5, iclass 33, count 0 2006.285.20:58:08.68#ibcon#about to read 6, iclass 33, count 0 2006.285.20:58:08.68#ibcon#read 6, iclass 33, count 0 2006.285.20:58:08.68#ibcon#end of sib2, iclass 33, count 0 2006.285.20:58:08.68#ibcon#*mode == 0, iclass 33, count 0 2006.285.20:58:08.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.20:58:08.68#ibcon#[27=USB\r\n] 2006.285.20:58:08.68#ibcon#*before write, iclass 33, count 0 2006.285.20:58:08.68#ibcon#enter sib2, iclass 33, count 0 2006.285.20:58:08.68#ibcon#flushed, iclass 33, count 0 2006.285.20:58:08.68#ibcon#about to write, iclass 33, count 0 2006.285.20:58:08.68#ibcon#wrote, iclass 33, count 0 2006.285.20:58:08.68#ibcon#about to read 3, iclass 33, count 0 2006.285.20:58:08.71#ibcon#read 3, iclass 33, count 0 2006.285.20:58:08.71#ibcon#about to read 4, iclass 33, count 0 2006.285.20:58:08.71#ibcon#read 4, iclass 33, count 0 2006.285.20:58:08.71#ibcon#about to read 5, iclass 33, count 0 2006.285.20:58:08.71#ibcon#read 5, iclass 33, count 0 2006.285.20:58:08.71#ibcon#about to read 6, iclass 33, count 0 2006.285.20:58:08.71#ibcon#read 6, iclass 33, count 0 2006.285.20:58:08.71#ibcon#end of sib2, iclass 33, count 0 2006.285.20:58:08.71#ibcon#*after write, iclass 33, count 0 2006.285.20:58:08.71#ibcon#*before return 0, iclass 33, count 0 2006.285.20:58:08.71#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:58:08.71#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.20:58:08.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.20:58:08.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.20:58:08.71$vck44/vabw=wide 2006.285.20:58:08.71#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.20:58:08.71#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.20:58:08.71#ibcon#ireg 8 cls_cnt 0 2006.285.20:58:08.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:58:08.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:58:08.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:58:08.71#ibcon#enter wrdev, iclass 35, count 0 2006.285.20:58:08.71#ibcon#first serial, iclass 35, count 0 2006.285.20:58:08.71#ibcon#enter sib2, iclass 35, count 0 2006.285.20:58:08.71#ibcon#flushed, iclass 35, count 0 2006.285.20:58:08.71#ibcon#about to write, iclass 35, count 0 2006.285.20:58:08.71#ibcon#wrote, iclass 35, count 0 2006.285.20:58:08.71#ibcon#about to read 3, iclass 35, count 0 2006.285.20:58:08.73#ibcon#read 3, iclass 35, count 0 2006.285.20:58:08.78#ibcon#about to read 4, iclass 35, count 0 2006.285.20:58:08.78#ibcon#read 4, iclass 35, count 0 2006.285.20:58:08.78#ibcon#about to read 5, iclass 35, count 0 2006.285.20:58:08.78#ibcon#read 5, iclass 35, count 0 2006.285.20:58:08.78#ibcon#about to read 6, iclass 35, count 0 2006.285.20:58:08.78#ibcon#read 6, iclass 35, count 0 2006.285.20:58:08.78#ibcon#end of sib2, iclass 35, count 0 2006.285.20:58:08.78#ibcon#*mode == 0, iclass 35, count 0 2006.285.20:58:08.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.20:58:08.78#ibcon#[25=BW32\r\n] 2006.285.20:58:08.78#ibcon#*before write, iclass 35, count 0 2006.285.20:58:08.78#ibcon#enter sib2, iclass 35, count 0 2006.285.20:58:08.78#ibcon#flushed, iclass 35, count 0 2006.285.20:58:08.78#ibcon#about to write, iclass 35, count 0 2006.285.20:58:08.78#ibcon#wrote, iclass 35, count 0 2006.285.20:58:08.78#ibcon#about to read 3, iclass 35, count 0 2006.285.20:58:08.81#ibcon#read 3, iclass 35, count 0 2006.285.20:58:08.81#ibcon#about to read 4, iclass 35, count 0 2006.285.20:58:08.81#ibcon#read 4, iclass 35, count 0 2006.285.20:58:08.81#ibcon#about to read 5, iclass 35, count 0 2006.285.20:58:08.81#ibcon#read 5, iclass 35, count 0 2006.285.20:58:08.81#ibcon#about to read 6, iclass 35, count 0 2006.285.20:58:08.81#ibcon#read 6, iclass 35, count 0 2006.285.20:58:08.81#ibcon#end of sib2, iclass 35, count 0 2006.285.20:58:08.81#ibcon#*after write, iclass 35, count 0 2006.285.20:58:08.81#ibcon#*before return 0, iclass 35, count 0 2006.285.20:58:08.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:58:08.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.20:58:08.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.20:58:08.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.20:58:08.81$vck44/vbbw=wide 2006.285.20:58:08.81#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.20:58:08.81#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.20:58:08.81#ibcon#ireg 8 cls_cnt 0 2006.285.20:58:08.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:58:08.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:58:08.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:58:08.83#ibcon#enter wrdev, iclass 37, count 0 2006.285.20:58:08.83#ibcon#first serial, iclass 37, count 0 2006.285.20:58:08.83#ibcon#enter sib2, iclass 37, count 0 2006.285.20:58:08.83#ibcon#flushed, iclass 37, count 0 2006.285.20:58:08.83#ibcon#about to write, iclass 37, count 0 2006.285.20:58:08.83#ibcon#wrote, iclass 37, count 0 2006.285.20:58:08.83#ibcon#about to read 3, iclass 37, count 0 2006.285.20:58:08.85#ibcon#read 3, iclass 37, count 0 2006.285.20:58:08.85#ibcon#about to read 4, iclass 37, count 0 2006.285.20:58:08.85#ibcon#read 4, iclass 37, count 0 2006.285.20:58:08.85#ibcon#about to read 5, iclass 37, count 0 2006.285.20:58:08.85#ibcon#read 5, iclass 37, count 0 2006.285.20:58:08.85#ibcon#about to read 6, iclass 37, count 0 2006.285.20:58:08.85#ibcon#read 6, iclass 37, count 0 2006.285.20:58:08.85#ibcon#end of sib2, iclass 37, count 0 2006.285.20:58:08.85#ibcon#*mode == 0, iclass 37, count 0 2006.285.20:58:08.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.20:58:08.85#ibcon#[27=BW32\r\n] 2006.285.20:58:08.85#ibcon#*before write, iclass 37, count 0 2006.285.20:58:08.85#ibcon#enter sib2, iclass 37, count 0 2006.285.20:58:08.85#ibcon#flushed, iclass 37, count 0 2006.285.20:58:08.85#ibcon#about to write, iclass 37, count 0 2006.285.20:58:08.85#ibcon#wrote, iclass 37, count 0 2006.285.20:58:08.85#ibcon#about to read 3, iclass 37, count 0 2006.285.20:58:08.88#ibcon#read 3, iclass 37, count 0 2006.285.20:58:08.88#ibcon#about to read 4, iclass 37, count 0 2006.285.20:58:08.88#ibcon#read 4, iclass 37, count 0 2006.285.20:58:08.88#ibcon#about to read 5, iclass 37, count 0 2006.285.20:58:08.88#ibcon#read 5, iclass 37, count 0 2006.285.20:58:08.88#ibcon#about to read 6, iclass 37, count 0 2006.285.20:58:08.88#ibcon#read 6, iclass 37, count 0 2006.285.20:58:08.88#ibcon#end of sib2, iclass 37, count 0 2006.285.20:58:08.88#ibcon#*after write, iclass 37, count 0 2006.285.20:58:08.88#ibcon#*before return 0, iclass 37, count 0 2006.285.20:58:08.88#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:58:08.88#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.20:58:08.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.20:58:08.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.20:58:08.88$setupk4/ifdk4 2006.285.20:58:08.88$ifdk4/lo= 2006.285.20:58:08.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.20:58:08.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.20:58:08.88$ifdk4/patch= 2006.285.20:58:08.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.20:58:08.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.20:58:08.88$setupk4/!*+20s 2006.285.20:58:10.81#abcon#<5=/00 0.1 0.5 14.211001015.4\r\n> 2006.285.20:58:10.83#abcon#{5=INTERFACE CLEAR} 2006.285.20:58:10.89#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:58:20.98#abcon#<5=/00 0.1 0.5 14.211001015.4\r\n> 2006.285.20:58:21.00#abcon#{5=INTERFACE CLEAR} 2006.285.20:58:21.06#abcon#[5=S1D000X0/0*\r\n] 2006.285.20:58:21.29$setupk4/"tpicd 2006.285.20:58:21.29$setupk4/echo=off 2006.285.20:58:21.29$setupk4/xlog=off 2006.285.20:58:21.29:!2006.285.21:02:30 2006.285.20:58:52.14#trakl#Source acquired 2006.285.20:58:53.14#flagr#flagr/antenna,acquired 2006.285.21:02:30.00:preob 2006.285.21:02:30.14/onsource/TRACKING 2006.285.21:02:30.14:!2006.285.21:02:40 2006.285.21:02:40.00:"tape 2006.285.21:02:40.00:"st=record 2006.285.21:02:40.00:data_valid=on 2006.285.21:02:40.00:midob 2006.285.21:02:41.14/onsource/TRACKING 2006.285.21:02:41.14/wx/14.19,1015.4,100 2006.285.21:02:41.27/cable/+6.5106E-03 2006.285.21:02:42.36/va/01,07,usb,yes,32,35 2006.285.21:02:42.36/va/02,06,usb,yes,32,33 2006.285.21:02:42.36/va/03,07,usb,yes,32,34 2006.285.21:02:42.36/va/04,06,usb,yes,34,35 2006.285.21:02:42.36/va/05,03,usb,yes,33,33 2006.285.21:02:42.36/va/06,04,usb,yes,30,29 2006.285.21:02:42.36/va/07,04,usb,yes,30,31 2006.285.21:02:42.36/va/08,03,usb,yes,31,38 2006.285.21:02:42.59/valo/01,524.99,yes,locked 2006.285.21:02:42.59/valo/02,534.99,yes,locked 2006.285.21:02:42.59/valo/03,564.99,yes,locked 2006.285.21:02:42.59/valo/04,624.99,yes,locked 2006.285.21:02:42.59/valo/05,734.99,yes,locked 2006.285.21:02:42.59/valo/06,814.99,yes,locked 2006.285.21:02:42.59/valo/07,864.99,yes,locked 2006.285.21:02:42.59/valo/08,884.99,yes,locked 2006.285.21:02:43.68/vb/01,04,usb,yes,30,28 2006.285.21:02:43.68/vb/02,05,usb,yes,28,28 2006.285.21:02:43.68/vb/03,04,usb,yes,29,32 2006.285.21:02:43.68/vb/04,05,usb,yes,29,28 2006.285.21:02:43.68/vb/05,04,usb,yes,26,28 2006.285.21:02:43.68/vb/06,03,usb,yes,37,33 2006.285.21:02:43.68/vb/07,04,usb,yes,30,30 2006.285.21:02:43.68/vb/08,04,usb,yes,27,31 2006.285.21:02:43.91/vblo/01,629.99,yes,locked 2006.285.21:02:43.91/vblo/02,634.99,yes,locked 2006.285.21:02:43.91/vblo/03,649.99,yes,locked 2006.285.21:02:43.91/vblo/04,679.99,yes,locked 2006.285.21:02:43.91/vblo/05,709.99,yes,locked 2006.285.21:02:43.91/vblo/06,719.99,yes,locked 2006.285.21:02:43.91/vblo/07,734.99,yes,locked 2006.285.21:02:43.91/vblo/08,744.99,yes,locked 2006.285.21:02:44.06/vabw/8 2006.285.21:02:44.21/vbbw/8 2006.285.21:02:44.34/xfe/off,on,12.0 2006.285.21:02:44.70/ifatt/23,28,28,28 2006.285.21:02:45.07/fmout-gps/S +2.83E-07 2006.285.21:02:45.09:!2006.285.21:03:30 2006.285.21:03:30.01:data_valid=off 2006.285.21:03:30.01:"et 2006.285.21:03:30.01:!+3s 2006.285.21:03:33.02:"tape 2006.285.21:03:33.02:postob 2006.285.21:03:33.19/cable/+6.5113E-03 2006.285.21:03:33.19/wx/14.19,1015.5,100 2006.285.21:03:34.08/fmout-gps/S +2.84E-07 2006.285.21:03:34.08:scan_name=285-2104,jd0610,200 2006.285.21:03:34.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.285.21:03:35.14#flagr#flagr/antenna,new-source 2006.285.21:03:35.14:checkk5 2006.285.21:03:35.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:03:35.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:03:36.63/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:03:37.06/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:03:37.41/chk_obsdata//k5ts1/T2852102??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.21:03:37.79/chk_obsdata//k5ts2/T2852102??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.21:03:38.34/chk_obsdata//k5ts3/T2852102??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.21:03:38.75/chk_obsdata//k5ts4/T2852102??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.21:03:39.54/k5log//k5ts1_log_newline 2006.285.21:03:40.65/k5log//k5ts2_log_newline 2006.285.21:03:41.42/k5log//k5ts3_log_newline 2006.285.21:03:42.48/k5log//k5ts4_log_newline 2006.285.21:03:42.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:03:42.50:setupk4=1 2006.285.21:03:42.50$setupk4/echo=on 2006.285.21:03:42.50$setupk4/pcalon 2006.285.21:03:42.51$pcalon/"no phase cal control is implemented here 2006.285.21:03:42.51$setupk4/"tpicd=stop 2006.285.21:03:42.51$setupk4/"rec=synch_on 2006.285.21:03:42.51$setupk4/"rec_mode=128 2006.285.21:03:42.51$setupk4/!* 2006.285.21:03:42.51$setupk4/recpk4 2006.285.21:03:42.51$recpk4/recpatch= 2006.285.21:03:42.51$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:03:42.51$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:03:42.51$setupk4/vck44 2006.285.21:03:42.51$vck44/valo=1,524.99 2006.285.21:03:42.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.21:03:42.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.21:03:42.51#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:42.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:03:42.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:03:42.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:03:42.51#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:03:42.51#ibcon#first serial, iclass 30, count 0 2006.285.21:03:42.51#ibcon#enter sib2, iclass 30, count 0 2006.285.21:03:42.51#ibcon#flushed, iclass 30, count 0 2006.285.21:03:42.51#ibcon#about to write, iclass 30, count 0 2006.285.21:03:42.51#ibcon#wrote, iclass 30, count 0 2006.285.21:03:42.51#ibcon#about to read 3, iclass 30, count 0 2006.285.21:03:42.53#ibcon#read 3, iclass 30, count 0 2006.285.21:03:42.53#ibcon#about to read 4, iclass 30, count 0 2006.285.21:03:42.53#ibcon#read 4, iclass 30, count 0 2006.285.21:03:42.53#ibcon#about to read 5, iclass 30, count 0 2006.285.21:03:42.53#ibcon#read 5, iclass 30, count 0 2006.285.21:03:42.53#ibcon#about to read 6, iclass 30, count 0 2006.285.21:03:42.53#ibcon#read 6, iclass 30, count 0 2006.285.21:03:42.53#ibcon#end of sib2, iclass 30, count 0 2006.285.21:03:42.53#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:03:42.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:03:42.53#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:03:42.53#ibcon#*before write, iclass 30, count 0 2006.285.21:03:42.53#ibcon#enter sib2, iclass 30, count 0 2006.285.21:03:42.53#ibcon#flushed, iclass 30, count 0 2006.285.21:03:42.53#ibcon#about to write, iclass 30, count 0 2006.285.21:03:42.53#ibcon#wrote, iclass 30, count 0 2006.285.21:03:42.53#ibcon#about to read 3, iclass 30, count 0 2006.285.21:03:42.58#ibcon#read 3, iclass 30, count 0 2006.285.21:03:42.58#ibcon#about to read 4, iclass 30, count 0 2006.285.21:03:42.58#ibcon#read 4, iclass 30, count 0 2006.285.21:03:42.58#ibcon#about to read 5, iclass 30, count 0 2006.285.21:03:42.58#ibcon#read 5, iclass 30, count 0 2006.285.21:03:42.58#ibcon#about to read 6, iclass 30, count 0 2006.285.21:03:42.58#ibcon#read 6, iclass 30, count 0 2006.285.21:03:42.58#ibcon#end of sib2, iclass 30, count 0 2006.285.21:03:42.58#ibcon#*after write, iclass 30, count 0 2006.285.21:03:42.58#ibcon#*before return 0, iclass 30, count 0 2006.285.21:03:42.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:03:42.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:03:42.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:03:42.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:03:42.58$vck44/va=1,7 2006.285.21:03:42.58#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.21:03:42.58#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.21:03:42.58#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:42.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:03:42.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:03:42.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:03:42.58#ibcon#enter wrdev, iclass 32, count 2 2006.285.21:03:42.58#ibcon#first serial, iclass 32, count 2 2006.285.21:03:42.58#ibcon#enter sib2, iclass 32, count 2 2006.285.21:03:42.58#ibcon#flushed, iclass 32, count 2 2006.285.21:03:42.58#ibcon#about to write, iclass 32, count 2 2006.285.21:03:42.58#ibcon#wrote, iclass 32, count 2 2006.285.21:03:42.58#ibcon#about to read 3, iclass 32, count 2 2006.285.21:03:42.60#ibcon#read 3, iclass 32, count 2 2006.285.21:03:42.60#ibcon#about to read 4, iclass 32, count 2 2006.285.21:03:42.60#ibcon#read 4, iclass 32, count 2 2006.285.21:03:42.60#ibcon#about to read 5, iclass 32, count 2 2006.285.21:03:42.60#ibcon#read 5, iclass 32, count 2 2006.285.21:03:42.60#ibcon#about to read 6, iclass 32, count 2 2006.285.21:03:42.60#ibcon#read 6, iclass 32, count 2 2006.285.21:03:42.60#ibcon#end of sib2, iclass 32, count 2 2006.285.21:03:42.60#ibcon#*mode == 0, iclass 32, count 2 2006.285.21:03:42.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.21:03:42.60#ibcon#[25=AT01-07\r\n] 2006.285.21:03:42.60#ibcon#*before write, iclass 32, count 2 2006.285.21:03:42.60#ibcon#enter sib2, iclass 32, count 2 2006.285.21:03:42.60#ibcon#flushed, iclass 32, count 2 2006.285.21:03:42.60#ibcon#about to write, iclass 32, count 2 2006.285.21:03:42.60#ibcon#wrote, iclass 32, count 2 2006.285.21:03:42.60#ibcon#about to read 3, iclass 32, count 2 2006.285.21:03:42.63#ibcon#read 3, iclass 32, count 2 2006.285.21:03:42.63#ibcon#about to read 4, iclass 32, count 2 2006.285.21:03:42.63#ibcon#read 4, iclass 32, count 2 2006.285.21:03:42.63#ibcon#about to read 5, iclass 32, count 2 2006.285.21:03:42.63#ibcon#read 5, iclass 32, count 2 2006.285.21:03:42.63#ibcon#about to read 6, iclass 32, count 2 2006.285.21:03:42.63#ibcon#read 6, iclass 32, count 2 2006.285.21:03:42.63#ibcon#end of sib2, iclass 32, count 2 2006.285.21:03:42.63#ibcon#*after write, iclass 32, count 2 2006.285.21:03:42.63#ibcon#*before return 0, iclass 32, count 2 2006.285.21:03:42.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:03:42.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:03:42.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.21:03:42.63#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:42.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:03:42.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:03:42.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:03:42.75#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:03:42.75#ibcon#first serial, iclass 32, count 0 2006.285.21:03:42.75#ibcon#enter sib2, iclass 32, count 0 2006.285.21:03:42.75#ibcon#flushed, iclass 32, count 0 2006.285.21:03:42.75#ibcon#about to write, iclass 32, count 0 2006.285.21:03:42.75#ibcon#wrote, iclass 32, count 0 2006.285.21:03:42.75#ibcon#about to read 3, iclass 32, count 0 2006.285.21:03:42.77#ibcon#read 3, iclass 32, count 0 2006.285.21:03:42.77#ibcon#about to read 4, iclass 32, count 0 2006.285.21:03:42.77#ibcon#read 4, iclass 32, count 0 2006.285.21:03:42.77#ibcon#about to read 5, iclass 32, count 0 2006.285.21:03:42.77#ibcon#read 5, iclass 32, count 0 2006.285.21:03:42.77#ibcon#about to read 6, iclass 32, count 0 2006.285.21:03:42.77#ibcon#read 6, iclass 32, count 0 2006.285.21:03:42.77#ibcon#end of sib2, iclass 32, count 0 2006.285.21:03:42.77#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:03:42.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:03:42.77#ibcon#[25=USB\r\n] 2006.285.21:03:42.77#ibcon#*before write, iclass 32, count 0 2006.285.21:03:42.77#ibcon#enter sib2, iclass 32, count 0 2006.285.21:03:42.77#ibcon#flushed, iclass 32, count 0 2006.285.21:03:42.77#ibcon#about to write, iclass 32, count 0 2006.285.21:03:42.77#ibcon#wrote, iclass 32, count 0 2006.285.21:03:42.77#ibcon#about to read 3, iclass 32, count 0 2006.285.21:03:42.80#ibcon#read 3, iclass 32, count 0 2006.285.21:03:42.80#ibcon#about to read 4, iclass 32, count 0 2006.285.21:03:42.80#ibcon#read 4, iclass 32, count 0 2006.285.21:03:42.80#ibcon#about to read 5, iclass 32, count 0 2006.285.21:03:42.80#ibcon#read 5, iclass 32, count 0 2006.285.21:03:42.80#ibcon#about to read 6, iclass 32, count 0 2006.285.21:03:42.80#ibcon#read 6, iclass 32, count 0 2006.285.21:03:42.80#ibcon#end of sib2, iclass 32, count 0 2006.285.21:03:42.80#ibcon#*after write, iclass 32, count 0 2006.285.21:03:42.80#ibcon#*before return 0, iclass 32, count 0 2006.285.21:03:42.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:03:42.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:03:42.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:03:42.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:03:42.80$vck44/valo=2,534.99 2006.285.21:03:42.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.21:03:42.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.21:03:42.80#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:42.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:03:42.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:03:42.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:03:42.80#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:03:42.80#ibcon#first serial, iclass 34, count 0 2006.285.21:03:42.80#ibcon#enter sib2, iclass 34, count 0 2006.285.21:03:42.80#ibcon#flushed, iclass 34, count 0 2006.285.21:03:42.80#ibcon#about to write, iclass 34, count 0 2006.285.21:03:42.80#ibcon#wrote, iclass 34, count 0 2006.285.21:03:42.80#ibcon#about to read 3, iclass 34, count 0 2006.285.21:03:42.82#ibcon#read 3, iclass 34, count 0 2006.285.21:03:42.82#ibcon#about to read 4, iclass 34, count 0 2006.285.21:03:42.82#ibcon#read 4, iclass 34, count 0 2006.285.21:03:42.82#ibcon#about to read 5, iclass 34, count 0 2006.285.21:03:42.82#ibcon#read 5, iclass 34, count 0 2006.285.21:03:42.82#ibcon#about to read 6, iclass 34, count 0 2006.285.21:03:42.82#ibcon#read 6, iclass 34, count 0 2006.285.21:03:42.82#ibcon#end of sib2, iclass 34, count 0 2006.285.21:03:42.82#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:03:42.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:03:42.82#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:03:42.82#ibcon#*before write, iclass 34, count 0 2006.285.21:03:42.82#ibcon#enter sib2, iclass 34, count 0 2006.285.21:03:42.82#ibcon#flushed, iclass 34, count 0 2006.285.21:03:42.82#ibcon#about to write, iclass 34, count 0 2006.285.21:03:42.82#ibcon#wrote, iclass 34, count 0 2006.285.21:03:42.82#ibcon#about to read 3, iclass 34, count 0 2006.285.21:03:42.86#ibcon#read 3, iclass 34, count 0 2006.285.21:03:42.86#ibcon#about to read 4, iclass 34, count 0 2006.285.21:03:42.86#ibcon#read 4, iclass 34, count 0 2006.285.21:03:42.86#ibcon#about to read 5, iclass 34, count 0 2006.285.21:03:42.86#ibcon#read 5, iclass 34, count 0 2006.285.21:03:42.86#ibcon#about to read 6, iclass 34, count 0 2006.285.21:03:42.86#ibcon#read 6, iclass 34, count 0 2006.285.21:03:42.86#ibcon#end of sib2, iclass 34, count 0 2006.285.21:03:42.86#ibcon#*after write, iclass 34, count 0 2006.285.21:03:42.86#ibcon#*before return 0, iclass 34, count 0 2006.285.21:03:42.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:03:42.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:03:42.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:03:42.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:03:42.86$vck44/va=2,6 2006.285.21:03:42.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.21:03:42.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.21:03:42.86#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:42.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:03:42.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:03:42.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:03:42.92#ibcon#enter wrdev, iclass 36, count 2 2006.285.21:03:42.92#ibcon#first serial, iclass 36, count 2 2006.285.21:03:42.92#ibcon#enter sib2, iclass 36, count 2 2006.285.21:03:42.92#ibcon#flushed, iclass 36, count 2 2006.285.21:03:42.92#ibcon#about to write, iclass 36, count 2 2006.285.21:03:42.92#ibcon#wrote, iclass 36, count 2 2006.285.21:03:42.92#ibcon#about to read 3, iclass 36, count 2 2006.285.21:03:42.94#ibcon#read 3, iclass 36, count 2 2006.285.21:03:42.94#ibcon#about to read 4, iclass 36, count 2 2006.285.21:03:42.94#ibcon#read 4, iclass 36, count 2 2006.285.21:03:42.94#ibcon#about to read 5, iclass 36, count 2 2006.285.21:03:42.94#ibcon#read 5, iclass 36, count 2 2006.285.21:03:42.94#ibcon#about to read 6, iclass 36, count 2 2006.285.21:03:42.94#ibcon#read 6, iclass 36, count 2 2006.285.21:03:42.94#ibcon#end of sib2, iclass 36, count 2 2006.285.21:03:42.94#ibcon#*mode == 0, iclass 36, count 2 2006.285.21:03:42.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.21:03:42.94#ibcon#[25=AT02-06\r\n] 2006.285.21:03:42.94#ibcon#*before write, iclass 36, count 2 2006.285.21:03:42.94#ibcon#enter sib2, iclass 36, count 2 2006.285.21:03:42.94#ibcon#flushed, iclass 36, count 2 2006.285.21:03:42.94#ibcon#about to write, iclass 36, count 2 2006.285.21:03:42.94#ibcon#wrote, iclass 36, count 2 2006.285.21:03:42.94#ibcon#about to read 3, iclass 36, count 2 2006.285.21:03:42.97#ibcon#read 3, iclass 36, count 2 2006.285.21:03:42.97#ibcon#about to read 4, iclass 36, count 2 2006.285.21:03:42.97#ibcon#read 4, iclass 36, count 2 2006.285.21:03:42.97#ibcon#about to read 5, iclass 36, count 2 2006.285.21:03:42.97#ibcon#read 5, iclass 36, count 2 2006.285.21:03:42.97#ibcon#about to read 6, iclass 36, count 2 2006.285.21:03:42.97#ibcon#read 6, iclass 36, count 2 2006.285.21:03:42.97#ibcon#end of sib2, iclass 36, count 2 2006.285.21:03:42.97#ibcon#*after write, iclass 36, count 2 2006.285.21:03:42.97#ibcon#*before return 0, iclass 36, count 2 2006.285.21:03:42.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:03:42.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:03:42.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.21:03:42.97#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:42.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:03:43.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:03:43.88#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:03:43.88#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:03:43.88#ibcon#first serial, iclass 36, count 0 2006.285.21:03:43.88#ibcon#enter sib2, iclass 36, count 0 2006.285.21:03:43.88#ibcon#flushed, iclass 36, count 0 2006.285.21:03:43.88#ibcon#about to write, iclass 36, count 0 2006.285.21:03:43.88#ibcon#wrote, iclass 36, count 0 2006.285.21:03:43.88#ibcon#about to read 3, iclass 36, count 0 2006.285.21:03:43.89#ibcon#read 3, iclass 36, count 0 2006.285.21:03:43.89#ibcon#about to read 4, iclass 36, count 0 2006.285.21:03:43.89#ibcon#read 4, iclass 36, count 0 2006.285.21:03:43.89#ibcon#about to read 5, iclass 36, count 0 2006.285.21:03:43.89#ibcon#read 5, iclass 36, count 0 2006.285.21:03:43.89#ibcon#about to read 6, iclass 36, count 0 2006.285.21:03:43.89#ibcon#read 6, iclass 36, count 0 2006.285.21:03:43.89#ibcon#end of sib2, iclass 36, count 0 2006.285.21:03:43.89#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:03:43.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:03:43.89#ibcon#[25=USB\r\n] 2006.285.21:03:43.89#ibcon#*before write, iclass 36, count 0 2006.285.21:03:43.89#ibcon#enter sib2, iclass 36, count 0 2006.285.21:03:43.89#ibcon#flushed, iclass 36, count 0 2006.285.21:03:43.89#ibcon#about to write, iclass 36, count 0 2006.285.21:03:43.89#ibcon#wrote, iclass 36, count 0 2006.285.21:03:43.89#ibcon#about to read 3, iclass 36, count 0 2006.285.21:03:43.92#ibcon#read 3, iclass 36, count 0 2006.285.21:03:43.92#ibcon#about to read 4, iclass 36, count 0 2006.285.21:03:43.92#ibcon#read 4, iclass 36, count 0 2006.285.21:03:43.92#ibcon#about to read 5, iclass 36, count 0 2006.285.21:03:43.92#ibcon#read 5, iclass 36, count 0 2006.285.21:03:43.92#ibcon#about to read 6, iclass 36, count 0 2006.285.21:03:43.92#ibcon#read 6, iclass 36, count 0 2006.285.21:03:43.92#ibcon#end of sib2, iclass 36, count 0 2006.285.21:03:43.92#ibcon#*after write, iclass 36, count 0 2006.285.21:03:43.92#ibcon#*before return 0, iclass 36, count 0 2006.285.21:03:43.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:03:43.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:03:43.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:03:43.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:03:43.92$vck44/valo=3,564.99 2006.285.21:03:43.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.21:03:43.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.21:03:43.92#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:43.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:03:43.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:03:43.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:03:43.92#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:03:43.92#ibcon#first serial, iclass 38, count 0 2006.285.21:03:43.92#ibcon#enter sib2, iclass 38, count 0 2006.285.21:03:43.92#ibcon#flushed, iclass 38, count 0 2006.285.21:03:43.92#ibcon#about to write, iclass 38, count 0 2006.285.21:03:43.92#ibcon#wrote, iclass 38, count 0 2006.285.21:03:43.92#ibcon#about to read 3, iclass 38, count 0 2006.285.21:03:43.94#ibcon#read 3, iclass 38, count 0 2006.285.21:03:43.94#ibcon#about to read 4, iclass 38, count 0 2006.285.21:03:43.94#ibcon#read 4, iclass 38, count 0 2006.285.21:03:43.94#ibcon#about to read 5, iclass 38, count 0 2006.285.21:03:43.94#ibcon#read 5, iclass 38, count 0 2006.285.21:03:43.94#ibcon#about to read 6, iclass 38, count 0 2006.285.21:03:43.94#ibcon#read 6, iclass 38, count 0 2006.285.21:03:43.94#ibcon#end of sib2, iclass 38, count 0 2006.285.21:03:43.94#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:03:43.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:03:43.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:03:43.94#ibcon#*before write, iclass 38, count 0 2006.285.21:03:43.94#ibcon#enter sib2, iclass 38, count 0 2006.285.21:03:43.94#ibcon#flushed, iclass 38, count 0 2006.285.21:03:43.94#ibcon#about to write, iclass 38, count 0 2006.285.21:03:43.94#ibcon#wrote, iclass 38, count 0 2006.285.21:03:43.94#ibcon#about to read 3, iclass 38, count 0 2006.285.21:03:43.98#ibcon#read 3, iclass 38, count 0 2006.285.21:03:43.98#ibcon#about to read 4, iclass 38, count 0 2006.285.21:03:43.98#ibcon#read 4, iclass 38, count 0 2006.285.21:03:43.98#ibcon#about to read 5, iclass 38, count 0 2006.285.21:03:43.98#ibcon#read 5, iclass 38, count 0 2006.285.21:03:43.98#ibcon#about to read 6, iclass 38, count 0 2006.285.21:03:43.98#ibcon#read 6, iclass 38, count 0 2006.285.21:03:43.98#ibcon#end of sib2, iclass 38, count 0 2006.285.21:03:43.98#ibcon#*after write, iclass 38, count 0 2006.285.21:03:43.98#ibcon#*before return 0, iclass 38, count 0 2006.285.21:03:43.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:03:43.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:03:43.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:03:43.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:03:43.98$vck44/va=3,7 2006.285.21:03:43.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.21:03:43.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.21:03:43.98#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:43.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:03:44.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:03:44.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:03:44.04#ibcon#enter wrdev, iclass 40, count 2 2006.285.21:03:44.04#ibcon#first serial, iclass 40, count 2 2006.285.21:03:44.04#ibcon#enter sib2, iclass 40, count 2 2006.285.21:03:44.04#ibcon#flushed, iclass 40, count 2 2006.285.21:03:44.04#ibcon#about to write, iclass 40, count 2 2006.285.21:03:44.04#ibcon#wrote, iclass 40, count 2 2006.285.21:03:44.04#ibcon#about to read 3, iclass 40, count 2 2006.285.21:03:44.06#ibcon#read 3, iclass 40, count 2 2006.285.21:03:44.06#ibcon#about to read 4, iclass 40, count 2 2006.285.21:03:44.06#ibcon#read 4, iclass 40, count 2 2006.285.21:03:44.06#ibcon#about to read 5, iclass 40, count 2 2006.285.21:03:44.06#ibcon#read 5, iclass 40, count 2 2006.285.21:03:44.06#ibcon#about to read 6, iclass 40, count 2 2006.285.21:03:44.06#ibcon#read 6, iclass 40, count 2 2006.285.21:03:44.06#ibcon#end of sib2, iclass 40, count 2 2006.285.21:03:44.06#ibcon#*mode == 0, iclass 40, count 2 2006.285.21:03:44.06#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.21:03:44.06#ibcon#[25=AT03-07\r\n] 2006.285.21:03:44.06#ibcon#*before write, iclass 40, count 2 2006.285.21:03:44.06#ibcon#enter sib2, iclass 40, count 2 2006.285.21:03:44.06#ibcon#flushed, iclass 40, count 2 2006.285.21:03:44.06#ibcon#about to write, iclass 40, count 2 2006.285.21:03:44.06#ibcon#wrote, iclass 40, count 2 2006.285.21:03:44.06#ibcon#about to read 3, iclass 40, count 2 2006.285.21:03:44.09#ibcon#read 3, iclass 40, count 2 2006.285.21:03:44.09#ibcon#about to read 4, iclass 40, count 2 2006.285.21:03:44.09#ibcon#read 4, iclass 40, count 2 2006.285.21:03:44.09#ibcon#about to read 5, iclass 40, count 2 2006.285.21:03:44.09#ibcon#read 5, iclass 40, count 2 2006.285.21:03:44.09#ibcon#about to read 6, iclass 40, count 2 2006.285.21:03:44.09#ibcon#read 6, iclass 40, count 2 2006.285.21:03:44.09#ibcon#end of sib2, iclass 40, count 2 2006.285.21:03:44.09#ibcon#*after write, iclass 40, count 2 2006.285.21:03:44.09#ibcon#*before return 0, iclass 40, count 2 2006.285.21:03:44.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:03:44.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:03:44.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.21:03:44.09#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:44.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:03:44.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:03:44.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:03:44.21#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:03:44.21#ibcon#first serial, iclass 40, count 0 2006.285.21:03:44.21#ibcon#enter sib2, iclass 40, count 0 2006.285.21:03:44.21#ibcon#flushed, iclass 40, count 0 2006.285.21:03:44.21#ibcon#about to write, iclass 40, count 0 2006.285.21:03:44.21#ibcon#wrote, iclass 40, count 0 2006.285.21:03:44.21#ibcon#about to read 3, iclass 40, count 0 2006.285.21:03:44.23#ibcon#read 3, iclass 40, count 0 2006.285.21:03:44.23#ibcon#about to read 4, iclass 40, count 0 2006.285.21:03:44.23#ibcon#read 4, iclass 40, count 0 2006.285.21:03:44.23#ibcon#about to read 5, iclass 40, count 0 2006.285.21:03:44.23#ibcon#read 5, iclass 40, count 0 2006.285.21:03:44.23#ibcon#about to read 6, iclass 40, count 0 2006.285.21:03:44.23#ibcon#read 6, iclass 40, count 0 2006.285.21:03:44.23#ibcon#end of sib2, iclass 40, count 0 2006.285.21:03:44.23#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:03:44.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:03:44.23#ibcon#[25=USB\r\n] 2006.285.21:03:44.23#ibcon#*before write, iclass 40, count 0 2006.285.21:03:44.23#ibcon#enter sib2, iclass 40, count 0 2006.285.21:03:44.23#ibcon#flushed, iclass 40, count 0 2006.285.21:03:44.23#ibcon#about to write, iclass 40, count 0 2006.285.21:03:44.23#ibcon#wrote, iclass 40, count 0 2006.285.21:03:44.23#ibcon#about to read 3, iclass 40, count 0 2006.285.21:03:44.26#ibcon#read 3, iclass 40, count 0 2006.285.21:03:44.26#ibcon#about to read 4, iclass 40, count 0 2006.285.21:03:44.26#ibcon#read 4, iclass 40, count 0 2006.285.21:03:44.26#ibcon#about to read 5, iclass 40, count 0 2006.285.21:03:44.26#ibcon#read 5, iclass 40, count 0 2006.285.21:03:44.26#ibcon#about to read 6, iclass 40, count 0 2006.285.21:03:44.26#ibcon#read 6, iclass 40, count 0 2006.285.21:03:44.26#ibcon#end of sib2, iclass 40, count 0 2006.285.21:03:44.26#ibcon#*after write, iclass 40, count 0 2006.285.21:03:44.26#ibcon#*before return 0, iclass 40, count 0 2006.285.21:03:44.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:03:44.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:03:44.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:03:44.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:03:44.26$vck44/valo=4,624.99 2006.285.21:03:44.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.21:03:44.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.21:03:44.26#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:44.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:03:44.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:03:44.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:03:44.26#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:03:44.26#ibcon#first serial, iclass 4, count 0 2006.285.21:03:44.26#ibcon#enter sib2, iclass 4, count 0 2006.285.21:03:44.26#ibcon#flushed, iclass 4, count 0 2006.285.21:03:44.26#ibcon#about to write, iclass 4, count 0 2006.285.21:03:44.26#ibcon#wrote, iclass 4, count 0 2006.285.21:03:44.26#ibcon#about to read 3, iclass 4, count 0 2006.285.21:03:44.28#ibcon#read 3, iclass 4, count 0 2006.285.21:03:44.88#ibcon#about to read 4, iclass 4, count 0 2006.285.21:03:44.88#ibcon#read 4, iclass 4, count 0 2006.285.21:03:44.88#ibcon#about to read 5, iclass 4, count 0 2006.285.21:03:44.88#ibcon#read 5, iclass 4, count 0 2006.285.21:03:44.88#ibcon#about to read 6, iclass 4, count 0 2006.285.21:03:44.88#ibcon#read 6, iclass 4, count 0 2006.285.21:03:44.88#ibcon#end of sib2, iclass 4, count 0 2006.285.21:03:44.88#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:03:44.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:03:44.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:03:44.88#ibcon#*before write, iclass 4, count 0 2006.285.21:03:44.88#ibcon#enter sib2, iclass 4, count 0 2006.285.21:03:44.88#ibcon#flushed, iclass 4, count 0 2006.285.21:03:44.88#ibcon#about to write, iclass 4, count 0 2006.285.21:03:44.88#ibcon#wrote, iclass 4, count 0 2006.285.21:03:44.88#ibcon#about to read 3, iclass 4, count 0 2006.285.21:03:44.93#ibcon#read 3, iclass 4, count 0 2006.285.21:03:44.93#ibcon#about to read 4, iclass 4, count 0 2006.285.21:03:44.93#ibcon#read 4, iclass 4, count 0 2006.285.21:03:44.93#ibcon#about to read 5, iclass 4, count 0 2006.285.21:03:44.93#ibcon#read 5, iclass 4, count 0 2006.285.21:03:44.93#ibcon#about to read 6, iclass 4, count 0 2006.285.21:03:44.93#ibcon#read 6, iclass 4, count 0 2006.285.21:03:44.93#ibcon#end of sib2, iclass 4, count 0 2006.285.21:03:44.93#ibcon#*after write, iclass 4, count 0 2006.285.21:03:44.93#ibcon#*before return 0, iclass 4, count 0 2006.285.21:03:44.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:03:44.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:03:44.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:03:44.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:03:44.93$vck44/va=4,6 2006.285.21:03:44.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.21:03:44.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.21:03:44.93#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:44.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:03:44.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:03:44.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:03:44.93#ibcon#enter wrdev, iclass 6, count 2 2006.285.21:03:44.93#ibcon#first serial, iclass 6, count 2 2006.285.21:03:44.93#ibcon#enter sib2, iclass 6, count 2 2006.285.21:03:44.93#ibcon#flushed, iclass 6, count 2 2006.285.21:03:44.93#ibcon#about to write, iclass 6, count 2 2006.285.21:03:44.93#ibcon#wrote, iclass 6, count 2 2006.285.21:03:44.93#ibcon#about to read 3, iclass 6, count 2 2006.285.21:03:44.95#ibcon#read 3, iclass 6, count 2 2006.285.21:03:44.95#ibcon#about to read 4, iclass 6, count 2 2006.285.21:03:44.95#ibcon#read 4, iclass 6, count 2 2006.285.21:03:44.95#ibcon#about to read 5, iclass 6, count 2 2006.285.21:03:44.95#ibcon#read 5, iclass 6, count 2 2006.285.21:03:44.95#ibcon#about to read 6, iclass 6, count 2 2006.285.21:03:44.95#ibcon#read 6, iclass 6, count 2 2006.285.21:03:44.95#ibcon#end of sib2, iclass 6, count 2 2006.285.21:03:44.95#ibcon#*mode == 0, iclass 6, count 2 2006.285.21:03:44.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.21:03:44.95#ibcon#[25=AT04-06\r\n] 2006.285.21:03:44.95#ibcon#*before write, iclass 6, count 2 2006.285.21:03:44.95#ibcon#enter sib2, iclass 6, count 2 2006.285.21:03:44.95#ibcon#flushed, iclass 6, count 2 2006.285.21:03:44.95#ibcon#about to write, iclass 6, count 2 2006.285.21:03:44.95#ibcon#wrote, iclass 6, count 2 2006.285.21:03:44.95#ibcon#about to read 3, iclass 6, count 2 2006.285.21:03:44.98#ibcon#read 3, iclass 6, count 2 2006.285.21:03:44.98#ibcon#about to read 4, iclass 6, count 2 2006.285.21:03:44.98#ibcon#read 4, iclass 6, count 2 2006.285.21:03:44.98#ibcon#about to read 5, iclass 6, count 2 2006.285.21:03:44.98#ibcon#read 5, iclass 6, count 2 2006.285.21:03:44.98#ibcon#about to read 6, iclass 6, count 2 2006.285.21:03:44.98#ibcon#read 6, iclass 6, count 2 2006.285.21:03:44.98#ibcon#end of sib2, iclass 6, count 2 2006.285.21:03:44.98#ibcon#*after write, iclass 6, count 2 2006.285.21:03:44.98#ibcon#*before return 0, iclass 6, count 2 2006.285.21:03:44.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:03:44.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:03:44.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.21:03:44.98#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:44.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:03:45.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:03:45.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:03:45.10#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:03:45.10#ibcon#first serial, iclass 6, count 0 2006.285.21:03:45.10#ibcon#enter sib2, iclass 6, count 0 2006.285.21:03:45.10#ibcon#flushed, iclass 6, count 0 2006.285.21:03:45.10#ibcon#about to write, iclass 6, count 0 2006.285.21:03:45.10#ibcon#wrote, iclass 6, count 0 2006.285.21:03:45.10#ibcon#about to read 3, iclass 6, count 0 2006.285.21:03:45.12#ibcon#read 3, iclass 6, count 0 2006.285.21:03:45.12#ibcon#about to read 4, iclass 6, count 0 2006.285.21:03:45.12#ibcon#read 4, iclass 6, count 0 2006.285.21:03:45.12#ibcon#about to read 5, iclass 6, count 0 2006.285.21:03:45.12#ibcon#read 5, iclass 6, count 0 2006.285.21:03:45.12#ibcon#about to read 6, iclass 6, count 0 2006.285.21:03:45.12#ibcon#read 6, iclass 6, count 0 2006.285.21:03:45.12#ibcon#end of sib2, iclass 6, count 0 2006.285.21:03:45.12#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:03:45.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:03:45.12#ibcon#[25=USB\r\n] 2006.285.21:03:45.12#ibcon#*before write, iclass 6, count 0 2006.285.21:03:45.12#ibcon#enter sib2, iclass 6, count 0 2006.285.21:03:45.12#ibcon#flushed, iclass 6, count 0 2006.285.21:03:45.12#ibcon#about to write, iclass 6, count 0 2006.285.21:03:45.12#ibcon#wrote, iclass 6, count 0 2006.285.21:03:45.12#ibcon#about to read 3, iclass 6, count 0 2006.285.21:03:45.15#ibcon#read 3, iclass 6, count 0 2006.285.21:03:45.15#ibcon#about to read 4, iclass 6, count 0 2006.285.21:03:45.15#ibcon#read 4, iclass 6, count 0 2006.285.21:03:45.15#ibcon#about to read 5, iclass 6, count 0 2006.285.21:03:45.15#ibcon#read 5, iclass 6, count 0 2006.285.21:03:45.15#ibcon#about to read 6, iclass 6, count 0 2006.285.21:03:45.15#ibcon#read 6, iclass 6, count 0 2006.285.21:03:45.15#ibcon#end of sib2, iclass 6, count 0 2006.285.21:03:45.15#ibcon#*after write, iclass 6, count 0 2006.285.21:03:45.15#ibcon#*before return 0, iclass 6, count 0 2006.285.21:03:45.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:03:45.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:03:45.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:03:45.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:03:45.15$vck44/valo=5,734.99 2006.285.21:03:45.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.21:03:45.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.21:03:45.15#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:45.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:03:45.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:03:45.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:03:45.15#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:03:45.15#ibcon#first serial, iclass 10, count 0 2006.285.21:03:45.15#ibcon#enter sib2, iclass 10, count 0 2006.285.21:03:45.15#ibcon#flushed, iclass 10, count 0 2006.285.21:03:45.15#ibcon#about to write, iclass 10, count 0 2006.285.21:03:45.15#ibcon#wrote, iclass 10, count 0 2006.285.21:03:45.15#ibcon#about to read 3, iclass 10, count 0 2006.285.21:03:45.17#ibcon#read 3, iclass 10, count 0 2006.285.21:03:45.25#ibcon#about to read 4, iclass 10, count 0 2006.285.21:03:45.25#ibcon#read 4, iclass 10, count 0 2006.285.21:03:45.25#ibcon#about to read 5, iclass 10, count 0 2006.285.21:03:45.25#ibcon#read 5, iclass 10, count 0 2006.285.21:03:45.25#ibcon#about to read 6, iclass 10, count 0 2006.285.21:03:45.25#ibcon#read 6, iclass 10, count 0 2006.285.21:03:45.25#ibcon#end of sib2, iclass 10, count 0 2006.285.21:03:45.25#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:03:45.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:03:45.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:03:45.25#ibcon#*before write, iclass 10, count 0 2006.285.21:03:45.25#ibcon#enter sib2, iclass 10, count 0 2006.285.21:03:45.25#ibcon#flushed, iclass 10, count 0 2006.285.21:03:45.25#ibcon#about to write, iclass 10, count 0 2006.285.21:03:45.25#ibcon#wrote, iclass 10, count 0 2006.285.21:03:45.25#ibcon#about to read 3, iclass 10, count 0 2006.285.21:03:45.29#ibcon#read 3, iclass 10, count 0 2006.285.21:03:45.29#ibcon#about to read 4, iclass 10, count 0 2006.285.21:03:45.29#ibcon#read 4, iclass 10, count 0 2006.285.21:03:45.29#ibcon#about to read 5, iclass 10, count 0 2006.285.21:03:45.29#ibcon#read 5, iclass 10, count 0 2006.285.21:03:45.29#ibcon#about to read 6, iclass 10, count 0 2006.285.21:03:45.29#ibcon#read 6, iclass 10, count 0 2006.285.21:03:45.29#ibcon#end of sib2, iclass 10, count 0 2006.285.21:03:45.29#ibcon#*after write, iclass 10, count 0 2006.285.21:03:45.29#ibcon#*before return 0, iclass 10, count 0 2006.285.21:03:45.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:03:45.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:03:45.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:03:45.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:03:45.29$vck44/va=5,3 2006.285.21:03:45.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.21:03:45.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.21:03:45.29#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:45.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:03:45.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:03:45.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:03:45.29#ibcon#enter wrdev, iclass 12, count 2 2006.285.21:03:45.29#ibcon#first serial, iclass 12, count 2 2006.285.21:03:45.29#ibcon#enter sib2, iclass 12, count 2 2006.285.21:03:45.29#ibcon#flushed, iclass 12, count 2 2006.285.21:03:45.29#ibcon#about to write, iclass 12, count 2 2006.285.21:03:45.29#ibcon#wrote, iclass 12, count 2 2006.285.21:03:45.29#ibcon#about to read 3, iclass 12, count 2 2006.285.21:03:45.31#ibcon#read 3, iclass 12, count 2 2006.285.21:03:45.31#ibcon#about to read 4, iclass 12, count 2 2006.285.21:03:45.31#ibcon#read 4, iclass 12, count 2 2006.285.21:03:45.31#ibcon#about to read 5, iclass 12, count 2 2006.285.21:03:45.31#ibcon#read 5, iclass 12, count 2 2006.285.21:03:45.31#ibcon#about to read 6, iclass 12, count 2 2006.285.21:03:45.31#ibcon#read 6, iclass 12, count 2 2006.285.21:03:45.31#ibcon#end of sib2, iclass 12, count 2 2006.285.21:03:45.31#ibcon#*mode == 0, iclass 12, count 2 2006.285.21:03:45.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.21:03:45.31#ibcon#[25=AT05-03\r\n] 2006.285.21:03:45.31#ibcon#*before write, iclass 12, count 2 2006.285.21:03:45.31#ibcon#enter sib2, iclass 12, count 2 2006.285.21:03:45.31#ibcon#flushed, iclass 12, count 2 2006.285.21:03:45.31#ibcon#about to write, iclass 12, count 2 2006.285.21:03:45.31#ibcon#wrote, iclass 12, count 2 2006.285.21:03:45.31#ibcon#about to read 3, iclass 12, count 2 2006.285.21:03:45.34#ibcon#read 3, iclass 12, count 2 2006.285.21:03:45.34#ibcon#about to read 4, iclass 12, count 2 2006.285.21:03:45.34#ibcon#read 4, iclass 12, count 2 2006.285.21:03:45.34#ibcon#about to read 5, iclass 12, count 2 2006.285.21:03:45.34#ibcon#read 5, iclass 12, count 2 2006.285.21:03:45.34#ibcon#about to read 6, iclass 12, count 2 2006.285.21:03:45.34#ibcon#read 6, iclass 12, count 2 2006.285.21:03:45.34#ibcon#end of sib2, iclass 12, count 2 2006.285.21:03:45.34#ibcon#*after write, iclass 12, count 2 2006.285.21:03:45.34#ibcon#*before return 0, iclass 12, count 2 2006.285.21:03:45.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:03:45.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:03:45.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.21:03:45.34#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:45.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:03:45.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:03:45.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:03:45.46#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:03:45.46#ibcon#first serial, iclass 12, count 0 2006.285.21:03:45.46#ibcon#enter sib2, iclass 12, count 0 2006.285.21:03:45.46#ibcon#flushed, iclass 12, count 0 2006.285.21:03:45.46#ibcon#about to write, iclass 12, count 0 2006.285.21:03:45.46#ibcon#wrote, iclass 12, count 0 2006.285.21:03:45.46#ibcon#about to read 3, iclass 12, count 0 2006.285.21:03:45.48#ibcon#read 3, iclass 12, count 0 2006.285.21:03:45.48#ibcon#about to read 4, iclass 12, count 0 2006.285.21:03:45.48#ibcon#read 4, iclass 12, count 0 2006.285.21:03:45.48#ibcon#about to read 5, iclass 12, count 0 2006.285.21:03:45.48#ibcon#read 5, iclass 12, count 0 2006.285.21:03:45.48#ibcon#about to read 6, iclass 12, count 0 2006.285.21:03:45.48#ibcon#read 6, iclass 12, count 0 2006.285.21:03:45.48#ibcon#end of sib2, iclass 12, count 0 2006.285.21:03:45.48#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:03:45.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:03:45.48#ibcon#[25=USB\r\n] 2006.285.21:03:45.48#ibcon#*before write, iclass 12, count 0 2006.285.21:03:45.48#ibcon#enter sib2, iclass 12, count 0 2006.285.21:03:45.48#ibcon#flushed, iclass 12, count 0 2006.285.21:03:45.48#ibcon#about to write, iclass 12, count 0 2006.285.21:03:45.48#ibcon#wrote, iclass 12, count 0 2006.285.21:03:45.48#ibcon#about to read 3, iclass 12, count 0 2006.285.21:03:45.51#ibcon#read 3, iclass 12, count 0 2006.285.21:03:45.51#ibcon#about to read 4, iclass 12, count 0 2006.285.21:03:45.51#ibcon#read 4, iclass 12, count 0 2006.285.21:03:45.51#ibcon#about to read 5, iclass 12, count 0 2006.285.21:03:45.51#ibcon#read 5, iclass 12, count 0 2006.285.21:03:45.51#ibcon#about to read 6, iclass 12, count 0 2006.285.21:03:45.51#ibcon#read 6, iclass 12, count 0 2006.285.21:03:45.51#ibcon#end of sib2, iclass 12, count 0 2006.285.21:03:45.51#ibcon#*after write, iclass 12, count 0 2006.285.21:03:45.51#ibcon#*before return 0, iclass 12, count 0 2006.285.21:03:45.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:03:45.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:03:45.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:03:45.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:03:45.51$vck44/valo=6,814.99 2006.285.21:03:45.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.21:03:45.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.21:03:45.51#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:45.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:03:45.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:03:45.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:03:45.51#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:03:45.51#ibcon#first serial, iclass 14, count 0 2006.285.21:03:45.51#ibcon#enter sib2, iclass 14, count 0 2006.285.21:03:45.51#ibcon#flushed, iclass 14, count 0 2006.285.21:03:45.51#ibcon#about to write, iclass 14, count 0 2006.285.21:03:45.51#ibcon#wrote, iclass 14, count 0 2006.285.21:03:45.51#ibcon#about to read 3, iclass 14, count 0 2006.285.21:03:45.53#ibcon#read 3, iclass 14, count 0 2006.285.21:03:45.53#ibcon#about to read 4, iclass 14, count 0 2006.285.21:03:45.53#ibcon#read 4, iclass 14, count 0 2006.285.21:03:45.53#ibcon#about to read 5, iclass 14, count 0 2006.285.21:03:45.53#ibcon#read 5, iclass 14, count 0 2006.285.21:03:45.53#ibcon#about to read 6, iclass 14, count 0 2006.285.21:03:45.53#ibcon#read 6, iclass 14, count 0 2006.285.21:03:45.53#ibcon#end of sib2, iclass 14, count 0 2006.285.21:03:45.53#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:03:45.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:03:45.53#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:03:45.53#ibcon#*before write, iclass 14, count 0 2006.285.21:03:45.53#ibcon#enter sib2, iclass 14, count 0 2006.285.21:03:45.53#ibcon#flushed, iclass 14, count 0 2006.285.21:03:45.53#ibcon#about to write, iclass 14, count 0 2006.285.21:03:45.53#ibcon#wrote, iclass 14, count 0 2006.285.21:03:45.53#ibcon#about to read 3, iclass 14, count 0 2006.285.21:03:45.57#ibcon#read 3, iclass 14, count 0 2006.285.21:03:45.57#ibcon#about to read 4, iclass 14, count 0 2006.285.21:03:45.57#ibcon#read 4, iclass 14, count 0 2006.285.21:03:45.57#ibcon#about to read 5, iclass 14, count 0 2006.285.21:03:45.57#ibcon#read 5, iclass 14, count 0 2006.285.21:03:45.57#ibcon#about to read 6, iclass 14, count 0 2006.285.21:03:45.57#ibcon#read 6, iclass 14, count 0 2006.285.21:03:45.57#ibcon#end of sib2, iclass 14, count 0 2006.285.21:03:45.57#ibcon#*after write, iclass 14, count 0 2006.285.21:03:45.57#ibcon#*before return 0, iclass 14, count 0 2006.285.21:03:45.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:03:45.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:03:45.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:03:45.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:03:45.57$vck44/va=6,4 2006.285.21:03:45.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.21:03:45.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.21:03:45.57#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:45.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:03:45.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:03:45.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:03:45.63#ibcon#enter wrdev, iclass 16, count 2 2006.285.21:03:45.63#ibcon#first serial, iclass 16, count 2 2006.285.21:03:45.63#ibcon#enter sib2, iclass 16, count 2 2006.285.21:03:45.63#ibcon#flushed, iclass 16, count 2 2006.285.21:03:45.63#ibcon#about to write, iclass 16, count 2 2006.285.21:03:45.63#ibcon#wrote, iclass 16, count 2 2006.285.21:03:45.63#ibcon#about to read 3, iclass 16, count 2 2006.285.21:03:45.65#ibcon#read 3, iclass 16, count 2 2006.285.21:03:45.65#ibcon#about to read 4, iclass 16, count 2 2006.285.21:03:45.65#ibcon#read 4, iclass 16, count 2 2006.285.21:03:45.65#ibcon#about to read 5, iclass 16, count 2 2006.285.21:03:45.65#ibcon#read 5, iclass 16, count 2 2006.285.21:03:45.65#ibcon#about to read 6, iclass 16, count 2 2006.285.21:03:45.65#ibcon#read 6, iclass 16, count 2 2006.285.21:03:45.65#ibcon#end of sib2, iclass 16, count 2 2006.285.21:03:45.65#ibcon#*mode == 0, iclass 16, count 2 2006.285.21:03:45.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.21:03:45.65#ibcon#[25=AT06-04\r\n] 2006.285.21:03:45.65#ibcon#*before write, iclass 16, count 2 2006.285.21:03:45.65#ibcon#enter sib2, iclass 16, count 2 2006.285.21:03:45.65#ibcon#flushed, iclass 16, count 2 2006.285.21:03:45.65#ibcon#about to write, iclass 16, count 2 2006.285.21:03:45.65#ibcon#wrote, iclass 16, count 2 2006.285.21:03:45.65#ibcon#about to read 3, iclass 16, count 2 2006.285.21:03:45.68#ibcon#read 3, iclass 16, count 2 2006.285.21:03:45.68#ibcon#about to read 4, iclass 16, count 2 2006.285.21:03:45.68#ibcon#read 4, iclass 16, count 2 2006.285.21:03:45.68#ibcon#about to read 5, iclass 16, count 2 2006.285.21:03:45.68#ibcon#read 5, iclass 16, count 2 2006.285.21:03:45.68#ibcon#about to read 6, iclass 16, count 2 2006.285.21:03:45.68#ibcon#read 6, iclass 16, count 2 2006.285.21:03:45.68#ibcon#end of sib2, iclass 16, count 2 2006.285.21:03:45.68#ibcon#*after write, iclass 16, count 2 2006.285.21:03:45.68#ibcon#*before return 0, iclass 16, count 2 2006.285.21:03:45.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:03:45.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:03:45.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.21:03:45.68#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:45.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:03:45.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:03:45.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:03:45.80#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:03:45.80#ibcon#first serial, iclass 16, count 0 2006.285.21:03:45.80#ibcon#enter sib2, iclass 16, count 0 2006.285.21:03:45.80#ibcon#flushed, iclass 16, count 0 2006.285.21:03:45.80#ibcon#about to write, iclass 16, count 0 2006.285.21:03:45.80#ibcon#wrote, iclass 16, count 0 2006.285.21:03:45.80#ibcon#about to read 3, iclass 16, count 0 2006.285.21:03:45.82#ibcon#read 3, iclass 16, count 0 2006.285.21:03:45.82#ibcon#about to read 4, iclass 16, count 0 2006.285.21:03:45.82#ibcon#read 4, iclass 16, count 0 2006.285.21:03:45.82#ibcon#about to read 5, iclass 16, count 0 2006.285.21:03:45.82#ibcon#read 5, iclass 16, count 0 2006.285.21:03:45.82#ibcon#about to read 6, iclass 16, count 0 2006.285.21:03:45.82#ibcon#read 6, iclass 16, count 0 2006.285.21:03:45.82#ibcon#end of sib2, iclass 16, count 0 2006.285.21:03:45.82#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:03:45.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:03:45.82#ibcon#[25=USB\r\n] 2006.285.21:03:45.82#ibcon#*before write, iclass 16, count 0 2006.285.21:03:45.82#ibcon#enter sib2, iclass 16, count 0 2006.285.21:03:45.82#ibcon#flushed, iclass 16, count 0 2006.285.21:03:45.82#ibcon#about to write, iclass 16, count 0 2006.285.21:03:45.82#ibcon#wrote, iclass 16, count 0 2006.285.21:03:45.82#ibcon#about to read 3, iclass 16, count 0 2006.285.21:03:45.85#ibcon#read 3, iclass 16, count 0 2006.285.21:03:45.85#ibcon#about to read 4, iclass 16, count 0 2006.285.21:03:45.85#ibcon#read 4, iclass 16, count 0 2006.285.21:03:45.85#ibcon#about to read 5, iclass 16, count 0 2006.285.21:03:45.85#ibcon#read 5, iclass 16, count 0 2006.285.21:03:45.85#ibcon#about to read 6, iclass 16, count 0 2006.285.21:03:45.85#ibcon#read 6, iclass 16, count 0 2006.285.21:03:45.85#ibcon#end of sib2, iclass 16, count 0 2006.285.21:03:45.85#ibcon#*after write, iclass 16, count 0 2006.285.21:03:45.85#ibcon#*before return 0, iclass 16, count 0 2006.285.21:03:45.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:03:45.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:03:45.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:03:45.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:03:45.85$vck44/valo=7,864.99 2006.285.21:03:45.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.21:03:45.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.21:03:45.85#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:45.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:03:45.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:03:45.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:03:45.85#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:03:45.85#ibcon#first serial, iclass 18, count 0 2006.285.21:03:45.85#ibcon#enter sib2, iclass 18, count 0 2006.285.21:03:45.85#ibcon#flushed, iclass 18, count 0 2006.285.21:03:45.85#ibcon#about to write, iclass 18, count 0 2006.285.21:03:45.85#ibcon#wrote, iclass 18, count 0 2006.285.21:03:45.85#ibcon#about to read 3, iclass 18, count 0 2006.285.21:03:45.87#ibcon#read 3, iclass 18, count 0 2006.285.21:03:45.87#ibcon#about to read 4, iclass 18, count 0 2006.285.21:03:45.87#ibcon#read 4, iclass 18, count 0 2006.285.21:03:45.87#ibcon#about to read 5, iclass 18, count 0 2006.285.21:03:45.87#ibcon#read 5, iclass 18, count 0 2006.285.21:03:45.87#ibcon#about to read 6, iclass 18, count 0 2006.285.21:03:45.87#ibcon#read 6, iclass 18, count 0 2006.285.21:03:45.87#ibcon#end of sib2, iclass 18, count 0 2006.285.21:03:45.87#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:03:45.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:03:45.87#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:03:45.87#ibcon#*before write, iclass 18, count 0 2006.285.21:03:45.87#ibcon#enter sib2, iclass 18, count 0 2006.285.21:03:45.87#ibcon#flushed, iclass 18, count 0 2006.285.21:03:45.87#ibcon#about to write, iclass 18, count 0 2006.285.21:03:45.87#ibcon#wrote, iclass 18, count 0 2006.285.21:03:45.87#ibcon#about to read 3, iclass 18, count 0 2006.285.21:03:45.91#ibcon#read 3, iclass 18, count 0 2006.285.21:03:45.91#ibcon#about to read 4, iclass 18, count 0 2006.285.21:03:45.91#ibcon#read 4, iclass 18, count 0 2006.285.21:03:45.91#ibcon#about to read 5, iclass 18, count 0 2006.285.21:03:45.91#ibcon#read 5, iclass 18, count 0 2006.285.21:03:45.91#ibcon#about to read 6, iclass 18, count 0 2006.285.21:03:45.91#ibcon#read 6, iclass 18, count 0 2006.285.21:03:45.91#ibcon#end of sib2, iclass 18, count 0 2006.285.21:03:45.91#ibcon#*after write, iclass 18, count 0 2006.285.21:03:45.91#ibcon#*before return 0, iclass 18, count 0 2006.285.21:03:45.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:03:45.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:03:45.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:03:45.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:03:45.91$vck44/va=7,4 2006.285.21:03:45.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.21:03:45.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.21:03:45.91#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:45.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:03:45.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:03:45.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:03:45.97#ibcon#enter wrdev, iclass 20, count 2 2006.285.21:03:45.97#ibcon#first serial, iclass 20, count 2 2006.285.21:03:45.97#ibcon#enter sib2, iclass 20, count 2 2006.285.21:03:45.97#ibcon#flushed, iclass 20, count 2 2006.285.21:03:45.97#ibcon#about to write, iclass 20, count 2 2006.285.21:03:45.97#ibcon#wrote, iclass 20, count 2 2006.285.21:03:45.97#ibcon#about to read 3, iclass 20, count 2 2006.285.21:03:45.99#ibcon#read 3, iclass 20, count 2 2006.285.21:03:45.99#ibcon#about to read 4, iclass 20, count 2 2006.285.21:03:45.99#ibcon#read 4, iclass 20, count 2 2006.285.21:03:45.99#ibcon#about to read 5, iclass 20, count 2 2006.285.21:03:45.99#ibcon#read 5, iclass 20, count 2 2006.285.21:03:45.99#ibcon#about to read 6, iclass 20, count 2 2006.285.21:03:45.99#ibcon#read 6, iclass 20, count 2 2006.285.21:03:45.99#ibcon#end of sib2, iclass 20, count 2 2006.285.21:03:45.99#ibcon#*mode == 0, iclass 20, count 2 2006.285.21:03:45.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.21:03:45.99#ibcon#[25=AT07-04\r\n] 2006.285.21:03:45.99#ibcon#*before write, iclass 20, count 2 2006.285.21:03:45.99#ibcon#enter sib2, iclass 20, count 2 2006.285.21:03:45.99#ibcon#flushed, iclass 20, count 2 2006.285.21:03:45.99#ibcon#about to write, iclass 20, count 2 2006.285.21:03:45.99#ibcon#wrote, iclass 20, count 2 2006.285.21:03:45.99#ibcon#about to read 3, iclass 20, count 2 2006.285.21:03:46.02#ibcon#read 3, iclass 20, count 2 2006.285.21:03:46.02#ibcon#about to read 4, iclass 20, count 2 2006.285.21:03:46.02#ibcon#read 4, iclass 20, count 2 2006.285.21:03:46.02#ibcon#about to read 5, iclass 20, count 2 2006.285.21:03:46.02#ibcon#read 5, iclass 20, count 2 2006.285.21:03:46.02#ibcon#about to read 6, iclass 20, count 2 2006.285.21:03:46.02#ibcon#read 6, iclass 20, count 2 2006.285.21:03:46.02#ibcon#end of sib2, iclass 20, count 2 2006.285.21:03:46.02#ibcon#*after write, iclass 20, count 2 2006.285.21:03:46.02#ibcon#*before return 0, iclass 20, count 2 2006.285.21:03:46.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:03:46.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:03:46.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.21:03:46.02#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:46.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:03:46.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:03:46.41#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:03:46.41#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:03:46.41#ibcon#first serial, iclass 20, count 0 2006.285.21:03:46.41#ibcon#enter sib2, iclass 20, count 0 2006.285.21:03:46.41#ibcon#flushed, iclass 20, count 0 2006.285.21:03:46.41#ibcon#about to write, iclass 20, count 0 2006.285.21:03:46.41#ibcon#wrote, iclass 20, count 0 2006.285.21:03:46.41#ibcon#about to read 3, iclass 20, count 0 2006.285.21:03:46.43#ibcon#read 3, iclass 20, count 0 2006.285.21:03:46.43#ibcon#about to read 4, iclass 20, count 0 2006.285.21:03:46.43#ibcon#read 4, iclass 20, count 0 2006.285.21:03:46.43#ibcon#about to read 5, iclass 20, count 0 2006.285.21:03:46.43#ibcon#read 5, iclass 20, count 0 2006.285.21:03:46.43#ibcon#about to read 6, iclass 20, count 0 2006.285.21:03:46.43#ibcon#read 6, iclass 20, count 0 2006.285.21:03:46.43#ibcon#end of sib2, iclass 20, count 0 2006.285.21:03:46.43#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:03:46.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:03:46.43#ibcon#[25=USB\r\n] 2006.285.21:03:46.43#ibcon#*before write, iclass 20, count 0 2006.285.21:03:46.43#ibcon#enter sib2, iclass 20, count 0 2006.285.21:03:46.43#ibcon#flushed, iclass 20, count 0 2006.285.21:03:46.43#ibcon#about to write, iclass 20, count 0 2006.285.21:03:46.43#ibcon#wrote, iclass 20, count 0 2006.285.21:03:46.43#ibcon#about to read 3, iclass 20, count 0 2006.285.21:03:46.46#ibcon#read 3, iclass 20, count 0 2006.285.21:03:46.46#ibcon#about to read 4, iclass 20, count 0 2006.285.21:03:46.46#ibcon#read 4, iclass 20, count 0 2006.285.21:03:46.46#ibcon#about to read 5, iclass 20, count 0 2006.285.21:03:46.46#ibcon#read 5, iclass 20, count 0 2006.285.21:03:46.46#ibcon#about to read 6, iclass 20, count 0 2006.285.21:03:46.46#ibcon#read 6, iclass 20, count 0 2006.285.21:03:46.46#ibcon#end of sib2, iclass 20, count 0 2006.285.21:03:46.46#ibcon#*after write, iclass 20, count 0 2006.285.21:03:46.46#ibcon#*before return 0, iclass 20, count 0 2006.285.21:03:46.46#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:03:46.46#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:03:46.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:03:46.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:03:46.46$vck44/valo=8,884.99 2006.285.21:03:46.46#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.21:03:46.46#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.21:03:46.46#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:46.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:03:46.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:03:46.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:03:46.46#ibcon#enter wrdev, iclass 22, count 0 2006.285.21:03:46.46#ibcon#first serial, iclass 22, count 0 2006.285.21:03:46.46#ibcon#enter sib2, iclass 22, count 0 2006.285.21:03:46.46#ibcon#flushed, iclass 22, count 0 2006.285.21:03:46.46#ibcon#about to write, iclass 22, count 0 2006.285.21:03:46.46#ibcon#wrote, iclass 22, count 0 2006.285.21:03:46.46#ibcon#about to read 3, iclass 22, count 0 2006.285.21:03:46.48#ibcon#read 3, iclass 22, count 0 2006.285.21:03:46.48#ibcon#about to read 4, iclass 22, count 0 2006.285.21:03:46.48#ibcon#read 4, iclass 22, count 0 2006.285.21:03:46.48#ibcon#about to read 5, iclass 22, count 0 2006.285.21:03:46.48#ibcon#read 5, iclass 22, count 0 2006.285.21:03:46.48#ibcon#about to read 6, iclass 22, count 0 2006.285.21:03:46.48#ibcon#read 6, iclass 22, count 0 2006.285.21:03:46.48#ibcon#end of sib2, iclass 22, count 0 2006.285.21:03:46.48#ibcon#*mode == 0, iclass 22, count 0 2006.285.21:03:46.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.21:03:46.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:03:46.48#ibcon#*before write, iclass 22, count 0 2006.285.21:03:46.48#ibcon#enter sib2, iclass 22, count 0 2006.285.21:03:46.48#ibcon#flushed, iclass 22, count 0 2006.285.21:03:46.48#ibcon#about to write, iclass 22, count 0 2006.285.21:03:46.48#ibcon#wrote, iclass 22, count 0 2006.285.21:03:46.48#ibcon#about to read 3, iclass 22, count 0 2006.285.21:03:46.52#ibcon#read 3, iclass 22, count 0 2006.285.21:03:46.52#ibcon#about to read 4, iclass 22, count 0 2006.285.21:03:46.52#ibcon#read 4, iclass 22, count 0 2006.285.21:03:46.52#ibcon#about to read 5, iclass 22, count 0 2006.285.21:03:46.52#ibcon#read 5, iclass 22, count 0 2006.285.21:03:46.52#ibcon#about to read 6, iclass 22, count 0 2006.285.21:03:46.52#ibcon#read 6, iclass 22, count 0 2006.285.21:03:46.52#ibcon#end of sib2, iclass 22, count 0 2006.285.21:03:46.52#ibcon#*after write, iclass 22, count 0 2006.285.21:03:46.52#ibcon#*before return 0, iclass 22, count 0 2006.285.21:03:46.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:03:46.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:03:46.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.21:03:46.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.21:03:46.52$vck44/va=8,3 2006.285.21:03:46.52#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.21:03:46.52#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.21:03:46.52#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:46.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:03:46.56#abcon#<5=/00 0.2 0.5 14.191001015.5\r\n> 2006.285.21:03:46.58#abcon#{5=INTERFACE CLEAR} 2006.285.21:03:46.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:03:46.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:03:46.58#ibcon#enter wrdev, iclass 25, count 2 2006.285.21:03:46.58#ibcon#first serial, iclass 25, count 2 2006.285.21:03:46.58#ibcon#enter sib2, iclass 25, count 2 2006.285.21:03:46.58#ibcon#flushed, iclass 25, count 2 2006.285.21:03:46.58#ibcon#about to write, iclass 25, count 2 2006.285.21:03:46.58#ibcon#wrote, iclass 25, count 2 2006.285.21:03:46.58#ibcon#about to read 3, iclass 25, count 2 2006.285.21:03:46.60#ibcon#read 3, iclass 25, count 2 2006.285.21:03:46.60#ibcon#about to read 4, iclass 25, count 2 2006.285.21:03:46.60#ibcon#read 4, iclass 25, count 2 2006.285.21:03:46.60#ibcon#about to read 5, iclass 25, count 2 2006.285.21:03:46.60#ibcon#read 5, iclass 25, count 2 2006.285.21:03:46.60#ibcon#about to read 6, iclass 25, count 2 2006.285.21:03:46.60#ibcon#read 6, iclass 25, count 2 2006.285.21:03:46.60#ibcon#end of sib2, iclass 25, count 2 2006.285.21:03:46.60#ibcon#*mode == 0, iclass 25, count 2 2006.285.21:03:46.60#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.21:03:46.60#ibcon#[25=AT08-03\r\n] 2006.285.21:03:46.60#ibcon#*before write, iclass 25, count 2 2006.285.21:03:46.60#ibcon#enter sib2, iclass 25, count 2 2006.285.21:03:46.60#ibcon#flushed, iclass 25, count 2 2006.285.21:03:46.60#ibcon#about to write, iclass 25, count 2 2006.285.21:03:46.60#ibcon#wrote, iclass 25, count 2 2006.285.21:03:46.60#ibcon#about to read 3, iclass 25, count 2 2006.285.21:03:46.63#ibcon#read 3, iclass 25, count 2 2006.285.21:03:46.63#ibcon#about to read 4, iclass 25, count 2 2006.285.21:03:46.63#ibcon#read 4, iclass 25, count 2 2006.285.21:03:46.63#ibcon#about to read 5, iclass 25, count 2 2006.285.21:03:46.63#ibcon#read 5, iclass 25, count 2 2006.285.21:03:46.63#ibcon#about to read 6, iclass 25, count 2 2006.285.21:03:46.63#ibcon#read 6, iclass 25, count 2 2006.285.21:03:46.63#ibcon#end of sib2, iclass 25, count 2 2006.285.21:03:46.63#ibcon#*after write, iclass 25, count 2 2006.285.21:03:46.63#ibcon#*before return 0, iclass 25, count 2 2006.285.21:03:46.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:03:46.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:03:46.63#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.21:03:46.63#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:46.63#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:03:46.64#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:03:46.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:03:46.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:03:46.75#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:03:46.75#ibcon#first serial, iclass 25, count 0 2006.285.21:03:46.75#ibcon#enter sib2, iclass 25, count 0 2006.285.21:03:46.75#ibcon#flushed, iclass 25, count 0 2006.285.21:03:46.75#ibcon#about to write, iclass 25, count 0 2006.285.21:03:46.75#ibcon#wrote, iclass 25, count 0 2006.285.21:03:46.75#ibcon#about to read 3, iclass 25, count 0 2006.285.21:03:46.77#ibcon#read 3, iclass 25, count 0 2006.285.21:03:46.77#ibcon#about to read 4, iclass 25, count 0 2006.285.21:03:46.77#ibcon#read 4, iclass 25, count 0 2006.285.21:03:46.77#ibcon#about to read 5, iclass 25, count 0 2006.285.21:03:46.77#ibcon#read 5, iclass 25, count 0 2006.285.21:03:46.77#ibcon#about to read 6, iclass 25, count 0 2006.285.21:03:46.77#ibcon#read 6, iclass 25, count 0 2006.285.21:03:46.77#ibcon#end of sib2, iclass 25, count 0 2006.285.21:03:46.77#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:03:46.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:03:46.77#ibcon#[25=USB\r\n] 2006.285.21:03:46.77#ibcon#*before write, iclass 25, count 0 2006.285.21:03:46.77#ibcon#enter sib2, iclass 25, count 0 2006.285.21:03:46.77#ibcon#flushed, iclass 25, count 0 2006.285.21:03:46.77#ibcon#about to write, iclass 25, count 0 2006.285.21:03:46.77#ibcon#wrote, iclass 25, count 0 2006.285.21:03:46.77#ibcon#about to read 3, iclass 25, count 0 2006.285.21:03:46.80#ibcon#read 3, iclass 25, count 0 2006.285.21:03:46.80#ibcon#about to read 4, iclass 25, count 0 2006.285.21:03:46.80#ibcon#read 4, iclass 25, count 0 2006.285.21:03:46.80#ibcon#about to read 5, iclass 25, count 0 2006.285.21:03:46.80#ibcon#read 5, iclass 25, count 0 2006.285.21:03:46.80#ibcon#about to read 6, iclass 25, count 0 2006.285.21:03:46.80#ibcon#read 6, iclass 25, count 0 2006.285.21:03:46.80#ibcon#end of sib2, iclass 25, count 0 2006.285.21:03:46.80#ibcon#*after write, iclass 25, count 0 2006.285.21:03:46.80#ibcon#*before return 0, iclass 25, count 0 2006.285.21:03:46.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:03:46.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:03:46.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:03:46.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:03:46.80$vck44/vblo=1,629.99 2006.285.21:03:46.80#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.21:03:46.80#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.21:03:46.80#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:46.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:03:46.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:03:46.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:03:46.80#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:03:46.80#ibcon#first serial, iclass 30, count 0 2006.285.21:03:46.80#ibcon#enter sib2, iclass 30, count 0 2006.285.21:03:46.80#ibcon#flushed, iclass 30, count 0 2006.285.21:03:46.80#ibcon#about to write, iclass 30, count 0 2006.285.21:03:46.80#ibcon#wrote, iclass 30, count 0 2006.285.21:03:46.80#ibcon#about to read 3, iclass 30, count 0 2006.285.21:03:46.82#ibcon#read 3, iclass 30, count 0 2006.285.21:03:46.82#ibcon#about to read 4, iclass 30, count 0 2006.285.21:03:46.82#ibcon#read 4, iclass 30, count 0 2006.285.21:03:46.82#ibcon#about to read 5, iclass 30, count 0 2006.285.21:03:46.82#ibcon#read 5, iclass 30, count 0 2006.285.21:03:46.82#ibcon#about to read 6, iclass 30, count 0 2006.285.21:03:46.82#ibcon#read 6, iclass 30, count 0 2006.285.21:03:46.82#ibcon#end of sib2, iclass 30, count 0 2006.285.21:03:46.82#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:03:46.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:03:46.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:03:46.82#ibcon#*before write, iclass 30, count 0 2006.285.21:03:46.82#ibcon#enter sib2, iclass 30, count 0 2006.285.21:03:46.82#ibcon#flushed, iclass 30, count 0 2006.285.21:03:46.82#ibcon#about to write, iclass 30, count 0 2006.285.21:03:46.82#ibcon#wrote, iclass 30, count 0 2006.285.21:03:46.82#ibcon#about to read 3, iclass 30, count 0 2006.285.21:03:46.86#ibcon#read 3, iclass 30, count 0 2006.285.21:03:46.86#ibcon#about to read 4, iclass 30, count 0 2006.285.21:03:46.86#ibcon#read 4, iclass 30, count 0 2006.285.21:03:46.86#ibcon#about to read 5, iclass 30, count 0 2006.285.21:03:46.86#ibcon#read 5, iclass 30, count 0 2006.285.21:03:46.86#ibcon#about to read 6, iclass 30, count 0 2006.285.21:03:46.86#ibcon#read 6, iclass 30, count 0 2006.285.21:03:46.86#ibcon#end of sib2, iclass 30, count 0 2006.285.21:03:46.86#ibcon#*after write, iclass 30, count 0 2006.285.21:03:46.86#ibcon#*before return 0, iclass 30, count 0 2006.285.21:03:46.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:03:46.86#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:03:46.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:03:46.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:03:46.86$vck44/vb=1,4 2006.285.21:03:46.86#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.21:03:46.86#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.21:03:46.86#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:46.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:03:46.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:03:46.86#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:03:46.86#ibcon#enter wrdev, iclass 32, count 2 2006.285.21:03:46.86#ibcon#first serial, iclass 32, count 2 2006.285.21:03:46.86#ibcon#enter sib2, iclass 32, count 2 2006.285.21:03:46.86#ibcon#flushed, iclass 32, count 2 2006.285.21:03:46.86#ibcon#about to write, iclass 32, count 2 2006.285.21:03:46.86#ibcon#wrote, iclass 32, count 2 2006.285.21:03:46.86#ibcon#about to read 3, iclass 32, count 2 2006.285.21:03:46.88#ibcon#read 3, iclass 32, count 2 2006.285.21:03:46.88#ibcon#about to read 4, iclass 32, count 2 2006.285.21:03:46.88#ibcon#read 4, iclass 32, count 2 2006.285.21:03:46.88#ibcon#about to read 5, iclass 32, count 2 2006.285.21:03:46.88#ibcon#read 5, iclass 32, count 2 2006.285.21:03:46.88#ibcon#about to read 6, iclass 32, count 2 2006.285.21:03:46.88#ibcon#read 6, iclass 32, count 2 2006.285.21:03:46.88#ibcon#end of sib2, iclass 32, count 2 2006.285.21:03:46.88#ibcon#*mode == 0, iclass 32, count 2 2006.285.21:03:46.88#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.21:03:46.88#ibcon#[27=AT01-04\r\n] 2006.285.21:03:46.88#ibcon#*before write, iclass 32, count 2 2006.285.21:03:46.88#ibcon#enter sib2, iclass 32, count 2 2006.285.21:03:46.88#ibcon#flushed, iclass 32, count 2 2006.285.21:03:46.88#ibcon#about to write, iclass 32, count 2 2006.285.21:03:46.88#ibcon#wrote, iclass 32, count 2 2006.285.21:03:46.88#ibcon#about to read 3, iclass 32, count 2 2006.285.21:03:46.91#ibcon#read 3, iclass 32, count 2 2006.285.21:03:46.91#ibcon#about to read 4, iclass 32, count 2 2006.285.21:03:46.91#ibcon#read 4, iclass 32, count 2 2006.285.21:03:46.91#ibcon#about to read 5, iclass 32, count 2 2006.285.21:03:46.91#ibcon#read 5, iclass 32, count 2 2006.285.21:03:46.91#ibcon#about to read 6, iclass 32, count 2 2006.285.21:03:46.91#ibcon#read 6, iclass 32, count 2 2006.285.21:03:46.91#ibcon#end of sib2, iclass 32, count 2 2006.285.21:03:46.91#ibcon#*after write, iclass 32, count 2 2006.285.21:03:46.91#ibcon#*before return 0, iclass 32, count 2 2006.285.21:03:46.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:03:46.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:03:46.91#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.21:03:46.91#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:46.91#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:03:47.03#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:03:47.03#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:03:47.03#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:03:47.03#ibcon#first serial, iclass 32, count 0 2006.285.21:03:47.03#ibcon#enter sib2, iclass 32, count 0 2006.285.21:03:47.03#ibcon#flushed, iclass 32, count 0 2006.285.21:03:47.03#ibcon#about to write, iclass 32, count 0 2006.285.21:03:47.03#ibcon#wrote, iclass 32, count 0 2006.285.21:03:47.03#ibcon#about to read 3, iclass 32, count 0 2006.285.21:03:47.05#ibcon#read 3, iclass 32, count 0 2006.285.21:03:47.05#ibcon#about to read 4, iclass 32, count 0 2006.285.21:03:47.05#ibcon#read 4, iclass 32, count 0 2006.285.21:03:47.05#ibcon#about to read 5, iclass 32, count 0 2006.285.21:03:47.05#ibcon#read 5, iclass 32, count 0 2006.285.21:03:47.05#ibcon#about to read 6, iclass 32, count 0 2006.285.21:03:47.05#ibcon#read 6, iclass 32, count 0 2006.285.21:03:47.05#ibcon#end of sib2, iclass 32, count 0 2006.285.21:03:47.05#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:03:47.05#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:03:47.05#ibcon#[27=USB\r\n] 2006.285.21:03:47.05#ibcon#*before write, iclass 32, count 0 2006.285.21:03:47.05#ibcon#enter sib2, iclass 32, count 0 2006.285.21:03:47.05#ibcon#flushed, iclass 32, count 0 2006.285.21:03:47.05#ibcon#about to write, iclass 32, count 0 2006.285.21:03:47.05#ibcon#wrote, iclass 32, count 0 2006.285.21:03:47.05#ibcon#about to read 3, iclass 32, count 0 2006.285.21:03:47.08#ibcon#read 3, iclass 32, count 0 2006.285.21:03:47.08#ibcon#about to read 4, iclass 32, count 0 2006.285.21:03:47.08#ibcon#read 4, iclass 32, count 0 2006.285.21:03:47.08#ibcon#about to read 5, iclass 32, count 0 2006.285.21:03:47.08#ibcon#read 5, iclass 32, count 0 2006.285.21:03:47.08#ibcon#about to read 6, iclass 32, count 0 2006.285.21:03:47.08#ibcon#read 6, iclass 32, count 0 2006.285.21:03:47.08#ibcon#end of sib2, iclass 32, count 0 2006.285.21:03:47.08#ibcon#*after write, iclass 32, count 0 2006.285.21:03:47.08#ibcon#*before return 0, iclass 32, count 0 2006.285.21:03:47.08#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:03:47.08#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:03:47.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:03:47.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:03:47.08$vck44/vblo=2,634.99 2006.285.21:03:47.08#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.21:03:47.08#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.21:03:47.08#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:47.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:03:47.08#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:03:47.08#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:03:47.08#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:03:47.08#ibcon#first serial, iclass 34, count 0 2006.285.21:03:47.08#ibcon#enter sib2, iclass 34, count 0 2006.285.21:03:47.08#ibcon#flushed, iclass 34, count 0 2006.285.21:03:47.08#ibcon#about to write, iclass 34, count 0 2006.285.21:03:47.08#ibcon#wrote, iclass 34, count 0 2006.285.21:03:47.08#ibcon#about to read 3, iclass 34, count 0 2006.285.21:03:47.10#ibcon#read 3, iclass 34, count 0 2006.285.21:03:47.38#ibcon#about to read 4, iclass 34, count 0 2006.285.21:03:47.38#ibcon#read 4, iclass 34, count 0 2006.285.21:03:47.38#ibcon#about to read 5, iclass 34, count 0 2006.285.21:03:47.38#ibcon#read 5, iclass 34, count 0 2006.285.21:03:47.38#ibcon#about to read 6, iclass 34, count 0 2006.285.21:03:47.38#ibcon#read 6, iclass 34, count 0 2006.285.21:03:47.38#ibcon#end of sib2, iclass 34, count 0 2006.285.21:03:47.38#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:03:47.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:03:47.38#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:03:47.38#ibcon#*before write, iclass 34, count 0 2006.285.21:03:47.38#ibcon#enter sib2, iclass 34, count 0 2006.285.21:03:47.38#ibcon#flushed, iclass 34, count 0 2006.285.21:03:47.38#ibcon#about to write, iclass 34, count 0 2006.285.21:03:47.38#ibcon#wrote, iclass 34, count 0 2006.285.21:03:47.38#ibcon#about to read 3, iclass 34, count 0 2006.285.21:03:47.42#ibcon#read 3, iclass 34, count 0 2006.285.21:03:47.42#ibcon#about to read 4, iclass 34, count 0 2006.285.21:03:47.42#ibcon#read 4, iclass 34, count 0 2006.285.21:03:47.42#ibcon#about to read 5, iclass 34, count 0 2006.285.21:03:47.42#ibcon#read 5, iclass 34, count 0 2006.285.21:03:47.42#ibcon#about to read 6, iclass 34, count 0 2006.285.21:03:47.42#ibcon#read 6, iclass 34, count 0 2006.285.21:03:47.42#ibcon#end of sib2, iclass 34, count 0 2006.285.21:03:47.42#ibcon#*after write, iclass 34, count 0 2006.285.21:03:47.42#ibcon#*before return 0, iclass 34, count 0 2006.285.21:03:47.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:03:47.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:03:47.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:03:47.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:03:47.42$vck44/vb=2,5 2006.285.21:03:47.42#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.21:03:47.42#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.21:03:47.42#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:47.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:03:47.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:03:47.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:03:47.42#ibcon#enter wrdev, iclass 36, count 2 2006.285.21:03:47.42#ibcon#first serial, iclass 36, count 2 2006.285.21:03:47.42#ibcon#enter sib2, iclass 36, count 2 2006.285.21:03:47.42#ibcon#flushed, iclass 36, count 2 2006.285.21:03:47.42#ibcon#about to write, iclass 36, count 2 2006.285.21:03:47.42#ibcon#wrote, iclass 36, count 2 2006.285.21:03:47.42#ibcon#about to read 3, iclass 36, count 2 2006.285.21:03:47.44#ibcon#read 3, iclass 36, count 2 2006.285.21:03:47.44#ibcon#about to read 4, iclass 36, count 2 2006.285.21:03:47.44#ibcon#read 4, iclass 36, count 2 2006.285.21:03:47.44#ibcon#about to read 5, iclass 36, count 2 2006.285.21:03:47.44#ibcon#read 5, iclass 36, count 2 2006.285.21:03:47.44#ibcon#about to read 6, iclass 36, count 2 2006.285.21:03:47.44#ibcon#read 6, iclass 36, count 2 2006.285.21:03:47.44#ibcon#end of sib2, iclass 36, count 2 2006.285.21:03:47.44#ibcon#*mode == 0, iclass 36, count 2 2006.285.21:03:47.44#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.21:03:47.44#ibcon#[27=AT02-05\r\n] 2006.285.21:03:47.44#ibcon#*before write, iclass 36, count 2 2006.285.21:03:47.44#ibcon#enter sib2, iclass 36, count 2 2006.285.21:03:47.44#ibcon#flushed, iclass 36, count 2 2006.285.21:03:47.44#ibcon#about to write, iclass 36, count 2 2006.285.21:03:47.44#ibcon#wrote, iclass 36, count 2 2006.285.21:03:47.44#ibcon#about to read 3, iclass 36, count 2 2006.285.21:03:47.47#ibcon#read 3, iclass 36, count 2 2006.285.21:03:47.47#ibcon#about to read 4, iclass 36, count 2 2006.285.21:03:47.47#ibcon#read 4, iclass 36, count 2 2006.285.21:03:47.47#ibcon#about to read 5, iclass 36, count 2 2006.285.21:03:47.47#ibcon#read 5, iclass 36, count 2 2006.285.21:03:47.47#ibcon#about to read 6, iclass 36, count 2 2006.285.21:03:47.47#ibcon#read 6, iclass 36, count 2 2006.285.21:03:47.47#ibcon#end of sib2, iclass 36, count 2 2006.285.21:03:47.47#ibcon#*after write, iclass 36, count 2 2006.285.21:03:47.47#ibcon#*before return 0, iclass 36, count 2 2006.285.21:03:47.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:03:47.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:03:47.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.21:03:47.47#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:47.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:03:47.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:03:47.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:03:47.59#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:03:47.59#ibcon#first serial, iclass 36, count 0 2006.285.21:03:47.59#ibcon#enter sib2, iclass 36, count 0 2006.285.21:03:47.59#ibcon#flushed, iclass 36, count 0 2006.285.21:03:47.59#ibcon#about to write, iclass 36, count 0 2006.285.21:03:47.59#ibcon#wrote, iclass 36, count 0 2006.285.21:03:47.59#ibcon#about to read 3, iclass 36, count 0 2006.285.21:03:47.61#ibcon#read 3, iclass 36, count 0 2006.285.21:03:47.61#ibcon#about to read 4, iclass 36, count 0 2006.285.21:03:47.61#ibcon#read 4, iclass 36, count 0 2006.285.21:03:47.61#ibcon#about to read 5, iclass 36, count 0 2006.285.21:03:47.61#ibcon#read 5, iclass 36, count 0 2006.285.21:03:47.61#ibcon#about to read 6, iclass 36, count 0 2006.285.21:03:47.61#ibcon#read 6, iclass 36, count 0 2006.285.21:03:47.61#ibcon#end of sib2, iclass 36, count 0 2006.285.21:03:47.61#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:03:47.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:03:47.61#ibcon#[27=USB\r\n] 2006.285.21:03:47.61#ibcon#*before write, iclass 36, count 0 2006.285.21:03:47.61#ibcon#enter sib2, iclass 36, count 0 2006.285.21:03:47.61#ibcon#flushed, iclass 36, count 0 2006.285.21:03:47.61#ibcon#about to write, iclass 36, count 0 2006.285.21:03:47.61#ibcon#wrote, iclass 36, count 0 2006.285.21:03:47.61#ibcon#about to read 3, iclass 36, count 0 2006.285.21:03:47.64#ibcon#read 3, iclass 36, count 0 2006.285.21:03:47.64#ibcon#about to read 4, iclass 36, count 0 2006.285.21:03:47.64#ibcon#read 4, iclass 36, count 0 2006.285.21:03:47.64#ibcon#about to read 5, iclass 36, count 0 2006.285.21:03:47.64#ibcon#read 5, iclass 36, count 0 2006.285.21:03:47.64#ibcon#about to read 6, iclass 36, count 0 2006.285.21:03:47.64#ibcon#read 6, iclass 36, count 0 2006.285.21:03:47.64#ibcon#end of sib2, iclass 36, count 0 2006.285.21:03:47.64#ibcon#*after write, iclass 36, count 0 2006.285.21:03:47.64#ibcon#*before return 0, iclass 36, count 0 2006.285.21:03:47.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:03:47.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:03:47.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:03:47.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:03:47.64$vck44/vblo=3,649.99 2006.285.21:03:47.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.21:03:47.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.21:03:47.64#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:47.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:03:47.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:03:47.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:03:47.64#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:03:47.64#ibcon#first serial, iclass 38, count 0 2006.285.21:03:47.64#ibcon#enter sib2, iclass 38, count 0 2006.285.21:03:47.64#ibcon#flushed, iclass 38, count 0 2006.285.21:03:47.64#ibcon#about to write, iclass 38, count 0 2006.285.21:03:47.64#ibcon#wrote, iclass 38, count 0 2006.285.21:03:47.64#ibcon#about to read 3, iclass 38, count 0 2006.285.21:03:47.66#ibcon#read 3, iclass 38, count 0 2006.285.21:03:47.66#ibcon#about to read 4, iclass 38, count 0 2006.285.21:03:47.66#ibcon#read 4, iclass 38, count 0 2006.285.21:03:47.66#ibcon#about to read 5, iclass 38, count 0 2006.285.21:03:47.66#ibcon#read 5, iclass 38, count 0 2006.285.21:03:47.66#ibcon#about to read 6, iclass 38, count 0 2006.285.21:03:47.66#ibcon#read 6, iclass 38, count 0 2006.285.21:03:47.66#ibcon#end of sib2, iclass 38, count 0 2006.285.21:03:47.66#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:03:47.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:03:47.66#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:03:47.66#ibcon#*before write, iclass 38, count 0 2006.285.21:03:47.66#ibcon#enter sib2, iclass 38, count 0 2006.285.21:03:47.66#ibcon#flushed, iclass 38, count 0 2006.285.21:03:47.66#ibcon#about to write, iclass 38, count 0 2006.285.21:03:47.66#ibcon#wrote, iclass 38, count 0 2006.285.21:03:47.66#ibcon#about to read 3, iclass 38, count 0 2006.285.21:03:47.70#ibcon#read 3, iclass 38, count 0 2006.285.21:03:47.70#ibcon#about to read 4, iclass 38, count 0 2006.285.21:03:47.70#ibcon#read 4, iclass 38, count 0 2006.285.21:03:47.70#ibcon#about to read 5, iclass 38, count 0 2006.285.21:03:47.70#ibcon#read 5, iclass 38, count 0 2006.285.21:03:47.70#ibcon#about to read 6, iclass 38, count 0 2006.285.21:03:47.70#ibcon#read 6, iclass 38, count 0 2006.285.21:03:47.70#ibcon#end of sib2, iclass 38, count 0 2006.285.21:03:47.70#ibcon#*after write, iclass 38, count 0 2006.285.21:03:47.70#ibcon#*before return 0, iclass 38, count 0 2006.285.21:03:47.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:03:47.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:03:47.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:03:47.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:03:47.70$vck44/vb=3,4 2006.285.21:03:47.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.21:03:47.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.21:03:47.70#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:47.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:03:47.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:03:47.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:03:47.76#ibcon#enter wrdev, iclass 40, count 2 2006.285.21:03:47.76#ibcon#first serial, iclass 40, count 2 2006.285.21:03:47.76#ibcon#enter sib2, iclass 40, count 2 2006.285.21:03:47.76#ibcon#flushed, iclass 40, count 2 2006.285.21:03:47.76#ibcon#about to write, iclass 40, count 2 2006.285.21:03:47.76#ibcon#wrote, iclass 40, count 2 2006.285.21:03:47.76#ibcon#about to read 3, iclass 40, count 2 2006.285.21:03:47.78#ibcon#read 3, iclass 40, count 2 2006.285.21:03:47.78#ibcon#about to read 4, iclass 40, count 2 2006.285.21:03:47.78#ibcon#read 4, iclass 40, count 2 2006.285.21:03:47.78#ibcon#about to read 5, iclass 40, count 2 2006.285.21:03:47.78#ibcon#read 5, iclass 40, count 2 2006.285.21:03:47.78#ibcon#about to read 6, iclass 40, count 2 2006.285.21:03:47.78#ibcon#read 6, iclass 40, count 2 2006.285.21:03:47.78#ibcon#end of sib2, iclass 40, count 2 2006.285.21:03:47.78#ibcon#*mode == 0, iclass 40, count 2 2006.285.21:03:47.78#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.21:03:47.78#ibcon#[27=AT03-04\r\n] 2006.285.21:03:47.78#ibcon#*before write, iclass 40, count 2 2006.285.21:03:47.78#ibcon#enter sib2, iclass 40, count 2 2006.285.21:03:47.78#ibcon#flushed, iclass 40, count 2 2006.285.21:03:47.78#ibcon#about to write, iclass 40, count 2 2006.285.21:03:47.78#ibcon#wrote, iclass 40, count 2 2006.285.21:03:47.78#ibcon#about to read 3, iclass 40, count 2 2006.285.21:03:47.81#ibcon#read 3, iclass 40, count 2 2006.285.21:03:47.81#ibcon#about to read 4, iclass 40, count 2 2006.285.21:03:47.81#ibcon#read 4, iclass 40, count 2 2006.285.21:03:47.81#ibcon#about to read 5, iclass 40, count 2 2006.285.21:03:47.81#ibcon#read 5, iclass 40, count 2 2006.285.21:03:47.81#ibcon#about to read 6, iclass 40, count 2 2006.285.21:03:47.81#ibcon#read 6, iclass 40, count 2 2006.285.21:03:47.81#ibcon#end of sib2, iclass 40, count 2 2006.285.21:03:47.81#ibcon#*after write, iclass 40, count 2 2006.285.21:03:47.81#ibcon#*before return 0, iclass 40, count 2 2006.285.21:03:47.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:03:47.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:03:47.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.21:03:47.81#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:47.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:03:47.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:03:47.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:03:47.93#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:03:47.93#ibcon#first serial, iclass 40, count 0 2006.285.21:03:47.93#ibcon#enter sib2, iclass 40, count 0 2006.285.21:03:47.93#ibcon#flushed, iclass 40, count 0 2006.285.21:03:47.93#ibcon#about to write, iclass 40, count 0 2006.285.21:03:47.93#ibcon#wrote, iclass 40, count 0 2006.285.21:03:47.93#ibcon#about to read 3, iclass 40, count 0 2006.285.21:03:47.95#ibcon#read 3, iclass 40, count 0 2006.285.21:03:47.95#ibcon#about to read 4, iclass 40, count 0 2006.285.21:03:47.95#ibcon#read 4, iclass 40, count 0 2006.285.21:03:47.95#ibcon#about to read 5, iclass 40, count 0 2006.285.21:03:47.95#ibcon#read 5, iclass 40, count 0 2006.285.21:03:47.95#ibcon#about to read 6, iclass 40, count 0 2006.285.21:03:47.95#ibcon#read 6, iclass 40, count 0 2006.285.21:03:47.95#ibcon#end of sib2, iclass 40, count 0 2006.285.21:03:47.95#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:03:47.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:03:47.95#ibcon#[27=USB\r\n] 2006.285.21:03:47.95#ibcon#*before write, iclass 40, count 0 2006.285.21:03:47.95#ibcon#enter sib2, iclass 40, count 0 2006.285.21:03:47.95#ibcon#flushed, iclass 40, count 0 2006.285.21:03:47.95#ibcon#about to write, iclass 40, count 0 2006.285.21:03:47.95#ibcon#wrote, iclass 40, count 0 2006.285.21:03:47.95#ibcon#about to read 3, iclass 40, count 0 2006.285.21:03:47.98#ibcon#read 3, iclass 40, count 0 2006.285.21:03:47.98#ibcon#about to read 4, iclass 40, count 0 2006.285.21:03:47.98#ibcon#read 4, iclass 40, count 0 2006.285.21:03:47.98#ibcon#about to read 5, iclass 40, count 0 2006.285.21:03:47.98#ibcon#read 5, iclass 40, count 0 2006.285.21:03:47.98#ibcon#about to read 6, iclass 40, count 0 2006.285.21:03:47.98#ibcon#read 6, iclass 40, count 0 2006.285.21:03:47.98#ibcon#end of sib2, iclass 40, count 0 2006.285.21:03:47.98#ibcon#*after write, iclass 40, count 0 2006.285.21:03:47.98#ibcon#*before return 0, iclass 40, count 0 2006.285.21:03:47.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:03:47.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:03:47.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:03:47.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:03:47.98$vck44/vblo=4,679.99 2006.285.21:03:47.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.21:03:47.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.21:03:47.98#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:47.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:03:47.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:03:47.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:03:47.98#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:03:47.98#ibcon#first serial, iclass 4, count 0 2006.285.21:03:47.98#ibcon#enter sib2, iclass 4, count 0 2006.285.21:03:47.98#ibcon#flushed, iclass 4, count 0 2006.285.21:03:47.98#ibcon#about to write, iclass 4, count 0 2006.285.21:03:47.98#ibcon#wrote, iclass 4, count 0 2006.285.21:03:47.98#ibcon#about to read 3, iclass 4, count 0 2006.285.21:03:48.00#ibcon#read 3, iclass 4, count 0 2006.285.21:03:48.00#ibcon#about to read 4, iclass 4, count 0 2006.285.21:03:48.00#ibcon#read 4, iclass 4, count 0 2006.285.21:03:48.00#ibcon#about to read 5, iclass 4, count 0 2006.285.21:03:48.00#ibcon#read 5, iclass 4, count 0 2006.285.21:03:48.00#ibcon#about to read 6, iclass 4, count 0 2006.285.21:03:48.00#ibcon#read 6, iclass 4, count 0 2006.285.21:03:48.00#ibcon#end of sib2, iclass 4, count 0 2006.285.21:03:48.00#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:03:48.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:03:48.00#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:03:48.00#ibcon#*before write, iclass 4, count 0 2006.285.21:03:48.00#ibcon#enter sib2, iclass 4, count 0 2006.285.21:03:48.00#ibcon#flushed, iclass 4, count 0 2006.285.21:03:48.00#ibcon#about to write, iclass 4, count 0 2006.285.21:03:48.00#ibcon#wrote, iclass 4, count 0 2006.285.21:03:48.00#ibcon#about to read 3, iclass 4, count 0 2006.285.21:03:48.04#ibcon#read 3, iclass 4, count 0 2006.285.21:03:48.04#ibcon#about to read 4, iclass 4, count 0 2006.285.21:03:48.04#ibcon#read 4, iclass 4, count 0 2006.285.21:03:48.04#ibcon#about to read 5, iclass 4, count 0 2006.285.21:03:48.04#ibcon#read 5, iclass 4, count 0 2006.285.21:03:48.04#ibcon#about to read 6, iclass 4, count 0 2006.285.21:03:48.04#ibcon#read 6, iclass 4, count 0 2006.285.21:03:48.04#ibcon#end of sib2, iclass 4, count 0 2006.285.21:03:48.04#ibcon#*after write, iclass 4, count 0 2006.285.21:03:48.04#ibcon#*before return 0, iclass 4, count 0 2006.285.21:03:48.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:03:48.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:03:48.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:03:48.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:03:48.04$vck44/vb=4,5 2006.285.21:03:48.14#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.21:03:48.14#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.21:03:48.14#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:48.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:03:48.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:03:48.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:03:48.14#ibcon#enter wrdev, iclass 6, count 2 2006.285.21:03:48.14#ibcon#first serial, iclass 6, count 2 2006.285.21:03:48.14#ibcon#enter sib2, iclass 6, count 2 2006.285.21:03:48.14#ibcon#flushed, iclass 6, count 2 2006.285.21:03:48.14#ibcon#about to write, iclass 6, count 2 2006.285.21:03:48.14#ibcon#wrote, iclass 6, count 2 2006.285.21:03:48.14#ibcon#about to read 3, iclass 6, count 2 2006.285.21:03:48.16#ibcon#read 3, iclass 6, count 2 2006.285.21:03:48.16#ibcon#about to read 4, iclass 6, count 2 2006.285.21:03:48.16#ibcon#read 4, iclass 6, count 2 2006.285.21:03:48.16#ibcon#about to read 5, iclass 6, count 2 2006.285.21:03:48.16#ibcon#read 5, iclass 6, count 2 2006.285.21:03:48.16#ibcon#about to read 6, iclass 6, count 2 2006.285.21:03:48.16#ibcon#read 6, iclass 6, count 2 2006.285.21:03:48.16#ibcon#end of sib2, iclass 6, count 2 2006.285.21:03:48.16#ibcon#*mode == 0, iclass 6, count 2 2006.285.21:03:48.16#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.21:03:48.16#ibcon#[27=AT04-05\r\n] 2006.285.21:03:48.16#ibcon#*before write, iclass 6, count 2 2006.285.21:03:48.16#ibcon#enter sib2, iclass 6, count 2 2006.285.21:03:48.16#ibcon#flushed, iclass 6, count 2 2006.285.21:03:48.16#ibcon#about to write, iclass 6, count 2 2006.285.21:03:48.16#ibcon#wrote, iclass 6, count 2 2006.285.21:03:48.16#ibcon#about to read 3, iclass 6, count 2 2006.285.21:03:48.19#ibcon#read 3, iclass 6, count 2 2006.285.21:03:48.19#ibcon#about to read 4, iclass 6, count 2 2006.285.21:03:48.19#ibcon#read 4, iclass 6, count 2 2006.285.21:03:48.19#ibcon#about to read 5, iclass 6, count 2 2006.285.21:03:48.19#ibcon#read 5, iclass 6, count 2 2006.285.21:03:48.19#ibcon#about to read 6, iclass 6, count 2 2006.285.21:03:48.19#ibcon#read 6, iclass 6, count 2 2006.285.21:03:48.19#ibcon#end of sib2, iclass 6, count 2 2006.285.21:03:48.19#ibcon#*after write, iclass 6, count 2 2006.285.21:03:48.19#ibcon#*before return 0, iclass 6, count 2 2006.285.21:03:48.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:03:48.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:03:48.19#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.21:03:48.19#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:48.19#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:03:48.31#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:03:48.31#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:03:48.31#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:03:48.31#ibcon#first serial, iclass 6, count 0 2006.285.21:03:48.31#ibcon#enter sib2, iclass 6, count 0 2006.285.21:03:48.31#ibcon#flushed, iclass 6, count 0 2006.285.21:03:48.31#ibcon#about to write, iclass 6, count 0 2006.285.21:03:48.31#ibcon#wrote, iclass 6, count 0 2006.285.21:03:48.31#ibcon#about to read 3, iclass 6, count 0 2006.285.21:03:48.33#ibcon#read 3, iclass 6, count 0 2006.285.21:03:48.33#ibcon#about to read 4, iclass 6, count 0 2006.285.21:03:48.33#ibcon#read 4, iclass 6, count 0 2006.285.21:03:48.33#ibcon#about to read 5, iclass 6, count 0 2006.285.21:03:48.33#ibcon#read 5, iclass 6, count 0 2006.285.21:03:48.33#ibcon#about to read 6, iclass 6, count 0 2006.285.21:03:48.33#ibcon#read 6, iclass 6, count 0 2006.285.21:03:48.33#ibcon#end of sib2, iclass 6, count 0 2006.285.21:03:48.33#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:03:48.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:03:48.33#ibcon#[27=USB\r\n] 2006.285.21:03:48.33#ibcon#*before write, iclass 6, count 0 2006.285.21:03:48.33#ibcon#enter sib2, iclass 6, count 0 2006.285.21:03:48.33#ibcon#flushed, iclass 6, count 0 2006.285.21:03:48.33#ibcon#about to write, iclass 6, count 0 2006.285.21:03:48.33#ibcon#wrote, iclass 6, count 0 2006.285.21:03:48.33#ibcon#about to read 3, iclass 6, count 0 2006.285.21:03:48.36#ibcon#read 3, iclass 6, count 0 2006.285.21:03:48.36#ibcon#about to read 4, iclass 6, count 0 2006.285.21:03:48.36#ibcon#read 4, iclass 6, count 0 2006.285.21:03:48.36#ibcon#about to read 5, iclass 6, count 0 2006.285.21:03:48.36#ibcon#read 5, iclass 6, count 0 2006.285.21:03:48.36#ibcon#about to read 6, iclass 6, count 0 2006.285.21:03:48.36#ibcon#read 6, iclass 6, count 0 2006.285.21:03:48.36#ibcon#end of sib2, iclass 6, count 0 2006.285.21:03:48.36#ibcon#*after write, iclass 6, count 0 2006.285.21:03:48.36#ibcon#*before return 0, iclass 6, count 0 2006.285.21:03:48.36#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:03:48.36#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:03:48.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:03:48.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:03:48.36$vck44/vblo=5,709.99 2006.285.21:03:48.36#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.21:03:48.36#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.21:03:48.36#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:48.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:03:48.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:03:48.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:03:48.36#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:03:48.36#ibcon#first serial, iclass 10, count 0 2006.285.21:03:48.36#ibcon#enter sib2, iclass 10, count 0 2006.285.21:03:48.36#ibcon#flushed, iclass 10, count 0 2006.285.21:03:48.36#ibcon#about to write, iclass 10, count 0 2006.285.21:03:48.36#ibcon#wrote, iclass 10, count 0 2006.285.21:03:48.36#ibcon#about to read 3, iclass 10, count 0 2006.285.21:03:48.38#ibcon#read 3, iclass 10, count 0 2006.285.21:03:48.38#ibcon#about to read 4, iclass 10, count 0 2006.285.21:03:48.38#ibcon#read 4, iclass 10, count 0 2006.285.21:03:48.38#ibcon#about to read 5, iclass 10, count 0 2006.285.21:03:48.38#ibcon#read 5, iclass 10, count 0 2006.285.21:03:48.38#ibcon#about to read 6, iclass 10, count 0 2006.285.21:03:48.38#ibcon#read 6, iclass 10, count 0 2006.285.21:03:48.38#ibcon#end of sib2, iclass 10, count 0 2006.285.21:03:48.38#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:03:48.38#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:03:48.38#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:03:48.38#ibcon#*before write, iclass 10, count 0 2006.285.21:03:48.38#ibcon#enter sib2, iclass 10, count 0 2006.285.21:03:48.38#ibcon#flushed, iclass 10, count 0 2006.285.21:03:48.38#ibcon#about to write, iclass 10, count 0 2006.285.21:03:48.38#ibcon#wrote, iclass 10, count 0 2006.285.21:03:48.38#ibcon#about to read 3, iclass 10, count 0 2006.285.21:03:48.42#ibcon#read 3, iclass 10, count 0 2006.285.21:03:48.42#ibcon#about to read 4, iclass 10, count 0 2006.285.21:03:48.42#ibcon#read 4, iclass 10, count 0 2006.285.21:03:48.42#ibcon#about to read 5, iclass 10, count 0 2006.285.21:03:48.42#ibcon#read 5, iclass 10, count 0 2006.285.21:03:48.42#ibcon#about to read 6, iclass 10, count 0 2006.285.21:03:48.42#ibcon#read 6, iclass 10, count 0 2006.285.21:03:48.42#ibcon#end of sib2, iclass 10, count 0 2006.285.21:03:48.42#ibcon#*after write, iclass 10, count 0 2006.285.21:03:48.42#ibcon#*before return 0, iclass 10, count 0 2006.285.21:03:48.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:03:48.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:03:48.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:03:48.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:03:48.42$vck44/vb=5,4 2006.285.21:03:48.42#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.21:03:48.42#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.21:03:48.42#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:48.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:03:48.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:03:48.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:03:48.48#ibcon#enter wrdev, iclass 12, count 2 2006.285.21:03:48.48#ibcon#first serial, iclass 12, count 2 2006.285.21:03:48.48#ibcon#enter sib2, iclass 12, count 2 2006.285.21:03:48.48#ibcon#flushed, iclass 12, count 2 2006.285.21:03:48.48#ibcon#about to write, iclass 12, count 2 2006.285.21:03:48.48#ibcon#wrote, iclass 12, count 2 2006.285.21:03:48.48#ibcon#about to read 3, iclass 12, count 2 2006.285.21:03:48.50#ibcon#read 3, iclass 12, count 2 2006.285.21:03:48.50#ibcon#about to read 4, iclass 12, count 2 2006.285.21:03:48.50#ibcon#read 4, iclass 12, count 2 2006.285.21:03:48.50#ibcon#about to read 5, iclass 12, count 2 2006.285.21:03:48.50#ibcon#read 5, iclass 12, count 2 2006.285.21:03:48.50#ibcon#about to read 6, iclass 12, count 2 2006.285.21:03:48.50#ibcon#read 6, iclass 12, count 2 2006.285.21:03:48.50#ibcon#end of sib2, iclass 12, count 2 2006.285.21:03:48.50#ibcon#*mode == 0, iclass 12, count 2 2006.285.21:03:48.50#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.21:03:48.50#ibcon#[27=AT05-04\r\n] 2006.285.21:03:48.50#ibcon#*before write, iclass 12, count 2 2006.285.21:03:48.50#ibcon#enter sib2, iclass 12, count 2 2006.285.21:03:48.50#ibcon#flushed, iclass 12, count 2 2006.285.21:03:48.50#ibcon#about to write, iclass 12, count 2 2006.285.21:03:48.50#ibcon#wrote, iclass 12, count 2 2006.285.21:03:48.50#ibcon#about to read 3, iclass 12, count 2 2006.285.21:03:48.53#ibcon#read 3, iclass 12, count 2 2006.285.21:03:48.53#ibcon#about to read 4, iclass 12, count 2 2006.285.21:03:48.53#ibcon#read 4, iclass 12, count 2 2006.285.21:03:48.53#ibcon#about to read 5, iclass 12, count 2 2006.285.21:03:48.53#ibcon#read 5, iclass 12, count 2 2006.285.21:03:48.53#ibcon#about to read 6, iclass 12, count 2 2006.285.21:03:48.53#ibcon#read 6, iclass 12, count 2 2006.285.21:03:48.53#ibcon#end of sib2, iclass 12, count 2 2006.285.21:03:48.53#ibcon#*after write, iclass 12, count 2 2006.285.21:03:48.53#ibcon#*before return 0, iclass 12, count 2 2006.285.21:03:48.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:03:48.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:03:48.53#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.21:03:48.53#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:48.53#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:03:48.65#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:03:48.65#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:03:48.65#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:03:48.65#ibcon#first serial, iclass 12, count 0 2006.285.21:03:48.65#ibcon#enter sib2, iclass 12, count 0 2006.285.21:03:48.65#ibcon#flushed, iclass 12, count 0 2006.285.21:03:48.65#ibcon#about to write, iclass 12, count 0 2006.285.21:03:48.65#ibcon#wrote, iclass 12, count 0 2006.285.21:03:48.65#ibcon#about to read 3, iclass 12, count 0 2006.285.21:03:48.67#ibcon#read 3, iclass 12, count 0 2006.285.21:03:48.67#ibcon#about to read 4, iclass 12, count 0 2006.285.21:03:48.67#ibcon#read 4, iclass 12, count 0 2006.285.21:03:48.67#ibcon#about to read 5, iclass 12, count 0 2006.285.21:03:48.67#ibcon#read 5, iclass 12, count 0 2006.285.21:03:48.67#ibcon#about to read 6, iclass 12, count 0 2006.285.21:03:48.67#ibcon#read 6, iclass 12, count 0 2006.285.21:03:48.67#ibcon#end of sib2, iclass 12, count 0 2006.285.21:03:48.67#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:03:48.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:03:48.67#ibcon#[27=USB\r\n] 2006.285.21:03:48.67#ibcon#*before write, iclass 12, count 0 2006.285.21:03:48.67#ibcon#enter sib2, iclass 12, count 0 2006.285.21:03:48.67#ibcon#flushed, iclass 12, count 0 2006.285.21:03:48.67#ibcon#about to write, iclass 12, count 0 2006.285.21:03:48.67#ibcon#wrote, iclass 12, count 0 2006.285.21:03:48.67#ibcon#about to read 3, iclass 12, count 0 2006.285.21:03:48.70#ibcon#read 3, iclass 12, count 0 2006.285.21:03:48.70#ibcon#about to read 4, iclass 12, count 0 2006.285.21:03:48.70#ibcon#read 4, iclass 12, count 0 2006.285.21:03:48.70#ibcon#about to read 5, iclass 12, count 0 2006.285.21:03:48.70#ibcon#read 5, iclass 12, count 0 2006.285.21:03:48.70#ibcon#about to read 6, iclass 12, count 0 2006.285.21:03:48.70#ibcon#read 6, iclass 12, count 0 2006.285.21:03:48.70#ibcon#end of sib2, iclass 12, count 0 2006.285.21:03:48.70#ibcon#*after write, iclass 12, count 0 2006.285.21:03:48.70#ibcon#*before return 0, iclass 12, count 0 2006.285.21:03:48.70#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:03:48.70#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:03:48.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:03:48.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:03:48.70$vck44/vblo=6,719.99 2006.285.21:03:48.70#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.21:03:48.70#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.21:03:48.70#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:48.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:03:48.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:03:48.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:03:48.70#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:03:48.70#ibcon#first serial, iclass 14, count 0 2006.285.21:03:48.70#ibcon#enter sib2, iclass 14, count 0 2006.285.21:03:48.70#ibcon#flushed, iclass 14, count 0 2006.285.21:03:48.70#ibcon#about to write, iclass 14, count 0 2006.285.21:03:48.70#ibcon#wrote, iclass 14, count 0 2006.285.21:03:48.70#ibcon#about to read 3, iclass 14, count 0 2006.285.21:03:48.72#ibcon#read 3, iclass 14, count 0 2006.285.21:03:48.72#ibcon#about to read 4, iclass 14, count 0 2006.285.21:03:48.72#ibcon#read 4, iclass 14, count 0 2006.285.21:03:48.72#ibcon#about to read 5, iclass 14, count 0 2006.285.21:03:48.72#ibcon#read 5, iclass 14, count 0 2006.285.21:03:48.72#ibcon#about to read 6, iclass 14, count 0 2006.285.21:03:48.72#ibcon#read 6, iclass 14, count 0 2006.285.21:03:48.72#ibcon#end of sib2, iclass 14, count 0 2006.285.21:03:48.72#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:03:48.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:03:48.72#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:03:48.72#ibcon#*before write, iclass 14, count 0 2006.285.21:03:48.72#ibcon#enter sib2, iclass 14, count 0 2006.285.21:03:48.72#ibcon#flushed, iclass 14, count 0 2006.285.21:03:48.72#ibcon#about to write, iclass 14, count 0 2006.285.21:03:48.72#ibcon#wrote, iclass 14, count 0 2006.285.21:03:48.72#ibcon#about to read 3, iclass 14, count 0 2006.285.21:03:48.76#ibcon#read 3, iclass 14, count 0 2006.285.21:03:48.76#ibcon#about to read 4, iclass 14, count 0 2006.285.21:03:48.76#ibcon#read 4, iclass 14, count 0 2006.285.21:03:48.76#ibcon#about to read 5, iclass 14, count 0 2006.285.21:03:48.76#ibcon#read 5, iclass 14, count 0 2006.285.21:03:48.76#ibcon#about to read 6, iclass 14, count 0 2006.285.21:03:48.76#ibcon#read 6, iclass 14, count 0 2006.285.21:03:48.76#ibcon#end of sib2, iclass 14, count 0 2006.285.21:03:48.76#ibcon#*after write, iclass 14, count 0 2006.285.21:03:48.76#ibcon#*before return 0, iclass 14, count 0 2006.285.21:03:48.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:03:48.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:03:48.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:03:48.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:03:48.76$vck44/vb=6,3 2006.285.21:03:48.76#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.21:03:48.76#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.21:03:48.76#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:48.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:03:48.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:03:48.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:03:48.82#ibcon#enter wrdev, iclass 16, count 2 2006.285.21:03:48.82#ibcon#first serial, iclass 16, count 2 2006.285.21:03:48.82#ibcon#enter sib2, iclass 16, count 2 2006.285.21:03:48.82#ibcon#flushed, iclass 16, count 2 2006.285.21:03:48.82#ibcon#about to write, iclass 16, count 2 2006.285.21:03:48.82#ibcon#wrote, iclass 16, count 2 2006.285.21:03:48.82#ibcon#about to read 3, iclass 16, count 2 2006.285.21:03:48.84#ibcon#read 3, iclass 16, count 2 2006.285.21:03:48.84#ibcon#about to read 4, iclass 16, count 2 2006.285.21:03:48.84#ibcon#read 4, iclass 16, count 2 2006.285.21:03:48.84#ibcon#about to read 5, iclass 16, count 2 2006.285.21:03:48.84#ibcon#read 5, iclass 16, count 2 2006.285.21:03:48.84#ibcon#about to read 6, iclass 16, count 2 2006.285.21:03:48.84#ibcon#read 6, iclass 16, count 2 2006.285.21:03:48.84#ibcon#end of sib2, iclass 16, count 2 2006.285.21:03:48.84#ibcon#*mode == 0, iclass 16, count 2 2006.285.21:03:48.84#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.21:03:48.84#ibcon#[27=AT06-03\r\n] 2006.285.21:03:48.84#ibcon#*before write, iclass 16, count 2 2006.285.21:03:48.84#ibcon#enter sib2, iclass 16, count 2 2006.285.21:03:48.84#ibcon#flushed, iclass 16, count 2 2006.285.21:03:48.84#ibcon#about to write, iclass 16, count 2 2006.285.21:03:48.84#ibcon#wrote, iclass 16, count 2 2006.285.21:03:48.84#ibcon#about to read 3, iclass 16, count 2 2006.285.21:03:48.87#ibcon#read 3, iclass 16, count 2 2006.285.21:03:48.87#ibcon#about to read 4, iclass 16, count 2 2006.285.21:03:48.87#ibcon#read 4, iclass 16, count 2 2006.285.21:03:48.87#ibcon#about to read 5, iclass 16, count 2 2006.285.21:03:48.87#ibcon#read 5, iclass 16, count 2 2006.285.21:03:48.87#ibcon#about to read 6, iclass 16, count 2 2006.285.21:03:48.87#ibcon#read 6, iclass 16, count 2 2006.285.21:03:48.87#ibcon#end of sib2, iclass 16, count 2 2006.285.21:03:48.87#ibcon#*after write, iclass 16, count 2 2006.285.21:03:48.87#ibcon#*before return 0, iclass 16, count 2 2006.285.21:03:48.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:03:48.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:03:48.87#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.21:03:48.87#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:48.87#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:03:48.99#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:03:48.99#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:03:48.99#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:03:48.99#ibcon#first serial, iclass 16, count 0 2006.285.21:03:48.99#ibcon#enter sib2, iclass 16, count 0 2006.285.21:03:48.99#ibcon#flushed, iclass 16, count 0 2006.285.21:03:48.99#ibcon#about to write, iclass 16, count 0 2006.285.21:03:48.99#ibcon#wrote, iclass 16, count 0 2006.285.21:03:48.99#ibcon#about to read 3, iclass 16, count 0 2006.285.21:03:49.01#ibcon#read 3, iclass 16, count 0 2006.285.21:03:49.01#ibcon#about to read 4, iclass 16, count 0 2006.285.21:03:49.01#ibcon#read 4, iclass 16, count 0 2006.285.21:03:49.01#ibcon#about to read 5, iclass 16, count 0 2006.285.21:03:49.01#ibcon#read 5, iclass 16, count 0 2006.285.21:03:49.01#ibcon#about to read 6, iclass 16, count 0 2006.285.21:03:49.01#ibcon#read 6, iclass 16, count 0 2006.285.21:03:49.01#ibcon#end of sib2, iclass 16, count 0 2006.285.21:03:49.01#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:03:49.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:03:49.01#ibcon#[27=USB\r\n] 2006.285.21:03:49.01#ibcon#*before write, iclass 16, count 0 2006.285.21:03:49.01#ibcon#enter sib2, iclass 16, count 0 2006.285.21:03:49.01#ibcon#flushed, iclass 16, count 0 2006.285.21:03:49.01#ibcon#about to write, iclass 16, count 0 2006.285.21:03:49.01#ibcon#wrote, iclass 16, count 0 2006.285.21:03:49.01#ibcon#about to read 3, iclass 16, count 0 2006.285.21:03:49.04#ibcon#read 3, iclass 16, count 0 2006.285.21:03:49.04#ibcon#about to read 4, iclass 16, count 0 2006.285.21:03:49.04#ibcon#read 4, iclass 16, count 0 2006.285.21:03:49.04#ibcon#about to read 5, iclass 16, count 0 2006.285.21:03:49.04#ibcon#read 5, iclass 16, count 0 2006.285.21:03:49.04#ibcon#about to read 6, iclass 16, count 0 2006.285.21:03:49.04#ibcon#read 6, iclass 16, count 0 2006.285.21:03:49.04#ibcon#end of sib2, iclass 16, count 0 2006.285.21:03:49.04#ibcon#*after write, iclass 16, count 0 2006.285.21:03:49.04#ibcon#*before return 0, iclass 16, count 0 2006.285.21:03:49.04#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:03:49.04#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:03:49.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:03:49.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:03:49.04$vck44/vblo=7,734.99 2006.285.21:03:49.04#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.21:03:49.04#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.21:03:49.04#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:49.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:03:49.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:03:49.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:03:49.04#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:03:49.04#ibcon#first serial, iclass 18, count 0 2006.285.21:03:49.04#ibcon#enter sib2, iclass 18, count 0 2006.285.21:03:49.04#ibcon#flushed, iclass 18, count 0 2006.285.21:03:49.04#ibcon#about to write, iclass 18, count 0 2006.285.21:03:49.04#ibcon#wrote, iclass 18, count 0 2006.285.21:03:49.04#ibcon#about to read 3, iclass 18, count 0 2006.285.21:03:49.06#ibcon#read 3, iclass 18, count 0 2006.285.21:03:49.36#ibcon#about to read 4, iclass 18, count 0 2006.285.21:03:49.36#ibcon#read 4, iclass 18, count 0 2006.285.21:03:49.36#ibcon#about to read 5, iclass 18, count 0 2006.285.21:03:49.36#ibcon#read 5, iclass 18, count 0 2006.285.21:03:49.36#ibcon#about to read 6, iclass 18, count 0 2006.285.21:03:49.36#ibcon#read 6, iclass 18, count 0 2006.285.21:03:49.36#ibcon#end of sib2, iclass 18, count 0 2006.285.21:03:49.36#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:03:49.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:03:49.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:03:49.36#ibcon#*before write, iclass 18, count 0 2006.285.21:03:49.36#ibcon#enter sib2, iclass 18, count 0 2006.285.21:03:49.36#ibcon#flushed, iclass 18, count 0 2006.285.21:03:49.36#ibcon#about to write, iclass 18, count 0 2006.285.21:03:49.36#ibcon#wrote, iclass 18, count 0 2006.285.21:03:49.36#ibcon#about to read 3, iclass 18, count 0 2006.285.21:03:49.40#ibcon#read 3, iclass 18, count 0 2006.285.21:03:49.40#ibcon#about to read 4, iclass 18, count 0 2006.285.21:03:49.40#ibcon#read 4, iclass 18, count 0 2006.285.21:03:49.40#ibcon#about to read 5, iclass 18, count 0 2006.285.21:03:49.40#ibcon#read 5, iclass 18, count 0 2006.285.21:03:49.40#ibcon#about to read 6, iclass 18, count 0 2006.285.21:03:49.40#ibcon#read 6, iclass 18, count 0 2006.285.21:03:49.40#ibcon#end of sib2, iclass 18, count 0 2006.285.21:03:49.40#ibcon#*after write, iclass 18, count 0 2006.285.21:03:49.40#ibcon#*before return 0, iclass 18, count 0 2006.285.21:03:49.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:03:49.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:03:49.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:03:49.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:03:49.40$vck44/vb=7,4 2006.285.21:03:49.40#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.21:03:49.40#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.21:03:49.40#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:49.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:03:49.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:03:49.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:03:49.40#ibcon#enter wrdev, iclass 20, count 2 2006.285.21:03:49.40#ibcon#first serial, iclass 20, count 2 2006.285.21:03:49.40#ibcon#enter sib2, iclass 20, count 2 2006.285.21:03:49.40#ibcon#flushed, iclass 20, count 2 2006.285.21:03:49.40#ibcon#about to write, iclass 20, count 2 2006.285.21:03:49.40#ibcon#wrote, iclass 20, count 2 2006.285.21:03:49.40#ibcon#about to read 3, iclass 20, count 2 2006.285.21:03:49.42#ibcon#read 3, iclass 20, count 2 2006.285.21:03:49.42#ibcon#about to read 4, iclass 20, count 2 2006.285.21:03:49.42#ibcon#read 4, iclass 20, count 2 2006.285.21:03:49.42#ibcon#about to read 5, iclass 20, count 2 2006.285.21:03:49.42#ibcon#read 5, iclass 20, count 2 2006.285.21:03:49.42#ibcon#about to read 6, iclass 20, count 2 2006.285.21:03:49.42#ibcon#read 6, iclass 20, count 2 2006.285.21:03:49.42#ibcon#end of sib2, iclass 20, count 2 2006.285.21:03:49.42#ibcon#*mode == 0, iclass 20, count 2 2006.285.21:03:49.42#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.21:03:49.42#ibcon#[27=AT07-04\r\n] 2006.285.21:03:49.42#ibcon#*before write, iclass 20, count 2 2006.285.21:03:49.42#ibcon#enter sib2, iclass 20, count 2 2006.285.21:03:49.42#ibcon#flushed, iclass 20, count 2 2006.285.21:03:49.42#ibcon#about to write, iclass 20, count 2 2006.285.21:03:49.42#ibcon#wrote, iclass 20, count 2 2006.285.21:03:49.42#ibcon#about to read 3, iclass 20, count 2 2006.285.21:03:49.45#ibcon#read 3, iclass 20, count 2 2006.285.21:03:49.45#ibcon#about to read 4, iclass 20, count 2 2006.285.21:03:49.45#ibcon#read 4, iclass 20, count 2 2006.285.21:03:49.45#ibcon#about to read 5, iclass 20, count 2 2006.285.21:03:49.45#ibcon#read 5, iclass 20, count 2 2006.285.21:03:49.45#ibcon#about to read 6, iclass 20, count 2 2006.285.21:03:49.45#ibcon#read 6, iclass 20, count 2 2006.285.21:03:49.45#ibcon#end of sib2, iclass 20, count 2 2006.285.21:03:49.45#ibcon#*after write, iclass 20, count 2 2006.285.21:03:49.45#ibcon#*before return 0, iclass 20, count 2 2006.285.21:03:49.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:03:49.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:03:49.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.21:03:49.45#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:49.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:03:49.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:03:49.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:03:49.57#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:03:49.57#ibcon#first serial, iclass 20, count 0 2006.285.21:03:49.57#ibcon#enter sib2, iclass 20, count 0 2006.285.21:03:49.57#ibcon#flushed, iclass 20, count 0 2006.285.21:03:49.57#ibcon#about to write, iclass 20, count 0 2006.285.21:03:49.57#ibcon#wrote, iclass 20, count 0 2006.285.21:03:49.57#ibcon#about to read 3, iclass 20, count 0 2006.285.21:03:49.59#ibcon#read 3, iclass 20, count 0 2006.285.21:03:49.59#ibcon#about to read 4, iclass 20, count 0 2006.285.21:03:49.59#ibcon#read 4, iclass 20, count 0 2006.285.21:03:49.59#ibcon#about to read 5, iclass 20, count 0 2006.285.21:03:49.59#ibcon#read 5, iclass 20, count 0 2006.285.21:03:49.59#ibcon#about to read 6, iclass 20, count 0 2006.285.21:03:49.59#ibcon#read 6, iclass 20, count 0 2006.285.21:03:49.59#ibcon#end of sib2, iclass 20, count 0 2006.285.21:03:49.59#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:03:49.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:03:49.59#ibcon#[27=USB\r\n] 2006.285.21:03:49.59#ibcon#*before write, iclass 20, count 0 2006.285.21:03:49.59#ibcon#enter sib2, iclass 20, count 0 2006.285.21:03:49.59#ibcon#flushed, iclass 20, count 0 2006.285.21:03:49.59#ibcon#about to write, iclass 20, count 0 2006.285.21:03:49.59#ibcon#wrote, iclass 20, count 0 2006.285.21:03:49.59#ibcon#about to read 3, iclass 20, count 0 2006.285.21:03:49.62#ibcon#read 3, iclass 20, count 0 2006.285.21:03:49.62#ibcon#about to read 4, iclass 20, count 0 2006.285.21:03:49.62#ibcon#read 4, iclass 20, count 0 2006.285.21:03:49.62#ibcon#about to read 5, iclass 20, count 0 2006.285.21:03:49.62#ibcon#read 5, iclass 20, count 0 2006.285.21:03:49.62#ibcon#about to read 6, iclass 20, count 0 2006.285.21:03:49.62#ibcon#read 6, iclass 20, count 0 2006.285.21:03:49.62#ibcon#end of sib2, iclass 20, count 0 2006.285.21:03:49.62#ibcon#*after write, iclass 20, count 0 2006.285.21:03:49.62#ibcon#*before return 0, iclass 20, count 0 2006.285.21:03:49.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:03:49.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:03:49.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:03:49.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:03:49.62$vck44/vblo=8,744.99 2006.285.21:03:49.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.21:03:49.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.21:03:49.62#ibcon#ireg 17 cls_cnt 0 2006.285.21:03:49.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:03:49.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:03:49.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:03:49.62#ibcon#enter wrdev, iclass 22, count 0 2006.285.21:03:49.62#ibcon#first serial, iclass 22, count 0 2006.285.21:03:49.62#ibcon#enter sib2, iclass 22, count 0 2006.285.21:03:49.62#ibcon#flushed, iclass 22, count 0 2006.285.21:03:49.62#ibcon#about to write, iclass 22, count 0 2006.285.21:03:49.62#ibcon#wrote, iclass 22, count 0 2006.285.21:03:49.62#ibcon#about to read 3, iclass 22, count 0 2006.285.21:03:49.64#ibcon#read 3, iclass 22, count 0 2006.285.21:03:49.64#ibcon#about to read 4, iclass 22, count 0 2006.285.21:03:49.64#ibcon#read 4, iclass 22, count 0 2006.285.21:03:49.64#ibcon#about to read 5, iclass 22, count 0 2006.285.21:03:49.64#ibcon#read 5, iclass 22, count 0 2006.285.21:03:49.64#ibcon#about to read 6, iclass 22, count 0 2006.285.21:03:49.64#ibcon#read 6, iclass 22, count 0 2006.285.21:03:49.64#ibcon#end of sib2, iclass 22, count 0 2006.285.21:03:49.64#ibcon#*mode == 0, iclass 22, count 0 2006.285.21:03:49.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.21:03:49.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:03:49.64#ibcon#*before write, iclass 22, count 0 2006.285.21:03:49.64#ibcon#enter sib2, iclass 22, count 0 2006.285.21:03:49.64#ibcon#flushed, iclass 22, count 0 2006.285.21:03:49.64#ibcon#about to write, iclass 22, count 0 2006.285.21:03:49.64#ibcon#wrote, iclass 22, count 0 2006.285.21:03:49.64#ibcon#about to read 3, iclass 22, count 0 2006.285.21:03:49.68#ibcon#read 3, iclass 22, count 0 2006.285.21:03:49.68#ibcon#about to read 4, iclass 22, count 0 2006.285.21:03:49.68#ibcon#read 4, iclass 22, count 0 2006.285.21:03:49.68#ibcon#about to read 5, iclass 22, count 0 2006.285.21:03:49.68#ibcon#read 5, iclass 22, count 0 2006.285.21:03:49.68#ibcon#about to read 6, iclass 22, count 0 2006.285.21:03:49.68#ibcon#read 6, iclass 22, count 0 2006.285.21:03:49.68#ibcon#end of sib2, iclass 22, count 0 2006.285.21:03:49.68#ibcon#*after write, iclass 22, count 0 2006.285.21:03:49.68#ibcon#*before return 0, iclass 22, count 0 2006.285.21:03:49.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:03:49.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:03:49.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.21:03:49.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.21:03:49.68$vck44/vb=8,4 2006.285.21:03:49.68#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.21:03:49.68#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.21:03:49.68#ibcon#ireg 11 cls_cnt 2 2006.285.21:03:49.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:03:49.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:03:49.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:03:49.74#ibcon#enter wrdev, iclass 24, count 2 2006.285.21:03:49.74#ibcon#first serial, iclass 24, count 2 2006.285.21:03:49.74#ibcon#enter sib2, iclass 24, count 2 2006.285.21:03:49.74#ibcon#flushed, iclass 24, count 2 2006.285.21:03:49.74#ibcon#about to write, iclass 24, count 2 2006.285.21:03:49.74#ibcon#wrote, iclass 24, count 2 2006.285.21:03:49.74#ibcon#about to read 3, iclass 24, count 2 2006.285.21:03:49.76#ibcon#read 3, iclass 24, count 2 2006.285.21:03:49.76#ibcon#about to read 4, iclass 24, count 2 2006.285.21:03:49.76#ibcon#read 4, iclass 24, count 2 2006.285.21:03:49.76#ibcon#about to read 5, iclass 24, count 2 2006.285.21:03:49.76#ibcon#read 5, iclass 24, count 2 2006.285.21:03:49.76#ibcon#about to read 6, iclass 24, count 2 2006.285.21:03:49.76#ibcon#read 6, iclass 24, count 2 2006.285.21:03:49.76#ibcon#end of sib2, iclass 24, count 2 2006.285.21:03:49.76#ibcon#*mode == 0, iclass 24, count 2 2006.285.21:03:49.76#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.21:03:49.76#ibcon#[27=AT08-04\r\n] 2006.285.21:03:49.76#ibcon#*before write, iclass 24, count 2 2006.285.21:03:49.76#ibcon#enter sib2, iclass 24, count 2 2006.285.21:03:49.76#ibcon#flushed, iclass 24, count 2 2006.285.21:03:49.76#ibcon#about to write, iclass 24, count 2 2006.285.21:03:49.76#ibcon#wrote, iclass 24, count 2 2006.285.21:03:49.76#ibcon#about to read 3, iclass 24, count 2 2006.285.21:03:49.79#ibcon#read 3, iclass 24, count 2 2006.285.21:03:49.79#ibcon#about to read 4, iclass 24, count 2 2006.285.21:03:49.79#ibcon#read 4, iclass 24, count 2 2006.285.21:03:49.79#ibcon#about to read 5, iclass 24, count 2 2006.285.21:03:49.79#ibcon#read 5, iclass 24, count 2 2006.285.21:03:49.79#ibcon#about to read 6, iclass 24, count 2 2006.285.21:03:49.79#ibcon#read 6, iclass 24, count 2 2006.285.21:03:49.79#ibcon#end of sib2, iclass 24, count 2 2006.285.21:03:49.79#ibcon#*after write, iclass 24, count 2 2006.285.21:03:49.79#ibcon#*before return 0, iclass 24, count 2 2006.285.21:03:49.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:03:49.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:03:49.79#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.21:03:49.79#ibcon#ireg 7 cls_cnt 0 2006.285.21:03:49.79#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:03:49.91#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:03:49.91#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:03:49.91#ibcon#enter wrdev, iclass 24, count 0 2006.285.21:03:49.91#ibcon#first serial, iclass 24, count 0 2006.285.21:03:49.91#ibcon#enter sib2, iclass 24, count 0 2006.285.21:03:49.91#ibcon#flushed, iclass 24, count 0 2006.285.21:03:49.91#ibcon#about to write, iclass 24, count 0 2006.285.21:03:49.91#ibcon#wrote, iclass 24, count 0 2006.285.21:03:49.91#ibcon#about to read 3, iclass 24, count 0 2006.285.21:03:49.93#ibcon#read 3, iclass 24, count 0 2006.285.21:03:49.93#ibcon#about to read 4, iclass 24, count 0 2006.285.21:03:49.93#ibcon#read 4, iclass 24, count 0 2006.285.21:03:49.93#ibcon#about to read 5, iclass 24, count 0 2006.285.21:03:49.93#ibcon#read 5, iclass 24, count 0 2006.285.21:03:49.93#ibcon#about to read 6, iclass 24, count 0 2006.285.21:03:49.93#ibcon#read 6, iclass 24, count 0 2006.285.21:03:49.93#ibcon#end of sib2, iclass 24, count 0 2006.285.21:03:49.93#ibcon#*mode == 0, iclass 24, count 0 2006.285.21:03:49.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.21:03:49.93#ibcon#[27=USB\r\n] 2006.285.21:03:49.93#ibcon#*before write, iclass 24, count 0 2006.285.21:03:49.93#ibcon#enter sib2, iclass 24, count 0 2006.285.21:03:49.93#ibcon#flushed, iclass 24, count 0 2006.285.21:03:49.93#ibcon#about to write, iclass 24, count 0 2006.285.21:03:49.93#ibcon#wrote, iclass 24, count 0 2006.285.21:03:49.93#ibcon#about to read 3, iclass 24, count 0 2006.285.21:03:49.96#ibcon#read 3, iclass 24, count 0 2006.285.21:03:49.96#ibcon#about to read 4, iclass 24, count 0 2006.285.21:03:49.96#ibcon#read 4, iclass 24, count 0 2006.285.21:03:49.96#ibcon#about to read 5, iclass 24, count 0 2006.285.21:03:49.96#ibcon#read 5, iclass 24, count 0 2006.285.21:03:49.96#ibcon#about to read 6, iclass 24, count 0 2006.285.21:03:49.96#ibcon#read 6, iclass 24, count 0 2006.285.21:03:49.96#ibcon#end of sib2, iclass 24, count 0 2006.285.21:03:49.96#ibcon#*after write, iclass 24, count 0 2006.285.21:03:49.96#ibcon#*before return 0, iclass 24, count 0 2006.285.21:03:49.96#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:03:49.96#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:03:49.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.21:03:49.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.21:03:49.96$vck44/vabw=wide 2006.285.21:03:49.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.21:03:49.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.21:03:49.96#ibcon#ireg 8 cls_cnt 0 2006.285.21:03:49.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:03:49.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:03:49.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:03:49.96#ibcon#enter wrdev, iclass 26, count 0 2006.285.21:03:49.96#ibcon#first serial, iclass 26, count 0 2006.285.21:03:49.96#ibcon#enter sib2, iclass 26, count 0 2006.285.21:03:49.96#ibcon#flushed, iclass 26, count 0 2006.285.21:03:49.96#ibcon#about to write, iclass 26, count 0 2006.285.21:03:49.96#ibcon#wrote, iclass 26, count 0 2006.285.21:03:49.96#ibcon#about to read 3, iclass 26, count 0 2006.285.21:03:49.98#ibcon#read 3, iclass 26, count 0 2006.285.21:03:49.98#ibcon#about to read 4, iclass 26, count 0 2006.285.21:03:49.98#ibcon#read 4, iclass 26, count 0 2006.285.21:03:49.98#ibcon#about to read 5, iclass 26, count 0 2006.285.21:03:49.98#ibcon#read 5, iclass 26, count 0 2006.285.21:03:49.98#ibcon#about to read 6, iclass 26, count 0 2006.285.21:03:49.98#ibcon#read 6, iclass 26, count 0 2006.285.21:03:49.98#ibcon#end of sib2, iclass 26, count 0 2006.285.21:03:49.98#ibcon#*mode == 0, iclass 26, count 0 2006.285.21:03:49.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.21:03:49.98#ibcon#[25=BW32\r\n] 2006.285.21:03:49.98#ibcon#*before write, iclass 26, count 0 2006.285.21:03:49.98#ibcon#enter sib2, iclass 26, count 0 2006.285.21:03:49.98#ibcon#flushed, iclass 26, count 0 2006.285.21:03:49.98#ibcon#about to write, iclass 26, count 0 2006.285.21:03:49.98#ibcon#wrote, iclass 26, count 0 2006.285.21:03:49.98#ibcon#about to read 3, iclass 26, count 0 2006.285.21:03:50.01#ibcon#read 3, iclass 26, count 0 2006.285.21:03:50.01#ibcon#about to read 4, iclass 26, count 0 2006.285.21:03:50.01#ibcon#read 4, iclass 26, count 0 2006.285.21:03:50.01#ibcon#about to read 5, iclass 26, count 0 2006.285.21:03:50.01#ibcon#read 5, iclass 26, count 0 2006.285.21:03:50.01#ibcon#about to read 6, iclass 26, count 0 2006.285.21:03:50.01#ibcon#read 6, iclass 26, count 0 2006.285.21:03:50.01#ibcon#end of sib2, iclass 26, count 0 2006.285.21:03:50.01#ibcon#*after write, iclass 26, count 0 2006.285.21:03:50.01#ibcon#*before return 0, iclass 26, count 0 2006.285.21:03:50.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:03:50.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:03:50.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.21:03:50.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.21:03:50.01$vck44/vbbw=wide 2006.285.21:03:50.01#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.21:03:50.01#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.21:03:50.01#ibcon#ireg 8 cls_cnt 0 2006.285.21:03:50.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:03:50.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:03:50.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:03:50.08#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:03:50.08#ibcon#first serial, iclass 28, count 0 2006.285.21:03:50.08#ibcon#enter sib2, iclass 28, count 0 2006.285.21:03:50.08#ibcon#flushed, iclass 28, count 0 2006.285.21:03:50.08#ibcon#about to write, iclass 28, count 0 2006.285.21:03:50.08#ibcon#wrote, iclass 28, count 0 2006.285.21:03:50.08#ibcon#about to read 3, iclass 28, count 0 2006.285.21:03:50.10#ibcon#read 3, iclass 28, count 0 2006.285.21:03:50.10#ibcon#about to read 4, iclass 28, count 0 2006.285.21:03:50.10#ibcon#read 4, iclass 28, count 0 2006.285.21:03:50.10#ibcon#about to read 5, iclass 28, count 0 2006.285.21:03:50.10#ibcon#read 5, iclass 28, count 0 2006.285.21:03:50.10#ibcon#about to read 6, iclass 28, count 0 2006.285.21:03:50.10#ibcon#read 6, iclass 28, count 0 2006.285.21:03:50.10#ibcon#end of sib2, iclass 28, count 0 2006.285.21:03:50.10#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:03:50.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:03:50.10#ibcon#[27=BW32\r\n] 2006.285.21:03:50.10#ibcon#*before write, iclass 28, count 0 2006.285.21:03:50.10#ibcon#enter sib2, iclass 28, count 0 2006.285.21:03:50.10#ibcon#flushed, iclass 28, count 0 2006.285.21:03:50.10#ibcon#about to write, iclass 28, count 0 2006.285.21:03:50.10#ibcon#wrote, iclass 28, count 0 2006.285.21:03:50.10#ibcon#about to read 3, iclass 28, count 0 2006.285.21:03:50.13#ibcon#read 3, iclass 28, count 0 2006.285.21:03:50.13#ibcon#about to read 4, iclass 28, count 0 2006.285.21:03:50.13#ibcon#read 4, iclass 28, count 0 2006.285.21:03:50.13#ibcon#about to read 5, iclass 28, count 0 2006.285.21:03:50.13#ibcon#read 5, iclass 28, count 0 2006.285.21:03:50.13#ibcon#about to read 6, iclass 28, count 0 2006.285.21:03:50.13#ibcon#read 6, iclass 28, count 0 2006.285.21:03:50.13#ibcon#end of sib2, iclass 28, count 0 2006.285.21:03:50.13#ibcon#*after write, iclass 28, count 0 2006.285.21:03:50.13#ibcon#*before return 0, iclass 28, count 0 2006.285.21:03:50.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:03:50.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:03:50.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:03:50.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:03:50.13$setupk4/ifdk4 2006.285.21:03:50.21$ifdk4/lo= 2006.285.21:03:50.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:03:50.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:03:50.21$ifdk4/patch= 2006.285.21:03:50.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:03:50.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:03:50.22$setupk4/!*+20s 2006.285.21:03:52.14#trakl#Source acquired 2006.285.21:03:52.14#flagr#flagr/antenna,acquired 2006.285.21:03:56.73#abcon#<5=/00 0.1 0.5 14.191001015.5\r\n> 2006.285.21:03:56.75#abcon#{5=INTERFACE CLEAR} 2006.285.21:03:56.81#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:04:02.53$setupk4/"tpicd 2006.285.21:04:02.53$setupk4/echo=off 2006.285.21:04:02.53$setupk4/xlog=off 2006.285.21:04:02.53:!2006.285.21:04:08 2006.285.21:04:08.00:preob 2006.285.21:04:08.14/onsource/TRACKING 2006.285.21:04:08.14:!2006.285.21:04:18 2006.285.21:04:18.00:"tape 2006.285.21:04:18.00:"st=record 2006.285.21:04:18.00:data_valid=on 2006.285.21:04:18.00:midob 2006.285.21:04:19.14/onsource/TRACKING 2006.285.21:04:19.14/wx/14.18,1015.5,100 2006.285.21:04:19.23/cable/+6.5109E-03 2006.285.21:04:20.32/va/01,07,usb,yes,32,35 2006.285.21:04:20.32/va/02,06,usb,yes,32,33 2006.285.21:04:20.32/va/03,07,usb,yes,32,34 2006.285.21:04:20.32/va/04,06,usb,yes,34,35 2006.285.21:04:20.32/va/05,03,usb,yes,33,33 2006.285.21:04:20.32/va/06,04,usb,yes,30,29 2006.285.21:04:20.32/va/07,04,usb,yes,30,31 2006.285.21:04:20.32/va/08,03,usb,yes,31,38 2006.285.21:04:20.55/valo/01,524.99,yes,locked 2006.285.21:04:20.55/valo/02,534.99,yes,locked 2006.285.21:04:20.55/valo/03,564.99,yes,locked 2006.285.21:04:20.55/valo/04,624.99,yes,locked 2006.285.21:04:20.55/valo/05,734.99,yes,locked 2006.285.21:04:20.55/valo/06,814.99,yes,locked 2006.285.21:04:20.55/valo/07,864.99,yes,locked 2006.285.21:04:20.55/valo/08,884.99,yes,locked 2006.285.21:04:21.64/vb/01,04,usb,yes,29,28 2006.285.21:04:21.64/vb/02,05,usb,yes,28,28 2006.285.21:04:21.64/vb/03,04,usb,yes,29,32 2006.285.21:04:21.64/vb/04,05,usb,yes,29,28 2006.285.21:04:21.64/vb/05,04,usb,yes,26,28 2006.285.21:04:21.64/vb/06,03,usb,yes,37,33 2006.285.21:04:21.64/vb/07,04,usb,yes,30,30 2006.285.21:04:21.64/vb/08,04,usb,yes,27,30 2006.285.21:04:21.87/vblo/01,629.99,yes,locked 2006.285.21:04:21.87/vblo/02,634.99,yes,locked 2006.285.21:04:21.87/vblo/03,649.99,yes,locked 2006.285.21:04:21.87/vblo/04,679.99,yes,locked 2006.285.21:04:21.87/vblo/05,709.99,yes,locked 2006.285.21:04:21.87/vblo/06,719.99,yes,locked 2006.285.21:04:21.87/vblo/07,734.99,yes,locked 2006.285.21:04:21.87/vblo/08,744.99,yes,locked 2006.285.21:04:22.02/vabw/8 2006.285.21:04:22.17/vbbw/8 2006.285.21:04:22.26/xfe/off,on,12.0 2006.285.21:04:22.63/ifatt/23,28,28,28 2006.285.21:04:23.08/fmout-gps/S +2.84E-07 2006.285.21:04:23.10:!2006.285.21:07:38 2006.285.21:07:38.01:data_valid=off 2006.285.21:07:38.01:"et 2006.285.21:07:38.01:!+3s 2006.285.21:07:41.02:"tape 2006.285.21:07:41.02:postob 2006.285.21:07:41.14/cable/+6.5105E-03 2006.285.21:07:41.14/wx/14.22,1015.5,100 2006.285.21:07:42.08/fmout-gps/S +2.92E-07 2006.285.21:07:42.08:scan_name=285-2108,jd0610,120 2006.285.21:07:42.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.285.21:07:43.14#flagr#flagr/antenna,new-source 2006.285.21:07:43.14:checkk5 2006.285.21:07:43.64/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:07:44.03/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:07:44.56/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:07:45.14/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:07:45.62/chk_obsdata//k5ts1/T2852104??a.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.21:07:45.99/chk_obsdata//k5ts2/T2852104??b.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.21:07:46.38/chk_obsdata//k5ts3/T2852104??c.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.21:07:46.89/chk_obsdata//k5ts4/T2852104??d.dat file size is correct (nominal:800MB, actual:800MB). 2006.285.21:07:47.99/k5log//k5ts1_log_newline 2006.285.21:07:48.74/k5log//k5ts2_log_newline 2006.285.21:07:49.55/k5log//k5ts3_log_newline 2006.285.21:07:50.84/k5log//k5ts4_log_newline 2006.285.21:07:50.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:07:50.86:setupk4=1 2006.285.21:07:50.86$setupk4/echo=on 2006.285.21:07:50.86$setupk4/pcalon 2006.285.21:07:50.86$pcalon/"no phase cal control is implemented here 2006.285.21:07:50.86$setupk4/"tpicd=stop 2006.285.21:07:50.86$setupk4/"rec=synch_on 2006.285.21:07:50.86$setupk4/"rec_mode=128 2006.285.21:07:50.86$setupk4/!* 2006.285.21:07:50.86$setupk4/recpk4 2006.285.21:07:50.86$recpk4/recpatch= 2006.285.21:07:50.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:07:50.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:07:50.87$setupk4/vck44 2006.285.21:07:50.87$vck44/valo=1,524.99 2006.285.21:07:50.87#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.21:07:50.87#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.21:07:50.87#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:50.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:07:50.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:07:50.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:07:50.87#ibcon#enter wrdev, iclass 21, count 0 2006.285.21:07:50.87#ibcon#first serial, iclass 21, count 0 2006.285.21:07:50.87#ibcon#enter sib2, iclass 21, count 0 2006.285.21:07:50.87#ibcon#flushed, iclass 21, count 0 2006.285.21:07:50.87#ibcon#about to write, iclass 21, count 0 2006.285.21:07:50.87#ibcon#wrote, iclass 21, count 0 2006.285.21:07:50.87#ibcon#about to read 3, iclass 21, count 0 2006.285.21:07:50.89#ibcon#read 3, iclass 21, count 0 2006.285.21:07:50.89#ibcon#about to read 4, iclass 21, count 0 2006.285.21:07:50.89#ibcon#read 4, iclass 21, count 0 2006.285.21:07:50.89#ibcon#about to read 5, iclass 21, count 0 2006.285.21:07:50.89#ibcon#read 5, iclass 21, count 0 2006.285.21:07:50.89#ibcon#about to read 6, iclass 21, count 0 2006.285.21:07:50.89#ibcon#read 6, iclass 21, count 0 2006.285.21:07:50.89#ibcon#end of sib2, iclass 21, count 0 2006.285.21:07:50.89#ibcon#*mode == 0, iclass 21, count 0 2006.285.21:07:50.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.21:07:50.89#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:07:50.89#ibcon#*before write, iclass 21, count 0 2006.285.21:07:50.89#ibcon#enter sib2, iclass 21, count 0 2006.285.21:07:50.89#ibcon#flushed, iclass 21, count 0 2006.285.21:07:50.89#ibcon#about to write, iclass 21, count 0 2006.285.21:07:50.89#ibcon#wrote, iclass 21, count 0 2006.285.21:07:50.89#ibcon#about to read 3, iclass 21, count 0 2006.285.21:07:50.94#ibcon#read 3, iclass 21, count 0 2006.285.21:07:50.94#ibcon#about to read 4, iclass 21, count 0 2006.285.21:07:50.94#ibcon#read 4, iclass 21, count 0 2006.285.21:07:50.94#ibcon#about to read 5, iclass 21, count 0 2006.285.21:07:50.94#ibcon#read 5, iclass 21, count 0 2006.285.21:07:50.94#ibcon#about to read 6, iclass 21, count 0 2006.285.21:07:50.94#ibcon#read 6, iclass 21, count 0 2006.285.21:07:50.94#ibcon#end of sib2, iclass 21, count 0 2006.285.21:07:50.94#ibcon#*after write, iclass 21, count 0 2006.285.21:07:50.94#ibcon#*before return 0, iclass 21, count 0 2006.285.21:07:50.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:07:50.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:07:50.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.21:07:50.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.21:07:50.94$vck44/va=1,7 2006.285.21:07:50.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.21:07:50.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.21:07:50.94#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:50.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:07:50.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:07:50.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:07:50.94#ibcon#enter wrdev, iclass 23, count 2 2006.285.21:07:50.94#ibcon#first serial, iclass 23, count 2 2006.285.21:07:50.94#ibcon#enter sib2, iclass 23, count 2 2006.285.21:07:50.94#ibcon#flushed, iclass 23, count 2 2006.285.21:07:50.94#ibcon#about to write, iclass 23, count 2 2006.285.21:07:50.94#ibcon#wrote, iclass 23, count 2 2006.285.21:07:50.94#ibcon#about to read 3, iclass 23, count 2 2006.285.21:07:50.96#ibcon#read 3, iclass 23, count 2 2006.285.21:07:50.96#ibcon#about to read 4, iclass 23, count 2 2006.285.21:07:50.96#ibcon#read 4, iclass 23, count 2 2006.285.21:07:50.96#ibcon#about to read 5, iclass 23, count 2 2006.285.21:07:50.96#ibcon#read 5, iclass 23, count 2 2006.285.21:07:50.96#ibcon#about to read 6, iclass 23, count 2 2006.285.21:07:50.96#ibcon#read 6, iclass 23, count 2 2006.285.21:07:50.96#ibcon#end of sib2, iclass 23, count 2 2006.285.21:07:50.96#ibcon#*mode == 0, iclass 23, count 2 2006.285.21:07:50.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.21:07:50.96#ibcon#[25=AT01-07\r\n] 2006.285.21:07:50.96#ibcon#*before write, iclass 23, count 2 2006.285.21:07:50.96#ibcon#enter sib2, iclass 23, count 2 2006.285.21:07:50.96#ibcon#flushed, iclass 23, count 2 2006.285.21:07:50.96#ibcon#about to write, iclass 23, count 2 2006.285.21:07:50.96#ibcon#wrote, iclass 23, count 2 2006.285.21:07:50.96#ibcon#about to read 3, iclass 23, count 2 2006.285.21:07:50.99#ibcon#read 3, iclass 23, count 2 2006.285.21:07:50.99#ibcon#about to read 4, iclass 23, count 2 2006.285.21:07:50.99#ibcon#read 4, iclass 23, count 2 2006.285.21:07:50.99#ibcon#about to read 5, iclass 23, count 2 2006.285.21:07:50.99#ibcon#read 5, iclass 23, count 2 2006.285.21:07:50.99#ibcon#about to read 6, iclass 23, count 2 2006.285.21:07:50.99#ibcon#read 6, iclass 23, count 2 2006.285.21:07:50.99#ibcon#end of sib2, iclass 23, count 2 2006.285.21:07:50.99#ibcon#*after write, iclass 23, count 2 2006.285.21:07:50.99#ibcon#*before return 0, iclass 23, count 2 2006.285.21:07:50.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:07:50.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:07:50.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.21:07:50.99#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:50.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:07:51.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:07:51.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:07:51.11#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:07:51.11#ibcon#first serial, iclass 23, count 0 2006.285.21:07:51.11#ibcon#enter sib2, iclass 23, count 0 2006.285.21:07:51.11#ibcon#flushed, iclass 23, count 0 2006.285.21:07:51.11#ibcon#about to write, iclass 23, count 0 2006.285.21:07:51.11#ibcon#wrote, iclass 23, count 0 2006.285.21:07:51.11#ibcon#about to read 3, iclass 23, count 0 2006.285.21:07:51.13#ibcon#read 3, iclass 23, count 0 2006.285.21:07:51.13#ibcon#about to read 4, iclass 23, count 0 2006.285.21:07:51.13#ibcon#read 4, iclass 23, count 0 2006.285.21:07:51.13#ibcon#about to read 5, iclass 23, count 0 2006.285.21:07:51.13#ibcon#read 5, iclass 23, count 0 2006.285.21:07:51.13#ibcon#about to read 6, iclass 23, count 0 2006.285.21:07:51.13#ibcon#read 6, iclass 23, count 0 2006.285.21:07:51.13#ibcon#end of sib2, iclass 23, count 0 2006.285.21:07:51.13#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:07:51.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:07:51.13#ibcon#[25=USB\r\n] 2006.285.21:07:51.13#ibcon#*before write, iclass 23, count 0 2006.285.21:07:51.13#ibcon#enter sib2, iclass 23, count 0 2006.285.21:07:51.13#ibcon#flushed, iclass 23, count 0 2006.285.21:07:51.13#ibcon#about to write, iclass 23, count 0 2006.285.21:07:51.13#ibcon#wrote, iclass 23, count 0 2006.285.21:07:51.13#ibcon#about to read 3, iclass 23, count 0 2006.285.21:07:51.16#ibcon#read 3, iclass 23, count 0 2006.285.21:07:51.16#ibcon#about to read 4, iclass 23, count 0 2006.285.21:07:51.16#ibcon#read 4, iclass 23, count 0 2006.285.21:07:51.16#ibcon#about to read 5, iclass 23, count 0 2006.285.21:07:51.16#ibcon#read 5, iclass 23, count 0 2006.285.21:07:51.16#ibcon#about to read 6, iclass 23, count 0 2006.285.21:07:51.16#ibcon#read 6, iclass 23, count 0 2006.285.21:07:51.16#ibcon#end of sib2, iclass 23, count 0 2006.285.21:07:51.16#ibcon#*after write, iclass 23, count 0 2006.285.21:07:51.16#ibcon#*before return 0, iclass 23, count 0 2006.285.21:07:51.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:07:51.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:07:51.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:07:51.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:07:51.16$vck44/valo=2,534.99 2006.285.21:07:51.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.21:07:51.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.21:07:51.16#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:51.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:07:51.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:07:51.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:07:51.16#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:07:51.16#ibcon#first serial, iclass 25, count 0 2006.285.21:07:51.16#ibcon#enter sib2, iclass 25, count 0 2006.285.21:07:51.16#ibcon#flushed, iclass 25, count 0 2006.285.21:07:51.16#ibcon#about to write, iclass 25, count 0 2006.285.21:07:51.16#ibcon#wrote, iclass 25, count 0 2006.285.21:07:51.16#ibcon#about to read 3, iclass 25, count 0 2006.285.21:07:51.18#ibcon#read 3, iclass 25, count 0 2006.285.21:07:51.18#ibcon#about to read 4, iclass 25, count 0 2006.285.21:07:51.18#ibcon#read 4, iclass 25, count 0 2006.285.21:07:51.18#ibcon#about to read 5, iclass 25, count 0 2006.285.21:07:51.18#ibcon#read 5, iclass 25, count 0 2006.285.21:07:51.18#ibcon#about to read 6, iclass 25, count 0 2006.285.21:07:51.18#ibcon#read 6, iclass 25, count 0 2006.285.21:07:51.18#ibcon#end of sib2, iclass 25, count 0 2006.285.21:07:51.18#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:07:51.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:07:51.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:07:51.18#ibcon#*before write, iclass 25, count 0 2006.285.21:07:51.18#ibcon#enter sib2, iclass 25, count 0 2006.285.21:07:51.18#ibcon#flushed, iclass 25, count 0 2006.285.21:07:51.18#ibcon#about to write, iclass 25, count 0 2006.285.21:07:51.18#ibcon#wrote, iclass 25, count 0 2006.285.21:07:51.18#ibcon#about to read 3, iclass 25, count 0 2006.285.21:07:51.22#ibcon#read 3, iclass 25, count 0 2006.285.21:07:51.22#ibcon#about to read 4, iclass 25, count 0 2006.285.21:07:51.22#ibcon#read 4, iclass 25, count 0 2006.285.21:07:51.22#ibcon#about to read 5, iclass 25, count 0 2006.285.21:07:51.22#ibcon#read 5, iclass 25, count 0 2006.285.21:07:51.22#ibcon#about to read 6, iclass 25, count 0 2006.285.21:07:51.22#ibcon#read 6, iclass 25, count 0 2006.285.21:07:51.22#ibcon#end of sib2, iclass 25, count 0 2006.285.21:07:51.22#ibcon#*after write, iclass 25, count 0 2006.285.21:07:51.22#ibcon#*before return 0, iclass 25, count 0 2006.285.21:07:51.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:07:51.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:07:51.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:07:51.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:07:51.22$vck44/va=2,6 2006.285.21:07:51.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.21:07:51.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.21:07:51.22#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:51.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:07:51.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:07:51.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:07:51.28#ibcon#enter wrdev, iclass 27, count 2 2006.285.21:07:51.28#ibcon#first serial, iclass 27, count 2 2006.285.21:07:51.28#ibcon#enter sib2, iclass 27, count 2 2006.285.21:07:51.28#ibcon#flushed, iclass 27, count 2 2006.285.21:07:51.28#ibcon#about to write, iclass 27, count 2 2006.285.21:07:51.28#ibcon#wrote, iclass 27, count 2 2006.285.21:07:51.28#ibcon#about to read 3, iclass 27, count 2 2006.285.21:07:51.30#ibcon#read 3, iclass 27, count 2 2006.285.21:07:51.30#ibcon#about to read 4, iclass 27, count 2 2006.285.21:07:51.30#ibcon#read 4, iclass 27, count 2 2006.285.21:07:51.30#ibcon#about to read 5, iclass 27, count 2 2006.285.21:07:51.30#ibcon#read 5, iclass 27, count 2 2006.285.21:07:51.30#ibcon#about to read 6, iclass 27, count 2 2006.285.21:07:51.30#ibcon#read 6, iclass 27, count 2 2006.285.21:07:51.30#ibcon#end of sib2, iclass 27, count 2 2006.285.21:07:51.30#ibcon#*mode == 0, iclass 27, count 2 2006.285.21:07:51.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.21:07:51.30#ibcon#[25=AT02-06\r\n] 2006.285.21:07:51.30#ibcon#*before write, iclass 27, count 2 2006.285.21:07:51.30#ibcon#enter sib2, iclass 27, count 2 2006.285.21:07:51.30#ibcon#flushed, iclass 27, count 2 2006.285.21:07:51.30#ibcon#about to write, iclass 27, count 2 2006.285.21:07:51.30#ibcon#wrote, iclass 27, count 2 2006.285.21:07:51.30#ibcon#about to read 3, iclass 27, count 2 2006.285.21:07:51.33#ibcon#read 3, iclass 27, count 2 2006.285.21:07:51.33#ibcon#about to read 4, iclass 27, count 2 2006.285.21:07:51.33#ibcon#read 4, iclass 27, count 2 2006.285.21:07:51.33#ibcon#about to read 5, iclass 27, count 2 2006.285.21:07:51.33#ibcon#read 5, iclass 27, count 2 2006.285.21:07:51.33#ibcon#about to read 6, iclass 27, count 2 2006.285.21:07:51.33#ibcon#read 6, iclass 27, count 2 2006.285.21:07:51.33#ibcon#end of sib2, iclass 27, count 2 2006.285.21:07:51.33#ibcon#*after write, iclass 27, count 2 2006.285.21:07:51.33#ibcon#*before return 0, iclass 27, count 2 2006.285.21:07:51.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:07:51.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:07:51.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.21:07:51.33#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:51.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:07:51.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:07:51.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:07:51.45#ibcon#enter wrdev, iclass 27, count 0 2006.285.21:07:51.45#ibcon#first serial, iclass 27, count 0 2006.285.21:07:51.45#ibcon#enter sib2, iclass 27, count 0 2006.285.21:07:51.45#ibcon#flushed, iclass 27, count 0 2006.285.21:07:51.45#ibcon#about to write, iclass 27, count 0 2006.285.21:07:51.45#ibcon#wrote, iclass 27, count 0 2006.285.21:07:51.45#ibcon#about to read 3, iclass 27, count 0 2006.285.21:07:51.47#ibcon#read 3, iclass 27, count 0 2006.285.21:07:51.47#ibcon#about to read 4, iclass 27, count 0 2006.285.21:07:51.47#ibcon#read 4, iclass 27, count 0 2006.285.21:07:51.47#ibcon#about to read 5, iclass 27, count 0 2006.285.21:07:51.47#ibcon#read 5, iclass 27, count 0 2006.285.21:07:51.47#ibcon#about to read 6, iclass 27, count 0 2006.285.21:07:51.47#ibcon#read 6, iclass 27, count 0 2006.285.21:07:51.47#ibcon#end of sib2, iclass 27, count 0 2006.285.21:07:51.47#ibcon#*mode == 0, iclass 27, count 0 2006.285.21:07:51.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.21:07:51.47#ibcon#[25=USB\r\n] 2006.285.21:07:51.47#ibcon#*before write, iclass 27, count 0 2006.285.21:07:51.47#ibcon#enter sib2, iclass 27, count 0 2006.285.21:07:51.47#ibcon#flushed, iclass 27, count 0 2006.285.21:07:51.47#ibcon#about to write, iclass 27, count 0 2006.285.21:07:51.47#ibcon#wrote, iclass 27, count 0 2006.285.21:07:51.47#ibcon#about to read 3, iclass 27, count 0 2006.285.21:07:51.50#ibcon#read 3, iclass 27, count 0 2006.285.21:07:51.50#ibcon#about to read 4, iclass 27, count 0 2006.285.21:07:51.50#ibcon#read 4, iclass 27, count 0 2006.285.21:07:51.50#ibcon#about to read 5, iclass 27, count 0 2006.285.21:07:51.50#ibcon#read 5, iclass 27, count 0 2006.285.21:07:51.50#ibcon#about to read 6, iclass 27, count 0 2006.285.21:07:51.50#ibcon#read 6, iclass 27, count 0 2006.285.21:07:51.50#ibcon#end of sib2, iclass 27, count 0 2006.285.21:07:51.50#ibcon#*after write, iclass 27, count 0 2006.285.21:07:51.50#ibcon#*before return 0, iclass 27, count 0 2006.285.21:07:51.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:07:51.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:07:51.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.21:07:51.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.21:07:51.50$vck44/valo=3,564.99 2006.285.21:07:51.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.21:07:51.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.21:07:51.50#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:51.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:07:51.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:07:51.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:07:51.50#ibcon#enter wrdev, iclass 29, count 0 2006.285.21:07:51.50#ibcon#first serial, iclass 29, count 0 2006.285.21:07:51.50#ibcon#enter sib2, iclass 29, count 0 2006.285.21:07:51.50#ibcon#flushed, iclass 29, count 0 2006.285.21:07:51.50#ibcon#about to write, iclass 29, count 0 2006.285.21:07:51.50#ibcon#wrote, iclass 29, count 0 2006.285.21:07:51.50#ibcon#about to read 3, iclass 29, count 0 2006.285.21:07:51.52#ibcon#read 3, iclass 29, count 0 2006.285.21:07:51.97#ibcon#about to read 4, iclass 29, count 0 2006.285.21:07:51.97#ibcon#read 4, iclass 29, count 0 2006.285.21:07:51.97#ibcon#about to read 5, iclass 29, count 0 2006.285.21:07:51.97#ibcon#read 5, iclass 29, count 0 2006.285.21:07:51.97#ibcon#about to read 6, iclass 29, count 0 2006.285.21:07:51.97#ibcon#read 6, iclass 29, count 0 2006.285.21:07:51.97#ibcon#end of sib2, iclass 29, count 0 2006.285.21:07:51.97#ibcon#*mode == 0, iclass 29, count 0 2006.285.21:07:51.97#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.21:07:51.97#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:07:51.97#ibcon#*before write, iclass 29, count 0 2006.285.21:07:51.97#ibcon#enter sib2, iclass 29, count 0 2006.285.21:07:51.97#ibcon#flushed, iclass 29, count 0 2006.285.21:07:51.97#ibcon#about to write, iclass 29, count 0 2006.285.21:07:51.97#ibcon#wrote, iclass 29, count 0 2006.285.21:07:51.97#ibcon#about to read 3, iclass 29, count 0 2006.285.21:07:52.02#ibcon#read 3, iclass 29, count 0 2006.285.21:07:52.02#ibcon#about to read 4, iclass 29, count 0 2006.285.21:07:52.02#ibcon#read 4, iclass 29, count 0 2006.285.21:07:52.02#ibcon#about to read 5, iclass 29, count 0 2006.285.21:07:52.02#ibcon#read 5, iclass 29, count 0 2006.285.21:07:52.02#ibcon#about to read 6, iclass 29, count 0 2006.285.21:07:52.02#ibcon#read 6, iclass 29, count 0 2006.285.21:07:52.02#ibcon#end of sib2, iclass 29, count 0 2006.285.21:07:52.02#ibcon#*after write, iclass 29, count 0 2006.285.21:07:52.02#ibcon#*before return 0, iclass 29, count 0 2006.285.21:07:52.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:07:52.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:07:52.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.21:07:52.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.21:07:52.02$vck44/va=3,7 2006.285.21:07:52.02#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.21:07:52.02#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.21:07:52.02#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:52.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:07:52.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:07:52.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:07:52.02#ibcon#enter wrdev, iclass 31, count 2 2006.285.21:07:52.02#ibcon#first serial, iclass 31, count 2 2006.285.21:07:52.02#ibcon#enter sib2, iclass 31, count 2 2006.285.21:07:52.02#ibcon#flushed, iclass 31, count 2 2006.285.21:07:52.02#ibcon#about to write, iclass 31, count 2 2006.285.21:07:52.02#ibcon#wrote, iclass 31, count 2 2006.285.21:07:52.02#ibcon#about to read 3, iclass 31, count 2 2006.285.21:07:52.04#ibcon#read 3, iclass 31, count 2 2006.285.21:07:52.04#ibcon#about to read 4, iclass 31, count 2 2006.285.21:07:52.04#ibcon#read 4, iclass 31, count 2 2006.285.21:07:52.04#ibcon#about to read 5, iclass 31, count 2 2006.285.21:07:52.04#ibcon#read 5, iclass 31, count 2 2006.285.21:07:52.04#ibcon#about to read 6, iclass 31, count 2 2006.285.21:07:52.04#ibcon#read 6, iclass 31, count 2 2006.285.21:07:52.04#ibcon#end of sib2, iclass 31, count 2 2006.285.21:07:52.04#ibcon#*mode == 0, iclass 31, count 2 2006.285.21:07:52.04#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.21:07:52.04#ibcon#[25=AT03-07\r\n] 2006.285.21:07:52.04#ibcon#*before write, iclass 31, count 2 2006.285.21:07:52.04#ibcon#enter sib2, iclass 31, count 2 2006.285.21:07:52.04#ibcon#flushed, iclass 31, count 2 2006.285.21:07:52.04#ibcon#about to write, iclass 31, count 2 2006.285.21:07:52.04#ibcon#wrote, iclass 31, count 2 2006.285.21:07:52.04#ibcon#about to read 3, iclass 31, count 2 2006.285.21:07:52.07#ibcon#read 3, iclass 31, count 2 2006.285.21:07:52.07#ibcon#about to read 4, iclass 31, count 2 2006.285.21:07:52.07#ibcon#read 4, iclass 31, count 2 2006.285.21:07:52.07#ibcon#about to read 5, iclass 31, count 2 2006.285.21:07:52.07#ibcon#read 5, iclass 31, count 2 2006.285.21:07:52.07#ibcon#about to read 6, iclass 31, count 2 2006.285.21:07:52.07#ibcon#read 6, iclass 31, count 2 2006.285.21:07:52.07#ibcon#end of sib2, iclass 31, count 2 2006.285.21:07:52.07#ibcon#*after write, iclass 31, count 2 2006.285.21:07:52.07#ibcon#*before return 0, iclass 31, count 2 2006.285.21:07:52.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:07:52.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:07:52.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.21:07:52.07#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:52.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:07:52.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:07:52.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:07:52.19#ibcon#enter wrdev, iclass 31, count 0 2006.285.21:07:52.19#ibcon#first serial, iclass 31, count 0 2006.285.21:07:52.19#ibcon#enter sib2, iclass 31, count 0 2006.285.21:07:52.19#ibcon#flushed, iclass 31, count 0 2006.285.21:07:52.19#ibcon#about to write, iclass 31, count 0 2006.285.21:07:52.19#ibcon#wrote, iclass 31, count 0 2006.285.21:07:52.19#ibcon#about to read 3, iclass 31, count 0 2006.285.21:07:52.21#ibcon#read 3, iclass 31, count 0 2006.285.21:07:52.21#ibcon#about to read 4, iclass 31, count 0 2006.285.21:07:52.21#ibcon#read 4, iclass 31, count 0 2006.285.21:07:52.21#ibcon#about to read 5, iclass 31, count 0 2006.285.21:07:52.21#ibcon#read 5, iclass 31, count 0 2006.285.21:07:52.21#ibcon#about to read 6, iclass 31, count 0 2006.285.21:07:52.21#ibcon#read 6, iclass 31, count 0 2006.285.21:07:52.21#ibcon#end of sib2, iclass 31, count 0 2006.285.21:07:52.21#ibcon#*mode == 0, iclass 31, count 0 2006.285.21:07:52.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.21:07:52.21#ibcon#[25=USB\r\n] 2006.285.21:07:52.21#ibcon#*before write, iclass 31, count 0 2006.285.21:07:52.21#ibcon#enter sib2, iclass 31, count 0 2006.285.21:07:52.21#ibcon#flushed, iclass 31, count 0 2006.285.21:07:52.21#ibcon#about to write, iclass 31, count 0 2006.285.21:07:52.21#ibcon#wrote, iclass 31, count 0 2006.285.21:07:52.21#ibcon#about to read 3, iclass 31, count 0 2006.285.21:07:52.24#ibcon#read 3, iclass 31, count 0 2006.285.21:07:52.24#ibcon#about to read 4, iclass 31, count 0 2006.285.21:07:52.24#ibcon#read 4, iclass 31, count 0 2006.285.21:07:52.24#ibcon#about to read 5, iclass 31, count 0 2006.285.21:07:52.24#ibcon#read 5, iclass 31, count 0 2006.285.21:07:52.24#ibcon#about to read 6, iclass 31, count 0 2006.285.21:07:52.24#ibcon#read 6, iclass 31, count 0 2006.285.21:07:52.24#ibcon#end of sib2, iclass 31, count 0 2006.285.21:07:52.24#ibcon#*after write, iclass 31, count 0 2006.285.21:07:52.24#ibcon#*before return 0, iclass 31, count 0 2006.285.21:07:52.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:07:52.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:07:52.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.21:07:52.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.21:07:52.24$vck44/valo=4,624.99 2006.285.21:07:52.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.21:07:52.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.21:07:52.24#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:52.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:07:52.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:07:52.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:07:52.24#ibcon#enter wrdev, iclass 33, count 0 2006.285.21:07:52.24#ibcon#first serial, iclass 33, count 0 2006.285.21:07:52.24#ibcon#enter sib2, iclass 33, count 0 2006.285.21:07:52.24#ibcon#flushed, iclass 33, count 0 2006.285.21:07:52.24#ibcon#about to write, iclass 33, count 0 2006.285.21:07:52.24#ibcon#wrote, iclass 33, count 0 2006.285.21:07:52.24#ibcon#about to read 3, iclass 33, count 0 2006.285.21:07:52.26#ibcon#read 3, iclass 33, count 0 2006.285.21:07:52.26#ibcon#about to read 4, iclass 33, count 0 2006.285.21:07:52.26#ibcon#read 4, iclass 33, count 0 2006.285.21:07:52.26#ibcon#about to read 5, iclass 33, count 0 2006.285.21:07:52.26#ibcon#read 5, iclass 33, count 0 2006.285.21:07:52.26#ibcon#about to read 6, iclass 33, count 0 2006.285.21:07:52.26#ibcon#read 6, iclass 33, count 0 2006.285.21:07:52.26#ibcon#end of sib2, iclass 33, count 0 2006.285.21:07:52.26#ibcon#*mode == 0, iclass 33, count 0 2006.285.21:07:52.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.21:07:52.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:07:52.26#ibcon#*before write, iclass 33, count 0 2006.285.21:07:52.26#ibcon#enter sib2, iclass 33, count 0 2006.285.21:07:52.26#ibcon#flushed, iclass 33, count 0 2006.285.21:07:52.26#ibcon#about to write, iclass 33, count 0 2006.285.21:07:52.26#ibcon#wrote, iclass 33, count 0 2006.285.21:07:52.26#ibcon#about to read 3, iclass 33, count 0 2006.285.21:07:52.30#ibcon#read 3, iclass 33, count 0 2006.285.21:07:52.30#ibcon#about to read 4, iclass 33, count 0 2006.285.21:07:52.30#ibcon#read 4, iclass 33, count 0 2006.285.21:07:52.30#ibcon#about to read 5, iclass 33, count 0 2006.285.21:07:52.30#ibcon#read 5, iclass 33, count 0 2006.285.21:07:52.30#ibcon#about to read 6, iclass 33, count 0 2006.285.21:07:52.30#ibcon#read 6, iclass 33, count 0 2006.285.21:07:52.30#ibcon#end of sib2, iclass 33, count 0 2006.285.21:07:52.30#ibcon#*after write, iclass 33, count 0 2006.285.21:07:52.30#ibcon#*before return 0, iclass 33, count 0 2006.285.21:07:52.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:07:52.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:07:52.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.21:07:52.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.21:07:52.30$vck44/va=4,6 2006.285.21:07:52.51#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.21:07:52.51#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.21:07:52.51#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:52.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:07:52.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:07:52.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:07:52.51#ibcon#enter wrdev, iclass 35, count 2 2006.285.21:07:52.51#ibcon#first serial, iclass 35, count 2 2006.285.21:07:52.51#ibcon#enter sib2, iclass 35, count 2 2006.285.21:07:52.51#ibcon#flushed, iclass 35, count 2 2006.285.21:07:52.51#ibcon#about to write, iclass 35, count 2 2006.285.21:07:52.51#ibcon#wrote, iclass 35, count 2 2006.285.21:07:52.51#ibcon#about to read 3, iclass 35, count 2 2006.285.21:07:52.53#ibcon#read 3, iclass 35, count 2 2006.285.21:07:52.53#ibcon#about to read 4, iclass 35, count 2 2006.285.21:07:52.53#ibcon#read 4, iclass 35, count 2 2006.285.21:07:52.53#ibcon#about to read 5, iclass 35, count 2 2006.285.21:07:52.53#ibcon#read 5, iclass 35, count 2 2006.285.21:07:52.53#ibcon#about to read 6, iclass 35, count 2 2006.285.21:07:52.53#ibcon#read 6, iclass 35, count 2 2006.285.21:07:52.53#ibcon#end of sib2, iclass 35, count 2 2006.285.21:07:52.53#ibcon#*mode == 0, iclass 35, count 2 2006.285.21:07:52.53#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.21:07:52.53#ibcon#[25=AT04-06\r\n] 2006.285.21:07:52.53#ibcon#*before write, iclass 35, count 2 2006.285.21:07:52.53#ibcon#enter sib2, iclass 35, count 2 2006.285.21:07:52.53#ibcon#flushed, iclass 35, count 2 2006.285.21:07:52.53#ibcon#about to write, iclass 35, count 2 2006.285.21:07:52.53#ibcon#wrote, iclass 35, count 2 2006.285.21:07:52.53#ibcon#about to read 3, iclass 35, count 2 2006.285.21:07:52.56#ibcon#read 3, iclass 35, count 2 2006.285.21:07:52.56#ibcon#about to read 4, iclass 35, count 2 2006.285.21:07:52.56#ibcon#read 4, iclass 35, count 2 2006.285.21:07:52.56#ibcon#about to read 5, iclass 35, count 2 2006.285.21:07:52.56#ibcon#read 5, iclass 35, count 2 2006.285.21:07:52.56#ibcon#about to read 6, iclass 35, count 2 2006.285.21:07:52.56#ibcon#read 6, iclass 35, count 2 2006.285.21:07:52.56#ibcon#end of sib2, iclass 35, count 2 2006.285.21:07:52.56#ibcon#*after write, iclass 35, count 2 2006.285.21:07:52.56#ibcon#*before return 0, iclass 35, count 2 2006.285.21:07:52.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:07:52.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:07:52.56#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.21:07:52.56#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:52.56#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:07:52.68#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:07:52.68#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:07:52.68#ibcon#enter wrdev, iclass 35, count 0 2006.285.21:07:52.68#ibcon#first serial, iclass 35, count 0 2006.285.21:07:52.68#ibcon#enter sib2, iclass 35, count 0 2006.285.21:07:52.68#ibcon#flushed, iclass 35, count 0 2006.285.21:07:52.68#ibcon#about to write, iclass 35, count 0 2006.285.21:07:52.68#ibcon#wrote, iclass 35, count 0 2006.285.21:07:52.68#ibcon#about to read 3, iclass 35, count 0 2006.285.21:07:52.70#ibcon#read 3, iclass 35, count 0 2006.285.21:07:52.70#ibcon#about to read 4, iclass 35, count 0 2006.285.21:07:52.70#ibcon#read 4, iclass 35, count 0 2006.285.21:07:52.70#ibcon#about to read 5, iclass 35, count 0 2006.285.21:07:52.70#ibcon#read 5, iclass 35, count 0 2006.285.21:07:52.70#ibcon#about to read 6, iclass 35, count 0 2006.285.21:07:52.70#ibcon#read 6, iclass 35, count 0 2006.285.21:07:52.70#ibcon#end of sib2, iclass 35, count 0 2006.285.21:07:52.70#ibcon#*mode == 0, iclass 35, count 0 2006.285.21:07:52.70#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.21:07:52.70#ibcon#[25=USB\r\n] 2006.285.21:07:52.70#ibcon#*before write, iclass 35, count 0 2006.285.21:07:52.70#ibcon#enter sib2, iclass 35, count 0 2006.285.21:07:52.70#ibcon#flushed, iclass 35, count 0 2006.285.21:07:52.70#ibcon#about to write, iclass 35, count 0 2006.285.21:07:52.70#ibcon#wrote, iclass 35, count 0 2006.285.21:07:52.70#ibcon#about to read 3, iclass 35, count 0 2006.285.21:07:52.73#ibcon#read 3, iclass 35, count 0 2006.285.21:07:52.73#ibcon#about to read 4, iclass 35, count 0 2006.285.21:07:52.73#ibcon#read 4, iclass 35, count 0 2006.285.21:07:52.73#ibcon#about to read 5, iclass 35, count 0 2006.285.21:07:52.73#ibcon#read 5, iclass 35, count 0 2006.285.21:07:52.73#ibcon#about to read 6, iclass 35, count 0 2006.285.21:07:52.73#ibcon#read 6, iclass 35, count 0 2006.285.21:07:52.73#ibcon#end of sib2, iclass 35, count 0 2006.285.21:07:52.73#ibcon#*after write, iclass 35, count 0 2006.285.21:07:52.73#ibcon#*before return 0, iclass 35, count 0 2006.285.21:07:52.73#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:07:52.73#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:07:52.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.21:07:52.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.21:07:52.73$vck44/valo=5,734.99 2006.285.21:07:52.73#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.21:07:52.73#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.21:07:52.73#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:52.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:07:52.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:07:52.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:07:52.73#ibcon#enter wrdev, iclass 37, count 0 2006.285.21:07:52.73#ibcon#first serial, iclass 37, count 0 2006.285.21:07:52.73#ibcon#enter sib2, iclass 37, count 0 2006.285.21:07:52.73#ibcon#flushed, iclass 37, count 0 2006.285.21:07:52.73#ibcon#about to write, iclass 37, count 0 2006.285.21:07:52.73#ibcon#wrote, iclass 37, count 0 2006.285.21:07:52.73#ibcon#about to read 3, iclass 37, count 0 2006.285.21:07:52.75#ibcon#read 3, iclass 37, count 0 2006.285.21:07:52.75#ibcon#about to read 4, iclass 37, count 0 2006.285.21:07:52.75#ibcon#read 4, iclass 37, count 0 2006.285.21:07:52.75#ibcon#about to read 5, iclass 37, count 0 2006.285.21:07:52.75#ibcon#read 5, iclass 37, count 0 2006.285.21:07:52.75#ibcon#about to read 6, iclass 37, count 0 2006.285.21:07:52.75#ibcon#read 6, iclass 37, count 0 2006.285.21:07:52.75#ibcon#end of sib2, iclass 37, count 0 2006.285.21:07:52.75#ibcon#*mode == 0, iclass 37, count 0 2006.285.21:07:52.75#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.21:07:52.75#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:07:52.75#ibcon#*before write, iclass 37, count 0 2006.285.21:07:52.75#ibcon#enter sib2, iclass 37, count 0 2006.285.21:07:52.75#ibcon#flushed, iclass 37, count 0 2006.285.21:07:52.75#ibcon#about to write, iclass 37, count 0 2006.285.21:07:52.75#ibcon#wrote, iclass 37, count 0 2006.285.21:07:52.75#ibcon#about to read 3, iclass 37, count 0 2006.285.21:07:52.79#ibcon#read 3, iclass 37, count 0 2006.285.21:07:52.79#ibcon#about to read 4, iclass 37, count 0 2006.285.21:07:52.79#ibcon#read 4, iclass 37, count 0 2006.285.21:07:52.79#ibcon#about to read 5, iclass 37, count 0 2006.285.21:07:52.79#ibcon#read 5, iclass 37, count 0 2006.285.21:07:52.79#ibcon#about to read 6, iclass 37, count 0 2006.285.21:07:52.79#ibcon#read 6, iclass 37, count 0 2006.285.21:07:52.79#ibcon#end of sib2, iclass 37, count 0 2006.285.21:07:52.79#ibcon#*after write, iclass 37, count 0 2006.285.21:07:52.79#ibcon#*before return 0, iclass 37, count 0 2006.285.21:07:52.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:07:52.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:07:52.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.21:07:52.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.21:07:52.79$vck44/va=5,3 2006.285.21:07:52.79#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.21:07:52.79#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.21:07:52.79#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:52.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:07:52.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:07:52.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:07:52.85#ibcon#enter wrdev, iclass 39, count 2 2006.285.21:07:52.85#ibcon#first serial, iclass 39, count 2 2006.285.21:07:52.85#ibcon#enter sib2, iclass 39, count 2 2006.285.21:07:52.85#ibcon#flushed, iclass 39, count 2 2006.285.21:07:52.85#ibcon#about to write, iclass 39, count 2 2006.285.21:07:52.85#ibcon#wrote, iclass 39, count 2 2006.285.21:07:52.85#ibcon#about to read 3, iclass 39, count 2 2006.285.21:07:52.87#ibcon#read 3, iclass 39, count 2 2006.285.21:07:52.87#ibcon#about to read 4, iclass 39, count 2 2006.285.21:07:52.87#ibcon#read 4, iclass 39, count 2 2006.285.21:07:52.87#ibcon#about to read 5, iclass 39, count 2 2006.285.21:07:52.87#ibcon#read 5, iclass 39, count 2 2006.285.21:07:52.87#ibcon#about to read 6, iclass 39, count 2 2006.285.21:07:52.87#ibcon#read 6, iclass 39, count 2 2006.285.21:07:52.87#ibcon#end of sib2, iclass 39, count 2 2006.285.21:07:52.87#ibcon#*mode == 0, iclass 39, count 2 2006.285.21:07:52.87#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.21:07:52.87#ibcon#[25=AT05-03\r\n] 2006.285.21:07:52.87#ibcon#*before write, iclass 39, count 2 2006.285.21:07:52.87#ibcon#enter sib2, iclass 39, count 2 2006.285.21:07:52.87#ibcon#flushed, iclass 39, count 2 2006.285.21:07:52.87#ibcon#about to write, iclass 39, count 2 2006.285.21:07:52.87#ibcon#wrote, iclass 39, count 2 2006.285.21:07:52.87#ibcon#about to read 3, iclass 39, count 2 2006.285.21:07:52.90#ibcon#read 3, iclass 39, count 2 2006.285.21:07:52.90#ibcon#about to read 4, iclass 39, count 2 2006.285.21:07:52.90#ibcon#read 4, iclass 39, count 2 2006.285.21:07:52.90#ibcon#about to read 5, iclass 39, count 2 2006.285.21:07:52.90#ibcon#read 5, iclass 39, count 2 2006.285.21:07:52.90#ibcon#about to read 6, iclass 39, count 2 2006.285.21:07:52.90#ibcon#read 6, iclass 39, count 2 2006.285.21:07:52.90#ibcon#end of sib2, iclass 39, count 2 2006.285.21:07:52.90#ibcon#*after write, iclass 39, count 2 2006.285.21:07:52.90#ibcon#*before return 0, iclass 39, count 2 2006.285.21:07:52.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:07:52.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:07:52.90#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.21:07:52.90#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:52.90#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:07:53.02#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:07:53.02#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:07:53.02#ibcon#enter wrdev, iclass 39, count 0 2006.285.21:07:53.02#ibcon#first serial, iclass 39, count 0 2006.285.21:07:53.02#ibcon#enter sib2, iclass 39, count 0 2006.285.21:07:53.02#ibcon#flushed, iclass 39, count 0 2006.285.21:07:53.02#ibcon#about to write, iclass 39, count 0 2006.285.21:07:53.02#ibcon#wrote, iclass 39, count 0 2006.285.21:07:53.02#ibcon#about to read 3, iclass 39, count 0 2006.285.21:07:53.04#ibcon#read 3, iclass 39, count 0 2006.285.21:07:53.04#ibcon#about to read 4, iclass 39, count 0 2006.285.21:07:53.04#ibcon#read 4, iclass 39, count 0 2006.285.21:07:53.04#ibcon#about to read 5, iclass 39, count 0 2006.285.21:07:53.04#ibcon#read 5, iclass 39, count 0 2006.285.21:07:53.04#ibcon#about to read 6, iclass 39, count 0 2006.285.21:07:53.04#ibcon#read 6, iclass 39, count 0 2006.285.21:07:53.04#ibcon#end of sib2, iclass 39, count 0 2006.285.21:07:53.04#ibcon#*mode == 0, iclass 39, count 0 2006.285.21:07:53.04#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.21:07:53.04#ibcon#[25=USB\r\n] 2006.285.21:07:53.04#ibcon#*before write, iclass 39, count 0 2006.285.21:07:53.04#ibcon#enter sib2, iclass 39, count 0 2006.285.21:07:53.04#ibcon#flushed, iclass 39, count 0 2006.285.21:07:53.04#ibcon#about to write, iclass 39, count 0 2006.285.21:07:53.04#ibcon#wrote, iclass 39, count 0 2006.285.21:07:53.04#ibcon#about to read 3, iclass 39, count 0 2006.285.21:07:53.07#ibcon#read 3, iclass 39, count 0 2006.285.21:07:53.07#ibcon#about to read 4, iclass 39, count 0 2006.285.21:07:53.07#ibcon#read 4, iclass 39, count 0 2006.285.21:07:53.07#ibcon#about to read 5, iclass 39, count 0 2006.285.21:07:53.07#ibcon#read 5, iclass 39, count 0 2006.285.21:07:53.07#ibcon#about to read 6, iclass 39, count 0 2006.285.21:07:53.07#ibcon#read 6, iclass 39, count 0 2006.285.21:07:53.07#ibcon#end of sib2, iclass 39, count 0 2006.285.21:07:53.07#ibcon#*after write, iclass 39, count 0 2006.285.21:07:53.07#ibcon#*before return 0, iclass 39, count 0 2006.285.21:07:53.07#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:07:53.07#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:07:53.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.21:07:53.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.21:07:53.07$vck44/valo=6,814.99 2006.285.21:07:53.07#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.21:07:53.07#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.21:07:53.07#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:53.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:07:53.07#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:07:53.07#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:07:53.07#ibcon#enter wrdev, iclass 3, count 0 2006.285.21:07:53.07#ibcon#first serial, iclass 3, count 0 2006.285.21:07:53.07#ibcon#enter sib2, iclass 3, count 0 2006.285.21:07:53.07#ibcon#flushed, iclass 3, count 0 2006.285.21:07:53.07#ibcon#about to write, iclass 3, count 0 2006.285.21:07:53.07#ibcon#wrote, iclass 3, count 0 2006.285.21:07:53.07#ibcon#about to read 3, iclass 3, count 0 2006.285.21:07:53.09#ibcon#read 3, iclass 3, count 0 2006.285.21:07:53.09#ibcon#about to read 4, iclass 3, count 0 2006.285.21:07:53.09#ibcon#read 4, iclass 3, count 0 2006.285.21:07:53.09#ibcon#about to read 5, iclass 3, count 0 2006.285.21:07:53.09#ibcon#read 5, iclass 3, count 0 2006.285.21:07:53.09#ibcon#about to read 6, iclass 3, count 0 2006.285.21:07:53.09#ibcon#read 6, iclass 3, count 0 2006.285.21:07:53.09#ibcon#end of sib2, iclass 3, count 0 2006.285.21:07:53.09#ibcon#*mode == 0, iclass 3, count 0 2006.285.21:07:53.09#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.21:07:53.09#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:07:53.09#ibcon#*before write, iclass 3, count 0 2006.285.21:07:53.09#ibcon#enter sib2, iclass 3, count 0 2006.285.21:07:53.09#ibcon#flushed, iclass 3, count 0 2006.285.21:07:53.09#ibcon#about to write, iclass 3, count 0 2006.285.21:07:53.09#ibcon#wrote, iclass 3, count 0 2006.285.21:07:53.09#ibcon#about to read 3, iclass 3, count 0 2006.285.21:07:53.13#ibcon#read 3, iclass 3, count 0 2006.285.21:07:53.13#ibcon#about to read 4, iclass 3, count 0 2006.285.21:07:53.13#ibcon#read 4, iclass 3, count 0 2006.285.21:07:53.13#ibcon#about to read 5, iclass 3, count 0 2006.285.21:07:53.13#ibcon#read 5, iclass 3, count 0 2006.285.21:07:53.13#ibcon#about to read 6, iclass 3, count 0 2006.285.21:07:53.13#ibcon#read 6, iclass 3, count 0 2006.285.21:07:53.13#ibcon#end of sib2, iclass 3, count 0 2006.285.21:07:53.13#ibcon#*after write, iclass 3, count 0 2006.285.21:07:53.13#ibcon#*before return 0, iclass 3, count 0 2006.285.21:07:53.13#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:07:53.13#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:07:53.13#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.21:07:53.13#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.21:07:53.13$vck44/va=6,4 2006.285.21:07:53.13#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.21:07:53.13#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.21:07:53.13#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:53.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:07:53.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:07:53.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:07:53.19#ibcon#enter wrdev, iclass 5, count 2 2006.285.21:07:53.19#ibcon#first serial, iclass 5, count 2 2006.285.21:07:53.19#ibcon#enter sib2, iclass 5, count 2 2006.285.21:07:53.19#ibcon#flushed, iclass 5, count 2 2006.285.21:07:53.19#ibcon#about to write, iclass 5, count 2 2006.285.21:07:53.19#ibcon#wrote, iclass 5, count 2 2006.285.21:07:53.19#ibcon#about to read 3, iclass 5, count 2 2006.285.21:07:53.21#ibcon#read 3, iclass 5, count 2 2006.285.21:07:53.21#ibcon#about to read 4, iclass 5, count 2 2006.285.21:07:53.21#ibcon#read 4, iclass 5, count 2 2006.285.21:07:53.21#ibcon#about to read 5, iclass 5, count 2 2006.285.21:07:53.21#ibcon#read 5, iclass 5, count 2 2006.285.21:07:53.21#ibcon#about to read 6, iclass 5, count 2 2006.285.21:07:53.21#ibcon#read 6, iclass 5, count 2 2006.285.21:07:53.21#ibcon#end of sib2, iclass 5, count 2 2006.285.21:07:53.21#ibcon#*mode == 0, iclass 5, count 2 2006.285.21:07:53.21#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.21:07:53.21#ibcon#[25=AT06-04\r\n] 2006.285.21:07:53.21#ibcon#*before write, iclass 5, count 2 2006.285.21:07:53.21#ibcon#enter sib2, iclass 5, count 2 2006.285.21:07:53.21#ibcon#flushed, iclass 5, count 2 2006.285.21:07:53.21#ibcon#about to write, iclass 5, count 2 2006.285.21:07:53.21#ibcon#wrote, iclass 5, count 2 2006.285.21:07:53.21#ibcon#about to read 3, iclass 5, count 2 2006.285.21:07:53.24#ibcon#read 3, iclass 5, count 2 2006.285.21:07:53.24#ibcon#about to read 4, iclass 5, count 2 2006.285.21:07:53.24#ibcon#read 4, iclass 5, count 2 2006.285.21:07:53.24#ibcon#about to read 5, iclass 5, count 2 2006.285.21:07:53.24#ibcon#read 5, iclass 5, count 2 2006.285.21:07:53.24#ibcon#about to read 6, iclass 5, count 2 2006.285.21:07:53.24#ibcon#read 6, iclass 5, count 2 2006.285.21:07:53.24#ibcon#end of sib2, iclass 5, count 2 2006.285.21:07:53.24#ibcon#*after write, iclass 5, count 2 2006.285.21:07:53.24#ibcon#*before return 0, iclass 5, count 2 2006.285.21:07:53.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:07:53.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:07:53.24#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.21:07:53.24#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:53.24#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:07:53.36#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:07:53.36#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:07:53.36#ibcon#enter wrdev, iclass 5, count 0 2006.285.21:07:53.36#ibcon#first serial, iclass 5, count 0 2006.285.21:07:53.36#ibcon#enter sib2, iclass 5, count 0 2006.285.21:07:53.36#ibcon#flushed, iclass 5, count 0 2006.285.21:07:53.36#ibcon#about to write, iclass 5, count 0 2006.285.21:07:53.36#ibcon#wrote, iclass 5, count 0 2006.285.21:07:53.36#ibcon#about to read 3, iclass 5, count 0 2006.285.21:07:53.38#ibcon#read 3, iclass 5, count 0 2006.285.21:07:53.38#ibcon#about to read 4, iclass 5, count 0 2006.285.21:07:53.38#ibcon#read 4, iclass 5, count 0 2006.285.21:07:53.38#ibcon#about to read 5, iclass 5, count 0 2006.285.21:07:53.38#ibcon#read 5, iclass 5, count 0 2006.285.21:07:53.38#ibcon#about to read 6, iclass 5, count 0 2006.285.21:07:53.38#ibcon#read 6, iclass 5, count 0 2006.285.21:07:53.38#ibcon#end of sib2, iclass 5, count 0 2006.285.21:07:53.38#ibcon#*mode == 0, iclass 5, count 0 2006.285.21:07:53.38#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.21:07:53.38#ibcon#[25=USB\r\n] 2006.285.21:07:53.38#ibcon#*before write, iclass 5, count 0 2006.285.21:07:53.38#ibcon#enter sib2, iclass 5, count 0 2006.285.21:07:53.38#ibcon#flushed, iclass 5, count 0 2006.285.21:07:53.38#ibcon#about to write, iclass 5, count 0 2006.285.21:07:53.38#ibcon#wrote, iclass 5, count 0 2006.285.21:07:53.38#ibcon#about to read 3, iclass 5, count 0 2006.285.21:07:53.41#ibcon#read 3, iclass 5, count 0 2006.285.21:07:53.41#ibcon#about to read 4, iclass 5, count 0 2006.285.21:07:53.41#ibcon#read 4, iclass 5, count 0 2006.285.21:07:53.41#ibcon#about to read 5, iclass 5, count 0 2006.285.21:07:53.41#ibcon#read 5, iclass 5, count 0 2006.285.21:07:53.41#ibcon#about to read 6, iclass 5, count 0 2006.285.21:07:53.41#ibcon#read 6, iclass 5, count 0 2006.285.21:07:53.41#ibcon#end of sib2, iclass 5, count 0 2006.285.21:07:53.41#ibcon#*after write, iclass 5, count 0 2006.285.21:07:53.41#ibcon#*before return 0, iclass 5, count 0 2006.285.21:07:53.41#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:07:53.41#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:07:53.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.21:07:53.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.21:07:53.41$vck44/valo=7,864.99 2006.285.21:07:53.41#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.21:07:53.41#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.21:07:53.41#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:53.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:07:53.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:07:53.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:07:53.41#ibcon#enter wrdev, iclass 7, count 0 2006.285.21:07:53.41#ibcon#first serial, iclass 7, count 0 2006.285.21:07:53.41#ibcon#enter sib2, iclass 7, count 0 2006.285.21:07:53.41#ibcon#flushed, iclass 7, count 0 2006.285.21:07:53.41#ibcon#about to write, iclass 7, count 0 2006.285.21:07:53.41#ibcon#wrote, iclass 7, count 0 2006.285.21:07:53.41#ibcon#about to read 3, iclass 7, count 0 2006.285.21:07:53.43#ibcon#read 3, iclass 7, count 0 2006.285.21:07:53.43#ibcon#about to read 4, iclass 7, count 0 2006.285.21:07:53.43#ibcon#read 4, iclass 7, count 0 2006.285.21:07:53.43#ibcon#about to read 5, iclass 7, count 0 2006.285.21:07:53.43#ibcon#read 5, iclass 7, count 0 2006.285.21:07:53.43#ibcon#about to read 6, iclass 7, count 0 2006.285.21:07:53.43#ibcon#read 6, iclass 7, count 0 2006.285.21:07:53.43#ibcon#end of sib2, iclass 7, count 0 2006.285.21:07:53.43#ibcon#*mode == 0, iclass 7, count 0 2006.285.21:07:53.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.21:07:53.43#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:07:53.43#ibcon#*before write, iclass 7, count 0 2006.285.21:07:53.43#ibcon#enter sib2, iclass 7, count 0 2006.285.21:07:53.43#ibcon#flushed, iclass 7, count 0 2006.285.21:07:53.43#ibcon#about to write, iclass 7, count 0 2006.285.21:07:53.43#ibcon#wrote, iclass 7, count 0 2006.285.21:07:53.43#ibcon#about to read 3, iclass 7, count 0 2006.285.21:07:53.47#ibcon#read 3, iclass 7, count 0 2006.285.21:07:53.47#ibcon#about to read 4, iclass 7, count 0 2006.285.21:07:53.47#ibcon#read 4, iclass 7, count 0 2006.285.21:07:53.47#ibcon#about to read 5, iclass 7, count 0 2006.285.21:07:53.47#ibcon#read 5, iclass 7, count 0 2006.285.21:07:53.47#ibcon#about to read 6, iclass 7, count 0 2006.285.21:07:53.47#ibcon#read 6, iclass 7, count 0 2006.285.21:07:53.47#ibcon#end of sib2, iclass 7, count 0 2006.285.21:07:53.47#ibcon#*after write, iclass 7, count 0 2006.285.21:07:53.47#ibcon#*before return 0, iclass 7, count 0 2006.285.21:07:53.47#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:07:53.47#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:07:53.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.21:07:53.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.21:07:53.47$vck44/va=7,4 2006.285.21:07:53.56#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.21:07:53.56#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.21:07:53.56#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:53.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:07:53.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:07:53.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:07:53.57#ibcon#enter wrdev, iclass 11, count 2 2006.285.21:07:53.57#ibcon#first serial, iclass 11, count 2 2006.285.21:07:53.57#ibcon#enter sib2, iclass 11, count 2 2006.285.21:07:53.57#ibcon#flushed, iclass 11, count 2 2006.285.21:07:53.57#ibcon#about to write, iclass 11, count 2 2006.285.21:07:53.57#ibcon#wrote, iclass 11, count 2 2006.285.21:07:53.57#ibcon#about to read 3, iclass 11, count 2 2006.285.21:07:53.58#ibcon#read 3, iclass 11, count 2 2006.285.21:07:53.58#ibcon#about to read 4, iclass 11, count 2 2006.285.21:07:53.58#ibcon#read 4, iclass 11, count 2 2006.285.21:07:53.58#ibcon#about to read 5, iclass 11, count 2 2006.285.21:07:53.58#ibcon#read 5, iclass 11, count 2 2006.285.21:07:53.58#ibcon#about to read 6, iclass 11, count 2 2006.285.21:07:53.58#ibcon#read 6, iclass 11, count 2 2006.285.21:07:53.58#ibcon#end of sib2, iclass 11, count 2 2006.285.21:07:53.58#ibcon#*mode == 0, iclass 11, count 2 2006.285.21:07:53.58#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.21:07:53.58#ibcon#[25=AT07-04\r\n] 2006.285.21:07:53.58#ibcon#*before write, iclass 11, count 2 2006.285.21:07:53.58#ibcon#enter sib2, iclass 11, count 2 2006.285.21:07:53.58#ibcon#flushed, iclass 11, count 2 2006.285.21:07:53.58#ibcon#about to write, iclass 11, count 2 2006.285.21:07:53.58#ibcon#wrote, iclass 11, count 2 2006.285.21:07:53.58#ibcon#about to read 3, iclass 11, count 2 2006.285.21:07:53.61#ibcon#read 3, iclass 11, count 2 2006.285.21:07:53.61#ibcon#about to read 4, iclass 11, count 2 2006.285.21:07:53.61#ibcon#read 4, iclass 11, count 2 2006.285.21:07:53.61#ibcon#about to read 5, iclass 11, count 2 2006.285.21:07:53.61#ibcon#read 5, iclass 11, count 2 2006.285.21:07:53.61#ibcon#about to read 6, iclass 11, count 2 2006.285.21:07:53.61#ibcon#read 6, iclass 11, count 2 2006.285.21:07:53.61#ibcon#end of sib2, iclass 11, count 2 2006.285.21:07:53.61#ibcon#*after write, iclass 11, count 2 2006.285.21:07:53.61#ibcon#*before return 0, iclass 11, count 2 2006.285.21:07:53.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:07:53.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:07:53.61#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.21:07:53.61#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:53.61#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:07:53.73#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:07:53.73#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:07:53.73#ibcon#enter wrdev, iclass 11, count 0 2006.285.21:07:53.73#ibcon#first serial, iclass 11, count 0 2006.285.21:07:53.73#ibcon#enter sib2, iclass 11, count 0 2006.285.21:07:53.73#ibcon#flushed, iclass 11, count 0 2006.285.21:07:53.73#ibcon#about to write, iclass 11, count 0 2006.285.21:07:53.73#ibcon#wrote, iclass 11, count 0 2006.285.21:07:53.73#ibcon#about to read 3, iclass 11, count 0 2006.285.21:07:53.75#ibcon#read 3, iclass 11, count 0 2006.285.21:07:53.75#ibcon#about to read 4, iclass 11, count 0 2006.285.21:07:53.75#ibcon#read 4, iclass 11, count 0 2006.285.21:07:53.75#ibcon#about to read 5, iclass 11, count 0 2006.285.21:07:53.75#ibcon#read 5, iclass 11, count 0 2006.285.21:07:53.75#ibcon#about to read 6, iclass 11, count 0 2006.285.21:07:53.75#ibcon#read 6, iclass 11, count 0 2006.285.21:07:53.75#ibcon#end of sib2, iclass 11, count 0 2006.285.21:07:53.75#ibcon#*mode == 0, iclass 11, count 0 2006.285.21:07:53.75#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.21:07:53.75#ibcon#[25=USB\r\n] 2006.285.21:07:53.75#ibcon#*before write, iclass 11, count 0 2006.285.21:07:53.75#ibcon#enter sib2, iclass 11, count 0 2006.285.21:07:53.75#ibcon#flushed, iclass 11, count 0 2006.285.21:07:53.75#ibcon#about to write, iclass 11, count 0 2006.285.21:07:53.75#ibcon#wrote, iclass 11, count 0 2006.285.21:07:53.75#ibcon#about to read 3, iclass 11, count 0 2006.285.21:07:53.78#ibcon#read 3, iclass 11, count 0 2006.285.21:07:53.78#ibcon#about to read 4, iclass 11, count 0 2006.285.21:07:53.78#ibcon#read 4, iclass 11, count 0 2006.285.21:07:53.78#ibcon#about to read 5, iclass 11, count 0 2006.285.21:07:53.78#ibcon#read 5, iclass 11, count 0 2006.285.21:07:53.78#ibcon#about to read 6, iclass 11, count 0 2006.285.21:07:53.78#ibcon#read 6, iclass 11, count 0 2006.285.21:07:53.78#ibcon#end of sib2, iclass 11, count 0 2006.285.21:07:53.78#ibcon#*after write, iclass 11, count 0 2006.285.21:07:53.78#ibcon#*before return 0, iclass 11, count 0 2006.285.21:07:53.78#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:07:53.78#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:07:53.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.21:07:53.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.21:07:53.78$vck44/valo=8,884.99 2006.285.21:07:53.78#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.21:07:53.78#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.21:07:53.78#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:53.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:07:53.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:07:53.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:07:53.78#ibcon#enter wrdev, iclass 13, count 0 2006.285.21:07:53.78#ibcon#first serial, iclass 13, count 0 2006.285.21:07:53.78#ibcon#enter sib2, iclass 13, count 0 2006.285.21:07:53.78#ibcon#flushed, iclass 13, count 0 2006.285.21:07:53.78#ibcon#about to write, iclass 13, count 0 2006.285.21:07:53.78#ibcon#wrote, iclass 13, count 0 2006.285.21:07:53.78#ibcon#about to read 3, iclass 13, count 0 2006.285.21:07:53.80#ibcon#read 3, iclass 13, count 0 2006.285.21:07:53.80#ibcon#about to read 4, iclass 13, count 0 2006.285.21:07:53.80#ibcon#read 4, iclass 13, count 0 2006.285.21:07:53.80#ibcon#about to read 5, iclass 13, count 0 2006.285.21:07:53.80#ibcon#read 5, iclass 13, count 0 2006.285.21:07:53.80#ibcon#about to read 6, iclass 13, count 0 2006.285.21:07:53.80#ibcon#read 6, iclass 13, count 0 2006.285.21:07:53.80#ibcon#end of sib2, iclass 13, count 0 2006.285.21:07:53.80#ibcon#*mode == 0, iclass 13, count 0 2006.285.21:07:53.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.21:07:53.80#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:07:53.80#ibcon#*before write, iclass 13, count 0 2006.285.21:07:53.80#ibcon#enter sib2, iclass 13, count 0 2006.285.21:07:53.80#ibcon#flushed, iclass 13, count 0 2006.285.21:07:53.80#ibcon#about to write, iclass 13, count 0 2006.285.21:07:53.80#ibcon#wrote, iclass 13, count 0 2006.285.21:07:53.80#ibcon#about to read 3, iclass 13, count 0 2006.285.21:07:53.84#ibcon#read 3, iclass 13, count 0 2006.285.21:07:53.84#ibcon#about to read 4, iclass 13, count 0 2006.285.21:07:53.84#ibcon#read 4, iclass 13, count 0 2006.285.21:07:53.84#ibcon#about to read 5, iclass 13, count 0 2006.285.21:07:53.84#ibcon#read 5, iclass 13, count 0 2006.285.21:07:53.84#ibcon#about to read 6, iclass 13, count 0 2006.285.21:07:53.84#ibcon#read 6, iclass 13, count 0 2006.285.21:07:53.84#ibcon#end of sib2, iclass 13, count 0 2006.285.21:07:53.84#ibcon#*after write, iclass 13, count 0 2006.285.21:07:53.84#ibcon#*before return 0, iclass 13, count 0 2006.285.21:07:53.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:07:53.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:07:53.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.21:07:53.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.21:07:53.84$vck44/va=8,3 2006.285.21:07:53.84#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.21:07:53.84#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.21:07:53.84#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:53.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:07:53.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:07:53.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:07:53.90#ibcon#enter wrdev, iclass 15, count 2 2006.285.21:07:53.90#ibcon#first serial, iclass 15, count 2 2006.285.21:07:53.90#ibcon#enter sib2, iclass 15, count 2 2006.285.21:07:53.90#ibcon#flushed, iclass 15, count 2 2006.285.21:07:53.90#ibcon#about to write, iclass 15, count 2 2006.285.21:07:53.90#ibcon#wrote, iclass 15, count 2 2006.285.21:07:53.90#ibcon#about to read 3, iclass 15, count 2 2006.285.21:07:53.92#ibcon#read 3, iclass 15, count 2 2006.285.21:07:53.92#ibcon#about to read 4, iclass 15, count 2 2006.285.21:07:53.92#ibcon#read 4, iclass 15, count 2 2006.285.21:07:53.92#ibcon#about to read 5, iclass 15, count 2 2006.285.21:07:53.92#ibcon#read 5, iclass 15, count 2 2006.285.21:07:53.92#ibcon#about to read 6, iclass 15, count 2 2006.285.21:07:53.92#ibcon#read 6, iclass 15, count 2 2006.285.21:07:53.92#ibcon#end of sib2, iclass 15, count 2 2006.285.21:07:53.92#ibcon#*mode == 0, iclass 15, count 2 2006.285.21:07:53.92#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.21:07:53.92#ibcon#[25=AT08-03\r\n] 2006.285.21:07:53.92#ibcon#*before write, iclass 15, count 2 2006.285.21:07:53.92#ibcon#enter sib2, iclass 15, count 2 2006.285.21:07:53.92#ibcon#flushed, iclass 15, count 2 2006.285.21:07:53.92#ibcon#about to write, iclass 15, count 2 2006.285.21:07:53.92#ibcon#wrote, iclass 15, count 2 2006.285.21:07:53.92#ibcon#about to read 3, iclass 15, count 2 2006.285.21:07:53.95#ibcon#read 3, iclass 15, count 2 2006.285.21:07:53.95#ibcon#about to read 4, iclass 15, count 2 2006.285.21:07:53.95#ibcon#read 4, iclass 15, count 2 2006.285.21:07:53.95#ibcon#about to read 5, iclass 15, count 2 2006.285.21:07:53.95#ibcon#read 5, iclass 15, count 2 2006.285.21:07:53.95#ibcon#about to read 6, iclass 15, count 2 2006.285.21:07:53.95#ibcon#read 6, iclass 15, count 2 2006.285.21:07:53.95#ibcon#end of sib2, iclass 15, count 2 2006.285.21:07:53.95#ibcon#*after write, iclass 15, count 2 2006.285.21:07:53.95#ibcon#*before return 0, iclass 15, count 2 2006.285.21:07:53.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:07:53.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:07:53.95#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.21:07:53.95#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:53.95#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:07:54.07#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:07:54.07#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:07:54.07#ibcon#enter wrdev, iclass 15, count 0 2006.285.21:07:54.07#ibcon#first serial, iclass 15, count 0 2006.285.21:07:54.07#ibcon#enter sib2, iclass 15, count 0 2006.285.21:07:54.07#ibcon#flushed, iclass 15, count 0 2006.285.21:07:54.07#ibcon#about to write, iclass 15, count 0 2006.285.21:07:54.07#ibcon#wrote, iclass 15, count 0 2006.285.21:07:54.07#ibcon#about to read 3, iclass 15, count 0 2006.285.21:07:54.09#ibcon#read 3, iclass 15, count 0 2006.285.21:07:54.09#ibcon#about to read 4, iclass 15, count 0 2006.285.21:07:54.09#ibcon#read 4, iclass 15, count 0 2006.285.21:07:54.09#ibcon#about to read 5, iclass 15, count 0 2006.285.21:07:54.09#ibcon#read 5, iclass 15, count 0 2006.285.21:07:54.09#ibcon#about to read 6, iclass 15, count 0 2006.285.21:07:54.09#ibcon#read 6, iclass 15, count 0 2006.285.21:07:54.09#ibcon#end of sib2, iclass 15, count 0 2006.285.21:07:54.09#ibcon#*mode == 0, iclass 15, count 0 2006.285.21:07:54.09#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.21:07:54.09#ibcon#[25=USB\r\n] 2006.285.21:07:54.09#ibcon#*before write, iclass 15, count 0 2006.285.21:07:54.09#ibcon#enter sib2, iclass 15, count 0 2006.285.21:07:54.09#ibcon#flushed, iclass 15, count 0 2006.285.21:07:54.09#ibcon#about to write, iclass 15, count 0 2006.285.21:07:54.09#ibcon#wrote, iclass 15, count 0 2006.285.21:07:54.09#ibcon#about to read 3, iclass 15, count 0 2006.285.21:07:54.12#ibcon#read 3, iclass 15, count 0 2006.285.21:07:54.12#ibcon#about to read 4, iclass 15, count 0 2006.285.21:07:54.12#ibcon#read 4, iclass 15, count 0 2006.285.21:07:54.12#ibcon#about to read 5, iclass 15, count 0 2006.285.21:07:54.12#ibcon#read 5, iclass 15, count 0 2006.285.21:07:54.12#ibcon#about to read 6, iclass 15, count 0 2006.285.21:07:54.12#ibcon#read 6, iclass 15, count 0 2006.285.21:07:54.12#ibcon#end of sib2, iclass 15, count 0 2006.285.21:07:54.12#ibcon#*after write, iclass 15, count 0 2006.285.21:07:54.12#ibcon#*before return 0, iclass 15, count 0 2006.285.21:07:54.12#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:07:54.12#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:07:54.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.21:07:54.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.21:07:54.12$vck44/vblo=1,629.99 2006.285.21:07:54.12#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.21:07:54.12#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.21:07:54.12#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:54.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:07:54.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:07:54.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:07:54.12#ibcon#enter wrdev, iclass 17, count 0 2006.285.21:07:54.12#ibcon#first serial, iclass 17, count 0 2006.285.21:07:54.12#ibcon#enter sib2, iclass 17, count 0 2006.285.21:07:54.12#ibcon#flushed, iclass 17, count 0 2006.285.21:07:54.12#ibcon#about to write, iclass 17, count 0 2006.285.21:07:54.12#ibcon#wrote, iclass 17, count 0 2006.285.21:07:54.12#ibcon#about to read 3, iclass 17, count 0 2006.285.21:07:54.14#ibcon#read 3, iclass 17, count 0 2006.285.21:07:54.14#ibcon#about to read 4, iclass 17, count 0 2006.285.21:07:54.14#ibcon#read 4, iclass 17, count 0 2006.285.21:07:54.14#ibcon#about to read 5, iclass 17, count 0 2006.285.21:07:54.14#ibcon#read 5, iclass 17, count 0 2006.285.21:07:54.14#ibcon#about to read 6, iclass 17, count 0 2006.285.21:07:54.14#ibcon#read 6, iclass 17, count 0 2006.285.21:07:54.14#ibcon#end of sib2, iclass 17, count 0 2006.285.21:07:54.14#ibcon#*mode == 0, iclass 17, count 0 2006.285.21:07:54.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.21:07:54.14#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:07:54.14#ibcon#*before write, iclass 17, count 0 2006.285.21:07:54.14#ibcon#enter sib2, iclass 17, count 0 2006.285.21:07:54.14#ibcon#flushed, iclass 17, count 0 2006.285.21:07:54.14#ibcon#about to write, iclass 17, count 0 2006.285.21:07:54.14#ibcon#wrote, iclass 17, count 0 2006.285.21:07:54.14#ibcon#about to read 3, iclass 17, count 0 2006.285.21:07:54.18#ibcon#read 3, iclass 17, count 0 2006.285.21:07:54.18#ibcon#about to read 4, iclass 17, count 0 2006.285.21:07:54.18#ibcon#read 4, iclass 17, count 0 2006.285.21:07:54.18#ibcon#about to read 5, iclass 17, count 0 2006.285.21:07:54.18#ibcon#read 5, iclass 17, count 0 2006.285.21:07:54.18#ibcon#about to read 6, iclass 17, count 0 2006.285.21:07:54.18#ibcon#read 6, iclass 17, count 0 2006.285.21:07:54.18#ibcon#end of sib2, iclass 17, count 0 2006.285.21:07:54.18#ibcon#*after write, iclass 17, count 0 2006.285.21:07:54.18#ibcon#*before return 0, iclass 17, count 0 2006.285.21:07:54.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:07:54.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:07:54.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.21:07:54.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.21:07:54.18$vck44/vb=1,4 2006.285.21:07:54.18#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.21:07:54.18#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.21:07:54.18#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:54.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:07:54.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:07:54.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:07:54.18#ibcon#enter wrdev, iclass 19, count 2 2006.285.21:07:54.18#ibcon#first serial, iclass 19, count 2 2006.285.21:07:54.18#ibcon#enter sib2, iclass 19, count 2 2006.285.21:07:54.18#ibcon#flushed, iclass 19, count 2 2006.285.21:07:54.18#ibcon#about to write, iclass 19, count 2 2006.285.21:07:54.18#ibcon#wrote, iclass 19, count 2 2006.285.21:07:54.18#ibcon#about to read 3, iclass 19, count 2 2006.285.21:07:54.20#ibcon#read 3, iclass 19, count 2 2006.285.21:07:54.20#ibcon#about to read 4, iclass 19, count 2 2006.285.21:07:54.20#ibcon#read 4, iclass 19, count 2 2006.285.21:07:54.20#ibcon#about to read 5, iclass 19, count 2 2006.285.21:07:54.20#ibcon#read 5, iclass 19, count 2 2006.285.21:07:54.20#ibcon#about to read 6, iclass 19, count 2 2006.285.21:07:54.20#ibcon#read 6, iclass 19, count 2 2006.285.21:07:54.20#ibcon#end of sib2, iclass 19, count 2 2006.285.21:07:54.20#ibcon#*mode == 0, iclass 19, count 2 2006.285.21:07:54.20#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.21:07:54.20#ibcon#[27=AT01-04\r\n] 2006.285.21:07:54.20#ibcon#*before write, iclass 19, count 2 2006.285.21:07:54.20#ibcon#enter sib2, iclass 19, count 2 2006.285.21:07:54.20#ibcon#flushed, iclass 19, count 2 2006.285.21:07:54.20#ibcon#about to write, iclass 19, count 2 2006.285.21:07:54.20#ibcon#wrote, iclass 19, count 2 2006.285.21:07:54.20#ibcon#about to read 3, iclass 19, count 2 2006.285.21:07:54.23#ibcon#read 3, iclass 19, count 2 2006.285.21:07:54.23#ibcon#about to read 4, iclass 19, count 2 2006.285.21:07:54.23#ibcon#read 4, iclass 19, count 2 2006.285.21:07:54.23#ibcon#about to read 5, iclass 19, count 2 2006.285.21:07:54.23#ibcon#read 5, iclass 19, count 2 2006.285.21:07:54.23#ibcon#about to read 6, iclass 19, count 2 2006.285.21:07:54.23#ibcon#read 6, iclass 19, count 2 2006.285.21:07:54.23#ibcon#end of sib2, iclass 19, count 2 2006.285.21:07:54.23#ibcon#*after write, iclass 19, count 2 2006.285.21:07:54.23#ibcon#*before return 0, iclass 19, count 2 2006.285.21:07:54.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:07:54.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:07:54.23#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.21:07:54.23#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:54.23#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:07:54.35#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:07:54.35#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:07:54.35#ibcon#enter wrdev, iclass 19, count 0 2006.285.21:07:54.35#ibcon#first serial, iclass 19, count 0 2006.285.21:07:54.35#ibcon#enter sib2, iclass 19, count 0 2006.285.21:07:54.35#ibcon#flushed, iclass 19, count 0 2006.285.21:07:54.35#ibcon#about to write, iclass 19, count 0 2006.285.21:07:54.35#ibcon#wrote, iclass 19, count 0 2006.285.21:07:54.35#ibcon#about to read 3, iclass 19, count 0 2006.285.21:07:54.37#ibcon#read 3, iclass 19, count 0 2006.285.21:07:54.37#ibcon#about to read 4, iclass 19, count 0 2006.285.21:07:54.37#ibcon#read 4, iclass 19, count 0 2006.285.21:07:54.37#ibcon#about to read 5, iclass 19, count 0 2006.285.21:07:54.37#ibcon#read 5, iclass 19, count 0 2006.285.21:07:54.37#ibcon#about to read 6, iclass 19, count 0 2006.285.21:07:54.37#ibcon#read 6, iclass 19, count 0 2006.285.21:07:54.37#ibcon#end of sib2, iclass 19, count 0 2006.285.21:07:54.37#ibcon#*mode == 0, iclass 19, count 0 2006.285.21:07:54.37#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.21:07:54.37#ibcon#[27=USB\r\n] 2006.285.21:07:54.37#ibcon#*before write, iclass 19, count 0 2006.285.21:07:54.37#ibcon#enter sib2, iclass 19, count 0 2006.285.21:07:54.37#ibcon#flushed, iclass 19, count 0 2006.285.21:07:54.37#ibcon#about to write, iclass 19, count 0 2006.285.21:07:54.37#ibcon#wrote, iclass 19, count 0 2006.285.21:07:54.37#ibcon#about to read 3, iclass 19, count 0 2006.285.21:07:54.40#ibcon#read 3, iclass 19, count 0 2006.285.21:07:54.40#ibcon#about to read 4, iclass 19, count 0 2006.285.21:07:54.40#ibcon#read 4, iclass 19, count 0 2006.285.21:07:54.40#ibcon#about to read 5, iclass 19, count 0 2006.285.21:07:54.40#ibcon#read 5, iclass 19, count 0 2006.285.21:07:54.40#ibcon#about to read 6, iclass 19, count 0 2006.285.21:07:54.40#ibcon#read 6, iclass 19, count 0 2006.285.21:07:54.40#ibcon#end of sib2, iclass 19, count 0 2006.285.21:07:54.40#ibcon#*after write, iclass 19, count 0 2006.285.21:07:54.40#ibcon#*before return 0, iclass 19, count 0 2006.285.21:07:54.40#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:07:54.40#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:07:54.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.21:07:54.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.21:07:54.40$vck44/vblo=2,634.99 2006.285.21:07:54.40#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.21:07:54.40#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.21:07:54.40#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:54.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:07:54.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:07:54.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:07:54.40#ibcon#enter wrdev, iclass 21, count 0 2006.285.21:07:54.40#ibcon#first serial, iclass 21, count 0 2006.285.21:07:54.40#ibcon#enter sib2, iclass 21, count 0 2006.285.21:07:54.40#ibcon#flushed, iclass 21, count 0 2006.285.21:07:54.40#ibcon#about to write, iclass 21, count 0 2006.285.21:07:54.40#ibcon#wrote, iclass 21, count 0 2006.285.21:07:54.40#ibcon#about to read 3, iclass 21, count 0 2006.285.21:07:54.42#ibcon#read 3, iclass 21, count 0 2006.285.21:07:54.42#ibcon#about to read 4, iclass 21, count 0 2006.285.21:07:54.42#ibcon#read 4, iclass 21, count 0 2006.285.21:07:54.42#ibcon#about to read 5, iclass 21, count 0 2006.285.21:07:54.42#ibcon#read 5, iclass 21, count 0 2006.285.21:07:54.42#ibcon#about to read 6, iclass 21, count 0 2006.285.21:07:54.42#ibcon#read 6, iclass 21, count 0 2006.285.21:07:54.42#ibcon#end of sib2, iclass 21, count 0 2006.285.21:07:54.42#ibcon#*mode == 0, iclass 21, count 0 2006.285.21:07:54.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.21:07:54.42#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:07:54.42#ibcon#*before write, iclass 21, count 0 2006.285.21:07:54.42#ibcon#enter sib2, iclass 21, count 0 2006.285.21:07:54.42#ibcon#flushed, iclass 21, count 0 2006.285.21:07:54.42#ibcon#about to write, iclass 21, count 0 2006.285.21:07:54.42#ibcon#wrote, iclass 21, count 0 2006.285.21:07:54.42#ibcon#about to read 3, iclass 21, count 0 2006.285.21:07:54.46#ibcon#read 3, iclass 21, count 0 2006.285.21:07:54.46#ibcon#about to read 4, iclass 21, count 0 2006.285.21:07:54.46#ibcon#read 4, iclass 21, count 0 2006.285.21:07:54.46#ibcon#about to read 5, iclass 21, count 0 2006.285.21:07:54.46#ibcon#read 5, iclass 21, count 0 2006.285.21:07:54.46#ibcon#about to read 6, iclass 21, count 0 2006.285.21:07:54.46#ibcon#read 6, iclass 21, count 0 2006.285.21:07:54.46#ibcon#end of sib2, iclass 21, count 0 2006.285.21:07:54.46#ibcon#*after write, iclass 21, count 0 2006.285.21:07:54.46#ibcon#*before return 0, iclass 21, count 0 2006.285.21:07:54.46#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:07:54.46#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:07:54.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.21:07:54.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.21:07:54.46$vck44/vb=2,5 2006.285.21:07:54.46#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.21:07:54.46#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.21:07:54.46#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:54.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:07:54.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:07:54.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:07:54.52#ibcon#enter wrdev, iclass 23, count 2 2006.285.21:07:54.52#ibcon#first serial, iclass 23, count 2 2006.285.21:07:54.52#ibcon#enter sib2, iclass 23, count 2 2006.285.21:07:54.52#ibcon#flushed, iclass 23, count 2 2006.285.21:07:54.52#ibcon#about to write, iclass 23, count 2 2006.285.21:07:54.52#ibcon#wrote, iclass 23, count 2 2006.285.21:07:54.52#ibcon#about to read 3, iclass 23, count 2 2006.285.21:07:54.54#ibcon#read 3, iclass 23, count 2 2006.285.21:07:54.62#ibcon#about to read 4, iclass 23, count 2 2006.285.21:07:54.62#ibcon#read 4, iclass 23, count 2 2006.285.21:07:54.62#ibcon#about to read 5, iclass 23, count 2 2006.285.21:07:54.62#ibcon#read 5, iclass 23, count 2 2006.285.21:07:54.62#ibcon#about to read 6, iclass 23, count 2 2006.285.21:07:54.62#ibcon#read 6, iclass 23, count 2 2006.285.21:07:54.62#ibcon#end of sib2, iclass 23, count 2 2006.285.21:07:54.62#ibcon#*mode == 0, iclass 23, count 2 2006.285.21:07:54.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.21:07:54.62#ibcon#[27=AT02-05\r\n] 2006.285.21:07:54.62#ibcon#*before write, iclass 23, count 2 2006.285.21:07:54.62#ibcon#enter sib2, iclass 23, count 2 2006.285.21:07:54.62#ibcon#flushed, iclass 23, count 2 2006.285.21:07:54.62#ibcon#about to write, iclass 23, count 2 2006.285.21:07:54.62#ibcon#wrote, iclass 23, count 2 2006.285.21:07:54.62#ibcon#about to read 3, iclass 23, count 2 2006.285.21:07:54.66#ibcon#read 3, iclass 23, count 2 2006.285.21:07:54.66#ibcon#about to read 4, iclass 23, count 2 2006.285.21:07:54.66#ibcon#read 4, iclass 23, count 2 2006.285.21:07:54.66#ibcon#about to read 5, iclass 23, count 2 2006.285.21:07:54.66#ibcon#read 5, iclass 23, count 2 2006.285.21:07:54.66#ibcon#about to read 6, iclass 23, count 2 2006.285.21:07:54.66#ibcon#read 6, iclass 23, count 2 2006.285.21:07:54.66#ibcon#end of sib2, iclass 23, count 2 2006.285.21:07:54.66#ibcon#*after write, iclass 23, count 2 2006.285.21:07:54.66#ibcon#*before return 0, iclass 23, count 2 2006.285.21:07:54.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:07:54.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:07:54.66#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.21:07:54.66#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:54.66#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:07:54.78#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:07:54.78#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:07:54.78#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:07:54.78#ibcon#first serial, iclass 23, count 0 2006.285.21:07:54.78#ibcon#enter sib2, iclass 23, count 0 2006.285.21:07:54.78#ibcon#flushed, iclass 23, count 0 2006.285.21:07:54.78#ibcon#about to write, iclass 23, count 0 2006.285.21:07:54.78#ibcon#wrote, iclass 23, count 0 2006.285.21:07:54.78#ibcon#about to read 3, iclass 23, count 0 2006.285.21:07:54.80#ibcon#read 3, iclass 23, count 0 2006.285.21:07:54.80#ibcon#about to read 4, iclass 23, count 0 2006.285.21:07:54.80#ibcon#read 4, iclass 23, count 0 2006.285.21:07:54.80#ibcon#about to read 5, iclass 23, count 0 2006.285.21:07:54.80#ibcon#read 5, iclass 23, count 0 2006.285.21:07:54.80#ibcon#about to read 6, iclass 23, count 0 2006.285.21:07:54.80#ibcon#read 6, iclass 23, count 0 2006.285.21:07:54.80#ibcon#end of sib2, iclass 23, count 0 2006.285.21:07:54.80#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:07:54.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:07:54.80#ibcon#[27=USB\r\n] 2006.285.21:07:54.80#ibcon#*before write, iclass 23, count 0 2006.285.21:07:54.80#ibcon#enter sib2, iclass 23, count 0 2006.285.21:07:54.80#ibcon#flushed, iclass 23, count 0 2006.285.21:07:54.80#ibcon#about to write, iclass 23, count 0 2006.285.21:07:54.80#ibcon#wrote, iclass 23, count 0 2006.285.21:07:54.80#ibcon#about to read 3, iclass 23, count 0 2006.285.21:07:54.83#ibcon#read 3, iclass 23, count 0 2006.285.21:07:54.83#ibcon#about to read 4, iclass 23, count 0 2006.285.21:07:54.83#ibcon#read 4, iclass 23, count 0 2006.285.21:07:54.83#ibcon#about to read 5, iclass 23, count 0 2006.285.21:07:54.83#ibcon#read 5, iclass 23, count 0 2006.285.21:07:54.83#ibcon#about to read 6, iclass 23, count 0 2006.285.21:07:54.83#ibcon#read 6, iclass 23, count 0 2006.285.21:07:54.83#ibcon#end of sib2, iclass 23, count 0 2006.285.21:07:54.83#ibcon#*after write, iclass 23, count 0 2006.285.21:07:54.83#ibcon#*before return 0, iclass 23, count 0 2006.285.21:07:54.83#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:07:54.83#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:07:54.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:07:54.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:07:54.83$vck44/vblo=3,649.99 2006.285.21:07:54.83#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.21:07:54.83#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.21:07:54.83#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:54.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:07:54.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:07:54.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:07:54.83#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:07:54.83#ibcon#first serial, iclass 25, count 0 2006.285.21:07:54.83#ibcon#enter sib2, iclass 25, count 0 2006.285.21:07:54.83#ibcon#flushed, iclass 25, count 0 2006.285.21:07:54.83#ibcon#about to write, iclass 25, count 0 2006.285.21:07:54.83#ibcon#wrote, iclass 25, count 0 2006.285.21:07:54.83#ibcon#about to read 3, iclass 25, count 0 2006.285.21:07:54.85#ibcon#read 3, iclass 25, count 0 2006.285.21:07:54.85#ibcon#about to read 4, iclass 25, count 0 2006.285.21:07:54.85#ibcon#read 4, iclass 25, count 0 2006.285.21:07:54.85#ibcon#about to read 5, iclass 25, count 0 2006.285.21:07:54.85#ibcon#read 5, iclass 25, count 0 2006.285.21:07:54.85#ibcon#about to read 6, iclass 25, count 0 2006.285.21:07:54.85#ibcon#read 6, iclass 25, count 0 2006.285.21:07:54.85#ibcon#end of sib2, iclass 25, count 0 2006.285.21:07:54.85#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:07:54.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:07:54.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:07:54.85#ibcon#*before write, iclass 25, count 0 2006.285.21:07:54.85#ibcon#enter sib2, iclass 25, count 0 2006.285.21:07:54.85#ibcon#flushed, iclass 25, count 0 2006.285.21:07:54.85#ibcon#about to write, iclass 25, count 0 2006.285.21:07:54.85#ibcon#wrote, iclass 25, count 0 2006.285.21:07:54.85#ibcon#about to read 3, iclass 25, count 0 2006.285.21:07:54.89#ibcon#read 3, iclass 25, count 0 2006.285.21:07:54.89#ibcon#about to read 4, iclass 25, count 0 2006.285.21:07:54.89#ibcon#read 4, iclass 25, count 0 2006.285.21:07:54.89#ibcon#about to read 5, iclass 25, count 0 2006.285.21:07:54.89#ibcon#read 5, iclass 25, count 0 2006.285.21:07:54.89#ibcon#about to read 6, iclass 25, count 0 2006.285.21:07:54.89#ibcon#read 6, iclass 25, count 0 2006.285.21:07:54.89#ibcon#end of sib2, iclass 25, count 0 2006.285.21:07:54.89#ibcon#*after write, iclass 25, count 0 2006.285.21:07:54.89#ibcon#*before return 0, iclass 25, count 0 2006.285.21:07:54.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:07:54.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:07:54.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:07:54.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:07:54.89$vck44/vb=3,4 2006.285.21:07:54.89#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.21:07:54.89#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.21:07:54.89#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:54.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:07:54.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:07:54.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:07:54.95#ibcon#enter wrdev, iclass 27, count 2 2006.285.21:07:54.95#ibcon#first serial, iclass 27, count 2 2006.285.21:07:54.95#ibcon#enter sib2, iclass 27, count 2 2006.285.21:07:54.95#ibcon#flushed, iclass 27, count 2 2006.285.21:07:54.95#ibcon#about to write, iclass 27, count 2 2006.285.21:07:54.95#ibcon#wrote, iclass 27, count 2 2006.285.21:07:54.95#ibcon#about to read 3, iclass 27, count 2 2006.285.21:07:54.97#ibcon#read 3, iclass 27, count 2 2006.285.21:07:54.97#ibcon#about to read 4, iclass 27, count 2 2006.285.21:07:54.97#ibcon#read 4, iclass 27, count 2 2006.285.21:07:54.97#ibcon#about to read 5, iclass 27, count 2 2006.285.21:07:54.97#ibcon#read 5, iclass 27, count 2 2006.285.21:07:54.97#ibcon#about to read 6, iclass 27, count 2 2006.285.21:07:54.97#ibcon#read 6, iclass 27, count 2 2006.285.21:07:54.97#ibcon#end of sib2, iclass 27, count 2 2006.285.21:07:54.97#ibcon#*mode == 0, iclass 27, count 2 2006.285.21:07:54.97#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.21:07:54.97#ibcon#[27=AT03-04\r\n] 2006.285.21:07:54.97#ibcon#*before write, iclass 27, count 2 2006.285.21:07:54.97#ibcon#enter sib2, iclass 27, count 2 2006.285.21:07:54.97#ibcon#flushed, iclass 27, count 2 2006.285.21:07:54.97#ibcon#about to write, iclass 27, count 2 2006.285.21:07:54.97#ibcon#wrote, iclass 27, count 2 2006.285.21:07:54.97#ibcon#about to read 3, iclass 27, count 2 2006.285.21:07:55.00#ibcon#read 3, iclass 27, count 2 2006.285.21:07:55.00#ibcon#about to read 4, iclass 27, count 2 2006.285.21:07:55.00#ibcon#read 4, iclass 27, count 2 2006.285.21:07:55.00#ibcon#about to read 5, iclass 27, count 2 2006.285.21:07:55.00#ibcon#read 5, iclass 27, count 2 2006.285.21:07:55.00#ibcon#about to read 6, iclass 27, count 2 2006.285.21:07:55.00#ibcon#read 6, iclass 27, count 2 2006.285.21:07:55.00#ibcon#end of sib2, iclass 27, count 2 2006.285.21:07:55.00#ibcon#*after write, iclass 27, count 2 2006.285.21:07:55.00#ibcon#*before return 0, iclass 27, count 2 2006.285.21:07:55.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:07:55.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:07:55.00#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.21:07:55.00#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:55.00#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:07:55.12#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:07:55.12#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:07:55.12#ibcon#enter wrdev, iclass 27, count 0 2006.285.21:07:55.12#ibcon#first serial, iclass 27, count 0 2006.285.21:07:55.12#ibcon#enter sib2, iclass 27, count 0 2006.285.21:07:55.12#ibcon#flushed, iclass 27, count 0 2006.285.21:07:55.12#ibcon#about to write, iclass 27, count 0 2006.285.21:07:55.12#ibcon#wrote, iclass 27, count 0 2006.285.21:07:55.12#ibcon#about to read 3, iclass 27, count 0 2006.285.21:07:55.14#ibcon#read 3, iclass 27, count 0 2006.285.21:07:55.14#ibcon#about to read 4, iclass 27, count 0 2006.285.21:07:55.14#ibcon#read 4, iclass 27, count 0 2006.285.21:07:55.14#ibcon#about to read 5, iclass 27, count 0 2006.285.21:07:55.14#ibcon#read 5, iclass 27, count 0 2006.285.21:07:55.14#ibcon#about to read 6, iclass 27, count 0 2006.285.21:07:55.14#ibcon#read 6, iclass 27, count 0 2006.285.21:07:55.14#ibcon#end of sib2, iclass 27, count 0 2006.285.21:07:55.14#ibcon#*mode == 0, iclass 27, count 0 2006.285.21:07:55.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.21:07:55.14#ibcon#[27=USB\r\n] 2006.285.21:07:55.14#ibcon#*before write, iclass 27, count 0 2006.285.21:07:55.14#ibcon#enter sib2, iclass 27, count 0 2006.285.21:07:55.14#ibcon#flushed, iclass 27, count 0 2006.285.21:07:55.14#ibcon#about to write, iclass 27, count 0 2006.285.21:07:55.14#ibcon#wrote, iclass 27, count 0 2006.285.21:07:55.14#ibcon#about to read 3, iclass 27, count 0 2006.285.21:07:55.17#ibcon#read 3, iclass 27, count 0 2006.285.21:07:55.17#ibcon#about to read 4, iclass 27, count 0 2006.285.21:07:55.17#ibcon#read 4, iclass 27, count 0 2006.285.21:07:55.17#ibcon#about to read 5, iclass 27, count 0 2006.285.21:07:55.17#ibcon#read 5, iclass 27, count 0 2006.285.21:07:55.17#ibcon#about to read 6, iclass 27, count 0 2006.285.21:07:55.17#ibcon#read 6, iclass 27, count 0 2006.285.21:07:55.17#ibcon#end of sib2, iclass 27, count 0 2006.285.21:07:55.17#ibcon#*after write, iclass 27, count 0 2006.285.21:07:55.17#ibcon#*before return 0, iclass 27, count 0 2006.285.21:07:55.17#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:07:55.17#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:07:55.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.21:07:55.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.21:07:55.17$vck44/vblo=4,679.99 2006.285.21:07:55.17#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.21:07:55.17#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.21:07:55.17#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:55.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:07:55.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:07:55.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:07:55.17#ibcon#enter wrdev, iclass 29, count 0 2006.285.21:07:55.17#ibcon#first serial, iclass 29, count 0 2006.285.21:07:55.17#ibcon#enter sib2, iclass 29, count 0 2006.285.21:07:55.17#ibcon#flushed, iclass 29, count 0 2006.285.21:07:55.17#ibcon#about to write, iclass 29, count 0 2006.285.21:07:55.17#ibcon#wrote, iclass 29, count 0 2006.285.21:07:55.17#ibcon#about to read 3, iclass 29, count 0 2006.285.21:07:55.19#ibcon#read 3, iclass 29, count 0 2006.285.21:07:55.19#ibcon#about to read 4, iclass 29, count 0 2006.285.21:07:55.19#ibcon#read 4, iclass 29, count 0 2006.285.21:07:55.19#ibcon#about to read 5, iclass 29, count 0 2006.285.21:07:55.19#ibcon#read 5, iclass 29, count 0 2006.285.21:07:55.19#ibcon#about to read 6, iclass 29, count 0 2006.285.21:07:55.19#ibcon#read 6, iclass 29, count 0 2006.285.21:07:55.19#ibcon#end of sib2, iclass 29, count 0 2006.285.21:07:55.19#ibcon#*mode == 0, iclass 29, count 0 2006.285.21:07:55.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.21:07:55.19#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:07:55.19#ibcon#*before write, iclass 29, count 0 2006.285.21:07:55.19#ibcon#enter sib2, iclass 29, count 0 2006.285.21:07:55.19#ibcon#flushed, iclass 29, count 0 2006.285.21:07:55.19#ibcon#about to write, iclass 29, count 0 2006.285.21:07:55.19#ibcon#wrote, iclass 29, count 0 2006.285.21:07:55.19#ibcon#about to read 3, iclass 29, count 0 2006.285.21:07:55.23#ibcon#read 3, iclass 29, count 0 2006.285.21:07:55.23#ibcon#about to read 4, iclass 29, count 0 2006.285.21:07:55.23#ibcon#read 4, iclass 29, count 0 2006.285.21:07:55.23#ibcon#about to read 5, iclass 29, count 0 2006.285.21:07:55.23#ibcon#read 5, iclass 29, count 0 2006.285.21:07:55.23#ibcon#about to read 6, iclass 29, count 0 2006.285.21:07:55.23#ibcon#read 6, iclass 29, count 0 2006.285.21:07:55.23#ibcon#end of sib2, iclass 29, count 0 2006.285.21:07:55.23#ibcon#*after write, iclass 29, count 0 2006.285.21:07:55.23#ibcon#*before return 0, iclass 29, count 0 2006.285.21:07:55.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:07:55.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:07:55.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.21:07:55.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.21:07:55.23$vck44/vb=4,5 2006.285.21:07:55.23#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.21:07:55.23#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.21:07:55.23#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:55.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:07:55.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:07:55.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:07:55.29#ibcon#enter wrdev, iclass 31, count 2 2006.285.21:07:55.29#ibcon#first serial, iclass 31, count 2 2006.285.21:07:55.29#ibcon#enter sib2, iclass 31, count 2 2006.285.21:07:55.29#ibcon#flushed, iclass 31, count 2 2006.285.21:07:55.29#ibcon#about to write, iclass 31, count 2 2006.285.21:07:55.29#ibcon#wrote, iclass 31, count 2 2006.285.21:07:55.29#ibcon#about to read 3, iclass 31, count 2 2006.285.21:07:55.31#ibcon#read 3, iclass 31, count 2 2006.285.21:07:55.31#ibcon#about to read 4, iclass 31, count 2 2006.285.21:07:55.31#ibcon#read 4, iclass 31, count 2 2006.285.21:07:55.31#ibcon#about to read 5, iclass 31, count 2 2006.285.21:07:55.31#ibcon#read 5, iclass 31, count 2 2006.285.21:07:55.31#ibcon#about to read 6, iclass 31, count 2 2006.285.21:07:55.31#ibcon#read 6, iclass 31, count 2 2006.285.21:07:55.31#ibcon#end of sib2, iclass 31, count 2 2006.285.21:07:55.31#ibcon#*mode == 0, iclass 31, count 2 2006.285.21:07:55.31#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.21:07:55.31#ibcon#[27=AT04-05\r\n] 2006.285.21:07:55.31#ibcon#*before write, iclass 31, count 2 2006.285.21:07:55.31#ibcon#enter sib2, iclass 31, count 2 2006.285.21:07:55.31#ibcon#flushed, iclass 31, count 2 2006.285.21:07:55.31#ibcon#about to write, iclass 31, count 2 2006.285.21:07:55.31#ibcon#wrote, iclass 31, count 2 2006.285.21:07:55.31#ibcon#about to read 3, iclass 31, count 2 2006.285.21:07:55.34#ibcon#read 3, iclass 31, count 2 2006.285.21:07:55.34#ibcon#about to read 4, iclass 31, count 2 2006.285.21:07:55.34#ibcon#read 4, iclass 31, count 2 2006.285.21:07:55.34#ibcon#about to read 5, iclass 31, count 2 2006.285.21:07:55.34#ibcon#read 5, iclass 31, count 2 2006.285.21:07:55.34#ibcon#about to read 6, iclass 31, count 2 2006.285.21:07:55.34#ibcon#read 6, iclass 31, count 2 2006.285.21:07:55.34#ibcon#end of sib2, iclass 31, count 2 2006.285.21:07:55.34#ibcon#*after write, iclass 31, count 2 2006.285.21:07:55.34#ibcon#*before return 0, iclass 31, count 2 2006.285.21:07:55.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:07:55.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:07:55.34#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.21:07:55.34#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:55.34#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:07:55.46#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:07:55.46#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:07:55.46#ibcon#enter wrdev, iclass 31, count 0 2006.285.21:07:55.46#ibcon#first serial, iclass 31, count 0 2006.285.21:07:55.46#ibcon#enter sib2, iclass 31, count 0 2006.285.21:07:55.46#ibcon#flushed, iclass 31, count 0 2006.285.21:07:55.46#ibcon#about to write, iclass 31, count 0 2006.285.21:07:55.46#ibcon#wrote, iclass 31, count 0 2006.285.21:07:55.46#ibcon#about to read 3, iclass 31, count 0 2006.285.21:07:55.48#ibcon#read 3, iclass 31, count 0 2006.285.21:07:55.48#ibcon#about to read 4, iclass 31, count 0 2006.285.21:07:55.48#ibcon#read 4, iclass 31, count 0 2006.285.21:07:55.48#ibcon#about to read 5, iclass 31, count 0 2006.285.21:07:55.48#ibcon#read 5, iclass 31, count 0 2006.285.21:07:55.48#ibcon#about to read 6, iclass 31, count 0 2006.285.21:07:55.48#ibcon#read 6, iclass 31, count 0 2006.285.21:07:55.48#ibcon#end of sib2, iclass 31, count 0 2006.285.21:07:55.48#ibcon#*mode == 0, iclass 31, count 0 2006.285.21:07:55.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.21:07:55.48#ibcon#[27=USB\r\n] 2006.285.21:07:55.48#ibcon#*before write, iclass 31, count 0 2006.285.21:07:55.48#ibcon#enter sib2, iclass 31, count 0 2006.285.21:07:55.48#ibcon#flushed, iclass 31, count 0 2006.285.21:07:55.48#ibcon#about to write, iclass 31, count 0 2006.285.21:07:55.48#ibcon#wrote, iclass 31, count 0 2006.285.21:07:55.48#ibcon#about to read 3, iclass 31, count 0 2006.285.21:07:55.51#ibcon#read 3, iclass 31, count 0 2006.285.21:07:55.51#ibcon#about to read 4, iclass 31, count 0 2006.285.21:07:55.51#ibcon#read 4, iclass 31, count 0 2006.285.21:07:55.51#ibcon#about to read 5, iclass 31, count 0 2006.285.21:07:55.51#ibcon#read 5, iclass 31, count 0 2006.285.21:07:55.51#ibcon#about to read 6, iclass 31, count 0 2006.285.21:07:55.51#ibcon#read 6, iclass 31, count 0 2006.285.21:07:55.51#ibcon#end of sib2, iclass 31, count 0 2006.285.21:07:55.51#ibcon#*after write, iclass 31, count 0 2006.285.21:07:55.51#ibcon#*before return 0, iclass 31, count 0 2006.285.21:07:55.51#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:07:55.51#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:07:55.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.21:07:55.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.21:07:55.51$vck44/vblo=5,709.99 2006.285.21:07:55.51#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.21:07:55.51#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.21:07:55.51#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:55.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:07:55.51#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:07:55.51#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:07:55.51#ibcon#enter wrdev, iclass 33, count 0 2006.285.21:07:55.51#ibcon#first serial, iclass 33, count 0 2006.285.21:07:55.51#ibcon#enter sib2, iclass 33, count 0 2006.285.21:07:55.51#ibcon#flushed, iclass 33, count 0 2006.285.21:07:55.51#ibcon#about to write, iclass 33, count 0 2006.285.21:07:55.51#ibcon#wrote, iclass 33, count 0 2006.285.21:07:55.51#ibcon#about to read 3, iclass 33, count 0 2006.285.21:07:55.53#ibcon#read 3, iclass 33, count 0 2006.285.21:07:55.64#ibcon#about to read 4, iclass 33, count 0 2006.285.21:07:55.64#ibcon#read 4, iclass 33, count 0 2006.285.21:07:55.64#ibcon#about to read 5, iclass 33, count 0 2006.285.21:07:55.64#ibcon#read 5, iclass 33, count 0 2006.285.21:07:55.64#ibcon#about to read 6, iclass 33, count 0 2006.285.21:07:55.64#ibcon#read 6, iclass 33, count 0 2006.285.21:07:55.64#ibcon#end of sib2, iclass 33, count 0 2006.285.21:07:55.64#ibcon#*mode == 0, iclass 33, count 0 2006.285.21:07:55.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.21:07:55.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:07:55.64#ibcon#*before write, iclass 33, count 0 2006.285.21:07:55.64#ibcon#enter sib2, iclass 33, count 0 2006.285.21:07:55.64#ibcon#flushed, iclass 33, count 0 2006.285.21:07:55.64#ibcon#about to write, iclass 33, count 0 2006.285.21:07:55.64#ibcon#wrote, iclass 33, count 0 2006.285.21:07:55.64#ibcon#about to read 3, iclass 33, count 0 2006.285.21:07:55.69#ibcon#read 3, iclass 33, count 0 2006.285.21:07:55.69#ibcon#about to read 4, iclass 33, count 0 2006.285.21:07:55.69#ibcon#read 4, iclass 33, count 0 2006.285.21:07:55.69#ibcon#about to read 5, iclass 33, count 0 2006.285.21:07:55.69#ibcon#read 5, iclass 33, count 0 2006.285.21:07:55.69#ibcon#about to read 6, iclass 33, count 0 2006.285.21:07:55.69#ibcon#read 6, iclass 33, count 0 2006.285.21:07:55.69#ibcon#end of sib2, iclass 33, count 0 2006.285.21:07:55.69#ibcon#*after write, iclass 33, count 0 2006.285.21:07:55.69#ibcon#*before return 0, iclass 33, count 0 2006.285.21:07:55.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:07:55.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:07:55.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.21:07:55.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.21:07:55.69$vck44/vb=5,4 2006.285.21:07:55.69#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.21:07:55.69#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.21:07:55.69#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:55.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:07:55.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:07:55.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:07:55.69#ibcon#enter wrdev, iclass 35, count 2 2006.285.21:07:55.69#ibcon#first serial, iclass 35, count 2 2006.285.21:07:55.69#ibcon#enter sib2, iclass 35, count 2 2006.285.21:07:55.69#ibcon#flushed, iclass 35, count 2 2006.285.21:07:55.69#ibcon#about to write, iclass 35, count 2 2006.285.21:07:55.69#ibcon#wrote, iclass 35, count 2 2006.285.21:07:55.69#ibcon#about to read 3, iclass 35, count 2 2006.285.21:07:55.71#ibcon#read 3, iclass 35, count 2 2006.285.21:07:55.71#ibcon#about to read 4, iclass 35, count 2 2006.285.21:07:55.71#ibcon#read 4, iclass 35, count 2 2006.285.21:07:55.71#ibcon#about to read 5, iclass 35, count 2 2006.285.21:07:55.71#ibcon#read 5, iclass 35, count 2 2006.285.21:07:55.71#ibcon#about to read 6, iclass 35, count 2 2006.285.21:07:55.71#ibcon#read 6, iclass 35, count 2 2006.285.21:07:55.71#ibcon#end of sib2, iclass 35, count 2 2006.285.21:07:55.71#ibcon#*mode == 0, iclass 35, count 2 2006.285.21:07:55.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.21:07:55.71#ibcon#[27=AT05-04\r\n] 2006.285.21:07:55.71#ibcon#*before write, iclass 35, count 2 2006.285.21:07:55.71#ibcon#enter sib2, iclass 35, count 2 2006.285.21:07:55.71#ibcon#flushed, iclass 35, count 2 2006.285.21:07:55.71#ibcon#about to write, iclass 35, count 2 2006.285.21:07:55.71#ibcon#wrote, iclass 35, count 2 2006.285.21:07:55.71#ibcon#about to read 3, iclass 35, count 2 2006.285.21:07:55.74#ibcon#read 3, iclass 35, count 2 2006.285.21:07:55.74#ibcon#about to read 4, iclass 35, count 2 2006.285.21:07:55.74#ibcon#read 4, iclass 35, count 2 2006.285.21:07:55.74#ibcon#about to read 5, iclass 35, count 2 2006.285.21:07:55.74#ibcon#read 5, iclass 35, count 2 2006.285.21:07:55.74#ibcon#about to read 6, iclass 35, count 2 2006.285.21:07:55.74#ibcon#read 6, iclass 35, count 2 2006.285.21:07:55.74#ibcon#end of sib2, iclass 35, count 2 2006.285.21:07:55.74#ibcon#*after write, iclass 35, count 2 2006.285.21:07:55.74#ibcon#*before return 0, iclass 35, count 2 2006.285.21:07:55.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:07:55.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:07:55.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.21:07:55.74#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:55.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:07:55.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:07:55.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:07:55.86#ibcon#enter wrdev, iclass 35, count 0 2006.285.21:07:55.86#ibcon#first serial, iclass 35, count 0 2006.285.21:07:55.86#ibcon#enter sib2, iclass 35, count 0 2006.285.21:07:55.86#ibcon#flushed, iclass 35, count 0 2006.285.21:07:55.86#ibcon#about to write, iclass 35, count 0 2006.285.21:07:55.86#ibcon#wrote, iclass 35, count 0 2006.285.21:07:55.86#ibcon#about to read 3, iclass 35, count 0 2006.285.21:07:55.88#ibcon#read 3, iclass 35, count 0 2006.285.21:07:55.88#ibcon#about to read 4, iclass 35, count 0 2006.285.21:07:55.88#ibcon#read 4, iclass 35, count 0 2006.285.21:07:55.88#ibcon#about to read 5, iclass 35, count 0 2006.285.21:07:55.88#ibcon#read 5, iclass 35, count 0 2006.285.21:07:55.88#ibcon#about to read 6, iclass 35, count 0 2006.285.21:07:55.88#ibcon#read 6, iclass 35, count 0 2006.285.21:07:55.88#ibcon#end of sib2, iclass 35, count 0 2006.285.21:07:55.88#ibcon#*mode == 0, iclass 35, count 0 2006.285.21:07:55.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.21:07:55.88#ibcon#[27=USB\r\n] 2006.285.21:07:55.88#ibcon#*before write, iclass 35, count 0 2006.285.21:07:55.88#ibcon#enter sib2, iclass 35, count 0 2006.285.21:07:55.88#ibcon#flushed, iclass 35, count 0 2006.285.21:07:55.88#ibcon#about to write, iclass 35, count 0 2006.285.21:07:55.88#ibcon#wrote, iclass 35, count 0 2006.285.21:07:55.88#ibcon#about to read 3, iclass 35, count 0 2006.285.21:07:55.91#ibcon#read 3, iclass 35, count 0 2006.285.21:07:55.91#ibcon#about to read 4, iclass 35, count 0 2006.285.21:07:55.91#ibcon#read 4, iclass 35, count 0 2006.285.21:07:55.91#ibcon#about to read 5, iclass 35, count 0 2006.285.21:07:55.91#ibcon#read 5, iclass 35, count 0 2006.285.21:07:55.91#ibcon#about to read 6, iclass 35, count 0 2006.285.21:07:55.91#ibcon#read 6, iclass 35, count 0 2006.285.21:07:55.91#ibcon#end of sib2, iclass 35, count 0 2006.285.21:07:55.91#ibcon#*after write, iclass 35, count 0 2006.285.21:07:55.91#ibcon#*before return 0, iclass 35, count 0 2006.285.21:07:55.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:07:55.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:07:55.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.21:07:55.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.21:07:55.91$vck44/vblo=6,719.99 2006.285.21:07:55.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.21:07:55.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.21:07:55.91#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:55.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:07:55.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:07:55.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:07:55.91#ibcon#enter wrdev, iclass 37, count 0 2006.285.21:07:55.91#ibcon#first serial, iclass 37, count 0 2006.285.21:07:55.91#ibcon#enter sib2, iclass 37, count 0 2006.285.21:07:55.91#ibcon#flushed, iclass 37, count 0 2006.285.21:07:55.91#ibcon#about to write, iclass 37, count 0 2006.285.21:07:55.91#ibcon#wrote, iclass 37, count 0 2006.285.21:07:55.91#ibcon#about to read 3, iclass 37, count 0 2006.285.21:07:55.93#ibcon#read 3, iclass 37, count 0 2006.285.21:07:55.93#ibcon#about to read 4, iclass 37, count 0 2006.285.21:07:55.93#ibcon#read 4, iclass 37, count 0 2006.285.21:07:55.93#ibcon#about to read 5, iclass 37, count 0 2006.285.21:07:55.93#ibcon#read 5, iclass 37, count 0 2006.285.21:07:55.93#ibcon#about to read 6, iclass 37, count 0 2006.285.21:07:55.93#ibcon#read 6, iclass 37, count 0 2006.285.21:07:55.93#ibcon#end of sib2, iclass 37, count 0 2006.285.21:07:55.93#ibcon#*mode == 0, iclass 37, count 0 2006.285.21:07:55.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.21:07:55.93#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:07:55.93#ibcon#*before write, iclass 37, count 0 2006.285.21:07:55.93#ibcon#enter sib2, iclass 37, count 0 2006.285.21:07:55.93#ibcon#flushed, iclass 37, count 0 2006.285.21:07:55.93#ibcon#about to write, iclass 37, count 0 2006.285.21:07:55.93#ibcon#wrote, iclass 37, count 0 2006.285.21:07:55.93#ibcon#about to read 3, iclass 37, count 0 2006.285.21:07:55.97#ibcon#read 3, iclass 37, count 0 2006.285.21:07:55.97#ibcon#about to read 4, iclass 37, count 0 2006.285.21:07:55.97#ibcon#read 4, iclass 37, count 0 2006.285.21:07:55.97#ibcon#about to read 5, iclass 37, count 0 2006.285.21:07:55.97#ibcon#read 5, iclass 37, count 0 2006.285.21:07:55.97#ibcon#about to read 6, iclass 37, count 0 2006.285.21:07:55.97#ibcon#read 6, iclass 37, count 0 2006.285.21:07:55.97#ibcon#end of sib2, iclass 37, count 0 2006.285.21:07:55.97#ibcon#*after write, iclass 37, count 0 2006.285.21:07:55.97#ibcon#*before return 0, iclass 37, count 0 2006.285.21:07:55.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:07:55.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:07:55.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.21:07:55.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.21:07:55.97$vck44/vb=6,3 2006.285.21:07:55.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.21:07:55.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.21:07:55.97#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:55.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:07:56.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:07:56.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:07:56.03#ibcon#enter wrdev, iclass 39, count 2 2006.285.21:07:56.03#ibcon#first serial, iclass 39, count 2 2006.285.21:07:56.03#ibcon#enter sib2, iclass 39, count 2 2006.285.21:07:56.03#ibcon#flushed, iclass 39, count 2 2006.285.21:07:56.03#ibcon#about to write, iclass 39, count 2 2006.285.21:07:56.03#ibcon#wrote, iclass 39, count 2 2006.285.21:07:56.03#ibcon#about to read 3, iclass 39, count 2 2006.285.21:07:56.05#ibcon#read 3, iclass 39, count 2 2006.285.21:07:56.05#ibcon#about to read 4, iclass 39, count 2 2006.285.21:07:56.05#ibcon#read 4, iclass 39, count 2 2006.285.21:07:56.05#ibcon#about to read 5, iclass 39, count 2 2006.285.21:07:56.05#ibcon#read 5, iclass 39, count 2 2006.285.21:07:56.05#ibcon#about to read 6, iclass 39, count 2 2006.285.21:07:56.05#ibcon#read 6, iclass 39, count 2 2006.285.21:07:56.05#ibcon#end of sib2, iclass 39, count 2 2006.285.21:07:56.05#ibcon#*mode == 0, iclass 39, count 2 2006.285.21:07:56.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.21:07:56.05#ibcon#[27=AT06-03\r\n] 2006.285.21:07:56.05#ibcon#*before write, iclass 39, count 2 2006.285.21:07:56.05#ibcon#enter sib2, iclass 39, count 2 2006.285.21:07:56.05#ibcon#flushed, iclass 39, count 2 2006.285.21:07:56.05#ibcon#about to write, iclass 39, count 2 2006.285.21:07:56.05#ibcon#wrote, iclass 39, count 2 2006.285.21:07:56.05#ibcon#about to read 3, iclass 39, count 2 2006.285.21:07:56.08#ibcon#read 3, iclass 39, count 2 2006.285.21:07:56.08#ibcon#about to read 4, iclass 39, count 2 2006.285.21:07:56.08#ibcon#read 4, iclass 39, count 2 2006.285.21:07:56.08#ibcon#about to read 5, iclass 39, count 2 2006.285.21:07:56.08#ibcon#read 5, iclass 39, count 2 2006.285.21:07:56.08#ibcon#about to read 6, iclass 39, count 2 2006.285.21:07:56.08#ibcon#read 6, iclass 39, count 2 2006.285.21:07:56.08#ibcon#end of sib2, iclass 39, count 2 2006.285.21:07:56.08#ibcon#*after write, iclass 39, count 2 2006.285.21:07:56.08#ibcon#*before return 0, iclass 39, count 2 2006.285.21:07:56.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:07:56.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:07:56.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.21:07:56.08#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:56.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:07:56.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:07:56.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:07:56.20#ibcon#enter wrdev, iclass 39, count 0 2006.285.21:07:56.20#ibcon#first serial, iclass 39, count 0 2006.285.21:07:56.20#ibcon#enter sib2, iclass 39, count 0 2006.285.21:07:56.20#ibcon#flushed, iclass 39, count 0 2006.285.21:07:56.20#ibcon#about to write, iclass 39, count 0 2006.285.21:07:56.20#ibcon#wrote, iclass 39, count 0 2006.285.21:07:56.20#ibcon#about to read 3, iclass 39, count 0 2006.285.21:07:56.22#ibcon#read 3, iclass 39, count 0 2006.285.21:07:56.22#ibcon#about to read 4, iclass 39, count 0 2006.285.21:07:56.22#ibcon#read 4, iclass 39, count 0 2006.285.21:07:56.22#ibcon#about to read 5, iclass 39, count 0 2006.285.21:07:56.22#ibcon#read 5, iclass 39, count 0 2006.285.21:07:56.22#ibcon#about to read 6, iclass 39, count 0 2006.285.21:07:56.22#ibcon#read 6, iclass 39, count 0 2006.285.21:07:56.22#ibcon#end of sib2, iclass 39, count 0 2006.285.21:07:56.22#ibcon#*mode == 0, iclass 39, count 0 2006.285.21:07:56.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.21:07:56.22#ibcon#[27=USB\r\n] 2006.285.21:07:56.22#ibcon#*before write, iclass 39, count 0 2006.285.21:07:56.22#ibcon#enter sib2, iclass 39, count 0 2006.285.21:07:56.22#ibcon#flushed, iclass 39, count 0 2006.285.21:07:56.22#ibcon#about to write, iclass 39, count 0 2006.285.21:07:56.22#ibcon#wrote, iclass 39, count 0 2006.285.21:07:56.22#ibcon#about to read 3, iclass 39, count 0 2006.285.21:07:56.25#ibcon#read 3, iclass 39, count 0 2006.285.21:07:56.25#ibcon#about to read 4, iclass 39, count 0 2006.285.21:07:56.25#ibcon#read 4, iclass 39, count 0 2006.285.21:07:56.25#ibcon#about to read 5, iclass 39, count 0 2006.285.21:07:56.25#ibcon#read 5, iclass 39, count 0 2006.285.21:07:56.25#ibcon#about to read 6, iclass 39, count 0 2006.285.21:07:56.25#ibcon#read 6, iclass 39, count 0 2006.285.21:07:56.25#ibcon#end of sib2, iclass 39, count 0 2006.285.21:07:56.25#ibcon#*after write, iclass 39, count 0 2006.285.21:07:56.25#ibcon#*before return 0, iclass 39, count 0 2006.285.21:07:56.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:07:56.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:07:56.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.21:07:56.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.21:07:56.25$vck44/vblo=7,734.99 2006.285.21:07:56.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.21:07:56.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.21:07:56.25#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:56.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:07:56.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:07:56.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:07:56.25#ibcon#enter wrdev, iclass 3, count 0 2006.285.21:07:56.25#ibcon#first serial, iclass 3, count 0 2006.285.21:07:56.25#ibcon#enter sib2, iclass 3, count 0 2006.285.21:07:56.25#ibcon#flushed, iclass 3, count 0 2006.285.21:07:56.25#ibcon#about to write, iclass 3, count 0 2006.285.21:07:56.25#ibcon#wrote, iclass 3, count 0 2006.285.21:07:56.25#ibcon#about to read 3, iclass 3, count 0 2006.285.21:07:56.27#ibcon#read 3, iclass 3, count 0 2006.285.21:07:56.27#ibcon#about to read 4, iclass 3, count 0 2006.285.21:07:56.27#ibcon#read 4, iclass 3, count 0 2006.285.21:07:56.27#ibcon#about to read 5, iclass 3, count 0 2006.285.21:07:56.27#ibcon#read 5, iclass 3, count 0 2006.285.21:07:56.27#ibcon#about to read 6, iclass 3, count 0 2006.285.21:07:56.27#ibcon#read 6, iclass 3, count 0 2006.285.21:07:56.27#ibcon#end of sib2, iclass 3, count 0 2006.285.21:07:56.27#ibcon#*mode == 0, iclass 3, count 0 2006.285.21:07:56.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.21:07:56.27#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:07:56.27#ibcon#*before write, iclass 3, count 0 2006.285.21:07:56.27#ibcon#enter sib2, iclass 3, count 0 2006.285.21:07:56.27#ibcon#flushed, iclass 3, count 0 2006.285.21:07:56.27#ibcon#about to write, iclass 3, count 0 2006.285.21:07:56.27#ibcon#wrote, iclass 3, count 0 2006.285.21:07:56.27#ibcon#about to read 3, iclass 3, count 0 2006.285.21:07:56.31#ibcon#read 3, iclass 3, count 0 2006.285.21:07:56.31#ibcon#about to read 4, iclass 3, count 0 2006.285.21:07:56.31#ibcon#read 4, iclass 3, count 0 2006.285.21:07:56.31#ibcon#about to read 5, iclass 3, count 0 2006.285.21:07:56.31#ibcon#read 5, iclass 3, count 0 2006.285.21:07:56.31#ibcon#about to read 6, iclass 3, count 0 2006.285.21:07:56.31#ibcon#read 6, iclass 3, count 0 2006.285.21:07:56.31#ibcon#end of sib2, iclass 3, count 0 2006.285.21:07:56.31#ibcon#*after write, iclass 3, count 0 2006.285.21:07:56.31#ibcon#*before return 0, iclass 3, count 0 2006.285.21:07:56.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:07:56.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:07:56.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.21:07:56.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.21:07:56.31$vck44/vb=7,4 2006.285.21:07:56.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.21:07:56.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.21:07:56.31#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:56.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:07:56.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:07:56.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:07:56.37#ibcon#enter wrdev, iclass 5, count 2 2006.285.21:07:56.37#ibcon#first serial, iclass 5, count 2 2006.285.21:07:56.37#ibcon#enter sib2, iclass 5, count 2 2006.285.21:07:56.37#ibcon#flushed, iclass 5, count 2 2006.285.21:07:56.37#ibcon#about to write, iclass 5, count 2 2006.285.21:07:56.37#ibcon#wrote, iclass 5, count 2 2006.285.21:07:56.37#ibcon#about to read 3, iclass 5, count 2 2006.285.21:07:56.39#ibcon#read 3, iclass 5, count 2 2006.285.21:07:56.39#ibcon#about to read 4, iclass 5, count 2 2006.285.21:07:56.39#ibcon#read 4, iclass 5, count 2 2006.285.21:07:56.39#ibcon#about to read 5, iclass 5, count 2 2006.285.21:07:56.39#ibcon#read 5, iclass 5, count 2 2006.285.21:07:56.39#ibcon#about to read 6, iclass 5, count 2 2006.285.21:07:56.39#ibcon#read 6, iclass 5, count 2 2006.285.21:07:56.39#ibcon#end of sib2, iclass 5, count 2 2006.285.21:07:56.39#ibcon#*mode == 0, iclass 5, count 2 2006.285.21:07:56.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.21:07:56.39#ibcon#[27=AT07-04\r\n] 2006.285.21:07:56.39#ibcon#*before write, iclass 5, count 2 2006.285.21:07:56.39#ibcon#enter sib2, iclass 5, count 2 2006.285.21:07:56.39#ibcon#flushed, iclass 5, count 2 2006.285.21:07:56.39#ibcon#about to write, iclass 5, count 2 2006.285.21:07:56.39#ibcon#wrote, iclass 5, count 2 2006.285.21:07:56.39#ibcon#about to read 3, iclass 5, count 2 2006.285.21:07:56.42#ibcon#read 3, iclass 5, count 2 2006.285.21:07:56.42#ibcon#about to read 4, iclass 5, count 2 2006.285.21:07:56.42#ibcon#read 4, iclass 5, count 2 2006.285.21:07:56.42#ibcon#about to read 5, iclass 5, count 2 2006.285.21:07:56.42#ibcon#read 5, iclass 5, count 2 2006.285.21:07:56.42#ibcon#about to read 6, iclass 5, count 2 2006.285.21:07:56.42#ibcon#read 6, iclass 5, count 2 2006.285.21:07:56.42#ibcon#end of sib2, iclass 5, count 2 2006.285.21:07:56.42#ibcon#*after write, iclass 5, count 2 2006.285.21:07:56.42#ibcon#*before return 0, iclass 5, count 2 2006.285.21:07:56.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:07:56.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:07:56.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.21:07:56.42#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:56.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:07:56.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:07:56.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:07:56.54#ibcon#enter wrdev, iclass 5, count 0 2006.285.21:07:56.54#ibcon#first serial, iclass 5, count 0 2006.285.21:07:56.54#ibcon#enter sib2, iclass 5, count 0 2006.285.21:07:56.54#ibcon#flushed, iclass 5, count 0 2006.285.21:07:56.54#ibcon#about to write, iclass 5, count 0 2006.285.21:07:56.54#ibcon#wrote, iclass 5, count 0 2006.285.21:07:56.54#ibcon#about to read 3, iclass 5, count 0 2006.285.21:07:56.56#ibcon#read 3, iclass 5, count 0 2006.285.21:07:56.56#ibcon#about to read 4, iclass 5, count 0 2006.285.21:07:56.56#ibcon#read 4, iclass 5, count 0 2006.285.21:07:56.56#ibcon#about to read 5, iclass 5, count 0 2006.285.21:07:56.56#ibcon#read 5, iclass 5, count 0 2006.285.21:07:56.56#ibcon#about to read 6, iclass 5, count 0 2006.285.21:07:56.56#ibcon#read 6, iclass 5, count 0 2006.285.21:07:56.56#ibcon#end of sib2, iclass 5, count 0 2006.285.21:07:56.56#ibcon#*mode == 0, iclass 5, count 0 2006.285.21:07:56.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.21:07:56.56#ibcon#[27=USB\r\n] 2006.285.21:07:56.56#ibcon#*before write, iclass 5, count 0 2006.285.21:07:56.56#ibcon#enter sib2, iclass 5, count 0 2006.285.21:07:56.56#ibcon#flushed, iclass 5, count 0 2006.285.21:07:56.56#ibcon#about to write, iclass 5, count 0 2006.285.21:07:56.56#ibcon#wrote, iclass 5, count 0 2006.285.21:07:56.56#ibcon#about to read 3, iclass 5, count 0 2006.285.21:07:56.59#ibcon#read 3, iclass 5, count 0 2006.285.21:07:56.59#ibcon#about to read 4, iclass 5, count 0 2006.285.21:07:56.59#ibcon#read 4, iclass 5, count 0 2006.285.21:07:56.59#ibcon#about to read 5, iclass 5, count 0 2006.285.21:07:56.59#ibcon#read 5, iclass 5, count 0 2006.285.21:07:56.59#ibcon#about to read 6, iclass 5, count 0 2006.285.21:07:56.59#ibcon#read 6, iclass 5, count 0 2006.285.21:07:56.59#ibcon#end of sib2, iclass 5, count 0 2006.285.21:07:56.59#ibcon#*after write, iclass 5, count 0 2006.285.21:07:56.59#ibcon#*before return 0, iclass 5, count 0 2006.285.21:07:56.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:07:56.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:07:56.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.21:07:56.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.21:07:56.59$vck44/vblo=8,744.99 2006.285.21:07:56.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.21:07:56.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.21:07:56.59#ibcon#ireg 17 cls_cnt 0 2006.285.21:07:56.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:07:56.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:07:56.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:07:56.59#ibcon#enter wrdev, iclass 7, count 0 2006.285.21:07:56.59#ibcon#first serial, iclass 7, count 0 2006.285.21:07:56.59#ibcon#enter sib2, iclass 7, count 0 2006.285.21:07:56.59#ibcon#flushed, iclass 7, count 0 2006.285.21:07:56.59#ibcon#about to write, iclass 7, count 0 2006.285.21:07:56.59#ibcon#wrote, iclass 7, count 0 2006.285.21:07:56.59#ibcon#about to read 3, iclass 7, count 0 2006.285.21:07:56.61#ibcon#read 3, iclass 7, count 0 2006.285.21:07:56.66#ibcon#about to read 4, iclass 7, count 0 2006.285.21:07:56.66#ibcon#read 4, iclass 7, count 0 2006.285.21:07:56.66#ibcon#about to read 5, iclass 7, count 0 2006.285.21:07:56.66#ibcon#read 5, iclass 7, count 0 2006.285.21:07:56.66#ibcon#about to read 6, iclass 7, count 0 2006.285.21:07:56.66#ibcon#read 6, iclass 7, count 0 2006.285.21:07:56.66#ibcon#end of sib2, iclass 7, count 0 2006.285.21:07:56.66#ibcon#*mode == 0, iclass 7, count 0 2006.285.21:07:56.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.21:07:56.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:07:56.66#ibcon#*before write, iclass 7, count 0 2006.285.21:07:56.66#ibcon#enter sib2, iclass 7, count 0 2006.285.21:07:56.66#ibcon#flushed, iclass 7, count 0 2006.285.21:07:56.66#ibcon#about to write, iclass 7, count 0 2006.285.21:07:56.66#ibcon#wrote, iclass 7, count 0 2006.285.21:07:56.66#ibcon#about to read 3, iclass 7, count 0 2006.285.21:07:56.70#ibcon#read 3, iclass 7, count 0 2006.285.21:07:56.70#ibcon#about to read 4, iclass 7, count 0 2006.285.21:07:56.70#ibcon#read 4, iclass 7, count 0 2006.285.21:07:56.70#ibcon#about to read 5, iclass 7, count 0 2006.285.21:07:56.70#ibcon#read 5, iclass 7, count 0 2006.285.21:07:56.70#ibcon#about to read 6, iclass 7, count 0 2006.285.21:07:56.70#ibcon#read 6, iclass 7, count 0 2006.285.21:07:56.70#ibcon#end of sib2, iclass 7, count 0 2006.285.21:07:56.70#ibcon#*after write, iclass 7, count 0 2006.285.21:07:56.70#ibcon#*before return 0, iclass 7, count 0 2006.285.21:07:56.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:07:56.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:07:56.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.21:07:56.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.21:07:56.70$vck44/vb=8,4 2006.285.21:07:56.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.21:07:56.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.21:07:56.70#ibcon#ireg 11 cls_cnt 2 2006.285.21:07:56.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:07:56.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:07:56.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:07:56.70#ibcon#enter wrdev, iclass 11, count 2 2006.285.21:07:56.70#ibcon#first serial, iclass 11, count 2 2006.285.21:07:56.70#ibcon#enter sib2, iclass 11, count 2 2006.285.21:07:56.70#ibcon#flushed, iclass 11, count 2 2006.285.21:07:56.70#ibcon#about to write, iclass 11, count 2 2006.285.21:07:56.70#ibcon#wrote, iclass 11, count 2 2006.285.21:07:56.70#ibcon#about to read 3, iclass 11, count 2 2006.285.21:07:56.72#ibcon#read 3, iclass 11, count 2 2006.285.21:07:56.72#ibcon#about to read 4, iclass 11, count 2 2006.285.21:07:56.72#ibcon#read 4, iclass 11, count 2 2006.285.21:07:56.72#ibcon#about to read 5, iclass 11, count 2 2006.285.21:07:56.72#ibcon#read 5, iclass 11, count 2 2006.285.21:07:56.72#ibcon#about to read 6, iclass 11, count 2 2006.285.21:07:56.72#ibcon#read 6, iclass 11, count 2 2006.285.21:07:56.72#ibcon#end of sib2, iclass 11, count 2 2006.285.21:07:56.72#ibcon#*mode == 0, iclass 11, count 2 2006.285.21:07:56.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.21:07:56.72#ibcon#[27=AT08-04\r\n] 2006.285.21:07:56.72#ibcon#*before write, iclass 11, count 2 2006.285.21:07:56.72#ibcon#enter sib2, iclass 11, count 2 2006.285.21:07:56.72#ibcon#flushed, iclass 11, count 2 2006.285.21:07:56.72#ibcon#about to write, iclass 11, count 2 2006.285.21:07:56.72#ibcon#wrote, iclass 11, count 2 2006.285.21:07:56.72#ibcon#about to read 3, iclass 11, count 2 2006.285.21:07:56.75#ibcon#read 3, iclass 11, count 2 2006.285.21:07:56.75#ibcon#about to read 4, iclass 11, count 2 2006.285.21:07:56.75#ibcon#read 4, iclass 11, count 2 2006.285.21:07:56.75#ibcon#about to read 5, iclass 11, count 2 2006.285.21:07:56.75#ibcon#read 5, iclass 11, count 2 2006.285.21:07:56.75#ibcon#about to read 6, iclass 11, count 2 2006.285.21:07:56.75#ibcon#read 6, iclass 11, count 2 2006.285.21:07:56.75#ibcon#end of sib2, iclass 11, count 2 2006.285.21:07:56.75#ibcon#*after write, iclass 11, count 2 2006.285.21:07:56.75#ibcon#*before return 0, iclass 11, count 2 2006.285.21:07:56.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:07:56.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:07:56.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.21:07:56.75#ibcon#ireg 7 cls_cnt 0 2006.285.21:07:56.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:07:56.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:07:56.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:07:56.87#ibcon#enter wrdev, iclass 11, count 0 2006.285.21:07:56.87#ibcon#first serial, iclass 11, count 0 2006.285.21:07:56.87#ibcon#enter sib2, iclass 11, count 0 2006.285.21:07:56.87#ibcon#flushed, iclass 11, count 0 2006.285.21:07:56.87#ibcon#about to write, iclass 11, count 0 2006.285.21:07:56.87#ibcon#wrote, iclass 11, count 0 2006.285.21:07:56.87#ibcon#about to read 3, iclass 11, count 0 2006.285.21:07:56.89#ibcon#read 3, iclass 11, count 0 2006.285.21:07:56.89#ibcon#about to read 4, iclass 11, count 0 2006.285.21:07:56.89#ibcon#read 4, iclass 11, count 0 2006.285.21:07:56.89#ibcon#about to read 5, iclass 11, count 0 2006.285.21:07:56.89#ibcon#read 5, iclass 11, count 0 2006.285.21:07:56.89#ibcon#about to read 6, iclass 11, count 0 2006.285.21:07:56.89#ibcon#read 6, iclass 11, count 0 2006.285.21:07:56.89#ibcon#end of sib2, iclass 11, count 0 2006.285.21:07:56.89#ibcon#*mode == 0, iclass 11, count 0 2006.285.21:07:56.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.21:07:56.89#ibcon#[27=USB\r\n] 2006.285.21:07:56.89#ibcon#*before write, iclass 11, count 0 2006.285.21:07:56.89#ibcon#enter sib2, iclass 11, count 0 2006.285.21:07:56.89#ibcon#flushed, iclass 11, count 0 2006.285.21:07:56.89#ibcon#about to write, iclass 11, count 0 2006.285.21:07:56.89#ibcon#wrote, iclass 11, count 0 2006.285.21:07:56.89#ibcon#about to read 3, iclass 11, count 0 2006.285.21:07:56.92#ibcon#read 3, iclass 11, count 0 2006.285.21:07:56.92#ibcon#about to read 4, iclass 11, count 0 2006.285.21:07:56.92#ibcon#read 4, iclass 11, count 0 2006.285.21:07:56.92#ibcon#about to read 5, iclass 11, count 0 2006.285.21:07:56.92#ibcon#read 5, iclass 11, count 0 2006.285.21:07:56.92#ibcon#about to read 6, iclass 11, count 0 2006.285.21:07:56.92#ibcon#read 6, iclass 11, count 0 2006.285.21:07:56.92#ibcon#end of sib2, iclass 11, count 0 2006.285.21:07:56.92#ibcon#*after write, iclass 11, count 0 2006.285.21:07:56.92#ibcon#*before return 0, iclass 11, count 0 2006.285.21:07:56.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:07:56.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:07:56.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.21:07:56.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.21:07:56.92$vck44/vabw=wide 2006.285.21:07:56.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.21:07:56.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.21:07:56.92#ibcon#ireg 8 cls_cnt 0 2006.285.21:07:56.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:07:56.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:07:56.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:07:56.92#ibcon#enter wrdev, iclass 13, count 0 2006.285.21:07:56.92#ibcon#first serial, iclass 13, count 0 2006.285.21:07:56.92#ibcon#enter sib2, iclass 13, count 0 2006.285.21:07:56.92#ibcon#flushed, iclass 13, count 0 2006.285.21:07:56.92#ibcon#about to write, iclass 13, count 0 2006.285.21:07:56.92#ibcon#wrote, iclass 13, count 0 2006.285.21:07:56.92#ibcon#about to read 3, iclass 13, count 0 2006.285.21:07:56.94#ibcon#read 3, iclass 13, count 0 2006.285.21:07:56.94#ibcon#about to read 4, iclass 13, count 0 2006.285.21:07:56.94#ibcon#read 4, iclass 13, count 0 2006.285.21:07:56.94#ibcon#about to read 5, iclass 13, count 0 2006.285.21:07:56.94#ibcon#read 5, iclass 13, count 0 2006.285.21:07:56.94#ibcon#about to read 6, iclass 13, count 0 2006.285.21:07:56.94#ibcon#read 6, iclass 13, count 0 2006.285.21:07:56.94#ibcon#end of sib2, iclass 13, count 0 2006.285.21:07:56.94#ibcon#*mode == 0, iclass 13, count 0 2006.285.21:07:56.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.21:07:56.94#ibcon#[25=BW32\r\n] 2006.285.21:07:56.94#ibcon#*before write, iclass 13, count 0 2006.285.21:07:56.94#ibcon#enter sib2, iclass 13, count 0 2006.285.21:07:56.94#ibcon#flushed, iclass 13, count 0 2006.285.21:07:56.94#ibcon#about to write, iclass 13, count 0 2006.285.21:07:56.94#ibcon#wrote, iclass 13, count 0 2006.285.21:07:56.94#ibcon#about to read 3, iclass 13, count 0 2006.285.21:07:56.97#ibcon#read 3, iclass 13, count 0 2006.285.21:07:56.97#ibcon#about to read 4, iclass 13, count 0 2006.285.21:07:56.97#ibcon#read 4, iclass 13, count 0 2006.285.21:07:56.97#ibcon#about to read 5, iclass 13, count 0 2006.285.21:07:56.97#ibcon#read 5, iclass 13, count 0 2006.285.21:07:56.97#ibcon#about to read 6, iclass 13, count 0 2006.285.21:07:56.97#ibcon#read 6, iclass 13, count 0 2006.285.21:07:56.97#ibcon#end of sib2, iclass 13, count 0 2006.285.21:07:56.97#ibcon#*after write, iclass 13, count 0 2006.285.21:07:56.97#ibcon#*before return 0, iclass 13, count 0 2006.285.21:07:56.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:07:56.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:07:56.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.21:07:56.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.21:07:56.97$vck44/vbbw=wide 2006.285.21:07:56.97#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.21:07:56.97#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.21:07:56.97#ibcon#ireg 8 cls_cnt 0 2006.285.21:07:56.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:07:57.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:07:57.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:07:57.04#ibcon#enter wrdev, iclass 15, count 0 2006.285.21:07:57.04#ibcon#first serial, iclass 15, count 0 2006.285.21:07:57.04#ibcon#enter sib2, iclass 15, count 0 2006.285.21:07:57.04#ibcon#flushed, iclass 15, count 0 2006.285.21:07:57.04#ibcon#about to write, iclass 15, count 0 2006.285.21:07:57.04#ibcon#wrote, iclass 15, count 0 2006.285.21:07:57.04#ibcon#about to read 3, iclass 15, count 0 2006.285.21:07:57.06#ibcon#read 3, iclass 15, count 0 2006.285.21:07:57.06#ibcon#about to read 4, iclass 15, count 0 2006.285.21:07:57.06#ibcon#read 4, iclass 15, count 0 2006.285.21:07:57.06#ibcon#about to read 5, iclass 15, count 0 2006.285.21:07:57.06#ibcon#read 5, iclass 15, count 0 2006.285.21:07:57.06#ibcon#about to read 6, iclass 15, count 0 2006.285.21:07:57.06#ibcon#read 6, iclass 15, count 0 2006.285.21:07:57.06#ibcon#end of sib2, iclass 15, count 0 2006.285.21:07:57.06#ibcon#*mode == 0, iclass 15, count 0 2006.285.21:07:57.06#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.21:07:57.06#ibcon#[27=BW32\r\n] 2006.285.21:07:57.06#ibcon#*before write, iclass 15, count 0 2006.285.21:07:57.06#ibcon#enter sib2, iclass 15, count 0 2006.285.21:07:57.06#ibcon#flushed, iclass 15, count 0 2006.285.21:07:57.06#ibcon#about to write, iclass 15, count 0 2006.285.21:07:57.06#ibcon#wrote, iclass 15, count 0 2006.285.21:07:57.06#ibcon#about to read 3, iclass 15, count 0 2006.285.21:07:57.09#ibcon#read 3, iclass 15, count 0 2006.285.21:07:57.09#ibcon#about to read 4, iclass 15, count 0 2006.285.21:07:57.09#ibcon#read 4, iclass 15, count 0 2006.285.21:07:57.09#ibcon#about to read 5, iclass 15, count 0 2006.285.21:07:57.09#ibcon#read 5, iclass 15, count 0 2006.285.21:07:57.09#ibcon#about to read 6, iclass 15, count 0 2006.285.21:07:57.09#ibcon#read 6, iclass 15, count 0 2006.285.21:07:57.09#ibcon#end of sib2, iclass 15, count 0 2006.285.21:07:57.09#ibcon#*after write, iclass 15, count 0 2006.285.21:07:57.09#ibcon#*before return 0, iclass 15, count 0 2006.285.21:07:57.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:07:57.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:07:57.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.21:07:57.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.21:07:57.09$setupk4/ifdk4 2006.285.21:07:57.09$ifdk4/lo= 2006.285.21:07:57.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:07:57.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:07:57.09$ifdk4/patch= 2006.285.21:07:57.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:07:57.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:07:57.09$setupk4/!*+20s 2006.285.21:08:00.81#abcon#<5=/00 0.2 0.7 14.221001015.5\r\n> 2006.285.21:08:00.83#abcon#{5=INTERFACE CLEAR} 2006.285.21:08:00.89#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:08:10.87$setupk4/"tpicd 2006.285.21:08:10.87$setupk4/echo=off 2006.285.21:08:10.87$setupk4/xlog=off 2006.285.21:08:10.87:!2006.285.21:08:42 2006.285.21:08:11.13#trakl#Source acquired 2006.285.21:08:12.13#flagr#flagr/antenna,acquired 2006.285.21:08:42.00:preob 2006.285.21:08:43.13/onsource/TRACKING 2006.285.21:08:43.13:!2006.285.21:08:52 2006.285.21:08:52.00:"tape 2006.285.21:08:52.00:"st=record 2006.285.21:08:52.00:data_valid=on 2006.285.21:08:52.00:midob 2006.285.21:08:52.13/onsource/TRACKING 2006.285.21:08:52.13/wx/14.23,1015.6,100 2006.285.21:08:52.20/cable/+6.5106E-03 2006.285.21:08:53.29/va/01,07,usb,yes,34,37 2006.285.21:08:53.29/va/02,06,usb,yes,34,35 2006.285.21:08:53.29/va/03,07,usb,yes,34,36 2006.285.21:08:53.29/va/04,06,usb,yes,35,37 2006.285.21:08:53.29/va/05,03,usb,yes,35,35 2006.285.21:08:53.29/va/06,04,usb,yes,32,31 2006.285.21:08:53.29/va/07,04,usb,yes,32,33 2006.285.21:08:53.29/va/08,03,usb,yes,33,40 2006.285.21:08:53.52/valo/01,524.99,yes,locked 2006.285.21:08:53.52/valo/02,534.99,yes,locked 2006.285.21:08:53.52/valo/03,564.99,yes,locked 2006.285.21:08:53.52/valo/04,624.99,yes,locked 2006.285.21:08:53.52/valo/05,734.99,yes,locked 2006.285.21:08:53.52/valo/06,814.99,yes,locked 2006.285.21:08:53.52/valo/07,864.99,yes,locked 2006.285.21:08:53.52/valo/08,884.99,yes,locked 2006.285.21:08:54.61/vb/01,04,usb,yes,31,29 2006.285.21:08:54.61/vb/02,05,usb,yes,29,29 2006.285.21:08:54.61/vb/03,04,usb,yes,30,33 2006.285.21:08:54.61/vb/04,05,usb,yes,31,29 2006.285.21:08:54.61/vb/05,04,usb,yes,27,29 2006.285.21:08:54.61/vb/06,03,usb,yes,39,34 2006.285.21:08:54.61/vb/07,04,usb,yes,31,31 2006.285.21:08:54.61/vb/08,04,usb,yes,28,32 2006.285.21:08:54.84/vblo/01,629.99,yes,locked 2006.285.21:08:54.84/vblo/02,634.99,yes,locked 2006.285.21:08:54.84/vblo/03,649.99,yes,locked 2006.285.21:08:54.84/vblo/04,679.99,yes,locked 2006.285.21:08:54.84/vblo/05,709.99,yes,locked 2006.285.21:08:54.84/vblo/06,719.99,yes,locked 2006.285.21:08:54.84/vblo/07,734.99,yes,locked 2006.285.21:08:54.84/vblo/08,744.99,yes,locked 2006.285.21:08:54.99/vabw/8 2006.285.21:08:55.14/vbbw/8 2006.285.21:08:55.30/xfe/off,on,12.0 2006.285.21:08:55.68/ifatt/23,28,28,28 2006.285.21:08:56.08/fmout-gps/S +2.93E-07 2006.285.21:08:56.10:!2006.285.21:10:52 2006.285.21:10:52.00:data_valid=off 2006.285.21:10:52.00:"et 2006.285.21:10:52.00:!+3s 2006.285.21:10:55.01:"tape 2006.285.21:10:55.01:postob 2006.285.21:10:55.11/cable/+6.5110E-03 2006.285.21:10:55.11/wx/14.23,1015.6,100 2006.285.21:10:56.07/fmout-gps/S +2.91E-07 2006.285.21:10:56.07:scan_name=285-2111,jd0610,320 2006.285.21:10:56.07:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.285.21:10:56.14#flagr#flagr/antenna,new-source 2006.285.21:10:57.14:checkk5 2006.285.21:10:57.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:10:57.97/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:10:58.57/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:10:59.01/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:10:59.50/chk_obsdata//k5ts1/T2852108??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.21:10:59.86/chk_obsdata//k5ts2/T2852108??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.21:11:00.24/chk_obsdata//k5ts3/T2852108??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.21:11:00.71/chk_obsdata//k5ts4/T2852108??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.21:11:01.88/k5log//k5ts1_log_newline 2006.285.21:11:02.70/k5log//k5ts2_log_newline 2006.285.21:11:03.47/k5log//k5ts3_log_newline 2006.285.21:11:04.26/k5log//k5ts4_log_newline 2006.285.21:11:04.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:11:04.28:setupk4=1 2006.285.21:11:04.28$setupk4/echo=on 2006.285.21:11:04.28$setupk4/pcalon 2006.285.21:11:04.28$pcalon/"no phase cal control is implemented here 2006.285.21:11:04.28$setupk4/"tpicd=stop 2006.285.21:11:04.28$setupk4/"rec=synch_on 2006.285.21:11:04.28$setupk4/"rec_mode=128 2006.285.21:11:04.28$setupk4/!* 2006.285.21:11:04.28$setupk4/recpk4 2006.285.21:11:04.28$recpk4/recpatch= 2006.285.21:11:04.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:11:04.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:11:04.29$setupk4/vck44 2006.285.21:11:04.29$vck44/valo=1,524.99 2006.285.21:11:04.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.21:11:04.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.21:11:04.29#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:04.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:11:04.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:11:04.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:11:04.29#ibcon#enter wrdev, iclass 24, count 0 2006.285.21:11:04.29#ibcon#first serial, iclass 24, count 0 2006.285.21:11:04.29#ibcon#enter sib2, iclass 24, count 0 2006.285.21:11:04.29#ibcon#flushed, iclass 24, count 0 2006.285.21:11:04.29#ibcon#about to write, iclass 24, count 0 2006.285.21:11:04.29#ibcon#wrote, iclass 24, count 0 2006.285.21:11:04.29#ibcon#about to read 3, iclass 24, count 0 2006.285.21:11:04.31#ibcon#read 3, iclass 24, count 0 2006.285.21:11:04.31#ibcon#about to read 4, iclass 24, count 0 2006.285.21:11:04.31#ibcon#read 4, iclass 24, count 0 2006.285.21:11:04.31#ibcon#about to read 5, iclass 24, count 0 2006.285.21:11:04.31#ibcon#read 5, iclass 24, count 0 2006.285.21:11:04.31#ibcon#about to read 6, iclass 24, count 0 2006.285.21:11:04.31#ibcon#read 6, iclass 24, count 0 2006.285.21:11:04.31#ibcon#end of sib2, iclass 24, count 0 2006.285.21:11:04.31#ibcon#*mode == 0, iclass 24, count 0 2006.285.21:11:04.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.21:11:04.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:11:04.31#ibcon#*before write, iclass 24, count 0 2006.285.21:11:04.31#ibcon#enter sib2, iclass 24, count 0 2006.285.21:11:04.31#ibcon#flushed, iclass 24, count 0 2006.285.21:11:04.31#ibcon#about to write, iclass 24, count 0 2006.285.21:11:04.31#ibcon#wrote, iclass 24, count 0 2006.285.21:11:04.31#ibcon#about to read 3, iclass 24, count 0 2006.285.21:11:04.36#ibcon#read 3, iclass 24, count 0 2006.285.21:11:04.36#ibcon#about to read 4, iclass 24, count 0 2006.285.21:11:04.36#ibcon#read 4, iclass 24, count 0 2006.285.21:11:04.36#ibcon#about to read 5, iclass 24, count 0 2006.285.21:11:04.36#ibcon#read 5, iclass 24, count 0 2006.285.21:11:04.36#ibcon#about to read 6, iclass 24, count 0 2006.285.21:11:04.36#ibcon#read 6, iclass 24, count 0 2006.285.21:11:04.36#ibcon#end of sib2, iclass 24, count 0 2006.285.21:11:04.36#ibcon#*after write, iclass 24, count 0 2006.285.21:11:04.36#ibcon#*before return 0, iclass 24, count 0 2006.285.21:11:04.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:11:04.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:11:04.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.21:11:04.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.21:11:04.36$vck44/va=1,7 2006.285.21:11:04.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.21:11:04.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.21:11:04.36#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:04.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:11:04.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:11:04.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:11:04.36#ibcon#enter wrdev, iclass 26, count 2 2006.285.21:11:04.36#ibcon#first serial, iclass 26, count 2 2006.285.21:11:04.36#ibcon#enter sib2, iclass 26, count 2 2006.285.21:11:04.36#ibcon#flushed, iclass 26, count 2 2006.285.21:11:04.36#ibcon#about to write, iclass 26, count 2 2006.285.21:11:04.36#ibcon#wrote, iclass 26, count 2 2006.285.21:11:04.36#ibcon#about to read 3, iclass 26, count 2 2006.285.21:11:04.38#ibcon#read 3, iclass 26, count 2 2006.285.21:11:04.38#ibcon#about to read 4, iclass 26, count 2 2006.285.21:11:04.38#ibcon#read 4, iclass 26, count 2 2006.285.21:11:04.38#ibcon#about to read 5, iclass 26, count 2 2006.285.21:11:04.38#ibcon#read 5, iclass 26, count 2 2006.285.21:11:04.38#ibcon#about to read 6, iclass 26, count 2 2006.285.21:11:04.38#ibcon#read 6, iclass 26, count 2 2006.285.21:11:04.38#ibcon#end of sib2, iclass 26, count 2 2006.285.21:11:04.38#ibcon#*mode == 0, iclass 26, count 2 2006.285.21:11:04.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.21:11:04.38#ibcon#[25=AT01-07\r\n] 2006.285.21:11:04.38#ibcon#*before write, iclass 26, count 2 2006.285.21:11:04.38#ibcon#enter sib2, iclass 26, count 2 2006.285.21:11:04.38#ibcon#flushed, iclass 26, count 2 2006.285.21:11:04.38#ibcon#about to write, iclass 26, count 2 2006.285.21:11:04.38#ibcon#wrote, iclass 26, count 2 2006.285.21:11:04.38#ibcon#about to read 3, iclass 26, count 2 2006.285.21:11:04.41#ibcon#read 3, iclass 26, count 2 2006.285.21:11:04.41#ibcon#about to read 4, iclass 26, count 2 2006.285.21:11:04.41#ibcon#read 4, iclass 26, count 2 2006.285.21:11:04.41#ibcon#about to read 5, iclass 26, count 2 2006.285.21:11:04.41#ibcon#read 5, iclass 26, count 2 2006.285.21:11:04.41#ibcon#about to read 6, iclass 26, count 2 2006.285.21:11:04.41#ibcon#read 6, iclass 26, count 2 2006.285.21:11:04.41#ibcon#end of sib2, iclass 26, count 2 2006.285.21:11:04.41#ibcon#*after write, iclass 26, count 2 2006.285.21:11:04.41#ibcon#*before return 0, iclass 26, count 2 2006.285.21:11:04.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:11:04.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:11:04.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.21:11:04.41#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:04.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:11:04.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:11:04.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:11:04.53#ibcon#enter wrdev, iclass 26, count 0 2006.285.21:11:04.53#ibcon#first serial, iclass 26, count 0 2006.285.21:11:04.53#ibcon#enter sib2, iclass 26, count 0 2006.285.21:11:04.53#ibcon#flushed, iclass 26, count 0 2006.285.21:11:04.53#ibcon#about to write, iclass 26, count 0 2006.285.21:11:04.53#ibcon#wrote, iclass 26, count 0 2006.285.21:11:04.53#ibcon#about to read 3, iclass 26, count 0 2006.285.21:11:04.55#ibcon#read 3, iclass 26, count 0 2006.285.21:11:04.55#ibcon#about to read 4, iclass 26, count 0 2006.285.21:11:04.55#ibcon#read 4, iclass 26, count 0 2006.285.21:11:04.55#ibcon#about to read 5, iclass 26, count 0 2006.285.21:11:04.55#ibcon#read 5, iclass 26, count 0 2006.285.21:11:04.55#ibcon#about to read 6, iclass 26, count 0 2006.285.21:11:04.55#ibcon#read 6, iclass 26, count 0 2006.285.21:11:04.55#ibcon#end of sib2, iclass 26, count 0 2006.285.21:11:04.55#ibcon#*mode == 0, iclass 26, count 0 2006.285.21:11:04.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.21:11:04.55#ibcon#[25=USB\r\n] 2006.285.21:11:04.55#ibcon#*before write, iclass 26, count 0 2006.285.21:11:04.55#ibcon#enter sib2, iclass 26, count 0 2006.285.21:11:04.55#ibcon#flushed, iclass 26, count 0 2006.285.21:11:04.55#ibcon#about to write, iclass 26, count 0 2006.285.21:11:04.55#ibcon#wrote, iclass 26, count 0 2006.285.21:11:04.55#ibcon#about to read 3, iclass 26, count 0 2006.285.21:11:04.58#ibcon#read 3, iclass 26, count 0 2006.285.21:11:04.58#ibcon#about to read 4, iclass 26, count 0 2006.285.21:11:04.58#ibcon#read 4, iclass 26, count 0 2006.285.21:11:04.58#ibcon#about to read 5, iclass 26, count 0 2006.285.21:11:04.58#ibcon#read 5, iclass 26, count 0 2006.285.21:11:04.58#ibcon#about to read 6, iclass 26, count 0 2006.285.21:11:04.58#ibcon#read 6, iclass 26, count 0 2006.285.21:11:04.58#ibcon#end of sib2, iclass 26, count 0 2006.285.21:11:04.58#ibcon#*after write, iclass 26, count 0 2006.285.21:11:04.58#ibcon#*before return 0, iclass 26, count 0 2006.285.21:11:04.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:11:04.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:11:04.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.21:11:04.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.21:11:04.58$vck44/valo=2,534.99 2006.285.21:11:04.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.21:11:04.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.21:11:04.58#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:04.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:11:04.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:11:04.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:11:04.58#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:11:04.58#ibcon#first serial, iclass 28, count 0 2006.285.21:11:04.58#ibcon#enter sib2, iclass 28, count 0 2006.285.21:11:04.58#ibcon#flushed, iclass 28, count 0 2006.285.21:11:04.58#ibcon#about to write, iclass 28, count 0 2006.285.21:11:04.58#ibcon#wrote, iclass 28, count 0 2006.285.21:11:04.58#ibcon#about to read 3, iclass 28, count 0 2006.285.21:11:04.60#ibcon#read 3, iclass 28, count 0 2006.285.21:11:04.60#ibcon#about to read 4, iclass 28, count 0 2006.285.21:11:04.60#ibcon#read 4, iclass 28, count 0 2006.285.21:11:04.60#ibcon#about to read 5, iclass 28, count 0 2006.285.21:11:04.60#ibcon#read 5, iclass 28, count 0 2006.285.21:11:04.60#ibcon#about to read 6, iclass 28, count 0 2006.285.21:11:04.60#ibcon#read 6, iclass 28, count 0 2006.285.21:11:04.60#ibcon#end of sib2, iclass 28, count 0 2006.285.21:11:04.60#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:11:04.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:11:04.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:11:04.60#ibcon#*before write, iclass 28, count 0 2006.285.21:11:04.60#ibcon#enter sib2, iclass 28, count 0 2006.285.21:11:04.60#ibcon#flushed, iclass 28, count 0 2006.285.21:11:04.60#ibcon#about to write, iclass 28, count 0 2006.285.21:11:04.60#ibcon#wrote, iclass 28, count 0 2006.285.21:11:04.60#ibcon#about to read 3, iclass 28, count 0 2006.285.21:11:04.64#ibcon#read 3, iclass 28, count 0 2006.285.21:11:04.64#ibcon#about to read 4, iclass 28, count 0 2006.285.21:11:04.64#ibcon#read 4, iclass 28, count 0 2006.285.21:11:04.64#ibcon#about to read 5, iclass 28, count 0 2006.285.21:11:04.64#ibcon#read 5, iclass 28, count 0 2006.285.21:11:04.64#ibcon#about to read 6, iclass 28, count 0 2006.285.21:11:04.64#ibcon#read 6, iclass 28, count 0 2006.285.21:11:04.64#ibcon#end of sib2, iclass 28, count 0 2006.285.21:11:04.64#ibcon#*after write, iclass 28, count 0 2006.285.21:11:04.64#ibcon#*before return 0, iclass 28, count 0 2006.285.21:11:04.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:11:04.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:11:04.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:11:04.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:11:04.64$vck44/va=2,6 2006.285.21:11:04.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.21:11:04.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.21:11:04.64#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:04.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:11:04.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:11:04.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:11:04.70#ibcon#enter wrdev, iclass 30, count 2 2006.285.21:11:04.70#ibcon#first serial, iclass 30, count 2 2006.285.21:11:04.70#ibcon#enter sib2, iclass 30, count 2 2006.285.21:11:04.70#ibcon#flushed, iclass 30, count 2 2006.285.21:11:04.70#ibcon#about to write, iclass 30, count 2 2006.285.21:11:04.70#ibcon#wrote, iclass 30, count 2 2006.285.21:11:04.70#ibcon#about to read 3, iclass 30, count 2 2006.285.21:11:04.72#ibcon#read 3, iclass 30, count 2 2006.285.21:11:04.72#ibcon#about to read 4, iclass 30, count 2 2006.285.21:11:04.72#ibcon#read 4, iclass 30, count 2 2006.285.21:11:04.72#ibcon#about to read 5, iclass 30, count 2 2006.285.21:11:04.72#ibcon#read 5, iclass 30, count 2 2006.285.21:11:04.72#ibcon#about to read 6, iclass 30, count 2 2006.285.21:11:04.72#ibcon#read 6, iclass 30, count 2 2006.285.21:11:04.72#ibcon#end of sib2, iclass 30, count 2 2006.285.21:11:04.72#ibcon#*mode == 0, iclass 30, count 2 2006.285.21:11:04.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.21:11:04.72#ibcon#[25=AT02-06\r\n] 2006.285.21:11:04.72#ibcon#*before write, iclass 30, count 2 2006.285.21:11:04.72#ibcon#enter sib2, iclass 30, count 2 2006.285.21:11:04.72#ibcon#flushed, iclass 30, count 2 2006.285.21:11:04.72#ibcon#about to write, iclass 30, count 2 2006.285.21:11:04.72#ibcon#wrote, iclass 30, count 2 2006.285.21:11:04.72#ibcon#about to read 3, iclass 30, count 2 2006.285.21:11:04.75#ibcon#read 3, iclass 30, count 2 2006.285.21:11:04.75#ibcon#about to read 4, iclass 30, count 2 2006.285.21:11:04.75#ibcon#read 4, iclass 30, count 2 2006.285.21:11:04.75#ibcon#about to read 5, iclass 30, count 2 2006.285.21:11:04.75#ibcon#read 5, iclass 30, count 2 2006.285.21:11:04.75#ibcon#about to read 6, iclass 30, count 2 2006.285.21:11:04.75#ibcon#read 6, iclass 30, count 2 2006.285.21:11:04.75#ibcon#end of sib2, iclass 30, count 2 2006.285.21:11:04.75#ibcon#*after write, iclass 30, count 2 2006.285.21:11:04.75#ibcon#*before return 0, iclass 30, count 2 2006.285.21:11:04.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:11:04.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:11:04.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.21:11:04.75#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:04.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:11:04.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:11:04.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:11:04.87#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:11:04.87#ibcon#first serial, iclass 30, count 0 2006.285.21:11:04.87#ibcon#enter sib2, iclass 30, count 0 2006.285.21:11:04.87#ibcon#flushed, iclass 30, count 0 2006.285.21:11:04.87#ibcon#about to write, iclass 30, count 0 2006.285.21:11:04.87#ibcon#wrote, iclass 30, count 0 2006.285.21:11:04.87#ibcon#about to read 3, iclass 30, count 0 2006.285.21:11:04.89#ibcon#read 3, iclass 30, count 0 2006.285.21:11:04.89#ibcon#about to read 4, iclass 30, count 0 2006.285.21:11:04.89#ibcon#read 4, iclass 30, count 0 2006.285.21:11:04.89#ibcon#about to read 5, iclass 30, count 0 2006.285.21:11:04.89#ibcon#read 5, iclass 30, count 0 2006.285.21:11:04.89#ibcon#about to read 6, iclass 30, count 0 2006.285.21:11:04.89#ibcon#read 6, iclass 30, count 0 2006.285.21:11:04.89#ibcon#end of sib2, iclass 30, count 0 2006.285.21:11:04.89#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:11:04.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:11:04.89#ibcon#[25=USB\r\n] 2006.285.21:11:04.89#ibcon#*before write, iclass 30, count 0 2006.285.21:11:04.89#ibcon#enter sib2, iclass 30, count 0 2006.285.21:11:04.89#ibcon#flushed, iclass 30, count 0 2006.285.21:11:04.89#ibcon#about to write, iclass 30, count 0 2006.285.21:11:04.89#ibcon#wrote, iclass 30, count 0 2006.285.21:11:04.89#ibcon#about to read 3, iclass 30, count 0 2006.285.21:11:04.92#ibcon#read 3, iclass 30, count 0 2006.285.21:11:04.92#ibcon#about to read 4, iclass 30, count 0 2006.285.21:11:04.92#ibcon#read 4, iclass 30, count 0 2006.285.21:11:04.92#ibcon#about to read 5, iclass 30, count 0 2006.285.21:11:04.92#ibcon#read 5, iclass 30, count 0 2006.285.21:11:04.92#ibcon#about to read 6, iclass 30, count 0 2006.285.21:11:04.92#ibcon#read 6, iclass 30, count 0 2006.285.21:11:04.92#ibcon#end of sib2, iclass 30, count 0 2006.285.21:11:04.92#ibcon#*after write, iclass 30, count 0 2006.285.21:11:04.92#ibcon#*before return 0, iclass 30, count 0 2006.285.21:11:04.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:11:04.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:11:04.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:11:04.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:11:04.92$vck44/valo=3,564.99 2006.285.21:11:04.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.21:11:04.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.21:11:04.92#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:04.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:11:04.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:11:04.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:11:04.92#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:11:04.92#ibcon#first serial, iclass 32, count 0 2006.285.21:11:04.92#ibcon#enter sib2, iclass 32, count 0 2006.285.21:11:04.92#ibcon#flushed, iclass 32, count 0 2006.285.21:11:04.92#ibcon#about to write, iclass 32, count 0 2006.285.21:11:04.92#ibcon#wrote, iclass 32, count 0 2006.285.21:11:04.92#ibcon#about to read 3, iclass 32, count 0 2006.285.21:11:04.94#ibcon#read 3, iclass 32, count 0 2006.285.21:11:04.94#ibcon#about to read 4, iclass 32, count 0 2006.285.21:11:04.94#ibcon#read 4, iclass 32, count 0 2006.285.21:11:04.94#ibcon#about to read 5, iclass 32, count 0 2006.285.21:11:04.94#ibcon#read 5, iclass 32, count 0 2006.285.21:11:04.94#ibcon#about to read 6, iclass 32, count 0 2006.285.21:11:04.94#ibcon#read 6, iclass 32, count 0 2006.285.21:11:04.94#ibcon#end of sib2, iclass 32, count 0 2006.285.21:11:04.94#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:11:04.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:11:04.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:11:04.94#ibcon#*before write, iclass 32, count 0 2006.285.21:11:04.94#ibcon#enter sib2, iclass 32, count 0 2006.285.21:11:04.94#ibcon#flushed, iclass 32, count 0 2006.285.21:11:04.94#ibcon#about to write, iclass 32, count 0 2006.285.21:11:04.94#ibcon#wrote, iclass 32, count 0 2006.285.21:11:04.94#ibcon#about to read 3, iclass 32, count 0 2006.285.21:11:04.98#ibcon#read 3, iclass 32, count 0 2006.285.21:11:04.98#ibcon#about to read 4, iclass 32, count 0 2006.285.21:11:04.98#ibcon#read 4, iclass 32, count 0 2006.285.21:11:04.98#ibcon#about to read 5, iclass 32, count 0 2006.285.21:11:04.98#ibcon#read 5, iclass 32, count 0 2006.285.21:11:04.98#ibcon#about to read 6, iclass 32, count 0 2006.285.21:11:04.98#ibcon#read 6, iclass 32, count 0 2006.285.21:11:04.98#ibcon#end of sib2, iclass 32, count 0 2006.285.21:11:04.98#ibcon#*after write, iclass 32, count 0 2006.285.21:11:04.98#ibcon#*before return 0, iclass 32, count 0 2006.285.21:11:04.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:11:04.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:11:04.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:11:04.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:11:04.98$vck44/va=3,7 2006.285.21:11:04.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.21:11:04.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.21:11:04.98#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:04.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:11:05.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:11:05.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:11:05.04#ibcon#enter wrdev, iclass 34, count 2 2006.285.21:11:05.04#ibcon#first serial, iclass 34, count 2 2006.285.21:11:05.04#ibcon#enter sib2, iclass 34, count 2 2006.285.21:11:05.04#ibcon#flushed, iclass 34, count 2 2006.285.21:11:05.04#ibcon#about to write, iclass 34, count 2 2006.285.21:11:05.04#ibcon#wrote, iclass 34, count 2 2006.285.21:11:05.04#ibcon#about to read 3, iclass 34, count 2 2006.285.21:11:05.06#ibcon#read 3, iclass 34, count 2 2006.285.21:11:05.06#ibcon#about to read 4, iclass 34, count 2 2006.285.21:11:05.06#ibcon#read 4, iclass 34, count 2 2006.285.21:11:05.06#ibcon#about to read 5, iclass 34, count 2 2006.285.21:11:05.06#ibcon#read 5, iclass 34, count 2 2006.285.21:11:05.06#ibcon#about to read 6, iclass 34, count 2 2006.285.21:11:05.06#ibcon#read 6, iclass 34, count 2 2006.285.21:11:05.06#ibcon#end of sib2, iclass 34, count 2 2006.285.21:11:05.06#ibcon#*mode == 0, iclass 34, count 2 2006.285.21:11:05.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.21:11:05.06#ibcon#[25=AT03-07\r\n] 2006.285.21:11:05.06#ibcon#*before write, iclass 34, count 2 2006.285.21:11:05.06#ibcon#enter sib2, iclass 34, count 2 2006.285.21:11:05.06#ibcon#flushed, iclass 34, count 2 2006.285.21:11:05.06#ibcon#about to write, iclass 34, count 2 2006.285.21:11:05.06#ibcon#wrote, iclass 34, count 2 2006.285.21:11:05.06#ibcon#about to read 3, iclass 34, count 2 2006.285.21:11:05.09#ibcon#read 3, iclass 34, count 2 2006.285.21:11:05.09#ibcon#about to read 4, iclass 34, count 2 2006.285.21:11:05.09#ibcon#read 4, iclass 34, count 2 2006.285.21:11:05.09#ibcon#about to read 5, iclass 34, count 2 2006.285.21:11:05.09#ibcon#read 5, iclass 34, count 2 2006.285.21:11:05.09#ibcon#about to read 6, iclass 34, count 2 2006.285.21:11:05.09#ibcon#read 6, iclass 34, count 2 2006.285.21:11:05.09#ibcon#end of sib2, iclass 34, count 2 2006.285.21:11:05.09#ibcon#*after write, iclass 34, count 2 2006.285.21:11:05.09#ibcon#*before return 0, iclass 34, count 2 2006.285.21:11:05.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:11:05.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:11:05.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.21:11:05.09#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:05.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:11:05.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:11:05.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:11:05.21#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:11:05.21#ibcon#first serial, iclass 34, count 0 2006.285.21:11:05.21#ibcon#enter sib2, iclass 34, count 0 2006.285.21:11:05.21#ibcon#flushed, iclass 34, count 0 2006.285.21:11:05.21#ibcon#about to write, iclass 34, count 0 2006.285.21:11:05.21#ibcon#wrote, iclass 34, count 0 2006.285.21:11:05.21#ibcon#about to read 3, iclass 34, count 0 2006.285.21:11:05.23#ibcon#read 3, iclass 34, count 0 2006.285.21:11:05.23#ibcon#about to read 4, iclass 34, count 0 2006.285.21:11:05.23#ibcon#read 4, iclass 34, count 0 2006.285.21:11:05.23#ibcon#about to read 5, iclass 34, count 0 2006.285.21:11:05.23#ibcon#read 5, iclass 34, count 0 2006.285.21:11:05.23#ibcon#about to read 6, iclass 34, count 0 2006.285.21:11:05.23#ibcon#read 6, iclass 34, count 0 2006.285.21:11:05.23#ibcon#end of sib2, iclass 34, count 0 2006.285.21:11:05.23#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:11:05.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:11:05.23#ibcon#[25=USB\r\n] 2006.285.21:11:05.23#ibcon#*before write, iclass 34, count 0 2006.285.21:11:05.23#ibcon#enter sib2, iclass 34, count 0 2006.285.21:11:05.23#ibcon#flushed, iclass 34, count 0 2006.285.21:11:05.23#ibcon#about to write, iclass 34, count 0 2006.285.21:11:05.23#ibcon#wrote, iclass 34, count 0 2006.285.21:11:05.23#ibcon#about to read 3, iclass 34, count 0 2006.285.21:11:05.26#ibcon#read 3, iclass 34, count 0 2006.285.21:11:05.26#ibcon#about to read 4, iclass 34, count 0 2006.285.21:11:05.26#ibcon#read 4, iclass 34, count 0 2006.285.21:11:05.26#ibcon#about to read 5, iclass 34, count 0 2006.285.21:11:05.26#ibcon#read 5, iclass 34, count 0 2006.285.21:11:05.26#ibcon#about to read 6, iclass 34, count 0 2006.285.21:11:05.26#ibcon#read 6, iclass 34, count 0 2006.285.21:11:05.26#ibcon#end of sib2, iclass 34, count 0 2006.285.21:11:05.26#ibcon#*after write, iclass 34, count 0 2006.285.21:11:05.26#ibcon#*before return 0, iclass 34, count 0 2006.285.21:11:05.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:11:05.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:11:05.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:11:05.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:11:05.26$vck44/valo=4,624.99 2006.285.21:11:05.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.21:11:05.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.21:11:05.26#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:05.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:11:05.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:11:05.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:11:05.26#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:11:05.26#ibcon#first serial, iclass 36, count 0 2006.285.21:11:05.26#ibcon#enter sib2, iclass 36, count 0 2006.285.21:11:05.26#ibcon#flushed, iclass 36, count 0 2006.285.21:11:05.26#ibcon#about to write, iclass 36, count 0 2006.285.21:11:05.26#ibcon#wrote, iclass 36, count 0 2006.285.21:11:05.26#ibcon#about to read 3, iclass 36, count 0 2006.285.21:11:05.28#ibcon#read 3, iclass 36, count 0 2006.285.21:11:05.28#ibcon#about to read 4, iclass 36, count 0 2006.285.21:11:05.28#ibcon#read 4, iclass 36, count 0 2006.285.21:11:05.28#ibcon#about to read 5, iclass 36, count 0 2006.285.21:11:05.28#ibcon#read 5, iclass 36, count 0 2006.285.21:11:05.28#ibcon#about to read 6, iclass 36, count 0 2006.285.21:11:05.28#ibcon#read 6, iclass 36, count 0 2006.285.21:11:05.28#ibcon#end of sib2, iclass 36, count 0 2006.285.21:11:05.28#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:11:05.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:11:05.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:11:05.28#ibcon#*before write, iclass 36, count 0 2006.285.21:11:05.28#ibcon#enter sib2, iclass 36, count 0 2006.285.21:11:05.28#ibcon#flushed, iclass 36, count 0 2006.285.21:11:05.28#ibcon#about to write, iclass 36, count 0 2006.285.21:11:05.28#ibcon#wrote, iclass 36, count 0 2006.285.21:11:05.28#ibcon#about to read 3, iclass 36, count 0 2006.285.21:11:05.32#ibcon#read 3, iclass 36, count 0 2006.285.21:11:05.32#ibcon#about to read 4, iclass 36, count 0 2006.285.21:11:05.32#ibcon#read 4, iclass 36, count 0 2006.285.21:11:05.32#ibcon#about to read 5, iclass 36, count 0 2006.285.21:11:05.32#ibcon#read 5, iclass 36, count 0 2006.285.21:11:05.32#ibcon#about to read 6, iclass 36, count 0 2006.285.21:11:05.32#ibcon#read 6, iclass 36, count 0 2006.285.21:11:05.32#ibcon#end of sib2, iclass 36, count 0 2006.285.21:11:05.32#ibcon#*after write, iclass 36, count 0 2006.285.21:11:05.32#ibcon#*before return 0, iclass 36, count 0 2006.285.21:11:05.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:11:05.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:11:05.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:11:05.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:11:05.32$vck44/va=4,6 2006.285.21:11:05.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.21:11:05.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.21:11:05.32#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:05.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:11:05.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:11:05.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:11:05.38#ibcon#enter wrdev, iclass 38, count 2 2006.285.21:11:05.38#ibcon#first serial, iclass 38, count 2 2006.285.21:11:05.38#ibcon#enter sib2, iclass 38, count 2 2006.285.21:11:05.38#ibcon#flushed, iclass 38, count 2 2006.285.21:11:05.38#ibcon#about to write, iclass 38, count 2 2006.285.21:11:05.38#ibcon#wrote, iclass 38, count 2 2006.285.21:11:05.38#ibcon#about to read 3, iclass 38, count 2 2006.285.21:11:05.40#ibcon#read 3, iclass 38, count 2 2006.285.21:11:05.40#ibcon#about to read 4, iclass 38, count 2 2006.285.21:11:05.40#ibcon#read 4, iclass 38, count 2 2006.285.21:11:05.40#ibcon#about to read 5, iclass 38, count 2 2006.285.21:11:05.40#ibcon#read 5, iclass 38, count 2 2006.285.21:11:05.40#ibcon#about to read 6, iclass 38, count 2 2006.285.21:11:05.40#ibcon#read 6, iclass 38, count 2 2006.285.21:11:05.40#ibcon#end of sib2, iclass 38, count 2 2006.285.21:11:05.40#ibcon#*mode == 0, iclass 38, count 2 2006.285.21:11:05.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.21:11:05.40#ibcon#[25=AT04-06\r\n] 2006.285.21:11:05.40#ibcon#*before write, iclass 38, count 2 2006.285.21:11:05.40#ibcon#enter sib2, iclass 38, count 2 2006.285.21:11:05.40#ibcon#flushed, iclass 38, count 2 2006.285.21:11:05.40#ibcon#about to write, iclass 38, count 2 2006.285.21:11:05.40#ibcon#wrote, iclass 38, count 2 2006.285.21:11:05.40#ibcon#about to read 3, iclass 38, count 2 2006.285.21:11:05.43#ibcon#read 3, iclass 38, count 2 2006.285.21:11:05.84#ibcon#about to read 4, iclass 38, count 2 2006.285.21:11:05.84#ibcon#read 4, iclass 38, count 2 2006.285.21:11:05.84#ibcon#about to read 5, iclass 38, count 2 2006.285.21:11:05.84#ibcon#read 5, iclass 38, count 2 2006.285.21:11:05.84#ibcon#about to read 6, iclass 38, count 2 2006.285.21:11:05.84#ibcon#read 6, iclass 38, count 2 2006.285.21:11:05.84#ibcon#end of sib2, iclass 38, count 2 2006.285.21:11:05.84#ibcon#*after write, iclass 38, count 2 2006.285.21:11:05.84#ibcon#*before return 0, iclass 38, count 2 2006.285.21:11:05.84#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:11:05.84#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:11:05.84#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.21:11:05.84#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:05.84#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:11:05.95#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:11:05.95#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:11:05.95#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:11:05.95#ibcon#first serial, iclass 38, count 0 2006.285.21:11:05.95#ibcon#enter sib2, iclass 38, count 0 2006.285.21:11:05.95#ibcon#flushed, iclass 38, count 0 2006.285.21:11:05.95#ibcon#about to write, iclass 38, count 0 2006.285.21:11:05.95#ibcon#wrote, iclass 38, count 0 2006.285.21:11:05.95#ibcon#about to read 3, iclass 38, count 0 2006.285.21:11:05.97#ibcon#read 3, iclass 38, count 0 2006.285.21:11:05.97#ibcon#about to read 4, iclass 38, count 0 2006.285.21:11:05.97#ibcon#read 4, iclass 38, count 0 2006.285.21:11:05.97#ibcon#about to read 5, iclass 38, count 0 2006.285.21:11:05.97#ibcon#read 5, iclass 38, count 0 2006.285.21:11:05.97#ibcon#about to read 6, iclass 38, count 0 2006.285.21:11:05.97#ibcon#read 6, iclass 38, count 0 2006.285.21:11:05.97#ibcon#end of sib2, iclass 38, count 0 2006.285.21:11:05.97#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:11:05.97#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:11:05.97#ibcon#[25=USB\r\n] 2006.285.21:11:05.97#ibcon#*before write, iclass 38, count 0 2006.285.21:11:05.97#ibcon#enter sib2, iclass 38, count 0 2006.285.21:11:05.97#ibcon#flushed, iclass 38, count 0 2006.285.21:11:05.97#ibcon#about to write, iclass 38, count 0 2006.285.21:11:05.97#ibcon#wrote, iclass 38, count 0 2006.285.21:11:05.97#ibcon#about to read 3, iclass 38, count 0 2006.285.21:11:06.00#ibcon#read 3, iclass 38, count 0 2006.285.21:11:06.00#ibcon#about to read 4, iclass 38, count 0 2006.285.21:11:06.00#ibcon#read 4, iclass 38, count 0 2006.285.21:11:06.00#ibcon#about to read 5, iclass 38, count 0 2006.285.21:11:06.00#ibcon#read 5, iclass 38, count 0 2006.285.21:11:06.00#ibcon#about to read 6, iclass 38, count 0 2006.285.21:11:06.00#ibcon#read 6, iclass 38, count 0 2006.285.21:11:06.00#ibcon#end of sib2, iclass 38, count 0 2006.285.21:11:06.00#ibcon#*after write, iclass 38, count 0 2006.285.21:11:06.00#ibcon#*before return 0, iclass 38, count 0 2006.285.21:11:06.00#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:11:06.00#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:11:06.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:11:06.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:11:06.00$vck44/valo=5,734.99 2006.285.21:11:06.00#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.21:11:06.00#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.21:11:06.00#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:06.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:11:06.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:11:06.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:11:06.00#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:11:06.00#ibcon#first serial, iclass 40, count 0 2006.285.21:11:06.00#ibcon#enter sib2, iclass 40, count 0 2006.285.21:11:06.00#ibcon#flushed, iclass 40, count 0 2006.285.21:11:06.00#ibcon#about to write, iclass 40, count 0 2006.285.21:11:06.00#ibcon#wrote, iclass 40, count 0 2006.285.21:11:06.00#ibcon#about to read 3, iclass 40, count 0 2006.285.21:11:06.02#ibcon#read 3, iclass 40, count 0 2006.285.21:11:06.02#ibcon#about to read 4, iclass 40, count 0 2006.285.21:11:06.02#ibcon#read 4, iclass 40, count 0 2006.285.21:11:06.02#ibcon#about to read 5, iclass 40, count 0 2006.285.21:11:06.02#ibcon#read 5, iclass 40, count 0 2006.285.21:11:06.02#ibcon#about to read 6, iclass 40, count 0 2006.285.21:11:06.02#ibcon#read 6, iclass 40, count 0 2006.285.21:11:06.02#ibcon#end of sib2, iclass 40, count 0 2006.285.21:11:06.02#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:11:06.02#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:11:06.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:11:06.02#ibcon#*before write, iclass 40, count 0 2006.285.21:11:06.02#ibcon#enter sib2, iclass 40, count 0 2006.285.21:11:06.02#ibcon#flushed, iclass 40, count 0 2006.285.21:11:06.02#ibcon#about to write, iclass 40, count 0 2006.285.21:11:06.02#ibcon#wrote, iclass 40, count 0 2006.285.21:11:06.02#ibcon#about to read 3, iclass 40, count 0 2006.285.21:11:06.06#ibcon#read 3, iclass 40, count 0 2006.285.21:11:06.06#ibcon#about to read 4, iclass 40, count 0 2006.285.21:11:06.06#ibcon#read 4, iclass 40, count 0 2006.285.21:11:06.06#ibcon#about to read 5, iclass 40, count 0 2006.285.21:11:06.06#ibcon#read 5, iclass 40, count 0 2006.285.21:11:06.06#ibcon#about to read 6, iclass 40, count 0 2006.285.21:11:06.06#ibcon#read 6, iclass 40, count 0 2006.285.21:11:06.06#ibcon#end of sib2, iclass 40, count 0 2006.285.21:11:06.06#ibcon#*after write, iclass 40, count 0 2006.285.21:11:06.06#ibcon#*before return 0, iclass 40, count 0 2006.285.21:11:06.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:11:06.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:11:06.06#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:11:06.06#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:11:06.06$vck44/va=5,3 2006.285.21:11:06.06#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.21:11:06.06#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.21:11:06.06#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:06.06#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:11:06.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:11:06.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:11:06.12#ibcon#enter wrdev, iclass 4, count 2 2006.285.21:11:06.12#ibcon#first serial, iclass 4, count 2 2006.285.21:11:06.12#ibcon#enter sib2, iclass 4, count 2 2006.285.21:11:06.12#ibcon#flushed, iclass 4, count 2 2006.285.21:11:06.12#ibcon#about to write, iclass 4, count 2 2006.285.21:11:06.12#ibcon#wrote, iclass 4, count 2 2006.285.21:11:06.12#ibcon#about to read 3, iclass 4, count 2 2006.285.21:11:06.14#ibcon#read 3, iclass 4, count 2 2006.285.21:11:06.39#ibcon#about to read 4, iclass 4, count 2 2006.285.21:11:06.39#ibcon#read 4, iclass 4, count 2 2006.285.21:11:06.39#ibcon#about to read 5, iclass 4, count 2 2006.285.21:11:06.39#ibcon#read 5, iclass 4, count 2 2006.285.21:11:06.39#ibcon#about to read 6, iclass 4, count 2 2006.285.21:11:06.39#ibcon#read 6, iclass 4, count 2 2006.285.21:11:06.39#ibcon#end of sib2, iclass 4, count 2 2006.285.21:11:06.39#ibcon#*mode == 0, iclass 4, count 2 2006.285.21:11:06.39#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.21:11:06.39#ibcon#[25=AT05-03\r\n] 2006.285.21:11:06.39#ibcon#*before write, iclass 4, count 2 2006.285.21:11:06.39#ibcon#enter sib2, iclass 4, count 2 2006.285.21:11:06.39#ibcon#flushed, iclass 4, count 2 2006.285.21:11:06.39#ibcon#about to write, iclass 4, count 2 2006.285.21:11:06.39#ibcon#wrote, iclass 4, count 2 2006.285.21:11:06.39#ibcon#about to read 3, iclass 4, count 2 2006.285.21:11:06.42#ibcon#read 3, iclass 4, count 2 2006.285.21:11:06.42#ibcon#about to read 4, iclass 4, count 2 2006.285.21:11:06.42#ibcon#read 4, iclass 4, count 2 2006.285.21:11:06.42#ibcon#about to read 5, iclass 4, count 2 2006.285.21:11:06.42#ibcon#read 5, iclass 4, count 2 2006.285.21:11:06.42#ibcon#about to read 6, iclass 4, count 2 2006.285.21:11:06.42#ibcon#read 6, iclass 4, count 2 2006.285.21:11:06.42#ibcon#end of sib2, iclass 4, count 2 2006.285.21:11:06.42#ibcon#*after write, iclass 4, count 2 2006.285.21:11:06.42#ibcon#*before return 0, iclass 4, count 2 2006.285.21:11:06.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:11:06.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:11:06.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.21:11:06.42#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:06.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:11:06.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:11:06.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:11:06.54#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:11:06.54#ibcon#first serial, iclass 4, count 0 2006.285.21:11:06.54#ibcon#enter sib2, iclass 4, count 0 2006.285.21:11:06.54#ibcon#flushed, iclass 4, count 0 2006.285.21:11:06.54#ibcon#about to write, iclass 4, count 0 2006.285.21:11:06.54#ibcon#wrote, iclass 4, count 0 2006.285.21:11:06.54#ibcon#about to read 3, iclass 4, count 0 2006.285.21:11:06.56#ibcon#read 3, iclass 4, count 0 2006.285.21:11:06.56#ibcon#about to read 4, iclass 4, count 0 2006.285.21:11:06.56#ibcon#read 4, iclass 4, count 0 2006.285.21:11:06.56#ibcon#about to read 5, iclass 4, count 0 2006.285.21:11:06.56#ibcon#read 5, iclass 4, count 0 2006.285.21:11:06.56#ibcon#about to read 6, iclass 4, count 0 2006.285.21:11:06.56#ibcon#read 6, iclass 4, count 0 2006.285.21:11:06.56#ibcon#end of sib2, iclass 4, count 0 2006.285.21:11:06.56#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:11:06.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:11:06.56#ibcon#[25=USB\r\n] 2006.285.21:11:06.56#ibcon#*before write, iclass 4, count 0 2006.285.21:11:06.56#ibcon#enter sib2, iclass 4, count 0 2006.285.21:11:06.56#ibcon#flushed, iclass 4, count 0 2006.285.21:11:06.56#ibcon#about to write, iclass 4, count 0 2006.285.21:11:06.56#ibcon#wrote, iclass 4, count 0 2006.285.21:11:06.56#ibcon#about to read 3, iclass 4, count 0 2006.285.21:11:06.59#ibcon#read 3, iclass 4, count 0 2006.285.21:11:06.59#ibcon#about to read 4, iclass 4, count 0 2006.285.21:11:06.59#ibcon#read 4, iclass 4, count 0 2006.285.21:11:06.59#ibcon#about to read 5, iclass 4, count 0 2006.285.21:11:06.59#ibcon#read 5, iclass 4, count 0 2006.285.21:11:06.59#ibcon#about to read 6, iclass 4, count 0 2006.285.21:11:06.59#ibcon#read 6, iclass 4, count 0 2006.285.21:11:06.59#ibcon#end of sib2, iclass 4, count 0 2006.285.21:11:06.59#ibcon#*after write, iclass 4, count 0 2006.285.21:11:06.59#ibcon#*before return 0, iclass 4, count 0 2006.285.21:11:06.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:11:06.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:11:06.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:11:06.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:11:06.59$vck44/valo=6,814.99 2006.285.21:11:06.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.21:11:06.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.21:11:06.59#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:06.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:11:06.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:11:06.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:11:06.59#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:11:06.59#ibcon#first serial, iclass 6, count 0 2006.285.21:11:06.59#ibcon#enter sib2, iclass 6, count 0 2006.285.21:11:06.59#ibcon#flushed, iclass 6, count 0 2006.285.21:11:06.59#ibcon#about to write, iclass 6, count 0 2006.285.21:11:06.59#ibcon#wrote, iclass 6, count 0 2006.285.21:11:06.59#ibcon#about to read 3, iclass 6, count 0 2006.285.21:11:06.61#ibcon#read 3, iclass 6, count 0 2006.285.21:11:06.61#ibcon#about to read 4, iclass 6, count 0 2006.285.21:11:06.61#ibcon#read 4, iclass 6, count 0 2006.285.21:11:06.61#ibcon#about to read 5, iclass 6, count 0 2006.285.21:11:06.61#ibcon#read 5, iclass 6, count 0 2006.285.21:11:06.61#ibcon#about to read 6, iclass 6, count 0 2006.285.21:11:06.61#ibcon#read 6, iclass 6, count 0 2006.285.21:11:06.61#ibcon#end of sib2, iclass 6, count 0 2006.285.21:11:06.61#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:11:06.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:11:06.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:11:06.61#ibcon#*before write, iclass 6, count 0 2006.285.21:11:06.61#ibcon#enter sib2, iclass 6, count 0 2006.285.21:11:06.61#ibcon#flushed, iclass 6, count 0 2006.285.21:11:06.61#ibcon#about to write, iclass 6, count 0 2006.285.21:11:06.61#ibcon#wrote, iclass 6, count 0 2006.285.21:11:06.61#ibcon#about to read 3, iclass 6, count 0 2006.285.21:11:06.65#ibcon#read 3, iclass 6, count 0 2006.285.21:11:06.65#ibcon#about to read 4, iclass 6, count 0 2006.285.21:11:06.65#ibcon#read 4, iclass 6, count 0 2006.285.21:11:06.65#ibcon#about to read 5, iclass 6, count 0 2006.285.21:11:06.65#ibcon#read 5, iclass 6, count 0 2006.285.21:11:06.65#ibcon#about to read 6, iclass 6, count 0 2006.285.21:11:06.65#ibcon#read 6, iclass 6, count 0 2006.285.21:11:06.65#ibcon#end of sib2, iclass 6, count 0 2006.285.21:11:06.65#ibcon#*after write, iclass 6, count 0 2006.285.21:11:06.65#ibcon#*before return 0, iclass 6, count 0 2006.285.21:11:06.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:11:06.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:11:06.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:11:06.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:11:06.65$vck44/va=6,4 2006.285.21:11:06.65#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.21:11:06.65#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.21:11:06.65#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:06.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:11:06.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:11:06.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:11:06.71#ibcon#enter wrdev, iclass 10, count 2 2006.285.21:11:06.71#ibcon#first serial, iclass 10, count 2 2006.285.21:11:06.71#ibcon#enter sib2, iclass 10, count 2 2006.285.21:11:06.71#ibcon#flushed, iclass 10, count 2 2006.285.21:11:06.71#ibcon#about to write, iclass 10, count 2 2006.285.21:11:06.71#ibcon#wrote, iclass 10, count 2 2006.285.21:11:06.71#ibcon#about to read 3, iclass 10, count 2 2006.285.21:11:06.73#ibcon#read 3, iclass 10, count 2 2006.285.21:11:06.73#ibcon#about to read 4, iclass 10, count 2 2006.285.21:11:06.73#ibcon#read 4, iclass 10, count 2 2006.285.21:11:06.73#ibcon#about to read 5, iclass 10, count 2 2006.285.21:11:06.73#ibcon#read 5, iclass 10, count 2 2006.285.21:11:06.73#ibcon#about to read 6, iclass 10, count 2 2006.285.21:11:06.73#ibcon#read 6, iclass 10, count 2 2006.285.21:11:06.73#ibcon#end of sib2, iclass 10, count 2 2006.285.21:11:06.73#ibcon#*mode == 0, iclass 10, count 2 2006.285.21:11:06.73#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.21:11:06.73#ibcon#[25=AT06-04\r\n] 2006.285.21:11:06.73#ibcon#*before write, iclass 10, count 2 2006.285.21:11:06.73#ibcon#enter sib2, iclass 10, count 2 2006.285.21:11:06.73#ibcon#flushed, iclass 10, count 2 2006.285.21:11:06.73#ibcon#about to write, iclass 10, count 2 2006.285.21:11:06.73#ibcon#wrote, iclass 10, count 2 2006.285.21:11:06.73#ibcon#about to read 3, iclass 10, count 2 2006.285.21:11:06.76#ibcon#read 3, iclass 10, count 2 2006.285.21:11:06.76#ibcon#about to read 4, iclass 10, count 2 2006.285.21:11:06.76#ibcon#read 4, iclass 10, count 2 2006.285.21:11:06.76#ibcon#about to read 5, iclass 10, count 2 2006.285.21:11:06.76#ibcon#read 5, iclass 10, count 2 2006.285.21:11:06.76#ibcon#about to read 6, iclass 10, count 2 2006.285.21:11:06.76#ibcon#read 6, iclass 10, count 2 2006.285.21:11:06.76#ibcon#end of sib2, iclass 10, count 2 2006.285.21:11:06.76#ibcon#*after write, iclass 10, count 2 2006.285.21:11:06.76#ibcon#*before return 0, iclass 10, count 2 2006.285.21:11:06.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:11:06.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:11:06.76#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.21:11:06.76#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:06.76#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:11:06.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:11:06.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:11:06.88#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:11:06.88#ibcon#first serial, iclass 10, count 0 2006.285.21:11:06.88#ibcon#enter sib2, iclass 10, count 0 2006.285.21:11:06.88#ibcon#flushed, iclass 10, count 0 2006.285.21:11:06.88#ibcon#about to write, iclass 10, count 0 2006.285.21:11:06.88#ibcon#wrote, iclass 10, count 0 2006.285.21:11:06.88#ibcon#about to read 3, iclass 10, count 0 2006.285.21:11:06.90#ibcon#read 3, iclass 10, count 0 2006.285.21:11:06.90#ibcon#about to read 4, iclass 10, count 0 2006.285.21:11:06.90#ibcon#read 4, iclass 10, count 0 2006.285.21:11:06.90#ibcon#about to read 5, iclass 10, count 0 2006.285.21:11:06.90#ibcon#read 5, iclass 10, count 0 2006.285.21:11:06.90#ibcon#about to read 6, iclass 10, count 0 2006.285.21:11:06.90#ibcon#read 6, iclass 10, count 0 2006.285.21:11:06.90#ibcon#end of sib2, iclass 10, count 0 2006.285.21:11:06.90#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:11:06.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:11:06.90#ibcon#[25=USB\r\n] 2006.285.21:11:06.90#ibcon#*before write, iclass 10, count 0 2006.285.21:11:06.90#ibcon#enter sib2, iclass 10, count 0 2006.285.21:11:06.90#ibcon#flushed, iclass 10, count 0 2006.285.21:11:06.90#ibcon#about to write, iclass 10, count 0 2006.285.21:11:06.90#ibcon#wrote, iclass 10, count 0 2006.285.21:11:06.90#ibcon#about to read 3, iclass 10, count 0 2006.285.21:11:06.93#ibcon#read 3, iclass 10, count 0 2006.285.21:11:06.93#ibcon#about to read 4, iclass 10, count 0 2006.285.21:11:06.93#ibcon#read 4, iclass 10, count 0 2006.285.21:11:06.93#ibcon#about to read 5, iclass 10, count 0 2006.285.21:11:06.93#ibcon#read 5, iclass 10, count 0 2006.285.21:11:06.93#ibcon#about to read 6, iclass 10, count 0 2006.285.21:11:06.93#ibcon#read 6, iclass 10, count 0 2006.285.21:11:06.93#ibcon#end of sib2, iclass 10, count 0 2006.285.21:11:06.93#ibcon#*after write, iclass 10, count 0 2006.285.21:11:06.93#ibcon#*before return 0, iclass 10, count 0 2006.285.21:11:06.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:11:06.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:11:06.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:11:06.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:11:06.93$vck44/valo=7,864.99 2006.285.21:11:06.93#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.21:11:06.93#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.21:11:06.93#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:06.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:11:06.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:11:06.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:11:06.93#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:11:06.93#ibcon#first serial, iclass 12, count 0 2006.285.21:11:06.93#ibcon#enter sib2, iclass 12, count 0 2006.285.21:11:06.93#ibcon#flushed, iclass 12, count 0 2006.285.21:11:06.93#ibcon#about to write, iclass 12, count 0 2006.285.21:11:06.93#ibcon#wrote, iclass 12, count 0 2006.285.21:11:06.93#ibcon#about to read 3, iclass 12, count 0 2006.285.21:11:06.95#ibcon#read 3, iclass 12, count 0 2006.285.21:11:06.95#ibcon#about to read 4, iclass 12, count 0 2006.285.21:11:06.95#ibcon#read 4, iclass 12, count 0 2006.285.21:11:06.95#ibcon#about to read 5, iclass 12, count 0 2006.285.21:11:06.95#ibcon#read 5, iclass 12, count 0 2006.285.21:11:06.95#ibcon#about to read 6, iclass 12, count 0 2006.285.21:11:06.95#ibcon#read 6, iclass 12, count 0 2006.285.21:11:06.95#ibcon#end of sib2, iclass 12, count 0 2006.285.21:11:06.95#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:11:06.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:11:06.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:11:06.95#ibcon#*before write, iclass 12, count 0 2006.285.21:11:06.95#ibcon#enter sib2, iclass 12, count 0 2006.285.21:11:06.95#ibcon#flushed, iclass 12, count 0 2006.285.21:11:06.95#ibcon#about to write, iclass 12, count 0 2006.285.21:11:06.95#ibcon#wrote, iclass 12, count 0 2006.285.21:11:06.95#ibcon#about to read 3, iclass 12, count 0 2006.285.21:11:06.99#ibcon#read 3, iclass 12, count 0 2006.285.21:11:06.99#ibcon#about to read 4, iclass 12, count 0 2006.285.21:11:06.99#ibcon#read 4, iclass 12, count 0 2006.285.21:11:06.99#ibcon#about to read 5, iclass 12, count 0 2006.285.21:11:06.99#ibcon#read 5, iclass 12, count 0 2006.285.21:11:06.99#ibcon#about to read 6, iclass 12, count 0 2006.285.21:11:06.99#ibcon#read 6, iclass 12, count 0 2006.285.21:11:06.99#ibcon#end of sib2, iclass 12, count 0 2006.285.21:11:06.99#ibcon#*after write, iclass 12, count 0 2006.285.21:11:06.99#ibcon#*before return 0, iclass 12, count 0 2006.285.21:11:06.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:11:06.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:11:06.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:11:06.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:11:06.99$vck44/va=7,4 2006.285.21:11:06.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.21:11:06.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.21:11:06.99#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:06.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:11:07.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:11:07.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:11:07.05#ibcon#enter wrdev, iclass 14, count 2 2006.285.21:11:07.05#ibcon#first serial, iclass 14, count 2 2006.285.21:11:07.05#ibcon#enter sib2, iclass 14, count 2 2006.285.21:11:07.05#ibcon#flushed, iclass 14, count 2 2006.285.21:11:07.05#ibcon#about to write, iclass 14, count 2 2006.285.21:11:07.05#ibcon#wrote, iclass 14, count 2 2006.285.21:11:07.05#ibcon#about to read 3, iclass 14, count 2 2006.285.21:11:07.07#ibcon#read 3, iclass 14, count 2 2006.285.21:11:07.07#ibcon#about to read 4, iclass 14, count 2 2006.285.21:11:07.07#ibcon#read 4, iclass 14, count 2 2006.285.21:11:07.07#ibcon#about to read 5, iclass 14, count 2 2006.285.21:11:07.07#ibcon#read 5, iclass 14, count 2 2006.285.21:11:07.07#ibcon#about to read 6, iclass 14, count 2 2006.285.21:11:07.07#ibcon#read 6, iclass 14, count 2 2006.285.21:11:07.07#ibcon#end of sib2, iclass 14, count 2 2006.285.21:11:07.07#ibcon#*mode == 0, iclass 14, count 2 2006.285.21:11:07.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.21:11:07.07#ibcon#[25=AT07-04\r\n] 2006.285.21:11:07.07#ibcon#*before write, iclass 14, count 2 2006.285.21:11:07.07#ibcon#enter sib2, iclass 14, count 2 2006.285.21:11:07.07#ibcon#flushed, iclass 14, count 2 2006.285.21:11:07.07#ibcon#about to write, iclass 14, count 2 2006.285.21:11:07.07#ibcon#wrote, iclass 14, count 2 2006.285.21:11:07.07#ibcon#about to read 3, iclass 14, count 2 2006.285.21:11:07.10#ibcon#read 3, iclass 14, count 2 2006.285.21:11:07.10#ibcon#about to read 4, iclass 14, count 2 2006.285.21:11:07.10#ibcon#read 4, iclass 14, count 2 2006.285.21:11:07.10#ibcon#about to read 5, iclass 14, count 2 2006.285.21:11:07.10#ibcon#read 5, iclass 14, count 2 2006.285.21:11:07.10#ibcon#about to read 6, iclass 14, count 2 2006.285.21:11:07.10#ibcon#read 6, iclass 14, count 2 2006.285.21:11:07.10#ibcon#end of sib2, iclass 14, count 2 2006.285.21:11:07.10#ibcon#*after write, iclass 14, count 2 2006.285.21:11:07.10#ibcon#*before return 0, iclass 14, count 2 2006.285.21:11:07.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:11:07.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:11:07.10#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.21:11:07.10#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:07.10#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:11:07.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:11:07.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:11:07.22#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:11:07.22#ibcon#first serial, iclass 14, count 0 2006.285.21:11:07.22#ibcon#enter sib2, iclass 14, count 0 2006.285.21:11:07.22#ibcon#flushed, iclass 14, count 0 2006.285.21:11:07.22#ibcon#about to write, iclass 14, count 0 2006.285.21:11:07.22#ibcon#wrote, iclass 14, count 0 2006.285.21:11:07.22#ibcon#about to read 3, iclass 14, count 0 2006.285.21:11:07.24#ibcon#read 3, iclass 14, count 0 2006.285.21:11:07.24#ibcon#about to read 4, iclass 14, count 0 2006.285.21:11:07.24#ibcon#read 4, iclass 14, count 0 2006.285.21:11:07.24#ibcon#about to read 5, iclass 14, count 0 2006.285.21:11:07.24#ibcon#read 5, iclass 14, count 0 2006.285.21:11:07.24#ibcon#about to read 6, iclass 14, count 0 2006.285.21:11:07.24#ibcon#read 6, iclass 14, count 0 2006.285.21:11:07.24#ibcon#end of sib2, iclass 14, count 0 2006.285.21:11:07.24#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:11:07.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:11:07.24#ibcon#[25=USB\r\n] 2006.285.21:11:07.24#ibcon#*before write, iclass 14, count 0 2006.285.21:11:07.24#ibcon#enter sib2, iclass 14, count 0 2006.285.21:11:07.24#ibcon#flushed, iclass 14, count 0 2006.285.21:11:07.24#ibcon#about to write, iclass 14, count 0 2006.285.21:11:07.24#ibcon#wrote, iclass 14, count 0 2006.285.21:11:07.24#ibcon#about to read 3, iclass 14, count 0 2006.285.21:11:07.27#ibcon#read 3, iclass 14, count 0 2006.285.21:11:07.27#ibcon#about to read 4, iclass 14, count 0 2006.285.21:11:07.27#ibcon#read 4, iclass 14, count 0 2006.285.21:11:07.27#ibcon#about to read 5, iclass 14, count 0 2006.285.21:11:07.27#ibcon#read 5, iclass 14, count 0 2006.285.21:11:07.27#ibcon#about to read 6, iclass 14, count 0 2006.285.21:11:07.27#ibcon#read 6, iclass 14, count 0 2006.285.21:11:07.27#ibcon#end of sib2, iclass 14, count 0 2006.285.21:11:07.27#ibcon#*after write, iclass 14, count 0 2006.285.21:11:07.27#ibcon#*before return 0, iclass 14, count 0 2006.285.21:11:07.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:11:07.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:11:07.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:11:07.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:11:07.27$vck44/valo=8,884.99 2006.285.21:11:07.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.21:11:07.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.21:11:07.27#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:07.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:11:07.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:11:07.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:11:07.27#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:11:07.27#ibcon#first serial, iclass 16, count 0 2006.285.21:11:07.27#ibcon#enter sib2, iclass 16, count 0 2006.285.21:11:07.27#ibcon#flushed, iclass 16, count 0 2006.285.21:11:07.27#ibcon#about to write, iclass 16, count 0 2006.285.21:11:07.27#ibcon#wrote, iclass 16, count 0 2006.285.21:11:07.27#ibcon#about to read 3, iclass 16, count 0 2006.285.21:11:07.29#ibcon#read 3, iclass 16, count 0 2006.285.21:11:07.29#ibcon#about to read 4, iclass 16, count 0 2006.285.21:11:07.29#ibcon#read 4, iclass 16, count 0 2006.285.21:11:07.29#ibcon#about to read 5, iclass 16, count 0 2006.285.21:11:07.29#ibcon#read 5, iclass 16, count 0 2006.285.21:11:07.29#ibcon#about to read 6, iclass 16, count 0 2006.285.21:11:07.29#ibcon#read 6, iclass 16, count 0 2006.285.21:11:07.29#ibcon#end of sib2, iclass 16, count 0 2006.285.21:11:07.29#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:11:07.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:11:07.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:11:07.29#ibcon#*before write, iclass 16, count 0 2006.285.21:11:07.29#ibcon#enter sib2, iclass 16, count 0 2006.285.21:11:07.29#ibcon#flushed, iclass 16, count 0 2006.285.21:11:07.29#ibcon#about to write, iclass 16, count 0 2006.285.21:11:07.29#ibcon#wrote, iclass 16, count 0 2006.285.21:11:07.29#ibcon#about to read 3, iclass 16, count 0 2006.285.21:11:07.33#ibcon#read 3, iclass 16, count 0 2006.285.21:11:07.33#ibcon#about to read 4, iclass 16, count 0 2006.285.21:11:07.33#ibcon#read 4, iclass 16, count 0 2006.285.21:11:07.33#ibcon#about to read 5, iclass 16, count 0 2006.285.21:11:07.33#ibcon#read 5, iclass 16, count 0 2006.285.21:11:07.33#ibcon#about to read 6, iclass 16, count 0 2006.285.21:11:07.33#ibcon#read 6, iclass 16, count 0 2006.285.21:11:07.33#ibcon#end of sib2, iclass 16, count 0 2006.285.21:11:07.33#ibcon#*after write, iclass 16, count 0 2006.285.21:11:07.33#ibcon#*before return 0, iclass 16, count 0 2006.285.21:11:07.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:11:07.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:11:07.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:11:07.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:11:07.33$vck44/va=8,3 2006.285.21:11:07.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.21:11:07.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.21:11:07.33#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:07.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:11:07.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:11:07.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:11:07.39#ibcon#enter wrdev, iclass 18, count 2 2006.285.21:11:07.39#ibcon#first serial, iclass 18, count 2 2006.285.21:11:07.39#ibcon#enter sib2, iclass 18, count 2 2006.285.21:11:07.39#ibcon#flushed, iclass 18, count 2 2006.285.21:11:07.39#ibcon#about to write, iclass 18, count 2 2006.285.21:11:07.39#ibcon#wrote, iclass 18, count 2 2006.285.21:11:07.39#ibcon#about to read 3, iclass 18, count 2 2006.285.21:11:07.41#ibcon#read 3, iclass 18, count 2 2006.285.21:11:07.41#ibcon#about to read 4, iclass 18, count 2 2006.285.21:11:07.41#ibcon#read 4, iclass 18, count 2 2006.285.21:11:07.41#ibcon#about to read 5, iclass 18, count 2 2006.285.21:11:07.41#ibcon#read 5, iclass 18, count 2 2006.285.21:11:07.41#ibcon#about to read 6, iclass 18, count 2 2006.285.21:11:07.41#ibcon#read 6, iclass 18, count 2 2006.285.21:11:07.41#ibcon#end of sib2, iclass 18, count 2 2006.285.21:11:07.41#ibcon#*mode == 0, iclass 18, count 2 2006.285.21:11:07.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.21:11:07.41#ibcon#[25=AT08-03\r\n] 2006.285.21:11:07.41#ibcon#*before write, iclass 18, count 2 2006.285.21:11:07.41#ibcon#enter sib2, iclass 18, count 2 2006.285.21:11:07.41#ibcon#flushed, iclass 18, count 2 2006.285.21:11:07.41#ibcon#about to write, iclass 18, count 2 2006.285.21:11:07.41#ibcon#wrote, iclass 18, count 2 2006.285.21:11:07.41#ibcon#about to read 3, iclass 18, count 2 2006.285.21:11:07.44#ibcon#read 3, iclass 18, count 2 2006.285.21:11:07.44#ibcon#about to read 4, iclass 18, count 2 2006.285.21:11:07.44#ibcon#read 4, iclass 18, count 2 2006.285.21:11:07.44#ibcon#about to read 5, iclass 18, count 2 2006.285.21:11:07.44#ibcon#read 5, iclass 18, count 2 2006.285.21:11:07.44#ibcon#about to read 6, iclass 18, count 2 2006.285.21:11:07.44#ibcon#read 6, iclass 18, count 2 2006.285.21:11:07.44#ibcon#end of sib2, iclass 18, count 2 2006.285.21:11:07.44#ibcon#*after write, iclass 18, count 2 2006.285.21:11:07.44#ibcon#*before return 0, iclass 18, count 2 2006.285.21:11:07.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:11:07.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:11:07.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.21:11:07.44#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:07.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:11:07.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:11:07.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:11:07.56#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:11:07.56#ibcon#first serial, iclass 18, count 0 2006.285.21:11:07.56#ibcon#enter sib2, iclass 18, count 0 2006.285.21:11:07.56#ibcon#flushed, iclass 18, count 0 2006.285.21:11:07.56#ibcon#about to write, iclass 18, count 0 2006.285.21:11:07.56#ibcon#wrote, iclass 18, count 0 2006.285.21:11:07.56#ibcon#about to read 3, iclass 18, count 0 2006.285.21:11:07.58#ibcon#read 3, iclass 18, count 0 2006.285.21:11:07.58#ibcon#about to read 4, iclass 18, count 0 2006.285.21:11:07.58#ibcon#read 4, iclass 18, count 0 2006.285.21:11:07.58#ibcon#about to read 5, iclass 18, count 0 2006.285.21:11:07.58#ibcon#read 5, iclass 18, count 0 2006.285.21:11:07.58#ibcon#about to read 6, iclass 18, count 0 2006.285.21:11:07.58#ibcon#read 6, iclass 18, count 0 2006.285.21:11:07.58#ibcon#end of sib2, iclass 18, count 0 2006.285.21:11:07.58#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:11:07.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:11:07.58#ibcon#[25=USB\r\n] 2006.285.21:11:07.58#ibcon#*before write, iclass 18, count 0 2006.285.21:11:07.58#ibcon#enter sib2, iclass 18, count 0 2006.285.21:11:07.58#ibcon#flushed, iclass 18, count 0 2006.285.21:11:07.58#ibcon#about to write, iclass 18, count 0 2006.285.21:11:07.58#ibcon#wrote, iclass 18, count 0 2006.285.21:11:07.58#ibcon#about to read 3, iclass 18, count 0 2006.285.21:11:07.61#ibcon#read 3, iclass 18, count 0 2006.285.21:11:07.61#ibcon#about to read 4, iclass 18, count 0 2006.285.21:11:07.61#ibcon#read 4, iclass 18, count 0 2006.285.21:11:07.61#ibcon#about to read 5, iclass 18, count 0 2006.285.21:11:07.61#ibcon#read 5, iclass 18, count 0 2006.285.21:11:07.61#ibcon#about to read 6, iclass 18, count 0 2006.285.21:11:07.61#ibcon#read 6, iclass 18, count 0 2006.285.21:11:07.61#ibcon#end of sib2, iclass 18, count 0 2006.285.21:11:07.61#ibcon#*after write, iclass 18, count 0 2006.285.21:11:07.61#ibcon#*before return 0, iclass 18, count 0 2006.285.21:11:07.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:11:07.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:11:07.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:11:07.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:11:07.61$vck44/vblo=1,629.99 2006.285.21:11:07.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.21:11:07.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.21:11:07.61#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:07.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:11:07.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:11:07.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:11:07.61#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:11:07.61#ibcon#first serial, iclass 20, count 0 2006.285.21:11:07.61#ibcon#enter sib2, iclass 20, count 0 2006.285.21:11:07.61#ibcon#flushed, iclass 20, count 0 2006.285.21:11:07.61#ibcon#about to write, iclass 20, count 0 2006.285.21:11:07.61#ibcon#wrote, iclass 20, count 0 2006.285.21:11:07.61#ibcon#about to read 3, iclass 20, count 0 2006.285.21:11:07.63#ibcon#read 3, iclass 20, count 0 2006.285.21:11:07.63#ibcon#about to read 4, iclass 20, count 0 2006.285.21:11:07.63#ibcon#read 4, iclass 20, count 0 2006.285.21:11:07.63#ibcon#about to read 5, iclass 20, count 0 2006.285.21:11:07.63#ibcon#read 5, iclass 20, count 0 2006.285.21:11:07.63#ibcon#about to read 6, iclass 20, count 0 2006.285.21:11:07.63#ibcon#read 6, iclass 20, count 0 2006.285.21:11:07.63#ibcon#end of sib2, iclass 20, count 0 2006.285.21:11:07.63#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:11:07.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:11:07.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:11:07.63#ibcon#*before write, iclass 20, count 0 2006.285.21:11:07.63#ibcon#enter sib2, iclass 20, count 0 2006.285.21:11:07.63#ibcon#flushed, iclass 20, count 0 2006.285.21:11:07.63#ibcon#about to write, iclass 20, count 0 2006.285.21:11:07.63#ibcon#wrote, iclass 20, count 0 2006.285.21:11:07.63#ibcon#about to read 3, iclass 20, count 0 2006.285.21:11:07.67#ibcon#read 3, iclass 20, count 0 2006.285.21:11:07.67#ibcon#about to read 4, iclass 20, count 0 2006.285.21:11:07.67#ibcon#read 4, iclass 20, count 0 2006.285.21:11:07.67#ibcon#about to read 5, iclass 20, count 0 2006.285.21:11:07.67#ibcon#read 5, iclass 20, count 0 2006.285.21:11:07.67#ibcon#about to read 6, iclass 20, count 0 2006.285.21:11:07.67#ibcon#read 6, iclass 20, count 0 2006.285.21:11:07.67#ibcon#end of sib2, iclass 20, count 0 2006.285.21:11:07.67#ibcon#*after write, iclass 20, count 0 2006.285.21:11:07.67#ibcon#*before return 0, iclass 20, count 0 2006.285.21:11:07.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:11:07.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:11:07.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:11:07.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:11:07.67$vck44/vb=1,4 2006.285.21:11:07.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.21:11:07.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.21:11:07.67#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:07.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:11:07.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:11:07.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:11:07.67#ibcon#enter wrdev, iclass 22, count 2 2006.285.21:11:07.67#ibcon#first serial, iclass 22, count 2 2006.285.21:11:07.67#ibcon#enter sib2, iclass 22, count 2 2006.285.21:11:07.67#ibcon#flushed, iclass 22, count 2 2006.285.21:11:07.67#ibcon#about to write, iclass 22, count 2 2006.285.21:11:07.67#ibcon#wrote, iclass 22, count 2 2006.285.21:11:07.67#ibcon#about to read 3, iclass 22, count 2 2006.285.21:11:07.69#ibcon#read 3, iclass 22, count 2 2006.285.21:11:07.69#ibcon#about to read 4, iclass 22, count 2 2006.285.21:11:07.69#ibcon#read 4, iclass 22, count 2 2006.285.21:11:07.69#ibcon#about to read 5, iclass 22, count 2 2006.285.21:11:07.69#ibcon#read 5, iclass 22, count 2 2006.285.21:11:07.69#ibcon#about to read 6, iclass 22, count 2 2006.285.21:11:07.69#ibcon#read 6, iclass 22, count 2 2006.285.21:11:07.69#ibcon#end of sib2, iclass 22, count 2 2006.285.21:11:07.69#ibcon#*mode == 0, iclass 22, count 2 2006.285.21:11:07.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.21:11:07.69#ibcon#[27=AT01-04\r\n] 2006.285.21:11:07.69#ibcon#*before write, iclass 22, count 2 2006.285.21:11:07.69#ibcon#enter sib2, iclass 22, count 2 2006.285.21:11:07.69#ibcon#flushed, iclass 22, count 2 2006.285.21:11:07.69#ibcon#about to write, iclass 22, count 2 2006.285.21:11:07.69#ibcon#wrote, iclass 22, count 2 2006.285.21:11:07.69#ibcon#about to read 3, iclass 22, count 2 2006.285.21:11:07.72#ibcon#read 3, iclass 22, count 2 2006.285.21:11:07.72#ibcon#about to read 4, iclass 22, count 2 2006.285.21:11:07.72#ibcon#read 4, iclass 22, count 2 2006.285.21:11:07.72#ibcon#about to read 5, iclass 22, count 2 2006.285.21:11:07.72#ibcon#read 5, iclass 22, count 2 2006.285.21:11:07.72#ibcon#about to read 6, iclass 22, count 2 2006.285.21:11:07.72#ibcon#read 6, iclass 22, count 2 2006.285.21:11:07.72#ibcon#end of sib2, iclass 22, count 2 2006.285.21:11:07.72#ibcon#*after write, iclass 22, count 2 2006.285.21:11:07.72#ibcon#*before return 0, iclass 22, count 2 2006.285.21:11:07.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:11:07.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:11:07.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.21:11:07.72#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:07.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:11:07.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:11:07.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:11:07.84#ibcon#enter wrdev, iclass 22, count 0 2006.285.21:11:07.84#ibcon#first serial, iclass 22, count 0 2006.285.21:11:07.84#ibcon#enter sib2, iclass 22, count 0 2006.285.21:11:07.84#ibcon#flushed, iclass 22, count 0 2006.285.21:11:07.84#ibcon#about to write, iclass 22, count 0 2006.285.21:11:07.84#ibcon#wrote, iclass 22, count 0 2006.285.21:11:07.84#ibcon#about to read 3, iclass 22, count 0 2006.285.21:11:07.86#ibcon#read 3, iclass 22, count 0 2006.285.21:11:07.86#ibcon#about to read 4, iclass 22, count 0 2006.285.21:11:07.86#ibcon#read 4, iclass 22, count 0 2006.285.21:11:07.86#ibcon#about to read 5, iclass 22, count 0 2006.285.21:11:07.86#ibcon#read 5, iclass 22, count 0 2006.285.21:11:07.86#ibcon#about to read 6, iclass 22, count 0 2006.285.21:11:07.86#ibcon#read 6, iclass 22, count 0 2006.285.21:11:07.86#ibcon#end of sib2, iclass 22, count 0 2006.285.21:11:07.86#ibcon#*mode == 0, iclass 22, count 0 2006.285.21:11:07.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.21:11:07.86#ibcon#[27=USB\r\n] 2006.285.21:11:07.86#ibcon#*before write, iclass 22, count 0 2006.285.21:11:07.86#ibcon#enter sib2, iclass 22, count 0 2006.285.21:11:07.86#ibcon#flushed, iclass 22, count 0 2006.285.21:11:07.86#ibcon#about to write, iclass 22, count 0 2006.285.21:11:07.86#ibcon#wrote, iclass 22, count 0 2006.285.21:11:07.86#ibcon#about to read 3, iclass 22, count 0 2006.285.21:11:07.89#ibcon#read 3, iclass 22, count 0 2006.285.21:11:07.89#ibcon#about to read 4, iclass 22, count 0 2006.285.21:11:07.89#ibcon#read 4, iclass 22, count 0 2006.285.21:11:07.89#ibcon#about to read 5, iclass 22, count 0 2006.285.21:11:07.89#ibcon#read 5, iclass 22, count 0 2006.285.21:11:07.89#ibcon#about to read 6, iclass 22, count 0 2006.285.21:11:07.89#ibcon#read 6, iclass 22, count 0 2006.285.21:11:07.89#ibcon#end of sib2, iclass 22, count 0 2006.285.21:11:07.89#ibcon#*after write, iclass 22, count 0 2006.285.21:11:07.89#ibcon#*before return 0, iclass 22, count 0 2006.285.21:11:07.89#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:11:07.89#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:11:07.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.21:11:07.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.21:11:07.89$vck44/vblo=2,634.99 2006.285.21:11:07.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.21:11:07.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.21:11:07.89#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:07.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:11:07.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:11:07.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:11:07.89#ibcon#enter wrdev, iclass 24, count 0 2006.285.21:11:07.89#ibcon#first serial, iclass 24, count 0 2006.285.21:11:07.89#ibcon#enter sib2, iclass 24, count 0 2006.285.21:11:07.89#ibcon#flushed, iclass 24, count 0 2006.285.21:11:07.89#ibcon#about to write, iclass 24, count 0 2006.285.21:11:07.89#ibcon#wrote, iclass 24, count 0 2006.285.21:11:07.89#ibcon#about to read 3, iclass 24, count 0 2006.285.21:11:07.91#ibcon#read 3, iclass 24, count 0 2006.285.21:11:07.91#ibcon#about to read 4, iclass 24, count 0 2006.285.21:11:07.91#ibcon#read 4, iclass 24, count 0 2006.285.21:11:07.91#ibcon#about to read 5, iclass 24, count 0 2006.285.21:11:07.91#ibcon#read 5, iclass 24, count 0 2006.285.21:11:07.91#ibcon#about to read 6, iclass 24, count 0 2006.285.21:11:07.91#ibcon#read 6, iclass 24, count 0 2006.285.21:11:07.91#ibcon#end of sib2, iclass 24, count 0 2006.285.21:11:07.91#ibcon#*mode == 0, iclass 24, count 0 2006.285.21:11:07.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.21:11:07.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:11:07.91#ibcon#*before write, iclass 24, count 0 2006.285.21:11:07.91#ibcon#enter sib2, iclass 24, count 0 2006.285.21:11:07.91#ibcon#flushed, iclass 24, count 0 2006.285.21:11:07.91#ibcon#about to write, iclass 24, count 0 2006.285.21:11:07.91#ibcon#wrote, iclass 24, count 0 2006.285.21:11:07.91#ibcon#about to read 3, iclass 24, count 0 2006.285.21:11:07.95#ibcon#read 3, iclass 24, count 0 2006.285.21:11:07.95#ibcon#about to read 4, iclass 24, count 0 2006.285.21:11:07.95#ibcon#read 4, iclass 24, count 0 2006.285.21:11:07.95#ibcon#about to read 5, iclass 24, count 0 2006.285.21:11:07.95#ibcon#read 5, iclass 24, count 0 2006.285.21:11:07.95#ibcon#about to read 6, iclass 24, count 0 2006.285.21:11:07.95#ibcon#read 6, iclass 24, count 0 2006.285.21:11:07.95#ibcon#end of sib2, iclass 24, count 0 2006.285.21:11:07.95#ibcon#*after write, iclass 24, count 0 2006.285.21:11:07.95#ibcon#*before return 0, iclass 24, count 0 2006.285.21:11:07.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:11:07.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:11:07.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.21:11:07.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.21:11:07.95$vck44/vb=2,5 2006.285.21:11:07.95#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.21:11:07.95#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.21:11:07.95#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:07.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:11:08.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:11:08.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:11:08.01#ibcon#enter wrdev, iclass 26, count 2 2006.285.21:11:08.01#ibcon#first serial, iclass 26, count 2 2006.285.21:11:08.01#ibcon#enter sib2, iclass 26, count 2 2006.285.21:11:08.01#ibcon#flushed, iclass 26, count 2 2006.285.21:11:08.01#ibcon#about to write, iclass 26, count 2 2006.285.21:11:08.01#ibcon#wrote, iclass 26, count 2 2006.285.21:11:08.01#ibcon#about to read 3, iclass 26, count 2 2006.285.21:11:08.03#ibcon#read 3, iclass 26, count 2 2006.285.21:11:08.03#ibcon#about to read 4, iclass 26, count 2 2006.285.21:11:08.03#ibcon#read 4, iclass 26, count 2 2006.285.21:11:08.03#ibcon#about to read 5, iclass 26, count 2 2006.285.21:11:08.03#ibcon#read 5, iclass 26, count 2 2006.285.21:11:08.03#ibcon#about to read 6, iclass 26, count 2 2006.285.21:11:08.03#ibcon#read 6, iclass 26, count 2 2006.285.21:11:08.03#ibcon#end of sib2, iclass 26, count 2 2006.285.21:11:08.03#ibcon#*mode == 0, iclass 26, count 2 2006.285.21:11:08.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.21:11:08.03#ibcon#[27=AT02-05\r\n] 2006.285.21:11:08.03#ibcon#*before write, iclass 26, count 2 2006.285.21:11:08.03#ibcon#enter sib2, iclass 26, count 2 2006.285.21:11:08.03#ibcon#flushed, iclass 26, count 2 2006.285.21:11:08.03#ibcon#about to write, iclass 26, count 2 2006.285.21:11:08.03#ibcon#wrote, iclass 26, count 2 2006.285.21:11:08.03#ibcon#about to read 3, iclass 26, count 2 2006.285.21:11:08.06#ibcon#read 3, iclass 26, count 2 2006.285.21:11:08.06#ibcon#about to read 4, iclass 26, count 2 2006.285.21:11:08.06#ibcon#read 4, iclass 26, count 2 2006.285.21:11:08.06#ibcon#about to read 5, iclass 26, count 2 2006.285.21:11:08.06#ibcon#read 5, iclass 26, count 2 2006.285.21:11:08.06#ibcon#about to read 6, iclass 26, count 2 2006.285.21:11:08.06#ibcon#read 6, iclass 26, count 2 2006.285.21:11:08.06#ibcon#end of sib2, iclass 26, count 2 2006.285.21:11:08.06#ibcon#*after write, iclass 26, count 2 2006.285.21:11:08.06#ibcon#*before return 0, iclass 26, count 2 2006.285.21:11:08.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:11:08.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:11:08.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.21:11:08.06#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:08.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:11:08.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:11:08.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:11:08.18#ibcon#enter wrdev, iclass 26, count 0 2006.285.21:11:08.18#ibcon#first serial, iclass 26, count 0 2006.285.21:11:08.18#ibcon#enter sib2, iclass 26, count 0 2006.285.21:11:08.18#ibcon#flushed, iclass 26, count 0 2006.285.21:11:08.18#ibcon#about to write, iclass 26, count 0 2006.285.21:11:08.18#ibcon#wrote, iclass 26, count 0 2006.285.21:11:08.18#ibcon#about to read 3, iclass 26, count 0 2006.285.21:11:08.20#ibcon#read 3, iclass 26, count 0 2006.285.21:11:08.20#ibcon#about to read 4, iclass 26, count 0 2006.285.21:11:08.20#ibcon#read 4, iclass 26, count 0 2006.285.21:11:08.20#ibcon#about to read 5, iclass 26, count 0 2006.285.21:11:08.20#ibcon#read 5, iclass 26, count 0 2006.285.21:11:08.20#ibcon#about to read 6, iclass 26, count 0 2006.285.21:11:08.20#ibcon#read 6, iclass 26, count 0 2006.285.21:11:08.20#ibcon#end of sib2, iclass 26, count 0 2006.285.21:11:08.20#ibcon#*mode == 0, iclass 26, count 0 2006.285.21:11:08.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.21:11:08.20#ibcon#[27=USB\r\n] 2006.285.21:11:08.20#ibcon#*before write, iclass 26, count 0 2006.285.21:11:08.20#ibcon#enter sib2, iclass 26, count 0 2006.285.21:11:08.20#ibcon#flushed, iclass 26, count 0 2006.285.21:11:08.20#ibcon#about to write, iclass 26, count 0 2006.285.21:11:08.20#ibcon#wrote, iclass 26, count 0 2006.285.21:11:08.20#ibcon#about to read 3, iclass 26, count 0 2006.285.21:11:08.23#ibcon#read 3, iclass 26, count 0 2006.285.21:11:08.23#ibcon#about to read 4, iclass 26, count 0 2006.285.21:11:08.23#ibcon#read 4, iclass 26, count 0 2006.285.21:11:08.23#ibcon#about to read 5, iclass 26, count 0 2006.285.21:11:08.23#ibcon#read 5, iclass 26, count 0 2006.285.21:11:08.23#ibcon#about to read 6, iclass 26, count 0 2006.285.21:11:08.23#ibcon#read 6, iclass 26, count 0 2006.285.21:11:08.23#ibcon#end of sib2, iclass 26, count 0 2006.285.21:11:08.23#ibcon#*after write, iclass 26, count 0 2006.285.21:11:08.23#ibcon#*before return 0, iclass 26, count 0 2006.285.21:11:08.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:11:08.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:11:08.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.21:11:08.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.21:11:08.23$vck44/vblo=3,649.99 2006.285.21:11:08.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.21:11:08.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.21:11:08.23#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:08.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:11:08.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:11:08.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:11:08.23#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:11:08.23#ibcon#first serial, iclass 28, count 0 2006.285.21:11:08.23#ibcon#enter sib2, iclass 28, count 0 2006.285.21:11:08.23#ibcon#flushed, iclass 28, count 0 2006.285.21:11:08.23#ibcon#about to write, iclass 28, count 0 2006.285.21:11:08.23#ibcon#wrote, iclass 28, count 0 2006.285.21:11:08.23#ibcon#about to read 3, iclass 28, count 0 2006.285.21:11:08.25#ibcon#read 3, iclass 28, count 0 2006.285.21:11:08.25#ibcon#about to read 4, iclass 28, count 0 2006.285.21:11:08.25#ibcon#read 4, iclass 28, count 0 2006.285.21:11:08.25#ibcon#about to read 5, iclass 28, count 0 2006.285.21:11:08.25#ibcon#read 5, iclass 28, count 0 2006.285.21:11:08.25#ibcon#about to read 6, iclass 28, count 0 2006.285.21:11:08.25#ibcon#read 6, iclass 28, count 0 2006.285.21:11:08.25#ibcon#end of sib2, iclass 28, count 0 2006.285.21:11:08.25#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:11:08.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:11:08.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:11:08.25#ibcon#*before write, iclass 28, count 0 2006.285.21:11:08.25#ibcon#enter sib2, iclass 28, count 0 2006.285.21:11:08.25#ibcon#flushed, iclass 28, count 0 2006.285.21:11:08.25#ibcon#about to write, iclass 28, count 0 2006.285.21:11:08.25#ibcon#wrote, iclass 28, count 0 2006.285.21:11:08.25#ibcon#about to read 3, iclass 28, count 0 2006.285.21:11:08.29#ibcon#read 3, iclass 28, count 0 2006.285.21:11:08.29#ibcon#about to read 4, iclass 28, count 0 2006.285.21:11:08.29#ibcon#read 4, iclass 28, count 0 2006.285.21:11:08.29#ibcon#about to read 5, iclass 28, count 0 2006.285.21:11:08.29#ibcon#read 5, iclass 28, count 0 2006.285.21:11:08.29#ibcon#about to read 6, iclass 28, count 0 2006.285.21:11:08.29#ibcon#read 6, iclass 28, count 0 2006.285.21:11:08.29#ibcon#end of sib2, iclass 28, count 0 2006.285.21:11:08.29#ibcon#*after write, iclass 28, count 0 2006.285.21:11:08.29#ibcon#*before return 0, iclass 28, count 0 2006.285.21:11:08.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:11:08.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:11:08.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:11:08.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:11:08.29$vck44/vb=3,4 2006.285.21:11:08.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.21:11:08.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.21:11:08.29#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:08.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:11:08.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:11:08.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:11:08.35#ibcon#enter wrdev, iclass 30, count 2 2006.285.21:11:08.35#ibcon#first serial, iclass 30, count 2 2006.285.21:11:08.35#ibcon#enter sib2, iclass 30, count 2 2006.285.21:11:08.35#ibcon#flushed, iclass 30, count 2 2006.285.21:11:08.35#ibcon#about to write, iclass 30, count 2 2006.285.21:11:08.35#ibcon#wrote, iclass 30, count 2 2006.285.21:11:08.35#ibcon#about to read 3, iclass 30, count 2 2006.285.21:11:08.37#ibcon#read 3, iclass 30, count 2 2006.285.21:11:08.37#ibcon#about to read 4, iclass 30, count 2 2006.285.21:11:08.37#ibcon#read 4, iclass 30, count 2 2006.285.21:11:08.37#ibcon#about to read 5, iclass 30, count 2 2006.285.21:11:08.37#ibcon#read 5, iclass 30, count 2 2006.285.21:11:08.37#ibcon#about to read 6, iclass 30, count 2 2006.285.21:11:08.37#ibcon#read 6, iclass 30, count 2 2006.285.21:11:08.37#ibcon#end of sib2, iclass 30, count 2 2006.285.21:11:08.37#ibcon#*mode == 0, iclass 30, count 2 2006.285.21:11:08.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.21:11:08.37#ibcon#[27=AT03-04\r\n] 2006.285.21:11:08.37#ibcon#*before write, iclass 30, count 2 2006.285.21:11:08.37#ibcon#enter sib2, iclass 30, count 2 2006.285.21:11:08.37#ibcon#flushed, iclass 30, count 2 2006.285.21:11:08.37#ibcon#about to write, iclass 30, count 2 2006.285.21:11:08.37#ibcon#wrote, iclass 30, count 2 2006.285.21:11:08.37#ibcon#about to read 3, iclass 30, count 2 2006.285.21:11:08.40#ibcon#read 3, iclass 30, count 2 2006.285.21:11:08.40#ibcon#about to read 4, iclass 30, count 2 2006.285.21:11:08.40#ibcon#read 4, iclass 30, count 2 2006.285.21:11:08.40#ibcon#about to read 5, iclass 30, count 2 2006.285.21:11:08.40#ibcon#read 5, iclass 30, count 2 2006.285.21:11:08.40#ibcon#about to read 6, iclass 30, count 2 2006.285.21:11:08.40#ibcon#read 6, iclass 30, count 2 2006.285.21:11:08.40#ibcon#end of sib2, iclass 30, count 2 2006.285.21:11:08.40#ibcon#*after write, iclass 30, count 2 2006.285.21:11:08.40#ibcon#*before return 0, iclass 30, count 2 2006.285.21:11:08.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:11:08.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:11:08.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.21:11:08.40#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:08.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:11:08.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:11:08.71#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:11:08.71#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:11:08.71#ibcon#first serial, iclass 30, count 0 2006.285.21:11:08.71#ibcon#enter sib2, iclass 30, count 0 2006.285.21:11:08.71#ibcon#flushed, iclass 30, count 0 2006.285.21:11:08.71#ibcon#about to write, iclass 30, count 0 2006.285.21:11:08.71#ibcon#wrote, iclass 30, count 0 2006.285.21:11:08.71#ibcon#about to read 3, iclass 30, count 0 2006.285.21:11:08.73#ibcon#read 3, iclass 30, count 0 2006.285.21:11:08.73#ibcon#about to read 4, iclass 30, count 0 2006.285.21:11:08.73#ibcon#read 4, iclass 30, count 0 2006.285.21:11:08.73#ibcon#about to read 5, iclass 30, count 0 2006.285.21:11:08.73#ibcon#read 5, iclass 30, count 0 2006.285.21:11:08.73#ibcon#about to read 6, iclass 30, count 0 2006.285.21:11:08.73#ibcon#read 6, iclass 30, count 0 2006.285.21:11:08.73#ibcon#end of sib2, iclass 30, count 0 2006.285.21:11:08.73#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:11:08.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:11:08.73#ibcon#[27=USB\r\n] 2006.285.21:11:08.73#ibcon#*before write, iclass 30, count 0 2006.285.21:11:08.73#ibcon#enter sib2, iclass 30, count 0 2006.285.21:11:08.73#ibcon#flushed, iclass 30, count 0 2006.285.21:11:08.73#ibcon#about to write, iclass 30, count 0 2006.285.21:11:08.73#ibcon#wrote, iclass 30, count 0 2006.285.21:11:08.73#ibcon#about to read 3, iclass 30, count 0 2006.285.21:11:08.76#ibcon#read 3, iclass 30, count 0 2006.285.21:11:08.76#ibcon#about to read 4, iclass 30, count 0 2006.285.21:11:08.76#ibcon#read 4, iclass 30, count 0 2006.285.21:11:08.76#ibcon#about to read 5, iclass 30, count 0 2006.285.21:11:08.76#ibcon#read 5, iclass 30, count 0 2006.285.21:11:08.76#ibcon#about to read 6, iclass 30, count 0 2006.285.21:11:08.76#ibcon#read 6, iclass 30, count 0 2006.285.21:11:08.76#ibcon#end of sib2, iclass 30, count 0 2006.285.21:11:08.76#ibcon#*after write, iclass 30, count 0 2006.285.21:11:08.76#ibcon#*before return 0, iclass 30, count 0 2006.285.21:11:08.76#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:11:08.76#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:11:08.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:11:08.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:11:08.76$vck44/vblo=4,679.99 2006.285.21:11:08.76#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.21:11:08.76#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.21:11:08.76#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:08.76#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:11:08.76#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:11:08.76#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:11:08.76#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:11:08.76#ibcon#first serial, iclass 32, count 0 2006.285.21:11:08.76#ibcon#enter sib2, iclass 32, count 0 2006.285.21:11:08.76#ibcon#flushed, iclass 32, count 0 2006.285.21:11:08.76#ibcon#about to write, iclass 32, count 0 2006.285.21:11:08.76#ibcon#wrote, iclass 32, count 0 2006.285.21:11:08.76#ibcon#about to read 3, iclass 32, count 0 2006.285.21:11:08.78#ibcon#read 3, iclass 32, count 0 2006.285.21:11:08.78#ibcon#about to read 4, iclass 32, count 0 2006.285.21:11:08.78#ibcon#read 4, iclass 32, count 0 2006.285.21:11:08.78#ibcon#about to read 5, iclass 32, count 0 2006.285.21:11:08.78#ibcon#read 5, iclass 32, count 0 2006.285.21:11:08.78#ibcon#about to read 6, iclass 32, count 0 2006.285.21:11:08.78#ibcon#read 6, iclass 32, count 0 2006.285.21:11:08.78#ibcon#end of sib2, iclass 32, count 0 2006.285.21:11:08.78#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:11:08.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:11:08.78#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:11:08.78#ibcon#*before write, iclass 32, count 0 2006.285.21:11:08.78#ibcon#enter sib2, iclass 32, count 0 2006.285.21:11:08.78#ibcon#flushed, iclass 32, count 0 2006.285.21:11:08.78#ibcon#about to write, iclass 32, count 0 2006.285.21:11:08.78#ibcon#wrote, iclass 32, count 0 2006.285.21:11:08.78#ibcon#about to read 3, iclass 32, count 0 2006.285.21:11:08.82#ibcon#read 3, iclass 32, count 0 2006.285.21:11:08.82#ibcon#about to read 4, iclass 32, count 0 2006.285.21:11:08.82#ibcon#read 4, iclass 32, count 0 2006.285.21:11:08.82#ibcon#about to read 5, iclass 32, count 0 2006.285.21:11:08.82#ibcon#read 5, iclass 32, count 0 2006.285.21:11:08.82#ibcon#about to read 6, iclass 32, count 0 2006.285.21:11:08.82#ibcon#read 6, iclass 32, count 0 2006.285.21:11:08.82#ibcon#end of sib2, iclass 32, count 0 2006.285.21:11:08.82#ibcon#*after write, iclass 32, count 0 2006.285.21:11:08.82#ibcon#*before return 0, iclass 32, count 0 2006.285.21:11:08.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:11:08.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:11:08.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:11:08.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:11:08.82$vck44/vb=4,5 2006.285.21:11:08.82#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.21:11:08.82#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.21:11:08.82#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:08.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:11:08.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:11:08.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:11:08.88#ibcon#enter wrdev, iclass 34, count 2 2006.285.21:11:08.88#ibcon#first serial, iclass 34, count 2 2006.285.21:11:08.88#ibcon#enter sib2, iclass 34, count 2 2006.285.21:11:08.88#ibcon#flushed, iclass 34, count 2 2006.285.21:11:08.88#ibcon#about to write, iclass 34, count 2 2006.285.21:11:08.88#ibcon#wrote, iclass 34, count 2 2006.285.21:11:08.88#ibcon#about to read 3, iclass 34, count 2 2006.285.21:11:08.90#ibcon#read 3, iclass 34, count 2 2006.285.21:11:08.90#ibcon#about to read 4, iclass 34, count 2 2006.285.21:11:08.90#ibcon#read 4, iclass 34, count 2 2006.285.21:11:08.90#ibcon#about to read 5, iclass 34, count 2 2006.285.21:11:08.90#ibcon#read 5, iclass 34, count 2 2006.285.21:11:08.90#ibcon#about to read 6, iclass 34, count 2 2006.285.21:11:08.90#ibcon#read 6, iclass 34, count 2 2006.285.21:11:08.90#ibcon#end of sib2, iclass 34, count 2 2006.285.21:11:08.90#ibcon#*mode == 0, iclass 34, count 2 2006.285.21:11:08.90#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.21:11:08.90#ibcon#[27=AT04-05\r\n] 2006.285.21:11:08.90#ibcon#*before write, iclass 34, count 2 2006.285.21:11:08.90#ibcon#enter sib2, iclass 34, count 2 2006.285.21:11:08.90#ibcon#flushed, iclass 34, count 2 2006.285.21:11:08.90#ibcon#about to write, iclass 34, count 2 2006.285.21:11:08.90#ibcon#wrote, iclass 34, count 2 2006.285.21:11:08.90#ibcon#about to read 3, iclass 34, count 2 2006.285.21:11:08.93#ibcon#read 3, iclass 34, count 2 2006.285.21:11:08.93#ibcon#about to read 4, iclass 34, count 2 2006.285.21:11:08.93#ibcon#read 4, iclass 34, count 2 2006.285.21:11:08.93#ibcon#about to read 5, iclass 34, count 2 2006.285.21:11:08.93#ibcon#read 5, iclass 34, count 2 2006.285.21:11:08.93#ibcon#about to read 6, iclass 34, count 2 2006.285.21:11:08.93#ibcon#read 6, iclass 34, count 2 2006.285.21:11:08.93#ibcon#end of sib2, iclass 34, count 2 2006.285.21:11:08.93#ibcon#*after write, iclass 34, count 2 2006.285.21:11:08.93#ibcon#*before return 0, iclass 34, count 2 2006.285.21:11:08.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:11:08.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:11:08.93#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.21:11:08.93#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:08.93#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:11:09.05#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:11:09.05#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:11:09.05#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:11:09.05#ibcon#first serial, iclass 34, count 0 2006.285.21:11:09.05#ibcon#enter sib2, iclass 34, count 0 2006.285.21:11:09.05#ibcon#flushed, iclass 34, count 0 2006.285.21:11:09.05#ibcon#about to write, iclass 34, count 0 2006.285.21:11:09.05#ibcon#wrote, iclass 34, count 0 2006.285.21:11:09.05#ibcon#about to read 3, iclass 34, count 0 2006.285.21:11:09.07#ibcon#read 3, iclass 34, count 0 2006.285.21:11:09.07#ibcon#about to read 4, iclass 34, count 0 2006.285.21:11:09.07#ibcon#read 4, iclass 34, count 0 2006.285.21:11:09.07#ibcon#about to read 5, iclass 34, count 0 2006.285.21:11:09.07#ibcon#read 5, iclass 34, count 0 2006.285.21:11:09.07#ibcon#about to read 6, iclass 34, count 0 2006.285.21:11:09.07#ibcon#read 6, iclass 34, count 0 2006.285.21:11:09.07#ibcon#end of sib2, iclass 34, count 0 2006.285.21:11:09.07#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:11:09.07#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:11:09.07#ibcon#[27=USB\r\n] 2006.285.21:11:09.07#ibcon#*before write, iclass 34, count 0 2006.285.21:11:09.07#ibcon#enter sib2, iclass 34, count 0 2006.285.21:11:09.07#ibcon#flushed, iclass 34, count 0 2006.285.21:11:09.07#ibcon#about to write, iclass 34, count 0 2006.285.21:11:09.07#ibcon#wrote, iclass 34, count 0 2006.285.21:11:09.07#ibcon#about to read 3, iclass 34, count 0 2006.285.21:11:09.10#ibcon#read 3, iclass 34, count 0 2006.285.21:11:09.10#ibcon#about to read 4, iclass 34, count 0 2006.285.21:11:09.10#ibcon#read 4, iclass 34, count 0 2006.285.21:11:09.10#ibcon#about to read 5, iclass 34, count 0 2006.285.21:11:09.10#ibcon#read 5, iclass 34, count 0 2006.285.21:11:09.10#ibcon#about to read 6, iclass 34, count 0 2006.285.21:11:09.10#ibcon#read 6, iclass 34, count 0 2006.285.21:11:09.10#ibcon#end of sib2, iclass 34, count 0 2006.285.21:11:09.10#ibcon#*after write, iclass 34, count 0 2006.285.21:11:09.10#ibcon#*before return 0, iclass 34, count 0 2006.285.21:11:09.10#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:11:09.10#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:11:09.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:11:09.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:11:09.10$vck44/vblo=5,709.99 2006.285.21:11:09.10#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.21:11:09.10#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.21:11:09.10#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:09.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:11:09.10#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:11:09.10#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:11:09.10#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:11:09.10#ibcon#first serial, iclass 36, count 0 2006.285.21:11:09.10#ibcon#enter sib2, iclass 36, count 0 2006.285.21:11:09.10#ibcon#flushed, iclass 36, count 0 2006.285.21:11:09.10#ibcon#about to write, iclass 36, count 0 2006.285.21:11:09.10#ibcon#wrote, iclass 36, count 0 2006.285.21:11:09.10#ibcon#about to read 3, iclass 36, count 0 2006.285.21:11:09.12#ibcon#read 3, iclass 36, count 0 2006.285.21:11:09.12#ibcon#about to read 4, iclass 36, count 0 2006.285.21:11:09.12#ibcon#read 4, iclass 36, count 0 2006.285.21:11:09.12#ibcon#about to read 5, iclass 36, count 0 2006.285.21:11:09.12#ibcon#read 5, iclass 36, count 0 2006.285.21:11:09.12#ibcon#about to read 6, iclass 36, count 0 2006.285.21:11:09.12#ibcon#read 6, iclass 36, count 0 2006.285.21:11:09.12#ibcon#end of sib2, iclass 36, count 0 2006.285.21:11:09.12#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:11:09.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:11:09.12#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:11:09.12#ibcon#*before write, iclass 36, count 0 2006.285.21:11:09.12#ibcon#enter sib2, iclass 36, count 0 2006.285.21:11:09.12#ibcon#flushed, iclass 36, count 0 2006.285.21:11:09.12#ibcon#about to write, iclass 36, count 0 2006.285.21:11:09.12#ibcon#wrote, iclass 36, count 0 2006.285.21:11:09.12#ibcon#about to read 3, iclass 36, count 0 2006.285.21:11:09.16#ibcon#read 3, iclass 36, count 0 2006.285.21:11:09.16#ibcon#about to read 4, iclass 36, count 0 2006.285.21:11:09.16#ibcon#read 4, iclass 36, count 0 2006.285.21:11:09.16#ibcon#about to read 5, iclass 36, count 0 2006.285.21:11:09.16#ibcon#read 5, iclass 36, count 0 2006.285.21:11:09.16#ibcon#about to read 6, iclass 36, count 0 2006.285.21:11:09.16#ibcon#read 6, iclass 36, count 0 2006.285.21:11:09.16#ibcon#end of sib2, iclass 36, count 0 2006.285.21:11:09.16#ibcon#*after write, iclass 36, count 0 2006.285.21:11:09.16#ibcon#*before return 0, iclass 36, count 0 2006.285.21:11:09.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:11:09.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:11:09.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:11:09.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:11:09.16$vck44/vb=5,4 2006.285.21:11:09.16#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.21:11:09.16#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.21:11:09.16#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:09.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:11:09.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:11:09.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:11:09.22#ibcon#enter wrdev, iclass 38, count 2 2006.285.21:11:09.22#ibcon#first serial, iclass 38, count 2 2006.285.21:11:09.22#ibcon#enter sib2, iclass 38, count 2 2006.285.21:11:09.22#ibcon#flushed, iclass 38, count 2 2006.285.21:11:09.22#ibcon#about to write, iclass 38, count 2 2006.285.21:11:09.22#ibcon#wrote, iclass 38, count 2 2006.285.21:11:09.22#ibcon#about to read 3, iclass 38, count 2 2006.285.21:11:09.24#ibcon#read 3, iclass 38, count 2 2006.285.21:11:09.24#ibcon#about to read 4, iclass 38, count 2 2006.285.21:11:09.24#ibcon#read 4, iclass 38, count 2 2006.285.21:11:09.24#ibcon#about to read 5, iclass 38, count 2 2006.285.21:11:09.24#ibcon#read 5, iclass 38, count 2 2006.285.21:11:09.24#ibcon#about to read 6, iclass 38, count 2 2006.285.21:11:09.24#ibcon#read 6, iclass 38, count 2 2006.285.21:11:09.24#ibcon#end of sib2, iclass 38, count 2 2006.285.21:11:09.24#ibcon#*mode == 0, iclass 38, count 2 2006.285.21:11:09.24#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.21:11:09.24#ibcon#[27=AT05-04\r\n] 2006.285.21:11:09.24#ibcon#*before write, iclass 38, count 2 2006.285.21:11:09.24#ibcon#enter sib2, iclass 38, count 2 2006.285.21:11:09.24#ibcon#flushed, iclass 38, count 2 2006.285.21:11:09.24#ibcon#about to write, iclass 38, count 2 2006.285.21:11:09.24#ibcon#wrote, iclass 38, count 2 2006.285.21:11:09.24#ibcon#about to read 3, iclass 38, count 2 2006.285.21:11:09.27#ibcon#read 3, iclass 38, count 2 2006.285.21:11:09.27#ibcon#about to read 4, iclass 38, count 2 2006.285.21:11:09.27#ibcon#read 4, iclass 38, count 2 2006.285.21:11:09.27#ibcon#about to read 5, iclass 38, count 2 2006.285.21:11:09.27#ibcon#read 5, iclass 38, count 2 2006.285.21:11:09.27#ibcon#about to read 6, iclass 38, count 2 2006.285.21:11:09.27#ibcon#read 6, iclass 38, count 2 2006.285.21:11:09.27#ibcon#end of sib2, iclass 38, count 2 2006.285.21:11:09.27#ibcon#*after write, iclass 38, count 2 2006.285.21:11:09.27#ibcon#*before return 0, iclass 38, count 2 2006.285.21:11:09.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:11:09.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:11:09.27#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.21:11:09.27#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:09.27#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:11:09.39#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:11:09.39#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:11:09.39#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:11:09.39#ibcon#first serial, iclass 38, count 0 2006.285.21:11:09.39#ibcon#enter sib2, iclass 38, count 0 2006.285.21:11:09.39#ibcon#flushed, iclass 38, count 0 2006.285.21:11:09.39#ibcon#about to write, iclass 38, count 0 2006.285.21:11:09.39#ibcon#wrote, iclass 38, count 0 2006.285.21:11:09.39#ibcon#about to read 3, iclass 38, count 0 2006.285.21:11:09.41#ibcon#read 3, iclass 38, count 0 2006.285.21:11:09.41#ibcon#about to read 4, iclass 38, count 0 2006.285.21:11:09.41#ibcon#read 4, iclass 38, count 0 2006.285.21:11:09.41#ibcon#about to read 5, iclass 38, count 0 2006.285.21:11:09.41#ibcon#read 5, iclass 38, count 0 2006.285.21:11:09.41#ibcon#about to read 6, iclass 38, count 0 2006.285.21:11:09.41#ibcon#read 6, iclass 38, count 0 2006.285.21:11:09.41#ibcon#end of sib2, iclass 38, count 0 2006.285.21:11:09.41#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:11:09.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:11:09.41#ibcon#[27=USB\r\n] 2006.285.21:11:09.41#ibcon#*before write, iclass 38, count 0 2006.285.21:11:09.41#ibcon#enter sib2, iclass 38, count 0 2006.285.21:11:09.41#ibcon#flushed, iclass 38, count 0 2006.285.21:11:09.41#ibcon#about to write, iclass 38, count 0 2006.285.21:11:09.41#ibcon#wrote, iclass 38, count 0 2006.285.21:11:09.41#ibcon#about to read 3, iclass 38, count 0 2006.285.21:11:09.44#ibcon#read 3, iclass 38, count 0 2006.285.21:11:09.44#ibcon#about to read 4, iclass 38, count 0 2006.285.21:11:09.44#ibcon#read 4, iclass 38, count 0 2006.285.21:11:09.44#ibcon#about to read 5, iclass 38, count 0 2006.285.21:11:09.44#ibcon#read 5, iclass 38, count 0 2006.285.21:11:09.44#ibcon#about to read 6, iclass 38, count 0 2006.285.21:11:09.44#ibcon#read 6, iclass 38, count 0 2006.285.21:11:09.44#ibcon#end of sib2, iclass 38, count 0 2006.285.21:11:09.44#ibcon#*after write, iclass 38, count 0 2006.285.21:11:09.44#ibcon#*before return 0, iclass 38, count 0 2006.285.21:11:09.44#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:11:09.44#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:11:09.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:11:09.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:11:09.44$vck44/vblo=6,719.99 2006.285.21:11:09.44#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.21:11:09.44#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.21:11:09.44#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:09.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:11:09.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:11:09.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:11:09.44#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:11:09.44#ibcon#first serial, iclass 40, count 0 2006.285.21:11:09.44#ibcon#enter sib2, iclass 40, count 0 2006.285.21:11:09.44#ibcon#flushed, iclass 40, count 0 2006.285.21:11:09.44#ibcon#about to write, iclass 40, count 0 2006.285.21:11:09.44#ibcon#wrote, iclass 40, count 0 2006.285.21:11:09.44#ibcon#about to read 3, iclass 40, count 0 2006.285.21:11:09.46#ibcon#read 3, iclass 40, count 0 2006.285.21:11:09.48#ibcon#about to read 4, iclass 40, count 0 2006.285.21:11:09.48#ibcon#read 4, iclass 40, count 0 2006.285.21:11:09.48#ibcon#about to read 5, iclass 40, count 0 2006.285.21:11:09.48#ibcon#read 5, iclass 40, count 0 2006.285.21:11:09.48#ibcon#about to read 6, iclass 40, count 0 2006.285.21:11:09.48#ibcon#read 6, iclass 40, count 0 2006.285.21:11:09.48#ibcon#end of sib2, iclass 40, count 0 2006.285.21:11:09.48#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:11:09.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:11:09.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:11:09.48#ibcon#*before write, iclass 40, count 0 2006.285.21:11:09.48#ibcon#enter sib2, iclass 40, count 0 2006.285.21:11:09.48#ibcon#flushed, iclass 40, count 0 2006.285.21:11:09.48#ibcon#about to write, iclass 40, count 0 2006.285.21:11:09.48#ibcon#wrote, iclass 40, count 0 2006.285.21:11:09.48#ibcon#about to read 3, iclass 40, count 0 2006.285.21:11:09.52#ibcon#read 3, iclass 40, count 0 2006.285.21:11:09.52#ibcon#about to read 4, iclass 40, count 0 2006.285.21:11:09.52#ibcon#read 4, iclass 40, count 0 2006.285.21:11:09.52#ibcon#about to read 5, iclass 40, count 0 2006.285.21:11:09.52#ibcon#read 5, iclass 40, count 0 2006.285.21:11:09.52#ibcon#about to read 6, iclass 40, count 0 2006.285.21:11:09.52#ibcon#read 6, iclass 40, count 0 2006.285.21:11:09.52#ibcon#end of sib2, iclass 40, count 0 2006.285.21:11:09.52#ibcon#*after write, iclass 40, count 0 2006.285.21:11:09.52#ibcon#*before return 0, iclass 40, count 0 2006.285.21:11:09.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:11:09.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:11:09.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:11:09.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:11:09.52$vck44/vb=6,3 2006.285.21:11:09.52#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.21:11:09.52#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.21:11:09.52#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:09.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:11:09.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:11:09.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:11:09.56#ibcon#enter wrdev, iclass 4, count 2 2006.285.21:11:09.56#ibcon#first serial, iclass 4, count 2 2006.285.21:11:09.56#ibcon#enter sib2, iclass 4, count 2 2006.285.21:11:09.56#ibcon#flushed, iclass 4, count 2 2006.285.21:11:09.56#ibcon#about to write, iclass 4, count 2 2006.285.21:11:09.56#ibcon#wrote, iclass 4, count 2 2006.285.21:11:09.56#ibcon#about to read 3, iclass 4, count 2 2006.285.21:11:09.58#ibcon#read 3, iclass 4, count 2 2006.285.21:11:09.58#ibcon#about to read 4, iclass 4, count 2 2006.285.21:11:09.58#ibcon#read 4, iclass 4, count 2 2006.285.21:11:09.58#ibcon#about to read 5, iclass 4, count 2 2006.285.21:11:09.58#ibcon#read 5, iclass 4, count 2 2006.285.21:11:09.58#ibcon#about to read 6, iclass 4, count 2 2006.285.21:11:09.58#ibcon#read 6, iclass 4, count 2 2006.285.21:11:09.58#ibcon#end of sib2, iclass 4, count 2 2006.285.21:11:09.58#ibcon#*mode == 0, iclass 4, count 2 2006.285.21:11:09.58#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.21:11:09.58#ibcon#[27=AT06-03\r\n] 2006.285.21:11:09.58#ibcon#*before write, iclass 4, count 2 2006.285.21:11:09.58#ibcon#enter sib2, iclass 4, count 2 2006.285.21:11:09.58#ibcon#flushed, iclass 4, count 2 2006.285.21:11:09.58#ibcon#about to write, iclass 4, count 2 2006.285.21:11:09.58#ibcon#wrote, iclass 4, count 2 2006.285.21:11:09.58#ibcon#about to read 3, iclass 4, count 2 2006.285.21:11:09.61#ibcon#read 3, iclass 4, count 2 2006.285.21:11:09.61#ibcon#about to read 4, iclass 4, count 2 2006.285.21:11:09.61#ibcon#read 4, iclass 4, count 2 2006.285.21:11:09.61#ibcon#about to read 5, iclass 4, count 2 2006.285.21:11:09.61#ibcon#read 5, iclass 4, count 2 2006.285.21:11:09.61#ibcon#about to read 6, iclass 4, count 2 2006.285.21:11:09.61#ibcon#read 6, iclass 4, count 2 2006.285.21:11:09.61#ibcon#end of sib2, iclass 4, count 2 2006.285.21:11:09.61#ibcon#*after write, iclass 4, count 2 2006.285.21:11:09.61#ibcon#*before return 0, iclass 4, count 2 2006.285.21:11:09.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:11:09.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:11:09.61#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.21:11:09.61#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:09.61#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:11:09.73#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:11:09.73#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:11:09.73#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:11:09.73#ibcon#first serial, iclass 4, count 0 2006.285.21:11:09.73#ibcon#enter sib2, iclass 4, count 0 2006.285.21:11:09.73#ibcon#flushed, iclass 4, count 0 2006.285.21:11:09.73#ibcon#about to write, iclass 4, count 0 2006.285.21:11:09.73#ibcon#wrote, iclass 4, count 0 2006.285.21:11:09.73#ibcon#about to read 3, iclass 4, count 0 2006.285.21:11:09.75#ibcon#read 3, iclass 4, count 0 2006.285.21:11:09.75#ibcon#about to read 4, iclass 4, count 0 2006.285.21:11:09.75#ibcon#read 4, iclass 4, count 0 2006.285.21:11:09.75#ibcon#about to read 5, iclass 4, count 0 2006.285.21:11:09.75#ibcon#read 5, iclass 4, count 0 2006.285.21:11:09.75#ibcon#about to read 6, iclass 4, count 0 2006.285.21:11:09.75#ibcon#read 6, iclass 4, count 0 2006.285.21:11:09.75#ibcon#end of sib2, iclass 4, count 0 2006.285.21:11:09.75#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:11:09.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:11:09.75#ibcon#[27=USB\r\n] 2006.285.21:11:09.75#ibcon#*before write, iclass 4, count 0 2006.285.21:11:09.75#ibcon#enter sib2, iclass 4, count 0 2006.285.21:11:09.75#ibcon#flushed, iclass 4, count 0 2006.285.21:11:09.75#ibcon#about to write, iclass 4, count 0 2006.285.21:11:09.75#ibcon#wrote, iclass 4, count 0 2006.285.21:11:09.75#ibcon#about to read 3, iclass 4, count 0 2006.285.21:11:09.78#ibcon#read 3, iclass 4, count 0 2006.285.21:11:09.78#ibcon#about to read 4, iclass 4, count 0 2006.285.21:11:09.78#ibcon#read 4, iclass 4, count 0 2006.285.21:11:09.78#ibcon#about to read 5, iclass 4, count 0 2006.285.21:11:09.78#ibcon#read 5, iclass 4, count 0 2006.285.21:11:09.78#ibcon#about to read 6, iclass 4, count 0 2006.285.21:11:09.78#ibcon#read 6, iclass 4, count 0 2006.285.21:11:09.78#ibcon#end of sib2, iclass 4, count 0 2006.285.21:11:09.78#ibcon#*after write, iclass 4, count 0 2006.285.21:11:09.78#ibcon#*before return 0, iclass 4, count 0 2006.285.21:11:09.78#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:11:09.78#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:11:09.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:11:09.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:11:09.78$vck44/vblo=7,734.99 2006.285.21:11:09.78#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.21:11:09.78#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.21:11:09.78#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:09.78#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:11:09.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:11:09.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:11:09.78#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:11:09.78#ibcon#first serial, iclass 6, count 0 2006.285.21:11:09.78#ibcon#enter sib2, iclass 6, count 0 2006.285.21:11:09.78#ibcon#flushed, iclass 6, count 0 2006.285.21:11:09.78#ibcon#about to write, iclass 6, count 0 2006.285.21:11:09.78#ibcon#wrote, iclass 6, count 0 2006.285.21:11:09.78#ibcon#about to read 3, iclass 6, count 0 2006.285.21:11:09.80#ibcon#read 3, iclass 6, count 0 2006.285.21:11:09.80#ibcon#about to read 4, iclass 6, count 0 2006.285.21:11:09.80#ibcon#read 4, iclass 6, count 0 2006.285.21:11:09.80#ibcon#about to read 5, iclass 6, count 0 2006.285.21:11:09.80#ibcon#read 5, iclass 6, count 0 2006.285.21:11:09.80#ibcon#about to read 6, iclass 6, count 0 2006.285.21:11:09.80#ibcon#read 6, iclass 6, count 0 2006.285.21:11:09.80#ibcon#end of sib2, iclass 6, count 0 2006.285.21:11:09.80#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:11:09.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:11:09.80#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:11:09.80#ibcon#*before write, iclass 6, count 0 2006.285.21:11:09.80#ibcon#enter sib2, iclass 6, count 0 2006.285.21:11:09.80#ibcon#flushed, iclass 6, count 0 2006.285.21:11:09.80#ibcon#about to write, iclass 6, count 0 2006.285.21:11:09.80#ibcon#wrote, iclass 6, count 0 2006.285.21:11:09.80#ibcon#about to read 3, iclass 6, count 0 2006.285.21:11:09.84#ibcon#read 3, iclass 6, count 0 2006.285.21:11:09.84#ibcon#about to read 4, iclass 6, count 0 2006.285.21:11:09.84#ibcon#read 4, iclass 6, count 0 2006.285.21:11:09.84#ibcon#about to read 5, iclass 6, count 0 2006.285.21:11:09.84#ibcon#read 5, iclass 6, count 0 2006.285.21:11:09.84#ibcon#about to read 6, iclass 6, count 0 2006.285.21:11:09.84#ibcon#read 6, iclass 6, count 0 2006.285.21:11:09.84#ibcon#end of sib2, iclass 6, count 0 2006.285.21:11:09.84#ibcon#*after write, iclass 6, count 0 2006.285.21:11:09.84#ibcon#*before return 0, iclass 6, count 0 2006.285.21:11:09.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:11:09.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:11:09.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:11:09.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:11:09.84$vck44/vb=7,4 2006.285.21:11:09.84#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.21:11:09.84#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.21:11:09.84#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:09.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:11:09.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:11:09.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:11:09.90#ibcon#enter wrdev, iclass 10, count 2 2006.285.21:11:09.90#ibcon#first serial, iclass 10, count 2 2006.285.21:11:09.90#ibcon#enter sib2, iclass 10, count 2 2006.285.21:11:09.90#ibcon#flushed, iclass 10, count 2 2006.285.21:11:09.90#ibcon#about to write, iclass 10, count 2 2006.285.21:11:09.90#ibcon#wrote, iclass 10, count 2 2006.285.21:11:09.90#ibcon#about to read 3, iclass 10, count 2 2006.285.21:11:09.92#ibcon#read 3, iclass 10, count 2 2006.285.21:11:09.92#ibcon#about to read 4, iclass 10, count 2 2006.285.21:11:09.92#ibcon#read 4, iclass 10, count 2 2006.285.21:11:09.92#ibcon#about to read 5, iclass 10, count 2 2006.285.21:11:09.92#ibcon#read 5, iclass 10, count 2 2006.285.21:11:09.92#ibcon#about to read 6, iclass 10, count 2 2006.285.21:11:09.92#ibcon#read 6, iclass 10, count 2 2006.285.21:11:09.92#ibcon#end of sib2, iclass 10, count 2 2006.285.21:11:09.92#ibcon#*mode == 0, iclass 10, count 2 2006.285.21:11:09.92#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.21:11:09.92#ibcon#[27=AT07-04\r\n] 2006.285.21:11:09.92#ibcon#*before write, iclass 10, count 2 2006.285.21:11:09.92#ibcon#enter sib2, iclass 10, count 2 2006.285.21:11:09.92#ibcon#flushed, iclass 10, count 2 2006.285.21:11:09.92#ibcon#about to write, iclass 10, count 2 2006.285.21:11:09.92#ibcon#wrote, iclass 10, count 2 2006.285.21:11:09.92#ibcon#about to read 3, iclass 10, count 2 2006.285.21:11:09.95#ibcon#read 3, iclass 10, count 2 2006.285.21:11:09.95#ibcon#about to read 4, iclass 10, count 2 2006.285.21:11:09.95#ibcon#read 4, iclass 10, count 2 2006.285.21:11:09.95#ibcon#about to read 5, iclass 10, count 2 2006.285.21:11:09.95#ibcon#read 5, iclass 10, count 2 2006.285.21:11:09.95#ibcon#about to read 6, iclass 10, count 2 2006.285.21:11:09.95#ibcon#read 6, iclass 10, count 2 2006.285.21:11:09.95#ibcon#end of sib2, iclass 10, count 2 2006.285.21:11:09.95#ibcon#*after write, iclass 10, count 2 2006.285.21:11:09.95#ibcon#*before return 0, iclass 10, count 2 2006.285.21:11:09.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:11:09.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:11:09.95#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.21:11:09.95#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:09.95#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:11:10.07#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:11:10.07#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:11:10.07#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:11:10.07#ibcon#first serial, iclass 10, count 0 2006.285.21:11:10.07#ibcon#enter sib2, iclass 10, count 0 2006.285.21:11:10.07#ibcon#flushed, iclass 10, count 0 2006.285.21:11:10.07#ibcon#about to write, iclass 10, count 0 2006.285.21:11:10.07#ibcon#wrote, iclass 10, count 0 2006.285.21:11:10.07#ibcon#about to read 3, iclass 10, count 0 2006.285.21:11:10.09#ibcon#read 3, iclass 10, count 0 2006.285.21:11:10.09#ibcon#about to read 4, iclass 10, count 0 2006.285.21:11:10.09#ibcon#read 4, iclass 10, count 0 2006.285.21:11:10.09#ibcon#about to read 5, iclass 10, count 0 2006.285.21:11:10.09#ibcon#read 5, iclass 10, count 0 2006.285.21:11:10.09#ibcon#about to read 6, iclass 10, count 0 2006.285.21:11:10.09#ibcon#read 6, iclass 10, count 0 2006.285.21:11:10.09#ibcon#end of sib2, iclass 10, count 0 2006.285.21:11:10.09#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:11:10.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:11:10.09#ibcon#[27=USB\r\n] 2006.285.21:11:10.09#ibcon#*before write, iclass 10, count 0 2006.285.21:11:10.09#ibcon#enter sib2, iclass 10, count 0 2006.285.21:11:10.09#ibcon#flushed, iclass 10, count 0 2006.285.21:11:10.09#ibcon#about to write, iclass 10, count 0 2006.285.21:11:10.09#ibcon#wrote, iclass 10, count 0 2006.285.21:11:10.09#ibcon#about to read 3, iclass 10, count 0 2006.285.21:11:10.12#ibcon#read 3, iclass 10, count 0 2006.285.21:11:10.12#ibcon#about to read 4, iclass 10, count 0 2006.285.21:11:10.12#ibcon#read 4, iclass 10, count 0 2006.285.21:11:10.12#ibcon#about to read 5, iclass 10, count 0 2006.285.21:11:10.12#ibcon#read 5, iclass 10, count 0 2006.285.21:11:10.12#ibcon#about to read 6, iclass 10, count 0 2006.285.21:11:10.12#ibcon#read 6, iclass 10, count 0 2006.285.21:11:10.12#ibcon#end of sib2, iclass 10, count 0 2006.285.21:11:10.12#ibcon#*after write, iclass 10, count 0 2006.285.21:11:10.12#ibcon#*before return 0, iclass 10, count 0 2006.285.21:11:10.12#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:11:10.12#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:11:10.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:11:10.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:11:10.12$vck44/vblo=8,744.99 2006.285.21:11:10.12#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.21:11:10.12#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.21:11:10.12#ibcon#ireg 17 cls_cnt 0 2006.285.21:11:10.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:11:10.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:11:10.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:11:10.12#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:11:10.12#ibcon#first serial, iclass 12, count 0 2006.285.21:11:10.12#ibcon#enter sib2, iclass 12, count 0 2006.285.21:11:10.12#ibcon#flushed, iclass 12, count 0 2006.285.21:11:10.12#ibcon#about to write, iclass 12, count 0 2006.285.21:11:10.12#ibcon#wrote, iclass 12, count 0 2006.285.21:11:10.12#ibcon#about to read 3, iclass 12, count 0 2006.285.21:11:10.14#ibcon#read 3, iclass 12, count 0 2006.285.21:11:10.14#ibcon#about to read 4, iclass 12, count 0 2006.285.21:11:10.14#ibcon#read 4, iclass 12, count 0 2006.285.21:11:10.14#ibcon#about to read 5, iclass 12, count 0 2006.285.21:11:10.14#ibcon#read 5, iclass 12, count 0 2006.285.21:11:10.14#ibcon#about to read 6, iclass 12, count 0 2006.285.21:11:10.14#ibcon#read 6, iclass 12, count 0 2006.285.21:11:10.14#ibcon#end of sib2, iclass 12, count 0 2006.285.21:11:10.14#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:11:10.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:11:10.14#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:11:10.14#ibcon#*before write, iclass 12, count 0 2006.285.21:11:10.14#ibcon#enter sib2, iclass 12, count 0 2006.285.21:11:10.14#ibcon#flushed, iclass 12, count 0 2006.285.21:11:10.14#ibcon#about to write, iclass 12, count 0 2006.285.21:11:10.14#ibcon#wrote, iclass 12, count 0 2006.285.21:11:10.14#ibcon#about to read 3, iclass 12, count 0 2006.285.21:11:10.18#ibcon#read 3, iclass 12, count 0 2006.285.21:11:10.18#ibcon#about to read 4, iclass 12, count 0 2006.285.21:11:10.18#ibcon#read 4, iclass 12, count 0 2006.285.21:11:10.18#ibcon#about to read 5, iclass 12, count 0 2006.285.21:11:10.18#ibcon#read 5, iclass 12, count 0 2006.285.21:11:10.18#ibcon#about to read 6, iclass 12, count 0 2006.285.21:11:10.18#ibcon#read 6, iclass 12, count 0 2006.285.21:11:10.18#ibcon#end of sib2, iclass 12, count 0 2006.285.21:11:10.18#ibcon#*after write, iclass 12, count 0 2006.285.21:11:10.18#ibcon#*before return 0, iclass 12, count 0 2006.285.21:11:10.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:11:10.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:11:10.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:11:10.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:11:10.18$vck44/vb=8,4 2006.285.21:11:10.18#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.21:11:10.18#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.21:11:10.18#ibcon#ireg 11 cls_cnt 2 2006.285.21:11:10.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:11:10.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:11:10.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:11:10.24#ibcon#enter wrdev, iclass 14, count 2 2006.285.21:11:10.24#ibcon#first serial, iclass 14, count 2 2006.285.21:11:10.24#ibcon#enter sib2, iclass 14, count 2 2006.285.21:11:10.24#ibcon#flushed, iclass 14, count 2 2006.285.21:11:10.24#ibcon#about to write, iclass 14, count 2 2006.285.21:11:10.24#ibcon#wrote, iclass 14, count 2 2006.285.21:11:10.24#ibcon#about to read 3, iclass 14, count 2 2006.285.21:11:10.26#ibcon#read 3, iclass 14, count 2 2006.285.21:11:10.26#ibcon#about to read 4, iclass 14, count 2 2006.285.21:11:10.26#ibcon#read 4, iclass 14, count 2 2006.285.21:11:10.26#ibcon#about to read 5, iclass 14, count 2 2006.285.21:11:10.26#ibcon#read 5, iclass 14, count 2 2006.285.21:11:10.26#ibcon#about to read 6, iclass 14, count 2 2006.285.21:11:10.26#ibcon#read 6, iclass 14, count 2 2006.285.21:11:10.26#ibcon#end of sib2, iclass 14, count 2 2006.285.21:11:10.26#ibcon#*mode == 0, iclass 14, count 2 2006.285.21:11:10.26#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.21:11:10.26#ibcon#[27=AT08-04\r\n] 2006.285.21:11:10.26#ibcon#*before write, iclass 14, count 2 2006.285.21:11:10.26#ibcon#enter sib2, iclass 14, count 2 2006.285.21:11:10.26#ibcon#flushed, iclass 14, count 2 2006.285.21:11:10.26#ibcon#about to write, iclass 14, count 2 2006.285.21:11:10.26#ibcon#wrote, iclass 14, count 2 2006.285.21:11:10.26#ibcon#about to read 3, iclass 14, count 2 2006.285.21:11:10.29#ibcon#read 3, iclass 14, count 2 2006.285.21:11:10.29#ibcon#about to read 4, iclass 14, count 2 2006.285.21:11:10.29#ibcon#read 4, iclass 14, count 2 2006.285.21:11:10.29#ibcon#about to read 5, iclass 14, count 2 2006.285.21:11:10.29#ibcon#read 5, iclass 14, count 2 2006.285.21:11:10.29#ibcon#about to read 6, iclass 14, count 2 2006.285.21:11:10.29#ibcon#read 6, iclass 14, count 2 2006.285.21:11:10.29#ibcon#end of sib2, iclass 14, count 2 2006.285.21:11:10.29#ibcon#*after write, iclass 14, count 2 2006.285.21:11:10.29#ibcon#*before return 0, iclass 14, count 2 2006.285.21:11:10.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:11:10.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:11:10.29#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.21:11:10.29#ibcon#ireg 7 cls_cnt 0 2006.285.21:11:10.29#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:11:10.41#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:11:10.41#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:11:10.41#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:11:10.41#ibcon#first serial, iclass 14, count 0 2006.285.21:11:10.41#ibcon#enter sib2, iclass 14, count 0 2006.285.21:11:10.41#ibcon#flushed, iclass 14, count 0 2006.285.21:11:10.41#ibcon#about to write, iclass 14, count 0 2006.285.21:11:10.41#ibcon#wrote, iclass 14, count 0 2006.285.21:11:10.41#ibcon#about to read 3, iclass 14, count 0 2006.285.21:11:10.43#ibcon#read 3, iclass 14, count 0 2006.285.21:11:10.43#ibcon#about to read 4, iclass 14, count 0 2006.285.21:11:10.43#ibcon#read 4, iclass 14, count 0 2006.285.21:11:10.43#ibcon#about to read 5, iclass 14, count 0 2006.285.21:11:10.43#ibcon#read 5, iclass 14, count 0 2006.285.21:11:10.43#ibcon#about to read 6, iclass 14, count 0 2006.285.21:11:10.43#ibcon#read 6, iclass 14, count 0 2006.285.21:11:10.43#ibcon#end of sib2, iclass 14, count 0 2006.285.21:11:10.43#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:11:10.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:11:10.43#ibcon#[27=USB\r\n] 2006.285.21:11:10.43#ibcon#*before write, iclass 14, count 0 2006.285.21:11:10.43#ibcon#enter sib2, iclass 14, count 0 2006.285.21:11:10.43#ibcon#flushed, iclass 14, count 0 2006.285.21:11:10.43#ibcon#about to write, iclass 14, count 0 2006.285.21:11:10.43#ibcon#wrote, iclass 14, count 0 2006.285.21:11:10.43#ibcon#about to read 3, iclass 14, count 0 2006.285.21:11:10.46#ibcon#read 3, iclass 14, count 0 2006.285.21:11:10.46#ibcon#about to read 4, iclass 14, count 0 2006.285.21:11:10.46#ibcon#read 4, iclass 14, count 0 2006.285.21:11:10.46#ibcon#about to read 5, iclass 14, count 0 2006.285.21:11:10.46#ibcon#read 5, iclass 14, count 0 2006.285.21:11:10.46#ibcon#about to read 6, iclass 14, count 0 2006.285.21:11:10.46#ibcon#read 6, iclass 14, count 0 2006.285.21:11:10.46#ibcon#end of sib2, iclass 14, count 0 2006.285.21:11:10.46#ibcon#*after write, iclass 14, count 0 2006.285.21:11:10.46#ibcon#*before return 0, iclass 14, count 0 2006.285.21:11:10.46#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:11:10.46#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:11:10.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:11:10.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:11:10.46$vck44/vabw=wide 2006.285.21:11:10.46#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.21:11:10.46#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.21:11:10.46#ibcon#ireg 8 cls_cnt 0 2006.285.21:11:10.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:11:10.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:11:10.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:11:10.46#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:11:10.46#ibcon#first serial, iclass 16, count 0 2006.285.21:11:10.46#ibcon#enter sib2, iclass 16, count 0 2006.285.21:11:10.46#ibcon#flushed, iclass 16, count 0 2006.285.21:11:10.46#ibcon#about to write, iclass 16, count 0 2006.285.21:11:10.46#ibcon#wrote, iclass 16, count 0 2006.285.21:11:10.46#ibcon#about to read 3, iclass 16, count 0 2006.285.21:11:10.48#ibcon#read 3, iclass 16, count 0 2006.285.21:11:10.56#ibcon#about to read 4, iclass 16, count 0 2006.285.21:11:10.56#ibcon#read 4, iclass 16, count 0 2006.285.21:11:10.56#ibcon#about to read 5, iclass 16, count 0 2006.285.21:11:10.56#ibcon#read 5, iclass 16, count 0 2006.285.21:11:10.56#ibcon#about to read 6, iclass 16, count 0 2006.285.21:11:10.56#ibcon#read 6, iclass 16, count 0 2006.285.21:11:10.56#ibcon#end of sib2, iclass 16, count 0 2006.285.21:11:10.56#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:11:10.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:11:10.56#ibcon#[25=BW32\r\n] 2006.285.21:11:10.56#ibcon#*before write, iclass 16, count 0 2006.285.21:11:10.56#ibcon#enter sib2, iclass 16, count 0 2006.285.21:11:10.56#ibcon#flushed, iclass 16, count 0 2006.285.21:11:10.56#ibcon#about to write, iclass 16, count 0 2006.285.21:11:10.56#ibcon#wrote, iclass 16, count 0 2006.285.21:11:10.56#ibcon#about to read 3, iclass 16, count 0 2006.285.21:11:10.59#ibcon#read 3, iclass 16, count 0 2006.285.21:11:10.59#ibcon#about to read 4, iclass 16, count 0 2006.285.21:11:10.59#ibcon#read 4, iclass 16, count 0 2006.285.21:11:10.59#ibcon#about to read 5, iclass 16, count 0 2006.285.21:11:10.59#ibcon#read 5, iclass 16, count 0 2006.285.21:11:10.59#ibcon#about to read 6, iclass 16, count 0 2006.285.21:11:10.59#ibcon#read 6, iclass 16, count 0 2006.285.21:11:10.59#ibcon#end of sib2, iclass 16, count 0 2006.285.21:11:10.59#ibcon#*after write, iclass 16, count 0 2006.285.21:11:10.59#ibcon#*before return 0, iclass 16, count 0 2006.285.21:11:10.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:11:10.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:11:10.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:11:10.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:11:10.59$vck44/vbbw=wide 2006.285.21:11:10.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.21:11:10.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.21:11:10.59#ibcon#ireg 8 cls_cnt 0 2006.285.21:11:10.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:11:10.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:11:10.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:11:10.59#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:11:10.59#ibcon#first serial, iclass 18, count 0 2006.285.21:11:10.59#ibcon#enter sib2, iclass 18, count 0 2006.285.21:11:10.59#ibcon#flushed, iclass 18, count 0 2006.285.21:11:10.59#ibcon#about to write, iclass 18, count 0 2006.285.21:11:10.59#ibcon#wrote, iclass 18, count 0 2006.285.21:11:10.59#ibcon#about to read 3, iclass 18, count 0 2006.285.21:11:10.61#ibcon#read 3, iclass 18, count 0 2006.285.21:11:10.61#ibcon#about to read 4, iclass 18, count 0 2006.285.21:11:10.61#ibcon#read 4, iclass 18, count 0 2006.285.21:11:10.61#ibcon#about to read 5, iclass 18, count 0 2006.285.21:11:10.61#ibcon#read 5, iclass 18, count 0 2006.285.21:11:10.61#ibcon#about to read 6, iclass 18, count 0 2006.285.21:11:10.61#ibcon#read 6, iclass 18, count 0 2006.285.21:11:10.61#ibcon#end of sib2, iclass 18, count 0 2006.285.21:11:10.61#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:11:10.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:11:10.61#ibcon#[27=BW32\r\n] 2006.285.21:11:10.61#ibcon#*before write, iclass 18, count 0 2006.285.21:11:10.61#ibcon#enter sib2, iclass 18, count 0 2006.285.21:11:10.61#ibcon#flushed, iclass 18, count 0 2006.285.21:11:10.61#ibcon#about to write, iclass 18, count 0 2006.285.21:11:10.61#ibcon#wrote, iclass 18, count 0 2006.285.21:11:10.61#ibcon#about to read 3, iclass 18, count 0 2006.285.21:11:10.64#ibcon#read 3, iclass 18, count 0 2006.285.21:11:10.64#ibcon#about to read 4, iclass 18, count 0 2006.285.21:11:10.64#ibcon#read 4, iclass 18, count 0 2006.285.21:11:10.64#ibcon#about to read 5, iclass 18, count 0 2006.285.21:11:10.64#ibcon#read 5, iclass 18, count 0 2006.285.21:11:10.64#ibcon#about to read 6, iclass 18, count 0 2006.285.21:11:10.64#ibcon#read 6, iclass 18, count 0 2006.285.21:11:10.64#ibcon#end of sib2, iclass 18, count 0 2006.285.21:11:10.64#ibcon#*after write, iclass 18, count 0 2006.285.21:11:10.64#ibcon#*before return 0, iclass 18, count 0 2006.285.21:11:10.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:11:10.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:11:10.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:11:10.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:11:10.64$setupk4/ifdk4 2006.285.21:11:10.64$ifdk4/lo= 2006.285.21:11:10.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:11:10.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:11:10.64$ifdk4/patch= 2006.285.21:11:10.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:11:10.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:11:10.64$setupk4/!*+20s 2006.285.21:11:14.04#abcon#<5=/00 0.2 0.7 14.231001015.6\r\n> 2006.285.21:11:14.06#abcon#{5=INTERFACE CLEAR} 2006.285.21:11:14.12#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:11:15.14#trakl#Source acquired 2006.285.21:11:17.14#flagr#flagr/antenna,acquired 2006.285.21:11:24.21#abcon#<5=/00 0.2 0.7 14.231001015.6\r\n> 2006.285.21:11:24.23#abcon#{5=INTERFACE CLEAR} 2006.285.21:11:24.29#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:11:24.29$setupk4/"tpicd 2006.285.21:11:24.29$setupk4/echo=off 2006.285.21:11:24.29$setupk4/xlog=off 2006.285.21:11:24.29:!2006.285.21:11:30 2006.285.21:11:30.00:preob 2006.285.21:11:30.14/onsource/TRACKING 2006.285.21:11:30.14:!2006.285.21:11:40 2006.285.21:11:40.00:"tape 2006.285.21:11:40.00:"st=record 2006.285.21:11:40.00:data_valid=on 2006.285.21:11:40.00:midob 2006.285.21:11:41.14/onsource/TRACKING 2006.285.21:11:41.14/wx/14.23,1015.6,100 2006.285.21:11:41.20/cable/+6.5103E-03 2006.285.21:11:42.29/va/01,07,usb,yes,33,36 2006.285.21:11:42.29/va/02,06,usb,yes,33,34 2006.285.21:11:42.29/va/03,07,usb,yes,33,35 2006.285.21:11:42.29/va/04,06,usb,yes,34,36 2006.285.21:11:42.29/va/05,03,usb,yes,34,34 2006.285.21:11:42.29/va/06,04,usb,yes,31,30 2006.285.21:11:42.29/va/07,04,usb,yes,31,32 2006.285.21:11:42.29/va/08,03,usb,yes,32,39 2006.285.21:11:42.52/valo/01,524.99,yes,locked 2006.285.21:11:42.52/valo/02,534.99,yes,locked 2006.285.21:11:42.52/valo/03,564.99,yes,locked 2006.285.21:11:42.52/valo/04,624.99,yes,locked 2006.285.21:11:42.52/valo/05,734.99,yes,locked 2006.285.21:11:42.52/valo/06,814.99,yes,locked 2006.285.21:11:42.52/valo/07,864.99,yes,locked 2006.285.21:11:42.52/valo/08,884.99,yes,locked 2006.285.21:11:43.61/vb/01,04,usb,yes,30,28 2006.285.21:11:43.61/vb/02,05,usb,yes,28,28 2006.285.21:11:43.61/vb/03,04,usb,yes,29,32 2006.285.21:11:43.61/vb/04,05,usb,yes,29,28 2006.285.21:11:43.61/vb/05,04,usb,yes,26,28 2006.285.21:11:43.61/vb/06,03,usb,yes,37,33 2006.285.21:11:43.61/vb/07,04,usb,yes,30,30 2006.285.21:11:43.61/vb/08,04,usb,yes,27,31 2006.285.21:11:43.84/vblo/01,629.99,yes,locked 2006.285.21:11:43.84/vblo/02,634.99,yes,locked 2006.285.21:11:43.84/vblo/03,649.99,yes,locked 2006.285.21:11:43.84/vblo/04,679.99,yes,locked 2006.285.21:11:43.84/vblo/05,709.99,yes,locked 2006.285.21:11:43.84/vblo/06,719.99,yes,locked 2006.285.21:11:43.84/vblo/07,734.99,yes,locked 2006.285.21:11:43.84/vblo/08,744.99,yes,locked 2006.285.21:11:43.99/vabw/8 2006.285.21:11:44.14/vbbw/8 2006.285.21:11:44.23/xfe/off,on,12.0 2006.285.21:11:44.62/ifatt/23,28,28,28 2006.285.21:11:45.07/fmout-gps/S +2.91E-07 2006.285.21:11:45.09:!2006.285.21:17:00 2006.285.21:17:00.02:data_valid=off 2006.285.21:17:00.02:"et 2006.285.21:17:00.02:!+3s 2006.285.21:17:03.04:"tape 2006.285.21:17:03.05:postob 2006.285.21:17:03.20/cable/+6.5115E-03 2006.285.21:17:03.20/wx/14.35,1015.6,100 2006.285.21:17:03.25/fmout-gps/S +2.87E-07 2006.285.21:17:03.26:scan_name=285-2119,jd0610,130 2006.285.21:17:03.26:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.285.21:17:04.14#flagr#flagr/antenna,new-source 2006.285.21:17:04.14:checkk5 2006.285.21:17:04.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:17:04.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:17:05.41/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:17:05.82/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:17:06.28/chk_obsdata//k5ts1/T2852111??a.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.285.21:17:06.67/chk_obsdata//k5ts2/T2852111??b.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.285.21:17:07.12/chk_obsdata//k5ts3/T2852111??c.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.285.21:17:07.55/chk_obsdata//k5ts4/T2852111??d.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.285.21:17:08.61/k5log//k5ts1_log_newline 2006.285.21:17:09.76/k5log//k5ts2_log_newline 2006.285.21:17:10.56/k5log//k5ts3_log_newline 2006.285.21:17:11.41/k5log//k5ts4_log_newline 2006.285.21:17:11.43/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:17:11.43:setupk4=1 2006.285.21:17:11.43$setupk4/echo=on 2006.285.21:17:11.43$setupk4/pcalon 2006.285.21:17:11.43$pcalon/"no phase cal control is implemented here 2006.285.21:17:11.43$setupk4/"tpicd=stop 2006.285.21:17:11.43$setupk4/"rec=synch_on 2006.285.21:17:11.43$setupk4/"rec_mode=128 2006.285.21:17:11.43$setupk4/!* 2006.285.21:17:11.43$setupk4/recpk4 2006.285.21:17:11.43$recpk4/recpatch= 2006.285.21:17:11.43$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:17:11.43$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:17:11.43$setupk4/vck44 2006.285.21:17:11.43$vck44/valo=1,524.99 2006.285.21:17:11.43#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.21:17:11.43#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.21:17:11.43#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:11.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:17:11.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:17:11.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:17:11.43#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:17:11.43#ibcon#first serial, iclass 23, count 0 2006.285.21:17:11.43#ibcon#enter sib2, iclass 23, count 0 2006.285.21:17:11.43#ibcon#flushed, iclass 23, count 0 2006.285.21:17:11.43#ibcon#about to write, iclass 23, count 0 2006.285.21:17:11.43#ibcon#wrote, iclass 23, count 0 2006.285.21:17:11.43#ibcon#about to read 3, iclass 23, count 0 2006.285.21:17:11.44#ibcon#read 3, iclass 23, count 0 2006.285.21:17:11.44#ibcon#about to read 4, iclass 23, count 0 2006.285.21:17:11.44#ibcon#read 4, iclass 23, count 0 2006.285.21:17:11.44#ibcon#about to read 5, iclass 23, count 0 2006.285.21:17:11.44#ibcon#read 5, iclass 23, count 0 2006.285.21:17:11.44#ibcon#about to read 6, iclass 23, count 0 2006.285.21:17:11.44#ibcon#read 6, iclass 23, count 0 2006.285.21:17:11.44#ibcon#end of sib2, iclass 23, count 0 2006.285.21:17:11.44#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:17:11.45#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:17:11.45#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:17:11.45#ibcon#*before write, iclass 23, count 0 2006.285.21:17:11.45#ibcon#enter sib2, iclass 23, count 0 2006.285.21:17:11.45#ibcon#flushed, iclass 23, count 0 2006.285.21:17:11.45#ibcon#about to write, iclass 23, count 0 2006.285.21:17:11.45#ibcon#wrote, iclass 23, count 0 2006.285.21:17:11.45#ibcon#about to read 3, iclass 23, count 0 2006.285.21:17:11.49#ibcon#read 3, iclass 23, count 0 2006.285.21:17:11.49#ibcon#about to read 4, iclass 23, count 0 2006.285.21:17:11.49#ibcon#read 4, iclass 23, count 0 2006.285.21:17:11.49#ibcon#about to read 5, iclass 23, count 0 2006.285.21:17:11.49#ibcon#read 5, iclass 23, count 0 2006.285.21:17:11.49#ibcon#about to read 6, iclass 23, count 0 2006.285.21:17:11.49#ibcon#read 6, iclass 23, count 0 2006.285.21:17:11.49#ibcon#end of sib2, iclass 23, count 0 2006.285.21:17:11.49#ibcon#*after write, iclass 23, count 0 2006.285.21:17:11.49#ibcon#*before return 0, iclass 23, count 0 2006.285.21:17:11.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:17:11.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:17:11.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:17:11.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:17:11.50$vck44/va=1,7 2006.285.21:17:11.50#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.21:17:11.50#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.21:17:11.50#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:11.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:17:11.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:17:11.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:17:11.50#ibcon#enter wrdev, iclass 25, count 2 2006.285.21:17:11.50#ibcon#first serial, iclass 25, count 2 2006.285.21:17:11.50#ibcon#enter sib2, iclass 25, count 2 2006.285.21:17:11.50#ibcon#flushed, iclass 25, count 2 2006.285.21:17:11.50#ibcon#about to write, iclass 25, count 2 2006.285.21:17:11.50#ibcon#wrote, iclass 25, count 2 2006.285.21:17:11.50#ibcon#about to read 3, iclass 25, count 2 2006.285.21:17:11.51#ibcon#read 3, iclass 25, count 2 2006.285.21:17:11.51#ibcon#about to read 4, iclass 25, count 2 2006.285.21:17:11.51#ibcon#read 4, iclass 25, count 2 2006.285.21:17:11.51#ibcon#about to read 5, iclass 25, count 2 2006.285.21:17:11.51#ibcon#read 5, iclass 25, count 2 2006.285.21:17:11.51#ibcon#about to read 6, iclass 25, count 2 2006.285.21:17:11.51#ibcon#read 6, iclass 25, count 2 2006.285.21:17:11.51#ibcon#end of sib2, iclass 25, count 2 2006.285.21:17:11.51#ibcon#*mode == 0, iclass 25, count 2 2006.285.21:17:11.52#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.21:17:11.52#ibcon#[25=AT01-07\r\n] 2006.285.21:17:11.52#ibcon#*before write, iclass 25, count 2 2006.285.21:17:11.52#ibcon#enter sib2, iclass 25, count 2 2006.285.21:17:11.52#ibcon#flushed, iclass 25, count 2 2006.285.21:17:11.52#ibcon#about to write, iclass 25, count 2 2006.285.21:17:11.52#ibcon#wrote, iclass 25, count 2 2006.285.21:17:11.52#ibcon#about to read 3, iclass 25, count 2 2006.285.21:17:11.54#ibcon#read 3, iclass 25, count 2 2006.285.21:17:11.54#ibcon#about to read 4, iclass 25, count 2 2006.285.21:17:11.54#ibcon#read 4, iclass 25, count 2 2006.285.21:17:11.54#ibcon#about to read 5, iclass 25, count 2 2006.285.21:17:11.54#ibcon#read 5, iclass 25, count 2 2006.285.21:17:11.54#ibcon#about to read 6, iclass 25, count 2 2006.285.21:17:11.54#ibcon#read 6, iclass 25, count 2 2006.285.21:17:11.54#ibcon#end of sib2, iclass 25, count 2 2006.285.21:17:11.54#ibcon#*after write, iclass 25, count 2 2006.285.21:17:11.54#ibcon#*before return 0, iclass 25, count 2 2006.285.21:17:11.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:17:11.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:17:11.55#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.21:17:11.55#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:11.55#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:17:11.66#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:17:11.66#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:17:11.66#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:17:11.66#ibcon#first serial, iclass 25, count 0 2006.285.21:17:11.67#ibcon#enter sib2, iclass 25, count 0 2006.285.21:17:11.67#ibcon#flushed, iclass 25, count 0 2006.285.21:17:11.67#ibcon#about to write, iclass 25, count 0 2006.285.21:17:11.67#ibcon#wrote, iclass 25, count 0 2006.285.21:17:11.67#ibcon#about to read 3, iclass 25, count 0 2006.285.21:17:11.68#ibcon#read 3, iclass 25, count 0 2006.285.21:17:11.68#ibcon#about to read 4, iclass 25, count 0 2006.285.21:17:11.68#ibcon#read 4, iclass 25, count 0 2006.285.21:17:11.68#ibcon#about to read 5, iclass 25, count 0 2006.285.21:17:11.68#ibcon#read 5, iclass 25, count 0 2006.285.21:17:11.68#ibcon#about to read 6, iclass 25, count 0 2006.285.21:17:11.68#ibcon#read 6, iclass 25, count 0 2006.285.21:17:11.68#ibcon#end of sib2, iclass 25, count 0 2006.285.21:17:11.68#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:17:11.68#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:17:11.69#ibcon#[25=USB\r\n] 2006.285.21:17:11.69#ibcon#*before write, iclass 25, count 0 2006.285.21:17:11.69#ibcon#enter sib2, iclass 25, count 0 2006.285.21:17:11.69#ibcon#flushed, iclass 25, count 0 2006.285.21:17:11.69#ibcon#about to write, iclass 25, count 0 2006.285.21:17:11.69#ibcon#wrote, iclass 25, count 0 2006.285.21:17:11.69#ibcon#about to read 3, iclass 25, count 0 2006.285.21:17:11.71#ibcon#read 3, iclass 25, count 0 2006.285.21:17:11.71#ibcon#about to read 4, iclass 25, count 0 2006.285.21:17:11.71#ibcon#read 4, iclass 25, count 0 2006.285.21:17:11.71#ibcon#about to read 5, iclass 25, count 0 2006.285.21:17:11.71#ibcon#read 5, iclass 25, count 0 2006.285.21:17:11.71#ibcon#about to read 6, iclass 25, count 0 2006.285.21:17:11.71#ibcon#read 6, iclass 25, count 0 2006.285.21:17:11.71#ibcon#end of sib2, iclass 25, count 0 2006.285.21:17:11.71#ibcon#*after write, iclass 25, count 0 2006.285.21:17:11.71#ibcon#*before return 0, iclass 25, count 0 2006.285.21:17:11.72#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:17:11.72#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:17:11.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:17:11.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:17:11.72$vck44/valo=2,534.99 2006.285.21:17:11.72#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.21:17:11.72#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.21:17:11.72#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:11.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:17:11.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:17:11.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:17:11.72#ibcon#enter wrdev, iclass 27, count 0 2006.285.21:17:11.72#ibcon#first serial, iclass 27, count 0 2006.285.21:17:11.72#ibcon#enter sib2, iclass 27, count 0 2006.285.21:17:11.72#ibcon#flushed, iclass 27, count 0 2006.285.21:17:11.72#ibcon#about to write, iclass 27, count 0 2006.285.21:17:11.72#ibcon#wrote, iclass 27, count 0 2006.285.21:17:11.72#ibcon#about to read 3, iclass 27, count 0 2006.285.21:17:11.73#ibcon#read 3, iclass 27, count 0 2006.285.21:17:11.73#ibcon#about to read 4, iclass 27, count 0 2006.285.21:17:11.73#ibcon#read 4, iclass 27, count 0 2006.285.21:17:11.73#ibcon#about to read 5, iclass 27, count 0 2006.285.21:17:11.73#ibcon#read 5, iclass 27, count 0 2006.285.21:17:11.73#ibcon#about to read 6, iclass 27, count 0 2006.285.21:17:11.73#ibcon#read 6, iclass 27, count 0 2006.285.21:17:11.73#ibcon#end of sib2, iclass 27, count 0 2006.285.21:17:11.73#ibcon#*mode == 0, iclass 27, count 0 2006.285.21:17:11.74#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.21:17:11.74#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:17:11.74#ibcon#*before write, iclass 27, count 0 2006.285.21:17:11.74#ibcon#enter sib2, iclass 27, count 0 2006.285.21:17:11.74#ibcon#flushed, iclass 27, count 0 2006.285.21:17:11.74#ibcon#about to write, iclass 27, count 0 2006.285.21:17:11.74#ibcon#wrote, iclass 27, count 0 2006.285.21:17:11.74#ibcon#about to read 3, iclass 27, count 0 2006.285.21:17:11.77#ibcon#read 3, iclass 27, count 0 2006.285.21:17:11.78#ibcon#about to read 4, iclass 27, count 0 2006.285.21:17:11.78#ibcon#read 4, iclass 27, count 0 2006.285.21:17:11.78#ibcon#about to read 5, iclass 27, count 0 2006.285.21:17:11.78#ibcon#read 5, iclass 27, count 0 2006.285.21:17:11.78#ibcon#about to read 6, iclass 27, count 0 2006.285.21:17:11.78#ibcon#read 6, iclass 27, count 0 2006.285.21:17:11.78#ibcon#end of sib2, iclass 27, count 0 2006.285.21:17:11.78#ibcon#*after write, iclass 27, count 0 2006.285.21:17:11.78#ibcon#*before return 0, iclass 27, count 0 2006.285.21:17:11.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:17:11.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:17:11.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.21:17:11.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.21:17:11.78$vck44/va=2,6 2006.285.21:17:11.78#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.21:17:11.78#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.21:17:11.78#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:11.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:17:11.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:17:11.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:17:11.83#ibcon#enter wrdev, iclass 29, count 2 2006.285.21:17:11.83#ibcon#first serial, iclass 29, count 2 2006.285.21:17:11.83#ibcon#enter sib2, iclass 29, count 2 2006.285.21:17:11.83#ibcon#flushed, iclass 29, count 2 2006.285.21:17:11.83#ibcon#about to write, iclass 29, count 2 2006.285.21:17:11.83#ibcon#wrote, iclass 29, count 2 2006.285.21:17:11.83#ibcon#about to read 3, iclass 29, count 2 2006.285.21:17:11.85#ibcon#read 3, iclass 29, count 2 2006.285.21:17:11.85#ibcon#about to read 4, iclass 29, count 2 2006.285.21:17:11.85#ibcon#read 4, iclass 29, count 2 2006.285.21:17:11.85#ibcon#about to read 5, iclass 29, count 2 2006.285.21:17:11.85#ibcon#read 5, iclass 29, count 2 2006.285.21:17:11.85#ibcon#about to read 6, iclass 29, count 2 2006.285.21:17:11.85#ibcon#read 6, iclass 29, count 2 2006.285.21:17:11.85#ibcon#end of sib2, iclass 29, count 2 2006.285.21:17:11.85#ibcon#*mode == 0, iclass 29, count 2 2006.285.21:17:11.85#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.21:17:11.86#ibcon#[25=AT02-06\r\n] 2006.285.21:17:11.86#ibcon#*before write, iclass 29, count 2 2006.285.21:17:11.86#ibcon#enter sib2, iclass 29, count 2 2006.285.21:17:11.86#ibcon#flushed, iclass 29, count 2 2006.285.21:17:11.86#ibcon#about to write, iclass 29, count 2 2006.285.21:17:11.86#ibcon#wrote, iclass 29, count 2 2006.285.21:17:11.86#ibcon#about to read 3, iclass 29, count 2 2006.285.21:17:11.88#ibcon#read 3, iclass 29, count 2 2006.285.21:17:11.88#ibcon#about to read 4, iclass 29, count 2 2006.285.21:17:11.88#ibcon#read 4, iclass 29, count 2 2006.285.21:17:11.88#ibcon#about to read 5, iclass 29, count 2 2006.285.21:17:11.88#ibcon#read 5, iclass 29, count 2 2006.285.21:17:11.88#ibcon#about to read 6, iclass 29, count 2 2006.285.21:17:11.88#ibcon#read 6, iclass 29, count 2 2006.285.21:17:11.88#ibcon#end of sib2, iclass 29, count 2 2006.285.21:17:11.88#ibcon#*after write, iclass 29, count 2 2006.285.21:17:11.88#ibcon#*before return 0, iclass 29, count 2 2006.285.21:17:11.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:17:11.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:17:11.89#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.21:17:11.89#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:11.89#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:17:12.01#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:17:12.01#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:17:12.01#ibcon#enter wrdev, iclass 29, count 0 2006.285.21:17:12.01#ibcon#first serial, iclass 29, count 0 2006.285.21:17:12.01#ibcon#enter sib2, iclass 29, count 0 2006.285.21:17:12.01#ibcon#flushed, iclass 29, count 0 2006.285.21:17:12.01#ibcon#about to write, iclass 29, count 0 2006.285.21:17:12.01#ibcon#wrote, iclass 29, count 0 2006.285.21:17:12.01#ibcon#about to read 3, iclass 29, count 0 2006.285.21:17:12.02#ibcon#read 3, iclass 29, count 0 2006.285.21:17:12.02#ibcon#about to read 4, iclass 29, count 0 2006.285.21:17:12.02#ibcon#read 4, iclass 29, count 0 2006.285.21:17:12.02#ibcon#about to read 5, iclass 29, count 0 2006.285.21:17:12.02#ibcon#read 5, iclass 29, count 0 2006.285.21:17:12.02#ibcon#about to read 6, iclass 29, count 0 2006.285.21:17:12.02#ibcon#read 6, iclass 29, count 0 2006.285.21:17:12.02#ibcon#end of sib2, iclass 29, count 0 2006.285.21:17:12.02#ibcon#*mode == 0, iclass 29, count 0 2006.285.21:17:12.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.21:17:12.03#ibcon#[25=USB\r\n] 2006.285.21:17:12.03#ibcon#*before write, iclass 29, count 0 2006.285.21:17:12.03#ibcon#enter sib2, iclass 29, count 0 2006.285.21:17:12.03#ibcon#flushed, iclass 29, count 0 2006.285.21:17:12.03#ibcon#about to write, iclass 29, count 0 2006.285.21:17:12.03#ibcon#wrote, iclass 29, count 0 2006.285.21:17:12.03#ibcon#about to read 3, iclass 29, count 0 2006.285.21:17:12.05#ibcon#read 3, iclass 29, count 0 2006.285.21:17:12.05#ibcon#about to read 4, iclass 29, count 0 2006.285.21:17:12.05#ibcon#read 4, iclass 29, count 0 2006.285.21:17:12.05#ibcon#about to read 5, iclass 29, count 0 2006.285.21:17:12.05#ibcon#read 5, iclass 29, count 0 2006.285.21:17:12.06#ibcon#about to read 6, iclass 29, count 0 2006.285.21:17:12.06#ibcon#read 6, iclass 29, count 0 2006.285.21:17:12.06#ibcon#end of sib2, iclass 29, count 0 2006.285.21:17:12.06#ibcon#*after write, iclass 29, count 0 2006.285.21:17:12.06#ibcon#*before return 0, iclass 29, count 0 2006.285.21:17:12.06#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:17:12.06#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:17:12.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.21:17:12.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.21:17:12.06$vck44/valo=3,564.99 2006.285.21:17:12.06#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.21:17:12.06#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.21:17:12.06#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:12.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:17:12.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:17:12.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:17:12.06#ibcon#enter wrdev, iclass 31, count 0 2006.285.21:17:12.06#ibcon#first serial, iclass 31, count 0 2006.285.21:17:12.06#ibcon#enter sib2, iclass 31, count 0 2006.285.21:17:12.06#ibcon#flushed, iclass 31, count 0 2006.285.21:17:12.06#ibcon#about to write, iclass 31, count 0 2006.285.21:17:12.06#ibcon#wrote, iclass 31, count 0 2006.285.21:17:12.06#ibcon#about to read 3, iclass 31, count 0 2006.285.21:17:12.07#ibcon#read 3, iclass 31, count 0 2006.285.21:17:12.49#ibcon#about to read 4, iclass 31, count 0 2006.285.21:17:12.49#ibcon#read 4, iclass 31, count 0 2006.285.21:17:12.49#ibcon#about to read 5, iclass 31, count 0 2006.285.21:17:12.49#ibcon#read 5, iclass 31, count 0 2006.285.21:17:12.49#ibcon#about to read 6, iclass 31, count 0 2006.285.21:17:12.49#ibcon#read 6, iclass 31, count 0 2006.285.21:17:12.49#ibcon#end of sib2, iclass 31, count 0 2006.285.21:17:12.49#ibcon#*mode == 0, iclass 31, count 0 2006.285.21:17:12.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.21:17:12.49#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:17:12.49#ibcon#*before write, iclass 31, count 0 2006.285.21:17:12.49#ibcon#enter sib2, iclass 31, count 0 2006.285.21:17:12.49#ibcon#flushed, iclass 31, count 0 2006.285.21:17:12.49#ibcon#about to write, iclass 31, count 0 2006.285.21:17:12.49#ibcon#wrote, iclass 31, count 0 2006.285.21:17:12.49#ibcon#about to read 3, iclass 31, count 0 2006.285.21:17:12.52#ibcon#read 3, iclass 31, count 0 2006.285.21:17:12.52#ibcon#about to read 4, iclass 31, count 0 2006.285.21:17:12.52#ibcon#read 4, iclass 31, count 0 2006.285.21:17:12.52#ibcon#about to read 5, iclass 31, count 0 2006.285.21:17:12.52#ibcon#read 5, iclass 31, count 0 2006.285.21:17:12.52#ibcon#about to read 6, iclass 31, count 0 2006.285.21:17:12.52#ibcon#read 6, iclass 31, count 0 2006.285.21:17:12.53#ibcon#end of sib2, iclass 31, count 0 2006.285.21:17:12.53#ibcon#*after write, iclass 31, count 0 2006.285.21:17:12.53#ibcon#*before return 0, iclass 31, count 0 2006.285.21:17:12.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:17:12.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:17:12.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.21:17:12.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.21:17:12.53$vck44/va=3,7 2006.285.21:17:12.53#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.21:17:12.53#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.21:17:12.53#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:12.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:17:12.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:17:12.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:17:12.53#ibcon#enter wrdev, iclass 33, count 2 2006.285.21:17:12.53#ibcon#first serial, iclass 33, count 2 2006.285.21:17:12.53#ibcon#enter sib2, iclass 33, count 2 2006.285.21:17:12.53#ibcon#flushed, iclass 33, count 2 2006.285.21:17:12.53#ibcon#about to write, iclass 33, count 2 2006.285.21:17:12.53#ibcon#wrote, iclass 33, count 2 2006.285.21:17:12.53#ibcon#about to read 3, iclass 33, count 2 2006.285.21:17:12.54#ibcon#read 3, iclass 33, count 2 2006.285.21:17:12.54#ibcon#about to read 4, iclass 33, count 2 2006.285.21:17:12.54#ibcon#read 4, iclass 33, count 2 2006.285.21:17:12.54#ibcon#about to read 5, iclass 33, count 2 2006.285.21:17:12.54#ibcon#read 5, iclass 33, count 2 2006.285.21:17:12.54#ibcon#about to read 6, iclass 33, count 2 2006.285.21:17:12.54#ibcon#read 6, iclass 33, count 2 2006.285.21:17:12.54#ibcon#end of sib2, iclass 33, count 2 2006.285.21:17:12.55#ibcon#*mode == 0, iclass 33, count 2 2006.285.21:17:12.55#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.21:17:12.55#ibcon#[25=AT03-07\r\n] 2006.285.21:17:12.55#ibcon#*before write, iclass 33, count 2 2006.285.21:17:12.55#ibcon#enter sib2, iclass 33, count 2 2006.285.21:17:12.55#ibcon#flushed, iclass 33, count 2 2006.285.21:17:12.55#ibcon#about to write, iclass 33, count 2 2006.285.21:17:12.55#ibcon#wrote, iclass 33, count 2 2006.285.21:17:12.55#ibcon#about to read 3, iclass 33, count 2 2006.285.21:17:12.57#ibcon#read 3, iclass 33, count 2 2006.285.21:17:12.57#ibcon#about to read 4, iclass 33, count 2 2006.285.21:17:12.57#ibcon#read 4, iclass 33, count 2 2006.285.21:17:12.57#ibcon#about to read 5, iclass 33, count 2 2006.285.21:17:12.57#ibcon#read 5, iclass 33, count 2 2006.285.21:17:12.57#ibcon#about to read 6, iclass 33, count 2 2006.285.21:17:12.57#ibcon#read 6, iclass 33, count 2 2006.285.21:17:12.58#ibcon#end of sib2, iclass 33, count 2 2006.285.21:17:12.58#ibcon#*after write, iclass 33, count 2 2006.285.21:17:12.58#ibcon#*before return 0, iclass 33, count 2 2006.285.21:17:12.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:17:12.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:17:12.58#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.21:17:12.58#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:12.58#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:17:12.69#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:17:12.69#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:17:12.69#ibcon#enter wrdev, iclass 33, count 0 2006.285.21:17:12.69#ibcon#first serial, iclass 33, count 0 2006.285.21:17:12.69#ibcon#enter sib2, iclass 33, count 0 2006.285.21:17:12.69#ibcon#flushed, iclass 33, count 0 2006.285.21:17:12.69#ibcon#about to write, iclass 33, count 0 2006.285.21:17:12.70#ibcon#wrote, iclass 33, count 0 2006.285.21:17:12.70#ibcon#about to read 3, iclass 33, count 0 2006.285.21:17:12.71#ibcon#read 3, iclass 33, count 0 2006.285.21:17:12.71#ibcon#about to read 4, iclass 33, count 0 2006.285.21:17:12.71#ibcon#read 4, iclass 33, count 0 2006.285.21:17:12.71#ibcon#about to read 5, iclass 33, count 0 2006.285.21:17:12.71#ibcon#read 5, iclass 33, count 0 2006.285.21:17:12.71#ibcon#about to read 6, iclass 33, count 0 2006.285.21:17:12.71#ibcon#read 6, iclass 33, count 0 2006.285.21:17:12.72#ibcon#end of sib2, iclass 33, count 0 2006.285.21:17:12.72#ibcon#*mode == 0, iclass 33, count 0 2006.285.21:17:12.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.21:17:12.72#ibcon#[25=USB\r\n] 2006.285.21:17:12.72#ibcon#*before write, iclass 33, count 0 2006.285.21:17:12.72#ibcon#enter sib2, iclass 33, count 0 2006.285.21:17:12.72#ibcon#flushed, iclass 33, count 0 2006.285.21:17:12.72#ibcon#about to write, iclass 33, count 0 2006.285.21:17:12.72#ibcon#wrote, iclass 33, count 0 2006.285.21:17:12.72#ibcon#about to read 3, iclass 33, count 0 2006.285.21:17:12.74#ibcon#read 3, iclass 33, count 0 2006.285.21:17:12.74#ibcon#about to read 4, iclass 33, count 0 2006.285.21:17:12.74#ibcon#read 4, iclass 33, count 0 2006.285.21:17:12.74#ibcon#about to read 5, iclass 33, count 0 2006.285.21:17:12.74#ibcon#read 5, iclass 33, count 0 2006.285.21:17:12.74#ibcon#about to read 6, iclass 33, count 0 2006.285.21:17:12.74#ibcon#read 6, iclass 33, count 0 2006.285.21:17:12.74#ibcon#end of sib2, iclass 33, count 0 2006.285.21:17:12.74#ibcon#*after write, iclass 33, count 0 2006.285.21:17:12.75#ibcon#*before return 0, iclass 33, count 0 2006.285.21:17:12.75#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:17:12.75#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:17:12.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.21:17:12.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.21:17:12.75$vck44/valo=4,624.99 2006.285.21:17:12.75#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.21:17:12.75#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.21:17:12.75#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:12.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:17:12.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:17:12.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:17:12.75#ibcon#enter wrdev, iclass 35, count 0 2006.285.21:17:12.75#ibcon#first serial, iclass 35, count 0 2006.285.21:17:12.75#ibcon#enter sib2, iclass 35, count 0 2006.285.21:17:12.75#ibcon#flushed, iclass 35, count 0 2006.285.21:17:12.75#ibcon#about to write, iclass 35, count 0 2006.285.21:17:12.75#ibcon#wrote, iclass 35, count 0 2006.285.21:17:12.75#ibcon#about to read 3, iclass 35, count 0 2006.285.21:17:12.76#ibcon#read 3, iclass 35, count 0 2006.285.21:17:12.99#ibcon#about to read 4, iclass 35, count 0 2006.285.21:17:12.99#ibcon#read 4, iclass 35, count 0 2006.285.21:17:12.99#ibcon#about to read 5, iclass 35, count 0 2006.285.21:17:12.99#ibcon#read 5, iclass 35, count 0 2006.285.21:17:12.99#ibcon#about to read 6, iclass 35, count 0 2006.285.21:17:12.99#ibcon#read 6, iclass 35, count 0 2006.285.21:17:12.99#ibcon#end of sib2, iclass 35, count 0 2006.285.21:17:12.99#ibcon#*mode == 0, iclass 35, count 0 2006.285.21:17:12.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.21:17:12.99#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:17:12.99#ibcon#*before write, iclass 35, count 0 2006.285.21:17:12.99#ibcon#enter sib2, iclass 35, count 0 2006.285.21:17:12.99#ibcon#flushed, iclass 35, count 0 2006.285.21:17:12.99#ibcon#about to write, iclass 35, count 0 2006.285.21:17:12.99#ibcon#wrote, iclass 35, count 0 2006.285.21:17:12.99#ibcon#about to read 3, iclass 35, count 0 2006.285.21:17:13.02#ibcon#read 3, iclass 35, count 0 2006.285.21:17:13.02#ibcon#about to read 4, iclass 35, count 0 2006.285.21:17:13.02#ibcon#read 4, iclass 35, count 0 2006.285.21:17:13.02#ibcon#about to read 5, iclass 35, count 0 2006.285.21:17:13.02#ibcon#read 5, iclass 35, count 0 2006.285.21:17:13.02#ibcon#about to read 6, iclass 35, count 0 2006.285.21:17:13.02#ibcon#read 6, iclass 35, count 0 2006.285.21:17:13.02#ibcon#end of sib2, iclass 35, count 0 2006.285.21:17:13.03#ibcon#*after write, iclass 35, count 0 2006.285.21:17:13.03#ibcon#*before return 0, iclass 35, count 0 2006.285.21:17:13.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:17:13.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:17:13.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.21:17:13.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.21:17:13.03$vck44/va=4,6 2006.285.21:17:13.03#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.21:17:13.03#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.21:17:13.03#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:13.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:17:13.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:17:13.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:17:13.03#ibcon#enter wrdev, iclass 37, count 2 2006.285.21:17:13.03#ibcon#first serial, iclass 37, count 2 2006.285.21:17:13.03#ibcon#enter sib2, iclass 37, count 2 2006.285.21:17:13.03#ibcon#flushed, iclass 37, count 2 2006.285.21:17:13.03#ibcon#about to write, iclass 37, count 2 2006.285.21:17:13.03#ibcon#wrote, iclass 37, count 2 2006.285.21:17:13.03#ibcon#about to read 3, iclass 37, count 2 2006.285.21:17:13.04#ibcon#read 3, iclass 37, count 2 2006.285.21:17:13.04#ibcon#about to read 4, iclass 37, count 2 2006.285.21:17:13.04#ibcon#read 4, iclass 37, count 2 2006.285.21:17:13.04#ibcon#about to read 5, iclass 37, count 2 2006.285.21:17:13.04#ibcon#read 5, iclass 37, count 2 2006.285.21:17:13.04#ibcon#about to read 6, iclass 37, count 2 2006.285.21:17:13.04#ibcon#read 6, iclass 37, count 2 2006.285.21:17:13.05#ibcon#end of sib2, iclass 37, count 2 2006.285.21:17:13.05#ibcon#*mode == 0, iclass 37, count 2 2006.285.21:17:13.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.21:17:13.05#ibcon#[25=AT04-06\r\n] 2006.285.21:17:13.05#ibcon#*before write, iclass 37, count 2 2006.285.21:17:13.05#ibcon#enter sib2, iclass 37, count 2 2006.285.21:17:13.05#ibcon#flushed, iclass 37, count 2 2006.285.21:17:13.05#ibcon#about to write, iclass 37, count 2 2006.285.21:17:13.05#ibcon#wrote, iclass 37, count 2 2006.285.21:17:13.05#ibcon#about to read 3, iclass 37, count 2 2006.285.21:17:13.07#ibcon#read 3, iclass 37, count 2 2006.285.21:17:13.07#ibcon#about to read 4, iclass 37, count 2 2006.285.21:17:13.07#ibcon#read 4, iclass 37, count 2 2006.285.21:17:13.07#ibcon#about to read 5, iclass 37, count 2 2006.285.21:17:13.07#ibcon#read 5, iclass 37, count 2 2006.285.21:17:13.07#ibcon#about to read 6, iclass 37, count 2 2006.285.21:17:13.07#ibcon#read 6, iclass 37, count 2 2006.285.21:17:13.07#ibcon#end of sib2, iclass 37, count 2 2006.285.21:17:13.08#ibcon#*after write, iclass 37, count 2 2006.285.21:17:13.08#ibcon#*before return 0, iclass 37, count 2 2006.285.21:17:13.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:17:13.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:17:13.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.21:17:13.08#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:13.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:17:13.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:17:13.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:17:13.19#ibcon#enter wrdev, iclass 37, count 0 2006.285.21:17:13.19#ibcon#first serial, iclass 37, count 0 2006.285.21:17:13.19#ibcon#enter sib2, iclass 37, count 0 2006.285.21:17:13.19#ibcon#flushed, iclass 37, count 0 2006.285.21:17:13.19#ibcon#about to write, iclass 37, count 0 2006.285.21:17:13.20#ibcon#wrote, iclass 37, count 0 2006.285.21:17:13.20#ibcon#about to read 3, iclass 37, count 0 2006.285.21:17:13.21#ibcon#read 3, iclass 37, count 0 2006.285.21:17:13.21#ibcon#about to read 4, iclass 37, count 0 2006.285.21:17:13.21#ibcon#read 4, iclass 37, count 0 2006.285.21:17:13.21#ibcon#about to read 5, iclass 37, count 0 2006.285.21:17:13.21#ibcon#read 5, iclass 37, count 0 2006.285.21:17:13.21#ibcon#about to read 6, iclass 37, count 0 2006.285.21:17:13.21#ibcon#read 6, iclass 37, count 0 2006.285.21:17:13.21#ibcon#end of sib2, iclass 37, count 0 2006.285.21:17:13.21#ibcon#*mode == 0, iclass 37, count 0 2006.285.21:17:13.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.21:17:13.22#ibcon#[25=USB\r\n] 2006.285.21:17:13.22#ibcon#*before write, iclass 37, count 0 2006.285.21:17:13.22#ibcon#enter sib2, iclass 37, count 0 2006.285.21:17:13.22#ibcon#flushed, iclass 37, count 0 2006.285.21:17:13.22#ibcon#about to write, iclass 37, count 0 2006.285.21:17:13.22#ibcon#wrote, iclass 37, count 0 2006.285.21:17:13.22#ibcon#about to read 3, iclass 37, count 0 2006.285.21:17:13.24#ibcon#read 3, iclass 37, count 0 2006.285.21:17:13.24#ibcon#about to read 4, iclass 37, count 0 2006.285.21:17:13.24#ibcon#read 4, iclass 37, count 0 2006.285.21:17:13.24#ibcon#about to read 5, iclass 37, count 0 2006.285.21:17:13.24#ibcon#read 5, iclass 37, count 0 2006.285.21:17:13.24#ibcon#about to read 6, iclass 37, count 0 2006.285.21:17:13.24#ibcon#read 6, iclass 37, count 0 2006.285.21:17:13.24#ibcon#end of sib2, iclass 37, count 0 2006.285.21:17:13.24#ibcon#*after write, iclass 37, count 0 2006.285.21:17:13.25#ibcon#*before return 0, iclass 37, count 0 2006.285.21:17:13.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:17:13.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:17:13.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.21:17:13.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.21:17:13.25$vck44/valo=5,734.99 2006.285.21:17:13.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.21:17:13.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.21:17:13.25#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:13.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:17:13.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:17:13.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:17:13.25#ibcon#enter wrdev, iclass 39, count 0 2006.285.21:17:13.25#ibcon#first serial, iclass 39, count 0 2006.285.21:17:13.25#ibcon#enter sib2, iclass 39, count 0 2006.285.21:17:13.25#ibcon#flushed, iclass 39, count 0 2006.285.21:17:13.25#ibcon#about to write, iclass 39, count 0 2006.285.21:17:13.25#ibcon#wrote, iclass 39, count 0 2006.285.21:17:13.25#ibcon#about to read 3, iclass 39, count 0 2006.285.21:17:13.26#ibcon#read 3, iclass 39, count 0 2006.285.21:17:13.26#ibcon#about to read 4, iclass 39, count 0 2006.285.21:17:13.26#ibcon#read 4, iclass 39, count 0 2006.285.21:17:13.26#ibcon#about to read 5, iclass 39, count 0 2006.285.21:17:13.26#ibcon#read 5, iclass 39, count 0 2006.285.21:17:13.26#ibcon#about to read 6, iclass 39, count 0 2006.285.21:17:13.26#ibcon#read 6, iclass 39, count 0 2006.285.21:17:13.27#ibcon#end of sib2, iclass 39, count 0 2006.285.21:17:13.27#ibcon#*mode == 0, iclass 39, count 0 2006.285.21:17:13.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.21:17:13.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:17:13.27#ibcon#*before write, iclass 39, count 0 2006.285.21:17:13.27#ibcon#enter sib2, iclass 39, count 0 2006.285.21:17:13.27#ibcon#flushed, iclass 39, count 0 2006.285.21:17:13.27#ibcon#about to write, iclass 39, count 0 2006.285.21:17:13.27#ibcon#wrote, iclass 39, count 0 2006.285.21:17:13.27#ibcon#about to read 3, iclass 39, count 0 2006.285.21:17:13.30#ibcon#read 3, iclass 39, count 0 2006.285.21:17:13.30#ibcon#about to read 4, iclass 39, count 0 2006.285.21:17:13.30#ibcon#read 4, iclass 39, count 0 2006.285.21:17:13.30#ibcon#about to read 5, iclass 39, count 0 2006.285.21:17:13.30#ibcon#read 5, iclass 39, count 0 2006.285.21:17:13.30#ibcon#about to read 6, iclass 39, count 0 2006.285.21:17:13.30#ibcon#read 6, iclass 39, count 0 2006.285.21:17:13.30#ibcon#end of sib2, iclass 39, count 0 2006.285.21:17:13.31#ibcon#*after write, iclass 39, count 0 2006.285.21:17:13.31#ibcon#*before return 0, iclass 39, count 0 2006.285.21:17:13.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:17:13.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:17:13.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.21:17:13.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.21:17:13.31$vck44/va=5,3 2006.285.21:17:13.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.21:17:13.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.21:17:13.31#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:13.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:17:13.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:17:13.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:17:13.36#ibcon#enter wrdev, iclass 3, count 2 2006.285.21:17:13.36#ibcon#first serial, iclass 3, count 2 2006.285.21:17:13.36#ibcon#enter sib2, iclass 3, count 2 2006.285.21:17:13.36#ibcon#flushed, iclass 3, count 2 2006.285.21:17:13.36#ibcon#about to write, iclass 3, count 2 2006.285.21:17:13.37#ibcon#wrote, iclass 3, count 2 2006.285.21:17:13.37#ibcon#about to read 3, iclass 3, count 2 2006.285.21:17:13.38#ibcon#read 3, iclass 3, count 2 2006.285.21:17:13.38#ibcon#about to read 4, iclass 3, count 2 2006.285.21:17:13.38#ibcon#read 4, iclass 3, count 2 2006.285.21:17:13.38#ibcon#about to read 5, iclass 3, count 2 2006.285.21:17:13.38#ibcon#read 5, iclass 3, count 2 2006.285.21:17:13.38#ibcon#about to read 6, iclass 3, count 2 2006.285.21:17:13.38#ibcon#read 6, iclass 3, count 2 2006.285.21:17:13.38#ibcon#end of sib2, iclass 3, count 2 2006.285.21:17:13.38#ibcon#*mode == 0, iclass 3, count 2 2006.285.21:17:13.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.21:17:13.39#ibcon#[25=AT05-03\r\n] 2006.285.21:17:13.39#ibcon#*before write, iclass 3, count 2 2006.285.21:17:13.39#ibcon#enter sib2, iclass 3, count 2 2006.285.21:17:13.39#ibcon#flushed, iclass 3, count 2 2006.285.21:17:13.39#ibcon#about to write, iclass 3, count 2 2006.285.21:17:13.39#ibcon#wrote, iclass 3, count 2 2006.285.21:17:13.39#ibcon#about to read 3, iclass 3, count 2 2006.285.21:17:13.41#ibcon#read 3, iclass 3, count 2 2006.285.21:17:13.41#ibcon#about to read 4, iclass 3, count 2 2006.285.21:17:13.41#ibcon#read 4, iclass 3, count 2 2006.285.21:17:13.41#ibcon#about to read 5, iclass 3, count 2 2006.285.21:17:13.41#ibcon#read 5, iclass 3, count 2 2006.285.21:17:13.41#ibcon#about to read 6, iclass 3, count 2 2006.285.21:17:13.41#ibcon#read 6, iclass 3, count 2 2006.285.21:17:13.41#ibcon#end of sib2, iclass 3, count 2 2006.285.21:17:13.42#ibcon#*after write, iclass 3, count 2 2006.285.21:17:13.42#ibcon#*before return 0, iclass 3, count 2 2006.285.21:17:13.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:17:13.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:17:13.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.21:17:13.42#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:13.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:17:13.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:17:13.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:17:13.53#ibcon#enter wrdev, iclass 3, count 0 2006.285.21:17:13.53#ibcon#first serial, iclass 3, count 0 2006.285.21:17:13.53#ibcon#enter sib2, iclass 3, count 0 2006.285.21:17:13.53#ibcon#flushed, iclass 3, count 0 2006.285.21:17:13.53#ibcon#about to write, iclass 3, count 0 2006.285.21:17:13.53#ibcon#wrote, iclass 3, count 0 2006.285.21:17:13.53#ibcon#about to read 3, iclass 3, count 0 2006.285.21:17:13.55#ibcon#read 3, iclass 3, count 0 2006.285.21:17:13.55#ibcon#about to read 4, iclass 3, count 0 2006.285.21:17:13.55#ibcon#read 4, iclass 3, count 0 2006.285.21:17:13.55#ibcon#about to read 5, iclass 3, count 0 2006.285.21:17:13.55#ibcon#read 5, iclass 3, count 0 2006.285.21:17:13.55#ibcon#about to read 6, iclass 3, count 0 2006.285.21:17:13.55#ibcon#read 6, iclass 3, count 0 2006.285.21:17:13.55#ibcon#end of sib2, iclass 3, count 0 2006.285.21:17:13.55#ibcon#*mode == 0, iclass 3, count 0 2006.285.21:17:13.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.21:17:13.55#ibcon#[25=USB\r\n] 2006.285.21:17:13.56#ibcon#*before write, iclass 3, count 0 2006.285.21:17:13.56#ibcon#enter sib2, iclass 3, count 0 2006.285.21:17:13.56#ibcon#flushed, iclass 3, count 0 2006.285.21:17:13.56#ibcon#about to write, iclass 3, count 0 2006.285.21:17:13.56#ibcon#wrote, iclass 3, count 0 2006.285.21:17:13.56#ibcon#about to read 3, iclass 3, count 0 2006.285.21:17:13.58#ibcon#read 3, iclass 3, count 0 2006.285.21:17:13.58#ibcon#about to read 4, iclass 3, count 0 2006.285.21:17:13.58#ibcon#read 4, iclass 3, count 0 2006.285.21:17:13.58#ibcon#about to read 5, iclass 3, count 0 2006.285.21:17:13.58#ibcon#read 5, iclass 3, count 0 2006.285.21:17:13.58#ibcon#about to read 6, iclass 3, count 0 2006.285.21:17:13.58#ibcon#read 6, iclass 3, count 0 2006.285.21:17:13.58#ibcon#end of sib2, iclass 3, count 0 2006.285.21:17:13.58#ibcon#*after write, iclass 3, count 0 2006.285.21:17:13.58#ibcon#*before return 0, iclass 3, count 0 2006.285.21:17:13.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:17:13.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:17:13.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.21:17:13.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.21:17:13.59$vck44/valo=6,814.99 2006.285.21:17:13.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.21:17:13.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.21:17:13.59#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:13.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:17:13.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:17:13.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:17:13.59#ibcon#enter wrdev, iclass 5, count 0 2006.285.21:17:13.59#ibcon#first serial, iclass 5, count 0 2006.285.21:17:13.59#ibcon#enter sib2, iclass 5, count 0 2006.285.21:17:13.59#ibcon#flushed, iclass 5, count 0 2006.285.21:17:13.59#ibcon#about to write, iclass 5, count 0 2006.285.21:17:13.59#ibcon#wrote, iclass 5, count 0 2006.285.21:17:13.59#ibcon#about to read 3, iclass 5, count 0 2006.285.21:17:13.60#ibcon#read 3, iclass 5, count 0 2006.285.21:17:13.60#ibcon#about to read 4, iclass 5, count 0 2006.285.21:17:13.60#ibcon#read 4, iclass 5, count 0 2006.285.21:17:13.60#ibcon#about to read 5, iclass 5, count 0 2006.285.21:17:13.60#ibcon#read 5, iclass 5, count 0 2006.285.21:17:13.60#ibcon#about to read 6, iclass 5, count 0 2006.285.21:17:13.60#ibcon#read 6, iclass 5, count 0 2006.285.21:17:13.60#ibcon#end of sib2, iclass 5, count 0 2006.285.21:17:13.60#ibcon#*mode == 0, iclass 5, count 0 2006.285.21:17:13.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.21:17:13.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:17:13.61#ibcon#*before write, iclass 5, count 0 2006.285.21:17:13.61#ibcon#enter sib2, iclass 5, count 0 2006.285.21:17:13.61#ibcon#flushed, iclass 5, count 0 2006.285.21:17:13.61#ibcon#about to write, iclass 5, count 0 2006.285.21:17:13.61#ibcon#wrote, iclass 5, count 0 2006.285.21:17:13.61#ibcon#about to read 3, iclass 5, count 0 2006.285.21:17:13.64#ibcon#read 3, iclass 5, count 0 2006.285.21:17:13.64#ibcon#about to read 4, iclass 5, count 0 2006.285.21:17:13.64#ibcon#read 4, iclass 5, count 0 2006.285.21:17:13.64#ibcon#about to read 5, iclass 5, count 0 2006.285.21:17:13.64#ibcon#read 5, iclass 5, count 0 2006.285.21:17:13.64#ibcon#about to read 6, iclass 5, count 0 2006.285.21:17:13.64#ibcon#read 6, iclass 5, count 0 2006.285.21:17:13.64#ibcon#end of sib2, iclass 5, count 0 2006.285.21:17:13.64#ibcon#*after write, iclass 5, count 0 2006.285.21:17:13.64#ibcon#*before return 0, iclass 5, count 0 2006.285.21:17:13.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:17:13.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:17:13.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.21:17:13.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.21:17:13.65$vck44/va=6,4 2006.285.21:17:13.65#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.21:17:13.65#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.21:17:13.65#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:13.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:17:13.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:17:13.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:17:13.70#ibcon#enter wrdev, iclass 7, count 2 2006.285.21:17:13.70#ibcon#first serial, iclass 7, count 2 2006.285.21:17:13.70#ibcon#enter sib2, iclass 7, count 2 2006.285.21:17:13.70#ibcon#flushed, iclass 7, count 2 2006.285.21:17:13.70#ibcon#about to write, iclass 7, count 2 2006.285.21:17:13.70#ibcon#wrote, iclass 7, count 2 2006.285.21:17:13.71#ibcon#about to read 3, iclass 7, count 2 2006.285.21:17:13.72#ibcon#read 3, iclass 7, count 2 2006.285.21:17:13.72#ibcon#about to read 4, iclass 7, count 2 2006.285.21:17:13.72#ibcon#read 4, iclass 7, count 2 2006.285.21:17:13.72#ibcon#about to read 5, iclass 7, count 2 2006.285.21:17:13.72#ibcon#read 5, iclass 7, count 2 2006.285.21:17:13.72#ibcon#about to read 6, iclass 7, count 2 2006.285.21:17:13.72#ibcon#read 6, iclass 7, count 2 2006.285.21:17:13.72#ibcon#end of sib2, iclass 7, count 2 2006.285.21:17:13.72#ibcon#*mode == 0, iclass 7, count 2 2006.285.21:17:13.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.21:17:13.73#ibcon#[25=AT06-04\r\n] 2006.285.21:17:13.73#ibcon#*before write, iclass 7, count 2 2006.285.21:17:13.73#ibcon#enter sib2, iclass 7, count 2 2006.285.21:17:13.73#ibcon#flushed, iclass 7, count 2 2006.285.21:17:13.73#ibcon#about to write, iclass 7, count 2 2006.285.21:17:13.73#ibcon#wrote, iclass 7, count 2 2006.285.21:17:13.73#ibcon#about to read 3, iclass 7, count 2 2006.285.21:17:13.75#ibcon#read 3, iclass 7, count 2 2006.285.21:17:13.75#ibcon#about to read 4, iclass 7, count 2 2006.285.21:17:13.75#ibcon#read 4, iclass 7, count 2 2006.285.21:17:13.75#ibcon#about to read 5, iclass 7, count 2 2006.285.21:17:13.75#ibcon#read 5, iclass 7, count 2 2006.285.21:17:13.75#ibcon#about to read 6, iclass 7, count 2 2006.285.21:17:13.75#ibcon#read 6, iclass 7, count 2 2006.285.21:17:13.75#ibcon#end of sib2, iclass 7, count 2 2006.285.21:17:13.75#ibcon#*after write, iclass 7, count 2 2006.285.21:17:13.75#ibcon#*before return 0, iclass 7, count 2 2006.285.21:17:13.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:17:13.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:17:13.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.21:17:13.76#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:13.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:17:13.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:17:13.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:17:13.87#ibcon#enter wrdev, iclass 7, count 0 2006.285.21:17:13.87#ibcon#first serial, iclass 7, count 0 2006.285.21:17:13.87#ibcon#enter sib2, iclass 7, count 0 2006.285.21:17:13.87#ibcon#flushed, iclass 7, count 0 2006.285.21:17:13.87#ibcon#about to write, iclass 7, count 0 2006.285.21:17:13.87#ibcon#wrote, iclass 7, count 0 2006.285.21:17:13.87#ibcon#about to read 3, iclass 7, count 0 2006.285.21:17:13.89#ibcon#read 3, iclass 7, count 0 2006.285.21:17:13.89#ibcon#about to read 4, iclass 7, count 0 2006.285.21:17:13.89#ibcon#read 4, iclass 7, count 0 2006.285.21:17:13.89#ibcon#about to read 5, iclass 7, count 0 2006.285.21:17:13.89#ibcon#read 5, iclass 7, count 0 2006.285.21:17:13.89#ibcon#about to read 6, iclass 7, count 0 2006.285.21:17:13.89#ibcon#read 6, iclass 7, count 0 2006.285.21:17:13.89#ibcon#end of sib2, iclass 7, count 0 2006.285.21:17:13.89#ibcon#*mode == 0, iclass 7, count 0 2006.285.21:17:13.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.21:17:13.89#ibcon#[25=USB\r\n] 2006.285.21:17:13.90#ibcon#*before write, iclass 7, count 0 2006.285.21:17:13.90#ibcon#enter sib2, iclass 7, count 0 2006.285.21:17:13.90#ibcon#flushed, iclass 7, count 0 2006.285.21:17:13.90#ibcon#about to write, iclass 7, count 0 2006.285.21:17:13.90#ibcon#wrote, iclass 7, count 0 2006.285.21:17:13.90#ibcon#about to read 3, iclass 7, count 0 2006.285.21:17:13.92#ibcon#read 3, iclass 7, count 0 2006.285.21:17:13.92#ibcon#about to read 4, iclass 7, count 0 2006.285.21:17:13.92#ibcon#read 4, iclass 7, count 0 2006.285.21:17:13.92#ibcon#about to read 5, iclass 7, count 0 2006.285.21:17:13.92#ibcon#read 5, iclass 7, count 0 2006.285.21:17:13.92#ibcon#about to read 6, iclass 7, count 0 2006.285.21:17:13.92#ibcon#read 6, iclass 7, count 0 2006.285.21:17:13.92#ibcon#end of sib2, iclass 7, count 0 2006.285.21:17:13.92#ibcon#*after write, iclass 7, count 0 2006.285.21:17:13.92#ibcon#*before return 0, iclass 7, count 0 2006.285.21:17:13.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:17:13.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:17:13.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.21:17:13.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.21:17:13.93$vck44/valo=7,864.99 2006.285.21:17:13.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.21:17:13.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.21:17:13.93#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:13.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:17:13.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:17:13.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:17:13.93#ibcon#enter wrdev, iclass 11, count 0 2006.285.21:17:13.93#ibcon#first serial, iclass 11, count 0 2006.285.21:17:13.93#ibcon#enter sib2, iclass 11, count 0 2006.285.21:17:13.93#ibcon#flushed, iclass 11, count 0 2006.285.21:17:13.93#ibcon#about to write, iclass 11, count 0 2006.285.21:17:13.93#ibcon#wrote, iclass 11, count 0 2006.285.21:17:13.93#ibcon#about to read 3, iclass 11, count 0 2006.285.21:17:13.94#ibcon#read 3, iclass 11, count 0 2006.285.21:17:13.94#ibcon#about to read 4, iclass 11, count 0 2006.285.21:17:13.94#ibcon#read 4, iclass 11, count 0 2006.285.21:17:13.94#ibcon#about to read 5, iclass 11, count 0 2006.285.21:17:13.94#ibcon#read 5, iclass 11, count 0 2006.285.21:17:13.94#ibcon#about to read 6, iclass 11, count 0 2006.285.21:17:13.94#ibcon#read 6, iclass 11, count 0 2006.285.21:17:13.94#ibcon#end of sib2, iclass 11, count 0 2006.285.21:17:13.94#ibcon#*mode == 0, iclass 11, count 0 2006.285.21:17:13.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.21:17:13.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:17:13.95#ibcon#*before write, iclass 11, count 0 2006.285.21:17:13.95#ibcon#enter sib2, iclass 11, count 0 2006.285.21:17:13.95#ibcon#flushed, iclass 11, count 0 2006.285.21:17:13.95#ibcon#about to write, iclass 11, count 0 2006.285.21:17:13.95#ibcon#wrote, iclass 11, count 0 2006.285.21:17:13.95#ibcon#about to read 3, iclass 11, count 0 2006.285.21:17:13.98#ibcon#read 3, iclass 11, count 0 2006.285.21:17:13.98#ibcon#about to read 4, iclass 11, count 0 2006.285.21:17:13.98#ibcon#read 4, iclass 11, count 0 2006.285.21:17:13.98#ibcon#about to read 5, iclass 11, count 0 2006.285.21:17:13.98#ibcon#read 5, iclass 11, count 0 2006.285.21:17:13.98#ibcon#about to read 6, iclass 11, count 0 2006.285.21:17:13.98#ibcon#read 6, iclass 11, count 0 2006.285.21:17:13.99#ibcon#end of sib2, iclass 11, count 0 2006.285.21:17:13.99#ibcon#*after write, iclass 11, count 0 2006.285.21:17:13.99#ibcon#*before return 0, iclass 11, count 0 2006.285.21:17:13.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:17:13.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:17:13.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.21:17:13.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.21:17:13.99$vck44/va=7,4 2006.285.21:17:13.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.21:17:13.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.21:17:13.99#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:13.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:17:14.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:17:14.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:17:14.04#ibcon#enter wrdev, iclass 13, count 2 2006.285.21:17:14.04#ibcon#first serial, iclass 13, count 2 2006.285.21:17:14.04#ibcon#enter sib2, iclass 13, count 2 2006.285.21:17:14.04#ibcon#flushed, iclass 13, count 2 2006.285.21:17:14.04#ibcon#about to write, iclass 13, count 2 2006.285.21:17:14.04#ibcon#wrote, iclass 13, count 2 2006.285.21:17:14.04#ibcon#about to read 3, iclass 13, count 2 2006.285.21:17:14.06#ibcon#read 3, iclass 13, count 2 2006.285.21:17:14.06#ibcon#about to read 4, iclass 13, count 2 2006.285.21:17:14.06#ibcon#read 4, iclass 13, count 2 2006.285.21:17:14.06#ibcon#about to read 5, iclass 13, count 2 2006.285.21:17:14.06#ibcon#read 5, iclass 13, count 2 2006.285.21:17:14.06#ibcon#about to read 6, iclass 13, count 2 2006.285.21:17:14.06#ibcon#read 6, iclass 13, count 2 2006.285.21:17:14.07#ibcon#end of sib2, iclass 13, count 2 2006.285.21:17:14.07#ibcon#*mode == 0, iclass 13, count 2 2006.285.21:17:14.07#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.21:17:14.07#ibcon#[25=AT07-04\r\n] 2006.285.21:17:14.07#ibcon#*before write, iclass 13, count 2 2006.285.21:17:14.07#ibcon#enter sib2, iclass 13, count 2 2006.285.21:17:14.07#ibcon#flushed, iclass 13, count 2 2006.285.21:17:14.07#ibcon#about to write, iclass 13, count 2 2006.285.21:17:14.07#ibcon#wrote, iclass 13, count 2 2006.285.21:17:14.07#ibcon#about to read 3, iclass 13, count 2 2006.285.21:17:14.09#ibcon#read 3, iclass 13, count 2 2006.285.21:17:14.09#ibcon#about to read 4, iclass 13, count 2 2006.285.21:17:14.09#ibcon#read 4, iclass 13, count 2 2006.285.21:17:14.09#ibcon#about to read 5, iclass 13, count 2 2006.285.21:17:14.09#ibcon#read 5, iclass 13, count 2 2006.285.21:17:14.09#ibcon#about to read 6, iclass 13, count 2 2006.285.21:17:14.09#ibcon#read 6, iclass 13, count 2 2006.285.21:17:14.10#ibcon#end of sib2, iclass 13, count 2 2006.285.21:17:14.10#ibcon#*after write, iclass 13, count 2 2006.285.21:17:14.10#ibcon#*before return 0, iclass 13, count 2 2006.285.21:17:14.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:17:14.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:17:14.10#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.21:17:14.10#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:14.10#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:17:14.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:17:14.24#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:17:14.24#ibcon#enter wrdev, iclass 13, count 0 2006.285.21:17:14.24#ibcon#first serial, iclass 13, count 0 2006.285.21:17:14.24#ibcon#enter sib2, iclass 13, count 0 2006.285.21:17:14.24#ibcon#flushed, iclass 13, count 0 2006.285.21:17:14.24#ibcon#about to write, iclass 13, count 0 2006.285.21:17:14.24#ibcon#wrote, iclass 13, count 0 2006.285.21:17:14.24#ibcon#about to read 3, iclass 13, count 0 2006.285.21:17:14.25#ibcon#read 3, iclass 13, count 0 2006.285.21:17:14.25#ibcon#about to read 4, iclass 13, count 0 2006.285.21:17:14.25#ibcon#read 4, iclass 13, count 0 2006.285.21:17:14.25#ibcon#about to read 5, iclass 13, count 0 2006.285.21:17:14.25#ibcon#read 5, iclass 13, count 0 2006.285.21:17:14.25#ibcon#about to read 6, iclass 13, count 0 2006.285.21:17:14.25#ibcon#read 6, iclass 13, count 0 2006.285.21:17:14.26#ibcon#end of sib2, iclass 13, count 0 2006.285.21:17:14.26#ibcon#*mode == 0, iclass 13, count 0 2006.285.21:17:14.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.21:17:14.26#ibcon#[25=USB\r\n] 2006.285.21:17:14.26#ibcon#*before write, iclass 13, count 0 2006.285.21:17:14.26#ibcon#enter sib2, iclass 13, count 0 2006.285.21:17:14.26#ibcon#flushed, iclass 13, count 0 2006.285.21:17:14.26#ibcon#about to write, iclass 13, count 0 2006.285.21:17:14.26#ibcon#wrote, iclass 13, count 0 2006.285.21:17:14.26#ibcon#about to read 3, iclass 13, count 0 2006.285.21:17:14.28#ibcon#read 3, iclass 13, count 0 2006.285.21:17:14.28#ibcon#about to read 4, iclass 13, count 0 2006.285.21:17:14.28#ibcon#read 4, iclass 13, count 0 2006.285.21:17:14.28#ibcon#about to read 5, iclass 13, count 0 2006.285.21:17:14.28#ibcon#read 5, iclass 13, count 0 2006.285.21:17:14.28#ibcon#about to read 6, iclass 13, count 0 2006.285.21:17:14.28#ibcon#read 6, iclass 13, count 0 2006.285.21:17:14.28#ibcon#end of sib2, iclass 13, count 0 2006.285.21:17:14.29#ibcon#*after write, iclass 13, count 0 2006.285.21:17:14.29#ibcon#*before return 0, iclass 13, count 0 2006.285.21:17:14.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:17:14.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:17:14.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.21:17:14.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.21:17:14.29$vck44/valo=8,884.99 2006.285.21:17:14.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.21:17:14.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.21:17:14.29#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:14.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:17:14.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:17:14.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:17:14.29#ibcon#enter wrdev, iclass 15, count 0 2006.285.21:17:14.29#ibcon#first serial, iclass 15, count 0 2006.285.21:17:14.29#ibcon#enter sib2, iclass 15, count 0 2006.285.21:17:14.29#ibcon#flushed, iclass 15, count 0 2006.285.21:17:14.29#ibcon#about to write, iclass 15, count 0 2006.285.21:17:14.29#ibcon#wrote, iclass 15, count 0 2006.285.21:17:14.29#ibcon#about to read 3, iclass 15, count 0 2006.285.21:17:14.30#ibcon#read 3, iclass 15, count 0 2006.285.21:17:14.30#ibcon#about to read 4, iclass 15, count 0 2006.285.21:17:14.30#ibcon#read 4, iclass 15, count 0 2006.285.21:17:14.30#ibcon#about to read 5, iclass 15, count 0 2006.285.21:17:14.30#ibcon#read 5, iclass 15, count 0 2006.285.21:17:14.30#ibcon#about to read 6, iclass 15, count 0 2006.285.21:17:14.30#ibcon#read 6, iclass 15, count 0 2006.285.21:17:14.30#ibcon#end of sib2, iclass 15, count 0 2006.285.21:17:14.31#ibcon#*mode == 0, iclass 15, count 0 2006.285.21:17:14.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.21:17:14.31#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:17:14.31#ibcon#*before write, iclass 15, count 0 2006.285.21:17:14.31#ibcon#enter sib2, iclass 15, count 0 2006.285.21:17:14.31#ibcon#flushed, iclass 15, count 0 2006.285.21:17:14.31#ibcon#about to write, iclass 15, count 0 2006.285.21:17:14.31#ibcon#wrote, iclass 15, count 0 2006.285.21:17:14.31#ibcon#about to read 3, iclass 15, count 0 2006.285.21:17:14.34#ibcon#read 3, iclass 15, count 0 2006.285.21:17:14.34#ibcon#about to read 4, iclass 15, count 0 2006.285.21:17:14.34#ibcon#read 4, iclass 15, count 0 2006.285.21:17:14.34#ibcon#about to read 5, iclass 15, count 0 2006.285.21:17:14.34#ibcon#read 5, iclass 15, count 0 2006.285.21:17:14.34#ibcon#about to read 6, iclass 15, count 0 2006.285.21:17:14.34#ibcon#read 6, iclass 15, count 0 2006.285.21:17:14.34#ibcon#end of sib2, iclass 15, count 0 2006.285.21:17:14.35#ibcon#*after write, iclass 15, count 0 2006.285.21:17:14.35#ibcon#*before return 0, iclass 15, count 0 2006.285.21:17:14.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:17:14.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:17:14.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.21:17:14.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.21:17:14.35$vck44/va=8,3 2006.285.21:17:14.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.21:17:14.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.21:17:14.35#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:14.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:17:14.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:17:14.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:17:14.40#ibcon#enter wrdev, iclass 17, count 2 2006.285.21:17:14.40#ibcon#first serial, iclass 17, count 2 2006.285.21:17:14.40#ibcon#enter sib2, iclass 17, count 2 2006.285.21:17:14.40#ibcon#flushed, iclass 17, count 2 2006.285.21:17:14.40#ibcon#about to write, iclass 17, count 2 2006.285.21:17:14.41#ibcon#wrote, iclass 17, count 2 2006.285.21:17:14.41#ibcon#about to read 3, iclass 17, count 2 2006.285.21:17:14.42#ibcon#read 3, iclass 17, count 2 2006.285.21:17:14.42#ibcon#about to read 4, iclass 17, count 2 2006.285.21:17:14.42#ibcon#read 4, iclass 17, count 2 2006.285.21:17:14.42#ibcon#about to read 5, iclass 17, count 2 2006.285.21:17:14.42#ibcon#read 5, iclass 17, count 2 2006.285.21:17:14.42#ibcon#about to read 6, iclass 17, count 2 2006.285.21:17:14.42#ibcon#read 6, iclass 17, count 2 2006.285.21:17:14.42#ibcon#end of sib2, iclass 17, count 2 2006.285.21:17:14.42#ibcon#*mode == 0, iclass 17, count 2 2006.285.21:17:14.43#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.21:17:14.43#ibcon#[25=AT08-03\r\n] 2006.285.21:17:14.43#ibcon#*before write, iclass 17, count 2 2006.285.21:17:14.43#ibcon#enter sib2, iclass 17, count 2 2006.285.21:17:14.43#ibcon#flushed, iclass 17, count 2 2006.285.21:17:14.43#ibcon#about to write, iclass 17, count 2 2006.285.21:17:14.43#ibcon#wrote, iclass 17, count 2 2006.285.21:17:14.43#ibcon#about to read 3, iclass 17, count 2 2006.285.21:17:14.45#ibcon#read 3, iclass 17, count 2 2006.285.21:17:14.45#ibcon#about to read 4, iclass 17, count 2 2006.285.21:17:14.45#ibcon#read 4, iclass 17, count 2 2006.285.21:17:14.45#ibcon#about to read 5, iclass 17, count 2 2006.285.21:17:14.45#ibcon#read 5, iclass 17, count 2 2006.285.21:17:14.45#ibcon#about to read 6, iclass 17, count 2 2006.285.21:17:14.45#ibcon#read 6, iclass 17, count 2 2006.285.21:17:14.45#ibcon#end of sib2, iclass 17, count 2 2006.285.21:17:14.45#ibcon#*after write, iclass 17, count 2 2006.285.21:17:14.46#ibcon#*before return 0, iclass 17, count 2 2006.285.21:17:14.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:17:14.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:17:14.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.21:17:14.46#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:14.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:17:14.57#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:17:14.57#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:17:14.57#ibcon#enter wrdev, iclass 17, count 0 2006.285.21:17:14.57#ibcon#first serial, iclass 17, count 0 2006.285.21:17:14.57#ibcon#enter sib2, iclass 17, count 0 2006.285.21:17:14.57#ibcon#flushed, iclass 17, count 0 2006.285.21:17:14.57#ibcon#about to write, iclass 17, count 0 2006.285.21:17:14.57#ibcon#wrote, iclass 17, count 0 2006.285.21:17:14.57#ibcon#about to read 3, iclass 17, count 0 2006.285.21:17:14.59#ibcon#read 3, iclass 17, count 0 2006.285.21:17:14.59#ibcon#about to read 4, iclass 17, count 0 2006.285.21:17:14.59#ibcon#read 4, iclass 17, count 0 2006.285.21:17:14.59#ibcon#about to read 5, iclass 17, count 0 2006.285.21:17:14.59#ibcon#read 5, iclass 17, count 0 2006.285.21:17:14.59#ibcon#about to read 6, iclass 17, count 0 2006.285.21:17:14.59#ibcon#read 6, iclass 17, count 0 2006.285.21:17:14.59#ibcon#end of sib2, iclass 17, count 0 2006.285.21:17:14.59#ibcon#*mode == 0, iclass 17, count 0 2006.285.21:17:14.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.21:17:14.59#ibcon#[25=USB\r\n] 2006.285.21:17:14.60#ibcon#*before write, iclass 17, count 0 2006.285.21:17:14.60#ibcon#enter sib2, iclass 17, count 0 2006.285.21:17:14.60#ibcon#flushed, iclass 17, count 0 2006.285.21:17:14.60#ibcon#about to write, iclass 17, count 0 2006.285.21:17:14.60#ibcon#wrote, iclass 17, count 0 2006.285.21:17:14.60#ibcon#about to read 3, iclass 17, count 0 2006.285.21:17:14.62#ibcon#read 3, iclass 17, count 0 2006.285.21:17:14.62#ibcon#about to read 4, iclass 17, count 0 2006.285.21:17:14.62#ibcon#read 4, iclass 17, count 0 2006.285.21:17:14.62#ibcon#about to read 5, iclass 17, count 0 2006.285.21:17:14.62#ibcon#read 5, iclass 17, count 0 2006.285.21:17:14.62#ibcon#about to read 6, iclass 17, count 0 2006.285.21:17:14.62#ibcon#read 6, iclass 17, count 0 2006.285.21:17:14.62#ibcon#end of sib2, iclass 17, count 0 2006.285.21:17:14.62#ibcon#*after write, iclass 17, count 0 2006.285.21:17:14.62#ibcon#*before return 0, iclass 17, count 0 2006.285.21:17:14.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:17:14.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:17:14.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.21:17:14.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.21:17:14.63$vck44/vblo=1,629.99 2006.285.21:17:14.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.21:17:14.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.21:17:14.63#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:14.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:17:14.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:17:14.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:17:14.63#ibcon#enter wrdev, iclass 19, count 0 2006.285.21:17:14.63#ibcon#first serial, iclass 19, count 0 2006.285.21:17:14.63#ibcon#enter sib2, iclass 19, count 0 2006.285.21:17:14.63#ibcon#flushed, iclass 19, count 0 2006.285.21:17:14.63#ibcon#about to write, iclass 19, count 0 2006.285.21:17:14.63#ibcon#wrote, iclass 19, count 0 2006.285.21:17:14.63#ibcon#about to read 3, iclass 19, count 0 2006.285.21:17:14.64#ibcon#read 3, iclass 19, count 0 2006.285.21:17:14.64#ibcon#about to read 4, iclass 19, count 0 2006.285.21:17:14.64#ibcon#read 4, iclass 19, count 0 2006.285.21:17:14.64#ibcon#about to read 5, iclass 19, count 0 2006.285.21:17:14.64#ibcon#read 5, iclass 19, count 0 2006.285.21:17:14.64#ibcon#about to read 6, iclass 19, count 0 2006.285.21:17:14.64#ibcon#read 6, iclass 19, count 0 2006.285.21:17:14.64#ibcon#end of sib2, iclass 19, count 0 2006.285.21:17:14.64#ibcon#*mode == 0, iclass 19, count 0 2006.285.21:17:14.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.21:17:14.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:17:14.65#ibcon#*before write, iclass 19, count 0 2006.285.21:17:14.65#ibcon#enter sib2, iclass 19, count 0 2006.285.21:17:14.65#ibcon#flushed, iclass 19, count 0 2006.285.21:17:14.65#ibcon#about to write, iclass 19, count 0 2006.285.21:17:14.65#ibcon#wrote, iclass 19, count 0 2006.285.21:17:14.65#ibcon#about to read 3, iclass 19, count 0 2006.285.21:17:14.68#ibcon#read 3, iclass 19, count 0 2006.285.21:17:14.68#ibcon#about to read 4, iclass 19, count 0 2006.285.21:17:14.68#ibcon#read 4, iclass 19, count 0 2006.285.21:17:14.68#ibcon#about to read 5, iclass 19, count 0 2006.285.21:17:14.68#ibcon#read 5, iclass 19, count 0 2006.285.21:17:14.68#ibcon#about to read 6, iclass 19, count 0 2006.285.21:17:14.68#ibcon#read 6, iclass 19, count 0 2006.285.21:17:14.68#ibcon#end of sib2, iclass 19, count 0 2006.285.21:17:14.68#ibcon#*after write, iclass 19, count 0 2006.285.21:17:14.68#ibcon#*before return 0, iclass 19, count 0 2006.285.21:17:14.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:17:14.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:17:14.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.21:17:14.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.21:17:14.69$vck44/vb=1,4 2006.285.21:17:14.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.21:17:14.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.21:17:14.69#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:14.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:17:14.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:17:14.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:17:14.69#ibcon#enter wrdev, iclass 21, count 2 2006.285.21:17:14.69#ibcon#first serial, iclass 21, count 2 2006.285.21:17:14.69#ibcon#enter sib2, iclass 21, count 2 2006.285.21:17:14.69#ibcon#flushed, iclass 21, count 2 2006.285.21:17:14.69#ibcon#about to write, iclass 21, count 2 2006.285.21:17:14.69#ibcon#wrote, iclass 21, count 2 2006.285.21:17:14.69#ibcon#about to read 3, iclass 21, count 2 2006.285.21:17:14.70#ibcon#read 3, iclass 21, count 2 2006.285.21:17:14.70#ibcon#about to read 4, iclass 21, count 2 2006.285.21:17:14.70#ibcon#read 4, iclass 21, count 2 2006.285.21:17:14.70#ibcon#about to read 5, iclass 21, count 2 2006.285.21:17:14.70#ibcon#read 5, iclass 21, count 2 2006.285.21:17:14.70#ibcon#about to read 6, iclass 21, count 2 2006.285.21:17:14.70#ibcon#read 6, iclass 21, count 2 2006.285.21:17:14.70#ibcon#end of sib2, iclass 21, count 2 2006.285.21:17:14.70#ibcon#*mode == 0, iclass 21, count 2 2006.285.21:17:14.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.21:17:14.71#ibcon#[27=AT01-04\r\n] 2006.285.21:17:14.71#ibcon#*before write, iclass 21, count 2 2006.285.21:17:14.71#ibcon#enter sib2, iclass 21, count 2 2006.285.21:17:14.71#ibcon#flushed, iclass 21, count 2 2006.285.21:17:14.71#ibcon#about to write, iclass 21, count 2 2006.285.21:17:14.71#ibcon#wrote, iclass 21, count 2 2006.285.21:17:14.71#ibcon#about to read 3, iclass 21, count 2 2006.285.21:17:14.73#ibcon#read 3, iclass 21, count 2 2006.285.21:17:14.73#ibcon#about to read 4, iclass 21, count 2 2006.285.21:17:14.73#ibcon#read 4, iclass 21, count 2 2006.285.21:17:14.73#ibcon#about to read 5, iclass 21, count 2 2006.285.21:17:14.73#ibcon#read 5, iclass 21, count 2 2006.285.21:17:14.73#ibcon#about to read 6, iclass 21, count 2 2006.285.21:17:14.73#ibcon#read 6, iclass 21, count 2 2006.285.21:17:14.73#ibcon#end of sib2, iclass 21, count 2 2006.285.21:17:14.73#ibcon#*after write, iclass 21, count 2 2006.285.21:17:14.73#ibcon#*before return 0, iclass 21, count 2 2006.285.21:17:14.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:17:14.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:17:14.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.21:17:14.74#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:14.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:17:14.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:17:14.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:17:14.85#ibcon#enter wrdev, iclass 21, count 0 2006.285.21:17:14.85#ibcon#first serial, iclass 21, count 0 2006.285.21:17:14.85#ibcon#enter sib2, iclass 21, count 0 2006.285.21:17:14.85#ibcon#flushed, iclass 21, count 0 2006.285.21:17:14.85#ibcon#about to write, iclass 21, count 0 2006.285.21:17:14.85#ibcon#wrote, iclass 21, count 0 2006.285.21:17:14.85#ibcon#about to read 3, iclass 21, count 0 2006.285.21:17:14.87#ibcon#read 3, iclass 21, count 0 2006.285.21:17:14.87#ibcon#about to read 4, iclass 21, count 0 2006.285.21:17:14.87#ibcon#read 4, iclass 21, count 0 2006.285.21:17:14.87#ibcon#about to read 5, iclass 21, count 0 2006.285.21:17:14.87#ibcon#read 5, iclass 21, count 0 2006.285.21:17:14.87#ibcon#about to read 6, iclass 21, count 0 2006.285.21:17:14.87#ibcon#read 6, iclass 21, count 0 2006.285.21:17:14.87#ibcon#end of sib2, iclass 21, count 0 2006.285.21:17:14.87#ibcon#*mode == 0, iclass 21, count 0 2006.285.21:17:14.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.21:17:14.87#ibcon#[27=USB\r\n] 2006.285.21:17:14.88#ibcon#*before write, iclass 21, count 0 2006.285.21:17:14.88#ibcon#enter sib2, iclass 21, count 0 2006.285.21:17:14.88#ibcon#flushed, iclass 21, count 0 2006.285.21:17:14.88#ibcon#about to write, iclass 21, count 0 2006.285.21:17:14.88#ibcon#wrote, iclass 21, count 0 2006.285.21:17:14.88#ibcon#about to read 3, iclass 21, count 0 2006.285.21:17:14.90#ibcon#read 3, iclass 21, count 0 2006.285.21:17:14.90#ibcon#about to read 4, iclass 21, count 0 2006.285.21:17:14.90#ibcon#read 4, iclass 21, count 0 2006.285.21:17:14.90#ibcon#about to read 5, iclass 21, count 0 2006.285.21:17:14.90#ibcon#read 5, iclass 21, count 0 2006.285.21:17:14.90#ibcon#about to read 6, iclass 21, count 0 2006.285.21:17:14.90#ibcon#read 6, iclass 21, count 0 2006.285.21:17:14.90#ibcon#end of sib2, iclass 21, count 0 2006.285.21:17:14.90#ibcon#*after write, iclass 21, count 0 2006.285.21:17:14.90#ibcon#*before return 0, iclass 21, count 0 2006.285.21:17:14.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:17:14.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:17:14.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.21:17:14.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.21:17:14.91$vck44/vblo=2,634.99 2006.285.21:17:14.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.21:17:14.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.21:17:14.91#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:14.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:17:14.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:17:14.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:17:14.91#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:17:14.91#ibcon#first serial, iclass 23, count 0 2006.285.21:17:14.91#ibcon#enter sib2, iclass 23, count 0 2006.285.21:17:14.91#ibcon#flushed, iclass 23, count 0 2006.285.21:17:14.91#ibcon#about to write, iclass 23, count 0 2006.285.21:17:14.91#ibcon#wrote, iclass 23, count 0 2006.285.21:17:14.91#ibcon#about to read 3, iclass 23, count 0 2006.285.21:17:14.92#ibcon#read 3, iclass 23, count 0 2006.285.21:17:14.92#ibcon#about to read 4, iclass 23, count 0 2006.285.21:17:14.92#ibcon#read 4, iclass 23, count 0 2006.285.21:17:14.92#ibcon#about to read 5, iclass 23, count 0 2006.285.21:17:14.92#ibcon#read 5, iclass 23, count 0 2006.285.21:17:14.92#ibcon#about to read 6, iclass 23, count 0 2006.285.21:17:14.92#ibcon#read 6, iclass 23, count 0 2006.285.21:17:14.92#ibcon#end of sib2, iclass 23, count 0 2006.285.21:17:14.92#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:17:14.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:17:14.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:17:14.93#ibcon#*before write, iclass 23, count 0 2006.285.21:17:14.93#ibcon#enter sib2, iclass 23, count 0 2006.285.21:17:14.93#ibcon#flushed, iclass 23, count 0 2006.285.21:17:14.93#ibcon#about to write, iclass 23, count 0 2006.285.21:17:14.93#ibcon#wrote, iclass 23, count 0 2006.285.21:17:14.93#ibcon#about to read 3, iclass 23, count 0 2006.285.21:17:14.96#ibcon#read 3, iclass 23, count 0 2006.285.21:17:14.96#ibcon#about to read 4, iclass 23, count 0 2006.285.21:17:14.96#ibcon#read 4, iclass 23, count 0 2006.285.21:17:14.96#ibcon#about to read 5, iclass 23, count 0 2006.285.21:17:14.96#ibcon#read 5, iclass 23, count 0 2006.285.21:17:14.96#ibcon#about to read 6, iclass 23, count 0 2006.285.21:17:14.97#ibcon#read 6, iclass 23, count 0 2006.285.21:17:14.97#ibcon#end of sib2, iclass 23, count 0 2006.285.21:17:14.97#ibcon#*after write, iclass 23, count 0 2006.285.21:17:14.97#ibcon#*before return 0, iclass 23, count 0 2006.285.21:17:14.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:17:14.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:17:14.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:17:14.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:17:14.97$vck44/vb=2,5 2006.285.21:17:14.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.21:17:14.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.21:17:14.97#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:14.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:17:15.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:17:15.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:17:15.02#ibcon#enter wrdev, iclass 25, count 2 2006.285.21:17:15.02#ibcon#first serial, iclass 25, count 2 2006.285.21:17:15.02#ibcon#enter sib2, iclass 25, count 2 2006.285.21:17:15.02#ibcon#flushed, iclass 25, count 2 2006.285.21:17:15.02#ibcon#about to write, iclass 25, count 2 2006.285.21:17:15.03#ibcon#wrote, iclass 25, count 2 2006.285.21:17:15.03#ibcon#about to read 3, iclass 25, count 2 2006.285.21:17:15.04#ibcon#read 3, iclass 25, count 2 2006.285.21:17:15.04#ibcon#about to read 4, iclass 25, count 2 2006.285.21:17:15.04#ibcon#read 4, iclass 25, count 2 2006.285.21:17:15.04#ibcon#about to read 5, iclass 25, count 2 2006.285.21:17:15.04#ibcon#read 5, iclass 25, count 2 2006.285.21:17:15.04#ibcon#about to read 6, iclass 25, count 2 2006.285.21:17:15.04#ibcon#read 6, iclass 25, count 2 2006.285.21:17:15.04#ibcon#end of sib2, iclass 25, count 2 2006.285.21:17:15.05#ibcon#*mode == 0, iclass 25, count 2 2006.285.21:17:15.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.21:17:15.05#ibcon#[27=AT02-05\r\n] 2006.285.21:17:15.05#ibcon#*before write, iclass 25, count 2 2006.285.21:17:15.05#ibcon#enter sib2, iclass 25, count 2 2006.285.21:17:15.05#ibcon#flushed, iclass 25, count 2 2006.285.21:17:15.05#ibcon#about to write, iclass 25, count 2 2006.285.21:17:15.05#ibcon#wrote, iclass 25, count 2 2006.285.21:17:15.05#ibcon#about to read 3, iclass 25, count 2 2006.285.21:17:15.07#ibcon#read 3, iclass 25, count 2 2006.285.21:17:15.07#ibcon#about to read 4, iclass 25, count 2 2006.285.21:17:15.07#ibcon#read 4, iclass 25, count 2 2006.285.21:17:15.07#ibcon#about to read 5, iclass 25, count 2 2006.285.21:17:15.07#ibcon#read 5, iclass 25, count 2 2006.285.21:17:15.07#ibcon#about to read 6, iclass 25, count 2 2006.285.21:17:15.07#ibcon#read 6, iclass 25, count 2 2006.285.21:17:15.08#ibcon#end of sib2, iclass 25, count 2 2006.285.21:17:15.08#ibcon#*after write, iclass 25, count 2 2006.285.21:17:15.08#ibcon#*before return 0, iclass 25, count 2 2006.285.21:17:15.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:17:15.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:17:15.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.21:17:15.08#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:15.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:17:15.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:17:15.25#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:17:15.25#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:17:15.25#ibcon#first serial, iclass 25, count 0 2006.285.21:17:15.25#ibcon#enter sib2, iclass 25, count 0 2006.285.21:17:15.25#ibcon#flushed, iclass 25, count 0 2006.285.21:17:15.25#ibcon#about to write, iclass 25, count 0 2006.285.21:17:15.25#ibcon#wrote, iclass 25, count 0 2006.285.21:17:15.25#ibcon#about to read 3, iclass 25, count 0 2006.285.21:17:15.26#ibcon#read 3, iclass 25, count 0 2006.285.21:17:15.26#ibcon#about to read 4, iclass 25, count 0 2006.285.21:17:15.26#ibcon#read 4, iclass 25, count 0 2006.285.21:17:15.26#ibcon#about to read 5, iclass 25, count 0 2006.285.21:17:15.26#ibcon#read 5, iclass 25, count 0 2006.285.21:17:15.26#ibcon#about to read 6, iclass 25, count 0 2006.285.21:17:15.26#ibcon#read 6, iclass 25, count 0 2006.285.21:17:15.26#ibcon#end of sib2, iclass 25, count 0 2006.285.21:17:15.27#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:17:15.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:17:15.27#ibcon#[27=USB\r\n] 2006.285.21:17:15.27#ibcon#*before write, iclass 25, count 0 2006.285.21:17:15.27#ibcon#enter sib2, iclass 25, count 0 2006.285.21:17:15.27#ibcon#flushed, iclass 25, count 0 2006.285.21:17:15.27#ibcon#about to write, iclass 25, count 0 2006.285.21:17:15.27#ibcon#wrote, iclass 25, count 0 2006.285.21:17:15.27#ibcon#about to read 3, iclass 25, count 0 2006.285.21:17:15.29#ibcon#read 3, iclass 25, count 0 2006.285.21:17:15.29#ibcon#about to read 4, iclass 25, count 0 2006.285.21:17:15.29#ibcon#read 4, iclass 25, count 0 2006.285.21:17:15.29#ibcon#about to read 5, iclass 25, count 0 2006.285.21:17:15.29#ibcon#read 5, iclass 25, count 0 2006.285.21:17:15.29#ibcon#about to read 6, iclass 25, count 0 2006.285.21:17:15.29#ibcon#read 6, iclass 25, count 0 2006.285.21:17:15.29#ibcon#end of sib2, iclass 25, count 0 2006.285.21:17:15.30#ibcon#*after write, iclass 25, count 0 2006.285.21:17:15.30#ibcon#*before return 0, iclass 25, count 0 2006.285.21:17:15.30#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:17:15.30#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:17:15.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:17:15.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:17:15.30$vck44/vblo=3,649.99 2006.285.21:17:15.30#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.21:17:15.30#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.21:17:15.30#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:15.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:17:15.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:17:15.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:17:15.30#ibcon#enter wrdev, iclass 27, count 0 2006.285.21:17:15.30#ibcon#first serial, iclass 27, count 0 2006.285.21:17:15.30#ibcon#enter sib2, iclass 27, count 0 2006.285.21:17:15.30#ibcon#flushed, iclass 27, count 0 2006.285.21:17:15.30#ibcon#about to write, iclass 27, count 0 2006.285.21:17:15.30#ibcon#wrote, iclass 27, count 0 2006.285.21:17:15.30#ibcon#about to read 3, iclass 27, count 0 2006.285.21:17:15.31#ibcon#read 3, iclass 27, count 0 2006.285.21:17:15.31#ibcon#about to read 4, iclass 27, count 0 2006.285.21:17:15.31#ibcon#read 4, iclass 27, count 0 2006.285.21:17:15.31#ibcon#about to read 5, iclass 27, count 0 2006.285.21:17:15.31#ibcon#read 5, iclass 27, count 0 2006.285.21:17:15.31#ibcon#about to read 6, iclass 27, count 0 2006.285.21:17:15.31#ibcon#read 6, iclass 27, count 0 2006.285.21:17:15.31#ibcon#end of sib2, iclass 27, count 0 2006.285.21:17:15.32#ibcon#*mode == 0, iclass 27, count 0 2006.285.21:17:15.32#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.21:17:15.32#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:17:15.32#ibcon#*before write, iclass 27, count 0 2006.285.21:17:15.32#ibcon#enter sib2, iclass 27, count 0 2006.285.21:17:15.32#ibcon#flushed, iclass 27, count 0 2006.285.21:17:15.32#ibcon#about to write, iclass 27, count 0 2006.285.21:17:15.32#ibcon#wrote, iclass 27, count 0 2006.285.21:17:15.32#ibcon#about to read 3, iclass 27, count 0 2006.285.21:17:15.35#ibcon#read 3, iclass 27, count 0 2006.285.21:17:15.35#ibcon#about to read 4, iclass 27, count 0 2006.285.21:17:15.35#ibcon#read 4, iclass 27, count 0 2006.285.21:17:15.35#ibcon#about to read 5, iclass 27, count 0 2006.285.21:17:15.35#ibcon#read 5, iclass 27, count 0 2006.285.21:17:15.35#ibcon#about to read 6, iclass 27, count 0 2006.285.21:17:15.35#ibcon#read 6, iclass 27, count 0 2006.285.21:17:15.35#ibcon#end of sib2, iclass 27, count 0 2006.285.21:17:15.36#ibcon#*after write, iclass 27, count 0 2006.285.21:17:15.36#ibcon#*before return 0, iclass 27, count 0 2006.285.21:17:15.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:17:15.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:17:15.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.21:17:15.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.21:17:15.36$vck44/vb=3,4 2006.285.21:17:15.36#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.21:17:15.36#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.21:17:15.36#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:15.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:17:15.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:17:15.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:17:15.41#ibcon#enter wrdev, iclass 29, count 2 2006.285.21:17:15.41#ibcon#first serial, iclass 29, count 2 2006.285.21:17:15.41#ibcon#enter sib2, iclass 29, count 2 2006.285.21:17:15.41#ibcon#flushed, iclass 29, count 2 2006.285.21:17:15.41#ibcon#about to write, iclass 29, count 2 2006.285.21:17:15.41#ibcon#wrote, iclass 29, count 2 2006.285.21:17:15.42#ibcon#about to read 3, iclass 29, count 2 2006.285.21:17:15.43#ibcon#read 3, iclass 29, count 2 2006.285.21:17:15.43#ibcon#about to read 4, iclass 29, count 2 2006.285.21:17:15.43#ibcon#read 4, iclass 29, count 2 2006.285.21:17:15.43#ibcon#about to read 5, iclass 29, count 2 2006.285.21:17:15.43#ibcon#read 5, iclass 29, count 2 2006.285.21:17:15.43#ibcon#about to read 6, iclass 29, count 2 2006.285.21:17:15.43#ibcon#read 6, iclass 29, count 2 2006.285.21:17:15.43#ibcon#end of sib2, iclass 29, count 2 2006.285.21:17:15.43#ibcon#*mode == 0, iclass 29, count 2 2006.285.21:17:15.43#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.21:17:15.43#ibcon#[27=AT03-04\r\n] 2006.285.21:17:15.44#ibcon#*before write, iclass 29, count 2 2006.285.21:17:15.44#ibcon#enter sib2, iclass 29, count 2 2006.285.21:17:15.44#ibcon#flushed, iclass 29, count 2 2006.285.21:17:15.44#ibcon#about to write, iclass 29, count 2 2006.285.21:17:15.44#ibcon#wrote, iclass 29, count 2 2006.285.21:17:15.44#ibcon#about to read 3, iclass 29, count 2 2006.285.21:17:15.46#ibcon#read 3, iclass 29, count 2 2006.285.21:17:15.46#ibcon#about to read 4, iclass 29, count 2 2006.285.21:17:15.46#ibcon#read 4, iclass 29, count 2 2006.285.21:17:15.46#ibcon#about to read 5, iclass 29, count 2 2006.285.21:17:15.46#ibcon#read 5, iclass 29, count 2 2006.285.21:17:15.46#ibcon#about to read 6, iclass 29, count 2 2006.285.21:17:15.46#ibcon#read 6, iclass 29, count 2 2006.285.21:17:15.46#ibcon#end of sib2, iclass 29, count 2 2006.285.21:17:15.46#ibcon#*after write, iclass 29, count 2 2006.285.21:17:15.46#ibcon#*before return 0, iclass 29, count 2 2006.285.21:17:15.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:17:15.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:17:15.47#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.21:17:15.47#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:15.47#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:17:15.58#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:17:15.58#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:17:15.58#ibcon#enter wrdev, iclass 29, count 0 2006.285.21:17:15.58#ibcon#first serial, iclass 29, count 0 2006.285.21:17:15.58#ibcon#enter sib2, iclass 29, count 0 2006.285.21:17:15.58#ibcon#flushed, iclass 29, count 0 2006.285.21:17:15.58#ibcon#about to write, iclass 29, count 0 2006.285.21:17:15.58#ibcon#wrote, iclass 29, count 0 2006.285.21:17:15.58#ibcon#about to read 3, iclass 29, count 0 2006.285.21:17:15.60#ibcon#read 3, iclass 29, count 0 2006.285.21:17:15.60#ibcon#about to read 4, iclass 29, count 0 2006.285.21:17:15.60#ibcon#read 4, iclass 29, count 0 2006.285.21:17:15.60#ibcon#about to read 5, iclass 29, count 0 2006.285.21:17:15.60#ibcon#read 5, iclass 29, count 0 2006.285.21:17:15.60#ibcon#about to read 6, iclass 29, count 0 2006.285.21:17:15.60#ibcon#read 6, iclass 29, count 0 2006.285.21:17:15.60#ibcon#end of sib2, iclass 29, count 0 2006.285.21:17:15.60#ibcon#*mode == 0, iclass 29, count 0 2006.285.21:17:15.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.21:17:15.60#ibcon#[27=USB\r\n] 2006.285.21:17:15.61#ibcon#*before write, iclass 29, count 0 2006.285.21:17:15.61#ibcon#enter sib2, iclass 29, count 0 2006.285.21:17:15.61#ibcon#flushed, iclass 29, count 0 2006.285.21:17:15.61#ibcon#about to write, iclass 29, count 0 2006.285.21:17:15.61#ibcon#wrote, iclass 29, count 0 2006.285.21:17:15.61#ibcon#about to read 3, iclass 29, count 0 2006.285.21:17:15.63#ibcon#read 3, iclass 29, count 0 2006.285.21:17:15.63#ibcon#about to read 4, iclass 29, count 0 2006.285.21:17:15.63#ibcon#read 4, iclass 29, count 0 2006.285.21:17:15.63#ibcon#about to read 5, iclass 29, count 0 2006.285.21:17:15.63#ibcon#read 5, iclass 29, count 0 2006.285.21:17:15.63#ibcon#about to read 6, iclass 29, count 0 2006.285.21:17:15.63#ibcon#read 6, iclass 29, count 0 2006.285.21:17:15.63#ibcon#end of sib2, iclass 29, count 0 2006.285.21:17:15.63#ibcon#*after write, iclass 29, count 0 2006.285.21:17:15.63#ibcon#*before return 0, iclass 29, count 0 2006.285.21:17:15.64#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:17:15.64#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:17:15.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.21:17:15.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.21:17:15.64$vck44/vblo=4,679.99 2006.285.21:17:15.64#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.21:17:15.64#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.21:17:15.64#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:15.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:17:15.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:17:15.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:17:15.64#ibcon#enter wrdev, iclass 31, count 0 2006.285.21:17:15.64#ibcon#first serial, iclass 31, count 0 2006.285.21:17:15.64#ibcon#enter sib2, iclass 31, count 0 2006.285.21:17:15.64#ibcon#flushed, iclass 31, count 0 2006.285.21:17:15.64#ibcon#about to write, iclass 31, count 0 2006.285.21:17:15.64#ibcon#wrote, iclass 31, count 0 2006.285.21:17:15.64#ibcon#about to read 3, iclass 31, count 0 2006.285.21:17:15.65#ibcon#read 3, iclass 31, count 0 2006.285.21:17:15.65#ibcon#about to read 4, iclass 31, count 0 2006.285.21:17:15.65#ibcon#read 4, iclass 31, count 0 2006.285.21:17:15.65#ibcon#about to read 5, iclass 31, count 0 2006.285.21:17:15.65#ibcon#read 5, iclass 31, count 0 2006.285.21:17:15.65#ibcon#about to read 6, iclass 31, count 0 2006.285.21:17:15.65#ibcon#read 6, iclass 31, count 0 2006.285.21:17:15.65#ibcon#end of sib2, iclass 31, count 0 2006.285.21:17:15.65#ibcon#*mode == 0, iclass 31, count 0 2006.285.21:17:15.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.21:17:15.66#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:17:15.66#ibcon#*before write, iclass 31, count 0 2006.285.21:17:15.66#ibcon#enter sib2, iclass 31, count 0 2006.285.21:17:15.66#ibcon#flushed, iclass 31, count 0 2006.285.21:17:15.66#ibcon#about to write, iclass 31, count 0 2006.285.21:17:15.66#ibcon#wrote, iclass 31, count 0 2006.285.21:17:15.66#ibcon#about to read 3, iclass 31, count 0 2006.285.21:17:15.69#ibcon#read 3, iclass 31, count 0 2006.285.21:17:15.69#ibcon#about to read 4, iclass 31, count 0 2006.285.21:17:15.69#ibcon#read 4, iclass 31, count 0 2006.285.21:17:15.69#ibcon#about to read 5, iclass 31, count 0 2006.285.21:17:15.69#ibcon#read 5, iclass 31, count 0 2006.285.21:17:15.69#ibcon#about to read 6, iclass 31, count 0 2006.285.21:17:15.69#ibcon#read 6, iclass 31, count 0 2006.285.21:17:15.69#ibcon#end of sib2, iclass 31, count 0 2006.285.21:17:15.69#ibcon#*after write, iclass 31, count 0 2006.285.21:17:15.69#ibcon#*before return 0, iclass 31, count 0 2006.285.21:17:15.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:17:15.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:17:15.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.21:17:15.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.21:17:15.70$vck44/vb=4,5 2006.285.21:17:15.70#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.21:17:15.70#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.21:17:15.70#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:15.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:17:15.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:17:15.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:17:15.75#ibcon#enter wrdev, iclass 33, count 2 2006.285.21:17:15.75#ibcon#first serial, iclass 33, count 2 2006.285.21:17:15.75#ibcon#enter sib2, iclass 33, count 2 2006.285.21:17:15.75#ibcon#flushed, iclass 33, count 2 2006.285.21:17:15.75#ibcon#about to write, iclass 33, count 2 2006.285.21:17:15.75#ibcon#wrote, iclass 33, count 2 2006.285.21:17:15.75#ibcon#about to read 3, iclass 33, count 2 2006.285.21:17:15.77#ibcon#read 3, iclass 33, count 2 2006.285.21:17:15.77#ibcon#about to read 4, iclass 33, count 2 2006.285.21:17:15.77#ibcon#read 4, iclass 33, count 2 2006.285.21:17:15.77#ibcon#about to read 5, iclass 33, count 2 2006.285.21:17:15.77#ibcon#read 5, iclass 33, count 2 2006.285.21:17:15.77#ibcon#about to read 6, iclass 33, count 2 2006.285.21:17:15.77#ibcon#read 6, iclass 33, count 2 2006.285.21:17:15.77#ibcon#end of sib2, iclass 33, count 2 2006.285.21:17:15.77#ibcon#*mode == 0, iclass 33, count 2 2006.285.21:17:15.77#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.21:17:15.77#ibcon#[27=AT04-05\r\n] 2006.285.21:17:15.78#ibcon#*before write, iclass 33, count 2 2006.285.21:17:15.78#ibcon#enter sib2, iclass 33, count 2 2006.285.21:17:15.78#ibcon#flushed, iclass 33, count 2 2006.285.21:17:15.78#ibcon#about to write, iclass 33, count 2 2006.285.21:17:15.78#ibcon#wrote, iclass 33, count 2 2006.285.21:17:15.78#ibcon#about to read 3, iclass 33, count 2 2006.285.21:17:15.80#ibcon#read 3, iclass 33, count 2 2006.285.21:17:15.80#ibcon#about to read 4, iclass 33, count 2 2006.285.21:17:15.80#ibcon#read 4, iclass 33, count 2 2006.285.21:17:15.80#ibcon#about to read 5, iclass 33, count 2 2006.285.21:17:15.80#ibcon#read 5, iclass 33, count 2 2006.285.21:17:15.80#ibcon#about to read 6, iclass 33, count 2 2006.285.21:17:15.80#ibcon#read 6, iclass 33, count 2 2006.285.21:17:15.80#ibcon#end of sib2, iclass 33, count 2 2006.285.21:17:15.80#ibcon#*after write, iclass 33, count 2 2006.285.21:17:15.80#ibcon#*before return 0, iclass 33, count 2 2006.285.21:17:15.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:17:15.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:17:15.81#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.21:17:15.81#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:15.81#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:17:15.92#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:17:15.92#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:17:15.92#ibcon#enter wrdev, iclass 33, count 0 2006.285.21:17:15.92#ibcon#first serial, iclass 33, count 0 2006.285.21:17:15.92#ibcon#enter sib2, iclass 33, count 0 2006.285.21:17:15.92#ibcon#flushed, iclass 33, count 0 2006.285.21:17:15.92#ibcon#about to write, iclass 33, count 0 2006.285.21:17:15.92#ibcon#wrote, iclass 33, count 0 2006.285.21:17:15.92#ibcon#about to read 3, iclass 33, count 0 2006.285.21:17:15.94#ibcon#read 3, iclass 33, count 0 2006.285.21:17:15.94#ibcon#about to read 4, iclass 33, count 0 2006.285.21:17:15.94#ibcon#read 4, iclass 33, count 0 2006.285.21:17:15.94#ibcon#about to read 5, iclass 33, count 0 2006.285.21:17:15.94#ibcon#read 5, iclass 33, count 0 2006.285.21:17:15.94#ibcon#about to read 6, iclass 33, count 0 2006.285.21:17:15.94#ibcon#read 6, iclass 33, count 0 2006.285.21:17:15.94#ibcon#end of sib2, iclass 33, count 0 2006.285.21:17:15.94#ibcon#*mode == 0, iclass 33, count 0 2006.285.21:17:15.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.21:17:15.94#ibcon#[27=USB\r\n] 2006.285.21:17:15.94#ibcon#*before write, iclass 33, count 0 2006.285.21:17:15.95#ibcon#enter sib2, iclass 33, count 0 2006.285.21:17:15.95#ibcon#flushed, iclass 33, count 0 2006.285.21:17:15.95#ibcon#about to write, iclass 33, count 0 2006.285.21:17:15.95#ibcon#wrote, iclass 33, count 0 2006.285.21:17:15.95#ibcon#about to read 3, iclass 33, count 0 2006.285.21:17:15.97#ibcon#read 3, iclass 33, count 0 2006.285.21:17:15.97#ibcon#about to read 4, iclass 33, count 0 2006.285.21:17:15.97#ibcon#read 4, iclass 33, count 0 2006.285.21:17:15.97#ibcon#about to read 5, iclass 33, count 0 2006.285.21:17:15.97#ibcon#read 5, iclass 33, count 0 2006.285.21:17:15.97#ibcon#about to read 6, iclass 33, count 0 2006.285.21:17:15.97#ibcon#read 6, iclass 33, count 0 2006.285.21:17:15.98#ibcon#end of sib2, iclass 33, count 0 2006.285.21:17:15.98#ibcon#*after write, iclass 33, count 0 2006.285.21:17:15.98#ibcon#*before return 0, iclass 33, count 0 2006.285.21:17:15.98#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:17:15.98#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:17:15.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.21:17:15.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.21:17:15.98$vck44/vblo=5,709.99 2006.285.21:17:15.98#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.21:17:15.98#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.21:17:15.98#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:15.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:17:15.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:17:15.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:17:15.98#ibcon#enter wrdev, iclass 35, count 0 2006.285.21:17:15.98#ibcon#first serial, iclass 35, count 0 2006.285.21:17:15.98#ibcon#enter sib2, iclass 35, count 0 2006.285.21:17:15.98#ibcon#flushed, iclass 35, count 0 2006.285.21:17:15.98#ibcon#about to write, iclass 35, count 0 2006.285.21:17:15.98#ibcon#wrote, iclass 35, count 0 2006.285.21:17:15.98#ibcon#about to read 3, iclass 35, count 0 2006.285.21:17:15.99#ibcon#read 3, iclass 35, count 0 2006.285.21:17:15.99#ibcon#about to read 4, iclass 35, count 0 2006.285.21:17:15.99#ibcon#read 4, iclass 35, count 0 2006.285.21:17:15.99#ibcon#about to read 5, iclass 35, count 0 2006.285.21:17:15.99#ibcon#read 5, iclass 35, count 0 2006.285.21:17:15.99#ibcon#about to read 6, iclass 35, count 0 2006.285.21:17:15.99#ibcon#read 6, iclass 35, count 0 2006.285.21:17:15.99#ibcon#end of sib2, iclass 35, count 0 2006.285.21:17:15.99#ibcon#*mode == 0, iclass 35, count 0 2006.285.21:17:15.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.21:17:16.00#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:17:16.00#ibcon#*before write, iclass 35, count 0 2006.285.21:17:16.00#ibcon#enter sib2, iclass 35, count 0 2006.285.21:17:16.00#ibcon#flushed, iclass 35, count 0 2006.285.21:17:16.00#ibcon#about to write, iclass 35, count 0 2006.285.21:17:16.00#ibcon#wrote, iclass 35, count 0 2006.285.21:17:16.00#ibcon#about to read 3, iclass 35, count 0 2006.285.21:17:16.03#ibcon#read 3, iclass 35, count 0 2006.285.21:17:16.03#ibcon#about to read 4, iclass 35, count 0 2006.285.21:17:16.03#ibcon#read 4, iclass 35, count 0 2006.285.21:17:16.03#ibcon#about to read 5, iclass 35, count 0 2006.285.21:17:16.03#ibcon#read 5, iclass 35, count 0 2006.285.21:17:16.03#ibcon#about to read 6, iclass 35, count 0 2006.285.21:17:16.03#ibcon#read 6, iclass 35, count 0 2006.285.21:17:16.03#ibcon#end of sib2, iclass 35, count 0 2006.285.21:17:16.04#ibcon#*after write, iclass 35, count 0 2006.285.21:17:16.04#ibcon#*before return 0, iclass 35, count 0 2006.285.21:17:16.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:17:16.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:17:16.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.21:17:16.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.21:17:16.04$vck44/vb=5,4 2006.285.21:17:16.04#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.21:17:16.04#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.21:17:16.04#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:16.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:17:16.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:17:16.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:17:16.09#ibcon#enter wrdev, iclass 37, count 2 2006.285.21:17:16.09#ibcon#first serial, iclass 37, count 2 2006.285.21:17:16.09#ibcon#enter sib2, iclass 37, count 2 2006.285.21:17:16.09#ibcon#flushed, iclass 37, count 2 2006.285.21:17:16.09#ibcon#about to write, iclass 37, count 2 2006.285.21:17:16.09#ibcon#wrote, iclass 37, count 2 2006.285.21:17:16.10#ibcon#about to read 3, iclass 37, count 2 2006.285.21:17:16.11#ibcon#read 3, iclass 37, count 2 2006.285.21:17:16.11#ibcon#about to read 4, iclass 37, count 2 2006.285.21:17:16.11#ibcon#read 4, iclass 37, count 2 2006.285.21:17:16.11#ibcon#about to read 5, iclass 37, count 2 2006.285.21:17:16.11#ibcon#read 5, iclass 37, count 2 2006.285.21:17:16.11#ibcon#about to read 6, iclass 37, count 2 2006.285.21:17:16.11#ibcon#read 6, iclass 37, count 2 2006.285.21:17:16.11#ibcon#end of sib2, iclass 37, count 2 2006.285.21:17:16.11#ibcon#*mode == 0, iclass 37, count 2 2006.285.21:17:16.11#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.21:17:16.11#ibcon#[27=AT05-04\r\n] 2006.285.21:17:16.12#ibcon#*before write, iclass 37, count 2 2006.285.21:17:16.12#ibcon#enter sib2, iclass 37, count 2 2006.285.21:17:16.12#ibcon#flushed, iclass 37, count 2 2006.285.21:17:16.12#ibcon#about to write, iclass 37, count 2 2006.285.21:17:16.12#ibcon#wrote, iclass 37, count 2 2006.285.21:17:16.12#ibcon#about to read 3, iclass 37, count 2 2006.285.21:17:16.14#ibcon#read 3, iclass 37, count 2 2006.285.21:17:16.14#ibcon#about to read 4, iclass 37, count 2 2006.285.21:17:16.14#ibcon#read 4, iclass 37, count 2 2006.285.21:17:16.14#ibcon#about to read 5, iclass 37, count 2 2006.285.21:17:16.14#ibcon#read 5, iclass 37, count 2 2006.285.21:17:16.14#ibcon#about to read 6, iclass 37, count 2 2006.285.21:17:16.14#ibcon#read 6, iclass 37, count 2 2006.285.21:17:16.14#ibcon#end of sib2, iclass 37, count 2 2006.285.21:17:16.14#ibcon#*after write, iclass 37, count 2 2006.285.21:17:16.14#ibcon#*before return 0, iclass 37, count 2 2006.285.21:17:16.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:17:16.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:17:16.15#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.21:17:16.15#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:16.15#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:17:16.26#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:17:16.26#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:17:16.26#ibcon#enter wrdev, iclass 37, count 0 2006.285.21:17:16.26#ibcon#first serial, iclass 37, count 0 2006.285.21:17:16.26#ibcon#enter sib2, iclass 37, count 0 2006.285.21:17:16.26#ibcon#flushed, iclass 37, count 0 2006.285.21:17:16.26#ibcon#about to write, iclass 37, count 0 2006.285.21:17:16.26#ibcon#wrote, iclass 37, count 0 2006.285.21:17:16.27#ibcon#about to read 3, iclass 37, count 0 2006.285.21:17:16.28#ibcon#read 3, iclass 37, count 0 2006.285.21:17:16.28#ibcon#about to read 4, iclass 37, count 0 2006.285.21:17:16.28#ibcon#read 4, iclass 37, count 0 2006.285.21:17:16.28#ibcon#about to read 5, iclass 37, count 0 2006.285.21:17:16.28#ibcon#read 5, iclass 37, count 0 2006.285.21:17:16.28#ibcon#about to read 6, iclass 37, count 0 2006.285.21:17:16.28#ibcon#read 6, iclass 37, count 0 2006.285.21:17:16.28#ibcon#end of sib2, iclass 37, count 0 2006.285.21:17:16.28#ibcon#*mode == 0, iclass 37, count 0 2006.285.21:17:16.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.21:17:16.29#ibcon#[27=USB\r\n] 2006.285.21:17:16.29#ibcon#*before write, iclass 37, count 0 2006.285.21:17:16.29#ibcon#enter sib2, iclass 37, count 0 2006.285.21:17:16.29#ibcon#flushed, iclass 37, count 0 2006.285.21:17:16.29#ibcon#about to write, iclass 37, count 0 2006.285.21:17:16.29#ibcon#wrote, iclass 37, count 0 2006.285.21:17:16.29#ibcon#about to read 3, iclass 37, count 0 2006.285.21:17:16.31#ibcon#read 3, iclass 37, count 0 2006.285.21:17:16.31#ibcon#about to read 4, iclass 37, count 0 2006.285.21:17:16.31#ibcon#read 4, iclass 37, count 0 2006.285.21:17:16.31#ibcon#about to read 5, iclass 37, count 0 2006.285.21:17:16.31#ibcon#read 5, iclass 37, count 0 2006.285.21:17:16.31#ibcon#about to read 6, iclass 37, count 0 2006.285.21:17:16.31#ibcon#read 6, iclass 37, count 0 2006.285.21:17:16.31#ibcon#end of sib2, iclass 37, count 0 2006.285.21:17:16.31#ibcon#*after write, iclass 37, count 0 2006.285.21:17:16.32#ibcon#*before return 0, iclass 37, count 0 2006.285.21:17:16.32#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:17:16.32#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:17:16.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.21:17:16.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.21:17:16.32$vck44/vblo=6,719.99 2006.285.21:17:16.32#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.21:17:16.32#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.21:17:16.32#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:16.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:17:16.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:17:16.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:17:16.32#ibcon#enter wrdev, iclass 39, count 0 2006.285.21:17:16.32#ibcon#first serial, iclass 39, count 0 2006.285.21:17:16.32#ibcon#enter sib2, iclass 39, count 0 2006.285.21:17:16.32#ibcon#flushed, iclass 39, count 0 2006.285.21:17:16.32#ibcon#about to write, iclass 39, count 0 2006.285.21:17:16.32#ibcon#wrote, iclass 39, count 0 2006.285.21:17:16.32#ibcon#about to read 3, iclass 39, count 0 2006.285.21:17:16.33#ibcon#read 3, iclass 39, count 0 2006.285.21:17:16.33#ibcon#about to read 4, iclass 39, count 0 2006.285.21:17:16.33#ibcon#read 4, iclass 39, count 0 2006.285.21:17:16.33#ibcon#about to read 5, iclass 39, count 0 2006.285.21:17:16.33#ibcon#read 5, iclass 39, count 0 2006.285.21:17:16.33#ibcon#about to read 6, iclass 39, count 0 2006.285.21:17:16.33#ibcon#read 6, iclass 39, count 0 2006.285.21:17:16.33#ibcon#end of sib2, iclass 39, count 0 2006.285.21:17:16.34#ibcon#*mode == 0, iclass 39, count 0 2006.285.21:17:16.34#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.21:17:16.34#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:17:16.34#ibcon#*before write, iclass 39, count 0 2006.285.21:17:16.34#ibcon#enter sib2, iclass 39, count 0 2006.285.21:17:16.34#ibcon#flushed, iclass 39, count 0 2006.285.21:17:16.34#ibcon#about to write, iclass 39, count 0 2006.285.21:17:16.34#ibcon#wrote, iclass 39, count 0 2006.285.21:17:16.34#ibcon#about to read 3, iclass 39, count 0 2006.285.21:17:16.37#ibcon#read 3, iclass 39, count 0 2006.285.21:17:16.37#ibcon#about to read 4, iclass 39, count 0 2006.285.21:17:16.37#ibcon#read 4, iclass 39, count 0 2006.285.21:17:16.37#ibcon#about to read 5, iclass 39, count 0 2006.285.21:17:16.37#ibcon#read 5, iclass 39, count 0 2006.285.21:17:16.37#ibcon#about to read 6, iclass 39, count 0 2006.285.21:17:16.37#ibcon#read 6, iclass 39, count 0 2006.285.21:17:16.37#ibcon#end of sib2, iclass 39, count 0 2006.285.21:17:16.37#ibcon#*after write, iclass 39, count 0 2006.285.21:17:16.38#ibcon#*before return 0, iclass 39, count 0 2006.285.21:17:16.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:17:16.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:17:16.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.21:17:16.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.21:17:16.38$vck44/vb=6,3 2006.285.21:17:16.38#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.21:17:16.38#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.21:17:16.38#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:16.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:17:16.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:17:16.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:17:16.43#ibcon#enter wrdev, iclass 3, count 2 2006.285.21:17:16.43#ibcon#first serial, iclass 3, count 2 2006.285.21:17:16.43#ibcon#enter sib2, iclass 3, count 2 2006.285.21:17:16.43#ibcon#flushed, iclass 3, count 2 2006.285.21:17:16.43#ibcon#about to write, iclass 3, count 2 2006.285.21:17:16.43#ibcon#wrote, iclass 3, count 2 2006.285.21:17:16.43#ibcon#about to read 3, iclass 3, count 2 2006.285.21:17:16.45#ibcon#read 3, iclass 3, count 2 2006.285.21:17:16.45#ibcon#about to read 4, iclass 3, count 2 2006.285.21:17:16.45#ibcon#read 4, iclass 3, count 2 2006.285.21:17:16.45#ibcon#about to read 5, iclass 3, count 2 2006.285.21:17:16.45#ibcon#read 5, iclass 3, count 2 2006.285.21:17:16.45#ibcon#about to read 6, iclass 3, count 2 2006.285.21:17:16.45#ibcon#read 6, iclass 3, count 2 2006.285.21:17:16.45#ibcon#end of sib2, iclass 3, count 2 2006.285.21:17:16.45#ibcon#*mode == 0, iclass 3, count 2 2006.285.21:17:16.45#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.21:17:16.45#ibcon#[27=AT06-03\r\n] 2006.285.21:17:16.46#ibcon#*before write, iclass 3, count 2 2006.285.21:17:16.46#ibcon#enter sib2, iclass 3, count 2 2006.285.21:17:16.46#ibcon#flushed, iclass 3, count 2 2006.285.21:17:16.46#ibcon#about to write, iclass 3, count 2 2006.285.21:17:16.46#ibcon#wrote, iclass 3, count 2 2006.285.21:17:16.46#ibcon#about to read 3, iclass 3, count 2 2006.285.21:17:16.48#ibcon#read 3, iclass 3, count 2 2006.285.21:17:16.48#ibcon#about to read 4, iclass 3, count 2 2006.285.21:17:16.48#ibcon#read 4, iclass 3, count 2 2006.285.21:17:16.48#ibcon#about to read 5, iclass 3, count 2 2006.285.21:17:16.48#ibcon#read 5, iclass 3, count 2 2006.285.21:17:16.48#ibcon#about to read 6, iclass 3, count 2 2006.285.21:17:16.48#ibcon#read 6, iclass 3, count 2 2006.285.21:17:16.48#ibcon#end of sib2, iclass 3, count 2 2006.285.21:17:16.48#ibcon#*after write, iclass 3, count 2 2006.285.21:17:16.48#ibcon#*before return 0, iclass 3, count 2 2006.285.21:17:16.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:17:16.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:17:16.49#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.21:17:16.49#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:16.49#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:17:16.60#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:17:16.60#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:17:16.60#ibcon#enter wrdev, iclass 3, count 0 2006.285.21:17:16.60#ibcon#first serial, iclass 3, count 0 2006.285.21:17:16.60#ibcon#enter sib2, iclass 3, count 0 2006.285.21:17:16.60#ibcon#flushed, iclass 3, count 0 2006.285.21:17:16.60#ibcon#about to write, iclass 3, count 0 2006.285.21:17:16.60#ibcon#wrote, iclass 3, count 0 2006.285.21:17:16.60#ibcon#about to read 3, iclass 3, count 0 2006.285.21:17:16.62#ibcon#read 3, iclass 3, count 0 2006.285.21:17:16.62#ibcon#about to read 4, iclass 3, count 0 2006.285.21:17:16.62#ibcon#read 4, iclass 3, count 0 2006.285.21:17:16.62#ibcon#about to read 5, iclass 3, count 0 2006.285.21:17:16.62#ibcon#read 5, iclass 3, count 0 2006.285.21:17:16.62#ibcon#about to read 6, iclass 3, count 0 2006.285.21:17:16.62#ibcon#read 6, iclass 3, count 0 2006.285.21:17:16.62#ibcon#end of sib2, iclass 3, count 0 2006.285.21:17:16.62#ibcon#*mode == 0, iclass 3, count 0 2006.285.21:17:16.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.21:17:16.62#ibcon#[27=USB\r\n] 2006.285.21:17:16.62#ibcon#*before write, iclass 3, count 0 2006.285.21:17:16.63#ibcon#enter sib2, iclass 3, count 0 2006.285.21:17:16.63#ibcon#flushed, iclass 3, count 0 2006.285.21:17:16.63#ibcon#about to write, iclass 3, count 0 2006.285.21:17:16.63#ibcon#wrote, iclass 3, count 0 2006.285.21:17:16.63#ibcon#about to read 3, iclass 3, count 0 2006.285.21:17:16.65#ibcon#read 3, iclass 3, count 0 2006.285.21:17:16.65#ibcon#about to read 4, iclass 3, count 0 2006.285.21:17:16.65#ibcon#read 4, iclass 3, count 0 2006.285.21:17:16.65#ibcon#about to read 5, iclass 3, count 0 2006.285.21:17:16.65#ibcon#read 5, iclass 3, count 0 2006.285.21:17:16.65#ibcon#about to read 6, iclass 3, count 0 2006.285.21:17:16.65#ibcon#read 6, iclass 3, count 0 2006.285.21:17:16.65#ibcon#end of sib2, iclass 3, count 0 2006.285.21:17:16.65#ibcon#*after write, iclass 3, count 0 2006.285.21:17:16.65#ibcon#*before return 0, iclass 3, count 0 2006.285.21:17:16.65#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:17:16.66#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:17:16.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.21:17:16.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.21:17:16.66$vck44/vblo=7,734.99 2006.285.21:17:16.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.21:17:16.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.21:17:16.66#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:16.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:17:16.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:17:16.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:17:16.66#ibcon#enter wrdev, iclass 5, count 0 2006.285.21:17:16.66#ibcon#first serial, iclass 5, count 0 2006.285.21:17:16.66#ibcon#enter sib2, iclass 5, count 0 2006.285.21:17:16.66#ibcon#flushed, iclass 5, count 0 2006.285.21:17:16.66#ibcon#about to write, iclass 5, count 0 2006.285.21:17:16.66#ibcon#wrote, iclass 5, count 0 2006.285.21:17:16.66#ibcon#about to read 3, iclass 5, count 0 2006.285.21:17:16.67#ibcon#read 3, iclass 5, count 0 2006.285.21:17:16.67#ibcon#about to read 4, iclass 5, count 0 2006.285.21:17:16.67#ibcon#read 4, iclass 5, count 0 2006.285.21:17:16.67#ibcon#about to read 5, iclass 5, count 0 2006.285.21:17:16.67#ibcon#read 5, iclass 5, count 0 2006.285.21:17:16.67#ibcon#about to read 6, iclass 5, count 0 2006.285.21:17:16.67#ibcon#read 6, iclass 5, count 0 2006.285.21:17:16.67#ibcon#end of sib2, iclass 5, count 0 2006.285.21:17:16.67#ibcon#*mode == 0, iclass 5, count 0 2006.285.21:17:16.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.21:17:16.68#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:17:16.68#ibcon#*before write, iclass 5, count 0 2006.285.21:17:16.68#ibcon#enter sib2, iclass 5, count 0 2006.285.21:17:16.68#ibcon#flushed, iclass 5, count 0 2006.285.21:17:16.68#ibcon#about to write, iclass 5, count 0 2006.285.21:17:16.68#ibcon#wrote, iclass 5, count 0 2006.285.21:17:16.68#ibcon#about to read 3, iclass 5, count 0 2006.285.21:17:16.71#ibcon#read 3, iclass 5, count 0 2006.285.21:17:16.71#ibcon#about to read 4, iclass 5, count 0 2006.285.21:17:16.71#ibcon#read 4, iclass 5, count 0 2006.285.21:17:16.71#ibcon#about to read 5, iclass 5, count 0 2006.285.21:17:16.71#ibcon#read 5, iclass 5, count 0 2006.285.21:17:16.71#ibcon#about to read 6, iclass 5, count 0 2006.285.21:17:16.71#ibcon#read 6, iclass 5, count 0 2006.285.21:17:16.71#ibcon#end of sib2, iclass 5, count 0 2006.285.21:17:16.71#ibcon#*after write, iclass 5, count 0 2006.285.21:17:16.71#ibcon#*before return 0, iclass 5, count 0 2006.285.21:17:16.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:17:16.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:17:16.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.21:17:16.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.21:17:16.72$vck44/vb=7,4 2006.285.21:17:16.72#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.21:17:16.72#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.21:17:16.72#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:16.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:17:16.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:17:16.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:17:16.77#ibcon#enter wrdev, iclass 7, count 2 2006.285.21:17:16.77#ibcon#first serial, iclass 7, count 2 2006.285.21:17:16.77#ibcon#enter sib2, iclass 7, count 2 2006.285.21:17:16.77#ibcon#flushed, iclass 7, count 2 2006.285.21:17:16.77#ibcon#about to write, iclass 7, count 2 2006.285.21:17:16.78#ibcon#wrote, iclass 7, count 2 2006.285.21:17:16.78#ibcon#about to read 3, iclass 7, count 2 2006.285.21:17:16.79#ibcon#read 3, iclass 7, count 2 2006.285.21:17:16.79#ibcon#about to read 4, iclass 7, count 2 2006.285.21:17:16.79#ibcon#read 4, iclass 7, count 2 2006.285.21:17:16.79#ibcon#about to read 5, iclass 7, count 2 2006.285.21:17:16.79#ibcon#read 5, iclass 7, count 2 2006.285.21:17:16.79#ibcon#about to read 6, iclass 7, count 2 2006.285.21:17:16.79#ibcon#read 6, iclass 7, count 2 2006.285.21:17:16.79#ibcon#end of sib2, iclass 7, count 2 2006.285.21:17:16.79#ibcon#*mode == 0, iclass 7, count 2 2006.285.21:17:16.79#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.21:17:16.79#ibcon#[27=AT07-04\r\n] 2006.285.21:17:16.80#ibcon#*before write, iclass 7, count 2 2006.285.21:17:16.80#ibcon#enter sib2, iclass 7, count 2 2006.285.21:17:16.80#ibcon#flushed, iclass 7, count 2 2006.285.21:17:16.80#ibcon#about to write, iclass 7, count 2 2006.285.21:17:16.80#ibcon#wrote, iclass 7, count 2 2006.285.21:17:16.80#ibcon#about to read 3, iclass 7, count 2 2006.285.21:17:16.82#ibcon#read 3, iclass 7, count 2 2006.285.21:17:16.82#ibcon#about to read 4, iclass 7, count 2 2006.285.21:17:16.82#ibcon#read 4, iclass 7, count 2 2006.285.21:17:16.82#ibcon#about to read 5, iclass 7, count 2 2006.285.21:17:16.82#ibcon#read 5, iclass 7, count 2 2006.285.21:17:16.82#ibcon#about to read 6, iclass 7, count 2 2006.285.21:17:16.82#ibcon#read 6, iclass 7, count 2 2006.285.21:17:16.82#ibcon#end of sib2, iclass 7, count 2 2006.285.21:17:16.82#ibcon#*after write, iclass 7, count 2 2006.285.21:17:16.82#ibcon#*before return 0, iclass 7, count 2 2006.285.21:17:16.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:17:16.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:17:16.83#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.21:17:16.83#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:16.83#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:17:16.94#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:17:16.94#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:17:16.94#ibcon#enter wrdev, iclass 7, count 0 2006.285.21:17:16.94#ibcon#first serial, iclass 7, count 0 2006.285.21:17:16.94#ibcon#enter sib2, iclass 7, count 0 2006.285.21:17:16.94#ibcon#flushed, iclass 7, count 0 2006.285.21:17:16.94#ibcon#about to write, iclass 7, count 0 2006.285.21:17:16.94#ibcon#wrote, iclass 7, count 0 2006.285.21:17:16.94#ibcon#about to read 3, iclass 7, count 0 2006.285.21:17:16.96#ibcon#read 3, iclass 7, count 0 2006.285.21:17:16.96#ibcon#about to read 4, iclass 7, count 0 2006.285.21:17:16.96#ibcon#read 4, iclass 7, count 0 2006.285.21:17:16.96#ibcon#about to read 5, iclass 7, count 0 2006.285.21:17:16.96#ibcon#read 5, iclass 7, count 0 2006.285.21:17:16.96#ibcon#about to read 6, iclass 7, count 0 2006.285.21:17:16.96#ibcon#read 6, iclass 7, count 0 2006.285.21:17:16.96#ibcon#end of sib2, iclass 7, count 0 2006.285.21:17:16.96#ibcon#*mode == 0, iclass 7, count 0 2006.285.21:17:16.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.21:17:16.96#ibcon#[27=USB\r\n] 2006.285.21:17:16.97#ibcon#*before write, iclass 7, count 0 2006.285.21:17:16.97#ibcon#enter sib2, iclass 7, count 0 2006.285.21:17:16.97#ibcon#flushed, iclass 7, count 0 2006.285.21:17:16.97#ibcon#about to write, iclass 7, count 0 2006.285.21:17:16.97#ibcon#wrote, iclass 7, count 0 2006.285.21:17:16.97#ibcon#about to read 3, iclass 7, count 0 2006.285.21:17:16.99#ibcon#read 3, iclass 7, count 0 2006.285.21:17:16.99#ibcon#about to read 4, iclass 7, count 0 2006.285.21:17:16.99#ibcon#read 4, iclass 7, count 0 2006.285.21:17:16.99#ibcon#about to read 5, iclass 7, count 0 2006.285.21:17:16.99#ibcon#read 5, iclass 7, count 0 2006.285.21:17:16.99#ibcon#about to read 6, iclass 7, count 0 2006.285.21:17:16.99#ibcon#read 6, iclass 7, count 0 2006.285.21:17:17.00#ibcon#end of sib2, iclass 7, count 0 2006.285.21:17:17.00#ibcon#*after write, iclass 7, count 0 2006.285.21:17:17.00#ibcon#*before return 0, iclass 7, count 0 2006.285.21:17:17.00#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:17:17.00#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:17:17.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.21:17:17.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.21:17:17.00$vck44/vblo=8,744.99 2006.285.21:17:17.00#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.21:17:17.00#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.21:17:17.00#ibcon#ireg 17 cls_cnt 0 2006.285.21:17:17.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:17:17.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:17:17.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:17:17.00#ibcon#enter wrdev, iclass 11, count 0 2006.285.21:17:17.00#ibcon#first serial, iclass 11, count 0 2006.285.21:17:17.00#ibcon#enter sib2, iclass 11, count 0 2006.285.21:17:17.00#ibcon#flushed, iclass 11, count 0 2006.285.21:17:17.00#ibcon#about to write, iclass 11, count 0 2006.285.21:17:17.00#ibcon#wrote, iclass 11, count 0 2006.285.21:17:17.00#ibcon#about to read 3, iclass 11, count 0 2006.285.21:17:17.01#ibcon#read 3, iclass 11, count 0 2006.285.21:17:17.01#ibcon#about to read 4, iclass 11, count 0 2006.285.21:17:17.01#ibcon#read 4, iclass 11, count 0 2006.285.21:17:17.01#ibcon#about to read 5, iclass 11, count 0 2006.285.21:17:17.01#ibcon#read 5, iclass 11, count 0 2006.285.21:17:17.01#ibcon#about to read 6, iclass 11, count 0 2006.285.21:17:17.01#ibcon#read 6, iclass 11, count 0 2006.285.21:17:17.01#ibcon#end of sib2, iclass 11, count 0 2006.285.21:17:17.01#ibcon#*mode == 0, iclass 11, count 0 2006.285.21:17:17.01#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.21:17:17.02#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:17:17.02#ibcon#*before write, iclass 11, count 0 2006.285.21:17:17.02#ibcon#enter sib2, iclass 11, count 0 2006.285.21:17:17.02#ibcon#flushed, iclass 11, count 0 2006.285.21:17:17.02#ibcon#about to write, iclass 11, count 0 2006.285.21:17:17.02#ibcon#wrote, iclass 11, count 0 2006.285.21:17:17.02#ibcon#about to read 3, iclass 11, count 0 2006.285.21:17:17.05#ibcon#read 3, iclass 11, count 0 2006.285.21:17:17.05#ibcon#about to read 4, iclass 11, count 0 2006.285.21:17:17.05#ibcon#read 4, iclass 11, count 0 2006.285.21:17:17.05#ibcon#about to read 5, iclass 11, count 0 2006.285.21:17:17.05#ibcon#read 5, iclass 11, count 0 2006.285.21:17:17.06#ibcon#about to read 6, iclass 11, count 0 2006.285.21:17:17.06#ibcon#read 6, iclass 11, count 0 2006.285.21:17:17.06#ibcon#end of sib2, iclass 11, count 0 2006.285.21:17:17.06#ibcon#*after write, iclass 11, count 0 2006.285.21:17:17.06#ibcon#*before return 0, iclass 11, count 0 2006.285.21:17:17.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:17:17.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:17:17.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.21:17:17.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.21:17:17.06$vck44/vb=8,4 2006.285.21:17:17.06#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.21:17:17.06#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.21:17:17.06#ibcon#ireg 11 cls_cnt 2 2006.285.21:17:17.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:17:17.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:17:17.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:17:17.11#ibcon#enter wrdev, iclass 13, count 2 2006.285.21:17:17.11#ibcon#first serial, iclass 13, count 2 2006.285.21:17:17.11#ibcon#enter sib2, iclass 13, count 2 2006.285.21:17:17.11#ibcon#flushed, iclass 13, count 2 2006.285.21:17:17.11#ibcon#about to write, iclass 13, count 2 2006.285.21:17:17.12#ibcon#wrote, iclass 13, count 2 2006.285.21:17:17.12#ibcon#about to read 3, iclass 13, count 2 2006.285.21:17:17.13#ibcon#read 3, iclass 13, count 2 2006.285.21:17:17.30#ibcon#about to read 4, iclass 13, count 2 2006.285.21:17:17.30#ibcon#read 4, iclass 13, count 2 2006.285.21:17:17.30#ibcon#about to read 5, iclass 13, count 2 2006.285.21:17:17.30#ibcon#read 5, iclass 13, count 2 2006.285.21:17:17.30#ibcon#about to read 6, iclass 13, count 2 2006.285.21:17:17.30#ibcon#read 6, iclass 13, count 2 2006.285.21:17:17.30#ibcon#end of sib2, iclass 13, count 2 2006.285.21:17:17.30#ibcon#*mode == 0, iclass 13, count 2 2006.285.21:17:17.30#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.21:17:17.30#ibcon#[27=AT08-04\r\n] 2006.285.21:17:17.30#ibcon#*before write, iclass 13, count 2 2006.285.21:17:17.30#ibcon#enter sib2, iclass 13, count 2 2006.285.21:17:17.30#ibcon#flushed, iclass 13, count 2 2006.285.21:17:17.30#ibcon#about to write, iclass 13, count 2 2006.285.21:17:17.30#ibcon#wrote, iclass 13, count 2 2006.285.21:17:17.30#ibcon#about to read 3, iclass 13, count 2 2006.285.21:17:17.32#ibcon#read 3, iclass 13, count 2 2006.285.21:17:17.32#ibcon#about to read 4, iclass 13, count 2 2006.285.21:17:17.32#ibcon#read 4, iclass 13, count 2 2006.285.21:17:17.32#ibcon#about to read 5, iclass 13, count 2 2006.285.21:17:17.32#ibcon#read 5, iclass 13, count 2 2006.285.21:17:17.32#ibcon#about to read 6, iclass 13, count 2 2006.285.21:17:17.32#ibcon#read 6, iclass 13, count 2 2006.285.21:17:17.32#ibcon#end of sib2, iclass 13, count 2 2006.285.21:17:17.33#ibcon#*after write, iclass 13, count 2 2006.285.21:17:17.33#ibcon#*before return 0, iclass 13, count 2 2006.285.21:17:17.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:17:17.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:17:17.33#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.21:17:17.33#ibcon#ireg 7 cls_cnt 0 2006.285.21:17:17.33#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:17:17.44#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:17:17.44#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:17:17.44#ibcon#enter wrdev, iclass 13, count 0 2006.285.21:17:17.44#ibcon#first serial, iclass 13, count 0 2006.285.21:17:17.44#ibcon#enter sib2, iclass 13, count 0 2006.285.21:17:17.44#ibcon#flushed, iclass 13, count 0 2006.285.21:17:17.44#ibcon#about to write, iclass 13, count 0 2006.285.21:17:17.44#ibcon#wrote, iclass 13, count 0 2006.285.21:17:17.45#ibcon#about to read 3, iclass 13, count 0 2006.285.21:17:17.46#ibcon#read 3, iclass 13, count 0 2006.285.21:17:17.46#ibcon#about to read 4, iclass 13, count 0 2006.285.21:17:17.46#ibcon#read 4, iclass 13, count 0 2006.285.21:17:17.46#ibcon#about to read 5, iclass 13, count 0 2006.285.21:17:17.46#ibcon#read 5, iclass 13, count 0 2006.285.21:17:17.46#ibcon#about to read 6, iclass 13, count 0 2006.285.21:17:17.46#ibcon#read 6, iclass 13, count 0 2006.285.21:17:17.46#ibcon#end of sib2, iclass 13, count 0 2006.285.21:17:17.46#ibcon#*mode == 0, iclass 13, count 0 2006.285.21:17:17.47#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.21:17:17.47#ibcon#[27=USB\r\n] 2006.285.21:17:17.47#ibcon#*before write, iclass 13, count 0 2006.285.21:17:17.47#ibcon#enter sib2, iclass 13, count 0 2006.285.21:17:17.47#ibcon#flushed, iclass 13, count 0 2006.285.21:17:17.47#ibcon#about to write, iclass 13, count 0 2006.285.21:17:17.47#ibcon#wrote, iclass 13, count 0 2006.285.21:17:17.47#ibcon#about to read 3, iclass 13, count 0 2006.285.21:17:17.49#ibcon#read 3, iclass 13, count 0 2006.285.21:17:17.49#ibcon#about to read 4, iclass 13, count 0 2006.285.21:17:17.49#ibcon#read 4, iclass 13, count 0 2006.285.21:17:17.49#ibcon#about to read 5, iclass 13, count 0 2006.285.21:17:17.49#ibcon#read 5, iclass 13, count 0 2006.285.21:17:17.49#ibcon#about to read 6, iclass 13, count 0 2006.285.21:17:17.49#ibcon#read 6, iclass 13, count 0 2006.285.21:17:17.49#ibcon#end of sib2, iclass 13, count 0 2006.285.21:17:17.49#ibcon#*after write, iclass 13, count 0 2006.285.21:17:17.50#ibcon#*before return 0, iclass 13, count 0 2006.285.21:17:17.50#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:17:17.50#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:17:17.50#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.21:17:17.50#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.21:17:17.50$vck44/vabw=wide 2006.285.21:17:17.50#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.21:17:17.50#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.21:17:17.50#ibcon#ireg 8 cls_cnt 0 2006.285.21:17:17.50#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:17:17.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:17:17.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:17:17.50#ibcon#enter wrdev, iclass 15, count 0 2006.285.21:17:17.50#ibcon#first serial, iclass 15, count 0 2006.285.21:17:17.50#ibcon#enter sib2, iclass 15, count 0 2006.285.21:17:17.50#ibcon#flushed, iclass 15, count 0 2006.285.21:17:17.50#ibcon#about to write, iclass 15, count 0 2006.285.21:17:17.50#ibcon#wrote, iclass 15, count 0 2006.285.21:17:17.50#ibcon#about to read 3, iclass 15, count 0 2006.285.21:17:17.51#ibcon#read 3, iclass 15, count 0 2006.285.21:17:17.51#ibcon#about to read 4, iclass 15, count 0 2006.285.21:17:17.51#ibcon#read 4, iclass 15, count 0 2006.285.21:17:17.51#ibcon#about to read 5, iclass 15, count 0 2006.285.21:17:17.51#ibcon#read 5, iclass 15, count 0 2006.285.21:17:17.51#ibcon#about to read 6, iclass 15, count 0 2006.285.21:17:17.51#ibcon#read 6, iclass 15, count 0 2006.285.21:17:17.51#ibcon#end of sib2, iclass 15, count 0 2006.285.21:17:17.51#ibcon#*mode == 0, iclass 15, count 0 2006.285.21:17:17.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.21:17:17.52#ibcon#[25=BW32\r\n] 2006.285.21:17:17.52#ibcon#*before write, iclass 15, count 0 2006.285.21:17:17.52#ibcon#enter sib2, iclass 15, count 0 2006.285.21:17:17.52#ibcon#flushed, iclass 15, count 0 2006.285.21:17:17.52#ibcon#about to write, iclass 15, count 0 2006.285.21:17:17.52#ibcon#wrote, iclass 15, count 0 2006.285.21:17:17.52#ibcon#about to read 3, iclass 15, count 0 2006.285.21:17:17.54#ibcon#read 3, iclass 15, count 0 2006.285.21:17:17.54#ibcon#about to read 4, iclass 15, count 0 2006.285.21:17:17.54#ibcon#read 4, iclass 15, count 0 2006.285.21:17:17.54#ibcon#about to read 5, iclass 15, count 0 2006.285.21:17:17.54#ibcon#read 5, iclass 15, count 0 2006.285.21:17:17.54#ibcon#about to read 6, iclass 15, count 0 2006.285.21:17:17.54#ibcon#read 6, iclass 15, count 0 2006.285.21:17:17.54#ibcon#end of sib2, iclass 15, count 0 2006.285.21:17:17.54#ibcon#*after write, iclass 15, count 0 2006.285.21:17:17.54#ibcon#*before return 0, iclass 15, count 0 2006.285.21:17:17.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:17:17.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:17:17.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.21:17:17.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.21:17:17.55$vck44/vbbw=wide 2006.285.21:17:17.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.21:17:17.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.21:17:17.55#ibcon#ireg 8 cls_cnt 0 2006.285.21:17:17.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:17:17.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:17:17.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:17:17.61#ibcon#enter wrdev, iclass 17, count 0 2006.285.21:17:17.61#ibcon#first serial, iclass 17, count 0 2006.285.21:17:17.61#ibcon#enter sib2, iclass 17, count 0 2006.285.21:17:17.61#ibcon#flushed, iclass 17, count 0 2006.285.21:17:17.61#ibcon#about to write, iclass 17, count 0 2006.285.21:17:17.61#ibcon#wrote, iclass 17, count 0 2006.285.21:17:17.61#ibcon#about to read 3, iclass 17, count 0 2006.285.21:17:17.63#ibcon#read 3, iclass 17, count 0 2006.285.21:17:17.63#ibcon#about to read 4, iclass 17, count 0 2006.285.21:17:17.63#ibcon#read 4, iclass 17, count 0 2006.285.21:17:17.63#ibcon#about to read 5, iclass 17, count 0 2006.285.21:17:17.63#ibcon#read 5, iclass 17, count 0 2006.285.21:17:17.63#ibcon#about to read 6, iclass 17, count 0 2006.285.21:17:17.63#ibcon#read 6, iclass 17, count 0 2006.285.21:17:17.63#ibcon#end of sib2, iclass 17, count 0 2006.285.21:17:17.63#ibcon#*mode == 0, iclass 17, count 0 2006.285.21:17:17.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.21:17:17.63#ibcon#[27=BW32\r\n] 2006.285.21:17:17.63#ibcon#*before write, iclass 17, count 0 2006.285.21:17:17.64#ibcon#enter sib2, iclass 17, count 0 2006.285.21:17:17.64#ibcon#flushed, iclass 17, count 0 2006.285.21:17:17.64#ibcon#about to write, iclass 17, count 0 2006.285.21:17:17.64#ibcon#wrote, iclass 17, count 0 2006.285.21:17:17.64#ibcon#about to read 3, iclass 17, count 0 2006.285.21:17:17.66#ibcon#read 3, iclass 17, count 0 2006.285.21:17:17.66#ibcon#about to read 4, iclass 17, count 0 2006.285.21:17:17.66#ibcon#read 4, iclass 17, count 0 2006.285.21:17:17.66#ibcon#about to read 5, iclass 17, count 0 2006.285.21:17:17.66#ibcon#read 5, iclass 17, count 0 2006.285.21:17:17.66#ibcon#about to read 6, iclass 17, count 0 2006.285.21:17:17.66#ibcon#read 6, iclass 17, count 0 2006.285.21:17:17.66#ibcon#end of sib2, iclass 17, count 0 2006.285.21:17:17.66#ibcon#*after write, iclass 17, count 0 2006.285.21:17:17.66#ibcon#*before return 0, iclass 17, count 0 2006.285.21:17:17.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:17:17.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:17:17.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.21:17:17.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.21:17:17.67$setupk4/ifdk4 2006.285.21:17:17.67$ifdk4/lo= 2006.285.21:17:17.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:17:17.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:17:17.67$ifdk4/patch= 2006.285.21:17:17.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:17:17.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:17:17.67$setupk4/!*+20s 2006.285.21:17:20.47#abcon#<5=/12 0.3 1.2 14.351001015.6\r\n> 2006.285.21:17:20.49#abcon#{5=INTERFACE CLEAR} 2006.285.21:17:20.55#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:17:23.13#trakl#Source acquired 2006.285.21:17:23.14#flagr#flagr/antenna,acquired 2006.285.21:17:30.64#abcon#<5=/12 0.3 1.2 14.361001015.6\r\n> 2006.285.21:17:30.66#abcon#{5=INTERFACE CLEAR} 2006.285.21:17:30.72#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:17:31.45$setupk4/"tpicd 2006.285.21:17:31.45$setupk4/echo=off 2006.285.21:17:31.46$setupk4/xlog=off 2006.285.21:17:31.46:!2006.285.21:19:45 2006.285.21:19:45.01:preob 2006.285.21:19:46.14/onsource/TRACKING 2006.285.21:19:46.14:!2006.285.21:19:55 2006.285.21:19:55.01:"tape 2006.285.21:19:55.01:"st=record 2006.285.21:19:55.01:data_valid=on 2006.285.21:19:55.02:midob 2006.285.21:19:56.14/onsource/TRACKING 2006.285.21:19:56.15/wx/14.36,1015.6,100 2006.285.21:19:56.31/cable/+6.5132E-03 2006.285.21:19:57.40/va/01,07,usb,yes,34,37 2006.285.21:19:57.40/va/02,06,usb,yes,35,35 2006.285.21:19:57.40/va/03,07,usb,yes,34,36 2006.285.21:19:57.40/va/04,06,usb,yes,36,37 2006.285.21:19:57.40/va/05,03,usb,yes,35,36 2006.285.21:19:57.40/va/06,04,usb,yes,32,31 2006.285.21:19:57.40/va/07,04,usb,yes,32,33 2006.285.21:19:57.40/va/08,03,usb,yes,33,40 2006.285.21:19:57.63/valo/01,524.99,yes,locked 2006.285.21:19:57.63/valo/02,534.99,yes,locked 2006.285.21:19:57.63/valo/03,564.99,yes,locked 2006.285.21:19:57.63/valo/04,624.99,yes,locked 2006.285.21:19:57.63/valo/05,734.99,yes,locked 2006.285.21:19:57.63/valo/06,814.99,yes,locked 2006.285.21:19:57.63/valo/07,864.99,yes,locked 2006.285.21:19:57.63/valo/08,884.99,yes,locked 2006.285.21:19:58.72/vb/01,04,usb,yes,31,29 2006.285.21:19:58.72/vb/02,05,usb,yes,29,29 2006.285.21:19:58.72/vb/03,04,usb,yes,30,33 2006.285.21:19:58.72/vb/04,05,usb,yes,30,29 2006.285.21:19:58.72/vb/05,04,usb,yes,27,29 2006.285.21:19:58.72/vb/06,03,usb,yes,39,34 2006.285.21:19:58.72/vb/07,04,usb,yes,31,31 2006.285.21:19:58.72/vb/08,04,usb,yes,28,32 2006.285.21:19:58.95/vblo/01,629.99,yes,locked 2006.285.21:19:58.95/vblo/02,634.99,yes,locked 2006.285.21:19:58.95/vblo/03,649.99,yes,locked 2006.285.21:19:58.95/vblo/04,679.99,yes,locked 2006.285.21:19:58.95/vblo/05,709.99,yes,locked 2006.285.21:19:58.95/vblo/06,719.99,yes,locked 2006.285.21:19:58.95/vblo/07,734.99,yes,locked 2006.285.21:19:58.95/vblo/08,744.99,yes,locked 2006.285.21:19:59.10/vabw/8 2006.285.21:19:59.25/vbbw/8 2006.285.21:19:59.34/xfe/off,on,12.0 2006.285.21:19:59.72/ifatt/23,28,28,28 2006.285.21:20:00.07/fmout-gps/S +2.86E-07 2006.285.21:20:00.09:!2006.285.21:22:05 2006.285.21:22:05.01:data_valid=off 2006.285.21:22:05.01:"et 2006.285.21:22:05.01:!+3s 2006.285.21:22:08.03:"tape 2006.285.21:22:08.03:postob 2006.285.21:22:08.21/cable/+6.5101E-03 2006.285.21:22:08.21/wx/14.42,1015.7,100 2006.285.21:22:08.27/fmout-gps/S +2.87E-07 2006.285.21:22:08.27:scan_name=285-2126,jd0610,100 2006.285.21:22:08.27:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.285.21:22:09.14#flagr#flagr/antenna,new-source 2006.285.21:22:09.14:checkk5 2006.285.21:22:09.90/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:22:10.35/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:22:10.76/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:22:11.21/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:22:11.58/chk_obsdata//k5ts1/T2852119??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.285.21:22:11.96/chk_obsdata//k5ts2/T2852119??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.285.21:22:12.48/chk_obsdata//k5ts3/T2852119??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.285.21:22:13.27/chk_obsdata//k5ts4/T2852119??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.285.21:22:14.19/k5log//k5ts1_log_newline 2006.285.21:22:15.04/k5log//k5ts2_log_newline 2006.285.21:22:15.76/k5log//k5ts3_log_newline 2006.285.21:22:16.60/k5log//k5ts4_log_newline 2006.285.21:22:16.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:22:16.62:setupk4=1 2006.285.21:22:16.62$setupk4/echo=on 2006.285.21:22:16.62$setupk4/pcalon 2006.285.21:22:16.62$pcalon/"no phase cal control is implemented here 2006.285.21:22:16.62$setupk4/"tpicd=stop 2006.285.21:22:16.62$setupk4/"rec=synch_on 2006.285.21:22:16.62$setupk4/"rec_mode=128 2006.285.21:22:16.62$setupk4/!* 2006.285.21:22:16.62$setupk4/recpk4 2006.285.21:22:16.62$recpk4/recpatch= 2006.285.21:22:16.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:22:16.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:22:16.62$setupk4/vck44 2006.285.21:22:16.63$vck44/valo=1,524.99 2006.285.21:22:16.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.21:22:16.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.21:22:16.63#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:16.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:22:16.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:22:16.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:22:16.63#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:22:16.63#ibcon#first serial, iclass 34, count 0 2006.285.21:22:16.63#ibcon#enter sib2, iclass 34, count 0 2006.285.21:22:16.63#ibcon#flushed, iclass 34, count 0 2006.285.21:22:16.63#ibcon#about to write, iclass 34, count 0 2006.285.21:22:16.63#ibcon#wrote, iclass 34, count 0 2006.285.21:22:16.63#ibcon#about to read 3, iclass 34, count 0 2006.285.21:22:16.64#ibcon#read 3, iclass 34, count 0 2006.285.21:22:16.64#ibcon#about to read 4, iclass 34, count 0 2006.285.21:22:16.64#ibcon#read 4, iclass 34, count 0 2006.285.21:22:16.64#ibcon#about to read 5, iclass 34, count 0 2006.285.21:22:16.64#ibcon#read 5, iclass 34, count 0 2006.285.21:22:16.64#ibcon#about to read 6, iclass 34, count 0 2006.285.21:22:16.64#ibcon#read 6, iclass 34, count 0 2006.285.21:22:16.64#ibcon#end of sib2, iclass 34, count 0 2006.285.21:22:16.64#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:22:16.64#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:22:16.64#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:22:16.64#ibcon#*before write, iclass 34, count 0 2006.285.21:22:16.64#ibcon#enter sib2, iclass 34, count 0 2006.285.21:22:16.64#ibcon#flushed, iclass 34, count 0 2006.285.21:22:16.64#ibcon#about to write, iclass 34, count 0 2006.285.21:22:16.64#ibcon#wrote, iclass 34, count 0 2006.285.21:22:16.64#ibcon#about to read 3, iclass 34, count 0 2006.285.21:22:16.69#ibcon#read 3, iclass 34, count 0 2006.285.21:22:16.69#ibcon#about to read 4, iclass 34, count 0 2006.285.21:22:16.69#ibcon#read 4, iclass 34, count 0 2006.285.21:22:16.69#ibcon#about to read 5, iclass 34, count 0 2006.285.21:22:16.69#ibcon#read 5, iclass 34, count 0 2006.285.21:22:16.69#ibcon#about to read 6, iclass 34, count 0 2006.285.21:22:16.69#ibcon#read 6, iclass 34, count 0 2006.285.21:22:16.69#ibcon#end of sib2, iclass 34, count 0 2006.285.21:22:16.69#ibcon#*after write, iclass 34, count 0 2006.285.21:22:16.69#ibcon#*before return 0, iclass 34, count 0 2006.285.21:22:16.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:22:16.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:22:16.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:22:16.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:22:16.69$vck44/va=1,7 2006.285.21:22:16.69#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.21:22:16.69#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.21:22:16.69#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:16.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:22:16.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:22:16.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:22:16.69#ibcon#enter wrdev, iclass 36, count 2 2006.285.21:22:16.69#ibcon#first serial, iclass 36, count 2 2006.285.21:22:16.69#ibcon#enter sib2, iclass 36, count 2 2006.285.21:22:16.69#ibcon#flushed, iclass 36, count 2 2006.285.21:22:16.69#ibcon#about to write, iclass 36, count 2 2006.285.21:22:16.69#ibcon#wrote, iclass 36, count 2 2006.285.21:22:16.69#ibcon#about to read 3, iclass 36, count 2 2006.285.21:22:16.71#ibcon#read 3, iclass 36, count 2 2006.285.21:22:16.71#ibcon#about to read 4, iclass 36, count 2 2006.285.21:22:16.71#ibcon#read 4, iclass 36, count 2 2006.285.21:22:16.71#ibcon#about to read 5, iclass 36, count 2 2006.285.21:22:16.71#ibcon#read 5, iclass 36, count 2 2006.285.21:22:16.71#ibcon#about to read 6, iclass 36, count 2 2006.285.21:22:16.71#ibcon#read 6, iclass 36, count 2 2006.285.21:22:16.71#ibcon#end of sib2, iclass 36, count 2 2006.285.21:22:16.71#ibcon#*mode == 0, iclass 36, count 2 2006.285.21:22:16.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.21:22:16.71#ibcon#[25=AT01-07\r\n] 2006.285.21:22:16.71#ibcon#*before write, iclass 36, count 2 2006.285.21:22:16.71#ibcon#enter sib2, iclass 36, count 2 2006.285.21:22:16.71#ibcon#flushed, iclass 36, count 2 2006.285.21:22:16.71#ibcon#about to write, iclass 36, count 2 2006.285.21:22:16.71#ibcon#wrote, iclass 36, count 2 2006.285.21:22:16.71#ibcon#about to read 3, iclass 36, count 2 2006.285.21:22:16.74#ibcon#read 3, iclass 36, count 2 2006.285.21:22:16.74#ibcon#about to read 4, iclass 36, count 2 2006.285.21:22:16.74#ibcon#read 4, iclass 36, count 2 2006.285.21:22:16.74#ibcon#about to read 5, iclass 36, count 2 2006.285.21:22:16.74#ibcon#read 5, iclass 36, count 2 2006.285.21:22:16.74#ibcon#about to read 6, iclass 36, count 2 2006.285.21:22:16.74#ibcon#read 6, iclass 36, count 2 2006.285.21:22:16.74#ibcon#end of sib2, iclass 36, count 2 2006.285.21:22:16.74#ibcon#*after write, iclass 36, count 2 2006.285.21:22:16.74#ibcon#*before return 0, iclass 36, count 2 2006.285.21:22:16.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:22:16.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:22:16.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.21:22:16.74#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:16.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:22:16.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:22:16.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:22:16.86#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:22:16.86#ibcon#first serial, iclass 36, count 0 2006.285.21:22:16.86#ibcon#enter sib2, iclass 36, count 0 2006.285.21:22:16.86#ibcon#flushed, iclass 36, count 0 2006.285.21:22:16.86#ibcon#about to write, iclass 36, count 0 2006.285.21:22:16.86#ibcon#wrote, iclass 36, count 0 2006.285.21:22:16.86#ibcon#about to read 3, iclass 36, count 0 2006.285.21:22:16.88#ibcon#read 3, iclass 36, count 0 2006.285.21:22:16.88#ibcon#about to read 4, iclass 36, count 0 2006.285.21:22:16.88#ibcon#read 4, iclass 36, count 0 2006.285.21:22:16.88#ibcon#about to read 5, iclass 36, count 0 2006.285.21:22:16.88#ibcon#read 5, iclass 36, count 0 2006.285.21:22:16.88#ibcon#about to read 6, iclass 36, count 0 2006.285.21:22:16.88#ibcon#read 6, iclass 36, count 0 2006.285.21:22:16.88#ibcon#end of sib2, iclass 36, count 0 2006.285.21:22:16.88#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:22:16.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:22:16.88#ibcon#[25=USB\r\n] 2006.285.21:22:16.88#ibcon#*before write, iclass 36, count 0 2006.285.21:22:16.88#ibcon#enter sib2, iclass 36, count 0 2006.285.21:22:16.88#ibcon#flushed, iclass 36, count 0 2006.285.21:22:16.88#ibcon#about to write, iclass 36, count 0 2006.285.21:22:16.88#ibcon#wrote, iclass 36, count 0 2006.285.21:22:16.88#ibcon#about to read 3, iclass 36, count 0 2006.285.21:22:16.91#ibcon#read 3, iclass 36, count 0 2006.285.21:22:16.91#ibcon#about to read 4, iclass 36, count 0 2006.285.21:22:16.91#ibcon#read 4, iclass 36, count 0 2006.285.21:22:16.91#ibcon#about to read 5, iclass 36, count 0 2006.285.21:22:16.91#ibcon#read 5, iclass 36, count 0 2006.285.21:22:16.91#ibcon#about to read 6, iclass 36, count 0 2006.285.21:22:16.91#ibcon#read 6, iclass 36, count 0 2006.285.21:22:16.91#ibcon#end of sib2, iclass 36, count 0 2006.285.21:22:16.91#ibcon#*after write, iclass 36, count 0 2006.285.21:22:16.91#ibcon#*before return 0, iclass 36, count 0 2006.285.21:22:16.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:22:16.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:22:16.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:22:16.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:22:16.91$vck44/valo=2,534.99 2006.285.21:22:16.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.21:22:16.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.21:22:16.91#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:16.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:22:16.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:22:16.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:22:16.91#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:22:16.91#ibcon#first serial, iclass 38, count 0 2006.285.21:22:16.91#ibcon#enter sib2, iclass 38, count 0 2006.285.21:22:16.91#ibcon#flushed, iclass 38, count 0 2006.285.21:22:16.91#ibcon#about to write, iclass 38, count 0 2006.285.21:22:16.91#ibcon#wrote, iclass 38, count 0 2006.285.21:22:16.91#ibcon#about to read 3, iclass 38, count 0 2006.285.21:22:16.93#ibcon#read 3, iclass 38, count 0 2006.285.21:22:16.93#ibcon#about to read 4, iclass 38, count 0 2006.285.21:22:16.93#ibcon#read 4, iclass 38, count 0 2006.285.21:22:16.93#ibcon#about to read 5, iclass 38, count 0 2006.285.21:22:16.93#ibcon#read 5, iclass 38, count 0 2006.285.21:22:16.93#ibcon#about to read 6, iclass 38, count 0 2006.285.21:22:16.93#ibcon#read 6, iclass 38, count 0 2006.285.21:22:16.93#ibcon#end of sib2, iclass 38, count 0 2006.285.21:22:16.93#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:22:16.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:22:16.93#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:22:16.93#ibcon#*before write, iclass 38, count 0 2006.285.21:22:16.93#ibcon#enter sib2, iclass 38, count 0 2006.285.21:22:16.93#ibcon#flushed, iclass 38, count 0 2006.285.21:22:16.93#ibcon#about to write, iclass 38, count 0 2006.285.21:22:16.93#ibcon#wrote, iclass 38, count 0 2006.285.21:22:16.93#ibcon#about to read 3, iclass 38, count 0 2006.285.21:22:16.97#ibcon#read 3, iclass 38, count 0 2006.285.21:22:16.97#ibcon#about to read 4, iclass 38, count 0 2006.285.21:22:16.97#ibcon#read 4, iclass 38, count 0 2006.285.21:22:16.97#ibcon#about to read 5, iclass 38, count 0 2006.285.21:22:16.97#ibcon#read 5, iclass 38, count 0 2006.285.21:22:16.97#ibcon#about to read 6, iclass 38, count 0 2006.285.21:22:16.97#ibcon#read 6, iclass 38, count 0 2006.285.21:22:16.97#ibcon#end of sib2, iclass 38, count 0 2006.285.21:22:16.97#ibcon#*after write, iclass 38, count 0 2006.285.21:22:16.97#ibcon#*before return 0, iclass 38, count 0 2006.285.21:22:16.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:22:16.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:22:16.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:22:16.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:22:16.97$vck44/va=2,6 2006.285.21:22:16.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.21:22:16.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.21:22:16.97#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:16.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:22:17.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:22:17.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:22:17.03#ibcon#enter wrdev, iclass 40, count 2 2006.285.21:22:17.03#ibcon#first serial, iclass 40, count 2 2006.285.21:22:17.03#ibcon#enter sib2, iclass 40, count 2 2006.285.21:22:17.03#ibcon#flushed, iclass 40, count 2 2006.285.21:22:17.03#ibcon#about to write, iclass 40, count 2 2006.285.21:22:17.03#ibcon#wrote, iclass 40, count 2 2006.285.21:22:17.03#ibcon#about to read 3, iclass 40, count 2 2006.285.21:22:17.05#ibcon#read 3, iclass 40, count 2 2006.285.21:22:17.05#ibcon#about to read 4, iclass 40, count 2 2006.285.21:22:17.05#ibcon#read 4, iclass 40, count 2 2006.285.21:22:17.05#ibcon#about to read 5, iclass 40, count 2 2006.285.21:22:17.05#ibcon#read 5, iclass 40, count 2 2006.285.21:22:17.05#ibcon#about to read 6, iclass 40, count 2 2006.285.21:22:17.05#ibcon#read 6, iclass 40, count 2 2006.285.21:22:17.05#ibcon#end of sib2, iclass 40, count 2 2006.285.21:22:17.05#ibcon#*mode == 0, iclass 40, count 2 2006.285.21:22:17.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.21:22:17.05#ibcon#[25=AT02-06\r\n] 2006.285.21:22:17.05#ibcon#*before write, iclass 40, count 2 2006.285.21:22:17.05#ibcon#enter sib2, iclass 40, count 2 2006.285.21:22:17.05#ibcon#flushed, iclass 40, count 2 2006.285.21:22:17.05#ibcon#about to write, iclass 40, count 2 2006.285.21:22:17.05#ibcon#wrote, iclass 40, count 2 2006.285.21:22:17.05#ibcon#about to read 3, iclass 40, count 2 2006.285.21:22:17.08#ibcon#read 3, iclass 40, count 2 2006.285.21:22:17.08#ibcon#about to read 4, iclass 40, count 2 2006.285.21:22:17.08#ibcon#read 4, iclass 40, count 2 2006.285.21:22:17.08#ibcon#about to read 5, iclass 40, count 2 2006.285.21:22:17.08#ibcon#read 5, iclass 40, count 2 2006.285.21:22:17.08#ibcon#about to read 6, iclass 40, count 2 2006.285.21:22:17.08#ibcon#read 6, iclass 40, count 2 2006.285.21:22:17.08#ibcon#end of sib2, iclass 40, count 2 2006.285.21:22:17.08#ibcon#*after write, iclass 40, count 2 2006.285.21:22:17.08#ibcon#*before return 0, iclass 40, count 2 2006.285.21:22:17.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:22:17.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:22:17.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.21:22:17.08#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:17.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:22:17.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:22:17.57#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:22:17.57#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:22:17.57#ibcon#first serial, iclass 40, count 0 2006.285.21:22:17.57#ibcon#enter sib2, iclass 40, count 0 2006.285.21:22:17.57#ibcon#flushed, iclass 40, count 0 2006.285.21:22:17.57#ibcon#about to write, iclass 40, count 0 2006.285.21:22:17.57#ibcon#wrote, iclass 40, count 0 2006.285.21:22:17.57#ibcon#about to read 3, iclass 40, count 0 2006.285.21:22:17.58#ibcon#read 3, iclass 40, count 0 2006.285.21:22:17.58#ibcon#about to read 4, iclass 40, count 0 2006.285.21:22:17.58#ibcon#read 4, iclass 40, count 0 2006.285.21:22:17.58#ibcon#about to read 5, iclass 40, count 0 2006.285.21:22:17.58#ibcon#read 5, iclass 40, count 0 2006.285.21:22:17.58#ibcon#about to read 6, iclass 40, count 0 2006.285.21:22:17.58#ibcon#read 6, iclass 40, count 0 2006.285.21:22:17.58#ibcon#end of sib2, iclass 40, count 0 2006.285.21:22:17.58#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:22:17.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:22:17.58#ibcon#[25=USB\r\n] 2006.285.21:22:17.58#ibcon#*before write, iclass 40, count 0 2006.285.21:22:17.58#ibcon#enter sib2, iclass 40, count 0 2006.285.21:22:17.58#ibcon#flushed, iclass 40, count 0 2006.285.21:22:17.58#ibcon#about to write, iclass 40, count 0 2006.285.21:22:17.58#ibcon#wrote, iclass 40, count 0 2006.285.21:22:17.58#ibcon#about to read 3, iclass 40, count 0 2006.285.21:22:17.61#ibcon#read 3, iclass 40, count 0 2006.285.21:22:17.61#ibcon#about to read 4, iclass 40, count 0 2006.285.21:22:17.61#ibcon#read 4, iclass 40, count 0 2006.285.21:22:17.61#ibcon#about to read 5, iclass 40, count 0 2006.285.21:22:17.61#ibcon#read 5, iclass 40, count 0 2006.285.21:22:17.61#ibcon#about to read 6, iclass 40, count 0 2006.285.21:22:17.61#ibcon#read 6, iclass 40, count 0 2006.285.21:22:17.61#ibcon#end of sib2, iclass 40, count 0 2006.285.21:22:17.61#ibcon#*after write, iclass 40, count 0 2006.285.21:22:17.61#ibcon#*before return 0, iclass 40, count 0 2006.285.21:22:17.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:22:17.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:22:17.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:22:17.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:22:17.61$vck44/valo=3,564.99 2006.285.21:22:17.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.21:22:17.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.21:22:17.61#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:17.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:22:17.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:22:17.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:22:17.61#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:22:17.61#ibcon#first serial, iclass 4, count 0 2006.285.21:22:17.61#ibcon#enter sib2, iclass 4, count 0 2006.285.21:22:17.61#ibcon#flushed, iclass 4, count 0 2006.285.21:22:17.61#ibcon#about to write, iclass 4, count 0 2006.285.21:22:17.61#ibcon#wrote, iclass 4, count 0 2006.285.21:22:17.61#ibcon#about to read 3, iclass 4, count 0 2006.285.21:22:17.63#ibcon#read 3, iclass 4, count 0 2006.285.21:22:17.63#ibcon#about to read 4, iclass 4, count 0 2006.285.21:22:17.63#ibcon#read 4, iclass 4, count 0 2006.285.21:22:17.63#ibcon#about to read 5, iclass 4, count 0 2006.285.21:22:17.63#ibcon#read 5, iclass 4, count 0 2006.285.21:22:17.63#ibcon#about to read 6, iclass 4, count 0 2006.285.21:22:17.63#ibcon#read 6, iclass 4, count 0 2006.285.21:22:17.63#ibcon#end of sib2, iclass 4, count 0 2006.285.21:22:17.63#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:22:17.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:22:17.63#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:22:17.63#ibcon#*before write, iclass 4, count 0 2006.285.21:22:17.63#ibcon#enter sib2, iclass 4, count 0 2006.285.21:22:17.63#ibcon#flushed, iclass 4, count 0 2006.285.21:22:17.63#ibcon#about to write, iclass 4, count 0 2006.285.21:22:17.63#ibcon#wrote, iclass 4, count 0 2006.285.21:22:17.63#ibcon#about to read 3, iclass 4, count 0 2006.285.21:22:17.67#ibcon#read 3, iclass 4, count 0 2006.285.21:22:17.67#ibcon#about to read 4, iclass 4, count 0 2006.285.21:22:17.67#ibcon#read 4, iclass 4, count 0 2006.285.21:22:17.67#ibcon#about to read 5, iclass 4, count 0 2006.285.21:22:17.67#ibcon#read 5, iclass 4, count 0 2006.285.21:22:17.67#ibcon#about to read 6, iclass 4, count 0 2006.285.21:22:17.67#ibcon#read 6, iclass 4, count 0 2006.285.21:22:17.67#ibcon#end of sib2, iclass 4, count 0 2006.285.21:22:17.67#ibcon#*after write, iclass 4, count 0 2006.285.21:22:17.67#ibcon#*before return 0, iclass 4, count 0 2006.285.21:22:17.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:22:17.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:22:17.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:22:17.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:22:17.67$vck44/va=3,7 2006.285.21:22:17.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.21:22:17.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.21:22:17.67#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:17.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:22:17.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:22:17.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:22:17.73#ibcon#enter wrdev, iclass 6, count 2 2006.285.21:22:17.73#ibcon#first serial, iclass 6, count 2 2006.285.21:22:17.73#ibcon#enter sib2, iclass 6, count 2 2006.285.21:22:17.73#ibcon#flushed, iclass 6, count 2 2006.285.21:22:17.73#ibcon#about to write, iclass 6, count 2 2006.285.21:22:17.73#ibcon#wrote, iclass 6, count 2 2006.285.21:22:17.73#ibcon#about to read 3, iclass 6, count 2 2006.285.21:22:17.75#ibcon#read 3, iclass 6, count 2 2006.285.21:22:17.75#ibcon#about to read 4, iclass 6, count 2 2006.285.21:22:17.75#ibcon#read 4, iclass 6, count 2 2006.285.21:22:17.75#ibcon#about to read 5, iclass 6, count 2 2006.285.21:22:17.75#ibcon#read 5, iclass 6, count 2 2006.285.21:22:17.75#ibcon#about to read 6, iclass 6, count 2 2006.285.21:22:17.75#ibcon#read 6, iclass 6, count 2 2006.285.21:22:17.75#ibcon#end of sib2, iclass 6, count 2 2006.285.21:22:17.75#ibcon#*mode == 0, iclass 6, count 2 2006.285.21:22:17.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.21:22:17.75#ibcon#[25=AT03-07\r\n] 2006.285.21:22:17.75#ibcon#*before write, iclass 6, count 2 2006.285.21:22:17.75#ibcon#enter sib2, iclass 6, count 2 2006.285.21:22:17.75#ibcon#flushed, iclass 6, count 2 2006.285.21:22:17.75#ibcon#about to write, iclass 6, count 2 2006.285.21:22:17.75#ibcon#wrote, iclass 6, count 2 2006.285.21:22:17.75#ibcon#about to read 3, iclass 6, count 2 2006.285.21:22:17.78#ibcon#read 3, iclass 6, count 2 2006.285.21:22:17.78#ibcon#about to read 4, iclass 6, count 2 2006.285.21:22:17.78#ibcon#read 4, iclass 6, count 2 2006.285.21:22:17.78#ibcon#about to read 5, iclass 6, count 2 2006.285.21:22:17.78#ibcon#read 5, iclass 6, count 2 2006.285.21:22:17.78#ibcon#about to read 6, iclass 6, count 2 2006.285.21:22:17.78#ibcon#read 6, iclass 6, count 2 2006.285.21:22:17.78#ibcon#end of sib2, iclass 6, count 2 2006.285.21:22:17.78#ibcon#*after write, iclass 6, count 2 2006.285.21:22:17.78#ibcon#*before return 0, iclass 6, count 2 2006.285.21:22:17.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:22:17.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:22:17.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.21:22:17.78#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:17.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:22:17.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:22:17.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:22:17.90#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:22:17.90#ibcon#first serial, iclass 6, count 0 2006.285.21:22:17.90#ibcon#enter sib2, iclass 6, count 0 2006.285.21:22:17.90#ibcon#flushed, iclass 6, count 0 2006.285.21:22:17.90#ibcon#about to write, iclass 6, count 0 2006.285.21:22:17.90#ibcon#wrote, iclass 6, count 0 2006.285.21:22:17.90#ibcon#about to read 3, iclass 6, count 0 2006.285.21:22:17.92#ibcon#read 3, iclass 6, count 0 2006.285.21:22:17.92#ibcon#about to read 4, iclass 6, count 0 2006.285.21:22:17.92#ibcon#read 4, iclass 6, count 0 2006.285.21:22:17.92#ibcon#about to read 5, iclass 6, count 0 2006.285.21:22:17.92#ibcon#read 5, iclass 6, count 0 2006.285.21:22:17.92#ibcon#about to read 6, iclass 6, count 0 2006.285.21:22:17.92#ibcon#read 6, iclass 6, count 0 2006.285.21:22:17.92#ibcon#end of sib2, iclass 6, count 0 2006.285.21:22:17.92#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:22:18.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:22:18.14#ibcon#[25=USB\r\n] 2006.285.21:22:18.14#ibcon#*before write, iclass 6, count 0 2006.285.21:22:18.14#ibcon#enter sib2, iclass 6, count 0 2006.285.21:22:18.14#ibcon#flushed, iclass 6, count 0 2006.285.21:22:18.14#ibcon#about to write, iclass 6, count 0 2006.285.21:22:18.14#ibcon#wrote, iclass 6, count 0 2006.285.21:22:18.14#ibcon#about to read 3, iclass 6, count 0 2006.285.21:22:18.17#ibcon#read 3, iclass 6, count 0 2006.285.21:22:18.17#ibcon#about to read 4, iclass 6, count 0 2006.285.21:22:18.17#ibcon#read 4, iclass 6, count 0 2006.285.21:22:18.17#ibcon#about to read 5, iclass 6, count 0 2006.285.21:22:18.17#ibcon#read 5, iclass 6, count 0 2006.285.21:22:18.17#ibcon#about to read 6, iclass 6, count 0 2006.285.21:22:18.17#ibcon#read 6, iclass 6, count 0 2006.285.21:22:18.17#ibcon#end of sib2, iclass 6, count 0 2006.285.21:22:18.17#ibcon#*after write, iclass 6, count 0 2006.285.21:22:18.17#ibcon#*before return 0, iclass 6, count 0 2006.285.21:22:18.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:22:18.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:22:18.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:22:18.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:22:18.17$vck44/valo=4,624.99 2006.285.21:22:18.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.21:22:18.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.21:22:18.17#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:18.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:22:18.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:22:18.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:22:18.17#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:22:18.17#ibcon#first serial, iclass 10, count 0 2006.285.21:22:18.17#ibcon#enter sib2, iclass 10, count 0 2006.285.21:22:18.17#ibcon#flushed, iclass 10, count 0 2006.285.21:22:18.17#ibcon#about to write, iclass 10, count 0 2006.285.21:22:18.17#ibcon#wrote, iclass 10, count 0 2006.285.21:22:18.17#ibcon#about to read 3, iclass 10, count 0 2006.285.21:22:18.19#ibcon#read 3, iclass 10, count 0 2006.285.21:22:18.19#ibcon#about to read 4, iclass 10, count 0 2006.285.21:22:18.19#ibcon#read 4, iclass 10, count 0 2006.285.21:22:18.19#ibcon#about to read 5, iclass 10, count 0 2006.285.21:22:18.19#ibcon#read 5, iclass 10, count 0 2006.285.21:22:18.19#ibcon#about to read 6, iclass 10, count 0 2006.285.21:22:18.19#ibcon#read 6, iclass 10, count 0 2006.285.21:22:18.19#ibcon#end of sib2, iclass 10, count 0 2006.285.21:22:18.19#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:22:18.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:22:18.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:22:18.19#ibcon#*before write, iclass 10, count 0 2006.285.21:22:18.19#ibcon#enter sib2, iclass 10, count 0 2006.285.21:22:18.19#ibcon#flushed, iclass 10, count 0 2006.285.21:22:18.19#ibcon#about to write, iclass 10, count 0 2006.285.21:22:18.19#ibcon#wrote, iclass 10, count 0 2006.285.21:22:18.19#ibcon#about to read 3, iclass 10, count 0 2006.285.21:22:18.23#ibcon#read 3, iclass 10, count 0 2006.285.21:22:18.23#ibcon#about to read 4, iclass 10, count 0 2006.285.21:22:18.23#ibcon#read 4, iclass 10, count 0 2006.285.21:22:18.23#ibcon#about to read 5, iclass 10, count 0 2006.285.21:22:18.23#ibcon#read 5, iclass 10, count 0 2006.285.21:22:18.23#ibcon#about to read 6, iclass 10, count 0 2006.285.21:22:18.23#ibcon#read 6, iclass 10, count 0 2006.285.21:22:18.23#ibcon#end of sib2, iclass 10, count 0 2006.285.21:22:18.23#ibcon#*after write, iclass 10, count 0 2006.285.21:22:18.23#ibcon#*before return 0, iclass 10, count 0 2006.285.21:22:18.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:22:18.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:22:18.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:22:18.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:22:18.23$vck44/va=4,6 2006.285.21:22:18.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.21:22:18.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.21:22:18.23#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:18.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:22:18.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:22:18.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:22:18.29#ibcon#enter wrdev, iclass 12, count 2 2006.285.21:22:18.29#ibcon#first serial, iclass 12, count 2 2006.285.21:22:18.29#ibcon#enter sib2, iclass 12, count 2 2006.285.21:22:18.29#ibcon#flushed, iclass 12, count 2 2006.285.21:22:18.29#ibcon#about to write, iclass 12, count 2 2006.285.21:22:18.29#ibcon#wrote, iclass 12, count 2 2006.285.21:22:18.29#ibcon#about to read 3, iclass 12, count 2 2006.285.21:22:18.31#ibcon#read 3, iclass 12, count 2 2006.285.21:22:18.31#ibcon#about to read 4, iclass 12, count 2 2006.285.21:22:18.31#ibcon#read 4, iclass 12, count 2 2006.285.21:22:18.31#ibcon#about to read 5, iclass 12, count 2 2006.285.21:22:18.31#ibcon#read 5, iclass 12, count 2 2006.285.21:22:18.31#ibcon#about to read 6, iclass 12, count 2 2006.285.21:22:18.31#ibcon#read 6, iclass 12, count 2 2006.285.21:22:18.31#ibcon#end of sib2, iclass 12, count 2 2006.285.21:22:18.31#ibcon#*mode == 0, iclass 12, count 2 2006.285.21:22:18.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.21:22:18.31#ibcon#[25=AT04-06\r\n] 2006.285.21:22:18.31#ibcon#*before write, iclass 12, count 2 2006.285.21:22:18.31#ibcon#enter sib2, iclass 12, count 2 2006.285.21:22:18.31#ibcon#flushed, iclass 12, count 2 2006.285.21:22:18.31#ibcon#about to write, iclass 12, count 2 2006.285.21:22:18.31#ibcon#wrote, iclass 12, count 2 2006.285.21:22:18.31#ibcon#about to read 3, iclass 12, count 2 2006.285.21:22:18.34#ibcon#read 3, iclass 12, count 2 2006.285.21:22:18.34#ibcon#about to read 4, iclass 12, count 2 2006.285.21:22:18.34#ibcon#read 4, iclass 12, count 2 2006.285.21:22:18.34#ibcon#about to read 5, iclass 12, count 2 2006.285.21:22:18.34#ibcon#read 5, iclass 12, count 2 2006.285.21:22:18.34#ibcon#about to read 6, iclass 12, count 2 2006.285.21:22:18.34#ibcon#read 6, iclass 12, count 2 2006.285.21:22:18.34#ibcon#end of sib2, iclass 12, count 2 2006.285.21:22:18.34#ibcon#*after write, iclass 12, count 2 2006.285.21:22:18.34#ibcon#*before return 0, iclass 12, count 2 2006.285.21:22:18.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:22:18.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:22:18.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.21:22:18.34#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:18.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:22:18.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:22:18.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:22:18.46#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:22:18.46#ibcon#first serial, iclass 12, count 0 2006.285.21:22:18.46#ibcon#enter sib2, iclass 12, count 0 2006.285.21:22:18.46#ibcon#flushed, iclass 12, count 0 2006.285.21:22:18.46#ibcon#about to write, iclass 12, count 0 2006.285.21:22:18.46#ibcon#wrote, iclass 12, count 0 2006.285.21:22:18.46#ibcon#about to read 3, iclass 12, count 0 2006.285.21:22:18.48#ibcon#read 3, iclass 12, count 0 2006.285.21:22:18.48#ibcon#about to read 4, iclass 12, count 0 2006.285.21:22:18.48#ibcon#read 4, iclass 12, count 0 2006.285.21:22:18.48#ibcon#about to read 5, iclass 12, count 0 2006.285.21:22:18.48#ibcon#read 5, iclass 12, count 0 2006.285.21:22:18.48#ibcon#about to read 6, iclass 12, count 0 2006.285.21:22:18.48#ibcon#read 6, iclass 12, count 0 2006.285.21:22:18.48#ibcon#end of sib2, iclass 12, count 0 2006.285.21:22:18.48#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:22:18.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:22:18.48#ibcon#[25=USB\r\n] 2006.285.21:22:18.48#ibcon#*before write, iclass 12, count 0 2006.285.21:22:18.48#ibcon#enter sib2, iclass 12, count 0 2006.285.21:22:18.48#ibcon#flushed, iclass 12, count 0 2006.285.21:22:18.48#ibcon#about to write, iclass 12, count 0 2006.285.21:22:18.48#ibcon#wrote, iclass 12, count 0 2006.285.21:22:18.48#ibcon#about to read 3, iclass 12, count 0 2006.285.21:22:18.51#ibcon#read 3, iclass 12, count 0 2006.285.21:22:18.51#ibcon#about to read 4, iclass 12, count 0 2006.285.21:22:18.51#ibcon#read 4, iclass 12, count 0 2006.285.21:22:18.51#ibcon#about to read 5, iclass 12, count 0 2006.285.21:22:18.51#ibcon#read 5, iclass 12, count 0 2006.285.21:22:18.51#ibcon#about to read 6, iclass 12, count 0 2006.285.21:22:18.51#ibcon#read 6, iclass 12, count 0 2006.285.21:22:18.51#ibcon#end of sib2, iclass 12, count 0 2006.285.21:22:18.51#ibcon#*after write, iclass 12, count 0 2006.285.21:22:18.51#ibcon#*before return 0, iclass 12, count 0 2006.285.21:22:18.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:22:18.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:22:18.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:22:18.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:22:18.51$vck44/valo=5,734.99 2006.285.21:22:18.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.21:22:18.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.21:22:18.51#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:18.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:22:18.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:22:18.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:22:18.51#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:22:18.51#ibcon#first serial, iclass 14, count 0 2006.285.21:22:18.51#ibcon#enter sib2, iclass 14, count 0 2006.285.21:22:18.51#ibcon#flushed, iclass 14, count 0 2006.285.21:22:18.51#ibcon#about to write, iclass 14, count 0 2006.285.21:22:18.51#ibcon#wrote, iclass 14, count 0 2006.285.21:22:18.51#ibcon#about to read 3, iclass 14, count 0 2006.285.21:22:18.53#ibcon#read 3, iclass 14, count 0 2006.285.21:22:18.53#ibcon#about to read 4, iclass 14, count 0 2006.285.21:22:18.53#ibcon#read 4, iclass 14, count 0 2006.285.21:22:18.53#ibcon#about to read 5, iclass 14, count 0 2006.285.21:22:18.53#ibcon#read 5, iclass 14, count 0 2006.285.21:22:18.53#ibcon#about to read 6, iclass 14, count 0 2006.285.21:22:18.53#ibcon#read 6, iclass 14, count 0 2006.285.21:22:18.53#ibcon#end of sib2, iclass 14, count 0 2006.285.21:22:18.53#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:22:18.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:22:18.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:22:18.53#ibcon#*before write, iclass 14, count 0 2006.285.21:22:18.53#ibcon#enter sib2, iclass 14, count 0 2006.285.21:22:18.53#ibcon#flushed, iclass 14, count 0 2006.285.21:22:18.53#ibcon#about to write, iclass 14, count 0 2006.285.21:22:18.53#ibcon#wrote, iclass 14, count 0 2006.285.21:22:18.53#ibcon#about to read 3, iclass 14, count 0 2006.285.21:22:18.57#ibcon#read 3, iclass 14, count 0 2006.285.21:22:18.57#ibcon#about to read 4, iclass 14, count 0 2006.285.21:22:18.57#ibcon#read 4, iclass 14, count 0 2006.285.21:22:18.57#ibcon#about to read 5, iclass 14, count 0 2006.285.21:22:18.57#ibcon#read 5, iclass 14, count 0 2006.285.21:22:18.57#ibcon#about to read 6, iclass 14, count 0 2006.285.21:22:18.57#ibcon#read 6, iclass 14, count 0 2006.285.21:22:18.57#ibcon#end of sib2, iclass 14, count 0 2006.285.21:22:18.57#ibcon#*after write, iclass 14, count 0 2006.285.21:22:18.57#ibcon#*before return 0, iclass 14, count 0 2006.285.21:22:18.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:22:18.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:22:18.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:22:18.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:22:18.57$vck44/va=5,3 2006.285.21:22:18.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.21:22:18.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.21:22:18.57#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:18.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:22:18.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:22:18.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:22:18.63#ibcon#enter wrdev, iclass 16, count 2 2006.285.21:22:18.63#ibcon#first serial, iclass 16, count 2 2006.285.21:22:18.63#ibcon#enter sib2, iclass 16, count 2 2006.285.21:22:18.63#ibcon#flushed, iclass 16, count 2 2006.285.21:22:18.63#ibcon#about to write, iclass 16, count 2 2006.285.21:22:18.63#ibcon#wrote, iclass 16, count 2 2006.285.21:22:18.63#ibcon#about to read 3, iclass 16, count 2 2006.285.21:22:18.65#ibcon#read 3, iclass 16, count 2 2006.285.21:22:18.65#ibcon#about to read 4, iclass 16, count 2 2006.285.21:22:18.65#ibcon#read 4, iclass 16, count 2 2006.285.21:22:18.65#ibcon#about to read 5, iclass 16, count 2 2006.285.21:22:18.65#ibcon#read 5, iclass 16, count 2 2006.285.21:22:18.65#ibcon#about to read 6, iclass 16, count 2 2006.285.21:22:18.65#ibcon#read 6, iclass 16, count 2 2006.285.21:22:18.65#ibcon#end of sib2, iclass 16, count 2 2006.285.21:22:18.65#ibcon#*mode == 0, iclass 16, count 2 2006.285.21:22:18.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.21:22:18.65#ibcon#[25=AT05-03\r\n] 2006.285.21:22:18.65#ibcon#*before write, iclass 16, count 2 2006.285.21:22:18.65#ibcon#enter sib2, iclass 16, count 2 2006.285.21:22:18.65#ibcon#flushed, iclass 16, count 2 2006.285.21:22:18.65#ibcon#about to write, iclass 16, count 2 2006.285.21:22:18.65#ibcon#wrote, iclass 16, count 2 2006.285.21:22:18.65#ibcon#about to read 3, iclass 16, count 2 2006.285.21:22:18.68#ibcon#read 3, iclass 16, count 2 2006.285.21:22:18.68#ibcon#about to read 4, iclass 16, count 2 2006.285.21:22:18.68#ibcon#read 4, iclass 16, count 2 2006.285.21:22:18.68#ibcon#about to read 5, iclass 16, count 2 2006.285.21:22:18.68#ibcon#read 5, iclass 16, count 2 2006.285.21:22:18.68#ibcon#about to read 6, iclass 16, count 2 2006.285.21:22:18.68#ibcon#read 6, iclass 16, count 2 2006.285.21:22:18.68#ibcon#end of sib2, iclass 16, count 2 2006.285.21:22:18.68#ibcon#*after write, iclass 16, count 2 2006.285.21:22:18.68#ibcon#*before return 0, iclass 16, count 2 2006.285.21:22:18.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:22:18.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:22:18.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.21:22:18.68#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:18.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:22:18.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:22:18.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:22:18.80#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:22:18.80#ibcon#first serial, iclass 16, count 0 2006.285.21:22:18.80#ibcon#enter sib2, iclass 16, count 0 2006.285.21:22:18.80#ibcon#flushed, iclass 16, count 0 2006.285.21:22:18.80#ibcon#about to write, iclass 16, count 0 2006.285.21:22:18.80#ibcon#wrote, iclass 16, count 0 2006.285.21:22:18.80#ibcon#about to read 3, iclass 16, count 0 2006.285.21:22:18.82#ibcon#read 3, iclass 16, count 0 2006.285.21:22:18.82#ibcon#about to read 4, iclass 16, count 0 2006.285.21:22:18.82#ibcon#read 4, iclass 16, count 0 2006.285.21:22:18.82#ibcon#about to read 5, iclass 16, count 0 2006.285.21:22:18.82#ibcon#read 5, iclass 16, count 0 2006.285.21:22:18.82#ibcon#about to read 6, iclass 16, count 0 2006.285.21:22:18.82#ibcon#read 6, iclass 16, count 0 2006.285.21:22:18.82#ibcon#end of sib2, iclass 16, count 0 2006.285.21:22:18.82#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:22:18.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:22:18.82#ibcon#[25=USB\r\n] 2006.285.21:22:18.82#ibcon#*before write, iclass 16, count 0 2006.285.21:22:18.82#ibcon#enter sib2, iclass 16, count 0 2006.285.21:22:18.82#ibcon#flushed, iclass 16, count 0 2006.285.21:22:18.82#ibcon#about to write, iclass 16, count 0 2006.285.21:22:18.82#ibcon#wrote, iclass 16, count 0 2006.285.21:22:18.82#ibcon#about to read 3, iclass 16, count 0 2006.285.21:22:18.85#ibcon#read 3, iclass 16, count 0 2006.285.21:22:18.85#ibcon#about to read 4, iclass 16, count 0 2006.285.21:22:18.85#ibcon#read 4, iclass 16, count 0 2006.285.21:22:18.85#ibcon#about to read 5, iclass 16, count 0 2006.285.21:22:18.85#ibcon#read 5, iclass 16, count 0 2006.285.21:22:18.85#ibcon#about to read 6, iclass 16, count 0 2006.285.21:22:18.85#ibcon#read 6, iclass 16, count 0 2006.285.21:22:18.85#ibcon#end of sib2, iclass 16, count 0 2006.285.21:22:18.85#ibcon#*after write, iclass 16, count 0 2006.285.21:22:18.85#ibcon#*before return 0, iclass 16, count 0 2006.285.21:22:18.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:22:18.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:22:18.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:22:18.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:22:18.85$vck44/valo=6,814.99 2006.285.21:22:18.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.21:22:18.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.21:22:18.85#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:18.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:22:18.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:22:18.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:22:18.85#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:22:18.85#ibcon#first serial, iclass 18, count 0 2006.285.21:22:18.85#ibcon#enter sib2, iclass 18, count 0 2006.285.21:22:18.85#ibcon#flushed, iclass 18, count 0 2006.285.21:22:18.85#ibcon#about to write, iclass 18, count 0 2006.285.21:22:18.85#ibcon#wrote, iclass 18, count 0 2006.285.21:22:18.85#ibcon#about to read 3, iclass 18, count 0 2006.285.21:22:18.87#ibcon#read 3, iclass 18, count 0 2006.285.21:22:18.87#ibcon#about to read 4, iclass 18, count 0 2006.285.21:22:18.87#ibcon#read 4, iclass 18, count 0 2006.285.21:22:18.87#ibcon#about to read 5, iclass 18, count 0 2006.285.21:22:18.87#ibcon#read 5, iclass 18, count 0 2006.285.21:22:18.87#ibcon#about to read 6, iclass 18, count 0 2006.285.21:22:18.87#ibcon#read 6, iclass 18, count 0 2006.285.21:22:18.87#ibcon#end of sib2, iclass 18, count 0 2006.285.21:22:18.87#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:22:18.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:22:18.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:22:18.87#ibcon#*before write, iclass 18, count 0 2006.285.21:22:18.87#ibcon#enter sib2, iclass 18, count 0 2006.285.21:22:18.87#ibcon#flushed, iclass 18, count 0 2006.285.21:22:18.87#ibcon#about to write, iclass 18, count 0 2006.285.21:22:18.87#ibcon#wrote, iclass 18, count 0 2006.285.21:22:18.87#ibcon#about to read 3, iclass 18, count 0 2006.285.21:22:18.91#ibcon#read 3, iclass 18, count 0 2006.285.21:22:18.91#ibcon#about to read 4, iclass 18, count 0 2006.285.21:22:18.91#ibcon#read 4, iclass 18, count 0 2006.285.21:22:18.91#ibcon#about to read 5, iclass 18, count 0 2006.285.21:22:18.91#ibcon#read 5, iclass 18, count 0 2006.285.21:22:18.91#ibcon#about to read 6, iclass 18, count 0 2006.285.21:22:18.91#ibcon#read 6, iclass 18, count 0 2006.285.21:22:18.91#ibcon#end of sib2, iclass 18, count 0 2006.285.21:22:18.91#ibcon#*after write, iclass 18, count 0 2006.285.21:22:18.91#ibcon#*before return 0, iclass 18, count 0 2006.285.21:22:18.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:22:18.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:22:18.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:22:18.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:22:18.91$vck44/va=6,4 2006.285.21:22:18.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.21:22:18.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.21:22:18.91#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:18.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:22:18.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:22:18.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:22:18.97#ibcon#enter wrdev, iclass 20, count 2 2006.285.21:22:18.97#ibcon#first serial, iclass 20, count 2 2006.285.21:22:18.97#ibcon#enter sib2, iclass 20, count 2 2006.285.21:22:18.97#ibcon#flushed, iclass 20, count 2 2006.285.21:22:18.97#ibcon#about to write, iclass 20, count 2 2006.285.21:22:18.97#ibcon#wrote, iclass 20, count 2 2006.285.21:22:18.97#ibcon#about to read 3, iclass 20, count 2 2006.285.21:22:18.99#ibcon#read 3, iclass 20, count 2 2006.285.21:22:18.99#ibcon#about to read 4, iclass 20, count 2 2006.285.21:22:18.99#ibcon#read 4, iclass 20, count 2 2006.285.21:22:18.99#ibcon#about to read 5, iclass 20, count 2 2006.285.21:22:18.99#ibcon#read 5, iclass 20, count 2 2006.285.21:22:18.99#ibcon#about to read 6, iclass 20, count 2 2006.285.21:22:18.99#ibcon#read 6, iclass 20, count 2 2006.285.21:22:18.99#ibcon#end of sib2, iclass 20, count 2 2006.285.21:22:18.99#ibcon#*mode == 0, iclass 20, count 2 2006.285.21:22:18.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.21:22:18.99#ibcon#[25=AT06-04\r\n] 2006.285.21:22:18.99#ibcon#*before write, iclass 20, count 2 2006.285.21:22:18.99#ibcon#enter sib2, iclass 20, count 2 2006.285.21:22:18.99#ibcon#flushed, iclass 20, count 2 2006.285.21:22:18.99#ibcon#about to write, iclass 20, count 2 2006.285.21:22:18.99#ibcon#wrote, iclass 20, count 2 2006.285.21:22:18.99#ibcon#about to read 3, iclass 20, count 2 2006.285.21:22:19.02#ibcon#read 3, iclass 20, count 2 2006.285.21:22:19.02#ibcon#about to read 4, iclass 20, count 2 2006.285.21:22:19.02#ibcon#read 4, iclass 20, count 2 2006.285.21:22:19.02#ibcon#about to read 5, iclass 20, count 2 2006.285.21:22:19.02#ibcon#read 5, iclass 20, count 2 2006.285.21:22:19.02#ibcon#about to read 6, iclass 20, count 2 2006.285.21:22:19.02#ibcon#read 6, iclass 20, count 2 2006.285.21:22:19.02#ibcon#end of sib2, iclass 20, count 2 2006.285.21:22:19.02#ibcon#*after write, iclass 20, count 2 2006.285.21:22:19.02#ibcon#*before return 0, iclass 20, count 2 2006.285.21:22:19.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:22:19.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:22:19.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.21:22:19.02#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:19.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:22:19.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:22:19.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:22:19.14#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:22:19.14#ibcon#first serial, iclass 20, count 0 2006.285.21:22:19.14#ibcon#enter sib2, iclass 20, count 0 2006.285.21:22:19.14#ibcon#flushed, iclass 20, count 0 2006.285.21:22:19.14#ibcon#about to write, iclass 20, count 0 2006.285.21:22:19.14#ibcon#wrote, iclass 20, count 0 2006.285.21:22:19.14#ibcon#about to read 3, iclass 20, count 0 2006.285.21:22:19.16#ibcon#read 3, iclass 20, count 0 2006.285.21:22:19.16#ibcon#about to read 4, iclass 20, count 0 2006.285.21:22:19.16#ibcon#read 4, iclass 20, count 0 2006.285.21:22:19.16#ibcon#about to read 5, iclass 20, count 0 2006.285.21:22:19.16#ibcon#read 5, iclass 20, count 0 2006.285.21:22:19.16#ibcon#about to read 6, iclass 20, count 0 2006.285.21:22:19.16#ibcon#read 6, iclass 20, count 0 2006.285.21:22:19.16#ibcon#end of sib2, iclass 20, count 0 2006.285.21:22:19.16#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:22:19.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:22:19.16#ibcon#[25=USB\r\n] 2006.285.21:22:19.16#ibcon#*before write, iclass 20, count 0 2006.285.21:22:19.16#ibcon#enter sib2, iclass 20, count 0 2006.285.21:22:19.16#ibcon#flushed, iclass 20, count 0 2006.285.21:22:19.16#ibcon#about to write, iclass 20, count 0 2006.285.21:22:19.16#ibcon#wrote, iclass 20, count 0 2006.285.21:22:19.16#ibcon#about to read 3, iclass 20, count 0 2006.285.21:22:19.19#ibcon#read 3, iclass 20, count 0 2006.285.21:22:19.19#ibcon#about to read 4, iclass 20, count 0 2006.285.21:22:19.19#ibcon#read 4, iclass 20, count 0 2006.285.21:22:19.19#ibcon#about to read 5, iclass 20, count 0 2006.285.21:22:19.19#ibcon#read 5, iclass 20, count 0 2006.285.21:22:19.19#ibcon#about to read 6, iclass 20, count 0 2006.285.21:22:19.19#ibcon#read 6, iclass 20, count 0 2006.285.21:22:19.19#ibcon#end of sib2, iclass 20, count 0 2006.285.21:22:19.19#ibcon#*after write, iclass 20, count 0 2006.285.21:22:19.19#ibcon#*before return 0, iclass 20, count 0 2006.285.21:22:19.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:22:19.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:22:19.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:22:19.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:22:19.19$vck44/valo=7,864.99 2006.285.21:22:19.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.21:22:19.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.21:22:19.25#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:19.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:22:19.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:22:19.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:22:19.25#ibcon#enter wrdev, iclass 22, count 0 2006.285.21:22:19.25#ibcon#first serial, iclass 22, count 0 2006.285.21:22:19.25#ibcon#enter sib2, iclass 22, count 0 2006.285.21:22:19.25#ibcon#flushed, iclass 22, count 0 2006.285.21:22:19.25#ibcon#about to write, iclass 22, count 0 2006.285.21:22:19.25#ibcon#wrote, iclass 22, count 0 2006.285.21:22:19.25#ibcon#about to read 3, iclass 22, count 0 2006.285.21:22:19.26#ibcon#read 3, iclass 22, count 0 2006.285.21:22:19.26#ibcon#about to read 4, iclass 22, count 0 2006.285.21:22:19.26#ibcon#read 4, iclass 22, count 0 2006.285.21:22:19.26#ibcon#about to read 5, iclass 22, count 0 2006.285.21:22:19.26#ibcon#read 5, iclass 22, count 0 2006.285.21:22:19.26#ibcon#about to read 6, iclass 22, count 0 2006.285.21:22:19.26#ibcon#read 6, iclass 22, count 0 2006.285.21:22:19.26#ibcon#end of sib2, iclass 22, count 0 2006.285.21:22:19.26#ibcon#*mode == 0, iclass 22, count 0 2006.285.21:22:19.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.21:22:19.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:22:19.26#ibcon#*before write, iclass 22, count 0 2006.285.21:22:19.26#ibcon#enter sib2, iclass 22, count 0 2006.285.21:22:19.26#ibcon#flushed, iclass 22, count 0 2006.285.21:22:19.26#ibcon#about to write, iclass 22, count 0 2006.285.21:22:19.26#ibcon#wrote, iclass 22, count 0 2006.285.21:22:19.26#ibcon#about to read 3, iclass 22, count 0 2006.285.21:22:19.30#ibcon#read 3, iclass 22, count 0 2006.285.21:22:19.30#ibcon#about to read 4, iclass 22, count 0 2006.285.21:22:19.30#ibcon#read 4, iclass 22, count 0 2006.285.21:22:19.30#ibcon#about to read 5, iclass 22, count 0 2006.285.21:22:19.30#ibcon#read 5, iclass 22, count 0 2006.285.21:22:19.30#ibcon#about to read 6, iclass 22, count 0 2006.285.21:22:19.30#ibcon#read 6, iclass 22, count 0 2006.285.21:22:19.30#ibcon#end of sib2, iclass 22, count 0 2006.285.21:22:19.30#ibcon#*after write, iclass 22, count 0 2006.285.21:22:19.30#ibcon#*before return 0, iclass 22, count 0 2006.285.21:22:19.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:22:19.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:22:19.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.21:22:19.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.21:22:19.30$vck44/va=7,4 2006.285.21:22:19.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.21:22:19.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.21:22:19.30#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:19.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:22:19.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:22:19.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:22:19.30#ibcon#enter wrdev, iclass 24, count 2 2006.285.21:22:19.30#ibcon#first serial, iclass 24, count 2 2006.285.21:22:19.30#ibcon#enter sib2, iclass 24, count 2 2006.285.21:22:19.30#ibcon#flushed, iclass 24, count 2 2006.285.21:22:19.30#ibcon#about to write, iclass 24, count 2 2006.285.21:22:19.30#ibcon#wrote, iclass 24, count 2 2006.285.21:22:19.30#ibcon#about to read 3, iclass 24, count 2 2006.285.21:22:19.32#ibcon#read 3, iclass 24, count 2 2006.285.21:22:19.32#ibcon#about to read 4, iclass 24, count 2 2006.285.21:22:19.32#ibcon#read 4, iclass 24, count 2 2006.285.21:22:19.32#ibcon#about to read 5, iclass 24, count 2 2006.285.21:22:19.32#ibcon#read 5, iclass 24, count 2 2006.285.21:22:19.32#ibcon#about to read 6, iclass 24, count 2 2006.285.21:22:19.32#ibcon#read 6, iclass 24, count 2 2006.285.21:22:19.32#ibcon#end of sib2, iclass 24, count 2 2006.285.21:22:19.32#ibcon#*mode == 0, iclass 24, count 2 2006.285.21:22:19.32#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.21:22:19.32#ibcon#[25=AT07-04\r\n] 2006.285.21:22:19.32#ibcon#*before write, iclass 24, count 2 2006.285.21:22:19.32#ibcon#enter sib2, iclass 24, count 2 2006.285.21:22:19.32#ibcon#flushed, iclass 24, count 2 2006.285.21:22:19.32#ibcon#about to write, iclass 24, count 2 2006.285.21:22:19.32#ibcon#wrote, iclass 24, count 2 2006.285.21:22:19.32#ibcon#about to read 3, iclass 24, count 2 2006.285.21:22:19.35#ibcon#read 3, iclass 24, count 2 2006.285.21:22:19.35#ibcon#about to read 4, iclass 24, count 2 2006.285.21:22:19.35#ibcon#read 4, iclass 24, count 2 2006.285.21:22:19.35#ibcon#about to read 5, iclass 24, count 2 2006.285.21:22:19.35#ibcon#read 5, iclass 24, count 2 2006.285.21:22:19.35#ibcon#about to read 6, iclass 24, count 2 2006.285.21:22:19.35#ibcon#read 6, iclass 24, count 2 2006.285.21:22:19.35#ibcon#end of sib2, iclass 24, count 2 2006.285.21:22:19.35#ibcon#*after write, iclass 24, count 2 2006.285.21:22:19.35#ibcon#*before return 0, iclass 24, count 2 2006.285.21:22:19.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:22:19.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:22:19.35#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.21:22:19.35#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:19.35#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:22:19.47#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:22:19.47#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:22:19.47#ibcon#enter wrdev, iclass 24, count 0 2006.285.21:22:19.47#ibcon#first serial, iclass 24, count 0 2006.285.21:22:19.47#ibcon#enter sib2, iclass 24, count 0 2006.285.21:22:19.47#ibcon#flushed, iclass 24, count 0 2006.285.21:22:19.47#ibcon#about to write, iclass 24, count 0 2006.285.21:22:19.47#ibcon#wrote, iclass 24, count 0 2006.285.21:22:19.47#ibcon#about to read 3, iclass 24, count 0 2006.285.21:22:19.49#ibcon#read 3, iclass 24, count 0 2006.285.21:22:19.49#ibcon#about to read 4, iclass 24, count 0 2006.285.21:22:19.49#ibcon#read 4, iclass 24, count 0 2006.285.21:22:19.49#ibcon#about to read 5, iclass 24, count 0 2006.285.21:22:19.49#ibcon#read 5, iclass 24, count 0 2006.285.21:22:19.49#ibcon#about to read 6, iclass 24, count 0 2006.285.21:22:19.49#ibcon#read 6, iclass 24, count 0 2006.285.21:22:19.49#ibcon#end of sib2, iclass 24, count 0 2006.285.21:22:19.49#ibcon#*mode == 0, iclass 24, count 0 2006.285.21:22:19.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.21:22:19.49#ibcon#[25=USB\r\n] 2006.285.21:22:19.49#ibcon#*before write, iclass 24, count 0 2006.285.21:22:19.49#ibcon#enter sib2, iclass 24, count 0 2006.285.21:22:19.49#ibcon#flushed, iclass 24, count 0 2006.285.21:22:19.49#ibcon#about to write, iclass 24, count 0 2006.285.21:22:19.49#ibcon#wrote, iclass 24, count 0 2006.285.21:22:19.49#ibcon#about to read 3, iclass 24, count 0 2006.285.21:22:19.52#ibcon#read 3, iclass 24, count 0 2006.285.21:22:19.52#ibcon#about to read 4, iclass 24, count 0 2006.285.21:22:19.52#ibcon#read 4, iclass 24, count 0 2006.285.21:22:19.52#ibcon#about to read 5, iclass 24, count 0 2006.285.21:22:19.52#ibcon#read 5, iclass 24, count 0 2006.285.21:22:19.52#ibcon#about to read 6, iclass 24, count 0 2006.285.21:22:19.52#ibcon#read 6, iclass 24, count 0 2006.285.21:22:19.52#ibcon#end of sib2, iclass 24, count 0 2006.285.21:22:19.52#ibcon#*after write, iclass 24, count 0 2006.285.21:22:19.52#ibcon#*before return 0, iclass 24, count 0 2006.285.21:22:19.52#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:22:19.52#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:22:19.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.21:22:19.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.21:22:19.52$vck44/valo=8,884.99 2006.285.21:22:19.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.21:22:19.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.21:22:19.52#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:19.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:22:19.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:22:19.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:22:19.52#ibcon#enter wrdev, iclass 26, count 0 2006.285.21:22:19.52#ibcon#first serial, iclass 26, count 0 2006.285.21:22:19.52#ibcon#enter sib2, iclass 26, count 0 2006.285.21:22:19.52#ibcon#flushed, iclass 26, count 0 2006.285.21:22:19.52#ibcon#about to write, iclass 26, count 0 2006.285.21:22:19.52#ibcon#wrote, iclass 26, count 0 2006.285.21:22:19.52#ibcon#about to read 3, iclass 26, count 0 2006.285.21:22:19.54#ibcon#read 3, iclass 26, count 0 2006.285.21:22:19.54#ibcon#about to read 4, iclass 26, count 0 2006.285.21:22:19.54#ibcon#read 4, iclass 26, count 0 2006.285.21:22:19.54#ibcon#about to read 5, iclass 26, count 0 2006.285.21:22:19.54#ibcon#read 5, iclass 26, count 0 2006.285.21:22:19.54#ibcon#about to read 6, iclass 26, count 0 2006.285.21:22:19.54#ibcon#read 6, iclass 26, count 0 2006.285.21:22:19.54#ibcon#end of sib2, iclass 26, count 0 2006.285.21:22:19.54#ibcon#*mode == 0, iclass 26, count 0 2006.285.21:22:19.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.21:22:19.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:22:19.54#ibcon#*before write, iclass 26, count 0 2006.285.21:22:19.54#ibcon#enter sib2, iclass 26, count 0 2006.285.21:22:19.54#ibcon#flushed, iclass 26, count 0 2006.285.21:22:19.54#ibcon#about to write, iclass 26, count 0 2006.285.21:22:19.54#ibcon#wrote, iclass 26, count 0 2006.285.21:22:19.54#ibcon#about to read 3, iclass 26, count 0 2006.285.21:22:19.58#ibcon#read 3, iclass 26, count 0 2006.285.21:22:19.58#ibcon#about to read 4, iclass 26, count 0 2006.285.21:22:19.58#ibcon#read 4, iclass 26, count 0 2006.285.21:22:19.58#ibcon#about to read 5, iclass 26, count 0 2006.285.21:22:19.58#ibcon#read 5, iclass 26, count 0 2006.285.21:22:19.58#ibcon#about to read 6, iclass 26, count 0 2006.285.21:22:19.58#ibcon#read 6, iclass 26, count 0 2006.285.21:22:19.58#ibcon#end of sib2, iclass 26, count 0 2006.285.21:22:19.58#ibcon#*after write, iclass 26, count 0 2006.285.21:22:19.58#ibcon#*before return 0, iclass 26, count 0 2006.285.21:22:19.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:22:19.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:22:19.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.21:22:19.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.21:22:19.58$vck44/va=8,3 2006.285.21:22:19.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.21:22:19.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.21:22:19.58#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:19.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:22:19.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:22:19.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:22:19.64#ibcon#enter wrdev, iclass 28, count 2 2006.285.21:22:19.64#ibcon#first serial, iclass 28, count 2 2006.285.21:22:19.64#ibcon#enter sib2, iclass 28, count 2 2006.285.21:22:19.64#ibcon#flushed, iclass 28, count 2 2006.285.21:22:19.64#ibcon#about to write, iclass 28, count 2 2006.285.21:22:19.64#ibcon#wrote, iclass 28, count 2 2006.285.21:22:19.64#ibcon#about to read 3, iclass 28, count 2 2006.285.21:22:19.66#ibcon#read 3, iclass 28, count 2 2006.285.21:22:19.66#ibcon#about to read 4, iclass 28, count 2 2006.285.21:22:19.66#ibcon#read 4, iclass 28, count 2 2006.285.21:22:19.66#ibcon#about to read 5, iclass 28, count 2 2006.285.21:22:19.66#ibcon#read 5, iclass 28, count 2 2006.285.21:22:19.66#ibcon#about to read 6, iclass 28, count 2 2006.285.21:22:19.66#ibcon#read 6, iclass 28, count 2 2006.285.21:22:19.66#ibcon#end of sib2, iclass 28, count 2 2006.285.21:22:19.66#ibcon#*mode == 0, iclass 28, count 2 2006.285.21:22:19.66#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.21:22:19.66#ibcon#[25=AT08-03\r\n] 2006.285.21:22:19.66#ibcon#*before write, iclass 28, count 2 2006.285.21:22:19.66#ibcon#enter sib2, iclass 28, count 2 2006.285.21:22:19.66#ibcon#flushed, iclass 28, count 2 2006.285.21:22:19.66#ibcon#about to write, iclass 28, count 2 2006.285.21:22:19.66#ibcon#wrote, iclass 28, count 2 2006.285.21:22:19.66#ibcon#about to read 3, iclass 28, count 2 2006.285.21:22:19.69#ibcon#read 3, iclass 28, count 2 2006.285.21:22:19.69#ibcon#about to read 4, iclass 28, count 2 2006.285.21:22:19.69#ibcon#read 4, iclass 28, count 2 2006.285.21:22:19.69#ibcon#about to read 5, iclass 28, count 2 2006.285.21:22:19.69#ibcon#read 5, iclass 28, count 2 2006.285.21:22:19.69#ibcon#about to read 6, iclass 28, count 2 2006.285.21:22:19.69#ibcon#read 6, iclass 28, count 2 2006.285.21:22:19.69#ibcon#end of sib2, iclass 28, count 2 2006.285.21:22:19.69#ibcon#*after write, iclass 28, count 2 2006.285.21:22:19.69#ibcon#*before return 0, iclass 28, count 2 2006.285.21:22:19.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:22:19.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:22:19.69#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.21:22:19.69#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:19.69#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:22:19.81#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:22:19.81#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:22:19.81#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:22:19.81#ibcon#first serial, iclass 28, count 0 2006.285.21:22:19.81#ibcon#enter sib2, iclass 28, count 0 2006.285.21:22:19.81#ibcon#flushed, iclass 28, count 0 2006.285.21:22:19.81#ibcon#about to write, iclass 28, count 0 2006.285.21:22:19.81#ibcon#wrote, iclass 28, count 0 2006.285.21:22:19.81#ibcon#about to read 3, iclass 28, count 0 2006.285.21:22:19.83#ibcon#read 3, iclass 28, count 0 2006.285.21:22:19.83#ibcon#about to read 4, iclass 28, count 0 2006.285.21:22:19.83#ibcon#read 4, iclass 28, count 0 2006.285.21:22:19.83#ibcon#about to read 5, iclass 28, count 0 2006.285.21:22:19.83#ibcon#read 5, iclass 28, count 0 2006.285.21:22:19.83#ibcon#about to read 6, iclass 28, count 0 2006.285.21:22:19.83#ibcon#read 6, iclass 28, count 0 2006.285.21:22:19.83#ibcon#end of sib2, iclass 28, count 0 2006.285.21:22:19.83#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:22:19.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:22:19.83#ibcon#[25=USB\r\n] 2006.285.21:22:19.83#ibcon#*before write, iclass 28, count 0 2006.285.21:22:19.83#ibcon#enter sib2, iclass 28, count 0 2006.285.21:22:19.83#ibcon#flushed, iclass 28, count 0 2006.285.21:22:19.83#ibcon#about to write, iclass 28, count 0 2006.285.21:22:19.83#ibcon#wrote, iclass 28, count 0 2006.285.21:22:19.83#ibcon#about to read 3, iclass 28, count 0 2006.285.21:22:19.86#ibcon#read 3, iclass 28, count 0 2006.285.21:22:19.86#ibcon#about to read 4, iclass 28, count 0 2006.285.21:22:19.86#ibcon#read 4, iclass 28, count 0 2006.285.21:22:19.86#ibcon#about to read 5, iclass 28, count 0 2006.285.21:22:19.86#ibcon#read 5, iclass 28, count 0 2006.285.21:22:19.86#ibcon#about to read 6, iclass 28, count 0 2006.285.21:22:19.86#ibcon#read 6, iclass 28, count 0 2006.285.21:22:19.86#ibcon#end of sib2, iclass 28, count 0 2006.285.21:22:19.86#ibcon#*after write, iclass 28, count 0 2006.285.21:22:19.86#ibcon#*before return 0, iclass 28, count 0 2006.285.21:22:19.86#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:22:19.86#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:22:19.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:22:19.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:22:19.86$vck44/vblo=1,629.99 2006.285.21:22:19.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.21:22:19.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.21:22:19.86#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:19.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:22:19.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:22:19.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:22:19.86#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:22:19.86#ibcon#first serial, iclass 30, count 0 2006.285.21:22:19.86#ibcon#enter sib2, iclass 30, count 0 2006.285.21:22:19.86#ibcon#flushed, iclass 30, count 0 2006.285.21:22:19.86#ibcon#about to write, iclass 30, count 0 2006.285.21:22:19.86#ibcon#wrote, iclass 30, count 0 2006.285.21:22:19.86#ibcon#about to read 3, iclass 30, count 0 2006.285.21:22:19.88#ibcon#read 3, iclass 30, count 0 2006.285.21:22:19.88#ibcon#about to read 4, iclass 30, count 0 2006.285.21:22:19.88#ibcon#read 4, iclass 30, count 0 2006.285.21:22:19.88#ibcon#about to read 5, iclass 30, count 0 2006.285.21:22:19.88#ibcon#read 5, iclass 30, count 0 2006.285.21:22:19.88#ibcon#about to read 6, iclass 30, count 0 2006.285.21:22:19.88#ibcon#read 6, iclass 30, count 0 2006.285.21:22:19.88#ibcon#end of sib2, iclass 30, count 0 2006.285.21:22:19.88#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:22:19.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:22:19.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:22:19.88#ibcon#*before write, iclass 30, count 0 2006.285.21:22:19.88#ibcon#enter sib2, iclass 30, count 0 2006.285.21:22:19.88#ibcon#flushed, iclass 30, count 0 2006.285.21:22:19.88#ibcon#about to write, iclass 30, count 0 2006.285.21:22:19.88#ibcon#wrote, iclass 30, count 0 2006.285.21:22:19.88#ibcon#about to read 3, iclass 30, count 0 2006.285.21:22:19.92#ibcon#read 3, iclass 30, count 0 2006.285.21:22:19.92#ibcon#about to read 4, iclass 30, count 0 2006.285.21:22:19.92#ibcon#read 4, iclass 30, count 0 2006.285.21:22:19.92#ibcon#about to read 5, iclass 30, count 0 2006.285.21:22:19.92#ibcon#read 5, iclass 30, count 0 2006.285.21:22:19.92#ibcon#about to read 6, iclass 30, count 0 2006.285.21:22:19.92#ibcon#read 6, iclass 30, count 0 2006.285.21:22:19.92#ibcon#end of sib2, iclass 30, count 0 2006.285.21:22:19.92#ibcon#*after write, iclass 30, count 0 2006.285.21:22:19.92#ibcon#*before return 0, iclass 30, count 0 2006.285.21:22:19.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:22:19.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:22:19.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:22:19.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:22:19.92$vck44/vb=1,4 2006.285.21:22:19.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.21:22:19.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.21:22:19.92#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:19.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:22:19.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:22:19.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:22:19.92#ibcon#enter wrdev, iclass 32, count 2 2006.285.21:22:19.92#ibcon#first serial, iclass 32, count 2 2006.285.21:22:19.92#ibcon#enter sib2, iclass 32, count 2 2006.285.21:22:19.92#ibcon#flushed, iclass 32, count 2 2006.285.21:22:19.92#ibcon#about to write, iclass 32, count 2 2006.285.21:22:19.92#ibcon#wrote, iclass 32, count 2 2006.285.21:22:19.92#ibcon#about to read 3, iclass 32, count 2 2006.285.21:22:19.94#ibcon#read 3, iclass 32, count 2 2006.285.21:22:19.94#ibcon#about to read 4, iclass 32, count 2 2006.285.21:22:19.94#ibcon#read 4, iclass 32, count 2 2006.285.21:22:19.94#ibcon#about to read 5, iclass 32, count 2 2006.285.21:22:19.94#ibcon#read 5, iclass 32, count 2 2006.285.21:22:19.94#ibcon#about to read 6, iclass 32, count 2 2006.285.21:22:19.94#ibcon#read 6, iclass 32, count 2 2006.285.21:22:19.94#ibcon#end of sib2, iclass 32, count 2 2006.285.21:22:19.94#ibcon#*mode == 0, iclass 32, count 2 2006.285.21:22:19.94#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.21:22:19.94#ibcon#[27=AT01-04\r\n] 2006.285.21:22:19.94#ibcon#*before write, iclass 32, count 2 2006.285.21:22:19.94#ibcon#enter sib2, iclass 32, count 2 2006.285.21:22:19.94#ibcon#flushed, iclass 32, count 2 2006.285.21:22:19.94#ibcon#about to write, iclass 32, count 2 2006.285.21:22:19.94#ibcon#wrote, iclass 32, count 2 2006.285.21:22:19.94#ibcon#about to read 3, iclass 32, count 2 2006.285.21:22:19.97#ibcon#read 3, iclass 32, count 2 2006.285.21:22:19.97#ibcon#about to read 4, iclass 32, count 2 2006.285.21:22:19.97#ibcon#read 4, iclass 32, count 2 2006.285.21:22:19.97#ibcon#about to read 5, iclass 32, count 2 2006.285.21:22:19.97#ibcon#read 5, iclass 32, count 2 2006.285.21:22:19.97#ibcon#about to read 6, iclass 32, count 2 2006.285.21:22:19.97#ibcon#read 6, iclass 32, count 2 2006.285.21:22:19.97#ibcon#end of sib2, iclass 32, count 2 2006.285.21:22:19.97#ibcon#*after write, iclass 32, count 2 2006.285.21:22:19.97#ibcon#*before return 0, iclass 32, count 2 2006.285.21:22:19.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:22:19.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:22:19.97#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.21:22:19.97#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:19.97#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:22:20.09#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:22:20.09#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:22:20.09#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:22:20.09#ibcon#first serial, iclass 32, count 0 2006.285.21:22:20.09#ibcon#enter sib2, iclass 32, count 0 2006.285.21:22:20.09#ibcon#flushed, iclass 32, count 0 2006.285.21:22:20.09#ibcon#about to write, iclass 32, count 0 2006.285.21:22:20.09#ibcon#wrote, iclass 32, count 0 2006.285.21:22:20.09#ibcon#about to read 3, iclass 32, count 0 2006.285.21:22:20.11#ibcon#read 3, iclass 32, count 0 2006.285.21:22:20.11#ibcon#about to read 4, iclass 32, count 0 2006.285.21:22:20.11#ibcon#read 4, iclass 32, count 0 2006.285.21:22:20.11#ibcon#about to read 5, iclass 32, count 0 2006.285.21:22:20.11#ibcon#read 5, iclass 32, count 0 2006.285.21:22:20.11#ibcon#about to read 6, iclass 32, count 0 2006.285.21:22:20.11#ibcon#read 6, iclass 32, count 0 2006.285.21:22:20.11#ibcon#end of sib2, iclass 32, count 0 2006.285.21:22:20.11#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:22:20.11#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:22:20.11#ibcon#[27=USB\r\n] 2006.285.21:22:20.11#ibcon#*before write, iclass 32, count 0 2006.285.21:22:20.11#ibcon#enter sib2, iclass 32, count 0 2006.285.21:22:20.11#ibcon#flushed, iclass 32, count 0 2006.285.21:22:20.11#ibcon#about to write, iclass 32, count 0 2006.285.21:22:20.11#ibcon#wrote, iclass 32, count 0 2006.285.21:22:20.11#ibcon#about to read 3, iclass 32, count 0 2006.285.21:22:20.14#ibcon#read 3, iclass 32, count 0 2006.285.21:22:20.14#ibcon#about to read 4, iclass 32, count 0 2006.285.21:22:20.14#ibcon#read 4, iclass 32, count 0 2006.285.21:22:20.14#ibcon#about to read 5, iclass 32, count 0 2006.285.21:22:20.14#ibcon#read 5, iclass 32, count 0 2006.285.21:22:20.14#ibcon#about to read 6, iclass 32, count 0 2006.285.21:22:20.14#ibcon#read 6, iclass 32, count 0 2006.285.21:22:20.14#ibcon#end of sib2, iclass 32, count 0 2006.285.21:22:20.14#ibcon#*after write, iclass 32, count 0 2006.285.21:22:20.14#ibcon#*before return 0, iclass 32, count 0 2006.285.21:22:20.14#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:22:20.14#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:22:20.14#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:22:20.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:22:20.14$vck44/vblo=2,634.99 2006.285.21:22:20.14#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.21:22:20.14#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.21:22:20.14#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:20.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:22:20.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:22:20.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:22:20.15#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:22:20.15#ibcon#first serial, iclass 34, count 0 2006.285.21:22:20.15#ibcon#enter sib2, iclass 34, count 0 2006.285.21:22:20.15#ibcon#flushed, iclass 34, count 0 2006.285.21:22:20.15#ibcon#about to write, iclass 34, count 0 2006.285.21:22:20.15#ibcon#wrote, iclass 34, count 0 2006.285.21:22:20.15#ibcon#about to read 3, iclass 34, count 0 2006.285.21:22:20.16#ibcon#read 3, iclass 34, count 0 2006.285.21:22:20.23#ibcon#about to read 4, iclass 34, count 0 2006.285.21:22:20.23#ibcon#read 4, iclass 34, count 0 2006.285.21:22:20.23#ibcon#about to read 5, iclass 34, count 0 2006.285.21:22:20.23#ibcon#read 5, iclass 34, count 0 2006.285.21:22:20.23#ibcon#about to read 6, iclass 34, count 0 2006.285.21:22:20.23#ibcon#read 6, iclass 34, count 0 2006.285.21:22:20.23#ibcon#end of sib2, iclass 34, count 0 2006.285.21:22:20.23#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:22:20.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:22:20.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:22:20.23#ibcon#*before write, iclass 34, count 0 2006.285.21:22:20.23#ibcon#enter sib2, iclass 34, count 0 2006.285.21:22:20.23#ibcon#flushed, iclass 34, count 0 2006.285.21:22:20.23#ibcon#about to write, iclass 34, count 0 2006.285.21:22:20.23#ibcon#wrote, iclass 34, count 0 2006.285.21:22:20.23#ibcon#about to read 3, iclass 34, count 0 2006.285.21:22:20.27#ibcon#read 3, iclass 34, count 0 2006.285.21:22:20.27#ibcon#about to read 4, iclass 34, count 0 2006.285.21:22:20.27#ibcon#read 4, iclass 34, count 0 2006.285.21:22:20.27#ibcon#about to read 5, iclass 34, count 0 2006.285.21:22:20.27#ibcon#read 5, iclass 34, count 0 2006.285.21:22:20.27#ibcon#about to read 6, iclass 34, count 0 2006.285.21:22:20.27#ibcon#read 6, iclass 34, count 0 2006.285.21:22:20.27#ibcon#end of sib2, iclass 34, count 0 2006.285.21:22:20.27#ibcon#*after write, iclass 34, count 0 2006.285.21:22:20.27#ibcon#*before return 0, iclass 34, count 0 2006.285.21:22:20.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:22:20.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:22:20.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:22:20.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:22:20.27$vck44/vb=2,5 2006.285.21:22:20.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.21:22:20.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.21:22:20.27#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:20.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:22:20.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:22:20.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:22:20.27#ibcon#enter wrdev, iclass 36, count 2 2006.285.21:22:20.27#ibcon#first serial, iclass 36, count 2 2006.285.21:22:20.27#ibcon#enter sib2, iclass 36, count 2 2006.285.21:22:20.27#ibcon#flushed, iclass 36, count 2 2006.285.21:22:20.27#ibcon#about to write, iclass 36, count 2 2006.285.21:22:20.27#ibcon#wrote, iclass 36, count 2 2006.285.21:22:20.27#ibcon#about to read 3, iclass 36, count 2 2006.285.21:22:20.29#ibcon#read 3, iclass 36, count 2 2006.285.21:22:20.29#ibcon#about to read 4, iclass 36, count 2 2006.285.21:22:20.29#ibcon#read 4, iclass 36, count 2 2006.285.21:22:20.29#ibcon#about to read 5, iclass 36, count 2 2006.285.21:22:20.29#ibcon#read 5, iclass 36, count 2 2006.285.21:22:20.29#ibcon#about to read 6, iclass 36, count 2 2006.285.21:22:20.29#ibcon#read 6, iclass 36, count 2 2006.285.21:22:20.29#ibcon#end of sib2, iclass 36, count 2 2006.285.21:22:20.29#ibcon#*mode == 0, iclass 36, count 2 2006.285.21:22:20.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.21:22:20.29#ibcon#[27=AT02-05\r\n] 2006.285.21:22:20.29#ibcon#*before write, iclass 36, count 2 2006.285.21:22:20.29#ibcon#enter sib2, iclass 36, count 2 2006.285.21:22:20.29#ibcon#flushed, iclass 36, count 2 2006.285.21:22:20.29#ibcon#about to write, iclass 36, count 2 2006.285.21:22:20.29#ibcon#wrote, iclass 36, count 2 2006.285.21:22:20.29#ibcon#about to read 3, iclass 36, count 2 2006.285.21:22:20.32#ibcon#read 3, iclass 36, count 2 2006.285.21:22:20.32#ibcon#about to read 4, iclass 36, count 2 2006.285.21:22:20.32#ibcon#read 4, iclass 36, count 2 2006.285.21:22:20.32#ibcon#about to read 5, iclass 36, count 2 2006.285.21:22:20.32#ibcon#read 5, iclass 36, count 2 2006.285.21:22:20.32#ibcon#about to read 6, iclass 36, count 2 2006.285.21:22:20.32#ibcon#read 6, iclass 36, count 2 2006.285.21:22:20.32#ibcon#end of sib2, iclass 36, count 2 2006.285.21:22:20.32#ibcon#*after write, iclass 36, count 2 2006.285.21:22:20.32#ibcon#*before return 0, iclass 36, count 2 2006.285.21:22:20.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:22:20.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:22:20.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.21:22:20.32#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:20.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:22:20.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:22:20.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:22:20.44#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:22:20.44#ibcon#first serial, iclass 36, count 0 2006.285.21:22:20.44#ibcon#enter sib2, iclass 36, count 0 2006.285.21:22:20.44#ibcon#flushed, iclass 36, count 0 2006.285.21:22:20.44#ibcon#about to write, iclass 36, count 0 2006.285.21:22:20.44#ibcon#wrote, iclass 36, count 0 2006.285.21:22:20.44#ibcon#about to read 3, iclass 36, count 0 2006.285.21:22:20.46#ibcon#read 3, iclass 36, count 0 2006.285.21:22:20.46#ibcon#about to read 4, iclass 36, count 0 2006.285.21:22:20.46#ibcon#read 4, iclass 36, count 0 2006.285.21:22:20.46#ibcon#about to read 5, iclass 36, count 0 2006.285.21:22:20.46#ibcon#read 5, iclass 36, count 0 2006.285.21:22:20.46#ibcon#about to read 6, iclass 36, count 0 2006.285.21:22:20.46#ibcon#read 6, iclass 36, count 0 2006.285.21:22:20.46#ibcon#end of sib2, iclass 36, count 0 2006.285.21:22:20.46#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:22:20.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:22:20.46#ibcon#[27=USB\r\n] 2006.285.21:22:20.46#ibcon#*before write, iclass 36, count 0 2006.285.21:22:20.46#ibcon#enter sib2, iclass 36, count 0 2006.285.21:22:20.46#ibcon#flushed, iclass 36, count 0 2006.285.21:22:20.46#ibcon#about to write, iclass 36, count 0 2006.285.21:22:20.46#ibcon#wrote, iclass 36, count 0 2006.285.21:22:20.46#ibcon#about to read 3, iclass 36, count 0 2006.285.21:22:20.49#ibcon#read 3, iclass 36, count 0 2006.285.21:22:20.49#ibcon#about to read 4, iclass 36, count 0 2006.285.21:22:20.49#ibcon#read 4, iclass 36, count 0 2006.285.21:22:20.49#ibcon#about to read 5, iclass 36, count 0 2006.285.21:22:20.49#ibcon#read 5, iclass 36, count 0 2006.285.21:22:20.49#ibcon#about to read 6, iclass 36, count 0 2006.285.21:22:20.49#ibcon#read 6, iclass 36, count 0 2006.285.21:22:20.49#ibcon#end of sib2, iclass 36, count 0 2006.285.21:22:20.49#ibcon#*after write, iclass 36, count 0 2006.285.21:22:20.49#ibcon#*before return 0, iclass 36, count 0 2006.285.21:22:20.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:22:20.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:22:20.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:22:20.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:22:20.49$vck44/vblo=3,649.99 2006.285.21:22:20.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.21:22:20.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.21:22:20.49#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:20.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:22:20.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:22:20.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:22:20.49#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:22:20.49#ibcon#first serial, iclass 38, count 0 2006.285.21:22:20.49#ibcon#enter sib2, iclass 38, count 0 2006.285.21:22:20.49#ibcon#flushed, iclass 38, count 0 2006.285.21:22:20.49#ibcon#about to write, iclass 38, count 0 2006.285.21:22:20.49#ibcon#wrote, iclass 38, count 0 2006.285.21:22:20.49#ibcon#about to read 3, iclass 38, count 0 2006.285.21:22:20.51#ibcon#read 3, iclass 38, count 0 2006.285.21:22:20.51#ibcon#about to read 4, iclass 38, count 0 2006.285.21:22:20.51#ibcon#read 4, iclass 38, count 0 2006.285.21:22:20.51#ibcon#about to read 5, iclass 38, count 0 2006.285.21:22:20.51#ibcon#read 5, iclass 38, count 0 2006.285.21:22:20.51#ibcon#about to read 6, iclass 38, count 0 2006.285.21:22:20.51#ibcon#read 6, iclass 38, count 0 2006.285.21:22:20.51#ibcon#end of sib2, iclass 38, count 0 2006.285.21:22:20.51#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:22:20.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:22:20.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:22:20.51#ibcon#*before write, iclass 38, count 0 2006.285.21:22:20.51#ibcon#enter sib2, iclass 38, count 0 2006.285.21:22:20.51#ibcon#flushed, iclass 38, count 0 2006.285.21:22:20.51#ibcon#about to write, iclass 38, count 0 2006.285.21:22:20.51#ibcon#wrote, iclass 38, count 0 2006.285.21:22:20.51#ibcon#about to read 3, iclass 38, count 0 2006.285.21:22:20.55#ibcon#read 3, iclass 38, count 0 2006.285.21:22:20.55#ibcon#about to read 4, iclass 38, count 0 2006.285.21:22:20.55#ibcon#read 4, iclass 38, count 0 2006.285.21:22:20.55#ibcon#about to read 5, iclass 38, count 0 2006.285.21:22:20.55#ibcon#read 5, iclass 38, count 0 2006.285.21:22:20.55#ibcon#about to read 6, iclass 38, count 0 2006.285.21:22:20.55#ibcon#read 6, iclass 38, count 0 2006.285.21:22:20.55#ibcon#end of sib2, iclass 38, count 0 2006.285.21:22:20.55#ibcon#*after write, iclass 38, count 0 2006.285.21:22:20.55#ibcon#*before return 0, iclass 38, count 0 2006.285.21:22:20.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:22:20.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:22:20.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:22:20.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:22:20.55$vck44/vb=3,4 2006.285.21:22:20.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.21:22:20.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.21:22:20.55#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:20.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:22:20.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:22:20.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:22:20.61#ibcon#enter wrdev, iclass 40, count 2 2006.285.21:22:20.61#ibcon#first serial, iclass 40, count 2 2006.285.21:22:20.61#ibcon#enter sib2, iclass 40, count 2 2006.285.21:22:20.61#ibcon#flushed, iclass 40, count 2 2006.285.21:22:20.61#ibcon#about to write, iclass 40, count 2 2006.285.21:22:20.61#ibcon#wrote, iclass 40, count 2 2006.285.21:22:20.61#ibcon#about to read 3, iclass 40, count 2 2006.285.21:22:20.63#ibcon#read 3, iclass 40, count 2 2006.285.21:22:20.63#ibcon#about to read 4, iclass 40, count 2 2006.285.21:22:20.63#ibcon#read 4, iclass 40, count 2 2006.285.21:22:20.63#ibcon#about to read 5, iclass 40, count 2 2006.285.21:22:20.63#ibcon#read 5, iclass 40, count 2 2006.285.21:22:20.63#ibcon#about to read 6, iclass 40, count 2 2006.285.21:22:20.63#ibcon#read 6, iclass 40, count 2 2006.285.21:22:20.63#ibcon#end of sib2, iclass 40, count 2 2006.285.21:22:20.63#ibcon#*mode == 0, iclass 40, count 2 2006.285.21:22:20.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.21:22:20.63#ibcon#[27=AT03-04\r\n] 2006.285.21:22:20.63#ibcon#*before write, iclass 40, count 2 2006.285.21:22:20.63#ibcon#enter sib2, iclass 40, count 2 2006.285.21:22:20.63#ibcon#flushed, iclass 40, count 2 2006.285.21:22:20.63#ibcon#about to write, iclass 40, count 2 2006.285.21:22:20.63#ibcon#wrote, iclass 40, count 2 2006.285.21:22:20.63#ibcon#about to read 3, iclass 40, count 2 2006.285.21:22:20.66#ibcon#read 3, iclass 40, count 2 2006.285.21:22:20.66#ibcon#about to read 4, iclass 40, count 2 2006.285.21:22:20.66#ibcon#read 4, iclass 40, count 2 2006.285.21:22:20.66#ibcon#about to read 5, iclass 40, count 2 2006.285.21:22:20.66#ibcon#read 5, iclass 40, count 2 2006.285.21:22:20.66#ibcon#about to read 6, iclass 40, count 2 2006.285.21:22:20.66#ibcon#read 6, iclass 40, count 2 2006.285.21:22:20.66#ibcon#end of sib2, iclass 40, count 2 2006.285.21:22:20.66#ibcon#*after write, iclass 40, count 2 2006.285.21:22:20.66#ibcon#*before return 0, iclass 40, count 2 2006.285.21:22:20.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:22:20.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:22:20.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.21:22:20.66#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:20.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:22:20.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:22:20.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:22:20.78#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:22:20.78#ibcon#first serial, iclass 40, count 0 2006.285.21:22:20.78#ibcon#enter sib2, iclass 40, count 0 2006.285.21:22:20.78#ibcon#flushed, iclass 40, count 0 2006.285.21:22:20.78#ibcon#about to write, iclass 40, count 0 2006.285.21:22:20.78#ibcon#wrote, iclass 40, count 0 2006.285.21:22:20.78#ibcon#about to read 3, iclass 40, count 0 2006.285.21:22:20.80#ibcon#read 3, iclass 40, count 0 2006.285.21:22:20.80#ibcon#about to read 4, iclass 40, count 0 2006.285.21:22:20.80#ibcon#read 4, iclass 40, count 0 2006.285.21:22:20.80#ibcon#about to read 5, iclass 40, count 0 2006.285.21:22:20.80#ibcon#read 5, iclass 40, count 0 2006.285.21:22:20.80#ibcon#about to read 6, iclass 40, count 0 2006.285.21:22:20.80#ibcon#read 6, iclass 40, count 0 2006.285.21:22:20.80#ibcon#end of sib2, iclass 40, count 0 2006.285.21:22:20.80#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:22:20.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:22:20.80#ibcon#[27=USB\r\n] 2006.285.21:22:20.80#ibcon#*before write, iclass 40, count 0 2006.285.21:22:20.80#ibcon#enter sib2, iclass 40, count 0 2006.285.21:22:20.80#ibcon#flushed, iclass 40, count 0 2006.285.21:22:20.80#ibcon#about to write, iclass 40, count 0 2006.285.21:22:20.80#ibcon#wrote, iclass 40, count 0 2006.285.21:22:20.80#ibcon#about to read 3, iclass 40, count 0 2006.285.21:22:20.83#ibcon#read 3, iclass 40, count 0 2006.285.21:22:20.83#ibcon#about to read 4, iclass 40, count 0 2006.285.21:22:20.83#ibcon#read 4, iclass 40, count 0 2006.285.21:22:20.83#ibcon#about to read 5, iclass 40, count 0 2006.285.21:22:20.83#ibcon#read 5, iclass 40, count 0 2006.285.21:22:20.83#ibcon#about to read 6, iclass 40, count 0 2006.285.21:22:20.83#ibcon#read 6, iclass 40, count 0 2006.285.21:22:20.83#ibcon#end of sib2, iclass 40, count 0 2006.285.21:22:20.83#ibcon#*after write, iclass 40, count 0 2006.285.21:22:20.83#ibcon#*before return 0, iclass 40, count 0 2006.285.21:22:20.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:22:20.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:22:20.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:22:20.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:22:20.83$vck44/vblo=4,679.99 2006.285.21:22:20.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.21:22:20.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.21:22:20.83#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:20.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:22:20.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:22:20.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:22:20.83#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:22:20.83#ibcon#first serial, iclass 4, count 0 2006.285.21:22:20.83#ibcon#enter sib2, iclass 4, count 0 2006.285.21:22:20.83#ibcon#flushed, iclass 4, count 0 2006.285.21:22:20.83#ibcon#about to write, iclass 4, count 0 2006.285.21:22:20.83#ibcon#wrote, iclass 4, count 0 2006.285.21:22:20.83#ibcon#about to read 3, iclass 4, count 0 2006.285.21:22:20.85#ibcon#read 3, iclass 4, count 0 2006.285.21:22:20.85#ibcon#about to read 4, iclass 4, count 0 2006.285.21:22:20.85#ibcon#read 4, iclass 4, count 0 2006.285.21:22:20.85#ibcon#about to read 5, iclass 4, count 0 2006.285.21:22:20.85#ibcon#read 5, iclass 4, count 0 2006.285.21:22:20.85#ibcon#about to read 6, iclass 4, count 0 2006.285.21:22:20.85#ibcon#read 6, iclass 4, count 0 2006.285.21:22:20.85#ibcon#end of sib2, iclass 4, count 0 2006.285.21:22:20.85#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:22:20.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:22:20.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:22:20.85#ibcon#*before write, iclass 4, count 0 2006.285.21:22:20.85#ibcon#enter sib2, iclass 4, count 0 2006.285.21:22:20.85#ibcon#flushed, iclass 4, count 0 2006.285.21:22:20.85#ibcon#about to write, iclass 4, count 0 2006.285.21:22:20.85#ibcon#wrote, iclass 4, count 0 2006.285.21:22:20.85#ibcon#about to read 3, iclass 4, count 0 2006.285.21:22:20.89#ibcon#read 3, iclass 4, count 0 2006.285.21:22:20.89#ibcon#about to read 4, iclass 4, count 0 2006.285.21:22:20.89#ibcon#read 4, iclass 4, count 0 2006.285.21:22:20.89#ibcon#about to read 5, iclass 4, count 0 2006.285.21:22:20.89#ibcon#read 5, iclass 4, count 0 2006.285.21:22:20.89#ibcon#about to read 6, iclass 4, count 0 2006.285.21:22:20.89#ibcon#read 6, iclass 4, count 0 2006.285.21:22:20.89#ibcon#end of sib2, iclass 4, count 0 2006.285.21:22:20.89#ibcon#*after write, iclass 4, count 0 2006.285.21:22:20.89#ibcon#*before return 0, iclass 4, count 0 2006.285.21:22:20.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:22:20.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:22:20.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:22:20.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:22:20.89$vck44/vb=4,5 2006.285.21:22:20.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.21:22:20.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.21:22:20.89#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:20.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:22:20.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:22:20.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:22:20.95#ibcon#enter wrdev, iclass 6, count 2 2006.285.21:22:20.95#ibcon#first serial, iclass 6, count 2 2006.285.21:22:20.95#ibcon#enter sib2, iclass 6, count 2 2006.285.21:22:20.95#ibcon#flushed, iclass 6, count 2 2006.285.21:22:20.95#ibcon#about to write, iclass 6, count 2 2006.285.21:22:20.95#ibcon#wrote, iclass 6, count 2 2006.285.21:22:20.95#ibcon#about to read 3, iclass 6, count 2 2006.285.21:22:20.97#ibcon#read 3, iclass 6, count 2 2006.285.21:22:20.97#ibcon#about to read 4, iclass 6, count 2 2006.285.21:22:20.97#ibcon#read 4, iclass 6, count 2 2006.285.21:22:20.97#ibcon#about to read 5, iclass 6, count 2 2006.285.21:22:20.97#ibcon#read 5, iclass 6, count 2 2006.285.21:22:20.97#ibcon#about to read 6, iclass 6, count 2 2006.285.21:22:20.97#ibcon#read 6, iclass 6, count 2 2006.285.21:22:20.97#ibcon#end of sib2, iclass 6, count 2 2006.285.21:22:20.97#ibcon#*mode == 0, iclass 6, count 2 2006.285.21:22:20.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.21:22:20.97#ibcon#[27=AT04-05\r\n] 2006.285.21:22:20.97#ibcon#*before write, iclass 6, count 2 2006.285.21:22:20.97#ibcon#enter sib2, iclass 6, count 2 2006.285.21:22:20.97#ibcon#flushed, iclass 6, count 2 2006.285.21:22:20.97#ibcon#about to write, iclass 6, count 2 2006.285.21:22:20.97#ibcon#wrote, iclass 6, count 2 2006.285.21:22:20.97#ibcon#about to read 3, iclass 6, count 2 2006.285.21:22:21.00#ibcon#read 3, iclass 6, count 2 2006.285.21:22:21.00#ibcon#about to read 4, iclass 6, count 2 2006.285.21:22:21.00#ibcon#read 4, iclass 6, count 2 2006.285.21:22:21.00#ibcon#about to read 5, iclass 6, count 2 2006.285.21:22:21.00#ibcon#read 5, iclass 6, count 2 2006.285.21:22:21.00#ibcon#about to read 6, iclass 6, count 2 2006.285.21:22:21.00#ibcon#read 6, iclass 6, count 2 2006.285.21:22:21.00#ibcon#end of sib2, iclass 6, count 2 2006.285.21:22:21.00#ibcon#*after write, iclass 6, count 2 2006.285.21:22:21.00#ibcon#*before return 0, iclass 6, count 2 2006.285.21:22:21.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:22:21.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:22:21.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.21:22:21.00#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:21.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:22:21.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:22:21.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:22:21.12#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:22:21.12#ibcon#first serial, iclass 6, count 0 2006.285.21:22:21.12#ibcon#enter sib2, iclass 6, count 0 2006.285.21:22:21.12#ibcon#flushed, iclass 6, count 0 2006.285.21:22:21.12#ibcon#about to write, iclass 6, count 0 2006.285.21:22:21.12#ibcon#wrote, iclass 6, count 0 2006.285.21:22:21.12#ibcon#about to read 3, iclass 6, count 0 2006.285.21:22:21.14#ibcon#read 3, iclass 6, count 0 2006.285.21:22:21.14#ibcon#about to read 4, iclass 6, count 0 2006.285.21:22:21.14#ibcon#read 4, iclass 6, count 0 2006.285.21:22:21.14#ibcon#about to read 5, iclass 6, count 0 2006.285.21:22:21.14#ibcon#read 5, iclass 6, count 0 2006.285.21:22:21.14#ibcon#about to read 6, iclass 6, count 0 2006.285.21:22:21.14#ibcon#read 6, iclass 6, count 0 2006.285.21:22:21.14#ibcon#end of sib2, iclass 6, count 0 2006.285.21:22:21.14#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:22:21.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:22:21.14#ibcon#[27=USB\r\n] 2006.285.21:22:21.14#ibcon#*before write, iclass 6, count 0 2006.285.21:22:21.14#ibcon#enter sib2, iclass 6, count 0 2006.285.21:22:21.14#ibcon#flushed, iclass 6, count 0 2006.285.21:22:21.14#ibcon#about to write, iclass 6, count 0 2006.285.21:22:21.14#ibcon#wrote, iclass 6, count 0 2006.285.21:22:21.14#ibcon#about to read 3, iclass 6, count 0 2006.285.21:22:21.17#ibcon#read 3, iclass 6, count 0 2006.285.21:22:21.17#ibcon#about to read 4, iclass 6, count 0 2006.285.21:22:21.17#ibcon#read 4, iclass 6, count 0 2006.285.21:22:21.17#ibcon#about to read 5, iclass 6, count 0 2006.285.21:22:21.17#ibcon#read 5, iclass 6, count 0 2006.285.21:22:21.17#ibcon#about to read 6, iclass 6, count 0 2006.285.21:22:21.17#ibcon#read 6, iclass 6, count 0 2006.285.21:22:21.17#ibcon#end of sib2, iclass 6, count 0 2006.285.21:22:21.17#ibcon#*after write, iclass 6, count 0 2006.285.21:22:21.17#ibcon#*before return 0, iclass 6, count 0 2006.285.21:22:21.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:22:21.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:22:21.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:22:21.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:22:21.17$vck44/vblo=5,709.99 2006.285.21:22:21.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.21:22:21.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.21:22:21.17#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:21.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:22:21.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:22:21.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:22:21.17#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:22:21.17#ibcon#first serial, iclass 10, count 0 2006.285.21:22:21.17#ibcon#enter sib2, iclass 10, count 0 2006.285.21:22:21.17#ibcon#flushed, iclass 10, count 0 2006.285.21:22:21.17#ibcon#about to write, iclass 10, count 0 2006.285.21:22:21.17#ibcon#wrote, iclass 10, count 0 2006.285.21:22:21.17#ibcon#about to read 3, iclass 10, count 0 2006.285.21:22:21.19#ibcon#read 3, iclass 10, count 0 2006.285.21:22:21.31#ibcon#about to read 4, iclass 10, count 0 2006.285.21:22:21.31#ibcon#read 4, iclass 10, count 0 2006.285.21:22:21.31#ibcon#about to read 5, iclass 10, count 0 2006.285.21:22:21.31#ibcon#read 5, iclass 10, count 0 2006.285.21:22:21.31#ibcon#about to read 6, iclass 10, count 0 2006.285.21:22:21.31#ibcon#read 6, iclass 10, count 0 2006.285.21:22:21.31#ibcon#end of sib2, iclass 10, count 0 2006.285.21:22:21.31#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:22:21.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:22:21.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:22:21.31#ibcon#*before write, iclass 10, count 0 2006.285.21:22:21.31#ibcon#enter sib2, iclass 10, count 0 2006.285.21:22:21.31#ibcon#flushed, iclass 10, count 0 2006.285.21:22:21.31#ibcon#about to write, iclass 10, count 0 2006.285.21:22:21.31#ibcon#wrote, iclass 10, count 0 2006.285.21:22:21.31#ibcon#about to read 3, iclass 10, count 0 2006.285.21:22:21.34#ibcon#read 3, iclass 10, count 0 2006.285.21:22:21.34#ibcon#about to read 4, iclass 10, count 0 2006.285.21:22:21.34#ibcon#read 4, iclass 10, count 0 2006.285.21:22:21.34#ibcon#about to read 5, iclass 10, count 0 2006.285.21:22:21.34#ibcon#read 5, iclass 10, count 0 2006.285.21:22:21.34#ibcon#about to read 6, iclass 10, count 0 2006.285.21:22:21.34#ibcon#read 6, iclass 10, count 0 2006.285.21:22:21.34#ibcon#end of sib2, iclass 10, count 0 2006.285.21:22:21.34#ibcon#*after write, iclass 10, count 0 2006.285.21:22:21.34#ibcon#*before return 0, iclass 10, count 0 2006.285.21:22:21.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:22:21.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:22:21.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:22:21.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:22:21.34$vck44/vb=5,4 2006.285.21:22:21.34#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.21:22:21.34#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.21:22:21.34#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:21.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:22:21.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:22:21.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:22:21.34#ibcon#enter wrdev, iclass 12, count 2 2006.285.21:22:21.34#ibcon#first serial, iclass 12, count 2 2006.285.21:22:21.34#ibcon#enter sib2, iclass 12, count 2 2006.285.21:22:21.34#ibcon#flushed, iclass 12, count 2 2006.285.21:22:21.34#ibcon#about to write, iclass 12, count 2 2006.285.21:22:21.34#ibcon#wrote, iclass 12, count 2 2006.285.21:22:21.34#ibcon#about to read 3, iclass 12, count 2 2006.285.21:22:21.36#ibcon#read 3, iclass 12, count 2 2006.285.21:22:21.36#ibcon#about to read 4, iclass 12, count 2 2006.285.21:22:21.36#ibcon#read 4, iclass 12, count 2 2006.285.21:22:21.36#ibcon#about to read 5, iclass 12, count 2 2006.285.21:22:21.36#ibcon#read 5, iclass 12, count 2 2006.285.21:22:21.36#ibcon#about to read 6, iclass 12, count 2 2006.285.21:22:21.36#ibcon#read 6, iclass 12, count 2 2006.285.21:22:21.36#ibcon#end of sib2, iclass 12, count 2 2006.285.21:22:21.36#ibcon#*mode == 0, iclass 12, count 2 2006.285.21:22:21.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.21:22:21.36#ibcon#[27=AT05-04\r\n] 2006.285.21:22:21.36#ibcon#*before write, iclass 12, count 2 2006.285.21:22:21.36#ibcon#enter sib2, iclass 12, count 2 2006.285.21:22:21.36#ibcon#flushed, iclass 12, count 2 2006.285.21:22:21.36#ibcon#about to write, iclass 12, count 2 2006.285.21:22:21.36#ibcon#wrote, iclass 12, count 2 2006.285.21:22:21.36#ibcon#about to read 3, iclass 12, count 2 2006.285.21:22:21.39#ibcon#read 3, iclass 12, count 2 2006.285.21:22:21.39#ibcon#about to read 4, iclass 12, count 2 2006.285.21:22:21.39#ibcon#read 4, iclass 12, count 2 2006.285.21:22:21.39#ibcon#about to read 5, iclass 12, count 2 2006.285.21:22:21.39#ibcon#read 5, iclass 12, count 2 2006.285.21:22:21.39#ibcon#about to read 6, iclass 12, count 2 2006.285.21:22:21.39#ibcon#read 6, iclass 12, count 2 2006.285.21:22:21.39#ibcon#end of sib2, iclass 12, count 2 2006.285.21:22:21.39#ibcon#*after write, iclass 12, count 2 2006.285.21:22:21.39#ibcon#*before return 0, iclass 12, count 2 2006.285.21:22:21.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:22:21.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:22:21.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.21:22:21.39#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:21.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:22:21.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:22:21.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:22:21.51#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:22:21.51#ibcon#first serial, iclass 12, count 0 2006.285.21:22:21.51#ibcon#enter sib2, iclass 12, count 0 2006.285.21:22:21.51#ibcon#flushed, iclass 12, count 0 2006.285.21:22:21.51#ibcon#about to write, iclass 12, count 0 2006.285.21:22:21.51#ibcon#wrote, iclass 12, count 0 2006.285.21:22:21.51#ibcon#about to read 3, iclass 12, count 0 2006.285.21:22:21.53#ibcon#read 3, iclass 12, count 0 2006.285.21:22:21.53#ibcon#about to read 4, iclass 12, count 0 2006.285.21:22:21.53#ibcon#read 4, iclass 12, count 0 2006.285.21:22:21.53#ibcon#about to read 5, iclass 12, count 0 2006.285.21:22:21.53#ibcon#read 5, iclass 12, count 0 2006.285.21:22:21.53#ibcon#about to read 6, iclass 12, count 0 2006.285.21:22:21.53#ibcon#read 6, iclass 12, count 0 2006.285.21:22:21.53#ibcon#end of sib2, iclass 12, count 0 2006.285.21:22:21.53#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:22:21.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:22:21.53#ibcon#[27=USB\r\n] 2006.285.21:22:21.53#ibcon#*before write, iclass 12, count 0 2006.285.21:22:21.53#ibcon#enter sib2, iclass 12, count 0 2006.285.21:22:21.53#ibcon#flushed, iclass 12, count 0 2006.285.21:22:21.53#ibcon#about to write, iclass 12, count 0 2006.285.21:22:21.53#ibcon#wrote, iclass 12, count 0 2006.285.21:22:21.53#ibcon#about to read 3, iclass 12, count 0 2006.285.21:22:21.56#ibcon#read 3, iclass 12, count 0 2006.285.21:22:21.56#ibcon#about to read 4, iclass 12, count 0 2006.285.21:22:21.56#ibcon#read 4, iclass 12, count 0 2006.285.21:22:21.56#ibcon#about to read 5, iclass 12, count 0 2006.285.21:22:21.56#ibcon#read 5, iclass 12, count 0 2006.285.21:22:21.56#ibcon#about to read 6, iclass 12, count 0 2006.285.21:22:21.56#ibcon#read 6, iclass 12, count 0 2006.285.21:22:21.56#ibcon#end of sib2, iclass 12, count 0 2006.285.21:22:21.56#ibcon#*after write, iclass 12, count 0 2006.285.21:22:21.56#ibcon#*before return 0, iclass 12, count 0 2006.285.21:22:21.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:22:21.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:22:21.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:22:21.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:22:21.56$vck44/vblo=6,719.99 2006.285.21:22:21.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.21:22:21.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.21:22:21.56#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:21.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:22:21.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:22:21.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:22:21.56#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:22:21.56#ibcon#first serial, iclass 14, count 0 2006.285.21:22:21.56#ibcon#enter sib2, iclass 14, count 0 2006.285.21:22:21.56#ibcon#flushed, iclass 14, count 0 2006.285.21:22:21.56#ibcon#about to write, iclass 14, count 0 2006.285.21:22:21.56#ibcon#wrote, iclass 14, count 0 2006.285.21:22:21.56#ibcon#about to read 3, iclass 14, count 0 2006.285.21:22:21.58#ibcon#read 3, iclass 14, count 0 2006.285.21:22:21.58#ibcon#about to read 4, iclass 14, count 0 2006.285.21:22:21.58#ibcon#read 4, iclass 14, count 0 2006.285.21:22:21.58#ibcon#about to read 5, iclass 14, count 0 2006.285.21:22:21.58#ibcon#read 5, iclass 14, count 0 2006.285.21:22:21.58#ibcon#about to read 6, iclass 14, count 0 2006.285.21:22:21.58#ibcon#read 6, iclass 14, count 0 2006.285.21:22:21.58#ibcon#end of sib2, iclass 14, count 0 2006.285.21:22:21.58#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:22:21.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:22:21.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:22:21.58#ibcon#*before write, iclass 14, count 0 2006.285.21:22:21.58#ibcon#enter sib2, iclass 14, count 0 2006.285.21:22:21.58#ibcon#flushed, iclass 14, count 0 2006.285.21:22:21.58#ibcon#about to write, iclass 14, count 0 2006.285.21:22:21.58#ibcon#wrote, iclass 14, count 0 2006.285.21:22:21.58#ibcon#about to read 3, iclass 14, count 0 2006.285.21:22:21.62#ibcon#read 3, iclass 14, count 0 2006.285.21:22:21.62#ibcon#about to read 4, iclass 14, count 0 2006.285.21:22:21.62#ibcon#read 4, iclass 14, count 0 2006.285.21:22:21.62#ibcon#about to read 5, iclass 14, count 0 2006.285.21:22:21.62#ibcon#read 5, iclass 14, count 0 2006.285.21:22:21.62#ibcon#about to read 6, iclass 14, count 0 2006.285.21:22:21.62#ibcon#read 6, iclass 14, count 0 2006.285.21:22:21.62#ibcon#end of sib2, iclass 14, count 0 2006.285.21:22:21.62#ibcon#*after write, iclass 14, count 0 2006.285.21:22:21.62#ibcon#*before return 0, iclass 14, count 0 2006.285.21:22:21.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:22:21.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:22:21.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:22:21.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:22:21.62$vck44/vb=6,3 2006.285.21:22:21.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.21:22:21.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.21:22:21.62#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:21.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:22:21.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:22:21.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:22:21.68#ibcon#enter wrdev, iclass 16, count 2 2006.285.21:22:21.68#ibcon#first serial, iclass 16, count 2 2006.285.21:22:21.68#ibcon#enter sib2, iclass 16, count 2 2006.285.21:22:21.68#ibcon#flushed, iclass 16, count 2 2006.285.21:22:21.68#ibcon#about to write, iclass 16, count 2 2006.285.21:22:21.68#ibcon#wrote, iclass 16, count 2 2006.285.21:22:21.68#ibcon#about to read 3, iclass 16, count 2 2006.285.21:22:21.70#ibcon#read 3, iclass 16, count 2 2006.285.21:22:21.70#ibcon#about to read 4, iclass 16, count 2 2006.285.21:22:21.70#ibcon#read 4, iclass 16, count 2 2006.285.21:22:21.70#ibcon#about to read 5, iclass 16, count 2 2006.285.21:22:21.70#ibcon#read 5, iclass 16, count 2 2006.285.21:22:21.70#ibcon#about to read 6, iclass 16, count 2 2006.285.21:22:21.70#ibcon#read 6, iclass 16, count 2 2006.285.21:22:21.70#ibcon#end of sib2, iclass 16, count 2 2006.285.21:22:21.70#ibcon#*mode == 0, iclass 16, count 2 2006.285.21:22:21.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.21:22:21.70#ibcon#[27=AT06-03\r\n] 2006.285.21:22:21.70#ibcon#*before write, iclass 16, count 2 2006.285.21:22:21.70#ibcon#enter sib2, iclass 16, count 2 2006.285.21:22:21.70#ibcon#flushed, iclass 16, count 2 2006.285.21:22:21.70#ibcon#about to write, iclass 16, count 2 2006.285.21:22:21.70#ibcon#wrote, iclass 16, count 2 2006.285.21:22:21.70#ibcon#about to read 3, iclass 16, count 2 2006.285.21:22:21.73#ibcon#read 3, iclass 16, count 2 2006.285.21:22:21.73#ibcon#about to read 4, iclass 16, count 2 2006.285.21:22:21.73#ibcon#read 4, iclass 16, count 2 2006.285.21:22:21.73#ibcon#about to read 5, iclass 16, count 2 2006.285.21:22:21.73#ibcon#read 5, iclass 16, count 2 2006.285.21:22:21.73#ibcon#about to read 6, iclass 16, count 2 2006.285.21:22:21.73#ibcon#read 6, iclass 16, count 2 2006.285.21:22:21.73#ibcon#end of sib2, iclass 16, count 2 2006.285.21:22:21.73#ibcon#*after write, iclass 16, count 2 2006.285.21:22:21.73#ibcon#*before return 0, iclass 16, count 2 2006.285.21:22:21.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:22:21.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:22:21.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.21:22:21.73#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:21.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:22:21.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:22:21.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:22:21.85#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:22:21.85#ibcon#first serial, iclass 16, count 0 2006.285.21:22:21.85#ibcon#enter sib2, iclass 16, count 0 2006.285.21:22:21.85#ibcon#flushed, iclass 16, count 0 2006.285.21:22:21.85#ibcon#about to write, iclass 16, count 0 2006.285.21:22:21.85#ibcon#wrote, iclass 16, count 0 2006.285.21:22:21.85#ibcon#about to read 3, iclass 16, count 0 2006.285.21:22:21.87#ibcon#read 3, iclass 16, count 0 2006.285.21:22:21.87#ibcon#about to read 4, iclass 16, count 0 2006.285.21:22:21.87#ibcon#read 4, iclass 16, count 0 2006.285.21:22:21.87#ibcon#about to read 5, iclass 16, count 0 2006.285.21:22:21.87#ibcon#read 5, iclass 16, count 0 2006.285.21:22:21.87#ibcon#about to read 6, iclass 16, count 0 2006.285.21:22:21.87#ibcon#read 6, iclass 16, count 0 2006.285.21:22:21.87#ibcon#end of sib2, iclass 16, count 0 2006.285.21:22:21.87#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:22:21.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:22:21.87#ibcon#[27=USB\r\n] 2006.285.21:22:21.87#ibcon#*before write, iclass 16, count 0 2006.285.21:22:21.87#ibcon#enter sib2, iclass 16, count 0 2006.285.21:22:21.87#ibcon#flushed, iclass 16, count 0 2006.285.21:22:21.87#ibcon#about to write, iclass 16, count 0 2006.285.21:22:21.87#ibcon#wrote, iclass 16, count 0 2006.285.21:22:21.87#ibcon#about to read 3, iclass 16, count 0 2006.285.21:22:21.90#ibcon#read 3, iclass 16, count 0 2006.285.21:22:21.90#ibcon#about to read 4, iclass 16, count 0 2006.285.21:22:21.90#ibcon#read 4, iclass 16, count 0 2006.285.21:22:21.90#ibcon#about to read 5, iclass 16, count 0 2006.285.21:22:21.90#ibcon#read 5, iclass 16, count 0 2006.285.21:22:21.90#ibcon#about to read 6, iclass 16, count 0 2006.285.21:22:21.90#ibcon#read 6, iclass 16, count 0 2006.285.21:22:21.90#ibcon#end of sib2, iclass 16, count 0 2006.285.21:22:21.90#ibcon#*after write, iclass 16, count 0 2006.285.21:22:21.90#ibcon#*before return 0, iclass 16, count 0 2006.285.21:22:21.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:22:21.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:22:21.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:22:21.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:22:21.90$vck44/vblo=7,734.99 2006.285.21:22:21.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.21:22:21.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.21:22:21.90#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:21.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:22:21.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:22:21.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:22:21.90#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:22:21.90#ibcon#first serial, iclass 18, count 0 2006.285.21:22:21.90#ibcon#enter sib2, iclass 18, count 0 2006.285.21:22:21.90#ibcon#flushed, iclass 18, count 0 2006.285.21:22:21.90#ibcon#about to write, iclass 18, count 0 2006.285.21:22:21.90#ibcon#wrote, iclass 18, count 0 2006.285.21:22:21.90#ibcon#about to read 3, iclass 18, count 0 2006.285.21:22:21.92#ibcon#read 3, iclass 18, count 0 2006.285.21:22:21.92#ibcon#about to read 4, iclass 18, count 0 2006.285.21:22:21.92#ibcon#read 4, iclass 18, count 0 2006.285.21:22:21.92#ibcon#about to read 5, iclass 18, count 0 2006.285.21:22:21.92#ibcon#read 5, iclass 18, count 0 2006.285.21:22:21.92#ibcon#about to read 6, iclass 18, count 0 2006.285.21:22:21.92#ibcon#read 6, iclass 18, count 0 2006.285.21:22:21.92#ibcon#end of sib2, iclass 18, count 0 2006.285.21:22:21.92#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:22:21.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:22:21.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:22:21.92#ibcon#*before write, iclass 18, count 0 2006.285.21:22:21.92#ibcon#enter sib2, iclass 18, count 0 2006.285.21:22:21.92#ibcon#flushed, iclass 18, count 0 2006.285.21:22:21.92#ibcon#about to write, iclass 18, count 0 2006.285.21:22:21.92#ibcon#wrote, iclass 18, count 0 2006.285.21:22:21.92#ibcon#about to read 3, iclass 18, count 0 2006.285.21:22:21.96#ibcon#read 3, iclass 18, count 0 2006.285.21:22:21.96#ibcon#about to read 4, iclass 18, count 0 2006.285.21:22:21.96#ibcon#read 4, iclass 18, count 0 2006.285.21:22:21.96#ibcon#about to read 5, iclass 18, count 0 2006.285.21:22:21.96#ibcon#read 5, iclass 18, count 0 2006.285.21:22:21.96#ibcon#about to read 6, iclass 18, count 0 2006.285.21:22:21.96#ibcon#read 6, iclass 18, count 0 2006.285.21:22:21.96#ibcon#end of sib2, iclass 18, count 0 2006.285.21:22:21.96#ibcon#*after write, iclass 18, count 0 2006.285.21:22:21.96#ibcon#*before return 0, iclass 18, count 0 2006.285.21:22:21.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:22:21.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:22:21.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:22:21.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:22:21.96$vck44/vb=7,4 2006.285.21:22:21.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.21:22:21.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.21:22:21.96#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:21.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:22:22.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:22:22.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:22:22.02#ibcon#enter wrdev, iclass 20, count 2 2006.285.21:22:22.02#ibcon#first serial, iclass 20, count 2 2006.285.21:22:22.02#ibcon#enter sib2, iclass 20, count 2 2006.285.21:22:22.02#ibcon#flushed, iclass 20, count 2 2006.285.21:22:22.02#ibcon#about to write, iclass 20, count 2 2006.285.21:22:22.02#ibcon#wrote, iclass 20, count 2 2006.285.21:22:22.02#ibcon#about to read 3, iclass 20, count 2 2006.285.21:22:22.04#ibcon#read 3, iclass 20, count 2 2006.285.21:22:22.04#ibcon#about to read 4, iclass 20, count 2 2006.285.21:22:22.04#ibcon#read 4, iclass 20, count 2 2006.285.21:22:22.04#ibcon#about to read 5, iclass 20, count 2 2006.285.21:22:22.04#ibcon#read 5, iclass 20, count 2 2006.285.21:22:22.04#ibcon#about to read 6, iclass 20, count 2 2006.285.21:22:22.04#ibcon#read 6, iclass 20, count 2 2006.285.21:22:22.04#ibcon#end of sib2, iclass 20, count 2 2006.285.21:22:22.04#ibcon#*mode == 0, iclass 20, count 2 2006.285.21:22:22.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.21:22:22.04#ibcon#[27=AT07-04\r\n] 2006.285.21:22:22.04#ibcon#*before write, iclass 20, count 2 2006.285.21:22:22.04#ibcon#enter sib2, iclass 20, count 2 2006.285.21:22:22.04#ibcon#flushed, iclass 20, count 2 2006.285.21:22:22.04#ibcon#about to write, iclass 20, count 2 2006.285.21:22:22.04#ibcon#wrote, iclass 20, count 2 2006.285.21:22:22.04#ibcon#about to read 3, iclass 20, count 2 2006.285.21:22:22.07#ibcon#read 3, iclass 20, count 2 2006.285.21:22:22.07#ibcon#about to read 4, iclass 20, count 2 2006.285.21:22:22.07#ibcon#read 4, iclass 20, count 2 2006.285.21:22:22.07#ibcon#about to read 5, iclass 20, count 2 2006.285.21:22:22.07#ibcon#read 5, iclass 20, count 2 2006.285.21:22:22.07#ibcon#about to read 6, iclass 20, count 2 2006.285.21:22:22.07#ibcon#read 6, iclass 20, count 2 2006.285.21:22:22.07#ibcon#end of sib2, iclass 20, count 2 2006.285.21:22:22.07#ibcon#*after write, iclass 20, count 2 2006.285.21:22:22.07#ibcon#*before return 0, iclass 20, count 2 2006.285.21:22:22.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:22:22.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:22:22.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.21:22:22.07#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:22.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:22:22.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:22:22.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:22:22.19#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:22:22.19#ibcon#first serial, iclass 20, count 0 2006.285.21:22:22.19#ibcon#enter sib2, iclass 20, count 0 2006.285.21:22:22.19#ibcon#flushed, iclass 20, count 0 2006.285.21:22:22.19#ibcon#about to write, iclass 20, count 0 2006.285.21:22:22.19#ibcon#wrote, iclass 20, count 0 2006.285.21:22:22.19#ibcon#about to read 3, iclass 20, count 0 2006.285.21:22:22.21#ibcon#read 3, iclass 20, count 0 2006.285.21:22:22.21#ibcon#about to read 4, iclass 20, count 0 2006.285.21:22:22.21#ibcon#read 4, iclass 20, count 0 2006.285.21:22:22.21#ibcon#about to read 5, iclass 20, count 0 2006.285.21:22:22.21#ibcon#read 5, iclass 20, count 0 2006.285.21:22:22.21#ibcon#about to read 6, iclass 20, count 0 2006.285.21:22:22.21#ibcon#read 6, iclass 20, count 0 2006.285.21:22:22.21#ibcon#end of sib2, iclass 20, count 0 2006.285.21:22:22.29#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:22:22.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:22:22.29#ibcon#[27=USB\r\n] 2006.285.21:22:22.29#ibcon#*before write, iclass 20, count 0 2006.285.21:22:22.29#ibcon#enter sib2, iclass 20, count 0 2006.285.21:22:22.29#ibcon#flushed, iclass 20, count 0 2006.285.21:22:22.29#ibcon#about to write, iclass 20, count 0 2006.285.21:22:22.29#ibcon#wrote, iclass 20, count 0 2006.285.21:22:22.29#ibcon#about to read 3, iclass 20, count 0 2006.285.21:22:22.31#ibcon#read 3, iclass 20, count 0 2006.285.21:22:22.31#ibcon#about to read 4, iclass 20, count 0 2006.285.21:22:22.31#ibcon#read 4, iclass 20, count 0 2006.285.21:22:22.31#ibcon#about to read 5, iclass 20, count 0 2006.285.21:22:22.31#ibcon#read 5, iclass 20, count 0 2006.285.21:22:22.31#ibcon#about to read 6, iclass 20, count 0 2006.285.21:22:22.31#ibcon#read 6, iclass 20, count 0 2006.285.21:22:22.31#ibcon#end of sib2, iclass 20, count 0 2006.285.21:22:22.31#ibcon#*after write, iclass 20, count 0 2006.285.21:22:22.31#ibcon#*before return 0, iclass 20, count 0 2006.285.21:22:22.31#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:22:22.31#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:22:22.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:22:22.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:22:22.31$vck44/vblo=8,744.99 2006.285.21:22:22.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.21:22:22.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.21:22:22.31#ibcon#ireg 17 cls_cnt 0 2006.285.21:22:22.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:22:22.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:22:22.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:22:22.31#ibcon#enter wrdev, iclass 22, count 0 2006.285.21:22:22.31#ibcon#first serial, iclass 22, count 0 2006.285.21:22:22.31#ibcon#enter sib2, iclass 22, count 0 2006.285.21:22:22.31#ibcon#flushed, iclass 22, count 0 2006.285.21:22:22.31#ibcon#about to write, iclass 22, count 0 2006.285.21:22:22.31#ibcon#wrote, iclass 22, count 0 2006.285.21:22:22.31#ibcon#about to read 3, iclass 22, count 0 2006.285.21:22:22.33#ibcon#read 3, iclass 22, count 0 2006.285.21:22:22.33#ibcon#about to read 4, iclass 22, count 0 2006.285.21:22:22.33#ibcon#read 4, iclass 22, count 0 2006.285.21:22:22.33#ibcon#about to read 5, iclass 22, count 0 2006.285.21:22:22.33#ibcon#read 5, iclass 22, count 0 2006.285.21:22:22.33#ibcon#about to read 6, iclass 22, count 0 2006.285.21:22:22.33#ibcon#read 6, iclass 22, count 0 2006.285.21:22:22.33#ibcon#end of sib2, iclass 22, count 0 2006.285.21:22:22.33#ibcon#*mode == 0, iclass 22, count 0 2006.285.21:22:22.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.21:22:22.33#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:22:22.33#ibcon#*before write, iclass 22, count 0 2006.285.21:22:22.33#ibcon#enter sib2, iclass 22, count 0 2006.285.21:22:22.33#ibcon#flushed, iclass 22, count 0 2006.285.21:22:22.33#ibcon#about to write, iclass 22, count 0 2006.285.21:22:22.33#ibcon#wrote, iclass 22, count 0 2006.285.21:22:22.33#ibcon#about to read 3, iclass 22, count 0 2006.285.21:22:22.37#ibcon#read 3, iclass 22, count 0 2006.285.21:22:22.37#ibcon#about to read 4, iclass 22, count 0 2006.285.21:22:22.37#ibcon#read 4, iclass 22, count 0 2006.285.21:22:22.37#ibcon#about to read 5, iclass 22, count 0 2006.285.21:22:22.37#ibcon#read 5, iclass 22, count 0 2006.285.21:22:22.37#ibcon#about to read 6, iclass 22, count 0 2006.285.21:22:22.37#ibcon#read 6, iclass 22, count 0 2006.285.21:22:22.37#ibcon#end of sib2, iclass 22, count 0 2006.285.21:22:22.37#ibcon#*after write, iclass 22, count 0 2006.285.21:22:22.37#ibcon#*before return 0, iclass 22, count 0 2006.285.21:22:22.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:22:22.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:22:22.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.21:22:22.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.21:22:22.37$vck44/vb=8,4 2006.285.21:22:22.37#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.21:22:22.37#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.21:22:22.37#ibcon#ireg 11 cls_cnt 2 2006.285.21:22:22.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:22:22.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:22:22.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:22:22.43#ibcon#enter wrdev, iclass 24, count 2 2006.285.21:22:22.43#ibcon#first serial, iclass 24, count 2 2006.285.21:22:22.43#ibcon#enter sib2, iclass 24, count 2 2006.285.21:22:22.43#ibcon#flushed, iclass 24, count 2 2006.285.21:22:22.43#ibcon#about to write, iclass 24, count 2 2006.285.21:22:22.43#ibcon#wrote, iclass 24, count 2 2006.285.21:22:22.43#ibcon#about to read 3, iclass 24, count 2 2006.285.21:22:22.45#ibcon#read 3, iclass 24, count 2 2006.285.21:22:22.45#ibcon#about to read 4, iclass 24, count 2 2006.285.21:22:22.45#ibcon#read 4, iclass 24, count 2 2006.285.21:22:22.45#ibcon#about to read 5, iclass 24, count 2 2006.285.21:22:22.45#ibcon#read 5, iclass 24, count 2 2006.285.21:22:22.45#ibcon#about to read 6, iclass 24, count 2 2006.285.21:22:22.45#ibcon#read 6, iclass 24, count 2 2006.285.21:22:22.45#ibcon#end of sib2, iclass 24, count 2 2006.285.21:22:22.45#ibcon#*mode == 0, iclass 24, count 2 2006.285.21:22:22.45#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.21:22:22.45#ibcon#[27=AT08-04\r\n] 2006.285.21:22:22.45#ibcon#*before write, iclass 24, count 2 2006.285.21:22:22.45#ibcon#enter sib2, iclass 24, count 2 2006.285.21:22:22.45#ibcon#flushed, iclass 24, count 2 2006.285.21:22:22.45#ibcon#about to write, iclass 24, count 2 2006.285.21:22:22.45#ibcon#wrote, iclass 24, count 2 2006.285.21:22:22.45#ibcon#about to read 3, iclass 24, count 2 2006.285.21:22:22.48#ibcon#read 3, iclass 24, count 2 2006.285.21:22:22.48#ibcon#about to read 4, iclass 24, count 2 2006.285.21:22:22.48#ibcon#read 4, iclass 24, count 2 2006.285.21:22:22.48#ibcon#about to read 5, iclass 24, count 2 2006.285.21:22:22.48#ibcon#read 5, iclass 24, count 2 2006.285.21:22:22.48#ibcon#about to read 6, iclass 24, count 2 2006.285.21:22:22.48#ibcon#read 6, iclass 24, count 2 2006.285.21:22:22.48#ibcon#end of sib2, iclass 24, count 2 2006.285.21:22:22.48#ibcon#*after write, iclass 24, count 2 2006.285.21:22:22.48#ibcon#*before return 0, iclass 24, count 2 2006.285.21:22:22.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:22:22.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:22:22.48#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.21:22:22.48#ibcon#ireg 7 cls_cnt 0 2006.285.21:22:22.48#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:22:22.60#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:22:22.60#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:22:22.60#ibcon#enter wrdev, iclass 24, count 0 2006.285.21:22:22.60#ibcon#first serial, iclass 24, count 0 2006.285.21:22:22.60#ibcon#enter sib2, iclass 24, count 0 2006.285.21:22:22.60#ibcon#flushed, iclass 24, count 0 2006.285.21:22:22.60#ibcon#about to write, iclass 24, count 0 2006.285.21:22:22.60#ibcon#wrote, iclass 24, count 0 2006.285.21:22:22.60#ibcon#about to read 3, iclass 24, count 0 2006.285.21:22:22.62#ibcon#read 3, iclass 24, count 0 2006.285.21:22:22.62#ibcon#about to read 4, iclass 24, count 0 2006.285.21:22:22.62#ibcon#read 4, iclass 24, count 0 2006.285.21:22:22.62#ibcon#about to read 5, iclass 24, count 0 2006.285.21:22:22.62#ibcon#read 5, iclass 24, count 0 2006.285.21:22:22.62#ibcon#about to read 6, iclass 24, count 0 2006.285.21:22:22.62#ibcon#read 6, iclass 24, count 0 2006.285.21:22:22.62#ibcon#end of sib2, iclass 24, count 0 2006.285.21:22:22.62#ibcon#*mode == 0, iclass 24, count 0 2006.285.21:22:22.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.21:22:22.62#ibcon#[27=USB\r\n] 2006.285.21:22:22.62#ibcon#*before write, iclass 24, count 0 2006.285.21:22:22.62#ibcon#enter sib2, iclass 24, count 0 2006.285.21:22:22.62#ibcon#flushed, iclass 24, count 0 2006.285.21:22:22.62#ibcon#about to write, iclass 24, count 0 2006.285.21:22:22.62#ibcon#wrote, iclass 24, count 0 2006.285.21:22:22.62#ibcon#about to read 3, iclass 24, count 0 2006.285.21:22:22.65#ibcon#read 3, iclass 24, count 0 2006.285.21:22:22.65#ibcon#about to read 4, iclass 24, count 0 2006.285.21:22:22.65#ibcon#read 4, iclass 24, count 0 2006.285.21:22:22.65#ibcon#about to read 5, iclass 24, count 0 2006.285.21:22:22.65#ibcon#read 5, iclass 24, count 0 2006.285.21:22:22.65#ibcon#about to read 6, iclass 24, count 0 2006.285.21:22:22.65#ibcon#read 6, iclass 24, count 0 2006.285.21:22:22.65#ibcon#end of sib2, iclass 24, count 0 2006.285.21:22:22.65#ibcon#*after write, iclass 24, count 0 2006.285.21:22:22.65#ibcon#*before return 0, iclass 24, count 0 2006.285.21:22:22.65#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:22:22.65#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:22:22.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.21:22:22.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.21:22:22.65$vck44/vabw=wide 2006.285.21:22:22.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.21:22:22.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.21:22:22.65#ibcon#ireg 8 cls_cnt 0 2006.285.21:22:22.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:22:22.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:22:22.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:22:22.65#ibcon#enter wrdev, iclass 26, count 0 2006.285.21:22:22.65#ibcon#first serial, iclass 26, count 0 2006.285.21:22:22.65#ibcon#enter sib2, iclass 26, count 0 2006.285.21:22:22.65#ibcon#flushed, iclass 26, count 0 2006.285.21:22:22.65#ibcon#about to write, iclass 26, count 0 2006.285.21:22:22.65#ibcon#wrote, iclass 26, count 0 2006.285.21:22:22.65#ibcon#about to read 3, iclass 26, count 0 2006.285.21:22:22.67#ibcon#read 3, iclass 26, count 0 2006.285.21:22:22.67#ibcon#about to read 4, iclass 26, count 0 2006.285.21:22:22.67#ibcon#read 4, iclass 26, count 0 2006.285.21:22:22.67#ibcon#about to read 5, iclass 26, count 0 2006.285.21:22:22.67#ibcon#read 5, iclass 26, count 0 2006.285.21:22:22.67#ibcon#about to read 6, iclass 26, count 0 2006.285.21:22:22.67#ibcon#read 6, iclass 26, count 0 2006.285.21:22:22.67#ibcon#end of sib2, iclass 26, count 0 2006.285.21:22:22.67#ibcon#*mode == 0, iclass 26, count 0 2006.285.21:22:22.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.21:22:22.67#ibcon#[25=BW32\r\n] 2006.285.21:22:22.67#ibcon#*before write, iclass 26, count 0 2006.285.21:22:22.67#ibcon#enter sib2, iclass 26, count 0 2006.285.21:22:22.67#ibcon#flushed, iclass 26, count 0 2006.285.21:22:22.67#ibcon#about to write, iclass 26, count 0 2006.285.21:22:22.67#ibcon#wrote, iclass 26, count 0 2006.285.21:22:22.67#ibcon#about to read 3, iclass 26, count 0 2006.285.21:22:22.70#ibcon#read 3, iclass 26, count 0 2006.285.21:22:22.70#ibcon#about to read 4, iclass 26, count 0 2006.285.21:22:22.70#ibcon#read 4, iclass 26, count 0 2006.285.21:22:22.70#ibcon#about to read 5, iclass 26, count 0 2006.285.21:22:22.70#ibcon#read 5, iclass 26, count 0 2006.285.21:22:22.70#ibcon#about to read 6, iclass 26, count 0 2006.285.21:22:22.70#ibcon#read 6, iclass 26, count 0 2006.285.21:22:22.70#ibcon#end of sib2, iclass 26, count 0 2006.285.21:22:22.70#ibcon#*after write, iclass 26, count 0 2006.285.21:22:22.70#ibcon#*before return 0, iclass 26, count 0 2006.285.21:22:22.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:22:22.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:22:22.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.21:22:22.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.21:22:22.70$vck44/vbbw=wide 2006.285.21:22:22.70#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.21:22:22.70#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.21:22:22.70#ibcon#ireg 8 cls_cnt 0 2006.285.21:22:22.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:22:22.77#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:22:22.77#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:22:22.77#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:22:22.77#ibcon#first serial, iclass 28, count 0 2006.285.21:22:22.77#ibcon#enter sib2, iclass 28, count 0 2006.285.21:22:22.77#ibcon#flushed, iclass 28, count 0 2006.285.21:22:22.77#ibcon#about to write, iclass 28, count 0 2006.285.21:22:22.77#ibcon#wrote, iclass 28, count 0 2006.285.21:22:22.77#ibcon#about to read 3, iclass 28, count 0 2006.285.21:22:22.79#ibcon#read 3, iclass 28, count 0 2006.285.21:22:22.79#ibcon#about to read 4, iclass 28, count 0 2006.285.21:22:22.79#ibcon#read 4, iclass 28, count 0 2006.285.21:22:22.79#ibcon#about to read 5, iclass 28, count 0 2006.285.21:22:22.79#ibcon#read 5, iclass 28, count 0 2006.285.21:22:22.79#ibcon#about to read 6, iclass 28, count 0 2006.285.21:22:22.79#ibcon#read 6, iclass 28, count 0 2006.285.21:22:22.79#ibcon#end of sib2, iclass 28, count 0 2006.285.21:22:22.79#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:22:22.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:22:22.79#ibcon#[27=BW32\r\n] 2006.285.21:22:22.79#ibcon#*before write, iclass 28, count 0 2006.285.21:22:22.79#ibcon#enter sib2, iclass 28, count 0 2006.285.21:22:22.79#ibcon#flushed, iclass 28, count 0 2006.285.21:22:22.79#ibcon#about to write, iclass 28, count 0 2006.285.21:22:22.79#ibcon#wrote, iclass 28, count 0 2006.285.21:22:22.79#ibcon#about to read 3, iclass 28, count 0 2006.285.21:22:22.82#ibcon#read 3, iclass 28, count 0 2006.285.21:22:22.82#ibcon#about to read 4, iclass 28, count 0 2006.285.21:22:22.82#ibcon#read 4, iclass 28, count 0 2006.285.21:22:22.82#ibcon#about to read 5, iclass 28, count 0 2006.285.21:22:22.82#ibcon#read 5, iclass 28, count 0 2006.285.21:22:22.82#ibcon#about to read 6, iclass 28, count 0 2006.285.21:22:22.82#ibcon#read 6, iclass 28, count 0 2006.285.21:22:22.82#ibcon#end of sib2, iclass 28, count 0 2006.285.21:22:22.82#ibcon#*after write, iclass 28, count 0 2006.285.21:22:22.82#ibcon#*before return 0, iclass 28, count 0 2006.285.21:22:22.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:22:22.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:22:22.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:22:22.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:22:22.82$setupk4/ifdk4 2006.285.21:22:22.82$ifdk4/lo= 2006.285.21:22:22.82$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:22:22.82$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:22:22.82$ifdk4/patch= 2006.285.21:22:22.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:22:22.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:22:22.83$setupk4/!*+20s 2006.285.21:22:25.72#abcon#<5=/10 0.5 1.2 14.421001015.7\r\n> 2006.285.21:22:25.74#abcon#{5=INTERFACE CLEAR} 2006.285.21:22:25.80#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:22:35.89#abcon#<5=/10 0.5 1.2 14.431001015.7\r\n> 2006.285.21:22:35.91#abcon#{5=INTERFACE CLEAR} 2006.285.21:22:35.97#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:22:36.64$setupk4/"tpicd 2006.285.21:22:36.64$setupk4/echo=off 2006.285.21:22:36.64$setupk4/xlog=off 2006.285.21:22:36.64:!2006.285.21:26:19 2006.285.21:22:43.14#trakl#Source acquired 2006.285.21:22:44.14#flagr#flagr/antenna,acquired 2006.285.21:26:19.00:preob 2006.285.21:26:19.13/onsource/TRACKING 2006.285.21:26:19.13:!2006.285.21:26:29 2006.285.21:26:29.00:"tape 2006.285.21:26:29.00:"st=record 2006.285.21:26:29.00:data_valid=on 2006.285.21:26:29.00:midob 2006.285.21:26:29.13/onsource/TRACKING 2006.285.21:26:29.13/wx/14.52,1015.7,100 2006.285.21:26:29.31/cable/+6.5120E-03 2006.285.21:26:30.40/va/01,07,usb,yes,33,36 2006.285.21:26:30.40/va/02,06,usb,yes,33,34 2006.285.21:26:30.40/va/03,07,usb,yes,33,35 2006.285.21:26:30.40/va/04,06,usb,yes,34,36 2006.285.21:26:30.40/va/05,03,usb,yes,34,34 2006.285.21:26:30.40/va/06,04,usb,yes,30,30 2006.285.21:26:30.40/va/07,04,usb,yes,31,32 2006.285.21:26:30.40/va/08,03,usb,yes,32,38 2006.285.21:26:30.63/valo/01,524.99,yes,locked 2006.285.21:26:30.63/valo/02,534.99,yes,locked 2006.285.21:26:30.63/valo/03,564.99,yes,locked 2006.285.21:26:30.63/valo/04,624.99,yes,locked 2006.285.21:26:30.63/valo/05,734.99,yes,locked 2006.285.21:26:30.63/valo/06,814.99,yes,locked 2006.285.21:26:30.63/valo/07,864.99,yes,locked 2006.285.21:26:30.63/valo/08,884.99,yes,locked 2006.285.21:26:31.72/vb/01,04,usb,yes,30,28 2006.285.21:26:31.72/vb/02,05,usb,yes,28,28 2006.285.21:26:31.72/vb/03,04,usb,yes,29,32 2006.285.21:26:31.72/vb/04,05,usb,yes,30,28 2006.285.21:26:31.72/vb/05,04,usb,yes,26,28 2006.285.21:26:31.72/vb/06,03,usb,yes,37,33 2006.285.21:26:31.72/vb/07,04,usb,yes,30,30 2006.285.21:26:31.72/vb/08,04,usb,yes,27,31 2006.285.21:26:31.96/vblo/01,629.99,yes,locked 2006.285.21:26:31.96/vblo/02,634.99,yes,locked 2006.285.21:26:31.96/vblo/03,649.99,yes,locked 2006.285.21:26:31.96/vblo/04,679.99,yes,locked 2006.285.21:26:31.96/vblo/05,709.99,yes,locked 2006.285.21:26:31.96/vblo/06,719.99,yes,locked 2006.285.21:26:31.96/vblo/07,734.99,yes,locked 2006.285.21:26:31.96/vblo/08,744.99,yes,locked 2006.285.21:26:32.11/vabw/8 2006.285.21:26:32.26/vbbw/8 2006.285.21:26:32.35/xfe/off,on,12.0 2006.285.21:26:32.74/ifatt/23,28,28,28 2006.285.21:26:33.07/fmout-gps/S +2.86E-07 2006.285.21:26:33.09:!2006.285.21:28:09 2006.285.21:28:09.00:data_valid=off 2006.285.21:28:09.00:"et 2006.285.21:28:09.00:!+3s 2006.285.21:28:12.01:"tape 2006.285.21:28:12.01:postob 2006.285.21:28:12.14/cable/+6.5100E-03 2006.285.21:28:12.14/wx/14.56,1015.7,100 2006.285.21:28:13.07/fmout-gps/S +2.80E-07 2006.285.21:28:13.07:scan_name=285-2130,jd0610,60 2006.285.21:28:13.07:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.285.21:28:14.14#flagr#flagr/antenna,new-source 2006.285.21:28:14.14:checkk5 2006.285.21:28:14.51/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:28:14.99/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:28:15.36/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:28:15.88/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:28:16.27/chk_obsdata//k5ts1/T2852126??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.21:28:16.75/chk_obsdata//k5ts2/T2852126??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.21:28:17.13/chk_obsdata//k5ts3/T2852126??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.21:28:17.82/chk_obsdata//k5ts4/T2852126??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.285.21:28:18.94/k5log//k5ts1_log_newline 2006.285.21:28:19.88/k5log//k5ts2_log_newline 2006.285.21:28:20.72/k5log//k5ts3_log_newline 2006.285.21:28:21.69/k5log//k5ts4_log_newline 2006.285.21:28:21.71/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:28:21.71:setupk4=1 2006.285.21:28:21.71$setupk4/echo=on 2006.285.21:28:21.71$setupk4/pcalon 2006.285.21:28:21.71$pcalon/"no phase cal control is implemented here 2006.285.21:28:21.71$setupk4/"tpicd=stop 2006.285.21:28:21.71$setupk4/"rec=synch_on 2006.285.21:28:21.71$setupk4/"rec_mode=128 2006.285.21:28:21.71$setupk4/!* 2006.285.21:28:21.71$setupk4/recpk4 2006.285.21:28:21.71$recpk4/recpatch= 2006.285.21:28:21.72$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:28:21.72$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:28:21.72$setupk4/vck44 2006.285.21:28:21.72$vck44/valo=1,524.99 2006.285.21:28:21.72#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.21:28:21.72#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.21:28:21.72#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:21.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:28:21.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:28:21.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:28:21.72#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:28:21.72#ibcon#first serial, iclass 32, count 0 2006.285.21:28:21.72#ibcon#enter sib2, iclass 32, count 0 2006.285.21:28:21.72#ibcon#flushed, iclass 32, count 0 2006.285.21:28:21.72#ibcon#about to write, iclass 32, count 0 2006.285.21:28:21.72#ibcon#wrote, iclass 32, count 0 2006.285.21:28:21.72#ibcon#about to read 3, iclass 32, count 0 2006.285.21:28:21.73#ibcon#read 3, iclass 32, count 0 2006.285.21:28:21.73#ibcon#about to read 4, iclass 32, count 0 2006.285.21:28:21.73#ibcon#read 4, iclass 32, count 0 2006.285.21:28:21.73#ibcon#about to read 5, iclass 32, count 0 2006.285.21:28:21.73#ibcon#read 5, iclass 32, count 0 2006.285.21:28:21.73#ibcon#about to read 6, iclass 32, count 0 2006.285.21:28:21.73#ibcon#read 6, iclass 32, count 0 2006.285.21:28:21.73#ibcon#end of sib2, iclass 32, count 0 2006.285.21:28:21.73#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:28:21.73#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:28:21.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:28:21.73#ibcon#*before write, iclass 32, count 0 2006.285.21:28:21.73#ibcon#enter sib2, iclass 32, count 0 2006.285.21:28:21.73#ibcon#flushed, iclass 32, count 0 2006.285.21:28:21.73#ibcon#about to write, iclass 32, count 0 2006.285.21:28:21.73#ibcon#wrote, iclass 32, count 0 2006.285.21:28:21.73#ibcon#about to read 3, iclass 32, count 0 2006.285.21:28:21.75#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:28:21.78#ibcon#read 3, iclass 32, count 0 2006.285.21:28:21.78#ibcon#about to read 4, iclass 32, count 0 2006.285.21:28:21.78#ibcon#read 4, iclass 32, count 0 2006.285.21:28:21.78#ibcon#about to read 5, iclass 32, count 0 2006.285.21:28:21.78#ibcon#read 5, iclass 32, count 0 2006.285.21:28:21.78#ibcon#about to read 6, iclass 32, count 0 2006.285.21:28:21.78#ibcon#read 6, iclass 32, count 0 2006.285.21:28:21.78#ibcon#end of sib2, iclass 32, count 0 2006.285.21:28:21.78#ibcon#*after write, iclass 32, count 0 2006.285.21:28:21.78#ibcon#*before return 0, iclass 32, count 0 2006.285.21:28:21.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:28:21.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:28:21.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:28:21.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:28:21.78$vck44/va=1,7 2006.285.21:28:21.78#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.21:28:21.78#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.21:28:21.78#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:21.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:28:21.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:28:21.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:28:21.78#ibcon#enter wrdev, iclass 35, count 2 2006.285.21:28:21.78#ibcon#first serial, iclass 35, count 2 2006.285.21:28:21.78#ibcon#enter sib2, iclass 35, count 2 2006.285.21:28:21.78#ibcon#flushed, iclass 35, count 2 2006.285.21:28:21.78#ibcon#about to write, iclass 35, count 2 2006.285.21:28:21.78#ibcon#wrote, iclass 35, count 2 2006.285.21:28:21.78#ibcon#about to read 3, iclass 35, count 2 2006.285.21:28:21.80#ibcon#read 3, iclass 35, count 2 2006.285.21:28:21.80#ibcon#about to read 4, iclass 35, count 2 2006.285.21:28:21.80#ibcon#read 4, iclass 35, count 2 2006.285.21:28:21.80#ibcon#about to read 5, iclass 35, count 2 2006.285.21:28:21.80#ibcon#read 5, iclass 35, count 2 2006.285.21:28:21.80#ibcon#about to read 6, iclass 35, count 2 2006.285.21:28:21.80#ibcon#read 6, iclass 35, count 2 2006.285.21:28:21.80#ibcon#end of sib2, iclass 35, count 2 2006.285.21:28:21.80#ibcon#*mode == 0, iclass 35, count 2 2006.285.21:28:21.80#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.21:28:21.80#ibcon#[25=AT01-07\r\n] 2006.285.21:28:21.80#ibcon#*before write, iclass 35, count 2 2006.285.21:28:21.80#ibcon#enter sib2, iclass 35, count 2 2006.285.21:28:21.80#ibcon#flushed, iclass 35, count 2 2006.285.21:28:21.80#ibcon#about to write, iclass 35, count 2 2006.285.21:28:21.80#ibcon#wrote, iclass 35, count 2 2006.285.21:28:21.80#ibcon#about to read 3, iclass 35, count 2 2006.285.21:28:21.83#ibcon#read 3, iclass 35, count 2 2006.285.21:28:21.83#ibcon#about to read 4, iclass 35, count 2 2006.285.21:28:21.83#ibcon#read 4, iclass 35, count 2 2006.285.21:28:21.83#ibcon#about to read 5, iclass 35, count 2 2006.285.21:28:21.83#ibcon#read 5, iclass 35, count 2 2006.285.21:28:21.83#ibcon#about to read 6, iclass 35, count 2 2006.285.21:28:21.83#ibcon#read 6, iclass 35, count 2 2006.285.21:28:21.83#ibcon#end of sib2, iclass 35, count 2 2006.285.21:28:21.83#ibcon#*after write, iclass 35, count 2 2006.285.21:28:21.83#ibcon#*before return 0, iclass 35, count 2 2006.285.21:28:21.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:28:21.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:28:21.83#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.21:28:21.83#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:21.83#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:28:21.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:28:21.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:28:21.95#ibcon#enter wrdev, iclass 35, count 0 2006.285.21:28:21.95#ibcon#first serial, iclass 35, count 0 2006.285.21:28:21.95#ibcon#enter sib2, iclass 35, count 0 2006.285.21:28:21.95#ibcon#flushed, iclass 35, count 0 2006.285.21:28:21.95#ibcon#about to write, iclass 35, count 0 2006.285.21:28:21.95#ibcon#wrote, iclass 35, count 0 2006.285.21:28:21.95#ibcon#about to read 3, iclass 35, count 0 2006.285.21:28:21.97#ibcon#read 3, iclass 35, count 0 2006.285.21:28:21.97#ibcon#about to read 4, iclass 35, count 0 2006.285.21:28:21.97#ibcon#read 4, iclass 35, count 0 2006.285.21:28:21.97#ibcon#about to read 5, iclass 35, count 0 2006.285.21:28:21.97#ibcon#read 5, iclass 35, count 0 2006.285.21:28:21.97#ibcon#about to read 6, iclass 35, count 0 2006.285.21:28:21.97#ibcon#read 6, iclass 35, count 0 2006.285.21:28:21.97#ibcon#end of sib2, iclass 35, count 0 2006.285.21:28:21.97#ibcon#*mode == 0, iclass 35, count 0 2006.285.21:28:21.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.21:28:21.97#ibcon#[25=USB\r\n] 2006.285.21:28:21.97#ibcon#*before write, iclass 35, count 0 2006.285.21:28:21.97#ibcon#enter sib2, iclass 35, count 0 2006.285.21:28:21.97#ibcon#flushed, iclass 35, count 0 2006.285.21:28:21.97#ibcon#about to write, iclass 35, count 0 2006.285.21:28:21.97#ibcon#wrote, iclass 35, count 0 2006.285.21:28:21.97#ibcon#about to read 3, iclass 35, count 0 2006.285.21:28:22.00#ibcon#read 3, iclass 35, count 0 2006.285.21:28:22.00#ibcon#about to read 4, iclass 35, count 0 2006.285.21:28:22.00#ibcon#read 4, iclass 35, count 0 2006.285.21:28:22.00#ibcon#about to read 5, iclass 35, count 0 2006.285.21:28:22.00#ibcon#read 5, iclass 35, count 0 2006.285.21:28:22.00#ibcon#about to read 6, iclass 35, count 0 2006.285.21:28:22.00#ibcon#read 6, iclass 35, count 0 2006.285.21:28:22.00#ibcon#end of sib2, iclass 35, count 0 2006.285.21:28:22.00#ibcon#*after write, iclass 35, count 0 2006.285.21:28:22.00#ibcon#*before return 0, iclass 35, count 0 2006.285.21:28:22.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:28:22.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:28:22.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.21:28:22.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.21:28:22.00$vck44/valo=2,534.99 2006.285.21:28:22.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.21:28:22.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.21:28:22.00#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:22.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:28:22.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:28:22.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:28:22.00#ibcon#enter wrdev, iclass 37, count 0 2006.285.21:28:22.00#ibcon#first serial, iclass 37, count 0 2006.285.21:28:22.00#ibcon#enter sib2, iclass 37, count 0 2006.285.21:28:22.00#ibcon#flushed, iclass 37, count 0 2006.285.21:28:22.00#ibcon#about to write, iclass 37, count 0 2006.285.21:28:22.00#ibcon#wrote, iclass 37, count 0 2006.285.21:28:22.00#ibcon#about to read 3, iclass 37, count 0 2006.285.21:28:22.02#ibcon#read 3, iclass 37, count 0 2006.285.21:28:22.02#ibcon#about to read 4, iclass 37, count 0 2006.285.21:28:22.02#ibcon#read 4, iclass 37, count 0 2006.285.21:28:22.02#ibcon#about to read 5, iclass 37, count 0 2006.285.21:28:22.02#ibcon#read 5, iclass 37, count 0 2006.285.21:28:22.02#ibcon#about to read 6, iclass 37, count 0 2006.285.21:28:22.02#ibcon#read 6, iclass 37, count 0 2006.285.21:28:22.02#ibcon#end of sib2, iclass 37, count 0 2006.285.21:28:22.02#ibcon#*mode == 0, iclass 37, count 0 2006.285.21:28:22.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.21:28:22.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:28:22.02#ibcon#*before write, iclass 37, count 0 2006.285.21:28:22.02#ibcon#enter sib2, iclass 37, count 0 2006.285.21:28:22.02#ibcon#flushed, iclass 37, count 0 2006.285.21:28:22.02#ibcon#about to write, iclass 37, count 0 2006.285.21:28:22.02#ibcon#wrote, iclass 37, count 0 2006.285.21:28:22.02#ibcon#about to read 3, iclass 37, count 0 2006.285.21:28:22.06#ibcon#read 3, iclass 37, count 0 2006.285.21:28:22.06#ibcon#about to read 4, iclass 37, count 0 2006.285.21:28:22.06#ibcon#read 4, iclass 37, count 0 2006.285.21:28:22.06#ibcon#about to read 5, iclass 37, count 0 2006.285.21:28:22.06#ibcon#read 5, iclass 37, count 0 2006.285.21:28:22.06#ibcon#about to read 6, iclass 37, count 0 2006.285.21:28:22.06#ibcon#read 6, iclass 37, count 0 2006.285.21:28:22.06#ibcon#end of sib2, iclass 37, count 0 2006.285.21:28:22.06#ibcon#*after write, iclass 37, count 0 2006.285.21:28:22.06#ibcon#*before return 0, iclass 37, count 0 2006.285.21:28:22.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:28:22.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:28:22.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.21:28:22.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.21:28:22.06$vck44/va=2,6 2006.285.21:28:22.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.21:28:22.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.21:28:22.06#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:22.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:28:22.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:28:22.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:28:22.12#ibcon#enter wrdev, iclass 39, count 2 2006.285.21:28:22.12#ibcon#first serial, iclass 39, count 2 2006.285.21:28:22.12#ibcon#enter sib2, iclass 39, count 2 2006.285.21:28:22.12#ibcon#flushed, iclass 39, count 2 2006.285.21:28:22.12#ibcon#about to write, iclass 39, count 2 2006.285.21:28:22.12#ibcon#wrote, iclass 39, count 2 2006.285.21:28:22.12#ibcon#about to read 3, iclass 39, count 2 2006.285.21:28:22.14#ibcon#read 3, iclass 39, count 2 2006.285.21:28:22.14#ibcon#about to read 4, iclass 39, count 2 2006.285.21:28:22.14#ibcon#read 4, iclass 39, count 2 2006.285.21:28:22.14#ibcon#about to read 5, iclass 39, count 2 2006.285.21:28:22.14#ibcon#read 5, iclass 39, count 2 2006.285.21:28:22.14#ibcon#about to read 6, iclass 39, count 2 2006.285.21:28:22.14#ibcon#read 6, iclass 39, count 2 2006.285.21:28:22.14#ibcon#end of sib2, iclass 39, count 2 2006.285.21:28:22.14#ibcon#*mode == 0, iclass 39, count 2 2006.285.21:28:22.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.21:28:22.14#ibcon#[25=AT02-06\r\n] 2006.285.21:28:22.14#ibcon#*before write, iclass 39, count 2 2006.285.21:28:22.14#ibcon#enter sib2, iclass 39, count 2 2006.285.21:28:22.14#ibcon#flushed, iclass 39, count 2 2006.285.21:28:22.14#ibcon#about to write, iclass 39, count 2 2006.285.21:28:22.14#ibcon#wrote, iclass 39, count 2 2006.285.21:28:22.14#ibcon#about to read 3, iclass 39, count 2 2006.285.21:28:22.17#ibcon#read 3, iclass 39, count 2 2006.285.21:28:22.17#ibcon#about to read 4, iclass 39, count 2 2006.285.21:28:22.17#ibcon#read 4, iclass 39, count 2 2006.285.21:28:22.17#ibcon#about to read 5, iclass 39, count 2 2006.285.21:28:22.17#ibcon#read 5, iclass 39, count 2 2006.285.21:28:22.17#ibcon#about to read 6, iclass 39, count 2 2006.285.21:28:22.17#ibcon#read 6, iclass 39, count 2 2006.285.21:28:22.17#ibcon#end of sib2, iclass 39, count 2 2006.285.21:28:22.17#ibcon#*after write, iclass 39, count 2 2006.285.21:28:22.17#ibcon#*before return 0, iclass 39, count 2 2006.285.21:28:22.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:28:22.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:28:22.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.21:28:22.17#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:22.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:28:22.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:28:22.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:28:22.29#ibcon#enter wrdev, iclass 39, count 0 2006.285.21:28:22.29#ibcon#first serial, iclass 39, count 0 2006.285.21:28:22.29#ibcon#enter sib2, iclass 39, count 0 2006.285.21:28:22.29#ibcon#flushed, iclass 39, count 0 2006.285.21:28:22.29#ibcon#about to write, iclass 39, count 0 2006.285.21:28:22.29#ibcon#wrote, iclass 39, count 0 2006.285.21:28:22.29#ibcon#about to read 3, iclass 39, count 0 2006.285.21:28:22.31#ibcon#read 3, iclass 39, count 0 2006.285.21:28:22.31#ibcon#about to read 4, iclass 39, count 0 2006.285.21:28:22.31#ibcon#read 4, iclass 39, count 0 2006.285.21:28:22.31#ibcon#about to read 5, iclass 39, count 0 2006.285.21:28:22.31#ibcon#read 5, iclass 39, count 0 2006.285.21:28:22.31#ibcon#about to read 6, iclass 39, count 0 2006.285.21:28:22.31#ibcon#read 6, iclass 39, count 0 2006.285.21:28:22.31#ibcon#end of sib2, iclass 39, count 0 2006.285.21:28:22.31#ibcon#*mode == 0, iclass 39, count 0 2006.285.21:28:22.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.21:28:22.31#ibcon#[25=USB\r\n] 2006.285.21:28:22.31#ibcon#*before write, iclass 39, count 0 2006.285.21:28:22.31#ibcon#enter sib2, iclass 39, count 0 2006.285.21:28:22.31#ibcon#flushed, iclass 39, count 0 2006.285.21:28:22.31#ibcon#about to write, iclass 39, count 0 2006.285.21:28:22.31#ibcon#wrote, iclass 39, count 0 2006.285.21:28:22.31#ibcon#about to read 3, iclass 39, count 0 2006.285.21:28:22.34#ibcon#read 3, iclass 39, count 0 2006.285.21:28:22.34#ibcon#about to read 4, iclass 39, count 0 2006.285.21:28:22.34#ibcon#read 4, iclass 39, count 0 2006.285.21:28:22.34#ibcon#about to read 5, iclass 39, count 0 2006.285.21:28:22.34#ibcon#read 5, iclass 39, count 0 2006.285.21:28:22.34#ibcon#about to read 6, iclass 39, count 0 2006.285.21:28:22.34#ibcon#read 6, iclass 39, count 0 2006.285.21:28:22.34#ibcon#end of sib2, iclass 39, count 0 2006.285.21:28:22.34#ibcon#*after write, iclass 39, count 0 2006.285.21:28:22.34#ibcon#*before return 0, iclass 39, count 0 2006.285.21:28:22.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:28:22.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:28:22.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.21:28:22.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.21:28:22.34$vck44/valo=3,564.99 2006.285.21:28:22.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.21:28:22.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.21:28:22.34#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:22.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:28:22.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:28:22.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:28:22.34#ibcon#enter wrdev, iclass 3, count 0 2006.285.21:28:22.34#ibcon#first serial, iclass 3, count 0 2006.285.21:28:22.34#ibcon#enter sib2, iclass 3, count 0 2006.285.21:28:22.34#ibcon#flushed, iclass 3, count 0 2006.285.21:28:22.34#ibcon#about to write, iclass 3, count 0 2006.285.21:28:22.34#ibcon#wrote, iclass 3, count 0 2006.285.21:28:22.34#ibcon#about to read 3, iclass 3, count 0 2006.285.21:28:22.36#ibcon#read 3, iclass 3, count 0 2006.285.21:28:22.36#ibcon#about to read 4, iclass 3, count 0 2006.285.21:28:22.36#ibcon#read 4, iclass 3, count 0 2006.285.21:28:22.36#ibcon#about to read 5, iclass 3, count 0 2006.285.21:28:22.36#ibcon#read 5, iclass 3, count 0 2006.285.21:28:22.36#ibcon#about to read 6, iclass 3, count 0 2006.285.21:28:22.36#ibcon#read 6, iclass 3, count 0 2006.285.21:28:22.36#ibcon#end of sib2, iclass 3, count 0 2006.285.21:28:22.36#ibcon#*mode == 0, iclass 3, count 0 2006.285.21:28:22.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.21:28:22.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:28:22.36#ibcon#*before write, iclass 3, count 0 2006.285.21:28:22.36#ibcon#enter sib2, iclass 3, count 0 2006.285.21:28:22.36#ibcon#flushed, iclass 3, count 0 2006.285.21:28:22.36#ibcon#about to write, iclass 3, count 0 2006.285.21:28:22.36#ibcon#wrote, iclass 3, count 0 2006.285.21:28:22.36#ibcon#about to read 3, iclass 3, count 0 2006.285.21:28:22.40#ibcon#read 3, iclass 3, count 0 2006.285.21:28:22.40#ibcon#about to read 4, iclass 3, count 0 2006.285.21:28:22.40#ibcon#read 4, iclass 3, count 0 2006.285.21:28:22.40#ibcon#about to read 5, iclass 3, count 0 2006.285.21:28:22.40#ibcon#read 5, iclass 3, count 0 2006.285.21:28:22.40#ibcon#about to read 6, iclass 3, count 0 2006.285.21:28:22.40#ibcon#read 6, iclass 3, count 0 2006.285.21:28:22.40#ibcon#end of sib2, iclass 3, count 0 2006.285.21:28:22.40#ibcon#*after write, iclass 3, count 0 2006.285.21:28:22.40#ibcon#*before return 0, iclass 3, count 0 2006.285.21:28:22.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:28:22.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:28:22.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.21:28:22.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.21:28:22.40$vck44/va=3,7 2006.285.21:28:22.40#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.21:28:22.40#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.21:28:22.40#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:22.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:28:22.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:28:22.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:28:22.46#ibcon#enter wrdev, iclass 5, count 2 2006.285.21:28:22.46#ibcon#first serial, iclass 5, count 2 2006.285.21:28:22.46#ibcon#enter sib2, iclass 5, count 2 2006.285.21:28:22.46#ibcon#flushed, iclass 5, count 2 2006.285.21:28:22.46#ibcon#about to write, iclass 5, count 2 2006.285.21:28:22.46#ibcon#wrote, iclass 5, count 2 2006.285.21:28:22.46#ibcon#about to read 3, iclass 5, count 2 2006.285.21:28:22.48#ibcon#read 3, iclass 5, count 2 2006.285.21:28:22.48#ibcon#about to read 4, iclass 5, count 2 2006.285.21:28:22.48#ibcon#read 4, iclass 5, count 2 2006.285.21:28:22.48#ibcon#about to read 5, iclass 5, count 2 2006.285.21:28:22.48#ibcon#read 5, iclass 5, count 2 2006.285.21:28:22.48#ibcon#about to read 6, iclass 5, count 2 2006.285.21:28:22.48#ibcon#read 6, iclass 5, count 2 2006.285.21:28:22.48#ibcon#end of sib2, iclass 5, count 2 2006.285.21:28:22.48#ibcon#*mode == 0, iclass 5, count 2 2006.285.21:28:22.48#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.21:28:22.48#ibcon#[25=AT03-07\r\n] 2006.285.21:28:22.48#ibcon#*before write, iclass 5, count 2 2006.285.21:28:22.48#ibcon#enter sib2, iclass 5, count 2 2006.285.21:28:22.48#ibcon#flushed, iclass 5, count 2 2006.285.21:28:22.48#ibcon#about to write, iclass 5, count 2 2006.285.21:28:22.48#ibcon#wrote, iclass 5, count 2 2006.285.21:28:22.48#ibcon#about to read 3, iclass 5, count 2 2006.285.21:28:22.51#ibcon#read 3, iclass 5, count 2 2006.285.21:28:22.51#ibcon#about to read 4, iclass 5, count 2 2006.285.21:28:22.51#ibcon#read 4, iclass 5, count 2 2006.285.21:28:22.51#ibcon#about to read 5, iclass 5, count 2 2006.285.21:28:22.51#ibcon#read 5, iclass 5, count 2 2006.285.21:28:22.51#ibcon#about to read 6, iclass 5, count 2 2006.285.21:28:22.51#ibcon#read 6, iclass 5, count 2 2006.285.21:28:22.51#ibcon#end of sib2, iclass 5, count 2 2006.285.21:28:22.51#ibcon#*after write, iclass 5, count 2 2006.285.21:28:22.51#ibcon#*before return 0, iclass 5, count 2 2006.285.21:28:22.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:28:22.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:28:22.51#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.21:28:22.51#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:22.51#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:28:22.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:28:22.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:28:22.63#ibcon#enter wrdev, iclass 5, count 0 2006.285.21:28:22.63#ibcon#first serial, iclass 5, count 0 2006.285.21:28:22.63#ibcon#enter sib2, iclass 5, count 0 2006.285.21:28:22.63#ibcon#flushed, iclass 5, count 0 2006.285.21:28:22.63#ibcon#about to write, iclass 5, count 0 2006.285.21:28:22.63#ibcon#wrote, iclass 5, count 0 2006.285.21:28:22.63#ibcon#about to read 3, iclass 5, count 0 2006.285.21:28:22.65#ibcon#read 3, iclass 5, count 0 2006.285.21:28:22.65#ibcon#about to read 4, iclass 5, count 0 2006.285.21:28:22.65#ibcon#read 4, iclass 5, count 0 2006.285.21:28:22.65#ibcon#about to read 5, iclass 5, count 0 2006.285.21:28:22.65#ibcon#read 5, iclass 5, count 0 2006.285.21:28:22.65#ibcon#about to read 6, iclass 5, count 0 2006.285.21:28:22.65#ibcon#read 6, iclass 5, count 0 2006.285.21:28:22.65#ibcon#end of sib2, iclass 5, count 0 2006.285.21:28:22.65#ibcon#*mode == 0, iclass 5, count 0 2006.285.21:28:22.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.21:28:22.65#ibcon#[25=USB\r\n] 2006.285.21:28:22.65#ibcon#*before write, iclass 5, count 0 2006.285.21:28:22.65#ibcon#enter sib2, iclass 5, count 0 2006.285.21:28:22.65#ibcon#flushed, iclass 5, count 0 2006.285.21:28:22.65#ibcon#about to write, iclass 5, count 0 2006.285.21:28:22.65#ibcon#wrote, iclass 5, count 0 2006.285.21:28:22.65#ibcon#about to read 3, iclass 5, count 0 2006.285.21:28:22.68#ibcon#read 3, iclass 5, count 0 2006.285.21:28:22.68#ibcon#about to read 4, iclass 5, count 0 2006.285.21:28:22.68#ibcon#read 4, iclass 5, count 0 2006.285.21:28:22.68#ibcon#about to read 5, iclass 5, count 0 2006.285.21:28:22.68#ibcon#read 5, iclass 5, count 0 2006.285.21:28:22.68#ibcon#about to read 6, iclass 5, count 0 2006.285.21:28:22.68#ibcon#read 6, iclass 5, count 0 2006.285.21:28:22.68#ibcon#end of sib2, iclass 5, count 0 2006.285.21:28:22.68#ibcon#*after write, iclass 5, count 0 2006.285.21:28:22.68#ibcon#*before return 0, iclass 5, count 0 2006.285.21:28:22.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:28:22.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:28:22.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.21:28:22.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.21:28:22.68$vck44/valo=4,624.99 2006.285.21:28:22.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.21:28:22.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.21:28:22.68#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:22.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:28:22.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:28:22.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:28:22.68#ibcon#enter wrdev, iclass 7, count 0 2006.285.21:28:22.68#ibcon#first serial, iclass 7, count 0 2006.285.21:28:22.68#ibcon#enter sib2, iclass 7, count 0 2006.285.21:28:22.68#ibcon#flushed, iclass 7, count 0 2006.285.21:28:22.68#ibcon#about to write, iclass 7, count 0 2006.285.21:28:22.68#ibcon#wrote, iclass 7, count 0 2006.285.21:28:22.68#ibcon#about to read 3, iclass 7, count 0 2006.285.21:28:23.13#ibcon#read 3, iclass 7, count 0 2006.285.21:28:23.13#ibcon#about to read 4, iclass 7, count 0 2006.285.21:28:23.13#ibcon#read 4, iclass 7, count 0 2006.285.21:28:23.13#ibcon#about to read 5, iclass 7, count 0 2006.285.21:28:23.13#ibcon#read 5, iclass 7, count 0 2006.285.21:28:23.13#ibcon#about to read 6, iclass 7, count 0 2006.285.21:28:23.13#ibcon#read 6, iclass 7, count 0 2006.285.21:28:23.13#ibcon#end of sib2, iclass 7, count 0 2006.285.21:28:23.13#ibcon#*mode == 0, iclass 7, count 0 2006.285.21:28:23.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.21:28:23.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:28:23.13#ibcon#*before write, iclass 7, count 0 2006.285.21:28:23.13#ibcon#enter sib2, iclass 7, count 0 2006.285.21:28:23.13#ibcon#flushed, iclass 7, count 0 2006.285.21:28:23.13#ibcon#about to write, iclass 7, count 0 2006.285.21:28:23.13#ibcon#wrote, iclass 7, count 0 2006.285.21:28:23.13#ibcon#about to read 3, iclass 7, count 0 2006.285.21:28:23.17#ibcon#read 3, iclass 7, count 0 2006.285.21:28:23.17#ibcon#about to read 4, iclass 7, count 0 2006.285.21:28:23.17#ibcon#read 4, iclass 7, count 0 2006.285.21:28:23.17#ibcon#about to read 5, iclass 7, count 0 2006.285.21:28:23.17#ibcon#read 5, iclass 7, count 0 2006.285.21:28:23.17#ibcon#about to read 6, iclass 7, count 0 2006.285.21:28:23.17#ibcon#read 6, iclass 7, count 0 2006.285.21:28:23.17#ibcon#end of sib2, iclass 7, count 0 2006.285.21:28:23.17#ibcon#*after write, iclass 7, count 0 2006.285.21:28:23.17#ibcon#*before return 0, iclass 7, count 0 2006.285.21:28:23.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:28:23.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:28:23.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.21:28:23.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.21:28:23.17$vck44/va=4,6 2006.285.21:28:23.17#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.21:28:23.17#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.21:28:23.17#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:23.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:28:23.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:28:23.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:28:23.17#ibcon#enter wrdev, iclass 11, count 2 2006.285.21:28:23.17#ibcon#first serial, iclass 11, count 2 2006.285.21:28:23.17#ibcon#enter sib2, iclass 11, count 2 2006.285.21:28:23.17#ibcon#flushed, iclass 11, count 2 2006.285.21:28:23.17#ibcon#about to write, iclass 11, count 2 2006.285.21:28:23.17#ibcon#wrote, iclass 11, count 2 2006.285.21:28:23.17#ibcon#about to read 3, iclass 11, count 2 2006.285.21:28:23.19#ibcon#read 3, iclass 11, count 2 2006.285.21:28:23.19#ibcon#about to read 4, iclass 11, count 2 2006.285.21:28:23.19#ibcon#read 4, iclass 11, count 2 2006.285.21:28:23.19#ibcon#about to read 5, iclass 11, count 2 2006.285.21:28:23.19#ibcon#read 5, iclass 11, count 2 2006.285.21:28:23.19#ibcon#about to read 6, iclass 11, count 2 2006.285.21:28:23.19#ibcon#read 6, iclass 11, count 2 2006.285.21:28:23.19#ibcon#end of sib2, iclass 11, count 2 2006.285.21:28:23.19#ibcon#*mode == 0, iclass 11, count 2 2006.285.21:28:23.19#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.21:28:23.19#ibcon#[25=AT04-06\r\n] 2006.285.21:28:23.19#ibcon#*before write, iclass 11, count 2 2006.285.21:28:23.19#ibcon#enter sib2, iclass 11, count 2 2006.285.21:28:23.19#ibcon#flushed, iclass 11, count 2 2006.285.21:28:23.19#ibcon#about to write, iclass 11, count 2 2006.285.21:28:23.19#ibcon#wrote, iclass 11, count 2 2006.285.21:28:23.19#ibcon#about to read 3, iclass 11, count 2 2006.285.21:28:23.22#ibcon#read 3, iclass 11, count 2 2006.285.21:28:23.22#ibcon#about to read 4, iclass 11, count 2 2006.285.21:28:23.22#ibcon#read 4, iclass 11, count 2 2006.285.21:28:23.22#ibcon#about to read 5, iclass 11, count 2 2006.285.21:28:23.22#ibcon#read 5, iclass 11, count 2 2006.285.21:28:23.22#ibcon#about to read 6, iclass 11, count 2 2006.285.21:28:23.22#ibcon#read 6, iclass 11, count 2 2006.285.21:28:23.22#ibcon#end of sib2, iclass 11, count 2 2006.285.21:28:23.22#ibcon#*after write, iclass 11, count 2 2006.285.21:28:23.22#ibcon#*before return 0, iclass 11, count 2 2006.285.21:28:23.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:28:23.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:28:23.22#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.21:28:23.22#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:23.22#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:28:23.34#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:28:23.34#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:28:23.34#ibcon#enter wrdev, iclass 11, count 0 2006.285.21:28:23.34#ibcon#first serial, iclass 11, count 0 2006.285.21:28:23.34#ibcon#enter sib2, iclass 11, count 0 2006.285.21:28:23.34#ibcon#flushed, iclass 11, count 0 2006.285.21:28:23.34#ibcon#about to write, iclass 11, count 0 2006.285.21:28:23.34#ibcon#wrote, iclass 11, count 0 2006.285.21:28:23.34#ibcon#about to read 3, iclass 11, count 0 2006.285.21:28:23.36#ibcon#read 3, iclass 11, count 0 2006.285.21:28:23.36#ibcon#about to read 4, iclass 11, count 0 2006.285.21:28:23.36#ibcon#read 4, iclass 11, count 0 2006.285.21:28:23.36#ibcon#about to read 5, iclass 11, count 0 2006.285.21:28:23.36#ibcon#read 5, iclass 11, count 0 2006.285.21:28:23.36#ibcon#about to read 6, iclass 11, count 0 2006.285.21:28:23.36#ibcon#read 6, iclass 11, count 0 2006.285.21:28:23.36#ibcon#end of sib2, iclass 11, count 0 2006.285.21:28:23.36#ibcon#*mode == 0, iclass 11, count 0 2006.285.21:28:23.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.21:28:23.36#ibcon#[25=USB\r\n] 2006.285.21:28:23.36#ibcon#*before write, iclass 11, count 0 2006.285.21:28:23.36#ibcon#enter sib2, iclass 11, count 0 2006.285.21:28:23.36#ibcon#flushed, iclass 11, count 0 2006.285.21:28:23.36#ibcon#about to write, iclass 11, count 0 2006.285.21:28:23.36#ibcon#wrote, iclass 11, count 0 2006.285.21:28:23.36#ibcon#about to read 3, iclass 11, count 0 2006.285.21:28:23.39#ibcon#read 3, iclass 11, count 0 2006.285.21:28:23.39#ibcon#about to read 4, iclass 11, count 0 2006.285.21:28:23.39#ibcon#read 4, iclass 11, count 0 2006.285.21:28:23.39#ibcon#about to read 5, iclass 11, count 0 2006.285.21:28:23.39#ibcon#read 5, iclass 11, count 0 2006.285.21:28:23.39#ibcon#about to read 6, iclass 11, count 0 2006.285.21:28:23.39#ibcon#read 6, iclass 11, count 0 2006.285.21:28:23.39#ibcon#end of sib2, iclass 11, count 0 2006.285.21:28:23.39#ibcon#*after write, iclass 11, count 0 2006.285.21:28:23.39#ibcon#*before return 0, iclass 11, count 0 2006.285.21:28:23.39#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:28:23.39#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:28:23.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.21:28:23.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.21:28:23.39$vck44/valo=5,734.99 2006.285.21:28:23.39#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.21:28:23.39#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.21:28:23.39#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:23.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:28:23.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:28:23.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:28:23.39#ibcon#enter wrdev, iclass 13, count 0 2006.285.21:28:23.39#ibcon#first serial, iclass 13, count 0 2006.285.21:28:23.39#ibcon#enter sib2, iclass 13, count 0 2006.285.21:28:23.39#ibcon#flushed, iclass 13, count 0 2006.285.21:28:23.39#ibcon#about to write, iclass 13, count 0 2006.285.21:28:23.39#ibcon#wrote, iclass 13, count 0 2006.285.21:28:23.39#ibcon#about to read 3, iclass 13, count 0 2006.285.21:28:23.41#ibcon#read 3, iclass 13, count 0 2006.285.21:28:23.41#ibcon#about to read 4, iclass 13, count 0 2006.285.21:28:23.41#ibcon#read 4, iclass 13, count 0 2006.285.21:28:23.41#ibcon#about to read 5, iclass 13, count 0 2006.285.21:28:23.41#ibcon#read 5, iclass 13, count 0 2006.285.21:28:23.41#ibcon#about to read 6, iclass 13, count 0 2006.285.21:28:23.41#ibcon#read 6, iclass 13, count 0 2006.285.21:28:23.41#ibcon#end of sib2, iclass 13, count 0 2006.285.21:28:23.41#ibcon#*mode == 0, iclass 13, count 0 2006.285.21:28:23.41#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.21:28:23.41#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:28:23.41#ibcon#*before write, iclass 13, count 0 2006.285.21:28:23.41#ibcon#enter sib2, iclass 13, count 0 2006.285.21:28:23.41#ibcon#flushed, iclass 13, count 0 2006.285.21:28:23.41#ibcon#about to write, iclass 13, count 0 2006.285.21:28:23.41#ibcon#wrote, iclass 13, count 0 2006.285.21:28:23.41#ibcon#about to read 3, iclass 13, count 0 2006.285.21:28:23.45#ibcon#read 3, iclass 13, count 0 2006.285.21:28:23.45#ibcon#about to read 4, iclass 13, count 0 2006.285.21:28:23.45#ibcon#read 4, iclass 13, count 0 2006.285.21:28:23.45#ibcon#about to read 5, iclass 13, count 0 2006.285.21:28:23.45#ibcon#read 5, iclass 13, count 0 2006.285.21:28:23.45#ibcon#about to read 6, iclass 13, count 0 2006.285.21:28:23.45#ibcon#read 6, iclass 13, count 0 2006.285.21:28:23.45#ibcon#end of sib2, iclass 13, count 0 2006.285.21:28:23.45#ibcon#*after write, iclass 13, count 0 2006.285.21:28:23.45#ibcon#*before return 0, iclass 13, count 0 2006.285.21:28:23.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:28:23.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:28:23.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.21:28:23.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.21:28:23.45$vck44/va=5,3 2006.285.21:28:23.88#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.21:28:23.88#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.21:28:23.88#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:23.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:28:23.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:28:23.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:28:23.88#ibcon#enter wrdev, iclass 15, count 2 2006.285.21:28:23.88#ibcon#first serial, iclass 15, count 2 2006.285.21:28:23.88#ibcon#enter sib2, iclass 15, count 2 2006.285.21:28:23.88#ibcon#flushed, iclass 15, count 2 2006.285.21:28:23.88#ibcon#about to write, iclass 15, count 2 2006.285.21:28:23.88#ibcon#wrote, iclass 15, count 2 2006.285.21:28:23.88#ibcon#about to read 3, iclass 15, count 2 2006.285.21:28:23.89#ibcon#read 3, iclass 15, count 2 2006.285.21:28:23.89#ibcon#about to read 4, iclass 15, count 2 2006.285.21:28:23.89#ibcon#read 4, iclass 15, count 2 2006.285.21:28:23.89#ibcon#about to read 5, iclass 15, count 2 2006.285.21:28:23.89#ibcon#read 5, iclass 15, count 2 2006.285.21:28:23.89#ibcon#about to read 6, iclass 15, count 2 2006.285.21:28:23.89#ibcon#read 6, iclass 15, count 2 2006.285.21:28:23.89#ibcon#end of sib2, iclass 15, count 2 2006.285.21:28:23.89#ibcon#*mode == 0, iclass 15, count 2 2006.285.21:28:23.89#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.21:28:23.89#ibcon#[25=AT05-03\r\n] 2006.285.21:28:23.89#ibcon#*before write, iclass 15, count 2 2006.285.21:28:23.89#ibcon#enter sib2, iclass 15, count 2 2006.285.21:28:23.89#ibcon#flushed, iclass 15, count 2 2006.285.21:28:23.89#ibcon#about to write, iclass 15, count 2 2006.285.21:28:23.89#ibcon#wrote, iclass 15, count 2 2006.285.21:28:23.89#ibcon#about to read 3, iclass 15, count 2 2006.285.21:28:23.92#ibcon#read 3, iclass 15, count 2 2006.285.21:28:23.92#ibcon#about to read 4, iclass 15, count 2 2006.285.21:28:23.92#ibcon#read 4, iclass 15, count 2 2006.285.21:28:23.92#ibcon#about to read 5, iclass 15, count 2 2006.285.21:28:23.92#ibcon#read 5, iclass 15, count 2 2006.285.21:28:23.92#ibcon#about to read 6, iclass 15, count 2 2006.285.21:28:23.92#ibcon#read 6, iclass 15, count 2 2006.285.21:28:23.92#ibcon#end of sib2, iclass 15, count 2 2006.285.21:28:23.92#ibcon#*after write, iclass 15, count 2 2006.285.21:28:23.92#ibcon#*before return 0, iclass 15, count 2 2006.285.21:28:23.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:28:23.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:28:23.92#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.21:28:23.92#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:23.92#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:28:24.04#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:28:24.04#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:28:24.04#ibcon#enter wrdev, iclass 15, count 0 2006.285.21:28:24.04#ibcon#first serial, iclass 15, count 0 2006.285.21:28:24.04#ibcon#enter sib2, iclass 15, count 0 2006.285.21:28:24.04#ibcon#flushed, iclass 15, count 0 2006.285.21:28:24.04#ibcon#about to write, iclass 15, count 0 2006.285.21:28:24.04#ibcon#wrote, iclass 15, count 0 2006.285.21:28:24.04#ibcon#about to read 3, iclass 15, count 0 2006.285.21:28:24.06#ibcon#read 3, iclass 15, count 0 2006.285.21:28:24.06#ibcon#about to read 4, iclass 15, count 0 2006.285.21:28:24.06#ibcon#read 4, iclass 15, count 0 2006.285.21:28:24.06#ibcon#about to read 5, iclass 15, count 0 2006.285.21:28:24.06#ibcon#read 5, iclass 15, count 0 2006.285.21:28:24.06#ibcon#about to read 6, iclass 15, count 0 2006.285.21:28:24.06#ibcon#read 6, iclass 15, count 0 2006.285.21:28:24.06#ibcon#end of sib2, iclass 15, count 0 2006.285.21:28:24.06#ibcon#*mode == 0, iclass 15, count 0 2006.285.21:28:24.06#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.21:28:24.06#ibcon#[25=USB\r\n] 2006.285.21:28:24.06#ibcon#*before write, iclass 15, count 0 2006.285.21:28:24.06#ibcon#enter sib2, iclass 15, count 0 2006.285.21:28:24.06#ibcon#flushed, iclass 15, count 0 2006.285.21:28:24.06#ibcon#about to write, iclass 15, count 0 2006.285.21:28:24.06#ibcon#wrote, iclass 15, count 0 2006.285.21:28:24.06#ibcon#about to read 3, iclass 15, count 0 2006.285.21:28:24.09#ibcon#read 3, iclass 15, count 0 2006.285.21:28:24.09#ibcon#about to read 4, iclass 15, count 0 2006.285.21:28:24.09#ibcon#read 4, iclass 15, count 0 2006.285.21:28:24.09#ibcon#about to read 5, iclass 15, count 0 2006.285.21:28:24.09#ibcon#read 5, iclass 15, count 0 2006.285.21:28:24.09#ibcon#about to read 6, iclass 15, count 0 2006.285.21:28:24.09#ibcon#read 6, iclass 15, count 0 2006.285.21:28:24.09#ibcon#end of sib2, iclass 15, count 0 2006.285.21:28:24.09#ibcon#*after write, iclass 15, count 0 2006.285.21:28:24.09#ibcon#*before return 0, iclass 15, count 0 2006.285.21:28:24.09#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:28:24.09#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:28:24.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.21:28:24.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.21:28:24.09$vck44/valo=6,814.99 2006.285.21:28:24.09#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.21:28:24.09#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.21:28:24.09#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:24.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:28:24.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:28:24.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:28:24.09#ibcon#enter wrdev, iclass 17, count 0 2006.285.21:28:24.09#ibcon#first serial, iclass 17, count 0 2006.285.21:28:24.09#ibcon#enter sib2, iclass 17, count 0 2006.285.21:28:24.09#ibcon#flushed, iclass 17, count 0 2006.285.21:28:24.09#ibcon#about to write, iclass 17, count 0 2006.285.21:28:24.09#ibcon#wrote, iclass 17, count 0 2006.285.21:28:24.09#ibcon#about to read 3, iclass 17, count 0 2006.285.21:28:24.11#ibcon#read 3, iclass 17, count 0 2006.285.21:28:24.11#ibcon#about to read 4, iclass 17, count 0 2006.285.21:28:24.11#ibcon#read 4, iclass 17, count 0 2006.285.21:28:24.11#ibcon#about to read 5, iclass 17, count 0 2006.285.21:28:24.11#ibcon#read 5, iclass 17, count 0 2006.285.21:28:24.11#ibcon#about to read 6, iclass 17, count 0 2006.285.21:28:24.11#ibcon#read 6, iclass 17, count 0 2006.285.21:28:24.11#ibcon#end of sib2, iclass 17, count 0 2006.285.21:28:24.11#ibcon#*mode == 0, iclass 17, count 0 2006.285.21:28:24.11#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.21:28:24.11#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:28:24.11#ibcon#*before write, iclass 17, count 0 2006.285.21:28:24.11#ibcon#enter sib2, iclass 17, count 0 2006.285.21:28:24.11#ibcon#flushed, iclass 17, count 0 2006.285.21:28:24.11#ibcon#about to write, iclass 17, count 0 2006.285.21:28:24.11#ibcon#wrote, iclass 17, count 0 2006.285.21:28:24.11#ibcon#about to read 3, iclass 17, count 0 2006.285.21:28:24.15#ibcon#read 3, iclass 17, count 0 2006.285.21:28:24.15#ibcon#about to read 4, iclass 17, count 0 2006.285.21:28:24.15#ibcon#read 4, iclass 17, count 0 2006.285.21:28:24.15#ibcon#about to read 5, iclass 17, count 0 2006.285.21:28:24.15#ibcon#read 5, iclass 17, count 0 2006.285.21:28:24.15#ibcon#about to read 6, iclass 17, count 0 2006.285.21:28:24.15#ibcon#read 6, iclass 17, count 0 2006.285.21:28:24.15#ibcon#end of sib2, iclass 17, count 0 2006.285.21:28:24.15#ibcon#*after write, iclass 17, count 0 2006.285.21:28:24.15#ibcon#*before return 0, iclass 17, count 0 2006.285.21:28:24.15#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:28:24.15#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:28:24.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.21:28:24.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.21:28:24.15$vck44/va=6,4 2006.285.21:28:24.15#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.21:28:24.15#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.21:28:24.15#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:24.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:28:24.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:28:24.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:28:24.21#ibcon#enter wrdev, iclass 19, count 2 2006.285.21:28:24.21#ibcon#first serial, iclass 19, count 2 2006.285.21:28:24.21#ibcon#enter sib2, iclass 19, count 2 2006.285.21:28:24.21#ibcon#flushed, iclass 19, count 2 2006.285.21:28:24.21#ibcon#about to write, iclass 19, count 2 2006.285.21:28:24.21#ibcon#wrote, iclass 19, count 2 2006.285.21:28:24.21#ibcon#about to read 3, iclass 19, count 2 2006.285.21:28:24.23#ibcon#read 3, iclass 19, count 2 2006.285.21:28:24.23#ibcon#about to read 4, iclass 19, count 2 2006.285.21:28:24.23#ibcon#read 4, iclass 19, count 2 2006.285.21:28:24.23#ibcon#about to read 5, iclass 19, count 2 2006.285.21:28:24.23#ibcon#read 5, iclass 19, count 2 2006.285.21:28:24.23#ibcon#about to read 6, iclass 19, count 2 2006.285.21:28:24.23#ibcon#read 6, iclass 19, count 2 2006.285.21:28:24.23#ibcon#end of sib2, iclass 19, count 2 2006.285.21:28:24.23#ibcon#*mode == 0, iclass 19, count 2 2006.285.21:28:24.23#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.21:28:24.23#ibcon#[25=AT06-04\r\n] 2006.285.21:28:24.23#ibcon#*before write, iclass 19, count 2 2006.285.21:28:24.23#ibcon#enter sib2, iclass 19, count 2 2006.285.21:28:24.23#ibcon#flushed, iclass 19, count 2 2006.285.21:28:24.23#ibcon#about to write, iclass 19, count 2 2006.285.21:28:24.23#ibcon#wrote, iclass 19, count 2 2006.285.21:28:24.23#ibcon#about to read 3, iclass 19, count 2 2006.285.21:28:24.26#ibcon#read 3, iclass 19, count 2 2006.285.21:28:24.26#ibcon#about to read 4, iclass 19, count 2 2006.285.21:28:24.26#ibcon#read 4, iclass 19, count 2 2006.285.21:28:24.26#ibcon#about to read 5, iclass 19, count 2 2006.285.21:28:24.26#ibcon#read 5, iclass 19, count 2 2006.285.21:28:24.26#ibcon#about to read 6, iclass 19, count 2 2006.285.21:28:24.26#ibcon#read 6, iclass 19, count 2 2006.285.21:28:24.26#ibcon#end of sib2, iclass 19, count 2 2006.285.21:28:24.26#ibcon#*after write, iclass 19, count 2 2006.285.21:28:24.26#ibcon#*before return 0, iclass 19, count 2 2006.285.21:28:24.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:28:24.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:28:24.26#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.21:28:24.26#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:24.26#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:28:24.38#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:28:24.38#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:28:24.38#ibcon#enter wrdev, iclass 19, count 0 2006.285.21:28:24.38#ibcon#first serial, iclass 19, count 0 2006.285.21:28:24.38#ibcon#enter sib2, iclass 19, count 0 2006.285.21:28:24.38#ibcon#flushed, iclass 19, count 0 2006.285.21:28:24.38#ibcon#about to write, iclass 19, count 0 2006.285.21:28:24.38#ibcon#wrote, iclass 19, count 0 2006.285.21:28:24.38#ibcon#about to read 3, iclass 19, count 0 2006.285.21:28:24.40#ibcon#read 3, iclass 19, count 0 2006.285.21:28:24.40#ibcon#about to read 4, iclass 19, count 0 2006.285.21:28:24.40#ibcon#read 4, iclass 19, count 0 2006.285.21:28:24.40#ibcon#about to read 5, iclass 19, count 0 2006.285.21:28:24.40#ibcon#read 5, iclass 19, count 0 2006.285.21:28:24.40#ibcon#about to read 6, iclass 19, count 0 2006.285.21:28:24.40#ibcon#read 6, iclass 19, count 0 2006.285.21:28:24.40#ibcon#end of sib2, iclass 19, count 0 2006.285.21:28:24.40#ibcon#*mode == 0, iclass 19, count 0 2006.285.21:28:24.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.21:28:24.40#ibcon#[25=USB\r\n] 2006.285.21:28:24.40#ibcon#*before write, iclass 19, count 0 2006.285.21:28:24.40#ibcon#enter sib2, iclass 19, count 0 2006.285.21:28:24.40#ibcon#flushed, iclass 19, count 0 2006.285.21:28:24.40#ibcon#about to write, iclass 19, count 0 2006.285.21:28:24.40#ibcon#wrote, iclass 19, count 0 2006.285.21:28:24.40#ibcon#about to read 3, iclass 19, count 0 2006.285.21:28:24.43#ibcon#read 3, iclass 19, count 0 2006.285.21:28:24.43#ibcon#about to read 4, iclass 19, count 0 2006.285.21:28:24.43#ibcon#read 4, iclass 19, count 0 2006.285.21:28:24.43#ibcon#about to read 5, iclass 19, count 0 2006.285.21:28:24.43#ibcon#read 5, iclass 19, count 0 2006.285.21:28:24.43#ibcon#about to read 6, iclass 19, count 0 2006.285.21:28:24.43#ibcon#read 6, iclass 19, count 0 2006.285.21:28:24.43#ibcon#end of sib2, iclass 19, count 0 2006.285.21:28:24.43#ibcon#*after write, iclass 19, count 0 2006.285.21:28:24.43#ibcon#*before return 0, iclass 19, count 0 2006.285.21:28:24.43#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:28:24.43#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:28:24.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.21:28:24.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.21:28:24.43$vck44/valo=7,864.99 2006.285.21:28:24.43#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.21:28:24.43#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.21:28:24.43#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:24.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:28:24.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:28:24.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:28:24.43#ibcon#enter wrdev, iclass 21, count 0 2006.285.21:28:24.43#ibcon#first serial, iclass 21, count 0 2006.285.21:28:24.43#ibcon#enter sib2, iclass 21, count 0 2006.285.21:28:24.43#ibcon#flushed, iclass 21, count 0 2006.285.21:28:24.43#ibcon#about to write, iclass 21, count 0 2006.285.21:28:24.43#ibcon#wrote, iclass 21, count 0 2006.285.21:28:24.43#ibcon#about to read 3, iclass 21, count 0 2006.285.21:28:24.45#ibcon#read 3, iclass 21, count 0 2006.285.21:28:24.45#ibcon#about to read 4, iclass 21, count 0 2006.285.21:28:24.45#ibcon#read 4, iclass 21, count 0 2006.285.21:28:24.45#ibcon#about to read 5, iclass 21, count 0 2006.285.21:28:24.45#ibcon#read 5, iclass 21, count 0 2006.285.21:28:24.45#ibcon#about to read 6, iclass 21, count 0 2006.285.21:28:24.45#ibcon#read 6, iclass 21, count 0 2006.285.21:28:24.45#ibcon#end of sib2, iclass 21, count 0 2006.285.21:28:24.45#ibcon#*mode == 0, iclass 21, count 0 2006.285.21:28:24.45#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.21:28:24.45#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:28:24.45#ibcon#*before write, iclass 21, count 0 2006.285.21:28:24.45#ibcon#enter sib2, iclass 21, count 0 2006.285.21:28:24.45#ibcon#flushed, iclass 21, count 0 2006.285.21:28:24.45#ibcon#about to write, iclass 21, count 0 2006.285.21:28:24.45#ibcon#wrote, iclass 21, count 0 2006.285.21:28:24.45#ibcon#about to read 3, iclass 21, count 0 2006.285.21:28:24.49#ibcon#read 3, iclass 21, count 0 2006.285.21:28:24.49#ibcon#about to read 4, iclass 21, count 0 2006.285.21:28:24.49#ibcon#read 4, iclass 21, count 0 2006.285.21:28:24.49#ibcon#about to read 5, iclass 21, count 0 2006.285.21:28:24.49#ibcon#read 5, iclass 21, count 0 2006.285.21:28:24.49#ibcon#about to read 6, iclass 21, count 0 2006.285.21:28:24.49#ibcon#read 6, iclass 21, count 0 2006.285.21:28:24.49#ibcon#end of sib2, iclass 21, count 0 2006.285.21:28:24.49#ibcon#*after write, iclass 21, count 0 2006.285.21:28:24.49#ibcon#*before return 0, iclass 21, count 0 2006.285.21:28:24.49#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:28:24.49#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:28:24.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.21:28:24.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.21:28:24.49$vck44/va=7,4 2006.285.21:28:24.49#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.21:28:24.49#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.21:28:24.49#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:24.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:28:24.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:28:24.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:28:24.55#ibcon#enter wrdev, iclass 23, count 2 2006.285.21:28:24.55#ibcon#first serial, iclass 23, count 2 2006.285.21:28:24.55#ibcon#enter sib2, iclass 23, count 2 2006.285.21:28:24.55#ibcon#flushed, iclass 23, count 2 2006.285.21:28:24.55#ibcon#about to write, iclass 23, count 2 2006.285.21:28:24.55#ibcon#wrote, iclass 23, count 2 2006.285.21:28:24.55#ibcon#about to read 3, iclass 23, count 2 2006.285.21:28:24.57#ibcon#read 3, iclass 23, count 2 2006.285.21:28:24.57#ibcon#about to read 4, iclass 23, count 2 2006.285.21:28:24.57#ibcon#read 4, iclass 23, count 2 2006.285.21:28:24.57#ibcon#about to read 5, iclass 23, count 2 2006.285.21:28:24.57#ibcon#read 5, iclass 23, count 2 2006.285.21:28:24.57#ibcon#about to read 6, iclass 23, count 2 2006.285.21:28:24.57#ibcon#read 6, iclass 23, count 2 2006.285.21:28:24.57#ibcon#end of sib2, iclass 23, count 2 2006.285.21:28:24.57#ibcon#*mode == 0, iclass 23, count 2 2006.285.21:28:24.57#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.21:28:24.57#ibcon#[25=AT07-04\r\n] 2006.285.21:28:24.57#ibcon#*before write, iclass 23, count 2 2006.285.21:28:24.57#ibcon#enter sib2, iclass 23, count 2 2006.285.21:28:24.57#ibcon#flushed, iclass 23, count 2 2006.285.21:28:24.57#ibcon#about to write, iclass 23, count 2 2006.285.21:28:24.57#ibcon#wrote, iclass 23, count 2 2006.285.21:28:24.57#ibcon#about to read 3, iclass 23, count 2 2006.285.21:28:24.60#ibcon#read 3, iclass 23, count 2 2006.285.21:28:24.60#ibcon#about to read 4, iclass 23, count 2 2006.285.21:28:24.60#ibcon#read 4, iclass 23, count 2 2006.285.21:28:24.60#ibcon#about to read 5, iclass 23, count 2 2006.285.21:28:24.60#ibcon#read 5, iclass 23, count 2 2006.285.21:28:24.60#ibcon#about to read 6, iclass 23, count 2 2006.285.21:28:24.60#ibcon#read 6, iclass 23, count 2 2006.285.21:28:24.60#ibcon#end of sib2, iclass 23, count 2 2006.285.21:28:24.60#ibcon#*after write, iclass 23, count 2 2006.285.21:28:24.60#ibcon#*before return 0, iclass 23, count 2 2006.285.21:28:24.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:28:24.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:28:24.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.21:28:24.60#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:24.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:28:24.72#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:28:24.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:28:24.72#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:28:24.72#ibcon#first serial, iclass 23, count 0 2006.285.21:28:24.72#ibcon#enter sib2, iclass 23, count 0 2006.285.21:28:24.72#ibcon#flushed, iclass 23, count 0 2006.285.21:28:24.72#ibcon#about to write, iclass 23, count 0 2006.285.21:28:24.72#ibcon#wrote, iclass 23, count 0 2006.285.21:28:24.72#ibcon#about to read 3, iclass 23, count 0 2006.285.21:28:24.74#ibcon#read 3, iclass 23, count 0 2006.285.21:28:24.74#ibcon#about to read 4, iclass 23, count 0 2006.285.21:28:24.74#ibcon#read 4, iclass 23, count 0 2006.285.21:28:24.74#ibcon#about to read 5, iclass 23, count 0 2006.285.21:28:24.74#ibcon#read 5, iclass 23, count 0 2006.285.21:28:24.74#ibcon#about to read 6, iclass 23, count 0 2006.285.21:28:24.74#ibcon#read 6, iclass 23, count 0 2006.285.21:28:24.74#ibcon#end of sib2, iclass 23, count 0 2006.285.21:28:24.74#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:28:24.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:28:24.74#ibcon#[25=USB\r\n] 2006.285.21:28:24.74#ibcon#*before write, iclass 23, count 0 2006.285.21:28:24.74#ibcon#enter sib2, iclass 23, count 0 2006.285.21:28:24.74#ibcon#flushed, iclass 23, count 0 2006.285.21:28:24.74#ibcon#about to write, iclass 23, count 0 2006.285.21:28:24.74#ibcon#wrote, iclass 23, count 0 2006.285.21:28:24.74#ibcon#about to read 3, iclass 23, count 0 2006.285.21:28:24.77#ibcon#read 3, iclass 23, count 0 2006.285.21:28:24.77#ibcon#about to read 4, iclass 23, count 0 2006.285.21:28:24.77#ibcon#read 4, iclass 23, count 0 2006.285.21:28:24.77#ibcon#about to read 5, iclass 23, count 0 2006.285.21:28:24.77#ibcon#read 5, iclass 23, count 0 2006.285.21:28:24.77#ibcon#about to read 6, iclass 23, count 0 2006.285.21:28:24.77#ibcon#read 6, iclass 23, count 0 2006.285.21:28:24.77#ibcon#end of sib2, iclass 23, count 0 2006.285.21:28:24.77#ibcon#*after write, iclass 23, count 0 2006.285.21:28:24.77#ibcon#*before return 0, iclass 23, count 0 2006.285.21:28:24.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:28:24.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:28:24.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:28:24.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:28:24.77$vck44/valo=8,884.99 2006.285.21:28:24.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.21:28:24.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.21:28:24.77#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:24.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:28:24.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:28:24.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:28:24.77#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:28:24.77#ibcon#first serial, iclass 25, count 0 2006.285.21:28:24.77#ibcon#enter sib2, iclass 25, count 0 2006.285.21:28:24.77#ibcon#flushed, iclass 25, count 0 2006.285.21:28:24.77#ibcon#about to write, iclass 25, count 0 2006.285.21:28:24.77#ibcon#wrote, iclass 25, count 0 2006.285.21:28:24.77#ibcon#about to read 3, iclass 25, count 0 2006.285.21:28:24.79#ibcon#read 3, iclass 25, count 0 2006.285.21:28:24.79#ibcon#about to read 4, iclass 25, count 0 2006.285.21:28:24.79#ibcon#read 4, iclass 25, count 0 2006.285.21:28:24.79#ibcon#about to read 5, iclass 25, count 0 2006.285.21:28:24.79#ibcon#read 5, iclass 25, count 0 2006.285.21:28:24.79#ibcon#about to read 6, iclass 25, count 0 2006.285.21:28:24.79#ibcon#read 6, iclass 25, count 0 2006.285.21:28:24.79#ibcon#end of sib2, iclass 25, count 0 2006.285.21:28:24.79#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:28:24.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:28:24.79#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:28:24.79#ibcon#*before write, iclass 25, count 0 2006.285.21:28:24.79#ibcon#enter sib2, iclass 25, count 0 2006.285.21:28:24.79#ibcon#flushed, iclass 25, count 0 2006.285.21:28:24.79#ibcon#about to write, iclass 25, count 0 2006.285.21:28:24.79#ibcon#wrote, iclass 25, count 0 2006.285.21:28:24.79#ibcon#about to read 3, iclass 25, count 0 2006.285.21:28:24.83#ibcon#read 3, iclass 25, count 0 2006.285.21:28:24.83#ibcon#about to read 4, iclass 25, count 0 2006.285.21:28:24.83#ibcon#read 4, iclass 25, count 0 2006.285.21:28:24.83#ibcon#about to read 5, iclass 25, count 0 2006.285.21:28:24.83#ibcon#read 5, iclass 25, count 0 2006.285.21:28:24.83#ibcon#about to read 6, iclass 25, count 0 2006.285.21:28:24.83#ibcon#read 6, iclass 25, count 0 2006.285.21:28:24.83#ibcon#end of sib2, iclass 25, count 0 2006.285.21:28:24.83#ibcon#*after write, iclass 25, count 0 2006.285.21:28:24.83#ibcon#*before return 0, iclass 25, count 0 2006.285.21:28:24.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:28:24.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:28:24.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:28:24.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:28:24.83$vck44/va=8,3 2006.285.21:28:24.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.21:28:24.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.21:28:24.83#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:24.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:28:24.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:28:24.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:28:24.89#ibcon#enter wrdev, iclass 27, count 2 2006.285.21:28:24.89#ibcon#first serial, iclass 27, count 2 2006.285.21:28:24.89#ibcon#enter sib2, iclass 27, count 2 2006.285.21:28:24.89#ibcon#flushed, iclass 27, count 2 2006.285.21:28:24.89#ibcon#about to write, iclass 27, count 2 2006.285.21:28:24.89#ibcon#wrote, iclass 27, count 2 2006.285.21:28:24.89#ibcon#about to read 3, iclass 27, count 2 2006.285.21:28:24.91#ibcon#read 3, iclass 27, count 2 2006.285.21:28:24.91#ibcon#about to read 4, iclass 27, count 2 2006.285.21:28:24.91#ibcon#read 4, iclass 27, count 2 2006.285.21:28:24.91#ibcon#about to read 5, iclass 27, count 2 2006.285.21:28:24.91#ibcon#read 5, iclass 27, count 2 2006.285.21:28:24.91#ibcon#about to read 6, iclass 27, count 2 2006.285.21:28:24.91#ibcon#read 6, iclass 27, count 2 2006.285.21:28:24.91#ibcon#end of sib2, iclass 27, count 2 2006.285.21:28:24.91#ibcon#*mode == 0, iclass 27, count 2 2006.285.21:28:24.91#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.21:28:24.91#ibcon#[25=AT08-03\r\n] 2006.285.21:28:24.91#ibcon#*before write, iclass 27, count 2 2006.285.21:28:24.91#ibcon#enter sib2, iclass 27, count 2 2006.285.21:28:24.91#ibcon#flushed, iclass 27, count 2 2006.285.21:28:24.91#ibcon#about to write, iclass 27, count 2 2006.285.21:28:24.91#ibcon#wrote, iclass 27, count 2 2006.285.21:28:24.91#ibcon#about to read 3, iclass 27, count 2 2006.285.21:28:24.94#ibcon#read 3, iclass 27, count 2 2006.285.21:28:24.94#ibcon#about to read 4, iclass 27, count 2 2006.285.21:28:24.94#ibcon#read 4, iclass 27, count 2 2006.285.21:28:24.94#ibcon#about to read 5, iclass 27, count 2 2006.285.21:28:24.94#ibcon#read 5, iclass 27, count 2 2006.285.21:28:24.94#ibcon#about to read 6, iclass 27, count 2 2006.285.21:28:24.94#ibcon#read 6, iclass 27, count 2 2006.285.21:28:24.94#ibcon#end of sib2, iclass 27, count 2 2006.285.21:28:24.94#ibcon#*after write, iclass 27, count 2 2006.285.21:28:24.94#ibcon#*before return 0, iclass 27, count 2 2006.285.21:28:24.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:28:24.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:28:24.94#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.21:28:24.94#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:24.94#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:28:25.06#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:28:25.06#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:28:25.06#ibcon#enter wrdev, iclass 27, count 0 2006.285.21:28:25.06#ibcon#first serial, iclass 27, count 0 2006.285.21:28:25.06#ibcon#enter sib2, iclass 27, count 0 2006.285.21:28:25.06#ibcon#flushed, iclass 27, count 0 2006.285.21:28:25.06#ibcon#about to write, iclass 27, count 0 2006.285.21:28:25.06#ibcon#wrote, iclass 27, count 0 2006.285.21:28:25.06#ibcon#about to read 3, iclass 27, count 0 2006.285.21:28:25.08#ibcon#read 3, iclass 27, count 0 2006.285.21:28:25.08#ibcon#about to read 4, iclass 27, count 0 2006.285.21:28:25.08#ibcon#read 4, iclass 27, count 0 2006.285.21:28:25.08#ibcon#about to read 5, iclass 27, count 0 2006.285.21:28:25.08#ibcon#read 5, iclass 27, count 0 2006.285.21:28:25.08#ibcon#about to read 6, iclass 27, count 0 2006.285.21:28:25.08#ibcon#read 6, iclass 27, count 0 2006.285.21:28:25.08#ibcon#end of sib2, iclass 27, count 0 2006.285.21:28:25.08#ibcon#*mode == 0, iclass 27, count 0 2006.285.21:28:25.08#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.21:28:25.08#ibcon#[25=USB\r\n] 2006.285.21:28:25.08#ibcon#*before write, iclass 27, count 0 2006.285.21:28:25.08#ibcon#enter sib2, iclass 27, count 0 2006.285.21:28:25.08#ibcon#flushed, iclass 27, count 0 2006.285.21:28:25.08#ibcon#about to write, iclass 27, count 0 2006.285.21:28:25.08#ibcon#wrote, iclass 27, count 0 2006.285.21:28:25.08#ibcon#about to read 3, iclass 27, count 0 2006.285.21:28:25.11#ibcon#read 3, iclass 27, count 0 2006.285.21:28:25.11#ibcon#about to read 4, iclass 27, count 0 2006.285.21:28:25.11#ibcon#read 4, iclass 27, count 0 2006.285.21:28:25.11#ibcon#about to read 5, iclass 27, count 0 2006.285.21:28:25.11#ibcon#read 5, iclass 27, count 0 2006.285.21:28:25.11#ibcon#about to read 6, iclass 27, count 0 2006.285.21:28:25.11#ibcon#read 6, iclass 27, count 0 2006.285.21:28:25.11#ibcon#end of sib2, iclass 27, count 0 2006.285.21:28:25.11#ibcon#*after write, iclass 27, count 0 2006.285.21:28:25.11#ibcon#*before return 0, iclass 27, count 0 2006.285.21:28:25.11#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:28:25.11#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:28:25.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.21:28:25.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.21:28:25.11$vck44/vblo=1,629.99 2006.285.21:28:25.11#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.21:28:25.11#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.21:28:25.11#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:25.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:28:25.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:28:25.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:28:25.11#ibcon#enter wrdev, iclass 29, count 0 2006.285.21:28:25.11#ibcon#first serial, iclass 29, count 0 2006.285.21:28:25.11#ibcon#enter sib2, iclass 29, count 0 2006.285.21:28:25.11#ibcon#flushed, iclass 29, count 0 2006.285.21:28:25.11#ibcon#about to write, iclass 29, count 0 2006.285.21:28:25.11#ibcon#wrote, iclass 29, count 0 2006.285.21:28:25.11#ibcon#about to read 3, iclass 29, count 0 2006.285.21:28:25.13#ibcon#read 3, iclass 29, count 0 2006.285.21:28:25.13#ibcon#about to read 4, iclass 29, count 0 2006.285.21:28:25.13#ibcon#read 4, iclass 29, count 0 2006.285.21:28:25.13#ibcon#about to read 5, iclass 29, count 0 2006.285.21:28:25.13#ibcon#read 5, iclass 29, count 0 2006.285.21:28:25.13#ibcon#about to read 6, iclass 29, count 0 2006.285.21:28:25.13#ibcon#read 6, iclass 29, count 0 2006.285.21:28:25.13#ibcon#end of sib2, iclass 29, count 0 2006.285.21:28:25.13#ibcon#*mode == 0, iclass 29, count 0 2006.285.21:28:25.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.21:28:25.13#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:28:25.13#ibcon#*before write, iclass 29, count 0 2006.285.21:28:25.13#ibcon#enter sib2, iclass 29, count 0 2006.285.21:28:25.13#ibcon#flushed, iclass 29, count 0 2006.285.21:28:25.13#ibcon#about to write, iclass 29, count 0 2006.285.21:28:25.13#ibcon#wrote, iclass 29, count 0 2006.285.21:28:25.13#ibcon#about to read 3, iclass 29, count 0 2006.285.21:28:25.17#ibcon#read 3, iclass 29, count 0 2006.285.21:28:25.17#ibcon#about to read 4, iclass 29, count 0 2006.285.21:28:25.17#ibcon#read 4, iclass 29, count 0 2006.285.21:28:25.17#ibcon#about to read 5, iclass 29, count 0 2006.285.21:28:25.17#ibcon#read 5, iclass 29, count 0 2006.285.21:28:25.17#ibcon#about to read 6, iclass 29, count 0 2006.285.21:28:25.17#ibcon#read 6, iclass 29, count 0 2006.285.21:28:25.17#ibcon#end of sib2, iclass 29, count 0 2006.285.21:28:25.17#ibcon#*after write, iclass 29, count 0 2006.285.21:28:25.17#ibcon#*before return 0, iclass 29, count 0 2006.285.21:28:25.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:28:25.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:28:25.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.21:28:25.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.21:28:25.17$vck44/vb=1,4 2006.285.21:28:25.17#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.21:28:25.17#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.21:28:25.17#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:25.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:28:25.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:28:25.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:28:25.17#ibcon#enter wrdev, iclass 31, count 2 2006.285.21:28:25.17#ibcon#first serial, iclass 31, count 2 2006.285.21:28:25.17#ibcon#enter sib2, iclass 31, count 2 2006.285.21:28:25.17#ibcon#flushed, iclass 31, count 2 2006.285.21:28:25.17#ibcon#about to write, iclass 31, count 2 2006.285.21:28:25.17#ibcon#wrote, iclass 31, count 2 2006.285.21:28:25.17#ibcon#about to read 3, iclass 31, count 2 2006.285.21:28:25.19#ibcon#read 3, iclass 31, count 2 2006.285.21:28:25.19#ibcon#about to read 4, iclass 31, count 2 2006.285.21:28:25.19#ibcon#read 4, iclass 31, count 2 2006.285.21:28:25.19#ibcon#about to read 5, iclass 31, count 2 2006.285.21:28:25.19#ibcon#read 5, iclass 31, count 2 2006.285.21:28:25.19#ibcon#about to read 6, iclass 31, count 2 2006.285.21:28:25.19#ibcon#read 6, iclass 31, count 2 2006.285.21:28:25.19#ibcon#end of sib2, iclass 31, count 2 2006.285.21:28:25.19#ibcon#*mode == 0, iclass 31, count 2 2006.285.21:28:25.19#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.21:28:25.19#ibcon#[27=AT01-04\r\n] 2006.285.21:28:25.19#ibcon#*before write, iclass 31, count 2 2006.285.21:28:25.19#ibcon#enter sib2, iclass 31, count 2 2006.285.21:28:25.19#ibcon#flushed, iclass 31, count 2 2006.285.21:28:25.19#ibcon#about to write, iclass 31, count 2 2006.285.21:28:25.19#ibcon#wrote, iclass 31, count 2 2006.285.21:28:25.19#ibcon#about to read 3, iclass 31, count 2 2006.285.21:28:25.22#ibcon#read 3, iclass 31, count 2 2006.285.21:28:25.22#ibcon#about to read 4, iclass 31, count 2 2006.285.21:28:25.22#ibcon#read 4, iclass 31, count 2 2006.285.21:28:25.22#ibcon#about to read 5, iclass 31, count 2 2006.285.21:28:25.22#ibcon#read 5, iclass 31, count 2 2006.285.21:28:25.22#ibcon#about to read 6, iclass 31, count 2 2006.285.21:28:25.22#ibcon#read 6, iclass 31, count 2 2006.285.21:28:25.22#ibcon#end of sib2, iclass 31, count 2 2006.285.21:28:25.22#ibcon#*after write, iclass 31, count 2 2006.285.21:28:25.22#ibcon#*before return 0, iclass 31, count 2 2006.285.21:28:25.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:28:25.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:28:25.22#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.21:28:25.22#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:25.22#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:28:25.34#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:28:25.34#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:28:25.34#ibcon#enter wrdev, iclass 31, count 0 2006.285.21:28:25.34#ibcon#first serial, iclass 31, count 0 2006.285.21:28:25.34#ibcon#enter sib2, iclass 31, count 0 2006.285.21:28:25.34#ibcon#flushed, iclass 31, count 0 2006.285.21:28:25.34#ibcon#about to write, iclass 31, count 0 2006.285.21:28:25.34#ibcon#wrote, iclass 31, count 0 2006.285.21:28:25.34#ibcon#about to read 3, iclass 31, count 0 2006.285.21:28:25.36#ibcon#read 3, iclass 31, count 0 2006.285.21:28:25.36#ibcon#about to read 4, iclass 31, count 0 2006.285.21:28:25.36#ibcon#read 4, iclass 31, count 0 2006.285.21:28:25.36#ibcon#about to read 5, iclass 31, count 0 2006.285.21:28:25.36#ibcon#read 5, iclass 31, count 0 2006.285.21:28:25.36#ibcon#about to read 6, iclass 31, count 0 2006.285.21:28:25.36#ibcon#read 6, iclass 31, count 0 2006.285.21:28:25.36#ibcon#end of sib2, iclass 31, count 0 2006.285.21:28:25.36#ibcon#*mode == 0, iclass 31, count 0 2006.285.21:28:25.36#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.21:28:25.36#ibcon#[27=USB\r\n] 2006.285.21:28:25.36#ibcon#*before write, iclass 31, count 0 2006.285.21:28:25.36#ibcon#enter sib2, iclass 31, count 0 2006.285.21:28:25.36#ibcon#flushed, iclass 31, count 0 2006.285.21:28:25.36#ibcon#about to write, iclass 31, count 0 2006.285.21:28:25.36#ibcon#wrote, iclass 31, count 0 2006.285.21:28:25.36#ibcon#about to read 3, iclass 31, count 0 2006.285.21:28:25.39#ibcon#read 3, iclass 31, count 0 2006.285.21:28:25.39#ibcon#about to read 4, iclass 31, count 0 2006.285.21:28:25.39#ibcon#read 4, iclass 31, count 0 2006.285.21:28:25.39#ibcon#about to read 5, iclass 31, count 0 2006.285.21:28:25.39#ibcon#read 5, iclass 31, count 0 2006.285.21:28:25.39#ibcon#about to read 6, iclass 31, count 0 2006.285.21:28:25.39#ibcon#read 6, iclass 31, count 0 2006.285.21:28:25.39#ibcon#end of sib2, iclass 31, count 0 2006.285.21:28:25.39#ibcon#*after write, iclass 31, count 0 2006.285.21:28:25.39#ibcon#*before return 0, iclass 31, count 0 2006.285.21:28:25.39#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:28:25.39#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:28:25.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.21:28:25.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.21:28:25.39$vck44/vblo=2,634.99 2006.285.21:28:25.39#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.21:28:25.39#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.21:28:25.39#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:25.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:28:25.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:28:25.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:28:25.39#ibcon#enter wrdev, iclass 33, count 0 2006.285.21:28:25.39#ibcon#first serial, iclass 33, count 0 2006.285.21:28:25.39#ibcon#enter sib2, iclass 33, count 0 2006.285.21:28:25.39#ibcon#flushed, iclass 33, count 0 2006.285.21:28:25.39#ibcon#about to write, iclass 33, count 0 2006.285.21:28:25.39#ibcon#wrote, iclass 33, count 0 2006.285.21:28:25.39#ibcon#about to read 3, iclass 33, count 0 2006.285.21:28:25.41#ibcon#read 3, iclass 33, count 0 2006.285.21:28:25.41#ibcon#about to read 4, iclass 33, count 0 2006.285.21:28:25.41#ibcon#read 4, iclass 33, count 0 2006.285.21:28:25.41#ibcon#about to read 5, iclass 33, count 0 2006.285.21:28:25.41#ibcon#read 5, iclass 33, count 0 2006.285.21:28:25.41#ibcon#about to read 6, iclass 33, count 0 2006.285.21:28:25.41#ibcon#read 6, iclass 33, count 0 2006.285.21:28:25.41#ibcon#end of sib2, iclass 33, count 0 2006.285.21:28:25.41#ibcon#*mode == 0, iclass 33, count 0 2006.285.21:28:25.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.21:28:25.41#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:28:25.41#ibcon#*before write, iclass 33, count 0 2006.285.21:28:25.41#ibcon#enter sib2, iclass 33, count 0 2006.285.21:28:25.41#ibcon#flushed, iclass 33, count 0 2006.285.21:28:25.41#ibcon#about to write, iclass 33, count 0 2006.285.21:28:25.41#ibcon#wrote, iclass 33, count 0 2006.285.21:28:25.41#ibcon#about to read 3, iclass 33, count 0 2006.285.21:28:25.45#ibcon#read 3, iclass 33, count 0 2006.285.21:28:25.45#ibcon#about to read 4, iclass 33, count 0 2006.285.21:28:25.45#ibcon#read 4, iclass 33, count 0 2006.285.21:28:25.45#ibcon#about to read 5, iclass 33, count 0 2006.285.21:28:25.45#ibcon#read 5, iclass 33, count 0 2006.285.21:28:25.45#ibcon#about to read 6, iclass 33, count 0 2006.285.21:28:25.45#ibcon#read 6, iclass 33, count 0 2006.285.21:28:25.45#ibcon#end of sib2, iclass 33, count 0 2006.285.21:28:25.45#ibcon#*after write, iclass 33, count 0 2006.285.21:28:25.45#ibcon#*before return 0, iclass 33, count 0 2006.285.21:28:25.45#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:28:25.45#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:28:25.45#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.21:28:25.45#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.21:28:25.45$vck44/vb=2,5 2006.285.21:28:25.45#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.21:28:25.45#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.21:28:25.45#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:25.45#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:28:25.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:28:25.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:28:25.51#ibcon#enter wrdev, iclass 35, count 2 2006.285.21:28:25.51#ibcon#first serial, iclass 35, count 2 2006.285.21:28:25.51#ibcon#enter sib2, iclass 35, count 2 2006.285.21:28:25.51#ibcon#flushed, iclass 35, count 2 2006.285.21:28:25.51#ibcon#about to write, iclass 35, count 2 2006.285.21:28:25.51#ibcon#wrote, iclass 35, count 2 2006.285.21:28:25.51#ibcon#about to read 3, iclass 35, count 2 2006.285.21:28:25.53#ibcon#read 3, iclass 35, count 2 2006.285.21:28:25.53#ibcon#about to read 4, iclass 35, count 2 2006.285.21:28:25.53#ibcon#read 4, iclass 35, count 2 2006.285.21:28:25.53#ibcon#about to read 5, iclass 35, count 2 2006.285.21:28:25.53#ibcon#read 5, iclass 35, count 2 2006.285.21:28:25.53#ibcon#about to read 6, iclass 35, count 2 2006.285.21:28:25.53#ibcon#read 6, iclass 35, count 2 2006.285.21:28:25.53#ibcon#end of sib2, iclass 35, count 2 2006.285.21:28:25.53#ibcon#*mode == 0, iclass 35, count 2 2006.285.21:28:25.53#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.21:28:25.53#ibcon#[27=AT02-05\r\n] 2006.285.21:28:25.53#ibcon#*before write, iclass 35, count 2 2006.285.21:28:25.53#ibcon#enter sib2, iclass 35, count 2 2006.285.21:28:25.53#ibcon#flushed, iclass 35, count 2 2006.285.21:28:25.53#ibcon#about to write, iclass 35, count 2 2006.285.21:28:25.53#ibcon#wrote, iclass 35, count 2 2006.285.21:28:25.53#ibcon#about to read 3, iclass 35, count 2 2006.285.21:28:25.56#ibcon#read 3, iclass 35, count 2 2006.285.21:28:25.56#ibcon#about to read 4, iclass 35, count 2 2006.285.21:28:25.56#ibcon#read 4, iclass 35, count 2 2006.285.21:28:25.56#ibcon#about to read 5, iclass 35, count 2 2006.285.21:28:25.56#ibcon#read 5, iclass 35, count 2 2006.285.21:28:25.56#ibcon#about to read 6, iclass 35, count 2 2006.285.21:28:25.56#ibcon#read 6, iclass 35, count 2 2006.285.21:28:25.56#ibcon#end of sib2, iclass 35, count 2 2006.285.21:28:25.56#ibcon#*after write, iclass 35, count 2 2006.285.21:28:25.56#ibcon#*before return 0, iclass 35, count 2 2006.285.21:28:25.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:28:25.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:28:25.56#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.21:28:25.56#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:25.56#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:28:25.68#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:28:25.68#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:28:25.68#ibcon#enter wrdev, iclass 35, count 0 2006.285.21:28:25.68#ibcon#first serial, iclass 35, count 0 2006.285.21:28:25.68#ibcon#enter sib2, iclass 35, count 0 2006.285.21:28:25.68#ibcon#flushed, iclass 35, count 0 2006.285.21:28:25.68#ibcon#about to write, iclass 35, count 0 2006.285.21:28:25.68#ibcon#wrote, iclass 35, count 0 2006.285.21:28:25.68#ibcon#about to read 3, iclass 35, count 0 2006.285.21:28:25.70#ibcon#read 3, iclass 35, count 0 2006.285.21:28:25.70#ibcon#about to read 4, iclass 35, count 0 2006.285.21:28:25.70#ibcon#read 4, iclass 35, count 0 2006.285.21:28:25.70#ibcon#about to read 5, iclass 35, count 0 2006.285.21:28:25.70#ibcon#read 5, iclass 35, count 0 2006.285.21:28:25.70#ibcon#about to read 6, iclass 35, count 0 2006.285.21:28:25.70#ibcon#read 6, iclass 35, count 0 2006.285.21:28:25.70#ibcon#end of sib2, iclass 35, count 0 2006.285.21:28:25.70#ibcon#*mode == 0, iclass 35, count 0 2006.285.21:28:25.70#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.21:28:25.70#ibcon#[27=USB\r\n] 2006.285.21:28:25.70#ibcon#*before write, iclass 35, count 0 2006.285.21:28:25.70#ibcon#enter sib2, iclass 35, count 0 2006.285.21:28:25.70#ibcon#flushed, iclass 35, count 0 2006.285.21:28:25.70#ibcon#about to write, iclass 35, count 0 2006.285.21:28:25.70#ibcon#wrote, iclass 35, count 0 2006.285.21:28:25.70#ibcon#about to read 3, iclass 35, count 0 2006.285.21:28:25.73#ibcon#read 3, iclass 35, count 0 2006.285.21:28:25.73#ibcon#about to read 4, iclass 35, count 0 2006.285.21:28:25.73#ibcon#read 4, iclass 35, count 0 2006.285.21:28:25.73#ibcon#about to read 5, iclass 35, count 0 2006.285.21:28:25.73#ibcon#read 5, iclass 35, count 0 2006.285.21:28:25.73#ibcon#about to read 6, iclass 35, count 0 2006.285.21:28:25.73#ibcon#read 6, iclass 35, count 0 2006.285.21:28:25.73#ibcon#end of sib2, iclass 35, count 0 2006.285.21:28:25.73#ibcon#*after write, iclass 35, count 0 2006.285.21:28:25.73#ibcon#*before return 0, iclass 35, count 0 2006.285.21:28:25.73#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:28:25.73#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:28:25.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.21:28:25.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.21:28:25.73$vck44/vblo=3,649.99 2006.285.21:28:25.73#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.21:28:25.73#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.21:28:25.73#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:25.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:28:25.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:28:25.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:28:25.73#ibcon#enter wrdev, iclass 37, count 0 2006.285.21:28:25.73#ibcon#first serial, iclass 37, count 0 2006.285.21:28:25.73#ibcon#enter sib2, iclass 37, count 0 2006.285.21:28:25.73#ibcon#flushed, iclass 37, count 0 2006.285.21:28:25.73#ibcon#about to write, iclass 37, count 0 2006.285.21:28:25.73#ibcon#wrote, iclass 37, count 0 2006.285.21:28:25.73#ibcon#about to read 3, iclass 37, count 0 2006.285.21:28:25.75#ibcon#read 3, iclass 37, count 0 2006.285.21:28:25.85#ibcon#about to read 4, iclass 37, count 0 2006.285.21:28:25.85#ibcon#read 4, iclass 37, count 0 2006.285.21:28:25.85#ibcon#about to read 5, iclass 37, count 0 2006.285.21:28:25.85#ibcon#read 5, iclass 37, count 0 2006.285.21:28:25.85#ibcon#about to read 6, iclass 37, count 0 2006.285.21:28:25.85#ibcon#read 6, iclass 37, count 0 2006.285.21:28:25.85#ibcon#end of sib2, iclass 37, count 0 2006.285.21:28:25.85#ibcon#*mode == 0, iclass 37, count 0 2006.285.21:28:25.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.21:28:25.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:28:25.85#ibcon#*before write, iclass 37, count 0 2006.285.21:28:25.85#ibcon#enter sib2, iclass 37, count 0 2006.285.21:28:25.85#ibcon#flushed, iclass 37, count 0 2006.285.21:28:25.85#ibcon#about to write, iclass 37, count 0 2006.285.21:28:25.85#ibcon#wrote, iclass 37, count 0 2006.285.21:28:25.85#ibcon#about to read 3, iclass 37, count 0 2006.285.21:28:25.89#ibcon#read 3, iclass 37, count 0 2006.285.21:28:25.89#ibcon#about to read 4, iclass 37, count 0 2006.285.21:28:25.89#ibcon#read 4, iclass 37, count 0 2006.285.21:28:25.89#ibcon#about to read 5, iclass 37, count 0 2006.285.21:28:25.89#ibcon#read 5, iclass 37, count 0 2006.285.21:28:25.89#ibcon#about to read 6, iclass 37, count 0 2006.285.21:28:25.89#ibcon#read 6, iclass 37, count 0 2006.285.21:28:25.89#ibcon#end of sib2, iclass 37, count 0 2006.285.21:28:25.89#ibcon#*after write, iclass 37, count 0 2006.285.21:28:25.89#ibcon#*before return 0, iclass 37, count 0 2006.285.21:28:25.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:28:25.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:28:25.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.21:28:25.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.21:28:25.89$vck44/vb=3,4 2006.285.21:28:25.89#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.21:28:25.89#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.21:28:25.89#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:25.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:28:25.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:28:25.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:28:25.89#ibcon#enter wrdev, iclass 39, count 2 2006.285.21:28:25.89#ibcon#first serial, iclass 39, count 2 2006.285.21:28:25.89#ibcon#enter sib2, iclass 39, count 2 2006.285.21:28:25.89#ibcon#flushed, iclass 39, count 2 2006.285.21:28:25.89#ibcon#about to write, iclass 39, count 2 2006.285.21:28:25.89#ibcon#wrote, iclass 39, count 2 2006.285.21:28:25.89#ibcon#about to read 3, iclass 39, count 2 2006.285.21:28:25.91#ibcon#read 3, iclass 39, count 2 2006.285.21:28:25.91#ibcon#about to read 4, iclass 39, count 2 2006.285.21:28:25.91#ibcon#read 4, iclass 39, count 2 2006.285.21:28:25.91#ibcon#about to read 5, iclass 39, count 2 2006.285.21:28:25.91#ibcon#read 5, iclass 39, count 2 2006.285.21:28:25.91#ibcon#about to read 6, iclass 39, count 2 2006.285.21:28:25.91#ibcon#read 6, iclass 39, count 2 2006.285.21:28:25.91#ibcon#end of sib2, iclass 39, count 2 2006.285.21:28:25.91#ibcon#*mode == 0, iclass 39, count 2 2006.285.21:28:25.91#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.21:28:25.91#ibcon#[27=AT03-04\r\n] 2006.285.21:28:25.91#ibcon#*before write, iclass 39, count 2 2006.285.21:28:25.91#ibcon#enter sib2, iclass 39, count 2 2006.285.21:28:25.91#ibcon#flushed, iclass 39, count 2 2006.285.21:28:25.91#ibcon#about to write, iclass 39, count 2 2006.285.21:28:25.91#ibcon#wrote, iclass 39, count 2 2006.285.21:28:25.91#ibcon#about to read 3, iclass 39, count 2 2006.285.21:28:25.94#ibcon#read 3, iclass 39, count 2 2006.285.21:28:25.94#ibcon#about to read 4, iclass 39, count 2 2006.285.21:28:25.94#ibcon#read 4, iclass 39, count 2 2006.285.21:28:25.94#ibcon#about to read 5, iclass 39, count 2 2006.285.21:28:25.94#ibcon#read 5, iclass 39, count 2 2006.285.21:28:25.94#ibcon#about to read 6, iclass 39, count 2 2006.285.21:28:25.94#ibcon#read 6, iclass 39, count 2 2006.285.21:28:25.94#ibcon#end of sib2, iclass 39, count 2 2006.285.21:28:25.94#ibcon#*after write, iclass 39, count 2 2006.285.21:28:25.94#ibcon#*before return 0, iclass 39, count 2 2006.285.21:28:25.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:28:25.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:28:25.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.21:28:25.94#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:25.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:28:26.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:28:26.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:28:26.06#ibcon#enter wrdev, iclass 39, count 0 2006.285.21:28:26.06#ibcon#first serial, iclass 39, count 0 2006.285.21:28:26.06#ibcon#enter sib2, iclass 39, count 0 2006.285.21:28:26.06#ibcon#flushed, iclass 39, count 0 2006.285.21:28:26.06#ibcon#about to write, iclass 39, count 0 2006.285.21:28:26.06#ibcon#wrote, iclass 39, count 0 2006.285.21:28:26.06#ibcon#about to read 3, iclass 39, count 0 2006.285.21:28:26.08#ibcon#read 3, iclass 39, count 0 2006.285.21:28:26.08#ibcon#about to read 4, iclass 39, count 0 2006.285.21:28:26.08#ibcon#read 4, iclass 39, count 0 2006.285.21:28:26.08#ibcon#about to read 5, iclass 39, count 0 2006.285.21:28:26.08#ibcon#read 5, iclass 39, count 0 2006.285.21:28:26.08#ibcon#about to read 6, iclass 39, count 0 2006.285.21:28:26.08#ibcon#read 6, iclass 39, count 0 2006.285.21:28:26.08#ibcon#end of sib2, iclass 39, count 0 2006.285.21:28:26.08#ibcon#*mode == 0, iclass 39, count 0 2006.285.21:28:26.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.21:28:26.08#ibcon#[27=USB\r\n] 2006.285.21:28:26.08#ibcon#*before write, iclass 39, count 0 2006.285.21:28:26.08#ibcon#enter sib2, iclass 39, count 0 2006.285.21:28:26.08#ibcon#flushed, iclass 39, count 0 2006.285.21:28:26.08#ibcon#about to write, iclass 39, count 0 2006.285.21:28:26.08#ibcon#wrote, iclass 39, count 0 2006.285.21:28:26.08#ibcon#about to read 3, iclass 39, count 0 2006.285.21:28:26.11#ibcon#read 3, iclass 39, count 0 2006.285.21:28:26.11#ibcon#about to read 4, iclass 39, count 0 2006.285.21:28:26.11#ibcon#read 4, iclass 39, count 0 2006.285.21:28:26.11#ibcon#about to read 5, iclass 39, count 0 2006.285.21:28:26.11#ibcon#read 5, iclass 39, count 0 2006.285.21:28:26.11#ibcon#about to read 6, iclass 39, count 0 2006.285.21:28:26.11#ibcon#read 6, iclass 39, count 0 2006.285.21:28:26.11#ibcon#end of sib2, iclass 39, count 0 2006.285.21:28:26.11#ibcon#*after write, iclass 39, count 0 2006.285.21:28:26.11#ibcon#*before return 0, iclass 39, count 0 2006.285.21:28:26.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:28:26.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:28:26.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.21:28:26.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.21:28:26.11$vck44/vblo=4,679.99 2006.285.21:28:26.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.21:28:26.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.21:28:26.11#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:26.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:28:26.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:28:26.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:28:26.11#ibcon#enter wrdev, iclass 3, count 0 2006.285.21:28:26.11#ibcon#first serial, iclass 3, count 0 2006.285.21:28:26.11#ibcon#enter sib2, iclass 3, count 0 2006.285.21:28:26.11#ibcon#flushed, iclass 3, count 0 2006.285.21:28:26.11#ibcon#about to write, iclass 3, count 0 2006.285.21:28:26.11#ibcon#wrote, iclass 3, count 0 2006.285.21:28:26.11#ibcon#about to read 3, iclass 3, count 0 2006.285.21:28:26.13#ibcon#read 3, iclass 3, count 0 2006.285.21:28:26.13#ibcon#about to read 4, iclass 3, count 0 2006.285.21:28:26.13#ibcon#read 4, iclass 3, count 0 2006.285.21:28:26.13#ibcon#about to read 5, iclass 3, count 0 2006.285.21:28:26.13#ibcon#read 5, iclass 3, count 0 2006.285.21:28:26.13#ibcon#about to read 6, iclass 3, count 0 2006.285.21:28:26.13#ibcon#read 6, iclass 3, count 0 2006.285.21:28:26.13#ibcon#end of sib2, iclass 3, count 0 2006.285.21:28:26.13#ibcon#*mode == 0, iclass 3, count 0 2006.285.21:28:26.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.21:28:26.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:28:26.13#ibcon#*before write, iclass 3, count 0 2006.285.21:28:26.13#ibcon#enter sib2, iclass 3, count 0 2006.285.21:28:26.13#ibcon#flushed, iclass 3, count 0 2006.285.21:28:26.13#ibcon#about to write, iclass 3, count 0 2006.285.21:28:26.13#ibcon#wrote, iclass 3, count 0 2006.285.21:28:26.13#ibcon#about to read 3, iclass 3, count 0 2006.285.21:28:26.17#ibcon#read 3, iclass 3, count 0 2006.285.21:28:26.17#ibcon#about to read 4, iclass 3, count 0 2006.285.21:28:26.17#ibcon#read 4, iclass 3, count 0 2006.285.21:28:26.17#ibcon#about to read 5, iclass 3, count 0 2006.285.21:28:26.17#ibcon#read 5, iclass 3, count 0 2006.285.21:28:26.17#ibcon#about to read 6, iclass 3, count 0 2006.285.21:28:26.17#ibcon#read 6, iclass 3, count 0 2006.285.21:28:26.17#ibcon#end of sib2, iclass 3, count 0 2006.285.21:28:26.17#ibcon#*after write, iclass 3, count 0 2006.285.21:28:26.17#ibcon#*before return 0, iclass 3, count 0 2006.285.21:28:26.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:28:26.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:28:26.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.21:28:26.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.21:28:26.17$vck44/vb=4,5 2006.285.21:28:26.17#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.21:28:26.17#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.21:28:26.17#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:26.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:28:26.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:28:26.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:28:26.23#ibcon#enter wrdev, iclass 5, count 2 2006.285.21:28:26.23#ibcon#first serial, iclass 5, count 2 2006.285.21:28:26.23#ibcon#enter sib2, iclass 5, count 2 2006.285.21:28:26.23#ibcon#flushed, iclass 5, count 2 2006.285.21:28:26.23#ibcon#about to write, iclass 5, count 2 2006.285.21:28:26.23#ibcon#wrote, iclass 5, count 2 2006.285.21:28:26.23#ibcon#about to read 3, iclass 5, count 2 2006.285.21:28:26.25#ibcon#read 3, iclass 5, count 2 2006.285.21:28:26.25#ibcon#about to read 4, iclass 5, count 2 2006.285.21:28:26.25#ibcon#read 4, iclass 5, count 2 2006.285.21:28:26.25#ibcon#about to read 5, iclass 5, count 2 2006.285.21:28:26.25#ibcon#read 5, iclass 5, count 2 2006.285.21:28:26.25#ibcon#about to read 6, iclass 5, count 2 2006.285.21:28:26.25#ibcon#read 6, iclass 5, count 2 2006.285.21:28:26.25#ibcon#end of sib2, iclass 5, count 2 2006.285.21:28:26.25#ibcon#*mode == 0, iclass 5, count 2 2006.285.21:28:26.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.21:28:26.25#ibcon#[27=AT04-05\r\n] 2006.285.21:28:26.25#ibcon#*before write, iclass 5, count 2 2006.285.21:28:26.25#ibcon#enter sib2, iclass 5, count 2 2006.285.21:28:26.25#ibcon#flushed, iclass 5, count 2 2006.285.21:28:26.25#ibcon#about to write, iclass 5, count 2 2006.285.21:28:26.25#ibcon#wrote, iclass 5, count 2 2006.285.21:28:26.25#ibcon#about to read 3, iclass 5, count 2 2006.285.21:28:26.28#ibcon#read 3, iclass 5, count 2 2006.285.21:28:26.28#ibcon#about to read 4, iclass 5, count 2 2006.285.21:28:26.28#ibcon#read 4, iclass 5, count 2 2006.285.21:28:26.28#ibcon#about to read 5, iclass 5, count 2 2006.285.21:28:26.28#ibcon#read 5, iclass 5, count 2 2006.285.21:28:26.28#ibcon#about to read 6, iclass 5, count 2 2006.285.21:28:26.28#ibcon#read 6, iclass 5, count 2 2006.285.21:28:26.28#ibcon#end of sib2, iclass 5, count 2 2006.285.21:28:26.28#ibcon#*after write, iclass 5, count 2 2006.285.21:28:26.28#ibcon#*before return 0, iclass 5, count 2 2006.285.21:28:26.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:28:26.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:28:26.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.21:28:26.28#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:26.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:28:26.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:28:26.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:28:26.40#ibcon#enter wrdev, iclass 5, count 0 2006.285.21:28:26.40#ibcon#first serial, iclass 5, count 0 2006.285.21:28:26.40#ibcon#enter sib2, iclass 5, count 0 2006.285.21:28:26.40#ibcon#flushed, iclass 5, count 0 2006.285.21:28:26.40#ibcon#about to write, iclass 5, count 0 2006.285.21:28:26.40#ibcon#wrote, iclass 5, count 0 2006.285.21:28:26.40#ibcon#about to read 3, iclass 5, count 0 2006.285.21:28:26.42#ibcon#read 3, iclass 5, count 0 2006.285.21:28:26.42#ibcon#about to read 4, iclass 5, count 0 2006.285.21:28:26.42#ibcon#read 4, iclass 5, count 0 2006.285.21:28:26.42#ibcon#about to read 5, iclass 5, count 0 2006.285.21:28:26.42#ibcon#read 5, iclass 5, count 0 2006.285.21:28:26.42#ibcon#about to read 6, iclass 5, count 0 2006.285.21:28:26.42#ibcon#read 6, iclass 5, count 0 2006.285.21:28:26.42#ibcon#end of sib2, iclass 5, count 0 2006.285.21:28:26.42#ibcon#*mode == 0, iclass 5, count 0 2006.285.21:28:26.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.21:28:26.42#ibcon#[27=USB\r\n] 2006.285.21:28:26.42#ibcon#*before write, iclass 5, count 0 2006.285.21:28:26.42#ibcon#enter sib2, iclass 5, count 0 2006.285.21:28:26.42#ibcon#flushed, iclass 5, count 0 2006.285.21:28:26.42#ibcon#about to write, iclass 5, count 0 2006.285.21:28:26.42#ibcon#wrote, iclass 5, count 0 2006.285.21:28:26.42#ibcon#about to read 3, iclass 5, count 0 2006.285.21:28:26.45#ibcon#read 3, iclass 5, count 0 2006.285.21:28:26.45#ibcon#about to read 4, iclass 5, count 0 2006.285.21:28:26.45#ibcon#read 4, iclass 5, count 0 2006.285.21:28:26.45#ibcon#about to read 5, iclass 5, count 0 2006.285.21:28:26.45#ibcon#read 5, iclass 5, count 0 2006.285.21:28:26.45#ibcon#about to read 6, iclass 5, count 0 2006.285.21:28:26.45#ibcon#read 6, iclass 5, count 0 2006.285.21:28:26.45#ibcon#end of sib2, iclass 5, count 0 2006.285.21:28:26.45#ibcon#*after write, iclass 5, count 0 2006.285.21:28:26.45#ibcon#*before return 0, iclass 5, count 0 2006.285.21:28:26.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:28:26.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:28:26.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.21:28:26.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.21:28:26.45$vck44/vblo=5,709.99 2006.285.21:28:26.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.21:28:26.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.21:28:26.45#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:26.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:28:26.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:28:26.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:28:26.45#ibcon#enter wrdev, iclass 7, count 0 2006.285.21:28:26.45#ibcon#first serial, iclass 7, count 0 2006.285.21:28:26.45#ibcon#enter sib2, iclass 7, count 0 2006.285.21:28:26.45#ibcon#flushed, iclass 7, count 0 2006.285.21:28:26.45#ibcon#about to write, iclass 7, count 0 2006.285.21:28:26.45#ibcon#wrote, iclass 7, count 0 2006.285.21:28:26.45#ibcon#about to read 3, iclass 7, count 0 2006.285.21:28:26.47#ibcon#read 3, iclass 7, count 0 2006.285.21:28:26.47#ibcon#about to read 4, iclass 7, count 0 2006.285.21:28:26.47#ibcon#read 4, iclass 7, count 0 2006.285.21:28:26.47#ibcon#about to read 5, iclass 7, count 0 2006.285.21:28:26.47#ibcon#read 5, iclass 7, count 0 2006.285.21:28:26.47#ibcon#about to read 6, iclass 7, count 0 2006.285.21:28:26.47#ibcon#read 6, iclass 7, count 0 2006.285.21:28:26.47#ibcon#end of sib2, iclass 7, count 0 2006.285.21:28:26.47#ibcon#*mode == 0, iclass 7, count 0 2006.285.21:28:26.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.21:28:26.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:28:26.47#ibcon#*before write, iclass 7, count 0 2006.285.21:28:26.47#ibcon#enter sib2, iclass 7, count 0 2006.285.21:28:26.47#ibcon#flushed, iclass 7, count 0 2006.285.21:28:26.47#ibcon#about to write, iclass 7, count 0 2006.285.21:28:26.47#ibcon#wrote, iclass 7, count 0 2006.285.21:28:26.47#ibcon#about to read 3, iclass 7, count 0 2006.285.21:28:26.51#ibcon#read 3, iclass 7, count 0 2006.285.21:28:26.51#ibcon#about to read 4, iclass 7, count 0 2006.285.21:28:26.51#ibcon#read 4, iclass 7, count 0 2006.285.21:28:26.51#ibcon#about to read 5, iclass 7, count 0 2006.285.21:28:26.51#ibcon#read 5, iclass 7, count 0 2006.285.21:28:26.51#ibcon#about to read 6, iclass 7, count 0 2006.285.21:28:26.51#ibcon#read 6, iclass 7, count 0 2006.285.21:28:26.51#ibcon#end of sib2, iclass 7, count 0 2006.285.21:28:26.51#ibcon#*after write, iclass 7, count 0 2006.285.21:28:26.51#ibcon#*before return 0, iclass 7, count 0 2006.285.21:28:26.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:28:26.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:28:26.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.21:28:26.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.21:28:26.51$vck44/vb=5,4 2006.285.21:28:26.51#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.21:28:26.51#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.21:28:26.51#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:26.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:28:26.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:28:26.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:28:26.57#ibcon#enter wrdev, iclass 11, count 2 2006.285.21:28:26.57#ibcon#first serial, iclass 11, count 2 2006.285.21:28:26.57#ibcon#enter sib2, iclass 11, count 2 2006.285.21:28:26.57#ibcon#flushed, iclass 11, count 2 2006.285.21:28:26.57#ibcon#about to write, iclass 11, count 2 2006.285.21:28:26.57#ibcon#wrote, iclass 11, count 2 2006.285.21:28:26.57#ibcon#about to read 3, iclass 11, count 2 2006.285.21:28:26.59#ibcon#read 3, iclass 11, count 2 2006.285.21:28:26.59#ibcon#about to read 4, iclass 11, count 2 2006.285.21:28:26.59#ibcon#read 4, iclass 11, count 2 2006.285.21:28:26.59#ibcon#about to read 5, iclass 11, count 2 2006.285.21:28:26.59#ibcon#read 5, iclass 11, count 2 2006.285.21:28:26.59#ibcon#about to read 6, iclass 11, count 2 2006.285.21:28:26.59#ibcon#read 6, iclass 11, count 2 2006.285.21:28:26.59#ibcon#end of sib2, iclass 11, count 2 2006.285.21:28:26.59#ibcon#*mode == 0, iclass 11, count 2 2006.285.21:28:26.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.21:28:26.59#ibcon#[27=AT05-04\r\n] 2006.285.21:28:26.59#ibcon#*before write, iclass 11, count 2 2006.285.21:28:26.59#ibcon#enter sib2, iclass 11, count 2 2006.285.21:28:26.59#ibcon#flushed, iclass 11, count 2 2006.285.21:28:26.59#ibcon#about to write, iclass 11, count 2 2006.285.21:28:26.59#ibcon#wrote, iclass 11, count 2 2006.285.21:28:26.59#ibcon#about to read 3, iclass 11, count 2 2006.285.21:28:26.62#ibcon#read 3, iclass 11, count 2 2006.285.21:28:26.62#ibcon#about to read 4, iclass 11, count 2 2006.285.21:28:26.62#ibcon#read 4, iclass 11, count 2 2006.285.21:28:26.62#ibcon#about to read 5, iclass 11, count 2 2006.285.21:28:26.62#ibcon#read 5, iclass 11, count 2 2006.285.21:28:26.62#ibcon#about to read 6, iclass 11, count 2 2006.285.21:28:26.62#ibcon#read 6, iclass 11, count 2 2006.285.21:28:26.62#ibcon#end of sib2, iclass 11, count 2 2006.285.21:28:26.62#ibcon#*after write, iclass 11, count 2 2006.285.21:28:26.62#ibcon#*before return 0, iclass 11, count 2 2006.285.21:28:26.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:28:26.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:28:26.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.21:28:26.62#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:26.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:28:26.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:28:26.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:28:26.74#ibcon#enter wrdev, iclass 11, count 0 2006.285.21:28:26.74#ibcon#first serial, iclass 11, count 0 2006.285.21:28:26.74#ibcon#enter sib2, iclass 11, count 0 2006.285.21:28:26.74#ibcon#flushed, iclass 11, count 0 2006.285.21:28:26.74#ibcon#about to write, iclass 11, count 0 2006.285.21:28:26.74#ibcon#wrote, iclass 11, count 0 2006.285.21:28:26.74#ibcon#about to read 3, iclass 11, count 0 2006.285.21:28:26.76#ibcon#read 3, iclass 11, count 0 2006.285.21:28:26.76#ibcon#about to read 4, iclass 11, count 0 2006.285.21:28:26.76#ibcon#read 4, iclass 11, count 0 2006.285.21:28:26.76#ibcon#about to read 5, iclass 11, count 0 2006.285.21:28:26.76#ibcon#read 5, iclass 11, count 0 2006.285.21:28:26.76#ibcon#about to read 6, iclass 11, count 0 2006.285.21:28:26.76#ibcon#read 6, iclass 11, count 0 2006.285.21:28:26.76#ibcon#end of sib2, iclass 11, count 0 2006.285.21:28:26.76#ibcon#*mode == 0, iclass 11, count 0 2006.285.21:28:26.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.21:28:26.76#ibcon#[27=USB\r\n] 2006.285.21:28:26.76#ibcon#*before write, iclass 11, count 0 2006.285.21:28:26.76#ibcon#enter sib2, iclass 11, count 0 2006.285.21:28:26.76#ibcon#flushed, iclass 11, count 0 2006.285.21:28:26.76#ibcon#about to write, iclass 11, count 0 2006.285.21:28:26.76#ibcon#wrote, iclass 11, count 0 2006.285.21:28:26.76#ibcon#about to read 3, iclass 11, count 0 2006.285.21:28:26.79#ibcon#read 3, iclass 11, count 0 2006.285.21:28:26.79#ibcon#about to read 4, iclass 11, count 0 2006.285.21:28:26.79#ibcon#read 4, iclass 11, count 0 2006.285.21:28:26.79#ibcon#about to read 5, iclass 11, count 0 2006.285.21:28:26.79#ibcon#read 5, iclass 11, count 0 2006.285.21:28:26.79#ibcon#about to read 6, iclass 11, count 0 2006.285.21:28:26.79#ibcon#read 6, iclass 11, count 0 2006.285.21:28:26.79#ibcon#end of sib2, iclass 11, count 0 2006.285.21:28:26.79#ibcon#*after write, iclass 11, count 0 2006.285.21:28:26.79#ibcon#*before return 0, iclass 11, count 0 2006.285.21:28:26.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:28:26.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:28:26.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.21:28:26.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.21:28:26.79$vck44/vblo=6,719.99 2006.285.21:28:26.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.21:28:26.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.21:28:26.79#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:26.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:28:26.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:28:26.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:28:26.79#ibcon#enter wrdev, iclass 13, count 0 2006.285.21:28:26.79#ibcon#first serial, iclass 13, count 0 2006.285.21:28:26.79#ibcon#enter sib2, iclass 13, count 0 2006.285.21:28:26.79#ibcon#flushed, iclass 13, count 0 2006.285.21:28:26.79#ibcon#about to write, iclass 13, count 0 2006.285.21:28:26.79#ibcon#wrote, iclass 13, count 0 2006.285.21:28:26.79#ibcon#about to read 3, iclass 13, count 0 2006.285.21:28:26.81#ibcon#read 3, iclass 13, count 0 2006.285.21:28:26.85#ibcon#about to read 4, iclass 13, count 0 2006.285.21:28:26.85#ibcon#read 4, iclass 13, count 0 2006.285.21:28:26.85#ibcon#about to read 5, iclass 13, count 0 2006.285.21:28:26.85#ibcon#read 5, iclass 13, count 0 2006.285.21:28:26.85#ibcon#about to read 6, iclass 13, count 0 2006.285.21:28:26.85#ibcon#read 6, iclass 13, count 0 2006.285.21:28:26.85#ibcon#end of sib2, iclass 13, count 0 2006.285.21:28:26.85#ibcon#*mode == 0, iclass 13, count 0 2006.285.21:28:26.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.21:28:26.85#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:28:26.85#ibcon#*before write, iclass 13, count 0 2006.285.21:28:26.85#ibcon#enter sib2, iclass 13, count 0 2006.285.21:28:26.85#ibcon#flushed, iclass 13, count 0 2006.285.21:28:26.85#ibcon#about to write, iclass 13, count 0 2006.285.21:28:26.85#ibcon#wrote, iclass 13, count 0 2006.285.21:28:26.85#ibcon#about to read 3, iclass 13, count 0 2006.285.21:28:26.89#ibcon#read 3, iclass 13, count 0 2006.285.21:28:26.89#ibcon#about to read 4, iclass 13, count 0 2006.285.21:28:26.89#ibcon#read 4, iclass 13, count 0 2006.285.21:28:26.89#ibcon#about to read 5, iclass 13, count 0 2006.285.21:28:26.89#ibcon#read 5, iclass 13, count 0 2006.285.21:28:26.89#ibcon#about to read 6, iclass 13, count 0 2006.285.21:28:26.89#ibcon#read 6, iclass 13, count 0 2006.285.21:28:26.89#ibcon#end of sib2, iclass 13, count 0 2006.285.21:28:26.89#ibcon#*after write, iclass 13, count 0 2006.285.21:28:26.89#ibcon#*before return 0, iclass 13, count 0 2006.285.21:28:26.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:28:26.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:28:26.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.21:28:26.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.21:28:26.89$vck44/vb=6,3 2006.285.21:28:26.89#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.21:28:26.89#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.21:28:26.89#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:26.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:28:26.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:28:26.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:28:26.91#ibcon#enter wrdev, iclass 15, count 2 2006.285.21:28:26.91#ibcon#first serial, iclass 15, count 2 2006.285.21:28:26.91#ibcon#enter sib2, iclass 15, count 2 2006.285.21:28:26.91#ibcon#flushed, iclass 15, count 2 2006.285.21:28:26.91#ibcon#about to write, iclass 15, count 2 2006.285.21:28:26.91#ibcon#wrote, iclass 15, count 2 2006.285.21:28:26.91#ibcon#about to read 3, iclass 15, count 2 2006.285.21:28:26.93#ibcon#read 3, iclass 15, count 2 2006.285.21:28:26.93#ibcon#about to read 4, iclass 15, count 2 2006.285.21:28:26.93#ibcon#read 4, iclass 15, count 2 2006.285.21:28:26.93#ibcon#about to read 5, iclass 15, count 2 2006.285.21:28:26.93#ibcon#read 5, iclass 15, count 2 2006.285.21:28:26.93#ibcon#about to read 6, iclass 15, count 2 2006.285.21:28:26.93#ibcon#read 6, iclass 15, count 2 2006.285.21:28:26.93#ibcon#end of sib2, iclass 15, count 2 2006.285.21:28:26.93#ibcon#*mode == 0, iclass 15, count 2 2006.285.21:28:26.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.21:28:26.93#ibcon#[27=AT06-03\r\n] 2006.285.21:28:26.93#ibcon#*before write, iclass 15, count 2 2006.285.21:28:26.93#ibcon#enter sib2, iclass 15, count 2 2006.285.21:28:26.93#ibcon#flushed, iclass 15, count 2 2006.285.21:28:26.93#ibcon#about to write, iclass 15, count 2 2006.285.21:28:26.93#ibcon#wrote, iclass 15, count 2 2006.285.21:28:26.93#ibcon#about to read 3, iclass 15, count 2 2006.285.21:28:26.96#ibcon#read 3, iclass 15, count 2 2006.285.21:28:26.96#ibcon#about to read 4, iclass 15, count 2 2006.285.21:28:26.96#ibcon#read 4, iclass 15, count 2 2006.285.21:28:26.96#ibcon#about to read 5, iclass 15, count 2 2006.285.21:28:26.96#ibcon#read 5, iclass 15, count 2 2006.285.21:28:26.96#ibcon#about to read 6, iclass 15, count 2 2006.285.21:28:26.96#ibcon#read 6, iclass 15, count 2 2006.285.21:28:26.96#ibcon#end of sib2, iclass 15, count 2 2006.285.21:28:26.96#ibcon#*after write, iclass 15, count 2 2006.285.21:28:26.96#ibcon#*before return 0, iclass 15, count 2 2006.285.21:28:26.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:28:26.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:28:26.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.21:28:26.96#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:26.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:28:27.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:28:27.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:28:27.08#ibcon#enter wrdev, iclass 15, count 0 2006.285.21:28:27.08#ibcon#first serial, iclass 15, count 0 2006.285.21:28:27.08#ibcon#enter sib2, iclass 15, count 0 2006.285.21:28:27.08#ibcon#flushed, iclass 15, count 0 2006.285.21:28:27.08#ibcon#about to write, iclass 15, count 0 2006.285.21:28:27.08#ibcon#wrote, iclass 15, count 0 2006.285.21:28:27.08#ibcon#about to read 3, iclass 15, count 0 2006.285.21:28:27.10#ibcon#read 3, iclass 15, count 0 2006.285.21:28:27.10#ibcon#about to read 4, iclass 15, count 0 2006.285.21:28:27.10#ibcon#read 4, iclass 15, count 0 2006.285.21:28:27.10#ibcon#about to read 5, iclass 15, count 0 2006.285.21:28:27.10#ibcon#read 5, iclass 15, count 0 2006.285.21:28:27.10#ibcon#about to read 6, iclass 15, count 0 2006.285.21:28:27.10#ibcon#read 6, iclass 15, count 0 2006.285.21:28:27.10#ibcon#end of sib2, iclass 15, count 0 2006.285.21:28:27.10#ibcon#*mode == 0, iclass 15, count 0 2006.285.21:28:27.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.21:28:27.10#ibcon#[27=USB\r\n] 2006.285.21:28:27.10#ibcon#*before write, iclass 15, count 0 2006.285.21:28:27.10#ibcon#enter sib2, iclass 15, count 0 2006.285.21:28:27.10#ibcon#flushed, iclass 15, count 0 2006.285.21:28:27.10#ibcon#about to write, iclass 15, count 0 2006.285.21:28:27.10#ibcon#wrote, iclass 15, count 0 2006.285.21:28:27.10#ibcon#about to read 3, iclass 15, count 0 2006.285.21:28:27.13#ibcon#read 3, iclass 15, count 0 2006.285.21:28:27.13#ibcon#about to read 4, iclass 15, count 0 2006.285.21:28:27.13#ibcon#read 4, iclass 15, count 0 2006.285.21:28:27.13#ibcon#about to read 5, iclass 15, count 0 2006.285.21:28:27.13#ibcon#read 5, iclass 15, count 0 2006.285.21:28:27.13#ibcon#about to read 6, iclass 15, count 0 2006.285.21:28:27.13#ibcon#read 6, iclass 15, count 0 2006.285.21:28:27.13#ibcon#end of sib2, iclass 15, count 0 2006.285.21:28:27.13#ibcon#*after write, iclass 15, count 0 2006.285.21:28:27.13#ibcon#*before return 0, iclass 15, count 0 2006.285.21:28:27.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:28:27.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:28:27.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.21:28:27.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.21:28:27.13$vck44/vblo=7,734.99 2006.285.21:28:27.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.21:28:27.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.21:28:27.13#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:27.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:28:27.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:28:27.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:28:27.13#ibcon#enter wrdev, iclass 17, count 0 2006.285.21:28:27.13#ibcon#first serial, iclass 17, count 0 2006.285.21:28:27.13#ibcon#enter sib2, iclass 17, count 0 2006.285.21:28:27.13#ibcon#flushed, iclass 17, count 0 2006.285.21:28:27.13#ibcon#about to write, iclass 17, count 0 2006.285.21:28:27.13#ibcon#wrote, iclass 17, count 0 2006.285.21:28:27.13#ibcon#about to read 3, iclass 17, count 0 2006.285.21:28:27.15#ibcon#read 3, iclass 17, count 0 2006.285.21:28:27.15#ibcon#about to read 4, iclass 17, count 0 2006.285.21:28:27.15#ibcon#read 4, iclass 17, count 0 2006.285.21:28:27.15#ibcon#about to read 5, iclass 17, count 0 2006.285.21:28:27.15#ibcon#read 5, iclass 17, count 0 2006.285.21:28:27.15#ibcon#about to read 6, iclass 17, count 0 2006.285.21:28:27.15#ibcon#read 6, iclass 17, count 0 2006.285.21:28:27.15#ibcon#end of sib2, iclass 17, count 0 2006.285.21:28:27.15#ibcon#*mode == 0, iclass 17, count 0 2006.285.21:28:27.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.21:28:27.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:28:27.15#ibcon#*before write, iclass 17, count 0 2006.285.21:28:27.15#ibcon#enter sib2, iclass 17, count 0 2006.285.21:28:27.15#ibcon#flushed, iclass 17, count 0 2006.285.21:28:27.15#ibcon#about to write, iclass 17, count 0 2006.285.21:28:27.15#ibcon#wrote, iclass 17, count 0 2006.285.21:28:27.15#ibcon#about to read 3, iclass 17, count 0 2006.285.21:28:27.19#ibcon#read 3, iclass 17, count 0 2006.285.21:28:27.19#ibcon#about to read 4, iclass 17, count 0 2006.285.21:28:27.19#ibcon#read 4, iclass 17, count 0 2006.285.21:28:27.19#ibcon#about to read 5, iclass 17, count 0 2006.285.21:28:27.19#ibcon#read 5, iclass 17, count 0 2006.285.21:28:27.19#ibcon#about to read 6, iclass 17, count 0 2006.285.21:28:27.19#ibcon#read 6, iclass 17, count 0 2006.285.21:28:27.19#ibcon#end of sib2, iclass 17, count 0 2006.285.21:28:27.19#ibcon#*after write, iclass 17, count 0 2006.285.21:28:27.19#ibcon#*before return 0, iclass 17, count 0 2006.285.21:28:27.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:28:27.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:28:27.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.21:28:27.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.21:28:27.19$vck44/vb=7,4 2006.285.21:28:27.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.21:28:27.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.21:28:27.19#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:27.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:28:27.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:28:27.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:28:27.25#ibcon#enter wrdev, iclass 19, count 2 2006.285.21:28:27.25#ibcon#first serial, iclass 19, count 2 2006.285.21:28:27.25#ibcon#enter sib2, iclass 19, count 2 2006.285.21:28:27.25#ibcon#flushed, iclass 19, count 2 2006.285.21:28:27.25#ibcon#about to write, iclass 19, count 2 2006.285.21:28:27.25#ibcon#wrote, iclass 19, count 2 2006.285.21:28:27.25#ibcon#about to read 3, iclass 19, count 2 2006.285.21:28:27.27#ibcon#read 3, iclass 19, count 2 2006.285.21:28:27.27#ibcon#about to read 4, iclass 19, count 2 2006.285.21:28:27.27#ibcon#read 4, iclass 19, count 2 2006.285.21:28:27.27#ibcon#about to read 5, iclass 19, count 2 2006.285.21:28:27.27#ibcon#read 5, iclass 19, count 2 2006.285.21:28:27.27#ibcon#about to read 6, iclass 19, count 2 2006.285.21:28:27.27#ibcon#read 6, iclass 19, count 2 2006.285.21:28:27.27#ibcon#end of sib2, iclass 19, count 2 2006.285.21:28:27.27#ibcon#*mode == 0, iclass 19, count 2 2006.285.21:28:27.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.21:28:27.27#ibcon#[27=AT07-04\r\n] 2006.285.21:28:27.27#ibcon#*before write, iclass 19, count 2 2006.285.21:28:27.27#ibcon#enter sib2, iclass 19, count 2 2006.285.21:28:27.27#ibcon#flushed, iclass 19, count 2 2006.285.21:28:27.27#ibcon#about to write, iclass 19, count 2 2006.285.21:28:27.27#ibcon#wrote, iclass 19, count 2 2006.285.21:28:27.27#ibcon#about to read 3, iclass 19, count 2 2006.285.21:28:27.30#ibcon#read 3, iclass 19, count 2 2006.285.21:28:27.30#ibcon#about to read 4, iclass 19, count 2 2006.285.21:28:27.30#ibcon#read 4, iclass 19, count 2 2006.285.21:28:27.30#ibcon#about to read 5, iclass 19, count 2 2006.285.21:28:27.30#ibcon#read 5, iclass 19, count 2 2006.285.21:28:27.30#ibcon#about to read 6, iclass 19, count 2 2006.285.21:28:27.30#ibcon#read 6, iclass 19, count 2 2006.285.21:28:27.30#ibcon#end of sib2, iclass 19, count 2 2006.285.21:28:27.30#ibcon#*after write, iclass 19, count 2 2006.285.21:28:27.30#ibcon#*before return 0, iclass 19, count 2 2006.285.21:28:27.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:28:27.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:28:27.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.21:28:27.30#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:27.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:28:27.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:28:27.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:28:27.42#ibcon#enter wrdev, iclass 19, count 0 2006.285.21:28:27.42#ibcon#first serial, iclass 19, count 0 2006.285.21:28:27.42#ibcon#enter sib2, iclass 19, count 0 2006.285.21:28:27.42#ibcon#flushed, iclass 19, count 0 2006.285.21:28:27.42#ibcon#about to write, iclass 19, count 0 2006.285.21:28:27.42#ibcon#wrote, iclass 19, count 0 2006.285.21:28:27.42#ibcon#about to read 3, iclass 19, count 0 2006.285.21:28:27.44#ibcon#read 3, iclass 19, count 0 2006.285.21:28:27.44#ibcon#about to read 4, iclass 19, count 0 2006.285.21:28:27.44#ibcon#read 4, iclass 19, count 0 2006.285.21:28:27.44#ibcon#about to read 5, iclass 19, count 0 2006.285.21:28:27.44#ibcon#read 5, iclass 19, count 0 2006.285.21:28:27.44#ibcon#about to read 6, iclass 19, count 0 2006.285.21:28:27.44#ibcon#read 6, iclass 19, count 0 2006.285.21:28:27.44#ibcon#end of sib2, iclass 19, count 0 2006.285.21:28:27.44#ibcon#*mode == 0, iclass 19, count 0 2006.285.21:28:27.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.21:28:27.44#ibcon#[27=USB\r\n] 2006.285.21:28:27.44#ibcon#*before write, iclass 19, count 0 2006.285.21:28:27.44#ibcon#enter sib2, iclass 19, count 0 2006.285.21:28:27.44#ibcon#flushed, iclass 19, count 0 2006.285.21:28:27.44#ibcon#about to write, iclass 19, count 0 2006.285.21:28:27.44#ibcon#wrote, iclass 19, count 0 2006.285.21:28:27.44#ibcon#about to read 3, iclass 19, count 0 2006.285.21:28:27.47#ibcon#read 3, iclass 19, count 0 2006.285.21:28:27.47#ibcon#about to read 4, iclass 19, count 0 2006.285.21:28:27.47#ibcon#read 4, iclass 19, count 0 2006.285.21:28:27.47#ibcon#about to read 5, iclass 19, count 0 2006.285.21:28:27.47#ibcon#read 5, iclass 19, count 0 2006.285.21:28:27.47#ibcon#about to read 6, iclass 19, count 0 2006.285.21:28:27.47#ibcon#read 6, iclass 19, count 0 2006.285.21:28:27.47#ibcon#end of sib2, iclass 19, count 0 2006.285.21:28:27.47#ibcon#*after write, iclass 19, count 0 2006.285.21:28:27.47#ibcon#*before return 0, iclass 19, count 0 2006.285.21:28:27.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:28:27.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:28:27.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.21:28:27.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.21:28:27.47$vck44/vblo=8,744.99 2006.285.21:28:27.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.21:28:27.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.21:28:27.47#ibcon#ireg 17 cls_cnt 0 2006.285.21:28:27.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:28:27.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:28:27.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:28:27.47#ibcon#enter wrdev, iclass 21, count 0 2006.285.21:28:27.47#ibcon#first serial, iclass 21, count 0 2006.285.21:28:27.47#ibcon#enter sib2, iclass 21, count 0 2006.285.21:28:27.47#ibcon#flushed, iclass 21, count 0 2006.285.21:28:27.47#ibcon#about to write, iclass 21, count 0 2006.285.21:28:27.47#ibcon#wrote, iclass 21, count 0 2006.285.21:28:27.47#ibcon#about to read 3, iclass 21, count 0 2006.285.21:28:27.49#ibcon#read 3, iclass 21, count 0 2006.285.21:28:27.49#ibcon#about to read 4, iclass 21, count 0 2006.285.21:28:27.49#ibcon#read 4, iclass 21, count 0 2006.285.21:28:27.49#ibcon#about to read 5, iclass 21, count 0 2006.285.21:28:27.49#ibcon#read 5, iclass 21, count 0 2006.285.21:28:27.49#ibcon#about to read 6, iclass 21, count 0 2006.285.21:28:27.49#ibcon#read 6, iclass 21, count 0 2006.285.21:28:27.49#ibcon#end of sib2, iclass 21, count 0 2006.285.21:28:27.49#ibcon#*mode == 0, iclass 21, count 0 2006.285.21:28:27.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.21:28:27.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:28:27.49#ibcon#*before write, iclass 21, count 0 2006.285.21:28:27.49#ibcon#enter sib2, iclass 21, count 0 2006.285.21:28:27.49#ibcon#flushed, iclass 21, count 0 2006.285.21:28:27.49#ibcon#about to write, iclass 21, count 0 2006.285.21:28:27.49#ibcon#wrote, iclass 21, count 0 2006.285.21:28:27.49#ibcon#about to read 3, iclass 21, count 0 2006.285.21:28:27.53#ibcon#read 3, iclass 21, count 0 2006.285.21:28:27.53#ibcon#about to read 4, iclass 21, count 0 2006.285.21:28:27.53#ibcon#read 4, iclass 21, count 0 2006.285.21:28:27.53#ibcon#about to read 5, iclass 21, count 0 2006.285.21:28:27.53#ibcon#read 5, iclass 21, count 0 2006.285.21:28:27.53#ibcon#about to read 6, iclass 21, count 0 2006.285.21:28:27.53#ibcon#read 6, iclass 21, count 0 2006.285.21:28:27.53#ibcon#end of sib2, iclass 21, count 0 2006.285.21:28:27.53#ibcon#*after write, iclass 21, count 0 2006.285.21:28:27.53#ibcon#*before return 0, iclass 21, count 0 2006.285.21:28:27.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:28:27.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:28:27.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.21:28:27.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.21:28:27.53$vck44/vb=8,4 2006.285.21:28:27.53#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.21:28:27.53#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.21:28:27.53#ibcon#ireg 11 cls_cnt 2 2006.285.21:28:27.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:28:27.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:28:27.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:28:27.59#ibcon#enter wrdev, iclass 23, count 2 2006.285.21:28:27.59#ibcon#first serial, iclass 23, count 2 2006.285.21:28:27.59#ibcon#enter sib2, iclass 23, count 2 2006.285.21:28:27.59#ibcon#flushed, iclass 23, count 2 2006.285.21:28:27.59#ibcon#about to write, iclass 23, count 2 2006.285.21:28:27.59#ibcon#wrote, iclass 23, count 2 2006.285.21:28:27.59#ibcon#about to read 3, iclass 23, count 2 2006.285.21:28:27.61#ibcon#read 3, iclass 23, count 2 2006.285.21:28:27.61#ibcon#about to read 4, iclass 23, count 2 2006.285.21:28:27.61#ibcon#read 4, iclass 23, count 2 2006.285.21:28:27.61#ibcon#about to read 5, iclass 23, count 2 2006.285.21:28:27.61#ibcon#read 5, iclass 23, count 2 2006.285.21:28:27.61#ibcon#about to read 6, iclass 23, count 2 2006.285.21:28:27.61#ibcon#read 6, iclass 23, count 2 2006.285.21:28:27.61#ibcon#end of sib2, iclass 23, count 2 2006.285.21:28:27.61#ibcon#*mode == 0, iclass 23, count 2 2006.285.21:28:27.61#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.21:28:27.61#ibcon#[27=AT08-04\r\n] 2006.285.21:28:27.61#ibcon#*before write, iclass 23, count 2 2006.285.21:28:27.61#ibcon#enter sib2, iclass 23, count 2 2006.285.21:28:27.61#ibcon#flushed, iclass 23, count 2 2006.285.21:28:27.61#ibcon#about to write, iclass 23, count 2 2006.285.21:28:27.61#ibcon#wrote, iclass 23, count 2 2006.285.21:28:27.61#ibcon#about to read 3, iclass 23, count 2 2006.285.21:28:27.64#ibcon#read 3, iclass 23, count 2 2006.285.21:28:27.64#ibcon#about to read 4, iclass 23, count 2 2006.285.21:28:27.64#ibcon#read 4, iclass 23, count 2 2006.285.21:28:27.64#ibcon#about to read 5, iclass 23, count 2 2006.285.21:28:27.64#ibcon#read 5, iclass 23, count 2 2006.285.21:28:27.64#ibcon#about to read 6, iclass 23, count 2 2006.285.21:28:27.64#ibcon#read 6, iclass 23, count 2 2006.285.21:28:27.64#ibcon#end of sib2, iclass 23, count 2 2006.285.21:28:27.64#ibcon#*after write, iclass 23, count 2 2006.285.21:28:27.64#ibcon#*before return 0, iclass 23, count 2 2006.285.21:28:27.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:28:27.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:28:27.64#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.21:28:27.64#ibcon#ireg 7 cls_cnt 0 2006.285.21:28:27.64#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:28:27.76#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:28:27.76#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:28:27.76#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:28:27.76#ibcon#first serial, iclass 23, count 0 2006.285.21:28:27.76#ibcon#enter sib2, iclass 23, count 0 2006.285.21:28:27.76#ibcon#flushed, iclass 23, count 0 2006.285.21:28:27.76#ibcon#about to write, iclass 23, count 0 2006.285.21:28:27.76#ibcon#wrote, iclass 23, count 0 2006.285.21:28:27.76#ibcon#about to read 3, iclass 23, count 0 2006.285.21:28:27.78#ibcon#read 3, iclass 23, count 0 2006.285.21:28:27.78#ibcon#about to read 4, iclass 23, count 0 2006.285.21:28:27.78#ibcon#read 4, iclass 23, count 0 2006.285.21:28:27.78#ibcon#about to read 5, iclass 23, count 0 2006.285.21:28:27.78#ibcon#read 5, iclass 23, count 0 2006.285.21:28:27.78#ibcon#about to read 6, iclass 23, count 0 2006.285.21:28:27.78#ibcon#read 6, iclass 23, count 0 2006.285.21:28:27.78#ibcon#end of sib2, iclass 23, count 0 2006.285.21:28:27.78#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:28:27.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:28:27.78#ibcon#[27=USB\r\n] 2006.285.21:28:27.78#ibcon#*before write, iclass 23, count 0 2006.285.21:28:27.78#ibcon#enter sib2, iclass 23, count 0 2006.285.21:28:27.78#ibcon#flushed, iclass 23, count 0 2006.285.21:28:27.78#ibcon#about to write, iclass 23, count 0 2006.285.21:28:27.78#ibcon#wrote, iclass 23, count 0 2006.285.21:28:27.78#ibcon#about to read 3, iclass 23, count 0 2006.285.21:28:27.81#ibcon#read 3, iclass 23, count 0 2006.285.21:28:27.81#ibcon#about to read 4, iclass 23, count 0 2006.285.21:28:27.81#ibcon#read 4, iclass 23, count 0 2006.285.21:28:27.81#ibcon#about to read 5, iclass 23, count 0 2006.285.21:28:27.81#ibcon#read 5, iclass 23, count 0 2006.285.21:28:27.81#ibcon#about to read 6, iclass 23, count 0 2006.285.21:28:27.81#ibcon#read 6, iclass 23, count 0 2006.285.21:28:27.81#ibcon#end of sib2, iclass 23, count 0 2006.285.21:28:27.81#ibcon#*after write, iclass 23, count 0 2006.285.21:28:27.81#ibcon#*before return 0, iclass 23, count 0 2006.285.21:28:27.81#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:28:27.81#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:28:27.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:28:27.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:28:27.81$vck44/vabw=wide 2006.285.21:28:27.81#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.21:28:27.81#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.21:28:27.81#ibcon#ireg 8 cls_cnt 0 2006.285.21:28:27.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:28:27.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:28:27.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:28:27.81#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:28:27.81#ibcon#first serial, iclass 25, count 0 2006.285.21:28:27.81#ibcon#enter sib2, iclass 25, count 0 2006.285.21:28:27.81#ibcon#flushed, iclass 25, count 0 2006.285.21:28:27.81#ibcon#about to write, iclass 25, count 0 2006.285.21:28:27.81#ibcon#wrote, iclass 25, count 0 2006.285.21:28:27.81#ibcon#about to read 3, iclass 25, count 0 2006.285.21:28:27.83#ibcon#read 3, iclass 25, count 0 2006.285.21:28:27.86#ibcon#about to read 4, iclass 25, count 0 2006.285.21:28:27.86#ibcon#read 4, iclass 25, count 0 2006.285.21:28:27.86#ibcon#about to read 5, iclass 25, count 0 2006.285.21:28:27.86#ibcon#read 5, iclass 25, count 0 2006.285.21:28:27.86#ibcon#about to read 6, iclass 25, count 0 2006.285.21:28:27.86#ibcon#read 6, iclass 25, count 0 2006.285.21:28:27.86#ibcon#end of sib2, iclass 25, count 0 2006.285.21:28:27.86#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:28:27.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:28:27.86#ibcon#[25=BW32\r\n] 2006.285.21:28:27.86#ibcon#*before write, iclass 25, count 0 2006.285.21:28:27.86#ibcon#enter sib2, iclass 25, count 0 2006.285.21:28:27.86#ibcon#flushed, iclass 25, count 0 2006.285.21:28:27.86#ibcon#about to write, iclass 25, count 0 2006.285.21:28:27.86#ibcon#wrote, iclass 25, count 0 2006.285.21:28:27.86#ibcon#about to read 3, iclass 25, count 0 2006.285.21:28:27.89#ibcon#read 3, iclass 25, count 0 2006.285.21:28:27.89#ibcon#about to read 4, iclass 25, count 0 2006.285.21:28:27.89#ibcon#read 4, iclass 25, count 0 2006.285.21:28:27.89#ibcon#about to read 5, iclass 25, count 0 2006.285.21:28:27.89#ibcon#read 5, iclass 25, count 0 2006.285.21:28:27.89#ibcon#about to read 6, iclass 25, count 0 2006.285.21:28:27.89#ibcon#read 6, iclass 25, count 0 2006.285.21:28:27.89#ibcon#end of sib2, iclass 25, count 0 2006.285.21:28:27.89#ibcon#*after write, iclass 25, count 0 2006.285.21:28:27.89#ibcon#*before return 0, iclass 25, count 0 2006.285.21:28:27.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:28:27.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:28:27.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:28:27.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:28:27.89$vck44/vbbw=wide 2006.285.21:28:27.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.21:28:27.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.21:28:27.89#ibcon#ireg 8 cls_cnt 0 2006.285.21:28:27.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:28:27.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:28:27.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:28:27.93#ibcon#enter wrdev, iclass 27, count 0 2006.285.21:28:27.93#ibcon#first serial, iclass 27, count 0 2006.285.21:28:27.93#ibcon#enter sib2, iclass 27, count 0 2006.285.21:28:27.93#ibcon#flushed, iclass 27, count 0 2006.285.21:28:27.93#ibcon#about to write, iclass 27, count 0 2006.285.21:28:27.93#ibcon#wrote, iclass 27, count 0 2006.285.21:28:27.93#ibcon#about to read 3, iclass 27, count 0 2006.285.21:28:27.95#ibcon#read 3, iclass 27, count 0 2006.285.21:28:27.95#ibcon#about to read 4, iclass 27, count 0 2006.285.21:28:27.95#ibcon#read 4, iclass 27, count 0 2006.285.21:28:27.95#ibcon#about to read 5, iclass 27, count 0 2006.285.21:28:27.95#ibcon#read 5, iclass 27, count 0 2006.285.21:28:27.95#ibcon#about to read 6, iclass 27, count 0 2006.285.21:28:27.95#ibcon#read 6, iclass 27, count 0 2006.285.21:28:27.95#ibcon#end of sib2, iclass 27, count 0 2006.285.21:28:27.95#ibcon#*mode == 0, iclass 27, count 0 2006.285.21:28:27.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.21:28:27.95#ibcon#[27=BW32\r\n] 2006.285.21:28:27.95#ibcon#*before write, iclass 27, count 0 2006.285.21:28:27.95#ibcon#enter sib2, iclass 27, count 0 2006.285.21:28:27.95#ibcon#flushed, iclass 27, count 0 2006.285.21:28:27.95#ibcon#about to write, iclass 27, count 0 2006.285.21:28:27.95#ibcon#wrote, iclass 27, count 0 2006.285.21:28:27.95#ibcon#about to read 3, iclass 27, count 0 2006.285.21:28:27.98#ibcon#read 3, iclass 27, count 0 2006.285.21:28:27.98#ibcon#about to read 4, iclass 27, count 0 2006.285.21:28:27.98#ibcon#read 4, iclass 27, count 0 2006.285.21:28:27.98#ibcon#about to read 5, iclass 27, count 0 2006.285.21:28:27.98#ibcon#read 5, iclass 27, count 0 2006.285.21:28:27.98#ibcon#about to read 6, iclass 27, count 0 2006.285.21:28:27.98#ibcon#read 6, iclass 27, count 0 2006.285.21:28:27.98#ibcon#end of sib2, iclass 27, count 0 2006.285.21:28:27.98#ibcon#*after write, iclass 27, count 0 2006.285.21:28:27.98#ibcon#*before return 0, iclass 27, count 0 2006.285.21:28:27.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:28:27.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:28:27.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.21:28:27.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.21:28:27.98$setupk4/ifdk4 2006.285.21:28:27.98$ifdk4/lo= 2006.285.21:28:27.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:28:27.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:28:27.98$ifdk4/patch= 2006.285.21:28:27.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:28:27.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:28:27.99$setupk4/!*+20s 2006.285.21:28:31.84#abcon#<5=/14 0.4 0.9 14.561001015.7\r\n> 2006.285.21:28:31.86#abcon#{5=INTERFACE CLEAR} 2006.285.21:28:31.92#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:28:41.14#trakl#Source acquired 2006.285.21:28:41.73$setupk4/"tpicd 2006.285.21:28:41.73$setupk4/echo=off 2006.285.21:28:41.73$setupk4/xlog=off 2006.285.21:28:41.73:!2006.285.21:29:56 2006.285.21:28:42.14#flagr#flagr/antenna,acquired 2006.285.21:29:56.00:preob 2006.285.21:29:56.14/onsource/TRACKING 2006.285.21:29:56.14:!2006.285.21:30:06 2006.285.21:30:06.00:"tape 2006.285.21:30:06.00:"st=record 2006.285.21:30:06.00:data_valid=on 2006.285.21:30:06.00:midob 2006.285.21:30:06.14/onsource/TRACKING 2006.285.21:30:06.14/wx/14.58,1015.8,100 2006.285.21:30:06.22/cable/+6.5111E-03 2006.285.21:30:07.31/va/01,07,usb,yes,33,36 2006.285.21:30:07.31/va/02,06,usb,yes,34,34 2006.285.21:30:07.31/va/03,07,usb,yes,33,35 2006.285.21:30:07.31/va/04,06,usb,yes,35,36 2006.285.21:30:07.31/va/05,03,usb,yes,34,34 2006.285.21:30:07.31/va/06,04,usb,yes,31,30 2006.285.21:30:07.31/va/07,04,usb,yes,31,32 2006.285.21:30:07.31/va/08,03,usb,yes,32,39 2006.285.21:30:07.54/valo/01,524.99,yes,locked 2006.285.21:30:07.54/valo/02,534.99,yes,locked 2006.285.21:30:07.54/valo/03,564.99,yes,locked 2006.285.21:30:07.54/valo/04,624.99,yes,locked 2006.285.21:30:07.54/valo/05,734.99,yes,locked 2006.285.21:30:07.54/valo/06,814.99,yes,locked 2006.285.21:30:07.54/valo/07,864.99,yes,locked 2006.285.21:30:07.54/valo/08,884.99,yes,locked 2006.285.21:30:08.63/vb/01,04,usb,yes,30,28 2006.285.21:30:08.63/vb/02,05,usb,yes,29,28 2006.285.21:30:08.63/vb/03,04,usb,yes,30,33 2006.285.21:30:08.63/vb/04,05,usb,yes,30,29 2006.285.21:30:08.63/vb/05,04,usb,yes,26,29 2006.285.21:30:08.63/vb/06,03,usb,yes,38,33 2006.285.21:30:08.63/vb/07,04,usb,yes,30,30 2006.285.21:30:08.63/vb/08,04,usb,yes,28,31 2006.285.21:30:08.86/vblo/01,629.99,yes,locked 2006.285.21:30:08.86/vblo/02,634.99,yes,locked 2006.285.21:30:08.86/vblo/03,649.99,yes,locked 2006.285.21:30:08.86/vblo/04,679.99,yes,locked 2006.285.21:30:08.86/vblo/05,709.99,yes,locked 2006.285.21:30:08.86/vblo/06,719.99,yes,locked 2006.285.21:30:08.86/vblo/07,734.99,yes,locked 2006.285.21:30:08.86/vblo/08,744.99,yes,locked 2006.285.21:30:09.01/vabw/8 2006.285.21:30:09.16/vbbw/8 2006.285.21:30:09.25/xfe/off,on,12.0 2006.285.21:30:09.62/ifatt/23,28,28,28 2006.285.21:30:10.07/fmout-gps/S +2.77E-07 2006.285.21:30:10.09:!2006.285.21:31:06 2006.285.21:31:06.00:data_valid=off 2006.285.21:31:06.00:"et 2006.285.21:31:06.00:!+3s 2006.285.21:31:09.01:"tape 2006.285.21:31:09.01:postob 2006.285.21:31:09.11/cable/+6.5108E-03 2006.285.21:31:09.11/wx/14.59,1015.8,100 2006.285.21:31:10.07/fmout-gps/S +2.76E-07 2006.285.21:31:10.07:scan_name=285-2133,jd0610,90 2006.285.21:31:10.07:source=3c274,123049.42,122328.0,2000.0,ccw 2006.285.21:31:10.14#flagr#flagr/antenna,new-source 2006.285.21:31:11.14:checkk5 2006.285.21:31:11.53/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:31:11.89/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:31:12.28/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:31:12.72/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:31:13.23/chk_obsdata//k5ts1/T2852130??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.21:31:13.69/chk_obsdata//k5ts2/T2852130??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.21:31:14.23/chk_obsdata//k5ts3/T2852130??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.21:31:14.74/chk_obsdata//k5ts4/T2852130??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.21:31:15.57/k5log//k5ts1_log_newline 2006.285.21:31:16.34/k5log//k5ts2_log_newline 2006.285.21:31:17.08/k5log//k5ts3_log_newline 2006.285.21:31:18.05/k5log//k5ts4_log_newline 2006.285.21:31:18.08/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:31:18.08:setupk4=1 2006.285.21:31:18.08$setupk4/echo=on 2006.285.21:31:18.08$setupk4/pcalon 2006.285.21:31:18.08$pcalon/"no phase cal control is implemented here 2006.285.21:31:18.08$setupk4/"tpicd=stop 2006.285.21:31:18.08$setupk4/"rec=synch_on 2006.285.21:31:18.08$setupk4/"rec_mode=128 2006.285.21:31:18.08$setupk4/!* 2006.285.21:31:18.08$setupk4/recpk4 2006.285.21:31:18.08$recpk4/recpatch= 2006.285.21:31:18.08$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:31:18.08$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:31:18.08$setupk4/vck44 2006.285.21:31:18.08$vck44/valo=1,524.99 2006.285.21:31:18.08#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.21:31:18.08#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.21:31:18.08#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:18.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:31:18.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:31:18.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:31:18.08#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:31:18.08#ibcon#first serial, iclass 28, count 0 2006.285.21:31:18.08#ibcon#enter sib2, iclass 28, count 0 2006.285.21:31:18.08#ibcon#flushed, iclass 28, count 0 2006.285.21:31:18.08#ibcon#about to write, iclass 28, count 0 2006.285.21:31:18.08#ibcon#wrote, iclass 28, count 0 2006.285.21:31:18.08#ibcon#about to read 3, iclass 28, count 0 2006.285.21:31:18.10#ibcon#read 3, iclass 28, count 0 2006.285.21:31:18.10#ibcon#about to read 4, iclass 28, count 0 2006.285.21:31:18.10#ibcon#read 4, iclass 28, count 0 2006.285.21:31:18.10#ibcon#about to read 5, iclass 28, count 0 2006.285.21:31:18.10#ibcon#read 5, iclass 28, count 0 2006.285.21:31:18.10#ibcon#about to read 6, iclass 28, count 0 2006.285.21:31:18.10#ibcon#read 6, iclass 28, count 0 2006.285.21:31:18.10#ibcon#end of sib2, iclass 28, count 0 2006.285.21:31:18.10#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:31:18.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:31:18.10#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:31:18.10#ibcon#*before write, iclass 28, count 0 2006.285.21:31:18.10#ibcon#enter sib2, iclass 28, count 0 2006.285.21:31:18.10#ibcon#flushed, iclass 28, count 0 2006.285.21:31:18.10#ibcon#about to write, iclass 28, count 0 2006.285.21:31:18.10#ibcon#wrote, iclass 28, count 0 2006.285.21:31:18.10#ibcon#about to read 3, iclass 28, count 0 2006.285.21:31:18.15#ibcon#read 3, iclass 28, count 0 2006.285.21:31:18.15#ibcon#about to read 4, iclass 28, count 0 2006.285.21:31:18.15#ibcon#read 4, iclass 28, count 0 2006.285.21:31:18.15#ibcon#about to read 5, iclass 28, count 0 2006.285.21:31:18.15#ibcon#read 5, iclass 28, count 0 2006.285.21:31:18.15#ibcon#about to read 6, iclass 28, count 0 2006.285.21:31:18.15#ibcon#read 6, iclass 28, count 0 2006.285.21:31:18.15#ibcon#end of sib2, iclass 28, count 0 2006.285.21:31:18.15#ibcon#*after write, iclass 28, count 0 2006.285.21:31:18.15#ibcon#*before return 0, iclass 28, count 0 2006.285.21:31:18.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:31:18.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:31:18.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:31:18.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:31:18.15$vck44/va=1,7 2006.285.21:31:18.15#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.21:31:18.15#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.21:31:18.15#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:18.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:31:18.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:31:18.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:31:18.15#ibcon#enter wrdev, iclass 30, count 2 2006.285.21:31:18.15#ibcon#first serial, iclass 30, count 2 2006.285.21:31:18.15#ibcon#enter sib2, iclass 30, count 2 2006.285.21:31:18.15#ibcon#flushed, iclass 30, count 2 2006.285.21:31:18.15#ibcon#about to write, iclass 30, count 2 2006.285.21:31:18.15#ibcon#wrote, iclass 30, count 2 2006.285.21:31:18.15#ibcon#about to read 3, iclass 30, count 2 2006.285.21:31:18.17#ibcon#read 3, iclass 30, count 2 2006.285.21:31:18.17#ibcon#about to read 4, iclass 30, count 2 2006.285.21:31:18.17#ibcon#read 4, iclass 30, count 2 2006.285.21:31:18.17#ibcon#about to read 5, iclass 30, count 2 2006.285.21:31:18.17#ibcon#read 5, iclass 30, count 2 2006.285.21:31:18.17#ibcon#about to read 6, iclass 30, count 2 2006.285.21:31:18.17#ibcon#read 6, iclass 30, count 2 2006.285.21:31:18.17#ibcon#end of sib2, iclass 30, count 2 2006.285.21:31:18.17#ibcon#*mode == 0, iclass 30, count 2 2006.285.21:31:18.17#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.21:31:18.17#ibcon#[25=AT01-07\r\n] 2006.285.21:31:18.17#ibcon#*before write, iclass 30, count 2 2006.285.21:31:18.17#ibcon#enter sib2, iclass 30, count 2 2006.285.21:31:18.17#ibcon#flushed, iclass 30, count 2 2006.285.21:31:18.17#ibcon#about to write, iclass 30, count 2 2006.285.21:31:18.17#ibcon#wrote, iclass 30, count 2 2006.285.21:31:18.17#ibcon#about to read 3, iclass 30, count 2 2006.285.21:31:18.20#ibcon#read 3, iclass 30, count 2 2006.285.21:31:18.20#ibcon#about to read 4, iclass 30, count 2 2006.285.21:31:18.20#ibcon#read 4, iclass 30, count 2 2006.285.21:31:18.20#ibcon#about to read 5, iclass 30, count 2 2006.285.21:31:18.20#ibcon#read 5, iclass 30, count 2 2006.285.21:31:18.20#ibcon#about to read 6, iclass 30, count 2 2006.285.21:31:18.20#ibcon#read 6, iclass 30, count 2 2006.285.21:31:18.20#ibcon#end of sib2, iclass 30, count 2 2006.285.21:31:18.20#ibcon#*after write, iclass 30, count 2 2006.285.21:31:18.20#ibcon#*before return 0, iclass 30, count 2 2006.285.21:31:18.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:31:18.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:31:18.20#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.21:31:18.20#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:18.20#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:31:18.32#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:31:18.32#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:31:18.32#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:31:18.32#ibcon#first serial, iclass 30, count 0 2006.285.21:31:18.32#ibcon#enter sib2, iclass 30, count 0 2006.285.21:31:18.32#ibcon#flushed, iclass 30, count 0 2006.285.21:31:18.32#ibcon#about to write, iclass 30, count 0 2006.285.21:31:18.32#ibcon#wrote, iclass 30, count 0 2006.285.21:31:18.32#ibcon#about to read 3, iclass 30, count 0 2006.285.21:31:18.34#ibcon#read 3, iclass 30, count 0 2006.285.21:31:18.34#ibcon#about to read 4, iclass 30, count 0 2006.285.21:31:18.34#ibcon#read 4, iclass 30, count 0 2006.285.21:31:18.34#ibcon#about to read 5, iclass 30, count 0 2006.285.21:31:18.34#ibcon#read 5, iclass 30, count 0 2006.285.21:31:18.34#ibcon#about to read 6, iclass 30, count 0 2006.285.21:31:18.34#ibcon#read 6, iclass 30, count 0 2006.285.21:31:18.34#ibcon#end of sib2, iclass 30, count 0 2006.285.21:31:18.34#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:31:18.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:31:18.34#ibcon#[25=USB\r\n] 2006.285.21:31:18.34#ibcon#*before write, iclass 30, count 0 2006.285.21:31:18.34#ibcon#enter sib2, iclass 30, count 0 2006.285.21:31:18.34#ibcon#flushed, iclass 30, count 0 2006.285.21:31:18.34#ibcon#about to write, iclass 30, count 0 2006.285.21:31:18.34#ibcon#wrote, iclass 30, count 0 2006.285.21:31:18.34#ibcon#about to read 3, iclass 30, count 0 2006.285.21:31:18.37#ibcon#read 3, iclass 30, count 0 2006.285.21:31:18.37#ibcon#about to read 4, iclass 30, count 0 2006.285.21:31:18.37#ibcon#read 4, iclass 30, count 0 2006.285.21:31:18.37#ibcon#about to read 5, iclass 30, count 0 2006.285.21:31:18.37#ibcon#read 5, iclass 30, count 0 2006.285.21:31:18.37#ibcon#about to read 6, iclass 30, count 0 2006.285.21:31:18.37#ibcon#read 6, iclass 30, count 0 2006.285.21:31:18.37#ibcon#end of sib2, iclass 30, count 0 2006.285.21:31:18.37#ibcon#*after write, iclass 30, count 0 2006.285.21:31:18.37#ibcon#*before return 0, iclass 30, count 0 2006.285.21:31:18.37#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:31:18.37#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:31:18.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:31:18.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:31:18.37$vck44/valo=2,534.99 2006.285.21:31:18.37#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.21:31:18.37#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.21:31:18.37#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:18.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:31:18.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:31:18.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:31:18.37#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:31:18.37#ibcon#first serial, iclass 32, count 0 2006.285.21:31:18.37#ibcon#enter sib2, iclass 32, count 0 2006.285.21:31:18.37#ibcon#flushed, iclass 32, count 0 2006.285.21:31:18.37#ibcon#about to write, iclass 32, count 0 2006.285.21:31:18.37#ibcon#wrote, iclass 32, count 0 2006.285.21:31:18.37#ibcon#about to read 3, iclass 32, count 0 2006.285.21:31:18.39#ibcon#read 3, iclass 32, count 0 2006.285.21:31:18.39#ibcon#about to read 4, iclass 32, count 0 2006.285.21:31:18.39#ibcon#read 4, iclass 32, count 0 2006.285.21:31:18.39#ibcon#about to read 5, iclass 32, count 0 2006.285.21:31:18.39#ibcon#read 5, iclass 32, count 0 2006.285.21:31:18.39#ibcon#about to read 6, iclass 32, count 0 2006.285.21:31:18.39#ibcon#read 6, iclass 32, count 0 2006.285.21:31:18.39#ibcon#end of sib2, iclass 32, count 0 2006.285.21:31:18.39#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:31:18.39#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:31:18.39#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:31:18.39#ibcon#*before write, iclass 32, count 0 2006.285.21:31:18.39#ibcon#enter sib2, iclass 32, count 0 2006.285.21:31:18.39#ibcon#flushed, iclass 32, count 0 2006.285.21:31:18.39#ibcon#about to write, iclass 32, count 0 2006.285.21:31:18.39#ibcon#wrote, iclass 32, count 0 2006.285.21:31:18.39#ibcon#about to read 3, iclass 32, count 0 2006.285.21:31:18.43#ibcon#read 3, iclass 32, count 0 2006.285.21:31:18.43#ibcon#about to read 4, iclass 32, count 0 2006.285.21:31:18.43#ibcon#read 4, iclass 32, count 0 2006.285.21:31:18.43#ibcon#about to read 5, iclass 32, count 0 2006.285.21:31:18.43#ibcon#read 5, iclass 32, count 0 2006.285.21:31:18.43#ibcon#about to read 6, iclass 32, count 0 2006.285.21:31:18.43#ibcon#read 6, iclass 32, count 0 2006.285.21:31:18.43#ibcon#end of sib2, iclass 32, count 0 2006.285.21:31:18.43#ibcon#*after write, iclass 32, count 0 2006.285.21:31:18.43#ibcon#*before return 0, iclass 32, count 0 2006.285.21:31:18.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:31:18.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:31:18.43#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:31:18.43#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:31:18.43$vck44/va=2,6 2006.285.21:31:18.92#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.21:31:18.92#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.21:31:18.92#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:18.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:31:18.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:31:18.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:31:18.92#ibcon#enter wrdev, iclass 34, count 2 2006.285.21:31:18.92#ibcon#first serial, iclass 34, count 2 2006.285.21:31:18.92#ibcon#enter sib2, iclass 34, count 2 2006.285.21:31:18.92#ibcon#flushed, iclass 34, count 2 2006.285.21:31:18.92#ibcon#about to write, iclass 34, count 2 2006.285.21:31:18.92#ibcon#wrote, iclass 34, count 2 2006.285.21:31:18.92#ibcon#about to read 3, iclass 34, count 2 2006.285.21:31:18.94#ibcon#read 3, iclass 34, count 2 2006.285.21:31:18.94#ibcon#about to read 4, iclass 34, count 2 2006.285.21:31:18.94#ibcon#read 4, iclass 34, count 2 2006.285.21:31:18.94#ibcon#about to read 5, iclass 34, count 2 2006.285.21:31:18.94#ibcon#read 5, iclass 34, count 2 2006.285.21:31:18.94#ibcon#about to read 6, iclass 34, count 2 2006.285.21:31:18.94#ibcon#read 6, iclass 34, count 2 2006.285.21:31:18.94#ibcon#end of sib2, iclass 34, count 2 2006.285.21:31:18.94#ibcon#*mode == 0, iclass 34, count 2 2006.285.21:31:18.94#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.21:31:18.94#ibcon#[25=AT02-06\r\n] 2006.285.21:31:18.94#ibcon#*before write, iclass 34, count 2 2006.285.21:31:18.94#ibcon#enter sib2, iclass 34, count 2 2006.285.21:31:18.94#ibcon#flushed, iclass 34, count 2 2006.285.21:31:18.94#ibcon#about to write, iclass 34, count 2 2006.285.21:31:18.94#ibcon#wrote, iclass 34, count 2 2006.285.21:31:18.94#ibcon#about to read 3, iclass 34, count 2 2006.285.21:31:18.97#ibcon#read 3, iclass 34, count 2 2006.285.21:31:18.97#ibcon#about to read 4, iclass 34, count 2 2006.285.21:31:18.97#ibcon#read 4, iclass 34, count 2 2006.285.21:31:18.97#ibcon#about to read 5, iclass 34, count 2 2006.285.21:31:18.97#ibcon#read 5, iclass 34, count 2 2006.285.21:31:18.97#ibcon#about to read 6, iclass 34, count 2 2006.285.21:31:18.97#ibcon#read 6, iclass 34, count 2 2006.285.21:31:18.97#ibcon#end of sib2, iclass 34, count 2 2006.285.21:31:18.97#ibcon#*after write, iclass 34, count 2 2006.285.21:31:18.97#ibcon#*before return 0, iclass 34, count 2 2006.285.21:31:18.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:31:18.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:31:18.97#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.21:31:18.97#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:18.97#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:31:19.09#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:31:19.09#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:31:19.09#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:31:19.09#ibcon#first serial, iclass 34, count 0 2006.285.21:31:19.09#ibcon#enter sib2, iclass 34, count 0 2006.285.21:31:19.09#ibcon#flushed, iclass 34, count 0 2006.285.21:31:19.09#ibcon#about to write, iclass 34, count 0 2006.285.21:31:19.09#ibcon#wrote, iclass 34, count 0 2006.285.21:31:19.09#ibcon#about to read 3, iclass 34, count 0 2006.285.21:31:19.11#ibcon#read 3, iclass 34, count 0 2006.285.21:31:19.11#ibcon#about to read 4, iclass 34, count 0 2006.285.21:31:19.11#ibcon#read 4, iclass 34, count 0 2006.285.21:31:19.11#ibcon#about to read 5, iclass 34, count 0 2006.285.21:31:19.11#ibcon#read 5, iclass 34, count 0 2006.285.21:31:19.11#ibcon#about to read 6, iclass 34, count 0 2006.285.21:31:19.11#ibcon#read 6, iclass 34, count 0 2006.285.21:31:19.11#ibcon#end of sib2, iclass 34, count 0 2006.285.21:31:19.11#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:31:19.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:31:19.11#ibcon#[25=USB\r\n] 2006.285.21:31:19.11#ibcon#*before write, iclass 34, count 0 2006.285.21:31:19.11#ibcon#enter sib2, iclass 34, count 0 2006.285.21:31:19.11#ibcon#flushed, iclass 34, count 0 2006.285.21:31:19.11#ibcon#about to write, iclass 34, count 0 2006.285.21:31:19.11#ibcon#wrote, iclass 34, count 0 2006.285.21:31:19.11#ibcon#about to read 3, iclass 34, count 0 2006.285.21:31:19.14#ibcon#read 3, iclass 34, count 0 2006.285.21:31:19.14#ibcon#about to read 4, iclass 34, count 0 2006.285.21:31:19.14#ibcon#read 4, iclass 34, count 0 2006.285.21:31:19.14#ibcon#about to read 5, iclass 34, count 0 2006.285.21:31:19.14#ibcon#read 5, iclass 34, count 0 2006.285.21:31:19.14#ibcon#about to read 6, iclass 34, count 0 2006.285.21:31:19.14#ibcon#read 6, iclass 34, count 0 2006.285.21:31:19.14#ibcon#end of sib2, iclass 34, count 0 2006.285.21:31:19.14#ibcon#*after write, iclass 34, count 0 2006.285.21:31:19.14#ibcon#*before return 0, iclass 34, count 0 2006.285.21:31:19.14#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:31:19.14#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:31:19.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:31:19.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:31:19.14$vck44/valo=3,564.99 2006.285.21:31:19.14#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.21:31:19.14#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.21:31:19.14#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:19.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:31:19.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:31:19.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:31:19.14#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:31:19.14#ibcon#first serial, iclass 36, count 0 2006.285.21:31:19.14#ibcon#enter sib2, iclass 36, count 0 2006.285.21:31:19.14#ibcon#flushed, iclass 36, count 0 2006.285.21:31:19.14#ibcon#about to write, iclass 36, count 0 2006.285.21:31:19.14#ibcon#wrote, iclass 36, count 0 2006.285.21:31:19.14#ibcon#about to read 3, iclass 36, count 0 2006.285.21:31:19.16#ibcon#read 3, iclass 36, count 0 2006.285.21:31:19.16#ibcon#about to read 4, iclass 36, count 0 2006.285.21:31:19.16#ibcon#read 4, iclass 36, count 0 2006.285.21:31:19.16#ibcon#about to read 5, iclass 36, count 0 2006.285.21:31:19.16#ibcon#read 5, iclass 36, count 0 2006.285.21:31:19.16#ibcon#about to read 6, iclass 36, count 0 2006.285.21:31:19.16#ibcon#read 6, iclass 36, count 0 2006.285.21:31:19.16#ibcon#end of sib2, iclass 36, count 0 2006.285.21:31:19.16#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:31:19.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:31:19.16#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:31:19.16#ibcon#*before write, iclass 36, count 0 2006.285.21:31:19.16#ibcon#enter sib2, iclass 36, count 0 2006.285.21:31:19.16#ibcon#flushed, iclass 36, count 0 2006.285.21:31:19.16#ibcon#about to write, iclass 36, count 0 2006.285.21:31:19.16#ibcon#wrote, iclass 36, count 0 2006.285.21:31:19.16#ibcon#about to read 3, iclass 36, count 0 2006.285.21:31:19.20#ibcon#read 3, iclass 36, count 0 2006.285.21:31:19.20#ibcon#about to read 4, iclass 36, count 0 2006.285.21:31:19.20#ibcon#read 4, iclass 36, count 0 2006.285.21:31:19.20#ibcon#about to read 5, iclass 36, count 0 2006.285.21:31:19.20#ibcon#read 5, iclass 36, count 0 2006.285.21:31:19.20#ibcon#about to read 6, iclass 36, count 0 2006.285.21:31:19.20#ibcon#read 6, iclass 36, count 0 2006.285.21:31:19.20#ibcon#end of sib2, iclass 36, count 0 2006.285.21:31:19.20#ibcon#*after write, iclass 36, count 0 2006.285.21:31:19.20#ibcon#*before return 0, iclass 36, count 0 2006.285.21:31:19.20#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:31:19.20#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:31:19.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:31:19.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:31:19.20$vck44/va=3,7 2006.285.21:31:19.20#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.21:31:19.20#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.21:31:19.20#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:19.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:31:19.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:31:19.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:31:19.26#ibcon#enter wrdev, iclass 38, count 2 2006.285.21:31:19.26#ibcon#first serial, iclass 38, count 2 2006.285.21:31:19.26#ibcon#enter sib2, iclass 38, count 2 2006.285.21:31:19.26#ibcon#flushed, iclass 38, count 2 2006.285.21:31:19.26#ibcon#about to write, iclass 38, count 2 2006.285.21:31:19.26#ibcon#wrote, iclass 38, count 2 2006.285.21:31:19.26#ibcon#about to read 3, iclass 38, count 2 2006.285.21:31:19.28#ibcon#read 3, iclass 38, count 2 2006.285.21:31:19.47#ibcon#about to read 4, iclass 38, count 2 2006.285.21:31:19.47#ibcon#read 4, iclass 38, count 2 2006.285.21:31:19.47#ibcon#about to read 5, iclass 38, count 2 2006.285.21:31:19.47#ibcon#read 5, iclass 38, count 2 2006.285.21:31:19.47#ibcon#about to read 6, iclass 38, count 2 2006.285.21:31:19.47#ibcon#read 6, iclass 38, count 2 2006.285.21:31:19.47#ibcon#end of sib2, iclass 38, count 2 2006.285.21:31:19.47#ibcon#*mode == 0, iclass 38, count 2 2006.285.21:31:19.47#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.21:31:19.47#ibcon#[25=AT03-07\r\n] 2006.285.21:31:19.47#ibcon#*before write, iclass 38, count 2 2006.285.21:31:19.47#ibcon#enter sib2, iclass 38, count 2 2006.285.21:31:19.47#ibcon#flushed, iclass 38, count 2 2006.285.21:31:19.47#ibcon#about to write, iclass 38, count 2 2006.285.21:31:19.47#ibcon#wrote, iclass 38, count 2 2006.285.21:31:19.47#ibcon#about to read 3, iclass 38, count 2 2006.285.21:31:19.50#ibcon#read 3, iclass 38, count 2 2006.285.21:31:19.50#ibcon#about to read 4, iclass 38, count 2 2006.285.21:31:19.50#ibcon#read 4, iclass 38, count 2 2006.285.21:31:19.50#ibcon#about to read 5, iclass 38, count 2 2006.285.21:31:19.50#ibcon#read 5, iclass 38, count 2 2006.285.21:31:19.50#ibcon#about to read 6, iclass 38, count 2 2006.285.21:31:19.50#ibcon#read 6, iclass 38, count 2 2006.285.21:31:19.50#ibcon#end of sib2, iclass 38, count 2 2006.285.21:31:19.50#ibcon#*after write, iclass 38, count 2 2006.285.21:31:19.50#ibcon#*before return 0, iclass 38, count 2 2006.285.21:31:19.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:31:19.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:31:19.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.21:31:19.50#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:19.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:31:19.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:31:19.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:31:19.62#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:31:19.62#ibcon#first serial, iclass 38, count 0 2006.285.21:31:19.62#ibcon#enter sib2, iclass 38, count 0 2006.285.21:31:19.62#ibcon#flushed, iclass 38, count 0 2006.285.21:31:19.62#ibcon#about to write, iclass 38, count 0 2006.285.21:31:19.62#ibcon#wrote, iclass 38, count 0 2006.285.21:31:19.62#ibcon#about to read 3, iclass 38, count 0 2006.285.21:31:19.64#ibcon#read 3, iclass 38, count 0 2006.285.21:31:19.64#ibcon#about to read 4, iclass 38, count 0 2006.285.21:31:19.64#ibcon#read 4, iclass 38, count 0 2006.285.21:31:19.64#ibcon#about to read 5, iclass 38, count 0 2006.285.21:31:19.64#ibcon#read 5, iclass 38, count 0 2006.285.21:31:19.64#ibcon#about to read 6, iclass 38, count 0 2006.285.21:31:19.64#ibcon#read 6, iclass 38, count 0 2006.285.21:31:19.64#ibcon#end of sib2, iclass 38, count 0 2006.285.21:31:19.64#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:31:19.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:31:19.64#ibcon#[25=USB\r\n] 2006.285.21:31:19.64#ibcon#*before write, iclass 38, count 0 2006.285.21:31:19.64#ibcon#enter sib2, iclass 38, count 0 2006.285.21:31:19.64#ibcon#flushed, iclass 38, count 0 2006.285.21:31:19.64#ibcon#about to write, iclass 38, count 0 2006.285.21:31:19.64#ibcon#wrote, iclass 38, count 0 2006.285.21:31:19.64#ibcon#about to read 3, iclass 38, count 0 2006.285.21:31:19.67#ibcon#read 3, iclass 38, count 0 2006.285.21:31:19.67#ibcon#about to read 4, iclass 38, count 0 2006.285.21:31:19.67#ibcon#read 4, iclass 38, count 0 2006.285.21:31:19.67#ibcon#about to read 5, iclass 38, count 0 2006.285.21:31:19.67#ibcon#read 5, iclass 38, count 0 2006.285.21:31:19.67#ibcon#about to read 6, iclass 38, count 0 2006.285.21:31:19.67#ibcon#read 6, iclass 38, count 0 2006.285.21:31:19.67#ibcon#end of sib2, iclass 38, count 0 2006.285.21:31:19.67#ibcon#*after write, iclass 38, count 0 2006.285.21:31:19.67#ibcon#*before return 0, iclass 38, count 0 2006.285.21:31:19.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:31:19.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:31:19.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:31:19.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:31:19.67$vck44/valo=4,624.99 2006.285.21:31:19.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.21:31:19.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.21:31:19.67#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:19.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:31:19.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:31:19.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:31:19.67#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:31:19.67#ibcon#first serial, iclass 40, count 0 2006.285.21:31:19.67#ibcon#enter sib2, iclass 40, count 0 2006.285.21:31:19.67#ibcon#flushed, iclass 40, count 0 2006.285.21:31:19.67#ibcon#about to write, iclass 40, count 0 2006.285.21:31:19.67#ibcon#wrote, iclass 40, count 0 2006.285.21:31:19.67#ibcon#about to read 3, iclass 40, count 0 2006.285.21:31:19.69#ibcon#read 3, iclass 40, count 0 2006.285.21:31:19.75#ibcon#about to read 4, iclass 40, count 0 2006.285.21:31:19.75#ibcon#read 4, iclass 40, count 0 2006.285.21:31:19.75#ibcon#about to read 5, iclass 40, count 0 2006.285.21:31:19.75#ibcon#read 5, iclass 40, count 0 2006.285.21:31:19.75#ibcon#about to read 6, iclass 40, count 0 2006.285.21:31:19.75#ibcon#read 6, iclass 40, count 0 2006.285.21:31:19.75#ibcon#end of sib2, iclass 40, count 0 2006.285.21:31:19.75#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:31:19.75#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:31:19.75#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:31:19.75#ibcon#*before write, iclass 40, count 0 2006.285.21:31:19.75#ibcon#enter sib2, iclass 40, count 0 2006.285.21:31:19.75#ibcon#flushed, iclass 40, count 0 2006.285.21:31:19.75#ibcon#about to write, iclass 40, count 0 2006.285.21:31:19.75#ibcon#wrote, iclass 40, count 0 2006.285.21:31:19.75#ibcon#about to read 3, iclass 40, count 0 2006.285.21:31:19.79#ibcon#read 3, iclass 40, count 0 2006.285.21:31:19.79#ibcon#about to read 4, iclass 40, count 0 2006.285.21:31:19.79#ibcon#read 4, iclass 40, count 0 2006.285.21:31:19.79#ibcon#about to read 5, iclass 40, count 0 2006.285.21:31:19.79#ibcon#read 5, iclass 40, count 0 2006.285.21:31:19.79#ibcon#about to read 6, iclass 40, count 0 2006.285.21:31:19.79#ibcon#read 6, iclass 40, count 0 2006.285.21:31:19.79#ibcon#end of sib2, iclass 40, count 0 2006.285.21:31:19.79#ibcon#*after write, iclass 40, count 0 2006.285.21:31:19.79#ibcon#*before return 0, iclass 40, count 0 2006.285.21:31:19.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:31:19.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:31:19.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:31:19.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:31:19.79$vck44/va=4,6 2006.285.21:31:19.79#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.21:31:19.79#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.21:31:19.79#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:19.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:31:19.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:31:19.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:31:19.79#ibcon#enter wrdev, iclass 4, count 2 2006.285.21:31:19.79#ibcon#first serial, iclass 4, count 2 2006.285.21:31:19.79#ibcon#enter sib2, iclass 4, count 2 2006.285.21:31:19.79#ibcon#flushed, iclass 4, count 2 2006.285.21:31:19.79#ibcon#about to write, iclass 4, count 2 2006.285.21:31:19.79#ibcon#wrote, iclass 4, count 2 2006.285.21:31:19.79#ibcon#about to read 3, iclass 4, count 2 2006.285.21:31:19.81#ibcon#read 3, iclass 4, count 2 2006.285.21:31:19.81#ibcon#about to read 4, iclass 4, count 2 2006.285.21:31:19.81#ibcon#read 4, iclass 4, count 2 2006.285.21:31:19.81#ibcon#about to read 5, iclass 4, count 2 2006.285.21:31:19.81#ibcon#read 5, iclass 4, count 2 2006.285.21:31:19.81#ibcon#about to read 6, iclass 4, count 2 2006.285.21:31:19.81#ibcon#read 6, iclass 4, count 2 2006.285.21:31:19.81#ibcon#end of sib2, iclass 4, count 2 2006.285.21:31:19.81#ibcon#*mode == 0, iclass 4, count 2 2006.285.21:31:19.81#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.21:31:19.81#ibcon#[25=AT04-06\r\n] 2006.285.21:31:19.81#ibcon#*before write, iclass 4, count 2 2006.285.21:31:19.81#ibcon#enter sib2, iclass 4, count 2 2006.285.21:31:19.81#ibcon#flushed, iclass 4, count 2 2006.285.21:31:19.81#ibcon#about to write, iclass 4, count 2 2006.285.21:31:19.81#ibcon#wrote, iclass 4, count 2 2006.285.21:31:19.81#ibcon#about to read 3, iclass 4, count 2 2006.285.21:31:19.84#ibcon#read 3, iclass 4, count 2 2006.285.21:31:19.84#ibcon#about to read 4, iclass 4, count 2 2006.285.21:31:19.84#ibcon#read 4, iclass 4, count 2 2006.285.21:31:19.84#ibcon#about to read 5, iclass 4, count 2 2006.285.21:31:19.84#ibcon#read 5, iclass 4, count 2 2006.285.21:31:19.84#ibcon#about to read 6, iclass 4, count 2 2006.285.21:31:19.84#ibcon#read 6, iclass 4, count 2 2006.285.21:31:19.84#ibcon#end of sib2, iclass 4, count 2 2006.285.21:31:19.84#ibcon#*after write, iclass 4, count 2 2006.285.21:31:19.84#ibcon#*before return 0, iclass 4, count 2 2006.285.21:31:19.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:31:19.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:31:19.84#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.21:31:19.84#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:19.84#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:31:19.96#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:31:19.96#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:31:19.96#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:31:19.96#ibcon#first serial, iclass 4, count 0 2006.285.21:31:19.96#ibcon#enter sib2, iclass 4, count 0 2006.285.21:31:19.96#ibcon#flushed, iclass 4, count 0 2006.285.21:31:19.96#ibcon#about to write, iclass 4, count 0 2006.285.21:31:19.96#ibcon#wrote, iclass 4, count 0 2006.285.21:31:19.96#ibcon#about to read 3, iclass 4, count 0 2006.285.21:31:19.98#ibcon#read 3, iclass 4, count 0 2006.285.21:31:19.98#ibcon#about to read 4, iclass 4, count 0 2006.285.21:31:19.98#ibcon#read 4, iclass 4, count 0 2006.285.21:31:19.98#ibcon#about to read 5, iclass 4, count 0 2006.285.21:31:19.98#ibcon#read 5, iclass 4, count 0 2006.285.21:31:19.98#ibcon#about to read 6, iclass 4, count 0 2006.285.21:31:19.98#ibcon#read 6, iclass 4, count 0 2006.285.21:31:19.98#ibcon#end of sib2, iclass 4, count 0 2006.285.21:31:19.98#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:31:19.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:31:19.98#ibcon#[25=USB\r\n] 2006.285.21:31:19.98#ibcon#*before write, iclass 4, count 0 2006.285.21:31:19.98#ibcon#enter sib2, iclass 4, count 0 2006.285.21:31:19.98#ibcon#flushed, iclass 4, count 0 2006.285.21:31:19.98#ibcon#about to write, iclass 4, count 0 2006.285.21:31:19.98#ibcon#wrote, iclass 4, count 0 2006.285.21:31:19.98#ibcon#about to read 3, iclass 4, count 0 2006.285.21:31:20.01#ibcon#read 3, iclass 4, count 0 2006.285.21:31:20.01#ibcon#about to read 4, iclass 4, count 0 2006.285.21:31:20.01#ibcon#read 4, iclass 4, count 0 2006.285.21:31:20.01#ibcon#about to read 5, iclass 4, count 0 2006.285.21:31:20.01#ibcon#read 5, iclass 4, count 0 2006.285.21:31:20.01#ibcon#about to read 6, iclass 4, count 0 2006.285.21:31:20.01#ibcon#read 6, iclass 4, count 0 2006.285.21:31:20.01#ibcon#end of sib2, iclass 4, count 0 2006.285.21:31:20.01#ibcon#*after write, iclass 4, count 0 2006.285.21:31:20.01#ibcon#*before return 0, iclass 4, count 0 2006.285.21:31:20.01#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:31:20.01#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:31:20.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:31:20.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:31:20.01$vck44/valo=5,734.99 2006.285.21:31:20.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.21:31:20.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.21:31:20.01#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:20.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:31:20.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:31:20.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:31:20.01#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:31:20.01#ibcon#first serial, iclass 6, count 0 2006.285.21:31:20.01#ibcon#enter sib2, iclass 6, count 0 2006.285.21:31:20.01#ibcon#flushed, iclass 6, count 0 2006.285.21:31:20.01#ibcon#about to write, iclass 6, count 0 2006.285.21:31:20.01#ibcon#wrote, iclass 6, count 0 2006.285.21:31:20.01#ibcon#about to read 3, iclass 6, count 0 2006.285.21:31:20.03#ibcon#read 3, iclass 6, count 0 2006.285.21:31:20.03#ibcon#about to read 4, iclass 6, count 0 2006.285.21:31:20.03#ibcon#read 4, iclass 6, count 0 2006.285.21:31:20.03#ibcon#about to read 5, iclass 6, count 0 2006.285.21:31:20.03#ibcon#read 5, iclass 6, count 0 2006.285.21:31:20.03#ibcon#about to read 6, iclass 6, count 0 2006.285.21:31:20.03#ibcon#read 6, iclass 6, count 0 2006.285.21:31:20.03#ibcon#end of sib2, iclass 6, count 0 2006.285.21:31:20.03#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:31:20.03#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:31:20.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:31:20.03#ibcon#*before write, iclass 6, count 0 2006.285.21:31:20.03#ibcon#enter sib2, iclass 6, count 0 2006.285.21:31:20.03#ibcon#flushed, iclass 6, count 0 2006.285.21:31:20.03#ibcon#about to write, iclass 6, count 0 2006.285.21:31:20.03#ibcon#wrote, iclass 6, count 0 2006.285.21:31:20.03#ibcon#about to read 3, iclass 6, count 0 2006.285.21:31:20.07#ibcon#read 3, iclass 6, count 0 2006.285.21:31:20.07#ibcon#about to read 4, iclass 6, count 0 2006.285.21:31:20.07#ibcon#read 4, iclass 6, count 0 2006.285.21:31:20.07#ibcon#about to read 5, iclass 6, count 0 2006.285.21:31:20.07#ibcon#read 5, iclass 6, count 0 2006.285.21:31:20.07#ibcon#about to read 6, iclass 6, count 0 2006.285.21:31:20.07#ibcon#read 6, iclass 6, count 0 2006.285.21:31:20.07#ibcon#end of sib2, iclass 6, count 0 2006.285.21:31:20.07#ibcon#*after write, iclass 6, count 0 2006.285.21:31:20.07#ibcon#*before return 0, iclass 6, count 0 2006.285.21:31:20.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:31:20.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:31:20.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:31:20.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:31:20.07$vck44/va=5,3 2006.285.21:31:20.07#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.21:31:20.07#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.21:31:20.07#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:20.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:31:20.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:31:20.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:31:20.13#ibcon#enter wrdev, iclass 10, count 2 2006.285.21:31:20.13#ibcon#first serial, iclass 10, count 2 2006.285.21:31:20.13#ibcon#enter sib2, iclass 10, count 2 2006.285.21:31:20.13#ibcon#flushed, iclass 10, count 2 2006.285.21:31:20.13#ibcon#about to write, iclass 10, count 2 2006.285.21:31:20.13#ibcon#wrote, iclass 10, count 2 2006.285.21:31:20.13#ibcon#about to read 3, iclass 10, count 2 2006.285.21:31:20.15#ibcon#read 3, iclass 10, count 2 2006.285.21:31:20.15#ibcon#about to read 4, iclass 10, count 2 2006.285.21:31:20.15#ibcon#read 4, iclass 10, count 2 2006.285.21:31:20.15#ibcon#about to read 5, iclass 10, count 2 2006.285.21:31:20.15#ibcon#read 5, iclass 10, count 2 2006.285.21:31:20.15#ibcon#about to read 6, iclass 10, count 2 2006.285.21:31:20.15#ibcon#read 6, iclass 10, count 2 2006.285.21:31:20.15#ibcon#end of sib2, iclass 10, count 2 2006.285.21:31:20.15#ibcon#*mode == 0, iclass 10, count 2 2006.285.21:31:20.15#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.21:31:20.15#ibcon#[25=AT05-03\r\n] 2006.285.21:31:20.15#ibcon#*before write, iclass 10, count 2 2006.285.21:31:20.15#ibcon#enter sib2, iclass 10, count 2 2006.285.21:31:20.15#ibcon#flushed, iclass 10, count 2 2006.285.21:31:20.15#ibcon#about to write, iclass 10, count 2 2006.285.21:31:20.15#ibcon#wrote, iclass 10, count 2 2006.285.21:31:20.15#ibcon#about to read 3, iclass 10, count 2 2006.285.21:31:20.18#ibcon#read 3, iclass 10, count 2 2006.285.21:31:20.18#ibcon#about to read 4, iclass 10, count 2 2006.285.21:31:20.18#ibcon#read 4, iclass 10, count 2 2006.285.21:31:20.18#ibcon#about to read 5, iclass 10, count 2 2006.285.21:31:20.18#ibcon#read 5, iclass 10, count 2 2006.285.21:31:20.18#ibcon#about to read 6, iclass 10, count 2 2006.285.21:31:20.18#ibcon#read 6, iclass 10, count 2 2006.285.21:31:20.18#ibcon#end of sib2, iclass 10, count 2 2006.285.21:31:20.18#ibcon#*after write, iclass 10, count 2 2006.285.21:31:20.18#ibcon#*before return 0, iclass 10, count 2 2006.285.21:31:20.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:31:20.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:31:20.18#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.21:31:20.18#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:20.18#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:31:20.30#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:31:20.30#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:31:20.30#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:31:20.30#ibcon#first serial, iclass 10, count 0 2006.285.21:31:20.30#ibcon#enter sib2, iclass 10, count 0 2006.285.21:31:20.30#ibcon#flushed, iclass 10, count 0 2006.285.21:31:20.30#ibcon#about to write, iclass 10, count 0 2006.285.21:31:20.30#ibcon#wrote, iclass 10, count 0 2006.285.21:31:20.30#ibcon#about to read 3, iclass 10, count 0 2006.285.21:31:20.32#ibcon#read 3, iclass 10, count 0 2006.285.21:31:20.32#ibcon#about to read 4, iclass 10, count 0 2006.285.21:31:20.32#ibcon#read 4, iclass 10, count 0 2006.285.21:31:20.32#ibcon#about to read 5, iclass 10, count 0 2006.285.21:31:20.32#ibcon#read 5, iclass 10, count 0 2006.285.21:31:20.32#ibcon#about to read 6, iclass 10, count 0 2006.285.21:31:20.32#ibcon#read 6, iclass 10, count 0 2006.285.21:31:20.32#ibcon#end of sib2, iclass 10, count 0 2006.285.21:31:20.32#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:31:20.32#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:31:20.32#ibcon#[25=USB\r\n] 2006.285.21:31:20.32#ibcon#*before write, iclass 10, count 0 2006.285.21:31:20.32#ibcon#enter sib2, iclass 10, count 0 2006.285.21:31:20.32#ibcon#flushed, iclass 10, count 0 2006.285.21:31:20.32#ibcon#about to write, iclass 10, count 0 2006.285.21:31:20.32#ibcon#wrote, iclass 10, count 0 2006.285.21:31:20.32#ibcon#about to read 3, iclass 10, count 0 2006.285.21:31:20.35#ibcon#read 3, iclass 10, count 0 2006.285.21:31:20.35#ibcon#about to read 4, iclass 10, count 0 2006.285.21:31:20.35#ibcon#read 4, iclass 10, count 0 2006.285.21:31:20.35#ibcon#about to read 5, iclass 10, count 0 2006.285.21:31:20.35#ibcon#read 5, iclass 10, count 0 2006.285.21:31:20.35#ibcon#about to read 6, iclass 10, count 0 2006.285.21:31:20.35#ibcon#read 6, iclass 10, count 0 2006.285.21:31:20.35#ibcon#end of sib2, iclass 10, count 0 2006.285.21:31:20.35#ibcon#*after write, iclass 10, count 0 2006.285.21:31:20.35#ibcon#*before return 0, iclass 10, count 0 2006.285.21:31:20.35#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:31:20.35#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:31:20.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:31:20.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:31:20.35$vck44/valo=6,814.99 2006.285.21:31:20.35#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.21:31:20.35#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.21:31:20.35#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:20.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:31:20.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:31:20.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:31:20.35#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:31:20.35#ibcon#first serial, iclass 12, count 0 2006.285.21:31:20.35#ibcon#enter sib2, iclass 12, count 0 2006.285.21:31:20.35#ibcon#flushed, iclass 12, count 0 2006.285.21:31:20.35#ibcon#about to write, iclass 12, count 0 2006.285.21:31:20.35#ibcon#wrote, iclass 12, count 0 2006.285.21:31:20.35#ibcon#about to read 3, iclass 12, count 0 2006.285.21:31:20.37#ibcon#read 3, iclass 12, count 0 2006.285.21:31:20.37#ibcon#about to read 4, iclass 12, count 0 2006.285.21:31:20.37#ibcon#read 4, iclass 12, count 0 2006.285.21:31:20.37#ibcon#about to read 5, iclass 12, count 0 2006.285.21:31:20.37#ibcon#read 5, iclass 12, count 0 2006.285.21:31:20.37#ibcon#about to read 6, iclass 12, count 0 2006.285.21:31:20.37#ibcon#read 6, iclass 12, count 0 2006.285.21:31:20.37#ibcon#end of sib2, iclass 12, count 0 2006.285.21:31:20.37#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:31:20.37#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:31:20.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:31:20.37#ibcon#*before write, iclass 12, count 0 2006.285.21:31:20.37#ibcon#enter sib2, iclass 12, count 0 2006.285.21:31:20.37#ibcon#flushed, iclass 12, count 0 2006.285.21:31:20.37#ibcon#about to write, iclass 12, count 0 2006.285.21:31:20.37#ibcon#wrote, iclass 12, count 0 2006.285.21:31:20.37#ibcon#about to read 3, iclass 12, count 0 2006.285.21:31:20.41#ibcon#read 3, iclass 12, count 0 2006.285.21:31:20.41#ibcon#about to read 4, iclass 12, count 0 2006.285.21:31:20.41#ibcon#read 4, iclass 12, count 0 2006.285.21:31:20.41#ibcon#about to read 5, iclass 12, count 0 2006.285.21:31:20.41#ibcon#read 5, iclass 12, count 0 2006.285.21:31:20.41#ibcon#about to read 6, iclass 12, count 0 2006.285.21:31:20.41#ibcon#read 6, iclass 12, count 0 2006.285.21:31:20.41#ibcon#end of sib2, iclass 12, count 0 2006.285.21:31:20.41#ibcon#*after write, iclass 12, count 0 2006.285.21:31:20.41#ibcon#*before return 0, iclass 12, count 0 2006.285.21:31:20.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:31:20.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:31:20.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:31:20.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:31:20.41$vck44/va=6,4 2006.285.21:31:20.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.21:31:20.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.21:31:20.41#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:20.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:31:20.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:31:20.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:31:20.47#ibcon#enter wrdev, iclass 14, count 2 2006.285.21:31:20.47#ibcon#first serial, iclass 14, count 2 2006.285.21:31:20.47#ibcon#enter sib2, iclass 14, count 2 2006.285.21:31:20.47#ibcon#flushed, iclass 14, count 2 2006.285.21:31:20.47#ibcon#about to write, iclass 14, count 2 2006.285.21:31:20.47#ibcon#wrote, iclass 14, count 2 2006.285.21:31:20.47#ibcon#about to read 3, iclass 14, count 2 2006.285.21:31:20.49#ibcon#read 3, iclass 14, count 2 2006.285.21:31:20.49#ibcon#about to read 4, iclass 14, count 2 2006.285.21:31:20.49#ibcon#read 4, iclass 14, count 2 2006.285.21:31:20.49#ibcon#about to read 5, iclass 14, count 2 2006.285.21:31:20.49#ibcon#read 5, iclass 14, count 2 2006.285.21:31:20.49#ibcon#about to read 6, iclass 14, count 2 2006.285.21:31:20.49#ibcon#read 6, iclass 14, count 2 2006.285.21:31:20.49#ibcon#end of sib2, iclass 14, count 2 2006.285.21:31:20.49#ibcon#*mode == 0, iclass 14, count 2 2006.285.21:31:20.49#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.21:31:20.49#ibcon#[25=AT06-04\r\n] 2006.285.21:31:20.49#ibcon#*before write, iclass 14, count 2 2006.285.21:31:20.49#ibcon#enter sib2, iclass 14, count 2 2006.285.21:31:20.49#ibcon#flushed, iclass 14, count 2 2006.285.21:31:20.49#ibcon#about to write, iclass 14, count 2 2006.285.21:31:20.49#ibcon#wrote, iclass 14, count 2 2006.285.21:31:20.49#ibcon#about to read 3, iclass 14, count 2 2006.285.21:31:20.52#ibcon#read 3, iclass 14, count 2 2006.285.21:31:20.52#ibcon#about to read 4, iclass 14, count 2 2006.285.21:31:20.52#ibcon#read 4, iclass 14, count 2 2006.285.21:31:20.52#ibcon#about to read 5, iclass 14, count 2 2006.285.21:31:20.52#ibcon#read 5, iclass 14, count 2 2006.285.21:31:20.52#ibcon#about to read 6, iclass 14, count 2 2006.285.21:31:20.52#ibcon#read 6, iclass 14, count 2 2006.285.21:31:20.52#ibcon#end of sib2, iclass 14, count 2 2006.285.21:31:20.52#ibcon#*after write, iclass 14, count 2 2006.285.21:31:20.52#ibcon#*before return 0, iclass 14, count 2 2006.285.21:31:20.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:31:20.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:31:20.52#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.21:31:20.52#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:20.52#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:31:20.64#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:31:20.67#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:31:20.67#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:31:20.67#ibcon#first serial, iclass 14, count 0 2006.285.21:31:20.67#ibcon#enter sib2, iclass 14, count 0 2006.285.21:31:20.67#ibcon#flushed, iclass 14, count 0 2006.285.21:31:20.67#ibcon#about to write, iclass 14, count 0 2006.285.21:31:20.67#ibcon#wrote, iclass 14, count 0 2006.285.21:31:20.67#ibcon#about to read 3, iclass 14, count 0 2006.285.21:31:20.69#ibcon#read 3, iclass 14, count 0 2006.285.21:31:20.69#ibcon#about to read 4, iclass 14, count 0 2006.285.21:31:20.69#ibcon#read 4, iclass 14, count 0 2006.285.21:31:20.69#ibcon#about to read 5, iclass 14, count 0 2006.285.21:31:20.69#ibcon#read 5, iclass 14, count 0 2006.285.21:31:20.69#ibcon#about to read 6, iclass 14, count 0 2006.285.21:31:20.69#ibcon#read 6, iclass 14, count 0 2006.285.21:31:20.69#ibcon#end of sib2, iclass 14, count 0 2006.285.21:31:20.69#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:31:20.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:31:20.69#ibcon#[25=USB\r\n] 2006.285.21:31:20.69#ibcon#*before write, iclass 14, count 0 2006.285.21:31:20.69#ibcon#enter sib2, iclass 14, count 0 2006.285.21:31:20.69#ibcon#flushed, iclass 14, count 0 2006.285.21:31:20.69#ibcon#about to write, iclass 14, count 0 2006.285.21:31:20.69#ibcon#wrote, iclass 14, count 0 2006.285.21:31:20.69#ibcon#about to read 3, iclass 14, count 0 2006.285.21:31:20.72#ibcon#read 3, iclass 14, count 0 2006.285.21:31:20.72#ibcon#about to read 4, iclass 14, count 0 2006.285.21:31:20.72#ibcon#read 4, iclass 14, count 0 2006.285.21:31:20.72#ibcon#about to read 5, iclass 14, count 0 2006.285.21:31:20.72#ibcon#read 5, iclass 14, count 0 2006.285.21:31:20.72#ibcon#about to read 6, iclass 14, count 0 2006.285.21:31:20.72#ibcon#read 6, iclass 14, count 0 2006.285.21:31:20.72#ibcon#end of sib2, iclass 14, count 0 2006.285.21:31:20.72#ibcon#*after write, iclass 14, count 0 2006.285.21:31:20.72#ibcon#*before return 0, iclass 14, count 0 2006.285.21:31:20.72#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:31:20.72#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:31:20.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:31:20.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:31:20.72$vck44/valo=7,864.99 2006.285.21:31:20.72#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.21:31:20.72#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.21:31:20.72#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:20.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:31:20.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:31:20.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:31:20.72#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:31:20.72#ibcon#first serial, iclass 16, count 0 2006.285.21:31:20.72#ibcon#enter sib2, iclass 16, count 0 2006.285.21:31:20.72#ibcon#flushed, iclass 16, count 0 2006.285.21:31:20.72#ibcon#about to write, iclass 16, count 0 2006.285.21:31:20.72#ibcon#wrote, iclass 16, count 0 2006.285.21:31:20.72#ibcon#about to read 3, iclass 16, count 0 2006.285.21:31:20.74#ibcon#read 3, iclass 16, count 0 2006.285.21:31:20.74#ibcon#about to read 4, iclass 16, count 0 2006.285.21:31:20.74#ibcon#read 4, iclass 16, count 0 2006.285.21:31:20.74#ibcon#about to read 5, iclass 16, count 0 2006.285.21:31:20.74#ibcon#read 5, iclass 16, count 0 2006.285.21:31:20.74#ibcon#about to read 6, iclass 16, count 0 2006.285.21:31:20.74#ibcon#read 6, iclass 16, count 0 2006.285.21:31:20.74#ibcon#end of sib2, iclass 16, count 0 2006.285.21:31:20.74#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:31:20.74#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:31:20.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:31:20.74#ibcon#*before write, iclass 16, count 0 2006.285.21:31:20.74#ibcon#enter sib2, iclass 16, count 0 2006.285.21:31:20.74#ibcon#flushed, iclass 16, count 0 2006.285.21:31:20.74#ibcon#about to write, iclass 16, count 0 2006.285.21:31:20.74#ibcon#wrote, iclass 16, count 0 2006.285.21:31:20.74#ibcon#about to read 3, iclass 16, count 0 2006.285.21:31:20.78#ibcon#read 3, iclass 16, count 0 2006.285.21:31:20.78#ibcon#about to read 4, iclass 16, count 0 2006.285.21:31:20.78#ibcon#read 4, iclass 16, count 0 2006.285.21:31:20.78#ibcon#about to read 5, iclass 16, count 0 2006.285.21:31:20.78#ibcon#read 5, iclass 16, count 0 2006.285.21:31:20.78#ibcon#about to read 6, iclass 16, count 0 2006.285.21:31:20.78#ibcon#read 6, iclass 16, count 0 2006.285.21:31:20.78#ibcon#end of sib2, iclass 16, count 0 2006.285.21:31:20.78#ibcon#*after write, iclass 16, count 0 2006.285.21:31:20.78#ibcon#*before return 0, iclass 16, count 0 2006.285.21:31:20.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:31:20.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:31:20.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:31:20.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:31:20.78$vck44/va=7,4 2006.285.21:31:20.78#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.21:31:20.78#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.21:31:20.78#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:20.78#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:31:20.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:31:20.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:31:20.84#ibcon#enter wrdev, iclass 18, count 2 2006.285.21:31:20.84#ibcon#first serial, iclass 18, count 2 2006.285.21:31:20.84#ibcon#enter sib2, iclass 18, count 2 2006.285.21:31:20.84#ibcon#flushed, iclass 18, count 2 2006.285.21:31:20.84#ibcon#about to write, iclass 18, count 2 2006.285.21:31:20.84#ibcon#wrote, iclass 18, count 2 2006.285.21:31:20.84#ibcon#about to read 3, iclass 18, count 2 2006.285.21:31:20.86#ibcon#read 3, iclass 18, count 2 2006.285.21:31:20.86#ibcon#about to read 4, iclass 18, count 2 2006.285.21:31:20.86#ibcon#read 4, iclass 18, count 2 2006.285.21:31:20.86#ibcon#about to read 5, iclass 18, count 2 2006.285.21:31:20.86#ibcon#read 5, iclass 18, count 2 2006.285.21:31:20.86#ibcon#about to read 6, iclass 18, count 2 2006.285.21:31:20.86#ibcon#read 6, iclass 18, count 2 2006.285.21:31:20.86#ibcon#end of sib2, iclass 18, count 2 2006.285.21:31:20.86#ibcon#*mode == 0, iclass 18, count 2 2006.285.21:31:20.86#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.21:31:20.86#ibcon#[25=AT07-04\r\n] 2006.285.21:31:20.86#ibcon#*before write, iclass 18, count 2 2006.285.21:31:20.86#ibcon#enter sib2, iclass 18, count 2 2006.285.21:31:20.86#ibcon#flushed, iclass 18, count 2 2006.285.21:31:20.86#ibcon#about to write, iclass 18, count 2 2006.285.21:31:20.86#ibcon#wrote, iclass 18, count 2 2006.285.21:31:20.86#ibcon#about to read 3, iclass 18, count 2 2006.285.21:31:20.89#ibcon#read 3, iclass 18, count 2 2006.285.21:31:20.89#ibcon#about to read 4, iclass 18, count 2 2006.285.21:31:20.89#ibcon#read 4, iclass 18, count 2 2006.285.21:31:20.89#ibcon#about to read 5, iclass 18, count 2 2006.285.21:31:20.89#ibcon#read 5, iclass 18, count 2 2006.285.21:31:20.89#ibcon#about to read 6, iclass 18, count 2 2006.285.21:31:20.89#ibcon#read 6, iclass 18, count 2 2006.285.21:31:20.89#ibcon#end of sib2, iclass 18, count 2 2006.285.21:31:20.89#ibcon#*after write, iclass 18, count 2 2006.285.21:31:20.89#ibcon#*before return 0, iclass 18, count 2 2006.285.21:31:20.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:31:20.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:31:20.89#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.21:31:20.89#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:20.89#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:31:21.01#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:31:21.01#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:31:21.01#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:31:21.01#ibcon#first serial, iclass 18, count 0 2006.285.21:31:21.01#ibcon#enter sib2, iclass 18, count 0 2006.285.21:31:21.01#ibcon#flushed, iclass 18, count 0 2006.285.21:31:21.01#ibcon#about to write, iclass 18, count 0 2006.285.21:31:21.01#ibcon#wrote, iclass 18, count 0 2006.285.21:31:21.01#ibcon#about to read 3, iclass 18, count 0 2006.285.21:31:21.03#ibcon#read 3, iclass 18, count 0 2006.285.21:31:21.03#ibcon#about to read 4, iclass 18, count 0 2006.285.21:31:21.03#ibcon#read 4, iclass 18, count 0 2006.285.21:31:21.03#ibcon#about to read 5, iclass 18, count 0 2006.285.21:31:21.03#ibcon#read 5, iclass 18, count 0 2006.285.21:31:21.03#ibcon#about to read 6, iclass 18, count 0 2006.285.21:31:21.03#ibcon#read 6, iclass 18, count 0 2006.285.21:31:21.03#ibcon#end of sib2, iclass 18, count 0 2006.285.21:31:21.03#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:31:21.03#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:31:21.03#ibcon#[25=USB\r\n] 2006.285.21:31:21.03#ibcon#*before write, iclass 18, count 0 2006.285.21:31:21.03#ibcon#enter sib2, iclass 18, count 0 2006.285.21:31:21.03#ibcon#flushed, iclass 18, count 0 2006.285.21:31:21.03#ibcon#about to write, iclass 18, count 0 2006.285.21:31:21.03#ibcon#wrote, iclass 18, count 0 2006.285.21:31:21.03#ibcon#about to read 3, iclass 18, count 0 2006.285.21:31:21.06#ibcon#read 3, iclass 18, count 0 2006.285.21:31:21.06#ibcon#about to read 4, iclass 18, count 0 2006.285.21:31:21.06#ibcon#read 4, iclass 18, count 0 2006.285.21:31:21.06#ibcon#about to read 5, iclass 18, count 0 2006.285.21:31:21.06#ibcon#read 5, iclass 18, count 0 2006.285.21:31:21.06#ibcon#about to read 6, iclass 18, count 0 2006.285.21:31:21.06#ibcon#read 6, iclass 18, count 0 2006.285.21:31:21.06#ibcon#end of sib2, iclass 18, count 0 2006.285.21:31:21.06#ibcon#*after write, iclass 18, count 0 2006.285.21:31:21.06#ibcon#*before return 0, iclass 18, count 0 2006.285.21:31:21.06#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:31:21.06#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:31:21.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:31:21.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:31:21.06$vck44/valo=8,884.99 2006.285.21:31:21.06#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.21:31:21.06#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.21:31:21.06#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:21.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:31:21.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:31:21.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:31:21.06#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:31:21.06#ibcon#first serial, iclass 20, count 0 2006.285.21:31:21.06#ibcon#enter sib2, iclass 20, count 0 2006.285.21:31:21.06#ibcon#flushed, iclass 20, count 0 2006.285.21:31:21.06#ibcon#about to write, iclass 20, count 0 2006.285.21:31:21.06#ibcon#wrote, iclass 20, count 0 2006.285.21:31:21.06#ibcon#about to read 3, iclass 20, count 0 2006.285.21:31:21.08#ibcon#read 3, iclass 20, count 0 2006.285.21:31:21.08#ibcon#about to read 4, iclass 20, count 0 2006.285.21:31:21.08#ibcon#read 4, iclass 20, count 0 2006.285.21:31:21.08#ibcon#about to read 5, iclass 20, count 0 2006.285.21:31:21.08#ibcon#read 5, iclass 20, count 0 2006.285.21:31:21.08#ibcon#about to read 6, iclass 20, count 0 2006.285.21:31:21.08#ibcon#read 6, iclass 20, count 0 2006.285.21:31:21.08#ibcon#end of sib2, iclass 20, count 0 2006.285.21:31:21.08#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:31:21.08#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:31:21.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:31:21.08#ibcon#*before write, iclass 20, count 0 2006.285.21:31:21.08#ibcon#enter sib2, iclass 20, count 0 2006.285.21:31:21.08#ibcon#flushed, iclass 20, count 0 2006.285.21:31:21.08#ibcon#about to write, iclass 20, count 0 2006.285.21:31:21.08#ibcon#wrote, iclass 20, count 0 2006.285.21:31:21.08#ibcon#about to read 3, iclass 20, count 0 2006.285.21:31:21.12#ibcon#read 3, iclass 20, count 0 2006.285.21:31:21.12#ibcon#about to read 4, iclass 20, count 0 2006.285.21:31:21.12#ibcon#read 4, iclass 20, count 0 2006.285.21:31:21.12#ibcon#about to read 5, iclass 20, count 0 2006.285.21:31:21.12#ibcon#read 5, iclass 20, count 0 2006.285.21:31:21.12#ibcon#about to read 6, iclass 20, count 0 2006.285.21:31:21.12#ibcon#read 6, iclass 20, count 0 2006.285.21:31:21.12#ibcon#end of sib2, iclass 20, count 0 2006.285.21:31:21.12#ibcon#*after write, iclass 20, count 0 2006.285.21:31:21.12#ibcon#*before return 0, iclass 20, count 0 2006.285.21:31:21.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:31:21.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:31:21.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:31:21.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:31:21.12$vck44/va=8,3 2006.285.21:31:21.12#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.21:31:21.12#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.21:31:21.12#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:21.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:31:21.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:31:21.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:31:21.18#ibcon#enter wrdev, iclass 22, count 2 2006.285.21:31:21.18#ibcon#first serial, iclass 22, count 2 2006.285.21:31:21.18#ibcon#enter sib2, iclass 22, count 2 2006.285.21:31:21.18#ibcon#flushed, iclass 22, count 2 2006.285.21:31:21.18#ibcon#about to write, iclass 22, count 2 2006.285.21:31:21.18#ibcon#wrote, iclass 22, count 2 2006.285.21:31:21.18#ibcon#about to read 3, iclass 22, count 2 2006.285.21:31:21.20#ibcon#read 3, iclass 22, count 2 2006.285.21:31:21.20#ibcon#about to read 4, iclass 22, count 2 2006.285.21:31:21.20#ibcon#read 4, iclass 22, count 2 2006.285.21:31:21.20#ibcon#about to read 5, iclass 22, count 2 2006.285.21:31:21.20#ibcon#read 5, iclass 22, count 2 2006.285.21:31:21.20#ibcon#about to read 6, iclass 22, count 2 2006.285.21:31:21.20#ibcon#read 6, iclass 22, count 2 2006.285.21:31:21.20#ibcon#end of sib2, iclass 22, count 2 2006.285.21:31:21.20#ibcon#*mode == 0, iclass 22, count 2 2006.285.21:31:21.20#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.21:31:21.20#ibcon#[25=AT08-03\r\n] 2006.285.21:31:21.20#ibcon#*before write, iclass 22, count 2 2006.285.21:31:21.20#ibcon#enter sib2, iclass 22, count 2 2006.285.21:31:21.20#ibcon#flushed, iclass 22, count 2 2006.285.21:31:21.20#ibcon#about to write, iclass 22, count 2 2006.285.21:31:21.20#ibcon#wrote, iclass 22, count 2 2006.285.21:31:21.20#ibcon#about to read 3, iclass 22, count 2 2006.285.21:31:21.23#ibcon#read 3, iclass 22, count 2 2006.285.21:31:21.23#ibcon#about to read 4, iclass 22, count 2 2006.285.21:31:21.23#ibcon#read 4, iclass 22, count 2 2006.285.21:31:21.23#ibcon#about to read 5, iclass 22, count 2 2006.285.21:31:21.23#ibcon#read 5, iclass 22, count 2 2006.285.21:31:21.23#ibcon#about to read 6, iclass 22, count 2 2006.285.21:31:21.23#ibcon#read 6, iclass 22, count 2 2006.285.21:31:21.23#ibcon#end of sib2, iclass 22, count 2 2006.285.21:31:21.23#ibcon#*after write, iclass 22, count 2 2006.285.21:31:21.23#ibcon#*before return 0, iclass 22, count 2 2006.285.21:31:21.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:31:21.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:31:21.23#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.21:31:21.23#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:21.23#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:31:21.35#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:31:21.35#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:31:21.35#ibcon#enter wrdev, iclass 22, count 0 2006.285.21:31:21.35#ibcon#first serial, iclass 22, count 0 2006.285.21:31:21.35#ibcon#enter sib2, iclass 22, count 0 2006.285.21:31:21.35#ibcon#flushed, iclass 22, count 0 2006.285.21:31:21.35#ibcon#about to write, iclass 22, count 0 2006.285.21:31:21.35#ibcon#wrote, iclass 22, count 0 2006.285.21:31:21.35#ibcon#about to read 3, iclass 22, count 0 2006.285.21:31:21.37#ibcon#read 3, iclass 22, count 0 2006.285.21:31:21.37#ibcon#about to read 4, iclass 22, count 0 2006.285.21:31:21.37#ibcon#read 4, iclass 22, count 0 2006.285.21:31:21.37#ibcon#about to read 5, iclass 22, count 0 2006.285.21:31:21.37#ibcon#read 5, iclass 22, count 0 2006.285.21:31:21.37#ibcon#about to read 6, iclass 22, count 0 2006.285.21:31:21.37#ibcon#read 6, iclass 22, count 0 2006.285.21:31:21.37#ibcon#end of sib2, iclass 22, count 0 2006.285.21:31:21.37#ibcon#*mode == 0, iclass 22, count 0 2006.285.21:31:21.37#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.21:31:21.37#ibcon#[25=USB\r\n] 2006.285.21:31:21.37#ibcon#*before write, iclass 22, count 0 2006.285.21:31:21.37#ibcon#enter sib2, iclass 22, count 0 2006.285.21:31:21.37#ibcon#flushed, iclass 22, count 0 2006.285.21:31:21.37#ibcon#about to write, iclass 22, count 0 2006.285.21:31:21.37#ibcon#wrote, iclass 22, count 0 2006.285.21:31:21.37#ibcon#about to read 3, iclass 22, count 0 2006.285.21:31:21.40#ibcon#read 3, iclass 22, count 0 2006.285.21:31:21.40#ibcon#about to read 4, iclass 22, count 0 2006.285.21:31:21.40#ibcon#read 4, iclass 22, count 0 2006.285.21:31:21.40#ibcon#about to read 5, iclass 22, count 0 2006.285.21:31:21.40#ibcon#read 5, iclass 22, count 0 2006.285.21:31:21.40#ibcon#about to read 6, iclass 22, count 0 2006.285.21:31:21.40#ibcon#read 6, iclass 22, count 0 2006.285.21:31:21.40#ibcon#end of sib2, iclass 22, count 0 2006.285.21:31:21.40#ibcon#*after write, iclass 22, count 0 2006.285.21:31:21.40#ibcon#*before return 0, iclass 22, count 0 2006.285.21:31:21.40#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:31:21.40#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:31:21.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.21:31:21.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.21:31:21.40$vck44/vblo=1,629.99 2006.285.21:31:21.40#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.21:31:21.40#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.21:31:21.40#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:21.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:31:21.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:31:21.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:31:21.40#ibcon#enter wrdev, iclass 24, count 0 2006.285.21:31:21.40#ibcon#first serial, iclass 24, count 0 2006.285.21:31:21.40#ibcon#enter sib2, iclass 24, count 0 2006.285.21:31:21.40#ibcon#flushed, iclass 24, count 0 2006.285.21:31:21.40#ibcon#about to write, iclass 24, count 0 2006.285.21:31:21.40#ibcon#wrote, iclass 24, count 0 2006.285.21:31:21.40#ibcon#about to read 3, iclass 24, count 0 2006.285.21:31:21.42#ibcon#read 3, iclass 24, count 0 2006.285.21:31:21.42#ibcon#about to read 4, iclass 24, count 0 2006.285.21:31:21.42#ibcon#read 4, iclass 24, count 0 2006.285.21:31:21.42#ibcon#about to read 5, iclass 24, count 0 2006.285.21:31:21.42#ibcon#read 5, iclass 24, count 0 2006.285.21:31:21.42#ibcon#about to read 6, iclass 24, count 0 2006.285.21:31:21.42#ibcon#read 6, iclass 24, count 0 2006.285.21:31:21.42#ibcon#end of sib2, iclass 24, count 0 2006.285.21:31:21.42#ibcon#*mode == 0, iclass 24, count 0 2006.285.21:31:21.42#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.21:31:21.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:31:21.42#ibcon#*before write, iclass 24, count 0 2006.285.21:31:21.42#ibcon#enter sib2, iclass 24, count 0 2006.285.21:31:21.42#ibcon#flushed, iclass 24, count 0 2006.285.21:31:21.42#ibcon#about to write, iclass 24, count 0 2006.285.21:31:21.42#ibcon#wrote, iclass 24, count 0 2006.285.21:31:21.42#ibcon#about to read 3, iclass 24, count 0 2006.285.21:31:21.46#ibcon#read 3, iclass 24, count 0 2006.285.21:31:21.46#ibcon#about to read 4, iclass 24, count 0 2006.285.21:31:21.46#ibcon#read 4, iclass 24, count 0 2006.285.21:31:21.46#ibcon#about to read 5, iclass 24, count 0 2006.285.21:31:21.46#ibcon#read 5, iclass 24, count 0 2006.285.21:31:21.46#ibcon#about to read 6, iclass 24, count 0 2006.285.21:31:21.46#ibcon#read 6, iclass 24, count 0 2006.285.21:31:21.46#ibcon#end of sib2, iclass 24, count 0 2006.285.21:31:21.46#ibcon#*after write, iclass 24, count 0 2006.285.21:31:21.46#ibcon#*before return 0, iclass 24, count 0 2006.285.21:31:21.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:31:21.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:31:21.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.21:31:21.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.21:31:21.46$vck44/vb=1,4 2006.285.21:31:21.60#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.21:31:21.60#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.21:31:21.60#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:21.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:31:21.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:31:21.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:31:21.60#ibcon#enter wrdev, iclass 26, count 2 2006.285.21:31:21.60#ibcon#first serial, iclass 26, count 2 2006.285.21:31:21.60#ibcon#enter sib2, iclass 26, count 2 2006.285.21:31:21.60#ibcon#flushed, iclass 26, count 2 2006.285.21:31:21.60#ibcon#about to write, iclass 26, count 2 2006.285.21:31:21.60#ibcon#wrote, iclass 26, count 2 2006.285.21:31:21.60#ibcon#about to read 3, iclass 26, count 2 2006.285.21:31:21.61#ibcon#read 3, iclass 26, count 2 2006.285.21:31:21.61#ibcon#about to read 4, iclass 26, count 2 2006.285.21:31:21.61#ibcon#read 4, iclass 26, count 2 2006.285.21:31:21.61#ibcon#about to read 5, iclass 26, count 2 2006.285.21:31:21.61#ibcon#read 5, iclass 26, count 2 2006.285.21:31:21.61#ibcon#about to read 6, iclass 26, count 2 2006.285.21:31:21.61#ibcon#read 6, iclass 26, count 2 2006.285.21:31:21.61#ibcon#end of sib2, iclass 26, count 2 2006.285.21:31:21.61#ibcon#*mode == 0, iclass 26, count 2 2006.285.21:31:21.61#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.21:31:21.61#ibcon#[27=AT01-04\r\n] 2006.285.21:31:21.61#ibcon#*before write, iclass 26, count 2 2006.285.21:31:21.61#ibcon#enter sib2, iclass 26, count 2 2006.285.21:31:21.61#ibcon#flushed, iclass 26, count 2 2006.285.21:31:21.61#ibcon#about to write, iclass 26, count 2 2006.285.21:31:21.61#ibcon#wrote, iclass 26, count 2 2006.285.21:31:21.61#ibcon#about to read 3, iclass 26, count 2 2006.285.21:31:21.64#ibcon#read 3, iclass 26, count 2 2006.285.21:31:21.64#ibcon#about to read 4, iclass 26, count 2 2006.285.21:31:21.64#ibcon#read 4, iclass 26, count 2 2006.285.21:31:21.64#ibcon#about to read 5, iclass 26, count 2 2006.285.21:31:21.64#ibcon#read 5, iclass 26, count 2 2006.285.21:31:21.64#ibcon#about to read 6, iclass 26, count 2 2006.285.21:31:21.64#ibcon#read 6, iclass 26, count 2 2006.285.21:31:21.64#ibcon#end of sib2, iclass 26, count 2 2006.285.21:31:21.64#ibcon#*after write, iclass 26, count 2 2006.285.21:31:21.64#ibcon#*before return 0, iclass 26, count 2 2006.285.21:31:21.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:31:21.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:31:21.64#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.21:31:21.64#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:21.64#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:31:21.76#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:31:21.76#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:31:21.76#ibcon#enter wrdev, iclass 26, count 0 2006.285.21:31:21.76#ibcon#first serial, iclass 26, count 0 2006.285.21:31:21.76#ibcon#enter sib2, iclass 26, count 0 2006.285.21:31:21.76#ibcon#flushed, iclass 26, count 0 2006.285.21:31:21.76#ibcon#about to write, iclass 26, count 0 2006.285.21:31:21.76#ibcon#wrote, iclass 26, count 0 2006.285.21:31:21.76#ibcon#about to read 3, iclass 26, count 0 2006.285.21:31:21.78#ibcon#read 3, iclass 26, count 0 2006.285.21:31:21.78#ibcon#about to read 4, iclass 26, count 0 2006.285.21:31:21.78#ibcon#read 4, iclass 26, count 0 2006.285.21:31:21.78#ibcon#about to read 5, iclass 26, count 0 2006.285.21:31:21.78#ibcon#read 5, iclass 26, count 0 2006.285.21:31:21.78#ibcon#about to read 6, iclass 26, count 0 2006.285.21:31:21.78#ibcon#read 6, iclass 26, count 0 2006.285.21:31:21.78#ibcon#end of sib2, iclass 26, count 0 2006.285.21:31:21.78#ibcon#*mode == 0, iclass 26, count 0 2006.285.21:31:21.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.21:31:21.78#ibcon#[27=USB\r\n] 2006.285.21:31:21.78#ibcon#*before write, iclass 26, count 0 2006.285.21:31:21.78#ibcon#enter sib2, iclass 26, count 0 2006.285.21:31:21.78#ibcon#flushed, iclass 26, count 0 2006.285.21:31:21.78#ibcon#about to write, iclass 26, count 0 2006.285.21:31:21.78#ibcon#wrote, iclass 26, count 0 2006.285.21:31:21.78#ibcon#about to read 3, iclass 26, count 0 2006.285.21:31:21.81#ibcon#read 3, iclass 26, count 0 2006.285.21:31:21.81#ibcon#about to read 4, iclass 26, count 0 2006.285.21:31:21.81#ibcon#read 4, iclass 26, count 0 2006.285.21:31:21.81#ibcon#about to read 5, iclass 26, count 0 2006.285.21:31:21.81#ibcon#read 5, iclass 26, count 0 2006.285.21:31:21.81#ibcon#about to read 6, iclass 26, count 0 2006.285.21:31:21.81#ibcon#read 6, iclass 26, count 0 2006.285.21:31:21.81#ibcon#end of sib2, iclass 26, count 0 2006.285.21:31:21.81#ibcon#*after write, iclass 26, count 0 2006.285.21:31:21.81#ibcon#*before return 0, iclass 26, count 0 2006.285.21:31:21.81#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:31:21.81#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:31:21.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.21:31:21.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.21:31:21.81$vck44/vblo=2,634.99 2006.285.21:31:21.81#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.21:31:21.81#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.21:31:21.81#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:21.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:31:21.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:31:21.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:31:21.81#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:31:21.81#ibcon#first serial, iclass 28, count 0 2006.285.21:31:21.81#ibcon#enter sib2, iclass 28, count 0 2006.285.21:31:21.81#ibcon#flushed, iclass 28, count 0 2006.285.21:31:21.81#ibcon#about to write, iclass 28, count 0 2006.285.21:31:21.81#ibcon#wrote, iclass 28, count 0 2006.285.21:31:21.81#ibcon#about to read 3, iclass 28, count 0 2006.285.21:31:21.83#ibcon#read 3, iclass 28, count 0 2006.285.21:31:21.83#ibcon#about to read 4, iclass 28, count 0 2006.285.21:31:21.83#ibcon#read 4, iclass 28, count 0 2006.285.21:31:21.83#ibcon#about to read 5, iclass 28, count 0 2006.285.21:31:21.83#ibcon#read 5, iclass 28, count 0 2006.285.21:31:21.83#ibcon#about to read 6, iclass 28, count 0 2006.285.21:31:21.83#ibcon#read 6, iclass 28, count 0 2006.285.21:31:21.83#ibcon#end of sib2, iclass 28, count 0 2006.285.21:31:21.83#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:31:21.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:31:21.83#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:31:21.83#ibcon#*before write, iclass 28, count 0 2006.285.21:31:21.83#ibcon#enter sib2, iclass 28, count 0 2006.285.21:31:21.83#ibcon#flushed, iclass 28, count 0 2006.285.21:31:21.83#ibcon#about to write, iclass 28, count 0 2006.285.21:31:21.83#ibcon#wrote, iclass 28, count 0 2006.285.21:31:21.83#ibcon#about to read 3, iclass 28, count 0 2006.285.21:31:21.87#ibcon#read 3, iclass 28, count 0 2006.285.21:31:21.87#ibcon#about to read 4, iclass 28, count 0 2006.285.21:31:21.87#ibcon#read 4, iclass 28, count 0 2006.285.21:31:21.87#ibcon#about to read 5, iclass 28, count 0 2006.285.21:31:21.87#ibcon#read 5, iclass 28, count 0 2006.285.21:31:21.87#ibcon#about to read 6, iclass 28, count 0 2006.285.21:31:21.87#ibcon#read 6, iclass 28, count 0 2006.285.21:31:21.87#ibcon#end of sib2, iclass 28, count 0 2006.285.21:31:21.87#ibcon#*after write, iclass 28, count 0 2006.285.21:31:21.87#ibcon#*before return 0, iclass 28, count 0 2006.285.21:31:21.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:31:21.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:31:21.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:31:21.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:31:21.87$vck44/vb=2,5 2006.285.21:31:21.87#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.21:31:21.87#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.21:31:21.87#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:21.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:31:21.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:31:21.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:31:21.93#ibcon#enter wrdev, iclass 30, count 2 2006.285.21:31:21.93#ibcon#first serial, iclass 30, count 2 2006.285.21:31:21.93#ibcon#enter sib2, iclass 30, count 2 2006.285.21:31:21.93#ibcon#flushed, iclass 30, count 2 2006.285.21:31:21.93#ibcon#about to write, iclass 30, count 2 2006.285.21:31:21.93#ibcon#wrote, iclass 30, count 2 2006.285.21:31:21.93#ibcon#about to read 3, iclass 30, count 2 2006.285.21:31:21.95#ibcon#read 3, iclass 30, count 2 2006.285.21:31:21.95#ibcon#about to read 4, iclass 30, count 2 2006.285.21:31:21.95#ibcon#read 4, iclass 30, count 2 2006.285.21:31:21.95#ibcon#about to read 5, iclass 30, count 2 2006.285.21:31:21.95#ibcon#read 5, iclass 30, count 2 2006.285.21:31:21.95#ibcon#about to read 6, iclass 30, count 2 2006.285.21:31:21.95#ibcon#read 6, iclass 30, count 2 2006.285.21:31:21.95#ibcon#end of sib2, iclass 30, count 2 2006.285.21:31:21.95#ibcon#*mode == 0, iclass 30, count 2 2006.285.21:31:21.95#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.21:31:21.95#ibcon#[27=AT02-05\r\n] 2006.285.21:31:21.95#ibcon#*before write, iclass 30, count 2 2006.285.21:31:21.95#ibcon#enter sib2, iclass 30, count 2 2006.285.21:31:21.95#ibcon#flushed, iclass 30, count 2 2006.285.21:31:21.95#ibcon#about to write, iclass 30, count 2 2006.285.21:31:21.95#ibcon#wrote, iclass 30, count 2 2006.285.21:31:21.95#ibcon#about to read 3, iclass 30, count 2 2006.285.21:31:21.98#ibcon#read 3, iclass 30, count 2 2006.285.21:31:21.98#ibcon#about to read 4, iclass 30, count 2 2006.285.21:31:21.98#ibcon#read 4, iclass 30, count 2 2006.285.21:31:21.98#ibcon#about to read 5, iclass 30, count 2 2006.285.21:31:21.98#ibcon#read 5, iclass 30, count 2 2006.285.21:31:21.98#ibcon#about to read 6, iclass 30, count 2 2006.285.21:31:21.98#ibcon#read 6, iclass 30, count 2 2006.285.21:31:21.98#ibcon#end of sib2, iclass 30, count 2 2006.285.21:31:21.98#ibcon#*after write, iclass 30, count 2 2006.285.21:31:21.98#ibcon#*before return 0, iclass 30, count 2 2006.285.21:31:21.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:31:21.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:31:21.98#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.21:31:21.98#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:21.98#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:31:22.10#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:31:22.10#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:31:22.10#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:31:22.10#ibcon#first serial, iclass 30, count 0 2006.285.21:31:22.10#ibcon#enter sib2, iclass 30, count 0 2006.285.21:31:22.10#ibcon#flushed, iclass 30, count 0 2006.285.21:31:22.10#ibcon#about to write, iclass 30, count 0 2006.285.21:31:22.10#ibcon#wrote, iclass 30, count 0 2006.285.21:31:22.10#ibcon#about to read 3, iclass 30, count 0 2006.285.21:31:22.12#ibcon#read 3, iclass 30, count 0 2006.285.21:31:22.12#ibcon#about to read 4, iclass 30, count 0 2006.285.21:31:22.12#ibcon#read 4, iclass 30, count 0 2006.285.21:31:22.12#ibcon#about to read 5, iclass 30, count 0 2006.285.21:31:22.12#ibcon#read 5, iclass 30, count 0 2006.285.21:31:22.12#ibcon#about to read 6, iclass 30, count 0 2006.285.21:31:22.12#ibcon#read 6, iclass 30, count 0 2006.285.21:31:22.12#ibcon#end of sib2, iclass 30, count 0 2006.285.21:31:22.12#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:31:22.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:31:22.12#ibcon#[27=USB\r\n] 2006.285.21:31:22.12#ibcon#*before write, iclass 30, count 0 2006.285.21:31:22.12#ibcon#enter sib2, iclass 30, count 0 2006.285.21:31:22.12#ibcon#flushed, iclass 30, count 0 2006.285.21:31:22.12#ibcon#about to write, iclass 30, count 0 2006.285.21:31:22.12#ibcon#wrote, iclass 30, count 0 2006.285.21:31:22.12#ibcon#about to read 3, iclass 30, count 0 2006.285.21:31:22.15#ibcon#read 3, iclass 30, count 0 2006.285.21:31:22.15#ibcon#about to read 4, iclass 30, count 0 2006.285.21:31:22.15#ibcon#read 4, iclass 30, count 0 2006.285.21:31:22.15#ibcon#about to read 5, iclass 30, count 0 2006.285.21:31:22.15#ibcon#read 5, iclass 30, count 0 2006.285.21:31:22.15#ibcon#about to read 6, iclass 30, count 0 2006.285.21:31:22.15#ibcon#read 6, iclass 30, count 0 2006.285.21:31:22.15#ibcon#end of sib2, iclass 30, count 0 2006.285.21:31:22.15#ibcon#*after write, iclass 30, count 0 2006.285.21:31:22.15#ibcon#*before return 0, iclass 30, count 0 2006.285.21:31:22.15#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:31:22.15#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:31:22.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:31:22.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:31:22.15$vck44/vblo=3,649.99 2006.285.21:31:22.15#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.21:31:22.15#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.21:31:22.15#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:22.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:31:22.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:31:22.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:31:22.15#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:31:22.15#ibcon#first serial, iclass 32, count 0 2006.285.21:31:22.15#ibcon#enter sib2, iclass 32, count 0 2006.285.21:31:22.15#ibcon#flushed, iclass 32, count 0 2006.285.21:31:22.15#ibcon#about to write, iclass 32, count 0 2006.285.21:31:22.15#ibcon#wrote, iclass 32, count 0 2006.285.21:31:22.15#ibcon#about to read 3, iclass 32, count 0 2006.285.21:31:22.17#ibcon#read 3, iclass 32, count 0 2006.285.21:31:22.17#ibcon#about to read 4, iclass 32, count 0 2006.285.21:31:22.17#ibcon#read 4, iclass 32, count 0 2006.285.21:31:22.17#ibcon#about to read 5, iclass 32, count 0 2006.285.21:31:22.17#ibcon#read 5, iclass 32, count 0 2006.285.21:31:22.17#ibcon#about to read 6, iclass 32, count 0 2006.285.21:31:22.17#ibcon#read 6, iclass 32, count 0 2006.285.21:31:22.17#ibcon#end of sib2, iclass 32, count 0 2006.285.21:31:22.17#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:31:22.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:31:22.17#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:31:22.17#ibcon#*before write, iclass 32, count 0 2006.285.21:31:22.17#ibcon#enter sib2, iclass 32, count 0 2006.285.21:31:22.17#ibcon#flushed, iclass 32, count 0 2006.285.21:31:22.17#ibcon#about to write, iclass 32, count 0 2006.285.21:31:22.17#ibcon#wrote, iclass 32, count 0 2006.285.21:31:22.17#ibcon#about to read 3, iclass 32, count 0 2006.285.21:31:22.21#ibcon#read 3, iclass 32, count 0 2006.285.21:31:22.21#ibcon#about to read 4, iclass 32, count 0 2006.285.21:31:22.21#ibcon#read 4, iclass 32, count 0 2006.285.21:31:22.21#ibcon#about to read 5, iclass 32, count 0 2006.285.21:31:22.21#ibcon#read 5, iclass 32, count 0 2006.285.21:31:22.21#ibcon#about to read 6, iclass 32, count 0 2006.285.21:31:22.21#ibcon#read 6, iclass 32, count 0 2006.285.21:31:22.21#ibcon#end of sib2, iclass 32, count 0 2006.285.21:31:22.21#ibcon#*after write, iclass 32, count 0 2006.285.21:31:22.21#ibcon#*before return 0, iclass 32, count 0 2006.285.21:31:22.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:31:22.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:31:22.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:31:22.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:31:22.21$vck44/vb=3,4 2006.285.21:31:22.21#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.21:31:22.21#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.21:31:22.21#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:22.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:31:22.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:31:22.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:31:22.27#ibcon#enter wrdev, iclass 34, count 2 2006.285.21:31:22.27#ibcon#first serial, iclass 34, count 2 2006.285.21:31:22.27#ibcon#enter sib2, iclass 34, count 2 2006.285.21:31:22.27#ibcon#flushed, iclass 34, count 2 2006.285.21:31:22.27#ibcon#about to write, iclass 34, count 2 2006.285.21:31:22.27#ibcon#wrote, iclass 34, count 2 2006.285.21:31:22.27#ibcon#about to read 3, iclass 34, count 2 2006.285.21:31:22.29#ibcon#read 3, iclass 34, count 2 2006.285.21:31:22.29#ibcon#about to read 4, iclass 34, count 2 2006.285.21:31:22.29#ibcon#read 4, iclass 34, count 2 2006.285.21:31:22.29#ibcon#about to read 5, iclass 34, count 2 2006.285.21:31:22.29#ibcon#read 5, iclass 34, count 2 2006.285.21:31:22.29#ibcon#about to read 6, iclass 34, count 2 2006.285.21:31:22.29#ibcon#read 6, iclass 34, count 2 2006.285.21:31:22.29#ibcon#end of sib2, iclass 34, count 2 2006.285.21:31:22.29#ibcon#*mode == 0, iclass 34, count 2 2006.285.21:31:22.29#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.21:31:22.29#ibcon#[27=AT03-04\r\n] 2006.285.21:31:22.29#ibcon#*before write, iclass 34, count 2 2006.285.21:31:22.29#ibcon#enter sib2, iclass 34, count 2 2006.285.21:31:22.29#ibcon#flushed, iclass 34, count 2 2006.285.21:31:22.29#ibcon#about to write, iclass 34, count 2 2006.285.21:31:22.29#ibcon#wrote, iclass 34, count 2 2006.285.21:31:22.29#ibcon#about to read 3, iclass 34, count 2 2006.285.21:31:22.32#ibcon#read 3, iclass 34, count 2 2006.285.21:31:22.32#ibcon#about to read 4, iclass 34, count 2 2006.285.21:31:22.32#ibcon#read 4, iclass 34, count 2 2006.285.21:31:22.32#ibcon#about to read 5, iclass 34, count 2 2006.285.21:31:22.32#ibcon#read 5, iclass 34, count 2 2006.285.21:31:22.32#ibcon#about to read 6, iclass 34, count 2 2006.285.21:31:22.32#ibcon#read 6, iclass 34, count 2 2006.285.21:31:22.32#ibcon#end of sib2, iclass 34, count 2 2006.285.21:31:22.32#ibcon#*after write, iclass 34, count 2 2006.285.21:31:22.32#ibcon#*before return 0, iclass 34, count 2 2006.285.21:31:22.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:31:22.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:31:22.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.21:31:22.32#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:22.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:31:22.44#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:31:22.44#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:31:22.44#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:31:22.44#ibcon#first serial, iclass 34, count 0 2006.285.21:31:22.44#ibcon#enter sib2, iclass 34, count 0 2006.285.21:31:22.44#ibcon#flushed, iclass 34, count 0 2006.285.21:31:22.44#ibcon#about to write, iclass 34, count 0 2006.285.21:31:22.44#ibcon#wrote, iclass 34, count 0 2006.285.21:31:22.44#ibcon#about to read 3, iclass 34, count 0 2006.285.21:31:22.46#ibcon#read 3, iclass 34, count 0 2006.285.21:31:22.46#ibcon#about to read 4, iclass 34, count 0 2006.285.21:31:22.46#ibcon#read 4, iclass 34, count 0 2006.285.21:31:22.46#ibcon#about to read 5, iclass 34, count 0 2006.285.21:31:22.46#ibcon#read 5, iclass 34, count 0 2006.285.21:31:22.46#ibcon#about to read 6, iclass 34, count 0 2006.285.21:31:22.46#ibcon#read 6, iclass 34, count 0 2006.285.21:31:22.46#ibcon#end of sib2, iclass 34, count 0 2006.285.21:31:22.46#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:31:22.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:31:22.46#ibcon#[27=USB\r\n] 2006.285.21:31:22.46#ibcon#*before write, iclass 34, count 0 2006.285.21:31:22.46#ibcon#enter sib2, iclass 34, count 0 2006.285.21:31:22.46#ibcon#flushed, iclass 34, count 0 2006.285.21:31:22.46#ibcon#about to write, iclass 34, count 0 2006.285.21:31:22.46#ibcon#wrote, iclass 34, count 0 2006.285.21:31:22.46#ibcon#about to read 3, iclass 34, count 0 2006.285.21:31:22.49#ibcon#read 3, iclass 34, count 0 2006.285.21:31:22.49#ibcon#about to read 4, iclass 34, count 0 2006.285.21:31:22.49#ibcon#read 4, iclass 34, count 0 2006.285.21:31:22.49#ibcon#about to read 5, iclass 34, count 0 2006.285.21:31:22.49#ibcon#read 5, iclass 34, count 0 2006.285.21:31:22.49#ibcon#about to read 6, iclass 34, count 0 2006.285.21:31:22.49#ibcon#read 6, iclass 34, count 0 2006.285.21:31:22.49#ibcon#end of sib2, iclass 34, count 0 2006.285.21:31:22.49#ibcon#*after write, iclass 34, count 0 2006.285.21:31:22.49#ibcon#*before return 0, iclass 34, count 0 2006.285.21:31:22.49#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:31:22.49#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:31:22.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:31:22.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:31:22.49$vck44/vblo=4,679.99 2006.285.21:31:22.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.21:31:22.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.21:31:22.49#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:22.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:31:22.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:31:22.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:31:22.49#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:31:22.49#ibcon#first serial, iclass 36, count 0 2006.285.21:31:22.49#ibcon#enter sib2, iclass 36, count 0 2006.285.21:31:22.49#ibcon#flushed, iclass 36, count 0 2006.285.21:31:22.49#ibcon#about to write, iclass 36, count 0 2006.285.21:31:22.49#ibcon#wrote, iclass 36, count 0 2006.285.21:31:22.49#ibcon#about to read 3, iclass 36, count 0 2006.285.21:31:22.51#ibcon#read 3, iclass 36, count 0 2006.285.21:31:22.60#ibcon#about to read 4, iclass 36, count 0 2006.285.21:31:22.60#ibcon#read 4, iclass 36, count 0 2006.285.21:31:22.60#ibcon#about to read 5, iclass 36, count 0 2006.285.21:31:22.60#ibcon#read 5, iclass 36, count 0 2006.285.21:31:22.60#ibcon#about to read 6, iclass 36, count 0 2006.285.21:31:22.60#ibcon#read 6, iclass 36, count 0 2006.285.21:31:22.60#ibcon#end of sib2, iclass 36, count 0 2006.285.21:31:22.60#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:31:22.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:31:22.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:31:22.60#ibcon#*before write, iclass 36, count 0 2006.285.21:31:22.60#ibcon#enter sib2, iclass 36, count 0 2006.285.21:31:22.60#ibcon#flushed, iclass 36, count 0 2006.285.21:31:22.60#ibcon#about to write, iclass 36, count 0 2006.285.21:31:22.60#ibcon#wrote, iclass 36, count 0 2006.285.21:31:22.60#ibcon#about to read 3, iclass 36, count 0 2006.285.21:31:22.64#ibcon#read 3, iclass 36, count 0 2006.285.21:31:22.64#ibcon#about to read 4, iclass 36, count 0 2006.285.21:31:22.64#ibcon#read 4, iclass 36, count 0 2006.285.21:31:22.64#ibcon#about to read 5, iclass 36, count 0 2006.285.21:31:22.64#ibcon#read 5, iclass 36, count 0 2006.285.21:31:22.64#ibcon#about to read 6, iclass 36, count 0 2006.285.21:31:22.64#ibcon#read 6, iclass 36, count 0 2006.285.21:31:22.64#ibcon#end of sib2, iclass 36, count 0 2006.285.21:31:22.64#ibcon#*after write, iclass 36, count 0 2006.285.21:31:22.64#ibcon#*before return 0, iclass 36, count 0 2006.285.21:31:22.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:31:22.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:31:22.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:31:22.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:31:22.64$vck44/vb=4,5 2006.285.21:31:22.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.21:31:22.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.21:31:22.64#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:22.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:31:22.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:31:22.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:31:22.64#ibcon#enter wrdev, iclass 38, count 2 2006.285.21:31:22.64#ibcon#first serial, iclass 38, count 2 2006.285.21:31:22.64#ibcon#enter sib2, iclass 38, count 2 2006.285.21:31:22.64#ibcon#flushed, iclass 38, count 2 2006.285.21:31:22.64#ibcon#about to write, iclass 38, count 2 2006.285.21:31:22.64#ibcon#wrote, iclass 38, count 2 2006.285.21:31:22.64#ibcon#about to read 3, iclass 38, count 2 2006.285.21:31:22.66#ibcon#read 3, iclass 38, count 2 2006.285.21:31:22.66#ibcon#about to read 4, iclass 38, count 2 2006.285.21:31:22.66#ibcon#read 4, iclass 38, count 2 2006.285.21:31:22.66#ibcon#about to read 5, iclass 38, count 2 2006.285.21:31:22.66#ibcon#read 5, iclass 38, count 2 2006.285.21:31:22.66#ibcon#about to read 6, iclass 38, count 2 2006.285.21:31:22.66#ibcon#read 6, iclass 38, count 2 2006.285.21:31:22.66#ibcon#end of sib2, iclass 38, count 2 2006.285.21:31:22.66#ibcon#*mode == 0, iclass 38, count 2 2006.285.21:31:22.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.21:31:22.66#ibcon#[27=AT04-05\r\n] 2006.285.21:31:22.66#ibcon#*before write, iclass 38, count 2 2006.285.21:31:22.66#ibcon#enter sib2, iclass 38, count 2 2006.285.21:31:22.66#ibcon#flushed, iclass 38, count 2 2006.285.21:31:22.66#ibcon#about to write, iclass 38, count 2 2006.285.21:31:22.66#ibcon#wrote, iclass 38, count 2 2006.285.21:31:22.66#ibcon#about to read 3, iclass 38, count 2 2006.285.21:31:22.69#ibcon#read 3, iclass 38, count 2 2006.285.21:31:22.69#ibcon#about to read 4, iclass 38, count 2 2006.285.21:31:22.69#ibcon#read 4, iclass 38, count 2 2006.285.21:31:22.69#ibcon#about to read 5, iclass 38, count 2 2006.285.21:31:22.69#ibcon#read 5, iclass 38, count 2 2006.285.21:31:22.69#ibcon#about to read 6, iclass 38, count 2 2006.285.21:31:22.69#ibcon#read 6, iclass 38, count 2 2006.285.21:31:22.69#ibcon#end of sib2, iclass 38, count 2 2006.285.21:31:22.69#ibcon#*after write, iclass 38, count 2 2006.285.21:31:22.69#ibcon#*before return 0, iclass 38, count 2 2006.285.21:31:22.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:31:22.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:31:22.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.21:31:22.69#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:22.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:31:22.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:31:22.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:31:22.81#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:31:22.81#ibcon#first serial, iclass 38, count 0 2006.285.21:31:22.81#ibcon#enter sib2, iclass 38, count 0 2006.285.21:31:22.81#ibcon#flushed, iclass 38, count 0 2006.285.21:31:22.81#ibcon#about to write, iclass 38, count 0 2006.285.21:31:22.81#ibcon#wrote, iclass 38, count 0 2006.285.21:31:22.81#ibcon#about to read 3, iclass 38, count 0 2006.285.21:31:22.83#ibcon#read 3, iclass 38, count 0 2006.285.21:31:22.83#ibcon#about to read 4, iclass 38, count 0 2006.285.21:31:22.83#ibcon#read 4, iclass 38, count 0 2006.285.21:31:22.83#ibcon#about to read 5, iclass 38, count 0 2006.285.21:31:22.83#ibcon#read 5, iclass 38, count 0 2006.285.21:31:22.83#ibcon#about to read 6, iclass 38, count 0 2006.285.21:31:22.83#ibcon#read 6, iclass 38, count 0 2006.285.21:31:22.83#ibcon#end of sib2, iclass 38, count 0 2006.285.21:31:22.83#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:31:22.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:31:22.83#ibcon#[27=USB\r\n] 2006.285.21:31:22.83#ibcon#*before write, iclass 38, count 0 2006.285.21:31:22.83#ibcon#enter sib2, iclass 38, count 0 2006.285.21:31:22.83#ibcon#flushed, iclass 38, count 0 2006.285.21:31:22.83#ibcon#about to write, iclass 38, count 0 2006.285.21:31:22.83#ibcon#wrote, iclass 38, count 0 2006.285.21:31:22.83#ibcon#about to read 3, iclass 38, count 0 2006.285.21:31:22.86#ibcon#read 3, iclass 38, count 0 2006.285.21:31:22.86#ibcon#about to read 4, iclass 38, count 0 2006.285.21:31:22.86#ibcon#read 4, iclass 38, count 0 2006.285.21:31:22.86#ibcon#about to read 5, iclass 38, count 0 2006.285.21:31:22.86#ibcon#read 5, iclass 38, count 0 2006.285.21:31:22.86#ibcon#about to read 6, iclass 38, count 0 2006.285.21:31:22.86#ibcon#read 6, iclass 38, count 0 2006.285.21:31:22.86#ibcon#end of sib2, iclass 38, count 0 2006.285.21:31:22.86#ibcon#*after write, iclass 38, count 0 2006.285.21:31:22.86#ibcon#*before return 0, iclass 38, count 0 2006.285.21:31:22.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:31:22.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:31:22.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:31:22.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:31:22.86$vck44/vblo=5,709.99 2006.285.21:31:22.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.21:31:22.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.21:31:22.86#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:22.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:31:22.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:31:22.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:31:22.86#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:31:22.86#ibcon#first serial, iclass 40, count 0 2006.285.21:31:22.86#ibcon#enter sib2, iclass 40, count 0 2006.285.21:31:22.86#ibcon#flushed, iclass 40, count 0 2006.285.21:31:22.86#ibcon#about to write, iclass 40, count 0 2006.285.21:31:22.86#ibcon#wrote, iclass 40, count 0 2006.285.21:31:22.86#ibcon#about to read 3, iclass 40, count 0 2006.285.21:31:22.88#ibcon#read 3, iclass 40, count 0 2006.285.21:31:22.88#ibcon#about to read 4, iclass 40, count 0 2006.285.21:31:22.88#ibcon#read 4, iclass 40, count 0 2006.285.21:31:22.88#ibcon#about to read 5, iclass 40, count 0 2006.285.21:31:22.88#ibcon#read 5, iclass 40, count 0 2006.285.21:31:22.88#ibcon#about to read 6, iclass 40, count 0 2006.285.21:31:22.88#ibcon#read 6, iclass 40, count 0 2006.285.21:31:22.88#ibcon#end of sib2, iclass 40, count 0 2006.285.21:31:22.88#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:31:22.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:31:22.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:31:22.88#ibcon#*before write, iclass 40, count 0 2006.285.21:31:22.88#ibcon#enter sib2, iclass 40, count 0 2006.285.21:31:22.88#ibcon#flushed, iclass 40, count 0 2006.285.21:31:22.88#ibcon#about to write, iclass 40, count 0 2006.285.21:31:22.88#ibcon#wrote, iclass 40, count 0 2006.285.21:31:22.88#ibcon#about to read 3, iclass 40, count 0 2006.285.21:31:22.92#ibcon#read 3, iclass 40, count 0 2006.285.21:31:22.92#ibcon#about to read 4, iclass 40, count 0 2006.285.21:31:22.92#ibcon#read 4, iclass 40, count 0 2006.285.21:31:22.92#ibcon#about to read 5, iclass 40, count 0 2006.285.21:31:22.92#ibcon#read 5, iclass 40, count 0 2006.285.21:31:22.92#ibcon#about to read 6, iclass 40, count 0 2006.285.21:31:22.92#ibcon#read 6, iclass 40, count 0 2006.285.21:31:22.92#ibcon#end of sib2, iclass 40, count 0 2006.285.21:31:22.92#ibcon#*after write, iclass 40, count 0 2006.285.21:31:22.92#ibcon#*before return 0, iclass 40, count 0 2006.285.21:31:22.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:31:22.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:31:22.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:31:22.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:31:22.92$vck44/vb=5,4 2006.285.21:31:22.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.21:31:22.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.21:31:22.92#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:22.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:31:22.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:31:22.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:31:22.98#ibcon#enter wrdev, iclass 4, count 2 2006.285.21:31:22.98#ibcon#first serial, iclass 4, count 2 2006.285.21:31:22.98#ibcon#enter sib2, iclass 4, count 2 2006.285.21:31:22.98#ibcon#flushed, iclass 4, count 2 2006.285.21:31:22.98#ibcon#about to write, iclass 4, count 2 2006.285.21:31:22.98#ibcon#wrote, iclass 4, count 2 2006.285.21:31:22.98#ibcon#about to read 3, iclass 4, count 2 2006.285.21:31:23.00#ibcon#read 3, iclass 4, count 2 2006.285.21:31:23.00#ibcon#about to read 4, iclass 4, count 2 2006.285.21:31:23.00#ibcon#read 4, iclass 4, count 2 2006.285.21:31:23.00#ibcon#about to read 5, iclass 4, count 2 2006.285.21:31:23.00#ibcon#read 5, iclass 4, count 2 2006.285.21:31:23.00#ibcon#about to read 6, iclass 4, count 2 2006.285.21:31:23.00#ibcon#read 6, iclass 4, count 2 2006.285.21:31:23.00#ibcon#end of sib2, iclass 4, count 2 2006.285.21:31:23.00#ibcon#*mode == 0, iclass 4, count 2 2006.285.21:31:23.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.21:31:23.00#ibcon#[27=AT05-04\r\n] 2006.285.21:31:23.00#ibcon#*before write, iclass 4, count 2 2006.285.21:31:23.00#ibcon#enter sib2, iclass 4, count 2 2006.285.21:31:23.00#ibcon#flushed, iclass 4, count 2 2006.285.21:31:23.00#ibcon#about to write, iclass 4, count 2 2006.285.21:31:23.00#ibcon#wrote, iclass 4, count 2 2006.285.21:31:23.00#ibcon#about to read 3, iclass 4, count 2 2006.285.21:31:23.03#ibcon#read 3, iclass 4, count 2 2006.285.21:31:23.03#ibcon#about to read 4, iclass 4, count 2 2006.285.21:31:23.03#ibcon#read 4, iclass 4, count 2 2006.285.21:31:23.03#ibcon#about to read 5, iclass 4, count 2 2006.285.21:31:23.03#ibcon#read 5, iclass 4, count 2 2006.285.21:31:23.03#ibcon#about to read 6, iclass 4, count 2 2006.285.21:31:23.03#ibcon#read 6, iclass 4, count 2 2006.285.21:31:23.03#ibcon#end of sib2, iclass 4, count 2 2006.285.21:31:23.03#ibcon#*after write, iclass 4, count 2 2006.285.21:31:23.03#ibcon#*before return 0, iclass 4, count 2 2006.285.21:31:23.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:31:23.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:31:23.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.21:31:23.03#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:23.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:31:23.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:31:23.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:31:23.15#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:31:23.15#ibcon#first serial, iclass 4, count 0 2006.285.21:31:23.15#ibcon#enter sib2, iclass 4, count 0 2006.285.21:31:23.15#ibcon#flushed, iclass 4, count 0 2006.285.21:31:23.15#ibcon#about to write, iclass 4, count 0 2006.285.21:31:23.15#ibcon#wrote, iclass 4, count 0 2006.285.21:31:23.15#ibcon#about to read 3, iclass 4, count 0 2006.285.21:31:23.17#ibcon#read 3, iclass 4, count 0 2006.285.21:31:23.17#ibcon#about to read 4, iclass 4, count 0 2006.285.21:31:23.17#ibcon#read 4, iclass 4, count 0 2006.285.21:31:23.17#ibcon#about to read 5, iclass 4, count 0 2006.285.21:31:23.17#ibcon#read 5, iclass 4, count 0 2006.285.21:31:23.17#ibcon#about to read 6, iclass 4, count 0 2006.285.21:31:23.17#ibcon#read 6, iclass 4, count 0 2006.285.21:31:23.17#ibcon#end of sib2, iclass 4, count 0 2006.285.21:31:23.17#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:31:23.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:31:23.17#ibcon#[27=USB\r\n] 2006.285.21:31:23.17#ibcon#*before write, iclass 4, count 0 2006.285.21:31:23.17#ibcon#enter sib2, iclass 4, count 0 2006.285.21:31:23.17#ibcon#flushed, iclass 4, count 0 2006.285.21:31:23.17#ibcon#about to write, iclass 4, count 0 2006.285.21:31:23.17#ibcon#wrote, iclass 4, count 0 2006.285.21:31:23.17#ibcon#about to read 3, iclass 4, count 0 2006.285.21:31:23.20#ibcon#read 3, iclass 4, count 0 2006.285.21:31:23.20#ibcon#about to read 4, iclass 4, count 0 2006.285.21:31:23.20#ibcon#read 4, iclass 4, count 0 2006.285.21:31:23.20#ibcon#about to read 5, iclass 4, count 0 2006.285.21:31:23.20#ibcon#read 5, iclass 4, count 0 2006.285.21:31:23.20#ibcon#about to read 6, iclass 4, count 0 2006.285.21:31:23.20#ibcon#read 6, iclass 4, count 0 2006.285.21:31:23.20#ibcon#end of sib2, iclass 4, count 0 2006.285.21:31:23.20#ibcon#*after write, iclass 4, count 0 2006.285.21:31:23.20#ibcon#*before return 0, iclass 4, count 0 2006.285.21:31:23.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:31:23.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:31:23.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:31:23.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:31:23.20$vck44/vblo=6,719.99 2006.285.21:31:23.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.21:31:23.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.21:31:23.20#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:23.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:31:23.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:31:23.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:31:23.20#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:31:23.20#ibcon#first serial, iclass 6, count 0 2006.285.21:31:23.20#ibcon#enter sib2, iclass 6, count 0 2006.285.21:31:23.20#ibcon#flushed, iclass 6, count 0 2006.285.21:31:23.20#ibcon#about to write, iclass 6, count 0 2006.285.21:31:23.20#ibcon#wrote, iclass 6, count 0 2006.285.21:31:23.20#ibcon#about to read 3, iclass 6, count 0 2006.285.21:31:23.22#ibcon#read 3, iclass 6, count 0 2006.285.21:31:23.22#ibcon#about to read 4, iclass 6, count 0 2006.285.21:31:23.22#ibcon#read 4, iclass 6, count 0 2006.285.21:31:23.22#ibcon#about to read 5, iclass 6, count 0 2006.285.21:31:23.22#ibcon#read 5, iclass 6, count 0 2006.285.21:31:23.22#ibcon#about to read 6, iclass 6, count 0 2006.285.21:31:23.22#ibcon#read 6, iclass 6, count 0 2006.285.21:31:23.22#ibcon#end of sib2, iclass 6, count 0 2006.285.21:31:23.22#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:31:23.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:31:23.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:31:23.22#ibcon#*before write, iclass 6, count 0 2006.285.21:31:23.22#ibcon#enter sib2, iclass 6, count 0 2006.285.21:31:23.22#ibcon#flushed, iclass 6, count 0 2006.285.21:31:23.22#ibcon#about to write, iclass 6, count 0 2006.285.21:31:23.22#ibcon#wrote, iclass 6, count 0 2006.285.21:31:23.22#ibcon#about to read 3, iclass 6, count 0 2006.285.21:31:23.26#ibcon#read 3, iclass 6, count 0 2006.285.21:31:23.26#ibcon#about to read 4, iclass 6, count 0 2006.285.21:31:23.26#ibcon#read 4, iclass 6, count 0 2006.285.21:31:23.26#ibcon#about to read 5, iclass 6, count 0 2006.285.21:31:23.26#ibcon#read 5, iclass 6, count 0 2006.285.21:31:23.26#ibcon#about to read 6, iclass 6, count 0 2006.285.21:31:23.26#ibcon#read 6, iclass 6, count 0 2006.285.21:31:23.26#ibcon#end of sib2, iclass 6, count 0 2006.285.21:31:23.26#ibcon#*after write, iclass 6, count 0 2006.285.21:31:23.26#ibcon#*before return 0, iclass 6, count 0 2006.285.21:31:23.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:31:23.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:31:23.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:31:23.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:31:23.26$vck44/vb=6,3 2006.285.21:31:23.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.21:31:23.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.21:31:23.26#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:23.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:31:23.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:31:23.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:31:23.32#ibcon#enter wrdev, iclass 10, count 2 2006.285.21:31:23.32#ibcon#first serial, iclass 10, count 2 2006.285.21:31:23.32#ibcon#enter sib2, iclass 10, count 2 2006.285.21:31:23.32#ibcon#flushed, iclass 10, count 2 2006.285.21:31:23.32#ibcon#about to write, iclass 10, count 2 2006.285.21:31:23.32#ibcon#wrote, iclass 10, count 2 2006.285.21:31:23.32#ibcon#about to read 3, iclass 10, count 2 2006.285.21:31:23.34#ibcon#read 3, iclass 10, count 2 2006.285.21:31:23.34#ibcon#about to read 4, iclass 10, count 2 2006.285.21:31:23.34#ibcon#read 4, iclass 10, count 2 2006.285.21:31:23.34#ibcon#about to read 5, iclass 10, count 2 2006.285.21:31:23.34#ibcon#read 5, iclass 10, count 2 2006.285.21:31:23.34#ibcon#about to read 6, iclass 10, count 2 2006.285.21:31:23.34#ibcon#read 6, iclass 10, count 2 2006.285.21:31:23.34#ibcon#end of sib2, iclass 10, count 2 2006.285.21:31:23.34#ibcon#*mode == 0, iclass 10, count 2 2006.285.21:31:23.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.21:31:23.34#ibcon#[27=AT06-03\r\n] 2006.285.21:31:23.34#ibcon#*before write, iclass 10, count 2 2006.285.21:31:23.34#ibcon#enter sib2, iclass 10, count 2 2006.285.21:31:23.34#ibcon#flushed, iclass 10, count 2 2006.285.21:31:23.34#ibcon#about to write, iclass 10, count 2 2006.285.21:31:23.34#ibcon#wrote, iclass 10, count 2 2006.285.21:31:23.34#ibcon#about to read 3, iclass 10, count 2 2006.285.21:31:23.37#ibcon#read 3, iclass 10, count 2 2006.285.21:31:23.37#ibcon#about to read 4, iclass 10, count 2 2006.285.21:31:23.37#ibcon#read 4, iclass 10, count 2 2006.285.21:31:23.37#ibcon#about to read 5, iclass 10, count 2 2006.285.21:31:23.37#ibcon#read 5, iclass 10, count 2 2006.285.21:31:23.37#ibcon#about to read 6, iclass 10, count 2 2006.285.21:31:23.37#ibcon#read 6, iclass 10, count 2 2006.285.21:31:23.37#ibcon#end of sib2, iclass 10, count 2 2006.285.21:31:23.37#ibcon#*after write, iclass 10, count 2 2006.285.21:31:23.37#ibcon#*before return 0, iclass 10, count 2 2006.285.21:31:23.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:31:23.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:31:23.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.21:31:23.37#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:23.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:31:23.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:31:23.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:31:23.49#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:31:23.49#ibcon#first serial, iclass 10, count 0 2006.285.21:31:23.49#ibcon#enter sib2, iclass 10, count 0 2006.285.21:31:23.49#ibcon#flushed, iclass 10, count 0 2006.285.21:31:23.49#ibcon#about to write, iclass 10, count 0 2006.285.21:31:23.49#ibcon#wrote, iclass 10, count 0 2006.285.21:31:23.49#ibcon#about to read 3, iclass 10, count 0 2006.285.21:31:23.51#ibcon#read 3, iclass 10, count 0 2006.285.21:31:23.51#ibcon#about to read 4, iclass 10, count 0 2006.285.21:31:23.51#ibcon#read 4, iclass 10, count 0 2006.285.21:31:23.51#ibcon#about to read 5, iclass 10, count 0 2006.285.21:31:23.51#ibcon#read 5, iclass 10, count 0 2006.285.21:31:23.51#ibcon#about to read 6, iclass 10, count 0 2006.285.21:31:23.51#ibcon#read 6, iclass 10, count 0 2006.285.21:31:23.51#ibcon#end of sib2, iclass 10, count 0 2006.285.21:31:23.51#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:31:23.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:31:23.51#ibcon#[27=USB\r\n] 2006.285.21:31:23.51#ibcon#*before write, iclass 10, count 0 2006.285.21:31:23.51#ibcon#enter sib2, iclass 10, count 0 2006.285.21:31:23.51#ibcon#flushed, iclass 10, count 0 2006.285.21:31:23.51#ibcon#about to write, iclass 10, count 0 2006.285.21:31:23.51#ibcon#wrote, iclass 10, count 0 2006.285.21:31:23.51#ibcon#about to read 3, iclass 10, count 0 2006.285.21:31:23.54#ibcon#read 3, iclass 10, count 0 2006.285.21:31:23.54#ibcon#about to read 4, iclass 10, count 0 2006.285.21:31:23.54#ibcon#read 4, iclass 10, count 0 2006.285.21:31:23.54#ibcon#about to read 5, iclass 10, count 0 2006.285.21:31:23.54#ibcon#read 5, iclass 10, count 0 2006.285.21:31:23.54#ibcon#about to read 6, iclass 10, count 0 2006.285.21:31:23.54#ibcon#read 6, iclass 10, count 0 2006.285.21:31:23.54#ibcon#end of sib2, iclass 10, count 0 2006.285.21:31:23.54#ibcon#*after write, iclass 10, count 0 2006.285.21:31:23.54#ibcon#*before return 0, iclass 10, count 0 2006.285.21:31:23.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:31:23.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:31:23.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:31:23.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:31:23.54$vck44/vblo=7,734.99 2006.285.21:31:23.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.21:31:23.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.21:31:23.54#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:23.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:31:23.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:31:23.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:31:23.54#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:31:23.54#ibcon#first serial, iclass 12, count 0 2006.285.21:31:23.54#ibcon#enter sib2, iclass 12, count 0 2006.285.21:31:23.54#ibcon#flushed, iclass 12, count 0 2006.285.21:31:23.54#ibcon#about to write, iclass 12, count 0 2006.285.21:31:23.54#ibcon#wrote, iclass 12, count 0 2006.285.21:31:23.54#ibcon#about to read 3, iclass 12, count 0 2006.285.21:31:23.56#ibcon#read 3, iclass 12, count 0 2006.285.21:31:23.59#ibcon#about to read 4, iclass 12, count 0 2006.285.21:31:23.59#ibcon#read 4, iclass 12, count 0 2006.285.21:31:23.59#ibcon#about to read 5, iclass 12, count 0 2006.285.21:31:23.59#ibcon#read 5, iclass 12, count 0 2006.285.21:31:23.59#ibcon#about to read 6, iclass 12, count 0 2006.285.21:31:23.59#ibcon#read 6, iclass 12, count 0 2006.285.21:31:23.59#ibcon#end of sib2, iclass 12, count 0 2006.285.21:31:23.59#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:31:23.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:31:23.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:31:23.59#ibcon#*before write, iclass 12, count 0 2006.285.21:31:23.59#ibcon#enter sib2, iclass 12, count 0 2006.285.21:31:23.59#ibcon#flushed, iclass 12, count 0 2006.285.21:31:23.59#ibcon#about to write, iclass 12, count 0 2006.285.21:31:23.59#ibcon#wrote, iclass 12, count 0 2006.285.21:31:23.59#ibcon#about to read 3, iclass 12, count 0 2006.285.21:31:23.63#ibcon#read 3, iclass 12, count 0 2006.285.21:31:23.63#ibcon#about to read 4, iclass 12, count 0 2006.285.21:31:23.63#ibcon#read 4, iclass 12, count 0 2006.285.21:31:23.63#ibcon#about to read 5, iclass 12, count 0 2006.285.21:31:23.63#ibcon#read 5, iclass 12, count 0 2006.285.21:31:23.63#ibcon#about to read 6, iclass 12, count 0 2006.285.21:31:23.63#ibcon#read 6, iclass 12, count 0 2006.285.21:31:23.63#ibcon#end of sib2, iclass 12, count 0 2006.285.21:31:23.63#ibcon#*after write, iclass 12, count 0 2006.285.21:31:23.63#ibcon#*before return 0, iclass 12, count 0 2006.285.21:31:23.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:31:23.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:31:23.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:31:23.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:31:23.63$vck44/vb=7,4 2006.285.21:31:23.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.21:31:23.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.21:31:23.63#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:23.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:31:23.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:31:23.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:31:23.66#ibcon#enter wrdev, iclass 14, count 2 2006.285.21:31:23.66#ibcon#first serial, iclass 14, count 2 2006.285.21:31:23.66#ibcon#enter sib2, iclass 14, count 2 2006.285.21:31:23.66#ibcon#flushed, iclass 14, count 2 2006.285.21:31:23.66#ibcon#about to write, iclass 14, count 2 2006.285.21:31:23.66#ibcon#wrote, iclass 14, count 2 2006.285.21:31:23.66#ibcon#about to read 3, iclass 14, count 2 2006.285.21:31:23.68#ibcon#read 3, iclass 14, count 2 2006.285.21:31:23.68#ibcon#about to read 4, iclass 14, count 2 2006.285.21:31:23.68#ibcon#read 4, iclass 14, count 2 2006.285.21:31:23.68#ibcon#about to read 5, iclass 14, count 2 2006.285.21:31:23.68#ibcon#read 5, iclass 14, count 2 2006.285.21:31:23.68#ibcon#about to read 6, iclass 14, count 2 2006.285.21:31:23.68#ibcon#read 6, iclass 14, count 2 2006.285.21:31:23.68#ibcon#end of sib2, iclass 14, count 2 2006.285.21:31:23.68#ibcon#*mode == 0, iclass 14, count 2 2006.285.21:31:23.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.21:31:23.68#ibcon#[27=AT07-04\r\n] 2006.285.21:31:23.68#ibcon#*before write, iclass 14, count 2 2006.285.21:31:23.68#ibcon#enter sib2, iclass 14, count 2 2006.285.21:31:23.68#ibcon#flushed, iclass 14, count 2 2006.285.21:31:23.68#ibcon#about to write, iclass 14, count 2 2006.285.21:31:23.68#ibcon#wrote, iclass 14, count 2 2006.285.21:31:23.68#ibcon#about to read 3, iclass 14, count 2 2006.285.21:31:23.71#ibcon#read 3, iclass 14, count 2 2006.285.21:31:23.71#ibcon#about to read 4, iclass 14, count 2 2006.285.21:31:23.71#ibcon#read 4, iclass 14, count 2 2006.285.21:31:23.71#ibcon#about to read 5, iclass 14, count 2 2006.285.21:31:23.71#ibcon#read 5, iclass 14, count 2 2006.285.21:31:23.71#ibcon#about to read 6, iclass 14, count 2 2006.285.21:31:23.71#ibcon#read 6, iclass 14, count 2 2006.285.21:31:23.71#ibcon#end of sib2, iclass 14, count 2 2006.285.21:31:23.71#ibcon#*after write, iclass 14, count 2 2006.285.21:31:23.71#ibcon#*before return 0, iclass 14, count 2 2006.285.21:31:23.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:31:23.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:31:23.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.21:31:23.71#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:23.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:31:23.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:31:23.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:31:23.83#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:31:23.83#ibcon#first serial, iclass 14, count 0 2006.285.21:31:23.83#ibcon#enter sib2, iclass 14, count 0 2006.285.21:31:23.83#ibcon#flushed, iclass 14, count 0 2006.285.21:31:23.83#ibcon#about to write, iclass 14, count 0 2006.285.21:31:23.83#ibcon#wrote, iclass 14, count 0 2006.285.21:31:23.83#ibcon#about to read 3, iclass 14, count 0 2006.285.21:31:23.85#ibcon#read 3, iclass 14, count 0 2006.285.21:31:23.85#ibcon#about to read 4, iclass 14, count 0 2006.285.21:31:23.85#ibcon#read 4, iclass 14, count 0 2006.285.21:31:23.85#ibcon#about to read 5, iclass 14, count 0 2006.285.21:31:23.85#ibcon#read 5, iclass 14, count 0 2006.285.21:31:23.85#ibcon#about to read 6, iclass 14, count 0 2006.285.21:31:23.85#ibcon#read 6, iclass 14, count 0 2006.285.21:31:23.85#ibcon#end of sib2, iclass 14, count 0 2006.285.21:31:23.85#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:31:23.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:31:23.85#ibcon#[27=USB\r\n] 2006.285.21:31:23.85#ibcon#*before write, iclass 14, count 0 2006.285.21:31:23.85#ibcon#enter sib2, iclass 14, count 0 2006.285.21:31:23.85#ibcon#flushed, iclass 14, count 0 2006.285.21:31:23.85#ibcon#about to write, iclass 14, count 0 2006.285.21:31:23.85#ibcon#wrote, iclass 14, count 0 2006.285.21:31:23.85#ibcon#about to read 3, iclass 14, count 0 2006.285.21:31:23.88#ibcon#read 3, iclass 14, count 0 2006.285.21:31:23.88#ibcon#about to read 4, iclass 14, count 0 2006.285.21:31:23.88#ibcon#read 4, iclass 14, count 0 2006.285.21:31:23.88#ibcon#about to read 5, iclass 14, count 0 2006.285.21:31:23.88#ibcon#read 5, iclass 14, count 0 2006.285.21:31:23.88#ibcon#about to read 6, iclass 14, count 0 2006.285.21:31:23.88#ibcon#read 6, iclass 14, count 0 2006.285.21:31:23.88#ibcon#end of sib2, iclass 14, count 0 2006.285.21:31:23.88#ibcon#*after write, iclass 14, count 0 2006.285.21:31:23.88#ibcon#*before return 0, iclass 14, count 0 2006.285.21:31:23.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:31:23.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:31:23.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:31:23.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:31:23.88$vck44/vblo=8,744.99 2006.285.21:31:23.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.21:31:23.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.21:31:23.88#ibcon#ireg 17 cls_cnt 0 2006.285.21:31:23.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:31:23.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:31:23.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:31:23.88#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:31:23.88#ibcon#first serial, iclass 16, count 0 2006.285.21:31:23.88#ibcon#enter sib2, iclass 16, count 0 2006.285.21:31:23.88#ibcon#flushed, iclass 16, count 0 2006.285.21:31:23.88#ibcon#about to write, iclass 16, count 0 2006.285.21:31:23.88#ibcon#wrote, iclass 16, count 0 2006.285.21:31:23.88#ibcon#about to read 3, iclass 16, count 0 2006.285.21:31:23.90#ibcon#read 3, iclass 16, count 0 2006.285.21:31:23.90#ibcon#about to read 4, iclass 16, count 0 2006.285.21:31:23.90#ibcon#read 4, iclass 16, count 0 2006.285.21:31:23.90#ibcon#about to read 5, iclass 16, count 0 2006.285.21:31:23.90#ibcon#read 5, iclass 16, count 0 2006.285.21:31:23.90#ibcon#about to read 6, iclass 16, count 0 2006.285.21:31:23.90#ibcon#read 6, iclass 16, count 0 2006.285.21:31:23.90#ibcon#end of sib2, iclass 16, count 0 2006.285.21:31:23.90#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:31:23.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:31:23.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:31:23.90#ibcon#*before write, iclass 16, count 0 2006.285.21:31:23.90#ibcon#enter sib2, iclass 16, count 0 2006.285.21:31:23.90#ibcon#flushed, iclass 16, count 0 2006.285.21:31:23.90#ibcon#about to write, iclass 16, count 0 2006.285.21:31:23.90#ibcon#wrote, iclass 16, count 0 2006.285.21:31:23.90#ibcon#about to read 3, iclass 16, count 0 2006.285.21:31:23.94#ibcon#read 3, iclass 16, count 0 2006.285.21:31:23.94#ibcon#about to read 4, iclass 16, count 0 2006.285.21:31:23.94#ibcon#read 4, iclass 16, count 0 2006.285.21:31:23.94#ibcon#about to read 5, iclass 16, count 0 2006.285.21:31:23.94#ibcon#read 5, iclass 16, count 0 2006.285.21:31:23.94#ibcon#about to read 6, iclass 16, count 0 2006.285.21:31:23.94#ibcon#read 6, iclass 16, count 0 2006.285.21:31:23.94#ibcon#end of sib2, iclass 16, count 0 2006.285.21:31:23.94#ibcon#*after write, iclass 16, count 0 2006.285.21:31:23.94#ibcon#*before return 0, iclass 16, count 0 2006.285.21:31:23.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:31:23.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:31:23.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:31:23.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:31:23.94$vck44/vb=8,4 2006.285.21:31:23.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.21:31:23.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.21:31:23.94#ibcon#ireg 11 cls_cnt 2 2006.285.21:31:23.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:31:24.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:31:24.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:31:24.00#ibcon#enter wrdev, iclass 18, count 2 2006.285.21:31:24.00#ibcon#first serial, iclass 18, count 2 2006.285.21:31:24.00#ibcon#enter sib2, iclass 18, count 2 2006.285.21:31:24.00#ibcon#flushed, iclass 18, count 2 2006.285.21:31:24.00#ibcon#about to write, iclass 18, count 2 2006.285.21:31:24.00#ibcon#wrote, iclass 18, count 2 2006.285.21:31:24.00#ibcon#about to read 3, iclass 18, count 2 2006.285.21:31:24.02#ibcon#read 3, iclass 18, count 2 2006.285.21:31:24.02#ibcon#about to read 4, iclass 18, count 2 2006.285.21:31:24.02#ibcon#read 4, iclass 18, count 2 2006.285.21:31:24.02#ibcon#about to read 5, iclass 18, count 2 2006.285.21:31:24.02#ibcon#read 5, iclass 18, count 2 2006.285.21:31:24.02#ibcon#about to read 6, iclass 18, count 2 2006.285.21:31:24.02#ibcon#read 6, iclass 18, count 2 2006.285.21:31:24.02#ibcon#end of sib2, iclass 18, count 2 2006.285.21:31:24.02#ibcon#*mode == 0, iclass 18, count 2 2006.285.21:31:24.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.21:31:24.02#ibcon#[27=AT08-04\r\n] 2006.285.21:31:24.02#ibcon#*before write, iclass 18, count 2 2006.285.21:31:24.02#ibcon#enter sib2, iclass 18, count 2 2006.285.21:31:24.02#ibcon#flushed, iclass 18, count 2 2006.285.21:31:24.02#ibcon#about to write, iclass 18, count 2 2006.285.21:31:24.02#ibcon#wrote, iclass 18, count 2 2006.285.21:31:24.02#ibcon#about to read 3, iclass 18, count 2 2006.285.21:31:24.05#ibcon#read 3, iclass 18, count 2 2006.285.21:31:24.05#ibcon#about to read 4, iclass 18, count 2 2006.285.21:31:24.05#ibcon#read 4, iclass 18, count 2 2006.285.21:31:24.05#ibcon#about to read 5, iclass 18, count 2 2006.285.21:31:24.05#ibcon#read 5, iclass 18, count 2 2006.285.21:31:24.05#ibcon#about to read 6, iclass 18, count 2 2006.285.21:31:24.05#ibcon#read 6, iclass 18, count 2 2006.285.21:31:24.05#ibcon#end of sib2, iclass 18, count 2 2006.285.21:31:24.05#ibcon#*after write, iclass 18, count 2 2006.285.21:31:24.05#ibcon#*before return 0, iclass 18, count 2 2006.285.21:31:24.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:31:24.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:31:24.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.21:31:24.05#ibcon#ireg 7 cls_cnt 0 2006.285.21:31:24.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:31:24.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:31:24.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:31:24.17#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:31:24.17#ibcon#first serial, iclass 18, count 0 2006.285.21:31:24.17#ibcon#enter sib2, iclass 18, count 0 2006.285.21:31:24.17#ibcon#flushed, iclass 18, count 0 2006.285.21:31:24.17#ibcon#about to write, iclass 18, count 0 2006.285.21:31:24.17#ibcon#wrote, iclass 18, count 0 2006.285.21:31:24.17#ibcon#about to read 3, iclass 18, count 0 2006.285.21:31:24.19#ibcon#read 3, iclass 18, count 0 2006.285.21:31:24.19#ibcon#about to read 4, iclass 18, count 0 2006.285.21:31:24.19#ibcon#read 4, iclass 18, count 0 2006.285.21:31:24.19#ibcon#about to read 5, iclass 18, count 0 2006.285.21:31:24.19#ibcon#read 5, iclass 18, count 0 2006.285.21:31:24.19#ibcon#about to read 6, iclass 18, count 0 2006.285.21:31:24.19#ibcon#read 6, iclass 18, count 0 2006.285.21:31:24.19#ibcon#end of sib2, iclass 18, count 0 2006.285.21:31:24.19#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:31:24.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:31:24.19#ibcon#[27=USB\r\n] 2006.285.21:31:24.19#ibcon#*before write, iclass 18, count 0 2006.285.21:31:24.19#ibcon#enter sib2, iclass 18, count 0 2006.285.21:31:24.19#ibcon#flushed, iclass 18, count 0 2006.285.21:31:24.19#ibcon#about to write, iclass 18, count 0 2006.285.21:31:24.19#ibcon#wrote, iclass 18, count 0 2006.285.21:31:24.19#ibcon#about to read 3, iclass 18, count 0 2006.285.21:31:24.22#ibcon#read 3, iclass 18, count 0 2006.285.21:31:24.22#ibcon#about to read 4, iclass 18, count 0 2006.285.21:31:24.22#ibcon#read 4, iclass 18, count 0 2006.285.21:31:24.22#ibcon#about to read 5, iclass 18, count 0 2006.285.21:31:24.22#ibcon#read 5, iclass 18, count 0 2006.285.21:31:24.22#ibcon#about to read 6, iclass 18, count 0 2006.285.21:31:24.22#ibcon#read 6, iclass 18, count 0 2006.285.21:31:24.22#ibcon#end of sib2, iclass 18, count 0 2006.285.21:31:24.22#ibcon#*after write, iclass 18, count 0 2006.285.21:31:24.22#ibcon#*before return 0, iclass 18, count 0 2006.285.21:31:24.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:31:24.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:31:24.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:31:24.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:31:24.22$vck44/vabw=wide 2006.285.21:31:24.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.21:31:24.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.21:31:24.22#ibcon#ireg 8 cls_cnt 0 2006.285.21:31:24.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:31:24.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:31:24.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:31:24.22#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:31:24.22#ibcon#first serial, iclass 20, count 0 2006.285.21:31:24.22#ibcon#enter sib2, iclass 20, count 0 2006.285.21:31:24.22#ibcon#flushed, iclass 20, count 0 2006.285.21:31:24.22#ibcon#about to write, iclass 20, count 0 2006.285.21:31:24.22#ibcon#wrote, iclass 20, count 0 2006.285.21:31:24.22#ibcon#about to read 3, iclass 20, count 0 2006.285.21:31:24.24#ibcon#read 3, iclass 20, count 0 2006.285.21:31:24.24#ibcon#about to read 4, iclass 20, count 0 2006.285.21:31:24.24#ibcon#read 4, iclass 20, count 0 2006.285.21:31:24.24#ibcon#about to read 5, iclass 20, count 0 2006.285.21:31:24.24#ibcon#read 5, iclass 20, count 0 2006.285.21:31:24.24#ibcon#about to read 6, iclass 20, count 0 2006.285.21:31:24.24#ibcon#read 6, iclass 20, count 0 2006.285.21:31:24.24#ibcon#end of sib2, iclass 20, count 0 2006.285.21:31:24.24#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:31:24.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:31:24.24#ibcon#[25=BW32\r\n] 2006.285.21:31:24.24#ibcon#*before write, iclass 20, count 0 2006.285.21:31:24.24#ibcon#enter sib2, iclass 20, count 0 2006.285.21:31:24.24#ibcon#flushed, iclass 20, count 0 2006.285.21:31:24.24#ibcon#about to write, iclass 20, count 0 2006.285.21:31:24.24#ibcon#wrote, iclass 20, count 0 2006.285.21:31:24.24#ibcon#about to read 3, iclass 20, count 0 2006.285.21:31:24.27#ibcon#read 3, iclass 20, count 0 2006.285.21:31:24.27#ibcon#about to read 4, iclass 20, count 0 2006.285.21:31:24.27#ibcon#read 4, iclass 20, count 0 2006.285.21:31:24.27#ibcon#about to read 5, iclass 20, count 0 2006.285.21:31:24.27#ibcon#read 5, iclass 20, count 0 2006.285.21:31:24.27#ibcon#about to read 6, iclass 20, count 0 2006.285.21:31:24.27#ibcon#read 6, iclass 20, count 0 2006.285.21:31:24.27#ibcon#end of sib2, iclass 20, count 0 2006.285.21:31:24.27#ibcon#*after write, iclass 20, count 0 2006.285.21:31:24.27#ibcon#*before return 0, iclass 20, count 0 2006.285.21:31:24.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:31:24.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:31:24.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:31:24.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:31:24.27$vck44/vbbw=wide 2006.285.21:31:24.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.21:31:24.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.21:31:24.27#ibcon#ireg 8 cls_cnt 0 2006.285.21:31:24.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:31:24.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:31:24.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:31:24.34#ibcon#enter wrdev, iclass 22, count 0 2006.285.21:31:24.34#ibcon#first serial, iclass 22, count 0 2006.285.21:31:24.34#ibcon#enter sib2, iclass 22, count 0 2006.285.21:31:24.34#ibcon#flushed, iclass 22, count 0 2006.285.21:31:24.34#ibcon#about to write, iclass 22, count 0 2006.285.21:31:24.34#ibcon#wrote, iclass 22, count 0 2006.285.21:31:24.34#ibcon#about to read 3, iclass 22, count 0 2006.285.21:31:24.36#ibcon#read 3, iclass 22, count 0 2006.285.21:31:24.36#ibcon#about to read 4, iclass 22, count 0 2006.285.21:31:24.36#ibcon#read 4, iclass 22, count 0 2006.285.21:31:24.36#ibcon#about to read 5, iclass 22, count 0 2006.285.21:31:24.36#ibcon#read 5, iclass 22, count 0 2006.285.21:31:24.36#ibcon#about to read 6, iclass 22, count 0 2006.285.21:31:24.36#ibcon#read 6, iclass 22, count 0 2006.285.21:31:24.36#ibcon#end of sib2, iclass 22, count 0 2006.285.21:31:24.36#ibcon#*mode == 0, iclass 22, count 0 2006.285.21:31:24.36#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.21:31:24.36#ibcon#[27=BW32\r\n] 2006.285.21:31:24.36#ibcon#*before write, iclass 22, count 0 2006.285.21:31:24.36#ibcon#enter sib2, iclass 22, count 0 2006.285.21:31:24.36#ibcon#flushed, iclass 22, count 0 2006.285.21:31:24.36#ibcon#about to write, iclass 22, count 0 2006.285.21:31:24.36#ibcon#wrote, iclass 22, count 0 2006.285.21:31:24.36#ibcon#about to read 3, iclass 22, count 0 2006.285.21:31:24.39#ibcon#read 3, iclass 22, count 0 2006.285.21:31:24.39#ibcon#about to read 4, iclass 22, count 0 2006.285.21:31:24.39#ibcon#read 4, iclass 22, count 0 2006.285.21:31:24.39#ibcon#about to read 5, iclass 22, count 0 2006.285.21:31:24.39#ibcon#read 5, iclass 22, count 0 2006.285.21:31:24.39#ibcon#about to read 6, iclass 22, count 0 2006.285.21:31:24.39#ibcon#read 6, iclass 22, count 0 2006.285.21:31:24.39#ibcon#end of sib2, iclass 22, count 0 2006.285.21:31:24.39#ibcon#*after write, iclass 22, count 0 2006.285.21:31:24.39#ibcon#*before return 0, iclass 22, count 0 2006.285.21:31:24.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:31:24.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:31:24.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.21:31:24.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.21:31:24.39$setupk4/ifdk4 2006.285.21:31:24.39$ifdk4/lo= 2006.285.21:31:24.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:31:24.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:31:24.39$ifdk4/patch= 2006.285.21:31:24.39$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:31:24.39$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:31:24.39$setupk4/!*+20s 2006.285.21:31:24.74#abcon#<5=/16 0.4 1.1 14.591001015.8\r\n> 2006.285.21:31:24.76#abcon#{5=INTERFACE CLEAR} 2006.285.21:31:24.82#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:31:34.91#abcon#<5=/16 0.4 1.2 14.591001015.8\r\n> 2006.285.21:31:34.93#abcon#{5=INTERFACE CLEAR} 2006.285.21:31:34.99#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:31:38.09$setupk4/"tpicd 2006.285.21:31:38.09$setupk4/echo=off 2006.285.21:31:38.09$setupk4/xlog=off 2006.285.21:31:38.09:!2006.285.21:33:19 2006.285.21:31:51.14#trakl#Source acquired 2006.285.21:31:52.14#flagr#flagr/antenna,acquired 2006.285.21:33:19.00:preob 2006.285.21:33:20.14/onsource/TRACKING 2006.285.21:33:20.14:!2006.285.21:33:29 2006.285.21:33:29.00:"tape 2006.285.21:33:29.00:"st=record 2006.285.21:33:29.00:data_valid=on 2006.285.21:33:29.00:midob 2006.285.21:33:29.14/onsource/TRACKING 2006.285.21:33:29.14/wx/14.63,1015.7,100 2006.285.21:33:29.23/cable/+6.5096E-03 2006.285.21:33:30.32/va/01,07,usb,yes,37,40 2006.285.21:33:30.32/va/02,06,usb,yes,37,37 2006.285.21:33:30.32/va/03,07,usb,yes,36,38 2006.285.21:33:30.32/va/04,06,usb,yes,38,40 2006.285.21:33:30.32/va/05,03,usb,yes,37,38 2006.285.21:33:30.32/va/06,04,usb,yes,34,33 2006.285.21:33:30.32/va/07,04,usb,yes,34,35 2006.285.21:33:30.32/va/08,03,usb,yes,35,43 2006.285.21:33:30.55/valo/01,524.99,yes,locked 2006.285.21:33:30.55/valo/02,534.99,yes,locked 2006.285.21:33:30.55/valo/03,564.99,yes,locked 2006.285.21:33:30.55/valo/04,624.99,yes,locked 2006.285.21:33:30.55/valo/05,734.99,yes,locked 2006.285.21:33:30.55/valo/06,814.99,yes,locked 2006.285.21:33:30.55/valo/07,864.99,yes,locked 2006.285.21:33:30.55/valo/08,884.99,yes,locked 2006.285.21:33:31.64/vb/01,04,usb,yes,38,35 2006.285.21:33:31.64/vb/02,05,usb,yes,36,36 2006.285.21:33:31.64/vb/03,04,usb,yes,37,41 2006.285.21:33:31.64/vb/04,05,usb,yes,37,36 2006.285.21:33:31.64/vb/05,04,usb,yes,33,36 2006.285.21:33:31.64/vb/06,03,usb,yes,47,42 2006.285.21:33:31.64/vb/07,04,usb,yes,38,38 2006.285.21:33:31.64/vb/08,04,usb,yes,34,39 2006.285.21:33:31.88/vblo/01,629.99,yes,locked 2006.285.21:33:31.88/vblo/02,634.99,yes,locked 2006.285.21:33:31.88/vblo/03,649.99,yes,locked 2006.285.21:33:31.88/vblo/04,679.99,yes,locked 2006.285.21:33:31.88/vblo/05,709.99,yes,locked 2006.285.21:33:31.88/vblo/06,719.99,yes,locked 2006.285.21:33:31.88/vblo/07,734.99,yes,locked 2006.285.21:33:31.88/vblo/08,744.99,yes,locked 2006.285.21:33:32.03/vabw/8 2006.285.21:33:32.18/vbbw/8 2006.285.21:33:32.30/xfe/off,on,12.0 2006.285.21:33:32.69/ifatt/23,28,28,28 2006.285.21:33:33.07/fmout-gps/S +2.69E-07 2006.285.21:33:33.09:!2006.285.21:34:59 2006.285.21:34:59.01:data_valid=off 2006.285.21:34:59.01:"et 2006.285.21:34:59.01:!+3s 2006.285.21:35:02.02:"tape 2006.285.21:35:02.02:postob 2006.285.21:35:02.15/cable/+6.5087E-03 2006.285.21:35:02.15/wx/14.68,1015.7,100 2006.285.21:35:02.21/fmout-gps/S +2.66E-07 2006.285.21:35:02.21:scan_name=285-2138,jd0610,330 2006.285.21:35:02.21:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.285.21:35:03.13#flagr#flagr/antenna,new-source 2006.285.21:35:03.13:checkk5 2006.285.21:35:03.80/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:35:04.22/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:35:04.69/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:35:05.14/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:35:05.54/chk_obsdata//k5ts1/T2852133??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.285.21:35:06.11/chk_obsdata//k5ts2/T2852133??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.285.21:35:06.52/chk_obsdata//k5ts3/T2852133??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.285.21:35:06.95/chk_obsdata//k5ts4/T2852133??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.285.21:35:07.74/k5log//k5ts1_log_newline 2006.285.21:35:08.65/k5log//k5ts2_log_newline 2006.285.21:35:09.72/k5log//k5ts3_log_newline 2006.285.21:35:10.50/k5log//k5ts4_log_newline 2006.285.21:35:10.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:35:10.52:setupk4=1 2006.285.21:35:10.52$setupk4/echo=on 2006.285.21:35:10.52$setupk4/pcalon 2006.285.21:35:10.52$pcalon/"no phase cal control is implemented here 2006.285.21:35:10.52$setupk4/"tpicd=stop 2006.285.21:35:10.53$setupk4/"rec=synch_on 2006.285.21:35:10.53$setupk4/"rec_mode=128 2006.285.21:35:10.53$setupk4/!* 2006.285.21:35:10.53$setupk4/recpk4 2006.285.21:35:10.53$recpk4/recpatch= 2006.285.21:35:10.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:35:10.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:35:10.53$setupk4/vck44 2006.285.21:35:10.53$vck44/valo=1,524.99 2006.285.21:35:10.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.21:35:10.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.21:35:10.53#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:10.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:35:10.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:35:10.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:35:10.53#ibcon#enter wrdev, iclass 11, count 0 2006.285.21:35:10.53#ibcon#first serial, iclass 11, count 0 2006.285.21:35:10.53#ibcon#enter sib2, iclass 11, count 0 2006.285.21:35:10.53#ibcon#flushed, iclass 11, count 0 2006.285.21:35:10.53#ibcon#about to write, iclass 11, count 0 2006.285.21:35:10.53#ibcon#wrote, iclass 11, count 0 2006.285.21:35:10.53#ibcon#about to read 3, iclass 11, count 0 2006.285.21:35:10.55#ibcon#read 3, iclass 11, count 0 2006.285.21:35:10.55#ibcon#about to read 4, iclass 11, count 0 2006.285.21:35:10.55#ibcon#read 4, iclass 11, count 0 2006.285.21:35:10.55#ibcon#about to read 5, iclass 11, count 0 2006.285.21:35:10.55#ibcon#read 5, iclass 11, count 0 2006.285.21:35:10.55#ibcon#about to read 6, iclass 11, count 0 2006.285.21:35:10.55#ibcon#read 6, iclass 11, count 0 2006.285.21:35:10.55#ibcon#end of sib2, iclass 11, count 0 2006.285.21:35:10.55#ibcon#*mode == 0, iclass 11, count 0 2006.285.21:35:10.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.21:35:10.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:35:10.55#ibcon#*before write, iclass 11, count 0 2006.285.21:35:10.55#ibcon#enter sib2, iclass 11, count 0 2006.285.21:35:10.55#ibcon#flushed, iclass 11, count 0 2006.285.21:35:10.55#ibcon#about to write, iclass 11, count 0 2006.285.21:35:10.55#ibcon#wrote, iclass 11, count 0 2006.285.21:35:10.55#ibcon#about to read 3, iclass 11, count 0 2006.285.21:35:10.60#ibcon#read 3, iclass 11, count 0 2006.285.21:35:10.60#ibcon#about to read 4, iclass 11, count 0 2006.285.21:35:10.60#ibcon#read 4, iclass 11, count 0 2006.285.21:35:10.60#ibcon#about to read 5, iclass 11, count 0 2006.285.21:35:10.60#ibcon#read 5, iclass 11, count 0 2006.285.21:35:10.60#ibcon#about to read 6, iclass 11, count 0 2006.285.21:35:10.60#ibcon#read 6, iclass 11, count 0 2006.285.21:35:10.60#ibcon#end of sib2, iclass 11, count 0 2006.285.21:35:10.60#ibcon#*after write, iclass 11, count 0 2006.285.21:35:10.60#ibcon#*before return 0, iclass 11, count 0 2006.285.21:35:10.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:35:10.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:35:10.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.21:35:10.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.21:35:10.60$vck44/va=1,7 2006.285.21:35:10.60#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.21:35:10.60#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.21:35:10.60#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:10.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:35:10.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:35:10.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:35:10.60#ibcon#enter wrdev, iclass 13, count 2 2006.285.21:35:10.60#ibcon#first serial, iclass 13, count 2 2006.285.21:35:10.60#ibcon#enter sib2, iclass 13, count 2 2006.285.21:35:10.60#ibcon#flushed, iclass 13, count 2 2006.285.21:35:10.60#ibcon#about to write, iclass 13, count 2 2006.285.21:35:10.60#ibcon#wrote, iclass 13, count 2 2006.285.21:35:10.60#ibcon#about to read 3, iclass 13, count 2 2006.285.21:35:10.62#ibcon#read 3, iclass 13, count 2 2006.285.21:35:10.62#ibcon#about to read 4, iclass 13, count 2 2006.285.21:35:10.62#ibcon#read 4, iclass 13, count 2 2006.285.21:35:10.62#ibcon#about to read 5, iclass 13, count 2 2006.285.21:35:10.62#ibcon#read 5, iclass 13, count 2 2006.285.21:35:10.62#ibcon#about to read 6, iclass 13, count 2 2006.285.21:35:10.62#ibcon#read 6, iclass 13, count 2 2006.285.21:35:10.62#ibcon#end of sib2, iclass 13, count 2 2006.285.21:35:10.62#ibcon#*mode == 0, iclass 13, count 2 2006.285.21:35:10.62#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.21:35:10.62#ibcon#[25=AT01-07\r\n] 2006.285.21:35:10.62#ibcon#*before write, iclass 13, count 2 2006.285.21:35:10.62#ibcon#enter sib2, iclass 13, count 2 2006.285.21:35:10.62#ibcon#flushed, iclass 13, count 2 2006.285.21:35:10.62#ibcon#about to write, iclass 13, count 2 2006.285.21:35:10.62#ibcon#wrote, iclass 13, count 2 2006.285.21:35:10.62#ibcon#about to read 3, iclass 13, count 2 2006.285.21:35:10.65#ibcon#read 3, iclass 13, count 2 2006.285.21:35:10.65#ibcon#about to read 4, iclass 13, count 2 2006.285.21:35:10.65#ibcon#read 4, iclass 13, count 2 2006.285.21:35:10.65#ibcon#about to read 5, iclass 13, count 2 2006.285.21:35:10.65#ibcon#read 5, iclass 13, count 2 2006.285.21:35:10.65#ibcon#about to read 6, iclass 13, count 2 2006.285.21:35:10.65#ibcon#read 6, iclass 13, count 2 2006.285.21:35:10.65#ibcon#end of sib2, iclass 13, count 2 2006.285.21:35:10.65#ibcon#*after write, iclass 13, count 2 2006.285.21:35:10.65#ibcon#*before return 0, iclass 13, count 2 2006.285.21:35:10.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:35:10.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:35:10.65#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.21:35:10.65#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:10.65#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:35:10.77#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:35:10.77#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:35:10.77#ibcon#enter wrdev, iclass 13, count 0 2006.285.21:35:10.77#ibcon#first serial, iclass 13, count 0 2006.285.21:35:10.77#ibcon#enter sib2, iclass 13, count 0 2006.285.21:35:10.77#ibcon#flushed, iclass 13, count 0 2006.285.21:35:10.77#ibcon#about to write, iclass 13, count 0 2006.285.21:35:10.77#ibcon#wrote, iclass 13, count 0 2006.285.21:35:10.77#ibcon#about to read 3, iclass 13, count 0 2006.285.21:35:10.79#ibcon#read 3, iclass 13, count 0 2006.285.21:35:10.79#ibcon#about to read 4, iclass 13, count 0 2006.285.21:35:10.79#ibcon#read 4, iclass 13, count 0 2006.285.21:35:10.79#ibcon#about to read 5, iclass 13, count 0 2006.285.21:35:10.79#ibcon#read 5, iclass 13, count 0 2006.285.21:35:10.79#ibcon#about to read 6, iclass 13, count 0 2006.285.21:35:10.79#ibcon#read 6, iclass 13, count 0 2006.285.21:35:10.79#ibcon#end of sib2, iclass 13, count 0 2006.285.21:35:10.79#ibcon#*mode == 0, iclass 13, count 0 2006.285.21:35:10.79#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.21:35:10.79#ibcon#[25=USB\r\n] 2006.285.21:35:10.79#ibcon#*before write, iclass 13, count 0 2006.285.21:35:10.79#ibcon#enter sib2, iclass 13, count 0 2006.285.21:35:10.79#ibcon#flushed, iclass 13, count 0 2006.285.21:35:10.79#ibcon#about to write, iclass 13, count 0 2006.285.21:35:10.79#ibcon#wrote, iclass 13, count 0 2006.285.21:35:10.79#ibcon#about to read 3, iclass 13, count 0 2006.285.21:35:10.82#ibcon#read 3, iclass 13, count 0 2006.285.21:35:10.82#ibcon#about to read 4, iclass 13, count 0 2006.285.21:35:10.82#ibcon#read 4, iclass 13, count 0 2006.285.21:35:10.82#ibcon#about to read 5, iclass 13, count 0 2006.285.21:35:10.82#ibcon#read 5, iclass 13, count 0 2006.285.21:35:10.82#ibcon#about to read 6, iclass 13, count 0 2006.285.21:35:10.82#ibcon#read 6, iclass 13, count 0 2006.285.21:35:10.82#ibcon#end of sib2, iclass 13, count 0 2006.285.21:35:10.82#ibcon#*after write, iclass 13, count 0 2006.285.21:35:10.82#ibcon#*before return 0, iclass 13, count 0 2006.285.21:35:10.82#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:35:10.82#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:35:10.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.21:35:10.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.21:35:10.82$vck44/valo=2,534.99 2006.285.21:35:10.82#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.21:35:11.16#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.21:35:11.16#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:11.16#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:35:11.16#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:35:11.16#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:35:11.16#ibcon#enter wrdev, iclass 15, count 0 2006.285.21:35:11.16#ibcon#first serial, iclass 15, count 0 2006.285.21:35:11.16#ibcon#enter sib2, iclass 15, count 0 2006.285.21:35:11.17#ibcon#flushed, iclass 15, count 0 2006.285.21:35:11.17#ibcon#about to write, iclass 15, count 0 2006.285.21:35:11.17#ibcon#wrote, iclass 15, count 0 2006.285.21:35:11.17#ibcon#about to read 3, iclass 15, count 0 2006.285.21:35:11.18#ibcon#read 3, iclass 15, count 0 2006.285.21:35:11.18#ibcon#about to read 4, iclass 15, count 0 2006.285.21:35:11.18#ibcon#read 4, iclass 15, count 0 2006.285.21:35:11.18#ibcon#about to read 5, iclass 15, count 0 2006.285.21:35:11.18#ibcon#read 5, iclass 15, count 0 2006.285.21:35:11.18#ibcon#about to read 6, iclass 15, count 0 2006.285.21:35:11.18#ibcon#read 6, iclass 15, count 0 2006.285.21:35:11.18#ibcon#end of sib2, iclass 15, count 0 2006.285.21:35:11.18#ibcon#*mode == 0, iclass 15, count 0 2006.285.21:35:11.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.21:35:11.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:35:11.18#ibcon#*before write, iclass 15, count 0 2006.285.21:35:11.18#ibcon#enter sib2, iclass 15, count 0 2006.285.21:35:11.18#ibcon#flushed, iclass 15, count 0 2006.285.21:35:11.18#ibcon#about to write, iclass 15, count 0 2006.285.21:35:11.18#ibcon#wrote, iclass 15, count 0 2006.285.21:35:11.18#ibcon#about to read 3, iclass 15, count 0 2006.285.21:35:11.22#ibcon#read 3, iclass 15, count 0 2006.285.21:35:11.22#ibcon#about to read 4, iclass 15, count 0 2006.285.21:35:11.22#ibcon#read 4, iclass 15, count 0 2006.285.21:35:11.22#ibcon#about to read 5, iclass 15, count 0 2006.285.21:35:11.22#ibcon#read 5, iclass 15, count 0 2006.285.21:35:11.22#ibcon#about to read 6, iclass 15, count 0 2006.285.21:35:11.22#ibcon#read 6, iclass 15, count 0 2006.285.21:35:11.22#ibcon#end of sib2, iclass 15, count 0 2006.285.21:35:11.22#ibcon#*after write, iclass 15, count 0 2006.285.21:35:11.22#ibcon#*before return 0, iclass 15, count 0 2006.285.21:35:11.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:35:11.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:35:11.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.21:35:11.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.21:35:11.22$vck44/va=2,6 2006.285.21:35:11.22#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.21:35:11.22#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.21:35:11.22#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:11.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:35:11.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:35:11.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:35:11.22#ibcon#enter wrdev, iclass 17, count 2 2006.285.21:35:11.22#ibcon#first serial, iclass 17, count 2 2006.285.21:35:11.22#ibcon#enter sib2, iclass 17, count 2 2006.285.21:35:11.22#ibcon#flushed, iclass 17, count 2 2006.285.21:35:11.22#ibcon#about to write, iclass 17, count 2 2006.285.21:35:11.22#ibcon#wrote, iclass 17, count 2 2006.285.21:35:11.22#ibcon#about to read 3, iclass 17, count 2 2006.285.21:35:11.24#ibcon#read 3, iclass 17, count 2 2006.285.21:35:11.24#ibcon#about to read 4, iclass 17, count 2 2006.285.21:35:11.24#ibcon#read 4, iclass 17, count 2 2006.285.21:35:11.24#ibcon#about to read 5, iclass 17, count 2 2006.285.21:35:11.24#ibcon#read 5, iclass 17, count 2 2006.285.21:35:11.24#ibcon#about to read 6, iclass 17, count 2 2006.285.21:35:11.24#ibcon#read 6, iclass 17, count 2 2006.285.21:35:11.24#ibcon#end of sib2, iclass 17, count 2 2006.285.21:35:11.24#ibcon#*mode == 0, iclass 17, count 2 2006.285.21:35:11.24#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.21:35:11.24#ibcon#[25=AT02-06\r\n] 2006.285.21:35:11.24#ibcon#*before write, iclass 17, count 2 2006.285.21:35:11.24#ibcon#enter sib2, iclass 17, count 2 2006.285.21:35:11.24#ibcon#flushed, iclass 17, count 2 2006.285.21:35:11.24#ibcon#about to write, iclass 17, count 2 2006.285.21:35:11.24#ibcon#wrote, iclass 17, count 2 2006.285.21:35:11.24#ibcon#about to read 3, iclass 17, count 2 2006.285.21:35:11.27#ibcon#read 3, iclass 17, count 2 2006.285.21:35:11.27#ibcon#about to read 4, iclass 17, count 2 2006.285.21:35:11.27#ibcon#read 4, iclass 17, count 2 2006.285.21:35:11.27#ibcon#about to read 5, iclass 17, count 2 2006.285.21:35:11.27#ibcon#read 5, iclass 17, count 2 2006.285.21:35:11.27#ibcon#about to read 6, iclass 17, count 2 2006.285.21:35:11.27#ibcon#read 6, iclass 17, count 2 2006.285.21:35:11.27#ibcon#end of sib2, iclass 17, count 2 2006.285.21:35:11.27#ibcon#*after write, iclass 17, count 2 2006.285.21:35:11.27#ibcon#*before return 0, iclass 17, count 2 2006.285.21:35:11.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:35:11.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:35:11.27#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.21:35:11.27#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:11.27#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:35:11.39#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:35:11.39#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:35:11.39#ibcon#enter wrdev, iclass 17, count 0 2006.285.21:35:11.39#ibcon#first serial, iclass 17, count 0 2006.285.21:35:11.39#ibcon#enter sib2, iclass 17, count 0 2006.285.21:35:11.39#ibcon#flushed, iclass 17, count 0 2006.285.21:35:11.39#ibcon#about to write, iclass 17, count 0 2006.285.21:35:11.39#ibcon#wrote, iclass 17, count 0 2006.285.21:35:11.39#ibcon#about to read 3, iclass 17, count 0 2006.285.21:35:11.41#ibcon#read 3, iclass 17, count 0 2006.285.21:35:11.41#ibcon#about to read 4, iclass 17, count 0 2006.285.21:35:11.41#ibcon#read 4, iclass 17, count 0 2006.285.21:35:11.41#ibcon#about to read 5, iclass 17, count 0 2006.285.21:35:11.41#ibcon#read 5, iclass 17, count 0 2006.285.21:35:11.41#ibcon#about to read 6, iclass 17, count 0 2006.285.21:35:11.41#ibcon#read 6, iclass 17, count 0 2006.285.21:35:11.41#ibcon#end of sib2, iclass 17, count 0 2006.285.21:35:11.41#ibcon#*mode == 0, iclass 17, count 0 2006.285.21:35:11.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.21:35:11.41#ibcon#[25=USB\r\n] 2006.285.21:35:11.41#ibcon#*before write, iclass 17, count 0 2006.285.21:35:11.41#ibcon#enter sib2, iclass 17, count 0 2006.285.21:35:11.41#ibcon#flushed, iclass 17, count 0 2006.285.21:35:11.41#ibcon#about to write, iclass 17, count 0 2006.285.21:35:11.41#ibcon#wrote, iclass 17, count 0 2006.285.21:35:11.41#ibcon#about to read 3, iclass 17, count 0 2006.285.21:35:11.44#ibcon#read 3, iclass 17, count 0 2006.285.21:35:11.44#ibcon#about to read 4, iclass 17, count 0 2006.285.21:35:11.44#ibcon#read 4, iclass 17, count 0 2006.285.21:35:11.44#ibcon#about to read 5, iclass 17, count 0 2006.285.21:35:11.44#ibcon#read 5, iclass 17, count 0 2006.285.21:35:11.44#ibcon#about to read 6, iclass 17, count 0 2006.285.21:35:11.44#ibcon#read 6, iclass 17, count 0 2006.285.21:35:11.44#ibcon#end of sib2, iclass 17, count 0 2006.285.21:35:11.44#ibcon#*after write, iclass 17, count 0 2006.285.21:35:11.44#ibcon#*before return 0, iclass 17, count 0 2006.285.21:35:11.44#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:35:11.44#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:35:11.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.21:35:11.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.21:35:11.44$vck44/valo=3,564.99 2006.285.21:35:11.44#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.21:35:11.44#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.21:35:11.44#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:11.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:35:11.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:35:11.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:35:11.44#ibcon#enter wrdev, iclass 19, count 0 2006.285.21:35:11.44#ibcon#first serial, iclass 19, count 0 2006.285.21:35:11.44#ibcon#enter sib2, iclass 19, count 0 2006.285.21:35:11.44#ibcon#flushed, iclass 19, count 0 2006.285.21:35:11.44#ibcon#about to write, iclass 19, count 0 2006.285.21:35:11.56#ibcon#wrote, iclass 19, count 0 2006.285.21:35:11.56#ibcon#about to read 3, iclass 19, count 0 2006.285.21:35:11.58#ibcon#read 3, iclass 19, count 0 2006.285.21:35:11.58#ibcon#about to read 4, iclass 19, count 0 2006.285.21:35:11.58#ibcon#read 4, iclass 19, count 0 2006.285.21:35:11.58#ibcon#about to read 5, iclass 19, count 0 2006.285.21:35:11.58#ibcon#read 5, iclass 19, count 0 2006.285.21:35:11.58#ibcon#about to read 6, iclass 19, count 0 2006.285.21:35:11.58#ibcon#read 6, iclass 19, count 0 2006.285.21:35:11.58#ibcon#end of sib2, iclass 19, count 0 2006.285.21:35:11.58#ibcon#*mode == 0, iclass 19, count 0 2006.285.21:35:11.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.21:35:11.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:35:11.58#ibcon#*before write, iclass 19, count 0 2006.285.21:35:11.58#ibcon#enter sib2, iclass 19, count 0 2006.285.21:35:11.58#ibcon#flushed, iclass 19, count 0 2006.285.21:35:11.58#ibcon#about to write, iclass 19, count 0 2006.285.21:35:11.58#ibcon#wrote, iclass 19, count 0 2006.285.21:35:11.58#ibcon#about to read 3, iclass 19, count 0 2006.285.21:35:11.62#ibcon#read 3, iclass 19, count 0 2006.285.21:35:11.62#ibcon#about to read 4, iclass 19, count 0 2006.285.21:35:11.62#ibcon#read 4, iclass 19, count 0 2006.285.21:35:11.62#ibcon#about to read 5, iclass 19, count 0 2006.285.21:35:11.62#ibcon#read 5, iclass 19, count 0 2006.285.21:35:11.62#ibcon#about to read 6, iclass 19, count 0 2006.285.21:35:11.62#ibcon#read 6, iclass 19, count 0 2006.285.21:35:11.62#ibcon#end of sib2, iclass 19, count 0 2006.285.21:35:11.62#ibcon#*after write, iclass 19, count 0 2006.285.21:35:11.62#ibcon#*before return 0, iclass 19, count 0 2006.285.21:35:11.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:35:11.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:35:11.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.21:35:11.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.21:35:11.62$vck44/va=3,7 2006.285.21:35:11.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.21:35:11.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.21:35:11.62#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:11.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:35:11.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:35:11.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:35:11.62#ibcon#enter wrdev, iclass 21, count 2 2006.285.21:35:11.62#ibcon#first serial, iclass 21, count 2 2006.285.21:35:11.62#ibcon#enter sib2, iclass 21, count 2 2006.285.21:35:11.62#ibcon#flushed, iclass 21, count 2 2006.285.21:35:11.62#ibcon#about to write, iclass 21, count 2 2006.285.21:35:11.62#ibcon#wrote, iclass 21, count 2 2006.285.21:35:11.62#ibcon#about to read 3, iclass 21, count 2 2006.285.21:35:11.64#ibcon#read 3, iclass 21, count 2 2006.285.21:35:11.64#ibcon#about to read 4, iclass 21, count 2 2006.285.21:35:11.64#ibcon#read 4, iclass 21, count 2 2006.285.21:35:11.64#ibcon#about to read 5, iclass 21, count 2 2006.285.21:35:11.64#ibcon#read 5, iclass 21, count 2 2006.285.21:35:11.64#ibcon#about to read 6, iclass 21, count 2 2006.285.21:35:11.64#ibcon#read 6, iclass 21, count 2 2006.285.21:35:11.64#ibcon#end of sib2, iclass 21, count 2 2006.285.21:35:11.64#ibcon#*mode == 0, iclass 21, count 2 2006.285.21:35:11.64#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.21:35:11.64#ibcon#[25=AT03-07\r\n] 2006.285.21:35:11.64#ibcon#*before write, iclass 21, count 2 2006.285.21:35:11.64#ibcon#enter sib2, iclass 21, count 2 2006.285.21:35:11.64#ibcon#flushed, iclass 21, count 2 2006.285.21:35:11.64#ibcon#about to write, iclass 21, count 2 2006.285.21:35:11.64#ibcon#wrote, iclass 21, count 2 2006.285.21:35:11.64#ibcon#about to read 3, iclass 21, count 2 2006.285.21:35:11.67#ibcon#read 3, iclass 21, count 2 2006.285.21:35:11.67#ibcon#about to read 4, iclass 21, count 2 2006.285.21:35:11.67#ibcon#read 4, iclass 21, count 2 2006.285.21:35:11.67#ibcon#about to read 5, iclass 21, count 2 2006.285.21:35:11.67#ibcon#read 5, iclass 21, count 2 2006.285.21:35:11.67#ibcon#about to read 6, iclass 21, count 2 2006.285.21:35:11.67#ibcon#read 6, iclass 21, count 2 2006.285.21:35:11.67#ibcon#end of sib2, iclass 21, count 2 2006.285.21:35:11.67#ibcon#*after write, iclass 21, count 2 2006.285.21:35:11.67#ibcon#*before return 0, iclass 21, count 2 2006.285.21:35:11.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:35:11.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:35:11.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.21:35:11.67#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:11.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:35:11.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:35:11.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:35:11.79#ibcon#enter wrdev, iclass 21, count 0 2006.285.21:35:11.79#ibcon#first serial, iclass 21, count 0 2006.285.21:35:11.79#ibcon#enter sib2, iclass 21, count 0 2006.285.21:35:11.79#ibcon#flushed, iclass 21, count 0 2006.285.21:35:11.79#ibcon#about to write, iclass 21, count 0 2006.285.21:35:11.79#ibcon#wrote, iclass 21, count 0 2006.285.21:35:11.79#ibcon#about to read 3, iclass 21, count 0 2006.285.21:35:11.81#ibcon#read 3, iclass 21, count 0 2006.285.21:35:11.81#ibcon#about to read 4, iclass 21, count 0 2006.285.21:35:11.81#ibcon#read 4, iclass 21, count 0 2006.285.21:35:11.81#ibcon#about to read 5, iclass 21, count 0 2006.285.21:35:11.81#ibcon#read 5, iclass 21, count 0 2006.285.21:35:11.81#ibcon#about to read 6, iclass 21, count 0 2006.285.21:35:11.81#ibcon#read 6, iclass 21, count 0 2006.285.21:35:11.81#ibcon#end of sib2, iclass 21, count 0 2006.285.21:35:11.81#ibcon#*mode == 0, iclass 21, count 0 2006.285.21:35:11.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.21:35:11.81#ibcon#[25=USB\r\n] 2006.285.21:35:11.81#ibcon#*before write, iclass 21, count 0 2006.285.21:35:11.81#ibcon#enter sib2, iclass 21, count 0 2006.285.21:35:11.81#ibcon#flushed, iclass 21, count 0 2006.285.21:35:11.81#ibcon#about to write, iclass 21, count 0 2006.285.21:35:11.81#ibcon#wrote, iclass 21, count 0 2006.285.21:35:11.81#ibcon#about to read 3, iclass 21, count 0 2006.285.21:35:11.84#ibcon#read 3, iclass 21, count 0 2006.285.21:35:11.84#ibcon#about to read 4, iclass 21, count 0 2006.285.21:35:11.84#ibcon#read 4, iclass 21, count 0 2006.285.21:35:11.84#ibcon#about to read 5, iclass 21, count 0 2006.285.21:35:11.84#ibcon#read 5, iclass 21, count 0 2006.285.21:35:11.84#ibcon#about to read 6, iclass 21, count 0 2006.285.21:35:11.84#ibcon#read 6, iclass 21, count 0 2006.285.21:35:11.84#ibcon#end of sib2, iclass 21, count 0 2006.285.21:35:11.84#ibcon#*after write, iclass 21, count 0 2006.285.21:35:11.84#ibcon#*before return 0, iclass 21, count 0 2006.285.21:35:11.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:35:11.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:35:11.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.21:35:11.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.21:35:11.84$vck44/valo=4,624.99 2006.285.21:35:11.84#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.21:35:11.84#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.21:35:11.84#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:11.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:35:11.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:35:11.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:35:11.84#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:35:11.84#ibcon#first serial, iclass 23, count 0 2006.285.21:35:11.84#ibcon#enter sib2, iclass 23, count 0 2006.285.21:35:11.84#ibcon#flushed, iclass 23, count 0 2006.285.21:35:11.84#ibcon#about to write, iclass 23, count 0 2006.285.21:35:11.89#ibcon#wrote, iclass 23, count 0 2006.285.21:35:11.89#ibcon#about to read 3, iclass 23, count 0 2006.285.21:35:11.90#ibcon#read 3, iclass 23, count 0 2006.285.21:35:11.90#ibcon#about to read 4, iclass 23, count 0 2006.285.21:35:11.90#ibcon#read 4, iclass 23, count 0 2006.285.21:35:11.90#ibcon#about to read 5, iclass 23, count 0 2006.285.21:35:11.90#ibcon#read 5, iclass 23, count 0 2006.285.21:35:11.90#ibcon#about to read 6, iclass 23, count 0 2006.285.21:35:11.90#ibcon#read 6, iclass 23, count 0 2006.285.21:35:11.90#ibcon#end of sib2, iclass 23, count 0 2006.285.21:35:11.90#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:35:11.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:35:11.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:35:11.90#ibcon#*before write, iclass 23, count 0 2006.285.21:35:11.90#ibcon#enter sib2, iclass 23, count 0 2006.285.21:35:11.90#ibcon#flushed, iclass 23, count 0 2006.285.21:35:11.90#ibcon#about to write, iclass 23, count 0 2006.285.21:35:11.90#ibcon#wrote, iclass 23, count 0 2006.285.21:35:11.90#ibcon#about to read 3, iclass 23, count 0 2006.285.21:35:11.94#ibcon#read 3, iclass 23, count 0 2006.285.21:35:11.94#ibcon#about to read 4, iclass 23, count 0 2006.285.21:35:11.94#ibcon#read 4, iclass 23, count 0 2006.285.21:35:11.94#ibcon#about to read 5, iclass 23, count 0 2006.285.21:35:11.94#ibcon#read 5, iclass 23, count 0 2006.285.21:35:11.94#ibcon#about to read 6, iclass 23, count 0 2006.285.21:35:11.94#ibcon#read 6, iclass 23, count 0 2006.285.21:35:11.94#ibcon#end of sib2, iclass 23, count 0 2006.285.21:35:11.94#ibcon#*after write, iclass 23, count 0 2006.285.21:35:11.94#ibcon#*before return 0, iclass 23, count 0 2006.285.21:35:11.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:35:11.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:35:11.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:35:11.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:35:11.94$vck44/va=4,6 2006.285.21:35:11.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.21:35:11.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.21:35:11.94#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:11.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:35:11.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:35:11.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:35:11.96#ibcon#enter wrdev, iclass 25, count 2 2006.285.21:35:11.96#ibcon#first serial, iclass 25, count 2 2006.285.21:35:11.96#ibcon#enter sib2, iclass 25, count 2 2006.285.21:35:11.96#ibcon#flushed, iclass 25, count 2 2006.285.21:35:11.96#ibcon#about to write, iclass 25, count 2 2006.285.21:35:11.96#ibcon#wrote, iclass 25, count 2 2006.285.21:35:11.96#ibcon#about to read 3, iclass 25, count 2 2006.285.21:35:11.98#ibcon#read 3, iclass 25, count 2 2006.285.21:35:11.98#ibcon#about to read 4, iclass 25, count 2 2006.285.21:35:11.98#ibcon#read 4, iclass 25, count 2 2006.285.21:35:11.98#ibcon#about to read 5, iclass 25, count 2 2006.285.21:35:11.98#ibcon#read 5, iclass 25, count 2 2006.285.21:35:11.98#ibcon#about to read 6, iclass 25, count 2 2006.285.21:35:11.98#ibcon#read 6, iclass 25, count 2 2006.285.21:35:11.98#ibcon#end of sib2, iclass 25, count 2 2006.285.21:35:11.98#ibcon#*mode == 0, iclass 25, count 2 2006.285.21:35:11.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.21:35:11.98#ibcon#[25=AT04-06\r\n] 2006.285.21:35:11.98#ibcon#*before write, iclass 25, count 2 2006.285.21:35:11.98#ibcon#enter sib2, iclass 25, count 2 2006.285.21:35:11.98#ibcon#flushed, iclass 25, count 2 2006.285.21:35:11.98#ibcon#about to write, iclass 25, count 2 2006.285.21:35:11.98#ibcon#wrote, iclass 25, count 2 2006.285.21:35:11.98#ibcon#about to read 3, iclass 25, count 2 2006.285.21:35:12.01#ibcon#read 3, iclass 25, count 2 2006.285.21:35:12.01#ibcon#about to read 4, iclass 25, count 2 2006.285.21:35:12.01#ibcon#read 4, iclass 25, count 2 2006.285.21:35:12.01#ibcon#about to read 5, iclass 25, count 2 2006.285.21:35:12.01#ibcon#read 5, iclass 25, count 2 2006.285.21:35:12.01#ibcon#about to read 6, iclass 25, count 2 2006.285.21:35:12.01#ibcon#read 6, iclass 25, count 2 2006.285.21:35:12.01#ibcon#end of sib2, iclass 25, count 2 2006.285.21:35:12.01#ibcon#*after write, iclass 25, count 2 2006.285.21:35:12.01#ibcon#*before return 0, iclass 25, count 2 2006.285.21:35:12.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:35:12.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:35:12.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.21:35:12.01#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:12.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:35:12.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:35:12.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:35:12.13#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:35:12.13#ibcon#first serial, iclass 25, count 0 2006.285.21:35:12.13#ibcon#enter sib2, iclass 25, count 0 2006.285.21:35:12.13#ibcon#flushed, iclass 25, count 0 2006.285.21:35:12.13#ibcon#about to write, iclass 25, count 0 2006.285.21:35:12.13#ibcon#wrote, iclass 25, count 0 2006.285.21:35:12.13#ibcon#about to read 3, iclass 25, count 0 2006.285.21:35:12.15#ibcon#read 3, iclass 25, count 0 2006.285.21:35:12.15#ibcon#about to read 4, iclass 25, count 0 2006.285.21:35:12.15#ibcon#read 4, iclass 25, count 0 2006.285.21:35:12.15#ibcon#about to read 5, iclass 25, count 0 2006.285.21:35:12.15#ibcon#read 5, iclass 25, count 0 2006.285.21:35:12.15#ibcon#about to read 6, iclass 25, count 0 2006.285.21:35:12.15#ibcon#read 6, iclass 25, count 0 2006.285.21:35:12.15#ibcon#end of sib2, iclass 25, count 0 2006.285.21:35:12.15#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:35:12.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:35:12.15#ibcon#[25=USB\r\n] 2006.285.21:35:12.15#ibcon#*before write, iclass 25, count 0 2006.285.21:35:12.15#ibcon#enter sib2, iclass 25, count 0 2006.285.21:35:12.15#ibcon#flushed, iclass 25, count 0 2006.285.21:35:12.15#ibcon#about to write, iclass 25, count 0 2006.285.21:35:12.15#ibcon#wrote, iclass 25, count 0 2006.285.21:35:12.15#ibcon#about to read 3, iclass 25, count 0 2006.285.21:35:12.18#ibcon#read 3, iclass 25, count 0 2006.285.21:35:12.18#ibcon#about to read 4, iclass 25, count 0 2006.285.21:35:12.18#ibcon#read 4, iclass 25, count 0 2006.285.21:35:12.18#ibcon#about to read 5, iclass 25, count 0 2006.285.21:35:12.18#ibcon#read 5, iclass 25, count 0 2006.285.21:35:12.18#ibcon#about to read 6, iclass 25, count 0 2006.285.21:35:12.18#ibcon#read 6, iclass 25, count 0 2006.285.21:35:12.18#ibcon#end of sib2, iclass 25, count 0 2006.285.21:35:12.18#ibcon#*after write, iclass 25, count 0 2006.285.21:35:12.18#ibcon#*before return 0, iclass 25, count 0 2006.285.21:35:12.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:35:12.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:35:12.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:35:12.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:35:12.18$vck44/valo=5,734.99 2006.285.21:35:12.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.21:35:12.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.21:35:12.18#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:12.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:35:12.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:35:12.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:35:12.18#ibcon#enter wrdev, iclass 27, count 0 2006.285.21:35:12.18#ibcon#first serial, iclass 27, count 0 2006.285.21:35:12.18#ibcon#enter sib2, iclass 27, count 0 2006.285.21:35:12.18#ibcon#flushed, iclass 27, count 0 2006.285.21:35:12.18#ibcon#about to write, iclass 27, count 0 2006.285.21:35:12.18#ibcon#wrote, iclass 27, count 0 2006.285.21:35:12.18#ibcon#about to read 3, iclass 27, count 0 2006.285.21:35:12.20#ibcon#read 3, iclass 27, count 0 2006.285.21:35:12.20#ibcon#about to read 4, iclass 27, count 0 2006.285.21:35:12.20#ibcon#read 4, iclass 27, count 0 2006.285.21:35:12.20#ibcon#about to read 5, iclass 27, count 0 2006.285.21:35:12.20#ibcon#read 5, iclass 27, count 0 2006.285.21:35:12.20#ibcon#about to read 6, iclass 27, count 0 2006.285.21:35:12.20#ibcon#read 6, iclass 27, count 0 2006.285.21:35:12.20#ibcon#end of sib2, iclass 27, count 0 2006.285.21:35:12.20#ibcon#*mode == 0, iclass 27, count 0 2006.285.21:35:12.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.21:35:12.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:35:12.20#ibcon#*before write, iclass 27, count 0 2006.285.21:35:12.20#ibcon#enter sib2, iclass 27, count 0 2006.285.21:35:12.20#ibcon#flushed, iclass 27, count 0 2006.285.21:35:12.20#ibcon#about to write, iclass 27, count 0 2006.285.21:35:12.20#ibcon#wrote, iclass 27, count 0 2006.285.21:35:12.20#ibcon#about to read 3, iclass 27, count 0 2006.285.21:35:12.24#ibcon#read 3, iclass 27, count 0 2006.285.21:35:12.24#ibcon#about to read 4, iclass 27, count 0 2006.285.21:35:12.24#ibcon#read 4, iclass 27, count 0 2006.285.21:35:12.24#ibcon#about to read 5, iclass 27, count 0 2006.285.21:35:12.24#ibcon#read 5, iclass 27, count 0 2006.285.21:35:12.24#ibcon#about to read 6, iclass 27, count 0 2006.285.21:35:12.24#ibcon#read 6, iclass 27, count 0 2006.285.21:35:12.24#ibcon#end of sib2, iclass 27, count 0 2006.285.21:35:12.24#ibcon#*after write, iclass 27, count 0 2006.285.21:35:12.24#ibcon#*before return 0, iclass 27, count 0 2006.285.21:35:12.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:35:12.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:35:12.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.21:35:12.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.21:35:12.24$vck44/va=5,3 2006.285.21:35:12.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.21:35:12.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.21:35:12.24#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:12.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:35:12.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:35:12.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:35:12.30#ibcon#enter wrdev, iclass 29, count 2 2006.285.21:35:12.30#ibcon#first serial, iclass 29, count 2 2006.285.21:35:12.30#ibcon#enter sib2, iclass 29, count 2 2006.285.21:35:12.30#ibcon#flushed, iclass 29, count 2 2006.285.21:35:12.30#ibcon#about to write, iclass 29, count 2 2006.285.21:35:12.30#ibcon#wrote, iclass 29, count 2 2006.285.21:35:12.30#ibcon#about to read 3, iclass 29, count 2 2006.285.21:35:12.32#ibcon#read 3, iclass 29, count 2 2006.285.21:35:12.32#ibcon#about to read 4, iclass 29, count 2 2006.285.21:35:12.32#ibcon#read 4, iclass 29, count 2 2006.285.21:35:12.32#ibcon#about to read 5, iclass 29, count 2 2006.285.21:35:12.32#ibcon#read 5, iclass 29, count 2 2006.285.21:35:12.32#ibcon#about to read 6, iclass 29, count 2 2006.285.21:35:12.32#ibcon#read 6, iclass 29, count 2 2006.285.21:35:12.32#ibcon#end of sib2, iclass 29, count 2 2006.285.21:35:12.32#ibcon#*mode == 0, iclass 29, count 2 2006.285.21:35:12.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.21:35:12.32#ibcon#[25=AT05-03\r\n] 2006.285.21:35:12.32#ibcon#*before write, iclass 29, count 2 2006.285.21:35:12.32#ibcon#enter sib2, iclass 29, count 2 2006.285.21:35:12.32#ibcon#flushed, iclass 29, count 2 2006.285.21:35:12.32#ibcon#about to write, iclass 29, count 2 2006.285.21:35:12.32#ibcon#wrote, iclass 29, count 2 2006.285.21:35:12.32#ibcon#about to read 3, iclass 29, count 2 2006.285.21:35:12.35#ibcon#read 3, iclass 29, count 2 2006.285.21:35:12.35#ibcon#about to read 4, iclass 29, count 2 2006.285.21:35:12.35#ibcon#read 4, iclass 29, count 2 2006.285.21:35:12.35#ibcon#about to read 5, iclass 29, count 2 2006.285.21:35:12.35#ibcon#read 5, iclass 29, count 2 2006.285.21:35:12.35#ibcon#about to read 6, iclass 29, count 2 2006.285.21:35:12.35#ibcon#read 6, iclass 29, count 2 2006.285.21:35:12.35#ibcon#end of sib2, iclass 29, count 2 2006.285.21:35:12.35#ibcon#*after write, iclass 29, count 2 2006.285.21:35:12.35#ibcon#*before return 0, iclass 29, count 2 2006.285.21:35:12.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:35:12.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:35:12.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.21:35:12.35#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:12.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:35:12.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:35:12.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:35:12.47#ibcon#enter wrdev, iclass 29, count 0 2006.285.21:35:12.47#ibcon#first serial, iclass 29, count 0 2006.285.21:35:12.47#ibcon#enter sib2, iclass 29, count 0 2006.285.21:35:12.47#ibcon#flushed, iclass 29, count 0 2006.285.21:35:12.47#ibcon#about to write, iclass 29, count 0 2006.285.21:35:12.47#ibcon#wrote, iclass 29, count 0 2006.285.21:35:12.47#ibcon#about to read 3, iclass 29, count 0 2006.285.21:35:12.49#ibcon#read 3, iclass 29, count 0 2006.285.21:35:12.49#ibcon#about to read 4, iclass 29, count 0 2006.285.21:35:12.49#ibcon#read 4, iclass 29, count 0 2006.285.21:35:12.49#ibcon#about to read 5, iclass 29, count 0 2006.285.21:35:12.49#ibcon#read 5, iclass 29, count 0 2006.285.21:35:12.49#ibcon#about to read 6, iclass 29, count 0 2006.285.21:35:12.49#ibcon#read 6, iclass 29, count 0 2006.285.21:35:12.49#ibcon#end of sib2, iclass 29, count 0 2006.285.21:35:12.49#ibcon#*mode == 0, iclass 29, count 0 2006.285.21:35:12.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.21:35:12.49#ibcon#[25=USB\r\n] 2006.285.21:35:12.49#ibcon#*before write, iclass 29, count 0 2006.285.21:35:12.49#ibcon#enter sib2, iclass 29, count 0 2006.285.21:35:12.49#ibcon#flushed, iclass 29, count 0 2006.285.21:35:12.49#ibcon#about to write, iclass 29, count 0 2006.285.21:35:12.49#ibcon#wrote, iclass 29, count 0 2006.285.21:35:12.49#ibcon#about to read 3, iclass 29, count 0 2006.285.21:35:12.52#ibcon#read 3, iclass 29, count 0 2006.285.21:35:12.52#ibcon#about to read 4, iclass 29, count 0 2006.285.21:35:12.52#ibcon#read 4, iclass 29, count 0 2006.285.21:35:12.52#ibcon#about to read 5, iclass 29, count 0 2006.285.21:35:12.52#ibcon#read 5, iclass 29, count 0 2006.285.21:35:12.52#ibcon#about to read 6, iclass 29, count 0 2006.285.21:35:12.52#ibcon#read 6, iclass 29, count 0 2006.285.21:35:12.52#ibcon#end of sib2, iclass 29, count 0 2006.285.21:35:12.52#ibcon#*after write, iclass 29, count 0 2006.285.21:35:12.52#ibcon#*before return 0, iclass 29, count 0 2006.285.21:35:12.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:35:12.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:35:12.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.21:35:12.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.21:35:12.52$vck44/valo=6,814.99 2006.285.21:35:12.52#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.21:35:12.52#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.21:35:12.52#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:12.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:35:12.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:35:12.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:35:12.52#ibcon#enter wrdev, iclass 31, count 0 2006.285.21:35:12.52#ibcon#first serial, iclass 31, count 0 2006.285.21:35:12.52#ibcon#enter sib2, iclass 31, count 0 2006.285.21:35:12.52#ibcon#flushed, iclass 31, count 0 2006.285.21:35:12.52#ibcon#about to write, iclass 31, count 0 2006.285.21:35:12.52#ibcon#wrote, iclass 31, count 0 2006.285.21:35:12.52#ibcon#about to read 3, iclass 31, count 0 2006.285.21:35:12.54#ibcon#read 3, iclass 31, count 0 2006.285.21:35:12.54#ibcon#about to read 4, iclass 31, count 0 2006.285.21:35:12.54#ibcon#read 4, iclass 31, count 0 2006.285.21:35:12.54#ibcon#about to read 5, iclass 31, count 0 2006.285.21:35:12.54#ibcon#read 5, iclass 31, count 0 2006.285.21:35:12.54#ibcon#about to read 6, iclass 31, count 0 2006.285.21:35:12.54#ibcon#read 6, iclass 31, count 0 2006.285.21:35:12.54#ibcon#end of sib2, iclass 31, count 0 2006.285.21:35:12.54#ibcon#*mode == 0, iclass 31, count 0 2006.285.21:35:12.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.21:35:12.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:35:12.54#ibcon#*before write, iclass 31, count 0 2006.285.21:35:12.54#ibcon#enter sib2, iclass 31, count 0 2006.285.21:35:12.54#ibcon#flushed, iclass 31, count 0 2006.285.21:35:12.54#ibcon#about to write, iclass 31, count 0 2006.285.21:35:12.54#ibcon#wrote, iclass 31, count 0 2006.285.21:35:12.54#ibcon#about to read 3, iclass 31, count 0 2006.285.21:35:12.58#ibcon#read 3, iclass 31, count 0 2006.285.21:35:12.58#ibcon#about to read 4, iclass 31, count 0 2006.285.21:35:12.58#ibcon#read 4, iclass 31, count 0 2006.285.21:35:12.58#ibcon#about to read 5, iclass 31, count 0 2006.285.21:35:12.58#ibcon#read 5, iclass 31, count 0 2006.285.21:35:12.58#ibcon#about to read 6, iclass 31, count 0 2006.285.21:35:12.58#ibcon#read 6, iclass 31, count 0 2006.285.21:35:12.58#ibcon#end of sib2, iclass 31, count 0 2006.285.21:35:12.58#ibcon#*after write, iclass 31, count 0 2006.285.21:35:12.58#ibcon#*before return 0, iclass 31, count 0 2006.285.21:35:12.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:35:12.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:35:12.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.21:35:12.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.21:35:12.58$vck44/va=6,4 2006.285.21:35:12.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.21:35:12.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.21:35:12.58#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:12.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:35:12.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:35:12.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:35:12.64#ibcon#enter wrdev, iclass 33, count 2 2006.285.21:35:12.64#ibcon#first serial, iclass 33, count 2 2006.285.21:35:12.64#ibcon#enter sib2, iclass 33, count 2 2006.285.21:35:12.64#ibcon#flushed, iclass 33, count 2 2006.285.21:35:12.64#ibcon#about to write, iclass 33, count 2 2006.285.21:35:12.64#ibcon#wrote, iclass 33, count 2 2006.285.21:35:12.64#ibcon#about to read 3, iclass 33, count 2 2006.285.21:35:12.66#ibcon#read 3, iclass 33, count 2 2006.285.21:35:12.66#ibcon#about to read 4, iclass 33, count 2 2006.285.21:35:12.66#ibcon#read 4, iclass 33, count 2 2006.285.21:35:12.66#ibcon#about to read 5, iclass 33, count 2 2006.285.21:35:12.66#ibcon#read 5, iclass 33, count 2 2006.285.21:35:12.66#ibcon#about to read 6, iclass 33, count 2 2006.285.21:35:12.66#ibcon#read 6, iclass 33, count 2 2006.285.21:35:12.66#ibcon#end of sib2, iclass 33, count 2 2006.285.21:35:12.66#ibcon#*mode == 0, iclass 33, count 2 2006.285.21:35:12.66#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.21:35:12.66#ibcon#[25=AT06-04\r\n] 2006.285.21:35:12.66#ibcon#*before write, iclass 33, count 2 2006.285.21:35:12.66#ibcon#enter sib2, iclass 33, count 2 2006.285.21:35:12.66#ibcon#flushed, iclass 33, count 2 2006.285.21:35:12.66#ibcon#about to write, iclass 33, count 2 2006.285.21:35:12.66#ibcon#wrote, iclass 33, count 2 2006.285.21:35:12.66#ibcon#about to read 3, iclass 33, count 2 2006.285.21:35:12.69#ibcon#read 3, iclass 33, count 2 2006.285.21:35:12.69#ibcon#about to read 4, iclass 33, count 2 2006.285.21:35:12.69#ibcon#read 4, iclass 33, count 2 2006.285.21:35:12.69#ibcon#about to read 5, iclass 33, count 2 2006.285.21:35:12.69#ibcon#read 5, iclass 33, count 2 2006.285.21:35:12.69#ibcon#about to read 6, iclass 33, count 2 2006.285.21:35:12.69#ibcon#read 6, iclass 33, count 2 2006.285.21:35:12.69#ibcon#end of sib2, iclass 33, count 2 2006.285.21:35:12.69#ibcon#*after write, iclass 33, count 2 2006.285.21:35:12.69#ibcon#*before return 0, iclass 33, count 2 2006.285.21:35:12.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:35:12.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:35:12.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.21:35:12.69#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:12.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:35:12.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:35:12.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:35:12.81#ibcon#enter wrdev, iclass 33, count 0 2006.285.21:35:12.81#ibcon#first serial, iclass 33, count 0 2006.285.21:35:12.81#ibcon#enter sib2, iclass 33, count 0 2006.285.21:35:12.81#ibcon#flushed, iclass 33, count 0 2006.285.21:35:12.81#ibcon#about to write, iclass 33, count 0 2006.285.21:35:12.81#ibcon#wrote, iclass 33, count 0 2006.285.21:35:12.81#ibcon#about to read 3, iclass 33, count 0 2006.285.21:35:12.83#ibcon#read 3, iclass 33, count 0 2006.285.21:35:12.83#ibcon#about to read 4, iclass 33, count 0 2006.285.21:35:12.83#ibcon#read 4, iclass 33, count 0 2006.285.21:35:12.83#ibcon#about to read 5, iclass 33, count 0 2006.285.21:35:12.83#ibcon#read 5, iclass 33, count 0 2006.285.21:35:12.83#ibcon#about to read 6, iclass 33, count 0 2006.285.21:35:12.83#ibcon#read 6, iclass 33, count 0 2006.285.21:35:12.83#ibcon#end of sib2, iclass 33, count 0 2006.285.21:35:12.83#ibcon#*mode == 0, iclass 33, count 0 2006.285.21:35:12.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.21:35:12.83#ibcon#[25=USB\r\n] 2006.285.21:35:12.83#ibcon#*before write, iclass 33, count 0 2006.285.21:35:12.83#ibcon#enter sib2, iclass 33, count 0 2006.285.21:35:12.83#ibcon#flushed, iclass 33, count 0 2006.285.21:35:12.83#ibcon#about to write, iclass 33, count 0 2006.285.21:35:12.83#ibcon#wrote, iclass 33, count 0 2006.285.21:35:12.83#ibcon#about to read 3, iclass 33, count 0 2006.285.21:35:12.86#ibcon#read 3, iclass 33, count 0 2006.285.21:35:12.86#ibcon#about to read 4, iclass 33, count 0 2006.285.21:35:12.86#ibcon#read 4, iclass 33, count 0 2006.285.21:35:12.86#ibcon#about to read 5, iclass 33, count 0 2006.285.21:35:12.86#ibcon#read 5, iclass 33, count 0 2006.285.21:35:12.86#ibcon#about to read 6, iclass 33, count 0 2006.285.21:35:12.86#ibcon#read 6, iclass 33, count 0 2006.285.21:35:12.86#ibcon#end of sib2, iclass 33, count 0 2006.285.21:35:12.86#ibcon#*after write, iclass 33, count 0 2006.285.21:35:12.86#ibcon#*before return 0, iclass 33, count 0 2006.285.21:35:12.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:35:12.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:35:12.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.21:35:12.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.21:35:12.86$vck44/valo=7,864.99 2006.285.21:35:12.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.21:35:12.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.21:35:12.86#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:12.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:35:12.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:35:12.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:35:12.86#ibcon#enter wrdev, iclass 35, count 0 2006.285.21:35:12.86#ibcon#first serial, iclass 35, count 0 2006.285.21:35:12.86#ibcon#enter sib2, iclass 35, count 0 2006.285.21:35:12.86#ibcon#flushed, iclass 35, count 0 2006.285.21:35:12.86#ibcon#about to write, iclass 35, count 0 2006.285.21:35:12.86#ibcon#wrote, iclass 35, count 0 2006.285.21:35:12.86#ibcon#about to read 3, iclass 35, count 0 2006.285.21:35:12.88#ibcon#read 3, iclass 35, count 0 2006.285.21:35:12.94#ibcon#about to read 4, iclass 35, count 0 2006.285.21:35:12.94#ibcon#read 4, iclass 35, count 0 2006.285.21:35:12.94#ibcon#about to read 5, iclass 35, count 0 2006.285.21:35:12.94#ibcon#read 5, iclass 35, count 0 2006.285.21:35:12.94#ibcon#about to read 6, iclass 35, count 0 2006.285.21:35:12.94#ibcon#read 6, iclass 35, count 0 2006.285.21:35:12.94#ibcon#end of sib2, iclass 35, count 0 2006.285.21:35:12.94#ibcon#*mode == 0, iclass 35, count 0 2006.285.21:35:12.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.21:35:12.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:35:12.94#ibcon#*before write, iclass 35, count 0 2006.285.21:35:12.94#ibcon#enter sib2, iclass 35, count 0 2006.285.21:35:12.94#ibcon#flushed, iclass 35, count 0 2006.285.21:35:12.94#ibcon#about to write, iclass 35, count 0 2006.285.21:35:12.94#ibcon#wrote, iclass 35, count 0 2006.285.21:35:12.94#ibcon#about to read 3, iclass 35, count 0 2006.285.21:35:12.98#ibcon#read 3, iclass 35, count 0 2006.285.21:35:12.98#ibcon#about to read 4, iclass 35, count 0 2006.285.21:35:12.98#ibcon#read 4, iclass 35, count 0 2006.285.21:35:12.98#ibcon#about to read 5, iclass 35, count 0 2006.285.21:35:12.98#ibcon#read 5, iclass 35, count 0 2006.285.21:35:12.98#ibcon#about to read 6, iclass 35, count 0 2006.285.21:35:12.98#ibcon#read 6, iclass 35, count 0 2006.285.21:35:12.98#ibcon#end of sib2, iclass 35, count 0 2006.285.21:35:12.98#ibcon#*after write, iclass 35, count 0 2006.285.21:35:12.98#ibcon#*before return 0, iclass 35, count 0 2006.285.21:35:12.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:35:12.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:35:12.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.21:35:12.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.21:35:12.98$vck44/va=7,4 2006.285.21:35:12.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.21:35:12.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.21:35:12.98#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:12.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:35:12.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:35:12.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:35:12.98#ibcon#enter wrdev, iclass 37, count 2 2006.285.21:35:12.98#ibcon#first serial, iclass 37, count 2 2006.285.21:35:12.98#ibcon#enter sib2, iclass 37, count 2 2006.285.21:35:12.98#ibcon#flushed, iclass 37, count 2 2006.285.21:35:12.98#ibcon#about to write, iclass 37, count 2 2006.285.21:35:12.98#ibcon#wrote, iclass 37, count 2 2006.285.21:35:12.98#ibcon#about to read 3, iclass 37, count 2 2006.285.21:35:13.00#ibcon#read 3, iclass 37, count 2 2006.285.21:35:13.00#ibcon#about to read 4, iclass 37, count 2 2006.285.21:35:13.00#ibcon#read 4, iclass 37, count 2 2006.285.21:35:13.00#ibcon#about to read 5, iclass 37, count 2 2006.285.21:35:13.00#ibcon#read 5, iclass 37, count 2 2006.285.21:35:13.00#ibcon#about to read 6, iclass 37, count 2 2006.285.21:35:13.00#ibcon#read 6, iclass 37, count 2 2006.285.21:35:13.00#ibcon#end of sib2, iclass 37, count 2 2006.285.21:35:13.00#ibcon#*mode == 0, iclass 37, count 2 2006.285.21:35:13.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.21:35:13.00#ibcon#[25=AT07-04\r\n] 2006.285.21:35:13.00#ibcon#*before write, iclass 37, count 2 2006.285.21:35:13.00#ibcon#enter sib2, iclass 37, count 2 2006.285.21:35:13.00#ibcon#flushed, iclass 37, count 2 2006.285.21:35:13.00#ibcon#about to write, iclass 37, count 2 2006.285.21:35:13.00#ibcon#wrote, iclass 37, count 2 2006.285.21:35:13.00#ibcon#about to read 3, iclass 37, count 2 2006.285.21:35:13.03#ibcon#read 3, iclass 37, count 2 2006.285.21:35:13.03#ibcon#about to read 4, iclass 37, count 2 2006.285.21:35:13.03#ibcon#read 4, iclass 37, count 2 2006.285.21:35:13.03#ibcon#about to read 5, iclass 37, count 2 2006.285.21:35:13.03#ibcon#read 5, iclass 37, count 2 2006.285.21:35:13.03#ibcon#about to read 6, iclass 37, count 2 2006.285.21:35:13.03#ibcon#read 6, iclass 37, count 2 2006.285.21:35:13.03#ibcon#end of sib2, iclass 37, count 2 2006.285.21:35:13.03#ibcon#*after write, iclass 37, count 2 2006.285.21:35:13.03#ibcon#*before return 0, iclass 37, count 2 2006.285.21:35:13.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:35:13.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:35:13.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.21:35:13.03#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:13.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:35:13.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:35:13.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:35:13.15#ibcon#enter wrdev, iclass 37, count 0 2006.285.21:35:13.15#ibcon#first serial, iclass 37, count 0 2006.285.21:35:13.15#ibcon#enter sib2, iclass 37, count 0 2006.285.21:35:13.15#ibcon#flushed, iclass 37, count 0 2006.285.21:35:13.15#ibcon#about to write, iclass 37, count 0 2006.285.21:35:13.15#ibcon#wrote, iclass 37, count 0 2006.285.21:35:13.15#ibcon#about to read 3, iclass 37, count 0 2006.285.21:35:13.17#ibcon#read 3, iclass 37, count 0 2006.285.21:35:13.17#ibcon#about to read 4, iclass 37, count 0 2006.285.21:35:13.17#ibcon#read 4, iclass 37, count 0 2006.285.21:35:13.17#ibcon#about to read 5, iclass 37, count 0 2006.285.21:35:13.17#ibcon#read 5, iclass 37, count 0 2006.285.21:35:13.17#ibcon#about to read 6, iclass 37, count 0 2006.285.21:35:13.17#ibcon#read 6, iclass 37, count 0 2006.285.21:35:13.17#ibcon#end of sib2, iclass 37, count 0 2006.285.21:35:13.17#ibcon#*mode == 0, iclass 37, count 0 2006.285.21:35:13.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.21:35:13.17#ibcon#[25=USB\r\n] 2006.285.21:35:13.17#ibcon#*before write, iclass 37, count 0 2006.285.21:35:13.17#ibcon#enter sib2, iclass 37, count 0 2006.285.21:35:13.17#ibcon#flushed, iclass 37, count 0 2006.285.21:35:13.17#ibcon#about to write, iclass 37, count 0 2006.285.21:35:13.17#ibcon#wrote, iclass 37, count 0 2006.285.21:35:13.17#ibcon#about to read 3, iclass 37, count 0 2006.285.21:35:13.20#ibcon#read 3, iclass 37, count 0 2006.285.21:35:13.20#ibcon#about to read 4, iclass 37, count 0 2006.285.21:35:13.20#ibcon#read 4, iclass 37, count 0 2006.285.21:35:13.20#ibcon#about to read 5, iclass 37, count 0 2006.285.21:35:13.20#ibcon#read 5, iclass 37, count 0 2006.285.21:35:13.20#ibcon#about to read 6, iclass 37, count 0 2006.285.21:35:13.20#ibcon#read 6, iclass 37, count 0 2006.285.21:35:13.20#ibcon#end of sib2, iclass 37, count 0 2006.285.21:35:13.20#ibcon#*after write, iclass 37, count 0 2006.285.21:35:13.20#ibcon#*before return 0, iclass 37, count 0 2006.285.21:35:13.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:35:13.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:35:13.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.21:35:13.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.21:35:13.20$vck44/valo=8,884.99 2006.285.21:35:13.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.21:35:13.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.21:35:13.20#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:13.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:35:13.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:35:13.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:35:13.20#ibcon#enter wrdev, iclass 39, count 0 2006.285.21:35:13.20#ibcon#first serial, iclass 39, count 0 2006.285.21:35:13.20#ibcon#enter sib2, iclass 39, count 0 2006.285.21:35:13.20#ibcon#flushed, iclass 39, count 0 2006.285.21:35:13.20#ibcon#about to write, iclass 39, count 0 2006.285.21:35:13.20#ibcon#wrote, iclass 39, count 0 2006.285.21:35:13.20#ibcon#about to read 3, iclass 39, count 0 2006.285.21:35:13.22#ibcon#read 3, iclass 39, count 0 2006.285.21:35:13.22#ibcon#about to read 4, iclass 39, count 0 2006.285.21:35:13.22#ibcon#read 4, iclass 39, count 0 2006.285.21:35:13.22#ibcon#about to read 5, iclass 39, count 0 2006.285.21:35:13.22#ibcon#read 5, iclass 39, count 0 2006.285.21:35:13.22#ibcon#about to read 6, iclass 39, count 0 2006.285.21:35:13.22#ibcon#read 6, iclass 39, count 0 2006.285.21:35:13.22#ibcon#end of sib2, iclass 39, count 0 2006.285.21:35:13.22#ibcon#*mode == 0, iclass 39, count 0 2006.285.21:35:13.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.21:35:13.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:35:13.22#ibcon#*before write, iclass 39, count 0 2006.285.21:35:13.22#ibcon#enter sib2, iclass 39, count 0 2006.285.21:35:13.22#ibcon#flushed, iclass 39, count 0 2006.285.21:35:13.22#ibcon#about to write, iclass 39, count 0 2006.285.21:35:13.22#ibcon#wrote, iclass 39, count 0 2006.285.21:35:13.22#ibcon#about to read 3, iclass 39, count 0 2006.285.21:35:13.26#ibcon#read 3, iclass 39, count 0 2006.285.21:35:13.26#ibcon#about to read 4, iclass 39, count 0 2006.285.21:35:13.26#ibcon#read 4, iclass 39, count 0 2006.285.21:35:13.26#ibcon#about to read 5, iclass 39, count 0 2006.285.21:35:13.26#ibcon#read 5, iclass 39, count 0 2006.285.21:35:13.26#ibcon#about to read 6, iclass 39, count 0 2006.285.21:35:13.26#ibcon#read 6, iclass 39, count 0 2006.285.21:35:13.26#ibcon#end of sib2, iclass 39, count 0 2006.285.21:35:13.26#ibcon#*after write, iclass 39, count 0 2006.285.21:35:13.26#ibcon#*before return 0, iclass 39, count 0 2006.285.21:35:13.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:35:13.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:35:13.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.21:35:13.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.21:35:13.26$vck44/va=8,3 2006.285.21:35:13.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.21:35:13.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.21:35:13.26#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:13.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:35:13.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:35:13.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:35:13.32#ibcon#enter wrdev, iclass 3, count 2 2006.285.21:35:13.32#ibcon#first serial, iclass 3, count 2 2006.285.21:35:13.32#ibcon#enter sib2, iclass 3, count 2 2006.285.21:35:13.32#ibcon#flushed, iclass 3, count 2 2006.285.21:35:13.32#ibcon#about to write, iclass 3, count 2 2006.285.21:35:13.32#ibcon#wrote, iclass 3, count 2 2006.285.21:35:13.32#ibcon#about to read 3, iclass 3, count 2 2006.285.21:35:13.34#ibcon#read 3, iclass 3, count 2 2006.285.21:35:13.34#ibcon#about to read 4, iclass 3, count 2 2006.285.21:35:13.34#ibcon#read 4, iclass 3, count 2 2006.285.21:35:13.34#ibcon#about to read 5, iclass 3, count 2 2006.285.21:35:13.34#ibcon#read 5, iclass 3, count 2 2006.285.21:35:13.34#ibcon#about to read 6, iclass 3, count 2 2006.285.21:35:13.34#ibcon#read 6, iclass 3, count 2 2006.285.21:35:13.34#ibcon#end of sib2, iclass 3, count 2 2006.285.21:35:13.34#ibcon#*mode == 0, iclass 3, count 2 2006.285.21:35:13.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.21:35:13.34#ibcon#[25=AT08-03\r\n] 2006.285.21:35:13.34#ibcon#*before write, iclass 3, count 2 2006.285.21:35:13.34#ibcon#enter sib2, iclass 3, count 2 2006.285.21:35:13.34#ibcon#flushed, iclass 3, count 2 2006.285.21:35:13.34#ibcon#about to write, iclass 3, count 2 2006.285.21:35:13.34#ibcon#wrote, iclass 3, count 2 2006.285.21:35:13.34#ibcon#about to read 3, iclass 3, count 2 2006.285.21:35:13.37#ibcon#read 3, iclass 3, count 2 2006.285.21:35:13.37#ibcon#about to read 4, iclass 3, count 2 2006.285.21:35:13.37#ibcon#read 4, iclass 3, count 2 2006.285.21:35:13.37#ibcon#about to read 5, iclass 3, count 2 2006.285.21:35:13.37#ibcon#read 5, iclass 3, count 2 2006.285.21:35:13.37#ibcon#about to read 6, iclass 3, count 2 2006.285.21:35:13.37#ibcon#read 6, iclass 3, count 2 2006.285.21:35:13.37#ibcon#end of sib2, iclass 3, count 2 2006.285.21:35:13.37#ibcon#*after write, iclass 3, count 2 2006.285.21:35:13.37#ibcon#*before return 0, iclass 3, count 2 2006.285.21:35:13.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:35:13.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.21:35:13.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.21:35:13.37#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:13.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:35:13.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:35:13.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:35:13.49#ibcon#enter wrdev, iclass 3, count 0 2006.285.21:35:13.49#ibcon#first serial, iclass 3, count 0 2006.285.21:35:13.49#ibcon#enter sib2, iclass 3, count 0 2006.285.21:35:13.49#ibcon#flushed, iclass 3, count 0 2006.285.21:35:13.49#ibcon#about to write, iclass 3, count 0 2006.285.21:35:13.49#ibcon#wrote, iclass 3, count 0 2006.285.21:35:13.49#ibcon#about to read 3, iclass 3, count 0 2006.285.21:35:13.51#ibcon#read 3, iclass 3, count 0 2006.285.21:35:13.51#ibcon#about to read 4, iclass 3, count 0 2006.285.21:35:13.51#ibcon#read 4, iclass 3, count 0 2006.285.21:35:13.51#ibcon#about to read 5, iclass 3, count 0 2006.285.21:35:13.51#ibcon#read 5, iclass 3, count 0 2006.285.21:35:13.51#ibcon#about to read 6, iclass 3, count 0 2006.285.21:35:13.51#ibcon#read 6, iclass 3, count 0 2006.285.21:35:13.51#ibcon#end of sib2, iclass 3, count 0 2006.285.21:35:13.51#ibcon#*mode == 0, iclass 3, count 0 2006.285.21:35:13.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.21:35:13.51#ibcon#[25=USB\r\n] 2006.285.21:35:13.51#ibcon#*before write, iclass 3, count 0 2006.285.21:35:13.51#ibcon#enter sib2, iclass 3, count 0 2006.285.21:35:13.51#ibcon#flushed, iclass 3, count 0 2006.285.21:35:13.51#ibcon#about to write, iclass 3, count 0 2006.285.21:35:13.51#ibcon#wrote, iclass 3, count 0 2006.285.21:35:13.51#ibcon#about to read 3, iclass 3, count 0 2006.285.21:35:13.54#ibcon#read 3, iclass 3, count 0 2006.285.21:35:13.54#ibcon#about to read 4, iclass 3, count 0 2006.285.21:35:13.54#ibcon#read 4, iclass 3, count 0 2006.285.21:35:13.54#ibcon#about to read 5, iclass 3, count 0 2006.285.21:35:13.54#ibcon#read 5, iclass 3, count 0 2006.285.21:35:13.54#ibcon#about to read 6, iclass 3, count 0 2006.285.21:35:13.54#ibcon#read 6, iclass 3, count 0 2006.285.21:35:13.54#ibcon#end of sib2, iclass 3, count 0 2006.285.21:35:13.54#ibcon#*after write, iclass 3, count 0 2006.285.21:35:13.54#ibcon#*before return 0, iclass 3, count 0 2006.285.21:35:13.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:35:13.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.21:35:13.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.21:35:13.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.21:35:13.54$vck44/vblo=1,629.99 2006.285.21:35:13.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.21:35:13.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.21:35:13.54#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:13.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:35:13.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:35:13.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:35:13.54#ibcon#enter wrdev, iclass 5, count 0 2006.285.21:35:13.54#ibcon#first serial, iclass 5, count 0 2006.285.21:35:13.54#ibcon#enter sib2, iclass 5, count 0 2006.285.21:35:13.54#ibcon#flushed, iclass 5, count 0 2006.285.21:35:13.54#ibcon#about to write, iclass 5, count 0 2006.285.21:35:13.54#ibcon#wrote, iclass 5, count 0 2006.285.21:35:13.54#ibcon#about to read 3, iclass 5, count 0 2006.285.21:35:13.56#ibcon#read 3, iclass 5, count 0 2006.285.21:35:13.56#ibcon#about to read 4, iclass 5, count 0 2006.285.21:35:13.56#ibcon#read 4, iclass 5, count 0 2006.285.21:35:13.56#ibcon#about to read 5, iclass 5, count 0 2006.285.21:35:13.56#ibcon#read 5, iclass 5, count 0 2006.285.21:35:13.56#ibcon#about to read 6, iclass 5, count 0 2006.285.21:35:13.56#ibcon#read 6, iclass 5, count 0 2006.285.21:35:13.56#ibcon#end of sib2, iclass 5, count 0 2006.285.21:35:13.56#ibcon#*mode == 0, iclass 5, count 0 2006.285.21:35:13.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.21:35:13.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:35:13.56#ibcon#*before write, iclass 5, count 0 2006.285.21:35:13.56#ibcon#enter sib2, iclass 5, count 0 2006.285.21:35:13.56#ibcon#flushed, iclass 5, count 0 2006.285.21:35:13.56#ibcon#about to write, iclass 5, count 0 2006.285.21:35:13.56#ibcon#wrote, iclass 5, count 0 2006.285.21:35:13.56#ibcon#about to read 3, iclass 5, count 0 2006.285.21:35:13.60#ibcon#read 3, iclass 5, count 0 2006.285.21:35:13.60#ibcon#about to read 4, iclass 5, count 0 2006.285.21:35:13.60#ibcon#read 4, iclass 5, count 0 2006.285.21:35:13.60#ibcon#about to read 5, iclass 5, count 0 2006.285.21:35:13.60#ibcon#read 5, iclass 5, count 0 2006.285.21:35:13.60#ibcon#about to read 6, iclass 5, count 0 2006.285.21:35:13.60#ibcon#read 6, iclass 5, count 0 2006.285.21:35:13.60#ibcon#end of sib2, iclass 5, count 0 2006.285.21:35:13.60#ibcon#*after write, iclass 5, count 0 2006.285.21:35:13.60#ibcon#*before return 0, iclass 5, count 0 2006.285.21:35:13.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:35:13.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.21:35:13.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.21:35:13.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.21:35:13.60$vck44/vb=1,4 2006.285.21:35:13.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.21:35:13.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.21:35:13.60#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:13.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:35:13.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:35:13.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:35:13.60#ibcon#enter wrdev, iclass 7, count 2 2006.285.21:35:13.60#ibcon#first serial, iclass 7, count 2 2006.285.21:35:13.60#ibcon#enter sib2, iclass 7, count 2 2006.285.21:35:13.60#ibcon#flushed, iclass 7, count 2 2006.285.21:35:13.60#ibcon#about to write, iclass 7, count 2 2006.285.21:35:13.60#ibcon#wrote, iclass 7, count 2 2006.285.21:35:13.60#ibcon#about to read 3, iclass 7, count 2 2006.285.21:35:13.62#ibcon#read 3, iclass 7, count 2 2006.285.21:35:13.62#ibcon#about to read 4, iclass 7, count 2 2006.285.21:35:13.62#ibcon#read 4, iclass 7, count 2 2006.285.21:35:13.62#ibcon#about to read 5, iclass 7, count 2 2006.285.21:35:13.62#ibcon#read 5, iclass 7, count 2 2006.285.21:35:13.62#ibcon#about to read 6, iclass 7, count 2 2006.285.21:35:13.62#ibcon#read 6, iclass 7, count 2 2006.285.21:35:13.62#ibcon#end of sib2, iclass 7, count 2 2006.285.21:35:13.62#ibcon#*mode == 0, iclass 7, count 2 2006.285.21:35:13.62#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.21:35:13.62#ibcon#[27=AT01-04\r\n] 2006.285.21:35:13.62#ibcon#*before write, iclass 7, count 2 2006.285.21:35:13.62#ibcon#enter sib2, iclass 7, count 2 2006.285.21:35:13.62#ibcon#flushed, iclass 7, count 2 2006.285.21:35:13.62#ibcon#about to write, iclass 7, count 2 2006.285.21:35:13.62#ibcon#wrote, iclass 7, count 2 2006.285.21:35:13.62#ibcon#about to read 3, iclass 7, count 2 2006.285.21:35:13.65#ibcon#read 3, iclass 7, count 2 2006.285.21:35:13.65#ibcon#about to read 4, iclass 7, count 2 2006.285.21:35:13.65#ibcon#read 4, iclass 7, count 2 2006.285.21:35:13.65#ibcon#about to read 5, iclass 7, count 2 2006.285.21:35:13.65#ibcon#read 5, iclass 7, count 2 2006.285.21:35:13.65#ibcon#about to read 6, iclass 7, count 2 2006.285.21:35:13.65#ibcon#read 6, iclass 7, count 2 2006.285.21:35:13.65#ibcon#end of sib2, iclass 7, count 2 2006.285.21:35:13.65#ibcon#*after write, iclass 7, count 2 2006.285.21:35:13.65#ibcon#*before return 0, iclass 7, count 2 2006.285.21:35:13.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:35:13.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.21:35:13.65#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.21:35:13.65#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:13.65#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:35:13.77#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:35:13.77#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:35:13.77#ibcon#enter wrdev, iclass 7, count 0 2006.285.21:35:13.77#ibcon#first serial, iclass 7, count 0 2006.285.21:35:13.77#ibcon#enter sib2, iclass 7, count 0 2006.285.21:35:13.77#ibcon#flushed, iclass 7, count 0 2006.285.21:35:13.77#ibcon#about to write, iclass 7, count 0 2006.285.21:35:13.77#ibcon#wrote, iclass 7, count 0 2006.285.21:35:13.77#ibcon#about to read 3, iclass 7, count 0 2006.285.21:35:13.79#ibcon#read 3, iclass 7, count 0 2006.285.21:35:13.79#ibcon#about to read 4, iclass 7, count 0 2006.285.21:35:13.79#ibcon#read 4, iclass 7, count 0 2006.285.21:35:13.79#ibcon#about to read 5, iclass 7, count 0 2006.285.21:35:13.79#ibcon#read 5, iclass 7, count 0 2006.285.21:35:13.79#ibcon#about to read 6, iclass 7, count 0 2006.285.21:35:13.79#ibcon#read 6, iclass 7, count 0 2006.285.21:35:13.79#ibcon#end of sib2, iclass 7, count 0 2006.285.21:35:13.79#ibcon#*mode == 0, iclass 7, count 0 2006.285.21:35:13.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.21:35:13.79#ibcon#[27=USB\r\n] 2006.285.21:35:13.79#ibcon#*before write, iclass 7, count 0 2006.285.21:35:13.79#ibcon#enter sib2, iclass 7, count 0 2006.285.21:35:13.79#ibcon#flushed, iclass 7, count 0 2006.285.21:35:13.79#ibcon#about to write, iclass 7, count 0 2006.285.21:35:13.79#ibcon#wrote, iclass 7, count 0 2006.285.21:35:13.79#ibcon#about to read 3, iclass 7, count 0 2006.285.21:35:13.82#ibcon#read 3, iclass 7, count 0 2006.285.21:35:13.82#ibcon#about to read 4, iclass 7, count 0 2006.285.21:35:13.82#ibcon#read 4, iclass 7, count 0 2006.285.21:35:13.82#ibcon#about to read 5, iclass 7, count 0 2006.285.21:35:13.82#ibcon#read 5, iclass 7, count 0 2006.285.21:35:13.82#ibcon#about to read 6, iclass 7, count 0 2006.285.21:35:13.82#ibcon#read 6, iclass 7, count 0 2006.285.21:35:13.82#ibcon#end of sib2, iclass 7, count 0 2006.285.21:35:13.82#ibcon#*after write, iclass 7, count 0 2006.285.21:35:13.82#ibcon#*before return 0, iclass 7, count 0 2006.285.21:35:13.82#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:35:13.82#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.21:35:13.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.21:35:13.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.21:35:13.82$vck44/vblo=2,634.99 2006.285.21:35:13.82#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.21:35:13.82#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.21:35:13.82#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:13.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:35:13.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:35:13.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:35:13.82#ibcon#enter wrdev, iclass 11, count 0 2006.285.21:35:13.82#ibcon#first serial, iclass 11, count 0 2006.285.21:35:13.82#ibcon#enter sib2, iclass 11, count 0 2006.285.21:35:13.82#ibcon#flushed, iclass 11, count 0 2006.285.21:35:13.82#ibcon#about to write, iclass 11, count 0 2006.285.21:35:13.82#ibcon#wrote, iclass 11, count 0 2006.285.21:35:13.82#ibcon#about to read 3, iclass 11, count 0 2006.285.21:35:13.84#ibcon#read 3, iclass 11, count 0 2006.285.21:35:13.91#ibcon#about to read 4, iclass 11, count 0 2006.285.21:35:13.91#ibcon#read 4, iclass 11, count 0 2006.285.21:35:13.91#ibcon#about to read 5, iclass 11, count 0 2006.285.21:35:13.91#ibcon#read 5, iclass 11, count 0 2006.285.21:35:13.91#ibcon#about to read 6, iclass 11, count 0 2006.285.21:35:13.91#ibcon#read 6, iclass 11, count 0 2006.285.21:35:13.91#ibcon#end of sib2, iclass 11, count 0 2006.285.21:35:13.91#ibcon#*mode == 0, iclass 11, count 0 2006.285.21:35:13.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.21:35:13.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:35:13.91#ibcon#*before write, iclass 11, count 0 2006.285.21:35:13.91#ibcon#enter sib2, iclass 11, count 0 2006.285.21:35:13.91#ibcon#flushed, iclass 11, count 0 2006.285.21:35:13.91#ibcon#about to write, iclass 11, count 0 2006.285.21:35:13.91#ibcon#wrote, iclass 11, count 0 2006.285.21:35:13.91#ibcon#about to read 3, iclass 11, count 0 2006.285.21:35:13.95#ibcon#read 3, iclass 11, count 0 2006.285.21:35:13.95#ibcon#about to read 4, iclass 11, count 0 2006.285.21:35:13.95#ibcon#read 4, iclass 11, count 0 2006.285.21:35:13.95#ibcon#about to read 5, iclass 11, count 0 2006.285.21:35:13.95#ibcon#read 5, iclass 11, count 0 2006.285.21:35:13.95#ibcon#about to read 6, iclass 11, count 0 2006.285.21:35:13.95#ibcon#read 6, iclass 11, count 0 2006.285.21:35:13.95#ibcon#end of sib2, iclass 11, count 0 2006.285.21:35:13.95#ibcon#*after write, iclass 11, count 0 2006.285.21:35:13.95#ibcon#*before return 0, iclass 11, count 0 2006.285.21:35:13.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:35:13.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.21:35:13.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.21:35:13.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.21:35:13.95$vck44/vb=2,5 2006.285.21:35:13.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.21:35:13.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.21:35:13.95#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:13.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:35:13.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:35:13.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:35:13.95#ibcon#enter wrdev, iclass 13, count 2 2006.285.21:35:13.95#ibcon#first serial, iclass 13, count 2 2006.285.21:35:13.95#ibcon#enter sib2, iclass 13, count 2 2006.285.21:35:13.95#ibcon#flushed, iclass 13, count 2 2006.285.21:35:13.95#ibcon#about to write, iclass 13, count 2 2006.285.21:35:13.95#ibcon#wrote, iclass 13, count 2 2006.285.21:35:13.95#ibcon#about to read 3, iclass 13, count 2 2006.285.21:35:13.97#ibcon#read 3, iclass 13, count 2 2006.285.21:35:13.97#ibcon#about to read 4, iclass 13, count 2 2006.285.21:35:13.97#ibcon#read 4, iclass 13, count 2 2006.285.21:35:13.97#ibcon#about to read 5, iclass 13, count 2 2006.285.21:35:13.97#ibcon#read 5, iclass 13, count 2 2006.285.21:35:13.97#ibcon#about to read 6, iclass 13, count 2 2006.285.21:35:13.97#ibcon#read 6, iclass 13, count 2 2006.285.21:35:13.97#ibcon#end of sib2, iclass 13, count 2 2006.285.21:35:13.97#ibcon#*mode == 0, iclass 13, count 2 2006.285.21:35:13.97#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.21:35:13.97#ibcon#[27=AT02-05\r\n] 2006.285.21:35:13.97#ibcon#*before write, iclass 13, count 2 2006.285.21:35:13.97#ibcon#enter sib2, iclass 13, count 2 2006.285.21:35:13.97#ibcon#flushed, iclass 13, count 2 2006.285.21:35:13.97#ibcon#about to write, iclass 13, count 2 2006.285.21:35:13.97#ibcon#wrote, iclass 13, count 2 2006.285.21:35:13.97#ibcon#about to read 3, iclass 13, count 2 2006.285.21:35:14.00#ibcon#read 3, iclass 13, count 2 2006.285.21:35:14.00#ibcon#about to read 4, iclass 13, count 2 2006.285.21:35:14.00#ibcon#read 4, iclass 13, count 2 2006.285.21:35:14.00#ibcon#about to read 5, iclass 13, count 2 2006.285.21:35:14.00#ibcon#read 5, iclass 13, count 2 2006.285.21:35:14.00#ibcon#about to read 6, iclass 13, count 2 2006.285.21:35:14.00#ibcon#read 6, iclass 13, count 2 2006.285.21:35:14.00#ibcon#end of sib2, iclass 13, count 2 2006.285.21:35:14.00#ibcon#*after write, iclass 13, count 2 2006.285.21:35:14.00#ibcon#*before return 0, iclass 13, count 2 2006.285.21:35:14.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:35:14.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.21:35:14.00#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.21:35:14.00#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:14.00#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:35:14.12#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:35:14.12#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:35:14.12#ibcon#enter wrdev, iclass 13, count 0 2006.285.21:35:14.12#ibcon#first serial, iclass 13, count 0 2006.285.21:35:14.12#ibcon#enter sib2, iclass 13, count 0 2006.285.21:35:14.12#ibcon#flushed, iclass 13, count 0 2006.285.21:35:14.12#ibcon#about to write, iclass 13, count 0 2006.285.21:35:14.12#ibcon#wrote, iclass 13, count 0 2006.285.21:35:14.12#ibcon#about to read 3, iclass 13, count 0 2006.285.21:35:14.14#ibcon#read 3, iclass 13, count 0 2006.285.21:35:14.14#ibcon#about to read 4, iclass 13, count 0 2006.285.21:35:14.14#ibcon#read 4, iclass 13, count 0 2006.285.21:35:14.14#ibcon#about to read 5, iclass 13, count 0 2006.285.21:35:14.14#ibcon#read 5, iclass 13, count 0 2006.285.21:35:14.14#ibcon#about to read 6, iclass 13, count 0 2006.285.21:35:14.14#ibcon#read 6, iclass 13, count 0 2006.285.21:35:14.14#ibcon#end of sib2, iclass 13, count 0 2006.285.21:35:14.14#ibcon#*mode == 0, iclass 13, count 0 2006.285.21:35:14.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.21:35:14.14#ibcon#[27=USB\r\n] 2006.285.21:35:14.14#ibcon#*before write, iclass 13, count 0 2006.285.21:35:14.14#ibcon#enter sib2, iclass 13, count 0 2006.285.21:35:14.14#ibcon#flushed, iclass 13, count 0 2006.285.21:35:14.14#ibcon#about to write, iclass 13, count 0 2006.285.21:35:14.14#ibcon#wrote, iclass 13, count 0 2006.285.21:35:14.14#ibcon#about to read 3, iclass 13, count 0 2006.285.21:35:14.17#ibcon#read 3, iclass 13, count 0 2006.285.21:35:14.17#ibcon#about to read 4, iclass 13, count 0 2006.285.21:35:14.17#ibcon#read 4, iclass 13, count 0 2006.285.21:35:14.17#ibcon#about to read 5, iclass 13, count 0 2006.285.21:35:14.17#ibcon#read 5, iclass 13, count 0 2006.285.21:35:14.17#ibcon#about to read 6, iclass 13, count 0 2006.285.21:35:14.17#ibcon#read 6, iclass 13, count 0 2006.285.21:35:14.17#ibcon#end of sib2, iclass 13, count 0 2006.285.21:35:14.17#ibcon#*after write, iclass 13, count 0 2006.285.21:35:14.17#ibcon#*before return 0, iclass 13, count 0 2006.285.21:35:14.17#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:35:14.17#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.21:35:14.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.21:35:14.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.21:35:14.17$vck44/vblo=3,649.99 2006.285.21:35:14.17#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.21:35:14.17#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.21:35:14.17#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:14.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:35:14.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:35:14.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:35:14.17#ibcon#enter wrdev, iclass 15, count 0 2006.285.21:35:14.17#ibcon#first serial, iclass 15, count 0 2006.285.21:35:14.17#ibcon#enter sib2, iclass 15, count 0 2006.285.21:35:14.17#ibcon#flushed, iclass 15, count 0 2006.285.21:35:14.17#ibcon#about to write, iclass 15, count 0 2006.285.21:35:14.17#ibcon#wrote, iclass 15, count 0 2006.285.21:35:14.17#ibcon#about to read 3, iclass 15, count 0 2006.285.21:35:14.19#ibcon#read 3, iclass 15, count 0 2006.285.21:35:14.19#ibcon#about to read 4, iclass 15, count 0 2006.285.21:35:14.19#ibcon#read 4, iclass 15, count 0 2006.285.21:35:14.19#ibcon#about to read 5, iclass 15, count 0 2006.285.21:35:14.19#ibcon#read 5, iclass 15, count 0 2006.285.21:35:14.19#ibcon#about to read 6, iclass 15, count 0 2006.285.21:35:14.19#ibcon#read 6, iclass 15, count 0 2006.285.21:35:14.19#ibcon#end of sib2, iclass 15, count 0 2006.285.21:35:14.19#ibcon#*mode == 0, iclass 15, count 0 2006.285.21:35:14.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.21:35:14.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:35:14.19#ibcon#*before write, iclass 15, count 0 2006.285.21:35:14.19#ibcon#enter sib2, iclass 15, count 0 2006.285.21:35:14.19#ibcon#flushed, iclass 15, count 0 2006.285.21:35:14.19#ibcon#about to write, iclass 15, count 0 2006.285.21:35:14.19#ibcon#wrote, iclass 15, count 0 2006.285.21:35:14.19#ibcon#about to read 3, iclass 15, count 0 2006.285.21:35:14.23#ibcon#read 3, iclass 15, count 0 2006.285.21:35:14.23#ibcon#about to read 4, iclass 15, count 0 2006.285.21:35:14.23#ibcon#read 4, iclass 15, count 0 2006.285.21:35:14.23#ibcon#about to read 5, iclass 15, count 0 2006.285.21:35:14.23#ibcon#read 5, iclass 15, count 0 2006.285.21:35:14.23#ibcon#about to read 6, iclass 15, count 0 2006.285.21:35:14.23#ibcon#read 6, iclass 15, count 0 2006.285.21:35:14.23#ibcon#end of sib2, iclass 15, count 0 2006.285.21:35:14.23#ibcon#*after write, iclass 15, count 0 2006.285.21:35:14.23#ibcon#*before return 0, iclass 15, count 0 2006.285.21:35:14.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:35:14.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.21:35:14.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.21:35:14.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.21:35:14.23$vck44/vb=3,4 2006.285.21:35:14.23#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.21:35:14.23#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.21:35:14.23#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:14.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:35:14.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:35:14.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:35:14.29#ibcon#enter wrdev, iclass 17, count 2 2006.285.21:35:14.29#ibcon#first serial, iclass 17, count 2 2006.285.21:35:14.29#ibcon#enter sib2, iclass 17, count 2 2006.285.21:35:14.29#ibcon#flushed, iclass 17, count 2 2006.285.21:35:14.29#ibcon#about to write, iclass 17, count 2 2006.285.21:35:14.29#ibcon#wrote, iclass 17, count 2 2006.285.21:35:14.29#ibcon#about to read 3, iclass 17, count 2 2006.285.21:35:14.31#ibcon#read 3, iclass 17, count 2 2006.285.21:35:14.31#ibcon#about to read 4, iclass 17, count 2 2006.285.21:35:14.31#ibcon#read 4, iclass 17, count 2 2006.285.21:35:14.31#ibcon#about to read 5, iclass 17, count 2 2006.285.21:35:14.31#ibcon#read 5, iclass 17, count 2 2006.285.21:35:14.31#ibcon#about to read 6, iclass 17, count 2 2006.285.21:35:14.31#ibcon#read 6, iclass 17, count 2 2006.285.21:35:14.31#ibcon#end of sib2, iclass 17, count 2 2006.285.21:35:14.31#ibcon#*mode == 0, iclass 17, count 2 2006.285.21:35:14.31#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.21:35:14.31#ibcon#[27=AT03-04\r\n] 2006.285.21:35:14.31#ibcon#*before write, iclass 17, count 2 2006.285.21:35:14.31#ibcon#enter sib2, iclass 17, count 2 2006.285.21:35:14.31#ibcon#flushed, iclass 17, count 2 2006.285.21:35:14.31#ibcon#about to write, iclass 17, count 2 2006.285.21:35:14.31#ibcon#wrote, iclass 17, count 2 2006.285.21:35:14.31#ibcon#about to read 3, iclass 17, count 2 2006.285.21:35:14.34#ibcon#read 3, iclass 17, count 2 2006.285.21:35:14.34#ibcon#about to read 4, iclass 17, count 2 2006.285.21:35:14.34#ibcon#read 4, iclass 17, count 2 2006.285.21:35:14.34#ibcon#about to read 5, iclass 17, count 2 2006.285.21:35:14.34#ibcon#read 5, iclass 17, count 2 2006.285.21:35:14.34#ibcon#about to read 6, iclass 17, count 2 2006.285.21:35:14.34#ibcon#read 6, iclass 17, count 2 2006.285.21:35:14.34#ibcon#end of sib2, iclass 17, count 2 2006.285.21:35:14.34#ibcon#*after write, iclass 17, count 2 2006.285.21:35:14.34#ibcon#*before return 0, iclass 17, count 2 2006.285.21:35:14.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:35:14.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.21:35:14.34#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.21:35:14.34#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:14.34#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:35:14.46#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:35:14.46#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:35:14.46#ibcon#enter wrdev, iclass 17, count 0 2006.285.21:35:14.46#ibcon#first serial, iclass 17, count 0 2006.285.21:35:14.46#ibcon#enter sib2, iclass 17, count 0 2006.285.21:35:14.46#ibcon#flushed, iclass 17, count 0 2006.285.21:35:14.46#ibcon#about to write, iclass 17, count 0 2006.285.21:35:14.46#ibcon#wrote, iclass 17, count 0 2006.285.21:35:14.46#ibcon#about to read 3, iclass 17, count 0 2006.285.21:35:14.48#ibcon#read 3, iclass 17, count 0 2006.285.21:35:14.48#ibcon#about to read 4, iclass 17, count 0 2006.285.21:35:14.48#ibcon#read 4, iclass 17, count 0 2006.285.21:35:14.48#ibcon#about to read 5, iclass 17, count 0 2006.285.21:35:14.48#ibcon#read 5, iclass 17, count 0 2006.285.21:35:14.48#ibcon#about to read 6, iclass 17, count 0 2006.285.21:35:14.48#ibcon#read 6, iclass 17, count 0 2006.285.21:35:14.48#ibcon#end of sib2, iclass 17, count 0 2006.285.21:35:14.48#ibcon#*mode == 0, iclass 17, count 0 2006.285.21:35:14.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.21:35:14.48#ibcon#[27=USB\r\n] 2006.285.21:35:14.48#ibcon#*before write, iclass 17, count 0 2006.285.21:35:14.48#ibcon#enter sib2, iclass 17, count 0 2006.285.21:35:14.48#ibcon#flushed, iclass 17, count 0 2006.285.21:35:14.48#ibcon#about to write, iclass 17, count 0 2006.285.21:35:14.48#ibcon#wrote, iclass 17, count 0 2006.285.21:35:14.48#ibcon#about to read 3, iclass 17, count 0 2006.285.21:35:14.51#ibcon#read 3, iclass 17, count 0 2006.285.21:35:14.51#ibcon#about to read 4, iclass 17, count 0 2006.285.21:35:14.51#ibcon#read 4, iclass 17, count 0 2006.285.21:35:14.51#ibcon#about to read 5, iclass 17, count 0 2006.285.21:35:14.51#ibcon#read 5, iclass 17, count 0 2006.285.21:35:14.51#ibcon#about to read 6, iclass 17, count 0 2006.285.21:35:14.51#ibcon#read 6, iclass 17, count 0 2006.285.21:35:14.51#ibcon#end of sib2, iclass 17, count 0 2006.285.21:35:14.51#ibcon#*after write, iclass 17, count 0 2006.285.21:35:14.51#ibcon#*before return 0, iclass 17, count 0 2006.285.21:35:14.51#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:35:14.51#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.21:35:14.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.21:35:14.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.21:35:14.51$vck44/vblo=4,679.99 2006.285.21:35:14.51#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.21:35:14.51#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.21:35:14.51#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:14.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:35:14.51#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:35:14.51#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:35:14.51#ibcon#enter wrdev, iclass 19, count 0 2006.285.21:35:14.51#ibcon#first serial, iclass 19, count 0 2006.285.21:35:14.51#ibcon#enter sib2, iclass 19, count 0 2006.285.21:35:14.51#ibcon#flushed, iclass 19, count 0 2006.285.21:35:14.51#ibcon#about to write, iclass 19, count 0 2006.285.21:35:14.51#ibcon#wrote, iclass 19, count 0 2006.285.21:35:14.51#ibcon#about to read 3, iclass 19, count 0 2006.285.21:35:14.53#ibcon#read 3, iclass 19, count 0 2006.285.21:35:14.53#ibcon#about to read 4, iclass 19, count 0 2006.285.21:35:14.53#ibcon#read 4, iclass 19, count 0 2006.285.21:35:14.53#ibcon#about to read 5, iclass 19, count 0 2006.285.21:35:14.53#ibcon#read 5, iclass 19, count 0 2006.285.21:35:14.53#ibcon#about to read 6, iclass 19, count 0 2006.285.21:35:14.53#ibcon#read 6, iclass 19, count 0 2006.285.21:35:14.53#ibcon#end of sib2, iclass 19, count 0 2006.285.21:35:14.53#ibcon#*mode == 0, iclass 19, count 0 2006.285.21:35:14.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.21:35:14.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:35:14.53#ibcon#*before write, iclass 19, count 0 2006.285.21:35:14.53#ibcon#enter sib2, iclass 19, count 0 2006.285.21:35:14.53#ibcon#flushed, iclass 19, count 0 2006.285.21:35:14.53#ibcon#about to write, iclass 19, count 0 2006.285.21:35:14.53#ibcon#wrote, iclass 19, count 0 2006.285.21:35:14.53#ibcon#about to read 3, iclass 19, count 0 2006.285.21:35:14.57#ibcon#read 3, iclass 19, count 0 2006.285.21:35:14.57#ibcon#about to read 4, iclass 19, count 0 2006.285.21:35:14.57#ibcon#read 4, iclass 19, count 0 2006.285.21:35:14.57#ibcon#about to read 5, iclass 19, count 0 2006.285.21:35:14.57#ibcon#read 5, iclass 19, count 0 2006.285.21:35:14.57#ibcon#about to read 6, iclass 19, count 0 2006.285.21:35:14.57#ibcon#read 6, iclass 19, count 0 2006.285.21:35:14.57#ibcon#end of sib2, iclass 19, count 0 2006.285.21:35:14.57#ibcon#*after write, iclass 19, count 0 2006.285.21:35:14.57#ibcon#*before return 0, iclass 19, count 0 2006.285.21:35:14.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:35:14.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.21:35:14.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.21:35:14.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.21:35:14.57$vck44/vb=4,5 2006.285.21:35:14.57#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.21:35:14.57#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.21:35:14.57#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:14.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:35:14.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:35:14.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:35:14.63#ibcon#enter wrdev, iclass 21, count 2 2006.285.21:35:14.63#ibcon#first serial, iclass 21, count 2 2006.285.21:35:14.63#ibcon#enter sib2, iclass 21, count 2 2006.285.21:35:14.63#ibcon#flushed, iclass 21, count 2 2006.285.21:35:14.63#ibcon#about to write, iclass 21, count 2 2006.285.21:35:14.63#ibcon#wrote, iclass 21, count 2 2006.285.21:35:14.63#ibcon#about to read 3, iclass 21, count 2 2006.285.21:35:14.65#ibcon#read 3, iclass 21, count 2 2006.285.21:35:14.65#ibcon#about to read 4, iclass 21, count 2 2006.285.21:35:14.65#ibcon#read 4, iclass 21, count 2 2006.285.21:35:14.65#ibcon#about to read 5, iclass 21, count 2 2006.285.21:35:14.65#ibcon#read 5, iclass 21, count 2 2006.285.21:35:14.65#ibcon#about to read 6, iclass 21, count 2 2006.285.21:35:14.65#ibcon#read 6, iclass 21, count 2 2006.285.21:35:14.65#ibcon#end of sib2, iclass 21, count 2 2006.285.21:35:14.65#ibcon#*mode == 0, iclass 21, count 2 2006.285.21:35:14.65#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.21:35:14.65#ibcon#[27=AT04-05\r\n] 2006.285.21:35:14.65#ibcon#*before write, iclass 21, count 2 2006.285.21:35:14.65#ibcon#enter sib2, iclass 21, count 2 2006.285.21:35:14.65#ibcon#flushed, iclass 21, count 2 2006.285.21:35:14.65#ibcon#about to write, iclass 21, count 2 2006.285.21:35:14.65#ibcon#wrote, iclass 21, count 2 2006.285.21:35:14.65#ibcon#about to read 3, iclass 21, count 2 2006.285.21:35:14.68#ibcon#read 3, iclass 21, count 2 2006.285.21:35:14.68#ibcon#about to read 4, iclass 21, count 2 2006.285.21:35:14.68#ibcon#read 4, iclass 21, count 2 2006.285.21:35:14.68#ibcon#about to read 5, iclass 21, count 2 2006.285.21:35:14.68#ibcon#read 5, iclass 21, count 2 2006.285.21:35:14.68#ibcon#about to read 6, iclass 21, count 2 2006.285.21:35:14.68#ibcon#read 6, iclass 21, count 2 2006.285.21:35:14.68#ibcon#end of sib2, iclass 21, count 2 2006.285.21:35:14.68#ibcon#*after write, iclass 21, count 2 2006.285.21:35:14.68#ibcon#*before return 0, iclass 21, count 2 2006.285.21:35:14.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:35:14.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.21:35:14.68#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.21:35:14.68#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:14.68#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:35:14.80#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:35:14.80#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:35:14.80#ibcon#enter wrdev, iclass 21, count 0 2006.285.21:35:14.80#ibcon#first serial, iclass 21, count 0 2006.285.21:35:14.80#ibcon#enter sib2, iclass 21, count 0 2006.285.21:35:14.80#ibcon#flushed, iclass 21, count 0 2006.285.21:35:14.80#ibcon#about to write, iclass 21, count 0 2006.285.21:35:14.80#ibcon#wrote, iclass 21, count 0 2006.285.21:35:14.80#ibcon#about to read 3, iclass 21, count 0 2006.285.21:35:14.82#ibcon#read 3, iclass 21, count 0 2006.285.21:35:14.82#ibcon#about to read 4, iclass 21, count 0 2006.285.21:35:14.82#ibcon#read 4, iclass 21, count 0 2006.285.21:35:14.82#ibcon#about to read 5, iclass 21, count 0 2006.285.21:35:14.82#ibcon#read 5, iclass 21, count 0 2006.285.21:35:14.82#ibcon#about to read 6, iclass 21, count 0 2006.285.21:35:14.82#ibcon#read 6, iclass 21, count 0 2006.285.21:35:14.82#ibcon#end of sib2, iclass 21, count 0 2006.285.21:35:14.82#ibcon#*mode == 0, iclass 21, count 0 2006.285.21:35:14.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.21:35:14.82#ibcon#[27=USB\r\n] 2006.285.21:35:14.82#ibcon#*before write, iclass 21, count 0 2006.285.21:35:14.82#ibcon#enter sib2, iclass 21, count 0 2006.285.21:35:14.82#ibcon#flushed, iclass 21, count 0 2006.285.21:35:14.82#ibcon#about to write, iclass 21, count 0 2006.285.21:35:14.82#ibcon#wrote, iclass 21, count 0 2006.285.21:35:14.82#ibcon#about to read 3, iclass 21, count 0 2006.285.21:35:14.85#ibcon#read 3, iclass 21, count 0 2006.285.21:35:14.85#ibcon#about to read 4, iclass 21, count 0 2006.285.21:35:14.85#ibcon#read 4, iclass 21, count 0 2006.285.21:35:14.85#ibcon#about to read 5, iclass 21, count 0 2006.285.21:35:14.85#ibcon#read 5, iclass 21, count 0 2006.285.21:35:14.85#ibcon#about to read 6, iclass 21, count 0 2006.285.21:35:14.85#ibcon#read 6, iclass 21, count 0 2006.285.21:35:14.85#ibcon#end of sib2, iclass 21, count 0 2006.285.21:35:14.85#ibcon#*after write, iclass 21, count 0 2006.285.21:35:14.85#ibcon#*before return 0, iclass 21, count 0 2006.285.21:35:14.85#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:35:14.85#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.21:35:14.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.21:35:14.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.21:35:14.85$vck44/vblo=5,709.99 2006.285.21:35:14.85#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.21:35:14.85#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.21:35:14.85#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:14.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:35:14.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:35:14.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:35:14.85#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:35:14.85#ibcon#first serial, iclass 23, count 0 2006.285.21:35:14.85#ibcon#enter sib2, iclass 23, count 0 2006.285.21:35:14.85#ibcon#flushed, iclass 23, count 0 2006.285.21:35:14.85#ibcon#about to write, iclass 23, count 0 2006.285.21:35:14.85#ibcon#wrote, iclass 23, count 0 2006.285.21:35:14.85#ibcon#about to read 3, iclass 23, count 0 2006.285.21:35:14.87#ibcon#read 3, iclass 23, count 0 2006.285.21:35:14.92#ibcon#about to read 4, iclass 23, count 0 2006.285.21:35:14.92#ibcon#read 4, iclass 23, count 0 2006.285.21:35:14.92#ibcon#about to read 5, iclass 23, count 0 2006.285.21:35:14.92#ibcon#read 5, iclass 23, count 0 2006.285.21:35:14.92#ibcon#about to read 6, iclass 23, count 0 2006.285.21:35:14.92#ibcon#read 6, iclass 23, count 0 2006.285.21:35:14.92#ibcon#end of sib2, iclass 23, count 0 2006.285.21:35:14.92#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:35:14.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:35:14.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:35:14.92#ibcon#*before write, iclass 23, count 0 2006.285.21:35:14.92#ibcon#enter sib2, iclass 23, count 0 2006.285.21:35:14.92#ibcon#flushed, iclass 23, count 0 2006.285.21:35:14.92#ibcon#about to write, iclass 23, count 0 2006.285.21:35:14.92#ibcon#wrote, iclass 23, count 0 2006.285.21:35:14.92#ibcon#about to read 3, iclass 23, count 0 2006.285.21:35:14.96#ibcon#read 3, iclass 23, count 0 2006.285.21:35:14.96#ibcon#about to read 4, iclass 23, count 0 2006.285.21:35:14.96#ibcon#read 4, iclass 23, count 0 2006.285.21:35:14.96#ibcon#about to read 5, iclass 23, count 0 2006.285.21:35:14.96#ibcon#read 5, iclass 23, count 0 2006.285.21:35:14.96#ibcon#about to read 6, iclass 23, count 0 2006.285.21:35:14.96#ibcon#read 6, iclass 23, count 0 2006.285.21:35:14.96#ibcon#end of sib2, iclass 23, count 0 2006.285.21:35:14.96#ibcon#*after write, iclass 23, count 0 2006.285.21:35:14.96#ibcon#*before return 0, iclass 23, count 0 2006.285.21:35:14.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:35:14.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.21:35:14.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:35:14.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:35:14.96$vck44/vb=5,4 2006.285.21:35:14.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.21:35:14.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.21:35:14.96#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:14.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:35:14.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:35:14.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:35:14.96#ibcon#enter wrdev, iclass 25, count 2 2006.285.21:35:14.96#ibcon#first serial, iclass 25, count 2 2006.285.21:35:14.96#ibcon#enter sib2, iclass 25, count 2 2006.285.21:35:14.96#ibcon#flushed, iclass 25, count 2 2006.285.21:35:14.96#ibcon#about to write, iclass 25, count 2 2006.285.21:35:14.96#ibcon#wrote, iclass 25, count 2 2006.285.21:35:14.96#ibcon#about to read 3, iclass 25, count 2 2006.285.21:35:14.98#ibcon#read 3, iclass 25, count 2 2006.285.21:35:14.98#ibcon#about to read 4, iclass 25, count 2 2006.285.21:35:14.98#ibcon#read 4, iclass 25, count 2 2006.285.21:35:14.98#ibcon#about to read 5, iclass 25, count 2 2006.285.21:35:14.98#ibcon#read 5, iclass 25, count 2 2006.285.21:35:14.98#ibcon#about to read 6, iclass 25, count 2 2006.285.21:35:14.98#ibcon#read 6, iclass 25, count 2 2006.285.21:35:14.98#ibcon#end of sib2, iclass 25, count 2 2006.285.21:35:14.98#ibcon#*mode == 0, iclass 25, count 2 2006.285.21:35:14.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.21:35:14.98#ibcon#[27=AT05-04\r\n] 2006.285.21:35:14.98#ibcon#*before write, iclass 25, count 2 2006.285.21:35:14.98#ibcon#enter sib2, iclass 25, count 2 2006.285.21:35:14.98#ibcon#flushed, iclass 25, count 2 2006.285.21:35:14.98#ibcon#about to write, iclass 25, count 2 2006.285.21:35:14.98#ibcon#wrote, iclass 25, count 2 2006.285.21:35:14.98#ibcon#about to read 3, iclass 25, count 2 2006.285.21:35:15.01#ibcon#read 3, iclass 25, count 2 2006.285.21:35:15.01#ibcon#about to read 4, iclass 25, count 2 2006.285.21:35:15.01#ibcon#read 4, iclass 25, count 2 2006.285.21:35:15.01#ibcon#about to read 5, iclass 25, count 2 2006.285.21:35:15.01#ibcon#read 5, iclass 25, count 2 2006.285.21:35:15.01#ibcon#about to read 6, iclass 25, count 2 2006.285.21:35:15.01#ibcon#read 6, iclass 25, count 2 2006.285.21:35:15.01#ibcon#end of sib2, iclass 25, count 2 2006.285.21:35:15.01#ibcon#*after write, iclass 25, count 2 2006.285.21:35:15.01#ibcon#*before return 0, iclass 25, count 2 2006.285.21:35:15.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:35:15.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.21:35:15.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.21:35:15.01#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:15.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:35:15.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:35:15.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:35:15.13#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:35:15.13#ibcon#first serial, iclass 25, count 0 2006.285.21:35:15.13#ibcon#enter sib2, iclass 25, count 0 2006.285.21:35:15.13#ibcon#flushed, iclass 25, count 0 2006.285.21:35:15.13#ibcon#about to write, iclass 25, count 0 2006.285.21:35:15.13#ibcon#wrote, iclass 25, count 0 2006.285.21:35:15.13#ibcon#about to read 3, iclass 25, count 0 2006.285.21:35:15.15#ibcon#read 3, iclass 25, count 0 2006.285.21:35:15.15#ibcon#about to read 4, iclass 25, count 0 2006.285.21:35:15.15#ibcon#read 4, iclass 25, count 0 2006.285.21:35:15.15#ibcon#about to read 5, iclass 25, count 0 2006.285.21:35:15.15#ibcon#read 5, iclass 25, count 0 2006.285.21:35:15.15#ibcon#about to read 6, iclass 25, count 0 2006.285.21:35:15.15#ibcon#read 6, iclass 25, count 0 2006.285.21:35:15.15#ibcon#end of sib2, iclass 25, count 0 2006.285.21:35:15.15#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:35:15.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:35:15.15#ibcon#[27=USB\r\n] 2006.285.21:35:15.15#ibcon#*before write, iclass 25, count 0 2006.285.21:35:15.15#ibcon#enter sib2, iclass 25, count 0 2006.285.21:35:15.15#ibcon#flushed, iclass 25, count 0 2006.285.21:35:15.15#ibcon#about to write, iclass 25, count 0 2006.285.21:35:15.15#ibcon#wrote, iclass 25, count 0 2006.285.21:35:15.15#ibcon#about to read 3, iclass 25, count 0 2006.285.21:35:15.18#ibcon#read 3, iclass 25, count 0 2006.285.21:35:15.18#ibcon#about to read 4, iclass 25, count 0 2006.285.21:35:15.18#ibcon#read 4, iclass 25, count 0 2006.285.21:35:15.18#ibcon#about to read 5, iclass 25, count 0 2006.285.21:35:15.18#ibcon#read 5, iclass 25, count 0 2006.285.21:35:15.18#ibcon#about to read 6, iclass 25, count 0 2006.285.21:35:15.18#ibcon#read 6, iclass 25, count 0 2006.285.21:35:15.18#ibcon#end of sib2, iclass 25, count 0 2006.285.21:35:15.18#ibcon#*after write, iclass 25, count 0 2006.285.21:35:15.18#ibcon#*before return 0, iclass 25, count 0 2006.285.21:35:15.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:35:15.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.21:35:15.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:35:15.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:35:15.18$vck44/vblo=6,719.99 2006.285.21:35:15.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.21:35:15.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.21:35:15.18#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:15.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:35:15.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:35:15.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:35:15.18#ibcon#enter wrdev, iclass 27, count 0 2006.285.21:35:15.18#ibcon#first serial, iclass 27, count 0 2006.285.21:35:15.18#ibcon#enter sib2, iclass 27, count 0 2006.285.21:35:15.18#ibcon#flushed, iclass 27, count 0 2006.285.21:35:15.18#ibcon#about to write, iclass 27, count 0 2006.285.21:35:15.18#ibcon#wrote, iclass 27, count 0 2006.285.21:35:15.18#ibcon#about to read 3, iclass 27, count 0 2006.285.21:35:15.20#ibcon#read 3, iclass 27, count 0 2006.285.21:35:15.20#ibcon#about to read 4, iclass 27, count 0 2006.285.21:35:15.20#ibcon#read 4, iclass 27, count 0 2006.285.21:35:15.20#ibcon#about to read 5, iclass 27, count 0 2006.285.21:35:15.20#ibcon#read 5, iclass 27, count 0 2006.285.21:35:15.20#ibcon#about to read 6, iclass 27, count 0 2006.285.21:35:15.20#ibcon#read 6, iclass 27, count 0 2006.285.21:35:15.20#ibcon#end of sib2, iclass 27, count 0 2006.285.21:35:15.20#ibcon#*mode == 0, iclass 27, count 0 2006.285.21:35:15.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.21:35:15.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:35:15.20#ibcon#*before write, iclass 27, count 0 2006.285.21:35:15.20#ibcon#enter sib2, iclass 27, count 0 2006.285.21:35:15.20#ibcon#flushed, iclass 27, count 0 2006.285.21:35:15.20#ibcon#about to write, iclass 27, count 0 2006.285.21:35:15.20#ibcon#wrote, iclass 27, count 0 2006.285.21:35:15.20#ibcon#about to read 3, iclass 27, count 0 2006.285.21:35:15.24#ibcon#read 3, iclass 27, count 0 2006.285.21:35:15.24#ibcon#about to read 4, iclass 27, count 0 2006.285.21:35:15.24#ibcon#read 4, iclass 27, count 0 2006.285.21:35:15.24#ibcon#about to read 5, iclass 27, count 0 2006.285.21:35:15.24#ibcon#read 5, iclass 27, count 0 2006.285.21:35:15.24#ibcon#about to read 6, iclass 27, count 0 2006.285.21:35:15.24#ibcon#read 6, iclass 27, count 0 2006.285.21:35:15.24#ibcon#end of sib2, iclass 27, count 0 2006.285.21:35:15.24#ibcon#*after write, iclass 27, count 0 2006.285.21:35:15.24#ibcon#*before return 0, iclass 27, count 0 2006.285.21:35:15.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:35:15.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.21:35:15.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.21:35:15.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.21:35:15.24$vck44/vb=6,3 2006.285.21:35:15.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.21:35:15.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.21:35:15.24#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:15.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:35:15.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:35:15.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:35:15.30#ibcon#enter wrdev, iclass 29, count 2 2006.285.21:35:15.30#ibcon#first serial, iclass 29, count 2 2006.285.21:35:15.30#ibcon#enter sib2, iclass 29, count 2 2006.285.21:35:15.30#ibcon#flushed, iclass 29, count 2 2006.285.21:35:15.30#ibcon#about to write, iclass 29, count 2 2006.285.21:35:15.30#ibcon#wrote, iclass 29, count 2 2006.285.21:35:15.30#ibcon#about to read 3, iclass 29, count 2 2006.285.21:35:15.32#ibcon#read 3, iclass 29, count 2 2006.285.21:35:15.32#ibcon#about to read 4, iclass 29, count 2 2006.285.21:35:15.32#ibcon#read 4, iclass 29, count 2 2006.285.21:35:15.32#ibcon#about to read 5, iclass 29, count 2 2006.285.21:35:15.32#ibcon#read 5, iclass 29, count 2 2006.285.21:35:15.32#ibcon#about to read 6, iclass 29, count 2 2006.285.21:35:15.32#ibcon#read 6, iclass 29, count 2 2006.285.21:35:15.32#ibcon#end of sib2, iclass 29, count 2 2006.285.21:35:15.32#ibcon#*mode == 0, iclass 29, count 2 2006.285.21:35:15.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.21:35:15.32#ibcon#[27=AT06-03\r\n] 2006.285.21:35:15.32#ibcon#*before write, iclass 29, count 2 2006.285.21:35:15.32#ibcon#enter sib2, iclass 29, count 2 2006.285.21:35:15.32#ibcon#flushed, iclass 29, count 2 2006.285.21:35:15.32#ibcon#about to write, iclass 29, count 2 2006.285.21:35:15.32#ibcon#wrote, iclass 29, count 2 2006.285.21:35:15.32#ibcon#about to read 3, iclass 29, count 2 2006.285.21:35:15.35#ibcon#read 3, iclass 29, count 2 2006.285.21:35:15.35#ibcon#about to read 4, iclass 29, count 2 2006.285.21:35:15.35#ibcon#read 4, iclass 29, count 2 2006.285.21:35:15.35#ibcon#about to read 5, iclass 29, count 2 2006.285.21:35:15.35#ibcon#read 5, iclass 29, count 2 2006.285.21:35:15.35#ibcon#about to read 6, iclass 29, count 2 2006.285.21:35:15.35#ibcon#read 6, iclass 29, count 2 2006.285.21:35:15.35#ibcon#end of sib2, iclass 29, count 2 2006.285.21:35:15.35#ibcon#*after write, iclass 29, count 2 2006.285.21:35:15.35#ibcon#*before return 0, iclass 29, count 2 2006.285.21:35:15.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:35:15.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.21:35:15.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.21:35:15.35#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:15.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:35:15.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:35:15.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:35:15.47#ibcon#enter wrdev, iclass 29, count 0 2006.285.21:35:15.47#ibcon#first serial, iclass 29, count 0 2006.285.21:35:15.47#ibcon#enter sib2, iclass 29, count 0 2006.285.21:35:15.47#ibcon#flushed, iclass 29, count 0 2006.285.21:35:15.47#ibcon#about to write, iclass 29, count 0 2006.285.21:35:15.47#ibcon#wrote, iclass 29, count 0 2006.285.21:35:15.47#ibcon#about to read 3, iclass 29, count 0 2006.285.21:35:15.49#ibcon#read 3, iclass 29, count 0 2006.285.21:35:15.49#ibcon#about to read 4, iclass 29, count 0 2006.285.21:35:15.49#ibcon#read 4, iclass 29, count 0 2006.285.21:35:15.49#ibcon#about to read 5, iclass 29, count 0 2006.285.21:35:15.49#ibcon#read 5, iclass 29, count 0 2006.285.21:35:15.49#ibcon#about to read 6, iclass 29, count 0 2006.285.21:35:15.49#ibcon#read 6, iclass 29, count 0 2006.285.21:35:15.49#ibcon#end of sib2, iclass 29, count 0 2006.285.21:35:15.49#ibcon#*mode == 0, iclass 29, count 0 2006.285.21:35:15.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.21:35:15.49#ibcon#[27=USB\r\n] 2006.285.21:35:15.49#ibcon#*before write, iclass 29, count 0 2006.285.21:35:15.49#ibcon#enter sib2, iclass 29, count 0 2006.285.21:35:15.49#ibcon#flushed, iclass 29, count 0 2006.285.21:35:15.49#ibcon#about to write, iclass 29, count 0 2006.285.21:35:15.49#ibcon#wrote, iclass 29, count 0 2006.285.21:35:15.49#ibcon#about to read 3, iclass 29, count 0 2006.285.21:35:15.52#ibcon#read 3, iclass 29, count 0 2006.285.21:35:15.52#ibcon#about to read 4, iclass 29, count 0 2006.285.21:35:15.52#ibcon#read 4, iclass 29, count 0 2006.285.21:35:15.52#ibcon#about to read 5, iclass 29, count 0 2006.285.21:35:15.52#ibcon#read 5, iclass 29, count 0 2006.285.21:35:15.52#ibcon#about to read 6, iclass 29, count 0 2006.285.21:35:15.52#ibcon#read 6, iclass 29, count 0 2006.285.21:35:15.52#ibcon#end of sib2, iclass 29, count 0 2006.285.21:35:15.52#ibcon#*after write, iclass 29, count 0 2006.285.21:35:15.52#ibcon#*before return 0, iclass 29, count 0 2006.285.21:35:15.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:35:15.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.21:35:15.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.21:35:15.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.21:35:15.52$vck44/vblo=7,734.99 2006.285.21:35:15.52#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.21:35:15.52#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.21:35:15.52#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:15.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:35:15.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:35:15.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:35:15.52#ibcon#enter wrdev, iclass 31, count 0 2006.285.21:35:15.52#ibcon#first serial, iclass 31, count 0 2006.285.21:35:15.52#ibcon#enter sib2, iclass 31, count 0 2006.285.21:35:15.52#ibcon#flushed, iclass 31, count 0 2006.285.21:35:15.52#ibcon#about to write, iclass 31, count 0 2006.285.21:35:15.52#ibcon#wrote, iclass 31, count 0 2006.285.21:35:15.52#ibcon#about to read 3, iclass 31, count 0 2006.285.21:35:15.54#ibcon#read 3, iclass 31, count 0 2006.285.21:35:15.54#ibcon#about to read 4, iclass 31, count 0 2006.285.21:35:15.54#ibcon#read 4, iclass 31, count 0 2006.285.21:35:15.54#ibcon#about to read 5, iclass 31, count 0 2006.285.21:35:15.54#ibcon#read 5, iclass 31, count 0 2006.285.21:35:15.54#ibcon#about to read 6, iclass 31, count 0 2006.285.21:35:15.54#ibcon#read 6, iclass 31, count 0 2006.285.21:35:15.54#ibcon#end of sib2, iclass 31, count 0 2006.285.21:35:15.54#ibcon#*mode == 0, iclass 31, count 0 2006.285.21:35:15.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.21:35:15.54#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:35:15.54#ibcon#*before write, iclass 31, count 0 2006.285.21:35:15.54#ibcon#enter sib2, iclass 31, count 0 2006.285.21:35:15.54#ibcon#flushed, iclass 31, count 0 2006.285.21:35:15.54#ibcon#about to write, iclass 31, count 0 2006.285.21:35:15.54#ibcon#wrote, iclass 31, count 0 2006.285.21:35:15.54#ibcon#about to read 3, iclass 31, count 0 2006.285.21:35:15.58#ibcon#read 3, iclass 31, count 0 2006.285.21:35:15.58#ibcon#about to read 4, iclass 31, count 0 2006.285.21:35:15.58#ibcon#read 4, iclass 31, count 0 2006.285.21:35:15.58#ibcon#about to read 5, iclass 31, count 0 2006.285.21:35:15.58#ibcon#read 5, iclass 31, count 0 2006.285.21:35:15.58#ibcon#about to read 6, iclass 31, count 0 2006.285.21:35:15.58#ibcon#read 6, iclass 31, count 0 2006.285.21:35:15.58#ibcon#end of sib2, iclass 31, count 0 2006.285.21:35:15.58#ibcon#*after write, iclass 31, count 0 2006.285.21:35:15.58#ibcon#*before return 0, iclass 31, count 0 2006.285.21:35:15.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:35:15.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.21:35:15.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.21:35:15.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.21:35:15.58$vck44/vb=7,4 2006.285.21:35:15.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.21:35:15.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.21:35:15.58#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:15.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:35:15.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:35:15.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:35:15.64#ibcon#enter wrdev, iclass 33, count 2 2006.285.21:35:15.64#ibcon#first serial, iclass 33, count 2 2006.285.21:35:15.64#ibcon#enter sib2, iclass 33, count 2 2006.285.21:35:15.64#ibcon#flushed, iclass 33, count 2 2006.285.21:35:15.64#ibcon#about to write, iclass 33, count 2 2006.285.21:35:15.64#ibcon#wrote, iclass 33, count 2 2006.285.21:35:15.64#ibcon#about to read 3, iclass 33, count 2 2006.285.21:35:15.66#ibcon#read 3, iclass 33, count 2 2006.285.21:35:15.66#ibcon#about to read 4, iclass 33, count 2 2006.285.21:35:15.66#ibcon#read 4, iclass 33, count 2 2006.285.21:35:15.66#ibcon#about to read 5, iclass 33, count 2 2006.285.21:35:15.66#ibcon#read 5, iclass 33, count 2 2006.285.21:35:15.66#ibcon#about to read 6, iclass 33, count 2 2006.285.21:35:15.66#ibcon#read 6, iclass 33, count 2 2006.285.21:35:15.66#ibcon#end of sib2, iclass 33, count 2 2006.285.21:35:15.66#ibcon#*mode == 0, iclass 33, count 2 2006.285.21:35:15.66#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.21:35:15.66#ibcon#[27=AT07-04\r\n] 2006.285.21:35:15.66#ibcon#*before write, iclass 33, count 2 2006.285.21:35:15.66#ibcon#enter sib2, iclass 33, count 2 2006.285.21:35:15.66#ibcon#flushed, iclass 33, count 2 2006.285.21:35:15.66#ibcon#about to write, iclass 33, count 2 2006.285.21:35:15.66#ibcon#wrote, iclass 33, count 2 2006.285.21:35:15.66#ibcon#about to read 3, iclass 33, count 2 2006.285.21:35:15.69#ibcon#read 3, iclass 33, count 2 2006.285.21:35:15.69#ibcon#about to read 4, iclass 33, count 2 2006.285.21:35:15.69#ibcon#read 4, iclass 33, count 2 2006.285.21:35:15.69#ibcon#about to read 5, iclass 33, count 2 2006.285.21:35:15.69#ibcon#read 5, iclass 33, count 2 2006.285.21:35:15.69#ibcon#about to read 6, iclass 33, count 2 2006.285.21:35:15.69#ibcon#read 6, iclass 33, count 2 2006.285.21:35:15.69#ibcon#end of sib2, iclass 33, count 2 2006.285.21:35:15.69#ibcon#*after write, iclass 33, count 2 2006.285.21:35:15.69#ibcon#*before return 0, iclass 33, count 2 2006.285.21:35:15.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:35:15.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.21:35:15.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.21:35:15.69#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:15.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:35:15.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:35:15.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:35:15.81#ibcon#enter wrdev, iclass 33, count 0 2006.285.21:35:15.81#ibcon#first serial, iclass 33, count 0 2006.285.21:35:15.81#ibcon#enter sib2, iclass 33, count 0 2006.285.21:35:15.81#ibcon#flushed, iclass 33, count 0 2006.285.21:35:15.81#ibcon#about to write, iclass 33, count 0 2006.285.21:35:15.81#ibcon#wrote, iclass 33, count 0 2006.285.21:35:15.81#ibcon#about to read 3, iclass 33, count 0 2006.285.21:35:15.83#ibcon#read 3, iclass 33, count 0 2006.285.21:35:15.83#ibcon#about to read 4, iclass 33, count 0 2006.285.21:35:15.83#ibcon#read 4, iclass 33, count 0 2006.285.21:35:15.83#ibcon#about to read 5, iclass 33, count 0 2006.285.21:35:15.83#ibcon#read 5, iclass 33, count 0 2006.285.21:35:15.83#ibcon#about to read 6, iclass 33, count 0 2006.285.21:35:15.83#ibcon#read 6, iclass 33, count 0 2006.285.21:35:15.83#ibcon#end of sib2, iclass 33, count 0 2006.285.21:35:15.83#ibcon#*mode == 0, iclass 33, count 0 2006.285.21:35:15.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.21:35:15.83#ibcon#[27=USB\r\n] 2006.285.21:35:15.83#ibcon#*before write, iclass 33, count 0 2006.285.21:35:15.83#ibcon#enter sib2, iclass 33, count 0 2006.285.21:35:15.83#ibcon#flushed, iclass 33, count 0 2006.285.21:35:15.83#ibcon#about to write, iclass 33, count 0 2006.285.21:35:15.83#ibcon#wrote, iclass 33, count 0 2006.285.21:35:15.83#ibcon#about to read 3, iclass 33, count 0 2006.285.21:35:15.86#ibcon#read 3, iclass 33, count 0 2006.285.21:35:15.86#ibcon#about to read 4, iclass 33, count 0 2006.285.21:35:15.86#ibcon#read 4, iclass 33, count 0 2006.285.21:35:15.86#ibcon#about to read 5, iclass 33, count 0 2006.285.21:35:15.86#ibcon#read 5, iclass 33, count 0 2006.285.21:35:15.86#ibcon#about to read 6, iclass 33, count 0 2006.285.21:35:15.86#ibcon#read 6, iclass 33, count 0 2006.285.21:35:15.86#ibcon#end of sib2, iclass 33, count 0 2006.285.21:35:15.86#ibcon#*after write, iclass 33, count 0 2006.285.21:35:15.86#ibcon#*before return 0, iclass 33, count 0 2006.285.21:35:15.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:35:15.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.21:35:15.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.21:35:15.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.21:35:15.86$vck44/vblo=8,744.99 2006.285.21:35:15.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.21:35:15.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.21:35:15.86#ibcon#ireg 17 cls_cnt 0 2006.285.21:35:15.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:35:15.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:35:15.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:35:15.86#ibcon#enter wrdev, iclass 35, count 0 2006.285.21:35:15.86#ibcon#first serial, iclass 35, count 0 2006.285.21:35:15.86#ibcon#enter sib2, iclass 35, count 0 2006.285.21:35:15.86#ibcon#flushed, iclass 35, count 0 2006.285.21:35:15.86#ibcon#about to write, iclass 35, count 0 2006.285.21:35:15.86#ibcon#wrote, iclass 35, count 0 2006.285.21:35:15.86#ibcon#about to read 3, iclass 35, count 0 2006.285.21:35:15.88#ibcon#read 3, iclass 35, count 0 2006.285.21:35:15.94#ibcon#about to read 4, iclass 35, count 0 2006.285.21:35:15.94#ibcon#read 4, iclass 35, count 0 2006.285.21:35:15.94#ibcon#about to read 5, iclass 35, count 0 2006.285.21:35:15.94#ibcon#read 5, iclass 35, count 0 2006.285.21:35:15.94#ibcon#about to read 6, iclass 35, count 0 2006.285.21:35:15.94#ibcon#read 6, iclass 35, count 0 2006.285.21:35:15.94#ibcon#end of sib2, iclass 35, count 0 2006.285.21:35:15.94#ibcon#*mode == 0, iclass 35, count 0 2006.285.21:35:15.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.21:35:15.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:35:15.94#ibcon#*before write, iclass 35, count 0 2006.285.21:35:15.94#ibcon#enter sib2, iclass 35, count 0 2006.285.21:35:15.94#ibcon#flushed, iclass 35, count 0 2006.285.21:35:15.94#ibcon#about to write, iclass 35, count 0 2006.285.21:35:15.94#ibcon#wrote, iclass 35, count 0 2006.285.21:35:15.94#ibcon#about to read 3, iclass 35, count 0 2006.285.21:35:15.98#ibcon#read 3, iclass 35, count 0 2006.285.21:35:15.98#ibcon#about to read 4, iclass 35, count 0 2006.285.21:35:15.98#ibcon#read 4, iclass 35, count 0 2006.285.21:35:15.98#ibcon#about to read 5, iclass 35, count 0 2006.285.21:35:15.98#ibcon#read 5, iclass 35, count 0 2006.285.21:35:15.98#ibcon#about to read 6, iclass 35, count 0 2006.285.21:35:15.98#ibcon#read 6, iclass 35, count 0 2006.285.21:35:15.98#ibcon#end of sib2, iclass 35, count 0 2006.285.21:35:15.98#ibcon#*after write, iclass 35, count 0 2006.285.21:35:15.98#ibcon#*before return 0, iclass 35, count 0 2006.285.21:35:15.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:35:15.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:35:15.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.21:35:15.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.21:35:15.98$vck44/vb=8,4 2006.285.21:35:15.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.21:35:15.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.21:35:15.98#ibcon#ireg 11 cls_cnt 2 2006.285.21:35:15.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:35:15.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:35:15.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:35:15.98#ibcon#enter wrdev, iclass 37, count 2 2006.285.21:35:15.98#ibcon#first serial, iclass 37, count 2 2006.285.21:35:15.98#ibcon#enter sib2, iclass 37, count 2 2006.285.21:35:15.98#ibcon#flushed, iclass 37, count 2 2006.285.21:35:15.98#ibcon#about to write, iclass 37, count 2 2006.285.21:35:15.98#ibcon#wrote, iclass 37, count 2 2006.285.21:35:15.98#ibcon#about to read 3, iclass 37, count 2 2006.285.21:35:16.00#ibcon#read 3, iclass 37, count 2 2006.285.21:35:16.00#ibcon#about to read 4, iclass 37, count 2 2006.285.21:35:16.00#ibcon#read 4, iclass 37, count 2 2006.285.21:35:16.00#ibcon#about to read 5, iclass 37, count 2 2006.285.21:35:16.00#ibcon#read 5, iclass 37, count 2 2006.285.21:35:16.00#ibcon#about to read 6, iclass 37, count 2 2006.285.21:35:16.00#ibcon#read 6, iclass 37, count 2 2006.285.21:35:16.00#ibcon#end of sib2, iclass 37, count 2 2006.285.21:35:16.00#ibcon#*mode == 0, iclass 37, count 2 2006.285.21:35:16.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.21:35:16.00#ibcon#[27=AT08-04\r\n] 2006.285.21:35:16.00#ibcon#*before write, iclass 37, count 2 2006.285.21:35:16.00#ibcon#enter sib2, iclass 37, count 2 2006.285.21:35:16.00#ibcon#flushed, iclass 37, count 2 2006.285.21:35:16.00#ibcon#about to write, iclass 37, count 2 2006.285.21:35:16.00#ibcon#wrote, iclass 37, count 2 2006.285.21:35:16.00#ibcon#about to read 3, iclass 37, count 2 2006.285.21:35:16.03#ibcon#read 3, iclass 37, count 2 2006.285.21:35:16.03#ibcon#about to read 4, iclass 37, count 2 2006.285.21:35:16.03#ibcon#read 4, iclass 37, count 2 2006.285.21:35:16.03#ibcon#about to read 5, iclass 37, count 2 2006.285.21:35:16.03#ibcon#read 5, iclass 37, count 2 2006.285.21:35:16.03#ibcon#about to read 6, iclass 37, count 2 2006.285.21:35:16.03#ibcon#read 6, iclass 37, count 2 2006.285.21:35:16.03#ibcon#end of sib2, iclass 37, count 2 2006.285.21:35:16.03#ibcon#*after write, iclass 37, count 2 2006.285.21:35:16.03#ibcon#*before return 0, iclass 37, count 2 2006.285.21:35:16.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:35:16.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.21:35:16.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.21:35:16.03#ibcon#ireg 7 cls_cnt 0 2006.285.21:35:16.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:35:16.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:35:16.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:35:16.15#ibcon#enter wrdev, iclass 37, count 0 2006.285.21:35:16.15#ibcon#first serial, iclass 37, count 0 2006.285.21:35:16.15#ibcon#enter sib2, iclass 37, count 0 2006.285.21:35:16.15#ibcon#flushed, iclass 37, count 0 2006.285.21:35:16.15#ibcon#about to write, iclass 37, count 0 2006.285.21:35:16.15#ibcon#wrote, iclass 37, count 0 2006.285.21:35:16.15#ibcon#about to read 3, iclass 37, count 0 2006.285.21:35:16.17#ibcon#read 3, iclass 37, count 0 2006.285.21:35:16.17#ibcon#about to read 4, iclass 37, count 0 2006.285.21:35:16.17#ibcon#read 4, iclass 37, count 0 2006.285.21:35:16.17#ibcon#about to read 5, iclass 37, count 0 2006.285.21:35:16.17#ibcon#read 5, iclass 37, count 0 2006.285.21:35:16.17#ibcon#about to read 6, iclass 37, count 0 2006.285.21:35:16.17#ibcon#read 6, iclass 37, count 0 2006.285.21:35:16.17#ibcon#end of sib2, iclass 37, count 0 2006.285.21:35:16.17#ibcon#*mode == 0, iclass 37, count 0 2006.285.21:35:16.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.21:35:16.17#ibcon#[27=USB\r\n] 2006.285.21:35:16.17#ibcon#*before write, iclass 37, count 0 2006.285.21:35:16.17#ibcon#enter sib2, iclass 37, count 0 2006.285.21:35:16.17#ibcon#flushed, iclass 37, count 0 2006.285.21:35:16.17#ibcon#about to write, iclass 37, count 0 2006.285.21:35:16.17#ibcon#wrote, iclass 37, count 0 2006.285.21:35:16.17#ibcon#about to read 3, iclass 37, count 0 2006.285.21:35:16.20#ibcon#read 3, iclass 37, count 0 2006.285.21:35:16.20#ibcon#about to read 4, iclass 37, count 0 2006.285.21:35:16.20#ibcon#read 4, iclass 37, count 0 2006.285.21:35:16.20#ibcon#about to read 5, iclass 37, count 0 2006.285.21:35:16.20#ibcon#read 5, iclass 37, count 0 2006.285.21:35:16.20#ibcon#about to read 6, iclass 37, count 0 2006.285.21:35:16.20#ibcon#read 6, iclass 37, count 0 2006.285.21:35:16.20#ibcon#end of sib2, iclass 37, count 0 2006.285.21:35:16.20#ibcon#*after write, iclass 37, count 0 2006.285.21:35:16.20#ibcon#*before return 0, iclass 37, count 0 2006.285.21:35:16.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:35:16.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.21:35:16.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.21:35:16.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.21:35:16.20$vck44/vabw=wide 2006.285.21:35:16.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.21:35:16.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.21:35:16.20#ibcon#ireg 8 cls_cnt 0 2006.285.21:35:16.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:35:16.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:35:16.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:35:16.20#ibcon#enter wrdev, iclass 39, count 0 2006.285.21:35:16.20#ibcon#first serial, iclass 39, count 0 2006.285.21:35:16.20#ibcon#enter sib2, iclass 39, count 0 2006.285.21:35:16.20#ibcon#flushed, iclass 39, count 0 2006.285.21:35:16.20#ibcon#about to write, iclass 39, count 0 2006.285.21:35:16.20#ibcon#wrote, iclass 39, count 0 2006.285.21:35:16.20#ibcon#about to read 3, iclass 39, count 0 2006.285.21:35:16.22#ibcon#read 3, iclass 39, count 0 2006.285.21:35:16.22#ibcon#about to read 4, iclass 39, count 0 2006.285.21:35:16.22#ibcon#read 4, iclass 39, count 0 2006.285.21:35:16.22#ibcon#about to read 5, iclass 39, count 0 2006.285.21:35:16.22#ibcon#read 5, iclass 39, count 0 2006.285.21:35:16.22#ibcon#about to read 6, iclass 39, count 0 2006.285.21:35:16.22#ibcon#read 6, iclass 39, count 0 2006.285.21:35:16.22#ibcon#end of sib2, iclass 39, count 0 2006.285.21:35:16.22#ibcon#*mode == 0, iclass 39, count 0 2006.285.21:35:16.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.21:35:16.22#ibcon#[25=BW32\r\n] 2006.285.21:35:16.22#ibcon#*before write, iclass 39, count 0 2006.285.21:35:16.22#ibcon#enter sib2, iclass 39, count 0 2006.285.21:35:16.22#ibcon#flushed, iclass 39, count 0 2006.285.21:35:16.22#ibcon#about to write, iclass 39, count 0 2006.285.21:35:16.22#ibcon#wrote, iclass 39, count 0 2006.285.21:35:16.22#ibcon#about to read 3, iclass 39, count 0 2006.285.21:35:16.25#ibcon#read 3, iclass 39, count 0 2006.285.21:35:16.25#ibcon#about to read 4, iclass 39, count 0 2006.285.21:35:16.25#ibcon#read 4, iclass 39, count 0 2006.285.21:35:16.25#ibcon#about to read 5, iclass 39, count 0 2006.285.21:35:16.25#ibcon#read 5, iclass 39, count 0 2006.285.21:35:16.25#ibcon#about to read 6, iclass 39, count 0 2006.285.21:35:16.25#ibcon#read 6, iclass 39, count 0 2006.285.21:35:16.25#ibcon#end of sib2, iclass 39, count 0 2006.285.21:35:16.25#ibcon#*after write, iclass 39, count 0 2006.285.21:35:16.25#ibcon#*before return 0, iclass 39, count 0 2006.285.21:35:16.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:35:16.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.21:35:16.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.21:35:16.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.21:35:16.25$vck44/vbbw=wide 2006.285.21:35:16.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.21:35:16.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.21:35:16.25#ibcon#ireg 8 cls_cnt 0 2006.285.21:35:16.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:35:16.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:35:16.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:35:16.32#ibcon#enter wrdev, iclass 3, count 0 2006.285.21:35:16.32#ibcon#first serial, iclass 3, count 0 2006.285.21:35:16.32#ibcon#enter sib2, iclass 3, count 0 2006.285.21:35:16.32#ibcon#flushed, iclass 3, count 0 2006.285.21:35:16.32#ibcon#about to write, iclass 3, count 0 2006.285.21:35:16.32#ibcon#wrote, iclass 3, count 0 2006.285.21:35:16.32#ibcon#about to read 3, iclass 3, count 0 2006.285.21:35:16.34#ibcon#read 3, iclass 3, count 0 2006.285.21:35:16.34#ibcon#about to read 4, iclass 3, count 0 2006.285.21:35:16.34#ibcon#read 4, iclass 3, count 0 2006.285.21:35:16.34#ibcon#about to read 5, iclass 3, count 0 2006.285.21:35:16.34#ibcon#read 5, iclass 3, count 0 2006.285.21:35:16.34#ibcon#about to read 6, iclass 3, count 0 2006.285.21:35:16.34#ibcon#read 6, iclass 3, count 0 2006.285.21:35:16.34#ibcon#end of sib2, iclass 3, count 0 2006.285.21:35:16.34#ibcon#*mode == 0, iclass 3, count 0 2006.285.21:35:16.34#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.21:35:16.34#ibcon#[27=BW32\r\n] 2006.285.21:35:16.34#ibcon#*before write, iclass 3, count 0 2006.285.21:35:16.34#ibcon#enter sib2, iclass 3, count 0 2006.285.21:35:16.34#ibcon#flushed, iclass 3, count 0 2006.285.21:35:16.34#ibcon#about to write, iclass 3, count 0 2006.285.21:35:16.34#ibcon#wrote, iclass 3, count 0 2006.285.21:35:16.34#ibcon#about to read 3, iclass 3, count 0 2006.285.21:35:16.37#ibcon#read 3, iclass 3, count 0 2006.285.21:35:16.37#ibcon#about to read 4, iclass 3, count 0 2006.285.21:35:16.37#ibcon#read 4, iclass 3, count 0 2006.285.21:35:16.37#ibcon#about to read 5, iclass 3, count 0 2006.285.21:35:16.37#ibcon#read 5, iclass 3, count 0 2006.285.21:35:16.37#ibcon#about to read 6, iclass 3, count 0 2006.285.21:35:16.37#ibcon#read 6, iclass 3, count 0 2006.285.21:35:16.37#ibcon#end of sib2, iclass 3, count 0 2006.285.21:35:16.37#ibcon#*after write, iclass 3, count 0 2006.285.21:35:16.37#ibcon#*before return 0, iclass 3, count 0 2006.285.21:35:16.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:35:16.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:35:16.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.21:35:16.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.21:35:16.37$setupk4/ifdk4 2006.285.21:35:16.37$ifdk4/lo= 2006.285.21:35:16.37$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:35:16.37$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:35:16.37$ifdk4/patch= 2006.285.21:35:16.37$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:35:16.37$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:35:16.37$setupk4/!*+20s 2006.285.21:35:18.87#abcon#<5=/15 0.4 1.2 14.691001015.7\r\n> 2006.285.21:35:18.89#abcon#{5=INTERFACE CLEAR} 2006.285.21:35:18.95#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:35:29.04#abcon#<5=/15 0.4 1.1 14.701001015.7\r\n> 2006.285.21:35:29.06#abcon#{5=INTERFACE CLEAR} 2006.285.21:35:29.12#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:35:30.54$setupk4/"tpicd 2006.285.21:35:30.54$setupk4/echo=off 2006.285.21:35:30.54$setupk4/xlog=off 2006.285.21:35:30.54:!2006.285.21:38:39 2006.285.21:36:18.14#trakl#Source acquired 2006.285.21:36:20.14#flagr#flagr/antenna,acquired 2006.285.21:38:39.00:preob 2006.285.21:38:39.14/onsource/TRACKING 2006.285.21:38:39.14:!2006.285.21:38:49 2006.285.21:38:49.00:"tape 2006.285.21:38:49.00:"st=record 2006.285.21:38:49.00:data_valid=on 2006.285.21:38:49.00:midob 2006.285.21:38:50.14/onsource/TRACKING 2006.285.21:38:50.14/wx/14.83,1015.8,100 2006.285.21:38:50.24/cable/+6.5109E-03 2006.285.21:38:51.33/va/01,07,usb,yes,33,36 2006.285.21:38:51.33/va/02,06,usb,yes,34,34 2006.285.21:38:51.33/va/03,07,usb,yes,33,35 2006.285.21:38:51.33/va/04,06,usb,yes,35,36 2006.285.21:38:51.33/va/05,03,usb,yes,34,35 2006.285.21:38:51.33/va/06,04,usb,yes,31,30 2006.285.21:38:51.33/va/07,04,usb,yes,31,32 2006.285.21:38:51.33/va/08,03,usb,yes,32,39 2006.285.21:38:51.56/valo/01,524.99,yes,locked 2006.285.21:38:51.56/valo/02,534.99,yes,locked 2006.285.21:38:51.56/valo/03,564.99,yes,locked 2006.285.21:38:51.56/valo/04,624.99,yes,locked 2006.285.21:38:51.56/valo/05,734.99,yes,locked 2006.285.21:38:51.56/valo/06,814.99,yes,locked 2006.285.21:38:51.56/valo/07,864.99,yes,locked 2006.285.21:38:51.56/valo/08,884.99,yes,locked 2006.285.21:38:52.65/vb/01,04,usb,yes,30,28 2006.285.21:38:52.65/vb/02,05,usb,yes,28,28 2006.285.21:38:52.65/vb/03,04,usb,yes,29,32 2006.285.21:38:52.65/vb/04,05,usb,yes,29,28 2006.285.21:38:52.65/vb/05,04,usb,yes,26,28 2006.285.21:38:52.65/vb/06,03,usb,yes,37,33 2006.285.21:38:52.65/vb/07,04,usb,yes,30,30 2006.285.21:38:52.65/vb/08,04,usb,yes,27,31 2006.285.21:38:52.88/vblo/01,629.99,yes,locked 2006.285.21:38:52.88/vblo/02,634.99,yes,locked 2006.285.21:38:52.88/vblo/03,649.99,yes,locked 2006.285.21:38:52.88/vblo/04,679.99,yes,locked 2006.285.21:38:52.88/vblo/05,709.99,yes,locked 2006.285.21:38:52.88/vblo/06,719.99,yes,locked 2006.285.21:38:52.88/vblo/07,734.99,yes,locked 2006.285.21:38:52.88/vblo/08,744.99,yes,locked 2006.285.21:38:53.03/vabw/8 2006.285.21:38:53.18/vbbw/8 2006.285.21:38:53.27/xfe/off,on,12.0 2006.285.21:38:53.64/ifatt/23,28,28,28 2006.285.21:38:54.07/fmout-gps/S +2.69E-07 2006.285.21:38:54.09:!2006.285.21:44:19 2006.285.21:44:19.00:data_valid=off 2006.285.21:44:19.00:"et 2006.285.21:44:19.00:!+3s 2006.285.21:44:22.01:"tape 2006.285.21:44:22.01:postob 2006.285.21:44:22.11/cable/+6.5137E-03 2006.285.21:44:22.11/wx/15.08,1015.9,100 2006.285.21:44:23.08/fmout-gps/S +2.67E-07 2006.285.21:44:23.08:scan_name=285-2149,jd0610,50 2006.285.21:44:23.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.285.21:44:23.14#flagr#flagr/antenna,new-source 2006.285.21:44:24.14:checkk5 2006.285.21:44:24.98/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:44:25.43/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:44:25.84/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:44:26.46/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:44:26.82/chk_obsdata//k5ts1/T2852138??a.dat file size is correct (nominal:1320MB, actual:1316MB). 2006.285.21:44:27.48/chk_obsdata//k5ts2/T2852138??b.dat file size is correct (nominal:1320MB, actual:1316MB). 2006.285.21:44:27.84/chk_obsdata//k5ts3/T2852138??c.dat file size is correct (nominal:1320MB, actual:1316MB). 2006.285.21:44:28.27/chk_obsdata//k5ts4/T2852138??d.dat file size is correct (nominal:1320MB, actual:1316MB). 2006.285.21:44:29.12/k5log//k5ts1_log_newline 2006.285.21:44:29.93/k5log//k5ts2_log_newline 2006.285.21:44:30.78/k5log//k5ts3_log_newline 2006.285.21:44:31.63/k5log//k5ts4_log_newline 2006.285.21:44:31.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:44:31.65:setupk4=1 2006.285.21:44:31.65$setupk4/echo=on 2006.285.21:44:31.65$setupk4/pcalon 2006.285.21:44:31.65$pcalon/"no phase cal control is implemented here 2006.285.21:44:31.65$setupk4/"tpicd=stop 2006.285.21:44:31.65$setupk4/"rec=synch_on 2006.285.21:44:31.65$setupk4/"rec_mode=128 2006.285.21:44:31.65$setupk4/!* 2006.285.21:44:31.65$setupk4/recpk4 2006.285.21:44:31.65$recpk4/recpatch= 2006.285.21:44:31.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:44:31.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:44:31.65$setupk4/vck44 2006.285.21:44:31.65$vck44/valo=1,524.99 2006.285.21:44:31.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.21:44:31.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.21:44:31.66#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:31.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:44:31.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:44:31.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:44:31.66#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:44:31.66#ibcon#first serial, iclass 14, count 0 2006.285.21:44:31.66#ibcon#enter sib2, iclass 14, count 0 2006.285.21:44:31.66#ibcon#flushed, iclass 14, count 0 2006.285.21:44:31.66#ibcon#about to write, iclass 14, count 0 2006.285.21:44:31.66#ibcon#wrote, iclass 14, count 0 2006.285.21:44:31.66#ibcon#about to read 3, iclass 14, count 0 2006.285.21:44:31.67#ibcon#read 3, iclass 14, count 0 2006.285.21:44:31.67#ibcon#about to read 4, iclass 14, count 0 2006.285.21:44:31.67#ibcon#read 4, iclass 14, count 0 2006.285.21:44:31.67#ibcon#about to read 5, iclass 14, count 0 2006.285.21:44:31.67#ibcon#read 5, iclass 14, count 0 2006.285.21:44:31.67#ibcon#about to read 6, iclass 14, count 0 2006.285.21:44:31.67#ibcon#read 6, iclass 14, count 0 2006.285.21:44:31.67#ibcon#end of sib2, iclass 14, count 0 2006.285.21:44:31.67#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:44:31.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:44:31.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:44:31.67#ibcon#*before write, iclass 14, count 0 2006.285.21:44:31.67#ibcon#enter sib2, iclass 14, count 0 2006.285.21:44:31.67#ibcon#flushed, iclass 14, count 0 2006.285.21:44:31.67#ibcon#about to write, iclass 14, count 0 2006.285.21:44:31.67#ibcon#wrote, iclass 14, count 0 2006.285.21:44:31.67#ibcon#about to read 3, iclass 14, count 0 2006.285.21:44:31.72#ibcon#read 3, iclass 14, count 0 2006.285.21:44:31.72#ibcon#about to read 4, iclass 14, count 0 2006.285.21:44:31.72#ibcon#read 4, iclass 14, count 0 2006.285.21:44:31.72#ibcon#about to read 5, iclass 14, count 0 2006.285.21:44:31.72#ibcon#read 5, iclass 14, count 0 2006.285.21:44:31.72#ibcon#about to read 6, iclass 14, count 0 2006.285.21:44:31.72#ibcon#read 6, iclass 14, count 0 2006.285.21:44:31.72#ibcon#end of sib2, iclass 14, count 0 2006.285.21:44:31.72#ibcon#*after write, iclass 14, count 0 2006.285.21:44:31.72#ibcon#*before return 0, iclass 14, count 0 2006.285.21:44:31.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:44:31.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:44:31.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:44:31.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:44:31.72$vck44/va=1,7 2006.285.21:44:31.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.21:44:31.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.21:44:31.72#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:31.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:44:31.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:44:31.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:44:31.72#ibcon#enter wrdev, iclass 16, count 2 2006.285.21:44:31.72#ibcon#first serial, iclass 16, count 2 2006.285.21:44:31.72#ibcon#enter sib2, iclass 16, count 2 2006.285.21:44:31.72#ibcon#flushed, iclass 16, count 2 2006.285.21:44:31.72#ibcon#about to write, iclass 16, count 2 2006.285.21:44:31.72#ibcon#wrote, iclass 16, count 2 2006.285.21:44:31.72#ibcon#about to read 3, iclass 16, count 2 2006.285.21:44:31.74#ibcon#read 3, iclass 16, count 2 2006.285.21:44:31.74#ibcon#about to read 4, iclass 16, count 2 2006.285.21:44:31.74#ibcon#read 4, iclass 16, count 2 2006.285.21:44:31.74#ibcon#about to read 5, iclass 16, count 2 2006.285.21:44:31.74#ibcon#read 5, iclass 16, count 2 2006.285.21:44:31.74#ibcon#about to read 6, iclass 16, count 2 2006.285.21:44:31.74#ibcon#read 6, iclass 16, count 2 2006.285.21:44:31.74#ibcon#end of sib2, iclass 16, count 2 2006.285.21:44:31.74#ibcon#*mode == 0, iclass 16, count 2 2006.285.21:44:31.74#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.21:44:31.74#ibcon#[25=AT01-07\r\n] 2006.285.21:44:31.74#ibcon#*before write, iclass 16, count 2 2006.285.21:44:31.74#ibcon#enter sib2, iclass 16, count 2 2006.285.21:44:31.74#ibcon#flushed, iclass 16, count 2 2006.285.21:44:31.74#ibcon#about to write, iclass 16, count 2 2006.285.21:44:31.74#ibcon#wrote, iclass 16, count 2 2006.285.21:44:31.74#ibcon#about to read 3, iclass 16, count 2 2006.285.21:44:31.77#ibcon#read 3, iclass 16, count 2 2006.285.21:44:31.77#ibcon#about to read 4, iclass 16, count 2 2006.285.21:44:31.77#ibcon#read 4, iclass 16, count 2 2006.285.21:44:31.77#ibcon#about to read 5, iclass 16, count 2 2006.285.21:44:31.77#ibcon#read 5, iclass 16, count 2 2006.285.21:44:31.77#ibcon#about to read 6, iclass 16, count 2 2006.285.21:44:31.77#ibcon#read 6, iclass 16, count 2 2006.285.21:44:31.77#ibcon#end of sib2, iclass 16, count 2 2006.285.21:44:31.77#ibcon#*after write, iclass 16, count 2 2006.285.21:44:31.77#ibcon#*before return 0, iclass 16, count 2 2006.285.21:44:31.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:44:31.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:44:31.77#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.21:44:31.77#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:31.77#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:44:31.89#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:44:31.89#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:44:31.89#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:44:31.89#ibcon#first serial, iclass 16, count 0 2006.285.21:44:31.89#ibcon#enter sib2, iclass 16, count 0 2006.285.21:44:31.89#ibcon#flushed, iclass 16, count 0 2006.285.21:44:31.89#ibcon#about to write, iclass 16, count 0 2006.285.21:44:31.89#ibcon#wrote, iclass 16, count 0 2006.285.21:44:31.89#ibcon#about to read 3, iclass 16, count 0 2006.285.21:44:31.91#ibcon#read 3, iclass 16, count 0 2006.285.21:44:31.91#ibcon#about to read 4, iclass 16, count 0 2006.285.21:44:31.91#ibcon#read 4, iclass 16, count 0 2006.285.21:44:31.91#ibcon#about to read 5, iclass 16, count 0 2006.285.21:44:31.91#ibcon#read 5, iclass 16, count 0 2006.285.21:44:31.91#ibcon#about to read 6, iclass 16, count 0 2006.285.21:44:31.91#ibcon#read 6, iclass 16, count 0 2006.285.21:44:31.91#ibcon#end of sib2, iclass 16, count 0 2006.285.21:44:31.91#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:44:31.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:44:31.91#ibcon#[25=USB\r\n] 2006.285.21:44:31.91#ibcon#*before write, iclass 16, count 0 2006.285.21:44:31.91#ibcon#enter sib2, iclass 16, count 0 2006.285.21:44:31.91#ibcon#flushed, iclass 16, count 0 2006.285.21:44:31.91#ibcon#about to write, iclass 16, count 0 2006.285.21:44:31.91#ibcon#wrote, iclass 16, count 0 2006.285.21:44:31.91#ibcon#about to read 3, iclass 16, count 0 2006.285.21:44:31.94#ibcon#read 3, iclass 16, count 0 2006.285.21:44:31.94#ibcon#about to read 4, iclass 16, count 0 2006.285.21:44:31.94#ibcon#read 4, iclass 16, count 0 2006.285.21:44:31.94#ibcon#about to read 5, iclass 16, count 0 2006.285.21:44:31.94#ibcon#read 5, iclass 16, count 0 2006.285.21:44:31.94#ibcon#about to read 6, iclass 16, count 0 2006.285.21:44:31.94#ibcon#read 6, iclass 16, count 0 2006.285.21:44:31.94#ibcon#end of sib2, iclass 16, count 0 2006.285.21:44:31.94#ibcon#*after write, iclass 16, count 0 2006.285.21:44:31.94#ibcon#*before return 0, iclass 16, count 0 2006.285.21:44:31.94#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:44:31.94#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:44:31.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:44:31.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:44:31.94$vck44/valo=2,534.99 2006.285.21:44:31.94#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.21:44:31.94#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.21:44:31.94#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:31.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:44:31.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:44:31.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:44:31.94#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:44:31.94#ibcon#first serial, iclass 18, count 0 2006.285.21:44:31.94#ibcon#enter sib2, iclass 18, count 0 2006.285.21:44:31.94#ibcon#flushed, iclass 18, count 0 2006.285.21:44:31.94#ibcon#about to write, iclass 18, count 0 2006.285.21:44:31.94#ibcon#wrote, iclass 18, count 0 2006.285.21:44:31.94#ibcon#about to read 3, iclass 18, count 0 2006.285.21:44:31.96#ibcon#read 3, iclass 18, count 0 2006.285.21:44:31.96#ibcon#about to read 4, iclass 18, count 0 2006.285.21:44:31.96#ibcon#read 4, iclass 18, count 0 2006.285.21:44:31.96#ibcon#about to read 5, iclass 18, count 0 2006.285.21:44:31.96#ibcon#read 5, iclass 18, count 0 2006.285.21:44:31.96#ibcon#about to read 6, iclass 18, count 0 2006.285.21:44:31.96#ibcon#read 6, iclass 18, count 0 2006.285.21:44:31.96#ibcon#end of sib2, iclass 18, count 0 2006.285.21:44:31.96#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:44:31.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:44:31.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:44:31.96#ibcon#*before write, iclass 18, count 0 2006.285.21:44:31.96#ibcon#enter sib2, iclass 18, count 0 2006.285.21:44:31.96#ibcon#flushed, iclass 18, count 0 2006.285.21:44:31.96#ibcon#about to write, iclass 18, count 0 2006.285.21:44:31.96#ibcon#wrote, iclass 18, count 0 2006.285.21:44:31.96#ibcon#about to read 3, iclass 18, count 0 2006.285.21:44:32.00#ibcon#read 3, iclass 18, count 0 2006.285.21:44:32.00#ibcon#about to read 4, iclass 18, count 0 2006.285.21:44:32.00#ibcon#read 4, iclass 18, count 0 2006.285.21:44:32.00#ibcon#about to read 5, iclass 18, count 0 2006.285.21:44:32.00#ibcon#read 5, iclass 18, count 0 2006.285.21:44:32.00#ibcon#about to read 6, iclass 18, count 0 2006.285.21:44:32.00#ibcon#read 6, iclass 18, count 0 2006.285.21:44:32.00#ibcon#end of sib2, iclass 18, count 0 2006.285.21:44:32.00#ibcon#*after write, iclass 18, count 0 2006.285.21:44:32.00#ibcon#*before return 0, iclass 18, count 0 2006.285.21:44:32.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:44:32.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:44:32.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:44:32.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:44:32.00$vck44/va=2,6 2006.285.21:44:32.00#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.21:44:32.00#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.21:44:32.00#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:32.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:44:32.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:44:32.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:44:32.06#ibcon#enter wrdev, iclass 20, count 2 2006.285.21:44:32.06#ibcon#first serial, iclass 20, count 2 2006.285.21:44:32.06#ibcon#enter sib2, iclass 20, count 2 2006.285.21:44:32.06#ibcon#flushed, iclass 20, count 2 2006.285.21:44:32.06#ibcon#about to write, iclass 20, count 2 2006.285.21:44:32.06#ibcon#wrote, iclass 20, count 2 2006.285.21:44:32.06#ibcon#about to read 3, iclass 20, count 2 2006.285.21:44:32.08#ibcon#read 3, iclass 20, count 2 2006.285.21:44:32.08#ibcon#about to read 4, iclass 20, count 2 2006.285.21:44:32.08#ibcon#read 4, iclass 20, count 2 2006.285.21:44:32.08#ibcon#about to read 5, iclass 20, count 2 2006.285.21:44:32.08#ibcon#read 5, iclass 20, count 2 2006.285.21:44:32.08#ibcon#about to read 6, iclass 20, count 2 2006.285.21:44:32.08#ibcon#read 6, iclass 20, count 2 2006.285.21:44:32.08#ibcon#end of sib2, iclass 20, count 2 2006.285.21:44:32.08#ibcon#*mode == 0, iclass 20, count 2 2006.285.21:44:32.08#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.21:44:32.08#ibcon#[25=AT02-06\r\n] 2006.285.21:44:32.08#ibcon#*before write, iclass 20, count 2 2006.285.21:44:32.08#ibcon#enter sib2, iclass 20, count 2 2006.285.21:44:32.08#ibcon#flushed, iclass 20, count 2 2006.285.21:44:32.08#ibcon#about to write, iclass 20, count 2 2006.285.21:44:32.08#ibcon#wrote, iclass 20, count 2 2006.285.21:44:32.08#ibcon#about to read 3, iclass 20, count 2 2006.285.21:44:32.11#ibcon#read 3, iclass 20, count 2 2006.285.21:44:32.11#ibcon#about to read 4, iclass 20, count 2 2006.285.21:44:32.11#ibcon#read 4, iclass 20, count 2 2006.285.21:44:32.11#ibcon#about to read 5, iclass 20, count 2 2006.285.21:44:32.11#ibcon#read 5, iclass 20, count 2 2006.285.21:44:32.11#ibcon#about to read 6, iclass 20, count 2 2006.285.21:44:32.11#ibcon#read 6, iclass 20, count 2 2006.285.21:44:32.11#ibcon#end of sib2, iclass 20, count 2 2006.285.21:44:32.11#ibcon#*after write, iclass 20, count 2 2006.285.21:44:32.11#ibcon#*before return 0, iclass 20, count 2 2006.285.21:44:32.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:44:32.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:44:32.11#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.21:44:32.11#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:32.11#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:44:32.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:44:32.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:44:32.23#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:44:32.23#ibcon#first serial, iclass 20, count 0 2006.285.21:44:32.23#ibcon#enter sib2, iclass 20, count 0 2006.285.21:44:32.23#ibcon#flushed, iclass 20, count 0 2006.285.21:44:32.23#ibcon#about to write, iclass 20, count 0 2006.285.21:44:32.23#ibcon#wrote, iclass 20, count 0 2006.285.21:44:32.23#ibcon#about to read 3, iclass 20, count 0 2006.285.21:44:32.25#ibcon#read 3, iclass 20, count 0 2006.285.21:44:32.25#ibcon#about to read 4, iclass 20, count 0 2006.285.21:44:32.25#ibcon#read 4, iclass 20, count 0 2006.285.21:44:32.25#ibcon#about to read 5, iclass 20, count 0 2006.285.21:44:32.25#ibcon#read 5, iclass 20, count 0 2006.285.21:44:32.25#ibcon#about to read 6, iclass 20, count 0 2006.285.21:44:32.25#ibcon#read 6, iclass 20, count 0 2006.285.21:44:32.25#ibcon#end of sib2, iclass 20, count 0 2006.285.21:44:32.25#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:44:32.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:44:32.25#ibcon#[25=USB\r\n] 2006.285.21:44:32.25#ibcon#*before write, iclass 20, count 0 2006.285.21:44:32.25#ibcon#enter sib2, iclass 20, count 0 2006.285.21:44:32.25#ibcon#flushed, iclass 20, count 0 2006.285.21:44:32.25#ibcon#about to write, iclass 20, count 0 2006.285.21:44:32.25#ibcon#wrote, iclass 20, count 0 2006.285.21:44:32.25#ibcon#about to read 3, iclass 20, count 0 2006.285.21:44:32.28#ibcon#read 3, iclass 20, count 0 2006.285.21:44:32.28#ibcon#about to read 4, iclass 20, count 0 2006.285.21:44:32.28#ibcon#read 4, iclass 20, count 0 2006.285.21:44:32.28#ibcon#about to read 5, iclass 20, count 0 2006.285.21:44:32.28#ibcon#read 5, iclass 20, count 0 2006.285.21:44:32.28#ibcon#about to read 6, iclass 20, count 0 2006.285.21:44:32.28#ibcon#read 6, iclass 20, count 0 2006.285.21:44:32.28#ibcon#end of sib2, iclass 20, count 0 2006.285.21:44:32.28#ibcon#*after write, iclass 20, count 0 2006.285.21:44:32.28#ibcon#*before return 0, iclass 20, count 0 2006.285.21:44:32.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:44:32.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:44:32.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:44:32.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:44:32.28$vck44/valo=3,564.99 2006.285.21:44:32.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.21:44:32.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.21:44:32.28#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:32.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:44:32.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:44:32.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:44:32.28#ibcon#enter wrdev, iclass 22, count 0 2006.285.21:44:32.28#ibcon#first serial, iclass 22, count 0 2006.285.21:44:32.28#ibcon#enter sib2, iclass 22, count 0 2006.285.21:44:32.28#ibcon#flushed, iclass 22, count 0 2006.285.21:44:32.28#ibcon#about to write, iclass 22, count 0 2006.285.21:44:32.28#ibcon#wrote, iclass 22, count 0 2006.285.21:44:32.28#ibcon#about to read 3, iclass 22, count 0 2006.285.21:44:32.30#ibcon#read 3, iclass 22, count 0 2006.285.21:44:32.30#ibcon#about to read 4, iclass 22, count 0 2006.285.21:44:32.30#ibcon#read 4, iclass 22, count 0 2006.285.21:44:32.77#ibcon#about to read 5, iclass 22, count 0 2006.285.21:44:32.77#ibcon#read 5, iclass 22, count 0 2006.285.21:44:32.77#ibcon#about to read 6, iclass 22, count 0 2006.285.21:44:32.77#ibcon#read 6, iclass 22, count 0 2006.285.21:44:32.77#ibcon#end of sib2, iclass 22, count 0 2006.285.21:44:32.77#ibcon#*mode == 0, iclass 22, count 0 2006.285.21:44:32.77#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.21:44:32.77#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:44:32.77#ibcon#*before write, iclass 22, count 0 2006.285.21:44:32.77#ibcon#enter sib2, iclass 22, count 0 2006.285.21:44:32.77#ibcon#flushed, iclass 22, count 0 2006.285.21:44:32.77#ibcon#about to write, iclass 22, count 0 2006.285.21:44:32.77#ibcon#wrote, iclass 22, count 0 2006.285.21:44:32.77#ibcon#about to read 3, iclass 22, count 0 2006.285.21:44:32.82#ibcon#read 3, iclass 22, count 0 2006.285.21:44:32.82#ibcon#about to read 4, iclass 22, count 0 2006.285.21:44:32.82#ibcon#read 4, iclass 22, count 0 2006.285.21:44:32.82#ibcon#about to read 5, iclass 22, count 0 2006.285.21:44:32.82#ibcon#read 5, iclass 22, count 0 2006.285.21:44:32.82#ibcon#about to read 6, iclass 22, count 0 2006.285.21:44:32.82#ibcon#read 6, iclass 22, count 0 2006.285.21:44:32.82#ibcon#end of sib2, iclass 22, count 0 2006.285.21:44:32.82#ibcon#*after write, iclass 22, count 0 2006.285.21:44:32.82#ibcon#*before return 0, iclass 22, count 0 2006.285.21:44:32.82#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:44:32.82#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:44:32.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.21:44:32.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.21:44:32.82$vck44/va=3,7 2006.285.21:44:32.82#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.21:44:32.82#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.21:44:32.82#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:32.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:44:32.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:44:32.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:44:32.82#ibcon#enter wrdev, iclass 24, count 2 2006.285.21:44:32.82#ibcon#first serial, iclass 24, count 2 2006.285.21:44:32.82#ibcon#enter sib2, iclass 24, count 2 2006.285.21:44:32.82#ibcon#flushed, iclass 24, count 2 2006.285.21:44:32.82#ibcon#about to write, iclass 24, count 2 2006.285.21:44:32.82#ibcon#wrote, iclass 24, count 2 2006.285.21:44:32.82#ibcon#about to read 3, iclass 24, count 2 2006.285.21:44:32.84#ibcon#read 3, iclass 24, count 2 2006.285.21:44:32.84#ibcon#about to read 4, iclass 24, count 2 2006.285.21:44:32.84#ibcon#read 4, iclass 24, count 2 2006.285.21:44:32.84#ibcon#about to read 5, iclass 24, count 2 2006.285.21:44:32.84#ibcon#read 5, iclass 24, count 2 2006.285.21:44:32.84#ibcon#about to read 6, iclass 24, count 2 2006.285.21:44:32.84#ibcon#read 6, iclass 24, count 2 2006.285.21:44:32.84#ibcon#end of sib2, iclass 24, count 2 2006.285.21:44:32.84#ibcon#*mode == 0, iclass 24, count 2 2006.285.21:44:32.84#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.21:44:32.84#ibcon#[25=AT03-07\r\n] 2006.285.21:44:32.84#ibcon#*before write, iclass 24, count 2 2006.285.21:44:32.84#ibcon#enter sib2, iclass 24, count 2 2006.285.21:44:32.84#ibcon#flushed, iclass 24, count 2 2006.285.21:44:32.84#ibcon#about to write, iclass 24, count 2 2006.285.21:44:32.84#ibcon#wrote, iclass 24, count 2 2006.285.21:44:32.84#ibcon#about to read 3, iclass 24, count 2 2006.285.21:44:32.87#ibcon#read 3, iclass 24, count 2 2006.285.21:44:32.87#ibcon#about to read 4, iclass 24, count 2 2006.285.21:44:32.87#ibcon#read 4, iclass 24, count 2 2006.285.21:44:32.87#ibcon#about to read 5, iclass 24, count 2 2006.285.21:44:32.87#ibcon#read 5, iclass 24, count 2 2006.285.21:44:32.87#ibcon#about to read 6, iclass 24, count 2 2006.285.21:44:32.87#ibcon#read 6, iclass 24, count 2 2006.285.21:44:32.87#ibcon#end of sib2, iclass 24, count 2 2006.285.21:44:32.87#ibcon#*after write, iclass 24, count 2 2006.285.21:44:32.87#ibcon#*before return 0, iclass 24, count 2 2006.285.21:44:32.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:44:32.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:44:32.87#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.21:44:32.87#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:32.87#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:44:32.99#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:44:32.99#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:44:32.99#ibcon#enter wrdev, iclass 24, count 0 2006.285.21:44:32.99#ibcon#first serial, iclass 24, count 0 2006.285.21:44:32.99#ibcon#enter sib2, iclass 24, count 0 2006.285.21:44:32.99#ibcon#flushed, iclass 24, count 0 2006.285.21:44:32.99#ibcon#about to write, iclass 24, count 0 2006.285.21:44:32.99#ibcon#wrote, iclass 24, count 0 2006.285.21:44:32.99#ibcon#about to read 3, iclass 24, count 0 2006.285.21:44:33.01#ibcon#read 3, iclass 24, count 0 2006.285.21:44:33.01#ibcon#about to read 4, iclass 24, count 0 2006.285.21:44:33.01#ibcon#read 4, iclass 24, count 0 2006.285.21:44:33.01#ibcon#about to read 5, iclass 24, count 0 2006.285.21:44:33.01#ibcon#read 5, iclass 24, count 0 2006.285.21:44:33.01#ibcon#about to read 6, iclass 24, count 0 2006.285.21:44:33.01#ibcon#read 6, iclass 24, count 0 2006.285.21:44:33.01#ibcon#end of sib2, iclass 24, count 0 2006.285.21:44:33.01#ibcon#*mode == 0, iclass 24, count 0 2006.285.21:44:33.01#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.21:44:33.01#ibcon#[25=USB\r\n] 2006.285.21:44:33.01#ibcon#*before write, iclass 24, count 0 2006.285.21:44:33.01#ibcon#enter sib2, iclass 24, count 0 2006.285.21:44:33.01#ibcon#flushed, iclass 24, count 0 2006.285.21:44:33.01#ibcon#about to write, iclass 24, count 0 2006.285.21:44:33.01#ibcon#wrote, iclass 24, count 0 2006.285.21:44:33.01#ibcon#about to read 3, iclass 24, count 0 2006.285.21:44:33.04#ibcon#read 3, iclass 24, count 0 2006.285.21:44:33.04#ibcon#about to read 4, iclass 24, count 0 2006.285.21:44:33.04#ibcon#read 4, iclass 24, count 0 2006.285.21:44:33.04#ibcon#about to read 5, iclass 24, count 0 2006.285.21:44:33.04#ibcon#read 5, iclass 24, count 0 2006.285.21:44:33.04#ibcon#about to read 6, iclass 24, count 0 2006.285.21:44:33.04#ibcon#read 6, iclass 24, count 0 2006.285.21:44:33.04#ibcon#end of sib2, iclass 24, count 0 2006.285.21:44:33.04#ibcon#*after write, iclass 24, count 0 2006.285.21:44:33.04#ibcon#*before return 0, iclass 24, count 0 2006.285.21:44:33.04#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:44:33.04#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:44:33.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.21:44:33.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.21:44:33.04$vck44/valo=4,624.99 2006.285.21:44:33.04#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.21:44:33.04#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.21:44:33.04#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:33.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:44:33.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:44:33.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:44:33.04#ibcon#enter wrdev, iclass 26, count 0 2006.285.21:44:33.04#ibcon#first serial, iclass 26, count 0 2006.285.21:44:33.04#ibcon#enter sib2, iclass 26, count 0 2006.285.21:44:33.04#ibcon#flushed, iclass 26, count 0 2006.285.21:44:33.04#ibcon#about to write, iclass 26, count 0 2006.285.21:44:33.04#ibcon#wrote, iclass 26, count 0 2006.285.21:44:33.04#ibcon#about to read 3, iclass 26, count 0 2006.285.21:44:33.06#ibcon#read 3, iclass 26, count 0 2006.285.21:44:33.06#ibcon#about to read 4, iclass 26, count 0 2006.285.21:44:33.06#ibcon#read 4, iclass 26, count 0 2006.285.21:44:33.06#ibcon#about to read 5, iclass 26, count 0 2006.285.21:44:33.06#ibcon#read 5, iclass 26, count 0 2006.285.21:44:33.06#ibcon#about to read 6, iclass 26, count 0 2006.285.21:44:33.06#ibcon#read 6, iclass 26, count 0 2006.285.21:44:33.06#ibcon#end of sib2, iclass 26, count 0 2006.285.21:44:33.06#ibcon#*mode == 0, iclass 26, count 0 2006.285.21:44:33.06#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.21:44:33.06#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:44:33.06#ibcon#*before write, iclass 26, count 0 2006.285.21:44:33.06#ibcon#enter sib2, iclass 26, count 0 2006.285.21:44:33.06#ibcon#flushed, iclass 26, count 0 2006.285.21:44:33.06#ibcon#about to write, iclass 26, count 0 2006.285.21:44:33.06#ibcon#wrote, iclass 26, count 0 2006.285.21:44:33.06#ibcon#about to read 3, iclass 26, count 0 2006.285.21:44:33.10#ibcon#read 3, iclass 26, count 0 2006.285.21:44:33.10#ibcon#about to read 4, iclass 26, count 0 2006.285.21:44:33.10#ibcon#read 4, iclass 26, count 0 2006.285.21:44:33.10#ibcon#about to read 5, iclass 26, count 0 2006.285.21:44:33.10#ibcon#read 5, iclass 26, count 0 2006.285.21:44:33.10#ibcon#about to read 6, iclass 26, count 0 2006.285.21:44:33.10#ibcon#read 6, iclass 26, count 0 2006.285.21:44:33.10#ibcon#end of sib2, iclass 26, count 0 2006.285.21:44:33.10#ibcon#*after write, iclass 26, count 0 2006.285.21:44:33.10#ibcon#*before return 0, iclass 26, count 0 2006.285.21:44:33.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:44:33.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:44:33.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.21:44:33.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.21:44:33.10$vck44/va=4,6 2006.285.21:44:33.10#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.21:44:33.10#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.21:44:33.10#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:33.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:44:33.16#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:44:33.16#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:44:33.16#ibcon#enter wrdev, iclass 28, count 2 2006.285.21:44:33.16#ibcon#first serial, iclass 28, count 2 2006.285.21:44:33.16#ibcon#enter sib2, iclass 28, count 2 2006.285.21:44:33.16#ibcon#flushed, iclass 28, count 2 2006.285.21:44:33.16#ibcon#about to write, iclass 28, count 2 2006.285.21:44:33.16#ibcon#wrote, iclass 28, count 2 2006.285.21:44:33.16#ibcon#about to read 3, iclass 28, count 2 2006.285.21:44:33.18#ibcon#read 3, iclass 28, count 2 2006.285.21:44:33.18#ibcon#about to read 4, iclass 28, count 2 2006.285.21:44:33.18#ibcon#read 4, iclass 28, count 2 2006.285.21:44:33.18#ibcon#about to read 5, iclass 28, count 2 2006.285.21:44:33.18#ibcon#read 5, iclass 28, count 2 2006.285.21:44:33.18#ibcon#about to read 6, iclass 28, count 2 2006.285.21:44:33.18#ibcon#read 6, iclass 28, count 2 2006.285.21:44:33.18#ibcon#end of sib2, iclass 28, count 2 2006.285.21:44:33.18#ibcon#*mode == 0, iclass 28, count 2 2006.285.21:44:33.18#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.21:44:33.18#ibcon#[25=AT04-06\r\n] 2006.285.21:44:33.18#ibcon#*before write, iclass 28, count 2 2006.285.21:44:33.18#ibcon#enter sib2, iclass 28, count 2 2006.285.21:44:33.18#ibcon#flushed, iclass 28, count 2 2006.285.21:44:33.18#ibcon#about to write, iclass 28, count 2 2006.285.21:44:33.18#ibcon#wrote, iclass 28, count 2 2006.285.21:44:33.18#ibcon#about to read 3, iclass 28, count 2 2006.285.21:44:33.21#ibcon#read 3, iclass 28, count 2 2006.285.21:44:33.21#ibcon#about to read 4, iclass 28, count 2 2006.285.21:44:33.21#ibcon#read 4, iclass 28, count 2 2006.285.21:44:33.21#ibcon#about to read 5, iclass 28, count 2 2006.285.21:44:33.21#ibcon#read 5, iclass 28, count 2 2006.285.21:44:33.21#ibcon#about to read 6, iclass 28, count 2 2006.285.21:44:33.21#ibcon#read 6, iclass 28, count 2 2006.285.21:44:33.21#ibcon#end of sib2, iclass 28, count 2 2006.285.21:44:33.21#ibcon#*after write, iclass 28, count 2 2006.285.21:44:33.21#ibcon#*before return 0, iclass 28, count 2 2006.285.21:44:33.21#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:44:33.21#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:44:33.21#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.21:44:33.21#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:33.21#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:44:33.33#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:44:33.33#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:44:33.33#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:44:33.33#ibcon#first serial, iclass 28, count 0 2006.285.21:44:33.33#ibcon#enter sib2, iclass 28, count 0 2006.285.21:44:33.33#ibcon#flushed, iclass 28, count 0 2006.285.21:44:33.33#ibcon#about to write, iclass 28, count 0 2006.285.21:44:33.33#ibcon#wrote, iclass 28, count 0 2006.285.21:44:33.33#ibcon#about to read 3, iclass 28, count 0 2006.285.21:44:33.35#ibcon#read 3, iclass 28, count 0 2006.285.21:44:33.35#ibcon#about to read 4, iclass 28, count 0 2006.285.21:44:33.35#ibcon#read 4, iclass 28, count 0 2006.285.21:44:33.35#ibcon#about to read 5, iclass 28, count 0 2006.285.21:44:33.35#ibcon#read 5, iclass 28, count 0 2006.285.21:44:33.35#ibcon#about to read 6, iclass 28, count 0 2006.285.21:44:33.35#ibcon#read 6, iclass 28, count 0 2006.285.21:44:33.35#ibcon#end of sib2, iclass 28, count 0 2006.285.21:44:33.35#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:44:33.35#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:44:33.35#ibcon#[25=USB\r\n] 2006.285.21:44:33.35#ibcon#*before write, iclass 28, count 0 2006.285.21:44:33.35#ibcon#enter sib2, iclass 28, count 0 2006.285.21:44:33.35#ibcon#flushed, iclass 28, count 0 2006.285.21:44:33.35#ibcon#about to write, iclass 28, count 0 2006.285.21:44:33.35#ibcon#wrote, iclass 28, count 0 2006.285.21:44:33.35#ibcon#about to read 3, iclass 28, count 0 2006.285.21:44:33.38#ibcon#read 3, iclass 28, count 0 2006.285.21:44:33.38#ibcon#about to read 4, iclass 28, count 0 2006.285.21:44:33.38#ibcon#read 4, iclass 28, count 0 2006.285.21:44:33.38#ibcon#about to read 5, iclass 28, count 0 2006.285.21:44:33.38#ibcon#read 5, iclass 28, count 0 2006.285.21:44:33.38#ibcon#about to read 6, iclass 28, count 0 2006.285.21:44:33.38#ibcon#read 6, iclass 28, count 0 2006.285.21:44:33.38#ibcon#end of sib2, iclass 28, count 0 2006.285.21:44:33.38#ibcon#*after write, iclass 28, count 0 2006.285.21:44:33.38#ibcon#*before return 0, iclass 28, count 0 2006.285.21:44:33.38#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:44:33.38#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:44:33.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:44:33.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:44:33.38$vck44/valo=5,734.99 2006.285.21:44:33.38#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.21:44:33.38#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.21:44:33.38#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:33.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:44:33.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:44:33.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:44:33.38#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:44:33.38#ibcon#first serial, iclass 30, count 0 2006.285.21:44:33.38#ibcon#enter sib2, iclass 30, count 0 2006.285.21:44:33.38#ibcon#flushed, iclass 30, count 0 2006.285.21:44:33.38#ibcon#about to write, iclass 30, count 0 2006.285.21:44:33.38#ibcon#wrote, iclass 30, count 0 2006.285.21:44:33.38#ibcon#about to read 3, iclass 30, count 0 2006.285.21:44:33.40#ibcon#read 3, iclass 30, count 0 2006.285.21:44:33.40#ibcon#about to read 4, iclass 30, count 0 2006.285.21:44:33.40#ibcon#read 4, iclass 30, count 0 2006.285.21:44:33.40#ibcon#about to read 5, iclass 30, count 0 2006.285.21:44:33.40#ibcon#read 5, iclass 30, count 0 2006.285.21:44:33.40#ibcon#about to read 6, iclass 30, count 0 2006.285.21:44:33.40#ibcon#read 6, iclass 30, count 0 2006.285.21:44:33.40#ibcon#end of sib2, iclass 30, count 0 2006.285.21:44:33.40#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:44:33.40#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:44:33.40#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:44:33.40#ibcon#*before write, iclass 30, count 0 2006.285.21:44:33.40#ibcon#enter sib2, iclass 30, count 0 2006.285.21:44:33.40#ibcon#flushed, iclass 30, count 0 2006.285.21:44:33.40#ibcon#about to write, iclass 30, count 0 2006.285.21:44:33.40#ibcon#wrote, iclass 30, count 0 2006.285.21:44:33.40#ibcon#about to read 3, iclass 30, count 0 2006.285.21:44:33.44#ibcon#read 3, iclass 30, count 0 2006.285.21:44:33.44#ibcon#about to read 4, iclass 30, count 0 2006.285.21:44:33.44#ibcon#read 4, iclass 30, count 0 2006.285.21:44:33.44#ibcon#about to read 5, iclass 30, count 0 2006.285.21:44:33.44#ibcon#read 5, iclass 30, count 0 2006.285.21:44:33.44#ibcon#about to read 6, iclass 30, count 0 2006.285.21:44:33.44#ibcon#read 6, iclass 30, count 0 2006.285.21:44:33.44#ibcon#end of sib2, iclass 30, count 0 2006.285.21:44:33.44#ibcon#*after write, iclass 30, count 0 2006.285.21:44:33.44#ibcon#*before return 0, iclass 30, count 0 2006.285.21:44:33.44#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:44:33.44#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:44:33.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:44:33.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:44:33.44$vck44/va=5,3 2006.285.21:44:33.44#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.21:44:33.44#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.21:44:33.44#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:33.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:44:33.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:44:33.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:44:33.50#ibcon#enter wrdev, iclass 32, count 2 2006.285.21:44:33.50#ibcon#first serial, iclass 32, count 2 2006.285.21:44:33.50#ibcon#enter sib2, iclass 32, count 2 2006.285.21:44:33.50#ibcon#flushed, iclass 32, count 2 2006.285.21:44:33.50#ibcon#about to write, iclass 32, count 2 2006.285.21:44:33.50#ibcon#wrote, iclass 32, count 2 2006.285.21:44:33.50#ibcon#about to read 3, iclass 32, count 2 2006.285.21:44:33.52#ibcon#read 3, iclass 32, count 2 2006.285.21:44:33.52#ibcon#about to read 4, iclass 32, count 2 2006.285.21:44:33.52#ibcon#read 4, iclass 32, count 2 2006.285.21:44:33.52#ibcon#about to read 5, iclass 32, count 2 2006.285.21:44:33.52#ibcon#read 5, iclass 32, count 2 2006.285.21:44:33.52#ibcon#about to read 6, iclass 32, count 2 2006.285.21:44:33.52#ibcon#read 6, iclass 32, count 2 2006.285.21:44:33.52#ibcon#end of sib2, iclass 32, count 2 2006.285.21:44:33.52#ibcon#*mode == 0, iclass 32, count 2 2006.285.21:44:33.52#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.21:44:33.52#ibcon#[25=AT05-03\r\n] 2006.285.21:44:33.52#ibcon#*before write, iclass 32, count 2 2006.285.21:44:33.52#ibcon#enter sib2, iclass 32, count 2 2006.285.21:44:33.52#ibcon#flushed, iclass 32, count 2 2006.285.21:44:33.52#ibcon#about to write, iclass 32, count 2 2006.285.21:44:33.52#ibcon#wrote, iclass 32, count 2 2006.285.21:44:33.52#ibcon#about to read 3, iclass 32, count 2 2006.285.21:44:33.55#ibcon#read 3, iclass 32, count 2 2006.285.21:44:33.55#ibcon#about to read 4, iclass 32, count 2 2006.285.21:44:33.55#ibcon#read 4, iclass 32, count 2 2006.285.21:44:33.55#ibcon#about to read 5, iclass 32, count 2 2006.285.21:44:33.55#ibcon#read 5, iclass 32, count 2 2006.285.21:44:33.55#ibcon#about to read 6, iclass 32, count 2 2006.285.21:44:33.55#ibcon#read 6, iclass 32, count 2 2006.285.21:44:33.55#ibcon#end of sib2, iclass 32, count 2 2006.285.21:44:33.55#ibcon#*after write, iclass 32, count 2 2006.285.21:44:33.55#ibcon#*before return 0, iclass 32, count 2 2006.285.21:44:33.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:44:33.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:44:33.55#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.21:44:33.55#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:33.55#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:44:33.67#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:44:33.67#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:44:33.67#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:44:33.67#ibcon#first serial, iclass 32, count 0 2006.285.21:44:33.67#ibcon#enter sib2, iclass 32, count 0 2006.285.21:44:33.67#ibcon#flushed, iclass 32, count 0 2006.285.21:44:33.67#ibcon#about to write, iclass 32, count 0 2006.285.21:44:33.67#ibcon#wrote, iclass 32, count 0 2006.285.21:44:33.67#ibcon#about to read 3, iclass 32, count 0 2006.285.21:44:33.69#ibcon#read 3, iclass 32, count 0 2006.285.21:44:33.69#ibcon#about to read 4, iclass 32, count 0 2006.285.21:44:33.69#ibcon#read 4, iclass 32, count 0 2006.285.21:44:33.69#ibcon#about to read 5, iclass 32, count 0 2006.285.21:44:33.69#ibcon#read 5, iclass 32, count 0 2006.285.21:44:33.69#ibcon#about to read 6, iclass 32, count 0 2006.285.21:44:33.69#ibcon#read 6, iclass 32, count 0 2006.285.21:44:33.69#ibcon#end of sib2, iclass 32, count 0 2006.285.21:44:33.69#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:44:33.69#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:44:33.69#ibcon#[25=USB\r\n] 2006.285.21:44:33.69#ibcon#*before write, iclass 32, count 0 2006.285.21:44:33.69#ibcon#enter sib2, iclass 32, count 0 2006.285.21:44:33.69#ibcon#flushed, iclass 32, count 0 2006.285.21:44:33.69#ibcon#about to write, iclass 32, count 0 2006.285.21:44:33.69#ibcon#wrote, iclass 32, count 0 2006.285.21:44:33.69#ibcon#about to read 3, iclass 32, count 0 2006.285.21:44:33.72#ibcon#read 3, iclass 32, count 0 2006.285.21:44:33.72#ibcon#about to read 4, iclass 32, count 0 2006.285.21:44:33.72#ibcon#read 4, iclass 32, count 0 2006.285.21:44:33.72#ibcon#about to read 5, iclass 32, count 0 2006.285.21:44:33.72#ibcon#read 5, iclass 32, count 0 2006.285.21:44:33.72#ibcon#about to read 6, iclass 32, count 0 2006.285.21:44:33.72#ibcon#read 6, iclass 32, count 0 2006.285.21:44:33.72#ibcon#end of sib2, iclass 32, count 0 2006.285.21:44:33.72#ibcon#*after write, iclass 32, count 0 2006.285.21:44:33.72#ibcon#*before return 0, iclass 32, count 0 2006.285.21:44:33.72#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:44:33.72#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:44:33.72#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:44:33.72#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:44:33.72$vck44/valo=6,814.99 2006.285.21:44:33.72#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.21:44:33.72#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.21:44:33.72#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:33.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:44:33.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:44:33.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:44:33.72#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:44:33.72#ibcon#first serial, iclass 34, count 0 2006.285.21:44:33.72#ibcon#enter sib2, iclass 34, count 0 2006.285.21:44:33.72#ibcon#flushed, iclass 34, count 0 2006.285.21:44:33.72#ibcon#about to write, iclass 34, count 0 2006.285.21:44:33.72#ibcon#wrote, iclass 34, count 0 2006.285.21:44:33.72#ibcon#about to read 3, iclass 34, count 0 2006.285.21:44:33.74#ibcon#read 3, iclass 34, count 0 2006.285.21:44:33.74#ibcon#about to read 4, iclass 34, count 0 2006.285.21:44:33.74#ibcon#read 4, iclass 34, count 0 2006.285.21:44:33.74#ibcon#about to read 5, iclass 34, count 0 2006.285.21:44:33.74#ibcon#read 5, iclass 34, count 0 2006.285.21:44:33.74#ibcon#about to read 6, iclass 34, count 0 2006.285.21:44:33.74#ibcon#read 6, iclass 34, count 0 2006.285.21:44:33.74#ibcon#end of sib2, iclass 34, count 0 2006.285.21:44:33.74#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:44:33.74#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:44:33.74#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:44:33.74#ibcon#*before write, iclass 34, count 0 2006.285.21:44:33.74#ibcon#enter sib2, iclass 34, count 0 2006.285.21:44:33.74#ibcon#flushed, iclass 34, count 0 2006.285.21:44:33.74#ibcon#about to write, iclass 34, count 0 2006.285.21:44:33.74#ibcon#wrote, iclass 34, count 0 2006.285.21:44:33.74#ibcon#about to read 3, iclass 34, count 0 2006.285.21:44:33.78#ibcon#read 3, iclass 34, count 0 2006.285.21:44:33.78#ibcon#about to read 4, iclass 34, count 0 2006.285.21:44:33.78#ibcon#read 4, iclass 34, count 0 2006.285.21:44:33.78#ibcon#about to read 5, iclass 34, count 0 2006.285.21:44:33.78#ibcon#read 5, iclass 34, count 0 2006.285.21:44:33.78#ibcon#about to read 6, iclass 34, count 0 2006.285.21:44:33.78#ibcon#read 6, iclass 34, count 0 2006.285.21:44:33.78#ibcon#end of sib2, iclass 34, count 0 2006.285.21:44:33.78#ibcon#*after write, iclass 34, count 0 2006.285.21:44:33.78#ibcon#*before return 0, iclass 34, count 0 2006.285.21:44:33.78#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:44:33.78#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:44:33.78#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:44:33.78#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:44:33.78$vck44/va=6,4 2006.285.21:44:33.78#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.21:44:33.78#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.21:44:33.78#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:33.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:44:33.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:44:33.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:44:33.84#ibcon#enter wrdev, iclass 36, count 2 2006.285.21:44:33.84#ibcon#first serial, iclass 36, count 2 2006.285.21:44:33.84#ibcon#enter sib2, iclass 36, count 2 2006.285.21:44:33.84#ibcon#flushed, iclass 36, count 2 2006.285.21:44:33.84#ibcon#about to write, iclass 36, count 2 2006.285.21:44:33.84#ibcon#wrote, iclass 36, count 2 2006.285.21:44:33.84#ibcon#about to read 3, iclass 36, count 2 2006.285.21:44:33.86#ibcon#read 3, iclass 36, count 2 2006.285.21:44:33.86#ibcon#about to read 4, iclass 36, count 2 2006.285.21:44:33.86#ibcon#read 4, iclass 36, count 2 2006.285.21:44:33.86#ibcon#about to read 5, iclass 36, count 2 2006.285.21:44:33.86#ibcon#read 5, iclass 36, count 2 2006.285.21:44:33.86#ibcon#about to read 6, iclass 36, count 2 2006.285.21:44:33.86#ibcon#read 6, iclass 36, count 2 2006.285.21:44:33.86#ibcon#end of sib2, iclass 36, count 2 2006.285.21:44:33.86#ibcon#*mode == 0, iclass 36, count 2 2006.285.21:44:33.86#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.21:44:33.86#ibcon#[25=AT06-04\r\n] 2006.285.21:44:33.86#ibcon#*before write, iclass 36, count 2 2006.285.21:44:33.86#ibcon#enter sib2, iclass 36, count 2 2006.285.21:44:33.86#ibcon#flushed, iclass 36, count 2 2006.285.21:44:33.86#ibcon#about to write, iclass 36, count 2 2006.285.21:44:33.86#ibcon#wrote, iclass 36, count 2 2006.285.21:44:33.86#ibcon#about to read 3, iclass 36, count 2 2006.285.21:44:33.89#ibcon#read 3, iclass 36, count 2 2006.285.21:44:33.89#ibcon#about to read 4, iclass 36, count 2 2006.285.21:44:33.89#ibcon#read 4, iclass 36, count 2 2006.285.21:44:33.89#ibcon#about to read 5, iclass 36, count 2 2006.285.21:44:33.89#ibcon#read 5, iclass 36, count 2 2006.285.21:44:33.89#ibcon#about to read 6, iclass 36, count 2 2006.285.21:44:33.89#ibcon#read 6, iclass 36, count 2 2006.285.21:44:33.89#ibcon#end of sib2, iclass 36, count 2 2006.285.21:44:33.89#ibcon#*after write, iclass 36, count 2 2006.285.21:44:33.89#ibcon#*before return 0, iclass 36, count 2 2006.285.21:44:33.89#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:44:33.89#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:44:33.89#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.21:44:33.89#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:33.89#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:44:34.01#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:44:34.01#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:44:34.01#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:44:34.01#ibcon#first serial, iclass 36, count 0 2006.285.21:44:34.01#ibcon#enter sib2, iclass 36, count 0 2006.285.21:44:34.01#ibcon#flushed, iclass 36, count 0 2006.285.21:44:34.01#ibcon#about to write, iclass 36, count 0 2006.285.21:44:34.01#ibcon#wrote, iclass 36, count 0 2006.285.21:44:34.01#ibcon#about to read 3, iclass 36, count 0 2006.285.21:44:34.03#ibcon#read 3, iclass 36, count 0 2006.285.21:44:34.03#ibcon#about to read 4, iclass 36, count 0 2006.285.21:44:34.03#ibcon#read 4, iclass 36, count 0 2006.285.21:44:34.03#ibcon#about to read 5, iclass 36, count 0 2006.285.21:44:34.03#ibcon#read 5, iclass 36, count 0 2006.285.21:44:34.03#ibcon#about to read 6, iclass 36, count 0 2006.285.21:44:34.03#ibcon#read 6, iclass 36, count 0 2006.285.21:44:34.03#ibcon#end of sib2, iclass 36, count 0 2006.285.21:44:34.03#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:44:34.03#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:44:34.03#ibcon#[25=USB\r\n] 2006.285.21:44:34.03#ibcon#*before write, iclass 36, count 0 2006.285.21:44:34.03#ibcon#enter sib2, iclass 36, count 0 2006.285.21:44:34.03#ibcon#flushed, iclass 36, count 0 2006.285.21:44:34.03#ibcon#about to write, iclass 36, count 0 2006.285.21:44:34.03#ibcon#wrote, iclass 36, count 0 2006.285.21:44:34.03#ibcon#about to read 3, iclass 36, count 0 2006.285.21:44:34.06#ibcon#read 3, iclass 36, count 0 2006.285.21:44:34.06#ibcon#about to read 4, iclass 36, count 0 2006.285.21:44:34.06#ibcon#read 4, iclass 36, count 0 2006.285.21:44:34.06#ibcon#about to read 5, iclass 36, count 0 2006.285.21:44:34.06#ibcon#read 5, iclass 36, count 0 2006.285.21:44:34.06#ibcon#about to read 6, iclass 36, count 0 2006.285.21:44:34.06#ibcon#read 6, iclass 36, count 0 2006.285.21:44:34.06#ibcon#end of sib2, iclass 36, count 0 2006.285.21:44:34.06#ibcon#*after write, iclass 36, count 0 2006.285.21:44:34.06#ibcon#*before return 0, iclass 36, count 0 2006.285.21:44:34.06#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:44:34.06#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:44:34.06#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:44:34.06#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:44:34.06$vck44/valo=7,864.99 2006.285.21:44:34.06#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.21:44:34.06#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.21:44:34.06#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:34.06#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:44:34.06#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:44:34.06#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:44:34.06#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:44:34.06#ibcon#first serial, iclass 38, count 0 2006.285.21:44:34.06#ibcon#enter sib2, iclass 38, count 0 2006.285.21:44:34.06#ibcon#flushed, iclass 38, count 0 2006.285.21:44:34.06#ibcon#about to write, iclass 38, count 0 2006.285.21:44:34.06#ibcon#wrote, iclass 38, count 0 2006.285.21:44:34.06#ibcon#about to read 3, iclass 38, count 0 2006.285.21:44:34.08#ibcon#read 3, iclass 38, count 0 2006.285.21:44:34.08#ibcon#about to read 4, iclass 38, count 0 2006.285.21:44:34.08#ibcon#read 4, iclass 38, count 0 2006.285.21:44:34.08#ibcon#about to read 5, iclass 38, count 0 2006.285.21:44:34.08#ibcon#read 5, iclass 38, count 0 2006.285.21:44:34.08#ibcon#about to read 6, iclass 38, count 0 2006.285.21:44:34.08#ibcon#read 6, iclass 38, count 0 2006.285.21:44:34.08#ibcon#end of sib2, iclass 38, count 0 2006.285.21:44:34.08#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:44:34.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:44:34.08#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:44:34.08#ibcon#*before write, iclass 38, count 0 2006.285.21:44:34.08#ibcon#enter sib2, iclass 38, count 0 2006.285.21:44:34.08#ibcon#flushed, iclass 38, count 0 2006.285.21:44:34.08#ibcon#about to write, iclass 38, count 0 2006.285.21:44:34.08#ibcon#wrote, iclass 38, count 0 2006.285.21:44:34.08#ibcon#about to read 3, iclass 38, count 0 2006.285.21:44:34.12#ibcon#read 3, iclass 38, count 0 2006.285.21:44:34.12#ibcon#about to read 4, iclass 38, count 0 2006.285.21:44:34.12#ibcon#read 4, iclass 38, count 0 2006.285.21:44:34.12#ibcon#about to read 5, iclass 38, count 0 2006.285.21:44:34.12#ibcon#read 5, iclass 38, count 0 2006.285.21:44:34.12#ibcon#about to read 6, iclass 38, count 0 2006.285.21:44:34.12#ibcon#read 6, iclass 38, count 0 2006.285.21:44:34.12#ibcon#end of sib2, iclass 38, count 0 2006.285.21:44:34.12#ibcon#*after write, iclass 38, count 0 2006.285.21:44:34.12#ibcon#*before return 0, iclass 38, count 0 2006.285.21:44:34.12#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:44:34.12#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:44:34.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:44:34.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:44:34.12$vck44/va=7,4 2006.285.21:44:34.12#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.21:44:34.12#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.21:44:34.12#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:34.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:44:34.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:44:34.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:44:34.18#ibcon#enter wrdev, iclass 40, count 2 2006.285.21:44:34.18#ibcon#first serial, iclass 40, count 2 2006.285.21:44:34.18#ibcon#enter sib2, iclass 40, count 2 2006.285.21:44:34.18#ibcon#flushed, iclass 40, count 2 2006.285.21:44:34.18#ibcon#about to write, iclass 40, count 2 2006.285.21:44:34.18#ibcon#wrote, iclass 40, count 2 2006.285.21:44:34.18#ibcon#about to read 3, iclass 40, count 2 2006.285.21:44:34.20#ibcon#read 3, iclass 40, count 2 2006.285.21:44:34.20#ibcon#about to read 4, iclass 40, count 2 2006.285.21:44:34.20#ibcon#read 4, iclass 40, count 2 2006.285.21:44:34.20#ibcon#about to read 5, iclass 40, count 2 2006.285.21:44:34.20#ibcon#read 5, iclass 40, count 2 2006.285.21:44:34.20#ibcon#about to read 6, iclass 40, count 2 2006.285.21:44:34.20#ibcon#read 6, iclass 40, count 2 2006.285.21:44:34.20#ibcon#end of sib2, iclass 40, count 2 2006.285.21:44:34.20#ibcon#*mode == 0, iclass 40, count 2 2006.285.21:44:34.20#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.21:44:34.20#ibcon#[25=AT07-04\r\n] 2006.285.21:44:34.20#ibcon#*before write, iclass 40, count 2 2006.285.21:44:34.20#ibcon#enter sib2, iclass 40, count 2 2006.285.21:44:34.20#ibcon#flushed, iclass 40, count 2 2006.285.21:44:34.20#ibcon#about to write, iclass 40, count 2 2006.285.21:44:34.20#ibcon#wrote, iclass 40, count 2 2006.285.21:44:34.20#ibcon#about to read 3, iclass 40, count 2 2006.285.21:44:34.23#ibcon#read 3, iclass 40, count 2 2006.285.21:44:34.23#ibcon#about to read 4, iclass 40, count 2 2006.285.21:44:34.23#ibcon#read 4, iclass 40, count 2 2006.285.21:44:34.23#ibcon#about to read 5, iclass 40, count 2 2006.285.21:44:34.23#ibcon#read 5, iclass 40, count 2 2006.285.21:44:34.23#ibcon#about to read 6, iclass 40, count 2 2006.285.21:44:34.23#ibcon#read 6, iclass 40, count 2 2006.285.21:44:34.23#ibcon#end of sib2, iclass 40, count 2 2006.285.21:44:34.23#ibcon#*after write, iclass 40, count 2 2006.285.21:44:34.23#ibcon#*before return 0, iclass 40, count 2 2006.285.21:44:34.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:44:34.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:44:34.23#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.21:44:34.23#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:34.23#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:44:34.35#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:44:34.35#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:44:34.35#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:44:34.35#ibcon#first serial, iclass 40, count 0 2006.285.21:44:34.35#ibcon#enter sib2, iclass 40, count 0 2006.285.21:44:34.35#ibcon#flushed, iclass 40, count 0 2006.285.21:44:34.35#ibcon#about to write, iclass 40, count 0 2006.285.21:44:34.35#ibcon#wrote, iclass 40, count 0 2006.285.21:44:34.35#ibcon#about to read 3, iclass 40, count 0 2006.285.21:44:34.37#ibcon#read 3, iclass 40, count 0 2006.285.21:44:34.37#ibcon#about to read 4, iclass 40, count 0 2006.285.21:44:34.37#ibcon#read 4, iclass 40, count 0 2006.285.21:44:34.37#ibcon#about to read 5, iclass 40, count 0 2006.285.21:44:34.37#ibcon#read 5, iclass 40, count 0 2006.285.21:44:34.37#ibcon#about to read 6, iclass 40, count 0 2006.285.21:44:34.37#ibcon#read 6, iclass 40, count 0 2006.285.21:44:34.37#ibcon#end of sib2, iclass 40, count 0 2006.285.21:44:34.37#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:44:34.37#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:44:34.37#ibcon#[25=USB\r\n] 2006.285.21:44:34.37#ibcon#*before write, iclass 40, count 0 2006.285.21:44:34.37#ibcon#enter sib2, iclass 40, count 0 2006.285.21:44:34.37#ibcon#flushed, iclass 40, count 0 2006.285.21:44:34.37#ibcon#about to write, iclass 40, count 0 2006.285.21:44:34.37#ibcon#wrote, iclass 40, count 0 2006.285.21:44:34.37#ibcon#about to read 3, iclass 40, count 0 2006.285.21:44:34.40#ibcon#read 3, iclass 40, count 0 2006.285.21:44:34.40#ibcon#about to read 4, iclass 40, count 0 2006.285.21:44:34.40#ibcon#read 4, iclass 40, count 0 2006.285.21:44:34.40#ibcon#about to read 5, iclass 40, count 0 2006.285.21:44:34.40#ibcon#read 5, iclass 40, count 0 2006.285.21:44:34.40#ibcon#about to read 6, iclass 40, count 0 2006.285.21:44:34.40#ibcon#read 6, iclass 40, count 0 2006.285.21:44:34.40#ibcon#end of sib2, iclass 40, count 0 2006.285.21:44:34.40#ibcon#*after write, iclass 40, count 0 2006.285.21:44:34.40#ibcon#*before return 0, iclass 40, count 0 2006.285.21:44:34.40#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:44:34.40#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:44:34.40#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:44:34.40#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:44:34.40$vck44/valo=8,884.99 2006.285.21:44:34.40#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.21:44:34.40#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.21:44:34.40#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:34.40#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:44:34.40#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:44:34.40#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:44:34.40#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:44:34.40#ibcon#first serial, iclass 4, count 0 2006.285.21:44:34.40#ibcon#enter sib2, iclass 4, count 0 2006.285.21:44:34.40#ibcon#flushed, iclass 4, count 0 2006.285.21:44:34.40#ibcon#about to write, iclass 4, count 0 2006.285.21:44:34.40#ibcon#wrote, iclass 4, count 0 2006.285.21:44:34.40#ibcon#about to read 3, iclass 4, count 0 2006.285.21:44:34.42#ibcon#read 3, iclass 4, count 0 2006.285.21:44:34.56#ibcon#about to read 4, iclass 4, count 0 2006.285.21:44:34.56#ibcon#read 4, iclass 4, count 0 2006.285.21:44:34.56#ibcon#about to read 5, iclass 4, count 0 2006.285.21:44:34.56#ibcon#read 5, iclass 4, count 0 2006.285.21:44:34.56#ibcon#about to read 6, iclass 4, count 0 2006.285.21:44:34.56#ibcon#read 6, iclass 4, count 0 2006.285.21:44:34.56#ibcon#end of sib2, iclass 4, count 0 2006.285.21:44:34.56#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:44:34.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:44:34.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:44:34.56#ibcon#*before write, iclass 4, count 0 2006.285.21:44:34.56#ibcon#enter sib2, iclass 4, count 0 2006.285.21:44:34.56#ibcon#flushed, iclass 4, count 0 2006.285.21:44:34.56#ibcon#about to write, iclass 4, count 0 2006.285.21:44:34.56#ibcon#wrote, iclass 4, count 0 2006.285.21:44:34.56#ibcon#about to read 3, iclass 4, count 0 2006.285.21:44:34.61#ibcon#read 3, iclass 4, count 0 2006.285.21:44:34.61#ibcon#about to read 4, iclass 4, count 0 2006.285.21:44:34.61#ibcon#read 4, iclass 4, count 0 2006.285.21:44:34.61#ibcon#about to read 5, iclass 4, count 0 2006.285.21:44:34.61#ibcon#read 5, iclass 4, count 0 2006.285.21:44:34.61#ibcon#about to read 6, iclass 4, count 0 2006.285.21:44:34.61#ibcon#read 6, iclass 4, count 0 2006.285.21:44:34.61#ibcon#end of sib2, iclass 4, count 0 2006.285.21:44:34.61#ibcon#*after write, iclass 4, count 0 2006.285.21:44:34.61#ibcon#*before return 0, iclass 4, count 0 2006.285.21:44:34.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:44:34.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:44:34.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:44:34.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:44:34.61$vck44/va=8,3 2006.285.21:44:34.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.21:44:34.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.21:44:34.61#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:34.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:44:34.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:44:34.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:44:34.61#ibcon#enter wrdev, iclass 6, count 2 2006.285.21:44:34.61#ibcon#first serial, iclass 6, count 2 2006.285.21:44:34.61#ibcon#enter sib2, iclass 6, count 2 2006.285.21:44:34.61#ibcon#flushed, iclass 6, count 2 2006.285.21:44:34.61#ibcon#about to write, iclass 6, count 2 2006.285.21:44:34.61#ibcon#wrote, iclass 6, count 2 2006.285.21:44:34.61#ibcon#about to read 3, iclass 6, count 2 2006.285.21:44:34.63#ibcon#read 3, iclass 6, count 2 2006.285.21:44:34.63#ibcon#about to read 4, iclass 6, count 2 2006.285.21:44:34.63#ibcon#read 4, iclass 6, count 2 2006.285.21:44:34.63#ibcon#about to read 5, iclass 6, count 2 2006.285.21:44:34.63#ibcon#read 5, iclass 6, count 2 2006.285.21:44:34.63#ibcon#about to read 6, iclass 6, count 2 2006.285.21:44:34.63#ibcon#read 6, iclass 6, count 2 2006.285.21:44:34.63#ibcon#end of sib2, iclass 6, count 2 2006.285.21:44:34.63#ibcon#*mode == 0, iclass 6, count 2 2006.285.21:44:34.63#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.21:44:34.63#ibcon#[25=AT08-03\r\n] 2006.285.21:44:34.63#ibcon#*before write, iclass 6, count 2 2006.285.21:44:34.63#ibcon#enter sib2, iclass 6, count 2 2006.285.21:44:34.63#ibcon#flushed, iclass 6, count 2 2006.285.21:44:34.63#ibcon#about to write, iclass 6, count 2 2006.285.21:44:34.63#ibcon#wrote, iclass 6, count 2 2006.285.21:44:34.63#ibcon#about to read 3, iclass 6, count 2 2006.285.21:44:34.66#ibcon#read 3, iclass 6, count 2 2006.285.21:44:34.66#ibcon#about to read 4, iclass 6, count 2 2006.285.21:44:34.66#ibcon#read 4, iclass 6, count 2 2006.285.21:44:34.66#ibcon#about to read 5, iclass 6, count 2 2006.285.21:44:34.66#ibcon#read 5, iclass 6, count 2 2006.285.21:44:34.66#ibcon#about to read 6, iclass 6, count 2 2006.285.21:44:34.66#ibcon#read 6, iclass 6, count 2 2006.285.21:44:34.66#ibcon#end of sib2, iclass 6, count 2 2006.285.21:44:34.66#ibcon#*after write, iclass 6, count 2 2006.285.21:44:34.66#ibcon#*before return 0, iclass 6, count 2 2006.285.21:44:34.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:44:34.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.21:44:34.66#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.21:44:34.66#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:34.66#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:44:34.78#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:44:34.78#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:44:34.78#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:44:34.78#ibcon#first serial, iclass 6, count 0 2006.285.21:44:34.78#ibcon#enter sib2, iclass 6, count 0 2006.285.21:44:34.78#ibcon#flushed, iclass 6, count 0 2006.285.21:44:34.78#ibcon#about to write, iclass 6, count 0 2006.285.21:44:34.78#ibcon#wrote, iclass 6, count 0 2006.285.21:44:34.78#ibcon#about to read 3, iclass 6, count 0 2006.285.21:44:34.80#ibcon#read 3, iclass 6, count 0 2006.285.21:44:34.80#ibcon#about to read 4, iclass 6, count 0 2006.285.21:44:34.80#ibcon#read 4, iclass 6, count 0 2006.285.21:44:34.80#ibcon#about to read 5, iclass 6, count 0 2006.285.21:44:34.80#ibcon#read 5, iclass 6, count 0 2006.285.21:44:34.80#ibcon#about to read 6, iclass 6, count 0 2006.285.21:44:34.80#ibcon#read 6, iclass 6, count 0 2006.285.21:44:34.80#ibcon#end of sib2, iclass 6, count 0 2006.285.21:44:34.80#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:44:34.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:44:34.80#ibcon#[25=USB\r\n] 2006.285.21:44:34.80#ibcon#*before write, iclass 6, count 0 2006.285.21:44:34.80#ibcon#enter sib2, iclass 6, count 0 2006.285.21:44:34.80#ibcon#flushed, iclass 6, count 0 2006.285.21:44:34.80#ibcon#about to write, iclass 6, count 0 2006.285.21:44:34.80#ibcon#wrote, iclass 6, count 0 2006.285.21:44:34.80#ibcon#about to read 3, iclass 6, count 0 2006.285.21:44:34.83#ibcon#read 3, iclass 6, count 0 2006.285.21:44:34.83#ibcon#about to read 4, iclass 6, count 0 2006.285.21:44:34.83#ibcon#read 4, iclass 6, count 0 2006.285.21:44:34.83#ibcon#about to read 5, iclass 6, count 0 2006.285.21:44:34.83#ibcon#read 5, iclass 6, count 0 2006.285.21:44:34.83#ibcon#about to read 6, iclass 6, count 0 2006.285.21:44:34.83#ibcon#read 6, iclass 6, count 0 2006.285.21:44:34.83#ibcon#end of sib2, iclass 6, count 0 2006.285.21:44:34.83#ibcon#*after write, iclass 6, count 0 2006.285.21:44:34.83#ibcon#*before return 0, iclass 6, count 0 2006.285.21:44:34.83#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:44:34.83#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.21:44:34.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:44:34.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:44:34.83$vck44/vblo=1,629.99 2006.285.21:44:34.83#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.21:44:34.83#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.21:44:34.83#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:34.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:44:34.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:44:34.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:44:34.83#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:44:34.83#ibcon#first serial, iclass 10, count 0 2006.285.21:44:34.83#ibcon#enter sib2, iclass 10, count 0 2006.285.21:44:34.83#ibcon#flushed, iclass 10, count 0 2006.285.21:44:34.83#ibcon#about to write, iclass 10, count 0 2006.285.21:44:34.83#ibcon#wrote, iclass 10, count 0 2006.285.21:44:34.83#ibcon#about to read 3, iclass 10, count 0 2006.285.21:44:34.85#ibcon#read 3, iclass 10, count 0 2006.285.21:44:34.85#ibcon#about to read 4, iclass 10, count 0 2006.285.21:44:34.85#ibcon#read 4, iclass 10, count 0 2006.285.21:44:34.85#ibcon#about to read 5, iclass 10, count 0 2006.285.21:44:34.85#ibcon#read 5, iclass 10, count 0 2006.285.21:44:34.85#ibcon#about to read 6, iclass 10, count 0 2006.285.21:44:34.85#ibcon#read 6, iclass 10, count 0 2006.285.21:44:34.85#ibcon#end of sib2, iclass 10, count 0 2006.285.21:44:34.85#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:44:34.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:44:34.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:44:34.85#ibcon#*before write, iclass 10, count 0 2006.285.21:44:34.85#ibcon#enter sib2, iclass 10, count 0 2006.285.21:44:34.85#ibcon#flushed, iclass 10, count 0 2006.285.21:44:34.85#ibcon#about to write, iclass 10, count 0 2006.285.21:44:34.85#ibcon#wrote, iclass 10, count 0 2006.285.21:44:34.85#ibcon#about to read 3, iclass 10, count 0 2006.285.21:44:34.89#ibcon#read 3, iclass 10, count 0 2006.285.21:44:34.89#ibcon#about to read 4, iclass 10, count 0 2006.285.21:44:34.89#ibcon#read 4, iclass 10, count 0 2006.285.21:44:34.89#ibcon#about to read 5, iclass 10, count 0 2006.285.21:44:34.89#ibcon#read 5, iclass 10, count 0 2006.285.21:44:34.89#ibcon#about to read 6, iclass 10, count 0 2006.285.21:44:34.89#ibcon#read 6, iclass 10, count 0 2006.285.21:44:34.89#ibcon#end of sib2, iclass 10, count 0 2006.285.21:44:34.89#ibcon#*after write, iclass 10, count 0 2006.285.21:44:34.89#ibcon#*before return 0, iclass 10, count 0 2006.285.21:44:34.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:44:34.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.21:44:34.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:44:34.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:44:34.89$vck44/vb=1,4 2006.285.21:44:34.89#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.21:44:34.89#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.21:44:34.89#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:34.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:44:34.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:44:34.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:44:34.89#ibcon#enter wrdev, iclass 12, count 2 2006.285.21:44:34.89#ibcon#first serial, iclass 12, count 2 2006.285.21:44:34.89#ibcon#enter sib2, iclass 12, count 2 2006.285.21:44:34.89#ibcon#flushed, iclass 12, count 2 2006.285.21:44:34.89#ibcon#about to write, iclass 12, count 2 2006.285.21:44:34.89#ibcon#wrote, iclass 12, count 2 2006.285.21:44:34.89#ibcon#about to read 3, iclass 12, count 2 2006.285.21:44:34.91#ibcon#read 3, iclass 12, count 2 2006.285.21:44:34.91#ibcon#about to read 4, iclass 12, count 2 2006.285.21:44:34.91#ibcon#read 4, iclass 12, count 2 2006.285.21:44:34.91#ibcon#about to read 5, iclass 12, count 2 2006.285.21:44:34.91#ibcon#read 5, iclass 12, count 2 2006.285.21:44:34.91#ibcon#about to read 6, iclass 12, count 2 2006.285.21:44:34.91#ibcon#read 6, iclass 12, count 2 2006.285.21:44:34.91#ibcon#end of sib2, iclass 12, count 2 2006.285.21:44:34.91#ibcon#*mode == 0, iclass 12, count 2 2006.285.21:44:34.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.21:44:34.91#ibcon#[27=AT01-04\r\n] 2006.285.21:44:34.91#ibcon#*before write, iclass 12, count 2 2006.285.21:44:34.91#ibcon#enter sib2, iclass 12, count 2 2006.285.21:44:34.91#ibcon#flushed, iclass 12, count 2 2006.285.21:44:34.91#ibcon#about to write, iclass 12, count 2 2006.285.21:44:34.91#ibcon#wrote, iclass 12, count 2 2006.285.21:44:34.91#ibcon#about to read 3, iclass 12, count 2 2006.285.21:44:34.94#ibcon#read 3, iclass 12, count 2 2006.285.21:44:34.94#ibcon#about to read 4, iclass 12, count 2 2006.285.21:44:34.94#ibcon#read 4, iclass 12, count 2 2006.285.21:44:34.94#ibcon#about to read 5, iclass 12, count 2 2006.285.21:44:34.94#ibcon#read 5, iclass 12, count 2 2006.285.21:44:34.94#ibcon#about to read 6, iclass 12, count 2 2006.285.21:44:34.94#ibcon#read 6, iclass 12, count 2 2006.285.21:44:34.94#ibcon#end of sib2, iclass 12, count 2 2006.285.21:44:34.94#ibcon#*after write, iclass 12, count 2 2006.285.21:44:34.94#ibcon#*before return 0, iclass 12, count 2 2006.285.21:44:34.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:44:34.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.21:44:34.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.21:44:34.94#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:34.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:44:35.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:44:35.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:44:35.06#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:44:35.06#ibcon#first serial, iclass 12, count 0 2006.285.21:44:35.06#ibcon#enter sib2, iclass 12, count 0 2006.285.21:44:35.06#ibcon#flushed, iclass 12, count 0 2006.285.21:44:35.06#ibcon#about to write, iclass 12, count 0 2006.285.21:44:35.06#ibcon#wrote, iclass 12, count 0 2006.285.21:44:35.06#ibcon#about to read 3, iclass 12, count 0 2006.285.21:44:35.08#ibcon#read 3, iclass 12, count 0 2006.285.21:44:35.08#ibcon#about to read 4, iclass 12, count 0 2006.285.21:44:35.08#ibcon#read 4, iclass 12, count 0 2006.285.21:44:35.08#ibcon#about to read 5, iclass 12, count 0 2006.285.21:44:35.08#ibcon#read 5, iclass 12, count 0 2006.285.21:44:35.08#ibcon#about to read 6, iclass 12, count 0 2006.285.21:44:35.08#ibcon#read 6, iclass 12, count 0 2006.285.21:44:35.08#ibcon#end of sib2, iclass 12, count 0 2006.285.21:44:35.08#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:44:35.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:44:35.08#ibcon#[27=USB\r\n] 2006.285.21:44:35.08#ibcon#*before write, iclass 12, count 0 2006.285.21:44:35.08#ibcon#enter sib2, iclass 12, count 0 2006.285.21:44:35.08#ibcon#flushed, iclass 12, count 0 2006.285.21:44:35.08#ibcon#about to write, iclass 12, count 0 2006.285.21:44:35.08#ibcon#wrote, iclass 12, count 0 2006.285.21:44:35.08#ibcon#about to read 3, iclass 12, count 0 2006.285.21:44:35.11#ibcon#read 3, iclass 12, count 0 2006.285.21:44:35.11#ibcon#about to read 4, iclass 12, count 0 2006.285.21:44:35.11#ibcon#read 4, iclass 12, count 0 2006.285.21:44:35.11#ibcon#about to read 5, iclass 12, count 0 2006.285.21:44:35.11#ibcon#read 5, iclass 12, count 0 2006.285.21:44:35.11#ibcon#about to read 6, iclass 12, count 0 2006.285.21:44:35.11#ibcon#read 6, iclass 12, count 0 2006.285.21:44:35.11#ibcon#end of sib2, iclass 12, count 0 2006.285.21:44:35.11#ibcon#*after write, iclass 12, count 0 2006.285.21:44:35.11#ibcon#*before return 0, iclass 12, count 0 2006.285.21:44:35.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:44:35.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.21:44:35.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:44:35.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:44:35.11$vck44/vblo=2,634.99 2006.285.21:44:35.11#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.21:44:35.11#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.21:44:35.11#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:35.11#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:44:35.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:44:35.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:44:35.11#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:44:35.11#ibcon#first serial, iclass 14, count 0 2006.285.21:44:35.11#ibcon#enter sib2, iclass 14, count 0 2006.285.21:44:35.11#ibcon#flushed, iclass 14, count 0 2006.285.21:44:35.11#ibcon#about to write, iclass 14, count 0 2006.285.21:44:35.11#ibcon#wrote, iclass 14, count 0 2006.285.21:44:35.11#ibcon#about to read 3, iclass 14, count 0 2006.285.21:44:35.13#ibcon#read 3, iclass 14, count 0 2006.285.21:44:35.13#ibcon#about to read 4, iclass 14, count 0 2006.285.21:44:35.13#ibcon#read 4, iclass 14, count 0 2006.285.21:44:35.13#ibcon#about to read 5, iclass 14, count 0 2006.285.21:44:35.13#ibcon#read 5, iclass 14, count 0 2006.285.21:44:35.13#ibcon#about to read 6, iclass 14, count 0 2006.285.21:44:35.13#ibcon#read 6, iclass 14, count 0 2006.285.21:44:35.13#ibcon#end of sib2, iclass 14, count 0 2006.285.21:44:35.13#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:44:35.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:44:35.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:44:35.13#ibcon#*before write, iclass 14, count 0 2006.285.21:44:35.13#ibcon#enter sib2, iclass 14, count 0 2006.285.21:44:35.13#ibcon#flushed, iclass 14, count 0 2006.285.21:44:35.13#ibcon#about to write, iclass 14, count 0 2006.285.21:44:35.13#ibcon#wrote, iclass 14, count 0 2006.285.21:44:35.13#ibcon#about to read 3, iclass 14, count 0 2006.285.21:44:35.17#ibcon#read 3, iclass 14, count 0 2006.285.21:44:35.17#ibcon#about to read 4, iclass 14, count 0 2006.285.21:44:35.17#ibcon#read 4, iclass 14, count 0 2006.285.21:44:35.17#ibcon#about to read 5, iclass 14, count 0 2006.285.21:44:35.17#ibcon#read 5, iclass 14, count 0 2006.285.21:44:35.17#ibcon#about to read 6, iclass 14, count 0 2006.285.21:44:35.17#ibcon#read 6, iclass 14, count 0 2006.285.21:44:35.17#ibcon#end of sib2, iclass 14, count 0 2006.285.21:44:35.17#ibcon#*after write, iclass 14, count 0 2006.285.21:44:35.17#ibcon#*before return 0, iclass 14, count 0 2006.285.21:44:35.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:44:35.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:44:35.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:44:35.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:44:35.17$vck44/vb=2,5 2006.285.21:44:35.17#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.21:44:35.17#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.21:44:35.17#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:35.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:44:35.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:44:35.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:44:35.23#ibcon#enter wrdev, iclass 16, count 2 2006.285.21:44:35.23#ibcon#first serial, iclass 16, count 2 2006.285.21:44:35.23#ibcon#enter sib2, iclass 16, count 2 2006.285.21:44:35.23#ibcon#flushed, iclass 16, count 2 2006.285.21:44:35.23#ibcon#about to write, iclass 16, count 2 2006.285.21:44:35.23#ibcon#wrote, iclass 16, count 2 2006.285.21:44:35.23#ibcon#about to read 3, iclass 16, count 2 2006.285.21:44:35.25#ibcon#read 3, iclass 16, count 2 2006.285.21:44:35.25#ibcon#about to read 4, iclass 16, count 2 2006.285.21:44:35.25#ibcon#read 4, iclass 16, count 2 2006.285.21:44:35.25#ibcon#about to read 5, iclass 16, count 2 2006.285.21:44:35.25#ibcon#read 5, iclass 16, count 2 2006.285.21:44:35.25#ibcon#about to read 6, iclass 16, count 2 2006.285.21:44:35.25#ibcon#read 6, iclass 16, count 2 2006.285.21:44:35.25#ibcon#end of sib2, iclass 16, count 2 2006.285.21:44:35.25#ibcon#*mode == 0, iclass 16, count 2 2006.285.21:44:35.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.21:44:35.25#ibcon#[27=AT02-05\r\n] 2006.285.21:44:35.25#ibcon#*before write, iclass 16, count 2 2006.285.21:44:35.25#ibcon#enter sib2, iclass 16, count 2 2006.285.21:44:35.25#ibcon#flushed, iclass 16, count 2 2006.285.21:44:35.25#ibcon#about to write, iclass 16, count 2 2006.285.21:44:35.25#ibcon#wrote, iclass 16, count 2 2006.285.21:44:35.25#ibcon#about to read 3, iclass 16, count 2 2006.285.21:44:35.28#ibcon#read 3, iclass 16, count 2 2006.285.21:44:35.28#ibcon#about to read 4, iclass 16, count 2 2006.285.21:44:35.28#ibcon#read 4, iclass 16, count 2 2006.285.21:44:35.28#ibcon#about to read 5, iclass 16, count 2 2006.285.21:44:35.28#ibcon#read 5, iclass 16, count 2 2006.285.21:44:35.28#ibcon#about to read 6, iclass 16, count 2 2006.285.21:44:35.28#ibcon#read 6, iclass 16, count 2 2006.285.21:44:35.28#ibcon#end of sib2, iclass 16, count 2 2006.285.21:44:35.28#ibcon#*after write, iclass 16, count 2 2006.285.21:44:35.28#ibcon#*before return 0, iclass 16, count 2 2006.285.21:44:35.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:44:35.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.21:44:35.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.21:44:35.28#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:35.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:44:35.40#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:44:35.40#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:44:35.40#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:44:35.40#ibcon#first serial, iclass 16, count 0 2006.285.21:44:35.40#ibcon#enter sib2, iclass 16, count 0 2006.285.21:44:35.40#ibcon#flushed, iclass 16, count 0 2006.285.21:44:35.40#ibcon#about to write, iclass 16, count 0 2006.285.21:44:35.40#ibcon#wrote, iclass 16, count 0 2006.285.21:44:35.40#ibcon#about to read 3, iclass 16, count 0 2006.285.21:44:35.42#ibcon#read 3, iclass 16, count 0 2006.285.21:44:35.42#ibcon#about to read 4, iclass 16, count 0 2006.285.21:44:35.42#ibcon#read 4, iclass 16, count 0 2006.285.21:44:35.42#ibcon#about to read 5, iclass 16, count 0 2006.285.21:44:35.42#ibcon#read 5, iclass 16, count 0 2006.285.21:44:35.42#ibcon#about to read 6, iclass 16, count 0 2006.285.21:44:35.42#ibcon#read 6, iclass 16, count 0 2006.285.21:44:35.42#ibcon#end of sib2, iclass 16, count 0 2006.285.21:44:35.42#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:44:35.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:44:35.42#ibcon#[27=USB\r\n] 2006.285.21:44:35.42#ibcon#*before write, iclass 16, count 0 2006.285.21:44:35.42#ibcon#enter sib2, iclass 16, count 0 2006.285.21:44:35.42#ibcon#flushed, iclass 16, count 0 2006.285.21:44:35.42#ibcon#about to write, iclass 16, count 0 2006.285.21:44:35.42#ibcon#wrote, iclass 16, count 0 2006.285.21:44:35.42#ibcon#about to read 3, iclass 16, count 0 2006.285.21:44:35.45#ibcon#read 3, iclass 16, count 0 2006.285.21:44:35.45#ibcon#about to read 4, iclass 16, count 0 2006.285.21:44:35.45#ibcon#read 4, iclass 16, count 0 2006.285.21:44:35.45#ibcon#about to read 5, iclass 16, count 0 2006.285.21:44:35.45#ibcon#read 5, iclass 16, count 0 2006.285.21:44:35.45#ibcon#about to read 6, iclass 16, count 0 2006.285.21:44:35.45#ibcon#read 6, iclass 16, count 0 2006.285.21:44:35.45#ibcon#end of sib2, iclass 16, count 0 2006.285.21:44:35.45#ibcon#*after write, iclass 16, count 0 2006.285.21:44:35.45#ibcon#*before return 0, iclass 16, count 0 2006.285.21:44:35.45#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:44:35.45#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.21:44:35.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:44:35.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:44:35.45$vck44/vblo=3,649.99 2006.285.21:44:35.46#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.21:44:35.46#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.21:44:35.46#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:35.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:44:35.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:44:35.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:44:35.46#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:44:35.46#ibcon#first serial, iclass 18, count 0 2006.285.21:44:35.46#ibcon#enter sib2, iclass 18, count 0 2006.285.21:44:35.46#ibcon#flushed, iclass 18, count 0 2006.285.21:44:35.46#ibcon#about to write, iclass 18, count 0 2006.285.21:44:35.46#ibcon#wrote, iclass 18, count 0 2006.285.21:44:35.46#ibcon#about to read 3, iclass 18, count 0 2006.285.21:44:35.47#ibcon#read 3, iclass 18, count 0 2006.285.21:44:35.47#ibcon#about to read 4, iclass 18, count 0 2006.285.21:44:35.47#ibcon#read 4, iclass 18, count 0 2006.285.21:44:35.47#ibcon#about to read 5, iclass 18, count 0 2006.285.21:44:35.47#ibcon#read 5, iclass 18, count 0 2006.285.21:44:35.47#ibcon#about to read 6, iclass 18, count 0 2006.285.21:44:35.47#ibcon#read 6, iclass 18, count 0 2006.285.21:44:35.47#ibcon#end of sib2, iclass 18, count 0 2006.285.21:44:35.47#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:44:35.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:44:35.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:44:35.47#ibcon#*before write, iclass 18, count 0 2006.285.21:44:35.47#ibcon#enter sib2, iclass 18, count 0 2006.285.21:44:35.47#ibcon#flushed, iclass 18, count 0 2006.285.21:44:35.47#ibcon#about to write, iclass 18, count 0 2006.285.21:44:35.47#ibcon#wrote, iclass 18, count 0 2006.285.21:44:35.47#ibcon#about to read 3, iclass 18, count 0 2006.285.21:44:35.51#ibcon#read 3, iclass 18, count 0 2006.285.21:44:35.51#ibcon#about to read 4, iclass 18, count 0 2006.285.21:44:35.51#ibcon#read 4, iclass 18, count 0 2006.285.21:44:35.51#ibcon#about to read 5, iclass 18, count 0 2006.285.21:44:35.51#ibcon#read 5, iclass 18, count 0 2006.285.21:44:35.51#ibcon#about to read 6, iclass 18, count 0 2006.285.21:44:35.51#ibcon#read 6, iclass 18, count 0 2006.285.21:44:35.51#ibcon#end of sib2, iclass 18, count 0 2006.285.21:44:35.51#ibcon#*after write, iclass 18, count 0 2006.285.21:44:35.51#ibcon#*before return 0, iclass 18, count 0 2006.285.21:44:35.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:44:35.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:44:35.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:44:35.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:44:35.51$vck44/vb=3,4 2006.285.21:44:35.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.21:44:35.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.21:44:35.51#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:35.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:44:35.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:44:35.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:44:35.57#ibcon#enter wrdev, iclass 20, count 2 2006.285.21:44:35.57#ibcon#first serial, iclass 20, count 2 2006.285.21:44:35.57#ibcon#enter sib2, iclass 20, count 2 2006.285.21:44:35.57#ibcon#flushed, iclass 20, count 2 2006.285.21:44:35.57#ibcon#about to write, iclass 20, count 2 2006.285.21:44:35.57#ibcon#wrote, iclass 20, count 2 2006.285.21:44:35.57#ibcon#about to read 3, iclass 20, count 2 2006.285.21:44:35.59#ibcon#read 3, iclass 20, count 2 2006.285.21:44:35.59#ibcon#about to read 4, iclass 20, count 2 2006.285.21:44:35.59#ibcon#read 4, iclass 20, count 2 2006.285.21:44:35.59#ibcon#about to read 5, iclass 20, count 2 2006.285.21:44:35.59#ibcon#read 5, iclass 20, count 2 2006.285.21:44:35.59#ibcon#about to read 6, iclass 20, count 2 2006.285.21:44:35.59#ibcon#read 6, iclass 20, count 2 2006.285.21:44:35.59#ibcon#end of sib2, iclass 20, count 2 2006.285.21:44:35.59#ibcon#*mode == 0, iclass 20, count 2 2006.285.21:44:35.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.21:44:35.59#ibcon#[27=AT03-04\r\n] 2006.285.21:44:35.59#ibcon#*before write, iclass 20, count 2 2006.285.21:44:35.59#ibcon#enter sib2, iclass 20, count 2 2006.285.21:44:35.59#ibcon#flushed, iclass 20, count 2 2006.285.21:44:35.59#ibcon#about to write, iclass 20, count 2 2006.285.21:44:35.59#ibcon#wrote, iclass 20, count 2 2006.285.21:44:35.59#ibcon#about to read 3, iclass 20, count 2 2006.285.21:44:35.62#ibcon#read 3, iclass 20, count 2 2006.285.21:44:35.62#ibcon#about to read 4, iclass 20, count 2 2006.285.21:44:35.62#ibcon#read 4, iclass 20, count 2 2006.285.21:44:35.62#ibcon#about to read 5, iclass 20, count 2 2006.285.21:44:35.62#ibcon#read 5, iclass 20, count 2 2006.285.21:44:35.62#ibcon#about to read 6, iclass 20, count 2 2006.285.21:44:35.62#ibcon#read 6, iclass 20, count 2 2006.285.21:44:35.62#ibcon#end of sib2, iclass 20, count 2 2006.285.21:44:35.62#ibcon#*after write, iclass 20, count 2 2006.285.21:44:35.62#ibcon#*before return 0, iclass 20, count 2 2006.285.21:44:35.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:44:35.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.21:44:35.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.21:44:35.62#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:35.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:44:35.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:44:35.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:44:35.74#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:44:35.74#ibcon#first serial, iclass 20, count 0 2006.285.21:44:35.74#ibcon#enter sib2, iclass 20, count 0 2006.285.21:44:35.74#ibcon#flushed, iclass 20, count 0 2006.285.21:44:35.74#ibcon#about to write, iclass 20, count 0 2006.285.21:44:35.74#ibcon#wrote, iclass 20, count 0 2006.285.21:44:35.74#ibcon#about to read 3, iclass 20, count 0 2006.285.21:44:35.76#ibcon#read 3, iclass 20, count 0 2006.285.21:44:35.76#ibcon#about to read 4, iclass 20, count 0 2006.285.21:44:35.76#ibcon#read 4, iclass 20, count 0 2006.285.21:44:35.76#ibcon#about to read 5, iclass 20, count 0 2006.285.21:44:35.76#ibcon#read 5, iclass 20, count 0 2006.285.21:44:35.76#ibcon#about to read 6, iclass 20, count 0 2006.285.21:44:35.76#ibcon#read 6, iclass 20, count 0 2006.285.21:44:35.76#ibcon#end of sib2, iclass 20, count 0 2006.285.21:44:35.76#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:44:35.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:44:35.76#ibcon#[27=USB\r\n] 2006.285.21:44:35.76#ibcon#*before write, iclass 20, count 0 2006.285.21:44:35.76#ibcon#enter sib2, iclass 20, count 0 2006.285.21:44:35.76#ibcon#flushed, iclass 20, count 0 2006.285.21:44:35.76#ibcon#about to write, iclass 20, count 0 2006.285.21:44:35.76#ibcon#wrote, iclass 20, count 0 2006.285.21:44:35.76#ibcon#about to read 3, iclass 20, count 0 2006.285.21:44:35.79#ibcon#read 3, iclass 20, count 0 2006.285.21:44:35.79#ibcon#about to read 4, iclass 20, count 0 2006.285.21:44:35.79#ibcon#read 4, iclass 20, count 0 2006.285.21:44:35.79#ibcon#about to read 5, iclass 20, count 0 2006.285.21:44:35.79#ibcon#read 5, iclass 20, count 0 2006.285.21:44:35.79#ibcon#about to read 6, iclass 20, count 0 2006.285.21:44:35.79#ibcon#read 6, iclass 20, count 0 2006.285.21:44:35.79#ibcon#end of sib2, iclass 20, count 0 2006.285.21:44:35.79#ibcon#*after write, iclass 20, count 0 2006.285.21:44:35.79#ibcon#*before return 0, iclass 20, count 0 2006.285.21:44:35.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:44:35.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.21:44:35.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:44:35.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:44:35.79$vck44/vblo=4,679.99 2006.285.21:44:35.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.21:44:35.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.21:44:35.79#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:35.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:44:35.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:44:35.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:44:35.79#ibcon#enter wrdev, iclass 22, count 0 2006.285.21:44:35.79#ibcon#first serial, iclass 22, count 0 2006.285.21:44:35.79#ibcon#enter sib2, iclass 22, count 0 2006.285.21:44:35.79#ibcon#flushed, iclass 22, count 0 2006.285.21:44:35.79#ibcon#about to write, iclass 22, count 0 2006.285.21:44:35.79#ibcon#wrote, iclass 22, count 0 2006.285.21:44:35.79#ibcon#about to read 3, iclass 22, count 0 2006.285.21:44:35.81#ibcon#read 3, iclass 22, count 0 2006.285.21:44:35.81#ibcon#about to read 4, iclass 22, count 0 2006.285.21:44:35.81#ibcon#read 4, iclass 22, count 0 2006.285.21:44:35.81#ibcon#about to read 5, iclass 22, count 0 2006.285.21:44:35.81#ibcon#read 5, iclass 22, count 0 2006.285.21:44:35.81#ibcon#about to read 6, iclass 22, count 0 2006.285.21:44:35.81#ibcon#read 6, iclass 22, count 0 2006.285.21:44:35.81#ibcon#end of sib2, iclass 22, count 0 2006.285.21:44:35.81#ibcon#*mode == 0, iclass 22, count 0 2006.285.21:44:35.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.21:44:35.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:44:35.81#ibcon#*before write, iclass 22, count 0 2006.285.21:44:35.81#ibcon#enter sib2, iclass 22, count 0 2006.285.21:44:35.81#ibcon#flushed, iclass 22, count 0 2006.285.21:44:35.81#ibcon#about to write, iclass 22, count 0 2006.285.21:44:35.81#ibcon#wrote, iclass 22, count 0 2006.285.21:44:35.81#ibcon#about to read 3, iclass 22, count 0 2006.285.21:44:35.85#ibcon#read 3, iclass 22, count 0 2006.285.21:44:35.85#ibcon#about to read 4, iclass 22, count 0 2006.285.21:44:35.85#ibcon#read 4, iclass 22, count 0 2006.285.21:44:35.85#ibcon#about to read 5, iclass 22, count 0 2006.285.21:44:35.85#ibcon#read 5, iclass 22, count 0 2006.285.21:44:35.85#ibcon#about to read 6, iclass 22, count 0 2006.285.21:44:35.85#ibcon#read 6, iclass 22, count 0 2006.285.21:44:35.85#ibcon#end of sib2, iclass 22, count 0 2006.285.21:44:35.85#ibcon#*after write, iclass 22, count 0 2006.285.21:44:35.85#ibcon#*before return 0, iclass 22, count 0 2006.285.21:44:35.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:44:35.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.21:44:35.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.21:44:35.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.21:44:35.85$vck44/vb=4,5 2006.285.21:44:35.85#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.21:44:35.85#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.21:44:35.85#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:35.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:44:35.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:44:35.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:44:35.91#ibcon#enter wrdev, iclass 24, count 2 2006.285.21:44:35.91#ibcon#first serial, iclass 24, count 2 2006.285.21:44:35.91#ibcon#enter sib2, iclass 24, count 2 2006.285.21:44:35.91#ibcon#flushed, iclass 24, count 2 2006.285.21:44:35.91#ibcon#about to write, iclass 24, count 2 2006.285.21:44:35.91#ibcon#wrote, iclass 24, count 2 2006.285.21:44:35.91#ibcon#about to read 3, iclass 24, count 2 2006.285.21:44:35.93#ibcon#read 3, iclass 24, count 2 2006.285.21:44:35.93#ibcon#about to read 4, iclass 24, count 2 2006.285.21:44:35.93#ibcon#read 4, iclass 24, count 2 2006.285.21:44:35.93#ibcon#about to read 5, iclass 24, count 2 2006.285.21:44:35.93#ibcon#read 5, iclass 24, count 2 2006.285.21:44:35.93#ibcon#about to read 6, iclass 24, count 2 2006.285.21:44:35.93#ibcon#read 6, iclass 24, count 2 2006.285.21:44:35.93#ibcon#end of sib2, iclass 24, count 2 2006.285.21:44:35.93#ibcon#*mode == 0, iclass 24, count 2 2006.285.21:44:35.93#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.21:44:35.93#ibcon#[27=AT04-05\r\n] 2006.285.21:44:35.93#ibcon#*before write, iclass 24, count 2 2006.285.21:44:35.93#ibcon#enter sib2, iclass 24, count 2 2006.285.21:44:35.93#ibcon#flushed, iclass 24, count 2 2006.285.21:44:35.93#ibcon#about to write, iclass 24, count 2 2006.285.21:44:35.93#ibcon#wrote, iclass 24, count 2 2006.285.21:44:35.93#ibcon#about to read 3, iclass 24, count 2 2006.285.21:44:35.96#ibcon#read 3, iclass 24, count 2 2006.285.21:44:35.96#ibcon#about to read 4, iclass 24, count 2 2006.285.21:44:35.96#ibcon#read 4, iclass 24, count 2 2006.285.21:44:35.96#ibcon#about to read 5, iclass 24, count 2 2006.285.21:44:35.96#ibcon#read 5, iclass 24, count 2 2006.285.21:44:35.96#ibcon#about to read 6, iclass 24, count 2 2006.285.21:44:35.96#ibcon#read 6, iclass 24, count 2 2006.285.21:44:35.96#ibcon#end of sib2, iclass 24, count 2 2006.285.21:44:35.96#ibcon#*after write, iclass 24, count 2 2006.285.21:44:35.96#ibcon#*before return 0, iclass 24, count 2 2006.285.21:44:35.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:44:35.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.21:44:35.96#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.21:44:35.96#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:35.96#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:44:36.08#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:44:36.08#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:44:36.08#ibcon#enter wrdev, iclass 24, count 0 2006.285.21:44:36.08#ibcon#first serial, iclass 24, count 0 2006.285.21:44:36.08#ibcon#enter sib2, iclass 24, count 0 2006.285.21:44:36.08#ibcon#flushed, iclass 24, count 0 2006.285.21:44:36.08#ibcon#about to write, iclass 24, count 0 2006.285.21:44:36.08#ibcon#wrote, iclass 24, count 0 2006.285.21:44:36.08#ibcon#about to read 3, iclass 24, count 0 2006.285.21:44:36.10#ibcon#read 3, iclass 24, count 0 2006.285.21:44:36.10#ibcon#about to read 4, iclass 24, count 0 2006.285.21:44:36.10#ibcon#read 4, iclass 24, count 0 2006.285.21:44:36.10#ibcon#about to read 5, iclass 24, count 0 2006.285.21:44:36.10#ibcon#read 5, iclass 24, count 0 2006.285.21:44:36.10#ibcon#about to read 6, iclass 24, count 0 2006.285.21:44:36.10#ibcon#read 6, iclass 24, count 0 2006.285.21:44:36.10#ibcon#end of sib2, iclass 24, count 0 2006.285.21:44:36.10#ibcon#*mode == 0, iclass 24, count 0 2006.285.21:44:36.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.21:44:36.10#ibcon#[27=USB\r\n] 2006.285.21:44:36.10#ibcon#*before write, iclass 24, count 0 2006.285.21:44:36.10#ibcon#enter sib2, iclass 24, count 0 2006.285.21:44:36.10#ibcon#flushed, iclass 24, count 0 2006.285.21:44:36.10#ibcon#about to write, iclass 24, count 0 2006.285.21:44:36.10#ibcon#wrote, iclass 24, count 0 2006.285.21:44:36.10#ibcon#about to read 3, iclass 24, count 0 2006.285.21:44:36.13#ibcon#read 3, iclass 24, count 0 2006.285.21:44:36.13#ibcon#about to read 4, iclass 24, count 0 2006.285.21:44:36.13#ibcon#read 4, iclass 24, count 0 2006.285.21:44:36.13#ibcon#about to read 5, iclass 24, count 0 2006.285.21:44:36.13#ibcon#read 5, iclass 24, count 0 2006.285.21:44:36.13#ibcon#about to read 6, iclass 24, count 0 2006.285.21:44:36.13#ibcon#read 6, iclass 24, count 0 2006.285.21:44:36.13#ibcon#end of sib2, iclass 24, count 0 2006.285.21:44:36.13#ibcon#*after write, iclass 24, count 0 2006.285.21:44:36.13#ibcon#*before return 0, iclass 24, count 0 2006.285.21:44:36.13#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:44:36.13#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.21:44:36.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.21:44:36.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.21:44:36.13$vck44/vblo=5,709.99 2006.285.21:44:36.13#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.21:44:36.13#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.21:44:36.13#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:36.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:44:36.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:44:36.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:44:36.13#ibcon#enter wrdev, iclass 26, count 0 2006.285.21:44:36.13#ibcon#first serial, iclass 26, count 0 2006.285.21:44:36.13#ibcon#enter sib2, iclass 26, count 0 2006.285.21:44:36.13#ibcon#flushed, iclass 26, count 0 2006.285.21:44:36.13#ibcon#about to write, iclass 26, count 0 2006.285.21:44:36.13#ibcon#wrote, iclass 26, count 0 2006.285.21:44:36.13#ibcon#about to read 3, iclass 26, count 0 2006.285.21:44:36.15#ibcon#read 3, iclass 26, count 0 2006.285.21:44:36.15#ibcon#about to read 4, iclass 26, count 0 2006.285.21:44:36.15#ibcon#read 4, iclass 26, count 0 2006.285.21:44:36.15#ibcon#about to read 5, iclass 26, count 0 2006.285.21:44:36.15#ibcon#read 5, iclass 26, count 0 2006.285.21:44:36.15#ibcon#about to read 6, iclass 26, count 0 2006.285.21:44:36.15#ibcon#read 6, iclass 26, count 0 2006.285.21:44:36.15#ibcon#end of sib2, iclass 26, count 0 2006.285.21:44:36.15#ibcon#*mode == 0, iclass 26, count 0 2006.285.21:44:36.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.21:44:36.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:44:36.15#ibcon#*before write, iclass 26, count 0 2006.285.21:44:36.15#ibcon#enter sib2, iclass 26, count 0 2006.285.21:44:36.15#ibcon#flushed, iclass 26, count 0 2006.285.21:44:36.15#ibcon#about to write, iclass 26, count 0 2006.285.21:44:36.15#ibcon#wrote, iclass 26, count 0 2006.285.21:44:36.15#ibcon#about to read 3, iclass 26, count 0 2006.285.21:44:36.19#ibcon#read 3, iclass 26, count 0 2006.285.21:44:36.19#ibcon#about to read 4, iclass 26, count 0 2006.285.21:44:36.19#ibcon#read 4, iclass 26, count 0 2006.285.21:44:36.19#ibcon#about to read 5, iclass 26, count 0 2006.285.21:44:36.19#ibcon#read 5, iclass 26, count 0 2006.285.21:44:36.19#ibcon#about to read 6, iclass 26, count 0 2006.285.21:44:36.19#ibcon#read 6, iclass 26, count 0 2006.285.21:44:36.19#ibcon#end of sib2, iclass 26, count 0 2006.285.21:44:36.19#ibcon#*after write, iclass 26, count 0 2006.285.21:44:36.19#ibcon#*before return 0, iclass 26, count 0 2006.285.21:44:36.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:44:36.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.21:44:36.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.21:44:36.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.21:44:36.19$vck44/vb=5,4 2006.285.21:44:36.19#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.21:44:36.19#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.21:44:36.19#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:36.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:44:36.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:44:36.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:44:36.25#ibcon#enter wrdev, iclass 28, count 2 2006.285.21:44:36.25#ibcon#first serial, iclass 28, count 2 2006.285.21:44:36.25#ibcon#enter sib2, iclass 28, count 2 2006.285.21:44:36.25#ibcon#flushed, iclass 28, count 2 2006.285.21:44:36.25#ibcon#about to write, iclass 28, count 2 2006.285.21:44:36.25#ibcon#wrote, iclass 28, count 2 2006.285.21:44:36.25#ibcon#about to read 3, iclass 28, count 2 2006.285.21:44:36.27#ibcon#read 3, iclass 28, count 2 2006.285.21:44:36.27#ibcon#about to read 4, iclass 28, count 2 2006.285.21:44:36.27#ibcon#read 4, iclass 28, count 2 2006.285.21:44:36.27#ibcon#about to read 5, iclass 28, count 2 2006.285.21:44:36.27#ibcon#read 5, iclass 28, count 2 2006.285.21:44:36.27#ibcon#about to read 6, iclass 28, count 2 2006.285.21:44:36.27#ibcon#read 6, iclass 28, count 2 2006.285.21:44:36.27#ibcon#end of sib2, iclass 28, count 2 2006.285.21:44:36.27#ibcon#*mode == 0, iclass 28, count 2 2006.285.21:44:36.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.21:44:36.27#ibcon#[27=AT05-04\r\n] 2006.285.21:44:36.27#ibcon#*before write, iclass 28, count 2 2006.285.21:44:36.27#ibcon#enter sib2, iclass 28, count 2 2006.285.21:44:36.27#ibcon#flushed, iclass 28, count 2 2006.285.21:44:36.27#ibcon#about to write, iclass 28, count 2 2006.285.21:44:36.27#ibcon#wrote, iclass 28, count 2 2006.285.21:44:36.27#ibcon#about to read 3, iclass 28, count 2 2006.285.21:44:36.30#ibcon#read 3, iclass 28, count 2 2006.285.21:44:36.30#ibcon#about to read 4, iclass 28, count 2 2006.285.21:44:36.30#ibcon#read 4, iclass 28, count 2 2006.285.21:44:36.30#ibcon#about to read 5, iclass 28, count 2 2006.285.21:44:36.30#ibcon#read 5, iclass 28, count 2 2006.285.21:44:36.30#ibcon#about to read 6, iclass 28, count 2 2006.285.21:44:36.30#ibcon#read 6, iclass 28, count 2 2006.285.21:44:36.30#ibcon#end of sib2, iclass 28, count 2 2006.285.21:44:36.30#ibcon#*after write, iclass 28, count 2 2006.285.21:44:36.30#ibcon#*before return 0, iclass 28, count 2 2006.285.21:44:36.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:44:36.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.21:44:36.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.21:44:36.30#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:36.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:44:36.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:44:36.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:44:36.42#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:44:36.42#ibcon#first serial, iclass 28, count 0 2006.285.21:44:36.42#ibcon#enter sib2, iclass 28, count 0 2006.285.21:44:36.42#ibcon#flushed, iclass 28, count 0 2006.285.21:44:36.42#ibcon#about to write, iclass 28, count 0 2006.285.21:44:36.42#ibcon#wrote, iclass 28, count 0 2006.285.21:44:36.42#ibcon#about to read 3, iclass 28, count 0 2006.285.21:44:36.44#ibcon#read 3, iclass 28, count 0 2006.285.21:44:36.44#ibcon#about to read 4, iclass 28, count 0 2006.285.21:44:36.44#ibcon#read 4, iclass 28, count 0 2006.285.21:44:36.44#ibcon#about to read 5, iclass 28, count 0 2006.285.21:44:36.44#ibcon#read 5, iclass 28, count 0 2006.285.21:44:36.44#ibcon#about to read 6, iclass 28, count 0 2006.285.21:44:36.44#ibcon#read 6, iclass 28, count 0 2006.285.21:44:36.44#ibcon#end of sib2, iclass 28, count 0 2006.285.21:44:36.44#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:44:36.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:44:36.44#ibcon#[27=USB\r\n] 2006.285.21:44:36.44#ibcon#*before write, iclass 28, count 0 2006.285.21:44:36.44#ibcon#enter sib2, iclass 28, count 0 2006.285.21:44:36.44#ibcon#flushed, iclass 28, count 0 2006.285.21:44:36.44#ibcon#about to write, iclass 28, count 0 2006.285.21:44:36.44#ibcon#wrote, iclass 28, count 0 2006.285.21:44:36.44#ibcon#about to read 3, iclass 28, count 0 2006.285.21:44:36.47#ibcon#read 3, iclass 28, count 0 2006.285.21:44:36.47#ibcon#about to read 4, iclass 28, count 0 2006.285.21:44:36.47#ibcon#read 4, iclass 28, count 0 2006.285.21:44:36.47#ibcon#about to read 5, iclass 28, count 0 2006.285.21:44:36.47#ibcon#read 5, iclass 28, count 0 2006.285.21:44:36.47#ibcon#about to read 6, iclass 28, count 0 2006.285.21:44:36.47#ibcon#read 6, iclass 28, count 0 2006.285.21:44:36.47#ibcon#end of sib2, iclass 28, count 0 2006.285.21:44:36.47#ibcon#*after write, iclass 28, count 0 2006.285.21:44:36.47#ibcon#*before return 0, iclass 28, count 0 2006.285.21:44:36.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:44:36.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.21:44:36.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:44:36.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:44:36.47$vck44/vblo=6,719.99 2006.285.21:44:36.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.21:44:36.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.21:44:36.49#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:36.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:44:36.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:44:36.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:44:36.49#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:44:36.49#ibcon#first serial, iclass 30, count 0 2006.285.21:44:36.49#ibcon#enter sib2, iclass 30, count 0 2006.285.21:44:36.49#ibcon#flushed, iclass 30, count 0 2006.285.21:44:36.49#ibcon#about to write, iclass 30, count 0 2006.285.21:44:36.49#ibcon#wrote, iclass 30, count 0 2006.285.21:44:36.49#ibcon#about to read 3, iclass 30, count 0 2006.285.21:44:36.51#ibcon#read 3, iclass 30, count 0 2006.285.21:44:36.51#ibcon#about to read 4, iclass 30, count 0 2006.285.21:44:36.51#ibcon#read 4, iclass 30, count 0 2006.285.21:44:36.51#ibcon#about to read 5, iclass 30, count 0 2006.285.21:44:36.51#ibcon#read 5, iclass 30, count 0 2006.285.21:44:36.51#ibcon#about to read 6, iclass 30, count 0 2006.285.21:44:36.51#ibcon#read 6, iclass 30, count 0 2006.285.21:44:36.51#ibcon#end of sib2, iclass 30, count 0 2006.285.21:44:36.51#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:44:36.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:44:36.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:44:36.51#ibcon#*before write, iclass 30, count 0 2006.285.21:44:36.51#ibcon#enter sib2, iclass 30, count 0 2006.285.21:44:36.51#ibcon#flushed, iclass 30, count 0 2006.285.21:44:36.51#ibcon#about to write, iclass 30, count 0 2006.285.21:44:36.51#ibcon#wrote, iclass 30, count 0 2006.285.21:44:36.51#ibcon#about to read 3, iclass 30, count 0 2006.285.21:44:36.55#ibcon#read 3, iclass 30, count 0 2006.285.21:44:36.55#ibcon#about to read 4, iclass 30, count 0 2006.285.21:44:36.55#ibcon#read 4, iclass 30, count 0 2006.285.21:44:36.55#ibcon#about to read 5, iclass 30, count 0 2006.285.21:44:36.55#ibcon#read 5, iclass 30, count 0 2006.285.21:44:36.55#ibcon#about to read 6, iclass 30, count 0 2006.285.21:44:36.55#ibcon#read 6, iclass 30, count 0 2006.285.21:44:36.55#ibcon#end of sib2, iclass 30, count 0 2006.285.21:44:36.55#ibcon#*after write, iclass 30, count 0 2006.285.21:44:36.55#ibcon#*before return 0, iclass 30, count 0 2006.285.21:44:36.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:44:36.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.21:44:36.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:44:36.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:44:36.55$vck44/vb=6,3 2006.285.21:44:36.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.21:44:36.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.21:44:36.55#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:36.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:44:36.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:44:36.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:44:36.59#ibcon#enter wrdev, iclass 32, count 2 2006.285.21:44:36.59#ibcon#first serial, iclass 32, count 2 2006.285.21:44:36.59#ibcon#enter sib2, iclass 32, count 2 2006.285.21:44:36.59#ibcon#flushed, iclass 32, count 2 2006.285.21:44:36.59#ibcon#about to write, iclass 32, count 2 2006.285.21:44:36.59#ibcon#wrote, iclass 32, count 2 2006.285.21:44:36.59#ibcon#about to read 3, iclass 32, count 2 2006.285.21:44:36.61#ibcon#read 3, iclass 32, count 2 2006.285.21:44:36.61#ibcon#about to read 4, iclass 32, count 2 2006.285.21:44:36.61#ibcon#read 4, iclass 32, count 2 2006.285.21:44:36.61#ibcon#about to read 5, iclass 32, count 2 2006.285.21:44:36.61#ibcon#read 5, iclass 32, count 2 2006.285.21:44:36.61#ibcon#about to read 6, iclass 32, count 2 2006.285.21:44:36.61#ibcon#read 6, iclass 32, count 2 2006.285.21:44:36.61#ibcon#end of sib2, iclass 32, count 2 2006.285.21:44:36.61#ibcon#*mode == 0, iclass 32, count 2 2006.285.21:44:36.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.21:44:36.61#ibcon#[27=AT06-03\r\n] 2006.285.21:44:36.61#ibcon#*before write, iclass 32, count 2 2006.285.21:44:36.61#ibcon#enter sib2, iclass 32, count 2 2006.285.21:44:36.61#ibcon#flushed, iclass 32, count 2 2006.285.21:44:36.61#ibcon#about to write, iclass 32, count 2 2006.285.21:44:36.61#ibcon#wrote, iclass 32, count 2 2006.285.21:44:36.61#ibcon#about to read 3, iclass 32, count 2 2006.285.21:44:36.64#ibcon#read 3, iclass 32, count 2 2006.285.21:44:36.64#ibcon#about to read 4, iclass 32, count 2 2006.285.21:44:36.64#ibcon#read 4, iclass 32, count 2 2006.285.21:44:36.64#ibcon#about to read 5, iclass 32, count 2 2006.285.21:44:36.64#ibcon#read 5, iclass 32, count 2 2006.285.21:44:36.64#ibcon#about to read 6, iclass 32, count 2 2006.285.21:44:36.64#ibcon#read 6, iclass 32, count 2 2006.285.21:44:36.64#ibcon#end of sib2, iclass 32, count 2 2006.285.21:44:36.64#ibcon#*after write, iclass 32, count 2 2006.285.21:44:36.64#ibcon#*before return 0, iclass 32, count 2 2006.285.21:44:36.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:44:36.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.21:44:36.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.21:44:36.64#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:36.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:44:36.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:44:36.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:44:36.76#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:44:36.76#ibcon#first serial, iclass 32, count 0 2006.285.21:44:36.76#ibcon#enter sib2, iclass 32, count 0 2006.285.21:44:36.76#ibcon#flushed, iclass 32, count 0 2006.285.21:44:36.76#ibcon#about to write, iclass 32, count 0 2006.285.21:44:36.76#ibcon#wrote, iclass 32, count 0 2006.285.21:44:36.76#ibcon#about to read 3, iclass 32, count 0 2006.285.21:44:36.78#ibcon#read 3, iclass 32, count 0 2006.285.21:44:36.78#ibcon#about to read 4, iclass 32, count 0 2006.285.21:44:36.78#ibcon#read 4, iclass 32, count 0 2006.285.21:44:36.78#ibcon#about to read 5, iclass 32, count 0 2006.285.21:44:36.78#ibcon#read 5, iclass 32, count 0 2006.285.21:44:36.78#ibcon#about to read 6, iclass 32, count 0 2006.285.21:44:36.78#ibcon#read 6, iclass 32, count 0 2006.285.21:44:36.78#ibcon#end of sib2, iclass 32, count 0 2006.285.21:44:36.78#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:44:36.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:44:36.78#ibcon#[27=USB\r\n] 2006.285.21:44:36.78#ibcon#*before write, iclass 32, count 0 2006.285.21:44:36.78#ibcon#enter sib2, iclass 32, count 0 2006.285.21:44:36.78#ibcon#flushed, iclass 32, count 0 2006.285.21:44:36.78#ibcon#about to write, iclass 32, count 0 2006.285.21:44:36.78#ibcon#wrote, iclass 32, count 0 2006.285.21:44:36.78#ibcon#about to read 3, iclass 32, count 0 2006.285.21:44:36.81#ibcon#read 3, iclass 32, count 0 2006.285.21:44:36.81#ibcon#about to read 4, iclass 32, count 0 2006.285.21:44:36.81#ibcon#read 4, iclass 32, count 0 2006.285.21:44:36.81#ibcon#about to read 5, iclass 32, count 0 2006.285.21:44:36.81#ibcon#read 5, iclass 32, count 0 2006.285.21:44:36.81#ibcon#about to read 6, iclass 32, count 0 2006.285.21:44:36.81#ibcon#read 6, iclass 32, count 0 2006.285.21:44:36.81#ibcon#end of sib2, iclass 32, count 0 2006.285.21:44:36.81#ibcon#*after write, iclass 32, count 0 2006.285.21:44:36.81#ibcon#*before return 0, iclass 32, count 0 2006.285.21:44:36.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:44:36.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.21:44:36.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:44:36.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:44:36.81$vck44/vblo=7,734.99 2006.285.21:44:36.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.21:44:36.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.21:44:36.81#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:36.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:44:36.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:44:36.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:44:36.81#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:44:36.81#ibcon#first serial, iclass 34, count 0 2006.285.21:44:36.81#ibcon#enter sib2, iclass 34, count 0 2006.285.21:44:36.81#ibcon#flushed, iclass 34, count 0 2006.285.21:44:36.81#ibcon#about to write, iclass 34, count 0 2006.285.21:44:36.81#ibcon#wrote, iclass 34, count 0 2006.285.21:44:36.81#ibcon#about to read 3, iclass 34, count 0 2006.285.21:44:36.83#ibcon#read 3, iclass 34, count 0 2006.285.21:44:36.83#ibcon#about to read 4, iclass 34, count 0 2006.285.21:44:36.83#ibcon#read 4, iclass 34, count 0 2006.285.21:44:36.83#ibcon#about to read 5, iclass 34, count 0 2006.285.21:44:36.83#ibcon#read 5, iclass 34, count 0 2006.285.21:44:36.83#ibcon#about to read 6, iclass 34, count 0 2006.285.21:44:36.83#ibcon#read 6, iclass 34, count 0 2006.285.21:44:36.83#ibcon#end of sib2, iclass 34, count 0 2006.285.21:44:36.83#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:44:36.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:44:36.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:44:36.83#ibcon#*before write, iclass 34, count 0 2006.285.21:44:36.83#ibcon#enter sib2, iclass 34, count 0 2006.285.21:44:36.83#ibcon#flushed, iclass 34, count 0 2006.285.21:44:36.83#ibcon#about to write, iclass 34, count 0 2006.285.21:44:36.83#ibcon#wrote, iclass 34, count 0 2006.285.21:44:36.83#ibcon#about to read 3, iclass 34, count 0 2006.285.21:44:36.87#ibcon#read 3, iclass 34, count 0 2006.285.21:44:36.87#ibcon#about to read 4, iclass 34, count 0 2006.285.21:44:36.87#ibcon#read 4, iclass 34, count 0 2006.285.21:44:36.87#ibcon#about to read 5, iclass 34, count 0 2006.285.21:44:36.87#ibcon#read 5, iclass 34, count 0 2006.285.21:44:36.87#ibcon#about to read 6, iclass 34, count 0 2006.285.21:44:36.87#ibcon#read 6, iclass 34, count 0 2006.285.21:44:36.87#ibcon#end of sib2, iclass 34, count 0 2006.285.21:44:36.87#ibcon#*after write, iclass 34, count 0 2006.285.21:44:36.87#ibcon#*before return 0, iclass 34, count 0 2006.285.21:44:36.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:44:36.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.21:44:36.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:44:36.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:44:36.87$vck44/vb=7,4 2006.285.21:44:36.87#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.21:44:36.87#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.21:44:36.87#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:36.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:44:36.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:44:36.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:44:36.93#ibcon#enter wrdev, iclass 36, count 2 2006.285.21:44:36.93#ibcon#first serial, iclass 36, count 2 2006.285.21:44:36.93#ibcon#enter sib2, iclass 36, count 2 2006.285.21:44:36.93#ibcon#flushed, iclass 36, count 2 2006.285.21:44:36.93#ibcon#about to write, iclass 36, count 2 2006.285.21:44:36.93#ibcon#wrote, iclass 36, count 2 2006.285.21:44:36.93#ibcon#about to read 3, iclass 36, count 2 2006.285.21:44:36.95#ibcon#read 3, iclass 36, count 2 2006.285.21:44:36.95#ibcon#about to read 4, iclass 36, count 2 2006.285.21:44:36.95#ibcon#read 4, iclass 36, count 2 2006.285.21:44:36.95#ibcon#about to read 5, iclass 36, count 2 2006.285.21:44:36.95#ibcon#read 5, iclass 36, count 2 2006.285.21:44:36.95#ibcon#about to read 6, iclass 36, count 2 2006.285.21:44:36.95#ibcon#read 6, iclass 36, count 2 2006.285.21:44:36.95#ibcon#end of sib2, iclass 36, count 2 2006.285.21:44:36.95#ibcon#*mode == 0, iclass 36, count 2 2006.285.21:44:36.95#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.21:44:36.95#ibcon#[27=AT07-04\r\n] 2006.285.21:44:36.95#ibcon#*before write, iclass 36, count 2 2006.285.21:44:36.95#ibcon#enter sib2, iclass 36, count 2 2006.285.21:44:36.95#ibcon#flushed, iclass 36, count 2 2006.285.21:44:36.95#ibcon#about to write, iclass 36, count 2 2006.285.21:44:36.95#ibcon#wrote, iclass 36, count 2 2006.285.21:44:36.95#ibcon#about to read 3, iclass 36, count 2 2006.285.21:44:36.98#ibcon#read 3, iclass 36, count 2 2006.285.21:44:36.98#ibcon#about to read 4, iclass 36, count 2 2006.285.21:44:36.98#ibcon#read 4, iclass 36, count 2 2006.285.21:44:36.98#ibcon#about to read 5, iclass 36, count 2 2006.285.21:44:36.98#ibcon#read 5, iclass 36, count 2 2006.285.21:44:36.98#ibcon#about to read 6, iclass 36, count 2 2006.285.21:44:36.98#ibcon#read 6, iclass 36, count 2 2006.285.21:44:36.98#ibcon#end of sib2, iclass 36, count 2 2006.285.21:44:36.98#ibcon#*after write, iclass 36, count 2 2006.285.21:44:36.98#ibcon#*before return 0, iclass 36, count 2 2006.285.21:44:36.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:44:36.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.21:44:36.98#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.21:44:36.98#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:36.98#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:44:37.10#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:44:37.10#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:44:37.10#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:44:37.10#ibcon#first serial, iclass 36, count 0 2006.285.21:44:37.10#ibcon#enter sib2, iclass 36, count 0 2006.285.21:44:37.10#ibcon#flushed, iclass 36, count 0 2006.285.21:44:37.10#ibcon#about to write, iclass 36, count 0 2006.285.21:44:37.10#ibcon#wrote, iclass 36, count 0 2006.285.21:44:37.10#ibcon#about to read 3, iclass 36, count 0 2006.285.21:44:37.12#ibcon#read 3, iclass 36, count 0 2006.285.21:44:37.12#ibcon#about to read 4, iclass 36, count 0 2006.285.21:44:37.12#ibcon#read 4, iclass 36, count 0 2006.285.21:44:37.12#ibcon#about to read 5, iclass 36, count 0 2006.285.21:44:37.12#ibcon#read 5, iclass 36, count 0 2006.285.21:44:37.12#ibcon#about to read 6, iclass 36, count 0 2006.285.21:44:37.12#ibcon#read 6, iclass 36, count 0 2006.285.21:44:37.12#ibcon#end of sib2, iclass 36, count 0 2006.285.21:44:37.12#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:44:37.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:44:37.12#ibcon#[27=USB\r\n] 2006.285.21:44:37.12#ibcon#*before write, iclass 36, count 0 2006.285.21:44:37.12#ibcon#enter sib2, iclass 36, count 0 2006.285.21:44:37.12#ibcon#flushed, iclass 36, count 0 2006.285.21:44:37.12#ibcon#about to write, iclass 36, count 0 2006.285.21:44:37.12#ibcon#wrote, iclass 36, count 0 2006.285.21:44:37.12#ibcon#about to read 3, iclass 36, count 0 2006.285.21:44:37.15#ibcon#read 3, iclass 36, count 0 2006.285.21:44:37.15#ibcon#about to read 4, iclass 36, count 0 2006.285.21:44:37.15#ibcon#read 4, iclass 36, count 0 2006.285.21:44:37.15#ibcon#about to read 5, iclass 36, count 0 2006.285.21:44:37.15#ibcon#read 5, iclass 36, count 0 2006.285.21:44:37.15#ibcon#about to read 6, iclass 36, count 0 2006.285.21:44:37.15#ibcon#read 6, iclass 36, count 0 2006.285.21:44:37.15#ibcon#end of sib2, iclass 36, count 0 2006.285.21:44:37.15#ibcon#*after write, iclass 36, count 0 2006.285.21:44:37.15#ibcon#*before return 0, iclass 36, count 0 2006.285.21:44:37.15#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:44:37.15#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.21:44:37.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:44:37.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:44:37.15$vck44/vblo=8,744.99 2006.285.21:44:37.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.21:44:37.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.21:44:37.15#ibcon#ireg 17 cls_cnt 0 2006.285.21:44:37.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:44:37.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:44:37.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:44:37.15#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:44:37.15#ibcon#first serial, iclass 38, count 0 2006.285.21:44:37.15#ibcon#enter sib2, iclass 38, count 0 2006.285.21:44:37.15#ibcon#flushed, iclass 38, count 0 2006.285.21:44:37.15#ibcon#about to write, iclass 38, count 0 2006.285.21:44:37.15#ibcon#wrote, iclass 38, count 0 2006.285.21:44:37.15#ibcon#about to read 3, iclass 38, count 0 2006.285.21:44:37.17#ibcon#read 3, iclass 38, count 0 2006.285.21:44:37.17#ibcon#about to read 4, iclass 38, count 0 2006.285.21:44:37.17#ibcon#read 4, iclass 38, count 0 2006.285.21:44:37.17#ibcon#about to read 5, iclass 38, count 0 2006.285.21:44:37.17#ibcon#read 5, iclass 38, count 0 2006.285.21:44:37.17#ibcon#about to read 6, iclass 38, count 0 2006.285.21:44:37.17#ibcon#read 6, iclass 38, count 0 2006.285.21:44:37.17#ibcon#end of sib2, iclass 38, count 0 2006.285.21:44:37.17#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:44:37.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:44:37.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:44:37.17#ibcon#*before write, iclass 38, count 0 2006.285.21:44:37.17#ibcon#enter sib2, iclass 38, count 0 2006.285.21:44:37.17#ibcon#flushed, iclass 38, count 0 2006.285.21:44:37.17#ibcon#about to write, iclass 38, count 0 2006.285.21:44:37.17#ibcon#wrote, iclass 38, count 0 2006.285.21:44:37.17#ibcon#about to read 3, iclass 38, count 0 2006.285.21:44:37.21#ibcon#read 3, iclass 38, count 0 2006.285.21:44:37.21#ibcon#about to read 4, iclass 38, count 0 2006.285.21:44:37.21#ibcon#read 4, iclass 38, count 0 2006.285.21:44:37.21#ibcon#about to read 5, iclass 38, count 0 2006.285.21:44:37.21#ibcon#read 5, iclass 38, count 0 2006.285.21:44:37.21#ibcon#about to read 6, iclass 38, count 0 2006.285.21:44:37.21#ibcon#read 6, iclass 38, count 0 2006.285.21:44:37.21#ibcon#end of sib2, iclass 38, count 0 2006.285.21:44:37.21#ibcon#*after write, iclass 38, count 0 2006.285.21:44:37.21#ibcon#*before return 0, iclass 38, count 0 2006.285.21:44:37.21#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:44:37.21#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.21:44:37.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:44:37.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:44:37.21$vck44/vb=8,4 2006.285.21:44:37.21#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.21:44:37.21#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.21:44:37.21#ibcon#ireg 11 cls_cnt 2 2006.285.21:44:37.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:44:37.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:44:37.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:44:37.27#ibcon#enter wrdev, iclass 40, count 2 2006.285.21:44:37.27#ibcon#first serial, iclass 40, count 2 2006.285.21:44:37.27#ibcon#enter sib2, iclass 40, count 2 2006.285.21:44:37.27#ibcon#flushed, iclass 40, count 2 2006.285.21:44:37.27#ibcon#about to write, iclass 40, count 2 2006.285.21:44:37.27#ibcon#wrote, iclass 40, count 2 2006.285.21:44:37.27#ibcon#about to read 3, iclass 40, count 2 2006.285.21:44:37.29#ibcon#read 3, iclass 40, count 2 2006.285.21:44:37.29#ibcon#about to read 4, iclass 40, count 2 2006.285.21:44:37.29#ibcon#read 4, iclass 40, count 2 2006.285.21:44:37.29#ibcon#about to read 5, iclass 40, count 2 2006.285.21:44:37.29#ibcon#read 5, iclass 40, count 2 2006.285.21:44:37.29#ibcon#about to read 6, iclass 40, count 2 2006.285.21:44:37.29#ibcon#read 6, iclass 40, count 2 2006.285.21:44:37.29#ibcon#end of sib2, iclass 40, count 2 2006.285.21:44:37.29#ibcon#*mode == 0, iclass 40, count 2 2006.285.21:44:37.29#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.21:44:37.29#ibcon#[27=AT08-04\r\n] 2006.285.21:44:37.29#ibcon#*before write, iclass 40, count 2 2006.285.21:44:37.29#ibcon#enter sib2, iclass 40, count 2 2006.285.21:44:37.29#ibcon#flushed, iclass 40, count 2 2006.285.21:44:37.29#ibcon#about to write, iclass 40, count 2 2006.285.21:44:37.29#ibcon#wrote, iclass 40, count 2 2006.285.21:44:37.29#ibcon#about to read 3, iclass 40, count 2 2006.285.21:44:37.32#ibcon#read 3, iclass 40, count 2 2006.285.21:44:37.32#ibcon#about to read 4, iclass 40, count 2 2006.285.21:44:37.32#ibcon#read 4, iclass 40, count 2 2006.285.21:44:37.32#ibcon#about to read 5, iclass 40, count 2 2006.285.21:44:37.32#ibcon#read 5, iclass 40, count 2 2006.285.21:44:37.32#ibcon#about to read 6, iclass 40, count 2 2006.285.21:44:37.32#ibcon#read 6, iclass 40, count 2 2006.285.21:44:37.32#ibcon#end of sib2, iclass 40, count 2 2006.285.21:44:37.32#ibcon#*after write, iclass 40, count 2 2006.285.21:44:37.32#ibcon#*before return 0, iclass 40, count 2 2006.285.21:44:37.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:44:37.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.21:44:37.32#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.21:44:37.32#ibcon#ireg 7 cls_cnt 0 2006.285.21:44:37.32#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:44:37.44#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:44:37.44#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:44:37.44#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:44:37.44#ibcon#first serial, iclass 40, count 0 2006.285.21:44:37.44#ibcon#enter sib2, iclass 40, count 0 2006.285.21:44:37.44#ibcon#flushed, iclass 40, count 0 2006.285.21:44:37.44#ibcon#about to write, iclass 40, count 0 2006.285.21:44:37.44#ibcon#wrote, iclass 40, count 0 2006.285.21:44:37.44#ibcon#about to read 3, iclass 40, count 0 2006.285.21:44:37.46#ibcon#read 3, iclass 40, count 0 2006.285.21:44:37.46#ibcon#about to read 4, iclass 40, count 0 2006.285.21:44:37.46#ibcon#read 4, iclass 40, count 0 2006.285.21:44:37.46#ibcon#about to read 5, iclass 40, count 0 2006.285.21:44:37.46#ibcon#read 5, iclass 40, count 0 2006.285.21:44:37.46#ibcon#about to read 6, iclass 40, count 0 2006.285.21:44:37.46#ibcon#read 6, iclass 40, count 0 2006.285.21:44:37.46#ibcon#end of sib2, iclass 40, count 0 2006.285.21:44:37.46#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:44:37.46#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:44:37.46#ibcon#[27=USB\r\n] 2006.285.21:44:37.46#ibcon#*before write, iclass 40, count 0 2006.285.21:44:37.46#ibcon#enter sib2, iclass 40, count 0 2006.285.21:44:37.46#ibcon#flushed, iclass 40, count 0 2006.285.21:44:37.46#ibcon#about to write, iclass 40, count 0 2006.285.21:44:37.46#ibcon#wrote, iclass 40, count 0 2006.285.21:44:37.46#ibcon#about to read 3, iclass 40, count 0 2006.285.21:44:37.49#ibcon#read 3, iclass 40, count 0 2006.285.21:44:37.49#ibcon#about to read 4, iclass 40, count 0 2006.285.21:44:37.49#ibcon#read 4, iclass 40, count 0 2006.285.21:44:37.49#ibcon#about to read 5, iclass 40, count 0 2006.285.21:44:37.49#ibcon#read 5, iclass 40, count 0 2006.285.21:44:37.49#ibcon#about to read 6, iclass 40, count 0 2006.285.21:44:37.49#ibcon#read 6, iclass 40, count 0 2006.285.21:44:37.49#ibcon#end of sib2, iclass 40, count 0 2006.285.21:44:37.49#ibcon#*after write, iclass 40, count 0 2006.285.21:44:37.49#ibcon#*before return 0, iclass 40, count 0 2006.285.21:44:37.49#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:44:37.49#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.21:44:37.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:44:37.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:44:37.49$vck44/vabw=wide 2006.285.21:44:37.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.21:44:37.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.21:44:37.54#ibcon#ireg 8 cls_cnt 0 2006.285.21:44:37.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:44:37.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:44:37.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:44:37.54#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:44:37.54#ibcon#first serial, iclass 4, count 0 2006.285.21:44:37.54#ibcon#enter sib2, iclass 4, count 0 2006.285.21:44:37.54#ibcon#flushed, iclass 4, count 0 2006.285.21:44:37.54#ibcon#about to write, iclass 4, count 0 2006.285.21:44:37.54#ibcon#wrote, iclass 4, count 0 2006.285.21:44:37.54#ibcon#about to read 3, iclass 4, count 0 2006.285.21:44:37.56#ibcon#read 3, iclass 4, count 0 2006.285.21:44:37.56#ibcon#about to read 4, iclass 4, count 0 2006.285.21:44:37.56#ibcon#read 4, iclass 4, count 0 2006.285.21:44:37.56#ibcon#about to read 5, iclass 4, count 0 2006.285.21:44:37.56#ibcon#read 5, iclass 4, count 0 2006.285.21:44:37.56#ibcon#about to read 6, iclass 4, count 0 2006.285.21:44:37.56#ibcon#read 6, iclass 4, count 0 2006.285.21:44:37.56#ibcon#end of sib2, iclass 4, count 0 2006.285.21:44:37.56#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:44:37.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:44:37.56#ibcon#[25=BW32\r\n] 2006.285.21:44:37.56#ibcon#*before write, iclass 4, count 0 2006.285.21:44:37.56#ibcon#enter sib2, iclass 4, count 0 2006.285.21:44:37.56#ibcon#flushed, iclass 4, count 0 2006.285.21:44:37.56#ibcon#about to write, iclass 4, count 0 2006.285.21:44:37.56#ibcon#wrote, iclass 4, count 0 2006.285.21:44:37.56#ibcon#about to read 3, iclass 4, count 0 2006.285.21:44:37.59#ibcon#read 3, iclass 4, count 0 2006.285.21:44:37.59#ibcon#about to read 4, iclass 4, count 0 2006.285.21:44:37.59#ibcon#read 4, iclass 4, count 0 2006.285.21:44:37.59#ibcon#about to read 5, iclass 4, count 0 2006.285.21:44:37.59#ibcon#read 5, iclass 4, count 0 2006.285.21:44:37.59#ibcon#about to read 6, iclass 4, count 0 2006.285.21:44:37.59#ibcon#read 6, iclass 4, count 0 2006.285.21:44:37.59#ibcon#end of sib2, iclass 4, count 0 2006.285.21:44:37.59#ibcon#*after write, iclass 4, count 0 2006.285.21:44:37.59#ibcon#*before return 0, iclass 4, count 0 2006.285.21:44:37.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:44:37.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.21:44:37.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:44:37.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:44:37.59$vck44/vbbw=wide 2006.285.21:44:37.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.21:44:37.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.21:44:37.59#ibcon#ireg 8 cls_cnt 0 2006.285.21:44:37.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:44:37.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:44:37.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:44:37.61#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:44:37.61#ibcon#first serial, iclass 6, count 0 2006.285.21:44:37.61#ibcon#enter sib2, iclass 6, count 0 2006.285.21:44:37.61#ibcon#flushed, iclass 6, count 0 2006.285.21:44:37.61#ibcon#about to write, iclass 6, count 0 2006.285.21:44:37.61#ibcon#wrote, iclass 6, count 0 2006.285.21:44:37.61#ibcon#about to read 3, iclass 6, count 0 2006.285.21:44:37.63#ibcon#read 3, iclass 6, count 0 2006.285.21:44:37.63#ibcon#about to read 4, iclass 6, count 0 2006.285.21:44:37.63#ibcon#read 4, iclass 6, count 0 2006.285.21:44:37.63#ibcon#about to read 5, iclass 6, count 0 2006.285.21:44:37.63#ibcon#read 5, iclass 6, count 0 2006.285.21:44:37.63#ibcon#about to read 6, iclass 6, count 0 2006.285.21:44:37.63#ibcon#read 6, iclass 6, count 0 2006.285.21:44:37.63#ibcon#end of sib2, iclass 6, count 0 2006.285.21:44:37.63#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:44:37.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:44:37.63#ibcon#[27=BW32\r\n] 2006.285.21:44:37.63#ibcon#*before write, iclass 6, count 0 2006.285.21:44:37.63#ibcon#enter sib2, iclass 6, count 0 2006.285.21:44:37.63#ibcon#flushed, iclass 6, count 0 2006.285.21:44:37.63#ibcon#about to write, iclass 6, count 0 2006.285.21:44:37.63#ibcon#wrote, iclass 6, count 0 2006.285.21:44:37.63#ibcon#about to read 3, iclass 6, count 0 2006.285.21:44:37.66#ibcon#read 3, iclass 6, count 0 2006.285.21:44:37.66#ibcon#about to read 4, iclass 6, count 0 2006.285.21:44:37.66#ibcon#read 4, iclass 6, count 0 2006.285.21:44:37.66#ibcon#about to read 5, iclass 6, count 0 2006.285.21:44:37.66#ibcon#read 5, iclass 6, count 0 2006.285.21:44:37.66#ibcon#about to read 6, iclass 6, count 0 2006.285.21:44:37.66#ibcon#read 6, iclass 6, count 0 2006.285.21:44:37.66#ibcon#end of sib2, iclass 6, count 0 2006.285.21:44:37.66#ibcon#*after write, iclass 6, count 0 2006.285.21:44:37.66#ibcon#*before return 0, iclass 6, count 0 2006.285.21:44:37.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:44:37.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:44:37.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:44:37.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:44:37.66$setupk4/ifdk4 2006.285.21:44:37.66$ifdk4/lo= 2006.285.21:44:37.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:44:37.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:44:37.66$ifdk4/patch= 2006.285.21:44:37.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:44:37.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:44:37.66$setupk4/!*+20s 2006.285.21:44:38.28#abcon#<5=/15 0.7 1.2 15.101001015.9\r\n> 2006.285.21:44:38.30#abcon#{5=INTERFACE CLEAR} 2006.285.21:44:38.36#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:44:41.14#trakl#Source acquired 2006.285.21:44:41.14#flagr#flagr/antenna,acquired 2006.285.21:44:48.45#abcon#<5=/15 0.7 1.2 15.101001015.9\r\n> 2006.285.21:44:48.47#abcon#{5=INTERFACE CLEAR} 2006.285.21:44:48.53#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:44:51.66$setupk4/"tpicd 2006.285.21:44:51.66$setupk4/echo=off 2006.285.21:44:51.66$setupk4/xlog=off 2006.285.21:44:51.66:!2006.285.21:48:56 2006.285.21:48:56.00:preob 2006.285.21:48:57.14/onsource/TRACKING 2006.285.21:48:57.14:!2006.285.21:49:06 2006.285.21:49:06.00:"tape 2006.285.21:49:06.00:"st=record 2006.285.21:49:06.00:data_valid=on 2006.285.21:49:06.00:midob 2006.285.21:49:06.14/onsource/TRACKING 2006.285.21:49:06.14/wx/15.28,1015.9,100 2006.285.21:49:06.22/cable/+6.5102E-03 2006.285.21:49:07.31/va/01,07,usb,yes,33,35 2006.285.21:49:07.31/va/02,06,usb,yes,33,33 2006.285.21:49:07.31/va/03,07,usb,yes,32,34 2006.285.21:49:07.31/va/04,06,usb,yes,34,35 2006.285.21:49:07.31/va/05,03,usb,yes,33,34 2006.285.21:49:07.31/va/06,04,usb,yes,30,30 2006.285.21:49:07.31/va/07,04,usb,yes,31,31 2006.285.21:49:07.31/va/08,03,usb,yes,31,38 2006.285.21:49:07.54/valo/01,524.99,yes,locked 2006.285.21:49:07.54/valo/02,534.99,yes,locked 2006.285.21:49:07.54/valo/03,564.99,yes,locked 2006.285.21:49:07.54/valo/04,624.99,yes,locked 2006.285.21:49:07.54/valo/05,734.99,yes,locked 2006.285.21:49:07.54/valo/06,814.99,yes,locked 2006.285.21:49:07.54/valo/07,864.99,yes,locked 2006.285.21:49:07.54/valo/08,884.99,yes,locked 2006.285.21:49:08.63/vb/01,04,usb,yes,30,28 2006.285.21:49:08.63/vb/02,05,usb,yes,28,28 2006.285.21:49:08.63/vb/03,04,usb,yes,29,32 2006.285.21:49:08.63/vb/04,05,usb,yes,29,28 2006.285.21:49:08.63/vb/05,04,usb,yes,26,28 2006.285.21:49:08.63/vb/06,03,usb,yes,37,33 2006.285.21:49:08.63/vb/07,04,usb,yes,30,30 2006.285.21:49:08.63/vb/08,04,usb,yes,27,31 2006.285.21:49:08.86/vblo/01,629.99,yes,locked 2006.285.21:49:08.86/vblo/02,634.99,yes,locked 2006.285.21:49:08.86/vblo/03,649.99,yes,locked 2006.285.21:49:08.86/vblo/04,679.99,yes,locked 2006.285.21:49:08.86/vblo/05,709.99,yes,locked 2006.285.21:49:08.86/vblo/06,719.99,yes,locked 2006.285.21:49:08.86/vblo/07,734.99,yes,locked 2006.285.21:49:08.86/vblo/08,744.99,yes,locked 2006.285.21:49:09.01/vabw/8 2006.285.21:49:09.16/vbbw/8 2006.285.21:49:09.25/xfe/off,on,12.0 2006.285.21:49:09.62/ifatt/23,28,28,28 2006.285.21:49:10.07/fmout-gps/S +2.69E-07 2006.285.21:49:10.09:!2006.285.21:49:56 2006.285.21:49:56.01:data_valid=off 2006.285.21:49:56.01:"et 2006.285.21:49:56.01:!+3s 2006.285.21:49:59.02:"tape 2006.285.21:49:59.02:postob 2006.285.21:49:59.23/cable/+6.5112E-03 2006.285.21:49:59.23/wx/15.31,1015.9,100 2006.285.21:50:00.07/fmout-gps/S +2.68E-07 2006.285.21:50:00.07:scan_name=285-2152,jd0610,260 2006.285.21:50:00.07:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.285.21:50:01.14#flagr#flagr/antenna,new-source 2006.285.21:50:01.14:checkk5 2006.285.21:50:01.69/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:50:02.22/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:50:02.60/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:50:03.10/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:50:03.72/chk_obsdata//k5ts1/T2852149??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.21:50:04.57/chk_obsdata//k5ts2/T2852149??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.21:50:05.06/chk_obsdata//k5ts3/T2852149??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.21:50:05.45/chk_obsdata//k5ts4/T2852149??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.21:50:06.35/k5log//k5ts1_log_newline 2006.285.21:50:07.37/k5log//k5ts2_log_newline 2006.285.21:50:08.09/k5log//k5ts3_log_newline 2006.285.21:50:08.84/k5log//k5ts4_log_newline 2006.285.21:50:08.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:50:08.86:setupk4=1 2006.285.21:50:08.86$setupk4/echo=on 2006.285.21:50:08.86$setupk4/pcalon 2006.285.21:50:08.86$pcalon/"no phase cal control is implemented here 2006.285.21:50:08.86$setupk4/"tpicd=stop 2006.285.21:50:08.86$setupk4/"rec=synch_on 2006.285.21:50:08.86$setupk4/"rec_mode=128 2006.285.21:50:08.86$setupk4/!* 2006.285.21:50:08.86$setupk4/recpk4 2006.285.21:50:08.86$recpk4/recpatch= 2006.285.21:50:08.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:50:08.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:50:08.87$setupk4/vck44 2006.285.21:50:08.87$vck44/valo=1,524.99 2006.285.21:50:08.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.21:50:08.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.21:50:08.87#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:08.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:50:08.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:50:08.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:50:08.87#ibcon#enter wrdev, iclass 37, count 0 2006.285.21:50:08.87#ibcon#first serial, iclass 37, count 0 2006.285.21:50:08.87#ibcon#enter sib2, iclass 37, count 0 2006.285.21:50:08.87#ibcon#flushed, iclass 37, count 0 2006.285.21:50:08.87#ibcon#about to write, iclass 37, count 0 2006.285.21:50:08.87#ibcon#wrote, iclass 37, count 0 2006.285.21:50:08.87#ibcon#about to read 3, iclass 37, count 0 2006.285.21:50:08.89#ibcon#read 3, iclass 37, count 0 2006.285.21:50:08.89#ibcon#about to read 4, iclass 37, count 0 2006.285.21:50:08.89#ibcon#read 4, iclass 37, count 0 2006.285.21:50:08.89#ibcon#about to read 5, iclass 37, count 0 2006.285.21:50:08.89#ibcon#read 5, iclass 37, count 0 2006.285.21:50:08.89#ibcon#about to read 6, iclass 37, count 0 2006.285.21:50:08.89#ibcon#read 6, iclass 37, count 0 2006.285.21:50:08.89#ibcon#end of sib2, iclass 37, count 0 2006.285.21:50:08.89#ibcon#*mode == 0, iclass 37, count 0 2006.285.21:50:08.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.21:50:08.89#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:50:08.89#ibcon#*before write, iclass 37, count 0 2006.285.21:50:08.89#ibcon#enter sib2, iclass 37, count 0 2006.285.21:50:08.89#ibcon#flushed, iclass 37, count 0 2006.285.21:50:08.89#ibcon#about to write, iclass 37, count 0 2006.285.21:50:08.89#ibcon#wrote, iclass 37, count 0 2006.285.21:50:08.89#ibcon#about to read 3, iclass 37, count 0 2006.285.21:50:08.94#ibcon#read 3, iclass 37, count 0 2006.285.21:50:08.94#ibcon#about to read 4, iclass 37, count 0 2006.285.21:50:08.94#ibcon#read 4, iclass 37, count 0 2006.285.21:50:08.94#ibcon#about to read 5, iclass 37, count 0 2006.285.21:50:08.94#ibcon#read 5, iclass 37, count 0 2006.285.21:50:08.94#ibcon#about to read 6, iclass 37, count 0 2006.285.21:50:08.94#ibcon#read 6, iclass 37, count 0 2006.285.21:50:08.94#ibcon#end of sib2, iclass 37, count 0 2006.285.21:50:08.94#ibcon#*after write, iclass 37, count 0 2006.285.21:50:08.94#ibcon#*before return 0, iclass 37, count 0 2006.285.21:50:08.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:50:08.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:50:08.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.21:50:08.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.21:50:08.94$vck44/va=1,7 2006.285.21:50:08.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.21:50:08.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.21:50:08.94#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:08.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:50:08.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:50:08.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:50:08.94#ibcon#enter wrdev, iclass 39, count 2 2006.285.21:50:08.94#ibcon#first serial, iclass 39, count 2 2006.285.21:50:08.94#ibcon#enter sib2, iclass 39, count 2 2006.285.21:50:08.94#ibcon#flushed, iclass 39, count 2 2006.285.21:50:08.94#ibcon#about to write, iclass 39, count 2 2006.285.21:50:08.94#ibcon#wrote, iclass 39, count 2 2006.285.21:50:08.94#ibcon#about to read 3, iclass 39, count 2 2006.285.21:50:08.96#ibcon#read 3, iclass 39, count 2 2006.285.21:50:08.96#ibcon#about to read 4, iclass 39, count 2 2006.285.21:50:08.96#ibcon#read 4, iclass 39, count 2 2006.285.21:50:08.96#ibcon#about to read 5, iclass 39, count 2 2006.285.21:50:08.96#ibcon#read 5, iclass 39, count 2 2006.285.21:50:08.96#ibcon#about to read 6, iclass 39, count 2 2006.285.21:50:08.96#ibcon#read 6, iclass 39, count 2 2006.285.21:50:08.96#ibcon#end of sib2, iclass 39, count 2 2006.285.21:50:08.96#ibcon#*mode == 0, iclass 39, count 2 2006.285.21:50:08.96#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.21:50:08.96#ibcon#[25=AT01-07\r\n] 2006.285.21:50:08.96#ibcon#*before write, iclass 39, count 2 2006.285.21:50:08.96#ibcon#enter sib2, iclass 39, count 2 2006.285.21:50:08.96#ibcon#flushed, iclass 39, count 2 2006.285.21:50:08.96#ibcon#about to write, iclass 39, count 2 2006.285.21:50:08.96#ibcon#wrote, iclass 39, count 2 2006.285.21:50:08.96#ibcon#about to read 3, iclass 39, count 2 2006.285.21:50:08.99#ibcon#read 3, iclass 39, count 2 2006.285.21:50:08.99#ibcon#about to read 4, iclass 39, count 2 2006.285.21:50:08.99#ibcon#read 4, iclass 39, count 2 2006.285.21:50:08.99#ibcon#about to read 5, iclass 39, count 2 2006.285.21:50:08.99#ibcon#read 5, iclass 39, count 2 2006.285.21:50:08.99#ibcon#about to read 6, iclass 39, count 2 2006.285.21:50:08.99#ibcon#read 6, iclass 39, count 2 2006.285.21:50:08.99#ibcon#end of sib2, iclass 39, count 2 2006.285.21:50:08.99#ibcon#*after write, iclass 39, count 2 2006.285.21:50:08.99#ibcon#*before return 0, iclass 39, count 2 2006.285.21:50:08.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:50:08.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:50:08.99#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.21:50:08.99#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:08.99#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:50:09.11#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:50:09.11#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:50:09.11#ibcon#enter wrdev, iclass 39, count 0 2006.285.21:50:09.11#ibcon#first serial, iclass 39, count 0 2006.285.21:50:09.11#ibcon#enter sib2, iclass 39, count 0 2006.285.21:50:09.11#ibcon#flushed, iclass 39, count 0 2006.285.21:50:09.11#ibcon#about to write, iclass 39, count 0 2006.285.21:50:09.11#ibcon#wrote, iclass 39, count 0 2006.285.21:50:09.11#ibcon#about to read 3, iclass 39, count 0 2006.285.21:50:09.13#ibcon#read 3, iclass 39, count 0 2006.285.21:50:09.13#ibcon#about to read 4, iclass 39, count 0 2006.285.21:50:09.13#ibcon#read 4, iclass 39, count 0 2006.285.21:50:09.13#ibcon#about to read 5, iclass 39, count 0 2006.285.21:50:09.13#ibcon#read 5, iclass 39, count 0 2006.285.21:50:09.13#ibcon#about to read 6, iclass 39, count 0 2006.285.21:50:09.13#ibcon#read 6, iclass 39, count 0 2006.285.21:50:09.13#ibcon#end of sib2, iclass 39, count 0 2006.285.21:50:09.13#ibcon#*mode == 0, iclass 39, count 0 2006.285.21:50:09.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.21:50:09.13#ibcon#[25=USB\r\n] 2006.285.21:50:09.13#ibcon#*before write, iclass 39, count 0 2006.285.21:50:09.13#ibcon#enter sib2, iclass 39, count 0 2006.285.21:50:09.13#ibcon#flushed, iclass 39, count 0 2006.285.21:50:09.13#ibcon#about to write, iclass 39, count 0 2006.285.21:50:09.13#ibcon#wrote, iclass 39, count 0 2006.285.21:50:09.13#ibcon#about to read 3, iclass 39, count 0 2006.285.21:50:09.16#ibcon#read 3, iclass 39, count 0 2006.285.21:50:09.16#ibcon#about to read 4, iclass 39, count 0 2006.285.21:50:09.16#ibcon#read 4, iclass 39, count 0 2006.285.21:50:09.16#ibcon#about to read 5, iclass 39, count 0 2006.285.21:50:09.16#ibcon#read 5, iclass 39, count 0 2006.285.21:50:09.16#ibcon#about to read 6, iclass 39, count 0 2006.285.21:50:09.16#ibcon#read 6, iclass 39, count 0 2006.285.21:50:09.16#ibcon#end of sib2, iclass 39, count 0 2006.285.21:50:09.16#ibcon#*after write, iclass 39, count 0 2006.285.21:50:09.16#ibcon#*before return 0, iclass 39, count 0 2006.285.21:50:09.16#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:50:09.16#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:50:09.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.21:50:09.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.21:50:09.16$vck44/valo=2,534.99 2006.285.21:50:09.16#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.21:50:09.16#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.21:50:09.16#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:09.16#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:50:09.16#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:50:09.16#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:50:09.16#ibcon#enter wrdev, iclass 3, count 0 2006.285.21:50:09.16#ibcon#first serial, iclass 3, count 0 2006.285.21:50:09.16#ibcon#enter sib2, iclass 3, count 0 2006.285.21:50:09.16#ibcon#flushed, iclass 3, count 0 2006.285.21:50:09.16#ibcon#about to write, iclass 3, count 0 2006.285.21:50:09.16#ibcon#wrote, iclass 3, count 0 2006.285.21:50:09.16#ibcon#about to read 3, iclass 3, count 0 2006.285.21:50:09.18#ibcon#read 3, iclass 3, count 0 2006.285.21:50:09.18#ibcon#about to read 4, iclass 3, count 0 2006.285.21:50:09.18#ibcon#read 4, iclass 3, count 0 2006.285.21:50:09.18#ibcon#about to read 5, iclass 3, count 0 2006.285.21:50:09.18#ibcon#read 5, iclass 3, count 0 2006.285.21:50:09.18#ibcon#about to read 6, iclass 3, count 0 2006.285.21:50:09.18#ibcon#read 6, iclass 3, count 0 2006.285.21:50:09.18#ibcon#end of sib2, iclass 3, count 0 2006.285.21:50:09.18#ibcon#*mode == 0, iclass 3, count 0 2006.285.21:50:09.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.21:50:09.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:50:09.18#ibcon#*before write, iclass 3, count 0 2006.285.21:50:09.18#ibcon#enter sib2, iclass 3, count 0 2006.285.21:50:09.18#ibcon#flushed, iclass 3, count 0 2006.285.21:50:09.18#ibcon#about to write, iclass 3, count 0 2006.285.21:50:09.18#ibcon#wrote, iclass 3, count 0 2006.285.21:50:09.18#ibcon#about to read 3, iclass 3, count 0 2006.285.21:50:09.22#ibcon#read 3, iclass 3, count 0 2006.285.21:50:09.22#ibcon#about to read 4, iclass 3, count 0 2006.285.21:50:09.22#ibcon#read 4, iclass 3, count 0 2006.285.21:50:09.22#ibcon#about to read 5, iclass 3, count 0 2006.285.21:50:09.22#ibcon#read 5, iclass 3, count 0 2006.285.21:50:09.22#ibcon#about to read 6, iclass 3, count 0 2006.285.21:50:09.22#ibcon#read 6, iclass 3, count 0 2006.285.21:50:09.22#ibcon#end of sib2, iclass 3, count 0 2006.285.21:50:09.22#ibcon#*after write, iclass 3, count 0 2006.285.21:50:09.22#ibcon#*before return 0, iclass 3, count 0 2006.285.21:50:09.22#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:50:09.22#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:50:09.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.21:50:09.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.21:50:09.22$vck44/va=2,6 2006.285.21:50:09.22#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.21:50:09.22#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.21:50:09.22#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:09.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:50:09.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:50:09.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:50:09.28#ibcon#enter wrdev, iclass 5, count 2 2006.285.21:50:09.28#ibcon#first serial, iclass 5, count 2 2006.285.21:50:09.28#ibcon#enter sib2, iclass 5, count 2 2006.285.21:50:09.28#ibcon#flushed, iclass 5, count 2 2006.285.21:50:09.28#ibcon#about to write, iclass 5, count 2 2006.285.21:50:09.28#ibcon#wrote, iclass 5, count 2 2006.285.21:50:09.28#ibcon#about to read 3, iclass 5, count 2 2006.285.21:50:09.30#ibcon#read 3, iclass 5, count 2 2006.285.21:50:09.30#ibcon#about to read 4, iclass 5, count 2 2006.285.21:50:09.30#ibcon#read 4, iclass 5, count 2 2006.285.21:50:09.30#ibcon#about to read 5, iclass 5, count 2 2006.285.21:50:09.30#ibcon#read 5, iclass 5, count 2 2006.285.21:50:09.30#ibcon#about to read 6, iclass 5, count 2 2006.285.21:50:09.30#ibcon#read 6, iclass 5, count 2 2006.285.21:50:09.30#ibcon#end of sib2, iclass 5, count 2 2006.285.21:50:09.30#ibcon#*mode == 0, iclass 5, count 2 2006.285.21:50:09.30#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.21:50:09.30#ibcon#[25=AT02-06\r\n] 2006.285.21:50:09.30#ibcon#*before write, iclass 5, count 2 2006.285.21:50:09.30#ibcon#enter sib2, iclass 5, count 2 2006.285.21:50:09.30#ibcon#flushed, iclass 5, count 2 2006.285.21:50:09.30#ibcon#about to write, iclass 5, count 2 2006.285.21:50:09.30#ibcon#wrote, iclass 5, count 2 2006.285.21:50:09.30#ibcon#about to read 3, iclass 5, count 2 2006.285.21:50:09.33#ibcon#read 3, iclass 5, count 2 2006.285.21:50:09.33#ibcon#about to read 4, iclass 5, count 2 2006.285.21:50:09.33#ibcon#read 4, iclass 5, count 2 2006.285.21:50:09.33#ibcon#about to read 5, iclass 5, count 2 2006.285.21:50:09.33#ibcon#read 5, iclass 5, count 2 2006.285.21:50:09.33#ibcon#about to read 6, iclass 5, count 2 2006.285.21:50:09.33#ibcon#read 6, iclass 5, count 2 2006.285.21:50:09.33#ibcon#end of sib2, iclass 5, count 2 2006.285.21:50:09.33#ibcon#*after write, iclass 5, count 2 2006.285.21:50:09.33#ibcon#*before return 0, iclass 5, count 2 2006.285.21:50:09.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:50:09.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:50:09.33#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.21:50:09.33#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:09.33#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:50:09.45#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:50:09.45#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:50:09.45#ibcon#enter wrdev, iclass 5, count 0 2006.285.21:50:09.45#ibcon#first serial, iclass 5, count 0 2006.285.21:50:09.45#ibcon#enter sib2, iclass 5, count 0 2006.285.21:50:09.45#ibcon#flushed, iclass 5, count 0 2006.285.21:50:09.45#ibcon#about to write, iclass 5, count 0 2006.285.21:50:09.45#ibcon#wrote, iclass 5, count 0 2006.285.21:50:09.45#ibcon#about to read 3, iclass 5, count 0 2006.285.21:50:09.47#ibcon#read 3, iclass 5, count 0 2006.285.21:50:09.47#ibcon#about to read 4, iclass 5, count 0 2006.285.21:50:09.47#ibcon#read 4, iclass 5, count 0 2006.285.21:50:09.47#ibcon#about to read 5, iclass 5, count 0 2006.285.21:50:09.47#ibcon#read 5, iclass 5, count 0 2006.285.21:50:09.47#ibcon#about to read 6, iclass 5, count 0 2006.285.21:50:09.47#ibcon#read 6, iclass 5, count 0 2006.285.21:50:09.47#ibcon#end of sib2, iclass 5, count 0 2006.285.21:50:09.47#ibcon#*mode == 0, iclass 5, count 0 2006.285.21:50:09.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.21:50:09.47#ibcon#[25=USB\r\n] 2006.285.21:50:09.47#ibcon#*before write, iclass 5, count 0 2006.285.21:50:09.47#ibcon#enter sib2, iclass 5, count 0 2006.285.21:50:09.47#ibcon#flushed, iclass 5, count 0 2006.285.21:50:09.47#ibcon#about to write, iclass 5, count 0 2006.285.21:50:09.47#ibcon#wrote, iclass 5, count 0 2006.285.21:50:09.47#ibcon#about to read 3, iclass 5, count 0 2006.285.21:50:09.50#ibcon#read 3, iclass 5, count 0 2006.285.21:50:09.50#ibcon#about to read 4, iclass 5, count 0 2006.285.21:50:09.50#ibcon#read 4, iclass 5, count 0 2006.285.21:50:09.50#ibcon#about to read 5, iclass 5, count 0 2006.285.21:50:09.50#ibcon#read 5, iclass 5, count 0 2006.285.21:50:09.50#ibcon#about to read 6, iclass 5, count 0 2006.285.21:50:09.50#ibcon#read 6, iclass 5, count 0 2006.285.21:50:09.50#ibcon#end of sib2, iclass 5, count 0 2006.285.21:50:09.50#ibcon#*after write, iclass 5, count 0 2006.285.21:50:09.50#ibcon#*before return 0, iclass 5, count 0 2006.285.21:50:09.50#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:50:09.50#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:50:09.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.21:50:09.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.21:50:09.50$vck44/valo=3,564.99 2006.285.21:50:09.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.21:50:09.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.21:50:09.50#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:09.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:50:09.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:50:09.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:50:09.50#ibcon#enter wrdev, iclass 7, count 0 2006.285.21:50:09.50#ibcon#first serial, iclass 7, count 0 2006.285.21:50:09.50#ibcon#enter sib2, iclass 7, count 0 2006.285.21:50:09.50#ibcon#flushed, iclass 7, count 0 2006.285.21:50:09.50#ibcon#about to write, iclass 7, count 0 2006.285.21:50:09.50#ibcon#wrote, iclass 7, count 0 2006.285.21:50:09.50#ibcon#about to read 3, iclass 7, count 0 2006.285.21:50:09.52#ibcon#read 3, iclass 7, count 0 2006.285.21:50:09.52#ibcon#about to read 4, iclass 7, count 0 2006.285.21:50:09.52#ibcon#read 4, iclass 7, count 0 2006.285.21:50:09.52#ibcon#about to read 5, iclass 7, count 0 2006.285.21:50:09.52#ibcon#read 5, iclass 7, count 0 2006.285.21:50:09.52#ibcon#about to read 6, iclass 7, count 0 2006.285.21:50:09.52#ibcon#read 6, iclass 7, count 0 2006.285.21:50:09.52#ibcon#end of sib2, iclass 7, count 0 2006.285.21:50:09.52#ibcon#*mode == 0, iclass 7, count 0 2006.285.21:50:09.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.21:50:09.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:50:09.52#ibcon#*before write, iclass 7, count 0 2006.285.21:50:09.52#ibcon#enter sib2, iclass 7, count 0 2006.285.21:50:09.52#ibcon#flushed, iclass 7, count 0 2006.285.21:50:09.52#ibcon#about to write, iclass 7, count 0 2006.285.21:50:09.52#ibcon#wrote, iclass 7, count 0 2006.285.21:50:09.52#ibcon#about to read 3, iclass 7, count 0 2006.285.21:50:09.56#ibcon#read 3, iclass 7, count 0 2006.285.21:50:09.56#ibcon#about to read 4, iclass 7, count 0 2006.285.21:50:09.56#ibcon#read 4, iclass 7, count 0 2006.285.21:50:09.56#ibcon#about to read 5, iclass 7, count 0 2006.285.21:50:09.56#ibcon#read 5, iclass 7, count 0 2006.285.21:50:09.56#ibcon#about to read 6, iclass 7, count 0 2006.285.21:50:09.56#ibcon#read 6, iclass 7, count 0 2006.285.21:50:09.56#ibcon#end of sib2, iclass 7, count 0 2006.285.21:50:09.56#ibcon#*after write, iclass 7, count 0 2006.285.21:50:09.56#ibcon#*before return 0, iclass 7, count 0 2006.285.21:50:09.56#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:50:09.56#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:50:09.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.21:50:09.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.21:50:09.57$vck44/va=3,7 2006.285.21:50:09.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.21:50:09.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.21:50:09.57#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:09.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:50:09.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:50:09.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:50:09.62#ibcon#enter wrdev, iclass 11, count 2 2006.285.21:50:09.62#ibcon#first serial, iclass 11, count 2 2006.285.21:50:09.62#ibcon#enter sib2, iclass 11, count 2 2006.285.21:50:09.62#ibcon#flushed, iclass 11, count 2 2006.285.21:50:09.62#ibcon#about to write, iclass 11, count 2 2006.285.21:50:09.62#ibcon#wrote, iclass 11, count 2 2006.285.21:50:09.62#ibcon#about to read 3, iclass 11, count 2 2006.285.21:50:09.64#ibcon#read 3, iclass 11, count 2 2006.285.21:50:09.64#ibcon#about to read 4, iclass 11, count 2 2006.285.21:50:09.64#ibcon#read 4, iclass 11, count 2 2006.285.21:50:09.64#ibcon#about to read 5, iclass 11, count 2 2006.285.21:50:09.64#ibcon#read 5, iclass 11, count 2 2006.285.21:50:09.64#ibcon#about to read 6, iclass 11, count 2 2006.285.21:50:09.64#ibcon#read 6, iclass 11, count 2 2006.285.21:50:09.64#ibcon#end of sib2, iclass 11, count 2 2006.285.21:50:09.64#ibcon#*mode == 0, iclass 11, count 2 2006.285.21:50:09.64#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.21:50:09.64#ibcon#[25=AT03-07\r\n] 2006.285.21:50:09.64#ibcon#*before write, iclass 11, count 2 2006.285.21:50:09.64#ibcon#enter sib2, iclass 11, count 2 2006.285.21:50:09.64#ibcon#flushed, iclass 11, count 2 2006.285.21:50:09.64#ibcon#about to write, iclass 11, count 2 2006.285.21:50:09.64#ibcon#wrote, iclass 11, count 2 2006.285.21:50:09.64#ibcon#about to read 3, iclass 11, count 2 2006.285.21:50:09.67#ibcon#read 3, iclass 11, count 2 2006.285.21:50:09.67#ibcon#about to read 4, iclass 11, count 2 2006.285.21:50:09.67#ibcon#read 4, iclass 11, count 2 2006.285.21:50:09.67#ibcon#about to read 5, iclass 11, count 2 2006.285.21:50:09.67#ibcon#read 5, iclass 11, count 2 2006.285.21:50:09.67#ibcon#about to read 6, iclass 11, count 2 2006.285.21:50:09.67#ibcon#read 6, iclass 11, count 2 2006.285.21:50:09.67#ibcon#end of sib2, iclass 11, count 2 2006.285.21:50:09.67#ibcon#*after write, iclass 11, count 2 2006.285.21:50:09.67#ibcon#*before return 0, iclass 11, count 2 2006.285.21:50:09.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:50:09.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:50:09.67#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.21:50:09.67#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:09.67#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:50:09.79#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:50:10.03#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:50:10.03#ibcon#enter wrdev, iclass 11, count 0 2006.285.21:50:10.03#ibcon#first serial, iclass 11, count 0 2006.285.21:50:10.03#ibcon#enter sib2, iclass 11, count 0 2006.285.21:50:10.03#ibcon#flushed, iclass 11, count 0 2006.285.21:50:10.03#ibcon#about to write, iclass 11, count 0 2006.285.21:50:10.03#ibcon#wrote, iclass 11, count 0 2006.285.21:50:10.03#ibcon#about to read 3, iclass 11, count 0 2006.285.21:50:10.04#ibcon#read 3, iclass 11, count 0 2006.285.21:50:10.04#ibcon#about to read 4, iclass 11, count 0 2006.285.21:50:10.04#ibcon#read 4, iclass 11, count 0 2006.285.21:50:10.04#ibcon#about to read 5, iclass 11, count 0 2006.285.21:50:10.04#ibcon#read 5, iclass 11, count 0 2006.285.21:50:10.04#ibcon#about to read 6, iclass 11, count 0 2006.285.21:50:10.04#ibcon#read 6, iclass 11, count 0 2006.285.21:50:10.04#ibcon#end of sib2, iclass 11, count 0 2006.285.21:50:10.04#ibcon#*mode == 0, iclass 11, count 0 2006.285.21:50:10.04#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.21:50:10.04#ibcon#[25=USB\r\n] 2006.285.21:50:10.04#ibcon#*before write, iclass 11, count 0 2006.285.21:50:10.04#ibcon#enter sib2, iclass 11, count 0 2006.285.21:50:10.04#ibcon#flushed, iclass 11, count 0 2006.285.21:50:10.04#ibcon#about to write, iclass 11, count 0 2006.285.21:50:10.04#ibcon#wrote, iclass 11, count 0 2006.285.21:50:10.04#ibcon#about to read 3, iclass 11, count 0 2006.285.21:50:10.07#ibcon#read 3, iclass 11, count 0 2006.285.21:50:10.07#ibcon#about to read 4, iclass 11, count 0 2006.285.21:50:10.07#ibcon#read 4, iclass 11, count 0 2006.285.21:50:10.07#ibcon#about to read 5, iclass 11, count 0 2006.285.21:50:10.07#ibcon#read 5, iclass 11, count 0 2006.285.21:50:10.07#ibcon#about to read 6, iclass 11, count 0 2006.285.21:50:10.07#ibcon#read 6, iclass 11, count 0 2006.285.21:50:10.07#ibcon#end of sib2, iclass 11, count 0 2006.285.21:50:10.07#ibcon#*after write, iclass 11, count 0 2006.285.21:50:10.07#ibcon#*before return 0, iclass 11, count 0 2006.285.21:50:10.07#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:50:10.07#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:50:10.07#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.21:50:10.07#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.21:50:10.07$vck44/valo=4,624.99 2006.285.21:50:10.07#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.21:50:10.07#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.21:50:10.07#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:10.07#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:50:10.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:50:10.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:50:10.07#ibcon#enter wrdev, iclass 13, count 0 2006.285.21:50:10.07#ibcon#first serial, iclass 13, count 0 2006.285.21:50:10.07#ibcon#enter sib2, iclass 13, count 0 2006.285.21:50:10.07#ibcon#flushed, iclass 13, count 0 2006.285.21:50:10.07#ibcon#about to write, iclass 13, count 0 2006.285.21:50:10.07#ibcon#wrote, iclass 13, count 0 2006.285.21:50:10.07#ibcon#about to read 3, iclass 13, count 0 2006.285.21:50:10.09#ibcon#read 3, iclass 13, count 0 2006.285.21:50:10.09#ibcon#about to read 4, iclass 13, count 0 2006.285.21:50:10.09#ibcon#read 4, iclass 13, count 0 2006.285.21:50:10.09#ibcon#about to read 5, iclass 13, count 0 2006.285.21:50:10.09#ibcon#read 5, iclass 13, count 0 2006.285.21:50:10.09#ibcon#about to read 6, iclass 13, count 0 2006.285.21:50:10.09#ibcon#read 6, iclass 13, count 0 2006.285.21:50:10.09#ibcon#end of sib2, iclass 13, count 0 2006.285.21:50:10.09#ibcon#*mode == 0, iclass 13, count 0 2006.285.21:50:10.09#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.21:50:10.09#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:50:10.09#ibcon#*before write, iclass 13, count 0 2006.285.21:50:10.09#ibcon#enter sib2, iclass 13, count 0 2006.285.21:50:10.09#ibcon#flushed, iclass 13, count 0 2006.285.21:50:10.09#ibcon#about to write, iclass 13, count 0 2006.285.21:50:10.09#ibcon#wrote, iclass 13, count 0 2006.285.21:50:10.09#ibcon#about to read 3, iclass 13, count 0 2006.285.21:50:10.13#ibcon#read 3, iclass 13, count 0 2006.285.21:50:10.13#ibcon#about to read 4, iclass 13, count 0 2006.285.21:50:10.13#ibcon#read 4, iclass 13, count 0 2006.285.21:50:10.13#ibcon#about to read 5, iclass 13, count 0 2006.285.21:50:10.13#ibcon#read 5, iclass 13, count 0 2006.285.21:50:10.13#ibcon#about to read 6, iclass 13, count 0 2006.285.21:50:10.13#ibcon#read 6, iclass 13, count 0 2006.285.21:50:10.13#ibcon#end of sib2, iclass 13, count 0 2006.285.21:50:10.13#ibcon#*after write, iclass 13, count 0 2006.285.21:50:10.13#ibcon#*before return 0, iclass 13, count 0 2006.285.21:50:10.13#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:50:10.13#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.21:50:10.13#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.21:50:10.13#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.21:50:10.13$vck44/va=4,6 2006.285.21:50:10.13#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.21:50:10.13#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.21:50:10.13#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:10.13#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:50:10.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:50:10.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:50:10.19#ibcon#enter wrdev, iclass 15, count 2 2006.285.21:50:10.19#ibcon#first serial, iclass 15, count 2 2006.285.21:50:10.19#ibcon#enter sib2, iclass 15, count 2 2006.285.21:50:10.19#ibcon#flushed, iclass 15, count 2 2006.285.21:50:10.19#ibcon#about to write, iclass 15, count 2 2006.285.21:50:10.19#ibcon#wrote, iclass 15, count 2 2006.285.21:50:10.19#ibcon#about to read 3, iclass 15, count 2 2006.285.21:50:10.21#ibcon#read 3, iclass 15, count 2 2006.285.21:50:10.21#ibcon#about to read 4, iclass 15, count 2 2006.285.21:50:10.21#ibcon#read 4, iclass 15, count 2 2006.285.21:50:10.21#ibcon#about to read 5, iclass 15, count 2 2006.285.21:50:10.21#ibcon#read 5, iclass 15, count 2 2006.285.21:50:10.21#ibcon#about to read 6, iclass 15, count 2 2006.285.21:50:10.21#ibcon#read 6, iclass 15, count 2 2006.285.21:50:10.21#ibcon#end of sib2, iclass 15, count 2 2006.285.21:50:10.21#ibcon#*mode == 0, iclass 15, count 2 2006.285.21:50:10.21#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.21:50:10.21#ibcon#[25=AT04-06\r\n] 2006.285.21:50:10.21#ibcon#*before write, iclass 15, count 2 2006.285.21:50:10.21#ibcon#enter sib2, iclass 15, count 2 2006.285.21:50:10.21#ibcon#flushed, iclass 15, count 2 2006.285.21:50:10.21#ibcon#about to write, iclass 15, count 2 2006.285.21:50:10.21#ibcon#wrote, iclass 15, count 2 2006.285.21:50:10.21#ibcon#about to read 3, iclass 15, count 2 2006.285.21:50:10.24#ibcon#read 3, iclass 15, count 2 2006.285.21:50:10.24#ibcon#about to read 4, iclass 15, count 2 2006.285.21:50:10.24#ibcon#read 4, iclass 15, count 2 2006.285.21:50:10.24#ibcon#about to read 5, iclass 15, count 2 2006.285.21:50:10.24#ibcon#read 5, iclass 15, count 2 2006.285.21:50:10.24#ibcon#about to read 6, iclass 15, count 2 2006.285.21:50:10.24#ibcon#read 6, iclass 15, count 2 2006.285.21:50:10.24#ibcon#end of sib2, iclass 15, count 2 2006.285.21:50:10.24#ibcon#*after write, iclass 15, count 2 2006.285.21:50:10.24#ibcon#*before return 0, iclass 15, count 2 2006.285.21:50:10.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:50:10.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.21:50:10.24#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.21:50:10.24#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:10.24#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:50:10.36#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:50:10.36#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:50:10.36#ibcon#enter wrdev, iclass 15, count 0 2006.285.21:50:10.36#ibcon#first serial, iclass 15, count 0 2006.285.21:50:10.36#ibcon#enter sib2, iclass 15, count 0 2006.285.21:50:10.36#ibcon#flushed, iclass 15, count 0 2006.285.21:50:10.36#ibcon#about to write, iclass 15, count 0 2006.285.21:50:10.36#ibcon#wrote, iclass 15, count 0 2006.285.21:50:10.36#ibcon#about to read 3, iclass 15, count 0 2006.285.21:50:10.38#ibcon#read 3, iclass 15, count 0 2006.285.21:50:10.38#ibcon#about to read 4, iclass 15, count 0 2006.285.21:50:10.38#ibcon#read 4, iclass 15, count 0 2006.285.21:50:10.38#ibcon#about to read 5, iclass 15, count 0 2006.285.21:50:10.38#ibcon#read 5, iclass 15, count 0 2006.285.21:50:10.38#ibcon#about to read 6, iclass 15, count 0 2006.285.21:50:10.38#ibcon#read 6, iclass 15, count 0 2006.285.21:50:10.38#ibcon#end of sib2, iclass 15, count 0 2006.285.21:50:10.38#ibcon#*mode == 0, iclass 15, count 0 2006.285.21:50:10.38#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.21:50:10.38#ibcon#[25=USB\r\n] 2006.285.21:50:10.38#ibcon#*before write, iclass 15, count 0 2006.285.21:50:10.38#ibcon#enter sib2, iclass 15, count 0 2006.285.21:50:10.38#ibcon#flushed, iclass 15, count 0 2006.285.21:50:10.38#ibcon#about to write, iclass 15, count 0 2006.285.21:50:10.38#ibcon#wrote, iclass 15, count 0 2006.285.21:50:10.38#ibcon#about to read 3, iclass 15, count 0 2006.285.21:50:10.41#ibcon#read 3, iclass 15, count 0 2006.285.21:50:10.41#ibcon#about to read 4, iclass 15, count 0 2006.285.21:50:10.41#ibcon#read 4, iclass 15, count 0 2006.285.21:50:10.41#ibcon#about to read 5, iclass 15, count 0 2006.285.21:50:10.41#ibcon#read 5, iclass 15, count 0 2006.285.21:50:10.41#ibcon#about to read 6, iclass 15, count 0 2006.285.21:50:10.41#ibcon#read 6, iclass 15, count 0 2006.285.21:50:10.41#ibcon#end of sib2, iclass 15, count 0 2006.285.21:50:10.41#ibcon#*after write, iclass 15, count 0 2006.285.21:50:10.41#ibcon#*before return 0, iclass 15, count 0 2006.285.21:50:10.41#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:50:10.41#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.21:50:10.41#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.21:50:10.41#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.21:50:10.41$vck44/valo=5,734.99 2006.285.21:50:10.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.21:50:10.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.21:50:10.61#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:10.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:50:10.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:50:10.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:50:10.61#ibcon#enter wrdev, iclass 17, count 0 2006.285.21:50:10.61#ibcon#first serial, iclass 17, count 0 2006.285.21:50:10.61#ibcon#enter sib2, iclass 17, count 0 2006.285.21:50:10.61#ibcon#flushed, iclass 17, count 0 2006.285.21:50:10.61#ibcon#about to write, iclass 17, count 0 2006.285.21:50:10.61#ibcon#wrote, iclass 17, count 0 2006.285.21:50:10.61#ibcon#about to read 3, iclass 17, count 0 2006.285.21:50:10.63#ibcon#read 3, iclass 17, count 0 2006.285.21:50:10.63#ibcon#about to read 4, iclass 17, count 0 2006.285.21:50:10.63#ibcon#read 4, iclass 17, count 0 2006.285.21:50:10.63#ibcon#about to read 5, iclass 17, count 0 2006.285.21:50:10.63#ibcon#read 5, iclass 17, count 0 2006.285.21:50:10.63#ibcon#about to read 6, iclass 17, count 0 2006.285.21:50:10.63#ibcon#read 6, iclass 17, count 0 2006.285.21:50:10.63#ibcon#end of sib2, iclass 17, count 0 2006.285.21:50:10.63#ibcon#*mode == 0, iclass 17, count 0 2006.285.21:50:10.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.21:50:10.63#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:50:10.63#ibcon#*before write, iclass 17, count 0 2006.285.21:50:10.63#ibcon#enter sib2, iclass 17, count 0 2006.285.21:50:10.63#ibcon#flushed, iclass 17, count 0 2006.285.21:50:10.63#ibcon#about to write, iclass 17, count 0 2006.285.21:50:10.63#ibcon#wrote, iclass 17, count 0 2006.285.21:50:10.63#ibcon#about to read 3, iclass 17, count 0 2006.285.21:50:10.67#ibcon#read 3, iclass 17, count 0 2006.285.21:50:10.67#ibcon#about to read 4, iclass 17, count 0 2006.285.21:50:10.67#ibcon#read 4, iclass 17, count 0 2006.285.21:50:10.67#ibcon#about to read 5, iclass 17, count 0 2006.285.21:50:10.67#ibcon#read 5, iclass 17, count 0 2006.285.21:50:10.67#ibcon#about to read 6, iclass 17, count 0 2006.285.21:50:10.67#ibcon#read 6, iclass 17, count 0 2006.285.21:50:10.67#ibcon#end of sib2, iclass 17, count 0 2006.285.21:50:10.67#ibcon#*after write, iclass 17, count 0 2006.285.21:50:10.67#ibcon#*before return 0, iclass 17, count 0 2006.285.21:50:10.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:50:10.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.21:50:10.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.21:50:10.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.21:50:10.67$vck44/va=5,3 2006.285.21:50:10.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.21:50:10.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.21:50:10.67#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:10.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:50:10.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:50:10.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:50:10.67#ibcon#enter wrdev, iclass 19, count 2 2006.285.21:50:10.67#ibcon#first serial, iclass 19, count 2 2006.285.21:50:10.67#ibcon#enter sib2, iclass 19, count 2 2006.285.21:50:10.67#ibcon#flushed, iclass 19, count 2 2006.285.21:50:10.67#ibcon#about to write, iclass 19, count 2 2006.285.21:50:10.67#ibcon#wrote, iclass 19, count 2 2006.285.21:50:10.67#ibcon#about to read 3, iclass 19, count 2 2006.285.21:50:10.69#ibcon#read 3, iclass 19, count 2 2006.285.21:50:10.69#ibcon#about to read 4, iclass 19, count 2 2006.285.21:50:10.69#ibcon#read 4, iclass 19, count 2 2006.285.21:50:10.69#ibcon#about to read 5, iclass 19, count 2 2006.285.21:50:10.69#ibcon#read 5, iclass 19, count 2 2006.285.21:50:10.69#ibcon#about to read 6, iclass 19, count 2 2006.285.21:50:10.69#ibcon#read 6, iclass 19, count 2 2006.285.21:50:10.69#ibcon#end of sib2, iclass 19, count 2 2006.285.21:50:10.69#ibcon#*mode == 0, iclass 19, count 2 2006.285.21:50:10.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.21:50:10.69#ibcon#[25=AT05-03\r\n] 2006.285.21:50:10.69#ibcon#*before write, iclass 19, count 2 2006.285.21:50:10.69#ibcon#enter sib2, iclass 19, count 2 2006.285.21:50:10.69#ibcon#flushed, iclass 19, count 2 2006.285.21:50:10.69#ibcon#about to write, iclass 19, count 2 2006.285.21:50:10.69#ibcon#wrote, iclass 19, count 2 2006.285.21:50:10.69#ibcon#about to read 3, iclass 19, count 2 2006.285.21:50:10.72#ibcon#read 3, iclass 19, count 2 2006.285.21:50:10.72#ibcon#about to read 4, iclass 19, count 2 2006.285.21:50:10.72#ibcon#read 4, iclass 19, count 2 2006.285.21:50:10.72#ibcon#about to read 5, iclass 19, count 2 2006.285.21:50:10.72#ibcon#read 5, iclass 19, count 2 2006.285.21:50:10.72#ibcon#about to read 6, iclass 19, count 2 2006.285.21:50:10.72#ibcon#read 6, iclass 19, count 2 2006.285.21:50:10.72#ibcon#end of sib2, iclass 19, count 2 2006.285.21:50:10.72#ibcon#*after write, iclass 19, count 2 2006.285.21:50:10.72#ibcon#*before return 0, iclass 19, count 2 2006.285.21:50:10.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:50:10.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.21:50:10.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.21:50:10.72#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:10.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:50:10.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:50:10.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:50:10.84#ibcon#enter wrdev, iclass 19, count 0 2006.285.21:50:10.84#ibcon#first serial, iclass 19, count 0 2006.285.21:50:10.84#ibcon#enter sib2, iclass 19, count 0 2006.285.21:50:10.84#ibcon#flushed, iclass 19, count 0 2006.285.21:50:10.84#ibcon#about to write, iclass 19, count 0 2006.285.21:50:10.84#ibcon#wrote, iclass 19, count 0 2006.285.21:50:10.84#ibcon#about to read 3, iclass 19, count 0 2006.285.21:50:10.86#ibcon#read 3, iclass 19, count 0 2006.285.21:50:10.86#ibcon#about to read 4, iclass 19, count 0 2006.285.21:50:10.86#ibcon#read 4, iclass 19, count 0 2006.285.21:50:10.86#ibcon#about to read 5, iclass 19, count 0 2006.285.21:50:10.86#ibcon#read 5, iclass 19, count 0 2006.285.21:50:10.86#ibcon#about to read 6, iclass 19, count 0 2006.285.21:50:10.86#ibcon#read 6, iclass 19, count 0 2006.285.21:50:10.86#ibcon#end of sib2, iclass 19, count 0 2006.285.21:50:10.86#ibcon#*mode == 0, iclass 19, count 0 2006.285.21:50:10.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.21:50:10.86#ibcon#[25=USB\r\n] 2006.285.21:50:10.86#ibcon#*before write, iclass 19, count 0 2006.285.21:50:10.86#ibcon#enter sib2, iclass 19, count 0 2006.285.21:50:10.86#ibcon#flushed, iclass 19, count 0 2006.285.21:50:10.86#ibcon#about to write, iclass 19, count 0 2006.285.21:50:10.86#ibcon#wrote, iclass 19, count 0 2006.285.21:50:10.86#ibcon#about to read 3, iclass 19, count 0 2006.285.21:50:10.89#ibcon#read 3, iclass 19, count 0 2006.285.21:50:10.89#ibcon#about to read 4, iclass 19, count 0 2006.285.21:50:10.89#ibcon#read 4, iclass 19, count 0 2006.285.21:50:10.89#ibcon#about to read 5, iclass 19, count 0 2006.285.21:50:10.89#ibcon#read 5, iclass 19, count 0 2006.285.21:50:10.89#ibcon#about to read 6, iclass 19, count 0 2006.285.21:50:10.89#ibcon#read 6, iclass 19, count 0 2006.285.21:50:10.89#ibcon#end of sib2, iclass 19, count 0 2006.285.21:50:10.89#ibcon#*after write, iclass 19, count 0 2006.285.21:50:10.89#ibcon#*before return 0, iclass 19, count 0 2006.285.21:50:10.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:50:10.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.21:50:10.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.21:50:10.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.21:50:10.89$vck44/valo=6,814.99 2006.285.21:50:10.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.21:50:10.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.21:50:10.89#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:10.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:50:10.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:50:10.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:50:10.89#ibcon#enter wrdev, iclass 21, count 0 2006.285.21:50:10.89#ibcon#first serial, iclass 21, count 0 2006.285.21:50:10.89#ibcon#enter sib2, iclass 21, count 0 2006.285.21:50:10.89#ibcon#flushed, iclass 21, count 0 2006.285.21:50:10.89#ibcon#about to write, iclass 21, count 0 2006.285.21:50:10.89#ibcon#wrote, iclass 21, count 0 2006.285.21:50:10.89#ibcon#about to read 3, iclass 21, count 0 2006.285.21:50:10.91#ibcon#read 3, iclass 21, count 0 2006.285.21:50:10.91#ibcon#about to read 4, iclass 21, count 0 2006.285.21:50:10.91#ibcon#read 4, iclass 21, count 0 2006.285.21:50:10.91#ibcon#about to read 5, iclass 21, count 0 2006.285.21:50:10.91#ibcon#read 5, iclass 21, count 0 2006.285.21:50:10.91#ibcon#about to read 6, iclass 21, count 0 2006.285.21:50:10.91#ibcon#read 6, iclass 21, count 0 2006.285.21:50:10.91#ibcon#end of sib2, iclass 21, count 0 2006.285.21:50:10.91#ibcon#*mode == 0, iclass 21, count 0 2006.285.21:50:10.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.21:50:10.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:50:10.91#ibcon#*before write, iclass 21, count 0 2006.285.21:50:10.91#ibcon#enter sib2, iclass 21, count 0 2006.285.21:50:10.91#ibcon#flushed, iclass 21, count 0 2006.285.21:50:10.91#ibcon#about to write, iclass 21, count 0 2006.285.21:50:10.91#ibcon#wrote, iclass 21, count 0 2006.285.21:50:10.91#ibcon#about to read 3, iclass 21, count 0 2006.285.21:50:10.95#ibcon#read 3, iclass 21, count 0 2006.285.21:50:10.95#ibcon#about to read 4, iclass 21, count 0 2006.285.21:50:10.95#ibcon#read 4, iclass 21, count 0 2006.285.21:50:10.95#ibcon#about to read 5, iclass 21, count 0 2006.285.21:50:10.95#ibcon#read 5, iclass 21, count 0 2006.285.21:50:10.95#ibcon#about to read 6, iclass 21, count 0 2006.285.21:50:10.95#ibcon#read 6, iclass 21, count 0 2006.285.21:50:10.95#ibcon#end of sib2, iclass 21, count 0 2006.285.21:50:10.95#ibcon#*after write, iclass 21, count 0 2006.285.21:50:10.95#ibcon#*before return 0, iclass 21, count 0 2006.285.21:50:10.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:50:10.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:50:10.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.21:50:10.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.21:50:10.95$vck44/va=6,4 2006.285.21:50:10.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.21:50:10.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.21:50:10.95#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:10.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:50:11.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:50:11.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:50:11.01#ibcon#enter wrdev, iclass 23, count 2 2006.285.21:50:11.01#ibcon#first serial, iclass 23, count 2 2006.285.21:50:11.01#ibcon#enter sib2, iclass 23, count 2 2006.285.21:50:11.01#ibcon#flushed, iclass 23, count 2 2006.285.21:50:11.01#ibcon#about to write, iclass 23, count 2 2006.285.21:50:11.01#ibcon#wrote, iclass 23, count 2 2006.285.21:50:11.01#ibcon#about to read 3, iclass 23, count 2 2006.285.21:50:11.03#ibcon#read 3, iclass 23, count 2 2006.285.21:50:11.03#ibcon#about to read 4, iclass 23, count 2 2006.285.21:50:11.03#ibcon#read 4, iclass 23, count 2 2006.285.21:50:11.03#ibcon#about to read 5, iclass 23, count 2 2006.285.21:50:11.03#ibcon#read 5, iclass 23, count 2 2006.285.21:50:11.03#ibcon#about to read 6, iclass 23, count 2 2006.285.21:50:11.03#ibcon#read 6, iclass 23, count 2 2006.285.21:50:11.03#ibcon#end of sib2, iclass 23, count 2 2006.285.21:50:11.03#ibcon#*mode == 0, iclass 23, count 2 2006.285.21:50:11.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.21:50:11.03#ibcon#[25=AT06-04\r\n] 2006.285.21:50:11.03#ibcon#*before write, iclass 23, count 2 2006.285.21:50:11.03#ibcon#enter sib2, iclass 23, count 2 2006.285.21:50:11.03#ibcon#flushed, iclass 23, count 2 2006.285.21:50:11.03#ibcon#about to write, iclass 23, count 2 2006.285.21:50:11.03#ibcon#wrote, iclass 23, count 2 2006.285.21:50:11.03#ibcon#about to read 3, iclass 23, count 2 2006.285.21:50:11.06#ibcon#read 3, iclass 23, count 2 2006.285.21:50:11.06#ibcon#about to read 4, iclass 23, count 2 2006.285.21:50:11.06#ibcon#read 4, iclass 23, count 2 2006.285.21:50:11.06#ibcon#about to read 5, iclass 23, count 2 2006.285.21:50:11.06#ibcon#read 5, iclass 23, count 2 2006.285.21:50:11.06#ibcon#about to read 6, iclass 23, count 2 2006.285.21:50:11.06#ibcon#read 6, iclass 23, count 2 2006.285.21:50:11.06#ibcon#end of sib2, iclass 23, count 2 2006.285.21:50:11.06#ibcon#*after write, iclass 23, count 2 2006.285.21:50:11.06#ibcon#*before return 0, iclass 23, count 2 2006.285.21:50:11.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:50:11.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:50:11.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.21:50:11.06#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:11.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:50:11.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:50:11.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:50:11.18#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:50:11.18#ibcon#first serial, iclass 23, count 0 2006.285.21:50:11.18#ibcon#enter sib2, iclass 23, count 0 2006.285.21:50:11.18#ibcon#flushed, iclass 23, count 0 2006.285.21:50:11.18#ibcon#about to write, iclass 23, count 0 2006.285.21:50:11.18#ibcon#wrote, iclass 23, count 0 2006.285.21:50:11.18#ibcon#about to read 3, iclass 23, count 0 2006.285.21:50:11.20#ibcon#read 3, iclass 23, count 0 2006.285.21:50:11.20#ibcon#about to read 4, iclass 23, count 0 2006.285.21:50:11.20#ibcon#read 4, iclass 23, count 0 2006.285.21:50:11.20#ibcon#about to read 5, iclass 23, count 0 2006.285.21:50:11.20#ibcon#read 5, iclass 23, count 0 2006.285.21:50:11.20#ibcon#about to read 6, iclass 23, count 0 2006.285.21:50:11.20#ibcon#read 6, iclass 23, count 0 2006.285.21:50:11.20#ibcon#end of sib2, iclass 23, count 0 2006.285.21:50:11.20#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:50:11.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:50:11.20#ibcon#[25=USB\r\n] 2006.285.21:50:11.20#ibcon#*before write, iclass 23, count 0 2006.285.21:50:11.20#ibcon#enter sib2, iclass 23, count 0 2006.285.21:50:11.20#ibcon#flushed, iclass 23, count 0 2006.285.21:50:11.20#ibcon#about to write, iclass 23, count 0 2006.285.21:50:11.20#ibcon#wrote, iclass 23, count 0 2006.285.21:50:11.20#ibcon#about to read 3, iclass 23, count 0 2006.285.21:50:11.23#ibcon#read 3, iclass 23, count 0 2006.285.21:50:11.23#ibcon#about to read 4, iclass 23, count 0 2006.285.21:50:11.23#ibcon#read 4, iclass 23, count 0 2006.285.21:50:11.23#ibcon#about to read 5, iclass 23, count 0 2006.285.21:50:11.23#ibcon#read 5, iclass 23, count 0 2006.285.21:50:11.23#ibcon#about to read 6, iclass 23, count 0 2006.285.21:50:11.23#ibcon#read 6, iclass 23, count 0 2006.285.21:50:11.23#ibcon#end of sib2, iclass 23, count 0 2006.285.21:50:11.23#ibcon#*after write, iclass 23, count 0 2006.285.21:50:11.23#ibcon#*before return 0, iclass 23, count 0 2006.285.21:50:11.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:50:11.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:50:11.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:50:11.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:50:11.23$vck44/valo=7,864.99 2006.285.21:50:11.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.21:50:11.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.21:50:11.23#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:11.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:50:11.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:50:11.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:50:11.23#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:50:11.23#ibcon#first serial, iclass 25, count 0 2006.285.21:50:11.23#ibcon#enter sib2, iclass 25, count 0 2006.285.21:50:11.23#ibcon#flushed, iclass 25, count 0 2006.285.21:50:11.23#ibcon#about to write, iclass 25, count 0 2006.285.21:50:11.23#ibcon#wrote, iclass 25, count 0 2006.285.21:50:11.23#ibcon#about to read 3, iclass 25, count 0 2006.285.21:50:11.25#ibcon#read 3, iclass 25, count 0 2006.285.21:50:11.25#ibcon#about to read 4, iclass 25, count 0 2006.285.21:50:11.25#ibcon#read 4, iclass 25, count 0 2006.285.21:50:11.25#ibcon#about to read 5, iclass 25, count 0 2006.285.21:50:11.25#ibcon#read 5, iclass 25, count 0 2006.285.21:50:11.25#ibcon#about to read 6, iclass 25, count 0 2006.285.21:50:11.25#ibcon#read 6, iclass 25, count 0 2006.285.21:50:11.25#ibcon#end of sib2, iclass 25, count 0 2006.285.21:50:11.25#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:50:11.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:50:11.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:50:11.25#ibcon#*before write, iclass 25, count 0 2006.285.21:50:11.25#ibcon#enter sib2, iclass 25, count 0 2006.285.21:50:11.25#ibcon#flushed, iclass 25, count 0 2006.285.21:50:11.25#ibcon#about to write, iclass 25, count 0 2006.285.21:50:11.25#ibcon#wrote, iclass 25, count 0 2006.285.21:50:11.25#ibcon#about to read 3, iclass 25, count 0 2006.285.21:50:11.29#ibcon#read 3, iclass 25, count 0 2006.285.21:50:11.29#ibcon#about to read 4, iclass 25, count 0 2006.285.21:50:11.29#ibcon#read 4, iclass 25, count 0 2006.285.21:50:11.29#ibcon#about to read 5, iclass 25, count 0 2006.285.21:50:11.29#ibcon#read 5, iclass 25, count 0 2006.285.21:50:11.29#ibcon#about to read 6, iclass 25, count 0 2006.285.21:50:11.29#ibcon#read 6, iclass 25, count 0 2006.285.21:50:11.29#ibcon#end of sib2, iclass 25, count 0 2006.285.21:50:11.29#ibcon#*after write, iclass 25, count 0 2006.285.21:50:11.29#ibcon#*before return 0, iclass 25, count 0 2006.285.21:50:11.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:50:11.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:50:11.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:50:11.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:50:11.29$vck44/va=7,4 2006.285.21:50:11.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.21:50:11.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.21:50:11.29#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:11.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:50:11.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:50:11.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:50:11.35#ibcon#enter wrdev, iclass 27, count 2 2006.285.21:50:11.35#ibcon#first serial, iclass 27, count 2 2006.285.21:50:11.35#ibcon#enter sib2, iclass 27, count 2 2006.285.21:50:11.35#ibcon#flushed, iclass 27, count 2 2006.285.21:50:11.35#ibcon#about to write, iclass 27, count 2 2006.285.21:50:11.35#ibcon#wrote, iclass 27, count 2 2006.285.21:50:11.35#ibcon#about to read 3, iclass 27, count 2 2006.285.21:50:11.37#ibcon#read 3, iclass 27, count 2 2006.285.21:50:11.37#ibcon#about to read 4, iclass 27, count 2 2006.285.21:50:11.37#ibcon#read 4, iclass 27, count 2 2006.285.21:50:11.37#ibcon#about to read 5, iclass 27, count 2 2006.285.21:50:11.37#ibcon#read 5, iclass 27, count 2 2006.285.21:50:11.37#ibcon#about to read 6, iclass 27, count 2 2006.285.21:50:11.37#ibcon#read 6, iclass 27, count 2 2006.285.21:50:11.37#ibcon#end of sib2, iclass 27, count 2 2006.285.21:50:11.37#ibcon#*mode == 0, iclass 27, count 2 2006.285.21:50:11.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.21:50:11.37#ibcon#[25=AT07-04\r\n] 2006.285.21:50:11.37#ibcon#*before write, iclass 27, count 2 2006.285.21:50:11.37#ibcon#enter sib2, iclass 27, count 2 2006.285.21:50:11.37#ibcon#flushed, iclass 27, count 2 2006.285.21:50:11.37#ibcon#about to write, iclass 27, count 2 2006.285.21:50:11.37#ibcon#wrote, iclass 27, count 2 2006.285.21:50:11.37#ibcon#about to read 3, iclass 27, count 2 2006.285.21:50:11.40#ibcon#read 3, iclass 27, count 2 2006.285.21:50:11.40#ibcon#about to read 4, iclass 27, count 2 2006.285.21:50:11.40#ibcon#read 4, iclass 27, count 2 2006.285.21:50:11.40#ibcon#about to read 5, iclass 27, count 2 2006.285.21:50:11.40#ibcon#read 5, iclass 27, count 2 2006.285.21:50:11.40#ibcon#about to read 6, iclass 27, count 2 2006.285.21:50:11.40#ibcon#read 6, iclass 27, count 2 2006.285.21:50:11.40#ibcon#end of sib2, iclass 27, count 2 2006.285.21:50:11.40#ibcon#*after write, iclass 27, count 2 2006.285.21:50:11.40#ibcon#*before return 0, iclass 27, count 2 2006.285.21:50:11.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:50:11.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:50:11.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.21:50:11.40#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:11.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:50:11.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:50:11.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:50:11.52#ibcon#enter wrdev, iclass 27, count 0 2006.285.21:50:11.52#ibcon#first serial, iclass 27, count 0 2006.285.21:50:11.52#ibcon#enter sib2, iclass 27, count 0 2006.285.21:50:11.52#ibcon#flushed, iclass 27, count 0 2006.285.21:50:11.52#ibcon#about to write, iclass 27, count 0 2006.285.21:50:11.52#ibcon#wrote, iclass 27, count 0 2006.285.21:50:11.52#ibcon#about to read 3, iclass 27, count 0 2006.285.21:50:11.54#ibcon#read 3, iclass 27, count 0 2006.285.21:50:11.54#ibcon#about to read 4, iclass 27, count 0 2006.285.21:50:11.54#ibcon#read 4, iclass 27, count 0 2006.285.21:50:11.54#ibcon#about to read 5, iclass 27, count 0 2006.285.21:50:11.54#ibcon#read 5, iclass 27, count 0 2006.285.21:50:11.54#ibcon#about to read 6, iclass 27, count 0 2006.285.21:50:11.54#ibcon#read 6, iclass 27, count 0 2006.285.21:50:11.54#ibcon#end of sib2, iclass 27, count 0 2006.285.21:50:11.54#ibcon#*mode == 0, iclass 27, count 0 2006.285.21:50:11.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.21:50:11.54#ibcon#[25=USB\r\n] 2006.285.21:50:11.54#ibcon#*before write, iclass 27, count 0 2006.285.21:50:11.54#ibcon#enter sib2, iclass 27, count 0 2006.285.21:50:11.54#ibcon#flushed, iclass 27, count 0 2006.285.21:50:11.54#ibcon#about to write, iclass 27, count 0 2006.285.21:50:11.54#ibcon#wrote, iclass 27, count 0 2006.285.21:50:11.54#ibcon#about to read 3, iclass 27, count 0 2006.285.21:50:11.57#ibcon#read 3, iclass 27, count 0 2006.285.21:50:11.57#ibcon#about to read 4, iclass 27, count 0 2006.285.21:50:11.57#ibcon#read 4, iclass 27, count 0 2006.285.21:50:11.57#ibcon#about to read 5, iclass 27, count 0 2006.285.21:50:11.57#ibcon#read 5, iclass 27, count 0 2006.285.21:50:11.57#ibcon#about to read 6, iclass 27, count 0 2006.285.21:50:11.57#ibcon#read 6, iclass 27, count 0 2006.285.21:50:11.57#ibcon#end of sib2, iclass 27, count 0 2006.285.21:50:11.57#ibcon#*after write, iclass 27, count 0 2006.285.21:50:11.57#ibcon#*before return 0, iclass 27, count 0 2006.285.21:50:11.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:50:11.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:50:11.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.21:50:11.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.21:50:11.57$vck44/valo=8,884.99 2006.285.21:50:11.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.21:50:11.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.21:50:11.57#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:11.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:50:11.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:50:11.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:50:11.57#ibcon#enter wrdev, iclass 29, count 0 2006.285.21:50:11.57#ibcon#first serial, iclass 29, count 0 2006.285.21:50:11.57#ibcon#enter sib2, iclass 29, count 0 2006.285.21:50:11.57#ibcon#flushed, iclass 29, count 0 2006.285.21:50:11.57#ibcon#about to write, iclass 29, count 0 2006.285.21:50:11.57#ibcon#wrote, iclass 29, count 0 2006.285.21:50:11.57#ibcon#about to read 3, iclass 29, count 0 2006.285.21:50:11.59#ibcon#read 3, iclass 29, count 0 2006.285.21:50:11.59#ibcon#about to read 4, iclass 29, count 0 2006.285.21:50:11.59#ibcon#read 4, iclass 29, count 0 2006.285.21:50:11.59#ibcon#about to read 5, iclass 29, count 0 2006.285.21:50:11.59#ibcon#read 5, iclass 29, count 0 2006.285.21:50:11.59#ibcon#about to read 6, iclass 29, count 0 2006.285.21:50:11.59#ibcon#read 6, iclass 29, count 0 2006.285.21:50:11.59#ibcon#end of sib2, iclass 29, count 0 2006.285.21:50:11.59#ibcon#*mode == 0, iclass 29, count 0 2006.285.21:50:11.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.21:50:11.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:50:11.59#ibcon#*before write, iclass 29, count 0 2006.285.21:50:11.59#ibcon#enter sib2, iclass 29, count 0 2006.285.21:50:11.59#ibcon#flushed, iclass 29, count 0 2006.285.21:50:11.59#ibcon#about to write, iclass 29, count 0 2006.285.21:50:11.59#ibcon#wrote, iclass 29, count 0 2006.285.21:50:11.59#ibcon#about to read 3, iclass 29, count 0 2006.285.21:50:11.63#ibcon#read 3, iclass 29, count 0 2006.285.21:50:11.63#ibcon#about to read 4, iclass 29, count 0 2006.285.21:50:11.63#ibcon#read 4, iclass 29, count 0 2006.285.21:50:11.63#ibcon#about to read 5, iclass 29, count 0 2006.285.21:50:11.63#ibcon#read 5, iclass 29, count 0 2006.285.21:50:11.63#ibcon#about to read 6, iclass 29, count 0 2006.285.21:50:11.63#ibcon#read 6, iclass 29, count 0 2006.285.21:50:11.63#ibcon#end of sib2, iclass 29, count 0 2006.285.21:50:11.63#ibcon#*after write, iclass 29, count 0 2006.285.21:50:11.63#ibcon#*before return 0, iclass 29, count 0 2006.285.21:50:11.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:50:11.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:50:11.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.21:50:11.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.21:50:11.63$vck44/va=8,3 2006.285.21:50:11.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.21:50:11.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.21:50:11.63#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:11.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:50:11.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:50:11.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:50:11.69#ibcon#enter wrdev, iclass 31, count 2 2006.285.21:50:11.69#ibcon#first serial, iclass 31, count 2 2006.285.21:50:11.69#ibcon#enter sib2, iclass 31, count 2 2006.285.21:50:11.69#ibcon#flushed, iclass 31, count 2 2006.285.21:50:11.69#ibcon#about to write, iclass 31, count 2 2006.285.21:50:11.69#ibcon#wrote, iclass 31, count 2 2006.285.21:50:11.69#ibcon#about to read 3, iclass 31, count 2 2006.285.21:50:11.71#ibcon#read 3, iclass 31, count 2 2006.285.21:50:11.71#ibcon#about to read 4, iclass 31, count 2 2006.285.21:50:11.71#ibcon#read 4, iclass 31, count 2 2006.285.21:50:11.71#ibcon#about to read 5, iclass 31, count 2 2006.285.21:50:11.71#ibcon#read 5, iclass 31, count 2 2006.285.21:50:11.71#ibcon#about to read 6, iclass 31, count 2 2006.285.21:50:11.71#ibcon#read 6, iclass 31, count 2 2006.285.21:50:11.71#ibcon#end of sib2, iclass 31, count 2 2006.285.21:50:11.71#ibcon#*mode == 0, iclass 31, count 2 2006.285.21:50:11.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.21:50:11.71#ibcon#[25=AT08-03\r\n] 2006.285.21:50:11.71#ibcon#*before write, iclass 31, count 2 2006.285.21:50:11.71#ibcon#enter sib2, iclass 31, count 2 2006.285.21:50:11.71#ibcon#flushed, iclass 31, count 2 2006.285.21:50:11.71#ibcon#about to write, iclass 31, count 2 2006.285.21:50:11.71#ibcon#wrote, iclass 31, count 2 2006.285.21:50:11.71#ibcon#about to read 3, iclass 31, count 2 2006.285.21:50:11.74#ibcon#read 3, iclass 31, count 2 2006.285.21:50:11.86#ibcon#about to read 4, iclass 31, count 2 2006.285.21:50:11.86#ibcon#read 4, iclass 31, count 2 2006.285.21:50:11.86#ibcon#about to read 5, iclass 31, count 2 2006.285.21:50:11.86#ibcon#read 5, iclass 31, count 2 2006.285.21:50:11.86#ibcon#about to read 6, iclass 31, count 2 2006.285.21:50:11.86#ibcon#read 6, iclass 31, count 2 2006.285.21:50:11.86#ibcon#end of sib2, iclass 31, count 2 2006.285.21:50:11.86#ibcon#*after write, iclass 31, count 2 2006.285.21:50:11.86#ibcon#*before return 0, iclass 31, count 2 2006.285.21:50:11.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:50:11.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:50:11.86#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.21:50:11.86#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:11.86#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:50:11.98#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:50:11.98#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:50:11.98#ibcon#enter wrdev, iclass 31, count 0 2006.285.21:50:11.98#ibcon#first serial, iclass 31, count 0 2006.285.21:50:11.98#ibcon#enter sib2, iclass 31, count 0 2006.285.21:50:11.98#ibcon#flushed, iclass 31, count 0 2006.285.21:50:11.98#ibcon#about to write, iclass 31, count 0 2006.285.21:50:11.98#ibcon#wrote, iclass 31, count 0 2006.285.21:50:11.98#ibcon#about to read 3, iclass 31, count 0 2006.285.21:50:12.00#ibcon#read 3, iclass 31, count 0 2006.285.21:50:12.00#ibcon#about to read 4, iclass 31, count 0 2006.285.21:50:12.00#ibcon#read 4, iclass 31, count 0 2006.285.21:50:12.00#ibcon#about to read 5, iclass 31, count 0 2006.285.21:50:12.00#ibcon#read 5, iclass 31, count 0 2006.285.21:50:12.00#ibcon#about to read 6, iclass 31, count 0 2006.285.21:50:12.00#ibcon#read 6, iclass 31, count 0 2006.285.21:50:12.00#ibcon#end of sib2, iclass 31, count 0 2006.285.21:50:12.00#ibcon#*mode == 0, iclass 31, count 0 2006.285.21:50:12.00#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.21:50:12.00#ibcon#[25=USB\r\n] 2006.285.21:50:12.00#ibcon#*before write, iclass 31, count 0 2006.285.21:50:12.00#ibcon#enter sib2, iclass 31, count 0 2006.285.21:50:12.00#ibcon#flushed, iclass 31, count 0 2006.285.21:50:12.00#ibcon#about to write, iclass 31, count 0 2006.285.21:50:12.00#ibcon#wrote, iclass 31, count 0 2006.285.21:50:12.00#ibcon#about to read 3, iclass 31, count 0 2006.285.21:50:12.03#ibcon#read 3, iclass 31, count 0 2006.285.21:50:12.03#ibcon#about to read 4, iclass 31, count 0 2006.285.21:50:12.03#ibcon#read 4, iclass 31, count 0 2006.285.21:50:12.03#ibcon#about to read 5, iclass 31, count 0 2006.285.21:50:12.03#ibcon#read 5, iclass 31, count 0 2006.285.21:50:12.03#ibcon#about to read 6, iclass 31, count 0 2006.285.21:50:12.03#ibcon#read 6, iclass 31, count 0 2006.285.21:50:12.03#ibcon#end of sib2, iclass 31, count 0 2006.285.21:50:12.03#ibcon#*after write, iclass 31, count 0 2006.285.21:50:12.03#ibcon#*before return 0, iclass 31, count 0 2006.285.21:50:12.03#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:50:12.03#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:50:12.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.21:50:12.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.21:50:12.03$vck44/vblo=1,629.99 2006.285.21:50:12.03#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.21:50:12.03#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.21:50:12.03#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:12.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:50:12.03#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:50:12.03#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:50:12.03#ibcon#enter wrdev, iclass 33, count 0 2006.285.21:50:12.03#ibcon#first serial, iclass 33, count 0 2006.285.21:50:12.03#ibcon#enter sib2, iclass 33, count 0 2006.285.21:50:12.03#ibcon#flushed, iclass 33, count 0 2006.285.21:50:12.03#ibcon#about to write, iclass 33, count 0 2006.285.21:50:12.03#ibcon#wrote, iclass 33, count 0 2006.285.21:50:12.03#ibcon#about to read 3, iclass 33, count 0 2006.285.21:50:12.05#ibcon#read 3, iclass 33, count 0 2006.285.21:50:12.05#ibcon#about to read 4, iclass 33, count 0 2006.285.21:50:12.05#ibcon#read 4, iclass 33, count 0 2006.285.21:50:12.05#ibcon#about to read 5, iclass 33, count 0 2006.285.21:50:12.05#ibcon#read 5, iclass 33, count 0 2006.285.21:50:12.05#ibcon#about to read 6, iclass 33, count 0 2006.285.21:50:12.05#ibcon#read 6, iclass 33, count 0 2006.285.21:50:12.05#ibcon#end of sib2, iclass 33, count 0 2006.285.21:50:12.05#ibcon#*mode == 0, iclass 33, count 0 2006.285.21:50:12.05#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.21:50:12.05#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:50:12.05#ibcon#*before write, iclass 33, count 0 2006.285.21:50:12.05#ibcon#enter sib2, iclass 33, count 0 2006.285.21:50:12.05#ibcon#flushed, iclass 33, count 0 2006.285.21:50:12.05#ibcon#about to write, iclass 33, count 0 2006.285.21:50:12.05#ibcon#wrote, iclass 33, count 0 2006.285.21:50:12.05#ibcon#about to read 3, iclass 33, count 0 2006.285.21:50:12.09#ibcon#read 3, iclass 33, count 0 2006.285.21:50:12.09#ibcon#about to read 4, iclass 33, count 0 2006.285.21:50:12.09#ibcon#read 4, iclass 33, count 0 2006.285.21:50:12.09#ibcon#about to read 5, iclass 33, count 0 2006.285.21:50:12.09#ibcon#read 5, iclass 33, count 0 2006.285.21:50:12.09#ibcon#about to read 6, iclass 33, count 0 2006.285.21:50:12.09#ibcon#read 6, iclass 33, count 0 2006.285.21:50:12.09#ibcon#end of sib2, iclass 33, count 0 2006.285.21:50:12.09#ibcon#*after write, iclass 33, count 0 2006.285.21:50:12.09#ibcon#*before return 0, iclass 33, count 0 2006.285.21:50:12.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:50:12.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:50:12.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.21:50:12.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.21:50:12.09$vck44/vb=1,4 2006.285.21:50:12.09#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.21:50:12.09#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.21:50:12.09#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:12.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:50:12.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:50:12.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:50:12.09#ibcon#enter wrdev, iclass 35, count 2 2006.285.21:50:12.09#ibcon#first serial, iclass 35, count 2 2006.285.21:50:12.09#ibcon#enter sib2, iclass 35, count 2 2006.285.21:50:12.09#ibcon#flushed, iclass 35, count 2 2006.285.21:50:12.09#ibcon#about to write, iclass 35, count 2 2006.285.21:50:12.09#ibcon#wrote, iclass 35, count 2 2006.285.21:50:12.09#ibcon#about to read 3, iclass 35, count 2 2006.285.21:50:12.11#ibcon#read 3, iclass 35, count 2 2006.285.21:50:12.11#ibcon#about to read 4, iclass 35, count 2 2006.285.21:50:12.11#ibcon#read 4, iclass 35, count 2 2006.285.21:50:12.11#ibcon#about to read 5, iclass 35, count 2 2006.285.21:50:12.11#ibcon#read 5, iclass 35, count 2 2006.285.21:50:12.11#ibcon#about to read 6, iclass 35, count 2 2006.285.21:50:12.11#ibcon#read 6, iclass 35, count 2 2006.285.21:50:12.11#ibcon#end of sib2, iclass 35, count 2 2006.285.21:50:12.11#ibcon#*mode == 0, iclass 35, count 2 2006.285.21:50:12.11#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.21:50:12.11#ibcon#[27=AT01-04\r\n] 2006.285.21:50:12.11#ibcon#*before write, iclass 35, count 2 2006.285.21:50:12.11#ibcon#enter sib2, iclass 35, count 2 2006.285.21:50:12.11#ibcon#flushed, iclass 35, count 2 2006.285.21:50:12.11#ibcon#about to write, iclass 35, count 2 2006.285.21:50:12.11#ibcon#wrote, iclass 35, count 2 2006.285.21:50:12.11#ibcon#about to read 3, iclass 35, count 2 2006.285.21:50:12.14#ibcon#read 3, iclass 35, count 2 2006.285.21:50:12.14#ibcon#about to read 4, iclass 35, count 2 2006.285.21:50:12.14#ibcon#read 4, iclass 35, count 2 2006.285.21:50:12.14#ibcon#about to read 5, iclass 35, count 2 2006.285.21:50:12.14#ibcon#read 5, iclass 35, count 2 2006.285.21:50:12.14#ibcon#about to read 6, iclass 35, count 2 2006.285.21:50:12.14#ibcon#read 6, iclass 35, count 2 2006.285.21:50:12.14#ibcon#end of sib2, iclass 35, count 2 2006.285.21:50:12.14#ibcon#*after write, iclass 35, count 2 2006.285.21:50:12.14#ibcon#*before return 0, iclass 35, count 2 2006.285.21:50:12.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:50:12.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.21:50:12.14#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.21:50:12.14#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:12.14#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:50:12.26#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:50:12.26#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:50:12.26#ibcon#enter wrdev, iclass 35, count 0 2006.285.21:50:12.26#ibcon#first serial, iclass 35, count 0 2006.285.21:50:12.26#ibcon#enter sib2, iclass 35, count 0 2006.285.21:50:12.26#ibcon#flushed, iclass 35, count 0 2006.285.21:50:12.26#ibcon#about to write, iclass 35, count 0 2006.285.21:50:12.26#ibcon#wrote, iclass 35, count 0 2006.285.21:50:12.26#ibcon#about to read 3, iclass 35, count 0 2006.285.21:50:12.28#ibcon#read 3, iclass 35, count 0 2006.285.21:50:12.28#ibcon#about to read 4, iclass 35, count 0 2006.285.21:50:12.28#ibcon#read 4, iclass 35, count 0 2006.285.21:50:12.28#ibcon#about to read 5, iclass 35, count 0 2006.285.21:50:12.28#ibcon#read 5, iclass 35, count 0 2006.285.21:50:12.28#ibcon#about to read 6, iclass 35, count 0 2006.285.21:50:12.28#ibcon#read 6, iclass 35, count 0 2006.285.21:50:12.28#ibcon#end of sib2, iclass 35, count 0 2006.285.21:50:12.28#ibcon#*mode == 0, iclass 35, count 0 2006.285.21:50:12.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.21:50:12.28#ibcon#[27=USB\r\n] 2006.285.21:50:12.28#ibcon#*before write, iclass 35, count 0 2006.285.21:50:12.28#ibcon#enter sib2, iclass 35, count 0 2006.285.21:50:12.28#ibcon#flushed, iclass 35, count 0 2006.285.21:50:12.28#ibcon#about to write, iclass 35, count 0 2006.285.21:50:12.28#ibcon#wrote, iclass 35, count 0 2006.285.21:50:12.28#ibcon#about to read 3, iclass 35, count 0 2006.285.21:50:12.31#ibcon#read 3, iclass 35, count 0 2006.285.21:50:12.31#ibcon#about to read 4, iclass 35, count 0 2006.285.21:50:12.31#ibcon#read 4, iclass 35, count 0 2006.285.21:50:12.31#ibcon#about to read 5, iclass 35, count 0 2006.285.21:50:12.31#ibcon#read 5, iclass 35, count 0 2006.285.21:50:12.31#ibcon#about to read 6, iclass 35, count 0 2006.285.21:50:12.31#ibcon#read 6, iclass 35, count 0 2006.285.21:50:12.31#ibcon#end of sib2, iclass 35, count 0 2006.285.21:50:12.31#ibcon#*after write, iclass 35, count 0 2006.285.21:50:12.31#ibcon#*before return 0, iclass 35, count 0 2006.285.21:50:12.31#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:50:12.31#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.21:50:12.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.21:50:12.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.21:50:12.31$vck44/vblo=2,634.99 2006.285.21:50:12.31#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.21:50:12.31#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.21:50:12.31#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:12.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:50:12.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:50:12.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:50:12.31#ibcon#enter wrdev, iclass 37, count 0 2006.285.21:50:12.31#ibcon#first serial, iclass 37, count 0 2006.285.21:50:12.31#ibcon#enter sib2, iclass 37, count 0 2006.285.21:50:12.31#ibcon#flushed, iclass 37, count 0 2006.285.21:50:12.31#ibcon#about to write, iclass 37, count 0 2006.285.21:50:12.31#ibcon#wrote, iclass 37, count 0 2006.285.21:50:12.31#ibcon#about to read 3, iclass 37, count 0 2006.285.21:50:12.33#ibcon#read 3, iclass 37, count 0 2006.285.21:50:12.33#ibcon#about to read 4, iclass 37, count 0 2006.285.21:50:12.33#ibcon#read 4, iclass 37, count 0 2006.285.21:50:12.33#ibcon#about to read 5, iclass 37, count 0 2006.285.21:50:12.33#ibcon#read 5, iclass 37, count 0 2006.285.21:50:12.33#ibcon#about to read 6, iclass 37, count 0 2006.285.21:50:12.33#ibcon#read 6, iclass 37, count 0 2006.285.21:50:12.33#ibcon#end of sib2, iclass 37, count 0 2006.285.21:50:12.33#ibcon#*mode == 0, iclass 37, count 0 2006.285.21:50:12.33#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.21:50:12.33#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:50:12.33#ibcon#*before write, iclass 37, count 0 2006.285.21:50:12.33#ibcon#enter sib2, iclass 37, count 0 2006.285.21:50:12.33#ibcon#flushed, iclass 37, count 0 2006.285.21:50:12.33#ibcon#about to write, iclass 37, count 0 2006.285.21:50:12.33#ibcon#wrote, iclass 37, count 0 2006.285.21:50:12.33#ibcon#about to read 3, iclass 37, count 0 2006.285.21:50:12.37#ibcon#read 3, iclass 37, count 0 2006.285.21:50:12.37#ibcon#about to read 4, iclass 37, count 0 2006.285.21:50:12.37#ibcon#read 4, iclass 37, count 0 2006.285.21:50:12.37#ibcon#about to read 5, iclass 37, count 0 2006.285.21:50:12.37#ibcon#read 5, iclass 37, count 0 2006.285.21:50:12.37#ibcon#about to read 6, iclass 37, count 0 2006.285.21:50:12.37#ibcon#read 6, iclass 37, count 0 2006.285.21:50:12.37#ibcon#end of sib2, iclass 37, count 0 2006.285.21:50:12.37#ibcon#*after write, iclass 37, count 0 2006.285.21:50:12.37#ibcon#*before return 0, iclass 37, count 0 2006.285.21:50:12.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:50:12.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.21:50:12.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.21:50:12.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.21:50:12.37$vck44/vb=2,5 2006.285.21:50:12.37#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.21:50:12.37#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.21:50:12.37#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:12.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:50:12.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:50:12.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:50:12.43#ibcon#enter wrdev, iclass 39, count 2 2006.285.21:50:12.43#ibcon#first serial, iclass 39, count 2 2006.285.21:50:12.43#ibcon#enter sib2, iclass 39, count 2 2006.285.21:50:12.43#ibcon#flushed, iclass 39, count 2 2006.285.21:50:12.43#ibcon#about to write, iclass 39, count 2 2006.285.21:50:12.43#ibcon#wrote, iclass 39, count 2 2006.285.21:50:12.43#ibcon#about to read 3, iclass 39, count 2 2006.285.21:50:12.45#ibcon#read 3, iclass 39, count 2 2006.285.21:50:12.45#ibcon#about to read 4, iclass 39, count 2 2006.285.21:50:12.45#ibcon#read 4, iclass 39, count 2 2006.285.21:50:12.45#ibcon#about to read 5, iclass 39, count 2 2006.285.21:50:12.45#ibcon#read 5, iclass 39, count 2 2006.285.21:50:12.45#ibcon#about to read 6, iclass 39, count 2 2006.285.21:50:12.45#ibcon#read 6, iclass 39, count 2 2006.285.21:50:12.45#ibcon#end of sib2, iclass 39, count 2 2006.285.21:50:12.45#ibcon#*mode == 0, iclass 39, count 2 2006.285.21:50:12.45#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.21:50:12.45#ibcon#[27=AT02-05\r\n] 2006.285.21:50:12.45#ibcon#*before write, iclass 39, count 2 2006.285.21:50:12.45#ibcon#enter sib2, iclass 39, count 2 2006.285.21:50:12.45#ibcon#flushed, iclass 39, count 2 2006.285.21:50:12.45#ibcon#about to write, iclass 39, count 2 2006.285.21:50:12.45#ibcon#wrote, iclass 39, count 2 2006.285.21:50:12.45#ibcon#about to read 3, iclass 39, count 2 2006.285.21:50:12.48#ibcon#read 3, iclass 39, count 2 2006.285.21:50:12.48#ibcon#about to read 4, iclass 39, count 2 2006.285.21:50:12.48#ibcon#read 4, iclass 39, count 2 2006.285.21:50:12.48#ibcon#about to read 5, iclass 39, count 2 2006.285.21:50:12.48#ibcon#read 5, iclass 39, count 2 2006.285.21:50:12.48#ibcon#about to read 6, iclass 39, count 2 2006.285.21:50:12.48#ibcon#read 6, iclass 39, count 2 2006.285.21:50:12.48#ibcon#end of sib2, iclass 39, count 2 2006.285.21:50:12.48#ibcon#*after write, iclass 39, count 2 2006.285.21:50:12.48#ibcon#*before return 0, iclass 39, count 2 2006.285.21:50:12.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:50:12.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.21:50:12.48#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.21:50:12.48#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:12.48#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:50:12.60#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:50:12.60#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:50:12.60#ibcon#enter wrdev, iclass 39, count 0 2006.285.21:50:12.60#ibcon#first serial, iclass 39, count 0 2006.285.21:50:12.60#ibcon#enter sib2, iclass 39, count 0 2006.285.21:50:12.60#ibcon#flushed, iclass 39, count 0 2006.285.21:50:12.60#ibcon#about to write, iclass 39, count 0 2006.285.21:50:12.60#ibcon#wrote, iclass 39, count 0 2006.285.21:50:12.60#ibcon#about to read 3, iclass 39, count 0 2006.285.21:50:12.62#ibcon#read 3, iclass 39, count 0 2006.285.21:50:12.62#ibcon#about to read 4, iclass 39, count 0 2006.285.21:50:12.62#ibcon#read 4, iclass 39, count 0 2006.285.21:50:12.62#ibcon#about to read 5, iclass 39, count 0 2006.285.21:50:12.62#ibcon#read 5, iclass 39, count 0 2006.285.21:50:12.62#ibcon#about to read 6, iclass 39, count 0 2006.285.21:50:12.62#ibcon#read 6, iclass 39, count 0 2006.285.21:50:12.62#ibcon#end of sib2, iclass 39, count 0 2006.285.21:50:12.62#ibcon#*mode == 0, iclass 39, count 0 2006.285.21:50:12.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.21:50:12.62#ibcon#[27=USB\r\n] 2006.285.21:50:12.62#ibcon#*before write, iclass 39, count 0 2006.285.21:50:12.62#ibcon#enter sib2, iclass 39, count 0 2006.285.21:50:12.62#ibcon#flushed, iclass 39, count 0 2006.285.21:50:12.62#ibcon#about to write, iclass 39, count 0 2006.285.21:50:12.62#ibcon#wrote, iclass 39, count 0 2006.285.21:50:12.62#ibcon#about to read 3, iclass 39, count 0 2006.285.21:50:12.65#ibcon#read 3, iclass 39, count 0 2006.285.21:50:12.65#ibcon#about to read 4, iclass 39, count 0 2006.285.21:50:12.65#ibcon#read 4, iclass 39, count 0 2006.285.21:50:12.65#ibcon#about to read 5, iclass 39, count 0 2006.285.21:50:12.65#ibcon#read 5, iclass 39, count 0 2006.285.21:50:12.65#ibcon#about to read 6, iclass 39, count 0 2006.285.21:50:12.65#ibcon#read 6, iclass 39, count 0 2006.285.21:50:12.65#ibcon#end of sib2, iclass 39, count 0 2006.285.21:50:12.65#ibcon#*after write, iclass 39, count 0 2006.285.21:50:12.65#ibcon#*before return 0, iclass 39, count 0 2006.285.21:50:12.65#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:50:12.65#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.21:50:12.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.21:50:12.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.21:50:12.65$vck44/vblo=3,649.99 2006.285.21:50:12.65#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.21:50:12.65#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.21:50:12.65#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:12.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:50:12.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:50:12.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:50:12.65#ibcon#enter wrdev, iclass 3, count 0 2006.285.21:50:12.65#ibcon#first serial, iclass 3, count 0 2006.285.21:50:12.65#ibcon#enter sib2, iclass 3, count 0 2006.285.21:50:12.65#ibcon#flushed, iclass 3, count 0 2006.285.21:50:12.65#ibcon#about to write, iclass 3, count 0 2006.285.21:50:12.65#ibcon#wrote, iclass 3, count 0 2006.285.21:50:12.65#ibcon#about to read 3, iclass 3, count 0 2006.285.21:50:12.67#ibcon#read 3, iclass 3, count 0 2006.285.21:50:12.67#ibcon#about to read 4, iclass 3, count 0 2006.285.21:50:12.67#ibcon#read 4, iclass 3, count 0 2006.285.21:50:12.67#ibcon#about to read 5, iclass 3, count 0 2006.285.21:50:12.67#ibcon#read 5, iclass 3, count 0 2006.285.21:50:12.67#ibcon#about to read 6, iclass 3, count 0 2006.285.21:50:12.67#ibcon#read 6, iclass 3, count 0 2006.285.21:50:12.67#ibcon#end of sib2, iclass 3, count 0 2006.285.21:50:12.67#ibcon#*mode == 0, iclass 3, count 0 2006.285.21:50:12.67#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.21:50:12.67#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:50:12.67#ibcon#*before write, iclass 3, count 0 2006.285.21:50:12.67#ibcon#enter sib2, iclass 3, count 0 2006.285.21:50:12.67#ibcon#flushed, iclass 3, count 0 2006.285.21:50:12.67#ibcon#about to write, iclass 3, count 0 2006.285.21:50:12.67#ibcon#wrote, iclass 3, count 0 2006.285.21:50:12.67#ibcon#about to read 3, iclass 3, count 0 2006.285.21:50:12.71#ibcon#read 3, iclass 3, count 0 2006.285.21:50:12.71#ibcon#about to read 4, iclass 3, count 0 2006.285.21:50:12.71#ibcon#read 4, iclass 3, count 0 2006.285.21:50:12.71#ibcon#about to read 5, iclass 3, count 0 2006.285.21:50:12.71#ibcon#read 5, iclass 3, count 0 2006.285.21:50:12.71#ibcon#about to read 6, iclass 3, count 0 2006.285.21:50:12.71#ibcon#read 6, iclass 3, count 0 2006.285.21:50:12.71#ibcon#end of sib2, iclass 3, count 0 2006.285.21:50:12.71#ibcon#*after write, iclass 3, count 0 2006.285.21:50:12.71#ibcon#*before return 0, iclass 3, count 0 2006.285.21:50:12.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:50:12.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.21:50:12.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.21:50:12.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.21:50:12.71$vck44/vb=3,4 2006.285.21:50:13.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.21:50:13.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.21:50:13.31#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:13.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:50:13.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:50:13.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:50:13.31#ibcon#enter wrdev, iclass 5, count 2 2006.285.21:50:13.31#ibcon#first serial, iclass 5, count 2 2006.285.21:50:13.31#ibcon#enter sib2, iclass 5, count 2 2006.285.21:50:13.31#ibcon#flushed, iclass 5, count 2 2006.285.21:50:13.31#ibcon#about to write, iclass 5, count 2 2006.285.21:50:13.31#ibcon#wrote, iclass 5, count 2 2006.285.21:50:13.31#ibcon#about to read 3, iclass 5, count 2 2006.285.21:50:13.33#ibcon#read 3, iclass 5, count 2 2006.285.21:50:13.33#ibcon#about to read 4, iclass 5, count 2 2006.285.21:50:13.33#ibcon#read 4, iclass 5, count 2 2006.285.21:50:13.33#ibcon#about to read 5, iclass 5, count 2 2006.285.21:50:13.33#ibcon#read 5, iclass 5, count 2 2006.285.21:50:13.33#ibcon#about to read 6, iclass 5, count 2 2006.285.21:50:13.33#ibcon#read 6, iclass 5, count 2 2006.285.21:50:13.33#ibcon#end of sib2, iclass 5, count 2 2006.285.21:50:13.33#ibcon#*mode == 0, iclass 5, count 2 2006.285.21:50:13.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.21:50:13.33#ibcon#[27=AT03-04\r\n] 2006.285.21:50:13.33#ibcon#*before write, iclass 5, count 2 2006.285.21:50:13.33#ibcon#enter sib2, iclass 5, count 2 2006.285.21:50:13.33#ibcon#flushed, iclass 5, count 2 2006.285.21:50:13.33#ibcon#about to write, iclass 5, count 2 2006.285.21:50:13.33#ibcon#wrote, iclass 5, count 2 2006.285.21:50:13.33#ibcon#about to read 3, iclass 5, count 2 2006.285.21:50:13.36#ibcon#read 3, iclass 5, count 2 2006.285.21:50:13.36#ibcon#about to read 4, iclass 5, count 2 2006.285.21:50:13.36#ibcon#read 4, iclass 5, count 2 2006.285.21:50:13.36#ibcon#about to read 5, iclass 5, count 2 2006.285.21:50:13.36#ibcon#read 5, iclass 5, count 2 2006.285.21:50:13.36#ibcon#about to read 6, iclass 5, count 2 2006.285.21:50:13.36#ibcon#read 6, iclass 5, count 2 2006.285.21:50:13.36#ibcon#end of sib2, iclass 5, count 2 2006.285.21:50:13.36#ibcon#*after write, iclass 5, count 2 2006.285.21:50:13.36#ibcon#*before return 0, iclass 5, count 2 2006.285.21:50:13.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:50:13.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.21:50:13.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.21:50:13.36#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:13.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:50:13.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:50:13.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:50:13.48#ibcon#enter wrdev, iclass 5, count 0 2006.285.21:50:13.48#ibcon#first serial, iclass 5, count 0 2006.285.21:50:13.48#ibcon#enter sib2, iclass 5, count 0 2006.285.21:50:13.48#ibcon#flushed, iclass 5, count 0 2006.285.21:50:13.48#ibcon#about to write, iclass 5, count 0 2006.285.21:50:13.48#ibcon#wrote, iclass 5, count 0 2006.285.21:50:13.48#ibcon#about to read 3, iclass 5, count 0 2006.285.21:50:13.50#ibcon#read 3, iclass 5, count 0 2006.285.21:50:13.50#ibcon#about to read 4, iclass 5, count 0 2006.285.21:50:13.50#ibcon#read 4, iclass 5, count 0 2006.285.21:50:13.50#ibcon#about to read 5, iclass 5, count 0 2006.285.21:50:13.50#ibcon#read 5, iclass 5, count 0 2006.285.21:50:13.50#ibcon#about to read 6, iclass 5, count 0 2006.285.21:50:13.50#ibcon#read 6, iclass 5, count 0 2006.285.21:50:13.50#ibcon#end of sib2, iclass 5, count 0 2006.285.21:50:13.50#ibcon#*mode == 0, iclass 5, count 0 2006.285.21:50:13.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.21:50:13.50#ibcon#[27=USB\r\n] 2006.285.21:50:13.50#ibcon#*before write, iclass 5, count 0 2006.285.21:50:13.50#ibcon#enter sib2, iclass 5, count 0 2006.285.21:50:13.50#ibcon#flushed, iclass 5, count 0 2006.285.21:50:13.50#ibcon#about to write, iclass 5, count 0 2006.285.21:50:13.50#ibcon#wrote, iclass 5, count 0 2006.285.21:50:13.50#ibcon#about to read 3, iclass 5, count 0 2006.285.21:50:13.53#ibcon#read 3, iclass 5, count 0 2006.285.21:50:13.53#ibcon#about to read 4, iclass 5, count 0 2006.285.21:50:13.53#ibcon#read 4, iclass 5, count 0 2006.285.21:50:13.53#ibcon#about to read 5, iclass 5, count 0 2006.285.21:50:13.53#ibcon#read 5, iclass 5, count 0 2006.285.21:50:13.53#ibcon#about to read 6, iclass 5, count 0 2006.285.21:50:13.53#ibcon#read 6, iclass 5, count 0 2006.285.21:50:13.53#ibcon#end of sib2, iclass 5, count 0 2006.285.21:50:13.53#ibcon#*after write, iclass 5, count 0 2006.285.21:50:13.53#ibcon#*before return 0, iclass 5, count 0 2006.285.21:50:13.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:50:13.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.21:50:13.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.21:50:13.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.21:50:13.53$vck44/vblo=4,679.99 2006.285.21:50:13.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.21:50:13.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.21:50:13.53#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:13.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:50:13.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:50:13.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:50:13.53#ibcon#enter wrdev, iclass 7, count 0 2006.285.21:50:13.53#ibcon#first serial, iclass 7, count 0 2006.285.21:50:13.53#ibcon#enter sib2, iclass 7, count 0 2006.285.21:50:13.53#ibcon#flushed, iclass 7, count 0 2006.285.21:50:13.53#ibcon#about to write, iclass 7, count 0 2006.285.21:50:13.53#ibcon#wrote, iclass 7, count 0 2006.285.21:50:13.53#ibcon#about to read 3, iclass 7, count 0 2006.285.21:50:13.55#ibcon#read 3, iclass 7, count 0 2006.285.21:50:13.55#ibcon#about to read 4, iclass 7, count 0 2006.285.21:50:13.55#ibcon#read 4, iclass 7, count 0 2006.285.21:50:13.55#ibcon#about to read 5, iclass 7, count 0 2006.285.21:50:13.55#ibcon#read 5, iclass 7, count 0 2006.285.21:50:13.55#ibcon#about to read 6, iclass 7, count 0 2006.285.21:50:13.55#ibcon#read 6, iclass 7, count 0 2006.285.21:50:13.55#ibcon#end of sib2, iclass 7, count 0 2006.285.21:50:13.55#ibcon#*mode == 0, iclass 7, count 0 2006.285.21:50:13.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.21:50:13.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:50:13.55#ibcon#*before write, iclass 7, count 0 2006.285.21:50:13.55#ibcon#enter sib2, iclass 7, count 0 2006.285.21:50:13.55#ibcon#flushed, iclass 7, count 0 2006.285.21:50:13.55#ibcon#about to write, iclass 7, count 0 2006.285.21:50:13.55#ibcon#wrote, iclass 7, count 0 2006.285.21:50:13.55#ibcon#about to read 3, iclass 7, count 0 2006.285.21:50:13.59#ibcon#read 3, iclass 7, count 0 2006.285.21:50:13.59#ibcon#about to read 4, iclass 7, count 0 2006.285.21:50:13.59#ibcon#read 4, iclass 7, count 0 2006.285.21:50:13.59#ibcon#about to read 5, iclass 7, count 0 2006.285.21:50:13.59#ibcon#read 5, iclass 7, count 0 2006.285.21:50:13.59#ibcon#about to read 6, iclass 7, count 0 2006.285.21:50:13.59#ibcon#read 6, iclass 7, count 0 2006.285.21:50:13.59#ibcon#end of sib2, iclass 7, count 0 2006.285.21:50:13.59#ibcon#*after write, iclass 7, count 0 2006.285.21:50:13.59#ibcon#*before return 0, iclass 7, count 0 2006.285.21:50:13.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:50:13.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.21:50:13.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.21:50:13.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.21:50:13.59$vck44/vb=4,5 2006.285.21:50:13.59#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.21:50:13.59#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.21:50:13.59#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:13.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:50:13.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:50:13.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:50:13.65#ibcon#enter wrdev, iclass 11, count 2 2006.285.21:50:13.65#ibcon#first serial, iclass 11, count 2 2006.285.21:50:13.65#ibcon#enter sib2, iclass 11, count 2 2006.285.21:50:13.65#ibcon#flushed, iclass 11, count 2 2006.285.21:50:13.65#ibcon#about to write, iclass 11, count 2 2006.285.21:50:13.65#ibcon#wrote, iclass 11, count 2 2006.285.21:50:13.65#ibcon#about to read 3, iclass 11, count 2 2006.285.21:50:13.67#ibcon#read 3, iclass 11, count 2 2006.285.21:50:13.67#ibcon#about to read 4, iclass 11, count 2 2006.285.21:50:13.67#ibcon#read 4, iclass 11, count 2 2006.285.21:50:13.67#ibcon#about to read 5, iclass 11, count 2 2006.285.21:50:13.67#ibcon#read 5, iclass 11, count 2 2006.285.21:50:13.67#ibcon#about to read 6, iclass 11, count 2 2006.285.21:50:13.67#ibcon#read 6, iclass 11, count 2 2006.285.21:50:13.67#ibcon#end of sib2, iclass 11, count 2 2006.285.21:50:13.67#ibcon#*mode == 0, iclass 11, count 2 2006.285.21:50:13.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.21:50:13.67#ibcon#[27=AT04-05\r\n] 2006.285.21:50:13.67#ibcon#*before write, iclass 11, count 2 2006.285.21:50:13.67#ibcon#enter sib2, iclass 11, count 2 2006.285.21:50:13.67#ibcon#flushed, iclass 11, count 2 2006.285.21:50:13.67#ibcon#about to write, iclass 11, count 2 2006.285.21:50:13.67#ibcon#wrote, iclass 11, count 2 2006.285.21:50:13.67#ibcon#about to read 3, iclass 11, count 2 2006.285.21:50:13.70#ibcon#read 3, iclass 11, count 2 2006.285.21:50:13.70#ibcon#about to read 4, iclass 11, count 2 2006.285.21:50:13.70#ibcon#read 4, iclass 11, count 2 2006.285.21:50:13.70#ibcon#about to read 5, iclass 11, count 2 2006.285.21:50:13.70#ibcon#read 5, iclass 11, count 2 2006.285.21:50:13.70#ibcon#about to read 6, iclass 11, count 2 2006.285.21:50:13.70#ibcon#read 6, iclass 11, count 2 2006.285.21:50:13.70#ibcon#end of sib2, iclass 11, count 2 2006.285.21:50:13.70#ibcon#*after write, iclass 11, count 2 2006.285.21:50:13.70#ibcon#*before return 0, iclass 11, count 2 2006.285.21:50:13.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:50:13.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.21:50:13.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.21:50:13.70#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:13.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:50:13.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:50:13.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:50:13.82#ibcon#enter wrdev, iclass 11, count 0 2006.285.21:50:13.82#ibcon#first serial, iclass 11, count 0 2006.285.21:50:13.82#ibcon#enter sib2, iclass 11, count 0 2006.285.21:50:13.82#ibcon#flushed, iclass 11, count 0 2006.285.21:50:13.82#ibcon#about to write, iclass 11, count 0 2006.285.21:50:13.82#ibcon#wrote, iclass 11, count 0 2006.285.21:50:13.82#ibcon#about to read 3, iclass 11, count 0 2006.285.21:50:13.84#ibcon#read 3, iclass 11, count 0 2006.285.21:50:13.84#ibcon#about to read 4, iclass 11, count 0 2006.285.21:50:13.84#ibcon#read 4, iclass 11, count 0 2006.285.21:50:13.84#ibcon#about to read 5, iclass 11, count 0 2006.285.21:50:13.84#ibcon#read 5, iclass 11, count 0 2006.285.21:50:13.84#ibcon#about to read 6, iclass 11, count 0 2006.285.21:50:13.84#ibcon#read 6, iclass 11, count 0 2006.285.21:50:13.84#ibcon#end of sib2, iclass 11, count 0 2006.285.21:50:13.84#ibcon#*mode == 0, iclass 11, count 0 2006.285.21:50:13.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.21:50:13.84#ibcon#[27=USB\r\n] 2006.285.21:50:13.84#ibcon#*before write, iclass 11, count 0 2006.285.21:50:13.84#ibcon#enter sib2, iclass 11, count 0 2006.285.21:50:13.84#ibcon#flushed, iclass 11, count 0 2006.285.21:50:13.84#ibcon#about to write, iclass 11, count 0 2006.285.21:50:13.84#ibcon#wrote, iclass 11, count 0 2006.285.21:50:13.84#ibcon#about to read 3, iclass 11, count 0 2006.285.21:50:13.87#ibcon#read 3, iclass 11, count 0 2006.285.21:50:13.87#ibcon#about to read 4, iclass 11, count 0 2006.285.21:50:13.87#ibcon#read 4, iclass 11, count 0 2006.285.21:50:13.87#ibcon#about to read 5, iclass 11, count 0 2006.285.21:50:13.87#ibcon#read 5, iclass 11, count 0 2006.285.21:50:13.87#ibcon#about to read 6, iclass 11, count 0 2006.285.21:50:13.87#ibcon#read 6, iclass 11, count 0 2006.285.21:50:13.87#ibcon#end of sib2, iclass 11, count 0 2006.285.21:50:13.87#ibcon#*after write, iclass 11, count 0 2006.285.21:50:13.87#ibcon#*before return 0, iclass 11, count 0 2006.285.21:50:13.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:50:13.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.21:50:13.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.21:50:13.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.21:50:13.87$vck44/vblo=5,709.99 2006.285.21:50:13.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.21:50:13.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.21:50:13.87#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:13.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:50:13.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:50:13.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:50:13.87#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:50:13.87#ibcon#first serial, iclass 14, count 0 2006.285.21:50:13.87#ibcon#enter sib2, iclass 14, count 0 2006.285.21:50:13.87#ibcon#flushed, iclass 14, count 0 2006.285.21:50:13.87#ibcon#about to write, iclass 14, count 0 2006.285.21:50:13.87#ibcon#wrote, iclass 14, count 0 2006.285.21:50:13.87#ibcon#about to read 3, iclass 14, count 0 2006.285.21:50:13.89#ibcon#read 3, iclass 14, count 0 2006.285.21:50:13.89#ibcon#about to read 4, iclass 14, count 0 2006.285.21:50:13.89#ibcon#read 4, iclass 14, count 0 2006.285.21:50:13.89#ibcon#about to read 5, iclass 14, count 0 2006.285.21:50:13.89#ibcon#read 5, iclass 14, count 0 2006.285.21:50:13.89#ibcon#about to read 6, iclass 14, count 0 2006.285.21:50:13.89#ibcon#read 6, iclass 14, count 0 2006.285.21:50:13.89#ibcon#end of sib2, iclass 14, count 0 2006.285.21:50:13.89#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:50:13.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:50:13.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:50:13.89#ibcon#*before write, iclass 14, count 0 2006.285.21:50:13.89#ibcon#enter sib2, iclass 14, count 0 2006.285.21:50:13.89#ibcon#flushed, iclass 14, count 0 2006.285.21:50:13.89#ibcon#about to write, iclass 14, count 0 2006.285.21:50:13.89#ibcon#wrote, iclass 14, count 0 2006.285.21:50:13.89#ibcon#about to read 3, iclass 14, count 0 2006.285.21:50:13.89#abcon#<5=/15 0.7 1.2 15.331001015.9\r\n> 2006.285.21:50:13.91#abcon#{5=INTERFACE CLEAR} 2006.285.21:50:13.93#ibcon#read 3, iclass 14, count 0 2006.285.21:50:13.93#ibcon#about to read 4, iclass 14, count 0 2006.285.21:50:13.93#ibcon#read 4, iclass 14, count 0 2006.285.21:50:13.93#ibcon#about to read 5, iclass 14, count 0 2006.285.21:50:13.93#ibcon#read 5, iclass 14, count 0 2006.285.21:50:13.93#ibcon#about to read 6, iclass 14, count 0 2006.285.21:50:13.93#ibcon#read 6, iclass 14, count 0 2006.285.21:50:13.93#ibcon#end of sib2, iclass 14, count 0 2006.285.21:50:13.93#ibcon#*after write, iclass 14, count 0 2006.285.21:50:13.93#ibcon#*before return 0, iclass 14, count 0 2006.285.21:50:13.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:50:13.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.21:50:13.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:50:13.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:50:13.93$vck44/vb=5,4 2006.285.21:50:13.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.21:50:13.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.21:50:13.93#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:13.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:50:13.97#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:50:13.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:50:13.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:50:13.99#ibcon#enter wrdev, iclass 18, count 2 2006.285.21:50:13.99#ibcon#first serial, iclass 18, count 2 2006.285.21:50:13.99#ibcon#enter sib2, iclass 18, count 2 2006.285.21:50:13.99#ibcon#flushed, iclass 18, count 2 2006.285.21:50:13.99#ibcon#about to write, iclass 18, count 2 2006.285.21:50:13.99#ibcon#wrote, iclass 18, count 2 2006.285.21:50:13.99#ibcon#about to read 3, iclass 18, count 2 2006.285.21:50:14.01#ibcon#read 3, iclass 18, count 2 2006.285.21:50:14.01#ibcon#about to read 4, iclass 18, count 2 2006.285.21:50:14.01#ibcon#read 4, iclass 18, count 2 2006.285.21:50:14.01#ibcon#about to read 5, iclass 18, count 2 2006.285.21:50:14.01#ibcon#read 5, iclass 18, count 2 2006.285.21:50:14.01#ibcon#about to read 6, iclass 18, count 2 2006.285.21:50:14.01#ibcon#read 6, iclass 18, count 2 2006.285.21:50:14.01#ibcon#end of sib2, iclass 18, count 2 2006.285.21:50:14.01#ibcon#*mode == 0, iclass 18, count 2 2006.285.21:50:14.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.21:50:14.01#ibcon#[27=AT05-04\r\n] 2006.285.21:50:14.01#ibcon#*before write, iclass 18, count 2 2006.285.21:50:14.01#ibcon#enter sib2, iclass 18, count 2 2006.285.21:50:14.01#ibcon#flushed, iclass 18, count 2 2006.285.21:50:14.01#ibcon#about to write, iclass 18, count 2 2006.285.21:50:14.01#ibcon#wrote, iclass 18, count 2 2006.285.21:50:14.01#ibcon#about to read 3, iclass 18, count 2 2006.285.21:50:14.04#ibcon#read 3, iclass 18, count 2 2006.285.21:50:14.04#ibcon#about to read 4, iclass 18, count 2 2006.285.21:50:14.04#ibcon#read 4, iclass 18, count 2 2006.285.21:50:14.04#ibcon#about to read 5, iclass 18, count 2 2006.285.21:50:14.04#ibcon#read 5, iclass 18, count 2 2006.285.21:50:14.04#ibcon#about to read 6, iclass 18, count 2 2006.285.21:50:14.04#ibcon#read 6, iclass 18, count 2 2006.285.21:50:14.04#ibcon#end of sib2, iclass 18, count 2 2006.285.21:50:14.04#ibcon#*after write, iclass 18, count 2 2006.285.21:50:14.04#ibcon#*before return 0, iclass 18, count 2 2006.285.21:50:14.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:50:14.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:50:14.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.21:50:14.04#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:14.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:50:14.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:50:14.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:50:14.16#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:50:14.16#ibcon#first serial, iclass 18, count 0 2006.285.21:50:14.16#ibcon#enter sib2, iclass 18, count 0 2006.285.21:50:14.16#ibcon#flushed, iclass 18, count 0 2006.285.21:50:14.16#ibcon#about to write, iclass 18, count 0 2006.285.21:50:14.16#ibcon#wrote, iclass 18, count 0 2006.285.21:50:14.16#ibcon#about to read 3, iclass 18, count 0 2006.285.21:50:14.18#ibcon#read 3, iclass 18, count 0 2006.285.21:50:14.18#ibcon#about to read 4, iclass 18, count 0 2006.285.21:50:14.18#ibcon#read 4, iclass 18, count 0 2006.285.21:50:14.18#ibcon#about to read 5, iclass 18, count 0 2006.285.21:50:14.18#ibcon#read 5, iclass 18, count 0 2006.285.21:50:14.18#ibcon#about to read 6, iclass 18, count 0 2006.285.21:50:14.18#ibcon#read 6, iclass 18, count 0 2006.285.21:50:14.18#ibcon#end of sib2, iclass 18, count 0 2006.285.21:50:14.18#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:50:14.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:50:14.18#ibcon#[27=USB\r\n] 2006.285.21:50:14.18#ibcon#*before write, iclass 18, count 0 2006.285.21:50:14.18#ibcon#enter sib2, iclass 18, count 0 2006.285.21:50:14.18#ibcon#flushed, iclass 18, count 0 2006.285.21:50:14.18#ibcon#about to write, iclass 18, count 0 2006.285.21:50:14.18#ibcon#wrote, iclass 18, count 0 2006.285.21:50:14.18#ibcon#about to read 3, iclass 18, count 0 2006.285.21:50:14.21#ibcon#read 3, iclass 18, count 0 2006.285.21:50:14.21#ibcon#about to read 4, iclass 18, count 0 2006.285.21:50:14.21#ibcon#read 4, iclass 18, count 0 2006.285.21:50:14.21#ibcon#about to read 5, iclass 18, count 0 2006.285.21:50:14.21#ibcon#read 5, iclass 18, count 0 2006.285.21:50:14.21#ibcon#about to read 6, iclass 18, count 0 2006.285.21:50:14.21#ibcon#read 6, iclass 18, count 0 2006.285.21:50:14.21#ibcon#end of sib2, iclass 18, count 0 2006.285.21:50:14.21#ibcon#*after write, iclass 18, count 0 2006.285.21:50:14.21#ibcon#*before return 0, iclass 18, count 0 2006.285.21:50:14.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:50:14.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:50:14.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:50:14.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:50:14.21$vck44/vblo=6,719.99 2006.285.21:50:14.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.21:50:14.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.21:50:14.21#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:14.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:50:14.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:50:14.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:50:14.21#ibcon#enter wrdev, iclass 21, count 0 2006.285.21:50:14.21#ibcon#first serial, iclass 21, count 0 2006.285.21:50:14.21#ibcon#enter sib2, iclass 21, count 0 2006.285.21:50:14.21#ibcon#flushed, iclass 21, count 0 2006.285.21:50:14.21#ibcon#about to write, iclass 21, count 0 2006.285.21:50:14.21#ibcon#wrote, iclass 21, count 0 2006.285.21:50:14.21#ibcon#about to read 3, iclass 21, count 0 2006.285.21:50:14.23#ibcon#read 3, iclass 21, count 0 2006.285.21:50:14.23#ibcon#about to read 4, iclass 21, count 0 2006.285.21:50:14.23#ibcon#read 4, iclass 21, count 0 2006.285.21:50:14.23#ibcon#about to read 5, iclass 21, count 0 2006.285.21:50:14.23#ibcon#read 5, iclass 21, count 0 2006.285.21:50:14.23#ibcon#about to read 6, iclass 21, count 0 2006.285.21:50:14.23#ibcon#read 6, iclass 21, count 0 2006.285.21:50:14.23#ibcon#end of sib2, iclass 21, count 0 2006.285.21:50:14.23#ibcon#*mode == 0, iclass 21, count 0 2006.285.21:50:14.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.21:50:14.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:50:14.23#ibcon#*before write, iclass 21, count 0 2006.285.21:50:14.23#ibcon#enter sib2, iclass 21, count 0 2006.285.21:50:14.23#ibcon#flushed, iclass 21, count 0 2006.285.21:50:14.23#ibcon#about to write, iclass 21, count 0 2006.285.21:50:14.23#ibcon#wrote, iclass 21, count 0 2006.285.21:50:14.23#ibcon#about to read 3, iclass 21, count 0 2006.285.21:50:14.27#ibcon#read 3, iclass 21, count 0 2006.285.21:50:14.27#ibcon#about to read 4, iclass 21, count 0 2006.285.21:50:14.27#ibcon#read 4, iclass 21, count 0 2006.285.21:50:14.27#ibcon#about to read 5, iclass 21, count 0 2006.285.21:50:14.27#ibcon#read 5, iclass 21, count 0 2006.285.21:50:14.27#ibcon#about to read 6, iclass 21, count 0 2006.285.21:50:14.27#ibcon#read 6, iclass 21, count 0 2006.285.21:50:14.27#ibcon#end of sib2, iclass 21, count 0 2006.285.21:50:14.27#ibcon#*after write, iclass 21, count 0 2006.285.21:50:14.27#ibcon#*before return 0, iclass 21, count 0 2006.285.21:50:14.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:50:14.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.21:50:14.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.21:50:14.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.21:50:14.27$vck44/vb=6,3 2006.285.21:50:14.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.21:50:14.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.21:50:14.27#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:14.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:50:14.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:50:14.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:50:14.33#ibcon#enter wrdev, iclass 23, count 2 2006.285.21:50:14.33#ibcon#first serial, iclass 23, count 2 2006.285.21:50:14.33#ibcon#enter sib2, iclass 23, count 2 2006.285.21:50:14.33#ibcon#flushed, iclass 23, count 2 2006.285.21:50:14.33#ibcon#about to write, iclass 23, count 2 2006.285.21:50:14.33#ibcon#wrote, iclass 23, count 2 2006.285.21:50:14.33#ibcon#about to read 3, iclass 23, count 2 2006.285.21:50:14.35#ibcon#read 3, iclass 23, count 2 2006.285.21:50:14.35#ibcon#about to read 4, iclass 23, count 2 2006.285.21:50:14.35#ibcon#read 4, iclass 23, count 2 2006.285.21:50:14.35#ibcon#about to read 5, iclass 23, count 2 2006.285.21:50:14.35#ibcon#read 5, iclass 23, count 2 2006.285.21:50:14.35#ibcon#about to read 6, iclass 23, count 2 2006.285.21:50:14.35#ibcon#read 6, iclass 23, count 2 2006.285.21:50:14.35#ibcon#end of sib2, iclass 23, count 2 2006.285.21:50:14.35#ibcon#*mode == 0, iclass 23, count 2 2006.285.21:50:14.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.21:50:14.35#ibcon#[27=AT06-03\r\n] 2006.285.21:50:14.35#ibcon#*before write, iclass 23, count 2 2006.285.21:50:14.35#ibcon#enter sib2, iclass 23, count 2 2006.285.21:50:14.35#ibcon#flushed, iclass 23, count 2 2006.285.21:50:14.35#ibcon#about to write, iclass 23, count 2 2006.285.21:50:14.35#ibcon#wrote, iclass 23, count 2 2006.285.21:50:14.35#ibcon#about to read 3, iclass 23, count 2 2006.285.21:50:14.38#ibcon#read 3, iclass 23, count 2 2006.285.21:50:14.38#ibcon#about to read 4, iclass 23, count 2 2006.285.21:50:14.38#ibcon#read 4, iclass 23, count 2 2006.285.21:50:14.38#ibcon#about to read 5, iclass 23, count 2 2006.285.21:50:14.38#ibcon#read 5, iclass 23, count 2 2006.285.21:50:14.38#ibcon#about to read 6, iclass 23, count 2 2006.285.21:50:14.38#ibcon#read 6, iclass 23, count 2 2006.285.21:50:14.38#ibcon#end of sib2, iclass 23, count 2 2006.285.21:50:14.38#ibcon#*after write, iclass 23, count 2 2006.285.21:50:14.38#ibcon#*before return 0, iclass 23, count 2 2006.285.21:50:14.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:50:14.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:50:14.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.21:50:14.38#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:14.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:50:14.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:50:14.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:50:14.50#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:50:14.50#ibcon#first serial, iclass 23, count 0 2006.285.21:50:14.50#ibcon#enter sib2, iclass 23, count 0 2006.285.21:50:14.50#ibcon#flushed, iclass 23, count 0 2006.285.21:50:14.50#ibcon#about to write, iclass 23, count 0 2006.285.21:50:14.50#ibcon#wrote, iclass 23, count 0 2006.285.21:50:14.50#ibcon#about to read 3, iclass 23, count 0 2006.285.21:50:14.52#ibcon#read 3, iclass 23, count 0 2006.285.21:50:14.52#ibcon#about to read 4, iclass 23, count 0 2006.285.21:50:14.52#ibcon#read 4, iclass 23, count 0 2006.285.21:50:14.52#ibcon#about to read 5, iclass 23, count 0 2006.285.21:50:14.52#ibcon#read 5, iclass 23, count 0 2006.285.21:50:14.52#ibcon#about to read 6, iclass 23, count 0 2006.285.21:50:14.52#ibcon#read 6, iclass 23, count 0 2006.285.21:50:14.52#ibcon#end of sib2, iclass 23, count 0 2006.285.21:50:14.52#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:50:14.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:50:14.52#ibcon#[27=USB\r\n] 2006.285.21:50:14.52#ibcon#*before write, iclass 23, count 0 2006.285.21:50:14.52#ibcon#enter sib2, iclass 23, count 0 2006.285.21:50:14.52#ibcon#flushed, iclass 23, count 0 2006.285.21:50:14.52#ibcon#about to write, iclass 23, count 0 2006.285.21:50:14.52#ibcon#wrote, iclass 23, count 0 2006.285.21:50:14.52#ibcon#about to read 3, iclass 23, count 0 2006.285.21:50:14.55#ibcon#read 3, iclass 23, count 0 2006.285.21:50:14.55#ibcon#about to read 4, iclass 23, count 0 2006.285.21:50:14.55#ibcon#read 4, iclass 23, count 0 2006.285.21:50:14.55#ibcon#about to read 5, iclass 23, count 0 2006.285.21:50:14.55#ibcon#read 5, iclass 23, count 0 2006.285.21:50:14.55#ibcon#about to read 6, iclass 23, count 0 2006.285.21:50:14.55#ibcon#read 6, iclass 23, count 0 2006.285.21:50:14.55#ibcon#end of sib2, iclass 23, count 0 2006.285.21:50:14.55#ibcon#*after write, iclass 23, count 0 2006.285.21:50:14.55#ibcon#*before return 0, iclass 23, count 0 2006.285.21:50:14.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:50:14.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:50:14.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:50:14.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:50:14.55$vck44/vblo=7,734.99 2006.285.21:50:14.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.21:50:14.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.21:50:14.55#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:14.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:50:14.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:50:14.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:50:14.55#ibcon#enter wrdev, iclass 25, count 0 2006.285.21:50:14.55#ibcon#first serial, iclass 25, count 0 2006.285.21:50:14.55#ibcon#enter sib2, iclass 25, count 0 2006.285.21:50:14.55#ibcon#flushed, iclass 25, count 0 2006.285.21:50:14.55#ibcon#about to write, iclass 25, count 0 2006.285.21:50:14.55#ibcon#wrote, iclass 25, count 0 2006.285.21:50:14.55#ibcon#about to read 3, iclass 25, count 0 2006.285.21:50:14.57#ibcon#read 3, iclass 25, count 0 2006.285.21:50:14.57#ibcon#about to read 4, iclass 25, count 0 2006.285.21:50:14.57#ibcon#read 4, iclass 25, count 0 2006.285.21:50:14.57#ibcon#about to read 5, iclass 25, count 0 2006.285.21:50:14.57#ibcon#read 5, iclass 25, count 0 2006.285.21:50:14.57#ibcon#about to read 6, iclass 25, count 0 2006.285.21:50:14.57#ibcon#read 6, iclass 25, count 0 2006.285.21:50:14.57#ibcon#end of sib2, iclass 25, count 0 2006.285.21:50:14.57#ibcon#*mode == 0, iclass 25, count 0 2006.285.21:50:14.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.21:50:14.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:50:14.57#ibcon#*before write, iclass 25, count 0 2006.285.21:50:14.57#ibcon#enter sib2, iclass 25, count 0 2006.285.21:50:14.57#ibcon#flushed, iclass 25, count 0 2006.285.21:50:14.57#ibcon#about to write, iclass 25, count 0 2006.285.21:50:14.57#ibcon#wrote, iclass 25, count 0 2006.285.21:50:14.57#ibcon#about to read 3, iclass 25, count 0 2006.285.21:50:14.61#ibcon#read 3, iclass 25, count 0 2006.285.21:50:14.61#ibcon#about to read 4, iclass 25, count 0 2006.285.21:50:14.61#ibcon#read 4, iclass 25, count 0 2006.285.21:50:14.61#ibcon#about to read 5, iclass 25, count 0 2006.285.21:50:14.61#ibcon#read 5, iclass 25, count 0 2006.285.21:50:14.61#ibcon#about to read 6, iclass 25, count 0 2006.285.21:50:14.61#ibcon#read 6, iclass 25, count 0 2006.285.21:50:14.61#ibcon#end of sib2, iclass 25, count 0 2006.285.21:50:14.61#ibcon#*after write, iclass 25, count 0 2006.285.21:50:14.61#ibcon#*before return 0, iclass 25, count 0 2006.285.21:50:14.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:50:14.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.21:50:14.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.21:50:14.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.21:50:14.61$vck44/vb=7,4 2006.285.21:50:14.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.21:50:14.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.21:50:14.61#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:14.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:50:14.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:50:14.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:50:14.67#ibcon#enter wrdev, iclass 27, count 2 2006.285.21:50:14.67#ibcon#first serial, iclass 27, count 2 2006.285.21:50:14.67#ibcon#enter sib2, iclass 27, count 2 2006.285.21:50:14.67#ibcon#flushed, iclass 27, count 2 2006.285.21:50:14.67#ibcon#about to write, iclass 27, count 2 2006.285.21:50:14.67#ibcon#wrote, iclass 27, count 2 2006.285.21:50:14.67#ibcon#about to read 3, iclass 27, count 2 2006.285.21:50:14.69#ibcon#read 3, iclass 27, count 2 2006.285.21:50:14.69#ibcon#about to read 4, iclass 27, count 2 2006.285.21:50:14.69#ibcon#read 4, iclass 27, count 2 2006.285.21:50:14.69#ibcon#about to read 5, iclass 27, count 2 2006.285.21:50:14.69#ibcon#read 5, iclass 27, count 2 2006.285.21:50:14.69#ibcon#about to read 6, iclass 27, count 2 2006.285.21:50:14.69#ibcon#read 6, iclass 27, count 2 2006.285.21:50:14.69#ibcon#end of sib2, iclass 27, count 2 2006.285.21:50:14.69#ibcon#*mode == 0, iclass 27, count 2 2006.285.21:50:14.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.21:50:14.69#ibcon#[27=AT07-04\r\n] 2006.285.21:50:14.69#ibcon#*before write, iclass 27, count 2 2006.285.21:50:14.69#ibcon#enter sib2, iclass 27, count 2 2006.285.21:50:14.69#ibcon#flushed, iclass 27, count 2 2006.285.21:50:14.69#ibcon#about to write, iclass 27, count 2 2006.285.21:50:14.69#ibcon#wrote, iclass 27, count 2 2006.285.21:50:14.69#ibcon#about to read 3, iclass 27, count 2 2006.285.21:50:14.72#ibcon#read 3, iclass 27, count 2 2006.285.21:50:14.72#ibcon#about to read 4, iclass 27, count 2 2006.285.21:50:14.72#ibcon#read 4, iclass 27, count 2 2006.285.21:50:14.72#ibcon#about to read 5, iclass 27, count 2 2006.285.21:50:14.72#ibcon#read 5, iclass 27, count 2 2006.285.21:50:14.72#ibcon#about to read 6, iclass 27, count 2 2006.285.21:50:14.72#ibcon#read 6, iclass 27, count 2 2006.285.21:50:14.72#ibcon#end of sib2, iclass 27, count 2 2006.285.21:50:14.72#ibcon#*after write, iclass 27, count 2 2006.285.21:50:14.72#ibcon#*before return 0, iclass 27, count 2 2006.285.21:50:14.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:50:14.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.21:50:14.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.21:50:14.72#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:14.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:50:14.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:50:14.97#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:50:14.97#ibcon#enter wrdev, iclass 27, count 0 2006.285.21:50:14.97#ibcon#first serial, iclass 27, count 0 2006.285.21:50:14.97#ibcon#enter sib2, iclass 27, count 0 2006.285.21:50:14.97#ibcon#flushed, iclass 27, count 0 2006.285.21:50:14.97#ibcon#about to write, iclass 27, count 0 2006.285.21:50:14.97#ibcon#wrote, iclass 27, count 0 2006.285.21:50:14.97#ibcon#about to read 3, iclass 27, count 0 2006.285.21:50:14.99#ibcon#read 3, iclass 27, count 0 2006.285.21:50:14.99#ibcon#about to read 4, iclass 27, count 0 2006.285.21:50:14.99#ibcon#read 4, iclass 27, count 0 2006.285.21:50:14.99#ibcon#about to read 5, iclass 27, count 0 2006.285.21:50:14.99#ibcon#read 5, iclass 27, count 0 2006.285.21:50:14.99#ibcon#about to read 6, iclass 27, count 0 2006.285.21:50:14.99#ibcon#read 6, iclass 27, count 0 2006.285.21:50:14.99#ibcon#end of sib2, iclass 27, count 0 2006.285.21:50:14.99#ibcon#*mode == 0, iclass 27, count 0 2006.285.21:50:14.99#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.21:50:14.99#ibcon#[27=USB\r\n] 2006.285.21:50:14.99#ibcon#*before write, iclass 27, count 0 2006.285.21:50:14.99#ibcon#enter sib2, iclass 27, count 0 2006.285.21:50:14.99#ibcon#flushed, iclass 27, count 0 2006.285.21:50:14.99#ibcon#about to write, iclass 27, count 0 2006.285.21:50:14.99#ibcon#wrote, iclass 27, count 0 2006.285.21:50:14.99#ibcon#about to read 3, iclass 27, count 0 2006.285.21:50:15.02#ibcon#read 3, iclass 27, count 0 2006.285.21:50:15.02#ibcon#about to read 4, iclass 27, count 0 2006.285.21:50:15.02#ibcon#read 4, iclass 27, count 0 2006.285.21:50:15.02#ibcon#about to read 5, iclass 27, count 0 2006.285.21:50:15.02#ibcon#read 5, iclass 27, count 0 2006.285.21:50:15.02#ibcon#about to read 6, iclass 27, count 0 2006.285.21:50:15.02#ibcon#read 6, iclass 27, count 0 2006.285.21:50:15.02#ibcon#end of sib2, iclass 27, count 0 2006.285.21:50:15.02#ibcon#*after write, iclass 27, count 0 2006.285.21:50:15.02#ibcon#*before return 0, iclass 27, count 0 2006.285.21:50:15.02#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:50:15.02#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.21:50:15.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.21:50:15.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.21:50:15.02$vck44/vblo=8,744.99 2006.285.21:50:15.02#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.21:50:15.02#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.21:50:15.02#ibcon#ireg 17 cls_cnt 0 2006.285.21:50:15.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:50:15.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:50:15.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:50:15.02#ibcon#enter wrdev, iclass 29, count 0 2006.285.21:50:15.02#ibcon#first serial, iclass 29, count 0 2006.285.21:50:15.02#ibcon#enter sib2, iclass 29, count 0 2006.285.21:50:15.02#ibcon#flushed, iclass 29, count 0 2006.285.21:50:15.02#ibcon#about to write, iclass 29, count 0 2006.285.21:50:15.02#ibcon#wrote, iclass 29, count 0 2006.285.21:50:15.02#ibcon#about to read 3, iclass 29, count 0 2006.285.21:50:15.04#ibcon#read 3, iclass 29, count 0 2006.285.21:50:15.04#ibcon#about to read 4, iclass 29, count 0 2006.285.21:50:15.04#ibcon#read 4, iclass 29, count 0 2006.285.21:50:15.04#ibcon#about to read 5, iclass 29, count 0 2006.285.21:50:15.04#ibcon#read 5, iclass 29, count 0 2006.285.21:50:15.04#ibcon#about to read 6, iclass 29, count 0 2006.285.21:50:15.04#ibcon#read 6, iclass 29, count 0 2006.285.21:50:15.04#ibcon#end of sib2, iclass 29, count 0 2006.285.21:50:15.04#ibcon#*mode == 0, iclass 29, count 0 2006.285.21:50:15.04#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.21:50:15.04#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:50:15.04#ibcon#*before write, iclass 29, count 0 2006.285.21:50:15.04#ibcon#enter sib2, iclass 29, count 0 2006.285.21:50:15.04#ibcon#flushed, iclass 29, count 0 2006.285.21:50:15.04#ibcon#about to write, iclass 29, count 0 2006.285.21:50:15.04#ibcon#wrote, iclass 29, count 0 2006.285.21:50:15.04#ibcon#about to read 3, iclass 29, count 0 2006.285.21:50:15.08#ibcon#read 3, iclass 29, count 0 2006.285.21:50:15.08#ibcon#about to read 4, iclass 29, count 0 2006.285.21:50:15.08#ibcon#read 4, iclass 29, count 0 2006.285.21:50:15.08#ibcon#about to read 5, iclass 29, count 0 2006.285.21:50:15.08#ibcon#read 5, iclass 29, count 0 2006.285.21:50:15.08#ibcon#about to read 6, iclass 29, count 0 2006.285.21:50:15.08#ibcon#read 6, iclass 29, count 0 2006.285.21:50:15.08#ibcon#end of sib2, iclass 29, count 0 2006.285.21:50:15.08#ibcon#*after write, iclass 29, count 0 2006.285.21:50:15.08#ibcon#*before return 0, iclass 29, count 0 2006.285.21:50:15.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:50:15.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.21:50:15.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.21:50:15.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.21:50:15.08$vck44/vb=8,4 2006.285.21:50:15.08#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.21:50:15.08#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.21:50:15.08#ibcon#ireg 11 cls_cnt 2 2006.285.21:50:15.08#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:50:15.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:50:15.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:50:15.14#ibcon#enter wrdev, iclass 31, count 2 2006.285.21:50:15.14#ibcon#first serial, iclass 31, count 2 2006.285.21:50:15.14#ibcon#enter sib2, iclass 31, count 2 2006.285.21:50:15.14#ibcon#flushed, iclass 31, count 2 2006.285.21:50:15.14#ibcon#about to write, iclass 31, count 2 2006.285.21:50:15.14#ibcon#wrote, iclass 31, count 2 2006.285.21:50:15.14#ibcon#about to read 3, iclass 31, count 2 2006.285.21:50:15.16#ibcon#read 3, iclass 31, count 2 2006.285.21:50:15.16#ibcon#about to read 4, iclass 31, count 2 2006.285.21:50:15.16#ibcon#read 4, iclass 31, count 2 2006.285.21:50:15.16#ibcon#about to read 5, iclass 31, count 2 2006.285.21:50:15.16#ibcon#read 5, iclass 31, count 2 2006.285.21:50:15.16#ibcon#about to read 6, iclass 31, count 2 2006.285.21:50:15.16#ibcon#read 6, iclass 31, count 2 2006.285.21:50:15.16#ibcon#end of sib2, iclass 31, count 2 2006.285.21:50:15.16#ibcon#*mode == 0, iclass 31, count 2 2006.285.21:50:15.16#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.21:50:15.16#ibcon#[27=AT08-04\r\n] 2006.285.21:50:15.16#ibcon#*before write, iclass 31, count 2 2006.285.21:50:15.16#ibcon#enter sib2, iclass 31, count 2 2006.285.21:50:15.16#ibcon#flushed, iclass 31, count 2 2006.285.21:50:15.16#ibcon#about to write, iclass 31, count 2 2006.285.21:50:15.16#ibcon#wrote, iclass 31, count 2 2006.285.21:50:15.16#ibcon#about to read 3, iclass 31, count 2 2006.285.21:50:15.19#ibcon#read 3, iclass 31, count 2 2006.285.21:50:15.19#ibcon#about to read 4, iclass 31, count 2 2006.285.21:50:15.19#ibcon#read 4, iclass 31, count 2 2006.285.21:50:15.19#ibcon#about to read 5, iclass 31, count 2 2006.285.21:50:15.19#ibcon#read 5, iclass 31, count 2 2006.285.21:50:15.19#ibcon#about to read 6, iclass 31, count 2 2006.285.21:50:15.19#ibcon#read 6, iclass 31, count 2 2006.285.21:50:15.19#ibcon#end of sib2, iclass 31, count 2 2006.285.21:50:15.19#ibcon#*after write, iclass 31, count 2 2006.285.21:50:15.19#ibcon#*before return 0, iclass 31, count 2 2006.285.21:50:15.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:50:15.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.21:50:15.19#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.21:50:15.19#ibcon#ireg 7 cls_cnt 0 2006.285.21:50:15.19#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:50:15.31#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:50:15.31#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:50:15.31#ibcon#enter wrdev, iclass 31, count 0 2006.285.21:50:15.31#ibcon#first serial, iclass 31, count 0 2006.285.21:50:15.31#ibcon#enter sib2, iclass 31, count 0 2006.285.21:50:15.31#ibcon#flushed, iclass 31, count 0 2006.285.21:50:15.31#ibcon#about to write, iclass 31, count 0 2006.285.21:50:15.31#ibcon#wrote, iclass 31, count 0 2006.285.21:50:15.31#ibcon#about to read 3, iclass 31, count 0 2006.285.21:50:15.33#ibcon#read 3, iclass 31, count 0 2006.285.21:50:15.33#ibcon#about to read 4, iclass 31, count 0 2006.285.21:50:15.33#ibcon#read 4, iclass 31, count 0 2006.285.21:50:15.33#ibcon#about to read 5, iclass 31, count 0 2006.285.21:50:15.33#ibcon#read 5, iclass 31, count 0 2006.285.21:50:15.33#ibcon#about to read 6, iclass 31, count 0 2006.285.21:50:15.33#ibcon#read 6, iclass 31, count 0 2006.285.21:50:15.33#ibcon#end of sib2, iclass 31, count 0 2006.285.21:50:15.33#ibcon#*mode == 0, iclass 31, count 0 2006.285.21:50:15.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.21:50:15.33#ibcon#[27=USB\r\n] 2006.285.21:50:15.33#ibcon#*before write, iclass 31, count 0 2006.285.21:50:15.33#ibcon#enter sib2, iclass 31, count 0 2006.285.21:50:15.33#ibcon#flushed, iclass 31, count 0 2006.285.21:50:15.33#ibcon#about to write, iclass 31, count 0 2006.285.21:50:15.33#ibcon#wrote, iclass 31, count 0 2006.285.21:50:15.33#ibcon#about to read 3, iclass 31, count 0 2006.285.21:50:15.36#ibcon#read 3, iclass 31, count 0 2006.285.21:50:15.36#ibcon#about to read 4, iclass 31, count 0 2006.285.21:50:15.36#ibcon#read 4, iclass 31, count 0 2006.285.21:50:15.36#ibcon#about to read 5, iclass 31, count 0 2006.285.21:50:15.36#ibcon#read 5, iclass 31, count 0 2006.285.21:50:15.36#ibcon#about to read 6, iclass 31, count 0 2006.285.21:50:15.36#ibcon#read 6, iclass 31, count 0 2006.285.21:50:15.36#ibcon#end of sib2, iclass 31, count 0 2006.285.21:50:15.36#ibcon#*after write, iclass 31, count 0 2006.285.21:50:15.36#ibcon#*before return 0, iclass 31, count 0 2006.285.21:50:15.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:50:15.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.21:50:15.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.21:50:15.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.21:50:15.36$vck44/vabw=wide 2006.285.21:50:15.36#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.21:50:15.36#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.21:50:15.36#ibcon#ireg 8 cls_cnt 0 2006.285.21:50:15.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:50:15.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:50:15.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:50:15.36#ibcon#enter wrdev, iclass 33, count 0 2006.285.21:50:15.36#ibcon#first serial, iclass 33, count 0 2006.285.21:50:15.36#ibcon#enter sib2, iclass 33, count 0 2006.285.21:50:15.36#ibcon#flushed, iclass 33, count 0 2006.285.21:50:15.36#ibcon#about to write, iclass 33, count 0 2006.285.21:50:15.36#ibcon#wrote, iclass 33, count 0 2006.285.21:50:15.36#ibcon#about to read 3, iclass 33, count 0 2006.285.21:50:15.38#ibcon#read 3, iclass 33, count 0 2006.285.21:50:15.38#ibcon#about to read 4, iclass 33, count 0 2006.285.21:50:15.38#ibcon#read 4, iclass 33, count 0 2006.285.21:50:15.38#ibcon#about to read 5, iclass 33, count 0 2006.285.21:50:15.38#ibcon#read 5, iclass 33, count 0 2006.285.21:50:15.38#ibcon#about to read 6, iclass 33, count 0 2006.285.21:50:15.38#ibcon#read 6, iclass 33, count 0 2006.285.21:50:15.38#ibcon#end of sib2, iclass 33, count 0 2006.285.21:50:15.38#ibcon#*mode == 0, iclass 33, count 0 2006.285.21:50:15.38#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.21:50:15.38#ibcon#[25=BW32\r\n] 2006.285.21:50:15.38#ibcon#*before write, iclass 33, count 0 2006.285.21:50:15.38#ibcon#enter sib2, iclass 33, count 0 2006.285.21:50:15.38#ibcon#flushed, iclass 33, count 0 2006.285.21:50:15.38#ibcon#about to write, iclass 33, count 0 2006.285.21:50:15.38#ibcon#wrote, iclass 33, count 0 2006.285.21:50:15.38#ibcon#about to read 3, iclass 33, count 0 2006.285.21:50:15.41#ibcon#read 3, iclass 33, count 0 2006.285.21:50:15.41#ibcon#about to read 4, iclass 33, count 0 2006.285.21:50:15.41#ibcon#read 4, iclass 33, count 0 2006.285.21:50:15.41#ibcon#about to read 5, iclass 33, count 0 2006.285.21:50:15.41#ibcon#read 5, iclass 33, count 0 2006.285.21:50:15.41#ibcon#about to read 6, iclass 33, count 0 2006.285.21:50:15.41#ibcon#read 6, iclass 33, count 0 2006.285.21:50:15.41#ibcon#end of sib2, iclass 33, count 0 2006.285.21:50:15.41#ibcon#*after write, iclass 33, count 0 2006.285.21:50:15.41#ibcon#*before return 0, iclass 33, count 0 2006.285.21:50:15.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:50:15.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.21:50:15.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.21:50:15.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.21:50:15.41$vck44/vbbw=wide 2006.285.21:50:15.41#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.21:50:15.41#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.21:50:15.41#ibcon#ireg 8 cls_cnt 0 2006.285.21:50:15.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:50:15.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:50:15.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:50:15.48#ibcon#enter wrdev, iclass 35, count 0 2006.285.21:50:15.48#ibcon#first serial, iclass 35, count 0 2006.285.21:50:15.48#ibcon#enter sib2, iclass 35, count 0 2006.285.21:50:15.48#ibcon#flushed, iclass 35, count 0 2006.285.21:50:15.48#ibcon#about to write, iclass 35, count 0 2006.285.21:50:15.48#ibcon#wrote, iclass 35, count 0 2006.285.21:50:15.48#ibcon#about to read 3, iclass 35, count 0 2006.285.21:50:15.50#ibcon#read 3, iclass 35, count 0 2006.285.21:50:15.50#ibcon#about to read 4, iclass 35, count 0 2006.285.21:50:15.50#ibcon#read 4, iclass 35, count 0 2006.285.21:50:15.50#ibcon#about to read 5, iclass 35, count 0 2006.285.21:50:15.50#ibcon#read 5, iclass 35, count 0 2006.285.21:50:15.50#ibcon#about to read 6, iclass 35, count 0 2006.285.21:50:15.50#ibcon#read 6, iclass 35, count 0 2006.285.21:50:15.50#ibcon#end of sib2, iclass 35, count 0 2006.285.21:50:15.50#ibcon#*mode == 0, iclass 35, count 0 2006.285.21:50:15.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.21:50:15.50#ibcon#[27=BW32\r\n] 2006.285.21:50:15.50#ibcon#*before write, iclass 35, count 0 2006.285.21:50:15.50#ibcon#enter sib2, iclass 35, count 0 2006.285.21:50:15.50#ibcon#flushed, iclass 35, count 0 2006.285.21:50:15.50#ibcon#about to write, iclass 35, count 0 2006.285.21:50:15.50#ibcon#wrote, iclass 35, count 0 2006.285.21:50:15.50#ibcon#about to read 3, iclass 35, count 0 2006.285.21:50:15.53#ibcon#read 3, iclass 35, count 0 2006.285.21:50:15.53#ibcon#about to read 4, iclass 35, count 0 2006.285.21:50:15.53#ibcon#read 4, iclass 35, count 0 2006.285.21:50:15.53#ibcon#about to read 5, iclass 35, count 0 2006.285.21:50:15.53#ibcon#read 5, iclass 35, count 0 2006.285.21:50:15.53#ibcon#about to read 6, iclass 35, count 0 2006.285.21:50:15.53#ibcon#read 6, iclass 35, count 0 2006.285.21:50:15.53#ibcon#end of sib2, iclass 35, count 0 2006.285.21:50:15.53#ibcon#*after write, iclass 35, count 0 2006.285.21:50:15.53#ibcon#*before return 0, iclass 35, count 0 2006.285.21:50:15.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:50:15.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.21:50:15.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.21:50:15.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.21:50:15.53$setupk4/ifdk4 2006.285.21:50:15.53$ifdk4/lo= 2006.285.21:50:15.53$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:50:15.53$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:50:15.53$ifdk4/patch= 2006.285.21:50:15.53$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:50:15.53$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:50:15.53$setupk4/!*+20s 2006.285.21:50:24.06#abcon#<5=/15 0.7 1.2 15.331001015.9\r\n> 2006.285.21:50:24.08#abcon#{5=INTERFACE CLEAR} 2006.285.21:50:24.14#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:50:28.87$setupk4/"tpicd 2006.285.21:50:28.87$setupk4/echo=off 2006.285.21:50:28.87$setupk4/xlog=off 2006.285.21:50:28.87:!2006.285.21:52:26 2006.285.21:50:35.13#trakl#Source acquired 2006.285.21:50:36.13#flagr#flagr/antenna,acquired 2006.285.21:52:26.00:preob 2006.285.21:52:26.13/onsource/TRACKING 2006.285.21:52:26.13:!2006.285.21:52:36 2006.285.21:52:36.00:"tape 2006.285.21:52:36.00:"st=record 2006.285.21:52:36.00:data_valid=on 2006.285.21:52:36.00:midob 2006.285.21:52:36.13/onsource/TRACKING 2006.285.21:52:36.13/wx/15.42,1015.9,100 2006.285.21:52:36.24/cable/+6.5108E-03 2006.285.21:52:37.33/va/01,07,usb,yes,34,37 2006.285.21:52:37.33/va/02,06,usb,yes,34,35 2006.285.21:52:37.33/va/03,07,usb,yes,34,36 2006.285.21:52:37.33/va/04,06,usb,yes,35,37 2006.285.21:52:37.33/va/05,03,usb,yes,35,35 2006.285.21:52:37.33/va/06,04,usb,yes,31,31 2006.285.21:52:37.33/va/07,04,usb,yes,32,33 2006.285.21:52:37.33/va/08,03,usb,yes,33,40 2006.285.21:52:37.56/valo/01,524.99,yes,locked 2006.285.21:52:37.56/valo/02,534.99,yes,locked 2006.285.21:52:37.56/valo/03,564.99,yes,locked 2006.285.21:52:37.56/valo/04,624.99,yes,locked 2006.285.21:52:37.56/valo/05,734.99,yes,locked 2006.285.21:52:37.56/valo/06,814.99,yes,locked 2006.285.21:52:37.56/valo/07,864.99,yes,locked 2006.285.21:52:37.56/valo/08,884.99,yes,locked 2006.285.21:52:38.65/vb/01,04,usb,yes,30,30 2006.285.21:52:38.65/vb/02,05,usb,yes,28,29 2006.285.21:52:38.65/vb/03,04,usb,yes,29,32 2006.285.21:52:38.65/vb/04,05,usb,yes,30,29 2006.285.21:52:38.65/vb/05,04,usb,yes,26,29 2006.285.21:52:38.65/vb/06,03,usb,yes,38,34 2006.285.21:52:38.65/vb/07,04,usb,yes,31,31 2006.285.21:52:38.65/vb/08,04,usb,yes,28,31 2006.285.21:52:38.88/vblo/01,629.99,yes,locked 2006.285.21:52:38.88/vblo/02,634.99,yes,locked 2006.285.21:52:38.88/vblo/03,649.99,yes,locked 2006.285.21:52:38.88/vblo/04,679.99,yes,locked 2006.285.21:52:38.88/vblo/05,709.99,yes,locked 2006.285.21:52:38.88/vblo/06,719.99,yes,locked 2006.285.21:52:38.88/vblo/07,734.99,yes,locked 2006.285.21:52:38.88/vblo/08,744.99,yes,locked 2006.285.21:52:39.03/vabw/8 2006.285.21:52:39.18/vbbw/8 2006.285.21:52:39.36/xfe/off,on,12.0 2006.285.21:52:39.74/ifatt/23,28,28,28 2006.285.21:52:40.07/fmout-gps/S +2.65E-07 2006.285.21:52:40.08:!2006.285.21:56:56 2006.285.21:56:56.01:data_valid=off 2006.285.21:56:56.02:"et 2006.285.21:56:56.02:!+3s 2006.285.21:56:59.04:"tape 2006.285.21:56:59.04:postob 2006.285.21:56:59.19/cable/+6.5113E-03 2006.285.21:56:59.19/wx/15.57,1016.0,100 2006.285.21:56:59.25/fmout-gps/S +2.63E-07 2006.285.21:56:59.25:scan_name=285-2206,jd0610,200 2006.285.21:56:59.25:source=1044+719,104827.62,714335.9,2000.0,cw 2006.285.21:57:00.14#flagr#flagr/antenna,new-source 2006.285.21:57:00.15:checkk5 2006.285.21:57:00.77/chk_autoobs//k5ts1/ autoobs is running! 2006.285.21:57:01.22/chk_autoobs//k5ts2/ autoobs is running! 2006.285.21:57:01.64/chk_autoobs//k5ts3/ autoobs is running! 2006.285.21:57:02.40/chk_autoobs//k5ts4/ autoobs is running! 2006.285.21:57:02.78/chk_obsdata//k5ts1/T2852152??a.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.285.21:57:03.18/chk_obsdata//k5ts2/T2852152??b.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.285.21:57:03.54/chk_obsdata//k5ts3/T2852152??c.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.285.21:57:04.07/chk_obsdata//k5ts4/T2852152??d.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.285.21:57:04.99/k5log//k5ts1_log_newline 2006.285.21:57:05.69/k5log//k5ts2_log_newline 2006.285.21:57:06.47/k5log//k5ts3_log_newline 2006.285.21:57:07.31/k5log//k5ts4_log_newline 2006.285.21:57:07.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.21:57:07.33:setupk4=1 2006.285.21:57:07.33$setupk4/echo=on 2006.285.21:57:07.33$setupk4/pcalon 2006.285.21:57:07.33$pcalon/"no phase cal control is implemented here 2006.285.21:57:07.33$setupk4/"tpicd=stop 2006.285.21:57:07.33$setupk4/"rec=synch_on 2006.285.21:57:07.33$setupk4/"rec_mode=128 2006.285.21:57:07.33$setupk4/!* 2006.285.21:57:07.33$setupk4/recpk4 2006.285.21:57:07.33$recpk4/recpatch= 2006.285.21:57:07.33$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.21:57:07.33$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.21:57:07.33$setupk4/vck44 2006.285.21:57:07.34$vck44/valo=1,524.99 2006.285.21:57:07.34#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.21:57:07.34#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.21:57:07.34#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:07.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:57:07.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:57:07.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:57:07.34#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:57:07.34#ibcon#first serial, iclass 20, count 0 2006.285.21:57:07.34#ibcon#enter sib2, iclass 20, count 0 2006.285.21:57:07.34#ibcon#flushed, iclass 20, count 0 2006.285.21:57:07.34#ibcon#about to write, iclass 20, count 0 2006.285.21:57:07.34#ibcon#wrote, iclass 20, count 0 2006.285.21:57:07.34#ibcon#about to read 3, iclass 20, count 0 2006.285.21:57:07.35#ibcon#read 3, iclass 20, count 0 2006.285.21:57:07.35#ibcon#about to read 4, iclass 20, count 0 2006.285.21:57:07.35#ibcon#read 4, iclass 20, count 0 2006.285.21:57:07.35#ibcon#about to read 5, iclass 20, count 0 2006.285.21:57:07.35#ibcon#read 5, iclass 20, count 0 2006.285.21:57:07.35#ibcon#about to read 6, iclass 20, count 0 2006.285.21:57:07.35#ibcon#read 6, iclass 20, count 0 2006.285.21:57:07.35#ibcon#end of sib2, iclass 20, count 0 2006.285.21:57:07.35#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:57:07.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:57:07.35#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.21:57:07.35#ibcon#*before write, iclass 20, count 0 2006.285.21:57:07.35#ibcon#enter sib2, iclass 20, count 0 2006.285.21:57:07.35#ibcon#flushed, iclass 20, count 0 2006.285.21:57:07.35#ibcon#about to write, iclass 20, count 0 2006.285.21:57:07.35#ibcon#wrote, iclass 20, count 0 2006.285.21:57:07.35#ibcon#about to read 3, iclass 20, count 0 2006.285.21:57:07.40#ibcon#read 3, iclass 20, count 0 2006.285.21:57:07.40#ibcon#about to read 4, iclass 20, count 0 2006.285.21:57:07.40#ibcon#read 4, iclass 20, count 0 2006.285.21:57:07.40#ibcon#about to read 5, iclass 20, count 0 2006.285.21:57:07.40#ibcon#read 5, iclass 20, count 0 2006.285.21:57:07.40#ibcon#about to read 6, iclass 20, count 0 2006.285.21:57:07.40#ibcon#read 6, iclass 20, count 0 2006.285.21:57:07.40#ibcon#end of sib2, iclass 20, count 0 2006.285.21:57:07.40#ibcon#*after write, iclass 20, count 0 2006.285.21:57:07.40#ibcon#*before return 0, iclass 20, count 0 2006.285.21:57:07.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:57:07.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:57:07.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:57:07.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:57:07.40$vck44/va=1,7 2006.285.21:57:07.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.21:57:07.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.21:57:07.40#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:07.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:57:07.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:57:07.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:57:07.40#ibcon#enter wrdev, iclass 22, count 2 2006.285.21:57:07.40#ibcon#first serial, iclass 22, count 2 2006.285.21:57:07.40#ibcon#enter sib2, iclass 22, count 2 2006.285.21:57:07.40#ibcon#flushed, iclass 22, count 2 2006.285.21:57:07.40#ibcon#about to write, iclass 22, count 2 2006.285.21:57:07.40#ibcon#wrote, iclass 22, count 2 2006.285.21:57:07.40#ibcon#about to read 3, iclass 22, count 2 2006.285.21:57:07.42#ibcon#read 3, iclass 22, count 2 2006.285.21:57:07.42#ibcon#about to read 4, iclass 22, count 2 2006.285.21:57:07.42#ibcon#read 4, iclass 22, count 2 2006.285.21:57:07.42#ibcon#about to read 5, iclass 22, count 2 2006.285.21:57:07.42#ibcon#read 5, iclass 22, count 2 2006.285.21:57:07.42#ibcon#about to read 6, iclass 22, count 2 2006.285.21:57:07.42#ibcon#read 6, iclass 22, count 2 2006.285.21:57:07.42#ibcon#end of sib2, iclass 22, count 2 2006.285.21:57:07.42#ibcon#*mode == 0, iclass 22, count 2 2006.285.21:57:07.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.21:57:07.42#ibcon#[25=AT01-07\r\n] 2006.285.21:57:07.42#ibcon#*before write, iclass 22, count 2 2006.285.21:57:07.42#ibcon#enter sib2, iclass 22, count 2 2006.285.21:57:07.42#ibcon#flushed, iclass 22, count 2 2006.285.21:57:07.42#ibcon#about to write, iclass 22, count 2 2006.285.21:57:07.42#ibcon#wrote, iclass 22, count 2 2006.285.21:57:07.42#ibcon#about to read 3, iclass 22, count 2 2006.285.21:57:07.45#ibcon#read 3, iclass 22, count 2 2006.285.21:57:07.45#ibcon#about to read 4, iclass 22, count 2 2006.285.21:57:07.45#ibcon#read 4, iclass 22, count 2 2006.285.21:57:07.45#ibcon#about to read 5, iclass 22, count 2 2006.285.21:57:07.45#ibcon#read 5, iclass 22, count 2 2006.285.21:57:07.45#ibcon#about to read 6, iclass 22, count 2 2006.285.21:57:07.45#ibcon#read 6, iclass 22, count 2 2006.285.21:57:07.45#ibcon#end of sib2, iclass 22, count 2 2006.285.21:57:07.45#ibcon#*after write, iclass 22, count 2 2006.285.21:57:07.45#ibcon#*before return 0, iclass 22, count 2 2006.285.21:57:07.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:57:07.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.21:57:07.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.21:57:07.45#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:07.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:57:07.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:57:07.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:57:07.57#ibcon#enter wrdev, iclass 22, count 0 2006.285.21:57:07.57#ibcon#first serial, iclass 22, count 0 2006.285.21:57:07.57#ibcon#enter sib2, iclass 22, count 0 2006.285.21:57:07.57#ibcon#flushed, iclass 22, count 0 2006.285.21:57:07.57#ibcon#about to write, iclass 22, count 0 2006.285.21:57:07.57#ibcon#wrote, iclass 22, count 0 2006.285.21:57:07.57#ibcon#about to read 3, iclass 22, count 0 2006.285.21:57:07.59#ibcon#read 3, iclass 22, count 0 2006.285.21:57:07.59#ibcon#about to read 4, iclass 22, count 0 2006.285.21:57:07.59#ibcon#read 4, iclass 22, count 0 2006.285.21:57:07.59#ibcon#about to read 5, iclass 22, count 0 2006.285.21:57:07.59#ibcon#read 5, iclass 22, count 0 2006.285.21:57:07.59#ibcon#about to read 6, iclass 22, count 0 2006.285.21:57:07.59#ibcon#read 6, iclass 22, count 0 2006.285.21:57:07.59#ibcon#end of sib2, iclass 22, count 0 2006.285.21:57:07.59#ibcon#*mode == 0, iclass 22, count 0 2006.285.21:57:07.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.21:57:07.59#ibcon#[25=USB\r\n] 2006.285.21:57:07.59#ibcon#*before write, iclass 22, count 0 2006.285.21:57:07.59#ibcon#enter sib2, iclass 22, count 0 2006.285.21:57:07.59#ibcon#flushed, iclass 22, count 0 2006.285.21:57:07.59#ibcon#about to write, iclass 22, count 0 2006.285.21:57:07.59#ibcon#wrote, iclass 22, count 0 2006.285.21:57:07.59#ibcon#about to read 3, iclass 22, count 0 2006.285.21:57:07.62#ibcon#read 3, iclass 22, count 0 2006.285.21:57:07.62#ibcon#about to read 4, iclass 22, count 0 2006.285.21:57:07.62#ibcon#read 4, iclass 22, count 0 2006.285.21:57:07.62#ibcon#about to read 5, iclass 22, count 0 2006.285.21:57:07.62#ibcon#read 5, iclass 22, count 0 2006.285.21:57:07.62#ibcon#about to read 6, iclass 22, count 0 2006.285.21:57:07.62#ibcon#read 6, iclass 22, count 0 2006.285.21:57:07.62#ibcon#end of sib2, iclass 22, count 0 2006.285.21:57:07.62#ibcon#*after write, iclass 22, count 0 2006.285.21:57:07.62#ibcon#*before return 0, iclass 22, count 0 2006.285.21:57:07.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:57:07.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.21:57:07.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.21:57:07.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.21:57:07.62$vck44/valo=2,534.99 2006.285.21:57:07.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.21:57:07.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.21:57:07.62#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:07.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:57:07.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:57:07.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:57:07.62#ibcon#enter wrdev, iclass 24, count 0 2006.285.21:57:07.62#ibcon#first serial, iclass 24, count 0 2006.285.21:57:07.62#ibcon#enter sib2, iclass 24, count 0 2006.285.21:57:07.62#ibcon#flushed, iclass 24, count 0 2006.285.21:57:07.62#ibcon#about to write, iclass 24, count 0 2006.285.21:57:07.62#ibcon#wrote, iclass 24, count 0 2006.285.21:57:07.62#ibcon#about to read 3, iclass 24, count 0 2006.285.21:57:07.64#ibcon#read 3, iclass 24, count 0 2006.285.21:57:07.64#ibcon#about to read 4, iclass 24, count 0 2006.285.21:57:07.64#ibcon#read 4, iclass 24, count 0 2006.285.21:57:07.64#ibcon#about to read 5, iclass 24, count 0 2006.285.21:57:07.64#ibcon#read 5, iclass 24, count 0 2006.285.21:57:07.64#ibcon#about to read 6, iclass 24, count 0 2006.285.21:57:07.64#ibcon#read 6, iclass 24, count 0 2006.285.21:57:07.64#ibcon#end of sib2, iclass 24, count 0 2006.285.21:57:07.64#ibcon#*mode == 0, iclass 24, count 0 2006.285.21:57:07.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.21:57:07.64#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.21:57:07.64#ibcon#*before write, iclass 24, count 0 2006.285.21:57:07.64#ibcon#enter sib2, iclass 24, count 0 2006.285.21:57:07.64#ibcon#flushed, iclass 24, count 0 2006.285.21:57:07.64#ibcon#about to write, iclass 24, count 0 2006.285.21:57:07.64#ibcon#wrote, iclass 24, count 0 2006.285.21:57:07.64#ibcon#about to read 3, iclass 24, count 0 2006.285.21:57:07.68#ibcon#read 3, iclass 24, count 0 2006.285.21:57:07.68#ibcon#about to read 4, iclass 24, count 0 2006.285.21:57:07.68#ibcon#read 4, iclass 24, count 0 2006.285.21:57:07.68#ibcon#about to read 5, iclass 24, count 0 2006.285.21:57:07.68#ibcon#read 5, iclass 24, count 0 2006.285.21:57:07.68#ibcon#about to read 6, iclass 24, count 0 2006.285.21:57:07.68#ibcon#read 6, iclass 24, count 0 2006.285.21:57:07.68#ibcon#end of sib2, iclass 24, count 0 2006.285.21:57:07.68#ibcon#*after write, iclass 24, count 0 2006.285.21:57:07.68#ibcon#*before return 0, iclass 24, count 0 2006.285.21:57:07.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:57:07.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.21:57:07.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.21:57:07.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.21:57:07.68$vck44/va=2,6 2006.285.21:57:07.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.21:57:07.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.21:57:07.68#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:07.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:57:07.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:57:07.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:57:07.74#ibcon#enter wrdev, iclass 26, count 2 2006.285.21:57:07.74#ibcon#first serial, iclass 26, count 2 2006.285.21:57:07.74#ibcon#enter sib2, iclass 26, count 2 2006.285.21:57:07.74#ibcon#flushed, iclass 26, count 2 2006.285.21:57:07.74#ibcon#about to write, iclass 26, count 2 2006.285.21:57:07.74#ibcon#wrote, iclass 26, count 2 2006.285.21:57:07.74#ibcon#about to read 3, iclass 26, count 2 2006.285.21:57:07.76#ibcon#read 3, iclass 26, count 2 2006.285.21:57:07.76#ibcon#about to read 4, iclass 26, count 2 2006.285.21:57:07.76#ibcon#read 4, iclass 26, count 2 2006.285.21:57:07.76#ibcon#about to read 5, iclass 26, count 2 2006.285.21:57:07.76#ibcon#read 5, iclass 26, count 2 2006.285.21:57:07.76#ibcon#about to read 6, iclass 26, count 2 2006.285.21:57:07.76#ibcon#read 6, iclass 26, count 2 2006.285.21:57:07.76#ibcon#end of sib2, iclass 26, count 2 2006.285.21:57:07.76#ibcon#*mode == 0, iclass 26, count 2 2006.285.21:57:07.76#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.21:57:07.76#ibcon#[25=AT02-06\r\n] 2006.285.21:57:07.76#ibcon#*before write, iclass 26, count 2 2006.285.21:57:07.76#ibcon#enter sib2, iclass 26, count 2 2006.285.21:57:07.76#ibcon#flushed, iclass 26, count 2 2006.285.21:57:07.76#ibcon#about to write, iclass 26, count 2 2006.285.21:57:07.76#ibcon#wrote, iclass 26, count 2 2006.285.21:57:07.76#ibcon#about to read 3, iclass 26, count 2 2006.285.21:57:07.79#ibcon#read 3, iclass 26, count 2 2006.285.21:57:07.79#ibcon#about to read 4, iclass 26, count 2 2006.285.21:57:07.79#ibcon#read 4, iclass 26, count 2 2006.285.21:57:07.79#ibcon#about to read 5, iclass 26, count 2 2006.285.21:57:07.79#ibcon#read 5, iclass 26, count 2 2006.285.21:57:07.79#ibcon#about to read 6, iclass 26, count 2 2006.285.21:57:07.79#ibcon#read 6, iclass 26, count 2 2006.285.21:57:07.79#ibcon#end of sib2, iclass 26, count 2 2006.285.21:57:07.79#ibcon#*after write, iclass 26, count 2 2006.285.21:57:07.79#ibcon#*before return 0, iclass 26, count 2 2006.285.21:57:07.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:57:07.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.21:57:07.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.21:57:07.79#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:07.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:57:07.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:57:08.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:57:08.48#ibcon#enter wrdev, iclass 26, count 0 2006.285.21:57:08.48#ibcon#first serial, iclass 26, count 0 2006.285.21:57:08.48#ibcon#enter sib2, iclass 26, count 0 2006.285.21:57:08.48#ibcon#flushed, iclass 26, count 0 2006.285.21:57:08.48#ibcon#about to write, iclass 26, count 0 2006.285.21:57:08.48#ibcon#wrote, iclass 26, count 0 2006.285.21:57:08.48#ibcon#about to read 3, iclass 26, count 0 2006.285.21:57:08.49#ibcon#read 3, iclass 26, count 0 2006.285.21:57:08.49#ibcon#about to read 4, iclass 26, count 0 2006.285.21:57:08.49#ibcon#read 4, iclass 26, count 0 2006.285.21:57:08.49#ibcon#about to read 5, iclass 26, count 0 2006.285.21:57:08.49#ibcon#read 5, iclass 26, count 0 2006.285.21:57:08.49#ibcon#about to read 6, iclass 26, count 0 2006.285.21:57:08.49#ibcon#read 6, iclass 26, count 0 2006.285.21:57:08.49#ibcon#end of sib2, iclass 26, count 0 2006.285.21:57:08.49#ibcon#*mode == 0, iclass 26, count 0 2006.285.21:57:08.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.21:57:08.49#ibcon#[25=USB\r\n] 2006.285.21:57:08.49#ibcon#*before write, iclass 26, count 0 2006.285.21:57:08.49#ibcon#enter sib2, iclass 26, count 0 2006.285.21:57:08.49#ibcon#flushed, iclass 26, count 0 2006.285.21:57:08.49#ibcon#about to write, iclass 26, count 0 2006.285.21:57:08.49#ibcon#wrote, iclass 26, count 0 2006.285.21:57:08.49#ibcon#about to read 3, iclass 26, count 0 2006.285.21:57:08.52#ibcon#read 3, iclass 26, count 0 2006.285.21:57:08.52#ibcon#about to read 4, iclass 26, count 0 2006.285.21:57:08.52#ibcon#read 4, iclass 26, count 0 2006.285.21:57:08.52#ibcon#about to read 5, iclass 26, count 0 2006.285.21:57:08.52#ibcon#read 5, iclass 26, count 0 2006.285.21:57:08.52#ibcon#about to read 6, iclass 26, count 0 2006.285.21:57:08.52#ibcon#read 6, iclass 26, count 0 2006.285.21:57:08.52#ibcon#end of sib2, iclass 26, count 0 2006.285.21:57:08.52#ibcon#*after write, iclass 26, count 0 2006.285.21:57:08.52#ibcon#*before return 0, iclass 26, count 0 2006.285.21:57:08.52#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:57:08.52#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.21:57:08.52#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.21:57:08.52#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.21:57:08.52$vck44/valo=3,564.99 2006.285.21:57:08.52#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.21:57:08.52#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.21:57:08.52#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:08.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:57:08.52#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:57:08.52#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:57:08.52#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:57:08.52#ibcon#first serial, iclass 28, count 0 2006.285.21:57:08.52#ibcon#enter sib2, iclass 28, count 0 2006.285.21:57:08.52#ibcon#flushed, iclass 28, count 0 2006.285.21:57:08.52#ibcon#about to write, iclass 28, count 0 2006.285.21:57:08.52#ibcon#wrote, iclass 28, count 0 2006.285.21:57:08.52#ibcon#about to read 3, iclass 28, count 0 2006.285.21:57:08.54#ibcon#read 3, iclass 28, count 0 2006.285.21:57:08.54#ibcon#about to read 4, iclass 28, count 0 2006.285.21:57:08.54#ibcon#read 4, iclass 28, count 0 2006.285.21:57:08.54#ibcon#about to read 5, iclass 28, count 0 2006.285.21:57:08.54#ibcon#read 5, iclass 28, count 0 2006.285.21:57:08.54#ibcon#about to read 6, iclass 28, count 0 2006.285.21:57:08.54#ibcon#read 6, iclass 28, count 0 2006.285.21:57:08.54#ibcon#end of sib2, iclass 28, count 0 2006.285.21:57:08.54#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:57:08.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:57:08.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.21:57:08.54#ibcon#*before write, iclass 28, count 0 2006.285.21:57:08.54#ibcon#enter sib2, iclass 28, count 0 2006.285.21:57:08.54#ibcon#flushed, iclass 28, count 0 2006.285.21:57:08.54#ibcon#about to write, iclass 28, count 0 2006.285.21:57:08.54#ibcon#wrote, iclass 28, count 0 2006.285.21:57:08.54#ibcon#about to read 3, iclass 28, count 0 2006.285.21:57:08.58#ibcon#read 3, iclass 28, count 0 2006.285.21:57:08.58#ibcon#about to read 4, iclass 28, count 0 2006.285.21:57:08.58#ibcon#read 4, iclass 28, count 0 2006.285.21:57:08.58#ibcon#about to read 5, iclass 28, count 0 2006.285.21:57:08.58#ibcon#read 5, iclass 28, count 0 2006.285.21:57:08.58#ibcon#about to read 6, iclass 28, count 0 2006.285.21:57:08.58#ibcon#read 6, iclass 28, count 0 2006.285.21:57:08.58#ibcon#end of sib2, iclass 28, count 0 2006.285.21:57:08.58#ibcon#*after write, iclass 28, count 0 2006.285.21:57:08.58#ibcon#*before return 0, iclass 28, count 0 2006.285.21:57:08.58#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:57:08.58#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:57:08.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:57:08.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:57:08.58$vck44/va=3,7 2006.285.21:57:08.58#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.21:57:08.58#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.21:57:08.58#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:08.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:57:08.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:57:08.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:57:08.64#ibcon#enter wrdev, iclass 30, count 2 2006.285.21:57:08.64#ibcon#first serial, iclass 30, count 2 2006.285.21:57:08.64#ibcon#enter sib2, iclass 30, count 2 2006.285.21:57:08.64#ibcon#flushed, iclass 30, count 2 2006.285.21:57:08.64#ibcon#about to write, iclass 30, count 2 2006.285.21:57:08.64#ibcon#wrote, iclass 30, count 2 2006.285.21:57:08.64#ibcon#about to read 3, iclass 30, count 2 2006.285.21:57:08.66#ibcon#read 3, iclass 30, count 2 2006.285.21:57:08.66#ibcon#about to read 4, iclass 30, count 2 2006.285.21:57:08.66#ibcon#read 4, iclass 30, count 2 2006.285.21:57:08.66#ibcon#about to read 5, iclass 30, count 2 2006.285.21:57:08.66#ibcon#read 5, iclass 30, count 2 2006.285.21:57:08.66#ibcon#about to read 6, iclass 30, count 2 2006.285.21:57:08.66#ibcon#read 6, iclass 30, count 2 2006.285.21:57:08.66#ibcon#end of sib2, iclass 30, count 2 2006.285.21:57:08.66#ibcon#*mode == 0, iclass 30, count 2 2006.285.21:57:08.66#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.21:57:08.66#ibcon#[25=AT03-07\r\n] 2006.285.21:57:08.66#ibcon#*before write, iclass 30, count 2 2006.285.21:57:08.66#ibcon#enter sib2, iclass 30, count 2 2006.285.21:57:08.66#ibcon#flushed, iclass 30, count 2 2006.285.21:57:08.66#ibcon#about to write, iclass 30, count 2 2006.285.21:57:08.66#ibcon#wrote, iclass 30, count 2 2006.285.21:57:08.66#ibcon#about to read 3, iclass 30, count 2 2006.285.21:57:08.69#ibcon#read 3, iclass 30, count 2 2006.285.21:57:08.69#ibcon#about to read 4, iclass 30, count 2 2006.285.21:57:08.69#ibcon#read 4, iclass 30, count 2 2006.285.21:57:08.69#ibcon#about to read 5, iclass 30, count 2 2006.285.21:57:08.69#ibcon#read 5, iclass 30, count 2 2006.285.21:57:08.69#ibcon#about to read 6, iclass 30, count 2 2006.285.21:57:08.69#ibcon#read 6, iclass 30, count 2 2006.285.21:57:08.69#ibcon#end of sib2, iclass 30, count 2 2006.285.21:57:08.69#ibcon#*after write, iclass 30, count 2 2006.285.21:57:08.69#ibcon#*before return 0, iclass 30, count 2 2006.285.21:57:08.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:57:08.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:57:08.69#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.21:57:08.69#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:08.69#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:57:08.81#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:57:08.81#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:57:08.81#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:57:08.81#ibcon#first serial, iclass 30, count 0 2006.285.21:57:08.81#ibcon#enter sib2, iclass 30, count 0 2006.285.21:57:08.81#ibcon#flushed, iclass 30, count 0 2006.285.21:57:08.81#ibcon#about to write, iclass 30, count 0 2006.285.21:57:08.81#ibcon#wrote, iclass 30, count 0 2006.285.21:57:08.81#ibcon#about to read 3, iclass 30, count 0 2006.285.21:57:08.83#ibcon#read 3, iclass 30, count 0 2006.285.21:57:08.87#ibcon#about to read 4, iclass 30, count 0 2006.285.21:57:08.87#ibcon#read 4, iclass 30, count 0 2006.285.21:57:08.87#ibcon#about to read 5, iclass 30, count 0 2006.285.21:57:08.87#ibcon#read 5, iclass 30, count 0 2006.285.21:57:08.87#ibcon#about to read 6, iclass 30, count 0 2006.285.21:57:08.87#ibcon#read 6, iclass 30, count 0 2006.285.21:57:08.87#ibcon#end of sib2, iclass 30, count 0 2006.285.21:57:08.87#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:57:08.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:57:08.87#ibcon#[25=USB\r\n] 2006.285.21:57:08.87#ibcon#*before write, iclass 30, count 0 2006.285.21:57:08.87#ibcon#enter sib2, iclass 30, count 0 2006.285.21:57:08.87#ibcon#flushed, iclass 30, count 0 2006.285.21:57:08.87#ibcon#about to write, iclass 30, count 0 2006.285.21:57:08.87#ibcon#wrote, iclass 30, count 0 2006.285.21:57:08.87#ibcon#about to read 3, iclass 30, count 0 2006.285.21:57:08.89#ibcon#read 3, iclass 30, count 0 2006.285.21:57:08.89#ibcon#about to read 4, iclass 30, count 0 2006.285.21:57:08.89#ibcon#read 4, iclass 30, count 0 2006.285.21:57:08.89#ibcon#about to read 5, iclass 30, count 0 2006.285.21:57:08.89#ibcon#read 5, iclass 30, count 0 2006.285.21:57:08.89#ibcon#about to read 6, iclass 30, count 0 2006.285.21:57:08.89#ibcon#read 6, iclass 30, count 0 2006.285.21:57:08.89#ibcon#end of sib2, iclass 30, count 0 2006.285.21:57:08.89#ibcon#*after write, iclass 30, count 0 2006.285.21:57:08.89#ibcon#*before return 0, iclass 30, count 0 2006.285.21:57:08.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:57:08.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:57:08.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:57:08.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:57:08.89$vck44/valo=4,624.99 2006.285.21:57:08.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.21:57:08.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.21:57:08.89#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:08.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:57:08.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:57:08.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:57:08.89#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:57:08.89#ibcon#first serial, iclass 32, count 0 2006.285.21:57:08.89#ibcon#enter sib2, iclass 32, count 0 2006.285.21:57:08.89#ibcon#flushed, iclass 32, count 0 2006.285.21:57:08.89#ibcon#about to write, iclass 32, count 0 2006.285.21:57:08.89#ibcon#wrote, iclass 32, count 0 2006.285.21:57:08.89#ibcon#about to read 3, iclass 32, count 0 2006.285.21:57:08.91#ibcon#read 3, iclass 32, count 0 2006.285.21:57:08.91#ibcon#about to read 4, iclass 32, count 0 2006.285.21:57:08.91#ibcon#read 4, iclass 32, count 0 2006.285.21:57:08.91#ibcon#about to read 5, iclass 32, count 0 2006.285.21:57:08.91#ibcon#read 5, iclass 32, count 0 2006.285.21:57:08.91#ibcon#about to read 6, iclass 32, count 0 2006.285.21:57:08.91#ibcon#read 6, iclass 32, count 0 2006.285.21:57:08.91#ibcon#end of sib2, iclass 32, count 0 2006.285.21:57:08.91#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:57:08.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:57:08.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.21:57:08.91#ibcon#*before write, iclass 32, count 0 2006.285.21:57:08.91#ibcon#enter sib2, iclass 32, count 0 2006.285.21:57:08.91#ibcon#flushed, iclass 32, count 0 2006.285.21:57:08.91#ibcon#about to write, iclass 32, count 0 2006.285.21:57:08.91#ibcon#wrote, iclass 32, count 0 2006.285.21:57:08.91#ibcon#about to read 3, iclass 32, count 0 2006.285.21:57:08.95#ibcon#read 3, iclass 32, count 0 2006.285.21:57:08.95#ibcon#about to read 4, iclass 32, count 0 2006.285.21:57:08.95#ibcon#read 4, iclass 32, count 0 2006.285.21:57:08.95#ibcon#about to read 5, iclass 32, count 0 2006.285.21:57:08.95#ibcon#read 5, iclass 32, count 0 2006.285.21:57:08.95#ibcon#about to read 6, iclass 32, count 0 2006.285.21:57:08.95#ibcon#read 6, iclass 32, count 0 2006.285.21:57:08.95#ibcon#end of sib2, iclass 32, count 0 2006.285.21:57:08.95#ibcon#*after write, iclass 32, count 0 2006.285.21:57:08.95#ibcon#*before return 0, iclass 32, count 0 2006.285.21:57:08.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:57:08.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:57:08.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:57:08.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:57:08.95$vck44/va=4,6 2006.285.21:57:08.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.21:57:08.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.21:57:08.95#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:08.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:57:09.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:57:09.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:57:09.01#ibcon#enter wrdev, iclass 34, count 2 2006.285.21:57:09.01#ibcon#first serial, iclass 34, count 2 2006.285.21:57:09.01#ibcon#enter sib2, iclass 34, count 2 2006.285.21:57:09.01#ibcon#flushed, iclass 34, count 2 2006.285.21:57:09.01#ibcon#about to write, iclass 34, count 2 2006.285.21:57:09.01#ibcon#wrote, iclass 34, count 2 2006.285.21:57:09.01#ibcon#about to read 3, iclass 34, count 2 2006.285.21:57:09.03#ibcon#read 3, iclass 34, count 2 2006.285.21:57:09.03#ibcon#about to read 4, iclass 34, count 2 2006.285.21:57:09.03#ibcon#read 4, iclass 34, count 2 2006.285.21:57:09.03#ibcon#about to read 5, iclass 34, count 2 2006.285.21:57:09.03#ibcon#read 5, iclass 34, count 2 2006.285.21:57:09.03#ibcon#about to read 6, iclass 34, count 2 2006.285.21:57:09.03#ibcon#read 6, iclass 34, count 2 2006.285.21:57:09.03#ibcon#end of sib2, iclass 34, count 2 2006.285.21:57:09.03#ibcon#*mode == 0, iclass 34, count 2 2006.285.21:57:09.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.21:57:09.03#ibcon#[25=AT04-06\r\n] 2006.285.21:57:09.03#ibcon#*before write, iclass 34, count 2 2006.285.21:57:09.03#ibcon#enter sib2, iclass 34, count 2 2006.285.21:57:09.03#ibcon#flushed, iclass 34, count 2 2006.285.21:57:09.03#ibcon#about to write, iclass 34, count 2 2006.285.21:57:09.03#ibcon#wrote, iclass 34, count 2 2006.285.21:57:09.03#ibcon#about to read 3, iclass 34, count 2 2006.285.21:57:09.06#ibcon#read 3, iclass 34, count 2 2006.285.21:57:09.06#ibcon#about to read 4, iclass 34, count 2 2006.285.21:57:09.06#ibcon#read 4, iclass 34, count 2 2006.285.21:57:09.06#ibcon#about to read 5, iclass 34, count 2 2006.285.21:57:09.06#ibcon#read 5, iclass 34, count 2 2006.285.21:57:09.06#ibcon#about to read 6, iclass 34, count 2 2006.285.21:57:09.06#ibcon#read 6, iclass 34, count 2 2006.285.21:57:09.06#ibcon#end of sib2, iclass 34, count 2 2006.285.21:57:09.06#ibcon#*after write, iclass 34, count 2 2006.285.21:57:09.06#ibcon#*before return 0, iclass 34, count 2 2006.285.21:57:09.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:57:09.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:57:09.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.21:57:09.06#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:09.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:57:09.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:57:09.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:57:09.18#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:57:09.18#ibcon#first serial, iclass 34, count 0 2006.285.21:57:09.18#ibcon#enter sib2, iclass 34, count 0 2006.285.21:57:09.18#ibcon#flushed, iclass 34, count 0 2006.285.21:57:09.18#ibcon#about to write, iclass 34, count 0 2006.285.21:57:09.18#ibcon#wrote, iclass 34, count 0 2006.285.21:57:09.18#ibcon#about to read 3, iclass 34, count 0 2006.285.21:57:09.20#ibcon#read 3, iclass 34, count 0 2006.285.21:57:09.20#ibcon#about to read 4, iclass 34, count 0 2006.285.21:57:09.20#ibcon#read 4, iclass 34, count 0 2006.285.21:57:09.20#ibcon#about to read 5, iclass 34, count 0 2006.285.21:57:09.20#ibcon#read 5, iclass 34, count 0 2006.285.21:57:09.20#ibcon#about to read 6, iclass 34, count 0 2006.285.21:57:09.20#ibcon#read 6, iclass 34, count 0 2006.285.21:57:09.20#ibcon#end of sib2, iclass 34, count 0 2006.285.21:57:09.20#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:57:09.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:57:09.20#ibcon#[25=USB\r\n] 2006.285.21:57:09.20#ibcon#*before write, iclass 34, count 0 2006.285.21:57:09.20#ibcon#enter sib2, iclass 34, count 0 2006.285.21:57:09.20#ibcon#flushed, iclass 34, count 0 2006.285.21:57:09.20#ibcon#about to write, iclass 34, count 0 2006.285.21:57:09.20#ibcon#wrote, iclass 34, count 0 2006.285.21:57:09.20#ibcon#about to read 3, iclass 34, count 0 2006.285.21:57:09.23#ibcon#read 3, iclass 34, count 0 2006.285.21:57:09.23#ibcon#about to read 4, iclass 34, count 0 2006.285.21:57:09.23#ibcon#read 4, iclass 34, count 0 2006.285.21:57:09.23#ibcon#about to read 5, iclass 34, count 0 2006.285.21:57:09.23#ibcon#read 5, iclass 34, count 0 2006.285.21:57:09.23#ibcon#about to read 6, iclass 34, count 0 2006.285.21:57:09.23#ibcon#read 6, iclass 34, count 0 2006.285.21:57:09.23#ibcon#end of sib2, iclass 34, count 0 2006.285.21:57:09.23#ibcon#*after write, iclass 34, count 0 2006.285.21:57:09.23#ibcon#*before return 0, iclass 34, count 0 2006.285.21:57:09.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:57:09.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:57:09.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:57:09.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:57:09.23$vck44/valo=5,734.99 2006.285.21:57:09.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.21:57:09.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.21:57:09.23#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:09.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:57:09.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:57:09.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:57:09.23#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:57:09.23#ibcon#first serial, iclass 36, count 0 2006.285.21:57:09.23#ibcon#enter sib2, iclass 36, count 0 2006.285.21:57:09.23#ibcon#flushed, iclass 36, count 0 2006.285.21:57:09.23#ibcon#about to write, iclass 36, count 0 2006.285.21:57:09.23#ibcon#wrote, iclass 36, count 0 2006.285.21:57:09.23#ibcon#about to read 3, iclass 36, count 0 2006.285.21:57:09.25#ibcon#read 3, iclass 36, count 0 2006.285.21:57:09.25#ibcon#about to read 4, iclass 36, count 0 2006.285.21:57:09.25#ibcon#read 4, iclass 36, count 0 2006.285.21:57:09.25#ibcon#about to read 5, iclass 36, count 0 2006.285.21:57:09.25#ibcon#read 5, iclass 36, count 0 2006.285.21:57:09.25#ibcon#about to read 6, iclass 36, count 0 2006.285.21:57:09.25#ibcon#read 6, iclass 36, count 0 2006.285.21:57:09.25#ibcon#end of sib2, iclass 36, count 0 2006.285.21:57:09.25#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:57:09.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:57:09.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.21:57:09.25#ibcon#*before write, iclass 36, count 0 2006.285.21:57:09.25#ibcon#enter sib2, iclass 36, count 0 2006.285.21:57:09.25#ibcon#flushed, iclass 36, count 0 2006.285.21:57:09.25#ibcon#about to write, iclass 36, count 0 2006.285.21:57:09.25#ibcon#wrote, iclass 36, count 0 2006.285.21:57:09.25#ibcon#about to read 3, iclass 36, count 0 2006.285.21:57:09.29#ibcon#read 3, iclass 36, count 0 2006.285.21:57:09.29#ibcon#about to read 4, iclass 36, count 0 2006.285.21:57:09.29#ibcon#read 4, iclass 36, count 0 2006.285.21:57:09.29#ibcon#about to read 5, iclass 36, count 0 2006.285.21:57:09.29#ibcon#read 5, iclass 36, count 0 2006.285.21:57:09.29#ibcon#about to read 6, iclass 36, count 0 2006.285.21:57:09.29#ibcon#read 6, iclass 36, count 0 2006.285.21:57:09.29#ibcon#end of sib2, iclass 36, count 0 2006.285.21:57:09.29#ibcon#*after write, iclass 36, count 0 2006.285.21:57:09.29#ibcon#*before return 0, iclass 36, count 0 2006.285.21:57:09.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:57:09.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:57:09.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:57:09.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:57:09.29$vck44/va=5,3 2006.285.21:57:09.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.21:57:09.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.21:57:09.29#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:09.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:57:09.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:57:09.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:57:09.35#ibcon#enter wrdev, iclass 38, count 2 2006.285.21:57:09.35#ibcon#first serial, iclass 38, count 2 2006.285.21:57:09.35#ibcon#enter sib2, iclass 38, count 2 2006.285.21:57:09.35#ibcon#flushed, iclass 38, count 2 2006.285.21:57:09.35#ibcon#about to write, iclass 38, count 2 2006.285.21:57:09.35#ibcon#wrote, iclass 38, count 2 2006.285.21:57:09.35#ibcon#about to read 3, iclass 38, count 2 2006.285.21:57:09.37#ibcon#read 3, iclass 38, count 2 2006.285.21:57:09.37#ibcon#about to read 4, iclass 38, count 2 2006.285.21:57:09.37#ibcon#read 4, iclass 38, count 2 2006.285.21:57:09.37#ibcon#about to read 5, iclass 38, count 2 2006.285.21:57:09.37#ibcon#read 5, iclass 38, count 2 2006.285.21:57:09.37#ibcon#about to read 6, iclass 38, count 2 2006.285.21:57:09.37#ibcon#read 6, iclass 38, count 2 2006.285.21:57:09.37#ibcon#end of sib2, iclass 38, count 2 2006.285.21:57:09.37#ibcon#*mode == 0, iclass 38, count 2 2006.285.21:57:09.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.21:57:09.37#ibcon#[25=AT05-03\r\n] 2006.285.21:57:09.37#ibcon#*before write, iclass 38, count 2 2006.285.21:57:09.37#ibcon#enter sib2, iclass 38, count 2 2006.285.21:57:09.37#ibcon#flushed, iclass 38, count 2 2006.285.21:57:09.37#ibcon#about to write, iclass 38, count 2 2006.285.21:57:09.37#ibcon#wrote, iclass 38, count 2 2006.285.21:57:09.37#ibcon#about to read 3, iclass 38, count 2 2006.285.21:57:09.40#ibcon#read 3, iclass 38, count 2 2006.285.21:57:09.40#ibcon#about to read 4, iclass 38, count 2 2006.285.21:57:09.40#ibcon#read 4, iclass 38, count 2 2006.285.21:57:09.40#ibcon#about to read 5, iclass 38, count 2 2006.285.21:57:09.40#ibcon#read 5, iclass 38, count 2 2006.285.21:57:09.40#ibcon#about to read 6, iclass 38, count 2 2006.285.21:57:09.40#ibcon#read 6, iclass 38, count 2 2006.285.21:57:09.40#ibcon#end of sib2, iclass 38, count 2 2006.285.21:57:09.40#ibcon#*after write, iclass 38, count 2 2006.285.21:57:09.40#ibcon#*before return 0, iclass 38, count 2 2006.285.21:57:09.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:57:09.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:57:09.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.21:57:09.40#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:09.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:57:09.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:57:09.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:57:09.52#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:57:09.52#ibcon#first serial, iclass 38, count 0 2006.285.21:57:09.52#ibcon#enter sib2, iclass 38, count 0 2006.285.21:57:09.52#ibcon#flushed, iclass 38, count 0 2006.285.21:57:09.52#ibcon#about to write, iclass 38, count 0 2006.285.21:57:09.52#ibcon#wrote, iclass 38, count 0 2006.285.21:57:09.52#ibcon#about to read 3, iclass 38, count 0 2006.285.21:57:09.54#ibcon#read 3, iclass 38, count 0 2006.285.21:57:09.54#ibcon#about to read 4, iclass 38, count 0 2006.285.21:57:09.54#ibcon#read 4, iclass 38, count 0 2006.285.21:57:09.54#ibcon#about to read 5, iclass 38, count 0 2006.285.21:57:09.54#ibcon#read 5, iclass 38, count 0 2006.285.21:57:09.54#ibcon#about to read 6, iclass 38, count 0 2006.285.21:57:09.54#ibcon#read 6, iclass 38, count 0 2006.285.21:57:09.54#ibcon#end of sib2, iclass 38, count 0 2006.285.21:57:09.54#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:57:09.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:57:09.54#ibcon#[25=USB\r\n] 2006.285.21:57:09.54#ibcon#*before write, iclass 38, count 0 2006.285.21:57:09.54#ibcon#enter sib2, iclass 38, count 0 2006.285.21:57:09.54#ibcon#flushed, iclass 38, count 0 2006.285.21:57:09.54#ibcon#about to write, iclass 38, count 0 2006.285.21:57:09.54#ibcon#wrote, iclass 38, count 0 2006.285.21:57:09.54#ibcon#about to read 3, iclass 38, count 0 2006.285.21:57:09.57#ibcon#read 3, iclass 38, count 0 2006.285.21:57:09.57#ibcon#about to read 4, iclass 38, count 0 2006.285.21:57:09.57#ibcon#read 4, iclass 38, count 0 2006.285.21:57:09.57#ibcon#about to read 5, iclass 38, count 0 2006.285.21:57:09.57#ibcon#read 5, iclass 38, count 0 2006.285.21:57:09.57#ibcon#about to read 6, iclass 38, count 0 2006.285.21:57:09.57#ibcon#read 6, iclass 38, count 0 2006.285.21:57:09.57#ibcon#end of sib2, iclass 38, count 0 2006.285.21:57:09.57#ibcon#*after write, iclass 38, count 0 2006.285.21:57:09.57#ibcon#*before return 0, iclass 38, count 0 2006.285.21:57:09.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:57:09.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:57:09.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:57:09.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:57:09.57$vck44/valo=6,814.99 2006.285.21:57:09.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.21:57:09.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.21:57:09.57#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:09.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:57:09.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:57:09.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:57:09.57#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:57:09.57#ibcon#first serial, iclass 40, count 0 2006.285.21:57:09.57#ibcon#enter sib2, iclass 40, count 0 2006.285.21:57:09.57#ibcon#flushed, iclass 40, count 0 2006.285.21:57:09.57#ibcon#about to write, iclass 40, count 0 2006.285.21:57:09.57#ibcon#wrote, iclass 40, count 0 2006.285.21:57:09.57#ibcon#about to read 3, iclass 40, count 0 2006.285.21:57:09.59#ibcon#read 3, iclass 40, count 0 2006.285.21:57:09.59#ibcon#about to read 4, iclass 40, count 0 2006.285.21:57:09.59#ibcon#read 4, iclass 40, count 0 2006.285.21:57:09.59#ibcon#about to read 5, iclass 40, count 0 2006.285.21:57:09.59#ibcon#read 5, iclass 40, count 0 2006.285.21:57:09.59#ibcon#about to read 6, iclass 40, count 0 2006.285.21:57:09.59#ibcon#read 6, iclass 40, count 0 2006.285.21:57:09.59#ibcon#end of sib2, iclass 40, count 0 2006.285.21:57:09.59#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:57:09.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:57:09.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.21:57:09.59#ibcon#*before write, iclass 40, count 0 2006.285.21:57:09.59#ibcon#enter sib2, iclass 40, count 0 2006.285.21:57:09.59#ibcon#flushed, iclass 40, count 0 2006.285.21:57:09.59#ibcon#about to write, iclass 40, count 0 2006.285.21:57:09.59#ibcon#wrote, iclass 40, count 0 2006.285.21:57:09.59#ibcon#about to read 3, iclass 40, count 0 2006.285.21:57:09.63#ibcon#read 3, iclass 40, count 0 2006.285.21:57:09.63#ibcon#about to read 4, iclass 40, count 0 2006.285.21:57:09.63#ibcon#read 4, iclass 40, count 0 2006.285.21:57:09.63#ibcon#about to read 5, iclass 40, count 0 2006.285.21:57:09.63#ibcon#read 5, iclass 40, count 0 2006.285.21:57:09.63#ibcon#about to read 6, iclass 40, count 0 2006.285.21:57:09.63#ibcon#read 6, iclass 40, count 0 2006.285.21:57:09.63#ibcon#end of sib2, iclass 40, count 0 2006.285.21:57:09.63#ibcon#*after write, iclass 40, count 0 2006.285.21:57:09.63#ibcon#*before return 0, iclass 40, count 0 2006.285.21:57:09.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:57:09.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:57:09.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:57:09.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:57:09.63$vck44/va=6,4 2006.285.21:57:09.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.21:57:09.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.21:57:09.63#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:09.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:57:09.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:57:09.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:57:09.69#ibcon#enter wrdev, iclass 4, count 2 2006.285.21:57:09.69#ibcon#first serial, iclass 4, count 2 2006.285.21:57:09.69#ibcon#enter sib2, iclass 4, count 2 2006.285.21:57:09.69#ibcon#flushed, iclass 4, count 2 2006.285.21:57:09.69#ibcon#about to write, iclass 4, count 2 2006.285.21:57:09.69#ibcon#wrote, iclass 4, count 2 2006.285.21:57:09.69#ibcon#about to read 3, iclass 4, count 2 2006.285.21:57:09.71#ibcon#read 3, iclass 4, count 2 2006.285.21:57:09.71#ibcon#about to read 4, iclass 4, count 2 2006.285.21:57:09.71#ibcon#read 4, iclass 4, count 2 2006.285.21:57:09.71#ibcon#about to read 5, iclass 4, count 2 2006.285.21:57:09.71#ibcon#read 5, iclass 4, count 2 2006.285.21:57:09.71#ibcon#about to read 6, iclass 4, count 2 2006.285.21:57:09.71#ibcon#read 6, iclass 4, count 2 2006.285.21:57:09.71#ibcon#end of sib2, iclass 4, count 2 2006.285.21:57:09.71#ibcon#*mode == 0, iclass 4, count 2 2006.285.21:57:09.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.21:57:09.71#ibcon#[25=AT06-04\r\n] 2006.285.21:57:09.71#ibcon#*before write, iclass 4, count 2 2006.285.21:57:09.71#ibcon#enter sib2, iclass 4, count 2 2006.285.21:57:09.71#ibcon#flushed, iclass 4, count 2 2006.285.21:57:09.71#ibcon#about to write, iclass 4, count 2 2006.285.21:57:09.71#ibcon#wrote, iclass 4, count 2 2006.285.21:57:09.71#ibcon#about to read 3, iclass 4, count 2 2006.285.21:57:09.74#ibcon#read 3, iclass 4, count 2 2006.285.21:57:09.74#ibcon#about to read 4, iclass 4, count 2 2006.285.21:57:09.74#ibcon#read 4, iclass 4, count 2 2006.285.21:57:09.74#ibcon#about to read 5, iclass 4, count 2 2006.285.21:57:09.74#ibcon#read 5, iclass 4, count 2 2006.285.21:57:09.74#ibcon#about to read 6, iclass 4, count 2 2006.285.21:57:09.74#ibcon#read 6, iclass 4, count 2 2006.285.21:57:09.74#ibcon#end of sib2, iclass 4, count 2 2006.285.21:57:09.74#ibcon#*after write, iclass 4, count 2 2006.285.21:57:09.74#ibcon#*before return 0, iclass 4, count 2 2006.285.21:57:09.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:57:09.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:57:09.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.21:57:09.74#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:09.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:57:09.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:57:09.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:57:09.86#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:57:09.86#ibcon#first serial, iclass 4, count 0 2006.285.21:57:09.86#ibcon#enter sib2, iclass 4, count 0 2006.285.21:57:09.86#ibcon#flushed, iclass 4, count 0 2006.285.21:57:09.86#ibcon#about to write, iclass 4, count 0 2006.285.21:57:09.86#ibcon#wrote, iclass 4, count 0 2006.285.21:57:09.86#ibcon#about to read 3, iclass 4, count 0 2006.285.21:57:09.88#ibcon#read 3, iclass 4, count 0 2006.285.21:57:09.88#ibcon#about to read 4, iclass 4, count 0 2006.285.21:57:09.88#ibcon#read 4, iclass 4, count 0 2006.285.21:57:09.88#ibcon#about to read 5, iclass 4, count 0 2006.285.21:57:09.88#ibcon#read 5, iclass 4, count 0 2006.285.21:57:09.88#ibcon#about to read 6, iclass 4, count 0 2006.285.21:57:09.88#ibcon#read 6, iclass 4, count 0 2006.285.21:57:09.88#ibcon#end of sib2, iclass 4, count 0 2006.285.21:57:09.88#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:57:09.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:57:09.88#ibcon#[25=USB\r\n] 2006.285.21:57:09.88#ibcon#*before write, iclass 4, count 0 2006.285.21:57:09.88#ibcon#enter sib2, iclass 4, count 0 2006.285.21:57:09.88#ibcon#flushed, iclass 4, count 0 2006.285.21:57:09.88#ibcon#about to write, iclass 4, count 0 2006.285.21:57:09.88#ibcon#wrote, iclass 4, count 0 2006.285.21:57:09.88#ibcon#about to read 3, iclass 4, count 0 2006.285.21:57:09.91#ibcon#read 3, iclass 4, count 0 2006.285.21:57:09.91#ibcon#about to read 4, iclass 4, count 0 2006.285.21:57:09.91#ibcon#read 4, iclass 4, count 0 2006.285.21:57:09.91#ibcon#about to read 5, iclass 4, count 0 2006.285.21:57:09.91#ibcon#read 5, iclass 4, count 0 2006.285.21:57:09.91#ibcon#about to read 6, iclass 4, count 0 2006.285.21:57:09.91#ibcon#read 6, iclass 4, count 0 2006.285.21:57:09.91#ibcon#end of sib2, iclass 4, count 0 2006.285.21:57:09.91#ibcon#*after write, iclass 4, count 0 2006.285.21:57:09.91#ibcon#*before return 0, iclass 4, count 0 2006.285.21:57:09.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:57:09.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:57:09.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:57:09.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:57:09.91$vck44/valo=7,864.99 2006.285.21:57:09.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.21:57:09.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.21:57:09.91#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:09.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:57:09.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:57:09.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:57:09.91#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:57:09.91#ibcon#first serial, iclass 6, count 0 2006.285.21:57:09.91#ibcon#enter sib2, iclass 6, count 0 2006.285.21:57:09.91#ibcon#flushed, iclass 6, count 0 2006.285.21:57:09.91#ibcon#about to write, iclass 6, count 0 2006.285.21:57:09.91#ibcon#wrote, iclass 6, count 0 2006.285.21:57:10.11#ibcon#about to read 3, iclass 6, count 0 2006.285.21:57:10.11#ibcon#read 3, iclass 6, count 0 2006.285.21:57:10.11#ibcon#about to read 4, iclass 6, count 0 2006.285.21:57:10.11#ibcon#read 4, iclass 6, count 0 2006.285.21:57:10.11#ibcon#about to read 5, iclass 6, count 0 2006.285.21:57:10.11#ibcon#read 5, iclass 6, count 0 2006.285.21:57:10.11#ibcon#about to read 6, iclass 6, count 0 2006.285.21:57:10.11#ibcon#read 6, iclass 6, count 0 2006.285.21:57:10.11#ibcon#end of sib2, iclass 6, count 0 2006.285.21:57:10.11#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:57:10.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:57:10.11#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.21:57:10.11#ibcon#*before write, iclass 6, count 0 2006.285.21:57:10.11#ibcon#enter sib2, iclass 6, count 0 2006.285.21:57:10.11#ibcon#flushed, iclass 6, count 0 2006.285.21:57:10.11#ibcon#about to write, iclass 6, count 0 2006.285.21:57:10.11#ibcon#wrote, iclass 6, count 0 2006.285.21:57:10.11#ibcon#about to read 3, iclass 6, count 0 2006.285.21:57:10.14#ibcon#read 3, iclass 6, count 0 2006.285.21:57:10.14#ibcon#about to read 4, iclass 6, count 0 2006.285.21:57:10.14#ibcon#read 4, iclass 6, count 0 2006.285.21:57:10.14#ibcon#about to read 5, iclass 6, count 0 2006.285.21:57:10.14#ibcon#read 5, iclass 6, count 0 2006.285.21:57:10.14#ibcon#about to read 6, iclass 6, count 0 2006.285.21:57:10.14#ibcon#read 6, iclass 6, count 0 2006.285.21:57:10.14#ibcon#end of sib2, iclass 6, count 0 2006.285.21:57:10.14#ibcon#*after write, iclass 6, count 0 2006.285.21:57:10.14#ibcon#*before return 0, iclass 6, count 0 2006.285.21:57:10.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:57:10.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:57:10.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:57:10.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:57:10.15$vck44/va=7,4 2006.285.21:57:10.15#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.21:57:10.15#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.21:57:10.15#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:10.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:57:10.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:57:10.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:57:10.15#ibcon#enter wrdev, iclass 10, count 2 2006.285.21:57:10.15#ibcon#first serial, iclass 10, count 2 2006.285.21:57:10.15#ibcon#enter sib2, iclass 10, count 2 2006.285.21:57:10.15#ibcon#flushed, iclass 10, count 2 2006.285.21:57:10.15#ibcon#about to write, iclass 10, count 2 2006.285.21:57:10.15#ibcon#wrote, iclass 10, count 2 2006.285.21:57:10.15#ibcon#about to read 3, iclass 10, count 2 2006.285.21:57:10.16#ibcon#read 3, iclass 10, count 2 2006.285.21:57:10.16#ibcon#about to read 4, iclass 10, count 2 2006.285.21:57:10.16#ibcon#read 4, iclass 10, count 2 2006.285.21:57:10.16#ibcon#about to read 5, iclass 10, count 2 2006.285.21:57:10.16#ibcon#read 5, iclass 10, count 2 2006.285.21:57:10.16#ibcon#about to read 6, iclass 10, count 2 2006.285.21:57:10.16#ibcon#read 6, iclass 10, count 2 2006.285.21:57:10.16#ibcon#end of sib2, iclass 10, count 2 2006.285.21:57:10.16#ibcon#*mode == 0, iclass 10, count 2 2006.285.21:57:10.16#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.21:57:10.16#ibcon#[25=AT07-04\r\n] 2006.285.21:57:10.16#ibcon#*before write, iclass 10, count 2 2006.285.21:57:10.16#ibcon#enter sib2, iclass 10, count 2 2006.285.21:57:10.16#ibcon#flushed, iclass 10, count 2 2006.285.21:57:10.16#ibcon#about to write, iclass 10, count 2 2006.285.21:57:10.16#ibcon#wrote, iclass 10, count 2 2006.285.21:57:10.16#ibcon#about to read 3, iclass 10, count 2 2006.285.21:57:10.19#ibcon#read 3, iclass 10, count 2 2006.285.21:57:10.19#ibcon#about to read 4, iclass 10, count 2 2006.285.21:57:10.19#ibcon#read 4, iclass 10, count 2 2006.285.21:57:10.19#ibcon#about to read 5, iclass 10, count 2 2006.285.21:57:10.19#ibcon#read 5, iclass 10, count 2 2006.285.21:57:10.19#ibcon#about to read 6, iclass 10, count 2 2006.285.21:57:10.19#ibcon#read 6, iclass 10, count 2 2006.285.21:57:10.19#ibcon#end of sib2, iclass 10, count 2 2006.285.21:57:10.19#ibcon#*after write, iclass 10, count 2 2006.285.21:57:10.19#ibcon#*before return 0, iclass 10, count 2 2006.285.21:57:10.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:57:10.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:57:10.19#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.21:57:10.19#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:10.19#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:57:10.31#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:57:10.31#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:57:10.31#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:57:10.31#ibcon#first serial, iclass 10, count 0 2006.285.21:57:10.31#ibcon#enter sib2, iclass 10, count 0 2006.285.21:57:10.31#ibcon#flushed, iclass 10, count 0 2006.285.21:57:10.31#ibcon#about to write, iclass 10, count 0 2006.285.21:57:10.31#ibcon#wrote, iclass 10, count 0 2006.285.21:57:10.31#ibcon#about to read 3, iclass 10, count 0 2006.285.21:57:10.33#ibcon#read 3, iclass 10, count 0 2006.285.21:57:10.33#ibcon#about to read 4, iclass 10, count 0 2006.285.21:57:10.33#ibcon#read 4, iclass 10, count 0 2006.285.21:57:10.33#ibcon#about to read 5, iclass 10, count 0 2006.285.21:57:10.33#ibcon#read 5, iclass 10, count 0 2006.285.21:57:10.33#ibcon#about to read 6, iclass 10, count 0 2006.285.21:57:10.33#ibcon#read 6, iclass 10, count 0 2006.285.21:57:10.33#ibcon#end of sib2, iclass 10, count 0 2006.285.21:57:10.33#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:57:10.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:57:10.33#ibcon#[25=USB\r\n] 2006.285.21:57:10.33#ibcon#*before write, iclass 10, count 0 2006.285.21:57:10.33#ibcon#enter sib2, iclass 10, count 0 2006.285.21:57:10.33#ibcon#flushed, iclass 10, count 0 2006.285.21:57:10.33#ibcon#about to write, iclass 10, count 0 2006.285.21:57:10.33#ibcon#wrote, iclass 10, count 0 2006.285.21:57:10.33#ibcon#about to read 3, iclass 10, count 0 2006.285.21:57:10.36#ibcon#read 3, iclass 10, count 0 2006.285.21:57:10.36#ibcon#about to read 4, iclass 10, count 0 2006.285.21:57:10.36#ibcon#read 4, iclass 10, count 0 2006.285.21:57:10.36#ibcon#about to read 5, iclass 10, count 0 2006.285.21:57:10.36#ibcon#read 5, iclass 10, count 0 2006.285.21:57:10.36#ibcon#about to read 6, iclass 10, count 0 2006.285.21:57:10.36#ibcon#read 6, iclass 10, count 0 2006.285.21:57:10.36#ibcon#end of sib2, iclass 10, count 0 2006.285.21:57:10.36#ibcon#*after write, iclass 10, count 0 2006.285.21:57:10.36#ibcon#*before return 0, iclass 10, count 0 2006.285.21:57:10.36#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:57:10.36#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:57:10.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:57:10.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:57:10.36$vck44/valo=8,884.99 2006.285.21:57:10.36#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.21:57:10.36#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.21:57:10.36#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:10.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:57:10.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:57:10.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:57:10.36#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:57:10.36#ibcon#first serial, iclass 12, count 0 2006.285.21:57:10.36#ibcon#enter sib2, iclass 12, count 0 2006.285.21:57:10.36#ibcon#flushed, iclass 12, count 0 2006.285.21:57:10.36#ibcon#about to write, iclass 12, count 0 2006.285.21:57:10.36#ibcon#wrote, iclass 12, count 0 2006.285.21:57:10.36#ibcon#about to read 3, iclass 12, count 0 2006.285.21:57:10.38#ibcon#read 3, iclass 12, count 0 2006.285.21:57:10.38#ibcon#about to read 4, iclass 12, count 0 2006.285.21:57:10.38#ibcon#read 4, iclass 12, count 0 2006.285.21:57:10.38#ibcon#about to read 5, iclass 12, count 0 2006.285.21:57:10.38#ibcon#read 5, iclass 12, count 0 2006.285.21:57:10.38#ibcon#about to read 6, iclass 12, count 0 2006.285.21:57:10.38#ibcon#read 6, iclass 12, count 0 2006.285.21:57:10.38#ibcon#end of sib2, iclass 12, count 0 2006.285.21:57:10.38#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:57:10.38#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:57:10.38#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.21:57:10.38#ibcon#*before write, iclass 12, count 0 2006.285.21:57:10.38#ibcon#enter sib2, iclass 12, count 0 2006.285.21:57:10.38#ibcon#flushed, iclass 12, count 0 2006.285.21:57:10.38#ibcon#about to write, iclass 12, count 0 2006.285.21:57:10.38#ibcon#wrote, iclass 12, count 0 2006.285.21:57:10.38#ibcon#about to read 3, iclass 12, count 0 2006.285.21:57:10.42#ibcon#read 3, iclass 12, count 0 2006.285.21:57:10.42#ibcon#about to read 4, iclass 12, count 0 2006.285.21:57:10.42#ibcon#read 4, iclass 12, count 0 2006.285.21:57:10.42#ibcon#about to read 5, iclass 12, count 0 2006.285.21:57:10.42#ibcon#read 5, iclass 12, count 0 2006.285.21:57:10.42#ibcon#about to read 6, iclass 12, count 0 2006.285.21:57:10.42#ibcon#read 6, iclass 12, count 0 2006.285.21:57:10.42#ibcon#end of sib2, iclass 12, count 0 2006.285.21:57:10.42#ibcon#*after write, iclass 12, count 0 2006.285.21:57:10.42#ibcon#*before return 0, iclass 12, count 0 2006.285.21:57:10.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:57:10.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:57:10.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:57:10.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:57:10.42$vck44/va=8,3 2006.285.21:57:10.42#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.21:57:10.42#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.21:57:10.42#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:10.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:57:10.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:57:10.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:57:10.48#ibcon#enter wrdev, iclass 14, count 2 2006.285.21:57:10.48#ibcon#first serial, iclass 14, count 2 2006.285.21:57:10.48#ibcon#enter sib2, iclass 14, count 2 2006.285.21:57:10.48#ibcon#flushed, iclass 14, count 2 2006.285.21:57:10.48#ibcon#about to write, iclass 14, count 2 2006.285.21:57:10.48#ibcon#wrote, iclass 14, count 2 2006.285.21:57:10.48#ibcon#about to read 3, iclass 14, count 2 2006.285.21:57:10.50#ibcon#read 3, iclass 14, count 2 2006.285.21:57:10.50#ibcon#about to read 4, iclass 14, count 2 2006.285.21:57:10.50#ibcon#read 4, iclass 14, count 2 2006.285.21:57:10.50#ibcon#about to read 5, iclass 14, count 2 2006.285.21:57:10.50#ibcon#read 5, iclass 14, count 2 2006.285.21:57:10.50#ibcon#about to read 6, iclass 14, count 2 2006.285.21:57:10.50#ibcon#read 6, iclass 14, count 2 2006.285.21:57:10.50#ibcon#end of sib2, iclass 14, count 2 2006.285.21:57:10.50#ibcon#*mode == 0, iclass 14, count 2 2006.285.21:57:10.50#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.21:57:10.50#ibcon#[25=AT08-03\r\n] 2006.285.21:57:10.50#ibcon#*before write, iclass 14, count 2 2006.285.21:57:10.50#ibcon#enter sib2, iclass 14, count 2 2006.285.21:57:10.50#ibcon#flushed, iclass 14, count 2 2006.285.21:57:10.50#ibcon#about to write, iclass 14, count 2 2006.285.21:57:10.50#ibcon#wrote, iclass 14, count 2 2006.285.21:57:10.50#ibcon#about to read 3, iclass 14, count 2 2006.285.21:57:10.53#ibcon#read 3, iclass 14, count 2 2006.285.21:57:10.53#ibcon#about to read 4, iclass 14, count 2 2006.285.21:57:10.53#ibcon#read 4, iclass 14, count 2 2006.285.21:57:10.53#ibcon#about to read 5, iclass 14, count 2 2006.285.21:57:10.53#ibcon#read 5, iclass 14, count 2 2006.285.21:57:10.53#ibcon#about to read 6, iclass 14, count 2 2006.285.21:57:10.53#ibcon#read 6, iclass 14, count 2 2006.285.21:57:10.53#ibcon#end of sib2, iclass 14, count 2 2006.285.21:57:10.53#ibcon#*after write, iclass 14, count 2 2006.285.21:57:10.53#ibcon#*before return 0, iclass 14, count 2 2006.285.21:57:10.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:57:10.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:57:10.53#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.21:57:10.53#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:10.53#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:57:10.65#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:57:10.65#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:57:10.65#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:57:10.65#ibcon#first serial, iclass 14, count 0 2006.285.21:57:10.65#ibcon#enter sib2, iclass 14, count 0 2006.285.21:57:10.65#ibcon#flushed, iclass 14, count 0 2006.285.21:57:10.65#ibcon#about to write, iclass 14, count 0 2006.285.21:57:10.65#ibcon#wrote, iclass 14, count 0 2006.285.21:57:10.65#ibcon#about to read 3, iclass 14, count 0 2006.285.21:57:10.67#ibcon#read 3, iclass 14, count 0 2006.285.21:57:10.67#ibcon#about to read 4, iclass 14, count 0 2006.285.21:57:10.67#ibcon#read 4, iclass 14, count 0 2006.285.21:57:10.67#ibcon#about to read 5, iclass 14, count 0 2006.285.21:57:10.67#ibcon#read 5, iclass 14, count 0 2006.285.21:57:10.67#ibcon#about to read 6, iclass 14, count 0 2006.285.21:57:10.67#ibcon#read 6, iclass 14, count 0 2006.285.21:57:10.67#ibcon#end of sib2, iclass 14, count 0 2006.285.21:57:10.67#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:57:10.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:57:10.67#ibcon#[25=USB\r\n] 2006.285.21:57:10.67#ibcon#*before write, iclass 14, count 0 2006.285.21:57:10.67#ibcon#enter sib2, iclass 14, count 0 2006.285.21:57:10.67#ibcon#flushed, iclass 14, count 0 2006.285.21:57:10.67#ibcon#about to write, iclass 14, count 0 2006.285.21:57:10.67#ibcon#wrote, iclass 14, count 0 2006.285.21:57:10.67#ibcon#about to read 3, iclass 14, count 0 2006.285.21:57:10.70#ibcon#read 3, iclass 14, count 0 2006.285.21:57:10.70#ibcon#about to read 4, iclass 14, count 0 2006.285.21:57:10.70#ibcon#read 4, iclass 14, count 0 2006.285.21:57:10.70#ibcon#about to read 5, iclass 14, count 0 2006.285.21:57:10.70#ibcon#read 5, iclass 14, count 0 2006.285.21:57:10.70#ibcon#about to read 6, iclass 14, count 0 2006.285.21:57:10.70#ibcon#read 6, iclass 14, count 0 2006.285.21:57:10.70#ibcon#end of sib2, iclass 14, count 0 2006.285.21:57:10.70#ibcon#*after write, iclass 14, count 0 2006.285.21:57:10.70#ibcon#*before return 0, iclass 14, count 0 2006.285.21:57:10.70#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:57:10.70#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:57:10.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:57:10.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:57:10.70$vck44/vblo=1,629.99 2006.285.21:57:10.70#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.21:57:10.70#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.21:57:10.70#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:10.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:57:10.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:57:10.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:57:10.70#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:57:10.70#ibcon#first serial, iclass 16, count 0 2006.285.21:57:10.70#ibcon#enter sib2, iclass 16, count 0 2006.285.21:57:10.70#ibcon#flushed, iclass 16, count 0 2006.285.21:57:10.70#ibcon#about to write, iclass 16, count 0 2006.285.21:57:10.70#ibcon#wrote, iclass 16, count 0 2006.285.21:57:10.70#ibcon#about to read 3, iclass 16, count 0 2006.285.21:57:10.72#ibcon#read 3, iclass 16, count 0 2006.285.21:57:10.72#ibcon#about to read 4, iclass 16, count 0 2006.285.21:57:10.72#ibcon#read 4, iclass 16, count 0 2006.285.21:57:10.72#ibcon#about to read 5, iclass 16, count 0 2006.285.21:57:10.72#ibcon#read 5, iclass 16, count 0 2006.285.21:57:10.72#ibcon#about to read 6, iclass 16, count 0 2006.285.21:57:10.72#ibcon#read 6, iclass 16, count 0 2006.285.21:57:10.72#ibcon#end of sib2, iclass 16, count 0 2006.285.21:57:10.72#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:57:10.72#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:57:10.72#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.21:57:10.72#ibcon#*before write, iclass 16, count 0 2006.285.21:57:10.72#ibcon#enter sib2, iclass 16, count 0 2006.285.21:57:10.72#ibcon#flushed, iclass 16, count 0 2006.285.21:57:10.72#ibcon#about to write, iclass 16, count 0 2006.285.21:57:10.72#ibcon#wrote, iclass 16, count 0 2006.285.21:57:10.72#ibcon#about to read 3, iclass 16, count 0 2006.285.21:57:10.76#ibcon#read 3, iclass 16, count 0 2006.285.21:57:10.76#ibcon#about to read 4, iclass 16, count 0 2006.285.21:57:10.76#ibcon#read 4, iclass 16, count 0 2006.285.21:57:10.76#ibcon#about to read 5, iclass 16, count 0 2006.285.21:57:10.76#ibcon#read 5, iclass 16, count 0 2006.285.21:57:10.76#ibcon#about to read 6, iclass 16, count 0 2006.285.21:57:10.76#ibcon#read 6, iclass 16, count 0 2006.285.21:57:10.76#ibcon#end of sib2, iclass 16, count 0 2006.285.21:57:10.76#ibcon#*after write, iclass 16, count 0 2006.285.21:57:10.76#ibcon#*before return 0, iclass 16, count 0 2006.285.21:57:10.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:57:10.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:57:10.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:57:10.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:57:10.76$vck44/vb=1,4 2006.285.21:57:10.76#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.21:57:10.76#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.21:57:10.76#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:10.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:57:10.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:57:10.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:57:10.76#ibcon#enter wrdev, iclass 18, count 2 2006.285.21:57:10.76#ibcon#first serial, iclass 18, count 2 2006.285.21:57:10.76#ibcon#enter sib2, iclass 18, count 2 2006.285.21:57:10.76#ibcon#flushed, iclass 18, count 2 2006.285.21:57:10.76#ibcon#about to write, iclass 18, count 2 2006.285.21:57:10.76#ibcon#wrote, iclass 18, count 2 2006.285.21:57:10.76#ibcon#about to read 3, iclass 18, count 2 2006.285.21:57:10.78#ibcon#read 3, iclass 18, count 2 2006.285.21:57:10.78#ibcon#about to read 4, iclass 18, count 2 2006.285.21:57:10.78#ibcon#read 4, iclass 18, count 2 2006.285.21:57:10.78#ibcon#about to read 5, iclass 18, count 2 2006.285.21:57:10.78#ibcon#read 5, iclass 18, count 2 2006.285.21:57:10.78#ibcon#about to read 6, iclass 18, count 2 2006.285.21:57:10.78#ibcon#read 6, iclass 18, count 2 2006.285.21:57:10.78#ibcon#end of sib2, iclass 18, count 2 2006.285.21:57:10.78#ibcon#*mode == 0, iclass 18, count 2 2006.285.21:57:10.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.21:57:10.78#ibcon#[27=AT01-04\r\n] 2006.285.21:57:10.78#ibcon#*before write, iclass 18, count 2 2006.285.21:57:10.78#ibcon#enter sib2, iclass 18, count 2 2006.285.21:57:10.78#ibcon#flushed, iclass 18, count 2 2006.285.21:57:10.78#ibcon#about to write, iclass 18, count 2 2006.285.21:57:10.78#ibcon#wrote, iclass 18, count 2 2006.285.21:57:10.78#ibcon#about to read 3, iclass 18, count 2 2006.285.21:57:10.81#ibcon#read 3, iclass 18, count 2 2006.285.21:57:10.81#ibcon#about to read 4, iclass 18, count 2 2006.285.21:57:10.81#ibcon#read 4, iclass 18, count 2 2006.285.21:57:10.81#ibcon#about to read 5, iclass 18, count 2 2006.285.21:57:10.81#ibcon#read 5, iclass 18, count 2 2006.285.21:57:10.81#ibcon#about to read 6, iclass 18, count 2 2006.285.21:57:10.81#ibcon#read 6, iclass 18, count 2 2006.285.21:57:10.81#ibcon#end of sib2, iclass 18, count 2 2006.285.21:57:10.81#ibcon#*after write, iclass 18, count 2 2006.285.21:57:10.81#ibcon#*before return 0, iclass 18, count 2 2006.285.21:57:10.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:57:10.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.21:57:10.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.21:57:10.81#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:10.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:57:10.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:57:10.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:57:10.93#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:57:10.93#ibcon#first serial, iclass 18, count 0 2006.285.21:57:10.93#ibcon#enter sib2, iclass 18, count 0 2006.285.21:57:10.93#ibcon#flushed, iclass 18, count 0 2006.285.21:57:10.93#ibcon#about to write, iclass 18, count 0 2006.285.21:57:10.93#ibcon#wrote, iclass 18, count 0 2006.285.21:57:10.93#ibcon#about to read 3, iclass 18, count 0 2006.285.21:57:10.95#ibcon#read 3, iclass 18, count 0 2006.285.21:57:10.95#ibcon#about to read 4, iclass 18, count 0 2006.285.21:57:10.95#ibcon#read 4, iclass 18, count 0 2006.285.21:57:10.97#ibcon#about to read 5, iclass 18, count 0 2006.285.21:57:10.97#ibcon#read 5, iclass 18, count 0 2006.285.21:57:10.97#ibcon#about to read 6, iclass 18, count 0 2006.285.21:57:10.97#ibcon#read 6, iclass 18, count 0 2006.285.21:57:10.97#ibcon#end of sib2, iclass 18, count 0 2006.285.21:57:10.97#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:57:10.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:57:10.97#ibcon#[27=USB\r\n] 2006.285.21:57:10.97#ibcon#*before write, iclass 18, count 0 2006.285.21:57:10.97#ibcon#enter sib2, iclass 18, count 0 2006.285.21:57:10.97#ibcon#flushed, iclass 18, count 0 2006.285.21:57:10.97#ibcon#about to write, iclass 18, count 0 2006.285.21:57:10.97#ibcon#wrote, iclass 18, count 0 2006.285.21:57:10.97#ibcon#about to read 3, iclass 18, count 0 2006.285.21:57:11.00#ibcon#read 3, iclass 18, count 0 2006.285.21:57:11.00#ibcon#about to read 4, iclass 18, count 0 2006.285.21:57:11.00#ibcon#read 4, iclass 18, count 0 2006.285.21:57:11.00#ibcon#about to read 5, iclass 18, count 0 2006.285.21:57:11.00#ibcon#read 5, iclass 18, count 0 2006.285.21:57:11.00#ibcon#about to read 6, iclass 18, count 0 2006.285.21:57:11.00#ibcon#read 6, iclass 18, count 0 2006.285.21:57:11.00#ibcon#end of sib2, iclass 18, count 0 2006.285.21:57:11.00#ibcon#*after write, iclass 18, count 0 2006.285.21:57:11.00#ibcon#*before return 0, iclass 18, count 0 2006.285.21:57:11.00#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:57:11.00#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.21:57:11.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:57:11.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:57:11.00$vck44/vblo=2,634.99 2006.285.21:57:11.00#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.21:57:11.00#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.21:57:11.00#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:11.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:57:11.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:57:11.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:57:11.00#ibcon#enter wrdev, iclass 20, count 0 2006.285.21:57:11.00#ibcon#first serial, iclass 20, count 0 2006.285.21:57:11.00#ibcon#enter sib2, iclass 20, count 0 2006.285.21:57:11.00#ibcon#flushed, iclass 20, count 0 2006.285.21:57:11.00#ibcon#about to write, iclass 20, count 0 2006.285.21:57:11.00#ibcon#wrote, iclass 20, count 0 2006.285.21:57:11.00#ibcon#about to read 3, iclass 20, count 0 2006.285.21:57:11.02#ibcon#read 3, iclass 20, count 0 2006.285.21:57:11.02#ibcon#about to read 4, iclass 20, count 0 2006.285.21:57:11.02#ibcon#read 4, iclass 20, count 0 2006.285.21:57:11.02#ibcon#about to read 5, iclass 20, count 0 2006.285.21:57:11.02#ibcon#read 5, iclass 20, count 0 2006.285.21:57:11.02#ibcon#about to read 6, iclass 20, count 0 2006.285.21:57:11.02#ibcon#read 6, iclass 20, count 0 2006.285.21:57:11.02#ibcon#end of sib2, iclass 20, count 0 2006.285.21:57:11.02#ibcon#*mode == 0, iclass 20, count 0 2006.285.21:57:11.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.21:57:11.02#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.21:57:11.02#ibcon#*before write, iclass 20, count 0 2006.285.21:57:11.02#ibcon#enter sib2, iclass 20, count 0 2006.285.21:57:11.02#ibcon#flushed, iclass 20, count 0 2006.285.21:57:11.02#ibcon#about to write, iclass 20, count 0 2006.285.21:57:11.02#ibcon#wrote, iclass 20, count 0 2006.285.21:57:11.02#ibcon#about to read 3, iclass 20, count 0 2006.285.21:57:11.06#ibcon#read 3, iclass 20, count 0 2006.285.21:57:11.06#ibcon#about to read 4, iclass 20, count 0 2006.285.21:57:11.06#ibcon#read 4, iclass 20, count 0 2006.285.21:57:11.06#ibcon#about to read 5, iclass 20, count 0 2006.285.21:57:11.06#ibcon#read 5, iclass 20, count 0 2006.285.21:57:11.06#ibcon#about to read 6, iclass 20, count 0 2006.285.21:57:11.06#ibcon#read 6, iclass 20, count 0 2006.285.21:57:11.06#ibcon#end of sib2, iclass 20, count 0 2006.285.21:57:11.06#ibcon#*after write, iclass 20, count 0 2006.285.21:57:11.06#ibcon#*before return 0, iclass 20, count 0 2006.285.21:57:11.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:57:11.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.21:57:11.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.21:57:11.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.21:57:11.06$vck44/vb=2,5 2006.285.21:57:11.06#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.21:57:11.06#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.21:57:11.06#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:11.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:57:11.07#abcon#<5=/15 0.7 1.2 15.581001016.0\r\n> 2006.285.21:57:11.09#abcon#{5=INTERFACE CLEAR} 2006.285.21:57:11.12#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:57:11.12#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:57:11.12#ibcon#enter wrdev, iclass 23, count 2 2006.285.21:57:11.12#ibcon#first serial, iclass 23, count 2 2006.285.21:57:11.12#ibcon#enter sib2, iclass 23, count 2 2006.285.21:57:11.12#ibcon#flushed, iclass 23, count 2 2006.285.21:57:11.12#ibcon#about to write, iclass 23, count 2 2006.285.21:57:11.12#ibcon#wrote, iclass 23, count 2 2006.285.21:57:11.12#ibcon#about to read 3, iclass 23, count 2 2006.285.21:57:11.14#ibcon#read 3, iclass 23, count 2 2006.285.21:57:11.14#ibcon#about to read 4, iclass 23, count 2 2006.285.21:57:11.14#ibcon#read 4, iclass 23, count 2 2006.285.21:57:11.14#ibcon#about to read 5, iclass 23, count 2 2006.285.21:57:11.14#ibcon#read 5, iclass 23, count 2 2006.285.21:57:11.14#ibcon#about to read 6, iclass 23, count 2 2006.285.21:57:11.14#ibcon#read 6, iclass 23, count 2 2006.285.21:57:11.14#ibcon#end of sib2, iclass 23, count 2 2006.285.21:57:11.14#ibcon#*mode == 0, iclass 23, count 2 2006.285.21:57:11.14#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.21:57:11.14#ibcon#[27=AT02-05\r\n] 2006.285.21:57:11.14#ibcon#*before write, iclass 23, count 2 2006.285.21:57:11.14#ibcon#enter sib2, iclass 23, count 2 2006.285.21:57:11.14#ibcon#flushed, iclass 23, count 2 2006.285.21:57:11.14#ibcon#about to write, iclass 23, count 2 2006.285.21:57:11.14#ibcon#wrote, iclass 23, count 2 2006.285.21:57:11.14#ibcon#about to read 3, iclass 23, count 2 2006.285.21:57:11.15#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:57:11.17#ibcon#read 3, iclass 23, count 2 2006.285.21:57:11.17#ibcon#about to read 4, iclass 23, count 2 2006.285.21:57:11.17#ibcon#read 4, iclass 23, count 2 2006.285.21:57:11.17#ibcon#about to read 5, iclass 23, count 2 2006.285.21:57:11.17#ibcon#read 5, iclass 23, count 2 2006.285.21:57:11.17#ibcon#about to read 6, iclass 23, count 2 2006.285.21:57:11.17#ibcon#read 6, iclass 23, count 2 2006.285.21:57:11.17#ibcon#end of sib2, iclass 23, count 2 2006.285.21:57:11.17#ibcon#*after write, iclass 23, count 2 2006.285.21:57:11.17#ibcon#*before return 0, iclass 23, count 2 2006.285.21:57:11.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:57:11.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.21:57:11.17#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.21:57:11.17#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:11.17#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:57:11.29#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:57:11.29#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:57:11.29#ibcon#enter wrdev, iclass 23, count 0 2006.285.21:57:11.29#ibcon#first serial, iclass 23, count 0 2006.285.21:57:11.29#ibcon#enter sib2, iclass 23, count 0 2006.285.21:57:11.29#ibcon#flushed, iclass 23, count 0 2006.285.21:57:11.29#ibcon#about to write, iclass 23, count 0 2006.285.21:57:11.29#ibcon#wrote, iclass 23, count 0 2006.285.21:57:11.29#ibcon#about to read 3, iclass 23, count 0 2006.285.21:57:11.31#ibcon#read 3, iclass 23, count 0 2006.285.21:57:11.31#ibcon#about to read 4, iclass 23, count 0 2006.285.21:57:11.31#ibcon#read 4, iclass 23, count 0 2006.285.21:57:11.31#ibcon#about to read 5, iclass 23, count 0 2006.285.21:57:11.31#ibcon#read 5, iclass 23, count 0 2006.285.21:57:11.31#ibcon#about to read 6, iclass 23, count 0 2006.285.21:57:11.31#ibcon#read 6, iclass 23, count 0 2006.285.21:57:11.31#ibcon#end of sib2, iclass 23, count 0 2006.285.21:57:11.31#ibcon#*mode == 0, iclass 23, count 0 2006.285.21:57:11.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.21:57:11.31#ibcon#[27=USB\r\n] 2006.285.21:57:11.31#ibcon#*before write, iclass 23, count 0 2006.285.21:57:11.31#ibcon#enter sib2, iclass 23, count 0 2006.285.21:57:11.31#ibcon#flushed, iclass 23, count 0 2006.285.21:57:11.31#ibcon#about to write, iclass 23, count 0 2006.285.21:57:11.31#ibcon#wrote, iclass 23, count 0 2006.285.21:57:11.31#ibcon#about to read 3, iclass 23, count 0 2006.285.21:57:11.34#ibcon#read 3, iclass 23, count 0 2006.285.21:57:11.34#ibcon#about to read 4, iclass 23, count 0 2006.285.21:57:11.34#ibcon#read 4, iclass 23, count 0 2006.285.21:57:11.34#ibcon#about to read 5, iclass 23, count 0 2006.285.21:57:11.34#ibcon#read 5, iclass 23, count 0 2006.285.21:57:11.34#ibcon#about to read 6, iclass 23, count 0 2006.285.21:57:11.34#ibcon#read 6, iclass 23, count 0 2006.285.21:57:11.34#ibcon#end of sib2, iclass 23, count 0 2006.285.21:57:11.34#ibcon#*after write, iclass 23, count 0 2006.285.21:57:11.34#ibcon#*before return 0, iclass 23, count 0 2006.285.21:57:11.34#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:57:11.34#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.21:57:11.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.21:57:11.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.21:57:11.34$vck44/vblo=3,649.99 2006.285.21:57:11.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.21:57:11.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.21:57:11.34#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:11.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:57:11.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:57:11.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:57:11.34#ibcon#enter wrdev, iclass 28, count 0 2006.285.21:57:11.34#ibcon#first serial, iclass 28, count 0 2006.285.21:57:11.34#ibcon#enter sib2, iclass 28, count 0 2006.285.21:57:11.34#ibcon#flushed, iclass 28, count 0 2006.285.21:57:11.34#ibcon#about to write, iclass 28, count 0 2006.285.21:57:11.34#ibcon#wrote, iclass 28, count 0 2006.285.21:57:11.34#ibcon#about to read 3, iclass 28, count 0 2006.285.21:57:11.36#ibcon#read 3, iclass 28, count 0 2006.285.21:57:11.36#ibcon#about to read 4, iclass 28, count 0 2006.285.21:57:11.36#ibcon#read 4, iclass 28, count 0 2006.285.21:57:11.36#ibcon#about to read 5, iclass 28, count 0 2006.285.21:57:11.36#ibcon#read 5, iclass 28, count 0 2006.285.21:57:11.36#ibcon#about to read 6, iclass 28, count 0 2006.285.21:57:11.36#ibcon#read 6, iclass 28, count 0 2006.285.21:57:11.36#ibcon#end of sib2, iclass 28, count 0 2006.285.21:57:11.36#ibcon#*mode == 0, iclass 28, count 0 2006.285.21:57:11.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.21:57:11.36#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.21:57:11.36#ibcon#*before write, iclass 28, count 0 2006.285.21:57:11.36#ibcon#enter sib2, iclass 28, count 0 2006.285.21:57:11.36#ibcon#flushed, iclass 28, count 0 2006.285.21:57:11.36#ibcon#about to write, iclass 28, count 0 2006.285.21:57:11.36#ibcon#wrote, iclass 28, count 0 2006.285.21:57:11.36#ibcon#about to read 3, iclass 28, count 0 2006.285.21:57:11.40#ibcon#read 3, iclass 28, count 0 2006.285.21:57:11.40#ibcon#about to read 4, iclass 28, count 0 2006.285.21:57:11.40#ibcon#read 4, iclass 28, count 0 2006.285.21:57:11.40#ibcon#about to read 5, iclass 28, count 0 2006.285.21:57:11.40#ibcon#read 5, iclass 28, count 0 2006.285.21:57:11.40#ibcon#about to read 6, iclass 28, count 0 2006.285.21:57:11.40#ibcon#read 6, iclass 28, count 0 2006.285.21:57:11.40#ibcon#end of sib2, iclass 28, count 0 2006.285.21:57:11.40#ibcon#*after write, iclass 28, count 0 2006.285.21:57:11.40#ibcon#*before return 0, iclass 28, count 0 2006.285.21:57:11.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:57:11.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.21:57:11.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.21:57:11.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.21:57:11.40$vck44/vb=3,4 2006.285.21:57:11.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.21:57:11.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.21:57:11.40#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:11.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:57:11.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:57:11.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:57:11.46#ibcon#enter wrdev, iclass 30, count 2 2006.285.21:57:11.46#ibcon#first serial, iclass 30, count 2 2006.285.21:57:11.46#ibcon#enter sib2, iclass 30, count 2 2006.285.21:57:11.46#ibcon#flushed, iclass 30, count 2 2006.285.21:57:11.46#ibcon#about to write, iclass 30, count 2 2006.285.21:57:11.46#ibcon#wrote, iclass 30, count 2 2006.285.21:57:11.46#ibcon#about to read 3, iclass 30, count 2 2006.285.21:57:11.48#ibcon#read 3, iclass 30, count 2 2006.285.21:57:11.48#ibcon#about to read 4, iclass 30, count 2 2006.285.21:57:11.48#ibcon#read 4, iclass 30, count 2 2006.285.21:57:11.48#ibcon#about to read 5, iclass 30, count 2 2006.285.21:57:11.48#ibcon#read 5, iclass 30, count 2 2006.285.21:57:11.48#ibcon#about to read 6, iclass 30, count 2 2006.285.21:57:11.48#ibcon#read 6, iclass 30, count 2 2006.285.21:57:11.48#ibcon#end of sib2, iclass 30, count 2 2006.285.21:57:11.48#ibcon#*mode == 0, iclass 30, count 2 2006.285.21:57:11.48#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.21:57:11.48#ibcon#[27=AT03-04\r\n] 2006.285.21:57:11.48#ibcon#*before write, iclass 30, count 2 2006.285.21:57:11.48#ibcon#enter sib2, iclass 30, count 2 2006.285.21:57:11.48#ibcon#flushed, iclass 30, count 2 2006.285.21:57:11.48#ibcon#about to write, iclass 30, count 2 2006.285.21:57:11.48#ibcon#wrote, iclass 30, count 2 2006.285.21:57:11.48#ibcon#about to read 3, iclass 30, count 2 2006.285.21:57:11.51#ibcon#read 3, iclass 30, count 2 2006.285.21:57:11.51#ibcon#about to read 4, iclass 30, count 2 2006.285.21:57:11.51#ibcon#read 4, iclass 30, count 2 2006.285.21:57:11.51#ibcon#about to read 5, iclass 30, count 2 2006.285.21:57:11.51#ibcon#read 5, iclass 30, count 2 2006.285.21:57:11.51#ibcon#about to read 6, iclass 30, count 2 2006.285.21:57:11.51#ibcon#read 6, iclass 30, count 2 2006.285.21:57:11.51#ibcon#end of sib2, iclass 30, count 2 2006.285.21:57:11.51#ibcon#*after write, iclass 30, count 2 2006.285.21:57:11.51#ibcon#*before return 0, iclass 30, count 2 2006.285.21:57:11.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:57:11.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.21:57:11.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.21:57:11.51#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:11.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:57:11.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:57:11.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:57:11.63#ibcon#enter wrdev, iclass 30, count 0 2006.285.21:57:11.63#ibcon#first serial, iclass 30, count 0 2006.285.21:57:11.63#ibcon#enter sib2, iclass 30, count 0 2006.285.21:57:11.63#ibcon#flushed, iclass 30, count 0 2006.285.21:57:11.63#ibcon#about to write, iclass 30, count 0 2006.285.21:57:11.63#ibcon#wrote, iclass 30, count 0 2006.285.21:57:11.63#ibcon#about to read 3, iclass 30, count 0 2006.285.21:57:11.65#ibcon#read 3, iclass 30, count 0 2006.285.21:57:11.65#ibcon#about to read 4, iclass 30, count 0 2006.285.21:57:11.65#ibcon#read 4, iclass 30, count 0 2006.285.21:57:11.65#ibcon#about to read 5, iclass 30, count 0 2006.285.21:57:11.65#ibcon#read 5, iclass 30, count 0 2006.285.21:57:11.65#ibcon#about to read 6, iclass 30, count 0 2006.285.21:57:11.65#ibcon#read 6, iclass 30, count 0 2006.285.21:57:11.65#ibcon#end of sib2, iclass 30, count 0 2006.285.21:57:11.65#ibcon#*mode == 0, iclass 30, count 0 2006.285.21:57:11.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.21:57:11.65#ibcon#[27=USB\r\n] 2006.285.21:57:11.65#ibcon#*before write, iclass 30, count 0 2006.285.21:57:11.65#ibcon#enter sib2, iclass 30, count 0 2006.285.21:57:11.65#ibcon#flushed, iclass 30, count 0 2006.285.21:57:11.65#ibcon#about to write, iclass 30, count 0 2006.285.21:57:11.65#ibcon#wrote, iclass 30, count 0 2006.285.21:57:11.65#ibcon#about to read 3, iclass 30, count 0 2006.285.21:57:11.68#ibcon#read 3, iclass 30, count 0 2006.285.21:57:11.68#ibcon#about to read 4, iclass 30, count 0 2006.285.21:57:11.68#ibcon#read 4, iclass 30, count 0 2006.285.21:57:11.68#ibcon#about to read 5, iclass 30, count 0 2006.285.21:57:11.68#ibcon#read 5, iclass 30, count 0 2006.285.21:57:11.68#ibcon#about to read 6, iclass 30, count 0 2006.285.21:57:11.68#ibcon#read 6, iclass 30, count 0 2006.285.21:57:11.68#ibcon#end of sib2, iclass 30, count 0 2006.285.21:57:11.68#ibcon#*after write, iclass 30, count 0 2006.285.21:57:11.68#ibcon#*before return 0, iclass 30, count 0 2006.285.21:57:11.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:57:11.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.21:57:11.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.21:57:11.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.21:57:11.68$vck44/vblo=4,679.99 2006.285.21:57:11.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.21:57:11.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.21:57:11.68#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:11.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:57:11.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:57:11.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:57:11.68#ibcon#enter wrdev, iclass 32, count 0 2006.285.21:57:11.68#ibcon#first serial, iclass 32, count 0 2006.285.21:57:11.68#ibcon#enter sib2, iclass 32, count 0 2006.285.21:57:11.68#ibcon#flushed, iclass 32, count 0 2006.285.21:57:11.68#ibcon#about to write, iclass 32, count 0 2006.285.21:57:11.68#ibcon#wrote, iclass 32, count 0 2006.285.21:57:11.68#ibcon#about to read 3, iclass 32, count 0 2006.285.21:57:11.70#ibcon#read 3, iclass 32, count 0 2006.285.21:57:11.70#ibcon#about to read 4, iclass 32, count 0 2006.285.21:57:11.70#ibcon#read 4, iclass 32, count 0 2006.285.21:57:11.70#ibcon#about to read 5, iclass 32, count 0 2006.285.21:57:11.70#ibcon#read 5, iclass 32, count 0 2006.285.21:57:11.70#ibcon#about to read 6, iclass 32, count 0 2006.285.21:57:11.70#ibcon#read 6, iclass 32, count 0 2006.285.21:57:11.70#ibcon#end of sib2, iclass 32, count 0 2006.285.21:57:11.70#ibcon#*mode == 0, iclass 32, count 0 2006.285.21:57:11.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.21:57:11.70#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.21:57:11.70#ibcon#*before write, iclass 32, count 0 2006.285.21:57:11.70#ibcon#enter sib2, iclass 32, count 0 2006.285.21:57:11.70#ibcon#flushed, iclass 32, count 0 2006.285.21:57:11.70#ibcon#about to write, iclass 32, count 0 2006.285.21:57:11.70#ibcon#wrote, iclass 32, count 0 2006.285.21:57:11.70#ibcon#about to read 3, iclass 32, count 0 2006.285.21:57:11.74#ibcon#read 3, iclass 32, count 0 2006.285.21:57:11.74#ibcon#about to read 4, iclass 32, count 0 2006.285.21:57:11.74#ibcon#read 4, iclass 32, count 0 2006.285.21:57:11.74#ibcon#about to read 5, iclass 32, count 0 2006.285.21:57:11.74#ibcon#read 5, iclass 32, count 0 2006.285.21:57:11.74#ibcon#about to read 6, iclass 32, count 0 2006.285.21:57:11.74#ibcon#read 6, iclass 32, count 0 2006.285.21:57:11.74#ibcon#end of sib2, iclass 32, count 0 2006.285.21:57:11.74#ibcon#*after write, iclass 32, count 0 2006.285.21:57:11.74#ibcon#*before return 0, iclass 32, count 0 2006.285.21:57:11.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:57:11.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.21:57:11.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.21:57:11.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.21:57:11.74$vck44/vb=4,5 2006.285.21:57:11.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.21:57:11.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.21:57:11.74#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:11.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:57:11.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:57:11.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:57:11.80#ibcon#enter wrdev, iclass 34, count 2 2006.285.21:57:11.80#ibcon#first serial, iclass 34, count 2 2006.285.21:57:11.80#ibcon#enter sib2, iclass 34, count 2 2006.285.21:57:11.80#ibcon#flushed, iclass 34, count 2 2006.285.21:57:11.80#ibcon#about to write, iclass 34, count 2 2006.285.21:57:11.80#ibcon#wrote, iclass 34, count 2 2006.285.21:57:11.80#ibcon#about to read 3, iclass 34, count 2 2006.285.21:57:11.82#ibcon#read 3, iclass 34, count 2 2006.285.21:57:11.82#ibcon#about to read 4, iclass 34, count 2 2006.285.21:57:11.82#ibcon#read 4, iclass 34, count 2 2006.285.21:57:11.82#ibcon#about to read 5, iclass 34, count 2 2006.285.21:57:11.82#ibcon#read 5, iclass 34, count 2 2006.285.21:57:11.82#ibcon#about to read 6, iclass 34, count 2 2006.285.21:57:11.82#ibcon#read 6, iclass 34, count 2 2006.285.21:57:11.82#ibcon#end of sib2, iclass 34, count 2 2006.285.21:57:11.82#ibcon#*mode == 0, iclass 34, count 2 2006.285.21:57:11.82#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.21:57:11.82#ibcon#[27=AT04-05\r\n] 2006.285.21:57:11.82#ibcon#*before write, iclass 34, count 2 2006.285.21:57:11.82#ibcon#enter sib2, iclass 34, count 2 2006.285.21:57:11.82#ibcon#flushed, iclass 34, count 2 2006.285.21:57:11.82#ibcon#about to write, iclass 34, count 2 2006.285.21:57:11.82#ibcon#wrote, iclass 34, count 2 2006.285.21:57:11.82#ibcon#about to read 3, iclass 34, count 2 2006.285.21:57:11.85#ibcon#read 3, iclass 34, count 2 2006.285.21:57:11.85#ibcon#about to read 4, iclass 34, count 2 2006.285.21:57:11.85#ibcon#read 4, iclass 34, count 2 2006.285.21:57:11.85#ibcon#about to read 5, iclass 34, count 2 2006.285.21:57:11.85#ibcon#read 5, iclass 34, count 2 2006.285.21:57:11.85#ibcon#about to read 6, iclass 34, count 2 2006.285.21:57:11.85#ibcon#read 6, iclass 34, count 2 2006.285.21:57:11.85#ibcon#end of sib2, iclass 34, count 2 2006.285.21:57:11.85#ibcon#*after write, iclass 34, count 2 2006.285.21:57:11.85#ibcon#*before return 0, iclass 34, count 2 2006.285.21:57:11.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:57:11.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.21:57:11.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.21:57:11.85#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:11.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:57:11.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:57:12.31#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:57:12.31#ibcon#enter wrdev, iclass 34, count 0 2006.285.21:57:12.31#ibcon#first serial, iclass 34, count 0 2006.285.21:57:12.31#ibcon#enter sib2, iclass 34, count 0 2006.285.21:57:12.31#ibcon#flushed, iclass 34, count 0 2006.285.21:57:12.31#ibcon#about to write, iclass 34, count 0 2006.285.21:57:12.31#ibcon#wrote, iclass 34, count 0 2006.285.21:57:12.31#ibcon#about to read 3, iclass 34, count 0 2006.285.21:57:12.32#ibcon#read 3, iclass 34, count 0 2006.285.21:57:12.32#ibcon#about to read 4, iclass 34, count 0 2006.285.21:57:12.32#ibcon#read 4, iclass 34, count 0 2006.285.21:57:12.32#ibcon#about to read 5, iclass 34, count 0 2006.285.21:57:12.32#ibcon#read 5, iclass 34, count 0 2006.285.21:57:12.32#ibcon#about to read 6, iclass 34, count 0 2006.285.21:57:12.32#ibcon#read 6, iclass 34, count 0 2006.285.21:57:12.32#ibcon#end of sib2, iclass 34, count 0 2006.285.21:57:12.32#ibcon#*mode == 0, iclass 34, count 0 2006.285.21:57:12.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.21:57:12.32#ibcon#[27=USB\r\n] 2006.285.21:57:12.32#ibcon#*before write, iclass 34, count 0 2006.285.21:57:12.32#ibcon#enter sib2, iclass 34, count 0 2006.285.21:57:12.32#ibcon#flushed, iclass 34, count 0 2006.285.21:57:12.32#ibcon#about to write, iclass 34, count 0 2006.285.21:57:12.32#ibcon#wrote, iclass 34, count 0 2006.285.21:57:12.32#ibcon#about to read 3, iclass 34, count 0 2006.285.21:57:12.35#ibcon#read 3, iclass 34, count 0 2006.285.21:57:12.35#ibcon#about to read 4, iclass 34, count 0 2006.285.21:57:12.35#ibcon#read 4, iclass 34, count 0 2006.285.21:57:12.35#ibcon#about to read 5, iclass 34, count 0 2006.285.21:57:12.35#ibcon#read 5, iclass 34, count 0 2006.285.21:57:12.35#ibcon#about to read 6, iclass 34, count 0 2006.285.21:57:12.35#ibcon#read 6, iclass 34, count 0 2006.285.21:57:12.35#ibcon#end of sib2, iclass 34, count 0 2006.285.21:57:12.35#ibcon#*after write, iclass 34, count 0 2006.285.21:57:12.35#ibcon#*before return 0, iclass 34, count 0 2006.285.21:57:12.35#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:57:12.35#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.21:57:12.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.21:57:12.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.21:57:12.35$vck44/vblo=5,709.99 2006.285.21:57:12.35#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.21:57:12.35#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.21:57:12.35#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:12.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:57:12.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:57:12.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:57:12.35#ibcon#enter wrdev, iclass 36, count 0 2006.285.21:57:12.35#ibcon#first serial, iclass 36, count 0 2006.285.21:57:12.35#ibcon#enter sib2, iclass 36, count 0 2006.285.21:57:12.35#ibcon#flushed, iclass 36, count 0 2006.285.21:57:12.35#ibcon#about to write, iclass 36, count 0 2006.285.21:57:12.35#ibcon#wrote, iclass 36, count 0 2006.285.21:57:12.35#ibcon#about to read 3, iclass 36, count 0 2006.285.21:57:12.37#ibcon#read 3, iclass 36, count 0 2006.285.21:57:12.37#ibcon#about to read 4, iclass 36, count 0 2006.285.21:57:12.37#ibcon#read 4, iclass 36, count 0 2006.285.21:57:12.37#ibcon#about to read 5, iclass 36, count 0 2006.285.21:57:12.37#ibcon#read 5, iclass 36, count 0 2006.285.21:57:12.37#ibcon#about to read 6, iclass 36, count 0 2006.285.21:57:12.37#ibcon#read 6, iclass 36, count 0 2006.285.21:57:12.37#ibcon#end of sib2, iclass 36, count 0 2006.285.21:57:12.37#ibcon#*mode == 0, iclass 36, count 0 2006.285.21:57:12.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.21:57:12.37#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.21:57:12.37#ibcon#*before write, iclass 36, count 0 2006.285.21:57:12.37#ibcon#enter sib2, iclass 36, count 0 2006.285.21:57:12.37#ibcon#flushed, iclass 36, count 0 2006.285.21:57:12.37#ibcon#about to write, iclass 36, count 0 2006.285.21:57:12.37#ibcon#wrote, iclass 36, count 0 2006.285.21:57:12.37#ibcon#about to read 3, iclass 36, count 0 2006.285.21:57:12.41#ibcon#read 3, iclass 36, count 0 2006.285.21:57:12.41#ibcon#about to read 4, iclass 36, count 0 2006.285.21:57:12.41#ibcon#read 4, iclass 36, count 0 2006.285.21:57:12.41#ibcon#about to read 5, iclass 36, count 0 2006.285.21:57:12.41#ibcon#read 5, iclass 36, count 0 2006.285.21:57:12.41#ibcon#about to read 6, iclass 36, count 0 2006.285.21:57:12.41#ibcon#read 6, iclass 36, count 0 2006.285.21:57:12.41#ibcon#end of sib2, iclass 36, count 0 2006.285.21:57:12.41#ibcon#*after write, iclass 36, count 0 2006.285.21:57:12.41#ibcon#*before return 0, iclass 36, count 0 2006.285.21:57:12.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:57:12.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.21:57:12.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.21:57:12.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.21:57:12.41$vck44/vb=5,4 2006.285.21:57:12.41#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.21:57:12.41#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.21:57:12.41#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:12.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:57:12.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:57:12.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:57:12.47#ibcon#enter wrdev, iclass 38, count 2 2006.285.21:57:12.47#ibcon#first serial, iclass 38, count 2 2006.285.21:57:12.47#ibcon#enter sib2, iclass 38, count 2 2006.285.21:57:12.47#ibcon#flushed, iclass 38, count 2 2006.285.21:57:12.47#ibcon#about to write, iclass 38, count 2 2006.285.21:57:12.47#ibcon#wrote, iclass 38, count 2 2006.285.21:57:12.47#ibcon#about to read 3, iclass 38, count 2 2006.285.21:57:12.49#ibcon#read 3, iclass 38, count 2 2006.285.21:57:12.49#ibcon#about to read 4, iclass 38, count 2 2006.285.21:57:12.49#ibcon#read 4, iclass 38, count 2 2006.285.21:57:12.49#ibcon#about to read 5, iclass 38, count 2 2006.285.21:57:12.49#ibcon#read 5, iclass 38, count 2 2006.285.21:57:12.49#ibcon#about to read 6, iclass 38, count 2 2006.285.21:57:12.49#ibcon#read 6, iclass 38, count 2 2006.285.21:57:12.49#ibcon#end of sib2, iclass 38, count 2 2006.285.21:57:12.49#ibcon#*mode == 0, iclass 38, count 2 2006.285.21:57:12.49#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.21:57:12.49#ibcon#[27=AT05-04\r\n] 2006.285.21:57:12.49#ibcon#*before write, iclass 38, count 2 2006.285.21:57:12.49#ibcon#enter sib2, iclass 38, count 2 2006.285.21:57:12.49#ibcon#flushed, iclass 38, count 2 2006.285.21:57:12.49#ibcon#about to write, iclass 38, count 2 2006.285.21:57:12.49#ibcon#wrote, iclass 38, count 2 2006.285.21:57:12.49#ibcon#about to read 3, iclass 38, count 2 2006.285.21:57:12.52#ibcon#read 3, iclass 38, count 2 2006.285.21:57:12.52#ibcon#about to read 4, iclass 38, count 2 2006.285.21:57:12.52#ibcon#read 4, iclass 38, count 2 2006.285.21:57:12.52#ibcon#about to read 5, iclass 38, count 2 2006.285.21:57:12.52#ibcon#read 5, iclass 38, count 2 2006.285.21:57:12.52#ibcon#about to read 6, iclass 38, count 2 2006.285.21:57:12.52#ibcon#read 6, iclass 38, count 2 2006.285.21:57:12.52#ibcon#end of sib2, iclass 38, count 2 2006.285.21:57:12.52#ibcon#*after write, iclass 38, count 2 2006.285.21:57:12.52#ibcon#*before return 0, iclass 38, count 2 2006.285.21:57:12.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:57:12.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.21:57:12.52#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.21:57:12.52#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:12.52#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:57:12.64#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:57:12.64#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:57:12.64#ibcon#enter wrdev, iclass 38, count 0 2006.285.21:57:12.64#ibcon#first serial, iclass 38, count 0 2006.285.21:57:12.64#ibcon#enter sib2, iclass 38, count 0 2006.285.21:57:12.64#ibcon#flushed, iclass 38, count 0 2006.285.21:57:12.64#ibcon#about to write, iclass 38, count 0 2006.285.21:57:12.64#ibcon#wrote, iclass 38, count 0 2006.285.21:57:12.64#ibcon#about to read 3, iclass 38, count 0 2006.285.21:57:12.66#ibcon#read 3, iclass 38, count 0 2006.285.21:57:12.66#ibcon#about to read 4, iclass 38, count 0 2006.285.21:57:12.66#ibcon#read 4, iclass 38, count 0 2006.285.21:57:12.66#ibcon#about to read 5, iclass 38, count 0 2006.285.21:57:12.66#ibcon#read 5, iclass 38, count 0 2006.285.21:57:12.66#ibcon#about to read 6, iclass 38, count 0 2006.285.21:57:12.66#ibcon#read 6, iclass 38, count 0 2006.285.21:57:12.66#ibcon#end of sib2, iclass 38, count 0 2006.285.21:57:12.66#ibcon#*mode == 0, iclass 38, count 0 2006.285.21:57:12.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.21:57:12.66#ibcon#[27=USB\r\n] 2006.285.21:57:12.66#ibcon#*before write, iclass 38, count 0 2006.285.21:57:12.66#ibcon#enter sib2, iclass 38, count 0 2006.285.21:57:12.66#ibcon#flushed, iclass 38, count 0 2006.285.21:57:12.66#ibcon#about to write, iclass 38, count 0 2006.285.21:57:12.66#ibcon#wrote, iclass 38, count 0 2006.285.21:57:12.66#ibcon#about to read 3, iclass 38, count 0 2006.285.21:57:12.69#ibcon#read 3, iclass 38, count 0 2006.285.21:57:12.69#ibcon#about to read 4, iclass 38, count 0 2006.285.21:57:12.69#ibcon#read 4, iclass 38, count 0 2006.285.21:57:12.69#ibcon#about to read 5, iclass 38, count 0 2006.285.21:57:12.69#ibcon#read 5, iclass 38, count 0 2006.285.21:57:12.69#ibcon#about to read 6, iclass 38, count 0 2006.285.21:57:12.69#ibcon#read 6, iclass 38, count 0 2006.285.21:57:12.69#ibcon#end of sib2, iclass 38, count 0 2006.285.21:57:12.69#ibcon#*after write, iclass 38, count 0 2006.285.21:57:12.69#ibcon#*before return 0, iclass 38, count 0 2006.285.21:57:12.69#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:57:12.69#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.21:57:12.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.21:57:12.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.21:57:12.69$vck44/vblo=6,719.99 2006.285.21:57:12.69#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.21:57:12.69#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.21:57:12.69#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:12.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:57:12.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:57:12.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:57:12.69#ibcon#enter wrdev, iclass 40, count 0 2006.285.21:57:12.69#ibcon#first serial, iclass 40, count 0 2006.285.21:57:12.69#ibcon#enter sib2, iclass 40, count 0 2006.285.21:57:12.69#ibcon#flushed, iclass 40, count 0 2006.285.21:57:12.69#ibcon#about to write, iclass 40, count 0 2006.285.21:57:12.69#ibcon#wrote, iclass 40, count 0 2006.285.21:57:12.69#ibcon#about to read 3, iclass 40, count 0 2006.285.21:57:12.71#ibcon#read 3, iclass 40, count 0 2006.285.21:57:12.71#ibcon#about to read 4, iclass 40, count 0 2006.285.21:57:12.71#ibcon#read 4, iclass 40, count 0 2006.285.21:57:12.71#ibcon#about to read 5, iclass 40, count 0 2006.285.21:57:12.71#ibcon#read 5, iclass 40, count 0 2006.285.21:57:12.71#ibcon#about to read 6, iclass 40, count 0 2006.285.21:57:12.71#ibcon#read 6, iclass 40, count 0 2006.285.21:57:12.71#ibcon#end of sib2, iclass 40, count 0 2006.285.21:57:12.71#ibcon#*mode == 0, iclass 40, count 0 2006.285.21:57:12.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.21:57:12.71#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.21:57:12.71#ibcon#*before write, iclass 40, count 0 2006.285.21:57:12.71#ibcon#enter sib2, iclass 40, count 0 2006.285.21:57:12.71#ibcon#flushed, iclass 40, count 0 2006.285.21:57:12.71#ibcon#about to write, iclass 40, count 0 2006.285.21:57:12.71#ibcon#wrote, iclass 40, count 0 2006.285.21:57:12.71#ibcon#about to read 3, iclass 40, count 0 2006.285.21:57:12.75#ibcon#read 3, iclass 40, count 0 2006.285.21:57:12.75#ibcon#about to read 4, iclass 40, count 0 2006.285.21:57:12.75#ibcon#read 4, iclass 40, count 0 2006.285.21:57:12.75#ibcon#about to read 5, iclass 40, count 0 2006.285.21:57:12.75#ibcon#read 5, iclass 40, count 0 2006.285.21:57:12.75#ibcon#about to read 6, iclass 40, count 0 2006.285.21:57:12.75#ibcon#read 6, iclass 40, count 0 2006.285.21:57:12.75#ibcon#end of sib2, iclass 40, count 0 2006.285.21:57:12.75#ibcon#*after write, iclass 40, count 0 2006.285.21:57:12.75#ibcon#*before return 0, iclass 40, count 0 2006.285.21:57:12.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:57:12.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.21:57:12.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.21:57:12.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.21:57:12.75$vck44/vb=6,3 2006.285.21:57:12.75#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.21:57:12.75#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.21:57:12.75#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:12.75#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:57:12.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:57:12.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:57:12.81#ibcon#enter wrdev, iclass 4, count 2 2006.285.21:57:12.81#ibcon#first serial, iclass 4, count 2 2006.285.21:57:12.81#ibcon#enter sib2, iclass 4, count 2 2006.285.21:57:12.81#ibcon#flushed, iclass 4, count 2 2006.285.21:57:12.81#ibcon#about to write, iclass 4, count 2 2006.285.21:57:12.81#ibcon#wrote, iclass 4, count 2 2006.285.21:57:12.81#ibcon#about to read 3, iclass 4, count 2 2006.285.21:57:12.83#ibcon#read 3, iclass 4, count 2 2006.285.21:57:12.83#ibcon#about to read 4, iclass 4, count 2 2006.285.21:57:12.83#ibcon#read 4, iclass 4, count 2 2006.285.21:57:12.83#ibcon#about to read 5, iclass 4, count 2 2006.285.21:57:12.83#ibcon#read 5, iclass 4, count 2 2006.285.21:57:12.83#ibcon#about to read 6, iclass 4, count 2 2006.285.21:57:12.83#ibcon#read 6, iclass 4, count 2 2006.285.21:57:12.83#ibcon#end of sib2, iclass 4, count 2 2006.285.21:57:12.83#ibcon#*mode == 0, iclass 4, count 2 2006.285.21:57:12.83#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.21:57:12.83#ibcon#[27=AT06-03\r\n] 2006.285.21:57:12.83#ibcon#*before write, iclass 4, count 2 2006.285.21:57:12.83#ibcon#enter sib2, iclass 4, count 2 2006.285.21:57:12.83#ibcon#flushed, iclass 4, count 2 2006.285.21:57:12.83#ibcon#about to write, iclass 4, count 2 2006.285.21:57:12.83#ibcon#wrote, iclass 4, count 2 2006.285.21:57:12.83#ibcon#about to read 3, iclass 4, count 2 2006.285.21:57:12.86#ibcon#read 3, iclass 4, count 2 2006.285.21:57:12.86#ibcon#about to read 4, iclass 4, count 2 2006.285.21:57:12.86#ibcon#read 4, iclass 4, count 2 2006.285.21:57:12.86#ibcon#about to read 5, iclass 4, count 2 2006.285.21:57:12.86#ibcon#read 5, iclass 4, count 2 2006.285.21:57:12.86#ibcon#about to read 6, iclass 4, count 2 2006.285.21:57:12.86#ibcon#read 6, iclass 4, count 2 2006.285.21:57:12.86#ibcon#end of sib2, iclass 4, count 2 2006.285.21:57:12.86#ibcon#*after write, iclass 4, count 2 2006.285.21:57:12.86#ibcon#*before return 0, iclass 4, count 2 2006.285.21:57:12.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:57:12.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.21:57:12.86#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.21:57:12.86#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:12.86#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:57:12.98#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:57:12.98#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:57:12.98#ibcon#enter wrdev, iclass 4, count 0 2006.285.21:57:12.98#ibcon#first serial, iclass 4, count 0 2006.285.21:57:12.98#ibcon#enter sib2, iclass 4, count 0 2006.285.21:57:12.98#ibcon#flushed, iclass 4, count 0 2006.285.21:57:12.98#ibcon#about to write, iclass 4, count 0 2006.285.21:57:12.98#ibcon#wrote, iclass 4, count 0 2006.285.21:57:12.98#ibcon#about to read 3, iclass 4, count 0 2006.285.21:57:13.00#ibcon#read 3, iclass 4, count 0 2006.285.21:57:13.00#ibcon#about to read 4, iclass 4, count 0 2006.285.21:57:13.00#ibcon#read 4, iclass 4, count 0 2006.285.21:57:13.00#ibcon#about to read 5, iclass 4, count 0 2006.285.21:57:13.00#ibcon#read 5, iclass 4, count 0 2006.285.21:57:13.00#ibcon#about to read 6, iclass 4, count 0 2006.285.21:57:13.00#ibcon#read 6, iclass 4, count 0 2006.285.21:57:13.00#ibcon#end of sib2, iclass 4, count 0 2006.285.21:57:13.00#ibcon#*mode == 0, iclass 4, count 0 2006.285.21:57:13.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.21:57:13.00#ibcon#[27=USB\r\n] 2006.285.21:57:13.00#ibcon#*before write, iclass 4, count 0 2006.285.21:57:13.00#ibcon#enter sib2, iclass 4, count 0 2006.285.21:57:13.00#ibcon#flushed, iclass 4, count 0 2006.285.21:57:13.00#ibcon#about to write, iclass 4, count 0 2006.285.21:57:13.00#ibcon#wrote, iclass 4, count 0 2006.285.21:57:13.00#ibcon#about to read 3, iclass 4, count 0 2006.285.21:57:13.03#ibcon#read 3, iclass 4, count 0 2006.285.21:57:13.03#ibcon#about to read 4, iclass 4, count 0 2006.285.21:57:13.03#ibcon#read 4, iclass 4, count 0 2006.285.21:57:13.03#ibcon#about to read 5, iclass 4, count 0 2006.285.21:57:13.03#ibcon#read 5, iclass 4, count 0 2006.285.21:57:13.03#ibcon#about to read 6, iclass 4, count 0 2006.285.21:57:13.03#ibcon#read 6, iclass 4, count 0 2006.285.21:57:13.03#ibcon#end of sib2, iclass 4, count 0 2006.285.21:57:13.03#ibcon#*after write, iclass 4, count 0 2006.285.21:57:13.03#ibcon#*before return 0, iclass 4, count 0 2006.285.21:57:13.03#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:57:13.03#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.21:57:13.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.21:57:13.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.21:57:13.03$vck44/vblo=7,734.99 2006.285.21:57:13.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.21:57:13.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.21:57:13.03#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:13.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:57:13.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:57:13.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:57:13.03#ibcon#enter wrdev, iclass 6, count 0 2006.285.21:57:13.03#ibcon#first serial, iclass 6, count 0 2006.285.21:57:13.03#ibcon#enter sib2, iclass 6, count 0 2006.285.21:57:13.03#ibcon#flushed, iclass 6, count 0 2006.285.21:57:13.03#ibcon#about to write, iclass 6, count 0 2006.285.21:57:13.03#ibcon#wrote, iclass 6, count 0 2006.285.21:57:13.03#ibcon#about to read 3, iclass 6, count 0 2006.285.21:57:13.05#ibcon#read 3, iclass 6, count 0 2006.285.21:57:13.05#ibcon#about to read 4, iclass 6, count 0 2006.285.21:57:13.05#ibcon#read 4, iclass 6, count 0 2006.285.21:57:13.05#ibcon#about to read 5, iclass 6, count 0 2006.285.21:57:13.05#ibcon#read 5, iclass 6, count 0 2006.285.21:57:13.05#ibcon#about to read 6, iclass 6, count 0 2006.285.21:57:13.05#ibcon#read 6, iclass 6, count 0 2006.285.21:57:13.05#ibcon#end of sib2, iclass 6, count 0 2006.285.21:57:13.05#ibcon#*mode == 0, iclass 6, count 0 2006.285.21:57:13.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.21:57:13.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.21:57:13.05#ibcon#*before write, iclass 6, count 0 2006.285.21:57:13.05#ibcon#enter sib2, iclass 6, count 0 2006.285.21:57:13.05#ibcon#flushed, iclass 6, count 0 2006.285.21:57:13.05#ibcon#about to write, iclass 6, count 0 2006.285.21:57:13.05#ibcon#wrote, iclass 6, count 0 2006.285.21:57:13.05#ibcon#about to read 3, iclass 6, count 0 2006.285.21:57:13.09#ibcon#read 3, iclass 6, count 0 2006.285.21:57:13.09#ibcon#about to read 4, iclass 6, count 0 2006.285.21:57:13.09#ibcon#read 4, iclass 6, count 0 2006.285.21:57:13.09#ibcon#about to read 5, iclass 6, count 0 2006.285.21:57:13.09#ibcon#read 5, iclass 6, count 0 2006.285.21:57:13.09#ibcon#about to read 6, iclass 6, count 0 2006.285.21:57:13.09#ibcon#read 6, iclass 6, count 0 2006.285.21:57:13.09#ibcon#end of sib2, iclass 6, count 0 2006.285.21:57:13.09#ibcon#*after write, iclass 6, count 0 2006.285.21:57:13.09#ibcon#*before return 0, iclass 6, count 0 2006.285.21:57:13.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:57:13.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.21:57:13.09#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.21:57:13.09#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.21:57:13.09$vck44/vb=7,4 2006.285.21:57:13.09#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.21:57:13.09#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.21:57:13.09#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:13.09#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:57:13.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:57:13.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:57:13.15#ibcon#enter wrdev, iclass 10, count 2 2006.285.21:57:13.15#ibcon#first serial, iclass 10, count 2 2006.285.21:57:13.15#ibcon#enter sib2, iclass 10, count 2 2006.285.21:57:13.15#ibcon#flushed, iclass 10, count 2 2006.285.21:57:13.15#ibcon#about to write, iclass 10, count 2 2006.285.21:57:13.15#ibcon#wrote, iclass 10, count 2 2006.285.21:57:13.15#ibcon#about to read 3, iclass 10, count 2 2006.285.21:57:13.17#ibcon#read 3, iclass 10, count 2 2006.285.21:57:13.17#ibcon#about to read 4, iclass 10, count 2 2006.285.21:57:13.17#ibcon#read 4, iclass 10, count 2 2006.285.21:57:13.17#ibcon#about to read 5, iclass 10, count 2 2006.285.21:57:13.17#ibcon#read 5, iclass 10, count 2 2006.285.21:57:13.17#ibcon#about to read 6, iclass 10, count 2 2006.285.21:57:13.17#ibcon#read 6, iclass 10, count 2 2006.285.21:57:13.17#ibcon#end of sib2, iclass 10, count 2 2006.285.21:57:13.17#ibcon#*mode == 0, iclass 10, count 2 2006.285.21:57:13.17#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.21:57:13.17#ibcon#[27=AT07-04\r\n] 2006.285.21:57:13.17#ibcon#*before write, iclass 10, count 2 2006.285.21:57:13.17#ibcon#enter sib2, iclass 10, count 2 2006.285.21:57:13.17#ibcon#flushed, iclass 10, count 2 2006.285.21:57:13.17#ibcon#about to write, iclass 10, count 2 2006.285.21:57:13.17#ibcon#wrote, iclass 10, count 2 2006.285.21:57:13.17#ibcon#about to read 3, iclass 10, count 2 2006.285.21:57:13.20#ibcon#read 3, iclass 10, count 2 2006.285.21:57:13.20#ibcon#about to read 4, iclass 10, count 2 2006.285.21:57:13.20#ibcon#read 4, iclass 10, count 2 2006.285.21:57:13.20#ibcon#about to read 5, iclass 10, count 2 2006.285.21:57:13.20#ibcon#read 5, iclass 10, count 2 2006.285.21:57:13.20#ibcon#about to read 6, iclass 10, count 2 2006.285.21:57:13.20#ibcon#read 6, iclass 10, count 2 2006.285.21:57:13.20#ibcon#end of sib2, iclass 10, count 2 2006.285.21:57:13.20#ibcon#*after write, iclass 10, count 2 2006.285.21:57:13.20#ibcon#*before return 0, iclass 10, count 2 2006.285.21:57:13.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:57:13.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.21:57:13.20#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.21:57:13.20#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:13.20#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:57:13.32#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:57:13.32#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:57:13.32#ibcon#enter wrdev, iclass 10, count 0 2006.285.21:57:13.32#ibcon#first serial, iclass 10, count 0 2006.285.21:57:13.32#ibcon#enter sib2, iclass 10, count 0 2006.285.21:57:13.32#ibcon#flushed, iclass 10, count 0 2006.285.21:57:13.32#ibcon#about to write, iclass 10, count 0 2006.285.21:57:13.32#ibcon#wrote, iclass 10, count 0 2006.285.21:57:13.32#ibcon#about to read 3, iclass 10, count 0 2006.285.21:57:13.34#ibcon#read 3, iclass 10, count 0 2006.285.21:57:13.34#ibcon#about to read 4, iclass 10, count 0 2006.285.21:57:13.34#ibcon#read 4, iclass 10, count 0 2006.285.21:57:13.34#ibcon#about to read 5, iclass 10, count 0 2006.285.21:57:13.34#ibcon#read 5, iclass 10, count 0 2006.285.21:57:13.34#ibcon#about to read 6, iclass 10, count 0 2006.285.21:57:13.34#ibcon#read 6, iclass 10, count 0 2006.285.21:57:13.34#ibcon#end of sib2, iclass 10, count 0 2006.285.21:57:13.34#ibcon#*mode == 0, iclass 10, count 0 2006.285.21:57:13.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.21:57:13.34#ibcon#[27=USB\r\n] 2006.285.21:57:13.34#ibcon#*before write, iclass 10, count 0 2006.285.21:57:13.34#ibcon#enter sib2, iclass 10, count 0 2006.285.21:57:13.34#ibcon#flushed, iclass 10, count 0 2006.285.21:57:13.34#ibcon#about to write, iclass 10, count 0 2006.285.21:57:13.34#ibcon#wrote, iclass 10, count 0 2006.285.21:57:13.34#ibcon#about to read 3, iclass 10, count 0 2006.285.21:57:13.37#ibcon#read 3, iclass 10, count 0 2006.285.21:57:13.37#ibcon#about to read 4, iclass 10, count 0 2006.285.21:57:13.37#ibcon#read 4, iclass 10, count 0 2006.285.21:57:13.37#ibcon#about to read 5, iclass 10, count 0 2006.285.21:57:13.37#ibcon#read 5, iclass 10, count 0 2006.285.21:57:13.37#ibcon#about to read 6, iclass 10, count 0 2006.285.21:57:13.37#ibcon#read 6, iclass 10, count 0 2006.285.21:57:13.37#ibcon#end of sib2, iclass 10, count 0 2006.285.21:57:13.37#ibcon#*after write, iclass 10, count 0 2006.285.21:57:13.37#ibcon#*before return 0, iclass 10, count 0 2006.285.21:57:13.37#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:57:13.37#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.21:57:13.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.21:57:13.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.21:57:13.37$vck44/vblo=8,744.99 2006.285.21:57:13.37#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.21:57:13.37#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.21:57:13.37#ibcon#ireg 17 cls_cnt 0 2006.285.21:57:13.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:57:13.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:57:13.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:57:13.37#ibcon#enter wrdev, iclass 12, count 0 2006.285.21:57:13.37#ibcon#first serial, iclass 12, count 0 2006.285.21:57:13.37#ibcon#enter sib2, iclass 12, count 0 2006.285.21:57:13.37#ibcon#flushed, iclass 12, count 0 2006.285.21:57:13.37#ibcon#about to write, iclass 12, count 0 2006.285.21:57:13.37#ibcon#wrote, iclass 12, count 0 2006.285.21:57:13.37#ibcon#about to read 3, iclass 12, count 0 2006.285.21:57:13.39#ibcon#read 3, iclass 12, count 0 2006.285.21:57:13.39#ibcon#about to read 4, iclass 12, count 0 2006.285.21:57:13.39#ibcon#read 4, iclass 12, count 0 2006.285.21:57:13.39#ibcon#about to read 5, iclass 12, count 0 2006.285.21:57:13.39#ibcon#read 5, iclass 12, count 0 2006.285.21:57:13.39#ibcon#about to read 6, iclass 12, count 0 2006.285.21:57:13.39#ibcon#read 6, iclass 12, count 0 2006.285.21:57:13.39#ibcon#end of sib2, iclass 12, count 0 2006.285.21:57:13.39#ibcon#*mode == 0, iclass 12, count 0 2006.285.21:57:13.39#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.21:57:13.39#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.21:57:13.39#ibcon#*before write, iclass 12, count 0 2006.285.21:57:13.39#ibcon#enter sib2, iclass 12, count 0 2006.285.21:57:13.39#ibcon#flushed, iclass 12, count 0 2006.285.21:57:13.39#ibcon#about to write, iclass 12, count 0 2006.285.21:57:13.39#ibcon#wrote, iclass 12, count 0 2006.285.21:57:13.39#ibcon#about to read 3, iclass 12, count 0 2006.285.21:57:13.43#ibcon#read 3, iclass 12, count 0 2006.285.21:57:13.43#ibcon#about to read 4, iclass 12, count 0 2006.285.21:57:13.43#ibcon#read 4, iclass 12, count 0 2006.285.21:57:13.43#ibcon#about to read 5, iclass 12, count 0 2006.285.21:57:13.43#ibcon#read 5, iclass 12, count 0 2006.285.21:57:13.43#ibcon#about to read 6, iclass 12, count 0 2006.285.21:57:13.43#ibcon#read 6, iclass 12, count 0 2006.285.21:57:13.43#ibcon#end of sib2, iclass 12, count 0 2006.285.21:57:13.43#ibcon#*after write, iclass 12, count 0 2006.285.21:57:13.43#ibcon#*before return 0, iclass 12, count 0 2006.285.21:57:13.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:57:13.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.21:57:13.43#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.21:57:13.43#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.21:57:13.43$vck44/vb=8,4 2006.285.21:57:13.43#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.21:57:13.43#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.21:57:13.43#ibcon#ireg 11 cls_cnt 2 2006.285.21:57:13.43#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:57:13.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:57:13.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:57:13.49#ibcon#enter wrdev, iclass 14, count 2 2006.285.21:57:13.49#ibcon#first serial, iclass 14, count 2 2006.285.21:57:13.49#ibcon#enter sib2, iclass 14, count 2 2006.285.21:57:13.49#ibcon#flushed, iclass 14, count 2 2006.285.21:57:13.49#ibcon#about to write, iclass 14, count 2 2006.285.21:57:13.49#ibcon#wrote, iclass 14, count 2 2006.285.21:57:13.49#ibcon#about to read 3, iclass 14, count 2 2006.285.21:57:13.51#ibcon#read 3, iclass 14, count 2 2006.285.21:57:13.51#ibcon#about to read 4, iclass 14, count 2 2006.285.21:57:13.51#ibcon#read 4, iclass 14, count 2 2006.285.21:57:13.51#ibcon#about to read 5, iclass 14, count 2 2006.285.21:57:13.51#ibcon#read 5, iclass 14, count 2 2006.285.21:57:13.51#ibcon#about to read 6, iclass 14, count 2 2006.285.21:57:13.51#ibcon#read 6, iclass 14, count 2 2006.285.21:57:13.51#ibcon#end of sib2, iclass 14, count 2 2006.285.21:57:13.51#ibcon#*mode == 0, iclass 14, count 2 2006.285.21:57:13.51#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.21:57:13.51#ibcon#[27=AT08-04\r\n] 2006.285.21:57:13.51#ibcon#*before write, iclass 14, count 2 2006.285.21:57:13.51#ibcon#enter sib2, iclass 14, count 2 2006.285.21:57:13.51#ibcon#flushed, iclass 14, count 2 2006.285.21:57:13.51#ibcon#about to write, iclass 14, count 2 2006.285.21:57:13.51#ibcon#wrote, iclass 14, count 2 2006.285.21:57:13.51#ibcon#about to read 3, iclass 14, count 2 2006.285.21:57:13.54#ibcon#read 3, iclass 14, count 2 2006.285.21:57:13.54#ibcon#about to read 4, iclass 14, count 2 2006.285.21:57:13.54#ibcon#read 4, iclass 14, count 2 2006.285.21:57:13.54#ibcon#about to read 5, iclass 14, count 2 2006.285.21:57:13.54#ibcon#read 5, iclass 14, count 2 2006.285.21:57:13.54#ibcon#about to read 6, iclass 14, count 2 2006.285.21:57:13.54#ibcon#read 6, iclass 14, count 2 2006.285.21:57:13.54#ibcon#end of sib2, iclass 14, count 2 2006.285.21:57:13.54#ibcon#*after write, iclass 14, count 2 2006.285.21:57:13.54#ibcon#*before return 0, iclass 14, count 2 2006.285.21:57:13.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:57:13.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.21:57:13.54#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.21:57:13.54#ibcon#ireg 7 cls_cnt 0 2006.285.21:57:13.54#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:57:13.66#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:57:13.66#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:57:13.66#ibcon#enter wrdev, iclass 14, count 0 2006.285.21:57:13.66#ibcon#first serial, iclass 14, count 0 2006.285.21:57:13.66#ibcon#enter sib2, iclass 14, count 0 2006.285.21:57:13.66#ibcon#flushed, iclass 14, count 0 2006.285.21:57:13.66#ibcon#about to write, iclass 14, count 0 2006.285.21:57:13.66#ibcon#wrote, iclass 14, count 0 2006.285.21:57:13.66#ibcon#about to read 3, iclass 14, count 0 2006.285.21:57:13.68#ibcon#read 3, iclass 14, count 0 2006.285.21:57:13.68#ibcon#about to read 4, iclass 14, count 0 2006.285.21:57:13.68#ibcon#read 4, iclass 14, count 0 2006.285.21:57:13.68#ibcon#about to read 5, iclass 14, count 0 2006.285.21:57:13.68#ibcon#read 5, iclass 14, count 0 2006.285.21:57:13.68#ibcon#about to read 6, iclass 14, count 0 2006.285.21:57:13.68#ibcon#read 6, iclass 14, count 0 2006.285.21:57:13.68#ibcon#end of sib2, iclass 14, count 0 2006.285.21:57:13.68#ibcon#*mode == 0, iclass 14, count 0 2006.285.21:57:13.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.21:57:13.68#ibcon#[27=USB\r\n] 2006.285.21:57:13.68#ibcon#*before write, iclass 14, count 0 2006.285.21:57:13.68#ibcon#enter sib2, iclass 14, count 0 2006.285.21:57:13.68#ibcon#flushed, iclass 14, count 0 2006.285.21:57:13.68#ibcon#about to write, iclass 14, count 0 2006.285.21:57:13.68#ibcon#wrote, iclass 14, count 0 2006.285.21:57:13.68#ibcon#about to read 3, iclass 14, count 0 2006.285.21:57:13.71#ibcon#read 3, iclass 14, count 0 2006.285.21:57:13.71#ibcon#about to read 4, iclass 14, count 0 2006.285.21:57:13.71#ibcon#read 4, iclass 14, count 0 2006.285.21:57:13.71#ibcon#about to read 5, iclass 14, count 0 2006.285.21:57:13.71#ibcon#read 5, iclass 14, count 0 2006.285.21:57:13.71#ibcon#about to read 6, iclass 14, count 0 2006.285.21:57:13.71#ibcon#read 6, iclass 14, count 0 2006.285.21:57:13.71#ibcon#end of sib2, iclass 14, count 0 2006.285.21:57:13.71#ibcon#*after write, iclass 14, count 0 2006.285.21:57:13.71#ibcon#*before return 0, iclass 14, count 0 2006.285.21:57:13.71#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:57:13.71#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.21:57:13.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.21:57:13.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.21:57:13.71$vck44/vabw=wide 2006.285.21:57:13.71#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.21:57:13.71#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.21:57:13.71#ibcon#ireg 8 cls_cnt 0 2006.285.21:57:13.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:57:13.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:57:13.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:57:13.71#ibcon#enter wrdev, iclass 16, count 0 2006.285.21:57:13.71#ibcon#first serial, iclass 16, count 0 2006.285.21:57:13.71#ibcon#enter sib2, iclass 16, count 0 2006.285.21:57:13.71#ibcon#flushed, iclass 16, count 0 2006.285.21:57:13.71#ibcon#about to write, iclass 16, count 0 2006.285.21:57:13.71#ibcon#wrote, iclass 16, count 0 2006.285.21:57:13.71#ibcon#about to read 3, iclass 16, count 0 2006.285.21:57:13.73#ibcon#read 3, iclass 16, count 0 2006.285.21:57:13.73#ibcon#about to read 4, iclass 16, count 0 2006.285.21:57:13.73#ibcon#read 4, iclass 16, count 0 2006.285.21:57:13.73#ibcon#about to read 5, iclass 16, count 0 2006.285.21:57:13.73#ibcon#read 5, iclass 16, count 0 2006.285.21:57:13.73#ibcon#about to read 6, iclass 16, count 0 2006.285.21:57:13.73#ibcon#read 6, iclass 16, count 0 2006.285.21:57:13.73#ibcon#end of sib2, iclass 16, count 0 2006.285.21:57:13.73#ibcon#*mode == 0, iclass 16, count 0 2006.285.21:57:13.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.21:57:13.73#ibcon#[25=BW32\r\n] 2006.285.21:57:13.73#ibcon#*before write, iclass 16, count 0 2006.285.21:57:13.73#ibcon#enter sib2, iclass 16, count 0 2006.285.21:57:13.73#ibcon#flushed, iclass 16, count 0 2006.285.21:57:13.73#ibcon#about to write, iclass 16, count 0 2006.285.21:57:13.73#ibcon#wrote, iclass 16, count 0 2006.285.21:57:13.73#ibcon#about to read 3, iclass 16, count 0 2006.285.21:57:13.76#ibcon#read 3, iclass 16, count 0 2006.285.21:57:13.76#ibcon#about to read 4, iclass 16, count 0 2006.285.21:57:13.76#ibcon#read 4, iclass 16, count 0 2006.285.21:57:13.76#ibcon#about to read 5, iclass 16, count 0 2006.285.21:57:13.76#ibcon#read 5, iclass 16, count 0 2006.285.21:57:13.76#ibcon#about to read 6, iclass 16, count 0 2006.285.21:57:13.76#ibcon#read 6, iclass 16, count 0 2006.285.21:57:13.76#ibcon#end of sib2, iclass 16, count 0 2006.285.21:57:13.76#ibcon#*after write, iclass 16, count 0 2006.285.21:57:13.76#ibcon#*before return 0, iclass 16, count 0 2006.285.21:57:13.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:57:13.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.21:57:13.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.21:57:13.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.21:57:13.76$vck44/vbbw=wide 2006.285.21:57:13.76#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.21:57:13.76#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.21:57:13.76#ibcon#ireg 8 cls_cnt 0 2006.285.21:57:13.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:57:13.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:57:13.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:57:13.83#ibcon#enter wrdev, iclass 18, count 0 2006.285.21:57:13.83#ibcon#first serial, iclass 18, count 0 2006.285.21:57:13.83#ibcon#enter sib2, iclass 18, count 0 2006.285.21:57:13.83#ibcon#flushed, iclass 18, count 0 2006.285.21:57:13.83#ibcon#about to write, iclass 18, count 0 2006.285.21:57:13.83#ibcon#wrote, iclass 18, count 0 2006.285.21:57:13.83#ibcon#about to read 3, iclass 18, count 0 2006.285.21:57:13.85#ibcon#read 3, iclass 18, count 0 2006.285.21:57:13.85#ibcon#about to read 4, iclass 18, count 0 2006.285.21:57:13.85#ibcon#read 4, iclass 18, count 0 2006.285.21:57:13.85#ibcon#about to read 5, iclass 18, count 0 2006.285.21:57:13.85#ibcon#read 5, iclass 18, count 0 2006.285.21:57:13.85#ibcon#about to read 6, iclass 18, count 0 2006.285.21:57:13.85#ibcon#read 6, iclass 18, count 0 2006.285.21:57:13.85#ibcon#end of sib2, iclass 18, count 0 2006.285.21:57:13.85#ibcon#*mode == 0, iclass 18, count 0 2006.285.21:57:13.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.21:57:13.85#ibcon#[27=BW32\r\n] 2006.285.21:57:13.85#ibcon#*before write, iclass 18, count 0 2006.285.21:57:13.85#ibcon#enter sib2, iclass 18, count 0 2006.285.21:57:13.85#ibcon#flushed, iclass 18, count 0 2006.285.21:57:13.85#ibcon#about to write, iclass 18, count 0 2006.285.21:57:13.85#ibcon#wrote, iclass 18, count 0 2006.285.21:57:13.85#ibcon#about to read 3, iclass 18, count 0 2006.285.21:57:13.88#ibcon#read 3, iclass 18, count 0 2006.285.21:57:13.88#ibcon#about to read 4, iclass 18, count 0 2006.285.21:57:13.88#ibcon#read 4, iclass 18, count 0 2006.285.21:57:13.88#ibcon#about to read 5, iclass 18, count 0 2006.285.21:57:13.88#ibcon#read 5, iclass 18, count 0 2006.285.21:57:13.88#ibcon#about to read 6, iclass 18, count 0 2006.285.21:57:13.88#ibcon#read 6, iclass 18, count 0 2006.285.21:57:13.88#ibcon#end of sib2, iclass 18, count 0 2006.285.21:57:13.88#ibcon#*after write, iclass 18, count 0 2006.285.21:57:13.88#ibcon#*before return 0, iclass 18, count 0 2006.285.21:57:13.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:57:13.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.21:57:13.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.21:57:13.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.21:57:13.88$setupk4/ifdk4 2006.285.21:57:13.88$ifdk4/lo= 2006.285.21:57:13.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.21:57:13.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.21:57:13.89$ifdk4/patch= 2006.285.21:57:14.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.21:57:14.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.21:57:14.05$setupk4/!*+20s 2006.285.21:57:18.14#trakl#Source acquired 2006.285.21:57:19.14#flagr#flagr/antenna,acquired 2006.285.21:57:21.24#abcon#<5=/15 0.7 1.2 15.581001016.0\r\n> 2006.285.21:57:21.26#abcon#{5=INTERFACE CLEAR} 2006.285.21:57:21.32#abcon#[5=S1D000X0/0*\r\n] 2006.285.21:57:27.34$setupk4/"tpicd 2006.285.21:57:27.34$setupk4/echo=off 2006.285.21:57:27.34$setupk4/xlog=off 2006.285.21:57:27.34:!2006.285.22:06:17 2006.285.22:06:17.00:preob 2006.285.22:06:17.14/onsource/TRACKING 2006.285.22:06:17.14:!2006.285.22:06:27 2006.285.22:06:27.00:"tape 2006.285.22:06:27.00:"st=record 2006.285.22:06:27.00:data_valid=on 2006.285.22:06:27.00:midob 2006.285.22:06:28.14/onsource/TRACKING 2006.285.22:06:28.14/wx/15.89,1016.1,100 2006.285.22:06:28.31/cable/+6.5115E-03 2006.285.22:06:29.40/va/01,07,usb,yes,33,35 2006.285.22:06:29.40/va/02,06,usb,yes,33,33 2006.285.22:06:29.40/va/03,07,usb,yes,32,34 2006.285.22:06:29.40/va/04,06,usb,yes,34,35 2006.285.22:06:29.40/va/05,03,usb,yes,33,34 2006.285.22:06:29.40/va/06,04,usb,yes,30,29 2006.285.22:06:29.40/va/07,04,usb,yes,30,31 2006.285.22:06:29.40/va/08,03,usb,yes,31,38 2006.285.22:06:29.63/valo/01,524.99,yes,locked 2006.285.22:06:29.63/valo/02,534.99,yes,locked 2006.285.22:06:29.63/valo/03,564.99,yes,locked 2006.285.22:06:29.63/valo/04,624.99,yes,locked 2006.285.22:06:29.63/valo/05,734.99,yes,locked 2006.285.22:06:29.63/valo/06,814.99,yes,locked 2006.285.22:06:29.63/valo/07,864.99,yes,locked 2006.285.22:06:29.63/valo/08,884.99,yes,locked 2006.285.22:06:30.72/vb/01,04,usb,yes,30,28 2006.285.22:06:30.72/vb/02,05,usb,yes,28,28 2006.285.22:06:30.72/vb/03,04,usb,yes,29,32 2006.285.22:06:30.72/vb/04,05,usb,yes,29,28 2006.285.22:06:30.72/vb/05,04,usb,yes,26,28 2006.285.22:06:30.72/vb/06,03,usb,yes,37,33 2006.285.22:06:30.72/vb/07,04,usb,yes,30,30 2006.285.22:06:30.72/vb/08,04,usb,yes,27,31 2006.285.22:06:30.95/vblo/01,629.99,yes,locked 2006.285.22:06:30.95/vblo/02,634.99,yes,locked 2006.285.22:06:30.95/vblo/03,649.99,yes,locked 2006.285.22:06:30.95/vblo/04,679.99,yes,locked 2006.285.22:06:30.95/vblo/05,709.99,yes,locked 2006.285.22:06:30.95/vblo/06,719.99,yes,locked 2006.285.22:06:30.95/vblo/07,734.99,yes,locked 2006.285.22:06:30.95/vblo/08,744.99,yes,locked 2006.285.22:06:31.10/vabw/8 2006.285.22:06:31.25/vbbw/8 2006.285.22:06:31.37/xfe/off,on,12.0 2006.285.22:06:31.75/ifatt/23,28,28,28 2006.285.22:06:32.07/fmout-gps/S +2.57E-07 2006.285.22:06:32.09:!2006.285.22:09:47 2006.285.22:09:47.01:data_valid=off 2006.285.22:09:47.01:"et 2006.285.22:09:47.01:!+3s 2006.285.22:09:50.02:"tape 2006.285.22:09:50.02:postob 2006.285.22:09:50.08/cable/+6.5098E-03 2006.285.22:09:50.08/wx/16.01,1016.1,100 2006.285.22:09:50.14/fmout-gps/S +2.54E-07 2006.285.22:09:50.14:scan_name=285-2211,jd0610,60 2006.285.22:09:50.14:source=3c345,164258.81,394837.0,2000.0,cw 2006.285.22:09:51.14#flagr#flagr/antenna,new-source 2006.285.22:09:51.14:checkk5 2006.285.22:09:51.67/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:09:52.08/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:09:52.56/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:09:52.97/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:09:53.53/chk_obsdata//k5ts1/T2852206??a.dat file size is correct (nominal:800MB, actual:796MB). 2006.285.22:09:54.01/chk_obsdata//k5ts2/T2852206??b.dat file size is correct (nominal:800MB, actual:796MB). 2006.285.22:09:54.85/chk_obsdata//k5ts3/T2852206??c.dat file size is correct (nominal:800MB, actual:796MB). 2006.285.22:09:55.28/chk_obsdata//k5ts4/T2852206??d.dat file size is correct (nominal:800MB, actual:796MB). 2006.285.22:09:56.20/k5log//k5ts1_log_newline 2006.285.22:09:56.93/k5log//k5ts2_log_newline 2006.285.22:09:57.70/k5log//k5ts3_log_newline 2006.285.22:09:58.43/k5log//k5ts4_log_newline 2006.285.22:09:58.45/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:09:58.45:setupk4=1 2006.285.22:09:58.46$setupk4/echo=on 2006.285.22:09:58.46$setupk4/pcalon 2006.285.22:09:58.46$pcalon/"no phase cal control is implemented here 2006.285.22:09:58.46$setupk4/"tpicd=stop 2006.285.22:09:58.46$setupk4/"rec=synch_on 2006.285.22:09:58.46$setupk4/"rec_mode=128 2006.285.22:09:58.46$setupk4/!* 2006.285.22:09:58.46$setupk4/recpk4 2006.285.22:09:58.46$recpk4/recpatch= 2006.285.22:09:58.46$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:09:58.46$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:09:58.46$setupk4/vck44 2006.285.22:09:58.46$vck44/valo=1,524.99 2006.285.22:09:58.46#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.22:09:58.46#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.22:09:58.46#ibcon#ireg 17 cls_cnt 0 2006.285.22:09:58.46#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:09:58.46#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:09:58.46#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:09:58.46#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:09:58.46#ibcon#first serial, iclass 35, count 0 2006.285.22:09:58.46#ibcon#enter sib2, iclass 35, count 0 2006.285.22:09:58.46#ibcon#flushed, iclass 35, count 0 2006.285.22:09:58.46#ibcon#about to write, iclass 35, count 0 2006.285.22:09:58.46#ibcon#wrote, iclass 35, count 0 2006.285.22:09:58.46#ibcon#about to read 3, iclass 35, count 0 2006.285.22:09:58.48#ibcon#read 3, iclass 35, count 0 2006.285.22:09:58.48#ibcon#about to read 4, iclass 35, count 0 2006.285.22:09:58.48#ibcon#read 4, iclass 35, count 0 2006.285.22:09:58.48#ibcon#about to read 5, iclass 35, count 0 2006.285.22:09:58.48#ibcon#read 5, iclass 35, count 0 2006.285.22:09:58.48#ibcon#about to read 6, iclass 35, count 0 2006.285.22:09:58.48#ibcon#read 6, iclass 35, count 0 2006.285.22:09:58.48#ibcon#end of sib2, iclass 35, count 0 2006.285.22:09:58.48#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:09:58.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:09:58.48#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:09:58.48#ibcon#*before write, iclass 35, count 0 2006.285.22:09:58.48#ibcon#enter sib2, iclass 35, count 0 2006.285.22:09:58.48#ibcon#flushed, iclass 35, count 0 2006.285.22:09:58.48#ibcon#about to write, iclass 35, count 0 2006.285.22:09:58.48#ibcon#wrote, iclass 35, count 0 2006.285.22:09:58.48#ibcon#about to read 3, iclass 35, count 0 2006.285.22:09:58.53#ibcon#read 3, iclass 35, count 0 2006.285.22:09:58.53#ibcon#about to read 4, iclass 35, count 0 2006.285.22:09:58.53#ibcon#read 4, iclass 35, count 0 2006.285.22:09:58.53#ibcon#about to read 5, iclass 35, count 0 2006.285.22:09:58.53#ibcon#read 5, iclass 35, count 0 2006.285.22:09:58.53#ibcon#about to read 6, iclass 35, count 0 2006.285.22:09:58.53#ibcon#read 6, iclass 35, count 0 2006.285.22:09:58.53#ibcon#end of sib2, iclass 35, count 0 2006.285.22:09:58.53#ibcon#*after write, iclass 35, count 0 2006.285.22:09:58.53#ibcon#*before return 0, iclass 35, count 0 2006.285.22:09:58.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:09:58.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:09:58.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:09:58.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:09:58.53$vck44/va=1,7 2006.285.22:09:58.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.22:09:58.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.22:09:58.53#ibcon#ireg 11 cls_cnt 2 2006.285.22:09:58.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:09:58.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:09:58.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:09:58.53#ibcon#enter wrdev, iclass 37, count 2 2006.285.22:09:58.53#ibcon#first serial, iclass 37, count 2 2006.285.22:09:58.53#ibcon#enter sib2, iclass 37, count 2 2006.285.22:09:58.53#ibcon#flushed, iclass 37, count 2 2006.285.22:09:58.53#ibcon#about to write, iclass 37, count 2 2006.285.22:09:58.53#ibcon#wrote, iclass 37, count 2 2006.285.22:09:58.53#ibcon#about to read 3, iclass 37, count 2 2006.285.22:09:58.55#ibcon#read 3, iclass 37, count 2 2006.285.22:09:58.55#ibcon#about to read 4, iclass 37, count 2 2006.285.22:09:58.55#ibcon#read 4, iclass 37, count 2 2006.285.22:09:58.55#ibcon#about to read 5, iclass 37, count 2 2006.285.22:09:58.55#ibcon#read 5, iclass 37, count 2 2006.285.22:09:58.55#ibcon#about to read 6, iclass 37, count 2 2006.285.22:09:58.55#ibcon#read 6, iclass 37, count 2 2006.285.22:09:58.55#ibcon#end of sib2, iclass 37, count 2 2006.285.22:09:58.55#ibcon#*mode == 0, iclass 37, count 2 2006.285.22:09:58.55#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.22:09:58.55#ibcon#[25=AT01-07\r\n] 2006.285.22:09:58.55#ibcon#*before write, iclass 37, count 2 2006.285.22:09:58.55#ibcon#enter sib2, iclass 37, count 2 2006.285.22:09:58.55#ibcon#flushed, iclass 37, count 2 2006.285.22:09:58.55#ibcon#about to write, iclass 37, count 2 2006.285.22:09:58.55#ibcon#wrote, iclass 37, count 2 2006.285.22:09:58.55#ibcon#about to read 3, iclass 37, count 2 2006.285.22:09:58.58#ibcon#read 3, iclass 37, count 2 2006.285.22:09:58.58#ibcon#about to read 4, iclass 37, count 2 2006.285.22:09:58.58#ibcon#read 4, iclass 37, count 2 2006.285.22:09:58.58#ibcon#about to read 5, iclass 37, count 2 2006.285.22:09:58.58#ibcon#read 5, iclass 37, count 2 2006.285.22:09:58.58#ibcon#about to read 6, iclass 37, count 2 2006.285.22:09:58.58#ibcon#read 6, iclass 37, count 2 2006.285.22:09:58.58#ibcon#end of sib2, iclass 37, count 2 2006.285.22:09:58.58#ibcon#*after write, iclass 37, count 2 2006.285.22:09:58.58#ibcon#*before return 0, iclass 37, count 2 2006.285.22:09:58.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:09:58.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:09:58.58#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.22:09:58.58#ibcon#ireg 7 cls_cnt 0 2006.285.22:09:58.58#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:09:58.70#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:09:58.70#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:09:58.70#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:09:58.70#ibcon#first serial, iclass 37, count 0 2006.285.22:09:58.70#ibcon#enter sib2, iclass 37, count 0 2006.285.22:09:58.70#ibcon#flushed, iclass 37, count 0 2006.285.22:09:58.70#ibcon#about to write, iclass 37, count 0 2006.285.22:09:58.70#ibcon#wrote, iclass 37, count 0 2006.285.22:09:58.70#ibcon#about to read 3, iclass 37, count 0 2006.285.22:09:58.72#ibcon#read 3, iclass 37, count 0 2006.285.22:09:58.72#ibcon#about to read 4, iclass 37, count 0 2006.285.22:09:58.72#ibcon#read 4, iclass 37, count 0 2006.285.22:09:58.72#ibcon#about to read 5, iclass 37, count 0 2006.285.22:09:58.72#ibcon#read 5, iclass 37, count 0 2006.285.22:09:58.72#ibcon#about to read 6, iclass 37, count 0 2006.285.22:09:58.72#ibcon#read 6, iclass 37, count 0 2006.285.22:09:58.72#ibcon#end of sib2, iclass 37, count 0 2006.285.22:09:58.72#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:09:58.72#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:09:58.72#ibcon#[25=USB\r\n] 2006.285.22:09:58.72#ibcon#*before write, iclass 37, count 0 2006.285.22:09:58.72#ibcon#enter sib2, iclass 37, count 0 2006.285.22:09:58.72#ibcon#flushed, iclass 37, count 0 2006.285.22:09:58.72#ibcon#about to write, iclass 37, count 0 2006.285.22:09:58.72#ibcon#wrote, iclass 37, count 0 2006.285.22:09:58.72#ibcon#about to read 3, iclass 37, count 0 2006.285.22:09:58.75#ibcon#read 3, iclass 37, count 0 2006.285.22:09:58.75#ibcon#about to read 4, iclass 37, count 0 2006.285.22:09:58.75#ibcon#read 4, iclass 37, count 0 2006.285.22:09:58.75#ibcon#about to read 5, iclass 37, count 0 2006.285.22:09:58.75#ibcon#read 5, iclass 37, count 0 2006.285.22:09:58.75#ibcon#about to read 6, iclass 37, count 0 2006.285.22:09:58.75#ibcon#read 6, iclass 37, count 0 2006.285.22:09:58.75#ibcon#end of sib2, iclass 37, count 0 2006.285.22:09:58.75#ibcon#*after write, iclass 37, count 0 2006.285.22:09:58.75#ibcon#*before return 0, iclass 37, count 0 2006.285.22:09:58.75#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:09:58.75#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:09:58.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:09:58.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:09:58.75$vck44/valo=2,534.99 2006.285.22:09:58.75#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.22:09:58.75#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.22:09:58.75#ibcon#ireg 17 cls_cnt 0 2006.285.22:09:58.75#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:09:58.75#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:09:58.75#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:09:58.75#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:09:58.75#ibcon#first serial, iclass 39, count 0 2006.285.22:09:58.75#ibcon#enter sib2, iclass 39, count 0 2006.285.22:09:58.75#ibcon#flushed, iclass 39, count 0 2006.285.22:09:58.75#ibcon#about to write, iclass 39, count 0 2006.285.22:09:58.75#ibcon#wrote, iclass 39, count 0 2006.285.22:09:58.75#ibcon#about to read 3, iclass 39, count 0 2006.285.22:09:58.77#ibcon#read 3, iclass 39, count 0 2006.285.22:09:58.77#ibcon#about to read 4, iclass 39, count 0 2006.285.22:09:58.77#ibcon#read 4, iclass 39, count 0 2006.285.22:09:58.77#ibcon#about to read 5, iclass 39, count 0 2006.285.22:09:58.77#ibcon#read 5, iclass 39, count 0 2006.285.22:09:58.77#ibcon#about to read 6, iclass 39, count 0 2006.285.22:09:58.77#ibcon#read 6, iclass 39, count 0 2006.285.22:09:58.77#ibcon#end of sib2, iclass 39, count 0 2006.285.22:09:58.77#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:09:58.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:09:58.77#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:09:58.77#ibcon#*before write, iclass 39, count 0 2006.285.22:09:58.77#ibcon#enter sib2, iclass 39, count 0 2006.285.22:09:58.77#ibcon#flushed, iclass 39, count 0 2006.285.22:09:58.77#ibcon#about to write, iclass 39, count 0 2006.285.22:09:58.77#ibcon#wrote, iclass 39, count 0 2006.285.22:09:58.77#ibcon#about to read 3, iclass 39, count 0 2006.285.22:09:58.81#ibcon#read 3, iclass 39, count 0 2006.285.22:09:58.81#ibcon#about to read 4, iclass 39, count 0 2006.285.22:09:58.81#ibcon#read 4, iclass 39, count 0 2006.285.22:09:58.81#ibcon#about to read 5, iclass 39, count 0 2006.285.22:09:58.81#ibcon#read 5, iclass 39, count 0 2006.285.22:09:58.81#ibcon#about to read 6, iclass 39, count 0 2006.285.22:09:58.81#ibcon#read 6, iclass 39, count 0 2006.285.22:09:58.81#ibcon#end of sib2, iclass 39, count 0 2006.285.22:09:58.81#ibcon#*after write, iclass 39, count 0 2006.285.22:09:58.81#ibcon#*before return 0, iclass 39, count 0 2006.285.22:09:58.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:09:58.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:09:58.81#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:09:58.81#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:09:58.81$vck44/va=2,6 2006.285.22:09:58.81#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.22:09:58.81#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.22:09:58.81#ibcon#ireg 11 cls_cnt 2 2006.285.22:09:58.81#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:09:58.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:09:58.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:09:58.87#ibcon#enter wrdev, iclass 3, count 2 2006.285.22:09:58.87#ibcon#first serial, iclass 3, count 2 2006.285.22:09:58.87#ibcon#enter sib2, iclass 3, count 2 2006.285.22:09:58.87#ibcon#flushed, iclass 3, count 2 2006.285.22:09:58.87#ibcon#about to write, iclass 3, count 2 2006.285.22:09:58.87#ibcon#wrote, iclass 3, count 2 2006.285.22:09:58.87#ibcon#about to read 3, iclass 3, count 2 2006.285.22:09:58.89#ibcon#read 3, iclass 3, count 2 2006.285.22:09:58.89#ibcon#about to read 4, iclass 3, count 2 2006.285.22:09:58.89#ibcon#read 4, iclass 3, count 2 2006.285.22:09:58.89#ibcon#about to read 5, iclass 3, count 2 2006.285.22:09:58.89#ibcon#read 5, iclass 3, count 2 2006.285.22:09:58.89#ibcon#about to read 6, iclass 3, count 2 2006.285.22:09:58.89#ibcon#read 6, iclass 3, count 2 2006.285.22:09:58.89#ibcon#end of sib2, iclass 3, count 2 2006.285.22:09:58.89#ibcon#*mode == 0, iclass 3, count 2 2006.285.22:09:58.89#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.22:09:58.89#ibcon#[25=AT02-06\r\n] 2006.285.22:09:58.89#ibcon#*before write, iclass 3, count 2 2006.285.22:09:58.89#ibcon#enter sib2, iclass 3, count 2 2006.285.22:09:58.89#ibcon#flushed, iclass 3, count 2 2006.285.22:09:58.89#ibcon#about to write, iclass 3, count 2 2006.285.22:09:58.89#ibcon#wrote, iclass 3, count 2 2006.285.22:09:58.89#ibcon#about to read 3, iclass 3, count 2 2006.285.22:09:58.92#ibcon#read 3, iclass 3, count 2 2006.285.22:09:58.92#ibcon#about to read 4, iclass 3, count 2 2006.285.22:09:58.92#ibcon#read 4, iclass 3, count 2 2006.285.22:09:58.92#ibcon#about to read 5, iclass 3, count 2 2006.285.22:09:58.92#ibcon#read 5, iclass 3, count 2 2006.285.22:09:58.92#ibcon#about to read 6, iclass 3, count 2 2006.285.22:09:58.92#ibcon#read 6, iclass 3, count 2 2006.285.22:09:58.92#ibcon#end of sib2, iclass 3, count 2 2006.285.22:09:58.92#ibcon#*after write, iclass 3, count 2 2006.285.22:09:58.92#ibcon#*before return 0, iclass 3, count 2 2006.285.22:09:58.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:09:58.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:09:58.92#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.22:09:58.92#ibcon#ireg 7 cls_cnt 0 2006.285.22:09:58.92#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:09:59.04#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:09:59.04#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:09:59.04#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:09:59.04#ibcon#first serial, iclass 3, count 0 2006.285.22:09:59.04#ibcon#enter sib2, iclass 3, count 0 2006.285.22:09:59.04#ibcon#flushed, iclass 3, count 0 2006.285.22:09:59.04#ibcon#about to write, iclass 3, count 0 2006.285.22:09:59.04#ibcon#wrote, iclass 3, count 0 2006.285.22:09:59.04#ibcon#about to read 3, iclass 3, count 0 2006.285.22:09:59.06#ibcon#read 3, iclass 3, count 0 2006.285.22:09:59.06#ibcon#about to read 4, iclass 3, count 0 2006.285.22:09:59.06#ibcon#read 4, iclass 3, count 0 2006.285.22:09:59.06#ibcon#about to read 5, iclass 3, count 0 2006.285.22:09:59.06#ibcon#read 5, iclass 3, count 0 2006.285.22:09:59.06#ibcon#about to read 6, iclass 3, count 0 2006.285.22:09:59.06#ibcon#read 6, iclass 3, count 0 2006.285.22:09:59.06#ibcon#end of sib2, iclass 3, count 0 2006.285.22:09:59.06#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:09:59.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:09:59.06#ibcon#[25=USB\r\n] 2006.285.22:09:59.06#ibcon#*before write, iclass 3, count 0 2006.285.22:09:59.06#ibcon#enter sib2, iclass 3, count 0 2006.285.22:09:59.06#ibcon#flushed, iclass 3, count 0 2006.285.22:09:59.06#ibcon#about to write, iclass 3, count 0 2006.285.22:09:59.06#ibcon#wrote, iclass 3, count 0 2006.285.22:09:59.06#ibcon#about to read 3, iclass 3, count 0 2006.285.22:09:59.09#ibcon#read 3, iclass 3, count 0 2006.285.22:09:59.09#ibcon#about to read 4, iclass 3, count 0 2006.285.22:09:59.09#ibcon#read 4, iclass 3, count 0 2006.285.22:09:59.09#ibcon#about to read 5, iclass 3, count 0 2006.285.22:09:59.09#ibcon#read 5, iclass 3, count 0 2006.285.22:09:59.09#ibcon#about to read 6, iclass 3, count 0 2006.285.22:09:59.09#ibcon#read 6, iclass 3, count 0 2006.285.22:09:59.09#ibcon#end of sib2, iclass 3, count 0 2006.285.22:09:59.09#ibcon#*after write, iclass 3, count 0 2006.285.22:09:59.09#ibcon#*before return 0, iclass 3, count 0 2006.285.22:09:59.09#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:09:59.09#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:09:59.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:09:59.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:09:59.09$vck44/valo=3,564.99 2006.285.22:09:59.09#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.22:09:59.09#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.22:09:59.09#ibcon#ireg 17 cls_cnt 0 2006.285.22:09:59.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:09:59.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:09:59.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:09:59.09#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:09:59.09#ibcon#first serial, iclass 5, count 0 2006.285.22:09:59.09#ibcon#enter sib2, iclass 5, count 0 2006.285.22:09:59.09#ibcon#flushed, iclass 5, count 0 2006.285.22:09:59.09#ibcon#about to write, iclass 5, count 0 2006.285.22:09:59.09#ibcon#wrote, iclass 5, count 0 2006.285.22:09:59.09#ibcon#about to read 3, iclass 5, count 0 2006.285.22:09:59.11#ibcon#read 3, iclass 5, count 0 2006.285.22:09:59.11#ibcon#about to read 4, iclass 5, count 0 2006.285.22:09:59.11#ibcon#read 4, iclass 5, count 0 2006.285.22:09:59.11#ibcon#about to read 5, iclass 5, count 0 2006.285.22:09:59.11#ibcon#read 5, iclass 5, count 0 2006.285.22:09:59.11#ibcon#about to read 6, iclass 5, count 0 2006.285.22:09:59.11#ibcon#read 6, iclass 5, count 0 2006.285.22:09:59.11#ibcon#end of sib2, iclass 5, count 0 2006.285.22:09:59.11#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:09:59.11#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:09:59.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:09:59.11#ibcon#*before write, iclass 5, count 0 2006.285.22:09:59.11#ibcon#enter sib2, iclass 5, count 0 2006.285.22:09:59.11#ibcon#flushed, iclass 5, count 0 2006.285.22:09:59.11#ibcon#about to write, iclass 5, count 0 2006.285.22:09:59.11#ibcon#wrote, iclass 5, count 0 2006.285.22:09:59.11#ibcon#about to read 3, iclass 5, count 0 2006.285.22:09:59.15#ibcon#read 3, iclass 5, count 0 2006.285.22:09:59.15#ibcon#about to read 4, iclass 5, count 0 2006.285.22:09:59.15#ibcon#read 4, iclass 5, count 0 2006.285.22:09:59.15#ibcon#about to read 5, iclass 5, count 0 2006.285.22:09:59.15#ibcon#read 5, iclass 5, count 0 2006.285.22:09:59.15#ibcon#about to read 6, iclass 5, count 0 2006.285.22:09:59.15#ibcon#read 6, iclass 5, count 0 2006.285.22:09:59.15#ibcon#end of sib2, iclass 5, count 0 2006.285.22:09:59.15#ibcon#*after write, iclass 5, count 0 2006.285.22:09:59.15#ibcon#*before return 0, iclass 5, count 0 2006.285.22:09:59.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:09:59.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:09:59.15#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:09:59.15#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:09:59.15$vck44/va=3,7 2006.285.22:09:59.15#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.22:09:59.15#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.22:09:59.15#ibcon#ireg 11 cls_cnt 2 2006.285.22:09:59.15#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:09:59.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:09:59.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:09:59.21#ibcon#enter wrdev, iclass 7, count 2 2006.285.22:09:59.21#ibcon#first serial, iclass 7, count 2 2006.285.22:09:59.21#ibcon#enter sib2, iclass 7, count 2 2006.285.22:09:59.21#ibcon#flushed, iclass 7, count 2 2006.285.22:09:59.21#ibcon#about to write, iclass 7, count 2 2006.285.22:09:59.21#ibcon#wrote, iclass 7, count 2 2006.285.22:09:59.21#ibcon#about to read 3, iclass 7, count 2 2006.285.22:09:59.23#ibcon#read 3, iclass 7, count 2 2006.285.22:09:59.23#ibcon#about to read 4, iclass 7, count 2 2006.285.22:09:59.23#ibcon#read 4, iclass 7, count 2 2006.285.22:09:59.23#ibcon#about to read 5, iclass 7, count 2 2006.285.22:09:59.23#ibcon#read 5, iclass 7, count 2 2006.285.22:09:59.23#ibcon#about to read 6, iclass 7, count 2 2006.285.22:09:59.23#ibcon#read 6, iclass 7, count 2 2006.285.22:09:59.23#ibcon#end of sib2, iclass 7, count 2 2006.285.22:09:59.23#ibcon#*mode == 0, iclass 7, count 2 2006.285.22:09:59.23#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.22:09:59.23#ibcon#[25=AT03-07\r\n] 2006.285.22:09:59.23#ibcon#*before write, iclass 7, count 2 2006.285.22:09:59.23#ibcon#enter sib2, iclass 7, count 2 2006.285.22:09:59.23#ibcon#flushed, iclass 7, count 2 2006.285.22:09:59.23#ibcon#about to write, iclass 7, count 2 2006.285.22:09:59.23#ibcon#wrote, iclass 7, count 2 2006.285.22:09:59.23#ibcon#about to read 3, iclass 7, count 2 2006.285.22:09:59.26#ibcon#read 3, iclass 7, count 2 2006.285.22:09:59.26#ibcon#about to read 4, iclass 7, count 2 2006.285.22:09:59.26#ibcon#read 4, iclass 7, count 2 2006.285.22:09:59.26#ibcon#about to read 5, iclass 7, count 2 2006.285.22:09:59.26#ibcon#read 5, iclass 7, count 2 2006.285.22:09:59.26#ibcon#about to read 6, iclass 7, count 2 2006.285.22:09:59.26#ibcon#read 6, iclass 7, count 2 2006.285.22:09:59.26#ibcon#end of sib2, iclass 7, count 2 2006.285.22:09:59.26#ibcon#*after write, iclass 7, count 2 2006.285.22:09:59.26#ibcon#*before return 0, iclass 7, count 2 2006.285.22:09:59.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:09:59.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:09:59.26#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.22:09:59.26#ibcon#ireg 7 cls_cnt 0 2006.285.22:09:59.26#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:09:59.38#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:09:59.38#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:09:59.38#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:09:59.38#ibcon#first serial, iclass 7, count 0 2006.285.22:09:59.38#ibcon#enter sib2, iclass 7, count 0 2006.285.22:09:59.38#ibcon#flushed, iclass 7, count 0 2006.285.22:09:59.38#ibcon#about to write, iclass 7, count 0 2006.285.22:09:59.38#ibcon#wrote, iclass 7, count 0 2006.285.22:09:59.38#ibcon#about to read 3, iclass 7, count 0 2006.285.22:09:59.40#ibcon#read 3, iclass 7, count 0 2006.285.22:09:59.40#ibcon#about to read 4, iclass 7, count 0 2006.285.22:09:59.40#ibcon#read 4, iclass 7, count 0 2006.285.22:09:59.40#ibcon#about to read 5, iclass 7, count 0 2006.285.22:09:59.40#ibcon#read 5, iclass 7, count 0 2006.285.22:09:59.40#ibcon#about to read 6, iclass 7, count 0 2006.285.22:09:59.40#ibcon#read 6, iclass 7, count 0 2006.285.22:09:59.40#ibcon#end of sib2, iclass 7, count 0 2006.285.22:09:59.40#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:09:59.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:09:59.40#ibcon#[25=USB\r\n] 2006.285.22:09:59.40#ibcon#*before write, iclass 7, count 0 2006.285.22:09:59.40#ibcon#enter sib2, iclass 7, count 0 2006.285.22:09:59.40#ibcon#flushed, iclass 7, count 0 2006.285.22:09:59.40#ibcon#about to write, iclass 7, count 0 2006.285.22:09:59.40#ibcon#wrote, iclass 7, count 0 2006.285.22:09:59.40#ibcon#about to read 3, iclass 7, count 0 2006.285.22:09:59.43#ibcon#read 3, iclass 7, count 0 2006.285.22:09:59.43#ibcon#about to read 4, iclass 7, count 0 2006.285.22:09:59.43#ibcon#read 4, iclass 7, count 0 2006.285.22:09:59.43#ibcon#about to read 5, iclass 7, count 0 2006.285.22:09:59.43#ibcon#read 5, iclass 7, count 0 2006.285.22:09:59.43#ibcon#about to read 6, iclass 7, count 0 2006.285.22:09:59.43#ibcon#read 6, iclass 7, count 0 2006.285.22:09:59.43#ibcon#end of sib2, iclass 7, count 0 2006.285.22:09:59.43#ibcon#*after write, iclass 7, count 0 2006.285.22:09:59.43#ibcon#*before return 0, iclass 7, count 0 2006.285.22:09:59.43#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:09:59.43#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:09:59.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:09:59.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:09:59.43$vck44/valo=4,624.99 2006.285.22:09:59.43#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.22:09:59.43#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.22:09:59.43#ibcon#ireg 17 cls_cnt 0 2006.285.22:09:59.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:09:59.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:09:59.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:09:59.43#ibcon#enter wrdev, iclass 11, count 0 2006.285.22:09:59.43#ibcon#first serial, iclass 11, count 0 2006.285.22:09:59.43#ibcon#enter sib2, iclass 11, count 0 2006.285.22:09:59.43#ibcon#flushed, iclass 11, count 0 2006.285.22:09:59.43#ibcon#about to write, iclass 11, count 0 2006.285.22:09:59.43#ibcon#wrote, iclass 11, count 0 2006.285.22:09:59.43#ibcon#about to read 3, iclass 11, count 0 2006.285.22:09:59.45#ibcon#read 3, iclass 11, count 0 2006.285.22:10:00.18#ibcon#about to read 4, iclass 11, count 0 2006.285.22:10:00.18#ibcon#read 4, iclass 11, count 0 2006.285.22:10:00.18#ibcon#about to read 5, iclass 11, count 0 2006.285.22:10:00.18#ibcon#read 5, iclass 11, count 0 2006.285.22:10:00.18#ibcon#about to read 6, iclass 11, count 0 2006.285.22:10:00.18#ibcon#read 6, iclass 11, count 0 2006.285.22:10:00.18#ibcon#end of sib2, iclass 11, count 0 2006.285.22:10:00.18#ibcon#*mode == 0, iclass 11, count 0 2006.285.22:10:00.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.22:10:00.18#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:10:00.18#ibcon#*before write, iclass 11, count 0 2006.285.22:10:00.18#ibcon#enter sib2, iclass 11, count 0 2006.285.22:10:00.18#ibcon#flushed, iclass 11, count 0 2006.285.22:10:00.18#ibcon#about to write, iclass 11, count 0 2006.285.22:10:00.18#ibcon#wrote, iclass 11, count 0 2006.285.22:10:00.18#ibcon#about to read 3, iclass 11, count 0 2006.285.22:10:00.22#ibcon#read 3, iclass 11, count 0 2006.285.22:10:00.22#ibcon#about to read 4, iclass 11, count 0 2006.285.22:10:00.22#ibcon#read 4, iclass 11, count 0 2006.285.22:10:00.22#ibcon#about to read 5, iclass 11, count 0 2006.285.22:10:00.22#ibcon#read 5, iclass 11, count 0 2006.285.22:10:00.22#ibcon#about to read 6, iclass 11, count 0 2006.285.22:10:00.22#ibcon#read 6, iclass 11, count 0 2006.285.22:10:00.22#ibcon#end of sib2, iclass 11, count 0 2006.285.22:10:00.22#ibcon#*after write, iclass 11, count 0 2006.285.22:10:00.22#ibcon#*before return 0, iclass 11, count 0 2006.285.22:10:00.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:10:00.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:10:00.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.22:10:00.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.22:10:00.22$vck44/va=4,6 2006.285.22:10:00.22#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.22:10:00.22#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.22:10:00.22#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:00.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:10:00.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:10:00.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:10:00.22#ibcon#enter wrdev, iclass 13, count 2 2006.285.22:10:00.22#ibcon#first serial, iclass 13, count 2 2006.285.22:10:00.22#ibcon#enter sib2, iclass 13, count 2 2006.285.22:10:00.22#ibcon#flushed, iclass 13, count 2 2006.285.22:10:00.22#ibcon#about to write, iclass 13, count 2 2006.285.22:10:00.22#ibcon#wrote, iclass 13, count 2 2006.285.22:10:00.22#ibcon#about to read 3, iclass 13, count 2 2006.285.22:10:00.24#ibcon#read 3, iclass 13, count 2 2006.285.22:10:00.24#ibcon#about to read 4, iclass 13, count 2 2006.285.22:10:00.24#ibcon#read 4, iclass 13, count 2 2006.285.22:10:00.24#ibcon#about to read 5, iclass 13, count 2 2006.285.22:10:00.24#ibcon#read 5, iclass 13, count 2 2006.285.22:10:00.24#ibcon#about to read 6, iclass 13, count 2 2006.285.22:10:00.24#ibcon#read 6, iclass 13, count 2 2006.285.22:10:00.24#ibcon#end of sib2, iclass 13, count 2 2006.285.22:10:00.24#ibcon#*mode == 0, iclass 13, count 2 2006.285.22:10:00.24#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.22:10:00.24#ibcon#[25=AT04-06\r\n] 2006.285.22:10:00.24#ibcon#*before write, iclass 13, count 2 2006.285.22:10:00.24#ibcon#enter sib2, iclass 13, count 2 2006.285.22:10:00.24#ibcon#flushed, iclass 13, count 2 2006.285.22:10:00.24#ibcon#about to write, iclass 13, count 2 2006.285.22:10:00.24#ibcon#wrote, iclass 13, count 2 2006.285.22:10:00.24#ibcon#about to read 3, iclass 13, count 2 2006.285.22:10:00.27#ibcon#read 3, iclass 13, count 2 2006.285.22:10:00.27#ibcon#about to read 4, iclass 13, count 2 2006.285.22:10:00.27#ibcon#read 4, iclass 13, count 2 2006.285.22:10:00.27#ibcon#about to read 5, iclass 13, count 2 2006.285.22:10:00.27#ibcon#read 5, iclass 13, count 2 2006.285.22:10:00.27#ibcon#about to read 6, iclass 13, count 2 2006.285.22:10:00.27#ibcon#read 6, iclass 13, count 2 2006.285.22:10:00.27#ibcon#end of sib2, iclass 13, count 2 2006.285.22:10:00.27#ibcon#*after write, iclass 13, count 2 2006.285.22:10:00.27#ibcon#*before return 0, iclass 13, count 2 2006.285.22:10:00.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:10:00.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:10:00.27#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.22:10:00.27#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:00.27#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:10:00.39#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:10:00.39#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:10:00.39#ibcon#enter wrdev, iclass 13, count 0 2006.285.22:10:00.39#ibcon#first serial, iclass 13, count 0 2006.285.22:10:00.39#ibcon#enter sib2, iclass 13, count 0 2006.285.22:10:00.39#ibcon#flushed, iclass 13, count 0 2006.285.22:10:00.39#ibcon#about to write, iclass 13, count 0 2006.285.22:10:00.39#ibcon#wrote, iclass 13, count 0 2006.285.22:10:00.39#ibcon#about to read 3, iclass 13, count 0 2006.285.22:10:00.41#ibcon#read 3, iclass 13, count 0 2006.285.22:10:00.41#ibcon#about to read 4, iclass 13, count 0 2006.285.22:10:00.41#ibcon#read 4, iclass 13, count 0 2006.285.22:10:00.41#ibcon#about to read 5, iclass 13, count 0 2006.285.22:10:00.41#ibcon#read 5, iclass 13, count 0 2006.285.22:10:00.41#ibcon#about to read 6, iclass 13, count 0 2006.285.22:10:00.41#ibcon#read 6, iclass 13, count 0 2006.285.22:10:00.41#ibcon#end of sib2, iclass 13, count 0 2006.285.22:10:00.41#ibcon#*mode == 0, iclass 13, count 0 2006.285.22:10:00.41#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.22:10:00.41#ibcon#[25=USB\r\n] 2006.285.22:10:00.41#ibcon#*before write, iclass 13, count 0 2006.285.22:10:00.41#ibcon#enter sib2, iclass 13, count 0 2006.285.22:10:00.41#ibcon#flushed, iclass 13, count 0 2006.285.22:10:00.41#ibcon#about to write, iclass 13, count 0 2006.285.22:10:00.41#ibcon#wrote, iclass 13, count 0 2006.285.22:10:00.41#ibcon#about to read 3, iclass 13, count 0 2006.285.22:10:00.44#ibcon#read 3, iclass 13, count 0 2006.285.22:10:00.44#ibcon#about to read 4, iclass 13, count 0 2006.285.22:10:00.44#ibcon#read 4, iclass 13, count 0 2006.285.22:10:00.44#ibcon#about to read 5, iclass 13, count 0 2006.285.22:10:00.44#ibcon#read 5, iclass 13, count 0 2006.285.22:10:00.44#ibcon#about to read 6, iclass 13, count 0 2006.285.22:10:00.44#ibcon#read 6, iclass 13, count 0 2006.285.22:10:00.44#ibcon#end of sib2, iclass 13, count 0 2006.285.22:10:00.44#ibcon#*after write, iclass 13, count 0 2006.285.22:10:00.44#ibcon#*before return 0, iclass 13, count 0 2006.285.22:10:00.44#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:10:00.44#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:10:00.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.22:10:00.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.22:10:00.44$vck44/valo=5,734.99 2006.285.22:10:00.44#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.22:10:00.44#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.22:10:00.44#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:00.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:10:00.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:10:00.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:10:00.44#ibcon#enter wrdev, iclass 15, count 0 2006.285.22:10:00.44#ibcon#first serial, iclass 15, count 0 2006.285.22:10:00.44#ibcon#enter sib2, iclass 15, count 0 2006.285.22:10:00.44#ibcon#flushed, iclass 15, count 0 2006.285.22:10:00.44#ibcon#about to write, iclass 15, count 0 2006.285.22:10:00.44#ibcon#wrote, iclass 15, count 0 2006.285.22:10:00.44#ibcon#about to read 3, iclass 15, count 0 2006.285.22:10:00.46#ibcon#read 3, iclass 15, count 0 2006.285.22:10:00.84#ibcon#about to read 4, iclass 15, count 0 2006.285.22:10:00.84#ibcon#read 4, iclass 15, count 0 2006.285.22:10:00.84#ibcon#about to read 5, iclass 15, count 0 2006.285.22:10:00.84#ibcon#read 5, iclass 15, count 0 2006.285.22:10:00.84#ibcon#about to read 6, iclass 15, count 0 2006.285.22:10:00.84#ibcon#read 6, iclass 15, count 0 2006.285.22:10:00.84#ibcon#end of sib2, iclass 15, count 0 2006.285.22:10:00.84#ibcon#*mode == 0, iclass 15, count 0 2006.285.22:10:00.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.22:10:00.84#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:10:00.84#ibcon#*before write, iclass 15, count 0 2006.285.22:10:00.84#ibcon#enter sib2, iclass 15, count 0 2006.285.22:10:00.84#ibcon#flushed, iclass 15, count 0 2006.285.22:10:00.84#ibcon#about to write, iclass 15, count 0 2006.285.22:10:00.84#ibcon#wrote, iclass 15, count 0 2006.285.22:10:00.84#ibcon#about to read 3, iclass 15, count 0 2006.285.22:10:00.88#ibcon#read 3, iclass 15, count 0 2006.285.22:10:00.88#ibcon#about to read 4, iclass 15, count 0 2006.285.22:10:00.88#ibcon#read 4, iclass 15, count 0 2006.285.22:10:00.88#ibcon#about to read 5, iclass 15, count 0 2006.285.22:10:00.88#ibcon#read 5, iclass 15, count 0 2006.285.22:10:00.88#ibcon#about to read 6, iclass 15, count 0 2006.285.22:10:00.88#ibcon#read 6, iclass 15, count 0 2006.285.22:10:00.88#ibcon#end of sib2, iclass 15, count 0 2006.285.22:10:00.88#ibcon#*after write, iclass 15, count 0 2006.285.22:10:00.88#ibcon#*before return 0, iclass 15, count 0 2006.285.22:10:00.88#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:10:00.88#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:10:00.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.22:10:00.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.22:10:00.88$vck44/va=5,3 2006.285.22:10:00.88#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.22:10:00.88#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.22:10:00.88#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:00.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:10:00.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:10:00.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:10:00.88#ibcon#enter wrdev, iclass 17, count 2 2006.285.22:10:00.88#ibcon#first serial, iclass 17, count 2 2006.285.22:10:00.88#ibcon#enter sib2, iclass 17, count 2 2006.285.22:10:00.88#ibcon#flushed, iclass 17, count 2 2006.285.22:10:00.88#ibcon#about to write, iclass 17, count 2 2006.285.22:10:00.88#ibcon#wrote, iclass 17, count 2 2006.285.22:10:00.88#ibcon#about to read 3, iclass 17, count 2 2006.285.22:10:00.90#ibcon#read 3, iclass 17, count 2 2006.285.22:10:00.90#ibcon#about to read 4, iclass 17, count 2 2006.285.22:10:00.90#ibcon#read 4, iclass 17, count 2 2006.285.22:10:00.90#ibcon#about to read 5, iclass 17, count 2 2006.285.22:10:00.90#ibcon#read 5, iclass 17, count 2 2006.285.22:10:00.90#ibcon#about to read 6, iclass 17, count 2 2006.285.22:10:00.90#ibcon#read 6, iclass 17, count 2 2006.285.22:10:00.90#ibcon#end of sib2, iclass 17, count 2 2006.285.22:10:00.90#ibcon#*mode == 0, iclass 17, count 2 2006.285.22:10:00.90#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.22:10:00.90#ibcon#[25=AT05-03\r\n] 2006.285.22:10:00.90#ibcon#*before write, iclass 17, count 2 2006.285.22:10:00.90#ibcon#enter sib2, iclass 17, count 2 2006.285.22:10:00.90#ibcon#flushed, iclass 17, count 2 2006.285.22:10:00.90#ibcon#about to write, iclass 17, count 2 2006.285.22:10:00.90#ibcon#wrote, iclass 17, count 2 2006.285.22:10:00.90#ibcon#about to read 3, iclass 17, count 2 2006.285.22:10:00.93#ibcon#read 3, iclass 17, count 2 2006.285.22:10:00.93#ibcon#about to read 4, iclass 17, count 2 2006.285.22:10:00.93#ibcon#read 4, iclass 17, count 2 2006.285.22:10:00.93#ibcon#about to read 5, iclass 17, count 2 2006.285.22:10:00.93#ibcon#read 5, iclass 17, count 2 2006.285.22:10:00.93#ibcon#about to read 6, iclass 17, count 2 2006.285.22:10:00.93#ibcon#read 6, iclass 17, count 2 2006.285.22:10:00.93#ibcon#end of sib2, iclass 17, count 2 2006.285.22:10:00.93#ibcon#*after write, iclass 17, count 2 2006.285.22:10:00.93#ibcon#*before return 0, iclass 17, count 2 2006.285.22:10:00.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:10:00.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:10:00.93#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.22:10:00.93#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:00.93#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:10:01.05#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:10:01.05#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:10:01.05#ibcon#enter wrdev, iclass 17, count 0 2006.285.22:10:01.05#ibcon#first serial, iclass 17, count 0 2006.285.22:10:01.05#ibcon#enter sib2, iclass 17, count 0 2006.285.22:10:01.05#ibcon#flushed, iclass 17, count 0 2006.285.22:10:01.05#ibcon#about to write, iclass 17, count 0 2006.285.22:10:01.05#ibcon#wrote, iclass 17, count 0 2006.285.22:10:01.05#ibcon#about to read 3, iclass 17, count 0 2006.285.22:10:01.07#ibcon#read 3, iclass 17, count 0 2006.285.22:10:01.07#ibcon#about to read 4, iclass 17, count 0 2006.285.22:10:01.07#ibcon#read 4, iclass 17, count 0 2006.285.22:10:01.07#ibcon#about to read 5, iclass 17, count 0 2006.285.22:10:01.07#ibcon#read 5, iclass 17, count 0 2006.285.22:10:01.07#ibcon#about to read 6, iclass 17, count 0 2006.285.22:10:01.07#ibcon#read 6, iclass 17, count 0 2006.285.22:10:01.07#ibcon#end of sib2, iclass 17, count 0 2006.285.22:10:01.07#ibcon#*mode == 0, iclass 17, count 0 2006.285.22:10:01.07#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.22:10:01.07#ibcon#[25=USB\r\n] 2006.285.22:10:01.07#ibcon#*before write, iclass 17, count 0 2006.285.22:10:01.07#ibcon#enter sib2, iclass 17, count 0 2006.285.22:10:01.07#ibcon#flushed, iclass 17, count 0 2006.285.22:10:01.07#ibcon#about to write, iclass 17, count 0 2006.285.22:10:01.07#ibcon#wrote, iclass 17, count 0 2006.285.22:10:01.07#ibcon#about to read 3, iclass 17, count 0 2006.285.22:10:01.10#ibcon#read 3, iclass 17, count 0 2006.285.22:10:01.10#ibcon#about to read 4, iclass 17, count 0 2006.285.22:10:01.10#ibcon#read 4, iclass 17, count 0 2006.285.22:10:01.10#ibcon#about to read 5, iclass 17, count 0 2006.285.22:10:01.10#ibcon#read 5, iclass 17, count 0 2006.285.22:10:01.10#ibcon#about to read 6, iclass 17, count 0 2006.285.22:10:01.10#ibcon#read 6, iclass 17, count 0 2006.285.22:10:01.10#ibcon#end of sib2, iclass 17, count 0 2006.285.22:10:01.10#ibcon#*after write, iclass 17, count 0 2006.285.22:10:01.10#ibcon#*before return 0, iclass 17, count 0 2006.285.22:10:01.10#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:10:01.10#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:10:01.10#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.22:10:01.10#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.22:10:01.10$vck44/valo=6,814.99 2006.285.22:10:01.10#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.22:10:01.10#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.22:10:01.10#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:01.10#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:10:01.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:10:01.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:10:01.10#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:10:01.10#ibcon#first serial, iclass 19, count 0 2006.285.22:10:01.10#ibcon#enter sib2, iclass 19, count 0 2006.285.22:10:01.10#ibcon#flushed, iclass 19, count 0 2006.285.22:10:01.10#ibcon#about to write, iclass 19, count 0 2006.285.22:10:01.10#ibcon#wrote, iclass 19, count 0 2006.285.22:10:01.10#ibcon#about to read 3, iclass 19, count 0 2006.285.22:10:01.12#ibcon#read 3, iclass 19, count 0 2006.285.22:10:01.12#ibcon#about to read 4, iclass 19, count 0 2006.285.22:10:01.12#ibcon#read 4, iclass 19, count 0 2006.285.22:10:01.12#ibcon#about to read 5, iclass 19, count 0 2006.285.22:10:01.12#ibcon#read 5, iclass 19, count 0 2006.285.22:10:01.12#ibcon#about to read 6, iclass 19, count 0 2006.285.22:10:01.12#ibcon#read 6, iclass 19, count 0 2006.285.22:10:01.12#ibcon#end of sib2, iclass 19, count 0 2006.285.22:10:01.12#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:10:01.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:10:01.12#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:10:01.12#ibcon#*before write, iclass 19, count 0 2006.285.22:10:01.12#ibcon#enter sib2, iclass 19, count 0 2006.285.22:10:01.12#ibcon#flushed, iclass 19, count 0 2006.285.22:10:01.12#ibcon#about to write, iclass 19, count 0 2006.285.22:10:01.12#ibcon#wrote, iclass 19, count 0 2006.285.22:10:01.12#ibcon#about to read 3, iclass 19, count 0 2006.285.22:10:01.16#ibcon#read 3, iclass 19, count 0 2006.285.22:10:01.16#ibcon#about to read 4, iclass 19, count 0 2006.285.22:10:01.16#ibcon#read 4, iclass 19, count 0 2006.285.22:10:01.16#ibcon#about to read 5, iclass 19, count 0 2006.285.22:10:01.16#ibcon#read 5, iclass 19, count 0 2006.285.22:10:01.16#ibcon#about to read 6, iclass 19, count 0 2006.285.22:10:01.16#ibcon#read 6, iclass 19, count 0 2006.285.22:10:01.16#ibcon#end of sib2, iclass 19, count 0 2006.285.22:10:01.16#ibcon#*after write, iclass 19, count 0 2006.285.22:10:01.16#ibcon#*before return 0, iclass 19, count 0 2006.285.22:10:01.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:10:01.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:10:01.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:10:01.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:10:01.16$vck44/va=6,4 2006.285.22:10:01.16#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.22:10:01.16#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.22:10:01.16#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:01.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:10:01.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:10:01.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:10:01.22#ibcon#enter wrdev, iclass 21, count 2 2006.285.22:10:01.22#ibcon#first serial, iclass 21, count 2 2006.285.22:10:01.22#ibcon#enter sib2, iclass 21, count 2 2006.285.22:10:01.22#ibcon#flushed, iclass 21, count 2 2006.285.22:10:01.22#ibcon#about to write, iclass 21, count 2 2006.285.22:10:01.22#ibcon#wrote, iclass 21, count 2 2006.285.22:10:01.22#ibcon#about to read 3, iclass 21, count 2 2006.285.22:10:01.24#ibcon#read 3, iclass 21, count 2 2006.285.22:10:01.24#ibcon#about to read 4, iclass 21, count 2 2006.285.22:10:01.24#ibcon#read 4, iclass 21, count 2 2006.285.22:10:01.24#ibcon#about to read 5, iclass 21, count 2 2006.285.22:10:01.24#ibcon#read 5, iclass 21, count 2 2006.285.22:10:01.24#ibcon#about to read 6, iclass 21, count 2 2006.285.22:10:01.24#ibcon#read 6, iclass 21, count 2 2006.285.22:10:01.24#ibcon#end of sib2, iclass 21, count 2 2006.285.22:10:01.24#ibcon#*mode == 0, iclass 21, count 2 2006.285.22:10:01.24#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.22:10:01.24#ibcon#[25=AT06-04\r\n] 2006.285.22:10:01.24#ibcon#*before write, iclass 21, count 2 2006.285.22:10:01.24#ibcon#enter sib2, iclass 21, count 2 2006.285.22:10:01.24#ibcon#flushed, iclass 21, count 2 2006.285.22:10:01.24#ibcon#about to write, iclass 21, count 2 2006.285.22:10:01.24#ibcon#wrote, iclass 21, count 2 2006.285.22:10:01.24#ibcon#about to read 3, iclass 21, count 2 2006.285.22:10:01.27#ibcon#read 3, iclass 21, count 2 2006.285.22:10:01.27#ibcon#about to read 4, iclass 21, count 2 2006.285.22:10:01.27#ibcon#read 4, iclass 21, count 2 2006.285.22:10:01.27#ibcon#about to read 5, iclass 21, count 2 2006.285.22:10:01.27#ibcon#read 5, iclass 21, count 2 2006.285.22:10:01.27#ibcon#about to read 6, iclass 21, count 2 2006.285.22:10:01.27#ibcon#read 6, iclass 21, count 2 2006.285.22:10:01.27#ibcon#end of sib2, iclass 21, count 2 2006.285.22:10:01.27#ibcon#*after write, iclass 21, count 2 2006.285.22:10:01.27#ibcon#*before return 0, iclass 21, count 2 2006.285.22:10:01.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:10:01.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:10:01.27#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.22:10:01.27#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:01.27#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:10:01.39#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:10:01.39#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:10:01.39#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:10:01.39#ibcon#first serial, iclass 21, count 0 2006.285.22:10:01.39#ibcon#enter sib2, iclass 21, count 0 2006.285.22:10:01.39#ibcon#flushed, iclass 21, count 0 2006.285.22:10:01.39#ibcon#about to write, iclass 21, count 0 2006.285.22:10:01.39#ibcon#wrote, iclass 21, count 0 2006.285.22:10:01.39#ibcon#about to read 3, iclass 21, count 0 2006.285.22:10:01.41#ibcon#read 3, iclass 21, count 0 2006.285.22:10:01.41#ibcon#about to read 4, iclass 21, count 0 2006.285.22:10:01.41#ibcon#read 4, iclass 21, count 0 2006.285.22:10:01.41#ibcon#about to read 5, iclass 21, count 0 2006.285.22:10:01.41#ibcon#read 5, iclass 21, count 0 2006.285.22:10:01.41#ibcon#about to read 6, iclass 21, count 0 2006.285.22:10:01.41#ibcon#read 6, iclass 21, count 0 2006.285.22:10:01.41#ibcon#end of sib2, iclass 21, count 0 2006.285.22:10:01.41#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:10:01.41#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:10:01.41#ibcon#[25=USB\r\n] 2006.285.22:10:01.41#ibcon#*before write, iclass 21, count 0 2006.285.22:10:01.41#ibcon#enter sib2, iclass 21, count 0 2006.285.22:10:01.41#ibcon#flushed, iclass 21, count 0 2006.285.22:10:01.41#ibcon#about to write, iclass 21, count 0 2006.285.22:10:01.41#ibcon#wrote, iclass 21, count 0 2006.285.22:10:01.41#ibcon#about to read 3, iclass 21, count 0 2006.285.22:10:01.44#ibcon#read 3, iclass 21, count 0 2006.285.22:10:01.44#ibcon#about to read 4, iclass 21, count 0 2006.285.22:10:01.44#ibcon#read 4, iclass 21, count 0 2006.285.22:10:01.44#ibcon#about to read 5, iclass 21, count 0 2006.285.22:10:01.44#ibcon#read 5, iclass 21, count 0 2006.285.22:10:01.44#ibcon#about to read 6, iclass 21, count 0 2006.285.22:10:01.44#ibcon#read 6, iclass 21, count 0 2006.285.22:10:01.44#ibcon#end of sib2, iclass 21, count 0 2006.285.22:10:01.44#ibcon#*after write, iclass 21, count 0 2006.285.22:10:01.44#ibcon#*before return 0, iclass 21, count 0 2006.285.22:10:01.44#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:10:01.44#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:10:01.44#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:10:01.44#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:10:01.44$vck44/valo=7,864.99 2006.285.22:10:01.44#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.22:10:01.44#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.22:10:01.44#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:01.44#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:10:01.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:10:01.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:10:01.44#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:10:01.44#ibcon#first serial, iclass 23, count 0 2006.285.22:10:01.44#ibcon#enter sib2, iclass 23, count 0 2006.285.22:10:01.44#ibcon#flushed, iclass 23, count 0 2006.285.22:10:01.44#ibcon#about to write, iclass 23, count 0 2006.285.22:10:01.44#ibcon#wrote, iclass 23, count 0 2006.285.22:10:01.44#ibcon#about to read 3, iclass 23, count 0 2006.285.22:10:01.46#ibcon#read 3, iclass 23, count 0 2006.285.22:10:01.46#ibcon#about to read 4, iclass 23, count 0 2006.285.22:10:01.46#ibcon#read 4, iclass 23, count 0 2006.285.22:10:01.46#ibcon#about to read 5, iclass 23, count 0 2006.285.22:10:01.46#ibcon#read 5, iclass 23, count 0 2006.285.22:10:01.46#ibcon#about to read 6, iclass 23, count 0 2006.285.22:10:01.46#ibcon#read 6, iclass 23, count 0 2006.285.22:10:01.46#ibcon#end of sib2, iclass 23, count 0 2006.285.22:10:01.46#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:10:01.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:10:01.46#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:10:01.46#ibcon#*before write, iclass 23, count 0 2006.285.22:10:01.46#ibcon#enter sib2, iclass 23, count 0 2006.285.22:10:01.46#ibcon#flushed, iclass 23, count 0 2006.285.22:10:01.46#ibcon#about to write, iclass 23, count 0 2006.285.22:10:01.46#ibcon#wrote, iclass 23, count 0 2006.285.22:10:01.46#ibcon#about to read 3, iclass 23, count 0 2006.285.22:10:01.50#ibcon#read 3, iclass 23, count 0 2006.285.22:10:01.56#ibcon#about to read 4, iclass 23, count 0 2006.285.22:10:01.56#ibcon#read 4, iclass 23, count 0 2006.285.22:10:01.56#ibcon#about to read 5, iclass 23, count 0 2006.285.22:10:01.56#ibcon#read 5, iclass 23, count 0 2006.285.22:10:01.56#ibcon#about to read 6, iclass 23, count 0 2006.285.22:10:01.56#ibcon#read 6, iclass 23, count 0 2006.285.22:10:01.56#ibcon#end of sib2, iclass 23, count 0 2006.285.22:10:01.56#ibcon#*after write, iclass 23, count 0 2006.285.22:10:01.56#ibcon#*before return 0, iclass 23, count 0 2006.285.22:10:01.56#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:10:01.56#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:10:01.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:10:01.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:10:01.56$vck44/va=7,4 2006.285.22:10:01.56#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.22:10:01.56#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.22:10:01.56#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:01.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:10:01.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:10:01.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:10:01.56#ibcon#enter wrdev, iclass 25, count 2 2006.285.22:10:01.56#ibcon#first serial, iclass 25, count 2 2006.285.22:10:01.56#ibcon#enter sib2, iclass 25, count 2 2006.285.22:10:01.56#ibcon#flushed, iclass 25, count 2 2006.285.22:10:01.56#ibcon#about to write, iclass 25, count 2 2006.285.22:10:01.56#ibcon#wrote, iclass 25, count 2 2006.285.22:10:01.56#ibcon#about to read 3, iclass 25, count 2 2006.285.22:10:01.58#ibcon#read 3, iclass 25, count 2 2006.285.22:10:01.58#ibcon#about to read 4, iclass 25, count 2 2006.285.22:10:01.58#ibcon#read 4, iclass 25, count 2 2006.285.22:10:01.58#ibcon#about to read 5, iclass 25, count 2 2006.285.22:10:01.58#ibcon#read 5, iclass 25, count 2 2006.285.22:10:01.58#ibcon#about to read 6, iclass 25, count 2 2006.285.22:10:01.58#ibcon#read 6, iclass 25, count 2 2006.285.22:10:01.58#ibcon#end of sib2, iclass 25, count 2 2006.285.22:10:01.58#ibcon#*mode == 0, iclass 25, count 2 2006.285.22:10:01.58#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.22:10:01.58#ibcon#[25=AT07-04\r\n] 2006.285.22:10:01.58#ibcon#*before write, iclass 25, count 2 2006.285.22:10:01.58#ibcon#enter sib2, iclass 25, count 2 2006.285.22:10:01.58#ibcon#flushed, iclass 25, count 2 2006.285.22:10:01.58#ibcon#about to write, iclass 25, count 2 2006.285.22:10:01.58#ibcon#wrote, iclass 25, count 2 2006.285.22:10:01.58#ibcon#about to read 3, iclass 25, count 2 2006.285.22:10:01.61#ibcon#read 3, iclass 25, count 2 2006.285.22:10:01.61#ibcon#about to read 4, iclass 25, count 2 2006.285.22:10:01.61#ibcon#read 4, iclass 25, count 2 2006.285.22:10:01.61#ibcon#about to read 5, iclass 25, count 2 2006.285.22:10:01.61#ibcon#read 5, iclass 25, count 2 2006.285.22:10:01.61#ibcon#about to read 6, iclass 25, count 2 2006.285.22:10:01.61#ibcon#read 6, iclass 25, count 2 2006.285.22:10:01.61#ibcon#end of sib2, iclass 25, count 2 2006.285.22:10:01.61#ibcon#*after write, iclass 25, count 2 2006.285.22:10:01.61#ibcon#*before return 0, iclass 25, count 2 2006.285.22:10:01.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:10:01.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:10:01.61#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.22:10:01.61#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:01.61#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:10:01.73#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:10:01.73#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:10:01.73#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:10:01.73#ibcon#first serial, iclass 25, count 0 2006.285.22:10:01.73#ibcon#enter sib2, iclass 25, count 0 2006.285.22:10:01.73#ibcon#flushed, iclass 25, count 0 2006.285.22:10:01.73#ibcon#about to write, iclass 25, count 0 2006.285.22:10:01.73#ibcon#wrote, iclass 25, count 0 2006.285.22:10:01.73#ibcon#about to read 3, iclass 25, count 0 2006.285.22:10:01.75#ibcon#read 3, iclass 25, count 0 2006.285.22:10:01.75#ibcon#about to read 4, iclass 25, count 0 2006.285.22:10:01.75#ibcon#read 4, iclass 25, count 0 2006.285.22:10:01.75#ibcon#about to read 5, iclass 25, count 0 2006.285.22:10:01.75#ibcon#read 5, iclass 25, count 0 2006.285.22:10:01.75#ibcon#about to read 6, iclass 25, count 0 2006.285.22:10:01.75#ibcon#read 6, iclass 25, count 0 2006.285.22:10:01.75#ibcon#end of sib2, iclass 25, count 0 2006.285.22:10:01.75#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:10:01.75#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:10:01.75#ibcon#[25=USB\r\n] 2006.285.22:10:01.75#ibcon#*before write, iclass 25, count 0 2006.285.22:10:01.75#ibcon#enter sib2, iclass 25, count 0 2006.285.22:10:01.75#ibcon#flushed, iclass 25, count 0 2006.285.22:10:01.75#ibcon#about to write, iclass 25, count 0 2006.285.22:10:01.75#ibcon#wrote, iclass 25, count 0 2006.285.22:10:01.75#ibcon#about to read 3, iclass 25, count 0 2006.285.22:10:01.78#ibcon#read 3, iclass 25, count 0 2006.285.22:10:01.78#ibcon#about to read 4, iclass 25, count 0 2006.285.22:10:01.78#ibcon#read 4, iclass 25, count 0 2006.285.22:10:01.78#ibcon#about to read 5, iclass 25, count 0 2006.285.22:10:01.78#ibcon#read 5, iclass 25, count 0 2006.285.22:10:01.78#ibcon#about to read 6, iclass 25, count 0 2006.285.22:10:01.78#ibcon#read 6, iclass 25, count 0 2006.285.22:10:01.78#ibcon#end of sib2, iclass 25, count 0 2006.285.22:10:01.78#ibcon#*after write, iclass 25, count 0 2006.285.22:10:01.78#ibcon#*before return 0, iclass 25, count 0 2006.285.22:10:01.78#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:10:01.78#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:10:01.78#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:10:01.78#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:10:01.78$vck44/valo=8,884.99 2006.285.22:10:01.78#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.22:10:01.78#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.22:10:01.78#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:01.78#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:10:01.78#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:10:01.78#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:10:01.78#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:10:01.78#ibcon#first serial, iclass 27, count 0 2006.285.22:10:01.78#ibcon#enter sib2, iclass 27, count 0 2006.285.22:10:01.78#ibcon#flushed, iclass 27, count 0 2006.285.22:10:01.78#ibcon#about to write, iclass 27, count 0 2006.285.22:10:01.78#ibcon#wrote, iclass 27, count 0 2006.285.22:10:01.78#ibcon#about to read 3, iclass 27, count 0 2006.285.22:10:01.80#ibcon#read 3, iclass 27, count 0 2006.285.22:10:01.80#ibcon#about to read 4, iclass 27, count 0 2006.285.22:10:01.80#ibcon#read 4, iclass 27, count 0 2006.285.22:10:01.80#ibcon#about to read 5, iclass 27, count 0 2006.285.22:10:01.80#ibcon#read 5, iclass 27, count 0 2006.285.22:10:01.80#ibcon#about to read 6, iclass 27, count 0 2006.285.22:10:01.80#ibcon#read 6, iclass 27, count 0 2006.285.22:10:01.80#ibcon#end of sib2, iclass 27, count 0 2006.285.22:10:01.80#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:10:01.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:10:01.80#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:10:01.80#ibcon#*before write, iclass 27, count 0 2006.285.22:10:01.80#ibcon#enter sib2, iclass 27, count 0 2006.285.22:10:01.80#ibcon#flushed, iclass 27, count 0 2006.285.22:10:01.80#ibcon#about to write, iclass 27, count 0 2006.285.22:10:01.80#ibcon#wrote, iclass 27, count 0 2006.285.22:10:01.80#ibcon#about to read 3, iclass 27, count 0 2006.285.22:10:01.84#ibcon#read 3, iclass 27, count 0 2006.285.22:10:01.84#ibcon#about to read 4, iclass 27, count 0 2006.285.22:10:01.84#ibcon#read 4, iclass 27, count 0 2006.285.22:10:01.84#ibcon#about to read 5, iclass 27, count 0 2006.285.22:10:01.84#ibcon#read 5, iclass 27, count 0 2006.285.22:10:01.84#ibcon#about to read 6, iclass 27, count 0 2006.285.22:10:01.84#ibcon#read 6, iclass 27, count 0 2006.285.22:10:01.84#ibcon#end of sib2, iclass 27, count 0 2006.285.22:10:01.84#ibcon#*after write, iclass 27, count 0 2006.285.22:10:01.84#ibcon#*before return 0, iclass 27, count 0 2006.285.22:10:01.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:10:01.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:10:01.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:10:01.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:10:01.84$vck44/va=8,3 2006.285.22:10:01.84#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.22:10:01.84#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.22:10:01.84#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:01.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:10:01.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:10:01.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:10:01.90#ibcon#enter wrdev, iclass 29, count 2 2006.285.22:10:01.90#ibcon#first serial, iclass 29, count 2 2006.285.22:10:01.90#ibcon#enter sib2, iclass 29, count 2 2006.285.22:10:01.90#ibcon#flushed, iclass 29, count 2 2006.285.22:10:01.90#ibcon#about to write, iclass 29, count 2 2006.285.22:10:01.90#ibcon#wrote, iclass 29, count 2 2006.285.22:10:01.90#ibcon#about to read 3, iclass 29, count 2 2006.285.22:10:01.92#ibcon#read 3, iclass 29, count 2 2006.285.22:10:01.92#ibcon#about to read 4, iclass 29, count 2 2006.285.22:10:01.92#ibcon#read 4, iclass 29, count 2 2006.285.22:10:01.92#ibcon#about to read 5, iclass 29, count 2 2006.285.22:10:01.92#ibcon#read 5, iclass 29, count 2 2006.285.22:10:01.92#ibcon#about to read 6, iclass 29, count 2 2006.285.22:10:01.92#ibcon#read 6, iclass 29, count 2 2006.285.22:10:01.92#ibcon#end of sib2, iclass 29, count 2 2006.285.22:10:01.92#ibcon#*mode == 0, iclass 29, count 2 2006.285.22:10:01.92#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.22:10:01.92#ibcon#[25=AT08-03\r\n] 2006.285.22:10:01.92#ibcon#*before write, iclass 29, count 2 2006.285.22:10:01.92#ibcon#enter sib2, iclass 29, count 2 2006.285.22:10:01.92#ibcon#flushed, iclass 29, count 2 2006.285.22:10:01.92#ibcon#about to write, iclass 29, count 2 2006.285.22:10:01.92#ibcon#wrote, iclass 29, count 2 2006.285.22:10:01.92#ibcon#about to read 3, iclass 29, count 2 2006.285.22:10:01.95#ibcon#read 3, iclass 29, count 2 2006.285.22:10:01.95#ibcon#about to read 4, iclass 29, count 2 2006.285.22:10:01.95#ibcon#read 4, iclass 29, count 2 2006.285.22:10:01.95#ibcon#about to read 5, iclass 29, count 2 2006.285.22:10:01.95#ibcon#read 5, iclass 29, count 2 2006.285.22:10:01.95#ibcon#about to read 6, iclass 29, count 2 2006.285.22:10:01.95#ibcon#read 6, iclass 29, count 2 2006.285.22:10:01.95#ibcon#end of sib2, iclass 29, count 2 2006.285.22:10:01.95#ibcon#*after write, iclass 29, count 2 2006.285.22:10:01.95#ibcon#*before return 0, iclass 29, count 2 2006.285.22:10:01.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:10:01.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:10:01.95#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.22:10:01.95#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:01.95#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:10:02.07#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:10:02.07#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:10:02.07#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:10:02.07#ibcon#first serial, iclass 29, count 0 2006.285.22:10:02.07#ibcon#enter sib2, iclass 29, count 0 2006.285.22:10:02.07#ibcon#flushed, iclass 29, count 0 2006.285.22:10:02.07#ibcon#about to write, iclass 29, count 0 2006.285.22:10:02.07#ibcon#wrote, iclass 29, count 0 2006.285.22:10:02.07#ibcon#about to read 3, iclass 29, count 0 2006.285.22:10:02.09#ibcon#read 3, iclass 29, count 0 2006.285.22:10:02.09#ibcon#about to read 4, iclass 29, count 0 2006.285.22:10:02.09#ibcon#read 4, iclass 29, count 0 2006.285.22:10:02.09#ibcon#about to read 5, iclass 29, count 0 2006.285.22:10:02.09#ibcon#read 5, iclass 29, count 0 2006.285.22:10:02.09#ibcon#about to read 6, iclass 29, count 0 2006.285.22:10:02.09#ibcon#read 6, iclass 29, count 0 2006.285.22:10:02.09#ibcon#end of sib2, iclass 29, count 0 2006.285.22:10:02.09#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:10:02.09#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:10:02.09#ibcon#[25=USB\r\n] 2006.285.22:10:02.09#ibcon#*before write, iclass 29, count 0 2006.285.22:10:02.09#ibcon#enter sib2, iclass 29, count 0 2006.285.22:10:02.09#ibcon#flushed, iclass 29, count 0 2006.285.22:10:02.09#ibcon#about to write, iclass 29, count 0 2006.285.22:10:02.09#ibcon#wrote, iclass 29, count 0 2006.285.22:10:02.09#ibcon#about to read 3, iclass 29, count 0 2006.285.22:10:02.12#ibcon#read 3, iclass 29, count 0 2006.285.22:10:02.12#ibcon#about to read 4, iclass 29, count 0 2006.285.22:10:02.12#ibcon#read 4, iclass 29, count 0 2006.285.22:10:02.12#ibcon#about to read 5, iclass 29, count 0 2006.285.22:10:02.12#ibcon#read 5, iclass 29, count 0 2006.285.22:10:02.12#ibcon#about to read 6, iclass 29, count 0 2006.285.22:10:02.12#ibcon#read 6, iclass 29, count 0 2006.285.22:10:02.12#ibcon#end of sib2, iclass 29, count 0 2006.285.22:10:02.12#ibcon#*after write, iclass 29, count 0 2006.285.22:10:02.12#ibcon#*before return 0, iclass 29, count 0 2006.285.22:10:02.12#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:10:02.12#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:10:02.12#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:10:02.12#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:10:02.12$vck44/vblo=1,629.99 2006.285.22:10:02.12#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.22:10:02.12#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.22:10:02.12#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:02.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:10:02.12#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:10:02.12#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:10:02.12#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:10:02.12#ibcon#first serial, iclass 31, count 0 2006.285.22:10:02.12#ibcon#enter sib2, iclass 31, count 0 2006.285.22:10:02.12#ibcon#flushed, iclass 31, count 0 2006.285.22:10:02.12#ibcon#about to write, iclass 31, count 0 2006.285.22:10:02.12#ibcon#wrote, iclass 31, count 0 2006.285.22:10:02.12#ibcon#about to read 3, iclass 31, count 0 2006.285.22:10:02.14#ibcon#read 3, iclass 31, count 0 2006.285.22:10:02.14#ibcon#about to read 4, iclass 31, count 0 2006.285.22:10:02.14#ibcon#read 4, iclass 31, count 0 2006.285.22:10:02.14#ibcon#about to read 5, iclass 31, count 0 2006.285.22:10:02.14#ibcon#read 5, iclass 31, count 0 2006.285.22:10:02.14#ibcon#about to read 6, iclass 31, count 0 2006.285.22:10:02.14#ibcon#read 6, iclass 31, count 0 2006.285.22:10:02.14#ibcon#end of sib2, iclass 31, count 0 2006.285.22:10:02.14#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:10:02.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:10:02.14#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:10:02.14#ibcon#*before write, iclass 31, count 0 2006.285.22:10:02.14#ibcon#enter sib2, iclass 31, count 0 2006.285.22:10:02.14#ibcon#flushed, iclass 31, count 0 2006.285.22:10:02.14#ibcon#about to write, iclass 31, count 0 2006.285.22:10:02.14#ibcon#wrote, iclass 31, count 0 2006.285.22:10:02.14#ibcon#about to read 3, iclass 31, count 0 2006.285.22:10:02.18#ibcon#read 3, iclass 31, count 0 2006.285.22:10:02.18#ibcon#about to read 4, iclass 31, count 0 2006.285.22:10:02.18#ibcon#read 4, iclass 31, count 0 2006.285.22:10:02.18#ibcon#about to read 5, iclass 31, count 0 2006.285.22:10:02.18#ibcon#read 5, iclass 31, count 0 2006.285.22:10:02.18#ibcon#about to read 6, iclass 31, count 0 2006.285.22:10:02.18#ibcon#read 6, iclass 31, count 0 2006.285.22:10:02.18#ibcon#end of sib2, iclass 31, count 0 2006.285.22:10:02.18#ibcon#*after write, iclass 31, count 0 2006.285.22:10:02.18#ibcon#*before return 0, iclass 31, count 0 2006.285.22:10:02.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:10:02.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:10:02.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:10:02.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:10:02.18$vck44/vb=1,4 2006.285.22:10:02.18#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.22:10:02.18#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.22:10:02.18#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:02.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:10:02.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:10:02.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:10:02.18#ibcon#enter wrdev, iclass 33, count 2 2006.285.22:10:02.18#ibcon#first serial, iclass 33, count 2 2006.285.22:10:02.18#ibcon#enter sib2, iclass 33, count 2 2006.285.22:10:02.18#ibcon#flushed, iclass 33, count 2 2006.285.22:10:02.18#ibcon#about to write, iclass 33, count 2 2006.285.22:10:02.18#ibcon#wrote, iclass 33, count 2 2006.285.22:10:02.18#ibcon#about to read 3, iclass 33, count 2 2006.285.22:10:02.20#ibcon#read 3, iclass 33, count 2 2006.285.22:10:02.20#ibcon#about to read 4, iclass 33, count 2 2006.285.22:10:02.20#ibcon#read 4, iclass 33, count 2 2006.285.22:10:02.20#ibcon#about to read 5, iclass 33, count 2 2006.285.22:10:02.20#ibcon#read 5, iclass 33, count 2 2006.285.22:10:02.20#ibcon#about to read 6, iclass 33, count 2 2006.285.22:10:02.20#ibcon#read 6, iclass 33, count 2 2006.285.22:10:02.20#ibcon#end of sib2, iclass 33, count 2 2006.285.22:10:02.20#ibcon#*mode == 0, iclass 33, count 2 2006.285.22:10:02.20#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.22:10:02.20#ibcon#[27=AT01-04\r\n] 2006.285.22:10:02.20#ibcon#*before write, iclass 33, count 2 2006.285.22:10:02.20#ibcon#enter sib2, iclass 33, count 2 2006.285.22:10:02.20#ibcon#flushed, iclass 33, count 2 2006.285.22:10:02.20#ibcon#about to write, iclass 33, count 2 2006.285.22:10:02.20#ibcon#wrote, iclass 33, count 2 2006.285.22:10:02.20#ibcon#about to read 3, iclass 33, count 2 2006.285.22:10:02.23#ibcon#read 3, iclass 33, count 2 2006.285.22:10:02.23#ibcon#about to read 4, iclass 33, count 2 2006.285.22:10:02.23#ibcon#read 4, iclass 33, count 2 2006.285.22:10:02.23#ibcon#about to read 5, iclass 33, count 2 2006.285.22:10:02.23#ibcon#read 5, iclass 33, count 2 2006.285.22:10:02.23#ibcon#about to read 6, iclass 33, count 2 2006.285.22:10:02.23#ibcon#read 6, iclass 33, count 2 2006.285.22:10:02.23#ibcon#end of sib2, iclass 33, count 2 2006.285.22:10:02.23#ibcon#*after write, iclass 33, count 2 2006.285.22:10:02.23#ibcon#*before return 0, iclass 33, count 2 2006.285.22:10:02.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:10:02.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:10:02.23#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.22:10:02.23#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:02.23#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:10:02.35#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:10:02.35#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:10:02.35#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:10:02.35#ibcon#first serial, iclass 33, count 0 2006.285.22:10:02.35#ibcon#enter sib2, iclass 33, count 0 2006.285.22:10:02.35#ibcon#flushed, iclass 33, count 0 2006.285.22:10:02.35#ibcon#about to write, iclass 33, count 0 2006.285.22:10:02.35#ibcon#wrote, iclass 33, count 0 2006.285.22:10:02.35#ibcon#about to read 3, iclass 33, count 0 2006.285.22:10:02.37#ibcon#read 3, iclass 33, count 0 2006.285.22:10:02.37#ibcon#about to read 4, iclass 33, count 0 2006.285.22:10:02.37#ibcon#read 4, iclass 33, count 0 2006.285.22:10:02.37#ibcon#about to read 5, iclass 33, count 0 2006.285.22:10:02.37#ibcon#read 5, iclass 33, count 0 2006.285.22:10:02.37#ibcon#about to read 6, iclass 33, count 0 2006.285.22:10:02.37#ibcon#read 6, iclass 33, count 0 2006.285.22:10:02.37#ibcon#end of sib2, iclass 33, count 0 2006.285.22:10:02.37#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:10:02.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:10:02.37#ibcon#[27=USB\r\n] 2006.285.22:10:02.37#ibcon#*before write, iclass 33, count 0 2006.285.22:10:02.37#ibcon#enter sib2, iclass 33, count 0 2006.285.22:10:02.37#ibcon#flushed, iclass 33, count 0 2006.285.22:10:02.37#ibcon#about to write, iclass 33, count 0 2006.285.22:10:02.37#ibcon#wrote, iclass 33, count 0 2006.285.22:10:02.37#ibcon#about to read 3, iclass 33, count 0 2006.285.22:10:02.40#ibcon#read 3, iclass 33, count 0 2006.285.22:10:02.40#ibcon#about to read 4, iclass 33, count 0 2006.285.22:10:02.40#ibcon#read 4, iclass 33, count 0 2006.285.22:10:02.40#ibcon#about to read 5, iclass 33, count 0 2006.285.22:10:02.40#ibcon#read 5, iclass 33, count 0 2006.285.22:10:02.40#ibcon#about to read 6, iclass 33, count 0 2006.285.22:10:02.40#ibcon#read 6, iclass 33, count 0 2006.285.22:10:02.40#ibcon#end of sib2, iclass 33, count 0 2006.285.22:10:02.40#ibcon#*after write, iclass 33, count 0 2006.285.22:10:02.40#ibcon#*before return 0, iclass 33, count 0 2006.285.22:10:02.40#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:10:02.40#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:10:02.40#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:10:02.40#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:10:02.40$vck44/vblo=2,634.99 2006.285.22:10:02.40#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.22:10:02.40#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.22:10:02.40#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:02.40#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:10:02.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:10:02.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:10:02.40#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:10:02.40#ibcon#first serial, iclass 35, count 0 2006.285.22:10:02.40#ibcon#enter sib2, iclass 35, count 0 2006.285.22:10:02.40#ibcon#flushed, iclass 35, count 0 2006.285.22:10:02.40#ibcon#about to write, iclass 35, count 0 2006.285.22:10:02.40#ibcon#wrote, iclass 35, count 0 2006.285.22:10:02.40#ibcon#about to read 3, iclass 35, count 0 2006.285.22:10:02.42#ibcon#read 3, iclass 35, count 0 2006.285.22:10:02.42#ibcon#about to read 4, iclass 35, count 0 2006.285.22:10:02.42#ibcon#read 4, iclass 35, count 0 2006.285.22:10:02.42#ibcon#about to read 5, iclass 35, count 0 2006.285.22:10:02.42#ibcon#read 5, iclass 35, count 0 2006.285.22:10:02.42#ibcon#about to read 6, iclass 35, count 0 2006.285.22:10:02.42#ibcon#read 6, iclass 35, count 0 2006.285.22:10:02.42#ibcon#end of sib2, iclass 35, count 0 2006.285.22:10:02.42#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:10:02.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:10:02.42#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:10:02.42#ibcon#*before write, iclass 35, count 0 2006.285.22:10:02.42#ibcon#enter sib2, iclass 35, count 0 2006.285.22:10:02.42#ibcon#flushed, iclass 35, count 0 2006.285.22:10:02.42#ibcon#about to write, iclass 35, count 0 2006.285.22:10:02.42#ibcon#wrote, iclass 35, count 0 2006.285.22:10:02.42#ibcon#about to read 3, iclass 35, count 0 2006.285.22:10:02.46#ibcon#read 3, iclass 35, count 0 2006.285.22:10:02.46#ibcon#about to read 4, iclass 35, count 0 2006.285.22:10:02.46#ibcon#read 4, iclass 35, count 0 2006.285.22:10:02.46#ibcon#about to read 5, iclass 35, count 0 2006.285.22:10:02.46#ibcon#read 5, iclass 35, count 0 2006.285.22:10:02.46#ibcon#about to read 6, iclass 35, count 0 2006.285.22:10:02.46#ibcon#read 6, iclass 35, count 0 2006.285.22:10:02.46#ibcon#end of sib2, iclass 35, count 0 2006.285.22:10:02.46#ibcon#*after write, iclass 35, count 0 2006.285.22:10:02.46#ibcon#*before return 0, iclass 35, count 0 2006.285.22:10:02.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:10:02.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:10:02.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:10:02.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:10:02.46$vck44/vb=2,5 2006.285.22:10:02.46#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.22:10:02.46#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.22:10:02.46#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:02.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:10:02.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:10:02.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:10:02.52#ibcon#enter wrdev, iclass 37, count 2 2006.285.22:10:02.52#ibcon#first serial, iclass 37, count 2 2006.285.22:10:02.52#ibcon#enter sib2, iclass 37, count 2 2006.285.22:10:02.52#ibcon#flushed, iclass 37, count 2 2006.285.22:10:02.52#ibcon#about to write, iclass 37, count 2 2006.285.22:10:02.52#ibcon#wrote, iclass 37, count 2 2006.285.22:10:02.52#ibcon#about to read 3, iclass 37, count 2 2006.285.22:10:02.54#ibcon#read 3, iclass 37, count 2 2006.285.22:10:02.54#ibcon#about to read 4, iclass 37, count 2 2006.285.22:10:02.54#ibcon#read 4, iclass 37, count 2 2006.285.22:10:02.54#ibcon#about to read 5, iclass 37, count 2 2006.285.22:10:02.54#ibcon#read 5, iclass 37, count 2 2006.285.22:10:02.54#ibcon#about to read 6, iclass 37, count 2 2006.285.22:10:02.54#ibcon#read 6, iclass 37, count 2 2006.285.22:10:02.54#ibcon#end of sib2, iclass 37, count 2 2006.285.22:10:02.54#ibcon#*mode == 0, iclass 37, count 2 2006.285.22:10:02.54#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.22:10:02.54#ibcon#[27=AT02-05\r\n] 2006.285.22:10:02.54#ibcon#*before write, iclass 37, count 2 2006.285.22:10:02.54#ibcon#enter sib2, iclass 37, count 2 2006.285.22:10:02.54#ibcon#flushed, iclass 37, count 2 2006.285.22:10:02.54#ibcon#about to write, iclass 37, count 2 2006.285.22:10:02.54#ibcon#wrote, iclass 37, count 2 2006.285.22:10:02.54#ibcon#about to read 3, iclass 37, count 2 2006.285.22:10:02.57#ibcon#read 3, iclass 37, count 2 2006.285.22:10:02.70#ibcon#about to read 4, iclass 37, count 2 2006.285.22:10:02.70#ibcon#read 4, iclass 37, count 2 2006.285.22:10:02.70#ibcon#about to read 5, iclass 37, count 2 2006.285.22:10:02.70#ibcon#read 5, iclass 37, count 2 2006.285.22:10:02.70#ibcon#about to read 6, iclass 37, count 2 2006.285.22:10:02.70#ibcon#read 6, iclass 37, count 2 2006.285.22:10:02.70#ibcon#end of sib2, iclass 37, count 2 2006.285.22:10:02.70#ibcon#*after write, iclass 37, count 2 2006.285.22:10:02.70#ibcon#*before return 0, iclass 37, count 2 2006.285.22:10:02.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:10:02.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:10:02.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.22:10:02.70#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:02.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:10:02.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:10:02.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:10:02.82#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:10:02.82#ibcon#first serial, iclass 37, count 0 2006.285.22:10:02.82#ibcon#enter sib2, iclass 37, count 0 2006.285.22:10:02.82#ibcon#flushed, iclass 37, count 0 2006.285.22:10:02.82#ibcon#about to write, iclass 37, count 0 2006.285.22:10:02.82#ibcon#wrote, iclass 37, count 0 2006.285.22:10:02.82#ibcon#about to read 3, iclass 37, count 0 2006.285.22:10:02.84#ibcon#read 3, iclass 37, count 0 2006.285.22:10:02.84#ibcon#about to read 4, iclass 37, count 0 2006.285.22:10:02.84#ibcon#read 4, iclass 37, count 0 2006.285.22:10:02.84#ibcon#about to read 5, iclass 37, count 0 2006.285.22:10:02.84#ibcon#read 5, iclass 37, count 0 2006.285.22:10:02.84#ibcon#about to read 6, iclass 37, count 0 2006.285.22:10:02.84#ibcon#read 6, iclass 37, count 0 2006.285.22:10:02.84#ibcon#end of sib2, iclass 37, count 0 2006.285.22:10:02.84#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:10:02.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:10:02.84#ibcon#[27=USB\r\n] 2006.285.22:10:02.84#ibcon#*before write, iclass 37, count 0 2006.285.22:10:02.84#ibcon#enter sib2, iclass 37, count 0 2006.285.22:10:02.84#ibcon#flushed, iclass 37, count 0 2006.285.22:10:02.84#ibcon#about to write, iclass 37, count 0 2006.285.22:10:02.84#ibcon#wrote, iclass 37, count 0 2006.285.22:10:02.84#ibcon#about to read 3, iclass 37, count 0 2006.285.22:10:02.87#ibcon#read 3, iclass 37, count 0 2006.285.22:10:02.87#ibcon#about to read 4, iclass 37, count 0 2006.285.22:10:02.87#ibcon#read 4, iclass 37, count 0 2006.285.22:10:02.87#ibcon#about to read 5, iclass 37, count 0 2006.285.22:10:02.87#ibcon#read 5, iclass 37, count 0 2006.285.22:10:02.87#ibcon#about to read 6, iclass 37, count 0 2006.285.22:10:02.87#ibcon#read 6, iclass 37, count 0 2006.285.22:10:02.87#ibcon#end of sib2, iclass 37, count 0 2006.285.22:10:02.87#ibcon#*after write, iclass 37, count 0 2006.285.22:10:02.87#ibcon#*before return 0, iclass 37, count 0 2006.285.22:10:02.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:10:02.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:10:02.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:10:02.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:10:02.87$vck44/vblo=3,649.99 2006.285.22:10:02.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.22:10:02.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.22:10:02.87#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:02.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:10:02.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:10:02.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:10:02.87#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:10:02.87#ibcon#first serial, iclass 39, count 0 2006.285.22:10:02.87#ibcon#enter sib2, iclass 39, count 0 2006.285.22:10:02.87#ibcon#flushed, iclass 39, count 0 2006.285.22:10:02.87#ibcon#about to write, iclass 39, count 0 2006.285.22:10:02.87#ibcon#wrote, iclass 39, count 0 2006.285.22:10:02.87#ibcon#about to read 3, iclass 39, count 0 2006.285.22:10:02.89#ibcon#read 3, iclass 39, count 0 2006.285.22:10:02.89#ibcon#about to read 4, iclass 39, count 0 2006.285.22:10:02.89#ibcon#read 4, iclass 39, count 0 2006.285.22:10:02.89#ibcon#about to read 5, iclass 39, count 0 2006.285.22:10:02.89#ibcon#read 5, iclass 39, count 0 2006.285.22:10:02.89#ibcon#about to read 6, iclass 39, count 0 2006.285.22:10:02.89#ibcon#read 6, iclass 39, count 0 2006.285.22:10:02.89#ibcon#end of sib2, iclass 39, count 0 2006.285.22:10:02.89#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:10:02.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:10:02.89#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:10:02.89#ibcon#*before write, iclass 39, count 0 2006.285.22:10:02.89#ibcon#enter sib2, iclass 39, count 0 2006.285.22:10:02.89#ibcon#flushed, iclass 39, count 0 2006.285.22:10:02.89#ibcon#about to write, iclass 39, count 0 2006.285.22:10:02.89#ibcon#wrote, iclass 39, count 0 2006.285.22:10:02.89#ibcon#about to read 3, iclass 39, count 0 2006.285.22:10:02.93#ibcon#read 3, iclass 39, count 0 2006.285.22:10:02.93#ibcon#about to read 4, iclass 39, count 0 2006.285.22:10:02.93#ibcon#read 4, iclass 39, count 0 2006.285.22:10:02.93#ibcon#about to read 5, iclass 39, count 0 2006.285.22:10:02.93#ibcon#read 5, iclass 39, count 0 2006.285.22:10:02.93#ibcon#about to read 6, iclass 39, count 0 2006.285.22:10:02.93#ibcon#read 6, iclass 39, count 0 2006.285.22:10:02.93#ibcon#end of sib2, iclass 39, count 0 2006.285.22:10:02.93#ibcon#*after write, iclass 39, count 0 2006.285.22:10:02.93#ibcon#*before return 0, iclass 39, count 0 2006.285.22:10:02.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:10:02.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:10:02.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:10:02.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:10:02.93$vck44/vb=3,4 2006.285.22:10:02.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.22:10:02.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.22:10:02.93#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:02.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:10:02.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:10:02.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:10:02.99#ibcon#enter wrdev, iclass 3, count 2 2006.285.22:10:02.99#ibcon#first serial, iclass 3, count 2 2006.285.22:10:02.99#ibcon#enter sib2, iclass 3, count 2 2006.285.22:10:02.99#ibcon#flushed, iclass 3, count 2 2006.285.22:10:02.99#ibcon#about to write, iclass 3, count 2 2006.285.22:10:02.99#ibcon#wrote, iclass 3, count 2 2006.285.22:10:02.99#ibcon#about to read 3, iclass 3, count 2 2006.285.22:10:03.01#ibcon#read 3, iclass 3, count 2 2006.285.22:10:03.01#ibcon#about to read 4, iclass 3, count 2 2006.285.22:10:03.01#ibcon#read 4, iclass 3, count 2 2006.285.22:10:03.01#ibcon#about to read 5, iclass 3, count 2 2006.285.22:10:03.01#ibcon#read 5, iclass 3, count 2 2006.285.22:10:03.01#ibcon#about to read 6, iclass 3, count 2 2006.285.22:10:03.01#ibcon#read 6, iclass 3, count 2 2006.285.22:10:03.01#ibcon#end of sib2, iclass 3, count 2 2006.285.22:10:03.01#ibcon#*mode == 0, iclass 3, count 2 2006.285.22:10:03.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.22:10:03.01#ibcon#[27=AT03-04\r\n] 2006.285.22:10:03.01#ibcon#*before write, iclass 3, count 2 2006.285.22:10:03.01#ibcon#enter sib2, iclass 3, count 2 2006.285.22:10:03.01#ibcon#flushed, iclass 3, count 2 2006.285.22:10:03.01#ibcon#about to write, iclass 3, count 2 2006.285.22:10:03.01#ibcon#wrote, iclass 3, count 2 2006.285.22:10:03.01#ibcon#about to read 3, iclass 3, count 2 2006.285.22:10:03.04#ibcon#read 3, iclass 3, count 2 2006.285.22:10:03.04#ibcon#about to read 4, iclass 3, count 2 2006.285.22:10:03.04#ibcon#read 4, iclass 3, count 2 2006.285.22:10:03.04#ibcon#about to read 5, iclass 3, count 2 2006.285.22:10:03.04#ibcon#read 5, iclass 3, count 2 2006.285.22:10:03.04#ibcon#about to read 6, iclass 3, count 2 2006.285.22:10:03.04#ibcon#read 6, iclass 3, count 2 2006.285.22:10:03.04#ibcon#end of sib2, iclass 3, count 2 2006.285.22:10:03.04#ibcon#*after write, iclass 3, count 2 2006.285.22:10:03.04#ibcon#*before return 0, iclass 3, count 2 2006.285.22:10:03.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:10:03.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:10:03.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.22:10:03.04#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:03.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:10:03.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:10:03.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:10:03.16#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:10:03.16#ibcon#first serial, iclass 3, count 0 2006.285.22:10:03.16#ibcon#enter sib2, iclass 3, count 0 2006.285.22:10:03.16#ibcon#flushed, iclass 3, count 0 2006.285.22:10:03.16#ibcon#about to write, iclass 3, count 0 2006.285.22:10:03.16#ibcon#wrote, iclass 3, count 0 2006.285.22:10:03.16#ibcon#about to read 3, iclass 3, count 0 2006.285.22:10:03.18#ibcon#read 3, iclass 3, count 0 2006.285.22:10:03.18#ibcon#about to read 4, iclass 3, count 0 2006.285.22:10:03.18#ibcon#read 4, iclass 3, count 0 2006.285.22:10:03.18#ibcon#about to read 5, iclass 3, count 0 2006.285.22:10:03.18#ibcon#read 5, iclass 3, count 0 2006.285.22:10:03.18#ibcon#about to read 6, iclass 3, count 0 2006.285.22:10:03.18#ibcon#read 6, iclass 3, count 0 2006.285.22:10:03.18#ibcon#end of sib2, iclass 3, count 0 2006.285.22:10:03.18#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:10:03.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:10:03.18#ibcon#[27=USB\r\n] 2006.285.22:10:03.18#ibcon#*before write, iclass 3, count 0 2006.285.22:10:03.18#ibcon#enter sib2, iclass 3, count 0 2006.285.22:10:03.18#ibcon#flushed, iclass 3, count 0 2006.285.22:10:03.18#ibcon#about to write, iclass 3, count 0 2006.285.22:10:03.18#ibcon#wrote, iclass 3, count 0 2006.285.22:10:03.18#ibcon#about to read 3, iclass 3, count 0 2006.285.22:10:03.21#ibcon#read 3, iclass 3, count 0 2006.285.22:10:03.21#ibcon#about to read 4, iclass 3, count 0 2006.285.22:10:03.21#ibcon#read 4, iclass 3, count 0 2006.285.22:10:03.21#ibcon#about to read 5, iclass 3, count 0 2006.285.22:10:03.21#ibcon#read 5, iclass 3, count 0 2006.285.22:10:03.21#ibcon#about to read 6, iclass 3, count 0 2006.285.22:10:03.21#ibcon#read 6, iclass 3, count 0 2006.285.22:10:03.21#ibcon#end of sib2, iclass 3, count 0 2006.285.22:10:03.21#ibcon#*after write, iclass 3, count 0 2006.285.22:10:03.21#ibcon#*before return 0, iclass 3, count 0 2006.285.22:10:03.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:10:03.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:10:03.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:10:03.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:10:03.21$vck44/vblo=4,679.99 2006.285.22:10:03.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.22:10:03.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.22:10:03.21#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:03.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:10:03.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:10:03.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:10:03.21#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:10:03.21#ibcon#first serial, iclass 5, count 0 2006.285.22:10:03.21#ibcon#enter sib2, iclass 5, count 0 2006.285.22:10:03.21#ibcon#flushed, iclass 5, count 0 2006.285.22:10:03.21#ibcon#about to write, iclass 5, count 0 2006.285.22:10:03.21#ibcon#wrote, iclass 5, count 0 2006.285.22:10:03.21#ibcon#about to read 3, iclass 5, count 0 2006.285.22:10:03.23#ibcon#read 3, iclass 5, count 0 2006.285.22:10:03.23#ibcon#about to read 4, iclass 5, count 0 2006.285.22:10:03.23#ibcon#read 4, iclass 5, count 0 2006.285.22:10:03.23#ibcon#about to read 5, iclass 5, count 0 2006.285.22:10:03.23#ibcon#read 5, iclass 5, count 0 2006.285.22:10:03.23#ibcon#about to read 6, iclass 5, count 0 2006.285.22:10:03.23#ibcon#read 6, iclass 5, count 0 2006.285.22:10:03.23#ibcon#end of sib2, iclass 5, count 0 2006.285.22:10:03.23#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:10:03.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:10:03.23#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.22:10:03.23#ibcon#*before write, iclass 5, count 0 2006.285.22:10:03.23#ibcon#enter sib2, iclass 5, count 0 2006.285.22:10:03.23#ibcon#flushed, iclass 5, count 0 2006.285.22:10:03.23#ibcon#about to write, iclass 5, count 0 2006.285.22:10:03.23#ibcon#wrote, iclass 5, count 0 2006.285.22:10:03.23#ibcon#about to read 3, iclass 5, count 0 2006.285.22:10:03.27#ibcon#read 3, iclass 5, count 0 2006.285.22:10:03.27#ibcon#about to read 4, iclass 5, count 0 2006.285.22:10:03.27#ibcon#read 4, iclass 5, count 0 2006.285.22:10:03.27#ibcon#about to read 5, iclass 5, count 0 2006.285.22:10:03.27#ibcon#read 5, iclass 5, count 0 2006.285.22:10:03.27#ibcon#about to read 6, iclass 5, count 0 2006.285.22:10:03.27#ibcon#read 6, iclass 5, count 0 2006.285.22:10:03.27#ibcon#end of sib2, iclass 5, count 0 2006.285.22:10:03.27#ibcon#*after write, iclass 5, count 0 2006.285.22:10:03.27#ibcon#*before return 0, iclass 5, count 0 2006.285.22:10:03.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:10:03.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:10:03.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:10:03.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:10:03.27$vck44/vb=4,5 2006.285.22:10:03.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.22:10:03.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.22:10:03.27#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:03.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:10:03.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:10:03.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:10:03.33#ibcon#enter wrdev, iclass 7, count 2 2006.285.22:10:03.33#ibcon#first serial, iclass 7, count 2 2006.285.22:10:03.33#ibcon#enter sib2, iclass 7, count 2 2006.285.22:10:03.33#ibcon#flushed, iclass 7, count 2 2006.285.22:10:03.33#ibcon#about to write, iclass 7, count 2 2006.285.22:10:03.33#ibcon#wrote, iclass 7, count 2 2006.285.22:10:03.33#ibcon#about to read 3, iclass 7, count 2 2006.285.22:10:03.35#ibcon#read 3, iclass 7, count 2 2006.285.22:10:03.35#ibcon#about to read 4, iclass 7, count 2 2006.285.22:10:03.35#ibcon#read 4, iclass 7, count 2 2006.285.22:10:03.35#ibcon#about to read 5, iclass 7, count 2 2006.285.22:10:03.35#ibcon#read 5, iclass 7, count 2 2006.285.22:10:03.35#ibcon#about to read 6, iclass 7, count 2 2006.285.22:10:03.35#ibcon#read 6, iclass 7, count 2 2006.285.22:10:03.35#ibcon#end of sib2, iclass 7, count 2 2006.285.22:10:03.35#ibcon#*mode == 0, iclass 7, count 2 2006.285.22:10:03.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.22:10:03.35#ibcon#[27=AT04-05\r\n] 2006.285.22:10:03.35#ibcon#*before write, iclass 7, count 2 2006.285.22:10:03.35#ibcon#enter sib2, iclass 7, count 2 2006.285.22:10:03.35#ibcon#flushed, iclass 7, count 2 2006.285.22:10:03.35#ibcon#about to write, iclass 7, count 2 2006.285.22:10:03.35#ibcon#wrote, iclass 7, count 2 2006.285.22:10:03.35#ibcon#about to read 3, iclass 7, count 2 2006.285.22:10:03.38#ibcon#read 3, iclass 7, count 2 2006.285.22:10:03.38#ibcon#about to read 4, iclass 7, count 2 2006.285.22:10:03.38#ibcon#read 4, iclass 7, count 2 2006.285.22:10:03.38#ibcon#about to read 5, iclass 7, count 2 2006.285.22:10:03.38#ibcon#read 5, iclass 7, count 2 2006.285.22:10:03.38#ibcon#about to read 6, iclass 7, count 2 2006.285.22:10:03.38#ibcon#read 6, iclass 7, count 2 2006.285.22:10:03.38#ibcon#end of sib2, iclass 7, count 2 2006.285.22:10:03.38#ibcon#*after write, iclass 7, count 2 2006.285.22:10:03.38#ibcon#*before return 0, iclass 7, count 2 2006.285.22:10:03.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:10:03.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:10:03.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.22:10:03.38#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:03.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:10:03.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:10:03.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:10:03.50#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:10:03.50#ibcon#first serial, iclass 7, count 0 2006.285.22:10:03.50#ibcon#enter sib2, iclass 7, count 0 2006.285.22:10:03.50#ibcon#flushed, iclass 7, count 0 2006.285.22:10:03.50#ibcon#about to write, iclass 7, count 0 2006.285.22:10:03.50#ibcon#wrote, iclass 7, count 0 2006.285.22:10:03.50#ibcon#about to read 3, iclass 7, count 0 2006.285.22:10:03.52#ibcon#read 3, iclass 7, count 0 2006.285.22:10:03.52#ibcon#about to read 4, iclass 7, count 0 2006.285.22:10:03.52#ibcon#read 4, iclass 7, count 0 2006.285.22:10:03.52#ibcon#about to read 5, iclass 7, count 0 2006.285.22:10:03.52#ibcon#read 5, iclass 7, count 0 2006.285.22:10:03.52#ibcon#about to read 6, iclass 7, count 0 2006.285.22:10:03.52#ibcon#read 6, iclass 7, count 0 2006.285.22:10:03.52#ibcon#end of sib2, iclass 7, count 0 2006.285.22:10:03.52#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:10:03.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:10:03.52#ibcon#[27=USB\r\n] 2006.285.22:10:03.52#ibcon#*before write, iclass 7, count 0 2006.285.22:10:03.52#ibcon#enter sib2, iclass 7, count 0 2006.285.22:10:03.52#ibcon#flushed, iclass 7, count 0 2006.285.22:10:03.52#ibcon#about to write, iclass 7, count 0 2006.285.22:10:03.52#ibcon#wrote, iclass 7, count 0 2006.285.22:10:03.52#ibcon#about to read 3, iclass 7, count 0 2006.285.22:10:03.55#ibcon#read 3, iclass 7, count 0 2006.285.22:10:03.55#ibcon#about to read 4, iclass 7, count 0 2006.285.22:10:03.55#ibcon#read 4, iclass 7, count 0 2006.285.22:10:03.55#ibcon#about to read 5, iclass 7, count 0 2006.285.22:10:03.55#ibcon#read 5, iclass 7, count 0 2006.285.22:10:03.55#ibcon#about to read 6, iclass 7, count 0 2006.285.22:10:03.55#ibcon#read 6, iclass 7, count 0 2006.285.22:10:03.55#ibcon#end of sib2, iclass 7, count 0 2006.285.22:10:03.55#ibcon#*after write, iclass 7, count 0 2006.285.22:10:03.55#ibcon#*before return 0, iclass 7, count 0 2006.285.22:10:03.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:10:03.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:10:03.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:10:03.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:10:03.55$vck44/vblo=5,709.99 2006.285.22:10:03.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.22:10:03.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.22:10:03.55#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:03.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:10:03.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:10:03.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:10:03.55#ibcon#enter wrdev, iclass 11, count 0 2006.285.22:10:03.55#ibcon#first serial, iclass 11, count 0 2006.285.22:10:03.55#ibcon#enter sib2, iclass 11, count 0 2006.285.22:10:03.55#ibcon#flushed, iclass 11, count 0 2006.285.22:10:03.55#ibcon#about to write, iclass 11, count 0 2006.285.22:10:03.55#ibcon#wrote, iclass 11, count 0 2006.285.22:10:03.90#ibcon#about to read 3, iclass 11, count 0 2006.285.22:10:03.90#ibcon#read 3, iclass 11, count 0 2006.285.22:10:03.90#ibcon#about to read 4, iclass 11, count 0 2006.285.22:10:03.90#ibcon#read 4, iclass 11, count 0 2006.285.22:10:03.90#ibcon#about to read 5, iclass 11, count 0 2006.285.22:10:03.90#ibcon#read 5, iclass 11, count 0 2006.285.22:10:03.90#ibcon#about to read 6, iclass 11, count 0 2006.285.22:10:03.90#ibcon#read 6, iclass 11, count 0 2006.285.22:10:03.90#ibcon#end of sib2, iclass 11, count 0 2006.285.22:10:03.90#ibcon#*mode == 0, iclass 11, count 0 2006.285.22:10:03.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.22:10:03.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.22:10:03.90#ibcon#*before write, iclass 11, count 0 2006.285.22:10:03.90#ibcon#enter sib2, iclass 11, count 0 2006.285.22:10:03.90#ibcon#flushed, iclass 11, count 0 2006.285.22:10:03.90#ibcon#about to write, iclass 11, count 0 2006.285.22:10:03.90#ibcon#wrote, iclass 11, count 0 2006.285.22:10:03.90#ibcon#about to read 3, iclass 11, count 0 2006.285.22:10:03.94#ibcon#read 3, iclass 11, count 0 2006.285.22:10:03.94#ibcon#about to read 4, iclass 11, count 0 2006.285.22:10:03.94#ibcon#read 4, iclass 11, count 0 2006.285.22:10:03.94#ibcon#about to read 5, iclass 11, count 0 2006.285.22:10:03.94#ibcon#read 5, iclass 11, count 0 2006.285.22:10:03.94#ibcon#about to read 6, iclass 11, count 0 2006.285.22:10:03.94#ibcon#read 6, iclass 11, count 0 2006.285.22:10:03.94#ibcon#end of sib2, iclass 11, count 0 2006.285.22:10:03.94#ibcon#*after write, iclass 11, count 0 2006.285.22:10:03.94#ibcon#*before return 0, iclass 11, count 0 2006.285.22:10:03.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:10:03.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:10:03.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.22:10:03.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.22:10:03.94$vck44/vb=5,4 2006.285.22:10:03.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.22:10:03.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.22:10:03.94#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:03.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:10:03.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:10:03.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:10:03.94#ibcon#enter wrdev, iclass 13, count 2 2006.285.22:10:03.94#ibcon#first serial, iclass 13, count 2 2006.285.22:10:03.94#ibcon#enter sib2, iclass 13, count 2 2006.285.22:10:03.94#ibcon#flushed, iclass 13, count 2 2006.285.22:10:03.94#ibcon#about to write, iclass 13, count 2 2006.285.22:10:03.94#ibcon#wrote, iclass 13, count 2 2006.285.22:10:03.94#ibcon#about to read 3, iclass 13, count 2 2006.285.22:10:03.96#ibcon#read 3, iclass 13, count 2 2006.285.22:10:03.96#ibcon#about to read 4, iclass 13, count 2 2006.285.22:10:03.96#ibcon#read 4, iclass 13, count 2 2006.285.22:10:03.96#ibcon#about to read 5, iclass 13, count 2 2006.285.22:10:03.96#ibcon#read 5, iclass 13, count 2 2006.285.22:10:03.96#ibcon#about to read 6, iclass 13, count 2 2006.285.22:10:03.96#ibcon#read 6, iclass 13, count 2 2006.285.22:10:03.96#ibcon#end of sib2, iclass 13, count 2 2006.285.22:10:03.96#ibcon#*mode == 0, iclass 13, count 2 2006.285.22:10:03.96#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.22:10:03.96#ibcon#[27=AT05-04\r\n] 2006.285.22:10:03.96#ibcon#*before write, iclass 13, count 2 2006.285.22:10:03.96#ibcon#enter sib2, iclass 13, count 2 2006.285.22:10:03.96#ibcon#flushed, iclass 13, count 2 2006.285.22:10:03.96#ibcon#about to write, iclass 13, count 2 2006.285.22:10:03.96#ibcon#wrote, iclass 13, count 2 2006.285.22:10:03.96#ibcon#about to read 3, iclass 13, count 2 2006.285.22:10:03.99#ibcon#read 3, iclass 13, count 2 2006.285.22:10:03.99#ibcon#about to read 4, iclass 13, count 2 2006.285.22:10:03.99#ibcon#read 4, iclass 13, count 2 2006.285.22:10:03.99#ibcon#about to read 5, iclass 13, count 2 2006.285.22:10:03.99#ibcon#read 5, iclass 13, count 2 2006.285.22:10:03.99#ibcon#about to read 6, iclass 13, count 2 2006.285.22:10:03.99#ibcon#read 6, iclass 13, count 2 2006.285.22:10:03.99#ibcon#end of sib2, iclass 13, count 2 2006.285.22:10:03.99#ibcon#*after write, iclass 13, count 2 2006.285.22:10:03.99#ibcon#*before return 0, iclass 13, count 2 2006.285.22:10:03.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:10:03.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:10:03.99#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.22:10:03.99#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:03.99#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:10:04.03#abcon#<5=/14 0.6 1.3 16.021001016.1\r\n> 2006.285.22:10:04.05#abcon#{5=INTERFACE CLEAR} 2006.285.22:10:04.11#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:10:04.11#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:10:04.11#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:10:04.11#ibcon#enter wrdev, iclass 13, count 0 2006.285.22:10:04.11#ibcon#first serial, iclass 13, count 0 2006.285.22:10:04.11#ibcon#enter sib2, iclass 13, count 0 2006.285.22:10:04.11#ibcon#flushed, iclass 13, count 0 2006.285.22:10:04.11#ibcon#about to write, iclass 13, count 0 2006.285.22:10:04.11#ibcon#wrote, iclass 13, count 0 2006.285.22:10:04.11#ibcon#about to read 3, iclass 13, count 0 2006.285.22:10:04.13#ibcon#read 3, iclass 13, count 0 2006.285.22:10:04.13#ibcon#about to read 4, iclass 13, count 0 2006.285.22:10:04.13#ibcon#read 4, iclass 13, count 0 2006.285.22:10:04.13#ibcon#about to read 5, iclass 13, count 0 2006.285.22:10:04.13#ibcon#read 5, iclass 13, count 0 2006.285.22:10:04.13#ibcon#about to read 6, iclass 13, count 0 2006.285.22:10:04.13#ibcon#read 6, iclass 13, count 0 2006.285.22:10:04.13#ibcon#end of sib2, iclass 13, count 0 2006.285.22:10:04.13#ibcon#*mode == 0, iclass 13, count 0 2006.285.22:10:04.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.22:10:04.13#ibcon#[27=USB\r\n] 2006.285.22:10:04.13#ibcon#*before write, iclass 13, count 0 2006.285.22:10:04.13#ibcon#enter sib2, iclass 13, count 0 2006.285.22:10:04.13#ibcon#flushed, iclass 13, count 0 2006.285.22:10:04.13#ibcon#about to write, iclass 13, count 0 2006.285.22:10:04.13#ibcon#wrote, iclass 13, count 0 2006.285.22:10:04.13#ibcon#about to read 3, iclass 13, count 0 2006.285.22:10:04.16#ibcon#read 3, iclass 13, count 0 2006.285.22:10:04.16#ibcon#about to read 4, iclass 13, count 0 2006.285.22:10:04.16#ibcon#read 4, iclass 13, count 0 2006.285.22:10:04.16#ibcon#about to read 5, iclass 13, count 0 2006.285.22:10:04.16#ibcon#read 5, iclass 13, count 0 2006.285.22:10:04.16#ibcon#about to read 6, iclass 13, count 0 2006.285.22:10:04.16#ibcon#read 6, iclass 13, count 0 2006.285.22:10:04.16#ibcon#end of sib2, iclass 13, count 0 2006.285.22:10:04.16#ibcon#*after write, iclass 13, count 0 2006.285.22:10:04.16#ibcon#*before return 0, iclass 13, count 0 2006.285.22:10:04.16#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:10:04.16#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:10:04.16#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.22:10:04.16#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.22:10:04.16$vck44/vblo=6,719.99 2006.285.22:10:04.16#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.22:10:04.16#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.22:10:04.16#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:04.16#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:10:04.16#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:10:04.16#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:10:04.16#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:10:04.16#ibcon#first serial, iclass 19, count 0 2006.285.22:10:04.16#ibcon#enter sib2, iclass 19, count 0 2006.285.22:10:04.16#ibcon#flushed, iclass 19, count 0 2006.285.22:10:04.16#ibcon#about to write, iclass 19, count 0 2006.285.22:10:04.16#ibcon#wrote, iclass 19, count 0 2006.285.22:10:04.16#ibcon#about to read 3, iclass 19, count 0 2006.285.22:10:04.18#ibcon#read 3, iclass 19, count 0 2006.285.22:10:04.18#ibcon#about to read 4, iclass 19, count 0 2006.285.22:10:04.18#ibcon#read 4, iclass 19, count 0 2006.285.22:10:04.18#ibcon#about to read 5, iclass 19, count 0 2006.285.22:10:04.18#ibcon#read 5, iclass 19, count 0 2006.285.22:10:04.18#ibcon#about to read 6, iclass 19, count 0 2006.285.22:10:04.18#ibcon#read 6, iclass 19, count 0 2006.285.22:10:04.18#ibcon#end of sib2, iclass 19, count 0 2006.285.22:10:04.18#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:10:04.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:10:04.18#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.22:10:04.18#ibcon#*before write, iclass 19, count 0 2006.285.22:10:04.18#ibcon#enter sib2, iclass 19, count 0 2006.285.22:10:04.18#ibcon#flushed, iclass 19, count 0 2006.285.22:10:04.18#ibcon#about to write, iclass 19, count 0 2006.285.22:10:04.18#ibcon#wrote, iclass 19, count 0 2006.285.22:10:04.18#ibcon#about to read 3, iclass 19, count 0 2006.285.22:10:04.22#ibcon#read 3, iclass 19, count 0 2006.285.22:10:04.22#ibcon#about to read 4, iclass 19, count 0 2006.285.22:10:04.22#ibcon#read 4, iclass 19, count 0 2006.285.22:10:04.22#ibcon#about to read 5, iclass 19, count 0 2006.285.22:10:04.22#ibcon#read 5, iclass 19, count 0 2006.285.22:10:04.22#ibcon#about to read 6, iclass 19, count 0 2006.285.22:10:04.22#ibcon#read 6, iclass 19, count 0 2006.285.22:10:04.22#ibcon#end of sib2, iclass 19, count 0 2006.285.22:10:04.22#ibcon#*after write, iclass 19, count 0 2006.285.22:10:04.22#ibcon#*before return 0, iclass 19, count 0 2006.285.22:10:04.22#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:10:04.22#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:10:04.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:10:04.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:10:04.22$vck44/vb=6,3 2006.285.22:10:04.22#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.22:10:04.22#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.22:10:04.22#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:04.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:10:04.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:10:04.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:10:04.28#ibcon#enter wrdev, iclass 21, count 2 2006.285.22:10:04.28#ibcon#first serial, iclass 21, count 2 2006.285.22:10:04.28#ibcon#enter sib2, iclass 21, count 2 2006.285.22:10:04.28#ibcon#flushed, iclass 21, count 2 2006.285.22:10:04.28#ibcon#about to write, iclass 21, count 2 2006.285.22:10:04.28#ibcon#wrote, iclass 21, count 2 2006.285.22:10:04.28#ibcon#about to read 3, iclass 21, count 2 2006.285.22:10:04.30#ibcon#read 3, iclass 21, count 2 2006.285.22:10:04.30#ibcon#about to read 4, iclass 21, count 2 2006.285.22:10:04.30#ibcon#read 4, iclass 21, count 2 2006.285.22:10:04.30#ibcon#about to read 5, iclass 21, count 2 2006.285.22:10:04.30#ibcon#read 5, iclass 21, count 2 2006.285.22:10:04.30#ibcon#about to read 6, iclass 21, count 2 2006.285.22:10:04.30#ibcon#read 6, iclass 21, count 2 2006.285.22:10:04.30#ibcon#end of sib2, iclass 21, count 2 2006.285.22:10:04.30#ibcon#*mode == 0, iclass 21, count 2 2006.285.22:10:04.30#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.22:10:04.30#ibcon#[27=AT06-03\r\n] 2006.285.22:10:04.30#ibcon#*before write, iclass 21, count 2 2006.285.22:10:04.30#ibcon#enter sib2, iclass 21, count 2 2006.285.22:10:04.30#ibcon#flushed, iclass 21, count 2 2006.285.22:10:04.30#ibcon#about to write, iclass 21, count 2 2006.285.22:10:04.30#ibcon#wrote, iclass 21, count 2 2006.285.22:10:04.30#ibcon#about to read 3, iclass 21, count 2 2006.285.22:10:04.33#ibcon#read 3, iclass 21, count 2 2006.285.22:10:04.33#ibcon#about to read 4, iclass 21, count 2 2006.285.22:10:04.33#ibcon#read 4, iclass 21, count 2 2006.285.22:10:04.33#ibcon#about to read 5, iclass 21, count 2 2006.285.22:10:04.33#ibcon#read 5, iclass 21, count 2 2006.285.22:10:04.33#ibcon#about to read 6, iclass 21, count 2 2006.285.22:10:04.33#ibcon#read 6, iclass 21, count 2 2006.285.22:10:04.33#ibcon#end of sib2, iclass 21, count 2 2006.285.22:10:04.33#ibcon#*after write, iclass 21, count 2 2006.285.22:10:04.33#ibcon#*before return 0, iclass 21, count 2 2006.285.22:10:04.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:10:04.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:10:04.33#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.22:10:04.33#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:04.33#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:10:04.45#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:10:04.45#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:10:04.45#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:10:04.45#ibcon#first serial, iclass 21, count 0 2006.285.22:10:04.45#ibcon#enter sib2, iclass 21, count 0 2006.285.22:10:04.45#ibcon#flushed, iclass 21, count 0 2006.285.22:10:04.45#ibcon#about to write, iclass 21, count 0 2006.285.22:10:04.45#ibcon#wrote, iclass 21, count 0 2006.285.22:10:04.45#ibcon#about to read 3, iclass 21, count 0 2006.285.22:10:04.47#ibcon#read 3, iclass 21, count 0 2006.285.22:10:04.47#ibcon#about to read 4, iclass 21, count 0 2006.285.22:10:04.47#ibcon#read 4, iclass 21, count 0 2006.285.22:10:04.47#ibcon#about to read 5, iclass 21, count 0 2006.285.22:10:04.47#ibcon#read 5, iclass 21, count 0 2006.285.22:10:04.47#ibcon#about to read 6, iclass 21, count 0 2006.285.22:10:04.47#ibcon#read 6, iclass 21, count 0 2006.285.22:10:04.47#ibcon#end of sib2, iclass 21, count 0 2006.285.22:10:04.47#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:10:04.47#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:10:04.47#ibcon#[27=USB\r\n] 2006.285.22:10:04.47#ibcon#*before write, iclass 21, count 0 2006.285.22:10:04.47#ibcon#enter sib2, iclass 21, count 0 2006.285.22:10:04.47#ibcon#flushed, iclass 21, count 0 2006.285.22:10:04.47#ibcon#about to write, iclass 21, count 0 2006.285.22:10:04.47#ibcon#wrote, iclass 21, count 0 2006.285.22:10:04.47#ibcon#about to read 3, iclass 21, count 0 2006.285.22:10:04.50#ibcon#read 3, iclass 21, count 0 2006.285.22:10:04.50#ibcon#about to read 4, iclass 21, count 0 2006.285.22:10:04.50#ibcon#read 4, iclass 21, count 0 2006.285.22:10:04.50#ibcon#about to read 5, iclass 21, count 0 2006.285.22:10:04.50#ibcon#read 5, iclass 21, count 0 2006.285.22:10:04.50#ibcon#about to read 6, iclass 21, count 0 2006.285.22:10:04.50#ibcon#read 6, iclass 21, count 0 2006.285.22:10:04.50#ibcon#end of sib2, iclass 21, count 0 2006.285.22:10:04.50#ibcon#*after write, iclass 21, count 0 2006.285.22:10:04.50#ibcon#*before return 0, iclass 21, count 0 2006.285.22:10:04.50#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:10:04.50#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:10:04.50#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:10:04.50#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:10:04.50$vck44/vblo=7,734.99 2006.285.22:10:04.50#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.22:10:04.50#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.22:10:04.50#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:04.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:10:04.50#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:10:04.50#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:10:04.50#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:10:04.50#ibcon#first serial, iclass 23, count 0 2006.285.22:10:04.50#ibcon#enter sib2, iclass 23, count 0 2006.285.22:10:04.50#ibcon#flushed, iclass 23, count 0 2006.285.22:10:04.50#ibcon#about to write, iclass 23, count 0 2006.285.22:10:04.50#ibcon#wrote, iclass 23, count 0 2006.285.22:10:04.50#ibcon#about to read 3, iclass 23, count 0 2006.285.22:10:04.52#ibcon#read 3, iclass 23, count 0 2006.285.22:10:04.72#ibcon#about to read 4, iclass 23, count 0 2006.285.22:10:04.72#ibcon#read 4, iclass 23, count 0 2006.285.22:10:04.72#ibcon#about to read 5, iclass 23, count 0 2006.285.22:10:04.72#ibcon#read 5, iclass 23, count 0 2006.285.22:10:04.72#ibcon#about to read 6, iclass 23, count 0 2006.285.22:10:04.72#ibcon#read 6, iclass 23, count 0 2006.285.22:10:04.72#ibcon#end of sib2, iclass 23, count 0 2006.285.22:10:04.72#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:10:04.72#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:10:04.72#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.22:10:04.72#ibcon#*before write, iclass 23, count 0 2006.285.22:10:04.72#ibcon#enter sib2, iclass 23, count 0 2006.285.22:10:04.72#ibcon#flushed, iclass 23, count 0 2006.285.22:10:04.72#ibcon#about to write, iclass 23, count 0 2006.285.22:10:04.72#ibcon#wrote, iclass 23, count 0 2006.285.22:10:04.72#ibcon#about to read 3, iclass 23, count 0 2006.285.22:10:04.76#ibcon#read 3, iclass 23, count 0 2006.285.22:10:04.76#ibcon#about to read 4, iclass 23, count 0 2006.285.22:10:04.76#ibcon#read 4, iclass 23, count 0 2006.285.22:10:04.76#ibcon#about to read 5, iclass 23, count 0 2006.285.22:10:04.76#ibcon#read 5, iclass 23, count 0 2006.285.22:10:04.76#ibcon#about to read 6, iclass 23, count 0 2006.285.22:10:04.76#ibcon#read 6, iclass 23, count 0 2006.285.22:10:04.76#ibcon#end of sib2, iclass 23, count 0 2006.285.22:10:04.76#ibcon#*after write, iclass 23, count 0 2006.285.22:10:04.76#ibcon#*before return 0, iclass 23, count 0 2006.285.22:10:04.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:10:04.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:10:04.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:10:04.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:10:04.76$vck44/vb=7,4 2006.285.22:10:04.76#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.22:10:04.76#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.22:10:04.76#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:04.76#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:10:04.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:10:04.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:10:04.76#ibcon#enter wrdev, iclass 25, count 2 2006.285.22:10:04.76#ibcon#first serial, iclass 25, count 2 2006.285.22:10:04.76#ibcon#enter sib2, iclass 25, count 2 2006.285.22:10:04.76#ibcon#flushed, iclass 25, count 2 2006.285.22:10:04.76#ibcon#about to write, iclass 25, count 2 2006.285.22:10:04.76#ibcon#wrote, iclass 25, count 2 2006.285.22:10:04.76#ibcon#about to read 3, iclass 25, count 2 2006.285.22:10:04.78#ibcon#read 3, iclass 25, count 2 2006.285.22:10:04.78#ibcon#about to read 4, iclass 25, count 2 2006.285.22:10:04.78#ibcon#read 4, iclass 25, count 2 2006.285.22:10:04.78#ibcon#about to read 5, iclass 25, count 2 2006.285.22:10:04.78#ibcon#read 5, iclass 25, count 2 2006.285.22:10:04.78#ibcon#about to read 6, iclass 25, count 2 2006.285.22:10:04.78#ibcon#read 6, iclass 25, count 2 2006.285.22:10:04.78#ibcon#end of sib2, iclass 25, count 2 2006.285.22:10:04.78#ibcon#*mode == 0, iclass 25, count 2 2006.285.22:10:04.78#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.22:10:04.78#ibcon#[27=AT07-04\r\n] 2006.285.22:10:04.78#ibcon#*before write, iclass 25, count 2 2006.285.22:10:04.78#ibcon#enter sib2, iclass 25, count 2 2006.285.22:10:04.78#ibcon#flushed, iclass 25, count 2 2006.285.22:10:04.78#ibcon#about to write, iclass 25, count 2 2006.285.22:10:04.78#ibcon#wrote, iclass 25, count 2 2006.285.22:10:04.78#ibcon#about to read 3, iclass 25, count 2 2006.285.22:10:04.81#ibcon#read 3, iclass 25, count 2 2006.285.22:10:04.81#ibcon#about to read 4, iclass 25, count 2 2006.285.22:10:04.81#ibcon#read 4, iclass 25, count 2 2006.285.22:10:04.81#ibcon#about to read 5, iclass 25, count 2 2006.285.22:10:04.81#ibcon#read 5, iclass 25, count 2 2006.285.22:10:04.81#ibcon#about to read 6, iclass 25, count 2 2006.285.22:10:04.81#ibcon#read 6, iclass 25, count 2 2006.285.22:10:04.81#ibcon#end of sib2, iclass 25, count 2 2006.285.22:10:04.81#ibcon#*after write, iclass 25, count 2 2006.285.22:10:04.81#ibcon#*before return 0, iclass 25, count 2 2006.285.22:10:04.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:10:04.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:10:04.81#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.22:10:04.81#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:04.81#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:10:04.93#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:10:04.93#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:10:04.93#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:10:04.93#ibcon#first serial, iclass 25, count 0 2006.285.22:10:04.93#ibcon#enter sib2, iclass 25, count 0 2006.285.22:10:04.93#ibcon#flushed, iclass 25, count 0 2006.285.22:10:04.93#ibcon#about to write, iclass 25, count 0 2006.285.22:10:04.93#ibcon#wrote, iclass 25, count 0 2006.285.22:10:04.93#ibcon#about to read 3, iclass 25, count 0 2006.285.22:10:04.95#ibcon#read 3, iclass 25, count 0 2006.285.22:10:04.95#ibcon#about to read 4, iclass 25, count 0 2006.285.22:10:04.95#ibcon#read 4, iclass 25, count 0 2006.285.22:10:04.95#ibcon#about to read 5, iclass 25, count 0 2006.285.22:10:04.95#ibcon#read 5, iclass 25, count 0 2006.285.22:10:04.95#ibcon#about to read 6, iclass 25, count 0 2006.285.22:10:04.95#ibcon#read 6, iclass 25, count 0 2006.285.22:10:04.95#ibcon#end of sib2, iclass 25, count 0 2006.285.22:10:04.95#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:10:04.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:10:04.95#ibcon#[27=USB\r\n] 2006.285.22:10:04.95#ibcon#*before write, iclass 25, count 0 2006.285.22:10:04.95#ibcon#enter sib2, iclass 25, count 0 2006.285.22:10:04.95#ibcon#flushed, iclass 25, count 0 2006.285.22:10:04.95#ibcon#about to write, iclass 25, count 0 2006.285.22:10:04.95#ibcon#wrote, iclass 25, count 0 2006.285.22:10:04.95#ibcon#about to read 3, iclass 25, count 0 2006.285.22:10:04.98#ibcon#read 3, iclass 25, count 0 2006.285.22:10:04.98#ibcon#about to read 4, iclass 25, count 0 2006.285.22:10:04.98#ibcon#read 4, iclass 25, count 0 2006.285.22:10:04.98#ibcon#about to read 5, iclass 25, count 0 2006.285.22:10:04.98#ibcon#read 5, iclass 25, count 0 2006.285.22:10:04.98#ibcon#about to read 6, iclass 25, count 0 2006.285.22:10:04.98#ibcon#read 6, iclass 25, count 0 2006.285.22:10:04.98#ibcon#end of sib2, iclass 25, count 0 2006.285.22:10:04.98#ibcon#*after write, iclass 25, count 0 2006.285.22:10:04.98#ibcon#*before return 0, iclass 25, count 0 2006.285.22:10:04.98#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:10:04.98#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:10:04.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:10:04.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:10:04.98$vck44/vblo=8,744.99 2006.285.22:10:04.98#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.22:10:04.98#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.22:10:04.98#ibcon#ireg 17 cls_cnt 0 2006.285.22:10:04.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:10:04.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:10:04.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:10:04.98#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:10:04.98#ibcon#first serial, iclass 27, count 0 2006.285.22:10:04.98#ibcon#enter sib2, iclass 27, count 0 2006.285.22:10:04.98#ibcon#flushed, iclass 27, count 0 2006.285.22:10:04.98#ibcon#about to write, iclass 27, count 0 2006.285.22:10:04.98#ibcon#wrote, iclass 27, count 0 2006.285.22:10:04.98#ibcon#about to read 3, iclass 27, count 0 2006.285.22:10:05.00#ibcon#read 3, iclass 27, count 0 2006.285.22:10:05.00#ibcon#about to read 4, iclass 27, count 0 2006.285.22:10:05.00#ibcon#read 4, iclass 27, count 0 2006.285.22:10:05.00#ibcon#about to read 5, iclass 27, count 0 2006.285.22:10:05.00#ibcon#read 5, iclass 27, count 0 2006.285.22:10:05.00#ibcon#about to read 6, iclass 27, count 0 2006.285.22:10:05.00#ibcon#read 6, iclass 27, count 0 2006.285.22:10:05.00#ibcon#end of sib2, iclass 27, count 0 2006.285.22:10:05.00#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:10:05.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:10:05.00#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.22:10:05.00#ibcon#*before write, iclass 27, count 0 2006.285.22:10:05.00#ibcon#enter sib2, iclass 27, count 0 2006.285.22:10:05.00#ibcon#flushed, iclass 27, count 0 2006.285.22:10:05.00#ibcon#about to write, iclass 27, count 0 2006.285.22:10:05.00#ibcon#wrote, iclass 27, count 0 2006.285.22:10:05.00#ibcon#about to read 3, iclass 27, count 0 2006.285.22:10:05.04#ibcon#read 3, iclass 27, count 0 2006.285.22:10:05.04#ibcon#about to read 4, iclass 27, count 0 2006.285.22:10:05.04#ibcon#read 4, iclass 27, count 0 2006.285.22:10:05.04#ibcon#about to read 5, iclass 27, count 0 2006.285.22:10:05.04#ibcon#read 5, iclass 27, count 0 2006.285.22:10:05.04#ibcon#about to read 6, iclass 27, count 0 2006.285.22:10:05.04#ibcon#read 6, iclass 27, count 0 2006.285.22:10:05.04#ibcon#end of sib2, iclass 27, count 0 2006.285.22:10:05.04#ibcon#*after write, iclass 27, count 0 2006.285.22:10:05.04#ibcon#*before return 0, iclass 27, count 0 2006.285.22:10:05.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:10:05.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:10:05.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:10:05.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:10:05.04$vck44/vb=8,4 2006.285.22:10:05.04#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.22:10:05.04#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.22:10:05.04#ibcon#ireg 11 cls_cnt 2 2006.285.22:10:05.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:10:05.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:10:05.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:10:05.10#ibcon#enter wrdev, iclass 29, count 2 2006.285.22:10:05.10#ibcon#first serial, iclass 29, count 2 2006.285.22:10:05.10#ibcon#enter sib2, iclass 29, count 2 2006.285.22:10:05.10#ibcon#flushed, iclass 29, count 2 2006.285.22:10:05.10#ibcon#about to write, iclass 29, count 2 2006.285.22:10:05.10#ibcon#wrote, iclass 29, count 2 2006.285.22:10:05.10#ibcon#about to read 3, iclass 29, count 2 2006.285.22:10:05.12#ibcon#read 3, iclass 29, count 2 2006.285.22:10:05.12#ibcon#about to read 4, iclass 29, count 2 2006.285.22:10:05.12#ibcon#read 4, iclass 29, count 2 2006.285.22:10:05.12#ibcon#about to read 5, iclass 29, count 2 2006.285.22:10:05.12#ibcon#read 5, iclass 29, count 2 2006.285.22:10:05.12#ibcon#about to read 6, iclass 29, count 2 2006.285.22:10:05.12#ibcon#read 6, iclass 29, count 2 2006.285.22:10:05.12#ibcon#end of sib2, iclass 29, count 2 2006.285.22:10:05.12#ibcon#*mode == 0, iclass 29, count 2 2006.285.22:10:05.12#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.22:10:05.12#ibcon#[27=AT08-04\r\n] 2006.285.22:10:05.12#ibcon#*before write, iclass 29, count 2 2006.285.22:10:05.12#ibcon#enter sib2, iclass 29, count 2 2006.285.22:10:05.12#ibcon#flushed, iclass 29, count 2 2006.285.22:10:05.12#ibcon#about to write, iclass 29, count 2 2006.285.22:10:05.12#ibcon#wrote, iclass 29, count 2 2006.285.22:10:05.12#ibcon#about to read 3, iclass 29, count 2 2006.285.22:10:05.15#ibcon#read 3, iclass 29, count 2 2006.285.22:10:05.15#ibcon#about to read 4, iclass 29, count 2 2006.285.22:10:05.15#ibcon#read 4, iclass 29, count 2 2006.285.22:10:05.15#ibcon#about to read 5, iclass 29, count 2 2006.285.22:10:05.15#ibcon#read 5, iclass 29, count 2 2006.285.22:10:05.15#ibcon#about to read 6, iclass 29, count 2 2006.285.22:10:05.15#ibcon#read 6, iclass 29, count 2 2006.285.22:10:05.15#ibcon#end of sib2, iclass 29, count 2 2006.285.22:10:05.15#ibcon#*after write, iclass 29, count 2 2006.285.22:10:05.15#ibcon#*before return 0, iclass 29, count 2 2006.285.22:10:05.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:10:05.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:10:05.15#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.22:10:05.15#ibcon#ireg 7 cls_cnt 0 2006.285.22:10:05.15#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:10:05.27#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:10:05.27#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:10:05.27#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:10:05.27#ibcon#first serial, iclass 29, count 0 2006.285.22:10:05.27#ibcon#enter sib2, iclass 29, count 0 2006.285.22:10:05.27#ibcon#flushed, iclass 29, count 0 2006.285.22:10:05.27#ibcon#about to write, iclass 29, count 0 2006.285.22:10:05.27#ibcon#wrote, iclass 29, count 0 2006.285.22:10:05.27#ibcon#about to read 3, iclass 29, count 0 2006.285.22:10:05.29#ibcon#read 3, iclass 29, count 0 2006.285.22:10:05.29#ibcon#about to read 4, iclass 29, count 0 2006.285.22:10:05.29#ibcon#read 4, iclass 29, count 0 2006.285.22:10:05.29#ibcon#about to read 5, iclass 29, count 0 2006.285.22:10:05.29#ibcon#read 5, iclass 29, count 0 2006.285.22:10:05.29#ibcon#about to read 6, iclass 29, count 0 2006.285.22:10:05.29#ibcon#read 6, iclass 29, count 0 2006.285.22:10:05.29#ibcon#end of sib2, iclass 29, count 0 2006.285.22:10:05.29#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:10:05.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:10:05.29#ibcon#[27=USB\r\n] 2006.285.22:10:05.29#ibcon#*before write, iclass 29, count 0 2006.285.22:10:05.29#ibcon#enter sib2, iclass 29, count 0 2006.285.22:10:05.29#ibcon#flushed, iclass 29, count 0 2006.285.22:10:05.29#ibcon#about to write, iclass 29, count 0 2006.285.22:10:05.29#ibcon#wrote, iclass 29, count 0 2006.285.22:10:05.29#ibcon#about to read 3, iclass 29, count 0 2006.285.22:10:05.32#ibcon#read 3, iclass 29, count 0 2006.285.22:10:05.32#ibcon#about to read 4, iclass 29, count 0 2006.285.22:10:05.32#ibcon#read 4, iclass 29, count 0 2006.285.22:10:05.32#ibcon#about to read 5, iclass 29, count 0 2006.285.22:10:05.32#ibcon#read 5, iclass 29, count 0 2006.285.22:10:05.32#ibcon#about to read 6, iclass 29, count 0 2006.285.22:10:05.32#ibcon#read 6, iclass 29, count 0 2006.285.22:10:05.32#ibcon#end of sib2, iclass 29, count 0 2006.285.22:10:05.32#ibcon#*after write, iclass 29, count 0 2006.285.22:10:05.32#ibcon#*before return 0, iclass 29, count 0 2006.285.22:10:05.32#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:10:05.32#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:10:05.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:10:05.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:10:05.32$vck44/vabw=wide 2006.285.22:10:05.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.22:10:05.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.22:10:05.32#ibcon#ireg 8 cls_cnt 0 2006.285.22:10:05.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:10:05.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:10:05.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:10:05.32#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:10:05.32#ibcon#first serial, iclass 31, count 0 2006.285.22:10:05.32#ibcon#enter sib2, iclass 31, count 0 2006.285.22:10:05.32#ibcon#flushed, iclass 31, count 0 2006.285.22:10:05.32#ibcon#about to write, iclass 31, count 0 2006.285.22:10:05.32#ibcon#wrote, iclass 31, count 0 2006.285.22:10:05.32#ibcon#about to read 3, iclass 31, count 0 2006.285.22:10:05.34#ibcon#read 3, iclass 31, count 0 2006.285.22:10:05.34#ibcon#about to read 4, iclass 31, count 0 2006.285.22:10:05.34#ibcon#read 4, iclass 31, count 0 2006.285.22:10:05.34#ibcon#about to read 5, iclass 31, count 0 2006.285.22:10:05.34#ibcon#read 5, iclass 31, count 0 2006.285.22:10:05.34#ibcon#about to read 6, iclass 31, count 0 2006.285.22:10:05.34#ibcon#read 6, iclass 31, count 0 2006.285.22:10:05.34#ibcon#end of sib2, iclass 31, count 0 2006.285.22:10:05.34#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:10:05.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:10:05.34#ibcon#[25=BW32\r\n] 2006.285.22:10:05.34#ibcon#*before write, iclass 31, count 0 2006.285.22:10:05.34#ibcon#enter sib2, iclass 31, count 0 2006.285.22:10:05.34#ibcon#flushed, iclass 31, count 0 2006.285.22:10:05.34#ibcon#about to write, iclass 31, count 0 2006.285.22:10:05.34#ibcon#wrote, iclass 31, count 0 2006.285.22:10:05.34#ibcon#about to read 3, iclass 31, count 0 2006.285.22:10:05.37#ibcon#read 3, iclass 31, count 0 2006.285.22:10:05.37#ibcon#about to read 4, iclass 31, count 0 2006.285.22:10:05.37#ibcon#read 4, iclass 31, count 0 2006.285.22:10:05.37#ibcon#about to read 5, iclass 31, count 0 2006.285.22:10:05.37#ibcon#read 5, iclass 31, count 0 2006.285.22:10:05.37#ibcon#about to read 6, iclass 31, count 0 2006.285.22:10:05.37#ibcon#read 6, iclass 31, count 0 2006.285.22:10:05.37#ibcon#end of sib2, iclass 31, count 0 2006.285.22:10:05.37#ibcon#*after write, iclass 31, count 0 2006.285.22:10:05.37#ibcon#*before return 0, iclass 31, count 0 2006.285.22:10:05.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:10:05.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:10:05.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:10:05.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:10:05.37$vck44/vbbw=wide 2006.285.22:10:05.37#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.22:10:05.37#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.22:10:05.37#ibcon#ireg 8 cls_cnt 0 2006.285.22:10:05.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:10:05.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:10:05.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:10:05.44#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:10:05.44#ibcon#first serial, iclass 33, count 0 2006.285.22:10:05.44#ibcon#enter sib2, iclass 33, count 0 2006.285.22:10:05.44#ibcon#flushed, iclass 33, count 0 2006.285.22:10:05.44#ibcon#about to write, iclass 33, count 0 2006.285.22:10:05.44#ibcon#wrote, iclass 33, count 0 2006.285.22:10:05.44#ibcon#about to read 3, iclass 33, count 0 2006.285.22:10:05.46#ibcon#read 3, iclass 33, count 0 2006.285.22:10:05.46#ibcon#about to read 4, iclass 33, count 0 2006.285.22:10:05.46#ibcon#read 4, iclass 33, count 0 2006.285.22:10:05.46#ibcon#about to read 5, iclass 33, count 0 2006.285.22:10:05.46#ibcon#read 5, iclass 33, count 0 2006.285.22:10:05.46#ibcon#about to read 6, iclass 33, count 0 2006.285.22:10:05.46#ibcon#read 6, iclass 33, count 0 2006.285.22:10:05.46#ibcon#end of sib2, iclass 33, count 0 2006.285.22:10:05.46#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:10:05.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:10:05.46#ibcon#[27=BW32\r\n] 2006.285.22:10:05.46#ibcon#*before write, iclass 33, count 0 2006.285.22:10:05.46#ibcon#enter sib2, iclass 33, count 0 2006.285.22:10:05.46#ibcon#flushed, iclass 33, count 0 2006.285.22:10:05.46#ibcon#about to write, iclass 33, count 0 2006.285.22:10:05.46#ibcon#wrote, iclass 33, count 0 2006.285.22:10:05.46#ibcon#about to read 3, iclass 33, count 0 2006.285.22:10:05.49#ibcon#read 3, iclass 33, count 0 2006.285.22:10:05.49#ibcon#about to read 4, iclass 33, count 0 2006.285.22:10:05.49#ibcon#read 4, iclass 33, count 0 2006.285.22:10:05.49#ibcon#about to read 5, iclass 33, count 0 2006.285.22:10:05.49#ibcon#read 5, iclass 33, count 0 2006.285.22:10:05.49#ibcon#about to read 6, iclass 33, count 0 2006.285.22:10:05.49#ibcon#read 6, iclass 33, count 0 2006.285.22:10:05.49#ibcon#end of sib2, iclass 33, count 0 2006.285.22:10:05.49#ibcon#*after write, iclass 33, count 0 2006.285.22:10:05.49#ibcon#*before return 0, iclass 33, count 0 2006.285.22:10:05.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:10:05.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:10:05.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:10:05.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:10:05.49$setupk4/ifdk4 2006.285.22:10:05.49$ifdk4/lo= 2006.285.22:10:05.49$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.22:10:05.49$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.22:10:05.49$ifdk4/patch= 2006.285.22:10:05.49$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.22:10:05.49$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.22:10:05.49$setupk4/!*+20s 2006.285.22:10:14.29#abcon#<5=/14 0.6 1.4 16.021001016.1\r\n> 2006.285.22:10:14.31#abcon#{5=INTERFACE CLEAR} 2006.285.22:10:14.37#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:10:18.14#trakl#Source acquired 2006.285.22:10:18.47$setupk4/"tpicd 2006.285.22:10:18.47$setupk4/echo=off 2006.285.22:10:18.47$setupk4/xlog=off 2006.285.22:10:18.47:!2006.285.22:10:51 2006.285.22:10:19.14#flagr#flagr/antenna,acquired 2006.285.22:10:51.00:preob 2006.285.22:10:51.14/onsource/TRACKING 2006.285.22:10:51.14:!2006.285.22:11:01 2006.285.22:11:01.00:"tape 2006.285.22:11:01.00:"st=record 2006.285.22:11:01.00:data_valid=on 2006.285.22:11:01.00:midob 2006.285.22:11:01.14/onsource/TRACKING 2006.285.22:11:01.14/wx/16.05,1016.1,100 2006.285.22:11:01.22/cable/+6.5104E-03 2006.285.22:11:02.31/va/01,07,usb,yes,42,46 2006.285.22:11:02.31/va/02,06,usb,yes,43,43 2006.285.22:11:02.31/va/03,07,usb,yes,42,44 2006.285.22:11:02.31/va/04,06,usb,yes,44,46 2006.285.22:11:02.31/va/05,03,usb,yes,43,44 2006.285.22:11:02.31/va/06,04,usb,yes,39,39 2006.285.22:11:02.31/va/07,04,usb,yes,40,41 2006.285.22:11:02.31/va/08,03,usb,yes,41,49 2006.285.22:11:02.54/valo/01,524.99,yes,locked 2006.285.22:11:02.54/valo/02,534.99,yes,locked 2006.285.22:11:02.54/valo/03,564.99,yes,locked 2006.285.22:11:02.54/valo/04,624.99,yes,locked 2006.285.22:11:02.54/valo/05,734.99,yes,locked 2006.285.22:11:02.54/valo/06,814.99,yes,locked 2006.285.22:11:02.54/valo/07,864.99,yes,locked 2006.285.22:11:02.54/valo/08,884.99,yes,locked 2006.285.22:11:03.63/vb/01,04,usb,yes,36,35 2006.285.22:11:03.63/vb/02,05,usb,yes,34,35 2006.285.22:11:03.63/vb/03,04,usb,yes,36,39 2006.285.22:11:03.63/vb/04,05,usb,yes,35,34 2006.285.22:11:03.63/vb/05,04,usb,yes,32,34 2006.285.22:11:03.63/vb/06,03,usb,yes,45,40 2006.285.22:11:03.63/vb/07,04,usb,yes,36,36 2006.285.22:11:03.63/vb/08,04,usb,yes,33,37 2006.285.22:11:03.87/vblo/01,629.99,yes,locked 2006.285.22:11:03.87/vblo/02,634.99,yes,locked 2006.285.22:11:03.87/vblo/03,649.99,yes,locked 2006.285.22:11:03.87/vblo/04,679.99,yes,locked 2006.285.22:11:03.87/vblo/05,709.99,yes,locked 2006.285.22:11:03.87/vblo/06,719.99,yes,locked 2006.285.22:11:03.87/vblo/07,734.99,yes,locked 2006.285.22:11:03.87/vblo/08,744.99,yes,locked 2006.285.22:11:04.02/vabw/8 2006.285.22:11:04.17/vbbw/8 2006.285.22:11:04.26/xfe/off,on,12.0 2006.285.22:11:04.63/ifatt/23,28,28,28 2006.285.22:11:05.07/fmout-gps/S +2.56E-07 2006.285.22:11:05.09:!2006.285.22:12:01 2006.285.22:12:01.00:data_valid=off 2006.285.22:12:01.00:"et 2006.285.22:12:01.00:!+3s 2006.285.22:12:04.01:"tape 2006.285.22:12:04.01:postob 2006.285.22:12:04.10/cable/+6.5095E-03 2006.285.22:12:04.10/wx/16.09,1016.1,100 2006.285.22:12:05.08/fmout-gps/S +2.57E-07 2006.285.22:12:05.08:scan_name=285-2214,jd0610,110 2006.285.22:12:05.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.285.22:12:05.14#flagr#flagr/antenna,new-source 2006.285.22:12:06.14:checkk5 2006.285.22:12:06.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:12:06.99/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:12:07.39/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:12:07.99/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:12:08.39/chk_obsdata//k5ts1/T2852211??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:12:08.83/chk_obsdata//k5ts2/T2852211??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:12:09.26/chk_obsdata//k5ts3/T2852211??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:12:09.63/chk_obsdata//k5ts4/T2852211??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:12:10.68/k5log//k5ts1_log_newline 2006.285.22:12:11.94/k5log//k5ts2_log_newline 2006.285.22:12:12.95/k5log//k5ts3_log_newline 2006.285.22:12:13.65/k5log//k5ts4_log_newline 2006.285.22:12:13.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:12:13.67:setupk4=1 2006.285.22:12:13.67$setupk4/echo=on 2006.285.22:12:13.67$setupk4/pcalon 2006.285.22:12:13.67$pcalon/"no phase cal control is implemented here 2006.285.22:12:13.67$setupk4/"tpicd=stop 2006.285.22:12:13.67$setupk4/"rec=synch_on 2006.285.22:12:13.67$setupk4/"rec_mode=128 2006.285.22:12:13.67$setupk4/!* 2006.285.22:12:13.67$setupk4/recpk4 2006.285.22:12:13.67$recpk4/recpatch= 2006.285.22:12:13.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:12:13.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:12:13.68$setupk4/vck44 2006.285.22:12:13.68$vck44/valo=1,524.99 2006.285.22:12:13.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.22:12:13.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.22:12:13.68#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:13.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:12:13.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:12:13.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:12:13.68#ibcon#enter wrdev, iclass 14, count 0 2006.285.22:12:13.68#ibcon#first serial, iclass 14, count 0 2006.285.22:12:13.68#ibcon#enter sib2, iclass 14, count 0 2006.285.22:12:13.68#ibcon#flushed, iclass 14, count 0 2006.285.22:12:13.68#ibcon#about to write, iclass 14, count 0 2006.285.22:12:13.68#ibcon#wrote, iclass 14, count 0 2006.285.22:12:13.68#ibcon#about to read 3, iclass 14, count 0 2006.285.22:12:13.69#ibcon#read 3, iclass 14, count 0 2006.285.22:12:13.69#ibcon#about to read 4, iclass 14, count 0 2006.285.22:12:13.69#ibcon#read 4, iclass 14, count 0 2006.285.22:12:13.69#ibcon#about to read 5, iclass 14, count 0 2006.285.22:12:13.69#ibcon#read 5, iclass 14, count 0 2006.285.22:12:13.69#ibcon#about to read 6, iclass 14, count 0 2006.285.22:12:13.69#ibcon#read 6, iclass 14, count 0 2006.285.22:12:13.69#ibcon#end of sib2, iclass 14, count 0 2006.285.22:12:13.69#ibcon#*mode == 0, iclass 14, count 0 2006.285.22:12:13.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.22:12:13.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:12:13.69#ibcon#*before write, iclass 14, count 0 2006.285.22:12:13.69#ibcon#enter sib2, iclass 14, count 0 2006.285.22:12:13.69#ibcon#flushed, iclass 14, count 0 2006.285.22:12:13.69#ibcon#about to write, iclass 14, count 0 2006.285.22:12:13.69#ibcon#wrote, iclass 14, count 0 2006.285.22:12:13.69#ibcon#about to read 3, iclass 14, count 0 2006.285.22:12:13.74#ibcon#read 3, iclass 14, count 0 2006.285.22:12:13.74#ibcon#about to read 4, iclass 14, count 0 2006.285.22:12:13.74#ibcon#read 4, iclass 14, count 0 2006.285.22:12:13.74#ibcon#about to read 5, iclass 14, count 0 2006.285.22:12:13.74#ibcon#read 5, iclass 14, count 0 2006.285.22:12:13.74#ibcon#about to read 6, iclass 14, count 0 2006.285.22:12:13.74#ibcon#read 6, iclass 14, count 0 2006.285.22:12:13.74#ibcon#end of sib2, iclass 14, count 0 2006.285.22:12:13.74#ibcon#*after write, iclass 14, count 0 2006.285.22:12:13.74#ibcon#*before return 0, iclass 14, count 0 2006.285.22:12:13.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:12:13.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:12:13.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.22:12:13.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.22:12:13.74$vck44/va=1,7 2006.285.22:12:13.74#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.22:12:13.74#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.22:12:13.74#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:13.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:12:13.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:12:13.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:12:13.74#ibcon#enter wrdev, iclass 16, count 2 2006.285.22:12:13.74#ibcon#first serial, iclass 16, count 2 2006.285.22:12:13.74#ibcon#enter sib2, iclass 16, count 2 2006.285.22:12:13.74#ibcon#flushed, iclass 16, count 2 2006.285.22:12:13.74#ibcon#about to write, iclass 16, count 2 2006.285.22:12:13.74#ibcon#wrote, iclass 16, count 2 2006.285.22:12:13.74#ibcon#about to read 3, iclass 16, count 2 2006.285.22:12:13.76#ibcon#read 3, iclass 16, count 2 2006.285.22:12:13.76#ibcon#about to read 4, iclass 16, count 2 2006.285.22:12:13.76#ibcon#read 4, iclass 16, count 2 2006.285.22:12:13.76#ibcon#about to read 5, iclass 16, count 2 2006.285.22:12:13.76#ibcon#read 5, iclass 16, count 2 2006.285.22:12:13.76#ibcon#about to read 6, iclass 16, count 2 2006.285.22:12:14.24#ibcon#read 6, iclass 16, count 2 2006.285.22:12:14.24#ibcon#end of sib2, iclass 16, count 2 2006.285.22:12:14.24#ibcon#*mode == 0, iclass 16, count 2 2006.285.22:12:14.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.22:12:14.24#ibcon#[25=AT01-07\r\n] 2006.285.22:12:14.24#ibcon#*before write, iclass 16, count 2 2006.285.22:12:14.24#ibcon#enter sib2, iclass 16, count 2 2006.285.22:12:14.24#ibcon#flushed, iclass 16, count 2 2006.285.22:12:14.24#ibcon#about to write, iclass 16, count 2 2006.285.22:12:14.24#ibcon#wrote, iclass 16, count 2 2006.285.22:12:14.24#ibcon#about to read 3, iclass 16, count 2 2006.285.22:12:14.27#ibcon#read 3, iclass 16, count 2 2006.285.22:12:14.27#ibcon#about to read 4, iclass 16, count 2 2006.285.22:12:14.27#ibcon#read 4, iclass 16, count 2 2006.285.22:12:14.27#ibcon#about to read 5, iclass 16, count 2 2006.285.22:12:14.27#ibcon#read 5, iclass 16, count 2 2006.285.22:12:14.27#ibcon#about to read 6, iclass 16, count 2 2006.285.22:12:14.27#ibcon#read 6, iclass 16, count 2 2006.285.22:12:14.27#ibcon#end of sib2, iclass 16, count 2 2006.285.22:12:14.27#ibcon#*after write, iclass 16, count 2 2006.285.22:12:14.27#ibcon#*before return 0, iclass 16, count 2 2006.285.22:12:14.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:12:14.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:12:14.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.22:12:14.27#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:14.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:12:14.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:12:14.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:12:14.39#ibcon#enter wrdev, iclass 16, count 0 2006.285.22:12:14.39#ibcon#first serial, iclass 16, count 0 2006.285.22:12:14.39#ibcon#enter sib2, iclass 16, count 0 2006.285.22:12:14.39#ibcon#flushed, iclass 16, count 0 2006.285.22:12:14.39#ibcon#about to write, iclass 16, count 0 2006.285.22:12:14.39#ibcon#wrote, iclass 16, count 0 2006.285.22:12:14.39#ibcon#about to read 3, iclass 16, count 0 2006.285.22:12:14.41#ibcon#read 3, iclass 16, count 0 2006.285.22:12:14.41#ibcon#about to read 4, iclass 16, count 0 2006.285.22:12:14.41#ibcon#read 4, iclass 16, count 0 2006.285.22:12:14.41#ibcon#about to read 5, iclass 16, count 0 2006.285.22:12:14.41#ibcon#read 5, iclass 16, count 0 2006.285.22:12:14.41#ibcon#about to read 6, iclass 16, count 0 2006.285.22:12:14.41#ibcon#read 6, iclass 16, count 0 2006.285.22:12:14.41#ibcon#end of sib2, iclass 16, count 0 2006.285.22:12:14.41#ibcon#*mode == 0, iclass 16, count 0 2006.285.22:12:14.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.22:12:14.41#ibcon#[25=USB\r\n] 2006.285.22:12:14.41#ibcon#*before write, iclass 16, count 0 2006.285.22:12:14.41#ibcon#enter sib2, iclass 16, count 0 2006.285.22:12:14.41#ibcon#flushed, iclass 16, count 0 2006.285.22:12:14.41#ibcon#about to write, iclass 16, count 0 2006.285.22:12:14.41#ibcon#wrote, iclass 16, count 0 2006.285.22:12:14.41#ibcon#about to read 3, iclass 16, count 0 2006.285.22:12:14.44#ibcon#read 3, iclass 16, count 0 2006.285.22:12:14.44#ibcon#about to read 4, iclass 16, count 0 2006.285.22:12:14.44#ibcon#read 4, iclass 16, count 0 2006.285.22:12:14.44#ibcon#about to read 5, iclass 16, count 0 2006.285.22:12:14.44#ibcon#read 5, iclass 16, count 0 2006.285.22:12:14.44#ibcon#about to read 6, iclass 16, count 0 2006.285.22:12:14.44#ibcon#read 6, iclass 16, count 0 2006.285.22:12:14.44#ibcon#end of sib2, iclass 16, count 0 2006.285.22:12:14.44#ibcon#*after write, iclass 16, count 0 2006.285.22:12:14.44#ibcon#*before return 0, iclass 16, count 0 2006.285.22:12:14.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:12:14.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:12:14.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.22:12:14.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.22:12:14.44$vck44/valo=2,534.99 2006.285.22:12:14.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.22:12:14.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.22:12:14.44#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:14.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:12:14.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:12:14.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:12:14.44#ibcon#enter wrdev, iclass 18, count 0 2006.285.22:12:14.44#ibcon#first serial, iclass 18, count 0 2006.285.22:12:14.44#ibcon#enter sib2, iclass 18, count 0 2006.285.22:12:14.44#ibcon#flushed, iclass 18, count 0 2006.285.22:12:14.44#ibcon#about to write, iclass 18, count 0 2006.285.22:12:14.44#ibcon#wrote, iclass 18, count 0 2006.285.22:12:14.44#ibcon#about to read 3, iclass 18, count 0 2006.285.22:12:14.46#ibcon#read 3, iclass 18, count 0 2006.285.22:12:14.71#ibcon#about to read 4, iclass 18, count 0 2006.285.22:12:14.71#ibcon#read 4, iclass 18, count 0 2006.285.22:12:14.71#ibcon#about to read 5, iclass 18, count 0 2006.285.22:12:14.71#ibcon#read 5, iclass 18, count 0 2006.285.22:12:14.71#ibcon#about to read 6, iclass 18, count 0 2006.285.22:12:14.71#ibcon#read 6, iclass 18, count 0 2006.285.22:12:14.71#ibcon#end of sib2, iclass 18, count 0 2006.285.22:12:14.71#ibcon#*mode == 0, iclass 18, count 0 2006.285.22:12:14.71#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.22:12:14.71#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:12:14.71#ibcon#*before write, iclass 18, count 0 2006.285.22:12:14.71#ibcon#enter sib2, iclass 18, count 0 2006.285.22:12:14.71#ibcon#flushed, iclass 18, count 0 2006.285.22:12:14.71#ibcon#about to write, iclass 18, count 0 2006.285.22:12:14.71#ibcon#wrote, iclass 18, count 0 2006.285.22:12:14.71#ibcon#about to read 3, iclass 18, count 0 2006.285.22:12:14.75#ibcon#read 3, iclass 18, count 0 2006.285.22:12:14.75#ibcon#about to read 4, iclass 18, count 0 2006.285.22:12:14.75#ibcon#read 4, iclass 18, count 0 2006.285.22:12:14.75#ibcon#about to read 5, iclass 18, count 0 2006.285.22:12:14.75#ibcon#read 5, iclass 18, count 0 2006.285.22:12:14.75#ibcon#about to read 6, iclass 18, count 0 2006.285.22:12:14.75#ibcon#read 6, iclass 18, count 0 2006.285.22:12:14.75#ibcon#end of sib2, iclass 18, count 0 2006.285.22:12:14.75#ibcon#*after write, iclass 18, count 0 2006.285.22:12:14.75#ibcon#*before return 0, iclass 18, count 0 2006.285.22:12:14.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:12:14.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:12:14.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.22:12:14.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.22:12:14.75$vck44/va=2,6 2006.285.22:12:14.75#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.22:12:14.75#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.22:12:14.75#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:14.75#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:12:14.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:12:14.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:12:14.75#ibcon#enter wrdev, iclass 20, count 2 2006.285.22:12:14.75#ibcon#first serial, iclass 20, count 2 2006.285.22:12:14.75#ibcon#enter sib2, iclass 20, count 2 2006.285.22:12:14.75#ibcon#flushed, iclass 20, count 2 2006.285.22:12:14.75#ibcon#about to write, iclass 20, count 2 2006.285.22:12:14.75#ibcon#wrote, iclass 20, count 2 2006.285.22:12:14.75#ibcon#about to read 3, iclass 20, count 2 2006.285.22:12:14.77#ibcon#read 3, iclass 20, count 2 2006.285.22:12:14.77#ibcon#about to read 4, iclass 20, count 2 2006.285.22:12:14.77#ibcon#read 4, iclass 20, count 2 2006.285.22:12:14.77#ibcon#about to read 5, iclass 20, count 2 2006.285.22:12:14.77#ibcon#read 5, iclass 20, count 2 2006.285.22:12:14.77#ibcon#about to read 6, iclass 20, count 2 2006.285.22:12:14.77#ibcon#read 6, iclass 20, count 2 2006.285.22:12:14.77#ibcon#end of sib2, iclass 20, count 2 2006.285.22:12:14.77#ibcon#*mode == 0, iclass 20, count 2 2006.285.22:12:14.77#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.22:12:14.77#ibcon#[25=AT02-06\r\n] 2006.285.22:12:14.77#ibcon#*before write, iclass 20, count 2 2006.285.22:12:14.77#ibcon#enter sib2, iclass 20, count 2 2006.285.22:12:14.77#ibcon#flushed, iclass 20, count 2 2006.285.22:12:14.77#ibcon#about to write, iclass 20, count 2 2006.285.22:12:14.77#ibcon#wrote, iclass 20, count 2 2006.285.22:12:14.77#ibcon#about to read 3, iclass 20, count 2 2006.285.22:12:14.80#ibcon#read 3, iclass 20, count 2 2006.285.22:12:14.80#ibcon#about to read 4, iclass 20, count 2 2006.285.22:12:14.80#ibcon#read 4, iclass 20, count 2 2006.285.22:12:14.80#ibcon#about to read 5, iclass 20, count 2 2006.285.22:12:14.80#ibcon#read 5, iclass 20, count 2 2006.285.22:12:14.80#ibcon#about to read 6, iclass 20, count 2 2006.285.22:12:14.80#ibcon#read 6, iclass 20, count 2 2006.285.22:12:14.80#ibcon#end of sib2, iclass 20, count 2 2006.285.22:12:14.80#ibcon#*after write, iclass 20, count 2 2006.285.22:12:14.80#ibcon#*before return 0, iclass 20, count 2 2006.285.22:12:14.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:12:14.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:12:14.80#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.22:12:14.80#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:14.80#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:12:14.92#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:12:14.92#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:12:14.92#ibcon#enter wrdev, iclass 20, count 0 2006.285.22:12:14.92#ibcon#first serial, iclass 20, count 0 2006.285.22:12:14.92#ibcon#enter sib2, iclass 20, count 0 2006.285.22:12:14.92#ibcon#flushed, iclass 20, count 0 2006.285.22:12:14.92#ibcon#about to write, iclass 20, count 0 2006.285.22:12:14.92#ibcon#wrote, iclass 20, count 0 2006.285.22:12:14.92#ibcon#about to read 3, iclass 20, count 0 2006.285.22:12:14.94#ibcon#read 3, iclass 20, count 0 2006.285.22:12:14.94#ibcon#about to read 4, iclass 20, count 0 2006.285.22:12:14.94#ibcon#read 4, iclass 20, count 0 2006.285.22:12:14.94#ibcon#about to read 5, iclass 20, count 0 2006.285.22:12:14.94#ibcon#read 5, iclass 20, count 0 2006.285.22:12:14.94#ibcon#about to read 6, iclass 20, count 0 2006.285.22:12:14.94#ibcon#read 6, iclass 20, count 0 2006.285.22:12:14.94#ibcon#end of sib2, iclass 20, count 0 2006.285.22:12:14.94#ibcon#*mode == 0, iclass 20, count 0 2006.285.22:12:14.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.22:12:14.94#ibcon#[25=USB\r\n] 2006.285.22:12:14.94#ibcon#*before write, iclass 20, count 0 2006.285.22:12:14.94#ibcon#enter sib2, iclass 20, count 0 2006.285.22:12:14.94#ibcon#flushed, iclass 20, count 0 2006.285.22:12:14.94#ibcon#about to write, iclass 20, count 0 2006.285.22:12:14.94#ibcon#wrote, iclass 20, count 0 2006.285.22:12:14.94#ibcon#about to read 3, iclass 20, count 0 2006.285.22:12:14.97#ibcon#read 3, iclass 20, count 0 2006.285.22:12:14.97#ibcon#about to read 4, iclass 20, count 0 2006.285.22:12:14.97#ibcon#read 4, iclass 20, count 0 2006.285.22:12:14.97#ibcon#about to read 5, iclass 20, count 0 2006.285.22:12:14.97#ibcon#read 5, iclass 20, count 0 2006.285.22:12:14.97#ibcon#about to read 6, iclass 20, count 0 2006.285.22:12:14.97#ibcon#read 6, iclass 20, count 0 2006.285.22:12:14.97#ibcon#end of sib2, iclass 20, count 0 2006.285.22:12:14.97#ibcon#*after write, iclass 20, count 0 2006.285.22:12:14.97#ibcon#*before return 0, iclass 20, count 0 2006.285.22:12:14.97#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:12:14.97#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:12:14.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.22:12:14.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.22:12:14.97$vck44/valo=3,564.99 2006.285.22:12:14.97#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.22:12:14.97#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.22:12:14.97#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:14.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:12:14.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:12:14.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:12:14.97#ibcon#enter wrdev, iclass 22, count 0 2006.285.22:12:14.97#ibcon#first serial, iclass 22, count 0 2006.285.22:12:14.97#ibcon#enter sib2, iclass 22, count 0 2006.285.22:12:14.97#ibcon#flushed, iclass 22, count 0 2006.285.22:12:14.97#ibcon#about to write, iclass 22, count 0 2006.285.22:12:14.97#ibcon#wrote, iclass 22, count 0 2006.285.22:12:14.97#ibcon#about to read 3, iclass 22, count 0 2006.285.22:12:14.99#ibcon#read 3, iclass 22, count 0 2006.285.22:12:14.99#ibcon#about to read 4, iclass 22, count 0 2006.285.22:12:14.99#ibcon#read 4, iclass 22, count 0 2006.285.22:12:14.99#ibcon#about to read 5, iclass 22, count 0 2006.285.22:12:14.99#ibcon#read 5, iclass 22, count 0 2006.285.22:12:14.99#ibcon#about to read 6, iclass 22, count 0 2006.285.22:12:14.99#ibcon#read 6, iclass 22, count 0 2006.285.22:12:14.99#ibcon#end of sib2, iclass 22, count 0 2006.285.22:12:14.99#ibcon#*mode == 0, iclass 22, count 0 2006.285.22:12:14.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.22:12:14.99#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:12:14.99#ibcon#*before write, iclass 22, count 0 2006.285.22:12:14.99#ibcon#enter sib2, iclass 22, count 0 2006.285.22:12:14.99#ibcon#flushed, iclass 22, count 0 2006.285.22:12:14.99#ibcon#about to write, iclass 22, count 0 2006.285.22:12:14.99#ibcon#wrote, iclass 22, count 0 2006.285.22:12:14.99#ibcon#about to read 3, iclass 22, count 0 2006.285.22:12:15.03#ibcon#read 3, iclass 22, count 0 2006.285.22:12:15.03#ibcon#about to read 4, iclass 22, count 0 2006.285.22:12:15.03#ibcon#read 4, iclass 22, count 0 2006.285.22:12:15.03#ibcon#about to read 5, iclass 22, count 0 2006.285.22:12:15.03#ibcon#read 5, iclass 22, count 0 2006.285.22:12:15.03#ibcon#about to read 6, iclass 22, count 0 2006.285.22:12:15.03#ibcon#read 6, iclass 22, count 0 2006.285.22:12:15.03#ibcon#end of sib2, iclass 22, count 0 2006.285.22:12:15.03#ibcon#*after write, iclass 22, count 0 2006.285.22:12:15.03#ibcon#*before return 0, iclass 22, count 0 2006.285.22:12:15.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:12:15.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:12:15.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.22:12:15.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.22:12:15.03$vck44/va=3,7 2006.285.22:12:15.03#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.22:12:15.03#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.22:12:15.03#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:15.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:12:15.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:12:15.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:12:15.09#ibcon#enter wrdev, iclass 24, count 2 2006.285.22:12:15.09#ibcon#first serial, iclass 24, count 2 2006.285.22:12:15.09#ibcon#enter sib2, iclass 24, count 2 2006.285.22:12:15.09#ibcon#flushed, iclass 24, count 2 2006.285.22:12:15.09#ibcon#about to write, iclass 24, count 2 2006.285.22:12:15.09#ibcon#wrote, iclass 24, count 2 2006.285.22:12:15.09#ibcon#about to read 3, iclass 24, count 2 2006.285.22:12:15.11#ibcon#read 3, iclass 24, count 2 2006.285.22:12:15.11#ibcon#about to read 4, iclass 24, count 2 2006.285.22:12:15.11#ibcon#read 4, iclass 24, count 2 2006.285.22:12:15.11#ibcon#about to read 5, iclass 24, count 2 2006.285.22:12:15.11#ibcon#read 5, iclass 24, count 2 2006.285.22:12:15.11#ibcon#about to read 6, iclass 24, count 2 2006.285.22:12:15.11#ibcon#read 6, iclass 24, count 2 2006.285.22:12:15.11#ibcon#end of sib2, iclass 24, count 2 2006.285.22:12:15.11#ibcon#*mode == 0, iclass 24, count 2 2006.285.22:12:15.11#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.22:12:15.11#ibcon#[25=AT03-07\r\n] 2006.285.22:12:15.11#ibcon#*before write, iclass 24, count 2 2006.285.22:12:15.11#ibcon#enter sib2, iclass 24, count 2 2006.285.22:12:15.11#ibcon#flushed, iclass 24, count 2 2006.285.22:12:15.11#ibcon#about to write, iclass 24, count 2 2006.285.22:12:15.11#ibcon#wrote, iclass 24, count 2 2006.285.22:12:15.11#ibcon#about to read 3, iclass 24, count 2 2006.285.22:12:15.14#ibcon#read 3, iclass 24, count 2 2006.285.22:12:15.14#ibcon#about to read 4, iclass 24, count 2 2006.285.22:12:15.14#ibcon#read 4, iclass 24, count 2 2006.285.22:12:15.14#ibcon#about to read 5, iclass 24, count 2 2006.285.22:12:15.14#ibcon#read 5, iclass 24, count 2 2006.285.22:12:15.14#ibcon#about to read 6, iclass 24, count 2 2006.285.22:12:15.14#ibcon#read 6, iclass 24, count 2 2006.285.22:12:15.14#ibcon#end of sib2, iclass 24, count 2 2006.285.22:12:15.14#ibcon#*after write, iclass 24, count 2 2006.285.22:12:15.14#ibcon#*before return 0, iclass 24, count 2 2006.285.22:12:15.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:12:15.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:12:15.14#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.22:12:15.14#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:15.14#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:12:15.26#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:12:15.26#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:12:15.26#ibcon#enter wrdev, iclass 24, count 0 2006.285.22:12:15.26#ibcon#first serial, iclass 24, count 0 2006.285.22:12:15.26#ibcon#enter sib2, iclass 24, count 0 2006.285.22:12:15.26#ibcon#flushed, iclass 24, count 0 2006.285.22:12:15.26#ibcon#about to write, iclass 24, count 0 2006.285.22:12:15.26#ibcon#wrote, iclass 24, count 0 2006.285.22:12:15.26#ibcon#about to read 3, iclass 24, count 0 2006.285.22:12:15.28#ibcon#read 3, iclass 24, count 0 2006.285.22:12:15.28#ibcon#about to read 4, iclass 24, count 0 2006.285.22:12:15.28#ibcon#read 4, iclass 24, count 0 2006.285.22:12:15.28#ibcon#about to read 5, iclass 24, count 0 2006.285.22:12:15.28#ibcon#read 5, iclass 24, count 0 2006.285.22:12:15.28#ibcon#about to read 6, iclass 24, count 0 2006.285.22:12:15.28#ibcon#read 6, iclass 24, count 0 2006.285.22:12:15.28#ibcon#end of sib2, iclass 24, count 0 2006.285.22:12:15.28#ibcon#*mode == 0, iclass 24, count 0 2006.285.22:12:15.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.22:12:15.28#ibcon#[25=USB\r\n] 2006.285.22:12:15.28#ibcon#*before write, iclass 24, count 0 2006.285.22:12:15.28#ibcon#enter sib2, iclass 24, count 0 2006.285.22:12:15.28#ibcon#flushed, iclass 24, count 0 2006.285.22:12:15.28#ibcon#about to write, iclass 24, count 0 2006.285.22:12:15.28#ibcon#wrote, iclass 24, count 0 2006.285.22:12:15.28#ibcon#about to read 3, iclass 24, count 0 2006.285.22:12:15.31#ibcon#read 3, iclass 24, count 0 2006.285.22:12:15.31#ibcon#about to read 4, iclass 24, count 0 2006.285.22:12:15.31#ibcon#read 4, iclass 24, count 0 2006.285.22:12:15.31#ibcon#about to read 5, iclass 24, count 0 2006.285.22:12:15.31#ibcon#read 5, iclass 24, count 0 2006.285.22:12:15.31#ibcon#about to read 6, iclass 24, count 0 2006.285.22:12:15.31#ibcon#read 6, iclass 24, count 0 2006.285.22:12:15.31#ibcon#end of sib2, iclass 24, count 0 2006.285.22:12:15.31#ibcon#*after write, iclass 24, count 0 2006.285.22:12:15.31#ibcon#*before return 0, iclass 24, count 0 2006.285.22:12:15.31#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:12:15.31#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:12:15.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.22:12:15.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.22:12:15.31$vck44/valo=4,624.99 2006.285.22:12:15.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.22:12:15.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.22:12:15.31#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:15.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:12:15.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:12:15.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:12:15.31#ibcon#enter wrdev, iclass 26, count 0 2006.285.22:12:15.31#ibcon#first serial, iclass 26, count 0 2006.285.22:12:15.31#ibcon#enter sib2, iclass 26, count 0 2006.285.22:12:15.31#ibcon#flushed, iclass 26, count 0 2006.285.22:12:15.31#ibcon#about to write, iclass 26, count 0 2006.285.22:12:15.31#ibcon#wrote, iclass 26, count 0 2006.285.22:12:15.31#ibcon#about to read 3, iclass 26, count 0 2006.285.22:12:15.33#ibcon#read 3, iclass 26, count 0 2006.285.22:12:15.33#ibcon#about to read 4, iclass 26, count 0 2006.285.22:12:15.33#ibcon#read 4, iclass 26, count 0 2006.285.22:12:15.33#ibcon#about to read 5, iclass 26, count 0 2006.285.22:12:15.33#ibcon#read 5, iclass 26, count 0 2006.285.22:12:15.33#ibcon#about to read 6, iclass 26, count 0 2006.285.22:12:15.33#ibcon#read 6, iclass 26, count 0 2006.285.22:12:15.33#ibcon#end of sib2, iclass 26, count 0 2006.285.22:12:15.33#ibcon#*mode == 0, iclass 26, count 0 2006.285.22:12:15.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.22:12:15.33#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:12:15.33#ibcon#*before write, iclass 26, count 0 2006.285.22:12:15.33#ibcon#enter sib2, iclass 26, count 0 2006.285.22:12:15.33#ibcon#flushed, iclass 26, count 0 2006.285.22:12:15.33#ibcon#about to write, iclass 26, count 0 2006.285.22:12:15.33#ibcon#wrote, iclass 26, count 0 2006.285.22:12:15.33#ibcon#about to read 3, iclass 26, count 0 2006.285.22:12:15.37#ibcon#read 3, iclass 26, count 0 2006.285.22:12:15.37#ibcon#about to read 4, iclass 26, count 0 2006.285.22:12:15.37#ibcon#read 4, iclass 26, count 0 2006.285.22:12:15.37#ibcon#about to read 5, iclass 26, count 0 2006.285.22:12:15.37#ibcon#read 5, iclass 26, count 0 2006.285.22:12:15.37#ibcon#about to read 6, iclass 26, count 0 2006.285.22:12:15.37#ibcon#read 6, iclass 26, count 0 2006.285.22:12:15.37#ibcon#end of sib2, iclass 26, count 0 2006.285.22:12:15.37#ibcon#*after write, iclass 26, count 0 2006.285.22:12:15.37#ibcon#*before return 0, iclass 26, count 0 2006.285.22:12:15.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:12:15.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:12:15.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.22:12:15.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.22:12:15.37$vck44/va=4,6 2006.285.22:12:15.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.22:12:15.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.22:12:15.37#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:15.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:12:15.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:12:15.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:12:15.43#ibcon#enter wrdev, iclass 28, count 2 2006.285.22:12:15.43#ibcon#first serial, iclass 28, count 2 2006.285.22:12:15.43#ibcon#enter sib2, iclass 28, count 2 2006.285.22:12:15.43#ibcon#flushed, iclass 28, count 2 2006.285.22:12:15.43#ibcon#about to write, iclass 28, count 2 2006.285.22:12:15.43#ibcon#wrote, iclass 28, count 2 2006.285.22:12:15.43#ibcon#about to read 3, iclass 28, count 2 2006.285.22:12:15.45#ibcon#read 3, iclass 28, count 2 2006.285.22:12:15.45#ibcon#about to read 4, iclass 28, count 2 2006.285.22:12:15.45#ibcon#read 4, iclass 28, count 2 2006.285.22:12:15.45#ibcon#about to read 5, iclass 28, count 2 2006.285.22:12:15.45#ibcon#read 5, iclass 28, count 2 2006.285.22:12:15.45#ibcon#about to read 6, iclass 28, count 2 2006.285.22:12:15.45#ibcon#read 6, iclass 28, count 2 2006.285.22:12:15.45#ibcon#end of sib2, iclass 28, count 2 2006.285.22:12:15.45#ibcon#*mode == 0, iclass 28, count 2 2006.285.22:12:15.45#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.22:12:15.45#ibcon#[25=AT04-06\r\n] 2006.285.22:12:15.45#ibcon#*before write, iclass 28, count 2 2006.285.22:12:15.45#ibcon#enter sib2, iclass 28, count 2 2006.285.22:12:15.45#ibcon#flushed, iclass 28, count 2 2006.285.22:12:15.45#ibcon#about to write, iclass 28, count 2 2006.285.22:12:15.45#ibcon#wrote, iclass 28, count 2 2006.285.22:12:15.45#ibcon#about to read 3, iclass 28, count 2 2006.285.22:12:15.48#ibcon#read 3, iclass 28, count 2 2006.285.22:12:15.48#ibcon#about to read 4, iclass 28, count 2 2006.285.22:12:15.48#ibcon#read 4, iclass 28, count 2 2006.285.22:12:15.48#ibcon#about to read 5, iclass 28, count 2 2006.285.22:12:15.48#ibcon#read 5, iclass 28, count 2 2006.285.22:12:15.48#ibcon#about to read 6, iclass 28, count 2 2006.285.22:12:15.48#ibcon#read 6, iclass 28, count 2 2006.285.22:12:15.48#ibcon#end of sib2, iclass 28, count 2 2006.285.22:12:15.48#ibcon#*after write, iclass 28, count 2 2006.285.22:12:15.48#ibcon#*before return 0, iclass 28, count 2 2006.285.22:12:15.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:12:15.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:12:15.48#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.22:12:15.48#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:15.48#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:12:15.60#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:12:15.60#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:12:15.60#ibcon#enter wrdev, iclass 28, count 0 2006.285.22:12:15.60#ibcon#first serial, iclass 28, count 0 2006.285.22:12:15.60#ibcon#enter sib2, iclass 28, count 0 2006.285.22:12:15.60#ibcon#flushed, iclass 28, count 0 2006.285.22:12:15.60#ibcon#about to write, iclass 28, count 0 2006.285.22:12:15.60#ibcon#wrote, iclass 28, count 0 2006.285.22:12:15.60#ibcon#about to read 3, iclass 28, count 0 2006.285.22:12:15.62#ibcon#read 3, iclass 28, count 0 2006.285.22:12:15.62#ibcon#about to read 4, iclass 28, count 0 2006.285.22:12:15.62#ibcon#read 4, iclass 28, count 0 2006.285.22:12:15.62#ibcon#about to read 5, iclass 28, count 0 2006.285.22:12:15.62#ibcon#read 5, iclass 28, count 0 2006.285.22:12:15.62#ibcon#about to read 6, iclass 28, count 0 2006.285.22:12:15.62#ibcon#read 6, iclass 28, count 0 2006.285.22:12:15.62#ibcon#end of sib2, iclass 28, count 0 2006.285.22:12:15.62#ibcon#*mode == 0, iclass 28, count 0 2006.285.22:12:15.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.22:12:15.62#ibcon#[25=USB\r\n] 2006.285.22:12:15.62#ibcon#*before write, iclass 28, count 0 2006.285.22:12:15.62#ibcon#enter sib2, iclass 28, count 0 2006.285.22:12:15.62#ibcon#flushed, iclass 28, count 0 2006.285.22:12:15.62#ibcon#about to write, iclass 28, count 0 2006.285.22:12:15.62#ibcon#wrote, iclass 28, count 0 2006.285.22:12:15.62#ibcon#about to read 3, iclass 28, count 0 2006.285.22:12:15.65#ibcon#read 3, iclass 28, count 0 2006.285.22:12:15.65#ibcon#about to read 4, iclass 28, count 0 2006.285.22:12:15.65#ibcon#read 4, iclass 28, count 0 2006.285.22:12:15.65#ibcon#about to read 5, iclass 28, count 0 2006.285.22:12:15.65#ibcon#read 5, iclass 28, count 0 2006.285.22:12:15.65#ibcon#about to read 6, iclass 28, count 0 2006.285.22:12:15.65#ibcon#read 6, iclass 28, count 0 2006.285.22:12:15.65#ibcon#end of sib2, iclass 28, count 0 2006.285.22:12:15.65#ibcon#*after write, iclass 28, count 0 2006.285.22:12:15.65#ibcon#*before return 0, iclass 28, count 0 2006.285.22:12:15.65#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:12:15.65#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:12:15.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.22:12:15.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.22:12:15.65$vck44/valo=5,734.99 2006.285.22:12:15.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.22:12:15.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.22:12:15.65#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:15.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:12:15.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:12:15.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:12:15.65#ibcon#enter wrdev, iclass 30, count 0 2006.285.22:12:15.65#ibcon#first serial, iclass 30, count 0 2006.285.22:12:15.65#ibcon#enter sib2, iclass 30, count 0 2006.285.22:12:15.65#ibcon#flushed, iclass 30, count 0 2006.285.22:12:15.65#ibcon#about to write, iclass 30, count 0 2006.285.22:12:15.65#ibcon#wrote, iclass 30, count 0 2006.285.22:12:15.65#ibcon#about to read 3, iclass 30, count 0 2006.285.22:12:15.67#ibcon#read 3, iclass 30, count 0 2006.285.22:12:15.67#ibcon#about to read 4, iclass 30, count 0 2006.285.22:12:15.67#ibcon#read 4, iclass 30, count 0 2006.285.22:12:15.67#ibcon#about to read 5, iclass 30, count 0 2006.285.22:12:15.67#ibcon#read 5, iclass 30, count 0 2006.285.22:12:15.67#ibcon#about to read 6, iclass 30, count 0 2006.285.22:12:15.67#ibcon#read 6, iclass 30, count 0 2006.285.22:12:15.67#ibcon#end of sib2, iclass 30, count 0 2006.285.22:12:15.67#ibcon#*mode == 0, iclass 30, count 0 2006.285.22:12:15.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.22:12:15.67#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:12:15.67#ibcon#*before write, iclass 30, count 0 2006.285.22:12:15.67#ibcon#enter sib2, iclass 30, count 0 2006.285.22:12:15.67#ibcon#flushed, iclass 30, count 0 2006.285.22:12:15.67#ibcon#about to write, iclass 30, count 0 2006.285.22:12:15.67#ibcon#wrote, iclass 30, count 0 2006.285.22:12:15.67#ibcon#about to read 3, iclass 30, count 0 2006.285.22:12:15.71#ibcon#read 3, iclass 30, count 0 2006.285.22:12:15.71#ibcon#about to read 4, iclass 30, count 0 2006.285.22:12:15.71#ibcon#read 4, iclass 30, count 0 2006.285.22:12:15.71#ibcon#about to read 5, iclass 30, count 0 2006.285.22:12:15.71#ibcon#read 5, iclass 30, count 0 2006.285.22:12:15.71#ibcon#about to read 6, iclass 30, count 0 2006.285.22:12:15.71#ibcon#read 6, iclass 30, count 0 2006.285.22:12:15.71#ibcon#end of sib2, iclass 30, count 0 2006.285.22:12:15.71#ibcon#*after write, iclass 30, count 0 2006.285.22:12:15.71#ibcon#*before return 0, iclass 30, count 0 2006.285.22:12:15.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:12:15.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:12:15.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.22:12:15.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.22:12:15.71$vck44/va=5,3 2006.285.22:12:15.71#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.22:12:15.71#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.22:12:15.71#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:15.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:12:15.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:12:15.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:12:15.77#ibcon#enter wrdev, iclass 32, count 2 2006.285.22:12:15.77#ibcon#first serial, iclass 32, count 2 2006.285.22:12:15.77#ibcon#enter sib2, iclass 32, count 2 2006.285.22:12:15.77#ibcon#flushed, iclass 32, count 2 2006.285.22:12:15.77#ibcon#about to write, iclass 32, count 2 2006.285.22:12:15.77#ibcon#wrote, iclass 32, count 2 2006.285.22:12:15.77#ibcon#about to read 3, iclass 32, count 2 2006.285.22:12:15.79#ibcon#read 3, iclass 32, count 2 2006.285.22:12:15.79#ibcon#about to read 4, iclass 32, count 2 2006.285.22:12:15.79#ibcon#read 4, iclass 32, count 2 2006.285.22:12:15.79#ibcon#about to read 5, iclass 32, count 2 2006.285.22:12:15.79#ibcon#read 5, iclass 32, count 2 2006.285.22:12:15.79#ibcon#about to read 6, iclass 32, count 2 2006.285.22:12:15.79#ibcon#read 6, iclass 32, count 2 2006.285.22:12:15.79#ibcon#end of sib2, iclass 32, count 2 2006.285.22:12:15.79#ibcon#*mode == 0, iclass 32, count 2 2006.285.22:12:15.79#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.22:12:15.79#ibcon#[25=AT05-03\r\n] 2006.285.22:12:15.79#ibcon#*before write, iclass 32, count 2 2006.285.22:12:15.79#ibcon#enter sib2, iclass 32, count 2 2006.285.22:12:15.79#ibcon#flushed, iclass 32, count 2 2006.285.22:12:15.79#ibcon#about to write, iclass 32, count 2 2006.285.22:12:15.79#ibcon#wrote, iclass 32, count 2 2006.285.22:12:15.79#ibcon#about to read 3, iclass 32, count 2 2006.285.22:12:15.82#ibcon#read 3, iclass 32, count 2 2006.285.22:12:15.82#ibcon#about to read 4, iclass 32, count 2 2006.285.22:12:15.82#ibcon#read 4, iclass 32, count 2 2006.285.22:12:15.82#ibcon#about to read 5, iclass 32, count 2 2006.285.22:12:15.82#ibcon#read 5, iclass 32, count 2 2006.285.22:12:15.82#ibcon#about to read 6, iclass 32, count 2 2006.285.22:12:15.82#ibcon#read 6, iclass 32, count 2 2006.285.22:12:15.82#ibcon#end of sib2, iclass 32, count 2 2006.285.22:12:15.82#ibcon#*after write, iclass 32, count 2 2006.285.22:12:15.82#ibcon#*before return 0, iclass 32, count 2 2006.285.22:12:15.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:12:15.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:12:15.82#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.22:12:15.82#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:15.82#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:12:15.94#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:12:16.08#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:12:16.08#ibcon#enter wrdev, iclass 32, count 0 2006.285.22:12:16.08#ibcon#first serial, iclass 32, count 0 2006.285.22:12:16.08#ibcon#enter sib2, iclass 32, count 0 2006.285.22:12:16.08#ibcon#flushed, iclass 32, count 0 2006.285.22:12:16.08#ibcon#about to write, iclass 32, count 0 2006.285.22:12:16.08#ibcon#wrote, iclass 32, count 0 2006.285.22:12:16.08#ibcon#about to read 3, iclass 32, count 0 2006.285.22:12:16.09#ibcon#read 3, iclass 32, count 0 2006.285.22:12:16.09#ibcon#about to read 4, iclass 32, count 0 2006.285.22:12:16.09#ibcon#read 4, iclass 32, count 0 2006.285.22:12:16.09#ibcon#about to read 5, iclass 32, count 0 2006.285.22:12:16.09#ibcon#read 5, iclass 32, count 0 2006.285.22:12:16.09#ibcon#about to read 6, iclass 32, count 0 2006.285.22:12:16.09#ibcon#read 6, iclass 32, count 0 2006.285.22:12:16.09#ibcon#end of sib2, iclass 32, count 0 2006.285.22:12:16.09#ibcon#*mode == 0, iclass 32, count 0 2006.285.22:12:16.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.22:12:16.09#ibcon#[25=USB\r\n] 2006.285.22:12:16.09#ibcon#*before write, iclass 32, count 0 2006.285.22:12:16.09#ibcon#enter sib2, iclass 32, count 0 2006.285.22:12:16.09#ibcon#flushed, iclass 32, count 0 2006.285.22:12:16.09#ibcon#about to write, iclass 32, count 0 2006.285.22:12:16.09#ibcon#wrote, iclass 32, count 0 2006.285.22:12:16.09#ibcon#about to read 3, iclass 32, count 0 2006.285.22:12:16.12#ibcon#read 3, iclass 32, count 0 2006.285.22:12:16.12#ibcon#about to read 4, iclass 32, count 0 2006.285.22:12:16.12#ibcon#read 4, iclass 32, count 0 2006.285.22:12:16.12#ibcon#about to read 5, iclass 32, count 0 2006.285.22:12:16.12#ibcon#read 5, iclass 32, count 0 2006.285.22:12:16.12#ibcon#about to read 6, iclass 32, count 0 2006.285.22:12:16.12#ibcon#read 6, iclass 32, count 0 2006.285.22:12:16.12#ibcon#end of sib2, iclass 32, count 0 2006.285.22:12:16.12#ibcon#*after write, iclass 32, count 0 2006.285.22:12:16.12#ibcon#*before return 0, iclass 32, count 0 2006.285.22:12:16.12#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:12:16.12#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:12:16.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.22:12:16.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.22:12:16.12$vck44/valo=6,814.99 2006.285.22:12:16.12#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.22:12:16.12#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.22:12:16.12#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:16.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:12:16.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:12:16.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:12:16.12#ibcon#enter wrdev, iclass 34, count 0 2006.285.22:12:16.12#ibcon#first serial, iclass 34, count 0 2006.285.22:12:16.12#ibcon#enter sib2, iclass 34, count 0 2006.285.22:12:16.12#ibcon#flushed, iclass 34, count 0 2006.285.22:12:16.12#ibcon#about to write, iclass 34, count 0 2006.285.22:12:16.12#ibcon#wrote, iclass 34, count 0 2006.285.22:12:16.12#ibcon#about to read 3, iclass 34, count 0 2006.285.22:12:16.14#ibcon#read 3, iclass 34, count 0 2006.285.22:12:16.14#ibcon#about to read 4, iclass 34, count 0 2006.285.22:12:16.14#ibcon#read 4, iclass 34, count 0 2006.285.22:12:16.14#ibcon#about to read 5, iclass 34, count 0 2006.285.22:12:16.14#ibcon#read 5, iclass 34, count 0 2006.285.22:12:16.14#ibcon#about to read 6, iclass 34, count 0 2006.285.22:12:16.14#ibcon#read 6, iclass 34, count 0 2006.285.22:12:16.14#ibcon#end of sib2, iclass 34, count 0 2006.285.22:12:16.14#ibcon#*mode == 0, iclass 34, count 0 2006.285.22:12:16.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.22:12:16.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:12:16.14#ibcon#*before write, iclass 34, count 0 2006.285.22:12:16.14#ibcon#enter sib2, iclass 34, count 0 2006.285.22:12:16.14#ibcon#flushed, iclass 34, count 0 2006.285.22:12:16.14#ibcon#about to write, iclass 34, count 0 2006.285.22:12:16.14#ibcon#wrote, iclass 34, count 0 2006.285.22:12:16.14#ibcon#about to read 3, iclass 34, count 0 2006.285.22:12:16.18#ibcon#read 3, iclass 34, count 0 2006.285.22:12:16.18#ibcon#about to read 4, iclass 34, count 0 2006.285.22:12:16.18#ibcon#read 4, iclass 34, count 0 2006.285.22:12:16.18#ibcon#about to read 5, iclass 34, count 0 2006.285.22:12:16.18#ibcon#read 5, iclass 34, count 0 2006.285.22:12:16.18#ibcon#about to read 6, iclass 34, count 0 2006.285.22:12:16.18#ibcon#read 6, iclass 34, count 0 2006.285.22:12:16.18#ibcon#end of sib2, iclass 34, count 0 2006.285.22:12:16.18#ibcon#*after write, iclass 34, count 0 2006.285.22:12:16.18#ibcon#*before return 0, iclass 34, count 0 2006.285.22:12:16.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:12:16.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:12:16.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.22:12:16.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.22:12:16.18$vck44/va=6,4 2006.285.22:12:16.18#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.22:12:16.18#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.22:12:16.18#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:16.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:12:16.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:12:16.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:12:16.24#ibcon#enter wrdev, iclass 36, count 2 2006.285.22:12:16.24#ibcon#first serial, iclass 36, count 2 2006.285.22:12:16.24#ibcon#enter sib2, iclass 36, count 2 2006.285.22:12:16.24#ibcon#flushed, iclass 36, count 2 2006.285.22:12:16.24#ibcon#about to write, iclass 36, count 2 2006.285.22:12:16.24#ibcon#wrote, iclass 36, count 2 2006.285.22:12:16.24#ibcon#about to read 3, iclass 36, count 2 2006.285.22:12:16.26#ibcon#read 3, iclass 36, count 2 2006.285.22:12:16.26#ibcon#about to read 4, iclass 36, count 2 2006.285.22:12:16.26#ibcon#read 4, iclass 36, count 2 2006.285.22:12:16.26#ibcon#about to read 5, iclass 36, count 2 2006.285.22:12:16.26#ibcon#read 5, iclass 36, count 2 2006.285.22:12:16.26#ibcon#about to read 6, iclass 36, count 2 2006.285.22:12:16.26#ibcon#read 6, iclass 36, count 2 2006.285.22:12:16.26#ibcon#end of sib2, iclass 36, count 2 2006.285.22:12:16.26#ibcon#*mode == 0, iclass 36, count 2 2006.285.22:12:16.26#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.22:12:16.26#ibcon#[25=AT06-04\r\n] 2006.285.22:12:16.26#ibcon#*before write, iclass 36, count 2 2006.285.22:12:16.26#ibcon#enter sib2, iclass 36, count 2 2006.285.22:12:16.26#ibcon#flushed, iclass 36, count 2 2006.285.22:12:16.26#ibcon#about to write, iclass 36, count 2 2006.285.22:12:16.26#ibcon#wrote, iclass 36, count 2 2006.285.22:12:16.26#ibcon#about to read 3, iclass 36, count 2 2006.285.22:12:16.29#ibcon#read 3, iclass 36, count 2 2006.285.22:12:16.29#ibcon#about to read 4, iclass 36, count 2 2006.285.22:12:16.29#ibcon#read 4, iclass 36, count 2 2006.285.22:12:16.29#ibcon#about to read 5, iclass 36, count 2 2006.285.22:12:16.29#ibcon#read 5, iclass 36, count 2 2006.285.22:12:16.29#ibcon#about to read 6, iclass 36, count 2 2006.285.22:12:16.29#ibcon#read 6, iclass 36, count 2 2006.285.22:12:16.29#ibcon#end of sib2, iclass 36, count 2 2006.285.22:12:16.29#ibcon#*after write, iclass 36, count 2 2006.285.22:12:16.29#ibcon#*before return 0, iclass 36, count 2 2006.285.22:12:16.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:12:16.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:12:16.29#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.22:12:16.29#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:16.29#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:12:16.38#abcon#<5=/14 0.4 1.4 16.101001016.1\r\n> 2006.285.22:12:16.40#abcon#{5=INTERFACE CLEAR} 2006.285.22:12:16.41#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:12:16.41#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:12:16.41#ibcon#enter wrdev, iclass 36, count 0 2006.285.22:12:16.41#ibcon#first serial, iclass 36, count 0 2006.285.22:12:16.41#ibcon#enter sib2, iclass 36, count 0 2006.285.22:12:16.41#ibcon#flushed, iclass 36, count 0 2006.285.22:12:16.41#ibcon#about to write, iclass 36, count 0 2006.285.22:12:16.41#ibcon#wrote, iclass 36, count 0 2006.285.22:12:16.41#ibcon#about to read 3, iclass 36, count 0 2006.285.22:12:16.43#ibcon#read 3, iclass 36, count 0 2006.285.22:12:16.43#ibcon#about to read 4, iclass 36, count 0 2006.285.22:12:16.43#ibcon#read 4, iclass 36, count 0 2006.285.22:12:16.43#ibcon#about to read 5, iclass 36, count 0 2006.285.22:12:16.43#ibcon#read 5, iclass 36, count 0 2006.285.22:12:16.43#ibcon#about to read 6, iclass 36, count 0 2006.285.22:12:16.43#ibcon#read 6, iclass 36, count 0 2006.285.22:12:16.43#ibcon#end of sib2, iclass 36, count 0 2006.285.22:12:16.43#ibcon#*mode == 0, iclass 36, count 0 2006.285.22:12:16.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.22:12:16.43#ibcon#[25=USB\r\n] 2006.285.22:12:16.43#ibcon#*before write, iclass 36, count 0 2006.285.22:12:16.43#ibcon#enter sib2, iclass 36, count 0 2006.285.22:12:16.43#ibcon#flushed, iclass 36, count 0 2006.285.22:12:16.43#ibcon#about to write, iclass 36, count 0 2006.285.22:12:16.43#ibcon#wrote, iclass 36, count 0 2006.285.22:12:16.43#ibcon#about to read 3, iclass 36, count 0 2006.285.22:12:16.46#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:12:16.46#ibcon#read 3, iclass 36, count 0 2006.285.22:12:16.46#ibcon#about to read 4, iclass 36, count 0 2006.285.22:12:16.46#ibcon#read 4, iclass 36, count 0 2006.285.22:12:16.46#ibcon#about to read 5, iclass 36, count 0 2006.285.22:12:16.46#ibcon#read 5, iclass 36, count 0 2006.285.22:12:16.46#ibcon#about to read 6, iclass 36, count 0 2006.285.22:12:16.46#ibcon#read 6, iclass 36, count 0 2006.285.22:12:16.46#ibcon#end of sib2, iclass 36, count 0 2006.285.22:12:16.46#ibcon#*after write, iclass 36, count 0 2006.285.22:12:16.46#ibcon#*before return 0, iclass 36, count 0 2006.285.22:12:16.46#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:12:16.46#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:12:16.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.22:12:16.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.22:12:16.46$vck44/valo=7,864.99 2006.285.22:12:16.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.22:12:16.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.22:12:16.46#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:16.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:12:16.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:12:16.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:12:16.46#ibcon#enter wrdev, iclass 4, count 0 2006.285.22:12:16.46#ibcon#first serial, iclass 4, count 0 2006.285.22:12:16.46#ibcon#enter sib2, iclass 4, count 0 2006.285.22:12:16.46#ibcon#flushed, iclass 4, count 0 2006.285.22:12:16.46#ibcon#about to write, iclass 4, count 0 2006.285.22:12:16.46#ibcon#wrote, iclass 4, count 0 2006.285.22:12:16.46#ibcon#about to read 3, iclass 4, count 0 2006.285.22:12:16.48#ibcon#read 3, iclass 4, count 0 2006.285.22:12:16.48#ibcon#about to read 4, iclass 4, count 0 2006.285.22:12:16.48#ibcon#read 4, iclass 4, count 0 2006.285.22:12:16.48#ibcon#about to read 5, iclass 4, count 0 2006.285.22:12:16.48#ibcon#read 5, iclass 4, count 0 2006.285.22:12:16.48#ibcon#about to read 6, iclass 4, count 0 2006.285.22:12:16.48#ibcon#read 6, iclass 4, count 0 2006.285.22:12:16.48#ibcon#end of sib2, iclass 4, count 0 2006.285.22:12:16.48#ibcon#*mode == 0, iclass 4, count 0 2006.285.22:12:16.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.22:12:16.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:12:16.48#ibcon#*before write, iclass 4, count 0 2006.285.22:12:16.48#ibcon#enter sib2, iclass 4, count 0 2006.285.22:12:16.48#ibcon#flushed, iclass 4, count 0 2006.285.22:12:16.48#ibcon#about to write, iclass 4, count 0 2006.285.22:12:16.48#ibcon#wrote, iclass 4, count 0 2006.285.22:12:16.48#ibcon#about to read 3, iclass 4, count 0 2006.285.22:12:16.52#ibcon#read 3, iclass 4, count 0 2006.285.22:12:16.52#ibcon#about to read 4, iclass 4, count 0 2006.285.22:12:16.52#ibcon#read 4, iclass 4, count 0 2006.285.22:12:16.52#ibcon#about to read 5, iclass 4, count 0 2006.285.22:12:16.52#ibcon#read 5, iclass 4, count 0 2006.285.22:12:16.52#ibcon#about to read 6, iclass 4, count 0 2006.285.22:12:16.52#ibcon#read 6, iclass 4, count 0 2006.285.22:12:16.52#ibcon#end of sib2, iclass 4, count 0 2006.285.22:12:16.52#ibcon#*after write, iclass 4, count 0 2006.285.22:12:16.52#ibcon#*before return 0, iclass 4, count 0 2006.285.22:12:16.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:12:16.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:12:16.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.22:12:16.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.22:12:16.52$vck44/va=7,4 2006.285.22:12:16.52#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.22:12:16.52#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.22:12:16.52#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:16.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:12:16.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:12:16.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:12:16.58#ibcon#enter wrdev, iclass 6, count 2 2006.285.22:12:16.58#ibcon#first serial, iclass 6, count 2 2006.285.22:12:16.58#ibcon#enter sib2, iclass 6, count 2 2006.285.22:12:16.58#ibcon#flushed, iclass 6, count 2 2006.285.22:12:16.58#ibcon#about to write, iclass 6, count 2 2006.285.22:12:16.58#ibcon#wrote, iclass 6, count 2 2006.285.22:12:16.58#ibcon#about to read 3, iclass 6, count 2 2006.285.22:12:16.60#ibcon#read 3, iclass 6, count 2 2006.285.22:12:16.60#ibcon#about to read 4, iclass 6, count 2 2006.285.22:12:16.60#ibcon#read 4, iclass 6, count 2 2006.285.22:12:16.60#ibcon#about to read 5, iclass 6, count 2 2006.285.22:12:16.60#ibcon#read 5, iclass 6, count 2 2006.285.22:12:16.60#ibcon#about to read 6, iclass 6, count 2 2006.285.22:12:16.60#ibcon#read 6, iclass 6, count 2 2006.285.22:12:16.60#ibcon#end of sib2, iclass 6, count 2 2006.285.22:12:16.60#ibcon#*mode == 0, iclass 6, count 2 2006.285.22:12:16.60#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.22:12:16.60#ibcon#[25=AT07-04\r\n] 2006.285.22:12:16.60#ibcon#*before write, iclass 6, count 2 2006.285.22:12:16.60#ibcon#enter sib2, iclass 6, count 2 2006.285.22:12:16.60#ibcon#flushed, iclass 6, count 2 2006.285.22:12:16.60#ibcon#about to write, iclass 6, count 2 2006.285.22:12:16.60#ibcon#wrote, iclass 6, count 2 2006.285.22:12:16.60#ibcon#about to read 3, iclass 6, count 2 2006.285.22:12:16.63#ibcon#read 3, iclass 6, count 2 2006.285.22:12:16.63#ibcon#about to read 4, iclass 6, count 2 2006.285.22:12:16.63#ibcon#read 4, iclass 6, count 2 2006.285.22:12:16.63#ibcon#about to read 5, iclass 6, count 2 2006.285.22:12:16.63#ibcon#read 5, iclass 6, count 2 2006.285.22:12:16.63#ibcon#about to read 6, iclass 6, count 2 2006.285.22:12:16.63#ibcon#read 6, iclass 6, count 2 2006.285.22:12:16.63#ibcon#end of sib2, iclass 6, count 2 2006.285.22:12:16.63#ibcon#*after write, iclass 6, count 2 2006.285.22:12:16.63#ibcon#*before return 0, iclass 6, count 2 2006.285.22:12:16.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:12:16.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:12:16.63#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.22:12:16.63#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:16.63#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:12:16.75#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:12:16.75#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:12:16.75#ibcon#enter wrdev, iclass 6, count 0 2006.285.22:12:16.75#ibcon#first serial, iclass 6, count 0 2006.285.22:12:16.75#ibcon#enter sib2, iclass 6, count 0 2006.285.22:12:16.75#ibcon#flushed, iclass 6, count 0 2006.285.22:12:16.75#ibcon#about to write, iclass 6, count 0 2006.285.22:12:16.75#ibcon#wrote, iclass 6, count 0 2006.285.22:12:16.75#ibcon#about to read 3, iclass 6, count 0 2006.285.22:12:16.77#ibcon#read 3, iclass 6, count 0 2006.285.22:12:16.77#ibcon#about to read 4, iclass 6, count 0 2006.285.22:12:16.77#ibcon#read 4, iclass 6, count 0 2006.285.22:12:16.77#ibcon#about to read 5, iclass 6, count 0 2006.285.22:12:16.77#ibcon#read 5, iclass 6, count 0 2006.285.22:12:16.77#ibcon#about to read 6, iclass 6, count 0 2006.285.22:12:16.77#ibcon#read 6, iclass 6, count 0 2006.285.22:12:16.77#ibcon#end of sib2, iclass 6, count 0 2006.285.22:12:16.77#ibcon#*mode == 0, iclass 6, count 0 2006.285.22:12:16.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.22:12:16.77#ibcon#[25=USB\r\n] 2006.285.22:12:16.77#ibcon#*before write, iclass 6, count 0 2006.285.22:12:16.77#ibcon#enter sib2, iclass 6, count 0 2006.285.22:12:16.77#ibcon#flushed, iclass 6, count 0 2006.285.22:12:16.77#ibcon#about to write, iclass 6, count 0 2006.285.22:12:16.77#ibcon#wrote, iclass 6, count 0 2006.285.22:12:16.77#ibcon#about to read 3, iclass 6, count 0 2006.285.22:12:16.80#ibcon#read 3, iclass 6, count 0 2006.285.22:12:16.80#ibcon#about to read 4, iclass 6, count 0 2006.285.22:12:16.80#ibcon#read 4, iclass 6, count 0 2006.285.22:12:16.80#ibcon#about to read 5, iclass 6, count 0 2006.285.22:12:16.80#ibcon#read 5, iclass 6, count 0 2006.285.22:12:16.80#ibcon#about to read 6, iclass 6, count 0 2006.285.22:12:16.80#ibcon#read 6, iclass 6, count 0 2006.285.22:12:16.80#ibcon#end of sib2, iclass 6, count 0 2006.285.22:12:16.80#ibcon#*after write, iclass 6, count 0 2006.285.22:12:16.80#ibcon#*before return 0, iclass 6, count 0 2006.285.22:12:16.80#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:12:16.80#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:12:16.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.22:12:16.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.22:12:16.80$vck44/valo=8,884.99 2006.285.22:12:16.80#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.22:12:16.80#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.22:12:16.80#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:16.80#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:12:16.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:12:16.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:12:16.80#ibcon#enter wrdev, iclass 10, count 0 2006.285.22:12:16.80#ibcon#first serial, iclass 10, count 0 2006.285.22:12:16.80#ibcon#enter sib2, iclass 10, count 0 2006.285.22:12:16.80#ibcon#flushed, iclass 10, count 0 2006.285.22:12:16.80#ibcon#about to write, iclass 10, count 0 2006.285.22:12:16.80#ibcon#wrote, iclass 10, count 0 2006.285.22:12:16.80#ibcon#about to read 3, iclass 10, count 0 2006.285.22:12:16.82#ibcon#read 3, iclass 10, count 0 2006.285.22:12:17.04#ibcon#about to read 4, iclass 10, count 0 2006.285.22:12:17.04#ibcon#read 4, iclass 10, count 0 2006.285.22:12:17.04#ibcon#about to read 5, iclass 10, count 0 2006.285.22:12:17.04#ibcon#read 5, iclass 10, count 0 2006.285.22:12:17.04#ibcon#about to read 6, iclass 10, count 0 2006.285.22:12:17.04#ibcon#read 6, iclass 10, count 0 2006.285.22:12:17.04#ibcon#end of sib2, iclass 10, count 0 2006.285.22:12:17.04#ibcon#*mode == 0, iclass 10, count 0 2006.285.22:12:17.04#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.22:12:17.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:12:17.04#ibcon#*before write, iclass 10, count 0 2006.285.22:12:17.04#ibcon#enter sib2, iclass 10, count 0 2006.285.22:12:17.04#ibcon#flushed, iclass 10, count 0 2006.285.22:12:17.04#ibcon#about to write, iclass 10, count 0 2006.285.22:12:17.04#ibcon#wrote, iclass 10, count 0 2006.285.22:12:17.04#ibcon#about to read 3, iclass 10, count 0 2006.285.22:12:17.08#ibcon#read 3, iclass 10, count 0 2006.285.22:12:17.08#ibcon#about to read 4, iclass 10, count 0 2006.285.22:12:17.08#ibcon#read 4, iclass 10, count 0 2006.285.22:12:17.08#ibcon#about to read 5, iclass 10, count 0 2006.285.22:12:17.08#ibcon#read 5, iclass 10, count 0 2006.285.22:12:17.08#ibcon#about to read 6, iclass 10, count 0 2006.285.22:12:17.08#ibcon#read 6, iclass 10, count 0 2006.285.22:12:17.08#ibcon#end of sib2, iclass 10, count 0 2006.285.22:12:17.08#ibcon#*after write, iclass 10, count 0 2006.285.22:12:17.08#ibcon#*before return 0, iclass 10, count 0 2006.285.22:12:17.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:12:17.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:12:17.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.22:12:17.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.22:12:17.08$vck44/va=8,3 2006.285.22:12:17.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.22:12:17.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.22:12:17.08#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:17.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:12:17.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:12:17.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:12:17.08#ibcon#enter wrdev, iclass 12, count 2 2006.285.22:12:17.08#ibcon#first serial, iclass 12, count 2 2006.285.22:12:17.08#ibcon#enter sib2, iclass 12, count 2 2006.285.22:12:17.08#ibcon#flushed, iclass 12, count 2 2006.285.22:12:17.08#ibcon#about to write, iclass 12, count 2 2006.285.22:12:17.08#ibcon#wrote, iclass 12, count 2 2006.285.22:12:17.08#ibcon#about to read 3, iclass 12, count 2 2006.285.22:12:17.10#ibcon#read 3, iclass 12, count 2 2006.285.22:12:17.10#ibcon#about to read 4, iclass 12, count 2 2006.285.22:12:17.10#ibcon#read 4, iclass 12, count 2 2006.285.22:12:17.10#ibcon#about to read 5, iclass 12, count 2 2006.285.22:12:17.10#ibcon#read 5, iclass 12, count 2 2006.285.22:12:17.10#ibcon#about to read 6, iclass 12, count 2 2006.285.22:12:17.10#ibcon#read 6, iclass 12, count 2 2006.285.22:12:17.10#ibcon#end of sib2, iclass 12, count 2 2006.285.22:12:17.10#ibcon#*mode == 0, iclass 12, count 2 2006.285.22:12:17.10#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.22:12:17.10#ibcon#[25=AT08-03\r\n] 2006.285.22:12:17.10#ibcon#*before write, iclass 12, count 2 2006.285.22:12:17.10#ibcon#enter sib2, iclass 12, count 2 2006.285.22:12:17.10#ibcon#flushed, iclass 12, count 2 2006.285.22:12:17.10#ibcon#about to write, iclass 12, count 2 2006.285.22:12:17.10#ibcon#wrote, iclass 12, count 2 2006.285.22:12:17.10#ibcon#about to read 3, iclass 12, count 2 2006.285.22:12:17.13#ibcon#read 3, iclass 12, count 2 2006.285.22:12:17.13#ibcon#about to read 4, iclass 12, count 2 2006.285.22:12:17.13#ibcon#read 4, iclass 12, count 2 2006.285.22:12:17.13#ibcon#about to read 5, iclass 12, count 2 2006.285.22:12:17.13#ibcon#read 5, iclass 12, count 2 2006.285.22:12:17.13#ibcon#about to read 6, iclass 12, count 2 2006.285.22:12:17.13#ibcon#read 6, iclass 12, count 2 2006.285.22:12:17.13#ibcon#end of sib2, iclass 12, count 2 2006.285.22:12:17.13#ibcon#*after write, iclass 12, count 2 2006.285.22:12:17.13#ibcon#*before return 0, iclass 12, count 2 2006.285.22:12:17.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:12:17.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:12:17.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.22:12:17.13#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:17.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:12:17.25#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:12:17.25#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:12:17.25#ibcon#enter wrdev, iclass 12, count 0 2006.285.22:12:17.25#ibcon#first serial, iclass 12, count 0 2006.285.22:12:17.25#ibcon#enter sib2, iclass 12, count 0 2006.285.22:12:17.25#ibcon#flushed, iclass 12, count 0 2006.285.22:12:17.25#ibcon#about to write, iclass 12, count 0 2006.285.22:12:17.25#ibcon#wrote, iclass 12, count 0 2006.285.22:12:17.25#ibcon#about to read 3, iclass 12, count 0 2006.285.22:12:17.27#ibcon#read 3, iclass 12, count 0 2006.285.22:12:17.27#ibcon#about to read 4, iclass 12, count 0 2006.285.22:12:17.27#ibcon#read 4, iclass 12, count 0 2006.285.22:12:17.27#ibcon#about to read 5, iclass 12, count 0 2006.285.22:12:17.27#ibcon#read 5, iclass 12, count 0 2006.285.22:12:17.27#ibcon#about to read 6, iclass 12, count 0 2006.285.22:12:17.27#ibcon#read 6, iclass 12, count 0 2006.285.22:12:17.27#ibcon#end of sib2, iclass 12, count 0 2006.285.22:12:17.27#ibcon#*mode == 0, iclass 12, count 0 2006.285.22:12:17.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.22:12:17.27#ibcon#[25=USB\r\n] 2006.285.22:12:17.27#ibcon#*before write, iclass 12, count 0 2006.285.22:12:17.27#ibcon#enter sib2, iclass 12, count 0 2006.285.22:12:17.27#ibcon#flushed, iclass 12, count 0 2006.285.22:12:17.27#ibcon#about to write, iclass 12, count 0 2006.285.22:12:17.27#ibcon#wrote, iclass 12, count 0 2006.285.22:12:17.27#ibcon#about to read 3, iclass 12, count 0 2006.285.22:12:17.30#ibcon#read 3, iclass 12, count 0 2006.285.22:12:17.30#ibcon#about to read 4, iclass 12, count 0 2006.285.22:12:17.30#ibcon#read 4, iclass 12, count 0 2006.285.22:12:17.30#ibcon#about to read 5, iclass 12, count 0 2006.285.22:12:17.30#ibcon#read 5, iclass 12, count 0 2006.285.22:12:17.30#ibcon#about to read 6, iclass 12, count 0 2006.285.22:12:17.30#ibcon#read 6, iclass 12, count 0 2006.285.22:12:17.30#ibcon#end of sib2, iclass 12, count 0 2006.285.22:12:17.30#ibcon#*after write, iclass 12, count 0 2006.285.22:12:17.30#ibcon#*before return 0, iclass 12, count 0 2006.285.22:12:17.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:12:17.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:12:17.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.22:12:17.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.22:12:17.30$vck44/vblo=1,629.99 2006.285.22:12:17.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.22:12:17.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.22:12:17.30#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:17.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:12:17.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:12:17.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:12:17.30#ibcon#enter wrdev, iclass 14, count 0 2006.285.22:12:17.30#ibcon#first serial, iclass 14, count 0 2006.285.22:12:17.30#ibcon#enter sib2, iclass 14, count 0 2006.285.22:12:17.30#ibcon#flushed, iclass 14, count 0 2006.285.22:12:17.30#ibcon#about to write, iclass 14, count 0 2006.285.22:12:17.30#ibcon#wrote, iclass 14, count 0 2006.285.22:12:17.30#ibcon#about to read 3, iclass 14, count 0 2006.285.22:12:17.32#ibcon#read 3, iclass 14, count 0 2006.285.22:12:17.32#ibcon#about to read 4, iclass 14, count 0 2006.285.22:12:17.32#ibcon#read 4, iclass 14, count 0 2006.285.22:12:17.32#ibcon#about to read 5, iclass 14, count 0 2006.285.22:12:17.32#ibcon#read 5, iclass 14, count 0 2006.285.22:12:17.32#ibcon#about to read 6, iclass 14, count 0 2006.285.22:12:17.32#ibcon#read 6, iclass 14, count 0 2006.285.22:12:17.32#ibcon#end of sib2, iclass 14, count 0 2006.285.22:12:17.32#ibcon#*mode == 0, iclass 14, count 0 2006.285.22:12:17.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.22:12:17.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:12:17.32#ibcon#*before write, iclass 14, count 0 2006.285.22:12:17.32#ibcon#enter sib2, iclass 14, count 0 2006.285.22:12:17.32#ibcon#flushed, iclass 14, count 0 2006.285.22:12:17.32#ibcon#about to write, iclass 14, count 0 2006.285.22:12:17.32#ibcon#wrote, iclass 14, count 0 2006.285.22:12:17.32#ibcon#about to read 3, iclass 14, count 0 2006.285.22:12:17.36#ibcon#read 3, iclass 14, count 0 2006.285.22:12:17.36#ibcon#about to read 4, iclass 14, count 0 2006.285.22:12:17.36#ibcon#read 4, iclass 14, count 0 2006.285.22:12:17.36#ibcon#about to read 5, iclass 14, count 0 2006.285.22:12:17.36#ibcon#read 5, iclass 14, count 0 2006.285.22:12:17.36#ibcon#about to read 6, iclass 14, count 0 2006.285.22:12:17.36#ibcon#read 6, iclass 14, count 0 2006.285.22:12:17.36#ibcon#end of sib2, iclass 14, count 0 2006.285.22:12:17.36#ibcon#*after write, iclass 14, count 0 2006.285.22:12:17.36#ibcon#*before return 0, iclass 14, count 0 2006.285.22:12:17.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:12:17.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:12:17.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.22:12:17.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.22:12:17.36$vck44/vb=1,4 2006.285.22:12:17.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.22:12:17.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.22:12:17.36#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:17.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:12:17.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:12:17.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:12:17.36#ibcon#enter wrdev, iclass 16, count 2 2006.285.22:12:17.36#ibcon#first serial, iclass 16, count 2 2006.285.22:12:17.36#ibcon#enter sib2, iclass 16, count 2 2006.285.22:12:17.36#ibcon#flushed, iclass 16, count 2 2006.285.22:12:17.36#ibcon#about to write, iclass 16, count 2 2006.285.22:12:17.36#ibcon#wrote, iclass 16, count 2 2006.285.22:12:17.36#ibcon#about to read 3, iclass 16, count 2 2006.285.22:12:17.38#ibcon#read 3, iclass 16, count 2 2006.285.22:12:17.38#ibcon#about to read 4, iclass 16, count 2 2006.285.22:12:17.38#ibcon#read 4, iclass 16, count 2 2006.285.22:12:17.38#ibcon#about to read 5, iclass 16, count 2 2006.285.22:12:17.38#ibcon#read 5, iclass 16, count 2 2006.285.22:12:17.38#ibcon#about to read 6, iclass 16, count 2 2006.285.22:12:17.38#ibcon#read 6, iclass 16, count 2 2006.285.22:12:17.38#ibcon#end of sib2, iclass 16, count 2 2006.285.22:12:17.38#ibcon#*mode == 0, iclass 16, count 2 2006.285.22:12:17.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.22:12:17.38#ibcon#[27=AT01-04\r\n] 2006.285.22:12:17.38#ibcon#*before write, iclass 16, count 2 2006.285.22:12:17.38#ibcon#enter sib2, iclass 16, count 2 2006.285.22:12:17.38#ibcon#flushed, iclass 16, count 2 2006.285.22:12:17.38#ibcon#about to write, iclass 16, count 2 2006.285.22:12:17.38#ibcon#wrote, iclass 16, count 2 2006.285.22:12:17.38#ibcon#about to read 3, iclass 16, count 2 2006.285.22:12:17.41#ibcon#read 3, iclass 16, count 2 2006.285.22:12:17.41#ibcon#about to read 4, iclass 16, count 2 2006.285.22:12:17.41#ibcon#read 4, iclass 16, count 2 2006.285.22:12:17.41#ibcon#about to read 5, iclass 16, count 2 2006.285.22:12:17.41#ibcon#read 5, iclass 16, count 2 2006.285.22:12:17.41#ibcon#about to read 6, iclass 16, count 2 2006.285.22:12:17.41#ibcon#read 6, iclass 16, count 2 2006.285.22:12:17.41#ibcon#end of sib2, iclass 16, count 2 2006.285.22:12:17.41#ibcon#*after write, iclass 16, count 2 2006.285.22:12:17.41#ibcon#*before return 0, iclass 16, count 2 2006.285.22:12:17.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:12:17.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:12:17.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.22:12:17.41#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:17.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:12:17.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:12:17.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:12:17.53#ibcon#enter wrdev, iclass 16, count 0 2006.285.22:12:17.53#ibcon#first serial, iclass 16, count 0 2006.285.22:12:17.53#ibcon#enter sib2, iclass 16, count 0 2006.285.22:12:17.53#ibcon#flushed, iclass 16, count 0 2006.285.22:12:17.53#ibcon#about to write, iclass 16, count 0 2006.285.22:12:17.53#ibcon#wrote, iclass 16, count 0 2006.285.22:12:17.53#ibcon#about to read 3, iclass 16, count 0 2006.285.22:12:17.55#ibcon#read 3, iclass 16, count 0 2006.285.22:12:17.55#ibcon#about to read 4, iclass 16, count 0 2006.285.22:12:17.55#ibcon#read 4, iclass 16, count 0 2006.285.22:12:17.55#ibcon#about to read 5, iclass 16, count 0 2006.285.22:12:17.55#ibcon#read 5, iclass 16, count 0 2006.285.22:12:17.55#ibcon#about to read 6, iclass 16, count 0 2006.285.22:12:17.55#ibcon#read 6, iclass 16, count 0 2006.285.22:12:17.55#ibcon#end of sib2, iclass 16, count 0 2006.285.22:12:17.55#ibcon#*mode == 0, iclass 16, count 0 2006.285.22:12:17.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.22:12:17.55#ibcon#[27=USB\r\n] 2006.285.22:12:17.55#ibcon#*before write, iclass 16, count 0 2006.285.22:12:17.55#ibcon#enter sib2, iclass 16, count 0 2006.285.22:12:17.55#ibcon#flushed, iclass 16, count 0 2006.285.22:12:17.55#ibcon#about to write, iclass 16, count 0 2006.285.22:12:17.55#ibcon#wrote, iclass 16, count 0 2006.285.22:12:17.55#ibcon#about to read 3, iclass 16, count 0 2006.285.22:12:17.58#ibcon#read 3, iclass 16, count 0 2006.285.22:12:17.58#ibcon#about to read 4, iclass 16, count 0 2006.285.22:12:17.58#ibcon#read 4, iclass 16, count 0 2006.285.22:12:17.58#ibcon#about to read 5, iclass 16, count 0 2006.285.22:12:17.58#ibcon#read 5, iclass 16, count 0 2006.285.22:12:17.58#ibcon#about to read 6, iclass 16, count 0 2006.285.22:12:17.58#ibcon#read 6, iclass 16, count 0 2006.285.22:12:17.58#ibcon#end of sib2, iclass 16, count 0 2006.285.22:12:17.58#ibcon#*after write, iclass 16, count 0 2006.285.22:12:17.58#ibcon#*before return 0, iclass 16, count 0 2006.285.22:12:17.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:12:17.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:12:17.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.22:12:17.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.22:12:17.58$vck44/vblo=2,634.99 2006.285.22:12:17.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.22:12:17.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.22:12:17.58#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:17.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:12:17.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:12:17.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:12:17.58#ibcon#enter wrdev, iclass 18, count 0 2006.285.22:12:17.58#ibcon#first serial, iclass 18, count 0 2006.285.22:12:17.58#ibcon#enter sib2, iclass 18, count 0 2006.285.22:12:17.58#ibcon#flushed, iclass 18, count 0 2006.285.22:12:17.58#ibcon#about to write, iclass 18, count 0 2006.285.22:12:17.58#ibcon#wrote, iclass 18, count 0 2006.285.22:12:17.58#ibcon#about to read 3, iclass 18, count 0 2006.285.22:12:17.60#ibcon#read 3, iclass 18, count 0 2006.285.22:12:17.60#ibcon#about to read 4, iclass 18, count 0 2006.285.22:12:17.60#ibcon#read 4, iclass 18, count 0 2006.285.22:12:17.60#ibcon#about to read 5, iclass 18, count 0 2006.285.22:12:17.60#ibcon#read 5, iclass 18, count 0 2006.285.22:12:17.60#ibcon#about to read 6, iclass 18, count 0 2006.285.22:12:17.60#ibcon#read 6, iclass 18, count 0 2006.285.22:12:17.60#ibcon#end of sib2, iclass 18, count 0 2006.285.22:12:17.60#ibcon#*mode == 0, iclass 18, count 0 2006.285.22:12:17.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.22:12:17.60#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:12:17.60#ibcon#*before write, iclass 18, count 0 2006.285.22:12:17.60#ibcon#enter sib2, iclass 18, count 0 2006.285.22:12:17.60#ibcon#flushed, iclass 18, count 0 2006.285.22:12:17.60#ibcon#about to write, iclass 18, count 0 2006.285.22:12:17.60#ibcon#wrote, iclass 18, count 0 2006.285.22:12:17.60#ibcon#about to read 3, iclass 18, count 0 2006.285.22:12:17.64#ibcon#read 3, iclass 18, count 0 2006.285.22:12:17.64#ibcon#about to read 4, iclass 18, count 0 2006.285.22:12:17.64#ibcon#read 4, iclass 18, count 0 2006.285.22:12:17.64#ibcon#about to read 5, iclass 18, count 0 2006.285.22:12:17.64#ibcon#read 5, iclass 18, count 0 2006.285.22:12:17.64#ibcon#about to read 6, iclass 18, count 0 2006.285.22:12:17.64#ibcon#read 6, iclass 18, count 0 2006.285.22:12:17.64#ibcon#end of sib2, iclass 18, count 0 2006.285.22:12:17.64#ibcon#*after write, iclass 18, count 0 2006.285.22:12:17.64#ibcon#*before return 0, iclass 18, count 0 2006.285.22:12:17.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:12:17.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:12:17.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.22:12:17.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.22:12:17.64$vck44/vb=2,5 2006.285.22:12:17.64#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.22:12:17.64#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.22:12:17.64#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:17.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:12:17.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:12:17.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:12:17.70#ibcon#enter wrdev, iclass 20, count 2 2006.285.22:12:17.70#ibcon#first serial, iclass 20, count 2 2006.285.22:12:17.70#ibcon#enter sib2, iclass 20, count 2 2006.285.22:12:17.70#ibcon#flushed, iclass 20, count 2 2006.285.22:12:17.70#ibcon#about to write, iclass 20, count 2 2006.285.22:12:17.70#ibcon#wrote, iclass 20, count 2 2006.285.22:12:17.70#ibcon#about to read 3, iclass 20, count 2 2006.285.22:12:17.72#ibcon#read 3, iclass 20, count 2 2006.285.22:12:17.72#ibcon#about to read 4, iclass 20, count 2 2006.285.22:12:17.72#ibcon#read 4, iclass 20, count 2 2006.285.22:12:17.72#ibcon#about to read 5, iclass 20, count 2 2006.285.22:12:17.72#ibcon#read 5, iclass 20, count 2 2006.285.22:12:17.72#ibcon#about to read 6, iclass 20, count 2 2006.285.22:12:17.72#ibcon#read 6, iclass 20, count 2 2006.285.22:12:17.72#ibcon#end of sib2, iclass 20, count 2 2006.285.22:12:17.72#ibcon#*mode == 0, iclass 20, count 2 2006.285.22:12:17.72#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.22:12:17.72#ibcon#[27=AT02-05\r\n] 2006.285.22:12:17.72#ibcon#*before write, iclass 20, count 2 2006.285.22:12:17.72#ibcon#enter sib2, iclass 20, count 2 2006.285.22:12:17.72#ibcon#flushed, iclass 20, count 2 2006.285.22:12:17.72#ibcon#about to write, iclass 20, count 2 2006.285.22:12:17.72#ibcon#wrote, iclass 20, count 2 2006.285.22:12:17.72#ibcon#about to read 3, iclass 20, count 2 2006.285.22:12:17.75#ibcon#read 3, iclass 20, count 2 2006.285.22:12:17.75#ibcon#about to read 4, iclass 20, count 2 2006.285.22:12:17.75#ibcon#read 4, iclass 20, count 2 2006.285.22:12:17.75#ibcon#about to read 5, iclass 20, count 2 2006.285.22:12:17.75#ibcon#read 5, iclass 20, count 2 2006.285.22:12:17.75#ibcon#about to read 6, iclass 20, count 2 2006.285.22:12:17.75#ibcon#read 6, iclass 20, count 2 2006.285.22:12:17.75#ibcon#end of sib2, iclass 20, count 2 2006.285.22:12:17.75#ibcon#*after write, iclass 20, count 2 2006.285.22:12:17.75#ibcon#*before return 0, iclass 20, count 2 2006.285.22:12:17.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:12:17.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:12:17.75#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.22:12:17.75#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:17.75#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:12:17.87#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:12:17.87#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:12:17.87#ibcon#enter wrdev, iclass 20, count 0 2006.285.22:12:17.87#ibcon#first serial, iclass 20, count 0 2006.285.22:12:17.87#ibcon#enter sib2, iclass 20, count 0 2006.285.22:12:17.87#ibcon#flushed, iclass 20, count 0 2006.285.22:12:17.87#ibcon#about to write, iclass 20, count 0 2006.285.22:12:17.87#ibcon#wrote, iclass 20, count 0 2006.285.22:12:17.87#ibcon#about to read 3, iclass 20, count 0 2006.285.22:12:17.89#ibcon#read 3, iclass 20, count 0 2006.285.22:12:17.89#ibcon#about to read 4, iclass 20, count 0 2006.285.22:12:17.89#ibcon#read 4, iclass 20, count 0 2006.285.22:12:17.89#ibcon#about to read 5, iclass 20, count 0 2006.285.22:12:17.89#ibcon#read 5, iclass 20, count 0 2006.285.22:12:17.89#ibcon#about to read 6, iclass 20, count 0 2006.285.22:12:17.89#ibcon#read 6, iclass 20, count 0 2006.285.22:12:17.89#ibcon#end of sib2, iclass 20, count 0 2006.285.22:12:17.89#ibcon#*mode == 0, iclass 20, count 0 2006.285.22:12:17.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.22:12:17.89#ibcon#[27=USB\r\n] 2006.285.22:12:17.89#ibcon#*before write, iclass 20, count 0 2006.285.22:12:17.89#ibcon#enter sib2, iclass 20, count 0 2006.285.22:12:17.89#ibcon#flushed, iclass 20, count 0 2006.285.22:12:17.89#ibcon#about to write, iclass 20, count 0 2006.285.22:12:17.89#ibcon#wrote, iclass 20, count 0 2006.285.22:12:17.89#ibcon#about to read 3, iclass 20, count 0 2006.285.22:12:17.92#ibcon#read 3, iclass 20, count 0 2006.285.22:12:17.92#ibcon#about to read 4, iclass 20, count 0 2006.285.22:12:17.92#ibcon#read 4, iclass 20, count 0 2006.285.22:12:17.92#ibcon#about to read 5, iclass 20, count 0 2006.285.22:12:17.92#ibcon#read 5, iclass 20, count 0 2006.285.22:12:17.92#ibcon#about to read 6, iclass 20, count 0 2006.285.22:12:17.92#ibcon#read 6, iclass 20, count 0 2006.285.22:12:17.92#ibcon#end of sib2, iclass 20, count 0 2006.285.22:12:17.92#ibcon#*after write, iclass 20, count 0 2006.285.22:12:17.92#ibcon#*before return 0, iclass 20, count 0 2006.285.22:12:17.92#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:12:17.92#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:12:17.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.22:12:17.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.22:12:17.92$vck44/vblo=3,649.99 2006.285.22:12:17.92#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.22:12:17.92#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.22:12:17.92#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:17.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:12:17.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:12:17.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:12:17.92#ibcon#enter wrdev, iclass 22, count 0 2006.285.22:12:17.92#ibcon#first serial, iclass 22, count 0 2006.285.22:12:17.92#ibcon#enter sib2, iclass 22, count 0 2006.285.22:12:17.92#ibcon#flushed, iclass 22, count 0 2006.285.22:12:17.92#ibcon#about to write, iclass 22, count 0 2006.285.22:12:17.92#ibcon#wrote, iclass 22, count 0 2006.285.22:12:17.92#ibcon#about to read 3, iclass 22, count 0 2006.285.22:12:17.97#ibcon#read 3, iclass 22, count 0 2006.285.22:12:17.97#ibcon#about to read 4, iclass 22, count 0 2006.285.22:12:17.97#ibcon#read 4, iclass 22, count 0 2006.285.22:12:17.97#ibcon#about to read 5, iclass 22, count 0 2006.285.22:12:17.97#ibcon#read 5, iclass 22, count 0 2006.285.22:12:17.97#ibcon#about to read 6, iclass 22, count 0 2006.285.22:12:17.97#ibcon#read 6, iclass 22, count 0 2006.285.22:12:17.97#ibcon#end of sib2, iclass 22, count 0 2006.285.22:12:17.97#ibcon#*mode == 0, iclass 22, count 0 2006.285.22:12:17.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.22:12:17.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:12:17.97#ibcon#*before write, iclass 22, count 0 2006.285.22:12:17.97#ibcon#enter sib2, iclass 22, count 0 2006.285.22:12:17.97#ibcon#flushed, iclass 22, count 0 2006.285.22:12:17.97#ibcon#about to write, iclass 22, count 0 2006.285.22:12:17.97#ibcon#wrote, iclass 22, count 0 2006.285.22:12:17.97#ibcon#about to read 3, iclass 22, count 0 2006.285.22:12:18.01#ibcon#read 3, iclass 22, count 0 2006.285.22:12:18.01#ibcon#about to read 4, iclass 22, count 0 2006.285.22:12:18.01#ibcon#read 4, iclass 22, count 0 2006.285.22:12:18.01#ibcon#about to read 5, iclass 22, count 0 2006.285.22:12:18.01#ibcon#read 5, iclass 22, count 0 2006.285.22:12:18.01#ibcon#about to read 6, iclass 22, count 0 2006.285.22:12:18.01#ibcon#read 6, iclass 22, count 0 2006.285.22:12:18.01#ibcon#end of sib2, iclass 22, count 0 2006.285.22:12:18.01#ibcon#*after write, iclass 22, count 0 2006.285.22:12:18.01#ibcon#*before return 0, iclass 22, count 0 2006.285.22:12:18.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:12:18.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:12:18.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.22:12:18.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.22:12:18.01$vck44/vb=3,4 2006.285.22:12:18.01#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.22:12:18.01#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.22:12:18.01#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:18.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:12:18.04#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:12:18.04#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:12:18.04#ibcon#enter wrdev, iclass 24, count 2 2006.285.22:12:18.04#ibcon#first serial, iclass 24, count 2 2006.285.22:12:18.04#ibcon#enter sib2, iclass 24, count 2 2006.285.22:12:18.04#ibcon#flushed, iclass 24, count 2 2006.285.22:12:18.04#ibcon#about to write, iclass 24, count 2 2006.285.22:12:18.04#ibcon#wrote, iclass 24, count 2 2006.285.22:12:18.04#ibcon#about to read 3, iclass 24, count 2 2006.285.22:12:18.06#ibcon#read 3, iclass 24, count 2 2006.285.22:12:18.06#ibcon#about to read 4, iclass 24, count 2 2006.285.22:12:18.06#ibcon#read 4, iclass 24, count 2 2006.285.22:12:18.06#ibcon#about to read 5, iclass 24, count 2 2006.285.22:12:18.06#ibcon#read 5, iclass 24, count 2 2006.285.22:12:18.06#ibcon#about to read 6, iclass 24, count 2 2006.285.22:12:18.06#ibcon#read 6, iclass 24, count 2 2006.285.22:12:18.06#ibcon#end of sib2, iclass 24, count 2 2006.285.22:12:18.06#ibcon#*mode == 0, iclass 24, count 2 2006.285.22:12:18.06#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.22:12:18.06#ibcon#[27=AT03-04\r\n] 2006.285.22:12:18.06#ibcon#*before write, iclass 24, count 2 2006.285.22:12:18.06#ibcon#enter sib2, iclass 24, count 2 2006.285.22:12:18.06#ibcon#flushed, iclass 24, count 2 2006.285.22:12:18.06#ibcon#about to write, iclass 24, count 2 2006.285.22:12:18.06#ibcon#wrote, iclass 24, count 2 2006.285.22:12:18.06#ibcon#about to read 3, iclass 24, count 2 2006.285.22:12:18.09#ibcon#read 3, iclass 24, count 2 2006.285.22:12:18.09#ibcon#about to read 4, iclass 24, count 2 2006.285.22:12:18.09#ibcon#read 4, iclass 24, count 2 2006.285.22:12:18.09#ibcon#about to read 5, iclass 24, count 2 2006.285.22:12:18.09#ibcon#read 5, iclass 24, count 2 2006.285.22:12:18.09#ibcon#about to read 6, iclass 24, count 2 2006.285.22:12:18.09#ibcon#read 6, iclass 24, count 2 2006.285.22:12:18.09#ibcon#end of sib2, iclass 24, count 2 2006.285.22:12:18.09#ibcon#*after write, iclass 24, count 2 2006.285.22:12:18.09#ibcon#*before return 0, iclass 24, count 2 2006.285.22:12:18.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:12:18.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:12:18.09#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.22:12:18.09#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:18.09#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:12:18.21#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:12:18.21#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:12:18.21#ibcon#enter wrdev, iclass 24, count 0 2006.285.22:12:18.21#ibcon#first serial, iclass 24, count 0 2006.285.22:12:18.21#ibcon#enter sib2, iclass 24, count 0 2006.285.22:12:18.21#ibcon#flushed, iclass 24, count 0 2006.285.22:12:18.21#ibcon#about to write, iclass 24, count 0 2006.285.22:12:18.21#ibcon#wrote, iclass 24, count 0 2006.285.22:12:18.21#ibcon#about to read 3, iclass 24, count 0 2006.285.22:12:18.23#ibcon#read 3, iclass 24, count 0 2006.285.22:12:18.23#ibcon#about to read 4, iclass 24, count 0 2006.285.22:12:18.23#ibcon#read 4, iclass 24, count 0 2006.285.22:12:18.23#ibcon#about to read 5, iclass 24, count 0 2006.285.22:12:18.23#ibcon#read 5, iclass 24, count 0 2006.285.22:12:18.23#ibcon#about to read 6, iclass 24, count 0 2006.285.22:12:18.23#ibcon#read 6, iclass 24, count 0 2006.285.22:12:18.23#ibcon#end of sib2, iclass 24, count 0 2006.285.22:12:18.23#ibcon#*mode == 0, iclass 24, count 0 2006.285.22:12:18.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.22:12:18.23#ibcon#[27=USB\r\n] 2006.285.22:12:18.23#ibcon#*before write, iclass 24, count 0 2006.285.22:12:18.23#ibcon#enter sib2, iclass 24, count 0 2006.285.22:12:18.23#ibcon#flushed, iclass 24, count 0 2006.285.22:12:18.23#ibcon#about to write, iclass 24, count 0 2006.285.22:12:18.23#ibcon#wrote, iclass 24, count 0 2006.285.22:12:18.23#ibcon#about to read 3, iclass 24, count 0 2006.285.22:12:18.26#ibcon#read 3, iclass 24, count 0 2006.285.22:12:18.26#ibcon#about to read 4, iclass 24, count 0 2006.285.22:12:18.26#ibcon#read 4, iclass 24, count 0 2006.285.22:12:18.26#ibcon#about to read 5, iclass 24, count 0 2006.285.22:12:18.26#ibcon#read 5, iclass 24, count 0 2006.285.22:12:18.26#ibcon#about to read 6, iclass 24, count 0 2006.285.22:12:18.26#ibcon#read 6, iclass 24, count 0 2006.285.22:12:18.26#ibcon#end of sib2, iclass 24, count 0 2006.285.22:12:18.26#ibcon#*after write, iclass 24, count 0 2006.285.22:12:18.26#ibcon#*before return 0, iclass 24, count 0 2006.285.22:12:18.26#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:12:18.26#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:12:18.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.22:12:18.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.22:12:18.26$vck44/vblo=4,679.99 2006.285.22:12:18.26#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.22:12:18.26#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.22:12:18.26#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:18.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:12:18.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:12:18.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:12:18.26#ibcon#enter wrdev, iclass 26, count 0 2006.285.22:12:18.26#ibcon#first serial, iclass 26, count 0 2006.285.22:12:18.26#ibcon#enter sib2, iclass 26, count 0 2006.285.22:12:18.26#ibcon#flushed, iclass 26, count 0 2006.285.22:12:18.26#ibcon#about to write, iclass 26, count 0 2006.285.22:12:18.26#ibcon#wrote, iclass 26, count 0 2006.285.22:12:18.26#ibcon#about to read 3, iclass 26, count 0 2006.285.22:12:18.28#ibcon#read 3, iclass 26, count 0 2006.285.22:12:18.28#ibcon#about to read 4, iclass 26, count 0 2006.285.22:12:18.28#ibcon#read 4, iclass 26, count 0 2006.285.22:12:18.28#ibcon#about to read 5, iclass 26, count 0 2006.285.22:12:18.28#ibcon#read 5, iclass 26, count 0 2006.285.22:12:18.28#ibcon#about to read 6, iclass 26, count 0 2006.285.22:12:18.28#ibcon#read 6, iclass 26, count 0 2006.285.22:12:18.28#ibcon#end of sib2, iclass 26, count 0 2006.285.22:12:18.28#ibcon#*mode == 0, iclass 26, count 0 2006.285.22:12:18.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.22:12:18.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.22:12:18.28#ibcon#*before write, iclass 26, count 0 2006.285.22:12:18.28#ibcon#enter sib2, iclass 26, count 0 2006.285.22:12:18.28#ibcon#flushed, iclass 26, count 0 2006.285.22:12:18.28#ibcon#about to write, iclass 26, count 0 2006.285.22:12:18.28#ibcon#wrote, iclass 26, count 0 2006.285.22:12:18.28#ibcon#about to read 3, iclass 26, count 0 2006.285.22:12:18.32#ibcon#read 3, iclass 26, count 0 2006.285.22:12:18.32#ibcon#about to read 4, iclass 26, count 0 2006.285.22:12:18.32#ibcon#read 4, iclass 26, count 0 2006.285.22:12:18.32#ibcon#about to read 5, iclass 26, count 0 2006.285.22:12:18.32#ibcon#read 5, iclass 26, count 0 2006.285.22:12:18.32#ibcon#about to read 6, iclass 26, count 0 2006.285.22:12:18.32#ibcon#read 6, iclass 26, count 0 2006.285.22:12:18.32#ibcon#end of sib2, iclass 26, count 0 2006.285.22:12:18.32#ibcon#*after write, iclass 26, count 0 2006.285.22:12:18.32#ibcon#*before return 0, iclass 26, count 0 2006.285.22:12:18.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:12:18.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:12:18.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.22:12:18.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.22:12:18.32$vck44/vb=4,5 2006.285.22:12:18.32#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.22:12:18.32#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.22:12:18.32#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:18.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:12:18.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:12:18.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:12:18.38#ibcon#enter wrdev, iclass 28, count 2 2006.285.22:12:18.38#ibcon#first serial, iclass 28, count 2 2006.285.22:12:18.38#ibcon#enter sib2, iclass 28, count 2 2006.285.22:12:18.38#ibcon#flushed, iclass 28, count 2 2006.285.22:12:18.38#ibcon#about to write, iclass 28, count 2 2006.285.22:12:18.38#ibcon#wrote, iclass 28, count 2 2006.285.22:12:18.38#ibcon#about to read 3, iclass 28, count 2 2006.285.22:12:18.40#ibcon#read 3, iclass 28, count 2 2006.285.22:12:18.40#ibcon#about to read 4, iclass 28, count 2 2006.285.22:12:18.40#ibcon#read 4, iclass 28, count 2 2006.285.22:12:18.40#ibcon#about to read 5, iclass 28, count 2 2006.285.22:12:18.40#ibcon#read 5, iclass 28, count 2 2006.285.22:12:18.40#ibcon#about to read 6, iclass 28, count 2 2006.285.22:12:18.40#ibcon#read 6, iclass 28, count 2 2006.285.22:12:18.40#ibcon#end of sib2, iclass 28, count 2 2006.285.22:12:18.40#ibcon#*mode == 0, iclass 28, count 2 2006.285.22:12:18.40#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.22:12:18.40#ibcon#[27=AT04-05\r\n] 2006.285.22:12:18.40#ibcon#*before write, iclass 28, count 2 2006.285.22:12:18.40#ibcon#enter sib2, iclass 28, count 2 2006.285.22:12:18.40#ibcon#flushed, iclass 28, count 2 2006.285.22:12:18.40#ibcon#about to write, iclass 28, count 2 2006.285.22:12:18.40#ibcon#wrote, iclass 28, count 2 2006.285.22:12:18.40#ibcon#about to read 3, iclass 28, count 2 2006.285.22:12:18.43#ibcon#read 3, iclass 28, count 2 2006.285.22:12:18.43#ibcon#about to read 4, iclass 28, count 2 2006.285.22:12:18.43#ibcon#read 4, iclass 28, count 2 2006.285.22:12:18.43#ibcon#about to read 5, iclass 28, count 2 2006.285.22:12:18.43#ibcon#read 5, iclass 28, count 2 2006.285.22:12:18.43#ibcon#about to read 6, iclass 28, count 2 2006.285.22:12:18.43#ibcon#read 6, iclass 28, count 2 2006.285.22:12:18.43#ibcon#end of sib2, iclass 28, count 2 2006.285.22:12:18.43#ibcon#*after write, iclass 28, count 2 2006.285.22:12:18.43#ibcon#*before return 0, iclass 28, count 2 2006.285.22:12:18.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:12:18.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:12:18.43#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.22:12:18.43#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:18.43#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:12:18.55#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:12:18.55#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:12:18.55#ibcon#enter wrdev, iclass 28, count 0 2006.285.22:12:18.55#ibcon#first serial, iclass 28, count 0 2006.285.22:12:18.55#ibcon#enter sib2, iclass 28, count 0 2006.285.22:12:18.55#ibcon#flushed, iclass 28, count 0 2006.285.22:12:18.55#ibcon#about to write, iclass 28, count 0 2006.285.22:12:18.55#ibcon#wrote, iclass 28, count 0 2006.285.22:12:18.55#ibcon#about to read 3, iclass 28, count 0 2006.285.22:12:18.57#ibcon#read 3, iclass 28, count 0 2006.285.22:12:18.57#ibcon#about to read 4, iclass 28, count 0 2006.285.22:12:18.57#ibcon#read 4, iclass 28, count 0 2006.285.22:12:18.57#ibcon#about to read 5, iclass 28, count 0 2006.285.22:12:18.57#ibcon#read 5, iclass 28, count 0 2006.285.22:12:18.57#ibcon#about to read 6, iclass 28, count 0 2006.285.22:12:18.57#ibcon#read 6, iclass 28, count 0 2006.285.22:12:18.57#ibcon#end of sib2, iclass 28, count 0 2006.285.22:12:18.57#ibcon#*mode == 0, iclass 28, count 0 2006.285.22:12:18.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.22:12:18.57#ibcon#[27=USB\r\n] 2006.285.22:12:18.57#ibcon#*before write, iclass 28, count 0 2006.285.22:12:18.57#ibcon#enter sib2, iclass 28, count 0 2006.285.22:12:18.57#ibcon#flushed, iclass 28, count 0 2006.285.22:12:18.57#ibcon#about to write, iclass 28, count 0 2006.285.22:12:18.57#ibcon#wrote, iclass 28, count 0 2006.285.22:12:18.57#ibcon#about to read 3, iclass 28, count 0 2006.285.22:12:18.60#ibcon#read 3, iclass 28, count 0 2006.285.22:12:18.60#ibcon#about to read 4, iclass 28, count 0 2006.285.22:12:18.60#ibcon#read 4, iclass 28, count 0 2006.285.22:12:18.60#ibcon#about to read 5, iclass 28, count 0 2006.285.22:12:18.60#ibcon#read 5, iclass 28, count 0 2006.285.22:12:18.60#ibcon#about to read 6, iclass 28, count 0 2006.285.22:12:18.60#ibcon#read 6, iclass 28, count 0 2006.285.22:12:18.60#ibcon#end of sib2, iclass 28, count 0 2006.285.22:12:18.60#ibcon#*after write, iclass 28, count 0 2006.285.22:12:18.60#ibcon#*before return 0, iclass 28, count 0 2006.285.22:12:18.60#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:12:18.60#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:12:18.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.22:12:18.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.22:12:18.60$vck44/vblo=5,709.99 2006.285.22:12:18.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.22:12:18.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.22:12:18.60#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:18.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:12:18.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:12:18.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:12:18.60#ibcon#enter wrdev, iclass 30, count 0 2006.285.22:12:18.60#ibcon#first serial, iclass 30, count 0 2006.285.22:12:18.60#ibcon#enter sib2, iclass 30, count 0 2006.285.22:12:18.60#ibcon#flushed, iclass 30, count 0 2006.285.22:12:18.60#ibcon#about to write, iclass 30, count 0 2006.285.22:12:18.60#ibcon#wrote, iclass 30, count 0 2006.285.22:12:18.60#ibcon#about to read 3, iclass 30, count 0 2006.285.22:12:18.62#ibcon#read 3, iclass 30, count 0 2006.285.22:12:18.62#ibcon#about to read 4, iclass 30, count 0 2006.285.22:12:18.62#ibcon#read 4, iclass 30, count 0 2006.285.22:12:18.62#ibcon#about to read 5, iclass 30, count 0 2006.285.22:12:18.62#ibcon#read 5, iclass 30, count 0 2006.285.22:12:18.62#ibcon#about to read 6, iclass 30, count 0 2006.285.22:12:18.62#ibcon#read 6, iclass 30, count 0 2006.285.22:12:18.62#ibcon#end of sib2, iclass 30, count 0 2006.285.22:12:18.62#ibcon#*mode == 0, iclass 30, count 0 2006.285.22:12:18.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.22:12:18.62#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.22:12:18.62#ibcon#*before write, iclass 30, count 0 2006.285.22:12:18.62#ibcon#enter sib2, iclass 30, count 0 2006.285.22:12:18.62#ibcon#flushed, iclass 30, count 0 2006.285.22:12:18.62#ibcon#about to write, iclass 30, count 0 2006.285.22:12:18.62#ibcon#wrote, iclass 30, count 0 2006.285.22:12:18.62#ibcon#about to read 3, iclass 30, count 0 2006.285.22:12:18.66#ibcon#read 3, iclass 30, count 0 2006.285.22:12:18.66#ibcon#about to read 4, iclass 30, count 0 2006.285.22:12:18.66#ibcon#read 4, iclass 30, count 0 2006.285.22:12:18.66#ibcon#about to read 5, iclass 30, count 0 2006.285.22:12:18.66#ibcon#read 5, iclass 30, count 0 2006.285.22:12:18.66#ibcon#about to read 6, iclass 30, count 0 2006.285.22:12:18.66#ibcon#read 6, iclass 30, count 0 2006.285.22:12:18.66#ibcon#end of sib2, iclass 30, count 0 2006.285.22:12:18.66#ibcon#*after write, iclass 30, count 0 2006.285.22:12:18.66#ibcon#*before return 0, iclass 30, count 0 2006.285.22:12:18.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:12:18.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:12:18.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.22:12:18.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.22:12:18.66$vck44/vb=5,4 2006.285.22:12:18.66#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.22:12:18.66#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.22:12:18.66#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:18.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:12:18.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:12:18.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:12:18.72#ibcon#enter wrdev, iclass 32, count 2 2006.285.22:12:18.72#ibcon#first serial, iclass 32, count 2 2006.285.22:12:18.72#ibcon#enter sib2, iclass 32, count 2 2006.285.22:12:18.72#ibcon#flushed, iclass 32, count 2 2006.285.22:12:18.72#ibcon#about to write, iclass 32, count 2 2006.285.22:12:18.72#ibcon#wrote, iclass 32, count 2 2006.285.22:12:18.72#ibcon#about to read 3, iclass 32, count 2 2006.285.22:12:18.74#ibcon#read 3, iclass 32, count 2 2006.285.22:12:18.74#ibcon#about to read 4, iclass 32, count 2 2006.285.22:12:18.74#ibcon#read 4, iclass 32, count 2 2006.285.22:12:18.74#ibcon#about to read 5, iclass 32, count 2 2006.285.22:12:18.74#ibcon#read 5, iclass 32, count 2 2006.285.22:12:18.74#ibcon#about to read 6, iclass 32, count 2 2006.285.22:12:18.74#ibcon#read 6, iclass 32, count 2 2006.285.22:12:18.74#ibcon#end of sib2, iclass 32, count 2 2006.285.22:12:18.74#ibcon#*mode == 0, iclass 32, count 2 2006.285.22:12:18.74#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.22:12:18.74#ibcon#[27=AT05-04\r\n] 2006.285.22:12:18.74#ibcon#*before write, iclass 32, count 2 2006.285.22:12:18.74#ibcon#enter sib2, iclass 32, count 2 2006.285.22:12:18.74#ibcon#flushed, iclass 32, count 2 2006.285.22:12:18.74#ibcon#about to write, iclass 32, count 2 2006.285.22:12:18.74#ibcon#wrote, iclass 32, count 2 2006.285.22:12:18.74#ibcon#about to read 3, iclass 32, count 2 2006.285.22:12:18.77#ibcon#read 3, iclass 32, count 2 2006.285.22:12:18.77#ibcon#about to read 4, iclass 32, count 2 2006.285.22:12:18.77#ibcon#read 4, iclass 32, count 2 2006.285.22:12:18.77#ibcon#about to read 5, iclass 32, count 2 2006.285.22:12:18.77#ibcon#read 5, iclass 32, count 2 2006.285.22:12:18.77#ibcon#about to read 6, iclass 32, count 2 2006.285.22:12:18.77#ibcon#read 6, iclass 32, count 2 2006.285.22:12:18.77#ibcon#end of sib2, iclass 32, count 2 2006.285.22:12:18.77#ibcon#*after write, iclass 32, count 2 2006.285.22:12:18.77#ibcon#*before return 0, iclass 32, count 2 2006.285.22:12:18.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:12:18.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:12:18.77#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.22:12:18.77#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:18.77#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:12:18.89#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:12:18.89#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:12:18.89#ibcon#enter wrdev, iclass 32, count 0 2006.285.22:12:18.89#ibcon#first serial, iclass 32, count 0 2006.285.22:12:18.89#ibcon#enter sib2, iclass 32, count 0 2006.285.22:12:18.89#ibcon#flushed, iclass 32, count 0 2006.285.22:12:18.89#ibcon#about to write, iclass 32, count 0 2006.285.22:12:18.89#ibcon#wrote, iclass 32, count 0 2006.285.22:12:18.89#ibcon#about to read 3, iclass 32, count 0 2006.285.22:12:18.91#ibcon#read 3, iclass 32, count 0 2006.285.22:12:18.91#ibcon#about to read 4, iclass 32, count 0 2006.285.22:12:18.91#ibcon#read 4, iclass 32, count 0 2006.285.22:12:18.91#ibcon#about to read 5, iclass 32, count 0 2006.285.22:12:18.91#ibcon#read 5, iclass 32, count 0 2006.285.22:12:18.91#ibcon#about to read 6, iclass 32, count 0 2006.285.22:12:18.91#ibcon#read 6, iclass 32, count 0 2006.285.22:12:18.91#ibcon#end of sib2, iclass 32, count 0 2006.285.22:12:18.91#ibcon#*mode == 0, iclass 32, count 0 2006.285.22:12:18.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.22:12:18.91#ibcon#[27=USB\r\n] 2006.285.22:12:18.91#ibcon#*before write, iclass 32, count 0 2006.285.22:12:18.91#ibcon#enter sib2, iclass 32, count 0 2006.285.22:12:18.91#ibcon#flushed, iclass 32, count 0 2006.285.22:12:18.91#ibcon#about to write, iclass 32, count 0 2006.285.22:12:18.91#ibcon#wrote, iclass 32, count 0 2006.285.22:12:18.91#ibcon#about to read 3, iclass 32, count 0 2006.285.22:12:18.94#ibcon#read 3, iclass 32, count 0 2006.285.22:12:18.94#ibcon#about to read 4, iclass 32, count 0 2006.285.22:12:18.94#ibcon#read 4, iclass 32, count 0 2006.285.22:12:18.94#ibcon#about to read 5, iclass 32, count 0 2006.285.22:12:18.94#ibcon#read 5, iclass 32, count 0 2006.285.22:12:18.94#ibcon#about to read 6, iclass 32, count 0 2006.285.22:12:18.94#ibcon#read 6, iclass 32, count 0 2006.285.22:12:18.94#ibcon#end of sib2, iclass 32, count 0 2006.285.22:12:18.94#ibcon#*after write, iclass 32, count 0 2006.285.22:12:18.94#ibcon#*before return 0, iclass 32, count 0 2006.285.22:12:18.94#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:12:18.94#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:12:18.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.22:12:18.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.22:12:18.94$vck44/vblo=6,719.99 2006.285.22:12:18.94#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.22:12:18.94#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.22:12:18.94#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:18.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:12:18.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:12:18.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:12:18.94#ibcon#enter wrdev, iclass 34, count 0 2006.285.22:12:18.94#ibcon#first serial, iclass 34, count 0 2006.285.22:12:18.94#ibcon#enter sib2, iclass 34, count 0 2006.285.22:12:18.94#ibcon#flushed, iclass 34, count 0 2006.285.22:12:18.94#ibcon#about to write, iclass 34, count 0 2006.285.22:12:18.94#ibcon#wrote, iclass 34, count 0 2006.285.22:12:18.94#ibcon#about to read 3, iclass 34, count 0 2006.285.22:12:18.96#ibcon#read 3, iclass 34, count 0 2006.285.22:12:18.99#ibcon#about to read 4, iclass 34, count 0 2006.285.22:12:18.99#ibcon#read 4, iclass 34, count 0 2006.285.22:12:18.99#ibcon#about to read 5, iclass 34, count 0 2006.285.22:12:18.99#ibcon#read 5, iclass 34, count 0 2006.285.22:12:18.99#ibcon#about to read 6, iclass 34, count 0 2006.285.22:12:18.99#ibcon#read 6, iclass 34, count 0 2006.285.22:12:18.99#ibcon#end of sib2, iclass 34, count 0 2006.285.22:12:18.99#ibcon#*mode == 0, iclass 34, count 0 2006.285.22:12:18.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.22:12:18.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.22:12:18.99#ibcon#*before write, iclass 34, count 0 2006.285.22:12:18.99#ibcon#enter sib2, iclass 34, count 0 2006.285.22:12:18.99#ibcon#flushed, iclass 34, count 0 2006.285.22:12:18.99#ibcon#about to write, iclass 34, count 0 2006.285.22:12:18.99#ibcon#wrote, iclass 34, count 0 2006.285.22:12:18.99#ibcon#about to read 3, iclass 34, count 0 2006.285.22:12:19.03#ibcon#read 3, iclass 34, count 0 2006.285.22:12:19.03#ibcon#about to read 4, iclass 34, count 0 2006.285.22:12:19.03#ibcon#read 4, iclass 34, count 0 2006.285.22:12:19.03#ibcon#about to read 5, iclass 34, count 0 2006.285.22:12:19.03#ibcon#read 5, iclass 34, count 0 2006.285.22:12:19.03#ibcon#about to read 6, iclass 34, count 0 2006.285.22:12:19.03#ibcon#read 6, iclass 34, count 0 2006.285.22:12:19.03#ibcon#end of sib2, iclass 34, count 0 2006.285.22:12:19.03#ibcon#*after write, iclass 34, count 0 2006.285.22:12:19.03#ibcon#*before return 0, iclass 34, count 0 2006.285.22:12:19.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:12:19.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:12:19.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.22:12:19.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.22:12:19.03$vck44/vb=6,3 2006.285.22:12:19.03#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.22:12:19.03#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.22:12:19.03#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:19.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:12:19.06#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:12:19.06#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:12:19.06#ibcon#enter wrdev, iclass 36, count 2 2006.285.22:12:19.06#ibcon#first serial, iclass 36, count 2 2006.285.22:12:19.06#ibcon#enter sib2, iclass 36, count 2 2006.285.22:12:19.06#ibcon#flushed, iclass 36, count 2 2006.285.22:12:19.06#ibcon#about to write, iclass 36, count 2 2006.285.22:12:19.06#ibcon#wrote, iclass 36, count 2 2006.285.22:12:19.06#ibcon#about to read 3, iclass 36, count 2 2006.285.22:12:19.08#ibcon#read 3, iclass 36, count 2 2006.285.22:12:19.08#ibcon#about to read 4, iclass 36, count 2 2006.285.22:12:19.08#ibcon#read 4, iclass 36, count 2 2006.285.22:12:19.08#ibcon#about to read 5, iclass 36, count 2 2006.285.22:12:19.08#ibcon#read 5, iclass 36, count 2 2006.285.22:12:19.08#ibcon#about to read 6, iclass 36, count 2 2006.285.22:12:19.08#ibcon#read 6, iclass 36, count 2 2006.285.22:12:19.08#ibcon#end of sib2, iclass 36, count 2 2006.285.22:12:19.08#ibcon#*mode == 0, iclass 36, count 2 2006.285.22:12:19.08#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.22:12:19.08#ibcon#[27=AT06-03\r\n] 2006.285.22:12:19.08#ibcon#*before write, iclass 36, count 2 2006.285.22:12:19.08#ibcon#enter sib2, iclass 36, count 2 2006.285.22:12:19.08#ibcon#flushed, iclass 36, count 2 2006.285.22:12:19.08#ibcon#about to write, iclass 36, count 2 2006.285.22:12:19.08#ibcon#wrote, iclass 36, count 2 2006.285.22:12:19.08#ibcon#about to read 3, iclass 36, count 2 2006.285.22:12:19.11#ibcon#read 3, iclass 36, count 2 2006.285.22:12:19.11#ibcon#about to read 4, iclass 36, count 2 2006.285.22:12:19.11#ibcon#read 4, iclass 36, count 2 2006.285.22:12:19.11#ibcon#about to read 5, iclass 36, count 2 2006.285.22:12:19.11#ibcon#read 5, iclass 36, count 2 2006.285.22:12:19.11#ibcon#about to read 6, iclass 36, count 2 2006.285.22:12:19.11#ibcon#read 6, iclass 36, count 2 2006.285.22:12:19.11#ibcon#end of sib2, iclass 36, count 2 2006.285.22:12:19.11#ibcon#*after write, iclass 36, count 2 2006.285.22:12:19.11#ibcon#*before return 0, iclass 36, count 2 2006.285.22:12:19.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:12:19.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:12:19.11#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.22:12:19.11#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:19.11#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:12:19.23#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:12:19.23#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:12:19.23#ibcon#enter wrdev, iclass 36, count 0 2006.285.22:12:19.23#ibcon#first serial, iclass 36, count 0 2006.285.22:12:19.23#ibcon#enter sib2, iclass 36, count 0 2006.285.22:12:19.23#ibcon#flushed, iclass 36, count 0 2006.285.22:12:19.23#ibcon#about to write, iclass 36, count 0 2006.285.22:12:19.23#ibcon#wrote, iclass 36, count 0 2006.285.22:12:19.23#ibcon#about to read 3, iclass 36, count 0 2006.285.22:12:19.25#ibcon#read 3, iclass 36, count 0 2006.285.22:12:19.25#ibcon#about to read 4, iclass 36, count 0 2006.285.22:12:19.25#ibcon#read 4, iclass 36, count 0 2006.285.22:12:19.25#ibcon#about to read 5, iclass 36, count 0 2006.285.22:12:19.25#ibcon#read 5, iclass 36, count 0 2006.285.22:12:19.25#ibcon#about to read 6, iclass 36, count 0 2006.285.22:12:19.25#ibcon#read 6, iclass 36, count 0 2006.285.22:12:19.25#ibcon#end of sib2, iclass 36, count 0 2006.285.22:12:19.25#ibcon#*mode == 0, iclass 36, count 0 2006.285.22:12:19.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.22:12:19.25#ibcon#[27=USB\r\n] 2006.285.22:12:19.25#ibcon#*before write, iclass 36, count 0 2006.285.22:12:19.25#ibcon#enter sib2, iclass 36, count 0 2006.285.22:12:19.25#ibcon#flushed, iclass 36, count 0 2006.285.22:12:19.25#ibcon#about to write, iclass 36, count 0 2006.285.22:12:19.25#ibcon#wrote, iclass 36, count 0 2006.285.22:12:19.25#ibcon#about to read 3, iclass 36, count 0 2006.285.22:12:19.28#ibcon#read 3, iclass 36, count 0 2006.285.22:12:19.28#ibcon#about to read 4, iclass 36, count 0 2006.285.22:12:19.28#ibcon#read 4, iclass 36, count 0 2006.285.22:12:19.28#ibcon#about to read 5, iclass 36, count 0 2006.285.22:12:19.28#ibcon#read 5, iclass 36, count 0 2006.285.22:12:19.28#ibcon#about to read 6, iclass 36, count 0 2006.285.22:12:19.28#ibcon#read 6, iclass 36, count 0 2006.285.22:12:19.28#ibcon#end of sib2, iclass 36, count 0 2006.285.22:12:19.28#ibcon#*after write, iclass 36, count 0 2006.285.22:12:19.28#ibcon#*before return 0, iclass 36, count 0 2006.285.22:12:19.28#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:12:19.28#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:12:19.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.22:12:19.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.22:12:19.28$vck44/vblo=7,734.99 2006.285.22:12:19.28#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.22:12:19.28#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.22:12:19.28#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:19.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:12:19.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:12:19.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:12:19.28#ibcon#enter wrdev, iclass 38, count 0 2006.285.22:12:19.28#ibcon#first serial, iclass 38, count 0 2006.285.22:12:19.28#ibcon#enter sib2, iclass 38, count 0 2006.285.22:12:19.28#ibcon#flushed, iclass 38, count 0 2006.285.22:12:19.28#ibcon#about to write, iclass 38, count 0 2006.285.22:12:19.28#ibcon#wrote, iclass 38, count 0 2006.285.22:12:19.28#ibcon#about to read 3, iclass 38, count 0 2006.285.22:12:19.30#ibcon#read 3, iclass 38, count 0 2006.285.22:12:19.30#ibcon#about to read 4, iclass 38, count 0 2006.285.22:12:19.30#ibcon#read 4, iclass 38, count 0 2006.285.22:12:19.30#ibcon#about to read 5, iclass 38, count 0 2006.285.22:12:19.30#ibcon#read 5, iclass 38, count 0 2006.285.22:12:19.30#ibcon#about to read 6, iclass 38, count 0 2006.285.22:12:19.30#ibcon#read 6, iclass 38, count 0 2006.285.22:12:19.30#ibcon#end of sib2, iclass 38, count 0 2006.285.22:12:19.30#ibcon#*mode == 0, iclass 38, count 0 2006.285.22:12:19.30#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.22:12:19.30#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.22:12:19.30#ibcon#*before write, iclass 38, count 0 2006.285.22:12:19.30#ibcon#enter sib2, iclass 38, count 0 2006.285.22:12:19.30#ibcon#flushed, iclass 38, count 0 2006.285.22:12:19.30#ibcon#about to write, iclass 38, count 0 2006.285.22:12:19.30#ibcon#wrote, iclass 38, count 0 2006.285.22:12:19.30#ibcon#about to read 3, iclass 38, count 0 2006.285.22:12:19.34#ibcon#read 3, iclass 38, count 0 2006.285.22:12:19.34#ibcon#about to read 4, iclass 38, count 0 2006.285.22:12:19.34#ibcon#read 4, iclass 38, count 0 2006.285.22:12:19.34#ibcon#about to read 5, iclass 38, count 0 2006.285.22:12:19.34#ibcon#read 5, iclass 38, count 0 2006.285.22:12:19.34#ibcon#about to read 6, iclass 38, count 0 2006.285.22:12:19.34#ibcon#read 6, iclass 38, count 0 2006.285.22:12:19.34#ibcon#end of sib2, iclass 38, count 0 2006.285.22:12:19.34#ibcon#*after write, iclass 38, count 0 2006.285.22:12:19.34#ibcon#*before return 0, iclass 38, count 0 2006.285.22:12:19.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:12:19.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:12:19.34#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.22:12:19.34#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.22:12:19.34$vck44/vb=7,4 2006.285.22:12:19.34#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.22:12:19.34#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.22:12:19.34#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:19.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:12:19.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:12:19.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:12:19.40#ibcon#enter wrdev, iclass 40, count 2 2006.285.22:12:19.40#ibcon#first serial, iclass 40, count 2 2006.285.22:12:19.40#ibcon#enter sib2, iclass 40, count 2 2006.285.22:12:19.40#ibcon#flushed, iclass 40, count 2 2006.285.22:12:19.40#ibcon#about to write, iclass 40, count 2 2006.285.22:12:19.40#ibcon#wrote, iclass 40, count 2 2006.285.22:12:19.40#ibcon#about to read 3, iclass 40, count 2 2006.285.22:12:19.42#ibcon#read 3, iclass 40, count 2 2006.285.22:12:19.42#ibcon#about to read 4, iclass 40, count 2 2006.285.22:12:19.42#ibcon#read 4, iclass 40, count 2 2006.285.22:12:19.42#ibcon#about to read 5, iclass 40, count 2 2006.285.22:12:19.42#ibcon#read 5, iclass 40, count 2 2006.285.22:12:19.42#ibcon#about to read 6, iclass 40, count 2 2006.285.22:12:19.42#ibcon#read 6, iclass 40, count 2 2006.285.22:12:19.42#ibcon#end of sib2, iclass 40, count 2 2006.285.22:12:19.42#ibcon#*mode == 0, iclass 40, count 2 2006.285.22:12:19.42#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.22:12:19.42#ibcon#[27=AT07-04\r\n] 2006.285.22:12:19.42#ibcon#*before write, iclass 40, count 2 2006.285.22:12:19.42#ibcon#enter sib2, iclass 40, count 2 2006.285.22:12:19.42#ibcon#flushed, iclass 40, count 2 2006.285.22:12:19.42#ibcon#about to write, iclass 40, count 2 2006.285.22:12:19.42#ibcon#wrote, iclass 40, count 2 2006.285.22:12:19.42#ibcon#about to read 3, iclass 40, count 2 2006.285.22:12:19.45#ibcon#read 3, iclass 40, count 2 2006.285.22:12:19.45#ibcon#about to read 4, iclass 40, count 2 2006.285.22:12:19.45#ibcon#read 4, iclass 40, count 2 2006.285.22:12:19.45#ibcon#about to read 5, iclass 40, count 2 2006.285.22:12:19.45#ibcon#read 5, iclass 40, count 2 2006.285.22:12:19.45#ibcon#about to read 6, iclass 40, count 2 2006.285.22:12:19.45#ibcon#read 6, iclass 40, count 2 2006.285.22:12:19.45#ibcon#end of sib2, iclass 40, count 2 2006.285.22:12:19.45#ibcon#*after write, iclass 40, count 2 2006.285.22:12:19.45#ibcon#*before return 0, iclass 40, count 2 2006.285.22:12:19.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:12:19.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:12:19.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.22:12:19.45#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:19.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:12:19.57#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:12:19.57#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:12:19.57#ibcon#enter wrdev, iclass 40, count 0 2006.285.22:12:19.57#ibcon#first serial, iclass 40, count 0 2006.285.22:12:19.57#ibcon#enter sib2, iclass 40, count 0 2006.285.22:12:19.57#ibcon#flushed, iclass 40, count 0 2006.285.22:12:19.57#ibcon#about to write, iclass 40, count 0 2006.285.22:12:19.57#ibcon#wrote, iclass 40, count 0 2006.285.22:12:19.57#ibcon#about to read 3, iclass 40, count 0 2006.285.22:12:19.59#ibcon#read 3, iclass 40, count 0 2006.285.22:12:19.59#ibcon#about to read 4, iclass 40, count 0 2006.285.22:12:19.59#ibcon#read 4, iclass 40, count 0 2006.285.22:12:19.59#ibcon#about to read 5, iclass 40, count 0 2006.285.22:12:19.59#ibcon#read 5, iclass 40, count 0 2006.285.22:12:19.59#ibcon#about to read 6, iclass 40, count 0 2006.285.22:12:19.59#ibcon#read 6, iclass 40, count 0 2006.285.22:12:19.59#ibcon#end of sib2, iclass 40, count 0 2006.285.22:12:19.59#ibcon#*mode == 0, iclass 40, count 0 2006.285.22:12:19.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.22:12:19.59#ibcon#[27=USB\r\n] 2006.285.22:12:19.59#ibcon#*before write, iclass 40, count 0 2006.285.22:12:19.59#ibcon#enter sib2, iclass 40, count 0 2006.285.22:12:19.59#ibcon#flushed, iclass 40, count 0 2006.285.22:12:19.59#ibcon#about to write, iclass 40, count 0 2006.285.22:12:19.59#ibcon#wrote, iclass 40, count 0 2006.285.22:12:19.59#ibcon#about to read 3, iclass 40, count 0 2006.285.22:12:19.62#ibcon#read 3, iclass 40, count 0 2006.285.22:12:19.62#ibcon#about to read 4, iclass 40, count 0 2006.285.22:12:19.62#ibcon#read 4, iclass 40, count 0 2006.285.22:12:19.62#ibcon#about to read 5, iclass 40, count 0 2006.285.22:12:19.62#ibcon#read 5, iclass 40, count 0 2006.285.22:12:19.62#ibcon#about to read 6, iclass 40, count 0 2006.285.22:12:19.62#ibcon#read 6, iclass 40, count 0 2006.285.22:12:19.62#ibcon#end of sib2, iclass 40, count 0 2006.285.22:12:19.62#ibcon#*after write, iclass 40, count 0 2006.285.22:12:19.62#ibcon#*before return 0, iclass 40, count 0 2006.285.22:12:19.62#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:12:19.62#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:12:19.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.22:12:19.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.22:12:19.62$vck44/vblo=8,744.99 2006.285.22:12:19.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.22:12:19.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.22:12:19.62#ibcon#ireg 17 cls_cnt 0 2006.285.22:12:19.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:12:19.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:12:19.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:12:19.62#ibcon#enter wrdev, iclass 4, count 0 2006.285.22:12:19.62#ibcon#first serial, iclass 4, count 0 2006.285.22:12:19.62#ibcon#enter sib2, iclass 4, count 0 2006.285.22:12:19.62#ibcon#flushed, iclass 4, count 0 2006.285.22:12:19.62#ibcon#about to write, iclass 4, count 0 2006.285.22:12:19.62#ibcon#wrote, iclass 4, count 0 2006.285.22:12:19.62#ibcon#about to read 3, iclass 4, count 0 2006.285.22:12:19.64#ibcon#read 3, iclass 4, count 0 2006.285.22:12:19.64#ibcon#about to read 4, iclass 4, count 0 2006.285.22:12:19.64#ibcon#read 4, iclass 4, count 0 2006.285.22:12:19.64#ibcon#about to read 5, iclass 4, count 0 2006.285.22:12:19.64#ibcon#read 5, iclass 4, count 0 2006.285.22:12:19.64#ibcon#about to read 6, iclass 4, count 0 2006.285.22:12:19.64#ibcon#read 6, iclass 4, count 0 2006.285.22:12:19.64#ibcon#end of sib2, iclass 4, count 0 2006.285.22:12:19.64#ibcon#*mode == 0, iclass 4, count 0 2006.285.22:12:19.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.22:12:19.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.22:12:19.64#ibcon#*before write, iclass 4, count 0 2006.285.22:12:19.64#ibcon#enter sib2, iclass 4, count 0 2006.285.22:12:19.64#ibcon#flushed, iclass 4, count 0 2006.285.22:12:19.64#ibcon#about to write, iclass 4, count 0 2006.285.22:12:19.64#ibcon#wrote, iclass 4, count 0 2006.285.22:12:19.64#ibcon#about to read 3, iclass 4, count 0 2006.285.22:12:19.68#ibcon#read 3, iclass 4, count 0 2006.285.22:12:19.68#ibcon#about to read 4, iclass 4, count 0 2006.285.22:12:19.68#ibcon#read 4, iclass 4, count 0 2006.285.22:12:19.68#ibcon#about to read 5, iclass 4, count 0 2006.285.22:12:19.68#ibcon#read 5, iclass 4, count 0 2006.285.22:12:19.68#ibcon#about to read 6, iclass 4, count 0 2006.285.22:12:19.68#ibcon#read 6, iclass 4, count 0 2006.285.22:12:19.68#ibcon#end of sib2, iclass 4, count 0 2006.285.22:12:19.68#ibcon#*after write, iclass 4, count 0 2006.285.22:12:19.68#ibcon#*before return 0, iclass 4, count 0 2006.285.22:12:19.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:12:19.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:12:19.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.22:12:19.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.22:12:19.68$vck44/vb=8,4 2006.285.22:12:19.68#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.22:12:19.68#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.22:12:19.68#ibcon#ireg 11 cls_cnt 2 2006.285.22:12:19.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:12:19.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:12:19.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:12:19.74#ibcon#enter wrdev, iclass 6, count 2 2006.285.22:12:19.74#ibcon#first serial, iclass 6, count 2 2006.285.22:12:19.74#ibcon#enter sib2, iclass 6, count 2 2006.285.22:12:19.74#ibcon#flushed, iclass 6, count 2 2006.285.22:12:19.74#ibcon#about to write, iclass 6, count 2 2006.285.22:12:19.74#ibcon#wrote, iclass 6, count 2 2006.285.22:12:19.74#ibcon#about to read 3, iclass 6, count 2 2006.285.22:12:19.76#ibcon#read 3, iclass 6, count 2 2006.285.22:12:19.76#ibcon#about to read 4, iclass 6, count 2 2006.285.22:12:19.76#ibcon#read 4, iclass 6, count 2 2006.285.22:12:19.76#ibcon#about to read 5, iclass 6, count 2 2006.285.22:12:19.76#ibcon#read 5, iclass 6, count 2 2006.285.22:12:19.76#ibcon#about to read 6, iclass 6, count 2 2006.285.22:12:19.76#ibcon#read 6, iclass 6, count 2 2006.285.22:12:19.76#ibcon#end of sib2, iclass 6, count 2 2006.285.22:12:19.76#ibcon#*mode == 0, iclass 6, count 2 2006.285.22:12:19.76#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.22:12:19.76#ibcon#[27=AT08-04\r\n] 2006.285.22:12:19.76#ibcon#*before write, iclass 6, count 2 2006.285.22:12:19.76#ibcon#enter sib2, iclass 6, count 2 2006.285.22:12:19.76#ibcon#flushed, iclass 6, count 2 2006.285.22:12:19.76#ibcon#about to write, iclass 6, count 2 2006.285.22:12:19.76#ibcon#wrote, iclass 6, count 2 2006.285.22:12:19.76#ibcon#about to read 3, iclass 6, count 2 2006.285.22:12:19.79#ibcon#read 3, iclass 6, count 2 2006.285.22:12:19.79#ibcon#about to read 4, iclass 6, count 2 2006.285.22:12:19.79#ibcon#read 4, iclass 6, count 2 2006.285.22:12:19.79#ibcon#about to read 5, iclass 6, count 2 2006.285.22:12:19.79#ibcon#read 5, iclass 6, count 2 2006.285.22:12:19.79#ibcon#about to read 6, iclass 6, count 2 2006.285.22:12:19.79#ibcon#read 6, iclass 6, count 2 2006.285.22:12:19.79#ibcon#end of sib2, iclass 6, count 2 2006.285.22:12:19.79#ibcon#*after write, iclass 6, count 2 2006.285.22:12:19.79#ibcon#*before return 0, iclass 6, count 2 2006.285.22:12:19.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:12:19.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:12:19.79#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.22:12:19.79#ibcon#ireg 7 cls_cnt 0 2006.285.22:12:19.79#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:12:19.91#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:12:19.91#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:12:19.91#ibcon#enter wrdev, iclass 6, count 0 2006.285.22:12:19.91#ibcon#first serial, iclass 6, count 0 2006.285.22:12:19.91#ibcon#enter sib2, iclass 6, count 0 2006.285.22:12:19.91#ibcon#flushed, iclass 6, count 0 2006.285.22:12:19.91#ibcon#about to write, iclass 6, count 0 2006.285.22:12:19.91#ibcon#wrote, iclass 6, count 0 2006.285.22:12:19.91#ibcon#about to read 3, iclass 6, count 0 2006.285.22:12:19.93#ibcon#read 3, iclass 6, count 0 2006.285.22:12:19.93#ibcon#about to read 4, iclass 6, count 0 2006.285.22:12:19.93#ibcon#read 4, iclass 6, count 0 2006.285.22:12:19.93#ibcon#about to read 5, iclass 6, count 0 2006.285.22:12:19.93#ibcon#read 5, iclass 6, count 0 2006.285.22:12:19.93#ibcon#about to read 6, iclass 6, count 0 2006.285.22:12:19.93#ibcon#read 6, iclass 6, count 0 2006.285.22:12:19.93#ibcon#end of sib2, iclass 6, count 0 2006.285.22:12:19.93#ibcon#*mode == 0, iclass 6, count 0 2006.285.22:12:19.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.22:12:19.93#ibcon#[27=USB\r\n] 2006.285.22:12:19.93#ibcon#*before write, iclass 6, count 0 2006.285.22:12:19.93#ibcon#enter sib2, iclass 6, count 0 2006.285.22:12:19.93#ibcon#flushed, iclass 6, count 0 2006.285.22:12:19.93#ibcon#about to write, iclass 6, count 0 2006.285.22:12:19.93#ibcon#wrote, iclass 6, count 0 2006.285.22:12:19.93#ibcon#about to read 3, iclass 6, count 0 2006.285.22:12:19.96#ibcon#read 3, iclass 6, count 0 2006.285.22:12:19.96#ibcon#about to read 4, iclass 6, count 0 2006.285.22:12:19.96#ibcon#read 4, iclass 6, count 0 2006.285.22:12:19.96#ibcon#about to read 5, iclass 6, count 0 2006.285.22:12:19.96#ibcon#read 5, iclass 6, count 0 2006.285.22:12:19.96#ibcon#about to read 6, iclass 6, count 0 2006.285.22:12:19.96#ibcon#read 6, iclass 6, count 0 2006.285.22:12:19.96#ibcon#end of sib2, iclass 6, count 0 2006.285.22:12:19.96#ibcon#*after write, iclass 6, count 0 2006.285.22:12:19.96#ibcon#*before return 0, iclass 6, count 0 2006.285.22:12:19.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:12:19.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:12:19.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.22:12:19.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.22:12:19.96$vck44/vabw=wide 2006.285.22:12:20.04#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.22:12:20.04#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.22:12:20.04#ibcon#ireg 8 cls_cnt 0 2006.285.22:12:20.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:12:20.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:12:20.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:12:20.04#ibcon#enter wrdev, iclass 10, count 0 2006.285.22:12:20.04#ibcon#first serial, iclass 10, count 0 2006.285.22:12:20.04#ibcon#enter sib2, iclass 10, count 0 2006.285.22:12:20.04#ibcon#flushed, iclass 10, count 0 2006.285.22:12:20.04#ibcon#about to write, iclass 10, count 0 2006.285.22:12:20.04#ibcon#wrote, iclass 10, count 0 2006.285.22:12:20.04#ibcon#about to read 3, iclass 10, count 0 2006.285.22:12:20.05#ibcon#read 3, iclass 10, count 0 2006.285.22:12:20.05#ibcon#about to read 4, iclass 10, count 0 2006.285.22:12:20.05#ibcon#read 4, iclass 10, count 0 2006.285.22:12:20.05#ibcon#about to read 5, iclass 10, count 0 2006.285.22:12:20.05#ibcon#read 5, iclass 10, count 0 2006.285.22:12:20.05#ibcon#about to read 6, iclass 10, count 0 2006.285.22:12:20.05#ibcon#read 6, iclass 10, count 0 2006.285.22:12:20.05#ibcon#end of sib2, iclass 10, count 0 2006.285.22:12:20.05#ibcon#*mode == 0, iclass 10, count 0 2006.285.22:12:20.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.22:12:20.05#ibcon#[25=BW32\r\n] 2006.285.22:12:20.05#ibcon#*before write, iclass 10, count 0 2006.285.22:12:20.05#ibcon#enter sib2, iclass 10, count 0 2006.285.22:12:20.05#ibcon#flushed, iclass 10, count 0 2006.285.22:12:20.05#ibcon#about to write, iclass 10, count 0 2006.285.22:12:20.05#ibcon#wrote, iclass 10, count 0 2006.285.22:12:20.05#ibcon#about to read 3, iclass 10, count 0 2006.285.22:12:20.08#ibcon#read 3, iclass 10, count 0 2006.285.22:12:20.08#ibcon#about to read 4, iclass 10, count 0 2006.285.22:12:20.08#ibcon#read 4, iclass 10, count 0 2006.285.22:12:20.08#ibcon#about to read 5, iclass 10, count 0 2006.285.22:12:20.08#ibcon#read 5, iclass 10, count 0 2006.285.22:12:20.08#ibcon#about to read 6, iclass 10, count 0 2006.285.22:12:20.08#ibcon#read 6, iclass 10, count 0 2006.285.22:12:20.08#ibcon#end of sib2, iclass 10, count 0 2006.285.22:12:20.08#ibcon#*after write, iclass 10, count 0 2006.285.22:12:20.08#ibcon#*before return 0, iclass 10, count 0 2006.285.22:12:20.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:12:20.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:12:20.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.22:12:20.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.22:12:20.08$vck44/vbbw=wide 2006.285.22:12:20.08#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.22:12:20.08#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.22:12:20.08#ibcon#ireg 8 cls_cnt 0 2006.285.22:12:20.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:12:20.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:12:20.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:12:20.08#ibcon#enter wrdev, iclass 12, count 0 2006.285.22:12:20.08#ibcon#first serial, iclass 12, count 0 2006.285.22:12:20.08#ibcon#enter sib2, iclass 12, count 0 2006.285.22:12:20.08#ibcon#flushed, iclass 12, count 0 2006.285.22:12:20.08#ibcon#about to write, iclass 12, count 0 2006.285.22:12:20.08#ibcon#wrote, iclass 12, count 0 2006.285.22:12:20.08#ibcon#about to read 3, iclass 12, count 0 2006.285.22:12:20.10#ibcon#read 3, iclass 12, count 0 2006.285.22:12:20.10#ibcon#about to read 4, iclass 12, count 0 2006.285.22:12:20.10#ibcon#read 4, iclass 12, count 0 2006.285.22:12:20.10#ibcon#about to read 5, iclass 12, count 0 2006.285.22:12:20.10#ibcon#read 5, iclass 12, count 0 2006.285.22:12:20.10#ibcon#about to read 6, iclass 12, count 0 2006.285.22:12:20.10#ibcon#read 6, iclass 12, count 0 2006.285.22:12:20.10#ibcon#end of sib2, iclass 12, count 0 2006.285.22:12:20.10#ibcon#*mode == 0, iclass 12, count 0 2006.285.22:12:20.10#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.22:12:20.10#ibcon#[27=BW32\r\n] 2006.285.22:12:20.10#ibcon#*before write, iclass 12, count 0 2006.285.22:12:20.10#ibcon#enter sib2, iclass 12, count 0 2006.285.22:12:20.10#ibcon#flushed, iclass 12, count 0 2006.285.22:12:20.10#ibcon#about to write, iclass 12, count 0 2006.285.22:12:20.10#ibcon#wrote, iclass 12, count 0 2006.285.22:12:20.10#ibcon#about to read 3, iclass 12, count 0 2006.285.22:12:20.13#ibcon#read 3, iclass 12, count 0 2006.285.22:12:20.13#ibcon#about to read 4, iclass 12, count 0 2006.285.22:12:20.13#ibcon#read 4, iclass 12, count 0 2006.285.22:12:20.13#ibcon#about to read 5, iclass 12, count 0 2006.285.22:12:20.13#ibcon#read 5, iclass 12, count 0 2006.285.22:12:20.13#ibcon#about to read 6, iclass 12, count 0 2006.285.22:12:20.13#ibcon#read 6, iclass 12, count 0 2006.285.22:12:20.13#ibcon#end of sib2, iclass 12, count 0 2006.285.22:12:20.13#ibcon#*after write, iclass 12, count 0 2006.285.22:12:20.13#ibcon#*before return 0, iclass 12, count 0 2006.285.22:12:20.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:12:20.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:12:20.13#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.22:12:20.13#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.22:12:20.13$setupk4/ifdk4 2006.285.22:12:20.13$ifdk4/lo= 2006.285.22:12:20.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.22:12:20.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.22:12:20.13$ifdk4/patch= 2006.285.22:12:20.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.22:12:20.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.22:12:20.13$setupk4/!*+20s 2006.285.22:12:26.55#abcon#<5=/14 0.4 1.4 16.101001016.1\r\n> 2006.285.22:12:26.57#abcon#{5=INTERFACE CLEAR} 2006.285.22:12:26.63#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:12:33.68$setupk4/"tpicd 2006.285.22:12:33.68$setupk4/echo=off 2006.285.22:12:33.68$setupk4/xlog=off 2006.285.22:12:33.68:!2006.285.22:14:49 2006.285.22:13:01.14#trakl#Source acquired 2006.285.22:13:02.14#flagr#flagr/antenna,acquired 2006.285.22:14:49.00:preob 2006.285.22:14:49.14/onsource/TRACKING 2006.285.22:14:49.14:!2006.285.22:14:59 2006.285.22:14:59.00:"tape 2006.285.22:14:59.00:"st=record 2006.285.22:14:59.00:data_valid=on 2006.285.22:14:59.00:midob 2006.285.22:14:59.14/onsource/TRACKING 2006.285.22:14:59.14/wx/16.21,1016.0,100 2006.285.22:14:59.30/cable/+6.5126E-03 2006.285.22:15:00.39/va/01,07,usb,yes,33,36 2006.285.22:15:00.39/va/02,06,usb,yes,33,34 2006.285.22:15:00.39/va/03,07,usb,yes,33,35 2006.285.22:15:00.39/va/04,06,usb,yes,34,36 2006.285.22:15:00.39/va/05,03,usb,yes,34,34 2006.285.22:15:00.39/va/06,04,usb,yes,30,30 2006.285.22:15:00.39/va/07,04,usb,yes,31,32 2006.285.22:15:00.39/va/08,03,usb,yes,32,38 2006.285.22:15:00.62/valo/01,524.99,yes,locked 2006.285.22:15:00.62/valo/02,534.99,yes,locked 2006.285.22:15:00.62/valo/03,564.99,yes,locked 2006.285.22:15:00.62/valo/04,624.99,yes,locked 2006.285.22:15:00.62/valo/05,734.99,yes,locked 2006.285.22:15:00.62/valo/06,814.99,yes,locked 2006.285.22:15:00.62/valo/07,864.99,yes,locked 2006.285.22:15:00.62/valo/08,884.99,yes,locked 2006.285.22:15:01.71/vb/01,04,usb,yes,30,28 2006.285.22:15:01.71/vb/02,05,usb,yes,28,28 2006.285.22:15:01.71/vb/03,04,usb,yes,29,32 2006.285.22:15:01.71/vb/04,05,usb,yes,29,28 2006.285.22:15:01.71/vb/05,04,usb,yes,26,28 2006.285.22:15:01.71/vb/06,03,usb,yes,37,33 2006.285.22:15:01.71/vb/07,04,usb,yes,30,30 2006.285.22:15:01.71/vb/08,04,usb,yes,27,31 2006.285.22:15:01.94/vblo/01,629.99,yes,locked 2006.285.22:15:01.94/vblo/02,634.99,yes,locked 2006.285.22:15:01.94/vblo/03,649.99,yes,locked 2006.285.22:15:01.94/vblo/04,679.99,yes,locked 2006.285.22:15:01.94/vblo/05,709.99,yes,locked 2006.285.22:15:01.94/vblo/06,719.99,yes,locked 2006.285.22:15:01.94/vblo/07,734.99,yes,locked 2006.285.22:15:01.94/vblo/08,744.99,yes,locked 2006.285.22:15:02.09/vabw/8 2006.285.22:15:02.24/vbbw/8 2006.285.22:15:02.33/xfe/off,on,12.0 2006.285.22:15:02.72/ifatt/23,28,28,28 2006.285.22:15:03.07/fmout-gps/S +2.59E-07 2006.285.22:15:03.09:!2006.285.22:16:49 2006.285.22:16:49.01:data_valid=off 2006.285.22:16:49.01:"et 2006.285.22:16:49.01:!+3s 2006.285.22:16:52.02:"tape 2006.285.22:16:52.02:postob 2006.285.22:16:52.10/cable/+6.5101E-03 2006.285.22:16:52.10/wx/16.32,1016.0,100 2006.285.22:16:53.08/fmout-gps/S +2.65E-07 2006.285.22:16:53.08:scan_name=285-2218,jd0610,60 2006.285.22:16:53.08:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.285.22:16:54.13#flagr#flagr/antenna,new-source 2006.285.22:16:54.13:checkk5 2006.285.22:16:54.50/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:16:54.97/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:16:55.39/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:16:55.87/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:16:56.22/chk_obsdata//k5ts1/T2852214??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.22:16:56.58/chk_obsdata//k5ts2/T2852214??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.22:16:56.99/chk_obsdata//k5ts3/T2852214??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.22:16:57.47/chk_obsdata//k5ts4/T2852214??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.22:16:58.27/k5log//k5ts1_log_newline 2006.285.22:16:59.03/k5log//k5ts2_log_newline 2006.285.22:17:00.19/k5log//k5ts3_log_newline 2006.285.22:17:01.22/k5log//k5ts4_log_newline 2006.285.22:17:01.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:17:01.24:setupk4=1 2006.285.22:17:01.24$setupk4/echo=on 2006.285.22:17:01.24$setupk4/pcalon 2006.285.22:17:01.24$pcalon/"no phase cal control is implemented here 2006.285.22:17:01.25$setupk4/"tpicd=stop 2006.285.22:17:01.25$setupk4/"rec=synch_on 2006.285.22:17:01.25$setupk4/"rec_mode=128 2006.285.22:17:01.25$setupk4/!* 2006.285.22:17:01.25$setupk4/recpk4 2006.285.22:17:01.25$recpk4/recpatch= 2006.285.22:17:01.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:17:01.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:17:01.25$setupk4/vck44 2006.285.22:17:01.25$vck44/valo=1,524.99 2006.285.22:17:01.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.22:17:01.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.22:17:01.25#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:01.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:17:01.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:17:01.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:17:01.25#ibcon#enter wrdev, iclass 20, count 0 2006.285.22:17:01.25#ibcon#first serial, iclass 20, count 0 2006.285.22:17:01.25#ibcon#enter sib2, iclass 20, count 0 2006.285.22:17:01.25#ibcon#flushed, iclass 20, count 0 2006.285.22:17:01.25#ibcon#about to write, iclass 20, count 0 2006.285.22:17:01.25#ibcon#wrote, iclass 20, count 0 2006.285.22:17:01.25#ibcon#about to read 3, iclass 20, count 0 2006.285.22:17:01.27#ibcon#read 3, iclass 20, count 0 2006.285.22:17:01.27#ibcon#about to read 4, iclass 20, count 0 2006.285.22:17:01.27#ibcon#read 4, iclass 20, count 0 2006.285.22:17:01.27#ibcon#about to read 5, iclass 20, count 0 2006.285.22:17:01.27#ibcon#read 5, iclass 20, count 0 2006.285.22:17:01.27#ibcon#about to read 6, iclass 20, count 0 2006.285.22:17:01.27#ibcon#read 6, iclass 20, count 0 2006.285.22:17:01.27#ibcon#end of sib2, iclass 20, count 0 2006.285.22:17:01.27#ibcon#*mode == 0, iclass 20, count 0 2006.285.22:17:01.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.22:17:01.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:17:01.27#ibcon#*before write, iclass 20, count 0 2006.285.22:17:01.27#ibcon#enter sib2, iclass 20, count 0 2006.285.22:17:01.27#ibcon#flushed, iclass 20, count 0 2006.285.22:17:01.27#ibcon#about to write, iclass 20, count 0 2006.285.22:17:01.27#ibcon#wrote, iclass 20, count 0 2006.285.22:17:01.27#ibcon#about to read 3, iclass 20, count 0 2006.285.22:17:01.32#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:17:01.32#ibcon#read 3, iclass 20, count 0 2006.285.22:17:01.32#ibcon#about to read 4, iclass 20, count 0 2006.285.22:17:01.32#ibcon#read 4, iclass 20, count 0 2006.285.22:17:01.32#ibcon#about to read 5, iclass 20, count 0 2006.285.22:17:01.32#ibcon#read 5, iclass 20, count 0 2006.285.22:17:01.32#ibcon#about to read 6, iclass 20, count 0 2006.285.22:17:01.32#ibcon#read 6, iclass 20, count 0 2006.285.22:17:01.32#ibcon#end of sib2, iclass 20, count 0 2006.285.22:17:01.32#ibcon#*after write, iclass 20, count 0 2006.285.22:17:01.32#ibcon#*before return 0, iclass 20, count 0 2006.285.22:17:01.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:17:01.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:17:01.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.22:17:01.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.22:17:01.32$vck44/va=1,7 2006.285.22:17:01.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.22:17:01.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.22:17:01.32#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:01.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:17:01.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:17:01.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:17:01.32#ibcon#enter wrdev, iclass 23, count 2 2006.285.22:17:01.32#ibcon#first serial, iclass 23, count 2 2006.285.22:17:01.32#ibcon#enter sib2, iclass 23, count 2 2006.285.22:17:01.32#ibcon#flushed, iclass 23, count 2 2006.285.22:17:01.32#ibcon#about to write, iclass 23, count 2 2006.285.22:17:01.32#ibcon#wrote, iclass 23, count 2 2006.285.22:17:01.32#ibcon#about to read 3, iclass 23, count 2 2006.285.22:17:01.34#ibcon#read 3, iclass 23, count 2 2006.285.22:17:01.34#ibcon#about to read 4, iclass 23, count 2 2006.285.22:17:01.34#ibcon#read 4, iclass 23, count 2 2006.285.22:17:01.34#ibcon#about to read 5, iclass 23, count 2 2006.285.22:17:01.34#ibcon#read 5, iclass 23, count 2 2006.285.22:17:01.34#ibcon#about to read 6, iclass 23, count 2 2006.285.22:17:01.34#ibcon#read 6, iclass 23, count 2 2006.285.22:17:01.34#ibcon#end of sib2, iclass 23, count 2 2006.285.22:17:01.34#ibcon#*mode == 0, iclass 23, count 2 2006.285.22:17:01.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.22:17:01.34#ibcon#[25=AT01-07\r\n] 2006.285.22:17:01.34#ibcon#*before write, iclass 23, count 2 2006.285.22:17:01.34#ibcon#enter sib2, iclass 23, count 2 2006.285.22:17:01.34#ibcon#flushed, iclass 23, count 2 2006.285.22:17:01.34#ibcon#about to write, iclass 23, count 2 2006.285.22:17:01.34#ibcon#wrote, iclass 23, count 2 2006.285.22:17:01.34#ibcon#about to read 3, iclass 23, count 2 2006.285.22:17:01.37#ibcon#read 3, iclass 23, count 2 2006.285.22:17:01.37#ibcon#about to read 4, iclass 23, count 2 2006.285.22:17:01.37#ibcon#read 4, iclass 23, count 2 2006.285.22:17:01.37#ibcon#about to read 5, iclass 23, count 2 2006.285.22:17:01.37#ibcon#read 5, iclass 23, count 2 2006.285.22:17:01.37#ibcon#about to read 6, iclass 23, count 2 2006.285.22:17:01.37#ibcon#read 6, iclass 23, count 2 2006.285.22:17:01.37#ibcon#end of sib2, iclass 23, count 2 2006.285.22:17:01.37#ibcon#*after write, iclass 23, count 2 2006.285.22:17:01.37#ibcon#*before return 0, iclass 23, count 2 2006.285.22:17:01.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:17:01.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:17:01.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.22:17:01.37#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:01.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:17:01.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:17:01.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:17:01.49#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:17:01.49#ibcon#first serial, iclass 23, count 0 2006.285.22:17:01.49#ibcon#enter sib2, iclass 23, count 0 2006.285.22:17:01.49#ibcon#flushed, iclass 23, count 0 2006.285.22:17:01.49#ibcon#about to write, iclass 23, count 0 2006.285.22:17:01.49#ibcon#wrote, iclass 23, count 0 2006.285.22:17:01.49#ibcon#about to read 3, iclass 23, count 0 2006.285.22:17:01.51#ibcon#read 3, iclass 23, count 0 2006.285.22:17:01.51#ibcon#about to read 4, iclass 23, count 0 2006.285.22:17:01.51#ibcon#read 4, iclass 23, count 0 2006.285.22:17:01.51#ibcon#about to read 5, iclass 23, count 0 2006.285.22:17:01.51#ibcon#read 5, iclass 23, count 0 2006.285.22:17:01.51#ibcon#about to read 6, iclass 23, count 0 2006.285.22:17:01.51#ibcon#read 6, iclass 23, count 0 2006.285.22:17:01.51#ibcon#end of sib2, iclass 23, count 0 2006.285.22:17:01.51#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:17:01.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:17:01.51#ibcon#[25=USB\r\n] 2006.285.22:17:01.51#ibcon#*before write, iclass 23, count 0 2006.285.22:17:01.51#ibcon#enter sib2, iclass 23, count 0 2006.285.22:17:01.51#ibcon#flushed, iclass 23, count 0 2006.285.22:17:01.51#ibcon#about to write, iclass 23, count 0 2006.285.22:17:01.51#ibcon#wrote, iclass 23, count 0 2006.285.22:17:01.51#ibcon#about to read 3, iclass 23, count 0 2006.285.22:17:01.54#ibcon#read 3, iclass 23, count 0 2006.285.22:17:01.54#ibcon#about to read 4, iclass 23, count 0 2006.285.22:17:01.54#ibcon#read 4, iclass 23, count 0 2006.285.22:17:01.54#ibcon#about to read 5, iclass 23, count 0 2006.285.22:17:01.54#ibcon#read 5, iclass 23, count 0 2006.285.22:17:01.54#ibcon#about to read 6, iclass 23, count 0 2006.285.22:17:01.54#ibcon#read 6, iclass 23, count 0 2006.285.22:17:01.54#ibcon#end of sib2, iclass 23, count 0 2006.285.22:17:01.54#ibcon#*after write, iclass 23, count 0 2006.285.22:17:01.54#ibcon#*before return 0, iclass 23, count 0 2006.285.22:17:01.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:17:01.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:17:01.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:17:01.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:17:01.54$vck44/valo=2,534.99 2006.285.22:17:01.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.22:17:01.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.22:17:01.54#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:01.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:17:01.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:17:01.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:17:01.54#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:17:01.54#ibcon#first serial, iclass 25, count 0 2006.285.22:17:01.54#ibcon#enter sib2, iclass 25, count 0 2006.285.22:17:01.54#ibcon#flushed, iclass 25, count 0 2006.285.22:17:01.54#ibcon#about to write, iclass 25, count 0 2006.285.22:17:01.54#ibcon#wrote, iclass 25, count 0 2006.285.22:17:01.54#ibcon#about to read 3, iclass 25, count 0 2006.285.22:17:01.56#ibcon#read 3, iclass 25, count 0 2006.285.22:17:01.56#ibcon#about to read 4, iclass 25, count 0 2006.285.22:17:01.56#ibcon#read 4, iclass 25, count 0 2006.285.22:17:01.56#ibcon#about to read 5, iclass 25, count 0 2006.285.22:17:01.56#ibcon#read 5, iclass 25, count 0 2006.285.22:17:01.56#ibcon#about to read 6, iclass 25, count 0 2006.285.22:17:01.56#ibcon#read 6, iclass 25, count 0 2006.285.22:17:01.56#ibcon#end of sib2, iclass 25, count 0 2006.285.22:17:01.56#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:17:01.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:17:01.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:17:01.56#ibcon#*before write, iclass 25, count 0 2006.285.22:17:01.56#ibcon#enter sib2, iclass 25, count 0 2006.285.22:17:01.56#ibcon#flushed, iclass 25, count 0 2006.285.22:17:01.56#ibcon#about to write, iclass 25, count 0 2006.285.22:17:01.56#ibcon#wrote, iclass 25, count 0 2006.285.22:17:01.56#ibcon#about to read 3, iclass 25, count 0 2006.285.22:17:01.60#ibcon#read 3, iclass 25, count 0 2006.285.22:17:01.60#ibcon#about to read 4, iclass 25, count 0 2006.285.22:17:01.60#ibcon#read 4, iclass 25, count 0 2006.285.22:17:01.60#ibcon#about to read 5, iclass 25, count 0 2006.285.22:17:01.60#ibcon#read 5, iclass 25, count 0 2006.285.22:17:01.60#ibcon#about to read 6, iclass 25, count 0 2006.285.22:17:01.60#ibcon#read 6, iclass 25, count 0 2006.285.22:17:01.60#ibcon#end of sib2, iclass 25, count 0 2006.285.22:17:01.60#ibcon#*after write, iclass 25, count 0 2006.285.22:17:01.60#ibcon#*before return 0, iclass 25, count 0 2006.285.22:17:01.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:17:01.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:17:01.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:17:01.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:17:01.60$vck44/va=2,6 2006.285.22:17:01.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.22:17:01.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.22:17:01.60#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:01.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:17:01.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:17:01.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:17:01.66#ibcon#enter wrdev, iclass 27, count 2 2006.285.22:17:01.66#ibcon#first serial, iclass 27, count 2 2006.285.22:17:01.66#ibcon#enter sib2, iclass 27, count 2 2006.285.22:17:01.66#ibcon#flushed, iclass 27, count 2 2006.285.22:17:01.66#ibcon#about to write, iclass 27, count 2 2006.285.22:17:01.66#ibcon#wrote, iclass 27, count 2 2006.285.22:17:01.66#ibcon#about to read 3, iclass 27, count 2 2006.285.22:17:01.68#ibcon#read 3, iclass 27, count 2 2006.285.22:17:01.68#ibcon#about to read 4, iclass 27, count 2 2006.285.22:17:01.68#ibcon#read 4, iclass 27, count 2 2006.285.22:17:01.68#ibcon#about to read 5, iclass 27, count 2 2006.285.22:17:01.68#ibcon#read 5, iclass 27, count 2 2006.285.22:17:01.68#ibcon#about to read 6, iclass 27, count 2 2006.285.22:17:01.68#ibcon#read 6, iclass 27, count 2 2006.285.22:17:01.68#ibcon#end of sib2, iclass 27, count 2 2006.285.22:17:01.68#ibcon#*mode == 0, iclass 27, count 2 2006.285.22:17:01.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.22:17:01.68#ibcon#[25=AT02-06\r\n] 2006.285.22:17:01.68#ibcon#*before write, iclass 27, count 2 2006.285.22:17:01.68#ibcon#enter sib2, iclass 27, count 2 2006.285.22:17:01.68#ibcon#flushed, iclass 27, count 2 2006.285.22:17:01.68#ibcon#about to write, iclass 27, count 2 2006.285.22:17:01.68#ibcon#wrote, iclass 27, count 2 2006.285.22:17:01.68#ibcon#about to read 3, iclass 27, count 2 2006.285.22:17:01.71#ibcon#read 3, iclass 27, count 2 2006.285.22:17:01.71#ibcon#about to read 4, iclass 27, count 2 2006.285.22:17:01.71#ibcon#read 4, iclass 27, count 2 2006.285.22:17:01.71#ibcon#about to read 5, iclass 27, count 2 2006.285.22:17:01.71#ibcon#read 5, iclass 27, count 2 2006.285.22:17:01.71#ibcon#about to read 6, iclass 27, count 2 2006.285.22:17:01.71#ibcon#read 6, iclass 27, count 2 2006.285.22:17:01.71#ibcon#end of sib2, iclass 27, count 2 2006.285.22:17:01.71#ibcon#*after write, iclass 27, count 2 2006.285.22:17:01.71#ibcon#*before return 0, iclass 27, count 2 2006.285.22:17:01.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:17:01.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:17:01.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.22:17:01.71#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:01.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:17:01.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:17:01.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:17:01.83#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:17:01.83#ibcon#first serial, iclass 27, count 0 2006.285.22:17:01.83#ibcon#enter sib2, iclass 27, count 0 2006.285.22:17:01.83#ibcon#flushed, iclass 27, count 0 2006.285.22:17:01.83#ibcon#about to write, iclass 27, count 0 2006.285.22:17:01.83#ibcon#wrote, iclass 27, count 0 2006.285.22:17:01.83#ibcon#about to read 3, iclass 27, count 0 2006.285.22:17:01.85#ibcon#read 3, iclass 27, count 0 2006.285.22:17:01.85#ibcon#about to read 4, iclass 27, count 0 2006.285.22:17:01.85#ibcon#read 4, iclass 27, count 0 2006.285.22:17:01.85#ibcon#about to read 5, iclass 27, count 0 2006.285.22:17:01.85#ibcon#read 5, iclass 27, count 0 2006.285.22:17:01.85#ibcon#about to read 6, iclass 27, count 0 2006.285.22:17:01.85#ibcon#read 6, iclass 27, count 0 2006.285.22:17:01.85#ibcon#end of sib2, iclass 27, count 0 2006.285.22:17:01.85#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:17:01.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:17:01.85#ibcon#[25=USB\r\n] 2006.285.22:17:01.85#ibcon#*before write, iclass 27, count 0 2006.285.22:17:01.85#ibcon#enter sib2, iclass 27, count 0 2006.285.22:17:01.85#ibcon#flushed, iclass 27, count 0 2006.285.22:17:01.85#ibcon#about to write, iclass 27, count 0 2006.285.22:17:01.85#ibcon#wrote, iclass 27, count 0 2006.285.22:17:01.85#ibcon#about to read 3, iclass 27, count 0 2006.285.22:17:01.88#ibcon#read 3, iclass 27, count 0 2006.285.22:17:01.88#ibcon#about to read 4, iclass 27, count 0 2006.285.22:17:01.88#ibcon#read 4, iclass 27, count 0 2006.285.22:17:01.88#ibcon#about to read 5, iclass 27, count 0 2006.285.22:17:01.88#ibcon#read 5, iclass 27, count 0 2006.285.22:17:01.88#ibcon#about to read 6, iclass 27, count 0 2006.285.22:17:01.88#ibcon#read 6, iclass 27, count 0 2006.285.22:17:01.88#ibcon#end of sib2, iclass 27, count 0 2006.285.22:17:01.88#ibcon#*after write, iclass 27, count 0 2006.285.22:17:01.88#ibcon#*before return 0, iclass 27, count 0 2006.285.22:17:01.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:17:01.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:17:01.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:17:01.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:17:01.88$vck44/valo=3,564.99 2006.285.22:17:01.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.22:17:01.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.22:17:01.88#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:01.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:17:01.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:17:01.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:17:01.88#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:17:01.88#ibcon#first serial, iclass 29, count 0 2006.285.22:17:01.88#ibcon#enter sib2, iclass 29, count 0 2006.285.22:17:01.88#ibcon#flushed, iclass 29, count 0 2006.285.22:17:01.88#ibcon#about to write, iclass 29, count 0 2006.285.22:17:01.88#ibcon#wrote, iclass 29, count 0 2006.285.22:17:01.88#ibcon#about to read 3, iclass 29, count 0 2006.285.22:17:01.90#ibcon#read 3, iclass 29, count 0 2006.285.22:17:01.90#ibcon#about to read 4, iclass 29, count 0 2006.285.22:17:01.90#ibcon#read 4, iclass 29, count 0 2006.285.22:17:01.90#ibcon#about to read 5, iclass 29, count 0 2006.285.22:17:01.90#ibcon#read 5, iclass 29, count 0 2006.285.22:17:01.90#ibcon#about to read 6, iclass 29, count 0 2006.285.22:17:01.90#ibcon#read 6, iclass 29, count 0 2006.285.22:17:01.90#ibcon#end of sib2, iclass 29, count 0 2006.285.22:17:01.90#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:17:01.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:17:01.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:17:01.90#ibcon#*before write, iclass 29, count 0 2006.285.22:17:01.90#ibcon#enter sib2, iclass 29, count 0 2006.285.22:17:01.90#ibcon#flushed, iclass 29, count 0 2006.285.22:17:01.90#ibcon#about to write, iclass 29, count 0 2006.285.22:17:01.90#ibcon#wrote, iclass 29, count 0 2006.285.22:17:01.90#ibcon#about to read 3, iclass 29, count 0 2006.285.22:17:01.94#ibcon#read 3, iclass 29, count 0 2006.285.22:17:01.94#ibcon#about to read 4, iclass 29, count 0 2006.285.22:17:01.94#ibcon#read 4, iclass 29, count 0 2006.285.22:17:01.94#ibcon#about to read 5, iclass 29, count 0 2006.285.22:17:01.94#ibcon#read 5, iclass 29, count 0 2006.285.22:17:01.94#ibcon#about to read 6, iclass 29, count 0 2006.285.22:17:01.94#ibcon#read 6, iclass 29, count 0 2006.285.22:17:01.94#ibcon#end of sib2, iclass 29, count 0 2006.285.22:17:01.94#ibcon#*after write, iclass 29, count 0 2006.285.22:17:01.94#ibcon#*before return 0, iclass 29, count 0 2006.285.22:17:01.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:17:01.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:17:01.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:17:01.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:17:01.94$vck44/va=3,7 2006.285.22:17:01.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.22:17:01.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.22:17:01.94#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:01.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:17:02.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:17:02.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:17:02.00#ibcon#enter wrdev, iclass 31, count 2 2006.285.22:17:02.00#ibcon#first serial, iclass 31, count 2 2006.285.22:17:02.00#ibcon#enter sib2, iclass 31, count 2 2006.285.22:17:02.00#ibcon#flushed, iclass 31, count 2 2006.285.22:17:02.00#ibcon#about to write, iclass 31, count 2 2006.285.22:17:02.00#ibcon#wrote, iclass 31, count 2 2006.285.22:17:02.00#ibcon#about to read 3, iclass 31, count 2 2006.285.22:17:02.02#ibcon#read 3, iclass 31, count 2 2006.285.22:17:02.02#ibcon#about to read 4, iclass 31, count 2 2006.285.22:17:02.02#ibcon#read 4, iclass 31, count 2 2006.285.22:17:02.02#ibcon#about to read 5, iclass 31, count 2 2006.285.22:17:02.02#ibcon#read 5, iclass 31, count 2 2006.285.22:17:02.02#ibcon#about to read 6, iclass 31, count 2 2006.285.22:17:02.02#ibcon#read 6, iclass 31, count 2 2006.285.22:17:02.02#ibcon#end of sib2, iclass 31, count 2 2006.285.22:17:02.02#ibcon#*mode == 0, iclass 31, count 2 2006.285.22:17:02.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.22:17:02.02#ibcon#[25=AT03-07\r\n] 2006.285.22:17:02.02#ibcon#*before write, iclass 31, count 2 2006.285.22:17:02.02#ibcon#enter sib2, iclass 31, count 2 2006.285.22:17:02.02#ibcon#flushed, iclass 31, count 2 2006.285.22:17:02.02#ibcon#about to write, iclass 31, count 2 2006.285.22:17:02.02#ibcon#wrote, iclass 31, count 2 2006.285.22:17:02.02#ibcon#about to read 3, iclass 31, count 2 2006.285.22:17:02.05#ibcon#read 3, iclass 31, count 2 2006.285.22:17:02.05#ibcon#about to read 4, iclass 31, count 2 2006.285.22:17:02.05#ibcon#read 4, iclass 31, count 2 2006.285.22:17:02.05#ibcon#about to read 5, iclass 31, count 2 2006.285.22:17:02.05#ibcon#read 5, iclass 31, count 2 2006.285.22:17:02.05#ibcon#about to read 6, iclass 31, count 2 2006.285.22:17:02.05#ibcon#read 6, iclass 31, count 2 2006.285.22:17:02.05#ibcon#end of sib2, iclass 31, count 2 2006.285.22:17:02.05#ibcon#*after write, iclass 31, count 2 2006.285.22:17:02.05#ibcon#*before return 0, iclass 31, count 2 2006.285.22:17:02.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:17:02.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:17:02.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.22:17:02.05#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:02.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:17:02.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:17:02.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:17:02.17#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:17:02.17#ibcon#first serial, iclass 31, count 0 2006.285.22:17:02.17#ibcon#enter sib2, iclass 31, count 0 2006.285.22:17:02.17#ibcon#flushed, iclass 31, count 0 2006.285.22:17:02.17#ibcon#about to write, iclass 31, count 0 2006.285.22:17:02.17#ibcon#wrote, iclass 31, count 0 2006.285.22:17:02.17#ibcon#about to read 3, iclass 31, count 0 2006.285.22:17:02.19#ibcon#read 3, iclass 31, count 0 2006.285.22:17:02.19#ibcon#about to read 4, iclass 31, count 0 2006.285.22:17:02.19#ibcon#read 4, iclass 31, count 0 2006.285.22:17:02.19#ibcon#about to read 5, iclass 31, count 0 2006.285.22:17:02.19#ibcon#read 5, iclass 31, count 0 2006.285.22:17:02.19#ibcon#about to read 6, iclass 31, count 0 2006.285.22:17:02.19#ibcon#read 6, iclass 31, count 0 2006.285.22:17:02.19#ibcon#end of sib2, iclass 31, count 0 2006.285.22:17:02.19#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:17:02.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:17:02.19#ibcon#[25=USB\r\n] 2006.285.22:17:02.19#ibcon#*before write, iclass 31, count 0 2006.285.22:17:02.19#ibcon#enter sib2, iclass 31, count 0 2006.285.22:17:02.19#ibcon#flushed, iclass 31, count 0 2006.285.22:17:02.19#ibcon#about to write, iclass 31, count 0 2006.285.22:17:02.19#ibcon#wrote, iclass 31, count 0 2006.285.22:17:02.19#ibcon#about to read 3, iclass 31, count 0 2006.285.22:17:02.22#ibcon#read 3, iclass 31, count 0 2006.285.22:17:02.22#ibcon#about to read 4, iclass 31, count 0 2006.285.22:17:02.22#ibcon#read 4, iclass 31, count 0 2006.285.22:17:02.22#ibcon#about to read 5, iclass 31, count 0 2006.285.22:17:02.22#ibcon#read 5, iclass 31, count 0 2006.285.22:17:02.22#ibcon#about to read 6, iclass 31, count 0 2006.285.22:17:02.22#ibcon#read 6, iclass 31, count 0 2006.285.22:17:02.22#ibcon#end of sib2, iclass 31, count 0 2006.285.22:17:02.22#ibcon#*after write, iclass 31, count 0 2006.285.22:17:02.22#ibcon#*before return 0, iclass 31, count 0 2006.285.22:17:02.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:17:02.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:17:02.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:17:02.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:17:02.22$vck44/valo=4,624.99 2006.285.22:17:02.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.22:17:02.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.22:17:02.22#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:02.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:17:02.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:17:02.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:17:02.22#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:17:02.22#ibcon#first serial, iclass 33, count 0 2006.285.22:17:02.22#ibcon#enter sib2, iclass 33, count 0 2006.285.22:17:02.22#ibcon#flushed, iclass 33, count 0 2006.285.22:17:02.22#ibcon#about to write, iclass 33, count 0 2006.285.22:17:02.22#ibcon#wrote, iclass 33, count 0 2006.285.22:17:02.22#ibcon#about to read 3, iclass 33, count 0 2006.285.22:17:02.24#ibcon#read 3, iclass 33, count 0 2006.285.22:17:02.24#ibcon#about to read 4, iclass 33, count 0 2006.285.22:17:02.24#ibcon#read 4, iclass 33, count 0 2006.285.22:17:02.24#ibcon#about to read 5, iclass 33, count 0 2006.285.22:17:02.24#ibcon#read 5, iclass 33, count 0 2006.285.22:17:02.24#ibcon#about to read 6, iclass 33, count 0 2006.285.22:17:02.24#ibcon#read 6, iclass 33, count 0 2006.285.22:17:02.24#ibcon#end of sib2, iclass 33, count 0 2006.285.22:17:02.24#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:17:02.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:17:02.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:17:02.24#ibcon#*before write, iclass 33, count 0 2006.285.22:17:02.24#ibcon#enter sib2, iclass 33, count 0 2006.285.22:17:02.24#ibcon#flushed, iclass 33, count 0 2006.285.22:17:02.24#ibcon#about to write, iclass 33, count 0 2006.285.22:17:02.24#ibcon#wrote, iclass 33, count 0 2006.285.22:17:02.24#ibcon#about to read 3, iclass 33, count 0 2006.285.22:17:02.28#ibcon#read 3, iclass 33, count 0 2006.285.22:17:02.28#ibcon#about to read 4, iclass 33, count 0 2006.285.22:17:02.28#ibcon#read 4, iclass 33, count 0 2006.285.22:17:02.28#ibcon#about to read 5, iclass 33, count 0 2006.285.22:17:02.28#ibcon#read 5, iclass 33, count 0 2006.285.22:17:02.28#ibcon#about to read 6, iclass 33, count 0 2006.285.22:17:02.28#ibcon#read 6, iclass 33, count 0 2006.285.22:17:02.28#ibcon#end of sib2, iclass 33, count 0 2006.285.22:17:02.28#ibcon#*after write, iclass 33, count 0 2006.285.22:17:02.28#ibcon#*before return 0, iclass 33, count 0 2006.285.22:17:02.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:17:02.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:17:02.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:17:02.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:17:02.28$vck44/va=4,6 2006.285.22:17:02.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.22:17:02.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.22:17:02.28#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:02.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:17:02.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:17:02.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:17:02.34#ibcon#enter wrdev, iclass 35, count 2 2006.285.22:17:02.34#ibcon#first serial, iclass 35, count 2 2006.285.22:17:02.34#ibcon#enter sib2, iclass 35, count 2 2006.285.22:17:02.34#ibcon#flushed, iclass 35, count 2 2006.285.22:17:02.34#ibcon#about to write, iclass 35, count 2 2006.285.22:17:02.34#ibcon#wrote, iclass 35, count 2 2006.285.22:17:02.34#ibcon#about to read 3, iclass 35, count 2 2006.285.22:17:02.36#ibcon#read 3, iclass 35, count 2 2006.285.22:17:02.36#ibcon#about to read 4, iclass 35, count 2 2006.285.22:17:02.36#ibcon#read 4, iclass 35, count 2 2006.285.22:17:02.36#ibcon#about to read 5, iclass 35, count 2 2006.285.22:17:02.36#ibcon#read 5, iclass 35, count 2 2006.285.22:17:02.36#ibcon#about to read 6, iclass 35, count 2 2006.285.22:17:02.36#ibcon#read 6, iclass 35, count 2 2006.285.22:17:02.36#ibcon#end of sib2, iclass 35, count 2 2006.285.22:17:02.36#ibcon#*mode == 0, iclass 35, count 2 2006.285.22:17:02.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.22:17:02.36#ibcon#[25=AT04-06\r\n] 2006.285.22:17:02.36#ibcon#*before write, iclass 35, count 2 2006.285.22:17:02.36#ibcon#enter sib2, iclass 35, count 2 2006.285.22:17:02.36#ibcon#flushed, iclass 35, count 2 2006.285.22:17:02.36#ibcon#about to write, iclass 35, count 2 2006.285.22:17:02.36#ibcon#wrote, iclass 35, count 2 2006.285.22:17:02.36#ibcon#about to read 3, iclass 35, count 2 2006.285.22:17:02.39#ibcon#read 3, iclass 35, count 2 2006.285.22:17:02.39#ibcon#about to read 4, iclass 35, count 2 2006.285.22:17:02.39#ibcon#read 4, iclass 35, count 2 2006.285.22:17:02.39#ibcon#about to read 5, iclass 35, count 2 2006.285.22:17:02.39#ibcon#read 5, iclass 35, count 2 2006.285.22:17:02.39#ibcon#about to read 6, iclass 35, count 2 2006.285.22:17:02.39#ibcon#read 6, iclass 35, count 2 2006.285.22:17:02.39#ibcon#end of sib2, iclass 35, count 2 2006.285.22:17:02.39#ibcon#*after write, iclass 35, count 2 2006.285.22:17:02.39#ibcon#*before return 0, iclass 35, count 2 2006.285.22:17:02.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:17:02.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:17:02.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.22:17:02.39#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:02.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:17:02.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:17:02.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:17:02.51#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:17:02.51#ibcon#first serial, iclass 35, count 0 2006.285.22:17:02.51#ibcon#enter sib2, iclass 35, count 0 2006.285.22:17:02.51#ibcon#flushed, iclass 35, count 0 2006.285.22:17:02.51#ibcon#about to write, iclass 35, count 0 2006.285.22:17:02.51#ibcon#wrote, iclass 35, count 0 2006.285.22:17:02.51#ibcon#about to read 3, iclass 35, count 0 2006.285.22:17:02.53#ibcon#read 3, iclass 35, count 0 2006.285.22:17:02.53#ibcon#about to read 4, iclass 35, count 0 2006.285.22:17:02.53#ibcon#read 4, iclass 35, count 0 2006.285.22:17:02.53#ibcon#about to read 5, iclass 35, count 0 2006.285.22:17:02.53#ibcon#read 5, iclass 35, count 0 2006.285.22:17:02.53#ibcon#about to read 6, iclass 35, count 0 2006.285.22:17:02.53#ibcon#read 6, iclass 35, count 0 2006.285.22:17:02.53#ibcon#end of sib2, iclass 35, count 0 2006.285.22:17:02.53#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:17:02.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:17:02.53#ibcon#[25=USB\r\n] 2006.285.22:17:02.53#ibcon#*before write, iclass 35, count 0 2006.285.22:17:02.53#ibcon#enter sib2, iclass 35, count 0 2006.285.22:17:02.53#ibcon#flushed, iclass 35, count 0 2006.285.22:17:02.53#ibcon#about to write, iclass 35, count 0 2006.285.22:17:02.53#ibcon#wrote, iclass 35, count 0 2006.285.22:17:02.53#ibcon#about to read 3, iclass 35, count 0 2006.285.22:17:02.56#ibcon#read 3, iclass 35, count 0 2006.285.22:17:02.56#ibcon#about to read 4, iclass 35, count 0 2006.285.22:17:02.56#ibcon#read 4, iclass 35, count 0 2006.285.22:17:02.56#ibcon#about to read 5, iclass 35, count 0 2006.285.22:17:02.56#ibcon#read 5, iclass 35, count 0 2006.285.22:17:02.56#ibcon#about to read 6, iclass 35, count 0 2006.285.22:17:02.56#ibcon#read 6, iclass 35, count 0 2006.285.22:17:02.56#ibcon#end of sib2, iclass 35, count 0 2006.285.22:17:02.56#ibcon#*after write, iclass 35, count 0 2006.285.22:17:02.56#ibcon#*before return 0, iclass 35, count 0 2006.285.22:17:02.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:17:02.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:17:02.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:17:02.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:17:02.56$vck44/valo=5,734.99 2006.285.22:17:02.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.22:17:02.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.22:17:02.56#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:02.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:17:02.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:17:02.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:17:02.56#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:17:02.56#ibcon#first serial, iclass 37, count 0 2006.285.22:17:02.56#ibcon#enter sib2, iclass 37, count 0 2006.285.22:17:02.56#ibcon#flushed, iclass 37, count 0 2006.285.22:17:02.56#ibcon#about to write, iclass 37, count 0 2006.285.22:17:02.56#ibcon#wrote, iclass 37, count 0 2006.285.22:17:02.56#ibcon#about to read 3, iclass 37, count 0 2006.285.22:17:02.58#ibcon#read 3, iclass 37, count 0 2006.285.22:17:02.58#ibcon#about to read 4, iclass 37, count 0 2006.285.22:17:02.58#ibcon#read 4, iclass 37, count 0 2006.285.22:17:02.58#ibcon#about to read 5, iclass 37, count 0 2006.285.22:17:02.58#ibcon#read 5, iclass 37, count 0 2006.285.22:17:02.58#ibcon#about to read 6, iclass 37, count 0 2006.285.22:17:02.58#ibcon#read 6, iclass 37, count 0 2006.285.22:17:02.58#ibcon#end of sib2, iclass 37, count 0 2006.285.22:17:02.58#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:17:02.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:17:02.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:17:02.58#ibcon#*before write, iclass 37, count 0 2006.285.22:17:02.58#ibcon#enter sib2, iclass 37, count 0 2006.285.22:17:02.58#ibcon#flushed, iclass 37, count 0 2006.285.22:17:02.58#ibcon#about to write, iclass 37, count 0 2006.285.22:17:02.58#ibcon#wrote, iclass 37, count 0 2006.285.22:17:02.58#ibcon#about to read 3, iclass 37, count 0 2006.285.22:17:02.62#ibcon#read 3, iclass 37, count 0 2006.285.22:17:02.62#ibcon#about to read 4, iclass 37, count 0 2006.285.22:17:02.62#ibcon#read 4, iclass 37, count 0 2006.285.22:17:02.62#ibcon#about to read 5, iclass 37, count 0 2006.285.22:17:02.62#ibcon#read 5, iclass 37, count 0 2006.285.22:17:02.62#ibcon#about to read 6, iclass 37, count 0 2006.285.22:17:02.62#ibcon#read 6, iclass 37, count 0 2006.285.22:17:02.62#ibcon#end of sib2, iclass 37, count 0 2006.285.22:17:02.62#ibcon#*after write, iclass 37, count 0 2006.285.22:17:02.62#ibcon#*before return 0, iclass 37, count 0 2006.285.22:17:02.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:17:02.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:17:02.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:17:02.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:17:02.62$vck44/va=5,3 2006.285.22:17:02.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.22:17:02.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.22:17:02.62#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:02.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:17:02.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:17:02.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:17:02.68#ibcon#enter wrdev, iclass 39, count 2 2006.285.22:17:02.68#ibcon#first serial, iclass 39, count 2 2006.285.22:17:02.68#ibcon#enter sib2, iclass 39, count 2 2006.285.22:17:02.68#ibcon#flushed, iclass 39, count 2 2006.285.22:17:02.68#ibcon#about to write, iclass 39, count 2 2006.285.22:17:02.68#ibcon#wrote, iclass 39, count 2 2006.285.22:17:02.68#ibcon#about to read 3, iclass 39, count 2 2006.285.22:17:02.70#ibcon#read 3, iclass 39, count 2 2006.285.22:17:02.70#ibcon#about to read 4, iclass 39, count 2 2006.285.22:17:02.70#ibcon#read 4, iclass 39, count 2 2006.285.22:17:02.70#ibcon#about to read 5, iclass 39, count 2 2006.285.22:17:02.70#ibcon#read 5, iclass 39, count 2 2006.285.22:17:02.70#ibcon#about to read 6, iclass 39, count 2 2006.285.22:17:02.70#ibcon#read 6, iclass 39, count 2 2006.285.22:17:02.70#ibcon#end of sib2, iclass 39, count 2 2006.285.22:17:02.70#ibcon#*mode == 0, iclass 39, count 2 2006.285.22:17:02.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.22:17:02.70#ibcon#[25=AT05-03\r\n] 2006.285.22:17:02.70#ibcon#*before write, iclass 39, count 2 2006.285.22:17:02.70#ibcon#enter sib2, iclass 39, count 2 2006.285.22:17:02.70#ibcon#flushed, iclass 39, count 2 2006.285.22:17:02.70#ibcon#about to write, iclass 39, count 2 2006.285.22:17:02.70#ibcon#wrote, iclass 39, count 2 2006.285.22:17:02.70#ibcon#about to read 3, iclass 39, count 2 2006.285.22:17:02.73#ibcon#read 3, iclass 39, count 2 2006.285.22:17:02.73#ibcon#about to read 4, iclass 39, count 2 2006.285.22:17:02.73#ibcon#read 4, iclass 39, count 2 2006.285.22:17:02.73#ibcon#about to read 5, iclass 39, count 2 2006.285.22:17:02.73#ibcon#read 5, iclass 39, count 2 2006.285.22:17:02.73#ibcon#about to read 6, iclass 39, count 2 2006.285.22:17:02.73#ibcon#read 6, iclass 39, count 2 2006.285.22:17:02.73#ibcon#end of sib2, iclass 39, count 2 2006.285.22:17:02.73#ibcon#*after write, iclass 39, count 2 2006.285.22:17:02.73#ibcon#*before return 0, iclass 39, count 2 2006.285.22:17:02.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:17:02.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:17:02.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.22:17:02.73#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:02.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:17:02.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:17:02.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:17:02.85#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:17:02.85#ibcon#first serial, iclass 39, count 0 2006.285.22:17:02.85#ibcon#enter sib2, iclass 39, count 0 2006.285.22:17:02.85#ibcon#flushed, iclass 39, count 0 2006.285.22:17:02.85#ibcon#about to write, iclass 39, count 0 2006.285.22:17:02.85#ibcon#wrote, iclass 39, count 0 2006.285.22:17:02.85#ibcon#about to read 3, iclass 39, count 0 2006.285.22:17:02.87#ibcon#read 3, iclass 39, count 0 2006.285.22:17:02.87#ibcon#about to read 4, iclass 39, count 0 2006.285.22:17:02.87#ibcon#read 4, iclass 39, count 0 2006.285.22:17:02.87#ibcon#about to read 5, iclass 39, count 0 2006.285.22:17:02.87#ibcon#read 5, iclass 39, count 0 2006.285.22:17:02.87#ibcon#about to read 6, iclass 39, count 0 2006.285.22:17:02.87#ibcon#read 6, iclass 39, count 0 2006.285.22:17:02.87#ibcon#end of sib2, iclass 39, count 0 2006.285.22:17:02.87#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:17:02.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:17:02.87#ibcon#[25=USB\r\n] 2006.285.22:17:02.87#ibcon#*before write, iclass 39, count 0 2006.285.22:17:02.87#ibcon#enter sib2, iclass 39, count 0 2006.285.22:17:02.87#ibcon#flushed, iclass 39, count 0 2006.285.22:17:02.87#ibcon#about to write, iclass 39, count 0 2006.285.22:17:02.87#ibcon#wrote, iclass 39, count 0 2006.285.22:17:02.87#ibcon#about to read 3, iclass 39, count 0 2006.285.22:17:02.90#ibcon#read 3, iclass 39, count 0 2006.285.22:17:02.90#ibcon#about to read 4, iclass 39, count 0 2006.285.22:17:02.90#ibcon#read 4, iclass 39, count 0 2006.285.22:17:02.90#ibcon#about to read 5, iclass 39, count 0 2006.285.22:17:02.90#ibcon#read 5, iclass 39, count 0 2006.285.22:17:02.90#ibcon#about to read 6, iclass 39, count 0 2006.285.22:17:02.90#ibcon#read 6, iclass 39, count 0 2006.285.22:17:02.90#ibcon#end of sib2, iclass 39, count 0 2006.285.22:17:02.90#ibcon#*after write, iclass 39, count 0 2006.285.22:17:02.90#ibcon#*before return 0, iclass 39, count 0 2006.285.22:17:02.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:17:02.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:17:02.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:17:02.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:17:02.90$vck44/valo=6,814.99 2006.285.22:17:02.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.22:17:02.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.22:17:02.90#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:02.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:17:02.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:17:02.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:17:02.90#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:17:02.90#ibcon#first serial, iclass 3, count 0 2006.285.22:17:02.90#ibcon#enter sib2, iclass 3, count 0 2006.285.22:17:02.90#ibcon#flushed, iclass 3, count 0 2006.285.22:17:02.90#ibcon#about to write, iclass 3, count 0 2006.285.22:17:02.90#ibcon#wrote, iclass 3, count 0 2006.285.22:17:02.90#ibcon#about to read 3, iclass 3, count 0 2006.285.22:17:02.92#ibcon#read 3, iclass 3, count 0 2006.285.22:17:02.92#ibcon#about to read 4, iclass 3, count 0 2006.285.22:17:02.92#ibcon#read 4, iclass 3, count 0 2006.285.22:17:02.92#ibcon#about to read 5, iclass 3, count 0 2006.285.22:17:02.92#ibcon#read 5, iclass 3, count 0 2006.285.22:17:02.92#ibcon#about to read 6, iclass 3, count 0 2006.285.22:17:02.92#ibcon#read 6, iclass 3, count 0 2006.285.22:17:02.92#ibcon#end of sib2, iclass 3, count 0 2006.285.22:17:02.92#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:17:02.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:17:02.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:17:02.92#ibcon#*before write, iclass 3, count 0 2006.285.22:17:02.92#ibcon#enter sib2, iclass 3, count 0 2006.285.22:17:02.92#ibcon#flushed, iclass 3, count 0 2006.285.22:17:02.92#ibcon#about to write, iclass 3, count 0 2006.285.22:17:02.92#ibcon#wrote, iclass 3, count 0 2006.285.22:17:02.92#ibcon#about to read 3, iclass 3, count 0 2006.285.22:17:02.96#ibcon#read 3, iclass 3, count 0 2006.285.22:17:02.96#ibcon#about to read 4, iclass 3, count 0 2006.285.22:17:02.96#ibcon#read 4, iclass 3, count 0 2006.285.22:17:02.96#ibcon#about to read 5, iclass 3, count 0 2006.285.22:17:02.96#ibcon#read 5, iclass 3, count 0 2006.285.22:17:02.96#ibcon#about to read 6, iclass 3, count 0 2006.285.22:17:02.96#ibcon#read 6, iclass 3, count 0 2006.285.22:17:02.96#ibcon#end of sib2, iclass 3, count 0 2006.285.22:17:02.96#ibcon#*after write, iclass 3, count 0 2006.285.22:17:02.96#ibcon#*before return 0, iclass 3, count 0 2006.285.22:17:02.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:17:02.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:17:02.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:17:02.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:17:02.96$vck44/va=6,4 2006.285.22:17:02.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.22:17:02.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.22:17:02.96#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:02.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:17:03.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:17:03.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:17:03.02#ibcon#enter wrdev, iclass 5, count 2 2006.285.22:17:03.02#ibcon#first serial, iclass 5, count 2 2006.285.22:17:03.02#ibcon#enter sib2, iclass 5, count 2 2006.285.22:17:03.02#ibcon#flushed, iclass 5, count 2 2006.285.22:17:03.02#ibcon#about to write, iclass 5, count 2 2006.285.22:17:03.02#ibcon#wrote, iclass 5, count 2 2006.285.22:17:03.02#ibcon#about to read 3, iclass 5, count 2 2006.285.22:17:03.04#ibcon#read 3, iclass 5, count 2 2006.285.22:17:03.04#ibcon#about to read 4, iclass 5, count 2 2006.285.22:17:03.04#ibcon#read 4, iclass 5, count 2 2006.285.22:17:03.04#ibcon#about to read 5, iclass 5, count 2 2006.285.22:17:03.04#ibcon#read 5, iclass 5, count 2 2006.285.22:17:03.04#ibcon#about to read 6, iclass 5, count 2 2006.285.22:17:03.04#ibcon#read 6, iclass 5, count 2 2006.285.22:17:03.04#ibcon#end of sib2, iclass 5, count 2 2006.285.22:17:03.04#ibcon#*mode == 0, iclass 5, count 2 2006.285.22:17:03.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.22:17:03.04#ibcon#[25=AT06-04\r\n] 2006.285.22:17:03.04#ibcon#*before write, iclass 5, count 2 2006.285.22:17:03.04#ibcon#enter sib2, iclass 5, count 2 2006.285.22:17:03.04#ibcon#flushed, iclass 5, count 2 2006.285.22:17:03.04#ibcon#about to write, iclass 5, count 2 2006.285.22:17:03.04#ibcon#wrote, iclass 5, count 2 2006.285.22:17:03.04#ibcon#about to read 3, iclass 5, count 2 2006.285.22:17:03.07#ibcon#read 3, iclass 5, count 2 2006.285.22:17:03.07#ibcon#about to read 4, iclass 5, count 2 2006.285.22:17:03.07#ibcon#read 4, iclass 5, count 2 2006.285.22:17:03.07#ibcon#about to read 5, iclass 5, count 2 2006.285.22:17:03.07#ibcon#read 5, iclass 5, count 2 2006.285.22:17:03.07#ibcon#about to read 6, iclass 5, count 2 2006.285.22:17:03.07#ibcon#read 6, iclass 5, count 2 2006.285.22:17:03.07#ibcon#end of sib2, iclass 5, count 2 2006.285.22:17:03.07#ibcon#*after write, iclass 5, count 2 2006.285.22:17:03.07#ibcon#*before return 0, iclass 5, count 2 2006.285.22:17:03.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:17:03.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:17:03.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.22:17:03.07#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:03.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:17:03.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:17:03.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:17:03.19#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:17:03.19#ibcon#first serial, iclass 5, count 0 2006.285.22:17:03.19#ibcon#enter sib2, iclass 5, count 0 2006.285.22:17:03.19#ibcon#flushed, iclass 5, count 0 2006.285.22:17:03.19#ibcon#about to write, iclass 5, count 0 2006.285.22:17:03.19#ibcon#wrote, iclass 5, count 0 2006.285.22:17:03.19#ibcon#about to read 3, iclass 5, count 0 2006.285.22:17:03.21#ibcon#read 3, iclass 5, count 0 2006.285.22:17:03.21#ibcon#about to read 4, iclass 5, count 0 2006.285.22:17:03.21#ibcon#read 4, iclass 5, count 0 2006.285.22:17:03.21#ibcon#about to read 5, iclass 5, count 0 2006.285.22:17:03.21#ibcon#read 5, iclass 5, count 0 2006.285.22:17:03.21#ibcon#about to read 6, iclass 5, count 0 2006.285.22:17:03.21#ibcon#read 6, iclass 5, count 0 2006.285.22:17:03.21#ibcon#end of sib2, iclass 5, count 0 2006.285.22:17:03.21#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:17:03.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:17:03.21#ibcon#[25=USB\r\n] 2006.285.22:17:03.21#ibcon#*before write, iclass 5, count 0 2006.285.22:17:03.21#ibcon#enter sib2, iclass 5, count 0 2006.285.22:17:03.21#ibcon#flushed, iclass 5, count 0 2006.285.22:17:03.21#ibcon#about to write, iclass 5, count 0 2006.285.22:17:03.21#ibcon#wrote, iclass 5, count 0 2006.285.22:17:03.21#ibcon#about to read 3, iclass 5, count 0 2006.285.22:17:03.24#ibcon#read 3, iclass 5, count 0 2006.285.22:17:03.24#ibcon#about to read 4, iclass 5, count 0 2006.285.22:17:03.24#ibcon#read 4, iclass 5, count 0 2006.285.22:17:03.24#ibcon#about to read 5, iclass 5, count 0 2006.285.22:17:03.24#ibcon#read 5, iclass 5, count 0 2006.285.22:17:03.24#ibcon#about to read 6, iclass 5, count 0 2006.285.22:17:03.24#ibcon#read 6, iclass 5, count 0 2006.285.22:17:03.24#ibcon#end of sib2, iclass 5, count 0 2006.285.22:17:03.24#ibcon#*after write, iclass 5, count 0 2006.285.22:17:03.24#ibcon#*before return 0, iclass 5, count 0 2006.285.22:17:03.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:17:03.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:17:03.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:17:03.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:17:03.24$vck44/valo=7,864.99 2006.285.22:17:03.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.22:17:03.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.22:17:03.24#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:03.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:17:03.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:17:03.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:17:03.24#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:17:03.24#ibcon#first serial, iclass 7, count 0 2006.285.22:17:03.24#ibcon#enter sib2, iclass 7, count 0 2006.285.22:17:03.24#ibcon#flushed, iclass 7, count 0 2006.285.22:17:03.24#ibcon#about to write, iclass 7, count 0 2006.285.22:17:03.24#ibcon#wrote, iclass 7, count 0 2006.285.22:17:03.24#ibcon#about to read 3, iclass 7, count 0 2006.285.22:17:03.26#ibcon#read 3, iclass 7, count 0 2006.285.22:17:03.26#ibcon#about to read 4, iclass 7, count 0 2006.285.22:17:03.26#ibcon#read 4, iclass 7, count 0 2006.285.22:17:03.26#ibcon#about to read 5, iclass 7, count 0 2006.285.22:17:03.26#ibcon#read 5, iclass 7, count 0 2006.285.22:17:03.26#ibcon#about to read 6, iclass 7, count 0 2006.285.22:17:03.26#ibcon#read 6, iclass 7, count 0 2006.285.22:17:03.26#ibcon#end of sib2, iclass 7, count 0 2006.285.22:17:03.26#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:17:03.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:17:03.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:17:03.26#ibcon#*before write, iclass 7, count 0 2006.285.22:17:03.26#ibcon#enter sib2, iclass 7, count 0 2006.285.22:17:03.26#ibcon#flushed, iclass 7, count 0 2006.285.22:17:03.26#ibcon#about to write, iclass 7, count 0 2006.285.22:17:03.26#ibcon#wrote, iclass 7, count 0 2006.285.22:17:03.26#ibcon#about to read 3, iclass 7, count 0 2006.285.22:17:03.30#ibcon#read 3, iclass 7, count 0 2006.285.22:17:03.30#ibcon#about to read 4, iclass 7, count 0 2006.285.22:17:03.30#ibcon#read 4, iclass 7, count 0 2006.285.22:17:03.30#ibcon#about to read 5, iclass 7, count 0 2006.285.22:17:03.30#ibcon#read 5, iclass 7, count 0 2006.285.22:17:03.30#ibcon#about to read 6, iclass 7, count 0 2006.285.22:17:03.30#ibcon#read 6, iclass 7, count 0 2006.285.22:17:03.30#ibcon#end of sib2, iclass 7, count 0 2006.285.22:17:03.30#ibcon#*after write, iclass 7, count 0 2006.285.22:17:03.30#ibcon#*before return 0, iclass 7, count 0 2006.285.22:17:03.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:17:03.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:17:03.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:17:03.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:17:03.30$vck44/va=7,4 2006.285.22:17:03.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.22:17:03.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.22:17:03.30#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:03.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:17:03.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:17:03.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:17:03.36#ibcon#enter wrdev, iclass 11, count 2 2006.285.22:17:03.36#ibcon#first serial, iclass 11, count 2 2006.285.22:17:03.36#ibcon#enter sib2, iclass 11, count 2 2006.285.22:17:03.36#ibcon#flushed, iclass 11, count 2 2006.285.22:17:03.36#ibcon#about to write, iclass 11, count 2 2006.285.22:17:03.36#ibcon#wrote, iclass 11, count 2 2006.285.22:17:03.36#ibcon#about to read 3, iclass 11, count 2 2006.285.22:17:03.38#ibcon#read 3, iclass 11, count 2 2006.285.22:17:03.38#ibcon#about to read 4, iclass 11, count 2 2006.285.22:17:03.38#ibcon#read 4, iclass 11, count 2 2006.285.22:17:03.38#ibcon#about to read 5, iclass 11, count 2 2006.285.22:17:03.38#ibcon#read 5, iclass 11, count 2 2006.285.22:17:03.38#ibcon#about to read 6, iclass 11, count 2 2006.285.22:17:03.38#ibcon#read 6, iclass 11, count 2 2006.285.22:17:03.38#ibcon#end of sib2, iclass 11, count 2 2006.285.22:17:03.38#ibcon#*mode == 0, iclass 11, count 2 2006.285.22:17:03.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.22:17:03.38#ibcon#[25=AT07-04\r\n] 2006.285.22:17:03.38#ibcon#*before write, iclass 11, count 2 2006.285.22:17:03.38#ibcon#enter sib2, iclass 11, count 2 2006.285.22:17:03.38#ibcon#flushed, iclass 11, count 2 2006.285.22:17:03.38#ibcon#about to write, iclass 11, count 2 2006.285.22:17:03.38#ibcon#wrote, iclass 11, count 2 2006.285.22:17:03.38#ibcon#about to read 3, iclass 11, count 2 2006.285.22:17:03.41#ibcon#read 3, iclass 11, count 2 2006.285.22:17:03.41#ibcon#about to read 4, iclass 11, count 2 2006.285.22:17:03.41#ibcon#read 4, iclass 11, count 2 2006.285.22:17:03.41#ibcon#about to read 5, iclass 11, count 2 2006.285.22:17:03.41#ibcon#read 5, iclass 11, count 2 2006.285.22:17:03.41#ibcon#about to read 6, iclass 11, count 2 2006.285.22:17:03.41#ibcon#read 6, iclass 11, count 2 2006.285.22:17:03.41#ibcon#end of sib2, iclass 11, count 2 2006.285.22:17:03.41#ibcon#*after write, iclass 11, count 2 2006.285.22:17:03.41#ibcon#*before return 0, iclass 11, count 2 2006.285.22:17:03.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:17:03.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:17:03.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.22:17:03.41#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:03.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:17:03.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:17:03.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:17:03.53#ibcon#enter wrdev, iclass 11, count 0 2006.285.22:17:03.53#ibcon#first serial, iclass 11, count 0 2006.285.22:17:03.53#ibcon#enter sib2, iclass 11, count 0 2006.285.22:17:03.53#ibcon#flushed, iclass 11, count 0 2006.285.22:17:03.53#ibcon#about to write, iclass 11, count 0 2006.285.22:17:03.53#ibcon#wrote, iclass 11, count 0 2006.285.22:17:03.53#ibcon#about to read 3, iclass 11, count 0 2006.285.22:17:03.55#ibcon#read 3, iclass 11, count 0 2006.285.22:17:03.55#ibcon#about to read 4, iclass 11, count 0 2006.285.22:17:03.55#ibcon#read 4, iclass 11, count 0 2006.285.22:17:03.55#ibcon#about to read 5, iclass 11, count 0 2006.285.22:17:03.55#ibcon#read 5, iclass 11, count 0 2006.285.22:17:03.55#ibcon#about to read 6, iclass 11, count 0 2006.285.22:17:03.55#ibcon#read 6, iclass 11, count 0 2006.285.22:17:03.55#ibcon#end of sib2, iclass 11, count 0 2006.285.22:17:03.55#ibcon#*mode == 0, iclass 11, count 0 2006.285.22:17:03.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.22:17:03.55#ibcon#[25=USB\r\n] 2006.285.22:17:03.55#ibcon#*before write, iclass 11, count 0 2006.285.22:17:03.55#ibcon#enter sib2, iclass 11, count 0 2006.285.22:17:03.55#ibcon#flushed, iclass 11, count 0 2006.285.22:17:03.55#ibcon#about to write, iclass 11, count 0 2006.285.22:17:03.55#ibcon#wrote, iclass 11, count 0 2006.285.22:17:03.55#ibcon#about to read 3, iclass 11, count 0 2006.285.22:17:03.58#ibcon#read 3, iclass 11, count 0 2006.285.22:17:03.58#ibcon#about to read 4, iclass 11, count 0 2006.285.22:17:03.58#ibcon#read 4, iclass 11, count 0 2006.285.22:17:03.58#ibcon#about to read 5, iclass 11, count 0 2006.285.22:17:03.58#ibcon#read 5, iclass 11, count 0 2006.285.22:17:03.58#ibcon#about to read 6, iclass 11, count 0 2006.285.22:17:03.58#ibcon#read 6, iclass 11, count 0 2006.285.22:17:03.58#ibcon#end of sib2, iclass 11, count 0 2006.285.22:17:03.58#ibcon#*after write, iclass 11, count 0 2006.285.22:17:03.58#ibcon#*before return 0, iclass 11, count 0 2006.285.22:17:03.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:17:03.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:17:03.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.22:17:03.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.22:17:03.58$vck44/valo=8,884.99 2006.285.22:17:03.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.22:17:03.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.22:17:03.58#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:03.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:17:03.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:17:03.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:17:03.58#ibcon#enter wrdev, iclass 13, count 0 2006.285.22:17:03.58#ibcon#first serial, iclass 13, count 0 2006.285.22:17:03.58#ibcon#enter sib2, iclass 13, count 0 2006.285.22:17:03.58#ibcon#flushed, iclass 13, count 0 2006.285.22:17:03.58#ibcon#about to write, iclass 13, count 0 2006.285.22:17:03.58#ibcon#wrote, iclass 13, count 0 2006.285.22:17:03.58#ibcon#about to read 3, iclass 13, count 0 2006.285.22:17:03.60#ibcon#read 3, iclass 13, count 0 2006.285.22:17:03.60#ibcon#about to read 4, iclass 13, count 0 2006.285.22:17:03.60#ibcon#read 4, iclass 13, count 0 2006.285.22:17:03.60#ibcon#about to read 5, iclass 13, count 0 2006.285.22:17:03.60#ibcon#read 5, iclass 13, count 0 2006.285.22:17:03.60#ibcon#about to read 6, iclass 13, count 0 2006.285.22:17:03.60#ibcon#read 6, iclass 13, count 0 2006.285.22:17:03.60#ibcon#end of sib2, iclass 13, count 0 2006.285.22:17:03.60#ibcon#*mode == 0, iclass 13, count 0 2006.285.22:17:03.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.22:17:03.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:17:03.60#ibcon#*before write, iclass 13, count 0 2006.285.22:17:03.60#ibcon#enter sib2, iclass 13, count 0 2006.285.22:17:03.60#ibcon#flushed, iclass 13, count 0 2006.285.22:17:03.60#ibcon#about to write, iclass 13, count 0 2006.285.22:17:03.60#ibcon#wrote, iclass 13, count 0 2006.285.22:17:03.60#ibcon#about to read 3, iclass 13, count 0 2006.285.22:17:03.64#ibcon#read 3, iclass 13, count 0 2006.285.22:17:03.64#ibcon#about to read 4, iclass 13, count 0 2006.285.22:17:03.64#ibcon#read 4, iclass 13, count 0 2006.285.22:17:03.64#ibcon#about to read 5, iclass 13, count 0 2006.285.22:17:03.64#ibcon#read 5, iclass 13, count 0 2006.285.22:17:03.64#ibcon#about to read 6, iclass 13, count 0 2006.285.22:17:03.64#ibcon#read 6, iclass 13, count 0 2006.285.22:17:03.64#ibcon#end of sib2, iclass 13, count 0 2006.285.22:17:03.64#ibcon#*after write, iclass 13, count 0 2006.285.22:17:03.64#ibcon#*before return 0, iclass 13, count 0 2006.285.22:17:03.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:17:03.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:17:03.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.22:17:03.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.22:17:03.64$vck44/va=8,3 2006.285.22:17:03.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.22:17:03.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.22:17:03.64#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:03.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:17:03.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:17:03.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:17:03.70#ibcon#enter wrdev, iclass 15, count 2 2006.285.22:17:03.70#ibcon#first serial, iclass 15, count 2 2006.285.22:17:03.70#ibcon#enter sib2, iclass 15, count 2 2006.285.22:17:03.70#ibcon#flushed, iclass 15, count 2 2006.285.22:17:03.70#ibcon#about to write, iclass 15, count 2 2006.285.22:17:03.70#ibcon#wrote, iclass 15, count 2 2006.285.22:17:03.70#ibcon#about to read 3, iclass 15, count 2 2006.285.22:17:03.72#ibcon#read 3, iclass 15, count 2 2006.285.22:17:03.72#ibcon#about to read 4, iclass 15, count 2 2006.285.22:17:03.72#ibcon#read 4, iclass 15, count 2 2006.285.22:17:03.72#ibcon#about to read 5, iclass 15, count 2 2006.285.22:17:03.72#ibcon#read 5, iclass 15, count 2 2006.285.22:17:03.72#ibcon#about to read 6, iclass 15, count 2 2006.285.22:17:03.72#ibcon#read 6, iclass 15, count 2 2006.285.22:17:03.72#ibcon#end of sib2, iclass 15, count 2 2006.285.22:17:03.72#ibcon#*mode == 0, iclass 15, count 2 2006.285.22:17:03.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.22:17:03.72#ibcon#[25=AT08-03\r\n] 2006.285.22:17:03.72#ibcon#*before write, iclass 15, count 2 2006.285.22:17:03.72#ibcon#enter sib2, iclass 15, count 2 2006.285.22:17:03.72#ibcon#flushed, iclass 15, count 2 2006.285.22:17:03.72#ibcon#about to write, iclass 15, count 2 2006.285.22:17:03.72#ibcon#wrote, iclass 15, count 2 2006.285.22:17:03.72#ibcon#about to read 3, iclass 15, count 2 2006.285.22:17:03.75#ibcon#read 3, iclass 15, count 2 2006.285.22:17:03.75#ibcon#about to read 4, iclass 15, count 2 2006.285.22:17:03.75#ibcon#read 4, iclass 15, count 2 2006.285.22:17:03.75#ibcon#about to read 5, iclass 15, count 2 2006.285.22:17:03.75#ibcon#read 5, iclass 15, count 2 2006.285.22:17:03.75#ibcon#about to read 6, iclass 15, count 2 2006.285.22:17:03.75#ibcon#read 6, iclass 15, count 2 2006.285.22:17:03.75#ibcon#end of sib2, iclass 15, count 2 2006.285.22:17:03.75#ibcon#*after write, iclass 15, count 2 2006.285.22:17:03.75#ibcon#*before return 0, iclass 15, count 2 2006.285.22:17:03.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:17:03.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:17:03.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.22:17:03.75#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:03.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:17:03.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:17:03.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:17:03.87#ibcon#enter wrdev, iclass 15, count 0 2006.285.22:17:03.87#ibcon#first serial, iclass 15, count 0 2006.285.22:17:03.87#ibcon#enter sib2, iclass 15, count 0 2006.285.22:17:03.87#ibcon#flushed, iclass 15, count 0 2006.285.22:17:03.87#ibcon#about to write, iclass 15, count 0 2006.285.22:17:03.87#ibcon#wrote, iclass 15, count 0 2006.285.22:17:03.87#ibcon#about to read 3, iclass 15, count 0 2006.285.22:17:03.89#ibcon#read 3, iclass 15, count 0 2006.285.22:17:03.89#ibcon#about to read 4, iclass 15, count 0 2006.285.22:17:03.89#ibcon#read 4, iclass 15, count 0 2006.285.22:17:03.89#ibcon#about to read 5, iclass 15, count 0 2006.285.22:17:03.89#ibcon#read 5, iclass 15, count 0 2006.285.22:17:03.89#ibcon#about to read 6, iclass 15, count 0 2006.285.22:17:03.89#ibcon#read 6, iclass 15, count 0 2006.285.22:17:03.89#ibcon#end of sib2, iclass 15, count 0 2006.285.22:17:03.89#ibcon#*mode == 0, iclass 15, count 0 2006.285.22:17:03.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.22:17:03.89#ibcon#[25=USB\r\n] 2006.285.22:17:03.89#ibcon#*before write, iclass 15, count 0 2006.285.22:17:03.89#ibcon#enter sib2, iclass 15, count 0 2006.285.22:17:03.89#ibcon#flushed, iclass 15, count 0 2006.285.22:17:03.89#ibcon#about to write, iclass 15, count 0 2006.285.22:17:03.89#ibcon#wrote, iclass 15, count 0 2006.285.22:17:03.89#ibcon#about to read 3, iclass 15, count 0 2006.285.22:17:03.92#ibcon#read 3, iclass 15, count 0 2006.285.22:17:03.92#ibcon#about to read 4, iclass 15, count 0 2006.285.22:17:03.92#ibcon#read 4, iclass 15, count 0 2006.285.22:17:03.92#ibcon#about to read 5, iclass 15, count 0 2006.285.22:17:03.92#ibcon#read 5, iclass 15, count 0 2006.285.22:17:03.92#ibcon#about to read 6, iclass 15, count 0 2006.285.22:17:03.92#ibcon#read 6, iclass 15, count 0 2006.285.22:17:03.92#ibcon#end of sib2, iclass 15, count 0 2006.285.22:17:03.92#ibcon#*after write, iclass 15, count 0 2006.285.22:17:03.92#ibcon#*before return 0, iclass 15, count 0 2006.285.22:17:03.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:17:03.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:17:03.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.22:17:03.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.22:17:03.92$vck44/vblo=1,629.99 2006.285.22:17:03.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.22:17:03.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.22:17:03.92#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:03.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:17:03.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:17:03.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:17:03.92#ibcon#enter wrdev, iclass 17, count 0 2006.285.22:17:03.92#ibcon#first serial, iclass 17, count 0 2006.285.22:17:03.92#ibcon#enter sib2, iclass 17, count 0 2006.285.22:17:03.92#ibcon#flushed, iclass 17, count 0 2006.285.22:17:03.92#ibcon#about to write, iclass 17, count 0 2006.285.22:17:03.92#ibcon#wrote, iclass 17, count 0 2006.285.22:17:03.92#ibcon#about to read 3, iclass 17, count 0 2006.285.22:17:03.94#ibcon#read 3, iclass 17, count 0 2006.285.22:17:03.94#ibcon#about to read 4, iclass 17, count 0 2006.285.22:17:03.94#ibcon#read 4, iclass 17, count 0 2006.285.22:17:03.94#ibcon#about to read 5, iclass 17, count 0 2006.285.22:17:03.94#ibcon#read 5, iclass 17, count 0 2006.285.22:17:03.94#ibcon#about to read 6, iclass 17, count 0 2006.285.22:17:03.94#ibcon#read 6, iclass 17, count 0 2006.285.22:17:03.94#ibcon#end of sib2, iclass 17, count 0 2006.285.22:17:03.94#ibcon#*mode == 0, iclass 17, count 0 2006.285.22:17:03.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.22:17:03.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:17:03.94#ibcon#*before write, iclass 17, count 0 2006.285.22:17:03.94#ibcon#enter sib2, iclass 17, count 0 2006.285.22:17:03.94#ibcon#flushed, iclass 17, count 0 2006.285.22:17:03.94#ibcon#about to write, iclass 17, count 0 2006.285.22:17:03.94#ibcon#wrote, iclass 17, count 0 2006.285.22:17:03.94#ibcon#about to read 3, iclass 17, count 0 2006.285.22:17:03.98#ibcon#read 3, iclass 17, count 0 2006.285.22:17:03.98#ibcon#about to read 4, iclass 17, count 0 2006.285.22:17:03.98#ibcon#read 4, iclass 17, count 0 2006.285.22:17:03.98#ibcon#about to read 5, iclass 17, count 0 2006.285.22:17:03.98#ibcon#read 5, iclass 17, count 0 2006.285.22:17:03.98#ibcon#about to read 6, iclass 17, count 0 2006.285.22:17:03.98#ibcon#read 6, iclass 17, count 0 2006.285.22:17:03.98#ibcon#end of sib2, iclass 17, count 0 2006.285.22:17:03.98#ibcon#*after write, iclass 17, count 0 2006.285.22:17:03.98#ibcon#*before return 0, iclass 17, count 0 2006.285.22:17:03.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:17:03.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:17:03.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.22:17:03.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.22:17:03.98$vck44/vb=1,4 2006.285.22:17:03.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.22:17:03.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.22:17:03.98#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:03.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:17:03.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:17:03.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:17:03.98#ibcon#enter wrdev, iclass 19, count 2 2006.285.22:17:03.98#ibcon#first serial, iclass 19, count 2 2006.285.22:17:03.98#ibcon#enter sib2, iclass 19, count 2 2006.285.22:17:03.98#ibcon#flushed, iclass 19, count 2 2006.285.22:17:03.98#ibcon#about to write, iclass 19, count 2 2006.285.22:17:03.98#ibcon#wrote, iclass 19, count 2 2006.285.22:17:03.98#ibcon#about to read 3, iclass 19, count 2 2006.285.22:17:04.00#ibcon#read 3, iclass 19, count 2 2006.285.22:17:04.00#ibcon#about to read 4, iclass 19, count 2 2006.285.22:17:04.00#ibcon#read 4, iclass 19, count 2 2006.285.22:17:04.00#ibcon#about to read 5, iclass 19, count 2 2006.285.22:17:04.00#ibcon#read 5, iclass 19, count 2 2006.285.22:17:04.00#ibcon#about to read 6, iclass 19, count 2 2006.285.22:17:04.00#ibcon#read 6, iclass 19, count 2 2006.285.22:17:04.00#ibcon#end of sib2, iclass 19, count 2 2006.285.22:17:04.00#ibcon#*mode == 0, iclass 19, count 2 2006.285.22:17:04.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.22:17:04.00#ibcon#[27=AT01-04\r\n] 2006.285.22:17:04.00#ibcon#*before write, iclass 19, count 2 2006.285.22:17:04.00#ibcon#enter sib2, iclass 19, count 2 2006.285.22:17:04.00#ibcon#flushed, iclass 19, count 2 2006.285.22:17:04.00#ibcon#about to write, iclass 19, count 2 2006.285.22:17:04.00#ibcon#wrote, iclass 19, count 2 2006.285.22:17:04.00#ibcon#about to read 3, iclass 19, count 2 2006.285.22:17:04.03#ibcon#read 3, iclass 19, count 2 2006.285.22:17:04.03#ibcon#about to read 4, iclass 19, count 2 2006.285.22:17:04.03#ibcon#read 4, iclass 19, count 2 2006.285.22:17:04.03#ibcon#about to read 5, iclass 19, count 2 2006.285.22:17:04.03#ibcon#read 5, iclass 19, count 2 2006.285.22:17:04.03#ibcon#about to read 6, iclass 19, count 2 2006.285.22:17:04.03#ibcon#read 6, iclass 19, count 2 2006.285.22:17:04.03#ibcon#end of sib2, iclass 19, count 2 2006.285.22:17:04.03#ibcon#*after write, iclass 19, count 2 2006.285.22:17:04.03#ibcon#*before return 0, iclass 19, count 2 2006.285.22:17:04.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:17:04.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:17:04.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.22:17:04.03#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:04.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:17:04.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:17:04.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:17:04.15#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:17:04.15#ibcon#first serial, iclass 19, count 0 2006.285.22:17:04.15#ibcon#enter sib2, iclass 19, count 0 2006.285.22:17:04.15#ibcon#flushed, iclass 19, count 0 2006.285.22:17:04.15#ibcon#about to write, iclass 19, count 0 2006.285.22:17:04.15#ibcon#wrote, iclass 19, count 0 2006.285.22:17:04.15#ibcon#about to read 3, iclass 19, count 0 2006.285.22:17:04.17#ibcon#read 3, iclass 19, count 0 2006.285.22:17:04.17#ibcon#about to read 4, iclass 19, count 0 2006.285.22:17:04.17#ibcon#read 4, iclass 19, count 0 2006.285.22:17:04.17#ibcon#about to read 5, iclass 19, count 0 2006.285.22:17:04.17#ibcon#read 5, iclass 19, count 0 2006.285.22:17:04.17#ibcon#about to read 6, iclass 19, count 0 2006.285.22:17:04.17#ibcon#read 6, iclass 19, count 0 2006.285.22:17:04.17#ibcon#end of sib2, iclass 19, count 0 2006.285.22:17:04.17#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:17:04.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:17:04.17#ibcon#[27=USB\r\n] 2006.285.22:17:04.17#ibcon#*before write, iclass 19, count 0 2006.285.22:17:04.17#ibcon#enter sib2, iclass 19, count 0 2006.285.22:17:04.17#ibcon#flushed, iclass 19, count 0 2006.285.22:17:04.17#ibcon#about to write, iclass 19, count 0 2006.285.22:17:04.17#ibcon#wrote, iclass 19, count 0 2006.285.22:17:04.17#ibcon#about to read 3, iclass 19, count 0 2006.285.22:17:04.20#ibcon#read 3, iclass 19, count 0 2006.285.22:17:04.20#ibcon#about to read 4, iclass 19, count 0 2006.285.22:17:04.20#ibcon#read 4, iclass 19, count 0 2006.285.22:17:04.20#ibcon#about to read 5, iclass 19, count 0 2006.285.22:17:04.20#ibcon#read 5, iclass 19, count 0 2006.285.22:17:04.20#ibcon#about to read 6, iclass 19, count 0 2006.285.22:17:04.20#ibcon#read 6, iclass 19, count 0 2006.285.22:17:04.20#ibcon#end of sib2, iclass 19, count 0 2006.285.22:17:04.20#ibcon#*after write, iclass 19, count 0 2006.285.22:17:04.20#ibcon#*before return 0, iclass 19, count 0 2006.285.22:17:04.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:17:04.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:17:04.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:17:04.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:17:04.20$vck44/vblo=2,634.99 2006.285.22:17:04.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.22:17:04.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.22:17:04.20#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:04.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:17:04.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:17:04.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:17:04.20#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:17:04.20#ibcon#first serial, iclass 21, count 0 2006.285.22:17:04.20#ibcon#enter sib2, iclass 21, count 0 2006.285.22:17:04.20#ibcon#flushed, iclass 21, count 0 2006.285.22:17:04.20#ibcon#about to write, iclass 21, count 0 2006.285.22:17:04.20#ibcon#wrote, iclass 21, count 0 2006.285.22:17:04.20#ibcon#about to read 3, iclass 21, count 0 2006.285.22:17:04.22#ibcon#read 3, iclass 21, count 0 2006.285.22:17:04.22#ibcon#about to read 4, iclass 21, count 0 2006.285.22:17:04.22#ibcon#read 4, iclass 21, count 0 2006.285.22:17:04.22#ibcon#about to read 5, iclass 21, count 0 2006.285.22:17:04.22#ibcon#read 5, iclass 21, count 0 2006.285.22:17:04.22#ibcon#about to read 6, iclass 21, count 0 2006.285.22:17:04.22#ibcon#read 6, iclass 21, count 0 2006.285.22:17:04.22#ibcon#end of sib2, iclass 21, count 0 2006.285.22:17:04.22#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:17:04.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:17:04.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:17:04.22#ibcon#*before write, iclass 21, count 0 2006.285.22:17:04.22#ibcon#enter sib2, iclass 21, count 0 2006.285.22:17:04.22#ibcon#flushed, iclass 21, count 0 2006.285.22:17:04.22#ibcon#about to write, iclass 21, count 0 2006.285.22:17:04.22#ibcon#wrote, iclass 21, count 0 2006.285.22:17:04.22#ibcon#about to read 3, iclass 21, count 0 2006.285.22:17:04.26#ibcon#read 3, iclass 21, count 0 2006.285.22:17:04.26#ibcon#about to read 4, iclass 21, count 0 2006.285.22:17:04.26#ibcon#read 4, iclass 21, count 0 2006.285.22:17:04.26#ibcon#about to read 5, iclass 21, count 0 2006.285.22:17:04.26#ibcon#read 5, iclass 21, count 0 2006.285.22:17:04.26#ibcon#about to read 6, iclass 21, count 0 2006.285.22:17:04.26#ibcon#read 6, iclass 21, count 0 2006.285.22:17:04.26#ibcon#end of sib2, iclass 21, count 0 2006.285.22:17:04.26#ibcon#*after write, iclass 21, count 0 2006.285.22:17:04.26#ibcon#*before return 0, iclass 21, count 0 2006.285.22:17:04.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:17:04.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:17:04.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:17:04.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:17:04.26$vck44/vb=2,5 2006.285.22:17:04.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.22:17:04.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.22:17:04.26#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:04.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:17:04.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:17:04.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:17:04.32#ibcon#enter wrdev, iclass 23, count 2 2006.285.22:17:04.32#ibcon#first serial, iclass 23, count 2 2006.285.22:17:04.32#ibcon#enter sib2, iclass 23, count 2 2006.285.22:17:04.32#ibcon#flushed, iclass 23, count 2 2006.285.22:17:04.32#ibcon#about to write, iclass 23, count 2 2006.285.22:17:04.32#ibcon#wrote, iclass 23, count 2 2006.285.22:17:04.32#ibcon#about to read 3, iclass 23, count 2 2006.285.22:17:04.34#ibcon#read 3, iclass 23, count 2 2006.285.22:17:04.34#ibcon#about to read 4, iclass 23, count 2 2006.285.22:17:04.34#ibcon#read 4, iclass 23, count 2 2006.285.22:17:04.34#ibcon#about to read 5, iclass 23, count 2 2006.285.22:17:04.34#ibcon#read 5, iclass 23, count 2 2006.285.22:17:04.34#ibcon#about to read 6, iclass 23, count 2 2006.285.22:17:04.34#ibcon#read 6, iclass 23, count 2 2006.285.22:17:04.34#ibcon#end of sib2, iclass 23, count 2 2006.285.22:17:04.34#ibcon#*mode == 0, iclass 23, count 2 2006.285.22:17:04.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.22:17:04.34#ibcon#[27=AT02-05\r\n] 2006.285.22:17:04.34#ibcon#*before write, iclass 23, count 2 2006.285.22:17:04.34#ibcon#enter sib2, iclass 23, count 2 2006.285.22:17:04.34#ibcon#flushed, iclass 23, count 2 2006.285.22:17:04.34#ibcon#about to write, iclass 23, count 2 2006.285.22:17:04.34#ibcon#wrote, iclass 23, count 2 2006.285.22:17:04.34#ibcon#about to read 3, iclass 23, count 2 2006.285.22:17:04.37#ibcon#read 3, iclass 23, count 2 2006.285.22:17:04.37#ibcon#about to read 4, iclass 23, count 2 2006.285.22:17:04.37#ibcon#read 4, iclass 23, count 2 2006.285.22:17:04.37#ibcon#about to read 5, iclass 23, count 2 2006.285.22:17:04.37#ibcon#read 5, iclass 23, count 2 2006.285.22:17:04.37#ibcon#about to read 6, iclass 23, count 2 2006.285.22:17:04.37#ibcon#read 6, iclass 23, count 2 2006.285.22:17:04.37#ibcon#end of sib2, iclass 23, count 2 2006.285.22:17:04.37#ibcon#*after write, iclass 23, count 2 2006.285.22:17:04.37#ibcon#*before return 0, iclass 23, count 2 2006.285.22:17:04.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:17:04.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:17:04.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.22:17:04.37#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:04.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:17:04.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:17:04.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:17:04.49#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:17:04.49#ibcon#first serial, iclass 23, count 0 2006.285.22:17:04.49#ibcon#enter sib2, iclass 23, count 0 2006.285.22:17:04.49#ibcon#flushed, iclass 23, count 0 2006.285.22:17:04.49#ibcon#about to write, iclass 23, count 0 2006.285.22:17:04.49#ibcon#wrote, iclass 23, count 0 2006.285.22:17:04.49#ibcon#about to read 3, iclass 23, count 0 2006.285.22:17:04.51#ibcon#read 3, iclass 23, count 0 2006.285.22:17:04.51#ibcon#about to read 4, iclass 23, count 0 2006.285.22:17:04.51#ibcon#read 4, iclass 23, count 0 2006.285.22:17:04.51#ibcon#about to read 5, iclass 23, count 0 2006.285.22:17:04.51#ibcon#read 5, iclass 23, count 0 2006.285.22:17:04.51#ibcon#about to read 6, iclass 23, count 0 2006.285.22:17:04.51#ibcon#read 6, iclass 23, count 0 2006.285.22:17:04.51#ibcon#end of sib2, iclass 23, count 0 2006.285.22:17:04.51#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:17:04.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:17:04.51#ibcon#[27=USB\r\n] 2006.285.22:17:04.51#ibcon#*before write, iclass 23, count 0 2006.285.22:17:04.51#ibcon#enter sib2, iclass 23, count 0 2006.285.22:17:04.51#ibcon#flushed, iclass 23, count 0 2006.285.22:17:04.51#ibcon#about to write, iclass 23, count 0 2006.285.22:17:04.51#ibcon#wrote, iclass 23, count 0 2006.285.22:17:04.51#ibcon#about to read 3, iclass 23, count 0 2006.285.22:17:04.54#ibcon#read 3, iclass 23, count 0 2006.285.22:17:04.54#ibcon#about to read 4, iclass 23, count 0 2006.285.22:17:04.54#ibcon#read 4, iclass 23, count 0 2006.285.22:17:04.54#ibcon#about to read 5, iclass 23, count 0 2006.285.22:17:04.54#ibcon#read 5, iclass 23, count 0 2006.285.22:17:04.54#ibcon#about to read 6, iclass 23, count 0 2006.285.22:17:04.54#ibcon#read 6, iclass 23, count 0 2006.285.22:17:04.54#ibcon#end of sib2, iclass 23, count 0 2006.285.22:17:04.54#ibcon#*after write, iclass 23, count 0 2006.285.22:17:04.54#ibcon#*before return 0, iclass 23, count 0 2006.285.22:17:04.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:17:04.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:17:04.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:17:04.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:17:04.54$vck44/vblo=3,649.99 2006.285.22:17:04.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.22:17:04.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.22:17:04.54#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:04.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:17:04.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:17:04.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:17:04.54#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:17:04.54#ibcon#first serial, iclass 25, count 0 2006.285.22:17:04.54#ibcon#enter sib2, iclass 25, count 0 2006.285.22:17:04.54#ibcon#flushed, iclass 25, count 0 2006.285.22:17:04.54#ibcon#about to write, iclass 25, count 0 2006.285.22:17:04.54#ibcon#wrote, iclass 25, count 0 2006.285.22:17:04.54#ibcon#about to read 3, iclass 25, count 0 2006.285.22:17:04.56#ibcon#read 3, iclass 25, count 0 2006.285.22:17:04.56#ibcon#about to read 4, iclass 25, count 0 2006.285.22:17:04.56#ibcon#read 4, iclass 25, count 0 2006.285.22:17:04.56#ibcon#about to read 5, iclass 25, count 0 2006.285.22:17:04.56#ibcon#read 5, iclass 25, count 0 2006.285.22:17:04.56#ibcon#about to read 6, iclass 25, count 0 2006.285.22:17:04.56#ibcon#read 6, iclass 25, count 0 2006.285.22:17:04.56#ibcon#end of sib2, iclass 25, count 0 2006.285.22:17:04.56#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:17:04.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:17:04.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:17:04.56#ibcon#*before write, iclass 25, count 0 2006.285.22:17:04.56#ibcon#enter sib2, iclass 25, count 0 2006.285.22:17:04.56#ibcon#flushed, iclass 25, count 0 2006.285.22:17:04.56#ibcon#about to write, iclass 25, count 0 2006.285.22:17:04.56#ibcon#wrote, iclass 25, count 0 2006.285.22:17:04.56#ibcon#about to read 3, iclass 25, count 0 2006.285.22:17:04.60#ibcon#read 3, iclass 25, count 0 2006.285.22:17:04.60#ibcon#about to read 4, iclass 25, count 0 2006.285.22:17:04.60#ibcon#read 4, iclass 25, count 0 2006.285.22:17:04.60#ibcon#about to read 5, iclass 25, count 0 2006.285.22:17:04.60#ibcon#read 5, iclass 25, count 0 2006.285.22:17:04.60#ibcon#about to read 6, iclass 25, count 0 2006.285.22:17:04.60#ibcon#read 6, iclass 25, count 0 2006.285.22:17:04.60#ibcon#end of sib2, iclass 25, count 0 2006.285.22:17:04.60#ibcon#*after write, iclass 25, count 0 2006.285.22:17:04.60#ibcon#*before return 0, iclass 25, count 0 2006.285.22:17:04.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:17:04.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:17:04.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:17:04.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:17:04.60$vck44/vb=3,4 2006.285.22:17:04.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.22:17:04.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.22:17:04.60#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:04.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:17:04.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:17:04.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:17:04.66#ibcon#enter wrdev, iclass 27, count 2 2006.285.22:17:04.66#ibcon#first serial, iclass 27, count 2 2006.285.22:17:04.66#ibcon#enter sib2, iclass 27, count 2 2006.285.22:17:04.66#ibcon#flushed, iclass 27, count 2 2006.285.22:17:04.66#ibcon#about to write, iclass 27, count 2 2006.285.22:17:04.66#ibcon#wrote, iclass 27, count 2 2006.285.22:17:04.66#ibcon#about to read 3, iclass 27, count 2 2006.285.22:17:04.68#ibcon#read 3, iclass 27, count 2 2006.285.22:17:04.68#ibcon#about to read 4, iclass 27, count 2 2006.285.22:17:04.68#ibcon#read 4, iclass 27, count 2 2006.285.22:17:04.68#ibcon#about to read 5, iclass 27, count 2 2006.285.22:17:04.68#ibcon#read 5, iclass 27, count 2 2006.285.22:17:04.68#ibcon#about to read 6, iclass 27, count 2 2006.285.22:17:04.68#ibcon#read 6, iclass 27, count 2 2006.285.22:17:04.68#ibcon#end of sib2, iclass 27, count 2 2006.285.22:17:04.68#ibcon#*mode == 0, iclass 27, count 2 2006.285.22:17:04.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.22:17:04.68#ibcon#[27=AT03-04\r\n] 2006.285.22:17:04.68#ibcon#*before write, iclass 27, count 2 2006.285.22:17:04.68#ibcon#enter sib2, iclass 27, count 2 2006.285.22:17:04.68#ibcon#flushed, iclass 27, count 2 2006.285.22:17:04.68#ibcon#about to write, iclass 27, count 2 2006.285.22:17:04.68#ibcon#wrote, iclass 27, count 2 2006.285.22:17:04.68#ibcon#about to read 3, iclass 27, count 2 2006.285.22:17:04.71#ibcon#read 3, iclass 27, count 2 2006.285.22:17:04.71#ibcon#about to read 4, iclass 27, count 2 2006.285.22:17:04.71#ibcon#read 4, iclass 27, count 2 2006.285.22:17:04.71#ibcon#about to read 5, iclass 27, count 2 2006.285.22:17:04.71#ibcon#read 5, iclass 27, count 2 2006.285.22:17:04.71#ibcon#about to read 6, iclass 27, count 2 2006.285.22:17:04.71#ibcon#read 6, iclass 27, count 2 2006.285.22:17:04.71#ibcon#end of sib2, iclass 27, count 2 2006.285.22:17:04.71#ibcon#*after write, iclass 27, count 2 2006.285.22:17:04.71#ibcon#*before return 0, iclass 27, count 2 2006.285.22:17:04.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:17:04.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:17:04.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.22:17:04.71#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:04.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:17:04.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:17:04.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:17:04.83#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:17:04.83#ibcon#first serial, iclass 27, count 0 2006.285.22:17:04.83#ibcon#enter sib2, iclass 27, count 0 2006.285.22:17:04.83#ibcon#flushed, iclass 27, count 0 2006.285.22:17:04.83#ibcon#about to write, iclass 27, count 0 2006.285.22:17:04.83#ibcon#wrote, iclass 27, count 0 2006.285.22:17:04.83#ibcon#about to read 3, iclass 27, count 0 2006.285.22:17:04.85#ibcon#read 3, iclass 27, count 0 2006.285.22:17:04.85#ibcon#about to read 4, iclass 27, count 0 2006.285.22:17:04.85#ibcon#read 4, iclass 27, count 0 2006.285.22:17:04.85#ibcon#about to read 5, iclass 27, count 0 2006.285.22:17:04.85#ibcon#read 5, iclass 27, count 0 2006.285.22:17:04.85#ibcon#about to read 6, iclass 27, count 0 2006.285.22:17:04.85#ibcon#read 6, iclass 27, count 0 2006.285.22:17:04.85#ibcon#end of sib2, iclass 27, count 0 2006.285.22:17:04.85#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:17:04.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:17:04.85#ibcon#[27=USB\r\n] 2006.285.22:17:04.85#ibcon#*before write, iclass 27, count 0 2006.285.22:17:04.85#ibcon#enter sib2, iclass 27, count 0 2006.285.22:17:04.85#ibcon#flushed, iclass 27, count 0 2006.285.22:17:04.85#ibcon#about to write, iclass 27, count 0 2006.285.22:17:04.85#ibcon#wrote, iclass 27, count 0 2006.285.22:17:04.85#ibcon#about to read 3, iclass 27, count 0 2006.285.22:17:04.88#ibcon#read 3, iclass 27, count 0 2006.285.22:17:04.88#ibcon#about to read 4, iclass 27, count 0 2006.285.22:17:04.88#ibcon#read 4, iclass 27, count 0 2006.285.22:17:04.88#ibcon#about to read 5, iclass 27, count 0 2006.285.22:17:04.88#ibcon#read 5, iclass 27, count 0 2006.285.22:17:04.88#ibcon#about to read 6, iclass 27, count 0 2006.285.22:17:04.88#ibcon#read 6, iclass 27, count 0 2006.285.22:17:04.88#ibcon#end of sib2, iclass 27, count 0 2006.285.22:17:04.88#ibcon#*after write, iclass 27, count 0 2006.285.22:17:04.88#ibcon#*before return 0, iclass 27, count 0 2006.285.22:17:04.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:17:04.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:17:04.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:17:04.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:17:04.88$vck44/vblo=4,679.99 2006.285.22:17:04.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.22:17:04.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.22:17:04.88#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:04.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:17:04.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:17:04.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:17:04.88#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:17:04.88#ibcon#first serial, iclass 29, count 0 2006.285.22:17:04.88#ibcon#enter sib2, iclass 29, count 0 2006.285.22:17:04.88#ibcon#flushed, iclass 29, count 0 2006.285.22:17:04.88#ibcon#about to write, iclass 29, count 0 2006.285.22:17:04.88#ibcon#wrote, iclass 29, count 0 2006.285.22:17:04.88#ibcon#about to read 3, iclass 29, count 0 2006.285.22:17:04.90#ibcon#read 3, iclass 29, count 0 2006.285.22:17:04.90#ibcon#about to read 4, iclass 29, count 0 2006.285.22:17:04.90#ibcon#read 4, iclass 29, count 0 2006.285.22:17:04.90#ibcon#about to read 5, iclass 29, count 0 2006.285.22:17:04.90#ibcon#read 5, iclass 29, count 0 2006.285.22:17:04.90#ibcon#about to read 6, iclass 29, count 0 2006.285.22:17:04.90#ibcon#read 6, iclass 29, count 0 2006.285.22:17:04.90#ibcon#end of sib2, iclass 29, count 0 2006.285.22:17:04.90#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:17:04.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:17:04.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.22:17:04.90#ibcon#*before write, iclass 29, count 0 2006.285.22:17:04.90#ibcon#enter sib2, iclass 29, count 0 2006.285.22:17:04.90#ibcon#flushed, iclass 29, count 0 2006.285.22:17:04.90#ibcon#about to write, iclass 29, count 0 2006.285.22:17:04.90#ibcon#wrote, iclass 29, count 0 2006.285.22:17:04.90#ibcon#about to read 3, iclass 29, count 0 2006.285.22:17:04.94#ibcon#read 3, iclass 29, count 0 2006.285.22:17:04.94#ibcon#about to read 4, iclass 29, count 0 2006.285.22:17:04.94#ibcon#read 4, iclass 29, count 0 2006.285.22:17:04.94#ibcon#about to read 5, iclass 29, count 0 2006.285.22:17:04.94#ibcon#read 5, iclass 29, count 0 2006.285.22:17:04.94#ibcon#about to read 6, iclass 29, count 0 2006.285.22:17:04.94#ibcon#read 6, iclass 29, count 0 2006.285.22:17:04.94#ibcon#end of sib2, iclass 29, count 0 2006.285.22:17:04.94#ibcon#*after write, iclass 29, count 0 2006.285.22:17:04.94#ibcon#*before return 0, iclass 29, count 0 2006.285.22:17:04.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:17:04.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:17:04.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:17:04.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:17:04.94$vck44/vb=4,5 2006.285.22:17:04.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.22:17:04.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.22:17:04.94#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:04.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:17:05.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:17:05.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:17:05.00#ibcon#enter wrdev, iclass 31, count 2 2006.285.22:17:05.00#ibcon#first serial, iclass 31, count 2 2006.285.22:17:05.00#ibcon#enter sib2, iclass 31, count 2 2006.285.22:17:05.00#ibcon#flushed, iclass 31, count 2 2006.285.22:17:05.00#ibcon#about to write, iclass 31, count 2 2006.285.22:17:05.00#ibcon#wrote, iclass 31, count 2 2006.285.22:17:05.00#ibcon#about to read 3, iclass 31, count 2 2006.285.22:17:05.02#ibcon#read 3, iclass 31, count 2 2006.285.22:17:05.02#ibcon#about to read 4, iclass 31, count 2 2006.285.22:17:05.02#ibcon#read 4, iclass 31, count 2 2006.285.22:17:05.02#ibcon#about to read 5, iclass 31, count 2 2006.285.22:17:05.02#ibcon#read 5, iclass 31, count 2 2006.285.22:17:05.02#ibcon#about to read 6, iclass 31, count 2 2006.285.22:17:05.02#ibcon#read 6, iclass 31, count 2 2006.285.22:17:05.02#ibcon#end of sib2, iclass 31, count 2 2006.285.22:17:05.02#ibcon#*mode == 0, iclass 31, count 2 2006.285.22:17:05.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.22:17:05.02#ibcon#[27=AT04-05\r\n] 2006.285.22:17:05.02#ibcon#*before write, iclass 31, count 2 2006.285.22:17:05.02#ibcon#enter sib2, iclass 31, count 2 2006.285.22:17:05.02#ibcon#flushed, iclass 31, count 2 2006.285.22:17:05.02#ibcon#about to write, iclass 31, count 2 2006.285.22:17:05.02#ibcon#wrote, iclass 31, count 2 2006.285.22:17:05.02#ibcon#about to read 3, iclass 31, count 2 2006.285.22:17:05.05#ibcon#read 3, iclass 31, count 2 2006.285.22:17:05.05#ibcon#about to read 4, iclass 31, count 2 2006.285.22:17:05.05#ibcon#read 4, iclass 31, count 2 2006.285.22:17:05.05#ibcon#about to read 5, iclass 31, count 2 2006.285.22:17:05.05#ibcon#read 5, iclass 31, count 2 2006.285.22:17:05.05#ibcon#about to read 6, iclass 31, count 2 2006.285.22:17:05.05#ibcon#read 6, iclass 31, count 2 2006.285.22:17:05.05#ibcon#end of sib2, iclass 31, count 2 2006.285.22:17:05.05#ibcon#*after write, iclass 31, count 2 2006.285.22:17:05.05#ibcon#*before return 0, iclass 31, count 2 2006.285.22:17:05.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:17:05.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:17:05.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.22:17:05.05#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:05.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:17:05.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:17:05.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:17:05.17#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:17:05.17#ibcon#first serial, iclass 31, count 0 2006.285.22:17:05.17#ibcon#enter sib2, iclass 31, count 0 2006.285.22:17:05.17#ibcon#flushed, iclass 31, count 0 2006.285.22:17:05.17#ibcon#about to write, iclass 31, count 0 2006.285.22:17:05.17#ibcon#wrote, iclass 31, count 0 2006.285.22:17:05.17#ibcon#about to read 3, iclass 31, count 0 2006.285.22:17:05.19#ibcon#read 3, iclass 31, count 0 2006.285.22:17:05.19#ibcon#about to read 4, iclass 31, count 0 2006.285.22:17:05.19#ibcon#read 4, iclass 31, count 0 2006.285.22:17:05.19#ibcon#about to read 5, iclass 31, count 0 2006.285.22:17:05.19#ibcon#read 5, iclass 31, count 0 2006.285.22:17:05.19#ibcon#about to read 6, iclass 31, count 0 2006.285.22:17:05.19#ibcon#read 6, iclass 31, count 0 2006.285.22:17:05.19#ibcon#end of sib2, iclass 31, count 0 2006.285.22:17:05.19#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:17:05.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:17:05.19#ibcon#[27=USB\r\n] 2006.285.22:17:05.19#ibcon#*before write, iclass 31, count 0 2006.285.22:17:05.19#ibcon#enter sib2, iclass 31, count 0 2006.285.22:17:05.19#ibcon#flushed, iclass 31, count 0 2006.285.22:17:05.19#ibcon#about to write, iclass 31, count 0 2006.285.22:17:05.19#ibcon#wrote, iclass 31, count 0 2006.285.22:17:05.19#ibcon#about to read 3, iclass 31, count 0 2006.285.22:17:05.22#ibcon#read 3, iclass 31, count 0 2006.285.22:17:05.22#ibcon#about to read 4, iclass 31, count 0 2006.285.22:17:05.22#ibcon#read 4, iclass 31, count 0 2006.285.22:17:05.22#ibcon#about to read 5, iclass 31, count 0 2006.285.22:17:05.22#ibcon#read 5, iclass 31, count 0 2006.285.22:17:05.22#ibcon#about to read 6, iclass 31, count 0 2006.285.22:17:05.22#ibcon#read 6, iclass 31, count 0 2006.285.22:17:05.22#ibcon#end of sib2, iclass 31, count 0 2006.285.22:17:05.22#ibcon#*after write, iclass 31, count 0 2006.285.22:17:05.22#ibcon#*before return 0, iclass 31, count 0 2006.285.22:17:05.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:17:05.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:17:05.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:17:05.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:17:05.22$vck44/vblo=5,709.99 2006.285.22:17:05.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.22:17:05.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.22:17:05.22#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:05.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:17:05.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:17:05.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:17:05.22#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:17:05.22#ibcon#first serial, iclass 33, count 0 2006.285.22:17:05.22#ibcon#enter sib2, iclass 33, count 0 2006.285.22:17:05.22#ibcon#flushed, iclass 33, count 0 2006.285.22:17:05.22#ibcon#about to write, iclass 33, count 0 2006.285.22:17:05.22#ibcon#wrote, iclass 33, count 0 2006.285.22:17:05.22#ibcon#about to read 3, iclass 33, count 0 2006.285.22:17:05.24#ibcon#read 3, iclass 33, count 0 2006.285.22:17:05.24#ibcon#about to read 4, iclass 33, count 0 2006.285.22:17:05.24#ibcon#read 4, iclass 33, count 0 2006.285.22:17:05.24#ibcon#about to read 5, iclass 33, count 0 2006.285.22:17:05.24#ibcon#read 5, iclass 33, count 0 2006.285.22:17:05.24#ibcon#about to read 6, iclass 33, count 0 2006.285.22:17:05.24#ibcon#read 6, iclass 33, count 0 2006.285.22:17:05.24#ibcon#end of sib2, iclass 33, count 0 2006.285.22:17:05.24#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:17:05.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:17:05.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.22:17:05.24#ibcon#*before write, iclass 33, count 0 2006.285.22:17:05.24#ibcon#enter sib2, iclass 33, count 0 2006.285.22:17:05.24#ibcon#flushed, iclass 33, count 0 2006.285.22:17:05.24#ibcon#about to write, iclass 33, count 0 2006.285.22:17:05.24#ibcon#wrote, iclass 33, count 0 2006.285.22:17:05.24#ibcon#about to read 3, iclass 33, count 0 2006.285.22:17:05.28#ibcon#read 3, iclass 33, count 0 2006.285.22:17:05.28#ibcon#about to read 4, iclass 33, count 0 2006.285.22:17:05.28#ibcon#read 4, iclass 33, count 0 2006.285.22:17:05.28#ibcon#about to read 5, iclass 33, count 0 2006.285.22:17:05.28#ibcon#read 5, iclass 33, count 0 2006.285.22:17:05.28#ibcon#about to read 6, iclass 33, count 0 2006.285.22:17:05.28#ibcon#read 6, iclass 33, count 0 2006.285.22:17:05.28#ibcon#end of sib2, iclass 33, count 0 2006.285.22:17:05.28#ibcon#*after write, iclass 33, count 0 2006.285.22:17:05.28#ibcon#*before return 0, iclass 33, count 0 2006.285.22:17:05.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:17:05.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:17:05.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:17:05.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:17:05.28$vck44/vb=5,4 2006.285.22:17:05.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.22:17:05.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.22:17:05.28#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:05.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:17:05.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:17:05.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:17:05.34#ibcon#enter wrdev, iclass 35, count 2 2006.285.22:17:05.34#ibcon#first serial, iclass 35, count 2 2006.285.22:17:05.34#ibcon#enter sib2, iclass 35, count 2 2006.285.22:17:05.34#ibcon#flushed, iclass 35, count 2 2006.285.22:17:05.34#ibcon#about to write, iclass 35, count 2 2006.285.22:17:05.34#ibcon#wrote, iclass 35, count 2 2006.285.22:17:05.34#ibcon#about to read 3, iclass 35, count 2 2006.285.22:17:05.36#ibcon#read 3, iclass 35, count 2 2006.285.22:17:05.36#ibcon#about to read 4, iclass 35, count 2 2006.285.22:17:05.36#ibcon#read 4, iclass 35, count 2 2006.285.22:17:05.36#ibcon#about to read 5, iclass 35, count 2 2006.285.22:17:05.36#ibcon#read 5, iclass 35, count 2 2006.285.22:17:05.36#ibcon#about to read 6, iclass 35, count 2 2006.285.22:17:05.36#ibcon#read 6, iclass 35, count 2 2006.285.22:17:05.36#ibcon#end of sib2, iclass 35, count 2 2006.285.22:17:05.36#ibcon#*mode == 0, iclass 35, count 2 2006.285.22:17:05.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.22:17:05.36#ibcon#[27=AT05-04\r\n] 2006.285.22:17:05.36#ibcon#*before write, iclass 35, count 2 2006.285.22:17:05.36#ibcon#enter sib2, iclass 35, count 2 2006.285.22:17:05.36#ibcon#flushed, iclass 35, count 2 2006.285.22:17:05.36#ibcon#about to write, iclass 35, count 2 2006.285.22:17:05.36#ibcon#wrote, iclass 35, count 2 2006.285.22:17:05.36#ibcon#about to read 3, iclass 35, count 2 2006.285.22:17:05.39#ibcon#read 3, iclass 35, count 2 2006.285.22:17:05.39#ibcon#about to read 4, iclass 35, count 2 2006.285.22:17:05.39#ibcon#read 4, iclass 35, count 2 2006.285.22:17:05.39#ibcon#about to read 5, iclass 35, count 2 2006.285.22:17:05.39#ibcon#read 5, iclass 35, count 2 2006.285.22:17:05.39#ibcon#about to read 6, iclass 35, count 2 2006.285.22:17:05.39#ibcon#read 6, iclass 35, count 2 2006.285.22:17:05.39#ibcon#end of sib2, iclass 35, count 2 2006.285.22:17:05.39#ibcon#*after write, iclass 35, count 2 2006.285.22:17:05.39#ibcon#*before return 0, iclass 35, count 2 2006.285.22:17:05.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:17:05.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:17:05.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.22:17:05.39#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:05.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:17:05.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:17:05.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:17:05.51#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:17:05.51#ibcon#first serial, iclass 35, count 0 2006.285.22:17:05.51#ibcon#enter sib2, iclass 35, count 0 2006.285.22:17:05.51#ibcon#flushed, iclass 35, count 0 2006.285.22:17:05.51#ibcon#about to write, iclass 35, count 0 2006.285.22:17:05.51#ibcon#wrote, iclass 35, count 0 2006.285.22:17:05.51#ibcon#about to read 3, iclass 35, count 0 2006.285.22:17:05.53#ibcon#read 3, iclass 35, count 0 2006.285.22:17:05.53#ibcon#about to read 4, iclass 35, count 0 2006.285.22:17:05.53#ibcon#read 4, iclass 35, count 0 2006.285.22:17:05.53#ibcon#about to read 5, iclass 35, count 0 2006.285.22:17:05.53#ibcon#read 5, iclass 35, count 0 2006.285.22:17:05.53#ibcon#about to read 6, iclass 35, count 0 2006.285.22:17:05.53#ibcon#read 6, iclass 35, count 0 2006.285.22:17:05.53#ibcon#end of sib2, iclass 35, count 0 2006.285.22:17:05.53#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:17:05.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:17:05.53#ibcon#[27=USB\r\n] 2006.285.22:17:05.53#ibcon#*before write, iclass 35, count 0 2006.285.22:17:05.53#ibcon#enter sib2, iclass 35, count 0 2006.285.22:17:05.53#ibcon#flushed, iclass 35, count 0 2006.285.22:17:05.53#ibcon#about to write, iclass 35, count 0 2006.285.22:17:05.53#ibcon#wrote, iclass 35, count 0 2006.285.22:17:05.53#ibcon#about to read 3, iclass 35, count 0 2006.285.22:17:05.56#ibcon#read 3, iclass 35, count 0 2006.285.22:17:05.56#ibcon#about to read 4, iclass 35, count 0 2006.285.22:17:05.56#ibcon#read 4, iclass 35, count 0 2006.285.22:17:05.56#ibcon#about to read 5, iclass 35, count 0 2006.285.22:17:05.56#ibcon#read 5, iclass 35, count 0 2006.285.22:17:05.56#ibcon#about to read 6, iclass 35, count 0 2006.285.22:17:05.56#ibcon#read 6, iclass 35, count 0 2006.285.22:17:05.56#ibcon#end of sib2, iclass 35, count 0 2006.285.22:17:05.56#ibcon#*after write, iclass 35, count 0 2006.285.22:17:05.56#ibcon#*before return 0, iclass 35, count 0 2006.285.22:17:05.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:17:05.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:17:05.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:17:05.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:17:05.56$vck44/vblo=6,719.99 2006.285.22:17:05.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.22:17:05.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.22:17:05.56#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:05.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:17:05.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:17:05.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:17:05.56#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:17:05.56#ibcon#first serial, iclass 37, count 0 2006.285.22:17:05.56#ibcon#enter sib2, iclass 37, count 0 2006.285.22:17:05.56#ibcon#flushed, iclass 37, count 0 2006.285.22:17:05.56#ibcon#about to write, iclass 37, count 0 2006.285.22:17:05.56#ibcon#wrote, iclass 37, count 0 2006.285.22:17:05.56#ibcon#about to read 3, iclass 37, count 0 2006.285.22:17:05.58#ibcon#read 3, iclass 37, count 0 2006.285.22:17:05.58#ibcon#about to read 4, iclass 37, count 0 2006.285.22:17:05.58#ibcon#read 4, iclass 37, count 0 2006.285.22:17:05.58#ibcon#about to read 5, iclass 37, count 0 2006.285.22:17:05.58#ibcon#read 5, iclass 37, count 0 2006.285.22:17:05.58#ibcon#about to read 6, iclass 37, count 0 2006.285.22:17:05.58#ibcon#read 6, iclass 37, count 0 2006.285.22:17:05.58#ibcon#end of sib2, iclass 37, count 0 2006.285.22:17:05.58#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:17:05.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:17:05.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.22:17:05.58#ibcon#*before write, iclass 37, count 0 2006.285.22:17:05.58#ibcon#enter sib2, iclass 37, count 0 2006.285.22:17:05.58#ibcon#flushed, iclass 37, count 0 2006.285.22:17:05.58#ibcon#about to write, iclass 37, count 0 2006.285.22:17:05.58#ibcon#wrote, iclass 37, count 0 2006.285.22:17:05.58#ibcon#about to read 3, iclass 37, count 0 2006.285.22:17:05.62#ibcon#read 3, iclass 37, count 0 2006.285.22:17:05.62#ibcon#about to read 4, iclass 37, count 0 2006.285.22:17:05.62#ibcon#read 4, iclass 37, count 0 2006.285.22:17:05.62#ibcon#about to read 5, iclass 37, count 0 2006.285.22:17:05.62#ibcon#read 5, iclass 37, count 0 2006.285.22:17:05.62#ibcon#about to read 6, iclass 37, count 0 2006.285.22:17:05.62#ibcon#read 6, iclass 37, count 0 2006.285.22:17:05.62#ibcon#end of sib2, iclass 37, count 0 2006.285.22:17:05.62#ibcon#*after write, iclass 37, count 0 2006.285.22:17:05.62#ibcon#*before return 0, iclass 37, count 0 2006.285.22:17:05.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:17:05.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:17:05.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:17:05.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:17:05.62$vck44/vb=6,3 2006.285.22:17:05.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.22:17:05.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.22:17:05.62#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:05.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:17:05.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:17:05.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:17:05.68#ibcon#enter wrdev, iclass 39, count 2 2006.285.22:17:05.68#ibcon#first serial, iclass 39, count 2 2006.285.22:17:05.68#ibcon#enter sib2, iclass 39, count 2 2006.285.22:17:05.68#ibcon#flushed, iclass 39, count 2 2006.285.22:17:05.68#ibcon#about to write, iclass 39, count 2 2006.285.22:17:05.68#ibcon#wrote, iclass 39, count 2 2006.285.22:17:05.68#ibcon#about to read 3, iclass 39, count 2 2006.285.22:17:05.70#ibcon#read 3, iclass 39, count 2 2006.285.22:17:05.70#ibcon#about to read 4, iclass 39, count 2 2006.285.22:17:05.70#ibcon#read 4, iclass 39, count 2 2006.285.22:17:05.70#ibcon#about to read 5, iclass 39, count 2 2006.285.22:17:05.70#ibcon#read 5, iclass 39, count 2 2006.285.22:17:05.70#ibcon#about to read 6, iclass 39, count 2 2006.285.22:17:05.70#ibcon#read 6, iclass 39, count 2 2006.285.22:17:05.70#ibcon#end of sib2, iclass 39, count 2 2006.285.22:17:05.70#ibcon#*mode == 0, iclass 39, count 2 2006.285.22:17:05.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.22:17:05.70#ibcon#[27=AT06-03\r\n] 2006.285.22:17:05.70#ibcon#*before write, iclass 39, count 2 2006.285.22:17:05.70#ibcon#enter sib2, iclass 39, count 2 2006.285.22:17:05.70#ibcon#flushed, iclass 39, count 2 2006.285.22:17:05.70#ibcon#about to write, iclass 39, count 2 2006.285.22:17:05.70#ibcon#wrote, iclass 39, count 2 2006.285.22:17:05.70#ibcon#about to read 3, iclass 39, count 2 2006.285.22:17:05.73#ibcon#read 3, iclass 39, count 2 2006.285.22:17:05.73#ibcon#about to read 4, iclass 39, count 2 2006.285.22:17:05.73#ibcon#read 4, iclass 39, count 2 2006.285.22:17:05.73#ibcon#about to read 5, iclass 39, count 2 2006.285.22:17:05.73#ibcon#read 5, iclass 39, count 2 2006.285.22:17:05.73#ibcon#about to read 6, iclass 39, count 2 2006.285.22:17:05.73#ibcon#read 6, iclass 39, count 2 2006.285.22:17:05.73#ibcon#end of sib2, iclass 39, count 2 2006.285.22:17:05.73#ibcon#*after write, iclass 39, count 2 2006.285.22:17:05.73#ibcon#*before return 0, iclass 39, count 2 2006.285.22:17:05.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:17:05.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:17:05.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.22:17:05.73#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:05.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:17:05.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:17:05.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:17:05.85#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:17:05.85#ibcon#first serial, iclass 39, count 0 2006.285.22:17:05.85#ibcon#enter sib2, iclass 39, count 0 2006.285.22:17:05.85#ibcon#flushed, iclass 39, count 0 2006.285.22:17:05.85#ibcon#about to write, iclass 39, count 0 2006.285.22:17:05.85#ibcon#wrote, iclass 39, count 0 2006.285.22:17:05.85#ibcon#about to read 3, iclass 39, count 0 2006.285.22:17:05.87#ibcon#read 3, iclass 39, count 0 2006.285.22:17:05.87#ibcon#about to read 4, iclass 39, count 0 2006.285.22:17:05.87#ibcon#read 4, iclass 39, count 0 2006.285.22:17:05.87#ibcon#about to read 5, iclass 39, count 0 2006.285.22:17:05.87#ibcon#read 5, iclass 39, count 0 2006.285.22:17:05.87#ibcon#about to read 6, iclass 39, count 0 2006.285.22:17:05.87#ibcon#read 6, iclass 39, count 0 2006.285.22:17:05.87#ibcon#end of sib2, iclass 39, count 0 2006.285.22:17:05.87#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:17:05.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:17:05.87#ibcon#[27=USB\r\n] 2006.285.22:17:05.87#ibcon#*before write, iclass 39, count 0 2006.285.22:17:05.87#ibcon#enter sib2, iclass 39, count 0 2006.285.22:17:05.87#ibcon#flushed, iclass 39, count 0 2006.285.22:17:05.87#ibcon#about to write, iclass 39, count 0 2006.285.22:17:05.87#ibcon#wrote, iclass 39, count 0 2006.285.22:17:05.87#ibcon#about to read 3, iclass 39, count 0 2006.285.22:17:05.90#ibcon#read 3, iclass 39, count 0 2006.285.22:17:05.90#ibcon#about to read 4, iclass 39, count 0 2006.285.22:17:05.90#ibcon#read 4, iclass 39, count 0 2006.285.22:17:05.90#ibcon#about to read 5, iclass 39, count 0 2006.285.22:17:05.90#ibcon#read 5, iclass 39, count 0 2006.285.22:17:05.90#ibcon#about to read 6, iclass 39, count 0 2006.285.22:17:05.90#ibcon#read 6, iclass 39, count 0 2006.285.22:17:05.90#ibcon#end of sib2, iclass 39, count 0 2006.285.22:17:05.90#ibcon#*after write, iclass 39, count 0 2006.285.22:17:05.90#ibcon#*before return 0, iclass 39, count 0 2006.285.22:17:05.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:17:05.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:17:05.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:17:05.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:17:05.90$vck44/vblo=7,734.99 2006.285.22:17:05.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.22:17:05.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.22:17:05.90#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:05.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:17:05.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:17:05.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:17:05.90#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:17:05.90#ibcon#first serial, iclass 3, count 0 2006.285.22:17:05.90#ibcon#enter sib2, iclass 3, count 0 2006.285.22:17:05.90#ibcon#flushed, iclass 3, count 0 2006.285.22:17:05.90#ibcon#about to write, iclass 3, count 0 2006.285.22:17:05.90#ibcon#wrote, iclass 3, count 0 2006.285.22:17:05.90#ibcon#about to read 3, iclass 3, count 0 2006.285.22:17:05.92#ibcon#read 3, iclass 3, count 0 2006.285.22:17:05.92#ibcon#about to read 4, iclass 3, count 0 2006.285.22:17:05.92#ibcon#read 4, iclass 3, count 0 2006.285.22:17:05.92#ibcon#about to read 5, iclass 3, count 0 2006.285.22:17:05.92#ibcon#read 5, iclass 3, count 0 2006.285.22:17:05.92#ibcon#about to read 6, iclass 3, count 0 2006.285.22:17:05.92#ibcon#read 6, iclass 3, count 0 2006.285.22:17:05.92#ibcon#end of sib2, iclass 3, count 0 2006.285.22:17:05.92#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:17:05.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:17:05.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.22:17:05.92#ibcon#*before write, iclass 3, count 0 2006.285.22:17:05.92#ibcon#enter sib2, iclass 3, count 0 2006.285.22:17:05.92#ibcon#flushed, iclass 3, count 0 2006.285.22:17:05.92#ibcon#about to write, iclass 3, count 0 2006.285.22:17:05.92#ibcon#wrote, iclass 3, count 0 2006.285.22:17:05.92#ibcon#about to read 3, iclass 3, count 0 2006.285.22:17:05.96#ibcon#read 3, iclass 3, count 0 2006.285.22:17:05.96#ibcon#about to read 4, iclass 3, count 0 2006.285.22:17:05.96#ibcon#read 4, iclass 3, count 0 2006.285.22:17:05.96#ibcon#about to read 5, iclass 3, count 0 2006.285.22:17:05.96#ibcon#read 5, iclass 3, count 0 2006.285.22:17:05.96#ibcon#about to read 6, iclass 3, count 0 2006.285.22:17:05.96#ibcon#read 6, iclass 3, count 0 2006.285.22:17:05.96#ibcon#end of sib2, iclass 3, count 0 2006.285.22:17:05.96#ibcon#*after write, iclass 3, count 0 2006.285.22:17:05.96#ibcon#*before return 0, iclass 3, count 0 2006.285.22:17:05.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:17:05.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:17:05.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:17:05.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:17:05.96$vck44/vb=7,4 2006.285.22:17:05.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.22:17:05.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.22:17:05.96#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:05.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:17:06.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:17:06.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:17:06.02#ibcon#enter wrdev, iclass 5, count 2 2006.285.22:17:06.02#ibcon#first serial, iclass 5, count 2 2006.285.22:17:06.02#ibcon#enter sib2, iclass 5, count 2 2006.285.22:17:06.02#ibcon#flushed, iclass 5, count 2 2006.285.22:17:06.02#ibcon#about to write, iclass 5, count 2 2006.285.22:17:06.02#ibcon#wrote, iclass 5, count 2 2006.285.22:17:06.02#ibcon#about to read 3, iclass 5, count 2 2006.285.22:17:06.04#ibcon#read 3, iclass 5, count 2 2006.285.22:17:06.04#ibcon#about to read 4, iclass 5, count 2 2006.285.22:17:06.04#ibcon#read 4, iclass 5, count 2 2006.285.22:17:06.04#ibcon#about to read 5, iclass 5, count 2 2006.285.22:17:06.04#ibcon#read 5, iclass 5, count 2 2006.285.22:17:06.04#ibcon#about to read 6, iclass 5, count 2 2006.285.22:17:06.04#ibcon#read 6, iclass 5, count 2 2006.285.22:17:06.04#ibcon#end of sib2, iclass 5, count 2 2006.285.22:17:06.04#ibcon#*mode == 0, iclass 5, count 2 2006.285.22:17:06.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.22:17:06.04#ibcon#[27=AT07-04\r\n] 2006.285.22:17:06.04#ibcon#*before write, iclass 5, count 2 2006.285.22:17:06.04#ibcon#enter sib2, iclass 5, count 2 2006.285.22:17:06.04#ibcon#flushed, iclass 5, count 2 2006.285.22:17:06.04#ibcon#about to write, iclass 5, count 2 2006.285.22:17:06.04#ibcon#wrote, iclass 5, count 2 2006.285.22:17:06.04#ibcon#about to read 3, iclass 5, count 2 2006.285.22:17:06.07#ibcon#read 3, iclass 5, count 2 2006.285.22:17:06.07#ibcon#about to read 4, iclass 5, count 2 2006.285.22:17:06.07#ibcon#read 4, iclass 5, count 2 2006.285.22:17:06.07#ibcon#about to read 5, iclass 5, count 2 2006.285.22:17:06.07#ibcon#read 5, iclass 5, count 2 2006.285.22:17:06.07#ibcon#about to read 6, iclass 5, count 2 2006.285.22:17:06.07#ibcon#read 6, iclass 5, count 2 2006.285.22:17:06.07#ibcon#end of sib2, iclass 5, count 2 2006.285.22:17:06.07#ibcon#*after write, iclass 5, count 2 2006.285.22:17:06.07#ibcon#*before return 0, iclass 5, count 2 2006.285.22:17:06.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:17:06.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:17:06.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.22:17:06.07#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:06.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:17:06.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:17:06.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:17:06.19#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:17:06.19#ibcon#first serial, iclass 5, count 0 2006.285.22:17:06.19#ibcon#enter sib2, iclass 5, count 0 2006.285.22:17:06.19#ibcon#flushed, iclass 5, count 0 2006.285.22:17:06.19#ibcon#about to write, iclass 5, count 0 2006.285.22:17:06.19#ibcon#wrote, iclass 5, count 0 2006.285.22:17:06.19#ibcon#about to read 3, iclass 5, count 0 2006.285.22:17:06.21#ibcon#read 3, iclass 5, count 0 2006.285.22:17:06.21#ibcon#about to read 4, iclass 5, count 0 2006.285.22:17:06.21#ibcon#read 4, iclass 5, count 0 2006.285.22:17:06.21#ibcon#about to read 5, iclass 5, count 0 2006.285.22:17:06.21#ibcon#read 5, iclass 5, count 0 2006.285.22:17:06.21#ibcon#about to read 6, iclass 5, count 0 2006.285.22:17:06.21#ibcon#read 6, iclass 5, count 0 2006.285.22:17:06.21#ibcon#end of sib2, iclass 5, count 0 2006.285.22:17:06.21#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:17:06.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:17:06.21#ibcon#[27=USB\r\n] 2006.285.22:17:06.21#ibcon#*before write, iclass 5, count 0 2006.285.22:17:06.21#ibcon#enter sib2, iclass 5, count 0 2006.285.22:17:06.21#ibcon#flushed, iclass 5, count 0 2006.285.22:17:06.21#ibcon#about to write, iclass 5, count 0 2006.285.22:17:06.21#ibcon#wrote, iclass 5, count 0 2006.285.22:17:06.21#ibcon#about to read 3, iclass 5, count 0 2006.285.22:17:06.24#ibcon#read 3, iclass 5, count 0 2006.285.22:17:06.24#ibcon#about to read 4, iclass 5, count 0 2006.285.22:17:06.24#ibcon#read 4, iclass 5, count 0 2006.285.22:17:06.24#ibcon#about to read 5, iclass 5, count 0 2006.285.22:17:06.24#ibcon#read 5, iclass 5, count 0 2006.285.22:17:06.24#ibcon#about to read 6, iclass 5, count 0 2006.285.22:17:06.24#ibcon#read 6, iclass 5, count 0 2006.285.22:17:06.24#ibcon#end of sib2, iclass 5, count 0 2006.285.22:17:06.24#ibcon#*after write, iclass 5, count 0 2006.285.22:17:06.24#ibcon#*before return 0, iclass 5, count 0 2006.285.22:17:06.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:17:06.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:17:06.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:17:06.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:17:06.24$vck44/vblo=8,744.99 2006.285.22:17:06.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.22:17:06.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.22:17:06.24#ibcon#ireg 17 cls_cnt 0 2006.285.22:17:06.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:17:06.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:17:06.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:17:06.24#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:17:06.24#ibcon#first serial, iclass 7, count 0 2006.285.22:17:06.24#ibcon#enter sib2, iclass 7, count 0 2006.285.22:17:06.24#ibcon#flushed, iclass 7, count 0 2006.285.22:17:06.24#ibcon#about to write, iclass 7, count 0 2006.285.22:17:06.24#ibcon#wrote, iclass 7, count 0 2006.285.22:17:06.24#ibcon#about to read 3, iclass 7, count 0 2006.285.22:17:06.26#ibcon#read 3, iclass 7, count 0 2006.285.22:17:06.26#ibcon#about to read 4, iclass 7, count 0 2006.285.22:17:06.26#ibcon#read 4, iclass 7, count 0 2006.285.22:17:06.26#ibcon#about to read 5, iclass 7, count 0 2006.285.22:17:06.26#ibcon#read 5, iclass 7, count 0 2006.285.22:17:06.26#ibcon#about to read 6, iclass 7, count 0 2006.285.22:17:06.26#ibcon#read 6, iclass 7, count 0 2006.285.22:17:06.26#ibcon#end of sib2, iclass 7, count 0 2006.285.22:17:06.26#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:17:06.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:17:06.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.22:17:06.26#ibcon#*before write, iclass 7, count 0 2006.285.22:17:06.26#ibcon#enter sib2, iclass 7, count 0 2006.285.22:17:06.26#ibcon#flushed, iclass 7, count 0 2006.285.22:17:06.26#ibcon#about to write, iclass 7, count 0 2006.285.22:17:06.26#ibcon#wrote, iclass 7, count 0 2006.285.22:17:06.26#ibcon#about to read 3, iclass 7, count 0 2006.285.22:17:06.30#ibcon#read 3, iclass 7, count 0 2006.285.22:17:06.30#ibcon#about to read 4, iclass 7, count 0 2006.285.22:17:06.30#ibcon#read 4, iclass 7, count 0 2006.285.22:17:06.30#ibcon#about to read 5, iclass 7, count 0 2006.285.22:17:06.30#ibcon#read 5, iclass 7, count 0 2006.285.22:17:06.30#ibcon#about to read 6, iclass 7, count 0 2006.285.22:17:06.30#ibcon#read 6, iclass 7, count 0 2006.285.22:17:06.30#ibcon#end of sib2, iclass 7, count 0 2006.285.22:17:06.30#ibcon#*after write, iclass 7, count 0 2006.285.22:17:06.30#ibcon#*before return 0, iclass 7, count 0 2006.285.22:17:06.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:17:06.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:17:06.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:17:06.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:17:06.30$vck44/vb=8,4 2006.285.22:17:06.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.22:17:06.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.22:17:06.30#ibcon#ireg 11 cls_cnt 2 2006.285.22:17:06.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:17:06.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:17:06.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:17:06.36#ibcon#enter wrdev, iclass 11, count 2 2006.285.22:17:06.36#ibcon#first serial, iclass 11, count 2 2006.285.22:17:06.36#ibcon#enter sib2, iclass 11, count 2 2006.285.22:17:06.36#ibcon#flushed, iclass 11, count 2 2006.285.22:17:06.36#ibcon#about to write, iclass 11, count 2 2006.285.22:17:06.36#ibcon#wrote, iclass 11, count 2 2006.285.22:17:06.36#ibcon#about to read 3, iclass 11, count 2 2006.285.22:17:06.38#ibcon#read 3, iclass 11, count 2 2006.285.22:17:06.38#ibcon#about to read 4, iclass 11, count 2 2006.285.22:17:06.38#ibcon#read 4, iclass 11, count 2 2006.285.22:17:06.38#ibcon#about to read 5, iclass 11, count 2 2006.285.22:17:06.38#ibcon#read 5, iclass 11, count 2 2006.285.22:17:06.38#ibcon#about to read 6, iclass 11, count 2 2006.285.22:17:06.38#ibcon#read 6, iclass 11, count 2 2006.285.22:17:06.38#ibcon#end of sib2, iclass 11, count 2 2006.285.22:17:06.38#ibcon#*mode == 0, iclass 11, count 2 2006.285.22:17:06.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.22:17:06.38#ibcon#[27=AT08-04\r\n] 2006.285.22:17:06.38#ibcon#*before write, iclass 11, count 2 2006.285.22:17:06.38#ibcon#enter sib2, iclass 11, count 2 2006.285.22:17:06.38#ibcon#flushed, iclass 11, count 2 2006.285.22:17:06.38#ibcon#about to write, iclass 11, count 2 2006.285.22:17:06.38#ibcon#wrote, iclass 11, count 2 2006.285.22:17:06.38#ibcon#about to read 3, iclass 11, count 2 2006.285.22:17:06.41#ibcon#read 3, iclass 11, count 2 2006.285.22:17:06.41#ibcon#about to read 4, iclass 11, count 2 2006.285.22:17:06.41#ibcon#read 4, iclass 11, count 2 2006.285.22:17:06.41#ibcon#about to read 5, iclass 11, count 2 2006.285.22:17:06.41#ibcon#read 5, iclass 11, count 2 2006.285.22:17:06.41#ibcon#about to read 6, iclass 11, count 2 2006.285.22:17:06.41#ibcon#read 6, iclass 11, count 2 2006.285.22:17:06.41#ibcon#end of sib2, iclass 11, count 2 2006.285.22:17:06.41#ibcon#*after write, iclass 11, count 2 2006.285.22:17:06.41#ibcon#*before return 0, iclass 11, count 2 2006.285.22:17:06.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:17:06.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:17:06.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.22:17:06.41#ibcon#ireg 7 cls_cnt 0 2006.285.22:17:06.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:17:06.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:17:06.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:17:06.53#ibcon#enter wrdev, iclass 11, count 0 2006.285.22:17:06.53#ibcon#first serial, iclass 11, count 0 2006.285.22:17:06.53#ibcon#enter sib2, iclass 11, count 0 2006.285.22:17:06.53#ibcon#flushed, iclass 11, count 0 2006.285.22:17:06.53#ibcon#about to write, iclass 11, count 0 2006.285.22:17:06.53#ibcon#wrote, iclass 11, count 0 2006.285.22:17:06.53#ibcon#about to read 3, iclass 11, count 0 2006.285.22:17:06.55#ibcon#read 3, iclass 11, count 0 2006.285.22:17:06.55#ibcon#about to read 4, iclass 11, count 0 2006.285.22:17:06.55#ibcon#read 4, iclass 11, count 0 2006.285.22:17:06.55#ibcon#about to read 5, iclass 11, count 0 2006.285.22:17:06.55#ibcon#read 5, iclass 11, count 0 2006.285.22:17:06.55#ibcon#about to read 6, iclass 11, count 0 2006.285.22:17:06.55#ibcon#read 6, iclass 11, count 0 2006.285.22:17:06.55#ibcon#end of sib2, iclass 11, count 0 2006.285.22:17:06.55#ibcon#*mode == 0, iclass 11, count 0 2006.285.22:17:06.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.22:17:06.55#ibcon#[27=USB\r\n] 2006.285.22:17:06.55#ibcon#*before write, iclass 11, count 0 2006.285.22:17:06.55#ibcon#enter sib2, iclass 11, count 0 2006.285.22:17:06.55#ibcon#flushed, iclass 11, count 0 2006.285.22:17:06.55#ibcon#about to write, iclass 11, count 0 2006.285.22:17:06.55#ibcon#wrote, iclass 11, count 0 2006.285.22:17:06.55#ibcon#about to read 3, iclass 11, count 0 2006.285.22:17:06.58#ibcon#read 3, iclass 11, count 0 2006.285.22:17:06.58#ibcon#about to read 4, iclass 11, count 0 2006.285.22:17:06.58#ibcon#read 4, iclass 11, count 0 2006.285.22:17:06.58#ibcon#about to read 5, iclass 11, count 0 2006.285.22:17:06.58#ibcon#read 5, iclass 11, count 0 2006.285.22:17:06.58#ibcon#about to read 6, iclass 11, count 0 2006.285.22:17:06.58#ibcon#read 6, iclass 11, count 0 2006.285.22:17:06.58#ibcon#end of sib2, iclass 11, count 0 2006.285.22:17:06.58#ibcon#*after write, iclass 11, count 0 2006.285.22:17:06.58#ibcon#*before return 0, iclass 11, count 0 2006.285.22:17:06.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:17:06.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:17:06.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.22:17:06.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.22:17:06.58$vck44/vabw=wide 2006.285.22:17:06.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.22:17:06.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.22:17:06.58#ibcon#ireg 8 cls_cnt 0 2006.285.22:17:06.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:17:06.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:17:06.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:17:06.58#ibcon#enter wrdev, iclass 13, count 0 2006.285.22:17:06.58#ibcon#first serial, iclass 13, count 0 2006.285.22:17:06.58#ibcon#enter sib2, iclass 13, count 0 2006.285.22:17:06.58#ibcon#flushed, iclass 13, count 0 2006.285.22:17:06.58#ibcon#about to write, iclass 13, count 0 2006.285.22:17:06.58#ibcon#wrote, iclass 13, count 0 2006.285.22:17:06.58#ibcon#about to read 3, iclass 13, count 0 2006.285.22:17:06.60#ibcon#read 3, iclass 13, count 0 2006.285.22:17:06.60#ibcon#about to read 4, iclass 13, count 0 2006.285.22:17:06.60#ibcon#read 4, iclass 13, count 0 2006.285.22:17:06.60#ibcon#about to read 5, iclass 13, count 0 2006.285.22:17:06.60#ibcon#read 5, iclass 13, count 0 2006.285.22:17:06.60#ibcon#about to read 6, iclass 13, count 0 2006.285.22:17:06.60#ibcon#read 6, iclass 13, count 0 2006.285.22:17:06.60#ibcon#end of sib2, iclass 13, count 0 2006.285.22:17:06.60#ibcon#*mode == 0, iclass 13, count 0 2006.285.22:17:06.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.22:17:06.60#ibcon#[25=BW32\r\n] 2006.285.22:17:06.60#ibcon#*before write, iclass 13, count 0 2006.285.22:17:06.60#ibcon#enter sib2, iclass 13, count 0 2006.285.22:17:06.60#ibcon#flushed, iclass 13, count 0 2006.285.22:17:06.60#ibcon#about to write, iclass 13, count 0 2006.285.22:17:06.60#ibcon#wrote, iclass 13, count 0 2006.285.22:17:06.60#ibcon#about to read 3, iclass 13, count 0 2006.285.22:17:06.63#ibcon#read 3, iclass 13, count 0 2006.285.22:17:06.63#ibcon#about to read 4, iclass 13, count 0 2006.285.22:17:06.63#ibcon#read 4, iclass 13, count 0 2006.285.22:17:06.63#ibcon#about to read 5, iclass 13, count 0 2006.285.22:17:06.63#ibcon#read 5, iclass 13, count 0 2006.285.22:17:06.63#ibcon#about to read 6, iclass 13, count 0 2006.285.22:17:06.63#ibcon#read 6, iclass 13, count 0 2006.285.22:17:06.63#ibcon#end of sib2, iclass 13, count 0 2006.285.22:17:06.63#ibcon#*after write, iclass 13, count 0 2006.285.22:17:06.63#ibcon#*before return 0, iclass 13, count 0 2006.285.22:17:06.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:17:06.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:17:06.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.22:17:06.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.22:17:06.63$vck44/vbbw=wide 2006.285.22:17:06.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.22:17:06.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.22:17:06.63#ibcon#ireg 8 cls_cnt 0 2006.285.22:17:06.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:17:06.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:17:06.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:17:06.70#ibcon#enter wrdev, iclass 15, count 0 2006.285.22:17:06.70#ibcon#first serial, iclass 15, count 0 2006.285.22:17:06.70#ibcon#enter sib2, iclass 15, count 0 2006.285.22:17:06.70#ibcon#flushed, iclass 15, count 0 2006.285.22:17:06.70#ibcon#about to write, iclass 15, count 0 2006.285.22:17:06.70#ibcon#wrote, iclass 15, count 0 2006.285.22:17:06.70#ibcon#about to read 3, iclass 15, count 0 2006.285.22:17:06.72#ibcon#read 3, iclass 15, count 0 2006.285.22:17:06.72#ibcon#about to read 4, iclass 15, count 0 2006.285.22:17:06.72#ibcon#read 4, iclass 15, count 0 2006.285.22:17:06.72#ibcon#about to read 5, iclass 15, count 0 2006.285.22:17:06.72#ibcon#read 5, iclass 15, count 0 2006.285.22:17:06.72#ibcon#about to read 6, iclass 15, count 0 2006.285.22:17:06.72#ibcon#read 6, iclass 15, count 0 2006.285.22:17:06.72#ibcon#end of sib2, iclass 15, count 0 2006.285.22:17:06.72#ibcon#*mode == 0, iclass 15, count 0 2006.285.22:17:06.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.22:17:06.72#ibcon#[27=BW32\r\n] 2006.285.22:17:06.72#ibcon#*before write, iclass 15, count 0 2006.285.22:17:06.72#ibcon#enter sib2, iclass 15, count 0 2006.285.22:17:06.72#ibcon#flushed, iclass 15, count 0 2006.285.22:17:06.72#ibcon#about to write, iclass 15, count 0 2006.285.22:17:06.72#ibcon#wrote, iclass 15, count 0 2006.285.22:17:06.72#ibcon#about to read 3, iclass 15, count 0 2006.285.22:17:06.75#ibcon#read 3, iclass 15, count 0 2006.285.22:17:06.75#ibcon#about to read 4, iclass 15, count 0 2006.285.22:17:06.75#ibcon#read 4, iclass 15, count 0 2006.285.22:17:06.75#ibcon#about to read 5, iclass 15, count 0 2006.285.22:17:06.75#ibcon#read 5, iclass 15, count 0 2006.285.22:17:06.75#ibcon#about to read 6, iclass 15, count 0 2006.285.22:17:06.75#ibcon#read 6, iclass 15, count 0 2006.285.22:17:06.75#ibcon#end of sib2, iclass 15, count 0 2006.285.22:17:06.75#ibcon#*after write, iclass 15, count 0 2006.285.22:17:06.75#ibcon#*before return 0, iclass 15, count 0 2006.285.22:17:06.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:17:06.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:17:06.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.22:17:06.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.22:17:06.75$setupk4/ifdk4 2006.285.22:17:06.75$ifdk4/lo= 2006.285.22:17:06.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.22:17:06.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.22:17:06.75$ifdk4/patch= 2006.285.22:17:06.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.22:17:06.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.22:17:06.75$setupk4/!*+20s 2006.285.22:17:11.41#abcon#<5=/14 0.3 0.8 16.331001016.0\r\n> 2006.285.22:17:11.43#abcon#{5=INTERFACE CLEAR} 2006.285.22:17:11.49#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:17:19.13#trakl#Source acquired 2006.285.22:17:20.13#flagr#flagr/antenna,acquired 2006.285.22:17:21.26$setupk4/"tpicd 2006.285.22:17:21.26$setupk4/echo=off 2006.285.22:17:21.26$setupk4/xlog=off 2006.285.22:17:21.26:!2006.285.22:18:36 2006.285.22:18:36.00:preob 2006.285.22:18:36.14/onsource/TRACKING 2006.285.22:18:36.14:!2006.285.22:18:46 2006.285.22:18:46.00:"tape 2006.285.22:18:46.00:"st=record 2006.285.22:18:46.00:data_valid=on 2006.285.22:18:46.00:midob 2006.285.22:18:47.14/onsource/TRACKING 2006.285.22:18:47.14/wx/16.36,1016.0,100 2006.285.22:18:47.20/cable/+6.5116E-03 2006.285.22:18:48.29/va/01,07,usb,yes,33,36 2006.285.22:18:48.29/va/02,06,usb,yes,33,34 2006.285.22:18:48.29/va/03,07,usb,yes,33,35 2006.285.22:18:48.29/va/04,06,usb,yes,34,36 2006.285.22:18:48.29/va/05,03,usb,yes,34,34 2006.285.22:18:48.29/va/06,04,usb,yes,30,30 2006.285.22:18:48.29/va/07,04,usb,yes,31,32 2006.285.22:18:48.29/va/08,03,usb,yes,32,39 2006.285.22:18:48.52/valo/01,524.99,yes,locked 2006.285.22:18:48.52/valo/02,534.99,yes,locked 2006.285.22:18:48.52/valo/03,564.99,yes,locked 2006.285.22:18:48.52/valo/04,624.99,yes,locked 2006.285.22:18:48.52/valo/05,734.99,yes,locked 2006.285.22:18:48.52/valo/06,814.99,yes,locked 2006.285.22:18:48.52/valo/07,864.99,yes,locked 2006.285.22:18:48.52/valo/08,884.99,yes,locked 2006.285.22:18:49.61/vb/01,04,usb,yes,30,28 2006.285.22:18:49.61/vb/02,05,usb,yes,29,29 2006.285.22:18:49.61/vb/03,04,usb,yes,30,33 2006.285.22:18:49.61/vb/04,05,usb,yes,30,29 2006.285.22:18:49.61/vb/05,04,usb,yes,26,29 2006.285.22:18:49.61/vb/06,03,usb,yes,38,34 2006.285.22:18:49.61/vb/07,04,usb,yes,31,31 2006.285.22:18:49.61/vb/08,04,usb,yes,28,31 2006.285.22:18:49.85/vblo/01,629.99,yes,locked 2006.285.22:18:49.85/vblo/02,634.99,yes,locked 2006.285.22:18:49.85/vblo/03,649.99,yes,locked 2006.285.22:18:49.85/vblo/04,679.99,yes,locked 2006.285.22:18:49.85/vblo/05,709.99,yes,locked 2006.285.22:18:49.85/vblo/06,719.99,yes,locked 2006.285.22:18:49.85/vblo/07,734.99,yes,locked 2006.285.22:18:49.85/vblo/08,744.99,yes,locked 2006.285.22:18:50.00/vabw/8 2006.285.22:18:50.15/vbbw/8 2006.285.22:18:50.24/xfe/off,on,11.7 2006.285.22:18:50.61/ifatt/23,28,28,28 2006.285.22:18:51.08/fmout-gps/S +2.65E-07 2006.285.22:18:51.10:!2006.285.22:19:46 2006.285.22:19:46.00:data_valid=off 2006.285.22:19:46.00:"et 2006.285.22:19:46.00:!+3s 2006.285.22:19:49.01:"tape 2006.285.22:19:49.01:postob 2006.285.22:19:49.19/cable/+6.5107E-03 2006.285.22:19:49.19/wx/16.37,1016.0,100 2006.285.22:19:50.07/fmout-gps/S +2.64E-07 2006.285.22:19:50.07:scan_name=285-2222,jd0610,140 2006.285.22:19:50.07:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.285.22:19:50.14#flagr#flagr/antenna,new-source 2006.285.22:19:51.14:checkk5 2006.285.22:19:51.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:19:51.92/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:19:52.31/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:19:52.68/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:19:53.10/chk_obsdata//k5ts1/T2852218??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:19:53.47/chk_obsdata//k5ts2/T2852218??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:19:54.11/chk_obsdata//k5ts3/T2852218??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:19:54.52/chk_obsdata//k5ts4/T2852218??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:19:55.54/k5log//k5ts1_log_newline 2006.285.22:19:56.35/k5log//k5ts2_log_newline 2006.285.22:19:57.28/k5log//k5ts3_log_newline 2006.285.22:19:58.00/k5log//k5ts4_log_newline 2006.285.22:19:58.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:19:58.02:setupk4=1 2006.285.22:19:58.02$setupk4/echo=on 2006.285.22:19:58.02$setupk4/pcalon 2006.285.22:19:58.02$pcalon/"no phase cal control is implemented here 2006.285.22:19:58.02$setupk4/"tpicd=stop 2006.285.22:19:58.02$setupk4/"rec=synch_on 2006.285.22:19:58.02$setupk4/"rec_mode=128 2006.285.22:19:58.02$setupk4/!* 2006.285.22:19:58.02$setupk4/recpk4 2006.285.22:19:58.02$recpk4/recpatch= 2006.285.22:19:58.02$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:19:58.02$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:19:58.02$setupk4/vck44 2006.285.22:19:58.03$vck44/valo=1,524.99 2006.285.22:19:58.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.22:19:58.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.22:19:58.03#ibcon#ireg 17 cls_cnt 0 2006.285.22:19:58.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:19:58.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:19:58.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:19:58.03#ibcon#enter wrdev, iclass 16, count 0 2006.285.22:19:58.03#ibcon#first serial, iclass 16, count 0 2006.285.22:19:58.03#ibcon#enter sib2, iclass 16, count 0 2006.285.22:19:58.03#ibcon#flushed, iclass 16, count 0 2006.285.22:19:58.03#ibcon#about to write, iclass 16, count 0 2006.285.22:19:58.03#ibcon#wrote, iclass 16, count 0 2006.285.22:19:58.03#ibcon#about to read 3, iclass 16, count 0 2006.285.22:19:58.05#ibcon#read 3, iclass 16, count 0 2006.285.22:19:58.05#ibcon#about to read 4, iclass 16, count 0 2006.285.22:19:58.05#ibcon#read 4, iclass 16, count 0 2006.285.22:19:58.05#ibcon#about to read 5, iclass 16, count 0 2006.285.22:19:58.05#ibcon#read 5, iclass 16, count 0 2006.285.22:19:58.05#ibcon#about to read 6, iclass 16, count 0 2006.285.22:19:58.05#ibcon#read 6, iclass 16, count 0 2006.285.22:19:58.05#ibcon#end of sib2, iclass 16, count 0 2006.285.22:19:58.05#ibcon#*mode == 0, iclass 16, count 0 2006.285.22:19:58.05#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.22:19:58.05#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:19:58.05#ibcon#*before write, iclass 16, count 0 2006.285.22:19:58.05#ibcon#enter sib2, iclass 16, count 0 2006.285.22:19:58.05#ibcon#flushed, iclass 16, count 0 2006.285.22:19:58.05#ibcon#about to write, iclass 16, count 0 2006.285.22:19:58.05#ibcon#wrote, iclass 16, count 0 2006.285.22:19:58.05#ibcon#about to read 3, iclass 16, count 0 2006.285.22:19:58.10#ibcon#read 3, iclass 16, count 0 2006.285.22:19:58.10#ibcon#about to read 4, iclass 16, count 0 2006.285.22:19:58.10#ibcon#read 4, iclass 16, count 0 2006.285.22:19:58.10#ibcon#about to read 5, iclass 16, count 0 2006.285.22:19:58.10#ibcon#read 5, iclass 16, count 0 2006.285.22:19:58.10#ibcon#about to read 6, iclass 16, count 0 2006.285.22:19:58.10#ibcon#read 6, iclass 16, count 0 2006.285.22:19:58.10#ibcon#end of sib2, iclass 16, count 0 2006.285.22:19:58.10#ibcon#*after write, iclass 16, count 0 2006.285.22:19:58.10#ibcon#*before return 0, iclass 16, count 0 2006.285.22:19:58.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:19:58.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:19:58.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.22:19:58.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.22:19:58.10$vck44/va=1,7 2006.285.22:19:58.10#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.22:19:58.10#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.22:19:58.10#ibcon#ireg 11 cls_cnt 2 2006.285.22:19:58.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:19:58.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:19:58.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:19:58.10#ibcon#enter wrdev, iclass 18, count 2 2006.285.22:19:58.10#ibcon#first serial, iclass 18, count 2 2006.285.22:19:58.10#ibcon#enter sib2, iclass 18, count 2 2006.285.22:19:58.10#ibcon#flushed, iclass 18, count 2 2006.285.22:19:58.10#ibcon#about to write, iclass 18, count 2 2006.285.22:19:58.10#ibcon#wrote, iclass 18, count 2 2006.285.22:19:58.10#ibcon#about to read 3, iclass 18, count 2 2006.285.22:19:58.12#ibcon#read 3, iclass 18, count 2 2006.285.22:19:58.12#ibcon#about to read 4, iclass 18, count 2 2006.285.22:19:58.12#ibcon#read 4, iclass 18, count 2 2006.285.22:19:58.12#ibcon#about to read 5, iclass 18, count 2 2006.285.22:19:58.12#ibcon#read 5, iclass 18, count 2 2006.285.22:19:58.12#ibcon#about to read 6, iclass 18, count 2 2006.285.22:19:58.12#ibcon#read 6, iclass 18, count 2 2006.285.22:19:58.12#ibcon#end of sib2, iclass 18, count 2 2006.285.22:19:58.12#ibcon#*mode == 0, iclass 18, count 2 2006.285.22:19:58.12#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.22:19:58.12#ibcon#[25=AT01-07\r\n] 2006.285.22:19:58.12#ibcon#*before write, iclass 18, count 2 2006.285.22:19:58.12#ibcon#enter sib2, iclass 18, count 2 2006.285.22:19:58.12#ibcon#flushed, iclass 18, count 2 2006.285.22:19:58.12#ibcon#about to write, iclass 18, count 2 2006.285.22:19:58.12#ibcon#wrote, iclass 18, count 2 2006.285.22:19:58.12#ibcon#about to read 3, iclass 18, count 2 2006.285.22:19:58.15#ibcon#read 3, iclass 18, count 2 2006.285.22:19:58.15#ibcon#about to read 4, iclass 18, count 2 2006.285.22:19:58.15#ibcon#read 4, iclass 18, count 2 2006.285.22:19:58.15#ibcon#about to read 5, iclass 18, count 2 2006.285.22:19:58.15#ibcon#read 5, iclass 18, count 2 2006.285.22:19:58.15#ibcon#about to read 6, iclass 18, count 2 2006.285.22:19:58.15#ibcon#read 6, iclass 18, count 2 2006.285.22:19:58.15#ibcon#end of sib2, iclass 18, count 2 2006.285.22:19:58.15#ibcon#*after write, iclass 18, count 2 2006.285.22:19:58.15#ibcon#*before return 0, iclass 18, count 2 2006.285.22:19:58.15#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:19:58.15#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:19:58.15#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.22:19:58.15#ibcon#ireg 7 cls_cnt 0 2006.285.22:19:58.15#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:19:58.27#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:19:58.27#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:19:58.27#ibcon#enter wrdev, iclass 18, count 0 2006.285.22:19:58.27#ibcon#first serial, iclass 18, count 0 2006.285.22:19:58.27#ibcon#enter sib2, iclass 18, count 0 2006.285.22:19:58.27#ibcon#flushed, iclass 18, count 0 2006.285.22:19:58.27#ibcon#about to write, iclass 18, count 0 2006.285.22:19:58.27#ibcon#wrote, iclass 18, count 0 2006.285.22:19:58.27#ibcon#about to read 3, iclass 18, count 0 2006.285.22:19:58.29#ibcon#read 3, iclass 18, count 0 2006.285.22:19:58.29#ibcon#about to read 4, iclass 18, count 0 2006.285.22:19:58.29#ibcon#read 4, iclass 18, count 0 2006.285.22:19:58.29#ibcon#about to read 5, iclass 18, count 0 2006.285.22:19:58.29#ibcon#read 5, iclass 18, count 0 2006.285.22:19:58.29#ibcon#about to read 6, iclass 18, count 0 2006.285.22:19:58.29#ibcon#read 6, iclass 18, count 0 2006.285.22:19:58.29#ibcon#end of sib2, iclass 18, count 0 2006.285.22:19:58.29#ibcon#*mode == 0, iclass 18, count 0 2006.285.22:19:58.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.22:19:58.29#ibcon#[25=USB\r\n] 2006.285.22:19:58.29#ibcon#*before write, iclass 18, count 0 2006.285.22:19:58.29#ibcon#enter sib2, iclass 18, count 0 2006.285.22:19:58.29#ibcon#flushed, iclass 18, count 0 2006.285.22:19:58.29#ibcon#about to write, iclass 18, count 0 2006.285.22:19:58.29#ibcon#wrote, iclass 18, count 0 2006.285.22:19:58.29#ibcon#about to read 3, iclass 18, count 0 2006.285.22:19:58.32#ibcon#read 3, iclass 18, count 0 2006.285.22:19:58.32#ibcon#about to read 4, iclass 18, count 0 2006.285.22:19:58.32#ibcon#read 4, iclass 18, count 0 2006.285.22:19:58.32#ibcon#about to read 5, iclass 18, count 0 2006.285.22:19:58.32#ibcon#read 5, iclass 18, count 0 2006.285.22:19:58.32#ibcon#about to read 6, iclass 18, count 0 2006.285.22:19:58.32#ibcon#read 6, iclass 18, count 0 2006.285.22:19:58.32#ibcon#end of sib2, iclass 18, count 0 2006.285.22:19:58.32#ibcon#*after write, iclass 18, count 0 2006.285.22:19:58.32#ibcon#*before return 0, iclass 18, count 0 2006.285.22:19:58.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:19:58.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:19:58.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.22:19:58.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.22:19:58.32$vck44/valo=2,534.99 2006.285.22:19:58.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.22:19:58.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.22:19:58.32#ibcon#ireg 17 cls_cnt 0 2006.285.22:19:58.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:19:58.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:19:58.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:19:58.32#ibcon#enter wrdev, iclass 20, count 0 2006.285.22:19:58.32#ibcon#first serial, iclass 20, count 0 2006.285.22:19:58.32#ibcon#enter sib2, iclass 20, count 0 2006.285.22:19:58.32#ibcon#flushed, iclass 20, count 0 2006.285.22:19:58.32#ibcon#about to write, iclass 20, count 0 2006.285.22:19:58.32#ibcon#wrote, iclass 20, count 0 2006.285.22:19:58.32#ibcon#about to read 3, iclass 20, count 0 2006.285.22:19:58.34#ibcon#read 3, iclass 20, count 0 2006.285.22:19:58.34#ibcon#about to read 4, iclass 20, count 0 2006.285.22:19:58.34#ibcon#read 4, iclass 20, count 0 2006.285.22:19:58.34#ibcon#about to read 5, iclass 20, count 0 2006.285.22:19:58.34#ibcon#read 5, iclass 20, count 0 2006.285.22:19:58.34#ibcon#about to read 6, iclass 20, count 0 2006.285.22:19:58.34#ibcon#read 6, iclass 20, count 0 2006.285.22:19:58.34#ibcon#end of sib2, iclass 20, count 0 2006.285.22:19:58.34#ibcon#*mode == 0, iclass 20, count 0 2006.285.22:19:58.34#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.22:19:58.34#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:19:58.34#ibcon#*before write, iclass 20, count 0 2006.285.22:19:58.34#ibcon#enter sib2, iclass 20, count 0 2006.285.22:19:58.34#ibcon#flushed, iclass 20, count 0 2006.285.22:19:58.34#ibcon#about to write, iclass 20, count 0 2006.285.22:19:58.34#ibcon#wrote, iclass 20, count 0 2006.285.22:19:58.34#ibcon#about to read 3, iclass 20, count 0 2006.285.22:19:58.38#ibcon#read 3, iclass 20, count 0 2006.285.22:19:58.38#ibcon#about to read 4, iclass 20, count 0 2006.285.22:19:58.38#ibcon#read 4, iclass 20, count 0 2006.285.22:19:58.38#ibcon#about to read 5, iclass 20, count 0 2006.285.22:19:58.38#ibcon#read 5, iclass 20, count 0 2006.285.22:19:58.38#ibcon#about to read 6, iclass 20, count 0 2006.285.22:19:58.38#ibcon#read 6, iclass 20, count 0 2006.285.22:19:58.38#ibcon#end of sib2, iclass 20, count 0 2006.285.22:19:58.38#ibcon#*after write, iclass 20, count 0 2006.285.22:19:58.38#ibcon#*before return 0, iclass 20, count 0 2006.285.22:19:58.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:19:58.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:19:58.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.22:19:58.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.22:19:58.38$vck44/va=2,6 2006.285.22:19:58.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.22:19:58.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.22:19:58.38#ibcon#ireg 11 cls_cnt 2 2006.285.22:19:58.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:19:58.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:19:58.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:19:58.44#ibcon#enter wrdev, iclass 22, count 2 2006.285.22:19:58.44#ibcon#first serial, iclass 22, count 2 2006.285.22:19:58.44#ibcon#enter sib2, iclass 22, count 2 2006.285.22:19:58.44#ibcon#flushed, iclass 22, count 2 2006.285.22:19:58.44#ibcon#about to write, iclass 22, count 2 2006.285.22:19:58.44#ibcon#wrote, iclass 22, count 2 2006.285.22:19:58.44#ibcon#about to read 3, iclass 22, count 2 2006.285.22:19:58.46#ibcon#read 3, iclass 22, count 2 2006.285.22:19:58.46#ibcon#about to read 4, iclass 22, count 2 2006.285.22:19:58.46#ibcon#read 4, iclass 22, count 2 2006.285.22:19:58.46#ibcon#about to read 5, iclass 22, count 2 2006.285.22:19:58.46#ibcon#read 5, iclass 22, count 2 2006.285.22:19:58.46#ibcon#about to read 6, iclass 22, count 2 2006.285.22:19:58.46#ibcon#read 6, iclass 22, count 2 2006.285.22:19:58.46#ibcon#end of sib2, iclass 22, count 2 2006.285.22:19:58.46#ibcon#*mode == 0, iclass 22, count 2 2006.285.22:19:58.46#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.22:19:58.46#ibcon#[25=AT02-06\r\n] 2006.285.22:19:58.46#ibcon#*before write, iclass 22, count 2 2006.285.22:19:58.46#ibcon#enter sib2, iclass 22, count 2 2006.285.22:19:58.46#ibcon#flushed, iclass 22, count 2 2006.285.22:19:58.46#ibcon#about to write, iclass 22, count 2 2006.285.22:19:58.46#ibcon#wrote, iclass 22, count 2 2006.285.22:19:58.46#ibcon#about to read 3, iclass 22, count 2 2006.285.22:19:58.49#ibcon#read 3, iclass 22, count 2 2006.285.22:19:58.49#ibcon#about to read 4, iclass 22, count 2 2006.285.22:19:58.49#ibcon#read 4, iclass 22, count 2 2006.285.22:19:58.49#ibcon#about to read 5, iclass 22, count 2 2006.285.22:19:58.49#ibcon#read 5, iclass 22, count 2 2006.285.22:19:58.49#ibcon#about to read 6, iclass 22, count 2 2006.285.22:19:58.49#ibcon#read 6, iclass 22, count 2 2006.285.22:19:58.49#ibcon#end of sib2, iclass 22, count 2 2006.285.22:19:58.49#ibcon#*after write, iclass 22, count 2 2006.285.22:19:58.49#ibcon#*before return 0, iclass 22, count 2 2006.285.22:19:58.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:19:58.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:19:58.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.22:19:58.49#ibcon#ireg 7 cls_cnt 0 2006.285.22:19:58.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:19:58.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:19:58.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:19:58.61#ibcon#enter wrdev, iclass 22, count 0 2006.285.22:19:58.61#ibcon#first serial, iclass 22, count 0 2006.285.22:19:58.61#ibcon#enter sib2, iclass 22, count 0 2006.285.22:19:58.61#ibcon#flushed, iclass 22, count 0 2006.285.22:19:58.61#ibcon#about to write, iclass 22, count 0 2006.285.22:19:58.61#ibcon#wrote, iclass 22, count 0 2006.285.22:19:58.61#ibcon#about to read 3, iclass 22, count 0 2006.285.22:19:58.63#ibcon#read 3, iclass 22, count 0 2006.285.22:19:58.63#ibcon#about to read 4, iclass 22, count 0 2006.285.22:19:58.63#ibcon#read 4, iclass 22, count 0 2006.285.22:19:58.63#ibcon#about to read 5, iclass 22, count 0 2006.285.22:19:58.63#ibcon#read 5, iclass 22, count 0 2006.285.22:19:58.63#ibcon#about to read 6, iclass 22, count 0 2006.285.22:19:58.63#ibcon#read 6, iclass 22, count 0 2006.285.22:19:58.63#ibcon#end of sib2, iclass 22, count 0 2006.285.22:19:58.63#ibcon#*mode == 0, iclass 22, count 0 2006.285.22:19:58.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.22:19:58.63#ibcon#[25=USB\r\n] 2006.285.22:19:58.63#ibcon#*before write, iclass 22, count 0 2006.285.22:19:58.63#ibcon#enter sib2, iclass 22, count 0 2006.285.22:19:58.63#ibcon#flushed, iclass 22, count 0 2006.285.22:19:58.63#ibcon#about to write, iclass 22, count 0 2006.285.22:19:58.63#ibcon#wrote, iclass 22, count 0 2006.285.22:19:58.63#ibcon#about to read 3, iclass 22, count 0 2006.285.22:19:58.66#ibcon#read 3, iclass 22, count 0 2006.285.22:19:58.66#ibcon#about to read 4, iclass 22, count 0 2006.285.22:19:58.66#ibcon#read 4, iclass 22, count 0 2006.285.22:19:58.66#ibcon#about to read 5, iclass 22, count 0 2006.285.22:19:58.66#ibcon#read 5, iclass 22, count 0 2006.285.22:19:58.66#ibcon#about to read 6, iclass 22, count 0 2006.285.22:19:58.66#ibcon#read 6, iclass 22, count 0 2006.285.22:19:58.66#ibcon#end of sib2, iclass 22, count 0 2006.285.22:19:58.66#ibcon#*after write, iclass 22, count 0 2006.285.22:19:58.66#ibcon#*before return 0, iclass 22, count 0 2006.285.22:19:58.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:19:58.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:19:58.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.22:19:58.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.22:19:58.66$vck44/valo=3,564.99 2006.285.22:19:58.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.22:19:58.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.22:19:58.66#ibcon#ireg 17 cls_cnt 0 2006.285.22:19:58.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:19:58.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:19:58.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:19:58.66#ibcon#enter wrdev, iclass 24, count 0 2006.285.22:19:58.66#ibcon#first serial, iclass 24, count 0 2006.285.22:19:58.66#ibcon#enter sib2, iclass 24, count 0 2006.285.22:19:58.66#ibcon#flushed, iclass 24, count 0 2006.285.22:19:58.66#ibcon#about to write, iclass 24, count 0 2006.285.22:19:58.66#ibcon#wrote, iclass 24, count 0 2006.285.22:19:58.66#ibcon#about to read 3, iclass 24, count 0 2006.285.22:19:58.68#ibcon#read 3, iclass 24, count 0 2006.285.22:19:58.68#ibcon#about to read 4, iclass 24, count 0 2006.285.22:19:58.68#ibcon#read 4, iclass 24, count 0 2006.285.22:19:58.68#ibcon#about to read 5, iclass 24, count 0 2006.285.22:19:58.68#ibcon#read 5, iclass 24, count 0 2006.285.22:19:58.68#ibcon#about to read 6, iclass 24, count 0 2006.285.22:19:58.68#ibcon#read 6, iclass 24, count 0 2006.285.22:19:58.68#ibcon#end of sib2, iclass 24, count 0 2006.285.22:19:58.68#ibcon#*mode == 0, iclass 24, count 0 2006.285.22:19:58.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.22:19:58.68#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:19:58.68#ibcon#*before write, iclass 24, count 0 2006.285.22:19:58.68#ibcon#enter sib2, iclass 24, count 0 2006.285.22:19:58.68#ibcon#flushed, iclass 24, count 0 2006.285.22:19:58.68#ibcon#about to write, iclass 24, count 0 2006.285.22:19:58.68#ibcon#wrote, iclass 24, count 0 2006.285.22:19:58.68#ibcon#about to read 3, iclass 24, count 0 2006.285.22:19:58.72#ibcon#read 3, iclass 24, count 0 2006.285.22:19:58.72#ibcon#about to read 4, iclass 24, count 0 2006.285.22:19:58.72#ibcon#read 4, iclass 24, count 0 2006.285.22:19:58.72#ibcon#about to read 5, iclass 24, count 0 2006.285.22:19:58.72#ibcon#read 5, iclass 24, count 0 2006.285.22:19:58.72#ibcon#about to read 6, iclass 24, count 0 2006.285.22:19:58.72#ibcon#read 6, iclass 24, count 0 2006.285.22:19:58.72#ibcon#end of sib2, iclass 24, count 0 2006.285.22:19:58.72#ibcon#*after write, iclass 24, count 0 2006.285.22:19:58.72#ibcon#*before return 0, iclass 24, count 0 2006.285.22:19:58.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:19:58.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:19:58.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.22:19:58.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.22:19:58.72$vck44/va=3,7 2006.285.22:19:58.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.22:19:58.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.22:19:58.72#ibcon#ireg 11 cls_cnt 2 2006.285.22:19:58.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:19:58.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:19:58.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:19:58.78#ibcon#enter wrdev, iclass 26, count 2 2006.285.22:19:58.78#ibcon#first serial, iclass 26, count 2 2006.285.22:19:58.78#ibcon#enter sib2, iclass 26, count 2 2006.285.22:19:58.78#ibcon#flushed, iclass 26, count 2 2006.285.22:19:58.78#ibcon#about to write, iclass 26, count 2 2006.285.22:19:58.78#ibcon#wrote, iclass 26, count 2 2006.285.22:19:58.78#ibcon#about to read 3, iclass 26, count 2 2006.285.22:19:58.80#ibcon#read 3, iclass 26, count 2 2006.285.22:19:58.80#ibcon#about to read 4, iclass 26, count 2 2006.285.22:19:58.80#ibcon#read 4, iclass 26, count 2 2006.285.22:19:58.80#ibcon#about to read 5, iclass 26, count 2 2006.285.22:19:58.80#ibcon#read 5, iclass 26, count 2 2006.285.22:19:58.80#ibcon#about to read 6, iclass 26, count 2 2006.285.22:19:58.80#ibcon#read 6, iclass 26, count 2 2006.285.22:19:58.80#ibcon#end of sib2, iclass 26, count 2 2006.285.22:19:58.80#ibcon#*mode == 0, iclass 26, count 2 2006.285.22:19:58.80#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.22:19:58.80#ibcon#[25=AT03-07\r\n] 2006.285.22:19:58.80#ibcon#*before write, iclass 26, count 2 2006.285.22:19:58.80#ibcon#enter sib2, iclass 26, count 2 2006.285.22:19:58.80#ibcon#flushed, iclass 26, count 2 2006.285.22:19:58.80#ibcon#about to write, iclass 26, count 2 2006.285.22:19:58.80#ibcon#wrote, iclass 26, count 2 2006.285.22:19:58.80#ibcon#about to read 3, iclass 26, count 2 2006.285.22:19:58.83#ibcon#read 3, iclass 26, count 2 2006.285.22:19:58.83#ibcon#about to read 4, iclass 26, count 2 2006.285.22:19:58.83#ibcon#read 4, iclass 26, count 2 2006.285.22:19:58.83#ibcon#about to read 5, iclass 26, count 2 2006.285.22:19:58.83#ibcon#read 5, iclass 26, count 2 2006.285.22:19:58.83#ibcon#about to read 6, iclass 26, count 2 2006.285.22:19:58.83#ibcon#read 6, iclass 26, count 2 2006.285.22:19:58.83#ibcon#end of sib2, iclass 26, count 2 2006.285.22:19:58.83#ibcon#*after write, iclass 26, count 2 2006.285.22:19:58.83#ibcon#*before return 0, iclass 26, count 2 2006.285.22:19:58.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:19:58.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:19:58.83#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.22:19:58.83#ibcon#ireg 7 cls_cnt 0 2006.285.22:19:58.83#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:19:58.95#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:19:58.95#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:19:58.95#ibcon#enter wrdev, iclass 26, count 0 2006.285.22:19:58.95#ibcon#first serial, iclass 26, count 0 2006.285.22:19:58.95#ibcon#enter sib2, iclass 26, count 0 2006.285.22:19:58.95#ibcon#flushed, iclass 26, count 0 2006.285.22:19:58.95#ibcon#about to write, iclass 26, count 0 2006.285.22:19:58.95#ibcon#wrote, iclass 26, count 0 2006.285.22:19:58.95#ibcon#about to read 3, iclass 26, count 0 2006.285.22:19:58.97#ibcon#read 3, iclass 26, count 0 2006.285.22:19:58.97#ibcon#about to read 4, iclass 26, count 0 2006.285.22:19:58.97#ibcon#read 4, iclass 26, count 0 2006.285.22:19:58.97#ibcon#about to read 5, iclass 26, count 0 2006.285.22:19:58.97#ibcon#read 5, iclass 26, count 0 2006.285.22:19:58.97#ibcon#about to read 6, iclass 26, count 0 2006.285.22:19:58.97#ibcon#read 6, iclass 26, count 0 2006.285.22:19:58.97#ibcon#end of sib2, iclass 26, count 0 2006.285.22:19:58.97#ibcon#*mode == 0, iclass 26, count 0 2006.285.22:19:58.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.22:19:58.97#ibcon#[25=USB\r\n] 2006.285.22:19:58.97#ibcon#*before write, iclass 26, count 0 2006.285.22:19:58.97#ibcon#enter sib2, iclass 26, count 0 2006.285.22:19:58.97#ibcon#flushed, iclass 26, count 0 2006.285.22:19:58.97#ibcon#about to write, iclass 26, count 0 2006.285.22:19:58.97#ibcon#wrote, iclass 26, count 0 2006.285.22:19:58.97#ibcon#about to read 3, iclass 26, count 0 2006.285.22:19:59.00#ibcon#read 3, iclass 26, count 0 2006.285.22:19:59.00#ibcon#about to read 4, iclass 26, count 0 2006.285.22:19:59.00#ibcon#read 4, iclass 26, count 0 2006.285.22:19:59.00#ibcon#about to read 5, iclass 26, count 0 2006.285.22:19:59.00#ibcon#read 5, iclass 26, count 0 2006.285.22:19:59.00#ibcon#about to read 6, iclass 26, count 0 2006.285.22:19:59.00#ibcon#read 6, iclass 26, count 0 2006.285.22:19:59.00#ibcon#end of sib2, iclass 26, count 0 2006.285.22:19:59.00#ibcon#*after write, iclass 26, count 0 2006.285.22:19:59.00#ibcon#*before return 0, iclass 26, count 0 2006.285.22:19:59.00#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:19:59.00#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:19:59.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.22:19:59.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.22:19:59.00$vck44/valo=4,624.99 2006.285.22:19:59.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.22:19:59.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.22:19:59.00#ibcon#ireg 17 cls_cnt 0 2006.285.22:19:59.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:19:59.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:19:59.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:19:59.00#ibcon#enter wrdev, iclass 28, count 0 2006.285.22:19:59.00#ibcon#first serial, iclass 28, count 0 2006.285.22:19:59.00#ibcon#enter sib2, iclass 28, count 0 2006.285.22:19:59.00#ibcon#flushed, iclass 28, count 0 2006.285.22:19:59.00#ibcon#about to write, iclass 28, count 0 2006.285.22:19:59.00#ibcon#wrote, iclass 28, count 0 2006.285.22:19:59.00#ibcon#about to read 3, iclass 28, count 0 2006.285.22:19:59.02#ibcon#read 3, iclass 28, count 0 2006.285.22:19:59.02#ibcon#about to read 4, iclass 28, count 0 2006.285.22:19:59.02#ibcon#read 4, iclass 28, count 0 2006.285.22:19:59.02#ibcon#about to read 5, iclass 28, count 0 2006.285.22:19:59.02#ibcon#read 5, iclass 28, count 0 2006.285.22:19:59.02#ibcon#about to read 6, iclass 28, count 0 2006.285.22:19:59.02#ibcon#read 6, iclass 28, count 0 2006.285.22:19:59.02#ibcon#end of sib2, iclass 28, count 0 2006.285.22:19:59.02#ibcon#*mode == 0, iclass 28, count 0 2006.285.22:19:59.02#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.22:19:59.02#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:19:59.02#ibcon#*before write, iclass 28, count 0 2006.285.22:19:59.02#ibcon#enter sib2, iclass 28, count 0 2006.285.22:19:59.02#ibcon#flushed, iclass 28, count 0 2006.285.22:19:59.02#ibcon#about to write, iclass 28, count 0 2006.285.22:19:59.02#ibcon#wrote, iclass 28, count 0 2006.285.22:19:59.02#ibcon#about to read 3, iclass 28, count 0 2006.285.22:19:59.06#ibcon#read 3, iclass 28, count 0 2006.285.22:19:59.06#ibcon#about to read 4, iclass 28, count 0 2006.285.22:19:59.06#ibcon#read 4, iclass 28, count 0 2006.285.22:19:59.06#ibcon#about to read 5, iclass 28, count 0 2006.285.22:19:59.06#ibcon#read 5, iclass 28, count 0 2006.285.22:19:59.06#ibcon#about to read 6, iclass 28, count 0 2006.285.22:19:59.06#ibcon#read 6, iclass 28, count 0 2006.285.22:19:59.06#ibcon#end of sib2, iclass 28, count 0 2006.285.22:19:59.06#ibcon#*after write, iclass 28, count 0 2006.285.22:19:59.06#ibcon#*before return 0, iclass 28, count 0 2006.285.22:19:59.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:19:59.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:19:59.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.22:19:59.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.22:19:59.06$vck44/va=4,6 2006.285.22:19:59.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.22:19:59.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.22:19:59.06#ibcon#ireg 11 cls_cnt 2 2006.285.22:19:59.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:19:59.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:19:59.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:19:59.12#ibcon#enter wrdev, iclass 30, count 2 2006.285.22:19:59.12#ibcon#first serial, iclass 30, count 2 2006.285.22:19:59.12#ibcon#enter sib2, iclass 30, count 2 2006.285.22:19:59.12#ibcon#flushed, iclass 30, count 2 2006.285.22:19:59.12#ibcon#about to write, iclass 30, count 2 2006.285.22:19:59.12#ibcon#wrote, iclass 30, count 2 2006.285.22:19:59.12#ibcon#about to read 3, iclass 30, count 2 2006.285.22:19:59.14#ibcon#read 3, iclass 30, count 2 2006.285.22:19:59.14#ibcon#about to read 4, iclass 30, count 2 2006.285.22:19:59.14#ibcon#read 4, iclass 30, count 2 2006.285.22:19:59.14#ibcon#about to read 5, iclass 30, count 2 2006.285.22:19:59.14#ibcon#read 5, iclass 30, count 2 2006.285.22:19:59.14#ibcon#about to read 6, iclass 30, count 2 2006.285.22:19:59.14#ibcon#read 6, iclass 30, count 2 2006.285.22:19:59.14#ibcon#end of sib2, iclass 30, count 2 2006.285.22:19:59.14#ibcon#*mode == 0, iclass 30, count 2 2006.285.22:19:59.14#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.22:19:59.14#ibcon#[25=AT04-06\r\n] 2006.285.22:19:59.14#ibcon#*before write, iclass 30, count 2 2006.285.22:19:59.14#ibcon#enter sib2, iclass 30, count 2 2006.285.22:19:59.14#ibcon#flushed, iclass 30, count 2 2006.285.22:19:59.14#ibcon#about to write, iclass 30, count 2 2006.285.22:19:59.14#ibcon#wrote, iclass 30, count 2 2006.285.22:19:59.14#ibcon#about to read 3, iclass 30, count 2 2006.285.22:19:59.17#ibcon#read 3, iclass 30, count 2 2006.285.22:19:59.17#ibcon#about to read 4, iclass 30, count 2 2006.285.22:19:59.17#ibcon#read 4, iclass 30, count 2 2006.285.22:19:59.17#ibcon#about to read 5, iclass 30, count 2 2006.285.22:19:59.17#ibcon#read 5, iclass 30, count 2 2006.285.22:19:59.17#ibcon#about to read 6, iclass 30, count 2 2006.285.22:19:59.17#ibcon#read 6, iclass 30, count 2 2006.285.22:19:59.17#ibcon#end of sib2, iclass 30, count 2 2006.285.22:19:59.17#ibcon#*after write, iclass 30, count 2 2006.285.22:19:59.17#ibcon#*before return 0, iclass 30, count 2 2006.285.22:19:59.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:19:59.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:19:59.17#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.22:19:59.17#ibcon#ireg 7 cls_cnt 0 2006.285.22:19:59.17#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:19:59.29#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:19:59.29#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:19:59.29#ibcon#enter wrdev, iclass 30, count 0 2006.285.22:19:59.29#ibcon#first serial, iclass 30, count 0 2006.285.22:19:59.29#ibcon#enter sib2, iclass 30, count 0 2006.285.22:19:59.29#ibcon#flushed, iclass 30, count 0 2006.285.22:19:59.29#ibcon#about to write, iclass 30, count 0 2006.285.22:19:59.29#ibcon#wrote, iclass 30, count 0 2006.285.22:19:59.29#ibcon#about to read 3, iclass 30, count 0 2006.285.22:19:59.31#ibcon#read 3, iclass 30, count 0 2006.285.22:19:59.31#ibcon#about to read 4, iclass 30, count 0 2006.285.22:19:59.31#ibcon#read 4, iclass 30, count 0 2006.285.22:19:59.31#ibcon#about to read 5, iclass 30, count 0 2006.285.22:19:59.31#ibcon#read 5, iclass 30, count 0 2006.285.22:19:59.31#ibcon#about to read 6, iclass 30, count 0 2006.285.22:19:59.31#ibcon#read 6, iclass 30, count 0 2006.285.22:19:59.31#ibcon#end of sib2, iclass 30, count 0 2006.285.22:19:59.31#ibcon#*mode == 0, iclass 30, count 0 2006.285.22:19:59.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.22:19:59.31#ibcon#[25=USB\r\n] 2006.285.22:19:59.31#ibcon#*before write, iclass 30, count 0 2006.285.22:19:59.31#ibcon#enter sib2, iclass 30, count 0 2006.285.22:19:59.31#ibcon#flushed, iclass 30, count 0 2006.285.22:19:59.31#ibcon#about to write, iclass 30, count 0 2006.285.22:19:59.31#ibcon#wrote, iclass 30, count 0 2006.285.22:19:59.31#ibcon#about to read 3, iclass 30, count 0 2006.285.22:19:59.34#ibcon#read 3, iclass 30, count 0 2006.285.22:19:59.34#ibcon#about to read 4, iclass 30, count 0 2006.285.22:19:59.34#ibcon#read 4, iclass 30, count 0 2006.285.22:19:59.34#ibcon#about to read 5, iclass 30, count 0 2006.285.22:19:59.34#ibcon#read 5, iclass 30, count 0 2006.285.22:19:59.34#ibcon#about to read 6, iclass 30, count 0 2006.285.22:19:59.34#ibcon#read 6, iclass 30, count 0 2006.285.22:19:59.34#ibcon#end of sib2, iclass 30, count 0 2006.285.22:19:59.34#ibcon#*after write, iclass 30, count 0 2006.285.22:19:59.34#ibcon#*before return 0, iclass 30, count 0 2006.285.22:19:59.34#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:19:59.34#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:19:59.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.22:19:59.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.22:19:59.34$vck44/valo=5,734.99 2006.285.22:19:59.34#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.22:19:59.34#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.22:19:59.34#ibcon#ireg 17 cls_cnt 0 2006.285.22:19:59.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:19:59.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:19:59.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:19:59.34#ibcon#enter wrdev, iclass 32, count 0 2006.285.22:19:59.34#ibcon#first serial, iclass 32, count 0 2006.285.22:19:59.34#ibcon#enter sib2, iclass 32, count 0 2006.285.22:19:59.34#ibcon#flushed, iclass 32, count 0 2006.285.22:19:59.34#ibcon#about to write, iclass 32, count 0 2006.285.22:19:59.34#ibcon#wrote, iclass 32, count 0 2006.285.22:19:59.34#ibcon#about to read 3, iclass 32, count 0 2006.285.22:19:59.36#ibcon#read 3, iclass 32, count 0 2006.285.22:19:59.36#ibcon#about to read 4, iclass 32, count 0 2006.285.22:19:59.36#ibcon#read 4, iclass 32, count 0 2006.285.22:19:59.36#ibcon#about to read 5, iclass 32, count 0 2006.285.22:19:59.36#ibcon#read 5, iclass 32, count 0 2006.285.22:19:59.36#ibcon#about to read 6, iclass 32, count 0 2006.285.22:19:59.36#ibcon#read 6, iclass 32, count 0 2006.285.22:19:59.36#ibcon#end of sib2, iclass 32, count 0 2006.285.22:19:59.36#ibcon#*mode == 0, iclass 32, count 0 2006.285.22:19:59.36#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.22:19:59.36#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:19:59.36#ibcon#*before write, iclass 32, count 0 2006.285.22:19:59.36#ibcon#enter sib2, iclass 32, count 0 2006.285.22:19:59.36#ibcon#flushed, iclass 32, count 0 2006.285.22:19:59.36#ibcon#about to write, iclass 32, count 0 2006.285.22:19:59.36#ibcon#wrote, iclass 32, count 0 2006.285.22:19:59.36#ibcon#about to read 3, iclass 32, count 0 2006.285.22:19:59.40#ibcon#read 3, iclass 32, count 0 2006.285.22:19:59.40#ibcon#about to read 4, iclass 32, count 0 2006.285.22:19:59.40#ibcon#read 4, iclass 32, count 0 2006.285.22:19:59.40#ibcon#about to read 5, iclass 32, count 0 2006.285.22:19:59.40#ibcon#read 5, iclass 32, count 0 2006.285.22:19:59.40#ibcon#about to read 6, iclass 32, count 0 2006.285.22:19:59.40#ibcon#read 6, iclass 32, count 0 2006.285.22:19:59.40#ibcon#end of sib2, iclass 32, count 0 2006.285.22:19:59.40#ibcon#*after write, iclass 32, count 0 2006.285.22:19:59.40#ibcon#*before return 0, iclass 32, count 0 2006.285.22:19:59.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:19:59.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:19:59.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.22:19:59.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.22:19:59.40$vck44/va=5,3 2006.285.22:19:59.40#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.22:19:59.40#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.22:19:59.40#ibcon#ireg 11 cls_cnt 2 2006.285.22:19:59.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:19:59.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:19:59.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:19:59.46#ibcon#enter wrdev, iclass 34, count 2 2006.285.22:19:59.46#ibcon#first serial, iclass 34, count 2 2006.285.22:19:59.46#ibcon#enter sib2, iclass 34, count 2 2006.285.22:19:59.46#ibcon#flushed, iclass 34, count 2 2006.285.22:19:59.46#ibcon#about to write, iclass 34, count 2 2006.285.22:19:59.46#ibcon#wrote, iclass 34, count 2 2006.285.22:19:59.46#ibcon#about to read 3, iclass 34, count 2 2006.285.22:19:59.48#ibcon#read 3, iclass 34, count 2 2006.285.22:19:59.48#ibcon#about to read 4, iclass 34, count 2 2006.285.22:19:59.48#ibcon#read 4, iclass 34, count 2 2006.285.22:19:59.48#ibcon#about to read 5, iclass 34, count 2 2006.285.22:19:59.48#ibcon#read 5, iclass 34, count 2 2006.285.22:19:59.48#ibcon#about to read 6, iclass 34, count 2 2006.285.22:19:59.48#ibcon#read 6, iclass 34, count 2 2006.285.22:19:59.48#ibcon#end of sib2, iclass 34, count 2 2006.285.22:19:59.48#ibcon#*mode == 0, iclass 34, count 2 2006.285.22:19:59.48#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.22:19:59.48#ibcon#[25=AT05-03\r\n] 2006.285.22:19:59.48#ibcon#*before write, iclass 34, count 2 2006.285.22:19:59.48#ibcon#enter sib2, iclass 34, count 2 2006.285.22:19:59.48#ibcon#flushed, iclass 34, count 2 2006.285.22:19:59.48#ibcon#about to write, iclass 34, count 2 2006.285.22:19:59.48#ibcon#wrote, iclass 34, count 2 2006.285.22:19:59.48#ibcon#about to read 3, iclass 34, count 2 2006.285.22:19:59.51#ibcon#read 3, iclass 34, count 2 2006.285.22:19:59.51#ibcon#about to read 4, iclass 34, count 2 2006.285.22:19:59.51#ibcon#read 4, iclass 34, count 2 2006.285.22:19:59.51#ibcon#about to read 5, iclass 34, count 2 2006.285.22:19:59.51#ibcon#read 5, iclass 34, count 2 2006.285.22:19:59.51#ibcon#about to read 6, iclass 34, count 2 2006.285.22:19:59.51#ibcon#read 6, iclass 34, count 2 2006.285.22:19:59.51#ibcon#end of sib2, iclass 34, count 2 2006.285.22:19:59.51#ibcon#*after write, iclass 34, count 2 2006.285.22:19:59.51#ibcon#*before return 0, iclass 34, count 2 2006.285.22:19:59.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:19:59.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:19:59.51#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.22:19:59.51#ibcon#ireg 7 cls_cnt 0 2006.285.22:19:59.51#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:19:59.63#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:19:59.63#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:19:59.63#ibcon#enter wrdev, iclass 34, count 0 2006.285.22:19:59.63#ibcon#first serial, iclass 34, count 0 2006.285.22:19:59.63#ibcon#enter sib2, iclass 34, count 0 2006.285.22:19:59.63#ibcon#flushed, iclass 34, count 0 2006.285.22:19:59.63#ibcon#about to write, iclass 34, count 0 2006.285.22:19:59.63#ibcon#wrote, iclass 34, count 0 2006.285.22:19:59.63#ibcon#about to read 3, iclass 34, count 0 2006.285.22:19:59.65#ibcon#read 3, iclass 34, count 0 2006.285.22:19:59.65#ibcon#about to read 4, iclass 34, count 0 2006.285.22:19:59.65#ibcon#read 4, iclass 34, count 0 2006.285.22:19:59.65#ibcon#about to read 5, iclass 34, count 0 2006.285.22:19:59.65#ibcon#read 5, iclass 34, count 0 2006.285.22:19:59.65#ibcon#about to read 6, iclass 34, count 0 2006.285.22:19:59.65#ibcon#read 6, iclass 34, count 0 2006.285.22:19:59.65#ibcon#end of sib2, iclass 34, count 0 2006.285.22:19:59.65#ibcon#*mode == 0, iclass 34, count 0 2006.285.22:19:59.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.22:19:59.65#ibcon#[25=USB\r\n] 2006.285.22:19:59.65#ibcon#*before write, iclass 34, count 0 2006.285.22:19:59.65#ibcon#enter sib2, iclass 34, count 0 2006.285.22:19:59.65#ibcon#flushed, iclass 34, count 0 2006.285.22:19:59.65#ibcon#about to write, iclass 34, count 0 2006.285.22:19:59.65#ibcon#wrote, iclass 34, count 0 2006.285.22:19:59.65#ibcon#about to read 3, iclass 34, count 0 2006.285.22:19:59.68#ibcon#read 3, iclass 34, count 0 2006.285.22:19:59.68#ibcon#about to read 4, iclass 34, count 0 2006.285.22:19:59.68#ibcon#read 4, iclass 34, count 0 2006.285.22:19:59.68#ibcon#about to read 5, iclass 34, count 0 2006.285.22:19:59.68#ibcon#read 5, iclass 34, count 0 2006.285.22:19:59.68#ibcon#about to read 6, iclass 34, count 0 2006.285.22:19:59.68#ibcon#read 6, iclass 34, count 0 2006.285.22:19:59.68#ibcon#end of sib2, iclass 34, count 0 2006.285.22:19:59.68#ibcon#*after write, iclass 34, count 0 2006.285.22:19:59.68#ibcon#*before return 0, iclass 34, count 0 2006.285.22:19:59.68#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:19:59.68#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:19:59.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.22:19:59.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.22:19:59.68$vck44/valo=6,814.99 2006.285.22:19:59.68#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.22:19:59.68#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.22:19:59.68#ibcon#ireg 17 cls_cnt 0 2006.285.22:19:59.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:19:59.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:19:59.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:19:59.68#ibcon#enter wrdev, iclass 36, count 0 2006.285.22:19:59.68#ibcon#first serial, iclass 36, count 0 2006.285.22:19:59.68#ibcon#enter sib2, iclass 36, count 0 2006.285.22:19:59.68#ibcon#flushed, iclass 36, count 0 2006.285.22:19:59.68#ibcon#about to write, iclass 36, count 0 2006.285.22:19:59.68#ibcon#wrote, iclass 36, count 0 2006.285.22:19:59.68#ibcon#about to read 3, iclass 36, count 0 2006.285.22:19:59.70#ibcon#read 3, iclass 36, count 0 2006.285.22:19:59.70#ibcon#about to read 4, iclass 36, count 0 2006.285.22:19:59.70#ibcon#read 4, iclass 36, count 0 2006.285.22:19:59.70#ibcon#about to read 5, iclass 36, count 0 2006.285.22:19:59.70#ibcon#read 5, iclass 36, count 0 2006.285.22:19:59.70#ibcon#about to read 6, iclass 36, count 0 2006.285.22:19:59.70#ibcon#read 6, iclass 36, count 0 2006.285.22:19:59.70#ibcon#end of sib2, iclass 36, count 0 2006.285.22:19:59.70#ibcon#*mode == 0, iclass 36, count 0 2006.285.22:19:59.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.22:19:59.70#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:19:59.70#ibcon#*before write, iclass 36, count 0 2006.285.22:19:59.70#ibcon#enter sib2, iclass 36, count 0 2006.285.22:19:59.70#ibcon#flushed, iclass 36, count 0 2006.285.22:19:59.70#ibcon#about to write, iclass 36, count 0 2006.285.22:19:59.70#ibcon#wrote, iclass 36, count 0 2006.285.22:19:59.70#ibcon#about to read 3, iclass 36, count 0 2006.285.22:19:59.74#ibcon#read 3, iclass 36, count 0 2006.285.22:19:59.74#ibcon#about to read 4, iclass 36, count 0 2006.285.22:19:59.74#ibcon#read 4, iclass 36, count 0 2006.285.22:19:59.74#ibcon#about to read 5, iclass 36, count 0 2006.285.22:19:59.74#ibcon#read 5, iclass 36, count 0 2006.285.22:19:59.74#ibcon#about to read 6, iclass 36, count 0 2006.285.22:19:59.74#ibcon#read 6, iclass 36, count 0 2006.285.22:19:59.74#ibcon#end of sib2, iclass 36, count 0 2006.285.22:19:59.74#ibcon#*after write, iclass 36, count 0 2006.285.22:19:59.74#ibcon#*before return 0, iclass 36, count 0 2006.285.22:19:59.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:19:59.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:19:59.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.22:19:59.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.22:19:59.74$vck44/va=6,4 2006.285.22:19:59.74#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.22:19:59.74#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.22:19:59.74#ibcon#ireg 11 cls_cnt 2 2006.285.22:19:59.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:19:59.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:19:59.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:19:59.80#ibcon#enter wrdev, iclass 38, count 2 2006.285.22:19:59.80#ibcon#first serial, iclass 38, count 2 2006.285.22:19:59.80#ibcon#enter sib2, iclass 38, count 2 2006.285.22:19:59.80#ibcon#flushed, iclass 38, count 2 2006.285.22:19:59.80#ibcon#about to write, iclass 38, count 2 2006.285.22:19:59.80#ibcon#wrote, iclass 38, count 2 2006.285.22:19:59.80#ibcon#about to read 3, iclass 38, count 2 2006.285.22:19:59.82#ibcon#read 3, iclass 38, count 2 2006.285.22:19:59.82#ibcon#about to read 4, iclass 38, count 2 2006.285.22:19:59.82#ibcon#read 4, iclass 38, count 2 2006.285.22:19:59.82#ibcon#about to read 5, iclass 38, count 2 2006.285.22:19:59.82#ibcon#read 5, iclass 38, count 2 2006.285.22:19:59.82#ibcon#about to read 6, iclass 38, count 2 2006.285.22:19:59.82#ibcon#read 6, iclass 38, count 2 2006.285.22:19:59.82#ibcon#end of sib2, iclass 38, count 2 2006.285.22:19:59.82#ibcon#*mode == 0, iclass 38, count 2 2006.285.22:19:59.82#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.22:19:59.82#ibcon#[25=AT06-04\r\n] 2006.285.22:19:59.82#ibcon#*before write, iclass 38, count 2 2006.285.22:19:59.82#ibcon#enter sib2, iclass 38, count 2 2006.285.22:19:59.82#ibcon#flushed, iclass 38, count 2 2006.285.22:19:59.82#ibcon#about to write, iclass 38, count 2 2006.285.22:19:59.82#ibcon#wrote, iclass 38, count 2 2006.285.22:19:59.82#ibcon#about to read 3, iclass 38, count 2 2006.285.22:19:59.85#ibcon#read 3, iclass 38, count 2 2006.285.22:19:59.85#ibcon#about to read 4, iclass 38, count 2 2006.285.22:19:59.85#ibcon#read 4, iclass 38, count 2 2006.285.22:19:59.85#ibcon#about to read 5, iclass 38, count 2 2006.285.22:19:59.85#ibcon#read 5, iclass 38, count 2 2006.285.22:19:59.85#ibcon#about to read 6, iclass 38, count 2 2006.285.22:19:59.85#ibcon#read 6, iclass 38, count 2 2006.285.22:19:59.85#ibcon#end of sib2, iclass 38, count 2 2006.285.22:19:59.85#ibcon#*after write, iclass 38, count 2 2006.285.22:19:59.85#ibcon#*before return 0, iclass 38, count 2 2006.285.22:19:59.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:19:59.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:19:59.85#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.22:19:59.85#ibcon#ireg 7 cls_cnt 0 2006.285.22:19:59.85#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:19:59.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:19:59.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:19:59.97#ibcon#enter wrdev, iclass 38, count 0 2006.285.22:19:59.97#ibcon#first serial, iclass 38, count 0 2006.285.22:19:59.97#ibcon#enter sib2, iclass 38, count 0 2006.285.22:19:59.97#ibcon#flushed, iclass 38, count 0 2006.285.22:19:59.97#ibcon#about to write, iclass 38, count 0 2006.285.22:19:59.97#ibcon#wrote, iclass 38, count 0 2006.285.22:19:59.97#ibcon#about to read 3, iclass 38, count 0 2006.285.22:19:59.99#ibcon#read 3, iclass 38, count 0 2006.285.22:19:59.99#ibcon#about to read 4, iclass 38, count 0 2006.285.22:19:59.99#ibcon#read 4, iclass 38, count 0 2006.285.22:19:59.99#ibcon#about to read 5, iclass 38, count 0 2006.285.22:19:59.99#ibcon#read 5, iclass 38, count 0 2006.285.22:19:59.99#ibcon#about to read 6, iclass 38, count 0 2006.285.22:19:59.99#ibcon#read 6, iclass 38, count 0 2006.285.22:19:59.99#ibcon#end of sib2, iclass 38, count 0 2006.285.22:19:59.99#ibcon#*mode == 0, iclass 38, count 0 2006.285.22:19:59.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.22:19:59.99#ibcon#[25=USB\r\n] 2006.285.22:19:59.99#ibcon#*before write, iclass 38, count 0 2006.285.22:19:59.99#ibcon#enter sib2, iclass 38, count 0 2006.285.22:19:59.99#ibcon#flushed, iclass 38, count 0 2006.285.22:19:59.99#ibcon#about to write, iclass 38, count 0 2006.285.22:19:59.99#ibcon#wrote, iclass 38, count 0 2006.285.22:19:59.99#ibcon#about to read 3, iclass 38, count 0 2006.285.22:20:00.02#ibcon#read 3, iclass 38, count 0 2006.285.22:20:00.02#ibcon#about to read 4, iclass 38, count 0 2006.285.22:20:00.02#ibcon#read 4, iclass 38, count 0 2006.285.22:20:00.02#ibcon#about to read 5, iclass 38, count 0 2006.285.22:20:00.02#ibcon#read 5, iclass 38, count 0 2006.285.22:20:00.02#ibcon#about to read 6, iclass 38, count 0 2006.285.22:20:00.02#ibcon#read 6, iclass 38, count 0 2006.285.22:20:00.02#ibcon#end of sib2, iclass 38, count 0 2006.285.22:20:00.02#ibcon#*after write, iclass 38, count 0 2006.285.22:20:00.02#ibcon#*before return 0, iclass 38, count 0 2006.285.22:20:00.02#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:20:00.02#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:20:00.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.22:20:00.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.22:20:00.02$vck44/valo=7,864.99 2006.285.22:20:00.02#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.22:20:00.02#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.22:20:00.02#ibcon#ireg 17 cls_cnt 0 2006.285.22:20:00.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:20:00.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:20:00.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:20:00.02#ibcon#enter wrdev, iclass 40, count 0 2006.285.22:20:00.02#ibcon#first serial, iclass 40, count 0 2006.285.22:20:00.02#ibcon#enter sib2, iclass 40, count 0 2006.285.22:20:00.02#ibcon#flushed, iclass 40, count 0 2006.285.22:20:00.02#ibcon#about to write, iclass 40, count 0 2006.285.22:20:00.02#ibcon#wrote, iclass 40, count 0 2006.285.22:20:00.02#ibcon#about to read 3, iclass 40, count 0 2006.285.22:20:00.04#ibcon#read 3, iclass 40, count 0 2006.285.22:20:00.04#ibcon#about to read 4, iclass 40, count 0 2006.285.22:20:00.04#ibcon#read 4, iclass 40, count 0 2006.285.22:20:00.04#ibcon#about to read 5, iclass 40, count 0 2006.285.22:20:00.04#ibcon#read 5, iclass 40, count 0 2006.285.22:20:00.04#ibcon#about to read 6, iclass 40, count 0 2006.285.22:20:00.04#ibcon#read 6, iclass 40, count 0 2006.285.22:20:00.04#ibcon#end of sib2, iclass 40, count 0 2006.285.22:20:00.04#ibcon#*mode == 0, iclass 40, count 0 2006.285.22:20:00.04#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.22:20:00.04#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:20:00.04#ibcon#*before write, iclass 40, count 0 2006.285.22:20:00.04#ibcon#enter sib2, iclass 40, count 0 2006.285.22:20:00.04#ibcon#flushed, iclass 40, count 0 2006.285.22:20:00.04#ibcon#about to write, iclass 40, count 0 2006.285.22:20:00.04#ibcon#wrote, iclass 40, count 0 2006.285.22:20:00.04#ibcon#about to read 3, iclass 40, count 0 2006.285.22:20:00.08#ibcon#read 3, iclass 40, count 0 2006.285.22:20:00.08#ibcon#about to read 4, iclass 40, count 0 2006.285.22:20:00.08#ibcon#read 4, iclass 40, count 0 2006.285.22:20:00.08#ibcon#about to read 5, iclass 40, count 0 2006.285.22:20:00.08#ibcon#read 5, iclass 40, count 0 2006.285.22:20:00.08#ibcon#about to read 6, iclass 40, count 0 2006.285.22:20:00.08#ibcon#read 6, iclass 40, count 0 2006.285.22:20:00.08#ibcon#end of sib2, iclass 40, count 0 2006.285.22:20:00.08#ibcon#*after write, iclass 40, count 0 2006.285.22:20:00.08#ibcon#*before return 0, iclass 40, count 0 2006.285.22:20:00.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:20:00.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:20:00.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.22:20:00.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.22:20:00.08$vck44/va=7,4 2006.285.22:20:00.08#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.22:20:00.08#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.22:20:00.08#ibcon#ireg 11 cls_cnt 2 2006.285.22:20:00.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:20:00.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:20:00.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:20:00.14#ibcon#enter wrdev, iclass 4, count 2 2006.285.22:20:00.14#ibcon#first serial, iclass 4, count 2 2006.285.22:20:00.14#ibcon#enter sib2, iclass 4, count 2 2006.285.22:20:00.14#ibcon#flushed, iclass 4, count 2 2006.285.22:20:00.14#ibcon#about to write, iclass 4, count 2 2006.285.22:20:00.14#ibcon#wrote, iclass 4, count 2 2006.285.22:20:00.14#ibcon#about to read 3, iclass 4, count 2 2006.285.22:20:00.16#ibcon#read 3, iclass 4, count 2 2006.285.22:20:00.16#ibcon#about to read 4, iclass 4, count 2 2006.285.22:20:00.16#ibcon#read 4, iclass 4, count 2 2006.285.22:20:00.16#ibcon#about to read 5, iclass 4, count 2 2006.285.22:20:00.16#ibcon#read 5, iclass 4, count 2 2006.285.22:20:00.16#ibcon#about to read 6, iclass 4, count 2 2006.285.22:20:00.16#ibcon#read 6, iclass 4, count 2 2006.285.22:20:00.16#ibcon#end of sib2, iclass 4, count 2 2006.285.22:20:00.16#ibcon#*mode == 0, iclass 4, count 2 2006.285.22:20:00.16#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.22:20:00.16#ibcon#[25=AT07-04\r\n] 2006.285.22:20:00.16#ibcon#*before write, iclass 4, count 2 2006.285.22:20:00.16#ibcon#enter sib2, iclass 4, count 2 2006.285.22:20:00.16#ibcon#flushed, iclass 4, count 2 2006.285.22:20:00.16#ibcon#about to write, iclass 4, count 2 2006.285.22:20:00.16#ibcon#wrote, iclass 4, count 2 2006.285.22:20:00.16#ibcon#about to read 3, iclass 4, count 2 2006.285.22:20:00.19#ibcon#read 3, iclass 4, count 2 2006.285.22:20:00.19#ibcon#about to read 4, iclass 4, count 2 2006.285.22:20:00.19#ibcon#read 4, iclass 4, count 2 2006.285.22:20:00.19#ibcon#about to read 5, iclass 4, count 2 2006.285.22:20:00.19#ibcon#read 5, iclass 4, count 2 2006.285.22:20:00.19#ibcon#about to read 6, iclass 4, count 2 2006.285.22:20:00.19#ibcon#read 6, iclass 4, count 2 2006.285.22:20:00.19#ibcon#end of sib2, iclass 4, count 2 2006.285.22:20:00.19#ibcon#*after write, iclass 4, count 2 2006.285.22:20:00.19#ibcon#*before return 0, iclass 4, count 2 2006.285.22:20:00.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:20:00.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:20:00.19#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.22:20:00.19#ibcon#ireg 7 cls_cnt 0 2006.285.22:20:00.19#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:20:00.31#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:20:00.31#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:20:00.31#ibcon#enter wrdev, iclass 4, count 0 2006.285.22:20:00.31#ibcon#first serial, iclass 4, count 0 2006.285.22:20:00.31#ibcon#enter sib2, iclass 4, count 0 2006.285.22:20:00.31#ibcon#flushed, iclass 4, count 0 2006.285.22:20:00.31#ibcon#about to write, iclass 4, count 0 2006.285.22:20:00.31#ibcon#wrote, iclass 4, count 0 2006.285.22:20:00.31#ibcon#about to read 3, iclass 4, count 0 2006.285.22:20:00.33#ibcon#read 3, iclass 4, count 0 2006.285.22:20:00.33#ibcon#about to read 4, iclass 4, count 0 2006.285.22:20:00.33#ibcon#read 4, iclass 4, count 0 2006.285.22:20:00.33#ibcon#about to read 5, iclass 4, count 0 2006.285.22:20:00.33#ibcon#read 5, iclass 4, count 0 2006.285.22:20:00.33#ibcon#about to read 6, iclass 4, count 0 2006.285.22:20:00.33#ibcon#read 6, iclass 4, count 0 2006.285.22:20:00.33#ibcon#end of sib2, iclass 4, count 0 2006.285.22:20:00.33#ibcon#*mode == 0, iclass 4, count 0 2006.285.22:20:00.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.22:20:00.33#ibcon#[25=USB\r\n] 2006.285.22:20:00.33#ibcon#*before write, iclass 4, count 0 2006.285.22:20:00.33#ibcon#enter sib2, iclass 4, count 0 2006.285.22:20:00.33#ibcon#flushed, iclass 4, count 0 2006.285.22:20:00.33#ibcon#about to write, iclass 4, count 0 2006.285.22:20:00.33#ibcon#wrote, iclass 4, count 0 2006.285.22:20:00.33#ibcon#about to read 3, iclass 4, count 0 2006.285.22:20:00.36#ibcon#read 3, iclass 4, count 0 2006.285.22:20:00.36#ibcon#about to read 4, iclass 4, count 0 2006.285.22:20:00.36#ibcon#read 4, iclass 4, count 0 2006.285.22:20:00.36#ibcon#about to read 5, iclass 4, count 0 2006.285.22:20:00.36#ibcon#read 5, iclass 4, count 0 2006.285.22:20:00.36#ibcon#about to read 6, iclass 4, count 0 2006.285.22:20:00.36#ibcon#read 6, iclass 4, count 0 2006.285.22:20:00.36#ibcon#end of sib2, iclass 4, count 0 2006.285.22:20:00.36#ibcon#*after write, iclass 4, count 0 2006.285.22:20:00.36#ibcon#*before return 0, iclass 4, count 0 2006.285.22:20:00.36#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:20:00.36#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:20:00.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.22:20:00.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.22:20:00.36$vck44/valo=8,884.99 2006.285.22:20:00.36#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.22:20:00.36#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.22:20:00.36#ibcon#ireg 17 cls_cnt 0 2006.285.22:20:00.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:20:00.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:20:00.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:20:00.36#ibcon#enter wrdev, iclass 6, count 0 2006.285.22:20:00.36#ibcon#first serial, iclass 6, count 0 2006.285.22:20:00.36#ibcon#enter sib2, iclass 6, count 0 2006.285.22:20:00.36#ibcon#flushed, iclass 6, count 0 2006.285.22:20:00.36#ibcon#about to write, iclass 6, count 0 2006.285.22:20:00.36#ibcon#wrote, iclass 6, count 0 2006.285.22:20:00.36#ibcon#about to read 3, iclass 6, count 0 2006.285.22:20:00.38#ibcon#read 3, iclass 6, count 0 2006.285.22:20:00.38#ibcon#about to read 4, iclass 6, count 0 2006.285.22:20:00.38#ibcon#read 4, iclass 6, count 0 2006.285.22:20:00.38#ibcon#about to read 5, iclass 6, count 0 2006.285.22:20:00.38#ibcon#read 5, iclass 6, count 0 2006.285.22:20:00.38#ibcon#about to read 6, iclass 6, count 0 2006.285.22:20:00.38#ibcon#read 6, iclass 6, count 0 2006.285.22:20:00.38#ibcon#end of sib2, iclass 6, count 0 2006.285.22:20:00.38#ibcon#*mode == 0, iclass 6, count 0 2006.285.22:20:00.38#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.22:20:00.38#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:20:00.38#ibcon#*before write, iclass 6, count 0 2006.285.22:20:00.38#ibcon#enter sib2, iclass 6, count 0 2006.285.22:20:00.38#ibcon#flushed, iclass 6, count 0 2006.285.22:20:00.38#ibcon#about to write, iclass 6, count 0 2006.285.22:20:00.38#ibcon#wrote, iclass 6, count 0 2006.285.22:20:00.38#ibcon#about to read 3, iclass 6, count 0 2006.285.22:20:00.42#ibcon#read 3, iclass 6, count 0 2006.285.22:20:00.42#ibcon#about to read 4, iclass 6, count 0 2006.285.22:20:00.42#ibcon#read 4, iclass 6, count 0 2006.285.22:20:00.42#ibcon#about to read 5, iclass 6, count 0 2006.285.22:20:00.42#ibcon#read 5, iclass 6, count 0 2006.285.22:20:00.42#ibcon#about to read 6, iclass 6, count 0 2006.285.22:20:00.42#ibcon#read 6, iclass 6, count 0 2006.285.22:20:00.42#ibcon#end of sib2, iclass 6, count 0 2006.285.22:20:00.42#ibcon#*after write, iclass 6, count 0 2006.285.22:20:00.42#ibcon#*before return 0, iclass 6, count 0 2006.285.22:20:00.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:20:00.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:20:00.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.22:20:00.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.22:20:00.42$vck44/va=8,3 2006.285.22:20:00.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.22:20:00.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.22:20:00.42#ibcon#ireg 11 cls_cnt 2 2006.285.22:20:00.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:20:00.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:20:00.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:20:00.48#ibcon#enter wrdev, iclass 10, count 2 2006.285.22:20:00.48#ibcon#first serial, iclass 10, count 2 2006.285.22:20:00.48#ibcon#enter sib2, iclass 10, count 2 2006.285.22:20:00.48#ibcon#flushed, iclass 10, count 2 2006.285.22:20:00.48#ibcon#about to write, iclass 10, count 2 2006.285.22:20:00.48#ibcon#wrote, iclass 10, count 2 2006.285.22:20:00.48#ibcon#about to read 3, iclass 10, count 2 2006.285.22:20:00.50#ibcon#read 3, iclass 10, count 2 2006.285.22:20:00.50#ibcon#about to read 4, iclass 10, count 2 2006.285.22:20:00.50#ibcon#read 4, iclass 10, count 2 2006.285.22:20:00.50#ibcon#about to read 5, iclass 10, count 2 2006.285.22:20:00.50#ibcon#read 5, iclass 10, count 2 2006.285.22:20:00.50#ibcon#about to read 6, iclass 10, count 2 2006.285.22:20:00.50#ibcon#read 6, iclass 10, count 2 2006.285.22:20:00.50#ibcon#end of sib2, iclass 10, count 2 2006.285.22:20:00.50#ibcon#*mode == 0, iclass 10, count 2 2006.285.22:20:00.50#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.22:20:00.50#ibcon#[25=AT08-03\r\n] 2006.285.22:20:00.50#ibcon#*before write, iclass 10, count 2 2006.285.22:20:00.50#ibcon#enter sib2, iclass 10, count 2 2006.285.22:20:00.50#ibcon#flushed, iclass 10, count 2 2006.285.22:20:00.50#ibcon#about to write, iclass 10, count 2 2006.285.22:20:00.50#ibcon#wrote, iclass 10, count 2 2006.285.22:20:00.50#ibcon#about to read 3, iclass 10, count 2 2006.285.22:20:00.53#ibcon#read 3, iclass 10, count 2 2006.285.22:20:00.53#ibcon#about to read 4, iclass 10, count 2 2006.285.22:20:00.53#ibcon#read 4, iclass 10, count 2 2006.285.22:20:00.53#ibcon#about to read 5, iclass 10, count 2 2006.285.22:20:00.53#ibcon#read 5, iclass 10, count 2 2006.285.22:20:00.53#ibcon#about to read 6, iclass 10, count 2 2006.285.22:20:00.53#ibcon#read 6, iclass 10, count 2 2006.285.22:20:00.53#ibcon#end of sib2, iclass 10, count 2 2006.285.22:20:00.53#ibcon#*after write, iclass 10, count 2 2006.285.22:20:00.53#ibcon#*before return 0, iclass 10, count 2 2006.285.22:20:00.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:20:00.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:20:00.53#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.22:20:00.53#ibcon#ireg 7 cls_cnt 0 2006.285.22:20:00.53#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:20:00.65#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:20:00.65#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:20:00.65#ibcon#enter wrdev, iclass 10, count 0 2006.285.22:20:00.65#ibcon#first serial, iclass 10, count 0 2006.285.22:20:00.65#ibcon#enter sib2, iclass 10, count 0 2006.285.22:20:00.65#ibcon#flushed, iclass 10, count 0 2006.285.22:20:00.65#ibcon#about to write, iclass 10, count 0 2006.285.22:20:00.65#ibcon#wrote, iclass 10, count 0 2006.285.22:20:00.65#ibcon#about to read 3, iclass 10, count 0 2006.285.22:20:00.67#ibcon#read 3, iclass 10, count 0 2006.285.22:20:00.67#ibcon#about to read 4, iclass 10, count 0 2006.285.22:20:00.67#ibcon#read 4, iclass 10, count 0 2006.285.22:20:00.67#ibcon#about to read 5, iclass 10, count 0 2006.285.22:20:00.67#ibcon#read 5, iclass 10, count 0 2006.285.22:20:00.67#ibcon#about to read 6, iclass 10, count 0 2006.285.22:20:00.67#ibcon#read 6, iclass 10, count 0 2006.285.22:20:00.67#ibcon#end of sib2, iclass 10, count 0 2006.285.22:20:00.67#ibcon#*mode == 0, iclass 10, count 0 2006.285.22:20:00.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.22:20:00.67#ibcon#[25=USB\r\n] 2006.285.22:20:00.67#ibcon#*before write, iclass 10, count 0 2006.285.22:20:00.67#ibcon#enter sib2, iclass 10, count 0 2006.285.22:20:00.67#ibcon#flushed, iclass 10, count 0 2006.285.22:20:00.67#ibcon#about to write, iclass 10, count 0 2006.285.22:20:00.67#ibcon#wrote, iclass 10, count 0 2006.285.22:20:00.67#ibcon#about to read 3, iclass 10, count 0 2006.285.22:20:00.70#ibcon#read 3, iclass 10, count 0 2006.285.22:20:00.70#ibcon#about to read 4, iclass 10, count 0 2006.285.22:20:00.70#ibcon#read 4, iclass 10, count 0 2006.285.22:20:00.70#ibcon#about to read 5, iclass 10, count 0 2006.285.22:20:00.70#ibcon#read 5, iclass 10, count 0 2006.285.22:20:00.70#ibcon#about to read 6, iclass 10, count 0 2006.285.22:20:00.70#ibcon#read 6, iclass 10, count 0 2006.285.22:20:00.70#ibcon#end of sib2, iclass 10, count 0 2006.285.22:20:00.70#ibcon#*after write, iclass 10, count 0 2006.285.22:20:00.70#ibcon#*before return 0, iclass 10, count 0 2006.285.22:20:00.70#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:20:00.70#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:20:00.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.22:20:00.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.22:20:00.70$vck44/vblo=1,629.99 2006.285.22:20:00.70#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.22:20:00.70#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.22:20:00.70#ibcon#ireg 17 cls_cnt 0 2006.285.22:20:00.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:20:00.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:20:00.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:20:00.70#ibcon#enter wrdev, iclass 12, count 0 2006.285.22:20:00.70#ibcon#first serial, iclass 12, count 0 2006.285.22:20:00.70#ibcon#enter sib2, iclass 12, count 0 2006.285.22:20:00.70#ibcon#flushed, iclass 12, count 0 2006.285.22:20:00.70#ibcon#about to write, iclass 12, count 0 2006.285.22:20:00.70#ibcon#wrote, iclass 12, count 0 2006.285.22:20:00.70#ibcon#about to read 3, iclass 12, count 0 2006.285.22:20:00.72#ibcon#read 3, iclass 12, count 0 2006.285.22:20:00.72#ibcon#about to read 4, iclass 12, count 0 2006.285.22:20:00.72#ibcon#read 4, iclass 12, count 0 2006.285.22:20:00.72#ibcon#about to read 5, iclass 12, count 0 2006.285.22:20:00.72#ibcon#read 5, iclass 12, count 0 2006.285.22:20:00.72#ibcon#about to read 6, iclass 12, count 0 2006.285.22:20:00.72#ibcon#read 6, iclass 12, count 0 2006.285.22:20:00.72#ibcon#end of sib2, iclass 12, count 0 2006.285.22:20:00.72#ibcon#*mode == 0, iclass 12, count 0 2006.285.22:20:00.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.22:20:00.72#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:20:00.72#ibcon#*before write, iclass 12, count 0 2006.285.22:20:00.72#ibcon#enter sib2, iclass 12, count 0 2006.285.22:20:00.72#ibcon#flushed, iclass 12, count 0 2006.285.22:20:00.72#ibcon#about to write, iclass 12, count 0 2006.285.22:20:00.72#ibcon#wrote, iclass 12, count 0 2006.285.22:20:00.72#ibcon#about to read 3, iclass 12, count 0 2006.285.22:20:00.76#ibcon#read 3, iclass 12, count 0 2006.285.22:20:00.76#ibcon#about to read 4, iclass 12, count 0 2006.285.22:20:00.76#ibcon#read 4, iclass 12, count 0 2006.285.22:20:00.76#ibcon#about to read 5, iclass 12, count 0 2006.285.22:20:00.76#ibcon#read 5, iclass 12, count 0 2006.285.22:20:00.76#ibcon#about to read 6, iclass 12, count 0 2006.285.22:20:00.76#ibcon#read 6, iclass 12, count 0 2006.285.22:20:00.76#ibcon#end of sib2, iclass 12, count 0 2006.285.22:20:00.76#ibcon#*after write, iclass 12, count 0 2006.285.22:20:00.76#ibcon#*before return 0, iclass 12, count 0 2006.285.22:20:00.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:20:00.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:20:00.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.22:20:00.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.22:20:00.76$vck44/vb=1,4 2006.285.22:20:00.76#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.22:20:00.76#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.22:20:00.76#ibcon#ireg 11 cls_cnt 2 2006.285.22:20:00.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:20:00.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:20:00.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:20:00.76#ibcon#enter wrdev, iclass 14, count 2 2006.285.22:20:00.76#ibcon#first serial, iclass 14, count 2 2006.285.22:20:00.76#ibcon#enter sib2, iclass 14, count 2 2006.285.22:20:00.76#ibcon#flushed, iclass 14, count 2 2006.285.22:20:00.76#ibcon#about to write, iclass 14, count 2 2006.285.22:20:00.76#ibcon#wrote, iclass 14, count 2 2006.285.22:20:00.76#ibcon#about to read 3, iclass 14, count 2 2006.285.22:20:00.78#ibcon#read 3, iclass 14, count 2 2006.285.22:20:00.78#ibcon#about to read 4, iclass 14, count 2 2006.285.22:20:00.78#ibcon#read 4, iclass 14, count 2 2006.285.22:20:00.78#ibcon#about to read 5, iclass 14, count 2 2006.285.22:20:00.78#ibcon#read 5, iclass 14, count 2 2006.285.22:20:00.78#ibcon#about to read 6, iclass 14, count 2 2006.285.22:20:00.78#ibcon#read 6, iclass 14, count 2 2006.285.22:20:00.78#ibcon#end of sib2, iclass 14, count 2 2006.285.22:20:00.78#ibcon#*mode == 0, iclass 14, count 2 2006.285.22:20:00.78#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.22:20:00.78#ibcon#[27=AT01-04\r\n] 2006.285.22:20:00.78#ibcon#*before write, iclass 14, count 2 2006.285.22:20:00.78#ibcon#enter sib2, iclass 14, count 2 2006.285.22:20:00.78#ibcon#flushed, iclass 14, count 2 2006.285.22:20:00.78#ibcon#about to write, iclass 14, count 2 2006.285.22:20:00.78#ibcon#wrote, iclass 14, count 2 2006.285.22:20:00.78#ibcon#about to read 3, iclass 14, count 2 2006.285.22:20:00.81#ibcon#read 3, iclass 14, count 2 2006.285.22:20:00.81#ibcon#about to read 4, iclass 14, count 2 2006.285.22:20:00.81#ibcon#read 4, iclass 14, count 2 2006.285.22:20:00.81#ibcon#about to read 5, iclass 14, count 2 2006.285.22:20:00.81#ibcon#read 5, iclass 14, count 2 2006.285.22:20:00.81#ibcon#about to read 6, iclass 14, count 2 2006.285.22:20:00.81#ibcon#read 6, iclass 14, count 2 2006.285.22:20:00.81#ibcon#end of sib2, iclass 14, count 2 2006.285.22:20:00.81#ibcon#*after write, iclass 14, count 2 2006.285.22:20:00.81#ibcon#*before return 0, iclass 14, count 2 2006.285.22:20:00.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:20:00.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:20:00.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.22:20:00.81#ibcon#ireg 7 cls_cnt 0 2006.285.22:20:00.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:20:00.93#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:20:00.93#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:20:00.93#ibcon#enter wrdev, iclass 14, count 0 2006.285.22:20:00.93#ibcon#first serial, iclass 14, count 0 2006.285.22:20:00.93#ibcon#enter sib2, iclass 14, count 0 2006.285.22:20:00.93#ibcon#flushed, iclass 14, count 0 2006.285.22:20:00.93#ibcon#about to write, iclass 14, count 0 2006.285.22:20:00.93#ibcon#wrote, iclass 14, count 0 2006.285.22:20:00.93#ibcon#about to read 3, iclass 14, count 0 2006.285.22:20:00.95#ibcon#read 3, iclass 14, count 0 2006.285.22:20:00.95#ibcon#about to read 4, iclass 14, count 0 2006.285.22:20:00.95#ibcon#read 4, iclass 14, count 0 2006.285.22:20:00.95#ibcon#about to read 5, iclass 14, count 0 2006.285.22:20:00.95#ibcon#read 5, iclass 14, count 0 2006.285.22:20:00.95#ibcon#about to read 6, iclass 14, count 0 2006.285.22:20:00.95#ibcon#read 6, iclass 14, count 0 2006.285.22:20:00.95#ibcon#end of sib2, iclass 14, count 0 2006.285.22:20:00.95#ibcon#*mode == 0, iclass 14, count 0 2006.285.22:20:00.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.22:20:00.95#ibcon#[27=USB\r\n] 2006.285.22:20:00.95#ibcon#*before write, iclass 14, count 0 2006.285.22:20:00.95#ibcon#enter sib2, iclass 14, count 0 2006.285.22:20:00.95#ibcon#flushed, iclass 14, count 0 2006.285.22:20:00.95#ibcon#about to write, iclass 14, count 0 2006.285.22:20:00.95#ibcon#wrote, iclass 14, count 0 2006.285.22:20:00.95#ibcon#about to read 3, iclass 14, count 0 2006.285.22:20:00.98#ibcon#read 3, iclass 14, count 0 2006.285.22:20:00.98#ibcon#about to read 4, iclass 14, count 0 2006.285.22:20:00.98#ibcon#read 4, iclass 14, count 0 2006.285.22:20:00.98#ibcon#about to read 5, iclass 14, count 0 2006.285.22:20:00.98#ibcon#read 5, iclass 14, count 0 2006.285.22:20:00.98#ibcon#about to read 6, iclass 14, count 0 2006.285.22:20:00.98#ibcon#read 6, iclass 14, count 0 2006.285.22:20:00.98#ibcon#end of sib2, iclass 14, count 0 2006.285.22:20:00.98#ibcon#*after write, iclass 14, count 0 2006.285.22:20:00.98#ibcon#*before return 0, iclass 14, count 0 2006.285.22:20:00.98#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:20:00.98#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:20:00.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.22:20:00.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.22:20:00.98$vck44/vblo=2,634.99 2006.285.22:20:00.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.22:20:00.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.22:20:00.98#ibcon#ireg 17 cls_cnt 0 2006.285.22:20:00.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:20:00.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:20:00.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:20:00.98#ibcon#enter wrdev, iclass 16, count 0 2006.285.22:20:00.98#ibcon#first serial, iclass 16, count 0 2006.285.22:20:00.98#ibcon#enter sib2, iclass 16, count 0 2006.285.22:20:00.98#ibcon#flushed, iclass 16, count 0 2006.285.22:20:00.98#ibcon#about to write, iclass 16, count 0 2006.285.22:20:00.98#ibcon#wrote, iclass 16, count 0 2006.285.22:20:00.98#ibcon#about to read 3, iclass 16, count 0 2006.285.22:20:01.00#ibcon#read 3, iclass 16, count 0 2006.285.22:20:01.00#ibcon#about to read 4, iclass 16, count 0 2006.285.22:20:01.00#ibcon#read 4, iclass 16, count 0 2006.285.22:20:01.00#ibcon#about to read 5, iclass 16, count 0 2006.285.22:20:01.00#ibcon#read 5, iclass 16, count 0 2006.285.22:20:01.00#ibcon#about to read 6, iclass 16, count 0 2006.285.22:20:01.00#ibcon#read 6, iclass 16, count 0 2006.285.22:20:01.00#ibcon#end of sib2, iclass 16, count 0 2006.285.22:20:01.00#ibcon#*mode == 0, iclass 16, count 0 2006.285.22:20:01.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.22:20:01.00#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:20:01.00#ibcon#*before write, iclass 16, count 0 2006.285.22:20:01.00#ibcon#enter sib2, iclass 16, count 0 2006.285.22:20:01.00#ibcon#flushed, iclass 16, count 0 2006.285.22:20:01.00#ibcon#about to write, iclass 16, count 0 2006.285.22:20:01.00#ibcon#wrote, iclass 16, count 0 2006.285.22:20:01.00#ibcon#about to read 3, iclass 16, count 0 2006.285.22:20:01.04#ibcon#read 3, iclass 16, count 0 2006.285.22:20:01.04#ibcon#about to read 4, iclass 16, count 0 2006.285.22:20:01.04#ibcon#read 4, iclass 16, count 0 2006.285.22:20:01.04#ibcon#about to read 5, iclass 16, count 0 2006.285.22:20:01.04#ibcon#read 5, iclass 16, count 0 2006.285.22:20:01.04#ibcon#about to read 6, iclass 16, count 0 2006.285.22:20:01.04#ibcon#read 6, iclass 16, count 0 2006.285.22:20:01.04#ibcon#end of sib2, iclass 16, count 0 2006.285.22:20:01.04#ibcon#*after write, iclass 16, count 0 2006.285.22:20:01.04#ibcon#*before return 0, iclass 16, count 0 2006.285.22:20:01.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:20:01.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:20:01.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.22:20:01.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.22:20:01.04$vck44/vb=2,5 2006.285.22:20:01.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.22:20:01.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.22:20:01.04#ibcon#ireg 11 cls_cnt 2 2006.285.22:20:01.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:20:01.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:20:01.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:20:01.10#ibcon#enter wrdev, iclass 18, count 2 2006.285.22:20:01.10#ibcon#first serial, iclass 18, count 2 2006.285.22:20:01.10#ibcon#enter sib2, iclass 18, count 2 2006.285.22:20:01.10#ibcon#flushed, iclass 18, count 2 2006.285.22:20:01.10#ibcon#about to write, iclass 18, count 2 2006.285.22:20:01.10#ibcon#wrote, iclass 18, count 2 2006.285.22:20:01.10#ibcon#about to read 3, iclass 18, count 2 2006.285.22:20:01.12#ibcon#read 3, iclass 18, count 2 2006.285.22:20:01.12#ibcon#about to read 4, iclass 18, count 2 2006.285.22:20:01.12#ibcon#read 4, iclass 18, count 2 2006.285.22:20:01.12#ibcon#about to read 5, iclass 18, count 2 2006.285.22:20:01.12#ibcon#read 5, iclass 18, count 2 2006.285.22:20:01.12#ibcon#about to read 6, iclass 18, count 2 2006.285.22:20:01.12#ibcon#read 6, iclass 18, count 2 2006.285.22:20:01.12#ibcon#end of sib2, iclass 18, count 2 2006.285.22:20:01.12#ibcon#*mode == 0, iclass 18, count 2 2006.285.22:20:01.12#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.22:20:01.12#ibcon#[27=AT02-05\r\n] 2006.285.22:20:01.12#ibcon#*before write, iclass 18, count 2 2006.285.22:20:01.12#ibcon#enter sib2, iclass 18, count 2 2006.285.22:20:01.12#ibcon#flushed, iclass 18, count 2 2006.285.22:20:01.12#ibcon#about to write, iclass 18, count 2 2006.285.22:20:01.12#ibcon#wrote, iclass 18, count 2 2006.285.22:20:01.12#ibcon#about to read 3, iclass 18, count 2 2006.285.22:20:01.15#ibcon#read 3, iclass 18, count 2 2006.285.22:20:01.15#ibcon#about to read 4, iclass 18, count 2 2006.285.22:20:01.15#ibcon#read 4, iclass 18, count 2 2006.285.22:20:01.15#ibcon#about to read 5, iclass 18, count 2 2006.285.22:20:01.15#ibcon#read 5, iclass 18, count 2 2006.285.22:20:01.15#ibcon#about to read 6, iclass 18, count 2 2006.285.22:20:01.15#ibcon#read 6, iclass 18, count 2 2006.285.22:20:01.15#ibcon#end of sib2, iclass 18, count 2 2006.285.22:20:01.15#ibcon#*after write, iclass 18, count 2 2006.285.22:20:01.15#ibcon#*before return 0, iclass 18, count 2 2006.285.22:20:01.15#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:20:01.15#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:20:01.15#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.22:20:01.15#ibcon#ireg 7 cls_cnt 0 2006.285.22:20:01.15#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:20:01.27#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:20:01.27#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:20:01.27#ibcon#enter wrdev, iclass 18, count 0 2006.285.22:20:01.27#ibcon#first serial, iclass 18, count 0 2006.285.22:20:01.27#ibcon#enter sib2, iclass 18, count 0 2006.285.22:20:01.27#ibcon#flushed, iclass 18, count 0 2006.285.22:20:01.27#ibcon#about to write, iclass 18, count 0 2006.285.22:20:01.27#ibcon#wrote, iclass 18, count 0 2006.285.22:20:01.27#ibcon#about to read 3, iclass 18, count 0 2006.285.22:20:01.29#ibcon#read 3, iclass 18, count 0 2006.285.22:20:01.29#ibcon#about to read 4, iclass 18, count 0 2006.285.22:20:01.29#ibcon#read 4, iclass 18, count 0 2006.285.22:20:01.29#ibcon#about to read 5, iclass 18, count 0 2006.285.22:20:01.29#ibcon#read 5, iclass 18, count 0 2006.285.22:20:01.29#ibcon#about to read 6, iclass 18, count 0 2006.285.22:20:01.29#ibcon#read 6, iclass 18, count 0 2006.285.22:20:01.29#ibcon#end of sib2, iclass 18, count 0 2006.285.22:20:01.29#ibcon#*mode == 0, iclass 18, count 0 2006.285.22:20:01.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.22:20:01.29#ibcon#[27=USB\r\n] 2006.285.22:20:01.29#ibcon#*before write, iclass 18, count 0 2006.285.22:20:01.29#ibcon#enter sib2, iclass 18, count 0 2006.285.22:20:01.29#ibcon#flushed, iclass 18, count 0 2006.285.22:20:01.29#ibcon#about to write, iclass 18, count 0 2006.285.22:20:01.29#ibcon#wrote, iclass 18, count 0 2006.285.22:20:01.29#ibcon#about to read 3, iclass 18, count 0 2006.285.22:20:01.32#ibcon#read 3, iclass 18, count 0 2006.285.22:20:01.32#ibcon#about to read 4, iclass 18, count 0 2006.285.22:20:01.32#ibcon#read 4, iclass 18, count 0 2006.285.22:20:01.32#ibcon#about to read 5, iclass 18, count 0 2006.285.22:20:01.32#ibcon#read 5, iclass 18, count 0 2006.285.22:20:01.32#ibcon#about to read 6, iclass 18, count 0 2006.285.22:20:01.32#ibcon#read 6, iclass 18, count 0 2006.285.22:20:01.32#ibcon#end of sib2, iclass 18, count 0 2006.285.22:20:01.32#ibcon#*after write, iclass 18, count 0 2006.285.22:20:01.32#ibcon#*before return 0, iclass 18, count 0 2006.285.22:20:01.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:20:01.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:20:01.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.22:20:01.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.22:20:01.32$vck44/vblo=3,649.99 2006.285.22:20:01.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.22:20:01.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.22:20:01.32#ibcon#ireg 17 cls_cnt 0 2006.285.22:20:01.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:20:01.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:20:01.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:20:01.32#ibcon#enter wrdev, iclass 20, count 0 2006.285.22:20:01.32#ibcon#first serial, iclass 20, count 0 2006.285.22:20:01.32#ibcon#enter sib2, iclass 20, count 0 2006.285.22:20:01.32#ibcon#flushed, iclass 20, count 0 2006.285.22:20:01.32#ibcon#about to write, iclass 20, count 0 2006.285.22:20:01.32#ibcon#wrote, iclass 20, count 0 2006.285.22:20:01.32#ibcon#about to read 3, iclass 20, count 0 2006.285.22:20:01.34#ibcon#read 3, iclass 20, count 0 2006.285.22:20:01.34#ibcon#about to read 4, iclass 20, count 0 2006.285.22:20:01.34#ibcon#read 4, iclass 20, count 0 2006.285.22:20:01.34#ibcon#about to read 5, iclass 20, count 0 2006.285.22:20:01.34#ibcon#read 5, iclass 20, count 0 2006.285.22:20:01.34#ibcon#about to read 6, iclass 20, count 0 2006.285.22:20:01.34#ibcon#read 6, iclass 20, count 0 2006.285.22:20:01.34#ibcon#end of sib2, iclass 20, count 0 2006.285.22:20:01.34#ibcon#*mode == 0, iclass 20, count 0 2006.285.22:20:01.34#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.22:20:01.34#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:20:01.34#ibcon#*before write, iclass 20, count 0 2006.285.22:20:01.34#ibcon#enter sib2, iclass 20, count 0 2006.285.22:20:01.34#ibcon#flushed, iclass 20, count 0 2006.285.22:20:01.34#ibcon#about to write, iclass 20, count 0 2006.285.22:20:01.34#ibcon#wrote, iclass 20, count 0 2006.285.22:20:01.34#ibcon#about to read 3, iclass 20, count 0 2006.285.22:20:01.38#ibcon#read 3, iclass 20, count 0 2006.285.22:20:01.38#ibcon#about to read 4, iclass 20, count 0 2006.285.22:20:01.38#ibcon#read 4, iclass 20, count 0 2006.285.22:20:01.38#ibcon#about to read 5, iclass 20, count 0 2006.285.22:20:01.38#ibcon#read 5, iclass 20, count 0 2006.285.22:20:01.38#ibcon#about to read 6, iclass 20, count 0 2006.285.22:20:01.38#ibcon#read 6, iclass 20, count 0 2006.285.22:20:01.38#ibcon#end of sib2, iclass 20, count 0 2006.285.22:20:01.38#ibcon#*after write, iclass 20, count 0 2006.285.22:20:01.38#ibcon#*before return 0, iclass 20, count 0 2006.285.22:20:01.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:20:01.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:20:01.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.22:20:01.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.22:20:01.38$vck44/vb=3,4 2006.285.22:20:01.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.22:20:01.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.22:20:01.38#ibcon#ireg 11 cls_cnt 2 2006.285.22:20:01.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:20:01.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:20:01.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:20:01.44#ibcon#enter wrdev, iclass 22, count 2 2006.285.22:20:01.44#ibcon#first serial, iclass 22, count 2 2006.285.22:20:01.44#ibcon#enter sib2, iclass 22, count 2 2006.285.22:20:01.44#ibcon#flushed, iclass 22, count 2 2006.285.22:20:01.44#ibcon#about to write, iclass 22, count 2 2006.285.22:20:01.44#ibcon#wrote, iclass 22, count 2 2006.285.22:20:01.44#ibcon#about to read 3, iclass 22, count 2 2006.285.22:20:01.46#ibcon#read 3, iclass 22, count 2 2006.285.22:20:01.46#ibcon#about to read 4, iclass 22, count 2 2006.285.22:20:01.46#ibcon#read 4, iclass 22, count 2 2006.285.22:20:01.46#ibcon#about to read 5, iclass 22, count 2 2006.285.22:20:01.46#ibcon#read 5, iclass 22, count 2 2006.285.22:20:01.46#ibcon#about to read 6, iclass 22, count 2 2006.285.22:20:01.46#ibcon#read 6, iclass 22, count 2 2006.285.22:20:01.46#ibcon#end of sib2, iclass 22, count 2 2006.285.22:20:01.46#ibcon#*mode == 0, iclass 22, count 2 2006.285.22:20:01.46#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.22:20:01.46#ibcon#[27=AT03-04\r\n] 2006.285.22:20:01.46#ibcon#*before write, iclass 22, count 2 2006.285.22:20:01.46#ibcon#enter sib2, iclass 22, count 2 2006.285.22:20:01.46#ibcon#flushed, iclass 22, count 2 2006.285.22:20:01.46#ibcon#about to write, iclass 22, count 2 2006.285.22:20:01.46#ibcon#wrote, iclass 22, count 2 2006.285.22:20:01.46#ibcon#about to read 3, iclass 22, count 2 2006.285.22:20:01.49#ibcon#read 3, iclass 22, count 2 2006.285.22:20:01.49#ibcon#about to read 4, iclass 22, count 2 2006.285.22:20:01.49#ibcon#read 4, iclass 22, count 2 2006.285.22:20:01.49#ibcon#about to read 5, iclass 22, count 2 2006.285.22:20:01.49#ibcon#read 5, iclass 22, count 2 2006.285.22:20:01.49#ibcon#about to read 6, iclass 22, count 2 2006.285.22:20:01.49#ibcon#read 6, iclass 22, count 2 2006.285.22:20:01.49#ibcon#end of sib2, iclass 22, count 2 2006.285.22:20:01.49#ibcon#*after write, iclass 22, count 2 2006.285.22:20:01.49#ibcon#*before return 0, iclass 22, count 2 2006.285.22:20:01.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:20:01.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:20:01.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.22:20:01.49#ibcon#ireg 7 cls_cnt 0 2006.285.22:20:01.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:20:01.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:20:01.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:20:01.61#ibcon#enter wrdev, iclass 22, count 0 2006.285.22:20:01.61#ibcon#first serial, iclass 22, count 0 2006.285.22:20:01.61#ibcon#enter sib2, iclass 22, count 0 2006.285.22:20:01.61#ibcon#flushed, iclass 22, count 0 2006.285.22:20:01.61#ibcon#about to write, iclass 22, count 0 2006.285.22:20:01.61#ibcon#wrote, iclass 22, count 0 2006.285.22:20:01.61#ibcon#about to read 3, iclass 22, count 0 2006.285.22:20:01.63#ibcon#read 3, iclass 22, count 0 2006.285.22:20:01.63#ibcon#about to read 4, iclass 22, count 0 2006.285.22:20:01.63#ibcon#read 4, iclass 22, count 0 2006.285.22:20:01.63#ibcon#about to read 5, iclass 22, count 0 2006.285.22:20:01.63#ibcon#read 5, iclass 22, count 0 2006.285.22:20:01.63#ibcon#about to read 6, iclass 22, count 0 2006.285.22:20:01.63#ibcon#read 6, iclass 22, count 0 2006.285.22:20:01.63#ibcon#end of sib2, iclass 22, count 0 2006.285.22:20:01.63#ibcon#*mode == 0, iclass 22, count 0 2006.285.22:20:01.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.22:20:01.63#ibcon#[27=USB\r\n] 2006.285.22:20:01.63#ibcon#*before write, iclass 22, count 0 2006.285.22:20:01.63#ibcon#enter sib2, iclass 22, count 0 2006.285.22:20:01.63#ibcon#flushed, iclass 22, count 0 2006.285.22:20:01.63#ibcon#about to write, iclass 22, count 0 2006.285.22:20:01.63#ibcon#wrote, iclass 22, count 0 2006.285.22:20:01.63#ibcon#about to read 3, iclass 22, count 0 2006.285.22:20:01.66#ibcon#read 3, iclass 22, count 0 2006.285.22:20:01.66#ibcon#about to read 4, iclass 22, count 0 2006.285.22:20:01.66#ibcon#read 4, iclass 22, count 0 2006.285.22:20:01.66#ibcon#about to read 5, iclass 22, count 0 2006.285.22:20:01.66#ibcon#read 5, iclass 22, count 0 2006.285.22:20:01.66#ibcon#about to read 6, iclass 22, count 0 2006.285.22:20:01.66#ibcon#read 6, iclass 22, count 0 2006.285.22:20:01.66#ibcon#end of sib2, iclass 22, count 0 2006.285.22:20:01.66#ibcon#*after write, iclass 22, count 0 2006.285.22:20:01.66#ibcon#*before return 0, iclass 22, count 0 2006.285.22:20:01.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:20:01.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:20:01.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.22:20:01.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.22:20:01.66$vck44/vblo=4,679.99 2006.285.22:20:01.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.22:20:01.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.22:20:01.66#ibcon#ireg 17 cls_cnt 0 2006.285.22:20:01.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:20:01.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:20:01.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:20:01.66#ibcon#enter wrdev, iclass 24, count 0 2006.285.22:20:01.66#ibcon#first serial, iclass 24, count 0 2006.285.22:20:01.66#ibcon#enter sib2, iclass 24, count 0 2006.285.22:20:01.66#ibcon#flushed, iclass 24, count 0 2006.285.22:20:01.66#ibcon#about to write, iclass 24, count 0 2006.285.22:20:01.66#ibcon#wrote, iclass 24, count 0 2006.285.22:20:01.66#ibcon#about to read 3, iclass 24, count 0 2006.285.22:20:01.68#ibcon#read 3, iclass 24, count 0 2006.285.22:20:01.68#ibcon#about to read 4, iclass 24, count 0 2006.285.22:20:01.68#ibcon#read 4, iclass 24, count 0 2006.285.22:20:01.68#ibcon#about to read 5, iclass 24, count 0 2006.285.22:20:01.68#ibcon#read 5, iclass 24, count 0 2006.285.22:20:01.68#ibcon#about to read 6, iclass 24, count 0 2006.285.22:20:01.68#ibcon#read 6, iclass 24, count 0 2006.285.22:20:01.68#ibcon#end of sib2, iclass 24, count 0 2006.285.22:20:01.68#ibcon#*mode == 0, iclass 24, count 0 2006.285.22:20:01.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.22:20:01.68#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.22:20:01.68#ibcon#*before write, iclass 24, count 0 2006.285.22:20:01.68#ibcon#enter sib2, iclass 24, count 0 2006.285.22:20:01.68#ibcon#flushed, iclass 24, count 0 2006.285.22:20:01.68#ibcon#about to write, iclass 24, count 0 2006.285.22:20:01.68#ibcon#wrote, iclass 24, count 0 2006.285.22:20:01.68#ibcon#about to read 3, iclass 24, count 0 2006.285.22:20:01.72#ibcon#read 3, iclass 24, count 0 2006.285.22:20:01.72#ibcon#about to read 4, iclass 24, count 0 2006.285.22:20:01.72#ibcon#read 4, iclass 24, count 0 2006.285.22:20:01.72#ibcon#about to read 5, iclass 24, count 0 2006.285.22:20:01.72#ibcon#read 5, iclass 24, count 0 2006.285.22:20:01.72#ibcon#about to read 6, iclass 24, count 0 2006.285.22:20:01.72#ibcon#read 6, iclass 24, count 0 2006.285.22:20:01.72#ibcon#end of sib2, iclass 24, count 0 2006.285.22:20:01.72#ibcon#*after write, iclass 24, count 0 2006.285.22:20:01.72#ibcon#*before return 0, iclass 24, count 0 2006.285.22:20:01.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:20:01.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:20:01.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.22:20:01.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.22:20:01.72$vck44/vb=4,5 2006.285.22:20:01.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.22:20:01.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.22:20:01.72#ibcon#ireg 11 cls_cnt 2 2006.285.22:20:01.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:20:01.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:20:01.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:20:01.78#ibcon#enter wrdev, iclass 26, count 2 2006.285.22:20:01.78#ibcon#first serial, iclass 26, count 2 2006.285.22:20:01.78#ibcon#enter sib2, iclass 26, count 2 2006.285.22:20:01.78#ibcon#flushed, iclass 26, count 2 2006.285.22:20:01.78#ibcon#about to write, iclass 26, count 2 2006.285.22:20:01.78#ibcon#wrote, iclass 26, count 2 2006.285.22:20:01.78#ibcon#about to read 3, iclass 26, count 2 2006.285.22:20:01.80#ibcon#read 3, iclass 26, count 2 2006.285.22:20:01.80#ibcon#about to read 4, iclass 26, count 2 2006.285.22:20:01.80#ibcon#read 4, iclass 26, count 2 2006.285.22:20:01.80#ibcon#about to read 5, iclass 26, count 2 2006.285.22:20:01.80#ibcon#read 5, iclass 26, count 2 2006.285.22:20:01.80#ibcon#about to read 6, iclass 26, count 2 2006.285.22:20:01.80#ibcon#read 6, iclass 26, count 2 2006.285.22:20:01.80#ibcon#end of sib2, iclass 26, count 2 2006.285.22:20:01.80#ibcon#*mode == 0, iclass 26, count 2 2006.285.22:20:01.80#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.22:20:01.80#ibcon#[27=AT04-05\r\n] 2006.285.22:20:01.80#ibcon#*before write, iclass 26, count 2 2006.285.22:20:01.80#ibcon#enter sib2, iclass 26, count 2 2006.285.22:20:01.80#ibcon#flushed, iclass 26, count 2 2006.285.22:20:01.80#ibcon#about to write, iclass 26, count 2 2006.285.22:20:01.80#ibcon#wrote, iclass 26, count 2 2006.285.22:20:01.80#ibcon#about to read 3, iclass 26, count 2 2006.285.22:20:01.83#ibcon#read 3, iclass 26, count 2 2006.285.22:20:01.83#ibcon#about to read 4, iclass 26, count 2 2006.285.22:20:01.83#ibcon#read 4, iclass 26, count 2 2006.285.22:20:01.83#ibcon#about to read 5, iclass 26, count 2 2006.285.22:20:01.83#ibcon#read 5, iclass 26, count 2 2006.285.22:20:01.83#ibcon#about to read 6, iclass 26, count 2 2006.285.22:20:01.83#ibcon#read 6, iclass 26, count 2 2006.285.22:20:01.83#ibcon#end of sib2, iclass 26, count 2 2006.285.22:20:01.83#ibcon#*after write, iclass 26, count 2 2006.285.22:20:01.83#ibcon#*before return 0, iclass 26, count 2 2006.285.22:20:01.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:20:01.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:20:01.83#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.22:20:01.83#ibcon#ireg 7 cls_cnt 0 2006.285.22:20:01.83#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:20:01.95#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:20:01.95#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:20:01.95#ibcon#enter wrdev, iclass 26, count 0 2006.285.22:20:01.95#ibcon#first serial, iclass 26, count 0 2006.285.22:20:01.95#ibcon#enter sib2, iclass 26, count 0 2006.285.22:20:01.95#ibcon#flushed, iclass 26, count 0 2006.285.22:20:01.95#ibcon#about to write, iclass 26, count 0 2006.285.22:20:01.95#ibcon#wrote, iclass 26, count 0 2006.285.22:20:01.95#ibcon#about to read 3, iclass 26, count 0 2006.285.22:20:01.97#ibcon#read 3, iclass 26, count 0 2006.285.22:20:01.97#ibcon#about to read 4, iclass 26, count 0 2006.285.22:20:01.97#ibcon#read 4, iclass 26, count 0 2006.285.22:20:01.97#ibcon#about to read 5, iclass 26, count 0 2006.285.22:20:01.97#ibcon#read 5, iclass 26, count 0 2006.285.22:20:01.97#ibcon#about to read 6, iclass 26, count 0 2006.285.22:20:01.97#ibcon#read 6, iclass 26, count 0 2006.285.22:20:01.97#ibcon#end of sib2, iclass 26, count 0 2006.285.22:20:01.97#ibcon#*mode == 0, iclass 26, count 0 2006.285.22:20:01.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.22:20:01.97#ibcon#[27=USB\r\n] 2006.285.22:20:01.97#ibcon#*before write, iclass 26, count 0 2006.285.22:20:01.97#ibcon#enter sib2, iclass 26, count 0 2006.285.22:20:01.97#ibcon#flushed, iclass 26, count 0 2006.285.22:20:01.97#ibcon#about to write, iclass 26, count 0 2006.285.22:20:01.97#ibcon#wrote, iclass 26, count 0 2006.285.22:20:01.97#ibcon#about to read 3, iclass 26, count 0 2006.285.22:20:02.00#ibcon#read 3, iclass 26, count 0 2006.285.22:20:02.00#ibcon#about to read 4, iclass 26, count 0 2006.285.22:20:02.00#ibcon#read 4, iclass 26, count 0 2006.285.22:20:02.00#ibcon#about to read 5, iclass 26, count 0 2006.285.22:20:02.00#ibcon#read 5, iclass 26, count 0 2006.285.22:20:02.00#ibcon#about to read 6, iclass 26, count 0 2006.285.22:20:02.00#ibcon#read 6, iclass 26, count 0 2006.285.22:20:02.00#ibcon#end of sib2, iclass 26, count 0 2006.285.22:20:02.00#ibcon#*after write, iclass 26, count 0 2006.285.22:20:02.00#ibcon#*before return 0, iclass 26, count 0 2006.285.22:20:02.00#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:20:02.00#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:20:02.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.22:20:02.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.22:20:02.00$vck44/vblo=5,709.99 2006.285.22:20:02.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.22:20:02.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.22:20:02.00#ibcon#ireg 17 cls_cnt 0 2006.285.22:20:02.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:20:02.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:20:02.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:20:02.00#ibcon#enter wrdev, iclass 28, count 0 2006.285.22:20:02.00#ibcon#first serial, iclass 28, count 0 2006.285.22:20:02.00#ibcon#enter sib2, iclass 28, count 0 2006.285.22:20:02.00#ibcon#flushed, iclass 28, count 0 2006.285.22:20:02.00#ibcon#about to write, iclass 28, count 0 2006.285.22:20:02.00#ibcon#wrote, iclass 28, count 0 2006.285.22:20:02.00#ibcon#about to read 3, iclass 28, count 0 2006.285.22:20:02.02#ibcon#read 3, iclass 28, count 0 2006.285.22:20:02.02#ibcon#about to read 4, iclass 28, count 0 2006.285.22:20:02.02#ibcon#read 4, iclass 28, count 0 2006.285.22:20:02.02#ibcon#about to read 5, iclass 28, count 0 2006.285.22:20:02.02#ibcon#read 5, iclass 28, count 0 2006.285.22:20:02.02#ibcon#about to read 6, iclass 28, count 0 2006.285.22:20:02.02#ibcon#read 6, iclass 28, count 0 2006.285.22:20:02.02#ibcon#end of sib2, iclass 28, count 0 2006.285.22:20:02.02#ibcon#*mode == 0, iclass 28, count 0 2006.285.22:20:02.02#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.22:20:02.02#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.22:20:02.02#ibcon#*before write, iclass 28, count 0 2006.285.22:20:02.02#ibcon#enter sib2, iclass 28, count 0 2006.285.22:20:02.02#ibcon#flushed, iclass 28, count 0 2006.285.22:20:02.02#ibcon#about to write, iclass 28, count 0 2006.285.22:20:02.02#ibcon#wrote, iclass 28, count 0 2006.285.22:20:02.02#ibcon#about to read 3, iclass 28, count 0 2006.285.22:20:02.06#ibcon#read 3, iclass 28, count 0 2006.285.22:20:02.06#ibcon#about to read 4, iclass 28, count 0 2006.285.22:20:02.06#ibcon#read 4, iclass 28, count 0 2006.285.22:20:02.06#ibcon#about to read 5, iclass 28, count 0 2006.285.22:20:02.06#ibcon#read 5, iclass 28, count 0 2006.285.22:20:02.06#ibcon#about to read 6, iclass 28, count 0 2006.285.22:20:02.06#ibcon#read 6, iclass 28, count 0 2006.285.22:20:02.06#ibcon#end of sib2, iclass 28, count 0 2006.285.22:20:02.06#ibcon#*after write, iclass 28, count 0 2006.285.22:20:02.06#ibcon#*before return 0, iclass 28, count 0 2006.285.22:20:02.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:20:02.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:20:02.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.22:20:02.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.22:20:02.06$vck44/vb=5,4 2006.285.22:20:02.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.22:20:02.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.22:20:02.06#ibcon#ireg 11 cls_cnt 2 2006.285.22:20:02.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:20:02.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:20:02.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:20:02.12#ibcon#enter wrdev, iclass 30, count 2 2006.285.22:20:02.12#ibcon#first serial, iclass 30, count 2 2006.285.22:20:02.12#ibcon#enter sib2, iclass 30, count 2 2006.285.22:20:02.12#ibcon#flushed, iclass 30, count 2 2006.285.22:20:02.12#ibcon#about to write, iclass 30, count 2 2006.285.22:20:02.12#ibcon#wrote, iclass 30, count 2 2006.285.22:20:02.12#ibcon#about to read 3, iclass 30, count 2 2006.285.22:20:02.14#ibcon#read 3, iclass 30, count 2 2006.285.22:20:02.14#ibcon#about to read 4, iclass 30, count 2 2006.285.22:20:02.14#ibcon#read 4, iclass 30, count 2 2006.285.22:20:02.14#ibcon#about to read 5, iclass 30, count 2 2006.285.22:20:02.14#ibcon#read 5, iclass 30, count 2 2006.285.22:20:02.14#ibcon#about to read 6, iclass 30, count 2 2006.285.22:20:02.14#ibcon#read 6, iclass 30, count 2 2006.285.22:20:02.14#ibcon#end of sib2, iclass 30, count 2 2006.285.22:20:02.14#ibcon#*mode == 0, iclass 30, count 2 2006.285.22:20:02.14#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.22:20:02.14#ibcon#[27=AT05-04\r\n] 2006.285.22:20:02.14#ibcon#*before write, iclass 30, count 2 2006.285.22:20:02.14#ibcon#enter sib2, iclass 30, count 2 2006.285.22:20:02.14#ibcon#flushed, iclass 30, count 2 2006.285.22:20:02.14#ibcon#about to write, iclass 30, count 2 2006.285.22:20:02.14#ibcon#wrote, iclass 30, count 2 2006.285.22:20:02.14#ibcon#about to read 3, iclass 30, count 2 2006.285.22:20:02.17#ibcon#read 3, iclass 30, count 2 2006.285.22:20:02.17#ibcon#about to read 4, iclass 30, count 2 2006.285.22:20:02.17#ibcon#read 4, iclass 30, count 2 2006.285.22:20:02.17#ibcon#about to read 5, iclass 30, count 2 2006.285.22:20:02.17#ibcon#read 5, iclass 30, count 2 2006.285.22:20:02.17#ibcon#about to read 6, iclass 30, count 2 2006.285.22:20:02.17#ibcon#read 6, iclass 30, count 2 2006.285.22:20:02.17#ibcon#end of sib2, iclass 30, count 2 2006.285.22:20:02.17#ibcon#*after write, iclass 30, count 2 2006.285.22:20:02.17#ibcon#*before return 0, iclass 30, count 2 2006.285.22:20:02.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:20:02.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:20:02.17#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.22:20:02.17#ibcon#ireg 7 cls_cnt 0 2006.285.22:20:02.17#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:20:02.29#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:20:02.29#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:20:02.29#ibcon#enter wrdev, iclass 30, count 0 2006.285.22:20:02.29#ibcon#first serial, iclass 30, count 0 2006.285.22:20:02.29#ibcon#enter sib2, iclass 30, count 0 2006.285.22:20:02.29#ibcon#flushed, iclass 30, count 0 2006.285.22:20:02.29#ibcon#about to write, iclass 30, count 0 2006.285.22:20:02.29#ibcon#wrote, iclass 30, count 0 2006.285.22:20:02.29#ibcon#about to read 3, iclass 30, count 0 2006.285.22:20:02.31#ibcon#read 3, iclass 30, count 0 2006.285.22:20:02.31#ibcon#about to read 4, iclass 30, count 0 2006.285.22:20:02.31#ibcon#read 4, iclass 30, count 0 2006.285.22:20:02.31#ibcon#about to read 5, iclass 30, count 0 2006.285.22:20:02.31#ibcon#read 5, iclass 30, count 0 2006.285.22:20:02.31#ibcon#about to read 6, iclass 30, count 0 2006.285.22:20:02.31#ibcon#read 6, iclass 30, count 0 2006.285.22:20:02.31#ibcon#end of sib2, iclass 30, count 0 2006.285.22:20:02.31#ibcon#*mode == 0, iclass 30, count 0 2006.285.22:20:02.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.22:20:02.31#ibcon#[27=USB\r\n] 2006.285.22:20:02.31#ibcon#*before write, iclass 30, count 0 2006.285.22:20:02.31#ibcon#enter sib2, iclass 30, count 0 2006.285.22:20:02.31#ibcon#flushed, iclass 30, count 0 2006.285.22:20:02.31#ibcon#about to write, iclass 30, count 0 2006.285.22:20:02.31#ibcon#wrote, iclass 30, count 0 2006.285.22:20:02.31#ibcon#about to read 3, iclass 30, count 0 2006.285.22:20:02.34#ibcon#read 3, iclass 30, count 0 2006.285.22:20:02.34#ibcon#about to read 4, iclass 30, count 0 2006.285.22:20:02.34#ibcon#read 4, iclass 30, count 0 2006.285.22:20:02.34#ibcon#about to read 5, iclass 30, count 0 2006.285.22:20:02.34#ibcon#read 5, iclass 30, count 0 2006.285.22:20:02.34#ibcon#about to read 6, iclass 30, count 0 2006.285.22:20:02.34#ibcon#read 6, iclass 30, count 0 2006.285.22:20:02.34#ibcon#end of sib2, iclass 30, count 0 2006.285.22:20:02.34#ibcon#*after write, iclass 30, count 0 2006.285.22:20:02.34#ibcon#*before return 0, iclass 30, count 0 2006.285.22:20:02.34#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:20:02.34#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:20:02.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.22:20:02.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.22:20:02.34$vck44/vblo=6,719.99 2006.285.22:20:02.34#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.22:20:02.34#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.22:20:02.34#ibcon#ireg 17 cls_cnt 0 2006.285.22:20:02.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:20:02.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:20:02.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:20:02.34#ibcon#enter wrdev, iclass 32, count 0 2006.285.22:20:02.34#ibcon#first serial, iclass 32, count 0 2006.285.22:20:02.34#ibcon#enter sib2, iclass 32, count 0 2006.285.22:20:02.34#ibcon#flushed, iclass 32, count 0 2006.285.22:20:02.34#ibcon#about to write, iclass 32, count 0 2006.285.22:20:02.34#ibcon#wrote, iclass 32, count 0 2006.285.22:20:02.34#ibcon#about to read 3, iclass 32, count 0 2006.285.22:20:02.36#ibcon#read 3, iclass 32, count 0 2006.285.22:20:02.36#ibcon#about to read 4, iclass 32, count 0 2006.285.22:20:02.36#ibcon#read 4, iclass 32, count 0 2006.285.22:20:02.36#ibcon#about to read 5, iclass 32, count 0 2006.285.22:20:02.36#ibcon#read 5, iclass 32, count 0 2006.285.22:20:02.36#ibcon#about to read 6, iclass 32, count 0 2006.285.22:20:02.36#ibcon#read 6, iclass 32, count 0 2006.285.22:20:02.36#ibcon#end of sib2, iclass 32, count 0 2006.285.22:20:02.36#ibcon#*mode == 0, iclass 32, count 0 2006.285.22:20:02.36#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.22:20:02.36#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.22:20:02.36#ibcon#*before write, iclass 32, count 0 2006.285.22:20:02.36#ibcon#enter sib2, iclass 32, count 0 2006.285.22:20:02.36#ibcon#flushed, iclass 32, count 0 2006.285.22:20:02.36#ibcon#about to write, iclass 32, count 0 2006.285.22:20:02.36#ibcon#wrote, iclass 32, count 0 2006.285.22:20:02.36#ibcon#about to read 3, iclass 32, count 0 2006.285.22:20:02.40#ibcon#read 3, iclass 32, count 0 2006.285.22:20:02.40#ibcon#about to read 4, iclass 32, count 0 2006.285.22:20:02.40#ibcon#read 4, iclass 32, count 0 2006.285.22:20:02.40#ibcon#about to read 5, iclass 32, count 0 2006.285.22:20:02.40#ibcon#read 5, iclass 32, count 0 2006.285.22:20:02.40#ibcon#about to read 6, iclass 32, count 0 2006.285.22:20:02.40#ibcon#read 6, iclass 32, count 0 2006.285.22:20:02.40#ibcon#end of sib2, iclass 32, count 0 2006.285.22:20:02.40#ibcon#*after write, iclass 32, count 0 2006.285.22:20:02.40#ibcon#*before return 0, iclass 32, count 0 2006.285.22:20:02.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:20:02.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:20:02.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.22:20:02.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.22:20:02.40$vck44/vb=6,3 2006.285.22:20:02.40#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.22:20:02.40#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.22:20:02.40#ibcon#ireg 11 cls_cnt 2 2006.285.22:20:02.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:20:02.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:20:02.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:20:02.46#ibcon#enter wrdev, iclass 34, count 2 2006.285.22:20:02.46#ibcon#first serial, iclass 34, count 2 2006.285.22:20:02.46#ibcon#enter sib2, iclass 34, count 2 2006.285.22:20:02.46#ibcon#flushed, iclass 34, count 2 2006.285.22:20:02.46#ibcon#about to write, iclass 34, count 2 2006.285.22:20:02.46#ibcon#wrote, iclass 34, count 2 2006.285.22:20:02.46#ibcon#about to read 3, iclass 34, count 2 2006.285.22:20:02.48#ibcon#read 3, iclass 34, count 2 2006.285.22:20:02.48#ibcon#about to read 4, iclass 34, count 2 2006.285.22:20:02.48#ibcon#read 4, iclass 34, count 2 2006.285.22:20:02.48#ibcon#about to read 5, iclass 34, count 2 2006.285.22:20:02.48#ibcon#read 5, iclass 34, count 2 2006.285.22:20:02.48#ibcon#about to read 6, iclass 34, count 2 2006.285.22:20:02.48#ibcon#read 6, iclass 34, count 2 2006.285.22:20:02.48#ibcon#end of sib2, iclass 34, count 2 2006.285.22:20:02.48#ibcon#*mode == 0, iclass 34, count 2 2006.285.22:20:02.48#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.22:20:02.48#ibcon#[27=AT06-03\r\n] 2006.285.22:20:02.48#ibcon#*before write, iclass 34, count 2 2006.285.22:20:02.48#ibcon#enter sib2, iclass 34, count 2 2006.285.22:20:02.48#ibcon#flushed, iclass 34, count 2 2006.285.22:20:02.48#ibcon#about to write, iclass 34, count 2 2006.285.22:20:02.48#ibcon#wrote, iclass 34, count 2 2006.285.22:20:02.48#ibcon#about to read 3, iclass 34, count 2 2006.285.22:20:02.51#ibcon#read 3, iclass 34, count 2 2006.285.22:20:02.51#ibcon#about to read 4, iclass 34, count 2 2006.285.22:20:02.51#ibcon#read 4, iclass 34, count 2 2006.285.22:20:02.51#ibcon#about to read 5, iclass 34, count 2 2006.285.22:20:02.51#ibcon#read 5, iclass 34, count 2 2006.285.22:20:02.51#ibcon#about to read 6, iclass 34, count 2 2006.285.22:20:02.51#ibcon#read 6, iclass 34, count 2 2006.285.22:20:02.51#ibcon#end of sib2, iclass 34, count 2 2006.285.22:20:02.51#ibcon#*after write, iclass 34, count 2 2006.285.22:20:02.51#ibcon#*before return 0, iclass 34, count 2 2006.285.22:20:02.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:20:02.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:20:02.51#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.22:20:02.51#ibcon#ireg 7 cls_cnt 0 2006.285.22:20:02.51#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:20:02.63#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:20:02.63#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:20:02.63#ibcon#enter wrdev, iclass 34, count 0 2006.285.22:20:02.63#ibcon#first serial, iclass 34, count 0 2006.285.22:20:02.63#ibcon#enter sib2, iclass 34, count 0 2006.285.22:20:02.63#ibcon#flushed, iclass 34, count 0 2006.285.22:20:02.63#ibcon#about to write, iclass 34, count 0 2006.285.22:20:02.63#ibcon#wrote, iclass 34, count 0 2006.285.22:20:02.63#ibcon#about to read 3, iclass 34, count 0 2006.285.22:20:02.65#ibcon#read 3, iclass 34, count 0 2006.285.22:20:02.65#ibcon#about to read 4, iclass 34, count 0 2006.285.22:20:02.65#ibcon#read 4, iclass 34, count 0 2006.285.22:20:02.65#ibcon#about to read 5, iclass 34, count 0 2006.285.22:20:02.65#ibcon#read 5, iclass 34, count 0 2006.285.22:20:02.65#ibcon#about to read 6, iclass 34, count 0 2006.285.22:20:02.65#ibcon#read 6, iclass 34, count 0 2006.285.22:20:02.65#ibcon#end of sib2, iclass 34, count 0 2006.285.22:20:02.65#ibcon#*mode == 0, iclass 34, count 0 2006.285.22:20:02.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.22:20:02.65#ibcon#[27=USB\r\n] 2006.285.22:20:02.65#ibcon#*before write, iclass 34, count 0 2006.285.22:20:02.65#ibcon#enter sib2, iclass 34, count 0 2006.285.22:20:02.65#ibcon#flushed, iclass 34, count 0 2006.285.22:20:02.65#ibcon#about to write, iclass 34, count 0 2006.285.22:20:02.65#ibcon#wrote, iclass 34, count 0 2006.285.22:20:02.65#ibcon#about to read 3, iclass 34, count 0 2006.285.22:20:02.68#ibcon#read 3, iclass 34, count 0 2006.285.22:20:02.68#ibcon#about to read 4, iclass 34, count 0 2006.285.22:20:02.68#ibcon#read 4, iclass 34, count 0 2006.285.22:20:02.68#ibcon#about to read 5, iclass 34, count 0 2006.285.22:20:02.68#ibcon#read 5, iclass 34, count 0 2006.285.22:20:02.68#ibcon#about to read 6, iclass 34, count 0 2006.285.22:20:02.68#ibcon#read 6, iclass 34, count 0 2006.285.22:20:02.68#ibcon#end of sib2, iclass 34, count 0 2006.285.22:20:02.68#ibcon#*after write, iclass 34, count 0 2006.285.22:20:02.68#ibcon#*before return 0, iclass 34, count 0 2006.285.22:20:02.68#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:20:02.68#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:20:02.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.22:20:02.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.22:20:02.68$vck44/vblo=7,734.99 2006.285.22:20:02.68#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.22:20:02.68#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.22:20:02.68#ibcon#ireg 17 cls_cnt 0 2006.285.22:20:02.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:20:02.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:20:02.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:20:02.68#ibcon#enter wrdev, iclass 36, count 0 2006.285.22:20:02.68#ibcon#first serial, iclass 36, count 0 2006.285.22:20:02.68#ibcon#enter sib2, iclass 36, count 0 2006.285.22:20:02.68#ibcon#flushed, iclass 36, count 0 2006.285.22:20:02.68#ibcon#about to write, iclass 36, count 0 2006.285.22:20:02.68#ibcon#wrote, iclass 36, count 0 2006.285.22:20:02.68#ibcon#about to read 3, iclass 36, count 0 2006.285.22:20:02.70#ibcon#read 3, iclass 36, count 0 2006.285.22:20:02.70#ibcon#about to read 4, iclass 36, count 0 2006.285.22:20:02.70#ibcon#read 4, iclass 36, count 0 2006.285.22:20:02.70#ibcon#about to read 5, iclass 36, count 0 2006.285.22:20:02.70#ibcon#read 5, iclass 36, count 0 2006.285.22:20:02.70#ibcon#about to read 6, iclass 36, count 0 2006.285.22:20:02.70#ibcon#read 6, iclass 36, count 0 2006.285.22:20:02.70#ibcon#end of sib2, iclass 36, count 0 2006.285.22:20:02.70#ibcon#*mode == 0, iclass 36, count 0 2006.285.22:20:02.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.22:20:02.70#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.22:20:02.70#ibcon#*before write, iclass 36, count 0 2006.285.22:20:02.70#ibcon#enter sib2, iclass 36, count 0 2006.285.22:20:02.70#ibcon#flushed, iclass 36, count 0 2006.285.22:20:02.70#ibcon#about to write, iclass 36, count 0 2006.285.22:20:02.70#ibcon#wrote, iclass 36, count 0 2006.285.22:20:02.70#ibcon#about to read 3, iclass 36, count 0 2006.285.22:20:02.74#ibcon#read 3, iclass 36, count 0 2006.285.22:20:02.74#ibcon#about to read 4, iclass 36, count 0 2006.285.22:20:02.74#ibcon#read 4, iclass 36, count 0 2006.285.22:20:02.74#ibcon#about to read 5, iclass 36, count 0 2006.285.22:20:02.74#ibcon#read 5, iclass 36, count 0 2006.285.22:20:02.74#ibcon#about to read 6, iclass 36, count 0 2006.285.22:20:02.74#ibcon#read 6, iclass 36, count 0 2006.285.22:20:02.74#ibcon#end of sib2, iclass 36, count 0 2006.285.22:20:02.74#ibcon#*after write, iclass 36, count 0 2006.285.22:20:02.74#ibcon#*before return 0, iclass 36, count 0 2006.285.22:20:02.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:20:02.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:20:02.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.22:20:02.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.22:20:02.74$vck44/vb=7,4 2006.285.22:20:02.74#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.22:20:02.74#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.22:20:02.74#ibcon#ireg 11 cls_cnt 2 2006.285.22:20:02.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:20:02.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:20:02.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:20:02.80#ibcon#enter wrdev, iclass 38, count 2 2006.285.22:20:02.80#ibcon#first serial, iclass 38, count 2 2006.285.22:20:02.80#ibcon#enter sib2, iclass 38, count 2 2006.285.22:20:02.80#ibcon#flushed, iclass 38, count 2 2006.285.22:20:02.80#ibcon#about to write, iclass 38, count 2 2006.285.22:20:02.80#ibcon#wrote, iclass 38, count 2 2006.285.22:20:02.80#ibcon#about to read 3, iclass 38, count 2 2006.285.22:20:02.82#ibcon#read 3, iclass 38, count 2 2006.285.22:20:02.82#ibcon#about to read 4, iclass 38, count 2 2006.285.22:20:02.82#ibcon#read 4, iclass 38, count 2 2006.285.22:20:02.82#ibcon#about to read 5, iclass 38, count 2 2006.285.22:20:02.82#ibcon#read 5, iclass 38, count 2 2006.285.22:20:02.82#ibcon#about to read 6, iclass 38, count 2 2006.285.22:20:02.82#ibcon#read 6, iclass 38, count 2 2006.285.22:20:02.82#ibcon#end of sib2, iclass 38, count 2 2006.285.22:20:02.82#ibcon#*mode == 0, iclass 38, count 2 2006.285.22:20:02.82#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.22:20:02.82#ibcon#[27=AT07-04\r\n] 2006.285.22:20:02.82#ibcon#*before write, iclass 38, count 2 2006.285.22:20:02.82#ibcon#enter sib2, iclass 38, count 2 2006.285.22:20:02.82#ibcon#flushed, iclass 38, count 2 2006.285.22:20:02.82#ibcon#about to write, iclass 38, count 2 2006.285.22:20:02.82#ibcon#wrote, iclass 38, count 2 2006.285.22:20:02.82#ibcon#about to read 3, iclass 38, count 2 2006.285.22:20:02.85#ibcon#read 3, iclass 38, count 2 2006.285.22:20:02.85#ibcon#about to read 4, iclass 38, count 2 2006.285.22:20:02.85#ibcon#read 4, iclass 38, count 2 2006.285.22:20:02.85#ibcon#about to read 5, iclass 38, count 2 2006.285.22:20:02.85#ibcon#read 5, iclass 38, count 2 2006.285.22:20:02.85#ibcon#about to read 6, iclass 38, count 2 2006.285.22:20:02.85#ibcon#read 6, iclass 38, count 2 2006.285.22:20:02.85#ibcon#end of sib2, iclass 38, count 2 2006.285.22:20:02.85#ibcon#*after write, iclass 38, count 2 2006.285.22:20:02.85#ibcon#*before return 0, iclass 38, count 2 2006.285.22:20:02.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:20:02.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:20:02.85#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.22:20:02.85#ibcon#ireg 7 cls_cnt 0 2006.285.22:20:02.85#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:20:02.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:20:02.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:20:02.97#ibcon#enter wrdev, iclass 38, count 0 2006.285.22:20:02.97#ibcon#first serial, iclass 38, count 0 2006.285.22:20:02.97#ibcon#enter sib2, iclass 38, count 0 2006.285.22:20:02.97#ibcon#flushed, iclass 38, count 0 2006.285.22:20:02.97#ibcon#about to write, iclass 38, count 0 2006.285.22:20:02.97#ibcon#wrote, iclass 38, count 0 2006.285.22:20:02.97#ibcon#about to read 3, iclass 38, count 0 2006.285.22:20:02.99#ibcon#read 3, iclass 38, count 0 2006.285.22:20:02.99#ibcon#about to read 4, iclass 38, count 0 2006.285.22:20:02.99#ibcon#read 4, iclass 38, count 0 2006.285.22:20:02.99#ibcon#about to read 5, iclass 38, count 0 2006.285.22:20:02.99#ibcon#read 5, iclass 38, count 0 2006.285.22:20:02.99#ibcon#about to read 6, iclass 38, count 0 2006.285.22:20:02.99#ibcon#read 6, iclass 38, count 0 2006.285.22:20:02.99#ibcon#end of sib2, iclass 38, count 0 2006.285.22:20:02.99#ibcon#*mode == 0, iclass 38, count 0 2006.285.22:20:02.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.22:20:02.99#ibcon#[27=USB\r\n] 2006.285.22:20:02.99#ibcon#*before write, iclass 38, count 0 2006.285.22:20:02.99#ibcon#enter sib2, iclass 38, count 0 2006.285.22:20:02.99#ibcon#flushed, iclass 38, count 0 2006.285.22:20:02.99#ibcon#about to write, iclass 38, count 0 2006.285.22:20:02.99#ibcon#wrote, iclass 38, count 0 2006.285.22:20:02.99#ibcon#about to read 3, iclass 38, count 0 2006.285.22:20:03.02#ibcon#read 3, iclass 38, count 0 2006.285.22:20:03.02#ibcon#about to read 4, iclass 38, count 0 2006.285.22:20:03.02#ibcon#read 4, iclass 38, count 0 2006.285.22:20:03.02#ibcon#about to read 5, iclass 38, count 0 2006.285.22:20:03.02#ibcon#read 5, iclass 38, count 0 2006.285.22:20:03.02#ibcon#about to read 6, iclass 38, count 0 2006.285.22:20:03.02#ibcon#read 6, iclass 38, count 0 2006.285.22:20:03.02#ibcon#end of sib2, iclass 38, count 0 2006.285.22:20:03.02#ibcon#*after write, iclass 38, count 0 2006.285.22:20:03.02#ibcon#*before return 0, iclass 38, count 0 2006.285.22:20:03.02#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:20:03.02#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:20:03.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.22:20:03.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.22:20:03.02$vck44/vblo=8,744.99 2006.285.22:20:03.02#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.22:20:03.02#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.22:20:03.02#ibcon#ireg 17 cls_cnt 0 2006.285.22:20:03.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:20:03.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:20:03.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:20:03.02#ibcon#enter wrdev, iclass 40, count 0 2006.285.22:20:03.02#ibcon#first serial, iclass 40, count 0 2006.285.22:20:03.02#ibcon#enter sib2, iclass 40, count 0 2006.285.22:20:03.02#ibcon#flushed, iclass 40, count 0 2006.285.22:20:03.02#ibcon#about to write, iclass 40, count 0 2006.285.22:20:03.02#ibcon#wrote, iclass 40, count 0 2006.285.22:20:03.02#ibcon#about to read 3, iclass 40, count 0 2006.285.22:20:03.04#ibcon#read 3, iclass 40, count 0 2006.285.22:20:03.04#ibcon#about to read 4, iclass 40, count 0 2006.285.22:20:03.04#ibcon#read 4, iclass 40, count 0 2006.285.22:20:03.04#ibcon#about to read 5, iclass 40, count 0 2006.285.22:20:03.04#ibcon#read 5, iclass 40, count 0 2006.285.22:20:03.04#ibcon#about to read 6, iclass 40, count 0 2006.285.22:20:03.04#ibcon#read 6, iclass 40, count 0 2006.285.22:20:03.04#ibcon#end of sib2, iclass 40, count 0 2006.285.22:20:03.04#ibcon#*mode == 0, iclass 40, count 0 2006.285.22:20:03.04#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.22:20:03.04#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.22:20:03.04#ibcon#*before write, iclass 40, count 0 2006.285.22:20:03.04#ibcon#enter sib2, iclass 40, count 0 2006.285.22:20:03.04#ibcon#flushed, iclass 40, count 0 2006.285.22:20:03.04#ibcon#about to write, iclass 40, count 0 2006.285.22:20:03.04#ibcon#wrote, iclass 40, count 0 2006.285.22:20:03.04#ibcon#about to read 3, iclass 40, count 0 2006.285.22:20:03.08#ibcon#read 3, iclass 40, count 0 2006.285.22:20:03.08#ibcon#about to read 4, iclass 40, count 0 2006.285.22:20:03.08#ibcon#read 4, iclass 40, count 0 2006.285.22:20:03.08#ibcon#about to read 5, iclass 40, count 0 2006.285.22:20:03.08#ibcon#read 5, iclass 40, count 0 2006.285.22:20:03.08#ibcon#about to read 6, iclass 40, count 0 2006.285.22:20:03.08#ibcon#read 6, iclass 40, count 0 2006.285.22:20:03.08#ibcon#end of sib2, iclass 40, count 0 2006.285.22:20:03.08#ibcon#*after write, iclass 40, count 0 2006.285.22:20:03.08#ibcon#*before return 0, iclass 40, count 0 2006.285.22:20:03.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:20:03.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:20:03.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.22:20:03.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.22:20:03.08$vck44/vb=8,4 2006.285.22:20:03.08#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.22:20:03.08#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.22:20:03.08#ibcon#ireg 11 cls_cnt 2 2006.285.22:20:03.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:20:03.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:20:03.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:20:03.14#ibcon#enter wrdev, iclass 4, count 2 2006.285.22:20:03.14#ibcon#first serial, iclass 4, count 2 2006.285.22:20:03.14#ibcon#enter sib2, iclass 4, count 2 2006.285.22:20:03.14#ibcon#flushed, iclass 4, count 2 2006.285.22:20:03.14#ibcon#about to write, iclass 4, count 2 2006.285.22:20:03.14#ibcon#wrote, iclass 4, count 2 2006.285.22:20:03.14#ibcon#about to read 3, iclass 4, count 2 2006.285.22:20:03.16#ibcon#read 3, iclass 4, count 2 2006.285.22:20:03.16#ibcon#about to read 4, iclass 4, count 2 2006.285.22:20:03.16#ibcon#read 4, iclass 4, count 2 2006.285.22:20:03.16#ibcon#about to read 5, iclass 4, count 2 2006.285.22:20:03.16#ibcon#read 5, iclass 4, count 2 2006.285.22:20:03.16#ibcon#about to read 6, iclass 4, count 2 2006.285.22:20:03.16#ibcon#read 6, iclass 4, count 2 2006.285.22:20:03.16#ibcon#end of sib2, iclass 4, count 2 2006.285.22:20:03.16#ibcon#*mode == 0, iclass 4, count 2 2006.285.22:20:03.16#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.22:20:03.16#ibcon#[27=AT08-04\r\n] 2006.285.22:20:03.16#ibcon#*before write, iclass 4, count 2 2006.285.22:20:03.16#ibcon#enter sib2, iclass 4, count 2 2006.285.22:20:03.16#ibcon#flushed, iclass 4, count 2 2006.285.22:20:03.16#ibcon#about to write, iclass 4, count 2 2006.285.22:20:03.16#ibcon#wrote, iclass 4, count 2 2006.285.22:20:03.16#ibcon#about to read 3, iclass 4, count 2 2006.285.22:20:03.19#ibcon#read 3, iclass 4, count 2 2006.285.22:20:03.19#ibcon#about to read 4, iclass 4, count 2 2006.285.22:20:03.19#ibcon#read 4, iclass 4, count 2 2006.285.22:20:03.19#ibcon#about to read 5, iclass 4, count 2 2006.285.22:20:03.19#ibcon#read 5, iclass 4, count 2 2006.285.22:20:03.19#ibcon#about to read 6, iclass 4, count 2 2006.285.22:20:03.19#ibcon#read 6, iclass 4, count 2 2006.285.22:20:03.19#ibcon#end of sib2, iclass 4, count 2 2006.285.22:20:03.19#ibcon#*after write, iclass 4, count 2 2006.285.22:20:03.19#ibcon#*before return 0, iclass 4, count 2 2006.285.22:20:03.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:20:03.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:20:03.19#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.22:20:03.19#ibcon#ireg 7 cls_cnt 0 2006.285.22:20:03.19#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:20:03.31#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:20:03.31#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:20:03.31#ibcon#enter wrdev, iclass 4, count 0 2006.285.22:20:03.31#ibcon#first serial, iclass 4, count 0 2006.285.22:20:03.31#ibcon#enter sib2, iclass 4, count 0 2006.285.22:20:03.31#ibcon#flushed, iclass 4, count 0 2006.285.22:20:03.31#ibcon#about to write, iclass 4, count 0 2006.285.22:20:03.31#ibcon#wrote, iclass 4, count 0 2006.285.22:20:03.31#ibcon#about to read 3, iclass 4, count 0 2006.285.22:20:03.33#ibcon#read 3, iclass 4, count 0 2006.285.22:20:03.33#ibcon#about to read 4, iclass 4, count 0 2006.285.22:20:03.33#ibcon#read 4, iclass 4, count 0 2006.285.22:20:03.33#ibcon#about to read 5, iclass 4, count 0 2006.285.22:20:03.33#ibcon#read 5, iclass 4, count 0 2006.285.22:20:03.33#ibcon#about to read 6, iclass 4, count 0 2006.285.22:20:03.33#ibcon#read 6, iclass 4, count 0 2006.285.22:20:03.33#ibcon#end of sib2, iclass 4, count 0 2006.285.22:20:03.33#ibcon#*mode == 0, iclass 4, count 0 2006.285.22:20:03.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.22:20:03.33#ibcon#[27=USB\r\n] 2006.285.22:20:03.33#ibcon#*before write, iclass 4, count 0 2006.285.22:20:03.33#ibcon#enter sib2, iclass 4, count 0 2006.285.22:20:03.33#ibcon#flushed, iclass 4, count 0 2006.285.22:20:03.33#ibcon#about to write, iclass 4, count 0 2006.285.22:20:03.33#ibcon#wrote, iclass 4, count 0 2006.285.22:20:03.33#ibcon#about to read 3, iclass 4, count 0 2006.285.22:20:03.36#ibcon#read 3, iclass 4, count 0 2006.285.22:20:03.36#ibcon#about to read 4, iclass 4, count 0 2006.285.22:20:03.36#ibcon#read 4, iclass 4, count 0 2006.285.22:20:03.36#ibcon#about to read 5, iclass 4, count 0 2006.285.22:20:03.36#ibcon#read 5, iclass 4, count 0 2006.285.22:20:03.36#ibcon#about to read 6, iclass 4, count 0 2006.285.22:20:03.36#ibcon#read 6, iclass 4, count 0 2006.285.22:20:03.36#ibcon#end of sib2, iclass 4, count 0 2006.285.22:20:03.36#ibcon#*after write, iclass 4, count 0 2006.285.22:20:03.36#ibcon#*before return 0, iclass 4, count 0 2006.285.22:20:03.36#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:20:03.36#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:20:03.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.22:20:03.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.22:20:03.36$vck44/vabw=wide 2006.285.22:20:03.36#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.22:20:03.36#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.22:20:03.36#ibcon#ireg 8 cls_cnt 0 2006.285.22:20:03.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:20:03.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:20:03.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:20:03.36#ibcon#enter wrdev, iclass 6, count 0 2006.285.22:20:03.36#ibcon#first serial, iclass 6, count 0 2006.285.22:20:03.36#ibcon#enter sib2, iclass 6, count 0 2006.285.22:20:03.36#ibcon#flushed, iclass 6, count 0 2006.285.22:20:03.36#ibcon#about to write, iclass 6, count 0 2006.285.22:20:03.36#ibcon#wrote, iclass 6, count 0 2006.285.22:20:03.36#ibcon#about to read 3, iclass 6, count 0 2006.285.22:20:03.38#ibcon#read 3, iclass 6, count 0 2006.285.22:20:03.38#ibcon#about to read 4, iclass 6, count 0 2006.285.22:20:03.38#ibcon#read 4, iclass 6, count 0 2006.285.22:20:03.38#ibcon#about to read 5, iclass 6, count 0 2006.285.22:20:03.38#ibcon#read 5, iclass 6, count 0 2006.285.22:20:03.38#ibcon#about to read 6, iclass 6, count 0 2006.285.22:20:03.38#ibcon#read 6, iclass 6, count 0 2006.285.22:20:03.38#ibcon#end of sib2, iclass 6, count 0 2006.285.22:20:03.38#ibcon#*mode == 0, iclass 6, count 0 2006.285.22:20:03.38#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.22:20:03.38#ibcon#[25=BW32\r\n] 2006.285.22:20:03.38#ibcon#*before write, iclass 6, count 0 2006.285.22:20:03.38#ibcon#enter sib2, iclass 6, count 0 2006.285.22:20:03.38#ibcon#flushed, iclass 6, count 0 2006.285.22:20:03.38#ibcon#about to write, iclass 6, count 0 2006.285.22:20:03.38#ibcon#wrote, iclass 6, count 0 2006.285.22:20:03.38#ibcon#about to read 3, iclass 6, count 0 2006.285.22:20:03.41#ibcon#read 3, iclass 6, count 0 2006.285.22:20:03.41#ibcon#about to read 4, iclass 6, count 0 2006.285.22:20:03.41#ibcon#read 4, iclass 6, count 0 2006.285.22:20:03.41#ibcon#about to read 5, iclass 6, count 0 2006.285.22:20:03.41#ibcon#read 5, iclass 6, count 0 2006.285.22:20:03.41#ibcon#about to read 6, iclass 6, count 0 2006.285.22:20:03.41#ibcon#read 6, iclass 6, count 0 2006.285.22:20:03.41#ibcon#end of sib2, iclass 6, count 0 2006.285.22:20:03.41#ibcon#*after write, iclass 6, count 0 2006.285.22:20:03.41#ibcon#*before return 0, iclass 6, count 0 2006.285.22:20:03.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:20:03.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:20:03.41#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.22:20:03.41#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.22:20:03.41$vck44/vbbw=wide 2006.285.22:20:03.41#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.22:20:03.41#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.22:20:03.41#ibcon#ireg 8 cls_cnt 0 2006.285.22:20:03.41#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:20:03.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:20:03.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:20:03.48#ibcon#enter wrdev, iclass 10, count 0 2006.285.22:20:03.48#ibcon#first serial, iclass 10, count 0 2006.285.22:20:03.48#ibcon#enter sib2, iclass 10, count 0 2006.285.22:20:03.48#ibcon#flushed, iclass 10, count 0 2006.285.22:20:03.48#ibcon#about to write, iclass 10, count 0 2006.285.22:20:03.48#ibcon#wrote, iclass 10, count 0 2006.285.22:20:03.48#ibcon#about to read 3, iclass 10, count 0 2006.285.22:20:03.50#ibcon#read 3, iclass 10, count 0 2006.285.22:20:03.50#ibcon#about to read 4, iclass 10, count 0 2006.285.22:20:03.50#ibcon#read 4, iclass 10, count 0 2006.285.22:20:03.50#ibcon#about to read 5, iclass 10, count 0 2006.285.22:20:03.50#ibcon#read 5, iclass 10, count 0 2006.285.22:20:03.50#ibcon#about to read 6, iclass 10, count 0 2006.285.22:20:03.50#ibcon#read 6, iclass 10, count 0 2006.285.22:20:03.50#ibcon#end of sib2, iclass 10, count 0 2006.285.22:20:03.50#ibcon#*mode == 0, iclass 10, count 0 2006.285.22:20:03.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.22:20:03.50#ibcon#[27=BW32\r\n] 2006.285.22:20:03.50#ibcon#*before write, iclass 10, count 0 2006.285.22:20:03.50#ibcon#enter sib2, iclass 10, count 0 2006.285.22:20:03.50#ibcon#flushed, iclass 10, count 0 2006.285.22:20:03.50#ibcon#about to write, iclass 10, count 0 2006.285.22:20:03.50#ibcon#wrote, iclass 10, count 0 2006.285.22:20:03.50#ibcon#about to read 3, iclass 10, count 0 2006.285.22:20:03.53#ibcon#read 3, iclass 10, count 0 2006.285.22:20:03.53#ibcon#about to read 4, iclass 10, count 0 2006.285.22:20:03.53#ibcon#read 4, iclass 10, count 0 2006.285.22:20:03.53#ibcon#about to read 5, iclass 10, count 0 2006.285.22:20:03.53#ibcon#read 5, iclass 10, count 0 2006.285.22:20:03.53#ibcon#about to read 6, iclass 10, count 0 2006.285.22:20:03.53#ibcon#read 6, iclass 10, count 0 2006.285.22:20:03.53#ibcon#end of sib2, iclass 10, count 0 2006.285.22:20:03.53#ibcon#*after write, iclass 10, count 0 2006.285.22:20:03.53#ibcon#*before return 0, iclass 10, count 0 2006.285.22:20:03.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:20:03.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:20:03.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.22:20:03.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.22:20:03.53$setupk4/ifdk4 2006.285.22:20:03.53$ifdk4/lo= 2006.285.22:20:03.53$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.22:20:03.53$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.22:20:03.53$ifdk4/patch= 2006.285.22:20:03.53$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.22:20:03.53$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.22:20:03.53$setupk4/!*+20s 2006.285.22:20:04.30#abcon#<5=/00 0.2 0.8 16.381001016.0\r\n> 2006.285.22:20:04.32#abcon#{5=INTERFACE CLEAR} 2006.285.22:20:04.38#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:20:14.47#abcon#<5=/14 0.3 0.8 16.391001016.0\r\n> 2006.285.22:20:14.49#abcon#{5=INTERFACE CLEAR} 2006.285.22:20:14.55#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:20:18.03$setupk4/"tpicd 2006.285.22:20:18.03$setupk4/echo=off 2006.285.22:20:18.03$setupk4/xlog=off 2006.285.22:20:18.03:!2006.285.22:22:06 2006.285.22:20:38.14#trakl#Source acquired 2006.285.22:20:38.14#flagr#flagr/antenna,acquired 2006.285.22:22:06.00:preob 2006.285.22:22:06.14/onsource/TRACKING 2006.285.22:22:06.14:!2006.285.22:22:16 2006.285.22:22:16.00:"tape 2006.285.22:22:16.00:"st=record 2006.285.22:22:16.00:data_valid=on 2006.285.22:22:16.00:midob 2006.285.22:22:17.14/onsource/TRACKING 2006.285.22:22:17.14/wx/16.53,1016.0,100 2006.285.22:22:17.27/cable/+6.5105E-03 2006.285.22:22:18.36/va/01,07,usb,yes,35,38 2006.285.22:22:18.36/va/02,06,usb,yes,35,36 2006.285.22:22:18.36/va/03,07,usb,yes,35,37 2006.285.22:22:18.36/va/04,06,usb,yes,36,38 2006.285.22:22:18.36/va/05,03,usb,yes,36,36 2006.285.22:22:18.36/va/06,04,usb,yes,32,32 2006.285.22:22:18.36/va/07,04,usb,yes,33,34 2006.285.22:22:18.36/va/08,03,usb,yes,34,41 2006.285.22:22:18.59/valo/01,524.99,yes,locked 2006.285.22:22:18.59/valo/02,534.99,yes,locked 2006.285.22:22:18.59/valo/03,564.99,yes,locked 2006.285.22:22:18.59/valo/04,624.99,yes,locked 2006.285.22:22:18.59/valo/05,734.99,yes,locked 2006.285.22:22:18.59/valo/06,814.99,yes,locked 2006.285.22:22:18.59/valo/07,864.99,yes,locked 2006.285.22:22:18.59/valo/08,884.99,yes,locked 2006.285.22:22:19.68/vb/01,04,usb,yes,32,30 2006.285.22:22:19.68/vb/02,05,usb,yes,30,30 2006.285.22:22:19.68/vb/03,04,usb,yes,32,34 2006.285.22:22:19.68/vb/04,05,usb,yes,32,30 2006.285.22:22:19.68/vb/05,04,usb,yes,28,30 2006.285.22:22:19.68/vb/06,03,usb,yes,40,35 2006.285.22:22:19.68/vb/07,04,usb,yes,32,32 2006.285.22:22:19.68/vb/08,04,usb,yes,29,33 2006.285.22:22:19.91/vblo/01,629.99,yes,locked 2006.285.22:22:19.91/vblo/02,634.99,yes,locked 2006.285.22:22:19.91/vblo/03,649.99,yes,locked 2006.285.22:22:19.91/vblo/04,679.99,yes,locked 2006.285.22:22:19.91/vblo/05,709.99,yes,locked 2006.285.22:22:19.91/vblo/06,719.99,yes,locked 2006.285.22:22:19.91/vblo/07,734.99,yes,locked 2006.285.22:22:19.91/vblo/08,744.99,yes,locked 2006.285.22:22:20.06/vabw/8 2006.285.22:22:20.21/vbbw/8 2006.285.22:22:20.30/xfe/off,on,11.7 2006.285.22:22:20.69/ifatt/23,28,28,28 2006.285.22:22:21.08/fmout-gps/S +2.64E-07 2006.285.22:22:21.10:!2006.285.22:24:36 2006.285.22:24:36.00:data_valid=off 2006.285.22:24:36.00:"et 2006.285.22:24:36.00:!+3s 2006.285.22:24:39.01:"tape 2006.285.22:24:39.01:postob 2006.285.22:24:39.16/cable/+6.5096E-03 2006.285.22:24:39.16/wx/16.63,1016.1,99 2006.285.22:24:40.08/fmout-gps/S +2.64E-07 2006.285.22:24:40.08:scan_name=285-2226,jd0610,110 2006.285.22:24:40.08:source=1611+343,161341.06,341247.9,2000.0,cw 2006.285.22:24:41.13#flagr#flagr/antenna,new-source 2006.285.22:24:41.13:checkk5 2006.285.22:24:41.77/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:24:42.26/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:24:42.87/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:24:43.31/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:24:43.69/chk_obsdata//k5ts1/T2852222??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.285.22:24:44.37/chk_obsdata//k5ts2/T2852222??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.285.22:24:44.80/chk_obsdata//k5ts3/T2852222??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.285.22:24:45.36/chk_obsdata//k5ts4/T2852222??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.285.22:24:46.10/k5log//k5ts1_log_newline 2006.285.22:24:46.90/k5log//k5ts2_log_newline 2006.285.22:24:47.64/k5log//k5ts3_log_newline 2006.285.22:24:48.60/k5log//k5ts4_log_newline 2006.285.22:24:48.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:24:48.62:setupk4=1 2006.285.22:24:48.62$setupk4/echo=on 2006.285.22:24:48.62$setupk4/pcalon 2006.285.22:24:48.62$pcalon/"no phase cal control is implemented here 2006.285.22:24:48.62$setupk4/"tpicd=stop 2006.285.22:24:48.62$setupk4/"rec=synch_on 2006.285.22:24:48.62$setupk4/"rec_mode=128 2006.285.22:24:48.62$setupk4/!* 2006.285.22:24:48.62$setupk4/recpk4 2006.285.22:24:48.62$recpk4/recpatch= 2006.285.22:24:48.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:24:48.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:24:48.62$setupk4/vck44 2006.285.22:24:48.62$vck44/valo=1,524.99 2006.285.22:24:48.62#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.22:24:48.62#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.22:24:48.62#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:48.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:24:48.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:24:48.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:24:48.62#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:24:48.62#ibcon#first serial, iclass 19, count 0 2006.285.22:24:48.62#ibcon#enter sib2, iclass 19, count 0 2006.285.22:24:48.62#ibcon#flushed, iclass 19, count 0 2006.285.22:24:48.62#ibcon#about to write, iclass 19, count 0 2006.285.22:24:48.62#ibcon#wrote, iclass 19, count 0 2006.285.22:24:48.62#ibcon#about to read 3, iclass 19, count 0 2006.285.22:24:48.64#ibcon#read 3, iclass 19, count 0 2006.285.22:24:48.64#ibcon#about to read 4, iclass 19, count 0 2006.285.22:24:48.64#ibcon#read 4, iclass 19, count 0 2006.285.22:24:48.64#ibcon#about to read 5, iclass 19, count 0 2006.285.22:24:48.64#ibcon#read 5, iclass 19, count 0 2006.285.22:24:48.64#ibcon#about to read 6, iclass 19, count 0 2006.285.22:24:48.64#ibcon#read 6, iclass 19, count 0 2006.285.22:24:48.64#ibcon#end of sib2, iclass 19, count 0 2006.285.22:24:48.64#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:24:48.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:24:48.64#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:24:48.64#ibcon#*before write, iclass 19, count 0 2006.285.22:24:48.64#ibcon#enter sib2, iclass 19, count 0 2006.285.22:24:48.64#ibcon#flushed, iclass 19, count 0 2006.285.22:24:48.64#ibcon#about to write, iclass 19, count 0 2006.285.22:24:48.64#ibcon#wrote, iclass 19, count 0 2006.285.22:24:48.64#ibcon#about to read 3, iclass 19, count 0 2006.285.22:24:48.69#ibcon#read 3, iclass 19, count 0 2006.285.22:24:48.69#ibcon#about to read 4, iclass 19, count 0 2006.285.22:24:48.69#ibcon#read 4, iclass 19, count 0 2006.285.22:24:48.69#ibcon#about to read 5, iclass 19, count 0 2006.285.22:24:48.69#ibcon#read 5, iclass 19, count 0 2006.285.22:24:48.69#ibcon#about to read 6, iclass 19, count 0 2006.285.22:24:48.69#ibcon#read 6, iclass 19, count 0 2006.285.22:24:48.69#ibcon#end of sib2, iclass 19, count 0 2006.285.22:24:48.69#ibcon#*after write, iclass 19, count 0 2006.285.22:24:48.69#ibcon#*before return 0, iclass 19, count 0 2006.285.22:24:48.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:24:48.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:24:48.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:24:48.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:24:48.69$vck44/va=1,7 2006.285.22:24:48.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.22:24:48.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.22:24:48.69#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:48.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:24:48.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:24:48.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:24:48.69#ibcon#enter wrdev, iclass 21, count 2 2006.285.22:24:48.69#ibcon#first serial, iclass 21, count 2 2006.285.22:24:48.69#ibcon#enter sib2, iclass 21, count 2 2006.285.22:24:48.69#ibcon#flushed, iclass 21, count 2 2006.285.22:24:48.69#ibcon#about to write, iclass 21, count 2 2006.285.22:24:48.69#ibcon#wrote, iclass 21, count 2 2006.285.22:24:48.69#ibcon#about to read 3, iclass 21, count 2 2006.285.22:24:48.71#ibcon#read 3, iclass 21, count 2 2006.285.22:24:48.71#ibcon#about to read 4, iclass 21, count 2 2006.285.22:24:48.71#ibcon#read 4, iclass 21, count 2 2006.285.22:24:48.71#ibcon#about to read 5, iclass 21, count 2 2006.285.22:24:48.71#ibcon#read 5, iclass 21, count 2 2006.285.22:24:48.71#ibcon#about to read 6, iclass 21, count 2 2006.285.22:24:48.71#ibcon#read 6, iclass 21, count 2 2006.285.22:24:48.71#ibcon#end of sib2, iclass 21, count 2 2006.285.22:24:48.71#ibcon#*mode == 0, iclass 21, count 2 2006.285.22:24:48.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.22:24:48.71#ibcon#[25=AT01-07\r\n] 2006.285.22:24:48.71#ibcon#*before write, iclass 21, count 2 2006.285.22:24:48.71#ibcon#enter sib2, iclass 21, count 2 2006.285.22:24:48.71#ibcon#flushed, iclass 21, count 2 2006.285.22:24:48.71#ibcon#about to write, iclass 21, count 2 2006.285.22:24:48.71#ibcon#wrote, iclass 21, count 2 2006.285.22:24:48.71#ibcon#about to read 3, iclass 21, count 2 2006.285.22:24:48.74#ibcon#read 3, iclass 21, count 2 2006.285.22:24:48.74#ibcon#about to read 4, iclass 21, count 2 2006.285.22:24:48.74#ibcon#read 4, iclass 21, count 2 2006.285.22:24:48.74#ibcon#about to read 5, iclass 21, count 2 2006.285.22:24:48.74#ibcon#read 5, iclass 21, count 2 2006.285.22:24:48.74#ibcon#about to read 6, iclass 21, count 2 2006.285.22:24:48.74#ibcon#read 6, iclass 21, count 2 2006.285.22:24:48.74#ibcon#end of sib2, iclass 21, count 2 2006.285.22:24:48.74#ibcon#*after write, iclass 21, count 2 2006.285.22:24:48.74#ibcon#*before return 0, iclass 21, count 2 2006.285.22:24:48.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:24:48.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:24:48.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.22:24:48.74#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:48.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:24:48.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:24:48.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:24:48.86#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:24:48.86#ibcon#first serial, iclass 21, count 0 2006.285.22:24:48.86#ibcon#enter sib2, iclass 21, count 0 2006.285.22:24:48.86#ibcon#flushed, iclass 21, count 0 2006.285.22:24:48.86#ibcon#about to write, iclass 21, count 0 2006.285.22:24:48.86#ibcon#wrote, iclass 21, count 0 2006.285.22:24:48.86#ibcon#about to read 3, iclass 21, count 0 2006.285.22:24:48.88#ibcon#read 3, iclass 21, count 0 2006.285.22:24:48.88#ibcon#about to read 4, iclass 21, count 0 2006.285.22:24:48.88#ibcon#read 4, iclass 21, count 0 2006.285.22:24:48.88#ibcon#about to read 5, iclass 21, count 0 2006.285.22:24:48.88#ibcon#read 5, iclass 21, count 0 2006.285.22:24:48.88#ibcon#about to read 6, iclass 21, count 0 2006.285.22:24:48.88#ibcon#read 6, iclass 21, count 0 2006.285.22:24:48.88#ibcon#end of sib2, iclass 21, count 0 2006.285.22:24:48.88#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:24:48.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:24:48.88#ibcon#[25=USB\r\n] 2006.285.22:24:48.88#ibcon#*before write, iclass 21, count 0 2006.285.22:24:48.88#ibcon#enter sib2, iclass 21, count 0 2006.285.22:24:48.88#ibcon#flushed, iclass 21, count 0 2006.285.22:24:48.88#ibcon#about to write, iclass 21, count 0 2006.285.22:24:48.88#ibcon#wrote, iclass 21, count 0 2006.285.22:24:48.88#ibcon#about to read 3, iclass 21, count 0 2006.285.22:24:48.91#ibcon#read 3, iclass 21, count 0 2006.285.22:24:48.91#ibcon#about to read 4, iclass 21, count 0 2006.285.22:24:48.91#ibcon#read 4, iclass 21, count 0 2006.285.22:24:48.91#ibcon#about to read 5, iclass 21, count 0 2006.285.22:24:48.91#ibcon#read 5, iclass 21, count 0 2006.285.22:24:48.91#ibcon#about to read 6, iclass 21, count 0 2006.285.22:24:48.91#ibcon#read 6, iclass 21, count 0 2006.285.22:24:48.91#ibcon#end of sib2, iclass 21, count 0 2006.285.22:24:48.91#ibcon#*after write, iclass 21, count 0 2006.285.22:24:48.91#ibcon#*before return 0, iclass 21, count 0 2006.285.22:24:48.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:24:48.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:24:48.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:24:48.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:24:48.91$vck44/valo=2,534.99 2006.285.22:24:48.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.22:24:48.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.22:24:48.91#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:48.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:24:48.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:24:48.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:24:48.91#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:24:48.91#ibcon#first serial, iclass 23, count 0 2006.285.22:24:48.91#ibcon#enter sib2, iclass 23, count 0 2006.285.22:24:48.91#ibcon#flushed, iclass 23, count 0 2006.285.22:24:48.91#ibcon#about to write, iclass 23, count 0 2006.285.22:24:48.91#ibcon#wrote, iclass 23, count 0 2006.285.22:24:48.91#ibcon#about to read 3, iclass 23, count 0 2006.285.22:24:48.93#ibcon#read 3, iclass 23, count 0 2006.285.22:24:48.93#ibcon#about to read 4, iclass 23, count 0 2006.285.22:24:48.93#ibcon#read 4, iclass 23, count 0 2006.285.22:24:48.93#ibcon#about to read 5, iclass 23, count 0 2006.285.22:24:48.93#ibcon#read 5, iclass 23, count 0 2006.285.22:24:48.93#ibcon#about to read 6, iclass 23, count 0 2006.285.22:24:48.93#ibcon#read 6, iclass 23, count 0 2006.285.22:24:48.93#ibcon#end of sib2, iclass 23, count 0 2006.285.22:24:48.93#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:24:48.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:24:48.93#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:24:48.93#ibcon#*before write, iclass 23, count 0 2006.285.22:24:48.93#ibcon#enter sib2, iclass 23, count 0 2006.285.22:24:48.93#ibcon#flushed, iclass 23, count 0 2006.285.22:24:48.93#ibcon#about to write, iclass 23, count 0 2006.285.22:24:48.93#ibcon#wrote, iclass 23, count 0 2006.285.22:24:48.93#ibcon#about to read 3, iclass 23, count 0 2006.285.22:24:48.97#ibcon#read 3, iclass 23, count 0 2006.285.22:24:48.97#ibcon#about to read 4, iclass 23, count 0 2006.285.22:24:48.97#ibcon#read 4, iclass 23, count 0 2006.285.22:24:48.97#ibcon#about to read 5, iclass 23, count 0 2006.285.22:24:48.97#ibcon#read 5, iclass 23, count 0 2006.285.22:24:48.97#ibcon#about to read 6, iclass 23, count 0 2006.285.22:24:48.97#ibcon#read 6, iclass 23, count 0 2006.285.22:24:48.97#ibcon#end of sib2, iclass 23, count 0 2006.285.22:24:48.97#ibcon#*after write, iclass 23, count 0 2006.285.22:24:48.97#ibcon#*before return 0, iclass 23, count 0 2006.285.22:24:48.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:24:48.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:24:48.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:24:48.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:24:48.97$vck44/va=2,6 2006.285.22:24:48.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.22:24:48.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.22:24:48.97#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:48.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:24:49.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:24:49.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:24:49.03#ibcon#enter wrdev, iclass 25, count 2 2006.285.22:24:49.03#ibcon#first serial, iclass 25, count 2 2006.285.22:24:49.03#ibcon#enter sib2, iclass 25, count 2 2006.285.22:24:49.03#ibcon#flushed, iclass 25, count 2 2006.285.22:24:49.03#ibcon#about to write, iclass 25, count 2 2006.285.22:24:49.03#ibcon#wrote, iclass 25, count 2 2006.285.22:24:49.03#ibcon#about to read 3, iclass 25, count 2 2006.285.22:24:49.05#ibcon#read 3, iclass 25, count 2 2006.285.22:24:49.05#ibcon#about to read 4, iclass 25, count 2 2006.285.22:24:49.05#ibcon#read 4, iclass 25, count 2 2006.285.22:24:49.05#ibcon#about to read 5, iclass 25, count 2 2006.285.22:24:49.05#ibcon#read 5, iclass 25, count 2 2006.285.22:24:49.05#ibcon#about to read 6, iclass 25, count 2 2006.285.22:24:49.05#ibcon#read 6, iclass 25, count 2 2006.285.22:24:49.05#ibcon#end of sib2, iclass 25, count 2 2006.285.22:24:49.05#ibcon#*mode == 0, iclass 25, count 2 2006.285.22:24:49.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.22:24:49.05#ibcon#[25=AT02-06\r\n] 2006.285.22:24:49.05#ibcon#*before write, iclass 25, count 2 2006.285.22:24:49.05#ibcon#enter sib2, iclass 25, count 2 2006.285.22:24:49.05#ibcon#flushed, iclass 25, count 2 2006.285.22:24:49.05#ibcon#about to write, iclass 25, count 2 2006.285.22:24:49.05#ibcon#wrote, iclass 25, count 2 2006.285.22:24:49.05#ibcon#about to read 3, iclass 25, count 2 2006.285.22:24:49.08#ibcon#read 3, iclass 25, count 2 2006.285.22:24:49.08#ibcon#about to read 4, iclass 25, count 2 2006.285.22:24:49.08#ibcon#read 4, iclass 25, count 2 2006.285.22:24:49.08#ibcon#about to read 5, iclass 25, count 2 2006.285.22:24:49.08#ibcon#read 5, iclass 25, count 2 2006.285.22:24:49.08#ibcon#about to read 6, iclass 25, count 2 2006.285.22:24:49.08#ibcon#read 6, iclass 25, count 2 2006.285.22:24:49.08#ibcon#end of sib2, iclass 25, count 2 2006.285.22:24:49.08#ibcon#*after write, iclass 25, count 2 2006.285.22:24:49.08#ibcon#*before return 0, iclass 25, count 2 2006.285.22:24:49.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:24:49.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:24:49.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.22:24:49.08#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:49.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:24:49.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:24:49.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:24:49.20#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:24:49.20#ibcon#first serial, iclass 25, count 0 2006.285.22:24:49.20#ibcon#enter sib2, iclass 25, count 0 2006.285.22:24:49.20#ibcon#flushed, iclass 25, count 0 2006.285.22:24:49.20#ibcon#about to write, iclass 25, count 0 2006.285.22:24:49.20#ibcon#wrote, iclass 25, count 0 2006.285.22:24:49.20#ibcon#about to read 3, iclass 25, count 0 2006.285.22:24:49.22#ibcon#read 3, iclass 25, count 0 2006.285.22:24:49.22#ibcon#about to read 4, iclass 25, count 0 2006.285.22:24:49.22#ibcon#read 4, iclass 25, count 0 2006.285.22:24:49.22#ibcon#about to read 5, iclass 25, count 0 2006.285.22:24:49.22#ibcon#read 5, iclass 25, count 0 2006.285.22:24:49.22#ibcon#about to read 6, iclass 25, count 0 2006.285.22:24:49.22#ibcon#read 6, iclass 25, count 0 2006.285.22:24:49.22#ibcon#end of sib2, iclass 25, count 0 2006.285.22:24:49.22#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:24:49.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:24:49.22#ibcon#[25=USB\r\n] 2006.285.22:24:49.22#ibcon#*before write, iclass 25, count 0 2006.285.22:24:49.22#ibcon#enter sib2, iclass 25, count 0 2006.285.22:24:49.22#ibcon#flushed, iclass 25, count 0 2006.285.22:24:49.22#ibcon#about to write, iclass 25, count 0 2006.285.22:24:49.22#ibcon#wrote, iclass 25, count 0 2006.285.22:24:49.22#ibcon#about to read 3, iclass 25, count 0 2006.285.22:24:49.25#ibcon#read 3, iclass 25, count 0 2006.285.22:24:49.25#ibcon#about to read 4, iclass 25, count 0 2006.285.22:24:49.25#ibcon#read 4, iclass 25, count 0 2006.285.22:24:49.25#ibcon#about to read 5, iclass 25, count 0 2006.285.22:24:49.25#ibcon#read 5, iclass 25, count 0 2006.285.22:24:49.25#ibcon#about to read 6, iclass 25, count 0 2006.285.22:24:49.25#ibcon#read 6, iclass 25, count 0 2006.285.22:24:49.25#ibcon#end of sib2, iclass 25, count 0 2006.285.22:24:49.25#ibcon#*after write, iclass 25, count 0 2006.285.22:24:49.25#ibcon#*before return 0, iclass 25, count 0 2006.285.22:24:49.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:24:49.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:24:49.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:24:49.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:24:49.25$vck44/valo=3,564.99 2006.285.22:24:49.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.22:24:49.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.22:24:49.25#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:49.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:24:49.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:24:49.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:24:49.25#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:24:49.25#ibcon#first serial, iclass 27, count 0 2006.285.22:24:49.25#ibcon#enter sib2, iclass 27, count 0 2006.285.22:24:49.25#ibcon#flushed, iclass 27, count 0 2006.285.22:24:49.25#ibcon#about to write, iclass 27, count 0 2006.285.22:24:49.25#ibcon#wrote, iclass 27, count 0 2006.285.22:24:49.25#ibcon#about to read 3, iclass 27, count 0 2006.285.22:24:49.27#ibcon#read 3, iclass 27, count 0 2006.285.22:24:49.27#ibcon#about to read 4, iclass 27, count 0 2006.285.22:24:49.27#ibcon#read 4, iclass 27, count 0 2006.285.22:24:49.27#ibcon#about to read 5, iclass 27, count 0 2006.285.22:24:49.27#ibcon#read 5, iclass 27, count 0 2006.285.22:24:49.27#ibcon#about to read 6, iclass 27, count 0 2006.285.22:24:49.27#ibcon#read 6, iclass 27, count 0 2006.285.22:24:49.27#ibcon#end of sib2, iclass 27, count 0 2006.285.22:24:49.27#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:24:49.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:24:49.27#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:24:49.27#ibcon#*before write, iclass 27, count 0 2006.285.22:24:49.27#ibcon#enter sib2, iclass 27, count 0 2006.285.22:24:49.27#ibcon#flushed, iclass 27, count 0 2006.285.22:24:49.27#ibcon#about to write, iclass 27, count 0 2006.285.22:24:49.27#ibcon#wrote, iclass 27, count 0 2006.285.22:24:49.27#ibcon#about to read 3, iclass 27, count 0 2006.285.22:24:49.31#ibcon#read 3, iclass 27, count 0 2006.285.22:24:49.31#ibcon#about to read 4, iclass 27, count 0 2006.285.22:24:49.31#ibcon#read 4, iclass 27, count 0 2006.285.22:24:49.31#ibcon#about to read 5, iclass 27, count 0 2006.285.22:24:49.31#ibcon#read 5, iclass 27, count 0 2006.285.22:24:49.31#ibcon#about to read 6, iclass 27, count 0 2006.285.22:24:49.31#ibcon#read 6, iclass 27, count 0 2006.285.22:24:49.31#ibcon#end of sib2, iclass 27, count 0 2006.285.22:24:49.31#ibcon#*after write, iclass 27, count 0 2006.285.22:24:49.31#ibcon#*before return 0, iclass 27, count 0 2006.285.22:24:49.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:24:49.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:24:49.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:24:49.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:24:49.31$vck44/va=3,7 2006.285.22:24:49.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.22:24:49.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.22:24:49.31#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:49.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:24:49.36#abcon#<5=/00 0.2 1.0 16.65 991016.1\r\n> 2006.285.22:24:49.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:24:49.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:24:49.37#ibcon#enter wrdev, iclass 29, count 2 2006.285.22:24:49.37#ibcon#first serial, iclass 29, count 2 2006.285.22:24:49.37#ibcon#enter sib2, iclass 29, count 2 2006.285.22:24:49.37#ibcon#flushed, iclass 29, count 2 2006.285.22:24:49.37#ibcon#about to write, iclass 29, count 2 2006.285.22:24:49.37#ibcon#wrote, iclass 29, count 2 2006.285.22:24:49.37#ibcon#about to read 3, iclass 29, count 2 2006.285.22:24:49.38#abcon#{5=INTERFACE CLEAR} 2006.285.22:24:49.39#ibcon#read 3, iclass 29, count 2 2006.285.22:24:49.39#ibcon#about to read 4, iclass 29, count 2 2006.285.22:24:49.39#ibcon#read 4, iclass 29, count 2 2006.285.22:24:49.39#ibcon#about to read 5, iclass 29, count 2 2006.285.22:24:49.39#ibcon#read 5, iclass 29, count 2 2006.285.22:24:49.39#ibcon#about to read 6, iclass 29, count 2 2006.285.22:24:49.39#ibcon#read 6, iclass 29, count 2 2006.285.22:24:49.39#ibcon#end of sib2, iclass 29, count 2 2006.285.22:24:49.39#ibcon#*mode == 0, iclass 29, count 2 2006.285.22:24:49.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.22:24:49.39#ibcon#[25=AT03-07\r\n] 2006.285.22:24:49.39#ibcon#*before write, iclass 29, count 2 2006.285.22:24:49.39#ibcon#enter sib2, iclass 29, count 2 2006.285.22:24:49.39#ibcon#flushed, iclass 29, count 2 2006.285.22:24:49.39#ibcon#about to write, iclass 29, count 2 2006.285.22:24:49.39#ibcon#wrote, iclass 29, count 2 2006.285.22:24:49.39#ibcon#about to read 3, iclass 29, count 2 2006.285.22:24:49.42#ibcon#read 3, iclass 29, count 2 2006.285.22:24:49.42#ibcon#about to read 4, iclass 29, count 2 2006.285.22:24:49.42#ibcon#read 4, iclass 29, count 2 2006.285.22:24:49.42#ibcon#about to read 5, iclass 29, count 2 2006.285.22:24:49.42#ibcon#read 5, iclass 29, count 2 2006.285.22:24:49.42#ibcon#about to read 6, iclass 29, count 2 2006.285.22:24:49.42#ibcon#read 6, iclass 29, count 2 2006.285.22:24:49.42#ibcon#end of sib2, iclass 29, count 2 2006.285.22:24:49.42#ibcon#*after write, iclass 29, count 2 2006.285.22:24:49.42#ibcon#*before return 0, iclass 29, count 2 2006.285.22:24:49.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:24:49.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:24:49.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.22:24:49.42#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:49.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:24:49.44#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:24:49.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:24:49.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:24:49.54#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:24:49.54#ibcon#first serial, iclass 29, count 0 2006.285.22:24:49.54#ibcon#enter sib2, iclass 29, count 0 2006.285.22:24:49.54#ibcon#flushed, iclass 29, count 0 2006.285.22:24:49.54#ibcon#about to write, iclass 29, count 0 2006.285.22:24:49.54#ibcon#wrote, iclass 29, count 0 2006.285.22:24:49.54#ibcon#about to read 3, iclass 29, count 0 2006.285.22:24:49.56#ibcon#read 3, iclass 29, count 0 2006.285.22:24:49.56#ibcon#about to read 4, iclass 29, count 0 2006.285.22:24:49.56#ibcon#read 4, iclass 29, count 0 2006.285.22:24:49.56#ibcon#about to read 5, iclass 29, count 0 2006.285.22:24:49.56#ibcon#read 5, iclass 29, count 0 2006.285.22:24:49.56#ibcon#about to read 6, iclass 29, count 0 2006.285.22:24:49.56#ibcon#read 6, iclass 29, count 0 2006.285.22:24:49.56#ibcon#end of sib2, iclass 29, count 0 2006.285.22:24:49.56#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:24:49.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:24:49.56#ibcon#[25=USB\r\n] 2006.285.22:24:49.56#ibcon#*before write, iclass 29, count 0 2006.285.22:24:49.56#ibcon#enter sib2, iclass 29, count 0 2006.285.22:24:49.56#ibcon#flushed, iclass 29, count 0 2006.285.22:24:49.56#ibcon#about to write, iclass 29, count 0 2006.285.22:24:49.56#ibcon#wrote, iclass 29, count 0 2006.285.22:24:49.56#ibcon#about to read 3, iclass 29, count 0 2006.285.22:24:49.59#ibcon#read 3, iclass 29, count 0 2006.285.22:24:49.59#ibcon#about to read 4, iclass 29, count 0 2006.285.22:24:49.59#ibcon#read 4, iclass 29, count 0 2006.285.22:24:49.59#ibcon#about to read 5, iclass 29, count 0 2006.285.22:24:49.59#ibcon#read 5, iclass 29, count 0 2006.285.22:24:49.59#ibcon#about to read 6, iclass 29, count 0 2006.285.22:24:49.59#ibcon#read 6, iclass 29, count 0 2006.285.22:24:49.59#ibcon#end of sib2, iclass 29, count 0 2006.285.22:24:49.59#ibcon#*after write, iclass 29, count 0 2006.285.22:24:49.59#ibcon#*before return 0, iclass 29, count 0 2006.285.22:24:49.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:24:49.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:24:49.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:24:49.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:24:49.59$vck44/valo=4,624.99 2006.285.22:24:49.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.22:24:49.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.22:24:49.59#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:49.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:24:49.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:24:49.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:24:49.59#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:24:49.59#ibcon#first serial, iclass 35, count 0 2006.285.22:24:49.59#ibcon#enter sib2, iclass 35, count 0 2006.285.22:24:49.59#ibcon#flushed, iclass 35, count 0 2006.285.22:24:49.59#ibcon#about to write, iclass 35, count 0 2006.285.22:24:49.59#ibcon#wrote, iclass 35, count 0 2006.285.22:24:49.59#ibcon#about to read 3, iclass 35, count 0 2006.285.22:24:49.61#ibcon#read 3, iclass 35, count 0 2006.285.22:24:49.61#ibcon#about to read 4, iclass 35, count 0 2006.285.22:24:49.61#ibcon#read 4, iclass 35, count 0 2006.285.22:24:49.61#ibcon#about to read 5, iclass 35, count 0 2006.285.22:24:49.61#ibcon#read 5, iclass 35, count 0 2006.285.22:24:49.61#ibcon#about to read 6, iclass 35, count 0 2006.285.22:24:49.61#ibcon#read 6, iclass 35, count 0 2006.285.22:24:49.61#ibcon#end of sib2, iclass 35, count 0 2006.285.22:24:49.61#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:24:49.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:24:49.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:24:49.61#ibcon#*before write, iclass 35, count 0 2006.285.22:24:49.61#ibcon#enter sib2, iclass 35, count 0 2006.285.22:24:49.61#ibcon#flushed, iclass 35, count 0 2006.285.22:24:49.61#ibcon#about to write, iclass 35, count 0 2006.285.22:24:49.61#ibcon#wrote, iclass 35, count 0 2006.285.22:24:49.61#ibcon#about to read 3, iclass 35, count 0 2006.285.22:24:49.65#ibcon#read 3, iclass 35, count 0 2006.285.22:24:49.65#ibcon#about to read 4, iclass 35, count 0 2006.285.22:24:49.65#ibcon#read 4, iclass 35, count 0 2006.285.22:24:49.65#ibcon#about to read 5, iclass 35, count 0 2006.285.22:24:49.65#ibcon#read 5, iclass 35, count 0 2006.285.22:24:49.65#ibcon#about to read 6, iclass 35, count 0 2006.285.22:24:49.65#ibcon#read 6, iclass 35, count 0 2006.285.22:24:49.65#ibcon#end of sib2, iclass 35, count 0 2006.285.22:24:49.65#ibcon#*after write, iclass 35, count 0 2006.285.22:24:49.65#ibcon#*before return 0, iclass 35, count 0 2006.285.22:24:49.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:24:49.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:24:49.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:24:49.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:24:49.65$vck44/va=4,6 2006.285.22:24:49.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.22:24:49.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.22:24:49.65#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:49.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:24:49.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:24:49.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:24:49.71#ibcon#enter wrdev, iclass 37, count 2 2006.285.22:24:49.71#ibcon#first serial, iclass 37, count 2 2006.285.22:24:49.71#ibcon#enter sib2, iclass 37, count 2 2006.285.22:24:49.71#ibcon#flushed, iclass 37, count 2 2006.285.22:24:49.71#ibcon#about to write, iclass 37, count 2 2006.285.22:24:49.71#ibcon#wrote, iclass 37, count 2 2006.285.22:24:49.71#ibcon#about to read 3, iclass 37, count 2 2006.285.22:24:49.73#ibcon#read 3, iclass 37, count 2 2006.285.22:24:49.73#ibcon#about to read 4, iclass 37, count 2 2006.285.22:24:49.73#ibcon#read 4, iclass 37, count 2 2006.285.22:24:49.73#ibcon#about to read 5, iclass 37, count 2 2006.285.22:24:49.73#ibcon#read 5, iclass 37, count 2 2006.285.22:24:49.73#ibcon#about to read 6, iclass 37, count 2 2006.285.22:24:49.73#ibcon#read 6, iclass 37, count 2 2006.285.22:24:49.73#ibcon#end of sib2, iclass 37, count 2 2006.285.22:24:49.73#ibcon#*mode == 0, iclass 37, count 2 2006.285.22:24:49.73#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.22:24:49.73#ibcon#[25=AT04-06\r\n] 2006.285.22:24:49.73#ibcon#*before write, iclass 37, count 2 2006.285.22:24:49.73#ibcon#enter sib2, iclass 37, count 2 2006.285.22:24:49.73#ibcon#flushed, iclass 37, count 2 2006.285.22:24:49.73#ibcon#about to write, iclass 37, count 2 2006.285.22:24:49.73#ibcon#wrote, iclass 37, count 2 2006.285.22:24:49.73#ibcon#about to read 3, iclass 37, count 2 2006.285.22:24:49.76#ibcon#read 3, iclass 37, count 2 2006.285.22:24:49.76#ibcon#about to read 4, iclass 37, count 2 2006.285.22:24:49.76#ibcon#read 4, iclass 37, count 2 2006.285.22:24:49.76#ibcon#about to read 5, iclass 37, count 2 2006.285.22:24:49.76#ibcon#read 5, iclass 37, count 2 2006.285.22:24:49.76#ibcon#about to read 6, iclass 37, count 2 2006.285.22:24:49.76#ibcon#read 6, iclass 37, count 2 2006.285.22:24:49.76#ibcon#end of sib2, iclass 37, count 2 2006.285.22:24:49.76#ibcon#*after write, iclass 37, count 2 2006.285.22:24:49.76#ibcon#*before return 0, iclass 37, count 2 2006.285.22:24:49.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:24:49.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:24:49.76#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.22:24:49.76#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:49.76#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:24:49.88#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:24:49.88#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:24:49.88#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:24:49.88#ibcon#first serial, iclass 37, count 0 2006.285.22:24:49.88#ibcon#enter sib2, iclass 37, count 0 2006.285.22:24:49.88#ibcon#flushed, iclass 37, count 0 2006.285.22:24:49.88#ibcon#about to write, iclass 37, count 0 2006.285.22:24:49.88#ibcon#wrote, iclass 37, count 0 2006.285.22:24:49.88#ibcon#about to read 3, iclass 37, count 0 2006.285.22:24:49.90#ibcon#read 3, iclass 37, count 0 2006.285.22:24:49.90#ibcon#about to read 4, iclass 37, count 0 2006.285.22:24:49.90#ibcon#read 4, iclass 37, count 0 2006.285.22:24:49.90#ibcon#about to read 5, iclass 37, count 0 2006.285.22:24:49.90#ibcon#read 5, iclass 37, count 0 2006.285.22:24:49.90#ibcon#about to read 6, iclass 37, count 0 2006.285.22:24:49.90#ibcon#read 6, iclass 37, count 0 2006.285.22:24:49.90#ibcon#end of sib2, iclass 37, count 0 2006.285.22:24:49.90#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:24:49.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:24:49.90#ibcon#[25=USB\r\n] 2006.285.22:24:49.90#ibcon#*before write, iclass 37, count 0 2006.285.22:24:49.90#ibcon#enter sib2, iclass 37, count 0 2006.285.22:24:49.90#ibcon#flushed, iclass 37, count 0 2006.285.22:24:49.90#ibcon#about to write, iclass 37, count 0 2006.285.22:24:49.90#ibcon#wrote, iclass 37, count 0 2006.285.22:24:49.90#ibcon#about to read 3, iclass 37, count 0 2006.285.22:24:49.93#ibcon#read 3, iclass 37, count 0 2006.285.22:24:49.93#ibcon#about to read 4, iclass 37, count 0 2006.285.22:24:49.93#ibcon#read 4, iclass 37, count 0 2006.285.22:24:49.93#ibcon#about to read 5, iclass 37, count 0 2006.285.22:24:49.93#ibcon#read 5, iclass 37, count 0 2006.285.22:24:49.93#ibcon#about to read 6, iclass 37, count 0 2006.285.22:24:49.93#ibcon#read 6, iclass 37, count 0 2006.285.22:24:49.93#ibcon#end of sib2, iclass 37, count 0 2006.285.22:24:49.93#ibcon#*after write, iclass 37, count 0 2006.285.22:24:49.93#ibcon#*before return 0, iclass 37, count 0 2006.285.22:24:49.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:24:49.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:24:49.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:24:49.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:24:49.93$vck44/valo=5,734.99 2006.285.22:24:49.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.22:24:49.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.22:24:49.93#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:49.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:24:49.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:24:49.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:24:49.93#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:24:49.93#ibcon#first serial, iclass 39, count 0 2006.285.22:24:49.93#ibcon#enter sib2, iclass 39, count 0 2006.285.22:24:49.93#ibcon#flushed, iclass 39, count 0 2006.285.22:24:49.93#ibcon#about to write, iclass 39, count 0 2006.285.22:24:49.93#ibcon#wrote, iclass 39, count 0 2006.285.22:24:49.93#ibcon#about to read 3, iclass 39, count 0 2006.285.22:24:49.95#ibcon#read 3, iclass 39, count 0 2006.285.22:24:49.95#ibcon#about to read 4, iclass 39, count 0 2006.285.22:24:49.95#ibcon#read 4, iclass 39, count 0 2006.285.22:24:49.95#ibcon#about to read 5, iclass 39, count 0 2006.285.22:24:49.95#ibcon#read 5, iclass 39, count 0 2006.285.22:24:49.95#ibcon#about to read 6, iclass 39, count 0 2006.285.22:24:49.95#ibcon#read 6, iclass 39, count 0 2006.285.22:24:49.95#ibcon#end of sib2, iclass 39, count 0 2006.285.22:24:49.95#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:24:49.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:24:49.95#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:24:49.95#ibcon#*before write, iclass 39, count 0 2006.285.22:24:49.95#ibcon#enter sib2, iclass 39, count 0 2006.285.22:24:49.95#ibcon#flushed, iclass 39, count 0 2006.285.22:24:49.95#ibcon#about to write, iclass 39, count 0 2006.285.22:24:49.95#ibcon#wrote, iclass 39, count 0 2006.285.22:24:49.95#ibcon#about to read 3, iclass 39, count 0 2006.285.22:24:49.99#ibcon#read 3, iclass 39, count 0 2006.285.22:24:49.99#ibcon#about to read 4, iclass 39, count 0 2006.285.22:24:49.99#ibcon#read 4, iclass 39, count 0 2006.285.22:24:49.99#ibcon#about to read 5, iclass 39, count 0 2006.285.22:24:49.99#ibcon#read 5, iclass 39, count 0 2006.285.22:24:49.99#ibcon#about to read 6, iclass 39, count 0 2006.285.22:24:49.99#ibcon#read 6, iclass 39, count 0 2006.285.22:24:49.99#ibcon#end of sib2, iclass 39, count 0 2006.285.22:24:49.99#ibcon#*after write, iclass 39, count 0 2006.285.22:24:49.99#ibcon#*before return 0, iclass 39, count 0 2006.285.22:24:49.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:24:49.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:24:49.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:24:49.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:24:49.99$vck44/va=5,3 2006.285.22:24:49.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.22:24:49.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.22:24:49.99#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:49.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:24:50.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:24:50.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:24:50.05#ibcon#enter wrdev, iclass 3, count 2 2006.285.22:24:50.05#ibcon#first serial, iclass 3, count 2 2006.285.22:24:50.05#ibcon#enter sib2, iclass 3, count 2 2006.285.22:24:50.05#ibcon#flushed, iclass 3, count 2 2006.285.22:24:50.05#ibcon#about to write, iclass 3, count 2 2006.285.22:24:50.05#ibcon#wrote, iclass 3, count 2 2006.285.22:24:50.05#ibcon#about to read 3, iclass 3, count 2 2006.285.22:24:50.07#ibcon#read 3, iclass 3, count 2 2006.285.22:24:50.07#ibcon#about to read 4, iclass 3, count 2 2006.285.22:24:50.07#ibcon#read 4, iclass 3, count 2 2006.285.22:24:50.07#ibcon#about to read 5, iclass 3, count 2 2006.285.22:24:50.07#ibcon#read 5, iclass 3, count 2 2006.285.22:24:50.07#ibcon#about to read 6, iclass 3, count 2 2006.285.22:24:50.07#ibcon#read 6, iclass 3, count 2 2006.285.22:24:50.07#ibcon#end of sib2, iclass 3, count 2 2006.285.22:24:50.07#ibcon#*mode == 0, iclass 3, count 2 2006.285.22:24:50.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.22:24:50.07#ibcon#[25=AT05-03\r\n] 2006.285.22:24:50.07#ibcon#*before write, iclass 3, count 2 2006.285.22:24:50.07#ibcon#enter sib2, iclass 3, count 2 2006.285.22:24:50.07#ibcon#flushed, iclass 3, count 2 2006.285.22:24:50.07#ibcon#about to write, iclass 3, count 2 2006.285.22:24:50.07#ibcon#wrote, iclass 3, count 2 2006.285.22:24:50.07#ibcon#about to read 3, iclass 3, count 2 2006.285.22:24:50.10#ibcon#read 3, iclass 3, count 2 2006.285.22:24:50.10#ibcon#about to read 4, iclass 3, count 2 2006.285.22:24:50.10#ibcon#read 4, iclass 3, count 2 2006.285.22:24:50.10#ibcon#about to read 5, iclass 3, count 2 2006.285.22:24:50.10#ibcon#read 5, iclass 3, count 2 2006.285.22:24:50.10#ibcon#about to read 6, iclass 3, count 2 2006.285.22:24:50.10#ibcon#read 6, iclass 3, count 2 2006.285.22:24:50.10#ibcon#end of sib2, iclass 3, count 2 2006.285.22:24:50.10#ibcon#*after write, iclass 3, count 2 2006.285.22:24:50.10#ibcon#*before return 0, iclass 3, count 2 2006.285.22:24:50.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:24:50.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:24:50.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.22:24:50.10#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:50.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:24:50.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:24:50.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:24:50.22#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:24:50.22#ibcon#first serial, iclass 3, count 0 2006.285.22:24:50.22#ibcon#enter sib2, iclass 3, count 0 2006.285.22:24:50.22#ibcon#flushed, iclass 3, count 0 2006.285.22:24:50.22#ibcon#about to write, iclass 3, count 0 2006.285.22:24:50.22#ibcon#wrote, iclass 3, count 0 2006.285.22:24:50.22#ibcon#about to read 3, iclass 3, count 0 2006.285.22:24:50.24#ibcon#read 3, iclass 3, count 0 2006.285.22:24:50.24#ibcon#about to read 4, iclass 3, count 0 2006.285.22:24:50.24#ibcon#read 4, iclass 3, count 0 2006.285.22:24:50.24#ibcon#about to read 5, iclass 3, count 0 2006.285.22:24:50.24#ibcon#read 5, iclass 3, count 0 2006.285.22:24:50.24#ibcon#about to read 6, iclass 3, count 0 2006.285.22:24:50.24#ibcon#read 6, iclass 3, count 0 2006.285.22:24:50.24#ibcon#end of sib2, iclass 3, count 0 2006.285.22:24:50.24#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:24:50.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:24:50.24#ibcon#[25=USB\r\n] 2006.285.22:24:50.24#ibcon#*before write, iclass 3, count 0 2006.285.22:24:50.24#ibcon#enter sib2, iclass 3, count 0 2006.285.22:24:50.24#ibcon#flushed, iclass 3, count 0 2006.285.22:24:50.24#ibcon#about to write, iclass 3, count 0 2006.285.22:24:50.24#ibcon#wrote, iclass 3, count 0 2006.285.22:24:50.24#ibcon#about to read 3, iclass 3, count 0 2006.285.22:24:50.27#ibcon#read 3, iclass 3, count 0 2006.285.22:24:50.27#ibcon#about to read 4, iclass 3, count 0 2006.285.22:24:50.27#ibcon#read 4, iclass 3, count 0 2006.285.22:24:50.27#ibcon#about to read 5, iclass 3, count 0 2006.285.22:24:50.27#ibcon#read 5, iclass 3, count 0 2006.285.22:24:50.27#ibcon#about to read 6, iclass 3, count 0 2006.285.22:24:50.27#ibcon#read 6, iclass 3, count 0 2006.285.22:24:50.27#ibcon#end of sib2, iclass 3, count 0 2006.285.22:24:50.27#ibcon#*after write, iclass 3, count 0 2006.285.22:24:50.27#ibcon#*before return 0, iclass 3, count 0 2006.285.22:24:50.27#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:24:50.27#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:24:50.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:24:50.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:24:50.27$vck44/valo=6,814.99 2006.285.22:24:50.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.22:24:50.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.22:24:50.27#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:50.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:24:50.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:24:50.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:24:50.27#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:24:50.27#ibcon#first serial, iclass 5, count 0 2006.285.22:24:50.27#ibcon#enter sib2, iclass 5, count 0 2006.285.22:24:50.27#ibcon#flushed, iclass 5, count 0 2006.285.22:24:50.27#ibcon#about to write, iclass 5, count 0 2006.285.22:24:50.27#ibcon#wrote, iclass 5, count 0 2006.285.22:24:50.27#ibcon#about to read 3, iclass 5, count 0 2006.285.22:24:50.29#ibcon#read 3, iclass 5, count 0 2006.285.22:24:50.29#ibcon#about to read 4, iclass 5, count 0 2006.285.22:24:50.29#ibcon#read 4, iclass 5, count 0 2006.285.22:24:50.29#ibcon#about to read 5, iclass 5, count 0 2006.285.22:24:50.29#ibcon#read 5, iclass 5, count 0 2006.285.22:24:50.29#ibcon#about to read 6, iclass 5, count 0 2006.285.22:24:50.29#ibcon#read 6, iclass 5, count 0 2006.285.22:24:50.29#ibcon#end of sib2, iclass 5, count 0 2006.285.22:24:50.29#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:24:50.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:24:50.29#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:24:50.29#ibcon#*before write, iclass 5, count 0 2006.285.22:24:50.29#ibcon#enter sib2, iclass 5, count 0 2006.285.22:24:50.29#ibcon#flushed, iclass 5, count 0 2006.285.22:24:50.29#ibcon#about to write, iclass 5, count 0 2006.285.22:24:50.29#ibcon#wrote, iclass 5, count 0 2006.285.22:24:50.29#ibcon#about to read 3, iclass 5, count 0 2006.285.22:24:50.33#ibcon#read 3, iclass 5, count 0 2006.285.22:24:50.33#ibcon#about to read 4, iclass 5, count 0 2006.285.22:24:50.33#ibcon#read 4, iclass 5, count 0 2006.285.22:24:50.33#ibcon#about to read 5, iclass 5, count 0 2006.285.22:24:50.33#ibcon#read 5, iclass 5, count 0 2006.285.22:24:50.33#ibcon#about to read 6, iclass 5, count 0 2006.285.22:24:50.33#ibcon#read 6, iclass 5, count 0 2006.285.22:24:50.33#ibcon#end of sib2, iclass 5, count 0 2006.285.22:24:50.33#ibcon#*after write, iclass 5, count 0 2006.285.22:24:50.33#ibcon#*before return 0, iclass 5, count 0 2006.285.22:24:50.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:24:50.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:24:50.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:24:50.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:24:50.33$vck44/va=6,4 2006.285.22:24:50.33#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.22:24:50.33#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.22:24:50.33#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:50.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:24:50.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:24:50.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:24:50.39#ibcon#enter wrdev, iclass 7, count 2 2006.285.22:24:50.39#ibcon#first serial, iclass 7, count 2 2006.285.22:24:50.39#ibcon#enter sib2, iclass 7, count 2 2006.285.22:24:50.39#ibcon#flushed, iclass 7, count 2 2006.285.22:24:50.39#ibcon#about to write, iclass 7, count 2 2006.285.22:24:50.39#ibcon#wrote, iclass 7, count 2 2006.285.22:24:50.39#ibcon#about to read 3, iclass 7, count 2 2006.285.22:24:50.41#ibcon#read 3, iclass 7, count 2 2006.285.22:24:50.41#ibcon#about to read 4, iclass 7, count 2 2006.285.22:24:50.41#ibcon#read 4, iclass 7, count 2 2006.285.22:24:50.41#ibcon#about to read 5, iclass 7, count 2 2006.285.22:24:50.41#ibcon#read 5, iclass 7, count 2 2006.285.22:24:50.41#ibcon#about to read 6, iclass 7, count 2 2006.285.22:24:50.41#ibcon#read 6, iclass 7, count 2 2006.285.22:24:50.41#ibcon#end of sib2, iclass 7, count 2 2006.285.22:24:50.41#ibcon#*mode == 0, iclass 7, count 2 2006.285.22:24:50.41#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.22:24:50.41#ibcon#[25=AT06-04\r\n] 2006.285.22:24:50.41#ibcon#*before write, iclass 7, count 2 2006.285.22:24:50.41#ibcon#enter sib2, iclass 7, count 2 2006.285.22:24:50.41#ibcon#flushed, iclass 7, count 2 2006.285.22:24:50.41#ibcon#about to write, iclass 7, count 2 2006.285.22:24:50.41#ibcon#wrote, iclass 7, count 2 2006.285.22:24:50.41#ibcon#about to read 3, iclass 7, count 2 2006.285.22:24:50.44#ibcon#read 3, iclass 7, count 2 2006.285.22:24:50.44#ibcon#about to read 4, iclass 7, count 2 2006.285.22:24:50.44#ibcon#read 4, iclass 7, count 2 2006.285.22:24:50.44#ibcon#about to read 5, iclass 7, count 2 2006.285.22:24:50.44#ibcon#read 5, iclass 7, count 2 2006.285.22:24:50.44#ibcon#about to read 6, iclass 7, count 2 2006.285.22:24:50.44#ibcon#read 6, iclass 7, count 2 2006.285.22:24:50.44#ibcon#end of sib2, iclass 7, count 2 2006.285.22:24:50.44#ibcon#*after write, iclass 7, count 2 2006.285.22:24:50.44#ibcon#*before return 0, iclass 7, count 2 2006.285.22:24:50.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:24:50.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:24:50.44#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.22:24:50.44#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:50.44#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:24:50.56#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:24:50.56#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:24:50.56#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:24:50.56#ibcon#first serial, iclass 7, count 0 2006.285.22:24:50.56#ibcon#enter sib2, iclass 7, count 0 2006.285.22:24:50.56#ibcon#flushed, iclass 7, count 0 2006.285.22:24:50.56#ibcon#about to write, iclass 7, count 0 2006.285.22:24:50.56#ibcon#wrote, iclass 7, count 0 2006.285.22:24:50.56#ibcon#about to read 3, iclass 7, count 0 2006.285.22:24:50.58#ibcon#read 3, iclass 7, count 0 2006.285.22:24:50.58#ibcon#about to read 4, iclass 7, count 0 2006.285.22:24:50.58#ibcon#read 4, iclass 7, count 0 2006.285.22:24:50.58#ibcon#about to read 5, iclass 7, count 0 2006.285.22:24:50.58#ibcon#read 5, iclass 7, count 0 2006.285.22:24:50.58#ibcon#about to read 6, iclass 7, count 0 2006.285.22:24:50.58#ibcon#read 6, iclass 7, count 0 2006.285.22:24:50.58#ibcon#end of sib2, iclass 7, count 0 2006.285.22:24:50.58#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:24:50.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:24:50.58#ibcon#[25=USB\r\n] 2006.285.22:24:50.58#ibcon#*before write, iclass 7, count 0 2006.285.22:24:50.58#ibcon#enter sib2, iclass 7, count 0 2006.285.22:24:50.58#ibcon#flushed, iclass 7, count 0 2006.285.22:24:50.58#ibcon#about to write, iclass 7, count 0 2006.285.22:24:50.58#ibcon#wrote, iclass 7, count 0 2006.285.22:24:50.58#ibcon#about to read 3, iclass 7, count 0 2006.285.22:24:50.61#ibcon#read 3, iclass 7, count 0 2006.285.22:24:50.61#ibcon#about to read 4, iclass 7, count 0 2006.285.22:24:50.61#ibcon#read 4, iclass 7, count 0 2006.285.22:24:50.61#ibcon#about to read 5, iclass 7, count 0 2006.285.22:24:50.61#ibcon#read 5, iclass 7, count 0 2006.285.22:24:50.61#ibcon#about to read 6, iclass 7, count 0 2006.285.22:24:50.61#ibcon#read 6, iclass 7, count 0 2006.285.22:24:50.61#ibcon#end of sib2, iclass 7, count 0 2006.285.22:24:50.61#ibcon#*after write, iclass 7, count 0 2006.285.22:24:50.61#ibcon#*before return 0, iclass 7, count 0 2006.285.22:24:50.61#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:24:50.61#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:24:50.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:24:50.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:24:50.61$vck44/valo=7,864.99 2006.285.22:24:50.61#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.22:24:50.61#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.22:24:50.61#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:50.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:24:50.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:24:50.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:24:50.61#ibcon#enter wrdev, iclass 11, count 0 2006.285.22:24:50.61#ibcon#first serial, iclass 11, count 0 2006.285.22:24:50.61#ibcon#enter sib2, iclass 11, count 0 2006.285.22:24:50.61#ibcon#flushed, iclass 11, count 0 2006.285.22:24:50.61#ibcon#about to write, iclass 11, count 0 2006.285.22:24:50.61#ibcon#wrote, iclass 11, count 0 2006.285.22:24:50.61#ibcon#about to read 3, iclass 11, count 0 2006.285.22:24:50.63#ibcon#read 3, iclass 11, count 0 2006.285.22:24:50.63#ibcon#about to read 4, iclass 11, count 0 2006.285.22:24:50.63#ibcon#read 4, iclass 11, count 0 2006.285.22:24:50.63#ibcon#about to read 5, iclass 11, count 0 2006.285.22:24:50.63#ibcon#read 5, iclass 11, count 0 2006.285.22:24:50.63#ibcon#about to read 6, iclass 11, count 0 2006.285.22:24:50.63#ibcon#read 6, iclass 11, count 0 2006.285.22:24:50.63#ibcon#end of sib2, iclass 11, count 0 2006.285.22:24:50.63#ibcon#*mode == 0, iclass 11, count 0 2006.285.22:24:50.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.22:24:50.63#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:24:50.63#ibcon#*before write, iclass 11, count 0 2006.285.22:24:50.63#ibcon#enter sib2, iclass 11, count 0 2006.285.22:24:50.63#ibcon#flushed, iclass 11, count 0 2006.285.22:24:50.63#ibcon#about to write, iclass 11, count 0 2006.285.22:24:50.63#ibcon#wrote, iclass 11, count 0 2006.285.22:24:50.63#ibcon#about to read 3, iclass 11, count 0 2006.285.22:24:50.67#ibcon#read 3, iclass 11, count 0 2006.285.22:24:50.67#ibcon#about to read 4, iclass 11, count 0 2006.285.22:24:50.67#ibcon#read 4, iclass 11, count 0 2006.285.22:24:50.67#ibcon#about to read 5, iclass 11, count 0 2006.285.22:24:50.67#ibcon#read 5, iclass 11, count 0 2006.285.22:24:50.67#ibcon#about to read 6, iclass 11, count 0 2006.285.22:24:50.67#ibcon#read 6, iclass 11, count 0 2006.285.22:24:50.67#ibcon#end of sib2, iclass 11, count 0 2006.285.22:24:50.67#ibcon#*after write, iclass 11, count 0 2006.285.22:24:50.67#ibcon#*before return 0, iclass 11, count 0 2006.285.22:24:50.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:24:50.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:24:50.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.22:24:50.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.22:24:50.67$vck44/va=7,4 2006.285.22:24:50.67#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.22:24:50.67#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.22:24:50.67#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:50.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:24:50.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:24:50.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:24:50.73#ibcon#enter wrdev, iclass 13, count 2 2006.285.22:24:50.73#ibcon#first serial, iclass 13, count 2 2006.285.22:24:50.73#ibcon#enter sib2, iclass 13, count 2 2006.285.22:24:50.73#ibcon#flushed, iclass 13, count 2 2006.285.22:24:50.73#ibcon#about to write, iclass 13, count 2 2006.285.22:24:50.73#ibcon#wrote, iclass 13, count 2 2006.285.22:24:50.73#ibcon#about to read 3, iclass 13, count 2 2006.285.22:24:50.75#ibcon#read 3, iclass 13, count 2 2006.285.22:24:50.75#ibcon#about to read 4, iclass 13, count 2 2006.285.22:24:50.75#ibcon#read 4, iclass 13, count 2 2006.285.22:24:50.75#ibcon#about to read 5, iclass 13, count 2 2006.285.22:24:50.75#ibcon#read 5, iclass 13, count 2 2006.285.22:24:50.75#ibcon#about to read 6, iclass 13, count 2 2006.285.22:24:50.75#ibcon#read 6, iclass 13, count 2 2006.285.22:24:50.75#ibcon#end of sib2, iclass 13, count 2 2006.285.22:24:50.75#ibcon#*mode == 0, iclass 13, count 2 2006.285.22:24:50.75#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.22:24:50.75#ibcon#[25=AT07-04\r\n] 2006.285.22:24:50.75#ibcon#*before write, iclass 13, count 2 2006.285.22:24:50.75#ibcon#enter sib2, iclass 13, count 2 2006.285.22:24:50.75#ibcon#flushed, iclass 13, count 2 2006.285.22:24:50.75#ibcon#about to write, iclass 13, count 2 2006.285.22:24:50.75#ibcon#wrote, iclass 13, count 2 2006.285.22:24:50.75#ibcon#about to read 3, iclass 13, count 2 2006.285.22:24:50.78#ibcon#read 3, iclass 13, count 2 2006.285.22:24:50.78#ibcon#about to read 4, iclass 13, count 2 2006.285.22:24:50.78#ibcon#read 4, iclass 13, count 2 2006.285.22:24:50.78#ibcon#about to read 5, iclass 13, count 2 2006.285.22:24:50.78#ibcon#read 5, iclass 13, count 2 2006.285.22:24:50.78#ibcon#about to read 6, iclass 13, count 2 2006.285.22:24:50.78#ibcon#read 6, iclass 13, count 2 2006.285.22:24:50.78#ibcon#end of sib2, iclass 13, count 2 2006.285.22:24:50.78#ibcon#*after write, iclass 13, count 2 2006.285.22:24:50.78#ibcon#*before return 0, iclass 13, count 2 2006.285.22:24:50.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:24:50.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:24:50.78#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.22:24:50.78#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:50.78#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:24:50.90#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:24:50.90#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:24:50.90#ibcon#enter wrdev, iclass 13, count 0 2006.285.22:24:50.90#ibcon#first serial, iclass 13, count 0 2006.285.22:24:50.90#ibcon#enter sib2, iclass 13, count 0 2006.285.22:24:50.90#ibcon#flushed, iclass 13, count 0 2006.285.22:24:50.90#ibcon#about to write, iclass 13, count 0 2006.285.22:24:50.90#ibcon#wrote, iclass 13, count 0 2006.285.22:24:50.90#ibcon#about to read 3, iclass 13, count 0 2006.285.22:24:50.92#ibcon#read 3, iclass 13, count 0 2006.285.22:24:50.92#ibcon#about to read 4, iclass 13, count 0 2006.285.22:24:50.92#ibcon#read 4, iclass 13, count 0 2006.285.22:24:50.92#ibcon#about to read 5, iclass 13, count 0 2006.285.22:24:50.92#ibcon#read 5, iclass 13, count 0 2006.285.22:24:50.92#ibcon#about to read 6, iclass 13, count 0 2006.285.22:24:50.92#ibcon#read 6, iclass 13, count 0 2006.285.22:24:50.92#ibcon#end of sib2, iclass 13, count 0 2006.285.22:24:50.92#ibcon#*mode == 0, iclass 13, count 0 2006.285.22:24:50.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.22:24:50.92#ibcon#[25=USB\r\n] 2006.285.22:24:50.92#ibcon#*before write, iclass 13, count 0 2006.285.22:24:50.92#ibcon#enter sib2, iclass 13, count 0 2006.285.22:24:50.92#ibcon#flushed, iclass 13, count 0 2006.285.22:24:50.92#ibcon#about to write, iclass 13, count 0 2006.285.22:24:50.92#ibcon#wrote, iclass 13, count 0 2006.285.22:24:50.92#ibcon#about to read 3, iclass 13, count 0 2006.285.22:24:50.95#ibcon#read 3, iclass 13, count 0 2006.285.22:24:50.95#ibcon#about to read 4, iclass 13, count 0 2006.285.22:24:50.95#ibcon#read 4, iclass 13, count 0 2006.285.22:24:50.95#ibcon#about to read 5, iclass 13, count 0 2006.285.22:24:50.95#ibcon#read 5, iclass 13, count 0 2006.285.22:24:50.95#ibcon#about to read 6, iclass 13, count 0 2006.285.22:24:50.95#ibcon#read 6, iclass 13, count 0 2006.285.22:24:50.95#ibcon#end of sib2, iclass 13, count 0 2006.285.22:24:50.95#ibcon#*after write, iclass 13, count 0 2006.285.22:24:50.95#ibcon#*before return 0, iclass 13, count 0 2006.285.22:24:50.95#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:24:50.95#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:24:50.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.22:24:50.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.22:24:50.95$vck44/valo=8,884.99 2006.285.22:24:50.95#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.22:24:50.95#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.22:24:50.95#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:50.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:24:50.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:24:50.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:24:50.95#ibcon#enter wrdev, iclass 15, count 0 2006.285.22:24:50.95#ibcon#first serial, iclass 15, count 0 2006.285.22:24:50.95#ibcon#enter sib2, iclass 15, count 0 2006.285.22:24:50.95#ibcon#flushed, iclass 15, count 0 2006.285.22:24:50.95#ibcon#about to write, iclass 15, count 0 2006.285.22:24:50.95#ibcon#wrote, iclass 15, count 0 2006.285.22:24:50.95#ibcon#about to read 3, iclass 15, count 0 2006.285.22:24:50.97#ibcon#read 3, iclass 15, count 0 2006.285.22:24:50.97#ibcon#about to read 4, iclass 15, count 0 2006.285.22:24:50.97#ibcon#read 4, iclass 15, count 0 2006.285.22:24:50.97#ibcon#about to read 5, iclass 15, count 0 2006.285.22:24:50.97#ibcon#read 5, iclass 15, count 0 2006.285.22:24:50.97#ibcon#about to read 6, iclass 15, count 0 2006.285.22:24:50.97#ibcon#read 6, iclass 15, count 0 2006.285.22:24:50.97#ibcon#end of sib2, iclass 15, count 0 2006.285.22:24:50.97#ibcon#*mode == 0, iclass 15, count 0 2006.285.22:24:50.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.22:24:50.97#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:24:50.97#ibcon#*before write, iclass 15, count 0 2006.285.22:24:50.97#ibcon#enter sib2, iclass 15, count 0 2006.285.22:24:50.97#ibcon#flushed, iclass 15, count 0 2006.285.22:24:50.97#ibcon#about to write, iclass 15, count 0 2006.285.22:24:50.97#ibcon#wrote, iclass 15, count 0 2006.285.22:24:50.97#ibcon#about to read 3, iclass 15, count 0 2006.285.22:24:51.01#ibcon#read 3, iclass 15, count 0 2006.285.22:24:51.01#ibcon#about to read 4, iclass 15, count 0 2006.285.22:24:51.01#ibcon#read 4, iclass 15, count 0 2006.285.22:24:51.01#ibcon#about to read 5, iclass 15, count 0 2006.285.22:24:51.01#ibcon#read 5, iclass 15, count 0 2006.285.22:24:51.01#ibcon#about to read 6, iclass 15, count 0 2006.285.22:24:51.01#ibcon#read 6, iclass 15, count 0 2006.285.22:24:51.01#ibcon#end of sib2, iclass 15, count 0 2006.285.22:24:51.01#ibcon#*after write, iclass 15, count 0 2006.285.22:24:51.01#ibcon#*before return 0, iclass 15, count 0 2006.285.22:24:51.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:24:51.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:24:51.01#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.22:24:51.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.22:24:51.01$vck44/va=8,3 2006.285.22:24:51.01#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.22:24:51.01#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.22:24:51.01#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:51.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:24:51.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:24:51.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:24:51.07#ibcon#enter wrdev, iclass 17, count 2 2006.285.22:24:51.07#ibcon#first serial, iclass 17, count 2 2006.285.22:24:51.07#ibcon#enter sib2, iclass 17, count 2 2006.285.22:24:51.07#ibcon#flushed, iclass 17, count 2 2006.285.22:24:51.07#ibcon#about to write, iclass 17, count 2 2006.285.22:24:51.07#ibcon#wrote, iclass 17, count 2 2006.285.22:24:51.07#ibcon#about to read 3, iclass 17, count 2 2006.285.22:24:51.09#ibcon#read 3, iclass 17, count 2 2006.285.22:24:51.09#ibcon#about to read 4, iclass 17, count 2 2006.285.22:24:51.09#ibcon#read 4, iclass 17, count 2 2006.285.22:24:51.09#ibcon#about to read 5, iclass 17, count 2 2006.285.22:24:51.09#ibcon#read 5, iclass 17, count 2 2006.285.22:24:51.09#ibcon#about to read 6, iclass 17, count 2 2006.285.22:24:51.09#ibcon#read 6, iclass 17, count 2 2006.285.22:24:51.09#ibcon#end of sib2, iclass 17, count 2 2006.285.22:24:51.09#ibcon#*mode == 0, iclass 17, count 2 2006.285.22:24:51.09#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.22:24:51.09#ibcon#[25=AT08-03\r\n] 2006.285.22:24:51.09#ibcon#*before write, iclass 17, count 2 2006.285.22:24:51.09#ibcon#enter sib2, iclass 17, count 2 2006.285.22:24:51.09#ibcon#flushed, iclass 17, count 2 2006.285.22:24:51.09#ibcon#about to write, iclass 17, count 2 2006.285.22:24:51.09#ibcon#wrote, iclass 17, count 2 2006.285.22:24:51.09#ibcon#about to read 3, iclass 17, count 2 2006.285.22:24:51.12#ibcon#read 3, iclass 17, count 2 2006.285.22:24:51.12#ibcon#about to read 4, iclass 17, count 2 2006.285.22:24:51.12#ibcon#read 4, iclass 17, count 2 2006.285.22:24:51.12#ibcon#about to read 5, iclass 17, count 2 2006.285.22:24:51.12#ibcon#read 5, iclass 17, count 2 2006.285.22:24:51.12#ibcon#about to read 6, iclass 17, count 2 2006.285.22:24:51.12#ibcon#read 6, iclass 17, count 2 2006.285.22:24:51.12#ibcon#end of sib2, iclass 17, count 2 2006.285.22:24:51.12#ibcon#*after write, iclass 17, count 2 2006.285.22:24:51.12#ibcon#*before return 0, iclass 17, count 2 2006.285.22:24:51.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:24:51.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:24:51.12#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.22:24:51.12#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:51.12#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:24:51.24#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:24:51.24#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:24:51.24#ibcon#enter wrdev, iclass 17, count 0 2006.285.22:24:51.24#ibcon#first serial, iclass 17, count 0 2006.285.22:24:51.24#ibcon#enter sib2, iclass 17, count 0 2006.285.22:24:51.24#ibcon#flushed, iclass 17, count 0 2006.285.22:24:51.24#ibcon#about to write, iclass 17, count 0 2006.285.22:24:51.24#ibcon#wrote, iclass 17, count 0 2006.285.22:24:51.24#ibcon#about to read 3, iclass 17, count 0 2006.285.22:24:51.26#ibcon#read 3, iclass 17, count 0 2006.285.22:24:51.26#ibcon#about to read 4, iclass 17, count 0 2006.285.22:24:51.26#ibcon#read 4, iclass 17, count 0 2006.285.22:24:51.26#ibcon#about to read 5, iclass 17, count 0 2006.285.22:24:51.26#ibcon#read 5, iclass 17, count 0 2006.285.22:24:51.26#ibcon#about to read 6, iclass 17, count 0 2006.285.22:24:51.26#ibcon#read 6, iclass 17, count 0 2006.285.22:24:51.26#ibcon#end of sib2, iclass 17, count 0 2006.285.22:24:51.26#ibcon#*mode == 0, iclass 17, count 0 2006.285.22:24:51.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.22:24:51.26#ibcon#[25=USB\r\n] 2006.285.22:24:51.26#ibcon#*before write, iclass 17, count 0 2006.285.22:24:51.26#ibcon#enter sib2, iclass 17, count 0 2006.285.22:24:51.26#ibcon#flushed, iclass 17, count 0 2006.285.22:24:51.26#ibcon#about to write, iclass 17, count 0 2006.285.22:24:51.26#ibcon#wrote, iclass 17, count 0 2006.285.22:24:51.26#ibcon#about to read 3, iclass 17, count 0 2006.285.22:24:51.29#ibcon#read 3, iclass 17, count 0 2006.285.22:24:51.29#ibcon#about to read 4, iclass 17, count 0 2006.285.22:24:51.29#ibcon#read 4, iclass 17, count 0 2006.285.22:24:51.29#ibcon#about to read 5, iclass 17, count 0 2006.285.22:24:51.29#ibcon#read 5, iclass 17, count 0 2006.285.22:24:51.29#ibcon#about to read 6, iclass 17, count 0 2006.285.22:24:51.29#ibcon#read 6, iclass 17, count 0 2006.285.22:24:51.29#ibcon#end of sib2, iclass 17, count 0 2006.285.22:24:51.29#ibcon#*after write, iclass 17, count 0 2006.285.22:24:51.29#ibcon#*before return 0, iclass 17, count 0 2006.285.22:24:51.29#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:24:51.29#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:24:51.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.22:24:51.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.22:24:51.29$vck44/vblo=1,629.99 2006.285.22:24:51.29#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.22:24:51.29#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.22:24:51.29#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:51.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:24:51.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:24:51.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:24:51.29#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:24:51.29#ibcon#first serial, iclass 19, count 0 2006.285.22:24:51.29#ibcon#enter sib2, iclass 19, count 0 2006.285.22:24:51.29#ibcon#flushed, iclass 19, count 0 2006.285.22:24:51.29#ibcon#about to write, iclass 19, count 0 2006.285.22:24:51.29#ibcon#wrote, iclass 19, count 0 2006.285.22:24:51.29#ibcon#about to read 3, iclass 19, count 0 2006.285.22:24:51.31#ibcon#read 3, iclass 19, count 0 2006.285.22:24:51.31#ibcon#about to read 4, iclass 19, count 0 2006.285.22:24:51.31#ibcon#read 4, iclass 19, count 0 2006.285.22:24:51.31#ibcon#about to read 5, iclass 19, count 0 2006.285.22:24:51.31#ibcon#read 5, iclass 19, count 0 2006.285.22:24:51.31#ibcon#about to read 6, iclass 19, count 0 2006.285.22:24:51.31#ibcon#read 6, iclass 19, count 0 2006.285.22:24:51.31#ibcon#end of sib2, iclass 19, count 0 2006.285.22:24:51.31#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:24:51.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:24:51.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:24:51.31#ibcon#*before write, iclass 19, count 0 2006.285.22:24:51.31#ibcon#enter sib2, iclass 19, count 0 2006.285.22:24:51.31#ibcon#flushed, iclass 19, count 0 2006.285.22:24:51.31#ibcon#about to write, iclass 19, count 0 2006.285.22:24:51.31#ibcon#wrote, iclass 19, count 0 2006.285.22:24:51.31#ibcon#about to read 3, iclass 19, count 0 2006.285.22:24:51.35#ibcon#read 3, iclass 19, count 0 2006.285.22:24:51.35#ibcon#about to read 4, iclass 19, count 0 2006.285.22:24:51.35#ibcon#read 4, iclass 19, count 0 2006.285.22:24:51.35#ibcon#about to read 5, iclass 19, count 0 2006.285.22:24:51.35#ibcon#read 5, iclass 19, count 0 2006.285.22:24:51.35#ibcon#about to read 6, iclass 19, count 0 2006.285.22:24:51.35#ibcon#read 6, iclass 19, count 0 2006.285.22:24:51.35#ibcon#end of sib2, iclass 19, count 0 2006.285.22:24:51.35#ibcon#*after write, iclass 19, count 0 2006.285.22:24:51.35#ibcon#*before return 0, iclass 19, count 0 2006.285.22:24:51.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:24:51.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:24:51.35#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:24:51.35#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:24:51.35$vck44/vb=1,4 2006.285.22:24:51.35#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.22:24:51.35#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.22:24:51.35#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:51.35#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:24:51.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:24:51.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:24:51.35#ibcon#enter wrdev, iclass 21, count 2 2006.285.22:24:51.35#ibcon#first serial, iclass 21, count 2 2006.285.22:24:51.35#ibcon#enter sib2, iclass 21, count 2 2006.285.22:24:51.35#ibcon#flushed, iclass 21, count 2 2006.285.22:24:51.35#ibcon#about to write, iclass 21, count 2 2006.285.22:24:51.35#ibcon#wrote, iclass 21, count 2 2006.285.22:24:51.35#ibcon#about to read 3, iclass 21, count 2 2006.285.22:24:51.37#ibcon#read 3, iclass 21, count 2 2006.285.22:24:51.37#ibcon#about to read 4, iclass 21, count 2 2006.285.22:24:51.37#ibcon#read 4, iclass 21, count 2 2006.285.22:24:51.37#ibcon#about to read 5, iclass 21, count 2 2006.285.22:24:51.37#ibcon#read 5, iclass 21, count 2 2006.285.22:24:51.37#ibcon#about to read 6, iclass 21, count 2 2006.285.22:24:51.37#ibcon#read 6, iclass 21, count 2 2006.285.22:24:51.37#ibcon#end of sib2, iclass 21, count 2 2006.285.22:24:51.37#ibcon#*mode == 0, iclass 21, count 2 2006.285.22:24:51.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.22:24:51.37#ibcon#[27=AT01-04\r\n] 2006.285.22:24:51.37#ibcon#*before write, iclass 21, count 2 2006.285.22:24:51.37#ibcon#enter sib2, iclass 21, count 2 2006.285.22:24:51.37#ibcon#flushed, iclass 21, count 2 2006.285.22:24:51.37#ibcon#about to write, iclass 21, count 2 2006.285.22:24:51.37#ibcon#wrote, iclass 21, count 2 2006.285.22:24:51.37#ibcon#about to read 3, iclass 21, count 2 2006.285.22:24:51.40#ibcon#read 3, iclass 21, count 2 2006.285.22:24:51.40#ibcon#about to read 4, iclass 21, count 2 2006.285.22:24:51.40#ibcon#read 4, iclass 21, count 2 2006.285.22:24:51.40#ibcon#about to read 5, iclass 21, count 2 2006.285.22:24:51.40#ibcon#read 5, iclass 21, count 2 2006.285.22:24:51.40#ibcon#about to read 6, iclass 21, count 2 2006.285.22:24:51.40#ibcon#read 6, iclass 21, count 2 2006.285.22:24:51.40#ibcon#end of sib2, iclass 21, count 2 2006.285.22:24:51.40#ibcon#*after write, iclass 21, count 2 2006.285.22:24:51.40#ibcon#*before return 0, iclass 21, count 2 2006.285.22:24:51.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:24:51.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:24:51.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.22:24:51.40#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:51.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:24:51.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:24:51.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:24:51.52#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:24:51.52#ibcon#first serial, iclass 21, count 0 2006.285.22:24:51.52#ibcon#enter sib2, iclass 21, count 0 2006.285.22:24:51.52#ibcon#flushed, iclass 21, count 0 2006.285.22:24:51.52#ibcon#about to write, iclass 21, count 0 2006.285.22:24:51.52#ibcon#wrote, iclass 21, count 0 2006.285.22:24:51.52#ibcon#about to read 3, iclass 21, count 0 2006.285.22:24:51.54#ibcon#read 3, iclass 21, count 0 2006.285.22:24:51.54#ibcon#about to read 4, iclass 21, count 0 2006.285.22:24:51.54#ibcon#read 4, iclass 21, count 0 2006.285.22:24:51.54#ibcon#about to read 5, iclass 21, count 0 2006.285.22:24:51.54#ibcon#read 5, iclass 21, count 0 2006.285.22:24:51.54#ibcon#about to read 6, iclass 21, count 0 2006.285.22:24:51.54#ibcon#read 6, iclass 21, count 0 2006.285.22:24:51.54#ibcon#end of sib2, iclass 21, count 0 2006.285.22:24:51.54#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:24:51.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:24:51.54#ibcon#[27=USB\r\n] 2006.285.22:24:51.54#ibcon#*before write, iclass 21, count 0 2006.285.22:24:51.54#ibcon#enter sib2, iclass 21, count 0 2006.285.22:24:51.54#ibcon#flushed, iclass 21, count 0 2006.285.22:24:51.54#ibcon#about to write, iclass 21, count 0 2006.285.22:24:51.54#ibcon#wrote, iclass 21, count 0 2006.285.22:24:51.54#ibcon#about to read 3, iclass 21, count 0 2006.285.22:24:51.57#ibcon#read 3, iclass 21, count 0 2006.285.22:24:51.57#ibcon#about to read 4, iclass 21, count 0 2006.285.22:24:51.57#ibcon#read 4, iclass 21, count 0 2006.285.22:24:51.57#ibcon#about to read 5, iclass 21, count 0 2006.285.22:24:51.57#ibcon#read 5, iclass 21, count 0 2006.285.22:24:51.57#ibcon#about to read 6, iclass 21, count 0 2006.285.22:24:51.57#ibcon#read 6, iclass 21, count 0 2006.285.22:24:51.57#ibcon#end of sib2, iclass 21, count 0 2006.285.22:24:51.57#ibcon#*after write, iclass 21, count 0 2006.285.22:24:51.57#ibcon#*before return 0, iclass 21, count 0 2006.285.22:24:51.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:24:51.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:24:51.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:24:51.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:24:51.57$vck44/vblo=2,634.99 2006.285.22:24:51.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.22:24:51.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.22:24:51.57#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:51.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:24:51.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:24:51.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:24:51.57#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:24:51.57#ibcon#first serial, iclass 23, count 0 2006.285.22:24:51.57#ibcon#enter sib2, iclass 23, count 0 2006.285.22:24:51.57#ibcon#flushed, iclass 23, count 0 2006.285.22:24:51.57#ibcon#about to write, iclass 23, count 0 2006.285.22:24:51.57#ibcon#wrote, iclass 23, count 0 2006.285.22:24:51.57#ibcon#about to read 3, iclass 23, count 0 2006.285.22:24:51.59#ibcon#read 3, iclass 23, count 0 2006.285.22:24:51.59#ibcon#about to read 4, iclass 23, count 0 2006.285.22:24:51.59#ibcon#read 4, iclass 23, count 0 2006.285.22:24:51.59#ibcon#about to read 5, iclass 23, count 0 2006.285.22:24:51.59#ibcon#read 5, iclass 23, count 0 2006.285.22:24:51.59#ibcon#about to read 6, iclass 23, count 0 2006.285.22:24:51.59#ibcon#read 6, iclass 23, count 0 2006.285.22:24:51.59#ibcon#end of sib2, iclass 23, count 0 2006.285.22:24:51.59#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:24:51.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:24:51.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:24:51.59#ibcon#*before write, iclass 23, count 0 2006.285.22:24:51.59#ibcon#enter sib2, iclass 23, count 0 2006.285.22:24:51.59#ibcon#flushed, iclass 23, count 0 2006.285.22:24:51.59#ibcon#about to write, iclass 23, count 0 2006.285.22:24:51.59#ibcon#wrote, iclass 23, count 0 2006.285.22:24:51.59#ibcon#about to read 3, iclass 23, count 0 2006.285.22:24:51.63#ibcon#read 3, iclass 23, count 0 2006.285.22:24:51.63#ibcon#about to read 4, iclass 23, count 0 2006.285.22:24:51.63#ibcon#read 4, iclass 23, count 0 2006.285.22:24:51.63#ibcon#about to read 5, iclass 23, count 0 2006.285.22:24:51.63#ibcon#read 5, iclass 23, count 0 2006.285.22:24:51.63#ibcon#about to read 6, iclass 23, count 0 2006.285.22:24:51.63#ibcon#read 6, iclass 23, count 0 2006.285.22:24:51.63#ibcon#end of sib2, iclass 23, count 0 2006.285.22:24:51.63#ibcon#*after write, iclass 23, count 0 2006.285.22:24:51.63#ibcon#*before return 0, iclass 23, count 0 2006.285.22:24:51.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:24:51.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:24:51.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:24:51.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:24:51.63$vck44/vb=2,5 2006.285.22:24:51.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.22:24:51.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.22:24:51.63#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:51.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:24:51.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:24:51.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:24:51.69#ibcon#enter wrdev, iclass 25, count 2 2006.285.22:24:51.69#ibcon#first serial, iclass 25, count 2 2006.285.22:24:51.69#ibcon#enter sib2, iclass 25, count 2 2006.285.22:24:51.69#ibcon#flushed, iclass 25, count 2 2006.285.22:24:51.69#ibcon#about to write, iclass 25, count 2 2006.285.22:24:51.69#ibcon#wrote, iclass 25, count 2 2006.285.22:24:51.69#ibcon#about to read 3, iclass 25, count 2 2006.285.22:24:51.71#ibcon#read 3, iclass 25, count 2 2006.285.22:24:51.71#ibcon#about to read 4, iclass 25, count 2 2006.285.22:24:51.71#ibcon#read 4, iclass 25, count 2 2006.285.22:24:51.71#ibcon#about to read 5, iclass 25, count 2 2006.285.22:24:51.71#ibcon#read 5, iclass 25, count 2 2006.285.22:24:51.71#ibcon#about to read 6, iclass 25, count 2 2006.285.22:24:51.71#ibcon#read 6, iclass 25, count 2 2006.285.22:24:51.71#ibcon#end of sib2, iclass 25, count 2 2006.285.22:24:51.71#ibcon#*mode == 0, iclass 25, count 2 2006.285.22:24:51.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.22:24:51.71#ibcon#[27=AT02-05\r\n] 2006.285.22:24:51.71#ibcon#*before write, iclass 25, count 2 2006.285.22:24:51.71#ibcon#enter sib2, iclass 25, count 2 2006.285.22:24:51.71#ibcon#flushed, iclass 25, count 2 2006.285.22:24:51.71#ibcon#about to write, iclass 25, count 2 2006.285.22:24:51.71#ibcon#wrote, iclass 25, count 2 2006.285.22:24:51.71#ibcon#about to read 3, iclass 25, count 2 2006.285.22:24:51.74#ibcon#read 3, iclass 25, count 2 2006.285.22:24:51.74#ibcon#about to read 4, iclass 25, count 2 2006.285.22:24:51.74#ibcon#read 4, iclass 25, count 2 2006.285.22:24:51.74#ibcon#about to read 5, iclass 25, count 2 2006.285.22:24:51.74#ibcon#read 5, iclass 25, count 2 2006.285.22:24:51.74#ibcon#about to read 6, iclass 25, count 2 2006.285.22:24:51.74#ibcon#read 6, iclass 25, count 2 2006.285.22:24:51.74#ibcon#end of sib2, iclass 25, count 2 2006.285.22:24:51.74#ibcon#*after write, iclass 25, count 2 2006.285.22:24:51.74#ibcon#*before return 0, iclass 25, count 2 2006.285.22:24:51.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:24:51.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:24:51.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.22:24:51.74#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:51.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:24:51.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:24:51.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:24:51.86#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:24:51.86#ibcon#first serial, iclass 25, count 0 2006.285.22:24:51.86#ibcon#enter sib2, iclass 25, count 0 2006.285.22:24:51.86#ibcon#flushed, iclass 25, count 0 2006.285.22:24:51.86#ibcon#about to write, iclass 25, count 0 2006.285.22:24:51.86#ibcon#wrote, iclass 25, count 0 2006.285.22:24:51.86#ibcon#about to read 3, iclass 25, count 0 2006.285.22:24:51.88#ibcon#read 3, iclass 25, count 0 2006.285.22:24:51.88#ibcon#about to read 4, iclass 25, count 0 2006.285.22:24:51.88#ibcon#read 4, iclass 25, count 0 2006.285.22:24:51.88#ibcon#about to read 5, iclass 25, count 0 2006.285.22:24:51.88#ibcon#read 5, iclass 25, count 0 2006.285.22:24:51.88#ibcon#about to read 6, iclass 25, count 0 2006.285.22:24:51.88#ibcon#read 6, iclass 25, count 0 2006.285.22:24:51.88#ibcon#end of sib2, iclass 25, count 0 2006.285.22:24:51.88#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:24:51.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:24:51.88#ibcon#[27=USB\r\n] 2006.285.22:24:51.88#ibcon#*before write, iclass 25, count 0 2006.285.22:24:51.88#ibcon#enter sib2, iclass 25, count 0 2006.285.22:24:51.88#ibcon#flushed, iclass 25, count 0 2006.285.22:24:51.88#ibcon#about to write, iclass 25, count 0 2006.285.22:24:51.88#ibcon#wrote, iclass 25, count 0 2006.285.22:24:51.88#ibcon#about to read 3, iclass 25, count 0 2006.285.22:24:51.91#ibcon#read 3, iclass 25, count 0 2006.285.22:24:51.91#ibcon#about to read 4, iclass 25, count 0 2006.285.22:24:51.91#ibcon#read 4, iclass 25, count 0 2006.285.22:24:51.91#ibcon#about to read 5, iclass 25, count 0 2006.285.22:24:51.91#ibcon#read 5, iclass 25, count 0 2006.285.22:24:51.91#ibcon#about to read 6, iclass 25, count 0 2006.285.22:24:51.91#ibcon#read 6, iclass 25, count 0 2006.285.22:24:51.91#ibcon#end of sib2, iclass 25, count 0 2006.285.22:24:51.91#ibcon#*after write, iclass 25, count 0 2006.285.22:24:51.91#ibcon#*before return 0, iclass 25, count 0 2006.285.22:24:51.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:24:51.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:24:51.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:24:51.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:24:51.91$vck44/vblo=3,649.99 2006.285.22:24:51.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.22:24:51.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.22:24:51.91#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:51.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:24:51.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:24:51.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:24:51.91#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:24:51.91#ibcon#first serial, iclass 27, count 0 2006.285.22:24:51.91#ibcon#enter sib2, iclass 27, count 0 2006.285.22:24:51.91#ibcon#flushed, iclass 27, count 0 2006.285.22:24:51.91#ibcon#about to write, iclass 27, count 0 2006.285.22:24:51.91#ibcon#wrote, iclass 27, count 0 2006.285.22:24:51.91#ibcon#about to read 3, iclass 27, count 0 2006.285.22:24:51.93#ibcon#read 3, iclass 27, count 0 2006.285.22:24:51.93#ibcon#about to read 4, iclass 27, count 0 2006.285.22:24:51.93#ibcon#read 4, iclass 27, count 0 2006.285.22:24:51.93#ibcon#about to read 5, iclass 27, count 0 2006.285.22:24:51.93#ibcon#read 5, iclass 27, count 0 2006.285.22:24:51.93#ibcon#about to read 6, iclass 27, count 0 2006.285.22:24:51.93#ibcon#read 6, iclass 27, count 0 2006.285.22:24:51.93#ibcon#end of sib2, iclass 27, count 0 2006.285.22:24:51.93#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:24:51.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:24:51.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:24:51.93#ibcon#*before write, iclass 27, count 0 2006.285.22:24:51.93#ibcon#enter sib2, iclass 27, count 0 2006.285.22:24:51.93#ibcon#flushed, iclass 27, count 0 2006.285.22:24:51.93#ibcon#about to write, iclass 27, count 0 2006.285.22:24:51.93#ibcon#wrote, iclass 27, count 0 2006.285.22:24:51.93#ibcon#about to read 3, iclass 27, count 0 2006.285.22:24:51.97#ibcon#read 3, iclass 27, count 0 2006.285.22:24:51.97#ibcon#about to read 4, iclass 27, count 0 2006.285.22:24:51.97#ibcon#read 4, iclass 27, count 0 2006.285.22:24:51.97#ibcon#about to read 5, iclass 27, count 0 2006.285.22:24:51.97#ibcon#read 5, iclass 27, count 0 2006.285.22:24:51.97#ibcon#about to read 6, iclass 27, count 0 2006.285.22:24:51.97#ibcon#read 6, iclass 27, count 0 2006.285.22:24:51.97#ibcon#end of sib2, iclass 27, count 0 2006.285.22:24:51.97#ibcon#*after write, iclass 27, count 0 2006.285.22:24:51.97#ibcon#*before return 0, iclass 27, count 0 2006.285.22:24:51.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:24:51.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:24:51.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:24:51.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:24:51.97$vck44/vb=3,4 2006.285.22:24:51.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.22:24:51.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.22:24:51.97#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:51.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:24:52.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:24:52.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:24:52.03#ibcon#enter wrdev, iclass 29, count 2 2006.285.22:24:52.03#ibcon#first serial, iclass 29, count 2 2006.285.22:24:52.03#ibcon#enter sib2, iclass 29, count 2 2006.285.22:24:52.03#ibcon#flushed, iclass 29, count 2 2006.285.22:24:52.03#ibcon#about to write, iclass 29, count 2 2006.285.22:24:52.03#ibcon#wrote, iclass 29, count 2 2006.285.22:24:52.03#ibcon#about to read 3, iclass 29, count 2 2006.285.22:24:52.05#ibcon#read 3, iclass 29, count 2 2006.285.22:24:52.05#ibcon#about to read 4, iclass 29, count 2 2006.285.22:24:52.05#ibcon#read 4, iclass 29, count 2 2006.285.22:24:52.05#ibcon#about to read 5, iclass 29, count 2 2006.285.22:24:52.05#ibcon#read 5, iclass 29, count 2 2006.285.22:24:52.05#ibcon#about to read 6, iclass 29, count 2 2006.285.22:24:52.05#ibcon#read 6, iclass 29, count 2 2006.285.22:24:52.05#ibcon#end of sib2, iclass 29, count 2 2006.285.22:24:52.05#ibcon#*mode == 0, iclass 29, count 2 2006.285.22:24:52.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.22:24:52.05#ibcon#[27=AT03-04\r\n] 2006.285.22:24:52.05#ibcon#*before write, iclass 29, count 2 2006.285.22:24:52.05#ibcon#enter sib2, iclass 29, count 2 2006.285.22:24:52.05#ibcon#flushed, iclass 29, count 2 2006.285.22:24:52.05#ibcon#about to write, iclass 29, count 2 2006.285.22:24:52.05#ibcon#wrote, iclass 29, count 2 2006.285.22:24:52.05#ibcon#about to read 3, iclass 29, count 2 2006.285.22:24:52.08#ibcon#read 3, iclass 29, count 2 2006.285.22:24:52.08#ibcon#about to read 4, iclass 29, count 2 2006.285.22:24:52.08#ibcon#read 4, iclass 29, count 2 2006.285.22:24:52.08#ibcon#about to read 5, iclass 29, count 2 2006.285.22:24:52.08#ibcon#read 5, iclass 29, count 2 2006.285.22:24:52.08#ibcon#about to read 6, iclass 29, count 2 2006.285.22:24:52.08#ibcon#read 6, iclass 29, count 2 2006.285.22:24:52.08#ibcon#end of sib2, iclass 29, count 2 2006.285.22:24:52.08#ibcon#*after write, iclass 29, count 2 2006.285.22:24:52.08#ibcon#*before return 0, iclass 29, count 2 2006.285.22:24:52.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:24:52.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:24:52.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.22:24:52.08#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:52.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:24:52.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:24:52.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:24:52.20#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:24:52.20#ibcon#first serial, iclass 29, count 0 2006.285.22:24:52.20#ibcon#enter sib2, iclass 29, count 0 2006.285.22:24:52.20#ibcon#flushed, iclass 29, count 0 2006.285.22:24:52.20#ibcon#about to write, iclass 29, count 0 2006.285.22:24:52.20#ibcon#wrote, iclass 29, count 0 2006.285.22:24:52.20#ibcon#about to read 3, iclass 29, count 0 2006.285.22:24:52.22#ibcon#read 3, iclass 29, count 0 2006.285.22:24:52.22#ibcon#about to read 4, iclass 29, count 0 2006.285.22:24:52.22#ibcon#read 4, iclass 29, count 0 2006.285.22:24:52.22#ibcon#about to read 5, iclass 29, count 0 2006.285.22:24:52.22#ibcon#read 5, iclass 29, count 0 2006.285.22:24:52.22#ibcon#about to read 6, iclass 29, count 0 2006.285.22:24:52.22#ibcon#read 6, iclass 29, count 0 2006.285.22:24:52.22#ibcon#end of sib2, iclass 29, count 0 2006.285.22:24:52.22#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:24:52.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:24:52.22#ibcon#[27=USB\r\n] 2006.285.22:24:52.22#ibcon#*before write, iclass 29, count 0 2006.285.22:24:52.22#ibcon#enter sib2, iclass 29, count 0 2006.285.22:24:52.22#ibcon#flushed, iclass 29, count 0 2006.285.22:24:52.22#ibcon#about to write, iclass 29, count 0 2006.285.22:24:52.22#ibcon#wrote, iclass 29, count 0 2006.285.22:24:52.22#ibcon#about to read 3, iclass 29, count 0 2006.285.22:24:52.25#ibcon#read 3, iclass 29, count 0 2006.285.22:24:52.25#ibcon#about to read 4, iclass 29, count 0 2006.285.22:24:52.25#ibcon#read 4, iclass 29, count 0 2006.285.22:24:52.25#ibcon#about to read 5, iclass 29, count 0 2006.285.22:24:52.25#ibcon#read 5, iclass 29, count 0 2006.285.22:24:52.25#ibcon#about to read 6, iclass 29, count 0 2006.285.22:24:52.25#ibcon#read 6, iclass 29, count 0 2006.285.22:24:52.25#ibcon#end of sib2, iclass 29, count 0 2006.285.22:24:52.25#ibcon#*after write, iclass 29, count 0 2006.285.22:24:52.25#ibcon#*before return 0, iclass 29, count 0 2006.285.22:24:52.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:24:52.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:24:52.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:24:52.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:24:52.25$vck44/vblo=4,679.99 2006.285.22:24:52.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.22:24:52.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.22:24:52.25#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:52.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:24:52.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:24:52.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:24:52.25#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:24:52.25#ibcon#first serial, iclass 31, count 0 2006.285.22:24:52.25#ibcon#enter sib2, iclass 31, count 0 2006.285.22:24:52.25#ibcon#flushed, iclass 31, count 0 2006.285.22:24:52.25#ibcon#about to write, iclass 31, count 0 2006.285.22:24:52.25#ibcon#wrote, iclass 31, count 0 2006.285.22:24:52.25#ibcon#about to read 3, iclass 31, count 0 2006.285.22:24:52.27#ibcon#read 3, iclass 31, count 0 2006.285.22:24:52.27#ibcon#about to read 4, iclass 31, count 0 2006.285.22:24:52.27#ibcon#read 4, iclass 31, count 0 2006.285.22:24:52.27#ibcon#about to read 5, iclass 31, count 0 2006.285.22:24:52.27#ibcon#read 5, iclass 31, count 0 2006.285.22:24:52.27#ibcon#about to read 6, iclass 31, count 0 2006.285.22:24:52.27#ibcon#read 6, iclass 31, count 0 2006.285.22:24:52.27#ibcon#end of sib2, iclass 31, count 0 2006.285.22:24:52.27#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:24:52.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:24:52.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.22:24:52.27#ibcon#*before write, iclass 31, count 0 2006.285.22:24:52.27#ibcon#enter sib2, iclass 31, count 0 2006.285.22:24:52.27#ibcon#flushed, iclass 31, count 0 2006.285.22:24:52.27#ibcon#about to write, iclass 31, count 0 2006.285.22:24:52.27#ibcon#wrote, iclass 31, count 0 2006.285.22:24:52.27#ibcon#about to read 3, iclass 31, count 0 2006.285.22:24:52.31#ibcon#read 3, iclass 31, count 0 2006.285.22:24:52.31#ibcon#about to read 4, iclass 31, count 0 2006.285.22:24:52.31#ibcon#read 4, iclass 31, count 0 2006.285.22:24:52.31#ibcon#about to read 5, iclass 31, count 0 2006.285.22:24:52.31#ibcon#read 5, iclass 31, count 0 2006.285.22:24:52.31#ibcon#about to read 6, iclass 31, count 0 2006.285.22:24:52.31#ibcon#read 6, iclass 31, count 0 2006.285.22:24:52.31#ibcon#end of sib2, iclass 31, count 0 2006.285.22:24:52.31#ibcon#*after write, iclass 31, count 0 2006.285.22:24:52.31#ibcon#*before return 0, iclass 31, count 0 2006.285.22:24:52.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:24:52.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:24:52.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:24:52.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:24:52.31$vck44/vb=4,5 2006.285.22:24:52.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.22:24:52.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.22:24:52.31#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:52.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:24:52.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:24:52.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:24:52.37#ibcon#enter wrdev, iclass 33, count 2 2006.285.22:24:52.37#ibcon#first serial, iclass 33, count 2 2006.285.22:24:52.37#ibcon#enter sib2, iclass 33, count 2 2006.285.22:24:52.37#ibcon#flushed, iclass 33, count 2 2006.285.22:24:52.37#ibcon#about to write, iclass 33, count 2 2006.285.22:24:52.37#ibcon#wrote, iclass 33, count 2 2006.285.22:24:52.37#ibcon#about to read 3, iclass 33, count 2 2006.285.22:24:52.39#ibcon#read 3, iclass 33, count 2 2006.285.22:24:52.39#ibcon#about to read 4, iclass 33, count 2 2006.285.22:24:52.39#ibcon#read 4, iclass 33, count 2 2006.285.22:24:52.39#ibcon#about to read 5, iclass 33, count 2 2006.285.22:24:52.39#ibcon#read 5, iclass 33, count 2 2006.285.22:24:52.39#ibcon#about to read 6, iclass 33, count 2 2006.285.22:24:52.39#ibcon#read 6, iclass 33, count 2 2006.285.22:24:52.39#ibcon#end of sib2, iclass 33, count 2 2006.285.22:24:52.39#ibcon#*mode == 0, iclass 33, count 2 2006.285.22:24:52.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.22:24:52.39#ibcon#[27=AT04-05\r\n] 2006.285.22:24:52.39#ibcon#*before write, iclass 33, count 2 2006.285.22:24:52.39#ibcon#enter sib2, iclass 33, count 2 2006.285.22:24:52.39#ibcon#flushed, iclass 33, count 2 2006.285.22:24:52.39#ibcon#about to write, iclass 33, count 2 2006.285.22:24:52.39#ibcon#wrote, iclass 33, count 2 2006.285.22:24:52.39#ibcon#about to read 3, iclass 33, count 2 2006.285.22:24:52.42#ibcon#read 3, iclass 33, count 2 2006.285.22:24:52.42#ibcon#about to read 4, iclass 33, count 2 2006.285.22:24:52.42#ibcon#read 4, iclass 33, count 2 2006.285.22:24:52.42#ibcon#about to read 5, iclass 33, count 2 2006.285.22:24:52.42#ibcon#read 5, iclass 33, count 2 2006.285.22:24:52.42#ibcon#about to read 6, iclass 33, count 2 2006.285.22:24:52.42#ibcon#read 6, iclass 33, count 2 2006.285.22:24:52.42#ibcon#end of sib2, iclass 33, count 2 2006.285.22:24:52.42#ibcon#*after write, iclass 33, count 2 2006.285.22:24:52.42#ibcon#*before return 0, iclass 33, count 2 2006.285.22:24:52.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:24:52.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:24:52.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.22:24:52.42#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:52.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:24:52.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:24:52.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:24:52.54#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:24:52.54#ibcon#first serial, iclass 33, count 0 2006.285.22:24:52.54#ibcon#enter sib2, iclass 33, count 0 2006.285.22:24:52.54#ibcon#flushed, iclass 33, count 0 2006.285.22:24:52.54#ibcon#about to write, iclass 33, count 0 2006.285.22:24:52.54#ibcon#wrote, iclass 33, count 0 2006.285.22:24:52.54#ibcon#about to read 3, iclass 33, count 0 2006.285.22:24:52.56#ibcon#read 3, iclass 33, count 0 2006.285.22:24:52.56#ibcon#about to read 4, iclass 33, count 0 2006.285.22:24:52.56#ibcon#read 4, iclass 33, count 0 2006.285.22:24:52.56#ibcon#about to read 5, iclass 33, count 0 2006.285.22:24:52.56#ibcon#read 5, iclass 33, count 0 2006.285.22:24:52.56#ibcon#about to read 6, iclass 33, count 0 2006.285.22:24:52.56#ibcon#read 6, iclass 33, count 0 2006.285.22:24:52.56#ibcon#end of sib2, iclass 33, count 0 2006.285.22:24:52.56#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:24:52.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:24:52.56#ibcon#[27=USB\r\n] 2006.285.22:24:52.56#ibcon#*before write, iclass 33, count 0 2006.285.22:24:52.56#ibcon#enter sib2, iclass 33, count 0 2006.285.22:24:52.56#ibcon#flushed, iclass 33, count 0 2006.285.22:24:52.56#ibcon#about to write, iclass 33, count 0 2006.285.22:24:52.56#ibcon#wrote, iclass 33, count 0 2006.285.22:24:52.56#ibcon#about to read 3, iclass 33, count 0 2006.285.22:24:52.59#ibcon#read 3, iclass 33, count 0 2006.285.22:24:52.59#ibcon#about to read 4, iclass 33, count 0 2006.285.22:24:52.59#ibcon#read 4, iclass 33, count 0 2006.285.22:24:52.59#ibcon#about to read 5, iclass 33, count 0 2006.285.22:24:52.59#ibcon#read 5, iclass 33, count 0 2006.285.22:24:52.59#ibcon#about to read 6, iclass 33, count 0 2006.285.22:24:52.59#ibcon#read 6, iclass 33, count 0 2006.285.22:24:52.59#ibcon#end of sib2, iclass 33, count 0 2006.285.22:24:52.59#ibcon#*after write, iclass 33, count 0 2006.285.22:24:52.59#ibcon#*before return 0, iclass 33, count 0 2006.285.22:24:52.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:24:52.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:24:52.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:24:52.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:24:52.59$vck44/vblo=5,709.99 2006.285.22:24:52.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.22:24:52.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.22:24:52.59#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:52.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:24:52.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:24:52.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:24:52.59#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:24:52.59#ibcon#first serial, iclass 35, count 0 2006.285.22:24:52.59#ibcon#enter sib2, iclass 35, count 0 2006.285.22:24:52.59#ibcon#flushed, iclass 35, count 0 2006.285.22:24:52.59#ibcon#about to write, iclass 35, count 0 2006.285.22:24:52.59#ibcon#wrote, iclass 35, count 0 2006.285.22:24:52.59#ibcon#about to read 3, iclass 35, count 0 2006.285.22:24:52.61#ibcon#read 3, iclass 35, count 0 2006.285.22:24:52.61#ibcon#about to read 4, iclass 35, count 0 2006.285.22:24:52.61#ibcon#read 4, iclass 35, count 0 2006.285.22:24:52.61#ibcon#about to read 5, iclass 35, count 0 2006.285.22:24:52.61#ibcon#read 5, iclass 35, count 0 2006.285.22:24:52.61#ibcon#about to read 6, iclass 35, count 0 2006.285.22:24:52.61#ibcon#read 6, iclass 35, count 0 2006.285.22:24:52.61#ibcon#end of sib2, iclass 35, count 0 2006.285.22:24:52.61#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:24:52.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:24:52.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.22:24:52.61#ibcon#*before write, iclass 35, count 0 2006.285.22:24:52.61#ibcon#enter sib2, iclass 35, count 0 2006.285.22:24:52.61#ibcon#flushed, iclass 35, count 0 2006.285.22:24:52.61#ibcon#about to write, iclass 35, count 0 2006.285.22:24:52.61#ibcon#wrote, iclass 35, count 0 2006.285.22:24:52.61#ibcon#about to read 3, iclass 35, count 0 2006.285.22:24:52.65#ibcon#read 3, iclass 35, count 0 2006.285.22:24:52.65#ibcon#about to read 4, iclass 35, count 0 2006.285.22:24:52.65#ibcon#read 4, iclass 35, count 0 2006.285.22:24:52.65#ibcon#about to read 5, iclass 35, count 0 2006.285.22:24:52.65#ibcon#read 5, iclass 35, count 0 2006.285.22:24:52.65#ibcon#about to read 6, iclass 35, count 0 2006.285.22:24:52.65#ibcon#read 6, iclass 35, count 0 2006.285.22:24:52.65#ibcon#end of sib2, iclass 35, count 0 2006.285.22:24:52.65#ibcon#*after write, iclass 35, count 0 2006.285.22:24:52.65#ibcon#*before return 0, iclass 35, count 0 2006.285.22:24:52.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:24:52.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:24:52.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:24:52.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:24:52.65$vck44/vb=5,4 2006.285.22:24:52.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.22:24:52.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.22:24:52.65#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:52.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:24:52.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:24:52.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:24:52.71#ibcon#enter wrdev, iclass 37, count 2 2006.285.22:24:52.71#ibcon#first serial, iclass 37, count 2 2006.285.22:24:52.71#ibcon#enter sib2, iclass 37, count 2 2006.285.22:24:52.71#ibcon#flushed, iclass 37, count 2 2006.285.22:24:52.71#ibcon#about to write, iclass 37, count 2 2006.285.22:24:52.71#ibcon#wrote, iclass 37, count 2 2006.285.22:24:52.71#ibcon#about to read 3, iclass 37, count 2 2006.285.22:24:52.73#ibcon#read 3, iclass 37, count 2 2006.285.22:24:52.73#ibcon#about to read 4, iclass 37, count 2 2006.285.22:24:52.73#ibcon#read 4, iclass 37, count 2 2006.285.22:24:52.73#ibcon#about to read 5, iclass 37, count 2 2006.285.22:24:52.73#ibcon#read 5, iclass 37, count 2 2006.285.22:24:52.73#ibcon#about to read 6, iclass 37, count 2 2006.285.22:24:52.73#ibcon#read 6, iclass 37, count 2 2006.285.22:24:52.73#ibcon#end of sib2, iclass 37, count 2 2006.285.22:24:52.73#ibcon#*mode == 0, iclass 37, count 2 2006.285.22:24:52.73#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.22:24:52.73#ibcon#[27=AT05-04\r\n] 2006.285.22:24:52.73#ibcon#*before write, iclass 37, count 2 2006.285.22:24:52.73#ibcon#enter sib2, iclass 37, count 2 2006.285.22:24:52.73#ibcon#flushed, iclass 37, count 2 2006.285.22:24:52.73#ibcon#about to write, iclass 37, count 2 2006.285.22:24:52.73#ibcon#wrote, iclass 37, count 2 2006.285.22:24:52.73#ibcon#about to read 3, iclass 37, count 2 2006.285.22:24:52.76#ibcon#read 3, iclass 37, count 2 2006.285.22:24:52.76#ibcon#about to read 4, iclass 37, count 2 2006.285.22:24:52.76#ibcon#read 4, iclass 37, count 2 2006.285.22:24:52.76#ibcon#about to read 5, iclass 37, count 2 2006.285.22:24:52.76#ibcon#read 5, iclass 37, count 2 2006.285.22:24:52.76#ibcon#about to read 6, iclass 37, count 2 2006.285.22:24:52.76#ibcon#read 6, iclass 37, count 2 2006.285.22:24:52.76#ibcon#end of sib2, iclass 37, count 2 2006.285.22:24:52.76#ibcon#*after write, iclass 37, count 2 2006.285.22:24:52.76#ibcon#*before return 0, iclass 37, count 2 2006.285.22:24:52.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:24:52.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:24:52.76#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.22:24:52.76#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:52.76#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:24:52.88#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:24:52.88#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:24:52.88#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:24:52.88#ibcon#first serial, iclass 37, count 0 2006.285.22:24:52.88#ibcon#enter sib2, iclass 37, count 0 2006.285.22:24:52.88#ibcon#flushed, iclass 37, count 0 2006.285.22:24:52.88#ibcon#about to write, iclass 37, count 0 2006.285.22:24:52.88#ibcon#wrote, iclass 37, count 0 2006.285.22:24:52.88#ibcon#about to read 3, iclass 37, count 0 2006.285.22:24:52.90#ibcon#read 3, iclass 37, count 0 2006.285.22:24:52.90#ibcon#about to read 4, iclass 37, count 0 2006.285.22:24:52.90#ibcon#read 4, iclass 37, count 0 2006.285.22:24:52.90#ibcon#about to read 5, iclass 37, count 0 2006.285.22:24:52.90#ibcon#read 5, iclass 37, count 0 2006.285.22:24:52.90#ibcon#about to read 6, iclass 37, count 0 2006.285.22:24:52.90#ibcon#read 6, iclass 37, count 0 2006.285.22:24:52.90#ibcon#end of sib2, iclass 37, count 0 2006.285.22:24:52.90#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:24:52.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:24:52.90#ibcon#[27=USB\r\n] 2006.285.22:24:52.90#ibcon#*before write, iclass 37, count 0 2006.285.22:24:52.90#ibcon#enter sib2, iclass 37, count 0 2006.285.22:24:52.90#ibcon#flushed, iclass 37, count 0 2006.285.22:24:52.90#ibcon#about to write, iclass 37, count 0 2006.285.22:24:52.90#ibcon#wrote, iclass 37, count 0 2006.285.22:24:52.90#ibcon#about to read 3, iclass 37, count 0 2006.285.22:24:52.93#ibcon#read 3, iclass 37, count 0 2006.285.22:24:52.93#ibcon#about to read 4, iclass 37, count 0 2006.285.22:24:52.93#ibcon#read 4, iclass 37, count 0 2006.285.22:24:52.93#ibcon#about to read 5, iclass 37, count 0 2006.285.22:24:52.93#ibcon#read 5, iclass 37, count 0 2006.285.22:24:52.93#ibcon#about to read 6, iclass 37, count 0 2006.285.22:24:52.93#ibcon#read 6, iclass 37, count 0 2006.285.22:24:52.93#ibcon#end of sib2, iclass 37, count 0 2006.285.22:24:52.93#ibcon#*after write, iclass 37, count 0 2006.285.22:24:52.93#ibcon#*before return 0, iclass 37, count 0 2006.285.22:24:52.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:24:52.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:24:52.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:24:52.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:24:52.93$vck44/vblo=6,719.99 2006.285.22:24:52.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.22:24:52.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.22:24:52.93#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:52.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:24:52.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:24:52.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:24:52.93#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:24:52.93#ibcon#first serial, iclass 39, count 0 2006.285.22:24:52.93#ibcon#enter sib2, iclass 39, count 0 2006.285.22:24:52.93#ibcon#flushed, iclass 39, count 0 2006.285.22:24:52.93#ibcon#about to write, iclass 39, count 0 2006.285.22:24:52.93#ibcon#wrote, iclass 39, count 0 2006.285.22:24:52.93#ibcon#about to read 3, iclass 39, count 0 2006.285.22:24:52.95#ibcon#read 3, iclass 39, count 0 2006.285.22:24:52.95#ibcon#about to read 4, iclass 39, count 0 2006.285.22:24:52.95#ibcon#read 4, iclass 39, count 0 2006.285.22:24:52.95#ibcon#about to read 5, iclass 39, count 0 2006.285.22:24:52.95#ibcon#read 5, iclass 39, count 0 2006.285.22:24:52.95#ibcon#about to read 6, iclass 39, count 0 2006.285.22:24:52.95#ibcon#read 6, iclass 39, count 0 2006.285.22:24:52.95#ibcon#end of sib2, iclass 39, count 0 2006.285.22:24:52.95#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:24:52.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:24:52.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.22:24:52.95#ibcon#*before write, iclass 39, count 0 2006.285.22:24:52.95#ibcon#enter sib2, iclass 39, count 0 2006.285.22:24:52.95#ibcon#flushed, iclass 39, count 0 2006.285.22:24:52.95#ibcon#about to write, iclass 39, count 0 2006.285.22:24:52.95#ibcon#wrote, iclass 39, count 0 2006.285.22:24:52.95#ibcon#about to read 3, iclass 39, count 0 2006.285.22:24:52.99#ibcon#read 3, iclass 39, count 0 2006.285.22:24:52.99#ibcon#about to read 4, iclass 39, count 0 2006.285.22:24:52.99#ibcon#read 4, iclass 39, count 0 2006.285.22:24:52.99#ibcon#about to read 5, iclass 39, count 0 2006.285.22:24:52.99#ibcon#read 5, iclass 39, count 0 2006.285.22:24:52.99#ibcon#about to read 6, iclass 39, count 0 2006.285.22:24:52.99#ibcon#read 6, iclass 39, count 0 2006.285.22:24:52.99#ibcon#end of sib2, iclass 39, count 0 2006.285.22:24:52.99#ibcon#*after write, iclass 39, count 0 2006.285.22:24:52.99#ibcon#*before return 0, iclass 39, count 0 2006.285.22:24:52.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:24:52.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:24:52.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:24:52.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:24:52.99$vck44/vb=6,3 2006.285.22:24:52.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.22:24:52.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.22:24:52.99#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:52.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:24:53.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:24:53.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:24:53.05#ibcon#enter wrdev, iclass 3, count 2 2006.285.22:24:53.05#ibcon#first serial, iclass 3, count 2 2006.285.22:24:53.05#ibcon#enter sib2, iclass 3, count 2 2006.285.22:24:53.05#ibcon#flushed, iclass 3, count 2 2006.285.22:24:53.05#ibcon#about to write, iclass 3, count 2 2006.285.22:24:53.05#ibcon#wrote, iclass 3, count 2 2006.285.22:24:53.05#ibcon#about to read 3, iclass 3, count 2 2006.285.22:24:53.07#ibcon#read 3, iclass 3, count 2 2006.285.22:24:53.07#ibcon#about to read 4, iclass 3, count 2 2006.285.22:24:53.07#ibcon#read 4, iclass 3, count 2 2006.285.22:24:53.07#ibcon#about to read 5, iclass 3, count 2 2006.285.22:24:53.07#ibcon#read 5, iclass 3, count 2 2006.285.22:24:53.07#ibcon#about to read 6, iclass 3, count 2 2006.285.22:24:53.07#ibcon#read 6, iclass 3, count 2 2006.285.22:24:53.07#ibcon#end of sib2, iclass 3, count 2 2006.285.22:24:53.07#ibcon#*mode == 0, iclass 3, count 2 2006.285.22:24:53.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.22:24:53.07#ibcon#[27=AT06-03\r\n] 2006.285.22:24:53.07#ibcon#*before write, iclass 3, count 2 2006.285.22:24:53.07#ibcon#enter sib2, iclass 3, count 2 2006.285.22:24:53.07#ibcon#flushed, iclass 3, count 2 2006.285.22:24:53.07#ibcon#about to write, iclass 3, count 2 2006.285.22:24:53.07#ibcon#wrote, iclass 3, count 2 2006.285.22:24:53.07#ibcon#about to read 3, iclass 3, count 2 2006.285.22:24:53.10#ibcon#read 3, iclass 3, count 2 2006.285.22:24:53.10#ibcon#about to read 4, iclass 3, count 2 2006.285.22:24:53.10#ibcon#read 4, iclass 3, count 2 2006.285.22:24:53.10#ibcon#about to read 5, iclass 3, count 2 2006.285.22:24:53.10#ibcon#read 5, iclass 3, count 2 2006.285.22:24:53.10#ibcon#about to read 6, iclass 3, count 2 2006.285.22:24:53.10#ibcon#read 6, iclass 3, count 2 2006.285.22:24:53.10#ibcon#end of sib2, iclass 3, count 2 2006.285.22:24:53.10#ibcon#*after write, iclass 3, count 2 2006.285.22:24:53.10#ibcon#*before return 0, iclass 3, count 2 2006.285.22:24:53.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:24:53.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:24:53.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.22:24:53.10#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:53.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:24:53.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:24:53.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:24:53.22#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:24:53.22#ibcon#first serial, iclass 3, count 0 2006.285.22:24:53.22#ibcon#enter sib2, iclass 3, count 0 2006.285.22:24:53.22#ibcon#flushed, iclass 3, count 0 2006.285.22:24:53.22#ibcon#about to write, iclass 3, count 0 2006.285.22:24:53.22#ibcon#wrote, iclass 3, count 0 2006.285.22:24:53.22#ibcon#about to read 3, iclass 3, count 0 2006.285.22:24:53.24#ibcon#read 3, iclass 3, count 0 2006.285.22:24:53.24#ibcon#about to read 4, iclass 3, count 0 2006.285.22:24:53.24#ibcon#read 4, iclass 3, count 0 2006.285.22:24:53.24#ibcon#about to read 5, iclass 3, count 0 2006.285.22:24:53.24#ibcon#read 5, iclass 3, count 0 2006.285.22:24:53.24#ibcon#about to read 6, iclass 3, count 0 2006.285.22:24:53.24#ibcon#read 6, iclass 3, count 0 2006.285.22:24:53.24#ibcon#end of sib2, iclass 3, count 0 2006.285.22:24:53.24#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:24:53.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:24:53.24#ibcon#[27=USB\r\n] 2006.285.22:24:53.24#ibcon#*before write, iclass 3, count 0 2006.285.22:24:53.24#ibcon#enter sib2, iclass 3, count 0 2006.285.22:24:53.24#ibcon#flushed, iclass 3, count 0 2006.285.22:24:53.24#ibcon#about to write, iclass 3, count 0 2006.285.22:24:53.24#ibcon#wrote, iclass 3, count 0 2006.285.22:24:53.24#ibcon#about to read 3, iclass 3, count 0 2006.285.22:24:53.27#ibcon#read 3, iclass 3, count 0 2006.285.22:24:53.27#ibcon#about to read 4, iclass 3, count 0 2006.285.22:24:53.27#ibcon#read 4, iclass 3, count 0 2006.285.22:24:53.27#ibcon#about to read 5, iclass 3, count 0 2006.285.22:24:53.27#ibcon#read 5, iclass 3, count 0 2006.285.22:24:53.27#ibcon#about to read 6, iclass 3, count 0 2006.285.22:24:53.27#ibcon#read 6, iclass 3, count 0 2006.285.22:24:53.27#ibcon#end of sib2, iclass 3, count 0 2006.285.22:24:53.27#ibcon#*after write, iclass 3, count 0 2006.285.22:24:53.27#ibcon#*before return 0, iclass 3, count 0 2006.285.22:24:53.27#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:24:53.27#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:24:53.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:24:53.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:24:53.27$vck44/vblo=7,734.99 2006.285.22:24:53.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.22:24:53.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.22:24:53.27#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:53.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:24:53.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:24:53.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:24:53.27#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:24:53.27#ibcon#first serial, iclass 5, count 0 2006.285.22:24:53.27#ibcon#enter sib2, iclass 5, count 0 2006.285.22:24:53.27#ibcon#flushed, iclass 5, count 0 2006.285.22:24:53.27#ibcon#about to write, iclass 5, count 0 2006.285.22:24:53.27#ibcon#wrote, iclass 5, count 0 2006.285.22:24:53.27#ibcon#about to read 3, iclass 5, count 0 2006.285.22:24:53.29#ibcon#read 3, iclass 5, count 0 2006.285.22:24:53.29#ibcon#about to read 4, iclass 5, count 0 2006.285.22:24:53.29#ibcon#read 4, iclass 5, count 0 2006.285.22:24:53.29#ibcon#about to read 5, iclass 5, count 0 2006.285.22:24:53.29#ibcon#read 5, iclass 5, count 0 2006.285.22:24:53.29#ibcon#about to read 6, iclass 5, count 0 2006.285.22:24:53.29#ibcon#read 6, iclass 5, count 0 2006.285.22:24:53.29#ibcon#end of sib2, iclass 5, count 0 2006.285.22:24:53.29#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:24:53.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:24:53.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.22:24:53.29#ibcon#*before write, iclass 5, count 0 2006.285.22:24:53.29#ibcon#enter sib2, iclass 5, count 0 2006.285.22:24:53.29#ibcon#flushed, iclass 5, count 0 2006.285.22:24:53.29#ibcon#about to write, iclass 5, count 0 2006.285.22:24:53.29#ibcon#wrote, iclass 5, count 0 2006.285.22:24:53.29#ibcon#about to read 3, iclass 5, count 0 2006.285.22:24:53.33#ibcon#read 3, iclass 5, count 0 2006.285.22:24:53.33#ibcon#about to read 4, iclass 5, count 0 2006.285.22:24:53.33#ibcon#read 4, iclass 5, count 0 2006.285.22:24:53.33#ibcon#about to read 5, iclass 5, count 0 2006.285.22:24:53.33#ibcon#read 5, iclass 5, count 0 2006.285.22:24:53.33#ibcon#about to read 6, iclass 5, count 0 2006.285.22:24:53.33#ibcon#read 6, iclass 5, count 0 2006.285.22:24:53.33#ibcon#end of sib2, iclass 5, count 0 2006.285.22:24:53.33#ibcon#*after write, iclass 5, count 0 2006.285.22:24:53.33#ibcon#*before return 0, iclass 5, count 0 2006.285.22:24:53.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:24:53.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:24:53.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:24:53.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:24:53.33$vck44/vb=7,4 2006.285.22:24:53.33#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.22:24:53.33#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.22:24:53.33#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:53.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:24:53.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:24:53.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:24:53.39#ibcon#enter wrdev, iclass 7, count 2 2006.285.22:24:53.39#ibcon#first serial, iclass 7, count 2 2006.285.22:24:53.39#ibcon#enter sib2, iclass 7, count 2 2006.285.22:24:53.39#ibcon#flushed, iclass 7, count 2 2006.285.22:24:53.39#ibcon#about to write, iclass 7, count 2 2006.285.22:24:53.39#ibcon#wrote, iclass 7, count 2 2006.285.22:24:53.39#ibcon#about to read 3, iclass 7, count 2 2006.285.22:24:53.41#ibcon#read 3, iclass 7, count 2 2006.285.22:24:53.41#ibcon#about to read 4, iclass 7, count 2 2006.285.22:24:53.41#ibcon#read 4, iclass 7, count 2 2006.285.22:24:53.41#ibcon#about to read 5, iclass 7, count 2 2006.285.22:24:53.41#ibcon#read 5, iclass 7, count 2 2006.285.22:24:53.41#ibcon#about to read 6, iclass 7, count 2 2006.285.22:24:53.41#ibcon#read 6, iclass 7, count 2 2006.285.22:24:53.41#ibcon#end of sib2, iclass 7, count 2 2006.285.22:24:53.41#ibcon#*mode == 0, iclass 7, count 2 2006.285.22:24:53.41#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.22:24:53.41#ibcon#[27=AT07-04\r\n] 2006.285.22:24:53.41#ibcon#*before write, iclass 7, count 2 2006.285.22:24:53.41#ibcon#enter sib2, iclass 7, count 2 2006.285.22:24:53.41#ibcon#flushed, iclass 7, count 2 2006.285.22:24:53.41#ibcon#about to write, iclass 7, count 2 2006.285.22:24:53.41#ibcon#wrote, iclass 7, count 2 2006.285.22:24:53.41#ibcon#about to read 3, iclass 7, count 2 2006.285.22:24:53.44#ibcon#read 3, iclass 7, count 2 2006.285.22:24:53.44#ibcon#about to read 4, iclass 7, count 2 2006.285.22:24:53.44#ibcon#read 4, iclass 7, count 2 2006.285.22:24:53.44#ibcon#about to read 5, iclass 7, count 2 2006.285.22:24:53.44#ibcon#read 5, iclass 7, count 2 2006.285.22:24:53.44#ibcon#about to read 6, iclass 7, count 2 2006.285.22:24:53.44#ibcon#read 6, iclass 7, count 2 2006.285.22:24:53.44#ibcon#end of sib2, iclass 7, count 2 2006.285.22:24:53.44#ibcon#*after write, iclass 7, count 2 2006.285.22:24:53.44#ibcon#*before return 0, iclass 7, count 2 2006.285.22:24:53.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:24:53.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:24:53.44#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.22:24:53.44#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:53.44#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:24:53.56#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:24:53.56#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:24:53.56#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:24:53.56#ibcon#first serial, iclass 7, count 0 2006.285.22:24:53.56#ibcon#enter sib2, iclass 7, count 0 2006.285.22:24:53.56#ibcon#flushed, iclass 7, count 0 2006.285.22:24:53.56#ibcon#about to write, iclass 7, count 0 2006.285.22:24:53.56#ibcon#wrote, iclass 7, count 0 2006.285.22:24:53.56#ibcon#about to read 3, iclass 7, count 0 2006.285.22:24:53.58#ibcon#read 3, iclass 7, count 0 2006.285.22:24:53.58#ibcon#about to read 4, iclass 7, count 0 2006.285.22:24:53.58#ibcon#read 4, iclass 7, count 0 2006.285.22:24:53.58#ibcon#about to read 5, iclass 7, count 0 2006.285.22:24:53.58#ibcon#read 5, iclass 7, count 0 2006.285.22:24:53.58#ibcon#about to read 6, iclass 7, count 0 2006.285.22:24:53.58#ibcon#read 6, iclass 7, count 0 2006.285.22:24:53.58#ibcon#end of sib2, iclass 7, count 0 2006.285.22:24:53.58#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:24:53.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:24:53.58#ibcon#[27=USB\r\n] 2006.285.22:24:53.58#ibcon#*before write, iclass 7, count 0 2006.285.22:24:53.58#ibcon#enter sib2, iclass 7, count 0 2006.285.22:24:53.58#ibcon#flushed, iclass 7, count 0 2006.285.22:24:53.58#ibcon#about to write, iclass 7, count 0 2006.285.22:24:53.58#ibcon#wrote, iclass 7, count 0 2006.285.22:24:53.58#ibcon#about to read 3, iclass 7, count 0 2006.285.22:24:53.61#ibcon#read 3, iclass 7, count 0 2006.285.22:24:53.61#ibcon#about to read 4, iclass 7, count 0 2006.285.22:24:53.61#ibcon#read 4, iclass 7, count 0 2006.285.22:24:53.61#ibcon#about to read 5, iclass 7, count 0 2006.285.22:24:53.61#ibcon#read 5, iclass 7, count 0 2006.285.22:24:53.61#ibcon#about to read 6, iclass 7, count 0 2006.285.22:24:53.61#ibcon#read 6, iclass 7, count 0 2006.285.22:24:53.61#ibcon#end of sib2, iclass 7, count 0 2006.285.22:24:53.61#ibcon#*after write, iclass 7, count 0 2006.285.22:24:53.61#ibcon#*before return 0, iclass 7, count 0 2006.285.22:24:53.61#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:24:53.61#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:24:53.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:24:53.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:24:53.61$vck44/vblo=8,744.99 2006.285.22:24:53.61#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.22:24:53.61#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.22:24:53.61#ibcon#ireg 17 cls_cnt 0 2006.285.22:24:53.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:24:53.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:24:53.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:24:53.61#ibcon#enter wrdev, iclass 11, count 0 2006.285.22:24:53.61#ibcon#first serial, iclass 11, count 0 2006.285.22:24:53.61#ibcon#enter sib2, iclass 11, count 0 2006.285.22:24:53.61#ibcon#flushed, iclass 11, count 0 2006.285.22:24:53.61#ibcon#about to write, iclass 11, count 0 2006.285.22:24:53.61#ibcon#wrote, iclass 11, count 0 2006.285.22:24:53.61#ibcon#about to read 3, iclass 11, count 0 2006.285.22:24:53.63#ibcon#read 3, iclass 11, count 0 2006.285.22:24:53.63#ibcon#about to read 4, iclass 11, count 0 2006.285.22:24:53.63#ibcon#read 4, iclass 11, count 0 2006.285.22:24:53.63#ibcon#about to read 5, iclass 11, count 0 2006.285.22:24:53.63#ibcon#read 5, iclass 11, count 0 2006.285.22:24:53.63#ibcon#about to read 6, iclass 11, count 0 2006.285.22:24:53.63#ibcon#read 6, iclass 11, count 0 2006.285.22:24:53.63#ibcon#end of sib2, iclass 11, count 0 2006.285.22:24:53.63#ibcon#*mode == 0, iclass 11, count 0 2006.285.22:24:53.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.22:24:53.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.22:24:53.63#ibcon#*before write, iclass 11, count 0 2006.285.22:24:53.63#ibcon#enter sib2, iclass 11, count 0 2006.285.22:24:53.63#ibcon#flushed, iclass 11, count 0 2006.285.22:24:53.63#ibcon#about to write, iclass 11, count 0 2006.285.22:24:53.63#ibcon#wrote, iclass 11, count 0 2006.285.22:24:53.63#ibcon#about to read 3, iclass 11, count 0 2006.285.22:24:53.67#ibcon#read 3, iclass 11, count 0 2006.285.22:24:53.67#ibcon#about to read 4, iclass 11, count 0 2006.285.22:24:53.67#ibcon#read 4, iclass 11, count 0 2006.285.22:24:53.67#ibcon#about to read 5, iclass 11, count 0 2006.285.22:24:53.67#ibcon#read 5, iclass 11, count 0 2006.285.22:24:53.67#ibcon#about to read 6, iclass 11, count 0 2006.285.22:24:53.67#ibcon#read 6, iclass 11, count 0 2006.285.22:24:53.67#ibcon#end of sib2, iclass 11, count 0 2006.285.22:24:53.67#ibcon#*after write, iclass 11, count 0 2006.285.22:24:53.67#ibcon#*before return 0, iclass 11, count 0 2006.285.22:24:53.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:24:53.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:24:53.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.22:24:53.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.22:24:53.67$vck44/vb=8,4 2006.285.22:24:53.67#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.22:24:53.67#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.22:24:53.67#ibcon#ireg 11 cls_cnt 2 2006.285.22:24:53.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:24:53.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:24:53.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:24:53.73#ibcon#enter wrdev, iclass 13, count 2 2006.285.22:24:53.73#ibcon#first serial, iclass 13, count 2 2006.285.22:24:53.73#ibcon#enter sib2, iclass 13, count 2 2006.285.22:24:53.73#ibcon#flushed, iclass 13, count 2 2006.285.22:24:53.73#ibcon#about to write, iclass 13, count 2 2006.285.22:24:53.73#ibcon#wrote, iclass 13, count 2 2006.285.22:24:53.73#ibcon#about to read 3, iclass 13, count 2 2006.285.22:24:53.75#ibcon#read 3, iclass 13, count 2 2006.285.22:24:53.75#ibcon#about to read 4, iclass 13, count 2 2006.285.22:24:53.75#ibcon#read 4, iclass 13, count 2 2006.285.22:24:53.75#ibcon#about to read 5, iclass 13, count 2 2006.285.22:24:53.75#ibcon#read 5, iclass 13, count 2 2006.285.22:24:53.75#ibcon#about to read 6, iclass 13, count 2 2006.285.22:24:53.75#ibcon#read 6, iclass 13, count 2 2006.285.22:24:53.75#ibcon#end of sib2, iclass 13, count 2 2006.285.22:24:53.75#ibcon#*mode == 0, iclass 13, count 2 2006.285.22:24:53.75#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.22:24:53.75#ibcon#[27=AT08-04\r\n] 2006.285.22:24:53.75#ibcon#*before write, iclass 13, count 2 2006.285.22:24:53.75#ibcon#enter sib2, iclass 13, count 2 2006.285.22:24:53.75#ibcon#flushed, iclass 13, count 2 2006.285.22:24:53.75#ibcon#about to write, iclass 13, count 2 2006.285.22:24:53.75#ibcon#wrote, iclass 13, count 2 2006.285.22:24:53.75#ibcon#about to read 3, iclass 13, count 2 2006.285.22:24:53.78#ibcon#read 3, iclass 13, count 2 2006.285.22:24:53.78#ibcon#about to read 4, iclass 13, count 2 2006.285.22:24:53.78#ibcon#read 4, iclass 13, count 2 2006.285.22:24:53.78#ibcon#about to read 5, iclass 13, count 2 2006.285.22:24:53.78#ibcon#read 5, iclass 13, count 2 2006.285.22:24:53.78#ibcon#about to read 6, iclass 13, count 2 2006.285.22:24:53.78#ibcon#read 6, iclass 13, count 2 2006.285.22:24:53.78#ibcon#end of sib2, iclass 13, count 2 2006.285.22:24:53.78#ibcon#*after write, iclass 13, count 2 2006.285.22:24:53.78#ibcon#*before return 0, iclass 13, count 2 2006.285.22:24:53.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:24:53.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:24:53.78#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.22:24:53.78#ibcon#ireg 7 cls_cnt 0 2006.285.22:24:53.78#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:24:53.90#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:24:53.90#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:24:53.90#ibcon#enter wrdev, iclass 13, count 0 2006.285.22:24:53.90#ibcon#first serial, iclass 13, count 0 2006.285.22:24:53.90#ibcon#enter sib2, iclass 13, count 0 2006.285.22:24:53.90#ibcon#flushed, iclass 13, count 0 2006.285.22:24:53.90#ibcon#about to write, iclass 13, count 0 2006.285.22:24:53.90#ibcon#wrote, iclass 13, count 0 2006.285.22:24:53.90#ibcon#about to read 3, iclass 13, count 0 2006.285.22:24:53.92#ibcon#read 3, iclass 13, count 0 2006.285.22:24:53.92#ibcon#about to read 4, iclass 13, count 0 2006.285.22:24:53.92#ibcon#read 4, iclass 13, count 0 2006.285.22:24:53.92#ibcon#about to read 5, iclass 13, count 0 2006.285.22:24:53.92#ibcon#read 5, iclass 13, count 0 2006.285.22:24:53.92#ibcon#about to read 6, iclass 13, count 0 2006.285.22:24:53.92#ibcon#read 6, iclass 13, count 0 2006.285.22:24:53.92#ibcon#end of sib2, iclass 13, count 0 2006.285.22:24:53.92#ibcon#*mode == 0, iclass 13, count 0 2006.285.22:24:53.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.22:24:53.92#ibcon#[27=USB\r\n] 2006.285.22:24:53.92#ibcon#*before write, iclass 13, count 0 2006.285.22:24:53.92#ibcon#enter sib2, iclass 13, count 0 2006.285.22:24:53.92#ibcon#flushed, iclass 13, count 0 2006.285.22:24:53.92#ibcon#about to write, iclass 13, count 0 2006.285.22:24:53.92#ibcon#wrote, iclass 13, count 0 2006.285.22:24:53.92#ibcon#about to read 3, iclass 13, count 0 2006.285.22:24:53.95#ibcon#read 3, iclass 13, count 0 2006.285.22:24:53.95#ibcon#about to read 4, iclass 13, count 0 2006.285.22:24:53.95#ibcon#read 4, iclass 13, count 0 2006.285.22:24:53.95#ibcon#about to read 5, iclass 13, count 0 2006.285.22:24:53.95#ibcon#read 5, iclass 13, count 0 2006.285.22:24:53.95#ibcon#about to read 6, iclass 13, count 0 2006.285.22:24:53.95#ibcon#read 6, iclass 13, count 0 2006.285.22:24:53.95#ibcon#end of sib2, iclass 13, count 0 2006.285.22:24:53.95#ibcon#*after write, iclass 13, count 0 2006.285.22:24:53.95#ibcon#*before return 0, iclass 13, count 0 2006.285.22:24:53.95#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:24:53.95#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:24:53.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.22:24:53.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.22:24:53.95$vck44/vabw=wide 2006.285.22:24:53.95#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.22:24:53.95#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.22:24:53.95#ibcon#ireg 8 cls_cnt 0 2006.285.22:24:53.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:24:53.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:24:53.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:24:53.95#ibcon#enter wrdev, iclass 15, count 0 2006.285.22:24:53.95#ibcon#first serial, iclass 15, count 0 2006.285.22:24:53.95#ibcon#enter sib2, iclass 15, count 0 2006.285.22:24:53.95#ibcon#flushed, iclass 15, count 0 2006.285.22:24:53.95#ibcon#about to write, iclass 15, count 0 2006.285.22:24:53.95#ibcon#wrote, iclass 15, count 0 2006.285.22:24:53.95#ibcon#about to read 3, iclass 15, count 0 2006.285.22:24:53.97#ibcon#read 3, iclass 15, count 0 2006.285.22:24:53.97#ibcon#about to read 4, iclass 15, count 0 2006.285.22:24:53.97#ibcon#read 4, iclass 15, count 0 2006.285.22:24:53.97#ibcon#about to read 5, iclass 15, count 0 2006.285.22:24:53.97#ibcon#read 5, iclass 15, count 0 2006.285.22:24:53.97#ibcon#about to read 6, iclass 15, count 0 2006.285.22:24:53.97#ibcon#read 6, iclass 15, count 0 2006.285.22:24:53.97#ibcon#end of sib2, iclass 15, count 0 2006.285.22:24:53.97#ibcon#*mode == 0, iclass 15, count 0 2006.285.22:24:53.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.22:24:53.97#ibcon#[25=BW32\r\n] 2006.285.22:24:53.97#ibcon#*before write, iclass 15, count 0 2006.285.22:24:53.97#ibcon#enter sib2, iclass 15, count 0 2006.285.22:24:53.97#ibcon#flushed, iclass 15, count 0 2006.285.22:24:53.97#ibcon#about to write, iclass 15, count 0 2006.285.22:24:53.97#ibcon#wrote, iclass 15, count 0 2006.285.22:24:53.97#ibcon#about to read 3, iclass 15, count 0 2006.285.22:24:54.00#ibcon#read 3, iclass 15, count 0 2006.285.22:24:54.00#ibcon#about to read 4, iclass 15, count 0 2006.285.22:24:54.00#ibcon#read 4, iclass 15, count 0 2006.285.22:24:54.00#ibcon#about to read 5, iclass 15, count 0 2006.285.22:24:54.00#ibcon#read 5, iclass 15, count 0 2006.285.22:24:54.00#ibcon#about to read 6, iclass 15, count 0 2006.285.22:24:54.00#ibcon#read 6, iclass 15, count 0 2006.285.22:24:54.00#ibcon#end of sib2, iclass 15, count 0 2006.285.22:24:54.00#ibcon#*after write, iclass 15, count 0 2006.285.22:24:54.00#ibcon#*before return 0, iclass 15, count 0 2006.285.22:24:54.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:24:54.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:24:54.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.22:24:54.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.22:24:54.00$vck44/vbbw=wide 2006.285.22:24:54.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.22:24:54.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.22:24:54.00#ibcon#ireg 8 cls_cnt 0 2006.285.22:24:54.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:24:54.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:24:54.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:24:54.07#ibcon#enter wrdev, iclass 17, count 0 2006.285.22:24:54.07#ibcon#first serial, iclass 17, count 0 2006.285.22:24:54.07#ibcon#enter sib2, iclass 17, count 0 2006.285.22:24:54.07#ibcon#flushed, iclass 17, count 0 2006.285.22:24:54.07#ibcon#about to write, iclass 17, count 0 2006.285.22:24:54.07#ibcon#wrote, iclass 17, count 0 2006.285.22:24:54.07#ibcon#about to read 3, iclass 17, count 0 2006.285.22:24:54.09#ibcon#read 3, iclass 17, count 0 2006.285.22:24:54.09#ibcon#about to read 4, iclass 17, count 0 2006.285.22:24:54.09#ibcon#read 4, iclass 17, count 0 2006.285.22:24:54.09#ibcon#about to read 5, iclass 17, count 0 2006.285.22:24:54.09#ibcon#read 5, iclass 17, count 0 2006.285.22:24:54.09#ibcon#about to read 6, iclass 17, count 0 2006.285.22:24:54.09#ibcon#read 6, iclass 17, count 0 2006.285.22:24:54.09#ibcon#end of sib2, iclass 17, count 0 2006.285.22:24:54.09#ibcon#*mode == 0, iclass 17, count 0 2006.285.22:24:54.09#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.22:24:54.09#ibcon#[27=BW32\r\n] 2006.285.22:24:54.09#ibcon#*before write, iclass 17, count 0 2006.285.22:24:54.09#ibcon#enter sib2, iclass 17, count 0 2006.285.22:24:54.09#ibcon#flushed, iclass 17, count 0 2006.285.22:24:54.09#ibcon#about to write, iclass 17, count 0 2006.285.22:24:54.09#ibcon#wrote, iclass 17, count 0 2006.285.22:24:54.09#ibcon#about to read 3, iclass 17, count 0 2006.285.22:24:54.12#ibcon#read 3, iclass 17, count 0 2006.285.22:24:54.12#ibcon#about to read 4, iclass 17, count 0 2006.285.22:24:54.12#ibcon#read 4, iclass 17, count 0 2006.285.22:24:54.12#ibcon#about to read 5, iclass 17, count 0 2006.285.22:24:54.12#ibcon#read 5, iclass 17, count 0 2006.285.22:24:54.12#ibcon#about to read 6, iclass 17, count 0 2006.285.22:24:54.12#ibcon#read 6, iclass 17, count 0 2006.285.22:24:54.12#ibcon#end of sib2, iclass 17, count 0 2006.285.22:24:54.12#ibcon#*after write, iclass 17, count 0 2006.285.22:24:54.12#ibcon#*before return 0, iclass 17, count 0 2006.285.22:24:54.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:24:54.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:24:54.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.22:24:54.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.22:24:54.12$setupk4/ifdk4 2006.285.22:24:54.12$ifdk4/lo= 2006.285.22:24:54.12$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.22:24:54.12$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.22:24:54.12$ifdk4/patch= 2006.285.22:24:54.12$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.22:24:54.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.22:24:54.12$setupk4/!*+20s 2006.285.22:24:59.53#abcon#<5=/00 0.2 1.0 16.65 991016.1\r\n> 2006.285.22:24:59.55#abcon#{5=INTERFACE CLEAR} 2006.285.22:24:59.61#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:25:08.63$setupk4/"tpicd 2006.285.22:25:08.63$setupk4/echo=off 2006.285.22:25:08.63$setupk4/xlog=off 2006.285.22:25:08.63:!2006.285.22:26:17 2006.285.22:25:16.13#trakl#Source acquired 2006.285.22:25:18.13#flagr#flagr/antenna,acquired 2006.285.22:26:17.00:preob 2006.285.22:26:17.13/onsource/TRACKING 2006.285.22:26:17.13:!2006.285.22:26:27 2006.285.22:26:27.00:"tape 2006.285.22:26:27.00:"st=record 2006.285.22:26:27.00:data_valid=on 2006.285.22:26:27.00:midob 2006.285.22:26:27.13/onsource/TRACKING 2006.285.22:26:27.13/wx/16.70,1016.1,98 2006.285.22:26:27.28/cable/+6.5100E-03 2006.285.22:26:28.37/va/01,07,usb,yes,38,41 2006.285.22:26:28.37/va/02,06,usb,yes,39,39 2006.285.22:26:28.37/va/03,07,usb,yes,38,40 2006.285.22:26:28.37/va/04,06,usb,yes,40,42 2006.285.22:26:28.37/va/05,03,usb,yes,39,40 2006.285.22:26:28.37/va/06,04,usb,yes,36,35 2006.285.22:26:28.37/va/07,04,usb,yes,36,37 2006.285.22:26:28.37/va/08,03,usb,yes,37,45 2006.285.22:26:28.60/valo/01,524.99,yes,locked 2006.285.22:26:28.60/valo/02,534.99,yes,locked 2006.285.22:26:28.60/valo/03,564.99,yes,locked 2006.285.22:26:28.60/valo/04,624.99,yes,locked 2006.285.22:26:28.60/valo/05,734.99,yes,locked 2006.285.22:26:28.60/valo/06,814.99,yes,locked 2006.285.22:26:28.60/valo/07,864.99,yes,locked 2006.285.22:26:28.60/valo/08,884.99,yes,locked 2006.285.22:26:29.69/vb/01,04,usb,yes,34,32 2006.285.22:26:29.69/vb/02,05,usb,yes,32,32 2006.285.22:26:29.69/vb/03,04,usb,yes,33,37 2006.285.22:26:29.69/vb/04,05,usb,yes,34,32 2006.285.22:26:29.69/vb/05,04,usb,yes,30,33 2006.285.22:26:29.69/vb/06,03,usb,yes,43,38 2006.285.22:26:29.69/vb/07,04,usb,yes,35,35 2006.285.22:26:29.69/vb/08,04,usb,yes,32,35 2006.285.22:26:29.92/vblo/01,629.99,yes,locked 2006.285.22:26:29.92/vblo/02,634.99,yes,locked 2006.285.22:26:29.92/vblo/03,649.99,yes,locked 2006.285.22:26:29.92/vblo/04,679.99,yes,locked 2006.285.22:26:29.92/vblo/05,709.99,yes,locked 2006.285.22:26:29.92/vblo/06,719.99,yes,locked 2006.285.22:26:29.92/vblo/07,734.99,yes,locked 2006.285.22:26:29.92/vblo/08,744.99,yes,locked 2006.285.22:26:30.07/vabw/8 2006.285.22:26:30.22/vbbw/8 2006.285.22:26:30.34/xfe/off,on,12.0 2006.285.22:26:30.72/ifatt/23,28,28,28 2006.285.22:26:31.07/fmout-gps/S +2.60E-07 2006.285.22:26:31.09:!2006.285.22:28:17 2006.285.22:28:17.02:data_valid=off 2006.285.22:28:17.02:"et 2006.285.22:28:17.02:!+3s 2006.285.22:28:20.04:"tape 2006.285.22:28:20.05:postob 2006.285.22:28:20.15/cable/+6.5088E-03 2006.285.22:28:20.15/wx/16.75,1016.1,98 2006.285.22:28:20.21/fmout-gps/S +2.59E-07 2006.285.22:28:20.21:scan_name=285-2231,jd0610,50 2006.285.22:28:20.21:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.285.22:28:21.14#flagr#flagr/antenna,new-source 2006.285.22:28:21.14:checkk5 2006.285.22:28:21.68/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:28:22.09/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:28:22.47/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:28:22.82/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:28:23.21/chk_obsdata//k5ts1/T2852226??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.22:28:23.57/chk_obsdata//k5ts2/T2852226??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.22:28:23.95/chk_obsdata//k5ts3/T2852226??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.22:28:24.56/chk_obsdata//k5ts4/T2852226??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.22:28:25.33/k5log//k5ts1_log_newline 2006.285.22:28:26.13/k5log//k5ts2_log_newline 2006.285.22:28:27.11/k5log//k5ts3_log_newline 2006.285.22:28:27.92/k5log//k5ts4_log_newline 2006.285.22:28:27.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:28:27.94:setupk4=1 2006.285.22:28:27.94$setupk4/echo=on 2006.285.22:28:27.94$setupk4/pcalon 2006.285.22:28:27.94$pcalon/"no phase cal control is implemented here 2006.285.22:28:27.94$setupk4/"tpicd=stop 2006.285.22:28:27.94$setupk4/"rec=synch_on 2006.285.22:28:27.94$setupk4/"rec_mode=128 2006.285.22:28:27.94$setupk4/!* 2006.285.22:28:27.94$setupk4/recpk4 2006.285.22:28:27.94$recpk4/recpatch= 2006.285.22:28:27.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:28:27.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:28:27.94$setupk4/vck44 2006.285.22:28:27.94$vck44/valo=1,524.99 2006.285.22:28:27.94#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.22:28:27.94#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.22:28:27.94#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:27.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:28:27.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:28:27.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:28:27.94#ibcon#enter wrdev, iclass 34, count 0 2006.285.22:28:27.94#ibcon#first serial, iclass 34, count 0 2006.285.22:28:27.94#ibcon#enter sib2, iclass 34, count 0 2006.285.22:28:27.94#ibcon#flushed, iclass 34, count 0 2006.285.22:28:27.94#ibcon#about to write, iclass 34, count 0 2006.285.22:28:27.94#ibcon#wrote, iclass 34, count 0 2006.285.22:28:27.94#ibcon#about to read 3, iclass 34, count 0 2006.285.22:28:27.96#ibcon#read 3, iclass 34, count 0 2006.285.22:28:27.97#ibcon#about to read 4, iclass 34, count 0 2006.285.22:28:27.97#ibcon#read 4, iclass 34, count 0 2006.285.22:28:27.97#ibcon#about to read 5, iclass 34, count 0 2006.285.22:28:27.97#ibcon#read 5, iclass 34, count 0 2006.285.22:28:27.97#ibcon#about to read 6, iclass 34, count 0 2006.285.22:28:27.97#ibcon#read 6, iclass 34, count 0 2006.285.22:28:27.97#ibcon#end of sib2, iclass 34, count 0 2006.285.22:28:27.97#ibcon#*mode == 0, iclass 34, count 0 2006.285.22:28:27.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.22:28:27.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:28:27.97#ibcon#*before write, iclass 34, count 0 2006.285.22:28:27.97#ibcon#enter sib2, iclass 34, count 0 2006.285.22:28:27.97#ibcon#flushed, iclass 34, count 0 2006.285.22:28:27.97#ibcon#about to write, iclass 34, count 0 2006.285.22:28:27.97#ibcon#wrote, iclass 34, count 0 2006.285.22:28:27.97#ibcon#about to read 3, iclass 34, count 0 2006.285.22:28:28.02#ibcon#read 3, iclass 34, count 0 2006.285.22:28:28.02#ibcon#about to read 4, iclass 34, count 0 2006.285.22:28:28.02#ibcon#read 4, iclass 34, count 0 2006.285.22:28:28.02#ibcon#about to read 5, iclass 34, count 0 2006.285.22:28:28.02#ibcon#read 5, iclass 34, count 0 2006.285.22:28:28.02#ibcon#about to read 6, iclass 34, count 0 2006.285.22:28:28.02#ibcon#read 6, iclass 34, count 0 2006.285.22:28:28.02#ibcon#end of sib2, iclass 34, count 0 2006.285.22:28:28.02#ibcon#*after write, iclass 34, count 0 2006.285.22:28:28.02#ibcon#*before return 0, iclass 34, count 0 2006.285.22:28:28.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:28:28.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:28:28.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.22:28:28.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.22:28:28.02$vck44/va=1,7 2006.285.22:28:28.02#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.22:28:28.02#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.22:28:28.02#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:28.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:28:28.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:28:28.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:28:28.02#ibcon#enter wrdev, iclass 36, count 2 2006.285.22:28:28.02#ibcon#first serial, iclass 36, count 2 2006.285.22:28:28.02#ibcon#enter sib2, iclass 36, count 2 2006.285.22:28:28.02#ibcon#flushed, iclass 36, count 2 2006.285.22:28:28.02#ibcon#about to write, iclass 36, count 2 2006.285.22:28:28.02#ibcon#wrote, iclass 36, count 2 2006.285.22:28:28.02#ibcon#about to read 3, iclass 36, count 2 2006.285.22:28:28.03#ibcon#read 3, iclass 36, count 2 2006.285.22:28:28.03#ibcon#about to read 4, iclass 36, count 2 2006.285.22:28:28.03#ibcon#read 4, iclass 36, count 2 2006.285.22:28:28.03#ibcon#about to read 5, iclass 36, count 2 2006.285.22:28:28.03#ibcon#read 5, iclass 36, count 2 2006.285.22:28:28.03#ibcon#about to read 6, iclass 36, count 2 2006.285.22:28:28.03#ibcon#read 6, iclass 36, count 2 2006.285.22:28:28.03#ibcon#end of sib2, iclass 36, count 2 2006.285.22:28:28.03#ibcon#*mode == 0, iclass 36, count 2 2006.285.22:28:28.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.22:28:28.04#ibcon#[25=AT01-07\r\n] 2006.285.22:28:28.04#ibcon#*before write, iclass 36, count 2 2006.285.22:28:28.04#ibcon#enter sib2, iclass 36, count 2 2006.285.22:28:28.04#ibcon#flushed, iclass 36, count 2 2006.285.22:28:28.04#ibcon#about to write, iclass 36, count 2 2006.285.22:28:28.04#ibcon#wrote, iclass 36, count 2 2006.285.22:28:28.04#ibcon#about to read 3, iclass 36, count 2 2006.285.22:28:28.06#ibcon#read 3, iclass 36, count 2 2006.285.22:28:28.06#ibcon#about to read 4, iclass 36, count 2 2006.285.22:28:28.06#ibcon#read 4, iclass 36, count 2 2006.285.22:28:28.06#ibcon#about to read 5, iclass 36, count 2 2006.285.22:28:28.06#ibcon#read 5, iclass 36, count 2 2006.285.22:28:28.06#ibcon#about to read 6, iclass 36, count 2 2006.285.22:28:28.06#ibcon#read 6, iclass 36, count 2 2006.285.22:28:28.07#ibcon#end of sib2, iclass 36, count 2 2006.285.22:28:28.07#ibcon#*after write, iclass 36, count 2 2006.285.22:28:28.07#ibcon#*before return 0, iclass 36, count 2 2006.285.22:28:28.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:28:28.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:28:28.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.22:28:28.07#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:28.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:28:28.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:28:28.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:28:28.19#ibcon#enter wrdev, iclass 36, count 0 2006.285.22:28:28.19#ibcon#first serial, iclass 36, count 0 2006.285.22:28:28.19#ibcon#enter sib2, iclass 36, count 0 2006.285.22:28:28.19#ibcon#flushed, iclass 36, count 0 2006.285.22:28:28.19#ibcon#about to write, iclass 36, count 0 2006.285.22:28:28.19#ibcon#wrote, iclass 36, count 0 2006.285.22:28:28.19#ibcon#about to read 3, iclass 36, count 0 2006.285.22:28:28.20#ibcon#read 3, iclass 36, count 0 2006.285.22:28:28.20#ibcon#about to read 4, iclass 36, count 0 2006.285.22:28:28.20#ibcon#read 4, iclass 36, count 0 2006.285.22:28:28.20#ibcon#about to read 5, iclass 36, count 0 2006.285.22:28:28.20#ibcon#read 5, iclass 36, count 0 2006.285.22:28:28.20#ibcon#about to read 6, iclass 36, count 0 2006.285.22:28:28.20#ibcon#read 6, iclass 36, count 0 2006.285.22:28:28.21#ibcon#end of sib2, iclass 36, count 0 2006.285.22:28:28.21#ibcon#*mode == 0, iclass 36, count 0 2006.285.22:28:28.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.22:28:28.21#ibcon#[25=USB\r\n] 2006.285.22:28:28.21#ibcon#*before write, iclass 36, count 0 2006.285.22:28:28.21#ibcon#enter sib2, iclass 36, count 0 2006.285.22:28:28.21#ibcon#flushed, iclass 36, count 0 2006.285.22:28:28.21#ibcon#about to write, iclass 36, count 0 2006.285.22:28:28.21#ibcon#wrote, iclass 36, count 0 2006.285.22:28:28.21#ibcon#about to read 3, iclass 36, count 0 2006.285.22:28:28.23#ibcon#read 3, iclass 36, count 0 2006.285.22:28:28.23#ibcon#about to read 4, iclass 36, count 0 2006.285.22:28:28.23#ibcon#read 4, iclass 36, count 0 2006.285.22:28:28.23#ibcon#about to read 5, iclass 36, count 0 2006.285.22:28:28.23#ibcon#read 5, iclass 36, count 0 2006.285.22:28:28.23#ibcon#about to read 6, iclass 36, count 0 2006.285.22:28:28.23#ibcon#read 6, iclass 36, count 0 2006.285.22:28:28.23#ibcon#end of sib2, iclass 36, count 0 2006.285.22:28:28.23#ibcon#*after write, iclass 36, count 0 2006.285.22:28:28.24#ibcon#*before return 0, iclass 36, count 0 2006.285.22:28:28.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:28:28.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:28:28.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.22:28:28.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.22:28:28.24$vck44/valo=2,534.99 2006.285.22:28:28.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.22:28:28.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.22:28:28.24#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:28.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:28:28.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:28:28.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:28:28.24#ibcon#enter wrdev, iclass 38, count 0 2006.285.22:28:28.24#ibcon#first serial, iclass 38, count 0 2006.285.22:28:28.24#ibcon#enter sib2, iclass 38, count 0 2006.285.22:28:28.24#ibcon#flushed, iclass 38, count 0 2006.285.22:28:28.24#ibcon#about to write, iclass 38, count 0 2006.285.22:28:28.24#ibcon#wrote, iclass 38, count 0 2006.285.22:28:28.24#ibcon#about to read 3, iclass 38, count 0 2006.285.22:28:28.25#ibcon#read 3, iclass 38, count 0 2006.285.22:28:28.25#ibcon#about to read 4, iclass 38, count 0 2006.285.22:28:28.25#ibcon#read 4, iclass 38, count 0 2006.285.22:28:28.25#ibcon#about to read 5, iclass 38, count 0 2006.285.22:28:28.25#ibcon#read 5, iclass 38, count 0 2006.285.22:28:28.25#ibcon#about to read 6, iclass 38, count 0 2006.285.22:28:28.25#ibcon#read 6, iclass 38, count 0 2006.285.22:28:28.25#ibcon#end of sib2, iclass 38, count 0 2006.285.22:28:28.25#ibcon#*mode == 0, iclass 38, count 0 2006.285.22:28:28.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.22:28:28.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:28:28.26#ibcon#*before write, iclass 38, count 0 2006.285.22:28:28.26#ibcon#enter sib2, iclass 38, count 0 2006.285.22:28:28.26#ibcon#flushed, iclass 38, count 0 2006.285.22:28:28.26#ibcon#about to write, iclass 38, count 0 2006.285.22:28:28.26#ibcon#wrote, iclass 38, count 0 2006.285.22:28:28.26#ibcon#about to read 3, iclass 38, count 0 2006.285.22:28:28.29#ibcon#read 3, iclass 38, count 0 2006.285.22:28:28.29#ibcon#about to read 4, iclass 38, count 0 2006.285.22:28:28.29#ibcon#read 4, iclass 38, count 0 2006.285.22:28:28.29#ibcon#about to read 5, iclass 38, count 0 2006.285.22:28:28.29#ibcon#read 5, iclass 38, count 0 2006.285.22:28:28.29#ibcon#about to read 6, iclass 38, count 0 2006.285.22:28:28.29#ibcon#read 6, iclass 38, count 0 2006.285.22:28:28.29#ibcon#end of sib2, iclass 38, count 0 2006.285.22:28:28.29#ibcon#*after write, iclass 38, count 0 2006.285.22:28:28.30#ibcon#*before return 0, iclass 38, count 0 2006.285.22:28:28.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:28:28.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:28:28.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.22:28:28.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.22:28:28.30$vck44/va=2,6 2006.285.22:28:28.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.22:28:28.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.22:28:28.30#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:28.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:28:28.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:28:28.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:28:28.35#ibcon#enter wrdev, iclass 40, count 2 2006.285.22:28:28.35#ibcon#first serial, iclass 40, count 2 2006.285.22:28:28.35#ibcon#enter sib2, iclass 40, count 2 2006.285.22:28:28.35#ibcon#flushed, iclass 40, count 2 2006.285.22:28:28.35#ibcon#about to write, iclass 40, count 2 2006.285.22:28:28.35#ibcon#wrote, iclass 40, count 2 2006.285.22:28:28.35#ibcon#about to read 3, iclass 40, count 2 2006.285.22:28:28.40#ibcon#read 3, iclass 40, count 2 2006.285.22:28:28.40#ibcon#about to read 4, iclass 40, count 2 2006.285.22:28:28.40#ibcon#read 4, iclass 40, count 2 2006.285.22:28:28.40#ibcon#about to read 5, iclass 40, count 2 2006.285.22:28:28.40#ibcon#read 5, iclass 40, count 2 2006.285.22:28:28.40#ibcon#about to read 6, iclass 40, count 2 2006.285.22:28:28.40#ibcon#read 6, iclass 40, count 2 2006.285.22:28:28.40#ibcon#end of sib2, iclass 40, count 2 2006.285.22:28:28.40#ibcon#*mode == 0, iclass 40, count 2 2006.285.22:28:28.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.22:28:28.40#ibcon#[25=AT02-06\r\n] 2006.285.22:28:28.40#ibcon#*before write, iclass 40, count 2 2006.285.22:28:28.40#ibcon#enter sib2, iclass 40, count 2 2006.285.22:28:28.40#ibcon#flushed, iclass 40, count 2 2006.285.22:28:28.40#ibcon#about to write, iclass 40, count 2 2006.285.22:28:28.40#ibcon#wrote, iclass 40, count 2 2006.285.22:28:28.40#ibcon#about to read 3, iclass 40, count 2 2006.285.22:28:28.42#ibcon#read 3, iclass 40, count 2 2006.285.22:28:28.43#ibcon#about to read 4, iclass 40, count 2 2006.285.22:28:28.43#ibcon#read 4, iclass 40, count 2 2006.285.22:28:28.43#ibcon#about to read 5, iclass 40, count 2 2006.285.22:28:28.43#ibcon#read 5, iclass 40, count 2 2006.285.22:28:28.43#ibcon#about to read 6, iclass 40, count 2 2006.285.22:28:28.43#ibcon#read 6, iclass 40, count 2 2006.285.22:28:28.43#ibcon#end of sib2, iclass 40, count 2 2006.285.22:28:28.43#ibcon#*after write, iclass 40, count 2 2006.285.22:28:28.43#ibcon#*before return 0, iclass 40, count 2 2006.285.22:28:28.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:28:28.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:28:28.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.22:28:28.43#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:28.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:28:28.54#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:28:28.54#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:28:28.54#ibcon#enter wrdev, iclass 40, count 0 2006.285.22:28:28.54#ibcon#first serial, iclass 40, count 0 2006.285.22:28:28.54#ibcon#enter sib2, iclass 40, count 0 2006.285.22:28:28.54#ibcon#flushed, iclass 40, count 0 2006.285.22:28:28.54#ibcon#about to write, iclass 40, count 0 2006.285.22:28:28.55#ibcon#wrote, iclass 40, count 0 2006.285.22:28:28.55#ibcon#about to read 3, iclass 40, count 0 2006.285.22:28:28.56#ibcon#read 3, iclass 40, count 0 2006.285.22:28:28.56#ibcon#about to read 4, iclass 40, count 0 2006.285.22:28:28.56#ibcon#read 4, iclass 40, count 0 2006.285.22:28:28.56#ibcon#about to read 5, iclass 40, count 0 2006.285.22:28:28.56#ibcon#read 5, iclass 40, count 0 2006.285.22:28:28.56#ibcon#about to read 6, iclass 40, count 0 2006.285.22:28:28.56#ibcon#read 6, iclass 40, count 0 2006.285.22:28:28.57#ibcon#end of sib2, iclass 40, count 0 2006.285.22:28:28.57#ibcon#*mode == 0, iclass 40, count 0 2006.285.22:28:28.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.22:28:28.57#ibcon#[25=USB\r\n] 2006.285.22:28:28.57#ibcon#*before write, iclass 40, count 0 2006.285.22:28:28.57#ibcon#enter sib2, iclass 40, count 0 2006.285.22:28:28.57#ibcon#flushed, iclass 40, count 0 2006.285.22:28:28.57#ibcon#about to write, iclass 40, count 0 2006.285.22:28:28.57#ibcon#wrote, iclass 40, count 0 2006.285.22:28:28.57#ibcon#about to read 3, iclass 40, count 0 2006.285.22:28:28.59#ibcon#read 3, iclass 40, count 0 2006.285.22:28:28.59#ibcon#about to read 4, iclass 40, count 0 2006.285.22:28:28.59#ibcon#read 4, iclass 40, count 0 2006.285.22:28:28.59#ibcon#about to read 5, iclass 40, count 0 2006.285.22:28:28.59#ibcon#read 5, iclass 40, count 0 2006.285.22:28:28.59#ibcon#about to read 6, iclass 40, count 0 2006.285.22:28:28.59#ibcon#read 6, iclass 40, count 0 2006.285.22:28:28.60#ibcon#end of sib2, iclass 40, count 0 2006.285.22:28:28.60#ibcon#*after write, iclass 40, count 0 2006.285.22:28:28.60#ibcon#*before return 0, iclass 40, count 0 2006.285.22:28:28.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:28:28.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:28:28.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.22:28:28.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.22:28:28.60$vck44/valo=3,564.99 2006.285.22:28:28.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.22:28:28.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.22:28:28.60#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:28.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:28:28.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:28:28.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:28:28.60#ibcon#enter wrdev, iclass 4, count 0 2006.285.22:28:28.60#ibcon#first serial, iclass 4, count 0 2006.285.22:28:28.60#ibcon#enter sib2, iclass 4, count 0 2006.285.22:28:28.60#ibcon#flushed, iclass 4, count 0 2006.285.22:28:28.60#ibcon#about to write, iclass 4, count 0 2006.285.22:28:28.60#ibcon#wrote, iclass 4, count 0 2006.285.22:28:28.60#ibcon#about to read 3, iclass 4, count 0 2006.285.22:28:28.61#ibcon#read 3, iclass 4, count 0 2006.285.22:28:28.61#ibcon#about to read 4, iclass 4, count 0 2006.285.22:28:28.61#ibcon#read 4, iclass 4, count 0 2006.285.22:28:28.61#ibcon#about to read 5, iclass 4, count 0 2006.285.22:28:28.61#ibcon#read 5, iclass 4, count 0 2006.285.22:28:28.62#ibcon#about to read 6, iclass 4, count 0 2006.285.22:28:28.62#ibcon#read 6, iclass 4, count 0 2006.285.22:28:28.62#ibcon#end of sib2, iclass 4, count 0 2006.285.22:28:28.62#ibcon#*mode == 0, iclass 4, count 0 2006.285.22:28:28.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.22:28:28.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:28:28.62#ibcon#*before write, iclass 4, count 0 2006.285.22:28:28.62#ibcon#enter sib2, iclass 4, count 0 2006.285.22:28:28.62#ibcon#flushed, iclass 4, count 0 2006.285.22:28:28.62#ibcon#about to write, iclass 4, count 0 2006.285.22:28:28.62#ibcon#wrote, iclass 4, count 0 2006.285.22:28:28.62#ibcon#about to read 3, iclass 4, count 0 2006.285.22:28:28.65#ibcon#read 3, iclass 4, count 0 2006.285.22:28:28.65#ibcon#about to read 4, iclass 4, count 0 2006.285.22:28:28.65#ibcon#read 4, iclass 4, count 0 2006.285.22:28:28.65#ibcon#about to read 5, iclass 4, count 0 2006.285.22:28:28.65#ibcon#read 5, iclass 4, count 0 2006.285.22:28:28.65#ibcon#about to read 6, iclass 4, count 0 2006.285.22:28:28.65#ibcon#read 6, iclass 4, count 0 2006.285.22:28:28.65#ibcon#end of sib2, iclass 4, count 0 2006.285.22:28:28.65#ibcon#*after write, iclass 4, count 0 2006.285.22:28:28.66#ibcon#*before return 0, iclass 4, count 0 2006.285.22:28:28.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:28:28.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:28:28.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.22:28:28.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.22:28:28.66$vck44/va=3,7 2006.285.22:28:28.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.22:28:28.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.22:28:28.66#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:28.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:28:28.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:28:28.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:28:28.71#ibcon#enter wrdev, iclass 6, count 2 2006.285.22:28:28.71#ibcon#first serial, iclass 6, count 2 2006.285.22:28:28.71#ibcon#enter sib2, iclass 6, count 2 2006.285.22:28:28.71#ibcon#flushed, iclass 6, count 2 2006.285.22:28:28.71#ibcon#about to write, iclass 6, count 2 2006.285.22:28:28.71#ibcon#wrote, iclass 6, count 2 2006.285.22:28:28.71#ibcon#about to read 3, iclass 6, count 2 2006.285.22:28:28.73#ibcon#read 3, iclass 6, count 2 2006.285.22:28:28.73#ibcon#about to read 4, iclass 6, count 2 2006.285.22:28:28.73#ibcon#read 4, iclass 6, count 2 2006.285.22:28:28.73#ibcon#about to read 5, iclass 6, count 2 2006.285.22:28:28.73#ibcon#read 5, iclass 6, count 2 2006.285.22:28:28.73#ibcon#about to read 6, iclass 6, count 2 2006.285.22:28:28.73#ibcon#read 6, iclass 6, count 2 2006.285.22:28:28.73#ibcon#end of sib2, iclass 6, count 2 2006.285.22:28:28.73#ibcon#*mode == 0, iclass 6, count 2 2006.285.22:28:28.73#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.22:28:28.74#ibcon#[25=AT03-07\r\n] 2006.285.22:28:28.74#ibcon#*before write, iclass 6, count 2 2006.285.22:28:28.74#ibcon#enter sib2, iclass 6, count 2 2006.285.22:28:28.74#ibcon#flushed, iclass 6, count 2 2006.285.22:28:28.74#ibcon#about to write, iclass 6, count 2 2006.285.22:28:28.74#ibcon#wrote, iclass 6, count 2 2006.285.22:28:28.74#ibcon#about to read 3, iclass 6, count 2 2006.285.22:28:28.76#ibcon#read 3, iclass 6, count 2 2006.285.22:28:28.76#ibcon#about to read 4, iclass 6, count 2 2006.285.22:28:28.76#ibcon#read 4, iclass 6, count 2 2006.285.22:28:28.76#ibcon#about to read 5, iclass 6, count 2 2006.285.22:28:28.76#ibcon#read 5, iclass 6, count 2 2006.285.22:28:28.76#ibcon#about to read 6, iclass 6, count 2 2006.285.22:28:28.76#ibcon#read 6, iclass 6, count 2 2006.285.22:28:28.76#ibcon#end of sib2, iclass 6, count 2 2006.285.22:28:28.76#ibcon#*after write, iclass 6, count 2 2006.285.22:28:28.77#ibcon#*before return 0, iclass 6, count 2 2006.285.22:28:28.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:28:28.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:28:28.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.22:28:28.77#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:28.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:28:28.88#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:28:28.88#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:28:28.88#ibcon#enter wrdev, iclass 6, count 0 2006.285.22:28:28.88#ibcon#first serial, iclass 6, count 0 2006.285.22:28:28.88#ibcon#enter sib2, iclass 6, count 0 2006.285.22:28:28.88#ibcon#flushed, iclass 6, count 0 2006.285.22:28:28.88#ibcon#about to write, iclass 6, count 0 2006.285.22:28:28.88#ibcon#wrote, iclass 6, count 0 2006.285.22:28:28.88#ibcon#about to read 3, iclass 6, count 0 2006.285.22:28:28.90#ibcon#read 3, iclass 6, count 0 2006.285.22:28:28.90#ibcon#about to read 4, iclass 6, count 0 2006.285.22:28:28.90#ibcon#read 4, iclass 6, count 0 2006.285.22:28:28.90#ibcon#about to read 5, iclass 6, count 0 2006.285.22:28:28.90#ibcon#read 5, iclass 6, count 0 2006.285.22:28:28.90#ibcon#about to read 6, iclass 6, count 0 2006.285.22:28:28.90#ibcon#read 6, iclass 6, count 0 2006.285.22:28:28.90#ibcon#end of sib2, iclass 6, count 0 2006.285.22:28:28.90#ibcon#*mode == 0, iclass 6, count 0 2006.285.22:28:28.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.22:28:28.91#ibcon#[25=USB\r\n] 2006.285.22:28:28.91#ibcon#*before write, iclass 6, count 0 2006.285.22:28:28.91#ibcon#enter sib2, iclass 6, count 0 2006.285.22:28:28.91#ibcon#flushed, iclass 6, count 0 2006.285.22:28:28.91#ibcon#about to write, iclass 6, count 0 2006.285.22:28:28.91#ibcon#wrote, iclass 6, count 0 2006.285.22:28:28.91#ibcon#about to read 3, iclass 6, count 0 2006.285.22:28:28.93#ibcon#read 3, iclass 6, count 0 2006.285.22:28:28.93#ibcon#about to read 4, iclass 6, count 0 2006.285.22:28:28.93#ibcon#read 4, iclass 6, count 0 2006.285.22:28:28.93#ibcon#about to read 5, iclass 6, count 0 2006.285.22:28:28.93#ibcon#read 5, iclass 6, count 0 2006.285.22:28:28.93#ibcon#about to read 6, iclass 6, count 0 2006.285.22:28:28.93#ibcon#read 6, iclass 6, count 0 2006.285.22:28:28.93#ibcon#end of sib2, iclass 6, count 0 2006.285.22:28:28.93#ibcon#*after write, iclass 6, count 0 2006.285.22:28:28.94#ibcon#*before return 0, iclass 6, count 0 2006.285.22:28:28.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:28:28.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:28:28.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.22:28:28.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.22:28:28.94$vck44/valo=4,624.99 2006.285.22:28:28.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.22:28:28.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.22:28:28.94#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:28.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:28:28.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:28:28.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:28:28.94#ibcon#enter wrdev, iclass 10, count 0 2006.285.22:28:28.94#ibcon#first serial, iclass 10, count 0 2006.285.22:28:28.94#ibcon#enter sib2, iclass 10, count 0 2006.285.22:28:28.94#ibcon#flushed, iclass 10, count 0 2006.285.22:28:28.94#ibcon#about to write, iclass 10, count 0 2006.285.22:28:28.94#ibcon#wrote, iclass 10, count 0 2006.285.22:28:28.94#ibcon#about to read 3, iclass 10, count 0 2006.285.22:28:28.95#ibcon#read 3, iclass 10, count 0 2006.285.22:28:28.95#ibcon#about to read 4, iclass 10, count 0 2006.285.22:28:28.95#ibcon#read 4, iclass 10, count 0 2006.285.22:28:28.95#ibcon#about to read 5, iclass 10, count 0 2006.285.22:28:28.95#ibcon#read 5, iclass 10, count 0 2006.285.22:28:28.95#ibcon#about to read 6, iclass 10, count 0 2006.285.22:28:28.95#ibcon#read 6, iclass 10, count 0 2006.285.22:28:28.95#ibcon#end of sib2, iclass 10, count 0 2006.285.22:28:28.95#ibcon#*mode == 0, iclass 10, count 0 2006.285.22:28:28.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.22:28:28.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:28:28.96#ibcon#*before write, iclass 10, count 0 2006.285.22:28:28.96#ibcon#enter sib2, iclass 10, count 0 2006.285.22:28:28.96#ibcon#flushed, iclass 10, count 0 2006.285.22:28:28.96#ibcon#about to write, iclass 10, count 0 2006.285.22:28:28.96#ibcon#wrote, iclass 10, count 0 2006.285.22:28:28.96#ibcon#about to read 3, iclass 10, count 0 2006.285.22:28:28.99#ibcon#read 3, iclass 10, count 0 2006.285.22:28:28.99#ibcon#about to read 4, iclass 10, count 0 2006.285.22:28:28.99#ibcon#read 4, iclass 10, count 0 2006.285.22:28:28.99#ibcon#about to read 5, iclass 10, count 0 2006.285.22:28:28.99#ibcon#read 5, iclass 10, count 0 2006.285.22:28:28.99#ibcon#about to read 6, iclass 10, count 0 2006.285.22:28:28.99#ibcon#read 6, iclass 10, count 0 2006.285.22:28:28.99#ibcon#end of sib2, iclass 10, count 0 2006.285.22:28:28.99#ibcon#*after write, iclass 10, count 0 2006.285.22:28:29.00#ibcon#*before return 0, iclass 10, count 0 2006.285.22:28:29.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:28:29.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:28:29.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.22:28:29.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.22:28:29.00$vck44/va=4,6 2006.285.22:28:29.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.22:28:29.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.22:28:29.00#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:29.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:28:29.05#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:28:29.05#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:28:29.05#ibcon#enter wrdev, iclass 12, count 2 2006.285.22:28:29.05#ibcon#first serial, iclass 12, count 2 2006.285.22:28:29.05#ibcon#enter sib2, iclass 12, count 2 2006.285.22:28:29.05#ibcon#flushed, iclass 12, count 2 2006.285.22:28:29.05#ibcon#about to write, iclass 12, count 2 2006.285.22:28:29.05#ibcon#wrote, iclass 12, count 2 2006.285.22:28:29.06#ibcon#about to read 3, iclass 12, count 2 2006.285.22:28:29.07#ibcon#read 3, iclass 12, count 2 2006.285.22:28:29.07#ibcon#about to read 4, iclass 12, count 2 2006.285.22:28:29.07#ibcon#read 4, iclass 12, count 2 2006.285.22:28:29.07#ibcon#about to read 5, iclass 12, count 2 2006.285.22:28:29.07#ibcon#read 5, iclass 12, count 2 2006.285.22:28:29.07#ibcon#about to read 6, iclass 12, count 2 2006.285.22:28:29.07#ibcon#read 6, iclass 12, count 2 2006.285.22:28:29.08#ibcon#end of sib2, iclass 12, count 2 2006.285.22:28:29.08#ibcon#*mode == 0, iclass 12, count 2 2006.285.22:28:29.08#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.22:28:29.08#ibcon#[25=AT04-06\r\n] 2006.285.22:28:29.08#ibcon#*before write, iclass 12, count 2 2006.285.22:28:29.08#ibcon#enter sib2, iclass 12, count 2 2006.285.22:28:29.08#ibcon#flushed, iclass 12, count 2 2006.285.22:28:29.08#ibcon#about to write, iclass 12, count 2 2006.285.22:28:29.08#ibcon#wrote, iclass 12, count 2 2006.285.22:28:29.08#ibcon#about to read 3, iclass 12, count 2 2006.285.22:28:29.10#ibcon#read 3, iclass 12, count 2 2006.285.22:28:29.10#ibcon#about to read 4, iclass 12, count 2 2006.285.22:28:29.10#ibcon#read 4, iclass 12, count 2 2006.285.22:28:29.10#ibcon#about to read 5, iclass 12, count 2 2006.285.22:28:29.10#ibcon#read 5, iclass 12, count 2 2006.285.22:28:29.10#ibcon#about to read 6, iclass 12, count 2 2006.285.22:28:29.10#ibcon#read 6, iclass 12, count 2 2006.285.22:28:29.10#ibcon#end of sib2, iclass 12, count 2 2006.285.22:28:29.10#ibcon#*after write, iclass 12, count 2 2006.285.22:28:29.11#ibcon#*before return 0, iclass 12, count 2 2006.285.22:28:29.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:28:29.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:28:29.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.22:28:29.11#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:29.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:28:29.22#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:28:29.22#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:28:29.22#ibcon#enter wrdev, iclass 12, count 0 2006.285.22:28:29.22#ibcon#first serial, iclass 12, count 0 2006.285.22:28:29.22#ibcon#enter sib2, iclass 12, count 0 2006.285.22:28:29.22#ibcon#flushed, iclass 12, count 0 2006.285.22:28:29.22#ibcon#about to write, iclass 12, count 0 2006.285.22:28:29.23#ibcon#wrote, iclass 12, count 0 2006.285.22:28:29.23#ibcon#about to read 3, iclass 12, count 0 2006.285.22:28:29.24#ibcon#read 3, iclass 12, count 0 2006.285.22:28:29.24#ibcon#about to read 4, iclass 12, count 0 2006.285.22:28:29.24#ibcon#read 4, iclass 12, count 0 2006.285.22:28:29.24#ibcon#about to read 5, iclass 12, count 0 2006.285.22:28:29.24#ibcon#read 5, iclass 12, count 0 2006.285.22:28:29.24#ibcon#about to read 6, iclass 12, count 0 2006.285.22:28:29.24#ibcon#read 6, iclass 12, count 0 2006.285.22:28:29.24#ibcon#end of sib2, iclass 12, count 0 2006.285.22:28:29.24#ibcon#*mode == 0, iclass 12, count 0 2006.285.22:28:29.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.22:28:29.25#ibcon#[25=USB\r\n] 2006.285.22:28:29.25#ibcon#*before write, iclass 12, count 0 2006.285.22:28:29.25#ibcon#enter sib2, iclass 12, count 0 2006.285.22:28:29.25#ibcon#flushed, iclass 12, count 0 2006.285.22:28:29.25#ibcon#about to write, iclass 12, count 0 2006.285.22:28:29.25#ibcon#wrote, iclass 12, count 0 2006.285.22:28:29.25#ibcon#about to read 3, iclass 12, count 0 2006.285.22:28:29.27#ibcon#read 3, iclass 12, count 0 2006.285.22:28:29.27#ibcon#about to read 4, iclass 12, count 0 2006.285.22:28:29.27#ibcon#read 4, iclass 12, count 0 2006.285.22:28:29.27#ibcon#about to read 5, iclass 12, count 0 2006.285.22:28:29.27#ibcon#read 5, iclass 12, count 0 2006.285.22:28:29.27#ibcon#about to read 6, iclass 12, count 0 2006.285.22:28:29.27#ibcon#read 6, iclass 12, count 0 2006.285.22:28:29.27#ibcon#end of sib2, iclass 12, count 0 2006.285.22:28:29.27#ibcon#*after write, iclass 12, count 0 2006.285.22:28:29.27#ibcon#*before return 0, iclass 12, count 0 2006.285.22:28:29.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:28:29.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:28:29.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.22:28:29.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.22:28:29.28$vck44/valo=5,734.99 2006.285.22:28:29.28#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.22:28:29.28#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.22:28:29.28#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:29.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:28:29.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:28:29.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:28:29.28#ibcon#enter wrdev, iclass 14, count 0 2006.285.22:28:29.28#ibcon#first serial, iclass 14, count 0 2006.285.22:28:29.28#ibcon#enter sib2, iclass 14, count 0 2006.285.22:28:29.28#ibcon#flushed, iclass 14, count 0 2006.285.22:28:29.28#ibcon#about to write, iclass 14, count 0 2006.285.22:28:29.28#ibcon#wrote, iclass 14, count 0 2006.285.22:28:29.28#ibcon#about to read 3, iclass 14, count 0 2006.285.22:28:29.29#ibcon#read 3, iclass 14, count 0 2006.285.22:28:29.29#ibcon#about to read 4, iclass 14, count 0 2006.285.22:28:29.29#ibcon#read 4, iclass 14, count 0 2006.285.22:28:29.29#ibcon#about to read 5, iclass 14, count 0 2006.285.22:28:29.29#ibcon#read 5, iclass 14, count 0 2006.285.22:28:29.29#ibcon#about to read 6, iclass 14, count 0 2006.285.22:28:29.29#ibcon#read 6, iclass 14, count 0 2006.285.22:28:29.29#ibcon#end of sib2, iclass 14, count 0 2006.285.22:28:29.29#ibcon#*mode == 0, iclass 14, count 0 2006.285.22:28:29.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.22:28:29.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:28:29.30#ibcon#*before write, iclass 14, count 0 2006.285.22:28:29.30#ibcon#enter sib2, iclass 14, count 0 2006.285.22:28:29.30#ibcon#flushed, iclass 14, count 0 2006.285.22:28:29.30#ibcon#about to write, iclass 14, count 0 2006.285.22:28:29.30#ibcon#wrote, iclass 14, count 0 2006.285.22:28:29.30#ibcon#about to read 3, iclass 14, count 0 2006.285.22:28:29.33#ibcon#read 3, iclass 14, count 0 2006.285.22:28:29.33#ibcon#about to read 4, iclass 14, count 0 2006.285.22:28:29.33#ibcon#read 4, iclass 14, count 0 2006.285.22:28:29.33#ibcon#about to read 5, iclass 14, count 0 2006.285.22:28:29.33#ibcon#read 5, iclass 14, count 0 2006.285.22:28:29.33#ibcon#about to read 6, iclass 14, count 0 2006.285.22:28:29.33#ibcon#read 6, iclass 14, count 0 2006.285.22:28:29.33#ibcon#end of sib2, iclass 14, count 0 2006.285.22:28:29.33#ibcon#*after write, iclass 14, count 0 2006.285.22:28:29.34#ibcon#*before return 0, iclass 14, count 0 2006.285.22:28:29.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:28:29.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:28:29.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.22:28:29.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.22:28:29.34$vck44/va=5,3 2006.285.22:28:29.34#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.22:28:29.34#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.22:28:29.34#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:29.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:28:29.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:28:29.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:28:29.40#ibcon#enter wrdev, iclass 16, count 2 2006.285.22:28:29.40#ibcon#first serial, iclass 16, count 2 2006.285.22:28:29.40#ibcon#enter sib2, iclass 16, count 2 2006.285.22:28:29.40#ibcon#flushed, iclass 16, count 2 2006.285.22:28:29.40#ibcon#about to write, iclass 16, count 2 2006.285.22:28:29.40#ibcon#wrote, iclass 16, count 2 2006.285.22:28:29.40#ibcon#about to read 3, iclass 16, count 2 2006.285.22:28:29.41#ibcon#read 3, iclass 16, count 2 2006.285.22:28:29.41#ibcon#about to read 4, iclass 16, count 2 2006.285.22:28:29.41#ibcon#read 4, iclass 16, count 2 2006.285.22:28:29.41#ibcon#about to read 5, iclass 16, count 2 2006.285.22:28:29.41#ibcon#read 5, iclass 16, count 2 2006.285.22:28:29.41#ibcon#about to read 6, iclass 16, count 2 2006.285.22:28:29.42#ibcon#read 6, iclass 16, count 2 2006.285.22:28:29.42#ibcon#end of sib2, iclass 16, count 2 2006.285.22:28:29.42#ibcon#*mode == 0, iclass 16, count 2 2006.285.22:28:29.42#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.22:28:29.42#ibcon#[25=AT05-03\r\n] 2006.285.22:28:29.42#ibcon#*before write, iclass 16, count 2 2006.285.22:28:29.42#ibcon#enter sib2, iclass 16, count 2 2006.285.22:28:29.42#ibcon#flushed, iclass 16, count 2 2006.285.22:28:29.42#ibcon#about to write, iclass 16, count 2 2006.285.22:28:29.42#ibcon#wrote, iclass 16, count 2 2006.285.22:28:29.42#ibcon#about to read 3, iclass 16, count 2 2006.285.22:28:29.44#ibcon#read 3, iclass 16, count 2 2006.285.22:28:29.44#ibcon#about to read 4, iclass 16, count 2 2006.285.22:28:29.44#ibcon#read 4, iclass 16, count 2 2006.285.22:28:29.44#ibcon#about to read 5, iclass 16, count 2 2006.285.22:28:29.44#ibcon#read 5, iclass 16, count 2 2006.285.22:28:29.44#ibcon#about to read 6, iclass 16, count 2 2006.285.22:28:29.44#ibcon#read 6, iclass 16, count 2 2006.285.22:28:29.44#ibcon#end of sib2, iclass 16, count 2 2006.285.22:28:29.44#ibcon#*after write, iclass 16, count 2 2006.285.22:28:29.45#ibcon#*before return 0, iclass 16, count 2 2006.285.22:28:29.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:28:29.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:28:29.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.22:28:29.45#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:29.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:28:29.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:28:29.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:28:29.56#ibcon#enter wrdev, iclass 16, count 0 2006.285.22:28:29.56#ibcon#first serial, iclass 16, count 0 2006.285.22:28:29.56#ibcon#enter sib2, iclass 16, count 0 2006.285.22:28:29.56#ibcon#flushed, iclass 16, count 0 2006.285.22:28:29.56#ibcon#about to write, iclass 16, count 0 2006.285.22:28:29.57#ibcon#wrote, iclass 16, count 0 2006.285.22:28:29.57#ibcon#about to read 3, iclass 16, count 0 2006.285.22:28:29.58#ibcon#read 3, iclass 16, count 0 2006.285.22:28:29.58#ibcon#about to read 4, iclass 16, count 0 2006.285.22:28:29.58#ibcon#read 4, iclass 16, count 0 2006.285.22:28:29.58#ibcon#about to read 5, iclass 16, count 0 2006.285.22:28:29.58#ibcon#read 5, iclass 16, count 0 2006.285.22:28:29.58#ibcon#about to read 6, iclass 16, count 0 2006.285.22:28:29.58#ibcon#read 6, iclass 16, count 0 2006.285.22:28:29.58#ibcon#end of sib2, iclass 16, count 0 2006.285.22:28:29.58#ibcon#*mode == 0, iclass 16, count 0 2006.285.22:28:29.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.22:28:29.59#ibcon#[25=USB\r\n] 2006.285.22:28:29.59#ibcon#*before write, iclass 16, count 0 2006.285.22:28:29.59#ibcon#enter sib2, iclass 16, count 0 2006.285.22:28:29.59#ibcon#flushed, iclass 16, count 0 2006.285.22:28:29.59#ibcon#about to write, iclass 16, count 0 2006.285.22:28:29.59#ibcon#wrote, iclass 16, count 0 2006.285.22:28:29.59#ibcon#about to read 3, iclass 16, count 0 2006.285.22:28:29.61#ibcon#read 3, iclass 16, count 0 2006.285.22:28:29.61#ibcon#about to read 4, iclass 16, count 0 2006.285.22:28:29.61#ibcon#read 4, iclass 16, count 0 2006.285.22:28:29.61#ibcon#about to read 5, iclass 16, count 0 2006.285.22:28:29.61#ibcon#read 5, iclass 16, count 0 2006.285.22:28:29.61#ibcon#about to read 6, iclass 16, count 0 2006.285.22:28:29.62#ibcon#read 6, iclass 16, count 0 2006.285.22:28:29.62#ibcon#end of sib2, iclass 16, count 0 2006.285.22:28:29.62#ibcon#*after write, iclass 16, count 0 2006.285.22:28:29.62#ibcon#*before return 0, iclass 16, count 0 2006.285.22:28:29.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:28:29.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:28:29.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.22:28:29.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.22:28:29.62$vck44/valo=6,814.99 2006.285.22:28:29.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.22:28:29.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.22:28:29.62#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:29.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:28:29.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:28:29.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:28:29.62#ibcon#enter wrdev, iclass 18, count 0 2006.285.22:28:29.62#ibcon#first serial, iclass 18, count 0 2006.285.22:28:29.62#ibcon#enter sib2, iclass 18, count 0 2006.285.22:28:29.62#ibcon#flushed, iclass 18, count 0 2006.285.22:28:29.62#ibcon#about to write, iclass 18, count 0 2006.285.22:28:29.62#ibcon#wrote, iclass 18, count 0 2006.285.22:28:29.62#ibcon#about to read 3, iclass 18, count 0 2006.285.22:28:29.63#ibcon#read 3, iclass 18, count 0 2006.285.22:28:29.63#ibcon#about to read 4, iclass 18, count 0 2006.285.22:28:29.63#ibcon#read 4, iclass 18, count 0 2006.285.22:28:29.63#ibcon#about to read 5, iclass 18, count 0 2006.285.22:28:29.63#ibcon#read 5, iclass 18, count 0 2006.285.22:28:29.63#ibcon#about to read 6, iclass 18, count 0 2006.285.22:28:29.63#ibcon#read 6, iclass 18, count 0 2006.285.22:28:29.63#ibcon#end of sib2, iclass 18, count 0 2006.285.22:28:29.63#ibcon#*mode == 0, iclass 18, count 0 2006.285.22:28:29.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.22:28:29.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:28:29.64#ibcon#*before write, iclass 18, count 0 2006.285.22:28:29.64#ibcon#enter sib2, iclass 18, count 0 2006.285.22:28:29.64#ibcon#flushed, iclass 18, count 0 2006.285.22:28:29.64#ibcon#about to write, iclass 18, count 0 2006.285.22:28:29.64#ibcon#wrote, iclass 18, count 0 2006.285.22:28:29.64#ibcon#about to read 3, iclass 18, count 0 2006.285.22:28:29.67#ibcon#read 3, iclass 18, count 0 2006.285.22:28:29.67#ibcon#about to read 4, iclass 18, count 0 2006.285.22:28:29.67#ibcon#read 4, iclass 18, count 0 2006.285.22:28:29.67#ibcon#about to read 5, iclass 18, count 0 2006.285.22:28:29.67#ibcon#read 5, iclass 18, count 0 2006.285.22:28:29.67#ibcon#about to read 6, iclass 18, count 0 2006.285.22:28:29.67#ibcon#read 6, iclass 18, count 0 2006.285.22:28:29.67#ibcon#end of sib2, iclass 18, count 0 2006.285.22:28:29.67#ibcon#*after write, iclass 18, count 0 2006.285.22:28:29.67#ibcon#*before return 0, iclass 18, count 0 2006.285.22:28:29.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:28:29.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:28:29.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.22:28:29.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.22:28:29.68$vck44/va=6,4 2006.285.22:28:29.68#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.22:28:29.68#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.22:28:29.68#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:29.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:28:29.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:28:29.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:28:29.73#ibcon#enter wrdev, iclass 20, count 2 2006.285.22:28:29.73#ibcon#first serial, iclass 20, count 2 2006.285.22:28:29.73#ibcon#enter sib2, iclass 20, count 2 2006.285.22:28:29.73#ibcon#flushed, iclass 20, count 2 2006.285.22:28:29.73#ibcon#about to write, iclass 20, count 2 2006.285.22:28:29.73#ibcon#wrote, iclass 20, count 2 2006.285.22:28:29.73#ibcon#about to read 3, iclass 20, count 2 2006.285.22:28:29.75#ibcon#read 3, iclass 20, count 2 2006.285.22:28:29.75#ibcon#about to read 4, iclass 20, count 2 2006.285.22:28:29.75#ibcon#read 4, iclass 20, count 2 2006.285.22:28:29.75#ibcon#about to read 5, iclass 20, count 2 2006.285.22:28:29.75#ibcon#read 5, iclass 20, count 2 2006.285.22:28:29.75#ibcon#about to read 6, iclass 20, count 2 2006.285.22:28:29.75#ibcon#read 6, iclass 20, count 2 2006.285.22:28:29.75#ibcon#end of sib2, iclass 20, count 2 2006.285.22:28:29.75#ibcon#*mode == 0, iclass 20, count 2 2006.285.22:28:29.75#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.22:28:29.76#ibcon#[25=AT06-04\r\n] 2006.285.22:28:29.76#ibcon#*before write, iclass 20, count 2 2006.285.22:28:29.76#ibcon#enter sib2, iclass 20, count 2 2006.285.22:28:29.76#ibcon#flushed, iclass 20, count 2 2006.285.22:28:29.76#ibcon#about to write, iclass 20, count 2 2006.285.22:28:29.76#ibcon#wrote, iclass 20, count 2 2006.285.22:28:29.76#ibcon#about to read 3, iclass 20, count 2 2006.285.22:28:29.78#ibcon#read 3, iclass 20, count 2 2006.285.22:28:29.78#ibcon#about to read 4, iclass 20, count 2 2006.285.22:28:29.78#ibcon#read 4, iclass 20, count 2 2006.285.22:28:29.78#ibcon#about to read 5, iclass 20, count 2 2006.285.22:28:29.78#ibcon#read 5, iclass 20, count 2 2006.285.22:28:29.78#ibcon#about to read 6, iclass 20, count 2 2006.285.22:28:29.78#ibcon#read 6, iclass 20, count 2 2006.285.22:28:29.78#ibcon#end of sib2, iclass 20, count 2 2006.285.22:28:29.78#ibcon#*after write, iclass 20, count 2 2006.285.22:28:29.78#ibcon#*before return 0, iclass 20, count 2 2006.285.22:28:29.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:28:29.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:28:29.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.22:28:29.79#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:29.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:28:29.90#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:28:29.90#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:28:29.90#ibcon#enter wrdev, iclass 20, count 0 2006.285.22:28:29.90#ibcon#first serial, iclass 20, count 0 2006.285.22:28:29.90#ibcon#enter sib2, iclass 20, count 0 2006.285.22:28:29.90#ibcon#flushed, iclass 20, count 0 2006.285.22:28:29.90#ibcon#about to write, iclass 20, count 0 2006.285.22:28:29.90#ibcon#wrote, iclass 20, count 0 2006.285.22:28:29.90#ibcon#about to read 3, iclass 20, count 0 2006.285.22:28:29.92#ibcon#read 3, iclass 20, count 0 2006.285.22:28:29.92#ibcon#about to read 4, iclass 20, count 0 2006.285.22:28:29.92#ibcon#read 4, iclass 20, count 0 2006.285.22:28:29.92#ibcon#about to read 5, iclass 20, count 0 2006.285.22:28:29.92#ibcon#read 5, iclass 20, count 0 2006.285.22:28:29.92#ibcon#about to read 6, iclass 20, count 0 2006.285.22:28:29.92#ibcon#read 6, iclass 20, count 0 2006.285.22:28:29.92#ibcon#end of sib2, iclass 20, count 0 2006.285.22:28:29.92#ibcon#*mode == 0, iclass 20, count 0 2006.285.22:28:29.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.22:28:29.93#ibcon#[25=USB\r\n] 2006.285.22:28:29.93#ibcon#*before write, iclass 20, count 0 2006.285.22:28:29.93#ibcon#enter sib2, iclass 20, count 0 2006.285.22:28:29.93#ibcon#flushed, iclass 20, count 0 2006.285.22:28:29.93#ibcon#about to write, iclass 20, count 0 2006.285.22:28:29.93#ibcon#wrote, iclass 20, count 0 2006.285.22:28:29.93#ibcon#about to read 3, iclass 20, count 0 2006.285.22:28:29.95#ibcon#read 3, iclass 20, count 0 2006.285.22:28:29.95#ibcon#about to read 4, iclass 20, count 0 2006.285.22:28:29.95#ibcon#read 4, iclass 20, count 0 2006.285.22:28:29.95#ibcon#about to read 5, iclass 20, count 0 2006.285.22:28:29.95#ibcon#read 5, iclass 20, count 0 2006.285.22:28:29.95#ibcon#about to read 6, iclass 20, count 0 2006.285.22:28:29.95#ibcon#read 6, iclass 20, count 0 2006.285.22:28:29.95#ibcon#end of sib2, iclass 20, count 0 2006.285.22:28:29.95#ibcon#*after write, iclass 20, count 0 2006.285.22:28:29.95#ibcon#*before return 0, iclass 20, count 0 2006.285.22:28:29.96#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:28:29.96#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:28:29.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.22:28:29.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.22:28:29.96$vck44/valo=7,864.99 2006.285.22:28:29.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.22:28:29.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.22:28:29.96#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:29.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:28:29.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:28:29.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:28:29.96#ibcon#enter wrdev, iclass 22, count 0 2006.285.22:28:29.96#ibcon#first serial, iclass 22, count 0 2006.285.22:28:29.96#ibcon#enter sib2, iclass 22, count 0 2006.285.22:28:29.96#ibcon#flushed, iclass 22, count 0 2006.285.22:28:29.96#ibcon#about to write, iclass 22, count 0 2006.285.22:28:29.96#ibcon#wrote, iclass 22, count 0 2006.285.22:28:29.96#ibcon#about to read 3, iclass 22, count 0 2006.285.22:28:29.97#ibcon#read 3, iclass 22, count 0 2006.285.22:28:29.97#ibcon#about to read 4, iclass 22, count 0 2006.285.22:28:29.97#ibcon#read 4, iclass 22, count 0 2006.285.22:28:29.97#ibcon#about to read 5, iclass 22, count 0 2006.285.22:28:29.97#ibcon#read 5, iclass 22, count 0 2006.285.22:28:29.97#ibcon#about to read 6, iclass 22, count 0 2006.285.22:28:29.97#ibcon#read 6, iclass 22, count 0 2006.285.22:28:29.97#ibcon#end of sib2, iclass 22, count 0 2006.285.22:28:29.98#ibcon#*mode == 0, iclass 22, count 0 2006.285.22:28:29.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.22:28:29.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:28:29.98#ibcon#*before write, iclass 22, count 0 2006.285.22:28:29.98#ibcon#enter sib2, iclass 22, count 0 2006.285.22:28:29.98#ibcon#flushed, iclass 22, count 0 2006.285.22:28:29.98#ibcon#about to write, iclass 22, count 0 2006.285.22:28:29.98#ibcon#wrote, iclass 22, count 0 2006.285.22:28:29.98#ibcon#about to read 3, iclass 22, count 0 2006.285.22:28:30.01#ibcon#read 3, iclass 22, count 0 2006.285.22:28:30.01#ibcon#about to read 4, iclass 22, count 0 2006.285.22:28:30.01#ibcon#read 4, iclass 22, count 0 2006.285.22:28:30.01#ibcon#about to read 5, iclass 22, count 0 2006.285.22:28:30.01#ibcon#read 5, iclass 22, count 0 2006.285.22:28:30.01#ibcon#about to read 6, iclass 22, count 0 2006.285.22:28:30.02#ibcon#read 6, iclass 22, count 0 2006.285.22:28:30.02#ibcon#end of sib2, iclass 22, count 0 2006.285.22:28:30.02#ibcon#*after write, iclass 22, count 0 2006.285.22:28:30.02#ibcon#*before return 0, iclass 22, count 0 2006.285.22:28:30.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:28:30.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:28:30.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.22:28:30.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.22:28:30.02$vck44/va=7,4 2006.285.22:28:30.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.22:28:30.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.22:28:30.02#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:30.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:28:30.07#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:28:30.07#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:28:30.07#ibcon#enter wrdev, iclass 24, count 2 2006.285.22:28:30.07#ibcon#first serial, iclass 24, count 2 2006.285.22:28:30.07#ibcon#enter sib2, iclass 24, count 2 2006.285.22:28:30.07#ibcon#flushed, iclass 24, count 2 2006.285.22:28:30.07#ibcon#about to write, iclass 24, count 2 2006.285.22:28:30.08#ibcon#wrote, iclass 24, count 2 2006.285.22:28:30.08#ibcon#about to read 3, iclass 24, count 2 2006.285.22:28:30.09#ibcon#read 3, iclass 24, count 2 2006.285.22:28:30.09#ibcon#about to read 4, iclass 24, count 2 2006.285.22:28:30.09#ibcon#read 4, iclass 24, count 2 2006.285.22:28:30.09#ibcon#about to read 5, iclass 24, count 2 2006.285.22:28:30.09#ibcon#read 5, iclass 24, count 2 2006.285.22:28:30.09#ibcon#about to read 6, iclass 24, count 2 2006.285.22:28:30.09#ibcon#read 6, iclass 24, count 2 2006.285.22:28:30.09#ibcon#end of sib2, iclass 24, count 2 2006.285.22:28:30.09#ibcon#*mode == 0, iclass 24, count 2 2006.285.22:28:30.09#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.22:28:30.10#ibcon#[25=AT07-04\r\n] 2006.285.22:28:30.10#ibcon#*before write, iclass 24, count 2 2006.285.22:28:30.10#ibcon#enter sib2, iclass 24, count 2 2006.285.22:28:30.10#ibcon#flushed, iclass 24, count 2 2006.285.22:28:30.10#ibcon#about to write, iclass 24, count 2 2006.285.22:28:30.10#ibcon#wrote, iclass 24, count 2 2006.285.22:28:30.10#ibcon#about to read 3, iclass 24, count 2 2006.285.22:28:30.12#ibcon#read 3, iclass 24, count 2 2006.285.22:28:30.12#ibcon#about to read 4, iclass 24, count 2 2006.285.22:28:30.12#ibcon#read 4, iclass 24, count 2 2006.285.22:28:30.12#ibcon#about to read 5, iclass 24, count 2 2006.285.22:28:30.12#ibcon#read 5, iclass 24, count 2 2006.285.22:28:30.12#ibcon#about to read 6, iclass 24, count 2 2006.285.22:28:30.12#ibcon#read 6, iclass 24, count 2 2006.285.22:28:30.12#ibcon#end of sib2, iclass 24, count 2 2006.285.22:28:30.12#ibcon#*after write, iclass 24, count 2 2006.285.22:28:30.12#ibcon#*before return 0, iclass 24, count 2 2006.285.22:28:30.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:28:30.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:28:30.13#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.22:28:30.13#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:30.13#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:28:30.24#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:28:30.24#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:28:30.24#ibcon#enter wrdev, iclass 24, count 0 2006.285.22:28:30.24#ibcon#first serial, iclass 24, count 0 2006.285.22:28:30.24#ibcon#enter sib2, iclass 24, count 0 2006.285.22:28:30.24#ibcon#flushed, iclass 24, count 0 2006.285.22:28:30.24#ibcon#about to write, iclass 24, count 0 2006.285.22:28:30.25#ibcon#wrote, iclass 24, count 0 2006.285.22:28:30.25#ibcon#about to read 3, iclass 24, count 0 2006.285.22:28:30.26#ibcon#read 3, iclass 24, count 0 2006.285.22:28:30.26#ibcon#about to read 4, iclass 24, count 0 2006.285.22:28:30.26#ibcon#read 4, iclass 24, count 0 2006.285.22:28:30.26#ibcon#about to read 5, iclass 24, count 0 2006.285.22:28:30.26#ibcon#read 5, iclass 24, count 0 2006.285.22:28:30.26#ibcon#about to read 6, iclass 24, count 0 2006.285.22:28:30.26#ibcon#read 6, iclass 24, count 0 2006.285.22:28:30.26#ibcon#end of sib2, iclass 24, count 0 2006.285.22:28:30.26#ibcon#*mode == 0, iclass 24, count 0 2006.285.22:28:30.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.22:28:30.27#ibcon#[25=USB\r\n] 2006.285.22:28:30.27#ibcon#*before write, iclass 24, count 0 2006.285.22:28:30.27#ibcon#enter sib2, iclass 24, count 0 2006.285.22:28:30.27#ibcon#flushed, iclass 24, count 0 2006.285.22:28:30.27#ibcon#about to write, iclass 24, count 0 2006.285.22:28:30.27#ibcon#wrote, iclass 24, count 0 2006.285.22:28:30.27#ibcon#about to read 3, iclass 24, count 0 2006.285.22:28:30.29#ibcon#read 3, iclass 24, count 0 2006.285.22:28:30.29#ibcon#about to read 4, iclass 24, count 0 2006.285.22:28:30.29#ibcon#read 4, iclass 24, count 0 2006.285.22:28:30.29#ibcon#about to read 5, iclass 24, count 0 2006.285.22:28:30.29#ibcon#read 5, iclass 24, count 0 2006.285.22:28:30.29#ibcon#about to read 6, iclass 24, count 0 2006.285.22:28:30.29#ibcon#read 6, iclass 24, count 0 2006.285.22:28:30.29#ibcon#end of sib2, iclass 24, count 0 2006.285.22:28:30.29#ibcon#*after write, iclass 24, count 0 2006.285.22:28:30.29#ibcon#*before return 0, iclass 24, count 0 2006.285.22:28:30.30#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:28:30.30#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:28:30.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.22:28:30.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.22:28:30.30$vck44/valo=8,884.99 2006.285.22:28:30.30#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.22:28:30.30#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.22:28:30.30#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:30.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:28:30.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:28:30.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:28:30.30#ibcon#enter wrdev, iclass 26, count 0 2006.285.22:28:30.30#ibcon#first serial, iclass 26, count 0 2006.285.22:28:30.30#ibcon#enter sib2, iclass 26, count 0 2006.285.22:28:30.30#ibcon#flushed, iclass 26, count 0 2006.285.22:28:30.30#ibcon#about to write, iclass 26, count 0 2006.285.22:28:30.30#ibcon#wrote, iclass 26, count 0 2006.285.22:28:30.30#ibcon#about to read 3, iclass 26, count 0 2006.285.22:28:30.31#ibcon#read 3, iclass 26, count 0 2006.285.22:28:30.31#ibcon#about to read 4, iclass 26, count 0 2006.285.22:28:30.31#ibcon#read 4, iclass 26, count 0 2006.285.22:28:30.31#ibcon#about to read 5, iclass 26, count 0 2006.285.22:28:30.31#ibcon#read 5, iclass 26, count 0 2006.285.22:28:30.31#ibcon#about to read 6, iclass 26, count 0 2006.285.22:28:30.31#ibcon#read 6, iclass 26, count 0 2006.285.22:28:30.31#ibcon#end of sib2, iclass 26, count 0 2006.285.22:28:30.31#ibcon#*mode == 0, iclass 26, count 0 2006.285.22:28:30.32#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.22:28:30.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:28:30.32#ibcon#*before write, iclass 26, count 0 2006.285.22:28:30.32#ibcon#enter sib2, iclass 26, count 0 2006.285.22:28:30.32#ibcon#flushed, iclass 26, count 0 2006.285.22:28:30.32#ibcon#about to write, iclass 26, count 0 2006.285.22:28:30.32#ibcon#wrote, iclass 26, count 0 2006.285.22:28:30.32#ibcon#about to read 3, iclass 26, count 0 2006.285.22:28:30.35#ibcon#read 3, iclass 26, count 0 2006.285.22:28:30.35#ibcon#about to read 4, iclass 26, count 0 2006.285.22:28:30.35#ibcon#read 4, iclass 26, count 0 2006.285.22:28:30.35#ibcon#about to read 5, iclass 26, count 0 2006.285.22:28:30.35#ibcon#read 5, iclass 26, count 0 2006.285.22:28:30.35#ibcon#about to read 6, iclass 26, count 0 2006.285.22:28:30.35#ibcon#read 6, iclass 26, count 0 2006.285.22:28:30.35#ibcon#end of sib2, iclass 26, count 0 2006.285.22:28:30.35#ibcon#*after write, iclass 26, count 0 2006.285.22:28:30.35#ibcon#*before return 0, iclass 26, count 0 2006.285.22:28:30.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:28:30.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.22:28:30.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.22:28:30.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.22:28:30.36$vck44/va=8,3 2006.285.22:28:30.36#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.22:28:30.36#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.22:28:30.36#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:30.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:28:30.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:28:30.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:28:30.41#ibcon#enter wrdev, iclass 28, count 2 2006.285.22:28:30.41#ibcon#first serial, iclass 28, count 2 2006.285.22:28:30.41#ibcon#enter sib2, iclass 28, count 2 2006.285.22:28:30.41#ibcon#flushed, iclass 28, count 2 2006.285.22:28:30.42#ibcon#about to write, iclass 28, count 2 2006.285.22:28:30.42#ibcon#wrote, iclass 28, count 2 2006.285.22:28:30.42#ibcon#about to read 3, iclass 28, count 2 2006.285.22:28:30.43#ibcon#read 3, iclass 28, count 2 2006.285.22:28:30.43#ibcon#about to read 4, iclass 28, count 2 2006.285.22:28:30.43#ibcon#read 4, iclass 28, count 2 2006.285.22:28:30.43#ibcon#about to read 5, iclass 28, count 2 2006.285.22:28:30.43#ibcon#read 5, iclass 28, count 2 2006.285.22:28:30.43#ibcon#about to read 6, iclass 28, count 2 2006.285.22:28:30.44#ibcon#read 6, iclass 28, count 2 2006.285.22:28:30.44#ibcon#end of sib2, iclass 28, count 2 2006.285.22:28:30.44#ibcon#*mode == 0, iclass 28, count 2 2006.285.22:28:30.44#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.22:28:30.44#ibcon#[25=AT08-03\r\n] 2006.285.22:28:30.44#ibcon#*before write, iclass 28, count 2 2006.285.22:28:30.44#ibcon#enter sib2, iclass 28, count 2 2006.285.22:28:30.44#ibcon#flushed, iclass 28, count 2 2006.285.22:28:30.44#ibcon#about to write, iclass 28, count 2 2006.285.22:28:30.44#ibcon#wrote, iclass 28, count 2 2006.285.22:28:30.44#ibcon#about to read 3, iclass 28, count 2 2006.285.22:28:30.46#ibcon#read 3, iclass 28, count 2 2006.285.22:28:30.46#ibcon#about to read 4, iclass 28, count 2 2006.285.22:28:30.46#ibcon#read 4, iclass 28, count 2 2006.285.22:28:30.46#ibcon#about to read 5, iclass 28, count 2 2006.285.22:28:30.46#ibcon#read 5, iclass 28, count 2 2006.285.22:28:30.46#ibcon#about to read 6, iclass 28, count 2 2006.285.22:28:30.46#ibcon#read 6, iclass 28, count 2 2006.285.22:28:30.47#ibcon#end of sib2, iclass 28, count 2 2006.285.22:28:30.47#ibcon#*after write, iclass 28, count 2 2006.285.22:28:30.47#ibcon#*before return 0, iclass 28, count 2 2006.285.22:28:30.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:28:30.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.22:28:30.47#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.22:28:30.47#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:30.47#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:28:30.58#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:28:30.58#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:28:30.58#ibcon#enter wrdev, iclass 28, count 0 2006.285.22:28:30.58#ibcon#first serial, iclass 28, count 0 2006.285.22:28:30.58#ibcon#enter sib2, iclass 28, count 0 2006.285.22:28:30.58#ibcon#flushed, iclass 28, count 0 2006.285.22:28:30.58#ibcon#about to write, iclass 28, count 0 2006.285.22:28:30.59#ibcon#wrote, iclass 28, count 0 2006.285.22:28:30.59#ibcon#about to read 3, iclass 28, count 0 2006.285.22:28:30.60#ibcon#read 3, iclass 28, count 0 2006.285.22:28:30.60#ibcon#about to read 4, iclass 28, count 0 2006.285.22:28:30.60#ibcon#read 4, iclass 28, count 0 2006.285.22:28:30.60#ibcon#about to read 5, iclass 28, count 0 2006.285.22:28:30.60#ibcon#read 5, iclass 28, count 0 2006.285.22:28:30.60#ibcon#about to read 6, iclass 28, count 0 2006.285.22:28:30.60#ibcon#read 6, iclass 28, count 0 2006.285.22:28:30.60#ibcon#end of sib2, iclass 28, count 0 2006.285.22:28:30.60#ibcon#*mode == 0, iclass 28, count 0 2006.285.22:28:30.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.22:28:30.61#ibcon#[25=USB\r\n] 2006.285.22:28:30.61#ibcon#*before write, iclass 28, count 0 2006.285.22:28:30.61#ibcon#enter sib2, iclass 28, count 0 2006.285.22:28:30.61#ibcon#flushed, iclass 28, count 0 2006.285.22:28:30.61#ibcon#about to write, iclass 28, count 0 2006.285.22:28:30.61#ibcon#wrote, iclass 28, count 0 2006.285.22:28:30.61#ibcon#about to read 3, iclass 28, count 0 2006.285.22:28:30.63#ibcon#read 3, iclass 28, count 0 2006.285.22:28:30.63#ibcon#about to read 4, iclass 28, count 0 2006.285.22:28:30.63#ibcon#read 4, iclass 28, count 0 2006.285.22:28:30.63#ibcon#about to read 5, iclass 28, count 0 2006.285.22:28:30.63#ibcon#read 5, iclass 28, count 0 2006.285.22:28:30.63#ibcon#about to read 6, iclass 28, count 0 2006.285.22:28:30.63#ibcon#read 6, iclass 28, count 0 2006.285.22:28:30.63#ibcon#end of sib2, iclass 28, count 0 2006.285.22:28:30.64#ibcon#*after write, iclass 28, count 0 2006.285.22:28:30.64#ibcon#*before return 0, iclass 28, count 0 2006.285.22:28:30.64#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:28:30.64#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.22:28:30.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.22:28:30.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.22:28:30.64$vck44/vblo=1,629.99 2006.285.22:28:30.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.22:28:30.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.22:28:30.64#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:30.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:28:30.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:28:30.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:28:30.64#ibcon#enter wrdev, iclass 30, count 0 2006.285.22:28:30.64#ibcon#first serial, iclass 30, count 0 2006.285.22:28:30.64#ibcon#enter sib2, iclass 30, count 0 2006.285.22:28:30.64#ibcon#flushed, iclass 30, count 0 2006.285.22:28:30.64#ibcon#about to write, iclass 30, count 0 2006.285.22:28:30.64#ibcon#wrote, iclass 30, count 0 2006.285.22:28:30.64#ibcon#about to read 3, iclass 30, count 0 2006.285.22:28:30.65#ibcon#read 3, iclass 30, count 0 2006.285.22:28:30.65#ibcon#about to read 4, iclass 30, count 0 2006.285.22:28:30.65#ibcon#read 4, iclass 30, count 0 2006.285.22:28:30.65#ibcon#about to read 5, iclass 30, count 0 2006.285.22:28:30.65#ibcon#read 5, iclass 30, count 0 2006.285.22:28:30.65#ibcon#about to read 6, iclass 30, count 0 2006.285.22:28:30.65#ibcon#read 6, iclass 30, count 0 2006.285.22:28:30.65#ibcon#end of sib2, iclass 30, count 0 2006.285.22:28:30.66#ibcon#*mode == 0, iclass 30, count 0 2006.285.22:28:30.66#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.22:28:30.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:28:30.66#ibcon#*before write, iclass 30, count 0 2006.285.22:28:30.66#ibcon#enter sib2, iclass 30, count 0 2006.285.22:28:30.66#ibcon#flushed, iclass 30, count 0 2006.285.22:28:30.66#ibcon#about to write, iclass 30, count 0 2006.285.22:28:30.66#ibcon#wrote, iclass 30, count 0 2006.285.22:28:30.66#ibcon#about to read 3, iclass 30, count 0 2006.285.22:28:30.69#ibcon#read 3, iclass 30, count 0 2006.285.22:28:30.69#ibcon#about to read 4, iclass 30, count 0 2006.285.22:28:30.69#ibcon#read 4, iclass 30, count 0 2006.285.22:28:30.69#ibcon#about to read 5, iclass 30, count 0 2006.285.22:28:30.69#ibcon#read 5, iclass 30, count 0 2006.285.22:28:30.69#ibcon#about to read 6, iclass 30, count 0 2006.285.22:28:30.69#ibcon#read 6, iclass 30, count 0 2006.285.22:28:30.69#ibcon#end of sib2, iclass 30, count 0 2006.285.22:28:30.69#ibcon#*after write, iclass 30, count 0 2006.285.22:28:30.70#ibcon#*before return 0, iclass 30, count 0 2006.285.22:28:30.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:28:30.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:28:30.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.22:28:30.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.22:28:30.70$vck44/vb=1,4 2006.285.22:28:30.70#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.22:28:30.70#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.22:28:30.70#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:30.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:28:30.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:28:30.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:28:30.70#ibcon#enter wrdev, iclass 32, count 2 2006.285.22:28:30.70#ibcon#first serial, iclass 32, count 2 2006.285.22:28:30.70#ibcon#enter sib2, iclass 32, count 2 2006.285.22:28:30.70#ibcon#flushed, iclass 32, count 2 2006.285.22:28:30.70#ibcon#about to write, iclass 32, count 2 2006.285.22:28:30.70#ibcon#wrote, iclass 32, count 2 2006.285.22:28:30.70#ibcon#about to read 3, iclass 32, count 2 2006.285.22:28:30.71#ibcon#read 3, iclass 32, count 2 2006.285.22:28:30.71#ibcon#about to read 4, iclass 32, count 2 2006.285.22:28:30.71#ibcon#read 4, iclass 32, count 2 2006.285.22:28:30.71#ibcon#about to read 5, iclass 32, count 2 2006.285.22:28:30.71#ibcon#read 5, iclass 32, count 2 2006.285.22:28:30.71#ibcon#about to read 6, iclass 32, count 2 2006.285.22:28:30.71#ibcon#read 6, iclass 32, count 2 2006.285.22:28:30.71#ibcon#end of sib2, iclass 32, count 2 2006.285.22:28:30.71#ibcon#*mode == 0, iclass 32, count 2 2006.285.22:28:30.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.22:28:30.72#ibcon#[27=AT01-04\r\n] 2006.285.22:28:30.72#ibcon#*before write, iclass 32, count 2 2006.285.22:28:30.72#ibcon#enter sib2, iclass 32, count 2 2006.285.22:28:30.72#ibcon#flushed, iclass 32, count 2 2006.285.22:28:30.72#ibcon#about to write, iclass 32, count 2 2006.285.22:28:30.72#ibcon#wrote, iclass 32, count 2 2006.285.22:28:30.72#ibcon#about to read 3, iclass 32, count 2 2006.285.22:28:30.74#ibcon#read 3, iclass 32, count 2 2006.285.22:28:30.74#ibcon#about to read 4, iclass 32, count 2 2006.285.22:28:30.74#ibcon#read 4, iclass 32, count 2 2006.285.22:28:30.74#ibcon#about to read 5, iclass 32, count 2 2006.285.22:28:30.74#ibcon#read 5, iclass 32, count 2 2006.285.22:28:30.74#ibcon#about to read 6, iclass 32, count 2 2006.285.22:28:30.74#ibcon#read 6, iclass 32, count 2 2006.285.22:28:30.74#ibcon#end of sib2, iclass 32, count 2 2006.285.22:28:30.74#ibcon#*after write, iclass 32, count 2 2006.285.22:28:30.74#ibcon#*before return 0, iclass 32, count 2 2006.285.22:28:30.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:28:30.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.22:28:30.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.22:28:30.75#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:30.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:28:30.86#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:28:30.86#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:28:30.86#ibcon#enter wrdev, iclass 32, count 0 2006.285.22:28:30.86#ibcon#first serial, iclass 32, count 0 2006.285.22:28:30.86#ibcon#enter sib2, iclass 32, count 0 2006.285.22:28:30.86#ibcon#flushed, iclass 32, count 0 2006.285.22:28:30.86#ibcon#about to write, iclass 32, count 0 2006.285.22:28:30.86#ibcon#wrote, iclass 32, count 0 2006.285.22:28:30.86#ibcon#about to read 3, iclass 32, count 0 2006.285.22:28:30.88#ibcon#read 3, iclass 32, count 0 2006.285.22:28:30.88#ibcon#about to read 4, iclass 32, count 0 2006.285.22:28:30.88#ibcon#read 4, iclass 32, count 0 2006.285.22:28:30.88#ibcon#about to read 5, iclass 32, count 0 2006.285.22:28:30.88#ibcon#read 5, iclass 32, count 0 2006.285.22:28:30.88#ibcon#about to read 6, iclass 32, count 0 2006.285.22:28:30.88#ibcon#read 6, iclass 32, count 0 2006.285.22:28:30.88#ibcon#end of sib2, iclass 32, count 0 2006.285.22:28:30.88#ibcon#*mode == 0, iclass 32, count 0 2006.285.22:28:30.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.22:28:30.89#ibcon#[27=USB\r\n] 2006.285.22:28:30.89#ibcon#*before write, iclass 32, count 0 2006.285.22:28:30.89#ibcon#enter sib2, iclass 32, count 0 2006.285.22:28:30.89#ibcon#flushed, iclass 32, count 0 2006.285.22:28:30.89#ibcon#about to write, iclass 32, count 0 2006.285.22:28:30.89#ibcon#wrote, iclass 32, count 0 2006.285.22:28:30.89#ibcon#about to read 3, iclass 32, count 0 2006.285.22:28:30.91#ibcon#read 3, iclass 32, count 0 2006.285.22:28:30.91#ibcon#about to read 4, iclass 32, count 0 2006.285.22:28:30.91#ibcon#read 4, iclass 32, count 0 2006.285.22:28:30.91#ibcon#about to read 5, iclass 32, count 0 2006.285.22:28:30.91#ibcon#read 5, iclass 32, count 0 2006.285.22:28:30.91#ibcon#about to read 6, iclass 32, count 0 2006.285.22:28:30.91#ibcon#read 6, iclass 32, count 0 2006.285.22:28:30.91#ibcon#end of sib2, iclass 32, count 0 2006.285.22:28:30.91#ibcon#*after write, iclass 32, count 0 2006.285.22:28:30.91#ibcon#*before return 0, iclass 32, count 0 2006.285.22:28:30.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:28:30.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.22:28:30.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.22:28:30.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.22:28:30.92$vck44/vblo=2,634.99 2006.285.22:28:30.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.22:28:30.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.22:28:30.92#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:30.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:28:30.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:28:30.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:28:30.92#ibcon#enter wrdev, iclass 34, count 0 2006.285.22:28:30.92#ibcon#first serial, iclass 34, count 0 2006.285.22:28:30.92#ibcon#enter sib2, iclass 34, count 0 2006.285.22:28:30.92#ibcon#flushed, iclass 34, count 0 2006.285.22:28:30.92#ibcon#about to write, iclass 34, count 0 2006.285.22:28:30.92#ibcon#wrote, iclass 34, count 0 2006.285.22:28:30.92#ibcon#about to read 3, iclass 34, count 0 2006.285.22:28:30.93#ibcon#read 3, iclass 34, count 0 2006.285.22:28:30.93#ibcon#about to read 4, iclass 34, count 0 2006.285.22:28:30.93#ibcon#read 4, iclass 34, count 0 2006.285.22:28:30.93#ibcon#about to read 5, iclass 34, count 0 2006.285.22:28:30.93#ibcon#read 5, iclass 34, count 0 2006.285.22:28:30.93#ibcon#about to read 6, iclass 34, count 0 2006.285.22:28:30.93#ibcon#read 6, iclass 34, count 0 2006.285.22:28:30.93#ibcon#end of sib2, iclass 34, count 0 2006.285.22:28:30.93#ibcon#*mode == 0, iclass 34, count 0 2006.285.22:28:30.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.22:28:30.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:28:30.94#ibcon#*before write, iclass 34, count 0 2006.285.22:28:30.94#ibcon#enter sib2, iclass 34, count 0 2006.285.22:28:30.94#ibcon#flushed, iclass 34, count 0 2006.285.22:28:30.94#ibcon#about to write, iclass 34, count 0 2006.285.22:28:30.94#ibcon#wrote, iclass 34, count 0 2006.285.22:28:30.94#ibcon#about to read 3, iclass 34, count 0 2006.285.22:28:30.97#ibcon#read 3, iclass 34, count 0 2006.285.22:28:30.97#ibcon#about to read 4, iclass 34, count 0 2006.285.22:28:30.97#ibcon#read 4, iclass 34, count 0 2006.285.22:28:30.97#ibcon#about to read 5, iclass 34, count 0 2006.285.22:28:30.97#ibcon#read 5, iclass 34, count 0 2006.285.22:28:30.97#ibcon#about to read 6, iclass 34, count 0 2006.285.22:28:30.97#ibcon#read 6, iclass 34, count 0 2006.285.22:28:30.97#ibcon#end of sib2, iclass 34, count 0 2006.285.22:28:30.97#ibcon#*after write, iclass 34, count 0 2006.285.22:28:30.98#ibcon#*before return 0, iclass 34, count 0 2006.285.22:28:30.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:28:30.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.22:28:30.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.22:28:30.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.22:28:30.98$vck44/vb=2,5 2006.285.22:28:30.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.22:28:30.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.22:28:30.98#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:30.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:28:31.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:28:31.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:28:31.04#ibcon#enter wrdev, iclass 36, count 2 2006.285.22:28:31.04#ibcon#first serial, iclass 36, count 2 2006.285.22:28:31.04#ibcon#enter sib2, iclass 36, count 2 2006.285.22:28:31.04#ibcon#flushed, iclass 36, count 2 2006.285.22:28:31.04#ibcon#about to write, iclass 36, count 2 2006.285.22:28:31.04#ibcon#wrote, iclass 36, count 2 2006.285.22:28:31.04#ibcon#about to read 3, iclass 36, count 2 2006.285.22:28:31.05#ibcon#read 3, iclass 36, count 2 2006.285.22:28:31.05#ibcon#about to read 4, iclass 36, count 2 2006.285.22:28:31.05#ibcon#read 4, iclass 36, count 2 2006.285.22:28:31.05#ibcon#about to read 5, iclass 36, count 2 2006.285.22:28:31.05#ibcon#read 5, iclass 36, count 2 2006.285.22:28:31.05#ibcon#about to read 6, iclass 36, count 2 2006.285.22:28:31.05#ibcon#read 6, iclass 36, count 2 2006.285.22:28:31.05#ibcon#end of sib2, iclass 36, count 2 2006.285.22:28:31.05#ibcon#*mode == 0, iclass 36, count 2 2006.285.22:28:31.05#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.22:28:31.06#ibcon#[27=AT02-05\r\n] 2006.285.22:28:31.06#ibcon#*before write, iclass 36, count 2 2006.285.22:28:31.06#ibcon#enter sib2, iclass 36, count 2 2006.285.22:28:31.06#ibcon#flushed, iclass 36, count 2 2006.285.22:28:31.06#ibcon#about to write, iclass 36, count 2 2006.285.22:28:31.06#ibcon#wrote, iclass 36, count 2 2006.285.22:28:31.06#ibcon#about to read 3, iclass 36, count 2 2006.285.22:28:31.08#ibcon#read 3, iclass 36, count 2 2006.285.22:28:31.08#ibcon#about to read 4, iclass 36, count 2 2006.285.22:28:31.08#ibcon#read 4, iclass 36, count 2 2006.285.22:28:31.08#ibcon#about to read 5, iclass 36, count 2 2006.285.22:28:31.08#ibcon#read 5, iclass 36, count 2 2006.285.22:28:31.08#ibcon#about to read 6, iclass 36, count 2 2006.285.22:28:31.08#ibcon#read 6, iclass 36, count 2 2006.285.22:28:31.08#ibcon#end of sib2, iclass 36, count 2 2006.285.22:28:31.08#ibcon#*after write, iclass 36, count 2 2006.285.22:28:31.09#ibcon#*before return 0, iclass 36, count 2 2006.285.22:28:31.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:28:31.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.22:28:31.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.22:28:31.09#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:31.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:28:31.20#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:28:31.20#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:28:31.20#ibcon#enter wrdev, iclass 36, count 0 2006.285.22:28:31.20#ibcon#first serial, iclass 36, count 0 2006.285.22:28:31.20#ibcon#enter sib2, iclass 36, count 0 2006.285.22:28:31.20#ibcon#flushed, iclass 36, count 0 2006.285.22:28:31.20#ibcon#about to write, iclass 36, count 0 2006.285.22:28:31.21#ibcon#wrote, iclass 36, count 0 2006.285.22:28:31.21#ibcon#about to read 3, iclass 36, count 0 2006.285.22:28:31.22#ibcon#read 3, iclass 36, count 0 2006.285.22:28:31.22#ibcon#about to read 4, iclass 36, count 0 2006.285.22:28:31.22#ibcon#read 4, iclass 36, count 0 2006.285.22:28:31.22#ibcon#about to read 5, iclass 36, count 0 2006.285.22:28:31.22#ibcon#read 5, iclass 36, count 0 2006.285.22:28:31.22#ibcon#about to read 6, iclass 36, count 0 2006.285.22:28:31.22#ibcon#read 6, iclass 36, count 0 2006.285.22:28:31.22#ibcon#end of sib2, iclass 36, count 0 2006.285.22:28:31.22#ibcon#*mode == 0, iclass 36, count 0 2006.285.22:28:31.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.22:28:31.23#ibcon#[27=USB\r\n] 2006.285.22:28:31.23#ibcon#*before write, iclass 36, count 0 2006.285.22:28:31.23#ibcon#enter sib2, iclass 36, count 0 2006.285.22:28:31.23#ibcon#flushed, iclass 36, count 0 2006.285.22:28:31.23#ibcon#about to write, iclass 36, count 0 2006.285.22:28:31.23#ibcon#wrote, iclass 36, count 0 2006.285.22:28:31.23#ibcon#about to read 3, iclass 36, count 0 2006.285.22:28:31.25#ibcon#read 3, iclass 36, count 0 2006.285.22:28:31.25#ibcon#about to read 4, iclass 36, count 0 2006.285.22:28:31.25#ibcon#read 4, iclass 36, count 0 2006.285.22:28:31.25#ibcon#about to read 5, iclass 36, count 0 2006.285.22:28:31.25#ibcon#read 5, iclass 36, count 0 2006.285.22:28:31.25#ibcon#about to read 6, iclass 36, count 0 2006.285.22:28:31.25#ibcon#read 6, iclass 36, count 0 2006.285.22:28:31.25#ibcon#end of sib2, iclass 36, count 0 2006.285.22:28:31.25#ibcon#*after write, iclass 36, count 0 2006.285.22:28:31.25#ibcon#*before return 0, iclass 36, count 0 2006.285.22:28:31.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:28:31.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.22:28:31.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.22:28:31.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.22:28:31.26$vck44/vblo=3,649.99 2006.285.22:28:31.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.22:28:31.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.22:28:31.26#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:31.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:28:31.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:28:31.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:28:31.26#ibcon#enter wrdev, iclass 38, count 0 2006.285.22:28:31.26#ibcon#first serial, iclass 38, count 0 2006.285.22:28:31.26#ibcon#enter sib2, iclass 38, count 0 2006.285.22:28:31.26#ibcon#flushed, iclass 38, count 0 2006.285.22:28:31.26#ibcon#about to write, iclass 38, count 0 2006.285.22:28:31.26#ibcon#wrote, iclass 38, count 0 2006.285.22:28:31.26#ibcon#about to read 3, iclass 38, count 0 2006.285.22:28:31.27#ibcon#read 3, iclass 38, count 0 2006.285.22:28:31.27#ibcon#about to read 4, iclass 38, count 0 2006.285.22:28:31.27#ibcon#read 4, iclass 38, count 0 2006.285.22:28:31.27#ibcon#about to read 5, iclass 38, count 0 2006.285.22:28:31.27#ibcon#read 5, iclass 38, count 0 2006.285.22:28:31.27#ibcon#about to read 6, iclass 38, count 0 2006.285.22:28:31.27#ibcon#read 6, iclass 38, count 0 2006.285.22:28:31.27#ibcon#end of sib2, iclass 38, count 0 2006.285.22:28:31.27#ibcon#*mode == 0, iclass 38, count 0 2006.285.22:28:31.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.22:28:31.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:28:31.28#ibcon#*before write, iclass 38, count 0 2006.285.22:28:31.28#ibcon#enter sib2, iclass 38, count 0 2006.285.22:28:31.28#ibcon#flushed, iclass 38, count 0 2006.285.22:28:31.28#ibcon#about to write, iclass 38, count 0 2006.285.22:28:31.28#ibcon#wrote, iclass 38, count 0 2006.285.22:28:31.28#ibcon#about to read 3, iclass 38, count 0 2006.285.22:28:31.31#ibcon#read 3, iclass 38, count 0 2006.285.22:28:31.31#ibcon#about to read 4, iclass 38, count 0 2006.285.22:28:31.31#ibcon#read 4, iclass 38, count 0 2006.285.22:28:31.31#ibcon#about to read 5, iclass 38, count 0 2006.285.22:28:31.31#ibcon#read 5, iclass 38, count 0 2006.285.22:28:31.31#ibcon#about to read 6, iclass 38, count 0 2006.285.22:28:31.31#ibcon#read 6, iclass 38, count 0 2006.285.22:28:31.31#ibcon#end of sib2, iclass 38, count 0 2006.285.22:28:31.31#ibcon#*after write, iclass 38, count 0 2006.285.22:28:31.31#ibcon#*before return 0, iclass 38, count 0 2006.285.22:28:31.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:28:31.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.22:28:31.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.22:28:31.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.22:28:31.32$vck44/vb=3,4 2006.285.22:28:31.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.22:28:31.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.22:28:31.32#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:31.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:28:31.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:28:31.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:28:31.37#ibcon#enter wrdev, iclass 40, count 2 2006.285.22:28:31.37#ibcon#first serial, iclass 40, count 2 2006.285.22:28:31.37#ibcon#enter sib2, iclass 40, count 2 2006.285.22:28:31.37#ibcon#flushed, iclass 40, count 2 2006.285.22:28:31.37#ibcon#about to write, iclass 40, count 2 2006.285.22:28:31.37#ibcon#wrote, iclass 40, count 2 2006.285.22:28:31.37#ibcon#about to read 3, iclass 40, count 2 2006.285.22:28:31.39#ibcon#read 3, iclass 40, count 2 2006.285.22:28:31.39#ibcon#about to read 4, iclass 40, count 2 2006.285.22:28:31.39#ibcon#read 4, iclass 40, count 2 2006.285.22:28:31.39#ibcon#about to read 5, iclass 40, count 2 2006.285.22:28:31.39#ibcon#read 5, iclass 40, count 2 2006.285.22:28:31.39#ibcon#about to read 6, iclass 40, count 2 2006.285.22:28:31.39#ibcon#read 6, iclass 40, count 2 2006.285.22:28:31.39#ibcon#end of sib2, iclass 40, count 2 2006.285.22:28:31.39#ibcon#*mode == 0, iclass 40, count 2 2006.285.22:28:31.39#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.22:28:31.40#ibcon#[27=AT03-04\r\n] 2006.285.22:28:31.40#ibcon#*before write, iclass 40, count 2 2006.285.22:28:31.40#ibcon#enter sib2, iclass 40, count 2 2006.285.22:28:31.40#ibcon#flushed, iclass 40, count 2 2006.285.22:28:31.40#ibcon#about to write, iclass 40, count 2 2006.285.22:28:31.40#ibcon#wrote, iclass 40, count 2 2006.285.22:28:31.40#ibcon#about to read 3, iclass 40, count 2 2006.285.22:28:31.42#ibcon#read 3, iclass 40, count 2 2006.285.22:28:31.42#ibcon#about to read 4, iclass 40, count 2 2006.285.22:28:31.42#ibcon#read 4, iclass 40, count 2 2006.285.22:28:31.42#ibcon#about to read 5, iclass 40, count 2 2006.285.22:28:31.42#ibcon#read 5, iclass 40, count 2 2006.285.22:28:31.42#ibcon#about to read 6, iclass 40, count 2 2006.285.22:28:31.43#ibcon#read 6, iclass 40, count 2 2006.285.22:28:31.43#ibcon#end of sib2, iclass 40, count 2 2006.285.22:28:31.43#ibcon#*after write, iclass 40, count 2 2006.285.22:28:31.43#ibcon#*before return 0, iclass 40, count 2 2006.285.22:28:31.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:28:31.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.22:28:31.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.22:28:31.43#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:31.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:28:31.54#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:28:31.54#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:28:31.54#ibcon#enter wrdev, iclass 40, count 0 2006.285.22:28:31.54#ibcon#first serial, iclass 40, count 0 2006.285.22:28:31.54#ibcon#enter sib2, iclass 40, count 0 2006.285.22:28:31.54#ibcon#flushed, iclass 40, count 0 2006.285.22:28:31.54#ibcon#about to write, iclass 40, count 0 2006.285.22:28:31.55#ibcon#wrote, iclass 40, count 0 2006.285.22:28:31.55#ibcon#about to read 3, iclass 40, count 0 2006.285.22:28:31.56#ibcon#read 3, iclass 40, count 0 2006.285.22:28:31.56#ibcon#about to read 4, iclass 40, count 0 2006.285.22:28:31.56#ibcon#read 4, iclass 40, count 0 2006.285.22:28:31.56#ibcon#about to read 5, iclass 40, count 0 2006.285.22:28:31.56#ibcon#read 5, iclass 40, count 0 2006.285.22:28:31.56#ibcon#about to read 6, iclass 40, count 0 2006.285.22:28:31.56#ibcon#read 6, iclass 40, count 0 2006.285.22:28:31.56#ibcon#end of sib2, iclass 40, count 0 2006.285.22:28:31.56#ibcon#*mode == 0, iclass 40, count 0 2006.285.22:28:31.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.22:28:31.57#ibcon#[27=USB\r\n] 2006.285.22:28:31.57#ibcon#*before write, iclass 40, count 0 2006.285.22:28:31.57#ibcon#enter sib2, iclass 40, count 0 2006.285.22:28:31.57#ibcon#flushed, iclass 40, count 0 2006.285.22:28:31.57#ibcon#about to write, iclass 40, count 0 2006.285.22:28:31.57#ibcon#wrote, iclass 40, count 0 2006.285.22:28:31.57#ibcon#about to read 3, iclass 40, count 0 2006.285.22:28:31.59#ibcon#read 3, iclass 40, count 0 2006.285.22:28:31.59#ibcon#about to read 4, iclass 40, count 0 2006.285.22:28:31.59#ibcon#read 4, iclass 40, count 0 2006.285.22:28:31.59#ibcon#about to read 5, iclass 40, count 0 2006.285.22:28:31.59#ibcon#read 5, iclass 40, count 0 2006.285.22:28:31.59#ibcon#about to read 6, iclass 40, count 0 2006.285.22:28:31.59#ibcon#read 6, iclass 40, count 0 2006.285.22:28:31.59#ibcon#end of sib2, iclass 40, count 0 2006.285.22:28:31.59#ibcon#*after write, iclass 40, count 0 2006.285.22:28:31.59#ibcon#*before return 0, iclass 40, count 0 2006.285.22:28:31.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:28:31.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.22:28:31.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.22:28:31.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.22:28:31.60$vck44/vblo=4,679.99 2006.285.22:28:31.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.22:28:31.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.22:28:31.60#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:31.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:28:31.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:28:31.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:28:31.60#ibcon#enter wrdev, iclass 4, count 0 2006.285.22:28:31.60#ibcon#first serial, iclass 4, count 0 2006.285.22:28:31.60#ibcon#enter sib2, iclass 4, count 0 2006.285.22:28:31.60#ibcon#flushed, iclass 4, count 0 2006.285.22:28:31.60#ibcon#about to write, iclass 4, count 0 2006.285.22:28:31.60#ibcon#wrote, iclass 4, count 0 2006.285.22:28:31.60#ibcon#about to read 3, iclass 4, count 0 2006.285.22:28:31.61#ibcon#read 3, iclass 4, count 0 2006.285.22:28:31.61#ibcon#about to read 4, iclass 4, count 0 2006.285.22:28:31.61#ibcon#read 4, iclass 4, count 0 2006.285.22:28:31.61#ibcon#about to read 5, iclass 4, count 0 2006.285.22:28:31.61#ibcon#read 5, iclass 4, count 0 2006.285.22:28:31.61#ibcon#about to read 6, iclass 4, count 0 2006.285.22:28:31.62#ibcon#read 6, iclass 4, count 0 2006.285.22:28:31.62#ibcon#end of sib2, iclass 4, count 0 2006.285.22:28:31.62#ibcon#*mode == 0, iclass 4, count 0 2006.285.22:28:31.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.22:28:31.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.22:28:31.62#ibcon#*before write, iclass 4, count 0 2006.285.22:28:31.62#ibcon#enter sib2, iclass 4, count 0 2006.285.22:28:31.62#ibcon#flushed, iclass 4, count 0 2006.285.22:28:31.62#ibcon#about to write, iclass 4, count 0 2006.285.22:28:31.62#ibcon#wrote, iclass 4, count 0 2006.285.22:28:31.62#ibcon#about to read 3, iclass 4, count 0 2006.285.22:28:31.65#ibcon#read 3, iclass 4, count 0 2006.285.22:28:31.65#ibcon#about to read 4, iclass 4, count 0 2006.285.22:28:31.65#ibcon#read 4, iclass 4, count 0 2006.285.22:28:31.65#ibcon#about to read 5, iclass 4, count 0 2006.285.22:28:31.65#ibcon#read 5, iclass 4, count 0 2006.285.22:28:31.65#ibcon#about to read 6, iclass 4, count 0 2006.285.22:28:31.65#ibcon#read 6, iclass 4, count 0 2006.285.22:28:31.65#ibcon#end of sib2, iclass 4, count 0 2006.285.22:28:31.65#ibcon#*after write, iclass 4, count 0 2006.285.22:28:31.65#ibcon#*before return 0, iclass 4, count 0 2006.285.22:28:31.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:28:31.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.22:28:31.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.22:28:31.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.22:28:31.66$vck44/vb=4,5 2006.285.22:28:31.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.22:28:31.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.22:28:31.66#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:31.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:28:31.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:28:31.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:28:31.71#ibcon#enter wrdev, iclass 6, count 2 2006.285.22:28:31.71#ibcon#first serial, iclass 6, count 2 2006.285.22:28:31.71#ibcon#enter sib2, iclass 6, count 2 2006.285.22:28:31.71#ibcon#flushed, iclass 6, count 2 2006.285.22:28:31.71#ibcon#about to write, iclass 6, count 2 2006.285.22:28:31.71#ibcon#wrote, iclass 6, count 2 2006.285.22:28:31.71#ibcon#about to read 3, iclass 6, count 2 2006.285.22:28:31.73#ibcon#read 3, iclass 6, count 2 2006.285.22:28:31.73#ibcon#about to read 4, iclass 6, count 2 2006.285.22:28:31.73#ibcon#read 4, iclass 6, count 2 2006.285.22:28:31.73#ibcon#about to read 5, iclass 6, count 2 2006.285.22:28:31.73#ibcon#read 5, iclass 6, count 2 2006.285.22:28:31.73#ibcon#about to read 6, iclass 6, count 2 2006.285.22:28:31.73#ibcon#read 6, iclass 6, count 2 2006.285.22:28:31.73#ibcon#end of sib2, iclass 6, count 2 2006.285.22:28:31.73#ibcon#*mode == 0, iclass 6, count 2 2006.285.22:28:31.73#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.22:28:31.74#ibcon#[27=AT04-05\r\n] 2006.285.22:28:31.74#ibcon#*before write, iclass 6, count 2 2006.285.22:28:31.74#ibcon#enter sib2, iclass 6, count 2 2006.285.22:28:31.74#ibcon#flushed, iclass 6, count 2 2006.285.22:28:31.74#ibcon#about to write, iclass 6, count 2 2006.285.22:28:31.74#ibcon#wrote, iclass 6, count 2 2006.285.22:28:31.74#ibcon#about to read 3, iclass 6, count 2 2006.285.22:28:31.76#ibcon#read 3, iclass 6, count 2 2006.285.22:28:31.76#ibcon#about to read 4, iclass 6, count 2 2006.285.22:28:31.76#ibcon#read 4, iclass 6, count 2 2006.285.22:28:31.76#ibcon#about to read 5, iclass 6, count 2 2006.285.22:28:31.76#ibcon#read 5, iclass 6, count 2 2006.285.22:28:31.76#ibcon#about to read 6, iclass 6, count 2 2006.285.22:28:31.76#ibcon#read 6, iclass 6, count 2 2006.285.22:28:31.76#ibcon#end of sib2, iclass 6, count 2 2006.285.22:28:31.76#ibcon#*after write, iclass 6, count 2 2006.285.22:28:31.77#ibcon#*before return 0, iclass 6, count 2 2006.285.22:28:31.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:28:31.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.22:28:31.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.22:28:31.77#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:31.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:28:31.88#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:28:31.88#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:28:31.88#ibcon#enter wrdev, iclass 6, count 0 2006.285.22:28:31.88#ibcon#first serial, iclass 6, count 0 2006.285.22:28:31.88#ibcon#enter sib2, iclass 6, count 0 2006.285.22:28:31.88#ibcon#flushed, iclass 6, count 0 2006.285.22:28:31.88#ibcon#about to write, iclass 6, count 0 2006.285.22:28:31.88#ibcon#wrote, iclass 6, count 0 2006.285.22:28:31.88#ibcon#about to read 3, iclass 6, count 0 2006.285.22:28:31.90#ibcon#read 3, iclass 6, count 0 2006.285.22:28:31.90#ibcon#about to read 4, iclass 6, count 0 2006.285.22:28:31.90#ibcon#read 4, iclass 6, count 0 2006.285.22:28:31.90#ibcon#about to read 5, iclass 6, count 0 2006.285.22:28:31.90#ibcon#read 5, iclass 6, count 0 2006.285.22:28:31.90#ibcon#about to read 6, iclass 6, count 0 2006.285.22:28:31.90#ibcon#read 6, iclass 6, count 0 2006.285.22:28:31.90#ibcon#end of sib2, iclass 6, count 0 2006.285.22:28:31.90#ibcon#*mode == 0, iclass 6, count 0 2006.285.22:28:31.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.22:28:31.91#ibcon#[27=USB\r\n] 2006.285.22:28:31.91#ibcon#*before write, iclass 6, count 0 2006.285.22:28:31.91#ibcon#enter sib2, iclass 6, count 0 2006.285.22:28:31.91#ibcon#flushed, iclass 6, count 0 2006.285.22:28:31.91#ibcon#about to write, iclass 6, count 0 2006.285.22:28:31.91#ibcon#wrote, iclass 6, count 0 2006.285.22:28:31.91#ibcon#about to read 3, iclass 6, count 0 2006.285.22:28:31.93#ibcon#read 3, iclass 6, count 0 2006.285.22:28:31.93#ibcon#about to read 4, iclass 6, count 0 2006.285.22:28:31.93#ibcon#read 4, iclass 6, count 0 2006.285.22:28:31.93#ibcon#about to read 5, iclass 6, count 0 2006.285.22:28:31.93#ibcon#read 5, iclass 6, count 0 2006.285.22:28:31.93#ibcon#about to read 6, iclass 6, count 0 2006.285.22:28:31.93#ibcon#read 6, iclass 6, count 0 2006.285.22:28:31.93#ibcon#end of sib2, iclass 6, count 0 2006.285.22:28:31.93#ibcon#*after write, iclass 6, count 0 2006.285.22:28:31.93#ibcon#*before return 0, iclass 6, count 0 2006.285.22:28:31.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:28:31.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.22:28:31.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.22:28:31.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.22:28:31.94$vck44/vblo=5,709.99 2006.285.22:28:31.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.22:28:31.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.22:28:31.94#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:31.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:28:31.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:28:31.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:28:31.94#ibcon#enter wrdev, iclass 10, count 0 2006.285.22:28:31.94#ibcon#first serial, iclass 10, count 0 2006.285.22:28:31.94#ibcon#enter sib2, iclass 10, count 0 2006.285.22:28:31.94#ibcon#flushed, iclass 10, count 0 2006.285.22:28:31.94#ibcon#about to write, iclass 10, count 0 2006.285.22:28:31.94#ibcon#wrote, iclass 10, count 0 2006.285.22:28:31.94#ibcon#about to read 3, iclass 10, count 0 2006.285.22:28:31.95#ibcon#read 3, iclass 10, count 0 2006.285.22:28:31.95#ibcon#about to read 4, iclass 10, count 0 2006.285.22:28:31.95#ibcon#read 4, iclass 10, count 0 2006.285.22:28:31.95#ibcon#about to read 5, iclass 10, count 0 2006.285.22:28:31.95#ibcon#read 5, iclass 10, count 0 2006.285.22:28:31.95#ibcon#about to read 6, iclass 10, count 0 2006.285.22:28:31.95#ibcon#read 6, iclass 10, count 0 2006.285.22:28:31.95#ibcon#end of sib2, iclass 10, count 0 2006.285.22:28:31.95#ibcon#*mode == 0, iclass 10, count 0 2006.285.22:28:31.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.22:28:31.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.22:28:31.96#ibcon#*before write, iclass 10, count 0 2006.285.22:28:31.96#ibcon#enter sib2, iclass 10, count 0 2006.285.22:28:31.96#ibcon#flushed, iclass 10, count 0 2006.285.22:28:31.96#ibcon#about to write, iclass 10, count 0 2006.285.22:28:31.96#ibcon#wrote, iclass 10, count 0 2006.285.22:28:31.96#ibcon#about to read 3, iclass 10, count 0 2006.285.22:28:31.99#ibcon#read 3, iclass 10, count 0 2006.285.22:28:31.99#ibcon#about to read 4, iclass 10, count 0 2006.285.22:28:31.99#ibcon#read 4, iclass 10, count 0 2006.285.22:28:31.99#ibcon#about to read 5, iclass 10, count 0 2006.285.22:28:31.99#ibcon#read 5, iclass 10, count 0 2006.285.22:28:31.99#ibcon#about to read 6, iclass 10, count 0 2006.285.22:28:31.99#ibcon#read 6, iclass 10, count 0 2006.285.22:28:31.99#ibcon#end of sib2, iclass 10, count 0 2006.285.22:28:31.99#ibcon#*after write, iclass 10, count 0 2006.285.22:28:31.99#ibcon#*before return 0, iclass 10, count 0 2006.285.22:28:32.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:28:32.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.22:28:32.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.22:28:32.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.22:28:32.00$vck44/vb=5,4 2006.285.22:28:32.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.22:28:32.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.22:28:32.00#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:32.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:28:32.05#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:28:32.05#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:28:32.05#ibcon#enter wrdev, iclass 12, count 2 2006.285.22:28:32.05#ibcon#first serial, iclass 12, count 2 2006.285.22:28:32.05#ibcon#enter sib2, iclass 12, count 2 2006.285.22:28:32.05#ibcon#flushed, iclass 12, count 2 2006.285.22:28:32.05#ibcon#about to write, iclass 12, count 2 2006.285.22:28:32.05#ibcon#wrote, iclass 12, count 2 2006.285.22:28:32.05#ibcon#about to read 3, iclass 12, count 2 2006.285.22:28:32.07#ibcon#read 3, iclass 12, count 2 2006.285.22:28:32.07#ibcon#about to read 4, iclass 12, count 2 2006.285.22:28:32.07#ibcon#read 4, iclass 12, count 2 2006.285.22:28:32.07#ibcon#about to read 5, iclass 12, count 2 2006.285.22:28:32.07#ibcon#read 5, iclass 12, count 2 2006.285.22:28:32.07#ibcon#about to read 6, iclass 12, count 2 2006.285.22:28:32.07#ibcon#read 6, iclass 12, count 2 2006.285.22:28:32.07#ibcon#end of sib2, iclass 12, count 2 2006.285.22:28:32.08#ibcon#*mode == 0, iclass 12, count 2 2006.285.22:28:32.08#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.22:28:32.08#ibcon#[27=AT05-04\r\n] 2006.285.22:28:32.08#ibcon#*before write, iclass 12, count 2 2006.285.22:28:32.08#ibcon#enter sib2, iclass 12, count 2 2006.285.22:28:32.08#ibcon#flushed, iclass 12, count 2 2006.285.22:28:32.08#ibcon#about to write, iclass 12, count 2 2006.285.22:28:32.08#ibcon#wrote, iclass 12, count 2 2006.285.22:28:32.08#ibcon#about to read 3, iclass 12, count 2 2006.285.22:28:32.10#ibcon#read 3, iclass 12, count 2 2006.285.22:28:32.10#ibcon#about to read 4, iclass 12, count 2 2006.285.22:28:32.10#ibcon#read 4, iclass 12, count 2 2006.285.22:28:32.10#ibcon#about to read 5, iclass 12, count 2 2006.285.22:28:32.10#ibcon#read 5, iclass 12, count 2 2006.285.22:28:32.10#ibcon#about to read 6, iclass 12, count 2 2006.285.22:28:32.10#ibcon#read 6, iclass 12, count 2 2006.285.22:28:32.10#ibcon#end of sib2, iclass 12, count 2 2006.285.22:28:32.10#ibcon#*after write, iclass 12, count 2 2006.285.22:28:32.10#ibcon#*before return 0, iclass 12, count 2 2006.285.22:28:32.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:28:32.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.22:28:32.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.22:28:32.11#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:32.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:28:32.22#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:28:32.22#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:28:32.22#ibcon#enter wrdev, iclass 12, count 0 2006.285.22:28:32.22#ibcon#first serial, iclass 12, count 0 2006.285.22:28:32.22#ibcon#enter sib2, iclass 12, count 0 2006.285.22:28:32.22#ibcon#flushed, iclass 12, count 0 2006.285.22:28:32.22#ibcon#about to write, iclass 12, count 0 2006.285.22:28:32.23#ibcon#wrote, iclass 12, count 0 2006.285.22:28:32.23#ibcon#about to read 3, iclass 12, count 0 2006.285.22:28:32.24#ibcon#read 3, iclass 12, count 0 2006.285.22:28:32.24#ibcon#about to read 4, iclass 12, count 0 2006.285.22:28:32.24#ibcon#read 4, iclass 12, count 0 2006.285.22:28:32.24#ibcon#about to read 5, iclass 12, count 0 2006.285.22:28:32.24#ibcon#read 5, iclass 12, count 0 2006.285.22:28:32.24#ibcon#about to read 6, iclass 12, count 0 2006.285.22:28:32.24#ibcon#read 6, iclass 12, count 0 2006.285.22:28:32.24#ibcon#end of sib2, iclass 12, count 0 2006.285.22:28:32.24#ibcon#*mode == 0, iclass 12, count 0 2006.285.22:28:32.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.22:28:32.25#ibcon#[27=USB\r\n] 2006.285.22:28:32.25#ibcon#*before write, iclass 12, count 0 2006.285.22:28:32.25#ibcon#enter sib2, iclass 12, count 0 2006.285.22:28:32.25#ibcon#flushed, iclass 12, count 0 2006.285.22:28:32.25#ibcon#about to write, iclass 12, count 0 2006.285.22:28:32.25#ibcon#wrote, iclass 12, count 0 2006.285.22:28:32.25#ibcon#about to read 3, iclass 12, count 0 2006.285.22:28:32.27#ibcon#read 3, iclass 12, count 0 2006.285.22:28:32.27#ibcon#about to read 4, iclass 12, count 0 2006.285.22:28:32.27#ibcon#read 4, iclass 12, count 0 2006.285.22:28:32.27#ibcon#about to read 5, iclass 12, count 0 2006.285.22:28:32.27#ibcon#read 5, iclass 12, count 0 2006.285.22:28:32.27#ibcon#about to read 6, iclass 12, count 0 2006.285.22:28:32.27#ibcon#read 6, iclass 12, count 0 2006.285.22:28:32.27#ibcon#end of sib2, iclass 12, count 0 2006.285.22:28:32.27#ibcon#*after write, iclass 12, count 0 2006.285.22:28:32.28#ibcon#*before return 0, iclass 12, count 0 2006.285.22:28:32.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:28:32.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.22:28:32.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.22:28:32.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.22:28:32.28$vck44/vblo=6,719.99 2006.285.22:28:32.28#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.22:28:32.28#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.22:28:32.28#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:32.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:28:32.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:28:32.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:28:32.28#ibcon#enter wrdev, iclass 14, count 0 2006.285.22:28:32.28#ibcon#first serial, iclass 14, count 0 2006.285.22:28:32.28#ibcon#enter sib2, iclass 14, count 0 2006.285.22:28:32.28#ibcon#flushed, iclass 14, count 0 2006.285.22:28:32.28#ibcon#about to write, iclass 14, count 0 2006.285.22:28:32.28#ibcon#wrote, iclass 14, count 0 2006.285.22:28:32.28#ibcon#about to read 3, iclass 14, count 0 2006.285.22:28:32.29#ibcon#read 3, iclass 14, count 0 2006.285.22:28:32.29#ibcon#about to read 4, iclass 14, count 0 2006.285.22:28:32.29#ibcon#read 4, iclass 14, count 0 2006.285.22:28:32.29#ibcon#about to read 5, iclass 14, count 0 2006.285.22:28:32.29#ibcon#read 5, iclass 14, count 0 2006.285.22:28:32.29#ibcon#about to read 6, iclass 14, count 0 2006.285.22:28:32.29#ibcon#read 6, iclass 14, count 0 2006.285.22:28:32.29#ibcon#end of sib2, iclass 14, count 0 2006.285.22:28:32.29#ibcon#*mode == 0, iclass 14, count 0 2006.285.22:28:32.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.22:28:32.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.22:28:32.30#ibcon#*before write, iclass 14, count 0 2006.285.22:28:32.30#ibcon#enter sib2, iclass 14, count 0 2006.285.22:28:32.30#ibcon#flushed, iclass 14, count 0 2006.285.22:28:32.30#ibcon#about to write, iclass 14, count 0 2006.285.22:28:32.30#ibcon#wrote, iclass 14, count 0 2006.285.22:28:32.30#ibcon#about to read 3, iclass 14, count 0 2006.285.22:28:32.33#ibcon#read 3, iclass 14, count 0 2006.285.22:28:32.33#ibcon#about to read 4, iclass 14, count 0 2006.285.22:28:32.33#ibcon#read 4, iclass 14, count 0 2006.285.22:28:32.33#ibcon#about to read 5, iclass 14, count 0 2006.285.22:28:32.33#ibcon#read 5, iclass 14, count 0 2006.285.22:28:32.33#ibcon#about to read 6, iclass 14, count 0 2006.285.22:28:32.33#ibcon#read 6, iclass 14, count 0 2006.285.22:28:32.33#ibcon#end of sib2, iclass 14, count 0 2006.285.22:28:32.33#ibcon#*after write, iclass 14, count 0 2006.285.22:28:32.33#ibcon#*before return 0, iclass 14, count 0 2006.285.22:28:32.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:28:32.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.22:28:32.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.22:28:32.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.22:28:32.34$vck44/vb=6,3 2006.285.22:28:32.34#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.22:28:32.34#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.22:28:32.34#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:32.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:28:32.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:28:32.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:28:32.39#ibcon#enter wrdev, iclass 16, count 2 2006.285.22:28:32.39#ibcon#first serial, iclass 16, count 2 2006.285.22:28:32.39#ibcon#enter sib2, iclass 16, count 2 2006.285.22:28:32.39#ibcon#flushed, iclass 16, count 2 2006.285.22:28:32.39#ibcon#about to write, iclass 16, count 2 2006.285.22:28:32.39#ibcon#wrote, iclass 16, count 2 2006.285.22:28:32.39#ibcon#about to read 3, iclass 16, count 2 2006.285.22:28:32.41#ibcon#read 3, iclass 16, count 2 2006.285.22:28:32.41#ibcon#about to read 4, iclass 16, count 2 2006.285.22:28:32.41#ibcon#read 4, iclass 16, count 2 2006.285.22:28:32.41#ibcon#about to read 5, iclass 16, count 2 2006.285.22:28:32.41#ibcon#read 5, iclass 16, count 2 2006.285.22:28:32.41#ibcon#about to read 6, iclass 16, count 2 2006.285.22:28:32.41#ibcon#read 6, iclass 16, count 2 2006.285.22:28:32.41#ibcon#end of sib2, iclass 16, count 2 2006.285.22:28:32.41#ibcon#*mode == 0, iclass 16, count 2 2006.285.22:28:32.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.22:28:32.42#ibcon#[27=AT06-03\r\n] 2006.285.22:28:32.42#ibcon#*before write, iclass 16, count 2 2006.285.22:28:32.42#ibcon#enter sib2, iclass 16, count 2 2006.285.22:28:32.42#ibcon#flushed, iclass 16, count 2 2006.285.22:28:32.42#ibcon#about to write, iclass 16, count 2 2006.285.22:28:32.42#ibcon#wrote, iclass 16, count 2 2006.285.22:28:32.42#ibcon#about to read 3, iclass 16, count 2 2006.285.22:28:32.44#ibcon#read 3, iclass 16, count 2 2006.285.22:28:32.44#ibcon#about to read 4, iclass 16, count 2 2006.285.22:28:32.44#ibcon#read 4, iclass 16, count 2 2006.285.22:28:32.44#ibcon#about to read 5, iclass 16, count 2 2006.285.22:28:32.44#ibcon#read 5, iclass 16, count 2 2006.285.22:28:32.44#ibcon#about to read 6, iclass 16, count 2 2006.285.22:28:32.45#ibcon#read 6, iclass 16, count 2 2006.285.22:28:32.45#ibcon#end of sib2, iclass 16, count 2 2006.285.22:28:32.45#ibcon#*after write, iclass 16, count 2 2006.285.22:28:32.45#ibcon#*before return 0, iclass 16, count 2 2006.285.22:28:32.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:28:32.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.22:28:32.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.22:28:32.45#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:32.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:28:32.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:28:32.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:28:32.56#ibcon#enter wrdev, iclass 16, count 0 2006.285.22:28:32.56#ibcon#first serial, iclass 16, count 0 2006.285.22:28:32.56#ibcon#enter sib2, iclass 16, count 0 2006.285.22:28:32.56#ibcon#flushed, iclass 16, count 0 2006.285.22:28:32.56#ibcon#about to write, iclass 16, count 0 2006.285.22:28:32.57#ibcon#wrote, iclass 16, count 0 2006.285.22:28:32.57#ibcon#about to read 3, iclass 16, count 0 2006.285.22:28:32.58#ibcon#read 3, iclass 16, count 0 2006.285.22:28:32.58#ibcon#about to read 4, iclass 16, count 0 2006.285.22:28:32.58#ibcon#read 4, iclass 16, count 0 2006.285.22:28:32.58#ibcon#about to read 5, iclass 16, count 0 2006.285.22:28:32.58#ibcon#read 5, iclass 16, count 0 2006.285.22:28:32.58#ibcon#about to read 6, iclass 16, count 0 2006.285.22:28:32.58#ibcon#read 6, iclass 16, count 0 2006.285.22:28:32.58#ibcon#end of sib2, iclass 16, count 0 2006.285.22:28:32.58#ibcon#*mode == 0, iclass 16, count 0 2006.285.22:28:32.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.22:28:32.59#ibcon#[27=USB\r\n] 2006.285.22:28:32.59#ibcon#*before write, iclass 16, count 0 2006.285.22:28:32.59#ibcon#enter sib2, iclass 16, count 0 2006.285.22:28:32.59#ibcon#flushed, iclass 16, count 0 2006.285.22:28:32.59#ibcon#about to write, iclass 16, count 0 2006.285.22:28:32.59#ibcon#wrote, iclass 16, count 0 2006.285.22:28:32.59#ibcon#about to read 3, iclass 16, count 0 2006.285.22:28:32.61#ibcon#read 3, iclass 16, count 0 2006.285.22:28:32.61#ibcon#about to read 4, iclass 16, count 0 2006.285.22:28:32.61#ibcon#read 4, iclass 16, count 0 2006.285.22:28:32.61#ibcon#about to read 5, iclass 16, count 0 2006.285.22:28:32.61#ibcon#read 5, iclass 16, count 0 2006.285.22:28:32.61#ibcon#about to read 6, iclass 16, count 0 2006.285.22:28:32.61#ibcon#read 6, iclass 16, count 0 2006.285.22:28:32.62#ibcon#end of sib2, iclass 16, count 0 2006.285.22:28:32.62#ibcon#*after write, iclass 16, count 0 2006.285.22:28:32.62#ibcon#*before return 0, iclass 16, count 0 2006.285.22:28:32.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:28:32.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.22:28:32.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.22:28:32.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.22:28:32.62$vck44/vblo=7,734.99 2006.285.22:28:32.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.22:28:32.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.22:28:32.62#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:32.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:28:32.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:28:32.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:28:32.62#ibcon#enter wrdev, iclass 18, count 0 2006.285.22:28:32.62#ibcon#first serial, iclass 18, count 0 2006.285.22:28:32.62#ibcon#enter sib2, iclass 18, count 0 2006.285.22:28:32.62#ibcon#flushed, iclass 18, count 0 2006.285.22:28:32.62#ibcon#about to write, iclass 18, count 0 2006.285.22:28:32.62#ibcon#wrote, iclass 18, count 0 2006.285.22:28:32.62#ibcon#about to read 3, iclass 18, count 0 2006.285.22:28:32.63#ibcon#read 3, iclass 18, count 0 2006.285.22:28:32.63#ibcon#about to read 4, iclass 18, count 0 2006.285.22:28:32.63#ibcon#read 4, iclass 18, count 0 2006.285.22:28:32.63#ibcon#about to read 5, iclass 18, count 0 2006.285.22:28:32.63#ibcon#read 5, iclass 18, count 0 2006.285.22:28:32.63#ibcon#about to read 6, iclass 18, count 0 2006.285.22:28:32.63#ibcon#read 6, iclass 18, count 0 2006.285.22:28:32.63#ibcon#end of sib2, iclass 18, count 0 2006.285.22:28:32.63#ibcon#*mode == 0, iclass 18, count 0 2006.285.22:28:32.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.22:28:32.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.22:28:32.64#ibcon#*before write, iclass 18, count 0 2006.285.22:28:32.64#ibcon#enter sib2, iclass 18, count 0 2006.285.22:28:32.64#ibcon#flushed, iclass 18, count 0 2006.285.22:28:32.64#ibcon#about to write, iclass 18, count 0 2006.285.22:28:32.64#ibcon#wrote, iclass 18, count 0 2006.285.22:28:32.64#ibcon#about to read 3, iclass 18, count 0 2006.285.22:28:32.67#ibcon#read 3, iclass 18, count 0 2006.285.22:28:32.67#ibcon#about to read 4, iclass 18, count 0 2006.285.22:28:32.67#ibcon#read 4, iclass 18, count 0 2006.285.22:28:32.67#ibcon#about to read 5, iclass 18, count 0 2006.285.22:28:32.67#ibcon#read 5, iclass 18, count 0 2006.285.22:28:32.67#ibcon#about to read 6, iclass 18, count 0 2006.285.22:28:32.67#ibcon#read 6, iclass 18, count 0 2006.285.22:28:32.67#ibcon#end of sib2, iclass 18, count 0 2006.285.22:28:32.67#ibcon#*after write, iclass 18, count 0 2006.285.22:28:32.67#ibcon#*before return 0, iclass 18, count 0 2006.285.22:28:32.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:28:32.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.22:28:32.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.22:28:32.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.22:28:32.68$vck44/vb=7,4 2006.285.22:28:32.68#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.22:28:32.68#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.22:28:32.68#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:32.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:28:32.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:28:32.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:28:32.73#ibcon#enter wrdev, iclass 20, count 2 2006.285.22:28:32.73#ibcon#first serial, iclass 20, count 2 2006.285.22:28:32.73#ibcon#enter sib2, iclass 20, count 2 2006.285.22:28:32.73#ibcon#flushed, iclass 20, count 2 2006.285.22:28:32.73#ibcon#about to write, iclass 20, count 2 2006.285.22:28:32.73#ibcon#wrote, iclass 20, count 2 2006.285.22:28:32.73#ibcon#about to read 3, iclass 20, count 2 2006.285.22:28:32.75#ibcon#read 3, iclass 20, count 2 2006.285.22:28:32.75#ibcon#about to read 4, iclass 20, count 2 2006.285.22:28:32.75#ibcon#read 4, iclass 20, count 2 2006.285.22:28:32.75#ibcon#about to read 5, iclass 20, count 2 2006.285.22:28:32.75#ibcon#read 5, iclass 20, count 2 2006.285.22:28:32.75#ibcon#about to read 6, iclass 20, count 2 2006.285.22:28:32.75#ibcon#read 6, iclass 20, count 2 2006.285.22:28:32.75#ibcon#end of sib2, iclass 20, count 2 2006.285.22:28:32.75#ibcon#*mode == 0, iclass 20, count 2 2006.285.22:28:32.75#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.22:28:32.75#ibcon#[27=AT07-04\r\n] 2006.285.22:28:32.76#ibcon#*before write, iclass 20, count 2 2006.285.22:28:32.76#ibcon#enter sib2, iclass 20, count 2 2006.285.22:28:32.76#ibcon#flushed, iclass 20, count 2 2006.285.22:28:32.76#ibcon#about to write, iclass 20, count 2 2006.285.22:28:32.76#ibcon#wrote, iclass 20, count 2 2006.285.22:28:32.76#ibcon#about to read 3, iclass 20, count 2 2006.285.22:28:32.78#ibcon#read 3, iclass 20, count 2 2006.285.22:28:32.78#ibcon#about to read 4, iclass 20, count 2 2006.285.22:28:32.78#ibcon#read 4, iclass 20, count 2 2006.285.22:28:32.78#ibcon#about to read 5, iclass 20, count 2 2006.285.22:28:32.78#ibcon#read 5, iclass 20, count 2 2006.285.22:28:32.78#ibcon#about to read 6, iclass 20, count 2 2006.285.22:28:32.78#ibcon#read 6, iclass 20, count 2 2006.285.22:28:32.78#ibcon#end of sib2, iclass 20, count 2 2006.285.22:28:32.78#ibcon#*after write, iclass 20, count 2 2006.285.22:28:32.78#ibcon#*before return 0, iclass 20, count 2 2006.285.22:28:32.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:28:32.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.22:28:32.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.22:28:32.79#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:32.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:28:32.90#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:28:32.90#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:28:32.90#ibcon#enter wrdev, iclass 20, count 0 2006.285.22:28:32.90#ibcon#first serial, iclass 20, count 0 2006.285.22:28:32.90#ibcon#enter sib2, iclass 20, count 0 2006.285.22:28:32.90#ibcon#flushed, iclass 20, count 0 2006.285.22:28:32.90#ibcon#about to write, iclass 20, count 0 2006.285.22:28:32.90#ibcon#wrote, iclass 20, count 0 2006.285.22:28:32.90#ibcon#about to read 3, iclass 20, count 0 2006.285.22:28:32.92#ibcon#read 3, iclass 20, count 0 2006.285.22:28:32.92#ibcon#about to read 4, iclass 20, count 0 2006.285.22:28:32.92#ibcon#read 4, iclass 20, count 0 2006.285.22:28:32.92#ibcon#about to read 5, iclass 20, count 0 2006.285.22:28:32.92#ibcon#read 5, iclass 20, count 0 2006.285.22:28:32.92#ibcon#about to read 6, iclass 20, count 0 2006.285.22:28:32.92#ibcon#read 6, iclass 20, count 0 2006.285.22:28:32.92#ibcon#end of sib2, iclass 20, count 0 2006.285.22:28:32.92#ibcon#*mode == 0, iclass 20, count 0 2006.285.22:28:32.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.22:28:32.92#ibcon#[27=USB\r\n] 2006.285.22:28:32.93#ibcon#*before write, iclass 20, count 0 2006.285.22:28:32.93#ibcon#enter sib2, iclass 20, count 0 2006.285.22:28:32.93#ibcon#flushed, iclass 20, count 0 2006.285.22:28:32.93#ibcon#about to write, iclass 20, count 0 2006.285.22:28:32.93#ibcon#wrote, iclass 20, count 0 2006.285.22:28:32.93#ibcon#about to read 3, iclass 20, count 0 2006.285.22:28:32.95#ibcon#read 3, iclass 20, count 0 2006.285.22:28:32.95#ibcon#about to read 4, iclass 20, count 0 2006.285.22:28:32.95#ibcon#read 4, iclass 20, count 0 2006.285.22:28:32.95#ibcon#about to read 5, iclass 20, count 0 2006.285.22:28:32.95#ibcon#read 5, iclass 20, count 0 2006.285.22:28:32.95#ibcon#about to read 6, iclass 20, count 0 2006.285.22:28:32.95#ibcon#read 6, iclass 20, count 0 2006.285.22:28:32.95#ibcon#end of sib2, iclass 20, count 0 2006.285.22:28:32.95#ibcon#*after write, iclass 20, count 0 2006.285.22:28:32.95#ibcon#*before return 0, iclass 20, count 0 2006.285.22:28:32.96#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:28:32.96#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.22:28:32.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.22:28:32.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.22:28:32.96$vck44/vblo=8,744.99 2006.285.22:28:32.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.22:28:32.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.22:28:32.96#ibcon#ireg 17 cls_cnt 0 2006.285.22:28:32.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:28:32.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:28:32.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:28:32.96#ibcon#enter wrdev, iclass 22, count 0 2006.285.22:28:32.96#ibcon#first serial, iclass 22, count 0 2006.285.22:28:32.96#ibcon#enter sib2, iclass 22, count 0 2006.285.22:28:32.96#ibcon#flushed, iclass 22, count 0 2006.285.22:28:32.96#ibcon#about to write, iclass 22, count 0 2006.285.22:28:32.96#ibcon#wrote, iclass 22, count 0 2006.285.22:28:32.96#ibcon#about to read 3, iclass 22, count 0 2006.285.22:28:32.97#ibcon#read 3, iclass 22, count 0 2006.285.22:28:32.97#ibcon#about to read 4, iclass 22, count 0 2006.285.22:28:32.97#ibcon#read 4, iclass 22, count 0 2006.285.22:28:32.97#ibcon#about to read 5, iclass 22, count 0 2006.285.22:28:32.97#ibcon#read 5, iclass 22, count 0 2006.285.22:28:32.97#ibcon#about to read 6, iclass 22, count 0 2006.285.22:28:32.97#ibcon#read 6, iclass 22, count 0 2006.285.22:28:32.97#ibcon#end of sib2, iclass 22, count 0 2006.285.22:28:32.97#ibcon#*mode == 0, iclass 22, count 0 2006.285.22:28:32.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.22:28:32.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.22:28:32.98#ibcon#*before write, iclass 22, count 0 2006.285.22:28:32.98#ibcon#enter sib2, iclass 22, count 0 2006.285.22:28:32.98#ibcon#flushed, iclass 22, count 0 2006.285.22:28:32.98#ibcon#about to write, iclass 22, count 0 2006.285.22:28:32.98#ibcon#wrote, iclass 22, count 0 2006.285.22:28:32.98#ibcon#about to read 3, iclass 22, count 0 2006.285.22:28:33.01#ibcon#read 3, iclass 22, count 0 2006.285.22:28:33.01#ibcon#about to read 4, iclass 22, count 0 2006.285.22:28:33.01#ibcon#read 4, iclass 22, count 0 2006.285.22:28:33.01#ibcon#about to read 5, iclass 22, count 0 2006.285.22:28:33.01#ibcon#read 5, iclass 22, count 0 2006.285.22:28:33.01#ibcon#about to read 6, iclass 22, count 0 2006.285.22:28:33.01#ibcon#read 6, iclass 22, count 0 2006.285.22:28:33.02#ibcon#end of sib2, iclass 22, count 0 2006.285.22:28:33.02#ibcon#*after write, iclass 22, count 0 2006.285.22:28:33.02#ibcon#*before return 0, iclass 22, count 0 2006.285.22:28:33.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:28:33.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.22:28:33.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.22:28:33.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.22:28:33.02$vck44/vb=8,4 2006.285.22:28:33.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.22:28:33.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.22:28:33.02#ibcon#ireg 11 cls_cnt 2 2006.285.22:28:33.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:28:33.07#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:28:33.07#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:28:33.07#ibcon#enter wrdev, iclass 24, count 2 2006.285.22:28:33.07#ibcon#first serial, iclass 24, count 2 2006.285.22:28:33.07#ibcon#enter sib2, iclass 24, count 2 2006.285.22:28:33.07#ibcon#flushed, iclass 24, count 2 2006.285.22:28:33.07#ibcon#about to write, iclass 24, count 2 2006.285.22:28:33.07#ibcon#wrote, iclass 24, count 2 2006.285.22:28:33.07#ibcon#about to read 3, iclass 24, count 2 2006.285.22:28:33.09#abcon#<5=/04 0.4 1.3 16.76 981016.1\r\n> 2006.285.22:28:33.10#ibcon#read 3, iclass 24, count 2 2006.285.22:28:33.10#ibcon#about to read 4, iclass 24, count 2 2006.285.22:28:33.10#ibcon#read 4, iclass 24, count 2 2006.285.22:28:33.10#ibcon#about to read 5, iclass 24, count 2 2006.285.22:28:33.10#ibcon#read 5, iclass 24, count 2 2006.285.22:28:33.10#ibcon#about to read 6, iclass 24, count 2 2006.285.22:28:33.10#ibcon#read 6, iclass 24, count 2 2006.285.22:28:33.10#ibcon#end of sib2, iclass 24, count 2 2006.285.22:28:33.10#ibcon#*mode == 0, iclass 24, count 2 2006.285.22:28:33.10#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.22:28:33.10#ibcon#[27=AT08-04\r\n] 2006.285.22:28:33.10#ibcon#*before write, iclass 24, count 2 2006.285.22:28:33.10#ibcon#enter sib2, iclass 24, count 2 2006.285.22:28:33.10#ibcon#flushed, iclass 24, count 2 2006.285.22:28:33.10#ibcon#about to write, iclass 24, count 2 2006.285.22:28:33.10#ibcon#wrote, iclass 24, count 2 2006.285.22:28:33.10#ibcon#about to read 3, iclass 24, count 2 2006.285.22:28:33.11#abcon#{5=INTERFACE CLEAR} 2006.285.22:28:33.12#ibcon#read 3, iclass 24, count 2 2006.285.22:28:33.12#ibcon#about to read 4, iclass 24, count 2 2006.285.22:28:33.12#ibcon#read 4, iclass 24, count 2 2006.285.22:28:33.12#ibcon#about to read 5, iclass 24, count 2 2006.285.22:28:33.12#ibcon#read 5, iclass 24, count 2 2006.285.22:28:33.12#ibcon#about to read 6, iclass 24, count 2 2006.285.22:28:33.12#ibcon#read 6, iclass 24, count 2 2006.285.22:28:33.12#ibcon#end of sib2, iclass 24, count 2 2006.285.22:28:33.12#ibcon#*after write, iclass 24, count 2 2006.285.22:28:33.12#ibcon#*before return 0, iclass 24, count 2 2006.285.22:28:33.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:28:33.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.22:28:33.13#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.22:28:33.13#ibcon#ireg 7 cls_cnt 0 2006.285.22:28:33.13#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:28:33.17#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:28:33.24#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:28:33.24#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:28:33.24#ibcon#enter wrdev, iclass 24, count 0 2006.285.22:28:33.24#ibcon#first serial, iclass 24, count 0 2006.285.22:28:33.24#ibcon#enter sib2, iclass 24, count 0 2006.285.22:28:33.24#ibcon#flushed, iclass 24, count 0 2006.285.22:28:33.24#ibcon#about to write, iclass 24, count 0 2006.285.22:28:33.24#ibcon#wrote, iclass 24, count 0 2006.285.22:28:33.25#ibcon#about to read 3, iclass 24, count 0 2006.285.22:28:33.26#ibcon#read 3, iclass 24, count 0 2006.285.22:28:33.26#ibcon#about to read 4, iclass 24, count 0 2006.285.22:28:33.26#ibcon#read 4, iclass 24, count 0 2006.285.22:28:33.26#ibcon#about to read 5, iclass 24, count 0 2006.285.22:28:33.26#ibcon#read 5, iclass 24, count 0 2006.285.22:28:33.26#ibcon#about to read 6, iclass 24, count 0 2006.285.22:28:33.26#ibcon#read 6, iclass 24, count 0 2006.285.22:28:33.26#ibcon#end of sib2, iclass 24, count 0 2006.285.22:28:33.26#ibcon#*mode == 0, iclass 24, count 0 2006.285.22:28:33.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.22:28:33.27#ibcon#[27=USB\r\n] 2006.285.22:28:33.27#ibcon#*before write, iclass 24, count 0 2006.285.22:28:33.27#ibcon#enter sib2, iclass 24, count 0 2006.285.22:28:33.27#ibcon#flushed, iclass 24, count 0 2006.285.22:28:33.27#ibcon#about to write, iclass 24, count 0 2006.285.22:28:33.27#ibcon#wrote, iclass 24, count 0 2006.285.22:28:33.27#ibcon#about to read 3, iclass 24, count 0 2006.285.22:28:33.29#ibcon#read 3, iclass 24, count 0 2006.285.22:28:33.29#ibcon#about to read 4, iclass 24, count 0 2006.285.22:28:33.29#ibcon#read 4, iclass 24, count 0 2006.285.22:28:33.29#ibcon#about to read 5, iclass 24, count 0 2006.285.22:28:33.29#ibcon#read 5, iclass 24, count 0 2006.285.22:28:33.29#ibcon#about to read 6, iclass 24, count 0 2006.285.22:28:33.29#ibcon#read 6, iclass 24, count 0 2006.285.22:28:33.29#ibcon#end of sib2, iclass 24, count 0 2006.285.22:28:33.29#ibcon#*after write, iclass 24, count 0 2006.285.22:28:33.29#ibcon#*before return 0, iclass 24, count 0 2006.285.22:28:33.30#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:28:33.30#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.22:28:33.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.22:28:33.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.22:28:33.30$vck44/vabw=wide 2006.285.22:28:33.30#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.22:28:33.30#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.22:28:33.30#ibcon#ireg 8 cls_cnt 0 2006.285.22:28:33.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:28:33.30#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:28:33.30#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:28:33.30#ibcon#enter wrdev, iclass 30, count 0 2006.285.22:28:33.30#ibcon#first serial, iclass 30, count 0 2006.285.22:28:33.30#ibcon#enter sib2, iclass 30, count 0 2006.285.22:28:33.30#ibcon#flushed, iclass 30, count 0 2006.285.22:28:33.30#ibcon#about to write, iclass 30, count 0 2006.285.22:28:33.30#ibcon#wrote, iclass 30, count 0 2006.285.22:28:33.30#ibcon#about to read 3, iclass 30, count 0 2006.285.22:28:33.31#ibcon#read 3, iclass 30, count 0 2006.285.22:28:33.31#ibcon#about to read 4, iclass 30, count 0 2006.285.22:28:33.31#ibcon#read 4, iclass 30, count 0 2006.285.22:28:33.31#ibcon#about to read 5, iclass 30, count 0 2006.285.22:28:33.31#ibcon#read 5, iclass 30, count 0 2006.285.22:28:33.31#ibcon#about to read 6, iclass 30, count 0 2006.285.22:28:33.31#ibcon#read 6, iclass 30, count 0 2006.285.22:28:33.31#ibcon#end of sib2, iclass 30, count 0 2006.285.22:28:33.31#ibcon#*mode == 0, iclass 30, count 0 2006.285.22:28:33.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.22:28:33.32#ibcon#[25=BW32\r\n] 2006.285.22:28:33.32#ibcon#*before write, iclass 30, count 0 2006.285.22:28:33.32#ibcon#enter sib2, iclass 30, count 0 2006.285.22:28:33.32#ibcon#flushed, iclass 30, count 0 2006.285.22:28:33.32#ibcon#about to write, iclass 30, count 0 2006.285.22:28:33.32#ibcon#wrote, iclass 30, count 0 2006.285.22:28:33.32#ibcon#about to read 3, iclass 30, count 0 2006.285.22:28:33.34#ibcon#read 3, iclass 30, count 0 2006.285.22:28:33.34#ibcon#about to read 4, iclass 30, count 0 2006.285.22:28:33.34#ibcon#read 4, iclass 30, count 0 2006.285.22:28:33.34#ibcon#about to read 5, iclass 30, count 0 2006.285.22:28:33.34#ibcon#read 5, iclass 30, count 0 2006.285.22:28:33.34#ibcon#about to read 6, iclass 30, count 0 2006.285.22:28:33.34#ibcon#read 6, iclass 30, count 0 2006.285.22:28:33.34#ibcon#end of sib2, iclass 30, count 0 2006.285.22:28:33.34#ibcon#*after write, iclass 30, count 0 2006.285.22:28:33.34#ibcon#*before return 0, iclass 30, count 0 2006.285.22:28:33.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:28:33.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:28:33.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.22:28:33.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.22:28:33.35$vck44/vbbw=wide 2006.285.22:28:33.35#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.22:28:33.35#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.22:28:33.35#ibcon#ireg 8 cls_cnt 0 2006.285.22:28:33.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:28:33.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:28:33.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:28:33.41#ibcon#enter wrdev, iclass 32, count 0 2006.285.22:28:33.41#ibcon#first serial, iclass 32, count 0 2006.285.22:28:33.41#ibcon#enter sib2, iclass 32, count 0 2006.285.22:28:33.41#ibcon#flushed, iclass 32, count 0 2006.285.22:28:33.41#ibcon#about to write, iclass 32, count 0 2006.285.22:28:33.41#ibcon#wrote, iclass 32, count 0 2006.285.22:28:33.41#ibcon#about to read 3, iclass 32, count 0 2006.285.22:28:33.44#ibcon#read 3, iclass 32, count 0 2006.285.22:28:33.44#ibcon#about to read 4, iclass 32, count 0 2006.285.22:28:33.44#ibcon#read 4, iclass 32, count 0 2006.285.22:28:33.44#ibcon#about to read 5, iclass 32, count 0 2006.285.22:28:33.44#ibcon#read 5, iclass 32, count 0 2006.285.22:28:33.44#ibcon#about to read 6, iclass 32, count 0 2006.285.22:28:33.44#ibcon#read 6, iclass 32, count 0 2006.285.22:28:33.44#ibcon#end of sib2, iclass 32, count 0 2006.285.22:28:33.44#ibcon#*mode == 0, iclass 32, count 0 2006.285.22:28:33.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.22:28:33.44#ibcon#[27=BW32\r\n] 2006.285.22:28:33.44#ibcon#*before write, iclass 32, count 0 2006.285.22:28:33.44#ibcon#enter sib2, iclass 32, count 0 2006.285.22:28:33.44#ibcon#flushed, iclass 32, count 0 2006.285.22:28:33.44#ibcon#about to write, iclass 32, count 0 2006.285.22:28:33.44#ibcon#wrote, iclass 32, count 0 2006.285.22:28:33.44#ibcon#about to read 3, iclass 32, count 0 2006.285.22:28:33.46#ibcon#read 3, iclass 32, count 0 2006.285.22:28:33.46#ibcon#about to read 4, iclass 32, count 0 2006.285.22:28:33.46#ibcon#read 4, iclass 32, count 0 2006.285.22:28:33.46#ibcon#about to read 5, iclass 32, count 0 2006.285.22:28:33.46#ibcon#read 5, iclass 32, count 0 2006.285.22:28:33.46#ibcon#about to read 6, iclass 32, count 0 2006.285.22:28:33.46#ibcon#read 6, iclass 32, count 0 2006.285.22:28:33.47#ibcon#end of sib2, iclass 32, count 0 2006.285.22:28:33.47#ibcon#*after write, iclass 32, count 0 2006.285.22:28:33.47#ibcon#*before return 0, iclass 32, count 0 2006.285.22:28:33.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:28:33.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:28:33.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.22:28:33.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.22:28:33.47$setupk4/ifdk4 2006.285.22:28:33.47$ifdk4/lo= 2006.285.22:28:33.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.22:28:33.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.22:28:33.47$ifdk4/patch= 2006.285.22:28:33.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.22:28:33.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.22:28:33.47$setupk4/!*+20s 2006.285.22:28:43.26#abcon#<5=/04 0.4 1.3 16.76 981016.1\r\n> 2006.285.22:28:43.28#abcon#{5=INTERFACE CLEAR} 2006.285.22:28:43.34#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:28:47.96$setupk4/"tpicd 2006.285.22:28:47.97$setupk4/echo=off 2006.285.22:28:47.97$setupk4/xlog=off 2006.285.22:28:47.97:!2006.285.22:31:13 2006.285.22:29:09.14#trakl#Source acquired 2006.285.22:29:10.15#flagr#flagr/antenna,acquired 2006.285.22:31:13.01:preob 2006.285.22:31:14.14/onsource/TRACKING 2006.285.22:31:14.15:!2006.285.22:31:23 2006.285.22:31:23.01:"tape 2006.285.22:31:23.01:"st=record 2006.285.22:31:23.01:data_valid=on 2006.285.22:31:23.02:midob 2006.285.22:31:24.14/onsource/TRACKING 2006.285.22:31:24.15/wx/16.83,1016.1,98 2006.285.22:31:24.19/cable/+6.5126E-03 2006.285.22:31:25.28/va/01,07,usb,yes,32,35 2006.285.22:31:25.28/va/02,06,usb,yes,32,32 2006.285.22:31:25.28/va/03,07,usb,yes,32,33 2006.285.22:31:25.28/va/04,06,usb,yes,33,34 2006.285.22:31:25.28/va/05,03,usb,yes,33,33 2006.285.22:31:25.28/va/06,04,usb,yes,29,29 2006.285.22:31:25.28/va/07,04,usb,yes,30,30 2006.285.22:31:25.28/va/08,03,usb,yes,30,37 2006.285.22:31:25.51/valo/01,524.99,yes,locked 2006.285.22:31:25.51/valo/02,534.99,yes,locked 2006.285.22:31:25.51/valo/03,564.99,yes,locked 2006.285.22:31:25.51/valo/04,624.99,yes,locked 2006.285.22:31:25.51/valo/05,734.99,yes,locked 2006.285.22:31:25.51/valo/06,814.99,yes,locked 2006.285.22:31:25.51/valo/07,864.99,yes,locked 2006.285.22:31:25.51/valo/08,884.99,yes,locked 2006.285.22:31:26.60/vb/01,04,usb,yes,30,28 2006.285.22:31:26.60/vb/02,05,usb,yes,28,28 2006.285.22:31:26.60/vb/03,04,usb,yes,29,32 2006.285.22:31:26.60/vb/04,05,usb,yes,29,28 2006.285.22:31:26.60/vb/05,04,usb,yes,26,28 2006.285.22:31:26.60/vb/06,03,usb,yes,37,33 2006.285.22:31:26.60/vb/07,04,usb,yes,30,30 2006.285.22:31:26.60/vb/08,04,usb,yes,27,30 2006.285.22:31:26.84/vblo/01,629.99,yes,locked 2006.285.22:31:26.84/vblo/02,634.99,yes,locked 2006.285.22:31:26.84/vblo/03,649.99,yes,locked 2006.285.22:31:26.84/vblo/04,679.99,yes,locked 2006.285.22:31:26.84/vblo/05,709.99,yes,locked 2006.285.22:31:26.84/vblo/06,719.99,yes,locked 2006.285.22:31:26.84/vblo/07,734.99,yes,locked 2006.285.22:31:26.84/vblo/08,744.99,yes,locked 2006.285.22:31:26.99/vabw/8 2006.285.22:31:27.14/vbbw/8 2006.285.22:31:27.23/xfe/off,on,12.0 2006.285.22:31:27.62/ifatt/23,28,28,28 2006.285.22:31:28.07/fmout-gps/S +2.59E-07 2006.285.22:31:28.09:!2006.285.22:32:13 2006.285.22:32:13.00:data_valid=off 2006.285.22:32:13.00:"et 2006.285.22:32:13.00:!+3s 2006.285.22:32:16.01:"tape 2006.285.22:32:16.01:postob 2006.285.22:32:16.07/cable/+6.5117E-03 2006.285.22:32:16.07/wx/16.86,1016.1,97 2006.285.22:32:17.07/fmout-gps/S +2.58E-07 2006.285.22:32:17.07:scan_name=285-2234,jd0610,340 2006.285.22:32:17.07:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.285.22:32:18.14#flagr#flagr/antenna,new-source 2006.285.22:32:18.15:checkk5 2006.285.22:32:18.51/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:32:18.96/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:32:19.34/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:32:19.75/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:32:20.13/chk_obsdata//k5ts1/T2852231??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.22:32:20.71/chk_obsdata//k5ts2/T2852231??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.22:32:21.11/chk_obsdata//k5ts3/T2852231??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.22:32:21.49/chk_obsdata//k5ts4/T2852231??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.22:32:22.27/k5log//k5ts1_log_newline 2006.285.22:32:23.06/k5log//k5ts2_log_newline 2006.285.22:32:23.74/k5log//k5ts3_log_newline 2006.285.22:32:24.48/k5log//k5ts4_log_newline 2006.285.22:32:24.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:32:24.50:setupk4=1 2006.285.22:32:24.50$setupk4/echo=on 2006.285.22:32:24.50$setupk4/pcalon 2006.285.22:32:24.50$pcalon/"no phase cal control is implemented here 2006.285.22:32:24.50$setupk4/"tpicd=stop 2006.285.22:32:24.50$setupk4/"rec=synch_on 2006.285.22:32:24.50$setupk4/"rec_mode=128 2006.285.22:32:24.50$setupk4/!* 2006.285.22:32:24.50$setupk4/recpk4 2006.285.22:32:24.50$recpk4/recpatch= 2006.285.22:32:24.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:32:24.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:32:24.50$setupk4/vck44 2006.285.22:32:24.50$vck44/valo=1,524.99 2006.285.22:32:24.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.22:32:24.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.22:32:24.50#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:24.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:32:24.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:32:24.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:32:24.50#ibcon#enter wrdev, iclass 17, count 0 2006.285.22:32:24.50#ibcon#first serial, iclass 17, count 0 2006.285.22:32:24.50#ibcon#enter sib2, iclass 17, count 0 2006.285.22:32:24.50#ibcon#flushed, iclass 17, count 0 2006.285.22:32:24.50#ibcon#about to write, iclass 17, count 0 2006.285.22:32:24.50#ibcon#wrote, iclass 17, count 0 2006.285.22:32:24.50#ibcon#about to read 3, iclass 17, count 0 2006.285.22:32:24.52#ibcon#read 3, iclass 17, count 0 2006.285.22:32:24.52#ibcon#about to read 4, iclass 17, count 0 2006.285.22:32:24.52#ibcon#read 4, iclass 17, count 0 2006.285.22:32:24.52#ibcon#about to read 5, iclass 17, count 0 2006.285.22:32:24.52#ibcon#read 5, iclass 17, count 0 2006.285.22:32:24.52#ibcon#about to read 6, iclass 17, count 0 2006.285.22:32:24.52#ibcon#read 6, iclass 17, count 0 2006.285.22:32:24.52#ibcon#end of sib2, iclass 17, count 0 2006.285.22:32:24.52#ibcon#*mode == 0, iclass 17, count 0 2006.285.22:32:24.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.22:32:24.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:32:24.52#ibcon#*before write, iclass 17, count 0 2006.285.22:32:24.52#ibcon#enter sib2, iclass 17, count 0 2006.285.22:32:24.52#ibcon#flushed, iclass 17, count 0 2006.285.22:32:24.52#ibcon#about to write, iclass 17, count 0 2006.285.22:32:24.52#ibcon#wrote, iclass 17, count 0 2006.285.22:32:24.52#ibcon#about to read 3, iclass 17, count 0 2006.285.22:32:24.57#ibcon#read 3, iclass 17, count 0 2006.285.22:32:24.57#ibcon#about to read 4, iclass 17, count 0 2006.285.22:32:24.57#ibcon#read 4, iclass 17, count 0 2006.285.22:32:24.57#ibcon#about to read 5, iclass 17, count 0 2006.285.22:32:24.57#ibcon#read 5, iclass 17, count 0 2006.285.22:32:24.57#ibcon#about to read 6, iclass 17, count 0 2006.285.22:32:24.57#ibcon#read 6, iclass 17, count 0 2006.285.22:32:24.57#ibcon#end of sib2, iclass 17, count 0 2006.285.22:32:24.57#ibcon#*after write, iclass 17, count 0 2006.285.22:32:24.57#ibcon#*before return 0, iclass 17, count 0 2006.285.22:32:24.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:32:24.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:32:24.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.22:32:24.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.22:32:24.57$vck44/va=1,7 2006.285.22:32:24.57#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.22:32:24.57#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.22:32:24.57#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:24.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:32:24.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:32:24.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:32:24.57#ibcon#enter wrdev, iclass 19, count 2 2006.285.22:32:24.57#ibcon#first serial, iclass 19, count 2 2006.285.22:32:24.57#ibcon#enter sib2, iclass 19, count 2 2006.285.22:32:24.57#ibcon#flushed, iclass 19, count 2 2006.285.22:32:24.57#ibcon#about to write, iclass 19, count 2 2006.285.22:32:24.57#ibcon#wrote, iclass 19, count 2 2006.285.22:32:24.57#ibcon#about to read 3, iclass 19, count 2 2006.285.22:32:24.59#ibcon#read 3, iclass 19, count 2 2006.285.22:32:24.59#ibcon#about to read 4, iclass 19, count 2 2006.285.22:32:24.59#ibcon#read 4, iclass 19, count 2 2006.285.22:32:24.59#ibcon#about to read 5, iclass 19, count 2 2006.285.22:32:24.59#ibcon#read 5, iclass 19, count 2 2006.285.22:32:24.59#ibcon#about to read 6, iclass 19, count 2 2006.285.22:32:24.59#ibcon#read 6, iclass 19, count 2 2006.285.22:32:24.59#ibcon#end of sib2, iclass 19, count 2 2006.285.22:32:24.59#ibcon#*mode == 0, iclass 19, count 2 2006.285.22:32:24.59#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.22:32:24.59#ibcon#[25=AT01-07\r\n] 2006.285.22:32:24.59#ibcon#*before write, iclass 19, count 2 2006.285.22:32:24.59#ibcon#enter sib2, iclass 19, count 2 2006.285.22:32:24.59#ibcon#flushed, iclass 19, count 2 2006.285.22:32:24.59#ibcon#about to write, iclass 19, count 2 2006.285.22:32:24.59#ibcon#wrote, iclass 19, count 2 2006.285.22:32:24.59#ibcon#about to read 3, iclass 19, count 2 2006.285.22:32:24.62#ibcon#read 3, iclass 19, count 2 2006.285.22:32:24.62#ibcon#about to read 4, iclass 19, count 2 2006.285.22:32:24.62#ibcon#read 4, iclass 19, count 2 2006.285.22:32:24.62#ibcon#about to read 5, iclass 19, count 2 2006.285.22:32:24.62#ibcon#read 5, iclass 19, count 2 2006.285.22:32:24.62#ibcon#about to read 6, iclass 19, count 2 2006.285.22:32:24.62#ibcon#read 6, iclass 19, count 2 2006.285.22:32:24.62#ibcon#end of sib2, iclass 19, count 2 2006.285.22:32:24.62#ibcon#*after write, iclass 19, count 2 2006.285.22:32:24.62#ibcon#*before return 0, iclass 19, count 2 2006.285.22:32:24.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:32:24.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:32:24.62#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.22:32:24.62#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:24.62#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:32:24.74#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:32:24.74#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:32:24.74#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:32:24.74#ibcon#first serial, iclass 19, count 0 2006.285.22:32:24.74#ibcon#enter sib2, iclass 19, count 0 2006.285.22:32:24.74#ibcon#flushed, iclass 19, count 0 2006.285.22:32:24.74#ibcon#about to write, iclass 19, count 0 2006.285.22:32:24.74#ibcon#wrote, iclass 19, count 0 2006.285.22:32:24.74#ibcon#about to read 3, iclass 19, count 0 2006.285.22:32:24.76#ibcon#read 3, iclass 19, count 0 2006.285.22:32:24.76#ibcon#about to read 4, iclass 19, count 0 2006.285.22:32:24.76#ibcon#read 4, iclass 19, count 0 2006.285.22:32:24.76#ibcon#about to read 5, iclass 19, count 0 2006.285.22:32:24.76#ibcon#read 5, iclass 19, count 0 2006.285.22:32:24.76#ibcon#about to read 6, iclass 19, count 0 2006.285.22:32:24.76#ibcon#read 6, iclass 19, count 0 2006.285.22:32:24.76#ibcon#end of sib2, iclass 19, count 0 2006.285.22:32:24.76#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:32:24.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:32:24.76#ibcon#[25=USB\r\n] 2006.285.22:32:24.76#ibcon#*before write, iclass 19, count 0 2006.285.22:32:24.76#ibcon#enter sib2, iclass 19, count 0 2006.285.22:32:24.76#ibcon#flushed, iclass 19, count 0 2006.285.22:32:24.76#ibcon#about to write, iclass 19, count 0 2006.285.22:32:24.76#ibcon#wrote, iclass 19, count 0 2006.285.22:32:24.76#ibcon#about to read 3, iclass 19, count 0 2006.285.22:32:24.79#ibcon#read 3, iclass 19, count 0 2006.285.22:32:24.79#ibcon#about to read 4, iclass 19, count 0 2006.285.22:32:24.79#ibcon#read 4, iclass 19, count 0 2006.285.22:32:24.79#ibcon#about to read 5, iclass 19, count 0 2006.285.22:32:24.79#ibcon#read 5, iclass 19, count 0 2006.285.22:32:24.79#ibcon#about to read 6, iclass 19, count 0 2006.285.22:32:24.79#ibcon#read 6, iclass 19, count 0 2006.285.22:32:24.79#ibcon#end of sib2, iclass 19, count 0 2006.285.22:32:24.79#ibcon#*after write, iclass 19, count 0 2006.285.22:32:24.79#ibcon#*before return 0, iclass 19, count 0 2006.285.22:32:24.79#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:32:24.79#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:32:24.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:32:24.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:32:24.79$vck44/valo=2,534.99 2006.285.22:32:24.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.22:32:24.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.22:32:24.80#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:24.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:32:24.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:32:24.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:32:24.80#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:32:24.80#ibcon#first serial, iclass 21, count 0 2006.285.22:32:24.80#ibcon#enter sib2, iclass 21, count 0 2006.285.22:32:24.80#ibcon#flushed, iclass 21, count 0 2006.285.22:32:24.80#ibcon#about to write, iclass 21, count 0 2006.285.22:32:24.80#ibcon#wrote, iclass 21, count 0 2006.285.22:32:24.80#ibcon#about to read 3, iclass 21, count 0 2006.285.22:32:24.81#ibcon#read 3, iclass 21, count 0 2006.285.22:32:24.81#ibcon#about to read 4, iclass 21, count 0 2006.285.22:32:24.81#ibcon#read 4, iclass 21, count 0 2006.285.22:32:24.81#ibcon#about to read 5, iclass 21, count 0 2006.285.22:32:24.81#ibcon#read 5, iclass 21, count 0 2006.285.22:32:24.81#ibcon#about to read 6, iclass 21, count 0 2006.285.22:32:24.81#ibcon#read 6, iclass 21, count 0 2006.285.22:32:24.81#ibcon#end of sib2, iclass 21, count 0 2006.285.22:32:24.81#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:32:24.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:32:24.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:32:24.81#ibcon#*before write, iclass 21, count 0 2006.285.22:32:24.81#ibcon#enter sib2, iclass 21, count 0 2006.285.22:32:24.81#ibcon#flushed, iclass 21, count 0 2006.285.22:32:24.81#ibcon#about to write, iclass 21, count 0 2006.285.22:32:24.81#ibcon#wrote, iclass 21, count 0 2006.285.22:32:24.81#ibcon#about to read 3, iclass 21, count 0 2006.285.22:32:24.85#ibcon#read 3, iclass 21, count 0 2006.285.22:32:24.85#ibcon#about to read 4, iclass 21, count 0 2006.285.22:32:24.85#ibcon#read 4, iclass 21, count 0 2006.285.22:32:24.85#ibcon#about to read 5, iclass 21, count 0 2006.285.22:32:24.85#ibcon#read 5, iclass 21, count 0 2006.285.22:32:24.85#ibcon#about to read 6, iclass 21, count 0 2006.285.22:32:24.85#ibcon#read 6, iclass 21, count 0 2006.285.22:32:24.85#ibcon#end of sib2, iclass 21, count 0 2006.285.22:32:24.85#ibcon#*after write, iclass 21, count 0 2006.285.22:32:24.85#ibcon#*before return 0, iclass 21, count 0 2006.285.22:32:24.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:32:24.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:32:24.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:32:24.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:32:24.85$vck44/va=2,6 2006.285.22:32:24.85#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.22:32:24.85#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.22:32:24.85#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:24.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:32:24.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:32:24.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:32:24.91#ibcon#enter wrdev, iclass 23, count 2 2006.285.22:32:24.91#ibcon#first serial, iclass 23, count 2 2006.285.22:32:24.91#ibcon#enter sib2, iclass 23, count 2 2006.285.22:32:24.91#ibcon#flushed, iclass 23, count 2 2006.285.22:32:24.91#ibcon#about to write, iclass 23, count 2 2006.285.22:32:24.91#ibcon#wrote, iclass 23, count 2 2006.285.22:32:24.91#ibcon#about to read 3, iclass 23, count 2 2006.285.22:32:24.93#ibcon#read 3, iclass 23, count 2 2006.285.22:32:24.93#ibcon#about to read 4, iclass 23, count 2 2006.285.22:32:24.93#ibcon#read 4, iclass 23, count 2 2006.285.22:32:24.93#ibcon#about to read 5, iclass 23, count 2 2006.285.22:32:24.93#ibcon#read 5, iclass 23, count 2 2006.285.22:32:24.93#ibcon#about to read 6, iclass 23, count 2 2006.285.22:32:24.93#ibcon#read 6, iclass 23, count 2 2006.285.22:32:24.93#ibcon#end of sib2, iclass 23, count 2 2006.285.22:32:24.93#ibcon#*mode == 0, iclass 23, count 2 2006.285.22:32:24.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.22:32:24.93#ibcon#[25=AT02-06\r\n] 2006.285.22:32:24.93#ibcon#*before write, iclass 23, count 2 2006.285.22:32:24.93#ibcon#enter sib2, iclass 23, count 2 2006.285.22:32:24.93#ibcon#flushed, iclass 23, count 2 2006.285.22:32:24.93#ibcon#about to write, iclass 23, count 2 2006.285.22:32:24.93#ibcon#wrote, iclass 23, count 2 2006.285.22:32:24.93#ibcon#about to read 3, iclass 23, count 2 2006.285.22:32:24.96#ibcon#read 3, iclass 23, count 2 2006.285.22:32:24.96#ibcon#about to read 4, iclass 23, count 2 2006.285.22:32:24.96#ibcon#read 4, iclass 23, count 2 2006.285.22:32:24.96#ibcon#about to read 5, iclass 23, count 2 2006.285.22:32:24.96#ibcon#read 5, iclass 23, count 2 2006.285.22:32:24.96#ibcon#about to read 6, iclass 23, count 2 2006.285.22:32:24.96#ibcon#read 6, iclass 23, count 2 2006.285.22:32:24.96#ibcon#end of sib2, iclass 23, count 2 2006.285.22:32:24.96#ibcon#*after write, iclass 23, count 2 2006.285.22:32:24.96#ibcon#*before return 0, iclass 23, count 2 2006.285.22:32:24.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:32:24.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:32:24.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.22:32:24.96#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:24.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:32:25.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:32:25.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:32:25.08#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:32:25.08#ibcon#first serial, iclass 23, count 0 2006.285.22:32:25.08#ibcon#enter sib2, iclass 23, count 0 2006.285.22:32:25.08#ibcon#flushed, iclass 23, count 0 2006.285.22:32:25.08#ibcon#about to write, iclass 23, count 0 2006.285.22:32:25.08#ibcon#wrote, iclass 23, count 0 2006.285.22:32:25.08#ibcon#about to read 3, iclass 23, count 0 2006.285.22:32:25.10#ibcon#read 3, iclass 23, count 0 2006.285.22:32:25.10#ibcon#about to read 4, iclass 23, count 0 2006.285.22:32:25.10#ibcon#read 4, iclass 23, count 0 2006.285.22:32:25.10#ibcon#about to read 5, iclass 23, count 0 2006.285.22:32:25.10#ibcon#read 5, iclass 23, count 0 2006.285.22:32:25.10#ibcon#about to read 6, iclass 23, count 0 2006.285.22:32:25.10#ibcon#read 6, iclass 23, count 0 2006.285.22:32:25.10#ibcon#end of sib2, iclass 23, count 0 2006.285.22:32:25.10#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:32:25.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:32:25.10#ibcon#[25=USB\r\n] 2006.285.22:32:25.10#ibcon#*before write, iclass 23, count 0 2006.285.22:32:25.10#ibcon#enter sib2, iclass 23, count 0 2006.285.22:32:25.10#ibcon#flushed, iclass 23, count 0 2006.285.22:32:25.10#ibcon#about to write, iclass 23, count 0 2006.285.22:32:25.10#ibcon#wrote, iclass 23, count 0 2006.285.22:32:25.10#ibcon#about to read 3, iclass 23, count 0 2006.285.22:32:25.13#ibcon#read 3, iclass 23, count 0 2006.285.22:32:25.13#ibcon#about to read 4, iclass 23, count 0 2006.285.22:32:25.13#ibcon#read 4, iclass 23, count 0 2006.285.22:32:25.13#ibcon#about to read 5, iclass 23, count 0 2006.285.22:32:25.13#ibcon#read 5, iclass 23, count 0 2006.285.22:32:25.13#ibcon#about to read 6, iclass 23, count 0 2006.285.22:32:25.13#ibcon#read 6, iclass 23, count 0 2006.285.22:32:25.13#ibcon#end of sib2, iclass 23, count 0 2006.285.22:32:25.13#ibcon#*after write, iclass 23, count 0 2006.285.22:32:25.13#ibcon#*before return 0, iclass 23, count 0 2006.285.22:32:25.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:32:25.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:32:25.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:32:25.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:32:25.13$vck44/valo=3,564.99 2006.285.22:32:25.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.22:32:25.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.22:32:25.13#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:25.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:32:25.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:32:25.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:32:25.13#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:32:25.13#ibcon#first serial, iclass 25, count 0 2006.285.22:32:25.13#ibcon#enter sib2, iclass 25, count 0 2006.285.22:32:25.13#ibcon#flushed, iclass 25, count 0 2006.285.22:32:25.13#ibcon#about to write, iclass 25, count 0 2006.285.22:32:25.13#ibcon#wrote, iclass 25, count 0 2006.285.22:32:25.13#ibcon#about to read 3, iclass 25, count 0 2006.285.22:32:25.15#ibcon#read 3, iclass 25, count 0 2006.285.22:32:25.15#ibcon#about to read 4, iclass 25, count 0 2006.285.22:32:25.15#ibcon#read 4, iclass 25, count 0 2006.285.22:32:25.15#ibcon#about to read 5, iclass 25, count 0 2006.285.22:32:25.15#ibcon#read 5, iclass 25, count 0 2006.285.22:32:25.15#ibcon#about to read 6, iclass 25, count 0 2006.285.22:32:25.15#ibcon#read 6, iclass 25, count 0 2006.285.22:32:25.15#ibcon#end of sib2, iclass 25, count 0 2006.285.22:32:25.15#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:32:25.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:32:25.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:32:25.15#ibcon#*before write, iclass 25, count 0 2006.285.22:32:25.15#ibcon#enter sib2, iclass 25, count 0 2006.285.22:32:25.15#ibcon#flushed, iclass 25, count 0 2006.285.22:32:25.15#ibcon#about to write, iclass 25, count 0 2006.285.22:32:25.15#ibcon#wrote, iclass 25, count 0 2006.285.22:32:25.15#ibcon#about to read 3, iclass 25, count 0 2006.285.22:32:25.19#ibcon#read 3, iclass 25, count 0 2006.285.22:32:25.19#ibcon#about to read 4, iclass 25, count 0 2006.285.22:32:25.19#ibcon#read 4, iclass 25, count 0 2006.285.22:32:25.19#ibcon#about to read 5, iclass 25, count 0 2006.285.22:32:25.19#ibcon#read 5, iclass 25, count 0 2006.285.22:32:25.19#ibcon#about to read 6, iclass 25, count 0 2006.285.22:32:25.19#ibcon#read 6, iclass 25, count 0 2006.285.22:32:25.19#ibcon#end of sib2, iclass 25, count 0 2006.285.22:32:25.19#ibcon#*after write, iclass 25, count 0 2006.285.22:32:25.19#ibcon#*before return 0, iclass 25, count 0 2006.285.22:32:25.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:32:25.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:32:25.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:32:25.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:32:25.19$vck44/va=3,7 2006.285.22:32:25.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.22:32:25.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.22:32:25.19#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:25.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:32:25.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:32:25.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:32:25.25#ibcon#enter wrdev, iclass 27, count 2 2006.285.22:32:25.25#ibcon#first serial, iclass 27, count 2 2006.285.22:32:25.25#ibcon#enter sib2, iclass 27, count 2 2006.285.22:32:25.25#ibcon#flushed, iclass 27, count 2 2006.285.22:32:25.25#ibcon#about to write, iclass 27, count 2 2006.285.22:32:25.25#ibcon#wrote, iclass 27, count 2 2006.285.22:32:25.25#ibcon#about to read 3, iclass 27, count 2 2006.285.22:32:25.27#ibcon#read 3, iclass 27, count 2 2006.285.22:32:25.27#ibcon#about to read 4, iclass 27, count 2 2006.285.22:32:25.27#ibcon#read 4, iclass 27, count 2 2006.285.22:32:25.27#ibcon#about to read 5, iclass 27, count 2 2006.285.22:32:25.27#ibcon#read 5, iclass 27, count 2 2006.285.22:32:25.27#ibcon#about to read 6, iclass 27, count 2 2006.285.22:32:25.27#ibcon#read 6, iclass 27, count 2 2006.285.22:32:25.27#ibcon#end of sib2, iclass 27, count 2 2006.285.22:32:25.27#ibcon#*mode == 0, iclass 27, count 2 2006.285.22:32:25.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.22:32:25.27#ibcon#[25=AT03-07\r\n] 2006.285.22:32:25.27#ibcon#*before write, iclass 27, count 2 2006.285.22:32:25.27#ibcon#enter sib2, iclass 27, count 2 2006.285.22:32:25.27#ibcon#flushed, iclass 27, count 2 2006.285.22:32:25.27#ibcon#about to write, iclass 27, count 2 2006.285.22:32:25.27#ibcon#wrote, iclass 27, count 2 2006.285.22:32:25.27#ibcon#about to read 3, iclass 27, count 2 2006.285.22:32:25.30#ibcon#read 3, iclass 27, count 2 2006.285.22:32:25.30#ibcon#about to read 4, iclass 27, count 2 2006.285.22:32:25.30#ibcon#read 4, iclass 27, count 2 2006.285.22:32:25.30#ibcon#about to read 5, iclass 27, count 2 2006.285.22:32:25.30#ibcon#read 5, iclass 27, count 2 2006.285.22:32:25.30#ibcon#about to read 6, iclass 27, count 2 2006.285.22:32:25.30#ibcon#read 6, iclass 27, count 2 2006.285.22:32:25.30#ibcon#end of sib2, iclass 27, count 2 2006.285.22:32:25.30#ibcon#*after write, iclass 27, count 2 2006.285.22:32:25.30#ibcon#*before return 0, iclass 27, count 2 2006.285.22:32:25.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:32:25.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:32:25.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.22:32:25.30#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:25.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:32:25.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:32:25.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:32:25.42#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:32:25.42#ibcon#first serial, iclass 27, count 0 2006.285.22:32:25.42#ibcon#enter sib2, iclass 27, count 0 2006.285.22:32:25.42#ibcon#flushed, iclass 27, count 0 2006.285.22:32:25.42#ibcon#about to write, iclass 27, count 0 2006.285.22:32:25.42#ibcon#wrote, iclass 27, count 0 2006.285.22:32:25.42#ibcon#about to read 3, iclass 27, count 0 2006.285.22:32:25.44#ibcon#read 3, iclass 27, count 0 2006.285.22:32:25.44#ibcon#about to read 4, iclass 27, count 0 2006.285.22:32:25.44#ibcon#read 4, iclass 27, count 0 2006.285.22:32:25.44#ibcon#about to read 5, iclass 27, count 0 2006.285.22:32:25.44#ibcon#read 5, iclass 27, count 0 2006.285.22:32:25.44#ibcon#about to read 6, iclass 27, count 0 2006.285.22:32:25.44#ibcon#read 6, iclass 27, count 0 2006.285.22:32:25.44#ibcon#end of sib2, iclass 27, count 0 2006.285.22:32:25.44#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:32:25.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:32:25.44#ibcon#[25=USB\r\n] 2006.285.22:32:25.44#ibcon#*before write, iclass 27, count 0 2006.285.22:32:25.44#ibcon#enter sib2, iclass 27, count 0 2006.285.22:32:25.44#ibcon#flushed, iclass 27, count 0 2006.285.22:32:25.44#ibcon#about to write, iclass 27, count 0 2006.285.22:32:25.44#ibcon#wrote, iclass 27, count 0 2006.285.22:32:25.44#ibcon#about to read 3, iclass 27, count 0 2006.285.22:32:25.47#ibcon#read 3, iclass 27, count 0 2006.285.22:32:25.47#ibcon#about to read 4, iclass 27, count 0 2006.285.22:32:25.47#ibcon#read 4, iclass 27, count 0 2006.285.22:32:25.47#ibcon#about to read 5, iclass 27, count 0 2006.285.22:32:25.47#ibcon#read 5, iclass 27, count 0 2006.285.22:32:25.47#ibcon#about to read 6, iclass 27, count 0 2006.285.22:32:25.47#ibcon#read 6, iclass 27, count 0 2006.285.22:32:25.47#ibcon#end of sib2, iclass 27, count 0 2006.285.22:32:25.47#ibcon#*after write, iclass 27, count 0 2006.285.22:32:25.47#ibcon#*before return 0, iclass 27, count 0 2006.285.22:32:25.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:32:25.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:32:25.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:32:25.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:32:25.47$vck44/valo=4,624.99 2006.285.22:32:25.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.22:32:25.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.22:32:25.47#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:25.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:32:25.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:32:25.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:32:25.47#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:32:25.47#ibcon#first serial, iclass 29, count 0 2006.285.22:32:25.47#ibcon#enter sib2, iclass 29, count 0 2006.285.22:32:25.47#ibcon#flushed, iclass 29, count 0 2006.285.22:32:25.47#ibcon#about to write, iclass 29, count 0 2006.285.22:32:25.47#ibcon#wrote, iclass 29, count 0 2006.285.22:32:25.47#ibcon#about to read 3, iclass 29, count 0 2006.285.22:32:25.49#ibcon#read 3, iclass 29, count 0 2006.285.22:32:25.49#ibcon#about to read 4, iclass 29, count 0 2006.285.22:32:25.49#ibcon#read 4, iclass 29, count 0 2006.285.22:32:25.49#ibcon#about to read 5, iclass 29, count 0 2006.285.22:32:25.49#ibcon#read 5, iclass 29, count 0 2006.285.22:32:25.49#ibcon#about to read 6, iclass 29, count 0 2006.285.22:32:25.49#ibcon#read 6, iclass 29, count 0 2006.285.22:32:25.49#ibcon#end of sib2, iclass 29, count 0 2006.285.22:32:25.49#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:32:25.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:32:25.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:32:25.49#ibcon#*before write, iclass 29, count 0 2006.285.22:32:25.49#ibcon#enter sib2, iclass 29, count 0 2006.285.22:32:25.49#ibcon#flushed, iclass 29, count 0 2006.285.22:32:25.49#ibcon#about to write, iclass 29, count 0 2006.285.22:32:25.49#ibcon#wrote, iclass 29, count 0 2006.285.22:32:25.49#ibcon#about to read 3, iclass 29, count 0 2006.285.22:32:25.53#ibcon#read 3, iclass 29, count 0 2006.285.22:32:25.53#ibcon#about to read 4, iclass 29, count 0 2006.285.22:32:25.53#ibcon#read 4, iclass 29, count 0 2006.285.22:32:25.53#ibcon#about to read 5, iclass 29, count 0 2006.285.22:32:25.53#ibcon#read 5, iclass 29, count 0 2006.285.22:32:25.53#ibcon#about to read 6, iclass 29, count 0 2006.285.22:32:25.53#ibcon#read 6, iclass 29, count 0 2006.285.22:32:25.53#ibcon#end of sib2, iclass 29, count 0 2006.285.22:32:25.53#ibcon#*after write, iclass 29, count 0 2006.285.22:32:25.53#ibcon#*before return 0, iclass 29, count 0 2006.285.22:32:25.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:32:25.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:32:25.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:32:25.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:32:25.53$vck44/va=4,6 2006.285.22:32:25.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.22:32:25.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.22:32:25.53#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:25.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:32:25.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:32:25.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:32:25.59#ibcon#enter wrdev, iclass 31, count 2 2006.285.22:32:25.59#ibcon#first serial, iclass 31, count 2 2006.285.22:32:25.59#ibcon#enter sib2, iclass 31, count 2 2006.285.22:32:25.59#ibcon#flushed, iclass 31, count 2 2006.285.22:32:25.59#ibcon#about to write, iclass 31, count 2 2006.285.22:32:25.59#ibcon#wrote, iclass 31, count 2 2006.285.22:32:25.59#ibcon#about to read 3, iclass 31, count 2 2006.285.22:32:25.61#ibcon#read 3, iclass 31, count 2 2006.285.22:32:25.61#ibcon#about to read 4, iclass 31, count 2 2006.285.22:32:25.61#ibcon#read 4, iclass 31, count 2 2006.285.22:32:25.61#ibcon#about to read 5, iclass 31, count 2 2006.285.22:32:25.61#ibcon#read 5, iclass 31, count 2 2006.285.22:32:25.61#ibcon#about to read 6, iclass 31, count 2 2006.285.22:32:25.61#ibcon#read 6, iclass 31, count 2 2006.285.22:32:25.61#ibcon#end of sib2, iclass 31, count 2 2006.285.22:32:25.61#ibcon#*mode == 0, iclass 31, count 2 2006.285.22:32:25.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.22:32:25.61#ibcon#[25=AT04-06\r\n] 2006.285.22:32:25.61#ibcon#*before write, iclass 31, count 2 2006.285.22:32:25.61#ibcon#enter sib2, iclass 31, count 2 2006.285.22:32:25.61#ibcon#flushed, iclass 31, count 2 2006.285.22:32:25.61#ibcon#about to write, iclass 31, count 2 2006.285.22:32:25.61#ibcon#wrote, iclass 31, count 2 2006.285.22:32:25.61#ibcon#about to read 3, iclass 31, count 2 2006.285.22:32:25.64#ibcon#read 3, iclass 31, count 2 2006.285.22:32:25.64#ibcon#about to read 4, iclass 31, count 2 2006.285.22:32:25.64#ibcon#read 4, iclass 31, count 2 2006.285.22:32:25.64#ibcon#about to read 5, iclass 31, count 2 2006.285.22:32:25.64#ibcon#read 5, iclass 31, count 2 2006.285.22:32:25.64#ibcon#about to read 6, iclass 31, count 2 2006.285.22:32:25.64#ibcon#read 6, iclass 31, count 2 2006.285.22:32:25.64#ibcon#end of sib2, iclass 31, count 2 2006.285.22:32:25.64#ibcon#*after write, iclass 31, count 2 2006.285.22:32:25.64#ibcon#*before return 0, iclass 31, count 2 2006.285.22:32:25.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:32:25.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:32:25.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.22:32:25.64#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:25.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:32:25.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:32:25.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:32:25.76#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:32:25.76#ibcon#first serial, iclass 31, count 0 2006.285.22:32:25.76#ibcon#enter sib2, iclass 31, count 0 2006.285.22:32:25.76#ibcon#flushed, iclass 31, count 0 2006.285.22:32:25.76#ibcon#about to write, iclass 31, count 0 2006.285.22:32:25.76#ibcon#wrote, iclass 31, count 0 2006.285.22:32:25.76#ibcon#about to read 3, iclass 31, count 0 2006.285.22:32:25.78#ibcon#read 3, iclass 31, count 0 2006.285.22:32:25.78#ibcon#about to read 4, iclass 31, count 0 2006.285.22:32:25.78#ibcon#read 4, iclass 31, count 0 2006.285.22:32:25.78#ibcon#about to read 5, iclass 31, count 0 2006.285.22:32:25.78#ibcon#read 5, iclass 31, count 0 2006.285.22:32:25.78#ibcon#about to read 6, iclass 31, count 0 2006.285.22:32:25.78#ibcon#read 6, iclass 31, count 0 2006.285.22:32:25.78#ibcon#end of sib2, iclass 31, count 0 2006.285.22:32:25.78#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:32:25.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:32:25.78#ibcon#[25=USB\r\n] 2006.285.22:32:25.78#ibcon#*before write, iclass 31, count 0 2006.285.22:32:25.78#ibcon#enter sib2, iclass 31, count 0 2006.285.22:32:25.78#ibcon#flushed, iclass 31, count 0 2006.285.22:32:25.78#ibcon#about to write, iclass 31, count 0 2006.285.22:32:25.78#ibcon#wrote, iclass 31, count 0 2006.285.22:32:25.78#ibcon#about to read 3, iclass 31, count 0 2006.285.22:32:25.81#ibcon#read 3, iclass 31, count 0 2006.285.22:32:25.81#ibcon#about to read 4, iclass 31, count 0 2006.285.22:32:25.81#ibcon#read 4, iclass 31, count 0 2006.285.22:32:25.81#ibcon#about to read 5, iclass 31, count 0 2006.285.22:32:25.81#ibcon#read 5, iclass 31, count 0 2006.285.22:32:25.81#ibcon#about to read 6, iclass 31, count 0 2006.285.22:32:25.81#ibcon#read 6, iclass 31, count 0 2006.285.22:32:25.81#ibcon#end of sib2, iclass 31, count 0 2006.285.22:32:25.81#ibcon#*after write, iclass 31, count 0 2006.285.22:32:25.81#ibcon#*before return 0, iclass 31, count 0 2006.285.22:32:25.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:32:25.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:32:25.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:32:25.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:32:25.81$vck44/valo=5,734.99 2006.285.22:32:25.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.22:32:25.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.22:32:25.81#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:25.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:32:25.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:32:25.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:32:25.81#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:32:25.81#ibcon#first serial, iclass 33, count 0 2006.285.22:32:25.81#ibcon#enter sib2, iclass 33, count 0 2006.285.22:32:25.81#ibcon#flushed, iclass 33, count 0 2006.285.22:32:25.81#ibcon#about to write, iclass 33, count 0 2006.285.22:32:25.81#ibcon#wrote, iclass 33, count 0 2006.285.22:32:25.81#ibcon#about to read 3, iclass 33, count 0 2006.285.22:32:25.83#ibcon#read 3, iclass 33, count 0 2006.285.22:32:25.83#ibcon#about to read 4, iclass 33, count 0 2006.285.22:32:25.83#ibcon#read 4, iclass 33, count 0 2006.285.22:32:25.83#ibcon#about to read 5, iclass 33, count 0 2006.285.22:32:25.83#ibcon#read 5, iclass 33, count 0 2006.285.22:32:25.83#ibcon#about to read 6, iclass 33, count 0 2006.285.22:32:25.83#ibcon#read 6, iclass 33, count 0 2006.285.22:32:25.83#ibcon#end of sib2, iclass 33, count 0 2006.285.22:32:25.83#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:32:25.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:32:25.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:32:25.83#ibcon#*before write, iclass 33, count 0 2006.285.22:32:25.83#ibcon#enter sib2, iclass 33, count 0 2006.285.22:32:25.83#ibcon#flushed, iclass 33, count 0 2006.285.22:32:25.83#ibcon#about to write, iclass 33, count 0 2006.285.22:32:25.83#ibcon#wrote, iclass 33, count 0 2006.285.22:32:25.83#ibcon#about to read 3, iclass 33, count 0 2006.285.22:32:25.87#ibcon#read 3, iclass 33, count 0 2006.285.22:32:25.87#ibcon#about to read 4, iclass 33, count 0 2006.285.22:32:25.87#ibcon#read 4, iclass 33, count 0 2006.285.22:32:25.87#ibcon#about to read 5, iclass 33, count 0 2006.285.22:32:25.87#ibcon#read 5, iclass 33, count 0 2006.285.22:32:25.87#ibcon#about to read 6, iclass 33, count 0 2006.285.22:32:25.87#ibcon#read 6, iclass 33, count 0 2006.285.22:32:25.87#ibcon#end of sib2, iclass 33, count 0 2006.285.22:32:25.87#ibcon#*after write, iclass 33, count 0 2006.285.22:32:25.87#ibcon#*before return 0, iclass 33, count 0 2006.285.22:32:25.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:32:25.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:32:25.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:32:25.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:32:25.87$vck44/va=5,3 2006.285.22:32:25.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.22:32:25.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.22:32:25.87#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:25.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:32:25.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:32:25.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:32:25.93#ibcon#enter wrdev, iclass 35, count 2 2006.285.22:32:25.93#ibcon#first serial, iclass 35, count 2 2006.285.22:32:25.93#ibcon#enter sib2, iclass 35, count 2 2006.285.22:32:25.93#ibcon#flushed, iclass 35, count 2 2006.285.22:32:25.93#ibcon#about to write, iclass 35, count 2 2006.285.22:32:25.93#ibcon#wrote, iclass 35, count 2 2006.285.22:32:25.93#ibcon#about to read 3, iclass 35, count 2 2006.285.22:32:25.95#ibcon#read 3, iclass 35, count 2 2006.285.22:32:25.95#ibcon#about to read 4, iclass 35, count 2 2006.285.22:32:25.95#ibcon#read 4, iclass 35, count 2 2006.285.22:32:25.95#ibcon#about to read 5, iclass 35, count 2 2006.285.22:32:25.95#ibcon#read 5, iclass 35, count 2 2006.285.22:32:25.95#ibcon#about to read 6, iclass 35, count 2 2006.285.22:32:25.95#ibcon#read 6, iclass 35, count 2 2006.285.22:32:25.95#ibcon#end of sib2, iclass 35, count 2 2006.285.22:32:25.95#ibcon#*mode == 0, iclass 35, count 2 2006.285.22:32:25.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.22:32:25.95#ibcon#[25=AT05-03\r\n] 2006.285.22:32:25.95#ibcon#*before write, iclass 35, count 2 2006.285.22:32:25.95#ibcon#enter sib2, iclass 35, count 2 2006.285.22:32:25.95#ibcon#flushed, iclass 35, count 2 2006.285.22:32:25.95#ibcon#about to write, iclass 35, count 2 2006.285.22:32:25.95#ibcon#wrote, iclass 35, count 2 2006.285.22:32:25.95#ibcon#about to read 3, iclass 35, count 2 2006.285.22:32:25.98#ibcon#read 3, iclass 35, count 2 2006.285.22:32:25.98#ibcon#about to read 4, iclass 35, count 2 2006.285.22:32:25.98#ibcon#read 4, iclass 35, count 2 2006.285.22:32:25.98#ibcon#about to read 5, iclass 35, count 2 2006.285.22:32:25.98#ibcon#read 5, iclass 35, count 2 2006.285.22:32:25.98#ibcon#about to read 6, iclass 35, count 2 2006.285.22:32:25.98#ibcon#read 6, iclass 35, count 2 2006.285.22:32:25.98#ibcon#end of sib2, iclass 35, count 2 2006.285.22:32:25.98#ibcon#*after write, iclass 35, count 2 2006.285.22:32:25.98#ibcon#*before return 0, iclass 35, count 2 2006.285.22:32:25.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:32:25.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:32:25.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.22:32:25.98#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:25.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:32:26.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:32:26.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:32:26.10#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:32:26.10#ibcon#first serial, iclass 35, count 0 2006.285.22:32:26.10#ibcon#enter sib2, iclass 35, count 0 2006.285.22:32:26.10#ibcon#flushed, iclass 35, count 0 2006.285.22:32:26.10#ibcon#about to write, iclass 35, count 0 2006.285.22:32:26.10#ibcon#wrote, iclass 35, count 0 2006.285.22:32:26.10#ibcon#about to read 3, iclass 35, count 0 2006.285.22:32:26.12#ibcon#read 3, iclass 35, count 0 2006.285.22:32:26.12#ibcon#about to read 4, iclass 35, count 0 2006.285.22:32:26.12#ibcon#read 4, iclass 35, count 0 2006.285.22:32:26.12#ibcon#about to read 5, iclass 35, count 0 2006.285.22:32:26.12#ibcon#read 5, iclass 35, count 0 2006.285.22:32:26.12#ibcon#about to read 6, iclass 35, count 0 2006.285.22:32:26.12#ibcon#read 6, iclass 35, count 0 2006.285.22:32:26.12#ibcon#end of sib2, iclass 35, count 0 2006.285.22:32:26.12#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:32:26.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:32:26.12#ibcon#[25=USB\r\n] 2006.285.22:32:26.12#ibcon#*before write, iclass 35, count 0 2006.285.22:32:26.12#ibcon#enter sib2, iclass 35, count 0 2006.285.22:32:26.12#ibcon#flushed, iclass 35, count 0 2006.285.22:32:26.12#ibcon#about to write, iclass 35, count 0 2006.285.22:32:26.12#ibcon#wrote, iclass 35, count 0 2006.285.22:32:26.12#ibcon#about to read 3, iclass 35, count 0 2006.285.22:32:26.15#ibcon#read 3, iclass 35, count 0 2006.285.22:32:26.15#ibcon#about to read 4, iclass 35, count 0 2006.285.22:32:26.15#ibcon#read 4, iclass 35, count 0 2006.285.22:32:26.15#ibcon#about to read 5, iclass 35, count 0 2006.285.22:32:26.15#ibcon#read 5, iclass 35, count 0 2006.285.22:32:26.15#ibcon#about to read 6, iclass 35, count 0 2006.285.22:32:26.15#ibcon#read 6, iclass 35, count 0 2006.285.22:32:26.15#ibcon#end of sib2, iclass 35, count 0 2006.285.22:32:26.15#ibcon#*after write, iclass 35, count 0 2006.285.22:32:26.15#ibcon#*before return 0, iclass 35, count 0 2006.285.22:32:26.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:32:26.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:32:26.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:32:26.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:32:26.15$vck44/valo=6,814.99 2006.285.22:32:26.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.22:32:26.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.22:32:26.15#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:26.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:32:26.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:32:26.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:32:26.15#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:32:26.15#ibcon#first serial, iclass 37, count 0 2006.285.22:32:26.15#ibcon#enter sib2, iclass 37, count 0 2006.285.22:32:26.15#ibcon#flushed, iclass 37, count 0 2006.285.22:32:26.15#ibcon#about to write, iclass 37, count 0 2006.285.22:32:26.15#ibcon#wrote, iclass 37, count 0 2006.285.22:32:26.15#ibcon#about to read 3, iclass 37, count 0 2006.285.22:32:26.17#ibcon#read 3, iclass 37, count 0 2006.285.22:32:26.17#ibcon#about to read 4, iclass 37, count 0 2006.285.22:32:26.17#ibcon#read 4, iclass 37, count 0 2006.285.22:32:26.17#ibcon#about to read 5, iclass 37, count 0 2006.285.22:32:26.17#ibcon#read 5, iclass 37, count 0 2006.285.22:32:26.17#ibcon#about to read 6, iclass 37, count 0 2006.285.22:32:26.17#ibcon#read 6, iclass 37, count 0 2006.285.22:32:26.17#ibcon#end of sib2, iclass 37, count 0 2006.285.22:32:26.17#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:32:26.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:32:26.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:32:26.17#ibcon#*before write, iclass 37, count 0 2006.285.22:32:26.17#ibcon#enter sib2, iclass 37, count 0 2006.285.22:32:26.17#ibcon#flushed, iclass 37, count 0 2006.285.22:32:26.17#ibcon#about to write, iclass 37, count 0 2006.285.22:32:26.17#ibcon#wrote, iclass 37, count 0 2006.285.22:32:26.17#ibcon#about to read 3, iclass 37, count 0 2006.285.22:32:26.21#ibcon#read 3, iclass 37, count 0 2006.285.22:32:26.21#ibcon#about to read 4, iclass 37, count 0 2006.285.22:32:26.21#ibcon#read 4, iclass 37, count 0 2006.285.22:32:26.21#ibcon#about to read 5, iclass 37, count 0 2006.285.22:32:26.21#ibcon#read 5, iclass 37, count 0 2006.285.22:32:26.21#ibcon#about to read 6, iclass 37, count 0 2006.285.22:32:26.21#ibcon#read 6, iclass 37, count 0 2006.285.22:32:26.21#ibcon#end of sib2, iclass 37, count 0 2006.285.22:32:26.21#ibcon#*after write, iclass 37, count 0 2006.285.22:32:26.21#ibcon#*before return 0, iclass 37, count 0 2006.285.22:32:26.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:32:26.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:32:26.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:32:26.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:32:26.21$vck44/va=6,4 2006.285.22:32:26.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.22:32:26.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.22:32:26.21#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:26.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:32:26.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:32:26.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:32:26.27#ibcon#enter wrdev, iclass 39, count 2 2006.285.22:32:26.27#ibcon#first serial, iclass 39, count 2 2006.285.22:32:26.27#ibcon#enter sib2, iclass 39, count 2 2006.285.22:32:26.27#ibcon#flushed, iclass 39, count 2 2006.285.22:32:26.27#ibcon#about to write, iclass 39, count 2 2006.285.22:32:26.27#ibcon#wrote, iclass 39, count 2 2006.285.22:32:26.27#ibcon#about to read 3, iclass 39, count 2 2006.285.22:32:26.29#ibcon#read 3, iclass 39, count 2 2006.285.22:32:26.29#ibcon#about to read 4, iclass 39, count 2 2006.285.22:32:26.29#ibcon#read 4, iclass 39, count 2 2006.285.22:32:26.29#ibcon#about to read 5, iclass 39, count 2 2006.285.22:32:26.29#ibcon#read 5, iclass 39, count 2 2006.285.22:32:26.29#ibcon#about to read 6, iclass 39, count 2 2006.285.22:32:26.29#ibcon#read 6, iclass 39, count 2 2006.285.22:32:26.29#ibcon#end of sib2, iclass 39, count 2 2006.285.22:32:26.29#ibcon#*mode == 0, iclass 39, count 2 2006.285.22:32:26.29#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.22:32:26.29#ibcon#[25=AT06-04\r\n] 2006.285.22:32:26.29#ibcon#*before write, iclass 39, count 2 2006.285.22:32:26.29#ibcon#enter sib2, iclass 39, count 2 2006.285.22:32:26.29#ibcon#flushed, iclass 39, count 2 2006.285.22:32:26.29#ibcon#about to write, iclass 39, count 2 2006.285.22:32:26.29#ibcon#wrote, iclass 39, count 2 2006.285.22:32:26.29#ibcon#about to read 3, iclass 39, count 2 2006.285.22:32:26.32#ibcon#read 3, iclass 39, count 2 2006.285.22:32:26.32#ibcon#about to read 4, iclass 39, count 2 2006.285.22:32:26.32#ibcon#read 4, iclass 39, count 2 2006.285.22:32:26.32#ibcon#about to read 5, iclass 39, count 2 2006.285.22:32:26.32#ibcon#read 5, iclass 39, count 2 2006.285.22:32:26.32#ibcon#about to read 6, iclass 39, count 2 2006.285.22:32:26.32#ibcon#read 6, iclass 39, count 2 2006.285.22:32:26.32#ibcon#end of sib2, iclass 39, count 2 2006.285.22:32:26.32#ibcon#*after write, iclass 39, count 2 2006.285.22:32:26.32#ibcon#*before return 0, iclass 39, count 2 2006.285.22:32:26.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:32:26.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:32:26.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.22:32:26.32#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:26.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:32:26.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:32:26.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:32:26.44#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:32:26.44#ibcon#first serial, iclass 39, count 0 2006.285.22:32:26.44#ibcon#enter sib2, iclass 39, count 0 2006.285.22:32:26.44#ibcon#flushed, iclass 39, count 0 2006.285.22:32:26.44#ibcon#about to write, iclass 39, count 0 2006.285.22:32:26.44#ibcon#wrote, iclass 39, count 0 2006.285.22:32:26.44#ibcon#about to read 3, iclass 39, count 0 2006.285.22:32:26.46#ibcon#read 3, iclass 39, count 0 2006.285.22:32:26.46#ibcon#about to read 4, iclass 39, count 0 2006.285.22:32:26.46#ibcon#read 4, iclass 39, count 0 2006.285.22:32:26.46#ibcon#about to read 5, iclass 39, count 0 2006.285.22:32:26.46#ibcon#read 5, iclass 39, count 0 2006.285.22:32:26.46#ibcon#about to read 6, iclass 39, count 0 2006.285.22:32:26.46#ibcon#read 6, iclass 39, count 0 2006.285.22:32:26.46#ibcon#end of sib2, iclass 39, count 0 2006.285.22:32:26.46#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:32:26.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:32:26.46#ibcon#[25=USB\r\n] 2006.285.22:32:26.46#ibcon#*before write, iclass 39, count 0 2006.285.22:32:26.46#ibcon#enter sib2, iclass 39, count 0 2006.285.22:32:26.46#ibcon#flushed, iclass 39, count 0 2006.285.22:32:26.46#ibcon#about to write, iclass 39, count 0 2006.285.22:32:26.46#ibcon#wrote, iclass 39, count 0 2006.285.22:32:26.46#ibcon#about to read 3, iclass 39, count 0 2006.285.22:32:26.49#ibcon#read 3, iclass 39, count 0 2006.285.22:32:26.49#ibcon#about to read 4, iclass 39, count 0 2006.285.22:32:26.49#ibcon#read 4, iclass 39, count 0 2006.285.22:32:26.49#ibcon#about to read 5, iclass 39, count 0 2006.285.22:32:26.49#ibcon#read 5, iclass 39, count 0 2006.285.22:32:26.49#ibcon#about to read 6, iclass 39, count 0 2006.285.22:32:26.49#ibcon#read 6, iclass 39, count 0 2006.285.22:32:26.49#ibcon#end of sib2, iclass 39, count 0 2006.285.22:32:26.49#ibcon#*after write, iclass 39, count 0 2006.285.22:32:26.49#ibcon#*before return 0, iclass 39, count 0 2006.285.22:32:26.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:32:26.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:32:26.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:32:26.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:32:26.49$vck44/valo=7,864.99 2006.285.22:32:26.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.22:32:26.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.22:32:26.49#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:26.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:32:26.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:32:26.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:32:26.49#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:32:26.49#ibcon#first serial, iclass 3, count 0 2006.285.22:32:26.49#ibcon#enter sib2, iclass 3, count 0 2006.285.22:32:26.49#ibcon#flushed, iclass 3, count 0 2006.285.22:32:26.49#ibcon#about to write, iclass 3, count 0 2006.285.22:32:26.49#ibcon#wrote, iclass 3, count 0 2006.285.22:32:26.49#ibcon#about to read 3, iclass 3, count 0 2006.285.22:32:26.51#ibcon#read 3, iclass 3, count 0 2006.285.22:32:26.51#ibcon#about to read 4, iclass 3, count 0 2006.285.22:32:26.51#ibcon#read 4, iclass 3, count 0 2006.285.22:32:26.51#ibcon#about to read 5, iclass 3, count 0 2006.285.22:32:26.51#ibcon#read 5, iclass 3, count 0 2006.285.22:32:26.51#ibcon#about to read 6, iclass 3, count 0 2006.285.22:32:26.51#ibcon#read 6, iclass 3, count 0 2006.285.22:32:26.51#ibcon#end of sib2, iclass 3, count 0 2006.285.22:32:26.51#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:32:26.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:32:26.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:32:26.51#ibcon#*before write, iclass 3, count 0 2006.285.22:32:26.51#ibcon#enter sib2, iclass 3, count 0 2006.285.22:32:26.51#ibcon#flushed, iclass 3, count 0 2006.285.22:32:26.51#ibcon#about to write, iclass 3, count 0 2006.285.22:32:26.51#ibcon#wrote, iclass 3, count 0 2006.285.22:32:26.51#ibcon#about to read 3, iclass 3, count 0 2006.285.22:32:26.55#ibcon#read 3, iclass 3, count 0 2006.285.22:32:26.55#ibcon#about to read 4, iclass 3, count 0 2006.285.22:32:26.55#ibcon#read 4, iclass 3, count 0 2006.285.22:32:26.55#ibcon#about to read 5, iclass 3, count 0 2006.285.22:32:26.55#ibcon#read 5, iclass 3, count 0 2006.285.22:32:26.55#ibcon#about to read 6, iclass 3, count 0 2006.285.22:32:26.55#ibcon#read 6, iclass 3, count 0 2006.285.22:32:26.55#ibcon#end of sib2, iclass 3, count 0 2006.285.22:32:26.55#ibcon#*after write, iclass 3, count 0 2006.285.22:32:26.55#ibcon#*before return 0, iclass 3, count 0 2006.285.22:32:26.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:32:26.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:32:26.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:32:26.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:32:26.55$vck44/va=7,4 2006.285.22:32:26.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.22:32:26.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.22:32:26.55#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:26.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:32:26.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:32:26.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:32:26.61#ibcon#enter wrdev, iclass 5, count 2 2006.285.22:32:26.61#ibcon#first serial, iclass 5, count 2 2006.285.22:32:26.61#ibcon#enter sib2, iclass 5, count 2 2006.285.22:32:26.61#ibcon#flushed, iclass 5, count 2 2006.285.22:32:26.61#ibcon#about to write, iclass 5, count 2 2006.285.22:32:26.61#ibcon#wrote, iclass 5, count 2 2006.285.22:32:26.61#ibcon#about to read 3, iclass 5, count 2 2006.285.22:32:26.63#ibcon#read 3, iclass 5, count 2 2006.285.22:32:26.63#ibcon#about to read 4, iclass 5, count 2 2006.285.22:32:26.63#ibcon#read 4, iclass 5, count 2 2006.285.22:32:26.63#ibcon#about to read 5, iclass 5, count 2 2006.285.22:32:26.63#ibcon#read 5, iclass 5, count 2 2006.285.22:32:26.63#ibcon#about to read 6, iclass 5, count 2 2006.285.22:32:26.63#ibcon#read 6, iclass 5, count 2 2006.285.22:32:26.63#ibcon#end of sib2, iclass 5, count 2 2006.285.22:32:26.63#ibcon#*mode == 0, iclass 5, count 2 2006.285.22:32:26.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.22:32:26.63#ibcon#[25=AT07-04\r\n] 2006.285.22:32:26.63#ibcon#*before write, iclass 5, count 2 2006.285.22:32:26.63#ibcon#enter sib2, iclass 5, count 2 2006.285.22:32:26.63#ibcon#flushed, iclass 5, count 2 2006.285.22:32:26.63#ibcon#about to write, iclass 5, count 2 2006.285.22:32:26.63#ibcon#wrote, iclass 5, count 2 2006.285.22:32:26.63#ibcon#about to read 3, iclass 5, count 2 2006.285.22:32:26.66#ibcon#read 3, iclass 5, count 2 2006.285.22:32:26.66#ibcon#about to read 4, iclass 5, count 2 2006.285.22:32:26.66#ibcon#read 4, iclass 5, count 2 2006.285.22:32:26.66#ibcon#about to read 5, iclass 5, count 2 2006.285.22:32:26.66#ibcon#read 5, iclass 5, count 2 2006.285.22:32:26.66#ibcon#about to read 6, iclass 5, count 2 2006.285.22:32:26.66#ibcon#read 6, iclass 5, count 2 2006.285.22:32:26.66#ibcon#end of sib2, iclass 5, count 2 2006.285.22:32:26.66#ibcon#*after write, iclass 5, count 2 2006.285.22:32:26.66#ibcon#*before return 0, iclass 5, count 2 2006.285.22:32:26.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:32:26.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:32:26.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.22:32:26.66#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:26.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:32:26.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:32:26.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:32:26.78#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:32:26.78#ibcon#first serial, iclass 5, count 0 2006.285.22:32:26.78#ibcon#enter sib2, iclass 5, count 0 2006.285.22:32:26.78#ibcon#flushed, iclass 5, count 0 2006.285.22:32:26.78#ibcon#about to write, iclass 5, count 0 2006.285.22:32:26.78#ibcon#wrote, iclass 5, count 0 2006.285.22:32:26.78#ibcon#about to read 3, iclass 5, count 0 2006.285.22:32:26.80#ibcon#read 3, iclass 5, count 0 2006.285.22:32:26.80#ibcon#about to read 4, iclass 5, count 0 2006.285.22:32:26.80#ibcon#read 4, iclass 5, count 0 2006.285.22:32:26.80#ibcon#about to read 5, iclass 5, count 0 2006.285.22:32:26.80#ibcon#read 5, iclass 5, count 0 2006.285.22:32:26.80#ibcon#about to read 6, iclass 5, count 0 2006.285.22:32:26.80#ibcon#read 6, iclass 5, count 0 2006.285.22:32:26.80#ibcon#end of sib2, iclass 5, count 0 2006.285.22:32:26.80#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:32:26.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:32:26.80#ibcon#[25=USB\r\n] 2006.285.22:32:26.80#ibcon#*before write, iclass 5, count 0 2006.285.22:32:26.80#ibcon#enter sib2, iclass 5, count 0 2006.285.22:32:26.80#ibcon#flushed, iclass 5, count 0 2006.285.22:32:26.80#ibcon#about to write, iclass 5, count 0 2006.285.22:32:26.80#ibcon#wrote, iclass 5, count 0 2006.285.22:32:26.80#ibcon#about to read 3, iclass 5, count 0 2006.285.22:32:26.83#ibcon#read 3, iclass 5, count 0 2006.285.22:32:26.83#ibcon#about to read 4, iclass 5, count 0 2006.285.22:32:26.83#ibcon#read 4, iclass 5, count 0 2006.285.22:32:26.83#ibcon#about to read 5, iclass 5, count 0 2006.285.22:32:26.83#ibcon#read 5, iclass 5, count 0 2006.285.22:32:26.83#ibcon#about to read 6, iclass 5, count 0 2006.285.22:32:26.83#ibcon#read 6, iclass 5, count 0 2006.285.22:32:26.83#ibcon#end of sib2, iclass 5, count 0 2006.285.22:32:26.83#ibcon#*after write, iclass 5, count 0 2006.285.22:32:26.83#ibcon#*before return 0, iclass 5, count 0 2006.285.22:32:26.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:32:26.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:32:26.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:32:26.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:32:26.83$vck44/valo=8,884.99 2006.285.22:32:26.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.22:32:26.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.22:32:26.83#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:26.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:32:26.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:32:26.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:32:26.83#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:32:26.83#ibcon#first serial, iclass 7, count 0 2006.285.22:32:26.83#ibcon#enter sib2, iclass 7, count 0 2006.285.22:32:26.83#ibcon#flushed, iclass 7, count 0 2006.285.22:32:26.83#ibcon#about to write, iclass 7, count 0 2006.285.22:32:26.83#ibcon#wrote, iclass 7, count 0 2006.285.22:32:26.83#ibcon#about to read 3, iclass 7, count 0 2006.285.22:32:26.85#ibcon#read 3, iclass 7, count 0 2006.285.22:32:26.85#ibcon#about to read 4, iclass 7, count 0 2006.285.22:32:26.85#ibcon#read 4, iclass 7, count 0 2006.285.22:32:26.85#ibcon#about to read 5, iclass 7, count 0 2006.285.22:32:26.85#ibcon#read 5, iclass 7, count 0 2006.285.22:32:26.85#ibcon#about to read 6, iclass 7, count 0 2006.285.22:32:26.85#ibcon#read 6, iclass 7, count 0 2006.285.22:32:26.85#ibcon#end of sib2, iclass 7, count 0 2006.285.22:32:26.85#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:32:26.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:32:26.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:32:26.85#ibcon#*before write, iclass 7, count 0 2006.285.22:32:26.85#ibcon#enter sib2, iclass 7, count 0 2006.285.22:32:26.85#ibcon#flushed, iclass 7, count 0 2006.285.22:32:26.85#ibcon#about to write, iclass 7, count 0 2006.285.22:32:26.85#ibcon#wrote, iclass 7, count 0 2006.285.22:32:26.85#ibcon#about to read 3, iclass 7, count 0 2006.285.22:32:26.89#ibcon#read 3, iclass 7, count 0 2006.285.22:32:26.89#ibcon#about to read 4, iclass 7, count 0 2006.285.22:32:26.89#ibcon#read 4, iclass 7, count 0 2006.285.22:32:26.89#ibcon#about to read 5, iclass 7, count 0 2006.285.22:32:26.89#ibcon#read 5, iclass 7, count 0 2006.285.22:32:26.89#ibcon#about to read 6, iclass 7, count 0 2006.285.22:32:26.89#ibcon#read 6, iclass 7, count 0 2006.285.22:32:26.89#ibcon#end of sib2, iclass 7, count 0 2006.285.22:32:26.89#ibcon#*after write, iclass 7, count 0 2006.285.22:32:26.89#ibcon#*before return 0, iclass 7, count 0 2006.285.22:32:26.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:32:26.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:32:26.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:32:26.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:32:26.89$vck44/va=8,3 2006.285.22:32:26.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.22:32:26.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.22:32:26.89#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:26.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:32:26.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:32:26.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:32:26.95#ibcon#enter wrdev, iclass 11, count 2 2006.285.22:32:26.95#ibcon#first serial, iclass 11, count 2 2006.285.22:32:26.95#ibcon#enter sib2, iclass 11, count 2 2006.285.22:32:26.95#ibcon#flushed, iclass 11, count 2 2006.285.22:32:26.95#ibcon#about to write, iclass 11, count 2 2006.285.22:32:26.95#ibcon#wrote, iclass 11, count 2 2006.285.22:32:26.95#ibcon#about to read 3, iclass 11, count 2 2006.285.22:32:26.97#ibcon#read 3, iclass 11, count 2 2006.285.22:32:26.97#ibcon#about to read 4, iclass 11, count 2 2006.285.22:32:26.97#ibcon#read 4, iclass 11, count 2 2006.285.22:32:26.97#ibcon#about to read 5, iclass 11, count 2 2006.285.22:32:26.97#ibcon#read 5, iclass 11, count 2 2006.285.22:32:26.97#ibcon#about to read 6, iclass 11, count 2 2006.285.22:32:26.97#ibcon#read 6, iclass 11, count 2 2006.285.22:32:26.97#ibcon#end of sib2, iclass 11, count 2 2006.285.22:32:26.97#ibcon#*mode == 0, iclass 11, count 2 2006.285.22:32:26.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.22:32:26.97#ibcon#[25=AT08-03\r\n] 2006.285.22:32:26.97#ibcon#*before write, iclass 11, count 2 2006.285.22:32:26.97#ibcon#enter sib2, iclass 11, count 2 2006.285.22:32:26.97#ibcon#flushed, iclass 11, count 2 2006.285.22:32:26.97#ibcon#about to write, iclass 11, count 2 2006.285.22:32:26.97#ibcon#wrote, iclass 11, count 2 2006.285.22:32:26.97#ibcon#about to read 3, iclass 11, count 2 2006.285.22:32:27.00#ibcon#read 3, iclass 11, count 2 2006.285.22:32:27.00#ibcon#about to read 4, iclass 11, count 2 2006.285.22:32:27.00#ibcon#read 4, iclass 11, count 2 2006.285.22:32:27.00#ibcon#about to read 5, iclass 11, count 2 2006.285.22:32:27.00#ibcon#read 5, iclass 11, count 2 2006.285.22:32:27.00#ibcon#about to read 6, iclass 11, count 2 2006.285.22:32:27.00#ibcon#read 6, iclass 11, count 2 2006.285.22:32:27.00#ibcon#end of sib2, iclass 11, count 2 2006.285.22:32:27.00#ibcon#*after write, iclass 11, count 2 2006.285.22:32:27.00#ibcon#*before return 0, iclass 11, count 2 2006.285.22:32:27.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:32:27.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:32:27.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.22:32:27.00#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:27.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:32:27.06#abcon#<5=/06 0.6 1.6 16.87 971016.1\r\n> 2006.285.22:32:27.08#abcon#{5=INTERFACE CLEAR} 2006.285.22:32:27.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:32:27.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:32:27.12#ibcon#enter wrdev, iclass 11, count 0 2006.285.22:32:27.12#ibcon#first serial, iclass 11, count 0 2006.285.22:32:27.12#ibcon#enter sib2, iclass 11, count 0 2006.285.22:32:27.12#ibcon#flushed, iclass 11, count 0 2006.285.22:32:27.12#ibcon#about to write, iclass 11, count 0 2006.285.22:32:27.12#ibcon#wrote, iclass 11, count 0 2006.285.22:32:27.12#ibcon#about to read 3, iclass 11, count 0 2006.285.22:32:27.14#ibcon#read 3, iclass 11, count 0 2006.285.22:32:27.14#ibcon#about to read 4, iclass 11, count 0 2006.285.22:32:27.14#ibcon#read 4, iclass 11, count 0 2006.285.22:32:27.14#ibcon#about to read 5, iclass 11, count 0 2006.285.22:32:27.14#ibcon#read 5, iclass 11, count 0 2006.285.22:32:27.14#ibcon#about to read 6, iclass 11, count 0 2006.285.22:32:27.14#ibcon#read 6, iclass 11, count 0 2006.285.22:32:27.14#ibcon#end of sib2, iclass 11, count 0 2006.285.22:32:27.14#ibcon#*mode == 0, iclass 11, count 0 2006.285.22:32:27.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.22:32:27.14#ibcon#[25=USB\r\n] 2006.285.22:32:27.14#ibcon#*before write, iclass 11, count 0 2006.285.22:32:27.14#ibcon#enter sib2, iclass 11, count 0 2006.285.22:32:27.14#ibcon#flushed, iclass 11, count 0 2006.285.22:32:27.14#ibcon#about to write, iclass 11, count 0 2006.285.22:32:27.14#ibcon#wrote, iclass 11, count 0 2006.285.22:32:27.14#ibcon#about to read 3, iclass 11, count 0 2006.285.22:32:27.14#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:32:27.17#ibcon#read 3, iclass 11, count 0 2006.285.22:32:27.17#ibcon#about to read 4, iclass 11, count 0 2006.285.22:32:27.17#ibcon#read 4, iclass 11, count 0 2006.285.22:32:27.17#ibcon#about to read 5, iclass 11, count 0 2006.285.22:32:27.17#ibcon#read 5, iclass 11, count 0 2006.285.22:32:27.17#ibcon#about to read 6, iclass 11, count 0 2006.285.22:32:27.17#ibcon#read 6, iclass 11, count 0 2006.285.22:32:27.17#ibcon#end of sib2, iclass 11, count 0 2006.285.22:32:27.17#ibcon#*after write, iclass 11, count 0 2006.285.22:32:27.17#ibcon#*before return 0, iclass 11, count 0 2006.285.22:32:27.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:32:27.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:32:27.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.22:32:27.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.22:32:27.17$vck44/vblo=1,629.99 2006.285.22:32:27.17#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.22:32:27.17#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.22:32:27.17#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:27.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:32:27.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:32:27.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:32:27.17#ibcon#enter wrdev, iclass 17, count 0 2006.285.22:32:27.17#ibcon#first serial, iclass 17, count 0 2006.285.22:32:27.17#ibcon#enter sib2, iclass 17, count 0 2006.285.22:32:27.17#ibcon#flushed, iclass 17, count 0 2006.285.22:32:27.17#ibcon#about to write, iclass 17, count 0 2006.285.22:32:27.17#ibcon#wrote, iclass 17, count 0 2006.285.22:32:27.17#ibcon#about to read 3, iclass 17, count 0 2006.285.22:32:27.19#ibcon#read 3, iclass 17, count 0 2006.285.22:32:27.19#ibcon#about to read 4, iclass 17, count 0 2006.285.22:32:27.19#ibcon#read 4, iclass 17, count 0 2006.285.22:32:27.19#ibcon#about to read 5, iclass 17, count 0 2006.285.22:32:27.19#ibcon#read 5, iclass 17, count 0 2006.285.22:32:27.19#ibcon#about to read 6, iclass 17, count 0 2006.285.22:32:27.19#ibcon#read 6, iclass 17, count 0 2006.285.22:32:27.19#ibcon#end of sib2, iclass 17, count 0 2006.285.22:32:27.19#ibcon#*mode == 0, iclass 17, count 0 2006.285.22:32:27.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.22:32:27.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:32:27.19#ibcon#*before write, iclass 17, count 0 2006.285.22:32:27.19#ibcon#enter sib2, iclass 17, count 0 2006.285.22:32:27.19#ibcon#flushed, iclass 17, count 0 2006.285.22:32:27.19#ibcon#about to write, iclass 17, count 0 2006.285.22:32:27.19#ibcon#wrote, iclass 17, count 0 2006.285.22:32:27.19#ibcon#about to read 3, iclass 17, count 0 2006.285.22:32:27.23#ibcon#read 3, iclass 17, count 0 2006.285.22:32:27.23#ibcon#about to read 4, iclass 17, count 0 2006.285.22:32:27.23#ibcon#read 4, iclass 17, count 0 2006.285.22:32:27.23#ibcon#about to read 5, iclass 17, count 0 2006.285.22:32:27.23#ibcon#read 5, iclass 17, count 0 2006.285.22:32:27.23#ibcon#about to read 6, iclass 17, count 0 2006.285.22:32:27.23#ibcon#read 6, iclass 17, count 0 2006.285.22:32:27.23#ibcon#end of sib2, iclass 17, count 0 2006.285.22:32:27.23#ibcon#*after write, iclass 17, count 0 2006.285.22:32:27.23#ibcon#*before return 0, iclass 17, count 0 2006.285.22:32:27.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:32:27.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:32:27.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.22:32:27.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.22:32:27.23$vck44/vb=1,4 2006.285.22:32:27.23#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.22:32:27.23#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.22:32:27.23#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:27.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:32:27.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:32:27.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:32:27.23#ibcon#enter wrdev, iclass 19, count 2 2006.285.22:32:27.23#ibcon#first serial, iclass 19, count 2 2006.285.22:32:27.23#ibcon#enter sib2, iclass 19, count 2 2006.285.22:32:27.23#ibcon#flushed, iclass 19, count 2 2006.285.22:32:27.23#ibcon#about to write, iclass 19, count 2 2006.285.22:32:27.23#ibcon#wrote, iclass 19, count 2 2006.285.22:32:27.23#ibcon#about to read 3, iclass 19, count 2 2006.285.22:32:27.25#ibcon#read 3, iclass 19, count 2 2006.285.22:32:27.25#ibcon#about to read 4, iclass 19, count 2 2006.285.22:32:27.25#ibcon#read 4, iclass 19, count 2 2006.285.22:32:27.25#ibcon#about to read 5, iclass 19, count 2 2006.285.22:32:27.25#ibcon#read 5, iclass 19, count 2 2006.285.22:32:27.25#ibcon#about to read 6, iclass 19, count 2 2006.285.22:32:27.25#ibcon#read 6, iclass 19, count 2 2006.285.22:32:27.25#ibcon#end of sib2, iclass 19, count 2 2006.285.22:32:27.25#ibcon#*mode == 0, iclass 19, count 2 2006.285.22:32:27.25#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.22:32:27.25#ibcon#[27=AT01-04\r\n] 2006.285.22:32:27.25#ibcon#*before write, iclass 19, count 2 2006.285.22:32:27.25#ibcon#enter sib2, iclass 19, count 2 2006.285.22:32:27.25#ibcon#flushed, iclass 19, count 2 2006.285.22:32:27.25#ibcon#about to write, iclass 19, count 2 2006.285.22:32:27.25#ibcon#wrote, iclass 19, count 2 2006.285.22:32:27.25#ibcon#about to read 3, iclass 19, count 2 2006.285.22:32:27.28#ibcon#read 3, iclass 19, count 2 2006.285.22:32:27.28#ibcon#about to read 4, iclass 19, count 2 2006.285.22:32:27.28#ibcon#read 4, iclass 19, count 2 2006.285.22:32:27.28#ibcon#about to read 5, iclass 19, count 2 2006.285.22:32:27.28#ibcon#read 5, iclass 19, count 2 2006.285.22:32:27.28#ibcon#about to read 6, iclass 19, count 2 2006.285.22:32:27.28#ibcon#read 6, iclass 19, count 2 2006.285.22:32:27.28#ibcon#end of sib2, iclass 19, count 2 2006.285.22:32:27.28#ibcon#*after write, iclass 19, count 2 2006.285.22:32:27.28#ibcon#*before return 0, iclass 19, count 2 2006.285.22:32:27.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:32:27.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:32:27.28#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.22:32:27.28#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:27.28#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:32:27.40#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:32:27.40#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:32:27.40#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:32:27.40#ibcon#first serial, iclass 19, count 0 2006.285.22:32:27.40#ibcon#enter sib2, iclass 19, count 0 2006.285.22:32:27.40#ibcon#flushed, iclass 19, count 0 2006.285.22:32:27.40#ibcon#about to write, iclass 19, count 0 2006.285.22:32:27.40#ibcon#wrote, iclass 19, count 0 2006.285.22:32:27.40#ibcon#about to read 3, iclass 19, count 0 2006.285.22:32:27.42#ibcon#read 3, iclass 19, count 0 2006.285.22:32:27.42#ibcon#about to read 4, iclass 19, count 0 2006.285.22:32:27.42#ibcon#read 4, iclass 19, count 0 2006.285.22:32:27.42#ibcon#about to read 5, iclass 19, count 0 2006.285.22:32:27.42#ibcon#read 5, iclass 19, count 0 2006.285.22:32:27.42#ibcon#about to read 6, iclass 19, count 0 2006.285.22:32:27.42#ibcon#read 6, iclass 19, count 0 2006.285.22:32:27.42#ibcon#end of sib2, iclass 19, count 0 2006.285.22:32:27.42#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:32:27.42#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:32:27.42#ibcon#[27=USB\r\n] 2006.285.22:32:27.42#ibcon#*before write, iclass 19, count 0 2006.285.22:32:27.42#ibcon#enter sib2, iclass 19, count 0 2006.285.22:32:27.42#ibcon#flushed, iclass 19, count 0 2006.285.22:32:27.42#ibcon#about to write, iclass 19, count 0 2006.285.22:32:27.42#ibcon#wrote, iclass 19, count 0 2006.285.22:32:27.42#ibcon#about to read 3, iclass 19, count 0 2006.285.22:32:27.45#ibcon#read 3, iclass 19, count 0 2006.285.22:32:27.45#ibcon#about to read 4, iclass 19, count 0 2006.285.22:32:27.45#ibcon#read 4, iclass 19, count 0 2006.285.22:32:27.45#ibcon#about to read 5, iclass 19, count 0 2006.285.22:32:27.45#ibcon#read 5, iclass 19, count 0 2006.285.22:32:27.45#ibcon#about to read 6, iclass 19, count 0 2006.285.22:32:27.45#ibcon#read 6, iclass 19, count 0 2006.285.22:32:27.45#ibcon#end of sib2, iclass 19, count 0 2006.285.22:32:27.45#ibcon#*after write, iclass 19, count 0 2006.285.22:32:27.45#ibcon#*before return 0, iclass 19, count 0 2006.285.22:32:27.45#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:32:27.45#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:32:27.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:32:27.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:32:27.45$vck44/vblo=2,634.99 2006.285.22:32:27.45#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.22:32:27.45#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.22:32:27.45#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:27.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:32:27.45#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:32:27.45#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:32:27.45#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:32:27.45#ibcon#first serial, iclass 21, count 0 2006.285.22:32:27.45#ibcon#enter sib2, iclass 21, count 0 2006.285.22:32:27.45#ibcon#flushed, iclass 21, count 0 2006.285.22:32:27.45#ibcon#about to write, iclass 21, count 0 2006.285.22:32:27.45#ibcon#wrote, iclass 21, count 0 2006.285.22:32:27.45#ibcon#about to read 3, iclass 21, count 0 2006.285.22:32:27.47#ibcon#read 3, iclass 21, count 0 2006.285.22:32:27.47#ibcon#about to read 4, iclass 21, count 0 2006.285.22:32:27.47#ibcon#read 4, iclass 21, count 0 2006.285.22:32:27.47#ibcon#about to read 5, iclass 21, count 0 2006.285.22:32:27.47#ibcon#read 5, iclass 21, count 0 2006.285.22:32:27.47#ibcon#about to read 6, iclass 21, count 0 2006.285.22:32:27.47#ibcon#read 6, iclass 21, count 0 2006.285.22:32:27.47#ibcon#end of sib2, iclass 21, count 0 2006.285.22:32:27.47#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:32:27.47#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:32:27.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:32:27.47#ibcon#*before write, iclass 21, count 0 2006.285.22:32:27.47#ibcon#enter sib2, iclass 21, count 0 2006.285.22:32:27.47#ibcon#flushed, iclass 21, count 0 2006.285.22:32:27.47#ibcon#about to write, iclass 21, count 0 2006.285.22:32:27.47#ibcon#wrote, iclass 21, count 0 2006.285.22:32:27.47#ibcon#about to read 3, iclass 21, count 0 2006.285.22:32:27.51#ibcon#read 3, iclass 21, count 0 2006.285.22:32:27.51#ibcon#about to read 4, iclass 21, count 0 2006.285.22:32:27.51#ibcon#read 4, iclass 21, count 0 2006.285.22:32:27.51#ibcon#about to read 5, iclass 21, count 0 2006.285.22:32:27.51#ibcon#read 5, iclass 21, count 0 2006.285.22:32:27.51#ibcon#about to read 6, iclass 21, count 0 2006.285.22:32:27.51#ibcon#read 6, iclass 21, count 0 2006.285.22:32:27.51#ibcon#end of sib2, iclass 21, count 0 2006.285.22:32:27.51#ibcon#*after write, iclass 21, count 0 2006.285.22:32:27.51#ibcon#*before return 0, iclass 21, count 0 2006.285.22:32:27.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:32:27.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:32:27.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:32:27.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:32:27.51$vck44/vb=2,5 2006.285.22:32:27.51#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.22:32:27.51#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.22:32:27.51#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:27.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:32:27.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:32:27.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:32:27.57#ibcon#enter wrdev, iclass 23, count 2 2006.285.22:32:27.57#ibcon#first serial, iclass 23, count 2 2006.285.22:32:27.57#ibcon#enter sib2, iclass 23, count 2 2006.285.22:32:27.57#ibcon#flushed, iclass 23, count 2 2006.285.22:32:27.57#ibcon#about to write, iclass 23, count 2 2006.285.22:32:27.57#ibcon#wrote, iclass 23, count 2 2006.285.22:32:27.57#ibcon#about to read 3, iclass 23, count 2 2006.285.22:32:27.59#ibcon#read 3, iclass 23, count 2 2006.285.22:32:27.59#ibcon#about to read 4, iclass 23, count 2 2006.285.22:32:27.59#ibcon#read 4, iclass 23, count 2 2006.285.22:32:27.59#ibcon#about to read 5, iclass 23, count 2 2006.285.22:32:27.59#ibcon#read 5, iclass 23, count 2 2006.285.22:32:27.59#ibcon#about to read 6, iclass 23, count 2 2006.285.22:32:27.59#ibcon#read 6, iclass 23, count 2 2006.285.22:32:27.59#ibcon#end of sib2, iclass 23, count 2 2006.285.22:32:27.59#ibcon#*mode == 0, iclass 23, count 2 2006.285.22:32:27.59#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.22:32:27.59#ibcon#[27=AT02-05\r\n] 2006.285.22:32:27.59#ibcon#*before write, iclass 23, count 2 2006.285.22:32:27.59#ibcon#enter sib2, iclass 23, count 2 2006.285.22:32:27.59#ibcon#flushed, iclass 23, count 2 2006.285.22:32:27.59#ibcon#about to write, iclass 23, count 2 2006.285.22:32:27.59#ibcon#wrote, iclass 23, count 2 2006.285.22:32:27.59#ibcon#about to read 3, iclass 23, count 2 2006.285.22:32:27.62#ibcon#read 3, iclass 23, count 2 2006.285.22:32:27.62#ibcon#about to read 4, iclass 23, count 2 2006.285.22:32:27.62#ibcon#read 4, iclass 23, count 2 2006.285.22:32:27.62#ibcon#about to read 5, iclass 23, count 2 2006.285.22:32:27.62#ibcon#read 5, iclass 23, count 2 2006.285.22:32:27.62#ibcon#about to read 6, iclass 23, count 2 2006.285.22:32:27.62#ibcon#read 6, iclass 23, count 2 2006.285.22:32:27.62#ibcon#end of sib2, iclass 23, count 2 2006.285.22:32:27.62#ibcon#*after write, iclass 23, count 2 2006.285.22:32:27.62#ibcon#*before return 0, iclass 23, count 2 2006.285.22:32:27.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:32:27.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:32:27.62#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.22:32:27.62#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:27.62#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:32:27.74#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:32:27.74#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:32:27.74#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:32:27.74#ibcon#first serial, iclass 23, count 0 2006.285.22:32:27.74#ibcon#enter sib2, iclass 23, count 0 2006.285.22:32:27.74#ibcon#flushed, iclass 23, count 0 2006.285.22:32:27.74#ibcon#about to write, iclass 23, count 0 2006.285.22:32:27.74#ibcon#wrote, iclass 23, count 0 2006.285.22:32:27.74#ibcon#about to read 3, iclass 23, count 0 2006.285.22:32:27.76#ibcon#read 3, iclass 23, count 0 2006.285.22:32:27.76#ibcon#about to read 4, iclass 23, count 0 2006.285.22:32:27.76#ibcon#read 4, iclass 23, count 0 2006.285.22:32:27.76#ibcon#about to read 5, iclass 23, count 0 2006.285.22:32:27.76#ibcon#read 5, iclass 23, count 0 2006.285.22:32:27.76#ibcon#about to read 6, iclass 23, count 0 2006.285.22:32:27.76#ibcon#read 6, iclass 23, count 0 2006.285.22:32:27.76#ibcon#end of sib2, iclass 23, count 0 2006.285.22:32:27.76#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:32:27.76#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:32:27.76#ibcon#[27=USB\r\n] 2006.285.22:32:27.76#ibcon#*before write, iclass 23, count 0 2006.285.22:32:27.76#ibcon#enter sib2, iclass 23, count 0 2006.285.22:32:27.76#ibcon#flushed, iclass 23, count 0 2006.285.22:32:27.76#ibcon#about to write, iclass 23, count 0 2006.285.22:32:27.76#ibcon#wrote, iclass 23, count 0 2006.285.22:32:27.76#ibcon#about to read 3, iclass 23, count 0 2006.285.22:32:27.79#ibcon#read 3, iclass 23, count 0 2006.285.22:32:27.79#ibcon#about to read 4, iclass 23, count 0 2006.285.22:32:27.79#ibcon#read 4, iclass 23, count 0 2006.285.22:32:27.79#ibcon#about to read 5, iclass 23, count 0 2006.285.22:32:27.79#ibcon#read 5, iclass 23, count 0 2006.285.22:32:27.79#ibcon#about to read 6, iclass 23, count 0 2006.285.22:32:27.79#ibcon#read 6, iclass 23, count 0 2006.285.22:32:27.79#ibcon#end of sib2, iclass 23, count 0 2006.285.22:32:27.79#ibcon#*after write, iclass 23, count 0 2006.285.22:32:27.79#ibcon#*before return 0, iclass 23, count 0 2006.285.22:32:27.79#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:32:27.79#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:32:27.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:32:27.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:32:27.79$vck44/vblo=3,649.99 2006.285.22:32:27.79#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.22:32:27.79#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.22:32:27.79#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:27.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:32:27.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:32:27.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:32:27.79#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:32:27.79#ibcon#first serial, iclass 25, count 0 2006.285.22:32:27.79#ibcon#enter sib2, iclass 25, count 0 2006.285.22:32:27.79#ibcon#flushed, iclass 25, count 0 2006.285.22:32:27.79#ibcon#about to write, iclass 25, count 0 2006.285.22:32:27.79#ibcon#wrote, iclass 25, count 0 2006.285.22:32:27.79#ibcon#about to read 3, iclass 25, count 0 2006.285.22:32:27.81#ibcon#read 3, iclass 25, count 0 2006.285.22:32:27.81#ibcon#about to read 4, iclass 25, count 0 2006.285.22:32:27.81#ibcon#read 4, iclass 25, count 0 2006.285.22:32:27.81#ibcon#about to read 5, iclass 25, count 0 2006.285.22:32:27.81#ibcon#read 5, iclass 25, count 0 2006.285.22:32:27.81#ibcon#about to read 6, iclass 25, count 0 2006.285.22:32:27.81#ibcon#read 6, iclass 25, count 0 2006.285.22:32:27.81#ibcon#end of sib2, iclass 25, count 0 2006.285.22:32:27.81#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:32:27.81#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:32:27.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:32:27.81#ibcon#*before write, iclass 25, count 0 2006.285.22:32:27.81#ibcon#enter sib2, iclass 25, count 0 2006.285.22:32:27.81#ibcon#flushed, iclass 25, count 0 2006.285.22:32:27.81#ibcon#about to write, iclass 25, count 0 2006.285.22:32:27.81#ibcon#wrote, iclass 25, count 0 2006.285.22:32:27.81#ibcon#about to read 3, iclass 25, count 0 2006.285.22:32:27.85#ibcon#read 3, iclass 25, count 0 2006.285.22:32:27.85#ibcon#about to read 4, iclass 25, count 0 2006.285.22:32:27.85#ibcon#read 4, iclass 25, count 0 2006.285.22:32:27.85#ibcon#about to read 5, iclass 25, count 0 2006.285.22:32:27.85#ibcon#read 5, iclass 25, count 0 2006.285.22:32:27.85#ibcon#about to read 6, iclass 25, count 0 2006.285.22:32:27.85#ibcon#read 6, iclass 25, count 0 2006.285.22:32:27.85#ibcon#end of sib2, iclass 25, count 0 2006.285.22:32:27.85#ibcon#*after write, iclass 25, count 0 2006.285.22:32:27.85#ibcon#*before return 0, iclass 25, count 0 2006.285.22:32:27.85#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:32:27.85#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:32:27.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:32:27.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:32:27.85$vck44/vb=3,4 2006.285.22:32:27.85#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.22:32:27.85#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.22:32:27.85#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:27.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:32:27.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:32:27.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:32:27.91#ibcon#enter wrdev, iclass 27, count 2 2006.285.22:32:27.91#ibcon#first serial, iclass 27, count 2 2006.285.22:32:27.91#ibcon#enter sib2, iclass 27, count 2 2006.285.22:32:27.91#ibcon#flushed, iclass 27, count 2 2006.285.22:32:27.91#ibcon#about to write, iclass 27, count 2 2006.285.22:32:27.91#ibcon#wrote, iclass 27, count 2 2006.285.22:32:27.91#ibcon#about to read 3, iclass 27, count 2 2006.285.22:32:27.93#ibcon#read 3, iclass 27, count 2 2006.285.22:32:27.93#ibcon#about to read 4, iclass 27, count 2 2006.285.22:32:27.93#ibcon#read 4, iclass 27, count 2 2006.285.22:32:27.93#ibcon#about to read 5, iclass 27, count 2 2006.285.22:32:27.93#ibcon#read 5, iclass 27, count 2 2006.285.22:32:27.93#ibcon#about to read 6, iclass 27, count 2 2006.285.22:32:27.93#ibcon#read 6, iclass 27, count 2 2006.285.22:32:27.93#ibcon#end of sib2, iclass 27, count 2 2006.285.22:32:27.93#ibcon#*mode == 0, iclass 27, count 2 2006.285.22:32:27.93#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.22:32:27.93#ibcon#[27=AT03-04\r\n] 2006.285.22:32:27.93#ibcon#*before write, iclass 27, count 2 2006.285.22:32:27.93#ibcon#enter sib2, iclass 27, count 2 2006.285.22:32:27.93#ibcon#flushed, iclass 27, count 2 2006.285.22:32:27.93#ibcon#about to write, iclass 27, count 2 2006.285.22:32:27.93#ibcon#wrote, iclass 27, count 2 2006.285.22:32:27.93#ibcon#about to read 3, iclass 27, count 2 2006.285.22:32:27.96#ibcon#read 3, iclass 27, count 2 2006.285.22:32:27.96#ibcon#about to read 4, iclass 27, count 2 2006.285.22:32:27.96#ibcon#read 4, iclass 27, count 2 2006.285.22:32:27.96#ibcon#about to read 5, iclass 27, count 2 2006.285.22:32:27.96#ibcon#read 5, iclass 27, count 2 2006.285.22:32:27.96#ibcon#about to read 6, iclass 27, count 2 2006.285.22:32:27.96#ibcon#read 6, iclass 27, count 2 2006.285.22:32:27.96#ibcon#end of sib2, iclass 27, count 2 2006.285.22:32:27.96#ibcon#*after write, iclass 27, count 2 2006.285.22:32:27.96#ibcon#*before return 0, iclass 27, count 2 2006.285.22:32:27.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:32:27.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:32:27.96#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.22:32:27.96#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:27.96#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:32:28.08#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:32:28.08#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:32:28.08#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:32:28.08#ibcon#first serial, iclass 27, count 0 2006.285.22:32:28.08#ibcon#enter sib2, iclass 27, count 0 2006.285.22:32:28.08#ibcon#flushed, iclass 27, count 0 2006.285.22:32:28.08#ibcon#about to write, iclass 27, count 0 2006.285.22:32:28.08#ibcon#wrote, iclass 27, count 0 2006.285.22:32:28.08#ibcon#about to read 3, iclass 27, count 0 2006.285.22:32:28.10#ibcon#read 3, iclass 27, count 0 2006.285.22:32:28.10#ibcon#about to read 4, iclass 27, count 0 2006.285.22:32:28.10#ibcon#read 4, iclass 27, count 0 2006.285.22:32:28.10#ibcon#about to read 5, iclass 27, count 0 2006.285.22:32:28.10#ibcon#read 5, iclass 27, count 0 2006.285.22:32:28.10#ibcon#about to read 6, iclass 27, count 0 2006.285.22:32:28.10#ibcon#read 6, iclass 27, count 0 2006.285.22:32:28.10#ibcon#end of sib2, iclass 27, count 0 2006.285.22:32:28.10#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:32:28.10#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:32:28.10#ibcon#[27=USB\r\n] 2006.285.22:32:28.10#ibcon#*before write, iclass 27, count 0 2006.285.22:32:28.10#ibcon#enter sib2, iclass 27, count 0 2006.285.22:32:28.10#ibcon#flushed, iclass 27, count 0 2006.285.22:32:28.10#ibcon#about to write, iclass 27, count 0 2006.285.22:32:28.10#ibcon#wrote, iclass 27, count 0 2006.285.22:32:28.10#ibcon#about to read 3, iclass 27, count 0 2006.285.22:32:28.13#ibcon#read 3, iclass 27, count 0 2006.285.22:32:28.13#ibcon#about to read 4, iclass 27, count 0 2006.285.22:32:28.13#ibcon#read 4, iclass 27, count 0 2006.285.22:32:28.13#ibcon#about to read 5, iclass 27, count 0 2006.285.22:32:28.13#ibcon#read 5, iclass 27, count 0 2006.285.22:32:28.13#ibcon#about to read 6, iclass 27, count 0 2006.285.22:32:28.13#ibcon#read 6, iclass 27, count 0 2006.285.22:32:28.13#ibcon#end of sib2, iclass 27, count 0 2006.285.22:32:28.13#ibcon#*after write, iclass 27, count 0 2006.285.22:32:28.13#ibcon#*before return 0, iclass 27, count 0 2006.285.22:32:28.13#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:32:28.13#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:32:28.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:32:28.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:32:28.13$vck44/vblo=4,679.99 2006.285.22:32:28.13#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.22:32:28.13#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.22:32:28.13#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:28.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:32:28.13#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:32:28.13#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:32:28.13#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:32:28.13#ibcon#first serial, iclass 29, count 0 2006.285.22:32:28.13#ibcon#enter sib2, iclass 29, count 0 2006.285.22:32:28.13#ibcon#flushed, iclass 29, count 0 2006.285.22:32:28.13#ibcon#about to write, iclass 29, count 0 2006.285.22:32:28.13#ibcon#wrote, iclass 29, count 0 2006.285.22:32:28.13#ibcon#about to read 3, iclass 29, count 0 2006.285.22:32:28.15#ibcon#read 3, iclass 29, count 0 2006.285.22:32:28.15#ibcon#about to read 4, iclass 29, count 0 2006.285.22:32:28.15#ibcon#read 4, iclass 29, count 0 2006.285.22:32:28.15#ibcon#about to read 5, iclass 29, count 0 2006.285.22:32:28.15#ibcon#read 5, iclass 29, count 0 2006.285.22:32:28.15#ibcon#about to read 6, iclass 29, count 0 2006.285.22:32:28.15#ibcon#read 6, iclass 29, count 0 2006.285.22:32:28.15#ibcon#end of sib2, iclass 29, count 0 2006.285.22:32:28.15#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:32:28.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:32:28.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.22:32:28.15#ibcon#*before write, iclass 29, count 0 2006.285.22:32:28.15#ibcon#enter sib2, iclass 29, count 0 2006.285.22:32:28.15#ibcon#flushed, iclass 29, count 0 2006.285.22:32:28.15#ibcon#about to write, iclass 29, count 0 2006.285.22:32:28.15#ibcon#wrote, iclass 29, count 0 2006.285.22:32:28.15#ibcon#about to read 3, iclass 29, count 0 2006.285.22:32:28.19#ibcon#read 3, iclass 29, count 0 2006.285.22:32:28.19#ibcon#about to read 4, iclass 29, count 0 2006.285.22:32:28.19#ibcon#read 4, iclass 29, count 0 2006.285.22:32:28.19#ibcon#about to read 5, iclass 29, count 0 2006.285.22:32:28.19#ibcon#read 5, iclass 29, count 0 2006.285.22:32:28.19#ibcon#about to read 6, iclass 29, count 0 2006.285.22:32:28.19#ibcon#read 6, iclass 29, count 0 2006.285.22:32:28.19#ibcon#end of sib2, iclass 29, count 0 2006.285.22:32:28.19#ibcon#*after write, iclass 29, count 0 2006.285.22:32:28.19#ibcon#*before return 0, iclass 29, count 0 2006.285.22:32:28.19#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:32:28.19#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:32:28.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:32:28.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:32:28.19$vck44/vb=4,5 2006.285.22:32:28.19#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.22:32:28.19#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.22:32:28.19#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:28.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:32:28.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:32:28.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:32:28.25#ibcon#enter wrdev, iclass 31, count 2 2006.285.22:32:28.25#ibcon#first serial, iclass 31, count 2 2006.285.22:32:28.25#ibcon#enter sib2, iclass 31, count 2 2006.285.22:32:28.25#ibcon#flushed, iclass 31, count 2 2006.285.22:32:28.25#ibcon#about to write, iclass 31, count 2 2006.285.22:32:28.25#ibcon#wrote, iclass 31, count 2 2006.285.22:32:28.25#ibcon#about to read 3, iclass 31, count 2 2006.285.22:32:28.27#ibcon#read 3, iclass 31, count 2 2006.285.22:32:28.27#ibcon#about to read 4, iclass 31, count 2 2006.285.22:32:28.27#ibcon#read 4, iclass 31, count 2 2006.285.22:32:28.27#ibcon#about to read 5, iclass 31, count 2 2006.285.22:32:28.27#ibcon#read 5, iclass 31, count 2 2006.285.22:32:28.27#ibcon#about to read 6, iclass 31, count 2 2006.285.22:32:28.27#ibcon#read 6, iclass 31, count 2 2006.285.22:32:28.27#ibcon#end of sib2, iclass 31, count 2 2006.285.22:32:28.27#ibcon#*mode == 0, iclass 31, count 2 2006.285.22:32:28.27#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.22:32:28.27#ibcon#[27=AT04-05\r\n] 2006.285.22:32:28.27#ibcon#*before write, iclass 31, count 2 2006.285.22:32:28.27#ibcon#enter sib2, iclass 31, count 2 2006.285.22:32:28.27#ibcon#flushed, iclass 31, count 2 2006.285.22:32:28.27#ibcon#about to write, iclass 31, count 2 2006.285.22:32:28.27#ibcon#wrote, iclass 31, count 2 2006.285.22:32:28.27#ibcon#about to read 3, iclass 31, count 2 2006.285.22:32:28.30#ibcon#read 3, iclass 31, count 2 2006.285.22:32:28.30#ibcon#about to read 4, iclass 31, count 2 2006.285.22:32:28.30#ibcon#read 4, iclass 31, count 2 2006.285.22:32:28.30#ibcon#about to read 5, iclass 31, count 2 2006.285.22:32:28.30#ibcon#read 5, iclass 31, count 2 2006.285.22:32:28.30#ibcon#about to read 6, iclass 31, count 2 2006.285.22:32:28.30#ibcon#read 6, iclass 31, count 2 2006.285.22:32:28.30#ibcon#end of sib2, iclass 31, count 2 2006.285.22:32:28.30#ibcon#*after write, iclass 31, count 2 2006.285.22:32:28.30#ibcon#*before return 0, iclass 31, count 2 2006.285.22:32:28.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:32:28.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:32:28.30#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.22:32:28.30#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:28.30#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:32:28.42#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:32:28.42#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:32:28.42#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:32:28.42#ibcon#first serial, iclass 31, count 0 2006.285.22:32:28.42#ibcon#enter sib2, iclass 31, count 0 2006.285.22:32:28.42#ibcon#flushed, iclass 31, count 0 2006.285.22:32:28.42#ibcon#about to write, iclass 31, count 0 2006.285.22:32:28.42#ibcon#wrote, iclass 31, count 0 2006.285.22:32:28.42#ibcon#about to read 3, iclass 31, count 0 2006.285.22:32:28.44#ibcon#read 3, iclass 31, count 0 2006.285.22:32:28.44#ibcon#about to read 4, iclass 31, count 0 2006.285.22:32:28.44#ibcon#read 4, iclass 31, count 0 2006.285.22:32:28.44#ibcon#about to read 5, iclass 31, count 0 2006.285.22:32:28.44#ibcon#read 5, iclass 31, count 0 2006.285.22:32:28.44#ibcon#about to read 6, iclass 31, count 0 2006.285.22:32:28.44#ibcon#read 6, iclass 31, count 0 2006.285.22:32:28.44#ibcon#end of sib2, iclass 31, count 0 2006.285.22:32:28.44#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:32:28.44#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:32:28.44#ibcon#[27=USB\r\n] 2006.285.22:32:28.44#ibcon#*before write, iclass 31, count 0 2006.285.22:32:28.44#ibcon#enter sib2, iclass 31, count 0 2006.285.22:32:28.44#ibcon#flushed, iclass 31, count 0 2006.285.22:32:28.44#ibcon#about to write, iclass 31, count 0 2006.285.22:32:28.44#ibcon#wrote, iclass 31, count 0 2006.285.22:32:28.44#ibcon#about to read 3, iclass 31, count 0 2006.285.22:32:28.47#ibcon#read 3, iclass 31, count 0 2006.285.22:32:28.47#ibcon#about to read 4, iclass 31, count 0 2006.285.22:32:28.47#ibcon#read 4, iclass 31, count 0 2006.285.22:32:28.47#ibcon#about to read 5, iclass 31, count 0 2006.285.22:32:28.47#ibcon#read 5, iclass 31, count 0 2006.285.22:32:28.47#ibcon#about to read 6, iclass 31, count 0 2006.285.22:32:28.47#ibcon#read 6, iclass 31, count 0 2006.285.22:32:28.47#ibcon#end of sib2, iclass 31, count 0 2006.285.22:32:28.47#ibcon#*after write, iclass 31, count 0 2006.285.22:32:28.47#ibcon#*before return 0, iclass 31, count 0 2006.285.22:32:28.47#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:32:28.47#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:32:28.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:32:28.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:32:28.47$vck44/vblo=5,709.99 2006.285.22:32:28.47#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.22:32:28.47#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.22:32:28.47#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:28.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:32:28.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:32:28.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:32:28.47#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:32:28.47#ibcon#first serial, iclass 33, count 0 2006.285.22:32:28.47#ibcon#enter sib2, iclass 33, count 0 2006.285.22:32:28.47#ibcon#flushed, iclass 33, count 0 2006.285.22:32:28.47#ibcon#about to write, iclass 33, count 0 2006.285.22:32:28.47#ibcon#wrote, iclass 33, count 0 2006.285.22:32:28.47#ibcon#about to read 3, iclass 33, count 0 2006.285.22:32:28.49#ibcon#read 3, iclass 33, count 0 2006.285.22:32:28.49#ibcon#about to read 4, iclass 33, count 0 2006.285.22:32:28.49#ibcon#read 4, iclass 33, count 0 2006.285.22:32:28.49#ibcon#about to read 5, iclass 33, count 0 2006.285.22:32:28.49#ibcon#read 5, iclass 33, count 0 2006.285.22:32:28.49#ibcon#about to read 6, iclass 33, count 0 2006.285.22:32:28.49#ibcon#read 6, iclass 33, count 0 2006.285.22:32:28.49#ibcon#end of sib2, iclass 33, count 0 2006.285.22:32:28.49#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:32:28.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:32:28.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.22:32:28.49#ibcon#*before write, iclass 33, count 0 2006.285.22:32:28.49#ibcon#enter sib2, iclass 33, count 0 2006.285.22:32:28.49#ibcon#flushed, iclass 33, count 0 2006.285.22:32:28.49#ibcon#about to write, iclass 33, count 0 2006.285.22:32:28.49#ibcon#wrote, iclass 33, count 0 2006.285.22:32:28.49#ibcon#about to read 3, iclass 33, count 0 2006.285.22:32:28.53#ibcon#read 3, iclass 33, count 0 2006.285.22:32:28.53#ibcon#about to read 4, iclass 33, count 0 2006.285.22:32:28.53#ibcon#read 4, iclass 33, count 0 2006.285.22:32:28.53#ibcon#about to read 5, iclass 33, count 0 2006.285.22:32:28.53#ibcon#read 5, iclass 33, count 0 2006.285.22:32:28.53#ibcon#about to read 6, iclass 33, count 0 2006.285.22:32:28.53#ibcon#read 6, iclass 33, count 0 2006.285.22:32:28.53#ibcon#end of sib2, iclass 33, count 0 2006.285.22:32:28.53#ibcon#*after write, iclass 33, count 0 2006.285.22:32:28.53#ibcon#*before return 0, iclass 33, count 0 2006.285.22:32:28.53#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:32:28.53#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:32:28.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:32:28.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:32:28.53$vck44/vb=5,4 2006.285.22:32:28.53#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.22:32:28.53#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.22:32:28.53#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:28.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:32:28.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:32:28.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:32:28.59#ibcon#enter wrdev, iclass 35, count 2 2006.285.22:32:28.59#ibcon#first serial, iclass 35, count 2 2006.285.22:32:28.59#ibcon#enter sib2, iclass 35, count 2 2006.285.22:32:28.59#ibcon#flushed, iclass 35, count 2 2006.285.22:32:28.59#ibcon#about to write, iclass 35, count 2 2006.285.22:32:28.59#ibcon#wrote, iclass 35, count 2 2006.285.22:32:28.59#ibcon#about to read 3, iclass 35, count 2 2006.285.22:32:28.61#ibcon#read 3, iclass 35, count 2 2006.285.22:32:28.61#ibcon#about to read 4, iclass 35, count 2 2006.285.22:32:28.61#ibcon#read 4, iclass 35, count 2 2006.285.22:32:28.61#ibcon#about to read 5, iclass 35, count 2 2006.285.22:32:28.61#ibcon#read 5, iclass 35, count 2 2006.285.22:32:28.61#ibcon#about to read 6, iclass 35, count 2 2006.285.22:32:28.61#ibcon#read 6, iclass 35, count 2 2006.285.22:32:28.61#ibcon#end of sib2, iclass 35, count 2 2006.285.22:32:28.61#ibcon#*mode == 0, iclass 35, count 2 2006.285.22:32:28.61#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.22:32:28.61#ibcon#[27=AT05-04\r\n] 2006.285.22:32:28.61#ibcon#*before write, iclass 35, count 2 2006.285.22:32:28.61#ibcon#enter sib2, iclass 35, count 2 2006.285.22:32:28.61#ibcon#flushed, iclass 35, count 2 2006.285.22:32:28.61#ibcon#about to write, iclass 35, count 2 2006.285.22:32:28.61#ibcon#wrote, iclass 35, count 2 2006.285.22:32:28.61#ibcon#about to read 3, iclass 35, count 2 2006.285.22:32:28.64#ibcon#read 3, iclass 35, count 2 2006.285.22:32:28.64#ibcon#about to read 4, iclass 35, count 2 2006.285.22:32:28.64#ibcon#read 4, iclass 35, count 2 2006.285.22:32:28.64#ibcon#about to read 5, iclass 35, count 2 2006.285.22:32:28.64#ibcon#read 5, iclass 35, count 2 2006.285.22:32:28.64#ibcon#about to read 6, iclass 35, count 2 2006.285.22:32:28.64#ibcon#read 6, iclass 35, count 2 2006.285.22:32:28.64#ibcon#end of sib2, iclass 35, count 2 2006.285.22:32:28.64#ibcon#*after write, iclass 35, count 2 2006.285.22:32:28.64#ibcon#*before return 0, iclass 35, count 2 2006.285.22:32:28.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:32:28.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:32:28.64#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.22:32:28.64#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:28.64#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:32:28.76#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:32:28.76#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:32:28.76#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:32:28.76#ibcon#first serial, iclass 35, count 0 2006.285.22:32:28.76#ibcon#enter sib2, iclass 35, count 0 2006.285.22:32:28.76#ibcon#flushed, iclass 35, count 0 2006.285.22:32:28.76#ibcon#about to write, iclass 35, count 0 2006.285.22:32:28.76#ibcon#wrote, iclass 35, count 0 2006.285.22:32:28.76#ibcon#about to read 3, iclass 35, count 0 2006.285.22:32:28.78#ibcon#read 3, iclass 35, count 0 2006.285.22:32:28.78#ibcon#about to read 4, iclass 35, count 0 2006.285.22:32:28.78#ibcon#read 4, iclass 35, count 0 2006.285.22:32:28.78#ibcon#about to read 5, iclass 35, count 0 2006.285.22:32:28.78#ibcon#read 5, iclass 35, count 0 2006.285.22:32:28.78#ibcon#about to read 6, iclass 35, count 0 2006.285.22:32:28.78#ibcon#read 6, iclass 35, count 0 2006.285.22:32:28.78#ibcon#end of sib2, iclass 35, count 0 2006.285.22:32:28.78#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:32:28.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:32:28.78#ibcon#[27=USB\r\n] 2006.285.22:32:28.78#ibcon#*before write, iclass 35, count 0 2006.285.22:32:28.78#ibcon#enter sib2, iclass 35, count 0 2006.285.22:32:28.78#ibcon#flushed, iclass 35, count 0 2006.285.22:32:28.78#ibcon#about to write, iclass 35, count 0 2006.285.22:32:28.78#ibcon#wrote, iclass 35, count 0 2006.285.22:32:28.78#ibcon#about to read 3, iclass 35, count 0 2006.285.22:32:28.81#ibcon#read 3, iclass 35, count 0 2006.285.22:32:28.81#ibcon#about to read 4, iclass 35, count 0 2006.285.22:32:28.81#ibcon#read 4, iclass 35, count 0 2006.285.22:32:28.81#ibcon#about to read 5, iclass 35, count 0 2006.285.22:32:28.81#ibcon#read 5, iclass 35, count 0 2006.285.22:32:28.81#ibcon#about to read 6, iclass 35, count 0 2006.285.22:32:28.81#ibcon#read 6, iclass 35, count 0 2006.285.22:32:28.81#ibcon#end of sib2, iclass 35, count 0 2006.285.22:32:28.81#ibcon#*after write, iclass 35, count 0 2006.285.22:32:28.81#ibcon#*before return 0, iclass 35, count 0 2006.285.22:32:28.81#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:32:28.81#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:32:28.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:32:28.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:32:28.81$vck44/vblo=6,719.99 2006.285.22:32:28.81#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.22:32:28.81#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.22:32:28.81#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:28.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:32:28.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:32:28.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:32:28.81#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:32:28.81#ibcon#first serial, iclass 37, count 0 2006.285.22:32:28.81#ibcon#enter sib2, iclass 37, count 0 2006.285.22:32:28.81#ibcon#flushed, iclass 37, count 0 2006.285.22:32:28.81#ibcon#about to write, iclass 37, count 0 2006.285.22:32:28.81#ibcon#wrote, iclass 37, count 0 2006.285.22:32:28.81#ibcon#about to read 3, iclass 37, count 0 2006.285.22:32:28.83#ibcon#read 3, iclass 37, count 0 2006.285.22:32:28.83#ibcon#about to read 4, iclass 37, count 0 2006.285.22:32:28.83#ibcon#read 4, iclass 37, count 0 2006.285.22:32:28.83#ibcon#about to read 5, iclass 37, count 0 2006.285.22:32:28.83#ibcon#read 5, iclass 37, count 0 2006.285.22:32:28.83#ibcon#about to read 6, iclass 37, count 0 2006.285.22:32:28.83#ibcon#read 6, iclass 37, count 0 2006.285.22:32:28.83#ibcon#end of sib2, iclass 37, count 0 2006.285.22:32:28.83#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:32:28.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:32:28.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.22:32:28.83#ibcon#*before write, iclass 37, count 0 2006.285.22:32:28.83#ibcon#enter sib2, iclass 37, count 0 2006.285.22:32:28.83#ibcon#flushed, iclass 37, count 0 2006.285.22:32:28.83#ibcon#about to write, iclass 37, count 0 2006.285.22:32:28.83#ibcon#wrote, iclass 37, count 0 2006.285.22:32:28.83#ibcon#about to read 3, iclass 37, count 0 2006.285.22:32:28.87#ibcon#read 3, iclass 37, count 0 2006.285.22:32:28.87#ibcon#about to read 4, iclass 37, count 0 2006.285.22:32:28.87#ibcon#read 4, iclass 37, count 0 2006.285.22:32:28.87#ibcon#about to read 5, iclass 37, count 0 2006.285.22:32:28.87#ibcon#read 5, iclass 37, count 0 2006.285.22:32:28.87#ibcon#about to read 6, iclass 37, count 0 2006.285.22:32:28.87#ibcon#read 6, iclass 37, count 0 2006.285.22:32:28.87#ibcon#end of sib2, iclass 37, count 0 2006.285.22:32:28.87#ibcon#*after write, iclass 37, count 0 2006.285.22:32:28.87#ibcon#*before return 0, iclass 37, count 0 2006.285.22:32:28.87#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:32:28.87#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:32:28.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:32:28.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:32:28.87$vck44/vb=6,3 2006.285.22:32:28.87#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.22:32:28.87#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.22:32:28.87#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:28.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:32:28.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:32:28.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:32:28.93#ibcon#enter wrdev, iclass 39, count 2 2006.285.22:32:28.93#ibcon#first serial, iclass 39, count 2 2006.285.22:32:28.93#ibcon#enter sib2, iclass 39, count 2 2006.285.22:32:28.93#ibcon#flushed, iclass 39, count 2 2006.285.22:32:28.93#ibcon#about to write, iclass 39, count 2 2006.285.22:32:28.93#ibcon#wrote, iclass 39, count 2 2006.285.22:32:28.93#ibcon#about to read 3, iclass 39, count 2 2006.285.22:32:28.95#ibcon#read 3, iclass 39, count 2 2006.285.22:32:28.95#ibcon#about to read 4, iclass 39, count 2 2006.285.22:32:28.95#ibcon#read 4, iclass 39, count 2 2006.285.22:32:28.95#ibcon#about to read 5, iclass 39, count 2 2006.285.22:32:28.95#ibcon#read 5, iclass 39, count 2 2006.285.22:32:28.95#ibcon#about to read 6, iclass 39, count 2 2006.285.22:32:28.95#ibcon#read 6, iclass 39, count 2 2006.285.22:32:28.95#ibcon#end of sib2, iclass 39, count 2 2006.285.22:32:28.95#ibcon#*mode == 0, iclass 39, count 2 2006.285.22:32:28.95#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.22:32:28.95#ibcon#[27=AT06-03\r\n] 2006.285.22:32:28.95#ibcon#*before write, iclass 39, count 2 2006.285.22:32:28.95#ibcon#enter sib2, iclass 39, count 2 2006.285.22:32:28.95#ibcon#flushed, iclass 39, count 2 2006.285.22:32:28.95#ibcon#about to write, iclass 39, count 2 2006.285.22:32:28.95#ibcon#wrote, iclass 39, count 2 2006.285.22:32:28.95#ibcon#about to read 3, iclass 39, count 2 2006.285.22:32:28.98#ibcon#read 3, iclass 39, count 2 2006.285.22:32:28.98#ibcon#about to read 4, iclass 39, count 2 2006.285.22:32:28.98#ibcon#read 4, iclass 39, count 2 2006.285.22:32:28.98#ibcon#about to read 5, iclass 39, count 2 2006.285.22:32:28.98#ibcon#read 5, iclass 39, count 2 2006.285.22:32:28.98#ibcon#about to read 6, iclass 39, count 2 2006.285.22:32:28.98#ibcon#read 6, iclass 39, count 2 2006.285.22:32:28.98#ibcon#end of sib2, iclass 39, count 2 2006.285.22:32:28.98#ibcon#*after write, iclass 39, count 2 2006.285.22:32:28.98#ibcon#*before return 0, iclass 39, count 2 2006.285.22:32:28.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:32:28.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:32:28.98#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.22:32:28.98#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:28.98#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:32:29.10#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:32:29.10#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:32:29.10#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:32:29.10#ibcon#first serial, iclass 39, count 0 2006.285.22:32:29.10#ibcon#enter sib2, iclass 39, count 0 2006.285.22:32:29.10#ibcon#flushed, iclass 39, count 0 2006.285.22:32:29.10#ibcon#about to write, iclass 39, count 0 2006.285.22:32:29.10#ibcon#wrote, iclass 39, count 0 2006.285.22:32:29.10#ibcon#about to read 3, iclass 39, count 0 2006.285.22:32:29.12#ibcon#read 3, iclass 39, count 0 2006.285.22:32:29.12#ibcon#about to read 4, iclass 39, count 0 2006.285.22:32:29.12#ibcon#read 4, iclass 39, count 0 2006.285.22:32:29.12#ibcon#about to read 5, iclass 39, count 0 2006.285.22:32:29.12#ibcon#read 5, iclass 39, count 0 2006.285.22:32:29.12#ibcon#about to read 6, iclass 39, count 0 2006.285.22:32:29.12#ibcon#read 6, iclass 39, count 0 2006.285.22:32:29.12#ibcon#end of sib2, iclass 39, count 0 2006.285.22:32:29.12#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:32:29.12#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:32:29.12#ibcon#[27=USB\r\n] 2006.285.22:32:29.12#ibcon#*before write, iclass 39, count 0 2006.285.22:32:29.12#ibcon#enter sib2, iclass 39, count 0 2006.285.22:32:29.12#ibcon#flushed, iclass 39, count 0 2006.285.22:32:29.12#ibcon#about to write, iclass 39, count 0 2006.285.22:32:29.12#ibcon#wrote, iclass 39, count 0 2006.285.22:32:29.12#ibcon#about to read 3, iclass 39, count 0 2006.285.22:32:29.15#ibcon#read 3, iclass 39, count 0 2006.285.22:32:29.15#ibcon#about to read 4, iclass 39, count 0 2006.285.22:32:29.15#ibcon#read 4, iclass 39, count 0 2006.285.22:32:29.15#ibcon#about to read 5, iclass 39, count 0 2006.285.22:32:29.15#ibcon#read 5, iclass 39, count 0 2006.285.22:32:29.15#ibcon#about to read 6, iclass 39, count 0 2006.285.22:32:29.15#ibcon#read 6, iclass 39, count 0 2006.285.22:32:29.15#ibcon#end of sib2, iclass 39, count 0 2006.285.22:32:29.15#ibcon#*after write, iclass 39, count 0 2006.285.22:32:29.15#ibcon#*before return 0, iclass 39, count 0 2006.285.22:32:29.15#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:32:29.15#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:32:29.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:32:29.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:32:29.15$vck44/vblo=7,734.99 2006.285.22:32:29.15#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.22:32:29.15#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.22:32:29.15#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:29.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:32:29.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:32:29.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:32:29.15#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:32:29.15#ibcon#first serial, iclass 3, count 0 2006.285.22:32:29.15#ibcon#enter sib2, iclass 3, count 0 2006.285.22:32:29.15#ibcon#flushed, iclass 3, count 0 2006.285.22:32:29.15#ibcon#about to write, iclass 3, count 0 2006.285.22:32:29.15#ibcon#wrote, iclass 3, count 0 2006.285.22:32:29.15#ibcon#about to read 3, iclass 3, count 0 2006.285.22:32:29.17#ibcon#read 3, iclass 3, count 0 2006.285.22:32:29.17#ibcon#about to read 4, iclass 3, count 0 2006.285.22:32:29.17#ibcon#read 4, iclass 3, count 0 2006.285.22:32:29.17#ibcon#about to read 5, iclass 3, count 0 2006.285.22:32:29.17#ibcon#read 5, iclass 3, count 0 2006.285.22:32:29.17#ibcon#about to read 6, iclass 3, count 0 2006.285.22:32:29.17#ibcon#read 6, iclass 3, count 0 2006.285.22:32:29.17#ibcon#end of sib2, iclass 3, count 0 2006.285.22:32:29.17#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:32:29.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:32:29.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.22:32:29.17#ibcon#*before write, iclass 3, count 0 2006.285.22:32:29.17#ibcon#enter sib2, iclass 3, count 0 2006.285.22:32:29.17#ibcon#flushed, iclass 3, count 0 2006.285.22:32:29.17#ibcon#about to write, iclass 3, count 0 2006.285.22:32:29.17#ibcon#wrote, iclass 3, count 0 2006.285.22:32:29.17#ibcon#about to read 3, iclass 3, count 0 2006.285.22:32:29.21#ibcon#read 3, iclass 3, count 0 2006.285.22:32:29.21#ibcon#about to read 4, iclass 3, count 0 2006.285.22:32:29.21#ibcon#read 4, iclass 3, count 0 2006.285.22:32:29.21#ibcon#about to read 5, iclass 3, count 0 2006.285.22:32:29.21#ibcon#read 5, iclass 3, count 0 2006.285.22:32:29.21#ibcon#about to read 6, iclass 3, count 0 2006.285.22:32:29.21#ibcon#read 6, iclass 3, count 0 2006.285.22:32:29.21#ibcon#end of sib2, iclass 3, count 0 2006.285.22:32:29.21#ibcon#*after write, iclass 3, count 0 2006.285.22:32:29.21#ibcon#*before return 0, iclass 3, count 0 2006.285.22:32:29.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:32:29.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:32:29.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:32:29.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:32:29.21$vck44/vb=7,4 2006.285.22:32:29.21#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.22:32:29.21#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.22:32:29.21#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:29.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:32:29.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:32:29.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:32:29.27#ibcon#enter wrdev, iclass 5, count 2 2006.285.22:32:29.27#ibcon#first serial, iclass 5, count 2 2006.285.22:32:29.27#ibcon#enter sib2, iclass 5, count 2 2006.285.22:32:29.27#ibcon#flushed, iclass 5, count 2 2006.285.22:32:29.27#ibcon#about to write, iclass 5, count 2 2006.285.22:32:29.27#ibcon#wrote, iclass 5, count 2 2006.285.22:32:29.27#ibcon#about to read 3, iclass 5, count 2 2006.285.22:32:29.29#ibcon#read 3, iclass 5, count 2 2006.285.22:32:29.29#ibcon#about to read 4, iclass 5, count 2 2006.285.22:32:29.29#ibcon#read 4, iclass 5, count 2 2006.285.22:32:29.29#ibcon#about to read 5, iclass 5, count 2 2006.285.22:32:29.29#ibcon#read 5, iclass 5, count 2 2006.285.22:32:29.29#ibcon#about to read 6, iclass 5, count 2 2006.285.22:32:29.29#ibcon#read 6, iclass 5, count 2 2006.285.22:32:29.29#ibcon#end of sib2, iclass 5, count 2 2006.285.22:32:29.29#ibcon#*mode == 0, iclass 5, count 2 2006.285.22:32:29.29#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.22:32:29.29#ibcon#[27=AT07-04\r\n] 2006.285.22:32:29.29#ibcon#*before write, iclass 5, count 2 2006.285.22:32:29.29#ibcon#enter sib2, iclass 5, count 2 2006.285.22:32:29.29#ibcon#flushed, iclass 5, count 2 2006.285.22:32:29.29#ibcon#about to write, iclass 5, count 2 2006.285.22:32:29.29#ibcon#wrote, iclass 5, count 2 2006.285.22:32:29.29#ibcon#about to read 3, iclass 5, count 2 2006.285.22:32:29.32#ibcon#read 3, iclass 5, count 2 2006.285.22:32:29.32#ibcon#about to read 4, iclass 5, count 2 2006.285.22:32:29.32#ibcon#read 4, iclass 5, count 2 2006.285.22:32:29.32#ibcon#about to read 5, iclass 5, count 2 2006.285.22:32:29.32#ibcon#read 5, iclass 5, count 2 2006.285.22:32:29.32#ibcon#about to read 6, iclass 5, count 2 2006.285.22:32:29.32#ibcon#read 6, iclass 5, count 2 2006.285.22:32:29.32#ibcon#end of sib2, iclass 5, count 2 2006.285.22:32:29.32#ibcon#*after write, iclass 5, count 2 2006.285.22:32:29.32#ibcon#*before return 0, iclass 5, count 2 2006.285.22:32:29.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:32:29.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:32:29.32#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.22:32:29.32#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:29.32#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:32:29.44#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:32:29.44#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:32:29.44#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:32:29.44#ibcon#first serial, iclass 5, count 0 2006.285.22:32:29.44#ibcon#enter sib2, iclass 5, count 0 2006.285.22:32:29.44#ibcon#flushed, iclass 5, count 0 2006.285.22:32:29.44#ibcon#about to write, iclass 5, count 0 2006.285.22:32:29.44#ibcon#wrote, iclass 5, count 0 2006.285.22:32:29.44#ibcon#about to read 3, iclass 5, count 0 2006.285.22:32:29.46#ibcon#read 3, iclass 5, count 0 2006.285.22:32:29.46#ibcon#about to read 4, iclass 5, count 0 2006.285.22:32:29.46#ibcon#read 4, iclass 5, count 0 2006.285.22:32:29.46#ibcon#about to read 5, iclass 5, count 0 2006.285.22:32:29.46#ibcon#read 5, iclass 5, count 0 2006.285.22:32:29.46#ibcon#about to read 6, iclass 5, count 0 2006.285.22:32:29.46#ibcon#read 6, iclass 5, count 0 2006.285.22:32:29.46#ibcon#end of sib2, iclass 5, count 0 2006.285.22:32:29.46#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:32:29.46#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:32:29.46#ibcon#[27=USB\r\n] 2006.285.22:32:29.46#ibcon#*before write, iclass 5, count 0 2006.285.22:32:29.46#ibcon#enter sib2, iclass 5, count 0 2006.285.22:32:29.46#ibcon#flushed, iclass 5, count 0 2006.285.22:32:29.46#ibcon#about to write, iclass 5, count 0 2006.285.22:32:29.46#ibcon#wrote, iclass 5, count 0 2006.285.22:32:29.46#ibcon#about to read 3, iclass 5, count 0 2006.285.22:32:29.49#ibcon#read 3, iclass 5, count 0 2006.285.22:32:29.49#ibcon#about to read 4, iclass 5, count 0 2006.285.22:32:29.49#ibcon#read 4, iclass 5, count 0 2006.285.22:32:29.49#ibcon#about to read 5, iclass 5, count 0 2006.285.22:32:29.49#ibcon#read 5, iclass 5, count 0 2006.285.22:32:29.49#ibcon#about to read 6, iclass 5, count 0 2006.285.22:32:29.49#ibcon#read 6, iclass 5, count 0 2006.285.22:32:29.49#ibcon#end of sib2, iclass 5, count 0 2006.285.22:32:29.49#ibcon#*after write, iclass 5, count 0 2006.285.22:32:29.49#ibcon#*before return 0, iclass 5, count 0 2006.285.22:32:29.49#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:32:29.49#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:32:29.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:32:29.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:32:29.49$vck44/vblo=8,744.99 2006.285.22:32:29.49#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.22:32:29.49#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.22:32:29.49#ibcon#ireg 17 cls_cnt 0 2006.285.22:32:29.49#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:32:29.49#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:32:29.49#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:32:29.49#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:32:29.49#ibcon#first serial, iclass 7, count 0 2006.285.22:32:29.49#ibcon#enter sib2, iclass 7, count 0 2006.285.22:32:29.49#ibcon#flushed, iclass 7, count 0 2006.285.22:32:29.49#ibcon#about to write, iclass 7, count 0 2006.285.22:32:29.49#ibcon#wrote, iclass 7, count 0 2006.285.22:32:29.49#ibcon#about to read 3, iclass 7, count 0 2006.285.22:32:29.51#ibcon#read 3, iclass 7, count 0 2006.285.22:32:29.51#ibcon#about to read 4, iclass 7, count 0 2006.285.22:32:29.51#ibcon#read 4, iclass 7, count 0 2006.285.22:32:29.51#ibcon#about to read 5, iclass 7, count 0 2006.285.22:32:29.51#ibcon#read 5, iclass 7, count 0 2006.285.22:32:29.51#ibcon#about to read 6, iclass 7, count 0 2006.285.22:32:29.51#ibcon#read 6, iclass 7, count 0 2006.285.22:32:29.51#ibcon#end of sib2, iclass 7, count 0 2006.285.22:32:29.51#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:32:29.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:32:29.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.22:32:29.51#ibcon#*before write, iclass 7, count 0 2006.285.22:32:29.51#ibcon#enter sib2, iclass 7, count 0 2006.285.22:32:29.51#ibcon#flushed, iclass 7, count 0 2006.285.22:32:29.51#ibcon#about to write, iclass 7, count 0 2006.285.22:32:29.51#ibcon#wrote, iclass 7, count 0 2006.285.22:32:29.51#ibcon#about to read 3, iclass 7, count 0 2006.285.22:32:29.55#ibcon#read 3, iclass 7, count 0 2006.285.22:32:29.55#ibcon#about to read 4, iclass 7, count 0 2006.285.22:32:29.55#ibcon#read 4, iclass 7, count 0 2006.285.22:32:29.55#ibcon#about to read 5, iclass 7, count 0 2006.285.22:32:29.55#ibcon#read 5, iclass 7, count 0 2006.285.22:32:29.55#ibcon#about to read 6, iclass 7, count 0 2006.285.22:32:29.55#ibcon#read 6, iclass 7, count 0 2006.285.22:32:29.55#ibcon#end of sib2, iclass 7, count 0 2006.285.22:32:29.55#ibcon#*after write, iclass 7, count 0 2006.285.22:32:29.55#ibcon#*before return 0, iclass 7, count 0 2006.285.22:32:29.55#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:32:29.55#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:32:29.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:32:29.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:32:29.55$vck44/vb=8,4 2006.285.22:32:29.55#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.22:32:29.55#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.22:32:29.55#ibcon#ireg 11 cls_cnt 2 2006.285.22:32:29.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:32:29.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:32:29.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:32:29.61#ibcon#enter wrdev, iclass 11, count 2 2006.285.22:32:29.61#ibcon#first serial, iclass 11, count 2 2006.285.22:32:29.61#ibcon#enter sib2, iclass 11, count 2 2006.285.22:32:29.61#ibcon#flushed, iclass 11, count 2 2006.285.22:32:29.61#ibcon#about to write, iclass 11, count 2 2006.285.22:32:29.61#ibcon#wrote, iclass 11, count 2 2006.285.22:32:29.61#ibcon#about to read 3, iclass 11, count 2 2006.285.22:32:29.63#ibcon#read 3, iclass 11, count 2 2006.285.22:32:29.63#ibcon#about to read 4, iclass 11, count 2 2006.285.22:32:29.63#ibcon#read 4, iclass 11, count 2 2006.285.22:32:29.63#ibcon#about to read 5, iclass 11, count 2 2006.285.22:32:29.63#ibcon#read 5, iclass 11, count 2 2006.285.22:32:29.63#ibcon#about to read 6, iclass 11, count 2 2006.285.22:32:29.63#ibcon#read 6, iclass 11, count 2 2006.285.22:32:29.63#ibcon#end of sib2, iclass 11, count 2 2006.285.22:32:29.63#ibcon#*mode == 0, iclass 11, count 2 2006.285.22:32:29.63#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.22:32:29.63#ibcon#[27=AT08-04\r\n] 2006.285.22:32:29.63#ibcon#*before write, iclass 11, count 2 2006.285.22:32:29.63#ibcon#enter sib2, iclass 11, count 2 2006.285.22:32:29.63#ibcon#flushed, iclass 11, count 2 2006.285.22:32:29.63#ibcon#about to write, iclass 11, count 2 2006.285.22:32:29.63#ibcon#wrote, iclass 11, count 2 2006.285.22:32:29.63#ibcon#about to read 3, iclass 11, count 2 2006.285.22:32:29.66#ibcon#read 3, iclass 11, count 2 2006.285.22:32:29.66#ibcon#about to read 4, iclass 11, count 2 2006.285.22:32:29.66#ibcon#read 4, iclass 11, count 2 2006.285.22:32:29.66#ibcon#about to read 5, iclass 11, count 2 2006.285.22:32:29.66#ibcon#read 5, iclass 11, count 2 2006.285.22:32:29.66#ibcon#about to read 6, iclass 11, count 2 2006.285.22:32:29.66#ibcon#read 6, iclass 11, count 2 2006.285.22:32:29.66#ibcon#end of sib2, iclass 11, count 2 2006.285.22:32:29.66#ibcon#*after write, iclass 11, count 2 2006.285.22:32:29.66#ibcon#*before return 0, iclass 11, count 2 2006.285.22:32:29.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:32:29.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:32:29.66#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.22:32:29.66#ibcon#ireg 7 cls_cnt 0 2006.285.22:32:29.66#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:32:29.78#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:32:29.78#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:32:29.78#ibcon#enter wrdev, iclass 11, count 0 2006.285.22:32:29.78#ibcon#first serial, iclass 11, count 0 2006.285.22:32:29.78#ibcon#enter sib2, iclass 11, count 0 2006.285.22:32:29.78#ibcon#flushed, iclass 11, count 0 2006.285.22:32:29.78#ibcon#about to write, iclass 11, count 0 2006.285.22:32:29.78#ibcon#wrote, iclass 11, count 0 2006.285.22:32:29.78#ibcon#about to read 3, iclass 11, count 0 2006.285.22:32:29.80#ibcon#read 3, iclass 11, count 0 2006.285.22:32:29.80#ibcon#about to read 4, iclass 11, count 0 2006.285.22:32:29.80#ibcon#read 4, iclass 11, count 0 2006.285.22:32:29.80#ibcon#about to read 5, iclass 11, count 0 2006.285.22:32:29.80#ibcon#read 5, iclass 11, count 0 2006.285.22:32:29.80#ibcon#about to read 6, iclass 11, count 0 2006.285.22:32:29.80#ibcon#read 6, iclass 11, count 0 2006.285.22:32:29.80#ibcon#end of sib2, iclass 11, count 0 2006.285.22:32:29.80#ibcon#*mode == 0, iclass 11, count 0 2006.285.22:32:29.80#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.22:32:29.80#ibcon#[27=USB\r\n] 2006.285.22:32:29.80#ibcon#*before write, iclass 11, count 0 2006.285.22:32:29.80#ibcon#enter sib2, iclass 11, count 0 2006.285.22:32:29.80#ibcon#flushed, iclass 11, count 0 2006.285.22:32:29.80#ibcon#about to write, iclass 11, count 0 2006.285.22:32:29.80#ibcon#wrote, iclass 11, count 0 2006.285.22:32:29.80#ibcon#about to read 3, iclass 11, count 0 2006.285.22:32:29.83#ibcon#read 3, iclass 11, count 0 2006.285.22:32:29.83#ibcon#about to read 4, iclass 11, count 0 2006.285.22:32:29.83#ibcon#read 4, iclass 11, count 0 2006.285.22:32:29.83#ibcon#about to read 5, iclass 11, count 0 2006.285.22:32:29.83#ibcon#read 5, iclass 11, count 0 2006.285.22:32:29.83#ibcon#about to read 6, iclass 11, count 0 2006.285.22:32:29.83#ibcon#read 6, iclass 11, count 0 2006.285.22:32:29.83#ibcon#end of sib2, iclass 11, count 0 2006.285.22:32:29.83#ibcon#*after write, iclass 11, count 0 2006.285.22:32:29.83#ibcon#*before return 0, iclass 11, count 0 2006.285.22:32:29.83#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:32:29.83#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:32:29.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.22:32:29.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.22:32:29.83$vck44/vabw=wide 2006.285.22:32:29.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.22:32:29.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.22:32:29.83#ibcon#ireg 8 cls_cnt 0 2006.285.22:32:29.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:32:29.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:32:29.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:32:29.83#ibcon#enter wrdev, iclass 13, count 0 2006.285.22:32:29.83#ibcon#first serial, iclass 13, count 0 2006.285.22:32:29.83#ibcon#enter sib2, iclass 13, count 0 2006.285.22:32:29.83#ibcon#flushed, iclass 13, count 0 2006.285.22:32:29.83#ibcon#about to write, iclass 13, count 0 2006.285.22:32:29.83#ibcon#wrote, iclass 13, count 0 2006.285.22:32:29.83#ibcon#about to read 3, iclass 13, count 0 2006.285.22:32:29.85#ibcon#read 3, iclass 13, count 0 2006.285.22:32:29.85#ibcon#about to read 4, iclass 13, count 0 2006.285.22:32:29.85#ibcon#read 4, iclass 13, count 0 2006.285.22:32:29.85#ibcon#about to read 5, iclass 13, count 0 2006.285.22:32:29.85#ibcon#read 5, iclass 13, count 0 2006.285.22:32:29.85#ibcon#about to read 6, iclass 13, count 0 2006.285.22:32:29.85#ibcon#read 6, iclass 13, count 0 2006.285.22:32:29.85#ibcon#end of sib2, iclass 13, count 0 2006.285.22:32:29.85#ibcon#*mode == 0, iclass 13, count 0 2006.285.22:32:29.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.22:32:29.85#ibcon#[25=BW32\r\n] 2006.285.22:32:29.85#ibcon#*before write, iclass 13, count 0 2006.285.22:32:29.85#ibcon#enter sib2, iclass 13, count 0 2006.285.22:32:29.85#ibcon#flushed, iclass 13, count 0 2006.285.22:32:29.85#ibcon#about to write, iclass 13, count 0 2006.285.22:32:29.85#ibcon#wrote, iclass 13, count 0 2006.285.22:32:29.85#ibcon#about to read 3, iclass 13, count 0 2006.285.22:32:29.88#ibcon#read 3, iclass 13, count 0 2006.285.22:32:29.88#ibcon#about to read 4, iclass 13, count 0 2006.285.22:32:29.88#ibcon#read 4, iclass 13, count 0 2006.285.22:32:29.88#ibcon#about to read 5, iclass 13, count 0 2006.285.22:32:29.88#ibcon#read 5, iclass 13, count 0 2006.285.22:32:29.88#ibcon#about to read 6, iclass 13, count 0 2006.285.22:32:29.88#ibcon#read 6, iclass 13, count 0 2006.285.22:32:29.88#ibcon#end of sib2, iclass 13, count 0 2006.285.22:32:29.88#ibcon#*after write, iclass 13, count 0 2006.285.22:32:29.88#ibcon#*before return 0, iclass 13, count 0 2006.285.22:32:29.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:32:29.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:32:29.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.22:32:29.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.22:32:29.88$vck44/vbbw=wide 2006.285.22:32:29.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.22:32:29.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.22:32:29.88#ibcon#ireg 8 cls_cnt 0 2006.285.22:32:29.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:32:29.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:32:29.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:32:29.95#ibcon#enter wrdev, iclass 15, count 0 2006.285.22:32:29.95#ibcon#first serial, iclass 15, count 0 2006.285.22:32:29.95#ibcon#enter sib2, iclass 15, count 0 2006.285.22:32:29.95#ibcon#flushed, iclass 15, count 0 2006.285.22:32:29.95#ibcon#about to write, iclass 15, count 0 2006.285.22:32:29.95#ibcon#wrote, iclass 15, count 0 2006.285.22:32:29.95#ibcon#about to read 3, iclass 15, count 0 2006.285.22:32:29.97#ibcon#read 3, iclass 15, count 0 2006.285.22:32:29.97#ibcon#about to read 4, iclass 15, count 0 2006.285.22:32:29.97#ibcon#read 4, iclass 15, count 0 2006.285.22:32:29.97#ibcon#about to read 5, iclass 15, count 0 2006.285.22:32:29.97#ibcon#read 5, iclass 15, count 0 2006.285.22:32:29.97#ibcon#about to read 6, iclass 15, count 0 2006.285.22:32:29.97#ibcon#read 6, iclass 15, count 0 2006.285.22:32:29.97#ibcon#end of sib2, iclass 15, count 0 2006.285.22:32:29.97#ibcon#*mode == 0, iclass 15, count 0 2006.285.22:32:29.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.22:32:29.97#ibcon#[27=BW32\r\n] 2006.285.22:32:29.97#ibcon#*before write, iclass 15, count 0 2006.285.22:32:29.97#ibcon#enter sib2, iclass 15, count 0 2006.285.22:32:29.97#ibcon#flushed, iclass 15, count 0 2006.285.22:32:29.97#ibcon#about to write, iclass 15, count 0 2006.285.22:32:29.97#ibcon#wrote, iclass 15, count 0 2006.285.22:32:29.97#ibcon#about to read 3, iclass 15, count 0 2006.285.22:32:30.00#ibcon#read 3, iclass 15, count 0 2006.285.22:32:30.00#ibcon#about to read 4, iclass 15, count 0 2006.285.22:32:30.00#ibcon#read 4, iclass 15, count 0 2006.285.22:32:30.00#ibcon#about to read 5, iclass 15, count 0 2006.285.22:32:30.00#ibcon#read 5, iclass 15, count 0 2006.285.22:32:30.00#ibcon#about to read 6, iclass 15, count 0 2006.285.22:32:30.00#ibcon#read 6, iclass 15, count 0 2006.285.22:32:30.00#ibcon#end of sib2, iclass 15, count 0 2006.285.22:32:30.00#ibcon#*after write, iclass 15, count 0 2006.285.22:32:30.00#ibcon#*before return 0, iclass 15, count 0 2006.285.22:32:30.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:32:30.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:32:30.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.22:32:30.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.22:32:30.00$setupk4/ifdk4 2006.285.22:32:30.00$ifdk4/lo= 2006.285.22:32:30.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.22:32:30.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.22:32:30.01$ifdk4/patch= 2006.285.22:32:30.01$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.22:32:30.01$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.22:32:30.01$setupk4/!*+20s 2006.285.22:32:35.14#trakl#Source acquired 2006.285.22:32:37.14#flagr#flagr/antenna,acquired 2006.285.22:32:37.23#abcon#<5=/06 0.7 1.6 16.87 971016.2\r\n> 2006.285.22:32:37.25#abcon#{5=INTERFACE CLEAR} 2006.285.22:32:37.31#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:32:44.52$setupk4/"tpicd 2006.285.22:32:44.52$setupk4/echo=off 2006.285.22:32:44.52$setupk4/xlog=off 2006.285.22:32:44.52:!2006.285.22:34:40 2006.285.22:34:40.00:preob 2006.285.22:34:41.13/onsource/TRACKING 2006.285.22:34:41.13:!2006.285.22:34:50 2006.285.22:34:50.00:"tape 2006.285.22:34:50.00:"st=record 2006.285.22:34:50.00:data_valid=on 2006.285.22:34:50.00:midob 2006.285.22:34:50.13/onsource/TRACKING 2006.285.22:34:50.13/wx/16.94,1016.1,97 2006.285.22:34:50.23/cable/+6.5114E-03 2006.285.22:34:51.32/va/01,07,usb,yes,33,36 2006.285.22:34:51.32/va/02,06,usb,yes,33,33 2006.285.22:34:51.32/va/03,07,usb,yes,33,34 2006.285.22:34:51.32/va/04,06,usb,yes,34,35 2006.285.22:34:51.32/va/05,03,usb,yes,33,34 2006.285.22:34:51.32/va/06,04,usb,yes,30,30 2006.285.22:34:51.32/va/07,04,usb,yes,31,31 2006.285.22:34:51.32/va/08,03,usb,yes,31,38 2006.285.22:34:51.55/valo/01,524.99,yes,locked 2006.285.22:34:51.55/valo/02,534.99,yes,locked 2006.285.22:34:51.55/valo/03,564.99,yes,locked 2006.285.22:34:51.55/valo/04,624.99,yes,locked 2006.285.22:34:51.55/valo/05,734.99,yes,locked 2006.285.22:34:51.55/valo/06,814.99,yes,locked 2006.285.22:34:51.55/valo/07,864.99,yes,locked 2006.285.22:34:51.55/valo/08,884.99,yes,locked 2006.285.22:34:52.64/vb/01,04,usb,yes,30,28 2006.285.22:34:52.64/vb/02,05,usb,yes,29,29 2006.285.22:34:52.64/vb/03,04,usb,yes,30,33 2006.285.22:34:52.64/vb/04,05,usb,yes,30,29 2006.285.22:34:52.64/vb/05,04,usb,yes,26,29 2006.285.22:34:52.64/vb/06,03,usb,yes,38,34 2006.285.22:34:52.64/vb/07,04,usb,yes,30,30 2006.285.22:34:52.64/vb/08,04,usb,yes,28,31 2006.285.22:34:52.88/vblo/01,629.99,yes,locked 2006.285.22:34:52.88/vblo/02,634.99,yes,locked 2006.285.22:34:52.88/vblo/03,649.99,yes,locked 2006.285.22:34:52.88/vblo/04,679.99,yes,locked 2006.285.22:34:52.88/vblo/05,709.99,yes,locked 2006.285.22:34:52.88/vblo/06,719.99,yes,locked 2006.285.22:34:52.88/vblo/07,734.99,yes,locked 2006.285.22:34:52.88/vblo/08,744.99,yes,locked 2006.285.22:34:53.03/vabw/8 2006.285.22:34:53.18/vbbw/8 2006.285.22:34:53.27/xfe/off,on,12.0 2006.285.22:34:53.66/ifatt/23,28,28,28 2006.285.22:34:54.07/fmout-gps/S +2.55E-07 2006.285.22:34:54.09:!2006.285.22:40:30 2006.285.22:40:30.00:data_valid=off 2006.285.22:40:30.00:"et 2006.285.22:40:30.00:!+3s 2006.285.22:40:33.01:"tape 2006.285.22:40:33.01:postob 2006.285.22:40:33.18/cable/+6.5102E-03 2006.285.22:40:33.18/wx/17.18,1016.1,96 2006.285.22:40:34.07/fmout-gps/S +2.53E-07 2006.285.22:40:34.07:scan_name=285-2245,jd0610,90 2006.285.22:40:34.07:source=3c274,123049.42,122328.0,2000.0,cw 2006.285.22:40:35.14#flagr#flagr/antenna,new-source 2006.285.22:40:35.14:checkk5 2006.285.22:40:35.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:40:36.08/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:40:36.48/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:40:36.82/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:40:37.20/chk_obsdata//k5ts1/T2852234??a.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.285.22:40:37.68/chk_obsdata//k5ts2/T2852234??b.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.285.22:40:38.26/chk_obsdata//k5ts3/T2852234??c.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.285.22:40:38.61/chk_obsdata//k5ts4/T2852234??d.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.285.22:40:39.42/k5log//k5ts1_log_newline 2006.285.22:40:40.33/k5log//k5ts2_log_newline 2006.285.22:40:41.18/k5log//k5ts3_log_newline 2006.285.22:40:41.97/k5log//k5ts4_log_newline 2006.285.22:40:41.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:40:41.99:setupk4=1 2006.285.22:40:41.99$setupk4/echo=on 2006.285.22:40:41.99$setupk4/pcalon 2006.285.22:40:41.99$pcalon/"no phase cal control is implemented here 2006.285.22:40:41.99$setupk4/"tpicd=stop 2006.285.22:40:41.99$setupk4/"rec=synch_on 2006.285.22:40:41.99$setupk4/"rec_mode=128 2006.285.22:40:41.99$setupk4/!* 2006.285.22:40:41.99$setupk4/recpk4 2006.285.22:40:41.99$recpk4/recpatch= 2006.285.22:40:42.00$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:40:42.00$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:40:42.00$setupk4/vck44 2006.285.22:40:42.00$vck44/valo=1,524.99 2006.285.22:40:42.00#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.22:40:42.00#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.22:40:42.00#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:42.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:40:42.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:40:42.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:40:42.00#ibcon#enter wrdev, iclass 32, count 0 2006.285.22:40:42.00#ibcon#first serial, iclass 32, count 0 2006.285.22:40:42.00#ibcon#enter sib2, iclass 32, count 0 2006.285.22:40:42.00#ibcon#flushed, iclass 32, count 0 2006.285.22:40:42.00#ibcon#about to write, iclass 32, count 0 2006.285.22:40:42.00#ibcon#wrote, iclass 32, count 0 2006.285.22:40:42.00#ibcon#about to read 3, iclass 32, count 0 2006.285.22:40:42.01#ibcon#read 3, iclass 32, count 0 2006.285.22:40:42.01#ibcon#about to read 4, iclass 32, count 0 2006.285.22:40:42.01#ibcon#read 4, iclass 32, count 0 2006.285.22:40:42.01#ibcon#about to read 5, iclass 32, count 0 2006.285.22:40:42.01#ibcon#read 5, iclass 32, count 0 2006.285.22:40:42.01#ibcon#about to read 6, iclass 32, count 0 2006.285.22:40:42.01#ibcon#read 6, iclass 32, count 0 2006.285.22:40:42.01#ibcon#end of sib2, iclass 32, count 0 2006.285.22:40:42.01#ibcon#*mode == 0, iclass 32, count 0 2006.285.22:40:42.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.22:40:42.01#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:40:42.01#ibcon#*before write, iclass 32, count 0 2006.285.22:40:42.01#ibcon#enter sib2, iclass 32, count 0 2006.285.22:40:42.01#ibcon#flushed, iclass 32, count 0 2006.285.22:40:42.01#ibcon#about to write, iclass 32, count 0 2006.285.22:40:42.01#ibcon#wrote, iclass 32, count 0 2006.285.22:40:42.01#ibcon#about to read 3, iclass 32, count 0 2006.285.22:40:42.06#ibcon#read 3, iclass 32, count 0 2006.285.22:40:42.06#ibcon#about to read 4, iclass 32, count 0 2006.285.22:40:42.06#ibcon#read 4, iclass 32, count 0 2006.285.22:40:42.06#ibcon#about to read 5, iclass 32, count 0 2006.285.22:40:42.06#ibcon#read 5, iclass 32, count 0 2006.285.22:40:42.06#ibcon#about to read 6, iclass 32, count 0 2006.285.22:40:42.06#ibcon#read 6, iclass 32, count 0 2006.285.22:40:42.06#ibcon#end of sib2, iclass 32, count 0 2006.285.22:40:42.06#ibcon#*after write, iclass 32, count 0 2006.285.22:40:42.06#ibcon#*before return 0, iclass 32, count 0 2006.285.22:40:42.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:40:42.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:40:42.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.22:40:42.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.22:40:42.06$vck44/va=1,7 2006.285.22:40:42.06#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.22:40:42.06#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.22:40:42.06#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:42.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:40:42.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:40:42.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:40:42.06#ibcon#enter wrdev, iclass 34, count 2 2006.285.22:40:42.06#ibcon#first serial, iclass 34, count 2 2006.285.22:40:42.06#ibcon#enter sib2, iclass 34, count 2 2006.285.22:40:42.06#ibcon#flushed, iclass 34, count 2 2006.285.22:40:42.06#ibcon#about to write, iclass 34, count 2 2006.285.22:40:42.06#ibcon#wrote, iclass 34, count 2 2006.285.22:40:42.06#ibcon#about to read 3, iclass 34, count 2 2006.285.22:40:42.08#ibcon#read 3, iclass 34, count 2 2006.285.22:40:42.08#ibcon#about to read 4, iclass 34, count 2 2006.285.22:40:42.08#ibcon#read 4, iclass 34, count 2 2006.285.22:40:42.08#ibcon#about to read 5, iclass 34, count 2 2006.285.22:40:42.08#ibcon#read 5, iclass 34, count 2 2006.285.22:40:42.08#ibcon#about to read 6, iclass 34, count 2 2006.285.22:40:42.08#ibcon#read 6, iclass 34, count 2 2006.285.22:40:42.08#ibcon#end of sib2, iclass 34, count 2 2006.285.22:40:42.08#ibcon#*mode == 0, iclass 34, count 2 2006.285.22:40:42.08#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.22:40:42.08#ibcon#[25=AT01-07\r\n] 2006.285.22:40:42.08#ibcon#*before write, iclass 34, count 2 2006.285.22:40:42.08#ibcon#enter sib2, iclass 34, count 2 2006.285.22:40:42.08#ibcon#flushed, iclass 34, count 2 2006.285.22:40:42.08#ibcon#about to write, iclass 34, count 2 2006.285.22:40:42.08#ibcon#wrote, iclass 34, count 2 2006.285.22:40:42.08#ibcon#about to read 3, iclass 34, count 2 2006.285.22:40:42.11#ibcon#read 3, iclass 34, count 2 2006.285.22:40:42.11#ibcon#about to read 4, iclass 34, count 2 2006.285.22:40:42.11#ibcon#read 4, iclass 34, count 2 2006.285.22:40:42.11#ibcon#about to read 5, iclass 34, count 2 2006.285.22:40:42.11#ibcon#read 5, iclass 34, count 2 2006.285.22:40:42.11#ibcon#about to read 6, iclass 34, count 2 2006.285.22:40:42.11#ibcon#read 6, iclass 34, count 2 2006.285.22:40:42.11#ibcon#end of sib2, iclass 34, count 2 2006.285.22:40:42.11#ibcon#*after write, iclass 34, count 2 2006.285.22:40:42.11#ibcon#*before return 0, iclass 34, count 2 2006.285.22:40:42.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:40:42.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:40:42.11#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.22:40:42.11#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:42.11#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:40:42.23#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:40:42.23#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:40:42.23#ibcon#enter wrdev, iclass 34, count 0 2006.285.22:40:42.23#ibcon#first serial, iclass 34, count 0 2006.285.22:40:42.23#ibcon#enter sib2, iclass 34, count 0 2006.285.22:40:42.23#ibcon#flushed, iclass 34, count 0 2006.285.22:40:42.23#ibcon#about to write, iclass 34, count 0 2006.285.22:40:42.23#ibcon#wrote, iclass 34, count 0 2006.285.22:40:42.23#ibcon#about to read 3, iclass 34, count 0 2006.285.22:40:42.25#ibcon#read 3, iclass 34, count 0 2006.285.22:40:42.25#ibcon#about to read 4, iclass 34, count 0 2006.285.22:40:42.25#ibcon#read 4, iclass 34, count 0 2006.285.22:40:42.25#ibcon#about to read 5, iclass 34, count 0 2006.285.22:40:42.25#ibcon#read 5, iclass 34, count 0 2006.285.22:40:42.25#ibcon#about to read 6, iclass 34, count 0 2006.285.22:40:42.25#ibcon#read 6, iclass 34, count 0 2006.285.22:40:42.25#ibcon#end of sib2, iclass 34, count 0 2006.285.22:40:42.25#ibcon#*mode == 0, iclass 34, count 0 2006.285.22:40:42.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.22:40:42.25#ibcon#[25=USB\r\n] 2006.285.22:40:42.25#ibcon#*before write, iclass 34, count 0 2006.285.22:40:42.25#ibcon#enter sib2, iclass 34, count 0 2006.285.22:40:42.25#ibcon#flushed, iclass 34, count 0 2006.285.22:40:42.25#ibcon#about to write, iclass 34, count 0 2006.285.22:40:42.25#ibcon#wrote, iclass 34, count 0 2006.285.22:40:42.25#ibcon#about to read 3, iclass 34, count 0 2006.285.22:40:42.28#ibcon#read 3, iclass 34, count 0 2006.285.22:40:42.28#ibcon#about to read 4, iclass 34, count 0 2006.285.22:40:42.28#ibcon#read 4, iclass 34, count 0 2006.285.22:40:42.28#ibcon#about to read 5, iclass 34, count 0 2006.285.22:40:42.28#ibcon#read 5, iclass 34, count 0 2006.285.22:40:42.28#ibcon#about to read 6, iclass 34, count 0 2006.285.22:40:42.28#ibcon#read 6, iclass 34, count 0 2006.285.22:40:42.28#ibcon#end of sib2, iclass 34, count 0 2006.285.22:40:42.28#ibcon#*after write, iclass 34, count 0 2006.285.22:40:42.28#ibcon#*before return 0, iclass 34, count 0 2006.285.22:40:42.28#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:40:42.28#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:40:42.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.22:40:42.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.22:40:42.28$vck44/valo=2,534.99 2006.285.22:40:42.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.22:40:42.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.22:40:42.28#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:42.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:40:42.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:40:42.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:40:42.28#ibcon#enter wrdev, iclass 36, count 0 2006.285.22:40:42.28#ibcon#first serial, iclass 36, count 0 2006.285.22:40:42.28#ibcon#enter sib2, iclass 36, count 0 2006.285.22:40:42.28#ibcon#flushed, iclass 36, count 0 2006.285.22:40:42.28#ibcon#about to write, iclass 36, count 0 2006.285.22:40:42.28#ibcon#wrote, iclass 36, count 0 2006.285.22:40:42.28#ibcon#about to read 3, iclass 36, count 0 2006.285.22:40:42.30#ibcon#read 3, iclass 36, count 0 2006.285.22:40:42.30#ibcon#about to read 4, iclass 36, count 0 2006.285.22:40:42.30#ibcon#read 4, iclass 36, count 0 2006.285.22:40:42.30#ibcon#about to read 5, iclass 36, count 0 2006.285.22:40:42.30#ibcon#read 5, iclass 36, count 0 2006.285.22:40:42.30#ibcon#about to read 6, iclass 36, count 0 2006.285.22:40:42.30#ibcon#read 6, iclass 36, count 0 2006.285.22:40:42.30#ibcon#end of sib2, iclass 36, count 0 2006.285.22:40:42.30#ibcon#*mode == 0, iclass 36, count 0 2006.285.22:40:42.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.22:40:42.30#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:40:42.30#ibcon#*before write, iclass 36, count 0 2006.285.22:40:42.30#ibcon#enter sib2, iclass 36, count 0 2006.285.22:40:42.30#ibcon#flushed, iclass 36, count 0 2006.285.22:40:42.30#ibcon#about to write, iclass 36, count 0 2006.285.22:40:42.30#ibcon#wrote, iclass 36, count 0 2006.285.22:40:42.30#ibcon#about to read 3, iclass 36, count 0 2006.285.22:40:42.34#ibcon#read 3, iclass 36, count 0 2006.285.22:40:42.34#ibcon#about to read 4, iclass 36, count 0 2006.285.22:40:42.34#ibcon#read 4, iclass 36, count 0 2006.285.22:40:42.34#ibcon#about to read 5, iclass 36, count 0 2006.285.22:40:42.34#ibcon#read 5, iclass 36, count 0 2006.285.22:40:42.34#ibcon#about to read 6, iclass 36, count 0 2006.285.22:40:42.34#ibcon#read 6, iclass 36, count 0 2006.285.22:40:42.34#ibcon#end of sib2, iclass 36, count 0 2006.285.22:40:42.34#ibcon#*after write, iclass 36, count 0 2006.285.22:40:42.34#ibcon#*before return 0, iclass 36, count 0 2006.285.22:40:42.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:40:42.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:40:42.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.22:40:42.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.22:40:42.34$vck44/va=2,6 2006.285.22:40:42.34#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.22:40:42.34#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.22:40:42.34#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:42.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:40:42.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:40:42.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:40:42.40#ibcon#enter wrdev, iclass 38, count 2 2006.285.22:40:42.40#ibcon#first serial, iclass 38, count 2 2006.285.22:40:42.40#ibcon#enter sib2, iclass 38, count 2 2006.285.22:40:42.40#ibcon#flushed, iclass 38, count 2 2006.285.22:40:42.40#ibcon#about to write, iclass 38, count 2 2006.285.22:40:42.40#ibcon#wrote, iclass 38, count 2 2006.285.22:40:42.40#ibcon#about to read 3, iclass 38, count 2 2006.285.22:40:42.42#ibcon#read 3, iclass 38, count 2 2006.285.22:40:42.42#ibcon#about to read 4, iclass 38, count 2 2006.285.22:40:42.42#ibcon#read 4, iclass 38, count 2 2006.285.22:40:42.42#ibcon#about to read 5, iclass 38, count 2 2006.285.22:40:42.42#ibcon#read 5, iclass 38, count 2 2006.285.22:40:42.42#ibcon#about to read 6, iclass 38, count 2 2006.285.22:40:42.42#ibcon#read 6, iclass 38, count 2 2006.285.22:40:42.42#ibcon#end of sib2, iclass 38, count 2 2006.285.22:40:42.42#ibcon#*mode == 0, iclass 38, count 2 2006.285.22:40:42.42#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.22:40:42.42#ibcon#[25=AT02-06\r\n] 2006.285.22:40:42.42#ibcon#*before write, iclass 38, count 2 2006.285.22:40:42.42#ibcon#enter sib2, iclass 38, count 2 2006.285.22:40:42.42#ibcon#flushed, iclass 38, count 2 2006.285.22:40:42.42#ibcon#about to write, iclass 38, count 2 2006.285.22:40:42.42#ibcon#wrote, iclass 38, count 2 2006.285.22:40:42.42#ibcon#about to read 3, iclass 38, count 2 2006.285.22:40:42.45#ibcon#read 3, iclass 38, count 2 2006.285.22:40:42.45#ibcon#about to read 4, iclass 38, count 2 2006.285.22:40:42.45#ibcon#read 4, iclass 38, count 2 2006.285.22:40:42.45#ibcon#about to read 5, iclass 38, count 2 2006.285.22:40:42.45#ibcon#read 5, iclass 38, count 2 2006.285.22:40:42.45#ibcon#about to read 6, iclass 38, count 2 2006.285.22:40:42.45#ibcon#read 6, iclass 38, count 2 2006.285.22:40:42.45#ibcon#end of sib2, iclass 38, count 2 2006.285.22:40:42.45#ibcon#*after write, iclass 38, count 2 2006.285.22:40:42.45#ibcon#*before return 0, iclass 38, count 2 2006.285.22:40:42.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:40:42.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:40:42.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.22:40:42.45#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:42.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:40:42.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:40:42.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:40:42.57#ibcon#enter wrdev, iclass 38, count 0 2006.285.22:40:42.57#ibcon#first serial, iclass 38, count 0 2006.285.22:40:42.57#ibcon#enter sib2, iclass 38, count 0 2006.285.22:40:42.57#ibcon#flushed, iclass 38, count 0 2006.285.22:40:42.57#ibcon#about to write, iclass 38, count 0 2006.285.22:40:42.57#ibcon#wrote, iclass 38, count 0 2006.285.22:40:42.57#ibcon#about to read 3, iclass 38, count 0 2006.285.22:40:42.59#ibcon#read 3, iclass 38, count 0 2006.285.22:40:42.59#ibcon#about to read 4, iclass 38, count 0 2006.285.22:40:42.59#ibcon#read 4, iclass 38, count 0 2006.285.22:40:42.59#ibcon#about to read 5, iclass 38, count 0 2006.285.22:40:42.59#ibcon#read 5, iclass 38, count 0 2006.285.22:40:42.59#ibcon#about to read 6, iclass 38, count 0 2006.285.22:40:42.59#ibcon#read 6, iclass 38, count 0 2006.285.22:40:42.59#ibcon#end of sib2, iclass 38, count 0 2006.285.22:40:42.59#ibcon#*mode == 0, iclass 38, count 0 2006.285.22:40:42.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.22:40:42.59#ibcon#[25=USB\r\n] 2006.285.22:40:42.59#ibcon#*before write, iclass 38, count 0 2006.285.22:40:42.59#ibcon#enter sib2, iclass 38, count 0 2006.285.22:40:42.59#ibcon#flushed, iclass 38, count 0 2006.285.22:40:42.59#ibcon#about to write, iclass 38, count 0 2006.285.22:40:42.59#ibcon#wrote, iclass 38, count 0 2006.285.22:40:42.59#ibcon#about to read 3, iclass 38, count 0 2006.285.22:40:42.62#ibcon#read 3, iclass 38, count 0 2006.285.22:40:42.62#ibcon#about to read 4, iclass 38, count 0 2006.285.22:40:42.62#ibcon#read 4, iclass 38, count 0 2006.285.22:40:42.62#ibcon#about to read 5, iclass 38, count 0 2006.285.22:40:42.62#ibcon#read 5, iclass 38, count 0 2006.285.22:40:42.62#ibcon#about to read 6, iclass 38, count 0 2006.285.22:40:42.62#ibcon#read 6, iclass 38, count 0 2006.285.22:40:42.62#ibcon#end of sib2, iclass 38, count 0 2006.285.22:40:42.62#ibcon#*after write, iclass 38, count 0 2006.285.22:40:42.62#ibcon#*before return 0, iclass 38, count 0 2006.285.22:40:42.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:40:42.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:40:42.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.22:40:42.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.22:40:42.62$vck44/valo=3,564.99 2006.285.22:40:42.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.22:40:42.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.22:40:42.62#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:42.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:40:42.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:40:42.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:40:42.62#ibcon#enter wrdev, iclass 40, count 0 2006.285.22:40:42.62#ibcon#first serial, iclass 40, count 0 2006.285.22:40:42.62#ibcon#enter sib2, iclass 40, count 0 2006.285.22:40:42.62#ibcon#flushed, iclass 40, count 0 2006.285.22:40:42.62#ibcon#about to write, iclass 40, count 0 2006.285.22:40:42.62#ibcon#wrote, iclass 40, count 0 2006.285.22:40:42.62#ibcon#about to read 3, iclass 40, count 0 2006.285.22:40:42.64#ibcon#read 3, iclass 40, count 0 2006.285.22:40:42.64#ibcon#about to read 4, iclass 40, count 0 2006.285.22:40:42.64#ibcon#read 4, iclass 40, count 0 2006.285.22:40:42.64#ibcon#about to read 5, iclass 40, count 0 2006.285.22:40:42.64#ibcon#read 5, iclass 40, count 0 2006.285.22:40:42.64#ibcon#about to read 6, iclass 40, count 0 2006.285.22:40:42.64#ibcon#read 6, iclass 40, count 0 2006.285.22:40:42.64#ibcon#end of sib2, iclass 40, count 0 2006.285.22:40:42.64#ibcon#*mode == 0, iclass 40, count 0 2006.285.22:40:42.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.22:40:42.64#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:40:42.64#ibcon#*before write, iclass 40, count 0 2006.285.22:40:42.64#ibcon#enter sib2, iclass 40, count 0 2006.285.22:40:42.64#ibcon#flushed, iclass 40, count 0 2006.285.22:40:42.64#ibcon#about to write, iclass 40, count 0 2006.285.22:40:42.64#ibcon#wrote, iclass 40, count 0 2006.285.22:40:42.64#ibcon#about to read 3, iclass 40, count 0 2006.285.22:40:42.68#ibcon#read 3, iclass 40, count 0 2006.285.22:40:42.68#ibcon#about to read 4, iclass 40, count 0 2006.285.22:40:42.68#ibcon#read 4, iclass 40, count 0 2006.285.22:40:42.68#ibcon#about to read 5, iclass 40, count 0 2006.285.22:40:42.68#ibcon#read 5, iclass 40, count 0 2006.285.22:40:42.68#ibcon#about to read 6, iclass 40, count 0 2006.285.22:40:42.68#ibcon#read 6, iclass 40, count 0 2006.285.22:40:42.68#ibcon#end of sib2, iclass 40, count 0 2006.285.22:40:42.68#ibcon#*after write, iclass 40, count 0 2006.285.22:40:42.68#ibcon#*before return 0, iclass 40, count 0 2006.285.22:40:42.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:40:42.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:40:42.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.22:40:42.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.22:40:42.68$vck44/va=3,7 2006.285.22:40:42.68#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.22:40:42.68#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.22:40:42.68#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:42.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:40:42.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:40:42.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:40:42.74#ibcon#enter wrdev, iclass 4, count 2 2006.285.22:40:42.74#ibcon#first serial, iclass 4, count 2 2006.285.22:40:42.74#ibcon#enter sib2, iclass 4, count 2 2006.285.22:40:42.74#ibcon#flushed, iclass 4, count 2 2006.285.22:40:42.74#ibcon#about to write, iclass 4, count 2 2006.285.22:40:42.74#ibcon#wrote, iclass 4, count 2 2006.285.22:40:42.74#ibcon#about to read 3, iclass 4, count 2 2006.285.22:40:42.76#ibcon#read 3, iclass 4, count 2 2006.285.22:40:42.76#ibcon#about to read 4, iclass 4, count 2 2006.285.22:40:42.76#ibcon#read 4, iclass 4, count 2 2006.285.22:40:42.76#ibcon#about to read 5, iclass 4, count 2 2006.285.22:40:42.76#ibcon#read 5, iclass 4, count 2 2006.285.22:40:42.76#ibcon#about to read 6, iclass 4, count 2 2006.285.22:40:42.76#ibcon#read 6, iclass 4, count 2 2006.285.22:40:42.76#ibcon#end of sib2, iclass 4, count 2 2006.285.22:40:42.76#ibcon#*mode == 0, iclass 4, count 2 2006.285.22:40:42.76#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.22:40:42.76#ibcon#[25=AT03-07\r\n] 2006.285.22:40:42.76#ibcon#*before write, iclass 4, count 2 2006.285.22:40:42.76#ibcon#enter sib2, iclass 4, count 2 2006.285.22:40:42.76#ibcon#flushed, iclass 4, count 2 2006.285.22:40:42.76#ibcon#about to write, iclass 4, count 2 2006.285.22:40:42.76#ibcon#wrote, iclass 4, count 2 2006.285.22:40:42.76#ibcon#about to read 3, iclass 4, count 2 2006.285.22:40:42.79#ibcon#read 3, iclass 4, count 2 2006.285.22:40:42.79#ibcon#about to read 4, iclass 4, count 2 2006.285.22:40:42.79#ibcon#read 4, iclass 4, count 2 2006.285.22:40:42.79#ibcon#about to read 5, iclass 4, count 2 2006.285.22:40:42.79#ibcon#read 5, iclass 4, count 2 2006.285.22:40:42.79#ibcon#about to read 6, iclass 4, count 2 2006.285.22:40:42.79#ibcon#read 6, iclass 4, count 2 2006.285.22:40:42.79#ibcon#end of sib2, iclass 4, count 2 2006.285.22:40:42.79#ibcon#*after write, iclass 4, count 2 2006.285.22:40:42.79#ibcon#*before return 0, iclass 4, count 2 2006.285.22:40:42.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:40:42.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:40:42.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.22:40:42.79#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:42.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:40:42.91#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:40:42.91#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:40:42.91#ibcon#enter wrdev, iclass 4, count 0 2006.285.22:40:42.91#ibcon#first serial, iclass 4, count 0 2006.285.22:40:42.91#ibcon#enter sib2, iclass 4, count 0 2006.285.22:40:42.91#ibcon#flushed, iclass 4, count 0 2006.285.22:40:42.91#ibcon#about to write, iclass 4, count 0 2006.285.22:40:42.91#ibcon#wrote, iclass 4, count 0 2006.285.22:40:42.91#ibcon#about to read 3, iclass 4, count 0 2006.285.22:40:42.93#ibcon#read 3, iclass 4, count 0 2006.285.22:40:42.93#ibcon#about to read 4, iclass 4, count 0 2006.285.22:40:42.93#ibcon#read 4, iclass 4, count 0 2006.285.22:40:42.93#ibcon#about to read 5, iclass 4, count 0 2006.285.22:40:42.93#ibcon#read 5, iclass 4, count 0 2006.285.22:40:42.93#ibcon#about to read 6, iclass 4, count 0 2006.285.22:40:42.93#ibcon#read 6, iclass 4, count 0 2006.285.22:40:42.93#ibcon#end of sib2, iclass 4, count 0 2006.285.22:40:42.93#ibcon#*mode == 0, iclass 4, count 0 2006.285.22:40:42.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.22:40:42.93#ibcon#[25=USB\r\n] 2006.285.22:40:42.93#ibcon#*before write, iclass 4, count 0 2006.285.22:40:42.93#ibcon#enter sib2, iclass 4, count 0 2006.285.22:40:42.93#ibcon#flushed, iclass 4, count 0 2006.285.22:40:42.93#ibcon#about to write, iclass 4, count 0 2006.285.22:40:42.93#ibcon#wrote, iclass 4, count 0 2006.285.22:40:42.93#ibcon#about to read 3, iclass 4, count 0 2006.285.22:40:42.96#ibcon#read 3, iclass 4, count 0 2006.285.22:40:42.96#ibcon#about to read 4, iclass 4, count 0 2006.285.22:40:42.96#ibcon#read 4, iclass 4, count 0 2006.285.22:40:42.96#ibcon#about to read 5, iclass 4, count 0 2006.285.22:40:42.96#ibcon#read 5, iclass 4, count 0 2006.285.22:40:42.96#ibcon#about to read 6, iclass 4, count 0 2006.285.22:40:42.96#ibcon#read 6, iclass 4, count 0 2006.285.22:40:42.96#ibcon#end of sib2, iclass 4, count 0 2006.285.22:40:42.96#ibcon#*after write, iclass 4, count 0 2006.285.22:40:42.96#ibcon#*before return 0, iclass 4, count 0 2006.285.22:40:42.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:40:42.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:40:42.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.22:40:42.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.22:40:42.96$vck44/valo=4,624.99 2006.285.22:40:42.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.22:40:42.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.22:40:42.96#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:42.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:40:42.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:40:42.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:40:42.96#ibcon#enter wrdev, iclass 6, count 0 2006.285.22:40:42.96#ibcon#first serial, iclass 6, count 0 2006.285.22:40:42.96#ibcon#enter sib2, iclass 6, count 0 2006.285.22:40:42.96#ibcon#flushed, iclass 6, count 0 2006.285.22:40:42.96#ibcon#about to write, iclass 6, count 0 2006.285.22:40:42.96#ibcon#wrote, iclass 6, count 0 2006.285.22:40:42.96#ibcon#about to read 3, iclass 6, count 0 2006.285.22:40:42.98#ibcon#read 3, iclass 6, count 0 2006.285.22:40:42.98#ibcon#about to read 4, iclass 6, count 0 2006.285.22:40:42.98#ibcon#read 4, iclass 6, count 0 2006.285.22:40:42.98#ibcon#about to read 5, iclass 6, count 0 2006.285.22:40:42.98#ibcon#read 5, iclass 6, count 0 2006.285.22:40:42.98#ibcon#about to read 6, iclass 6, count 0 2006.285.22:40:42.98#ibcon#read 6, iclass 6, count 0 2006.285.22:40:42.98#ibcon#end of sib2, iclass 6, count 0 2006.285.22:40:42.98#ibcon#*mode == 0, iclass 6, count 0 2006.285.22:40:42.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.22:40:42.98#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:40:42.98#ibcon#*before write, iclass 6, count 0 2006.285.22:40:42.98#ibcon#enter sib2, iclass 6, count 0 2006.285.22:40:42.98#ibcon#flushed, iclass 6, count 0 2006.285.22:40:42.98#ibcon#about to write, iclass 6, count 0 2006.285.22:40:42.98#ibcon#wrote, iclass 6, count 0 2006.285.22:40:42.98#ibcon#about to read 3, iclass 6, count 0 2006.285.22:40:43.02#ibcon#read 3, iclass 6, count 0 2006.285.22:40:43.02#ibcon#about to read 4, iclass 6, count 0 2006.285.22:40:43.02#ibcon#read 4, iclass 6, count 0 2006.285.22:40:43.02#ibcon#about to read 5, iclass 6, count 0 2006.285.22:40:43.02#ibcon#read 5, iclass 6, count 0 2006.285.22:40:43.02#ibcon#about to read 6, iclass 6, count 0 2006.285.22:40:43.02#ibcon#read 6, iclass 6, count 0 2006.285.22:40:43.02#ibcon#end of sib2, iclass 6, count 0 2006.285.22:40:43.02#ibcon#*after write, iclass 6, count 0 2006.285.22:40:43.02#ibcon#*before return 0, iclass 6, count 0 2006.285.22:40:43.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:40:43.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:40:43.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.22:40:43.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.22:40:43.02$vck44/va=4,6 2006.285.22:40:43.02#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.22:40:43.02#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.22:40:43.02#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:43.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:40:43.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:40:43.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:40:43.08#ibcon#enter wrdev, iclass 10, count 2 2006.285.22:40:43.08#ibcon#first serial, iclass 10, count 2 2006.285.22:40:43.08#ibcon#enter sib2, iclass 10, count 2 2006.285.22:40:43.08#ibcon#flushed, iclass 10, count 2 2006.285.22:40:43.08#ibcon#about to write, iclass 10, count 2 2006.285.22:40:43.08#ibcon#wrote, iclass 10, count 2 2006.285.22:40:43.08#ibcon#about to read 3, iclass 10, count 2 2006.285.22:40:43.10#ibcon#read 3, iclass 10, count 2 2006.285.22:40:43.10#ibcon#about to read 4, iclass 10, count 2 2006.285.22:40:43.10#ibcon#read 4, iclass 10, count 2 2006.285.22:40:43.10#ibcon#about to read 5, iclass 10, count 2 2006.285.22:40:43.10#ibcon#read 5, iclass 10, count 2 2006.285.22:40:43.10#ibcon#about to read 6, iclass 10, count 2 2006.285.22:40:43.10#ibcon#read 6, iclass 10, count 2 2006.285.22:40:43.10#ibcon#end of sib2, iclass 10, count 2 2006.285.22:40:43.10#ibcon#*mode == 0, iclass 10, count 2 2006.285.22:40:43.10#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.22:40:43.10#ibcon#[25=AT04-06\r\n] 2006.285.22:40:43.10#ibcon#*before write, iclass 10, count 2 2006.285.22:40:43.10#ibcon#enter sib2, iclass 10, count 2 2006.285.22:40:43.10#ibcon#flushed, iclass 10, count 2 2006.285.22:40:43.10#ibcon#about to write, iclass 10, count 2 2006.285.22:40:43.10#ibcon#wrote, iclass 10, count 2 2006.285.22:40:43.10#ibcon#about to read 3, iclass 10, count 2 2006.285.22:40:43.13#ibcon#read 3, iclass 10, count 2 2006.285.22:40:43.13#ibcon#about to read 4, iclass 10, count 2 2006.285.22:40:43.13#ibcon#read 4, iclass 10, count 2 2006.285.22:40:43.13#ibcon#about to read 5, iclass 10, count 2 2006.285.22:40:43.13#ibcon#read 5, iclass 10, count 2 2006.285.22:40:43.13#ibcon#about to read 6, iclass 10, count 2 2006.285.22:40:43.13#ibcon#read 6, iclass 10, count 2 2006.285.22:40:43.13#ibcon#end of sib2, iclass 10, count 2 2006.285.22:40:43.13#ibcon#*after write, iclass 10, count 2 2006.285.22:40:43.13#ibcon#*before return 0, iclass 10, count 2 2006.285.22:40:43.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:40:43.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:40:43.13#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.22:40:43.13#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:43.13#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:40:43.25#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:40:43.25#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:40:43.25#ibcon#enter wrdev, iclass 10, count 0 2006.285.22:40:43.25#ibcon#first serial, iclass 10, count 0 2006.285.22:40:43.25#ibcon#enter sib2, iclass 10, count 0 2006.285.22:40:43.25#ibcon#flushed, iclass 10, count 0 2006.285.22:40:43.25#ibcon#about to write, iclass 10, count 0 2006.285.22:40:43.25#ibcon#wrote, iclass 10, count 0 2006.285.22:40:43.25#ibcon#about to read 3, iclass 10, count 0 2006.285.22:40:43.27#ibcon#read 3, iclass 10, count 0 2006.285.22:40:43.27#ibcon#about to read 4, iclass 10, count 0 2006.285.22:40:43.27#ibcon#read 4, iclass 10, count 0 2006.285.22:40:43.27#ibcon#about to read 5, iclass 10, count 0 2006.285.22:40:43.27#ibcon#read 5, iclass 10, count 0 2006.285.22:40:43.27#ibcon#about to read 6, iclass 10, count 0 2006.285.22:40:43.27#ibcon#read 6, iclass 10, count 0 2006.285.22:40:43.27#ibcon#end of sib2, iclass 10, count 0 2006.285.22:40:43.27#ibcon#*mode == 0, iclass 10, count 0 2006.285.22:40:43.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.22:40:43.27#ibcon#[25=USB\r\n] 2006.285.22:40:43.27#ibcon#*before write, iclass 10, count 0 2006.285.22:40:43.27#ibcon#enter sib2, iclass 10, count 0 2006.285.22:40:43.27#ibcon#flushed, iclass 10, count 0 2006.285.22:40:43.27#ibcon#about to write, iclass 10, count 0 2006.285.22:40:43.27#ibcon#wrote, iclass 10, count 0 2006.285.22:40:43.27#ibcon#about to read 3, iclass 10, count 0 2006.285.22:40:43.30#ibcon#read 3, iclass 10, count 0 2006.285.22:40:43.30#ibcon#about to read 4, iclass 10, count 0 2006.285.22:40:43.30#ibcon#read 4, iclass 10, count 0 2006.285.22:40:43.30#ibcon#about to read 5, iclass 10, count 0 2006.285.22:40:43.30#ibcon#read 5, iclass 10, count 0 2006.285.22:40:43.30#ibcon#about to read 6, iclass 10, count 0 2006.285.22:40:43.30#ibcon#read 6, iclass 10, count 0 2006.285.22:40:43.30#ibcon#end of sib2, iclass 10, count 0 2006.285.22:40:43.30#ibcon#*after write, iclass 10, count 0 2006.285.22:40:43.30#ibcon#*before return 0, iclass 10, count 0 2006.285.22:40:43.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:40:43.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:40:43.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.22:40:43.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.22:40:43.30$vck44/valo=5,734.99 2006.285.22:40:43.30#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.22:40:43.30#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.22:40:43.30#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:43.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:40:43.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:40:43.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:40:43.30#ibcon#enter wrdev, iclass 12, count 0 2006.285.22:40:43.30#ibcon#first serial, iclass 12, count 0 2006.285.22:40:43.30#ibcon#enter sib2, iclass 12, count 0 2006.285.22:40:43.30#ibcon#flushed, iclass 12, count 0 2006.285.22:40:43.30#ibcon#about to write, iclass 12, count 0 2006.285.22:40:43.30#ibcon#wrote, iclass 12, count 0 2006.285.22:40:43.30#ibcon#about to read 3, iclass 12, count 0 2006.285.22:40:43.32#ibcon#read 3, iclass 12, count 0 2006.285.22:40:43.32#ibcon#about to read 4, iclass 12, count 0 2006.285.22:40:43.32#ibcon#read 4, iclass 12, count 0 2006.285.22:40:43.32#ibcon#about to read 5, iclass 12, count 0 2006.285.22:40:43.32#ibcon#read 5, iclass 12, count 0 2006.285.22:40:43.32#ibcon#about to read 6, iclass 12, count 0 2006.285.22:40:43.32#ibcon#read 6, iclass 12, count 0 2006.285.22:40:43.32#ibcon#end of sib2, iclass 12, count 0 2006.285.22:40:43.32#ibcon#*mode == 0, iclass 12, count 0 2006.285.22:40:43.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.22:40:43.32#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:40:43.32#ibcon#*before write, iclass 12, count 0 2006.285.22:40:43.32#ibcon#enter sib2, iclass 12, count 0 2006.285.22:40:43.32#ibcon#flushed, iclass 12, count 0 2006.285.22:40:43.32#ibcon#about to write, iclass 12, count 0 2006.285.22:40:43.32#ibcon#wrote, iclass 12, count 0 2006.285.22:40:43.32#ibcon#about to read 3, iclass 12, count 0 2006.285.22:40:43.36#ibcon#read 3, iclass 12, count 0 2006.285.22:40:43.36#ibcon#about to read 4, iclass 12, count 0 2006.285.22:40:43.36#ibcon#read 4, iclass 12, count 0 2006.285.22:40:43.36#ibcon#about to read 5, iclass 12, count 0 2006.285.22:40:43.36#ibcon#read 5, iclass 12, count 0 2006.285.22:40:43.36#ibcon#about to read 6, iclass 12, count 0 2006.285.22:40:43.36#ibcon#read 6, iclass 12, count 0 2006.285.22:40:43.36#ibcon#end of sib2, iclass 12, count 0 2006.285.22:40:43.36#ibcon#*after write, iclass 12, count 0 2006.285.22:40:43.36#ibcon#*before return 0, iclass 12, count 0 2006.285.22:40:43.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:40:43.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:40:43.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.22:40:43.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.22:40:43.36$vck44/va=5,3 2006.285.22:40:43.36#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.22:40:43.36#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.22:40:43.36#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:43.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:40:43.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:40:43.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:40:43.42#ibcon#enter wrdev, iclass 14, count 2 2006.285.22:40:43.42#ibcon#first serial, iclass 14, count 2 2006.285.22:40:43.42#ibcon#enter sib2, iclass 14, count 2 2006.285.22:40:43.42#ibcon#flushed, iclass 14, count 2 2006.285.22:40:43.42#ibcon#about to write, iclass 14, count 2 2006.285.22:40:43.42#ibcon#wrote, iclass 14, count 2 2006.285.22:40:43.42#ibcon#about to read 3, iclass 14, count 2 2006.285.22:40:43.44#ibcon#read 3, iclass 14, count 2 2006.285.22:40:43.44#ibcon#about to read 4, iclass 14, count 2 2006.285.22:40:43.44#ibcon#read 4, iclass 14, count 2 2006.285.22:40:43.44#ibcon#about to read 5, iclass 14, count 2 2006.285.22:40:43.44#ibcon#read 5, iclass 14, count 2 2006.285.22:40:43.44#ibcon#about to read 6, iclass 14, count 2 2006.285.22:40:43.44#ibcon#read 6, iclass 14, count 2 2006.285.22:40:43.44#ibcon#end of sib2, iclass 14, count 2 2006.285.22:40:43.44#ibcon#*mode == 0, iclass 14, count 2 2006.285.22:40:43.44#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.22:40:43.44#ibcon#[25=AT05-03\r\n] 2006.285.22:40:43.44#ibcon#*before write, iclass 14, count 2 2006.285.22:40:43.44#ibcon#enter sib2, iclass 14, count 2 2006.285.22:40:43.44#ibcon#flushed, iclass 14, count 2 2006.285.22:40:43.44#ibcon#about to write, iclass 14, count 2 2006.285.22:40:43.44#ibcon#wrote, iclass 14, count 2 2006.285.22:40:43.44#ibcon#about to read 3, iclass 14, count 2 2006.285.22:40:43.47#ibcon#read 3, iclass 14, count 2 2006.285.22:40:43.47#ibcon#about to read 4, iclass 14, count 2 2006.285.22:40:43.47#ibcon#read 4, iclass 14, count 2 2006.285.22:40:43.47#ibcon#about to read 5, iclass 14, count 2 2006.285.22:40:43.47#ibcon#read 5, iclass 14, count 2 2006.285.22:40:43.47#ibcon#about to read 6, iclass 14, count 2 2006.285.22:40:43.47#ibcon#read 6, iclass 14, count 2 2006.285.22:40:43.47#ibcon#end of sib2, iclass 14, count 2 2006.285.22:40:43.47#ibcon#*after write, iclass 14, count 2 2006.285.22:40:43.47#ibcon#*before return 0, iclass 14, count 2 2006.285.22:40:43.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:40:43.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:40:43.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.22:40:43.47#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:43.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:40:43.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:40:43.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:40:43.59#ibcon#enter wrdev, iclass 14, count 0 2006.285.22:40:43.59#ibcon#first serial, iclass 14, count 0 2006.285.22:40:43.59#ibcon#enter sib2, iclass 14, count 0 2006.285.22:40:43.59#ibcon#flushed, iclass 14, count 0 2006.285.22:40:43.59#ibcon#about to write, iclass 14, count 0 2006.285.22:40:43.59#ibcon#wrote, iclass 14, count 0 2006.285.22:40:43.59#ibcon#about to read 3, iclass 14, count 0 2006.285.22:40:43.61#ibcon#read 3, iclass 14, count 0 2006.285.22:40:43.61#ibcon#about to read 4, iclass 14, count 0 2006.285.22:40:43.61#ibcon#read 4, iclass 14, count 0 2006.285.22:40:43.61#ibcon#about to read 5, iclass 14, count 0 2006.285.22:40:43.61#ibcon#read 5, iclass 14, count 0 2006.285.22:40:43.61#ibcon#about to read 6, iclass 14, count 0 2006.285.22:40:43.61#ibcon#read 6, iclass 14, count 0 2006.285.22:40:43.61#ibcon#end of sib2, iclass 14, count 0 2006.285.22:40:43.61#ibcon#*mode == 0, iclass 14, count 0 2006.285.22:40:43.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.22:40:43.61#ibcon#[25=USB\r\n] 2006.285.22:40:43.61#ibcon#*before write, iclass 14, count 0 2006.285.22:40:43.61#ibcon#enter sib2, iclass 14, count 0 2006.285.22:40:43.61#ibcon#flushed, iclass 14, count 0 2006.285.22:40:43.61#ibcon#about to write, iclass 14, count 0 2006.285.22:40:43.61#ibcon#wrote, iclass 14, count 0 2006.285.22:40:43.61#ibcon#about to read 3, iclass 14, count 0 2006.285.22:40:43.64#ibcon#read 3, iclass 14, count 0 2006.285.22:40:43.64#ibcon#about to read 4, iclass 14, count 0 2006.285.22:40:43.64#ibcon#read 4, iclass 14, count 0 2006.285.22:40:43.64#ibcon#about to read 5, iclass 14, count 0 2006.285.22:40:43.64#ibcon#read 5, iclass 14, count 0 2006.285.22:40:43.64#ibcon#about to read 6, iclass 14, count 0 2006.285.22:40:43.64#ibcon#read 6, iclass 14, count 0 2006.285.22:40:43.64#ibcon#end of sib2, iclass 14, count 0 2006.285.22:40:43.64#ibcon#*after write, iclass 14, count 0 2006.285.22:40:43.64#ibcon#*before return 0, iclass 14, count 0 2006.285.22:40:43.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:40:43.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:40:43.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.22:40:43.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.22:40:43.64$vck44/valo=6,814.99 2006.285.22:40:43.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.22:40:43.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.22:40:43.64#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:43.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:40:43.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:40:43.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:40:43.64#ibcon#enter wrdev, iclass 16, count 0 2006.285.22:40:43.64#ibcon#first serial, iclass 16, count 0 2006.285.22:40:43.64#ibcon#enter sib2, iclass 16, count 0 2006.285.22:40:43.64#ibcon#flushed, iclass 16, count 0 2006.285.22:40:43.64#ibcon#about to write, iclass 16, count 0 2006.285.22:40:43.64#ibcon#wrote, iclass 16, count 0 2006.285.22:40:43.64#ibcon#about to read 3, iclass 16, count 0 2006.285.22:40:43.66#ibcon#read 3, iclass 16, count 0 2006.285.22:40:43.66#ibcon#about to read 4, iclass 16, count 0 2006.285.22:40:43.66#ibcon#read 4, iclass 16, count 0 2006.285.22:40:43.66#ibcon#about to read 5, iclass 16, count 0 2006.285.22:40:43.66#ibcon#read 5, iclass 16, count 0 2006.285.22:40:43.66#ibcon#about to read 6, iclass 16, count 0 2006.285.22:40:43.66#ibcon#read 6, iclass 16, count 0 2006.285.22:40:43.66#ibcon#end of sib2, iclass 16, count 0 2006.285.22:40:43.66#ibcon#*mode == 0, iclass 16, count 0 2006.285.22:40:43.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.22:40:43.66#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:40:43.66#ibcon#*before write, iclass 16, count 0 2006.285.22:40:43.66#ibcon#enter sib2, iclass 16, count 0 2006.285.22:40:43.66#ibcon#flushed, iclass 16, count 0 2006.285.22:40:43.66#ibcon#about to write, iclass 16, count 0 2006.285.22:40:43.66#ibcon#wrote, iclass 16, count 0 2006.285.22:40:43.66#ibcon#about to read 3, iclass 16, count 0 2006.285.22:40:43.70#ibcon#read 3, iclass 16, count 0 2006.285.22:40:43.70#ibcon#about to read 4, iclass 16, count 0 2006.285.22:40:43.70#ibcon#read 4, iclass 16, count 0 2006.285.22:40:43.70#ibcon#about to read 5, iclass 16, count 0 2006.285.22:40:43.70#ibcon#read 5, iclass 16, count 0 2006.285.22:40:43.70#ibcon#about to read 6, iclass 16, count 0 2006.285.22:40:43.70#ibcon#read 6, iclass 16, count 0 2006.285.22:40:43.70#ibcon#end of sib2, iclass 16, count 0 2006.285.22:40:43.70#ibcon#*after write, iclass 16, count 0 2006.285.22:40:43.70#ibcon#*before return 0, iclass 16, count 0 2006.285.22:40:43.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:40:43.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:40:43.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.22:40:43.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.22:40:43.70$vck44/va=6,4 2006.285.22:40:43.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.22:40:43.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.22:40:43.70#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:43.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:40:43.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:40:43.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:40:43.76#ibcon#enter wrdev, iclass 18, count 2 2006.285.22:40:43.76#ibcon#first serial, iclass 18, count 2 2006.285.22:40:43.76#ibcon#enter sib2, iclass 18, count 2 2006.285.22:40:43.76#ibcon#flushed, iclass 18, count 2 2006.285.22:40:43.76#ibcon#about to write, iclass 18, count 2 2006.285.22:40:43.76#ibcon#wrote, iclass 18, count 2 2006.285.22:40:43.76#ibcon#about to read 3, iclass 18, count 2 2006.285.22:40:43.78#ibcon#read 3, iclass 18, count 2 2006.285.22:40:43.78#ibcon#about to read 4, iclass 18, count 2 2006.285.22:40:43.78#ibcon#read 4, iclass 18, count 2 2006.285.22:40:43.78#ibcon#about to read 5, iclass 18, count 2 2006.285.22:40:43.78#ibcon#read 5, iclass 18, count 2 2006.285.22:40:43.78#ibcon#about to read 6, iclass 18, count 2 2006.285.22:40:43.78#ibcon#read 6, iclass 18, count 2 2006.285.22:40:43.78#ibcon#end of sib2, iclass 18, count 2 2006.285.22:40:43.78#ibcon#*mode == 0, iclass 18, count 2 2006.285.22:40:43.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.22:40:43.78#ibcon#[25=AT06-04\r\n] 2006.285.22:40:43.78#ibcon#*before write, iclass 18, count 2 2006.285.22:40:43.78#ibcon#enter sib2, iclass 18, count 2 2006.285.22:40:43.78#ibcon#flushed, iclass 18, count 2 2006.285.22:40:43.78#ibcon#about to write, iclass 18, count 2 2006.285.22:40:43.78#ibcon#wrote, iclass 18, count 2 2006.285.22:40:43.78#ibcon#about to read 3, iclass 18, count 2 2006.285.22:40:43.81#ibcon#read 3, iclass 18, count 2 2006.285.22:40:43.81#ibcon#about to read 4, iclass 18, count 2 2006.285.22:40:43.81#ibcon#read 4, iclass 18, count 2 2006.285.22:40:43.81#ibcon#about to read 5, iclass 18, count 2 2006.285.22:40:43.81#ibcon#read 5, iclass 18, count 2 2006.285.22:40:43.81#ibcon#about to read 6, iclass 18, count 2 2006.285.22:40:43.81#ibcon#read 6, iclass 18, count 2 2006.285.22:40:43.81#ibcon#end of sib2, iclass 18, count 2 2006.285.22:40:43.81#ibcon#*after write, iclass 18, count 2 2006.285.22:40:43.81#ibcon#*before return 0, iclass 18, count 2 2006.285.22:40:43.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:40:43.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:40:43.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.22:40:43.81#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:43.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:40:43.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:40:43.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:40:43.93#ibcon#enter wrdev, iclass 18, count 0 2006.285.22:40:43.93#ibcon#first serial, iclass 18, count 0 2006.285.22:40:43.93#ibcon#enter sib2, iclass 18, count 0 2006.285.22:40:43.93#ibcon#flushed, iclass 18, count 0 2006.285.22:40:43.93#ibcon#about to write, iclass 18, count 0 2006.285.22:40:43.93#ibcon#wrote, iclass 18, count 0 2006.285.22:40:43.93#ibcon#about to read 3, iclass 18, count 0 2006.285.22:40:43.95#ibcon#read 3, iclass 18, count 0 2006.285.22:40:43.95#ibcon#about to read 4, iclass 18, count 0 2006.285.22:40:43.95#ibcon#read 4, iclass 18, count 0 2006.285.22:40:43.95#ibcon#about to read 5, iclass 18, count 0 2006.285.22:40:43.95#ibcon#read 5, iclass 18, count 0 2006.285.22:40:43.95#ibcon#about to read 6, iclass 18, count 0 2006.285.22:40:43.95#ibcon#read 6, iclass 18, count 0 2006.285.22:40:43.95#ibcon#end of sib2, iclass 18, count 0 2006.285.22:40:43.95#ibcon#*mode == 0, iclass 18, count 0 2006.285.22:40:43.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.22:40:43.95#ibcon#[25=USB\r\n] 2006.285.22:40:43.95#ibcon#*before write, iclass 18, count 0 2006.285.22:40:43.95#ibcon#enter sib2, iclass 18, count 0 2006.285.22:40:43.95#ibcon#flushed, iclass 18, count 0 2006.285.22:40:43.95#ibcon#about to write, iclass 18, count 0 2006.285.22:40:43.95#ibcon#wrote, iclass 18, count 0 2006.285.22:40:43.95#ibcon#about to read 3, iclass 18, count 0 2006.285.22:40:43.98#ibcon#read 3, iclass 18, count 0 2006.285.22:40:43.98#ibcon#about to read 4, iclass 18, count 0 2006.285.22:40:43.98#ibcon#read 4, iclass 18, count 0 2006.285.22:40:43.98#ibcon#about to read 5, iclass 18, count 0 2006.285.22:40:43.98#ibcon#read 5, iclass 18, count 0 2006.285.22:40:43.98#ibcon#about to read 6, iclass 18, count 0 2006.285.22:40:43.98#ibcon#read 6, iclass 18, count 0 2006.285.22:40:43.98#ibcon#end of sib2, iclass 18, count 0 2006.285.22:40:43.98#ibcon#*after write, iclass 18, count 0 2006.285.22:40:43.98#ibcon#*before return 0, iclass 18, count 0 2006.285.22:40:43.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:40:43.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:40:43.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.22:40:43.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.22:40:43.98$vck44/valo=7,864.99 2006.285.22:40:43.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.22:40:43.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.22:40:43.98#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:43.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:40:43.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:40:43.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:40:43.98#ibcon#enter wrdev, iclass 20, count 0 2006.285.22:40:43.98#ibcon#first serial, iclass 20, count 0 2006.285.22:40:43.98#ibcon#enter sib2, iclass 20, count 0 2006.285.22:40:43.98#ibcon#flushed, iclass 20, count 0 2006.285.22:40:43.98#ibcon#about to write, iclass 20, count 0 2006.285.22:40:43.98#ibcon#wrote, iclass 20, count 0 2006.285.22:40:43.98#ibcon#about to read 3, iclass 20, count 0 2006.285.22:40:44.00#ibcon#read 3, iclass 20, count 0 2006.285.22:40:44.00#ibcon#about to read 4, iclass 20, count 0 2006.285.22:40:44.00#ibcon#read 4, iclass 20, count 0 2006.285.22:40:44.00#ibcon#about to read 5, iclass 20, count 0 2006.285.22:40:44.00#ibcon#read 5, iclass 20, count 0 2006.285.22:40:44.00#ibcon#about to read 6, iclass 20, count 0 2006.285.22:40:44.00#ibcon#read 6, iclass 20, count 0 2006.285.22:40:44.00#ibcon#end of sib2, iclass 20, count 0 2006.285.22:40:44.00#ibcon#*mode == 0, iclass 20, count 0 2006.285.22:40:44.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.22:40:44.00#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:40:44.00#ibcon#*before write, iclass 20, count 0 2006.285.22:40:44.00#ibcon#enter sib2, iclass 20, count 0 2006.285.22:40:44.00#ibcon#flushed, iclass 20, count 0 2006.285.22:40:44.00#ibcon#about to write, iclass 20, count 0 2006.285.22:40:44.00#ibcon#wrote, iclass 20, count 0 2006.285.22:40:44.00#ibcon#about to read 3, iclass 20, count 0 2006.285.22:40:44.04#ibcon#read 3, iclass 20, count 0 2006.285.22:40:44.04#ibcon#about to read 4, iclass 20, count 0 2006.285.22:40:44.04#ibcon#read 4, iclass 20, count 0 2006.285.22:40:44.04#ibcon#about to read 5, iclass 20, count 0 2006.285.22:40:44.04#ibcon#read 5, iclass 20, count 0 2006.285.22:40:44.04#ibcon#about to read 6, iclass 20, count 0 2006.285.22:40:44.04#ibcon#read 6, iclass 20, count 0 2006.285.22:40:44.04#ibcon#end of sib2, iclass 20, count 0 2006.285.22:40:44.04#ibcon#*after write, iclass 20, count 0 2006.285.22:40:44.04#ibcon#*before return 0, iclass 20, count 0 2006.285.22:40:44.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:40:44.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:40:44.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.22:40:44.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.22:40:44.04$vck44/va=7,4 2006.285.22:40:44.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.22:40:44.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.22:40:44.04#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:44.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:40:44.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:40:44.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:40:44.10#ibcon#enter wrdev, iclass 22, count 2 2006.285.22:40:44.10#ibcon#first serial, iclass 22, count 2 2006.285.22:40:44.10#ibcon#enter sib2, iclass 22, count 2 2006.285.22:40:44.10#ibcon#flushed, iclass 22, count 2 2006.285.22:40:44.10#ibcon#about to write, iclass 22, count 2 2006.285.22:40:44.10#ibcon#wrote, iclass 22, count 2 2006.285.22:40:44.10#ibcon#about to read 3, iclass 22, count 2 2006.285.22:40:44.12#ibcon#read 3, iclass 22, count 2 2006.285.22:40:44.12#ibcon#about to read 4, iclass 22, count 2 2006.285.22:40:44.12#ibcon#read 4, iclass 22, count 2 2006.285.22:40:44.12#ibcon#about to read 5, iclass 22, count 2 2006.285.22:40:44.12#ibcon#read 5, iclass 22, count 2 2006.285.22:40:44.12#ibcon#about to read 6, iclass 22, count 2 2006.285.22:40:44.12#ibcon#read 6, iclass 22, count 2 2006.285.22:40:44.12#ibcon#end of sib2, iclass 22, count 2 2006.285.22:40:44.12#ibcon#*mode == 0, iclass 22, count 2 2006.285.22:40:44.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.22:40:44.12#ibcon#[25=AT07-04\r\n] 2006.285.22:40:44.12#ibcon#*before write, iclass 22, count 2 2006.285.22:40:44.12#ibcon#enter sib2, iclass 22, count 2 2006.285.22:40:44.12#ibcon#flushed, iclass 22, count 2 2006.285.22:40:44.12#ibcon#about to write, iclass 22, count 2 2006.285.22:40:44.12#ibcon#wrote, iclass 22, count 2 2006.285.22:40:44.12#ibcon#about to read 3, iclass 22, count 2 2006.285.22:40:44.15#ibcon#read 3, iclass 22, count 2 2006.285.22:40:44.15#ibcon#about to read 4, iclass 22, count 2 2006.285.22:40:44.15#ibcon#read 4, iclass 22, count 2 2006.285.22:40:44.15#ibcon#about to read 5, iclass 22, count 2 2006.285.22:40:44.15#ibcon#read 5, iclass 22, count 2 2006.285.22:40:44.15#ibcon#about to read 6, iclass 22, count 2 2006.285.22:40:44.15#ibcon#read 6, iclass 22, count 2 2006.285.22:40:44.15#ibcon#end of sib2, iclass 22, count 2 2006.285.22:40:44.15#ibcon#*after write, iclass 22, count 2 2006.285.22:40:44.15#ibcon#*before return 0, iclass 22, count 2 2006.285.22:40:44.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:40:44.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:40:44.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.22:40:44.15#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:44.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:40:44.27#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:40:44.27#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:40:44.27#ibcon#enter wrdev, iclass 22, count 0 2006.285.22:40:44.27#ibcon#first serial, iclass 22, count 0 2006.285.22:40:44.27#ibcon#enter sib2, iclass 22, count 0 2006.285.22:40:44.27#ibcon#flushed, iclass 22, count 0 2006.285.22:40:44.27#ibcon#about to write, iclass 22, count 0 2006.285.22:40:44.27#ibcon#wrote, iclass 22, count 0 2006.285.22:40:44.27#ibcon#about to read 3, iclass 22, count 0 2006.285.22:40:44.29#ibcon#read 3, iclass 22, count 0 2006.285.22:40:44.29#ibcon#about to read 4, iclass 22, count 0 2006.285.22:40:44.29#ibcon#read 4, iclass 22, count 0 2006.285.22:40:44.29#ibcon#about to read 5, iclass 22, count 0 2006.285.22:40:44.29#ibcon#read 5, iclass 22, count 0 2006.285.22:40:44.29#ibcon#about to read 6, iclass 22, count 0 2006.285.22:40:44.29#ibcon#read 6, iclass 22, count 0 2006.285.22:40:44.29#ibcon#end of sib2, iclass 22, count 0 2006.285.22:40:44.29#ibcon#*mode == 0, iclass 22, count 0 2006.285.22:40:44.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.22:40:44.29#ibcon#[25=USB\r\n] 2006.285.22:40:44.29#ibcon#*before write, iclass 22, count 0 2006.285.22:40:44.29#ibcon#enter sib2, iclass 22, count 0 2006.285.22:40:44.29#ibcon#flushed, iclass 22, count 0 2006.285.22:40:44.29#ibcon#about to write, iclass 22, count 0 2006.285.22:40:44.29#ibcon#wrote, iclass 22, count 0 2006.285.22:40:44.29#ibcon#about to read 3, iclass 22, count 0 2006.285.22:40:44.32#ibcon#read 3, iclass 22, count 0 2006.285.22:40:44.32#ibcon#about to read 4, iclass 22, count 0 2006.285.22:40:44.32#ibcon#read 4, iclass 22, count 0 2006.285.22:40:44.32#ibcon#about to read 5, iclass 22, count 0 2006.285.22:40:44.32#ibcon#read 5, iclass 22, count 0 2006.285.22:40:44.32#ibcon#about to read 6, iclass 22, count 0 2006.285.22:40:44.32#ibcon#read 6, iclass 22, count 0 2006.285.22:40:44.32#ibcon#end of sib2, iclass 22, count 0 2006.285.22:40:44.32#ibcon#*after write, iclass 22, count 0 2006.285.22:40:44.32#ibcon#*before return 0, iclass 22, count 0 2006.285.22:40:44.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:40:44.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:40:44.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.22:40:44.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.22:40:44.32$vck44/valo=8,884.99 2006.285.22:40:44.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.22:40:44.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.22:40:44.32#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:44.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:40:44.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:40:44.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:40:44.32#ibcon#enter wrdev, iclass 24, count 0 2006.285.22:40:44.32#ibcon#first serial, iclass 24, count 0 2006.285.22:40:44.32#ibcon#enter sib2, iclass 24, count 0 2006.285.22:40:44.32#ibcon#flushed, iclass 24, count 0 2006.285.22:40:44.32#ibcon#about to write, iclass 24, count 0 2006.285.22:40:44.32#ibcon#wrote, iclass 24, count 0 2006.285.22:40:44.32#ibcon#about to read 3, iclass 24, count 0 2006.285.22:40:44.34#ibcon#read 3, iclass 24, count 0 2006.285.22:40:44.34#ibcon#about to read 4, iclass 24, count 0 2006.285.22:40:44.34#ibcon#read 4, iclass 24, count 0 2006.285.22:40:44.34#ibcon#about to read 5, iclass 24, count 0 2006.285.22:40:44.34#ibcon#read 5, iclass 24, count 0 2006.285.22:40:44.34#ibcon#about to read 6, iclass 24, count 0 2006.285.22:40:44.34#ibcon#read 6, iclass 24, count 0 2006.285.22:40:44.34#ibcon#end of sib2, iclass 24, count 0 2006.285.22:40:44.34#ibcon#*mode == 0, iclass 24, count 0 2006.285.22:40:44.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.22:40:44.34#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:40:44.34#ibcon#*before write, iclass 24, count 0 2006.285.22:40:44.34#ibcon#enter sib2, iclass 24, count 0 2006.285.22:40:44.34#ibcon#flushed, iclass 24, count 0 2006.285.22:40:44.34#ibcon#about to write, iclass 24, count 0 2006.285.22:40:44.34#ibcon#wrote, iclass 24, count 0 2006.285.22:40:44.34#ibcon#about to read 3, iclass 24, count 0 2006.285.22:40:44.38#ibcon#read 3, iclass 24, count 0 2006.285.22:40:44.38#ibcon#about to read 4, iclass 24, count 0 2006.285.22:40:44.38#ibcon#read 4, iclass 24, count 0 2006.285.22:40:44.38#ibcon#about to read 5, iclass 24, count 0 2006.285.22:40:44.38#ibcon#read 5, iclass 24, count 0 2006.285.22:40:44.38#ibcon#about to read 6, iclass 24, count 0 2006.285.22:40:44.38#ibcon#read 6, iclass 24, count 0 2006.285.22:40:44.38#ibcon#end of sib2, iclass 24, count 0 2006.285.22:40:44.38#ibcon#*after write, iclass 24, count 0 2006.285.22:40:44.38#ibcon#*before return 0, iclass 24, count 0 2006.285.22:40:44.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:40:44.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:40:44.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.22:40:44.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.22:40:44.38$vck44/va=8,3 2006.285.22:40:44.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.22:40:44.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.22:40:44.38#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:44.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:40:44.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:40:44.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:40:44.44#ibcon#enter wrdev, iclass 26, count 2 2006.285.22:40:44.44#ibcon#first serial, iclass 26, count 2 2006.285.22:40:44.44#ibcon#enter sib2, iclass 26, count 2 2006.285.22:40:44.44#ibcon#flushed, iclass 26, count 2 2006.285.22:40:44.44#ibcon#about to write, iclass 26, count 2 2006.285.22:40:44.44#ibcon#wrote, iclass 26, count 2 2006.285.22:40:44.44#ibcon#about to read 3, iclass 26, count 2 2006.285.22:40:44.46#ibcon#read 3, iclass 26, count 2 2006.285.22:40:44.46#ibcon#about to read 4, iclass 26, count 2 2006.285.22:40:44.46#ibcon#read 4, iclass 26, count 2 2006.285.22:40:44.46#ibcon#about to read 5, iclass 26, count 2 2006.285.22:40:44.46#ibcon#read 5, iclass 26, count 2 2006.285.22:40:44.46#ibcon#about to read 6, iclass 26, count 2 2006.285.22:40:44.46#ibcon#read 6, iclass 26, count 2 2006.285.22:40:44.46#ibcon#end of sib2, iclass 26, count 2 2006.285.22:40:44.46#ibcon#*mode == 0, iclass 26, count 2 2006.285.22:40:44.46#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.22:40:44.46#ibcon#[25=AT08-03\r\n] 2006.285.22:40:44.46#ibcon#*before write, iclass 26, count 2 2006.285.22:40:44.46#ibcon#enter sib2, iclass 26, count 2 2006.285.22:40:44.46#ibcon#flushed, iclass 26, count 2 2006.285.22:40:44.46#ibcon#about to write, iclass 26, count 2 2006.285.22:40:44.46#ibcon#wrote, iclass 26, count 2 2006.285.22:40:44.46#ibcon#about to read 3, iclass 26, count 2 2006.285.22:40:44.49#ibcon#read 3, iclass 26, count 2 2006.285.22:40:44.49#ibcon#about to read 4, iclass 26, count 2 2006.285.22:40:44.49#ibcon#read 4, iclass 26, count 2 2006.285.22:40:44.49#ibcon#about to read 5, iclass 26, count 2 2006.285.22:40:44.49#ibcon#read 5, iclass 26, count 2 2006.285.22:40:44.49#ibcon#about to read 6, iclass 26, count 2 2006.285.22:40:44.49#ibcon#read 6, iclass 26, count 2 2006.285.22:40:44.49#ibcon#end of sib2, iclass 26, count 2 2006.285.22:40:44.49#ibcon#*after write, iclass 26, count 2 2006.285.22:40:44.49#ibcon#*before return 0, iclass 26, count 2 2006.285.22:40:44.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:40:44.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:40:44.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.22:40:44.49#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:44.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:40:44.61#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:40:44.61#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:40:44.61#ibcon#enter wrdev, iclass 26, count 0 2006.285.22:40:44.61#ibcon#first serial, iclass 26, count 0 2006.285.22:40:44.61#ibcon#enter sib2, iclass 26, count 0 2006.285.22:40:44.61#ibcon#flushed, iclass 26, count 0 2006.285.22:40:44.61#ibcon#about to write, iclass 26, count 0 2006.285.22:40:44.61#ibcon#wrote, iclass 26, count 0 2006.285.22:40:44.61#ibcon#about to read 3, iclass 26, count 0 2006.285.22:40:44.63#ibcon#read 3, iclass 26, count 0 2006.285.22:40:44.63#ibcon#about to read 4, iclass 26, count 0 2006.285.22:40:44.63#ibcon#read 4, iclass 26, count 0 2006.285.22:40:44.63#ibcon#about to read 5, iclass 26, count 0 2006.285.22:40:44.63#ibcon#read 5, iclass 26, count 0 2006.285.22:40:44.63#ibcon#about to read 6, iclass 26, count 0 2006.285.22:40:44.63#ibcon#read 6, iclass 26, count 0 2006.285.22:40:44.63#ibcon#end of sib2, iclass 26, count 0 2006.285.22:40:44.63#ibcon#*mode == 0, iclass 26, count 0 2006.285.22:40:44.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.22:40:44.63#ibcon#[25=USB\r\n] 2006.285.22:40:44.63#ibcon#*before write, iclass 26, count 0 2006.285.22:40:44.63#ibcon#enter sib2, iclass 26, count 0 2006.285.22:40:44.63#ibcon#flushed, iclass 26, count 0 2006.285.22:40:44.63#ibcon#about to write, iclass 26, count 0 2006.285.22:40:44.63#ibcon#wrote, iclass 26, count 0 2006.285.22:40:44.63#ibcon#about to read 3, iclass 26, count 0 2006.285.22:40:44.66#ibcon#read 3, iclass 26, count 0 2006.285.22:40:44.66#ibcon#about to read 4, iclass 26, count 0 2006.285.22:40:44.66#ibcon#read 4, iclass 26, count 0 2006.285.22:40:44.66#ibcon#about to read 5, iclass 26, count 0 2006.285.22:40:44.66#ibcon#read 5, iclass 26, count 0 2006.285.22:40:44.66#ibcon#about to read 6, iclass 26, count 0 2006.285.22:40:44.66#ibcon#read 6, iclass 26, count 0 2006.285.22:40:44.66#ibcon#end of sib2, iclass 26, count 0 2006.285.22:40:44.66#ibcon#*after write, iclass 26, count 0 2006.285.22:40:44.66#ibcon#*before return 0, iclass 26, count 0 2006.285.22:40:44.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:40:44.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:40:44.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.22:40:44.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.22:40:44.66$vck44/vblo=1,629.99 2006.285.22:40:44.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.22:40:44.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.22:40:44.66#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:44.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:40:44.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:40:44.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:40:44.66#ibcon#enter wrdev, iclass 28, count 0 2006.285.22:40:44.66#ibcon#first serial, iclass 28, count 0 2006.285.22:40:44.66#ibcon#enter sib2, iclass 28, count 0 2006.285.22:40:44.66#ibcon#flushed, iclass 28, count 0 2006.285.22:40:44.66#ibcon#about to write, iclass 28, count 0 2006.285.22:40:44.66#ibcon#wrote, iclass 28, count 0 2006.285.22:40:44.66#ibcon#about to read 3, iclass 28, count 0 2006.285.22:40:44.68#ibcon#read 3, iclass 28, count 0 2006.285.22:40:44.68#ibcon#about to read 4, iclass 28, count 0 2006.285.22:40:44.68#ibcon#read 4, iclass 28, count 0 2006.285.22:40:44.68#ibcon#about to read 5, iclass 28, count 0 2006.285.22:40:44.68#ibcon#read 5, iclass 28, count 0 2006.285.22:40:44.68#ibcon#about to read 6, iclass 28, count 0 2006.285.22:40:44.68#ibcon#read 6, iclass 28, count 0 2006.285.22:40:44.68#ibcon#end of sib2, iclass 28, count 0 2006.285.22:40:44.68#ibcon#*mode == 0, iclass 28, count 0 2006.285.22:40:44.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.22:40:44.68#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:40:44.68#ibcon#*before write, iclass 28, count 0 2006.285.22:40:44.68#ibcon#enter sib2, iclass 28, count 0 2006.285.22:40:44.68#ibcon#flushed, iclass 28, count 0 2006.285.22:40:44.68#ibcon#about to write, iclass 28, count 0 2006.285.22:40:44.68#ibcon#wrote, iclass 28, count 0 2006.285.22:40:44.68#ibcon#about to read 3, iclass 28, count 0 2006.285.22:40:44.72#ibcon#read 3, iclass 28, count 0 2006.285.22:40:44.72#ibcon#about to read 4, iclass 28, count 0 2006.285.22:40:44.72#ibcon#read 4, iclass 28, count 0 2006.285.22:40:44.72#ibcon#about to read 5, iclass 28, count 0 2006.285.22:40:44.72#ibcon#read 5, iclass 28, count 0 2006.285.22:40:44.72#ibcon#about to read 6, iclass 28, count 0 2006.285.22:40:44.72#ibcon#read 6, iclass 28, count 0 2006.285.22:40:44.72#ibcon#end of sib2, iclass 28, count 0 2006.285.22:40:44.72#ibcon#*after write, iclass 28, count 0 2006.285.22:40:44.72#ibcon#*before return 0, iclass 28, count 0 2006.285.22:40:44.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:40:44.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:40:44.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.22:40:44.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.22:40:44.72$vck44/vb=1,4 2006.285.22:40:44.72#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.22:40:44.72#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.22:40:44.72#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:44.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:40:44.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:40:44.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:40:44.72#ibcon#enter wrdev, iclass 30, count 2 2006.285.22:40:44.72#ibcon#first serial, iclass 30, count 2 2006.285.22:40:44.72#ibcon#enter sib2, iclass 30, count 2 2006.285.22:40:44.72#ibcon#flushed, iclass 30, count 2 2006.285.22:40:44.72#ibcon#about to write, iclass 30, count 2 2006.285.22:40:44.72#ibcon#wrote, iclass 30, count 2 2006.285.22:40:44.72#ibcon#about to read 3, iclass 30, count 2 2006.285.22:40:44.74#ibcon#read 3, iclass 30, count 2 2006.285.22:40:44.74#ibcon#about to read 4, iclass 30, count 2 2006.285.22:40:44.74#ibcon#read 4, iclass 30, count 2 2006.285.22:40:44.74#ibcon#about to read 5, iclass 30, count 2 2006.285.22:40:44.74#ibcon#read 5, iclass 30, count 2 2006.285.22:40:44.74#ibcon#about to read 6, iclass 30, count 2 2006.285.22:40:44.74#ibcon#read 6, iclass 30, count 2 2006.285.22:40:44.74#ibcon#end of sib2, iclass 30, count 2 2006.285.22:40:44.74#ibcon#*mode == 0, iclass 30, count 2 2006.285.22:40:44.74#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.22:40:44.74#ibcon#[27=AT01-04\r\n] 2006.285.22:40:44.74#ibcon#*before write, iclass 30, count 2 2006.285.22:40:44.74#ibcon#enter sib2, iclass 30, count 2 2006.285.22:40:44.74#ibcon#flushed, iclass 30, count 2 2006.285.22:40:44.74#ibcon#about to write, iclass 30, count 2 2006.285.22:40:44.74#ibcon#wrote, iclass 30, count 2 2006.285.22:40:44.74#ibcon#about to read 3, iclass 30, count 2 2006.285.22:40:44.77#ibcon#read 3, iclass 30, count 2 2006.285.22:40:44.77#ibcon#about to read 4, iclass 30, count 2 2006.285.22:40:44.77#ibcon#read 4, iclass 30, count 2 2006.285.22:40:44.77#ibcon#about to read 5, iclass 30, count 2 2006.285.22:40:44.77#ibcon#read 5, iclass 30, count 2 2006.285.22:40:44.77#ibcon#about to read 6, iclass 30, count 2 2006.285.22:40:44.77#ibcon#read 6, iclass 30, count 2 2006.285.22:40:44.77#ibcon#end of sib2, iclass 30, count 2 2006.285.22:40:44.77#ibcon#*after write, iclass 30, count 2 2006.285.22:40:44.77#ibcon#*before return 0, iclass 30, count 2 2006.285.22:40:44.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:40:44.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.22:40:44.77#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.22:40:44.77#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:44.77#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:40:44.89#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:40:44.89#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:40:44.89#ibcon#enter wrdev, iclass 30, count 0 2006.285.22:40:44.89#ibcon#first serial, iclass 30, count 0 2006.285.22:40:44.89#ibcon#enter sib2, iclass 30, count 0 2006.285.22:40:44.89#ibcon#flushed, iclass 30, count 0 2006.285.22:40:44.89#ibcon#about to write, iclass 30, count 0 2006.285.22:40:44.89#ibcon#wrote, iclass 30, count 0 2006.285.22:40:44.89#ibcon#about to read 3, iclass 30, count 0 2006.285.22:40:44.91#ibcon#read 3, iclass 30, count 0 2006.285.22:40:44.91#ibcon#about to read 4, iclass 30, count 0 2006.285.22:40:44.91#ibcon#read 4, iclass 30, count 0 2006.285.22:40:44.91#ibcon#about to read 5, iclass 30, count 0 2006.285.22:40:44.91#ibcon#read 5, iclass 30, count 0 2006.285.22:40:44.91#ibcon#about to read 6, iclass 30, count 0 2006.285.22:40:44.91#ibcon#read 6, iclass 30, count 0 2006.285.22:40:44.91#ibcon#end of sib2, iclass 30, count 0 2006.285.22:40:44.91#ibcon#*mode == 0, iclass 30, count 0 2006.285.22:40:44.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.22:40:44.91#ibcon#[27=USB\r\n] 2006.285.22:40:44.91#ibcon#*before write, iclass 30, count 0 2006.285.22:40:44.91#ibcon#enter sib2, iclass 30, count 0 2006.285.22:40:44.91#ibcon#flushed, iclass 30, count 0 2006.285.22:40:44.91#ibcon#about to write, iclass 30, count 0 2006.285.22:40:44.91#ibcon#wrote, iclass 30, count 0 2006.285.22:40:44.91#ibcon#about to read 3, iclass 30, count 0 2006.285.22:40:44.94#ibcon#read 3, iclass 30, count 0 2006.285.22:40:44.94#ibcon#about to read 4, iclass 30, count 0 2006.285.22:40:44.94#ibcon#read 4, iclass 30, count 0 2006.285.22:40:44.94#ibcon#about to read 5, iclass 30, count 0 2006.285.22:40:44.94#ibcon#read 5, iclass 30, count 0 2006.285.22:40:44.94#ibcon#about to read 6, iclass 30, count 0 2006.285.22:40:44.94#ibcon#read 6, iclass 30, count 0 2006.285.22:40:44.94#ibcon#end of sib2, iclass 30, count 0 2006.285.22:40:44.94#ibcon#*after write, iclass 30, count 0 2006.285.22:40:44.94#ibcon#*before return 0, iclass 30, count 0 2006.285.22:40:44.94#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:40:44.94#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.22:40:44.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.22:40:44.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.22:40:44.94$vck44/vblo=2,634.99 2006.285.22:40:44.94#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.22:40:44.94#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.22:40:44.94#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:44.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:40:44.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:40:44.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:40:44.94#ibcon#enter wrdev, iclass 32, count 0 2006.285.22:40:44.94#ibcon#first serial, iclass 32, count 0 2006.285.22:40:44.94#ibcon#enter sib2, iclass 32, count 0 2006.285.22:40:44.94#ibcon#flushed, iclass 32, count 0 2006.285.22:40:44.94#ibcon#about to write, iclass 32, count 0 2006.285.22:40:44.94#ibcon#wrote, iclass 32, count 0 2006.285.22:40:44.94#ibcon#about to read 3, iclass 32, count 0 2006.285.22:40:44.96#ibcon#read 3, iclass 32, count 0 2006.285.22:40:44.96#ibcon#about to read 4, iclass 32, count 0 2006.285.22:40:44.96#ibcon#read 4, iclass 32, count 0 2006.285.22:40:44.96#ibcon#about to read 5, iclass 32, count 0 2006.285.22:40:44.96#ibcon#read 5, iclass 32, count 0 2006.285.22:40:44.96#ibcon#about to read 6, iclass 32, count 0 2006.285.22:40:44.96#ibcon#read 6, iclass 32, count 0 2006.285.22:40:44.96#ibcon#end of sib2, iclass 32, count 0 2006.285.22:40:44.96#ibcon#*mode == 0, iclass 32, count 0 2006.285.22:40:44.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.22:40:44.96#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:40:44.96#ibcon#*before write, iclass 32, count 0 2006.285.22:40:44.96#ibcon#enter sib2, iclass 32, count 0 2006.285.22:40:44.96#ibcon#flushed, iclass 32, count 0 2006.285.22:40:44.96#ibcon#about to write, iclass 32, count 0 2006.285.22:40:44.96#ibcon#wrote, iclass 32, count 0 2006.285.22:40:44.96#ibcon#about to read 3, iclass 32, count 0 2006.285.22:40:45.00#ibcon#read 3, iclass 32, count 0 2006.285.22:40:45.00#ibcon#about to read 4, iclass 32, count 0 2006.285.22:40:45.00#ibcon#read 4, iclass 32, count 0 2006.285.22:40:45.00#ibcon#about to read 5, iclass 32, count 0 2006.285.22:40:45.00#ibcon#read 5, iclass 32, count 0 2006.285.22:40:45.00#ibcon#about to read 6, iclass 32, count 0 2006.285.22:40:45.00#ibcon#read 6, iclass 32, count 0 2006.285.22:40:45.00#ibcon#end of sib2, iclass 32, count 0 2006.285.22:40:45.00#ibcon#*after write, iclass 32, count 0 2006.285.22:40:45.00#ibcon#*before return 0, iclass 32, count 0 2006.285.22:40:45.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:40:45.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:40:45.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.22:40:45.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.22:40:45.00$vck44/vb=2,5 2006.285.22:40:45.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.22:40:45.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.22:40:45.00#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:45.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:40:45.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:40:45.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:40:45.06#ibcon#enter wrdev, iclass 34, count 2 2006.285.22:40:45.06#ibcon#first serial, iclass 34, count 2 2006.285.22:40:45.06#ibcon#enter sib2, iclass 34, count 2 2006.285.22:40:45.06#ibcon#flushed, iclass 34, count 2 2006.285.22:40:45.06#ibcon#about to write, iclass 34, count 2 2006.285.22:40:45.06#ibcon#wrote, iclass 34, count 2 2006.285.22:40:45.06#ibcon#about to read 3, iclass 34, count 2 2006.285.22:40:45.08#ibcon#read 3, iclass 34, count 2 2006.285.22:40:45.08#ibcon#about to read 4, iclass 34, count 2 2006.285.22:40:45.08#ibcon#read 4, iclass 34, count 2 2006.285.22:40:45.08#ibcon#about to read 5, iclass 34, count 2 2006.285.22:40:45.08#ibcon#read 5, iclass 34, count 2 2006.285.22:40:45.08#ibcon#about to read 6, iclass 34, count 2 2006.285.22:40:45.08#ibcon#read 6, iclass 34, count 2 2006.285.22:40:45.08#ibcon#end of sib2, iclass 34, count 2 2006.285.22:40:45.08#ibcon#*mode == 0, iclass 34, count 2 2006.285.22:40:45.08#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.22:40:45.08#ibcon#[27=AT02-05\r\n] 2006.285.22:40:45.08#ibcon#*before write, iclass 34, count 2 2006.285.22:40:45.08#ibcon#enter sib2, iclass 34, count 2 2006.285.22:40:45.08#ibcon#flushed, iclass 34, count 2 2006.285.22:40:45.08#ibcon#about to write, iclass 34, count 2 2006.285.22:40:45.08#ibcon#wrote, iclass 34, count 2 2006.285.22:40:45.08#ibcon#about to read 3, iclass 34, count 2 2006.285.22:40:45.11#ibcon#read 3, iclass 34, count 2 2006.285.22:40:45.11#ibcon#about to read 4, iclass 34, count 2 2006.285.22:40:45.11#ibcon#read 4, iclass 34, count 2 2006.285.22:40:45.11#ibcon#about to read 5, iclass 34, count 2 2006.285.22:40:45.11#ibcon#read 5, iclass 34, count 2 2006.285.22:40:45.11#ibcon#about to read 6, iclass 34, count 2 2006.285.22:40:45.11#ibcon#read 6, iclass 34, count 2 2006.285.22:40:45.11#ibcon#end of sib2, iclass 34, count 2 2006.285.22:40:45.11#ibcon#*after write, iclass 34, count 2 2006.285.22:40:45.11#ibcon#*before return 0, iclass 34, count 2 2006.285.22:40:45.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:40:45.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:40:45.11#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.22:40:45.11#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:45.11#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:40:45.23#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:40:45.23#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:40:45.23#ibcon#enter wrdev, iclass 34, count 0 2006.285.22:40:45.23#ibcon#first serial, iclass 34, count 0 2006.285.22:40:45.23#ibcon#enter sib2, iclass 34, count 0 2006.285.22:40:45.23#ibcon#flushed, iclass 34, count 0 2006.285.22:40:45.23#ibcon#about to write, iclass 34, count 0 2006.285.22:40:45.23#ibcon#wrote, iclass 34, count 0 2006.285.22:40:45.23#ibcon#about to read 3, iclass 34, count 0 2006.285.22:40:45.25#ibcon#read 3, iclass 34, count 0 2006.285.22:40:45.25#ibcon#about to read 4, iclass 34, count 0 2006.285.22:40:45.25#ibcon#read 4, iclass 34, count 0 2006.285.22:40:45.25#ibcon#about to read 5, iclass 34, count 0 2006.285.22:40:45.25#ibcon#read 5, iclass 34, count 0 2006.285.22:40:45.25#ibcon#about to read 6, iclass 34, count 0 2006.285.22:40:45.25#ibcon#read 6, iclass 34, count 0 2006.285.22:40:45.25#ibcon#end of sib2, iclass 34, count 0 2006.285.22:40:45.25#ibcon#*mode == 0, iclass 34, count 0 2006.285.22:40:45.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.22:40:45.25#ibcon#[27=USB\r\n] 2006.285.22:40:45.25#ibcon#*before write, iclass 34, count 0 2006.285.22:40:45.25#ibcon#enter sib2, iclass 34, count 0 2006.285.22:40:45.25#ibcon#flushed, iclass 34, count 0 2006.285.22:40:45.25#ibcon#about to write, iclass 34, count 0 2006.285.22:40:45.25#ibcon#wrote, iclass 34, count 0 2006.285.22:40:45.25#ibcon#about to read 3, iclass 34, count 0 2006.285.22:40:45.28#ibcon#read 3, iclass 34, count 0 2006.285.22:40:45.28#ibcon#about to read 4, iclass 34, count 0 2006.285.22:40:45.28#ibcon#read 4, iclass 34, count 0 2006.285.22:40:45.28#ibcon#about to read 5, iclass 34, count 0 2006.285.22:40:45.28#ibcon#read 5, iclass 34, count 0 2006.285.22:40:45.28#ibcon#about to read 6, iclass 34, count 0 2006.285.22:40:45.28#ibcon#read 6, iclass 34, count 0 2006.285.22:40:45.28#ibcon#end of sib2, iclass 34, count 0 2006.285.22:40:45.28#ibcon#*after write, iclass 34, count 0 2006.285.22:40:45.28#ibcon#*before return 0, iclass 34, count 0 2006.285.22:40:45.28#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:40:45.28#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:40:45.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.22:40:45.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.22:40:45.28$vck44/vblo=3,649.99 2006.285.22:40:45.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.22:40:45.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.22:40:45.28#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:45.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:40:45.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:40:45.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:40:45.28#ibcon#enter wrdev, iclass 36, count 0 2006.285.22:40:45.28#ibcon#first serial, iclass 36, count 0 2006.285.22:40:45.28#ibcon#enter sib2, iclass 36, count 0 2006.285.22:40:45.28#ibcon#flushed, iclass 36, count 0 2006.285.22:40:45.28#ibcon#about to write, iclass 36, count 0 2006.285.22:40:45.28#ibcon#wrote, iclass 36, count 0 2006.285.22:40:45.28#ibcon#about to read 3, iclass 36, count 0 2006.285.22:40:45.30#ibcon#read 3, iclass 36, count 0 2006.285.22:40:45.30#ibcon#about to read 4, iclass 36, count 0 2006.285.22:40:45.30#ibcon#read 4, iclass 36, count 0 2006.285.22:40:45.30#ibcon#about to read 5, iclass 36, count 0 2006.285.22:40:45.30#ibcon#read 5, iclass 36, count 0 2006.285.22:40:45.30#ibcon#about to read 6, iclass 36, count 0 2006.285.22:40:45.30#ibcon#read 6, iclass 36, count 0 2006.285.22:40:45.30#ibcon#end of sib2, iclass 36, count 0 2006.285.22:40:45.30#ibcon#*mode == 0, iclass 36, count 0 2006.285.22:40:45.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.22:40:45.30#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:40:45.30#ibcon#*before write, iclass 36, count 0 2006.285.22:40:45.30#ibcon#enter sib2, iclass 36, count 0 2006.285.22:40:45.30#ibcon#flushed, iclass 36, count 0 2006.285.22:40:45.30#ibcon#about to write, iclass 36, count 0 2006.285.22:40:45.30#ibcon#wrote, iclass 36, count 0 2006.285.22:40:45.30#ibcon#about to read 3, iclass 36, count 0 2006.285.22:40:45.34#ibcon#read 3, iclass 36, count 0 2006.285.22:40:45.34#ibcon#about to read 4, iclass 36, count 0 2006.285.22:40:45.34#ibcon#read 4, iclass 36, count 0 2006.285.22:40:45.34#ibcon#about to read 5, iclass 36, count 0 2006.285.22:40:45.34#ibcon#read 5, iclass 36, count 0 2006.285.22:40:45.34#ibcon#about to read 6, iclass 36, count 0 2006.285.22:40:45.34#ibcon#read 6, iclass 36, count 0 2006.285.22:40:45.34#ibcon#end of sib2, iclass 36, count 0 2006.285.22:40:45.34#ibcon#*after write, iclass 36, count 0 2006.285.22:40:45.34#ibcon#*before return 0, iclass 36, count 0 2006.285.22:40:45.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:40:45.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:40:45.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.22:40:45.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.22:40:45.34$vck44/vb=3,4 2006.285.22:40:45.34#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.22:40:45.34#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.22:40:45.34#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:45.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:40:45.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:40:45.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:40:45.40#ibcon#enter wrdev, iclass 38, count 2 2006.285.22:40:45.40#ibcon#first serial, iclass 38, count 2 2006.285.22:40:45.40#ibcon#enter sib2, iclass 38, count 2 2006.285.22:40:45.40#ibcon#flushed, iclass 38, count 2 2006.285.22:40:45.40#ibcon#about to write, iclass 38, count 2 2006.285.22:40:45.40#ibcon#wrote, iclass 38, count 2 2006.285.22:40:45.40#ibcon#about to read 3, iclass 38, count 2 2006.285.22:40:45.42#ibcon#read 3, iclass 38, count 2 2006.285.22:40:45.42#ibcon#about to read 4, iclass 38, count 2 2006.285.22:40:45.42#ibcon#read 4, iclass 38, count 2 2006.285.22:40:45.42#ibcon#about to read 5, iclass 38, count 2 2006.285.22:40:45.42#ibcon#read 5, iclass 38, count 2 2006.285.22:40:45.42#ibcon#about to read 6, iclass 38, count 2 2006.285.22:40:45.42#ibcon#read 6, iclass 38, count 2 2006.285.22:40:45.42#ibcon#end of sib2, iclass 38, count 2 2006.285.22:40:45.42#ibcon#*mode == 0, iclass 38, count 2 2006.285.22:40:45.42#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.22:40:45.42#ibcon#[27=AT03-04\r\n] 2006.285.22:40:45.42#ibcon#*before write, iclass 38, count 2 2006.285.22:40:45.42#ibcon#enter sib2, iclass 38, count 2 2006.285.22:40:45.42#ibcon#flushed, iclass 38, count 2 2006.285.22:40:45.42#ibcon#about to write, iclass 38, count 2 2006.285.22:40:45.42#ibcon#wrote, iclass 38, count 2 2006.285.22:40:45.42#ibcon#about to read 3, iclass 38, count 2 2006.285.22:40:45.45#ibcon#read 3, iclass 38, count 2 2006.285.22:40:45.45#ibcon#about to read 4, iclass 38, count 2 2006.285.22:40:45.45#ibcon#read 4, iclass 38, count 2 2006.285.22:40:45.45#ibcon#about to read 5, iclass 38, count 2 2006.285.22:40:45.45#ibcon#read 5, iclass 38, count 2 2006.285.22:40:45.45#ibcon#about to read 6, iclass 38, count 2 2006.285.22:40:45.45#ibcon#read 6, iclass 38, count 2 2006.285.22:40:45.45#ibcon#end of sib2, iclass 38, count 2 2006.285.22:40:45.45#ibcon#*after write, iclass 38, count 2 2006.285.22:40:45.45#ibcon#*before return 0, iclass 38, count 2 2006.285.22:40:45.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:40:45.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:40:45.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.22:40:45.45#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:45.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:40:45.53#abcon#<5=/05 0.9 2.0 17.20 961016.1\r\n> 2006.285.22:40:45.55#abcon#{5=INTERFACE CLEAR} 2006.285.22:40:45.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:40:45.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:40:45.57#ibcon#enter wrdev, iclass 38, count 0 2006.285.22:40:45.57#ibcon#first serial, iclass 38, count 0 2006.285.22:40:45.57#ibcon#enter sib2, iclass 38, count 0 2006.285.22:40:45.57#ibcon#flushed, iclass 38, count 0 2006.285.22:40:45.57#ibcon#about to write, iclass 38, count 0 2006.285.22:40:45.57#ibcon#wrote, iclass 38, count 0 2006.285.22:40:45.57#ibcon#about to read 3, iclass 38, count 0 2006.285.22:40:45.59#ibcon#read 3, iclass 38, count 0 2006.285.22:40:45.59#ibcon#about to read 4, iclass 38, count 0 2006.285.22:40:45.59#ibcon#read 4, iclass 38, count 0 2006.285.22:40:45.59#ibcon#about to read 5, iclass 38, count 0 2006.285.22:40:45.59#ibcon#read 5, iclass 38, count 0 2006.285.22:40:45.59#ibcon#about to read 6, iclass 38, count 0 2006.285.22:40:45.59#ibcon#read 6, iclass 38, count 0 2006.285.22:40:45.59#ibcon#end of sib2, iclass 38, count 0 2006.285.22:40:45.59#ibcon#*mode == 0, iclass 38, count 0 2006.285.22:40:45.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.22:40:45.59#ibcon#[27=USB\r\n] 2006.285.22:40:45.59#ibcon#*before write, iclass 38, count 0 2006.285.22:40:45.59#ibcon#enter sib2, iclass 38, count 0 2006.285.22:40:45.59#ibcon#flushed, iclass 38, count 0 2006.285.22:40:45.59#ibcon#about to write, iclass 38, count 0 2006.285.22:40:45.59#ibcon#wrote, iclass 38, count 0 2006.285.22:40:45.59#ibcon#about to read 3, iclass 38, count 0 2006.285.22:40:45.61#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:40:45.62#ibcon#read 3, iclass 38, count 0 2006.285.22:40:45.62#ibcon#about to read 4, iclass 38, count 0 2006.285.22:40:45.62#ibcon#read 4, iclass 38, count 0 2006.285.22:40:45.62#ibcon#about to read 5, iclass 38, count 0 2006.285.22:40:45.62#ibcon#read 5, iclass 38, count 0 2006.285.22:40:45.62#ibcon#about to read 6, iclass 38, count 0 2006.285.22:40:45.62#ibcon#read 6, iclass 38, count 0 2006.285.22:40:45.62#ibcon#end of sib2, iclass 38, count 0 2006.285.22:40:45.62#ibcon#*after write, iclass 38, count 0 2006.285.22:40:45.62#ibcon#*before return 0, iclass 38, count 0 2006.285.22:40:45.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:40:45.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:40:45.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.22:40:45.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.22:40:45.62$vck44/vblo=4,679.99 2006.285.22:40:45.62#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.22:40:45.62#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.22:40:45.62#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:45.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:40:45.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:40:45.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:40:45.62#ibcon#enter wrdev, iclass 6, count 0 2006.285.22:40:45.62#ibcon#first serial, iclass 6, count 0 2006.285.22:40:45.62#ibcon#enter sib2, iclass 6, count 0 2006.285.22:40:45.62#ibcon#flushed, iclass 6, count 0 2006.285.22:40:45.62#ibcon#about to write, iclass 6, count 0 2006.285.22:40:45.62#ibcon#wrote, iclass 6, count 0 2006.285.22:40:45.62#ibcon#about to read 3, iclass 6, count 0 2006.285.22:40:45.64#ibcon#read 3, iclass 6, count 0 2006.285.22:40:45.64#ibcon#about to read 4, iclass 6, count 0 2006.285.22:40:45.64#ibcon#read 4, iclass 6, count 0 2006.285.22:40:45.64#ibcon#about to read 5, iclass 6, count 0 2006.285.22:40:45.64#ibcon#read 5, iclass 6, count 0 2006.285.22:40:45.64#ibcon#about to read 6, iclass 6, count 0 2006.285.22:40:45.64#ibcon#read 6, iclass 6, count 0 2006.285.22:40:45.64#ibcon#end of sib2, iclass 6, count 0 2006.285.22:40:45.64#ibcon#*mode == 0, iclass 6, count 0 2006.285.22:40:45.64#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.22:40:45.64#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.22:40:45.64#ibcon#*before write, iclass 6, count 0 2006.285.22:40:45.64#ibcon#enter sib2, iclass 6, count 0 2006.285.22:40:45.64#ibcon#flushed, iclass 6, count 0 2006.285.22:40:45.64#ibcon#about to write, iclass 6, count 0 2006.285.22:40:45.64#ibcon#wrote, iclass 6, count 0 2006.285.22:40:45.64#ibcon#about to read 3, iclass 6, count 0 2006.285.22:40:45.68#ibcon#read 3, iclass 6, count 0 2006.285.22:40:45.68#ibcon#about to read 4, iclass 6, count 0 2006.285.22:40:45.68#ibcon#read 4, iclass 6, count 0 2006.285.22:40:45.68#ibcon#about to read 5, iclass 6, count 0 2006.285.22:40:45.68#ibcon#read 5, iclass 6, count 0 2006.285.22:40:45.68#ibcon#about to read 6, iclass 6, count 0 2006.285.22:40:45.68#ibcon#read 6, iclass 6, count 0 2006.285.22:40:45.68#ibcon#end of sib2, iclass 6, count 0 2006.285.22:40:45.68#ibcon#*after write, iclass 6, count 0 2006.285.22:40:45.68#ibcon#*before return 0, iclass 6, count 0 2006.285.22:40:45.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:40:45.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:40:45.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.22:40:45.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.22:40:45.68$vck44/vb=4,5 2006.285.22:40:45.68#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.22:40:45.68#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.22:40:45.68#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:45.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:40:45.74#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:40:45.74#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:40:45.74#ibcon#enter wrdev, iclass 10, count 2 2006.285.22:40:45.74#ibcon#first serial, iclass 10, count 2 2006.285.22:40:45.74#ibcon#enter sib2, iclass 10, count 2 2006.285.22:40:45.74#ibcon#flushed, iclass 10, count 2 2006.285.22:40:45.74#ibcon#about to write, iclass 10, count 2 2006.285.22:40:45.74#ibcon#wrote, iclass 10, count 2 2006.285.22:40:45.74#ibcon#about to read 3, iclass 10, count 2 2006.285.22:40:45.76#ibcon#read 3, iclass 10, count 2 2006.285.22:40:45.76#ibcon#about to read 4, iclass 10, count 2 2006.285.22:40:45.76#ibcon#read 4, iclass 10, count 2 2006.285.22:40:45.76#ibcon#about to read 5, iclass 10, count 2 2006.285.22:40:45.76#ibcon#read 5, iclass 10, count 2 2006.285.22:40:45.76#ibcon#about to read 6, iclass 10, count 2 2006.285.22:40:45.76#ibcon#read 6, iclass 10, count 2 2006.285.22:40:45.76#ibcon#end of sib2, iclass 10, count 2 2006.285.22:40:45.76#ibcon#*mode == 0, iclass 10, count 2 2006.285.22:40:45.76#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.22:40:45.76#ibcon#[27=AT04-05\r\n] 2006.285.22:40:45.76#ibcon#*before write, iclass 10, count 2 2006.285.22:40:45.76#ibcon#enter sib2, iclass 10, count 2 2006.285.22:40:45.76#ibcon#flushed, iclass 10, count 2 2006.285.22:40:45.76#ibcon#about to write, iclass 10, count 2 2006.285.22:40:45.76#ibcon#wrote, iclass 10, count 2 2006.285.22:40:45.76#ibcon#about to read 3, iclass 10, count 2 2006.285.22:40:45.79#ibcon#read 3, iclass 10, count 2 2006.285.22:40:45.79#ibcon#about to read 4, iclass 10, count 2 2006.285.22:40:45.79#ibcon#read 4, iclass 10, count 2 2006.285.22:40:45.79#ibcon#about to read 5, iclass 10, count 2 2006.285.22:40:45.79#ibcon#read 5, iclass 10, count 2 2006.285.22:40:45.79#ibcon#about to read 6, iclass 10, count 2 2006.285.22:40:45.79#ibcon#read 6, iclass 10, count 2 2006.285.22:40:45.79#ibcon#end of sib2, iclass 10, count 2 2006.285.22:40:45.79#ibcon#*after write, iclass 10, count 2 2006.285.22:40:45.79#ibcon#*before return 0, iclass 10, count 2 2006.285.22:40:45.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:40:45.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:40:45.79#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.22:40:45.79#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:45.79#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:40:45.91#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:40:45.91#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:40:45.91#ibcon#enter wrdev, iclass 10, count 0 2006.285.22:40:45.91#ibcon#first serial, iclass 10, count 0 2006.285.22:40:45.91#ibcon#enter sib2, iclass 10, count 0 2006.285.22:40:45.91#ibcon#flushed, iclass 10, count 0 2006.285.22:40:45.91#ibcon#about to write, iclass 10, count 0 2006.285.22:40:45.91#ibcon#wrote, iclass 10, count 0 2006.285.22:40:45.91#ibcon#about to read 3, iclass 10, count 0 2006.285.22:40:45.93#ibcon#read 3, iclass 10, count 0 2006.285.22:40:45.93#ibcon#about to read 4, iclass 10, count 0 2006.285.22:40:45.93#ibcon#read 4, iclass 10, count 0 2006.285.22:40:45.93#ibcon#about to read 5, iclass 10, count 0 2006.285.22:40:45.93#ibcon#read 5, iclass 10, count 0 2006.285.22:40:45.93#ibcon#about to read 6, iclass 10, count 0 2006.285.22:40:45.93#ibcon#read 6, iclass 10, count 0 2006.285.22:40:45.93#ibcon#end of sib2, iclass 10, count 0 2006.285.22:40:45.93#ibcon#*mode == 0, iclass 10, count 0 2006.285.22:40:45.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.22:40:45.93#ibcon#[27=USB\r\n] 2006.285.22:40:45.93#ibcon#*before write, iclass 10, count 0 2006.285.22:40:45.93#ibcon#enter sib2, iclass 10, count 0 2006.285.22:40:45.93#ibcon#flushed, iclass 10, count 0 2006.285.22:40:45.93#ibcon#about to write, iclass 10, count 0 2006.285.22:40:45.93#ibcon#wrote, iclass 10, count 0 2006.285.22:40:45.93#ibcon#about to read 3, iclass 10, count 0 2006.285.22:40:45.96#ibcon#read 3, iclass 10, count 0 2006.285.22:40:45.96#ibcon#about to read 4, iclass 10, count 0 2006.285.22:40:45.96#ibcon#read 4, iclass 10, count 0 2006.285.22:40:45.96#ibcon#about to read 5, iclass 10, count 0 2006.285.22:40:45.96#ibcon#read 5, iclass 10, count 0 2006.285.22:40:45.96#ibcon#about to read 6, iclass 10, count 0 2006.285.22:40:45.96#ibcon#read 6, iclass 10, count 0 2006.285.22:40:45.96#ibcon#end of sib2, iclass 10, count 0 2006.285.22:40:45.96#ibcon#*after write, iclass 10, count 0 2006.285.22:40:45.96#ibcon#*before return 0, iclass 10, count 0 2006.285.22:40:45.96#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:40:45.96#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:40:45.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.22:40:45.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.22:40:45.96$vck44/vblo=5,709.99 2006.285.22:40:45.96#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.22:40:45.96#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.22:40:45.96#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:45.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:40:45.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:40:45.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:40:45.96#ibcon#enter wrdev, iclass 12, count 0 2006.285.22:40:45.96#ibcon#first serial, iclass 12, count 0 2006.285.22:40:45.96#ibcon#enter sib2, iclass 12, count 0 2006.285.22:40:45.96#ibcon#flushed, iclass 12, count 0 2006.285.22:40:45.96#ibcon#about to write, iclass 12, count 0 2006.285.22:40:45.96#ibcon#wrote, iclass 12, count 0 2006.285.22:40:45.96#ibcon#about to read 3, iclass 12, count 0 2006.285.22:40:45.98#ibcon#read 3, iclass 12, count 0 2006.285.22:40:45.98#ibcon#about to read 4, iclass 12, count 0 2006.285.22:40:45.98#ibcon#read 4, iclass 12, count 0 2006.285.22:40:45.98#ibcon#about to read 5, iclass 12, count 0 2006.285.22:40:45.98#ibcon#read 5, iclass 12, count 0 2006.285.22:40:45.98#ibcon#about to read 6, iclass 12, count 0 2006.285.22:40:45.98#ibcon#read 6, iclass 12, count 0 2006.285.22:40:45.98#ibcon#end of sib2, iclass 12, count 0 2006.285.22:40:45.98#ibcon#*mode == 0, iclass 12, count 0 2006.285.22:40:45.98#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.22:40:45.98#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.22:40:45.98#ibcon#*before write, iclass 12, count 0 2006.285.22:40:45.98#ibcon#enter sib2, iclass 12, count 0 2006.285.22:40:45.98#ibcon#flushed, iclass 12, count 0 2006.285.22:40:45.98#ibcon#about to write, iclass 12, count 0 2006.285.22:40:45.98#ibcon#wrote, iclass 12, count 0 2006.285.22:40:45.98#ibcon#about to read 3, iclass 12, count 0 2006.285.22:40:46.02#ibcon#read 3, iclass 12, count 0 2006.285.22:40:46.02#ibcon#about to read 4, iclass 12, count 0 2006.285.22:40:46.02#ibcon#read 4, iclass 12, count 0 2006.285.22:40:46.02#ibcon#about to read 5, iclass 12, count 0 2006.285.22:40:46.02#ibcon#read 5, iclass 12, count 0 2006.285.22:40:46.02#ibcon#about to read 6, iclass 12, count 0 2006.285.22:40:46.02#ibcon#read 6, iclass 12, count 0 2006.285.22:40:46.02#ibcon#end of sib2, iclass 12, count 0 2006.285.22:40:46.02#ibcon#*after write, iclass 12, count 0 2006.285.22:40:46.02#ibcon#*before return 0, iclass 12, count 0 2006.285.22:40:46.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:40:46.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:40:46.02#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.22:40:46.02#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.22:40:46.02$vck44/vb=5,4 2006.285.22:40:46.02#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.22:40:46.02#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.22:40:46.02#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:46.02#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:40:46.08#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:40:46.08#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:40:46.08#ibcon#enter wrdev, iclass 14, count 2 2006.285.22:40:46.08#ibcon#first serial, iclass 14, count 2 2006.285.22:40:46.08#ibcon#enter sib2, iclass 14, count 2 2006.285.22:40:46.08#ibcon#flushed, iclass 14, count 2 2006.285.22:40:46.08#ibcon#about to write, iclass 14, count 2 2006.285.22:40:46.08#ibcon#wrote, iclass 14, count 2 2006.285.22:40:46.08#ibcon#about to read 3, iclass 14, count 2 2006.285.22:40:46.10#ibcon#read 3, iclass 14, count 2 2006.285.22:40:46.10#ibcon#about to read 4, iclass 14, count 2 2006.285.22:40:46.10#ibcon#read 4, iclass 14, count 2 2006.285.22:40:46.10#ibcon#about to read 5, iclass 14, count 2 2006.285.22:40:46.10#ibcon#read 5, iclass 14, count 2 2006.285.22:40:46.10#ibcon#about to read 6, iclass 14, count 2 2006.285.22:40:46.10#ibcon#read 6, iclass 14, count 2 2006.285.22:40:46.10#ibcon#end of sib2, iclass 14, count 2 2006.285.22:40:46.10#ibcon#*mode == 0, iclass 14, count 2 2006.285.22:40:46.10#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.22:40:46.10#ibcon#[27=AT05-04\r\n] 2006.285.22:40:46.10#ibcon#*before write, iclass 14, count 2 2006.285.22:40:46.10#ibcon#enter sib2, iclass 14, count 2 2006.285.22:40:46.10#ibcon#flushed, iclass 14, count 2 2006.285.22:40:46.10#ibcon#about to write, iclass 14, count 2 2006.285.22:40:46.10#ibcon#wrote, iclass 14, count 2 2006.285.22:40:46.10#ibcon#about to read 3, iclass 14, count 2 2006.285.22:40:46.13#ibcon#read 3, iclass 14, count 2 2006.285.22:40:46.13#ibcon#about to read 4, iclass 14, count 2 2006.285.22:40:46.13#ibcon#read 4, iclass 14, count 2 2006.285.22:40:46.13#ibcon#about to read 5, iclass 14, count 2 2006.285.22:40:46.13#ibcon#read 5, iclass 14, count 2 2006.285.22:40:46.13#ibcon#about to read 6, iclass 14, count 2 2006.285.22:40:46.13#ibcon#read 6, iclass 14, count 2 2006.285.22:40:46.13#ibcon#end of sib2, iclass 14, count 2 2006.285.22:40:46.13#ibcon#*after write, iclass 14, count 2 2006.285.22:40:46.13#ibcon#*before return 0, iclass 14, count 2 2006.285.22:40:46.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:40:46.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:40:46.13#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.22:40:46.13#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:46.13#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:40:46.25#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:40:46.25#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:40:46.25#ibcon#enter wrdev, iclass 14, count 0 2006.285.22:40:46.25#ibcon#first serial, iclass 14, count 0 2006.285.22:40:46.25#ibcon#enter sib2, iclass 14, count 0 2006.285.22:40:46.25#ibcon#flushed, iclass 14, count 0 2006.285.22:40:46.25#ibcon#about to write, iclass 14, count 0 2006.285.22:40:46.25#ibcon#wrote, iclass 14, count 0 2006.285.22:40:46.25#ibcon#about to read 3, iclass 14, count 0 2006.285.22:40:46.27#ibcon#read 3, iclass 14, count 0 2006.285.22:40:46.27#ibcon#about to read 4, iclass 14, count 0 2006.285.22:40:46.27#ibcon#read 4, iclass 14, count 0 2006.285.22:40:46.27#ibcon#about to read 5, iclass 14, count 0 2006.285.22:40:46.27#ibcon#read 5, iclass 14, count 0 2006.285.22:40:46.27#ibcon#about to read 6, iclass 14, count 0 2006.285.22:40:46.27#ibcon#read 6, iclass 14, count 0 2006.285.22:40:46.27#ibcon#end of sib2, iclass 14, count 0 2006.285.22:40:46.27#ibcon#*mode == 0, iclass 14, count 0 2006.285.22:40:46.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.22:40:46.27#ibcon#[27=USB\r\n] 2006.285.22:40:46.27#ibcon#*before write, iclass 14, count 0 2006.285.22:40:46.27#ibcon#enter sib2, iclass 14, count 0 2006.285.22:40:46.27#ibcon#flushed, iclass 14, count 0 2006.285.22:40:46.27#ibcon#about to write, iclass 14, count 0 2006.285.22:40:46.27#ibcon#wrote, iclass 14, count 0 2006.285.22:40:46.27#ibcon#about to read 3, iclass 14, count 0 2006.285.22:40:46.30#ibcon#read 3, iclass 14, count 0 2006.285.22:40:46.30#ibcon#about to read 4, iclass 14, count 0 2006.285.22:40:46.30#ibcon#read 4, iclass 14, count 0 2006.285.22:40:46.30#ibcon#about to read 5, iclass 14, count 0 2006.285.22:40:46.30#ibcon#read 5, iclass 14, count 0 2006.285.22:40:46.30#ibcon#about to read 6, iclass 14, count 0 2006.285.22:40:46.30#ibcon#read 6, iclass 14, count 0 2006.285.22:40:46.30#ibcon#end of sib2, iclass 14, count 0 2006.285.22:40:46.30#ibcon#*after write, iclass 14, count 0 2006.285.22:40:46.30#ibcon#*before return 0, iclass 14, count 0 2006.285.22:40:46.30#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:40:46.30#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:40:46.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.22:40:46.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.22:40:46.30$vck44/vblo=6,719.99 2006.285.22:40:46.30#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.22:40:46.30#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.22:40:46.30#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:46.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:40:46.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:40:46.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:40:46.30#ibcon#enter wrdev, iclass 16, count 0 2006.285.22:40:46.30#ibcon#first serial, iclass 16, count 0 2006.285.22:40:46.30#ibcon#enter sib2, iclass 16, count 0 2006.285.22:40:46.30#ibcon#flushed, iclass 16, count 0 2006.285.22:40:46.30#ibcon#about to write, iclass 16, count 0 2006.285.22:40:46.30#ibcon#wrote, iclass 16, count 0 2006.285.22:40:46.30#ibcon#about to read 3, iclass 16, count 0 2006.285.22:40:46.32#ibcon#read 3, iclass 16, count 0 2006.285.22:40:46.32#ibcon#about to read 4, iclass 16, count 0 2006.285.22:40:46.32#ibcon#read 4, iclass 16, count 0 2006.285.22:40:46.32#ibcon#about to read 5, iclass 16, count 0 2006.285.22:40:46.32#ibcon#read 5, iclass 16, count 0 2006.285.22:40:46.32#ibcon#about to read 6, iclass 16, count 0 2006.285.22:40:46.32#ibcon#read 6, iclass 16, count 0 2006.285.22:40:46.32#ibcon#end of sib2, iclass 16, count 0 2006.285.22:40:46.32#ibcon#*mode == 0, iclass 16, count 0 2006.285.22:40:46.32#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.22:40:46.32#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.22:40:46.32#ibcon#*before write, iclass 16, count 0 2006.285.22:40:46.32#ibcon#enter sib2, iclass 16, count 0 2006.285.22:40:46.32#ibcon#flushed, iclass 16, count 0 2006.285.22:40:46.32#ibcon#about to write, iclass 16, count 0 2006.285.22:40:46.32#ibcon#wrote, iclass 16, count 0 2006.285.22:40:46.32#ibcon#about to read 3, iclass 16, count 0 2006.285.22:40:46.36#ibcon#read 3, iclass 16, count 0 2006.285.22:40:46.36#ibcon#about to read 4, iclass 16, count 0 2006.285.22:40:46.36#ibcon#read 4, iclass 16, count 0 2006.285.22:40:46.36#ibcon#about to read 5, iclass 16, count 0 2006.285.22:40:46.36#ibcon#read 5, iclass 16, count 0 2006.285.22:40:46.36#ibcon#about to read 6, iclass 16, count 0 2006.285.22:40:46.36#ibcon#read 6, iclass 16, count 0 2006.285.22:40:46.36#ibcon#end of sib2, iclass 16, count 0 2006.285.22:40:46.36#ibcon#*after write, iclass 16, count 0 2006.285.22:40:46.36#ibcon#*before return 0, iclass 16, count 0 2006.285.22:40:46.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:40:46.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:40:46.36#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.22:40:46.36#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.22:40:46.36$vck44/vb=6,3 2006.285.22:40:46.36#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.22:40:46.36#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.22:40:46.36#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:46.36#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:40:46.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:40:46.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:40:46.42#ibcon#enter wrdev, iclass 18, count 2 2006.285.22:40:46.42#ibcon#first serial, iclass 18, count 2 2006.285.22:40:46.42#ibcon#enter sib2, iclass 18, count 2 2006.285.22:40:46.42#ibcon#flushed, iclass 18, count 2 2006.285.22:40:46.42#ibcon#about to write, iclass 18, count 2 2006.285.22:40:46.42#ibcon#wrote, iclass 18, count 2 2006.285.22:40:46.42#ibcon#about to read 3, iclass 18, count 2 2006.285.22:40:46.44#ibcon#read 3, iclass 18, count 2 2006.285.22:40:46.44#ibcon#about to read 4, iclass 18, count 2 2006.285.22:40:46.44#ibcon#read 4, iclass 18, count 2 2006.285.22:40:46.44#ibcon#about to read 5, iclass 18, count 2 2006.285.22:40:46.44#ibcon#read 5, iclass 18, count 2 2006.285.22:40:46.44#ibcon#about to read 6, iclass 18, count 2 2006.285.22:40:46.44#ibcon#read 6, iclass 18, count 2 2006.285.22:40:46.44#ibcon#end of sib2, iclass 18, count 2 2006.285.22:40:46.44#ibcon#*mode == 0, iclass 18, count 2 2006.285.22:40:46.44#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.22:40:46.44#ibcon#[27=AT06-03\r\n] 2006.285.22:40:46.44#ibcon#*before write, iclass 18, count 2 2006.285.22:40:46.44#ibcon#enter sib2, iclass 18, count 2 2006.285.22:40:46.44#ibcon#flushed, iclass 18, count 2 2006.285.22:40:46.44#ibcon#about to write, iclass 18, count 2 2006.285.22:40:46.44#ibcon#wrote, iclass 18, count 2 2006.285.22:40:46.44#ibcon#about to read 3, iclass 18, count 2 2006.285.22:40:46.47#ibcon#read 3, iclass 18, count 2 2006.285.22:40:46.47#ibcon#about to read 4, iclass 18, count 2 2006.285.22:40:46.47#ibcon#read 4, iclass 18, count 2 2006.285.22:40:46.47#ibcon#about to read 5, iclass 18, count 2 2006.285.22:40:46.47#ibcon#read 5, iclass 18, count 2 2006.285.22:40:46.47#ibcon#about to read 6, iclass 18, count 2 2006.285.22:40:46.47#ibcon#read 6, iclass 18, count 2 2006.285.22:40:46.47#ibcon#end of sib2, iclass 18, count 2 2006.285.22:40:46.47#ibcon#*after write, iclass 18, count 2 2006.285.22:40:46.47#ibcon#*before return 0, iclass 18, count 2 2006.285.22:40:46.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:40:46.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:40:46.47#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.22:40:46.47#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:46.47#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:40:46.59#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:40:46.59#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:40:46.59#ibcon#enter wrdev, iclass 18, count 0 2006.285.22:40:46.59#ibcon#first serial, iclass 18, count 0 2006.285.22:40:46.59#ibcon#enter sib2, iclass 18, count 0 2006.285.22:40:46.59#ibcon#flushed, iclass 18, count 0 2006.285.22:40:46.59#ibcon#about to write, iclass 18, count 0 2006.285.22:40:46.59#ibcon#wrote, iclass 18, count 0 2006.285.22:40:46.59#ibcon#about to read 3, iclass 18, count 0 2006.285.22:40:46.61#ibcon#read 3, iclass 18, count 0 2006.285.22:40:46.61#ibcon#about to read 4, iclass 18, count 0 2006.285.22:40:46.61#ibcon#read 4, iclass 18, count 0 2006.285.22:40:46.61#ibcon#about to read 5, iclass 18, count 0 2006.285.22:40:46.61#ibcon#read 5, iclass 18, count 0 2006.285.22:40:46.61#ibcon#about to read 6, iclass 18, count 0 2006.285.22:40:46.61#ibcon#read 6, iclass 18, count 0 2006.285.22:40:46.61#ibcon#end of sib2, iclass 18, count 0 2006.285.22:40:46.61#ibcon#*mode == 0, iclass 18, count 0 2006.285.22:40:46.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.22:40:46.61#ibcon#[27=USB\r\n] 2006.285.22:40:46.61#ibcon#*before write, iclass 18, count 0 2006.285.22:40:46.61#ibcon#enter sib2, iclass 18, count 0 2006.285.22:40:46.61#ibcon#flushed, iclass 18, count 0 2006.285.22:40:46.61#ibcon#about to write, iclass 18, count 0 2006.285.22:40:46.61#ibcon#wrote, iclass 18, count 0 2006.285.22:40:46.61#ibcon#about to read 3, iclass 18, count 0 2006.285.22:40:46.64#ibcon#read 3, iclass 18, count 0 2006.285.22:40:46.64#ibcon#about to read 4, iclass 18, count 0 2006.285.22:40:46.64#ibcon#read 4, iclass 18, count 0 2006.285.22:40:46.64#ibcon#about to read 5, iclass 18, count 0 2006.285.22:40:46.64#ibcon#read 5, iclass 18, count 0 2006.285.22:40:46.64#ibcon#about to read 6, iclass 18, count 0 2006.285.22:40:46.64#ibcon#read 6, iclass 18, count 0 2006.285.22:40:46.64#ibcon#end of sib2, iclass 18, count 0 2006.285.22:40:46.64#ibcon#*after write, iclass 18, count 0 2006.285.22:40:46.64#ibcon#*before return 0, iclass 18, count 0 2006.285.22:40:46.64#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:40:46.64#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:40:46.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.22:40:46.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.22:40:46.64$vck44/vblo=7,734.99 2006.285.22:40:46.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.22:40:46.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.22:40:46.64#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:46.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:40:46.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:40:46.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:40:46.64#ibcon#enter wrdev, iclass 20, count 0 2006.285.22:40:46.64#ibcon#first serial, iclass 20, count 0 2006.285.22:40:46.64#ibcon#enter sib2, iclass 20, count 0 2006.285.22:40:46.64#ibcon#flushed, iclass 20, count 0 2006.285.22:40:46.64#ibcon#about to write, iclass 20, count 0 2006.285.22:40:46.64#ibcon#wrote, iclass 20, count 0 2006.285.22:40:46.64#ibcon#about to read 3, iclass 20, count 0 2006.285.22:40:46.66#ibcon#read 3, iclass 20, count 0 2006.285.22:40:46.66#ibcon#about to read 4, iclass 20, count 0 2006.285.22:40:46.66#ibcon#read 4, iclass 20, count 0 2006.285.22:40:46.66#ibcon#about to read 5, iclass 20, count 0 2006.285.22:40:46.66#ibcon#read 5, iclass 20, count 0 2006.285.22:40:46.66#ibcon#about to read 6, iclass 20, count 0 2006.285.22:40:46.66#ibcon#read 6, iclass 20, count 0 2006.285.22:40:46.66#ibcon#end of sib2, iclass 20, count 0 2006.285.22:40:46.66#ibcon#*mode == 0, iclass 20, count 0 2006.285.22:40:46.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.22:40:46.66#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.22:40:46.66#ibcon#*before write, iclass 20, count 0 2006.285.22:40:46.66#ibcon#enter sib2, iclass 20, count 0 2006.285.22:40:46.66#ibcon#flushed, iclass 20, count 0 2006.285.22:40:46.66#ibcon#about to write, iclass 20, count 0 2006.285.22:40:46.66#ibcon#wrote, iclass 20, count 0 2006.285.22:40:46.66#ibcon#about to read 3, iclass 20, count 0 2006.285.22:40:46.70#ibcon#read 3, iclass 20, count 0 2006.285.22:40:46.70#ibcon#about to read 4, iclass 20, count 0 2006.285.22:40:46.70#ibcon#read 4, iclass 20, count 0 2006.285.22:40:46.70#ibcon#about to read 5, iclass 20, count 0 2006.285.22:40:46.70#ibcon#read 5, iclass 20, count 0 2006.285.22:40:46.70#ibcon#about to read 6, iclass 20, count 0 2006.285.22:40:46.70#ibcon#read 6, iclass 20, count 0 2006.285.22:40:46.70#ibcon#end of sib2, iclass 20, count 0 2006.285.22:40:46.70#ibcon#*after write, iclass 20, count 0 2006.285.22:40:46.70#ibcon#*before return 0, iclass 20, count 0 2006.285.22:40:46.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:40:46.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:40:46.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.22:40:46.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.22:40:46.70$vck44/vb=7,4 2006.285.22:40:46.70#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.22:40:46.70#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.22:40:46.70#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:46.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:40:46.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:40:46.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:40:46.76#ibcon#enter wrdev, iclass 22, count 2 2006.285.22:40:46.76#ibcon#first serial, iclass 22, count 2 2006.285.22:40:46.76#ibcon#enter sib2, iclass 22, count 2 2006.285.22:40:46.76#ibcon#flushed, iclass 22, count 2 2006.285.22:40:46.76#ibcon#about to write, iclass 22, count 2 2006.285.22:40:46.76#ibcon#wrote, iclass 22, count 2 2006.285.22:40:46.76#ibcon#about to read 3, iclass 22, count 2 2006.285.22:40:46.78#ibcon#read 3, iclass 22, count 2 2006.285.22:40:46.78#ibcon#about to read 4, iclass 22, count 2 2006.285.22:40:46.78#ibcon#read 4, iclass 22, count 2 2006.285.22:40:46.78#ibcon#about to read 5, iclass 22, count 2 2006.285.22:40:46.78#ibcon#read 5, iclass 22, count 2 2006.285.22:40:46.78#ibcon#about to read 6, iclass 22, count 2 2006.285.22:40:46.78#ibcon#read 6, iclass 22, count 2 2006.285.22:40:46.78#ibcon#end of sib2, iclass 22, count 2 2006.285.22:40:46.78#ibcon#*mode == 0, iclass 22, count 2 2006.285.22:40:46.78#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.22:40:46.78#ibcon#[27=AT07-04\r\n] 2006.285.22:40:46.78#ibcon#*before write, iclass 22, count 2 2006.285.22:40:46.78#ibcon#enter sib2, iclass 22, count 2 2006.285.22:40:46.78#ibcon#flushed, iclass 22, count 2 2006.285.22:40:46.78#ibcon#about to write, iclass 22, count 2 2006.285.22:40:46.78#ibcon#wrote, iclass 22, count 2 2006.285.22:40:46.78#ibcon#about to read 3, iclass 22, count 2 2006.285.22:40:46.81#ibcon#read 3, iclass 22, count 2 2006.285.22:40:46.81#ibcon#about to read 4, iclass 22, count 2 2006.285.22:40:46.81#ibcon#read 4, iclass 22, count 2 2006.285.22:40:46.81#ibcon#about to read 5, iclass 22, count 2 2006.285.22:40:46.81#ibcon#read 5, iclass 22, count 2 2006.285.22:40:46.81#ibcon#about to read 6, iclass 22, count 2 2006.285.22:40:46.81#ibcon#read 6, iclass 22, count 2 2006.285.22:40:46.81#ibcon#end of sib2, iclass 22, count 2 2006.285.22:40:46.81#ibcon#*after write, iclass 22, count 2 2006.285.22:40:46.81#ibcon#*before return 0, iclass 22, count 2 2006.285.22:40:46.81#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:40:46.81#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:40:46.81#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.22:40:46.81#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:46.81#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:40:46.93#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:40:46.93#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:40:46.93#ibcon#enter wrdev, iclass 22, count 0 2006.285.22:40:46.93#ibcon#first serial, iclass 22, count 0 2006.285.22:40:46.93#ibcon#enter sib2, iclass 22, count 0 2006.285.22:40:46.93#ibcon#flushed, iclass 22, count 0 2006.285.22:40:46.93#ibcon#about to write, iclass 22, count 0 2006.285.22:40:46.93#ibcon#wrote, iclass 22, count 0 2006.285.22:40:46.93#ibcon#about to read 3, iclass 22, count 0 2006.285.22:40:46.95#ibcon#read 3, iclass 22, count 0 2006.285.22:40:46.95#ibcon#about to read 4, iclass 22, count 0 2006.285.22:40:46.95#ibcon#read 4, iclass 22, count 0 2006.285.22:40:46.95#ibcon#about to read 5, iclass 22, count 0 2006.285.22:40:46.95#ibcon#read 5, iclass 22, count 0 2006.285.22:40:46.95#ibcon#about to read 6, iclass 22, count 0 2006.285.22:40:46.95#ibcon#read 6, iclass 22, count 0 2006.285.22:40:46.95#ibcon#end of sib2, iclass 22, count 0 2006.285.22:40:46.95#ibcon#*mode == 0, iclass 22, count 0 2006.285.22:40:46.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.22:40:46.95#ibcon#[27=USB\r\n] 2006.285.22:40:46.95#ibcon#*before write, iclass 22, count 0 2006.285.22:40:46.95#ibcon#enter sib2, iclass 22, count 0 2006.285.22:40:46.95#ibcon#flushed, iclass 22, count 0 2006.285.22:40:46.95#ibcon#about to write, iclass 22, count 0 2006.285.22:40:46.95#ibcon#wrote, iclass 22, count 0 2006.285.22:40:46.95#ibcon#about to read 3, iclass 22, count 0 2006.285.22:40:46.98#ibcon#read 3, iclass 22, count 0 2006.285.22:40:46.98#ibcon#about to read 4, iclass 22, count 0 2006.285.22:40:46.98#ibcon#read 4, iclass 22, count 0 2006.285.22:40:46.98#ibcon#about to read 5, iclass 22, count 0 2006.285.22:40:46.98#ibcon#read 5, iclass 22, count 0 2006.285.22:40:46.98#ibcon#about to read 6, iclass 22, count 0 2006.285.22:40:46.98#ibcon#read 6, iclass 22, count 0 2006.285.22:40:46.98#ibcon#end of sib2, iclass 22, count 0 2006.285.22:40:46.98#ibcon#*after write, iclass 22, count 0 2006.285.22:40:46.98#ibcon#*before return 0, iclass 22, count 0 2006.285.22:40:46.98#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:40:46.98#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:40:46.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.22:40:46.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.22:40:46.98$vck44/vblo=8,744.99 2006.285.22:40:46.98#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.22:40:46.98#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.22:40:46.98#ibcon#ireg 17 cls_cnt 0 2006.285.22:40:46.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:40:46.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:40:46.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:40:46.98#ibcon#enter wrdev, iclass 24, count 0 2006.285.22:40:46.98#ibcon#first serial, iclass 24, count 0 2006.285.22:40:46.98#ibcon#enter sib2, iclass 24, count 0 2006.285.22:40:46.98#ibcon#flushed, iclass 24, count 0 2006.285.22:40:46.98#ibcon#about to write, iclass 24, count 0 2006.285.22:40:46.98#ibcon#wrote, iclass 24, count 0 2006.285.22:40:46.98#ibcon#about to read 3, iclass 24, count 0 2006.285.22:40:47.00#ibcon#read 3, iclass 24, count 0 2006.285.22:40:47.00#ibcon#about to read 4, iclass 24, count 0 2006.285.22:40:47.00#ibcon#read 4, iclass 24, count 0 2006.285.22:40:47.00#ibcon#about to read 5, iclass 24, count 0 2006.285.22:40:47.00#ibcon#read 5, iclass 24, count 0 2006.285.22:40:47.00#ibcon#about to read 6, iclass 24, count 0 2006.285.22:40:47.00#ibcon#read 6, iclass 24, count 0 2006.285.22:40:47.00#ibcon#end of sib2, iclass 24, count 0 2006.285.22:40:47.00#ibcon#*mode == 0, iclass 24, count 0 2006.285.22:40:47.00#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.22:40:47.00#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.22:40:47.00#ibcon#*before write, iclass 24, count 0 2006.285.22:40:47.00#ibcon#enter sib2, iclass 24, count 0 2006.285.22:40:47.00#ibcon#flushed, iclass 24, count 0 2006.285.22:40:47.00#ibcon#about to write, iclass 24, count 0 2006.285.22:40:47.00#ibcon#wrote, iclass 24, count 0 2006.285.22:40:47.00#ibcon#about to read 3, iclass 24, count 0 2006.285.22:40:47.04#ibcon#read 3, iclass 24, count 0 2006.285.22:40:47.04#ibcon#about to read 4, iclass 24, count 0 2006.285.22:40:47.04#ibcon#read 4, iclass 24, count 0 2006.285.22:40:47.04#ibcon#about to read 5, iclass 24, count 0 2006.285.22:40:47.04#ibcon#read 5, iclass 24, count 0 2006.285.22:40:47.04#ibcon#about to read 6, iclass 24, count 0 2006.285.22:40:47.04#ibcon#read 6, iclass 24, count 0 2006.285.22:40:47.04#ibcon#end of sib2, iclass 24, count 0 2006.285.22:40:47.04#ibcon#*after write, iclass 24, count 0 2006.285.22:40:47.04#ibcon#*before return 0, iclass 24, count 0 2006.285.22:40:47.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:40:47.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:40:47.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.22:40:47.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.22:40:47.04$vck44/vb=8,4 2006.285.22:40:47.04#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.22:40:47.04#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.22:40:47.04#ibcon#ireg 11 cls_cnt 2 2006.285.22:40:47.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:40:47.10#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:40:47.10#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:40:47.10#ibcon#enter wrdev, iclass 26, count 2 2006.285.22:40:47.10#ibcon#first serial, iclass 26, count 2 2006.285.22:40:47.10#ibcon#enter sib2, iclass 26, count 2 2006.285.22:40:47.10#ibcon#flushed, iclass 26, count 2 2006.285.22:40:47.10#ibcon#about to write, iclass 26, count 2 2006.285.22:40:47.10#ibcon#wrote, iclass 26, count 2 2006.285.22:40:47.10#ibcon#about to read 3, iclass 26, count 2 2006.285.22:40:47.12#ibcon#read 3, iclass 26, count 2 2006.285.22:40:47.12#ibcon#about to read 4, iclass 26, count 2 2006.285.22:40:47.12#ibcon#read 4, iclass 26, count 2 2006.285.22:40:47.12#ibcon#about to read 5, iclass 26, count 2 2006.285.22:40:47.12#ibcon#read 5, iclass 26, count 2 2006.285.22:40:47.12#ibcon#about to read 6, iclass 26, count 2 2006.285.22:40:47.12#ibcon#read 6, iclass 26, count 2 2006.285.22:40:47.12#ibcon#end of sib2, iclass 26, count 2 2006.285.22:40:47.12#ibcon#*mode == 0, iclass 26, count 2 2006.285.22:40:47.12#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.22:40:47.12#ibcon#[27=AT08-04\r\n] 2006.285.22:40:47.12#ibcon#*before write, iclass 26, count 2 2006.285.22:40:47.12#ibcon#enter sib2, iclass 26, count 2 2006.285.22:40:47.12#ibcon#flushed, iclass 26, count 2 2006.285.22:40:47.12#ibcon#about to write, iclass 26, count 2 2006.285.22:40:47.12#ibcon#wrote, iclass 26, count 2 2006.285.22:40:47.12#ibcon#about to read 3, iclass 26, count 2 2006.285.22:40:47.15#ibcon#read 3, iclass 26, count 2 2006.285.22:40:47.15#ibcon#about to read 4, iclass 26, count 2 2006.285.22:40:47.15#ibcon#read 4, iclass 26, count 2 2006.285.22:40:47.15#ibcon#about to read 5, iclass 26, count 2 2006.285.22:40:47.15#ibcon#read 5, iclass 26, count 2 2006.285.22:40:47.15#ibcon#about to read 6, iclass 26, count 2 2006.285.22:40:47.15#ibcon#read 6, iclass 26, count 2 2006.285.22:40:47.15#ibcon#end of sib2, iclass 26, count 2 2006.285.22:40:47.15#ibcon#*after write, iclass 26, count 2 2006.285.22:40:47.15#ibcon#*before return 0, iclass 26, count 2 2006.285.22:40:47.15#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:40:47.15#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.22:40:47.15#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.22:40:47.15#ibcon#ireg 7 cls_cnt 0 2006.285.22:40:47.15#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:40:47.27#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:40:47.27#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:40:47.27#ibcon#enter wrdev, iclass 26, count 0 2006.285.22:40:47.27#ibcon#first serial, iclass 26, count 0 2006.285.22:40:47.27#ibcon#enter sib2, iclass 26, count 0 2006.285.22:40:47.27#ibcon#flushed, iclass 26, count 0 2006.285.22:40:47.27#ibcon#about to write, iclass 26, count 0 2006.285.22:40:47.27#ibcon#wrote, iclass 26, count 0 2006.285.22:40:47.27#ibcon#about to read 3, iclass 26, count 0 2006.285.22:40:47.29#ibcon#read 3, iclass 26, count 0 2006.285.22:40:47.29#ibcon#about to read 4, iclass 26, count 0 2006.285.22:40:47.29#ibcon#read 4, iclass 26, count 0 2006.285.22:40:47.29#ibcon#about to read 5, iclass 26, count 0 2006.285.22:40:47.29#ibcon#read 5, iclass 26, count 0 2006.285.22:40:47.29#ibcon#about to read 6, iclass 26, count 0 2006.285.22:40:47.29#ibcon#read 6, iclass 26, count 0 2006.285.22:40:47.29#ibcon#end of sib2, iclass 26, count 0 2006.285.22:40:47.29#ibcon#*mode == 0, iclass 26, count 0 2006.285.22:40:47.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.22:40:47.29#ibcon#[27=USB\r\n] 2006.285.22:40:47.29#ibcon#*before write, iclass 26, count 0 2006.285.22:40:47.29#ibcon#enter sib2, iclass 26, count 0 2006.285.22:40:47.29#ibcon#flushed, iclass 26, count 0 2006.285.22:40:47.29#ibcon#about to write, iclass 26, count 0 2006.285.22:40:47.29#ibcon#wrote, iclass 26, count 0 2006.285.22:40:47.29#ibcon#about to read 3, iclass 26, count 0 2006.285.22:40:47.32#ibcon#read 3, iclass 26, count 0 2006.285.22:40:47.32#ibcon#about to read 4, iclass 26, count 0 2006.285.22:40:47.32#ibcon#read 4, iclass 26, count 0 2006.285.22:40:47.32#ibcon#about to read 5, iclass 26, count 0 2006.285.22:40:47.32#ibcon#read 5, iclass 26, count 0 2006.285.22:40:47.32#ibcon#about to read 6, iclass 26, count 0 2006.285.22:40:47.32#ibcon#read 6, iclass 26, count 0 2006.285.22:40:47.32#ibcon#end of sib2, iclass 26, count 0 2006.285.22:40:47.32#ibcon#*after write, iclass 26, count 0 2006.285.22:40:47.32#ibcon#*before return 0, iclass 26, count 0 2006.285.22:40:47.32#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:40:47.32#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.22:40:47.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.22:40:47.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.22:40:47.32$vck44/vabw=wide 2006.285.22:40:47.32#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.22:40:47.32#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.22:40:47.32#ibcon#ireg 8 cls_cnt 0 2006.285.22:40:47.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:40:47.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:40:47.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:40:47.32#ibcon#enter wrdev, iclass 28, count 0 2006.285.22:40:47.32#ibcon#first serial, iclass 28, count 0 2006.285.22:40:47.32#ibcon#enter sib2, iclass 28, count 0 2006.285.22:40:47.32#ibcon#flushed, iclass 28, count 0 2006.285.22:40:47.32#ibcon#about to write, iclass 28, count 0 2006.285.22:40:47.32#ibcon#wrote, iclass 28, count 0 2006.285.22:40:47.32#ibcon#about to read 3, iclass 28, count 0 2006.285.22:40:47.34#ibcon#read 3, iclass 28, count 0 2006.285.22:40:47.34#ibcon#about to read 4, iclass 28, count 0 2006.285.22:40:47.34#ibcon#read 4, iclass 28, count 0 2006.285.22:40:47.34#ibcon#about to read 5, iclass 28, count 0 2006.285.22:40:47.34#ibcon#read 5, iclass 28, count 0 2006.285.22:40:47.34#ibcon#about to read 6, iclass 28, count 0 2006.285.22:40:47.34#ibcon#read 6, iclass 28, count 0 2006.285.22:40:47.34#ibcon#end of sib2, iclass 28, count 0 2006.285.22:40:47.34#ibcon#*mode == 0, iclass 28, count 0 2006.285.22:40:47.34#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.22:40:47.34#ibcon#[25=BW32\r\n] 2006.285.22:40:47.34#ibcon#*before write, iclass 28, count 0 2006.285.22:40:47.34#ibcon#enter sib2, iclass 28, count 0 2006.285.22:40:47.34#ibcon#flushed, iclass 28, count 0 2006.285.22:40:47.34#ibcon#about to write, iclass 28, count 0 2006.285.22:40:47.34#ibcon#wrote, iclass 28, count 0 2006.285.22:40:47.34#ibcon#about to read 3, iclass 28, count 0 2006.285.22:40:47.37#ibcon#read 3, iclass 28, count 0 2006.285.22:40:47.37#ibcon#about to read 4, iclass 28, count 0 2006.285.22:40:47.37#ibcon#read 4, iclass 28, count 0 2006.285.22:40:47.37#ibcon#about to read 5, iclass 28, count 0 2006.285.22:40:47.37#ibcon#read 5, iclass 28, count 0 2006.285.22:40:47.37#ibcon#about to read 6, iclass 28, count 0 2006.285.22:40:47.37#ibcon#read 6, iclass 28, count 0 2006.285.22:40:47.37#ibcon#end of sib2, iclass 28, count 0 2006.285.22:40:47.37#ibcon#*after write, iclass 28, count 0 2006.285.22:40:47.37#ibcon#*before return 0, iclass 28, count 0 2006.285.22:40:47.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:40:47.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.22:40:47.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.22:40:47.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.22:40:47.37$vck44/vbbw=wide 2006.285.22:40:47.37#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.22:40:47.37#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.22:40:47.37#ibcon#ireg 8 cls_cnt 0 2006.285.22:40:47.37#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:40:47.44#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:40:47.44#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:40:47.44#ibcon#enter wrdev, iclass 30, count 0 2006.285.22:40:47.44#ibcon#first serial, iclass 30, count 0 2006.285.22:40:47.44#ibcon#enter sib2, iclass 30, count 0 2006.285.22:40:47.44#ibcon#flushed, iclass 30, count 0 2006.285.22:40:47.44#ibcon#about to write, iclass 30, count 0 2006.285.22:40:47.44#ibcon#wrote, iclass 30, count 0 2006.285.22:40:47.44#ibcon#about to read 3, iclass 30, count 0 2006.285.22:40:47.46#ibcon#read 3, iclass 30, count 0 2006.285.22:40:47.46#ibcon#about to read 4, iclass 30, count 0 2006.285.22:40:47.46#ibcon#read 4, iclass 30, count 0 2006.285.22:40:47.46#ibcon#about to read 5, iclass 30, count 0 2006.285.22:40:47.46#ibcon#read 5, iclass 30, count 0 2006.285.22:40:47.46#ibcon#about to read 6, iclass 30, count 0 2006.285.22:40:47.46#ibcon#read 6, iclass 30, count 0 2006.285.22:40:47.46#ibcon#end of sib2, iclass 30, count 0 2006.285.22:40:47.46#ibcon#*mode == 0, iclass 30, count 0 2006.285.22:40:47.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.22:40:47.46#ibcon#[27=BW32\r\n] 2006.285.22:40:47.46#ibcon#*before write, iclass 30, count 0 2006.285.22:40:47.46#ibcon#enter sib2, iclass 30, count 0 2006.285.22:40:47.46#ibcon#flushed, iclass 30, count 0 2006.285.22:40:47.46#ibcon#about to write, iclass 30, count 0 2006.285.22:40:47.46#ibcon#wrote, iclass 30, count 0 2006.285.22:40:47.46#ibcon#about to read 3, iclass 30, count 0 2006.285.22:40:47.49#ibcon#read 3, iclass 30, count 0 2006.285.22:40:47.49#ibcon#about to read 4, iclass 30, count 0 2006.285.22:40:47.49#ibcon#read 4, iclass 30, count 0 2006.285.22:40:47.49#ibcon#about to read 5, iclass 30, count 0 2006.285.22:40:47.49#ibcon#read 5, iclass 30, count 0 2006.285.22:40:47.49#ibcon#about to read 6, iclass 30, count 0 2006.285.22:40:47.49#ibcon#read 6, iclass 30, count 0 2006.285.22:40:47.49#ibcon#end of sib2, iclass 30, count 0 2006.285.22:40:47.49#ibcon#*after write, iclass 30, count 0 2006.285.22:40:47.49#ibcon#*before return 0, iclass 30, count 0 2006.285.22:40:47.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:40:47.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.22:40:47.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.22:40:47.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.22:40:47.49$setupk4/ifdk4 2006.285.22:40:47.49$ifdk4/lo= 2006.285.22:40:47.49$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.22:40:47.49$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.22:40:47.49$ifdk4/patch= 2006.285.22:40:47.50$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.22:40:47.50$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.22:40:47.50$setupk4/!*+20s 2006.285.22:40:55.70#abcon#<5=/05 0.9 2.0 17.21 961016.1\r\n> 2006.285.22:40:55.72#abcon#{5=INTERFACE CLEAR} 2006.285.22:40:55.78#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:41:02.01$setupk4/"tpicd 2006.285.22:41:02.01$setupk4/echo=off 2006.285.22:41:02.01$setupk4/xlog=off 2006.285.22:41:02.01:!2006.285.22:45:45 2006.285.22:41:33.14#trakl#Source acquired 2006.285.22:41:33.14#flagr#flagr/antenna,acquired 2006.285.22:45:45.00:preob 2006.285.22:45:46.14/onsource/TRACKING 2006.285.22:45:46.14:!2006.285.22:45:55 2006.285.22:45:55.00:"tape 2006.285.22:45:55.00:"st=record 2006.285.22:45:55.00:data_valid=on 2006.285.22:45:55.00:midob 2006.285.22:45:55.14/onsource/TRACKING 2006.285.22:45:55.14/wx/17.53,1016.1,93 2006.285.22:45:55.34/cable/+6.5095E-03 2006.285.22:45:56.43/va/01,07,usb,yes,35,38 2006.285.22:45:56.43/va/02,06,usb,yes,35,36 2006.285.22:45:56.43/va/03,07,usb,yes,35,37 2006.285.22:45:56.43/va/04,06,usb,yes,36,38 2006.285.22:45:56.43/va/05,03,usb,yes,35,36 2006.285.22:45:56.43/va/06,04,usb,yes,32,31 2006.285.22:45:56.43/va/07,04,usb,yes,32,33 2006.285.22:45:56.43/va/08,03,usb,yes,33,40 2006.285.22:45:56.66/valo/01,524.99,yes,locked 2006.285.22:45:56.66/valo/02,534.99,yes,locked 2006.285.22:45:56.66/valo/03,564.99,yes,locked 2006.285.22:45:56.66/valo/04,624.99,yes,locked 2006.285.22:45:56.66/valo/05,734.99,yes,locked 2006.285.22:45:56.66/valo/06,814.99,yes,locked 2006.285.22:45:56.66/valo/07,864.99,yes,locked 2006.285.22:45:56.66/valo/08,884.99,yes,locked 2006.285.22:45:57.75/vb/01,04,usb,yes,38,35 2006.285.22:45:57.75/vb/02,05,usb,yes,36,35 2006.285.22:45:57.75/vb/03,04,usb,yes,42,41 2006.285.22:45:57.75/vb/04,05,usb,yes,37,42 2006.285.22:45:57.75/vb/05,04,usb,yes,33,36 2006.285.22:45:57.75/vb/06,03,usb,yes,46,42 2006.285.22:45:57.75/vb/07,04,usb,yes,37,38 2006.285.22:45:57.75/vb/08,04,usb,yes,34,38 2006.285.22:45:57.98/vblo/01,629.99,yes,locked 2006.285.22:45:57.98/vblo/02,634.99,yes,locked 2006.285.22:45:57.98/vblo/03,649.99,yes,locked 2006.285.22:45:57.98/vblo/04,679.99,yes,locked 2006.285.22:45:57.98/vblo/05,709.99,yes,locked 2006.285.22:45:57.98/vblo/06,719.99,yes,locked 2006.285.22:45:57.98/vblo/07,734.99,yes,locked 2006.285.22:45:57.98/vblo/08,744.99,yes,locked 2006.285.22:45:58.13/vabw/8 2006.285.22:45:58.28/vbbw/8 2006.285.22:45:58.37/xfe/off,on,12.0 2006.285.22:45:58.76/ifatt/23,28,28,28 2006.285.22:45:59.07/fmout-gps/S +2.62E-07 2006.285.22:45:59.09:!2006.285.22:47:25 2006.285.22:47:25.00:data_valid=off 2006.285.22:47:25.00:"et 2006.285.22:47:25.00:!+3s 2006.285.22:47:28.01:"tape 2006.285.22:47:28.01:postob 2006.285.22:47:28.07/cable/+6.5104E-03 2006.285.22:47:28.07/wx/17.64,1016.1,92 2006.285.22:47:29.07/fmout-gps/S +2.65E-07 2006.285.22:47:29.07:scan_name=285-2249,jd0610,290 2006.285.22:47:29.07:source=oj287,085448.87,200630.6,2000.0,cw 2006.285.22:47:29.14#flagr#flagr/antenna,new-source 2006.285.22:47:30.14:checkk5 2006.285.22:47:30.51/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:47:30.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:47:31.30/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:47:31.64/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:47:32.19/chk_obsdata//k5ts1/T2852245??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.285.22:47:32.58/chk_obsdata//k5ts2/T2852245??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.285.22:47:32.97/chk_obsdata//k5ts3/T2852245??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.285.22:47:33.35/chk_obsdata//k5ts4/T2852245??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.285.22:47:34.40/k5log//k5ts1_log_newline 2006.285.22:47:35.15/k5log//k5ts2_log_newline 2006.285.22:47:35.85/k5log//k5ts3_log_newline 2006.285.22:47:36.66/k5log//k5ts4_log_newline 2006.285.22:47:36.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:47:36.68:setupk4=1 2006.285.22:47:36.68$setupk4/echo=on 2006.285.22:47:36.68$setupk4/pcalon 2006.285.22:47:36.68$pcalon/"no phase cal control is implemented here 2006.285.22:47:36.68$setupk4/"tpicd=stop 2006.285.22:47:36.68$setupk4/"rec=synch_on 2006.285.22:47:36.68$setupk4/"rec_mode=128 2006.285.22:47:36.68$setupk4/!* 2006.285.22:47:36.68$setupk4/recpk4 2006.285.22:47:36.68$recpk4/recpatch= 2006.285.22:47:36.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:47:36.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:47:36.68$setupk4/vck44 2006.285.22:47:36.68$vck44/valo=1,524.99 2006.285.22:47:36.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.22:47:36.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.22:47:36.68#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:36.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:47:36.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:47:36.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:47:36.68#ibcon#enter wrdev, iclass 15, count 0 2006.285.22:47:36.68#ibcon#first serial, iclass 15, count 0 2006.285.22:47:36.68#ibcon#enter sib2, iclass 15, count 0 2006.285.22:47:36.68#ibcon#flushed, iclass 15, count 0 2006.285.22:47:36.68#ibcon#about to write, iclass 15, count 0 2006.285.22:47:36.68#ibcon#wrote, iclass 15, count 0 2006.285.22:47:36.68#ibcon#about to read 3, iclass 15, count 0 2006.285.22:47:36.70#ibcon#read 3, iclass 15, count 0 2006.285.22:47:36.70#ibcon#about to read 4, iclass 15, count 0 2006.285.22:47:36.70#ibcon#read 4, iclass 15, count 0 2006.285.22:47:36.70#ibcon#about to read 5, iclass 15, count 0 2006.285.22:47:36.70#ibcon#read 5, iclass 15, count 0 2006.285.22:47:36.70#ibcon#about to read 6, iclass 15, count 0 2006.285.22:47:36.70#ibcon#read 6, iclass 15, count 0 2006.285.22:47:36.70#ibcon#end of sib2, iclass 15, count 0 2006.285.22:47:36.70#ibcon#*mode == 0, iclass 15, count 0 2006.285.22:47:36.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.22:47:36.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:47:36.70#ibcon#*before write, iclass 15, count 0 2006.285.22:47:36.70#ibcon#enter sib2, iclass 15, count 0 2006.285.22:47:36.70#ibcon#flushed, iclass 15, count 0 2006.285.22:47:36.70#ibcon#about to write, iclass 15, count 0 2006.285.22:47:36.70#ibcon#wrote, iclass 15, count 0 2006.285.22:47:36.70#ibcon#about to read 3, iclass 15, count 0 2006.285.22:47:36.75#ibcon#read 3, iclass 15, count 0 2006.285.22:47:36.75#ibcon#about to read 4, iclass 15, count 0 2006.285.22:47:36.75#ibcon#read 4, iclass 15, count 0 2006.285.22:47:36.75#ibcon#about to read 5, iclass 15, count 0 2006.285.22:47:36.75#ibcon#read 5, iclass 15, count 0 2006.285.22:47:36.75#ibcon#about to read 6, iclass 15, count 0 2006.285.22:47:36.75#ibcon#read 6, iclass 15, count 0 2006.285.22:47:36.75#ibcon#end of sib2, iclass 15, count 0 2006.285.22:47:36.75#ibcon#*after write, iclass 15, count 0 2006.285.22:47:36.75#ibcon#*before return 0, iclass 15, count 0 2006.285.22:47:36.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:47:36.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:47:36.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.22:47:36.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.22:47:36.75$vck44/va=1,7 2006.285.22:47:36.75#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.22:47:36.75#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.22:47:36.75#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:36.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:47:36.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:47:36.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:47:36.75#ibcon#enter wrdev, iclass 17, count 2 2006.285.22:47:36.75#ibcon#first serial, iclass 17, count 2 2006.285.22:47:36.75#ibcon#enter sib2, iclass 17, count 2 2006.285.22:47:36.75#ibcon#flushed, iclass 17, count 2 2006.285.22:47:36.75#ibcon#about to write, iclass 17, count 2 2006.285.22:47:36.75#ibcon#wrote, iclass 17, count 2 2006.285.22:47:36.75#ibcon#about to read 3, iclass 17, count 2 2006.285.22:47:36.77#ibcon#read 3, iclass 17, count 2 2006.285.22:47:36.77#ibcon#about to read 4, iclass 17, count 2 2006.285.22:47:36.77#ibcon#read 4, iclass 17, count 2 2006.285.22:47:36.77#ibcon#about to read 5, iclass 17, count 2 2006.285.22:47:36.77#ibcon#read 5, iclass 17, count 2 2006.285.22:47:36.77#ibcon#about to read 6, iclass 17, count 2 2006.285.22:47:36.77#ibcon#read 6, iclass 17, count 2 2006.285.22:47:36.77#ibcon#end of sib2, iclass 17, count 2 2006.285.22:47:36.77#ibcon#*mode == 0, iclass 17, count 2 2006.285.22:47:36.77#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.22:47:36.77#ibcon#[25=AT01-07\r\n] 2006.285.22:47:36.77#ibcon#*before write, iclass 17, count 2 2006.285.22:47:36.77#ibcon#enter sib2, iclass 17, count 2 2006.285.22:47:36.77#ibcon#flushed, iclass 17, count 2 2006.285.22:47:36.77#ibcon#about to write, iclass 17, count 2 2006.285.22:47:36.77#ibcon#wrote, iclass 17, count 2 2006.285.22:47:36.77#ibcon#about to read 3, iclass 17, count 2 2006.285.22:47:36.80#ibcon#read 3, iclass 17, count 2 2006.285.22:47:36.80#ibcon#about to read 4, iclass 17, count 2 2006.285.22:47:36.80#ibcon#read 4, iclass 17, count 2 2006.285.22:47:36.80#ibcon#about to read 5, iclass 17, count 2 2006.285.22:47:36.80#ibcon#read 5, iclass 17, count 2 2006.285.22:47:36.80#ibcon#about to read 6, iclass 17, count 2 2006.285.22:47:36.80#ibcon#read 6, iclass 17, count 2 2006.285.22:47:36.80#ibcon#end of sib2, iclass 17, count 2 2006.285.22:47:36.80#ibcon#*after write, iclass 17, count 2 2006.285.22:47:36.80#ibcon#*before return 0, iclass 17, count 2 2006.285.22:47:36.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:47:36.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:47:36.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.22:47:36.80#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:36.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:47:36.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:47:36.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:47:36.92#ibcon#enter wrdev, iclass 17, count 0 2006.285.22:47:36.92#ibcon#first serial, iclass 17, count 0 2006.285.22:47:36.92#ibcon#enter sib2, iclass 17, count 0 2006.285.22:47:36.92#ibcon#flushed, iclass 17, count 0 2006.285.22:47:36.92#ibcon#about to write, iclass 17, count 0 2006.285.22:47:36.92#ibcon#wrote, iclass 17, count 0 2006.285.22:47:36.92#ibcon#about to read 3, iclass 17, count 0 2006.285.22:47:36.94#ibcon#read 3, iclass 17, count 0 2006.285.22:47:36.94#ibcon#about to read 4, iclass 17, count 0 2006.285.22:47:36.94#ibcon#read 4, iclass 17, count 0 2006.285.22:47:36.94#ibcon#about to read 5, iclass 17, count 0 2006.285.22:47:36.94#ibcon#read 5, iclass 17, count 0 2006.285.22:47:36.94#ibcon#about to read 6, iclass 17, count 0 2006.285.22:47:36.94#ibcon#read 6, iclass 17, count 0 2006.285.22:47:36.94#ibcon#end of sib2, iclass 17, count 0 2006.285.22:47:36.94#ibcon#*mode == 0, iclass 17, count 0 2006.285.22:47:36.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.22:47:36.94#ibcon#[25=USB\r\n] 2006.285.22:47:36.94#ibcon#*before write, iclass 17, count 0 2006.285.22:47:36.94#ibcon#enter sib2, iclass 17, count 0 2006.285.22:47:36.94#ibcon#flushed, iclass 17, count 0 2006.285.22:47:36.94#ibcon#about to write, iclass 17, count 0 2006.285.22:47:36.94#ibcon#wrote, iclass 17, count 0 2006.285.22:47:36.94#ibcon#about to read 3, iclass 17, count 0 2006.285.22:47:36.97#ibcon#read 3, iclass 17, count 0 2006.285.22:47:36.97#ibcon#about to read 4, iclass 17, count 0 2006.285.22:47:36.97#ibcon#read 4, iclass 17, count 0 2006.285.22:47:36.97#ibcon#about to read 5, iclass 17, count 0 2006.285.22:47:36.97#ibcon#read 5, iclass 17, count 0 2006.285.22:47:36.97#ibcon#about to read 6, iclass 17, count 0 2006.285.22:47:36.97#ibcon#read 6, iclass 17, count 0 2006.285.22:47:36.97#ibcon#end of sib2, iclass 17, count 0 2006.285.22:47:36.97#ibcon#*after write, iclass 17, count 0 2006.285.22:47:36.97#ibcon#*before return 0, iclass 17, count 0 2006.285.22:47:36.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:47:36.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:47:36.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.22:47:36.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.22:47:36.97$vck44/valo=2,534.99 2006.285.22:47:36.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.22:47:36.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.22:47:36.97#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:36.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:47:36.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:47:36.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:47:36.97#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:47:36.97#ibcon#first serial, iclass 19, count 0 2006.285.22:47:36.97#ibcon#enter sib2, iclass 19, count 0 2006.285.22:47:36.97#ibcon#flushed, iclass 19, count 0 2006.285.22:47:36.97#ibcon#about to write, iclass 19, count 0 2006.285.22:47:36.97#ibcon#wrote, iclass 19, count 0 2006.285.22:47:36.97#ibcon#about to read 3, iclass 19, count 0 2006.285.22:47:36.99#ibcon#read 3, iclass 19, count 0 2006.285.22:47:36.99#ibcon#about to read 4, iclass 19, count 0 2006.285.22:47:36.99#ibcon#read 4, iclass 19, count 0 2006.285.22:47:36.99#ibcon#about to read 5, iclass 19, count 0 2006.285.22:47:36.99#ibcon#read 5, iclass 19, count 0 2006.285.22:47:36.99#ibcon#about to read 6, iclass 19, count 0 2006.285.22:47:36.99#ibcon#read 6, iclass 19, count 0 2006.285.22:47:36.99#ibcon#end of sib2, iclass 19, count 0 2006.285.22:47:36.99#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:47:36.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:47:36.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:47:36.99#ibcon#*before write, iclass 19, count 0 2006.285.22:47:36.99#ibcon#enter sib2, iclass 19, count 0 2006.285.22:47:36.99#ibcon#flushed, iclass 19, count 0 2006.285.22:47:36.99#ibcon#about to write, iclass 19, count 0 2006.285.22:47:36.99#ibcon#wrote, iclass 19, count 0 2006.285.22:47:36.99#ibcon#about to read 3, iclass 19, count 0 2006.285.22:47:37.03#ibcon#read 3, iclass 19, count 0 2006.285.22:47:37.03#ibcon#about to read 4, iclass 19, count 0 2006.285.22:47:37.03#ibcon#read 4, iclass 19, count 0 2006.285.22:47:37.03#ibcon#about to read 5, iclass 19, count 0 2006.285.22:47:37.03#ibcon#read 5, iclass 19, count 0 2006.285.22:47:37.03#ibcon#about to read 6, iclass 19, count 0 2006.285.22:47:37.03#ibcon#read 6, iclass 19, count 0 2006.285.22:47:37.03#ibcon#end of sib2, iclass 19, count 0 2006.285.22:47:37.03#ibcon#*after write, iclass 19, count 0 2006.285.22:47:37.03#ibcon#*before return 0, iclass 19, count 0 2006.285.22:47:37.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:47:37.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:47:37.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:47:37.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:47:37.03$vck44/va=2,6 2006.285.22:47:37.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.22:47:37.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.22:47:37.03#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:37.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:47:37.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:47:37.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:47:37.09#ibcon#enter wrdev, iclass 21, count 2 2006.285.22:47:37.09#ibcon#first serial, iclass 21, count 2 2006.285.22:47:37.09#ibcon#enter sib2, iclass 21, count 2 2006.285.22:47:37.09#ibcon#flushed, iclass 21, count 2 2006.285.22:47:37.09#ibcon#about to write, iclass 21, count 2 2006.285.22:47:37.09#ibcon#wrote, iclass 21, count 2 2006.285.22:47:37.09#ibcon#about to read 3, iclass 21, count 2 2006.285.22:47:37.11#ibcon#read 3, iclass 21, count 2 2006.285.22:47:37.11#ibcon#about to read 4, iclass 21, count 2 2006.285.22:47:37.11#ibcon#read 4, iclass 21, count 2 2006.285.22:47:37.11#ibcon#about to read 5, iclass 21, count 2 2006.285.22:47:37.11#ibcon#read 5, iclass 21, count 2 2006.285.22:47:37.11#ibcon#about to read 6, iclass 21, count 2 2006.285.22:47:37.11#ibcon#read 6, iclass 21, count 2 2006.285.22:47:37.11#ibcon#end of sib2, iclass 21, count 2 2006.285.22:47:37.11#ibcon#*mode == 0, iclass 21, count 2 2006.285.22:47:37.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.22:47:37.11#ibcon#[25=AT02-06\r\n] 2006.285.22:47:37.11#ibcon#*before write, iclass 21, count 2 2006.285.22:47:37.11#ibcon#enter sib2, iclass 21, count 2 2006.285.22:47:37.11#ibcon#flushed, iclass 21, count 2 2006.285.22:47:37.11#ibcon#about to write, iclass 21, count 2 2006.285.22:47:37.11#ibcon#wrote, iclass 21, count 2 2006.285.22:47:37.11#ibcon#about to read 3, iclass 21, count 2 2006.285.22:47:37.14#ibcon#read 3, iclass 21, count 2 2006.285.22:47:37.14#ibcon#about to read 4, iclass 21, count 2 2006.285.22:47:37.14#ibcon#read 4, iclass 21, count 2 2006.285.22:47:37.14#ibcon#about to read 5, iclass 21, count 2 2006.285.22:47:37.14#ibcon#read 5, iclass 21, count 2 2006.285.22:47:37.14#ibcon#about to read 6, iclass 21, count 2 2006.285.22:47:37.14#ibcon#read 6, iclass 21, count 2 2006.285.22:47:37.14#ibcon#end of sib2, iclass 21, count 2 2006.285.22:47:37.14#ibcon#*after write, iclass 21, count 2 2006.285.22:47:37.14#ibcon#*before return 0, iclass 21, count 2 2006.285.22:47:37.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:47:37.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:47:37.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.22:47:37.14#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:37.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:47:37.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:47:37.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:47:37.26#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:47:37.26#ibcon#first serial, iclass 21, count 0 2006.285.22:47:37.26#ibcon#enter sib2, iclass 21, count 0 2006.285.22:47:37.26#ibcon#flushed, iclass 21, count 0 2006.285.22:47:37.26#ibcon#about to write, iclass 21, count 0 2006.285.22:47:37.26#ibcon#wrote, iclass 21, count 0 2006.285.22:47:37.26#ibcon#about to read 3, iclass 21, count 0 2006.285.22:47:37.28#ibcon#read 3, iclass 21, count 0 2006.285.22:47:37.28#ibcon#about to read 4, iclass 21, count 0 2006.285.22:47:37.28#ibcon#read 4, iclass 21, count 0 2006.285.22:47:37.28#ibcon#about to read 5, iclass 21, count 0 2006.285.22:47:37.28#ibcon#read 5, iclass 21, count 0 2006.285.22:47:37.28#ibcon#about to read 6, iclass 21, count 0 2006.285.22:47:37.28#ibcon#read 6, iclass 21, count 0 2006.285.22:47:37.28#ibcon#end of sib2, iclass 21, count 0 2006.285.22:47:37.28#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:47:37.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:47:37.28#ibcon#[25=USB\r\n] 2006.285.22:47:37.28#ibcon#*before write, iclass 21, count 0 2006.285.22:47:37.28#ibcon#enter sib2, iclass 21, count 0 2006.285.22:47:37.28#ibcon#flushed, iclass 21, count 0 2006.285.22:47:37.28#ibcon#about to write, iclass 21, count 0 2006.285.22:47:37.28#ibcon#wrote, iclass 21, count 0 2006.285.22:47:37.28#ibcon#about to read 3, iclass 21, count 0 2006.285.22:47:37.31#ibcon#read 3, iclass 21, count 0 2006.285.22:47:37.31#ibcon#about to read 4, iclass 21, count 0 2006.285.22:47:37.31#ibcon#read 4, iclass 21, count 0 2006.285.22:47:37.31#ibcon#about to read 5, iclass 21, count 0 2006.285.22:47:37.31#ibcon#read 5, iclass 21, count 0 2006.285.22:47:37.31#ibcon#about to read 6, iclass 21, count 0 2006.285.22:47:37.31#ibcon#read 6, iclass 21, count 0 2006.285.22:47:37.31#ibcon#end of sib2, iclass 21, count 0 2006.285.22:47:37.31#ibcon#*after write, iclass 21, count 0 2006.285.22:47:37.31#ibcon#*before return 0, iclass 21, count 0 2006.285.22:47:37.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:47:37.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:47:37.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:47:37.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:47:37.31$vck44/valo=3,564.99 2006.285.22:47:37.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.22:47:37.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.22:47:37.31#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:37.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:47:37.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:47:37.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:47:37.31#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:47:37.31#ibcon#first serial, iclass 23, count 0 2006.285.22:47:37.31#ibcon#enter sib2, iclass 23, count 0 2006.285.22:47:37.31#ibcon#flushed, iclass 23, count 0 2006.285.22:47:37.31#ibcon#about to write, iclass 23, count 0 2006.285.22:47:37.31#ibcon#wrote, iclass 23, count 0 2006.285.22:47:37.31#ibcon#about to read 3, iclass 23, count 0 2006.285.22:47:37.33#ibcon#read 3, iclass 23, count 0 2006.285.22:47:37.33#ibcon#about to read 4, iclass 23, count 0 2006.285.22:47:37.33#ibcon#read 4, iclass 23, count 0 2006.285.22:47:37.33#ibcon#about to read 5, iclass 23, count 0 2006.285.22:47:37.33#ibcon#read 5, iclass 23, count 0 2006.285.22:47:37.33#ibcon#about to read 6, iclass 23, count 0 2006.285.22:47:37.33#ibcon#read 6, iclass 23, count 0 2006.285.22:47:37.33#ibcon#end of sib2, iclass 23, count 0 2006.285.22:47:37.33#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:47:37.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:47:37.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:47:37.33#ibcon#*before write, iclass 23, count 0 2006.285.22:47:37.33#ibcon#enter sib2, iclass 23, count 0 2006.285.22:47:37.33#ibcon#flushed, iclass 23, count 0 2006.285.22:47:37.33#ibcon#about to write, iclass 23, count 0 2006.285.22:47:37.33#ibcon#wrote, iclass 23, count 0 2006.285.22:47:37.33#ibcon#about to read 3, iclass 23, count 0 2006.285.22:47:37.37#ibcon#read 3, iclass 23, count 0 2006.285.22:47:37.37#ibcon#about to read 4, iclass 23, count 0 2006.285.22:47:37.37#ibcon#read 4, iclass 23, count 0 2006.285.22:47:37.37#ibcon#about to read 5, iclass 23, count 0 2006.285.22:47:37.37#ibcon#read 5, iclass 23, count 0 2006.285.22:47:37.37#ibcon#about to read 6, iclass 23, count 0 2006.285.22:47:37.37#ibcon#read 6, iclass 23, count 0 2006.285.22:47:37.37#ibcon#end of sib2, iclass 23, count 0 2006.285.22:47:37.37#ibcon#*after write, iclass 23, count 0 2006.285.22:47:37.37#ibcon#*before return 0, iclass 23, count 0 2006.285.22:47:37.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:47:37.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:47:37.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:47:37.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:47:37.37$vck44/va=3,7 2006.285.22:47:37.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.22:47:37.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.22:47:37.37#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:37.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:47:37.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:47:37.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:47:37.43#ibcon#enter wrdev, iclass 25, count 2 2006.285.22:47:37.43#ibcon#first serial, iclass 25, count 2 2006.285.22:47:37.43#ibcon#enter sib2, iclass 25, count 2 2006.285.22:47:37.43#ibcon#flushed, iclass 25, count 2 2006.285.22:47:37.43#ibcon#about to write, iclass 25, count 2 2006.285.22:47:37.43#ibcon#wrote, iclass 25, count 2 2006.285.22:47:37.43#ibcon#about to read 3, iclass 25, count 2 2006.285.22:47:37.45#ibcon#read 3, iclass 25, count 2 2006.285.22:47:37.45#ibcon#about to read 4, iclass 25, count 2 2006.285.22:47:37.45#ibcon#read 4, iclass 25, count 2 2006.285.22:47:37.45#ibcon#about to read 5, iclass 25, count 2 2006.285.22:47:37.45#ibcon#read 5, iclass 25, count 2 2006.285.22:47:37.45#ibcon#about to read 6, iclass 25, count 2 2006.285.22:47:37.45#ibcon#read 6, iclass 25, count 2 2006.285.22:47:37.45#ibcon#end of sib2, iclass 25, count 2 2006.285.22:47:37.45#ibcon#*mode == 0, iclass 25, count 2 2006.285.22:47:37.45#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.22:47:37.45#ibcon#[25=AT03-07\r\n] 2006.285.22:47:37.45#ibcon#*before write, iclass 25, count 2 2006.285.22:47:37.45#ibcon#enter sib2, iclass 25, count 2 2006.285.22:47:37.45#ibcon#flushed, iclass 25, count 2 2006.285.22:47:37.45#ibcon#about to write, iclass 25, count 2 2006.285.22:47:37.45#ibcon#wrote, iclass 25, count 2 2006.285.22:47:37.45#ibcon#about to read 3, iclass 25, count 2 2006.285.22:47:37.48#ibcon#read 3, iclass 25, count 2 2006.285.22:47:37.48#ibcon#about to read 4, iclass 25, count 2 2006.285.22:47:37.48#ibcon#read 4, iclass 25, count 2 2006.285.22:47:37.48#ibcon#about to read 5, iclass 25, count 2 2006.285.22:47:37.48#ibcon#read 5, iclass 25, count 2 2006.285.22:47:37.48#ibcon#about to read 6, iclass 25, count 2 2006.285.22:47:37.48#ibcon#read 6, iclass 25, count 2 2006.285.22:47:37.48#ibcon#end of sib2, iclass 25, count 2 2006.285.22:47:37.48#ibcon#*after write, iclass 25, count 2 2006.285.22:47:37.48#ibcon#*before return 0, iclass 25, count 2 2006.285.22:47:37.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:47:37.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:47:37.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.22:47:37.48#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:37.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:47:37.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:47:37.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:47:37.60#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:47:37.60#ibcon#first serial, iclass 25, count 0 2006.285.22:47:37.60#ibcon#enter sib2, iclass 25, count 0 2006.285.22:47:37.60#ibcon#flushed, iclass 25, count 0 2006.285.22:47:37.60#ibcon#about to write, iclass 25, count 0 2006.285.22:47:37.60#ibcon#wrote, iclass 25, count 0 2006.285.22:47:37.60#ibcon#about to read 3, iclass 25, count 0 2006.285.22:47:37.62#ibcon#read 3, iclass 25, count 0 2006.285.22:47:37.62#ibcon#about to read 4, iclass 25, count 0 2006.285.22:47:37.62#ibcon#read 4, iclass 25, count 0 2006.285.22:47:37.62#ibcon#about to read 5, iclass 25, count 0 2006.285.22:47:37.62#ibcon#read 5, iclass 25, count 0 2006.285.22:47:37.62#ibcon#about to read 6, iclass 25, count 0 2006.285.22:47:37.62#ibcon#read 6, iclass 25, count 0 2006.285.22:47:37.62#ibcon#end of sib2, iclass 25, count 0 2006.285.22:47:37.62#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:47:37.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:47:37.62#ibcon#[25=USB\r\n] 2006.285.22:47:37.62#ibcon#*before write, iclass 25, count 0 2006.285.22:47:37.62#ibcon#enter sib2, iclass 25, count 0 2006.285.22:47:37.62#ibcon#flushed, iclass 25, count 0 2006.285.22:47:37.62#ibcon#about to write, iclass 25, count 0 2006.285.22:47:37.62#ibcon#wrote, iclass 25, count 0 2006.285.22:47:37.62#ibcon#about to read 3, iclass 25, count 0 2006.285.22:47:37.65#ibcon#read 3, iclass 25, count 0 2006.285.22:47:37.65#ibcon#about to read 4, iclass 25, count 0 2006.285.22:47:37.65#ibcon#read 4, iclass 25, count 0 2006.285.22:47:37.65#ibcon#about to read 5, iclass 25, count 0 2006.285.22:47:37.65#ibcon#read 5, iclass 25, count 0 2006.285.22:47:37.65#ibcon#about to read 6, iclass 25, count 0 2006.285.22:47:37.65#ibcon#read 6, iclass 25, count 0 2006.285.22:47:37.65#ibcon#end of sib2, iclass 25, count 0 2006.285.22:47:37.65#ibcon#*after write, iclass 25, count 0 2006.285.22:47:37.65#ibcon#*before return 0, iclass 25, count 0 2006.285.22:47:37.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:47:37.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:47:37.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:47:37.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:47:37.65$vck44/valo=4,624.99 2006.285.22:47:37.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.22:47:37.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.22:47:37.65#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:37.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:47:37.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:47:37.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:47:37.65#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:47:37.65#ibcon#first serial, iclass 27, count 0 2006.285.22:47:37.65#ibcon#enter sib2, iclass 27, count 0 2006.285.22:47:37.65#ibcon#flushed, iclass 27, count 0 2006.285.22:47:37.65#ibcon#about to write, iclass 27, count 0 2006.285.22:47:37.65#ibcon#wrote, iclass 27, count 0 2006.285.22:47:37.65#ibcon#about to read 3, iclass 27, count 0 2006.285.22:47:37.67#ibcon#read 3, iclass 27, count 0 2006.285.22:47:37.67#ibcon#about to read 4, iclass 27, count 0 2006.285.22:47:37.67#ibcon#read 4, iclass 27, count 0 2006.285.22:47:37.67#ibcon#about to read 5, iclass 27, count 0 2006.285.22:47:37.67#ibcon#read 5, iclass 27, count 0 2006.285.22:47:37.67#ibcon#about to read 6, iclass 27, count 0 2006.285.22:47:37.67#ibcon#read 6, iclass 27, count 0 2006.285.22:47:37.67#ibcon#end of sib2, iclass 27, count 0 2006.285.22:47:37.67#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:47:37.67#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:47:37.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:47:37.67#ibcon#*before write, iclass 27, count 0 2006.285.22:47:37.67#ibcon#enter sib2, iclass 27, count 0 2006.285.22:47:37.67#ibcon#flushed, iclass 27, count 0 2006.285.22:47:37.67#ibcon#about to write, iclass 27, count 0 2006.285.22:47:37.67#ibcon#wrote, iclass 27, count 0 2006.285.22:47:37.67#ibcon#about to read 3, iclass 27, count 0 2006.285.22:47:37.71#ibcon#read 3, iclass 27, count 0 2006.285.22:47:37.71#ibcon#about to read 4, iclass 27, count 0 2006.285.22:47:37.71#ibcon#read 4, iclass 27, count 0 2006.285.22:47:37.71#ibcon#about to read 5, iclass 27, count 0 2006.285.22:47:37.71#ibcon#read 5, iclass 27, count 0 2006.285.22:47:37.71#ibcon#about to read 6, iclass 27, count 0 2006.285.22:47:37.71#ibcon#read 6, iclass 27, count 0 2006.285.22:47:37.71#ibcon#end of sib2, iclass 27, count 0 2006.285.22:47:37.71#ibcon#*after write, iclass 27, count 0 2006.285.22:47:37.71#ibcon#*before return 0, iclass 27, count 0 2006.285.22:47:37.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:47:37.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:47:37.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:47:37.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:47:37.71$vck44/va=4,6 2006.285.22:47:37.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.22:47:37.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.22:47:37.71#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:37.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:47:37.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:47:37.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:47:37.77#ibcon#enter wrdev, iclass 29, count 2 2006.285.22:47:37.77#ibcon#first serial, iclass 29, count 2 2006.285.22:47:37.77#ibcon#enter sib2, iclass 29, count 2 2006.285.22:47:37.77#ibcon#flushed, iclass 29, count 2 2006.285.22:47:37.77#ibcon#about to write, iclass 29, count 2 2006.285.22:47:37.77#ibcon#wrote, iclass 29, count 2 2006.285.22:47:37.77#ibcon#about to read 3, iclass 29, count 2 2006.285.22:47:37.79#ibcon#read 3, iclass 29, count 2 2006.285.22:47:37.79#ibcon#about to read 4, iclass 29, count 2 2006.285.22:47:37.79#ibcon#read 4, iclass 29, count 2 2006.285.22:47:37.79#ibcon#about to read 5, iclass 29, count 2 2006.285.22:47:37.79#ibcon#read 5, iclass 29, count 2 2006.285.22:47:37.79#ibcon#about to read 6, iclass 29, count 2 2006.285.22:47:37.79#ibcon#read 6, iclass 29, count 2 2006.285.22:47:37.79#ibcon#end of sib2, iclass 29, count 2 2006.285.22:47:37.79#ibcon#*mode == 0, iclass 29, count 2 2006.285.22:47:37.79#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.22:47:37.79#ibcon#[25=AT04-06\r\n] 2006.285.22:47:37.79#ibcon#*before write, iclass 29, count 2 2006.285.22:47:37.79#ibcon#enter sib2, iclass 29, count 2 2006.285.22:47:37.79#ibcon#flushed, iclass 29, count 2 2006.285.22:47:37.79#ibcon#about to write, iclass 29, count 2 2006.285.22:47:37.79#ibcon#wrote, iclass 29, count 2 2006.285.22:47:37.79#ibcon#about to read 3, iclass 29, count 2 2006.285.22:47:37.82#ibcon#read 3, iclass 29, count 2 2006.285.22:47:37.82#ibcon#about to read 4, iclass 29, count 2 2006.285.22:47:37.82#ibcon#read 4, iclass 29, count 2 2006.285.22:47:37.82#ibcon#about to read 5, iclass 29, count 2 2006.285.22:47:37.82#ibcon#read 5, iclass 29, count 2 2006.285.22:47:37.82#ibcon#about to read 6, iclass 29, count 2 2006.285.22:47:37.82#ibcon#read 6, iclass 29, count 2 2006.285.22:47:37.82#ibcon#end of sib2, iclass 29, count 2 2006.285.22:47:37.82#ibcon#*after write, iclass 29, count 2 2006.285.22:47:37.82#ibcon#*before return 0, iclass 29, count 2 2006.285.22:47:37.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:47:37.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:47:37.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.22:47:37.82#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:37.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:47:37.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:47:37.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:47:37.94#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:47:37.94#ibcon#first serial, iclass 29, count 0 2006.285.22:47:37.94#ibcon#enter sib2, iclass 29, count 0 2006.285.22:47:37.94#ibcon#flushed, iclass 29, count 0 2006.285.22:47:37.94#ibcon#about to write, iclass 29, count 0 2006.285.22:47:37.94#ibcon#wrote, iclass 29, count 0 2006.285.22:47:37.94#ibcon#about to read 3, iclass 29, count 0 2006.285.22:47:37.96#ibcon#read 3, iclass 29, count 0 2006.285.22:47:37.96#ibcon#about to read 4, iclass 29, count 0 2006.285.22:47:37.96#ibcon#read 4, iclass 29, count 0 2006.285.22:47:37.96#ibcon#about to read 5, iclass 29, count 0 2006.285.22:47:37.96#ibcon#read 5, iclass 29, count 0 2006.285.22:47:37.96#ibcon#about to read 6, iclass 29, count 0 2006.285.22:47:37.96#ibcon#read 6, iclass 29, count 0 2006.285.22:47:37.96#ibcon#end of sib2, iclass 29, count 0 2006.285.22:47:37.96#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:47:37.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:47:37.96#ibcon#[25=USB\r\n] 2006.285.22:47:37.96#ibcon#*before write, iclass 29, count 0 2006.285.22:47:37.96#ibcon#enter sib2, iclass 29, count 0 2006.285.22:47:37.96#ibcon#flushed, iclass 29, count 0 2006.285.22:47:37.96#ibcon#about to write, iclass 29, count 0 2006.285.22:47:37.96#ibcon#wrote, iclass 29, count 0 2006.285.22:47:37.96#ibcon#about to read 3, iclass 29, count 0 2006.285.22:47:37.99#ibcon#read 3, iclass 29, count 0 2006.285.22:47:37.99#ibcon#about to read 4, iclass 29, count 0 2006.285.22:47:37.99#ibcon#read 4, iclass 29, count 0 2006.285.22:47:37.99#ibcon#about to read 5, iclass 29, count 0 2006.285.22:47:37.99#ibcon#read 5, iclass 29, count 0 2006.285.22:47:37.99#ibcon#about to read 6, iclass 29, count 0 2006.285.22:47:37.99#ibcon#read 6, iclass 29, count 0 2006.285.22:47:37.99#ibcon#end of sib2, iclass 29, count 0 2006.285.22:47:37.99#ibcon#*after write, iclass 29, count 0 2006.285.22:47:37.99#ibcon#*before return 0, iclass 29, count 0 2006.285.22:47:37.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:47:37.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:47:37.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:47:37.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:47:37.99$vck44/valo=5,734.99 2006.285.22:47:37.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.22:47:37.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.22:47:37.99#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:37.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:47:37.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:47:37.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:47:37.99#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:47:37.99#ibcon#first serial, iclass 31, count 0 2006.285.22:47:37.99#ibcon#enter sib2, iclass 31, count 0 2006.285.22:47:37.99#ibcon#flushed, iclass 31, count 0 2006.285.22:47:37.99#ibcon#about to write, iclass 31, count 0 2006.285.22:47:37.99#ibcon#wrote, iclass 31, count 0 2006.285.22:47:37.99#ibcon#about to read 3, iclass 31, count 0 2006.285.22:47:38.01#ibcon#read 3, iclass 31, count 0 2006.285.22:47:38.01#ibcon#about to read 4, iclass 31, count 0 2006.285.22:47:38.01#ibcon#read 4, iclass 31, count 0 2006.285.22:47:38.01#ibcon#about to read 5, iclass 31, count 0 2006.285.22:47:38.01#ibcon#read 5, iclass 31, count 0 2006.285.22:47:38.01#ibcon#about to read 6, iclass 31, count 0 2006.285.22:47:38.01#ibcon#read 6, iclass 31, count 0 2006.285.22:47:38.01#ibcon#end of sib2, iclass 31, count 0 2006.285.22:47:38.01#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:47:38.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:47:38.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:47:38.01#ibcon#*before write, iclass 31, count 0 2006.285.22:47:38.01#ibcon#enter sib2, iclass 31, count 0 2006.285.22:47:38.01#ibcon#flushed, iclass 31, count 0 2006.285.22:47:38.01#ibcon#about to write, iclass 31, count 0 2006.285.22:47:38.01#ibcon#wrote, iclass 31, count 0 2006.285.22:47:38.01#ibcon#about to read 3, iclass 31, count 0 2006.285.22:47:38.05#ibcon#read 3, iclass 31, count 0 2006.285.22:47:38.05#ibcon#about to read 4, iclass 31, count 0 2006.285.22:47:38.05#ibcon#read 4, iclass 31, count 0 2006.285.22:47:38.05#ibcon#about to read 5, iclass 31, count 0 2006.285.22:47:38.05#ibcon#read 5, iclass 31, count 0 2006.285.22:47:38.05#ibcon#about to read 6, iclass 31, count 0 2006.285.22:47:38.05#ibcon#read 6, iclass 31, count 0 2006.285.22:47:38.05#ibcon#end of sib2, iclass 31, count 0 2006.285.22:47:38.05#ibcon#*after write, iclass 31, count 0 2006.285.22:47:38.05#ibcon#*before return 0, iclass 31, count 0 2006.285.22:47:38.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:47:38.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:47:38.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:47:38.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:47:38.05$vck44/va=5,3 2006.285.22:47:38.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.22:47:38.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.22:47:38.05#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:38.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:47:38.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:47:38.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:47:38.11#ibcon#enter wrdev, iclass 33, count 2 2006.285.22:47:38.11#ibcon#first serial, iclass 33, count 2 2006.285.22:47:38.11#ibcon#enter sib2, iclass 33, count 2 2006.285.22:47:38.11#ibcon#flushed, iclass 33, count 2 2006.285.22:47:38.11#ibcon#about to write, iclass 33, count 2 2006.285.22:47:38.11#ibcon#wrote, iclass 33, count 2 2006.285.22:47:38.11#ibcon#about to read 3, iclass 33, count 2 2006.285.22:47:38.13#ibcon#read 3, iclass 33, count 2 2006.285.22:47:38.13#ibcon#about to read 4, iclass 33, count 2 2006.285.22:47:38.13#ibcon#read 4, iclass 33, count 2 2006.285.22:47:38.13#ibcon#about to read 5, iclass 33, count 2 2006.285.22:47:38.13#ibcon#read 5, iclass 33, count 2 2006.285.22:47:38.13#ibcon#about to read 6, iclass 33, count 2 2006.285.22:47:38.13#ibcon#read 6, iclass 33, count 2 2006.285.22:47:38.13#ibcon#end of sib2, iclass 33, count 2 2006.285.22:47:38.13#ibcon#*mode == 0, iclass 33, count 2 2006.285.22:47:38.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.22:47:38.13#ibcon#[25=AT05-03\r\n] 2006.285.22:47:38.13#ibcon#*before write, iclass 33, count 2 2006.285.22:47:38.13#ibcon#enter sib2, iclass 33, count 2 2006.285.22:47:38.13#ibcon#flushed, iclass 33, count 2 2006.285.22:47:38.13#ibcon#about to write, iclass 33, count 2 2006.285.22:47:38.13#ibcon#wrote, iclass 33, count 2 2006.285.22:47:38.13#ibcon#about to read 3, iclass 33, count 2 2006.285.22:47:38.16#ibcon#read 3, iclass 33, count 2 2006.285.22:47:38.16#ibcon#about to read 4, iclass 33, count 2 2006.285.22:47:38.16#ibcon#read 4, iclass 33, count 2 2006.285.22:47:38.16#ibcon#about to read 5, iclass 33, count 2 2006.285.22:47:38.16#ibcon#read 5, iclass 33, count 2 2006.285.22:47:38.16#ibcon#about to read 6, iclass 33, count 2 2006.285.22:47:38.16#ibcon#read 6, iclass 33, count 2 2006.285.22:47:38.16#ibcon#end of sib2, iclass 33, count 2 2006.285.22:47:38.16#ibcon#*after write, iclass 33, count 2 2006.285.22:47:38.16#ibcon#*before return 0, iclass 33, count 2 2006.285.22:47:38.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:47:38.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:47:38.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.22:47:38.16#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:38.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:47:38.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:47:38.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:47:38.28#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:47:38.28#ibcon#first serial, iclass 33, count 0 2006.285.22:47:38.28#ibcon#enter sib2, iclass 33, count 0 2006.285.22:47:38.28#ibcon#flushed, iclass 33, count 0 2006.285.22:47:38.28#ibcon#about to write, iclass 33, count 0 2006.285.22:47:38.28#ibcon#wrote, iclass 33, count 0 2006.285.22:47:38.28#ibcon#about to read 3, iclass 33, count 0 2006.285.22:47:38.30#ibcon#read 3, iclass 33, count 0 2006.285.22:47:38.30#ibcon#about to read 4, iclass 33, count 0 2006.285.22:47:38.30#ibcon#read 4, iclass 33, count 0 2006.285.22:47:38.30#ibcon#about to read 5, iclass 33, count 0 2006.285.22:47:38.30#ibcon#read 5, iclass 33, count 0 2006.285.22:47:38.30#ibcon#about to read 6, iclass 33, count 0 2006.285.22:47:38.30#ibcon#read 6, iclass 33, count 0 2006.285.22:47:38.30#ibcon#end of sib2, iclass 33, count 0 2006.285.22:47:38.30#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:47:38.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:47:38.30#ibcon#[25=USB\r\n] 2006.285.22:47:38.30#ibcon#*before write, iclass 33, count 0 2006.285.22:47:38.30#ibcon#enter sib2, iclass 33, count 0 2006.285.22:47:38.30#ibcon#flushed, iclass 33, count 0 2006.285.22:47:38.30#ibcon#about to write, iclass 33, count 0 2006.285.22:47:38.30#ibcon#wrote, iclass 33, count 0 2006.285.22:47:38.30#ibcon#about to read 3, iclass 33, count 0 2006.285.22:47:38.33#ibcon#read 3, iclass 33, count 0 2006.285.22:47:38.33#ibcon#about to read 4, iclass 33, count 0 2006.285.22:47:38.33#ibcon#read 4, iclass 33, count 0 2006.285.22:47:38.33#ibcon#about to read 5, iclass 33, count 0 2006.285.22:47:38.33#ibcon#read 5, iclass 33, count 0 2006.285.22:47:38.33#ibcon#about to read 6, iclass 33, count 0 2006.285.22:47:38.33#ibcon#read 6, iclass 33, count 0 2006.285.22:47:38.33#ibcon#end of sib2, iclass 33, count 0 2006.285.22:47:38.33#ibcon#*after write, iclass 33, count 0 2006.285.22:47:38.33#ibcon#*before return 0, iclass 33, count 0 2006.285.22:47:38.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:47:38.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:47:38.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:47:38.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:47:38.33$vck44/valo=6,814.99 2006.285.22:47:38.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.22:47:38.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.22:47:38.33#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:38.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:47:38.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:47:38.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:47:38.33#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:47:38.33#ibcon#first serial, iclass 35, count 0 2006.285.22:47:38.33#ibcon#enter sib2, iclass 35, count 0 2006.285.22:47:38.33#ibcon#flushed, iclass 35, count 0 2006.285.22:47:38.33#ibcon#about to write, iclass 35, count 0 2006.285.22:47:38.33#ibcon#wrote, iclass 35, count 0 2006.285.22:47:38.33#ibcon#about to read 3, iclass 35, count 0 2006.285.22:47:38.35#ibcon#read 3, iclass 35, count 0 2006.285.22:47:38.35#ibcon#about to read 4, iclass 35, count 0 2006.285.22:47:38.35#ibcon#read 4, iclass 35, count 0 2006.285.22:47:38.35#ibcon#about to read 5, iclass 35, count 0 2006.285.22:47:38.35#ibcon#read 5, iclass 35, count 0 2006.285.22:47:38.35#ibcon#about to read 6, iclass 35, count 0 2006.285.22:47:38.35#ibcon#read 6, iclass 35, count 0 2006.285.22:47:38.35#ibcon#end of sib2, iclass 35, count 0 2006.285.22:47:38.35#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:47:38.35#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:47:38.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:47:38.35#ibcon#*before write, iclass 35, count 0 2006.285.22:47:38.35#ibcon#enter sib2, iclass 35, count 0 2006.285.22:47:38.35#ibcon#flushed, iclass 35, count 0 2006.285.22:47:38.35#ibcon#about to write, iclass 35, count 0 2006.285.22:47:38.35#ibcon#wrote, iclass 35, count 0 2006.285.22:47:38.35#ibcon#about to read 3, iclass 35, count 0 2006.285.22:47:38.39#ibcon#read 3, iclass 35, count 0 2006.285.22:47:38.39#ibcon#about to read 4, iclass 35, count 0 2006.285.22:47:38.39#ibcon#read 4, iclass 35, count 0 2006.285.22:47:38.39#ibcon#about to read 5, iclass 35, count 0 2006.285.22:47:38.39#ibcon#read 5, iclass 35, count 0 2006.285.22:47:38.39#ibcon#about to read 6, iclass 35, count 0 2006.285.22:47:38.39#ibcon#read 6, iclass 35, count 0 2006.285.22:47:38.39#ibcon#end of sib2, iclass 35, count 0 2006.285.22:47:38.39#ibcon#*after write, iclass 35, count 0 2006.285.22:47:38.39#ibcon#*before return 0, iclass 35, count 0 2006.285.22:47:38.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:47:38.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:47:38.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:47:38.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:47:38.39$vck44/va=6,4 2006.285.22:47:38.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.22:47:38.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.22:47:38.39#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:38.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:47:38.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:47:38.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:47:38.45#ibcon#enter wrdev, iclass 37, count 2 2006.285.22:47:38.45#ibcon#first serial, iclass 37, count 2 2006.285.22:47:38.45#ibcon#enter sib2, iclass 37, count 2 2006.285.22:47:38.45#ibcon#flushed, iclass 37, count 2 2006.285.22:47:38.45#ibcon#about to write, iclass 37, count 2 2006.285.22:47:38.45#ibcon#wrote, iclass 37, count 2 2006.285.22:47:38.45#ibcon#about to read 3, iclass 37, count 2 2006.285.22:47:38.47#ibcon#read 3, iclass 37, count 2 2006.285.22:47:38.47#ibcon#about to read 4, iclass 37, count 2 2006.285.22:47:38.47#ibcon#read 4, iclass 37, count 2 2006.285.22:47:38.47#ibcon#about to read 5, iclass 37, count 2 2006.285.22:47:38.47#ibcon#read 5, iclass 37, count 2 2006.285.22:47:38.47#ibcon#about to read 6, iclass 37, count 2 2006.285.22:47:38.47#ibcon#read 6, iclass 37, count 2 2006.285.22:47:38.47#ibcon#end of sib2, iclass 37, count 2 2006.285.22:47:38.47#ibcon#*mode == 0, iclass 37, count 2 2006.285.22:47:38.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.22:47:38.47#ibcon#[25=AT06-04\r\n] 2006.285.22:47:38.47#ibcon#*before write, iclass 37, count 2 2006.285.22:47:38.47#ibcon#enter sib2, iclass 37, count 2 2006.285.22:47:38.47#ibcon#flushed, iclass 37, count 2 2006.285.22:47:38.47#ibcon#about to write, iclass 37, count 2 2006.285.22:47:38.47#ibcon#wrote, iclass 37, count 2 2006.285.22:47:38.47#ibcon#about to read 3, iclass 37, count 2 2006.285.22:47:38.50#ibcon#read 3, iclass 37, count 2 2006.285.22:47:38.50#ibcon#about to read 4, iclass 37, count 2 2006.285.22:47:38.50#ibcon#read 4, iclass 37, count 2 2006.285.22:47:38.50#ibcon#about to read 5, iclass 37, count 2 2006.285.22:47:38.50#ibcon#read 5, iclass 37, count 2 2006.285.22:47:38.50#ibcon#about to read 6, iclass 37, count 2 2006.285.22:47:38.50#ibcon#read 6, iclass 37, count 2 2006.285.22:47:38.50#ibcon#end of sib2, iclass 37, count 2 2006.285.22:47:38.50#ibcon#*after write, iclass 37, count 2 2006.285.22:47:38.50#ibcon#*before return 0, iclass 37, count 2 2006.285.22:47:38.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:47:38.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:47:38.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.22:47:38.50#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:38.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:47:38.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:47:38.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:47:38.62#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:47:38.62#ibcon#first serial, iclass 37, count 0 2006.285.22:47:38.62#ibcon#enter sib2, iclass 37, count 0 2006.285.22:47:38.62#ibcon#flushed, iclass 37, count 0 2006.285.22:47:38.62#ibcon#about to write, iclass 37, count 0 2006.285.22:47:38.62#ibcon#wrote, iclass 37, count 0 2006.285.22:47:38.62#ibcon#about to read 3, iclass 37, count 0 2006.285.22:47:38.64#ibcon#read 3, iclass 37, count 0 2006.285.22:47:38.64#ibcon#about to read 4, iclass 37, count 0 2006.285.22:47:38.64#ibcon#read 4, iclass 37, count 0 2006.285.22:47:38.64#ibcon#about to read 5, iclass 37, count 0 2006.285.22:47:38.64#ibcon#read 5, iclass 37, count 0 2006.285.22:47:38.64#ibcon#about to read 6, iclass 37, count 0 2006.285.22:47:38.64#ibcon#read 6, iclass 37, count 0 2006.285.22:47:38.64#ibcon#end of sib2, iclass 37, count 0 2006.285.22:47:38.64#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:47:38.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:47:38.64#ibcon#[25=USB\r\n] 2006.285.22:47:38.64#ibcon#*before write, iclass 37, count 0 2006.285.22:47:38.64#ibcon#enter sib2, iclass 37, count 0 2006.285.22:47:38.64#ibcon#flushed, iclass 37, count 0 2006.285.22:47:38.64#ibcon#about to write, iclass 37, count 0 2006.285.22:47:38.64#ibcon#wrote, iclass 37, count 0 2006.285.22:47:38.64#ibcon#about to read 3, iclass 37, count 0 2006.285.22:47:38.67#ibcon#read 3, iclass 37, count 0 2006.285.22:47:38.67#ibcon#about to read 4, iclass 37, count 0 2006.285.22:47:38.67#ibcon#read 4, iclass 37, count 0 2006.285.22:47:38.67#ibcon#about to read 5, iclass 37, count 0 2006.285.22:47:38.67#ibcon#read 5, iclass 37, count 0 2006.285.22:47:38.67#ibcon#about to read 6, iclass 37, count 0 2006.285.22:47:38.67#ibcon#read 6, iclass 37, count 0 2006.285.22:47:38.67#ibcon#end of sib2, iclass 37, count 0 2006.285.22:47:38.67#ibcon#*after write, iclass 37, count 0 2006.285.22:47:38.67#ibcon#*before return 0, iclass 37, count 0 2006.285.22:47:38.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:47:38.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:47:38.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:47:38.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:47:38.67$vck44/valo=7,864.99 2006.285.22:47:38.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.22:47:38.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.22:47:38.67#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:38.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:47:38.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:47:38.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:47:38.67#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:47:38.67#ibcon#first serial, iclass 39, count 0 2006.285.22:47:38.67#ibcon#enter sib2, iclass 39, count 0 2006.285.22:47:38.67#ibcon#flushed, iclass 39, count 0 2006.285.22:47:38.67#ibcon#about to write, iclass 39, count 0 2006.285.22:47:38.67#ibcon#wrote, iclass 39, count 0 2006.285.22:47:38.67#ibcon#about to read 3, iclass 39, count 0 2006.285.22:47:38.69#ibcon#read 3, iclass 39, count 0 2006.285.22:47:38.69#ibcon#about to read 4, iclass 39, count 0 2006.285.22:47:38.69#ibcon#read 4, iclass 39, count 0 2006.285.22:47:38.69#ibcon#about to read 5, iclass 39, count 0 2006.285.22:47:38.69#ibcon#read 5, iclass 39, count 0 2006.285.22:47:38.69#ibcon#about to read 6, iclass 39, count 0 2006.285.22:47:38.69#ibcon#read 6, iclass 39, count 0 2006.285.22:47:38.69#ibcon#end of sib2, iclass 39, count 0 2006.285.22:47:38.69#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:47:38.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:47:38.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:47:38.69#ibcon#*before write, iclass 39, count 0 2006.285.22:47:38.69#ibcon#enter sib2, iclass 39, count 0 2006.285.22:47:38.69#ibcon#flushed, iclass 39, count 0 2006.285.22:47:38.69#ibcon#about to write, iclass 39, count 0 2006.285.22:47:38.69#ibcon#wrote, iclass 39, count 0 2006.285.22:47:38.69#ibcon#about to read 3, iclass 39, count 0 2006.285.22:47:38.73#ibcon#read 3, iclass 39, count 0 2006.285.22:47:38.73#ibcon#about to read 4, iclass 39, count 0 2006.285.22:47:38.73#ibcon#read 4, iclass 39, count 0 2006.285.22:47:38.73#ibcon#about to read 5, iclass 39, count 0 2006.285.22:47:38.73#ibcon#read 5, iclass 39, count 0 2006.285.22:47:38.73#ibcon#about to read 6, iclass 39, count 0 2006.285.22:47:38.73#ibcon#read 6, iclass 39, count 0 2006.285.22:47:38.73#ibcon#end of sib2, iclass 39, count 0 2006.285.22:47:38.73#ibcon#*after write, iclass 39, count 0 2006.285.22:47:38.73#ibcon#*before return 0, iclass 39, count 0 2006.285.22:47:38.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:47:38.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:47:38.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:47:38.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:47:38.73$vck44/va=7,4 2006.285.22:47:38.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.22:47:38.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.22:47:38.73#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:38.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:47:38.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:47:38.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:47:38.79#ibcon#enter wrdev, iclass 3, count 2 2006.285.22:47:38.79#ibcon#first serial, iclass 3, count 2 2006.285.22:47:38.79#ibcon#enter sib2, iclass 3, count 2 2006.285.22:47:38.79#ibcon#flushed, iclass 3, count 2 2006.285.22:47:38.79#ibcon#about to write, iclass 3, count 2 2006.285.22:47:38.79#ibcon#wrote, iclass 3, count 2 2006.285.22:47:38.79#ibcon#about to read 3, iclass 3, count 2 2006.285.22:47:38.81#ibcon#read 3, iclass 3, count 2 2006.285.22:47:38.81#ibcon#about to read 4, iclass 3, count 2 2006.285.22:47:38.81#ibcon#read 4, iclass 3, count 2 2006.285.22:47:38.81#ibcon#about to read 5, iclass 3, count 2 2006.285.22:47:38.81#ibcon#read 5, iclass 3, count 2 2006.285.22:47:38.81#ibcon#about to read 6, iclass 3, count 2 2006.285.22:47:38.81#ibcon#read 6, iclass 3, count 2 2006.285.22:47:38.81#ibcon#end of sib2, iclass 3, count 2 2006.285.22:47:38.81#ibcon#*mode == 0, iclass 3, count 2 2006.285.22:47:38.81#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.22:47:38.81#ibcon#[25=AT07-04\r\n] 2006.285.22:47:38.81#ibcon#*before write, iclass 3, count 2 2006.285.22:47:38.81#ibcon#enter sib2, iclass 3, count 2 2006.285.22:47:38.81#ibcon#flushed, iclass 3, count 2 2006.285.22:47:38.81#ibcon#about to write, iclass 3, count 2 2006.285.22:47:38.81#ibcon#wrote, iclass 3, count 2 2006.285.22:47:38.81#ibcon#about to read 3, iclass 3, count 2 2006.285.22:47:38.84#ibcon#read 3, iclass 3, count 2 2006.285.22:47:38.84#ibcon#about to read 4, iclass 3, count 2 2006.285.22:47:38.84#ibcon#read 4, iclass 3, count 2 2006.285.22:47:38.84#ibcon#about to read 5, iclass 3, count 2 2006.285.22:47:38.84#ibcon#read 5, iclass 3, count 2 2006.285.22:47:38.84#ibcon#about to read 6, iclass 3, count 2 2006.285.22:47:38.84#ibcon#read 6, iclass 3, count 2 2006.285.22:47:38.84#ibcon#end of sib2, iclass 3, count 2 2006.285.22:47:38.84#ibcon#*after write, iclass 3, count 2 2006.285.22:47:38.84#ibcon#*before return 0, iclass 3, count 2 2006.285.22:47:38.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:47:38.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:47:38.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.22:47:38.84#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:38.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:47:38.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:47:38.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:47:38.96#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:47:38.96#ibcon#first serial, iclass 3, count 0 2006.285.22:47:38.96#ibcon#enter sib2, iclass 3, count 0 2006.285.22:47:38.96#ibcon#flushed, iclass 3, count 0 2006.285.22:47:38.96#ibcon#about to write, iclass 3, count 0 2006.285.22:47:38.96#ibcon#wrote, iclass 3, count 0 2006.285.22:47:38.96#ibcon#about to read 3, iclass 3, count 0 2006.285.22:47:38.98#ibcon#read 3, iclass 3, count 0 2006.285.22:47:38.98#ibcon#about to read 4, iclass 3, count 0 2006.285.22:47:38.98#ibcon#read 4, iclass 3, count 0 2006.285.22:47:38.98#ibcon#about to read 5, iclass 3, count 0 2006.285.22:47:38.98#ibcon#read 5, iclass 3, count 0 2006.285.22:47:38.98#ibcon#about to read 6, iclass 3, count 0 2006.285.22:47:38.98#ibcon#read 6, iclass 3, count 0 2006.285.22:47:38.98#ibcon#end of sib2, iclass 3, count 0 2006.285.22:47:38.98#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:47:38.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:47:38.98#ibcon#[25=USB\r\n] 2006.285.22:47:38.98#ibcon#*before write, iclass 3, count 0 2006.285.22:47:38.98#ibcon#enter sib2, iclass 3, count 0 2006.285.22:47:38.98#ibcon#flushed, iclass 3, count 0 2006.285.22:47:38.98#ibcon#about to write, iclass 3, count 0 2006.285.22:47:38.98#ibcon#wrote, iclass 3, count 0 2006.285.22:47:38.98#ibcon#about to read 3, iclass 3, count 0 2006.285.22:47:39.01#ibcon#read 3, iclass 3, count 0 2006.285.22:47:39.01#ibcon#about to read 4, iclass 3, count 0 2006.285.22:47:39.01#ibcon#read 4, iclass 3, count 0 2006.285.22:47:39.01#ibcon#about to read 5, iclass 3, count 0 2006.285.22:47:39.01#ibcon#read 5, iclass 3, count 0 2006.285.22:47:39.01#ibcon#about to read 6, iclass 3, count 0 2006.285.22:47:39.01#ibcon#read 6, iclass 3, count 0 2006.285.22:47:39.01#ibcon#end of sib2, iclass 3, count 0 2006.285.22:47:39.01#ibcon#*after write, iclass 3, count 0 2006.285.22:47:39.01#ibcon#*before return 0, iclass 3, count 0 2006.285.22:47:39.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:47:39.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:47:39.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:47:39.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:47:39.01$vck44/valo=8,884.99 2006.285.22:47:39.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.22:47:39.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.22:47:39.01#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:39.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:47:39.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:47:39.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:47:39.01#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:47:39.01#ibcon#first serial, iclass 5, count 0 2006.285.22:47:39.01#ibcon#enter sib2, iclass 5, count 0 2006.285.22:47:39.01#ibcon#flushed, iclass 5, count 0 2006.285.22:47:39.01#ibcon#about to write, iclass 5, count 0 2006.285.22:47:39.01#ibcon#wrote, iclass 5, count 0 2006.285.22:47:39.01#ibcon#about to read 3, iclass 5, count 0 2006.285.22:47:39.03#ibcon#read 3, iclass 5, count 0 2006.285.22:47:39.03#ibcon#about to read 4, iclass 5, count 0 2006.285.22:47:39.03#ibcon#read 4, iclass 5, count 0 2006.285.22:47:39.03#ibcon#about to read 5, iclass 5, count 0 2006.285.22:47:39.03#ibcon#read 5, iclass 5, count 0 2006.285.22:47:39.03#ibcon#about to read 6, iclass 5, count 0 2006.285.22:47:39.03#ibcon#read 6, iclass 5, count 0 2006.285.22:47:39.03#ibcon#end of sib2, iclass 5, count 0 2006.285.22:47:39.03#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:47:39.03#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:47:39.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:47:39.03#ibcon#*before write, iclass 5, count 0 2006.285.22:47:39.03#ibcon#enter sib2, iclass 5, count 0 2006.285.22:47:39.03#ibcon#flushed, iclass 5, count 0 2006.285.22:47:39.03#ibcon#about to write, iclass 5, count 0 2006.285.22:47:39.03#ibcon#wrote, iclass 5, count 0 2006.285.22:47:39.03#ibcon#about to read 3, iclass 5, count 0 2006.285.22:47:39.07#ibcon#read 3, iclass 5, count 0 2006.285.22:47:39.07#ibcon#about to read 4, iclass 5, count 0 2006.285.22:47:39.07#ibcon#read 4, iclass 5, count 0 2006.285.22:47:39.07#ibcon#about to read 5, iclass 5, count 0 2006.285.22:47:39.07#ibcon#read 5, iclass 5, count 0 2006.285.22:47:39.07#ibcon#about to read 6, iclass 5, count 0 2006.285.22:47:39.07#ibcon#read 6, iclass 5, count 0 2006.285.22:47:39.07#ibcon#end of sib2, iclass 5, count 0 2006.285.22:47:39.07#ibcon#*after write, iclass 5, count 0 2006.285.22:47:39.07#ibcon#*before return 0, iclass 5, count 0 2006.285.22:47:39.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:47:39.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:47:39.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:47:39.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:47:39.07$vck44/va=8,3 2006.285.22:47:39.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.22:47:39.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.22:47:39.07#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:39.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:47:39.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:47:39.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:47:39.13#ibcon#enter wrdev, iclass 7, count 2 2006.285.22:47:39.13#ibcon#first serial, iclass 7, count 2 2006.285.22:47:39.13#ibcon#enter sib2, iclass 7, count 2 2006.285.22:47:39.13#ibcon#flushed, iclass 7, count 2 2006.285.22:47:39.13#ibcon#about to write, iclass 7, count 2 2006.285.22:47:39.13#ibcon#wrote, iclass 7, count 2 2006.285.22:47:39.13#ibcon#about to read 3, iclass 7, count 2 2006.285.22:47:39.15#ibcon#read 3, iclass 7, count 2 2006.285.22:47:39.15#ibcon#about to read 4, iclass 7, count 2 2006.285.22:47:39.15#ibcon#read 4, iclass 7, count 2 2006.285.22:47:39.15#ibcon#about to read 5, iclass 7, count 2 2006.285.22:47:39.15#ibcon#read 5, iclass 7, count 2 2006.285.22:47:39.15#ibcon#about to read 6, iclass 7, count 2 2006.285.22:47:39.15#ibcon#read 6, iclass 7, count 2 2006.285.22:47:39.15#ibcon#end of sib2, iclass 7, count 2 2006.285.22:47:39.15#ibcon#*mode == 0, iclass 7, count 2 2006.285.22:47:39.15#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.22:47:39.15#ibcon#[25=AT08-03\r\n] 2006.285.22:47:39.15#ibcon#*before write, iclass 7, count 2 2006.285.22:47:39.15#ibcon#enter sib2, iclass 7, count 2 2006.285.22:47:39.15#ibcon#flushed, iclass 7, count 2 2006.285.22:47:39.15#ibcon#about to write, iclass 7, count 2 2006.285.22:47:39.15#ibcon#wrote, iclass 7, count 2 2006.285.22:47:39.15#ibcon#about to read 3, iclass 7, count 2 2006.285.22:47:39.18#ibcon#read 3, iclass 7, count 2 2006.285.22:47:39.18#ibcon#about to read 4, iclass 7, count 2 2006.285.22:47:39.18#ibcon#read 4, iclass 7, count 2 2006.285.22:47:39.18#ibcon#about to read 5, iclass 7, count 2 2006.285.22:47:39.18#ibcon#read 5, iclass 7, count 2 2006.285.22:47:39.18#ibcon#about to read 6, iclass 7, count 2 2006.285.22:47:39.18#ibcon#read 6, iclass 7, count 2 2006.285.22:47:39.18#ibcon#end of sib2, iclass 7, count 2 2006.285.22:47:39.18#ibcon#*after write, iclass 7, count 2 2006.285.22:47:39.18#ibcon#*before return 0, iclass 7, count 2 2006.285.22:47:39.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:47:39.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.22:47:39.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.22:47:39.18#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:39.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:47:39.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:47:39.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:47:39.30#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:47:39.30#ibcon#first serial, iclass 7, count 0 2006.285.22:47:39.30#ibcon#enter sib2, iclass 7, count 0 2006.285.22:47:39.30#ibcon#flushed, iclass 7, count 0 2006.285.22:47:39.30#ibcon#about to write, iclass 7, count 0 2006.285.22:47:39.30#ibcon#wrote, iclass 7, count 0 2006.285.22:47:39.30#ibcon#about to read 3, iclass 7, count 0 2006.285.22:47:39.32#ibcon#read 3, iclass 7, count 0 2006.285.22:47:39.32#ibcon#about to read 4, iclass 7, count 0 2006.285.22:47:39.32#ibcon#read 4, iclass 7, count 0 2006.285.22:47:39.32#ibcon#about to read 5, iclass 7, count 0 2006.285.22:47:39.32#ibcon#read 5, iclass 7, count 0 2006.285.22:47:39.32#ibcon#about to read 6, iclass 7, count 0 2006.285.22:47:39.32#ibcon#read 6, iclass 7, count 0 2006.285.22:47:39.32#ibcon#end of sib2, iclass 7, count 0 2006.285.22:47:39.32#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:47:39.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:47:39.32#ibcon#[25=USB\r\n] 2006.285.22:47:39.32#ibcon#*before write, iclass 7, count 0 2006.285.22:47:39.32#ibcon#enter sib2, iclass 7, count 0 2006.285.22:47:39.32#ibcon#flushed, iclass 7, count 0 2006.285.22:47:39.32#ibcon#about to write, iclass 7, count 0 2006.285.22:47:39.32#ibcon#wrote, iclass 7, count 0 2006.285.22:47:39.32#ibcon#about to read 3, iclass 7, count 0 2006.285.22:47:39.35#ibcon#read 3, iclass 7, count 0 2006.285.22:47:39.35#ibcon#about to read 4, iclass 7, count 0 2006.285.22:47:39.35#ibcon#read 4, iclass 7, count 0 2006.285.22:47:39.35#ibcon#about to read 5, iclass 7, count 0 2006.285.22:47:39.35#ibcon#read 5, iclass 7, count 0 2006.285.22:47:39.35#ibcon#about to read 6, iclass 7, count 0 2006.285.22:47:39.35#ibcon#read 6, iclass 7, count 0 2006.285.22:47:39.35#ibcon#end of sib2, iclass 7, count 0 2006.285.22:47:39.35#ibcon#*after write, iclass 7, count 0 2006.285.22:47:39.35#ibcon#*before return 0, iclass 7, count 0 2006.285.22:47:39.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:47:39.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.22:47:39.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:47:39.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:47:39.35$vck44/vblo=1,629.99 2006.285.22:47:39.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.22:47:39.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.22:47:39.35#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:39.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:47:39.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:47:39.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:47:39.35#ibcon#enter wrdev, iclass 11, count 0 2006.285.22:47:39.35#ibcon#first serial, iclass 11, count 0 2006.285.22:47:39.35#ibcon#enter sib2, iclass 11, count 0 2006.285.22:47:39.35#ibcon#flushed, iclass 11, count 0 2006.285.22:47:39.35#ibcon#about to write, iclass 11, count 0 2006.285.22:47:39.35#ibcon#wrote, iclass 11, count 0 2006.285.22:47:39.35#ibcon#about to read 3, iclass 11, count 0 2006.285.22:47:39.37#ibcon#read 3, iclass 11, count 0 2006.285.22:47:39.37#ibcon#about to read 4, iclass 11, count 0 2006.285.22:47:39.37#ibcon#read 4, iclass 11, count 0 2006.285.22:47:39.37#ibcon#about to read 5, iclass 11, count 0 2006.285.22:47:39.37#ibcon#read 5, iclass 11, count 0 2006.285.22:47:39.37#ibcon#about to read 6, iclass 11, count 0 2006.285.22:47:39.37#ibcon#read 6, iclass 11, count 0 2006.285.22:47:39.37#ibcon#end of sib2, iclass 11, count 0 2006.285.22:47:39.37#ibcon#*mode == 0, iclass 11, count 0 2006.285.22:47:39.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.22:47:39.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:47:39.37#ibcon#*before write, iclass 11, count 0 2006.285.22:47:39.37#ibcon#enter sib2, iclass 11, count 0 2006.285.22:47:39.37#ibcon#flushed, iclass 11, count 0 2006.285.22:47:39.37#ibcon#about to write, iclass 11, count 0 2006.285.22:47:39.37#ibcon#wrote, iclass 11, count 0 2006.285.22:47:39.37#ibcon#about to read 3, iclass 11, count 0 2006.285.22:47:39.41#ibcon#read 3, iclass 11, count 0 2006.285.22:47:39.41#ibcon#about to read 4, iclass 11, count 0 2006.285.22:47:39.41#ibcon#read 4, iclass 11, count 0 2006.285.22:47:39.41#ibcon#about to read 5, iclass 11, count 0 2006.285.22:47:39.41#ibcon#read 5, iclass 11, count 0 2006.285.22:47:39.41#ibcon#about to read 6, iclass 11, count 0 2006.285.22:47:39.41#ibcon#read 6, iclass 11, count 0 2006.285.22:47:39.41#ibcon#end of sib2, iclass 11, count 0 2006.285.22:47:39.41#ibcon#*after write, iclass 11, count 0 2006.285.22:47:39.41#ibcon#*before return 0, iclass 11, count 0 2006.285.22:47:39.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:47:39.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.22:47:39.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.22:47:39.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.22:47:39.41$vck44/vb=1,4 2006.285.22:47:39.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.22:47:39.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.22:47:39.41#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:39.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:47:39.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:47:39.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:47:39.41#ibcon#enter wrdev, iclass 13, count 2 2006.285.22:47:39.41#ibcon#first serial, iclass 13, count 2 2006.285.22:47:39.41#ibcon#enter sib2, iclass 13, count 2 2006.285.22:47:39.41#ibcon#flushed, iclass 13, count 2 2006.285.22:47:39.41#ibcon#about to write, iclass 13, count 2 2006.285.22:47:39.41#ibcon#wrote, iclass 13, count 2 2006.285.22:47:39.41#ibcon#about to read 3, iclass 13, count 2 2006.285.22:47:39.43#ibcon#read 3, iclass 13, count 2 2006.285.22:47:39.43#ibcon#about to read 4, iclass 13, count 2 2006.285.22:47:39.43#ibcon#read 4, iclass 13, count 2 2006.285.22:47:39.43#ibcon#about to read 5, iclass 13, count 2 2006.285.22:47:39.43#ibcon#read 5, iclass 13, count 2 2006.285.22:47:39.43#ibcon#about to read 6, iclass 13, count 2 2006.285.22:47:39.43#ibcon#read 6, iclass 13, count 2 2006.285.22:47:39.43#ibcon#end of sib2, iclass 13, count 2 2006.285.22:47:39.43#ibcon#*mode == 0, iclass 13, count 2 2006.285.22:47:39.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.22:47:39.43#ibcon#[27=AT01-04\r\n] 2006.285.22:47:39.43#ibcon#*before write, iclass 13, count 2 2006.285.22:47:39.43#ibcon#enter sib2, iclass 13, count 2 2006.285.22:47:39.43#ibcon#flushed, iclass 13, count 2 2006.285.22:47:39.43#ibcon#about to write, iclass 13, count 2 2006.285.22:47:39.43#ibcon#wrote, iclass 13, count 2 2006.285.22:47:39.43#ibcon#about to read 3, iclass 13, count 2 2006.285.22:47:39.46#ibcon#read 3, iclass 13, count 2 2006.285.22:47:39.46#ibcon#about to read 4, iclass 13, count 2 2006.285.22:47:39.46#ibcon#read 4, iclass 13, count 2 2006.285.22:47:39.46#ibcon#about to read 5, iclass 13, count 2 2006.285.22:47:39.46#ibcon#read 5, iclass 13, count 2 2006.285.22:47:39.46#ibcon#about to read 6, iclass 13, count 2 2006.285.22:47:39.46#ibcon#read 6, iclass 13, count 2 2006.285.22:47:39.46#ibcon#end of sib2, iclass 13, count 2 2006.285.22:47:39.46#ibcon#*after write, iclass 13, count 2 2006.285.22:47:39.46#ibcon#*before return 0, iclass 13, count 2 2006.285.22:47:39.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:47:39.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.22:47:39.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.22:47:39.46#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:39.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:47:39.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:47:39.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:47:39.58#ibcon#enter wrdev, iclass 13, count 0 2006.285.22:47:39.58#ibcon#first serial, iclass 13, count 0 2006.285.22:47:39.58#ibcon#enter sib2, iclass 13, count 0 2006.285.22:47:39.58#ibcon#flushed, iclass 13, count 0 2006.285.22:47:39.58#ibcon#about to write, iclass 13, count 0 2006.285.22:47:39.58#ibcon#wrote, iclass 13, count 0 2006.285.22:47:39.58#ibcon#about to read 3, iclass 13, count 0 2006.285.22:47:39.60#ibcon#read 3, iclass 13, count 0 2006.285.22:47:39.60#ibcon#about to read 4, iclass 13, count 0 2006.285.22:47:39.60#ibcon#read 4, iclass 13, count 0 2006.285.22:47:39.60#ibcon#about to read 5, iclass 13, count 0 2006.285.22:47:39.60#ibcon#read 5, iclass 13, count 0 2006.285.22:47:39.60#ibcon#about to read 6, iclass 13, count 0 2006.285.22:47:39.60#ibcon#read 6, iclass 13, count 0 2006.285.22:47:39.60#ibcon#end of sib2, iclass 13, count 0 2006.285.22:47:39.60#ibcon#*mode == 0, iclass 13, count 0 2006.285.22:47:39.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.22:47:39.60#ibcon#[27=USB\r\n] 2006.285.22:47:39.60#ibcon#*before write, iclass 13, count 0 2006.285.22:47:39.60#ibcon#enter sib2, iclass 13, count 0 2006.285.22:47:39.60#ibcon#flushed, iclass 13, count 0 2006.285.22:47:39.60#ibcon#about to write, iclass 13, count 0 2006.285.22:47:39.60#ibcon#wrote, iclass 13, count 0 2006.285.22:47:39.60#ibcon#about to read 3, iclass 13, count 0 2006.285.22:47:39.63#ibcon#read 3, iclass 13, count 0 2006.285.22:47:39.63#ibcon#about to read 4, iclass 13, count 0 2006.285.22:47:39.63#ibcon#read 4, iclass 13, count 0 2006.285.22:47:39.63#ibcon#about to read 5, iclass 13, count 0 2006.285.22:47:39.63#ibcon#read 5, iclass 13, count 0 2006.285.22:47:39.63#ibcon#about to read 6, iclass 13, count 0 2006.285.22:47:39.63#ibcon#read 6, iclass 13, count 0 2006.285.22:47:39.63#ibcon#end of sib2, iclass 13, count 0 2006.285.22:47:39.63#ibcon#*after write, iclass 13, count 0 2006.285.22:47:39.63#ibcon#*before return 0, iclass 13, count 0 2006.285.22:47:39.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:47:39.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.22:47:39.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.22:47:39.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.22:47:39.63$vck44/vblo=2,634.99 2006.285.22:47:39.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.22:47:39.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.22:47:39.63#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:39.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:47:39.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:47:39.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:47:39.63#ibcon#enter wrdev, iclass 15, count 0 2006.285.22:47:39.63#ibcon#first serial, iclass 15, count 0 2006.285.22:47:39.63#ibcon#enter sib2, iclass 15, count 0 2006.285.22:47:39.63#ibcon#flushed, iclass 15, count 0 2006.285.22:47:39.63#ibcon#about to write, iclass 15, count 0 2006.285.22:47:39.63#ibcon#wrote, iclass 15, count 0 2006.285.22:47:39.63#ibcon#about to read 3, iclass 15, count 0 2006.285.22:47:39.65#ibcon#read 3, iclass 15, count 0 2006.285.22:47:39.65#ibcon#about to read 4, iclass 15, count 0 2006.285.22:47:39.65#ibcon#read 4, iclass 15, count 0 2006.285.22:47:39.65#ibcon#about to read 5, iclass 15, count 0 2006.285.22:47:39.65#ibcon#read 5, iclass 15, count 0 2006.285.22:47:39.65#ibcon#about to read 6, iclass 15, count 0 2006.285.22:47:39.65#ibcon#read 6, iclass 15, count 0 2006.285.22:47:39.65#ibcon#end of sib2, iclass 15, count 0 2006.285.22:47:39.65#ibcon#*mode == 0, iclass 15, count 0 2006.285.22:47:39.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.22:47:39.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:47:39.65#ibcon#*before write, iclass 15, count 0 2006.285.22:47:39.65#ibcon#enter sib2, iclass 15, count 0 2006.285.22:47:39.65#ibcon#flushed, iclass 15, count 0 2006.285.22:47:39.65#ibcon#about to write, iclass 15, count 0 2006.285.22:47:39.65#ibcon#wrote, iclass 15, count 0 2006.285.22:47:39.65#ibcon#about to read 3, iclass 15, count 0 2006.285.22:47:39.69#ibcon#read 3, iclass 15, count 0 2006.285.22:47:39.69#ibcon#about to read 4, iclass 15, count 0 2006.285.22:47:39.69#ibcon#read 4, iclass 15, count 0 2006.285.22:47:39.69#ibcon#about to read 5, iclass 15, count 0 2006.285.22:47:39.69#ibcon#read 5, iclass 15, count 0 2006.285.22:47:39.69#ibcon#about to read 6, iclass 15, count 0 2006.285.22:47:39.69#ibcon#read 6, iclass 15, count 0 2006.285.22:47:39.69#ibcon#end of sib2, iclass 15, count 0 2006.285.22:47:39.69#ibcon#*after write, iclass 15, count 0 2006.285.22:47:39.69#ibcon#*before return 0, iclass 15, count 0 2006.285.22:47:39.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:47:39.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.22:47:39.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.22:47:39.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.22:47:39.69$vck44/vb=2,5 2006.285.22:47:39.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.22:47:39.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.22:47:39.69#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:39.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:47:39.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:47:39.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:47:39.75#ibcon#enter wrdev, iclass 17, count 2 2006.285.22:47:39.75#ibcon#first serial, iclass 17, count 2 2006.285.22:47:39.75#ibcon#enter sib2, iclass 17, count 2 2006.285.22:47:39.75#ibcon#flushed, iclass 17, count 2 2006.285.22:47:39.75#ibcon#about to write, iclass 17, count 2 2006.285.22:47:39.75#ibcon#wrote, iclass 17, count 2 2006.285.22:47:39.75#ibcon#about to read 3, iclass 17, count 2 2006.285.22:47:39.77#ibcon#read 3, iclass 17, count 2 2006.285.22:47:39.77#ibcon#about to read 4, iclass 17, count 2 2006.285.22:47:39.77#ibcon#read 4, iclass 17, count 2 2006.285.22:47:39.77#ibcon#about to read 5, iclass 17, count 2 2006.285.22:47:39.77#ibcon#read 5, iclass 17, count 2 2006.285.22:47:39.77#ibcon#about to read 6, iclass 17, count 2 2006.285.22:47:39.77#ibcon#read 6, iclass 17, count 2 2006.285.22:47:39.77#ibcon#end of sib2, iclass 17, count 2 2006.285.22:47:39.77#ibcon#*mode == 0, iclass 17, count 2 2006.285.22:47:39.77#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.22:47:39.77#ibcon#[27=AT02-05\r\n] 2006.285.22:47:39.77#ibcon#*before write, iclass 17, count 2 2006.285.22:47:39.77#ibcon#enter sib2, iclass 17, count 2 2006.285.22:47:39.77#ibcon#flushed, iclass 17, count 2 2006.285.22:47:39.77#ibcon#about to write, iclass 17, count 2 2006.285.22:47:39.77#ibcon#wrote, iclass 17, count 2 2006.285.22:47:39.77#ibcon#about to read 3, iclass 17, count 2 2006.285.22:47:39.80#ibcon#read 3, iclass 17, count 2 2006.285.22:47:39.80#ibcon#about to read 4, iclass 17, count 2 2006.285.22:47:39.80#ibcon#read 4, iclass 17, count 2 2006.285.22:47:39.80#ibcon#about to read 5, iclass 17, count 2 2006.285.22:47:39.80#ibcon#read 5, iclass 17, count 2 2006.285.22:47:39.80#ibcon#about to read 6, iclass 17, count 2 2006.285.22:47:39.80#ibcon#read 6, iclass 17, count 2 2006.285.22:47:39.80#ibcon#end of sib2, iclass 17, count 2 2006.285.22:47:39.80#ibcon#*after write, iclass 17, count 2 2006.285.22:47:39.80#ibcon#*before return 0, iclass 17, count 2 2006.285.22:47:39.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:47:39.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.22:47:39.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.22:47:39.80#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:39.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:47:39.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:47:39.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:47:39.92#ibcon#enter wrdev, iclass 17, count 0 2006.285.22:47:39.92#ibcon#first serial, iclass 17, count 0 2006.285.22:47:39.92#ibcon#enter sib2, iclass 17, count 0 2006.285.22:47:39.92#ibcon#flushed, iclass 17, count 0 2006.285.22:47:39.92#ibcon#about to write, iclass 17, count 0 2006.285.22:47:39.92#ibcon#wrote, iclass 17, count 0 2006.285.22:47:39.92#ibcon#about to read 3, iclass 17, count 0 2006.285.22:47:39.94#ibcon#read 3, iclass 17, count 0 2006.285.22:47:39.94#ibcon#about to read 4, iclass 17, count 0 2006.285.22:47:39.94#ibcon#read 4, iclass 17, count 0 2006.285.22:47:39.94#ibcon#about to read 5, iclass 17, count 0 2006.285.22:47:39.94#ibcon#read 5, iclass 17, count 0 2006.285.22:47:39.94#ibcon#about to read 6, iclass 17, count 0 2006.285.22:47:39.94#ibcon#read 6, iclass 17, count 0 2006.285.22:47:39.94#ibcon#end of sib2, iclass 17, count 0 2006.285.22:47:39.94#ibcon#*mode == 0, iclass 17, count 0 2006.285.22:47:39.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.22:47:39.94#ibcon#[27=USB\r\n] 2006.285.22:47:39.94#ibcon#*before write, iclass 17, count 0 2006.285.22:47:39.94#ibcon#enter sib2, iclass 17, count 0 2006.285.22:47:39.94#ibcon#flushed, iclass 17, count 0 2006.285.22:47:39.94#ibcon#about to write, iclass 17, count 0 2006.285.22:47:39.94#ibcon#wrote, iclass 17, count 0 2006.285.22:47:39.94#ibcon#about to read 3, iclass 17, count 0 2006.285.22:47:39.97#ibcon#read 3, iclass 17, count 0 2006.285.22:47:39.97#ibcon#about to read 4, iclass 17, count 0 2006.285.22:47:39.97#ibcon#read 4, iclass 17, count 0 2006.285.22:47:39.97#ibcon#about to read 5, iclass 17, count 0 2006.285.22:47:39.97#ibcon#read 5, iclass 17, count 0 2006.285.22:47:39.97#ibcon#about to read 6, iclass 17, count 0 2006.285.22:47:39.97#ibcon#read 6, iclass 17, count 0 2006.285.22:47:39.97#ibcon#end of sib2, iclass 17, count 0 2006.285.22:47:39.97#ibcon#*after write, iclass 17, count 0 2006.285.22:47:39.97#ibcon#*before return 0, iclass 17, count 0 2006.285.22:47:39.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:47:39.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.22:47:39.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.22:47:39.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.22:47:39.97$vck44/vblo=3,649.99 2006.285.22:47:39.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.22:47:39.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.22:47:39.97#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:39.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:47:39.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:47:39.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:47:39.97#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:47:39.97#ibcon#first serial, iclass 19, count 0 2006.285.22:47:39.97#ibcon#enter sib2, iclass 19, count 0 2006.285.22:47:39.97#ibcon#flushed, iclass 19, count 0 2006.285.22:47:39.97#ibcon#about to write, iclass 19, count 0 2006.285.22:47:39.97#ibcon#wrote, iclass 19, count 0 2006.285.22:47:39.97#ibcon#about to read 3, iclass 19, count 0 2006.285.22:47:39.99#ibcon#read 3, iclass 19, count 0 2006.285.22:47:39.99#ibcon#about to read 4, iclass 19, count 0 2006.285.22:47:39.99#ibcon#read 4, iclass 19, count 0 2006.285.22:47:39.99#ibcon#about to read 5, iclass 19, count 0 2006.285.22:47:39.99#ibcon#read 5, iclass 19, count 0 2006.285.22:47:39.99#ibcon#about to read 6, iclass 19, count 0 2006.285.22:47:39.99#ibcon#read 6, iclass 19, count 0 2006.285.22:47:39.99#ibcon#end of sib2, iclass 19, count 0 2006.285.22:47:39.99#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:47:39.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:47:39.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:47:39.99#ibcon#*before write, iclass 19, count 0 2006.285.22:47:39.99#ibcon#enter sib2, iclass 19, count 0 2006.285.22:47:39.99#ibcon#flushed, iclass 19, count 0 2006.285.22:47:39.99#ibcon#about to write, iclass 19, count 0 2006.285.22:47:39.99#ibcon#wrote, iclass 19, count 0 2006.285.22:47:39.99#ibcon#about to read 3, iclass 19, count 0 2006.285.22:47:40.03#ibcon#read 3, iclass 19, count 0 2006.285.22:47:40.03#ibcon#about to read 4, iclass 19, count 0 2006.285.22:47:40.03#ibcon#read 4, iclass 19, count 0 2006.285.22:47:40.03#ibcon#about to read 5, iclass 19, count 0 2006.285.22:47:40.03#ibcon#read 5, iclass 19, count 0 2006.285.22:47:40.03#ibcon#about to read 6, iclass 19, count 0 2006.285.22:47:40.03#ibcon#read 6, iclass 19, count 0 2006.285.22:47:40.03#ibcon#end of sib2, iclass 19, count 0 2006.285.22:47:40.03#ibcon#*after write, iclass 19, count 0 2006.285.22:47:40.03#ibcon#*before return 0, iclass 19, count 0 2006.285.22:47:40.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:47:40.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.22:47:40.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:47:40.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:47:40.03$vck44/vb=3,4 2006.285.22:47:40.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.22:47:40.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.22:47:40.03#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:40.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:47:40.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:47:40.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:47:40.09#ibcon#enter wrdev, iclass 21, count 2 2006.285.22:47:40.09#ibcon#first serial, iclass 21, count 2 2006.285.22:47:40.09#ibcon#enter sib2, iclass 21, count 2 2006.285.22:47:40.09#ibcon#flushed, iclass 21, count 2 2006.285.22:47:40.09#ibcon#about to write, iclass 21, count 2 2006.285.22:47:40.09#ibcon#wrote, iclass 21, count 2 2006.285.22:47:40.09#ibcon#about to read 3, iclass 21, count 2 2006.285.22:47:40.11#ibcon#read 3, iclass 21, count 2 2006.285.22:47:40.11#ibcon#about to read 4, iclass 21, count 2 2006.285.22:47:40.11#ibcon#read 4, iclass 21, count 2 2006.285.22:47:40.11#ibcon#about to read 5, iclass 21, count 2 2006.285.22:47:40.11#ibcon#read 5, iclass 21, count 2 2006.285.22:47:40.11#ibcon#about to read 6, iclass 21, count 2 2006.285.22:47:40.11#ibcon#read 6, iclass 21, count 2 2006.285.22:47:40.11#ibcon#end of sib2, iclass 21, count 2 2006.285.22:47:40.11#ibcon#*mode == 0, iclass 21, count 2 2006.285.22:47:40.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.22:47:40.11#ibcon#[27=AT03-04\r\n] 2006.285.22:47:40.11#ibcon#*before write, iclass 21, count 2 2006.285.22:47:40.11#ibcon#enter sib2, iclass 21, count 2 2006.285.22:47:40.11#ibcon#flushed, iclass 21, count 2 2006.285.22:47:40.11#ibcon#about to write, iclass 21, count 2 2006.285.22:47:40.11#ibcon#wrote, iclass 21, count 2 2006.285.22:47:40.11#ibcon#about to read 3, iclass 21, count 2 2006.285.22:47:40.14#ibcon#read 3, iclass 21, count 2 2006.285.22:47:40.14#ibcon#about to read 4, iclass 21, count 2 2006.285.22:47:40.14#ibcon#read 4, iclass 21, count 2 2006.285.22:47:40.14#ibcon#about to read 5, iclass 21, count 2 2006.285.22:47:40.14#ibcon#read 5, iclass 21, count 2 2006.285.22:47:40.14#ibcon#about to read 6, iclass 21, count 2 2006.285.22:47:40.14#ibcon#read 6, iclass 21, count 2 2006.285.22:47:40.14#ibcon#end of sib2, iclass 21, count 2 2006.285.22:47:40.14#ibcon#*after write, iclass 21, count 2 2006.285.22:47:40.14#ibcon#*before return 0, iclass 21, count 2 2006.285.22:47:40.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:47:40.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.22:47:40.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.22:47:40.14#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:40.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:47:40.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:47:40.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:47:40.26#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:47:40.26#ibcon#first serial, iclass 21, count 0 2006.285.22:47:40.26#ibcon#enter sib2, iclass 21, count 0 2006.285.22:47:40.26#ibcon#flushed, iclass 21, count 0 2006.285.22:47:40.26#ibcon#about to write, iclass 21, count 0 2006.285.22:47:40.26#ibcon#wrote, iclass 21, count 0 2006.285.22:47:40.26#ibcon#about to read 3, iclass 21, count 0 2006.285.22:47:40.28#ibcon#read 3, iclass 21, count 0 2006.285.22:47:40.28#ibcon#about to read 4, iclass 21, count 0 2006.285.22:47:40.28#ibcon#read 4, iclass 21, count 0 2006.285.22:47:40.28#ibcon#about to read 5, iclass 21, count 0 2006.285.22:47:40.28#ibcon#read 5, iclass 21, count 0 2006.285.22:47:40.28#ibcon#about to read 6, iclass 21, count 0 2006.285.22:47:40.28#ibcon#read 6, iclass 21, count 0 2006.285.22:47:40.28#ibcon#end of sib2, iclass 21, count 0 2006.285.22:47:40.28#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:47:40.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:47:40.28#ibcon#[27=USB\r\n] 2006.285.22:47:40.28#ibcon#*before write, iclass 21, count 0 2006.285.22:47:40.28#ibcon#enter sib2, iclass 21, count 0 2006.285.22:47:40.28#ibcon#flushed, iclass 21, count 0 2006.285.22:47:40.28#ibcon#about to write, iclass 21, count 0 2006.285.22:47:40.28#ibcon#wrote, iclass 21, count 0 2006.285.22:47:40.28#ibcon#about to read 3, iclass 21, count 0 2006.285.22:47:40.31#ibcon#read 3, iclass 21, count 0 2006.285.22:47:40.31#ibcon#about to read 4, iclass 21, count 0 2006.285.22:47:40.31#ibcon#read 4, iclass 21, count 0 2006.285.22:47:40.31#ibcon#about to read 5, iclass 21, count 0 2006.285.22:47:40.31#ibcon#read 5, iclass 21, count 0 2006.285.22:47:40.31#ibcon#about to read 6, iclass 21, count 0 2006.285.22:47:40.31#ibcon#read 6, iclass 21, count 0 2006.285.22:47:40.31#ibcon#end of sib2, iclass 21, count 0 2006.285.22:47:40.31#ibcon#*after write, iclass 21, count 0 2006.285.22:47:40.31#ibcon#*before return 0, iclass 21, count 0 2006.285.22:47:40.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:47:40.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.22:47:40.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:47:40.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:47:40.31$vck44/vblo=4,679.99 2006.285.22:47:40.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.22:47:40.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.22:47:40.31#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:40.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:47:40.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:47:40.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:47:40.31#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:47:40.31#ibcon#first serial, iclass 23, count 0 2006.285.22:47:40.31#ibcon#enter sib2, iclass 23, count 0 2006.285.22:47:40.31#ibcon#flushed, iclass 23, count 0 2006.285.22:47:40.31#ibcon#about to write, iclass 23, count 0 2006.285.22:47:40.31#ibcon#wrote, iclass 23, count 0 2006.285.22:47:40.31#ibcon#about to read 3, iclass 23, count 0 2006.285.22:47:40.33#ibcon#read 3, iclass 23, count 0 2006.285.22:47:40.33#ibcon#about to read 4, iclass 23, count 0 2006.285.22:47:40.33#ibcon#read 4, iclass 23, count 0 2006.285.22:47:40.33#ibcon#about to read 5, iclass 23, count 0 2006.285.22:47:40.33#ibcon#read 5, iclass 23, count 0 2006.285.22:47:40.33#ibcon#about to read 6, iclass 23, count 0 2006.285.22:47:40.33#ibcon#read 6, iclass 23, count 0 2006.285.22:47:40.33#ibcon#end of sib2, iclass 23, count 0 2006.285.22:47:40.33#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:47:40.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:47:40.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.22:47:40.33#ibcon#*before write, iclass 23, count 0 2006.285.22:47:40.33#ibcon#enter sib2, iclass 23, count 0 2006.285.22:47:40.33#ibcon#flushed, iclass 23, count 0 2006.285.22:47:40.33#ibcon#about to write, iclass 23, count 0 2006.285.22:47:40.33#ibcon#wrote, iclass 23, count 0 2006.285.22:47:40.33#ibcon#about to read 3, iclass 23, count 0 2006.285.22:47:40.37#ibcon#read 3, iclass 23, count 0 2006.285.22:47:40.37#ibcon#about to read 4, iclass 23, count 0 2006.285.22:47:40.37#ibcon#read 4, iclass 23, count 0 2006.285.22:47:40.37#ibcon#about to read 5, iclass 23, count 0 2006.285.22:47:40.37#ibcon#read 5, iclass 23, count 0 2006.285.22:47:40.37#ibcon#about to read 6, iclass 23, count 0 2006.285.22:47:40.37#ibcon#read 6, iclass 23, count 0 2006.285.22:47:40.37#ibcon#end of sib2, iclass 23, count 0 2006.285.22:47:40.37#ibcon#*after write, iclass 23, count 0 2006.285.22:47:40.37#ibcon#*before return 0, iclass 23, count 0 2006.285.22:47:40.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:47:40.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.22:47:40.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:47:40.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:47:40.37$vck44/vb=4,5 2006.285.22:47:40.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.22:47:40.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.22:47:40.37#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:40.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:47:40.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:47:40.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:47:40.43#ibcon#enter wrdev, iclass 25, count 2 2006.285.22:47:40.43#ibcon#first serial, iclass 25, count 2 2006.285.22:47:40.43#ibcon#enter sib2, iclass 25, count 2 2006.285.22:47:40.43#ibcon#flushed, iclass 25, count 2 2006.285.22:47:40.43#ibcon#about to write, iclass 25, count 2 2006.285.22:47:40.43#ibcon#wrote, iclass 25, count 2 2006.285.22:47:40.43#ibcon#about to read 3, iclass 25, count 2 2006.285.22:47:40.45#ibcon#read 3, iclass 25, count 2 2006.285.22:47:40.45#ibcon#about to read 4, iclass 25, count 2 2006.285.22:47:40.45#ibcon#read 4, iclass 25, count 2 2006.285.22:47:40.45#ibcon#about to read 5, iclass 25, count 2 2006.285.22:47:40.45#ibcon#read 5, iclass 25, count 2 2006.285.22:47:40.45#ibcon#about to read 6, iclass 25, count 2 2006.285.22:47:40.45#ibcon#read 6, iclass 25, count 2 2006.285.22:47:40.45#ibcon#end of sib2, iclass 25, count 2 2006.285.22:47:40.45#ibcon#*mode == 0, iclass 25, count 2 2006.285.22:47:40.45#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.22:47:40.45#ibcon#[27=AT04-05\r\n] 2006.285.22:47:40.45#ibcon#*before write, iclass 25, count 2 2006.285.22:47:40.45#ibcon#enter sib2, iclass 25, count 2 2006.285.22:47:40.45#ibcon#flushed, iclass 25, count 2 2006.285.22:47:40.45#ibcon#about to write, iclass 25, count 2 2006.285.22:47:40.45#ibcon#wrote, iclass 25, count 2 2006.285.22:47:40.45#ibcon#about to read 3, iclass 25, count 2 2006.285.22:47:40.48#ibcon#read 3, iclass 25, count 2 2006.285.22:47:40.48#ibcon#about to read 4, iclass 25, count 2 2006.285.22:47:40.48#ibcon#read 4, iclass 25, count 2 2006.285.22:47:40.48#ibcon#about to read 5, iclass 25, count 2 2006.285.22:47:40.48#ibcon#read 5, iclass 25, count 2 2006.285.22:47:40.48#ibcon#about to read 6, iclass 25, count 2 2006.285.22:47:40.48#ibcon#read 6, iclass 25, count 2 2006.285.22:47:40.48#ibcon#end of sib2, iclass 25, count 2 2006.285.22:47:40.48#ibcon#*after write, iclass 25, count 2 2006.285.22:47:40.48#ibcon#*before return 0, iclass 25, count 2 2006.285.22:47:40.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:47:40.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.22:47:40.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.22:47:40.48#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:40.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:47:40.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:47:40.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:47:40.60#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:47:40.60#ibcon#first serial, iclass 25, count 0 2006.285.22:47:40.60#ibcon#enter sib2, iclass 25, count 0 2006.285.22:47:40.60#ibcon#flushed, iclass 25, count 0 2006.285.22:47:40.60#ibcon#about to write, iclass 25, count 0 2006.285.22:47:40.60#ibcon#wrote, iclass 25, count 0 2006.285.22:47:40.60#ibcon#about to read 3, iclass 25, count 0 2006.285.22:47:40.62#ibcon#read 3, iclass 25, count 0 2006.285.22:47:40.62#ibcon#about to read 4, iclass 25, count 0 2006.285.22:47:40.62#ibcon#read 4, iclass 25, count 0 2006.285.22:47:40.62#ibcon#about to read 5, iclass 25, count 0 2006.285.22:47:40.62#ibcon#read 5, iclass 25, count 0 2006.285.22:47:40.62#ibcon#about to read 6, iclass 25, count 0 2006.285.22:47:40.62#ibcon#read 6, iclass 25, count 0 2006.285.22:47:40.62#ibcon#end of sib2, iclass 25, count 0 2006.285.22:47:40.62#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:47:40.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:47:40.62#ibcon#[27=USB\r\n] 2006.285.22:47:40.62#ibcon#*before write, iclass 25, count 0 2006.285.22:47:40.62#ibcon#enter sib2, iclass 25, count 0 2006.285.22:47:40.62#ibcon#flushed, iclass 25, count 0 2006.285.22:47:40.62#ibcon#about to write, iclass 25, count 0 2006.285.22:47:40.62#ibcon#wrote, iclass 25, count 0 2006.285.22:47:40.62#ibcon#about to read 3, iclass 25, count 0 2006.285.22:47:40.65#ibcon#read 3, iclass 25, count 0 2006.285.22:47:40.65#ibcon#about to read 4, iclass 25, count 0 2006.285.22:47:40.65#ibcon#read 4, iclass 25, count 0 2006.285.22:47:40.65#ibcon#about to read 5, iclass 25, count 0 2006.285.22:47:40.65#ibcon#read 5, iclass 25, count 0 2006.285.22:47:40.65#ibcon#about to read 6, iclass 25, count 0 2006.285.22:47:40.65#ibcon#read 6, iclass 25, count 0 2006.285.22:47:40.65#ibcon#end of sib2, iclass 25, count 0 2006.285.22:47:40.65#ibcon#*after write, iclass 25, count 0 2006.285.22:47:40.65#ibcon#*before return 0, iclass 25, count 0 2006.285.22:47:40.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:47:40.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.22:47:40.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:47:40.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:47:40.65$vck44/vblo=5,709.99 2006.285.22:47:40.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.22:47:40.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.22:47:40.65#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:40.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:47:40.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:47:40.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:47:40.65#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:47:40.65#ibcon#first serial, iclass 27, count 0 2006.285.22:47:40.65#ibcon#enter sib2, iclass 27, count 0 2006.285.22:47:40.65#ibcon#flushed, iclass 27, count 0 2006.285.22:47:40.65#ibcon#about to write, iclass 27, count 0 2006.285.22:47:40.65#ibcon#wrote, iclass 27, count 0 2006.285.22:47:40.65#ibcon#about to read 3, iclass 27, count 0 2006.285.22:47:40.67#ibcon#read 3, iclass 27, count 0 2006.285.22:47:40.67#ibcon#about to read 4, iclass 27, count 0 2006.285.22:47:40.67#ibcon#read 4, iclass 27, count 0 2006.285.22:47:40.67#ibcon#about to read 5, iclass 27, count 0 2006.285.22:47:40.67#ibcon#read 5, iclass 27, count 0 2006.285.22:47:40.67#ibcon#about to read 6, iclass 27, count 0 2006.285.22:47:40.67#ibcon#read 6, iclass 27, count 0 2006.285.22:47:40.67#ibcon#end of sib2, iclass 27, count 0 2006.285.22:47:40.67#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:47:40.67#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:47:40.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.22:47:40.67#ibcon#*before write, iclass 27, count 0 2006.285.22:47:40.67#ibcon#enter sib2, iclass 27, count 0 2006.285.22:47:40.67#ibcon#flushed, iclass 27, count 0 2006.285.22:47:40.67#ibcon#about to write, iclass 27, count 0 2006.285.22:47:40.67#ibcon#wrote, iclass 27, count 0 2006.285.22:47:40.67#ibcon#about to read 3, iclass 27, count 0 2006.285.22:47:40.71#ibcon#read 3, iclass 27, count 0 2006.285.22:47:40.71#ibcon#about to read 4, iclass 27, count 0 2006.285.22:47:40.71#ibcon#read 4, iclass 27, count 0 2006.285.22:47:40.71#ibcon#about to read 5, iclass 27, count 0 2006.285.22:47:40.71#ibcon#read 5, iclass 27, count 0 2006.285.22:47:40.71#ibcon#about to read 6, iclass 27, count 0 2006.285.22:47:40.71#ibcon#read 6, iclass 27, count 0 2006.285.22:47:40.71#ibcon#end of sib2, iclass 27, count 0 2006.285.22:47:40.71#ibcon#*after write, iclass 27, count 0 2006.285.22:47:40.71#ibcon#*before return 0, iclass 27, count 0 2006.285.22:47:40.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:47:40.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.22:47:40.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:47:40.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:47:40.71$vck44/vb=5,4 2006.285.22:47:40.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.22:47:40.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.22:47:40.71#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:40.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:47:40.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:47:40.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:47:40.77#ibcon#enter wrdev, iclass 29, count 2 2006.285.22:47:40.77#ibcon#first serial, iclass 29, count 2 2006.285.22:47:40.77#ibcon#enter sib2, iclass 29, count 2 2006.285.22:47:40.77#ibcon#flushed, iclass 29, count 2 2006.285.22:47:40.77#ibcon#about to write, iclass 29, count 2 2006.285.22:47:40.77#ibcon#wrote, iclass 29, count 2 2006.285.22:47:40.77#ibcon#about to read 3, iclass 29, count 2 2006.285.22:47:40.79#ibcon#read 3, iclass 29, count 2 2006.285.22:47:40.79#ibcon#about to read 4, iclass 29, count 2 2006.285.22:47:40.79#ibcon#read 4, iclass 29, count 2 2006.285.22:47:40.79#ibcon#about to read 5, iclass 29, count 2 2006.285.22:47:40.79#ibcon#read 5, iclass 29, count 2 2006.285.22:47:40.79#ibcon#about to read 6, iclass 29, count 2 2006.285.22:47:40.79#ibcon#read 6, iclass 29, count 2 2006.285.22:47:40.79#ibcon#end of sib2, iclass 29, count 2 2006.285.22:47:40.79#ibcon#*mode == 0, iclass 29, count 2 2006.285.22:47:40.79#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.22:47:40.79#ibcon#[27=AT05-04\r\n] 2006.285.22:47:40.79#ibcon#*before write, iclass 29, count 2 2006.285.22:47:40.79#ibcon#enter sib2, iclass 29, count 2 2006.285.22:47:40.79#ibcon#flushed, iclass 29, count 2 2006.285.22:47:40.79#ibcon#about to write, iclass 29, count 2 2006.285.22:47:40.79#ibcon#wrote, iclass 29, count 2 2006.285.22:47:40.79#ibcon#about to read 3, iclass 29, count 2 2006.285.22:47:40.82#ibcon#read 3, iclass 29, count 2 2006.285.22:47:40.82#ibcon#about to read 4, iclass 29, count 2 2006.285.22:47:40.82#ibcon#read 4, iclass 29, count 2 2006.285.22:47:40.82#ibcon#about to read 5, iclass 29, count 2 2006.285.22:47:40.82#ibcon#read 5, iclass 29, count 2 2006.285.22:47:40.82#ibcon#about to read 6, iclass 29, count 2 2006.285.22:47:40.82#ibcon#read 6, iclass 29, count 2 2006.285.22:47:40.82#ibcon#end of sib2, iclass 29, count 2 2006.285.22:47:40.82#ibcon#*after write, iclass 29, count 2 2006.285.22:47:40.82#ibcon#*before return 0, iclass 29, count 2 2006.285.22:47:40.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:47:40.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.22:47:40.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.22:47:40.82#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:40.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:47:40.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:47:40.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:47:40.94#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:47:40.94#ibcon#first serial, iclass 29, count 0 2006.285.22:47:40.94#ibcon#enter sib2, iclass 29, count 0 2006.285.22:47:40.94#ibcon#flushed, iclass 29, count 0 2006.285.22:47:40.94#ibcon#about to write, iclass 29, count 0 2006.285.22:47:40.94#ibcon#wrote, iclass 29, count 0 2006.285.22:47:40.94#ibcon#about to read 3, iclass 29, count 0 2006.285.22:47:40.96#ibcon#read 3, iclass 29, count 0 2006.285.22:47:40.96#ibcon#about to read 4, iclass 29, count 0 2006.285.22:47:40.96#ibcon#read 4, iclass 29, count 0 2006.285.22:47:40.96#ibcon#about to read 5, iclass 29, count 0 2006.285.22:47:40.96#ibcon#read 5, iclass 29, count 0 2006.285.22:47:40.96#ibcon#about to read 6, iclass 29, count 0 2006.285.22:47:40.96#ibcon#read 6, iclass 29, count 0 2006.285.22:47:40.96#ibcon#end of sib2, iclass 29, count 0 2006.285.22:47:40.96#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:47:40.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:47:40.96#ibcon#[27=USB\r\n] 2006.285.22:47:40.96#ibcon#*before write, iclass 29, count 0 2006.285.22:47:40.96#ibcon#enter sib2, iclass 29, count 0 2006.285.22:47:40.96#ibcon#flushed, iclass 29, count 0 2006.285.22:47:40.96#ibcon#about to write, iclass 29, count 0 2006.285.22:47:40.96#ibcon#wrote, iclass 29, count 0 2006.285.22:47:40.96#ibcon#about to read 3, iclass 29, count 0 2006.285.22:47:40.99#ibcon#read 3, iclass 29, count 0 2006.285.22:47:40.99#ibcon#about to read 4, iclass 29, count 0 2006.285.22:47:40.99#ibcon#read 4, iclass 29, count 0 2006.285.22:47:40.99#ibcon#about to read 5, iclass 29, count 0 2006.285.22:47:40.99#ibcon#read 5, iclass 29, count 0 2006.285.22:47:40.99#ibcon#about to read 6, iclass 29, count 0 2006.285.22:47:40.99#ibcon#read 6, iclass 29, count 0 2006.285.22:47:40.99#ibcon#end of sib2, iclass 29, count 0 2006.285.22:47:40.99#ibcon#*after write, iclass 29, count 0 2006.285.22:47:40.99#ibcon#*before return 0, iclass 29, count 0 2006.285.22:47:40.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:47:40.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.22:47:40.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:47:40.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:47:40.99$vck44/vblo=6,719.99 2006.285.22:47:40.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.22:47:40.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.22:47:40.99#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:40.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:47:40.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:47:40.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:47:40.99#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:47:40.99#ibcon#first serial, iclass 31, count 0 2006.285.22:47:40.99#ibcon#enter sib2, iclass 31, count 0 2006.285.22:47:40.99#ibcon#flushed, iclass 31, count 0 2006.285.22:47:40.99#ibcon#about to write, iclass 31, count 0 2006.285.22:47:40.99#ibcon#wrote, iclass 31, count 0 2006.285.22:47:40.99#ibcon#about to read 3, iclass 31, count 0 2006.285.22:47:41.01#ibcon#read 3, iclass 31, count 0 2006.285.22:47:41.01#ibcon#about to read 4, iclass 31, count 0 2006.285.22:47:41.01#ibcon#read 4, iclass 31, count 0 2006.285.22:47:41.01#ibcon#about to read 5, iclass 31, count 0 2006.285.22:47:41.01#ibcon#read 5, iclass 31, count 0 2006.285.22:47:41.01#ibcon#about to read 6, iclass 31, count 0 2006.285.22:47:41.01#ibcon#read 6, iclass 31, count 0 2006.285.22:47:41.01#ibcon#end of sib2, iclass 31, count 0 2006.285.22:47:41.01#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:47:41.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:47:41.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.22:47:41.01#ibcon#*before write, iclass 31, count 0 2006.285.22:47:41.01#ibcon#enter sib2, iclass 31, count 0 2006.285.22:47:41.01#ibcon#flushed, iclass 31, count 0 2006.285.22:47:41.01#ibcon#about to write, iclass 31, count 0 2006.285.22:47:41.01#ibcon#wrote, iclass 31, count 0 2006.285.22:47:41.01#ibcon#about to read 3, iclass 31, count 0 2006.285.22:47:41.05#ibcon#read 3, iclass 31, count 0 2006.285.22:47:41.05#ibcon#about to read 4, iclass 31, count 0 2006.285.22:47:41.05#ibcon#read 4, iclass 31, count 0 2006.285.22:47:41.05#ibcon#about to read 5, iclass 31, count 0 2006.285.22:47:41.05#ibcon#read 5, iclass 31, count 0 2006.285.22:47:41.05#ibcon#about to read 6, iclass 31, count 0 2006.285.22:47:41.05#ibcon#read 6, iclass 31, count 0 2006.285.22:47:41.05#ibcon#end of sib2, iclass 31, count 0 2006.285.22:47:41.05#ibcon#*after write, iclass 31, count 0 2006.285.22:47:41.05#ibcon#*before return 0, iclass 31, count 0 2006.285.22:47:41.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:47:41.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:47:41.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:47:41.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:47:41.05$vck44/vb=6,3 2006.285.22:47:41.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.22:47:41.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.22:47:41.05#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:41.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:47:41.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:47:41.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:47:41.11#ibcon#enter wrdev, iclass 33, count 2 2006.285.22:47:41.11#ibcon#first serial, iclass 33, count 2 2006.285.22:47:41.11#ibcon#enter sib2, iclass 33, count 2 2006.285.22:47:41.11#ibcon#flushed, iclass 33, count 2 2006.285.22:47:41.11#ibcon#about to write, iclass 33, count 2 2006.285.22:47:41.11#ibcon#wrote, iclass 33, count 2 2006.285.22:47:41.11#ibcon#about to read 3, iclass 33, count 2 2006.285.22:47:41.13#ibcon#read 3, iclass 33, count 2 2006.285.22:47:41.13#ibcon#about to read 4, iclass 33, count 2 2006.285.22:47:41.13#ibcon#read 4, iclass 33, count 2 2006.285.22:47:41.13#ibcon#about to read 5, iclass 33, count 2 2006.285.22:47:41.13#ibcon#read 5, iclass 33, count 2 2006.285.22:47:41.13#ibcon#about to read 6, iclass 33, count 2 2006.285.22:47:41.13#ibcon#read 6, iclass 33, count 2 2006.285.22:47:41.13#ibcon#end of sib2, iclass 33, count 2 2006.285.22:47:41.13#ibcon#*mode == 0, iclass 33, count 2 2006.285.22:47:41.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.22:47:41.13#ibcon#[27=AT06-03\r\n] 2006.285.22:47:41.13#ibcon#*before write, iclass 33, count 2 2006.285.22:47:41.13#ibcon#enter sib2, iclass 33, count 2 2006.285.22:47:41.13#ibcon#flushed, iclass 33, count 2 2006.285.22:47:41.13#ibcon#about to write, iclass 33, count 2 2006.285.22:47:41.13#ibcon#wrote, iclass 33, count 2 2006.285.22:47:41.13#ibcon#about to read 3, iclass 33, count 2 2006.285.22:47:41.16#ibcon#read 3, iclass 33, count 2 2006.285.22:47:41.16#ibcon#about to read 4, iclass 33, count 2 2006.285.22:47:41.16#ibcon#read 4, iclass 33, count 2 2006.285.22:47:41.16#ibcon#about to read 5, iclass 33, count 2 2006.285.22:47:41.16#ibcon#read 5, iclass 33, count 2 2006.285.22:47:41.16#ibcon#about to read 6, iclass 33, count 2 2006.285.22:47:41.16#ibcon#read 6, iclass 33, count 2 2006.285.22:47:41.16#ibcon#end of sib2, iclass 33, count 2 2006.285.22:47:41.16#ibcon#*after write, iclass 33, count 2 2006.285.22:47:41.16#ibcon#*before return 0, iclass 33, count 2 2006.285.22:47:41.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:47:41.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.22:47:41.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.22:47:41.16#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:41.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:47:41.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:47:41.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:47:41.28#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:47:41.28#ibcon#first serial, iclass 33, count 0 2006.285.22:47:41.28#ibcon#enter sib2, iclass 33, count 0 2006.285.22:47:41.28#ibcon#flushed, iclass 33, count 0 2006.285.22:47:41.28#ibcon#about to write, iclass 33, count 0 2006.285.22:47:41.28#ibcon#wrote, iclass 33, count 0 2006.285.22:47:41.28#ibcon#about to read 3, iclass 33, count 0 2006.285.22:47:41.30#ibcon#read 3, iclass 33, count 0 2006.285.22:47:41.30#ibcon#about to read 4, iclass 33, count 0 2006.285.22:47:41.30#ibcon#read 4, iclass 33, count 0 2006.285.22:47:41.30#ibcon#about to read 5, iclass 33, count 0 2006.285.22:47:41.30#ibcon#read 5, iclass 33, count 0 2006.285.22:47:41.30#ibcon#about to read 6, iclass 33, count 0 2006.285.22:47:41.30#ibcon#read 6, iclass 33, count 0 2006.285.22:47:41.30#ibcon#end of sib2, iclass 33, count 0 2006.285.22:47:41.30#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:47:41.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:47:41.30#ibcon#[27=USB\r\n] 2006.285.22:47:41.30#ibcon#*before write, iclass 33, count 0 2006.285.22:47:41.30#ibcon#enter sib2, iclass 33, count 0 2006.285.22:47:41.30#ibcon#flushed, iclass 33, count 0 2006.285.22:47:41.30#ibcon#about to write, iclass 33, count 0 2006.285.22:47:41.30#ibcon#wrote, iclass 33, count 0 2006.285.22:47:41.30#ibcon#about to read 3, iclass 33, count 0 2006.285.22:47:41.33#ibcon#read 3, iclass 33, count 0 2006.285.22:47:41.33#ibcon#about to read 4, iclass 33, count 0 2006.285.22:47:41.33#ibcon#read 4, iclass 33, count 0 2006.285.22:47:41.33#ibcon#about to read 5, iclass 33, count 0 2006.285.22:47:41.33#ibcon#read 5, iclass 33, count 0 2006.285.22:47:41.33#ibcon#about to read 6, iclass 33, count 0 2006.285.22:47:41.33#ibcon#read 6, iclass 33, count 0 2006.285.22:47:41.33#ibcon#end of sib2, iclass 33, count 0 2006.285.22:47:41.33#ibcon#*after write, iclass 33, count 0 2006.285.22:47:41.33#ibcon#*before return 0, iclass 33, count 0 2006.285.22:47:41.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:47:41.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.22:47:41.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:47:41.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:47:41.33$vck44/vblo=7,734.99 2006.285.22:47:41.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.22:47:41.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.22:47:41.33#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:41.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:47:41.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:47:41.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:47:41.33#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:47:41.33#ibcon#first serial, iclass 35, count 0 2006.285.22:47:41.33#ibcon#enter sib2, iclass 35, count 0 2006.285.22:47:41.33#ibcon#flushed, iclass 35, count 0 2006.285.22:47:41.33#ibcon#about to write, iclass 35, count 0 2006.285.22:47:41.33#ibcon#wrote, iclass 35, count 0 2006.285.22:47:41.33#ibcon#about to read 3, iclass 35, count 0 2006.285.22:47:41.35#ibcon#read 3, iclass 35, count 0 2006.285.22:47:41.35#ibcon#about to read 4, iclass 35, count 0 2006.285.22:47:41.35#ibcon#read 4, iclass 35, count 0 2006.285.22:47:41.35#ibcon#about to read 5, iclass 35, count 0 2006.285.22:47:41.35#ibcon#read 5, iclass 35, count 0 2006.285.22:47:41.35#ibcon#about to read 6, iclass 35, count 0 2006.285.22:47:41.35#ibcon#read 6, iclass 35, count 0 2006.285.22:47:41.35#ibcon#end of sib2, iclass 35, count 0 2006.285.22:47:41.35#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:47:41.35#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:47:41.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.22:47:41.35#ibcon#*before write, iclass 35, count 0 2006.285.22:47:41.35#ibcon#enter sib2, iclass 35, count 0 2006.285.22:47:41.35#ibcon#flushed, iclass 35, count 0 2006.285.22:47:41.35#ibcon#about to write, iclass 35, count 0 2006.285.22:47:41.35#ibcon#wrote, iclass 35, count 0 2006.285.22:47:41.35#ibcon#about to read 3, iclass 35, count 0 2006.285.22:47:41.39#ibcon#read 3, iclass 35, count 0 2006.285.22:47:41.39#ibcon#about to read 4, iclass 35, count 0 2006.285.22:47:41.39#ibcon#read 4, iclass 35, count 0 2006.285.22:47:41.39#ibcon#about to read 5, iclass 35, count 0 2006.285.22:47:41.39#ibcon#read 5, iclass 35, count 0 2006.285.22:47:41.39#ibcon#about to read 6, iclass 35, count 0 2006.285.22:47:41.39#ibcon#read 6, iclass 35, count 0 2006.285.22:47:41.39#ibcon#end of sib2, iclass 35, count 0 2006.285.22:47:41.39#ibcon#*after write, iclass 35, count 0 2006.285.22:47:41.39#ibcon#*before return 0, iclass 35, count 0 2006.285.22:47:41.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:47:41.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.22:47:41.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:47:41.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:47:41.39$vck44/vb=7,4 2006.285.22:47:41.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.22:47:41.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.22:47:41.39#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:41.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:47:41.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:47:41.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:47:41.45#ibcon#enter wrdev, iclass 37, count 2 2006.285.22:47:41.45#ibcon#first serial, iclass 37, count 2 2006.285.22:47:41.45#ibcon#enter sib2, iclass 37, count 2 2006.285.22:47:41.45#ibcon#flushed, iclass 37, count 2 2006.285.22:47:41.45#ibcon#about to write, iclass 37, count 2 2006.285.22:47:41.45#ibcon#wrote, iclass 37, count 2 2006.285.22:47:41.45#ibcon#about to read 3, iclass 37, count 2 2006.285.22:47:41.47#ibcon#read 3, iclass 37, count 2 2006.285.22:47:41.47#ibcon#about to read 4, iclass 37, count 2 2006.285.22:47:41.47#ibcon#read 4, iclass 37, count 2 2006.285.22:47:41.47#ibcon#about to read 5, iclass 37, count 2 2006.285.22:47:41.47#ibcon#read 5, iclass 37, count 2 2006.285.22:47:41.47#ibcon#about to read 6, iclass 37, count 2 2006.285.22:47:41.47#ibcon#read 6, iclass 37, count 2 2006.285.22:47:41.47#ibcon#end of sib2, iclass 37, count 2 2006.285.22:47:41.47#ibcon#*mode == 0, iclass 37, count 2 2006.285.22:47:41.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.22:47:41.47#ibcon#[27=AT07-04\r\n] 2006.285.22:47:41.47#ibcon#*before write, iclass 37, count 2 2006.285.22:47:41.47#ibcon#enter sib2, iclass 37, count 2 2006.285.22:47:41.47#ibcon#flushed, iclass 37, count 2 2006.285.22:47:41.47#ibcon#about to write, iclass 37, count 2 2006.285.22:47:41.47#ibcon#wrote, iclass 37, count 2 2006.285.22:47:41.47#ibcon#about to read 3, iclass 37, count 2 2006.285.22:47:41.50#ibcon#read 3, iclass 37, count 2 2006.285.22:47:41.50#ibcon#about to read 4, iclass 37, count 2 2006.285.22:47:41.50#ibcon#read 4, iclass 37, count 2 2006.285.22:47:41.50#ibcon#about to read 5, iclass 37, count 2 2006.285.22:47:41.50#ibcon#read 5, iclass 37, count 2 2006.285.22:47:41.50#ibcon#about to read 6, iclass 37, count 2 2006.285.22:47:41.50#ibcon#read 6, iclass 37, count 2 2006.285.22:47:41.50#ibcon#end of sib2, iclass 37, count 2 2006.285.22:47:41.50#ibcon#*after write, iclass 37, count 2 2006.285.22:47:41.50#ibcon#*before return 0, iclass 37, count 2 2006.285.22:47:41.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:47:41.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.22:47:41.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.22:47:41.50#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:41.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:47:41.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:47:41.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:47:41.62#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:47:41.62#ibcon#first serial, iclass 37, count 0 2006.285.22:47:41.62#ibcon#enter sib2, iclass 37, count 0 2006.285.22:47:41.62#ibcon#flushed, iclass 37, count 0 2006.285.22:47:41.62#ibcon#about to write, iclass 37, count 0 2006.285.22:47:41.62#ibcon#wrote, iclass 37, count 0 2006.285.22:47:41.62#ibcon#about to read 3, iclass 37, count 0 2006.285.22:47:41.64#ibcon#read 3, iclass 37, count 0 2006.285.22:47:41.64#ibcon#about to read 4, iclass 37, count 0 2006.285.22:47:41.64#ibcon#read 4, iclass 37, count 0 2006.285.22:47:41.64#ibcon#about to read 5, iclass 37, count 0 2006.285.22:47:41.64#ibcon#read 5, iclass 37, count 0 2006.285.22:47:41.64#ibcon#about to read 6, iclass 37, count 0 2006.285.22:47:41.64#ibcon#read 6, iclass 37, count 0 2006.285.22:47:41.64#ibcon#end of sib2, iclass 37, count 0 2006.285.22:47:41.64#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:47:41.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:47:41.64#ibcon#[27=USB\r\n] 2006.285.22:47:41.64#ibcon#*before write, iclass 37, count 0 2006.285.22:47:41.64#ibcon#enter sib2, iclass 37, count 0 2006.285.22:47:41.64#ibcon#flushed, iclass 37, count 0 2006.285.22:47:41.64#ibcon#about to write, iclass 37, count 0 2006.285.22:47:41.64#ibcon#wrote, iclass 37, count 0 2006.285.22:47:41.64#ibcon#about to read 3, iclass 37, count 0 2006.285.22:47:41.67#ibcon#read 3, iclass 37, count 0 2006.285.22:47:41.67#ibcon#about to read 4, iclass 37, count 0 2006.285.22:47:41.67#ibcon#read 4, iclass 37, count 0 2006.285.22:47:41.67#ibcon#about to read 5, iclass 37, count 0 2006.285.22:47:41.67#ibcon#read 5, iclass 37, count 0 2006.285.22:47:41.67#ibcon#about to read 6, iclass 37, count 0 2006.285.22:47:41.67#ibcon#read 6, iclass 37, count 0 2006.285.22:47:41.67#ibcon#end of sib2, iclass 37, count 0 2006.285.22:47:41.67#ibcon#*after write, iclass 37, count 0 2006.285.22:47:41.67#ibcon#*before return 0, iclass 37, count 0 2006.285.22:47:41.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:47:41.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.22:47:41.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:47:41.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:47:41.67$vck44/vblo=8,744.99 2006.285.22:47:41.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.22:47:41.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.22:47:41.67#ibcon#ireg 17 cls_cnt 0 2006.285.22:47:41.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:47:41.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:47:41.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:47:41.67#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:47:41.67#ibcon#first serial, iclass 39, count 0 2006.285.22:47:41.67#ibcon#enter sib2, iclass 39, count 0 2006.285.22:47:41.67#ibcon#flushed, iclass 39, count 0 2006.285.22:47:41.67#ibcon#about to write, iclass 39, count 0 2006.285.22:47:41.67#ibcon#wrote, iclass 39, count 0 2006.285.22:47:41.67#ibcon#about to read 3, iclass 39, count 0 2006.285.22:47:41.69#ibcon#read 3, iclass 39, count 0 2006.285.22:47:41.69#ibcon#about to read 4, iclass 39, count 0 2006.285.22:47:41.69#ibcon#read 4, iclass 39, count 0 2006.285.22:47:41.69#ibcon#about to read 5, iclass 39, count 0 2006.285.22:47:41.69#ibcon#read 5, iclass 39, count 0 2006.285.22:47:41.69#ibcon#about to read 6, iclass 39, count 0 2006.285.22:47:41.69#ibcon#read 6, iclass 39, count 0 2006.285.22:47:41.69#ibcon#end of sib2, iclass 39, count 0 2006.285.22:47:41.69#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:47:41.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:47:41.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.22:47:41.69#ibcon#*before write, iclass 39, count 0 2006.285.22:47:41.69#ibcon#enter sib2, iclass 39, count 0 2006.285.22:47:41.69#ibcon#flushed, iclass 39, count 0 2006.285.22:47:41.69#ibcon#about to write, iclass 39, count 0 2006.285.22:47:41.69#ibcon#wrote, iclass 39, count 0 2006.285.22:47:41.69#ibcon#about to read 3, iclass 39, count 0 2006.285.22:47:41.73#ibcon#read 3, iclass 39, count 0 2006.285.22:47:41.73#ibcon#about to read 4, iclass 39, count 0 2006.285.22:47:41.73#ibcon#read 4, iclass 39, count 0 2006.285.22:47:41.73#ibcon#about to read 5, iclass 39, count 0 2006.285.22:47:41.73#ibcon#read 5, iclass 39, count 0 2006.285.22:47:41.73#ibcon#about to read 6, iclass 39, count 0 2006.285.22:47:41.73#ibcon#read 6, iclass 39, count 0 2006.285.22:47:41.73#ibcon#end of sib2, iclass 39, count 0 2006.285.22:47:41.73#ibcon#*after write, iclass 39, count 0 2006.285.22:47:41.73#ibcon#*before return 0, iclass 39, count 0 2006.285.22:47:41.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:47:41.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.22:47:41.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:47:41.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:47:41.73$vck44/vb=8,4 2006.285.22:47:41.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.22:47:41.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.22:47:41.73#ibcon#ireg 11 cls_cnt 2 2006.285.22:47:41.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:47:41.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:47:41.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:47:41.79#ibcon#enter wrdev, iclass 3, count 2 2006.285.22:47:41.79#ibcon#first serial, iclass 3, count 2 2006.285.22:47:41.79#ibcon#enter sib2, iclass 3, count 2 2006.285.22:47:41.79#ibcon#flushed, iclass 3, count 2 2006.285.22:47:41.79#ibcon#about to write, iclass 3, count 2 2006.285.22:47:41.79#ibcon#wrote, iclass 3, count 2 2006.285.22:47:41.79#ibcon#about to read 3, iclass 3, count 2 2006.285.22:47:41.81#ibcon#read 3, iclass 3, count 2 2006.285.22:47:41.81#ibcon#about to read 4, iclass 3, count 2 2006.285.22:47:41.81#ibcon#read 4, iclass 3, count 2 2006.285.22:47:41.81#ibcon#about to read 5, iclass 3, count 2 2006.285.22:47:41.81#ibcon#read 5, iclass 3, count 2 2006.285.22:47:41.81#ibcon#about to read 6, iclass 3, count 2 2006.285.22:47:41.81#ibcon#read 6, iclass 3, count 2 2006.285.22:47:41.81#ibcon#end of sib2, iclass 3, count 2 2006.285.22:47:41.81#ibcon#*mode == 0, iclass 3, count 2 2006.285.22:47:41.81#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.22:47:41.81#ibcon#[27=AT08-04\r\n] 2006.285.22:47:41.81#ibcon#*before write, iclass 3, count 2 2006.285.22:47:41.81#ibcon#enter sib2, iclass 3, count 2 2006.285.22:47:41.81#ibcon#flushed, iclass 3, count 2 2006.285.22:47:41.81#ibcon#about to write, iclass 3, count 2 2006.285.22:47:41.81#ibcon#wrote, iclass 3, count 2 2006.285.22:47:41.81#ibcon#about to read 3, iclass 3, count 2 2006.285.22:47:41.84#ibcon#read 3, iclass 3, count 2 2006.285.22:47:41.84#ibcon#about to read 4, iclass 3, count 2 2006.285.22:47:41.84#ibcon#read 4, iclass 3, count 2 2006.285.22:47:41.84#ibcon#about to read 5, iclass 3, count 2 2006.285.22:47:41.84#ibcon#read 5, iclass 3, count 2 2006.285.22:47:41.84#ibcon#about to read 6, iclass 3, count 2 2006.285.22:47:41.84#ibcon#read 6, iclass 3, count 2 2006.285.22:47:41.84#ibcon#end of sib2, iclass 3, count 2 2006.285.22:47:41.84#ibcon#*after write, iclass 3, count 2 2006.285.22:47:41.84#ibcon#*before return 0, iclass 3, count 2 2006.285.22:47:41.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:47:41.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.22:47:41.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.22:47:41.84#ibcon#ireg 7 cls_cnt 0 2006.285.22:47:41.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:47:41.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:47:41.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:47:41.96#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:47:41.96#ibcon#first serial, iclass 3, count 0 2006.285.22:47:41.96#ibcon#enter sib2, iclass 3, count 0 2006.285.22:47:41.96#ibcon#flushed, iclass 3, count 0 2006.285.22:47:41.96#ibcon#about to write, iclass 3, count 0 2006.285.22:47:41.96#ibcon#wrote, iclass 3, count 0 2006.285.22:47:41.96#ibcon#about to read 3, iclass 3, count 0 2006.285.22:47:41.98#ibcon#read 3, iclass 3, count 0 2006.285.22:47:41.98#ibcon#about to read 4, iclass 3, count 0 2006.285.22:47:41.98#ibcon#read 4, iclass 3, count 0 2006.285.22:47:41.98#ibcon#about to read 5, iclass 3, count 0 2006.285.22:47:41.98#ibcon#read 5, iclass 3, count 0 2006.285.22:47:41.98#ibcon#about to read 6, iclass 3, count 0 2006.285.22:47:41.98#ibcon#read 6, iclass 3, count 0 2006.285.22:47:41.98#ibcon#end of sib2, iclass 3, count 0 2006.285.22:47:41.98#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:47:41.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:47:41.98#ibcon#[27=USB\r\n] 2006.285.22:47:41.98#ibcon#*before write, iclass 3, count 0 2006.285.22:47:41.98#ibcon#enter sib2, iclass 3, count 0 2006.285.22:47:41.98#ibcon#flushed, iclass 3, count 0 2006.285.22:47:41.98#ibcon#about to write, iclass 3, count 0 2006.285.22:47:41.98#ibcon#wrote, iclass 3, count 0 2006.285.22:47:41.98#ibcon#about to read 3, iclass 3, count 0 2006.285.22:47:42.01#ibcon#read 3, iclass 3, count 0 2006.285.22:47:42.01#ibcon#about to read 4, iclass 3, count 0 2006.285.22:47:42.01#ibcon#read 4, iclass 3, count 0 2006.285.22:47:42.01#ibcon#about to read 5, iclass 3, count 0 2006.285.22:47:42.01#ibcon#read 5, iclass 3, count 0 2006.285.22:47:42.01#ibcon#about to read 6, iclass 3, count 0 2006.285.22:47:42.01#ibcon#read 6, iclass 3, count 0 2006.285.22:47:42.01#ibcon#end of sib2, iclass 3, count 0 2006.285.22:47:42.01#ibcon#*after write, iclass 3, count 0 2006.285.22:47:42.01#ibcon#*before return 0, iclass 3, count 0 2006.285.22:47:42.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:47:42.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.22:47:42.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:47:42.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:47:42.01$vck44/vabw=wide 2006.285.22:47:42.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.22:47:42.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.22:47:42.01#ibcon#ireg 8 cls_cnt 0 2006.285.22:47:42.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:47:42.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:47:42.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:47:42.01#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:47:42.01#ibcon#first serial, iclass 5, count 0 2006.285.22:47:42.01#ibcon#enter sib2, iclass 5, count 0 2006.285.22:47:42.01#ibcon#flushed, iclass 5, count 0 2006.285.22:47:42.01#ibcon#about to write, iclass 5, count 0 2006.285.22:47:42.01#ibcon#wrote, iclass 5, count 0 2006.285.22:47:42.01#ibcon#about to read 3, iclass 5, count 0 2006.285.22:47:42.03#ibcon#read 3, iclass 5, count 0 2006.285.22:47:42.03#ibcon#about to read 4, iclass 5, count 0 2006.285.22:47:42.03#ibcon#read 4, iclass 5, count 0 2006.285.22:47:42.03#ibcon#about to read 5, iclass 5, count 0 2006.285.22:47:42.03#ibcon#read 5, iclass 5, count 0 2006.285.22:47:42.03#ibcon#about to read 6, iclass 5, count 0 2006.285.22:47:42.03#ibcon#read 6, iclass 5, count 0 2006.285.22:47:42.03#ibcon#end of sib2, iclass 5, count 0 2006.285.22:47:42.03#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:47:42.03#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:47:42.03#ibcon#[25=BW32\r\n] 2006.285.22:47:42.03#ibcon#*before write, iclass 5, count 0 2006.285.22:47:42.03#ibcon#enter sib2, iclass 5, count 0 2006.285.22:47:42.03#ibcon#flushed, iclass 5, count 0 2006.285.22:47:42.03#ibcon#about to write, iclass 5, count 0 2006.285.22:47:42.03#ibcon#wrote, iclass 5, count 0 2006.285.22:47:42.03#ibcon#about to read 3, iclass 5, count 0 2006.285.22:47:42.06#ibcon#read 3, iclass 5, count 0 2006.285.22:47:42.06#ibcon#about to read 4, iclass 5, count 0 2006.285.22:47:42.06#ibcon#read 4, iclass 5, count 0 2006.285.22:47:42.06#ibcon#about to read 5, iclass 5, count 0 2006.285.22:47:42.06#ibcon#read 5, iclass 5, count 0 2006.285.22:47:42.06#ibcon#about to read 6, iclass 5, count 0 2006.285.22:47:42.06#ibcon#read 6, iclass 5, count 0 2006.285.22:47:42.06#ibcon#end of sib2, iclass 5, count 0 2006.285.22:47:42.06#ibcon#*after write, iclass 5, count 0 2006.285.22:47:42.06#ibcon#*before return 0, iclass 5, count 0 2006.285.22:47:42.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:47:42.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.22:47:42.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:47:42.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:47:42.06$vck44/vbbw=wide 2006.285.22:47:42.06#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.22:47:42.06#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.22:47:42.06#ibcon#ireg 8 cls_cnt 0 2006.285.22:47:42.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:47:42.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:47:42.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:47:42.13#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:47:42.13#ibcon#first serial, iclass 7, count 0 2006.285.22:47:42.13#ibcon#enter sib2, iclass 7, count 0 2006.285.22:47:42.13#ibcon#flushed, iclass 7, count 0 2006.285.22:47:42.13#ibcon#about to write, iclass 7, count 0 2006.285.22:47:42.13#ibcon#wrote, iclass 7, count 0 2006.285.22:47:42.13#ibcon#about to read 3, iclass 7, count 0 2006.285.22:47:42.15#ibcon#read 3, iclass 7, count 0 2006.285.22:47:42.15#ibcon#about to read 4, iclass 7, count 0 2006.285.22:47:42.15#ibcon#read 4, iclass 7, count 0 2006.285.22:47:42.15#ibcon#about to read 5, iclass 7, count 0 2006.285.22:47:42.15#ibcon#read 5, iclass 7, count 0 2006.285.22:47:42.15#ibcon#about to read 6, iclass 7, count 0 2006.285.22:47:42.15#ibcon#read 6, iclass 7, count 0 2006.285.22:47:42.15#ibcon#end of sib2, iclass 7, count 0 2006.285.22:47:42.15#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:47:42.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:47:42.15#ibcon#[27=BW32\r\n] 2006.285.22:47:42.15#ibcon#*before write, iclass 7, count 0 2006.285.22:47:42.15#ibcon#enter sib2, iclass 7, count 0 2006.285.22:47:42.15#ibcon#flushed, iclass 7, count 0 2006.285.22:47:42.15#ibcon#about to write, iclass 7, count 0 2006.285.22:47:42.15#ibcon#wrote, iclass 7, count 0 2006.285.22:47:42.15#ibcon#about to read 3, iclass 7, count 0 2006.285.22:47:42.18#ibcon#read 3, iclass 7, count 0 2006.285.22:47:42.18#ibcon#about to read 4, iclass 7, count 0 2006.285.22:47:42.18#ibcon#read 4, iclass 7, count 0 2006.285.22:47:42.18#ibcon#about to read 5, iclass 7, count 0 2006.285.22:47:42.18#ibcon#read 5, iclass 7, count 0 2006.285.22:47:42.18#ibcon#about to read 6, iclass 7, count 0 2006.285.22:47:42.18#ibcon#read 6, iclass 7, count 0 2006.285.22:47:42.18#ibcon#end of sib2, iclass 7, count 0 2006.285.22:47:42.18#ibcon#*after write, iclass 7, count 0 2006.285.22:47:42.18#ibcon#*before return 0, iclass 7, count 0 2006.285.22:47:42.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:47:42.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:47:42.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:47:42.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:47:42.18$setupk4/ifdk4 2006.285.22:47:42.18$ifdk4/lo= 2006.285.22:47:42.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.22:47:42.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.22:47:42.18$ifdk4/patch= 2006.285.22:47:42.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.22:47:42.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.22:47:42.18$setupk4/!*+20s 2006.285.22:47:42.60#abcon#<5=/04 1.5 2.9 17.67 921016.1\r\n> 2006.285.22:47:42.62#abcon#{5=INTERFACE CLEAR} 2006.285.22:47:42.68#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:47:52.77#abcon#<5=/04 1.5 2.9 17.68 921016.1\r\n> 2006.285.22:47:52.79#abcon#{5=INTERFACE CLEAR} 2006.285.22:47:52.85#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:47:56.69$setupk4/"tpicd 2006.285.22:47:56.69$setupk4/echo=off 2006.285.22:47:56.69$setupk4/xlog=off 2006.285.22:47:56.69:!2006.285.22:49:38 2006.285.22:48:11.14#trakl#Source acquired 2006.285.22:48:11.14#flagr#flagr/antenna,acquired 2006.285.22:49:38.00:preob 2006.285.22:49:39.14/onsource/TRACKING 2006.285.22:49:39.14:!2006.285.22:49:48 2006.285.22:49:48.00:"tape 2006.285.22:49:48.00:"st=record 2006.285.22:49:48.00:data_valid=on 2006.285.22:49:48.00:midob 2006.285.22:49:48.14/onsource/TRACKING 2006.285.22:49:48.14/wx/17.81,1016.2,91 2006.285.22:49:48.32/cable/+6.5128E-03 2006.285.22:49:49.41/va/01,07,usb,yes,31,34 2006.285.22:49:49.41/va/02,06,usb,yes,31,32 2006.285.22:49:49.41/va/03,07,usb,yes,31,33 2006.285.22:49:49.41/va/04,06,usb,yes,32,34 2006.285.22:49:49.41/va/05,03,usb,yes,32,32 2006.285.22:49:49.41/va/06,04,usb,yes,29,28 2006.285.22:49:49.41/va/07,04,usb,yes,29,30 2006.285.22:49:49.41/va/08,03,usb,yes,30,37 2006.285.22:49:49.64/valo/01,524.99,yes,locked 2006.285.22:49:49.64/valo/02,534.99,yes,locked 2006.285.22:49:49.64/valo/03,564.99,yes,locked 2006.285.22:49:49.64/valo/04,624.99,yes,locked 2006.285.22:49:49.64/valo/05,734.99,yes,locked 2006.285.22:49:49.64/valo/06,814.99,yes,locked 2006.285.22:49:49.64/valo/07,864.99,yes,locked 2006.285.22:49:49.64/valo/08,884.99,yes,locked 2006.285.22:49:50.73/vb/01,04,usb,yes,30,28 2006.285.22:49:50.73/vb/02,05,usb,yes,28,28 2006.285.22:49:50.73/vb/03,04,usb,yes,29,32 2006.285.22:49:50.73/vb/04,05,usb,yes,29,28 2006.285.22:49:50.73/vb/05,04,usb,yes,26,28 2006.285.22:49:50.73/vb/06,03,usb,yes,37,33 2006.285.22:49:50.73/vb/07,04,usb,yes,30,30 2006.285.22:49:50.73/vb/08,04,usb,yes,27,31 2006.285.22:49:50.96/vblo/01,629.99,yes,locked 2006.285.22:49:50.96/vblo/02,634.99,yes,locked 2006.285.22:49:50.96/vblo/03,649.99,yes,locked 2006.285.22:49:50.96/vblo/04,679.99,yes,locked 2006.285.22:49:50.96/vblo/05,709.99,yes,locked 2006.285.22:49:50.96/vblo/06,719.99,yes,locked 2006.285.22:49:50.96/vblo/07,734.99,yes,locked 2006.285.22:49:50.96/vblo/08,744.99,yes,locked 2006.285.22:49:51.11/vabw/8 2006.285.22:49:51.26/vbbw/8 2006.285.22:49:51.35/xfe/off,on,12.0 2006.285.22:49:51.74/ifatt/23,28,28,28 2006.285.22:49:52.07/fmout-gps/S +2.64E-07 2006.285.22:49:52.09:!2006.285.22:54:38 2006.285.22:54:38.01:data_valid=off 2006.285.22:54:38.01:"et 2006.285.22:54:38.01:!+3s 2006.285.22:54:41.02:"tape 2006.285.22:54:41.02:postob 2006.285.22:54:41.18/cable/+6.5114E-03 2006.285.22:54:41.18/wx/18.13,1016.2,89 2006.285.22:54:41.24/fmout-gps/S +2.61E-07 2006.285.22:54:41.24:scan_name=285-2258,jd0610,60 2006.285.22:54:41.24:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.285.22:54:42.14#flagr#flagr/antenna,new-source 2006.285.22:54:42.14:checkk5 2006.285.22:54:42.49/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:54:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:54:43.32/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:54:43.71/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:54:44.12/chk_obsdata//k5ts1/T2852249??a.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.22:54:44.55/chk_obsdata//k5ts2/T2852249??b.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.22:54:44.93/chk_obsdata//k5ts3/T2852249??c.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.22:54:45.55/chk_obsdata//k5ts4/T2852249??d.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.285.22:54:46.22/k5log//k5ts1_log_newline 2006.285.22:54:47.03/k5log//k5ts2_log_newline 2006.285.22:54:47.73/k5log//k5ts3_log_newline 2006.285.22:54:48.75/k5log//k5ts4_log_newline 2006.285.22:54:48.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:54:48.77:setupk4=1 2006.285.22:54:48.77$setupk4/echo=on 2006.285.22:54:48.77$setupk4/pcalon 2006.285.22:54:48.77$pcalon/"no phase cal control is implemented here 2006.285.22:54:48.77$setupk4/"tpicd=stop 2006.285.22:54:48.77$setupk4/"rec=synch_on 2006.285.22:54:48.77$setupk4/"rec_mode=128 2006.285.22:54:48.77$setupk4/!* 2006.285.22:54:48.77$setupk4/recpk4 2006.285.22:54:48.77$recpk4/recpatch= 2006.285.22:54:48.77$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:54:48.77$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:54:48.77$setupk4/vck44 2006.285.22:54:48.77$vck44/valo=1,524.99 2006.285.22:54:48.78#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.22:54:48.78#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.22:54:48.78#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:48.78#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:54:48.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:54:48.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:54:48.78#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:54:48.78#ibcon#first serial, iclass 33, count 0 2006.285.22:54:48.78#ibcon#enter sib2, iclass 33, count 0 2006.285.22:54:48.78#ibcon#flushed, iclass 33, count 0 2006.285.22:54:48.78#ibcon#about to write, iclass 33, count 0 2006.285.22:54:48.78#ibcon#wrote, iclass 33, count 0 2006.285.22:54:48.78#ibcon#about to read 3, iclass 33, count 0 2006.285.22:54:48.79#ibcon#read 3, iclass 33, count 0 2006.285.22:54:48.79#ibcon#about to read 4, iclass 33, count 0 2006.285.22:54:48.79#ibcon#read 4, iclass 33, count 0 2006.285.22:54:48.79#ibcon#about to read 5, iclass 33, count 0 2006.285.22:54:48.79#ibcon#read 5, iclass 33, count 0 2006.285.22:54:48.79#ibcon#about to read 6, iclass 33, count 0 2006.285.22:54:48.79#ibcon#read 6, iclass 33, count 0 2006.285.22:54:48.79#ibcon#end of sib2, iclass 33, count 0 2006.285.22:54:48.79#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:54:48.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:54:48.79#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:54:48.79#ibcon#*before write, iclass 33, count 0 2006.285.22:54:48.79#ibcon#enter sib2, iclass 33, count 0 2006.285.22:54:48.79#ibcon#flushed, iclass 33, count 0 2006.285.22:54:48.79#ibcon#about to write, iclass 33, count 0 2006.285.22:54:48.79#ibcon#wrote, iclass 33, count 0 2006.285.22:54:48.79#ibcon#about to read 3, iclass 33, count 0 2006.285.22:54:48.84#ibcon#read 3, iclass 33, count 0 2006.285.22:54:48.84#ibcon#about to read 4, iclass 33, count 0 2006.285.22:54:48.84#ibcon#read 4, iclass 33, count 0 2006.285.22:54:48.84#ibcon#about to read 5, iclass 33, count 0 2006.285.22:54:48.84#ibcon#read 5, iclass 33, count 0 2006.285.22:54:48.84#ibcon#about to read 6, iclass 33, count 0 2006.285.22:54:48.84#ibcon#read 6, iclass 33, count 0 2006.285.22:54:48.84#ibcon#end of sib2, iclass 33, count 0 2006.285.22:54:48.84#ibcon#*after write, iclass 33, count 0 2006.285.22:54:48.84#ibcon#*before return 0, iclass 33, count 0 2006.285.22:54:48.84#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:54:48.84#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:54:48.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:54:48.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:54:48.84$vck44/va=1,7 2006.285.22:54:48.84#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.22:54:48.84#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.22:54:48.84#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:48.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:54:48.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:54:48.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:54:48.84#ibcon#enter wrdev, iclass 35, count 2 2006.285.22:54:48.84#ibcon#first serial, iclass 35, count 2 2006.285.22:54:48.84#ibcon#enter sib2, iclass 35, count 2 2006.285.22:54:48.84#ibcon#flushed, iclass 35, count 2 2006.285.22:54:48.84#ibcon#about to write, iclass 35, count 2 2006.285.22:54:48.84#ibcon#wrote, iclass 35, count 2 2006.285.22:54:48.84#ibcon#about to read 3, iclass 35, count 2 2006.285.22:54:48.86#ibcon#read 3, iclass 35, count 2 2006.285.22:54:48.86#ibcon#about to read 4, iclass 35, count 2 2006.285.22:54:48.86#ibcon#read 4, iclass 35, count 2 2006.285.22:54:48.86#ibcon#about to read 5, iclass 35, count 2 2006.285.22:54:48.86#ibcon#read 5, iclass 35, count 2 2006.285.22:54:48.86#ibcon#about to read 6, iclass 35, count 2 2006.285.22:54:48.86#ibcon#read 6, iclass 35, count 2 2006.285.22:54:48.86#ibcon#end of sib2, iclass 35, count 2 2006.285.22:54:48.86#ibcon#*mode == 0, iclass 35, count 2 2006.285.22:54:48.86#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.22:54:48.86#ibcon#[25=AT01-07\r\n] 2006.285.22:54:48.86#ibcon#*before write, iclass 35, count 2 2006.285.22:54:48.86#ibcon#enter sib2, iclass 35, count 2 2006.285.22:54:48.86#ibcon#flushed, iclass 35, count 2 2006.285.22:54:48.86#ibcon#about to write, iclass 35, count 2 2006.285.22:54:48.86#ibcon#wrote, iclass 35, count 2 2006.285.22:54:48.86#ibcon#about to read 3, iclass 35, count 2 2006.285.22:54:48.89#ibcon#read 3, iclass 35, count 2 2006.285.22:54:48.89#ibcon#about to read 4, iclass 35, count 2 2006.285.22:54:48.89#ibcon#read 4, iclass 35, count 2 2006.285.22:54:48.89#ibcon#about to read 5, iclass 35, count 2 2006.285.22:54:48.89#ibcon#read 5, iclass 35, count 2 2006.285.22:54:48.89#ibcon#about to read 6, iclass 35, count 2 2006.285.22:54:48.89#ibcon#read 6, iclass 35, count 2 2006.285.22:54:48.89#ibcon#end of sib2, iclass 35, count 2 2006.285.22:54:48.89#ibcon#*after write, iclass 35, count 2 2006.285.22:54:48.89#ibcon#*before return 0, iclass 35, count 2 2006.285.22:54:48.89#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:54:48.89#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:54:48.89#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.22:54:48.89#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:48.89#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:54:49.01#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:54:49.01#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:54:49.01#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:54:49.01#ibcon#first serial, iclass 35, count 0 2006.285.22:54:49.01#ibcon#enter sib2, iclass 35, count 0 2006.285.22:54:49.01#ibcon#flushed, iclass 35, count 0 2006.285.22:54:49.01#ibcon#about to write, iclass 35, count 0 2006.285.22:54:49.01#ibcon#wrote, iclass 35, count 0 2006.285.22:54:49.01#ibcon#about to read 3, iclass 35, count 0 2006.285.22:54:49.03#ibcon#read 3, iclass 35, count 0 2006.285.22:54:49.03#ibcon#about to read 4, iclass 35, count 0 2006.285.22:54:49.03#ibcon#read 4, iclass 35, count 0 2006.285.22:54:49.03#ibcon#about to read 5, iclass 35, count 0 2006.285.22:54:49.03#ibcon#read 5, iclass 35, count 0 2006.285.22:54:49.03#ibcon#about to read 6, iclass 35, count 0 2006.285.22:54:49.03#ibcon#read 6, iclass 35, count 0 2006.285.22:54:49.03#ibcon#end of sib2, iclass 35, count 0 2006.285.22:54:49.03#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:54:49.03#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:54:49.03#ibcon#[25=USB\r\n] 2006.285.22:54:49.03#ibcon#*before write, iclass 35, count 0 2006.285.22:54:49.03#ibcon#enter sib2, iclass 35, count 0 2006.285.22:54:49.03#ibcon#flushed, iclass 35, count 0 2006.285.22:54:49.03#ibcon#about to write, iclass 35, count 0 2006.285.22:54:49.03#ibcon#wrote, iclass 35, count 0 2006.285.22:54:49.03#ibcon#about to read 3, iclass 35, count 0 2006.285.22:54:49.06#ibcon#read 3, iclass 35, count 0 2006.285.22:54:49.06#ibcon#about to read 4, iclass 35, count 0 2006.285.22:54:49.06#ibcon#read 4, iclass 35, count 0 2006.285.22:54:49.06#ibcon#about to read 5, iclass 35, count 0 2006.285.22:54:49.06#ibcon#read 5, iclass 35, count 0 2006.285.22:54:49.06#ibcon#about to read 6, iclass 35, count 0 2006.285.22:54:49.06#ibcon#read 6, iclass 35, count 0 2006.285.22:54:49.06#ibcon#end of sib2, iclass 35, count 0 2006.285.22:54:49.06#ibcon#*after write, iclass 35, count 0 2006.285.22:54:49.06#ibcon#*before return 0, iclass 35, count 0 2006.285.22:54:49.06#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:54:49.06#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:54:49.06#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:54:49.06#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:54:49.06$vck44/valo=2,534.99 2006.285.22:54:49.06#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.22:54:49.06#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.22:54:49.06#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:49.06#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:54:49.06#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:54:49.06#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:54:49.06#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:54:49.06#ibcon#first serial, iclass 37, count 0 2006.285.22:54:49.06#ibcon#enter sib2, iclass 37, count 0 2006.285.22:54:49.06#ibcon#flushed, iclass 37, count 0 2006.285.22:54:49.06#ibcon#about to write, iclass 37, count 0 2006.285.22:54:49.06#ibcon#wrote, iclass 37, count 0 2006.285.22:54:49.06#ibcon#about to read 3, iclass 37, count 0 2006.285.22:54:49.08#ibcon#read 3, iclass 37, count 0 2006.285.22:54:49.08#ibcon#about to read 4, iclass 37, count 0 2006.285.22:54:49.08#ibcon#read 4, iclass 37, count 0 2006.285.22:54:49.08#ibcon#about to read 5, iclass 37, count 0 2006.285.22:54:49.08#ibcon#read 5, iclass 37, count 0 2006.285.22:54:49.08#ibcon#about to read 6, iclass 37, count 0 2006.285.22:54:49.08#ibcon#read 6, iclass 37, count 0 2006.285.22:54:49.08#ibcon#end of sib2, iclass 37, count 0 2006.285.22:54:49.08#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:54:49.08#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:54:49.08#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:54:49.08#ibcon#*before write, iclass 37, count 0 2006.285.22:54:49.08#ibcon#enter sib2, iclass 37, count 0 2006.285.22:54:49.08#ibcon#flushed, iclass 37, count 0 2006.285.22:54:49.08#ibcon#about to write, iclass 37, count 0 2006.285.22:54:49.08#ibcon#wrote, iclass 37, count 0 2006.285.22:54:49.08#ibcon#about to read 3, iclass 37, count 0 2006.285.22:54:49.12#ibcon#read 3, iclass 37, count 0 2006.285.22:54:49.12#ibcon#about to read 4, iclass 37, count 0 2006.285.22:54:49.12#ibcon#read 4, iclass 37, count 0 2006.285.22:54:49.12#ibcon#about to read 5, iclass 37, count 0 2006.285.22:54:49.12#ibcon#read 5, iclass 37, count 0 2006.285.22:54:49.12#ibcon#about to read 6, iclass 37, count 0 2006.285.22:54:49.12#ibcon#read 6, iclass 37, count 0 2006.285.22:54:49.12#ibcon#end of sib2, iclass 37, count 0 2006.285.22:54:49.12#ibcon#*after write, iclass 37, count 0 2006.285.22:54:49.12#ibcon#*before return 0, iclass 37, count 0 2006.285.22:54:49.12#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:54:49.12#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:54:49.12#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:54:49.12#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:54:49.12$vck44/va=2,6 2006.285.22:54:49.12#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.22:54:49.12#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.22:54:49.12#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:49.12#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:54:49.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:54:49.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:54:49.18#ibcon#enter wrdev, iclass 39, count 2 2006.285.22:54:49.18#ibcon#first serial, iclass 39, count 2 2006.285.22:54:49.18#ibcon#enter sib2, iclass 39, count 2 2006.285.22:54:49.18#ibcon#flushed, iclass 39, count 2 2006.285.22:54:49.18#ibcon#about to write, iclass 39, count 2 2006.285.22:54:49.18#ibcon#wrote, iclass 39, count 2 2006.285.22:54:49.18#ibcon#about to read 3, iclass 39, count 2 2006.285.22:54:49.20#ibcon#read 3, iclass 39, count 2 2006.285.22:54:49.20#ibcon#about to read 4, iclass 39, count 2 2006.285.22:54:49.20#ibcon#read 4, iclass 39, count 2 2006.285.22:54:49.20#ibcon#about to read 5, iclass 39, count 2 2006.285.22:54:49.20#ibcon#read 5, iclass 39, count 2 2006.285.22:54:49.20#ibcon#about to read 6, iclass 39, count 2 2006.285.22:54:49.20#ibcon#read 6, iclass 39, count 2 2006.285.22:54:49.20#ibcon#end of sib2, iclass 39, count 2 2006.285.22:54:49.20#ibcon#*mode == 0, iclass 39, count 2 2006.285.22:54:49.20#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.22:54:49.20#ibcon#[25=AT02-06\r\n] 2006.285.22:54:49.20#ibcon#*before write, iclass 39, count 2 2006.285.22:54:49.20#ibcon#enter sib2, iclass 39, count 2 2006.285.22:54:49.20#ibcon#flushed, iclass 39, count 2 2006.285.22:54:49.20#ibcon#about to write, iclass 39, count 2 2006.285.22:54:49.20#ibcon#wrote, iclass 39, count 2 2006.285.22:54:49.20#ibcon#about to read 3, iclass 39, count 2 2006.285.22:54:49.23#ibcon#read 3, iclass 39, count 2 2006.285.22:54:49.23#ibcon#about to read 4, iclass 39, count 2 2006.285.22:54:49.23#ibcon#read 4, iclass 39, count 2 2006.285.22:54:49.23#ibcon#about to read 5, iclass 39, count 2 2006.285.22:54:49.23#ibcon#read 5, iclass 39, count 2 2006.285.22:54:49.23#ibcon#about to read 6, iclass 39, count 2 2006.285.22:54:49.23#ibcon#read 6, iclass 39, count 2 2006.285.22:54:49.23#ibcon#end of sib2, iclass 39, count 2 2006.285.22:54:49.23#ibcon#*after write, iclass 39, count 2 2006.285.22:54:49.23#ibcon#*before return 0, iclass 39, count 2 2006.285.22:54:49.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:54:49.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:54:49.23#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.22:54:49.23#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:49.23#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:54:49.35#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:54:49.35#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:54:49.35#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:54:49.35#ibcon#first serial, iclass 39, count 0 2006.285.22:54:49.35#ibcon#enter sib2, iclass 39, count 0 2006.285.22:54:49.35#ibcon#flushed, iclass 39, count 0 2006.285.22:54:49.35#ibcon#about to write, iclass 39, count 0 2006.285.22:54:49.35#ibcon#wrote, iclass 39, count 0 2006.285.22:54:49.35#ibcon#about to read 3, iclass 39, count 0 2006.285.22:54:49.37#ibcon#read 3, iclass 39, count 0 2006.285.22:54:49.37#ibcon#about to read 4, iclass 39, count 0 2006.285.22:54:49.37#ibcon#read 4, iclass 39, count 0 2006.285.22:54:49.37#ibcon#about to read 5, iclass 39, count 0 2006.285.22:54:49.37#ibcon#read 5, iclass 39, count 0 2006.285.22:54:49.37#ibcon#about to read 6, iclass 39, count 0 2006.285.22:54:49.37#ibcon#read 6, iclass 39, count 0 2006.285.22:54:49.37#ibcon#end of sib2, iclass 39, count 0 2006.285.22:54:49.37#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:54:49.37#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:54:49.37#ibcon#[25=USB\r\n] 2006.285.22:54:49.37#ibcon#*before write, iclass 39, count 0 2006.285.22:54:49.37#ibcon#enter sib2, iclass 39, count 0 2006.285.22:54:49.37#ibcon#flushed, iclass 39, count 0 2006.285.22:54:49.37#ibcon#about to write, iclass 39, count 0 2006.285.22:54:49.37#ibcon#wrote, iclass 39, count 0 2006.285.22:54:49.37#ibcon#about to read 3, iclass 39, count 0 2006.285.22:54:49.40#ibcon#read 3, iclass 39, count 0 2006.285.22:54:49.40#ibcon#about to read 4, iclass 39, count 0 2006.285.22:54:49.40#ibcon#read 4, iclass 39, count 0 2006.285.22:54:49.40#ibcon#about to read 5, iclass 39, count 0 2006.285.22:54:49.40#ibcon#read 5, iclass 39, count 0 2006.285.22:54:49.40#ibcon#about to read 6, iclass 39, count 0 2006.285.22:54:49.40#ibcon#read 6, iclass 39, count 0 2006.285.22:54:49.40#ibcon#end of sib2, iclass 39, count 0 2006.285.22:54:49.40#ibcon#*after write, iclass 39, count 0 2006.285.22:54:49.40#ibcon#*before return 0, iclass 39, count 0 2006.285.22:54:49.40#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:54:49.40#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:54:49.40#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:54:49.40#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:54:49.40$vck44/valo=3,564.99 2006.285.22:54:49.40#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.22:54:49.40#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.22:54:49.40#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:49.40#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:54:49.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:54:49.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:54:49.40#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:54:49.40#ibcon#first serial, iclass 3, count 0 2006.285.22:54:49.40#ibcon#enter sib2, iclass 3, count 0 2006.285.22:54:49.40#ibcon#flushed, iclass 3, count 0 2006.285.22:54:49.40#ibcon#about to write, iclass 3, count 0 2006.285.22:54:49.40#ibcon#wrote, iclass 3, count 0 2006.285.22:54:49.40#ibcon#about to read 3, iclass 3, count 0 2006.285.22:54:49.42#ibcon#read 3, iclass 3, count 0 2006.285.22:54:49.42#ibcon#about to read 4, iclass 3, count 0 2006.285.22:54:49.42#ibcon#read 4, iclass 3, count 0 2006.285.22:54:49.42#ibcon#about to read 5, iclass 3, count 0 2006.285.22:54:49.42#ibcon#read 5, iclass 3, count 0 2006.285.22:54:49.42#ibcon#about to read 6, iclass 3, count 0 2006.285.22:54:49.42#ibcon#read 6, iclass 3, count 0 2006.285.22:54:49.42#ibcon#end of sib2, iclass 3, count 0 2006.285.22:54:49.42#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:54:49.42#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:54:49.42#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:54:49.42#ibcon#*before write, iclass 3, count 0 2006.285.22:54:49.42#ibcon#enter sib2, iclass 3, count 0 2006.285.22:54:49.42#ibcon#flushed, iclass 3, count 0 2006.285.22:54:49.42#ibcon#about to write, iclass 3, count 0 2006.285.22:54:49.42#ibcon#wrote, iclass 3, count 0 2006.285.22:54:49.42#ibcon#about to read 3, iclass 3, count 0 2006.285.22:54:49.46#ibcon#read 3, iclass 3, count 0 2006.285.22:54:49.46#ibcon#about to read 4, iclass 3, count 0 2006.285.22:54:49.46#ibcon#read 4, iclass 3, count 0 2006.285.22:54:49.46#ibcon#about to read 5, iclass 3, count 0 2006.285.22:54:49.46#ibcon#read 5, iclass 3, count 0 2006.285.22:54:49.46#ibcon#about to read 6, iclass 3, count 0 2006.285.22:54:49.46#ibcon#read 6, iclass 3, count 0 2006.285.22:54:49.46#ibcon#end of sib2, iclass 3, count 0 2006.285.22:54:49.46#ibcon#*after write, iclass 3, count 0 2006.285.22:54:49.46#ibcon#*before return 0, iclass 3, count 0 2006.285.22:54:49.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:54:49.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:54:49.46#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:54:49.46#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:54:49.46$vck44/va=3,7 2006.285.22:54:49.46#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.22:54:49.46#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.22:54:49.46#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:49.46#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:54:49.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:54:49.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:54:49.52#ibcon#enter wrdev, iclass 5, count 2 2006.285.22:54:49.52#ibcon#first serial, iclass 5, count 2 2006.285.22:54:49.52#ibcon#enter sib2, iclass 5, count 2 2006.285.22:54:49.52#ibcon#flushed, iclass 5, count 2 2006.285.22:54:49.52#ibcon#about to write, iclass 5, count 2 2006.285.22:54:49.52#ibcon#wrote, iclass 5, count 2 2006.285.22:54:49.52#ibcon#about to read 3, iclass 5, count 2 2006.285.22:54:49.54#ibcon#read 3, iclass 5, count 2 2006.285.22:54:49.54#ibcon#about to read 4, iclass 5, count 2 2006.285.22:54:49.54#ibcon#read 4, iclass 5, count 2 2006.285.22:54:49.54#ibcon#about to read 5, iclass 5, count 2 2006.285.22:54:49.54#ibcon#read 5, iclass 5, count 2 2006.285.22:54:49.54#ibcon#about to read 6, iclass 5, count 2 2006.285.22:54:49.54#ibcon#read 6, iclass 5, count 2 2006.285.22:54:49.54#ibcon#end of sib2, iclass 5, count 2 2006.285.22:54:49.54#ibcon#*mode == 0, iclass 5, count 2 2006.285.22:54:49.54#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.22:54:49.54#ibcon#[25=AT03-07\r\n] 2006.285.22:54:49.54#ibcon#*before write, iclass 5, count 2 2006.285.22:54:49.54#ibcon#enter sib2, iclass 5, count 2 2006.285.22:54:49.54#ibcon#flushed, iclass 5, count 2 2006.285.22:54:49.54#ibcon#about to write, iclass 5, count 2 2006.285.22:54:49.54#ibcon#wrote, iclass 5, count 2 2006.285.22:54:49.54#ibcon#about to read 3, iclass 5, count 2 2006.285.22:54:49.57#ibcon#read 3, iclass 5, count 2 2006.285.22:54:49.57#ibcon#about to read 4, iclass 5, count 2 2006.285.22:54:49.57#ibcon#read 4, iclass 5, count 2 2006.285.22:54:49.57#ibcon#about to read 5, iclass 5, count 2 2006.285.22:54:49.57#ibcon#read 5, iclass 5, count 2 2006.285.22:54:49.57#ibcon#about to read 6, iclass 5, count 2 2006.285.22:54:49.57#ibcon#read 6, iclass 5, count 2 2006.285.22:54:49.57#ibcon#end of sib2, iclass 5, count 2 2006.285.22:54:49.57#ibcon#*after write, iclass 5, count 2 2006.285.22:54:49.57#ibcon#*before return 0, iclass 5, count 2 2006.285.22:54:49.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:54:49.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:54:49.57#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.22:54:49.57#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:49.57#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:54:49.69#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:54:49.69#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:54:49.69#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:54:49.69#ibcon#first serial, iclass 5, count 0 2006.285.22:54:49.69#ibcon#enter sib2, iclass 5, count 0 2006.285.22:54:49.69#ibcon#flushed, iclass 5, count 0 2006.285.22:54:49.69#ibcon#about to write, iclass 5, count 0 2006.285.22:54:49.69#ibcon#wrote, iclass 5, count 0 2006.285.22:54:49.69#ibcon#about to read 3, iclass 5, count 0 2006.285.22:54:49.71#ibcon#read 3, iclass 5, count 0 2006.285.22:54:49.71#ibcon#about to read 4, iclass 5, count 0 2006.285.22:54:49.71#ibcon#read 4, iclass 5, count 0 2006.285.22:54:49.71#ibcon#about to read 5, iclass 5, count 0 2006.285.22:54:49.71#ibcon#read 5, iclass 5, count 0 2006.285.22:54:49.71#ibcon#about to read 6, iclass 5, count 0 2006.285.22:54:49.71#ibcon#read 6, iclass 5, count 0 2006.285.22:54:49.71#ibcon#end of sib2, iclass 5, count 0 2006.285.22:54:49.71#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:54:49.71#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:54:49.71#ibcon#[25=USB\r\n] 2006.285.22:54:49.71#ibcon#*before write, iclass 5, count 0 2006.285.22:54:49.71#ibcon#enter sib2, iclass 5, count 0 2006.285.22:54:49.71#ibcon#flushed, iclass 5, count 0 2006.285.22:54:49.71#ibcon#about to write, iclass 5, count 0 2006.285.22:54:49.71#ibcon#wrote, iclass 5, count 0 2006.285.22:54:49.71#ibcon#about to read 3, iclass 5, count 0 2006.285.22:54:49.74#ibcon#read 3, iclass 5, count 0 2006.285.22:54:49.74#ibcon#about to read 4, iclass 5, count 0 2006.285.22:54:49.74#ibcon#read 4, iclass 5, count 0 2006.285.22:54:49.74#ibcon#about to read 5, iclass 5, count 0 2006.285.22:54:49.74#ibcon#read 5, iclass 5, count 0 2006.285.22:54:49.74#ibcon#about to read 6, iclass 5, count 0 2006.285.22:54:49.74#ibcon#read 6, iclass 5, count 0 2006.285.22:54:49.74#ibcon#end of sib2, iclass 5, count 0 2006.285.22:54:49.74#ibcon#*after write, iclass 5, count 0 2006.285.22:54:49.74#ibcon#*before return 0, iclass 5, count 0 2006.285.22:54:49.74#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:54:49.74#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:54:49.74#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:54:49.74#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:54:49.74$vck44/valo=4,624.99 2006.285.22:54:49.74#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.22:54:49.74#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.22:54:49.74#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:49.74#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:54:49.74#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:54:49.74#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:54:49.74#ibcon#enter wrdev, iclass 7, count 0 2006.285.22:54:49.74#ibcon#first serial, iclass 7, count 0 2006.285.22:54:49.74#ibcon#enter sib2, iclass 7, count 0 2006.285.22:54:49.74#ibcon#flushed, iclass 7, count 0 2006.285.22:54:49.74#ibcon#about to write, iclass 7, count 0 2006.285.22:54:49.74#ibcon#wrote, iclass 7, count 0 2006.285.22:54:49.74#ibcon#about to read 3, iclass 7, count 0 2006.285.22:54:49.76#ibcon#read 3, iclass 7, count 0 2006.285.22:54:49.76#ibcon#about to read 4, iclass 7, count 0 2006.285.22:54:49.76#ibcon#read 4, iclass 7, count 0 2006.285.22:54:49.76#ibcon#about to read 5, iclass 7, count 0 2006.285.22:54:49.76#ibcon#read 5, iclass 7, count 0 2006.285.22:54:49.76#ibcon#about to read 6, iclass 7, count 0 2006.285.22:54:49.76#ibcon#read 6, iclass 7, count 0 2006.285.22:54:49.76#ibcon#end of sib2, iclass 7, count 0 2006.285.22:54:49.76#ibcon#*mode == 0, iclass 7, count 0 2006.285.22:54:49.76#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.22:54:49.76#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:54:49.76#ibcon#*before write, iclass 7, count 0 2006.285.22:54:49.76#ibcon#enter sib2, iclass 7, count 0 2006.285.22:54:49.76#ibcon#flushed, iclass 7, count 0 2006.285.22:54:49.76#ibcon#about to write, iclass 7, count 0 2006.285.22:54:49.76#ibcon#wrote, iclass 7, count 0 2006.285.22:54:49.76#ibcon#about to read 3, iclass 7, count 0 2006.285.22:54:49.80#ibcon#read 3, iclass 7, count 0 2006.285.22:54:49.80#ibcon#about to read 4, iclass 7, count 0 2006.285.22:54:49.80#ibcon#read 4, iclass 7, count 0 2006.285.22:54:49.80#ibcon#about to read 5, iclass 7, count 0 2006.285.22:54:49.80#ibcon#read 5, iclass 7, count 0 2006.285.22:54:49.80#ibcon#about to read 6, iclass 7, count 0 2006.285.22:54:49.80#ibcon#read 6, iclass 7, count 0 2006.285.22:54:49.80#ibcon#end of sib2, iclass 7, count 0 2006.285.22:54:49.80#ibcon#*after write, iclass 7, count 0 2006.285.22:54:49.80#ibcon#*before return 0, iclass 7, count 0 2006.285.22:54:49.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:54:49.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.22:54:49.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.22:54:49.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.22:54:49.80$vck44/va=4,6 2006.285.22:54:49.80#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.22:54:49.80#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.22:54:49.80#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:49.80#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:54:49.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:54:49.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:54:49.86#ibcon#enter wrdev, iclass 11, count 2 2006.285.22:54:49.86#ibcon#first serial, iclass 11, count 2 2006.285.22:54:49.86#ibcon#enter sib2, iclass 11, count 2 2006.285.22:54:49.86#ibcon#flushed, iclass 11, count 2 2006.285.22:54:49.86#ibcon#about to write, iclass 11, count 2 2006.285.22:54:49.86#ibcon#wrote, iclass 11, count 2 2006.285.22:54:49.86#ibcon#about to read 3, iclass 11, count 2 2006.285.22:54:49.88#ibcon#read 3, iclass 11, count 2 2006.285.22:54:49.88#ibcon#about to read 4, iclass 11, count 2 2006.285.22:54:49.88#ibcon#read 4, iclass 11, count 2 2006.285.22:54:49.88#ibcon#about to read 5, iclass 11, count 2 2006.285.22:54:49.88#ibcon#read 5, iclass 11, count 2 2006.285.22:54:49.88#ibcon#about to read 6, iclass 11, count 2 2006.285.22:54:49.88#ibcon#read 6, iclass 11, count 2 2006.285.22:54:49.88#ibcon#end of sib2, iclass 11, count 2 2006.285.22:54:49.88#ibcon#*mode == 0, iclass 11, count 2 2006.285.22:54:49.88#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.22:54:49.88#ibcon#[25=AT04-06\r\n] 2006.285.22:54:49.88#ibcon#*before write, iclass 11, count 2 2006.285.22:54:49.88#ibcon#enter sib2, iclass 11, count 2 2006.285.22:54:49.88#ibcon#flushed, iclass 11, count 2 2006.285.22:54:49.88#ibcon#about to write, iclass 11, count 2 2006.285.22:54:49.88#ibcon#wrote, iclass 11, count 2 2006.285.22:54:49.88#ibcon#about to read 3, iclass 11, count 2 2006.285.22:54:49.91#ibcon#read 3, iclass 11, count 2 2006.285.22:54:49.91#ibcon#about to read 4, iclass 11, count 2 2006.285.22:54:49.91#ibcon#read 4, iclass 11, count 2 2006.285.22:54:49.91#ibcon#about to read 5, iclass 11, count 2 2006.285.22:54:49.91#ibcon#read 5, iclass 11, count 2 2006.285.22:54:49.91#ibcon#about to read 6, iclass 11, count 2 2006.285.22:54:49.91#ibcon#read 6, iclass 11, count 2 2006.285.22:54:49.91#ibcon#end of sib2, iclass 11, count 2 2006.285.22:54:49.91#ibcon#*after write, iclass 11, count 2 2006.285.22:54:49.91#ibcon#*before return 0, iclass 11, count 2 2006.285.22:54:49.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:54:49.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.22:54:49.91#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.22:54:49.91#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:49.91#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:54:50.03#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:54:50.03#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:54:50.03#ibcon#enter wrdev, iclass 11, count 0 2006.285.22:54:50.03#ibcon#first serial, iclass 11, count 0 2006.285.22:54:50.03#ibcon#enter sib2, iclass 11, count 0 2006.285.22:54:50.03#ibcon#flushed, iclass 11, count 0 2006.285.22:54:50.03#ibcon#about to write, iclass 11, count 0 2006.285.22:54:50.03#ibcon#wrote, iclass 11, count 0 2006.285.22:54:50.03#ibcon#about to read 3, iclass 11, count 0 2006.285.22:54:50.05#ibcon#read 3, iclass 11, count 0 2006.285.22:54:50.05#ibcon#about to read 4, iclass 11, count 0 2006.285.22:54:50.05#ibcon#read 4, iclass 11, count 0 2006.285.22:54:50.05#ibcon#about to read 5, iclass 11, count 0 2006.285.22:54:50.05#ibcon#read 5, iclass 11, count 0 2006.285.22:54:50.05#ibcon#about to read 6, iclass 11, count 0 2006.285.22:54:50.05#ibcon#read 6, iclass 11, count 0 2006.285.22:54:50.05#ibcon#end of sib2, iclass 11, count 0 2006.285.22:54:50.05#ibcon#*mode == 0, iclass 11, count 0 2006.285.22:54:50.05#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.22:54:50.05#ibcon#[25=USB\r\n] 2006.285.22:54:50.05#ibcon#*before write, iclass 11, count 0 2006.285.22:54:50.05#ibcon#enter sib2, iclass 11, count 0 2006.285.22:54:50.05#ibcon#flushed, iclass 11, count 0 2006.285.22:54:50.05#ibcon#about to write, iclass 11, count 0 2006.285.22:54:50.05#ibcon#wrote, iclass 11, count 0 2006.285.22:54:50.05#ibcon#about to read 3, iclass 11, count 0 2006.285.22:54:50.08#ibcon#read 3, iclass 11, count 0 2006.285.22:54:50.08#ibcon#about to read 4, iclass 11, count 0 2006.285.22:54:50.08#ibcon#read 4, iclass 11, count 0 2006.285.22:54:50.08#ibcon#about to read 5, iclass 11, count 0 2006.285.22:54:50.08#ibcon#read 5, iclass 11, count 0 2006.285.22:54:50.08#ibcon#about to read 6, iclass 11, count 0 2006.285.22:54:50.08#ibcon#read 6, iclass 11, count 0 2006.285.22:54:50.08#ibcon#end of sib2, iclass 11, count 0 2006.285.22:54:50.08#ibcon#*after write, iclass 11, count 0 2006.285.22:54:50.08#ibcon#*before return 0, iclass 11, count 0 2006.285.22:54:50.08#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:54:50.08#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.22:54:50.08#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.22:54:50.08#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.22:54:50.08$vck44/valo=5,734.99 2006.285.22:54:50.08#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.22:54:50.08#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.22:54:50.08#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:50.08#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:54:50.08#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:54:50.08#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:54:50.08#ibcon#enter wrdev, iclass 13, count 0 2006.285.22:54:50.08#ibcon#first serial, iclass 13, count 0 2006.285.22:54:50.08#ibcon#enter sib2, iclass 13, count 0 2006.285.22:54:50.08#ibcon#flushed, iclass 13, count 0 2006.285.22:54:50.08#ibcon#about to write, iclass 13, count 0 2006.285.22:54:50.08#ibcon#wrote, iclass 13, count 0 2006.285.22:54:50.08#ibcon#about to read 3, iclass 13, count 0 2006.285.22:54:50.10#ibcon#read 3, iclass 13, count 0 2006.285.22:54:50.10#ibcon#about to read 4, iclass 13, count 0 2006.285.22:54:50.10#ibcon#read 4, iclass 13, count 0 2006.285.22:54:50.10#ibcon#about to read 5, iclass 13, count 0 2006.285.22:54:50.10#ibcon#read 5, iclass 13, count 0 2006.285.22:54:50.10#ibcon#about to read 6, iclass 13, count 0 2006.285.22:54:50.10#ibcon#read 6, iclass 13, count 0 2006.285.22:54:50.10#ibcon#end of sib2, iclass 13, count 0 2006.285.22:54:50.10#ibcon#*mode == 0, iclass 13, count 0 2006.285.22:54:50.10#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.22:54:50.10#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:54:50.10#ibcon#*before write, iclass 13, count 0 2006.285.22:54:50.10#ibcon#enter sib2, iclass 13, count 0 2006.285.22:54:50.10#ibcon#flushed, iclass 13, count 0 2006.285.22:54:50.10#ibcon#about to write, iclass 13, count 0 2006.285.22:54:50.10#ibcon#wrote, iclass 13, count 0 2006.285.22:54:50.10#ibcon#about to read 3, iclass 13, count 0 2006.285.22:54:50.14#ibcon#read 3, iclass 13, count 0 2006.285.22:54:50.14#ibcon#about to read 4, iclass 13, count 0 2006.285.22:54:50.14#ibcon#read 4, iclass 13, count 0 2006.285.22:54:50.14#ibcon#about to read 5, iclass 13, count 0 2006.285.22:54:50.14#ibcon#read 5, iclass 13, count 0 2006.285.22:54:50.14#ibcon#about to read 6, iclass 13, count 0 2006.285.22:54:50.14#ibcon#read 6, iclass 13, count 0 2006.285.22:54:50.14#ibcon#end of sib2, iclass 13, count 0 2006.285.22:54:50.14#ibcon#*after write, iclass 13, count 0 2006.285.22:54:50.14#ibcon#*before return 0, iclass 13, count 0 2006.285.22:54:50.14#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:54:50.14#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:54:50.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.22:54:50.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.22:54:50.14$vck44/va=5,3 2006.285.22:54:50.14#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.22:54:50.14#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.22:54:50.14#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:50.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:54:50.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:54:50.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:54:50.20#ibcon#enter wrdev, iclass 15, count 2 2006.285.22:54:50.20#ibcon#first serial, iclass 15, count 2 2006.285.22:54:50.20#ibcon#enter sib2, iclass 15, count 2 2006.285.22:54:50.20#ibcon#flushed, iclass 15, count 2 2006.285.22:54:50.20#ibcon#about to write, iclass 15, count 2 2006.285.22:54:50.20#ibcon#wrote, iclass 15, count 2 2006.285.22:54:50.20#ibcon#about to read 3, iclass 15, count 2 2006.285.22:54:50.22#ibcon#read 3, iclass 15, count 2 2006.285.22:54:50.22#ibcon#about to read 4, iclass 15, count 2 2006.285.22:54:50.22#ibcon#read 4, iclass 15, count 2 2006.285.22:54:50.22#ibcon#about to read 5, iclass 15, count 2 2006.285.22:54:50.22#ibcon#read 5, iclass 15, count 2 2006.285.22:54:50.22#ibcon#about to read 6, iclass 15, count 2 2006.285.22:54:50.22#ibcon#read 6, iclass 15, count 2 2006.285.22:54:50.22#ibcon#end of sib2, iclass 15, count 2 2006.285.22:54:50.22#ibcon#*mode == 0, iclass 15, count 2 2006.285.22:54:50.22#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.22:54:50.22#ibcon#[25=AT05-03\r\n] 2006.285.22:54:50.22#ibcon#*before write, iclass 15, count 2 2006.285.22:54:50.22#ibcon#enter sib2, iclass 15, count 2 2006.285.22:54:50.22#ibcon#flushed, iclass 15, count 2 2006.285.22:54:50.22#ibcon#about to write, iclass 15, count 2 2006.285.22:54:50.22#ibcon#wrote, iclass 15, count 2 2006.285.22:54:50.22#ibcon#about to read 3, iclass 15, count 2 2006.285.22:54:50.25#ibcon#read 3, iclass 15, count 2 2006.285.22:54:50.25#ibcon#about to read 4, iclass 15, count 2 2006.285.22:54:50.25#ibcon#read 4, iclass 15, count 2 2006.285.22:54:50.25#ibcon#about to read 5, iclass 15, count 2 2006.285.22:54:50.25#ibcon#read 5, iclass 15, count 2 2006.285.22:54:50.25#ibcon#about to read 6, iclass 15, count 2 2006.285.22:54:50.25#ibcon#read 6, iclass 15, count 2 2006.285.22:54:50.25#ibcon#end of sib2, iclass 15, count 2 2006.285.22:54:50.25#ibcon#*after write, iclass 15, count 2 2006.285.22:54:50.25#ibcon#*before return 0, iclass 15, count 2 2006.285.22:54:50.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:54:50.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:54:50.25#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.22:54:50.25#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:50.25#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:54:50.37#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:54:50.37#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:54:50.37#ibcon#enter wrdev, iclass 15, count 0 2006.285.22:54:50.37#ibcon#first serial, iclass 15, count 0 2006.285.22:54:50.37#ibcon#enter sib2, iclass 15, count 0 2006.285.22:54:50.37#ibcon#flushed, iclass 15, count 0 2006.285.22:54:50.37#ibcon#about to write, iclass 15, count 0 2006.285.22:54:50.37#ibcon#wrote, iclass 15, count 0 2006.285.22:54:50.37#ibcon#about to read 3, iclass 15, count 0 2006.285.22:54:50.39#ibcon#read 3, iclass 15, count 0 2006.285.22:54:50.39#ibcon#about to read 4, iclass 15, count 0 2006.285.22:54:50.39#ibcon#read 4, iclass 15, count 0 2006.285.22:54:50.39#ibcon#about to read 5, iclass 15, count 0 2006.285.22:54:50.39#ibcon#read 5, iclass 15, count 0 2006.285.22:54:50.39#ibcon#about to read 6, iclass 15, count 0 2006.285.22:54:50.39#ibcon#read 6, iclass 15, count 0 2006.285.22:54:50.39#ibcon#end of sib2, iclass 15, count 0 2006.285.22:54:50.39#ibcon#*mode == 0, iclass 15, count 0 2006.285.22:54:50.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.22:54:50.39#ibcon#[25=USB\r\n] 2006.285.22:54:50.39#ibcon#*before write, iclass 15, count 0 2006.285.22:54:50.39#ibcon#enter sib2, iclass 15, count 0 2006.285.22:54:50.39#ibcon#flushed, iclass 15, count 0 2006.285.22:54:50.39#ibcon#about to write, iclass 15, count 0 2006.285.22:54:50.39#ibcon#wrote, iclass 15, count 0 2006.285.22:54:50.39#ibcon#about to read 3, iclass 15, count 0 2006.285.22:54:50.42#ibcon#read 3, iclass 15, count 0 2006.285.22:54:50.42#ibcon#about to read 4, iclass 15, count 0 2006.285.22:54:50.42#ibcon#read 4, iclass 15, count 0 2006.285.22:54:50.42#ibcon#about to read 5, iclass 15, count 0 2006.285.22:54:50.42#ibcon#read 5, iclass 15, count 0 2006.285.22:54:50.42#ibcon#about to read 6, iclass 15, count 0 2006.285.22:54:50.42#ibcon#read 6, iclass 15, count 0 2006.285.22:54:50.42#ibcon#end of sib2, iclass 15, count 0 2006.285.22:54:50.42#ibcon#*after write, iclass 15, count 0 2006.285.22:54:50.42#ibcon#*before return 0, iclass 15, count 0 2006.285.22:54:50.42#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:54:50.42#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:54:50.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.22:54:50.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.22:54:50.42$vck44/valo=6,814.99 2006.285.22:54:50.42#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.22:54:50.42#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.22:54:50.42#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:50.42#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:54:50.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:54:50.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:54:50.42#ibcon#enter wrdev, iclass 17, count 0 2006.285.22:54:50.42#ibcon#first serial, iclass 17, count 0 2006.285.22:54:50.42#ibcon#enter sib2, iclass 17, count 0 2006.285.22:54:50.42#ibcon#flushed, iclass 17, count 0 2006.285.22:54:50.42#ibcon#about to write, iclass 17, count 0 2006.285.22:54:50.42#ibcon#wrote, iclass 17, count 0 2006.285.22:54:50.42#ibcon#about to read 3, iclass 17, count 0 2006.285.22:54:50.44#ibcon#read 3, iclass 17, count 0 2006.285.22:54:50.44#ibcon#about to read 4, iclass 17, count 0 2006.285.22:54:50.44#ibcon#read 4, iclass 17, count 0 2006.285.22:54:50.44#ibcon#about to read 5, iclass 17, count 0 2006.285.22:54:50.44#ibcon#read 5, iclass 17, count 0 2006.285.22:54:50.44#ibcon#about to read 6, iclass 17, count 0 2006.285.22:54:50.44#ibcon#read 6, iclass 17, count 0 2006.285.22:54:50.44#ibcon#end of sib2, iclass 17, count 0 2006.285.22:54:50.44#ibcon#*mode == 0, iclass 17, count 0 2006.285.22:54:50.44#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.22:54:50.44#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:54:50.44#ibcon#*before write, iclass 17, count 0 2006.285.22:54:50.44#ibcon#enter sib2, iclass 17, count 0 2006.285.22:54:50.44#ibcon#flushed, iclass 17, count 0 2006.285.22:54:50.44#ibcon#about to write, iclass 17, count 0 2006.285.22:54:50.44#ibcon#wrote, iclass 17, count 0 2006.285.22:54:50.44#ibcon#about to read 3, iclass 17, count 0 2006.285.22:54:50.48#ibcon#read 3, iclass 17, count 0 2006.285.22:54:50.48#ibcon#about to read 4, iclass 17, count 0 2006.285.22:54:50.48#ibcon#read 4, iclass 17, count 0 2006.285.22:54:50.48#ibcon#about to read 5, iclass 17, count 0 2006.285.22:54:50.48#ibcon#read 5, iclass 17, count 0 2006.285.22:54:50.48#ibcon#about to read 6, iclass 17, count 0 2006.285.22:54:50.48#ibcon#read 6, iclass 17, count 0 2006.285.22:54:50.48#ibcon#end of sib2, iclass 17, count 0 2006.285.22:54:50.48#ibcon#*after write, iclass 17, count 0 2006.285.22:54:50.48#ibcon#*before return 0, iclass 17, count 0 2006.285.22:54:50.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:54:50.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:54:50.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.22:54:50.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.22:54:50.48$vck44/va=6,4 2006.285.22:54:50.48#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.22:54:50.48#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.22:54:50.48#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:50.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:54:50.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:54:50.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:54:50.54#ibcon#enter wrdev, iclass 19, count 2 2006.285.22:54:50.54#ibcon#first serial, iclass 19, count 2 2006.285.22:54:50.54#ibcon#enter sib2, iclass 19, count 2 2006.285.22:54:50.54#ibcon#flushed, iclass 19, count 2 2006.285.22:54:50.54#ibcon#about to write, iclass 19, count 2 2006.285.22:54:50.54#ibcon#wrote, iclass 19, count 2 2006.285.22:54:50.54#ibcon#about to read 3, iclass 19, count 2 2006.285.22:54:50.56#ibcon#read 3, iclass 19, count 2 2006.285.22:54:50.56#ibcon#about to read 4, iclass 19, count 2 2006.285.22:54:50.56#ibcon#read 4, iclass 19, count 2 2006.285.22:54:50.56#ibcon#about to read 5, iclass 19, count 2 2006.285.22:54:50.56#ibcon#read 5, iclass 19, count 2 2006.285.22:54:50.56#ibcon#about to read 6, iclass 19, count 2 2006.285.22:54:50.56#ibcon#read 6, iclass 19, count 2 2006.285.22:54:50.56#ibcon#end of sib2, iclass 19, count 2 2006.285.22:54:50.56#ibcon#*mode == 0, iclass 19, count 2 2006.285.22:54:50.56#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.22:54:50.56#ibcon#[25=AT06-04\r\n] 2006.285.22:54:50.56#ibcon#*before write, iclass 19, count 2 2006.285.22:54:50.56#ibcon#enter sib2, iclass 19, count 2 2006.285.22:54:50.56#ibcon#flushed, iclass 19, count 2 2006.285.22:54:50.56#ibcon#about to write, iclass 19, count 2 2006.285.22:54:50.56#ibcon#wrote, iclass 19, count 2 2006.285.22:54:50.56#ibcon#about to read 3, iclass 19, count 2 2006.285.22:54:50.59#ibcon#read 3, iclass 19, count 2 2006.285.22:54:50.59#ibcon#about to read 4, iclass 19, count 2 2006.285.22:54:50.59#ibcon#read 4, iclass 19, count 2 2006.285.22:54:50.59#ibcon#about to read 5, iclass 19, count 2 2006.285.22:54:50.59#ibcon#read 5, iclass 19, count 2 2006.285.22:54:50.59#ibcon#about to read 6, iclass 19, count 2 2006.285.22:54:50.59#ibcon#read 6, iclass 19, count 2 2006.285.22:54:50.59#ibcon#end of sib2, iclass 19, count 2 2006.285.22:54:50.59#ibcon#*after write, iclass 19, count 2 2006.285.22:54:50.59#ibcon#*before return 0, iclass 19, count 2 2006.285.22:54:50.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:54:50.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:54:50.59#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.22:54:50.59#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:50.59#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:54:50.71#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:54:50.71#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:54:50.71#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:54:50.71#ibcon#first serial, iclass 19, count 0 2006.285.22:54:50.71#ibcon#enter sib2, iclass 19, count 0 2006.285.22:54:50.71#ibcon#flushed, iclass 19, count 0 2006.285.22:54:50.71#ibcon#about to write, iclass 19, count 0 2006.285.22:54:50.71#ibcon#wrote, iclass 19, count 0 2006.285.22:54:50.71#ibcon#about to read 3, iclass 19, count 0 2006.285.22:54:50.73#ibcon#read 3, iclass 19, count 0 2006.285.22:54:50.73#ibcon#about to read 4, iclass 19, count 0 2006.285.22:54:50.73#ibcon#read 4, iclass 19, count 0 2006.285.22:54:50.73#ibcon#about to read 5, iclass 19, count 0 2006.285.22:54:50.73#ibcon#read 5, iclass 19, count 0 2006.285.22:54:50.73#ibcon#about to read 6, iclass 19, count 0 2006.285.22:54:50.73#ibcon#read 6, iclass 19, count 0 2006.285.22:54:50.73#ibcon#end of sib2, iclass 19, count 0 2006.285.22:54:50.73#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:54:50.73#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:54:50.73#ibcon#[25=USB\r\n] 2006.285.22:54:50.73#ibcon#*before write, iclass 19, count 0 2006.285.22:54:50.73#ibcon#enter sib2, iclass 19, count 0 2006.285.22:54:50.73#ibcon#flushed, iclass 19, count 0 2006.285.22:54:50.73#ibcon#about to write, iclass 19, count 0 2006.285.22:54:50.73#ibcon#wrote, iclass 19, count 0 2006.285.22:54:50.73#ibcon#about to read 3, iclass 19, count 0 2006.285.22:54:50.76#ibcon#read 3, iclass 19, count 0 2006.285.22:54:50.76#ibcon#about to read 4, iclass 19, count 0 2006.285.22:54:50.76#ibcon#read 4, iclass 19, count 0 2006.285.22:54:50.76#ibcon#about to read 5, iclass 19, count 0 2006.285.22:54:50.76#ibcon#read 5, iclass 19, count 0 2006.285.22:54:50.76#ibcon#about to read 6, iclass 19, count 0 2006.285.22:54:50.76#ibcon#read 6, iclass 19, count 0 2006.285.22:54:50.76#ibcon#end of sib2, iclass 19, count 0 2006.285.22:54:50.76#ibcon#*after write, iclass 19, count 0 2006.285.22:54:50.76#ibcon#*before return 0, iclass 19, count 0 2006.285.22:54:50.76#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:54:50.76#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:54:50.76#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:54:50.76#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:54:50.76$vck44/valo=7,864.99 2006.285.22:54:50.76#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.22:54:50.76#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.22:54:50.76#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:50.76#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:54:50.76#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:54:50.76#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:54:50.76#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:54:50.76#ibcon#first serial, iclass 21, count 0 2006.285.22:54:50.76#ibcon#enter sib2, iclass 21, count 0 2006.285.22:54:50.76#ibcon#flushed, iclass 21, count 0 2006.285.22:54:50.76#ibcon#about to write, iclass 21, count 0 2006.285.22:54:50.76#ibcon#wrote, iclass 21, count 0 2006.285.22:54:50.76#ibcon#about to read 3, iclass 21, count 0 2006.285.22:54:50.78#ibcon#read 3, iclass 21, count 0 2006.285.22:54:50.78#ibcon#about to read 4, iclass 21, count 0 2006.285.22:54:50.78#ibcon#read 4, iclass 21, count 0 2006.285.22:54:50.78#ibcon#about to read 5, iclass 21, count 0 2006.285.22:54:50.78#ibcon#read 5, iclass 21, count 0 2006.285.22:54:50.78#ibcon#about to read 6, iclass 21, count 0 2006.285.22:54:50.78#ibcon#read 6, iclass 21, count 0 2006.285.22:54:50.78#ibcon#end of sib2, iclass 21, count 0 2006.285.22:54:50.78#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:54:50.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:54:50.78#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:54:50.78#ibcon#*before write, iclass 21, count 0 2006.285.22:54:50.78#ibcon#enter sib2, iclass 21, count 0 2006.285.22:54:50.78#ibcon#flushed, iclass 21, count 0 2006.285.22:54:50.78#ibcon#about to write, iclass 21, count 0 2006.285.22:54:50.78#ibcon#wrote, iclass 21, count 0 2006.285.22:54:50.78#ibcon#about to read 3, iclass 21, count 0 2006.285.22:54:50.82#ibcon#read 3, iclass 21, count 0 2006.285.22:54:50.82#ibcon#about to read 4, iclass 21, count 0 2006.285.22:54:50.82#ibcon#read 4, iclass 21, count 0 2006.285.22:54:50.82#ibcon#about to read 5, iclass 21, count 0 2006.285.22:54:50.82#ibcon#read 5, iclass 21, count 0 2006.285.22:54:50.82#ibcon#about to read 6, iclass 21, count 0 2006.285.22:54:50.82#ibcon#read 6, iclass 21, count 0 2006.285.22:54:50.82#ibcon#end of sib2, iclass 21, count 0 2006.285.22:54:50.82#ibcon#*after write, iclass 21, count 0 2006.285.22:54:50.82#ibcon#*before return 0, iclass 21, count 0 2006.285.22:54:50.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:54:50.82#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:54:50.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:54:50.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:54:50.82$vck44/va=7,4 2006.285.22:54:50.82#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.22:54:50.82#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.22:54:50.82#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:50.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:54:50.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:54:50.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:54:50.88#ibcon#enter wrdev, iclass 23, count 2 2006.285.22:54:50.88#ibcon#first serial, iclass 23, count 2 2006.285.22:54:50.88#ibcon#enter sib2, iclass 23, count 2 2006.285.22:54:50.88#ibcon#flushed, iclass 23, count 2 2006.285.22:54:50.88#ibcon#about to write, iclass 23, count 2 2006.285.22:54:50.88#ibcon#wrote, iclass 23, count 2 2006.285.22:54:50.88#ibcon#about to read 3, iclass 23, count 2 2006.285.22:54:50.90#ibcon#read 3, iclass 23, count 2 2006.285.22:54:50.90#ibcon#about to read 4, iclass 23, count 2 2006.285.22:54:50.90#ibcon#read 4, iclass 23, count 2 2006.285.22:54:50.90#ibcon#about to read 5, iclass 23, count 2 2006.285.22:54:50.90#ibcon#read 5, iclass 23, count 2 2006.285.22:54:50.90#ibcon#about to read 6, iclass 23, count 2 2006.285.22:54:50.90#ibcon#read 6, iclass 23, count 2 2006.285.22:54:50.90#ibcon#end of sib2, iclass 23, count 2 2006.285.22:54:50.90#ibcon#*mode == 0, iclass 23, count 2 2006.285.22:54:50.90#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.22:54:50.90#ibcon#[25=AT07-04\r\n] 2006.285.22:54:50.90#ibcon#*before write, iclass 23, count 2 2006.285.22:54:50.90#ibcon#enter sib2, iclass 23, count 2 2006.285.22:54:50.90#ibcon#flushed, iclass 23, count 2 2006.285.22:54:50.90#ibcon#about to write, iclass 23, count 2 2006.285.22:54:50.90#ibcon#wrote, iclass 23, count 2 2006.285.22:54:50.90#ibcon#about to read 3, iclass 23, count 2 2006.285.22:54:50.93#ibcon#read 3, iclass 23, count 2 2006.285.22:54:50.93#ibcon#about to read 4, iclass 23, count 2 2006.285.22:54:50.93#ibcon#read 4, iclass 23, count 2 2006.285.22:54:50.93#ibcon#about to read 5, iclass 23, count 2 2006.285.22:54:50.93#ibcon#read 5, iclass 23, count 2 2006.285.22:54:50.93#ibcon#about to read 6, iclass 23, count 2 2006.285.22:54:50.93#ibcon#read 6, iclass 23, count 2 2006.285.22:54:50.93#ibcon#end of sib2, iclass 23, count 2 2006.285.22:54:50.93#ibcon#*after write, iclass 23, count 2 2006.285.22:54:50.93#ibcon#*before return 0, iclass 23, count 2 2006.285.22:54:50.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:54:50.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:54:50.93#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.22:54:50.93#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:50.93#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:54:51.05#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:54:51.05#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:54:51.05#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:54:51.05#ibcon#first serial, iclass 23, count 0 2006.285.22:54:51.05#ibcon#enter sib2, iclass 23, count 0 2006.285.22:54:51.05#ibcon#flushed, iclass 23, count 0 2006.285.22:54:51.05#ibcon#about to write, iclass 23, count 0 2006.285.22:54:51.05#ibcon#wrote, iclass 23, count 0 2006.285.22:54:51.05#ibcon#about to read 3, iclass 23, count 0 2006.285.22:54:51.07#ibcon#read 3, iclass 23, count 0 2006.285.22:54:51.07#ibcon#about to read 4, iclass 23, count 0 2006.285.22:54:51.07#ibcon#read 4, iclass 23, count 0 2006.285.22:54:51.07#ibcon#about to read 5, iclass 23, count 0 2006.285.22:54:51.07#ibcon#read 5, iclass 23, count 0 2006.285.22:54:51.07#ibcon#about to read 6, iclass 23, count 0 2006.285.22:54:51.07#ibcon#read 6, iclass 23, count 0 2006.285.22:54:51.07#ibcon#end of sib2, iclass 23, count 0 2006.285.22:54:51.07#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:54:51.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:54:51.07#ibcon#[25=USB\r\n] 2006.285.22:54:51.07#ibcon#*before write, iclass 23, count 0 2006.285.22:54:51.07#ibcon#enter sib2, iclass 23, count 0 2006.285.22:54:51.07#ibcon#flushed, iclass 23, count 0 2006.285.22:54:51.07#ibcon#about to write, iclass 23, count 0 2006.285.22:54:51.07#ibcon#wrote, iclass 23, count 0 2006.285.22:54:51.07#ibcon#about to read 3, iclass 23, count 0 2006.285.22:54:51.10#ibcon#read 3, iclass 23, count 0 2006.285.22:54:51.10#ibcon#about to read 4, iclass 23, count 0 2006.285.22:54:51.10#ibcon#read 4, iclass 23, count 0 2006.285.22:54:51.10#ibcon#about to read 5, iclass 23, count 0 2006.285.22:54:51.10#ibcon#read 5, iclass 23, count 0 2006.285.22:54:51.10#ibcon#about to read 6, iclass 23, count 0 2006.285.22:54:51.10#ibcon#read 6, iclass 23, count 0 2006.285.22:54:51.10#ibcon#end of sib2, iclass 23, count 0 2006.285.22:54:51.10#ibcon#*after write, iclass 23, count 0 2006.285.22:54:51.10#ibcon#*before return 0, iclass 23, count 0 2006.285.22:54:51.10#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:54:51.10#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:54:51.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:54:51.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:54:51.10$vck44/valo=8,884.99 2006.285.22:54:51.10#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.22:54:51.10#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.22:54:51.10#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:51.10#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:54:51.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:54:51.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:54:51.10#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:54:51.10#ibcon#first serial, iclass 25, count 0 2006.285.22:54:51.10#ibcon#enter sib2, iclass 25, count 0 2006.285.22:54:51.10#ibcon#flushed, iclass 25, count 0 2006.285.22:54:51.10#ibcon#about to write, iclass 25, count 0 2006.285.22:54:51.10#ibcon#wrote, iclass 25, count 0 2006.285.22:54:51.10#ibcon#about to read 3, iclass 25, count 0 2006.285.22:54:51.12#ibcon#read 3, iclass 25, count 0 2006.285.22:54:51.12#ibcon#about to read 4, iclass 25, count 0 2006.285.22:54:51.12#ibcon#read 4, iclass 25, count 0 2006.285.22:54:51.12#ibcon#about to read 5, iclass 25, count 0 2006.285.22:54:51.12#ibcon#read 5, iclass 25, count 0 2006.285.22:54:51.12#ibcon#about to read 6, iclass 25, count 0 2006.285.22:54:51.12#ibcon#read 6, iclass 25, count 0 2006.285.22:54:51.12#ibcon#end of sib2, iclass 25, count 0 2006.285.22:54:51.12#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:54:51.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:54:51.12#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:54:51.12#ibcon#*before write, iclass 25, count 0 2006.285.22:54:51.12#ibcon#enter sib2, iclass 25, count 0 2006.285.22:54:51.12#ibcon#flushed, iclass 25, count 0 2006.285.22:54:51.12#ibcon#about to write, iclass 25, count 0 2006.285.22:54:51.12#ibcon#wrote, iclass 25, count 0 2006.285.22:54:51.12#ibcon#about to read 3, iclass 25, count 0 2006.285.22:54:51.16#ibcon#read 3, iclass 25, count 0 2006.285.22:54:51.16#ibcon#about to read 4, iclass 25, count 0 2006.285.22:54:51.16#ibcon#read 4, iclass 25, count 0 2006.285.22:54:51.16#ibcon#about to read 5, iclass 25, count 0 2006.285.22:54:51.16#ibcon#read 5, iclass 25, count 0 2006.285.22:54:51.16#ibcon#about to read 6, iclass 25, count 0 2006.285.22:54:51.16#ibcon#read 6, iclass 25, count 0 2006.285.22:54:51.16#ibcon#end of sib2, iclass 25, count 0 2006.285.22:54:51.16#ibcon#*after write, iclass 25, count 0 2006.285.22:54:51.16#ibcon#*before return 0, iclass 25, count 0 2006.285.22:54:51.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:54:51.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:54:51.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:54:51.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:54:51.16$vck44/va=8,3 2006.285.22:54:51.16#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.22:54:51.16#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.22:54:51.16#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:51.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:54:51.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:54:51.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:54:51.22#ibcon#enter wrdev, iclass 27, count 2 2006.285.22:54:51.22#ibcon#first serial, iclass 27, count 2 2006.285.22:54:51.22#ibcon#enter sib2, iclass 27, count 2 2006.285.22:54:51.22#ibcon#flushed, iclass 27, count 2 2006.285.22:54:51.22#ibcon#about to write, iclass 27, count 2 2006.285.22:54:51.22#ibcon#wrote, iclass 27, count 2 2006.285.22:54:51.22#ibcon#about to read 3, iclass 27, count 2 2006.285.22:54:51.24#ibcon#read 3, iclass 27, count 2 2006.285.22:54:51.24#ibcon#about to read 4, iclass 27, count 2 2006.285.22:54:51.24#ibcon#read 4, iclass 27, count 2 2006.285.22:54:51.24#ibcon#about to read 5, iclass 27, count 2 2006.285.22:54:51.24#ibcon#read 5, iclass 27, count 2 2006.285.22:54:51.24#ibcon#about to read 6, iclass 27, count 2 2006.285.22:54:51.24#ibcon#read 6, iclass 27, count 2 2006.285.22:54:51.24#ibcon#end of sib2, iclass 27, count 2 2006.285.22:54:51.24#ibcon#*mode == 0, iclass 27, count 2 2006.285.22:54:51.24#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.22:54:51.24#ibcon#[25=AT08-03\r\n] 2006.285.22:54:51.24#ibcon#*before write, iclass 27, count 2 2006.285.22:54:51.24#ibcon#enter sib2, iclass 27, count 2 2006.285.22:54:51.24#ibcon#flushed, iclass 27, count 2 2006.285.22:54:51.24#ibcon#about to write, iclass 27, count 2 2006.285.22:54:51.24#ibcon#wrote, iclass 27, count 2 2006.285.22:54:51.24#ibcon#about to read 3, iclass 27, count 2 2006.285.22:54:51.27#ibcon#read 3, iclass 27, count 2 2006.285.22:54:51.27#ibcon#about to read 4, iclass 27, count 2 2006.285.22:54:51.27#ibcon#read 4, iclass 27, count 2 2006.285.22:54:51.27#ibcon#about to read 5, iclass 27, count 2 2006.285.22:54:51.27#ibcon#read 5, iclass 27, count 2 2006.285.22:54:51.27#ibcon#about to read 6, iclass 27, count 2 2006.285.22:54:51.27#ibcon#read 6, iclass 27, count 2 2006.285.22:54:51.27#ibcon#end of sib2, iclass 27, count 2 2006.285.22:54:51.27#ibcon#*after write, iclass 27, count 2 2006.285.22:54:51.27#ibcon#*before return 0, iclass 27, count 2 2006.285.22:54:51.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:54:51.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:54:51.27#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.22:54:51.27#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:51.27#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:54:51.39#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:54:51.39#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:54:51.39#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:54:51.39#ibcon#first serial, iclass 27, count 0 2006.285.22:54:51.39#ibcon#enter sib2, iclass 27, count 0 2006.285.22:54:51.39#ibcon#flushed, iclass 27, count 0 2006.285.22:54:51.39#ibcon#about to write, iclass 27, count 0 2006.285.22:54:51.39#ibcon#wrote, iclass 27, count 0 2006.285.22:54:51.39#ibcon#about to read 3, iclass 27, count 0 2006.285.22:54:51.41#ibcon#read 3, iclass 27, count 0 2006.285.22:54:51.41#ibcon#about to read 4, iclass 27, count 0 2006.285.22:54:51.41#ibcon#read 4, iclass 27, count 0 2006.285.22:54:51.41#ibcon#about to read 5, iclass 27, count 0 2006.285.22:54:51.41#ibcon#read 5, iclass 27, count 0 2006.285.22:54:51.41#ibcon#about to read 6, iclass 27, count 0 2006.285.22:54:51.41#ibcon#read 6, iclass 27, count 0 2006.285.22:54:51.41#ibcon#end of sib2, iclass 27, count 0 2006.285.22:54:51.41#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:54:51.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:54:51.41#ibcon#[25=USB\r\n] 2006.285.22:54:51.41#ibcon#*before write, iclass 27, count 0 2006.285.22:54:51.41#ibcon#enter sib2, iclass 27, count 0 2006.285.22:54:51.41#ibcon#flushed, iclass 27, count 0 2006.285.22:54:51.41#ibcon#about to write, iclass 27, count 0 2006.285.22:54:51.41#ibcon#wrote, iclass 27, count 0 2006.285.22:54:51.41#ibcon#about to read 3, iclass 27, count 0 2006.285.22:54:51.44#ibcon#read 3, iclass 27, count 0 2006.285.22:54:51.44#ibcon#about to read 4, iclass 27, count 0 2006.285.22:54:51.44#ibcon#read 4, iclass 27, count 0 2006.285.22:54:51.44#ibcon#about to read 5, iclass 27, count 0 2006.285.22:54:51.44#ibcon#read 5, iclass 27, count 0 2006.285.22:54:51.44#ibcon#about to read 6, iclass 27, count 0 2006.285.22:54:51.44#ibcon#read 6, iclass 27, count 0 2006.285.22:54:51.44#ibcon#end of sib2, iclass 27, count 0 2006.285.22:54:51.44#ibcon#*after write, iclass 27, count 0 2006.285.22:54:51.44#ibcon#*before return 0, iclass 27, count 0 2006.285.22:54:51.44#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:54:51.44#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:54:51.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:54:51.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:54:51.44$vck44/vblo=1,629.99 2006.285.22:54:51.44#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.22:54:51.44#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.22:54:51.44#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:51.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:54:51.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:54:51.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:54:51.44#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:54:51.44#ibcon#first serial, iclass 29, count 0 2006.285.22:54:51.44#ibcon#enter sib2, iclass 29, count 0 2006.285.22:54:51.44#ibcon#flushed, iclass 29, count 0 2006.285.22:54:51.44#ibcon#about to write, iclass 29, count 0 2006.285.22:54:51.44#ibcon#wrote, iclass 29, count 0 2006.285.22:54:51.44#ibcon#about to read 3, iclass 29, count 0 2006.285.22:54:51.46#ibcon#read 3, iclass 29, count 0 2006.285.22:54:51.46#ibcon#about to read 4, iclass 29, count 0 2006.285.22:54:51.46#ibcon#read 4, iclass 29, count 0 2006.285.22:54:51.46#ibcon#about to read 5, iclass 29, count 0 2006.285.22:54:51.46#ibcon#read 5, iclass 29, count 0 2006.285.22:54:51.46#ibcon#about to read 6, iclass 29, count 0 2006.285.22:54:51.46#ibcon#read 6, iclass 29, count 0 2006.285.22:54:51.46#ibcon#end of sib2, iclass 29, count 0 2006.285.22:54:51.46#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:54:51.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:54:51.46#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:54:51.46#ibcon#*before write, iclass 29, count 0 2006.285.22:54:51.46#ibcon#enter sib2, iclass 29, count 0 2006.285.22:54:51.46#ibcon#flushed, iclass 29, count 0 2006.285.22:54:51.46#ibcon#about to write, iclass 29, count 0 2006.285.22:54:51.46#ibcon#wrote, iclass 29, count 0 2006.285.22:54:51.46#ibcon#about to read 3, iclass 29, count 0 2006.285.22:54:51.50#ibcon#read 3, iclass 29, count 0 2006.285.22:54:51.50#ibcon#about to read 4, iclass 29, count 0 2006.285.22:54:51.50#ibcon#read 4, iclass 29, count 0 2006.285.22:54:51.50#ibcon#about to read 5, iclass 29, count 0 2006.285.22:54:51.50#ibcon#read 5, iclass 29, count 0 2006.285.22:54:51.50#ibcon#about to read 6, iclass 29, count 0 2006.285.22:54:51.50#ibcon#read 6, iclass 29, count 0 2006.285.22:54:51.50#ibcon#end of sib2, iclass 29, count 0 2006.285.22:54:51.50#ibcon#*after write, iclass 29, count 0 2006.285.22:54:51.50#ibcon#*before return 0, iclass 29, count 0 2006.285.22:54:51.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:54:51.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:54:51.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:54:51.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:54:51.50$vck44/vb=1,4 2006.285.22:54:51.50#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.22:54:51.50#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.22:54:51.50#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:51.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:54:51.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:54:51.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:54:51.50#ibcon#enter wrdev, iclass 31, count 2 2006.285.22:54:51.50#ibcon#first serial, iclass 31, count 2 2006.285.22:54:51.50#ibcon#enter sib2, iclass 31, count 2 2006.285.22:54:51.50#ibcon#flushed, iclass 31, count 2 2006.285.22:54:51.50#ibcon#about to write, iclass 31, count 2 2006.285.22:54:51.50#ibcon#wrote, iclass 31, count 2 2006.285.22:54:51.50#ibcon#about to read 3, iclass 31, count 2 2006.285.22:54:51.52#ibcon#read 3, iclass 31, count 2 2006.285.22:54:51.52#ibcon#about to read 4, iclass 31, count 2 2006.285.22:54:51.52#ibcon#read 4, iclass 31, count 2 2006.285.22:54:51.52#ibcon#about to read 5, iclass 31, count 2 2006.285.22:54:51.52#ibcon#read 5, iclass 31, count 2 2006.285.22:54:51.52#ibcon#about to read 6, iclass 31, count 2 2006.285.22:54:51.52#ibcon#read 6, iclass 31, count 2 2006.285.22:54:51.52#ibcon#end of sib2, iclass 31, count 2 2006.285.22:54:51.52#ibcon#*mode == 0, iclass 31, count 2 2006.285.22:54:51.52#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.22:54:51.52#ibcon#[27=AT01-04\r\n] 2006.285.22:54:51.52#ibcon#*before write, iclass 31, count 2 2006.285.22:54:51.52#ibcon#enter sib2, iclass 31, count 2 2006.285.22:54:51.52#ibcon#flushed, iclass 31, count 2 2006.285.22:54:51.52#ibcon#about to write, iclass 31, count 2 2006.285.22:54:51.52#ibcon#wrote, iclass 31, count 2 2006.285.22:54:51.52#ibcon#about to read 3, iclass 31, count 2 2006.285.22:54:51.55#ibcon#read 3, iclass 31, count 2 2006.285.22:54:51.55#ibcon#about to read 4, iclass 31, count 2 2006.285.22:54:51.55#ibcon#read 4, iclass 31, count 2 2006.285.22:54:51.55#ibcon#about to read 5, iclass 31, count 2 2006.285.22:54:51.55#ibcon#read 5, iclass 31, count 2 2006.285.22:54:51.55#ibcon#about to read 6, iclass 31, count 2 2006.285.22:54:51.55#ibcon#read 6, iclass 31, count 2 2006.285.22:54:51.55#ibcon#end of sib2, iclass 31, count 2 2006.285.22:54:51.55#ibcon#*after write, iclass 31, count 2 2006.285.22:54:51.55#ibcon#*before return 0, iclass 31, count 2 2006.285.22:54:51.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:54:51.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.22:54:51.55#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.22:54:51.55#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:51.55#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:54:51.67#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:54:51.67#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:54:51.67#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:54:51.67#ibcon#first serial, iclass 31, count 0 2006.285.22:54:51.67#ibcon#enter sib2, iclass 31, count 0 2006.285.22:54:51.67#ibcon#flushed, iclass 31, count 0 2006.285.22:54:51.67#ibcon#about to write, iclass 31, count 0 2006.285.22:54:51.67#ibcon#wrote, iclass 31, count 0 2006.285.22:54:51.67#ibcon#about to read 3, iclass 31, count 0 2006.285.22:54:51.69#ibcon#read 3, iclass 31, count 0 2006.285.22:54:51.69#ibcon#about to read 4, iclass 31, count 0 2006.285.22:54:51.69#ibcon#read 4, iclass 31, count 0 2006.285.22:54:51.69#ibcon#about to read 5, iclass 31, count 0 2006.285.22:54:51.69#ibcon#read 5, iclass 31, count 0 2006.285.22:54:51.69#ibcon#about to read 6, iclass 31, count 0 2006.285.22:54:51.69#ibcon#read 6, iclass 31, count 0 2006.285.22:54:51.69#ibcon#end of sib2, iclass 31, count 0 2006.285.22:54:51.69#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:54:51.69#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:54:51.69#ibcon#[27=USB\r\n] 2006.285.22:54:51.69#ibcon#*before write, iclass 31, count 0 2006.285.22:54:51.69#ibcon#enter sib2, iclass 31, count 0 2006.285.22:54:51.69#ibcon#flushed, iclass 31, count 0 2006.285.22:54:51.69#ibcon#about to write, iclass 31, count 0 2006.285.22:54:51.69#ibcon#wrote, iclass 31, count 0 2006.285.22:54:51.69#ibcon#about to read 3, iclass 31, count 0 2006.285.22:54:51.72#ibcon#read 3, iclass 31, count 0 2006.285.22:54:51.72#ibcon#about to read 4, iclass 31, count 0 2006.285.22:54:51.72#ibcon#read 4, iclass 31, count 0 2006.285.22:54:51.72#ibcon#about to read 5, iclass 31, count 0 2006.285.22:54:51.72#ibcon#read 5, iclass 31, count 0 2006.285.22:54:51.72#ibcon#about to read 6, iclass 31, count 0 2006.285.22:54:51.72#ibcon#read 6, iclass 31, count 0 2006.285.22:54:51.72#ibcon#end of sib2, iclass 31, count 0 2006.285.22:54:51.72#ibcon#*after write, iclass 31, count 0 2006.285.22:54:51.72#ibcon#*before return 0, iclass 31, count 0 2006.285.22:54:51.72#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:54:51.72#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.22:54:51.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:54:51.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:54:51.72$vck44/vblo=2,634.99 2006.285.22:54:51.72#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.22:54:51.72#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.22:54:51.72#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:51.72#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:54:51.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:54:51.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:54:51.72#ibcon#enter wrdev, iclass 33, count 0 2006.285.22:54:51.72#ibcon#first serial, iclass 33, count 0 2006.285.22:54:51.72#ibcon#enter sib2, iclass 33, count 0 2006.285.22:54:51.72#ibcon#flushed, iclass 33, count 0 2006.285.22:54:51.72#ibcon#about to write, iclass 33, count 0 2006.285.22:54:51.72#ibcon#wrote, iclass 33, count 0 2006.285.22:54:51.72#ibcon#about to read 3, iclass 33, count 0 2006.285.22:54:51.74#ibcon#read 3, iclass 33, count 0 2006.285.22:54:51.74#ibcon#about to read 4, iclass 33, count 0 2006.285.22:54:51.74#ibcon#read 4, iclass 33, count 0 2006.285.22:54:51.74#ibcon#about to read 5, iclass 33, count 0 2006.285.22:54:51.74#ibcon#read 5, iclass 33, count 0 2006.285.22:54:51.74#ibcon#about to read 6, iclass 33, count 0 2006.285.22:54:51.74#ibcon#read 6, iclass 33, count 0 2006.285.22:54:51.74#ibcon#end of sib2, iclass 33, count 0 2006.285.22:54:51.74#ibcon#*mode == 0, iclass 33, count 0 2006.285.22:54:51.74#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.22:54:51.74#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:54:51.74#ibcon#*before write, iclass 33, count 0 2006.285.22:54:51.74#ibcon#enter sib2, iclass 33, count 0 2006.285.22:54:51.74#ibcon#flushed, iclass 33, count 0 2006.285.22:54:51.74#ibcon#about to write, iclass 33, count 0 2006.285.22:54:51.74#ibcon#wrote, iclass 33, count 0 2006.285.22:54:51.74#ibcon#about to read 3, iclass 33, count 0 2006.285.22:54:51.78#ibcon#read 3, iclass 33, count 0 2006.285.22:54:51.78#ibcon#about to read 4, iclass 33, count 0 2006.285.22:54:51.78#ibcon#read 4, iclass 33, count 0 2006.285.22:54:51.78#ibcon#about to read 5, iclass 33, count 0 2006.285.22:54:51.78#ibcon#read 5, iclass 33, count 0 2006.285.22:54:51.78#ibcon#about to read 6, iclass 33, count 0 2006.285.22:54:51.78#ibcon#read 6, iclass 33, count 0 2006.285.22:54:51.78#ibcon#end of sib2, iclass 33, count 0 2006.285.22:54:51.78#ibcon#*after write, iclass 33, count 0 2006.285.22:54:51.78#ibcon#*before return 0, iclass 33, count 0 2006.285.22:54:51.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:54:51.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.22:54:51.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.22:54:51.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.22:54:51.78$vck44/vb=2,5 2006.285.22:54:51.78#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.22:54:51.78#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.22:54:51.78#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:51.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:54:51.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:54:51.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:54:51.84#ibcon#enter wrdev, iclass 35, count 2 2006.285.22:54:51.84#ibcon#first serial, iclass 35, count 2 2006.285.22:54:51.84#ibcon#enter sib2, iclass 35, count 2 2006.285.22:54:51.84#ibcon#flushed, iclass 35, count 2 2006.285.22:54:51.84#ibcon#about to write, iclass 35, count 2 2006.285.22:54:51.84#ibcon#wrote, iclass 35, count 2 2006.285.22:54:51.84#ibcon#about to read 3, iclass 35, count 2 2006.285.22:54:51.86#ibcon#read 3, iclass 35, count 2 2006.285.22:54:51.86#ibcon#about to read 4, iclass 35, count 2 2006.285.22:54:51.86#ibcon#read 4, iclass 35, count 2 2006.285.22:54:51.86#ibcon#about to read 5, iclass 35, count 2 2006.285.22:54:51.86#ibcon#read 5, iclass 35, count 2 2006.285.22:54:51.86#ibcon#about to read 6, iclass 35, count 2 2006.285.22:54:51.86#ibcon#read 6, iclass 35, count 2 2006.285.22:54:51.86#ibcon#end of sib2, iclass 35, count 2 2006.285.22:54:51.86#ibcon#*mode == 0, iclass 35, count 2 2006.285.22:54:51.86#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.22:54:51.86#ibcon#[27=AT02-05\r\n] 2006.285.22:54:51.86#ibcon#*before write, iclass 35, count 2 2006.285.22:54:51.86#ibcon#enter sib2, iclass 35, count 2 2006.285.22:54:51.86#ibcon#flushed, iclass 35, count 2 2006.285.22:54:51.86#ibcon#about to write, iclass 35, count 2 2006.285.22:54:51.86#ibcon#wrote, iclass 35, count 2 2006.285.22:54:51.86#ibcon#about to read 3, iclass 35, count 2 2006.285.22:54:51.89#ibcon#read 3, iclass 35, count 2 2006.285.22:54:51.89#ibcon#about to read 4, iclass 35, count 2 2006.285.22:54:51.89#ibcon#read 4, iclass 35, count 2 2006.285.22:54:51.89#ibcon#about to read 5, iclass 35, count 2 2006.285.22:54:51.89#ibcon#read 5, iclass 35, count 2 2006.285.22:54:51.89#ibcon#about to read 6, iclass 35, count 2 2006.285.22:54:51.89#ibcon#read 6, iclass 35, count 2 2006.285.22:54:51.89#ibcon#end of sib2, iclass 35, count 2 2006.285.22:54:51.89#ibcon#*after write, iclass 35, count 2 2006.285.22:54:51.89#ibcon#*before return 0, iclass 35, count 2 2006.285.22:54:51.89#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:54:51.89#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.22:54:51.89#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.22:54:51.89#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:51.89#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:54:52.01#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:54:52.01#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:54:52.01#ibcon#enter wrdev, iclass 35, count 0 2006.285.22:54:52.01#ibcon#first serial, iclass 35, count 0 2006.285.22:54:52.01#ibcon#enter sib2, iclass 35, count 0 2006.285.22:54:52.01#ibcon#flushed, iclass 35, count 0 2006.285.22:54:52.01#ibcon#about to write, iclass 35, count 0 2006.285.22:54:52.01#ibcon#wrote, iclass 35, count 0 2006.285.22:54:52.01#ibcon#about to read 3, iclass 35, count 0 2006.285.22:54:52.03#ibcon#read 3, iclass 35, count 0 2006.285.22:54:52.03#ibcon#about to read 4, iclass 35, count 0 2006.285.22:54:52.03#ibcon#read 4, iclass 35, count 0 2006.285.22:54:52.03#ibcon#about to read 5, iclass 35, count 0 2006.285.22:54:52.03#ibcon#read 5, iclass 35, count 0 2006.285.22:54:52.03#ibcon#about to read 6, iclass 35, count 0 2006.285.22:54:52.03#ibcon#read 6, iclass 35, count 0 2006.285.22:54:52.03#ibcon#end of sib2, iclass 35, count 0 2006.285.22:54:52.03#ibcon#*mode == 0, iclass 35, count 0 2006.285.22:54:52.03#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.22:54:52.03#ibcon#[27=USB\r\n] 2006.285.22:54:52.03#ibcon#*before write, iclass 35, count 0 2006.285.22:54:52.03#ibcon#enter sib2, iclass 35, count 0 2006.285.22:54:52.03#ibcon#flushed, iclass 35, count 0 2006.285.22:54:52.03#ibcon#about to write, iclass 35, count 0 2006.285.22:54:52.03#ibcon#wrote, iclass 35, count 0 2006.285.22:54:52.03#ibcon#about to read 3, iclass 35, count 0 2006.285.22:54:52.06#ibcon#read 3, iclass 35, count 0 2006.285.22:54:52.06#ibcon#about to read 4, iclass 35, count 0 2006.285.22:54:52.06#ibcon#read 4, iclass 35, count 0 2006.285.22:54:52.06#ibcon#about to read 5, iclass 35, count 0 2006.285.22:54:52.06#ibcon#read 5, iclass 35, count 0 2006.285.22:54:52.06#ibcon#about to read 6, iclass 35, count 0 2006.285.22:54:52.06#ibcon#read 6, iclass 35, count 0 2006.285.22:54:52.06#ibcon#end of sib2, iclass 35, count 0 2006.285.22:54:52.06#ibcon#*after write, iclass 35, count 0 2006.285.22:54:52.06#ibcon#*before return 0, iclass 35, count 0 2006.285.22:54:52.06#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:54:52.06#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.22:54:52.06#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.22:54:52.06#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.22:54:52.06$vck44/vblo=3,649.99 2006.285.22:54:52.06#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.22:54:52.06#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.22:54:52.06#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:52.06#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:54:52.06#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:54:52.06#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:54:52.06#ibcon#enter wrdev, iclass 37, count 0 2006.285.22:54:52.06#ibcon#first serial, iclass 37, count 0 2006.285.22:54:52.06#ibcon#enter sib2, iclass 37, count 0 2006.285.22:54:52.06#ibcon#flushed, iclass 37, count 0 2006.285.22:54:52.06#ibcon#about to write, iclass 37, count 0 2006.285.22:54:52.06#ibcon#wrote, iclass 37, count 0 2006.285.22:54:52.06#ibcon#about to read 3, iclass 37, count 0 2006.285.22:54:52.08#ibcon#read 3, iclass 37, count 0 2006.285.22:54:52.08#ibcon#about to read 4, iclass 37, count 0 2006.285.22:54:52.08#ibcon#read 4, iclass 37, count 0 2006.285.22:54:52.08#ibcon#about to read 5, iclass 37, count 0 2006.285.22:54:52.08#ibcon#read 5, iclass 37, count 0 2006.285.22:54:52.08#ibcon#about to read 6, iclass 37, count 0 2006.285.22:54:52.08#ibcon#read 6, iclass 37, count 0 2006.285.22:54:52.08#ibcon#end of sib2, iclass 37, count 0 2006.285.22:54:52.08#ibcon#*mode == 0, iclass 37, count 0 2006.285.22:54:52.08#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.22:54:52.08#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:54:52.08#ibcon#*before write, iclass 37, count 0 2006.285.22:54:52.08#ibcon#enter sib2, iclass 37, count 0 2006.285.22:54:52.08#ibcon#flushed, iclass 37, count 0 2006.285.22:54:52.08#ibcon#about to write, iclass 37, count 0 2006.285.22:54:52.08#ibcon#wrote, iclass 37, count 0 2006.285.22:54:52.08#ibcon#about to read 3, iclass 37, count 0 2006.285.22:54:52.12#ibcon#read 3, iclass 37, count 0 2006.285.22:54:52.12#ibcon#about to read 4, iclass 37, count 0 2006.285.22:54:52.12#ibcon#read 4, iclass 37, count 0 2006.285.22:54:52.12#ibcon#about to read 5, iclass 37, count 0 2006.285.22:54:52.12#ibcon#read 5, iclass 37, count 0 2006.285.22:54:52.12#ibcon#about to read 6, iclass 37, count 0 2006.285.22:54:52.12#ibcon#read 6, iclass 37, count 0 2006.285.22:54:52.12#ibcon#end of sib2, iclass 37, count 0 2006.285.22:54:52.12#ibcon#*after write, iclass 37, count 0 2006.285.22:54:52.12#ibcon#*before return 0, iclass 37, count 0 2006.285.22:54:52.12#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:54:52.12#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.22:54:52.12#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.22:54:52.12#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.22:54:52.12$vck44/vb=3,4 2006.285.22:54:52.12#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.22:54:52.12#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.22:54:52.12#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:52.12#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:54:52.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:54:52.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:54:52.18#ibcon#enter wrdev, iclass 39, count 2 2006.285.22:54:52.18#ibcon#first serial, iclass 39, count 2 2006.285.22:54:52.18#ibcon#enter sib2, iclass 39, count 2 2006.285.22:54:52.18#ibcon#flushed, iclass 39, count 2 2006.285.22:54:52.18#ibcon#about to write, iclass 39, count 2 2006.285.22:54:52.18#ibcon#wrote, iclass 39, count 2 2006.285.22:54:52.18#ibcon#about to read 3, iclass 39, count 2 2006.285.22:54:52.20#ibcon#read 3, iclass 39, count 2 2006.285.22:54:52.20#ibcon#about to read 4, iclass 39, count 2 2006.285.22:54:52.20#ibcon#read 4, iclass 39, count 2 2006.285.22:54:52.20#ibcon#about to read 5, iclass 39, count 2 2006.285.22:54:52.20#ibcon#read 5, iclass 39, count 2 2006.285.22:54:52.20#ibcon#about to read 6, iclass 39, count 2 2006.285.22:54:52.20#ibcon#read 6, iclass 39, count 2 2006.285.22:54:52.20#ibcon#end of sib2, iclass 39, count 2 2006.285.22:54:52.20#ibcon#*mode == 0, iclass 39, count 2 2006.285.22:54:52.20#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.22:54:52.20#ibcon#[27=AT03-04\r\n] 2006.285.22:54:52.20#ibcon#*before write, iclass 39, count 2 2006.285.22:54:52.20#ibcon#enter sib2, iclass 39, count 2 2006.285.22:54:52.20#ibcon#flushed, iclass 39, count 2 2006.285.22:54:52.20#ibcon#about to write, iclass 39, count 2 2006.285.22:54:52.20#ibcon#wrote, iclass 39, count 2 2006.285.22:54:52.20#ibcon#about to read 3, iclass 39, count 2 2006.285.22:54:52.23#ibcon#read 3, iclass 39, count 2 2006.285.22:54:52.23#ibcon#about to read 4, iclass 39, count 2 2006.285.22:54:52.23#ibcon#read 4, iclass 39, count 2 2006.285.22:54:52.23#ibcon#about to read 5, iclass 39, count 2 2006.285.22:54:52.23#ibcon#read 5, iclass 39, count 2 2006.285.22:54:52.23#ibcon#about to read 6, iclass 39, count 2 2006.285.22:54:52.23#ibcon#read 6, iclass 39, count 2 2006.285.22:54:52.23#ibcon#end of sib2, iclass 39, count 2 2006.285.22:54:52.23#ibcon#*after write, iclass 39, count 2 2006.285.22:54:52.23#ibcon#*before return 0, iclass 39, count 2 2006.285.22:54:52.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:54:52.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.22:54:52.23#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.22:54:52.23#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:52.23#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:54:52.35#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:54:52.35#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:54:52.35#ibcon#enter wrdev, iclass 39, count 0 2006.285.22:54:52.35#ibcon#first serial, iclass 39, count 0 2006.285.22:54:52.35#ibcon#enter sib2, iclass 39, count 0 2006.285.22:54:52.35#ibcon#flushed, iclass 39, count 0 2006.285.22:54:52.35#ibcon#about to write, iclass 39, count 0 2006.285.22:54:52.35#ibcon#wrote, iclass 39, count 0 2006.285.22:54:52.35#ibcon#about to read 3, iclass 39, count 0 2006.285.22:54:52.37#ibcon#read 3, iclass 39, count 0 2006.285.22:54:52.37#ibcon#about to read 4, iclass 39, count 0 2006.285.22:54:52.37#ibcon#read 4, iclass 39, count 0 2006.285.22:54:52.37#ibcon#about to read 5, iclass 39, count 0 2006.285.22:54:52.37#ibcon#read 5, iclass 39, count 0 2006.285.22:54:52.37#ibcon#about to read 6, iclass 39, count 0 2006.285.22:54:52.37#ibcon#read 6, iclass 39, count 0 2006.285.22:54:52.37#ibcon#end of sib2, iclass 39, count 0 2006.285.22:54:52.37#ibcon#*mode == 0, iclass 39, count 0 2006.285.22:54:52.37#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.22:54:52.37#ibcon#[27=USB\r\n] 2006.285.22:54:52.37#ibcon#*before write, iclass 39, count 0 2006.285.22:54:52.37#ibcon#enter sib2, iclass 39, count 0 2006.285.22:54:52.37#ibcon#flushed, iclass 39, count 0 2006.285.22:54:52.37#ibcon#about to write, iclass 39, count 0 2006.285.22:54:52.37#ibcon#wrote, iclass 39, count 0 2006.285.22:54:52.37#ibcon#about to read 3, iclass 39, count 0 2006.285.22:54:52.40#ibcon#read 3, iclass 39, count 0 2006.285.22:54:52.40#ibcon#about to read 4, iclass 39, count 0 2006.285.22:54:52.40#ibcon#read 4, iclass 39, count 0 2006.285.22:54:52.40#ibcon#about to read 5, iclass 39, count 0 2006.285.22:54:52.40#ibcon#read 5, iclass 39, count 0 2006.285.22:54:52.40#ibcon#about to read 6, iclass 39, count 0 2006.285.22:54:52.40#ibcon#read 6, iclass 39, count 0 2006.285.22:54:52.40#ibcon#end of sib2, iclass 39, count 0 2006.285.22:54:52.40#ibcon#*after write, iclass 39, count 0 2006.285.22:54:52.40#ibcon#*before return 0, iclass 39, count 0 2006.285.22:54:52.40#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:54:52.40#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.22:54:52.40#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.22:54:52.40#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.22:54:52.40$vck44/vblo=4,679.99 2006.285.22:54:52.40#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.22:54:52.40#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.22:54:52.40#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:52.40#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:54:52.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:54:52.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:54:52.40#ibcon#enter wrdev, iclass 3, count 0 2006.285.22:54:52.40#ibcon#first serial, iclass 3, count 0 2006.285.22:54:52.40#ibcon#enter sib2, iclass 3, count 0 2006.285.22:54:52.40#ibcon#flushed, iclass 3, count 0 2006.285.22:54:52.40#ibcon#about to write, iclass 3, count 0 2006.285.22:54:52.40#ibcon#wrote, iclass 3, count 0 2006.285.22:54:52.40#ibcon#about to read 3, iclass 3, count 0 2006.285.22:54:52.42#ibcon#read 3, iclass 3, count 0 2006.285.22:54:52.42#ibcon#about to read 4, iclass 3, count 0 2006.285.22:54:52.42#ibcon#read 4, iclass 3, count 0 2006.285.22:54:52.42#ibcon#about to read 5, iclass 3, count 0 2006.285.22:54:52.42#ibcon#read 5, iclass 3, count 0 2006.285.22:54:52.42#ibcon#about to read 6, iclass 3, count 0 2006.285.22:54:52.42#ibcon#read 6, iclass 3, count 0 2006.285.22:54:52.42#ibcon#end of sib2, iclass 3, count 0 2006.285.22:54:52.42#ibcon#*mode == 0, iclass 3, count 0 2006.285.22:54:52.42#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.22:54:52.42#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.22:54:52.42#ibcon#*before write, iclass 3, count 0 2006.285.22:54:52.42#ibcon#enter sib2, iclass 3, count 0 2006.285.22:54:52.42#ibcon#flushed, iclass 3, count 0 2006.285.22:54:52.42#ibcon#about to write, iclass 3, count 0 2006.285.22:54:52.42#ibcon#wrote, iclass 3, count 0 2006.285.22:54:52.42#ibcon#about to read 3, iclass 3, count 0 2006.285.22:54:52.46#ibcon#read 3, iclass 3, count 0 2006.285.22:54:52.46#ibcon#about to read 4, iclass 3, count 0 2006.285.22:54:52.46#ibcon#read 4, iclass 3, count 0 2006.285.22:54:52.46#ibcon#about to read 5, iclass 3, count 0 2006.285.22:54:52.46#ibcon#read 5, iclass 3, count 0 2006.285.22:54:52.46#ibcon#about to read 6, iclass 3, count 0 2006.285.22:54:52.46#ibcon#read 6, iclass 3, count 0 2006.285.22:54:52.46#ibcon#end of sib2, iclass 3, count 0 2006.285.22:54:52.46#ibcon#*after write, iclass 3, count 0 2006.285.22:54:52.46#ibcon#*before return 0, iclass 3, count 0 2006.285.22:54:52.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:54:52.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.22:54:52.46#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.22:54:52.46#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.22:54:52.46$vck44/vb=4,5 2006.285.22:54:52.46#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.22:54:52.46#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.22:54:52.46#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:52.46#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:54:52.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:54:52.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:54:52.52#ibcon#enter wrdev, iclass 5, count 2 2006.285.22:54:52.52#ibcon#first serial, iclass 5, count 2 2006.285.22:54:52.52#ibcon#enter sib2, iclass 5, count 2 2006.285.22:54:52.52#ibcon#flushed, iclass 5, count 2 2006.285.22:54:52.52#ibcon#about to write, iclass 5, count 2 2006.285.22:54:52.52#ibcon#wrote, iclass 5, count 2 2006.285.22:54:52.52#ibcon#about to read 3, iclass 5, count 2 2006.285.22:54:52.54#ibcon#read 3, iclass 5, count 2 2006.285.22:54:52.54#ibcon#about to read 4, iclass 5, count 2 2006.285.22:54:52.54#ibcon#read 4, iclass 5, count 2 2006.285.22:54:52.54#ibcon#about to read 5, iclass 5, count 2 2006.285.22:54:52.54#ibcon#read 5, iclass 5, count 2 2006.285.22:54:52.54#ibcon#about to read 6, iclass 5, count 2 2006.285.22:54:52.54#ibcon#read 6, iclass 5, count 2 2006.285.22:54:52.54#ibcon#end of sib2, iclass 5, count 2 2006.285.22:54:52.54#ibcon#*mode == 0, iclass 5, count 2 2006.285.22:54:52.54#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.22:54:52.54#ibcon#[27=AT04-05\r\n] 2006.285.22:54:52.54#ibcon#*before write, iclass 5, count 2 2006.285.22:54:52.54#ibcon#enter sib2, iclass 5, count 2 2006.285.22:54:52.54#ibcon#flushed, iclass 5, count 2 2006.285.22:54:52.54#ibcon#about to write, iclass 5, count 2 2006.285.22:54:52.54#ibcon#wrote, iclass 5, count 2 2006.285.22:54:52.54#ibcon#about to read 3, iclass 5, count 2 2006.285.22:54:52.57#ibcon#read 3, iclass 5, count 2 2006.285.22:54:52.57#ibcon#about to read 4, iclass 5, count 2 2006.285.22:54:52.57#ibcon#read 4, iclass 5, count 2 2006.285.22:54:52.57#ibcon#about to read 5, iclass 5, count 2 2006.285.22:54:52.57#ibcon#read 5, iclass 5, count 2 2006.285.22:54:52.57#ibcon#about to read 6, iclass 5, count 2 2006.285.22:54:52.57#ibcon#read 6, iclass 5, count 2 2006.285.22:54:52.57#ibcon#end of sib2, iclass 5, count 2 2006.285.22:54:52.57#ibcon#*after write, iclass 5, count 2 2006.285.22:54:52.57#ibcon#*before return 0, iclass 5, count 2 2006.285.22:54:52.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:54:52.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.22:54:52.57#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.22:54:52.57#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:52.57#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:54:52.66#abcon#<5=/04 2.5 4.9 18.15 901016.2\r\n> 2006.285.22:54:52.68#abcon#{5=INTERFACE CLEAR} 2006.285.22:54:52.69#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:54:52.69#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:54:52.69#ibcon#enter wrdev, iclass 5, count 0 2006.285.22:54:52.69#ibcon#first serial, iclass 5, count 0 2006.285.22:54:52.69#ibcon#enter sib2, iclass 5, count 0 2006.285.22:54:52.69#ibcon#flushed, iclass 5, count 0 2006.285.22:54:52.69#ibcon#about to write, iclass 5, count 0 2006.285.22:54:52.69#ibcon#wrote, iclass 5, count 0 2006.285.22:54:52.69#ibcon#about to read 3, iclass 5, count 0 2006.285.22:54:52.71#ibcon#read 3, iclass 5, count 0 2006.285.22:54:52.71#ibcon#about to read 4, iclass 5, count 0 2006.285.22:54:52.71#ibcon#read 4, iclass 5, count 0 2006.285.22:54:52.71#ibcon#about to read 5, iclass 5, count 0 2006.285.22:54:52.71#ibcon#read 5, iclass 5, count 0 2006.285.22:54:52.71#ibcon#about to read 6, iclass 5, count 0 2006.285.22:54:52.71#ibcon#read 6, iclass 5, count 0 2006.285.22:54:52.71#ibcon#end of sib2, iclass 5, count 0 2006.285.22:54:52.71#ibcon#*mode == 0, iclass 5, count 0 2006.285.22:54:52.71#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.22:54:52.71#ibcon#[27=USB\r\n] 2006.285.22:54:52.71#ibcon#*before write, iclass 5, count 0 2006.285.22:54:52.71#ibcon#enter sib2, iclass 5, count 0 2006.285.22:54:52.71#ibcon#flushed, iclass 5, count 0 2006.285.22:54:52.71#ibcon#about to write, iclass 5, count 0 2006.285.22:54:52.71#ibcon#wrote, iclass 5, count 0 2006.285.22:54:52.71#ibcon#about to read 3, iclass 5, count 0 2006.285.22:54:52.74#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:54:52.74#ibcon#read 3, iclass 5, count 0 2006.285.22:54:52.74#ibcon#about to read 4, iclass 5, count 0 2006.285.22:54:52.74#ibcon#read 4, iclass 5, count 0 2006.285.22:54:52.74#ibcon#about to read 5, iclass 5, count 0 2006.285.22:54:52.74#ibcon#read 5, iclass 5, count 0 2006.285.22:54:52.74#ibcon#about to read 6, iclass 5, count 0 2006.285.22:54:52.74#ibcon#read 6, iclass 5, count 0 2006.285.22:54:52.74#ibcon#end of sib2, iclass 5, count 0 2006.285.22:54:52.74#ibcon#*after write, iclass 5, count 0 2006.285.22:54:52.74#ibcon#*before return 0, iclass 5, count 0 2006.285.22:54:52.74#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:54:52.74#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.22:54:52.74#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.22:54:52.74#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.22:54:52.74$vck44/vblo=5,709.99 2006.285.22:54:52.74#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.22:54:52.74#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.22:54:52.74#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:52.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:54:52.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:54:52.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:54:52.74#ibcon#enter wrdev, iclass 13, count 0 2006.285.22:54:52.74#ibcon#first serial, iclass 13, count 0 2006.285.22:54:52.74#ibcon#enter sib2, iclass 13, count 0 2006.285.22:54:52.74#ibcon#flushed, iclass 13, count 0 2006.285.22:54:52.74#ibcon#about to write, iclass 13, count 0 2006.285.22:54:52.74#ibcon#wrote, iclass 13, count 0 2006.285.22:54:52.74#ibcon#about to read 3, iclass 13, count 0 2006.285.22:54:52.76#ibcon#read 3, iclass 13, count 0 2006.285.22:54:52.76#ibcon#about to read 4, iclass 13, count 0 2006.285.22:54:52.76#ibcon#read 4, iclass 13, count 0 2006.285.22:54:52.76#ibcon#about to read 5, iclass 13, count 0 2006.285.22:54:52.76#ibcon#read 5, iclass 13, count 0 2006.285.22:54:52.76#ibcon#about to read 6, iclass 13, count 0 2006.285.22:54:52.76#ibcon#read 6, iclass 13, count 0 2006.285.22:54:52.76#ibcon#end of sib2, iclass 13, count 0 2006.285.22:54:52.76#ibcon#*mode == 0, iclass 13, count 0 2006.285.22:54:52.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.22:54:52.76#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.22:54:52.76#ibcon#*before write, iclass 13, count 0 2006.285.22:54:52.76#ibcon#enter sib2, iclass 13, count 0 2006.285.22:54:52.76#ibcon#flushed, iclass 13, count 0 2006.285.22:54:52.76#ibcon#about to write, iclass 13, count 0 2006.285.22:54:52.76#ibcon#wrote, iclass 13, count 0 2006.285.22:54:52.76#ibcon#about to read 3, iclass 13, count 0 2006.285.22:54:52.80#ibcon#read 3, iclass 13, count 0 2006.285.22:54:52.80#ibcon#about to read 4, iclass 13, count 0 2006.285.22:54:52.80#ibcon#read 4, iclass 13, count 0 2006.285.22:54:52.80#ibcon#about to read 5, iclass 13, count 0 2006.285.22:54:52.80#ibcon#read 5, iclass 13, count 0 2006.285.22:54:52.80#ibcon#about to read 6, iclass 13, count 0 2006.285.22:54:52.80#ibcon#read 6, iclass 13, count 0 2006.285.22:54:52.80#ibcon#end of sib2, iclass 13, count 0 2006.285.22:54:52.80#ibcon#*after write, iclass 13, count 0 2006.285.22:54:52.80#ibcon#*before return 0, iclass 13, count 0 2006.285.22:54:52.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:54:52.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.22:54:52.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.22:54:52.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.22:54:52.80$vck44/vb=5,4 2006.285.22:54:52.80#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.22:54:52.80#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.22:54:52.80#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:52.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:54:52.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:54:52.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:54:52.86#ibcon#enter wrdev, iclass 15, count 2 2006.285.22:54:52.86#ibcon#first serial, iclass 15, count 2 2006.285.22:54:52.86#ibcon#enter sib2, iclass 15, count 2 2006.285.22:54:52.86#ibcon#flushed, iclass 15, count 2 2006.285.22:54:52.86#ibcon#about to write, iclass 15, count 2 2006.285.22:54:52.86#ibcon#wrote, iclass 15, count 2 2006.285.22:54:52.86#ibcon#about to read 3, iclass 15, count 2 2006.285.22:54:52.88#ibcon#read 3, iclass 15, count 2 2006.285.22:54:52.88#ibcon#about to read 4, iclass 15, count 2 2006.285.22:54:52.88#ibcon#read 4, iclass 15, count 2 2006.285.22:54:52.88#ibcon#about to read 5, iclass 15, count 2 2006.285.22:54:52.88#ibcon#read 5, iclass 15, count 2 2006.285.22:54:52.88#ibcon#about to read 6, iclass 15, count 2 2006.285.22:54:52.88#ibcon#read 6, iclass 15, count 2 2006.285.22:54:52.88#ibcon#end of sib2, iclass 15, count 2 2006.285.22:54:52.88#ibcon#*mode == 0, iclass 15, count 2 2006.285.22:54:52.88#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.22:54:52.88#ibcon#[27=AT05-04\r\n] 2006.285.22:54:52.88#ibcon#*before write, iclass 15, count 2 2006.285.22:54:52.88#ibcon#enter sib2, iclass 15, count 2 2006.285.22:54:52.88#ibcon#flushed, iclass 15, count 2 2006.285.22:54:52.88#ibcon#about to write, iclass 15, count 2 2006.285.22:54:52.88#ibcon#wrote, iclass 15, count 2 2006.285.22:54:52.88#ibcon#about to read 3, iclass 15, count 2 2006.285.22:54:52.91#ibcon#read 3, iclass 15, count 2 2006.285.22:54:52.91#ibcon#about to read 4, iclass 15, count 2 2006.285.22:54:52.91#ibcon#read 4, iclass 15, count 2 2006.285.22:54:52.91#ibcon#about to read 5, iclass 15, count 2 2006.285.22:54:52.91#ibcon#read 5, iclass 15, count 2 2006.285.22:54:52.91#ibcon#about to read 6, iclass 15, count 2 2006.285.22:54:52.91#ibcon#read 6, iclass 15, count 2 2006.285.22:54:52.91#ibcon#end of sib2, iclass 15, count 2 2006.285.22:54:52.91#ibcon#*after write, iclass 15, count 2 2006.285.22:54:52.91#ibcon#*before return 0, iclass 15, count 2 2006.285.22:54:52.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:54:52.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.22:54:52.91#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.22:54:52.91#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:52.91#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:54:53.03#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:54:53.03#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:54:53.03#ibcon#enter wrdev, iclass 15, count 0 2006.285.22:54:53.03#ibcon#first serial, iclass 15, count 0 2006.285.22:54:53.03#ibcon#enter sib2, iclass 15, count 0 2006.285.22:54:53.03#ibcon#flushed, iclass 15, count 0 2006.285.22:54:53.03#ibcon#about to write, iclass 15, count 0 2006.285.22:54:53.03#ibcon#wrote, iclass 15, count 0 2006.285.22:54:53.03#ibcon#about to read 3, iclass 15, count 0 2006.285.22:54:53.05#ibcon#read 3, iclass 15, count 0 2006.285.22:54:53.05#ibcon#about to read 4, iclass 15, count 0 2006.285.22:54:53.05#ibcon#read 4, iclass 15, count 0 2006.285.22:54:53.05#ibcon#about to read 5, iclass 15, count 0 2006.285.22:54:53.05#ibcon#read 5, iclass 15, count 0 2006.285.22:54:53.05#ibcon#about to read 6, iclass 15, count 0 2006.285.22:54:53.05#ibcon#read 6, iclass 15, count 0 2006.285.22:54:53.05#ibcon#end of sib2, iclass 15, count 0 2006.285.22:54:53.05#ibcon#*mode == 0, iclass 15, count 0 2006.285.22:54:53.05#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.22:54:53.05#ibcon#[27=USB\r\n] 2006.285.22:54:53.05#ibcon#*before write, iclass 15, count 0 2006.285.22:54:53.05#ibcon#enter sib2, iclass 15, count 0 2006.285.22:54:53.05#ibcon#flushed, iclass 15, count 0 2006.285.22:54:53.05#ibcon#about to write, iclass 15, count 0 2006.285.22:54:53.05#ibcon#wrote, iclass 15, count 0 2006.285.22:54:53.05#ibcon#about to read 3, iclass 15, count 0 2006.285.22:54:53.08#ibcon#read 3, iclass 15, count 0 2006.285.22:54:53.08#ibcon#about to read 4, iclass 15, count 0 2006.285.22:54:53.08#ibcon#read 4, iclass 15, count 0 2006.285.22:54:53.08#ibcon#about to read 5, iclass 15, count 0 2006.285.22:54:53.08#ibcon#read 5, iclass 15, count 0 2006.285.22:54:53.08#ibcon#about to read 6, iclass 15, count 0 2006.285.22:54:53.08#ibcon#read 6, iclass 15, count 0 2006.285.22:54:53.08#ibcon#end of sib2, iclass 15, count 0 2006.285.22:54:53.08#ibcon#*after write, iclass 15, count 0 2006.285.22:54:53.08#ibcon#*before return 0, iclass 15, count 0 2006.285.22:54:53.08#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:54:53.08#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.22:54:53.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.22:54:53.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.22:54:53.08$vck44/vblo=6,719.99 2006.285.22:54:53.08#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.22:54:53.08#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.22:54:53.08#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:53.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:54:53.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:54:53.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:54:53.08#ibcon#enter wrdev, iclass 17, count 0 2006.285.22:54:53.08#ibcon#first serial, iclass 17, count 0 2006.285.22:54:53.08#ibcon#enter sib2, iclass 17, count 0 2006.285.22:54:53.08#ibcon#flushed, iclass 17, count 0 2006.285.22:54:53.08#ibcon#about to write, iclass 17, count 0 2006.285.22:54:53.08#ibcon#wrote, iclass 17, count 0 2006.285.22:54:53.08#ibcon#about to read 3, iclass 17, count 0 2006.285.22:54:53.10#ibcon#read 3, iclass 17, count 0 2006.285.22:54:53.10#ibcon#about to read 4, iclass 17, count 0 2006.285.22:54:53.10#ibcon#read 4, iclass 17, count 0 2006.285.22:54:53.10#ibcon#about to read 5, iclass 17, count 0 2006.285.22:54:53.10#ibcon#read 5, iclass 17, count 0 2006.285.22:54:53.10#ibcon#about to read 6, iclass 17, count 0 2006.285.22:54:53.10#ibcon#read 6, iclass 17, count 0 2006.285.22:54:53.10#ibcon#end of sib2, iclass 17, count 0 2006.285.22:54:53.10#ibcon#*mode == 0, iclass 17, count 0 2006.285.22:54:53.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.22:54:53.10#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.22:54:53.10#ibcon#*before write, iclass 17, count 0 2006.285.22:54:53.10#ibcon#enter sib2, iclass 17, count 0 2006.285.22:54:53.10#ibcon#flushed, iclass 17, count 0 2006.285.22:54:53.10#ibcon#about to write, iclass 17, count 0 2006.285.22:54:53.10#ibcon#wrote, iclass 17, count 0 2006.285.22:54:53.10#ibcon#about to read 3, iclass 17, count 0 2006.285.22:54:53.14#ibcon#read 3, iclass 17, count 0 2006.285.22:54:53.14#ibcon#about to read 4, iclass 17, count 0 2006.285.22:54:53.14#ibcon#read 4, iclass 17, count 0 2006.285.22:54:53.14#ibcon#about to read 5, iclass 17, count 0 2006.285.22:54:53.14#ibcon#read 5, iclass 17, count 0 2006.285.22:54:53.14#ibcon#about to read 6, iclass 17, count 0 2006.285.22:54:53.14#ibcon#read 6, iclass 17, count 0 2006.285.22:54:53.14#ibcon#end of sib2, iclass 17, count 0 2006.285.22:54:53.14#ibcon#*after write, iclass 17, count 0 2006.285.22:54:53.14#ibcon#*before return 0, iclass 17, count 0 2006.285.22:54:53.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:54:53.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.22:54:53.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.22:54:53.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.22:54:53.14$vck44/vb=6,3 2006.285.22:54:53.14#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.22:54:53.14#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.22:54:53.14#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:53.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:54:53.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:54:53.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:54:53.20#ibcon#enter wrdev, iclass 19, count 2 2006.285.22:54:53.20#ibcon#first serial, iclass 19, count 2 2006.285.22:54:53.20#ibcon#enter sib2, iclass 19, count 2 2006.285.22:54:53.20#ibcon#flushed, iclass 19, count 2 2006.285.22:54:53.20#ibcon#about to write, iclass 19, count 2 2006.285.22:54:53.20#ibcon#wrote, iclass 19, count 2 2006.285.22:54:53.20#ibcon#about to read 3, iclass 19, count 2 2006.285.22:54:53.22#ibcon#read 3, iclass 19, count 2 2006.285.22:54:53.22#ibcon#about to read 4, iclass 19, count 2 2006.285.22:54:53.22#ibcon#read 4, iclass 19, count 2 2006.285.22:54:53.22#ibcon#about to read 5, iclass 19, count 2 2006.285.22:54:53.22#ibcon#read 5, iclass 19, count 2 2006.285.22:54:53.22#ibcon#about to read 6, iclass 19, count 2 2006.285.22:54:53.22#ibcon#read 6, iclass 19, count 2 2006.285.22:54:53.22#ibcon#end of sib2, iclass 19, count 2 2006.285.22:54:53.22#ibcon#*mode == 0, iclass 19, count 2 2006.285.22:54:53.22#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.22:54:53.22#ibcon#[27=AT06-03\r\n] 2006.285.22:54:53.22#ibcon#*before write, iclass 19, count 2 2006.285.22:54:53.22#ibcon#enter sib2, iclass 19, count 2 2006.285.22:54:53.22#ibcon#flushed, iclass 19, count 2 2006.285.22:54:53.22#ibcon#about to write, iclass 19, count 2 2006.285.22:54:53.22#ibcon#wrote, iclass 19, count 2 2006.285.22:54:53.22#ibcon#about to read 3, iclass 19, count 2 2006.285.22:54:53.25#ibcon#read 3, iclass 19, count 2 2006.285.22:54:53.25#ibcon#about to read 4, iclass 19, count 2 2006.285.22:54:53.25#ibcon#read 4, iclass 19, count 2 2006.285.22:54:53.25#ibcon#about to read 5, iclass 19, count 2 2006.285.22:54:53.25#ibcon#read 5, iclass 19, count 2 2006.285.22:54:53.25#ibcon#about to read 6, iclass 19, count 2 2006.285.22:54:53.25#ibcon#read 6, iclass 19, count 2 2006.285.22:54:53.25#ibcon#end of sib2, iclass 19, count 2 2006.285.22:54:53.25#ibcon#*after write, iclass 19, count 2 2006.285.22:54:53.25#ibcon#*before return 0, iclass 19, count 2 2006.285.22:54:53.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:54:53.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.22:54:53.25#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.22:54:53.25#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:53.25#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:54:53.37#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:54:53.37#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:54:53.37#ibcon#enter wrdev, iclass 19, count 0 2006.285.22:54:53.37#ibcon#first serial, iclass 19, count 0 2006.285.22:54:53.37#ibcon#enter sib2, iclass 19, count 0 2006.285.22:54:53.37#ibcon#flushed, iclass 19, count 0 2006.285.22:54:53.37#ibcon#about to write, iclass 19, count 0 2006.285.22:54:53.37#ibcon#wrote, iclass 19, count 0 2006.285.22:54:53.37#ibcon#about to read 3, iclass 19, count 0 2006.285.22:54:53.39#ibcon#read 3, iclass 19, count 0 2006.285.22:54:53.39#ibcon#about to read 4, iclass 19, count 0 2006.285.22:54:53.39#ibcon#read 4, iclass 19, count 0 2006.285.22:54:53.39#ibcon#about to read 5, iclass 19, count 0 2006.285.22:54:53.39#ibcon#read 5, iclass 19, count 0 2006.285.22:54:53.39#ibcon#about to read 6, iclass 19, count 0 2006.285.22:54:53.39#ibcon#read 6, iclass 19, count 0 2006.285.22:54:53.39#ibcon#end of sib2, iclass 19, count 0 2006.285.22:54:53.39#ibcon#*mode == 0, iclass 19, count 0 2006.285.22:54:53.39#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.22:54:53.39#ibcon#[27=USB\r\n] 2006.285.22:54:53.39#ibcon#*before write, iclass 19, count 0 2006.285.22:54:53.39#ibcon#enter sib2, iclass 19, count 0 2006.285.22:54:53.39#ibcon#flushed, iclass 19, count 0 2006.285.22:54:53.39#ibcon#about to write, iclass 19, count 0 2006.285.22:54:53.39#ibcon#wrote, iclass 19, count 0 2006.285.22:54:53.39#ibcon#about to read 3, iclass 19, count 0 2006.285.22:54:53.42#ibcon#read 3, iclass 19, count 0 2006.285.22:54:53.42#ibcon#about to read 4, iclass 19, count 0 2006.285.22:54:53.42#ibcon#read 4, iclass 19, count 0 2006.285.22:54:53.42#ibcon#about to read 5, iclass 19, count 0 2006.285.22:54:53.42#ibcon#read 5, iclass 19, count 0 2006.285.22:54:53.42#ibcon#about to read 6, iclass 19, count 0 2006.285.22:54:53.42#ibcon#read 6, iclass 19, count 0 2006.285.22:54:53.42#ibcon#end of sib2, iclass 19, count 0 2006.285.22:54:53.42#ibcon#*after write, iclass 19, count 0 2006.285.22:54:53.42#ibcon#*before return 0, iclass 19, count 0 2006.285.22:54:53.42#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:54:53.42#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.22:54:53.42#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.22:54:53.42#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.22:54:53.42$vck44/vblo=7,734.99 2006.285.22:54:53.42#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.22:54:53.42#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.22:54:53.42#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:53.42#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:54:53.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:54:53.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:54:53.42#ibcon#enter wrdev, iclass 21, count 0 2006.285.22:54:53.42#ibcon#first serial, iclass 21, count 0 2006.285.22:54:53.42#ibcon#enter sib2, iclass 21, count 0 2006.285.22:54:53.42#ibcon#flushed, iclass 21, count 0 2006.285.22:54:53.42#ibcon#about to write, iclass 21, count 0 2006.285.22:54:53.42#ibcon#wrote, iclass 21, count 0 2006.285.22:54:53.42#ibcon#about to read 3, iclass 21, count 0 2006.285.22:54:53.44#ibcon#read 3, iclass 21, count 0 2006.285.22:54:53.44#ibcon#about to read 4, iclass 21, count 0 2006.285.22:54:53.44#ibcon#read 4, iclass 21, count 0 2006.285.22:54:53.44#ibcon#about to read 5, iclass 21, count 0 2006.285.22:54:53.44#ibcon#read 5, iclass 21, count 0 2006.285.22:54:53.44#ibcon#about to read 6, iclass 21, count 0 2006.285.22:54:53.44#ibcon#read 6, iclass 21, count 0 2006.285.22:54:53.44#ibcon#end of sib2, iclass 21, count 0 2006.285.22:54:53.44#ibcon#*mode == 0, iclass 21, count 0 2006.285.22:54:53.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.22:54:53.44#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.22:54:53.44#ibcon#*before write, iclass 21, count 0 2006.285.22:54:53.44#ibcon#enter sib2, iclass 21, count 0 2006.285.22:54:53.44#ibcon#flushed, iclass 21, count 0 2006.285.22:54:53.44#ibcon#about to write, iclass 21, count 0 2006.285.22:54:53.44#ibcon#wrote, iclass 21, count 0 2006.285.22:54:53.44#ibcon#about to read 3, iclass 21, count 0 2006.285.22:54:53.48#ibcon#read 3, iclass 21, count 0 2006.285.22:54:53.48#ibcon#about to read 4, iclass 21, count 0 2006.285.22:54:53.48#ibcon#read 4, iclass 21, count 0 2006.285.22:54:53.48#ibcon#about to read 5, iclass 21, count 0 2006.285.22:54:53.48#ibcon#read 5, iclass 21, count 0 2006.285.22:54:53.48#ibcon#about to read 6, iclass 21, count 0 2006.285.22:54:53.48#ibcon#read 6, iclass 21, count 0 2006.285.22:54:53.48#ibcon#end of sib2, iclass 21, count 0 2006.285.22:54:53.48#ibcon#*after write, iclass 21, count 0 2006.285.22:54:53.48#ibcon#*before return 0, iclass 21, count 0 2006.285.22:54:53.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:54:53.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.22:54:53.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.22:54:53.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.22:54:53.48$vck44/vb=7,4 2006.285.22:54:53.48#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.22:54:53.48#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.22:54:53.48#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:53.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:54:53.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:54:53.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:54:53.54#ibcon#enter wrdev, iclass 23, count 2 2006.285.22:54:53.54#ibcon#first serial, iclass 23, count 2 2006.285.22:54:53.54#ibcon#enter sib2, iclass 23, count 2 2006.285.22:54:53.54#ibcon#flushed, iclass 23, count 2 2006.285.22:54:53.54#ibcon#about to write, iclass 23, count 2 2006.285.22:54:53.54#ibcon#wrote, iclass 23, count 2 2006.285.22:54:53.54#ibcon#about to read 3, iclass 23, count 2 2006.285.22:54:53.56#ibcon#read 3, iclass 23, count 2 2006.285.22:54:53.56#ibcon#about to read 4, iclass 23, count 2 2006.285.22:54:53.56#ibcon#read 4, iclass 23, count 2 2006.285.22:54:53.56#ibcon#about to read 5, iclass 23, count 2 2006.285.22:54:53.56#ibcon#read 5, iclass 23, count 2 2006.285.22:54:53.56#ibcon#about to read 6, iclass 23, count 2 2006.285.22:54:53.56#ibcon#read 6, iclass 23, count 2 2006.285.22:54:53.56#ibcon#end of sib2, iclass 23, count 2 2006.285.22:54:53.56#ibcon#*mode == 0, iclass 23, count 2 2006.285.22:54:53.56#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.22:54:53.56#ibcon#[27=AT07-04\r\n] 2006.285.22:54:53.56#ibcon#*before write, iclass 23, count 2 2006.285.22:54:53.56#ibcon#enter sib2, iclass 23, count 2 2006.285.22:54:53.56#ibcon#flushed, iclass 23, count 2 2006.285.22:54:53.56#ibcon#about to write, iclass 23, count 2 2006.285.22:54:53.56#ibcon#wrote, iclass 23, count 2 2006.285.22:54:53.56#ibcon#about to read 3, iclass 23, count 2 2006.285.22:54:53.59#ibcon#read 3, iclass 23, count 2 2006.285.22:54:53.59#ibcon#about to read 4, iclass 23, count 2 2006.285.22:54:53.59#ibcon#read 4, iclass 23, count 2 2006.285.22:54:53.59#ibcon#about to read 5, iclass 23, count 2 2006.285.22:54:53.59#ibcon#read 5, iclass 23, count 2 2006.285.22:54:53.59#ibcon#about to read 6, iclass 23, count 2 2006.285.22:54:53.59#ibcon#read 6, iclass 23, count 2 2006.285.22:54:53.59#ibcon#end of sib2, iclass 23, count 2 2006.285.22:54:53.59#ibcon#*after write, iclass 23, count 2 2006.285.22:54:53.59#ibcon#*before return 0, iclass 23, count 2 2006.285.22:54:53.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:54:53.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.22:54:53.59#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.22:54:53.59#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:53.59#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:54:53.71#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:54:53.71#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:54:53.71#ibcon#enter wrdev, iclass 23, count 0 2006.285.22:54:53.71#ibcon#first serial, iclass 23, count 0 2006.285.22:54:53.71#ibcon#enter sib2, iclass 23, count 0 2006.285.22:54:53.71#ibcon#flushed, iclass 23, count 0 2006.285.22:54:53.71#ibcon#about to write, iclass 23, count 0 2006.285.22:54:53.71#ibcon#wrote, iclass 23, count 0 2006.285.22:54:53.71#ibcon#about to read 3, iclass 23, count 0 2006.285.22:54:53.73#ibcon#read 3, iclass 23, count 0 2006.285.22:54:53.73#ibcon#about to read 4, iclass 23, count 0 2006.285.22:54:53.73#ibcon#read 4, iclass 23, count 0 2006.285.22:54:53.73#ibcon#about to read 5, iclass 23, count 0 2006.285.22:54:53.73#ibcon#read 5, iclass 23, count 0 2006.285.22:54:53.73#ibcon#about to read 6, iclass 23, count 0 2006.285.22:54:53.73#ibcon#read 6, iclass 23, count 0 2006.285.22:54:53.73#ibcon#end of sib2, iclass 23, count 0 2006.285.22:54:53.73#ibcon#*mode == 0, iclass 23, count 0 2006.285.22:54:53.73#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.22:54:53.73#ibcon#[27=USB\r\n] 2006.285.22:54:53.73#ibcon#*before write, iclass 23, count 0 2006.285.22:54:53.73#ibcon#enter sib2, iclass 23, count 0 2006.285.22:54:53.73#ibcon#flushed, iclass 23, count 0 2006.285.22:54:53.73#ibcon#about to write, iclass 23, count 0 2006.285.22:54:53.73#ibcon#wrote, iclass 23, count 0 2006.285.22:54:53.73#ibcon#about to read 3, iclass 23, count 0 2006.285.22:54:53.76#ibcon#read 3, iclass 23, count 0 2006.285.22:54:53.76#ibcon#about to read 4, iclass 23, count 0 2006.285.22:54:53.76#ibcon#read 4, iclass 23, count 0 2006.285.22:54:53.76#ibcon#about to read 5, iclass 23, count 0 2006.285.22:54:53.76#ibcon#read 5, iclass 23, count 0 2006.285.22:54:53.76#ibcon#about to read 6, iclass 23, count 0 2006.285.22:54:53.76#ibcon#read 6, iclass 23, count 0 2006.285.22:54:53.76#ibcon#end of sib2, iclass 23, count 0 2006.285.22:54:53.76#ibcon#*after write, iclass 23, count 0 2006.285.22:54:53.76#ibcon#*before return 0, iclass 23, count 0 2006.285.22:54:53.76#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:54:53.76#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.22:54:53.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.22:54:53.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.22:54:53.76$vck44/vblo=8,744.99 2006.285.22:54:53.76#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.22:54:53.76#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.22:54:53.76#ibcon#ireg 17 cls_cnt 0 2006.285.22:54:53.76#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:54:53.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:54:53.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:54:53.76#ibcon#enter wrdev, iclass 25, count 0 2006.285.22:54:53.76#ibcon#first serial, iclass 25, count 0 2006.285.22:54:53.76#ibcon#enter sib2, iclass 25, count 0 2006.285.22:54:53.76#ibcon#flushed, iclass 25, count 0 2006.285.22:54:53.76#ibcon#about to write, iclass 25, count 0 2006.285.22:54:53.76#ibcon#wrote, iclass 25, count 0 2006.285.22:54:53.76#ibcon#about to read 3, iclass 25, count 0 2006.285.22:54:53.78#ibcon#read 3, iclass 25, count 0 2006.285.22:54:53.78#ibcon#about to read 4, iclass 25, count 0 2006.285.22:54:53.78#ibcon#read 4, iclass 25, count 0 2006.285.22:54:53.78#ibcon#about to read 5, iclass 25, count 0 2006.285.22:54:53.78#ibcon#read 5, iclass 25, count 0 2006.285.22:54:53.78#ibcon#about to read 6, iclass 25, count 0 2006.285.22:54:53.78#ibcon#read 6, iclass 25, count 0 2006.285.22:54:53.78#ibcon#end of sib2, iclass 25, count 0 2006.285.22:54:53.78#ibcon#*mode == 0, iclass 25, count 0 2006.285.22:54:53.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.22:54:53.78#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.22:54:53.78#ibcon#*before write, iclass 25, count 0 2006.285.22:54:53.78#ibcon#enter sib2, iclass 25, count 0 2006.285.22:54:53.78#ibcon#flushed, iclass 25, count 0 2006.285.22:54:53.78#ibcon#about to write, iclass 25, count 0 2006.285.22:54:53.78#ibcon#wrote, iclass 25, count 0 2006.285.22:54:53.78#ibcon#about to read 3, iclass 25, count 0 2006.285.22:54:53.82#ibcon#read 3, iclass 25, count 0 2006.285.22:54:53.82#ibcon#about to read 4, iclass 25, count 0 2006.285.22:54:53.82#ibcon#read 4, iclass 25, count 0 2006.285.22:54:53.82#ibcon#about to read 5, iclass 25, count 0 2006.285.22:54:53.82#ibcon#read 5, iclass 25, count 0 2006.285.22:54:53.82#ibcon#about to read 6, iclass 25, count 0 2006.285.22:54:53.82#ibcon#read 6, iclass 25, count 0 2006.285.22:54:53.82#ibcon#end of sib2, iclass 25, count 0 2006.285.22:54:53.82#ibcon#*after write, iclass 25, count 0 2006.285.22:54:53.82#ibcon#*before return 0, iclass 25, count 0 2006.285.22:54:53.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:54:53.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.22:54:53.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.22:54:53.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.22:54:53.82$vck44/vb=8,4 2006.285.22:54:53.82#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.22:54:53.82#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.22:54:53.82#ibcon#ireg 11 cls_cnt 2 2006.285.22:54:53.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:54:53.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:54:53.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:54:53.88#ibcon#enter wrdev, iclass 27, count 2 2006.285.22:54:53.88#ibcon#first serial, iclass 27, count 2 2006.285.22:54:53.88#ibcon#enter sib2, iclass 27, count 2 2006.285.22:54:53.88#ibcon#flushed, iclass 27, count 2 2006.285.22:54:53.88#ibcon#about to write, iclass 27, count 2 2006.285.22:54:53.88#ibcon#wrote, iclass 27, count 2 2006.285.22:54:53.88#ibcon#about to read 3, iclass 27, count 2 2006.285.22:54:53.90#ibcon#read 3, iclass 27, count 2 2006.285.22:54:53.90#ibcon#about to read 4, iclass 27, count 2 2006.285.22:54:53.90#ibcon#read 4, iclass 27, count 2 2006.285.22:54:53.90#ibcon#about to read 5, iclass 27, count 2 2006.285.22:54:53.90#ibcon#read 5, iclass 27, count 2 2006.285.22:54:53.90#ibcon#about to read 6, iclass 27, count 2 2006.285.22:54:53.90#ibcon#read 6, iclass 27, count 2 2006.285.22:54:53.90#ibcon#end of sib2, iclass 27, count 2 2006.285.22:54:53.90#ibcon#*mode == 0, iclass 27, count 2 2006.285.22:54:53.90#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.22:54:53.90#ibcon#[27=AT08-04\r\n] 2006.285.22:54:53.90#ibcon#*before write, iclass 27, count 2 2006.285.22:54:53.90#ibcon#enter sib2, iclass 27, count 2 2006.285.22:54:53.90#ibcon#flushed, iclass 27, count 2 2006.285.22:54:53.90#ibcon#about to write, iclass 27, count 2 2006.285.22:54:53.90#ibcon#wrote, iclass 27, count 2 2006.285.22:54:53.90#ibcon#about to read 3, iclass 27, count 2 2006.285.22:54:53.93#ibcon#read 3, iclass 27, count 2 2006.285.22:54:53.93#ibcon#about to read 4, iclass 27, count 2 2006.285.22:54:53.93#ibcon#read 4, iclass 27, count 2 2006.285.22:54:53.93#ibcon#about to read 5, iclass 27, count 2 2006.285.22:54:53.93#ibcon#read 5, iclass 27, count 2 2006.285.22:54:53.93#ibcon#about to read 6, iclass 27, count 2 2006.285.22:54:53.93#ibcon#read 6, iclass 27, count 2 2006.285.22:54:53.93#ibcon#end of sib2, iclass 27, count 2 2006.285.22:54:53.93#ibcon#*after write, iclass 27, count 2 2006.285.22:54:53.93#ibcon#*before return 0, iclass 27, count 2 2006.285.22:54:53.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:54:53.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:54:53.93#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.22:54:53.93#ibcon#ireg 7 cls_cnt 0 2006.285.22:54:53.93#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:54:54.05#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:54:54.05#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:54:54.05#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:54:54.05#ibcon#first serial, iclass 27, count 0 2006.285.22:54:54.05#ibcon#enter sib2, iclass 27, count 0 2006.285.22:54:54.05#ibcon#flushed, iclass 27, count 0 2006.285.22:54:54.05#ibcon#about to write, iclass 27, count 0 2006.285.22:54:54.05#ibcon#wrote, iclass 27, count 0 2006.285.22:54:54.05#ibcon#about to read 3, iclass 27, count 0 2006.285.22:54:54.07#ibcon#read 3, iclass 27, count 0 2006.285.22:54:54.07#ibcon#about to read 4, iclass 27, count 0 2006.285.22:54:54.07#ibcon#read 4, iclass 27, count 0 2006.285.22:54:54.07#ibcon#about to read 5, iclass 27, count 0 2006.285.22:54:54.07#ibcon#read 5, iclass 27, count 0 2006.285.22:54:54.07#ibcon#about to read 6, iclass 27, count 0 2006.285.22:54:54.07#ibcon#read 6, iclass 27, count 0 2006.285.22:54:54.07#ibcon#end of sib2, iclass 27, count 0 2006.285.22:54:54.07#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:54:54.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:54:54.07#ibcon#[27=USB\r\n] 2006.285.22:54:54.07#ibcon#*before write, iclass 27, count 0 2006.285.22:54:54.07#ibcon#enter sib2, iclass 27, count 0 2006.285.22:54:54.07#ibcon#flushed, iclass 27, count 0 2006.285.22:54:54.07#ibcon#about to write, iclass 27, count 0 2006.285.22:54:54.07#ibcon#wrote, iclass 27, count 0 2006.285.22:54:54.07#ibcon#about to read 3, iclass 27, count 0 2006.285.22:54:54.10#ibcon#read 3, iclass 27, count 0 2006.285.22:54:54.10#ibcon#about to read 4, iclass 27, count 0 2006.285.22:54:54.10#ibcon#read 4, iclass 27, count 0 2006.285.22:54:54.10#ibcon#about to read 5, iclass 27, count 0 2006.285.22:54:54.10#ibcon#read 5, iclass 27, count 0 2006.285.22:54:54.10#ibcon#about to read 6, iclass 27, count 0 2006.285.22:54:54.10#ibcon#read 6, iclass 27, count 0 2006.285.22:54:54.10#ibcon#end of sib2, iclass 27, count 0 2006.285.22:54:54.10#ibcon#*after write, iclass 27, count 0 2006.285.22:54:54.10#ibcon#*before return 0, iclass 27, count 0 2006.285.22:54:54.10#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:54:54.10#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:54:54.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:54:54.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:54:54.10$vck44/vabw=wide 2006.285.22:54:54.10#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.22:54:54.10#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.22:54:54.10#ibcon#ireg 8 cls_cnt 0 2006.285.22:54:54.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:54:54.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:54:54.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:54:54.10#ibcon#enter wrdev, iclass 29, count 0 2006.285.22:54:54.10#ibcon#first serial, iclass 29, count 0 2006.285.22:54:54.10#ibcon#enter sib2, iclass 29, count 0 2006.285.22:54:54.10#ibcon#flushed, iclass 29, count 0 2006.285.22:54:54.10#ibcon#about to write, iclass 29, count 0 2006.285.22:54:54.10#ibcon#wrote, iclass 29, count 0 2006.285.22:54:54.10#ibcon#about to read 3, iclass 29, count 0 2006.285.22:54:54.12#ibcon#read 3, iclass 29, count 0 2006.285.22:54:54.12#ibcon#about to read 4, iclass 29, count 0 2006.285.22:54:54.12#ibcon#read 4, iclass 29, count 0 2006.285.22:54:54.12#ibcon#about to read 5, iclass 29, count 0 2006.285.22:54:54.12#ibcon#read 5, iclass 29, count 0 2006.285.22:54:54.12#ibcon#about to read 6, iclass 29, count 0 2006.285.22:54:54.12#ibcon#read 6, iclass 29, count 0 2006.285.22:54:54.12#ibcon#end of sib2, iclass 29, count 0 2006.285.22:54:54.12#ibcon#*mode == 0, iclass 29, count 0 2006.285.22:54:54.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.22:54:54.12#ibcon#[25=BW32\r\n] 2006.285.22:54:54.12#ibcon#*before write, iclass 29, count 0 2006.285.22:54:54.12#ibcon#enter sib2, iclass 29, count 0 2006.285.22:54:54.12#ibcon#flushed, iclass 29, count 0 2006.285.22:54:54.12#ibcon#about to write, iclass 29, count 0 2006.285.22:54:54.12#ibcon#wrote, iclass 29, count 0 2006.285.22:54:54.12#ibcon#about to read 3, iclass 29, count 0 2006.285.22:54:54.15#ibcon#read 3, iclass 29, count 0 2006.285.22:54:54.15#ibcon#about to read 4, iclass 29, count 0 2006.285.22:54:54.15#ibcon#read 4, iclass 29, count 0 2006.285.22:54:54.15#ibcon#about to read 5, iclass 29, count 0 2006.285.22:54:54.15#ibcon#read 5, iclass 29, count 0 2006.285.22:54:54.15#ibcon#about to read 6, iclass 29, count 0 2006.285.22:54:54.15#ibcon#read 6, iclass 29, count 0 2006.285.22:54:54.15#ibcon#end of sib2, iclass 29, count 0 2006.285.22:54:54.15#ibcon#*after write, iclass 29, count 0 2006.285.22:54:54.15#ibcon#*before return 0, iclass 29, count 0 2006.285.22:54:54.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:54:54.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.22:54:54.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.22:54:54.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.22:54:54.15$vck44/vbbw=wide 2006.285.22:54:54.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.22:54:54.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.22:54:54.15#ibcon#ireg 8 cls_cnt 0 2006.285.22:54:54.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:54:54.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:54:54.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:54:54.22#ibcon#enter wrdev, iclass 31, count 0 2006.285.22:54:54.22#ibcon#first serial, iclass 31, count 0 2006.285.22:54:54.22#ibcon#enter sib2, iclass 31, count 0 2006.285.22:54:54.22#ibcon#flushed, iclass 31, count 0 2006.285.22:54:54.22#ibcon#about to write, iclass 31, count 0 2006.285.22:54:54.22#ibcon#wrote, iclass 31, count 0 2006.285.22:54:54.22#ibcon#about to read 3, iclass 31, count 0 2006.285.22:54:54.24#ibcon#read 3, iclass 31, count 0 2006.285.22:54:54.24#ibcon#about to read 4, iclass 31, count 0 2006.285.22:54:54.24#ibcon#read 4, iclass 31, count 0 2006.285.22:54:54.24#ibcon#about to read 5, iclass 31, count 0 2006.285.22:54:54.24#ibcon#read 5, iclass 31, count 0 2006.285.22:54:54.24#ibcon#about to read 6, iclass 31, count 0 2006.285.22:54:54.24#ibcon#read 6, iclass 31, count 0 2006.285.22:54:54.24#ibcon#end of sib2, iclass 31, count 0 2006.285.22:54:54.24#ibcon#*mode == 0, iclass 31, count 0 2006.285.22:54:54.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.22:54:54.24#ibcon#[27=BW32\r\n] 2006.285.22:54:54.24#ibcon#*before write, iclass 31, count 0 2006.285.22:54:54.24#ibcon#enter sib2, iclass 31, count 0 2006.285.22:54:54.24#ibcon#flushed, iclass 31, count 0 2006.285.22:54:54.24#ibcon#about to write, iclass 31, count 0 2006.285.22:54:54.24#ibcon#wrote, iclass 31, count 0 2006.285.22:54:54.24#ibcon#about to read 3, iclass 31, count 0 2006.285.22:54:54.27#ibcon#read 3, iclass 31, count 0 2006.285.22:54:54.27#ibcon#about to read 4, iclass 31, count 0 2006.285.22:54:54.27#ibcon#read 4, iclass 31, count 0 2006.285.22:54:54.27#ibcon#about to read 5, iclass 31, count 0 2006.285.22:54:54.27#ibcon#read 5, iclass 31, count 0 2006.285.22:54:54.27#ibcon#about to read 6, iclass 31, count 0 2006.285.22:54:54.27#ibcon#read 6, iclass 31, count 0 2006.285.22:54:54.27#ibcon#end of sib2, iclass 31, count 0 2006.285.22:54:54.27#ibcon#*after write, iclass 31, count 0 2006.285.22:54:54.27#ibcon#*before return 0, iclass 31, count 0 2006.285.22:54:54.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:54:54.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.22:54:54.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.22:54:54.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.22:54:54.27$setupk4/ifdk4 2006.285.22:54:54.27$ifdk4/lo= 2006.285.22:54:54.27$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.22:54:54.27$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.22:54:54.27$ifdk4/patch= 2006.285.22:54:54.27$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.22:54:54.27$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.22:54:54.27$setupk4/!*+20s 2006.285.22:55:02.83#abcon#<5=/04 2.6 4.8 18.16 901016.2\r\n> 2006.285.22:55:02.85#abcon#{5=INTERFACE CLEAR} 2006.285.22:55:02.91#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:55:06.14#trakl#Source acquired 2006.285.22:55:07.14#flagr#flagr/antenna,acquired 2006.285.22:55:08.78$setupk4/"tpicd 2006.285.22:55:08.78$setupk4/echo=off 2006.285.22:55:08.78$setupk4/xlog=off 2006.285.22:55:08.78:!2006.285.22:58:35 2006.285.22:58:35.00:preob 2006.285.22:58:35.14/onsource/TRACKING 2006.285.22:58:35.14:!2006.285.22:58:45 2006.285.22:58:45.00:"tape 2006.285.22:58:45.00:"st=record 2006.285.22:58:45.00:data_valid=on 2006.285.22:58:45.00:midob 2006.285.22:58:46.13/onsource/TRACKING 2006.285.22:58:46.13/wx/18.36,1016.3,89 2006.285.22:58:46.31/cable/+6.5117E-03 2006.285.22:58:47.40/va/01,07,usb,yes,32,35 2006.285.22:58:47.40/va/02,06,usb,yes,33,33 2006.285.22:58:47.40/va/03,07,usb,yes,32,34 2006.285.22:58:47.40/va/04,06,usb,yes,34,35 2006.285.22:58:47.40/va/05,03,usb,yes,33,34 2006.285.22:58:47.40/va/06,04,usb,yes,30,29 2006.285.22:58:47.40/va/07,04,usb,yes,30,31 2006.285.22:58:47.40/va/08,03,usb,yes,31,38 2006.285.22:58:47.63/valo/01,524.99,yes,locked 2006.285.22:58:47.63/valo/02,534.99,yes,locked 2006.285.22:58:47.63/valo/03,564.99,yes,locked 2006.285.22:58:47.63/valo/04,624.99,yes,locked 2006.285.22:58:47.63/valo/05,734.99,yes,locked 2006.285.22:58:47.63/valo/06,814.99,yes,locked 2006.285.22:58:47.63/valo/07,864.99,yes,locked 2006.285.22:58:47.63/valo/08,884.99,yes,locked 2006.285.22:58:48.72/vb/01,04,usb,yes,30,28 2006.285.22:58:48.72/vb/02,05,usb,yes,29,29 2006.285.22:58:48.72/vb/03,04,usb,yes,30,33 2006.285.22:58:48.72/vb/04,05,usb,yes,30,29 2006.285.22:58:48.72/vb/05,04,usb,yes,26,29 2006.285.22:58:48.72/vb/06,03,usb,yes,38,33 2006.285.22:58:48.72/vb/07,04,usb,yes,30,30 2006.285.22:58:48.72/vb/08,04,usb,yes,28,31 2006.285.22:58:48.95/vblo/01,629.99,yes,locked 2006.285.22:58:48.95/vblo/02,634.99,yes,locked 2006.285.22:58:48.95/vblo/03,649.99,yes,locked 2006.285.22:58:48.95/vblo/04,679.99,yes,locked 2006.285.22:58:48.95/vblo/05,709.99,yes,locked 2006.285.22:58:48.95/vblo/06,719.99,yes,locked 2006.285.22:58:48.95/vblo/07,734.99,yes,locked 2006.285.22:58:48.95/vblo/08,744.99,yes,locked 2006.285.22:58:49.10/vabw/8 2006.285.22:58:49.25/vbbw/8 2006.285.22:58:49.34/xfe/off,on,12.0 2006.285.22:58:49.72/ifatt/23,28,28,28 2006.285.22:58:50.07/fmout-gps/S +2.65E-07 2006.285.22:58:50.09:!2006.285.22:59:45 2006.285.22:59:45.01:data_valid=off 2006.285.22:59:45.01:"et 2006.285.22:59:45.01:!+3s 2006.285.22:59:48.02:"tape 2006.285.22:59:48.02:postob 2006.285.22:59:48.22/cable/+6.5097E-03 2006.285.22:59:48.22/wx/18.41,1016.3,89 2006.285.22:59:49.08/fmout-gps/S +2.66E-07 2006.285.22:59:49.08:scan_name=285-2301,jd0610,110 2006.285.22:59:49.08:source=0528+134,053056.42,133155.1,2000.0,cw 2006.285.22:59:49.13#flagr#flagr/antenna,new-source 2006.285.22:59:50.13:checkk5 2006.285.22:59:50.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.22:59:50.90/chk_autoobs//k5ts2/ autoobs is running! 2006.285.22:59:51.25/chk_autoobs//k5ts3/ autoobs is running! 2006.285.22:59:51.63/chk_autoobs//k5ts4/ autoobs is running! 2006.285.22:59:51.97/chk_obsdata//k5ts1/T2852258??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:59:52.35/chk_obsdata//k5ts2/T2852258??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:59:52.73/chk_obsdata//k5ts3/T2852258??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:59:53.11/chk_obsdata//k5ts4/T2852258??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.285.22:59:53.84/k5log//k5ts1_log_newline 2006.285.22:59:54.82/k5log//k5ts2_log_newline 2006.285.22:59:55.50/k5log//k5ts3_log_newline 2006.285.22:59:56.50/k5log//k5ts4_log_newline 2006.285.22:59:56.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.22:59:56.52:setupk4=1 2006.285.22:59:56.52$setupk4/echo=on 2006.285.22:59:56.52$setupk4/pcalon 2006.285.22:59:56.52$pcalon/"no phase cal control is implemented here 2006.285.22:59:56.52$setupk4/"tpicd=stop 2006.285.22:59:56.52$setupk4/"rec=synch_on 2006.285.22:59:56.52$setupk4/"rec_mode=128 2006.285.22:59:56.52$setupk4/!* 2006.285.22:59:56.52$setupk4/recpk4 2006.285.22:59:56.52$recpk4/recpatch= 2006.285.22:59:56.52$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.22:59:56.52$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.22:59:56.52$setupk4/vck44 2006.285.22:59:56.52$vck44/valo=1,524.99 2006.285.22:59:56.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.22:59:56.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.22:59:56.53#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:56.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:59:56.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:59:56.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:59:56.53#ibcon#enter wrdev, iclass 6, count 0 2006.285.22:59:56.53#ibcon#first serial, iclass 6, count 0 2006.285.22:59:56.53#ibcon#enter sib2, iclass 6, count 0 2006.285.22:59:56.53#ibcon#flushed, iclass 6, count 0 2006.285.22:59:56.53#ibcon#about to write, iclass 6, count 0 2006.285.22:59:56.53#ibcon#wrote, iclass 6, count 0 2006.285.22:59:56.53#ibcon#about to read 3, iclass 6, count 0 2006.285.22:59:56.55#ibcon#read 3, iclass 6, count 0 2006.285.22:59:56.55#ibcon#about to read 4, iclass 6, count 0 2006.285.22:59:56.55#ibcon#read 4, iclass 6, count 0 2006.285.22:59:56.55#ibcon#about to read 5, iclass 6, count 0 2006.285.22:59:56.55#ibcon#read 5, iclass 6, count 0 2006.285.22:59:56.55#ibcon#about to read 6, iclass 6, count 0 2006.285.22:59:56.55#ibcon#read 6, iclass 6, count 0 2006.285.22:59:56.55#ibcon#end of sib2, iclass 6, count 0 2006.285.22:59:56.55#ibcon#*mode == 0, iclass 6, count 0 2006.285.22:59:56.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.22:59:56.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.22:59:56.55#ibcon#*before write, iclass 6, count 0 2006.285.22:59:56.55#ibcon#enter sib2, iclass 6, count 0 2006.285.22:59:56.55#ibcon#flushed, iclass 6, count 0 2006.285.22:59:56.55#ibcon#about to write, iclass 6, count 0 2006.285.22:59:56.55#ibcon#wrote, iclass 6, count 0 2006.285.22:59:56.55#ibcon#about to read 3, iclass 6, count 0 2006.285.22:59:56.60#ibcon#read 3, iclass 6, count 0 2006.285.22:59:56.60#ibcon#about to read 4, iclass 6, count 0 2006.285.22:59:56.60#ibcon#read 4, iclass 6, count 0 2006.285.22:59:56.60#ibcon#about to read 5, iclass 6, count 0 2006.285.22:59:56.60#ibcon#read 5, iclass 6, count 0 2006.285.22:59:56.60#ibcon#about to read 6, iclass 6, count 0 2006.285.22:59:56.60#ibcon#read 6, iclass 6, count 0 2006.285.22:59:56.60#ibcon#end of sib2, iclass 6, count 0 2006.285.22:59:56.60#ibcon#*after write, iclass 6, count 0 2006.285.22:59:56.60#ibcon#*before return 0, iclass 6, count 0 2006.285.22:59:56.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:59:56.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:59:56.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.22:59:56.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.22:59:56.60$vck44/va=1,7 2006.285.22:59:56.60#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.22:59:56.60#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.22:59:56.60#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:56.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:59:56.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:59:56.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:59:56.60#ibcon#enter wrdev, iclass 10, count 2 2006.285.22:59:56.60#ibcon#first serial, iclass 10, count 2 2006.285.22:59:56.60#ibcon#enter sib2, iclass 10, count 2 2006.285.22:59:56.60#ibcon#flushed, iclass 10, count 2 2006.285.22:59:56.60#ibcon#about to write, iclass 10, count 2 2006.285.22:59:56.60#ibcon#wrote, iclass 10, count 2 2006.285.22:59:56.60#ibcon#about to read 3, iclass 10, count 2 2006.285.22:59:56.62#ibcon#read 3, iclass 10, count 2 2006.285.22:59:56.62#ibcon#about to read 4, iclass 10, count 2 2006.285.22:59:56.62#ibcon#read 4, iclass 10, count 2 2006.285.22:59:56.62#ibcon#about to read 5, iclass 10, count 2 2006.285.22:59:56.62#ibcon#read 5, iclass 10, count 2 2006.285.22:59:56.62#ibcon#about to read 6, iclass 10, count 2 2006.285.22:59:56.62#ibcon#read 6, iclass 10, count 2 2006.285.22:59:56.62#ibcon#end of sib2, iclass 10, count 2 2006.285.22:59:56.62#ibcon#*mode == 0, iclass 10, count 2 2006.285.22:59:56.62#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.22:59:56.62#ibcon#[25=AT01-07\r\n] 2006.285.22:59:56.62#ibcon#*before write, iclass 10, count 2 2006.285.22:59:56.62#ibcon#enter sib2, iclass 10, count 2 2006.285.22:59:56.62#ibcon#flushed, iclass 10, count 2 2006.285.22:59:56.62#ibcon#about to write, iclass 10, count 2 2006.285.22:59:56.62#ibcon#wrote, iclass 10, count 2 2006.285.22:59:56.62#ibcon#about to read 3, iclass 10, count 2 2006.285.22:59:56.65#ibcon#read 3, iclass 10, count 2 2006.285.22:59:56.65#ibcon#about to read 4, iclass 10, count 2 2006.285.22:59:56.65#ibcon#read 4, iclass 10, count 2 2006.285.22:59:56.65#ibcon#about to read 5, iclass 10, count 2 2006.285.22:59:56.65#ibcon#read 5, iclass 10, count 2 2006.285.22:59:56.65#ibcon#about to read 6, iclass 10, count 2 2006.285.22:59:56.65#ibcon#read 6, iclass 10, count 2 2006.285.22:59:56.65#ibcon#end of sib2, iclass 10, count 2 2006.285.22:59:56.65#ibcon#*after write, iclass 10, count 2 2006.285.22:59:56.65#ibcon#*before return 0, iclass 10, count 2 2006.285.22:59:56.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:59:56.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:59:56.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.22:59:56.65#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:56.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:59:56.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:59:56.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:59:56.77#ibcon#enter wrdev, iclass 10, count 0 2006.285.22:59:56.77#ibcon#first serial, iclass 10, count 0 2006.285.22:59:56.77#ibcon#enter sib2, iclass 10, count 0 2006.285.22:59:56.77#ibcon#flushed, iclass 10, count 0 2006.285.22:59:56.77#ibcon#about to write, iclass 10, count 0 2006.285.22:59:56.77#ibcon#wrote, iclass 10, count 0 2006.285.22:59:56.77#ibcon#about to read 3, iclass 10, count 0 2006.285.22:59:56.79#ibcon#read 3, iclass 10, count 0 2006.285.22:59:56.79#ibcon#about to read 4, iclass 10, count 0 2006.285.22:59:56.79#ibcon#read 4, iclass 10, count 0 2006.285.22:59:56.79#ibcon#about to read 5, iclass 10, count 0 2006.285.22:59:56.79#ibcon#read 5, iclass 10, count 0 2006.285.22:59:56.79#ibcon#about to read 6, iclass 10, count 0 2006.285.22:59:56.79#ibcon#read 6, iclass 10, count 0 2006.285.22:59:56.79#ibcon#end of sib2, iclass 10, count 0 2006.285.22:59:56.79#ibcon#*mode == 0, iclass 10, count 0 2006.285.22:59:56.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.22:59:56.79#ibcon#[25=USB\r\n] 2006.285.22:59:56.79#ibcon#*before write, iclass 10, count 0 2006.285.22:59:56.79#ibcon#enter sib2, iclass 10, count 0 2006.285.22:59:56.79#ibcon#flushed, iclass 10, count 0 2006.285.22:59:56.79#ibcon#about to write, iclass 10, count 0 2006.285.22:59:56.79#ibcon#wrote, iclass 10, count 0 2006.285.22:59:56.79#ibcon#about to read 3, iclass 10, count 0 2006.285.22:59:56.82#ibcon#read 3, iclass 10, count 0 2006.285.22:59:56.82#ibcon#about to read 4, iclass 10, count 0 2006.285.22:59:56.82#ibcon#read 4, iclass 10, count 0 2006.285.22:59:56.82#ibcon#about to read 5, iclass 10, count 0 2006.285.22:59:56.82#ibcon#read 5, iclass 10, count 0 2006.285.22:59:56.82#ibcon#about to read 6, iclass 10, count 0 2006.285.22:59:56.82#ibcon#read 6, iclass 10, count 0 2006.285.22:59:56.82#ibcon#end of sib2, iclass 10, count 0 2006.285.22:59:56.82#ibcon#*after write, iclass 10, count 0 2006.285.22:59:56.82#ibcon#*before return 0, iclass 10, count 0 2006.285.22:59:56.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:59:56.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:59:56.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.22:59:56.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.22:59:56.82$vck44/valo=2,534.99 2006.285.22:59:56.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.22:59:56.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.22:59:56.82#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:56.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:59:56.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:59:56.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:59:56.82#ibcon#enter wrdev, iclass 12, count 0 2006.285.22:59:56.82#ibcon#first serial, iclass 12, count 0 2006.285.22:59:56.82#ibcon#enter sib2, iclass 12, count 0 2006.285.22:59:56.82#ibcon#flushed, iclass 12, count 0 2006.285.22:59:56.82#ibcon#about to write, iclass 12, count 0 2006.285.22:59:56.82#ibcon#wrote, iclass 12, count 0 2006.285.22:59:56.82#ibcon#about to read 3, iclass 12, count 0 2006.285.22:59:56.84#ibcon#read 3, iclass 12, count 0 2006.285.22:59:56.84#ibcon#about to read 4, iclass 12, count 0 2006.285.22:59:56.84#ibcon#read 4, iclass 12, count 0 2006.285.22:59:56.84#ibcon#about to read 5, iclass 12, count 0 2006.285.22:59:56.84#ibcon#read 5, iclass 12, count 0 2006.285.22:59:56.84#ibcon#about to read 6, iclass 12, count 0 2006.285.22:59:56.84#ibcon#read 6, iclass 12, count 0 2006.285.22:59:56.84#ibcon#end of sib2, iclass 12, count 0 2006.285.22:59:56.84#ibcon#*mode == 0, iclass 12, count 0 2006.285.22:59:56.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.22:59:56.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.22:59:56.84#ibcon#*before write, iclass 12, count 0 2006.285.22:59:56.84#ibcon#enter sib2, iclass 12, count 0 2006.285.22:59:56.84#ibcon#flushed, iclass 12, count 0 2006.285.22:59:56.84#ibcon#about to write, iclass 12, count 0 2006.285.22:59:56.84#ibcon#wrote, iclass 12, count 0 2006.285.22:59:56.84#ibcon#about to read 3, iclass 12, count 0 2006.285.22:59:56.88#ibcon#read 3, iclass 12, count 0 2006.285.22:59:56.88#ibcon#about to read 4, iclass 12, count 0 2006.285.22:59:56.88#ibcon#read 4, iclass 12, count 0 2006.285.22:59:56.88#ibcon#about to read 5, iclass 12, count 0 2006.285.22:59:56.88#ibcon#read 5, iclass 12, count 0 2006.285.22:59:56.88#ibcon#about to read 6, iclass 12, count 0 2006.285.22:59:56.88#ibcon#read 6, iclass 12, count 0 2006.285.22:59:56.88#ibcon#end of sib2, iclass 12, count 0 2006.285.22:59:56.88#ibcon#*after write, iclass 12, count 0 2006.285.22:59:56.88#ibcon#*before return 0, iclass 12, count 0 2006.285.22:59:56.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:59:56.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:59:56.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.22:59:56.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.22:59:56.88$vck44/va=2,6 2006.285.22:59:56.88#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.22:59:56.88#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.22:59:56.88#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:56.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:59:56.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:59:56.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:59:56.94#ibcon#enter wrdev, iclass 14, count 2 2006.285.22:59:56.94#ibcon#first serial, iclass 14, count 2 2006.285.22:59:56.94#ibcon#enter sib2, iclass 14, count 2 2006.285.22:59:56.94#ibcon#flushed, iclass 14, count 2 2006.285.22:59:56.94#ibcon#about to write, iclass 14, count 2 2006.285.22:59:56.94#ibcon#wrote, iclass 14, count 2 2006.285.22:59:56.94#ibcon#about to read 3, iclass 14, count 2 2006.285.22:59:56.96#ibcon#read 3, iclass 14, count 2 2006.285.22:59:56.96#ibcon#about to read 4, iclass 14, count 2 2006.285.22:59:56.96#ibcon#read 4, iclass 14, count 2 2006.285.22:59:56.96#ibcon#about to read 5, iclass 14, count 2 2006.285.22:59:56.96#ibcon#read 5, iclass 14, count 2 2006.285.22:59:56.96#ibcon#about to read 6, iclass 14, count 2 2006.285.22:59:56.96#ibcon#read 6, iclass 14, count 2 2006.285.22:59:56.96#ibcon#end of sib2, iclass 14, count 2 2006.285.22:59:56.96#ibcon#*mode == 0, iclass 14, count 2 2006.285.22:59:56.96#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.22:59:56.96#ibcon#[25=AT02-06\r\n] 2006.285.22:59:56.96#ibcon#*before write, iclass 14, count 2 2006.285.22:59:56.96#ibcon#enter sib2, iclass 14, count 2 2006.285.22:59:56.96#ibcon#flushed, iclass 14, count 2 2006.285.22:59:56.96#ibcon#about to write, iclass 14, count 2 2006.285.22:59:56.96#ibcon#wrote, iclass 14, count 2 2006.285.22:59:56.96#ibcon#about to read 3, iclass 14, count 2 2006.285.22:59:56.99#ibcon#read 3, iclass 14, count 2 2006.285.22:59:56.99#ibcon#about to read 4, iclass 14, count 2 2006.285.22:59:56.99#ibcon#read 4, iclass 14, count 2 2006.285.22:59:56.99#ibcon#about to read 5, iclass 14, count 2 2006.285.22:59:56.99#ibcon#read 5, iclass 14, count 2 2006.285.22:59:56.99#ibcon#about to read 6, iclass 14, count 2 2006.285.22:59:56.99#ibcon#read 6, iclass 14, count 2 2006.285.22:59:56.99#ibcon#end of sib2, iclass 14, count 2 2006.285.22:59:56.99#ibcon#*after write, iclass 14, count 2 2006.285.22:59:56.99#ibcon#*before return 0, iclass 14, count 2 2006.285.22:59:56.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:59:56.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:59:56.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.22:59:56.99#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:56.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:59:57.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:59:57.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:59:57.11#ibcon#enter wrdev, iclass 14, count 0 2006.285.22:59:57.11#ibcon#first serial, iclass 14, count 0 2006.285.22:59:57.11#ibcon#enter sib2, iclass 14, count 0 2006.285.22:59:57.11#ibcon#flushed, iclass 14, count 0 2006.285.22:59:57.11#ibcon#about to write, iclass 14, count 0 2006.285.22:59:57.11#ibcon#wrote, iclass 14, count 0 2006.285.22:59:57.11#ibcon#about to read 3, iclass 14, count 0 2006.285.22:59:57.13#ibcon#read 3, iclass 14, count 0 2006.285.22:59:57.13#ibcon#about to read 4, iclass 14, count 0 2006.285.22:59:57.13#ibcon#read 4, iclass 14, count 0 2006.285.22:59:57.13#ibcon#about to read 5, iclass 14, count 0 2006.285.22:59:57.13#ibcon#read 5, iclass 14, count 0 2006.285.22:59:57.13#ibcon#about to read 6, iclass 14, count 0 2006.285.22:59:57.13#ibcon#read 6, iclass 14, count 0 2006.285.22:59:57.13#ibcon#end of sib2, iclass 14, count 0 2006.285.22:59:57.13#ibcon#*mode == 0, iclass 14, count 0 2006.285.22:59:57.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.22:59:57.13#ibcon#[25=USB\r\n] 2006.285.22:59:57.13#ibcon#*before write, iclass 14, count 0 2006.285.22:59:57.13#ibcon#enter sib2, iclass 14, count 0 2006.285.22:59:57.13#ibcon#flushed, iclass 14, count 0 2006.285.22:59:57.13#ibcon#about to write, iclass 14, count 0 2006.285.22:59:57.13#ibcon#wrote, iclass 14, count 0 2006.285.22:59:57.13#ibcon#about to read 3, iclass 14, count 0 2006.285.22:59:57.16#ibcon#read 3, iclass 14, count 0 2006.285.22:59:57.16#ibcon#about to read 4, iclass 14, count 0 2006.285.22:59:57.16#ibcon#read 4, iclass 14, count 0 2006.285.22:59:57.16#ibcon#about to read 5, iclass 14, count 0 2006.285.22:59:57.16#ibcon#read 5, iclass 14, count 0 2006.285.22:59:57.16#ibcon#about to read 6, iclass 14, count 0 2006.285.22:59:57.16#ibcon#read 6, iclass 14, count 0 2006.285.22:59:57.16#ibcon#end of sib2, iclass 14, count 0 2006.285.22:59:57.16#ibcon#*after write, iclass 14, count 0 2006.285.22:59:57.16#ibcon#*before return 0, iclass 14, count 0 2006.285.22:59:57.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:59:57.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:59:57.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.22:59:57.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.22:59:57.16$vck44/valo=3,564.99 2006.285.22:59:57.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.22:59:57.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.22:59:57.16#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:57.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:59:57.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:59:57.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:59:57.16#ibcon#enter wrdev, iclass 16, count 0 2006.285.22:59:57.16#ibcon#first serial, iclass 16, count 0 2006.285.22:59:57.16#ibcon#enter sib2, iclass 16, count 0 2006.285.22:59:57.16#ibcon#flushed, iclass 16, count 0 2006.285.22:59:57.16#ibcon#about to write, iclass 16, count 0 2006.285.22:59:57.16#ibcon#wrote, iclass 16, count 0 2006.285.22:59:57.16#ibcon#about to read 3, iclass 16, count 0 2006.285.22:59:57.18#ibcon#read 3, iclass 16, count 0 2006.285.22:59:57.18#ibcon#about to read 4, iclass 16, count 0 2006.285.22:59:57.18#ibcon#read 4, iclass 16, count 0 2006.285.22:59:57.18#ibcon#about to read 5, iclass 16, count 0 2006.285.22:59:57.18#ibcon#read 5, iclass 16, count 0 2006.285.22:59:57.18#ibcon#about to read 6, iclass 16, count 0 2006.285.22:59:57.18#ibcon#read 6, iclass 16, count 0 2006.285.22:59:57.18#ibcon#end of sib2, iclass 16, count 0 2006.285.22:59:57.18#ibcon#*mode == 0, iclass 16, count 0 2006.285.22:59:57.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.22:59:57.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.22:59:57.18#ibcon#*before write, iclass 16, count 0 2006.285.22:59:57.18#ibcon#enter sib2, iclass 16, count 0 2006.285.22:59:57.18#ibcon#flushed, iclass 16, count 0 2006.285.22:59:57.18#ibcon#about to write, iclass 16, count 0 2006.285.22:59:57.18#ibcon#wrote, iclass 16, count 0 2006.285.22:59:57.18#ibcon#about to read 3, iclass 16, count 0 2006.285.22:59:57.22#ibcon#read 3, iclass 16, count 0 2006.285.22:59:57.22#ibcon#about to read 4, iclass 16, count 0 2006.285.22:59:57.22#ibcon#read 4, iclass 16, count 0 2006.285.22:59:57.22#ibcon#about to read 5, iclass 16, count 0 2006.285.22:59:57.22#ibcon#read 5, iclass 16, count 0 2006.285.22:59:57.22#ibcon#about to read 6, iclass 16, count 0 2006.285.22:59:57.22#ibcon#read 6, iclass 16, count 0 2006.285.22:59:57.22#ibcon#end of sib2, iclass 16, count 0 2006.285.22:59:57.22#ibcon#*after write, iclass 16, count 0 2006.285.22:59:57.22#ibcon#*before return 0, iclass 16, count 0 2006.285.22:59:57.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:59:57.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:59:57.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.22:59:57.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.22:59:57.22$vck44/va=3,7 2006.285.22:59:57.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.22:59:57.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.22:59:57.22#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:57.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:59:57.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:59:57.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:59:57.28#ibcon#enter wrdev, iclass 18, count 2 2006.285.22:59:57.28#ibcon#first serial, iclass 18, count 2 2006.285.22:59:57.28#ibcon#enter sib2, iclass 18, count 2 2006.285.22:59:57.28#ibcon#flushed, iclass 18, count 2 2006.285.22:59:57.28#ibcon#about to write, iclass 18, count 2 2006.285.22:59:57.28#ibcon#wrote, iclass 18, count 2 2006.285.22:59:57.28#ibcon#about to read 3, iclass 18, count 2 2006.285.22:59:57.30#ibcon#read 3, iclass 18, count 2 2006.285.22:59:57.30#ibcon#about to read 4, iclass 18, count 2 2006.285.22:59:57.30#ibcon#read 4, iclass 18, count 2 2006.285.22:59:57.30#ibcon#about to read 5, iclass 18, count 2 2006.285.22:59:57.30#ibcon#read 5, iclass 18, count 2 2006.285.22:59:57.30#ibcon#about to read 6, iclass 18, count 2 2006.285.22:59:57.30#ibcon#read 6, iclass 18, count 2 2006.285.22:59:57.30#ibcon#end of sib2, iclass 18, count 2 2006.285.22:59:57.30#ibcon#*mode == 0, iclass 18, count 2 2006.285.22:59:57.30#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.22:59:57.30#ibcon#[25=AT03-07\r\n] 2006.285.22:59:57.30#ibcon#*before write, iclass 18, count 2 2006.285.22:59:57.30#ibcon#enter sib2, iclass 18, count 2 2006.285.22:59:57.30#ibcon#flushed, iclass 18, count 2 2006.285.22:59:57.30#ibcon#about to write, iclass 18, count 2 2006.285.22:59:57.30#ibcon#wrote, iclass 18, count 2 2006.285.22:59:57.30#ibcon#about to read 3, iclass 18, count 2 2006.285.22:59:57.33#ibcon#read 3, iclass 18, count 2 2006.285.22:59:57.33#ibcon#about to read 4, iclass 18, count 2 2006.285.22:59:57.33#ibcon#read 4, iclass 18, count 2 2006.285.22:59:57.33#ibcon#about to read 5, iclass 18, count 2 2006.285.22:59:57.33#ibcon#read 5, iclass 18, count 2 2006.285.22:59:57.33#ibcon#about to read 6, iclass 18, count 2 2006.285.22:59:57.33#ibcon#read 6, iclass 18, count 2 2006.285.22:59:57.33#ibcon#end of sib2, iclass 18, count 2 2006.285.22:59:57.33#ibcon#*after write, iclass 18, count 2 2006.285.22:59:57.33#ibcon#*before return 0, iclass 18, count 2 2006.285.22:59:57.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:59:57.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:59:57.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.22:59:57.33#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:57.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:59:57.45#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:59:57.45#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:59:57.45#ibcon#enter wrdev, iclass 18, count 0 2006.285.22:59:57.45#ibcon#first serial, iclass 18, count 0 2006.285.22:59:57.45#ibcon#enter sib2, iclass 18, count 0 2006.285.22:59:57.45#ibcon#flushed, iclass 18, count 0 2006.285.22:59:57.45#ibcon#about to write, iclass 18, count 0 2006.285.22:59:57.45#ibcon#wrote, iclass 18, count 0 2006.285.22:59:57.45#ibcon#about to read 3, iclass 18, count 0 2006.285.22:59:57.47#ibcon#read 3, iclass 18, count 0 2006.285.22:59:57.47#ibcon#about to read 4, iclass 18, count 0 2006.285.22:59:57.47#ibcon#read 4, iclass 18, count 0 2006.285.22:59:57.47#ibcon#about to read 5, iclass 18, count 0 2006.285.22:59:57.47#ibcon#read 5, iclass 18, count 0 2006.285.22:59:57.47#ibcon#about to read 6, iclass 18, count 0 2006.285.22:59:57.47#ibcon#read 6, iclass 18, count 0 2006.285.22:59:57.47#ibcon#end of sib2, iclass 18, count 0 2006.285.22:59:57.47#ibcon#*mode == 0, iclass 18, count 0 2006.285.22:59:57.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.22:59:57.47#ibcon#[25=USB\r\n] 2006.285.22:59:57.47#ibcon#*before write, iclass 18, count 0 2006.285.22:59:57.47#ibcon#enter sib2, iclass 18, count 0 2006.285.22:59:57.47#ibcon#flushed, iclass 18, count 0 2006.285.22:59:57.47#ibcon#about to write, iclass 18, count 0 2006.285.22:59:57.47#ibcon#wrote, iclass 18, count 0 2006.285.22:59:57.47#ibcon#about to read 3, iclass 18, count 0 2006.285.22:59:57.50#ibcon#read 3, iclass 18, count 0 2006.285.22:59:57.50#ibcon#about to read 4, iclass 18, count 0 2006.285.22:59:57.50#ibcon#read 4, iclass 18, count 0 2006.285.22:59:57.50#ibcon#about to read 5, iclass 18, count 0 2006.285.22:59:57.50#ibcon#read 5, iclass 18, count 0 2006.285.22:59:57.50#ibcon#about to read 6, iclass 18, count 0 2006.285.22:59:57.50#ibcon#read 6, iclass 18, count 0 2006.285.22:59:57.50#ibcon#end of sib2, iclass 18, count 0 2006.285.22:59:57.50#ibcon#*after write, iclass 18, count 0 2006.285.22:59:57.50#ibcon#*before return 0, iclass 18, count 0 2006.285.22:59:57.50#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:59:57.50#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.22:59:57.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.22:59:57.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.22:59:57.50$vck44/valo=4,624.99 2006.285.22:59:57.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.22:59:57.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.22:59:57.50#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:57.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:59:57.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:59:57.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:59:57.50#ibcon#enter wrdev, iclass 20, count 0 2006.285.22:59:57.50#ibcon#first serial, iclass 20, count 0 2006.285.22:59:57.50#ibcon#enter sib2, iclass 20, count 0 2006.285.22:59:57.50#ibcon#flushed, iclass 20, count 0 2006.285.22:59:57.50#ibcon#about to write, iclass 20, count 0 2006.285.22:59:57.50#ibcon#wrote, iclass 20, count 0 2006.285.22:59:57.50#ibcon#about to read 3, iclass 20, count 0 2006.285.22:59:57.52#ibcon#read 3, iclass 20, count 0 2006.285.22:59:57.52#ibcon#about to read 4, iclass 20, count 0 2006.285.22:59:57.52#ibcon#read 4, iclass 20, count 0 2006.285.22:59:57.52#ibcon#about to read 5, iclass 20, count 0 2006.285.22:59:57.52#ibcon#read 5, iclass 20, count 0 2006.285.22:59:57.52#ibcon#about to read 6, iclass 20, count 0 2006.285.22:59:57.52#ibcon#read 6, iclass 20, count 0 2006.285.22:59:57.52#ibcon#end of sib2, iclass 20, count 0 2006.285.22:59:57.52#ibcon#*mode == 0, iclass 20, count 0 2006.285.22:59:57.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.22:59:57.52#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.22:59:57.52#ibcon#*before write, iclass 20, count 0 2006.285.22:59:57.52#ibcon#enter sib2, iclass 20, count 0 2006.285.22:59:57.52#ibcon#flushed, iclass 20, count 0 2006.285.22:59:57.52#ibcon#about to write, iclass 20, count 0 2006.285.22:59:57.52#ibcon#wrote, iclass 20, count 0 2006.285.22:59:57.52#ibcon#about to read 3, iclass 20, count 0 2006.285.22:59:57.56#ibcon#read 3, iclass 20, count 0 2006.285.22:59:57.56#ibcon#about to read 4, iclass 20, count 0 2006.285.22:59:57.56#ibcon#read 4, iclass 20, count 0 2006.285.22:59:57.56#ibcon#about to read 5, iclass 20, count 0 2006.285.22:59:57.56#ibcon#read 5, iclass 20, count 0 2006.285.22:59:57.56#ibcon#about to read 6, iclass 20, count 0 2006.285.22:59:57.56#ibcon#read 6, iclass 20, count 0 2006.285.22:59:57.56#ibcon#end of sib2, iclass 20, count 0 2006.285.22:59:57.56#ibcon#*after write, iclass 20, count 0 2006.285.22:59:57.56#ibcon#*before return 0, iclass 20, count 0 2006.285.22:59:57.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:59:57.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.22:59:57.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.22:59:57.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.22:59:57.56$vck44/va=4,6 2006.285.22:59:57.56#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.22:59:57.56#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.22:59:57.56#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:57.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:59:57.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:59:57.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:59:57.62#ibcon#enter wrdev, iclass 22, count 2 2006.285.22:59:57.62#ibcon#first serial, iclass 22, count 2 2006.285.22:59:57.62#ibcon#enter sib2, iclass 22, count 2 2006.285.22:59:57.62#ibcon#flushed, iclass 22, count 2 2006.285.22:59:57.62#ibcon#about to write, iclass 22, count 2 2006.285.22:59:57.62#ibcon#wrote, iclass 22, count 2 2006.285.22:59:57.62#ibcon#about to read 3, iclass 22, count 2 2006.285.22:59:57.64#ibcon#read 3, iclass 22, count 2 2006.285.22:59:57.64#ibcon#about to read 4, iclass 22, count 2 2006.285.22:59:57.64#ibcon#read 4, iclass 22, count 2 2006.285.22:59:57.64#ibcon#about to read 5, iclass 22, count 2 2006.285.22:59:57.64#ibcon#read 5, iclass 22, count 2 2006.285.22:59:57.64#ibcon#about to read 6, iclass 22, count 2 2006.285.22:59:57.64#ibcon#read 6, iclass 22, count 2 2006.285.22:59:57.64#ibcon#end of sib2, iclass 22, count 2 2006.285.22:59:57.64#ibcon#*mode == 0, iclass 22, count 2 2006.285.22:59:57.64#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.22:59:57.64#ibcon#[25=AT04-06\r\n] 2006.285.22:59:57.64#ibcon#*before write, iclass 22, count 2 2006.285.22:59:57.64#ibcon#enter sib2, iclass 22, count 2 2006.285.22:59:57.64#ibcon#flushed, iclass 22, count 2 2006.285.22:59:57.64#ibcon#about to write, iclass 22, count 2 2006.285.22:59:57.64#ibcon#wrote, iclass 22, count 2 2006.285.22:59:57.64#ibcon#about to read 3, iclass 22, count 2 2006.285.22:59:57.67#ibcon#read 3, iclass 22, count 2 2006.285.22:59:57.67#ibcon#about to read 4, iclass 22, count 2 2006.285.22:59:57.67#ibcon#read 4, iclass 22, count 2 2006.285.22:59:57.67#ibcon#about to read 5, iclass 22, count 2 2006.285.22:59:57.67#ibcon#read 5, iclass 22, count 2 2006.285.22:59:57.67#ibcon#about to read 6, iclass 22, count 2 2006.285.22:59:57.67#ibcon#read 6, iclass 22, count 2 2006.285.22:59:57.67#ibcon#end of sib2, iclass 22, count 2 2006.285.22:59:57.67#ibcon#*after write, iclass 22, count 2 2006.285.22:59:57.67#ibcon#*before return 0, iclass 22, count 2 2006.285.22:59:57.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:59:57.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.22:59:57.67#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.22:59:57.67#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:57.67#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:59:57.79#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:59:57.79#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:59:57.79#ibcon#enter wrdev, iclass 22, count 0 2006.285.22:59:57.79#ibcon#first serial, iclass 22, count 0 2006.285.22:59:57.79#ibcon#enter sib2, iclass 22, count 0 2006.285.22:59:57.79#ibcon#flushed, iclass 22, count 0 2006.285.22:59:57.79#ibcon#about to write, iclass 22, count 0 2006.285.22:59:57.79#ibcon#wrote, iclass 22, count 0 2006.285.22:59:57.79#ibcon#about to read 3, iclass 22, count 0 2006.285.22:59:57.81#ibcon#read 3, iclass 22, count 0 2006.285.22:59:57.81#ibcon#about to read 4, iclass 22, count 0 2006.285.22:59:57.81#ibcon#read 4, iclass 22, count 0 2006.285.22:59:57.81#ibcon#about to read 5, iclass 22, count 0 2006.285.22:59:57.81#ibcon#read 5, iclass 22, count 0 2006.285.22:59:57.81#ibcon#about to read 6, iclass 22, count 0 2006.285.22:59:57.81#ibcon#read 6, iclass 22, count 0 2006.285.22:59:57.81#ibcon#end of sib2, iclass 22, count 0 2006.285.22:59:57.81#ibcon#*mode == 0, iclass 22, count 0 2006.285.22:59:57.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.22:59:57.81#ibcon#[25=USB\r\n] 2006.285.22:59:57.81#ibcon#*before write, iclass 22, count 0 2006.285.22:59:57.81#ibcon#enter sib2, iclass 22, count 0 2006.285.22:59:57.81#ibcon#flushed, iclass 22, count 0 2006.285.22:59:57.81#ibcon#about to write, iclass 22, count 0 2006.285.22:59:57.81#ibcon#wrote, iclass 22, count 0 2006.285.22:59:57.81#ibcon#about to read 3, iclass 22, count 0 2006.285.22:59:57.84#ibcon#read 3, iclass 22, count 0 2006.285.22:59:57.84#ibcon#about to read 4, iclass 22, count 0 2006.285.22:59:57.84#ibcon#read 4, iclass 22, count 0 2006.285.22:59:57.84#ibcon#about to read 5, iclass 22, count 0 2006.285.22:59:57.84#ibcon#read 5, iclass 22, count 0 2006.285.22:59:57.84#ibcon#about to read 6, iclass 22, count 0 2006.285.22:59:57.84#ibcon#read 6, iclass 22, count 0 2006.285.22:59:57.84#ibcon#end of sib2, iclass 22, count 0 2006.285.22:59:57.84#ibcon#*after write, iclass 22, count 0 2006.285.22:59:57.84#ibcon#*before return 0, iclass 22, count 0 2006.285.22:59:57.84#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:59:57.84#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.22:59:57.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.22:59:57.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.22:59:57.84$vck44/valo=5,734.99 2006.285.22:59:57.84#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.22:59:57.84#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.22:59:57.84#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:57.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:59:57.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:59:57.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:59:57.84#ibcon#enter wrdev, iclass 24, count 0 2006.285.22:59:57.84#ibcon#first serial, iclass 24, count 0 2006.285.22:59:57.84#ibcon#enter sib2, iclass 24, count 0 2006.285.22:59:57.84#ibcon#flushed, iclass 24, count 0 2006.285.22:59:57.84#ibcon#about to write, iclass 24, count 0 2006.285.22:59:57.84#ibcon#wrote, iclass 24, count 0 2006.285.22:59:57.84#ibcon#about to read 3, iclass 24, count 0 2006.285.22:59:57.86#ibcon#read 3, iclass 24, count 0 2006.285.22:59:57.86#ibcon#about to read 4, iclass 24, count 0 2006.285.22:59:57.86#ibcon#read 4, iclass 24, count 0 2006.285.22:59:57.86#ibcon#about to read 5, iclass 24, count 0 2006.285.22:59:57.86#ibcon#read 5, iclass 24, count 0 2006.285.22:59:57.86#ibcon#about to read 6, iclass 24, count 0 2006.285.22:59:57.86#ibcon#read 6, iclass 24, count 0 2006.285.22:59:57.86#ibcon#end of sib2, iclass 24, count 0 2006.285.22:59:57.86#ibcon#*mode == 0, iclass 24, count 0 2006.285.22:59:57.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.22:59:57.86#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.22:59:57.86#ibcon#*before write, iclass 24, count 0 2006.285.22:59:57.86#ibcon#enter sib2, iclass 24, count 0 2006.285.22:59:57.86#ibcon#flushed, iclass 24, count 0 2006.285.22:59:57.86#ibcon#about to write, iclass 24, count 0 2006.285.22:59:57.86#ibcon#wrote, iclass 24, count 0 2006.285.22:59:57.86#ibcon#about to read 3, iclass 24, count 0 2006.285.22:59:57.90#ibcon#read 3, iclass 24, count 0 2006.285.22:59:57.90#ibcon#about to read 4, iclass 24, count 0 2006.285.22:59:57.90#ibcon#read 4, iclass 24, count 0 2006.285.22:59:57.90#ibcon#about to read 5, iclass 24, count 0 2006.285.22:59:57.90#ibcon#read 5, iclass 24, count 0 2006.285.22:59:57.90#ibcon#about to read 6, iclass 24, count 0 2006.285.22:59:57.90#ibcon#read 6, iclass 24, count 0 2006.285.22:59:57.90#ibcon#end of sib2, iclass 24, count 0 2006.285.22:59:57.90#ibcon#*after write, iclass 24, count 0 2006.285.22:59:57.90#ibcon#*before return 0, iclass 24, count 0 2006.285.22:59:57.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:59:57.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.22:59:57.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.22:59:57.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.22:59:57.90$vck44/va=5,3 2006.285.22:59:57.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.22:59:57.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.22:59:57.90#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:57.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:59:57.92#abcon#<5=/03 3.2 6.0 18.42 891016.3\r\n> 2006.285.22:59:57.94#abcon#{5=INTERFACE CLEAR} 2006.285.22:59:57.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:59:57.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:59:57.96#ibcon#enter wrdev, iclass 27, count 2 2006.285.22:59:57.96#ibcon#first serial, iclass 27, count 2 2006.285.22:59:57.96#ibcon#enter sib2, iclass 27, count 2 2006.285.22:59:57.96#ibcon#flushed, iclass 27, count 2 2006.285.22:59:57.96#ibcon#about to write, iclass 27, count 2 2006.285.22:59:57.96#ibcon#wrote, iclass 27, count 2 2006.285.22:59:57.96#ibcon#about to read 3, iclass 27, count 2 2006.285.22:59:57.98#ibcon#read 3, iclass 27, count 2 2006.285.22:59:57.98#ibcon#about to read 4, iclass 27, count 2 2006.285.22:59:57.98#ibcon#read 4, iclass 27, count 2 2006.285.22:59:57.98#ibcon#about to read 5, iclass 27, count 2 2006.285.22:59:57.98#ibcon#read 5, iclass 27, count 2 2006.285.22:59:57.98#ibcon#about to read 6, iclass 27, count 2 2006.285.22:59:57.98#ibcon#read 6, iclass 27, count 2 2006.285.22:59:57.98#ibcon#end of sib2, iclass 27, count 2 2006.285.22:59:57.98#ibcon#*mode == 0, iclass 27, count 2 2006.285.22:59:57.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.22:59:57.98#ibcon#[25=AT05-03\r\n] 2006.285.22:59:57.98#ibcon#*before write, iclass 27, count 2 2006.285.22:59:57.98#ibcon#enter sib2, iclass 27, count 2 2006.285.22:59:57.98#ibcon#flushed, iclass 27, count 2 2006.285.22:59:57.98#ibcon#about to write, iclass 27, count 2 2006.285.22:59:57.98#ibcon#wrote, iclass 27, count 2 2006.285.22:59:57.98#ibcon#about to read 3, iclass 27, count 2 2006.285.22:59:58.00#abcon#[5=S1D000X0/0*\r\n] 2006.285.22:59:58.01#ibcon#read 3, iclass 27, count 2 2006.285.22:59:58.01#ibcon#about to read 4, iclass 27, count 2 2006.285.22:59:58.01#ibcon#read 4, iclass 27, count 2 2006.285.22:59:58.01#ibcon#about to read 5, iclass 27, count 2 2006.285.22:59:58.01#ibcon#read 5, iclass 27, count 2 2006.285.22:59:58.01#ibcon#about to read 6, iclass 27, count 2 2006.285.22:59:58.01#ibcon#read 6, iclass 27, count 2 2006.285.22:59:58.01#ibcon#end of sib2, iclass 27, count 2 2006.285.22:59:58.01#ibcon#*after write, iclass 27, count 2 2006.285.22:59:58.01#ibcon#*before return 0, iclass 27, count 2 2006.285.22:59:58.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:59:58.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.22:59:58.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.22:59:58.01#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:58.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:59:58.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:59:58.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:59:58.13#ibcon#enter wrdev, iclass 27, count 0 2006.285.22:59:58.13#ibcon#first serial, iclass 27, count 0 2006.285.22:59:58.13#ibcon#enter sib2, iclass 27, count 0 2006.285.22:59:58.13#ibcon#flushed, iclass 27, count 0 2006.285.22:59:58.13#ibcon#about to write, iclass 27, count 0 2006.285.22:59:58.13#ibcon#wrote, iclass 27, count 0 2006.285.22:59:58.13#ibcon#about to read 3, iclass 27, count 0 2006.285.22:59:58.15#ibcon#read 3, iclass 27, count 0 2006.285.22:59:58.15#ibcon#about to read 4, iclass 27, count 0 2006.285.22:59:58.15#ibcon#read 4, iclass 27, count 0 2006.285.22:59:58.15#ibcon#about to read 5, iclass 27, count 0 2006.285.22:59:58.15#ibcon#read 5, iclass 27, count 0 2006.285.22:59:58.15#ibcon#about to read 6, iclass 27, count 0 2006.285.22:59:58.15#ibcon#read 6, iclass 27, count 0 2006.285.22:59:58.15#ibcon#end of sib2, iclass 27, count 0 2006.285.22:59:58.15#ibcon#*mode == 0, iclass 27, count 0 2006.285.22:59:58.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.22:59:58.15#ibcon#[25=USB\r\n] 2006.285.22:59:58.15#ibcon#*before write, iclass 27, count 0 2006.285.22:59:58.15#ibcon#enter sib2, iclass 27, count 0 2006.285.22:59:58.15#ibcon#flushed, iclass 27, count 0 2006.285.22:59:58.15#ibcon#about to write, iclass 27, count 0 2006.285.22:59:58.15#ibcon#wrote, iclass 27, count 0 2006.285.22:59:58.15#ibcon#about to read 3, iclass 27, count 0 2006.285.22:59:58.18#ibcon#read 3, iclass 27, count 0 2006.285.22:59:58.18#ibcon#about to read 4, iclass 27, count 0 2006.285.22:59:58.18#ibcon#read 4, iclass 27, count 0 2006.285.22:59:58.18#ibcon#about to read 5, iclass 27, count 0 2006.285.22:59:58.18#ibcon#read 5, iclass 27, count 0 2006.285.22:59:58.18#ibcon#about to read 6, iclass 27, count 0 2006.285.22:59:58.18#ibcon#read 6, iclass 27, count 0 2006.285.22:59:58.18#ibcon#end of sib2, iclass 27, count 0 2006.285.22:59:58.18#ibcon#*after write, iclass 27, count 0 2006.285.22:59:58.18#ibcon#*before return 0, iclass 27, count 0 2006.285.22:59:58.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:59:58.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.22:59:58.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.22:59:58.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.22:59:58.18$vck44/valo=6,814.99 2006.285.22:59:58.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.22:59:58.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.22:59:58.18#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:58.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:59:58.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:59:58.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:59:58.18#ibcon#enter wrdev, iclass 32, count 0 2006.285.22:59:58.18#ibcon#first serial, iclass 32, count 0 2006.285.22:59:58.18#ibcon#enter sib2, iclass 32, count 0 2006.285.22:59:58.18#ibcon#flushed, iclass 32, count 0 2006.285.22:59:58.18#ibcon#about to write, iclass 32, count 0 2006.285.22:59:58.18#ibcon#wrote, iclass 32, count 0 2006.285.22:59:58.18#ibcon#about to read 3, iclass 32, count 0 2006.285.22:59:58.20#ibcon#read 3, iclass 32, count 0 2006.285.22:59:58.20#ibcon#about to read 4, iclass 32, count 0 2006.285.22:59:58.20#ibcon#read 4, iclass 32, count 0 2006.285.22:59:58.20#ibcon#about to read 5, iclass 32, count 0 2006.285.22:59:58.20#ibcon#read 5, iclass 32, count 0 2006.285.22:59:58.20#ibcon#about to read 6, iclass 32, count 0 2006.285.22:59:58.20#ibcon#read 6, iclass 32, count 0 2006.285.22:59:58.20#ibcon#end of sib2, iclass 32, count 0 2006.285.22:59:58.20#ibcon#*mode == 0, iclass 32, count 0 2006.285.22:59:58.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.22:59:58.20#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.22:59:58.20#ibcon#*before write, iclass 32, count 0 2006.285.22:59:58.20#ibcon#enter sib2, iclass 32, count 0 2006.285.22:59:58.20#ibcon#flushed, iclass 32, count 0 2006.285.22:59:58.20#ibcon#about to write, iclass 32, count 0 2006.285.22:59:58.20#ibcon#wrote, iclass 32, count 0 2006.285.22:59:58.20#ibcon#about to read 3, iclass 32, count 0 2006.285.22:59:58.24#ibcon#read 3, iclass 32, count 0 2006.285.22:59:58.24#ibcon#about to read 4, iclass 32, count 0 2006.285.22:59:58.24#ibcon#read 4, iclass 32, count 0 2006.285.22:59:58.24#ibcon#about to read 5, iclass 32, count 0 2006.285.22:59:58.24#ibcon#read 5, iclass 32, count 0 2006.285.22:59:58.24#ibcon#about to read 6, iclass 32, count 0 2006.285.22:59:58.24#ibcon#read 6, iclass 32, count 0 2006.285.22:59:58.24#ibcon#end of sib2, iclass 32, count 0 2006.285.22:59:58.24#ibcon#*after write, iclass 32, count 0 2006.285.22:59:58.24#ibcon#*before return 0, iclass 32, count 0 2006.285.22:59:58.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:59:58.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.22:59:58.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.22:59:58.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.22:59:58.24$vck44/va=6,4 2006.285.22:59:58.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.22:59:58.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.22:59:58.24#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:58.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:59:58.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:59:58.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:59:58.30#ibcon#enter wrdev, iclass 34, count 2 2006.285.22:59:58.30#ibcon#first serial, iclass 34, count 2 2006.285.22:59:58.30#ibcon#enter sib2, iclass 34, count 2 2006.285.22:59:58.30#ibcon#flushed, iclass 34, count 2 2006.285.22:59:58.30#ibcon#about to write, iclass 34, count 2 2006.285.22:59:58.30#ibcon#wrote, iclass 34, count 2 2006.285.22:59:58.30#ibcon#about to read 3, iclass 34, count 2 2006.285.22:59:58.32#ibcon#read 3, iclass 34, count 2 2006.285.22:59:58.32#ibcon#about to read 4, iclass 34, count 2 2006.285.22:59:58.32#ibcon#read 4, iclass 34, count 2 2006.285.22:59:58.32#ibcon#about to read 5, iclass 34, count 2 2006.285.22:59:58.32#ibcon#read 5, iclass 34, count 2 2006.285.22:59:58.32#ibcon#about to read 6, iclass 34, count 2 2006.285.22:59:58.32#ibcon#read 6, iclass 34, count 2 2006.285.22:59:58.32#ibcon#end of sib2, iclass 34, count 2 2006.285.22:59:58.32#ibcon#*mode == 0, iclass 34, count 2 2006.285.22:59:58.32#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.22:59:58.32#ibcon#[25=AT06-04\r\n] 2006.285.22:59:58.32#ibcon#*before write, iclass 34, count 2 2006.285.22:59:58.32#ibcon#enter sib2, iclass 34, count 2 2006.285.22:59:58.32#ibcon#flushed, iclass 34, count 2 2006.285.22:59:58.32#ibcon#about to write, iclass 34, count 2 2006.285.22:59:58.32#ibcon#wrote, iclass 34, count 2 2006.285.22:59:58.32#ibcon#about to read 3, iclass 34, count 2 2006.285.22:59:58.35#ibcon#read 3, iclass 34, count 2 2006.285.22:59:58.35#ibcon#about to read 4, iclass 34, count 2 2006.285.22:59:58.35#ibcon#read 4, iclass 34, count 2 2006.285.22:59:58.35#ibcon#about to read 5, iclass 34, count 2 2006.285.22:59:58.35#ibcon#read 5, iclass 34, count 2 2006.285.22:59:58.35#ibcon#about to read 6, iclass 34, count 2 2006.285.22:59:58.35#ibcon#read 6, iclass 34, count 2 2006.285.22:59:58.35#ibcon#end of sib2, iclass 34, count 2 2006.285.22:59:58.35#ibcon#*after write, iclass 34, count 2 2006.285.22:59:58.35#ibcon#*before return 0, iclass 34, count 2 2006.285.22:59:58.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:59:58.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.22:59:58.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.22:59:58.35#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:58.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:59:58.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:59:58.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:59:58.47#ibcon#enter wrdev, iclass 34, count 0 2006.285.22:59:58.47#ibcon#first serial, iclass 34, count 0 2006.285.22:59:58.47#ibcon#enter sib2, iclass 34, count 0 2006.285.22:59:58.47#ibcon#flushed, iclass 34, count 0 2006.285.22:59:58.47#ibcon#about to write, iclass 34, count 0 2006.285.22:59:58.47#ibcon#wrote, iclass 34, count 0 2006.285.22:59:58.47#ibcon#about to read 3, iclass 34, count 0 2006.285.22:59:58.49#ibcon#read 3, iclass 34, count 0 2006.285.22:59:58.49#ibcon#about to read 4, iclass 34, count 0 2006.285.22:59:58.49#ibcon#read 4, iclass 34, count 0 2006.285.22:59:58.49#ibcon#about to read 5, iclass 34, count 0 2006.285.22:59:58.49#ibcon#read 5, iclass 34, count 0 2006.285.22:59:58.49#ibcon#about to read 6, iclass 34, count 0 2006.285.22:59:58.49#ibcon#read 6, iclass 34, count 0 2006.285.22:59:58.49#ibcon#end of sib2, iclass 34, count 0 2006.285.22:59:58.49#ibcon#*mode == 0, iclass 34, count 0 2006.285.22:59:58.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.22:59:58.49#ibcon#[25=USB\r\n] 2006.285.22:59:58.49#ibcon#*before write, iclass 34, count 0 2006.285.22:59:58.49#ibcon#enter sib2, iclass 34, count 0 2006.285.22:59:58.49#ibcon#flushed, iclass 34, count 0 2006.285.22:59:58.49#ibcon#about to write, iclass 34, count 0 2006.285.22:59:58.49#ibcon#wrote, iclass 34, count 0 2006.285.22:59:58.49#ibcon#about to read 3, iclass 34, count 0 2006.285.22:59:58.52#ibcon#read 3, iclass 34, count 0 2006.285.22:59:58.52#ibcon#about to read 4, iclass 34, count 0 2006.285.22:59:58.52#ibcon#read 4, iclass 34, count 0 2006.285.22:59:58.52#ibcon#about to read 5, iclass 34, count 0 2006.285.22:59:58.52#ibcon#read 5, iclass 34, count 0 2006.285.22:59:58.52#ibcon#about to read 6, iclass 34, count 0 2006.285.22:59:58.52#ibcon#read 6, iclass 34, count 0 2006.285.22:59:58.52#ibcon#end of sib2, iclass 34, count 0 2006.285.22:59:58.52#ibcon#*after write, iclass 34, count 0 2006.285.22:59:58.52#ibcon#*before return 0, iclass 34, count 0 2006.285.22:59:58.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:59:58.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.22:59:58.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.22:59:58.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.22:59:58.52$vck44/valo=7,864.99 2006.285.22:59:58.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.22:59:58.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.22:59:58.52#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:58.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:59:58.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:59:58.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:59:58.52#ibcon#enter wrdev, iclass 36, count 0 2006.285.22:59:58.52#ibcon#first serial, iclass 36, count 0 2006.285.22:59:58.52#ibcon#enter sib2, iclass 36, count 0 2006.285.22:59:58.52#ibcon#flushed, iclass 36, count 0 2006.285.22:59:58.52#ibcon#about to write, iclass 36, count 0 2006.285.22:59:58.52#ibcon#wrote, iclass 36, count 0 2006.285.22:59:58.52#ibcon#about to read 3, iclass 36, count 0 2006.285.22:59:58.54#ibcon#read 3, iclass 36, count 0 2006.285.22:59:58.54#ibcon#about to read 4, iclass 36, count 0 2006.285.22:59:58.54#ibcon#read 4, iclass 36, count 0 2006.285.22:59:58.54#ibcon#about to read 5, iclass 36, count 0 2006.285.22:59:58.54#ibcon#read 5, iclass 36, count 0 2006.285.22:59:58.54#ibcon#about to read 6, iclass 36, count 0 2006.285.22:59:58.54#ibcon#read 6, iclass 36, count 0 2006.285.22:59:58.54#ibcon#end of sib2, iclass 36, count 0 2006.285.22:59:58.54#ibcon#*mode == 0, iclass 36, count 0 2006.285.22:59:58.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.22:59:58.54#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.22:59:58.54#ibcon#*before write, iclass 36, count 0 2006.285.22:59:58.54#ibcon#enter sib2, iclass 36, count 0 2006.285.22:59:58.54#ibcon#flushed, iclass 36, count 0 2006.285.22:59:58.54#ibcon#about to write, iclass 36, count 0 2006.285.22:59:58.54#ibcon#wrote, iclass 36, count 0 2006.285.22:59:58.54#ibcon#about to read 3, iclass 36, count 0 2006.285.22:59:58.58#ibcon#read 3, iclass 36, count 0 2006.285.22:59:58.58#ibcon#about to read 4, iclass 36, count 0 2006.285.22:59:58.58#ibcon#read 4, iclass 36, count 0 2006.285.22:59:58.58#ibcon#about to read 5, iclass 36, count 0 2006.285.22:59:58.58#ibcon#read 5, iclass 36, count 0 2006.285.22:59:58.58#ibcon#about to read 6, iclass 36, count 0 2006.285.22:59:58.58#ibcon#read 6, iclass 36, count 0 2006.285.22:59:58.58#ibcon#end of sib2, iclass 36, count 0 2006.285.22:59:58.58#ibcon#*after write, iclass 36, count 0 2006.285.22:59:58.58#ibcon#*before return 0, iclass 36, count 0 2006.285.22:59:58.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:59:58.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.22:59:58.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.22:59:58.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.22:59:58.58$vck44/va=7,4 2006.285.22:59:58.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.22:59:58.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.22:59:58.58#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:58.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:59:58.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:59:58.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:59:58.64#ibcon#enter wrdev, iclass 38, count 2 2006.285.22:59:58.64#ibcon#first serial, iclass 38, count 2 2006.285.22:59:58.64#ibcon#enter sib2, iclass 38, count 2 2006.285.22:59:58.64#ibcon#flushed, iclass 38, count 2 2006.285.22:59:58.64#ibcon#about to write, iclass 38, count 2 2006.285.22:59:58.64#ibcon#wrote, iclass 38, count 2 2006.285.22:59:58.64#ibcon#about to read 3, iclass 38, count 2 2006.285.22:59:58.66#ibcon#read 3, iclass 38, count 2 2006.285.22:59:58.66#ibcon#about to read 4, iclass 38, count 2 2006.285.22:59:58.66#ibcon#read 4, iclass 38, count 2 2006.285.22:59:58.66#ibcon#about to read 5, iclass 38, count 2 2006.285.22:59:58.66#ibcon#read 5, iclass 38, count 2 2006.285.22:59:58.66#ibcon#about to read 6, iclass 38, count 2 2006.285.22:59:58.66#ibcon#read 6, iclass 38, count 2 2006.285.22:59:58.66#ibcon#end of sib2, iclass 38, count 2 2006.285.22:59:58.66#ibcon#*mode == 0, iclass 38, count 2 2006.285.22:59:58.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.22:59:58.66#ibcon#[25=AT07-04\r\n] 2006.285.22:59:58.66#ibcon#*before write, iclass 38, count 2 2006.285.22:59:58.66#ibcon#enter sib2, iclass 38, count 2 2006.285.22:59:58.66#ibcon#flushed, iclass 38, count 2 2006.285.22:59:58.66#ibcon#about to write, iclass 38, count 2 2006.285.22:59:58.66#ibcon#wrote, iclass 38, count 2 2006.285.22:59:58.66#ibcon#about to read 3, iclass 38, count 2 2006.285.22:59:58.69#ibcon#read 3, iclass 38, count 2 2006.285.22:59:58.69#ibcon#about to read 4, iclass 38, count 2 2006.285.22:59:58.69#ibcon#read 4, iclass 38, count 2 2006.285.22:59:58.69#ibcon#about to read 5, iclass 38, count 2 2006.285.22:59:58.69#ibcon#read 5, iclass 38, count 2 2006.285.22:59:58.69#ibcon#about to read 6, iclass 38, count 2 2006.285.22:59:58.69#ibcon#read 6, iclass 38, count 2 2006.285.22:59:58.69#ibcon#end of sib2, iclass 38, count 2 2006.285.22:59:58.69#ibcon#*after write, iclass 38, count 2 2006.285.22:59:58.69#ibcon#*before return 0, iclass 38, count 2 2006.285.22:59:58.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:59:58.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.22:59:58.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.22:59:58.69#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:58.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:59:58.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:59:58.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:59:58.81#ibcon#enter wrdev, iclass 38, count 0 2006.285.22:59:58.81#ibcon#first serial, iclass 38, count 0 2006.285.22:59:58.81#ibcon#enter sib2, iclass 38, count 0 2006.285.22:59:58.81#ibcon#flushed, iclass 38, count 0 2006.285.22:59:58.81#ibcon#about to write, iclass 38, count 0 2006.285.22:59:58.81#ibcon#wrote, iclass 38, count 0 2006.285.22:59:58.81#ibcon#about to read 3, iclass 38, count 0 2006.285.22:59:58.83#ibcon#read 3, iclass 38, count 0 2006.285.22:59:58.83#ibcon#about to read 4, iclass 38, count 0 2006.285.22:59:58.83#ibcon#read 4, iclass 38, count 0 2006.285.22:59:58.83#ibcon#about to read 5, iclass 38, count 0 2006.285.22:59:58.83#ibcon#read 5, iclass 38, count 0 2006.285.22:59:58.83#ibcon#about to read 6, iclass 38, count 0 2006.285.22:59:58.83#ibcon#read 6, iclass 38, count 0 2006.285.22:59:58.83#ibcon#end of sib2, iclass 38, count 0 2006.285.22:59:58.83#ibcon#*mode == 0, iclass 38, count 0 2006.285.22:59:58.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.22:59:58.83#ibcon#[25=USB\r\n] 2006.285.22:59:58.83#ibcon#*before write, iclass 38, count 0 2006.285.22:59:58.83#ibcon#enter sib2, iclass 38, count 0 2006.285.22:59:58.83#ibcon#flushed, iclass 38, count 0 2006.285.22:59:58.83#ibcon#about to write, iclass 38, count 0 2006.285.22:59:58.83#ibcon#wrote, iclass 38, count 0 2006.285.22:59:58.83#ibcon#about to read 3, iclass 38, count 0 2006.285.22:59:58.86#ibcon#read 3, iclass 38, count 0 2006.285.22:59:58.86#ibcon#about to read 4, iclass 38, count 0 2006.285.22:59:58.86#ibcon#read 4, iclass 38, count 0 2006.285.22:59:58.86#ibcon#about to read 5, iclass 38, count 0 2006.285.22:59:58.86#ibcon#read 5, iclass 38, count 0 2006.285.22:59:58.86#ibcon#about to read 6, iclass 38, count 0 2006.285.22:59:58.86#ibcon#read 6, iclass 38, count 0 2006.285.22:59:58.86#ibcon#end of sib2, iclass 38, count 0 2006.285.22:59:58.86#ibcon#*after write, iclass 38, count 0 2006.285.22:59:58.86#ibcon#*before return 0, iclass 38, count 0 2006.285.22:59:58.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:59:58.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.22:59:58.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.22:59:58.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.22:59:58.86$vck44/valo=8,884.99 2006.285.22:59:58.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.22:59:58.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.22:59:58.86#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:58.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:59:58.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:59:58.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:59:58.86#ibcon#enter wrdev, iclass 40, count 0 2006.285.22:59:58.86#ibcon#first serial, iclass 40, count 0 2006.285.22:59:58.86#ibcon#enter sib2, iclass 40, count 0 2006.285.22:59:58.86#ibcon#flushed, iclass 40, count 0 2006.285.22:59:58.86#ibcon#about to write, iclass 40, count 0 2006.285.22:59:58.86#ibcon#wrote, iclass 40, count 0 2006.285.22:59:58.86#ibcon#about to read 3, iclass 40, count 0 2006.285.22:59:58.88#ibcon#read 3, iclass 40, count 0 2006.285.22:59:58.88#ibcon#about to read 4, iclass 40, count 0 2006.285.22:59:58.88#ibcon#read 4, iclass 40, count 0 2006.285.22:59:58.88#ibcon#about to read 5, iclass 40, count 0 2006.285.22:59:58.88#ibcon#read 5, iclass 40, count 0 2006.285.22:59:58.88#ibcon#about to read 6, iclass 40, count 0 2006.285.22:59:58.88#ibcon#read 6, iclass 40, count 0 2006.285.22:59:58.88#ibcon#end of sib2, iclass 40, count 0 2006.285.22:59:58.88#ibcon#*mode == 0, iclass 40, count 0 2006.285.22:59:58.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.22:59:58.88#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.22:59:58.88#ibcon#*before write, iclass 40, count 0 2006.285.22:59:58.88#ibcon#enter sib2, iclass 40, count 0 2006.285.22:59:58.88#ibcon#flushed, iclass 40, count 0 2006.285.22:59:58.88#ibcon#about to write, iclass 40, count 0 2006.285.22:59:58.88#ibcon#wrote, iclass 40, count 0 2006.285.22:59:58.88#ibcon#about to read 3, iclass 40, count 0 2006.285.22:59:58.92#ibcon#read 3, iclass 40, count 0 2006.285.22:59:58.92#ibcon#about to read 4, iclass 40, count 0 2006.285.22:59:58.92#ibcon#read 4, iclass 40, count 0 2006.285.22:59:58.92#ibcon#about to read 5, iclass 40, count 0 2006.285.22:59:58.92#ibcon#read 5, iclass 40, count 0 2006.285.22:59:58.92#ibcon#about to read 6, iclass 40, count 0 2006.285.22:59:58.92#ibcon#read 6, iclass 40, count 0 2006.285.22:59:58.92#ibcon#end of sib2, iclass 40, count 0 2006.285.22:59:58.92#ibcon#*after write, iclass 40, count 0 2006.285.22:59:58.92#ibcon#*before return 0, iclass 40, count 0 2006.285.22:59:58.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:59:58.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.22:59:58.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.22:59:58.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.22:59:58.92$vck44/va=8,3 2006.285.22:59:58.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.22:59:58.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.22:59:58.92#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:58.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:59:58.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:59:58.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:59:58.98#ibcon#enter wrdev, iclass 4, count 2 2006.285.22:59:58.98#ibcon#first serial, iclass 4, count 2 2006.285.22:59:58.98#ibcon#enter sib2, iclass 4, count 2 2006.285.22:59:58.98#ibcon#flushed, iclass 4, count 2 2006.285.22:59:58.98#ibcon#about to write, iclass 4, count 2 2006.285.22:59:58.98#ibcon#wrote, iclass 4, count 2 2006.285.22:59:58.98#ibcon#about to read 3, iclass 4, count 2 2006.285.22:59:59.00#ibcon#read 3, iclass 4, count 2 2006.285.22:59:59.00#ibcon#about to read 4, iclass 4, count 2 2006.285.22:59:59.00#ibcon#read 4, iclass 4, count 2 2006.285.22:59:59.00#ibcon#about to read 5, iclass 4, count 2 2006.285.22:59:59.00#ibcon#read 5, iclass 4, count 2 2006.285.22:59:59.00#ibcon#about to read 6, iclass 4, count 2 2006.285.22:59:59.00#ibcon#read 6, iclass 4, count 2 2006.285.22:59:59.00#ibcon#end of sib2, iclass 4, count 2 2006.285.22:59:59.00#ibcon#*mode == 0, iclass 4, count 2 2006.285.22:59:59.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.22:59:59.00#ibcon#[25=AT08-03\r\n] 2006.285.22:59:59.00#ibcon#*before write, iclass 4, count 2 2006.285.22:59:59.00#ibcon#enter sib2, iclass 4, count 2 2006.285.22:59:59.00#ibcon#flushed, iclass 4, count 2 2006.285.22:59:59.00#ibcon#about to write, iclass 4, count 2 2006.285.22:59:59.00#ibcon#wrote, iclass 4, count 2 2006.285.22:59:59.00#ibcon#about to read 3, iclass 4, count 2 2006.285.22:59:59.03#ibcon#read 3, iclass 4, count 2 2006.285.22:59:59.03#ibcon#about to read 4, iclass 4, count 2 2006.285.22:59:59.03#ibcon#read 4, iclass 4, count 2 2006.285.22:59:59.03#ibcon#about to read 5, iclass 4, count 2 2006.285.22:59:59.03#ibcon#read 5, iclass 4, count 2 2006.285.22:59:59.03#ibcon#about to read 6, iclass 4, count 2 2006.285.22:59:59.03#ibcon#read 6, iclass 4, count 2 2006.285.22:59:59.03#ibcon#end of sib2, iclass 4, count 2 2006.285.22:59:59.03#ibcon#*after write, iclass 4, count 2 2006.285.22:59:59.03#ibcon#*before return 0, iclass 4, count 2 2006.285.22:59:59.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:59:59.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.22:59:59.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.22:59:59.03#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:59.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:59:59.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:59:59.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:59:59.15#ibcon#enter wrdev, iclass 4, count 0 2006.285.22:59:59.15#ibcon#first serial, iclass 4, count 0 2006.285.22:59:59.15#ibcon#enter sib2, iclass 4, count 0 2006.285.22:59:59.15#ibcon#flushed, iclass 4, count 0 2006.285.22:59:59.15#ibcon#about to write, iclass 4, count 0 2006.285.22:59:59.15#ibcon#wrote, iclass 4, count 0 2006.285.22:59:59.15#ibcon#about to read 3, iclass 4, count 0 2006.285.22:59:59.17#ibcon#read 3, iclass 4, count 0 2006.285.22:59:59.17#ibcon#about to read 4, iclass 4, count 0 2006.285.22:59:59.17#ibcon#read 4, iclass 4, count 0 2006.285.22:59:59.17#ibcon#about to read 5, iclass 4, count 0 2006.285.22:59:59.17#ibcon#read 5, iclass 4, count 0 2006.285.22:59:59.17#ibcon#about to read 6, iclass 4, count 0 2006.285.22:59:59.17#ibcon#read 6, iclass 4, count 0 2006.285.22:59:59.17#ibcon#end of sib2, iclass 4, count 0 2006.285.22:59:59.17#ibcon#*mode == 0, iclass 4, count 0 2006.285.22:59:59.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.22:59:59.17#ibcon#[25=USB\r\n] 2006.285.22:59:59.17#ibcon#*before write, iclass 4, count 0 2006.285.22:59:59.17#ibcon#enter sib2, iclass 4, count 0 2006.285.22:59:59.17#ibcon#flushed, iclass 4, count 0 2006.285.22:59:59.17#ibcon#about to write, iclass 4, count 0 2006.285.22:59:59.17#ibcon#wrote, iclass 4, count 0 2006.285.22:59:59.17#ibcon#about to read 3, iclass 4, count 0 2006.285.22:59:59.20#ibcon#read 3, iclass 4, count 0 2006.285.22:59:59.20#ibcon#about to read 4, iclass 4, count 0 2006.285.22:59:59.20#ibcon#read 4, iclass 4, count 0 2006.285.22:59:59.20#ibcon#about to read 5, iclass 4, count 0 2006.285.22:59:59.20#ibcon#read 5, iclass 4, count 0 2006.285.22:59:59.20#ibcon#about to read 6, iclass 4, count 0 2006.285.22:59:59.20#ibcon#read 6, iclass 4, count 0 2006.285.22:59:59.20#ibcon#end of sib2, iclass 4, count 0 2006.285.22:59:59.20#ibcon#*after write, iclass 4, count 0 2006.285.22:59:59.20#ibcon#*before return 0, iclass 4, count 0 2006.285.22:59:59.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:59:59.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.22:59:59.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.22:59:59.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.22:59:59.20$vck44/vblo=1,629.99 2006.285.22:59:59.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.22:59:59.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.22:59:59.20#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:59.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:59:59.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:59:59.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:59:59.20#ibcon#enter wrdev, iclass 6, count 0 2006.285.22:59:59.20#ibcon#first serial, iclass 6, count 0 2006.285.22:59:59.20#ibcon#enter sib2, iclass 6, count 0 2006.285.22:59:59.20#ibcon#flushed, iclass 6, count 0 2006.285.22:59:59.20#ibcon#about to write, iclass 6, count 0 2006.285.22:59:59.20#ibcon#wrote, iclass 6, count 0 2006.285.22:59:59.20#ibcon#about to read 3, iclass 6, count 0 2006.285.22:59:59.22#ibcon#read 3, iclass 6, count 0 2006.285.22:59:59.22#ibcon#about to read 4, iclass 6, count 0 2006.285.22:59:59.22#ibcon#read 4, iclass 6, count 0 2006.285.22:59:59.22#ibcon#about to read 5, iclass 6, count 0 2006.285.22:59:59.22#ibcon#read 5, iclass 6, count 0 2006.285.22:59:59.22#ibcon#about to read 6, iclass 6, count 0 2006.285.22:59:59.22#ibcon#read 6, iclass 6, count 0 2006.285.22:59:59.22#ibcon#end of sib2, iclass 6, count 0 2006.285.22:59:59.22#ibcon#*mode == 0, iclass 6, count 0 2006.285.22:59:59.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.22:59:59.22#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.22:59:59.22#ibcon#*before write, iclass 6, count 0 2006.285.22:59:59.22#ibcon#enter sib2, iclass 6, count 0 2006.285.22:59:59.22#ibcon#flushed, iclass 6, count 0 2006.285.22:59:59.22#ibcon#about to write, iclass 6, count 0 2006.285.22:59:59.22#ibcon#wrote, iclass 6, count 0 2006.285.22:59:59.22#ibcon#about to read 3, iclass 6, count 0 2006.285.22:59:59.26#ibcon#read 3, iclass 6, count 0 2006.285.22:59:59.26#ibcon#about to read 4, iclass 6, count 0 2006.285.22:59:59.26#ibcon#read 4, iclass 6, count 0 2006.285.22:59:59.26#ibcon#about to read 5, iclass 6, count 0 2006.285.22:59:59.26#ibcon#read 5, iclass 6, count 0 2006.285.22:59:59.26#ibcon#about to read 6, iclass 6, count 0 2006.285.22:59:59.26#ibcon#read 6, iclass 6, count 0 2006.285.22:59:59.26#ibcon#end of sib2, iclass 6, count 0 2006.285.22:59:59.26#ibcon#*after write, iclass 6, count 0 2006.285.22:59:59.26#ibcon#*before return 0, iclass 6, count 0 2006.285.22:59:59.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:59:59.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.22:59:59.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.22:59:59.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.22:59:59.26$vck44/vb=1,4 2006.285.22:59:59.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.22:59:59.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.22:59:59.26#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:59.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:59:59.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:59:59.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:59:59.26#ibcon#enter wrdev, iclass 10, count 2 2006.285.22:59:59.26#ibcon#first serial, iclass 10, count 2 2006.285.22:59:59.26#ibcon#enter sib2, iclass 10, count 2 2006.285.22:59:59.26#ibcon#flushed, iclass 10, count 2 2006.285.22:59:59.26#ibcon#about to write, iclass 10, count 2 2006.285.22:59:59.26#ibcon#wrote, iclass 10, count 2 2006.285.22:59:59.26#ibcon#about to read 3, iclass 10, count 2 2006.285.22:59:59.28#ibcon#read 3, iclass 10, count 2 2006.285.22:59:59.28#ibcon#about to read 4, iclass 10, count 2 2006.285.22:59:59.28#ibcon#read 4, iclass 10, count 2 2006.285.22:59:59.28#ibcon#about to read 5, iclass 10, count 2 2006.285.22:59:59.28#ibcon#read 5, iclass 10, count 2 2006.285.22:59:59.28#ibcon#about to read 6, iclass 10, count 2 2006.285.22:59:59.28#ibcon#read 6, iclass 10, count 2 2006.285.22:59:59.28#ibcon#end of sib2, iclass 10, count 2 2006.285.22:59:59.28#ibcon#*mode == 0, iclass 10, count 2 2006.285.22:59:59.28#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.22:59:59.28#ibcon#[27=AT01-04\r\n] 2006.285.22:59:59.28#ibcon#*before write, iclass 10, count 2 2006.285.22:59:59.28#ibcon#enter sib2, iclass 10, count 2 2006.285.22:59:59.28#ibcon#flushed, iclass 10, count 2 2006.285.22:59:59.28#ibcon#about to write, iclass 10, count 2 2006.285.22:59:59.28#ibcon#wrote, iclass 10, count 2 2006.285.22:59:59.28#ibcon#about to read 3, iclass 10, count 2 2006.285.22:59:59.31#ibcon#read 3, iclass 10, count 2 2006.285.22:59:59.31#ibcon#about to read 4, iclass 10, count 2 2006.285.22:59:59.31#ibcon#read 4, iclass 10, count 2 2006.285.22:59:59.31#ibcon#about to read 5, iclass 10, count 2 2006.285.22:59:59.31#ibcon#read 5, iclass 10, count 2 2006.285.22:59:59.31#ibcon#about to read 6, iclass 10, count 2 2006.285.22:59:59.31#ibcon#read 6, iclass 10, count 2 2006.285.22:59:59.31#ibcon#end of sib2, iclass 10, count 2 2006.285.22:59:59.31#ibcon#*after write, iclass 10, count 2 2006.285.22:59:59.31#ibcon#*before return 0, iclass 10, count 2 2006.285.22:59:59.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:59:59.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.22:59:59.31#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.22:59:59.31#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:59.31#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:59:59.43#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:59:59.43#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:59:59.43#ibcon#enter wrdev, iclass 10, count 0 2006.285.22:59:59.43#ibcon#first serial, iclass 10, count 0 2006.285.22:59:59.43#ibcon#enter sib2, iclass 10, count 0 2006.285.22:59:59.43#ibcon#flushed, iclass 10, count 0 2006.285.22:59:59.43#ibcon#about to write, iclass 10, count 0 2006.285.22:59:59.43#ibcon#wrote, iclass 10, count 0 2006.285.22:59:59.43#ibcon#about to read 3, iclass 10, count 0 2006.285.22:59:59.45#ibcon#read 3, iclass 10, count 0 2006.285.22:59:59.45#ibcon#about to read 4, iclass 10, count 0 2006.285.22:59:59.45#ibcon#read 4, iclass 10, count 0 2006.285.22:59:59.45#ibcon#about to read 5, iclass 10, count 0 2006.285.22:59:59.45#ibcon#read 5, iclass 10, count 0 2006.285.22:59:59.45#ibcon#about to read 6, iclass 10, count 0 2006.285.22:59:59.45#ibcon#read 6, iclass 10, count 0 2006.285.22:59:59.45#ibcon#end of sib2, iclass 10, count 0 2006.285.22:59:59.45#ibcon#*mode == 0, iclass 10, count 0 2006.285.22:59:59.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.22:59:59.45#ibcon#[27=USB\r\n] 2006.285.22:59:59.45#ibcon#*before write, iclass 10, count 0 2006.285.22:59:59.45#ibcon#enter sib2, iclass 10, count 0 2006.285.22:59:59.45#ibcon#flushed, iclass 10, count 0 2006.285.22:59:59.45#ibcon#about to write, iclass 10, count 0 2006.285.22:59:59.45#ibcon#wrote, iclass 10, count 0 2006.285.22:59:59.45#ibcon#about to read 3, iclass 10, count 0 2006.285.22:59:59.48#ibcon#read 3, iclass 10, count 0 2006.285.22:59:59.48#ibcon#about to read 4, iclass 10, count 0 2006.285.22:59:59.48#ibcon#read 4, iclass 10, count 0 2006.285.22:59:59.48#ibcon#about to read 5, iclass 10, count 0 2006.285.22:59:59.48#ibcon#read 5, iclass 10, count 0 2006.285.22:59:59.48#ibcon#about to read 6, iclass 10, count 0 2006.285.22:59:59.48#ibcon#read 6, iclass 10, count 0 2006.285.22:59:59.48#ibcon#end of sib2, iclass 10, count 0 2006.285.22:59:59.48#ibcon#*after write, iclass 10, count 0 2006.285.22:59:59.48#ibcon#*before return 0, iclass 10, count 0 2006.285.22:59:59.48#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:59:59.48#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.22:59:59.48#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.22:59:59.48#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.22:59:59.48$vck44/vblo=2,634.99 2006.285.22:59:59.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.22:59:59.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.22:59:59.48#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:59.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:59:59.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:59:59.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:59:59.48#ibcon#enter wrdev, iclass 12, count 0 2006.285.22:59:59.48#ibcon#first serial, iclass 12, count 0 2006.285.22:59:59.48#ibcon#enter sib2, iclass 12, count 0 2006.285.22:59:59.48#ibcon#flushed, iclass 12, count 0 2006.285.22:59:59.48#ibcon#about to write, iclass 12, count 0 2006.285.22:59:59.48#ibcon#wrote, iclass 12, count 0 2006.285.22:59:59.48#ibcon#about to read 3, iclass 12, count 0 2006.285.22:59:59.50#ibcon#read 3, iclass 12, count 0 2006.285.22:59:59.50#ibcon#about to read 4, iclass 12, count 0 2006.285.22:59:59.50#ibcon#read 4, iclass 12, count 0 2006.285.22:59:59.50#ibcon#about to read 5, iclass 12, count 0 2006.285.22:59:59.50#ibcon#read 5, iclass 12, count 0 2006.285.22:59:59.50#ibcon#about to read 6, iclass 12, count 0 2006.285.22:59:59.50#ibcon#read 6, iclass 12, count 0 2006.285.22:59:59.50#ibcon#end of sib2, iclass 12, count 0 2006.285.22:59:59.50#ibcon#*mode == 0, iclass 12, count 0 2006.285.22:59:59.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.22:59:59.50#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.22:59:59.50#ibcon#*before write, iclass 12, count 0 2006.285.22:59:59.50#ibcon#enter sib2, iclass 12, count 0 2006.285.22:59:59.50#ibcon#flushed, iclass 12, count 0 2006.285.22:59:59.50#ibcon#about to write, iclass 12, count 0 2006.285.22:59:59.50#ibcon#wrote, iclass 12, count 0 2006.285.22:59:59.50#ibcon#about to read 3, iclass 12, count 0 2006.285.22:59:59.54#ibcon#read 3, iclass 12, count 0 2006.285.22:59:59.54#ibcon#about to read 4, iclass 12, count 0 2006.285.22:59:59.54#ibcon#read 4, iclass 12, count 0 2006.285.22:59:59.54#ibcon#about to read 5, iclass 12, count 0 2006.285.22:59:59.54#ibcon#read 5, iclass 12, count 0 2006.285.22:59:59.54#ibcon#about to read 6, iclass 12, count 0 2006.285.22:59:59.54#ibcon#read 6, iclass 12, count 0 2006.285.22:59:59.54#ibcon#end of sib2, iclass 12, count 0 2006.285.22:59:59.54#ibcon#*after write, iclass 12, count 0 2006.285.22:59:59.54#ibcon#*before return 0, iclass 12, count 0 2006.285.22:59:59.54#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:59:59.54#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.22:59:59.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.22:59:59.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.22:59:59.54$vck44/vb=2,5 2006.285.22:59:59.54#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.22:59:59.54#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.22:59:59.54#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:59.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:59:59.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:59:59.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:59:59.60#ibcon#enter wrdev, iclass 14, count 2 2006.285.22:59:59.60#ibcon#first serial, iclass 14, count 2 2006.285.22:59:59.60#ibcon#enter sib2, iclass 14, count 2 2006.285.22:59:59.60#ibcon#flushed, iclass 14, count 2 2006.285.22:59:59.60#ibcon#about to write, iclass 14, count 2 2006.285.22:59:59.60#ibcon#wrote, iclass 14, count 2 2006.285.22:59:59.60#ibcon#about to read 3, iclass 14, count 2 2006.285.22:59:59.62#ibcon#read 3, iclass 14, count 2 2006.285.22:59:59.62#ibcon#about to read 4, iclass 14, count 2 2006.285.22:59:59.62#ibcon#read 4, iclass 14, count 2 2006.285.22:59:59.62#ibcon#about to read 5, iclass 14, count 2 2006.285.22:59:59.62#ibcon#read 5, iclass 14, count 2 2006.285.22:59:59.62#ibcon#about to read 6, iclass 14, count 2 2006.285.22:59:59.62#ibcon#read 6, iclass 14, count 2 2006.285.22:59:59.62#ibcon#end of sib2, iclass 14, count 2 2006.285.22:59:59.62#ibcon#*mode == 0, iclass 14, count 2 2006.285.22:59:59.62#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.22:59:59.62#ibcon#[27=AT02-05\r\n] 2006.285.22:59:59.62#ibcon#*before write, iclass 14, count 2 2006.285.22:59:59.62#ibcon#enter sib2, iclass 14, count 2 2006.285.22:59:59.62#ibcon#flushed, iclass 14, count 2 2006.285.22:59:59.62#ibcon#about to write, iclass 14, count 2 2006.285.22:59:59.62#ibcon#wrote, iclass 14, count 2 2006.285.22:59:59.62#ibcon#about to read 3, iclass 14, count 2 2006.285.22:59:59.65#ibcon#read 3, iclass 14, count 2 2006.285.22:59:59.65#ibcon#about to read 4, iclass 14, count 2 2006.285.22:59:59.65#ibcon#read 4, iclass 14, count 2 2006.285.22:59:59.65#ibcon#about to read 5, iclass 14, count 2 2006.285.22:59:59.65#ibcon#read 5, iclass 14, count 2 2006.285.22:59:59.65#ibcon#about to read 6, iclass 14, count 2 2006.285.22:59:59.65#ibcon#read 6, iclass 14, count 2 2006.285.22:59:59.65#ibcon#end of sib2, iclass 14, count 2 2006.285.22:59:59.65#ibcon#*after write, iclass 14, count 2 2006.285.22:59:59.65#ibcon#*before return 0, iclass 14, count 2 2006.285.22:59:59.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:59:59.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.22:59:59.65#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.22:59:59.65#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:59.65#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:59:59.77#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:59:59.77#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:59:59.77#ibcon#enter wrdev, iclass 14, count 0 2006.285.22:59:59.77#ibcon#first serial, iclass 14, count 0 2006.285.22:59:59.77#ibcon#enter sib2, iclass 14, count 0 2006.285.22:59:59.77#ibcon#flushed, iclass 14, count 0 2006.285.22:59:59.77#ibcon#about to write, iclass 14, count 0 2006.285.22:59:59.77#ibcon#wrote, iclass 14, count 0 2006.285.22:59:59.77#ibcon#about to read 3, iclass 14, count 0 2006.285.22:59:59.79#ibcon#read 3, iclass 14, count 0 2006.285.22:59:59.79#ibcon#about to read 4, iclass 14, count 0 2006.285.22:59:59.79#ibcon#read 4, iclass 14, count 0 2006.285.22:59:59.79#ibcon#about to read 5, iclass 14, count 0 2006.285.22:59:59.79#ibcon#read 5, iclass 14, count 0 2006.285.22:59:59.79#ibcon#about to read 6, iclass 14, count 0 2006.285.22:59:59.79#ibcon#read 6, iclass 14, count 0 2006.285.22:59:59.79#ibcon#end of sib2, iclass 14, count 0 2006.285.22:59:59.79#ibcon#*mode == 0, iclass 14, count 0 2006.285.22:59:59.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.22:59:59.79#ibcon#[27=USB\r\n] 2006.285.22:59:59.79#ibcon#*before write, iclass 14, count 0 2006.285.22:59:59.79#ibcon#enter sib2, iclass 14, count 0 2006.285.22:59:59.79#ibcon#flushed, iclass 14, count 0 2006.285.22:59:59.79#ibcon#about to write, iclass 14, count 0 2006.285.22:59:59.79#ibcon#wrote, iclass 14, count 0 2006.285.22:59:59.79#ibcon#about to read 3, iclass 14, count 0 2006.285.22:59:59.82#ibcon#read 3, iclass 14, count 0 2006.285.22:59:59.82#ibcon#about to read 4, iclass 14, count 0 2006.285.22:59:59.82#ibcon#read 4, iclass 14, count 0 2006.285.22:59:59.82#ibcon#about to read 5, iclass 14, count 0 2006.285.22:59:59.82#ibcon#read 5, iclass 14, count 0 2006.285.22:59:59.82#ibcon#about to read 6, iclass 14, count 0 2006.285.22:59:59.82#ibcon#read 6, iclass 14, count 0 2006.285.22:59:59.82#ibcon#end of sib2, iclass 14, count 0 2006.285.22:59:59.82#ibcon#*after write, iclass 14, count 0 2006.285.22:59:59.82#ibcon#*before return 0, iclass 14, count 0 2006.285.22:59:59.82#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:59:59.82#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.22:59:59.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.22:59:59.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.22:59:59.82$vck44/vblo=3,649.99 2006.285.22:59:59.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.22:59:59.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.22:59:59.82#ibcon#ireg 17 cls_cnt 0 2006.285.22:59:59.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:59:59.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:59:59.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:59:59.82#ibcon#enter wrdev, iclass 16, count 0 2006.285.22:59:59.82#ibcon#first serial, iclass 16, count 0 2006.285.22:59:59.82#ibcon#enter sib2, iclass 16, count 0 2006.285.22:59:59.82#ibcon#flushed, iclass 16, count 0 2006.285.22:59:59.82#ibcon#about to write, iclass 16, count 0 2006.285.22:59:59.82#ibcon#wrote, iclass 16, count 0 2006.285.22:59:59.82#ibcon#about to read 3, iclass 16, count 0 2006.285.22:59:59.84#ibcon#read 3, iclass 16, count 0 2006.285.22:59:59.84#ibcon#about to read 4, iclass 16, count 0 2006.285.22:59:59.84#ibcon#read 4, iclass 16, count 0 2006.285.22:59:59.84#ibcon#about to read 5, iclass 16, count 0 2006.285.22:59:59.84#ibcon#read 5, iclass 16, count 0 2006.285.22:59:59.84#ibcon#about to read 6, iclass 16, count 0 2006.285.22:59:59.84#ibcon#read 6, iclass 16, count 0 2006.285.22:59:59.84#ibcon#end of sib2, iclass 16, count 0 2006.285.22:59:59.84#ibcon#*mode == 0, iclass 16, count 0 2006.285.22:59:59.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.22:59:59.84#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.22:59:59.84#ibcon#*before write, iclass 16, count 0 2006.285.22:59:59.84#ibcon#enter sib2, iclass 16, count 0 2006.285.22:59:59.84#ibcon#flushed, iclass 16, count 0 2006.285.22:59:59.84#ibcon#about to write, iclass 16, count 0 2006.285.22:59:59.84#ibcon#wrote, iclass 16, count 0 2006.285.22:59:59.84#ibcon#about to read 3, iclass 16, count 0 2006.285.22:59:59.88#ibcon#read 3, iclass 16, count 0 2006.285.22:59:59.88#ibcon#about to read 4, iclass 16, count 0 2006.285.22:59:59.88#ibcon#read 4, iclass 16, count 0 2006.285.22:59:59.88#ibcon#about to read 5, iclass 16, count 0 2006.285.22:59:59.88#ibcon#read 5, iclass 16, count 0 2006.285.22:59:59.88#ibcon#about to read 6, iclass 16, count 0 2006.285.22:59:59.88#ibcon#read 6, iclass 16, count 0 2006.285.22:59:59.88#ibcon#end of sib2, iclass 16, count 0 2006.285.22:59:59.88#ibcon#*after write, iclass 16, count 0 2006.285.22:59:59.88#ibcon#*before return 0, iclass 16, count 0 2006.285.22:59:59.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:59:59.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.22:59:59.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.22:59:59.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.22:59:59.88$vck44/vb=3,4 2006.285.22:59:59.88#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.22:59:59.88#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.22:59:59.88#ibcon#ireg 11 cls_cnt 2 2006.285.22:59:59.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:59:59.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:59:59.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:59:59.94#ibcon#enter wrdev, iclass 18, count 2 2006.285.22:59:59.94#ibcon#first serial, iclass 18, count 2 2006.285.22:59:59.94#ibcon#enter sib2, iclass 18, count 2 2006.285.22:59:59.94#ibcon#flushed, iclass 18, count 2 2006.285.22:59:59.94#ibcon#about to write, iclass 18, count 2 2006.285.22:59:59.94#ibcon#wrote, iclass 18, count 2 2006.285.22:59:59.94#ibcon#about to read 3, iclass 18, count 2 2006.285.22:59:59.96#ibcon#read 3, iclass 18, count 2 2006.285.22:59:59.96#ibcon#about to read 4, iclass 18, count 2 2006.285.22:59:59.96#ibcon#read 4, iclass 18, count 2 2006.285.22:59:59.96#ibcon#about to read 5, iclass 18, count 2 2006.285.22:59:59.96#ibcon#read 5, iclass 18, count 2 2006.285.22:59:59.96#ibcon#about to read 6, iclass 18, count 2 2006.285.22:59:59.96#ibcon#read 6, iclass 18, count 2 2006.285.22:59:59.96#ibcon#end of sib2, iclass 18, count 2 2006.285.22:59:59.96#ibcon#*mode == 0, iclass 18, count 2 2006.285.22:59:59.96#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.22:59:59.96#ibcon#[27=AT03-04\r\n] 2006.285.22:59:59.96#ibcon#*before write, iclass 18, count 2 2006.285.22:59:59.96#ibcon#enter sib2, iclass 18, count 2 2006.285.22:59:59.96#ibcon#flushed, iclass 18, count 2 2006.285.22:59:59.96#ibcon#about to write, iclass 18, count 2 2006.285.22:59:59.96#ibcon#wrote, iclass 18, count 2 2006.285.22:59:59.96#ibcon#about to read 3, iclass 18, count 2 2006.285.22:59:59.99#ibcon#read 3, iclass 18, count 2 2006.285.22:59:59.99#ibcon#about to read 4, iclass 18, count 2 2006.285.22:59:59.99#ibcon#read 4, iclass 18, count 2 2006.285.22:59:59.99#ibcon#about to read 5, iclass 18, count 2 2006.285.22:59:59.99#ibcon#read 5, iclass 18, count 2 2006.285.22:59:59.99#ibcon#about to read 6, iclass 18, count 2 2006.285.22:59:59.99#ibcon#read 6, iclass 18, count 2 2006.285.22:59:59.99#ibcon#end of sib2, iclass 18, count 2 2006.285.22:59:59.99#ibcon#*after write, iclass 18, count 2 2006.285.22:59:59.99#ibcon#*before return 0, iclass 18, count 2 2006.285.22:59:59.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:59:59.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.22:59:59.99#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.22:59:59.99#ibcon#ireg 7 cls_cnt 0 2006.285.22:59:59.99#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:00:00.11#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:00:00.11#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:00:00.11#ibcon#enter wrdev, iclass 18, count 0 2006.285.23:00:00.11#ibcon#first serial, iclass 18, count 0 2006.285.23:00:00.11#ibcon#enter sib2, iclass 18, count 0 2006.285.23:00:00.11#ibcon#flushed, iclass 18, count 0 2006.285.23:00:00.11#ibcon#about to write, iclass 18, count 0 2006.285.23:00:00.11#ibcon#wrote, iclass 18, count 0 2006.285.23:00:00.11#ibcon#about to read 3, iclass 18, count 0 2006.285.23:00:00.13#ibcon#read 3, iclass 18, count 0 2006.285.23:00:00.13#ibcon#about to read 4, iclass 18, count 0 2006.285.23:00:00.13#ibcon#read 4, iclass 18, count 0 2006.285.23:00:00.13#ibcon#about to read 5, iclass 18, count 0 2006.285.23:00:00.13#ibcon#read 5, iclass 18, count 0 2006.285.23:00:00.13#ibcon#about to read 6, iclass 18, count 0 2006.285.23:00:00.13#ibcon#read 6, iclass 18, count 0 2006.285.23:00:00.13#ibcon#end of sib2, iclass 18, count 0 2006.285.23:00:00.13#ibcon#*mode == 0, iclass 18, count 0 2006.285.23:00:00.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.23:00:00.13#ibcon#[27=USB\r\n] 2006.285.23:00:00.13#ibcon#*before write, iclass 18, count 0 2006.285.23:00:00.13#ibcon#enter sib2, iclass 18, count 0 2006.285.23:00:00.13#ibcon#flushed, iclass 18, count 0 2006.285.23:00:00.13#ibcon#about to write, iclass 18, count 0 2006.285.23:00:00.13#ibcon#wrote, iclass 18, count 0 2006.285.23:00:00.13#ibcon#about to read 3, iclass 18, count 0 2006.285.23:00:00.16#ibcon#read 3, iclass 18, count 0 2006.285.23:00:00.16#ibcon#about to read 4, iclass 18, count 0 2006.285.23:00:00.16#ibcon#read 4, iclass 18, count 0 2006.285.23:00:00.16#ibcon#about to read 5, iclass 18, count 0 2006.285.23:00:00.16#ibcon#read 5, iclass 18, count 0 2006.285.23:00:00.16#ibcon#about to read 6, iclass 18, count 0 2006.285.23:00:00.16#ibcon#read 6, iclass 18, count 0 2006.285.23:00:00.16#ibcon#end of sib2, iclass 18, count 0 2006.285.23:00:00.16#ibcon#*after write, iclass 18, count 0 2006.285.23:00:00.16#ibcon#*before return 0, iclass 18, count 0 2006.285.23:00:00.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:00:00.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:00:00.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.23:00:00.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.23:00:00.16$vck44/vblo=4,679.99 2006.285.23:00:00.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.23:00:00.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.23:00:00.16#ibcon#ireg 17 cls_cnt 0 2006.285.23:00:00.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:00:00.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:00:00.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:00:00.16#ibcon#enter wrdev, iclass 20, count 0 2006.285.23:00:00.16#ibcon#first serial, iclass 20, count 0 2006.285.23:00:00.16#ibcon#enter sib2, iclass 20, count 0 2006.285.23:00:00.16#ibcon#flushed, iclass 20, count 0 2006.285.23:00:00.16#ibcon#about to write, iclass 20, count 0 2006.285.23:00:00.16#ibcon#wrote, iclass 20, count 0 2006.285.23:00:00.16#ibcon#about to read 3, iclass 20, count 0 2006.285.23:00:00.18#ibcon#read 3, iclass 20, count 0 2006.285.23:00:00.18#ibcon#about to read 4, iclass 20, count 0 2006.285.23:00:00.18#ibcon#read 4, iclass 20, count 0 2006.285.23:00:00.18#ibcon#about to read 5, iclass 20, count 0 2006.285.23:00:00.18#ibcon#read 5, iclass 20, count 0 2006.285.23:00:00.18#ibcon#about to read 6, iclass 20, count 0 2006.285.23:00:00.18#ibcon#read 6, iclass 20, count 0 2006.285.23:00:00.18#ibcon#end of sib2, iclass 20, count 0 2006.285.23:00:00.18#ibcon#*mode == 0, iclass 20, count 0 2006.285.23:00:00.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.23:00:00.18#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:00:00.18#ibcon#*before write, iclass 20, count 0 2006.285.23:00:00.18#ibcon#enter sib2, iclass 20, count 0 2006.285.23:00:00.18#ibcon#flushed, iclass 20, count 0 2006.285.23:00:00.18#ibcon#about to write, iclass 20, count 0 2006.285.23:00:00.18#ibcon#wrote, iclass 20, count 0 2006.285.23:00:00.18#ibcon#about to read 3, iclass 20, count 0 2006.285.23:00:00.22#ibcon#read 3, iclass 20, count 0 2006.285.23:00:00.22#ibcon#about to read 4, iclass 20, count 0 2006.285.23:00:00.22#ibcon#read 4, iclass 20, count 0 2006.285.23:00:00.22#ibcon#about to read 5, iclass 20, count 0 2006.285.23:00:00.22#ibcon#read 5, iclass 20, count 0 2006.285.23:00:00.22#ibcon#about to read 6, iclass 20, count 0 2006.285.23:00:00.22#ibcon#read 6, iclass 20, count 0 2006.285.23:00:00.22#ibcon#end of sib2, iclass 20, count 0 2006.285.23:00:00.22#ibcon#*after write, iclass 20, count 0 2006.285.23:00:00.22#ibcon#*before return 0, iclass 20, count 0 2006.285.23:00:00.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:00:00.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:00:00.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.23:00:00.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.23:00:00.22$vck44/vb=4,5 2006.285.23:00:00.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.23:00:00.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.23:00:00.22#ibcon#ireg 11 cls_cnt 2 2006.285.23:00:00.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:00:00.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:00:00.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:00:00.28#ibcon#enter wrdev, iclass 22, count 2 2006.285.23:00:00.28#ibcon#first serial, iclass 22, count 2 2006.285.23:00:00.28#ibcon#enter sib2, iclass 22, count 2 2006.285.23:00:00.28#ibcon#flushed, iclass 22, count 2 2006.285.23:00:00.28#ibcon#about to write, iclass 22, count 2 2006.285.23:00:00.28#ibcon#wrote, iclass 22, count 2 2006.285.23:00:00.28#ibcon#about to read 3, iclass 22, count 2 2006.285.23:00:00.30#ibcon#read 3, iclass 22, count 2 2006.285.23:00:00.30#ibcon#about to read 4, iclass 22, count 2 2006.285.23:00:00.30#ibcon#read 4, iclass 22, count 2 2006.285.23:00:00.30#ibcon#about to read 5, iclass 22, count 2 2006.285.23:00:00.30#ibcon#read 5, iclass 22, count 2 2006.285.23:00:00.30#ibcon#about to read 6, iclass 22, count 2 2006.285.23:00:00.30#ibcon#read 6, iclass 22, count 2 2006.285.23:00:00.30#ibcon#end of sib2, iclass 22, count 2 2006.285.23:00:00.30#ibcon#*mode == 0, iclass 22, count 2 2006.285.23:00:00.30#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.23:00:00.30#ibcon#[27=AT04-05\r\n] 2006.285.23:00:00.30#ibcon#*before write, iclass 22, count 2 2006.285.23:00:00.30#ibcon#enter sib2, iclass 22, count 2 2006.285.23:00:00.30#ibcon#flushed, iclass 22, count 2 2006.285.23:00:00.30#ibcon#about to write, iclass 22, count 2 2006.285.23:00:00.30#ibcon#wrote, iclass 22, count 2 2006.285.23:00:00.30#ibcon#about to read 3, iclass 22, count 2 2006.285.23:00:00.33#ibcon#read 3, iclass 22, count 2 2006.285.23:00:00.33#ibcon#about to read 4, iclass 22, count 2 2006.285.23:00:00.33#ibcon#read 4, iclass 22, count 2 2006.285.23:00:00.33#ibcon#about to read 5, iclass 22, count 2 2006.285.23:00:00.33#ibcon#read 5, iclass 22, count 2 2006.285.23:00:00.33#ibcon#about to read 6, iclass 22, count 2 2006.285.23:00:00.33#ibcon#read 6, iclass 22, count 2 2006.285.23:00:00.33#ibcon#end of sib2, iclass 22, count 2 2006.285.23:00:00.33#ibcon#*after write, iclass 22, count 2 2006.285.23:00:00.33#ibcon#*before return 0, iclass 22, count 2 2006.285.23:00:00.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:00:00.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:00:00.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.23:00:00.33#ibcon#ireg 7 cls_cnt 0 2006.285.23:00:00.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:00:00.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:00:00.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:00:00.45#ibcon#enter wrdev, iclass 22, count 0 2006.285.23:00:00.45#ibcon#first serial, iclass 22, count 0 2006.285.23:00:00.45#ibcon#enter sib2, iclass 22, count 0 2006.285.23:00:00.45#ibcon#flushed, iclass 22, count 0 2006.285.23:00:00.45#ibcon#about to write, iclass 22, count 0 2006.285.23:00:00.45#ibcon#wrote, iclass 22, count 0 2006.285.23:00:00.45#ibcon#about to read 3, iclass 22, count 0 2006.285.23:00:00.47#ibcon#read 3, iclass 22, count 0 2006.285.23:00:00.47#ibcon#about to read 4, iclass 22, count 0 2006.285.23:00:00.47#ibcon#read 4, iclass 22, count 0 2006.285.23:00:00.47#ibcon#about to read 5, iclass 22, count 0 2006.285.23:00:00.47#ibcon#read 5, iclass 22, count 0 2006.285.23:00:00.47#ibcon#about to read 6, iclass 22, count 0 2006.285.23:00:00.47#ibcon#read 6, iclass 22, count 0 2006.285.23:00:00.47#ibcon#end of sib2, iclass 22, count 0 2006.285.23:00:00.47#ibcon#*mode == 0, iclass 22, count 0 2006.285.23:00:00.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.23:00:00.47#ibcon#[27=USB\r\n] 2006.285.23:00:00.47#ibcon#*before write, iclass 22, count 0 2006.285.23:00:00.47#ibcon#enter sib2, iclass 22, count 0 2006.285.23:00:00.47#ibcon#flushed, iclass 22, count 0 2006.285.23:00:00.47#ibcon#about to write, iclass 22, count 0 2006.285.23:00:00.47#ibcon#wrote, iclass 22, count 0 2006.285.23:00:00.47#ibcon#about to read 3, iclass 22, count 0 2006.285.23:00:00.50#ibcon#read 3, iclass 22, count 0 2006.285.23:00:00.50#ibcon#about to read 4, iclass 22, count 0 2006.285.23:00:00.50#ibcon#read 4, iclass 22, count 0 2006.285.23:00:00.50#ibcon#about to read 5, iclass 22, count 0 2006.285.23:00:00.50#ibcon#read 5, iclass 22, count 0 2006.285.23:00:00.50#ibcon#about to read 6, iclass 22, count 0 2006.285.23:00:00.50#ibcon#read 6, iclass 22, count 0 2006.285.23:00:00.50#ibcon#end of sib2, iclass 22, count 0 2006.285.23:00:00.50#ibcon#*after write, iclass 22, count 0 2006.285.23:00:00.50#ibcon#*before return 0, iclass 22, count 0 2006.285.23:00:00.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:00:00.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:00:00.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.23:00:00.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.23:00:00.50$vck44/vblo=5,709.99 2006.285.23:00:00.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.23:00:00.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.23:00:00.50#ibcon#ireg 17 cls_cnt 0 2006.285.23:00:00.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:00:00.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:00:00.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:00:00.50#ibcon#enter wrdev, iclass 24, count 0 2006.285.23:00:00.50#ibcon#first serial, iclass 24, count 0 2006.285.23:00:00.50#ibcon#enter sib2, iclass 24, count 0 2006.285.23:00:00.50#ibcon#flushed, iclass 24, count 0 2006.285.23:00:00.50#ibcon#about to write, iclass 24, count 0 2006.285.23:00:00.50#ibcon#wrote, iclass 24, count 0 2006.285.23:00:00.50#ibcon#about to read 3, iclass 24, count 0 2006.285.23:00:00.52#ibcon#read 3, iclass 24, count 0 2006.285.23:00:00.52#ibcon#about to read 4, iclass 24, count 0 2006.285.23:00:00.52#ibcon#read 4, iclass 24, count 0 2006.285.23:00:00.52#ibcon#about to read 5, iclass 24, count 0 2006.285.23:00:00.52#ibcon#read 5, iclass 24, count 0 2006.285.23:00:00.52#ibcon#about to read 6, iclass 24, count 0 2006.285.23:00:00.52#ibcon#read 6, iclass 24, count 0 2006.285.23:00:00.52#ibcon#end of sib2, iclass 24, count 0 2006.285.23:00:00.52#ibcon#*mode == 0, iclass 24, count 0 2006.285.23:00:00.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.23:00:00.52#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:00:00.52#ibcon#*before write, iclass 24, count 0 2006.285.23:00:00.52#ibcon#enter sib2, iclass 24, count 0 2006.285.23:00:00.52#ibcon#flushed, iclass 24, count 0 2006.285.23:00:00.52#ibcon#about to write, iclass 24, count 0 2006.285.23:00:00.52#ibcon#wrote, iclass 24, count 0 2006.285.23:00:00.52#ibcon#about to read 3, iclass 24, count 0 2006.285.23:00:00.56#ibcon#read 3, iclass 24, count 0 2006.285.23:00:00.56#ibcon#about to read 4, iclass 24, count 0 2006.285.23:00:00.56#ibcon#read 4, iclass 24, count 0 2006.285.23:00:00.56#ibcon#about to read 5, iclass 24, count 0 2006.285.23:00:00.56#ibcon#read 5, iclass 24, count 0 2006.285.23:00:00.56#ibcon#about to read 6, iclass 24, count 0 2006.285.23:00:00.56#ibcon#read 6, iclass 24, count 0 2006.285.23:00:00.56#ibcon#end of sib2, iclass 24, count 0 2006.285.23:00:00.56#ibcon#*after write, iclass 24, count 0 2006.285.23:00:00.56#ibcon#*before return 0, iclass 24, count 0 2006.285.23:00:00.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:00:00.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:00:00.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.23:00:00.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.23:00:00.56$vck44/vb=5,4 2006.285.23:00:00.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.23:00:00.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.23:00:00.56#ibcon#ireg 11 cls_cnt 2 2006.285.23:00:00.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:00:00.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:00:00.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:00:00.62#ibcon#enter wrdev, iclass 26, count 2 2006.285.23:00:00.62#ibcon#first serial, iclass 26, count 2 2006.285.23:00:00.62#ibcon#enter sib2, iclass 26, count 2 2006.285.23:00:00.62#ibcon#flushed, iclass 26, count 2 2006.285.23:00:00.62#ibcon#about to write, iclass 26, count 2 2006.285.23:00:00.62#ibcon#wrote, iclass 26, count 2 2006.285.23:00:00.62#ibcon#about to read 3, iclass 26, count 2 2006.285.23:00:00.64#ibcon#read 3, iclass 26, count 2 2006.285.23:00:00.64#ibcon#about to read 4, iclass 26, count 2 2006.285.23:00:00.64#ibcon#read 4, iclass 26, count 2 2006.285.23:00:00.64#ibcon#about to read 5, iclass 26, count 2 2006.285.23:00:00.64#ibcon#read 5, iclass 26, count 2 2006.285.23:00:00.64#ibcon#about to read 6, iclass 26, count 2 2006.285.23:00:00.64#ibcon#read 6, iclass 26, count 2 2006.285.23:00:00.64#ibcon#end of sib2, iclass 26, count 2 2006.285.23:00:00.64#ibcon#*mode == 0, iclass 26, count 2 2006.285.23:00:00.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.23:00:00.64#ibcon#[27=AT05-04\r\n] 2006.285.23:00:00.64#ibcon#*before write, iclass 26, count 2 2006.285.23:00:00.64#ibcon#enter sib2, iclass 26, count 2 2006.285.23:00:00.64#ibcon#flushed, iclass 26, count 2 2006.285.23:00:00.64#ibcon#about to write, iclass 26, count 2 2006.285.23:00:00.64#ibcon#wrote, iclass 26, count 2 2006.285.23:00:00.64#ibcon#about to read 3, iclass 26, count 2 2006.285.23:00:00.67#ibcon#read 3, iclass 26, count 2 2006.285.23:00:00.67#ibcon#about to read 4, iclass 26, count 2 2006.285.23:00:00.67#ibcon#read 4, iclass 26, count 2 2006.285.23:00:00.67#ibcon#about to read 5, iclass 26, count 2 2006.285.23:00:00.67#ibcon#read 5, iclass 26, count 2 2006.285.23:00:00.67#ibcon#about to read 6, iclass 26, count 2 2006.285.23:00:00.67#ibcon#read 6, iclass 26, count 2 2006.285.23:00:00.67#ibcon#end of sib2, iclass 26, count 2 2006.285.23:00:00.67#ibcon#*after write, iclass 26, count 2 2006.285.23:00:00.67#ibcon#*before return 0, iclass 26, count 2 2006.285.23:00:00.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:00:00.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:00:00.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.23:00:00.67#ibcon#ireg 7 cls_cnt 0 2006.285.23:00:00.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:00:00.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:00:00.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:00:00.79#ibcon#enter wrdev, iclass 26, count 0 2006.285.23:00:00.79#ibcon#first serial, iclass 26, count 0 2006.285.23:00:00.79#ibcon#enter sib2, iclass 26, count 0 2006.285.23:00:00.79#ibcon#flushed, iclass 26, count 0 2006.285.23:00:00.79#ibcon#about to write, iclass 26, count 0 2006.285.23:00:00.79#ibcon#wrote, iclass 26, count 0 2006.285.23:00:00.79#ibcon#about to read 3, iclass 26, count 0 2006.285.23:00:00.81#ibcon#read 3, iclass 26, count 0 2006.285.23:00:00.81#ibcon#about to read 4, iclass 26, count 0 2006.285.23:00:00.81#ibcon#read 4, iclass 26, count 0 2006.285.23:00:00.81#ibcon#about to read 5, iclass 26, count 0 2006.285.23:00:00.81#ibcon#read 5, iclass 26, count 0 2006.285.23:00:00.81#ibcon#about to read 6, iclass 26, count 0 2006.285.23:00:00.81#ibcon#read 6, iclass 26, count 0 2006.285.23:00:00.81#ibcon#end of sib2, iclass 26, count 0 2006.285.23:00:00.81#ibcon#*mode == 0, iclass 26, count 0 2006.285.23:00:00.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.23:00:00.81#ibcon#[27=USB\r\n] 2006.285.23:00:00.81#ibcon#*before write, iclass 26, count 0 2006.285.23:00:00.81#ibcon#enter sib2, iclass 26, count 0 2006.285.23:00:00.81#ibcon#flushed, iclass 26, count 0 2006.285.23:00:00.81#ibcon#about to write, iclass 26, count 0 2006.285.23:00:00.81#ibcon#wrote, iclass 26, count 0 2006.285.23:00:00.81#ibcon#about to read 3, iclass 26, count 0 2006.285.23:00:00.84#ibcon#read 3, iclass 26, count 0 2006.285.23:00:00.84#ibcon#about to read 4, iclass 26, count 0 2006.285.23:00:00.84#ibcon#read 4, iclass 26, count 0 2006.285.23:00:00.84#ibcon#about to read 5, iclass 26, count 0 2006.285.23:00:00.84#ibcon#read 5, iclass 26, count 0 2006.285.23:00:00.84#ibcon#about to read 6, iclass 26, count 0 2006.285.23:00:00.84#ibcon#read 6, iclass 26, count 0 2006.285.23:00:00.84#ibcon#end of sib2, iclass 26, count 0 2006.285.23:00:00.84#ibcon#*after write, iclass 26, count 0 2006.285.23:00:00.84#ibcon#*before return 0, iclass 26, count 0 2006.285.23:00:00.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:00:00.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:00:00.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.23:00:00.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.23:00:00.84$vck44/vblo=6,719.99 2006.285.23:00:00.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.23:00:00.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.23:00:00.84#ibcon#ireg 17 cls_cnt 0 2006.285.23:00:00.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:00:00.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:00:00.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:00:00.84#ibcon#enter wrdev, iclass 28, count 0 2006.285.23:00:00.84#ibcon#first serial, iclass 28, count 0 2006.285.23:00:00.84#ibcon#enter sib2, iclass 28, count 0 2006.285.23:00:00.84#ibcon#flushed, iclass 28, count 0 2006.285.23:00:00.84#ibcon#about to write, iclass 28, count 0 2006.285.23:00:00.84#ibcon#wrote, iclass 28, count 0 2006.285.23:00:00.84#ibcon#about to read 3, iclass 28, count 0 2006.285.23:00:00.86#ibcon#read 3, iclass 28, count 0 2006.285.23:00:00.86#ibcon#about to read 4, iclass 28, count 0 2006.285.23:00:00.86#ibcon#read 4, iclass 28, count 0 2006.285.23:00:00.86#ibcon#about to read 5, iclass 28, count 0 2006.285.23:00:00.86#ibcon#read 5, iclass 28, count 0 2006.285.23:00:00.86#ibcon#about to read 6, iclass 28, count 0 2006.285.23:00:00.86#ibcon#read 6, iclass 28, count 0 2006.285.23:00:00.86#ibcon#end of sib2, iclass 28, count 0 2006.285.23:00:00.86#ibcon#*mode == 0, iclass 28, count 0 2006.285.23:00:00.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.23:00:00.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:00:00.86#ibcon#*before write, iclass 28, count 0 2006.285.23:00:00.86#ibcon#enter sib2, iclass 28, count 0 2006.285.23:00:00.86#ibcon#flushed, iclass 28, count 0 2006.285.23:00:00.86#ibcon#about to write, iclass 28, count 0 2006.285.23:00:00.86#ibcon#wrote, iclass 28, count 0 2006.285.23:00:00.86#ibcon#about to read 3, iclass 28, count 0 2006.285.23:00:00.90#ibcon#read 3, iclass 28, count 0 2006.285.23:00:00.90#ibcon#about to read 4, iclass 28, count 0 2006.285.23:00:00.90#ibcon#read 4, iclass 28, count 0 2006.285.23:00:00.90#ibcon#about to read 5, iclass 28, count 0 2006.285.23:00:00.90#ibcon#read 5, iclass 28, count 0 2006.285.23:00:00.90#ibcon#about to read 6, iclass 28, count 0 2006.285.23:00:00.90#ibcon#read 6, iclass 28, count 0 2006.285.23:00:00.90#ibcon#end of sib2, iclass 28, count 0 2006.285.23:00:00.90#ibcon#*after write, iclass 28, count 0 2006.285.23:00:00.90#ibcon#*before return 0, iclass 28, count 0 2006.285.23:00:00.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:00:00.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:00:00.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.23:00:00.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.23:00:00.90$vck44/vb=6,3 2006.285.23:00:00.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.23:00:00.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.23:00:00.90#ibcon#ireg 11 cls_cnt 2 2006.285.23:00:00.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:00:00.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:00:00.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:00:00.96#ibcon#enter wrdev, iclass 30, count 2 2006.285.23:00:00.96#ibcon#first serial, iclass 30, count 2 2006.285.23:00:00.96#ibcon#enter sib2, iclass 30, count 2 2006.285.23:00:00.96#ibcon#flushed, iclass 30, count 2 2006.285.23:00:00.96#ibcon#about to write, iclass 30, count 2 2006.285.23:00:00.96#ibcon#wrote, iclass 30, count 2 2006.285.23:00:00.96#ibcon#about to read 3, iclass 30, count 2 2006.285.23:00:00.98#ibcon#read 3, iclass 30, count 2 2006.285.23:00:00.98#ibcon#about to read 4, iclass 30, count 2 2006.285.23:00:00.98#ibcon#read 4, iclass 30, count 2 2006.285.23:00:00.98#ibcon#about to read 5, iclass 30, count 2 2006.285.23:00:00.98#ibcon#read 5, iclass 30, count 2 2006.285.23:00:00.98#ibcon#about to read 6, iclass 30, count 2 2006.285.23:00:00.98#ibcon#read 6, iclass 30, count 2 2006.285.23:00:00.98#ibcon#end of sib2, iclass 30, count 2 2006.285.23:00:00.98#ibcon#*mode == 0, iclass 30, count 2 2006.285.23:00:00.98#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.23:00:00.98#ibcon#[27=AT06-03\r\n] 2006.285.23:00:00.98#ibcon#*before write, iclass 30, count 2 2006.285.23:00:00.98#ibcon#enter sib2, iclass 30, count 2 2006.285.23:00:00.98#ibcon#flushed, iclass 30, count 2 2006.285.23:00:00.98#ibcon#about to write, iclass 30, count 2 2006.285.23:00:00.98#ibcon#wrote, iclass 30, count 2 2006.285.23:00:00.98#ibcon#about to read 3, iclass 30, count 2 2006.285.23:00:01.01#ibcon#read 3, iclass 30, count 2 2006.285.23:00:01.01#ibcon#about to read 4, iclass 30, count 2 2006.285.23:00:01.01#ibcon#read 4, iclass 30, count 2 2006.285.23:00:01.01#ibcon#about to read 5, iclass 30, count 2 2006.285.23:00:01.01#ibcon#read 5, iclass 30, count 2 2006.285.23:00:01.01#ibcon#about to read 6, iclass 30, count 2 2006.285.23:00:01.01#ibcon#read 6, iclass 30, count 2 2006.285.23:00:01.01#ibcon#end of sib2, iclass 30, count 2 2006.285.23:00:01.01#ibcon#*after write, iclass 30, count 2 2006.285.23:00:01.01#ibcon#*before return 0, iclass 30, count 2 2006.285.23:00:01.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:00:01.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:00:01.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.23:00:01.01#ibcon#ireg 7 cls_cnt 0 2006.285.23:00:01.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:00:01.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:00:01.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:00:01.13#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:00:01.13#ibcon#first serial, iclass 30, count 0 2006.285.23:00:01.13#ibcon#enter sib2, iclass 30, count 0 2006.285.23:00:01.13#ibcon#flushed, iclass 30, count 0 2006.285.23:00:01.13#ibcon#about to write, iclass 30, count 0 2006.285.23:00:01.13#ibcon#wrote, iclass 30, count 0 2006.285.23:00:01.13#ibcon#about to read 3, iclass 30, count 0 2006.285.23:00:01.15#ibcon#read 3, iclass 30, count 0 2006.285.23:00:01.15#ibcon#about to read 4, iclass 30, count 0 2006.285.23:00:01.15#ibcon#read 4, iclass 30, count 0 2006.285.23:00:01.15#ibcon#about to read 5, iclass 30, count 0 2006.285.23:00:01.15#ibcon#read 5, iclass 30, count 0 2006.285.23:00:01.15#ibcon#about to read 6, iclass 30, count 0 2006.285.23:00:01.15#ibcon#read 6, iclass 30, count 0 2006.285.23:00:01.15#ibcon#end of sib2, iclass 30, count 0 2006.285.23:00:01.15#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:00:01.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:00:01.15#ibcon#[27=USB\r\n] 2006.285.23:00:01.15#ibcon#*before write, iclass 30, count 0 2006.285.23:00:01.15#ibcon#enter sib2, iclass 30, count 0 2006.285.23:00:01.15#ibcon#flushed, iclass 30, count 0 2006.285.23:00:01.15#ibcon#about to write, iclass 30, count 0 2006.285.23:00:01.15#ibcon#wrote, iclass 30, count 0 2006.285.23:00:01.15#ibcon#about to read 3, iclass 30, count 0 2006.285.23:00:01.18#ibcon#read 3, iclass 30, count 0 2006.285.23:00:01.18#ibcon#about to read 4, iclass 30, count 0 2006.285.23:00:01.18#ibcon#read 4, iclass 30, count 0 2006.285.23:00:01.18#ibcon#about to read 5, iclass 30, count 0 2006.285.23:00:01.18#ibcon#read 5, iclass 30, count 0 2006.285.23:00:01.18#ibcon#about to read 6, iclass 30, count 0 2006.285.23:00:01.18#ibcon#read 6, iclass 30, count 0 2006.285.23:00:01.18#ibcon#end of sib2, iclass 30, count 0 2006.285.23:00:01.18#ibcon#*after write, iclass 30, count 0 2006.285.23:00:01.18#ibcon#*before return 0, iclass 30, count 0 2006.285.23:00:01.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:00:01.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:00:01.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:00:01.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:00:01.18$vck44/vblo=7,734.99 2006.285.23:00:01.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.23:00:01.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.23:00:01.18#ibcon#ireg 17 cls_cnt 0 2006.285.23:00:01.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:00:01.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:00:01.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:00:01.18#ibcon#enter wrdev, iclass 32, count 0 2006.285.23:00:01.18#ibcon#first serial, iclass 32, count 0 2006.285.23:00:01.18#ibcon#enter sib2, iclass 32, count 0 2006.285.23:00:01.18#ibcon#flushed, iclass 32, count 0 2006.285.23:00:01.18#ibcon#about to write, iclass 32, count 0 2006.285.23:00:01.18#ibcon#wrote, iclass 32, count 0 2006.285.23:00:01.18#ibcon#about to read 3, iclass 32, count 0 2006.285.23:00:01.20#ibcon#read 3, iclass 32, count 0 2006.285.23:00:01.20#ibcon#about to read 4, iclass 32, count 0 2006.285.23:00:01.20#ibcon#read 4, iclass 32, count 0 2006.285.23:00:01.20#ibcon#about to read 5, iclass 32, count 0 2006.285.23:00:01.20#ibcon#read 5, iclass 32, count 0 2006.285.23:00:01.20#ibcon#about to read 6, iclass 32, count 0 2006.285.23:00:01.20#ibcon#read 6, iclass 32, count 0 2006.285.23:00:01.20#ibcon#end of sib2, iclass 32, count 0 2006.285.23:00:01.20#ibcon#*mode == 0, iclass 32, count 0 2006.285.23:00:01.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.23:00:01.20#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:00:01.20#ibcon#*before write, iclass 32, count 0 2006.285.23:00:01.20#ibcon#enter sib2, iclass 32, count 0 2006.285.23:00:01.20#ibcon#flushed, iclass 32, count 0 2006.285.23:00:01.20#ibcon#about to write, iclass 32, count 0 2006.285.23:00:01.20#ibcon#wrote, iclass 32, count 0 2006.285.23:00:01.20#ibcon#about to read 3, iclass 32, count 0 2006.285.23:00:01.24#ibcon#read 3, iclass 32, count 0 2006.285.23:00:01.24#ibcon#about to read 4, iclass 32, count 0 2006.285.23:00:01.24#ibcon#read 4, iclass 32, count 0 2006.285.23:00:01.24#ibcon#about to read 5, iclass 32, count 0 2006.285.23:00:01.24#ibcon#read 5, iclass 32, count 0 2006.285.23:00:01.24#ibcon#about to read 6, iclass 32, count 0 2006.285.23:00:01.24#ibcon#read 6, iclass 32, count 0 2006.285.23:00:01.24#ibcon#end of sib2, iclass 32, count 0 2006.285.23:00:01.24#ibcon#*after write, iclass 32, count 0 2006.285.23:00:01.24#ibcon#*before return 0, iclass 32, count 0 2006.285.23:00:01.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:00:01.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:00:01.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.23:00:01.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.23:00:01.24$vck44/vb=7,4 2006.285.23:00:01.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.23:00:01.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.23:00:01.24#ibcon#ireg 11 cls_cnt 2 2006.285.23:00:01.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:00:01.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:00:01.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:00:01.30#ibcon#enter wrdev, iclass 34, count 2 2006.285.23:00:01.30#ibcon#first serial, iclass 34, count 2 2006.285.23:00:01.30#ibcon#enter sib2, iclass 34, count 2 2006.285.23:00:01.30#ibcon#flushed, iclass 34, count 2 2006.285.23:00:01.30#ibcon#about to write, iclass 34, count 2 2006.285.23:00:01.30#ibcon#wrote, iclass 34, count 2 2006.285.23:00:01.30#ibcon#about to read 3, iclass 34, count 2 2006.285.23:00:01.32#ibcon#read 3, iclass 34, count 2 2006.285.23:00:01.32#ibcon#about to read 4, iclass 34, count 2 2006.285.23:00:01.32#ibcon#read 4, iclass 34, count 2 2006.285.23:00:01.32#ibcon#about to read 5, iclass 34, count 2 2006.285.23:00:01.32#ibcon#read 5, iclass 34, count 2 2006.285.23:00:01.32#ibcon#about to read 6, iclass 34, count 2 2006.285.23:00:01.32#ibcon#read 6, iclass 34, count 2 2006.285.23:00:01.32#ibcon#end of sib2, iclass 34, count 2 2006.285.23:00:01.32#ibcon#*mode == 0, iclass 34, count 2 2006.285.23:00:01.32#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.23:00:01.32#ibcon#[27=AT07-04\r\n] 2006.285.23:00:01.32#ibcon#*before write, iclass 34, count 2 2006.285.23:00:01.32#ibcon#enter sib2, iclass 34, count 2 2006.285.23:00:01.32#ibcon#flushed, iclass 34, count 2 2006.285.23:00:01.32#ibcon#about to write, iclass 34, count 2 2006.285.23:00:01.32#ibcon#wrote, iclass 34, count 2 2006.285.23:00:01.32#ibcon#about to read 3, iclass 34, count 2 2006.285.23:00:01.35#ibcon#read 3, iclass 34, count 2 2006.285.23:00:01.35#ibcon#about to read 4, iclass 34, count 2 2006.285.23:00:01.35#ibcon#read 4, iclass 34, count 2 2006.285.23:00:01.35#ibcon#about to read 5, iclass 34, count 2 2006.285.23:00:01.35#ibcon#read 5, iclass 34, count 2 2006.285.23:00:01.35#ibcon#about to read 6, iclass 34, count 2 2006.285.23:00:01.35#ibcon#read 6, iclass 34, count 2 2006.285.23:00:01.35#ibcon#end of sib2, iclass 34, count 2 2006.285.23:00:01.35#ibcon#*after write, iclass 34, count 2 2006.285.23:00:01.35#ibcon#*before return 0, iclass 34, count 2 2006.285.23:00:01.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:00:01.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:00:01.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.23:00:01.35#ibcon#ireg 7 cls_cnt 0 2006.285.23:00:01.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:00:01.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:00:01.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:00:01.47#ibcon#enter wrdev, iclass 34, count 0 2006.285.23:00:01.47#ibcon#first serial, iclass 34, count 0 2006.285.23:00:01.47#ibcon#enter sib2, iclass 34, count 0 2006.285.23:00:01.47#ibcon#flushed, iclass 34, count 0 2006.285.23:00:01.47#ibcon#about to write, iclass 34, count 0 2006.285.23:00:01.47#ibcon#wrote, iclass 34, count 0 2006.285.23:00:01.47#ibcon#about to read 3, iclass 34, count 0 2006.285.23:00:01.49#ibcon#read 3, iclass 34, count 0 2006.285.23:00:01.49#ibcon#about to read 4, iclass 34, count 0 2006.285.23:00:01.49#ibcon#read 4, iclass 34, count 0 2006.285.23:00:01.49#ibcon#about to read 5, iclass 34, count 0 2006.285.23:00:01.49#ibcon#read 5, iclass 34, count 0 2006.285.23:00:01.49#ibcon#about to read 6, iclass 34, count 0 2006.285.23:00:01.49#ibcon#read 6, iclass 34, count 0 2006.285.23:00:01.49#ibcon#end of sib2, iclass 34, count 0 2006.285.23:00:01.49#ibcon#*mode == 0, iclass 34, count 0 2006.285.23:00:01.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.23:00:01.49#ibcon#[27=USB\r\n] 2006.285.23:00:01.49#ibcon#*before write, iclass 34, count 0 2006.285.23:00:01.49#ibcon#enter sib2, iclass 34, count 0 2006.285.23:00:01.49#ibcon#flushed, iclass 34, count 0 2006.285.23:00:01.49#ibcon#about to write, iclass 34, count 0 2006.285.23:00:01.49#ibcon#wrote, iclass 34, count 0 2006.285.23:00:01.49#ibcon#about to read 3, iclass 34, count 0 2006.285.23:00:01.52#ibcon#read 3, iclass 34, count 0 2006.285.23:00:01.52#ibcon#about to read 4, iclass 34, count 0 2006.285.23:00:01.52#ibcon#read 4, iclass 34, count 0 2006.285.23:00:01.52#ibcon#about to read 5, iclass 34, count 0 2006.285.23:00:01.52#ibcon#read 5, iclass 34, count 0 2006.285.23:00:01.52#ibcon#about to read 6, iclass 34, count 0 2006.285.23:00:01.52#ibcon#read 6, iclass 34, count 0 2006.285.23:00:01.52#ibcon#end of sib2, iclass 34, count 0 2006.285.23:00:01.52#ibcon#*after write, iclass 34, count 0 2006.285.23:00:01.52#ibcon#*before return 0, iclass 34, count 0 2006.285.23:00:01.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:00:01.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:00:01.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.23:00:01.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.23:00:01.52$vck44/vblo=8,744.99 2006.285.23:00:01.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.23:00:01.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.23:00:01.52#ibcon#ireg 17 cls_cnt 0 2006.285.23:00:01.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:00:01.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:00:01.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:00:01.52#ibcon#enter wrdev, iclass 36, count 0 2006.285.23:00:01.52#ibcon#first serial, iclass 36, count 0 2006.285.23:00:01.52#ibcon#enter sib2, iclass 36, count 0 2006.285.23:00:01.52#ibcon#flushed, iclass 36, count 0 2006.285.23:00:01.52#ibcon#about to write, iclass 36, count 0 2006.285.23:00:01.52#ibcon#wrote, iclass 36, count 0 2006.285.23:00:01.52#ibcon#about to read 3, iclass 36, count 0 2006.285.23:00:01.54#ibcon#read 3, iclass 36, count 0 2006.285.23:00:01.54#ibcon#about to read 4, iclass 36, count 0 2006.285.23:00:01.54#ibcon#read 4, iclass 36, count 0 2006.285.23:00:01.54#ibcon#about to read 5, iclass 36, count 0 2006.285.23:00:01.54#ibcon#read 5, iclass 36, count 0 2006.285.23:00:01.54#ibcon#about to read 6, iclass 36, count 0 2006.285.23:00:01.54#ibcon#read 6, iclass 36, count 0 2006.285.23:00:01.54#ibcon#end of sib2, iclass 36, count 0 2006.285.23:00:01.54#ibcon#*mode == 0, iclass 36, count 0 2006.285.23:00:01.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.23:00:01.54#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:00:01.54#ibcon#*before write, iclass 36, count 0 2006.285.23:00:01.54#ibcon#enter sib2, iclass 36, count 0 2006.285.23:00:01.54#ibcon#flushed, iclass 36, count 0 2006.285.23:00:01.54#ibcon#about to write, iclass 36, count 0 2006.285.23:00:01.54#ibcon#wrote, iclass 36, count 0 2006.285.23:00:01.54#ibcon#about to read 3, iclass 36, count 0 2006.285.23:00:01.58#ibcon#read 3, iclass 36, count 0 2006.285.23:00:01.58#ibcon#about to read 4, iclass 36, count 0 2006.285.23:00:01.58#ibcon#read 4, iclass 36, count 0 2006.285.23:00:01.58#ibcon#about to read 5, iclass 36, count 0 2006.285.23:00:01.58#ibcon#read 5, iclass 36, count 0 2006.285.23:00:01.58#ibcon#about to read 6, iclass 36, count 0 2006.285.23:00:01.58#ibcon#read 6, iclass 36, count 0 2006.285.23:00:01.58#ibcon#end of sib2, iclass 36, count 0 2006.285.23:00:01.58#ibcon#*after write, iclass 36, count 0 2006.285.23:00:01.58#ibcon#*before return 0, iclass 36, count 0 2006.285.23:00:01.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:00:01.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:00:01.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.23:00:01.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.23:00:01.58$vck44/vb=8,4 2006.285.23:00:01.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.23:00:01.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.23:00:01.58#ibcon#ireg 11 cls_cnt 2 2006.285.23:00:01.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:00:01.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:00:01.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:00:01.64#ibcon#enter wrdev, iclass 38, count 2 2006.285.23:00:01.64#ibcon#first serial, iclass 38, count 2 2006.285.23:00:01.64#ibcon#enter sib2, iclass 38, count 2 2006.285.23:00:01.64#ibcon#flushed, iclass 38, count 2 2006.285.23:00:01.64#ibcon#about to write, iclass 38, count 2 2006.285.23:00:01.64#ibcon#wrote, iclass 38, count 2 2006.285.23:00:01.64#ibcon#about to read 3, iclass 38, count 2 2006.285.23:00:01.66#ibcon#read 3, iclass 38, count 2 2006.285.23:00:01.66#ibcon#about to read 4, iclass 38, count 2 2006.285.23:00:01.66#ibcon#read 4, iclass 38, count 2 2006.285.23:00:01.66#ibcon#about to read 5, iclass 38, count 2 2006.285.23:00:01.66#ibcon#read 5, iclass 38, count 2 2006.285.23:00:01.66#ibcon#about to read 6, iclass 38, count 2 2006.285.23:00:01.66#ibcon#read 6, iclass 38, count 2 2006.285.23:00:01.66#ibcon#end of sib2, iclass 38, count 2 2006.285.23:00:01.66#ibcon#*mode == 0, iclass 38, count 2 2006.285.23:00:01.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.23:00:01.66#ibcon#[27=AT08-04\r\n] 2006.285.23:00:01.66#ibcon#*before write, iclass 38, count 2 2006.285.23:00:01.66#ibcon#enter sib2, iclass 38, count 2 2006.285.23:00:01.66#ibcon#flushed, iclass 38, count 2 2006.285.23:00:01.66#ibcon#about to write, iclass 38, count 2 2006.285.23:00:01.66#ibcon#wrote, iclass 38, count 2 2006.285.23:00:01.66#ibcon#about to read 3, iclass 38, count 2 2006.285.23:00:01.69#ibcon#read 3, iclass 38, count 2 2006.285.23:00:01.69#ibcon#about to read 4, iclass 38, count 2 2006.285.23:00:01.69#ibcon#read 4, iclass 38, count 2 2006.285.23:00:01.69#ibcon#about to read 5, iclass 38, count 2 2006.285.23:00:01.69#ibcon#read 5, iclass 38, count 2 2006.285.23:00:01.69#ibcon#about to read 6, iclass 38, count 2 2006.285.23:00:01.69#ibcon#read 6, iclass 38, count 2 2006.285.23:00:01.69#ibcon#end of sib2, iclass 38, count 2 2006.285.23:00:01.69#ibcon#*after write, iclass 38, count 2 2006.285.23:00:01.69#ibcon#*before return 0, iclass 38, count 2 2006.285.23:00:01.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:00:01.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:00:01.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.23:00:01.69#ibcon#ireg 7 cls_cnt 0 2006.285.23:00:01.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:00:01.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:00:01.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:00:01.81#ibcon#enter wrdev, iclass 38, count 0 2006.285.23:00:01.81#ibcon#first serial, iclass 38, count 0 2006.285.23:00:01.81#ibcon#enter sib2, iclass 38, count 0 2006.285.23:00:01.81#ibcon#flushed, iclass 38, count 0 2006.285.23:00:01.81#ibcon#about to write, iclass 38, count 0 2006.285.23:00:01.81#ibcon#wrote, iclass 38, count 0 2006.285.23:00:01.81#ibcon#about to read 3, iclass 38, count 0 2006.285.23:00:01.83#ibcon#read 3, iclass 38, count 0 2006.285.23:00:01.83#ibcon#about to read 4, iclass 38, count 0 2006.285.23:00:01.83#ibcon#read 4, iclass 38, count 0 2006.285.23:00:01.83#ibcon#about to read 5, iclass 38, count 0 2006.285.23:00:01.83#ibcon#read 5, iclass 38, count 0 2006.285.23:00:01.83#ibcon#about to read 6, iclass 38, count 0 2006.285.23:00:01.83#ibcon#read 6, iclass 38, count 0 2006.285.23:00:01.83#ibcon#end of sib2, iclass 38, count 0 2006.285.23:00:01.83#ibcon#*mode == 0, iclass 38, count 0 2006.285.23:00:01.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.23:00:01.83#ibcon#[27=USB\r\n] 2006.285.23:00:01.83#ibcon#*before write, iclass 38, count 0 2006.285.23:00:01.83#ibcon#enter sib2, iclass 38, count 0 2006.285.23:00:01.83#ibcon#flushed, iclass 38, count 0 2006.285.23:00:01.83#ibcon#about to write, iclass 38, count 0 2006.285.23:00:01.83#ibcon#wrote, iclass 38, count 0 2006.285.23:00:01.83#ibcon#about to read 3, iclass 38, count 0 2006.285.23:00:01.86#ibcon#read 3, iclass 38, count 0 2006.285.23:00:01.86#ibcon#about to read 4, iclass 38, count 0 2006.285.23:00:01.86#ibcon#read 4, iclass 38, count 0 2006.285.23:00:01.86#ibcon#about to read 5, iclass 38, count 0 2006.285.23:00:01.86#ibcon#read 5, iclass 38, count 0 2006.285.23:00:01.86#ibcon#about to read 6, iclass 38, count 0 2006.285.23:00:01.86#ibcon#read 6, iclass 38, count 0 2006.285.23:00:01.86#ibcon#end of sib2, iclass 38, count 0 2006.285.23:00:01.86#ibcon#*after write, iclass 38, count 0 2006.285.23:00:01.86#ibcon#*before return 0, iclass 38, count 0 2006.285.23:00:01.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:00:01.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:00:01.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.23:00:01.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.23:00:01.86$vck44/vabw=wide 2006.285.23:00:01.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.23:00:01.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.23:00:01.86#ibcon#ireg 8 cls_cnt 0 2006.285.23:00:01.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:00:01.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:00:01.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:00:01.86#ibcon#enter wrdev, iclass 40, count 0 2006.285.23:00:01.86#ibcon#first serial, iclass 40, count 0 2006.285.23:00:01.86#ibcon#enter sib2, iclass 40, count 0 2006.285.23:00:01.86#ibcon#flushed, iclass 40, count 0 2006.285.23:00:01.86#ibcon#about to write, iclass 40, count 0 2006.285.23:00:01.86#ibcon#wrote, iclass 40, count 0 2006.285.23:00:01.86#ibcon#about to read 3, iclass 40, count 0 2006.285.23:00:01.88#ibcon#read 3, iclass 40, count 0 2006.285.23:00:01.88#ibcon#about to read 4, iclass 40, count 0 2006.285.23:00:01.88#ibcon#read 4, iclass 40, count 0 2006.285.23:00:01.88#ibcon#about to read 5, iclass 40, count 0 2006.285.23:00:01.88#ibcon#read 5, iclass 40, count 0 2006.285.23:00:01.88#ibcon#about to read 6, iclass 40, count 0 2006.285.23:00:01.88#ibcon#read 6, iclass 40, count 0 2006.285.23:00:01.88#ibcon#end of sib2, iclass 40, count 0 2006.285.23:00:01.88#ibcon#*mode == 0, iclass 40, count 0 2006.285.23:00:01.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.23:00:01.88#ibcon#[25=BW32\r\n] 2006.285.23:00:01.88#ibcon#*before write, iclass 40, count 0 2006.285.23:00:01.88#ibcon#enter sib2, iclass 40, count 0 2006.285.23:00:01.88#ibcon#flushed, iclass 40, count 0 2006.285.23:00:01.88#ibcon#about to write, iclass 40, count 0 2006.285.23:00:01.88#ibcon#wrote, iclass 40, count 0 2006.285.23:00:01.88#ibcon#about to read 3, iclass 40, count 0 2006.285.23:00:01.91#ibcon#read 3, iclass 40, count 0 2006.285.23:00:01.91#ibcon#about to read 4, iclass 40, count 0 2006.285.23:00:01.91#ibcon#read 4, iclass 40, count 0 2006.285.23:00:01.91#ibcon#about to read 5, iclass 40, count 0 2006.285.23:00:01.91#ibcon#read 5, iclass 40, count 0 2006.285.23:00:01.91#ibcon#about to read 6, iclass 40, count 0 2006.285.23:00:01.91#ibcon#read 6, iclass 40, count 0 2006.285.23:00:01.91#ibcon#end of sib2, iclass 40, count 0 2006.285.23:00:01.91#ibcon#*after write, iclass 40, count 0 2006.285.23:00:01.91#ibcon#*before return 0, iclass 40, count 0 2006.285.23:00:01.91#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:00:01.91#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:00:01.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.23:00:01.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.23:00:01.91$vck44/vbbw=wide 2006.285.23:00:01.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.23:00:01.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.23:00:01.91#ibcon#ireg 8 cls_cnt 0 2006.285.23:00:01.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:00:01.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:00:01.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:00:01.98#ibcon#enter wrdev, iclass 4, count 0 2006.285.23:00:01.98#ibcon#first serial, iclass 4, count 0 2006.285.23:00:01.98#ibcon#enter sib2, iclass 4, count 0 2006.285.23:00:01.98#ibcon#flushed, iclass 4, count 0 2006.285.23:00:01.98#ibcon#about to write, iclass 4, count 0 2006.285.23:00:01.98#ibcon#wrote, iclass 4, count 0 2006.285.23:00:01.98#ibcon#about to read 3, iclass 4, count 0 2006.285.23:00:02.00#ibcon#read 3, iclass 4, count 0 2006.285.23:00:02.00#ibcon#about to read 4, iclass 4, count 0 2006.285.23:00:02.00#ibcon#read 4, iclass 4, count 0 2006.285.23:00:02.00#ibcon#about to read 5, iclass 4, count 0 2006.285.23:00:02.00#ibcon#read 5, iclass 4, count 0 2006.285.23:00:02.00#ibcon#about to read 6, iclass 4, count 0 2006.285.23:00:02.00#ibcon#read 6, iclass 4, count 0 2006.285.23:00:02.00#ibcon#end of sib2, iclass 4, count 0 2006.285.23:00:02.00#ibcon#*mode == 0, iclass 4, count 0 2006.285.23:00:02.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.23:00:02.00#ibcon#[27=BW32\r\n] 2006.285.23:00:02.00#ibcon#*before write, iclass 4, count 0 2006.285.23:00:02.00#ibcon#enter sib2, iclass 4, count 0 2006.285.23:00:02.00#ibcon#flushed, iclass 4, count 0 2006.285.23:00:02.00#ibcon#about to write, iclass 4, count 0 2006.285.23:00:02.00#ibcon#wrote, iclass 4, count 0 2006.285.23:00:02.00#ibcon#about to read 3, iclass 4, count 0 2006.285.23:00:02.03#ibcon#read 3, iclass 4, count 0 2006.285.23:00:02.03#ibcon#about to read 4, iclass 4, count 0 2006.285.23:00:02.03#ibcon#read 4, iclass 4, count 0 2006.285.23:00:02.03#ibcon#about to read 5, iclass 4, count 0 2006.285.23:00:02.03#ibcon#read 5, iclass 4, count 0 2006.285.23:00:02.03#ibcon#about to read 6, iclass 4, count 0 2006.285.23:00:02.03#ibcon#read 6, iclass 4, count 0 2006.285.23:00:02.03#ibcon#end of sib2, iclass 4, count 0 2006.285.23:00:02.03#ibcon#*after write, iclass 4, count 0 2006.285.23:00:02.03#ibcon#*before return 0, iclass 4, count 0 2006.285.23:00:02.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:00:02.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:00:02.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.23:00:02.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.23:00:02.03$setupk4/ifdk4 2006.285.23:00:02.03$ifdk4/lo= 2006.285.23:00:02.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:00:02.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:00:02.03$ifdk4/patch= 2006.285.23:00:02.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:00:02.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:00:02.03$setupk4/!*+20s 2006.285.23:00:08.09#abcon#<5=/03 3.2 5.9 18.42 891016.3\r\n> 2006.285.23:00:08.11#abcon#{5=INTERFACE CLEAR} 2006.285.23:00:08.17#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:00:14.13#trakl#Source acquired 2006.285.23:00:16.13#flagr#flagr/antenna,acquired 2006.285.23:00:16.53$setupk4/"tpicd 2006.285.23:00:16.53$setupk4/echo=off 2006.285.23:00:16.53$setupk4/xlog=off 2006.285.23:00:16.53:!2006.285.23:01:42 2006.285.23:01:42.00:preob 2006.285.23:01:42.14/onsource/TRACKING 2006.285.23:01:42.14:!2006.285.23:01:52 2006.285.23:01:52.00:"tape 2006.285.23:01:52.00:"st=record 2006.285.23:01:52.00:data_valid=on 2006.285.23:01:52.00:midob 2006.285.23:01:52.14/onsource/TRACKING 2006.285.23:01:52.14/wx/18.49,1016.4,90 2006.285.23:01:52.35/cable/+6.5121E-03 2006.285.23:01:53.44/va/01,07,usb,yes,33,35 2006.285.23:01:53.44/va/02,06,usb,yes,33,33 2006.285.23:01:53.44/va/03,07,usb,yes,32,34 2006.285.23:01:53.44/va/04,06,usb,yes,34,35 2006.285.23:01:53.44/va/05,03,usb,yes,33,34 2006.285.23:01:53.44/va/06,04,usb,yes,30,29 2006.285.23:01:53.44/va/07,04,usb,yes,30,31 2006.285.23:01:53.44/va/08,03,usb,yes,31,38 2006.285.23:01:53.67/valo/01,524.99,yes,locked 2006.285.23:01:53.67/valo/02,534.99,yes,locked 2006.285.23:01:53.67/valo/03,564.99,yes,locked 2006.285.23:01:53.67/valo/04,624.99,yes,locked 2006.285.23:01:53.67/valo/05,734.99,yes,locked 2006.285.23:01:53.67/valo/06,814.99,yes,locked 2006.285.23:01:53.67/valo/07,864.99,yes,locked 2006.285.23:01:53.67/valo/08,884.99,yes,locked 2006.285.23:01:54.76/vb/01,04,usb,yes,30,28 2006.285.23:01:54.76/vb/02,05,usb,yes,29,28 2006.285.23:01:54.76/vb/03,04,usb,yes,29,32 2006.285.23:01:54.76/vb/04,05,usb,yes,30,29 2006.285.23:01:54.76/vb/05,04,usb,yes,26,28 2006.285.23:01:54.76/vb/06,03,usb,yes,37,33 2006.285.23:01:54.76/vb/07,04,usb,yes,30,30 2006.285.23:01:54.76/vb/08,04,usb,yes,27,31 2006.285.23:01:55.00/vblo/01,629.99,yes,locked 2006.285.23:01:55.00/vblo/02,634.99,yes,locked 2006.285.23:01:55.00/vblo/03,649.99,yes,locked 2006.285.23:01:55.00/vblo/04,679.99,yes,locked 2006.285.23:01:55.00/vblo/05,709.99,yes,locked 2006.285.23:01:55.00/vblo/06,719.99,yes,locked 2006.285.23:01:55.00/vblo/07,734.99,yes,locked 2006.285.23:01:55.00/vblo/08,744.99,yes,locked 2006.285.23:01:55.15/vabw/8 2006.285.23:01:55.30/vbbw/8 2006.285.23:01:55.41/xfe/off,on,12.0 2006.285.23:01:55.81/ifatt/23,28,28,28 2006.285.23:01:56.08/fmout-gps/S +2.67E-07 2006.285.23:01:56.09:!2006.285.23:03:42 2006.285.23:03:42.00:data_valid=off 2006.285.23:03:42.00:"et 2006.285.23:03:42.00:!+3s 2006.285.23:03:45.01:"tape 2006.285.23:03:45.01:postob 2006.285.23:03:45.08/cable/+6.5113E-03 2006.285.23:03:45.08/wx/18.57,1016.4,90 2006.285.23:03:46.07/fmout-gps/S +2.67E-07 2006.285.23:03:46.07:scan_name=285-2307,jd0610,40 2006.285.23:03:46.07:source=3c345,164258.81,394837.0,2000.0,cw 2006.285.23:03:47.14#flagr#flagr/antenna,new-source 2006.285.23:03:47.14:checkk5 2006.285.23:03:47.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.23:03:47.98/chk_autoobs//k5ts2/ autoobs is running! 2006.285.23:03:48.35/chk_autoobs//k5ts3/ autoobs is running! 2006.285.23:03:48.71/chk_autoobs//k5ts4/ autoobs is running! 2006.285.23:03:49.07/chk_obsdata//k5ts1/T2852301??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.23:03:49.51/chk_obsdata//k5ts2/T2852301??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.23:03:49.86/chk_obsdata//k5ts3/T2852301??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.23:03:50.24/chk_obsdata//k5ts4/T2852301??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.285.23:03:51.01/k5log//k5ts1_log_newline 2006.285.23:03:51.86/k5log//k5ts2_log_newline 2006.285.23:03:52.66/k5log//k5ts3_log_newline 2006.285.23:03:53.68/k5log//k5ts4_log_newline 2006.285.23:03:53.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.23:03:53.70:setupk4=1 2006.285.23:03:53.70$setupk4/echo=on 2006.285.23:03:53.70$setupk4/pcalon 2006.285.23:03:53.70$pcalon/"no phase cal control is implemented here 2006.285.23:03:53.70$setupk4/"tpicd=stop 2006.285.23:03:53.70$setupk4/"rec=synch_on 2006.285.23:03:53.70$setupk4/"rec_mode=128 2006.285.23:03:53.70$setupk4/!* 2006.285.23:03:53.70$setupk4/recpk4 2006.285.23:03:53.70$recpk4/recpatch= 2006.285.23:03:53.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.23:03:53.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.23:03:53.70$setupk4/vck44 2006.285.23:03:53.70$vck44/valo=1,524.99 2006.285.23:03:53.70#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.23:03:53.71#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.23:03:53.71#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:53.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:03:53.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:03:53.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:03:53.71#ibcon#enter wrdev, iclass 31, count 0 2006.285.23:03:53.71#ibcon#first serial, iclass 31, count 0 2006.285.23:03:53.71#ibcon#enter sib2, iclass 31, count 0 2006.285.23:03:53.71#ibcon#flushed, iclass 31, count 0 2006.285.23:03:53.71#ibcon#about to write, iclass 31, count 0 2006.285.23:03:53.71#ibcon#wrote, iclass 31, count 0 2006.285.23:03:53.71#ibcon#about to read 3, iclass 31, count 0 2006.285.23:03:53.72#ibcon#read 3, iclass 31, count 0 2006.285.23:03:53.72#ibcon#about to read 4, iclass 31, count 0 2006.285.23:03:53.73#ibcon#read 4, iclass 31, count 0 2006.285.23:03:53.73#ibcon#about to read 5, iclass 31, count 0 2006.285.23:03:53.73#ibcon#read 5, iclass 31, count 0 2006.285.23:03:53.73#ibcon#about to read 6, iclass 31, count 0 2006.285.23:03:53.73#ibcon#read 6, iclass 31, count 0 2006.285.23:03:53.73#ibcon#end of sib2, iclass 31, count 0 2006.285.23:03:53.73#ibcon#*mode == 0, iclass 31, count 0 2006.285.23:03:53.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.23:03:53.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.23:03:53.73#ibcon#*before write, iclass 31, count 0 2006.285.23:03:53.73#ibcon#enter sib2, iclass 31, count 0 2006.285.23:03:53.73#ibcon#flushed, iclass 31, count 0 2006.285.23:03:53.73#ibcon#about to write, iclass 31, count 0 2006.285.23:03:53.73#ibcon#wrote, iclass 31, count 0 2006.285.23:03:53.73#ibcon#about to read 3, iclass 31, count 0 2006.285.23:03:53.77#ibcon#read 3, iclass 31, count 0 2006.285.23:03:53.77#ibcon#about to read 4, iclass 31, count 0 2006.285.23:03:53.78#ibcon#read 4, iclass 31, count 0 2006.285.23:03:53.78#ibcon#about to read 5, iclass 31, count 0 2006.285.23:03:53.78#ibcon#read 5, iclass 31, count 0 2006.285.23:03:53.78#ibcon#about to read 6, iclass 31, count 0 2006.285.23:03:53.78#ibcon#read 6, iclass 31, count 0 2006.285.23:03:53.78#ibcon#end of sib2, iclass 31, count 0 2006.285.23:03:53.78#ibcon#*after write, iclass 31, count 0 2006.285.23:03:53.78#ibcon#*before return 0, iclass 31, count 0 2006.285.23:03:53.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:03:53.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:03:53.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.23:03:53.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.23:03:53.78$vck44/va=1,7 2006.285.23:03:53.78#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.23:03:53.78#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.23:03:53.78#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:53.78#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:03:53.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:03:53.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:03:53.78#ibcon#enter wrdev, iclass 33, count 2 2006.285.23:03:53.78#ibcon#first serial, iclass 33, count 2 2006.285.23:03:53.78#ibcon#enter sib2, iclass 33, count 2 2006.285.23:03:53.78#ibcon#flushed, iclass 33, count 2 2006.285.23:03:53.78#ibcon#about to write, iclass 33, count 2 2006.285.23:03:53.78#ibcon#wrote, iclass 33, count 2 2006.285.23:03:53.78#ibcon#about to read 3, iclass 33, count 2 2006.285.23:03:53.79#ibcon#read 3, iclass 33, count 2 2006.285.23:03:53.79#ibcon#about to read 4, iclass 33, count 2 2006.285.23:03:53.80#ibcon#read 4, iclass 33, count 2 2006.285.23:03:53.80#ibcon#about to read 5, iclass 33, count 2 2006.285.23:03:53.80#ibcon#read 5, iclass 33, count 2 2006.285.23:03:53.80#ibcon#about to read 6, iclass 33, count 2 2006.285.23:03:53.80#ibcon#read 6, iclass 33, count 2 2006.285.23:03:53.80#ibcon#end of sib2, iclass 33, count 2 2006.285.23:03:53.80#ibcon#*mode == 0, iclass 33, count 2 2006.285.23:03:53.80#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.23:03:53.80#ibcon#[25=AT01-07\r\n] 2006.285.23:03:53.80#ibcon#*before write, iclass 33, count 2 2006.285.23:03:53.80#ibcon#enter sib2, iclass 33, count 2 2006.285.23:03:53.80#ibcon#flushed, iclass 33, count 2 2006.285.23:03:53.80#ibcon#about to write, iclass 33, count 2 2006.285.23:03:53.80#ibcon#wrote, iclass 33, count 2 2006.285.23:03:53.80#ibcon#about to read 3, iclass 33, count 2 2006.285.23:03:53.82#ibcon#read 3, iclass 33, count 2 2006.285.23:03:53.82#ibcon#about to read 4, iclass 33, count 2 2006.285.23:03:53.83#ibcon#read 4, iclass 33, count 2 2006.285.23:03:53.83#ibcon#about to read 5, iclass 33, count 2 2006.285.23:03:53.83#ibcon#read 5, iclass 33, count 2 2006.285.23:03:53.83#ibcon#about to read 6, iclass 33, count 2 2006.285.23:03:53.83#ibcon#read 6, iclass 33, count 2 2006.285.23:03:53.83#ibcon#end of sib2, iclass 33, count 2 2006.285.23:03:53.83#ibcon#*after write, iclass 33, count 2 2006.285.23:03:53.83#ibcon#*before return 0, iclass 33, count 2 2006.285.23:03:53.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:03:53.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:03:53.83#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.23:03:53.83#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:53.83#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:03:53.94#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:03:53.94#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:03:53.94#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:03:53.95#ibcon#first serial, iclass 33, count 0 2006.285.23:03:53.95#ibcon#enter sib2, iclass 33, count 0 2006.285.23:03:53.95#ibcon#flushed, iclass 33, count 0 2006.285.23:03:53.95#ibcon#about to write, iclass 33, count 0 2006.285.23:03:53.95#ibcon#wrote, iclass 33, count 0 2006.285.23:03:53.95#ibcon#about to read 3, iclass 33, count 0 2006.285.23:03:53.97#ibcon#read 3, iclass 33, count 0 2006.285.23:03:53.97#ibcon#about to read 4, iclass 33, count 0 2006.285.23:03:53.97#ibcon#read 4, iclass 33, count 0 2006.285.23:03:53.97#ibcon#about to read 5, iclass 33, count 0 2006.285.23:03:53.97#ibcon#read 5, iclass 33, count 0 2006.285.23:03:53.97#ibcon#about to read 6, iclass 33, count 0 2006.285.23:03:53.97#ibcon#read 6, iclass 33, count 0 2006.285.23:03:53.97#ibcon#end of sib2, iclass 33, count 0 2006.285.23:03:53.97#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:03:53.97#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:03:53.97#ibcon#[25=USB\r\n] 2006.285.23:03:53.97#ibcon#*before write, iclass 33, count 0 2006.285.23:03:53.97#ibcon#enter sib2, iclass 33, count 0 2006.285.23:03:53.97#ibcon#flushed, iclass 33, count 0 2006.285.23:03:53.97#ibcon#about to write, iclass 33, count 0 2006.285.23:03:53.97#ibcon#wrote, iclass 33, count 0 2006.285.23:03:53.97#ibcon#about to read 3, iclass 33, count 0 2006.285.23:03:53.99#ibcon#read 3, iclass 33, count 0 2006.285.23:03:53.99#ibcon#about to read 4, iclass 33, count 0 2006.285.23:03:54.00#ibcon#read 4, iclass 33, count 0 2006.285.23:03:54.00#ibcon#about to read 5, iclass 33, count 0 2006.285.23:03:54.00#ibcon#read 5, iclass 33, count 0 2006.285.23:03:54.00#ibcon#about to read 6, iclass 33, count 0 2006.285.23:03:54.00#ibcon#read 6, iclass 33, count 0 2006.285.23:03:54.00#ibcon#end of sib2, iclass 33, count 0 2006.285.23:03:54.00#ibcon#*after write, iclass 33, count 0 2006.285.23:03:54.00#ibcon#*before return 0, iclass 33, count 0 2006.285.23:03:54.00#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:03:54.00#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:03:54.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:03:54.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:03:54.00$vck44/valo=2,534.99 2006.285.23:03:54.00#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.23:03:54.00#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.23:03:54.00#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:54.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:03:54.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:03:54.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:03:54.00#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:03:54.00#ibcon#first serial, iclass 35, count 0 2006.285.23:03:54.00#ibcon#enter sib2, iclass 35, count 0 2006.285.23:03:54.00#ibcon#flushed, iclass 35, count 0 2006.285.23:03:54.00#ibcon#about to write, iclass 35, count 0 2006.285.23:03:54.00#ibcon#wrote, iclass 35, count 0 2006.285.23:03:54.00#ibcon#about to read 3, iclass 35, count 0 2006.285.23:03:54.01#ibcon#read 3, iclass 35, count 0 2006.285.23:03:54.01#ibcon#about to read 4, iclass 35, count 0 2006.285.23:03:54.02#ibcon#read 4, iclass 35, count 0 2006.285.23:03:54.02#ibcon#about to read 5, iclass 35, count 0 2006.285.23:03:54.02#ibcon#read 5, iclass 35, count 0 2006.285.23:03:54.02#ibcon#about to read 6, iclass 35, count 0 2006.285.23:03:54.02#ibcon#read 6, iclass 35, count 0 2006.285.23:03:54.02#ibcon#end of sib2, iclass 35, count 0 2006.285.23:03:54.02#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:03:54.02#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:03:54.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.23:03:54.02#ibcon#*before write, iclass 35, count 0 2006.285.23:03:54.02#ibcon#enter sib2, iclass 35, count 0 2006.285.23:03:54.02#ibcon#flushed, iclass 35, count 0 2006.285.23:03:54.02#ibcon#about to write, iclass 35, count 0 2006.285.23:03:54.02#ibcon#wrote, iclass 35, count 0 2006.285.23:03:54.02#ibcon#about to read 3, iclass 35, count 0 2006.285.23:03:54.06#ibcon#read 3, iclass 35, count 0 2006.285.23:03:54.06#ibcon#about to read 4, iclass 35, count 0 2006.285.23:03:54.06#ibcon#read 4, iclass 35, count 0 2006.285.23:03:54.06#ibcon#about to read 5, iclass 35, count 0 2006.285.23:03:54.06#ibcon#read 5, iclass 35, count 0 2006.285.23:03:54.06#ibcon#about to read 6, iclass 35, count 0 2006.285.23:03:54.06#ibcon#read 6, iclass 35, count 0 2006.285.23:03:54.06#ibcon#end of sib2, iclass 35, count 0 2006.285.23:03:54.06#ibcon#*after write, iclass 35, count 0 2006.285.23:03:54.06#ibcon#*before return 0, iclass 35, count 0 2006.285.23:03:54.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:03:54.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:03:54.06#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:03:54.06#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:03:54.06$vck44/va=2,6 2006.285.23:03:54.06#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.23:03:54.06#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.23:03:54.06#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:54.06#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:03:54.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:03:54.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:03:54.12#ibcon#enter wrdev, iclass 37, count 2 2006.285.23:03:54.12#ibcon#first serial, iclass 37, count 2 2006.285.23:03:54.12#ibcon#enter sib2, iclass 37, count 2 2006.285.23:03:54.12#ibcon#flushed, iclass 37, count 2 2006.285.23:03:54.12#ibcon#about to write, iclass 37, count 2 2006.285.23:03:54.12#ibcon#wrote, iclass 37, count 2 2006.285.23:03:54.12#ibcon#about to read 3, iclass 37, count 2 2006.285.23:03:54.14#ibcon#read 3, iclass 37, count 2 2006.285.23:03:54.14#ibcon#about to read 4, iclass 37, count 2 2006.285.23:03:54.14#ibcon#read 4, iclass 37, count 2 2006.285.23:03:54.14#ibcon#about to read 5, iclass 37, count 2 2006.285.23:03:54.14#ibcon#read 5, iclass 37, count 2 2006.285.23:03:54.14#ibcon#about to read 6, iclass 37, count 2 2006.285.23:03:54.14#ibcon#read 6, iclass 37, count 2 2006.285.23:03:54.14#ibcon#end of sib2, iclass 37, count 2 2006.285.23:03:54.14#ibcon#*mode == 0, iclass 37, count 2 2006.285.23:03:54.14#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.23:03:54.14#ibcon#[25=AT02-06\r\n] 2006.285.23:03:54.14#ibcon#*before write, iclass 37, count 2 2006.285.23:03:54.14#ibcon#enter sib2, iclass 37, count 2 2006.285.23:03:54.14#ibcon#flushed, iclass 37, count 2 2006.285.23:03:54.14#ibcon#about to write, iclass 37, count 2 2006.285.23:03:54.14#ibcon#wrote, iclass 37, count 2 2006.285.23:03:54.14#ibcon#about to read 3, iclass 37, count 2 2006.285.23:03:54.16#ibcon#read 3, iclass 37, count 2 2006.285.23:03:54.16#ibcon#about to read 4, iclass 37, count 2 2006.285.23:03:54.17#ibcon#read 4, iclass 37, count 2 2006.285.23:03:54.17#ibcon#about to read 5, iclass 37, count 2 2006.285.23:03:54.17#ibcon#read 5, iclass 37, count 2 2006.285.23:03:54.17#ibcon#about to read 6, iclass 37, count 2 2006.285.23:03:54.17#ibcon#read 6, iclass 37, count 2 2006.285.23:03:54.17#ibcon#end of sib2, iclass 37, count 2 2006.285.23:03:54.17#ibcon#*after write, iclass 37, count 2 2006.285.23:03:54.17#ibcon#*before return 0, iclass 37, count 2 2006.285.23:03:54.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:03:54.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:03:54.17#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.23:03:54.17#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:54.17#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:03:54.28#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:03:54.29#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:03:54.29#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:03:54.29#ibcon#first serial, iclass 37, count 0 2006.285.23:03:54.29#ibcon#enter sib2, iclass 37, count 0 2006.285.23:03:54.29#ibcon#flushed, iclass 37, count 0 2006.285.23:03:54.29#ibcon#about to write, iclass 37, count 0 2006.285.23:03:54.29#ibcon#wrote, iclass 37, count 0 2006.285.23:03:54.29#ibcon#about to read 3, iclass 37, count 0 2006.285.23:03:54.30#ibcon#read 3, iclass 37, count 0 2006.285.23:03:54.30#ibcon#about to read 4, iclass 37, count 0 2006.285.23:03:54.31#ibcon#read 4, iclass 37, count 0 2006.285.23:03:54.31#ibcon#about to read 5, iclass 37, count 0 2006.285.23:03:54.31#ibcon#read 5, iclass 37, count 0 2006.285.23:03:54.31#ibcon#about to read 6, iclass 37, count 0 2006.285.23:03:54.31#ibcon#read 6, iclass 37, count 0 2006.285.23:03:54.31#ibcon#end of sib2, iclass 37, count 0 2006.285.23:03:54.31#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:03:54.31#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:03:54.31#ibcon#[25=USB\r\n] 2006.285.23:03:54.31#ibcon#*before write, iclass 37, count 0 2006.285.23:03:54.31#ibcon#enter sib2, iclass 37, count 0 2006.285.23:03:54.31#ibcon#flushed, iclass 37, count 0 2006.285.23:03:54.31#ibcon#about to write, iclass 37, count 0 2006.285.23:03:54.31#ibcon#wrote, iclass 37, count 0 2006.285.23:03:54.31#ibcon#about to read 3, iclass 37, count 0 2006.285.23:03:54.33#ibcon#read 3, iclass 37, count 0 2006.285.23:03:54.33#ibcon#about to read 4, iclass 37, count 0 2006.285.23:03:54.34#ibcon#read 4, iclass 37, count 0 2006.285.23:03:54.34#ibcon#about to read 5, iclass 37, count 0 2006.285.23:03:54.34#ibcon#read 5, iclass 37, count 0 2006.285.23:03:54.34#ibcon#about to read 6, iclass 37, count 0 2006.285.23:03:54.34#ibcon#read 6, iclass 37, count 0 2006.285.23:03:54.34#ibcon#end of sib2, iclass 37, count 0 2006.285.23:03:54.34#ibcon#*after write, iclass 37, count 0 2006.285.23:03:54.34#ibcon#*before return 0, iclass 37, count 0 2006.285.23:03:54.34#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:03:54.34#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:03:54.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:03:54.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:03:54.34$vck44/valo=3,564.99 2006.285.23:03:54.34#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.23:03:54.34#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.23:03:54.34#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:54.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:03:54.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:03:54.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:03:54.34#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:03:54.34#ibcon#first serial, iclass 39, count 0 2006.285.23:03:54.34#ibcon#enter sib2, iclass 39, count 0 2006.285.23:03:54.34#ibcon#flushed, iclass 39, count 0 2006.285.23:03:54.34#ibcon#about to write, iclass 39, count 0 2006.285.23:03:54.34#ibcon#wrote, iclass 39, count 0 2006.285.23:03:54.34#ibcon#about to read 3, iclass 39, count 0 2006.285.23:03:54.35#ibcon#read 3, iclass 39, count 0 2006.285.23:03:54.35#ibcon#about to read 4, iclass 39, count 0 2006.285.23:03:54.36#ibcon#read 4, iclass 39, count 0 2006.285.23:03:54.36#ibcon#about to read 5, iclass 39, count 0 2006.285.23:03:54.36#ibcon#read 5, iclass 39, count 0 2006.285.23:03:54.36#ibcon#about to read 6, iclass 39, count 0 2006.285.23:03:54.36#ibcon#read 6, iclass 39, count 0 2006.285.23:03:54.36#ibcon#end of sib2, iclass 39, count 0 2006.285.23:03:54.36#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:03:54.36#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:03:54.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.23:03:54.36#ibcon#*before write, iclass 39, count 0 2006.285.23:03:54.36#ibcon#enter sib2, iclass 39, count 0 2006.285.23:03:54.36#ibcon#flushed, iclass 39, count 0 2006.285.23:03:54.36#ibcon#about to write, iclass 39, count 0 2006.285.23:03:54.36#ibcon#wrote, iclass 39, count 0 2006.285.23:03:54.36#ibcon#about to read 3, iclass 39, count 0 2006.285.23:03:54.39#ibcon#read 3, iclass 39, count 0 2006.285.23:03:54.39#ibcon#about to read 4, iclass 39, count 0 2006.285.23:03:54.40#ibcon#read 4, iclass 39, count 0 2006.285.23:03:54.40#ibcon#about to read 5, iclass 39, count 0 2006.285.23:03:54.40#ibcon#read 5, iclass 39, count 0 2006.285.23:03:54.40#ibcon#about to read 6, iclass 39, count 0 2006.285.23:03:54.40#ibcon#read 6, iclass 39, count 0 2006.285.23:03:54.40#ibcon#end of sib2, iclass 39, count 0 2006.285.23:03:54.40#ibcon#*after write, iclass 39, count 0 2006.285.23:03:54.40#ibcon#*before return 0, iclass 39, count 0 2006.285.23:03:54.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:03:54.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:03:54.40#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:03:54.40#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:03:54.40$vck44/va=3,7 2006.285.23:03:54.40#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.23:03:54.40#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.23:03:54.40#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:54.40#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:03:54.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:03:54.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:03:54.47#ibcon#enter wrdev, iclass 3, count 2 2006.285.23:03:54.47#ibcon#first serial, iclass 3, count 2 2006.285.23:03:54.47#ibcon#enter sib2, iclass 3, count 2 2006.285.23:03:54.47#ibcon#flushed, iclass 3, count 2 2006.285.23:03:54.47#ibcon#about to write, iclass 3, count 2 2006.285.23:03:54.47#ibcon#wrote, iclass 3, count 2 2006.285.23:03:54.47#ibcon#about to read 3, iclass 3, count 2 2006.285.23:03:54.48#ibcon#read 3, iclass 3, count 2 2006.285.23:03:54.49#ibcon#about to read 4, iclass 3, count 2 2006.285.23:03:54.49#ibcon#read 4, iclass 3, count 2 2006.285.23:03:54.49#ibcon#about to read 5, iclass 3, count 2 2006.285.23:03:54.49#ibcon#read 5, iclass 3, count 2 2006.285.23:03:54.49#ibcon#about to read 6, iclass 3, count 2 2006.285.23:03:54.49#ibcon#read 6, iclass 3, count 2 2006.285.23:03:54.49#ibcon#end of sib2, iclass 3, count 2 2006.285.23:03:54.49#ibcon#*mode == 0, iclass 3, count 2 2006.285.23:03:54.49#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.23:03:54.49#ibcon#[25=AT03-07\r\n] 2006.285.23:03:54.49#ibcon#*before write, iclass 3, count 2 2006.285.23:03:54.49#ibcon#enter sib2, iclass 3, count 2 2006.285.23:03:54.49#ibcon#flushed, iclass 3, count 2 2006.285.23:03:54.49#ibcon#about to write, iclass 3, count 2 2006.285.23:03:54.49#ibcon#wrote, iclass 3, count 2 2006.285.23:03:54.49#ibcon#about to read 3, iclass 3, count 2 2006.285.23:03:54.52#ibcon#read 3, iclass 3, count 2 2006.285.23:03:54.52#ibcon#about to read 4, iclass 3, count 2 2006.285.23:03:54.52#ibcon#read 4, iclass 3, count 2 2006.285.23:03:54.52#ibcon#about to read 5, iclass 3, count 2 2006.285.23:03:54.52#ibcon#read 5, iclass 3, count 2 2006.285.23:03:54.52#ibcon#about to read 6, iclass 3, count 2 2006.285.23:03:54.52#ibcon#read 6, iclass 3, count 2 2006.285.23:03:54.52#ibcon#end of sib2, iclass 3, count 2 2006.285.23:03:54.52#ibcon#*after write, iclass 3, count 2 2006.285.23:03:54.52#ibcon#*before return 0, iclass 3, count 2 2006.285.23:03:54.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:03:54.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:03:54.52#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.23:03:54.52#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:54.52#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:03:54.63#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:03:54.64#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:03:54.64#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:03:54.64#ibcon#first serial, iclass 3, count 0 2006.285.23:03:54.64#ibcon#enter sib2, iclass 3, count 0 2006.285.23:03:54.64#ibcon#flushed, iclass 3, count 0 2006.285.23:03:54.64#ibcon#about to write, iclass 3, count 0 2006.285.23:03:54.64#ibcon#wrote, iclass 3, count 0 2006.285.23:03:54.64#ibcon#about to read 3, iclass 3, count 0 2006.285.23:03:54.65#ibcon#read 3, iclass 3, count 0 2006.285.23:03:54.66#ibcon#about to read 4, iclass 3, count 0 2006.285.23:03:54.66#ibcon#read 4, iclass 3, count 0 2006.285.23:03:54.66#ibcon#about to read 5, iclass 3, count 0 2006.285.23:03:54.66#ibcon#read 5, iclass 3, count 0 2006.285.23:03:54.66#ibcon#about to read 6, iclass 3, count 0 2006.285.23:03:54.66#ibcon#read 6, iclass 3, count 0 2006.285.23:03:54.66#ibcon#end of sib2, iclass 3, count 0 2006.285.23:03:54.66#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:03:54.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:03:54.66#ibcon#[25=USB\r\n] 2006.285.23:03:54.66#ibcon#*before write, iclass 3, count 0 2006.285.23:03:54.66#ibcon#enter sib2, iclass 3, count 0 2006.285.23:03:54.66#ibcon#flushed, iclass 3, count 0 2006.285.23:03:54.66#ibcon#about to write, iclass 3, count 0 2006.285.23:03:54.66#ibcon#wrote, iclass 3, count 0 2006.285.23:03:54.66#ibcon#about to read 3, iclass 3, count 0 2006.285.23:03:54.68#ibcon#read 3, iclass 3, count 0 2006.285.23:03:54.69#ibcon#about to read 4, iclass 3, count 0 2006.285.23:03:54.69#ibcon#read 4, iclass 3, count 0 2006.285.23:03:54.69#ibcon#about to read 5, iclass 3, count 0 2006.285.23:03:54.69#ibcon#read 5, iclass 3, count 0 2006.285.23:03:54.69#ibcon#about to read 6, iclass 3, count 0 2006.285.23:03:54.69#ibcon#read 6, iclass 3, count 0 2006.285.23:03:54.69#ibcon#end of sib2, iclass 3, count 0 2006.285.23:03:54.69#ibcon#*after write, iclass 3, count 0 2006.285.23:03:54.69#ibcon#*before return 0, iclass 3, count 0 2006.285.23:03:54.69#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:03:54.69#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:03:54.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:03:54.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:03:54.69$vck44/valo=4,624.99 2006.285.23:03:54.69#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.23:03:54.69#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.23:03:54.69#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:54.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:03:54.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:03:54.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:03:54.69#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:03:54.69#ibcon#first serial, iclass 5, count 0 2006.285.23:03:54.69#ibcon#enter sib2, iclass 5, count 0 2006.285.23:03:54.69#ibcon#flushed, iclass 5, count 0 2006.285.23:03:54.69#ibcon#about to write, iclass 5, count 0 2006.285.23:03:54.69#ibcon#wrote, iclass 5, count 0 2006.285.23:03:54.69#ibcon#about to read 3, iclass 5, count 0 2006.285.23:03:54.70#ibcon#read 3, iclass 5, count 0 2006.285.23:03:54.71#ibcon#about to read 4, iclass 5, count 0 2006.285.23:03:54.71#ibcon#read 4, iclass 5, count 0 2006.285.23:03:54.71#ibcon#about to read 5, iclass 5, count 0 2006.285.23:03:54.71#ibcon#read 5, iclass 5, count 0 2006.285.23:03:54.71#ibcon#about to read 6, iclass 5, count 0 2006.285.23:03:54.71#ibcon#read 6, iclass 5, count 0 2006.285.23:03:54.71#ibcon#end of sib2, iclass 5, count 0 2006.285.23:03:54.71#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:03:54.71#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:03:54.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.23:03:54.71#ibcon#*before write, iclass 5, count 0 2006.285.23:03:54.71#ibcon#enter sib2, iclass 5, count 0 2006.285.23:03:54.71#ibcon#flushed, iclass 5, count 0 2006.285.23:03:54.71#ibcon#about to write, iclass 5, count 0 2006.285.23:03:54.71#ibcon#wrote, iclass 5, count 0 2006.285.23:03:54.71#ibcon#about to read 3, iclass 5, count 0 2006.285.23:03:54.74#ibcon#read 3, iclass 5, count 0 2006.285.23:03:54.74#ibcon#about to read 4, iclass 5, count 0 2006.285.23:03:54.75#ibcon#read 4, iclass 5, count 0 2006.285.23:03:54.75#ibcon#about to read 5, iclass 5, count 0 2006.285.23:03:54.75#ibcon#read 5, iclass 5, count 0 2006.285.23:03:54.75#ibcon#about to read 6, iclass 5, count 0 2006.285.23:03:54.75#ibcon#read 6, iclass 5, count 0 2006.285.23:03:54.75#ibcon#end of sib2, iclass 5, count 0 2006.285.23:03:54.75#ibcon#*after write, iclass 5, count 0 2006.285.23:03:54.75#ibcon#*before return 0, iclass 5, count 0 2006.285.23:03:54.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:03:54.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:03:54.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:03:54.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:03:54.75$vck44/va=4,6 2006.285.23:03:54.75#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.23:03:54.75#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.23:03:54.75#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:54.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:03:54.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:03:54.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:03:54.80#ibcon#enter wrdev, iclass 7, count 2 2006.285.23:03:54.81#ibcon#first serial, iclass 7, count 2 2006.285.23:03:54.81#ibcon#enter sib2, iclass 7, count 2 2006.285.23:03:54.81#ibcon#flushed, iclass 7, count 2 2006.285.23:03:54.81#ibcon#about to write, iclass 7, count 2 2006.285.23:03:54.81#ibcon#wrote, iclass 7, count 2 2006.285.23:03:54.81#ibcon#about to read 3, iclass 7, count 2 2006.285.23:03:54.82#ibcon#read 3, iclass 7, count 2 2006.285.23:03:54.82#ibcon#about to read 4, iclass 7, count 2 2006.285.23:03:54.83#ibcon#read 4, iclass 7, count 2 2006.285.23:03:54.83#ibcon#about to read 5, iclass 7, count 2 2006.285.23:03:54.83#ibcon#read 5, iclass 7, count 2 2006.285.23:03:54.83#ibcon#about to read 6, iclass 7, count 2 2006.285.23:03:54.83#ibcon#read 6, iclass 7, count 2 2006.285.23:03:54.83#ibcon#end of sib2, iclass 7, count 2 2006.285.23:03:54.83#ibcon#*mode == 0, iclass 7, count 2 2006.285.23:03:54.83#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.23:03:54.83#ibcon#[25=AT04-06\r\n] 2006.285.23:03:54.83#ibcon#*before write, iclass 7, count 2 2006.285.23:03:54.83#ibcon#enter sib2, iclass 7, count 2 2006.285.23:03:54.83#ibcon#flushed, iclass 7, count 2 2006.285.23:03:54.83#ibcon#about to write, iclass 7, count 2 2006.285.23:03:54.83#ibcon#wrote, iclass 7, count 2 2006.285.23:03:54.83#ibcon#about to read 3, iclass 7, count 2 2006.285.23:03:54.85#ibcon#read 3, iclass 7, count 2 2006.285.23:03:54.85#ibcon#about to read 4, iclass 7, count 2 2006.285.23:03:54.86#ibcon#read 4, iclass 7, count 2 2006.285.23:03:54.86#ibcon#about to read 5, iclass 7, count 2 2006.285.23:03:54.86#ibcon#read 5, iclass 7, count 2 2006.285.23:03:54.86#ibcon#about to read 6, iclass 7, count 2 2006.285.23:03:54.86#ibcon#read 6, iclass 7, count 2 2006.285.23:03:54.86#ibcon#end of sib2, iclass 7, count 2 2006.285.23:03:54.86#ibcon#*after write, iclass 7, count 2 2006.285.23:03:54.86#ibcon#*before return 0, iclass 7, count 2 2006.285.23:03:54.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:03:54.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:03:54.86#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.23:03:54.86#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:54.86#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:03:54.97#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:03:54.97#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:03:54.97#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:03:54.98#ibcon#first serial, iclass 7, count 0 2006.285.23:03:54.98#ibcon#enter sib2, iclass 7, count 0 2006.285.23:03:54.98#ibcon#flushed, iclass 7, count 0 2006.285.23:03:54.98#ibcon#about to write, iclass 7, count 0 2006.285.23:03:54.98#ibcon#wrote, iclass 7, count 0 2006.285.23:03:54.98#ibcon#about to read 3, iclass 7, count 0 2006.285.23:03:54.99#ibcon#read 3, iclass 7, count 0 2006.285.23:03:54.99#ibcon#about to read 4, iclass 7, count 0 2006.285.23:03:55.00#ibcon#read 4, iclass 7, count 0 2006.285.23:03:55.00#ibcon#about to read 5, iclass 7, count 0 2006.285.23:03:55.00#ibcon#read 5, iclass 7, count 0 2006.285.23:03:55.00#ibcon#about to read 6, iclass 7, count 0 2006.285.23:03:55.00#ibcon#read 6, iclass 7, count 0 2006.285.23:03:55.00#ibcon#end of sib2, iclass 7, count 0 2006.285.23:03:55.00#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:03:55.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:03:55.00#ibcon#[25=USB\r\n] 2006.285.23:03:55.00#ibcon#*before write, iclass 7, count 0 2006.285.23:03:55.00#ibcon#enter sib2, iclass 7, count 0 2006.285.23:03:55.00#ibcon#flushed, iclass 7, count 0 2006.285.23:03:55.00#ibcon#about to write, iclass 7, count 0 2006.285.23:03:55.00#ibcon#wrote, iclass 7, count 0 2006.285.23:03:55.00#ibcon#about to read 3, iclass 7, count 0 2006.285.23:03:55.02#ibcon#read 3, iclass 7, count 0 2006.285.23:03:55.02#ibcon#about to read 4, iclass 7, count 0 2006.285.23:03:55.03#ibcon#read 4, iclass 7, count 0 2006.285.23:03:55.03#ibcon#about to read 5, iclass 7, count 0 2006.285.23:03:55.03#ibcon#read 5, iclass 7, count 0 2006.285.23:03:55.03#ibcon#about to read 6, iclass 7, count 0 2006.285.23:03:55.03#ibcon#read 6, iclass 7, count 0 2006.285.23:03:55.03#ibcon#end of sib2, iclass 7, count 0 2006.285.23:03:55.03#ibcon#*after write, iclass 7, count 0 2006.285.23:03:55.03#ibcon#*before return 0, iclass 7, count 0 2006.285.23:03:55.03#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:03:55.03#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:03:55.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:03:55.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:03:55.03$vck44/valo=5,734.99 2006.285.23:03:55.03#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.23:03:55.03#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.23:03:55.03#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:55.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:03:55.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:03:55.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:03:55.03#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:03:55.03#ibcon#first serial, iclass 11, count 0 2006.285.23:03:55.03#ibcon#enter sib2, iclass 11, count 0 2006.285.23:03:55.03#ibcon#flushed, iclass 11, count 0 2006.285.23:03:55.03#ibcon#about to write, iclass 11, count 0 2006.285.23:03:55.03#ibcon#wrote, iclass 11, count 0 2006.285.23:03:55.03#ibcon#about to read 3, iclass 11, count 0 2006.285.23:03:55.04#ibcon#read 3, iclass 11, count 0 2006.285.23:03:55.04#ibcon#about to read 4, iclass 11, count 0 2006.285.23:03:55.05#ibcon#read 4, iclass 11, count 0 2006.285.23:03:55.05#ibcon#about to read 5, iclass 11, count 0 2006.285.23:03:55.05#ibcon#read 5, iclass 11, count 0 2006.285.23:03:55.05#ibcon#about to read 6, iclass 11, count 0 2006.285.23:03:55.05#ibcon#read 6, iclass 11, count 0 2006.285.23:03:55.05#ibcon#end of sib2, iclass 11, count 0 2006.285.23:03:55.05#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:03:55.05#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:03:55.05#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.23:03:55.05#ibcon#*before write, iclass 11, count 0 2006.285.23:03:55.05#ibcon#enter sib2, iclass 11, count 0 2006.285.23:03:55.05#ibcon#flushed, iclass 11, count 0 2006.285.23:03:55.05#ibcon#about to write, iclass 11, count 0 2006.285.23:03:55.05#ibcon#wrote, iclass 11, count 0 2006.285.23:03:55.05#ibcon#about to read 3, iclass 11, count 0 2006.285.23:03:55.08#ibcon#read 3, iclass 11, count 0 2006.285.23:03:55.09#ibcon#about to read 4, iclass 11, count 0 2006.285.23:03:55.09#ibcon#read 4, iclass 11, count 0 2006.285.23:03:55.09#ibcon#about to read 5, iclass 11, count 0 2006.285.23:03:55.09#ibcon#read 5, iclass 11, count 0 2006.285.23:03:55.09#ibcon#about to read 6, iclass 11, count 0 2006.285.23:03:55.09#ibcon#read 6, iclass 11, count 0 2006.285.23:03:55.09#ibcon#end of sib2, iclass 11, count 0 2006.285.23:03:55.09#ibcon#*after write, iclass 11, count 0 2006.285.23:03:55.09#ibcon#*before return 0, iclass 11, count 0 2006.285.23:03:55.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:03:55.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:03:55.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:03:55.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:03:55.09$vck44/va=5,3 2006.285.23:03:55.09#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.23:03:55.09#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.23:03:55.09#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:55.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:03:55.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:03:55.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:03:55.15#ibcon#enter wrdev, iclass 13, count 2 2006.285.23:03:55.15#ibcon#first serial, iclass 13, count 2 2006.285.23:03:55.15#ibcon#enter sib2, iclass 13, count 2 2006.285.23:03:55.15#ibcon#flushed, iclass 13, count 2 2006.285.23:03:55.15#ibcon#about to write, iclass 13, count 2 2006.285.23:03:55.15#ibcon#wrote, iclass 13, count 2 2006.285.23:03:55.15#ibcon#about to read 3, iclass 13, count 2 2006.285.23:03:55.16#ibcon#read 3, iclass 13, count 2 2006.285.23:03:55.16#ibcon#about to read 4, iclass 13, count 2 2006.285.23:03:55.16#ibcon#read 4, iclass 13, count 2 2006.285.23:03:55.17#ibcon#about to read 5, iclass 13, count 2 2006.285.23:03:55.17#ibcon#read 5, iclass 13, count 2 2006.285.23:03:55.17#ibcon#about to read 6, iclass 13, count 2 2006.285.23:03:55.17#ibcon#read 6, iclass 13, count 2 2006.285.23:03:55.17#ibcon#end of sib2, iclass 13, count 2 2006.285.23:03:55.17#ibcon#*mode == 0, iclass 13, count 2 2006.285.23:03:55.17#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.23:03:55.17#ibcon#[25=AT05-03\r\n] 2006.285.23:03:55.17#ibcon#*before write, iclass 13, count 2 2006.285.23:03:55.17#ibcon#enter sib2, iclass 13, count 2 2006.285.23:03:55.17#ibcon#flushed, iclass 13, count 2 2006.285.23:03:55.17#ibcon#about to write, iclass 13, count 2 2006.285.23:03:55.17#ibcon#wrote, iclass 13, count 2 2006.285.23:03:55.17#ibcon#about to read 3, iclass 13, count 2 2006.285.23:03:55.19#ibcon#read 3, iclass 13, count 2 2006.285.23:03:55.20#ibcon#about to read 4, iclass 13, count 2 2006.285.23:03:55.20#ibcon#read 4, iclass 13, count 2 2006.285.23:03:55.20#ibcon#about to read 5, iclass 13, count 2 2006.285.23:03:55.20#ibcon#read 5, iclass 13, count 2 2006.285.23:03:55.20#ibcon#about to read 6, iclass 13, count 2 2006.285.23:03:55.20#ibcon#read 6, iclass 13, count 2 2006.285.23:03:55.20#ibcon#end of sib2, iclass 13, count 2 2006.285.23:03:55.20#ibcon#*after write, iclass 13, count 2 2006.285.23:03:55.20#ibcon#*before return 0, iclass 13, count 2 2006.285.23:03:55.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:03:55.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:03:55.20#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.23:03:55.20#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:55.20#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:03:55.31#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:03:55.31#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:03:55.31#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:03:55.32#ibcon#first serial, iclass 13, count 0 2006.285.23:03:55.32#ibcon#enter sib2, iclass 13, count 0 2006.285.23:03:55.32#ibcon#flushed, iclass 13, count 0 2006.285.23:03:55.32#ibcon#about to write, iclass 13, count 0 2006.285.23:03:55.32#ibcon#wrote, iclass 13, count 0 2006.285.23:03:55.32#ibcon#about to read 3, iclass 13, count 0 2006.285.23:03:55.33#ibcon#read 3, iclass 13, count 0 2006.285.23:03:55.33#ibcon#about to read 4, iclass 13, count 0 2006.285.23:03:55.33#ibcon#read 4, iclass 13, count 0 2006.285.23:03:55.34#ibcon#about to read 5, iclass 13, count 0 2006.285.23:03:55.34#ibcon#read 5, iclass 13, count 0 2006.285.23:03:55.34#ibcon#about to read 6, iclass 13, count 0 2006.285.23:03:55.34#ibcon#read 6, iclass 13, count 0 2006.285.23:03:55.34#ibcon#end of sib2, iclass 13, count 0 2006.285.23:03:55.34#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:03:55.34#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:03:55.34#ibcon#[25=USB\r\n] 2006.285.23:03:55.34#ibcon#*before write, iclass 13, count 0 2006.285.23:03:55.34#ibcon#enter sib2, iclass 13, count 0 2006.285.23:03:55.34#ibcon#flushed, iclass 13, count 0 2006.285.23:03:55.34#ibcon#about to write, iclass 13, count 0 2006.285.23:03:55.34#ibcon#wrote, iclass 13, count 0 2006.285.23:03:55.34#ibcon#about to read 3, iclass 13, count 0 2006.285.23:03:55.36#ibcon#read 3, iclass 13, count 0 2006.285.23:03:55.36#ibcon#about to read 4, iclass 13, count 0 2006.285.23:03:55.37#ibcon#read 4, iclass 13, count 0 2006.285.23:03:55.37#ibcon#about to read 5, iclass 13, count 0 2006.285.23:03:55.37#ibcon#read 5, iclass 13, count 0 2006.285.23:03:55.37#ibcon#about to read 6, iclass 13, count 0 2006.285.23:03:55.37#ibcon#read 6, iclass 13, count 0 2006.285.23:03:55.37#ibcon#end of sib2, iclass 13, count 0 2006.285.23:03:55.37#ibcon#*after write, iclass 13, count 0 2006.285.23:03:55.37#ibcon#*before return 0, iclass 13, count 0 2006.285.23:03:55.37#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:03:55.37#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:03:55.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:03:55.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:03:55.37$vck44/valo=6,814.99 2006.285.23:03:55.37#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.23:03:55.37#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.23:03:55.37#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:55.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:03:55.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:03:55.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:03:55.37#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:03:55.37#ibcon#first serial, iclass 15, count 0 2006.285.23:03:55.37#ibcon#enter sib2, iclass 15, count 0 2006.285.23:03:55.37#ibcon#flushed, iclass 15, count 0 2006.285.23:03:55.37#ibcon#about to write, iclass 15, count 0 2006.285.23:03:55.37#ibcon#wrote, iclass 15, count 0 2006.285.23:03:55.37#ibcon#about to read 3, iclass 15, count 0 2006.285.23:03:55.38#ibcon#read 3, iclass 15, count 0 2006.285.23:03:55.38#ibcon#about to read 4, iclass 15, count 0 2006.285.23:03:55.39#ibcon#read 4, iclass 15, count 0 2006.285.23:03:55.39#ibcon#about to read 5, iclass 15, count 0 2006.285.23:03:55.39#ibcon#read 5, iclass 15, count 0 2006.285.23:03:55.39#ibcon#about to read 6, iclass 15, count 0 2006.285.23:03:55.39#ibcon#read 6, iclass 15, count 0 2006.285.23:03:55.39#ibcon#end of sib2, iclass 15, count 0 2006.285.23:03:55.39#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:03:55.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:03:55.39#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.23:03:55.39#ibcon#*before write, iclass 15, count 0 2006.285.23:03:55.39#ibcon#enter sib2, iclass 15, count 0 2006.285.23:03:55.39#ibcon#flushed, iclass 15, count 0 2006.285.23:03:55.39#ibcon#about to write, iclass 15, count 0 2006.285.23:03:55.39#ibcon#wrote, iclass 15, count 0 2006.285.23:03:55.39#ibcon#about to read 3, iclass 15, count 0 2006.285.23:03:55.42#ibcon#read 3, iclass 15, count 0 2006.285.23:03:55.42#ibcon#about to read 4, iclass 15, count 0 2006.285.23:03:55.43#ibcon#read 4, iclass 15, count 0 2006.285.23:03:55.43#ibcon#about to read 5, iclass 15, count 0 2006.285.23:03:55.43#ibcon#read 5, iclass 15, count 0 2006.285.23:03:55.43#ibcon#about to read 6, iclass 15, count 0 2006.285.23:03:55.43#ibcon#read 6, iclass 15, count 0 2006.285.23:03:55.43#ibcon#end of sib2, iclass 15, count 0 2006.285.23:03:55.43#ibcon#*after write, iclass 15, count 0 2006.285.23:03:55.43#ibcon#*before return 0, iclass 15, count 0 2006.285.23:03:55.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:03:55.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:03:55.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:03:55.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:03:55.43$vck44/va=6,4 2006.285.23:03:55.43#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.23:03:55.43#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.23:03:55.43#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:55.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:03:55.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:03:55.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:03:55.49#ibcon#enter wrdev, iclass 17, count 2 2006.285.23:03:55.49#ibcon#first serial, iclass 17, count 2 2006.285.23:03:55.49#ibcon#enter sib2, iclass 17, count 2 2006.285.23:03:55.49#ibcon#flushed, iclass 17, count 2 2006.285.23:03:55.49#ibcon#about to write, iclass 17, count 2 2006.285.23:03:55.49#ibcon#wrote, iclass 17, count 2 2006.285.23:03:55.49#ibcon#about to read 3, iclass 17, count 2 2006.285.23:03:55.50#ibcon#read 3, iclass 17, count 2 2006.285.23:03:55.50#ibcon#about to read 4, iclass 17, count 2 2006.285.23:03:55.51#ibcon#read 4, iclass 17, count 2 2006.285.23:03:55.51#ibcon#about to read 5, iclass 17, count 2 2006.285.23:03:55.51#ibcon#read 5, iclass 17, count 2 2006.285.23:03:55.51#ibcon#about to read 6, iclass 17, count 2 2006.285.23:03:55.51#ibcon#read 6, iclass 17, count 2 2006.285.23:03:55.51#ibcon#end of sib2, iclass 17, count 2 2006.285.23:03:55.51#ibcon#*mode == 0, iclass 17, count 2 2006.285.23:03:55.51#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.23:03:55.51#ibcon#[25=AT06-04\r\n] 2006.285.23:03:55.51#ibcon#*before write, iclass 17, count 2 2006.285.23:03:55.51#ibcon#enter sib2, iclass 17, count 2 2006.285.23:03:55.51#ibcon#flushed, iclass 17, count 2 2006.285.23:03:55.51#ibcon#about to write, iclass 17, count 2 2006.285.23:03:55.51#ibcon#wrote, iclass 17, count 2 2006.285.23:03:55.51#ibcon#about to read 3, iclass 17, count 2 2006.285.23:03:55.53#ibcon#read 3, iclass 17, count 2 2006.285.23:03:55.54#ibcon#about to read 4, iclass 17, count 2 2006.285.23:03:55.54#ibcon#read 4, iclass 17, count 2 2006.285.23:03:55.54#ibcon#about to read 5, iclass 17, count 2 2006.285.23:03:55.54#ibcon#read 5, iclass 17, count 2 2006.285.23:03:55.54#ibcon#about to read 6, iclass 17, count 2 2006.285.23:03:55.54#ibcon#read 6, iclass 17, count 2 2006.285.23:03:55.54#ibcon#end of sib2, iclass 17, count 2 2006.285.23:03:55.54#ibcon#*after write, iclass 17, count 2 2006.285.23:03:55.54#ibcon#*before return 0, iclass 17, count 2 2006.285.23:03:55.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:03:55.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:03:55.54#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.23:03:55.54#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:55.54#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:03:55.65#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:03:55.65#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:03:55.66#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:03:55.66#ibcon#first serial, iclass 17, count 0 2006.285.23:03:55.66#ibcon#enter sib2, iclass 17, count 0 2006.285.23:03:55.66#ibcon#flushed, iclass 17, count 0 2006.285.23:03:55.66#ibcon#about to write, iclass 17, count 0 2006.285.23:03:55.66#ibcon#wrote, iclass 17, count 0 2006.285.23:03:55.66#ibcon#about to read 3, iclass 17, count 0 2006.285.23:03:55.67#ibcon#read 3, iclass 17, count 0 2006.285.23:03:55.67#ibcon#about to read 4, iclass 17, count 0 2006.285.23:03:55.68#ibcon#read 4, iclass 17, count 0 2006.285.23:03:55.68#ibcon#about to read 5, iclass 17, count 0 2006.285.23:03:55.68#ibcon#read 5, iclass 17, count 0 2006.285.23:03:55.68#ibcon#about to read 6, iclass 17, count 0 2006.285.23:03:55.68#ibcon#read 6, iclass 17, count 0 2006.285.23:03:55.68#ibcon#end of sib2, iclass 17, count 0 2006.285.23:03:55.68#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:03:55.68#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:03:55.68#ibcon#[25=USB\r\n] 2006.285.23:03:55.68#ibcon#*before write, iclass 17, count 0 2006.285.23:03:55.68#ibcon#enter sib2, iclass 17, count 0 2006.285.23:03:55.68#ibcon#flushed, iclass 17, count 0 2006.285.23:03:55.68#ibcon#about to write, iclass 17, count 0 2006.285.23:03:55.68#ibcon#wrote, iclass 17, count 0 2006.285.23:03:55.68#ibcon#about to read 3, iclass 17, count 0 2006.285.23:03:55.70#ibcon#read 3, iclass 17, count 0 2006.285.23:03:55.70#ibcon#about to read 4, iclass 17, count 0 2006.285.23:03:55.70#ibcon#read 4, iclass 17, count 0 2006.285.23:03:55.71#ibcon#about to read 5, iclass 17, count 0 2006.285.23:03:55.71#ibcon#read 5, iclass 17, count 0 2006.285.23:03:55.71#ibcon#about to read 6, iclass 17, count 0 2006.285.23:03:55.71#ibcon#read 6, iclass 17, count 0 2006.285.23:03:55.71#ibcon#end of sib2, iclass 17, count 0 2006.285.23:03:55.71#ibcon#*after write, iclass 17, count 0 2006.285.23:03:55.71#ibcon#*before return 0, iclass 17, count 0 2006.285.23:03:55.71#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:03:55.71#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:03:55.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:03:55.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:03:55.71$vck44/valo=7,864.99 2006.285.23:03:55.71#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.23:03:55.71#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.23:03:55.71#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:55.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:03:55.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:03:55.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:03:55.71#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:03:55.71#ibcon#first serial, iclass 19, count 0 2006.285.23:03:55.71#ibcon#enter sib2, iclass 19, count 0 2006.285.23:03:55.71#ibcon#flushed, iclass 19, count 0 2006.285.23:03:55.71#ibcon#about to write, iclass 19, count 0 2006.285.23:03:55.71#ibcon#wrote, iclass 19, count 0 2006.285.23:03:55.71#ibcon#about to read 3, iclass 19, count 0 2006.285.23:03:55.72#ibcon#read 3, iclass 19, count 0 2006.285.23:03:55.72#ibcon#about to read 4, iclass 19, count 0 2006.285.23:03:55.73#ibcon#read 4, iclass 19, count 0 2006.285.23:03:55.73#ibcon#about to read 5, iclass 19, count 0 2006.285.23:03:55.73#ibcon#read 5, iclass 19, count 0 2006.285.23:03:55.73#ibcon#about to read 6, iclass 19, count 0 2006.285.23:03:55.73#ibcon#read 6, iclass 19, count 0 2006.285.23:03:55.73#ibcon#end of sib2, iclass 19, count 0 2006.285.23:03:55.73#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:03:55.73#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:03:55.73#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.23:03:55.73#ibcon#*before write, iclass 19, count 0 2006.285.23:03:55.73#ibcon#enter sib2, iclass 19, count 0 2006.285.23:03:55.73#ibcon#flushed, iclass 19, count 0 2006.285.23:03:55.73#ibcon#about to write, iclass 19, count 0 2006.285.23:03:55.73#ibcon#wrote, iclass 19, count 0 2006.285.23:03:55.73#ibcon#about to read 3, iclass 19, count 0 2006.285.23:03:55.76#ibcon#read 3, iclass 19, count 0 2006.285.23:03:55.76#ibcon#about to read 4, iclass 19, count 0 2006.285.23:03:55.76#ibcon#read 4, iclass 19, count 0 2006.285.23:03:55.77#ibcon#about to read 5, iclass 19, count 0 2006.285.23:03:55.77#ibcon#read 5, iclass 19, count 0 2006.285.23:03:55.77#ibcon#about to read 6, iclass 19, count 0 2006.285.23:03:55.77#ibcon#read 6, iclass 19, count 0 2006.285.23:03:55.77#ibcon#end of sib2, iclass 19, count 0 2006.285.23:03:55.77#ibcon#*after write, iclass 19, count 0 2006.285.23:03:55.77#ibcon#*before return 0, iclass 19, count 0 2006.285.23:03:55.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:03:55.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:03:55.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:03:55.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:03:55.77$vck44/va=7,4 2006.285.23:03:55.77#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.23:03:55.77#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.23:03:55.77#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:55.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:03:55.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:03:55.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:03:55.82#ibcon#enter wrdev, iclass 21, count 2 2006.285.23:03:55.83#ibcon#first serial, iclass 21, count 2 2006.285.23:03:55.83#ibcon#enter sib2, iclass 21, count 2 2006.285.23:03:55.83#ibcon#flushed, iclass 21, count 2 2006.285.23:03:55.83#ibcon#about to write, iclass 21, count 2 2006.285.23:03:55.83#ibcon#wrote, iclass 21, count 2 2006.285.23:03:55.83#ibcon#about to read 3, iclass 21, count 2 2006.285.23:03:55.84#ibcon#read 3, iclass 21, count 2 2006.285.23:03:55.84#ibcon#about to read 4, iclass 21, count 2 2006.285.23:03:55.84#ibcon#read 4, iclass 21, count 2 2006.285.23:03:55.85#ibcon#about to read 5, iclass 21, count 2 2006.285.23:03:55.85#ibcon#read 5, iclass 21, count 2 2006.285.23:03:55.85#ibcon#about to read 6, iclass 21, count 2 2006.285.23:03:55.85#ibcon#read 6, iclass 21, count 2 2006.285.23:03:55.85#ibcon#end of sib2, iclass 21, count 2 2006.285.23:03:55.85#ibcon#*mode == 0, iclass 21, count 2 2006.285.23:03:55.85#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.23:03:55.85#ibcon#[25=AT07-04\r\n] 2006.285.23:03:55.85#ibcon#*before write, iclass 21, count 2 2006.285.23:03:55.85#ibcon#enter sib2, iclass 21, count 2 2006.285.23:03:55.85#ibcon#flushed, iclass 21, count 2 2006.285.23:03:55.85#ibcon#about to write, iclass 21, count 2 2006.285.23:03:55.85#ibcon#wrote, iclass 21, count 2 2006.285.23:03:55.85#ibcon#about to read 3, iclass 21, count 2 2006.285.23:03:55.87#ibcon#read 3, iclass 21, count 2 2006.285.23:03:55.87#ibcon#about to read 4, iclass 21, count 2 2006.285.23:03:55.88#ibcon#read 4, iclass 21, count 2 2006.285.23:03:55.88#ibcon#about to read 5, iclass 21, count 2 2006.285.23:03:55.88#ibcon#read 5, iclass 21, count 2 2006.285.23:03:55.88#ibcon#about to read 6, iclass 21, count 2 2006.285.23:03:55.88#ibcon#read 6, iclass 21, count 2 2006.285.23:03:55.88#ibcon#end of sib2, iclass 21, count 2 2006.285.23:03:55.88#ibcon#*after write, iclass 21, count 2 2006.285.23:03:55.88#ibcon#*before return 0, iclass 21, count 2 2006.285.23:03:55.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:03:55.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:03:55.88#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.23:03:55.88#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:55.88#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:03:55.99#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:03:55.99#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:03:55.99#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:03:56.00#ibcon#first serial, iclass 21, count 0 2006.285.23:03:56.00#ibcon#enter sib2, iclass 21, count 0 2006.285.23:03:56.00#ibcon#flushed, iclass 21, count 0 2006.285.23:03:56.00#ibcon#about to write, iclass 21, count 0 2006.285.23:03:56.00#ibcon#wrote, iclass 21, count 0 2006.285.23:03:56.00#ibcon#about to read 3, iclass 21, count 0 2006.285.23:03:56.01#ibcon#read 3, iclass 21, count 0 2006.285.23:03:56.01#ibcon#about to read 4, iclass 21, count 0 2006.285.23:03:56.02#ibcon#read 4, iclass 21, count 0 2006.285.23:03:56.02#ibcon#about to read 5, iclass 21, count 0 2006.285.23:03:56.02#ibcon#read 5, iclass 21, count 0 2006.285.23:03:56.02#ibcon#about to read 6, iclass 21, count 0 2006.285.23:03:56.02#ibcon#read 6, iclass 21, count 0 2006.285.23:03:56.02#ibcon#end of sib2, iclass 21, count 0 2006.285.23:03:56.02#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:03:56.02#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:03:56.02#ibcon#[25=USB\r\n] 2006.285.23:03:56.02#ibcon#*before write, iclass 21, count 0 2006.285.23:03:56.02#ibcon#enter sib2, iclass 21, count 0 2006.285.23:03:56.02#ibcon#flushed, iclass 21, count 0 2006.285.23:03:56.02#ibcon#about to write, iclass 21, count 0 2006.285.23:03:56.02#ibcon#wrote, iclass 21, count 0 2006.285.23:03:56.02#ibcon#about to read 3, iclass 21, count 0 2006.285.23:03:56.04#ibcon#read 3, iclass 21, count 0 2006.285.23:03:56.04#ibcon#about to read 4, iclass 21, count 0 2006.285.23:03:56.05#ibcon#read 4, iclass 21, count 0 2006.285.23:03:56.05#ibcon#about to read 5, iclass 21, count 0 2006.285.23:03:56.05#ibcon#read 5, iclass 21, count 0 2006.285.23:03:56.05#ibcon#about to read 6, iclass 21, count 0 2006.285.23:03:56.05#ibcon#read 6, iclass 21, count 0 2006.285.23:03:56.05#ibcon#end of sib2, iclass 21, count 0 2006.285.23:03:56.05#ibcon#*after write, iclass 21, count 0 2006.285.23:03:56.05#ibcon#*before return 0, iclass 21, count 0 2006.285.23:03:56.05#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:03:56.05#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:03:56.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:03:56.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:03:56.05$vck44/valo=8,884.99 2006.285.23:03:56.05#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.23:03:56.05#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.23:03:56.05#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:56.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:03:56.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:03:56.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:03:56.05#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:03:56.05#ibcon#first serial, iclass 23, count 0 2006.285.23:03:56.05#ibcon#enter sib2, iclass 23, count 0 2006.285.23:03:56.05#ibcon#flushed, iclass 23, count 0 2006.285.23:03:56.05#ibcon#about to write, iclass 23, count 0 2006.285.23:03:56.05#ibcon#wrote, iclass 23, count 0 2006.285.23:03:56.05#ibcon#about to read 3, iclass 23, count 0 2006.285.23:03:56.06#ibcon#read 3, iclass 23, count 0 2006.285.23:03:56.07#ibcon#about to read 4, iclass 23, count 0 2006.285.23:03:56.07#ibcon#read 4, iclass 23, count 0 2006.285.23:03:56.07#ibcon#about to read 5, iclass 23, count 0 2006.285.23:03:56.07#ibcon#read 5, iclass 23, count 0 2006.285.23:03:56.07#ibcon#about to read 6, iclass 23, count 0 2006.285.23:03:56.07#ibcon#read 6, iclass 23, count 0 2006.285.23:03:56.07#ibcon#end of sib2, iclass 23, count 0 2006.285.23:03:56.07#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:03:56.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:03:56.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.23:03:56.07#ibcon#*before write, iclass 23, count 0 2006.285.23:03:56.07#ibcon#enter sib2, iclass 23, count 0 2006.285.23:03:56.07#ibcon#flushed, iclass 23, count 0 2006.285.23:03:56.07#ibcon#about to write, iclass 23, count 0 2006.285.23:03:56.07#ibcon#wrote, iclass 23, count 0 2006.285.23:03:56.07#ibcon#about to read 3, iclass 23, count 0 2006.285.23:03:56.10#ibcon#read 3, iclass 23, count 0 2006.285.23:03:56.11#ibcon#about to read 4, iclass 23, count 0 2006.285.23:03:56.11#ibcon#read 4, iclass 23, count 0 2006.285.23:03:56.11#ibcon#about to read 5, iclass 23, count 0 2006.285.23:03:56.11#ibcon#read 5, iclass 23, count 0 2006.285.23:03:56.11#ibcon#about to read 6, iclass 23, count 0 2006.285.23:03:56.11#ibcon#read 6, iclass 23, count 0 2006.285.23:03:56.11#ibcon#end of sib2, iclass 23, count 0 2006.285.23:03:56.11#ibcon#*after write, iclass 23, count 0 2006.285.23:03:56.11#ibcon#*before return 0, iclass 23, count 0 2006.285.23:03:56.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:03:56.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:03:56.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:03:56.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:03:56.11$vck44/va=8,3 2006.285.23:03:56.11#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.23:03:56.11#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.23:03:56.11#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:56.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:03:56.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:03:56.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:03:56.16#ibcon#enter wrdev, iclass 25, count 2 2006.285.23:03:56.17#ibcon#first serial, iclass 25, count 2 2006.285.23:03:56.17#ibcon#enter sib2, iclass 25, count 2 2006.285.23:03:56.17#ibcon#flushed, iclass 25, count 2 2006.285.23:03:56.17#ibcon#about to write, iclass 25, count 2 2006.285.23:03:56.17#ibcon#wrote, iclass 25, count 2 2006.285.23:03:56.17#ibcon#about to read 3, iclass 25, count 2 2006.285.23:03:56.18#ibcon#read 3, iclass 25, count 2 2006.285.23:03:56.18#ibcon#about to read 4, iclass 25, count 2 2006.285.23:03:56.18#ibcon#read 4, iclass 25, count 2 2006.285.23:03:56.19#ibcon#about to read 5, iclass 25, count 2 2006.285.23:03:56.19#ibcon#read 5, iclass 25, count 2 2006.285.23:03:56.19#ibcon#about to read 6, iclass 25, count 2 2006.285.23:03:56.19#ibcon#read 6, iclass 25, count 2 2006.285.23:03:56.19#ibcon#end of sib2, iclass 25, count 2 2006.285.23:03:56.19#ibcon#*mode == 0, iclass 25, count 2 2006.285.23:03:56.19#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.23:03:56.19#ibcon#[25=AT08-03\r\n] 2006.285.23:03:56.19#ibcon#*before write, iclass 25, count 2 2006.285.23:03:56.19#ibcon#enter sib2, iclass 25, count 2 2006.285.23:03:56.19#ibcon#flushed, iclass 25, count 2 2006.285.23:03:56.19#ibcon#about to write, iclass 25, count 2 2006.285.23:03:56.19#ibcon#wrote, iclass 25, count 2 2006.285.23:03:56.19#ibcon#about to read 3, iclass 25, count 2 2006.285.23:03:56.21#ibcon#read 3, iclass 25, count 2 2006.285.23:03:56.21#ibcon#about to read 4, iclass 25, count 2 2006.285.23:03:56.22#ibcon#read 4, iclass 25, count 2 2006.285.23:03:56.22#ibcon#about to read 5, iclass 25, count 2 2006.285.23:03:56.22#ibcon#read 5, iclass 25, count 2 2006.285.23:03:56.22#ibcon#about to read 6, iclass 25, count 2 2006.285.23:03:56.22#ibcon#read 6, iclass 25, count 2 2006.285.23:03:56.22#ibcon#end of sib2, iclass 25, count 2 2006.285.23:03:56.22#ibcon#*after write, iclass 25, count 2 2006.285.23:03:56.22#ibcon#*before return 0, iclass 25, count 2 2006.285.23:03:56.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:03:56.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:03:56.22#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.23:03:56.22#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:56.22#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:03:56.33#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:03:56.33#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:03:56.33#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:03:56.34#ibcon#first serial, iclass 25, count 0 2006.285.23:03:56.34#ibcon#enter sib2, iclass 25, count 0 2006.285.23:03:56.34#ibcon#flushed, iclass 25, count 0 2006.285.23:03:56.34#ibcon#about to write, iclass 25, count 0 2006.285.23:03:56.34#ibcon#wrote, iclass 25, count 0 2006.285.23:03:56.34#ibcon#about to read 3, iclass 25, count 0 2006.285.23:03:56.35#ibcon#read 3, iclass 25, count 0 2006.285.23:03:56.35#ibcon#about to read 4, iclass 25, count 0 2006.285.23:03:56.35#ibcon#read 4, iclass 25, count 0 2006.285.23:03:56.36#ibcon#about to read 5, iclass 25, count 0 2006.285.23:03:56.36#ibcon#read 5, iclass 25, count 0 2006.285.23:03:56.36#ibcon#about to read 6, iclass 25, count 0 2006.285.23:03:56.36#ibcon#read 6, iclass 25, count 0 2006.285.23:03:56.36#ibcon#end of sib2, iclass 25, count 0 2006.285.23:03:56.36#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:03:56.36#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:03:56.36#ibcon#[25=USB\r\n] 2006.285.23:03:56.36#ibcon#*before write, iclass 25, count 0 2006.285.23:03:56.36#ibcon#enter sib2, iclass 25, count 0 2006.285.23:03:56.36#ibcon#flushed, iclass 25, count 0 2006.285.23:03:56.36#ibcon#about to write, iclass 25, count 0 2006.285.23:03:56.36#ibcon#wrote, iclass 25, count 0 2006.285.23:03:56.36#ibcon#about to read 3, iclass 25, count 0 2006.285.23:03:56.38#ibcon#read 3, iclass 25, count 0 2006.285.23:03:56.38#ibcon#about to read 4, iclass 25, count 0 2006.285.23:03:56.38#ibcon#read 4, iclass 25, count 0 2006.285.23:03:56.39#ibcon#about to read 5, iclass 25, count 0 2006.285.23:03:56.39#ibcon#read 5, iclass 25, count 0 2006.285.23:03:56.39#ibcon#about to read 6, iclass 25, count 0 2006.285.23:03:56.39#ibcon#read 6, iclass 25, count 0 2006.285.23:03:56.39#ibcon#end of sib2, iclass 25, count 0 2006.285.23:03:56.39#ibcon#*after write, iclass 25, count 0 2006.285.23:03:56.39#ibcon#*before return 0, iclass 25, count 0 2006.285.23:03:56.39#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:03:56.39#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:03:56.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:03:56.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:03:56.39$vck44/vblo=1,629.99 2006.285.23:03:56.39#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.23:03:56.39#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.23:03:56.39#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:56.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:03:56.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:03:56.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:03:56.39#ibcon#enter wrdev, iclass 27, count 0 2006.285.23:03:56.39#ibcon#first serial, iclass 27, count 0 2006.285.23:03:56.39#ibcon#enter sib2, iclass 27, count 0 2006.285.23:03:56.39#ibcon#flushed, iclass 27, count 0 2006.285.23:03:56.39#ibcon#about to write, iclass 27, count 0 2006.285.23:03:56.39#ibcon#wrote, iclass 27, count 0 2006.285.23:03:56.39#ibcon#about to read 3, iclass 27, count 0 2006.285.23:03:56.40#ibcon#read 3, iclass 27, count 0 2006.285.23:03:56.40#ibcon#about to read 4, iclass 27, count 0 2006.285.23:03:56.41#ibcon#read 4, iclass 27, count 0 2006.285.23:03:56.41#ibcon#about to read 5, iclass 27, count 0 2006.285.23:03:56.41#ibcon#read 5, iclass 27, count 0 2006.285.23:03:56.41#ibcon#about to read 6, iclass 27, count 0 2006.285.23:03:56.41#ibcon#read 6, iclass 27, count 0 2006.285.23:03:56.41#ibcon#end of sib2, iclass 27, count 0 2006.285.23:03:56.41#ibcon#*mode == 0, iclass 27, count 0 2006.285.23:03:56.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.23:03:56.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.23:03:56.41#ibcon#*before write, iclass 27, count 0 2006.285.23:03:56.41#ibcon#enter sib2, iclass 27, count 0 2006.285.23:03:56.41#ibcon#flushed, iclass 27, count 0 2006.285.23:03:56.41#ibcon#about to write, iclass 27, count 0 2006.285.23:03:56.41#ibcon#wrote, iclass 27, count 0 2006.285.23:03:56.41#ibcon#about to read 3, iclass 27, count 0 2006.285.23:03:56.44#ibcon#read 3, iclass 27, count 0 2006.285.23:03:56.44#ibcon#about to read 4, iclass 27, count 0 2006.285.23:03:56.44#ibcon#read 4, iclass 27, count 0 2006.285.23:03:56.45#ibcon#about to read 5, iclass 27, count 0 2006.285.23:03:56.45#ibcon#read 5, iclass 27, count 0 2006.285.23:03:56.45#ibcon#about to read 6, iclass 27, count 0 2006.285.23:03:56.45#ibcon#read 6, iclass 27, count 0 2006.285.23:03:56.45#ibcon#end of sib2, iclass 27, count 0 2006.285.23:03:56.45#ibcon#*after write, iclass 27, count 0 2006.285.23:03:56.45#ibcon#*before return 0, iclass 27, count 0 2006.285.23:03:56.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:03:56.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:03:56.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.23:03:56.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.23:03:56.45$vck44/vb=1,4 2006.285.23:03:56.45#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.23:03:56.45#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.23:03:56.45#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:56.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:03:56.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:03:56.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:03:56.45#ibcon#enter wrdev, iclass 29, count 2 2006.285.23:03:56.45#ibcon#first serial, iclass 29, count 2 2006.285.23:03:56.45#ibcon#enter sib2, iclass 29, count 2 2006.285.23:03:56.45#ibcon#flushed, iclass 29, count 2 2006.285.23:03:56.45#ibcon#about to write, iclass 29, count 2 2006.285.23:03:56.45#ibcon#wrote, iclass 29, count 2 2006.285.23:03:56.45#ibcon#about to read 3, iclass 29, count 2 2006.285.23:03:56.46#ibcon#read 3, iclass 29, count 2 2006.285.23:03:56.46#ibcon#about to read 4, iclass 29, count 2 2006.285.23:03:56.47#ibcon#read 4, iclass 29, count 2 2006.285.23:03:56.47#ibcon#about to read 5, iclass 29, count 2 2006.285.23:03:56.47#ibcon#read 5, iclass 29, count 2 2006.285.23:03:56.47#ibcon#about to read 6, iclass 29, count 2 2006.285.23:03:56.47#ibcon#read 6, iclass 29, count 2 2006.285.23:03:56.47#ibcon#end of sib2, iclass 29, count 2 2006.285.23:03:56.47#ibcon#*mode == 0, iclass 29, count 2 2006.285.23:03:56.47#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.23:03:56.47#ibcon#[27=AT01-04\r\n] 2006.285.23:03:56.47#ibcon#*before write, iclass 29, count 2 2006.285.23:03:56.47#ibcon#enter sib2, iclass 29, count 2 2006.285.23:03:56.47#ibcon#flushed, iclass 29, count 2 2006.285.23:03:56.47#ibcon#about to write, iclass 29, count 2 2006.285.23:03:56.47#ibcon#wrote, iclass 29, count 2 2006.285.23:03:56.47#ibcon#about to read 3, iclass 29, count 2 2006.285.23:03:56.49#ibcon#read 3, iclass 29, count 2 2006.285.23:03:56.50#ibcon#about to read 4, iclass 29, count 2 2006.285.23:03:56.50#ibcon#read 4, iclass 29, count 2 2006.285.23:03:56.50#ibcon#about to read 5, iclass 29, count 2 2006.285.23:03:56.50#ibcon#read 5, iclass 29, count 2 2006.285.23:03:56.50#ibcon#about to read 6, iclass 29, count 2 2006.285.23:03:56.50#ibcon#read 6, iclass 29, count 2 2006.285.23:03:56.50#ibcon#end of sib2, iclass 29, count 2 2006.285.23:03:56.50#ibcon#*after write, iclass 29, count 2 2006.285.23:03:56.50#ibcon#*before return 0, iclass 29, count 2 2006.285.23:03:56.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:03:56.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:03:56.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.23:03:56.50#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:56.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:03:56.61#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:03:56.61#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:03:56.62#ibcon#enter wrdev, iclass 29, count 0 2006.285.23:03:56.62#ibcon#first serial, iclass 29, count 0 2006.285.23:03:56.62#ibcon#enter sib2, iclass 29, count 0 2006.285.23:03:56.62#ibcon#flushed, iclass 29, count 0 2006.285.23:03:56.62#ibcon#about to write, iclass 29, count 0 2006.285.23:03:56.62#ibcon#wrote, iclass 29, count 0 2006.285.23:03:56.62#ibcon#about to read 3, iclass 29, count 0 2006.285.23:03:56.63#ibcon#read 3, iclass 29, count 0 2006.285.23:03:56.63#ibcon#about to read 4, iclass 29, count 0 2006.285.23:03:56.64#ibcon#read 4, iclass 29, count 0 2006.285.23:03:56.64#ibcon#about to read 5, iclass 29, count 0 2006.285.23:03:56.64#ibcon#read 5, iclass 29, count 0 2006.285.23:03:56.64#ibcon#about to read 6, iclass 29, count 0 2006.285.23:03:56.64#ibcon#read 6, iclass 29, count 0 2006.285.23:03:56.64#ibcon#end of sib2, iclass 29, count 0 2006.285.23:03:56.64#ibcon#*mode == 0, iclass 29, count 0 2006.285.23:03:56.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.23:03:56.64#ibcon#[27=USB\r\n] 2006.285.23:03:56.64#ibcon#*before write, iclass 29, count 0 2006.285.23:03:56.64#ibcon#enter sib2, iclass 29, count 0 2006.285.23:03:56.64#ibcon#flushed, iclass 29, count 0 2006.285.23:03:56.64#ibcon#about to write, iclass 29, count 0 2006.285.23:03:56.64#ibcon#wrote, iclass 29, count 0 2006.285.23:03:56.64#ibcon#about to read 3, iclass 29, count 0 2006.285.23:03:56.66#ibcon#read 3, iclass 29, count 0 2006.285.23:03:56.66#ibcon#about to read 4, iclass 29, count 0 2006.285.23:03:56.66#ibcon#read 4, iclass 29, count 0 2006.285.23:03:56.67#ibcon#about to read 5, iclass 29, count 0 2006.285.23:03:56.67#ibcon#read 5, iclass 29, count 0 2006.285.23:03:56.67#ibcon#about to read 6, iclass 29, count 0 2006.285.23:03:56.67#ibcon#read 6, iclass 29, count 0 2006.285.23:03:56.67#ibcon#end of sib2, iclass 29, count 0 2006.285.23:03:56.67#ibcon#*after write, iclass 29, count 0 2006.285.23:03:56.67#ibcon#*before return 0, iclass 29, count 0 2006.285.23:03:56.67#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:03:56.67#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:03:56.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.23:03:56.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.23:03:56.67$vck44/vblo=2,634.99 2006.285.23:03:56.67#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.23:03:56.67#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.23:03:56.67#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:56.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:03:56.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:03:56.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:03:56.67#ibcon#enter wrdev, iclass 31, count 0 2006.285.23:03:56.67#ibcon#first serial, iclass 31, count 0 2006.285.23:03:56.67#ibcon#enter sib2, iclass 31, count 0 2006.285.23:03:56.67#ibcon#flushed, iclass 31, count 0 2006.285.23:03:56.67#ibcon#about to write, iclass 31, count 0 2006.285.23:03:56.67#ibcon#wrote, iclass 31, count 0 2006.285.23:03:56.67#ibcon#about to read 3, iclass 31, count 0 2006.285.23:03:56.68#ibcon#read 3, iclass 31, count 0 2006.285.23:03:56.68#ibcon#about to read 4, iclass 31, count 0 2006.285.23:03:56.69#ibcon#read 4, iclass 31, count 0 2006.285.23:03:56.69#ibcon#about to read 5, iclass 31, count 0 2006.285.23:03:56.69#ibcon#read 5, iclass 31, count 0 2006.285.23:03:56.69#ibcon#about to read 6, iclass 31, count 0 2006.285.23:03:56.69#ibcon#read 6, iclass 31, count 0 2006.285.23:03:56.69#ibcon#end of sib2, iclass 31, count 0 2006.285.23:03:56.69#ibcon#*mode == 0, iclass 31, count 0 2006.285.23:03:56.69#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.23:03:56.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.23:03:56.69#ibcon#*before write, iclass 31, count 0 2006.285.23:03:56.69#ibcon#enter sib2, iclass 31, count 0 2006.285.23:03:56.69#ibcon#flushed, iclass 31, count 0 2006.285.23:03:56.69#ibcon#about to write, iclass 31, count 0 2006.285.23:03:56.69#ibcon#wrote, iclass 31, count 0 2006.285.23:03:56.69#ibcon#about to read 3, iclass 31, count 0 2006.285.23:03:56.72#ibcon#read 3, iclass 31, count 0 2006.285.23:03:56.72#ibcon#about to read 4, iclass 31, count 0 2006.285.23:03:56.72#ibcon#read 4, iclass 31, count 0 2006.285.23:03:56.73#ibcon#about to read 5, iclass 31, count 0 2006.285.23:03:56.73#ibcon#read 5, iclass 31, count 0 2006.285.23:03:56.73#ibcon#about to read 6, iclass 31, count 0 2006.285.23:03:56.73#ibcon#read 6, iclass 31, count 0 2006.285.23:03:56.73#ibcon#end of sib2, iclass 31, count 0 2006.285.23:03:56.73#ibcon#*after write, iclass 31, count 0 2006.285.23:03:56.73#ibcon#*before return 0, iclass 31, count 0 2006.285.23:03:56.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:03:56.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:03:56.73#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.23:03:56.73#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.23:03:56.73$vck44/vb=2,5 2006.285.23:03:56.73#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.23:03:56.73#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.23:03:56.73#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:56.73#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:03:56.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:03:56.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:03:56.79#ibcon#enter wrdev, iclass 33, count 2 2006.285.23:03:56.79#ibcon#first serial, iclass 33, count 2 2006.285.23:03:56.79#ibcon#enter sib2, iclass 33, count 2 2006.285.23:03:56.79#ibcon#flushed, iclass 33, count 2 2006.285.23:03:56.79#ibcon#about to write, iclass 33, count 2 2006.285.23:03:56.79#ibcon#wrote, iclass 33, count 2 2006.285.23:03:56.79#ibcon#about to read 3, iclass 33, count 2 2006.285.23:03:56.80#ibcon#read 3, iclass 33, count 2 2006.285.23:03:56.80#ibcon#about to read 4, iclass 33, count 2 2006.285.23:03:56.80#ibcon#read 4, iclass 33, count 2 2006.285.23:03:56.81#ibcon#about to read 5, iclass 33, count 2 2006.285.23:03:56.81#ibcon#read 5, iclass 33, count 2 2006.285.23:03:56.81#ibcon#about to read 6, iclass 33, count 2 2006.285.23:03:56.81#ibcon#read 6, iclass 33, count 2 2006.285.23:03:56.81#ibcon#end of sib2, iclass 33, count 2 2006.285.23:03:56.81#ibcon#*mode == 0, iclass 33, count 2 2006.285.23:03:56.81#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.23:03:56.81#ibcon#[27=AT02-05\r\n] 2006.285.23:03:56.81#ibcon#*before write, iclass 33, count 2 2006.285.23:03:56.81#ibcon#enter sib2, iclass 33, count 2 2006.285.23:03:56.81#ibcon#flushed, iclass 33, count 2 2006.285.23:03:56.81#ibcon#about to write, iclass 33, count 2 2006.285.23:03:56.81#ibcon#wrote, iclass 33, count 2 2006.285.23:03:56.81#ibcon#about to read 3, iclass 33, count 2 2006.285.23:03:56.83#ibcon#read 3, iclass 33, count 2 2006.285.23:03:56.84#ibcon#about to read 4, iclass 33, count 2 2006.285.23:03:56.84#ibcon#read 4, iclass 33, count 2 2006.285.23:03:56.84#ibcon#about to read 5, iclass 33, count 2 2006.285.23:03:56.84#ibcon#read 5, iclass 33, count 2 2006.285.23:03:56.84#ibcon#about to read 6, iclass 33, count 2 2006.285.23:03:56.84#ibcon#read 6, iclass 33, count 2 2006.285.23:03:56.84#ibcon#end of sib2, iclass 33, count 2 2006.285.23:03:56.84#ibcon#*after write, iclass 33, count 2 2006.285.23:03:56.84#ibcon#*before return 0, iclass 33, count 2 2006.285.23:03:56.84#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:03:56.84#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:03:56.84#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.23:03:56.84#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:56.84#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:03:56.95#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:03:56.95#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:03:56.95#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:03:56.96#ibcon#first serial, iclass 33, count 0 2006.285.23:03:56.96#ibcon#enter sib2, iclass 33, count 0 2006.285.23:03:56.96#ibcon#flushed, iclass 33, count 0 2006.285.23:03:56.96#ibcon#about to write, iclass 33, count 0 2006.285.23:03:56.96#ibcon#wrote, iclass 33, count 0 2006.285.23:03:56.96#ibcon#about to read 3, iclass 33, count 0 2006.285.23:03:56.97#ibcon#read 3, iclass 33, count 0 2006.285.23:03:56.97#ibcon#about to read 4, iclass 33, count 0 2006.285.23:03:56.98#ibcon#read 4, iclass 33, count 0 2006.285.23:03:56.98#ibcon#about to read 5, iclass 33, count 0 2006.285.23:03:56.98#ibcon#read 5, iclass 33, count 0 2006.285.23:03:56.98#ibcon#about to read 6, iclass 33, count 0 2006.285.23:03:56.98#ibcon#read 6, iclass 33, count 0 2006.285.23:03:56.98#ibcon#end of sib2, iclass 33, count 0 2006.285.23:03:56.98#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:03:56.98#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:03:56.98#ibcon#[27=USB\r\n] 2006.285.23:03:56.98#ibcon#*before write, iclass 33, count 0 2006.285.23:03:56.98#ibcon#enter sib2, iclass 33, count 0 2006.285.23:03:56.98#ibcon#flushed, iclass 33, count 0 2006.285.23:03:56.98#ibcon#about to write, iclass 33, count 0 2006.285.23:03:56.98#ibcon#wrote, iclass 33, count 0 2006.285.23:03:56.98#ibcon#about to read 3, iclass 33, count 0 2006.285.23:03:57.01#ibcon#read 3, iclass 33, count 0 2006.285.23:03:57.01#ibcon#about to read 4, iclass 33, count 0 2006.285.23:03:57.01#ibcon#read 4, iclass 33, count 0 2006.285.23:03:57.01#ibcon#about to read 5, iclass 33, count 0 2006.285.23:03:57.01#ibcon#read 5, iclass 33, count 0 2006.285.23:03:57.01#ibcon#about to read 6, iclass 33, count 0 2006.285.23:03:57.01#ibcon#read 6, iclass 33, count 0 2006.285.23:03:57.01#ibcon#end of sib2, iclass 33, count 0 2006.285.23:03:57.01#ibcon#*after write, iclass 33, count 0 2006.285.23:03:57.01#ibcon#*before return 0, iclass 33, count 0 2006.285.23:03:57.01#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:03:57.01#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:03:57.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:03:57.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:03:57.01$vck44/vblo=3,649.99 2006.285.23:03:57.01#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.23:03:57.01#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.23:03:57.01#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:57.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:03:57.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:03:57.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:03:57.01#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:03:57.01#ibcon#first serial, iclass 35, count 0 2006.285.23:03:57.01#ibcon#enter sib2, iclass 35, count 0 2006.285.23:03:57.01#ibcon#flushed, iclass 35, count 0 2006.285.23:03:57.01#ibcon#about to write, iclass 35, count 0 2006.285.23:03:57.01#ibcon#wrote, iclass 35, count 0 2006.285.23:03:57.01#ibcon#about to read 3, iclass 35, count 0 2006.285.23:03:57.02#ibcon#read 3, iclass 35, count 0 2006.285.23:03:57.02#ibcon#about to read 4, iclass 35, count 0 2006.285.23:03:57.03#ibcon#read 4, iclass 35, count 0 2006.285.23:03:57.03#ibcon#about to read 5, iclass 35, count 0 2006.285.23:03:57.03#ibcon#read 5, iclass 35, count 0 2006.285.23:03:57.03#ibcon#about to read 6, iclass 35, count 0 2006.285.23:03:57.03#ibcon#read 6, iclass 35, count 0 2006.285.23:03:57.03#ibcon#end of sib2, iclass 35, count 0 2006.285.23:03:57.03#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:03:57.03#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:03:57.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.23:03:57.03#ibcon#*before write, iclass 35, count 0 2006.285.23:03:57.03#ibcon#enter sib2, iclass 35, count 0 2006.285.23:03:57.03#ibcon#flushed, iclass 35, count 0 2006.285.23:03:57.03#ibcon#about to write, iclass 35, count 0 2006.285.23:03:57.03#ibcon#wrote, iclass 35, count 0 2006.285.23:03:57.03#ibcon#about to read 3, iclass 35, count 0 2006.285.23:03:57.06#ibcon#read 3, iclass 35, count 0 2006.285.23:03:57.06#ibcon#about to read 4, iclass 35, count 0 2006.285.23:03:57.07#ibcon#read 4, iclass 35, count 0 2006.285.23:03:57.07#ibcon#about to read 5, iclass 35, count 0 2006.285.23:03:57.07#ibcon#read 5, iclass 35, count 0 2006.285.23:03:57.07#ibcon#about to read 6, iclass 35, count 0 2006.285.23:03:57.07#ibcon#read 6, iclass 35, count 0 2006.285.23:03:57.07#ibcon#end of sib2, iclass 35, count 0 2006.285.23:03:57.07#ibcon#*after write, iclass 35, count 0 2006.285.23:03:57.07#ibcon#*before return 0, iclass 35, count 0 2006.285.23:03:57.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:03:57.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:03:57.07#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:03:57.07#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:03:57.07$vck44/vb=3,4 2006.285.23:03:57.07#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.23:03:57.07#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.23:03:57.07#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:57.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:03:57.12#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:03:57.12#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:03:57.12#ibcon#enter wrdev, iclass 37, count 2 2006.285.23:03:57.13#ibcon#first serial, iclass 37, count 2 2006.285.23:03:57.13#ibcon#enter sib2, iclass 37, count 2 2006.285.23:03:57.13#ibcon#flushed, iclass 37, count 2 2006.285.23:03:57.13#ibcon#about to write, iclass 37, count 2 2006.285.23:03:57.13#ibcon#wrote, iclass 37, count 2 2006.285.23:03:57.13#ibcon#about to read 3, iclass 37, count 2 2006.285.23:03:57.14#ibcon#read 3, iclass 37, count 2 2006.285.23:03:57.14#ibcon#about to read 4, iclass 37, count 2 2006.285.23:03:57.15#ibcon#read 4, iclass 37, count 2 2006.285.23:03:57.15#ibcon#about to read 5, iclass 37, count 2 2006.285.23:03:57.15#ibcon#read 5, iclass 37, count 2 2006.285.23:03:57.15#ibcon#about to read 6, iclass 37, count 2 2006.285.23:03:57.15#ibcon#read 6, iclass 37, count 2 2006.285.23:03:57.15#ibcon#end of sib2, iclass 37, count 2 2006.285.23:03:57.15#ibcon#*mode == 0, iclass 37, count 2 2006.285.23:03:57.15#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.23:03:57.15#ibcon#[27=AT03-04\r\n] 2006.285.23:03:57.15#ibcon#*before write, iclass 37, count 2 2006.285.23:03:57.15#ibcon#enter sib2, iclass 37, count 2 2006.285.23:03:57.15#ibcon#flushed, iclass 37, count 2 2006.285.23:03:57.15#ibcon#about to write, iclass 37, count 2 2006.285.23:03:57.15#ibcon#wrote, iclass 37, count 2 2006.285.23:03:57.15#ibcon#about to read 3, iclass 37, count 2 2006.285.23:03:57.17#ibcon#read 3, iclass 37, count 2 2006.285.23:03:57.17#ibcon#about to read 4, iclass 37, count 2 2006.285.23:03:57.17#ibcon#read 4, iclass 37, count 2 2006.285.23:03:57.18#ibcon#about to read 5, iclass 37, count 2 2006.285.23:03:57.18#ibcon#read 5, iclass 37, count 2 2006.285.23:03:57.18#ibcon#about to read 6, iclass 37, count 2 2006.285.23:03:57.18#ibcon#read 6, iclass 37, count 2 2006.285.23:03:57.18#ibcon#end of sib2, iclass 37, count 2 2006.285.23:03:57.18#ibcon#*after write, iclass 37, count 2 2006.285.23:03:57.18#ibcon#*before return 0, iclass 37, count 2 2006.285.23:03:57.18#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:03:57.18#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:03:57.18#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.23:03:57.18#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:57.18#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:03:57.29#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:03:57.29#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:03:57.29#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:03:57.30#ibcon#first serial, iclass 37, count 0 2006.285.23:03:57.30#ibcon#enter sib2, iclass 37, count 0 2006.285.23:03:57.30#ibcon#flushed, iclass 37, count 0 2006.285.23:03:57.30#ibcon#about to write, iclass 37, count 0 2006.285.23:03:57.30#ibcon#wrote, iclass 37, count 0 2006.285.23:03:57.30#ibcon#about to read 3, iclass 37, count 0 2006.285.23:03:57.31#ibcon#read 3, iclass 37, count 0 2006.285.23:03:57.31#ibcon#about to read 4, iclass 37, count 0 2006.285.23:03:57.31#ibcon#read 4, iclass 37, count 0 2006.285.23:03:57.32#ibcon#about to read 5, iclass 37, count 0 2006.285.23:03:57.32#ibcon#read 5, iclass 37, count 0 2006.285.23:03:57.32#ibcon#about to read 6, iclass 37, count 0 2006.285.23:03:57.32#ibcon#read 6, iclass 37, count 0 2006.285.23:03:57.32#ibcon#end of sib2, iclass 37, count 0 2006.285.23:03:57.32#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:03:57.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:03:57.32#ibcon#[27=USB\r\n] 2006.285.23:03:57.32#ibcon#*before write, iclass 37, count 0 2006.285.23:03:57.32#ibcon#enter sib2, iclass 37, count 0 2006.285.23:03:57.32#ibcon#flushed, iclass 37, count 0 2006.285.23:03:57.32#ibcon#about to write, iclass 37, count 0 2006.285.23:03:57.32#ibcon#wrote, iclass 37, count 0 2006.285.23:03:57.32#ibcon#about to read 3, iclass 37, count 0 2006.285.23:03:57.34#ibcon#read 3, iclass 37, count 0 2006.285.23:03:57.34#ibcon#about to read 4, iclass 37, count 0 2006.285.23:03:57.34#ibcon#read 4, iclass 37, count 0 2006.285.23:03:57.35#ibcon#about to read 5, iclass 37, count 0 2006.285.23:03:57.35#ibcon#read 5, iclass 37, count 0 2006.285.23:03:57.35#ibcon#about to read 6, iclass 37, count 0 2006.285.23:03:57.35#ibcon#read 6, iclass 37, count 0 2006.285.23:03:57.35#ibcon#end of sib2, iclass 37, count 0 2006.285.23:03:57.35#ibcon#*after write, iclass 37, count 0 2006.285.23:03:57.35#ibcon#*before return 0, iclass 37, count 0 2006.285.23:03:57.35#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:03:57.35#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:03:57.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:03:57.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:03:57.35$vck44/vblo=4,679.99 2006.285.23:03:57.35#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.23:03:57.35#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.23:03:57.35#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:57.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:03:57.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:03:57.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:03:57.35#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:03:57.35#ibcon#first serial, iclass 39, count 0 2006.285.23:03:57.35#ibcon#enter sib2, iclass 39, count 0 2006.285.23:03:57.35#ibcon#flushed, iclass 39, count 0 2006.285.23:03:57.35#ibcon#about to write, iclass 39, count 0 2006.285.23:03:57.35#ibcon#wrote, iclass 39, count 0 2006.285.23:03:57.35#ibcon#about to read 3, iclass 39, count 0 2006.285.23:03:57.36#ibcon#read 3, iclass 39, count 0 2006.285.23:03:57.36#ibcon#about to read 4, iclass 39, count 0 2006.285.23:03:57.37#ibcon#read 4, iclass 39, count 0 2006.285.23:03:57.37#ibcon#about to read 5, iclass 39, count 0 2006.285.23:03:57.37#ibcon#read 5, iclass 39, count 0 2006.285.23:03:57.37#ibcon#about to read 6, iclass 39, count 0 2006.285.23:03:57.37#ibcon#read 6, iclass 39, count 0 2006.285.23:03:57.37#ibcon#end of sib2, iclass 39, count 0 2006.285.23:03:57.37#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:03:57.37#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:03:57.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:03:57.37#ibcon#*before write, iclass 39, count 0 2006.285.23:03:57.37#ibcon#enter sib2, iclass 39, count 0 2006.285.23:03:57.37#ibcon#flushed, iclass 39, count 0 2006.285.23:03:57.37#ibcon#about to write, iclass 39, count 0 2006.285.23:03:57.37#ibcon#wrote, iclass 39, count 0 2006.285.23:03:57.37#ibcon#about to read 3, iclass 39, count 0 2006.285.23:03:57.40#ibcon#read 3, iclass 39, count 0 2006.285.23:03:57.40#ibcon#about to read 4, iclass 39, count 0 2006.285.23:03:57.40#ibcon#read 4, iclass 39, count 0 2006.285.23:03:57.41#ibcon#about to read 5, iclass 39, count 0 2006.285.23:03:57.41#ibcon#read 5, iclass 39, count 0 2006.285.23:03:57.41#ibcon#about to read 6, iclass 39, count 0 2006.285.23:03:57.41#ibcon#read 6, iclass 39, count 0 2006.285.23:03:57.41#ibcon#end of sib2, iclass 39, count 0 2006.285.23:03:57.41#ibcon#*after write, iclass 39, count 0 2006.285.23:03:57.41#ibcon#*before return 0, iclass 39, count 0 2006.285.23:03:57.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:03:57.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:03:57.41#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:03:57.41#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:03:57.41$vck44/vb=4,5 2006.285.23:03:57.41#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.23:03:57.41#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.23:03:57.41#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:57.41#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:03:57.46#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:03:57.46#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:03:57.46#ibcon#enter wrdev, iclass 3, count 2 2006.285.23:03:57.47#ibcon#first serial, iclass 3, count 2 2006.285.23:03:57.47#ibcon#enter sib2, iclass 3, count 2 2006.285.23:03:57.47#ibcon#flushed, iclass 3, count 2 2006.285.23:03:57.47#ibcon#about to write, iclass 3, count 2 2006.285.23:03:57.47#ibcon#wrote, iclass 3, count 2 2006.285.23:03:57.47#ibcon#about to read 3, iclass 3, count 2 2006.285.23:03:57.49#ibcon#read 3, iclass 3, count 2 2006.285.23:03:57.49#ibcon#about to read 4, iclass 3, count 2 2006.285.23:03:57.49#ibcon#read 4, iclass 3, count 2 2006.285.23:03:57.49#ibcon#about to read 5, iclass 3, count 2 2006.285.23:03:57.49#ibcon#read 5, iclass 3, count 2 2006.285.23:03:57.49#ibcon#about to read 6, iclass 3, count 2 2006.285.23:03:57.49#ibcon#read 6, iclass 3, count 2 2006.285.23:03:57.49#ibcon#end of sib2, iclass 3, count 2 2006.285.23:03:57.49#ibcon#*mode == 0, iclass 3, count 2 2006.285.23:03:57.49#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.23:03:57.49#ibcon#[27=AT04-05\r\n] 2006.285.23:03:57.49#ibcon#*before write, iclass 3, count 2 2006.285.23:03:57.49#ibcon#enter sib2, iclass 3, count 2 2006.285.23:03:57.49#ibcon#flushed, iclass 3, count 2 2006.285.23:03:57.49#ibcon#about to write, iclass 3, count 2 2006.285.23:03:57.49#ibcon#wrote, iclass 3, count 2 2006.285.23:03:57.49#ibcon#about to read 3, iclass 3, count 2 2006.285.23:03:57.51#ibcon#read 3, iclass 3, count 2 2006.285.23:03:57.52#ibcon#about to read 4, iclass 3, count 2 2006.285.23:03:57.52#ibcon#read 4, iclass 3, count 2 2006.285.23:03:57.52#ibcon#about to read 5, iclass 3, count 2 2006.285.23:03:57.52#ibcon#read 5, iclass 3, count 2 2006.285.23:03:57.52#ibcon#about to read 6, iclass 3, count 2 2006.285.23:03:57.52#ibcon#read 6, iclass 3, count 2 2006.285.23:03:57.52#ibcon#end of sib2, iclass 3, count 2 2006.285.23:03:57.52#ibcon#*after write, iclass 3, count 2 2006.285.23:03:57.52#ibcon#*before return 0, iclass 3, count 2 2006.285.23:03:57.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:03:57.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:03:57.52#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.23:03:57.52#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:57.52#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:03:57.63#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:03:57.63#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:03:57.64#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:03:57.64#ibcon#first serial, iclass 3, count 0 2006.285.23:03:57.64#ibcon#enter sib2, iclass 3, count 0 2006.285.23:03:57.64#ibcon#flushed, iclass 3, count 0 2006.285.23:03:57.64#ibcon#about to write, iclass 3, count 0 2006.285.23:03:57.64#ibcon#wrote, iclass 3, count 0 2006.285.23:03:57.64#ibcon#about to read 3, iclass 3, count 0 2006.285.23:03:57.65#ibcon#read 3, iclass 3, count 0 2006.285.23:03:57.65#ibcon#about to read 4, iclass 3, count 0 2006.285.23:03:57.65#ibcon#read 4, iclass 3, count 0 2006.285.23:03:57.66#ibcon#about to read 5, iclass 3, count 0 2006.285.23:03:57.66#ibcon#read 5, iclass 3, count 0 2006.285.23:03:57.66#ibcon#about to read 6, iclass 3, count 0 2006.285.23:03:57.66#ibcon#read 6, iclass 3, count 0 2006.285.23:03:57.66#ibcon#end of sib2, iclass 3, count 0 2006.285.23:03:57.66#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:03:57.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:03:57.66#ibcon#[27=USB\r\n] 2006.285.23:03:57.66#ibcon#*before write, iclass 3, count 0 2006.285.23:03:57.66#ibcon#enter sib2, iclass 3, count 0 2006.285.23:03:57.66#ibcon#flushed, iclass 3, count 0 2006.285.23:03:57.66#ibcon#about to write, iclass 3, count 0 2006.285.23:03:57.66#ibcon#wrote, iclass 3, count 0 2006.285.23:03:57.66#ibcon#about to read 3, iclass 3, count 0 2006.285.23:03:57.68#ibcon#read 3, iclass 3, count 0 2006.285.23:03:57.68#ibcon#about to read 4, iclass 3, count 0 2006.285.23:03:57.68#ibcon#read 4, iclass 3, count 0 2006.285.23:03:57.69#ibcon#about to read 5, iclass 3, count 0 2006.285.23:03:57.69#ibcon#read 5, iclass 3, count 0 2006.285.23:03:57.69#ibcon#about to read 6, iclass 3, count 0 2006.285.23:03:57.69#ibcon#read 6, iclass 3, count 0 2006.285.23:03:57.69#ibcon#end of sib2, iclass 3, count 0 2006.285.23:03:57.69#ibcon#*after write, iclass 3, count 0 2006.285.23:03:57.69#ibcon#*before return 0, iclass 3, count 0 2006.285.23:03:57.69#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:03:57.69#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:03:57.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:03:57.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:03:57.69$vck44/vblo=5,709.99 2006.285.23:03:57.69#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.23:03:57.69#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.23:03:57.69#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:57.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:03:57.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:03:57.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:03:57.69#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:03:57.69#ibcon#first serial, iclass 5, count 0 2006.285.23:03:57.69#ibcon#enter sib2, iclass 5, count 0 2006.285.23:03:57.69#ibcon#flushed, iclass 5, count 0 2006.285.23:03:57.69#ibcon#about to write, iclass 5, count 0 2006.285.23:03:57.69#ibcon#wrote, iclass 5, count 0 2006.285.23:03:57.69#ibcon#about to read 3, iclass 5, count 0 2006.285.23:03:57.70#ibcon#read 3, iclass 5, count 0 2006.285.23:03:57.70#ibcon#about to read 4, iclass 5, count 0 2006.285.23:03:57.71#ibcon#read 4, iclass 5, count 0 2006.285.23:03:57.71#ibcon#about to read 5, iclass 5, count 0 2006.285.23:03:57.71#ibcon#read 5, iclass 5, count 0 2006.285.23:03:57.71#ibcon#about to read 6, iclass 5, count 0 2006.285.23:03:57.71#ibcon#read 6, iclass 5, count 0 2006.285.23:03:57.71#ibcon#end of sib2, iclass 5, count 0 2006.285.23:03:57.71#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:03:57.71#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:03:57.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:03:57.71#ibcon#*before write, iclass 5, count 0 2006.285.23:03:57.71#ibcon#enter sib2, iclass 5, count 0 2006.285.23:03:57.71#ibcon#flushed, iclass 5, count 0 2006.285.23:03:57.71#ibcon#about to write, iclass 5, count 0 2006.285.23:03:57.71#ibcon#wrote, iclass 5, count 0 2006.285.23:03:57.71#ibcon#about to read 3, iclass 5, count 0 2006.285.23:03:57.74#ibcon#read 3, iclass 5, count 0 2006.285.23:03:57.74#ibcon#about to read 4, iclass 5, count 0 2006.285.23:03:57.74#ibcon#read 4, iclass 5, count 0 2006.285.23:03:57.75#ibcon#about to read 5, iclass 5, count 0 2006.285.23:03:57.75#ibcon#read 5, iclass 5, count 0 2006.285.23:03:57.75#ibcon#about to read 6, iclass 5, count 0 2006.285.23:03:57.75#ibcon#read 6, iclass 5, count 0 2006.285.23:03:57.75#ibcon#end of sib2, iclass 5, count 0 2006.285.23:03:57.75#ibcon#*after write, iclass 5, count 0 2006.285.23:03:57.75#ibcon#*before return 0, iclass 5, count 0 2006.285.23:03:57.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:03:57.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:03:57.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:03:57.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:03:57.75$vck44/vb=5,4 2006.285.23:03:57.75#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.23:03:57.75#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.23:03:57.75#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:57.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:03:57.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:03:57.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:03:57.80#ibcon#enter wrdev, iclass 7, count 2 2006.285.23:03:57.80#ibcon#first serial, iclass 7, count 2 2006.285.23:03:57.81#ibcon#enter sib2, iclass 7, count 2 2006.285.23:03:57.81#ibcon#flushed, iclass 7, count 2 2006.285.23:03:57.81#ibcon#about to write, iclass 7, count 2 2006.285.23:03:57.81#ibcon#wrote, iclass 7, count 2 2006.285.23:03:57.81#ibcon#about to read 3, iclass 7, count 2 2006.285.23:03:57.82#ibcon#read 3, iclass 7, count 2 2006.285.23:03:57.82#ibcon#about to read 4, iclass 7, count 2 2006.285.23:03:57.82#ibcon#read 4, iclass 7, count 2 2006.285.23:03:57.83#ibcon#about to read 5, iclass 7, count 2 2006.285.23:03:57.83#ibcon#read 5, iclass 7, count 2 2006.285.23:03:57.83#ibcon#about to read 6, iclass 7, count 2 2006.285.23:03:57.83#ibcon#read 6, iclass 7, count 2 2006.285.23:03:57.83#ibcon#end of sib2, iclass 7, count 2 2006.285.23:03:57.83#ibcon#*mode == 0, iclass 7, count 2 2006.285.23:03:57.83#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.23:03:57.83#ibcon#[27=AT05-04\r\n] 2006.285.23:03:57.83#ibcon#*before write, iclass 7, count 2 2006.285.23:03:57.83#ibcon#enter sib2, iclass 7, count 2 2006.285.23:03:57.83#ibcon#flushed, iclass 7, count 2 2006.285.23:03:57.83#ibcon#about to write, iclass 7, count 2 2006.285.23:03:57.83#ibcon#wrote, iclass 7, count 2 2006.285.23:03:57.83#ibcon#about to read 3, iclass 7, count 2 2006.285.23:03:57.85#ibcon#read 3, iclass 7, count 2 2006.285.23:03:57.85#ibcon#about to read 4, iclass 7, count 2 2006.285.23:03:57.85#ibcon#read 4, iclass 7, count 2 2006.285.23:03:57.86#ibcon#about to read 5, iclass 7, count 2 2006.285.23:03:57.86#ibcon#read 5, iclass 7, count 2 2006.285.23:03:57.86#ibcon#about to read 6, iclass 7, count 2 2006.285.23:03:57.86#ibcon#read 6, iclass 7, count 2 2006.285.23:03:57.86#ibcon#end of sib2, iclass 7, count 2 2006.285.23:03:57.86#ibcon#*after write, iclass 7, count 2 2006.285.23:03:57.86#ibcon#*before return 0, iclass 7, count 2 2006.285.23:03:57.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:03:57.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:03:57.86#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.23:03:57.86#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:57.86#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:03:57.97#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:03:57.97#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:03:57.97#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:03:57.98#ibcon#first serial, iclass 7, count 0 2006.285.23:03:57.98#ibcon#enter sib2, iclass 7, count 0 2006.285.23:03:57.98#ibcon#flushed, iclass 7, count 0 2006.285.23:03:57.98#ibcon#about to write, iclass 7, count 0 2006.285.23:03:57.98#ibcon#wrote, iclass 7, count 0 2006.285.23:03:57.98#ibcon#about to read 3, iclass 7, count 0 2006.285.23:03:57.99#ibcon#read 3, iclass 7, count 0 2006.285.23:03:57.99#ibcon#about to read 4, iclass 7, count 0 2006.285.23:03:57.99#ibcon#read 4, iclass 7, count 0 2006.285.23:03:58.00#ibcon#about to read 5, iclass 7, count 0 2006.285.23:03:58.00#ibcon#read 5, iclass 7, count 0 2006.285.23:03:58.00#ibcon#about to read 6, iclass 7, count 0 2006.285.23:03:58.00#ibcon#read 6, iclass 7, count 0 2006.285.23:03:58.00#ibcon#end of sib2, iclass 7, count 0 2006.285.23:03:58.00#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:03:58.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:03:58.00#ibcon#[27=USB\r\n] 2006.285.23:03:58.00#ibcon#*before write, iclass 7, count 0 2006.285.23:03:58.00#ibcon#enter sib2, iclass 7, count 0 2006.285.23:03:58.00#ibcon#flushed, iclass 7, count 0 2006.285.23:03:58.00#ibcon#about to write, iclass 7, count 0 2006.285.23:03:58.00#ibcon#wrote, iclass 7, count 0 2006.285.23:03:58.00#ibcon#about to read 3, iclass 7, count 0 2006.285.23:03:58.02#ibcon#read 3, iclass 7, count 0 2006.285.23:03:58.02#ibcon#about to read 4, iclass 7, count 0 2006.285.23:03:58.03#ibcon#read 4, iclass 7, count 0 2006.285.23:03:58.03#ibcon#about to read 5, iclass 7, count 0 2006.285.23:03:58.03#ibcon#read 5, iclass 7, count 0 2006.285.23:03:58.03#ibcon#about to read 6, iclass 7, count 0 2006.285.23:03:58.03#ibcon#read 6, iclass 7, count 0 2006.285.23:03:58.03#ibcon#end of sib2, iclass 7, count 0 2006.285.23:03:58.03#ibcon#*after write, iclass 7, count 0 2006.285.23:03:58.03#ibcon#*before return 0, iclass 7, count 0 2006.285.23:03:58.03#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:03:58.03#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:03:58.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:03:58.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:03:58.03$vck44/vblo=6,719.99 2006.285.23:03:58.03#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.23:03:58.03#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.23:03:58.03#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:58.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:03:58.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:03:58.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:03:58.03#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:03:58.03#ibcon#first serial, iclass 11, count 0 2006.285.23:03:58.03#ibcon#enter sib2, iclass 11, count 0 2006.285.23:03:58.03#ibcon#flushed, iclass 11, count 0 2006.285.23:03:58.03#ibcon#about to write, iclass 11, count 0 2006.285.23:03:58.03#ibcon#wrote, iclass 11, count 0 2006.285.23:03:58.03#ibcon#about to read 3, iclass 11, count 0 2006.285.23:03:58.04#ibcon#read 3, iclass 11, count 0 2006.285.23:03:58.04#ibcon#about to read 4, iclass 11, count 0 2006.285.23:03:58.05#ibcon#read 4, iclass 11, count 0 2006.285.23:03:58.05#ibcon#about to read 5, iclass 11, count 0 2006.285.23:03:58.05#ibcon#read 5, iclass 11, count 0 2006.285.23:03:58.05#ibcon#about to read 6, iclass 11, count 0 2006.285.23:03:58.05#ibcon#read 6, iclass 11, count 0 2006.285.23:03:58.05#ibcon#end of sib2, iclass 11, count 0 2006.285.23:03:58.05#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:03:58.05#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:03:58.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:03:58.05#ibcon#*before write, iclass 11, count 0 2006.285.23:03:58.05#ibcon#enter sib2, iclass 11, count 0 2006.285.23:03:58.05#ibcon#flushed, iclass 11, count 0 2006.285.23:03:58.05#ibcon#about to write, iclass 11, count 0 2006.285.23:03:58.05#ibcon#wrote, iclass 11, count 0 2006.285.23:03:58.05#ibcon#about to read 3, iclass 11, count 0 2006.285.23:03:58.08#ibcon#read 3, iclass 11, count 0 2006.285.23:03:58.08#ibcon#about to read 4, iclass 11, count 0 2006.285.23:03:58.09#ibcon#read 4, iclass 11, count 0 2006.285.23:03:58.09#ibcon#about to read 5, iclass 11, count 0 2006.285.23:03:58.09#ibcon#read 5, iclass 11, count 0 2006.285.23:03:58.09#ibcon#about to read 6, iclass 11, count 0 2006.285.23:03:58.09#ibcon#read 6, iclass 11, count 0 2006.285.23:03:58.09#ibcon#end of sib2, iclass 11, count 0 2006.285.23:03:58.09#ibcon#*after write, iclass 11, count 0 2006.285.23:03:58.09#ibcon#*before return 0, iclass 11, count 0 2006.285.23:03:58.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:03:58.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:03:58.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:03:58.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:03:58.09$vck44/vb=6,3 2006.285.23:03:58.09#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.23:03:58.09#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.23:03:58.09#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:58.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:03:58.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:03:58.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:03:58.14#ibcon#enter wrdev, iclass 13, count 2 2006.285.23:03:58.15#ibcon#first serial, iclass 13, count 2 2006.285.23:03:58.15#ibcon#enter sib2, iclass 13, count 2 2006.285.23:03:58.15#ibcon#flushed, iclass 13, count 2 2006.285.23:03:58.15#ibcon#about to write, iclass 13, count 2 2006.285.23:03:58.15#ibcon#wrote, iclass 13, count 2 2006.285.23:03:58.15#ibcon#about to read 3, iclass 13, count 2 2006.285.23:03:58.16#ibcon#read 3, iclass 13, count 2 2006.285.23:03:58.16#ibcon#about to read 4, iclass 13, count 2 2006.285.23:03:58.16#ibcon#read 4, iclass 13, count 2 2006.285.23:03:58.17#ibcon#about to read 5, iclass 13, count 2 2006.285.23:03:58.17#ibcon#read 5, iclass 13, count 2 2006.285.23:03:58.17#ibcon#about to read 6, iclass 13, count 2 2006.285.23:03:58.17#ibcon#read 6, iclass 13, count 2 2006.285.23:03:58.17#ibcon#end of sib2, iclass 13, count 2 2006.285.23:03:58.17#ibcon#*mode == 0, iclass 13, count 2 2006.285.23:03:58.17#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.23:03:58.17#ibcon#[27=AT06-03\r\n] 2006.285.23:03:58.17#ibcon#*before write, iclass 13, count 2 2006.285.23:03:58.17#ibcon#enter sib2, iclass 13, count 2 2006.285.23:03:58.17#ibcon#flushed, iclass 13, count 2 2006.285.23:03:58.17#ibcon#about to write, iclass 13, count 2 2006.285.23:03:58.17#ibcon#wrote, iclass 13, count 2 2006.285.23:03:58.17#ibcon#about to read 3, iclass 13, count 2 2006.285.23:03:58.19#ibcon#read 3, iclass 13, count 2 2006.285.23:03:58.19#ibcon#about to read 4, iclass 13, count 2 2006.285.23:03:58.20#ibcon#read 4, iclass 13, count 2 2006.285.23:03:58.20#ibcon#about to read 5, iclass 13, count 2 2006.285.23:03:58.20#ibcon#read 5, iclass 13, count 2 2006.285.23:03:58.20#ibcon#about to read 6, iclass 13, count 2 2006.285.23:03:58.20#ibcon#read 6, iclass 13, count 2 2006.285.23:03:58.20#ibcon#end of sib2, iclass 13, count 2 2006.285.23:03:58.20#ibcon#*after write, iclass 13, count 2 2006.285.23:03:58.20#ibcon#*before return 0, iclass 13, count 2 2006.285.23:03:58.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:03:58.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:03:58.20#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.23:03:58.20#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:58.20#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:03:58.31#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:03:58.31#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:03:58.31#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:03:58.32#ibcon#first serial, iclass 13, count 0 2006.285.23:03:58.32#ibcon#enter sib2, iclass 13, count 0 2006.285.23:03:58.32#ibcon#flushed, iclass 13, count 0 2006.285.23:03:58.32#ibcon#about to write, iclass 13, count 0 2006.285.23:03:58.32#ibcon#wrote, iclass 13, count 0 2006.285.23:03:58.32#ibcon#about to read 3, iclass 13, count 0 2006.285.23:03:58.33#ibcon#read 3, iclass 13, count 0 2006.285.23:03:58.33#ibcon#about to read 4, iclass 13, count 0 2006.285.23:03:58.33#ibcon#read 4, iclass 13, count 0 2006.285.23:03:58.34#ibcon#about to read 5, iclass 13, count 0 2006.285.23:03:58.34#ibcon#read 5, iclass 13, count 0 2006.285.23:03:58.34#ibcon#about to read 6, iclass 13, count 0 2006.285.23:03:58.34#ibcon#read 6, iclass 13, count 0 2006.285.23:03:58.34#ibcon#end of sib2, iclass 13, count 0 2006.285.23:03:58.34#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:03:58.34#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:03:58.34#ibcon#[27=USB\r\n] 2006.285.23:03:58.34#ibcon#*before write, iclass 13, count 0 2006.285.23:03:58.34#ibcon#enter sib2, iclass 13, count 0 2006.285.23:03:58.34#ibcon#flushed, iclass 13, count 0 2006.285.23:03:58.34#ibcon#about to write, iclass 13, count 0 2006.285.23:03:58.34#ibcon#wrote, iclass 13, count 0 2006.285.23:03:58.34#ibcon#about to read 3, iclass 13, count 0 2006.285.23:03:58.36#ibcon#read 3, iclass 13, count 0 2006.285.23:03:58.36#ibcon#about to read 4, iclass 13, count 0 2006.285.23:03:58.36#ibcon#read 4, iclass 13, count 0 2006.285.23:03:58.37#ibcon#about to read 5, iclass 13, count 0 2006.285.23:03:58.37#ibcon#read 5, iclass 13, count 0 2006.285.23:03:58.37#ibcon#about to read 6, iclass 13, count 0 2006.285.23:03:58.37#ibcon#read 6, iclass 13, count 0 2006.285.23:03:58.37#ibcon#end of sib2, iclass 13, count 0 2006.285.23:03:58.37#ibcon#*after write, iclass 13, count 0 2006.285.23:03:58.37#ibcon#*before return 0, iclass 13, count 0 2006.285.23:03:58.37#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:03:58.37#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:03:58.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:03:58.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:03:58.37$vck44/vblo=7,734.99 2006.285.23:03:58.37#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.23:03:58.37#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.23:03:58.37#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:58.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:03:58.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:03:58.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:03:58.37#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:03:58.37#ibcon#first serial, iclass 15, count 0 2006.285.23:03:58.37#ibcon#enter sib2, iclass 15, count 0 2006.285.23:03:58.37#ibcon#flushed, iclass 15, count 0 2006.285.23:03:58.37#ibcon#about to write, iclass 15, count 0 2006.285.23:03:58.37#ibcon#wrote, iclass 15, count 0 2006.285.23:03:58.37#ibcon#about to read 3, iclass 15, count 0 2006.285.23:03:58.38#ibcon#read 3, iclass 15, count 0 2006.285.23:03:58.38#ibcon#about to read 4, iclass 15, count 0 2006.285.23:03:58.38#ibcon#read 4, iclass 15, count 0 2006.285.23:03:58.39#ibcon#about to read 5, iclass 15, count 0 2006.285.23:03:58.39#ibcon#read 5, iclass 15, count 0 2006.285.23:03:58.39#ibcon#about to read 6, iclass 15, count 0 2006.285.23:03:58.39#ibcon#read 6, iclass 15, count 0 2006.285.23:03:58.39#ibcon#end of sib2, iclass 15, count 0 2006.285.23:03:58.39#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:03:58.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:03:58.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:03:58.39#ibcon#*before write, iclass 15, count 0 2006.285.23:03:58.39#ibcon#enter sib2, iclass 15, count 0 2006.285.23:03:58.39#ibcon#flushed, iclass 15, count 0 2006.285.23:03:58.39#ibcon#about to write, iclass 15, count 0 2006.285.23:03:58.39#ibcon#wrote, iclass 15, count 0 2006.285.23:03:58.39#ibcon#about to read 3, iclass 15, count 0 2006.285.23:03:58.42#ibcon#read 3, iclass 15, count 0 2006.285.23:03:58.42#ibcon#about to read 4, iclass 15, count 0 2006.285.23:03:58.42#ibcon#read 4, iclass 15, count 0 2006.285.23:03:58.43#ibcon#about to read 5, iclass 15, count 0 2006.285.23:03:58.43#ibcon#read 5, iclass 15, count 0 2006.285.23:03:58.43#ibcon#about to read 6, iclass 15, count 0 2006.285.23:03:58.43#ibcon#read 6, iclass 15, count 0 2006.285.23:03:58.43#ibcon#end of sib2, iclass 15, count 0 2006.285.23:03:58.43#ibcon#*after write, iclass 15, count 0 2006.285.23:03:58.43#ibcon#*before return 0, iclass 15, count 0 2006.285.23:03:58.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:03:58.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:03:58.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:03:58.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:03:58.43$vck44/vb=7,4 2006.285.23:03:58.43#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.23:03:58.43#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.23:03:58.43#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:58.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:03:58.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:03:58.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:03:58.48#ibcon#enter wrdev, iclass 17, count 2 2006.285.23:03:58.49#ibcon#first serial, iclass 17, count 2 2006.285.23:03:58.49#ibcon#enter sib2, iclass 17, count 2 2006.285.23:03:58.49#ibcon#flushed, iclass 17, count 2 2006.285.23:03:58.49#ibcon#about to write, iclass 17, count 2 2006.285.23:03:58.49#ibcon#wrote, iclass 17, count 2 2006.285.23:03:58.49#ibcon#about to read 3, iclass 17, count 2 2006.285.23:03:58.50#ibcon#read 3, iclass 17, count 2 2006.285.23:03:58.51#ibcon#about to read 4, iclass 17, count 2 2006.285.23:03:58.51#ibcon#read 4, iclass 17, count 2 2006.285.23:03:58.51#ibcon#about to read 5, iclass 17, count 2 2006.285.23:03:58.51#ibcon#read 5, iclass 17, count 2 2006.285.23:03:58.51#ibcon#about to read 6, iclass 17, count 2 2006.285.23:03:58.51#ibcon#read 6, iclass 17, count 2 2006.285.23:03:58.51#ibcon#end of sib2, iclass 17, count 2 2006.285.23:03:58.51#ibcon#*mode == 0, iclass 17, count 2 2006.285.23:03:58.51#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.23:03:58.51#ibcon#[27=AT07-04\r\n] 2006.285.23:03:58.51#ibcon#*before write, iclass 17, count 2 2006.285.23:03:58.51#ibcon#enter sib2, iclass 17, count 2 2006.285.23:03:58.51#ibcon#flushed, iclass 17, count 2 2006.285.23:03:58.51#ibcon#about to write, iclass 17, count 2 2006.285.23:03:58.51#ibcon#wrote, iclass 17, count 2 2006.285.23:03:58.51#ibcon#about to read 3, iclass 17, count 2 2006.285.23:03:58.53#ibcon#read 3, iclass 17, count 2 2006.285.23:03:58.54#ibcon#about to read 4, iclass 17, count 2 2006.285.23:03:58.54#ibcon#read 4, iclass 17, count 2 2006.285.23:03:58.54#ibcon#about to read 5, iclass 17, count 2 2006.285.23:03:58.54#ibcon#read 5, iclass 17, count 2 2006.285.23:03:58.54#ibcon#about to read 6, iclass 17, count 2 2006.285.23:03:58.54#ibcon#read 6, iclass 17, count 2 2006.285.23:03:58.54#ibcon#end of sib2, iclass 17, count 2 2006.285.23:03:58.54#ibcon#*after write, iclass 17, count 2 2006.285.23:03:58.54#ibcon#*before return 0, iclass 17, count 2 2006.285.23:03:58.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:03:58.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:03:58.54#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.23:03:58.54#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:58.54#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:03:58.65#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:03:58.65#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:03:58.66#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:03:58.66#ibcon#first serial, iclass 17, count 0 2006.285.23:03:58.66#ibcon#enter sib2, iclass 17, count 0 2006.285.23:03:58.66#ibcon#flushed, iclass 17, count 0 2006.285.23:03:58.66#ibcon#about to write, iclass 17, count 0 2006.285.23:03:58.66#ibcon#wrote, iclass 17, count 0 2006.285.23:03:58.66#ibcon#about to read 3, iclass 17, count 0 2006.285.23:03:58.67#ibcon#read 3, iclass 17, count 0 2006.285.23:03:58.67#ibcon#about to read 4, iclass 17, count 0 2006.285.23:03:58.67#ibcon#read 4, iclass 17, count 0 2006.285.23:03:58.68#ibcon#about to read 5, iclass 17, count 0 2006.285.23:03:58.68#ibcon#read 5, iclass 17, count 0 2006.285.23:03:58.68#ibcon#about to read 6, iclass 17, count 0 2006.285.23:03:58.68#ibcon#read 6, iclass 17, count 0 2006.285.23:03:58.68#ibcon#end of sib2, iclass 17, count 0 2006.285.23:03:58.68#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:03:58.68#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:03:58.68#ibcon#[27=USB\r\n] 2006.285.23:03:58.68#ibcon#*before write, iclass 17, count 0 2006.285.23:03:58.68#ibcon#enter sib2, iclass 17, count 0 2006.285.23:03:58.68#ibcon#flushed, iclass 17, count 0 2006.285.23:03:58.68#ibcon#about to write, iclass 17, count 0 2006.285.23:03:58.68#ibcon#wrote, iclass 17, count 0 2006.285.23:03:58.68#ibcon#about to read 3, iclass 17, count 0 2006.285.23:03:58.70#ibcon#read 3, iclass 17, count 0 2006.285.23:03:58.70#ibcon#about to read 4, iclass 17, count 0 2006.285.23:03:58.70#ibcon#read 4, iclass 17, count 0 2006.285.23:03:58.71#ibcon#about to read 5, iclass 17, count 0 2006.285.23:03:58.71#ibcon#read 5, iclass 17, count 0 2006.285.23:03:58.71#ibcon#about to read 6, iclass 17, count 0 2006.285.23:03:58.71#ibcon#read 6, iclass 17, count 0 2006.285.23:03:58.71#ibcon#end of sib2, iclass 17, count 0 2006.285.23:03:58.71#ibcon#*after write, iclass 17, count 0 2006.285.23:03:58.71#ibcon#*before return 0, iclass 17, count 0 2006.285.23:03:58.71#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:03:58.71#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:03:58.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:03:58.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:03:58.71$vck44/vblo=8,744.99 2006.285.23:03:58.71#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.23:03:58.71#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.23:03:58.71#ibcon#ireg 17 cls_cnt 0 2006.285.23:03:58.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:03:58.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:03:58.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:03:58.71#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:03:58.71#ibcon#first serial, iclass 19, count 0 2006.285.23:03:58.71#ibcon#enter sib2, iclass 19, count 0 2006.285.23:03:58.71#ibcon#flushed, iclass 19, count 0 2006.285.23:03:58.71#ibcon#about to write, iclass 19, count 0 2006.285.23:03:58.71#ibcon#wrote, iclass 19, count 0 2006.285.23:03:58.71#ibcon#about to read 3, iclass 19, count 0 2006.285.23:03:58.72#ibcon#read 3, iclass 19, count 0 2006.285.23:03:58.72#ibcon#about to read 4, iclass 19, count 0 2006.285.23:03:58.72#ibcon#read 4, iclass 19, count 0 2006.285.23:03:58.73#ibcon#about to read 5, iclass 19, count 0 2006.285.23:03:58.73#ibcon#read 5, iclass 19, count 0 2006.285.23:03:58.73#ibcon#about to read 6, iclass 19, count 0 2006.285.23:03:58.73#ibcon#read 6, iclass 19, count 0 2006.285.23:03:58.73#ibcon#end of sib2, iclass 19, count 0 2006.285.23:03:58.73#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:03:58.73#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:03:58.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:03:58.73#ibcon#*before write, iclass 19, count 0 2006.285.23:03:58.73#ibcon#enter sib2, iclass 19, count 0 2006.285.23:03:58.73#ibcon#flushed, iclass 19, count 0 2006.285.23:03:58.73#ibcon#about to write, iclass 19, count 0 2006.285.23:03:58.73#ibcon#wrote, iclass 19, count 0 2006.285.23:03:58.73#ibcon#about to read 3, iclass 19, count 0 2006.285.23:03:58.76#ibcon#read 3, iclass 19, count 0 2006.285.23:03:58.76#ibcon#about to read 4, iclass 19, count 0 2006.285.23:03:58.76#ibcon#read 4, iclass 19, count 0 2006.285.23:03:58.77#ibcon#about to read 5, iclass 19, count 0 2006.285.23:03:58.77#ibcon#read 5, iclass 19, count 0 2006.285.23:03:58.77#ibcon#about to read 6, iclass 19, count 0 2006.285.23:03:58.77#ibcon#read 6, iclass 19, count 0 2006.285.23:03:58.77#ibcon#end of sib2, iclass 19, count 0 2006.285.23:03:58.77#ibcon#*after write, iclass 19, count 0 2006.285.23:03:58.77#ibcon#*before return 0, iclass 19, count 0 2006.285.23:03:58.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:03:58.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:03:58.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:03:58.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:03:58.77$vck44/vb=8,4 2006.285.23:03:58.77#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.23:03:58.77#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.23:03:58.77#ibcon#ireg 11 cls_cnt 2 2006.285.23:03:58.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:03:58.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:03:58.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:03:58.82#ibcon#enter wrdev, iclass 21, count 2 2006.285.23:03:58.82#ibcon#first serial, iclass 21, count 2 2006.285.23:03:58.83#ibcon#enter sib2, iclass 21, count 2 2006.285.23:03:58.83#ibcon#flushed, iclass 21, count 2 2006.285.23:03:58.83#ibcon#about to write, iclass 21, count 2 2006.285.23:03:58.83#ibcon#wrote, iclass 21, count 2 2006.285.23:03:58.83#ibcon#about to read 3, iclass 21, count 2 2006.285.23:03:58.84#ibcon#read 3, iclass 21, count 2 2006.285.23:03:58.84#ibcon#about to read 4, iclass 21, count 2 2006.285.23:03:58.84#ibcon#read 4, iclass 21, count 2 2006.285.23:03:58.85#ibcon#about to read 5, iclass 21, count 2 2006.285.23:03:58.85#ibcon#read 5, iclass 21, count 2 2006.285.23:03:58.85#ibcon#about to read 6, iclass 21, count 2 2006.285.23:03:58.85#ibcon#read 6, iclass 21, count 2 2006.285.23:03:58.85#ibcon#end of sib2, iclass 21, count 2 2006.285.23:03:58.85#ibcon#*mode == 0, iclass 21, count 2 2006.285.23:03:58.85#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.23:03:58.85#ibcon#[27=AT08-04\r\n] 2006.285.23:03:58.85#ibcon#*before write, iclass 21, count 2 2006.285.23:03:58.85#ibcon#enter sib2, iclass 21, count 2 2006.285.23:03:58.85#ibcon#flushed, iclass 21, count 2 2006.285.23:03:58.85#ibcon#about to write, iclass 21, count 2 2006.285.23:03:58.85#ibcon#wrote, iclass 21, count 2 2006.285.23:03:58.85#ibcon#about to read 3, iclass 21, count 2 2006.285.23:03:58.87#ibcon#read 3, iclass 21, count 2 2006.285.23:03:58.87#ibcon#about to read 4, iclass 21, count 2 2006.285.23:03:58.87#ibcon#read 4, iclass 21, count 2 2006.285.23:03:58.88#ibcon#about to read 5, iclass 21, count 2 2006.285.23:03:58.88#ibcon#read 5, iclass 21, count 2 2006.285.23:03:58.88#ibcon#about to read 6, iclass 21, count 2 2006.285.23:03:58.88#ibcon#read 6, iclass 21, count 2 2006.285.23:03:58.88#ibcon#end of sib2, iclass 21, count 2 2006.285.23:03:58.88#ibcon#*after write, iclass 21, count 2 2006.285.23:03:58.88#ibcon#*before return 0, iclass 21, count 2 2006.285.23:03:58.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:03:58.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:03:58.88#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.23:03:58.88#ibcon#ireg 7 cls_cnt 0 2006.285.23:03:58.88#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:03:58.99#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:03:58.99#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:03:58.99#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:03:59.00#ibcon#first serial, iclass 21, count 0 2006.285.23:03:59.00#ibcon#enter sib2, iclass 21, count 0 2006.285.23:03:59.00#ibcon#flushed, iclass 21, count 0 2006.285.23:03:59.00#ibcon#about to write, iclass 21, count 0 2006.285.23:03:59.00#ibcon#wrote, iclass 21, count 0 2006.285.23:03:59.00#ibcon#about to read 3, iclass 21, count 0 2006.285.23:03:59.01#ibcon#read 3, iclass 21, count 0 2006.285.23:03:59.01#ibcon#about to read 4, iclass 21, count 0 2006.285.23:03:59.01#ibcon#read 4, iclass 21, count 0 2006.285.23:03:59.02#ibcon#about to read 5, iclass 21, count 0 2006.285.23:03:59.02#ibcon#read 5, iclass 21, count 0 2006.285.23:03:59.02#ibcon#about to read 6, iclass 21, count 0 2006.285.23:03:59.02#ibcon#read 6, iclass 21, count 0 2006.285.23:03:59.02#ibcon#end of sib2, iclass 21, count 0 2006.285.23:03:59.02#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:03:59.02#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:03:59.02#ibcon#[27=USB\r\n] 2006.285.23:03:59.02#ibcon#*before write, iclass 21, count 0 2006.285.23:03:59.02#ibcon#enter sib2, iclass 21, count 0 2006.285.23:03:59.02#ibcon#flushed, iclass 21, count 0 2006.285.23:03:59.02#ibcon#about to write, iclass 21, count 0 2006.285.23:03:59.02#ibcon#wrote, iclass 21, count 0 2006.285.23:03:59.02#ibcon#about to read 3, iclass 21, count 0 2006.285.23:03:59.04#ibcon#read 3, iclass 21, count 0 2006.285.23:03:59.04#ibcon#about to read 4, iclass 21, count 0 2006.285.23:03:59.04#ibcon#read 4, iclass 21, count 0 2006.285.23:03:59.05#ibcon#about to read 5, iclass 21, count 0 2006.285.23:03:59.05#ibcon#read 5, iclass 21, count 0 2006.285.23:03:59.05#ibcon#about to read 6, iclass 21, count 0 2006.285.23:03:59.05#ibcon#read 6, iclass 21, count 0 2006.285.23:03:59.05#ibcon#end of sib2, iclass 21, count 0 2006.285.23:03:59.05#ibcon#*after write, iclass 21, count 0 2006.285.23:03:59.05#ibcon#*before return 0, iclass 21, count 0 2006.285.23:03:59.05#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:03:59.05#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:03:59.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:03:59.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:03:59.05$vck44/vabw=wide 2006.285.23:03:59.05#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.23:03:59.05#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.23:03:59.05#ibcon#ireg 8 cls_cnt 0 2006.285.23:03:59.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:03:59.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:03:59.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:03:59.05#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:03:59.05#ibcon#first serial, iclass 23, count 0 2006.285.23:03:59.05#ibcon#enter sib2, iclass 23, count 0 2006.285.23:03:59.05#ibcon#flushed, iclass 23, count 0 2006.285.23:03:59.05#ibcon#about to write, iclass 23, count 0 2006.285.23:03:59.05#ibcon#wrote, iclass 23, count 0 2006.285.23:03:59.05#ibcon#about to read 3, iclass 23, count 0 2006.285.23:03:59.06#ibcon#read 3, iclass 23, count 0 2006.285.23:03:59.07#ibcon#about to read 4, iclass 23, count 0 2006.285.23:03:59.07#ibcon#read 4, iclass 23, count 0 2006.285.23:03:59.07#ibcon#about to read 5, iclass 23, count 0 2006.285.23:03:59.07#ibcon#read 5, iclass 23, count 0 2006.285.23:03:59.07#ibcon#about to read 6, iclass 23, count 0 2006.285.23:03:59.07#ibcon#read 6, iclass 23, count 0 2006.285.23:03:59.07#ibcon#end of sib2, iclass 23, count 0 2006.285.23:03:59.07#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:03:59.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:03:59.07#ibcon#[25=BW32\r\n] 2006.285.23:03:59.07#ibcon#*before write, iclass 23, count 0 2006.285.23:03:59.07#ibcon#enter sib2, iclass 23, count 0 2006.285.23:03:59.07#ibcon#flushed, iclass 23, count 0 2006.285.23:03:59.07#ibcon#about to write, iclass 23, count 0 2006.285.23:03:59.07#ibcon#wrote, iclass 23, count 0 2006.285.23:03:59.07#ibcon#about to read 3, iclass 23, count 0 2006.285.23:03:59.09#ibcon#read 3, iclass 23, count 0 2006.285.23:03:59.09#ibcon#about to read 4, iclass 23, count 0 2006.285.23:03:59.09#ibcon#read 4, iclass 23, count 0 2006.285.23:03:59.10#ibcon#about to read 5, iclass 23, count 0 2006.285.23:03:59.10#ibcon#read 5, iclass 23, count 0 2006.285.23:03:59.10#ibcon#about to read 6, iclass 23, count 0 2006.285.23:03:59.10#ibcon#read 6, iclass 23, count 0 2006.285.23:03:59.10#ibcon#end of sib2, iclass 23, count 0 2006.285.23:03:59.10#ibcon#*after write, iclass 23, count 0 2006.285.23:03:59.10#ibcon#*before return 0, iclass 23, count 0 2006.285.23:03:59.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:03:59.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:03:59.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:03:59.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:03:59.10$vck44/vbbw=wide 2006.285.23:03:59.10#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.23:03:59.10#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.23:03:59.10#ibcon#ireg 8 cls_cnt 0 2006.285.23:03:59.10#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:03:59.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:03:59.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:03:59.16#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:03:59.17#ibcon#first serial, iclass 25, count 0 2006.285.23:03:59.17#ibcon#enter sib2, iclass 25, count 0 2006.285.23:03:59.17#ibcon#flushed, iclass 25, count 0 2006.285.23:03:59.17#ibcon#about to write, iclass 25, count 0 2006.285.23:03:59.17#ibcon#wrote, iclass 25, count 0 2006.285.23:03:59.17#ibcon#about to read 3, iclass 25, count 0 2006.285.23:03:59.18#ibcon#read 3, iclass 25, count 0 2006.285.23:03:59.18#ibcon#about to read 4, iclass 25, count 0 2006.285.23:03:59.18#ibcon#read 4, iclass 25, count 0 2006.285.23:03:59.19#ibcon#about to read 5, iclass 25, count 0 2006.285.23:03:59.19#ibcon#read 5, iclass 25, count 0 2006.285.23:03:59.19#ibcon#about to read 6, iclass 25, count 0 2006.285.23:03:59.19#ibcon#read 6, iclass 25, count 0 2006.285.23:03:59.19#ibcon#end of sib2, iclass 25, count 0 2006.285.23:03:59.19#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:03:59.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:03:59.19#ibcon#[27=BW32\r\n] 2006.285.23:03:59.19#ibcon#*before write, iclass 25, count 0 2006.285.23:03:59.19#ibcon#enter sib2, iclass 25, count 0 2006.285.23:03:59.19#ibcon#flushed, iclass 25, count 0 2006.285.23:03:59.19#ibcon#about to write, iclass 25, count 0 2006.285.23:03:59.19#ibcon#wrote, iclass 25, count 0 2006.285.23:03:59.19#ibcon#about to read 3, iclass 25, count 0 2006.285.23:03:59.21#ibcon#read 3, iclass 25, count 0 2006.285.23:03:59.21#ibcon#about to read 4, iclass 25, count 0 2006.285.23:03:59.22#ibcon#read 4, iclass 25, count 0 2006.285.23:03:59.22#ibcon#about to read 5, iclass 25, count 0 2006.285.23:03:59.22#ibcon#read 5, iclass 25, count 0 2006.285.23:03:59.22#ibcon#about to read 6, iclass 25, count 0 2006.285.23:03:59.22#ibcon#read 6, iclass 25, count 0 2006.285.23:03:59.22#ibcon#end of sib2, iclass 25, count 0 2006.285.23:03:59.22#ibcon#*after write, iclass 25, count 0 2006.285.23:03:59.22#ibcon#*before return 0, iclass 25, count 0 2006.285.23:03:59.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:03:59.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:03:59.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:03:59.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:03:59.22$setupk4/ifdk4 2006.285.23:03:59.22$ifdk4/lo= 2006.285.23:03:59.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:03:59.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:03:59.22$ifdk4/patch= 2006.285.23:03:59.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:03:59.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:03:59.22$setupk4/!*+20s 2006.285.23:04:02.09#abcon#<5=/03 3.2 7.5 18.59 891016.4\r\n> 2006.285.23:04:02.11#abcon#{5=INTERFACE CLEAR} 2006.285.23:04:02.17#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:04:12.26#abcon#<5=/03 3.2 7.5 18.60 891016.4\r\n> 2006.285.23:04:12.28#abcon#{5=INTERFACE CLEAR} 2006.285.23:04:12.34#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:04:13.72$setupk4/"tpicd 2006.285.23:04:13.73$setupk4/echo=off 2006.285.23:04:13.73$setupk4/xlog=off 2006.285.23:04:13.73:!2006.285.23:07:29 2006.285.23:05:03.14#trakl#Source acquired 2006.285.23:05:04.15#flagr#flagr/antenna,acquired 2006.285.23:07:25.13#trakl#Off source 2006.285.23:07:25.13?ERROR st -7 Antenna off-source! 2006.285.23:07:25.13#trakl#az 50.646 el 14.081 azerr*cos(el) 0.0220 elerr 0.0106 2006.285.23:07:25.13#flagr#flagr/antenna,off-source 2006.285.23:07:29.01:preob 2006.285.23:07:30.13?ERROR an -103 Pointing computer tracking errors are too large. 2006.285.23:07:30.13?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.285.23:07:30.13/onsource/SLEWING 2006.285.23:07:30.13:!2006.285.23:07:39 2006.285.23:07:32.13#trakl#Source re-acquired 2006.285.23:07:32.13#flagr#flagr/antenna,re-acquired 2006.285.23:07:39.00:"tape 2006.285.23:07:39.00:"st=record 2006.285.23:07:39.00:data_valid=on 2006.285.23:07:39.00:midob 2006.285.23:07:39.13/onsource/TRACKING 2006.285.23:07:39.14/wx/18.75,1016.4,89 2006.285.23:07:39.19/cable/+6.5093E-03 2006.285.23:07:40.28/va/01,07,usb,yes,35,38 2006.285.23:07:40.28/va/02,06,usb,yes,35,36 2006.285.23:07:40.28/va/03,07,usb,yes,35,37 2006.285.23:07:40.28/va/04,06,usb,yes,37,38 2006.285.23:07:40.28/va/05,03,usb,yes,36,37 2006.285.23:07:40.28/va/06,04,usb,yes,33,32 2006.285.23:07:40.28/va/07,04,usb,yes,33,34 2006.285.23:07:40.28/va/08,03,usb,yes,34,41 2006.285.23:07:40.51/valo/01,524.99,yes,locked 2006.285.23:07:40.51/valo/02,534.99,yes,locked 2006.285.23:07:40.51/valo/03,564.99,yes,locked 2006.285.23:07:40.51/valo/04,624.99,yes,locked 2006.285.23:07:40.51/valo/05,734.99,yes,locked 2006.285.23:07:40.51/valo/06,814.99,yes,locked 2006.285.23:07:40.51/valo/07,864.99,yes,locked 2006.285.23:07:40.51/valo/08,884.99,yes,locked 2006.285.23:07:41.60/vb/01,04,usb,yes,32,30 2006.285.23:07:41.60/vb/02,05,usb,yes,31,30 2006.285.23:07:41.60/vb/03,04,usb,yes,32,35 2006.285.23:07:41.60/vb/04,05,usb,yes,32,31 2006.285.23:07:41.60/vb/05,04,usb,yes,28,31 2006.285.23:07:41.60/vb/06,03,usb,yes,41,36 2006.285.23:07:41.60/vb/07,04,usb,yes,33,33 2006.285.23:07:41.60/vb/08,04,usb,yes,30,34 2006.285.23:07:41.83/vblo/01,629.99,yes,locked 2006.285.23:07:41.83/vblo/02,634.99,yes,locked 2006.285.23:07:41.83/vblo/03,649.99,yes,locked 2006.285.23:07:41.83/vblo/04,679.99,yes,locked 2006.285.23:07:41.83/vblo/05,709.99,yes,locked 2006.285.23:07:41.83/vblo/06,719.99,yes,locked 2006.285.23:07:41.83/vblo/07,734.99,yes,locked 2006.285.23:07:41.83/vblo/08,744.99,yes,locked 2006.285.23:07:41.98/vabw/8 2006.285.23:07:42.13/vbbw/8 2006.285.23:07:42.22/xfe/off,on,12.0 2006.285.23:07:42.59/ifatt/23,28,28,28 2006.285.23:07:43.06/fmout-gps/S +2.62E-07 2006.285.23:07:43.08:!2006.285.23:08:19 2006.285.23:08:19.00:data_valid=off 2006.285.23:08:19.00:"et 2006.285.23:08:19.01:!+3s 2006.285.23:08:22.03:"tape 2006.285.23:08:22.03:postob 2006.285.23:08:22.26/cable/+6.5091E-03 2006.285.23:08:22.26/wx/18.78,1016.3,89 2006.285.23:08:22.32/fmout-gps/S +2.62E-07 2006.285.23:08:22.32:scan_name=285-2309,jd0610,70 2006.285.23:08:22.32:source=1611+343,161341.06,341247.9,2000.0,cw 2006.285.23:08:23.13#flagr#flagr/antenna,new-source 2006.285.23:08:23.14:checkk5 2006.285.23:08:23.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.23:08:23.96/chk_autoobs//k5ts2/ autoobs is running! 2006.285.23:08:24.35/chk_autoobs//k5ts3/ autoobs is running! 2006.285.23:08:24.94/chk_autoobs//k5ts4/ autoobs is running! 2006.285.23:08:25.37/chk_obsdata//k5ts1/T2852307??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.23:08:25.70/chk_obsdata//k5ts2/T2852307??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.23:08:26.03/chk_obsdata//k5ts3/T2852307??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.23:08:26.44/chk_obsdata//k5ts4/T2852307??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.285.23:08:27.43/k5log//k5ts1_log_newline 2006.285.23:08:28.39/k5log//k5ts2_log_newline 2006.285.23:08:29.35/k5log//k5ts3_log_newline 2006.285.23:08:30.36/k5log//k5ts4_log_newline 2006.285.23:08:30.38/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.23:08:30.38:setupk4=1 2006.285.23:08:30.38$setupk4/echo=on 2006.285.23:08:30.38$setupk4/pcalon 2006.285.23:08:30.38$pcalon/"no phase cal control is implemented here 2006.285.23:08:30.38$setupk4/"tpicd=stop 2006.285.23:08:30.38$setupk4/"rec=synch_on 2006.285.23:08:30.38$setupk4/"rec_mode=128 2006.285.23:08:30.38$setupk4/!* 2006.285.23:08:30.38$setupk4/recpk4 2006.285.23:08:30.38$recpk4/recpatch= 2006.285.23:08:30.38$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.23:08:30.38$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.23:08:30.38$setupk4/vck44 2006.285.23:08:30.38$vck44/valo=1,524.99 2006.285.23:08:30.38#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.23:08:30.38#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.23:08:30.38#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:30.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:08:30.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:08:30.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:08:30.38#ibcon#enter wrdev, iclass 31, count 0 2006.285.23:08:30.38#ibcon#first serial, iclass 31, count 0 2006.285.23:08:30.38#ibcon#enter sib2, iclass 31, count 0 2006.285.23:08:30.38#ibcon#flushed, iclass 31, count 0 2006.285.23:08:30.38#ibcon#about to write, iclass 31, count 0 2006.285.23:08:30.38#ibcon#wrote, iclass 31, count 0 2006.285.23:08:30.38#ibcon#about to read 3, iclass 31, count 0 2006.285.23:08:30.40#ibcon#read 3, iclass 31, count 0 2006.285.23:08:30.40#ibcon#about to read 4, iclass 31, count 0 2006.285.23:08:30.40#ibcon#read 4, iclass 31, count 0 2006.285.23:08:30.40#ibcon#about to read 5, iclass 31, count 0 2006.285.23:08:30.40#ibcon#read 5, iclass 31, count 0 2006.285.23:08:30.40#ibcon#about to read 6, iclass 31, count 0 2006.285.23:08:30.40#ibcon#read 6, iclass 31, count 0 2006.285.23:08:30.40#ibcon#end of sib2, iclass 31, count 0 2006.285.23:08:30.40#ibcon#*mode == 0, iclass 31, count 0 2006.285.23:08:30.40#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.23:08:30.40#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.23:08:30.40#ibcon#*before write, iclass 31, count 0 2006.285.23:08:30.40#ibcon#enter sib2, iclass 31, count 0 2006.285.23:08:30.40#ibcon#flushed, iclass 31, count 0 2006.285.23:08:30.40#ibcon#about to write, iclass 31, count 0 2006.285.23:08:30.40#ibcon#wrote, iclass 31, count 0 2006.285.23:08:30.40#ibcon#about to read 3, iclass 31, count 0 2006.285.23:08:30.45#ibcon#read 3, iclass 31, count 0 2006.285.23:08:30.45#ibcon#about to read 4, iclass 31, count 0 2006.285.23:08:30.45#ibcon#read 4, iclass 31, count 0 2006.285.23:08:30.45#ibcon#about to read 5, iclass 31, count 0 2006.285.23:08:30.45#ibcon#read 5, iclass 31, count 0 2006.285.23:08:30.45#ibcon#about to read 6, iclass 31, count 0 2006.285.23:08:30.45#ibcon#read 6, iclass 31, count 0 2006.285.23:08:30.45#ibcon#end of sib2, iclass 31, count 0 2006.285.23:08:30.45#ibcon#*after write, iclass 31, count 0 2006.285.23:08:30.45#ibcon#*before return 0, iclass 31, count 0 2006.285.23:08:30.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:08:30.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:08:30.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.23:08:30.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.23:08:30.45$vck44/va=1,7 2006.285.23:08:30.46#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.23:08:30.46#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.23:08:30.46#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:30.46#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:08:30.46#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:08:30.46#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:08:30.46#ibcon#enter wrdev, iclass 33, count 2 2006.285.23:08:30.46#ibcon#first serial, iclass 33, count 2 2006.285.23:08:30.46#ibcon#enter sib2, iclass 33, count 2 2006.285.23:08:30.46#ibcon#flushed, iclass 33, count 2 2006.285.23:08:30.46#ibcon#about to write, iclass 33, count 2 2006.285.23:08:30.46#ibcon#wrote, iclass 33, count 2 2006.285.23:08:30.46#ibcon#about to read 3, iclass 33, count 2 2006.285.23:08:30.47#ibcon#read 3, iclass 33, count 2 2006.285.23:08:30.47#ibcon#about to read 4, iclass 33, count 2 2006.285.23:08:30.47#ibcon#read 4, iclass 33, count 2 2006.285.23:08:30.47#ibcon#about to read 5, iclass 33, count 2 2006.285.23:08:30.47#ibcon#read 5, iclass 33, count 2 2006.285.23:08:30.47#ibcon#about to read 6, iclass 33, count 2 2006.285.23:08:30.47#ibcon#read 6, iclass 33, count 2 2006.285.23:08:30.47#ibcon#end of sib2, iclass 33, count 2 2006.285.23:08:30.47#ibcon#*mode == 0, iclass 33, count 2 2006.285.23:08:30.47#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.23:08:30.47#ibcon#[25=AT01-07\r\n] 2006.285.23:08:30.47#ibcon#*before write, iclass 33, count 2 2006.285.23:08:30.47#ibcon#enter sib2, iclass 33, count 2 2006.285.23:08:30.47#ibcon#flushed, iclass 33, count 2 2006.285.23:08:30.47#ibcon#about to write, iclass 33, count 2 2006.285.23:08:30.47#ibcon#wrote, iclass 33, count 2 2006.285.23:08:30.47#ibcon#about to read 3, iclass 33, count 2 2006.285.23:08:30.50#ibcon#read 3, iclass 33, count 2 2006.285.23:08:30.50#ibcon#about to read 4, iclass 33, count 2 2006.285.23:08:30.50#ibcon#read 4, iclass 33, count 2 2006.285.23:08:30.50#ibcon#about to read 5, iclass 33, count 2 2006.285.23:08:30.50#ibcon#read 5, iclass 33, count 2 2006.285.23:08:30.50#ibcon#about to read 6, iclass 33, count 2 2006.285.23:08:30.50#ibcon#read 6, iclass 33, count 2 2006.285.23:08:30.50#ibcon#end of sib2, iclass 33, count 2 2006.285.23:08:30.50#ibcon#*after write, iclass 33, count 2 2006.285.23:08:30.50#ibcon#*before return 0, iclass 33, count 2 2006.285.23:08:30.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:08:30.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:08:30.50#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.23:08:30.50#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:30.50#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:08:30.62#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:08:30.62#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:08:30.62#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:08:30.62#ibcon#first serial, iclass 33, count 0 2006.285.23:08:30.62#ibcon#enter sib2, iclass 33, count 0 2006.285.23:08:30.62#ibcon#flushed, iclass 33, count 0 2006.285.23:08:30.62#ibcon#about to write, iclass 33, count 0 2006.285.23:08:30.62#ibcon#wrote, iclass 33, count 0 2006.285.23:08:30.62#ibcon#about to read 3, iclass 33, count 0 2006.285.23:08:30.64#ibcon#read 3, iclass 33, count 0 2006.285.23:08:30.64#ibcon#about to read 4, iclass 33, count 0 2006.285.23:08:30.64#ibcon#read 4, iclass 33, count 0 2006.285.23:08:30.64#ibcon#about to read 5, iclass 33, count 0 2006.285.23:08:30.64#ibcon#read 5, iclass 33, count 0 2006.285.23:08:30.64#ibcon#about to read 6, iclass 33, count 0 2006.285.23:08:30.64#ibcon#read 6, iclass 33, count 0 2006.285.23:08:30.64#ibcon#end of sib2, iclass 33, count 0 2006.285.23:08:30.64#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:08:30.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:08:30.64#ibcon#[25=USB\r\n] 2006.285.23:08:30.64#ibcon#*before write, iclass 33, count 0 2006.285.23:08:30.64#ibcon#enter sib2, iclass 33, count 0 2006.285.23:08:30.64#ibcon#flushed, iclass 33, count 0 2006.285.23:08:30.64#ibcon#about to write, iclass 33, count 0 2006.285.23:08:30.64#ibcon#wrote, iclass 33, count 0 2006.285.23:08:30.64#ibcon#about to read 3, iclass 33, count 0 2006.285.23:08:30.67#ibcon#read 3, iclass 33, count 0 2006.285.23:08:30.67#ibcon#about to read 4, iclass 33, count 0 2006.285.23:08:30.67#ibcon#read 4, iclass 33, count 0 2006.285.23:08:30.67#ibcon#about to read 5, iclass 33, count 0 2006.285.23:08:30.67#ibcon#read 5, iclass 33, count 0 2006.285.23:08:30.67#ibcon#about to read 6, iclass 33, count 0 2006.285.23:08:30.67#ibcon#read 6, iclass 33, count 0 2006.285.23:08:30.67#ibcon#end of sib2, iclass 33, count 0 2006.285.23:08:30.67#ibcon#*after write, iclass 33, count 0 2006.285.23:08:30.67#ibcon#*before return 0, iclass 33, count 0 2006.285.23:08:30.67#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:08:30.67#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:08:30.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:08:30.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:08:30.67$vck44/valo=2,534.99 2006.285.23:08:30.68#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.23:08:30.68#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.23:08:30.68#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:30.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:08:30.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:08:30.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:08:30.68#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:08:30.68#ibcon#first serial, iclass 35, count 0 2006.285.23:08:30.68#ibcon#enter sib2, iclass 35, count 0 2006.285.23:08:30.68#ibcon#flushed, iclass 35, count 0 2006.285.23:08:30.68#ibcon#about to write, iclass 35, count 0 2006.285.23:08:30.68#ibcon#wrote, iclass 35, count 0 2006.285.23:08:30.68#ibcon#about to read 3, iclass 35, count 0 2006.285.23:08:30.69#ibcon#read 3, iclass 35, count 0 2006.285.23:08:30.69#ibcon#about to read 4, iclass 35, count 0 2006.285.23:08:30.69#ibcon#read 4, iclass 35, count 0 2006.285.23:08:30.69#ibcon#about to read 5, iclass 35, count 0 2006.285.23:08:30.69#ibcon#read 5, iclass 35, count 0 2006.285.23:08:30.69#ibcon#about to read 6, iclass 35, count 0 2006.285.23:08:30.69#ibcon#read 6, iclass 35, count 0 2006.285.23:08:30.69#ibcon#end of sib2, iclass 35, count 0 2006.285.23:08:30.69#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:08:30.69#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:08:30.69#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.23:08:30.69#ibcon#*before write, iclass 35, count 0 2006.285.23:08:30.69#ibcon#enter sib2, iclass 35, count 0 2006.285.23:08:30.69#ibcon#flushed, iclass 35, count 0 2006.285.23:08:30.69#ibcon#about to write, iclass 35, count 0 2006.285.23:08:30.69#ibcon#wrote, iclass 35, count 0 2006.285.23:08:30.69#ibcon#about to read 3, iclass 35, count 0 2006.285.23:08:30.73#ibcon#read 3, iclass 35, count 0 2006.285.23:08:30.73#ibcon#about to read 4, iclass 35, count 0 2006.285.23:08:30.73#ibcon#read 4, iclass 35, count 0 2006.285.23:08:30.73#ibcon#about to read 5, iclass 35, count 0 2006.285.23:08:30.73#ibcon#read 5, iclass 35, count 0 2006.285.23:08:30.73#ibcon#about to read 6, iclass 35, count 0 2006.285.23:08:30.73#ibcon#read 6, iclass 35, count 0 2006.285.23:08:30.73#ibcon#end of sib2, iclass 35, count 0 2006.285.23:08:30.73#ibcon#*after write, iclass 35, count 0 2006.285.23:08:30.73#ibcon#*before return 0, iclass 35, count 0 2006.285.23:08:30.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:08:30.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:08:30.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:08:30.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:08:30.73$vck44/va=2,6 2006.285.23:08:30.74#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.23:08:30.74#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.23:08:30.74#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:30.74#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:08:30.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:08:30.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:08:30.78#ibcon#enter wrdev, iclass 37, count 2 2006.285.23:08:30.78#ibcon#first serial, iclass 37, count 2 2006.285.23:08:30.78#ibcon#enter sib2, iclass 37, count 2 2006.285.23:08:30.78#ibcon#flushed, iclass 37, count 2 2006.285.23:08:30.78#ibcon#about to write, iclass 37, count 2 2006.285.23:08:30.78#ibcon#wrote, iclass 37, count 2 2006.285.23:08:30.78#ibcon#about to read 3, iclass 37, count 2 2006.285.23:08:30.80#ibcon#read 3, iclass 37, count 2 2006.285.23:08:30.80#ibcon#about to read 4, iclass 37, count 2 2006.285.23:08:30.80#ibcon#read 4, iclass 37, count 2 2006.285.23:08:30.80#ibcon#about to read 5, iclass 37, count 2 2006.285.23:08:30.80#ibcon#read 5, iclass 37, count 2 2006.285.23:08:30.80#ibcon#about to read 6, iclass 37, count 2 2006.285.23:08:30.80#ibcon#read 6, iclass 37, count 2 2006.285.23:08:30.80#ibcon#end of sib2, iclass 37, count 2 2006.285.23:08:30.80#ibcon#*mode == 0, iclass 37, count 2 2006.285.23:08:30.80#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.23:08:30.80#ibcon#[25=AT02-06\r\n] 2006.285.23:08:30.80#ibcon#*before write, iclass 37, count 2 2006.285.23:08:30.80#ibcon#enter sib2, iclass 37, count 2 2006.285.23:08:30.80#ibcon#flushed, iclass 37, count 2 2006.285.23:08:30.80#ibcon#about to write, iclass 37, count 2 2006.285.23:08:30.80#ibcon#wrote, iclass 37, count 2 2006.285.23:08:30.80#ibcon#about to read 3, iclass 37, count 2 2006.285.23:08:30.83#ibcon#read 3, iclass 37, count 2 2006.285.23:08:30.83#ibcon#about to read 4, iclass 37, count 2 2006.285.23:08:30.83#ibcon#read 4, iclass 37, count 2 2006.285.23:08:30.83#ibcon#about to read 5, iclass 37, count 2 2006.285.23:08:30.83#ibcon#read 5, iclass 37, count 2 2006.285.23:08:30.83#ibcon#about to read 6, iclass 37, count 2 2006.285.23:08:30.83#ibcon#read 6, iclass 37, count 2 2006.285.23:08:30.83#ibcon#end of sib2, iclass 37, count 2 2006.285.23:08:30.83#ibcon#*after write, iclass 37, count 2 2006.285.23:08:30.83#ibcon#*before return 0, iclass 37, count 2 2006.285.23:08:30.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:08:30.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:08:30.83#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.23:08:30.83#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:30.83#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:08:30.95#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:08:30.95#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:08:30.95#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:08:30.95#ibcon#first serial, iclass 37, count 0 2006.285.23:08:30.95#ibcon#enter sib2, iclass 37, count 0 2006.285.23:08:30.95#ibcon#flushed, iclass 37, count 0 2006.285.23:08:30.95#ibcon#about to write, iclass 37, count 0 2006.285.23:08:30.95#ibcon#wrote, iclass 37, count 0 2006.285.23:08:30.95#ibcon#about to read 3, iclass 37, count 0 2006.285.23:08:30.97#ibcon#read 3, iclass 37, count 0 2006.285.23:08:30.97#ibcon#about to read 4, iclass 37, count 0 2006.285.23:08:30.97#ibcon#read 4, iclass 37, count 0 2006.285.23:08:30.97#ibcon#about to read 5, iclass 37, count 0 2006.285.23:08:30.97#ibcon#read 5, iclass 37, count 0 2006.285.23:08:30.97#ibcon#about to read 6, iclass 37, count 0 2006.285.23:08:30.97#ibcon#read 6, iclass 37, count 0 2006.285.23:08:30.97#ibcon#end of sib2, iclass 37, count 0 2006.285.23:08:30.97#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:08:30.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:08:30.97#ibcon#[25=USB\r\n] 2006.285.23:08:30.97#ibcon#*before write, iclass 37, count 0 2006.285.23:08:30.97#ibcon#enter sib2, iclass 37, count 0 2006.285.23:08:30.97#ibcon#flushed, iclass 37, count 0 2006.285.23:08:30.97#ibcon#about to write, iclass 37, count 0 2006.285.23:08:30.97#ibcon#wrote, iclass 37, count 0 2006.285.23:08:30.97#ibcon#about to read 3, iclass 37, count 0 2006.285.23:08:31.00#ibcon#read 3, iclass 37, count 0 2006.285.23:08:31.00#ibcon#about to read 4, iclass 37, count 0 2006.285.23:08:31.00#ibcon#read 4, iclass 37, count 0 2006.285.23:08:31.00#ibcon#about to read 5, iclass 37, count 0 2006.285.23:08:31.00#ibcon#read 5, iclass 37, count 0 2006.285.23:08:31.00#ibcon#about to read 6, iclass 37, count 0 2006.285.23:08:31.00#ibcon#read 6, iclass 37, count 0 2006.285.23:08:31.00#ibcon#end of sib2, iclass 37, count 0 2006.285.23:08:31.00#ibcon#*after write, iclass 37, count 0 2006.285.23:08:31.00#ibcon#*before return 0, iclass 37, count 0 2006.285.23:08:31.00#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:08:31.00#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:08:31.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:08:31.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:08:31.00$vck44/valo=3,564.99 2006.285.23:08:31.01#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.23:08:31.01#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.23:08:31.01#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:31.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:08:31.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:08:31.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:08:31.01#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:08:31.01#ibcon#first serial, iclass 39, count 0 2006.285.23:08:31.01#ibcon#enter sib2, iclass 39, count 0 2006.285.23:08:31.01#ibcon#flushed, iclass 39, count 0 2006.285.23:08:31.01#ibcon#about to write, iclass 39, count 0 2006.285.23:08:31.01#ibcon#wrote, iclass 39, count 0 2006.285.23:08:31.01#ibcon#about to read 3, iclass 39, count 0 2006.285.23:08:31.02#ibcon#read 3, iclass 39, count 0 2006.285.23:08:31.02#ibcon#about to read 4, iclass 39, count 0 2006.285.23:08:31.02#ibcon#read 4, iclass 39, count 0 2006.285.23:08:31.02#ibcon#about to read 5, iclass 39, count 0 2006.285.23:08:31.02#ibcon#read 5, iclass 39, count 0 2006.285.23:08:31.02#ibcon#about to read 6, iclass 39, count 0 2006.285.23:08:31.02#ibcon#read 6, iclass 39, count 0 2006.285.23:08:31.02#ibcon#end of sib2, iclass 39, count 0 2006.285.23:08:31.02#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:08:31.02#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:08:31.02#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.23:08:31.02#ibcon#*before write, iclass 39, count 0 2006.285.23:08:31.02#ibcon#enter sib2, iclass 39, count 0 2006.285.23:08:31.02#ibcon#flushed, iclass 39, count 0 2006.285.23:08:31.02#ibcon#about to write, iclass 39, count 0 2006.285.23:08:31.02#ibcon#wrote, iclass 39, count 0 2006.285.23:08:31.02#ibcon#about to read 3, iclass 39, count 0 2006.285.23:08:31.06#ibcon#read 3, iclass 39, count 0 2006.285.23:08:31.06#ibcon#about to read 4, iclass 39, count 0 2006.285.23:08:31.06#ibcon#read 4, iclass 39, count 0 2006.285.23:08:31.06#ibcon#about to read 5, iclass 39, count 0 2006.285.23:08:31.06#ibcon#read 5, iclass 39, count 0 2006.285.23:08:31.06#ibcon#about to read 6, iclass 39, count 0 2006.285.23:08:31.06#ibcon#read 6, iclass 39, count 0 2006.285.23:08:31.06#ibcon#end of sib2, iclass 39, count 0 2006.285.23:08:31.06#ibcon#*after write, iclass 39, count 0 2006.285.23:08:31.06#ibcon#*before return 0, iclass 39, count 0 2006.285.23:08:31.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:08:31.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:08:31.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:08:31.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:08:31.06$vck44/va=3,7 2006.285.23:08:31.07#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.23:08:31.07#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.23:08:31.07#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:31.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:08:31.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:08:31.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:08:31.11#ibcon#enter wrdev, iclass 3, count 2 2006.285.23:08:31.11#ibcon#first serial, iclass 3, count 2 2006.285.23:08:31.11#ibcon#enter sib2, iclass 3, count 2 2006.285.23:08:31.11#ibcon#flushed, iclass 3, count 2 2006.285.23:08:31.11#ibcon#about to write, iclass 3, count 2 2006.285.23:08:31.11#ibcon#wrote, iclass 3, count 2 2006.285.23:08:31.11#ibcon#about to read 3, iclass 3, count 2 2006.285.23:08:31.13#ibcon#read 3, iclass 3, count 2 2006.285.23:08:31.13#ibcon#about to read 4, iclass 3, count 2 2006.285.23:08:31.13#ibcon#read 4, iclass 3, count 2 2006.285.23:08:31.13#ibcon#about to read 5, iclass 3, count 2 2006.285.23:08:31.13#ibcon#read 5, iclass 3, count 2 2006.285.23:08:31.13#ibcon#about to read 6, iclass 3, count 2 2006.285.23:08:31.13#ibcon#read 6, iclass 3, count 2 2006.285.23:08:31.13#ibcon#end of sib2, iclass 3, count 2 2006.285.23:08:31.13#ibcon#*mode == 0, iclass 3, count 2 2006.285.23:08:31.13#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.23:08:31.13#ibcon#[25=AT03-07\r\n] 2006.285.23:08:31.13#ibcon#*before write, iclass 3, count 2 2006.285.23:08:31.13#ibcon#enter sib2, iclass 3, count 2 2006.285.23:08:31.13#ibcon#flushed, iclass 3, count 2 2006.285.23:08:31.13#ibcon#about to write, iclass 3, count 2 2006.285.23:08:31.13#ibcon#wrote, iclass 3, count 2 2006.285.23:08:31.13#ibcon#about to read 3, iclass 3, count 2 2006.285.23:08:31.16#ibcon#read 3, iclass 3, count 2 2006.285.23:08:31.16#ibcon#about to read 4, iclass 3, count 2 2006.285.23:08:31.16#ibcon#read 4, iclass 3, count 2 2006.285.23:08:31.16#ibcon#about to read 5, iclass 3, count 2 2006.285.23:08:31.16#ibcon#read 5, iclass 3, count 2 2006.285.23:08:31.16#ibcon#about to read 6, iclass 3, count 2 2006.285.23:08:31.16#ibcon#read 6, iclass 3, count 2 2006.285.23:08:31.16#ibcon#end of sib2, iclass 3, count 2 2006.285.23:08:31.16#ibcon#*after write, iclass 3, count 2 2006.285.23:08:31.16#ibcon#*before return 0, iclass 3, count 2 2006.285.23:08:31.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:08:31.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:08:31.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.23:08:31.16#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:31.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:08:31.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:08:31.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:08:31.28#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:08:31.28#ibcon#first serial, iclass 3, count 0 2006.285.23:08:31.28#ibcon#enter sib2, iclass 3, count 0 2006.285.23:08:31.28#ibcon#flushed, iclass 3, count 0 2006.285.23:08:31.28#ibcon#about to write, iclass 3, count 0 2006.285.23:08:31.28#ibcon#wrote, iclass 3, count 0 2006.285.23:08:31.28#ibcon#about to read 3, iclass 3, count 0 2006.285.23:08:31.30#ibcon#read 3, iclass 3, count 0 2006.285.23:08:31.30#ibcon#about to read 4, iclass 3, count 0 2006.285.23:08:31.30#ibcon#read 4, iclass 3, count 0 2006.285.23:08:31.30#ibcon#about to read 5, iclass 3, count 0 2006.285.23:08:31.30#ibcon#read 5, iclass 3, count 0 2006.285.23:08:31.30#ibcon#about to read 6, iclass 3, count 0 2006.285.23:08:31.30#ibcon#read 6, iclass 3, count 0 2006.285.23:08:31.30#ibcon#end of sib2, iclass 3, count 0 2006.285.23:08:31.30#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:08:31.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:08:31.30#ibcon#[25=USB\r\n] 2006.285.23:08:31.30#ibcon#*before write, iclass 3, count 0 2006.285.23:08:31.30#ibcon#enter sib2, iclass 3, count 0 2006.285.23:08:31.30#ibcon#flushed, iclass 3, count 0 2006.285.23:08:31.30#ibcon#about to write, iclass 3, count 0 2006.285.23:08:31.30#ibcon#wrote, iclass 3, count 0 2006.285.23:08:31.30#ibcon#about to read 3, iclass 3, count 0 2006.285.23:08:31.33#ibcon#read 3, iclass 3, count 0 2006.285.23:08:31.33#ibcon#about to read 4, iclass 3, count 0 2006.285.23:08:31.33#ibcon#read 4, iclass 3, count 0 2006.285.23:08:31.33#ibcon#about to read 5, iclass 3, count 0 2006.285.23:08:31.33#ibcon#read 5, iclass 3, count 0 2006.285.23:08:31.33#ibcon#about to read 6, iclass 3, count 0 2006.285.23:08:31.33#ibcon#read 6, iclass 3, count 0 2006.285.23:08:31.33#ibcon#end of sib2, iclass 3, count 0 2006.285.23:08:31.33#ibcon#*after write, iclass 3, count 0 2006.285.23:08:31.33#ibcon#*before return 0, iclass 3, count 0 2006.285.23:08:31.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:08:31.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:08:31.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:08:31.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:08:31.33$vck44/valo=4,624.99 2006.285.23:08:31.34#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.23:08:31.34#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.23:08:31.34#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:31.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:08:31.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:08:31.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:08:31.34#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:08:31.34#ibcon#first serial, iclass 5, count 0 2006.285.23:08:31.34#ibcon#enter sib2, iclass 5, count 0 2006.285.23:08:31.34#ibcon#flushed, iclass 5, count 0 2006.285.23:08:31.34#ibcon#about to write, iclass 5, count 0 2006.285.23:08:31.34#ibcon#wrote, iclass 5, count 0 2006.285.23:08:31.34#ibcon#about to read 3, iclass 5, count 0 2006.285.23:08:31.35#ibcon#read 3, iclass 5, count 0 2006.285.23:08:31.35#ibcon#about to read 4, iclass 5, count 0 2006.285.23:08:31.35#ibcon#read 4, iclass 5, count 0 2006.285.23:08:31.35#ibcon#about to read 5, iclass 5, count 0 2006.285.23:08:31.35#ibcon#read 5, iclass 5, count 0 2006.285.23:08:31.35#ibcon#about to read 6, iclass 5, count 0 2006.285.23:08:31.35#ibcon#read 6, iclass 5, count 0 2006.285.23:08:31.35#ibcon#end of sib2, iclass 5, count 0 2006.285.23:08:31.35#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:08:31.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:08:31.35#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.23:08:31.35#ibcon#*before write, iclass 5, count 0 2006.285.23:08:31.35#ibcon#enter sib2, iclass 5, count 0 2006.285.23:08:31.35#ibcon#flushed, iclass 5, count 0 2006.285.23:08:31.35#ibcon#about to write, iclass 5, count 0 2006.285.23:08:31.35#ibcon#wrote, iclass 5, count 0 2006.285.23:08:31.35#ibcon#about to read 3, iclass 5, count 0 2006.285.23:08:31.39#ibcon#read 3, iclass 5, count 0 2006.285.23:08:31.39#ibcon#about to read 4, iclass 5, count 0 2006.285.23:08:31.39#ibcon#read 4, iclass 5, count 0 2006.285.23:08:31.39#ibcon#about to read 5, iclass 5, count 0 2006.285.23:08:31.39#ibcon#read 5, iclass 5, count 0 2006.285.23:08:31.39#ibcon#about to read 6, iclass 5, count 0 2006.285.23:08:31.39#ibcon#read 6, iclass 5, count 0 2006.285.23:08:31.39#ibcon#end of sib2, iclass 5, count 0 2006.285.23:08:31.39#ibcon#*after write, iclass 5, count 0 2006.285.23:08:31.39#ibcon#*before return 0, iclass 5, count 0 2006.285.23:08:31.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:08:31.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:08:31.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:08:31.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:08:31.39$vck44/va=4,6 2006.285.23:08:31.40#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.23:08:31.40#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.23:08:31.40#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:31.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:08:31.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:08:31.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:08:31.44#ibcon#enter wrdev, iclass 7, count 2 2006.285.23:08:31.44#ibcon#first serial, iclass 7, count 2 2006.285.23:08:31.44#ibcon#enter sib2, iclass 7, count 2 2006.285.23:08:31.44#ibcon#flushed, iclass 7, count 2 2006.285.23:08:31.44#ibcon#about to write, iclass 7, count 2 2006.285.23:08:31.44#ibcon#wrote, iclass 7, count 2 2006.285.23:08:31.44#ibcon#about to read 3, iclass 7, count 2 2006.285.23:08:31.46#ibcon#read 3, iclass 7, count 2 2006.285.23:08:31.46#ibcon#about to read 4, iclass 7, count 2 2006.285.23:08:31.46#ibcon#read 4, iclass 7, count 2 2006.285.23:08:31.46#ibcon#about to read 5, iclass 7, count 2 2006.285.23:08:31.46#ibcon#read 5, iclass 7, count 2 2006.285.23:08:31.46#ibcon#about to read 6, iclass 7, count 2 2006.285.23:08:31.46#ibcon#read 6, iclass 7, count 2 2006.285.23:08:31.46#ibcon#end of sib2, iclass 7, count 2 2006.285.23:08:31.46#ibcon#*mode == 0, iclass 7, count 2 2006.285.23:08:31.46#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.23:08:31.46#ibcon#[25=AT04-06\r\n] 2006.285.23:08:31.46#ibcon#*before write, iclass 7, count 2 2006.285.23:08:31.46#ibcon#enter sib2, iclass 7, count 2 2006.285.23:08:31.46#ibcon#flushed, iclass 7, count 2 2006.285.23:08:31.46#ibcon#about to write, iclass 7, count 2 2006.285.23:08:31.46#ibcon#wrote, iclass 7, count 2 2006.285.23:08:31.46#ibcon#about to read 3, iclass 7, count 2 2006.285.23:08:31.49#ibcon#read 3, iclass 7, count 2 2006.285.23:08:31.49#ibcon#about to read 4, iclass 7, count 2 2006.285.23:08:31.49#ibcon#read 4, iclass 7, count 2 2006.285.23:08:31.49#ibcon#about to read 5, iclass 7, count 2 2006.285.23:08:31.49#ibcon#read 5, iclass 7, count 2 2006.285.23:08:31.49#ibcon#about to read 6, iclass 7, count 2 2006.285.23:08:31.49#ibcon#read 6, iclass 7, count 2 2006.285.23:08:31.49#ibcon#end of sib2, iclass 7, count 2 2006.285.23:08:31.49#ibcon#*after write, iclass 7, count 2 2006.285.23:08:31.49#ibcon#*before return 0, iclass 7, count 2 2006.285.23:08:31.49#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:08:31.49#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:08:31.49#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.23:08:31.49#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:31.49#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:08:31.61#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:08:31.61#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:08:31.61#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:08:31.61#ibcon#first serial, iclass 7, count 0 2006.285.23:08:31.61#ibcon#enter sib2, iclass 7, count 0 2006.285.23:08:31.61#ibcon#flushed, iclass 7, count 0 2006.285.23:08:31.61#ibcon#about to write, iclass 7, count 0 2006.285.23:08:31.61#ibcon#wrote, iclass 7, count 0 2006.285.23:08:31.61#ibcon#about to read 3, iclass 7, count 0 2006.285.23:08:31.63#ibcon#read 3, iclass 7, count 0 2006.285.23:08:31.63#ibcon#about to read 4, iclass 7, count 0 2006.285.23:08:31.63#ibcon#read 4, iclass 7, count 0 2006.285.23:08:31.63#ibcon#about to read 5, iclass 7, count 0 2006.285.23:08:31.63#ibcon#read 5, iclass 7, count 0 2006.285.23:08:31.63#ibcon#about to read 6, iclass 7, count 0 2006.285.23:08:31.63#ibcon#read 6, iclass 7, count 0 2006.285.23:08:31.63#ibcon#end of sib2, iclass 7, count 0 2006.285.23:08:31.63#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:08:31.63#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:08:31.63#ibcon#[25=USB\r\n] 2006.285.23:08:31.63#ibcon#*before write, iclass 7, count 0 2006.285.23:08:31.63#ibcon#enter sib2, iclass 7, count 0 2006.285.23:08:31.63#ibcon#flushed, iclass 7, count 0 2006.285.23:08:31.63#ibcon#about to write, iclass 7, count 0 2006.285.23:08:31.63#ibcon#wrote, iclass 7, count 0 2006.285.23:08:31.63#ibcon#about to read 3, iclass 7, count 0 2006.285.23:08:31.66#ibcon#read 3, iclass 7, count 0 2006.285.23:08:31.66#ibcon#about to read 4, iclass 7, count 0 2006.285.23:08:31.66#ibcon#read 4, iclass 7, count 0 2006.285.23:08:31.66#ibcon#about to read 5, iclass 7, count 0 2006.285.23:08:31.66#ibcon#read 5, iclass 7, count 0 2006.285.23:08:31.66#ibcon#about to read 6, iclass 7, count 0 2006.285.23:08:31.66#ibcon#read 6, iclass 7, count 0 2006.285.23:08:31.66#ibcon#end of sib2, iclass 7, count 0 2006.285.23:08:31.66#ibcon#*after write, iclass 7, count 0 2006.285.23:08:31.66#ibcon#*before return 0, iclass 7, count 0 2006.285.23:08:31.66#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:08:31.66#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:08:31.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:08:31.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:08:31.66$vck44/valo=5,734.99 2006.285.23:08:31.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.23:08:31.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.23:08:31.67#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:31.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:08:31.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:08:31.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:08:31.67#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:08:31.67#ibcon#first serial, iclass 11, count 0 2006.285.23:08:31.67#ibcon#enter sib2, iclass 11, count 0 2006.285.23:08:31.67#ibcon#flushed, iclass 11, count 0 2006.285.23:08:31.67#ibcon#about to write, iclass 11, count 0 2006.285.23:08:31.67#ibcon#wrote, iclass 11, count 0 2006.285.23:08:31.67#ibcon#about to read 3, iclass 11, count 0 2006.285.23:08:31.68#ibcon#read 3, iclass 11, count 0 2006.285.23:08:31.68#ibcon#about to read 4, iclass 11, count 0 2006.285.23:08:31.68#ibcon#read 4, iclass 11, count 0 2006.285.23:08:31.68#ibcon#about to read 5, iclass 11, count 0 2006.285.23:08:31.68#ibcon#read 5, iclass 11, count 0 2006.285.23:08:31.68#ibcon#about to read 6, iclass 11, count 0 2006.285.23:08:31.68#ibcon#read 6, iclass 11, count 0 2006.285.23:08:31.68#ibcon#end of sib2, iclass 11, count 0 2006.285.23:08:31.68#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:08:31.68#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:08:31.68#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.23:08:31.68#ibcon#*before write, iclass 11, count 0 2006.285.23:08:31.68#ibcon#enter sib2, iclass 11, count 0 2006.285.23:08:31.68#ibcon#flushed, iclass 11, count 0 2006.285.23:08:31.68#ibcon#about to write, iclass 11, count 0 2006.285.23:08:31.68#ibcon#wrote, iclass 11, count 0 2006.285.23:08:31.68#ibcon#about to read 3, iclass 11, count 0 2006.285.23:08:31.72#ibcon#read 3, iclass 11, count 0 2006.285.23:08:31.72#ibcon#about to read 4, iclass 11, count 0 2006.285.23:08:31.72#ibcon#read 4, iclass 11, count 0 2006.285.23:08:31.72#ibcon#about to read 5, iclass 11, count 0 2006.285.23:08:31.72#ibcon#read 5, iclass 11, count 0 2006.285.23:08:31.72#ibcon#about to read 6, iclass 11, count 0 2006.285.23:08:31.72#ibcon#read 6, iclass 11, count 0 2006.285.23:08:31.72#ibcon#end of sib2, iclass 11, count 0 2006.285.23:08:31.72#ibcon#*after write, iclass 11, count 0 2006.285.23:08:31.72#ibcon#*before return 0, iclass 11, count 0 2006.285.23:08:31.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:08:31.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:08:31.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:08:31.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:08:31.72$vck44/va=5,3 2006.285.23:08:31.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.23:08:31.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.23:08:31.73#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:31.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:08:31.77#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:08:31.77#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:08:31.77#ibcon#enter wrdev, iclass 13, count 2 2006.285.23:08:31.77#ibcon#first serial, iclass 13, count 2 2006.285.23:08:31.77#ibcon#enter sib2, iclass 13, count 2 2006.285.23:08:31.77#ibcon#flushed, iclass 13, count 2 2006.285.23:08:31.77#ibcon#about to write, iclass 13, count 2 2006.285.23:08:31.77#ibcon#wrote, iclass 13, count 2 2006.285.23:08:31.77#ibcon#about to read 3, iclass 13, count 2 2006.285.23:08:31.79#ibcon#read 3, iclass 13, count 2 2006.285.23:08:31.79#ibcon#about to read 4, iclass 13, count 2 2006.285.23:08:31.79#ibcon#read 4, iclass 13, count 2 2006.285.23:08:31.79#ibcon#about to read 5, iclass 13, count 2 2006.285.23:08:31.79#ibcon#read 5, iclass 13, count 2 2006.285.23:08:31.79#ibcon#about to read 6, iclass 13, count 2 2006.285.23:08:31.79#ibcon#read 6, iclass 13, count 2 2006.285.23:08:31.79#ibcon#end of sib2, iclass 13, count 2 2006.285.23:08:31.79#ibcon#*mode == 0, iclass 13, count 2 2006.285.23:08:31.79#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.23:08:31.79#ibcon#[25=AT05-03\r\n] 2006.285.23:08:31.79#ibcon#*before write, iclass 13, count 2 2006.285.23:08:31.79#ibcon#enter sib2, iclass 13, count 2 2006.285.23:08:31.79#ibcon#flushed, iclass 13, count 2 2006.285.23:08:31.79#ibcon#about to write, iclass 13, count 2 2006.285.23:08:31.79#ibcon#wrote, iclass 13, count 2 2006.285.23:08:31.79#ibcon#about to read 3, iclass 13, count 2 2006.285.23:08:31.82#ibcon#read 3, iclass 13, count 2 2006.285.23:08:31.82#ibcon#about to read 4, iclass 13, count 2 2006.285.23:08:31.82#ibcon#read 4, iclass 13, count 2 2006.285.23:08:31.82#ibcon#about to read 5, iclass 13, count 2 2006.285.23:08:31.82#ibcon#read 5, iclass 13, count 2 2006.285.23:08:31.82#ibcon#about to read 6, iclass 13, count 2 2006.285.23:08:31.82#ibcon#read 6, iclass 13, count 2 2006.285.23:08:31.82#ibcon#end of sib2, iclass 13, count 2 2006.285.23:08:31.82#ibcon#*after write, iclass 13, count 2 2006.285.23:08:31.82#ibcon#*before return 0, iclass 13, count 2 2006.285.23:08:31.82#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:08:31.82#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:08:31.82#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.23:08:31.82#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:31.82#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:08:31.94#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:08:31.94#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:08:31.94#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:08:31.94#ibcon#first serial, iclass 13, count 0 2006.285.23:08:31.94#ibcon#enter sib2, iclass 13, count 0 2006.285.23:08:31.94#ibcon#flushed, iclass 13, count 0 2006.285.23:08:31.94#ibcon#about to write, iclass 13, count 0 2006.285.23:08:31.94#ibcon#wrote, iclass 13, count 0 2006.285.23:08:31.94#ibcon#about to read 3, iclass 13, count 0 2006.285.23:08:31.96#ibcon#read 3, iclass 13, count 0 2006.285.23:08:31.96#ibcon#about to read 4, iclass 13, count 0 2006.285.23:08:31.96#ibcon#read 4, iclass 13, count 0 2006.285.23:08:31.96#ibcon#about to read 5, iclass 13, count 0 2006.285.23:08:31.96#ibcon#read 5, iclass 13, count 0 2006.285.23:08:31.96#ibcon#about to read 6, iclass 13, count 0 2006.285.23:08:31.96#ibcon#read 6, iclass 13, count 0 2006.285.23:08:31.96#ibcon#end of sib2, iclass 13, count 0 2006.285.23:08:31.96#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:08:31.96#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:08:31.96#ibcon#[25=USB\r\n] 2006.285.23:08:31.96#ibcon#*before write, iclass 13, count 0 2006.285.23:08:31.96#ibcon#enter sib2, iclass 13, count 0 2006.285.23:08:31.96#ibcon#flushed, iclass 13, count 0 2006.285.23:08:31.96#ibcon#about to write, iclass 13, count 0 2006.285.23:08:31.96#ibcon#wrote, iclass 13, count 0 2006.285.23:08:31.96#ibcon#about to read 3, iclass 13, count 0 2006.285.23:08:31.99#ibcon#read 3, iclass 13, count 0 2006.285.23:08:31.99#ibcon#about to read 4, iclass 13, count 0 2006.285.23:08:31.99#ibcon#read 4, iclass 13, count 0 2006.285.23:08:31.99#ibcon#about to read 5, iclass 13, count 0 2006.285.23:08:31.99#ibcon#read 5, iclass 13, count 0 2006.285.23:08:31.99#ibcon#about to read 6, iclass 13, count 0 2006.285.23:08:31.99#ibcon#read 6, iclass 13, count 0 2006.285.23:08:31.99#ibcon#end of sib2, iclass 13, count 0 2006.285.23:08:31.99#ibcon#*after write, iclass 13, count 0 2006.285.23:08:31.99#ibcon#*before return 0, iclass 13, count 0 2006.285.23:08:31.99#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:08:31.99#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:08:31.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:08:31.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:08:31.99$vck44/valo=6,814.99 2006.285.23:08:32.00#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.23:08:32.00#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.23:08:32.00#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:32.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:08:32.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:08:32.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:08:32.00#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:08:32.00#ibcon#first serial, iclass 15, count 0 2006.285.23:08:32.00#ibcon#enter sib2, iclass 15, count 0 2006.285.23:08:32.00#ibcon#flushed, iclass 15, count 0 2006.285.23:08:32.00#ibcon#about to write, iclass 15, count 0 2006.285.23:08:32.00#ibcon#wrote, iclass 15, count 0 2006.285.23:08:32.00#ibcon#about to read 3, iclass 15, count 0 2006.285.23:08:32.01#ibcon#read 3, iclass 15, count 0 2006.285.23:08:32.01#ibcon#about to read 4, iclass 15, count 0 2006.285.23:08:32.01#ibcon#read 4, iclass 15, count 0 2006.285.23:08:32.01#ibcon#about to read 5, iclass 15, count 0 2006.285.23:08:32.01#ibcon#read 5, iclass 15, count 0 2006.285.23:08:32.01#ibcon#about to read 6, iclass 15, count 0 2006.285.23:08:32.01#ibcon#read 6, iclass 15, count 0 2006.285.23:08:32.01#ibcon#end of sib2, iclass 15, count 0 2006.285.23:08:32.01#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:08:32.01#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:08:32.01#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.23:08:32.01#ibcon#*before write, iclass 15, count 0 2006.285.23:08:32.01#ibcon#enter sib2, iclass 15, count 0 2006.285.23:08:32.01#ibcon#flushed, iclass 15, count 0 2006.285.23:08:32.01#ibcon#about to write, iclass 15, count 0 2006.285.23:08:32.01#ibcon#wrote, iclass 15, count 0 2006.285.23:08:32.01#ibcon#about to read 3, iclass 15, count 0 2006.285.23:08:32.05#ibcon#read 3, iclass 15, count 0 2006.285.23:08:32.05#ibcon#about to read 4, iclass 15, count 0 2006.285.23:08:32.05#ibcon#read 4, iclass 15, count 0 2006.285.23:08:32.05#ibcon#about to read 5, iclass 15, count 0 2006.285.23:08:32.05#ibcon#read 5, iclass 15, count 0 2006.285.23:08:32.05#ibcon#about to read 6, iclass 15, count 0 2006.285.23:08:32.05#ibcon#read 6, iclass 15, count 0 2006.285.23:08:32.05#ibcon#end of sib2, iclass 15, count 0 2006.285.23:08:32.05#ibcon#*after write, iclass 15, count 0 2006.285.23:08:32.05#ibcon#*before return 0, iclass 15, count 0 2006.285.23:08:32.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:08:32.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:08:32.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:08:32.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:08:32.05$vck44/va=6,4 2006.285.23:08:32.06#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.23:08:32.06#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.23:08:32.06#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:32.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:08:32.10#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:08:32.10#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:08:32.10#ibcon#enter wrdev, iclass 17, count 2 2006.285.23:08:32.10#ibcon#first serial, iclass 17, count 2 2006.285.23:08:32.10#ibcon#enter sib2, iclass 17, count 2 2006.285.23:08:32.10#ibcon#flushed, iclass 17, count 2 2006.285.23:08:32.10#ibcon#about to write, iclass 17, count 2 2006.285.23:08:32.10#ibcon#wrote, iclass 17, count 2 2006.285.23:08:32.10#ibcon#about to read 3, iclass 17, count 2 2006.285.23:08:32.12#ibcon#read 3, iclass 17, count 2 2006.285.23:08:32.12#ibcon#about to read 4, iclass 17, count 2 2006.285.23:08:32.12#ibcon#read 4, iclass 17, count 2 2006.285.23:08:32.12#ibcon#about to read 5, iclass 17, count 2 2006.285.23:08:32.12#ibcon#read 5, iclass 17, count 2 2006.285.23:08:32.12#ibcon#about to read 6, iclass 17, count 2 2006.285.23:08:32.12#ibcon#read 6, iclass 17, count 2 2006.285.23:08:32.12#ibcon#end of sib2, iclass 17, count 2 2006.285.23:08:32.12#ibcon#*mode == 0, iclass 17, count 2 2006.285.23:08:32.12#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.23:08:32.12#ibcon#[25=AT06-04\r\n] 2006.285.23:08:32.12#ibcon#*before write, iclass 17, count 2 2006.285.23:08:32.12#ibcon#enter sib2, iclass 17, count 2 2006.285.23:08:32.12#ibcon#flushed, iclass 17, count 2 2006.285.23:08:32.12#ibcon#about to write, iclass 17, count 2 2006.285.23:08:32.12#ibcon#wrote, iclass 17, count 2 2006.285.23:08:32.12#ibcon#about to read 3, iclass 17, count 2 2006.285.23:08:32.15#ibcon#read 3, iclass 17, count 2 2006.285.23:08:32.15#ibcon#about to read 4, iclass 17, count 2 2006.285.23:08:32.15#ibcon#read 4, iclass 17, count 2 2006.285.23:08:32.15#ibcon#about to read 5, iclass 17, count 2 2006.285.23:08:32.15#ibcon#read 5, iclass 17, count 2 2006.285.23:08:32.15#ibcon#about to read 6, iclass 17, count 2 2006.285.23:08:32.15#ibcon#read 6, iclass 17, count 2 2006.285.23:08:32.15#ibcon#end of sib2, iclass 17, count 2 2006.285.23:08:32.15#ibcon#*after write, iclass 17, count 2 2006.285.23:08:32.15#ibcon#*before return 0, iclass 17, count 2 2006.285.23:08:32.15#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:08:32.15#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:08:32.15#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.23:08:32.15#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:32.15#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:08:32.27#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:08:32.27#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:08:32.27#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:08:32.27#ibcon#first serial, iclass 17, count 0 2006.285.23:08:32.27#ibcon#enter sib2, iclass 17, count 0 2006.285.23:08:32.27#ibcon#flushed, iclass 17, count 0 2006.285.23:08:32.27#ibcon#about to write, iclass 17, count 0 2006.285.23:08:32.27#ibcon#wrote, iclass 17, count 0 2006.285.23:08:32.27#ibcon#about to read 3, iclass 17, count 0 2006.285.23:08:32.29#ibcon#read 3, iclass 17, count 0 2006.285.23:08:32.29#ibcon#about to read 4, iclass 17, count 0 2006.285.23:08:32.29#ibcon#read 4, iclass 17, count 0 2006.285.23:08:32.29#ibcon#about to read 5, iclass 17, count 0 2006.285.23:08:32.29#ibcon#read 5, iclass 17, count 0 2006.285.23:08:32.29#ibcon#about to read 6, iclass 17, count 0 2006.285.23:08:32.29#ibcon#read 6, iclass 17, count 0 2006.285.23:08:32.29#ibcon#end of sib2, iclass 17, count 0 2006.285.23:08:32.29#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:08:32.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:08:32.29#ibcon#[25=USB\r\n] 2006.285.23:08:32.29#ibcon#*before write, iclass 17, count 0 2006.285.23:08:32.29#ibcon#enter sib2, iclass 17, count 0 2006.285.23:08:32.29#ibcon#flushed, iclass 17, count 0 2006.285.23:08:32.29#ibcon#about to write, iclass 17, count 0 2006.285.23:08:32.29#ibcon#wrote, iclass 17, count 0 2006.285.23:08:32.29#ibcon#about to read 3, iclass 17, count 0 2006.285.23:08:32.32#ibcon#read 3, iclass 17, count 0 2006.285.23:08:32.32#ibcon#about to read 4, iclass 17, count 0 2006.285.23:08:32.32#ibcon#read 4, iclass 17, count 0 2006.285.23:08:32.32#ibcon#about to read 5, iclass 17, count 0 2006.285.23:08:32.32#ibcon#read 5, iclass 17, count 0 2006.285.23:08:32.32#ibcon#about to read 6, iclass 17, count 0 2006.285.23:08:32.32#ibcon#read 6, iclass 17, count 0 2006.285.23:08:32.32#ibcon#end of sib2, iclass 17, count 0 2006.285.23:08:32.32#ibcon#*after write, iclass 17, count 0 2006.285.23:08:32.32#ibcon#*before return 0, iclass 17, count 0 2006.285.23:08:32.32#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:08:32.32#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:08:32.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:08:32.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:08:32.32$vck44/valo=7,864.99 2006.285.23:08:32.33#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.23:08:32.33#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.23:08:32.33#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:32.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:08:32.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:08:32.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:08:32.33#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:08:32.33#ibcon#first serial, iclass 19, count 0 2006.285.23:08:32.33#ibcon#enter sib2, iclass 19, count 0 2006.285.23:08:32.33#ibcon#flushed, iclass 19, count 0 2006.285.23:08:32.33#ibcon#about to write, iclass 19, count 0 2006.285.23:08:32.33#ibcon#wrote, iclass 19, count 0 2006.285.23:08:32.33#ibcon#about to read 3, iclass 19, count 0 2006.285.23:08:32.34#ibcon#read 3, iclass 19, count 0 2006.285.23:08:32.34#ibcon#about to read 4, iclass 19, count 0 2006.285.23:08:32.34#ibcon#read 4, iclass 19, count 0 2006.285.23:08:32.34#ibcon#about to read 5, iclass 19, count 0 2006.285.23:08:32.34#ibcon#read 5, iclass 19, count 0 2006.285.23:08:32.34#ibcon#about to read 6, iclass 19, count 0 2006.285.23:08:32.34#ibcon#read 6, iclass 19, count 0 2006.285.23:08:32.34#ibcon#end of sib2, iclass 19, count 0 2006.285.23:08:32.34#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:08:32.34#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:08:32.34#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.23:08:32.34#ibcon#*before write, iclass 19, count 0 2006.285.23:08:32.34#ibcon#enter sib2, iclass 19, count 0 2006.285.23:08:32.34#ibcon#flushed, iclass 19, count 0 2006.285.23:08:32.34#ibcon#about to write, iclass 19, count 0 2006.285.23:08:32.34#ibcon#wrote, iclass 19, count 0 2006.285.23:08:32.34#ibcon#about to read 3, iclass 19, count 0 2006.285.23:08:32.38#ibcon#read 3, iclass 19, count 0 2006.285.23:08:32.38#ibcon#about to read 4, iclass 19, count 0 2006.285.23:08:32.38#ibcon#read 4, iclass 19, count 0 2006.285.23:08:32.38#ibcon#about to read 5, iclass 19, count 0 2006.285.23:08:32.38#ibcon#read 5, iclass 19, count 0 2006.285.23:08:32.38#ibcon#about to read 6, iclass 19, count 0 2006.285.23:08:32.38#ibcon#read 6, iclass 19, count 0 2006.285.23:08:32.38#ibcon#end of sib2, iclass 19, count 0 2006.285.23:08:32.38#ibcon#*after write, iclass 19, count 0 2006.285.23:08:32.38#ibcon#*before return 0, iclass 19, count 0 2006.285.23:08:32.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:08:32.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:08:32.38#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:08:32.38#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:08:32.38$vck44/va=7,4 2006.285.23:08:32.39#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.23:08:32.39#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.23:08:32.39#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:32.39#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:08:32.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:08:32.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:08:32.43#ibcon#enter wrdev, iclass 21, count 2 2006.285.23:08:32.43#ibcon#first serial, iclass 21, count 2 2006.285.23:08:32.43#ibcon#enter sib2, iclass 21, count 2 2006.285.23:08:32.43#ibcon#flushed, iclass 21, count 2 2006.285.23:08:32.43#ibcon#about to write, iclass 21, count 2 2006.285.23:08:32.43#ibcon#wrote, iclass 21, count 2 2006.285.23:08:32.43#ibcon#about to read 3, iclass 21, count 2 2006.285.23:08:32.45#ibcon#read 3, iclass 21, count 2 2006.285.23:08:32.45#ibcon#about to read 4, iclass 21, count 2 2006.285.23:08:32.45#ibcon#read 4, iclass 21, count 2 2006.285.23:08:32.45#ibcon#about to read 5, iclass 21, count 2 2006.285.23:08:32.45#ibcon#read 5, iclass 21, count 2 2006.285.23:08:32.45#ibcon#about to read 6, iclass 21, count 2 2006.285.23:08:32.45#ibcon#read 6, iclass 21, count 2 2006.285.23:08:32.45#ibcon#end of sib2, iclass 21, count 2 2006.285.23:08:32.45#ibcon#*mode == 0, iclass 21, count 2 2006.285.23:08:32.45#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.23:08:32.45#ibcon#[25=AT07-04\r\n] 2006.285.23:08:32.45#ibcon#*before write, iclass 21, count 2 2006.285.23:08:32.45#ibcon#enter sib2, iclass 21, count 2 2006.285.23:08:32.45#ibcon#flushed, iclass 21, count 2 2006.285.23:08:32.45#ibcon#about to write, iclass 21, count 2 2006.285.23:08:32.45#ibcon#wrote, iclass 21, count 2 2006.285.23:08:32.45#ibcon#about to read 3, iclass 21, count 2 2006.285.23:08:32.48#ibcon#read 3, iclass 21, count 2 2006.285.23:08:32.48#ibcon#about to read 4, iclass 21, count 2 2006.285.23:08:32.48#ibcon#read 4, iclass 21, count 2 2006.285.23:08:32.48#ibcon#about to read 5, iclass 21, count 2 2006.285.23:08:32.48#ibcon#read 5, iclass 21, count 2 2006.285.23:08:32.48#ibcon#about to read 6, iclass 21, count 2 2006.285.23:08:32.48#ibcon#read 6, iclass 21, count 2 2006.285.23:08:32.48#ibcon#end of sib2, iclass 21, count 2 2006.285.23:08:32.48#ibcon#*after write, iclass 21, count 2 2006.285.23:08:32.48#ibcon#*before return 0, iclass 21, count 2 2006.285.23:08:32.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:08:32.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:08:32.48#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.23:08:32.48#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:32.48#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:08:32.60#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:08:32.60#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:08:32.60#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:08:32.60#ibcon#first serial, iclass 21, count 0 2006.285.23:08:32.60#ibcon#enter sib2, iclass 21, count 0 2006.285.23:08:32.60#ibcon#flushed, iclass 21, count 0 2006.285.23:08:32.60#ibcon#about to write, iclass 21, count 0 2006.285.23:08:32.60#ibcon#wrote, iclass 21, count 0 2006.285.23:08:32.60#ibcon#about to read 3, iclass 21, count 0 2006.285.23:08:32.62#ibcon#read 3, iclass 21, count 0 2006.285.23:08:32.62#ibcon#about to read 4, iclass 21, count 0 2006.285.23:08:32.62#ibcon#read 4, iclass 21, count 0 2006.285.23:08:32.62#ibcon#about to read 5, iclass 21, count 0 2006.285.23:08:32.62#ibcon#read 5, iclass 21, count 0 2006.285.23:08:32.62#ibcon#about to read 6, iclass 21, count 0 2006.285.23:08:32.62#ibcon#read 6, iclass 21, count 0 2006.285.23:08:32.62#ibcon#end of sib2, iclass 21, count 0 2006.285.23:08:32.62#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:08:32.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:08:32.62#ibcon#[25=USB\r\n] 2006.285.23:08:32.62#ibcon#*before write, iclass 21, count 0 2006.285.23:08:32.62#ibcon#enter sib2, iclass 21, count 0 2006.285.23:08:32.62#ibcon#flushed, iclass 21, count 0 2006.285.23:08:32.62#ibcon#about to write, iclass 21, count 0 2006.285.23:08:32.62#ibcon#wrote, iclass 21, count 0 2006.285.23:08:32.62#ibcon#about to read 3, iclass 21, count 0 2006.285.23:08:32.65#ibcon#read 3, iclass 21, count 0 2006.285.23:08:32.65#ibcon#about to read 4, iclass 21, count 0 2006.285.23:08:32.65#ibcon#read 4, iclass 21, count 0 2006.285.23:08:32.65#ibcon#about to read 5, iclass 21, count 0 2006.285.23:08:32.65#ibcon#read 5, iclass 21, count 0 2006.285.23:08:32.65#ibcon#about to read 6, iclass 21, count 0 2006.285.23:08:32.65#ibcon#read 6, iclass 21, count 0 2006.285.23:08:32.65#ibcon#end of sib2, iclass 21, count 0 2006.285.23:08:32.65#ibcon#*after write, iclass 21, count 0 2006.285.23:08:32.65#ibcon#*before return 0, iclass 21, count 0 2006.285.23:08:32.65#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:08:32.65#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:08:32.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:08:32.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:08:32.65$vck44/valo=8,884.99 2006.285.23:08:32.66#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.23:08:32.66#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.23:08:32.66#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:32.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:08:32.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:08:32.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:08:32.66#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:08:32.66#ibcon#first serial, iclass 23, count 0 2006.285.23:08:32.66#ibcon#enter sib2, iclass 23, count 0 2006.285.23:08:32.66#ibcon#flushed, iclass 23, count 0 2006.285.23:08:32.66#ibcon#about to write, iclass 23, count 0 2006.285.23:08:32.66#ibcon#wrote, iclass 23, count 0 2006.285.23:08:32.66#ibcon#about to read 3, iclass 23, count 0 2006.285.23:08:32.67#ibcon#read 3, iclass 23, count 0 2006.285.23:08:32.67#ibcon#about to read 4, iclass 23, count 0 2006.285.23:08:32.67#ibcon#read 4, iclass 23, count 0 2006.285.23:08:32.67#ibcon#about to read 5, iclass 23, count 0 2006.285.23:08:32.67#ibcon#read 5, iclass 23, count 0 2006.285.23:08:32.67#ibcon#about to read 6, iclass 23, count 0 2006.285.23:08:32.67#ibcon#read 6, iclass 23, count 0 2006.285.23:08:32.67#ibcon#end of sib2, iclass 23, count 0 2006.285.23:08:32.67#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:08:32.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:08:32.67#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.23:08:32.67#ibcon#*before write, iclass 23, count 0 2006.285.23:08:32.67#ibcon#enter sib2, iclass 23, count 0 2006.285.23:08:32.67#ibcon#flushed, iclass 23, count 0 2006.285.23:08:32.67#ibcon#about to write, iclass 23, count 0 2006.285.23:08:32.67#ibcon#wrote, iclass 23, count 0 2006.285.23:08:32.67#ibcon#about to read 3, iclass 23, count 0 2006.285.23:08:32.71#ibcon#read 3, iclass 23, count 0 2006.285.23:08:32.71#ibcon#about to read 4, iclass 23, count 0 2006.285.23:08:32.71#ibcon#read 4, iclass 23, count 0 2006.285.23:08:32.71#ibcon#about to read 5, iclass 23, count 0 2006.285.23:08:32.71#ibcon#read 5, iclass 23, count 0 2006.285.23:08:32.71#ibcon#about to read 6, iclass 23, count 0 2006.285.23:08:32.71#ibcon#read 6, iclass 23, count 0 2006.285.23:08:32.71#ibcon#end of sib2, iclass 23, count 0 2006.285.23:08:32.71#ibcon#*after write, iclass 23, count 0 2006.285.23:08:32.71#ibcon#*before return 0, iclass 23, count 0 2006.285.23:08:32.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:08:32.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:08:32.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:08:32.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:08:32.71$vck44/va=8,3 2006.285.23:08:32.72#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.23:08:32.72#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.23:08:32.72#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:32.72#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:08:32.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:08:32.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:08:32.76#ibcon#enter wrdev, iclass 25, count 2 2006.285.23:08:32.76#ibcon#first serial, iclass 25, count 2 2006.285.23:08:32.76#ibcon#enter sib2, iclass 25, count 2 2006.285.23:08:32.76#ibcon#flushed, iclass 25, count 2 2006.285.23:08:32.76#ibcon#about to write, iclass 25, count 2 2006.285.23:08:32.76#ibcon#wrote, iclass 25, count 2 2006.285.23:08:32.76#ibcon#about to read 3, iclass 25, count 2 2006.285.23:08:32.78#ibcon#read 3, iclass 25, count 2 2006.285.23:08:32.78#ibcon#about to read 4, iclass 25, count 2 2006.285.23:08:32.78#ibcon#read 4, iclass 25, count 2 2006.285.23:08:32.78#ibcon#about to read 5, iclass 25, count 2 2006.285.23:08:32.78#ibcon#read 5, iclass 25, count 2 2006.285.23:08:32.78#ibcon#about to read 6, iclass 25, count 2 2006.285.23:08:32.78#ibcon#read 6, iclass 25, count 2 2006.285.23:08:32.78#ibcon#end of sib2, iclass 25, count 2 2006.285.23:08:32.78#ibcon#*mode == 0, iclass 25, count 2 2006.285.23:08:32.78#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.23:08:32.78#ibcon#[25=AT08-03\r\n] 2006.285.23:08:32.78#ibcon#*before write, iclass 25, count 2 2006.285.23:08:32.78#ibcon#enter sib2, iclass 25, count 2 2006.285.23:08:32.78#ibcon#flushed, iclass 25, count 2 2006.285.23:08:32.78#ibcon#about to write, iclass 25, count 2 2006.285.23:08:32.78#ibcon#wrote, iclass 25, count 2 2006.285.23:08:32.78#ibcon#about to read 3, iclass 25, count 2 2006.285.23:08:32.81#ibcon#read 3, iclass 25, count 2 2006.285.23:08:32.81#ibcon#about to read 4, iclass 25, count 2 2006.285.23:08:32.81#ibcon#read 4, iclass 25, count 2 2006.285.23:08:32.81#ibcon#about to read 5, iclass 25, count 2 2006.285.23:08:32.81#ibcon#read 5, iclass 25, count 2 2006.285.23:08:32.81#ibcon#about to read 6, iclass 25, count 2 2006.285.23:08:32.81#ibcon#read 6, iclass 25, count 2 2006.285.23:08:32.81#ibcon#end of sib2, iclass 25, count 2 2006.285.23:08:32.81#ibcon#*after write, iclass 25, count 2 2006.285.23:08:32.81#ibcon#*before return 0, iclass 25, count 2 2006.285.23:08:32.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:08:32.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:08:32.81#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.23:08:32.81#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:32.81#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:08:32.93#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:08:32.93#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:08:32.93#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:08:32.93#ibcon#first serial, iclass 25, count 0 2006.285.23:08:32.93#ibcon#enter sib2, iclass 25, count 0 2006.285.23:08:32.93#ibcon#flushed, iclass 25, count 0 2006.285.23:08:32.93#ibcon#about to write, iclass 25, count 0 2006.285.23:08:32.93#ibcon#wrote, iclass 25, count 0 2006.285.23:08:32.93#ibcon#about to read 3, iclass 25, count 0 2006.285.23:08:32.95#ibcon#read 3, iclass 25, count 0 2006.285.23:08:32.95#ibcon#about to read 4, iclass 25, count 0 2006.285.23:08:32.95#ibcon#read 4, iclass 25, count 0 2006.285.23:08:32.95#ibcon#about to read 5, iclass 25, count 0 2006.285.23:08:32.95#ibcon#read 5, iclass 25, count 0 2006.285.23:08:32.95#ibcon#about to read 6, iclass 25, count 0 2006.285.23:08:32.95#ibcon#read 6, iclass 25, count 0 2006.285.23:08:32.95#ibcon#end of sib2, iclass 25, count 0 2006.285.23:08:32.95#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:08:32.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:08:32.95#ibcon#[25=USB\r\n] 2006.285.23:08:32.95#ibcon#*before write, iclass 25, count 0 2006.285.23:08:32.95#ibcon#enter sib2, iclass 25, count 0 2006.285.23:08:32.95#ibcon#flushed, iclass 25, count 0 2006.285.23:08:32.95#ibcon#about to write, iclass 25, count 0 2006.285.23:08:32.95#ibcon#wrote, iclass 25, count 0 2006.285.23:08:32.95#ibcon#about to read 3, iclass 25, count 0 2006.285.23:08:32.98#ibcon#read 3, iclass 25, count 0 2006.285.23:08:32.98#ibcon#about to read 4, iclass 25, count 0 2006.285.23:08:32.98#ibcon#read 4, iclass 25, count 0 2006.285.23:08:32.98#ibcon#about to read 5, iclass 25, count 0 2006.285.23:08:32.98#ibcon#read 5, iclass 25, count 0 2006.285.23:08:32.98#ibcon#about to read 6, iclass 25, count 0 2006.285.23:08:32.98#ibcon#read 6, iclass 25, count 0 2006.285.23:08:32.98#ibcon#end of sib2, iclass 25, count 0 2006.285.23:08:32.98#ibcon#*after write, iclass 25, count 0 2006.285.23:08:32.98#ibcon#*before return 0, iclass 25, count 0 2006.285.23:08:32.98#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:08:32.98#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:08:32.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:08:32.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:08:32.98$vck44/vblo=1,629.99 2006.285.23:08:32.99#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.23:08:32.99#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.23:08:32.99#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:32.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:08:32.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:08:32.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:08:32.99#ibcon#enter wrdev, iclass 27, count 0 2006.285.23:08:32.99#ibcon#first serial, iclass 27, count 0 2006.285.23:08:32.99#ibcon#enter sib2, iclass 27, count 0 2006.285.23:08:32.99#ibcon#flushed, iclass 27, count 0 2006.285.23:08:32.99#ibcon#about to write, iclass 27, count 0 2006.285.23:08:32.99#ibcon#wrote, iclass 27, count 0 2006.285.23:08:32.99#ibcon#about to read 3, iclass 27, count 0 2006.285.23:08:33.00#ibcon#read 3, iclass 27, count 0 2006.285.23:08:33.00#ibcon#about to read 4, iclass 27, count 0 2006.285.23:08:33.00#ibcon#read 4, iclass 27, count 0 2006.285.23:08:33.00#ibcon#about to read 5, iclass 27, count 0 2006.285.23:08:33.00#ibcon#read 5, iclass 27, count 0 2006.285.23:08:33.00#ibcon#about to read 6, iclass 27, count 0 2006.285.23:08:33.00#ibcon#read 6, iclass 27, count 0 2006.285.23:08:33.00#ibcon#end of sib2, iclass 27, count 0 2006.285.23:08:33.00#ibcon#*mode == 0, iclass 27, count 0 2006.285.23:08:33.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.23:08:33.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.23:08:33.00#ibcon#*before write, iclass 27, count 0 2006.285.23:08:33.00#ibcon#enter sib2, iclass 27, count 0 2006.285.23:08:33.00#ibcon#flushed, iclass 27, count 0 2006.285.23:08:33.00#ibcon#about to write, iclass 27, count 0 2006.285.23:08:33.00#ibcon#wrote, iclass 27, count 0 2006.285.23:08:33.00#ibcon#about to read 3, iclass 27, count 0 2006.285.23:08:33.04#ibcon#read 3, iclass 27, count 0 2006.285.23:08:33.04#ibcon#about to read 4, iclass 27, count 0 2006.285.23:08:33.04#ibcon#read 4, iclass 27, count 0 2006.285.23:08:33.04#ibcon#about to read 5, iclass 27, count 0 2006.285.23:08:33.04#ibcon#read 5, iclass 27, count 0 2006.285.23:08:33.04#ibcon#about to read 6, iclass 27, count 0 2006.285.23:08:33.04#ibcon#read 6, iclass 27, count 0 2006.285.23:08:33.04#ibcon#end of sib2, iclass 27, count 0 2006.285.23:08:33.04#ibcon#*after write, iclass 27, count 0 2006.285.23:08:33.04#ibcon#*before return 0, iclass 27, count 0 2006.285.23:08:33.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:08:33.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:08:33.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.23:08:33.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.23:08:33.04$vck44/vb=1,4 2006.285.23:08:33.05#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.23:08:33.05#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.23:08:33.05#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:33.05#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:08:33.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:08:33.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:08:33.05#ibcon#enter wrdev, iclass 29, count 2 2006.285.23:08:33.05#ibcon#first serial, iclass 29, count 2 2006.285.23:08:33.05#ibcon#enter sib2, iclass 29, count 2 2006.285.23:08:33.05#ibcon#flushed, iclass 29, count 2 2006.285.23:08:33.05#ibcon#about to write, iclass 29, count 2 2006.285.23:08:33.05#ibcon#wrote, iclass 29, count 2 2006.285.23:08:33.05#ibcon#about to read 3, iclass 29, count 2 2006.285.23:08:33.06#ibcon#read 3, iclass 29, count 2 2006.285.23:08:33.06#ibcon#about to read 4, iclass 29, count 2 2006.285.23:08:33.06#ibcon#read 4, iclass 29, count 2 2006.285.23:08:33.06#ibcon#about to read 5, iclass 29, count 2 2006.285.23:08:33.06#ibcon#read 5, iclass 29, count 2 2006.285.23:08:33.06#ibcon#about to read 6, iclass 29, count 2 2006.285.23:08:33.06#ibcon#read 6, iclass 29, count 2 2006.285.23:08:33.06#ibcon#end of sib2, iclass 29, count 2 2006.285.23:08:33.06#ibcon#*mode == 0, iclass 29, count 2 2006.285.23:08:33.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.23:08:33.06#ibcon#[27=AT01-04\r\n] 2006.285.23:08:33.06#ibcon#*before write, iclass 29, count 2 2006.285.23:08:33.06#ibcon#enter sib2, iclass 29, count 2 2006.285.23:08:33.06#ibcon#flushed, iclass 29, count 2 2006.285.23:08:33.06#ibcon#about to write, iclass 29, count 2 2006.285.23:08:33.06#ibcon#wrote, iclass 29, count 2 2006.285.23:08:33.06#ibcon#about to read 3, iclass 29, count 2 2006.285.23:08:33.09#ibcon#read 3, iclass 29, count 2 2006.285.23:08:33.09#ibcon#about to read 4, iclass 29, count 2 2006.285.23:08:33.09#ibcon#read 4, iclass 29, count 2 2006.285.23:08:33.09#ibcon#about to read 5, iclass 29, count 2 2006.285.23:08:33.09#ibcon#read 5, iclass 29, count 2 2006.285.23:08:33.09#ibcon#about to read 6, iclass 29, count 2 2006.285.23:08:33.09#ibcon#read 6, iclass 29, count 2 2006.285.23:08:33.09#ibcon#end of sib2, iclass 29, count 2 2006.285.23:08:33.09#ibcon#*after write, iclass 29, count 2 2006.285.23:08:33.09#ibcon#*before return 0, iclass 29, count 2 2006.285.23:08:33.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:08:33.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:08:33.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.23:08:33.09#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:33.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:08:33.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:08:33.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:08:33.21#ibcon#enter wrdev, iclass 29, count 0 2006.285.23:08:33.21#ibcon#first serial, iclass 29, count 0 2006.285.23:08:33.21#ibcon#enter sib2, iclass 29, count 0 2006.285.23:08:33.21#ibcon#flushed, iclass 29, count 0 2006.285.23:08:33.21#ibcon#about to write, iclass 29, count 0 2006.285.23:08:33.21#ibcon#wrote, iclass 29, count 0 2006.285.23:08:33.21#ibcon#about to read 3, iclass 29, count 0 2006.285.23:08:33.23#ibcon#read 3, iclass 29, count 0 2006.285.23:08:33.23#ibcon#about to read 4, iclass 29, count 0 2006.285.23:08:33.23#ibcon#read 4, iclass 29, count 0 2006.285.23:08:33.23#ibcon#about to read 5, iclass 29, count 0 2006.285.23:08:33.23#ibcon#read 5, iclass 29, count 0 2006.285.23:08:33.23#ibcon#about to read 6, iclass 29, count 0 2006.285.23:08:33.23#ibcon#read 6, iclass 29, count 0 2006.285.23:08:33.23#ibcon#end of sib2, iclass 29, count 0 2006.285.23:08:33.23#ibcon#*mode == 0, iclass 29, count 0 2006.285.23:08:33.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.23:08:33.23#ibcon#[27=USB\r\n] 2006.285.23:08:33.23#ibcon#*before write, iclass 29, count 0 2006.285.23:08:33.23#ibcon#enter sib2, iclass 29, count 0 2006.285.23:08:33.23#ibcon#flushed, iclass 29, count 0 2006.285.23:08:33.23#ibcon#about to write, iclass 29, count 0 2006.285.23:08:33.23#ibcon#wrote, iclass 29, count 0 2006.285.23:08:33.23#ibcon#about to read 3, iclass 29, count 0 2006.285.23:08:33.26#ibcon#read 3, iclass 29, count 0 2006.285.23:08:33.26#ibcon#about to read 4, iclass 29, count 0 2006.285.23:08:33.26#ibcon#read 4, iclass 29, count 0 2006.285.23:08:33.26#ibcon#about to read 5, iclass 29, count 0 2006.285.23:08:33.26#ibcon#read 5, iclass 29, count 0 2006.285.23:08:33.26#ibcon#about to read 6, iclass 29, count 0 2006.285.23:08:33.26#ibcon#read 6, iclass 29, count 0 2006.285.23:08:33.26#ibcon#end of sib2, iclass 29, count 0 2006.285.23:08:33.26#ibcon#*after write, iclass 29, count 0 2006.285.23:08:33.26#ibcon#*before return 0, iclass 29, count 0 2006.285.23:08:33.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:08:33.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:08:33.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.23:08:33.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.23:08:33.26$vck44/vblo=2,634.99 2006.285.23:08:33.27#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.23:08:33.27#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.23:08:33.27#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:33.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:08:33.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:08:33.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:08:33.27#ibcon#enter wrdev, iclass 31, count 0 2006.285.23:08:33.27#ibcon#first serial, iclass 31, count 0 2006.285.23:08:33.27#ibcon#enter sib2, iclass 31, count 0 2006.285.23:08:33.27#ibcon#flushed, iclass 31, count 0 2006.285.23:08:33.27#ibcon#about to write, iclass 31, count 0 2006.285.23:08:33.27#ibcon#wrote, iclass 31, count 0 2006.285.23:08:33.27#ibcon#about to read 3, iclass 31, count 0 2006.285.23:08:33.28#ibcon#read 3, iclass 31, count 0 2006.285.23:08:33.28#ibcon#about to read 4, iclass 31, count 0 2006.285.23:08:33.28#ibcon#read 4, iclass 31, count 0 2006.285.23:08:33.28#ibcon#about to read 5, iclass 31, count 0 2006.285.23:08:33.28#ibcon#read 5, iclass 31, count 0 2006.285.23:08:33.28#ibcon#about to read 6, iclass 31, count 0 2006.285.23:08:33.28#ibcon#read 6, iclass 31, count 0 2006.285.23:08:33.28#ibcon#end of sib2, iclass 31, count 0 2006.285.23:08:33.28#ibcon#*mode == 0, iclass 31, count 0 2006.285.23:08:33.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.23:08:33.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.23:08:33.28#ibcon#*before write, iclass 31, count 0 2006.285.23:08:33.28#ibcon#enter sib2, iclass 31, count 0 2006.285.23:08:33.28#ibcon#flushed, iclass 31, count 0 2006.285.23:08:33.28#ibcon#about to write, iclass 31, count 0 2006.285.23:08:33.28#ibcon#wrote, iclass 31, count 0 2006.285.23:08:33.28#ibcon#about to read 3, iclass 31, count 0 2006.285.23:08:33.32#ibcon#read 3, iclass 31, count 0 2006.285.23:08:33.32#ibcon#about to read 4, iclass 31, count 0 2006.285.23:08:33.32#ibcon#read 4, iclass 31, count 0 2006.285.23:08:33.32#ibcon#about to read 5, iclass 31, count 0 2006.285.23:08:33.32#ibcon#read 5, iclass 31, count 0 2006.285.23:08:33.32#ibcon#about to read 6, iclass 31, count 0 2006.285.23:08:33.32#ibcon#read 6, iclass 31, count 0 2006.285.23:08:33.32#ibcon#end of sib2, iclass 31, count 0 2006.285.23:08:33.32#ibcon#*after write, iclass 31, count 0 2006.285.23:08:33.32#ibcon#*before return 0, iclass 31, count 0 2006.285.23:08:33.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:08:33.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:08:33.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.23:08:33.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.23:08:33.32$vck44/vb=2,5 2006.285.23:08:33.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.23:08:33.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.23:08:33.32#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:33.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:08:33.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:08:33.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:08:33.38#ibcon#enter wrdev, iclass 33, count 2 2006.285.23:08:33.38#ibcon#first serial, iclass 33, count 2 2006.285.23:08:33.38#ibcon#enter sib2, iclass 33, count 2 2006.285.23:08:33.38#ibcon#flushed, iclass 33, count 2 2006.285.23:08:33.38#ibcon#about to write, iclass 33, count 2 2006.285.23:08:33.38#ibcon#wrote, iclass 33, count 2 2006.285.23:08:33.38#ibcon#about to read 3, iclass 33, count 2 2006.285.23:08:33.40#ibcon#read 3, iclass 33, count 2 2006.285.23:08:33.40#ibcon#about to read 4, iclass 33, count 2 2006.285.23:08:33.40#ibcon#read 4, iclass 33, count 2 2006.285.23:08:33.40#ibcon#about to read 5, iclass 33, count 2 2006.285.23:08:33.40#ibcon#read 5, iclass 33, count 2 2006.285.23:08:33.40#ibcon#about to read 6, iclass 33, count 2 2006.285.23:08:33.40#ibcon#read 6, iclass 33, count 2 2006.285.23:08:33.40#ibcon#end of sib2, iclass 33, count 2 2006.285.23:08:33.40#ibcon#*mode == 0, iclass 33, count 2 2006.285.23:08:33.40#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.23:08:33.40#ibcon#[27=AT02-05\r\n] 2006.285.23:08:33.40#ibcon#*before write, iclass 33, count 2 2006.285.23:08:33.40#ibcon#enter sib2, iclass 33, count 2 2006.285.23:08:33.40#ibcon#flushed, iclass 33, count 2 2006.285.23:08:33.40#ibcon#about to write, iclass 33, count 2 2006.285.23:08:33.40#ibcon#wrote, iclass 33, count 2 2006.285.23:08:33.40#ibcon#about to read 3, iclass 33, count 2 2006.285.23:08:33.43#ibcon#read 3, iclass 33, count 2 2006.285.23:08:33.43#ibcon#about to read 4, iclass 33, count 2 2006.285.23:08:33.43#ibcon#read 4, iclass 33, count 2 2006.285.23:08:33.43#ibcon#about to read 5, iclass 33, count 2 2006.285.23:08:33.43#ibcon#read 5, iclass 33, count 2 2006.285.23:08:33.43#ibcon#about to read 6, iclass 33, count 2 2006.285.23:08:33.43#ibcon#read 6, iclass 33, count 2 2006.285.23:08:33.43#ibcon#end of sib2, iclass 33, count 2 2006.285.23:08:33.43#ibcon#*after write, iclass 33, count 2 2006.285.23:08:33.43#ibcon#*before return 0, iclass 33, count 2 2006.285.23:08:33.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:08:33.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:08:33.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.23:08:33.43#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:33.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:08:33.55#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:08:33.55#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:08:33.55#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:08:33.55#ibcon#first serial, iclass 33, count 0 2006.285.23:08:33.55#ibcon#enter sib2, iclass 33, count 0 2006.285.23:08:33.55#ibcon#flushed, iclass 33, count 0 2006.285.23:08:33.55#ibcon#about to write, iclass 33, count 0 2006.285.23:08:33.55#ibcon#wrote, iclass 33, count 0 2006.285.23:08:33.55#ibcon#about to read 3, iclass 33, count 0 2006.285.23:08:33.57#ibcon#read 3, iclass 33, count 0 2006.285.23:08:33.57#ibcon#about to read 4, iclass 33, count 0 2006.285.23:08:33.57#ibcon#read 4, iclass 33, count 0 2006.285.23:08:33.57#ibcon#about to read 5, iclass 33, count 0 2006.285.23:08:33.57#ibcon#read 5, iclass 33, count 0 2006.285.23:08:33.57#ibcon#about to read 6, iclass 33, count 0 2006.285.23:08:33.57#ibcon#read 6, iclass 33, count 0 2006.285.23:08:33.57#ibcon#end of sib2, iclass 33, count 0 2006.285.23:08:33.57#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:08:33.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:08:33.57#ibcon#[27=USB\r\n] 2006.285.23:08:33.57#ibcon#*before write, iclass 33, count 0 2006.285.23:08:33.57#ibcon#enter sib2, iclass 33, count 0 2006.285.23:08:33.57#ibcon#flushed, iclass 33, count 0 2006.285.23:08:33.57#ibcon#about to write, iclass 33, count 0 2006.285.23:08:33.57#ibcon#wrote, iclass 33, count 0 2006.285.23:08:33.57#ibcon#about to read 3, iclass 33, count 0 2006.285.23:08:33.60#ibcon#read 3, iclass 33, count 0 2006.285.23:08:33.60#ibcon#about to read 4, iclass 33, count 0 2006.285.23:08:33.60#ibcon#read 4, iclass 33, count 0 2006.285.23:08:33.60#ibcon#about to read 5, iclass 33, count 0 2006.285.23:08:33.60#ibcon#read 5, iclass 33, count 0 2006.285.23:08:33.60#ibcon#about to read 6, iclass 33, count 0 2006.285.23:08:33.60#ibcon#read 6, iclass 33, count 0 2006.285.23:08:33.60#ibcon#end of sib2, iclass 33, count 0 2006.285.23:08:33.60#ibcon#*after write, iclass 33, count 0 2006.285.23:08:33.60#ibcon#*before return 0, iclass 33, count 0 2006.285.23:08:33.60#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:08:33.60#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:08:33.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:08:33.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:08:33.60$vck44/vblo=3,649.99 2006.285.23:08:33.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.23:08:33.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.23:08:33.60#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:33.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:08:33.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:08:33.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:08:33.60#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:08:33.60#ibcon#first serial, iclass 35, count 0 2006.285.23:08:33.60#ibcon#enter sib2, iclass 35, count 0 2006.285.23:08:33.60#ibcon#flushed, iclass 35, count 0 2006.285.23:08:33.60#ibcon#about to write, iclass 35, count 0 2006.285.23:08:33.60#ibcon#wrote, iclass 35, count 0 2006.285.23:08:33.61#ibcon#about to read 3, iclass 35, count 0 2006.285.23:08:33.62#ibcon#read 3, iclass 35, count 0 2006.285.23:08:33.62#ibcon#about to read 4, iclass 35, count 0 2006.285.23:08:33.62#ibcon#read 4, iclass 35, count 0 2006.285.23:08:33.62#ibcon#about to read 5, iclass 35, count 0 2006.285.23:08:33.62#ibcon#read 5, iclass 35, count 0 2006.285.23:08:33.62#ibcon#about to read 6, iclass 35, count 0 2006.285.23:08:33.62#ibcon#read 6, iclass 35, count 0 2006.285.23:08:33.62#ibcon#end of sib2, iclass 35, count 0 2006.285.23:08:33.62#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:08:33.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:08:33.62#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.23:08:33.62#ibcon#*before write, iclass 35, count 0 2006.285.23:08:33.62#ibcon#enter sib2, iclass 35, count 0 2006.285.23:08:33.62#ibcon#flushed, iclass 35, count 0 2006.285.23:08:33.62#ibcon#about to write, iclass 35, count 0 2006.285.23:08:33.62#ibcon#wrote, iclass 35, count 0 2006.285.23:08:33.62#ibcon#about to read 3, iclass 35, count 0 2006.285.23:08:33.66#ibcon#read 3, iclass 35, count 0 2006.285.23:08:33.66#ibcon#about to read 4, iclass 35, count 0 2006.285.23:08:33.66#ibcon#read 4, iclass 35, count 0 2006.285.23:08:33.66#ibcon#about to read 5, iclass 35, count 0 2006.285.23:08:33.66#ibcon#read 5, iclass 35, count 0 2006.285.23:08:33.66#ibcon#about to read 6, iclass 35, count 0 2006.285.23:08:33.66#ibcon#read 6, iclass 35, count 0 2006.285.23:08:33.66#ibcon#end of sib2, iclass 35, count 0 2006.285.23:08:33.66#ibcon#*after write, iclass 35, count 0 2006.285.23:08:33.66#ibcon#*before return 0, iclass 35, count 0 2006.285.23:08:33.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:08:33.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:08:33.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:08:33.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:08:33.66$vck44/vb=3,4 2006.285.23:08:33.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.23:08:33.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.23:08:33.66#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:33.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:08:33.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:08:33.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:08:33.72#ibcon#enter wrdev, iclass 37, count 2 2006.285.23:08:33.72#ibcon#first serial, iclass 37, count 2 2006.285.23:08:33.72#ibcon#enter sib2, iclass 37, count 2 2006.285.23:08:33.72#ibcon#flushed, iclass 37, count 2 2006.285.23:08:33.72#ibcon#about to write, iclass 37, count 2 2006.285.23:08:33.72#ibcon#wrote, iclass 37, count 2 2006.285.23:08:33.72#ibcon#about to read 3, iclass 37, count 2 2006.285.23:08:33.74#ibcon#read 3, iclass 37, count 2 2006.285.23:08:33.74#ibcon#about to read 4, iclass 37, count 2 2006.285.23:08:33.74#ibcon#read 4, iclass 37, count 2 2006.285.23:08:33.74#ibcon#about to read 5, iclass 37, count 2 2006.285.23:08:33.74#ibcon#read 5, iclass 37, count 2 2006.285.23:08:33.74#ibcon#about to read 6, iclass 37, count 2 2006.285.23:08:33.74#ibcon#read 6, iclass 37, count 2 2006.285.23:08:33.74#ibcon#end of sib2, iclass 37, count 2 2006.285.23:08:33.74#ibcon#*mode == 0, iclass 37, count 2 2006.285.23:08:33.74#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.23:08:33.74#ibcon#[27=AT03-04\r\n] 2006.285.23:08:33.74#ibcon#*before write, iclass 37, count 2 2006.285.23:08:33.74#ibcon#enter sib2, iclass 37, count 2 2006.285.23:08:33.74#ibcon#flushed, iclass 37, count 2 2006.285.23:08:33.74#ibcon#about to write, iclass 37, count 2 2006.285.23:08:33.74#ibcon#wrote, iclass 37, count 2 2006.285.23:08:33.74#ibcon#about to read 3, iclass 37, count 2 2006.285.23:08:33.77#ibcon#read 3, iclass 37, count 2 2006.285.23:08:33.77#ibcon#about to read 4, iclass 37, count 2 2006.285.23:08:33.77#ibcon#read 4, iclass 37, count 2 2006.285.23:08:33.77#ibcon#about to read 5, iclass 37, count 2 2006.285.23:08:33.77#ibcon#read 5, iclass 37, count 2 2006.285.23:08:33.77#ibcon#about to read 6, iclass 37, count 2 2006.285.23:08:33.77#ibcon#read 6, iclass 37, count 2 2006.285.23:08:33.77#ibcon#end of sib2, iclass 37, count 2 2006.285.23:08:33.77#ibcon#*after write, iclass 37, count 2 2006.285.23:08:33.77#ibcon#*before return 0, iclass 37, count 2 2006.285.23:08:33.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:08:33.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:08:33.77#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.23:08:33.77#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:33.77#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:08:33.89#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:08:33.89#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:08:33.89#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:08:33.89#ibcon#first serial, iclass 37, count 0 2006.285.23:08:33.89#ibcon#enter sib2, iclass 37, count 0 2006.285.23:08:33.89#ibcon#flushed, iclass 37, count 0 2006.285.23:08:33.89#ibcon#about to write, iclass 37, count 0 2006.285.23:08:33.89#ibcon#wrote, iclass 37, count 0 2006.285.23:08:33.89#ibcon#about to read 3, iclass 37, count 0 2006.285.23:08:33.91#ibcon#read 3, iclass 37, count 0 2006.285.23:08:33.91#ibcon#about to read 4, iclass 37, count 0 2006.285.23:08:33.91#ibcon#read 4, iclass 37, count 0 2006.285.23:08:33.91#ibcon#about to read 5, iclass 37, count 0 2006.285.23:08:33.91#ibcon#read 5, iclass 37, count 0 2006.285.23:08:33.91#ibcon#about to read 6, iclass 37, count 0 2006.285.23:08:33.91#ibcon#read 6, iclass 37, count 0 2006.285.23:08:33.91#ibcon#end of sib2, iclass 37, count 0 2006.285.23:08:33.91#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:08:33.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:08:33.91#ibcon#[27=USB\r\n] 2006.285.23:08:33.91#ibcon#*before write, iclass 37, count 0 2006.285.23:08:33.91#ibcon#enter sib2, iclass 37, count 0 2006.285.23:08:33.91#ibcon#flushed, iclass 37, count 0 2006.285.23:08:33.91#ibcon#about to write, iclass 37, count 0 2006.285.23:08:33.91#ibcon#wrote, iclass 37, count 0 2006.285.23:08:33.91#ibcon#about to read 3, iclass 37, count 0 2006.285.23:08:33.94#ibcon#read 3, iclass 37, count 0 2006.285.23:08:33.94#ibcon#about to read 4, iclass 37, count 0 2006.285.23:08:33.94#ibcon#read 4, iclass 37, count 0 2006.285.23:08:33.94#ibcon#about to read 5, iclass 37, count 0 2006.285.23:08:33.94#ibcon#read 5, iclass 37, count 0 2006.285.23:08:33.94#ibcon#about to read 6, iclass 37, count 0 2006.285.23:08:33.94#ibcon#read 6, iclass 37, count 0 2006.285.23:08:33.94#ibcon#end of sib2, iclass 37, count 0 2006.285.23:08:33.94#ibcon#*after write, iclass 37, count 0 2006.285.23:08:33.94#ibcon#*before return 0, iclass 37, count 0 2006.285.23:08:33.94#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:08:33.94#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:08:33.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:08:33.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:08:33.94$vck44/vblo=4,679.99 2006.285.23:08:33.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.23:08:33.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.23:08:33.94#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:33.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:08:33.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:08:33.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:08:33.94#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:08:33.94#ibcon#first serial, iclass 39, count 0 2006.285.23:08:33.94#ibcon#enter sib2, iclass 39, count 0 2006.285.23:08:33.94#ibcon#flushed, iclass 39, count 0 2006.285.23:08:33.94#ibcon#about to write, iclass 39, count 0 2006.285.23:08:33.94#ibcon#wrote, iclass 39, count 0 2006.285.23:08:33.94#ibcon#about to read 3, iclass 39, count 0 2006.285.23:08:33.96#ibcon#read 3, iclass 39, count 0 2006.285.23:08:33.96#ibcon#about to read 4, iclass 39, count 0 2006.285.23:08:33.96#ibcon#read 4, iclass 39, count 0 2006.285.23:08:33.96#ibcon#about to read 5, iclass 39, count 0 2006.285.23:08:33.96#ibcon#read 5, iclass 39, count 0 2006.285.23:08:33.96#ibcon#about to read 6, iclass 39, count 0 2006.285.23:08:33.96#ibcon#read 6, iclass 39, count 0 2006.285.23:08:33.96#ibcon#end of sib2, iclass 39, count 0 2006.285.23:08:33.96#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:08:33.96#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:08:33.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:08:33.96#ibcon#*before write, iclass 39, count 0 2006.285.23:08:33.96#ibcon#enter sib2, iclass 39, count 0 2006.285.23:08:33.96#ibcon#flushed, iclass 39, count 0 2006.285.23:08:33.96#ibcon#about to write, iclass 39, count 0 2006.285.23:08:33.96#ibcon#wrote, iclass 39, count 0 2006.285.23:08:33.96#ibcon#about to read 3, iclass 39, count 0 2006.285.23:08:34.00#ibcon#read 3, iclass 39, count 0 2006.285.23:08:34.00#ibcon#about to read 4, iclass 39, count 0 2006.285.23:08:34.00#ibcon#read 4, iclass 39, count 0 2006.285.23:08:34.00#ibcon#about to read 5, iclass 39, count 0 2006.285.23:08:34.00#ibcon#read 5, iclass 39, count 0 2006.285.23:08:34.00#ibcon#about to read 6, iclass 39, count 0 2006.285.23:08:34.00#ibcon#read 6, iclass 39, count 0 2006.285.23:08:34.00#ibcon#end of sib2, iclass 39, count 0 2006.285.23:08:34.00#ibcon#*after write, iclass 39, count 0 2006.285.23:08:34.00#ibcon#*before return 0, iclass 39, count 0 2006.285.23:08:34.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:08:34.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:08:34.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:08:34.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:08:34.00$vck44/vb=4,5 2006.285.23:08:34.00#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.23:08:34.00#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.23:08:34.00#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:34.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:08:34.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:08:34.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:08:34.06#ibcon#enter wrdev, iclass 3, count 2 2006.285.23:08:34.06#ibcon#first serial, iclass 3, count 2 2006.285.23:08:34.06#ibcon#enter sib2, iclass 3, count 2 2006.285.23:08:34.06#ibcon#flushed, iclass 3, count 2 2006.285.23:08:34.06#ibcon#about to write, iclass 3, count 2 2006.285.23:08:34.06#ibcon#wrote, iclass 3, count 2 2006.285.23:08:34.06#ibcon#about to read 3, iclass 3, count 2 2006.285.23:08:34.08#ibcon#read 3, iclass 3, count 2 2006.285.23:08:34.08#ibcon#about to read 4, iclass 3, count 2 2006.285.23:08:34.08#ibcon#read 4, iclass 3, count 2 2006.285.23:08:34.08#ibcon#about to read 5, iclass 3, count 2 2006.285.23:08:34.08#ibcon#read 5, iclass 3, count 2 2006.285.23:08:34.08#ibcon#about to read 6, iclass 3, count 2 2006.285.23:08:34.08#ibcon#read 6, iclass 3, count 2 2006.285.23:08:34.08#ibcon#end of sib2, iclass 3, count 2 2006.285.23:08:34.08#ibcon#*mode == 0, iclass 3, count 2 2006.285.23:08:34.08#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.23:08:34.08#ibcon#[27=AT04-05\r\n] 2006.285.23:08:34.08#ibcon#*before write, iclass 3, count 2 2006.285.23:08:34.08#ibcon#enter sib2, iclass 3, count 2 2006.285.23:08:34.08#ibcon#flushed, iclass 3, count 2 2006.285.23:08:34.08#ibcon#about to write, iclass 3, count 2 2006.285.23:08:34.08#ibcon#wrote, iclass 3, count 2 2006.285.23:08:34.08#ibcon#about to read 3, iclass 3, count 2 2006.285.23:08:34.11#ibcon#read 3, iclass 3, count 2 2006.285.23:08:34.11#ibcon#about to read 4, iclass 3, count 2 2006.285.23:08:34.11#ibcon#read 4, iclass 3, count 2 2006.285.23:08:34.11#ibcon#about to read 5, iclass 3, count 2 2006.285.23:08:34.11#ibcon#read 5, iclass 3, count 2 2006.285.23:08:34.11#ibcon#about to read 6, iclass 3, count 2 2006.285.23:08:34.11#ibcon#read 6, iclass 3, count 2 2006.285.23:08:34.11#ibcon#end of sib2, iclass 3, count 2 2006.285.23:08:34.11#ibcon#*after write, iclass 3, count 2 2006.285.23:08:34.11#ibcon#*before return 0, iclass 3, count 2 2006.285.23:08:34.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:08:34.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:08:34.11#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.23:08:34.11#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:34.11#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:08:34.23#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:08:34.23#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:08:34.23#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:08:34.23#ibcon#first serial, iclass 3, count 0 2006.285.23:08:34.23#ibcon#enter sib2, iclass 3, count 0 2006.285.23:08:34.23#ibcon#flushed, iclass 3, count 0 2006.285.23:08:34.23#ibcon#about to write, iclass 3, count 0 2006.285.23:08:34.23#ibcon#wrote, iclass 3, count 0 2006.285.23:08:34.23#ibcon#about to read 3, iclass 3, count 0 2006.285.23:08:34.25#ibcon#read 3, iclass 3, count 0 2006.285.23:08:34.25#ibcon#about to read 4, iclass 3, count 0 2006.285.23:08:34.25#ibcon#read 4, iclass 3, count 0 2006.285.23:08:34.25#ibcon#about to read 5, iclass 3, count 0 2006.285.23:08:34.25#ibcon#read 5, iclass 3, count 0 2006.285.23:08:34.25#ibcon#about to read 6, iclass 3, count 0 2006.285.23:08:34.25#ibcon#read 6, iclass 3, count 0 2006.285.23:08:34.25#ibcon#end of sib2, iclass 3, count 0 2006.285.23:08:34.25#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:08:34.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:08:34.25#ibcon#[27=USB\r\n] 2006.285.23:08:34.25#ibcon#*before write, iclass 3, count 0 2006.285.23:08:34.25#ibcon#enter sib2, iclass 3, count 0 2006.285.23:08:34.25#ibcon#flushed, iclass 3, count 0 2006.285.23:08:34.25#ibcon#about to write, iclass 3, count 0 2006.285.23:08:34.25#ibcon#wrote, iclass 3, count 0 2006.285.23:08:34.25#ibcon#about to read 3, iclass 3, count 0 2006.285.23:08:34.28#ibcon#read 3, iclass 3, count 0 2006.285.23:08:34.28#ibcon#about to read 4, iclass 3, count 0 2006.285.23:08:34.28#ibcon#read 4, iclass 3, count 0 2006.285.23:08:34.28#ibcon#about to read 5, iclass 3, count 0 2006.285.23:08:34.28#ibcon#read 5, iclass 3, count 0 2006.285.23:08:34.28#ibcon#about to read 6, iclass 3, count 0 2006.285.23:08:34.28#ibcon#read 6, iclass 3, count 0 2006.285.23:08:34.28#ibcon#end of sib2, iclass 3, count 0 2006.285.23:08:34.28#ibcon#*after write, iclass 3, count 0 2006.285.23:08:34.28#ibcon#*before return 0, iclass 3, count 0 2006.285.23:08:34.28#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:08:34.28#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:08:34.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:08:34.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:08:34.28$vck44/vblo=5,709.99 2006.285.23:08:34.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.23:08:34.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.23:08:34.28#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:34.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:08:34.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:08:34.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:08:34.28#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:08:34.28#ibcon#first serial, iclass 5, count 0 2006.285.23:08:34.28#ibcon#enter sib2, iclass 5, count 0 2006.285.23:08:34.28#ibcon#flushed, iclass 5, count 0 2006.285.23:08:34.28#ibcon#about to write, iclass 5, count 0 2006.285.23:08:34.28#ibcon#wrote, iclass 5, count 0 2006.285.23:08:34.28#ibcon#about to read 3, iclass 5, count 0 2006.285.23:08:34.30#ibcon#read 3, iclass 5, count 0 2006.285.23:08:34.30#ibcon#about to read 4, iclass 5, count 0 2006.285.23:08:34.30#ibcon#read 4, iclass 5, count 0 2006.285.23:08:34.30#ibcon#about to read 5, iclass 5, count 0 2006.285.23:08:34.30#ibcon#read 5, iclass 5, count 0 2006.285.23:08:34.30#ibcon#about to read 6, iclass 5, count 0 2006.285.23:08:34.30#ibcon#read 6, iclass 5, count 0 2006.285.23:08:34.30#ibcon#end of sib2, iclass 5, count 0 2006.285.23:08:34.30#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:08:34.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:08:34.30#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:08:34.30#ibcon#*before write, iclass 5, count 0 2006.285.23:08:34.30#ibcon#enter sib2, iclass 5, count 0 2006.285.23:08:34.30#ibcon#flushed, iclass 5, count 0 2006.285.23:08:34.30#ibcon#about to write, iclass 5, count 0 2006.285.23:08:34.30#ibcon#wrote, iclass 5, count 0 2006.285.23:08:34.30#ibcon#about to read 3, iclass 5, count 0 2006.285.23:08:34.34#ibcon#read 3, iclass 5, count 0 2006.285.23:08:34.34#ibcon#about to read 4, iclass 5, count 0 2006.285.23:08:34.34#ibcon#read 4, iclass 5, count 0 2006.285.23:08:34.34#ibcon#about to read 5, iclass 5, count 0 2006.285.23:08:34.34#ibcon#read 5, iclass 5, count 0 2006.285.23:08:34.34#ibcon#about to read 6, iclass 5, count 0 2006.285.23:08:34.34#ibcon#read 6, iclass 5, count 0 2006.285.23:08:34.34#ibcon#end of sib2, iclass 5, count 0 2006.285.23:08:34.34#ibcon#*after write, iclass 5, count 0 2006.285.23:08:34.34#ibcon#*before return 0, iclass 5, count 0 2006.285.23:08:34.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:08:34.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:08:34.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:08:34.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:08:34.34$vck44/vb=5,4 2006.285.23:08:34.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.23:08:34.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.23:08:34.34#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:34.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:08:34.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:08:34.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:08:34.40#ibcon#enter wrdev, iclass 7, count 2 2006.285.23:08:34.40#ibcon#first serial, iclass 7, count 2 2006.285.23:08:34.40#ibcon#enter sib2, iclass 7, count 2 2006.285.23:08:34.40#ibcon#flushed, iclass 7, count 2 2006.285.23:08:34.40#ibcon#about to write, iclass 7, count 2 2006.285.23:08:34.40#ibcon#wrote, iclass 7, count 2 2006.285.23:08:34.40#ibcon#about to read 3, iclass 7, count 2 2006.285.23:08:34.42#ibcon#read 3, iclass 7, count 2 2006.285.23:08:34.42#ibcon#about to read 4, iclass 7, count 2 2006.285.23:08:34.42#ibcon#read 4, iclass 7, count 2 2006.285.23:08:34.42#ibcon#about to read 5, iclass 7, count 2 2006.285.23:08:34.42#ibcon#read 5, iclass 7, count 2 2006.285.23:08:34.42#ibcon#about to read 6, iclass 7, count 2 2006.285.23:08:34.42#ibcon#read 6, iclass 7, count 2 2006.285.23:08:34.42#ibcon#end of sib2, iclass 7, count 2 2006.285.23:08:34.42#ibcon#*mode == 0, iclass 7, count 2 2006.285.23:08:34.42#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.23:08:34.42#ibcon#[27=AT05-04\r\n] 2006.285.23:08:34.42#ibcon#*before write, iclass 7, count 2 2006.285.23:08:34.42#ibcon#enter sib2, iclass 7, count 2 2006.285.23:08:34.42#ibcon#flushed, iclass 7, count 2 2006.285.23:08:34.42#ibcon#about to write, iclass 7, count 2 2006.285.23:08:34.42#ibcon#wrote, iclass 7, count 2 2006.285.23:08:34.42#ibcon#about to read 3, iclass 7, count 2 2006.285.23:08:34.45#ibcon#read 3, iclass 7, count 2 2006.285.23:08:34.45#ibcon#about to read 4, iclass 7, count 2 2006.285.23:08:34.45#ibcon#read 4, iclass 7, count 2 2006.285.23:08:34.45#ibcon#about to read 5, iclass 7, count 2 2006.285.23:08:34.45#ibcon#read 5, iclass 7, count 2 2006.285.23:08:34.45#ibcon#about to read 6, iclass 7, count 2 2006.285.23:08:34.45#ibcon#read 6, iclass 7, count 2 2006.285.23:08:34.45#ibcon#end of sib2, iclass 7, count 2 2006.285.23:08:34.45#ibcon#*after write, iclass 7, count 2 2006.285.23:08:34.45#ibcon#*before return 0, iclass 7, count 2 2006.285.23:08:34.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:08:34.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:08:34.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.23:08:34.45#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:34.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:08:34.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:08:34.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:08:34.57#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:08:34.57#ibcon#first serial, iclass 7, count 0 2006.285.23:08:34.57#ibcon#enter sib2, iclass 7, count 0 2006.285.23:08:34.57#ibcon#flushed, iclass 7, count 0 2006.285.23:08:34.57#ibcon#about to write, iclass 7, count 0 2006.285.23:08:34.57#ibcon#wrote, iclass 7, count 0 2006.285.23:08:34.57#ibcon#about to read 3, iclass 7, count 0 2006.285.23:08:34.59#ibcon#read 3, iclass 7, count 0 2006.285.23:08:34.59#ibcon#about to read 4, iclass 7, count 0 2006.285.23:08:34.59#ibcon#read 4, iclass 7, count 0 2006.285.23:08:34.59#ibcon#about to read 5, iclass 7, count 0 2006.285.23:08:34.59#ibcon#read 5, iclass 7, count 0 2006.285.23:08:34.59#ibcon#about to read 6, iclass 7, count 0 2006.285.23:08:34.59#ibcon#read 6, iclass 7, count 0 2006.285.23:08:34.59#ibcon#end of sib2, iclass 7, count 0 2006.285.23:08:34.59#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:08:34.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:08:34.59#ibcon#[27=USB\r\n] 2006.285.23:08:34.59#ibcon#*before write, iclass 7, count 0 2006.285.23:08:34.59#ibcon#enter sib2, iclass 7, count 0 2006.285.23:08:34.59#ibcon#flushed, iclass 7, count 0 2006.285.23:08:34.59#ibcon#about to write, iclass 7, count 0 2006.285.23:08:34.59#ibcon#wrote, iclass 7, count 0 2006.285.23:08:34.59#ibcon#about to read 3, iclass 7, count 0 2006.285.23:08:34.62#ibcon#read 3, iclass 7, count 0 2006.285.23:08:34.62#ibcon#about to read 4, iclass 7, count 0 2006.285.23:08:34.62#ibcon#read 4, iclass 7, count 0 2006.285.23:08:34.62#ibcon#about to read 5, iclass 7, count 0 2006.285.23:08:34.62#ibcon#read 5, iclass 7, count 0 2006.285.23:08:34.62#ibcon#about to read 6, iclass 7, count 0 2006.285.23:08:34.62#ibcon#read 6, iclass 7, count 0 2006.285.23:08:34.62#ibcon#end of sib2, iclass 7, count 0 2006.285.23:08:34.62#ibcon#*after write, iclass 7, count 0 2006.285.23:08:34.62#ibcon#*before return 0, iclass 7, count 0 2006.285.23:08:34.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:08:34.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:08:34.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:08:34.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:08:34.62$vck44/vblo=6,719.99 2006.285.23:08:34.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.23:08:34.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.23:08:34.62#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:34.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:08:34.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:08:34.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:08:34.62#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:08:34.62#ibcon#first serial, iclass 11, count 0 2006.285.23:08:34.62#ibcon#enter sib2, iclass 11, count 0 2006.285.23:08:34.62#ibcon#flushed, iclass 11, count 0 2006.285.23:08:34.62#ibcon#about to write, iclass 11, count 0 2006.285.23:08:34.62#ibcon#wrote, iclass 11, count 0 2006.285.23:08:34.62#ibcon#about to read 3, iclass 11, count 0 2006.285.23:08:34.64#ibcon#read 3, iclass 11, count 0 2006.285.23:08:34.64#ibcon#about to read 4, iclass 11, count 0 2006.285.23:08:34.64#ibcon#read 4, iclass 11, count 0 2006.285.23:08:34.64#ibcon#about to read 5, iclass 11, count 0 2006.285.23:08:34.64#ibcon#read 5, iclass 11, count 0 2006.285.23:08:34.64#ibcon#about to read 6, iclass 11, count 0 2006.285.23:08:34.64#ibcon#read 6, iclass 11, count 0 2006.285.23:08:34.64#ibcon#end of sib2, iclass 11, count 0 2006.285.23:08:34.64#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:08:34.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:08:34.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:08:34.64#ibcon#*before write, iclass 11, count 0 2006.285.23:08:34.64#ibcon#enter sib2, iclass 11, count 0 2006.285.23:08:34.64#ibcon#flushed, iclass 11, count 0 2006.285.23:08:34.64#ibcon#about to write, iclass 11, count 0 2006.285.23:08:34.64#ibcon#wrote, iclass 11, count 0 2006.285.23:08:34.64#ibcon#about to read 3, iclass 11, count 0 2006.285.23:08:34.68#ibcon#read 3, iclass 11, count 0 2006.285.23:08:34.68#ibcon#about to read 4, iclass 11, count 0 2006.285.23:08:34.68#ibcon#read 4, iclass 11, count 0 2006.285.23:08:34.68#ibcon#about to read 5, iclass 11, count 0 2006.285.23:08:34.68#ibcon#read 5, iclass 11, count 0 2006.285.23:08:34.68#ibcon#about to read 6, iclass 11, count 0 2006.285.23:08:34.68#ibcon#read 6, iclass 11, count 0 2006.285.23:08:34.68#ibcon#end of sib2, iclass 11, count 0 2006.285.23:08:34.68#ibcon#*after write, iclass 11, count 0 2006.285.23:08:34.68#ibcon#*before return 0, iclass 11, count 0 2006.285.23:08:34.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:08:34.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:08:34.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:08:34.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:08:34.68$vck44/vb=6,3 2006.285.23:08:34.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.23:08:34.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.23:08:34.68#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:34.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:08:34.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:08:34.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:08:34.74#ibcon#enter wrdev, iclass 13, count 2 2006.285.23:08:34.74#ibcon#first serial, iclass 13, count 2 2006.285.23:08:34.74#ibcon#enter sib2, iclass 13, count 2 2006.285.23:08:34.74#ibcon#flushed, iclass 13, count 2 2006.285.23:08:34.74#ibcon#about to write, iclass 13, count 2 2006.285.23:08:34.74#ibcon#wrote, iclass 13, count 2 2006.285.23:08:34.74#ibcon#about to read 3, iclass 13, count 2 2006.285.23:08:34.76#ibcon#read 3, iclass 13, count 2 2006.285.23:08:34.76#ibcon#about to read 4, iclass 13, count 2 2006.285.23:08:34.76#ibcon#read 4, iclass 13, count 2 2006.285.23:08:34.76#ibcon#about to read 5, iclass 13, count 2 2006.285.23:08:34.76#ibcon#read 5, iclass 13, count 2 2006.285.23:08:34.76#ibcon#about to read 6, iclass 13, count 2 2006.285.23:08:34.76#ibcon#read 6, iclass 13, count 2 2006.285.23:08:34.76#ibcon#end of sib2, iclass 13, count 2 2006.285.23:08:34.76#ibcon#*mode == 0, iclass 13, count 2 2006.285.23:08:34.76#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.23:08:34.76#ibcon#[27=AT06-03\r\n] 2006.285.23:08:34.76#ibcon#*before write, iclass 13, count 2 2006.285.23:08:34.76#ibcon#enter sib2, iclass 13, count 2 2006.285.23:08:34.76#ibcon#flushed, iclass 13, count 2 2006.285.23:08:34.76#ibcon#about to write, iclass 13, count 2 2006.285.23:08:34.76#ibcon#wrote, iclass 13, count 2 2006.285.23:08:34.76#ibcon#about to read 3, iclass 13, count 2 2006.285.23:08:34.79#ibcon#read 3, iclass 13, count 2 2006.285.23:08:34.79#ibcon#about to read 4, iclass 13, count 2 2006.285.23:08:34.79#ibcon#read 4, iclass 13, count 2 2006.285.23:08:34.79#ibcon#about to read 5, iclass 13, count 2 2006.285.23:08:34.79#ibcon#read 5, iclass 13, count 2 2006.285.23:08:34.79#ibcon#about to read 6, iclass 13, count 2 2006.285.23:08:34.79#ibcon#read 6, iclass 13, count 2 2006.285.23:08:34.79#ibcon#end of sib2, iclass 13, count 2 2006.285.23:08:34.79#ibcon#*after write, iclass 13, count 2 2006.285.23:08:34.79#ibcon#*before return 0, iclass 13, count 2 2006.285.23:08:34.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:08:34.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:08:34.79#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.23:08:34.79#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:34.79#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:08:34.91#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:08:34.91#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:08:34.91#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:08:34.91#ibcon#first serial, iclass 13, count 0 2006.285.23:08:34.91#ibcon#enter sib2, iclass 13, count 0 2006.285.23:08:34.91#ibcon#flushed, iclass 13, count 0 2006.285.23:08:34.91#ibcon#about to write, iclass 13, count 0 2006.285.23:08:34.91#ibcon#wrote, iclass 13, count 0 2006.285.23:08:34.91#ibcon#about to read 3, iclass 13, count 0 2006.285.23:08:34.93#ibcon#read 3, iclass 13, count 0 2006.285.23:08:34.93#ibcon#about to read 4, iclass 13, count 0 2006.285.23:08:34.93#ibcon#read 4, iclass 13, count 0 2006.285.23:08:34.93#ibcon#about to read 5, iclass 13, count 0 2006.285.23:08:34.93#ibcon#read 5, iclass 13, count 0 2006.285.23:08:34.93#ibcon#about to read 6, iclass 13, count 0 2006.285.23:08:34.93#ibcon#read 6, iclass 13, count 0 2006.285.23:08:34.93#ibcon#end of sib2, iclass 13, count 0 2006.285.23:08:34.93#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:08:34.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:08:34.93#ibcon#[27=USB\r\n] 2006.285.23:08:34.93#ibcon#*before write, iclass 13, count 0 2006.285.23:08:34.93#ibcon#enter sib2, iclass 13, count 0 2006.285.23:08:34.93#ibcon#flushed, iclass 13, count 0 2006.285.23:08:34.93#ibcon#about to write, iclass 13, count 0 2006.285.23:08:34.93#ibcon#wrote, iclass 13, count 0 2006.285.23:08:34.93#ibcon#about to read 3, iclass 13, count 0 2006.285.23:08:34.96#ibcon#read 3, iclass 13, count 0 2006.285.23:08:34.96#ibcon#about to read 4, iclass 13, count 0 2006.285.23:08:34.96#ibcon#read 4, iclass 13, count 0 2006.285.23:08:34.96#ibcon#about to read 5, iclass 13, count 0 2006.285.23:08:34.96#ibcon#read 5, iclass 13, count 0 2006.285.23:08:34.96#ibcon#about to read 6, iclass 13, count 0 2006.285.23:08:34.96#ibcon#read 6, iclass 13, count 0 2006.285.23:08:34.96#ibcon#end of sib2, iclass 13, count 0 2006.285.23:08:34.96#ibcon#*after write, iclass 13, count 0 2006.285.23:08:34.96#ibcon#*before return 0, iclass 13, count 0 2006.285.23:08:34.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:08:34.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:08:34.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:08:34.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:08:34.96$vck44/vblo=7,734.99 2006.285.23:08:34.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.23:08:34.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.23:08:34.96#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:34.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:08:34.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:08:34.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:08:34.96#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:08:34.96#ibcon#first serial, iclass 15, count 0 2006.285.23:08:34.96#ibcon#enter sib2, iclass 15, count 0 2006.285.23:08:34.96#ibcon#flushed, iclass 15, count 0 2006.285.23:08:34.96#ibcon#about to write, iclass 15, count 0 2006.285.23:08:34.96#ibcon#wrote, iclass 15, count 0 2006.285.23:08:34.96#ibcon#about to read 3, iclass 15, count 0 2006.285.23:08:34.98#ibcon#read 3, iclass 15, count 0 2006.285.23:08:34.98#ibcon#about to read 4, iclass 15, count 0 2006.285.23:08:34.98#ibcon#read 4, iclass 15, count 0 2006.285.23:08:34.98#ibcon#about to read 5, iclass 15, count 0 2006.285.23:08:34.98#ibcon#read 5, iclass 15, count 0 2006.285.23:08:34.98#ibcon#about to read 6, iclass 15, count 0 2006.285.23:08:34.98#ibcon#read 6, iclass 15, count 0 2006.285.23:08:34.98#ibcon#end of sib2, iclass 15, count 0 2006.285.23:08:34.98#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:08:34.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:08:34.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:08:34.98#ibcon#*before write, iclass 15, count 0 2006.285.23:08:34.98#ibcon#enter sib2, iclass 15, count 0 2006.285.23:08:34.98#ibcon#flushed, iclass 15, count 0 2006.285.23:08:34.98#ibcon#about to write, iclass 15, count 0 2006.285.23:08:34.98#ibcon#wrote, iclass 15, count 0 2006.285.23:08:34.98#ibcon#about to read 3, iclass 15, count 0 2006.285.23:08:35.02#ibcon#read 3, iclass 15, count 0 2006.285.23:08:35.02#ibcon#about to read 4, iclass 15, count 0 2006.285.23:08:35.02#ibcon#read 4, iclass 15, count 0 2006.285.23:08:35.02#ibcon#about to read 5, iclass 15, count 0 2006.285.23:08:35.02#ibcon#read 5, iclass 15, count 0 2006.285.23:08:35.02#ibcon#about to read 6, iclass 15, count 0 2006.285.23:08:35.02#ibcon#read 6, iclass 15, count 0 2006.285.23:08:35.02#ibcon#end of sib2, iclass 15, count 0 2006.285.23:08:35.02#ibcon#*after write, iclass 15, count 0 2006.285.23:08:35.02#ibcon#*before return 0, iclass 15, count 0 2006.285.23:08:35.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:08:35.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:08:35.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:08:35.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:08:35.02$vck44/vb=7,4 2006.285.23:08:35.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.23:08:35.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.23:08:35.02#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:35.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:08:35.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:08:35.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:08:35.08#ibcon#enter wrdev, iclass 17, count 2 2006.285.23:08:35.08#ibcon#first serial, iclass 17, count 2 2006.285.23:08:35.08#ibcon#enter sib2, iclass 17, count 2 2006.285.23:08:35.08#ibcon#flushed, iclass 17, count 2 2006.285.23:08:35.08#ibcon#about to write, iclass 17, count 2 2006.285.23:08:35.08#ibcon#wrote, iclass 17, count 2 2006.285.23:08:35.08#ibcon#about to read 3, iclass 17, count 2 2006.285.23:08:35.10#ibcon#read 3, iclass 17, count 2 2006.285.23:08:35.10#ibcon#about to read 4, iclass 17, count 2 2006.285.23:08:35.10#ibcon#read 4, iclass 17, count 2 2006.285.23:08:35.10#ibcon#about to read 5, iclass 17, count 2 2006.285.23:08:35.10#ibcon#read 5, iclass 17, count 2 2006.285.23:08:35.10#ibcon#about to read 6, iclass 17, count 2 2006.285.23:08:35.10#ibcon#read 6, iclass 17, count 2 2006.285.23:08:35.10#ibcon#end of sib2, iclass 17, count 2 2006.285.23:08:35.10#ibcon#*mode == 0, iclass 17, count 2 2006.285.23:08:35.10#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.23:08:35.10#ibcon#[27=AT07-04\r\n] 2006.285.23:08:35.10#ibcon#*before write, iclass 17, count 2 2006.285.23:08:35.10#ibcon#enter sib2, iclass 17, count 2 2006.285.23:08:35.10#ibcon#flushed, iclass 17, count 2 2006.285.23:08:35.10#ibcon#about to write, iclass 17, count 2 2006.285.23:08:35.10#ibcon#wrote, iclass 17, count 2 2006.285.23:08:35.10#ibcon#about to read 3, iclass 17, count 2 2006.285.23:08:35.13#trakl#Source acquired 2006.285.23:08:35.13#ibcon#read 3, iclass 17, count 2 2006.285.23:08:35.13#ibcon#about to read 4, iclass 17, count 2 2006.285.23:08:35.13#ibcon#read 4, iclass 17, count 2 2006.285.23:08:35.13#ibcon#about to read 5, iclass 17, count 2 2006.285.23:08:35.13#ibcon#read 5, iclass 17, count 2 2006.285.23:08:35.13#ibcon#about to read 6, iclass 17, count 2 2006.285.23:08:35.13#ibcon#read 6, iclass 17, count 2 2006.285.23:08:35.13#ibcon#end of sib2, iclass 17, count 2 2006.285.23:08:35.13#ibcon#*after write, iclass 17, count 2 2006.285.23:08:35.13#ibcon#*before return 0, iclass 17, count 2 2006.285.23:08:35.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:08:35.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:08:35.13#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.23:08:35.13#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:35.13#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:08:35.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:08:35.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:08:35.25#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:08:35.25#ibcon#first serial, iclass 17, count 0 2006.285.23:08:35.25#ibcon#enter sib2, iclass 17, count 0 2006.285.23:08:35.25#ibcon#flushed, iclass 17, count 0 2006.285.23:08:35.25#ibcon#about to write, iclass 17, count 0 2006.285.23:08:35.25#ibcon#wrote, iclass 17, count 0 2006.285.23:08:35.25#ibcon#about to read 3, iclass 17, count 0 2006.285.23:08:35.27#ibcon#read 3, iclass 17, count 0 2006.285.23:08:35.27#ibcon#about to read 4, iclass 17, count 0 2006.285.23:08:35.27#ibcon#read 4, iclass 17, count 0 2006.285.23:08:35.27#ibcon#about to read 5, iclass 17, count 0 2006.285.23:08:35.27#ibcon#read 5, iclass 17, count 0 2006.285.23:08:35.27#ibcon#about to read 6, iclass 17, count 0 2006.285.23:08:35.27#ibcon#read 6, iclass 17, count 0 2006.285.23:08:35.27#ibcon#end of sib2, iclass 17, count 0 2006.285.23:08:35.27#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:08:35.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:08:35.27#ibcon#[27=USB\r\n] 2006.285.23:08:35.27#ibcon#*before write, iclass 17, count 0 2006.285.23:08:35.27#ibcon#enter sib2, iclass 17, count 0 2006.285.23:08:35.27#ibcon#flushed, iclass 17, count 0 2006.285.23:08:35.27#ibcon#about to write, iclass 17, count 0 2006.285.23:08:35.27#ibcon#wrote, iclass 17, count 0 2006.285.23:08:35.27#ibcon#about to read 3, iclass 17, count 0 2006.285.23:08:35.30#ibcon#read 3, iclass 17, count 0 2006.285.23:08:35.30#ibcon#about to read 4, iclass 17, count 0 2006.285.23:08:35.30#ibcon#read 4, iclass 17, count 0 2006.285.23:08:35.30#ibcon#about to read 5, iclass 17, count 0 2006.285.23:08:35.30#ibcon#read 5, iclass 17, count 0 2006.285.23:08:35.30#ibcon#about to read 6, iclass 17, count 0 2006.285.23:08:35.30#ibcon#read 6, iclass 17, count 0 2006.285.23:08:35.30#ibcon#end of sib2, iclass 17, count 0 2006.285.23:08:35.30#ibcon#*after write, iclass 17, count 0 2006.285.23:08:35.30#ibcon#*before return 0, iclass 17, count 0 2006.285.23:08:35.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:08:35.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:08:35.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:08:35.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:08:35.30$vck44/vblo=8,744.99 2006.285.23:08:35.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.23:08:35.30#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.23:08:35.30#ibcon#ireg 17 cls_cnt 0 2006.285.23:08:35.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:08:35.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:08:35.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:08:35.30#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:08:35.30#ibcon#first serial, iclass 19, count 0 2006.285.23:08:35.30#ibcon#enter sib2, iclass 19, count 0 2006.285.23:08:35.30#ibcon#flushed, iclass 19, count 0 2006.285.23:08:35.30#ibcon#about to write, iclass 19, count 0 2006.285.23:08:35.30#ibcon#wrote, iclass 19, count 0 2006.285.23:08:35.31#ibcon#about to read 3, iclass 19, count 0 2006.285.23:08:35.32#ibcon#read 3, iclass 19, count 0 2006.285.23:08:35.32#ibcon#about to read 4, iclass 19, count 0 2006.285.23:08:35.32#ibcon#read 4, iclass 19, count 0 2006.285.23:08:35.32#ibcon#about to read 5, iclass 19, count 0 2006.285.23:08:35.32#ibcon#read 5, iclass 19, count 0 2006.285.23:08:35.32#ibcon#about to read 6, iclass 19, count 0 2006.285.23:08:35.32#ibcon#read 6, iclass 19, count 0 2006.285.23:08:35.32#ibcon#end of sib2, iclass 19, count 0 2006.285.23:08:35.32#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:08:35.32#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:08:35.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:08:35.32#ibcon#*before write, iclass 19, count 0 2006.285.23:08:35.32#ibcon#enter sib2, iclass 19, count 0 2006.285.23:08:35.32#ibcon#flushed, iclass 19, count 0 2006.285.23:08:35.32#ibcon#about to write, iclass 19, count 0 2006.285.23:08:35.32#ibcon#wrote, iclass 19, count 0 2006.285.23:08:35.32#ibcon#about to read 3, iclass 19, count 0 2006.285.23:08:35.36#ibcon#read 3, iclass 19, count 0 2006.285.23:08:35.36#ibcon#about to read 4, iclass 19, count 0 2006.285.23:08:35.36#ibcon#read 4, iclass 19, count 0 2006.285.23:08:35.36#ibcon#about to read 5, iclass 19, count 0 2006.285.23:08:35.36#ibcon#read 5, iclass 19, count 0 2006.285.23:08:35.36#ibcon#about to read 6, iclass 19, count 0 2006.285.23:08:35.36#ibcon#read 6, iclass 19, count 0 2006.285.23:08:35.36#ibcon#end of sib2, iclass 19, count 0 2006.285.23:08:35.36#ibcon#*after write, iclass 19, count 0 2006.285.23:08:35.36#ibcon#*before return 0, iclass 19, count 0 2006.285.23:08:35.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:08:35.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:08:35.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:08:35.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:08:35.36$vck44/vb=8,4 2006.285.23:08:35.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.23:08:35.36#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.23:08:35.36#ibcon#ireg 11 cls_cnt 2 2006.285.23:08:35.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:08:35.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:08:35.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:08:35.42#ibcon#enter wrdev, iclass 21, count 2 2006.285.23:08:35.42#ibcon#first serial, iclass 21, count 2 2006.285.23:08:35.42#ibcon#enter sib2, iclass 21, count 2 2006.285.23:08:35.42#ibcon#flushed, iclass 21, count 2 2006.285.23:08:35.42#ibcon#about to write, iclass 21, count 2 2006.285.23:08:35.42#ibcon#wrote, iclass 21, count 2 2006.285.23:08:35.42#ibcon#about to read 3, iclass 21, count 2 2006.285.23:08:35.44#ibcon#read 3, iclass 21, count 2 2006.285.23:08:35.44#ibcon#about to read 4, iclass 21, count 2 2006.285.23:08:35.44#ibcon#read 4, iclass 21, count 2 2006.285.23:08:35.44#ibcon#about to read 5, iclass 21, count 2 2006.285.23:08:35.44#ibcon#read 5, iclass 21, count 2 2006.285.23:08:35.44#ibcon#about to read 6, iclass 21, count 2 2006.285.23:08:35.44#ibcon#read 6, iclass 21, count 2 2006.285.23:08:35.44#ibcon#end of sib2, iclass 21, count 2 2006.285.23:08:35.44#ibcon#*mode == 0, iclass 21, count 2 2006.285.23:08:35.44#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.23:08:35.44#ibcon#[27=AT08-04\r\n] 2006.285.23:08:35.44#ibcon#*before write, iclass 21, count 2 2006.285.23:08:35.44#ibcon#enter sib2, iclass 21, count 2 2006.285.23:08:35.44#ibcon#flushed, iclass 21, count 2 2006.285.23:08:35.44#ibcon#about to write, iclass 21, count 2 2006.285.23:08:35.44#ibcon#wrote, iclass 21, count 2 2006.285.23:08:35.44#ibcon#about to read 3, iclass 21, count 2 2006.285.23:08:35.47#ibcon#read 3, iclass 21, count 2 2006.285.23:08:35.47#ibcon#about to read 4, iclass 21, count 2 2006.285.23:08:35.47#ibcon#read 4, iclass 21, count 2 2006.285.23:08:35.47#ibcon#about to read 5, iclass 21, count 2 2006.285.23:08:35.47#ibcon#read 5, iclass 21, count 2 2006.285.23:08:35.47#ibcon#about to read 6, iclass 21, count 2 2006.285.23:08:35.47#ibcon#read 6, iclass 21, count 2 2006.285.23:08:35.47#ibcon#end of sib2, iclass 21, count 2 2006.285.23:08:35.47#ibcon#*after write, iclass 21, count 2 2006.285.23:08:35.47#ibcon#*before return 0, iclass 21, count 2 2006.285.23:08:35.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:08:35.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:08:35.47#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.23:08:35.47#ibcon#ireg 7 cls_cnt 0 2006.285.23:08:35.47#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:08:35.59#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:08:35.59#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:08:35.59#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:08:35.59#ibcon#first serial, iclass 21, count 0 2006.285.23:08:35.59#ibcon#enter sib2, iclass 21, count 0 2006.285.23:08:35.59#ibcon#flushed, iclass 21, count 0 2006.285.23:08:35.59#ibcon#about to write, iclass 21, count 0 2006.285.23:08:35.59#ibcon#wrote, iclass 21, count 0 2006.285.23:08:35.59#ibcon#about to read 3, iclass 21, count 0 2006.285.23:08:35.61#ibcon#read 3, iclass 21, count 0 2006.285.23:08:35.61#ibcon#about to read 4, iclass 21, count 0 2006.285.23:08:35.61#ibcon#read 4, iclass 21, count 0 2006.285.23:08:35.61#ibcon#about to read 5, iclass 21, count 0 2006.285.23:08:35.61#ibcon#read 5, iclass 21, count 0 2006.285.23:08:35.61#ibcon#about to read 6, iclass 21, count 0 2006.285.23:08:35.61#ibcon#read 6, iclass 21, count 0 2006.285.23:08:35.61#ibcon#end of sib2, iclass 21, count 0 2006.285.23:08:35.61#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:08:35.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:08:35.61#ibcon#[27=USB\r\n] 2006.285.23:08:35.61#ibcon#*before write, iclass 21, count 0 2006.285.23:08:35.61#ibcon#enter sib2, iclass 21, count 0 2006.285.23:08:35.61#ibcon#flushed, iclass 21, count 0 2006.285.23:08:35.61#ibcon#about to write, iclass 21, count 0 2006.285.23:08:35.61#ibcon#wrote, iclass 21, count 0 2006.285.23:08:35.61#ibcon#about to read 3, iclass 21, count 0 2006.285.23:08:35.64#ibcon#read 3, iclass 21, count 0 2006.285.23:08:35.64#ibcon#about to read 4, iclass 21, count 0 2006.285.23:08:35.64#ibcon#read 4, iclass 21, count 0 2006.285.23:08:35.64#ibcon#about to read 5, iclass 21, count 0 2006.285.23:08:35.64#ibcon#read 5, iclass 21, count 0 2006.285.23:08:35.64#ibcon#about to read 6, iclass 21, count 0 2006.285.23:08:35.64#ibcon#read 6, iclass 21, count 0 2006.285.23:08:35.64#ibcon#end of sib2, iclass 21, count 0 2006.285.23:08:35.64#ibcon#*after write, iclass 21, count 0 2006.285.23:08:35.64#ibcon#*before return 0, iclass 21, count 0 2006.285.23:08:35.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:08:35.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:08:35.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:08:35.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:08:35.64$vck44/vabw=wide 2006.285.23:08:35.64#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.23:08:35.64#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.23:08:35.64#ibcon#ireg 8 cls_cnt 0 2006.285.23:08:35.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:08:35.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:08:35.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:08:35.64#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:08:35.64#ibcon#first serial, iclass 23, count 0 2006.285.23:08:35.64#ibcon#enter sib2, iclass 23, count 0 2006.285.23:08:35.64#ibcon#flushed, iclass 23, count 0 2006.285.23:08:35.64#ibcon#about to write, iclass 23, count 0 2006.285.23:08:35.64#ibcon#wrote, iclass 23, count 0 2006.285.23:08:35.64#ibcon#about to read 3, iclass 23, count 0 2006.285.23:08:35.66#ibcon#read 3, iclass 23, count 0 2006.285.23:08:35.66#ibcon#about to read 4, iclass 23, count 0 2006.285.23:08:35.66#ibcon#read 4, iclass 23, count 0 2006.285.23:08:35.66#ibcon#about to read 5, iclass 23, count 0 2006.285.23:08:35.66#ibcon#read 5, iclass 23, count 0 2006.285.23:08:35.66#ibcon#about to read 6, iclass 23, count 0 2006.285.23:08:35.66#ibcon#read 6, iclass 23, count 0 2006.285.23:08:35.66#ibcon#end of sib2, iclass 23, count 0 2006.285.23:08:35.66#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:08:35.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:08:35.66#ibcon#[25=BW32\r\n] 2006.285.23:08:35.66#ibcon#*before write, iclass 23, count 0 2006.285.23:08:35.66#ibcon#enter sib2, iclass 23, count 0 2006.285.23:08:35.66#ibcon#flushed, iclass 23, count 0 2006.285.23:08:35.66#ibcon#about to write, iclass 23, count 0 2006.285.23:08:35.66#ibcon#wrote, iclass 23, count 0 2006.285.23:08:35.66#ibcon#about to read 3, iclass 23, count 0 2006.285.23:08:35.69#ibcon#read 3, iclass 23, count 0 2006.285.23:08:35.69#ibcon#about to read 4, iclass 23, count 0 2006.285.23:08:35.69#ibcon#read 4, iclass 23, count 0 2006.285.23:08:35.69#ibcon#about to read 5, iclass 23, count 0 2006.285.23:08:35.69#ibcon#read 5, iclass 23, count 0 2006.285.23:08:35.69#ibcon#about to read 6, iclass 23, count 0 2006.285.23:08:35.69#ibcon#read 6, iclass 23, count 0 2006.285.23:08:35.69#ibcon#end of sib2, iclass 23, count 0 2006.285.23:08:35.69#ibcon#*after write, iclass 23, count 0 2006.285.23:08:35.69#ibcon#*before return 0, iclass 23, count 0 2006.285.23:08:35.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:08:35.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:08:35.69#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:08:35.69#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:08:35.69$vck44/vbbw=wide 2006.285.23:08:35.69#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.23:08:35.69#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.23:08:35.69#ibcon#ireg 8 cls_cnt 0 2006.285.23:08:35.69#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:08:35.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:08:35.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:08:35.76#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:08:35.76#ibcon#first serial, iclass 25, count 0 2006.285.23:08:35.76#ibcon#enter sib2, iclass 25, count 0 2006.285.23:08:35.76#ibcon#flushed, iclass 25, count 0 2006.285.23:08:35.76#ibcon#about to write, iclass 25, count 0 2006.285.23:08:35.76#ibcon#wrote, iclass 25, count 0 2006.285.23:08:35.76#ibcon#about to read 3, iclass 25, count 0 2006.285.23:08:35.78#ibcon#read 3, iclass 25, count 0 2006.285.23:08:35.78#ibcon#about to read 4, iclass 25, count 0 2006.285.23:08:35.78#ibcon#read 4, iclass 25, count 0 2006.285.23:08:35.78#ibcon#about to read 5, iclass 25, count 0 2006.285.23:08:35.78#ibcon#read 5, iclass 25, count 0 2006.285.23:08:35.78#ibcon#about to read 6, iclass 25, count 0 2006.285.23:08:35.78#ibcon#read 6, iclass 25, count 0 2006.285.23:08:35.78#ibcon#end of sib2, iclass 25, count 0 2006.285.23:08:35.78#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:08:35.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:08:35.78#ibcon#[27=BW32\r\n] 2006.285.23:08:35.78#ibcon#*before write, iclass 25, count 0 2006.285.23:08:35.78#ibcon#enter sib2, iclass 25, count 0 2006.285.23:08:35.78#ibcon#flushed, iclass 25, count 0 2006.285.23:08:35.78#ibcon#about to write, iclass 25, count 0 2006.285.23:08:35.78#ibcon#wrote, iclass 25, count 0 2006.285.23:08:35.78#ibcon#about to read 3, iclass 25, count 0 2006.285.23:08:35.81#ibcon#read 3, iclass 25, count 0 2006.285.23:08:35.81#ibcon#about to read 4, iclass 25, count 0 2006.285.23:08:35.81#ibcon#read 4, iclass 25, count 0 2006.285.23:08:35.81#ibcon#about to read 5, iclass 25, count 0 2006.285.23:08:35.81#ibcon#read 5, iclass 25, count 0 2006.285.23:08:35.81#ibcon#about to read 6, iclass 25, count 0 2006.285.23:08:35.81#ibcon#read 6, iclass 25, count 0 2006.285.23:08:35.81#ibcon#end of sib2, iclass 25, count 0 2006.285.23:08:35.81#ibcon#*after write, iclass 25, count 0 2006.285.23:08:35.81#ibcon#*before return 0, iclass 25, count 0 2006.285.23:08:35.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:08:35.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:08:35.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:08:35.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:08:35.81$setupk4/ifdk4 2006.285.23:08:35.81$ifdk4/lo= 2006.285.23:08:35.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:08:35.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:08:35.82$ifdk4/patch= 2006.285.23:08:35.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:08:35.82$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:08:35.82$setupk4/!*+20s 2006.285.23:08:36.13#flagr#flagr/antenna,acquired 2006.285.23:08:39.60#abcon#<5=/03 3.2 7.5 18.79 891016.3\r\n> 2006.285.23:08:39.62#abcon#{5=INTERFACE CLEAR} 2006.285.23:08:39.68#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:08:49.77#abcon#<5=/03 3.2 7.5 18.80 891016.3\r\n> 2006.285.23:08:49.79#abcon#{5=INTERFACE CLEAR} 2006.285.23:08:49.85#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:08:50.40$setupk4/"tpicd 2006.285.23:08:50.40$setupk4/echo=off 2006.285.23:08:50.40$setupk4/xlog=off 2006.285.23:08:50.40:!2006.285.23:08:56 2006.285.23:08:56.00:preob 2006.285.23:08:56.13/onsource/TRACKING 2006.285.23:08:56.13:!2006.285.23:09:06 2006.285.23:09:06.00:"tape 2006.285.23:09:06.00:"st=record 2006.285.23:09:06.00:data_valid=on 2006.285.23:09:06.00:midob 2006.285.23:09:06.13/onsource/TRACKING 2006.285.23:09:06.14/wx/18.80,1016.4,90 2006.285.23:09:06.22/cable/+6.5093E-03 2006.285.23:09:07.31/va/01,07,usb,yes,35,38 2006.285.23:09:07.31/va/02,06,usb,yes,35,35 2006.285.23:09:07.31/va/03,07,usb,yes,34,36 2006.285.23:09:07.31/va/04,06,usb,yes,36,38 2006.285.23:09:07.31/va/05,03,usb,yes,35,36 2006.285.23:09:07.31/va/06,04,usb,yes,32,31 2006.285.23:09:07.31/va/07,04,usb,yes,32,33 2006.285.23:09:07.31/va/08,03,usb,yes,33,40 2006.285.23:09:07.54/valo/01,524.99,yes,locked 2006.285.23:09:07.54/valo/02,534.99,yes,locked 2006.285.23:09:07.54/valo/03,564.99,yes,locked 2006.285.23:09:07.54/valo/04,624.99,yes,locked 2006.285.23:09:07.54/valo/05,734.99,yes,locked 2006.285.23:09:07.54/valo/06,814.99,yes,locked 2006.285.23:09:07.54/valo/07,864.99,yes,locked 2006.285.23:09:07.54/valo/08,884.99,yes,locked 2006.285.23:09:08.63/vb/01,04,usb,yes,32,30 2006.285.23:09:08.63/vb/02,05,usb,yes,30,30 2006.285.23:09:08.63/vb/03,04,usb,yes,31,34 2006.285.23:09:08.63/vb/04,05,usb,yes,31,30 2006.285.23:09:08.63/vb/05,04,usb,yes,28,30 2006.285.23:09:08.63/vb/06,03,usb,yes,40,35 2006.285.23:09:08.63/vb/07,04,usb,yes,32,32 2006.285.23:09:08.63/vb/08,04,usb,yes,29,33 2006.285.23:09:08.86/vblo/01,629.99,yes,locked 2006.285.23:09:08.86/vblo/02,634.99,yes,locked 2006.285.23:09:08.86/vblo/03,649.99,yes,locked 2006.285.23:09:08.86/vblo/04,679.99,yes,locked 2006.285.23:09:08.86/vblo/05,709.99,yes,locked 2006.285.23:09:08.86/vblo/06,719.99,yes,locked 2006.285.23:09:08.86/vblo/07,734.99,yes,locked 2006.285.23:09:08.86/vblo/08,744.99,yes,locked 2006.285.23:09:09.01/vabw/8 2006.285.23:09:09.16/vbbw/8 2006.285.23:09:09.25/xfe/off,on,12.0 2006.285.23:09:09.64/ifatt/23,28,28,28 2006.285.23:09:10.07/fmout-gps/S +2.61E-07 2006.285.23:09:10.09:!2006.285.23:10:16 2006.285.23:10:16.00:data_valid=off 2006.285.23:10:16.00:"et 2006.285.23:10:16.00:!+3s 2006.285.23:10:19.01:"tape 2006.285.23:10:19.01:postob 2006.285.23:10:19.23/cable/+6.5097E-03 2006.285.23:10:19.23/wx/18.85,1016.4,89 2006.285.23:10:20.07/fmout-gps/S +2.60E-07 2006.285.23:10:20.07:scan_name=285-2323,jd0610,50 2006.285.23:10:20.07:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.285.23:10:21.14#flagr#flagr/antenna,new-source 2006.285.23:10:21.14:checkk5 2006.285.23:10:21.51/chk_autoobs//k5ts1/ autoobs is running! 2006.285.23:10:21.91/chk_autoobs//k5ts2/ autoobs is running! 2006.285.23:10:22.28/chk_autoobs//k5ts3/ autoobs is running! 2006.285.23:10:22.87/chk_autoobs//k5ts4/ autoobs is running! 2006.285.23:10:23.24/chk_obsdata//k5ts1/T2852309??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.23:10:23.57/chk_obsdata//k5ts2/T2852309??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.23:10:23.93/chk_obsdata//k5ts3/T2852309??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.23:10:24.31/chk_obsdata//k5ts4/T2852309??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.23:10:25.08/k5log//k5ts1_log_newline 2006.285.23:10:26.33/k5log//k5ts2_log_newline 2006.285.23:10:27.35/k5log//k5ts3_log_newline 2006.285.23:10:28.11/k5log//k5ts4_log_newline 2006.285.23:10:28.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.23:10:28.13:setupk4=1 2006.285.23:10:28.14$setupk4/echo=on 2006.285.23:10:28.14$setupk4/pcalon 2006.285.23:10:28.14$pcalon/"no phase cal control is implemented here 2006.285.23:10:28.14$setupk4/"tpicd=stop 2006.285.23:10:28.14$setupk4/"rec=synch_on 2006.285.23:10:28.14$setupk4/"rec_mode=128 2006.285.23:10:28.14$setupk4/!* 2006.285.23:10:28.14$setupk4/recpk4 2006.285.23:10:28.14$recpk4/recpatch= 2006.285.23:10:28.14$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.23:10:28.14$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.23:10:28.14$setupk4/vck44 2006.285.23:10:28.14$vck44/valo=1,524.99 2006.285.23:10:28.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.23:10:28.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.23:10:28.14#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:28.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:10:28.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:10:28.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:10:28.14#ibcon#enter wrdev, iclass 38, count 0 2006.285.23:10:28.14#ibcon#first serial, iclass 38, count 0 2006.285.23:10:28.14#ibcon#enter sib2, iclass 38, count 0 2006.285.23:10:28.14#ibcon#flushed, iclass 38, count 0 2006.285.23:10:28.14#ibcon#about to write, iclass 38, count 0 2006.285.23:10:28.14#ibcon#wrote, iclass 38, count 0 2006.285.23:10:28.14#ibcon#about to read 3, iclass 38, count 0 2006.285.23:10:28.15#ibcon#read 3, iclass 38, count 0 2006.285.23:10:28.15#ibcon#about to read 4, iclass 38, count 0 2006.285.23:10:28.15#ibcon#read 4, iclass 38, count 0 2006.285.23:10:28.15#ibcon#about to read 5, iclass 38, count 0 2006.285.23:10:28.15#ibcon#read 5, iclass 38, count 0 2006.285.23:10:28.15#ibcon#about to read 6, iclass 38, count 0 2006.285.23:10:28.15#ibcon#read 6, iclass 38, count 0 2006.285.23:10:28.15#ibcon#end of sib2, iclass 38, count 0 2006.285.23:10:28.15#ibcon#*mode == 0, iclass 38, count 0 2006.285.23:10:28.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.23:10:28.15#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.23:10:28.15#ibcon#*before write, iclass 38, count 0 2006.285.23:10:28.15#ibcon#enter sib2, iclass 38, count 0 2006.285.23:10:28.15#ibcon#flushed, iclass 38, count 0 2006.285.23:10:28.15#ibcon#about to write, iclass 38, count 0 2006.285.23:10:28.15#ibcon#wrote, iclass 38, count 0 2006.285.23:10:28.15#ibcon#about to read 3, iclass 38, count 0 2006.285.23:10:28.20#ibcon#read 3, iclass 38, count 0 2006.285.23:10:28.20#ibcon#about to read 4, iclass 38, count 0 2006.285.23:10:28.20#ibcon#read 4, iclass 38, count 0 2006.285.23:10:28.20#ibcon#about to read 5, iclass 38, count 0 2006.285.23:10:28.20#ibcon#read 5, iclass 38, count 0 2006.285.23:10:28.20#ibcon#about to read 6, iclass 38, count 0 2006.285.23:10:28.20#ibcon#read 6, iclass 38, count 0 2006.285.23:10:28.20#ibcon#end of sib2, iclass 38, count 0 2006.285.23:10:28.20#ibcon#*after write, iclass 38, count 0 2006.285.23:10:28.20#ibcon#*before return 0, iclass 38, count 0 2006.285.23:10:28.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:10:28.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:10:28.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.23:10:28.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.23:10:28.20$vck44/va=1,7 2006.285.23:10:28.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.23:10:28.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.23:10:28.20#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:28.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:10:28.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:10:28.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:10:28.20#ibcon#enter wrdev, iclass 40, count 2 2006.285.23:10:28.20#ibcon#first serial, iclass 40, count 2 2006.285.23:10:28.20#ibcon#enter sib2, iclass 40, count 2 2006.285.23:10:28.20#ibcon#flushed, iclass 40, count 2 2006.285.23:10:28.20#ibcon#about to write, iclass 40, count 2 2006.285.23:10:28.20#ibcon#wrote, iclass 40, count 2 2006.285.23:10:28.20#ibcon#about to read 3, iclass 40, count 2 2006.285.23:10:28.22#ibcon#read 3, iclass 40, count 2 2006.285.23:10:28.22#ibcon#about to read 4, iclass 40, count 2 2006.285.23:10:28.22#ibcon#read 4, iclass 40, count 2 2006.285.23:10:28.22#ibcon#about to read 5, iclass 40, count 2 2006.285.23:10:28.22#ibcon#read 5, iclass 40, count 2 2006.285.23:10:28.22#ibcon#about to read 6, iclass 40, count 2 2006.285.23:10:28.22#ibcon#read 6, iclass 40, count 2 2006.285.23:10:28.22#ibcon#end of sib2, iclass 40, count 2 2006.285.23:10:28.22#ibcon#*mode == 0, iclass 40, count 2 2006.285.23:10:28.22#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.23:10:28.22#ibcon#[25=AT01-07\r\n] 2006.285.23:10:28.22#ibcon#*before write, iclass 40, count 2 2006.285.23:10:28.22#ibcon#enter sib2, iclass 40, count 2 2006.285.23:10:28.22#ibcon#flushed, iclass 40, count 2 2006.285.23:10:28.22#ibcon#about to write, iclass 40, count 2 2006.285.23:10:28.22#ibcon#wrote, iclass 40, count 2 2006.285.23:10:28.22#ibcon#about to read 3, iclass 40, count 2 2006.285.23:10:28.25#ibcon#read 3, iclass 40, count 2 2006.285.23:10:28.25#ibcon#about to read 4, iclass 40, count 2 2006.285.23:10:28.25#ibcon#read 4, iclass 40, count 2 2006.285.23:10:28.25#ibcon#about to read 5, iclass 40, count 2 2006.285.23:10:28.25#ibcon#read 5, iclass 40, count 2 2006.285.23:10:28.25#ibcon#about to read 6, iclass 40, count 2 2006.285.23:10:28.25#ibcon#read 6, iclass 40, count 2 2006.285.23:10:28.25#ibcon#end of sib2, iclass 40, count 2 2006.285.23:10:28.25#ibcon#*after write, iclass 40, count 2 2006.285.23:10:28.25#ibcon#*before return 0, iclass 40, count 2 2006.285.23:10:28.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:10:28.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:10:28.25#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.23:10:28.25#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:28.25#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:10:28.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:10:28.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:10:28.38#ibcon#enter wrdev, iclass 40, count 0 2006.285.23:10:28.38#ibcon#first serial, iclass 40, count 0 2006.285.23:10:28.38#ibcon#enter sib2, iclass 40, count 0 2006.285.23:10:28.38#ibcon#flushed, iclass 40, count 0 2006.285.23:10:28.38#ibcon#about to write, iclass 40, count 0 2006.285.23:10:28.38#ibcon#wrote, iclass 40, count 0 2006.285.23:10:28.38#ibcon#about to read 3, iclass 40, count 0 2006.285.23:10:28.40#ibcon#read 3, iclass 40, count 0 2006.285.23:10:28.40#ibcon#about to read 4, iclass 40, count 0 2006.285.23:10:28.40#ibcon#read 4, iclass 40, count 0 2006.285.23:10:28.40#ibcon#about to read 5, iclass 40, count 0 2006.285.23:10:28.40#ibcon#read 5, iclass 40, count 0 2006.285.23:10:28.40#ibcon#about to read 6, iclass 40, count 0 2006.285.23:10:28.40#ibcon#read 6, iclass 40, count 0 2006.285.23:10:28.40#ibcon#end of sib2, iclass 40, count 0 2006.285.23:10:28.40#ibcon#*mode == 0, iclass 40, count 0 2006.285.23:10:28.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.23:10:28.40#ibcon#[25=USB\r\n] 2006.285.23:10:28.40#ibcon#*before write, iclass 40, count 0 2006.285.23:10:28.40#ibcon#enter sib2, iclass 40, count 0 2006.285.23:10:28.40#ibcon#flushed, iclass 40, count 0 2006.285.23:10:28.40#ibcon#about to write, iclass 40, count 0 2006.285.23:10:28.40#ibcon#wrote, iclass 40, count 0 2006.285.23:10:28.40#ibcon#about to read 3, iclass 40, count 0 2006.285.23:10:28.43#ibcon#read 3, iclass 40, count 0 2006.285.23:10:28.43#ibcon#about to read 4, iclass 40, count 0 2006.285.23:10:28.43#ibcon#read 4, iclass 40, count 0 2006.285.23:10:28.43#ibcon#about to read 5, iclass 40, count 0 2006.285.23:10:28.43#ibcon#read 5, iclass 40, count 0 2006.285.23:10:28.43#ibcon#about to read 6, iclass 40, count 0 2006.285.23:10:28.43#ibcon#read 6, iclass 40, count 0 2006.285.23:10:28.43#ibcon#end of sib2, iclass 40, count 0 2006.285.23:10:28.43#ibcon#*after write, iclass 40, count 0 2006.285.23:10:28.43#ibcon#*before return 0, iclass 40, count 0 2006.285.23:10:28.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:10:28.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:10:28.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.23:10:28.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.23:10:28.43$vck44/valo=2,534.99 2006.285.23:10:28.43#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.23:10:28.43#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.23:10:28.43#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:28.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:10:28.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:10:28.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:10:28.43#ibcon#enter wrdev, iclass 4, count 0 2006.285.23:10:28.43#ibcon#first serial, iclass 4, count 0 2006.285.23:10:28.43#ibcon#enter sib2, iclass 4, count 0 2006.285.23:10:28.43#ibcon#flushed, iclass 4, count 0 2006.285.23:10:28.43#ibcon#about to write, iclass 4, count 0 2006.285.23:10:28.43#ibcon#wrote, iclass 4, count 0 2006.285.23:10:28.43#ibcon#about to read 3, iclass 4, count 0 2006.285.23:10:28.45#ibcon#read 3, iclass 4, count 0 2006.285.23:10:28.45#ibcon#about to read 4, iclass 4, count 0 2006.285.23:10:28.45#ibcon#read 4, iclass 4, count 0 2006.285.23:10:28.45#ibcon#about to read 5, iclass 4, count 0 2006.285.23:10:28.45#ibcon#read 5, iclass 4, count 0 2006.285.23:10:28.45#ibcon#about to read 6, iclass 4, count 0 2006.285.23:10:28.45#ibcon#read 6, iclass 4, count 0 2006.285.23:10:28.45#ibcon#end of sib2, iclass 4, count 0 2006.285.23:10:28.45#ibcon#*mode == 0, iclass 4, count 0 2006.285.23:10:28.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.23:10:28.45#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.23:10:28.45#ibcon#*before write, iclass 4, count 0 2006.285.23:10:28.45#ibcon#enter sib2, iclass 4, count 0 2006.285.23:10:28.45#ibcon#flushed, iclass 4, count 0 2006.285.23:10:28.45#ibcon#about to write, iclass 4, count 0 2006.285.23:10:28.45#ibcon#wrote, iclass 4, count 0 2006.285.23:10:28.45#ibcon#about to read 3, iclass 4, count 0 2006.285.23:10:28.49#ibcon#read 3, iclass 4, count 0 2006.285.23:10:28.49#ibcon#about to read 4, iclass 4, count 0 2006.285.23:10:28.49#ibcon#read 4, iclass 4, count 0 2006.285.23:10:28.49#ibcon#about to read 5, iclass 4, count 0 2006.285.23:10:28.49#ibcon#read 5, iclass 4, count 0 2006.285.23:10:28.49#ibcon#about to read 6, iclass 4, count 0 2006.285.23:10:28.49#ibcon#read 6, iclass 4, count 0 2006.285.23:10:28.49#ibcon#end of sib2, iclass 4, count 0 2006.285.23:10:28.49#ibcon#*after write, iclass 4, count 0 2006.285.23:10:28.49#ibcon#*before return 0, iclass 4, count 0 2006.285.23:10:28.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:10:28.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:10:28.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.23:10:28.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.23:10:28.49$vck44/va=2,6 2006.285.23:10:28.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.23:10:28.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.23:10:28.49#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:28.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.23:10:28.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.23:10:28.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.23:10:28.55#ibcon#enter wrdev, iclass 6, count 2 2006.285.23:10:28.55#ibcon#first serial, iclass 6, count 2 2006.285.23:10:28.55#ibcon#enter sib2, iclass 6, count 2 2006.285.23:10:28.55#ibcon#flushed, iclass 6, count 2 2006.285.23:10:28.55#ibcon#about to write, iclass 6, count 2 2006.285.23:10:28.55#ibcon#wrote, iclass 6, count 2 2006.285.23:10:28.55#ibcon#about to read 3, iclass 6, count 2 2006.285.23:10:28.57#ibcon#read 3, iclass 6, count 2 2006.285.23:10:28.57#ibcon#about to read 4, iclass 6, count 2 2006.285.23:10:28.57#ibcon#read 4, iclass 6, count 2 2006.285.23:10:28.57#ibcon#about to read 5, iclass 6, count 2 2006.285.23:10:28.57#ibcon#read 5, iclass 6, count 2 2006.285.23:10:28.57#ibcon#about to read 6, iclass 6, count 2 2006.285.23:10:28.57#ibcon#read 6, iclass 6, count 2 2006.285.23:10:28.57#ibcon#end of sib2, iclass 6, count 2 2006.285.23:10:28.57#ibcon#*mode == 0, iclass 6, count 2 2006.285.23:10:28.57#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.23:10:28.57#ibcon#[25=AT02-06\r\n] 2006.285.23:10:28.57#ibcon#*before write, iclass 6, count 2 2006.285.23:10:28.57#ibcon#enter sib2, iclass 6, count 2 2006.285.23:10:28.57#ibcon#flushed, iclass 6, count 2 2006.285.23:10:28.57#ibcon#about to write, iclass 6, count 2 2006.285.23:10:28.57#ibcon#wrote, iclass 6, count 2 2006.285.23:10:28.57#ibcon#about to read 3, iclass 6, count 2 2006.285.23:10:28.60#ibcon#read 3, iclass 6, count 2 2006.285.23:10:28.60#ibcon#about to read 4, iclass 6, count 2 2006.285.23:10:28.60#ibcon#read 4, iclass 6, count 2 2006.285.23:10:28.60#ibcon#about to read 5, iclass 6, count 2 2006.285.23:10:28.60#ibcon#read 5, iclass 6, count 2 2006.285.23:10:28.60#ibcon#about to read 6, iclass 6, count 2 2006.285.23:10:28.60#ibcon#read 6, iclass 6, count 2 2006.285.23:10:28.60#ibcon#end of sib2, iclass 6, count 2 2006.285.23:10:28.60#ibcon#*after write, iclass 6, count 2 2006.285.23:10:28.60#ibcon#*before return 0, iclass 6, count 2 2006.285.23:10:28.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.23:10:28.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.23:10:28.60#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.23:10:28.60#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:28.60#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.23:10:28.72#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.23:10:28.72#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.23:10:28.72#ibcon#enter wrdev, iclass 6, count 0 2006.285.23:10:28.72#ibcon#first serial, iclass 6, count 0 2006.285.23:10:28.72#ibcon#enter sib2, iclass 6, count 0 2006.285.23:10:28.72#ibcon#flushed, iclass 6, count 0 2006.285.23:10:28.72#ibcon#about to write, iclass 6, count 0 2006.285.23:10:28.72#ibcon#wrote, iclass 6, count 0 2006.285.23:10:28.72#ibcon#about to read 3, iclass 6, count 0 2006.285.23:10:28.74#ibcon#read 3, iclass 6, count 0 2006.285.23:10:28.74#ibcon#about to read 4, iclass 6, count 0 2006.285.23:10:28.74#ibcon#read 4, iclass 6, count 0 2006.285.23:10:28.74#ibcon#about to read 5, iclass 6, count 0 2006.285.23:10:28.74#ibcon#read 5, iclass 6, count 0 2006.285.23:10:28.74#ibcon#about to read 6, iclass 6, count 0 2006.285.23:10:28.74#ibcon#read 6, iclass 6, count 0 2006.285.23:10:28.74#ibcon#end of sib2, iclass 6, count 0 2006.285.23:10:28.74#ibcon#*mode == 0, iclass 6, count 0 2006.285.23:10:28.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.23:10:28.74#ibcon#[25=USB\r\n] 2006.285.23:10:28.74#ibcon#*before write, iclass 6, count 0 2006.285.23:10:28.74#ibcon#enter sib2, iclass 6, count 0 2006.285.23:10:28.74#ibcon#flushed, iclass 6, count 0 2006.285.23:10:28.74#ibcon#about to write, iclass 6, count 0 2006.285.23:10:28.74#ibcon#wrote, iclass 6, count 0 2006.285.23:10:28.74#ibcon#about to read 3, iclass 6, count 0 2006.285.23:10:28.77#ibcon#read 3, iclass 6, count 0 2006.285.23:10:28.77#ibcon#about to read 4, iclass 6, count 0 2006.285.23:10:28.77#ibcon#read 4, iclass 6, count 0 2006.285.23:10:28.77#ibcon#about to read 5, iclass 6, count 0 2006.285.23:10:28.77#ibcon#read 5, iclass 6, count 0 2006.285.23:10:28.77#ibcon#about to read 6, iclass 6, count 0 2006.285.23:10:28.77#ibcon#read 6, iclass 6, count 0 2006.285.23:10:28.77#ibcon#end of sib2, iclass 6, count 0 2006.285.23:10:28.77#ibcon#*after write, iclass 6, count 0 2006.285.23:10:28.77#ibcon#*before return 0, iclass 6, count 0 2006.285.23:10:28.77#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.23:10:28.77#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.23:10:28.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.23:10:28.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.23:10:28.77$vck44/valo=3,564.99 2006.285.23:10:28.77#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.23:10:28.77#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.23:10:28.77#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:28.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.23:10:28.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.23:10:28.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.23:10:28.77#ibcon#enter wrdev, iclass 10, count 0 2006.285.23:10:28.77#ibcon#first serial, iclass 10, count 0 2006.285.23:10:28.77#ibcon#enter sib2, iclass 10, count 0 2006.285.23:10:28.77#ibcon#flushed, iclass 10, count 0 2006.285.23:10:28.77#ibcon#about to write, iclass 10, count 0 2006.285.23:10:28.77#ibcon#wrote, iclass 10, count 0 2006.285.23:10:28.77#ibcon#about to read 3, iclass 10, count 0 2006.285.23:10:28.79#ibcon#read 3, iclass 10, count 0 2006.285.23:10:28.79#ibcon#about to read 4, iclass 10, count 0 2006.285.23:10:28.79#ibcon#read 4, iclass 10, count 0 2006.285.23:10:28.79#ibcon#about to read 5, iclass 10, count 0 2006.285.23:10:28.79#ibcon#read 5, iclass 10, count 0 2006.285.23:10:28.79#ibcon#about to read 6, iclass 10, count 0 2006.285.23:10:28.79#ibcon#read 6, iclass 10, count 0 2006.285.23:10:28.79#ibcon#end of sib2, iclass 10, count 0 2006.285.23:10:28.79#ibcon#*mode == 0, iclass 10, count 0 2006.285.23:10:28.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.23:10:28.79#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.23:10:28.79#ibcon#*before write, iclass 10, count 0 2006.285.23:10:28.79#ibcon#enter sib2, iclass 10, count 0 2006.285.23:10:28.79#ibcon#flushed, iclass 10, count 0 2006.285.23:10:28.79#ibcon#about to write, iclass 10, count 0 2006.285.23:10:28.79#ibcon#wrote, iclass 10, count 0 2006.285.23:10:28.79#ibcon#about to read 3, iclass 10, count 0 2006.285.23:10:28.83#ibcon#read 3, iclass 10, count 0 2006.285.23:10:28.83#ibcon#about to read 4, iclass 10, count 0 2006.285.23:10:28.83#ibcon#read 4, iclass 10, count 0 2006.285.23:10:28.83#ibcon#about to read 5, iclass 10, count 0 2006.285.23:10:28.83#ibcon#read 5, iclass 10, count 0 2006.285.23:10:28.83#ibcon#about to read 6, iclass 10, count 0 2006.285.23:10:28.83#ibcon#read 6, iclass 10, count 0 2006.285.23:10:28.83#ibcon#end of sib2, iclass 10, count 0 2006.285.23:10:28.83#ibcon#*after write, iclass 10, count 0 2006.285.23:10:28.83#ibcon#*before return 0, iclass 10, count 0 2006.285.23:10:28.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.23:10:28.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.23:10:28.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.23:10:28.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.23:10:28.83$vck44/va=3,7 2006.285.23:10:28.83#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.23:10:28.83#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.23:10:28.83#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:28.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.23:10:28.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.23:10:28.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.23:10:28.89#ibcon#enter wrdev, iclass 12, count 2 2006.285.23:10:28.89#ibcon#first serial, iclass 12, count 2 2006.285.23:10:28.89#ibcon#enter sib2, iclass 12, count 2 2006.285.23:10:28.89#ibcon#flushed, iclass 12, count 2 2006.285.23:10:28.89#ibcon#about to write, iclass 12, count 2 2006.285.23:10:28.89#ibcon#wrote, iclass 12, count 2 2006.285.23:10:28.89#ibcon#about to read 3, iclass 12, count 2 2006.285.23:10:28.91#ibcon#read 3, iclass 12, count 2 2006.285.23:10:28.91#ibcon#about to read 4, iclass 12, count 2 2006.285.23:10:28.91#ibcon#read 4, iclass 12, count 2 2006.285.23:10:28.91#ibcon#about to read 5, iclass 12, count 2 2006.285.23:10:28.91#ibcon#read 5, iclass 12, count 2 2006.285.23:10:28.91#ibcon#about to read 6, iclass 12, count 2 2006.285.23:10:28.91#ibcon#read 6, iclass 12, count 2 2006.285.23:10:28.91#ibcon#end of sib2, iclass 12, count 2 2006.285.23:10:28.91#ibcon#*mode == 0, iclass 12, count 2 2006.285.23:10:28.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.23:10:28.91#ibcon#[25=AT03-07\r\n] 2006.285.23:10:28.91#ibcon#*before write, iclass 12, count 2 2006.285.23:10:28.91#ibcon#enter sib2, iclass 12, count 2 2006.285.23:10:28.91#ibcon#flushed, iclass 12, count 2 2006.285.23:10:28.91#ibcon#about to write, iclass 12, count 2 2006.285.23:10:28.91#ibcon#wrote, iclass 12, count 2 2006.285.23:10:28.91#ibcon#about to read 3, iclass 12, count 2 2006.285.23:10:28.94#ibcon#read 3, iclass 12, count 2 2006.285.23:10:28.94#ibcon#about to read 4, iclass 12, count 2 2006.285.23:10:28.94#ibcon#read 4, iclass 12, count 2 2006.285.23:10:28.94#ibcon#about to read 5, iclass 12, count 2 2006.285.23:10:28.94#ibcon#read 5, iclass 12, count 2 2006.285.23:10:28.94#ibcon#about to read 6, iclass 12, count 2 2006.285.23:10:28.94#ibcon#read 6, iclass 12, count 2 2006.285.23:10:28.94#ibcon#end of sib2, iclass 12, count 2 2006.285.23:10:28.94#ibcon#*after write, iclass 12, count 2 2006.285.23:10:28.94#ibcon#*before return 0, iclass 12, count 2 2006.285.23:10:28.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.23:10:28.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.23:10:28.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.23:10:28.94#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:28.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.23:10:29.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.23:10:29.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.23:10:29.06#ibcon#enter wrdev, iclass 12, count 0 2006.285.23:10:29.06#ibcon#first serial, iclass 12, count 0 2006.285.23:10:29.06#ibcon#enter sib2, iclass 12, count 0 2006.285.23:10:29.06#ibcon#flushed, iclass 12, count 0 2006.285.23:10:29.06#ibcon#about to write, iclass 12, count 0 2006.285.23:10:29.06#ibcon#wrote, iclass 12, count 0 2006.285.23:10:29.06#ibcon#about to read 3, iclass 12, count 0 2006.285.23:10:29.08#ibcon#read 3, iclass 12, count 0 2006.285.23:10:29.08#ibcon#about to read 4, iclass 12, count 0 2006.285.23:10:29.08#ibcon#read 4, iclass 12, count 0 2006.285.23:10:29.08#ibcon#about to read 5, iclass 12, count 0 2006.285.23:10:29.08#ibcon#read 5, iclass 12, count 0 2006.285.23:10:29.08#ibcon#about to read 6, iclass 12, count 0 2006.285.23:10:29.08#ibcon#read 6, iclass 12, count 0 2006.285.23:10:29.08#ibcon#end of sib2, iclass 12, count 0 2006.285.23:10:29.08#ibcon#*mode == 0, iclass 12, count 0 2006.285.23:10:29.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.23:10:29.08#ibcon#[25=USB\r\n] 2006.285.23:10:29.08#ibcon#*before write, iclass 12, count 0 2006.285.23:10:29.08#ibcon#enter sib2, iclass 12, count 0 2006.285.23:10:29.08#ibcon#flushed, iclass 12, count 0 2006.285.23:10:29.08#ibcon#about to write, iclass 12, count 0 2006.285.23:10:29.08#ibcon#wrote, iclass 12, count 0 2006.285.23:10:29.08#ibcon#about to read 3, iclass 12, count 0 2006.285.23:10:29.11#ibcon#read 3, iclass 12, count 0 2006.285.23:10:29.11#ibcon#about to read 4, iclass 12, count 0 2006.285.23:10:29.11#ibcon#read 4, iclass 12, count 0 2006.285.23:10:29.11#ibcon#about to read 5, iclass 12, count 0 2006.285.23:10:29.11#ibcon#read 5, iclass 12, count 0 2006.285.23:10:29.11#ibcon#about to read 6, iclass 12, count 0 2006.285.23:10:29.11#ibcon#read 6, iclass 12, count 0 2006.285.23:10:29.11#ibcon#end of sib2, iclass 12, count 0 2006.285.23:10:29.11#ibcon#*after write, iclass 12, count 0 2006.285.23:10:29.11#ibcon#*before return 0, iclass 12, count 0 2006.285.23:10:29.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.23:10:29.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.23:10:29.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.23:10:29.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.23:10:29.11$vck44/valo=4,624.99 2006.285.23:10:29.11#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.23:10:29.11#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.23:10:29.11#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:29.11#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:10:29.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:10:29.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:10:29.11#ibcon#enter wrdev, iclass 14, count 0 2006.285.23:10:29.11#ibcon#first serial, iclass 14, count 0 2006.285.23:10:29.11#ibcon#enter sib2, iclass 14, count 0 2006.285.23:10:29.11#ibcon#flushed, iclass 14, count 0 2006.285.23:10:29.11#ibcon#about to write, iclass 14, count 0 2006.285.23:10:29.11#ibcon#wrote, iclass 14, count 0 2006.285.23:10:29.11#ibcon#about to read 3, iclass 14, count 0 2006.285.23:10:29.13#ibcon#read 3, iclass 14, count 0 2006.285.23:10:29.13#ibcon#about to read 4, iclass 14, count 0 2006.285.23:10:29.13#ibcon#read 4, iclass 14, count 0 2006.285.23:10:29.13#ibcon#about to read 5, iclass 14, count 0 2006.285.23:10:29.13#ibcon#read 5, iclass 14, count 0 2006.285.23:10:29.13#ibcon#about to read 6, iclass 14, count 0 2006.285.23:10:29.13#ibcon#read 6, iclass 14, count 0 2006.285.23:10:29.13#ibcon#end of sib2, iclass 14, count 0 2006.285.23:10:29.13#ibcon#*mode == 0, iclass 14, count 0 2006.285.23:10:29.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.23:10:29.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.23:10:29.13#ibcon#*before write, iclass 14, count 0 2006.285.23:10:29.13#ibcon#enter sib2, iclass 14, count 0 2006.285.23:10:29.13#ibcon#flushed, iclass 14, count 0 2006.285.23:10:29.13#ibcon#about to write, iclass 14, count 0 2006.285.23:10:29.13#ibcon#wrote, iclass 14, count 0 2006.285.23:10:29.13#ibcon#about to read 3, iclass 14, count 0 2006.285.23:10:29.17#ibcon#read 3, iclass 14, count 0 2006.285.23:10:29.17#ibcon#about to read 4, iclass 14, count 0 2006.285.23:10:29.17#ibcon#read 4, iclass 14, count 0 2006.285.23:10:29.17#ibcon#about to read 5, iclass 14, count 0 2006.285.23:10:29.17#ibcon#read 5, iclass 14, count 0 2006.285.23:10:29.17#ibcon#about to read 6, iclass 14, count 0 2006.285.23:10:29.17#ibcon#read 6, iclass 14, count 0 2006.285.23:10:29.17#ibcon#end of sib2, iclass 14, count 0 2006.285.23:10:29.17#ibcon#*after write, iclass 14, count 0 2006.285.23:10:29.17#ibcon#*before return 0, iclass 14, count 0 2006.285.23:10:29.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:10:29.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:10:29.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.23:10:29.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.23:10:29.17$vck44/va=4,6 2006.285.23:10:29.17#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.23:10:29.17#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.23:10:29.17#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:29.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:10:29.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:10:29.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:10:29.23#ibcon#enter wrdev, iclass 16, count 2 2006.285.23:10:29.23#ibcon#first serial, iclass 16, count 2 2006.285.23:10:29.23#ibcon#enter sib2, iclass 16, count 2 2006.285.23:10:29.23#ibcon#flushed, iclass 16, count 2 2006.285.23:10:29.23#ibcon#about to write, iclass 16, count 2 2006.285.23:10:29.23#ibcon#wrote, iclass 16, count 2 2006.285.23:10:29.23#ibcon#about to read 3, iclass 16, count 2 2006.285.23:10:29.25#ibcon#read 3, iclass 16, count 2 2006.285.23:10:29.25#ibcon#about to read 4, iclass 16, count 2 2006.285.23:10:29.25#ibcon#read 4, iclass 16, count 2 2006.285.23:10:29.25#ibcon#about to read 5, iclass 16, count 2 2006.285.23:10:29.25#ibcon#read 5, iclass 16, count 2 2006.285.23:10:29.25#ibcon#about to read 6, iclass 16, count 2 2006.285.23:10:29.25#ibcon#read 6, iclass 16, count 2 2006.285.23:10:29.25#ibcon#end of sib2, iclass 16, count 2 2006.285.23:10:29.25#ibcon#*mode == 0, iclass 16, count 2 2006.285.23:10:29.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.23:10:29.25#ibcon#[25=AT04-06\r\n] 2006.285.23:10:29.25#ibcon#*before write, iclass 16, count 2 2006.285.23:10:29.25#ibcon#enter sib2, iclass 16, count 2 2006.285.23:10:29.25#ibcon#flushed, iclass 16, count 2 2006.285.23:10:29.25#ibcon#about to write, iclass 16, count 2 2006.285.23:10:29.25#ibcon#wrote, iclass 16, count 2 2006.285.23:10:29.25#ibcon#about to read 3, iclass 16, count 2 2006.285.23:10:29.28#ibcon#read 3, iclass 16, count 2 2006.285.23:10:29.28#ibcon#about to read 4, iclass 16, count 2 2006.285.23:10:29.28#ibcon#read 4, iclass 16, count 2 2006.285.23:10:29.28#ibcon#about to read 5, iclass 16, count 2 2006.285.23:10:29.28#ibcon#read 5, iclass 16, count 2 2006.285.23:10:29.28#ibcon#about to read 6, iclass 16, count 2 2006.285.23:10:29.28#ibcon#read 6, iclass 16, count 2 2006.285.23:10:29.28#ibcon#end of sib2, iclass 16, count 2 2006.285.23:10:29.28#ibcon#*after write, iclass 16, count 2 2006.285.23:10:29.28#ibcon#*before return 0, iclass 16, count 2 2006.285.23:10:29.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:10:29.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:10:29.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.23:10:29.28#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:29.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:10:29.40#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:10:29.40#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:10:29.40#ibcon#enter wrdev, iclass 16, count 0 2006.285.23:10:29.40#ibcon#first serial, iclass 16, count 0 2006.285.23:10:29.40#ibcon#enter sib2, iclass 16, count 0 2006.285.23:10:29.40#ibcon#flushed, iclass 16, count 0 2006.285.23:10:29.40#ibcon#about to write, iclass 16, count 0 2006.285.23:10:29.40#ibcon#wrote, iclass 16, count 0 2006.285.23:10:29.40#ibcon#about to read 3, iclass 16, count 0 2006.285.23:10:29.42#ibcon#read 3, iclass 16, count 0 2006.285.23:10:29.42#ibcon#about to read 4, iclass 16, count 0 2006.285.23:10:29.42#ibcon#read 4, iclass 16, count 0 2006.285.23:10:29.42#ibcon#about to read 5, iclass 16, count 0 2006.285.23:10:29.42#ibcon#read 5, iclass 16, count 0 2006.285.23:10:29.42#ibcon#about to read 6, iclass 16, count 0 2006.285.23:10:29.42#ibcon#read 6, iclass 16, count 0 2006.285.23:10:29.42#ibcon#end of sib2, iclass 16, count 0 2006.285.23:10:29.42#ibcon#*mode == 0, iclass 16, count 0 2006.285.23:10:29.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.23:10:29.42#ibcon#[25=USB\r\n] 2006.285.23:10:29.42#ibcon#*before write, iclass 16, count 0 2006.285.23:10:29.42#ibcon#enter sib2, iclass 16, count 0 2006.285.23:10:29.42#ibcon#flushed, iclass 16, count 0 2006.285.23:10:29.42#ibcon#about to write, iclass 16, count 0 2006.285.23:10:29.42#ibcon#wrote, iclass 16, count 0 2006.285.23:10:29.42#ibcon#about to read 3, iclass 16, count 0 2006.285.23:10:29.45#ibcon#read 3, iclass 16, count 0 2006.285.23:10:29.45#ibcon#about to read 4, iclass 16, count 0 2006.285.23:10:29.45#ibcon#read 4, iclass 16, count 0 2006.285.23:10:29.45#ibcon#about to read 5, iclass 16, count 0 2006.285.23:10:29.45#ibcon#read 5, iclass 16, count 0 2006.285.23:10:29.45#ibcon#about to read 6, iclass 16, count 0 2006.285.23:10:29.45#ibcon#read 6, iclass 16, count 0 2006.285.23:10:29.45#ibcon#end of sib2, iclass 16, count 0 2006.285.23:10:29.45#ibcon#*after write, iclass 16, count 0 2006.285.23:10:29.45#ibcon#*before return 0, iclass 16, count 0 2006.285.23:10:29.45#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:10:29.45#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:10:29.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.23:10:29.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.23:10:29.45$vck44/valo=5,734.99 2006.285.23:10:29.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.23:10:29.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.23:10:29.45#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:29.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:10:29.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:10:29.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:10:29.45#ibcon#enter wrdev, iclass 18, count 0 2006.285.23:10:29.45#ibcon#first serial, iclass 18, count 0 2006.285.23:10:29.45#ibcon#enter sib2, iclass 18, count 0 2006.285.23:10:29.45#ibcon#flushed, iclass 18, count 0 2006.285.23:10:29.45#ibcon#about to write, iclass 18, count 0 2006.285.23:10:29.45#ibcon#wrote, iclass 18, count 0 2006.285.23:10:29.45#ibcon#about to read 3, iclass 18, count 0 2006.285.23:10:29.47#ibcon#read 3, iclass 18, count 0 2006.285.23:10:29.47#ibcon#about to read 4, iclass 18, count 0 2006.285.23:10:29.47#ibcon#read 4, iclass 18, count 0 2006.285.23:10:29.47#ibcon#about to read 5, iclass 18, count 0 2006.285.23:10:29.47#ibcon#read 5, iclass 18, count 0 2006.285.23:10:29.47#ibcon#about to read 6, iclass 18, count 0 2006.285.23:10:29.47#ibcon#read 6, iclass 18, count 0 2006.285.23:10:29.47#ibcon#end of sib2, iclass 18, count 0 2006.285.23:10:29.47#ibcon#*mode == 0, iclass 18, count 0 2006.285.23:10:29.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.23:10:29.47#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.23:10:29.47#ibcon#*before write, iclass 18, count 0 2006.285.23:10:29.47#ibcon#enter sib2, iclass 18, count 0 2006.285.23:10:29.47#ibcon#flushed, iclass 18, count 0 2006.285.23:10:29.47#ibcon#about to write, iclass 18, count 0 2006.285.23:10:29.47#ibcon#wrote, iclass 18, count 0 2006.285.23:10:29.47#ibcon#about to read 3, iclass 18, count 0 2006.285.23:10:29.51#ibcon#read 3, iclass 18, count 0 2006.285.23:10:29.51#ibcon#about to read 4, iclass 18, count 0 2006.285.23:10:29.51#ibcon#read 4, iclass 18, count 0 2006.285.23:10:29.51#ibcon#about to read 5, iclass 18, count 0 2006.285.23:10:29.51#ibcon#read 5, iclass 18, count 0 2006.285.23:10:29.51#ibcon#about to read 6, iclass 18, count 0 2006.285.23:10:29.51#ibcon#read 6, iclass 18, count 0 2006.285.23:10:29.51#ibcon#end of sib2, iclass 18, count 0 2006.285.23:10:29.51#ibcon#*after write, iclass 18, count 0 2006.285.23:10:29.51#ibcon#*before return 0, iclass 18, count 0 2006.285.23:10:29.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:10:29.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:10:29.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.23:10:29.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.23:10:29.51$vck44/va=5,3 2006.285.23:10:29.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.23:10:29.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.23:10:29.51#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:29.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:10:29.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:10:29.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:10:29.57#ibcon#enter wrdev, iclass 20, count 2 2006.285.23:10:29.57#ibcon#first serial, iclass 20, count 2 2006.285.23:10:29.57#ibcon#enter sib2, iclass 20, count 2 2006.285.23:10:29.57#ibcon#flushed, iclass 20, count 2 2006.285.23:10:29.57#ibcon#about to write, iclass 20, count 2 2006.285.23:10:29.57#ibcon#wrote, iclass 20, count 2 2006.285.23:10:29.57#ibcon#about to read 3, iclass 20, count 2 2006.285.23:10:29.59#ibcon#read 3, iclass 20, count 2 2006.285.23:10:29.59#ibcon#about to read 4, iclass 20, count 2 2006.285.23:10:29.59#ibcon#read 4, iclass 20, count 2 2006.285.23:10:29.59#ibcon#about to read 5, iclass 20, count 2 2006.285.23:10:29.59#ibcon#read 5, iclass 20, count 2 2006.285.23:10:29.59#ibcon#about to read 6, iclass 20, count 2 2006.285.23:10:29.59#ibcon#read 6, iclass 20, count 2 2006.285.23:10:29.59#ibcon#end of sib2, iclass 20, count 2 2006.285.23:10:29.59#ibcon#*mode == 0, iclass 20, count 2 2006.285.23:10:29.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.23:10:29.59#ibcon#[25=AT05-03\r\n] 2006.285.23:10:29.59#ibcon#*before write, iclass 20, count 2 2006.285.23:10:29.59#ibcon#enter sib2, iclass 20, count 2 2006.285.23:10:29.59#ibcon#flushed, iclass 20, count 2 2006.285.23:10:29.59#ibcon#about to write, iclass 20, count 2 2006.285.23:10:29.59#ibcon#wrote, iclass 20, count 2 2006.285.23:10:29.59#ibcon#about to read 3, iclass 20, count 2 2006.285.23:10:29.62#ibcon#read 3, iclass 20, count 2 2006.285.23:10:29.62#ibcon#about to read 4, iclass 20, count 2 2006.285.23:10:29.62#ibcon#read 4, iclass 20, count 2 2006.285.23:10:29.62#ibcon#about to read 5, iclass 20, count 2 2006.285.23:10:29.62#ibcon#read 5, iclass 20, count 2 2006.285.23:10:29.62#ibcon#about to read 6, iclass 20, count 2 2006.285.23:10:29.62#ibcon#read 6, iclass 20, count 2 2006.285.23:10:29.62#ibcon#end of sib2, iclass 20, count 2 2006.285.23:10:29.62#ibcon#*after write, iclass 20, count 2 2006.285.23:10:29.62#ibcon#*before return 0, iclass 20, count 2 2006.285.23:10:29.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:10:29.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:10:29.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.23:10:29.62#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:29.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:10:29.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:10:29.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:10:29.74#ibcon#enter wrdev, iclass 20, count 0 2006.285.23:10:29.74#ibcon#first serial, iclass 20, count 0 2006.285.23:10:29.74#ibcon#enter sib2, iclass 20, count 0 2006.285.23:10:29.74#ibcon#flushed, iclass 20, count 0 2006.285.23:10:29.74#ibcon#about to write, iclass 20, count 0 2006.285.23:10:29.74#ibcon#wrote, iclass 20, count 0 2006.285.23:10:29.74#ibcon#about to read 3, iclass 20, count 0 2006.285.23:10:29.76#ibcon#read 3, iclass 20, count 0 2006.285.23:10:29.76#ibcon#about to read 4, iclass 20, count 0 2006.285.23:10:29.76#ibcon#read 4, iclass 20, count 0 2006.285.23:10:29.76#ibcon#about to read 5, iclass 20, count 0 2006.285.23:10:29.76#ibcon#read 5, iclass 20, count 0 2006.285.23:10:29.76#ibcon#about to read 6, iclass 20, count 0 2006.285.23:10:29.76#ibcon#read 6, iclass 20, count 0 2006.285.23:10:29.76#ibcon#end of sib2, iclass 20, count 0 2006.285.23:10:29.76#ibcon#*mode == 0, iclass 20, count 0 2006.285.23:10:29.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.23:10:29.76#ibcon#[25=USB\r\n] 2006.285.23:10:29.76#ibcon#*before write, iclass 20, count 0 2006.285.23:10:29.76#ibcon#enter sib2, iclass 20, count 0 2006.285.23:10:29.76#ibcon#flushed, iclass 20, count 0 2006.285.23:10:29.76#ibcon#about to write, iclass 20, count 0 2006.285.23:10:29.76#ibcon#wrote, iclass 20, count 0 2006.285.23:10:29.76#ibcon#about to read 3, iclass 20, count 0 2006.285.23:10:29.79#ibcon#read 3, iclass 20, count 0 2006.285.23:10:29.79#ibcon#about to read 4, iclass 20, count 0 2006.285.23:10:29.79#ibcon#read 4, iclass 20, count 0 2006.285.23:10:29.79#ibcon#about to read 5, iclass 20, count 0 2006.285.23:10:29.79#ibcon#read 5, iclass 20, count 0 2006.285.23:10:29.79#ibcon#about to read 6, iclass 20, count 0 2006.285.23:10:29.79#ibcon#read 6, iclass 20, count 0 2006.285.23:10:29.79#ibcon#end of sib2, iclass 20, count 0 2006.285.23:10:29.79#ibcon#*after write, iclass 20, count 0 2006.285.23:10:29.79#ibcon#*before return 0, iclass 20, count 0 2006.285.23:10:29.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:10:29.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:10:29.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.23:10:29.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.23:10:29.79$vck44/valo=6,814.99 2006.285.23:10:29.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.23:10:29.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.23:10:29.79#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:29.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:10:29.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:10:29.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:10:29.79#ibcon#enter wrdev, iclass 22, count 0 2006.285.23:10:29.79#ibcon#first serial, iclass 22, count 0 2006.285.23:10:29.79#ibcon#enter sib2, iclass 22, count 0 2006.285.23:10:29.79#ibcon#flushed, iclass 22, count 0 2006.285.23:10:29.79#ibcon#about to write, iclass 22, count 0 2006.285.23:10:29.79#ibcon#wrote, iclass 22, count 0 2006.285.23:10:29.79#ibcon#about to read 3, iclass 22, count 0 2006.285.23:10:29.81#ibcon#read 3, iclass 22, count 0 2006.285.23:10:29.81#ibcon#about to read 4, iclass 22, count 0 2006.285.23:10:29.81#ibcon#read 4, iclass 22, count 0 2006.285.23:10:29.81#ibcon#about to read 5, iclass 22, count 0 2006.285.23:10:29.81#ibcon#read 5, iclass 22, count 0 2006.285.23:10:29.81#ibcon#about to read 6, iclass 22, count 0 2006.285.23:10:29.81#ibcon#read 6, iclass 22, count 0 2006.285.23:10:29.81#ibcon#end of sib2, iclass 22, count 0 2006.285.23:10:29.81#ibcon#*mode == 0, iclass 22, count 0 2006.285.23:10:29.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.23:10:29.81#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.23:10:29.81#ibcon#*before write, iclass 22, count 0 2006.285.23:10:29.81#ibcon#enter sib2, iclass 22, count 0 2006.285.23:10:29.81#ibcon#flushed, iclass 22, count 0 2006.285.23:10:29.81#ibcon#about to write, iclass 22, count 0 2006.285.23:10:29.81#ibcon#wrote, iclass 22, count 0 2006.285.23:10:29.81#ibcon#about to read 3, iclass 22, count 0 2006.285.23:10:29.85#ibcon#read 3, iclass 22, count 0 2006.285.23:10:29.85#ibcon#about to read 4, iclass 22, count 0 2006.285.23:10:29.85#ibcon#read 4, iclass 22, count 0 2006.285.23:10:29.85#ibcon#about to read 5, iclass 22, count 0 2006.285.23:10:29.85#ibcon#read 5, iclass 22, count 0 2006.285.23:10:29.85#ibcon#about to read 6, iclass 22, count 0 2006.285.23:10:29.85#ibcon#read 6, iclass 22, count 0 2006.285.23:10:29.85#ibcon#end of sib2, iclass 22, count 0 2006.285.23:10:29.85#ibcon#*after write, iclass 22, count 0 2006.285.23:10:29.85#ibcon#*before return 0, iclass 22, count 0 2006.285.23:10:29.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:10:29.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:10:29.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.23:10:29.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.23:10:29.85$vck44/va=6,4 2006.285.23:10:29.85#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.23:10:29.85#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.23:10:29.85#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:29.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:10:29.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:10:29.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:10:29.91#ibcon#enter wrdev, iclass 24, count 2 2006.285.23:10:29.91#ibcon#first serial, iclass 24, count 2 2006.285.23:10:29.91#ibcon#enter sib2, iclass 24, count 2 2006.285.23:10:29.91#ibcon#flushed, iclass 24, count 2 2006.285.23:10:29.91#ibcon#about to write, iclass 24, count 2 2006.285.23:10:29.91#ibcon#wrote, iclass 24, count 2 2006.285.23:10:29.91#ibcon#about to read 3, iclass 24, count 2 2006.285.23:10:29.93#ibcon#read 3, iclass 24, count 2 2006.285.23:10:29.93#ibcon#about to read 4, iclass 24, count 2 2006.285.23:10:29.93#ibcon#read 4, iclass 24, count 2 2006.285.23:10:29.93#ibcon#about to read 5, iclass 24, count 2 2006.285.23:10:29.93#ibcon#read 5, iclass 24, count 2 2006.285.23:10:29.93#ibcon#about to read 6, iclass 24, count 2 2006.285.23:10:29.93#ibcon#read 6, iclass 24, count 2 2006.285.23:10:29.93#ibcon#end of sib2, iclass 24, count 2 2006.285.23:10:29.93#ibcon#*mode == 0, iclass 24, count 2 2006.285.23:10:29.93#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.23:10:29.93#ibcon#[25=AT06-04\r\n] 2006.285.23:10:29.93#ibcon#*before write, iclass 24, count 2 2006.285.23:10:29.93#ibcon#enter sib2, iclass 24, count 2 2006.285.23:10:29.93#ibcon#flushed, iclass 24, count 2 2006.285.23:10:29.93#ibcon#about to write, iclass 24, count 2 2006.285.23:10:29.93#ibcon#wrote, iclass 24, count 2 2006.285.23:10:29.93#ibcon#about to read 3, iclass 24, count 2 2006.285.23:10:29.96#ibcon#read 3, iclass 24, count 2 2006.285.23:10:29.96#ibcon#about to read 4, iclass 24, count 2 2006.285.23:10:29.96#ibcon#read 4, iclass 24, count 2 2006.285.23:10:29.96#ibcon#about to read 5, iclass 24, count 2 2006.285.23:10:29.96#ibcon#read 5, iclass 24, count 2 2006.285.23:10:29.96#ibcon#about to read 6, iclass 24, count 2 2006.285.23:10:29.96#ibcon#read 6, iclass 24, count 2 2006.285.23:10:29.96#ibcon#end of sib2, iclass 24, count 2 2006.285.23:10:29.96#ibcon#*after write, iclass 24, count 2 2006.285.23:10:29.96#ibcon#*before return 0, iclass 24, count 2 2006.285.23:10:29.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:10:29.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:10:29.96#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.23:10:29.96#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:29.96#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:10:30.08#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:10:30.08#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:10:30.08#ibcon#enter wrdev, iclass 24, count 0 2006.285.23:10:30.08#ibcon#first serial, iclass 24, count 0 2006.285.23:10:30.08#ibcon#enter sib2, iclass 24, count 0 2006.285.23:10:30.08#ibcon#flushed, iclass 24, count 0 2006.285.23:10:30.08#ibcon#about to write, iclass 24, count 0 2006.285.23:10:30.08#ibcon#wrote, iclass 24, count 0 2006.285.23:10:30.08#ibcon#about to read 3, iclass 24, count 0 2006.285.23:10:30.10#ibcon#read 3, iclass 24, count 0 2006.285.23:10:30.10#ibcon#about to read 4, iclass 24, count 0 2006.285.23:10:30.10#ibcon#read 4, iclass 24, count 0 2006.285.23:10:30.10#ibcon#about to read 5, iclass 24, count 0 2006.285.23:10:30.10#ibcon#read 5, iclass 24, count 0 2006.285.23:10:30.10#ibcon#about to read 6, iclass 24, count 0 2006.285.23:10:30.10#ibcon#read 6, iclass 24, count 0 2006.285.23:10:30.10#ibcon#end of sib2, iclass 24, count 0 2006.285.23:10:30.10#ibcon#*mode == 0, iclass 24, count 0 2006.285.23:10:30.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.23:10:30.10#ibcon#[25=USB\r\n] 2006.285.23:10:30.10#ibcon#*before write, iclass 24, count 0 2006.285.23:10:30.10#ibcon#enter sib2, iclass 24, count 0 2006.285.23:10:30.10#ibcon#flushed, iclass 24, count 0 2006.285.23:10:30.10#ibcon#about to write, iclass 24, count 0 2006.285.23:10:30.10#ibcon#wrote, iclass 24, count 0 2006.285.23:10:30.10#ibcon#about to read 3, iclass 24, count 0 2006.285.23:10:30.13#ibcon#read 3, iclass 24, count 0 2006.285.23:10:30.13#ibcon#about to read 4, iclass 24, count 0 2006.285.23:10:30.13#ibcon#read 4, iclass 24, count 0 2006.285.23:10:30.13#ibcon#about to read 5, iclass 24, count 0 2006.285.23:10:30.13#ibcon#read 5, iclass 24, count 0 2006.285.23:10:30.13#ibcon#about to read 6, iclass 24, count 0 2006.285.23:10:30.13#ibcon#read 6, iclass 24, count 0 2006.285.23:10:30.13#ibcon#end of sib2, iclass 24, count 0 2006.285.23:10:30.13#ibcon#*after write, iclass 24, count 0 2006.285.23:10:30.13#ibcon#*before return 0, iclass 24, count 0 2006.285.23:10:30.13#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:10:30.13#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:10:30.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.23:10:30.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.23:10:30.13$vck44/valo=7,864.99 2006.285.23:10:30.13#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.23:10:30.13#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.23:10:30.13#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:30.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:10:30.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:10:30.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:10:30.13#ibcon#enter wrdev, iclass 26, count 0 2006.285.23:10:30.13#ibcon#first serial, iclass 26, count 0 2006.285.23:10:30.13#ibcon#enter sib2, iclass 26, count 0 2006.285.23:10:30.13#ibcon#flushed, iclass 26, count 0 2006.285.23:10:30.13#ibcon#about to write, iclass 26, count 0 2006.285.23:10:30.13#ibcon#wrote, iclass 26, count 0 2006.285.23:10:30.13#ibcon#about to read 3, iclass 26, count 0 2006.285.23:10:30.15#ibcon#read 3, iclass 26, count 0 2006.285.23:10:30.15#ibcon#about to read 4, iclass 26, count 0 2006.285.23:10:30.15#ibcon#read 4, iclass 26, count 0 2006.285.23:10:30.15#ibcon#about to read 5, iclass 26, count 0 2006.285.23:10:30.15#ibcon#read 5, iclass 26, count 0 2006.285.23:10:30.15#ibcon#about to read 6, iclass 26, count 0 2006.285.23:10:30.15#ibcon#read 6, iclass 26, count 0 2006.285.23:10:30.15#ibcon#end of sib2, iclass 26, count 0 2006.285.23:10:30.15#ibcon#*mode == 0, iclass 26, count 0 2006.285.23:10:30.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.23:10:30.15#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.23:10:30.15#ibcon#*before write, iclass 26, count 0 2006.285.23:10:30.15#ibcon#enter sib2, iclass 26, count 0 2006.285.23:10:30.15#ibcon#flushed, iclass 26, count 0 2006.285.23:10:30.15#ibcon#about to write, iclass 26, count 0 2006.285.23:10:30.15#ibcon#wrote, iclass 26, count 0 2006.285.23:10:30.15#ibcon#about to read 3, iclass 26, count 0 2006.285.23:10:30.19#ibcon#read 3, iclass 26, count 0 2006.285.23:10:30.19#ibcon#about to read 4, iclass 26, count 0 2006.285.23:10:30.19#ibcon#read 4, iclass 26, count 0 2006.285.23:10:30.19#ibcon#about to read 5, iclass 26, count 0 2006.285.23:10:30.19#ibcon#read 5, iclass 26, count 0 2006.285.23:10:30.19#ibcon#about to read 6, iclass 26, count 0 2006.285.23:10:30.19#ibcon#read 6, iclass 26, count 0 2006.285.23:10:30.19#ibcon#end of sib2, iclass 26, count 0 2006.285.23:10:30.19#ibcon#*after write, iclass 26, count 0 2006.285.23:10:30.19#ibcon#*before return 0, iclass 26, count 0 2006.285.23:10:30.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:10:30.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:10:30.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.23:10:30.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.23:10:30.19$vck44/va=7,4 2006.285.23:10:30.19#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.23:10:30.19#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.23:10:30.19#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:30.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:10:30.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:10:30.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:10:30.25#ibcon#enter wrdev, iclass 28, count 2 2006.285.23:10:30.25#ibcon#first serial, iclass 28, count 2 2006.285.23:10:30.25#ibcon#enter sib2, iclass 28, count 2 2006.285.23:10:30.25#ibcon#flushed, iclass 28, count 2 2006.285.23:10:30.25#ibcon#about to write, iclass 28, count 2 2006.285.23:10:30.25#ibcon#wrote, iclass 28, count 2 2006.285.23:10:30.25#ibcon#about to read 3, iclass 28, count 2 2006.285.23:10:30.27#ibcon#read 3, iclass 28, count 2 2006.285.23:10:30.27#ibcon#about to read 4, iclass 28, count 2 2006.285.23:10:30.27#ibcon#read 4, iclass 28, count 2 2006.285.23:10:30.27#ibcon#about to read 5, iclass 28, count 2 2006.285.23:10:30.27#ibcon#read 5, iclass 28, count 2 2006.285.23:10:30.27#ibcon#about to read 6, iclass 28, count 2 2006.285.23:10:30.27#ibcon#read 6, iclass 28, count 2 2006.285.23:10:30.27#ibcon#end of sib2, iclass 28, count 2 2006.285.23:10:30.27#ibcon#*mode == 0, iclass 28, count 2 2006.285.23:10:30.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.23:10:30.27#ibcon#[25=AT07-04\r\n] 2006.285.23:10:30.27#ibcon#*before write, iclass 28, count 2 2006.285.23:10:30.27#ibcon#enter sib2, iclass 28, count 2 2006.285.23:10:30.27#ibcon#flushed, iclass 28, count 2 2006.285.23:10:30.27#ibcon#about to write, iclass 28, count 2 2006.285.23:10:30.27#ibcon#wrote, iclass 28, count 2 2006.285.23:10:30.27#ibcon#about to read 3, iclass 28, count 2 2006.285.23:10:30.30#ibcon#read 3, iclass 28, count 2 2006.285.23:10:30.30#ibcon#about to read 4, iclass 28, count 2 2006.285.23:10:30.30#ibcon#read 4, iclass 28, count 2 2006.285.23:10:30.30#ibcon#about to read 5, iclass 28, count 2 2006.285.23:10:30.30#ibcon#read 5, iclass 28, count 2 2006.285.23:10:30.30#ibcon#about to read 6, iclass 28, count 2 2006.285.23:10:30.30#ibcon#read 6, iclass 28, count 2 2006.285.23:10:30.30#ibcon#end of sib2, iclass 28, count 2 2006.285.23:10:30.30#ibcon#*after write, iclass 28, count 2 2006.285.23:10:30.30#ibcon#*before return 0, iclass 28, count 2 2006.285.23:10:30.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:10:30.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:10:30.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.23:10:30.30#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:30.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:10:30.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:10:30.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:10:30.42#ibcon#enter wrdev, iclass 28, count 0 2006.285.23:10:30.42#ibcon#first serial, iclass 28, count 0 2006.285.23:10:30.42#ibcon#enter sib2, iclass 28, count 0 2006.285.23:10:30.42#ibcon#flushed, iclass 28, count 0 2006.285.23:10:30.42#ibcon#about to write, iclass 28, count 0 2006.285.23:10:30.42#ibcon#wrote, iclass 28, count 0 2006.285.23:10:30.42#ibcon#about to read 3, iclass 28, count 0 2006.285.23:10:30.44#ibcon#read 3, iclass 28, count 0 2006.285.23:10:30.44#ibcon#about to read 4, iclass 28, count 0 2006.285.23:10:30.44#ibcon#read 4, iclass 28, count 0 2006.285.23:10:30.44#ibcon#about to read 5, iclass 28, count 0 2006.285.23:10:30.44#ibcon#read 5, iclass 28, count 0 2006.285.23:10:30.44#ibcon#about to read 6, iclass 28, count 0 2006.285.23:10:30.44#ibcon#read 6, iclass 28, count 0 2006.285.23:10:30.44#ibcon#end of sib2, iclass 28, count 0 2006.285.23:10:30.44#ibcon#*mode == 0, iclass 28, count 0 2006.285.23:10:30.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.23:10:30.44#ibcon#[25=USB\r\n] 2006.285.23:10:30.44#ibcon#*before write, iclass 28, count 0 2006.285.23:10:30.44#ibcon#enter sib2, iclass 28, count 0 2006.285.23:10:30.44#ibcon#flushed, iclass 28, count 0 2006.285.23:10:30.44#ibcon#about to write, iclass 28, count 0 2006.285.23:10:30.44#ibcon#wrote, iclass 28, count 0 2006.285.23:10:30.44#ibcon#about to read 3, iclass 28, count 0 2006.285.23:10:30.47#ibcon#read 3, iclass 28, count 0 2006.285.23:10:30.47#ibcon#about to read 4, iclass 28, count 0 2006.285.23:10:30.47#ibcon#read 4, iclass 28, count 0 2006.285.23:10:30.47#ibcon#about to read 5, iclass 28, count 0 2006.285.23:10:30.47#ibcon#read 5, iclass 28, count 0 2006.285.23:10:30.47#ibcon#about to read 6, iclass 28, count 0 2006.285.23:10:30.47#ibcon#read 6, iclass 28, count 0 2006.285.23:10:30.47#ibcon#end of sib2, iclass 28, count 0 2006.285.23:10:30.47#ibcon#*after write, iclass 28, count 0 2006.285.23:10:30.47#ibcon#*before return 0, iclass 28, count 0 2006.285.23:10:30.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:10:30.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:10:30.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.23:10:30.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.23:10:30.47$vck44/valo=8,884.99 2006.285.23:10:30.47#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.23:10:30.47#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.23:10:30.47#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:30.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:10:30.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:10:30.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:10:30.47#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:10:30.47#ibcon#first serial, iclass 30, count 0 2006.285.23:10:30.47#ibcon#enter sib2, iclass 30, count 0 2006.285.23:10:30.47#ibcon#flushed, iclass 30, count 0 2006.285.23:10:30.47#ibcon#about to write, iclass 30, count 0 2006.285.23:10:30.47#ibcon#wrote, iclass 30, count 0 2006.285.23:10:30.47#ibcon#about to read 3, iclass 30, count 0 2006.285.23:10:30.49#ibcon#read 3, iclass 30, count 0 2006.285.23:10:30.49#ibcon#about to read 4, iclass 30, count 0 2006.285.23:10:30.49#ibcon#read 4, iclass 30, count 0 2006.285.23:10:30.49#ibcon#about to read 5, iclass 30, count 0 2006.285.23:10:30.49#ibcon#read 5, iclass 30, count 0 2006.285.23:10:30.49#ibcon#about to read 6, iclass 30, count 0 2006.285.23:10:30.49#ibcon#read 6, iclass 30, count 0 2006.285.23:10:30.49#ibcon#end of sib2, iclass 30, count 0 2006.285.23:10:30.49#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:10:30.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:10:30.49#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.23:10:30.49#ibcon#*before write, iclass 30, count 0 2006.285.23:10:30.49#ibcon#enter sib2, iclass 30, count 0 2006.285.23:10:30.49#ibcon#flushed, iclass 30, count 0 2006.285.23:10:30.49#ibcon#about to write, iclass 30, count 0 2006.285.23:10:30.49#ibcon#wrote, iclass 30, count 0 2006.285.23:10:30.49#ibcon#about to read 3, iclass 30, count 0 2006.285.23:10:30.53#ibcon#read 3, iclass 30, count 0 2006.285.23:10:30.53#ibcon#about to read 4, iclass 30, count 0 2006.285.23:10:30.53#ibcon#read 4, iclass 30, count 0 2006.285.23:10:30.53#ibcon#about to read 5, iclass 30, count 0 2006.285.23:10:30.53#ibcon#read 5, iclass 30, count 0 2006.285.23:10:30.53#ibcon#about to read 6, iclass 30, count 0 2006.285.23:10:30.53#ibcon#read 6, iclass 30, count 0 2006.285.23:10:30.53#ibcon#end of sib2, iclass 30, count 0 2006.285.23:10:30.53#ibcon#*after write, iclass 30, count 0 2006.285.23:10:30.53#ibcon#*before return 0, iclass 30, count 0 2006.285.23:10:30.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:10:30.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:10:30.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:10:30.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:10:30.53$vck44/va=8,3 2006.285.23:10:30.53#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.23:10:30.53#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.23:10:30.53#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:30.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:10:30.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:10:30.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:10:30.59#ibcon#enter wrdev, iclass 32, count 2 2006.285.23:10:30.59#ibcon#first serial, iclass 32, count 2 2006.285.23:10:30.59#ibcon#enter sib2, iclass 32, count 2 2006.285.23:10:30.59#ibcon#flushed, iclass 32, count 2 2006.285.23:10:30.59#ibcon#about to write, iclass 32, count 2 2006.285.23:10:30.59#ibcon#wrote, iclass 32, count 2 2006.285.23:10:30.59#ibcon#about to read 3, iclass 32, count 2 2006.285.23:10:30.61#ibcon#read 3, iclass 32, count 2 2006.285.23:10:30.61#ibcon#about to read 4, iclass 32, count 2 2006.285.23:10:30.61#ibcon#read 4, iclass 32, count 2 2006.285.23:10:30.61#ibcon#about to read 5, iclass 32, count 2 2006.285.23:10:30.61#ibcon#read 5, iclass 32, count 2 2006.285.23:10:30.61#ibcon#about to read 6, iclass 32, count 2 2006.285.23:10:30.61#ibcon#read 6, iclass 32, count 2 2006.285.23:10:30.61#ibcon#end of sib2, iclass 32, count 2 2006.285.23:10:30.61#ibcon#*mode == 0, iclass 32, count 2 2006.285.23:10:30.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.23:10:30.61#ibcon#[25=AT08-03\r\n] 2006.285.23:10:30.61#ibcon#*before write, iclass 32, count 2 2006.285.23:10:30.61#ibcon#enter sib2, iclass 32, count 2 2006.285.23:10:30.61#ibcon#flushed, iclass 32, count 2 2006.285.23:10:30.61#ibcon#about to write, iclass 32, count 2 2006.285.23:10:30.61#ibcon#wrote, iclass 32, count 2 2006.285.23:10:30.61#ibcon#about to read 3, iclass 32, count 2 2006.285.23:10:30.64#ibcon#read 3, iclass 32, count 2 2006.285.23:10:30.64#ibcon#about to read 4, iclass 32, count 2 2006.285.23:10:30.64#ibcon#read 4, iclass 32, count 2 2006.285.23:10:30.64#ibcon#about to read 5, iclass 32, count 2 2006.285.23:10:30.64#ibcon#read 5, iclass 32, count 2 2006.285.23:10:30.64#ibcon#about to read 6, iclass 32, count 2 2006.285.23:10:30.64#ibcon#read 6, iclass 32, count 2 2006.285.23:10:30.64#ibcon#end of sib2, iclass 32, count 2 2006.285.23:10:30.64#ibcon#*after write, iclass 32, count 2 2006.285.23:10:30.64#ibcon#*before return 0, iclass 32, count 2 2006.285.23:10:30.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:10:30.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:10:30.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.23:10:30.64#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:30.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:10:30.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:10:30.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:10:30.76#ibcon#enter wrdev, iclass 32, count 0 2006.285.23:10:30.76#ibcon#first serial, iclass 32, count 0 2006.285.23:10:30.76#ibcon#enter sib2, iclass 32, count 0 2006.285.23:10:30.76#ibcon#flushed, iclass 32, count 0 2006.285.23:10:30.76#ibcon#about to write, iclass 32, count 0 2006.285.23:10:30.76#ibcon#wrote, iclass 32, count 0 2006.285.23:10:30.76#ibcon#about to read 3, iclass 32, count 0 2006.285.23:10:30.78#ibcon#read 3, iclass 32, count 0 2006.285.23:10:30.78#ibcon#about to read 4, iclass 32, count 0 2006.285.23:10:30.78#ibcon#read 4, iclass 32, count 0 2006.285.23:10:30.78#ibcon#about to read 5, iclass 32, count 0 2006.285.23:10:30.78#ibcon#read 5, iclass 32, count 0 2006.285.23:10:30.78#ibcon#about to read 6, iclass 32, count 0 2006.285.23:10:30.78#ibcon#read 6, iclass 32, count 0 2006.285.23:10:30.78#ibcon#end of sib2, iclass 32, count 0 2006.285.23:10:30.78#ibcon#*mode == 0, iclass 32, count 0 2006.285.23:10:30.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.23:10:30.78#ibcon#[25=USB\r\n] 2006.285.23:10:30.78#ibcon#*before write, iclass 32, count 0 2006.285.23:10:30.78#ibcon#enter sib2, iclass 32, count 0 2006.285.23:10:30.78#ibcon#flushed, iclass 32, count 0 2006.285.23:10:30.78#ibcon#about to write, iclass 32, count 0 2006.285.23:10:30.78#ibcon#wrote, iclass 32, count 0 2006.285.23:10:30.78#ibcon#about to read 3, iclass 32, count 0 2006.285.23:10:30.81#ibcon#read 3, iclass 32, count 0 2006.285.23:10:30.81#ibcon#about to read 4, iclass 32, count 0 2006.285.23:10:30.81#ibcon#read 4, iclass 32, count 0 2006.285.23:10:30.81#ibcon#about to read 5, iclass 32, count 0 2006.285.23:10:30.81#ibcon#read 5, iclass 32, count 0 2006.285.23:10:30.81#ibcon#about to read 6, iclass 32, count 0 2006.285.23:10:30.81#ibcon#read 6, iclass 32, count 0 2006.285.23:10:30.81#ibcon#end of sib2, iclass 32, count 0 2006.285.23:10:30.81#ibcon#*after write, iclass 32, count 0 2006.285.23:10:30.81#ibcon#*before return 0, iclass 32, count 0 2006.285.23:10:30.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:10:30.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:10:30.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.23:10:30.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.23:10:30.81$vck44/vblo=1,629.99 2006.285.23:10:30.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.23:10:30.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.23:10:30.81#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:30.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:10:30.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:10:30.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:10:30.81#ibcon#enter wrdev, iclass 34, count 0 2006.285.23:10:30.81#ibcon#first serial, iclass 34, count 0 2006.285.23:10:30.81#ibcon#enter sib2, iclass 34, count 0 2006.285.23:10:30.81#ibcon#flushed, iclass 34, count 0 2006.285.23:10:30.81#ibcon#about to write, iclass 34, count 0 2006.285.23:10:30.81#ibcon#wrote, iclass 34, count 0 2006.285.23:10:30.81#ibcon#about to read 3, iclass 34, count 0 2006.285.23:10:30.83#ibcon#read 3, iclass 34, count 0 2006.285.23:10:30.83#ibcon#about to read 4, iclass 34, count 0 2006.285.23:10:30.83#ibcon#read 4, iclass 34, count 0 2006.285.23:10:30.83#ibcon#about to read 5, iclass 34, count 0 2006.285.23:10:30.83#ibcon#read 5, iclass 34, count 0 2006.285.23:10:30.83#ibcon#about to read 6, iclass 34, count 0 2006.285.23:10:30.83#ibcon#read 6, iclass 34, count 0 2006.285.23:10:30.83#ibcon#end of sib2, iclass 34, count 0 2006.285.23:10:30.83#ibcon#*mode == 0, iclass 34, count 0 2006.285.23:10:30.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.23:10:30.83#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.23:10:30.83#ibcon#*before write, iclass 34, count 0 2006.285.23:10:30.83#ibcon#enter sib2, iclass 34, count 0 2006.285.23:10:30.83#ibcon#flushed, iclass 34, count 0 2006.285.23:10:30.83#ibcon#about to write, iclass 34, count 0 2006.285.23:10:30.83#ibcon#wrote, iclass 34, count 0 2006.285.23:10:30.83#ibcon#about to read 3, iclass 34, count 0 2006.285.23:10:30.87#ibcon#read 3, iclass 34, count 0 2006.285.23:10:30.87#ibcon#about to read 4, iclass 34, count 0 2006.285.23:10:30.87#ibcon#read 4, iclass 34, count 0 2006.285.23:10:30.87#ibcon#about to read 5, iclass 34, count 0 2006.285.23:10:30.87#ibcon#read 5, iclass 34, count 0 2006.285.23:10:30.87#ibcon#about to read 6, iclass 34, count 0 2006.285.23:10:30.87#ibcon#read 6, iclass 34, count 0 2006.285.23:10:30.87#ibcon#end of sib2, iclass 34, count 0 2006.285.23:10:30.87#ibcon#*after write, iclass 34, count 0 2006.285.23:10:30.87#ibcon#*before return 0, iclass 34, count 0 2006.285.23:10:30.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:10:30.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:10:30.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.23:10:30.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.23:10:30.87$vck44/vb=1,4 2006.285.23:10:30.87#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.23:10:30.87#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.23:10:30.87#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:30.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:10:30.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:10:30.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:10:30.87#ibcon#enter wrdev, iclass 36, count 2 2006.285.23:10:30.87#ibcon#first serial, iclass 36, count 2 2006.285.23:10:30.87#ibcon#enter sib2, iclass 36, count 2 2006.285.23:10:30.87#ibcon#flushed, iclass 36, count 2 2006.285.23:10:30.87#ibcon#about to write, iclass 36, count 2 2006.285.23:10:30.87#ibcon#wrote, iclass 36, count 2 2006.285.23:10:30.87#ibcon#about to read 3, iclass 36, count 2 2006.285.23:10:30.89#ibcon#read 3, iclass 36, count 2 2006.285.23:10:30.89#ibcon#about to read 4, iclass 36, count 2 2006.285.23:10:30.89#ibcon#read 4, iclass 36, count 2 2006.285.23:10:30.89#ibcon#about to read 5, iclass 36, count 2 2006.285.23:10:30.89#ibcon#read 5, iclass 36, count 2 2006.285.23:10:30.89#ibcon#about to read 6, iclass 36, count 2 2006.285.23:10:30.89#ibcon#read 6, iclass 36, count 2 2006.285.23:10:30.89#ibcon#end of sib2, iclass 36, count 2 2006.285.23:10:30.89#ibcon#*mode == 0, iclass 36, count 2 2006.285.23:10:30.89#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.23:10:30.89#ibcon#[27=AT01-04\r\n] 2006.285.23:10:30.89#ibcon#*before write, iclass 36, count 2 2006.285.23:10:30.89#ibcon#enter sib2, iclass 36, count 2 2006.285.23:10:30.89#ibcon#flushed, iclass 36, count 2 2006.285.23:10:30.89#ibcon#about to write, iclass 36, count 2 2006.285.23:10:30.89#ibcon#wrote, iclass 36, count 2 2006.285.23:10:30.89#ibcon#about to read 3, iclass 36, count 2 2006.285.23:10:30.92#ibcon#read 3, iclass 36, count 2 2006.285.23:10:30.92#ibcon#about to read 4, iclass 36, count 2 2006.285.23:10:30.92#ibcon#read 4, iclass 36, count 2 2006.285.23:10:30.92#ibcon#about to read 5, iclass 36, count 2 2006.285.23:10:30.92#ibcon#read 5, iclass 36, count 2 2006.285.23:10:30.92#ibcon#about to read 6, iclass 36, count 2 2006.285.23:10:30.92#ibcon#read 6, iclass 36, count 2 2006.285.23:10:30.92#ibcon#end of sib2, iclass 36, count 2 2006.285.23:10:30.92#ibcon#*after write, iclass 36, count 2 2006.285.23:10:30.92#ibcon#*before return 0, iclass 36, count 2 2006.285.23:10:30.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:10:30.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:10:30.92#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.23:10:30.92#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:30.92#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:10:31.04#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:10:31.04#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:10:31.04#ibcon#enter wrdev, iclass 36, count 0 2006.285.23:10:31.04#ibcon#first serial, iclass 36, count 0 2006.285.23:10:31.04#ibcon#enter sib2, iclass 36, count 0 2006.285.23:10:31.04#ibcon#flushed, iclass 36, count 0 2006.285.23:10:31.04#ibcon#about to write, iclass 36, count 0 2006.285.23:10:31.04#ibcon#wrote, iclass 36, count 0 2006.285.23:10:31.04#ibcon#about to read 3, iclass 36, count 0 2006.285.23:10:31.06#ibcon#read 3, iclass 36, count 0 2006.285.23:10:31.06#ibcon#about to read 4, iclass 36, count 0 2006.285.23:10:31.06#ibcon#read 4, iclass 36, count 0 2006.285.23:10:31.06#ibcon#about to read 5, iclass 36, count 0 2006.285.23:10:31.06#ibcon#read 5, iclass 36, count 0 2006.285.23:10:31.06#ibcon#about to read 6, iclass 36, count 0 2006.285.23:10:31.06#ibcon#read 6, iclass 36, count 0 2006.285.23:10:31.06#ibcon#end of sib2, iclass 36, count 0 2006.285.23:10:31.06#ibcon#*mode == 0, iclass 36, count 0 2006.285.23:10:31.06#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.23:10:31.06#ibcon#[27=USB\r\n] 2006.285.23:10:31.06#ibcon#*before write, iclass 36, count 0 2006.285.23:10:31.06#ibcon#enter sib2, iclass 36, count 0 2006.285.23:10:31.06#ibcon#flushed, iclass 36, count 0 2006.285.23:10:31.06#ibcon#about to write, iclass 36, count 0 2006.285.23:10:31.06#ibcon#wrote, iclass 36, count 0 2006.285.23:10:31.06#ibcon#about to read 3, iclass 36, count 0 2006.285.23:10:31.09#ibcon#read 3, iclass 36, count 0 2006.285.23:10:31.09#ibcon#about to read 4, iclass 36, count 0 2006.285.23:10:31.09#ibcon#read 4, iclass 36, count 0 2006.285.23:10:31.09#ibcon#about to read 5, iclass 36, count 0 2006.285.23:10:31.09#ibcon#read 5, iclass 36, count 0 2006.285.23:10:31.09#ibcon#about to read 6, iclass 36, count 0 2006.285.23:10:31.09#ibcon#read 6, iclass 36, count 0 2006.285.23:10:31.09#ibcon#end of sib2, iclass 36, count 0 2006.285.23:10:31.09#ibcon#*after write, iclass 36, count 0 2006.285.23:10:31.09#ibcon#*before return 0, iclass 36, count 0 2006.285.23:10:31.09#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:10:31.09#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:10:31.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.23:10:31.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.23:10:31.09$vck44/vblo=2,634.99 2006.285.23:10:31.09#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.23:10:31.09#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.23:10:31.09#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:31.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:10:31.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:10:31.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:10:31.09#ibcon#enter wrdev, iclass 38, count 0 2006.285.23:10:31.09#ibcon#first serial, iclass 38, count 0 2006.285.23:10:31.09#ibcon#enter sib2, iclass 38, count 0 2006.285.23:10:31.09#ibcon#flushed, iclass 38, count 0 2006.285.23:10:31.09#ibcon#about to write, iclass 38, count 0 2006.285.23:10:31.09#ibcon#wrote, iclass 38, count 0 2006.285.23:10:31.09#ibcon#about to read 3, iclass 38, count 0 2006.285.23:10:31.11#ibcon#read 3, iclass 38, count 0 2006.285.23:10:31.11#ibcon#about to read 4, iclass 38, count 0 2006.285.23:10:31.11#ibcon#read 4, iclass 38, count 0 2006.285.23:10:31.11#ibcon#about to read 5, iclass 38, count 0 2006.285.23:10:31.11#ibcon#read 5, iclass 38, count 0 2006.285.23:10:31.11#ibcon#about to read 6, iclass 38, count 0 2006.285.23:10:31.11#ibcon#read 6, iclass 38, count 0 2006.285.23:10:31.11#ibcon#end of sib2, iclass 38, count 0 2006.285.23:10:31.11#ibcon#*mode == 0, iclass 38, count 0 2006.285.23:10:31.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.23:10:31.11#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.23:10:31.11#ibcon#*before write, iclass 38, count 0 2006.285.23:10:31.11#ibcon#enter sib2, iclass 38, count 0 2006.285.23:10:31.11#ibcon#flushed, iclass 38, count 0 2006.285.23:10:31.11#ibcon#about to write, iclass 38, count 0 2006.285.23:10:31.11#ibcon#wrote, iclass 38, count 0 2006.285.23:10:31.11#ibcon#about to read 3, iclass 38, count 0 2006.285.23:10:31.15#ibcon#read 3, iclass 38, count 0 2006.285.23:10:31.15#ibcon#about to read 4, iclass 38, count 0 2006.285.23:10:31.15#ibcon#read 4, iclass 38, count 0 2006.285.23:10:31.15#ibcon#about to read 5, iclass 38, count 0 2006.285.23:10:31.15#ibcon#read 5, iclass 38, count 0 2006.285.23:10:31.15#ibcon#about to read 6, iclass 38, count 0 2006.285.23:10:31.15#ibcon#read 6, iclass 38, count 0 2006.285.23:10:31.15#ibcon#end of sib2, iclass 38, count 0 2006.285.23:10:31.15#ibcon#*after write, iclass 38, count 0 2006.285.23:10:31.15#ibcon#*before return 0, iclass 38, count 0 2006.285.23:10:31.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:10:31.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:10:31.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.23:10:31.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.23:10:31.15$vck44/vb=2,5 2006.285.23:10:31.15#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.23:10:31.15#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.23:10:31.15#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:31.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:10:31.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:10:31.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:10:31.21#ibcon#enter wrdev, iclass 40, count 2 2006.285.23:10:31.21#ibcon#first serial, iclass 40, count 2 2006.285.23:10:31.21#ibcon#enter sib2, iclass 40, count 2 2006.285.23:10:31.21#ibcon#flushed, iclass 40, count 2 2006.285.23:10:31.21#ibcon#about to write, iclass 40, count 2 2006.285.23:10:31.21#ibcon#wrote, iclass 40, count 2 2006.285.23:10:31.21#ibcon#about to read 3, iclass 40, count 2 2006.285.23:10:31.23#ibcon#read 3, iclass 40, count 2 2006.285.23:10:31.23#ibcon#about to read 4, iclass 40, count 2 2006.285.23:10:31.23#ibcon#read 4, iclass 40, count 2 2006.285.23:10:31.23#ibcon#about to read 5, iclass 40, count 2 2006.285.23:10:31.23#ibcon#read 5, iclass 40, count 2 2006.285.23:10:31.23#ibcon#about to read 6, iclass 40, count 2 2006.285.23:10:31.23#ibcon#read 6, iclass 40, count 2 2006.285.23:10:31.23#ibcon#end of sib2, iclass 40, count 2 2006.285.23:10:31.23#ibcon#*mode == 0, iclass 40, count 2 2006.285.23:10:31.23#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.23:10:31.23#ibcon#[27=AT02-05\r\n] 2006.285.23:10:31.23#ibcon#*before write, iclass 40, count 2 2006.285.23:10:31.23#ibcon#enter sib2, iclass 40, count 2 2006.285.23:10:31.23#ibcon#flushed, iclass 40, count 2 2006.285.23:10:31.23#ibcon#about to write, iclass 40, count 2 2006.285.23:10:31.23#ibcon#wrote, iclass 40, count 2 2006.285.23:10:31.23#ibcon#about to read 3, iclass 40, count 2 2006.285.23:10:31.26#ibcon#read 3, iclass 40, count 2 2006.285.23:10:31.26#ibcon#about to read 4, iclass 40, count 2 2006.285.23:10:31.26#ibcon#read 4, iclass 40, count 2 2006.285.23:10:31.26#ibcon#about to read 5, iclass 40, count 2 2006.285.23:10:31.26#ibcon#read 5, iclass 40, count 2 2006.285.23:10:31.26#ibcon#about to read 6, iclass 40, count 2 2006.285.23:10:31.26#ibcon#read 6, iclass 40, count 2 2006.285.23:10:31.26#ibcon#end of sib2, iclass 40, count 2 2006.285.23:10:31.26#ibcon#*after write, iclass 40, count 2 2006.285.23:10:31.26#ibcon#*before return 0, iclass 40, count 2 2006.285.23:10:31.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:10:31.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:10:31.26#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.23:10:31.26#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:31.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:10:31.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:10:31.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:10:31.38#ibcon#enter wrdev, iclass 40, count 0 2006.285.23:10:31.38#ibcon#first serial, iclass 40, count 0 2006.285.23:10:31.38#ibcon#enter sib2, iclass 40, count 0 2006.285.23:10:31.38#ibcon#flushed, iclass 40, count 0 2006.285.23:10:31.38#ibcon#about to write, iclass 40, count 0 2006.285.23:10:31.38#ibcon#wrote, iclass 40, count 0 2006.285.23:10:31.38#ibcon#about to read 3, iclass 40, count 0 2006.285.23:10:31.40#ibcon#read 3, iclass 40, count 0 2006.285.23:10:31.40#ibcon#about to read 4, iclass 40, count 0 2006.285.23:10:31.40#ibcon#read 4, iclass 40, count 0 2006.285.23:10:31.40#ibcon#about to read 5, iclass 40, count 0 2006.285.23:10:31.40#ibcon#read 5, iclass 40, count 0 2006.285.23:10:31.40#ibcon#about to read 6, iclass 40, count 0 2006.285.23:10:31.40#ibcon#read 6, iclass 40, count 0 2006.285.23:10:31.40#ibcon#end of sib2, iclass 40, count 0 2006.285.23:10:31.40#ibcon#*mode == 0, iclass 40, count 0 2006.285.23:10:31.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.23:10:31.40#ibcon#[27=USB\r\n] 2006.285.23:10:31.40#ibcon#*before write, iclass 40, count 0 2006.285.23:10:31.40#ibcon#enter sib2, iclass 40, count 0 2006.285.23:10:31.40#ibcon#flushed, iclass 40, count 0 2006.285.23:10:31.40#ibcon#about to write, iclass 40, count 0 2006.285.23:10:31.40#ibcon#wrote, iclass 40, count 0 2006.285.23:10:31.40#ibcon#about to read 3, iclass 40, count 0 2006.285.23:10:31.43#ibcon#read 3, iclass 40, count 0 2006.285.23:10:31.43#ibcon#about to read 4, iclass 40, count 0 2006.285.23:10:31.43#ibcon#read 4, iclass 40, count 0 2006.285.23:10:31.43#ibcon#about to read 5, iclass 40, count 0 2006.285.23:10:31.43#ibcon#read 5, iclass 40, count 0 2006.285.23:10:31.43#ibcon#about to read 6, iclass 40, count 0 2006.285.23:10:31.43#ibcon#read 6, iclass 40, count 0 2006.285.23:10:31.43#ibcon#end of sib2, iclass 40, count 0 2006.285.23:10:31.43#ibcon#*after write, iclass 40, count 0 2006.285.23:10:31.43#ibcon#*before return 0, iclass 40, count 0 2006.285.23:10:31.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:10:31.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:10:31.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.23:10:31.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.23:10:31.43$vck44/vblo=3,649.99 2006.285.23:10:31.43#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.23:10:31.43#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.23:10:31.43#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:31.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:10:31.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:10:31.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:10:31.43#ibcon#enter wrdev, iclass 4, count 0 2006.285.23:10:31.43#ibcon#first serial, iclass 4, count 0 2006.285.23:10:31.43#ibcon#enter sib2, iclass 4, count 0 2006.285.23:10:31.43#ibcon#flushed, iclass 4, count 0 2006.285.23:10:31.43#ibcon#about to write, iclass 4, count 0 2006.285.23:10:31.43#ibcon#wrote, iclass 4, count 0 2006.285.23:10:31.43#ibcon#about to read 3, iclass 4, count 0 2006.285.23:10:31.45#ibcon#read 3, iclass 4, count 0 2006.285.23:10:31.45#ibcon#about to read 4, iclass 4, count 0 2006.285.23:10:31.45#ibcon#read 4, iclass 4, count 0 2006.285.23:10:31.45#ibcon#about to read 5, iclass 4, count 0 2006.285.23:10:31.45#ibcon#read 5, iclass 4, count 0 2006.285.23:10:31.45#ibcon#about to read 6, iclass 4, count 0 2006.285.23:10:31.45#ibcon#read 6, iclass 4, count 0 2006.285.23:10:31.45#ibcon#end of sib2, iclass 4, count 0 2006.285.23:10:31.45#ibcon#*mode == 0, iclass 4, count 0 2006.285.23:10:31.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.23:10:31.45#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.23:10:31.45#ibcon#*before write, iclass 4, count 0 2006.285.23:10:31.45#ibcon#enter sib2, iclass 4, count 0 2006.285.23:10:31.45#ibcon#flushed, iclass 4, count 0 2006.285.23:10:31.45#ibcon#about to write, iclass 4, count 0 2006.285.23:10:31.45#ibcon#wrote, iclass 4, count 0 2006.285.23:10:31.45#ibcon#about to read 3, iclass 4, count 0 2006.285.23:10:31.48#abcon#<5=/03 3.2 7.5 18.87 891016.4\r\n> 2006.285.23:10:31.49#ibcon#read 3, iclass 4, count 0 2006.285.23:10:31.49#ibcon#about to read 4, iclass 4, count 0 2006.285.23:10:31.49#ibcon#read 4, iclass 4, count 0 2006.285.23:10:31.49#ibcon#about to read 5, iclass 4, count 0 2006.285.23:10:31.49#ibcon#read 5, iclass 4, count 0 2006.285.23:10:31.49#ibcon#about to read 6, iclass 4, count 0 2006.285.23:10:31.49#ibcon#read 6, iclass 4, count 0 2006.285.23:10:31.49#ibcon#end of sib2, iclass 4, count 0 2006.285.23:10:31.49#ibcon#*after write, iclass 4, count 0 2006.285.23:10:31.49#ibcon#*before return 0, iclass 4, count 0 2006.285.23:10:31.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:10:31.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:10:31.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.23:10:31.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.23:10:31.49$vck44/vb=3,4 2006.285.23:10:31.49#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.23:10:31.49#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.23:10:31.49#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:31.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:10:31.50#abcon#{5=INTERFACE CLEAR} 2006.285.23:10:31.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:10:31.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:10:31.55#ibcon#enter wrdev, iclass 11, count 2 2006.285.23:10:31.55#ibcon#first serial, iclass 11, count 2 2006.285.23:10:31.55#ibcon#enter sib2, iclass 11, count 2 2006.285.23:10:31.55#ibcon#flushed, iclass 11, count 2 2006.285.23:10:31.55#ibcon#about to write, iclass 11, count 2 2006.285.23:10:31.55#ibcon#wrote, iclass 11, count 2 2006.285.23:10:31.55#ibcon#about to read 3, iclass 11, count 2 2006.285.23:10:31.56#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:10:31.57#ibcon#read 3, iclass 11, count 2 2006.285.23:10:31.57#ibcon#about to read 4, iclass 11, count 2 2006.285.23:10:31.57#ibcon#read 4, iclass 11, count 2 2006.285.23:10:31.57#ibcon#about to read 5, iclass 11, count 2 2006.285.23:10:31.57#ibcon#read 5, iclass 11, count 2 2006.285.23:10:31.57#ibcon#about to read 6, iclass 11, count 2 2006.285.23:10:31.57#ibcon#read 6, iclass 11, count 2 2006.285.23:10:31.57#ibcon#end of sib2, iclass 11, count 2 2006.285.23:10:31.57#ibcon#*mode == 0, iclass 11, count 2 2006.285.23:10:31.57#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.23:10:31.57#ibcon#[27=AT03-04\r\n] 2006.285.23:10:31.57#ibcon#*before write, iclass 11, count 2 2006.285.23:10:31.57#ibcon#enter sib2, iclass 11, count 2 2006.285.23:10:31.57#ibcon#flushed, iclass 11, count 2 2006.285.23:10:31.57#ibcon#about to write, iclass 11, count 2 2006.285.23:10:31.57#ibcon#wrote, iclass 11, count 2 2006.285.23:10:31.57#ibcon#about to read 3, iclass 11, count 2 2006.285.23:10:31.60#ibcon#read 3, iclass 11, count 2 2006.285.23:10:31.60#ibcon#about to read 4, iclass 11, count 2 2006.285.23:10:31.60#ibcon#read 4, iclass 11, count 2 2006.285.23:10:31.60#ibcon#about to read 5, iclass 11, count 2 2006.285.23:10:31.60#ibcon#read 5, iclass 11, count 2 2006.285.23:10:31.60#ibcon#about to read 6, iclass 11, count 2 2006.285.23:10:31.60#ibcon#read 6, iclass 11, count 2 2006.285.23:10:31.60#ibcon#end of sib2, iclass 11, count 2 2006.285.23:10:31.60#ibcon#*after write, iclass 11, count 2 2006.285.23:10:31.60#ibcon#*before return 0, iclass 11, count 2 2006.285.23:10:31.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:10:31.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:10:31.60#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.23:10:31.60#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:31.60#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:10:31.72#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:10:31.72#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:10:31.72#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:10:31.72#ibcon#first serial, iclass 11, count 0 2006.285.23:10:31.72#ibcon#enter sib2, iclass 11, count 0 2006.285.23:10:31.72#ibcon#flushed, iclass 11, count 0 2006.285.23:10:31.72#ibcon#about to write, iclass 11, count 0 2006.285.23:10:31.72#ibcon#wrote, iclass 11, count 0 2006.285.23:10:31.72#ibcon#about to read 3, iclass 11, count 0 2006.285.23:10:31.74#ibcon#read 3, iclass 11, count 0 2006.285.23:10:31.74#ibcon#about to read 4, iclass 11, count 0 2006.285.23:10:31.74#ibcon#read 4, iclass 11, count 0 2006.285.23:10:31.74#ibcon#about to read 5, iclass 11, count 0 2006.285.23:10:31.74#ibcon#read 5, iclass 11, count 0 2006.285.23:10:31.74#ibcon#about to read 6, iclass 11, count 0 2006.285.23:10:31.74#ibcon#read 6, iclass 11, count 0 2006.285.23:10:31.74#ibcon#end of sib2, iclass 11, count 0 2006.285.23:10:31.74#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:10:31.74#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:10:31.74#ibcon#[27=USB\r\n] 2006.285.23:10:31.74#ibcon#*before write, iclass 11, count 0 2006.285.23:10:31.74#ibcon#enter sib2, iclass 11, count 0 2006.285.23:10:31.74#ibcon#flushed, iclass 11, count 0 2006.285.23:10:31.74#ibcon#about to write, iclass 11, count 0 2006.285.23:10:31.74#ibcon#wrote, iclass 11, count 0 2006.285.23:10:31.74#ibcon#about to read 3, iclass 11, count 0 2006.285.23:10:31.77#ibcon#read 3, iclass 11, count 0 2006.285.23:10:31.77#ibcon#about to read 4, iclass 11, count 0 2006.285.23:10:31.77#ibcon#read 4, iclass 11, count 0 2006.285.23:10:31.77#ibcon#about to read 5, iclass 11, count 0 2006.285.23:10:31.77#ibcon#read 5, iclass 11, count 0 2006.285.23:10:31.77#ibcon#about to read 6, iclass 11, count 0 2006.285.23:10:31.77#ibcon#read 6, iclass 11, count 0 2006.285.23:10:31.77#ibcon#end of sib2, iclass 11, count 0 2006.285.23:10:31.77#ibcon#*after write, iclass 11, count 0 2006.285.23:10:31.77#ibcon#*before return 0, iclass 11, count 0 2006.285.23:10:31.77#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:10:31.77#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:10:31.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:10:31.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:10:31.77$vck44/vblo=4,679.99 2006.285.23:10:31.77#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.23:10:31.77#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.23:10:31.77#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:31.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:10:31.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:10:31.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:10:31.77#ibcon#enter wrdev, iclass 14, count 0 2006.285.23:10:31.77#ibcon#first serial, iclass 14, count 0 2006.285.23:10:31.77#ibcon#enter sib2, iclass 14, count 0 2006.285.23:10:31.77#ibcon#flushed, iclass 14, count 0 2006.285.23:10:31.77#ibcon#about to write, iclass 14, count 0 2006.285.23:10:31.77#ibcon#wrote, iclass 14, count 0 2006.285.23:10:31.77#ibcon#about to read 3, iclass 14, count 0 2006.285.23:10:31.79#ibcon#read 3, iclass 14, count 0 2006.285.23:10:31.79#ibcon#about to read 4, iclass 14, count 0 2006.285.23:10:31.79#ibcon#read 4, iclass 14, count 0 2006.285.23:10:31.79#ibcon#about to read 5, iclass 14, count 0 2006.285.23:10:31.79#ibcon#read 5, iclass 14, count 0 2006.285.23:10:31.79#ibcon#about to read 6, iclass 14, count 0 2006.285.23:10:31.79#ibcon#read 6, iclass 14, count 0 2006.285.23:10:31.79#ibcon#end of sib2, iclass 14, count 0 2006.285.23:10:31.79#ibcon#*mode == 0, iclass 14, count 0 2006.285.23:10:31.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.23:10:31.79#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:10:31.79#ibcon#*before write, iclass 14, count 0 2006.285.23:10:31.79#ibcon#enter sib2, iclass 14, count 0 2006.285.23:10:31.79#ibcon#flushed, iclass 14, count 0 2006.285.23:10:31.79#ibcon#about to write, iclass 14, count 0 2006.285.23:10:31.79#ibcon#wrote, iclass 14, count 0 2006.285.23:10:31.79#ibcon#about to read 3, iclass 14, count 0 2006.285.23:10:31.83#ibcon#read 3, iclass 14, count 0 2006.285.23:10:31.83#ibcon#about to read 4, iclass 14, count 0 2006.285.23:10:31.83#ibcon#read 4, iclass 14, count 0 2006.285.23:10:31.83#ibcon#about to read 5, iclass 14, count 0 2006.285.23:10:31.83#ibcon#read 5, iclass 14, count 0 2006.285.23:10:31.83#ibcon#about to read 6, iclass 14, count 0 2006.285.23:10:31.83#ibcon#read 6, iclass 14, count 0 2006.285.23:10:31.83#ibcon#end of sib2, iclass 14, count 0 2006.285.23:10:31.83#ibcon#*after write, iclass 14, count 0 2006.285.23:10:31.83#ibcon#*before return 0, iclass 14, count 0 2006.285.23:10:31.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:10:31.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:10:31.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.23:10:31.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.23:10:31.83$vck44/vb=4,5 2006.285.23:10:31.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.23:10:31.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.23:10:31.83#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:31.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:10:31.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:10:31.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:10:31.89#ibcon#enter wrdev, iclass 16, count 2 2006.285.23:10:31.89#ibcon#first serial, iclass 16, count 2 2006.285.23:10:31.89#ibcon#enter sib2, iclass 16, count 2 2006.285.23:10:31.89#ibcon#flushed, iclass 16, count 2 2006.285.23:10:31.89#ibcon#about to write, iclass 16, count 2 2006.285.23:10:31.89#ibcon#wrote, iclass 16, count 2 2006.285.23:10:31.89#ibcon#about to read 3, iclass 16, count 2 2006.285.23:10:31.91#ibcon#read 3, iclass 16, count 2 2006.285.23:10:31.91#ibcon#about to read 4, iclass 16, count 2 2006.285.23:10:31.91#ibcon#read 4, iclass 16, count 2 2006.285.23:10:31.91#ibcon#about to read 5, iclass 16, count 2 2006.285.23:10:31.91#ibcon#read 5, iclass 16, count 2 2006.285.23:10:31.91#ibcon#about to read 6, iclass 16, count 2 2006.285.23:10:31.91#ibcon#read 6, iclass 16, count 2 2006.285.23:10:31.91#ibcon#end of sib2, iclass 16, count 2 2006.285.23:10:31.91#ibcon#*mode == 0, iclass 16, count 2 2006.285.23:10:31.91#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.23:10:31.91#ibcon#[27=AT04-05\r\n] 2006.285.23:10:31.91#ibcon#*before write, iclass 16, count 2 2006.285.23:10:31.91#ibcon#enter sib2, iclass 16, count 2 2006.285.23:10:31.91#ibcon#flushed, iclass 16, count 2 2006.285.23:10:31.91#ibcon#about to write, iclass 16, count 2 2006.285.23:10:31.91#ibcon#wrote, iclass 16, count 2 2006.285.23:10:31.91#ibcon#about to read 3, iclass 16, count 2 2006.285.23:10:31.94#ibcon#read 3, iclass 16, count 2 2006.285.23:10:31.94#ibcon#about to read 4, iclass 16, count 2 2006.285.23:10:31.94#ibcon#read 4, iclass 16, count 2 2006.285.23:10:31.94#ibcon#about to read 5, iclass 16, count 2 2006.285.23:10:31.94#ibcon#read 5, iclass 16, count 2 2006.285.23:10:31.94#ibcon#about to read 6, iclass 16, count 2 2006.285.23:10:31.94#ibcon#read 6, iclass 16, count 2 2006.285.23:10:31.94#ibcon#end of sib2, iclass 16, count 2 2006.285.23:10:31.94#ibcon#*after write, iclass 16, count 2 2006.285.23:10:31.94#ibcon#*before return 0, iclass 16, count 2 2006.285.23:10:31.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:10:31.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:10:31.94#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.23:10:31.94#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:31.94#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:10:32.06#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:10:32.06#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:10:32.06#ibcon#enter wrdev, iclass 16, count 0 2006.285.23:10:32.06#ibcon#first serial, iclass 16, count 0 2006.285.23:10:32.06#ibcon#enter sib2, iclass 16, count 0 2006.285.23:10:32.06#ibcon#flushed, iclass 16, count 0 2006.285.23:10:32.06#ibcon#about to write, iclass 16, count 0 2006.285.23:10:32.06#ibcon#wrote, iclass 16, count 0 2006.285.23:10:32.06#ibcon#about to read 3, iclass 16, count 0 2006.285.23:10:32.08#ibcon#read 3, iclass 16, count 0 2006.285.23:10:32.08#ibcon#about to read 4, iclass 16, count 0 2006.285.23:10:32.08#ibcon#read 4, iclass 16, count 0 2006.285.23:10:32.08#ibcon#about to read 5, iclass 16, count 0 2006.285.23:10:32.08#ibcon#read 5, iclass 16, count 0 2006.285.23:10:32.08#ibcon#about to read 6, iclass 16, count 0 2006.285.23:10:32.08#ibcon#read 6, iclass 16, count 0 2006.285.23:10:32.08#ibcon#end of sib2, iclass 16, count 0 2006.285.23:10:32.08#ibcon#*mode == 0, iclass 16, count 0 2006.285.23:10:32.08#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.23:10:32.08#ibcon#[27=USB\r\n] 2006.285.23:10:32.08#ibcon#*before write, iclass 16, count 0 2006.285.23:10:32.08#ibcon#enter sib2, iclass 16, count 0 2006.285.23:10:32.08#ibcon#flushed, iclass 16, count 0 2006.285.23:10:32.08#ibcon#about to write, iclass 16, count 0 2006.285.23:10:32.08#ibcon#wrote, iclass 16, count 0 2006.285.23:10:32.08#ibcon#about to read 3, iclass 16, count 0 2006.285.23:10:32.11#ibcon#read 3, iclass 16, count 0 2006.285.23:10:32.11#ibcon#about to read 4, iclass 16, count 0 2006.285.23:10:32.11#ibcon#read 4, iclass 16, count 0 2006.285.23:10:32.11#ibcon#about to read 5, iclass 16, count 0 2006.285.23:10:32.11#ibcon#read 5, iclass 16, count 0 2006.285.23:10:32.11#ibcon#about to read 6, iclass 16, count 0 2006.285.23:10:32.11#ibcon#read 6, iclass 16, count 0 2006.285.23:10:32.11#ibcon#end of sib2, iclass 16, count 0 2006.285.23:10:32.11#ibcon#*after write, iclass 16, count 0 2006.285.23:10:32.11#ibcon#*before return 0, iclass 16, count 0 2006.285.23:10:32.11#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:10:32.11#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:10:32.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.23:10:32.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.23:10:32.11$vck44/vblo=5,709.99 2006.285.23:10:32.11#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.23:10:32.11#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.23:10:32.11#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:32.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:10:32.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:10:32.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:10:32.11#ibcon#enter wrdev, iclass 18, count 0 2006.285.23:10:32.11#ibcon#first serial, iclass 18, count 0 2006.285.23:10:32.11#ibcon#enter sib2, iclass 18, count 0 2006.285.23:10:32.11#ibcon#flushed, iclass 18, count 0 2006.285.23:10:32.11#ibcon#about to write, iclass 18, count 0 2006.285.23:10:32.11#ibcon#wrote, iclass 18, count 0 2006.285.23:10:32.11#ibcon#about to read 3, iclass 18, count 0 2006.285.23:10:32.13#ibcon#read 3, iclass 18, count 0 2006.285.23:10:32.13#ibcon#about to read 4, iclass 18, count 0 2006.285.23:10:32.13#ibcon#read 4, iclass 18, count 0 2006.285.23:10:32.13#ibcon#about to read 5, iclass 18, count 0 2006.285.23:10:32.13#ibcon#read 5, iclass 18, count 0 2006.285.23:10:32.13#ibcon#about to read 6, iclass 18, count 0 2006.285.23:10:32.13#ibcon#read 6, iclass 18, count 0 2006.285.23:10:32.13#ibcon#end of sib2, iclass 18, count 0 2006.285.23:10:32.13#ibcon#*mode == 0, iclass 18, count 0 2006.285.23:10:32.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.23:10:32.13#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:10:32.13#ibcon#*before write, iclass 18, count 0 2006.285.23:10:32.13#ibcon#enter sib2, iclass 18, count 0 2006.285.23:10:32.13#ibcon#flushed, iclass 18, count 0 2006.285.23:10:32.13#ibcon#about to write, iclass 18, count 0 2006.285.23:10:32.13#ibcon#wrote, iclass 18, count 0 2006.285.23:10:32.13#ibcon#about to read 3, iclass 18, count 0 2006.285.23:10:32.17#ibcon#read 3, iclass 18, count 0 2006.285.23:10:32.17#ibcon#about to read 4, iclass 18, count 0 2006.285.23:10:32.17#ibcon#read 4, iclass 18, count 0 2006.285.23:10:32.17#ibcon#about to read 5, iclass 18, count 0 2006.285.23:10:32.17#ibcon#read 5, iclass 18, count 0 2006.285.23:10:32.17#ibcon#about to read 6, iclass 18, count 0 2006.285.23:10:32.17#ibcon#read 6, iclass 18, count 0 2006.285.23:10:32.17#ibcon#end of sib2, iclass 18, count 0 2006.285.23:10:32.17#ibcon#*after write, iclass 18, count 0 2006.285.23:10:32.17#ibcon#*before return 0, iclass 18, count 0 2006.285.23:10:32.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:10:32.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:10:32.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.23:10:32.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.23:10:32.17$vck44/vb=5,4 2006.285.23:10:32.17#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.23:10:32.17#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.23:10:32.17#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:32.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:10:32.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:10:32.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:10:32.23#ibcon#enter wrdev, iclass 20, count 2 2006.285.23:10:32.23#ibcon#first serial, iclass 20, count 2 2006.285.23:10:32.23#ibcon#enter sib2, iclass 20, count 2 2006.285.23:10:32.23#ibcon#flushed, iclass 20, count 2 2006.285.23:10:32.23#ibcon#about to write, iclass 20, count 2 2006.285.23:10:32.23#ibcon#wrote, iclass 20, count 2 2006.285.23:10:32.23#ibcon#about to read 3, iclass 20, count 2 2006.285.23:10:32.25#ibcon#read 3, iclass 20, count 2 2006.285.23:10:32.25#ibcon#about to read 4, iclass 20, count 2 2006.285.23:10:32.25#ibcon#read 4, iclass 20, count 2 2006.285.23:10:32.25#ibcon#about to read 5, iclass 20, count 2 2006.285.23:10:32.25#ibcon#read 5, iclass 20, count 2 2006.285.23:10:32.25#ibcon#about to read 6, iclass 20, count 2 2006.285.23:10:32.25#ibcon#read 6, iclass 20, count 2 2006.285.23:10:32.25#ibcon#end of sib2, iclass 20, count 2 2006.285.23:10:32.25#ibcon#*mode == 0, iclass 20, count 2 2006.285.23:10:32.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.23:10:32.25#ibcon#[27=AT05-04\r\n] 2006.285.23:10:32.25#ibcon#*before write, iclass 20, count 2 2006.285.23:10:32.25#ibcon#enter sib2, iclass 20, count 2 2006.285.23:10:32.25#ibcon#flushed, iclass 20, count 2 2006.285.23:10:32.25#ibcon#about to write, iclass 20, count 2 2006.285.23:10:32.25#ibcon#wrote, iclass 20, count 2 2006.285.23:10:32.25#ibcon#about to read 3, iclass 20, count 2 2006.285.23:10:32.28#ibcon#read 3, iclass 20, count 2 2006.285.23:10:32.28#ibcon#about to read 4, iclass 20, count 2 2006.285.23:10:32.28#ibcon#read 4, iclass 20, count 2 2006.285.23:10:32.28#ibcon#about to read 5, iclass 20, count 2 2006.285.23:10:32.28#ibcon#read 5, iclass 20, count 2 2006.285.23:10:32.28#ibcon#about to read 6, iclass 20, count 2 2006.285.23:10:32.28#ibcon#read 6, iclass 20, count 2 2006.285.23:10:32.28#ibcon#end of sib2, iclass 20, count 2 2006.285.23:10:32.28#ibcon#*after write, iclass 20, count 2 2006.285.23:10:32.28#ibcon#*before return 0, iclass 20, count 2 2006.285.23:10:32.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:10:32.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:10:32.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.23:10:32.28#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:32.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:10:32.40#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:10:32.40#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:10:32.40#ibcon#enter wrdev, iclass 20, count 0 2006.285.23:10:32.40#ibcon#first serial, iclass 20, count 0 2006.285.23:10:32.40#ibcon#enter sib2, iclass 20, count 0 2006.285.23:10:32.40#ibcon#flushed, iclass 20, count 0 2006.285.23:10:32.40#ibcon#about to write, iclass 20, count 0 2006.285.23:10:32.40#ibcon#wrote, iclass 20, count 0 2006.285.23:10:32.40#ibcon#about to read 3, iclass 20, count 0 2006.285.23:10:32.42#ibcon#read 3, iclass 20, count 0 2006.285.23:10:32.42#ibcon#about to read 4, iclass 20, count 0 2006.285.23:10:32.42#ibcon#read 4, iclass 20, count 0 2006.285.23:10:32.42#ibcon#about to read 5, iclass 20, count 0 2006.285.23:10:32.42#ibcon#read 5, iclass 20, count 0 2006.285.23:10:32.42#ibcon#about to read 6, iclass 20, count 0 2006.285.23:10:32.42#ibcon#read 6, iclass 20, count 0 2006.285.23:10:32.42#ibcon#end of sib2, iclass 20, count 0 2006.285.23:10:32.42#ibcon#*mode == 0, iclass 20, count 0 2006.285.23:10:32.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.23:10:32.42#ibcon#[27=USB\r\n] 2006.285.23:10:32.42#ibcon#*before write, iclass 20, count 0 2006.285.23:10:32.42#ibcon#enter sib2, iclass 20, count 0 2006.285.23:10:32.42#ibcon#flushed, iclass 20, count 0 2006.285.23:10:32.42#ibcon#about to write, iclass 20, count 0 2006.285.23:10:32.42#ibcon#wrote, iclass 20, count 0 2006.285.23:10:32.42#ibcon#about to read 3, iclass 20, count 0 2006.285.23:10:32.45#ibcon#read 3, iclass 20, count 0 2006.285.23:10:32.45#ibcon#about to read 4, iclass 20, count 0 2006.285.23:10:32.45#ibcon#read 4, iclass 20, count 0 2006.285.23:10:32.45#ibcon#about to read 5, iclass 20, count 0 2006.285.23:10:32.45#ibcon#read 5, iclass 20, count 0 2006.285.23:10:32.45#ibcon#about to read 6, iclass 20, count 0 2006.285.23:10:32.45#ibcon#read 6, iclass 20, count 0 2006.285.23:10:32.45#ibcon#end of sib2, iclass 20, count 0 2006.285.23:10:32.45#ibcon#*after write, iclass 20, count 0 2006.285.23:10:32.45#ibcon#*before return 0, iclass 20, count 0 2006.285.23:10:32.45#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:10:32.45#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:10:32.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.23:10:32.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.23:10:32.45$vck44/vblo=6,719.99 2006.285.23:10:32.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.23:10:32.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.23:10:32.45#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:32.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:10:32.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:10:32.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:10:32.45#ibcon#enter wrdev, iclass 22, count 0 2006.285.23:10:32.45#ibcon#first serial, iclass 22, count 0 2006.285.23:10:32.45#ibcon#enter sib2, iclass 22, count 0 2006.285.23:10:32.45#ibcon#flushed, iclass 22, count 0 2006.285.23:10:32.45#ibcon#about to write, iclass 22, count 0 2006.285.23:10:32.45#ibcon#wrote, iclass 22, count 0 2006.285.23:10:32.45#ibcon#about to read 3, iclass 22, count 0 2006.285.23:10:32.47#ibcon#read 3, iclass 22, count 0 2006.285.23:10:32.47#ibcon#about to read 4, iclass 22, count 0 2006.285.23:10:32.47#ibcon#read 4, iclass 22, count 0 2006.285.23:10:32.47#ibcon#about to read 5, iclass 22, count 0 2006.285.23:10:32.47#ibcon#read 5, iclass 22, count 0 2006.285.23:10:32.47#ibcon#about to read 6, iclass 22, count 0 2006.285.23:10:32.47#ibcon#read 6, iclass 22, count 0 2006.285.23:10:32.47#ibcon#end of sib2, iclass 22, count 0 2006.285.23:10:32.47#ibcon#*mode == 0, iclass 22, count 0 2006.285.23:10:32.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.23:10:32.47#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:10:32.47#ibcon#*before write, iclass 22, count 0 2006.285.23:10:32.47#ibcon#enter sib2, iclass 22, count 0 2006.285.23:10:32.47#ibcon#flushed, iclass 22, count 0 2006.285.23:10:32.47#ibcon#about to write, iclass 22, count 0 2006.285.23:10:32.47#ibcon#wrote, iclass 22, count 0 2006.285.23:10:32.47#ibcon#about to read 3, iclass 22, count 0 2006.285.23:10:32.51#ibcon#read 3, iclass 22, count 0 2006.285.23:10:32.51#ibcon#about to read 4, iclass 22, count 0 2006.285.23:10:32.51#ibcon#read 4, iclass 22, count 0 2006.285.23:10:32.51#ibcon#about to read 5, iclass 22, count 0 2006.285.23:10:32.51#ibcon#read 5, iclass 22, count 0 2006.285.23:10:32.51#ibcon#about to read 6, iclass 22, count 0 2006.285.23:10:32.51#ibcon#read 6, iclass 22, count 0 2006.285.23:10:32.51#ibcon#end of sib2, iclass 22, count 0 2006.285.23:10:32.51#ibcon#*after write, iclass 22, count 0 2006.285.23:10:32.51#ibcon#*before return 0, iclass 22, count 0 2006.285.23:10:32.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:10:32.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:10:32.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.23:10:32.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.23:10:32.51$vck44/vb=6,3 2006.285.23:10:32.51#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.23:10:32.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.23:10:32.51#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:32.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:10:32.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:10:32.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:10:32.57#ibcon#enter wrdev, iclass 24, count 2 2006.285.23:10:32.57#ibcon#first serial, iclass 24, count 2 2006.285.23:10:32.57#ibcon#enter sib2, iclass 24, count 2 2006.285.23:10:32.57#ibcon#flushed, iclass 24, count 2 2006.285.23:10:32.57#ibcon#about to write, iclass 24, count 2 2006.285.23:10:32.57#ibcon#wrote, iclass 24, count 2 2006.285.23:10:32.57#ibcon#about to read 3, iclass 24, count 2 2006.285.23:10:32.59#ibcon#read 3, iclass 24, count 2 2006.285.23:10:32.59#ibcon#about to read 4, iclass 24, count 2 2006.285.23:10:32.59#ibcon#read 4, iclass 24, count 2 2006.285.23:10:32.59#ibcon#about to read 5, iclass 24, count 2 2006.285.23:10:32.59#ibcon#read 5, iclass 24, count 2 2006.285.23:10:32.59#ibcon#about to read 6, iclass 24, count 2 2006.285.23:10:32.59#ibcon#read 6, iclass 24, count 2 2006.285.23:10:32.59#ibcon#end of sib2, iclass 24, count 2 2006.285.23:10:32.59#ibcon#*mode == 0, iclass 24, count 2 2006.285.23:10:32.59#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.23:10:32.59#ibcon#[27=AT06-03\r\n] 2006.285.23:10:32.59#ibcon#*before write, iclass 24, count 2 2006.285.23:10:32.59#ibcon#enter sib2, iclass 24, count 2 2006.285.23:10:32.59#ibcon#flushed, iclass 24, count 2 2006.285.23:10:32.59#ibcon#about to write, iclass 24, count 2 2006.285.23:10:32.59#ibcon#wrote, iclass 24, count 2 2006.285.23:10:32.59#ibcon#about to read 3, iclass 24, count 2 2006.285.23:10:32.62#ibcon#read 3, iclass 24, count 2 2006.285.23:10:32.62#ibcon#about to read 4, iclass 24, count 2 2006.285.23:10:32.62#ibcon#read 4, iclass 24, count 2 2006.285.23:10:32.62#ibcon#about to read 5, iclass 24, count 2 2006.285.23:10:32.62#ibcon#read 5, iclass 24, count 2 2006.285.23:10:32.62#ibcon#about to read 6, iclass 24, count 2 2006.285.23:10:32.62#ibcon#read 6, iclass 24, count 2 2006.285.23:10:32.62#ibcon#end of sib2, iclass 24, count 2 2006.285.23:10:32.62#ibcon#*after write, iclass 24, count 2 2006.285.23:10:32.62#ibcon#*before return 0, iclass 24, count 2 2006.285.23:10:32.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:10:32.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:10:32.62#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.23:10:32.62#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:32.62#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:10:32.74#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:10:32.74#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:10:32.74#ibcon#enter wrdev, iclass 24, count 0 2006.285.23:10:32.74#ibcon#first serial, iclass 24, count 0 2006.285.23:10:32.74#ibcon#enter sib2, iclass 24, count 0 2006.285.23:10:32.74#ibcon#flushed, iclass 24, count 0 2006.285.23:10:32.74#ibcon#about to write, iclass 24, count 0 2006.285.23:10:32.74#ibcon#wrote, iclass 24, count 0 2006.285.23:10:32.74#ibcon#about to read 3, iclass 24, count 0 2006.285.23:10:32.76#ibcon#read 3, iclass 24, count 0 2006.285.23:10:32.76#ibcon#about to read 4, iclass 24, count 0 2006.285.23:10:32.76#ibcon#read 4, iclass 24, count 0 2006.285.23:10:32.76#ibcon#about to read 5, iclass 24, count 0 2006.285.23:10:32.76#ibcon#read 5, iclass 24, count 0 2006.285.23:10:32.76#ibcon#about to read 6, iclass 24, count 0 2006.285.23:10:32.76#ibcon#read 6, iclass 24, count 0 2006.285.23:10:32.76#ibcon#end of sib2, iclass 24, count 0 2006.285.23:10:32.76#ibcon#*mode == 0, iclass 24, count 0 2006.285.23:10:32.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.23:10:32.76#ibcon#[27=USB\r\n] 2006.285.23:10:32.76#ibcon#*before write, iclass 24, count 0 2006.285.23:10:32.76#ibcon#enter sib2, iclass 24, count 0 2006.285.23:10:32.76#ibcon#flushed, iclass 24, count 0 2006.285.23:10:32.76#ibcon#about to write, iclass 24, count 0 2006.285.23:10:32.76#ibcon#wrote, iclass 24, count 0 2006.285.23:10:32.76#ibcon#about to read 3, iclass 24, count 0 2006.285.23:10:32.79#ibcon#read 3, iclass 24, count 0 2006.285.23:10:32.79#ibcon#about to read 4, iclass 24, count 0 2006.285.23:10:32.79#ibcon#read 4, iclass 24, count 0 2006.285.23:10:32.79#ibcon#about to read 5, iclass 24, count 0 2006.285.23:10:32.79#ibcon#read 5, iclass 24, count 0 2006.285.23:10:32.79#ibcon#about to read 6, iclass 24, count 0 2006.285.23:10:32.79#ibcon#read 6, iclass 24, count 0 2006.285.23:10:32.79#ibcon#end of sib2, iclass 24, count 0 2006.285.23:10:32.79#ibcon#*after write, iclass 24, count 0 2006.285.23:10:32.79#ibcon#*before return 0, iclass 24, count 0 2006.285.23:10:32.79#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:10:32.79#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:10:32.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.23:10:32.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.23:10:32.79$vck44/vblo=7,734.99 2006.285.23:10:32.79#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.23:10:32.79#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.23:10:32.79#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:32.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:10:32.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:10:32.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:10:32.79#ibcon#enter wrdev, iclass 26, count 0 2006.285.23:10:32.79#ibcon#first serial, iclass 26, count 0 2006.285.23:10:32.79#ibcon#enter sib2, iclass 26, count 0 2006.285.23:10:32.79#ibcon#flushed, iclass 26, count 0 2006.285.23:10:32.79#ibcon#about to write, iclass 26, count 0 2006.285.23:10:32.79#ibcon#wrote, iclass 26, count 0 2006.285.23:10:32.79#ibcon#about to read 3, iclass 26, count 0 2006.285.23:10:32.81#ibcon#read 3, iclass 26, count 0 2006.285.23:10:32.81#ibcon#about to read 4, iclass 26, count 0 2006.285.23:10:32.81#ibcon#read 4, iclass 26, count 0 2006.285.23:10:32.81#ibcon#about to read 5, iclass 26, count 0 2006.285.23:10:32.81#ibcon#read 5, iclass 26, count 0 2006.285.23:10:32.81#ibcon#about to read 6, iclass 26, count 0 2006.285.23:10:32.81#ibcon#read 6, iclass 26, count 0 2006.285.23:10:32.81#ibcon#end of sib2, iclass 26, count 0 2006.285.23:10:32.81#ibcon#*mode == 0, iclass 26, count 0 2006.285.23:10:32.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.23:10:32.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:10:32.81#ibcon#*before write, iclass 26, count 0 2006.285.23:10:32.81#ibcon#enter sib2, iclass 26, count 0 2006.285.23:10:32.81#ibcon#flushed, iclass 26, count 0 2006.285.23:10:32.81#ibcon#about to write, iclass 26, count 0 2006.285.23:10:32.81#ibcon#wrote, iclass 26, count 0 2006.285.23:10:32.81#ibcon#about to read 3, iclass 26, count 0 2006.285.23:10:32.85#ibcon#read 3, iclass 26, count 0 2006.285.23:10:32.85#ibcon#about to read 4, iclass 26, count 0 2006.285.23:10:32.85#ibcon#read 4, iclass 26, count 0 2006.285.23:10:32.85#ibcon#about to read 5, iclass 26, count 0 2006.285.23:10:32.85#ibcon#read 5, iclass 26, count 0 2006.285.23:10:32.85#ibcon#about to read 6, iclass 26, count 0 2006.285.23:10:32.85#ibcon#read 6, iclass 26, count 0 2006.285.23:10:32.85#ibcon#end of sib2, iclass 26, count 0 2006.285.23:10:32.85#ibcon#*after write, iclass 26, count 0 2006.285.23:10:32.85#ibcon#*before return 0, iclass 26, count 0 2006.285.23:10:32.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:10:32.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:10:32.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.23:10:32.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.23:10:32.85$vck44/vb=7,4 2006.285.23:10:32.85#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.23:10:32.85#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.23:10:32.85#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:32.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:10:32.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:10:32.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:10:32.91#ibcon#enter wrdev, iclass 28, count 2 2006.285.23:10:32.91#ibcon#first serial, iclass 28, count 2 2006.285.23:10:32.91#ibcon#enter sib2, iclass 28, count 2 2006.285.23:10:32.91#ibcon#flushed, iclass 28, count 2 2006.285.23:10:32.91#ibcon#about to write, iclass 28, count 2 2006.285.23:10:32.91#ibcon#wrote, iclass 28, count 2 2006.285.23:10:32.91#ibcon#about to read 3, iclass 28, count 2 2006.285.23:10:32.93#ibcon#read 3, iclass 28, count 2 2006.285.23:10:32.93#ibcon#about to read 4, iclass 28, count 2 2006.285.23:10:32.93#ibcon#read 4, iclass 28, count 2 2006.285.23:10:32.93#ibcon#about to read 5, iclass 28, count 2 2006.285.23:10:32.93#ibcon#read 5, iclass 28, count 2 2006.285.23:10:32.93#ibcon#about to read 6, iclass 28, count 2 2006.285.23:10:32.93#ibcon#read 6, iclass 28, count 2 2006.285.23:10:32.93#ibcon#end of sib2, iclass 28, count 2 2006.285.23:10:32.93#ibcon#*mode == 0, iclass 28, count 2 2006.285.23:10:32.93#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.23:10:32.93#ibcon#[27=AT07-04\r\n] 2006.285.23:10:32.93#ibcon#*before write, iclass 28, count 2 2006.285.23:10:32.93#ibcon#enter sib2, iclass 28, count 2 2006.285.23:10:32.93#ibcon#flushed, iclass 28, count 2 2006.285.23:10:32.93#ibcon#about to write, iclass 28, count 2 2006.285.23:10:32.93#ibcon#wrote, iclass 28, count 2 2006.285.23:10:32.93#ibcon#about to read 3, iclass 28, count 2 2006.285.23:10:32.96#ibcon#read 3, iclass 28, count 2 2006.285.23:10:32.96#ibcon#about to read 4, iclass 28, count 2 2006.285.23:10:32.96#ibcon#read 4, iclass 28, count 2 2006.285.23:10:32.96#ibcon#about to read 5, iclass 28, count 2 2006.285.23:10:32.96#ibcon#read 5, iclass 28, count 2 2006.285.23:10:32.96#ibcon#about to read 6, iclass 28, count 2 2006.285.23:10:32.96#ibcon#read 6, iclass 28, count 2 2006.285.23:10:32.96#ibcon#end of sib2, iclass 28, count 2 2006.285.23:10:32.96#ibcon#*after write, iclass 28, count 2 2006.285.23:10:32.96#ibcon#*before return 0, iclass 28, count 2 2006.285.23:10:32.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:10:32.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:10:32.96#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.23:10:32.96#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:32.96#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:10:33.08#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:10:33.08#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:10:33.08#ibcon#enter wrdev, iclass 28, count 0 2006.285.23:10:33.08#ibcon#first serial, iclass 28, count 0 2006.285.23:10:33.08#ibcon#enter sib2, iclass 28, count 0 2006.285.23:10:33.08#ibcon#flushed, iclass 28, count 0 2006.285.23:10:33.08#ibcon#about to write, iclass 28, count 0 2006.285.23:10:33.08#ibcon#wrote, iclass 28, count 0 2006.285.23:10:33.08#ibcon#about to read 3, iclass 28, count 0 2006.285.23:10:33.10#ibcon#read 3, iclass 28, count 0 2006.285.23:10:33.10#ibcon#about to read 4, iclass 28, count 0 2006.285.23:10:33.10#ibcon#read 4, iclass 28, count 0 2006.285.23:10:33.10#ibcon#about to read 5, iclass 28, count 0 2006.285.23:10:33.10#ibcon#read 5, iclass 28, count 0 2006.285.23:10:33.10#ibcon#about to read 6, iclass 28, count 0 2006.285.23:10:33.10#ibcon#read 6, iclass 28, count 0 2006.285.23:10:33.10#ibcon#end of sib2, iclass 28, count 0 2006.285.23:10:33.10#ibcon#*mode == 0, iclass 28, count 0 2006.285.23:10:33.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.23:10:33.10#ibcon#[27=USB\r\n] 2006.285.23:10:33.10#ibcon#*before write, iclass 28, count 0 2006.285.23:10:33.10#ibcon#enter sib2, iclass 28, count 0 2006.285.23:10:33.10#ibcon#flushed, iclass 28, count 0 2006.285.23:10:33.10#ibcon#about to write, iclass 28, count 0 2006.285.23:10:33.10#ibcon#wrote, iclass 28, count 0 2006.285.23:10:33.10#ibcon#about to read 3, iclass 28, count 0 2006.285.23:10:33.13#ibcon#read 3, iclass 28, count 0 2006.285.23:10:33.13#ibcon#about to read 4, iclass 28, count 0 2006.285.23:10:33.13#ibcon#read 4, iclass 28, count 0 2006.285.23:10:33.13#ibcon#about to read 5, iclass 28, count 0 2006.285.23:10:33.13#ibcon#read 5, iclass 28, count 0 2006.285.23:10:33.13#ibcon#about to read 6, iclass 28, count 0 2006.285.23:10:33.13#ibcon#read 6, iclass 28, count 0 2006.285.23:10:33.13#ibcon#end of sib2, iclass 28, count 0 2006.285.23:10:33.13#ibcon#*after write, iclass 28, count 0 2006.285.23:10:33.13#ibcon#*before return 0, iclass 28, count 0 2006.285.23:10:33.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:10:33.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:10:33.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.23:10:33.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.23:10:33.13$vck44/vblo=8,744.99 2006.285.23:10:33.13#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.23:10:33.13#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.23:10:33.13#ibcon#ireg 17 cls_cnt 0 2006.285.23:10:33.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:10:33.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:10:33.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:10:33.13#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:10:33.13#ibcon#first serial, iclass 30, count 0 2006.285.23:10:33.13#ibcon#enter sib2, iclass 30, count 0 2006.285.23:10:33.13#ibcon#flushed, iclass 30, count 0 2006.285.23:10:33.13#ibcon#about to write, iclass 30, count 0 2006.285.23:10:33.13#ibcon#wrote, iclass 30, count 0 2006.285.23:10:33.13#ibcon#about to read 3, iclass 30, count 0 2006.285.23:10:33.15#ibcon#read 3, iclass 30, count 0 2006.285.23:10:33.15#ibcon#about to read 4, iclass 30, count 0 2006.285.23:10:33.15#ibcon#read 4, iclass 30, count 0 2006.285.23:10:33.15#ibcon#about to read 5, iclass 30, count 0 2006.285.23:10:33.15#ibcon#read 5, iclass 30, count 0 2006.285.23:10:33.15#ibcon#about to read 6, iclass 30, count 0 2006.285.23:10:33.15#ibcon#read 6, iclass 30, count 0 2006.285.23:10:33.15#ibcon#end of sib2, iclass 30, count 0 2006.285.23:10:33.15#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:10:33.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:10:33.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:10:33.15#ibcon#*before write, iclass 30, count 0 2006.285.23:10:33.15#ibcon#enter sib2, iclass 30, count 0 2006.285.23:10:33.15#ibcon#flushed, iclass 30, count 0 2006.285.23:10:33.15#ibcon#about to write, iclass 30, count 0 2006.285.23:10:33.15#ibcon#wrote, iclass 30, count 0 2006.285.23:10:33.15#ibcon#about to read 3, iclass 30, count 0 2006.285.23:10:33.19#ibcon#read 3, iclass 30, count 0 2006.285.23:10:33.19#ibcon#about to read 4, iclass 30, count 0 2006.285.23:10:33.19#ibcon#read 4, iclass 30, count 0 2006.285.23:10:33.19#ibcon#about to read 5, iclass 30, count 0 2006.285.23:10:33.19#ibcon#read 5, iclass 30, count 0 2006.285.23:10:33.19#ibcon#about to read 6, iclass 30, count 0 2006.285.23:10:33.19#ibcon#read 6, iclass 30, count 0 2006.285.23:10:33.19#ibcon#end of sib2, iclass 30, count 0 2006.285.23:10:33.19#ibcon#*after write, iclass 30, count 0 2006.285.23:10:33.19#ibcon#*before return 0, iclass 30, count 0 2006.285.23:10:33.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:10:33.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:10:33.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:10:33.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:10:33.19$vck44/vb=8,4 2006.285.23:10:33.19#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.23:10:33.19#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.23:10:33.19#ibcon#ireg 11 cls_cnt 2 2006.285.23:10:33.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:10:33.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:10:33.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:10:33.25#ibcon#enter wrdev, iclass 32, count 2 2006.285.23:10:33.25#ibcon#first serial, iclass 32, count 2 2006.285.23:10:33.25#ibcon#enter sib2, iclass 32, count 2 2006.285.23:10:33.25#ibcon#flushed, iclass 32, count 2 2006.285.23:10:33.25#ibcon#about to write, iclass 32, count 2 2006.285.23:10:33.25#ibcon#wrote, iclass 32, count 2 2006.285.23:10:33.25#ibcon#about to read 3, iclass 32, count 2 2006.285.23:10:33.27#ibcon#read 3, iclass 32, count 2 2006.285.23:10:33.27#ibcon#about to read 4, iclass 32, count 2 2006.285.23:10:33.27#ibcon#read 4, iclass 32, count 2 2006.285.23:10:33.27#ibcon#about to read 5, iclass 32, count 2 2006.285.23:10:33.27#ibcon#read 5, iclass 32, count 2 2006.285.23:10:33.27#ibcon#about to read 6, iclass 32, count 2 2006.285.23:10:33.27#ibcon#read 6, iclass 32, count 2 2006.285.23:10:33.27#ibcon#end of sib2, iclass 32, count 2 2006.285.23:10:33.27#ibcon#*mode == 0, iclass 32, count 2 2006.285.23:10:33.27#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.23:10:33.27#ibcon#[27=AT08-04\r\n] 2006.285.23:10:33.27#ibcon#*before write, iclass 32, count 2 2006.285.23:10:33.27#ibcon#enter sib2, iclass 32, count 2 2006.285.23:10:33.27#ibcon#flushed, iclass 32, count 2 2006.285.23:10:33.27#ibcon#about to write, iclass 32, count 2 2006.285.23:10:33.27#ibcon#wrote, iclass 32, count 2 2006.285.23:10:33.27#ibcon#about to read 3, iclass 32, count 2 2006.285.23:10:33.30#ibcon#read 3, iclass 32, count 2 2006.285.23:10:33.30#ibcon#about to read 4, iclass 32, count 2 2006.285.23:10:33.30#ibcon#read 4, iclass 32, count 2 2006.285.23:10:33.30#ibcon#about to read 5, iclass 32, count 2 2006.285.23:10:33.30#ibcon#read 5, iclass 32, count 2 2006.285.23:10:33.30#ibcon#about to read 6, iclass 32, count 2 2006.285.23:10:33.30#ibcon#read 6, iclass 32, count 2 2006.285.23:10:33.30#ibcon#end of sib2, iclass 32, count 2 2006.285.23:10:33.30#ibcon#*after write, iclass 32, count 2 2006.285.23:10:33.30#ibcon#*before return 0, iclass 32, count 2 2006.285.23:10:33.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:10:33.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:10:33.30#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.23:10:33.30#ibcon#ireg 7 cls_cnt 0 2006.285.23:10:33.30#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:10:33.42#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:10:33.42#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:10:33.42#ibcon#enter wrdev, iclass 32, count 0 2006.285.23:10:33.42#ibcon#first serial, iclass 32, count 0 2006.285.23:10:33.42#ibcon#enter sib2, iclass 32, count 0 2006.285.23:10:33.42#ibcon#flushed, iclass 32, count 0 2006.285.23:10:33.42#ibcon#about to write, iclass 32, count 0 2006.285.23:10:33.42#ibcon#wrote, iclass 32, count 0 2006.285.23:10:33.42#ibcon#about to read 3, iclass 32, count 0 2006.285.23:10:33.44#ibcon#read 3, iclass 32, count 0 2006.285.23:10:33.44#ibcon#about to read 4, iclass 32, count 0 2006.285.23:10:33.44#ibcon#read 4, iclass 32, count 0 2006.285.23:10:33.44#ibcon#about to read 5, iclass 32, count 0 2006.285.23:10:33.44#ibcon#read 5, iclass 32, count 0 2006.285.23:10:33.44#ibcon#about to read 6, iclass 32, count 0 2006.285.23:10:33.44#ibcon#read 6, iclass 32, count 0 2006.285.23:10:33.44#ibcon#end of sib2, iclass 32, count 0 2006.285.23:10:33.44#ibcon#*mode == 0, iclass 32, count 0 2006.285.23:10:33.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.23:10:33.44#ibcon#[27=USB\r\n] 2006.285.23:10:33.44#ibcon#*before write, iclass 32, count 0 2006.285.23:10:33.44#ibcon#enter sib2, iclass 32, count 0 2006.285.23:10:33.44#ibcon#flushed, iclass 32, count 0 2006.285.23:10:33.44#ibcon#about to write, iclass 32, count 0 2006.285.23:10:33.44#ibcon#wrote, iclass 32, count 0 2006.285.23:10:33.44#ibcon#about to read 3, iclass 32, count 0 2006.285.23:10:33.47#ibcon#read 3, iclass 32, count 0 2006.285.23:10:33.47#ibcon#about to read 4, iclass 32, count 0 2006.285.23:10:33.47#ibcon#read 4, iclass 32, count 0 2006.285.23:10:33.47#ibcon#about to read 5, iclass 32, count 0 2006.285.23:10:33.47#ibcon#read 5, iclass 32, count 0 2006.285.23:10:33.47#ibcon#about to read 6, iclass 32, count 0 2006.285.23:10:33.47#ibcon#read 6, iclass 32, count 0 2006.285.23:10:33.47#ibcon#end of sib2, iclass 32, count 0 2006.285.23:10:33.47#ibcon#*after write, iclass 32, count 0 2006.285.23:10:33.47#ibcon#*before return 0, iclass 32, count 0 2006.285.23:10:33.47#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:10:33.47#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:10:33.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.23:10:33.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.23:10:33.47$vck44/vabw=wide 2006.285.23:10:33.47#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.23:10:33.47#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.23:10:33.47#ibcon#ireg 8 cls_cnt 0 2006.285.23:10:33.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:10:33.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:10:33.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:10:33.47#ibcon#enter wrdev, iclass 34, count 0 2006.285.23:10:33.47#ibcon#first serial, iclass 34, count 0 2006.285.23:10:33.47#ibcon#enter sib2, iclass 34, count 0 2006.285.23:10:33.47#ibcon#flushed, iclass 34, count 0 2006.285.23:10:33.47#ibcon#about to write, iclass 34, count 0 2006.285.23:10:33.47#ibcon#wrote, iclass 34, count 0 2006.285.23:10:33.47#ibcon#about to read 3, iclass 34, count 0 2006.285.23:10:33.49#ibcon#read 3, iclass 34, count 0 2006.285.23:10:33.49#ibcon#about to read 4, iclass 34, count 0 2006.285.23:10:33.49#ibcon#read 4, iclass 34, count 0 2006.285.23:10:33.49#ibcon#about to read 5, iclass 34, count 0 2006.285.23:10:33.49#ibcon#read 5, iclass 34, count 0 2006.285.23:10:33.49#ibcon#about to read 6, iclass 34, count 0 2006.285.23:10:33.49#ibcon#read 6, iclass 34, count 0 2006.285.23:10:33.49#ibcon#end of sib2, iclass 34, count 0 2006.285.23:10:33.49#ibcon#*mode == 0, iclass 34, count 0 2006.285.23:10:33.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.23:10:33.49#ibcon#[25=BW32\r\n] 2006.285.23:10:33.49#ibcon#*before write, iclass 34, count 0 2006.285.23:10:33.49#ibcon#enter sib2, iclass 34, count 0 2006.285.23:10:33.49#ibcon#flushed, iclass 34, count 0 2006.285.23:10:33.49#ibcon#about to write, iclass 34, count 0 2006.285.23:10:33.49#ibcon#wrote, iclass 34, count 0 2006.285.23:10:33.49#ibcon#about to read 3, iclass 34, count 0 2006.285.23:10:33.52#ibcon#read 3, iclass 34, count 0 2006.285.23:10:33.52#ibcon#about to read 4, iclass 34, count 0 2006.285.23:10:33.52#ibcon#read 4, iclass 34, count 0 2006.285.23:10:33.52#ibcon#about to read 5, iclass 34, count 0 2006.285.23:10:33.52#ibcon#read 5, iclass 34, count 0 2006.285.23:10:33.52#ibcon#about to read 6, iclass 34, count 0 2006.285.23:10:33.52#ibcon#read 6, iclass 34, count 0 2006.285.23:10:33.52#ibcon#end of sib2, iclass 34, count 0 2006.285.23:10:33.52#ibcon#*after write, iclass 34, count 0 2006.285.23:10:33.52#ibcon#*before return 0, iclass 34, count 0 2006.285.23:10:33.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:10:33.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:10:33.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.23:10:33.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.23:10:33.52$vck44/vbbw=wide 2006.285.23:10:33.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.23:10:33.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.23:10:33.52#ibcon#ireg 8 cls_cnt 0 2006.285.23:10:33.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:10:33.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:10:33.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:10:33.59#ibcon#enter wrdev, iclass 36, count 0 2006.285.23:10:33.59#ibcon#first serial, iclass 36, count 0 2006.285.23:10:33.59#ibcon#enter sib2, iclass 36, count 0 2006.285.23:10:33.59#ibcon#flushed, iclass 36, count 0 2006.285.23:10:33.59#ibcon#about to write, iclass 36, count 0 2006.285.23:10:33.59#ibcon#wrote, iclass 36, count 0 2006.285.23:10:33.59#ibcon#about to read 3, iclass 36, count 0 2006.285.23:10:33.61#ibcon#read 3, iclass 36, count 0 2006.285.23:10:33.61#ibcon#about to read 4, iclass 36, count 0 2006.285.23:10:33.61#ibcon#read 4, iclass 36, count 0 2006.285.23:10:33.61#ibcon#about to read 5, iclass 36, count 0 2006.285.23:10:33.61#ibcon#read 5, iclass 36, count 0 2006.285.23:10:33.61#ibcon#about to read 6, iclass 36, count 0 2006.285.23:10:33.61#ibcon#read 6, iclass 36, count 0 2006.285.23:10:33.61#ibcon#end of sib2, iclass 36, count 0 2006.285.23:10:33.61#ibcon#*mode == 0, iclass 36, count 0 2006.285.23:10:33.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.23:10:33.61#ibcon#[27=BW32\r\n] 2006.285.23:10:33.61#ibcon#*before write, iclass 36, count 0 2006.285.23:10:33.61#ibcon#enter sib2, iclass 36, count 0 2006.285.23:10:33.61#ibcon#flushed, iclass 36, count 0 2006.285.23:10:33.61#ibcon#about to write, iclass 36, count 0 2006.285.23:10:33.61#ibcon#wrote, iclass 36, count 0 2006.285.23:10:33.61#ibcon#about to read 3, iclass 36, count 0 2006.285.23:10:33.64#ibcon#read 3, iclass 36, count 0 2006.285.23:10:33.64#ibcon#about to read 4, iclass 36, count 0 2006.285.23:10:33.64#ibcon#read 4, iclass 36, count 0 2006.285.23:10:33.64#ibcon#about to read 5, iclass 36, count 0 2006.285.23:10:33.64#ibcon#read 5, iclass 36, count 0 2006.285.23:10:33.64#ibcon#about to read 6, iclass 36, count 0 2006.285.23:10:33.64#ibcon#read 6, iclass 36, count 0 2006.285.23:10:33.64#ibcon#end of sib2, iclass 36, count 0 2006.285.23:10:33.64#ibcon#*after write, iclass 36, count 0 2006.285.23:10:33.64#ibcon#*before return 0, iclass 36, count 0 2006.285.23:10:33.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:10:33.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:10:33.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.23:10:33.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.23:10:33.64$setupk4/ifdk4 2006.285.23:10:33.64$ifdk4/lo= 2006.285.23:10:33.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:10:33.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:10:33.64$ifdk4/patch= 2006.285.23:10:33.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:10:33.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:10:33.65$setupk4/!*+20s 2006.285.23:10:41.65#abcon#<5=/03 3.1 7.5 18.87 891016.4\r\n> 2006.285.23:10:41.67#abcon#{5=INTERFACE CLEAR} 2006.285.23:10:41.73#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:10:48.16$setupk4/"tpicd 2006.285.23:10:48.16$setupk4/echo=off 2006.285.23:10:48.16$setupk4/xlog=off 2006.285.23:10:48.16:!2006.285.23:23:02 2006.285.23:11:09.14#trakl#Source acquired 2006.285.23:11:10.14#flagr#flagr/antenna,acquired 2006.285.23:23:02.00:preob 2006.285.23:23:02.14/onsource/TRACKING 2006.285.23:23:02.14:!2006.285.23:23:12 2006.285.23:23:12.00:"tape 2006.285.23:23:12.00:"st=record 2006.285.23:23:12.00:data_valid=on 2006.285.23:23:12.00:midob 2006.285.23:23:13.14/onsource/TRACKING 2006.285.23:23:13.14/wx/19.22,1016.4,88 2006.285.23:23:13.27/cable/+6.5105E-03 2006.285.23:23:14.36/va/01,07,usb,yes,32,35 2006.285.23:23:14.36/va/02,06,usb,yes,32,33 2006.285.23:23:14.36/va/03,07,usb,yes,32,33 2006.285.23:23:14.36/va/04,06,usb,yes,33,35 2006.285.23:23:14.36/va/05,03,usb,yes,33,33 2006.285.23:23:14.36/va/06,04,usb,yes,29,29 2006.285.23:23:14.36/va/07,04,usb,yes,30,31 2006.285.23:23:14.36/va/08,03,usb,yes,31,37 2006.285.23:23:14.59/valo/01,524.99,yes,locked 2006.285.23:23:14.59/valo/02,534.99,yes,locked 2006.285.23:23:14.59/valo/03,564.99,yes,locked 2006.285.23:23:14.59/valo/04,624.99,yes,locked 2006.285.23:23:14.59/valo/05,734.99,yes,locked 2006.285.23:23:14.59/valo/06,814.99,yes,locked 2006.285.23:23:14.59/valo/07,864.99,yes,locked 2006.285.23:23:14.59/valo/08,884.99,yes,locked 2006.285.23:23:15.68/vb/01,04,usb,yes,31,28 2006.285.23:23:15.68/vb/02,05,usb,yes,29,29 2006.285.23:23:15.68/vb/03,04,usb,yes,30,33 2006.285.23:23:15.68/vb/04,05,usb,yes,30,29 2006.285.23:23:15.68/vb/05,04,usb,yes,26,29 2006.285.23:23:15.68/vb/06,03,usb,yes,38,34 2006.285.23:23:15.68/vb/07,04,usb,yes,31,31 2006.285.23:23:15.68/vb/08,04,usb,yes,28,32 2006.285.23:23:15.91/vblo/01,629.99,yes,locked 2006.285.23:23:15.91/vblo/02,634.99,yes,locked 2006.285.23:23:15.91/vblo/03,649.99,yes,locked 2006.285.23:23:15.91/vblo/04,679.99,yes,locked 2006.285.23:23:15.91/vblo/05,709.99,yes,locked 2006.285.23:23:15.91/vblo/06,719.99,yes,locked 2006.285.23:23:15.91/vblo/07,734.99,yes,locked 2006.285.23:23:15.91/vblo/08,744.99,yes,locked 2006.285.23:23:16.06/vabw/8 2006.285.23:23:16.21/vbbw/8 2006.285.23:23:16.30/xfe/off,on,12.0 2006.285.23:23:16.68/ifatt/23,28,28,28 2006.285.23:23:17.08/fmout-gps/S +2.65E-07 2006.285.23:23:17.10:!2006.285.23:24:02 2006.285.23:24:02.00:data_valid=off 2006.285.23:24:02.00:"et 2006.285.23:24:02.00:!+3s 2006.285.23:24:05.01:"tape 2006.285.23:24:05.01:postob 2006.285.23:24:05.07/cable/+6.5102E-03 2006.285.23:24:05.07/wx/19.23,1016.4,89 2006.285.23:24:06.08/fmout-gps/S +2.66E-07 2006.285.23:24:06.08:scan_name=285-2326,jd0610,150 2006.285.23:24:06.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.285.23:24:07.14#flagr#flagr/antenna,new-source 2006.285.23:24:07.14:checkk5 2006.285.23:24:07.59/chk_autoobs//k5ts1/ autoobs is running! 2006.285.23:24:07.99/chk_autoobs//k5ts2/ autoobs is running! 2006.285.23:24:08.39/chk_autoobs//k5ts3/ autoobs is running! 2006.285.23:24:08.80/chk_autoobs//k5ts4/ autoobs is running! 2006.285.23:24:09.18/chk_obsdata//k5ts1/T2852323??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.23:24:09.53/chk_obsdata//k5ts2/T2852323??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.23:24:09.99/chk_obsdata//k5ts3/T2852323??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.23:24:10.41/chk_obsdata//k5ts4/T2852323??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.285.23:24:11.20/k5log//k5ts1_log_newline 2006.285.23:24:11.95/k5log//k5ts2_log_newline 2006.285.23:24:12.78/k5log//k5ts3_log_newline 2006.285.23:24:13.53/k5log//k5ts4_log_newline 2006.285.23:24:13.56/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.23:24:13.56:setupk4=1 2006.285.23:24:13.56$setupk4/echo=on 2006.285.23:24:13.56$setupk4/pcalon 2006.285.23:24:13.56$pcalon/"no phase cal control is implemented here 2006.285.23:24:13.56$setupk4/"tpicd=stop 2006.285.23:24:13.56$setupk4/"rec=synch_on 2006.285.23:24:13.56$setupk4/"rec_mode=128 2006.285.23:24:13.56$setupk4/!* 2006.285.23:24:13.56$setupk4/recpk4 2006.285.23:24:13.56$recpk4/recpatch= 2006.285.23:24:13.56$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.23:24:13.56$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.23:24:13.56$setupk4/vck44 2006.285.23:24:13.56$vck44/valo=1,524.99 2006.285.23:24:13.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.23:24:13.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.23:24:13.57#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:13.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:24:13.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:24:13.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:24:13.57#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:24:13.57#ibcon#first serial, iclass 37, count 0 2006.285.23:24:13.57#ibcon#enter sib2, iclass 37, count 0 2006.285.23:24:13.57#ibcon#flushed, iclass 37, count 0 2006.285.23:24:13.57#ibcon#about to write, iclass 37, count 0 2006.285.23:24:13.57#ibcon#wrote, iclass 37, count 0 2006.285.23:24:13.57#ibcon#about to read 3, iclass 37, count 0 2006.285.23:24:13.58#ibcon#read 3, iclass 37, count 0 2006.285.23:24:13.58#ibcon#about to read 4, iclass 37, count 0 2006.285.23:24:13.58#ibcon#read 4, iclass 37, count 0 2006.285.23:24:13.58#ibcon#about to read 5, iclass 37, count 0 2006.285.23:24:13.58#ibcon#read 5, iclass 37, count 0 2006.285.23:24:13.58#ibcon#about to read 6, iclass 37, count 0 2006.285.23:24:13.58#ibcon#read 6, iclass 37, count 0 2006.285.23:24:13.58#ibcon#end of sib2, iclass 37, count 0 2006.285.23:24:13.58#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:24:13.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:24:13.58#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.23:24:13.58#ibcon#*before write, iclass 37, count 0 2006.285.23:24:13.58#ibcon#enter sib2, iclass 37, count 0 2006.285.23:24:13.58#ibcon#flushed, iclass 37, count 0 2006.285.23:24:13.58#ibcon#about to write, iclass 37, count 0 2006.285.23:24:13.58#ibcon#wrote, iclass 37, count 0 2006.285.23:24:13.58#ibcon#about to read 3, iclass 37, count 0 2006.285.23:24:13.63#ibcon#read 3, iclass 37, count 0 2006.285.23:24:13.63#ibcon#about to read 4, iclass 37, count 0 2006.285.23:24:13.63#ibcon#read 4, iclass 37, count 0 2006.285.23:24:13.63#ibcon#about to read 5, iclass 37, count 0 2006.285.23:24:13.63#ibcon#read 5, iclass 37, count 0 2006.285.23:24:13.63#ibcon#about to read 6, iclass 37, count 0 2006.285.23:24:13.63#ibcon#read 6, iclass 37, count 0 2006.285.23:24:13.63#ibcon#end of sib2, iclass 37, count 0 2006.285.23:24:13.63#ibcon#*after write, iclass 37, count 0 2006.285.23:24:13.63#ibcon#*before return 0, iclass 37, count 0 2006.285.23:24:13.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:24:13.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:24:13.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:24:13.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:24:13.63$vck44/va=1,7 2006.285.23:24:13.63#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.23:24:13.63#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.23:24:13.63#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:13.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:24:13.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:24:13.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:24:13.63#ibcon#enter wrdev, iclass 39, count 2 2006.285.23:24:13.63#ibcon#first serial, iclass 39, count 2 2006.285.23:24:13.63#ibcon#enter sib2, iclass 39, count 2 2006.285.23:24:13.63#ibcon#flushed, iclass 39, count 2 2006.285.23:24:13.63#ibcon#about to write, iclass 39, count 2 2006.285.23:24:13.63#ibcon#wrote, iclass 39, count 2 2006.285.23:24:13.63#ibcon#about to read 3, iclass 39, count 2 2006.285.23:24:13.65#ibcon#read 3, iclass 39, count 2 2006.285.23:24:13.65#ibcon#about to read 4, iclass 39, count 2 2006.285.23:24:13.65#ibcon#read 4, iclass 39, count 2 2006.285.23:24:13.65#ibcon#about to read 5, iclass 39, count 2 2006.285.23:24:13.65#ibcon#read 5, iclass 39, count 2 2006.285.23:24:13.65#ibcon#about to read 6, iclass 39, count 2 2006.285.23:24:13.65#ibcon#read 6, iclass 39, count 2 2006.285.23:24:13.65#ibcon#end of sib2, iclass 39, count 2 2006.285.23:24:13.65#ibcon#*mode == 0, iclass 39, count 2 2006.285.23:24:13.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.23:24:13.65#ibcon#[25=AT01-07\r\n] 2006.285.23:24:13.65#ibcon#*before write, iclass 39, count 2 2006.285.23:24:13.65#ibcon#enter sib2, iclass 39, count 2 2006.285.23:24:13.65#ibcon#flushed, iclass 39, count 2 2006.285.23:24:13.65#ibcon#about to write, iclass 39, count 2 2006.285.23:24:13.65#ibcon#wrote, iclass 39, count 2 2006.285.23:24:13.65#ibcon#about to read 3, iclass 39, count 2 2006.285.23:24:13.68#ibcon#read 3, iclass 39, count 2 2006.285.23:24:13.68#ibcon#about to read 4, iclass 39, count 2 2006.285.23:24:13.68#ibcon#read 4, iclass 39, count 2 2006.285.23:24:13.68#ibcon#about to read 5, iclass 39, count 2 2006.285.23:24:13.68#ibcon#read 5, iclass 39, count 2 2006.285.23:24:13.68#ibcon#about to read 6, iclass 39, count 2 2006.285.23:24:13.68#ibcon#read 6, iclass 39, count 2 2006.285.23:24:13.68#ibcon#end of sib2, iclass 39, count 2 2006.285.23:24:13.68#ibcon#*after write, iclass 39, count 2 2006.285.23:24:13.68#ibcon#*before return 0, iclass 39, count 2 2006.285.23:24:13.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:24:13.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:24:13.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.23:24:13.68#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:13.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:24:13.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:24:13.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:24:13.80#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:24:13.80#ibcon#first serial, iclass 39, count 0 2006.285.23:24:13.80#ibcon#enter sib2, iclass 39, count 0 2006.285.23:24:13.80#ibcon#flushed, iclass 39, count 0 2006.285.23:24:13.80#ibcon#about to write, iclass 39, count 0 2006.285.23:24:13.80#ibcon#wrote, iclass 39, count 0 2006.285.23:24:13.80#ibcon#about to read 3, iclass 39, count 0 2006.285.23:24:13.82#ibcon#read 3, iclass 39, count 0 2006.285.23:24:13.82#ibcon#about to read 4, iclass 39, count 0 2006.285.23:24:13.82#ibcon#read 4, iclass 39, count 0 2006.285.23:24:13.82#ibcon#about to read 5, iclass 39, count 0 2006.285.23:24:13.82#ibcon#read 5, iclass 39, count 0 2006.285.23:24:13.82#ibcon#about to read 6, iclass 39, count 0 2006.285.23:24:13.82#ibcon#read 6, iclass 39, count 0 2006.285.23:24:13.82#ibcon#end of sib2, iclass 39, count 0 2006.285.23:24:13.82#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:24:13.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:24:13.82#ibcon#[25=USB\r\n] 2006.285.23:24:13.82#ibcon#*before write, iclass 39, count 0 2006.285.23:24:13.82#ibcon#enter sib2, iclass 39, count 0 2006.285.23:24:13.82#ibcon#flushed, iclass 39, count 0 2006.285.23:24:13.82#ibcon#about to write, iclass 39, count 0 2006.285.23:24:13.82#ibcon#wrote, iclass 39, count 0 2006.285.23:24:13.82#ibcon#about to read 3, iclass 39, count 0 2006.285.23:24:13.85#ibcon#read 3, iclass 39, count 0 2006.285.23:24:13.85#ibcon#about to read 4, iclass 39, count 0 2006.285.23:24:13.85#ibcon#read 4, iclass 39, count 0 2006.285.23:24:13.85#ibcon#about to read 5, iclass 39, count 0 2006.285.23:24:13.85#ibcon#read 5, iclass 39, count 0 2006.285.23:24:13.85#ibcon#about to read 6, iclass 39, count 0 2006.285.23:24:13.85#ibcon#read 6, iclass 39, count 0 2006.285.23:24:13.85#ibcon#end of sib2, iclass 39, count 0 2006.285.23:24:13.85#ibcon#*after write, iclass 39, count 0 2006.285.23:24:13.85#ibcon#*before return 0, iclass 39, count 0 2006.285.23:24:13.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:24:13.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:24:13.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:24:13.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:24:13.85$vck44/valo=2,534.99 2006.285.23:24:13.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.23:24:13.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.23:24:13.85#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:13.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:24:13.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:24:13.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:24:13.85#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:24:13.85#ibcon#first serial, iclass 3, count 0 2006.285.23:24:13.85#ibcon#enter sib2, iclass 3, count 0 2006.285.23:24:13.85#ibcon#flushed, iclass 3, count 0 2006.285.23:24:13.85#ibcon#about to write, iclass 3, count 0 2006.285.23:24:13.85#ibcon#wrote, iclass 3, count 0 2006.285.23:24:13.85#ibcon#about to read 3, iclass 3, count 0 2006.285.23:24:13.87#ibcon#read 3, iclass 3, count 0 2006.285.23:24:13.87#ibcon#about to read 4, iclass 3, count 0 2006.285.23:24:13.87#ibcon#read 4, iclass 3, count 0 2006.285.23:24:13.87#ibcon#about to read 5, iclass 3, count 0 2006.285.23:24:13.87#ibcon#read 5, iclass 3, count 0 2006.285.23:24:13.87#ibcon#about to read 6, iclass 3, count 0 2006.285.23:24:13.87#ibcon#read 6, iclass 3, count 0 2006.285.23:24:13.87#ibcon#end of sib2, iclass 3, count 0 2006.285.23:24:13.87#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:24:13.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:24:13.87#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.23:24:13.87#ibcon#*before write, iclass 3, count 0 2006.285.23:24:13.87#ibcon#enter sib2, iclass 3, count 0 2006.285.23:24:13.87#ibcon#flushed, iclass 3, count 0 2006.285.23:24:13.87#ibcon#about to write, iclass 3, count 0 2006.285.23:24:13.87#ibcon#wrote, iclass 3, count 0 2006.285.23:24:13.87#ibcon#about to read 3, iclass 3, count 0 2006.285.23:24:13.91#ibcon#read 3, iclass 3, count 0 2006.285.23:24:13.91#ibcon#about to read 4, iclass 3, count 0 2006.285.23:24:13.91#ibcon#read 4, iclass 3, count 0 2006.285.23:24:13.91#ibcon#about to read 5, iclass 3, count 0 2006.285.23:24:13.91#ibcon#read 5, iclass 3, count 0 2006.285.23:24:13.91#ibcon#about to read 6, iclass 3, count 0 2006.285.23:24:13.91#ibcon#read 6, iclass 3, count 0 2006.285.23:24:13.91#ibcon#end of sib2, iclass 3, count 0 2006.285.23:24:13.91#ibcon#*after write, iclass 3, count 0 2006.285.23:24:13.91#ibcon#*before return 0, iclass 3, count 0 2006.285.23:24:13.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:24:13.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:24:13.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:24:13.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:24:13.91$vck44/va=2,6 2006.285.23:24:13.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.23:24:13.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.23:24:13.91#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:13.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:24:13.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:24:13.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:24:13.97#ibcon#enter wrdev, iclass 5, count 2 2006.285.23:24:13.97#ibcon#first serial, iclass 5, count 2 2006.285.23:24:13.97#ibcon#enter sib2, iclass 5, count 2 2006.285.23:24:13.97#ibcon#flushed, iclass 5, count 2 2006.285.23:24:13.97#ibcon#about to write, iclass 5, count 2 2006.285.23:24:13.97#ibcon#wrote, iclass 5, count 2 2006.285.23:24:13.97#ibcon#about to read 3, iclass 5, count 2 2006.285.23:24:13.99#ibcon#read 3, iclass 5, count 2 2006.285.23:24:13.99#ibcon#about to read 4, iclass 5, count 2 2006.285.23:24:13.99#ibcon#read 4, iclass 5, count 2 2006.285.23:24:13.99#ibcon#about to read 5, iclass 5, count 2 2006.285.23:24:13.99#ibcon#read 5, iclass 5, count 2 2006.285.23:24:13.99#ibcon#about to read 6, iclass 5, count 2 2006.285.23:24:13.99#ibcon#read 6, iclass 5, count 2 2006.285.23:24:13.99#ibcon#end of sib2, iclass 5, count 2 2006.285.23:24:13.99#ibcon#*mode == 0, iclass 5, count 2 2006.285.23:24:13.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.23:24:13.99#ibcon#[25=AT02-06\r\n] 2006.285.23:24:13.99#ibcon#*before write, iclass 5, count 2 2006.285.23:24:13.99#ibcon#enter sib2, iclass 5, count 2 2006.285.23:24:13.99#ibcon#flushed, iclass 5, count 2 2006.285.23:24:13.99#ibcon#about to write, iclass 5, count 2 2006.285.23:24:13.99#ibcon#wrote, iclass 5, count 2 2006.285.23:24:13.99#ibcon#about to read 3, iclass 5, count 2 2006.285.23:24:14.02#ibcon#read 3, iclass 5, count 2 2006.285.23:24:14.02#ibcon#about to read 4, iclass 5, count 2 2006.285.23:24:14.02#ibcon#read 4, iclass 5, count 2 2006.285.23:24:14.02#ibcon#about to read 5, iclass 5, count 2 2006.285.23:24:14.02#ibcon#read 5, iclass 5, count 2 2006.285.23:24:14.02#ibcon#about to read 6, iclass 5, count 2 2006.285.23:24:14.02#ibcon#read 6, iclass 5, count 2 2006.285.23:24:14.02#ibcon#end of sib2, iclass 5, count 2 2006.285.23:24:14.02#ibcon#*after write, iclass 5, count 2 2006.285.23:24:14.02#ibcon#*before return 0, iclass 5, count 2 2006.285.23:24:14.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:24:14.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:24:14.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.23:24:14.02#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:14.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:24:14.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:24:14.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:24:14.14#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:24:14.14#ibcon#first serial, iclass 5, count 0 2006.285.23:24:14.14#ibcon#enter sib2, iclass 5, count 0 2006.285.23:24:14.14#ibcon#flushed, iclass 5, count 0 2006.285.23:24:14.14#ibcon#about to write, iclass 5, count 0 2006.285.23:24:14.14#ibcon#wrote, iclass 5, count 0 2006.285.23:24:14.14#ibcon#about to read 3, iclass 5, count 0 2006.285.23:24:14.16#ibcon#read 3, iclass 5, count 0 2006.285.23:24:14.16#ibcon#about to read 4, iclass 5, count 0 2006.285.23:24:14.16#ibcon#read 4, iclass 5, count 0 2006.285.23:24:14.16#ibcon#about to read 5, iclass 5, count 0 2006.285.23:24:14.16#ibcon#read 5, iclass 5, count 0 2006.285.23:24:14.16#ibcon#about to read 6, iclass 5, count 0 2006.285.23:24:14.16#ibcon#read 6, iclass 5, count 0 2006.285.23:24:14.16#ibcon#end of sib2, iclass 5, count 0 2006.285.23:24:14.16#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:24:14.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:24:14.16#ibcon#[25=USB\r\n] 2006.285.23:24:14.16#ibcon#*before write, iclass 5, count 0 2006.285.23:24:14.16#ibcon#enter sib2, iclass 5, count 0 2006.285.23:24:14.16#ibcon#flushed, iclass 5, count 0 2006.285.23:24:14.16#ibcon#about to write, iclass 5, count 0 2006.285.23:24:14.16#ibcon#wrote, iclass 5, count 0 2006.285.23:24:14.16#ibcon#about to read 3, iclass 5, count 0 2006.285.23:24:14.19#ibcon#read 3, iclass 5, count 0 2006.285.23:24:14.19#ibcon#about to read 4, iclass 5, count 0 2006.285.23:24:14.19#ibcon#read 4, iclass 5, count 0 2006.285.23:24:14.19#ibcon#about to read 5, iclass 5, count 0 2006.285.23:24:14.19#ibcon#read 5, iclass 5, count 0 2006.285.23:24:14.19#ibcon#about to read 6, iclass 5, count 0 2006.285.23:24:14.19#ibcon#read 6, iclass 5, count 0 2006.285.23:24:14.19#ibcon#end of sib2, iclass 5, count 0 2006.285.23:24:14.19#ibcon#*after write, iclass 5, count 0 2006.285.23:24:14.19#ibcon#*before return 0, iclass 5, count 0 2006.285.23:24:14.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:24:14.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:24:14.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:24:14.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:24:14.19$vck44/valo=3,564.99 2006.285.23:24:14.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.23:24:14.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.23:24:14.19#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:14.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:24:14.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:24:14.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:24:14.19#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:24:14.19#ibcon#first serial, iclass 7, count 0 2006.285.23:24:14.19#ibcon#enter sib2, iclass 7, count 0 2006.285.23:24:14.19#ibcon#flushed, iclass 7, count 0 2006.285.23:24:14.19#ibcon#about to write, iclass 7, count 0 2006.285.23:24:14.19#ibcon#wrote, iclass 7, count 0 2006.285.23:24:14.19#ibcon#about to read 3, iclass 7, count 0 2006.285.23:24:14.21#ibcon#read 3, iclass 7, count 0 2006.285.23:24:14.21#ibcon#about to read 4, iclass 7, count 0 2006.285.23:24:14.21#ibcon#read 4, iclass 7, count 0 2006.285.23:24:14.21#ibcon#about to read 5, iclass 7, count 0 2006.285.23:24:14.21#ibcon#read 5, iclass 7, count 0 2006.285.23:24:14.21#ibcon#about to read 6, iclass 7, count 0 2006.285.23:24:14.21#ibcon#read 6, iclass 7, count 0 2006.285.23:24:14.21#ibcon#end of sib2, iclass 7, count 0 2006.285.23:24:14.21#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:24:14.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:24:14.21#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.23:24:14.21#ibcon#*before write, iclass 7, count 0 2006.285.23:24:14.21#ibcon#enter sib2, iclass 7, count 0 2006.285.23:24:14.21#ibcon#flushed, iclass 7, count 0 2006.285.23:24:14.21#ibcon#about to write, iclass 7, count 0 2006.285.23:24:14.21#ibcon#wrote, iclass 7, count 0 2006.285.23:24:14.21#ibcon#about to read 3, iclass 7, count 0 2006.285.23:24:14.25#ibcon#read 3, iclass 7, count 0 2006.285.23:24:14.25#ibcon#about to read 4, iclass 7, count 0 2006.285.23:24:14.25#ibcon#read 4, iclass 7, count 0 2006.285.23:24:14.25#ibcon#about to read 5, iclass 7, count 0 2006.285.23:24:14.25#ibcon#read 5, iclass 7, count 0 2006.285.23:24:14.25#ibcon#about to read 6, iclass 7, count 0 2006.285.23:24:14.25#ibcon#read 6, iclass 7, count 0 2006.285.23:24:14.25#ibcon#end of sib2, iclass 7, count 0 2006.285.23:24:14.25#ibcon#*after write, iclass 7, count 0 2006.285.23:24:14.25#ibcon#*before return 0, iclass 7, count 0 2006.285.23:24:14.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:24:14.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:24:14.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:24:14.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:24:14.25$vck44/va=3,7 2006.285.23:24:14.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.23:24:14.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.23:24:14.25#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:14.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:24:14.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:24:14.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:24:14.31#ibcon#enter wrdev, iclass 11, count 2 2006.285.23:24:14.31#ibcon#first serial, iclass 11, count 2 2006.285.23:24:14.31#ibcon#enter sib2, iclass 11, count 2 2006.285.23:24:14.31#ibcon#flushed, iclass 11, count 2 2006.285.23:24:14.31#ibcon#about to write, iclass 11, count 2 2006.285.23:24:14.31#ibcon#wrote, iclass 11, count 2 2006.285.23:24:14.31#ibcon#about to read 3, iclass 11, count 2 2006.285.23:24:14.33#ibcon#read 3, iclass 11, count 2 2006.285.23:24:14.33#ibcon#about to read 4, iclass 11, count 2 2006.285.23:24:14.33#ibcon#read 4, iclass 11, count 2 2006.285.23:24:14.33#ibcon#about to read 5, iclass 11, count 2 2006.285.23:24:14.33#ibcon#read 5, iclass 11, count 2 2006.285.23:24:14.33#ibcon#about to read 6, iclass 11, count 2 2006.285.23:24:14.33#ibcon#read 6, iclass 11, count 2 2006.285.23:24:14.33#ibcon#end of sib2, iclass 11, count 2 2006.285.23:24:14.33#ibcon#*mode == 0, iclass 11, count 2 2006.285.23:24:14.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.23:24:14.33#ibcon#[25=AT03-07\r\n] 2006.285.23:24:14.33#ibcon#*before write, iclass 11, count 2 2006.285.23:24:14.33#ibcon#enter sib2, iclass 11, count 2 2006.285.23:24:14.33#ibcon#flushed, iclass 11, count 2 2006.285.23:24:14.33#ibcon#about to write, iclass 11, count 2 2006.285.23:24:14.33#ibcon#wrote, iclass 11, count 2 2006.285.23:24:14.33#ibcon#about to read 3, iclass 11, count 2 2006.285.23:24:14.36#ibcon#read 3, iclass 11, count 2 2006.285.23:24:14.36#ibcon#about to read 4, iclass 11, count 2 2006.285.23:24:14.36#ibcon#read 4, iclass 11, count 2 2006.285.23:24:14.36#ibcon#about to read 5, iclass 11, count 2 2006.285.23:24:14.36#ibcon#read 5, iclass 11, count 2 2006.285.23:24:14.36#ibcon#about to read 6, iclass 11, count 2 2006.285.23:24:14.36#ibcon#read 6, iclass 11, count 2 2006.285.23:24:14.36#ibcon#end of sib2, iclass 11, count 2 2006.285.23:24:14.36#ibcon#*after write, iclass 11, count 2 2006.285.23:24:14.36#ibcon#*before return 0, iclass 11, count 2 2006.285.23:24:14.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:24:14.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:24:14.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.23:24:14.36#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:14.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:24:14.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:24:14.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:24:14.48#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:24:14.48#ibcon#first serial, iclass 11, count 0 2006.285.23:24:14.48#ibcon#enter sib2, iclass 11, count 0 2006.285.23:24:14.48#ibcon#flushed, iclass 11, count 0 2006.285.23:24:14.48#ibcon#about to write, iclass 11, count 0 2006.285.23:24:14.48#ibcon#wrote, iclass 11, count 0 2006.285.23:24:14.48#ibcon#about to read 3, iclass 11, count 0 2006.285.23:24:14.50#ibcon#read 3, iclass 11, count 0 2006.285.23:24:14.50#ibcon#about to read 4, iclass 11, count 0 2006.285.23:24:14.50#ibcon#read 4, iclass 11, count 0 2006.285.23:24:14.50#ibcon#about to read 5, iclass 11, count 0 2006.285.23:24:14.50#ibcon#read 5, iclass 11, count 0 2006.285.23:24:14.50#ibcon#about to read 6, iclass 11, count 0 2006.285.23:24:14.50#ibcon#read 6, iclass 11, count 0 2006.285.23:24:14.50#ibcon#end of sib2, iclass 11, count 0 2006.285.23:24:14.50#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:24:14.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:24:14.50#ibcon#[25=USB\r\n] 2006.285.23:24:14.50#ibcon#*before write, iclass 11, count 0 2006.285.23:24:14.50#ibcon#enter sib2, iclass 11, count 0 2006.285.23:24:14.50#ibcon#flushed, iclass 11, count 0 2006.285.23:24:14.50#ibcon#about to write, iclass 11, count 0 2006.285.23:24:14.50#ibcon#wrote, iclass 11, count 0 2006.285.23:24:14.50#ibcon#about to read 3, iclass 11, count 0 2006.285.23:24:14.53#ibcon#read 3, iclass 11, count 0 2006.285.23:24:14.53#ibcon#about to read 4, iclass 11, count 0 2006.285.23:24:14.53#ibcon#read 4, iclass 11, count 0 2006.285.23:24:14.53#ibcon#about to read 5, iclass 11, count 0 2006.285.23:24:14.53#ibcon#read 5, iclass 11, count 0 2006.285.23:24:14.53#ibcon#about to read 6, iclass 11, count 0 2006.285.23:24:14.53#ibcon#read 6, iclass 11, count 0 2006.285.23:24:14.53#ibcon#end of sib2, iclass 11, count 0 2006.285.23:24:14.53#ibcon#*after write, iclass 11, count 0 2006.285.23:24:14.53#ibcon#*before return 0, iclass 11, count 0 2006.285.23:24:14.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:24:14.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:24:14.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:24:14.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:24:14.53$vck44/valo=4,624.99 2006.285.23:24:14.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.23:24:14.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.23:24:14.53#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:14.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:24:14.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:24:14.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:24:14.53#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:24:14.53#ibcon#first serial, iclass 13, count 0 2006.285.23:24:14.53#ibcon#enter sib2, iclass 13, count 0 2006.285.23:24:14.53#ibcon#flushed, iclass 13, count 0 2006.285.23:24:14.53#ibcon#about to write, iclass 13, count 0 2006.285.23:24:14.53#ibcon#wrote, iclass 13, count 0 2006.285.23:24:14.53#ibcon#about to read 3, iclass 13, count 0 2006.285.23:24:14.55#ibcon#read 3, iclass 13, count 0 2006.285.23:24:14.55#ibcon#about to read 4, iclass 13, count 0 2006.285.23:24:14.55#ibcon#read 4, iclass 13, count 0 2006.285.23:24:14.55#ibcon#about to read 5, iclass 13, count 0 2006.285.23:24:14.55#ibcon#read 5, iclass 13, count 0 2006.285.23:24:14.55#ibcon#about to read 6, iclass 13, count 0 2006.285.23:24:14.55#ibcon#read 6, iclass 13, count 0 2006.285.23:24:14.55#ibcon#end of sib2, iclass 13, count 0 2006.285.23:24:14.55#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:24:14.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:24:14.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.23:24:14.55#ibcon#*before write, iclass 13, count 0 2006.285.23:24:14.55#ibcon#enter sib2, iclass 13, count 0 2006.285.23:24:14.55#ibcon#flushed, iclass 13, count 0 2006.285.23:24:14.55#ibcon#about to write, iclass 13, count 0 2006.285.23:24:14.55#ibcon#wrote, iclass 13, count 0 2006.285.23:24:14.55#ibcon#about to read 3, iclass 13, count 0 2006.285.23:24:14.59#ibcon#read 3, iclass 13, count 0 2006.285.23:24:14.59#ibcon#about to read 4, iclass 13, count 0 2006.285.23:24:14.59#ibcon#read 4, iclass 13, count 0 2006.285.23:24:14.59#ibcon#about to read 5, iclass 13, count 0 2006.285.23:24:14.59#ibcon#read 5, iclass 13, count 0 2006.285.23:24:14.59#ibcon#about to read 6, iclass 13, count 0 2006.285.23:24:14.59#ibcon#read 6, iclass 13, count 0 2006.285.23:24:14.59#ibcon#end of sib2, iclass 13, count 0 2006.285.23:24:14.59#ibcon#*after write, iclass 13, count 0 2006.285.23:24:14.59#ibcon#*before return 0, iclass 13, count 0 2006.285.23:24:14.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:24:14.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:24:14.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:24:14.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:24:14.59$vck44/va=4,6 2006.285.23:24:14.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.23:24:14.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.23:24:14.59#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:14.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:24:14.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:24:14.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:24:14.65#ibcon#enter wrdev, iclass 15, count 2 2006.285.23:24:14.65#ibcon#first serial, iclass 15, count 2 2006.285.23:24:14.65#ibcon#enter sib2, iclass 15, count 2 2006.285.23:24:14.65#ibcon#flushed, iclass 15, count 2 2006.285.23:24:14.65#ibcon#about to write, iclass 15, count 2 2006.285.23:24:14.65#ibcon#wrote, iclass 15, count 2 2006.285.23:24:14.65#ibcon#about to read 3, iclass 15, count 2 2006.285.23:24:14.67#ibcon#read 3, iclass 15, count 2 2006.285.23:24:14.67#ibcon#about to read 4, iclass 15, count 2 2006.285.23:24:14.67#ibcon#read 4, iclass 15, count 2 2006.285.23:24:14.67#ibcon#about to read 5, iclass 15, count 2 2006.285.23:24:14.67#ibcon#read 5, iclass 15, count 2 2006.285.23:24:14.67#ibcon#about to read 6, iclass 15, count 2 2006.285.23:24:14.67#ibcon#read 6, iclass 15, count 2 2006.285.23:24:14.67#ibcon#end of sib2, iclass 15, count 2 2006.285.23:24:14.67#ibcon#*mode == 0, iclass 15, count 2 2006.285.23:24:14.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.23:24:14.67#ibcon#[25=AT04-06\r\n] 2006.285.23:24:14.67#ibcon#*before write, iclass 15, count 2 2006.285.23:24:14.67#ibcon#enter sib2, iclass 15, count 2 2006.285.23:24:14.67#ibcon#flushed, iclass 15, count 2 2006.285.23:24:14.67#ibcon#about to write, iclass 15, count 2 2006.285.23:24:14.67#ibcon#wrote, iclass 15, count 2 2006.285.23:24:14.67#ibcon#about to read 3, iclass 15, count 2 2006.285.23:24:14.70#ibcon#read 3, iclass 15, count 2 2006.285.23:24:14.70#ibcon#about to read 4, iclass 15, count 2 2006.285.23:24:14.70#ibcon#read 4, iclass 15, count 2 2006.285.23:24:14.70#ibcon#about to read 5, iclass 15, count 2 2006.285.23:24:14.70#ibcon#read 5, iclass 15, count 2 2006.285.23:24:14.70#ibcon#about to read 6, iclass 15, count 2 2006.285.23:24:14.70#ibcon#read 6, iclass 15, count 2 2006.285.23:24:14.70#ibcon#end of sib2, iclass 15, count 2 2006.285.23:24:14.70#ibcon#*after write, iclass 15, count 2 2006.285.23:24:14.70#ibcon#*before return 0, iclass 15, count 2 2006.285.23:24:14.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:24:14.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:24:14.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.23:24:14.70#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:14.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:24:14.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:24:14.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:24:14.82#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:24:14.82#ibcon#first serial, iclass 15, count 0 2006.285.23:24:14.82#ibcon#enter sib2, iclass 15, count 0 2006.285.23:24:14.82#ibcon#flushed, iclass 15, count 0 2006.285.23:24:14.82#ibcon#about to write, iclass 15, count 0 2006.285.23:24:14.82#ibcon#wrote, iclass 15, count 0 2006.285.23:24:14.82#ibcon#about to read 3, iclass 15, count 0 2006.285.23:24:14.84#ibcon#read 3, iclass 15, count 0 2006.285.23:24:14.84#ibcon#about to read 4, iclass 15, count 0 2006.285.23:24:14.84#ibcon#read 4, iclass 15, count 0 2006.285.23:24:14.84#ibcon#about to read 5, iclass 15, count 0 2006.285.23:24:14.84#ibcon#read 5, iclass 15, count 0 2006.285.23:24:14.84#ibcon#about to read 6, iclass 15, count 0 2006.285.23:24:14.84#ibcon#read 6, iclass 15, count 0 2006.285.23:24:14.84#ibcon#end of sib2, iclass 15, count 0 2006.285.23:24:14.84#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:24:14.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:24:14.84#ibcon#[25=USB\r\n] 2006.285.23:24:14.84#ibcon#*before write, iclass 15, count 0 2006.285.23:24:14.84#ibcon#enter sib2, iclass 15, count 0 2006.285.23:24:14.84#ibcon#flushed, iclass 15, count 0 2006.285.23:24:14.84#ibcon#about to write, iclass 15, count 0 2006.285.23:24:14.84#ibcon#wrote, iclass 15, count 0 2006.285.23:24:14.84#ibcon#about to read 3, iclass 15, count 0 2006.285.23:24:14.87#ibcon#read 3, iclass 15, count 0 2006.285.23:24:14.87#ibcon#about to read 4, iclass 15, count 0 2006.285.23:24:14.87#ibcon#read 4, iclass 15, count 0 2006.285.23:24:14.87#ibcon#about to read 5, iclass 15, count 0 2006.285.23:24:14.87#ibcon#read 5, iclass 15, count 0 2006.285.23:24:14.87#ibcon#about to read 6, iclass 15, count 0 2006.285.23:24:14.87#ibcon#read 6, iclass 15, count 0 2006.285.23:24:14.87#ibcon#end of sib2, iclass 15, count 0 2006.285.23:24:14.87#ibcon#*after write, iclass 15, count 0 2006.285.23:24:14.87#ibcon#*before return 0, iclass 15, count 0 2006.285.23:24:14.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:24:14.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:24:14.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:24:14.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:24:14.87$vck44/valo=5,734.99 2006.285.23:24:14.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.23:24:14.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.23:24:14.87#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:14.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:24:14.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:24:14.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:24:14.87#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:24:14.87#ibcon#first serial, iclass 17, count 0 2006.285.23:24:14.87#ibcon#enter sib2, iclass 17, count 0 2006.285.23:24:14.87#ibcon#flushed, iclass 17, count 0 2006.285.23:24:14.87#ibcon#about to write, iclass 17, count 0 2006.285.23:24:14.87#ibcon#wrote, iclass 17, count 0 2006.285.23:24:14.87#ibcon#about to read 3, iclass 17, count 0 2006.285.23:24:14.89#ibcon#read 3, iclass 17, count 0 2006.285.23:24:14.89#ibcon#about to read 4, iclass 17, count 0 2006.285.23:24:14.89#ibcon#read 4, iclass 17, count 0 2006.285.23:24:14.89#ibcon#about to read 5, iclass 17, count 0 2006.285.23:24:14.89#ibcon#read 5, iclass 17, count 0 2006.285.23:24:14.89#ibcon#about to read 6, iclass 17, count 0 2006.285.23:24:14.89#ibcon#read 6, iclass 17, count 0 2006.285.23:24:14.89#ibcon#end of sib2, iclass 17, count 0 2006.285.23:24:14.89#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:24:14.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:24:14.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.23:24:14.89#ibcon#*before write, iclass 17, count 0 2006.285.23:24:14.89#ibcon#enter sib2, iclass 17, count 0 2006.285.23:24:14.89#ibcon#flushed, iclass 17, count 0 2006.285.23:24:14.89#ibcon#about to write, iclass 17, count 0 2006.285.23:24:14.89#ibcon#wrote, iclass 17, count 0 2006.285.23:24:14.89#ibcon#about to read 3, iclass 17, count 0 2006.285.23:24:14.93#ibcon#read 3, iclass 17, count 0 2006.285.23:24:14.93#ibcon#about to read 4, iclass 17, count 0 2006.285.23:24:14.93#ibcon#read 4, iclass 17, count 0 2006.285.23:24:14.93#ibcon#about to read 5, iclass 17, count 0 2006.285.23:24:14.93#ibcon#read 5, iclass 17, count 0 2006.285.23:24:14.93#ibcon#about to read 6, iclass 17, count 0 2006.285.23:24:14.93#ibcon#read 6, iclass 17, count 0 2006.285.23:24:14.93#ibcon#end of sib2, iclass 17, count 0 2006.285.23:24:14.93#ibcon#*after write, iclass 17, count 0 2006.285.23:24:14.93#ibcon#*before return 0, iclass 17, count 0 2006.285.23:24:14.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:24:14.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:24:14.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:24:14.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:24:14.93$vck44/va=5,3 2006.285.23:24:14.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.23:24:14.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.23:24:14.93#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:14.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:24:14.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:24:14.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:24:14.99#ibcon#enter wrdev, iclass 19, count 2 2006.285.23:24:14.99#ibcon#first serial, iclass 19, count 2 2006.285.23:24:14.99#ibcon#enter sib2, iclass 19, count 2 2006.285.23:24:14.99#ibcon#flushed, iclass 19, count 2 2006.285.23:24:14.99#ibcon#about to write, iclass 19, count 2 2006.285.23:24:14.99#ibcon#wrote, iclass 19, count 2 2006.285.23:24:14.99#ibcon#about to read 3, iclass 19, count 2 2006.285.23:24:15.01#ibcon#read 3, iclass 19, count 2 2006.285.23:24:15.01#ibcon#about to read 4, iclass 19, count 2 2006.285.23:24:15.01#ibcon#read 4, iclass 19, count 2 2006.285.23:24:15.01#ibcon#about to read 5, iclass 19, count 2 2006.285.23:24:15.01#ibcon#read 5, iclass 19, count 2 2006.285.23:24:15.01#ibcon#about to read 6, iclass 19, count 2 2006.285.23:24:15.01#ibcon#read 6, iclass 19, count 2 2006.285.23:24:15.01#ibcon#end of sib2, iclass 19, count 2 2006.285.23:24:15.01#ibcon#*mode == 0, iclass 19, count 2 2006.285.23:24:15.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.23:24:15.01#ibcon#[25=AT05-03\r\n] 2006.285.23:24:15.01#ibcon#*before write, iclass 19, count 2 2006.285.23:24:15.01#ibcon#enter sib2, iclass 19, count 2 2006.285.23:24:15.01#ibcon#flushed, iclass 19, count 2 2006.285.23:24:15.01#ibcon#about to write, iclass 19, count 2 2006.285.23:24:15.01#ibcon#wrote, iclass 19, count 2 2006.285.23:24:15.01#ibcon#about to read 3, iclass 19, count 2 2006.285.23:24:15.04#ibcon#read 3, iclass 19, count 2 2006.285.23:24:15.04#ibcon#about to read 4, iclass 19, count 2 2006.285.23:24:15.04#ibcon#read 4, iclass 19, count 2 2006.285.23:24:15.04#ibcon#about to read 5, iclass 19, count 2 2006.285.23:24:15.04#ibcon#read 5, iclass 19, count 2 2006.285.23:24:15.04#ibcon#about to read 6, iclass 19, count 2 2006.285.23:24:15.04#ibcon#read 6, iclass 19, count 2 2006.285.23:24:15.04#ibcon#end of sib2, iclass 19, count 2 2006.285.23:24:15.04#ibcon#*after write, iclass 19, count 2 2006.285.23:24:15.04#ibcon#*before return 0, iclass 19, count 2 2006.285.23:24:15.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:24:15.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:24:15.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.23:24:15.04#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:15.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:24:15.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:24:15.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:24:15.16#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:24:15.16#ibcon#first serial, iclass 19, count 0 2006.285.23:24:15.16#ibcon#enter sib2, iclass 19, count 0 2006.285.23:24:15.16#ibcon#flushed, iclass 19, count 0 2006.285.23:24:15.16#ibcon#about to write, iclass 19, count 0 2006.285.23:24:15.16#ibcon#wrote, iclass 19, count 0 2006.285.23:24:15.16#ibcon#about to read 3, iclass 19, count 0 2006.285.23:24:15.18#ibcon#read 3, iclass 19, count 0 2006.285.23:24:15.18#ibcon#about to read 4, iclass 19, count 0 2006.285.23:24:15.18#ibcon#read 4, iclass 19, count 0 2006.285.23:24:15.18#ibcon#about to read 5, iclass 19, count 0 2006.285.23:24:15.18#ibcon#read 5, iclass 19, count 0 2006.285.23:24:15.18#ibcon#about to read 6, iclass 19, count 0 2006.285.23:24:15.18#ibcon#read 6, iclass 19, count 0 2006.285.23:24:15.18#ibcon#end of sib2, iclass 19, count 0 2006.285.23:24:15.18#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:24:15.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:24:15.18#ibcon#[25=USB\r\n] 2006.285.23:24:15.18#ibcon#*before write, iclass 19, count 0 2006.285.23:24:15.18#ibcon#enter sib2, iclass 19, count 0 2006.285.23:24:15.18#ibcon#flushed, iclass 19, count 0 2006.285.23:24:15.18#ibcon#about to write, iclass 19, count 0 2006.285.23:24:15.18#ibcon#wrote, iclass 19, count 0 2006.285.23:24:15.18#ibcon#about to read 3, iclass 19, count 0 2006.285.23:24:15.21#ibcon#read 3, iclass 19, count 0 2006.285.23:24:15.21#ibcon#about to read 4, iclass 19, count 0 2006.285.23:24:15.21#ibcon#read 4, iclass 19, count 0 2006.285.23:24:15.21#ibcon#about to read 5, iclass 19, count 0 2006.285.23:24:15.21#ibcon#read 5, iclass 19, count 0 2006.285.23:24:15.21#ibcon#about to read 6, iclass 19, count 0 2006.285.23:24:15.21#ibcon#read 6, iclass 19, count 0 2006.285.23:24:15.21#ibcon#end of sib2, iclass 19, count 0 2006.285.23:24:15.21#ibcon#*after write, iclass 19, count 0 2006.285.23:24:15.21#ibcon#*before return 0, iclass 19, count 0 2006.285.23:24:15.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:24:15.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:24:15.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:24:15.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:24:15.21$vck44/valo=6,814.99 2006.285.23:24:15.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.23:24:15.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.23:24:15.21#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:15.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:24:15.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:24:15.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:24:15.21#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:24:15.21#ibcon#first serial, iclass 21, count 0 2006.285.23:24:15.21#ibcon#enter sib2, iclass 21, count 0 2006.285.23:24:15.21#ibcon#flushed, iclass 21, count 0 2006.285.23:24:15.21#ibcon#about to write, iclass 21, count 0 2006.285.23:24:15.21#ibcon#wrote, iclass 21, count 0 2006.285.23:24:15.21#ibcon#about to read 3, iclass 21, count 0 2006.285.23:24:15.23#ibcon#read 3, iclass 21, count 0 2006.285.23:24:15.23#ibcon#about to read 4, iclass 21, count 0 2006.285.23:24:15.23#ibcon#read 4, iclass 21, count 0 2006.285.23:24:15.23#ibcon#about to read 5, iclass 21, count 0 2006.285.23:24:15.23#ibcon#read 5, iclass 21, count 0 2006.285.23:24:15.23#ibcon#about to read 6, iclass 21, count 0 2006.285.23:24:15.23#ibcon#read 6, iclass 21, count 0 2006.285.23:24:15.23#ibcon#end of sib2, iclass 21, count 0 2006.285.23:24:15.23#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:24:15.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:24:15.23#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.23:24:15.23#ibcon#*before write, iclass 21, count 0 2006.285.23:24:15.23#ibcon#enter sib2, iclass 21, count 0 2006.285.23:24:15.23#ibcon#flushed, iclass 21, count 0 2006.285.23:24:15.23#ibcon#about to write, iclass 21, count 0 2006.285.23:24:15.23#ibcon#wrote, iclass 21, count 0 2006.285.23:24:15.23#ibcon#about to read 3, iclass 21, count 0 2006.285.23:24:15.27#ibcon#read 3, iclass 21, count 0 2006.285.23:24:15.27#ibcon#about to read 4, iclass 21, count 0 2006.285.23:24:15.27#ibcon#read 4, iclass 21, count 0 2006.285.23:24:15.27#ibcon#about to read 5, iclass 21, count 0 2006.285.23:24:15.27#ibcon#read 5, iclass 21, count 0 2006.285.23:24:15.27#ibcon#about to read 6, iclass 21, count 0 2006.285.23:24:15.27#ibcon#read 6, iclass 21, count 0 2006.285.23:24:15.27#ibcon#end of sib2, iclass 21, count 0 2006.285.23:24:15.27#ibcon#*after write, iclass 21, count 0 2006.285.23:24:15.27#ibcon#*before return 0, iclass 21, count 0 2006.285.23:24:15.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:24:15.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:24:15.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:24:15.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:24:15.27$vck44/va=6,4 2006.285.23:24:15.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.23:24:15.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.23:24:15.27#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:15.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:24:15.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:24:15.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:24:15.33#ibcon#enter wrdev, iclass 23, count 2 2006.285.23:24:15.33#ibcon#first serial, iclass 23, count 2 2006.285.23:24:15.33#ibcon#enter sib2, iclass 23, count 2 2006.285.23:24:15.33#ibcon#flushed, iclass 23, count 2 2006.285.23:24:15.33#ibcon#about to write, iclass 23, count 2 2006.285.23:24:15.33#ibcon#wrote, iclass 23, count 2 2006.285.23:24:15.33#ibcon#about to read 3, iclass 23, count 2 2006.285.23:24:15.35#ibcon#read 3, iclass 23, count 2 2006.285.23:24:15.35#ibcon#about to read 4, iclass 23, count 2 2006.285.23:24:15.35#ibcon#read 4, iclass 23, count 2 2006.285.23:24:15.35#ibcon#about to read 5, iclass 23, count 2 2006.285.23:24:15.35#ibcon#read 5, iclass 23, count 2 2006.285.23:24:15.35#ibcon#about to read 6, iclass 23, count 2 2006.285.23:24:15.35#ibcon#read 6, iclass 23, count 2 2006.285.23:24:15.35#ibcon#end of sib2, iclass 23, count 2 2006.285.23:24:15.35#ibcon#*mode == 0, iclass 23, count 2 2006.285.23:24:15.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.23:24:15.35#ibcon#[25=AT06-04\r\n] 2006.285.23:24:15.35#ibcon#*before write, iclass 23, count 2 2006.285.23:24:15.35#ibcon#enter sib2, iclass 23, count 2 2006.285.23:24:15.35#ibcon#flushed, iclass 23, count 2 2006.285.23:24:15.35#ibcon#about to write, iclass 23, count 2 2006.285.23:24:15.35#ibcon#wrote, iclass 23, count 2 2006.285.23:24:15.35#ibcon#about to read 3, iclass 23, count 2 2006.285.23:24:15.38#ibcon#read 3, iclass 23, count 2 2006.285.23:24:15.38#ibcon#about to read 4, iclass 23, count 2 2006.285.23:24:15.38#ibcon#read 4, iclass 23, count 2 2006.285.23:24:15.38#ibcon#about to read 5, iclass 23, count 2 2006.285.23:24:15.38#ibcon#read 5, iclass 23, count 2 2006.285.23:24:15.38#ibcon#about to read 6, iclass 23, count 2 2006.285.23:24:15.38#ibcon#read 6, iclass 23, count 2 2006.285.23:24:15.38#ibcon#end of sib2, iclass 23, count 2 2006.285.23:24:15.38#ibcon#*after write, iclass 23, count 2 2006.285.23:24:15.38#ibcon#*before return 0, iclass 23, count 2 2006.285.23:24:15.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:24:15.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:24:15.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.23:24:15.38#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:15.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:24:15.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:24:15.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:24:15.50#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:24:15.50#ibcon#first serial, iclass 23, count 0 2006.285.23:24:15.50#ibcon#enter sib2, iclass 23, count 0 2006.285.23:24:15.50#ibcon#flushed, iclass 23, count 0 2006.285.23:24:15.50#ibcon#about to write, iclass 23, count 0 2006.285.23:24:15.50#ibcon#wrote, iclass 23, count 0 2006.285.23:24:15.50#ibcon#about to read 3, iclass 23, count 0 2006.285.23:24:15.52#ibcon#read 3, iclass 23, count 0 2006.285.23:24:15.52#ibcon#about to read 4, iclass 23, count 0 2006.285.23:24:15.52#ibcon#read 4, iclass 23, count 0 2006.285.23:24:15.52#ibcon#about to read 5, iclass 23, count 0 2006.285.23:24:15.52#ibcon#read 5, iclass 23, count 0 2006.285.23:24:15.52#ibcon#about to read 6, iclass 23, count 0 2006.285.23:24:15.52#ibcon#read 6, iclass 23, count 0 2006.285.23:24:15.52#ibcon#end of sib2, iclass 23, count 0 2006.285.23:24:15.52#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:24:15.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:24:15.52#ibcon#[25=USB\r\n] 2006.285.23:24:15.52#ibcon#*before write, iclass 23, count 0 2006.285.23:24:15.52#ibcon#enter sib2, iclass 23, count 0 2006.285.23:24:15.52#ibcon#flushed, iclass 23, count 0 2006.285.23:24:15.52#ibcon#about to write, iclass 23, count 0 2006.285.23:24:15.52#ibcon#wrote, iclass 23, count 0 2006.285.23:24:15.52#ibcon#about to read 3, iclass 23, count 0 2006.285.23:24:15.55#ibcon#read 3, iclass 23, count 0 2006.285.23:24:15.55#ibcon#about to read 4, iclass 23, count 0 2006.285.23:24:15.55#ibcon#read 4, iclass 23, count 0 2006.285.23:24:15.55#ibcon#about to read 5, iclass 23, count 0 2006.285.23:24:15.55#ibcon#read 5, iclass 23, count 0 2006.285.23:24:15.55#ibcon#about to read 6, iclass 23, count 0 2006.285.23:24:15.55#ibcon#read 6, iclass 23, count 0 2006.285.23:24:15.55#ibcon#end of sib2, iclass 23, count 0 2006.285.23:24:15.55#ibcon#*after write, iclass 23, count 0 2006.285.23:24:15.55#ibcon#*before return 0, iclass 23, count 0 2006.285.23:24:15.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:24:15.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:24:15.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:24:15.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:24:15.55$vck44/valo=7,864.99 2006.285.23:24:15.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.23:24:15.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.23:24:15.55#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:15.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:24:15.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:24:15.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:24:15.55#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:24:15.55#ibcon#first serial, iclass 25, count 0 2006.285.23:24:15.55#ibcon#enter sib2, iclass 25, count 0 2006.285.23:24:15.55#ibcon#flushed, iclass 25, count 0 2006.285.23:24:15.55#ibcon#about to write, iclass 25, count 0 2006.285.23:24:15.55#ibcon#wrote, iclass 25, count 0 2006.285.23:24:15.55#ibcon#about to read 3, iclass 25, count 0 2006.285.23:24:15.57#ibcon#read 3, iclass 25, count 0 2006.285.23:24:15.57#ibcon#about to read 4, iclass 25, count 0 2006.285.23:24:15.57#ibcon#read 4, iclass 25, count 0 2006.285.23:24:15.57#ibcon#about to read 5, iclass 25, count 0 2006.285.23:24:15.57#ibcon#read 5, iclass 25, count 0 2006.285.23:24:15.57#ibcon#about to read 6, iclass 25, count 0 2006.285.23:24:15.57#ibcon#read 6, iclass 25, count 0 2006.285.23:24:15.57#ibcon#end of sib2, iclass 25, count 0 2006.285.23:24:15.57#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:24:15.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:24:15.57#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.23:24:15.57#ibcon#*before write, iclass 25, count 0 2006.285.23:24:15.57#ibcon#enter sib2, iclass 25, count 0 2006.285.23:24:15.57#ibcon#flushed, iclass 25, count 0 2006.285.23:24:15.57#ibcon#about to write, iclass 25, count 0 2006.285.23:24:15.57#ibcon#wrote, iclass 25, count 0 2006.285.23:24:15.57#ibcon#about to read 3, iclass 25, count 0 2006.285.23:24:15.61#ibcon#read 3, iclass 25, count 0 2006.285.23:24:15.61#ibcon#about to read 4, iclass 25, count 0 2006.285.23:24:15.61#ibcon#read 4, iclass 25, count 0 2006.285.23:24:15.61#ibcon#about to read 5, iclass 25, count 0 2006.285.23:24:15.61#ibcon#read 5, iclass 25, count 0 2006.285.23:24:15.61#ibcon#about to read 6, iclass 25, count 0 2006.285.23:24:15.61#ibcon#read 6, iclass 25, count 0 2006.285.23:24:15.61#ibcon#end of sib2, iclass 25, count 0 2006.285.23:24:15.61#ibcon#*after write, iclass 25, count 0 2006.285.23:24:15.61#ibcon#*before return 0, iclass 25, count 0 2006.285.23:24:15.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:24:15.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:24:15.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:24:15.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:24:15.61$vck44/va=7,4 2006.285.23:24:15.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.23:24:15.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.23:24:15.61#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:15.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:24:15.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:24:15.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:24:15.67#ibcon#enter wrdev, iclass 27, count 2 2006.285.23:24:15.67#ibcon#first serial, iclass 27, count 2 2006.285.23:24:15.67#ibcon#enter sib2, iclass 27, count 2 2006.285.23:24:15.67#ibcon#flushed, iclass 27, count 2 2006.285.23:24:15.67#ibcon#about to write, iclass 27, count 2 2006.285.23:24:15.67#ibcon#wrote, iclass 27, count 2 2006.285.23:24:15.67#ibcon#about to read 3, iclass 27, count 2 2006.285.23:24:15.69#ibcon#read 3, iclass 27, count 2 2006.285.23:24:15.69#ibcon#about to read 4, iclass 27, count 2 2006.285.23:24:15.69#ibcon#read 4, iclass 27, count 2 2006.285.23:24:15.69#ibcon#about to read 5, iclass 27, count 2 2006.285.23:24:15.69#ibcon#read 5, iclass 27, count 2 2006.285.23:24:15.69#ibcon#about to read 6, iclass 27, count 2 2006.285.23:24:15.69#ibcon#read 6, iclass 27, count 2 2006.285.23:24:15.69#ibcon#end of sib2, iclass 27, count 2 2006.285.23:24:15.69#ibcon#*mode == 0, iclass 27, count 2 2006.285.23:24:15.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.23:24:15.69#ibcon#[25=AT07-04\r\n] 2006.285.23:24:15.69#ibcon#*before write, iclass 27, count 2 2006.285.23:24:15.69#ibcon#enter sib2, iclass 27, count 2 2006.285.23:24:15.69#ibcon#flushed, iclass 27, count 2 2006.285.23:24:15.69#ibcon#about to write, iclass 27, count 2 2006.285.23:24:15.69#ibcon#wrote, iclass 27, count 2 2006.285.23:24:15.69#ibcon#about to read 3, iclass 27, count 2 2006.285.23:24:15.70#abcon#<5=/03 3.6 7.6 19.23 891016.4\r\n> 2006.285.23:24:15.72#abcon#{5=INTERFACE CLEAR} 2006.285.23:24:15.72#ibcon#read 3, iclass 27, count 2 2006.285.23:24:15.72#ibcon#about to read 4, iclass 27, count 2 2006.285.23:24:15.72#ibcon#read 4, iclass 27, count 2 2006.285.23:24:15.72#ibcon#about to read 5, iclass 27, count 2 2006.285.23:24:15.72#ibcon#read 5, iclass 27, count 2 2006.285.23:24:15.72#ibcon#about to read 6, iclass 27, count 2 2006.285.23:24:15.72#ibcon#read 6, iclass 27, count 2 2006.285.23:24:15.72#ibcon#end of sib2, iclass 27, count 2 2006.285.23:24:15.72#ibcon#*after write, iclass 27, count 2 2006.285.23:24:15.72#ibcon#*before return 0, iclass 27, count 2 2006.285.23:24:15.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:24:15.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:24:15.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.23:24:15.72#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:15.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:24:15.78#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:24:15.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:24:15.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:24:15.84#ibcon#enter wrdev, iclass 27, count 0 2006.285.23:24:15.84#ibcon#first serial, iclass 27, count 0 2006.285.23:24:15.84#ibcon#enter sib2, iclass 27, count 0 2006.285.23:24:15.84#ibcon#flushed, iclass 27, count 0 2006.285.23:24:15.84#ibcon#about to write, iclass 27, count 0 2006.285.23:24:15.84#ibcon#wrote, iclass 27, count 0 2006.285.23:24:15.84#ibcon#about to read 3, iclass 27, count 0 2006.285.23:24:15.86#ibcon#read 3, iclass 27, count 0 2006.285.23:24:15.86#ibcon#about to read 4, iclass 27, count 0 2006.285.23:24:15.86#ibcon#read 4, iclass 27, count 0 2006.285.23:24:15.86#ibcon#about to read 5, iclass 27, count 0 2006.285.23:24:15.86#ibcon#read 5, iclass 27, count 0 2006.285.23:24:15.86#ibcon#about to read 6, iclass 27, count 0 2006.285.23:24:15.86#ibcon#read 6, iclass 27, count 0 2006.285.23:24:15.86#ibcon#end of sib2, iclass 27, count 0 2006.285.23:24:15.86#ibcon#*mode == 0, iclass 27, count 0 2006.285.23:24:15.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.23:24:15.86#ibcon#[25=USB\r\n] 2006.285.23:24:15.86#ibcon#*before write, iclass 27, count 0 2006.285.23:24:15.86#ibcon#enter sib2, iclass 27, count 0 2006.285.23:24:15.86#ibcon#flushed, iclass 27, count 0 2006.285.23:24:15.86#ibcon#about to write, iclass 27, count 0 2006.285.23:24:15.86#ibcon#wrote, iclass 27, count 0 2006.285.23:24:15.86#ibcon#about to read 3, iclass 27, count 0 2006.285.23:24:15.89#ibcon#read 3, iclass 27, count 0 2006.285.23:24:15.89#ibcon#about to read 4, iclass 27, count 0 2006.285.23:24:15.89#ibcon#read 4, iclass 27, count 0 2006.285.23:24:15.89#ibcon#about to read 5, iclass 27, count 0 2006.285.23:24:15.89#ibcon#read 5, iclass 27, count 0 2006.285.23:24:15.89#ibcon#about to read 6, iclass 27, count 0 2006.285.23:24:15.89#ibcon#read 6, iclass 27, count 0 2006.285.23:24:15.89#ibcon#end of sib2, iclass 27, count 0 2006.285.23:24:15.89#ibcon#*after write, iclass 27, count 0 2006.285.23:24:15.89#ibcon#*before return 0, iclass 27, count 0 2006.285.23:24:15.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:24:15.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:24:15.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.23:24:15.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.23:24:15.89$vck44/valo=8,884.99 2006.285.23:24:15.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.23:24:15.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.23:24:15.89#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:15.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:24:15.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:24:15.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:24:15.89#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:24:15.89#ibcon#first serial, iclass 33, count 0 2006.285.23:24:15.89#ibcon#enter sib2, iclass 33, count 0 2006.285.23:24:15.89#ibcon#flushed, iclass 33, count 0 2006.285.23:24:15.89#ibcon#about to write, iclass 33, count 0 2006.285.23:24:15.89#ibcon#wrote, iclass 33, count 0 2006.285.23:24:15.89#ibcon#about to read 3, iclass 33, count 0 2006.285.23:24:15.91#ibcon#read 3, iclass 33, count 0 2006.285.23:24:15.91#ibcon#about to read 4, iclass 33, count 0 2006.285.23:24:15.91#ibcon#read 4, iclass 33, count 0 2006.285.23:24:15.91#ibcon#about to read 5, iclass 33, count 0 2006.285.23:24:15.91#ibcon#read 5, iclass 33, count 0 2006.285.23:24:15.91#ibcon#about to read 6, iclass 33, count 0 2006.285.23:24:15.91#ibcon#read 6, iclass 33, count 0 2006.285.23:24:15.91#ibcon#end of sib2, iclass 33, count 0 2006.285.23:24:15.91#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:24:15.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:24:15.91#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.23:24:15.91#ibcon#*before write, iclass 33, count 0 2006.285.23:24:15.91#ibcon#enter sib2, iclass 33, count 0 2006.285.23:24:15.91#ibcon#flushed, iclass 33, count 0 2006.285.23:24:15.91#ibcon#about to write, iclass 33, count 0 2006.285.23:24:15.91#ibcon#wrote, iclass 33, count 0 2006.285.23:24:15.91#ibcon#about to read 3, iclass 33, count 0 2006.285.23:24:15.95#ibcon#read 3, iclass 33, count 0 2006.285.23:24:15.95#ibcon#about to read 4, iclass 33, count 0 2006.285.23:24:15.95#ibcon#read 4, iclass 33, count 0 2006.285.23:24:15.95#ibcon#about to read 5, iclass 33, count 0 2006.285.23:24:15.95#ibcon#read 5, iclass 33, count 0 2006.285.23:24:15.95#ibcon#about to read 6, iclass 33, count 0 2006.285.23:24:15.95#ibcon#read 6, iclass 33, count 0 2006.285.23:24:15.95#ibcon#end of sib2, iclass 33, count 0 2006.285.23:24:15.95#ibcon#*after write, iclass 33, count 0 2006.285.23:24:15.95#ibcon#*before return 0, iclass 33, count 0 2006.285.23:24:15.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:24:15.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:24:15.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:24:15.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:24:15.95$vck44/va=8,3 2006.285.23:24:15.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.23:24:15.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.23:24:15.95#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:15.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.23:24:16.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.23:24:16.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.23:24:16.01#ibcon#enter wrdev, iclass 35, count 2 2006.285.23:24:16.01#ibcon#first serial, iclass 35, count 2 2006.285.23:24:16.01#ibcon#enter sib2, iclass 35, count 2 2006.285.23:24:16.01#ibcon#flushed, iclass 35, count 2 2006.285.23:24:16.01#ibcon#about to write, iclass 35, count 2 2006.285.23:24:16.01#ibcon#wrote, iclass 35, count 2 2006.285.23:24:16.01#ibcon#about to read 3, iclass 35, count 2 2006.285.23:24:16.03#ibcon#read 3, iclass 35, count 2 2006.285.23:24:16.03#ibcon#about to read 4, iclass 35, count 2 2006.285.23:24:16.03#ibcon#read 4, iclass 35, count 2 2006.285.23:24:16.03#ibcon#about to read 5, iclass 35, count 2 2006.285.23:24:16.03#ibcon#read 5, iclass 35, count 2 2006.285.23:24:16.03#ibcon#about to read 6, iclass 35, count 2 2006.285.23:24:16.03#ibcon#read 6, iclass 35, count 2 2006.285.23:24:16.03#ibcon#end of sib2, iclass 35, count 2 2006.285.23:24:16.03#ibcon#*mode == 0, iclass 35, count 2 2006.285.23:24:16.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.23:24:16.03#ibcon#[25=AT08-03\r\n] 2006.285.23:24:16.03#ibcon#*before write, iclass 35, count 2 2006.285.23:24:16.03#ibcon#enter sib2, iclass 35, count 2 2006.285.23:24:16.03#ibcon#flushed, iclass 35, count 2 2006.285.23:24:16.03#ibcon#about to write, iclass 35, count 2 2006.285.23:24:16.03#ibcon#wrote, iclass 35, count 2 2006.285.23:24:16.03#ibcon#about to read 3, iclass 35, count 2 2006.285.23:24:16.06#ibcon#read 3, iclass 35, count 2 2006.285.23:24:16.06#ibcon#about to read 4, iclass 35, count 2 2006.285.23:24:16.06#ibcon#read 4, iclass 35, count 2 2006.285.23:24:16.06#ibcon#about to read 5, iclass 35, count 2 2006.285.23:24:16.06#ibcon#read 5, iclass 35, count 2 2006.285.23:24:16.06#ibcon#about to read 6, iclass 35, count 2 2006.285.23:24:16.06#ibcon#read 6, iclass 35, count 2 2006.285.23:24:16.06#ibcon#end of sib2, iclass 35, count 2 2006.285.23:24:16.06#ibcon#*after write, iclass 35, count 2 2006.285.23:24:16.06#ibcon#*before return 0, iclass 35, count 2 2006.285.23:24:16.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.23:24:16.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.23:24:16.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.23:24:16.06#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:16.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.23:24:16.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.23:24:16.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.23:24:16.18#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:24:16.18#ibcon#first serial, iclass 35, count 0 2006.285.23:24:16.18#ibcon#enter sib2, iclass 35, count 0 2006.285.23:24:16.18#ibcon#flushed, iclass 35, count 0 2006.285.23:24:16.18#ibcon#about to write, iclass 35, count 0 2006.285.23:24:16.18#ibcon#wrote, iclass 35, count 0 2006.285.23:24:16.18#ibcon#about to read 3, iclass 35, count 0 2006.285.23:24:16.20#ibcon#read 3, iclass 35, count 0 2006.285.23:24:16.20#ibcon#about to read 4, iclass 35, count 0 2006.285.23:24:16.20#ibcon#read 4, iclass 35, count 0 2006.285.23:24:16.20#ibcon#about to read 5, iclass 35, count 0 2006.285.23:24:16.20#ibcon#read 5, iclass 35, count 0 2006.285.23:24:16.20#ibcon#about to read 6, iclass 35, count 0 2006.285.23:24:16.20#ibcon#read 6, iclass 35, count 0 2006.285.23:24:16.20#ibcon#end of sib2, iclass 35, count 0 2006.285.23:24:16.20#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:24:16.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:24:16.20#ibcon#[25=USB\r\n] 2006.285.23:24:16.20#ibcon#*before write, iclass 35, count 0 2006.285.23:24:16.20#ibcon#enter sib2, iclass 35, count 0 2006.285.23:24:16.20#ibcon#flushed, iclass 35, count 0 2006.285.23:24:16.20#ibcon#about to write, iclass 35, count 0 2006.285.23:24:16.20#ibcon#wrote, iclass 35, count 0 2006.285.23:24:16.20#ibcon#about to read 3, iclass 35, count 0 2006.285.23:24:16.23#ibcon#read 3, iclass 35, count 0 2006.285.23:24:16.23#ibcon#about to read 4, iclass 35, count 0 2006.285.23:24:16.23#ibcon#read 4, iclass 35, count 0 2006.285.23:24:16.23#ibcon#about to read 5, iclass 35, count 0 2006.285.23:24:16.23#ibcon#read 5, iclass 35, count 0 2006.285.23:24:16.23#ibcon#about to read 6, iclass 35, count 0 2006.285.23:24:16.23#ibcon#read 6, iclass 35, count 0 2006.285.23:24:16.23#ibcon#end of sib2, iclass 35, count 0 2006.285.23:24:16.23#ibcon#*after write, iclass 35, count 0 2006.285.23:24:16.23#ibcon#*before return 0, iclass 35, count 0 2006.285.23:24:16.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.23:24:16.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.23:24:16.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:24:16.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:24:16.23$vck44/vblo=1,629.99 2006.285.23:24:16.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.23:24:16.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.23:24:16.23#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:16.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:24:16.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:24:16.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:24:16.23#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:24:16.23#ibcon#first serial, iclass 37, count 0 2006.285.23:24:16.23#ibcon#enter sib2, iclass 37, count 0 2006.285.23:24:16.23#ibcon#flushed, iclass 37, count 0 2006.285.23:24:16.23#ibcon#about to write, iclass 37, count 0 2006.285.23:24:16.23#ibcon#wrote, iclass 37, count 0 2006.285.23:24:16.23#ibcon#about to read 3, iclass 37, count 0 2006.285.23:24:16.25#ibcon#read 3, iclass 37, count 0 2006.285.23:24:16.25#ibcon#about to read 4, iclass 37, count 0 2006.285.23:24:16.25#ibcon#read 4, iclass 37, count 0 2006.285.23:24:16.25#ibcon#about to read 5, iclass 37, count 0 2006.285.23:24:16.25#ibcon#read 5, iclass 37, count 0 2006.285.23:24:16.25#ibcon#about to read 6, iclass 37, count 0 2006.285.23:24:16.25#ibcon#read 6, iclass 37, count 0 2006.285.23:24:16.25#ibcon#end of sib2, iclass 37, count 0 2006.285.23:24:16.25#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:24:16.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:24:16.25#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.23:24:16.25#ibcon#*before write, iclass 37, count 0 2006.285.23:24:16.25#ibcon#enter sib2, iclass 37, count 0 2006.285.23:24:16.25#ibcon#flushed, iclass 37, count 0 2006.285.23:24:16.25#ibcon#about to write, iclass 37, count 0 2006.285.23:24:16.25#ibcon#wrote, iclass 37, count 0 2006.285.23:24:16.25#ibcon#about to read 3, iclass 37, count 0 2006.285.23:24:16.29#ibcon#read 3, iclass 37, count 0 2006.285.23:24:16.29#ibcon#about to read 4, iclass 37, count 0 2006.285.23:24:16.29#ibcon#read 4, iclass 37, count 0 2006.285.23:24:16.29#ibcon#about to read 5, iclass 37, count 0 2006.285.23:24:16.29#ibcon#read 5, iclass 37, count 0 2006.285.23:24:16.29#ibcon#about to read 6, iclass 37, count 0 2006.285.23:24:16.29#ibcon#read 6, iclass 37, count 0 2006.285.23:24:16.29#ibcon#end of sib2, iclass 37, count 0 2006.285.23:24:16.29#ibcon#*after write, iclass 37, count 0 2006.285.23:24:16.29#ibcon#*before return 0, iclass 37, count 0 2006.285.23:24:16.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:24:16.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:24:16.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:24:16.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:24:16.29$vck44/vb=1,4 2006.285.23:24:16.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.23:24:16.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.23:24:16.29#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:16.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:24:16.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:24:16.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:24:16.29#ibcon#enter wrdev, iclass 39, count 2 2006.285.23:24:16.29#ibcon#first serial, iclass 39, count 2 2006.285.23:24:16.29#ibcon#enter sib2, iclass 39, count 2 2006.285.23:24:16.29#ibcon#flushed, iclass 39, count 2 2006.285.23:24:16.29#ibcon#about to write, iclass 39, count 2 2006.285.23:24:16.29#ibcon#wrote, iclass 39, count 2 2006.285.23:24:16.29#ibcon#about to read 3, iclass 39, count 2 2006.285.23:24:16.31#ibcon#read 3, iclass 39, count 2 2006.285.23:24:16.31#ibcon#about to read 4, iclass 39, count 2 2006.285.23:24:16.31#ibcon#read 4, iclass 39, count 2 2006.285.23:24:16.31#ibcon#about to read 5, iclass 39, count 2 2006.285.23:24:16.31#ibcon#read 5, iclass 39, count 2 2006.285.23:24:16.31#ibcon#about to read 6, iclass 39, count 2 2006.285.23:24:16.31#ibcon#read 6, iclass 39, count 2 2006.285.23:24:16.31#ibcon#end of sib2, iclass 39, count 2 2006.285.23:24:16.31#ibcon#*mode == 0, iclass 39, count 2 2006.285.23:24:16.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.23:24:16.31#ibcon#[27=AT01-04\r\n] 2006.285.23:24:16.31#ibcon#*before write, iclass 39, count 2 2006.285.23:24:16.31#ibcon#enter sib2, iclass 39, count 2 2006.285.23:24:16.31#ibcon#flushed, iclass 39, count 2 2006.285.23:24:16.31#ibcon#about to write, iclass 39, count 2 2006.285.23:24:16.31#ibcon#wrote, iclass 39, count 2 2006.285.23:24:16.31#ibcon#about to read 3, iclass 39, count 2 2006.285.23:24:16.34#ibcon#read 3, iclass 39, count 2 2006.285.23:24:16.34#ibcon#about to read 4, iclass 39, count 2 2006.285.23:24:16.34#ibcon#read 4, iclass 39, count 2 2006.285.23:24:16.34#ibcon#about to read 5, iclass 39, count 2 2006.285.23:24:16.34#ibcon#read 5, iclass 39, count 2 2006.285.23:24:16.34#ibcon#about to read 6, iclass 39, count 2 2006.285.23:24:16.34#ibcon#read 6, iclass 39, count 2 2006.285.23:24:16.34#ibcon#end of sib2, iclass 39, count 2 2006.285.23:24:16.34#ibcon#*after write, iclass 39, count 2 2006.285.23:24:16.34#ibcon#*before return 0, iclass 39, count 2 2006.285.23:24:16.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:24:16.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:24:16.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.23:24:16.34#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:16.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:24:16.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:24:16.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:24:16.46#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:24:16.46#ibcon#first serial, iclass 39, count 0 2006.285.23:24:16.46#ibcon#enter sib2, iclass 39, count 0 2006.285.23:24:16.46#ibcon#flushed, iclass 39, count 0 2006.285.23:24:16.46#ibcon#about to write, iclass 39, count 0 2006.285.23:24:16.46#ibcon#wrote, iclass 39, count 0 2006.285.23:24:16.46#ibcon#about to read 3, iclass 39, count 0 2006.285.23:24:16.48#ibcon#read 3, iclass 39, count 0 2006.285.23:24:16.48#ibcon#about to read 4, iclass 39, count 0 2006.285.23:24:16.48#ibcon#read 4, iclass 39, count 0 2006.285.23:24:16.48#ibcon#about to read 5, iclass 39, count 0 2006.285.23:24:16.48#ibcon#read 5, iclass 39, count 0 2006.285.23:24:16.48#ibcon#about to read 6, iclass 39, count 0 2006.285.23:24:16.48#ibcon#read 6, iclass 39, count 0 2006.285.23:24:16.48#ibcon#end of sib2, iclass 39, count 0 2006.285.23:24:16.48#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:24:16.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:24:16.48#ibcon#[27=USB\r\n] 2006.285.23:24:16.48#ibcon#*before write, iclass 39, count 0 2006.285.23:24:16.48#ibcon#enter sib2, iclass 39, count 0 2006.285.23:24:16.48#ibcon#flushed, iclass 39, count 0 2006.285.23:24:16.48#ibcon#about to write, iclass 39, count 0 2006.285.23:24:16.48#ibcon#wrote, iclass 39, count 0 2006.285.23:24:16.48#ibcon#about to read 3, iclass 39, count 0 2006.285.23:24:16.51#ibcon#read 3, iclass 39, count 0 2006.285.23:24:16.51#ibcon#about to read 4, iclass 39, count 0 2006.285.23:24:16.51#ibcon#read 4, iclass 39, count 0 2006.285.23:24:16.51#ibcon#about to read 5, iclass 39, count 0 2006.285.23:24:16.51#ibcon#read 5, iclass 39, count 0 2006.285.23:24:16.51#ibcon#about to read 6, iclass 39, count 0 2006.285.23:24:16.51#ibcon#read 6, iclass 39, count 0 2006.285.23:24:16.51#ibcon#end of sib2, iclass 39, count 0 2006.285.23:24:16.51#ibcon#*after write, iclass 39, count 0 2006.285.23:24:16.51#ibcon#*before return 0, iclass 39, count 0 2006.285.23:24:16.51#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:24:16.51#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:24:16.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:24:16.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:24:16.51$vck44/vblo=2,634.99 2006.285.23:24:16.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.23:24:16.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.23:24:16.51#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:16.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:24:16.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:24:16.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:24:16.51#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:24:16.51#ibcon#first serial, iclass 3, count 0 2006.285.23:24:16.51#ibcon#enter sib2, iclass 3, count 0 2006.285.23:24:16.51#ibcon#flushed, iclass 3, count 0 2006.285.23:24:16.51#ibcon#about to write, iclass 3, count 0 2006.285.23:24:16.51#ibcon#wrote, iclass 3, count 0 2006.285.23:24:16.51#ibcon#about to read 3, iclass 3, count 0 2006.285.23:24:16.53#ibcon#read 3, iclass 3, count 0 2006.285.23:24:16.53#ibcon#about to read 4, iclass 3, count 0 2006.285.23:24:16.53#ibcon#read 4, iclass 3, count 0 2006.285.23:24:16.53#ibcon#about to read 5, iclass 3, count 0 2006.285.23:24:16.53#ibcon#read 5, iclass 3, count 0 2006.285.23:24:16.53#ibcon#about to read 6, iclass 3, count 0 2006.285.23:24:16.53#ibcon#read 6, iclass 3, count 0 2006.285.23:24:16.53#ibcon#end of sib2, iclass 3, count 0 2006.285.23:24:16.53#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:24:16.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:24:16.53#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.23:24:16.53#ibcon#*before write, iclass 3, count 0 2006.285.23:24:16.53#ibcon#enter sib2, iclass 3, count 0 2006.285.23:24:16.53#ibcon#flushed, iclass 3, count 0 2006.285.23:24:16.53#ibcon#about to write, iclass 3, count 0 2006.285.23:24:16.53#ibcon#wrote, iclass 3, count 0 2006.285.23:24:16.53#ibcon#about to read 3, iclass 3, count 0 2006.285.23:24:16.57#ibcon#read 3, iclass 3, count 0 2006.285.23:24:16.57#ibcon#about to read 4, iclass 3, count 0 2006.285.23:24:16.57#ibcon#read 4, iclass 3, count 0 2006.285.23:24:16.57#ibcon#about to read 5, iclass 3, count 0 2006.285.23:24:16.57#ibcon#read 5, iclass 3, count 0 2006.285.23:24:16.57#ibcon#about to read 6, iclass 3, count 0 2006.285.23:24:16.57#ibcon#read 6, iclass 3, count 0 2006.285.23:24:16.57#ibcon#end of sib2, iclass 3, count 0 2006.285.23:24:16.57#ibcon#*after write, iclass 3, count 0 2006.285.23:24:16.57#ibcon#*before return 0, iclass 3, count 0 2006.285.23:24:16.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:24:16.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:24:16.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:24:16.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:24:16.57$vck44/vb=2,5 2006.285.23:24:16.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.23:24:16.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.23:24:16.57#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:16.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:24:16.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:24:16.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:24:16.63#ibcon#enter wrdev, iclass 5, count 2 2006.285.23:24:16.63#ibcon#first serial, iclass 5, count 2 2006.285.23:24:16.63#ibcon#enter sib2, iclass 5, count 2 2006.285.23:24:16.63#ibcon#flushed, iclass 5, count 2 2006.285.23:24:16.63#ibcon#about to write, iclass 5, count 2 2006.285.23:24:16.63#ibcon#wrote, iclass 5, count 2 2006.285.23:24:16.63#ibcon#about to read 3, iclass 5, count 2 2006.285.23:24:16.65#ibcon#read 3, iclass 5, count 2 2006.285.23:24:16.65#ibcon#about to read 4, iclass 5, count 2 2006.285.23:24:16.65#ibcon#read 4, iclass 5, count 2 2006.285.23:24:16.65#ibcon#about to read 5, iclass 5, count 2 2006.285.23:24:16.65#ibcon#read 5, iclass 5, count 2 2006.285.23:24:16.65#ibcon#about to read 6, iclass 5, count 2 2006.285.23:24:16.65#ibcon#read 6, iclass 5, count 2 2006.285.23:24:16.65#ibcon#end of sib2, iclass 5, count 2 2006.285.23:24:16.65#ibcon#*mode == 0, iclass 5, count 2 2006.285.23:24:16.65#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.23:24:16.65#ibcon#[27=AT02-05\r\n] 2006.285.23:24:16.65#ibcon#*before write, iclass 5, count 2 2006.285.23:24:16.65#ibcon#enter sib2, iclass 5, count 2 2006.285.23:24:16.65#ibcon#flushed, iclass 5, count 2 2006.285.23:24:16.65#ibcon#about to write, iclass 5, count 2 2006.285.23:24:16.65#ibcon#wrote, iclass 5, count 2 2006.285.23:24:16.65#ibcon#about to read 3, iclass 5, count 2 2006.285.23:24:16.68#ibcon#read 3, iclass 5, count 2 2006.285.23:24:16.68#ibcon#about to read 4, iclass 5, count 2 2006.285.23:24:16.68#ibcon#read 4, iclass 5, count 2 2006.285.23:24:16.68#ibcon#about to read 5, iclass 5, count 2 2006.285.23:24:16.68#ibcon#read 5, iclass 5, count 2 2006.285.23:24:16.68#ibcon#about to read 6, iclass 5, count 2 2006.285.23:24:16.68#ibcon#read 6, iclass 5, count 2 2006.285.23:24:16.68#ibcon#end of sib2, iclass 5, count 2 2006.285.23:24:16.68#ibcon#*after write, iclass 5, count 2 2006.285.23:24:16.68#ibcon#*before return 0, iclass 5, count 2 2006.285.23:24:16.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:24:16.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:24:16.68#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.23:24:16.68#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:16.68#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:24:16.80#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:24:16.80#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:24:16.80#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:24:16.80#ibcon#first serial, iclass 5, count 0 2006.285.23:24:16.80#ibcon#enter sib2, iclass 5, count 0 2006.285.23:24:16.80#ibcon#flushed, iclass 5, count 0 2006.285.23:24:16.80#ibcon#about to write, iclass 5, count 0 2006.285.23:24:16.80#ibcon#wrote, iclass 5, count 0 2006.285.23:24:16.80#ibcon#about to read 3, iclass 5, count 0 2006.285.23:24:16.82#ibcon#read 3, iclass 5, count 0 2006.285.23:24:16.82#ibcon#about to read 4, iclass 5, count 0 2006.285.23:24:16.82#ibcon#read 4, iclass 5, count 0 2006.285.23:24:16.82#ibcon#about to read 5, iclass 5, count 0 2006.285.23:24:16.82#ibcon#read 5, iclass 5, count 0 2006.285.23:24:16.82#ibcon#about to read 6, iclass 5, count 0 2006.285.23:24:16.82#ibcon#read 6, iclass 5, count 0 2006.285.23:24:16.82#ibcon#end of sib2, iclass 5, count 0 2006.285.23:24:16.82#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:24:16.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:24:16.82#ibcon#[27=USB\r\n] 2006.285.23:24:16.82#ibcon#*before write, iclass 5, count 0 2006.285.23:24:16.82#ibcon#enter sib2, iclass 5, count 0 2006.285.23:24:16.82#ibcon#flushed, iclass 5, count 0 2006.285.23:24:16.82#ibcon#about to write, iclass 5, count 0 2006.285.23:24:16.82#ibcon#wrote, iclass 5, count 0 2006.285.23:24:16.82#ibcon#about to read 3, iclass 5, count 0 2006.285.23:24:16.85#ibcon#read 3, iclass 5, count 0 2006.285.23:24:16.85#ibcon#about to read 4, iclass 5, count 0 2006.285.23:24:16.85#ibcon#read 4, iclass 5, count 0 2006.285.23:24:16.85#ibcon#about to read 5, iclass 5, count 0 2006.285.23:24:16.85#ibcon#read 5, iclass 5, count 0 2006.285.23:24:16.85#ibcon#about to read 6, iclass 5, count 0 2006.285.23:24:16.85#ibcon#read 6, iclass 5, count 0 2006.285.23:24:16.85#ibcon#end of sib2, iclass 5, count 0 2006.285.23:24:16.85#ibcon#*after write, iclass 5, count 0 2006.285.23:24:16.85#ibcon#*before return 0, iclass 5, count 0 2006.285.23:24:16.85#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:24:16.85#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:24:16.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:24:16.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:24:16.85$vck44/vblo=3,649.99 2006.285.23:24:16.85#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.23:24:16.85#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.23:24:16.85#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:16.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:24:16.85#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:24:16.85#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:24:16.85#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:24:16.85#ibcon#first serial, iclass 7, count 0 2006.285.23:24:16.85#ibcon#enter sib2, iclass 7, count 0 2006.285.23:24:16.85#ibcon#flushed, iclass 7, count 0 2006.285.23:24:16.85#ibcon#about to write, iclass 7, count 0 2006.285.23:24:16.85#ibcon#wrote, iclass 7, count 0 2006.285.23:24:16.85#ibcon#about to read 3, iclass 7, count 0 2006.285.23:24:16.87#ibcon#read 3, iclass 7, count 0 2006.285.23:24:16.87#ibcon#about to read 4, iclass 7, count 0 2006.285.23:24:16.87#ibcon#read 4, iclass 7, count 0 2006.285.23:24:16.87#ibcon#about to read 5, iclass 7, count 0 2006.285.23:24:16.87#ibcon#read 5, iclass 7, count 0 2006.285.23:24:16.87#ibcon#about to read 6, iclass 7, count 0 2006.285.23:24:16.87#ibcon#read 6, iclass 7, count 0 2006.285.23:24:16.87#ibcon#end of sib2, iclass 7, count 0 2006.285.23:24:16.87#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:24:16.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:24:16.87#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.23:24:16.87#ibcon#*before write, iclass 7, count 0 2006.285.23:24:16.87#ibcon#enter sib2, iclass 7, count 0 2006.285.23:24:16.87#ibcon#flushed, iclass 7, count 0 2006.285.23:24:16.87#ibcon#about to write, iclass 7, count 0 2006.285.23:24:16.87#ibcon#wrote, iclass 7, count 0 2006.285.23:24:16.87#ibcon#about to read 3, iclass 7, count 0 2006.285.23:24:16.91#ibcon#read 3, iclass 7, count 0 2006.285.23:24:16.91#ibcon#about to read 4, iclass 7, count 0 2006.285.23:24:16.91#ibcon#read 4, iclass 7, count 0 2006.285.23:24:16.91#ibcon#about to read 5, iclass 7, count 0 2006.285.23:24:16.91#ibcon#read 5, iclass 7, count 0 2006.285.23:24:16.91#ibcon#about to read 6, iclass 7, count 0 2006.285.23:24:16.91#ibcon#read 6, iclass 7, count 0 2006.285.23:24:16.91#ibcon#end of sib2, iclass 7, count 0 2006.285.23:24:16.91#ibcon#*after write, iclass 7, count 0 2006.285.23:24:16.91#ibcon#*before return 0, iclass 7, count 0 2006.285.23:24:16.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:24:16.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:24:16.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:24:16.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:24:16.91$vck44/vb=3,4 2006.285.23:24:16.91#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.23:24:16.91#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.23:24:16.91#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:16.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:24:16.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:24:16.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:24:16.97#ibcon#enter wrdev, iclass 11, count 2 2006.285.23:24:16.97#ibcon#first serial, iclass 11, count 2 2006.285.23:24:16.97#ibcon#enter sib2, iclass 11, count 2 2006.285.23:24:16.97#ibcon#flushed, iclass 11, count 2 2006.285.23:24:16.97#ibcon#about to write, iclass 11, count 2 2006.285.23:24:16.97#ibcon#wrote, iclass 11, count 2 2006.285.23:24:16.97#ibcon#about to read 3, iclass 11, count 2 2006.285.23:24:16.99#ibcon#read 3, iclass 11, count 2 2006.285.23:24:16.99#ibcon#about to read 4, iclass 11, count 2 2006.285.23:24:16.99#ibcon#read 4, iclass 11, count 2 2006.285.23:24:16.99#ibcon#about to read 5, iclass 11, count 2 2006.285.23:24:16.99#ibcon#read 5, iclass 11, count 2 2006.285.23:24:16.99#ibcon#about to read 6, iclass 11, count 2 2006.285.23:24:16.99#ibcon#read 6, iclass 11, count 2 2006.285.23:24:16.99#ibcon#end of sib2, iclass 11, count 2 2006.285.23:24:16.99#ibcon#*mode == 0, iclass 11, count 2 2006.285.23:24:16.99#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.23:24:16.99#ibcon#[27=AT03-04\r\n] 2006.285.23:24:16.99#ibcon#*before write, iclass 11, count 2 2006.285.23:24:16.99#ibcon#enter sib2, iclass 11, count 2 2006.285.23:24:16.99#ibcon#flushed, iclass 11, count 2 2006.285.23:24:16.99#ibcon#about to write, iclass 11, count 2 2006.285.23:24:16.99#ibcon#wrote, iclass 11, count 2 2006.285.23:24:16.99#ibcon#about to read 3, iclass 11, count 2 2006.285.23:24:17.02#ibcon#read 3, iclass 11, count 2 2006.285.23:24:17.02#ibcon#about to read 4, iclass 11, count 2 2006.285.23:24:17.02#ibcon#read 4, iclass 11, count 2 2006.285.23:24:17.02#ibcon#about to read 5, iclass 11, count 2 2006.285.23:24:17.02#ibcon#read 5, iclass 11, count 2 2006.285.23:24:17.02#ibcon#about to read 6, iclass 11, count 2 2006.285.23:24:17.02#ibcon#read 6, iclass 11, count 2 2006.285.23:24:17.02#ibcon#end of sib2, iclass 11, count 2 2006.285.23:24:17.02#ibcon#*after write, iclass 11, count 2 2006.285.23:24:17.02#ibcon#*before return 0, iclass 11, count 2 2006.285.23:24:17.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:24:17.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:24:17.02#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.23:24:17.02#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:17.02#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:24:17.14#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:24:17.14#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:24:17.14#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:24:17.14#ibcon#first serial, iclass 11, count 0 2006.285.23:24:17.14#ibcon#enter sib2, iclass 11, count 0 2006.285.23:24:17.14#ibcon#flushed, iclass 11, count 0 2006.285.23:24:17.14#ibcon#about to write, iclass 11, count 0 2006.285.23:24:17.14#ibcon#wrote, iclass 11, count 0 2006.285.23:24:17.14#ibcon#about to read 3, iclass 11, count 0 2006.285.23:24:17.16#ibcon#read 3, iclass 11, count 0 2006.285.23:24:17.16#ibcon#about to read 4, iclass 11, count 0 2006.285.23:24:17.16#ibcon#read 4, iclass 11, count 0 2006.285.23:24:17.16#ibcon#about to read 5, iclass 11, count 0 2006.285.23:24:17.16#ibcon#read 5, iclass 11, count 0 2006.285.23:24:17.16#ibcon#about to read 6, iclass 11, count 0 2006.285.23:24:17.16#ibcon#read 6, iclass 11, count 0 2006.285.23:24:17.16#ibcon#end of sib2, iclass 11, count 0 2006.285.23:24:17.16#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:24:17.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:24:17.16#ibcon#[27=USB\r\n] 2006.285.23:24:17.16#ibcon#*before write, iclass 11, count 0 2006.285.23:24:17.16#ibcon#enter sib2, iclass 11, count 0 2006.285.23:24:17.16#ibcon#flushed, iclass 11, count 0 2006.285.23:24:17.16#ibcon#about to write, iclass 11, count 0 2006.285.23:24:17.16#ibcon#wrote, iclass 11, count 0 2006.285.23:24:17.16#ibcon#about to read 3, iclass 11, count 0 2006.285.23:24:17.19#ibcon#read 3, iclass 11, count 0 2006.285.23:24:17.19#ibcon#about to read 4, iclass 11, count 0 2006.285.23:24:17.19#ibcon#read 4, iclass 11, count 0 2006.285.23:24:17.19#ibcon#about to read 5, iclass 11, count 0 2006.285.23:24:17.19#ibcon#read 5, iclass 11, count 0 2006.285.23:24:17.19#ibcon#about to read 6, iclass 11, count 0 2006.285.23:24:17.19#ibcon#read 6, iclass 11, count 0 2006.285.23:24:17.19#ibcon#end of sib2, iclass 11, count 0 2006.285.23:24:17.19#ibcon#*after write, iclass 11, count 0 2006.285.23:24:17.19#ibcon#*before return 0, iclass 11, count 0 2006.285.23:24:17.19#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:24:17.19#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:24:17.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:24:17.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:24:17.19$vck44/vblo=4,679.99 2006.285.23:24:17.19#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.23:24:17.19#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.23:24:17.19#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:17.19#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:24:17.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:24:17.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:24:17.19#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:24:17.19#ibcon#first serial, iclass 13, count 0 2006.285.23:24:17.19#ibcon#enter sib2, iclass 13, count 0 2006.285.23:24:17.19#ibcon#flushed, iclass 13, count 0 2006.285.23:24:17.19#ibcon#about to write, iclass 13, count 0 2006.285.23:24:17.19#ibcon#wrote, iclass 13, count 0 2006.285.23:24:17.19#ibcon#about to read 3, iclass 13, count 0 2006.285.23:24:17.21#ibcon#read 3, iclass 13, count 0 2006.285.23:24:17.21#ibcon#about to read 4, iclass 13, count 0 2006.285.23:24:17.21#ibcon#read 4, iclass 13, count 0 2006.285.23:24:17.21#ibcon#about to read 5, iclass 13, count 0 2006.285.23:24:17.21#ibcon#read 5, iclass 13, count 0 2006.285.23:24:17.21#ibcon#about to read 6, iclass 13, count 0 2006.285.23:24:17.21#ibcon#read 6, iclass 13, count 0 2006.285.23:24:17.21#ibcon#end of sib2, iclass 13, count 0 2006.285.23:24:17.21#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:24:17.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:24:17.21#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:24:17.21#ibcon#*before write, iclass 13, count 0 2006.285.23:24:17.21#ibcon#enter sib2, iclass 13, count 0 2006.285.23:24:17.21#ibcon#flushed, iclass 13, count 0 2006.285.23:24:17.21#ibcon#about to write, iclass 13, count 0 2006.285.23:24:17.21#ibcon#wrote, iclass 13, count 0 2006.285.23:24:17.21#ibcon#about to read 3, iclass 13, count 0 2006.285.23:24:17.25#ibcon#read 3, iclass 13, count 0 2006.285.23:24:17.25#ibcon#about to read 4, iclass 13, count 0 2006.285.23:24:17.25#ibcon#read 4, iclass 13, count 0 2006.285.23:24:17.25#ibcon#about to read 5, iclass 13, count 0 2006.285.23:24:17.25#ibcon#read 5, iclass 13, count 0 2006.285.23:24:17.25#ibcon#about to read 6, iclass 13, count 0 2006.285.23:24:17.25#ibcon#read 6, iclass 13, count 0 2006.285.23:24:17.25#ibcon#end of sib2, iclass 13, count 0 2006.285.23:24:17.25#ibcon#*after write, iclass 13, count 0 2006.285.23:24:17.25#ibcon#*before return 0, iclass 13, count 0 2006.285.23:24:17.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:24:17.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:24:17.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:24:17.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:24:17.25$vck44/vb=4,5 2006.285.23:24:17.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.23:24:17.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.23:24:17.25#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:17.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:24:17.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:24:17.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:24:17.31#ibcon#enter wrdev, iclass 15, count 2 2006.285.23:24:17.31#ibcon#first serial, iclass 15, count 2 2006.285.23:24:17.31#ibcon#enter sib2, iclass 15, count 2 2006.285.23:24:17.31#ibcon#flushed, iclass 15, count 2 2006.285.23:24:17.31#ibcon#about to write, iclass 15, count 2 2006.285.23:24:17.31#ibcon#wrote, iclass 15, count 2 2006.285.23:24:17.31#ibcon#about to read 3, iclass 15, count 2 2006.285.23:24:17.33#ibcon#read 3, iclass 15, count 2 2006.285.23:24:17.33#ibcon#about to read 4, iclass 15, count 2 2006.285.23:24:17.33#ibcon#read 4, iclass 15, count 2 2006.285.23:24:17.33#ibcon#about to read 5, iclass 15, count 2 2006.285.23:24:17.33#ibcon#read 5, iclass 15, count 2 2006.285.23:24:17.33#ibcon#about to read 6, iclass 15, count 2 2006.285.23:24:17.33#ibcon#read 6, iclass 15, count 2 2006.285.23:24:17.33#ibcon#end of sib2, iclass 15, count 2 2006.285.23:24:17.33#ibcon#*mode == 0, iclass 15, count 2 2006.285.23:24:17.33#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.23:24:17.33#ibcon#[27=AT04-05\r\n] 2006.285.23:24:17.33#ibcon#*before write, iclass 15, count 2 2006.285.23:24:17.33#ibcon#enter sib2, iclass 15, count 2 2006.285.23:24:17.33#ibcon#flushed, iclass 15, count 2 2006.285.23:24:17.33#ibcon#about to write, iclass 15, count 2 2006.285.23:24:17.33#ibcon#wrote, iclass 15, count 2 2006.285.23:24:17.33#ibcon#about to read 3, iclass 15, count 2 2006.285.23:24:17.36#ibcon#read 3, iclass 15, count 2 2006.285.23:24:17.36#ibcon#about to read 4, iclass 15, count 2 2006.285.23:24:17.36#ibcon#read 4, iclass 15, count 2 2006.285.23:24:17.36#ibcon#about to read 5, iclass 15, count 2 2006.285.23:24:17.36#ibcon#read 5, iclass 15, count 2 2006.285.23:24:17.36#ibcon#about to read 6, iclass 15, count 2 2006.285.23:24:17.36#ibcon#read 6, iclass 15, count 2 2006.285.23:24:17.36#ibcon#end of sib2, iclass 15, count 2 2006.285.23:24:17.36#ibcon#*after write, iclass 15, count 2 2006.285.23:24:17.36#ibcon#*before return 0, iclass 15, count 2 2006.285.23:24:17.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:24:17.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:24:17.36#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.23:24:17.36#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:17.36#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:24:17.48#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:24:17.48#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:24:17.48#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:24:17.48#ibcon#first serial, iclass 15, count 0 2006.285.23:24:17.48#ibcon#enter sib2, iclass 15, count 0 2006.285.23:24:17.48#ibcon#flushed, iclass 15, count 0 2006.285.23:24:17.48#ibcon#about to write, iclass 15, count 0 2006.285.23:24:17.48#ibcon#wrote, iclass 15, count 0 2006.285.23:24:17.48#ibcon#about to read 3, iclass 15, count 0 2006.285.23:24:17.50#ibcon#read 3, iclass 15, count 0 2006.285.23:24:17.50#ibcon#about to read 4, iclass 15, count 0 2006.285.23:24:17.50#ibcon#read 4, iclass 15, count 0 2006.285.23:24:17.50#ibcon#about to read 5, iclass 15, count 0 2006.285.23:24:17.50#ibcon#read 5, iclass 15, count 0 2006.285.23:24:17.50#ibcon#about to read 6, iclass 15, count 0 2006.285.23:24:17.50#ibcon#read 6, iclass 15, count 0 2006.285.23:24:17.50#ibcon#end of sib2, iclass 15, count 0 2006.285.23:24:17.50#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:24:17.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:24:17.50#ibcon#[27=USB\r\n] 2006.285.23:24:17.50#ibcon#*before write, iclass 15, count 0 2006.285.23:24:17.50#ibcon#enter sib2, iclass 15, count 0 2006.285.23:24:17.50#ibcon#flushed, iclass 15, count 0 2006.285.23:24:17.50#ibcon#about to write, iclass 15, count 0 2006.285.23:24:17.50#ibcon#wrote, iclass 15, count 0 2006.285.23:24:17.50#ibcon#about to read 3, iclass 15, count 0 2006.285.23:24:17.53#ibcon#read 3, iclass 15, count 0 2006.285.23:24:17.53#ibcon#about to read 4, iclass 15, count 0 2006.285.23:24:17.53#ibcon#read 4, iclass 15, count 0 2006.285.23:24:17.53#ibcon#about to read 5, iclass 15, count 0 2006.285.23:24:17.53#ibcon#read 5, iclass 15, count 0 2006.285.23:24:17.53#ibcon#about to read 6, iclass 15, count 0 2006.285.23:24:17.53#ibcon#read 6, iclass 15, count 0 2006.285.23:24:17.53#ibcon#end of sib2, iclass 15, count 0 2006.285.23:24:17.53#ibcon#*after write, iclass 15, count 0 2006.285.23:24:17.53#ibcon#*before return 0, iclass 15, count 0 2006.285.23:24:17.53#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:24:17.53#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:24:17.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:24:17.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:24:17.53$vck44/vblo=5,709.99 2006.285.23:24:17.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.23:24:17.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.23:24:17.53#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:17.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:24:17.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:24:17.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:24:17.53#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:24:17.53#ibcon#first serial, iclass 17, count 0 2006.285.23:24:17.53#ibcon#enter sib2, iclass 17, count 0 2006.285.23:24:17.53#ibcon#flushed, iclass 17, count 0 2006.285.23:24:17.53#ibcon#about to write, iclass 17, count 0 2006.285.23:24:17.53#ibcon#wrote, iclass 17, count 0 2006.285.23:24:17.53#ibcon#about to read 3, iclass 17, count 0 2006.285.23:24:17.55#ibcon#read 3, iclass 17, count 0 2006.285.23:24:17.55#ibcon#about to read 4, iclass 17, count 0 2006.285.23:24:17.55#ibcon#read 4, iclass 17, count 0 2006.285.23:24:17.55#ibcon#about to read 5, iclass 17, count 0 2006.285.23:24:17.55#ibcon#read 5, iclass 17, count 0 2006.285.23:24:17.55#ibcon#about to read 6, iclass 17, count 0 2006.285.23:24:17.55#ibcon#read 6, iclass 17, count 0 2006.285.23:24:17.55#ibcon#end of sib2, iclass 17, count 0 2006.285.23:24:17.55#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:24:17.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:24:17.55#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:24:17.55#ibcon#*before write, iclass 17, count 0 2006.285.23:24:17.55#ibcon#enter sib2, iclass 17, count 0 2006.285.23:24:17.55#ibcon#flushed, iclass 17, count 0 2006.285.23:24:17.55#ibcon#about to write, iclass 17, count 0 2006.285.23:24:17.55#ibcon#wrote, iclass 17, count 0 2006.285.23:24:17.55#ibcon#about to read 3, iclass 17, count 0 2006.285.23:24:17.59#ibcon#read 3, iclass 17, count 0 2006.285.23:24:17.59#ibcon#about to read 4, iclass 17, count 0 2006.285.23:24:17.59#ibcon#read 4, iclass 17, count 0 2006.285.23:24:17.59#ibcon#about to read 5, iclass 17, count 0 2006.285.23:24:17.59#ibcon#read 5, iclass 17, count 0 2006.285.23:24:17.59#ibcon#about to read 6, iclass 17, count 0 2006.285.23:24:17.59#ibcon#read 6, iclass 17, count 0 2006.285.23:24:17.59#ibcon#end of sib2, iclass 17, count 0 2006.285.23:24:17.59#ibcon#*after write, iclass 17, count 0 2006.285.23:24:17.59#ibcon#*before return 0, iclass 17, count 0 2006.285.23:24:17.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:24:17.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:24:17.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:24:17.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:24:17.59$vck44/vb=5,4 2006.285.23:24:17.59#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.23:24:17.59#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.23:24:17.59#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:17.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:24:17.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:24:17.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:24:17.65#ibcon#enter wrdev, iclass 19, count 2 2006.285.23:24:17.65#ibcon#first serial, iclass 19, count 2 2006.285.23:24:17.65#ibcon#enter sib2, iclass 19, count 2 2006.285.23:24:17.65#ibcon#flushed, iclass 19, count 2 2006.285.23:24:17.65#ibcon#about to write, iclass 19, count 2 2006.285.23:24:17.65#ibcon#wrote, iclass 19, count 2 2006.285.23:24:17.65#ibcon#about to read 3, iclass 19, count 2 2006.285.23:24:17.67#ibcon#read 3, iclass 19, count 2 2006.285.23:24:17.67#ibcon#about to read 4, iclass 19, count 2 2006.285.23:24:17.67#ibcon#read 4, iclass 19, count 2 2006.285.23:24:17.67#ibcon#about to read 5, iclass 19, count 2 2006.285.23:24:17.67#ibcon#read 5, iclass 19, count 2 2006.285.23:24:17.67#ibcon#about to read 6, iclass 19, count 2 2006.285.23:24:17.67#ibcon#read 6, iclass 19, count 2 2006.285.23:24:17.67#ibcon#end of sib2, iclass 19, count 2 2006.285.23:24:17.67#ibcon#*mode == 0, iclass 19, count 2 2006.285.23:24:17.67#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.23:24:17.67#ibcon#[27=AT05-04\r\n] 2006.285.23:24:17.67#ibcon#*before write, iclass 19, count 2 2006.285.23:24:17.67#ibcon#enter sib2, iclass 19, count 2 2006.285.23:24:17.67#ibcon#flushed, iclass 19, count 2 2006.285.23:24:17.67#ibcon#about to write, iclass 19, count 2 2006.285.23:24:17.67#ibcon#wrote, iclass 19, count 2 2006.285.23:24:17.67#ibcon#about to read 3, iclass 19, count 2 2006.285.23:24:17.70#ibcon#read 3, iclass 19, count 2 2006.285.23:24:17.70#ibcon#about to read 4, iclass 19, count 2 2006.285.23:24:17.70#ibcon#read 4, iclass 19, count 2 2006.285.23:24:17.70#ibcon#about to read 5, iclass 19, count 2 2006.285.23:24:17.70#ibcon#read 5, iclass 19, count 2 2006.285.23:24:17.70#ibcon#about to read 6, iclass 19, count 2 2006.285.23:24:17.70#ibcon#read 6, iclass 19, count 2 2006.285.23:24:17.70#ibcon#end of sib2, iclass 19, count 2 2006.285.23:24:17.70#ibcon#*after write, iclass 19, count 2 2006.285.23:24:17.70#ibcon#*before return 0, iclass 19, count 2 2006.285.23:24:17.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:24:17.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:24:17.70#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.23:24:17.70#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:17.70#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:24:17.82#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:24:17.82#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:24:17.82#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:24:17.82#ibcon#first serial, iclass 19, count 0 2006.285.23:24:17.82#ibcon#enter sib2, iclass 19, count 0 2006.285.23:24:17.82#ibcon#flushed, iclass 19, count 0 2006.285.23:24:17.82#ibcon#about to write, iclass 19, count 0 2006.285.23:24:17.82#ibcon#wrote, iclass 19, count 0 2006.285.23:24:17.82#ibcon#about to read 3, iclass 19, count 0 2006.285.23:24:17.84#ibcon#read 3, iclass 19, count 0 2006.285.23:24:17.84#ibcon#about to read 4, iclass 19, count 0 2006.285.23:24:17.84#ibcon#read 4, iclass 19, count 0 2006.285.23:24:17.84#ibcon#about to read 5, iclass 19, count 0 2006.285.23:24:17.84#ibcon#read 5, iclass 19, count 0 2006.285.23:24:17.84#ibcon#about to read 6, iclass 19, count 0 2006.285.23:24:17.84#ibcon#read 6, iclass 19, count 0 2006.285.23:24:17.84#ibcon#end of sib2, iclass 19, count 0 2006.285.23:24:17.84#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:24:17.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:24:17.84#ibcon#[27=USB\r\n] 2006.285.23:24:17.84#ibcon#*before write, iclass 19, count 0 2006.285.23:24:17.84#ibcon#enter sib2, iclass 19, count 0 2006.285.23:24:17.84#ibcon#flushed, iclass 19, count 0 2006.285.23:24:17.84#ibcon#about to write, iclass 19, count 0 2006.285.23:24:17.84#ibcon#wrote, iclass 19, count 0 2006.285.23:24:17.84#ibcon#about to read 3, iclass 19, count 0 2006.285.23:24:17.87#ibcon#read 3, iclass 19, count 0 2006.285.23:24:17.87#ibcon#about to read 4, iclass 19, count 0 2006.285.23:24:17.87#ibcon#read 4, iclass 19, count 0 2006.285.23:24:17.87#ibcon#about to read 5, iclass 19, count 0 2006.285.23:24:17.87#ibcon#read 5, iclass 19, count 0 2006.285.23:24:17.87#ibcon#about to read 6, iclass 19, count 0 2006.285.23:24:17.87#ibcon#read 6, iclass 19, count 0 2006.285.23:24:17.87#ibcon#end of sib2, iclass 19, count 0 2006.285.23:24:17.87#ibcon#*after write, iclass 19, count 0 2006.285.23:24:17.87#ibcon#*before return 0, iclass 19, count 0 2006.285.23:24:17.87#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:24:17.87#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:24:17.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:24:17.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:24:17.87$vck44/vblo=6,719.99 2006.285.23:24:17.87#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.23:24:17.87#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.23:24:17.87#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:17.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:24:17.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:24:17.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:24:17.87#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:24:17.87#ibcon#first serial, iclass 21, count 0 2006.285.23:24:17.87#ibcon#enter sib2, iclass 21, count 0 2006.285.23:24:17.87#ibcon#flushed, iclass 21, count 0 2006.285.23:24:17.87#ibcon#about to write, iclass 21, count 0 2006.285.23:24:17.87#ibcon#wrote, iclass 21, count 0 2006.285.23:24:17.87#ibcon#about to read 3, iclass 21, count 0 2006.285.23:24:17.89#ibcon#read 3, iclass 21, count 0 2006.285.23:24:17.89#ibcon#about to read 4, iclass 21, count 0 2006.285.23:24:17.89#ibcon#read 4, iclass 21, count 0 2006.285.23:24:17.89#ibcon#about to read 5, iclass 21, count 0 2006.285.23:24:17.89#ibcon#read 5, iclass 21, count 0 2006.285.23:24:17.89#ibcon#about to read 6, iclass 21, count 0 2006.285.23:24:17.89#ibcon#read 6, iclass 21, count 0 2006.285.23:24:17.89#ibcon#end of sib2, iclass 21, count 0 2006.285.23:24:17.89#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:24:17.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:24:17.89#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:24:17.89#ibcon#*before write, iclass 21, count 0 2006.285.23:24:17.89#ibcon#enter sib2, iclass 21, count 0 2006.285.23:24:17.89#ibcon#flushed, iclass 21, count 0 2006.285.23:24:17.89#ibcon#about to write, iclass 21, count 0 2006.285.23:24:17.89#ibcon#wrote, iclass 21, count 0 2006.285.23:24:17.89#ibcon#about to read 3, iclass 21, count 0 2006.285.23:24:17.93#ibcon#read 3, iclass 21, count 0 2006.285.23:24:17.93#ibcon#about to read 4, iclass 21, count 0 2006.285.23:24:17.93#ibcon#read 4, iclass 21, count 0 2006.285.23:24:17.93#ibcon#about to read 5, iclass 21, count 0 2006.285.23:24:17.93#ibcon#read 5, iclass 21, count 0 2006.285.23:24:17.93#ibcon#about to read 6, iclass 21, count 0 2006.285.23:24:17.93#ibcon#read 6, iclass 21, count 0 2006.285.23:24:17.93#ibcon#end of sib2, iclass 21, count 0 2006.285.23:24:17.93#ibcon#*after write, iclass 21, count 0 2006.285.23:24:17.93#ibcon#*before return 0, iclass 21, count 0 2006.285.23:24:17.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:24:17.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:24:17.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:24:17.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:24:17.93$vck44/vb=6,3 2006.285.23:24:17.93#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.23:24:17.93#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.23:24:17.93#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:17.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:24:17.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:24:17.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:24:17.99#ibcon#enter wrdev, iclass 23, count 2 2006.285.23:24:17.99#ibcon#first serial, iclass 23, count 2 2006.285.23:24:17.99#ibcon#enter sib2, iclass 23, count 2 2006.285.23:24:17.99#ibcon#flushed, iclass 23, count 2 2006.285.23:24:17.99#ibcon#about to write, iclass 23, count 2 2006.285.23:24:17.99#ibcon#wrote, iclass 23, count 2 2006.285.23:24:17.99#ibcon#about to read 3, iclass 23, count 2 2006.285.23:24:18.01#ibcon#read 3, iclass 23, count 2 2006.285.23:24:18.01#ibcon#about to read 4, iclass 23, count 2 2006.285.23:24:18.01#ibcon#read 4, iclass 23, count 2 2006.285.23:24:18.01#ibcon#about to read 5, iclass 23, count 2 2006.285.23:24:18.01#ibcon#read 5, iclass 23, count 2 2006.285.23:24:18.01#ibcon#about to read 6, iclass 23, count 2 2006.285.23:24:18.01#ibcon#read 6, iclass 23, count 2 2006.285.23:24:18.01#ibcon#end of sib2, iclass 23, count 2 2006.285.23:24:18.01#ibcon#*mode == 0, iclass 23, count 2 2006.285.23:24:18.01#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.23:24:18.01#ibcon#[27=AT06-03\r\n] 2006.285.23:24:18.01#ibcon#*before write, iclass 23, count 2 2006.285.23:24:18.01#ibcon#enter sib2, iclass 23, count 2 2006.285.23:24:18.01#ibcon#flushed, iclass 23, count 2 2006.285.23:24:18.01#ibcon#about to write, iclass 23, count 2 2006.285.23:24:18.01#ibcon#wrote, iclass 23, count 2 2006.285.23:24:18.01#ibcon#about to read 3, iclass 23, count 2 2006.285.23:24:18.04#ibcon#read 3, iclass 23, count 2 2006.285.23:24:18.04#ibcon#about to read 4, iclass 23, count 2 2006.285.23:24:18.04#ibcon#read 4, iclass 23, count 2 2006.285.23:24:18.04#ibcon#about to read 5, iclass 23, count 2 2006.285.23:24:18.04#ibcon#read 5, iclass 23, count 2 2006.285.23:24:18.04#ibcon#about to read 6, iclass 23, count 2 2006.285.23:24:18.04#ibcon#read 6, iclass 23, count 2 2006.285.23:24:18.04#ibcon#end of sib2, iclass 23, count 2 2006.285.23:24:18.04#ibcon#*after write, iclass 23, count 2 2006.285.23:24:18.04#ibcon#*before return 0, iclass 23, count 2 2006.285.23:24:18.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:24:18.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:24:18.04#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.23:24:18.04#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:18.04#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:24:18.16#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:24:18.16#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:24:18.16#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:24:18.16#ibcon#first serial, iclass 23, count 0 2006.285.23:24:18.16#ibcon#enter sib2, iclass 23, count 0 2006.285.23:24:18.16#ibcon#flushed, iclass 23, count 0 2006.285.23:24:18.16#ibcon#about to write, iclass 23, count 0 2006.285.23:24:18.16#ibcon#wrote, iclass 23, count 0 2006.285.23:24:18.16#ibcon#about to read 3, iclass 23, count 0 2006.285.23:24:18.18#ibcon#read 3, iclass 23, count 0 2006.285.23:24:18.18#ibcon#about to read 4, iclass 23, count 0 2006.285.23:24:18.18#ibcon#read 4, iclass 23, count 0 2006.285.23:24:18.18#ibcon#about to read 5, iclass 23, count 0 2006.285.23:24:18.18#ibcon#read 5, iclass 23, count 0 2006.285.23:24:18.18#ibcon#about to read 6, iclass 23, count 0 2006.285.23:24:18.18#ibcon#read 6, iclass 23, count 0 2006.285.23:24:18.18#ibcon#end of sib2, iclass 23, count 0 2006.285.23:24:18.18#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:24:18.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:24:18.18#ibcon#[27=USB\r\n] 2006.285.23:24:18.18#ibcon#*before write, iclass 23, count 0 2006.285.23:24:18.18#ibcon#enter sib2, iclass 23, count 0 2006.285.23:24:18.18#ibcon#flushed, iclass 23, count 0 2006.285.23:24:18.18#ibcon#about to write, iclass 23, count 0 2006.285.23:24:18.18#ibcon#wrote, iclass 23, count 0 2006.285.23:24:18.18#ibcon#about to read 3, iclass 23, count 0 2006.285.23:24:18.21#ibcon#read 3, iclass 23, count 0 2006.285.23:24:18.21#ibcon#about to read 4, iclass 23, count 0 2006.285.23:24:18.21#ibcon#read 4, iclass 23, count 0 2006.285.23:24:18.21#ibcon#about to read 5, iclass 23, count 0 2006.285.23:24:18.21#ibcon#read 5, iclass 23, count 0 2006.285.23:24:18.21#ibcon#about to read 6, iclass 23, count 0 2006.285.23:24:18.21#ibcon#read 6, iclass 23, count 0 2006.285.23:24:18.21#ibcon#end of sib2, iclass 23, count 0 2006.285.23:24:18.21#ibcon#*after write, iclass 23, count 0 2006.285.23:24:18.21#ibcon#*before return 0, iclass 23, count 0 2006.285.23:24:18.21#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:24:18.21#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:24:18.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:24:18.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:24:18.21$vck44/vblo=7,734.99 2006.285.23:24:18.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.23:24:18.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.23:24:18.21#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:18.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:24:18.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:24:18.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:24:18.21#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:24:18.21#ibcon#first serial, iclass 25, count 0 2006.285.23:24:18.21#ibcon#enter sib2, iclass 25, count 0 2006.285.23:24:18.21#ibcon#flushed, iclass 25, count 0 2006.285.23:24:18.21#ibcon#about to write, iclass 25, count 0 2006.285.23:24:18.21#ibcon#wrote, iclass 25, count 0 2006.285.23:24:18.21#ibcon#about to read 3, iclass 25, count 0 2006.285.23:24:18.23#ibcon#read 3, iclass 25, count 0 2006.285.23:24:18.23#ibcon#about to read 4, iclass 25, count 0 2006.285.23:24:18.23#ibcon#read 4, iclass 25, count 0 2006.285.23:24:18.23#ibcon#about to read 5, iclass 25, count 0 2006.285.23:24:18.23#ibcon#read 5, iclass 25, count 0 2006.285.23:24:18.23#ibcon#about to read 6, iclass 25, count 0 2006.285.23:24:18.23#ibcon#read 6, iclass 25, count 0 2006.285.23:24:18.23#ibcon#end of sib2, iclass 25, count 0 2006.285.23:24:18.23#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:24:18.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:24:18.23#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:24:18.23#ibcon#*before write, iclass 25, count 0 2006.285.23:24:18.23#ibcon#enter sib2, iclass 25, count 0 2006.285.23:24:18.23#ibcon#flushed, iclass 25, count 0 2006.285.23:24:18.23#ibcon#about to write, iclass 25, count 0 2006.285.23:24:18.23#ibcon#wrote, iclass 25, count 0 2006.285.23:24:18.23#ibcon#about to read 3, iclass 25, count 0 2006.285.23:24:18.27#ibcon#read 3, iclass 25, count 0 2006.285.23:24:18.27#ibcon#about to read 4, iclass 25, count 0 2006.285.23:24:18.27#ibcon#read 4, iclass 25, count 0 2006.285.23:24:18.27#ibcon#about to read 5, iclass 25, count 0 2006.285.23:24:18.27#ibcon#read 5, iclass 25, count 0 2006.285.23:24:18.27#ibcon#about to read 6, iclass 25, count 0 2006.285.23:24:18.27#ibcon#read 6, iclass 25, count 0 2006.285.23:24:18.27#ibcon#end of sib2, iclass 25, count 0 2006.285.23:24:18.27#ibcon#*after write, iclass 25, count 0 2006.285.23:24:18.27#ibcon#*before return 0, iclass 25, count 0 2006.285.23:24:18.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:24:18.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:24:18.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:24:18.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:24:18.27$vck44/vb=7,4 2006.285.23:24:18.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.23:24:18.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.23:24:18.27#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:18.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:24:18.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:24:18.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:24:18.33#ibcon#enter wrdev, iclass 27, count 2 2006.285.23:24:18.33#ibcon#first serial, iclass 27, count 2 2006.285.23:24:18.33#ibcon#enter sib2, iclass 27, count 2 2006.285.23:24:18.33#ibcon#flushed, iclass 27, count 2 2006.285.23:24:18.33#ibcon#about to write, iclass 27, count 2 2006.285.23:24:18.33#ibcon#wrote, iclass 27, count 2 2006.285.23:24:18.33#ibcon#about to read 3, iclass 27, count 2 2006.285.23:24:18.35#ibcon#read 3, iclass 27, count 2 2006.285.23:24:18.35#ibcon#about to read 4, iclass 27, count 2 2006.285.23:24:18.35#ibcon#read 4, iclass 27, count 2 2006.285.23:24:18.35#ibcon#about to read 5, iclass 27, count 2 2006.285.23:24:18.35#ibcon#read 5, iclass 27, count 2 2006.285.23:24:18.35#ibcon#about to read 6, iclass 27, count 2 2006.285.23:24:18.35#ibcon#read 6, iclass 27, count 2 2006.285.23:24:18.35#ibcon#end of sib2, iclass 27, count 2 2006.285.23:24:18.35#ibcon#*mode == 0, iclass 27, count 2 2006.285.23:24:18.35#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.23:24:18.35#ibcon#[27=AT07-04\r\n] 2006.285.23:24:18.35#ibcon#*before write, iclass 27, count 2 2006.285.23:24:18.35#ibcon#enter sib2, iclass 27, count 2 2006.285.23:24:18.35#ibcon#flushed, iclass 27, count 2 2006.285.23:24:18.35#ibcon#about to write, iclass 27, count 2 2006.285.23:24:18.35#ibcon#wrote, iclass 27, count 2 2006.285.23:24:18.35#ibcon#about to read 3, iclass 27, count 2 2006.285.23:24:18.38#ibcon#read 3, iclass 27, count 2 2006.285.23:24:18.38#ibcon#about to read 4, iclass 27, count 2 2006.285.23:24:18.38#ibcon#read 4, iclass 27, count 2 2006.285.23:24:18.38#ibcon#about to read 5, iclass 27, count 2 2006.285.23:24:18.38#ibcon#read 5, iclass 27, count 2 2006.285.23:24:18.38#ibcon#about to read 6, iclass 27, count 2 2006.285.23:24:18.38#ibcon#read 6, iclass 27, count 2 2006.285.23:24:18.38#ibcon#end of sib2, iclass 27, count 2 2006.285.23:24:18.38#ibcon#*after write, iclass 27, count 2 2006.285.23:24:18.38#ibcon#*before return 0, iclass 27, count 2 2006.285.23:24:18.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:24:18.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:24:18.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.23:24:18.38#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:18.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:24:18.50#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:24:18.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:24:18.50#ibcon#enter wrdev, iclass 27, count 0 2006.285.23:24:18.50#ibcon#first serial, iclass 27, count 0 2006.285.23:24:18.50#ibcon#enter sib2, iclass 27, count 0 2006.285.23:24:18.50#ibcon#flushed, iclass 27, count 0 2006.285.23:24:18.50#ibcon#about to write, iclass 27, count 0 2006.285.23:24:18.50#ibcon#wrote, iclass 27, count 0 2006.285.23:24:18.50#ibcon#about to read 3, iclass 27, count 0 2006.285.23:24:18.52#ibcon#read 3, iclass 27, count 0 2006.285.23:24:18.52#ibcon#about to read 4, iclass 27, count 0 2006.285.23:24:18.52#ibcon#read 4, iclass 27, count 0 2006.285.23:24:18.52#ibcon#about to read 5, iclass 27, count 0 2006.285.23:24:18.52#ibcon#read 5, iclass 27, count 0 2006.285.23:24:18.52#ibcon#about to read 6, iclass 27, count 0 2006.285.23:24:18.52#ibcon#read 6, iclass 27, count 0 2006.285.23:24:18.52#ibcon#end of sib2, iclass 27, count 0 2006.285.23:24:18.52#ibcon#*mode == 0, iclass 27, count 0 2006.285.23:24:18.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.23:24:18.52#ibcon#[27=USB\r\n] 2006.285.23:24:18.52#ibcon#*before write, iclass 27, count 0 2006.285.23:24:18.52#ibcon#enter sib2, iclass 27, count 0 2006.285.23:24:18.52#ibcon#flushed, iclass 27, count 0 2006.285.23:24:18.52#ibcon#about to write, iclass 27, count 0 2006.285.23:24:18.52#ibcon#wrote, iclass 27, count 0 2006.285.23:24:18.52#ibcon#about to read 3, iclass 27, count 0 2006.285.23:24:18.55#ibcon#read 3, iclass 27, count 0 2006.285.23:24:18.55#ibcon#about to read 4, iclass 27, count 0 2006.285.23:24:18.55#ibcon#read 4, iclass 27, count 0 2006.285.23:24:18.55#ibcon#about to read 5, iclass 27, count 0 2006.285.23:24:18.55#ibcon#read 5, iclass 27, count 0 2006.285.23:24:18.55#ibcon#about to read 6, iclass 27, count 0 2006.285.23:24:18.55#ibcon#read 6, iclass 27, count 0 2006.285.23:24:18.55#ibcon#end of sib2, iclass 27, count 0 2006.285.23:24:18.55#ibcon#*after write, iclass 27, count 0 2006.285.23:24:18.55#ibcon#*before return 0, iclass 27, count 0 2006.285.23:24:18.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:24:18.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:24:18.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.23:24:18.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.23:24:18.55$vck44/vblo=8,744.99 2006.285.23:24:18.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.23:24:18.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.23:24:18.55#ibcon#ireg 17 cls_cnt 0 2006.285.23:24:18.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.23:24:18.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.23:24:18.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.23:24:18.55#ibcon#enter wrdev, iclass 29, count 0 2006.285.23:24:18.55#ibcon#first serial, iclass 29, count 0 2006.285.23:24:18.55#ibcon#enter sib2, iclass 29, count 0 2006.285.23:24:18.55#ibcon#flushed, iclass 29, count 0 2006.285.23:24:18.55#ibcon#about to write, iclass 29, count 0 2006.285.23:24:18.55#ibcon#wrote, iclass 29, count 0 2006.285.23:24:18.55#ibcon#about to read 3, iclass 29, count 0 2006.285.23:24:18.57#ibcon#read 3, iclass 29, count 0 2006.285.23:24:18.57#ibcon#about to read 4, iclass 29, count 0 2006.285.23:24:18.57#ibcon#read 4, iclass 29, count 0 2006.285.23:24:18.57#ibcon#about to read 5, iclass 29, count 0 2006.285.23:24:18.57#ibcon#read 5, iclass 29, count 0 2006.285.23:24:18.57#ibcon#about to read 6, iclass 29, count 0 2006.285.23:24:18.57#ibcon#read 6, iclass 29, count 0 2006.285.23:24:18.57#ibcon#end of sib2, iclass 29, count 0 2006.285.23:24:18.57#ibcon#*mode == 0, iclass 29, count 0 2006.285.23:24:18.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.23:24:18.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:24:18.57#ibcon#*before write, iclass 29, count 0 2006.285.23:24:18.57#ibcon#enter sib2, iclass 29, count 0 2006.285.23:24:18.57#ibcon#flushed, iclass 29, count 0 2006.285.23:24:18.57#ibcon#about to write, iclass 29, count 0 2006.285.23:24:18.57#ibcon#wrote, iclass 29, count 0 2006.285.23:24:18.57#ibcon#about to read 3, iclass 29, count 0 2006.285.23:24:18.61#ibcon#read 3, iclass 29, count 0 2006.285.23:24:18.61#ibcon#about to read 4, iclass 29, count 0 2006.285.23:24:18.61#ibcon#read 4, iclass 29, count 0 2006.285.23:24:18.61#ibcon#about to read 5, iclass 29, count 0 2006.285.23:24:18.61#ibcon#read 5, iclass 29, count 0 2006.285.23:24:18.61#ibcon#about to read 6, iclass 29, count 0 2006.285.23:24:18.61#ibcon#read 6, iclass 29, count 0 2006.285.23:24:18.61#ibcon#end of sib2, iclass 29, count 0 2006.285.23:24:18.61#ibcon#*after write, iclass 29, count 0 2006.285.23:24:18.61#ibcon#*before return 0, iclass 29, count 0 2006.285.23:24:18.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.23:24:18.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.23:24:18.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.23:24:18.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.23:24:18.61$vck44/vb=8,4 2006.285.23:24:18.61#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.23:24:18.61#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.23:24:18.61#ibcon#ireg 11 cls_cnt 2 2006.285.23:24:18.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.23:24:18.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.23:24:18.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.23:24:18.67#ibcon#enter wrdev, iclass 31, count 2 2006.285.23:24:18.67#ibcon#first serial, iclass 31, count 2 2006.285.23:24:18.67#ibcon#enter sib2, iclass 31, count 2 2006.285.23:24:18.67#ibcon#flushed, iclass 31, count 2 2006.285.23:24:18.67#ibcon#about to write, iclass 31, count 2 2006.285.23:24:18.67#ibcon#wrote, iclass 31, count 2 2006.285.23:24:18.67#ibcon#about to read 3, iclass 31, count 2 2006.285.23:24:18.69#ibcon#read 3, iclass 31, count 2 2006.285.23:24:18.69#ibcon#about to read 4, iclass 31, count 2 2006.285.23:24:18.69#ibcon#read 4, iclass 31, count 2 2006.285.23:24:18.69#ibcon#about to read 5, iclass 31, count 2 2006.285.23:24:18.69#ibcon#read 5, iclass 31, count 2 2006.285.23:24:18.69#ibcon#about to read 6, iclass 31, count 2 2006.285.23:24:18.69#ibcon#read 6, iclass 31, count 2 2006.285.23:24:18.69#ibcon#end of sib2, iclass 31, count 2 2006.285.23:24:18.69#ibcon#*mode == 0, iclass 31, count 2 2006.285.23:24:18.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.23:24:18.69#ibcon#[27=AT08-04\r\n] 2006.285.23:24:18.69#ibcon#*before write, iclass 31, count 2 2006.285.23:24:18.69#ibcon#enter sib2, iclass 31, count 2 2006.285.23:24:18.69#ibcon#flushed, iclass 31, count 2 2006.285.23:24:18.69#ibcon#about to write, iclass 31, count 2 2006.285.23:24:18.69#ibcon#wrote, iclass 31, count 2 2006.285.23:24:18.69#ibcon#about to read 3, iclass 31, count 2 2006.285.23:24:18.72#ibcon#read 3, iclass 31, count 2 2006.285.23:24:18.72#ibcon#about to read 4, iclass 31, count 2 2006.285.23:24:18.72#ibcon#read 4, iclass 31, count 2 2006.285.23:24:18.72#ibcon#about to read 5, iclass 31, count 2 2006.285.23:24:18.72#ibcon#read 5, iclass 31, count 2 2006.285.23:24:18.72#ibcon#about to read 6, iclass 31, count 2 2006.285.23:24:18.72#ibcon#read 6, iclass 31, count 2 2006.285.23:24:18.72#ibcon#end of sib2, iclass 31, count 2 2006.285.23:24:18.72#ibcon#*after write, iclass 31, count 2 2006.285.23:24:18.72#ibcon#*before return 0, iclass 31, count 2 2006.285.23:24:18.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.23:24:18.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.23:24:18.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.23:24:18.72#ibcon#ireg 7 cls_cnt 0 2006.285.23:24:18.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.23:24:18.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.23:24:18.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.23:24:18.84#ibcon#enter wrdev, iclass 31, count 0 2006.285.23:24:18.84#ibcon#first serial, iclass 31, count 0 2006.285.23:24:18.84#ibcon#enter sib2, iclass 31, count 0 2006.285.23:24:18.84#ibcon#flushed, iclass 31, count 0 2006.285.23:24:18.84#ibcon#about to write, iclass 31, count 0 2006.285.23:24:18.84#ibcon#wrote, iclass 31, count 0 2006.285.23:24:18.84#ibcon#about to read 3, iclass 31, count 0 2006.285.23:24:18.86#ibcon#read 3, iclass 31, count 0 2006.285.23:24:18.86#ibcon#about to read 4, iclass 31, count 0 2006.285.23:24:18.86#ibcon#read 4, iclass 31, count 0 2006.285.23:24:18.86#ibcon#about to read 5, iclass 31, count 0 2006.285.23:24:18.86#ibcon#read 5, iclass 31, count 0 2006.285.23:24:18.86#ibcon#about to read 6, iclass 31, count 0 2006.285.23:24:18.86#ibcon#read 6, iclass 31, count 0 2006.285.23:24:18.86#ibcon#end of sib2, iclass 31, count 0 2006.285.23:24:18.86#ibcon#*mode == 0, iclass 31, count 0 2006.285.23:24:18.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.23:24:18.86#ibcon#[27=USB\r\n] 2006.285.23:24:18.86#ibcon#*before write, iclass 31, count 0 2006.285.23:24:18.86#ibcon#enter sib2, iclass 31, count 0 2006.285.23:24:18.86#ibcon#flushed, iclass 31, count 0 2006.285.23:24:18.86#ibcon#about to write, iclass 31, count 0 2006.285.23:24:18.86#ibcon#wrote, iclass 31, count 0 2006.285.23:24:18.86#ibcon#about to read 3, iclass 31, count 0 2006.285.23:24:18.89#ibcon#read 3, iclass 31, count 0 2006.285.23:24:18.89#ibcon#about to read 4, iclass 31, count 0 2006.285.23:24:18.89#ibcon#read 4, iclass 31, count 0 2006.285.23:24:18.89#ibcon#about to read 5, iclass 31, count 0 2006.285.23:24:18.89#ibcon#read 5, iclass 31, count 0 2006.285.23:24:18.89#ibcon#about to read 6, iclass 31, count 0 2006.285.23:24:18.89#ibcon#read 6, iclass 31, count 0 2006.285.23:24:18.89#ibcon#end of sib2, iclass 31, count 0 2006.285.23:24:18.89#ibcon#*after write, iclass 31, count 0 2006.285.23:24:18.89#ibcon#*before return 0, iclass 31, count 0 2006.285.23:24:18.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.23:24:18.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.23:24:18.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.23:24:18.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.23:24:18.89$vck44/vabw=wide 2006.285.23:24:18.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.23:24:18.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.23:24:18.89#ibcon#ireg 8 cls_cnt 0 2006.285.23:24:18.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:24:18.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:24:18.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:24:18.89#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:24:18.89#ibcon#first serial, iclass 33, count 0 2006.285.23:24:18.89#ibcon#enter sib2, iclass 33, count 0 2006.285.23:24:18.89#ibcon#flushed, iclass 33, count 0 2006.285.23:24:18.89#ibcon#about to write, iclass 33, count 0 2006.285.23:24:18.89#ibcon#wrote, iclass 33, count 0 2006.285.23:24:18.89#ibcon#about to read 3, iclass 33, count 0 2006.285.23:24:18.91#ibcon#read 3, iclass 33, count 0 2006.285.23:24:18.91#ibcon#about to read 4, iclass 33, count 0 2006.285.23:24:18.91#ibcon#read 4, iclass 33, count 0 2006.285.23:24:18.91#ibcon#about to read 5, iclass 33, count 0 2006.285.23:24:18.91#ibcon#read 5, iclass 33, count 0 2006.285.23:24:18.91#ibcon#about to read 6, iclass 33, count 0 2006.285.23:24:18.91#ibcon#read 6, iclass 33, count 0 2006.285.23:24:18.91#ibcon#end of sib2, iclass 33, count 0 2006.285.23:24:18.91#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:24:18.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:24:18.91#ibcon#[25=BW32\r\n] 2006.285.23:24:18.91#ibcon#*before write, iclass 33, count 0 2006.285.23:24:18.91#ibcon#enter sib2, iclass 33, count 0 2006.285.23:24:18.91#ibcon#flushed, iclass 33, count 0 2006.285.23:24:18.91#ibcon#about to write, iclass 33, count 0 2006.285.23:24:18.91#ibcon#wrote, iclass 33, count 0 2006.285.23:24:18.91#ibcon#about to read 3, iclass 33, count 0 2006.285.23:24:18.94#ibcon#read 3, iclass 33, count 0 2006.285.23:24:18.94#ibcon#about to read 4, iclass 33, count 0 2006.285.23:24:18.94#ibcon#read 4, iclass 33, count 0 2006.285.23:24:18.94#ibcon#about to read 5, iclass 33, count 0 2006.285.23:24:18.94#ibcon#read 5, iclass 33, count 0 2006.285.23:24:18.94#ibcon#about to read 6, iclass 33, count 0 2006.285.23:24:18.94#ibcon#read 6, iclass 33, count 0 2006.285.23:24:18.94#ibcon#end of sib2, iclass 33, count 0 2006.285.23:24:18.94#ibcon#*after write, iclass 33, count 0 2006.285.23:24:18.94#ibcon#*before return 0, iclass 33, count 0 2006.285.23:24:18.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:24:18.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:24:18.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:24:18.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:24:18.94$vck44/vbbw=wide 2006.285.23:24:18.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.23:24:18.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.23:24:18.94#ibcon#ireg 8 cls_cnt 0 2006.285.23:24:18.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:24:19.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:24:19.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:24:19.01#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:24:19.01#ibcon#first serial, iclass 35, count 0 2006.285.23:24:19.01#ibcon#enter sib2, iclass 35, count 0 2006.285.23:24:19.01#ibcon#flushed, iclass 35, count 0 2006.285.23:24:19.01#ibcon#about to write, iclass 35, count 0 2006.285.23:24:19.01#ibcon#wrote, iclass 35, count 0 2006.285.23:24:19.01#ibcon#about to read 3, iclass 35, count 0 2006.285.23:24:19.03#ibcon#read 3, iclass 35, count 0 2006.285.23:24:19.03#ibcon#about to read 4, iclass 35, count 0 2006.285.23:24:19.03#ibcon#read 4, iclass 35, count 0 2006.285.23:24:19.03#ibcon#about to read 5, iclass 35, count 0 2006.285.23:24:19.03#ibcon#read 5, iclass 35, count 0 2006.285.23:24:19.03#ibcon#about to read 6, iclass 35, count 0 2006.285.23:24:19.03#ibcon#read 6, iclass 35, count 0 2006.285.23:24:19.03#ibcon#end of sib2, iclass 35, count 0 2006.285.23:24:19.03#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:24:19.03#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:24:19.03#ibcon#[27=BW32\r\n] 2006.285.23:24:19.03#ibcon#*before write, iclass 35, count 0 2006.285.23:24:19.03#ibcon#enter sib2, iclass 35, count 0 2006.285.23:24:19.03#ibcon#flushed, iclass 35, count 0 2006.285.23:24:19.03#ibcon#about to write, iclass 35, count 0 2006.285.23:24:19.03#ibcon#wrote, iclass 35, count 0 2006.285.23:24:19.03#ibcon#about to read 3, iclass 35, count 0 2006.285.23:24:19.06#ibcon#read 3, iclass 35, count 0 2006.285.23:24:19.06#ibcon#about to read 4, iclass 35, count 0 2006.285.23:24:19.06#ibcon#read 4, iclass 35, count 0 2006.285.23:24:19.06#ibcon#about to read 5, iclass 35, count 0 2006.285.23:24:19.06#ibcon#read 5, iclass 35, count 0 2006.285.23:24:19.06#ibcon#about to read 6, iclass 35, count 0 2006.285.23:24:19.06#ibcon#read 6, iclass 35, count 0 2006.285.23:24:19.06#ibcon#end of sib2, iclass 35, count 0 2006.285.23:24:19.06#ibcon#*after write, iclass 35, count 0 2006.285.23:24:19.06#ibcon#*before return 0, iclass 35, count 0 2006.285.23:24:19.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:24:19.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:24:19.06#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:24:19.06#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:24:19.06$setupk4/ifdk4 2006.285.23:24:19.06$ifdk4/lo= 2006.285.23:24:19.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:24:19.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:24:19.06$ifdk4/patch= 2006.285.23:24:19.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:24:19.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:24:19.06$setupk4/!*+20s 2006.285.23:24:25.87#abcon#<5=/03 3.6 7.6 19.23 891016.4\r\n> 2006.285.23:24:25.89#abcon#{5=INTERFACE CLEAR} 2006.285.23:24:25.95#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:24:30.13#trakl#Source acquired 2006.285.23:24:30.13#flagr#flagr/antenna,acquired 2006.285.23:24:33.57$setupk4/"tpicd 2006.285.23:24:33.57$setupk4/echo=off 2006.285.23:24:33.57$setupk4/xlog=off 2006.285.23:24:33.57:!2006.285.23:26:39 2006.285.23:26:39.00:preob 2006.285.23:26:40.14/onsource/TRACKING 2006.285.23:26:40.14:!2006.285.23:26:49 2006.285.23:26:49.00:"tape 2006.285.23:26:49.00:"st=record 2006.285.23:26:49.00:data_valid=on 2006.285.23:26:49.00:midob 2006.285.23:26:49.14/onsource/TRACKING 2006.285.23:26:49.14/wx/19.27,1016.4,89 2006.285.23:26:49.28/cable/+6.5092E-03 2006.285.23:26:50.37/va/01,07,usb,yes,37,40 2006.285.23:26:50.37/va/02,06,usb,yes,37,37 2006.285.23:26:50.37/va/03,07,usb,yes,36,38 2006.285.23:26:50.37/va/04,06,usb,yes,38,40 2006.285.23:26:50.37/va/05,03,usb,yes,38,38 2006.285.23:26:50.37/va/06,04,usb,yes,34,33 2006.285.23:26:50.37/va/07,04,usb,yes,35,35 2006.285.23:26:50.37/va/08,03,usb,yes,35,43 2006.285.23:26:50.60/valo/01,524.99,yes,locked 2006.285.23:26:50.60/valo/02,534.99,yes,locked 2006.285.23:26:50.60/valo/03,564.99,yes,locked 2006.285.23:26:50.60/valo/04,624.99,yes,locked 2006.285.23:26:50.60/valo/05,734.99,yes,locked 2006.285.23:26:50.60/valo/06,814.99,yes,locked 2006.285.23:26:50.60/valo/07,864.99,yes,locked 2006.285.23:26:50.60/valo/08,884.99,yes,locked 2006.285.23:26:51.69/vb/01,04,usb,yes,33,31 2006.285.23:26:51.69/vb/02,05,usb,yes,31,31 2006.285.23:26:51.69/vb/03,04,usb,yes,32,35 2006.285.23:26:51.69/vb/04,05,usb,yes,32,31 2006.285.23:26:51.69/vb/05,04,usb,yes,29,31 2006.285.23:26:51.69/vb/06,03,usb,yes,42,37 2006.285.23:26:51.69/vb/07,04,usb,yes,33,33 2006.285.23:26:51.69/vb/08,04,usb,yes,30,34 2006.285.23:26:51.92/vblo/01,629.99,yes,locked 2006.285.23:26:51.92/vblo/02,634.99,yes,locked 2006.285.23:26:51.92/vblo/03,649.99,yes,locked 2006.285.23:26:51.92/vblo/04,679.99,yes,locked 2006.285.23:26:51.92/vblo/05,709.99,yes,locked 2006.285.23:26:51.92/vblo/06,719.99,yes,locked 2006.285.23:26:51.92/vblo/07,734.99,yes,locked 2006.285.23:26:51.92/vblo/08,744.99,yes,locked 2006.285.23:26:52.07/vabw/8 2006.285.23:26:52.22/vbbw/8 2006.285.23:26:52.37/xfe/off,on,12.0 2006.285.23:26:52.76/ifatt/23,28,28,28 2006.285.23:26:53.07/fmout-gps/S +2.67E-07 2006.285.23:26:53.09:!2006.285.23:29:19 2006.285.23:29:19.00:data_valid=off 2006.285.23:29:19.00:"et 2006.285.23:29:19.00:!+3s 2006.285.23:29:22.01:"tape 2006.285.23:29:22.01:postob 2006.285.23:29:22.11/cable/+6.5087E-03 2006.285.23:29:22.11/wx/19.32,1016.5,88 2006.285.23:29:23.08/fmout-gps/S +2.74E-07 2006.285.23:29:23.08:scan_name=285-2330,jd0610,360 2006.285.23:29:23.08:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.285.23:29:23.14#flagr#flagr/antenna,new-source 2006.285.23:29:24.14:checkk5 2006.285.23:29:24.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.23:29:25.13/chk_autoobs//k5ts2/ autoobs is running! 2006.285.23:29:25.55/chk_autoobs//k5ts3/ autoobs is running! 2006.285.23:29:25.92/chk_autoobs//k5ts4/ autoobs is running! 2006.285.23:29:26.29/chk_obsdata//k5ts1/T2852326??a.dat file size is correct (nominal:600MB, actual:596MB). 2006.285.23:29:26.91/chk_obsdata//k5ts2/T2852326??b.dat file size is correct (nominal:600MB, actual:596MB). 2006.285.23:29:27.52/chk_obsdata//k5ts3/T2852326??c.dat file size is correct (nominal:600MB, actual:596MB). 2006.285.23:29:27.90/chk_obsdata//k5ts4/T2852326??d.dat file size is correct (nominal:600MB, actual:596MB). 2006.285.23:29:31.66/k5log//k5ts1_log_newline 2006.285.23:29:32.43/k5log//k5ts2_log_newline 2006.285.23:29:33.31/k5log//k5ts3_log_newline 2006.285.23:29:34.11/k5log//k5ts4_log_newline 2006.285.23:29:34.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.23:29:34.13:setupk4=1 2006.285.23:29:34.13$setupk4/echo=on 2006.285.23:29:34.13$setupk4/pcalon 2006.285.23:29:34.13$pcalon/"no phase cal control is implemented here 2006.285.23:29:34.13$setupk4/"tpicd=stop 2006.285.23:29:34.13$setupk4/"rec=synch_on 2006.285.23:29:34.13$setupk4/"rec_mode=128 2006.285.23:29:34.13$setupk4/!* 2006.285.23:29:34.13$setupk4/recpk4 2006.285.23:29:34.13$recpk4/recpatch= 2006.285.23:29:34.13$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.23:29:34.13$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.23:29:34.13$setupk4/vck44 2006.285.23:29:34.14$vck44/valo=1,524.99 2006.285.23:29:34.14#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.23:29:34.14#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.23:29:34.14#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:34.14#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:29:34.14#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:29:34.14#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:29:34.14#ibcon#enter wrdev, iclass 20, count 0 2006.285.23:29:34.14#ibcon#first serial, iclass 20, count 0 2006.285.23:29:34.14#ibcon#enter sib2, iclass 20, count 0 2006.285.23:29:34.14#ibcon#flushed, iclass 20, count 0 2006.285.23:29:34.14#ibcon#about to write, iclass 20, count 0 2006.285.23:29:34.14#ibcon#wrote, iclass 20, count 0 2006.285.23:29:34.14#ibcon#about to read 3, iclass 20, count 0 2006.285.23:29:34.15#ibcon#read 3, iclass 20, count 0 2006.285.23:29:34.15#ibcon#about to read 4, iclass 20, count 0 2006.285.23:29:34.15#ibcon#read 4, iclass 20, count 0 2006.285.23:29:34.15#ibcon#about to read 5, iclass 20, count 0 2006.285.23:29:34.15#ibcon#read 5, iclass 20, count 0 2006.285.23:29:34.15#ibcon#about to read 6, iclass 20, count 0 2006.285.23:29:34.15#ibcon#read 6, iclass 20, count 0 2006.285.23:29:34.15#ibcon#end of sib2, iclass 20, count 0 2006.285.23:29:34.15#ibcon#*mode == 0, iclass 20, count 0 2006.285.23:29:34.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.23:29:34.15#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.23:29:34.15#ibcon#*before write, iclass 20, count 0 2006.285.23:29:34.15#ibcon#enter sib2, iclass 20, count 0 2006.285.23:29:34.15#ibcon#flushed, iclass 20, count 0 2006.285.23:29:34.15#ibcon#about to write, iclass 20, count 0 2006.285.23:29:34.15#ibcon#wrote, iclass 20, count 0 2006.285.23:29:34.15#ibcon#about to read 3, iclass 20, count 0 2006.285.23:29:34.20#ibcon#read 3, iclass 20, count 0 2006.285.23:29:34.20#ibcon#about to read 4, iclass 20, count 0 2006.285.23:29:34.20#ibcon#read 4, iclass 20, count 0 2006.285.23:29:34.20#ibcon#about to read 5, iclass 20, count 0 2006.285.23:29:34.20#ibcon#read 5, iclass 20, count 0 2006.285.23:29:34.20#ibcon#about to read 6, iclass 20, count 0 2006.285.23:29:34.20#ibcon#read 6, iclass 20, count 0 2006.285.23:29:34.20#ibcon#end of sib2, iclass 20, count 0 2006.285.23:29:34.20#ibcon#*after write, iclass 20, count 0 2006.285.23:29:34.20#ibcon#*before return 0, iclass 20, count 0 2006.285.23:29:34.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:29:34.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:29:34.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.23:29:34.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.23:29:34.20$vck44/va=1,7 2006.285.23:29:34.20#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.23:29:34.20#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.23:29:34.20#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:34.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:29:34.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:29:34.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:29:34.20#ibcon#enter wrdev, iclass 22, count 2 2006.285.23:29:34.20#ibcon#first serial, iclass 22, count 2 2006.285.23:29:34.20#ibcon#enter sib2, iclass 22, count 2 2006.285.23:29:34.20#ibcon#flushed, iclass 22, count 2 2006.285.23:29:34.20#ibcon#about to write, iclass 22, count 2 2006.285.23:29:34.20#ibcon#wrote, iclass 22, count 2 2006.285.23:29:34.20#ibcon#about to read 3, iclass 22, count 2 2006.285.23:29:34.22#ibcon#read 3, iclass 22, count 2 2006.285.23:29:34.22#ibcon#about to read 4, iclass 22, count 2 2006.285.23:29:34.22#ibcon#read 4, iclass 22, count 2 2006.285.23:29:34.22#ibcon#about to read 5, iclass 22, count 2 2006.285.23:29:34.22#ibcon#read 5, iclass 22, count 2 2006.285.23:29:34.22#ibcon#about to read 6, iclass 22, count 2 2006.285.23:29:34.22#ibcon#read 6, iclass 22, count 2 2006.285.23:29:34.22#ibcon#end of sib2, iclass 22, count 2 2006.285.23:29:34.22#ibcon#*mode == 0, iclass 22, count 2 2006.285.23:29:34.22#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.23:29:34.22#ibcon#[25=AT01-07\r\n] 2006.285.23:29:34.22#ibcon#*before write, iclass 22, count 2 2006.285.23:29:34.22#ibcon#enter sib2, iclass 22, count 2 2006.285.23:29:34.22#ibcon#flushed, iclass 22, count 2 2006.285.23:29:34.22#ibcon#about to write, iclass 22, count 2 2006.285.23:29:34.22#ibcon#wrote, iclass 22, count 2 2006.285.23:29:34.22#ibcon#about to read 3, iclass 22, count 2 2006.285.23:29:34.25#ibcon#read 3, iclass 22, count 2 2006.285.23:29:34.25#ibcon#about to read 4, iclass 22, count 2 2006.285.23:29:34.25#ibcon#read 4, iclass 22, count 2 2006.285.23:29:34.25#ibcon#about to read 5, iclass 22, count 2 2006.285.23:29:34.25#ibcon#read 5, iclass 22, count 2 2006.285.23:29:34.25#ibcon#about to read 6, iclass 22, count 2 2006.285.23:29:34.25#ibcon#read 6, iclass 22, count 2 2006.285.23:29:34.25#ibcon#end of sib2, iclass 22, count 2 2006.285.23:29:34.25#ibcon#*after write, iclass 22, count 2 2006.285.23:29:34.25#ibcon#*before return 0, iclass 22, count 2 2006.285.23:29:34.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:29:34.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:29:34.25#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.23:29:34.25#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:34.25#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:29:34.37#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:29:34.37#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:29:34.37#ibcon#enter wrdev, iclass 22, count 0 2006.285.23:29:34.37#ibcon#first serial, iclass 22, count 0 2006.285.23:29:34.37#ibcon#enter sib2, iclass 22, count 0 2006.285.23:29:34.37#ibcon#flushed, iclass 22, count 0 2006.285.23:29:34.37#ibcon#about to write, iclass 22, count 0 2006.285.23:29:34.37#ibcon#wrote, iclass 22, count 0 2006.285.23:29:34.37#ibcon#about to read 3, iclass 22, count 0 2006.285.23:29:34.39#ibcon#read 3, iclass 22, count 0 2006.285.23:29:34.39#ibcon#about to read 4, iclass 22, count 0 2006.285.23:29:34.39#ibcon#read 4, iclass 22, count 0 2006.285.23:29:34.39#ibcon#about to read 5, iclass 22, count 0 2006.285.23:29:34.39#ibcon#read 5, iclass 22, count 0 2006.285.23:29:34.39#ibcon#about to read 6, iclass 22, count 0 2006.285.23:29:34.39#ibcon#read 6, iclass 22, count 0 2006.285.23:29:34.39#ibcon#end of sib2, iclass 22, count 0 2006.285.23:29:34.39#ibcon#*mode == 0, iclass 22, count 0 2006.285.23:29:34.39#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.23:29:34.39#ibcon#[25=USB\r\n] 2006.285.23:29:34.39#ibcon#*before write, iclass 22, count 0 2006.285.23:29:34.39#ibcon#enter sib2, iclass 22, count 0 2006.285.23:29:34.39#ibcon#flushed, iclass 22, count 0 2006.285.23:29:34.39#ibcon#about to write, iclass 22, count 0 2006.285.23:29:34.39#ibcon#wrote, iclass 22, count 0 2006.285.23:29:34.39#ibcon#about to read 3, iclass 22, count 0 2006.285.23:29:34.42#ibcon#read 3, iclass 22, count 0 2006.285.23:29:34.42#ibcon#about to read 4, iclass 22, count 0 2006.285.23:29:34.42#ibcon#read 4, iclass 22, count 0 2006.285.23:29:34.42#ibcon#about to read 5, iclass 22, count 0 2006.285.23:29:34.42#ibcon#read 5, iclass 22, count 0 2006.285.23:29:34.42#ibcon#about to read 6, iclass 22, count 0 2006.285.23:29:34.42#ibcon#read 6, iclass 22, count 0 2006.285.23:29:34.42#ibcon#end of sib2, iclass 22, count 0 2006.285.23:29:34.42#ibcon#*after write, iclass 22, count 0 2006.285.23:29:34.42#ibcon#*before return 0, iclass 22, count 0 2006.285.23:29:34.42#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:29:34.42#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:29:34.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.23:29:34.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.23:29:34.42$vck44/valo=2,534.99 2006.285.23:29:34.42#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.23:29:34.42#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.23:29:34.42#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:34.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:29:34.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:29:34.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:29:34.42#ibcon#enter wrdev, iclass 24, count 0 2006.285.23:29:34.42#ibcon#first serial, iclass 24, count 0 2006.285.23:29:34.42#ibcon#enter sib2, iclass 24, count 0 2006.285.23:29:34.42#ibcon#flushed, iclass 24, count 0 2006.285.23:29:34.42#ibcon#about to write, iclass 24, count 0 2006.285.23:29:34.42#ibcon#wrote, iclass 24, count 0 2006.285.23:29:34.42#ibcon#about to read 3, iclass 24, count 0 2006.285.23:29:34.44#ibcon#read 3, iclass 24, count 0 2006.285.23:29:34.44#ibcon#about to read 4, iclass 24, count 0 2006.285.23:29:34.44#ibcon#read 4, iclass 24, count 0 2006.285.23:29:34.44#ibcon#about to read 5, iclass 24, count 0 2006.285.23:29:34.44#ibcon#read 5, iclass 24, count 0 2006.285.23:29:34.44#ibcon#about to read 6, iclass 24, count 0 2006.285.23:29:34.44#ibcon#read 6, iclass 24, count 0 2006.285.23:29:34.44#ibcon#end of sib2, iclass 24, count 0 2006.285.23:29:34.44#ibcon#*mode == 0, iclass 24, count 0 2006.285.23:29:34.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.23:29:34.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.23:29:34.44#ibcon#*before write, iclass 24, count 0 2006.285.23:29:34.44#ibcon#enter sib2, iclass 24, count 0 2006.285.23:29:34.44#ibcon#flushed, iclass 24, count 0 2006.285.23:29:34.44#ibcon#about to write, iclass 24, count 0 2006.285.23:29:34.44#ibcon#wrote, iclass 24, count 0 2006.285.23:29:34.44#ibcon#about to read 3, iclass 24, count 0 2006.285.23:29:34.48#ibcon#read 3, iclass 24, count 0 2006.285.23:29:34.48#ibcon#about to read 4, iclass 24, count 0 2006.285.23:29:34.48#ibcon#read 4, iclass 24, count 0 2006.285.23:29:34.48#ibcon#about to read 5, iclass 24, count 0 2006.285.23:29:34.48#ibcon#read 5, iclass 24, count 0 2006.285.23:29:34.48#ibcon#about to read 6, iclass 24, count 0 2006.285.23:29:34.48#ibcon#read 6, iclass 24, count 0 2006.285.23:29:34.48#ibcon#end of sib2, iclass 24, count 0 2006.285.23:29:34.48#ibcon#*after write, iclass 24, count 0 2006.285.23:29:34.48#ibcon#*before return 0, iclass 24, count 0 2006.285.23:29:34.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:29:34.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:29:34.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.23:29:34.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.23:29:34.48$vck44/va=2,6 2006.285.23:29:34.48#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.23:29:34.48#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.23:29:34.48#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:34.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:29:34.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:29:34.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:29:34.54#ibcon#enter wrdev, iclass 26, count 2 2006.285.23:29:34.54#ibcon#first serial, iclass 26, count 2 2006.285.23:29:34.54#ibcon#enter sib2, iclass 26, count 2 2006.285.23:29:34.54#ibcon#flushed, iclass 26, count 2 2006.285.23:29:34.54#ibcon#about to write, iclass 26, count 2 2006.285.23:29:34.54#ibcon#wrote, iclass 26, count 2 2006.285.23:29:34.54#ibcon#about to read 3, iclass 26, count 2 2006.285.23:29:34.56#ibcon#read 3, iclass 26, count 2 2006.285.23:29:34.56#ibcon#about to read 4, iclass 26, count 2 2006.285.23:29:34.56#ibcon#read 4, iclass 26, count 2 2006.285.23:29:34.56#ibcon#about to read 5, iclass 26, count 2 2006.285.23:29:34.56#ibcon#read 5, iclass 26, count 2 2006.285.23:29:34.56#ibcon#about to read 6, iclass 26, count 2 2006.285.23:29:34.56#ibcon#read 6, iclass 26, count 2 2006.285.23:29:34.56#ibcon#end of sib2, iclass 26, count 2 2006.285.23:29:34.56#ibcon#*mode == 0, iclass 26, count 2 2006.285.23:29:34.56#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.23:29:34.56#ibcon#[25=AT02-06\r\n] 2006.285.23:29:34.56#ibcon#*before write, iclass 26, count 2 2006.285.23:29:34.56#ibcon#enter sib2, iclass 26, count 2 2006.285.23:29:34.56#ibcon#flushed, iclass 26, count 2 2006.285.23:29:34.56#ibcon#about to write, iclass 26, count 2 2006.285.23:29:34.56#ibcon#wrote, iclass 26, count 2 2006.285.23:29:34.56#ibcon#about to read 3, iclass 26, count 2 2006.285.23:29:34.59#ibcon#read 3, iclass 26, count 2 2006.285.23:29:34.59#ibcon#about to read 4, iclass 26, count 2 2006.285.23:29:34.59#ibcon#read 4, iclass 26, count 2 2006.285.23:29:34.59#ibcon#about to read 5, iclass 26, count 2 2006.285.23:29:34.59#ibcon#read 5, iclass 26, count 2 2006.285.23:29:34.59#ibcon#about to read 6, iclass 26, count 2 2006.285.23:29:34.59#ibcon#read 6, iclass 26, count 2 2006.285.23:29:34.59#ibcon#end of sib2, iclass 26, count 2 2006.285.23:29:34.59#ibcon#*after write, iclass 26, count 2 2006.285.23:29:34.59#ibcon#*before return 0, iclass 26, count 2 2006.285.23:29:34.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:29:34.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:29:34.59#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.23:29:34.59#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:34.59#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:29:34.71#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:29:34.71#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:29:34.71#ibcon#enter wrdev, iclass 26, count 0 2006.285.23:29:34.71#ibcon#first serial, iclass 26, count 0 2006.285.23:29:34.71#ibcon#enter sib2, iclass 26, count 0 2006.285.23:29:34.71#ibcon#flushed, iclass 26, count 0 2006.285.23:29:34.71#ibcon#about to write, iclass 26, count 0 2006.285.23:29:34.71#ibcon#wrote, iclass 26, count 0 2006.285.23:29:34.71#ibcon#about to read 3, iclass 26, count 0 2006.285.23:29:34.73#ibcon#read 3, iclass 26, count 0 2006.285.23:29:34.73#ibcon#about to read 4, iclass 26, count 0 2006.285.23:29:34.73#ibcon#read 4, iclass 26, count 0 2006.285.23:29:34.73#ibcon#about to read 5, iclass 26, count 0 2006.285.23:29:34.73#ibcon#read 5, iclass 26, count 0 2006.285.23:29:34.73#ibcon#about to read 6, iclass 26, count 0 2006.285.23:29:34.73#ibcon#read 6, iclass 26, count 0 2006.285.23:29:34.73#ibcon#end of sib2, iclass 26, count 0 2006.285.23:29:34.73#ibcon#*mode == 0, iclass 26, count 0 2006.285.23:29:34.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.23:29:34.73#ibcon#[25=USB\r\n] 2006.285.23:29:34.73#ibcon#*before write, iclass 26, count 0 2006.285.23:29:34.73#ibcon#enter sib2, iclass 26, count 0 2006.285.23:29:34.73#ibcon#flushed, iclass 26, count 0 2006.285.23:29:34.73#ibcon#about to write, iclass 26, count 0 2006.285.23:29:34.73#ibcon#wrote, iclass 26, count 0 2006.285.23:29:34.73#ibcon#about to read 3, iclass 26, count 0 2006.285.23:29:34.76#ibcon#read 3, iclass 26, count 0 2006.285.23:29:34.76#ibcon#about to read 4, iclass 26, count 0 2006.285.23:29:34.76#ibcon#read 4, iclass 26, count 0 2006.285.23:29:34.76#ibcon#about to read 5, iclass 26, count 0 2006.285.23:29:34.76#ibcon#read 5, iclass 26, count 0 2006.285.23:29:34.76#ibcon#about to read 6, iclass 26, count 0 2006.285.23:29:34.76#ibcon#read 6, iclass 26, count 0 2006.285.23:29:34.76#ibcon#end of sib2, iclass 26, count 0 2006.285.23:29:34.76#ibcon#*after write, iclass 26, count 0 2006.285.23:29:34.76#ibcon#*before return 0, iclass 26, count 0 2006.285.23:29:34.76#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:29:34.76#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:29:34.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.23:29:34.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.23:29:34.76$vck44/valo=3,564.99 2006.285.23:29:34.76#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.23:29:34.76#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.23:29:34.76#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:34.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:29:34.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:29:34.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:29:34.76#ibcon#enter wrdev, iclass 28, count 0 2006.285.23:29:34.76#ibcon#first serial, iclass 28, count 0 2006.285.23:29:34.76#ibcon#enter sib2, iclass 28, count 0 2006.285.23:29:34.76#ibcon#flushed, iclass 28, count 0 2006.285.23:29:34.76#ibcon#about to write, iclass 28, count 0 2006.285.23:29:34.76#ibcon#wrote, iclass 28, count 0 2006.285.23:29:34.76#ibcon#about to read 3, iclass 28, count 0 2006.285.23:29:34.78#ibcon#read 3, iclass 28, count 0 2006.285.23:29:34.78#ibcon#about to read 4, iclass 28, count 0 2006.285.23:29:34.78#ibcon#read 4, iclass 28, count 0 2006.285.23:29:34.78#ibcon#about to read 5, iclass 28, count 0 2006.285.23:29:34.78#ibcon#read 5, iclass 28, count 0 2006.285.23:29:34.78#ibcon#about to read 6, iclass 28, count 0 2006.285.23:29:34.78#ibcon#read 6, iclass 28, count 0 2006.285.23:29:34.78#ibcon#end of sib2, iclass 28, count 0 2006.285.23:29:34.78#ibcon#*mode == 0, iclass 28, count 0 2006.285.23:29:34.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.23:29:34.78#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.23:29:34.78#ibcon#*before write, iclass 28, count 0 2006.285.23:29:34.78#ibcon#enter sib2, iclass 28, count 0 2006.285.23:29:34.78#ibcon#flushed, iclass 28, count 0 2006.285.23:29:34.78#ibcon#about to write, iclass 28, count 0 2006.285.23:29:34.78#ibcon#wrote, iclass 28, count 0 2006.285.23:29:34.78#ibcon#about to read 3, iclass 28, count 0 2006.285.23:29:34.82#ibcon#read 3, iclass 28, count 0 2006.285.23:29:34.82#ibcon#about to read 4, iclass 28, count 0 2006.285.23:29:34.82#ibcon#read 4, iclass 28, count 0 2006.285.23:29:34.82#ibcon#about to read 5, iclass 28, count 0 2006.285.23:29:34.82#ibcon#read 5, iclass 28, count 0 2006.285.23:29:34.82#ibcon#about to read 6, iclass 28, count 0 2006.285.23:29:34.82#ibcon#read 6, iclass 28, count 0 2006.285.23:29:34.82#ibcon#end of sib2, iclass 28, count 0 2006.285.23:29:34.82#ibcon#*after write, iclass 28, count 0 2006.285.23:29:34.82#ibcon#*before return 0, iclass 28, count 0 2006.285.23:29:34.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:29:34.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:29:34.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.23:29:34.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.23:29:34.82$vck44/va=3,7 2006.285.23:29:34.82#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.23:29:34.82#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.23:29:34.82#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:34.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:29:34.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:29:34.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:29:34.88#ibcon#enter wrdev, iclass 30, count 2 2006.285.23:29:34.88#ibcon#first serial, iclass 30, count 2 2006.285.23:29:34.88#ibcon#enter sib2, iclass 30, count 2 2006.285.23:29:34.88#ibcon#flushed, iclass 30, count 2 2006.285.23:29:34.88#ibcon#about to write, iclass 30, count 2 2006.285.23:29:34.88#ibcon#wrote, iclass 30, count 2 2006.285.23:29:34.88#ibcon#about to read 3, iclass 30, count 2 2006.285.23:29:34.90#ibcon#read 3, iclass 30, count 2 2006.285.23:29:34.90#ibcon#about to read 4, iclass 30, count 2 2006.285.23:29:34.90#ibcon#read 4, iclass 30, count 2 2006.285.23:29:34.90#ibcon#about to read 5, iclass 30, count 2 2006.285.23:29:34.90#ibcon#read 5, iclass 30, count 2 2006.285.23:29:34.90#ibcon#about to read 6, iclass 30, count 2 2006.285.23:29:34.90#ibcon#read 6, iclass 30, count 2 2006.285.23:29:34.90#ibcon#end of sib2, iclass 30, count 2 2006.285.23:29:34.90#ibcon#*mode == 0, iclass 30, count 2 2006.285.23:29:34.90#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.23:29:34.90#ibcon#[25=AT03-07\r\n] 2006.285.23:29:34.90#ibcon#*before write, iclass 30, count 2 2006.285.23:29:34.90#ibcon#enter sib2, iclass 30, count 2 2006.285.23:29:34.90#ibcon#flushed, iclass 30, count 2 2006.285.23:29:34.90#ibcon#about to write, iclass 30, count 2 2006.285.23:29:34.90#ibcon#wrote, iclass 30, count 2 2006.285.23:29:34.90#ibcon#about to read 3, iclass 30, count 2 2006.285.23:29:34.93#ibcon#read 3, iclass 30, count 2 2006.285.23:29:34.93#ibcon#about to read 4, iclass 30, count 2 2006.285.23:29:34.93#ibcon#read 4, iclass 30, count 2 2006.285.23:29:34.93#ibcon#about to read 5, iclass 30, count 2 2006.285.23:29:34.93#ibcon#read 5, iclass 30, count 2 2006.285.23:29:34.93#ibcon#about to read 6, iclass 30, count 2 2006.285.23:29:34.93#ibcon#read 6, iclass 30, count 2 2006.285.23:29:34.93#ibcon#end of sib2, iclass 30, count 2 2006.285.23:29:34.93#ibcon#*after write, iclass 30, count 2 2006.285.23:29:34.93#ibcon#*before return 0, iclass 30, count 2 2006.285.23:29:34.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:29:34.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:29:34.93#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.23:29:34.93#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:34.93#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:29:35.05#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:29:35.05#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:29:35.05#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:29:35.05#ibcon#first serial, iclass 30, count 0 2006.285.23:29:35.05#ibcon#enter sib2, iclass 30, count 0 2006.285.23:29:35.05#ibcon#flushed, iclass 30, count 0 2006.285.23:29:35.05#ibcon#about to write, iclass 30, count 0 2006.285.23:29:35.05#ibcon#wrote, iclass 30, count 0 2006.285.23:29:35.05#ibcon#about to read 3, iclass 30, count 0 2006.285.23:29:35.07#ibcon#read 3, iclass 30, count 0 2006.285.23:29:35.07#ibcon#about to read 4, iclass 30, count 0 2006.285.23:29:35.07#ibcon#read 4, iclass 30, count 0 2006.285.23:29:35.07#ibcon#about to read 5, iclass 30, count 0 2006.285.23:29:35.07#ibcon#read 5, iclass 30, count 0 2006.285.23:29:35.07#ibcon#about to read 6, iclass 30, count 0 2006.285.23:29:35.07#ibcon#read 6, iclass 30, count 0 2006.285.23:29:35.07#ibcon#end of sib2, iclass 30, count 0 2006.285.23:29:35.07#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:29:35.07#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:29:35.07#ibcon#[25=USB\r\n] 2006.285.23:29:35.07#ibcon#*before write, iclass 30, count 0 2006.285.23:29:35.07#ibcon#enter sib2, iclass 30, count 0 2006.285.23:29:35.07#ibcon#flushed, iclass 30, count 0 2006.285.23:29:35.07#ibcon#about to write, iclass 30, count 0 2006.285.23:29:35.07#ibcon#wrote, iclass 30, count 0 2006.285.23:29:35.07#ibcon#about to read 3, iclass 30, count 0 2006.285.23:29:35.10#ibcon#read 3, iclass 30, count 0 2006.285.23:29:35.10#ibcon#about to read 4, iclass 30, count 0 2006.285.23:29:35.10#ibcon#read 4, iclass 30, count 0 2006.285.23:29:35.10#ibcon#about to read 5, iclass 30, count 0 2006.285.23:29:35.10#ibcon#read 5, iclass 30, count 0 2006.285.23:29:35.10#ibcon#about to read 6, iclass 30, count 0 2006.285.23:29:35.10#ibcon#read 6, iclass 30, count 0 2006.285.23:29:35.10#ibcon#end of sib2, iclass 30, count 0 2006.285.23:29:35.10#ibcon#*after write, iclass 30, count 0 2006.285.23:29:35.10#ibcon#*before return 0, iclass 30, count 0 2006.285.23:29:35.10#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:29:35.10#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:29:35.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:29:35.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:29:35.10$vck44/valo=4,624.99 2006.285.23:29:35.10#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.23:29:35.10#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.23:29:35.10#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:35.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:29:35.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:29:35.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:29:35.10#ibcon#enter wrdev, iclass 32, count 0 2006.285.23:29:35.10#ibcon#first serial, iclass 32, count 0 2006.285.23:29:35.10#ibcon#enter sib2, iclass 32, count 0 2006.285.23:29:35.10#ibcon#flushed, iclass 32, count 0 2006.285.23:29:35.10#ibcon#about to write, iclass 32, count 0 2006.285.23:29:35.10#ibcon#wrote, iclass 32, count 0 2006.285.23:29:35.10#ibcon#about to read 3, iclass 32, count 0 2006.285.23:29:35.12#ibcon#read 3, iclass 32, count 0 2006.285.23:29:35.12#ibcon#about to read 4, iclass 32, count 0 2006.285.23:29:35.12#ibcon#read 4, iclass 32, count 0 2006.285.23:29:35.12#ibcon#about to read 5, iclass 32, count 0 2006.285.23:29:35.12#ibcon#read 5, iclass 32, count 0 2006.285.23:29:35.12#ibcon#about to read 6, iclass 32, count 0 2006.285.23:29:35.12#ibcon#read 6, iclass 32, count 0 2006.285.23:29:35.12#ibcon#end of sib2, iclass 32, count 0 2006.285.23:29:35.12#ibcon#*mode == 0, iclass 32, count 0 2006.285.23:29:35.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.23:29:35.12#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.23:29:35.12#ibcon#*before write, iclass 32, count 0 2006.285.23:29:35.12#ibcon#enter sib2, iclass 32, count 0 2006.285.23:29:35.12#ibcon#flushed, iclass 32, count 0 2006.285.23:29:35.12#ibcon#about to write, iclass 32, count 0 2006.285.23:29:35.12#ibcon#wrote, iclass 32, count 0 2006.285.23:29:35.12#ibcon#about to read 3, iclass 32, count 0 2006.285.23:29:35.16#ibcon#read 3, iclass 32, count 0 2006.285.23:29:35.16#ibcon#about to read 4, iclass 32, count 0 2006.285.23:29:35.16#ibcon#read 4, iclass 32, count 0 2006.285.23:29:35.16#ibcon#about to read 5, iclass 32, count 0 2006.285.23:29:35.16#ibcon#read 5, iclass 32, count 0 2006.285.23:29:35.16#ibcon#about to read 6, iclass 32, count 0 2006.285.23:29:35.16#ibcon#read 6, iclass 32, count 0 2006.285.23:29:35.16#ibcon#end of sib2, iclass 32, count 0 2006.285.23:29:35.16#ibcon#*after write, iclass 32, count 0 2006.285.23:29:35.16#ibcon#*before return 0, iclass 32, count 0 2006.285.23:29:35.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:29:35.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:29:35.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.23:29:35.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.23:29:35.16$vck44/va=4,6 2006.285.23:29:35.16#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.23:29:35.16#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.23:29:35.16#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:35.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:29:35.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:29:35.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:29:35.22#ibcon#enter wrdev, iclass 34, count 2 2006.285.23:29:35.22#ibcon#first serial, iclass 34, count 2 2006.285.23:29:35.22#ibcon#enter sib2, iclass 34, count 2 2006.285.23:29:35.22#ibcon#flushed, iclass 34, count 2 2006.285.23:29:35.22#ibcon#about to write, iclass 34, count 2 2006.285.23:29:35.22#ibcon#wrote, iclass 34, count 2 2006.285.23:29:35.22#ibcon#about to read 3, iclass 34, count 2 2006.285.23:29:35.24#ibcon#read 3, iclass 34, count 2 2006.285.23:29:35.24#ibcon#about to read 4, iclass 34, count 2 2006.285.23:29:35.24#ibcon#read 4, iclass 34, count 2 2006.285.23:29:35.24#ibcon#about to read 5, iclass 34, count 2 2006.285.23:29:35.24#ibcon#read 5, iclass 34, count 2 2006.285.23:29:35.24#ibcon#about to read 6, iclass 34, count 2 2006.285.23:29:35.24#ibcon#read 6, iclass 34, count 2 2006.285.23:29:35.24#ibcon#end of sib2, iclass 34, count 2 2006.285.23:29:35.24#ibcon#*mode == 0, iclass 34, count 2 2006.285.23:29:35.24#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.23:29:35.24#ibcon#[25=AT04-06\r\n] 2006.285.23:29:35.24#ibcon#*before write, iclass 34, count 2 2006.285.23:29:35.24#ibcon#enter sib2, iclass 34, count 2 2006.285.23:29:35.24#ibcon#flushed, iclass 34, count 2 2006.285.23:29:35.24#ibcon#about to write, iclass 34, count 2 2006.285.23:29:35.24#ibcon#wrote, iclass 34, count 2 2006.285.23:29:35.24#ibcon#about to read 3, iclass 34, count 2 2006.285.23:29:35.27#ibcon#read 3, iclass 34, count 2 2006.285.23:29:35.27#ibcon#about to read 4, iclass 34, count 2 2006.285.23:29:35.27#ibcon#read 4, iclass 34, count 2 2006.285.23:29:35.27#ibcon#about to read 5, iclass 34, count 2 2006.285.23:29:35.27#ibcon#read 5, iclass 34, count 2 2006.285.23:29:35.27#ibcon#about to read 6, iclass 34, count 2 2006.285.23:29:35.27#ibcon#read 6, iclass 34, count 2 2006.285.23:29:35.27#ibcon#end of sib2, iclass 34, count 2 2006.285.23:29:35.27#ibcon#*after write, iclass 34, count 2 2006.285.23:29:35.27#ibcon#*before return 0, iclass 34, count 2 2006.285.23:29:35.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:29:35.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:29:35.27#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.23:29:35.27#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:35.27#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:29:35.39#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:29:35.39#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:29:35.39#ibcon#enter wrdev, iclass 34, count 0 2006.285.23:29:35.39#ibcon#first serial, iclass 34, count 0 2006.285.23:29:35.39#ibcon#enter sib2, iclass 34, count 0 2006.285.23:29:35.39#ibcon#flushed, iclass 34, count 0 2006.285.23:29:35.39#ibcon#about to write, iclass 34, count 0 2006.285.23:29:35.39#ibcon#wrote, iclass 34, count 0 2006.285.23:29:35.39#ibcon#about to read 3, iclass 34, count 0 2006.285.23:29:35.41#ibcon#read 3, iclass 34, count 0 2006.285.23:29:35.41#ibcon#about to read 4, iclass 34, count 0 2006.285.23:29:35.41#ibcon#read 4, iclass 34, count 0 2006.285.23:29:35.41#ibcon#about to read 5, iclass 34, count 0 2006.285.23:29:35.41#ibcon#read 5, iclass 34, count 0 2006.285.23:29:35.41#ibcon#about to read 6, iclass 34, count 0 2006.285.23:29:35.41#ibcon#read 6, iclass 34, count 0 2006.285.23:29:35.41#ibcon#end of sib2, iclass 34, count 0 2006.285.23:29:35.41#ibcon#*mode == 0, iclass 34, count 0 2006.285.23:29:35.41#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.23:29:35.41#ibcon#[25=USB\r\n] 2006.285.23:29:35.41#ibcon#*before write, iclass 34, count 0 2006.285.23:29:35.41#ibcon#enter sib2, iclass 34, count 0 2006.285.23:29:35.41#ibcon#flushed, iclass 34, count 0 2006.285.23:29:35.41#ibcon#about to write, iclass 34, count 0 2006.285.23:29:35.41#ibcon#wrote, iclass 34, count 0 2006.285.23:29:35.41#ibcon#about to read 3, iclass 34, count 0 2006.285.23:29:35.44#ibcon#read 3, iclass 34, count 0 2006.285.23:29:35.44#ibcon#about to read 4, iclass 34, count 0 2006.285.23:29:35.44#ibcon#read 4, iclass 34, count 0 2006.285.23:29:35.44#ibcon#about to read 5, iclass 34, count 0 2006.285.23:29:35.44#ibcon#read 5, iclass 34, count 0 2006.285.23:29:35.44#ibcon#about to read 6, iclass 34, count 0 2006.285.23:29:35.44#ibcon#read 6, iclass 34, count 0 2006.285.23:29:35.44#ibcon#end of sib2, iclass 34, count 0 2006.285.23:29:35.44#ibcon#*after write, iclass 34, count 0 2006.285.23:29:35.44#ibcon#*before return 0, iclass 34, count 0 2006.285.23:29:35.44#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:29:35.44#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:29:35.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.23:29:35.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.23:29:35.44$vck44/valo=5,734.99 2006.285.23:29:35.44#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.23:29:35.44#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.23:29:35.44#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:35.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:29:35.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:29:35.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:29:35.44#ibcon#enter wrdev, iclass 36, count 0 2006.285.23:29:35.44#ibcon#first serial, iclass 36, count 0 2006.285.23:29:35.44#ibcon#enter sib2, iclass 36, count 0 2006.285.23:29:35.44#ibcon#flushed, iclass 36, count 0 2006.285.23:29:35.44#ibcon#about to write, iclass 36, count 0 2006.285.23:29:35.44#ibcon#wrote, iclass 36, count 0 2006.285.23:29:35.44#ibcon#about to read 3, iclass 36, count 0 2006.285.23:29:35.46#ibcon#read 3, iclass 36, count 0 2006.285.23:29:35.46#ibcon#about to read 4, iclass 36, count 0 2006.285.23:29:35.46#ibcon#read 4, iclass 36, count 0 2006.285.23:29:35.46#ibcon#about to read 5, iclass 36, count 0 2006.285.23:29:35.46#ibcon#read 5, iclass 36, count 0 2006.285.23:29:35.46#ibcon#about to read 6, iclass 36, count 0 2006.285.23:29:35.46#ibcon#read 6, iclass 36, count 0 2006.285.23:29:35.46#ibcon#end of sib2, iclass 36, count 0 2006.285.23:29:35.46#ibcon#*mode == 0, iclass 36, count 0 2006.285.23:29:35.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.23:29:35.46#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.23:29:35.46#ibcon#*before write, iclass 36, count 0 2006.285.23:29:35.46#ibcon#enter sib2, iclass 36, count 0 2006.285.23:29:35.46#ibcon#flushed, iclass 36, count 0 2006.285.23:29:35.46#ibcon#about to write, iclass 36, count 0 2006.285.23:29:35.46#ibcon#wrote, iclass 36, count 0 2006.285.23:29:35.46#ibcon#about to read 3, iclass 36, count 0 2006.285.23:29:35.50#ibcon#read 3, iclass 36, count 0 2006.285.23:29:35.50#ibcon#about to read 4, iclass 36, count 0 2006.285.23:29:35.50#ibcon#read 4, iclass 36, count 0 2006.285.23:29:35.50#ibcon#about to read 5, iclass 36, count 0 2006.285.23:29:35.50#ibcon#read 5, iclass 36, count 0 2006.285.23:29:35.50#ibcon#about to read 6, iclass 36, count 0 2006.285.23:29:35.50#ibcon#read 6, iclass 36, count 0 2006.285.23:29:35.50#ibcon#end of sib2, iclass 36, count 0 2006.285.23:29:35.50#ibcon#*after write, iclass 36, count 0 2006.285.23:29:35.50#ibcon#*before return 0, iclass 36, count 0 2006.285.23:29:35.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:29:35.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:29:35.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.23:29:35.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.23:29:35.50$vck44/va=5,3 2006.285.23:29:35.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.23:29:35.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.23:29:35.50#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:35.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:29:35.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:29:35.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:29:35.56#ibcon#enter wrdev, iclass 38, count 2 2006.285.23:29:35.56#ibcon#first serial, iclass 38, count 2 2006.285.23:29:35.56#ibcon#enter sib2, iclass 38, count 2 2006.285.23:29:35.56#ibcon#flushed, iclass 38, count 2 2006.285.23:29:35.56#ibcon#about to write, iclass 38, count 2 2006.285.23:29:35.56#ibcon#wrote, iclass 38, count 2 2006.285.23:29:35.56#ibcon#about to read 3, iclass 38, count 2 2006.285.23:29:35.58#ibcon#read 3, iclass 38, count 2 2006.285.23:29:35.58#ibcon#about to read 4, iclass 38, count 2 2006.285.23:29:35.58#ibcon#read 4, iclass 38, count 2 2006.285.23:29:35.58#ibcon#about to read 5, iclass 38, count 2 2006.285.23:29:35.58#ibcon#read 5, iclass 38, count 2 2006.285.23:29:35.58#ibcon#about to read 6, iclass 38, count 2 2006.285.23:29:35.58#ibcon#read 6, iclass 38, count 2 2006.285.23:29:35.58#ibcon#end of sib2, iclass 38, count 2 2006.285.23:29:35.58#ibcon#*mode == 0, iclass 38, count 2 2006.285.23:29:35.58#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.23:29:35.58#ibcon#[25=AT05-03\r\n] 2006.285.23:29:35.58#ibcon#*before write, iclass 38, count 2 2006.285.23:29:35.58#ibcon#enter sib2, iclass 38, count 2 2006.285.23:29:35.58#ibcon#flushed, iclass 38, count 2 2006.285.23:29:35.58#ibcon#about to write, iclass 38, count 2 2006.285.23:29:35.58#ibcon#wrote, iclass 38, count 2 2006.285.23:29:35.58#ibcon#about to read 3, iclass 38, count 2 2006.285.23:29:35.61#ibcon#read 3, iclass 38, count 2 2006.285.23:29:35.61#ibcon#about to read 4, iclass 38, count 2 2006.285.23:29:35.61#ibcon#read 4, iclass 38, count 2 2006.285.23:29:35.61#ibcon#about to read 5, iclass 38, count 2 2006.285.23:29:35.61#ibcon#read 5, iclass 38, count 2 2006.285.23:29:35.61#ibcon#about to read 6, iclass 38, count 2 2006.285.23:29:35.61#ibcon#read 6, iclass 38, count 2 2006.285.23:29:35.61#ibcon#end of sib2, iclass 38, count 2 2006.285.23:29:35.61#ibcon#*after write, iclass 38, count 2 2006.285.23:29:35.61#ibcon#*before return 0, iclass 38, count 2 2006.285.23:29:35.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:29:35.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:29:35.61#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.23:29:35.61#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:35.61#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:29:35.73#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:29:35.73#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:29:35.73#ibcon#enter wrdev, iclass 38, count 0 2006.285.23:29:35.73#ibcon#first serial, iclass 38, count 0 2006.285.23:29:35.73#ibcon#enter sib2, iclass 38, count 0 2006.285.23:29:35.73#ibcon#flushed, iclass 38, count 0 2006.285.23:29:35.73#ibcon#about to write, iclass 38, count 0 2006.285.23:29:35.73#ibcon#wrote, iclass 38, count 0 2006.285.23:29:35.73#ibcon#about to read 3, iclass 38, count 0 2006.285.23:29:35.75#ibcon#read 3, iclass 38, count 0 2006.285.23:29:35.75#ibcon#about to read 4, iclass 38, count 0 2006.285.23:29:35.75#ibcon#read 4, iclass 38, count 0 2006.285.23:29:35.75#ibcon#about to read 5, iclass 38, count 0 2006.285.23:29:35.75#ibcon#read 5, iclass 38, count 0 2006.285.23:29:35.75#ibcon#about to read 6, iclass 38, count 0 2006.285.23:29:35.75#ibcon#read 6, iclass 38, count 0 2006.285.23:29:35.75#ibcon#end of sib2, iclass 38, count 0 2006.285.23:29:35.75#ibcon#*mode == 0, iclass 38, count 0 2006.285.23:29:35.75#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.23:29:35.75#ibcon#[25=USB\r\n] 2006.285.23:29:35.75#ibcon#*before write, iclass 38, count 0 2006.285.23:29:35.75#ibcon#enter sib2, iclass 38, count 0 2006.285.23:29:35.75#ibcon#flushed, iclass 38, count 0 2006.285.23:29:35.75#ibcon#about to write, iclass 38, count 0 2006.285.23:29:35.75#ibcon#wrote, iclass 38, count 0 2006.285.23:29:35.75#ibcon#about to read 3, iclass 38, count 0 2006.285.23:29:35.78#ibcon#read 3, iclass 38, count 0 2006.285.23:29:35.78#ibcon#about to read 4, iclass 38, count 0 2006.285.23:29:35.78#ibcon#read 4, iclass 38, count 0 2006.285.23:29:35.78#ibcon#about to read 5, iclass 38, count 0 2006.285.23:29:35.78#ibcon#read 5, iclass 38, count 0 2006.285.23:29:35.78#ibcon#about to read 6, iclass 38, count 0 2006.285.23:29:35.78#ibcon#read 6, iclass 38, count 0 2006.285.23:29:35.78#ibcon#end of sib2, iclass 38, count 0 2006.285.23:29:35.78#ibcon#*after write, iclass 38, count 0 2006.285.23:29:35.78#ibcon#*before return 0, iclass 38, count 0 2006.285.23:29:35.78#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:29:35.78#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:29:35.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.23:29:35.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.23:29:35.78$vck44/valo=6,814.99 2006.285.23:29:35.78#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.23:29:35.78#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.23:29:35.78#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:35.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:29:35.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:29:35.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:29:35.78#ibcon#enter wrdev, iclass 40, count 0 2006.285.23:29:35.78#ibcon#first serial, iclass 40, count 0 2006.285.23:29:35.78#ibcon#enter sib2, iclass 40, count 0 2006.285.23:29:35.78#ibcon#flushed, iclass 40, count 0 2006.285.23:29:35.78#ibcon#about to write, iclass 40, count 0 2006.285.23:29:35.78#ibcon#wrote, iclass 40, count 0 2006.285.23:29:35.78#ibcon#about to read 3, iclass 40, count 0 2006.285.23:29:35.80#ibcon#read 3, iclass 40, count 0 2006.285.23:29:35.80#ibcon#about to read 4, iclass 40, count 0 2006.285.23:29:35.80#ibcon#read 4, iclass 40, count 0 2006.285.23:29:35.80#ibcon#about to read 5, iclass 40, count 0 2006.285.23:29:35.80#ibcon#read 5, iclass 40, count 0 2006.285.23:29:35.80#ibcon#about to read 6, iclass 40, count 0 2006.285.23:29:35.80#ibcon#read 6, iclass 40, count 0 2006.285.23:29:35.80#ibcon#end of sib2, iclass 40, count 0 2006.285.23:29:35.80#ibcon#*mode == 0, iclass 40, count 0 2006.285.23:29:35.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.23:29:35.80#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.23:29:35.80#ibcon#*before write, iclass 40, count 0 2006.285.23:29:35.80#ibcon#enter sib2, iclass 40, count 0 2006.285.23:29:35.80#ibcon#flushed, iclass 40, count 0 2006.285.23:29:35.80#ibcon#about to write, iclass 40, count 0 2006.285.23:29:35.80#ibcon#wrote, iclass 40, count 0 2006.285.23:29:35.80#ibcon#about to read 3, iclass 40, count 0 2006.285.23:29:35.84#ibcon#read 3, iclass 40, count 0 2006.285.23:29:35.84#ibcon#about to read 4, iclass 40, count 0 2006.285.23:29:35.84#ibcon#read 4, iclass 40, count 0 2006.285.23:29:35.84#ibcon#about to read 5, iclass 40, count 0 2006.285.23:29:35.84#ibcon#read 5, iclass 40, count 0 2006.285.23:29:35.84#ibcon#about to read 6, iclass 40, count 0 2006.285.23:29:35.84#ibcon#read 6, iclass 40, count 0 2006.285.23:29:35.84#ibcon#end of sib2, iclass 40, count 0 2006.285.23:29:35.84#ibcon#*after write, iclass 40, count 0 2006.285.23:29:35.84#ibcon#*before return 0, iclass 40, count 0 2006.285.23:29:35.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:29:35.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:29:35.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.23:29:35.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.23:29:35.84$vck44/va=6,4 2006.285.23:29:35.84#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.23:29:35.84#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.23:29:35.84#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:35.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:29:35.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:29:35.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:29:35.90#ibcon#enter wrdev, iclass 4, count 2 2006.285.23:29:35.90#ibcon#first serial, iclass 4, count 2 2006.285.23:29:35.90#ibcon#enter sib2, iclass 4, count 2 2006.285.23:29:35.90#ibcon#flushed, iclass 4, count 2 2006.285.23:29:35.90#ibcon#about to write, iclass 4, count 2 2006.285.23:29:35.90#ibcon#wrote, iclass 4, count 2 2006.285.23:29:35.90#ibcon#about to read 3, iclass 4, count 2 2006.285.23:29:35.92#ibcon#read 3, iclass 4, count 2 2006.285.23:29:35.92#ibcon#about to read 4, iclass 4, count 2 2006.285.23:29:35.92#ibcon#read 4, iclass 4, count 2 2006.285.23:29:35.92#ibcon#about to read 5, iclass 4, count 2 2006.285.23:29:35.92#ibcon#read 5, iclass 4, count 2 2006.285.23:29:35.92#ibcon#about to read 6, iclass 4, count 2 2006.285.23:29:35.92#ibcon#read 6, iclass 4, count 2 2006.285.23:29:35.92#ibcon#end of sib2, iclass 4, count 2 2006.285.23:29:35.92#ibcon#*mode == 0, iclass 4, count 2 2006.285.23:29:35.92#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.23:29:35.92#ibcon#[25=AT06-04\r\n] 2006.285.23:29:35.92#ibcon#*before write, iclass 4, count 2 2006.285.23:29:35.92#ibcon#enter sib2, iclass 4, count 2 2006.285.23:29:35.92#ibcon#flushed, iclass 4, count 2 2006.285.23:29:35.92#ibcon#about to write, iclass 4, count 2 2006.285.23:29:35.92#ibcon#wrote, iclass 4, count 2 2006.285.23:29:35.92#ibcon#about to read 3, iclass 4, count 2 2006.285.23:29:35.95#ibcon#read 3, iclass 4, count 2 2006.285.23:29:35.95#ibcon#about to read 4, iclass 4, count 2 2006.285.23:29:35.95#ibcon#read 4, iclass 4, count 2 2006.285.23:29:35.95#ibcon#about to read 5, iclass 4, count 2 2006.285.23:29:35.95#ibcon#read 5, iclass 4, count 2 2006.285.23:29:35.95#ibcon#about to read 6, iclass 4, count 2 2006.285.23:29:35.95#ibcon#read 6, iclass 4, count 2 2006.285.23:29:35.95#ibcon#end of sib2, iclass 4, count 2 2006.285.23:29:35.95#ibcon#*after write, iclass 4, count 2 2006.285.23:29:35.95#ibcon#*before return 0, iclass 4, count 2 2006.285.23:29:35.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:29:35.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:29:35.95#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.23:29:35.95#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:35.95#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:29:36.07#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:29:36.07#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:29:36.07#ibcon#enter wrdev, iclass 4, count 0 2006.285.23:29:36.07#ibcon#first serial, iclass 4, count 0 2006.285.23:29:36.07#ibcon#enter sib2, iclass 4, count 0 2006.285.23:29:36.07#ibcon#flushed, iclass 4, count 0 2006.285.23:29:36.07#ibcon#about to write, iclass 4, count 0 2006.285.23:29:36.07#ibcon#wrote, iclass 4, count 0 2006.285.23:29:36.07#ibcon#about to read 3, iclass 4, count 0 2006.285.23:29:36.09#ibcon#read 3, iclass 4, count 0 2006.285.23:29:36.09#ibcon#about to read 4, iclass 4, count 0 2006.285.23:29:36.09#ibcon#read 4, iclass 4, count 0 2006.285.23:29:36.09#ibcon#about to read 5, iclass 4, count 0 2006.285.23:29:36.09#ibcon#read 5, iclass 4, count 0 2006.285.23:29:36.09#ibcon#about to read 6, iclass 4, count 0 2006.285.23:29:36.09#ibcon#read 6, iclass 4, count 0 2006.285.23:29:36.09#ibcon#end of sib2, iclass 4, count 0 2006.285.23:29:36.09#ibcon#*mode == 0, iclass 4, count 0 2006.285.23:29:36.09#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.23:29:36.09#ibcon#[25=USB\r\n] 2006.285.23:29:36.09#ibcon#*before write, iclass 4, count 0 2006.285.23:29:36.09#ibcon#enter sib2, iclass 4, count 0 2006.285.23:29:36.09#ibcon#flushed, iclass 4, count 0 2006.285.23:29:36.09#ibcon#about to write, iclass 4, count 0 2006.285.23:29:36.09#ibcon#wrote, iclass 4, count 0 2006.285.23:29:36.09#ibcon#about to read 3, iclass 4, count 0 2006.285.23:29:36.12#ibcon#read 3, iclass 4, count 0 2006.285.23:29:36.12#ibcon#about to read 4, iclass 4, count 0 2006.285.23:29:36.12#ibcon#read 4, iclass 4, count 0 2006.285.23:29:36.12#ibcon#about to read 5, iclass 4, count 0 2006.285.23:29:36.12#ibcon#read 5, iclass 4, count 0 2006.285.23:29:36.12#ibcon#about to read 6, iclass 4, count 0 2006.285.23:29:36.12#ibcon#read 6, iclass 4, count 0 2006.285.23:29:36.12#ibcon#end of sib2, iclass 4, count 0 2006.285.23:29:36.12#ibcon#*after write, iclass 4, count 0 2006.285.23:29:36.12#ibcon#*before return 0, iclass 4, count 0 2006.285.23:29:36.12#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:29:36.12#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:29:36.12#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.23:29:36.12#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.23:29:36.12$vck44/valo=7,864.99 2006.285.23:29:36.12#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.23:29:36.12#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.23:29:36.12#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:36.12#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:29:36.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:29:36.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:29:36.12#ibcon#enter wrdev, iclass 6, count 0 2006.285.23:29:36.12#ibcon#first serial, iclass 6, count 0 2006.285.23:29:36.12#ibcon#enter sib2, iclass 6, count 0 2006.285.23:29:36.12#ibcon#flushed, iclass 6, count 0 2006.285.23:29:36.12#ibcon#about to write, iclass 6, count 0 2006.285.23:29:36.12#ibcon#wrote, iclass 6, count 0 2006.285.23:29:36.12#ibcon#about to read 3, iclass 6, count 0 2006.285.23:29:36.14#ibcon#read 3, iclass 6, count 0 2006.285.23:29:36.14#ibcon#about to read 4, iclass 6, count 0 2006.285.23:29:36.14#ibcon#read 4, iclass 6, count 0 2006.285.23:29:36.14#ibcon#about to read 5, iclass 6, count 0 2006.285.23:29:36.14#ibcon#read 5, iclass 6, count 0 2006.285.23:29:36.14#ibcon#about to read 6, iclass 6, count 0 2006.285.23:29:36.14#ibcon#read 6, iclass 6, count 0 2006.285.23:29:36.14#ibcon#end of sib2, iclass 6, count 0 2006.285.23:29:36.14#ibcon#*mode == 0, iclass 6, count 0 2006.285.23:29:36.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.23:29:36.14#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.23:29:36.14#ibcon#*before write, iclass 6, count 0 2006.285.23:29:36.14#ibcon#enter sib2, iclass 6, count 0 2006.285.23:29:36.14#ibcon#flushed, iclass 6, count 0 2006.285.23:29:36.14#ibcon#about to write, iclass 6, count 0 2006.285.23:29:36.14#ibcon#wrote, iclass 6, count 0 2006.285.23:29:36.14#ibcon#about to read 3, iclass 6, count 0 2006.285.23:29:36.18#ibcon#read 3, iclass 6, count 0 2006.285.23:29:36.18#ibcon#about to read 4, iclass 6, count 0 2006.285.23:29:36.18#ibcon#read 4, iclass 6, count 0 2006.285.23:29:36.18#ibcon#about to read 5, iclass 6, count 0 2006.285.23:29:36.18#ibcon#read 5, iclass 6, count 0 2006.285.23:29:36.18#ibcon#about to read 6, iclass 6, count 0 2006.285.23:29:36.18#ibcon#read 6, iclass 6, count 0 2006.285.23:29:36.18#ibcon#end of sib2, iclass 6, count 0 2006.285.23:29:36.18#ibcon#*after write, iclass 6, count 0 2006.285.23:29:36.18#ibcon#*before return 0, iclass 6, count 0 2006.285.23:29:36.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:29:36.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:29:36.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.23:29:36.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.23:29:36.18$vck44/va=7,4 2006.285.23:29:36.18#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.23:29:36.18#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.23:29:36.18#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:36.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:29:36.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:29:36.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:29:36.24#ibcon#enter wrdev, iclass 10, count 2 2006.285.23:29:36.24#ibcon#first serial, iclass 10, count 2 2006.285.23:29:36.24#ibcon#enter sib2, iclass 10, count 2 2006.285.23:29:36.24#ibcon#flushed, iclass 10, count 2 2006.285.23:29:36.24#ibcon#about to write, iclass 10, count 2 2006.285.23:29:36.24#ibcon#wrote, iclass 10, count 2 2006.285.23:29:36.24#ibcon#about to read 3, iclass 10, count 2 2006.285.23:29:36.26#ibcon#read 3, iclass 10, count 2 2006.285.23:29:36.26#ibcon#about to read 4, iclass 10, count 2 2006.285.23:29:36.26#ibcon#read 4, iclass 10, count 2 2006.285.23:29:36.26#ibcon#about to read 5, iclass 10, count 2 2006.285.23:29:36.26#ibcon#read 5, iclass 10, count 2 2006.285.23:29:36.26#ibcon#about to read 6, iclass 10, count 2 2006.285.23:29:36.26#ibcon#read 6, iclass 10, count 2 2006.285.23:29:36.26#ibcon#end of sib2, iclass 10, count 2 2006.285.23:29:36.26#ibcon#*mode == 0, iclass 10, count 2 2006.285.23:29:36.26#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.23:29:36.26#ibcon#[25=AT07-04\r\n] 2006.285.23:29:36.26#ibcon#*before write, iclass 10, count 2 2006.285.23:29:36.26#ibcon#enter sib2, iclass 10, count 2 2006.285.23:29:36.26#ibcon#flushed, iclass 10, count 2 2006.285.23:29:36.26#ibcon#about to write, iclass 10, count 2 2006.285.23:29:36.26#ibcon#wrote, iclass 10, count 2 2006.285.23:29:36.26#ibcon#about to read 3, iclass 10, count 2 2006.285.23:29:36.29#ibcon#read 3, iclass 10, count 2 2006.285.23:29:36.29#ibcon#about to read 4, iclass 10, count 2 2006.285.23:29:36.29#ibcon#read 4, iclass 10, count 2 2006.285.23:29:36.29#ibcon#about to read 5, iclass 10, count 2 2006.285.23:29:36.29#ibcon#read 5, iclass 10, count 2 2006.285.23:29:36.29#ibcon#about to read 6, iclass 10, count 2 2006.285.23:29:36.29#ibcon#read 6, iclass 10, count 2 2006.285.23:29:36.29#ibcon#end of sib2, iclass 10, count 2 2006.285.23:29:36.29#ibcon#*after write, iclass 10, count 2 2006.285.23:29:36.29#ibcon#*before return 0, iclass 10, count 2 2006.285.23:29:36.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:29:36.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:29:36.29#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.23:29:36.29#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:36.29#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:29:36.41#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:29:36.41#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:29:36.41#ibcon#enter wrdev, iclass 10, count 0 2006.285.23:29:36.41#ibcon#first serial, iclass 10, count 0 2006.285.23:29:36.41#ibcon#enter sib2, iclass 10, count 0 2006.285.23:29:36.41#ibcon#flushed, iclass 10, count 0 2006.285.23:29:36.41#ibcon#about to write, iclass 10, count 0 2006.285.23:29:36.41#ibcon#wrote, iclass 10, count 0 2006.285.23:29:36.41#ibcon#about to read 3, iclass 10, count 0 2006.285.23:29:36.43#ibcon#read 3, iclass 10, count 0 2006.285.23:29:36.43#ibcon#about to read 4, iclass 10, count 0 2006.285.23:29:36.43#ibcon#read 4, iclass 10, count 0 2006.285.23:29:36.43#ibcon#about to read 5, iclass 10, count 0 2006.285.23:29:36.43#ibcon#read 5, iclass 10, count 0 2006.285.23:29:36.43#ibcon#about to read 6, iclass 10, count 0 2006.285.23:29:36.43#ibcon#read 6, iclass 10, count 0 2006.285.23:29:36.43#ibcon#end of sib2, iclass 10, count 0 2006.285.23:29:36.43#ibcon#*mode == 0, iclass 10, count 0 2006.285.23:29:36.43#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.23:29:36.43#ibcon#[25=USB\r\n] 2006.285.23:29:36.43#ibcon#*before write, iclass 10, count 0 2006.285.23:29:36.43#ibcon#enter sib2, iclass 10, count 0 2006.285.23:29:36.43#ibcon#flushed, iclass 10, count 0 2006.285.23:29:36.43#ibcon#about to write, iclass 10, count 0 2006.285.23:29:36.43#ibcon#wrote, iclass 10, count 0 2006.285.23:29:36.43#ibcon#about to read 3, iclass 10, count 0 2006.285.23:29:36.46#ibcon#read 3, iclass 10, count 0 2006.285.23:29:36.46#ibcon#about to read 4, iclass 10, count 0 2006.285.23:29:36.46#ibcon#read 4, iclass 10, count 0 2006.285.23:29:36.46#ibcon#about to read 5, iclass 10, count 0 2006.285.23:29:36.46#ibcon#read 5, iclass 10, count 0 2006.285.23:29:36.46#ibcon#about to read 6, iclass 10, count 0 2006.285.23:29:36.46#ibcon#read 6, iclass 10, count 0 2006.285.23:29:36.46#ibcon#end of sib2, iclass 10, count 0 2006.285.23:29:36.46#ibcon#*after write, iclass 10, count 0 2006.285.23:29:36.46#ibcon#*before return 0, iclass 10, count 0 2006.285.23:29:36.46#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:29:36.46#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:29:36.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.23:29:36.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.23:29:36.46$vck44/valo=8,884.99 2006.285.23:29:36.46#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.23:29:36.46#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.23:29:36.46#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:36.46#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:29:36.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:29:36.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:29:36.46#ibcon#enter wrdev, iclass 12, count 0 2006.285.23:29:36.46#ibcon#first serial, iclass 12, count 0 2006.285.23:29:36.46#ibcon#enter sib2, iclass 12, count 0 2006.285.23:29:36.46#ibcon#flushed, iclass 12, count 0 2006.285.23:29:36.46#ibcon#about to write, iclass 12, count 0 2006.285.23:29:36.46#ibcon#wrote, iclass 12, count 0 2006.285.23:29:36.46#ibcon#about to read 3, iclass 12, count 0 2006.285.23:29:36.48#ibcon#read 3, iclass 12, count 0 2006.285.23:29:36.48#ibcon#about to read 4, iclass 12, count 0 2006.285.23:29:36.48#ibcon#read 4, iclass 12, count 0 2006.285.23:29:36.48#ibcon#about to read 5, iclass 12, count 0 2006.285.23:29:36.48#ibcon#read 5, iclass 12, count 0 2006.285.23:29:36.48#ibcon#about to read 6, iclass 12, count 0 2006.285.23:29:36.48#ibcon#read 6, iclass 12, count 0 2006.285.23:29:36.48#ibcon#end of sib2, iclass 12, count 0 2006.285.23:29:36.48#ibcon#*mode == 0, iclass 12, count 0 2006.285.23:29:36.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.23:29:36.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.23:29:36.48#ibcon#*before write, iclass 12, count 0 2006.285.23:29:36.48#ibcon#enter sib2, iclass 12, count 0 2006.285.23:29:36.48#ibcon#flushed, iclass 12, count 0 2006.285.23:29:36.48#ibcon#about to write, iclass 12, count 0 2006.285.23:29:36.48#ibcon#wrote, iclass 12, count 0 2006.285.23:29:36.48#ibcon#about to read 3, iclass 12, count 0 2006.285.23:29:36.52#ibcon#read 3, iclass 12, count 0 2006.285.23:29:36.52#ibcon#about to read 4, iclass 12, count 0 2006.285.23:29:36.52#ibcon#read 4, iclass 12, count 0 2006.285.23:29:36.52#ibcon#about to read 5, iclass 12, count 0 2006.285.23:29:36.52#ibcon#read 5, iclass 12, count 0 2006.285.23:29:36.52#ibcon#about to read 6, iclass 12, count 0 2006.285.23:29:36.52#ibcon#read 6, iclass 12, count 0 2006.285.23:29:36.52#ibcon#end of sib2, iclass 12, count 0 2006.285.23:29:36.52#ibcon#*after write, iclass 12, count 0 2006.285.23:29:36.52#ibcon#*before return 0, iclass 12, count 0 2006.285.23:29:36.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:29:36.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:29:36.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.23:29:36.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.23:29:36.52$vck44/va=8,3 2006.285.23:29:36.52#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.23:29:36.52#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.23:29:36.52#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:36.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.23:29:36.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.23:29:36.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.23:29:36.58#ibcon#enter wrdev, iclass 14, count 2 2006.285.23:29:36.58#ibcon#first serial, iclass 14, count 2 2006.285.23:29:36.58#ibcon#enter sib2, iclass 14, count 2 2006.285.23:29:36.58#ibcon#flushed, iclass 14, count 2 2006.285.23:29:36.58#ibcon#about to write, iclass 14, count 2 2006.285.23:29:36.58#ibcon#wrote, iclass 14, count 2 2006.285.23:29:36.58#ibcon#about to read 3, iclass 14, count 2 2006.285.23:29:36.60#ibcon#read 3, iclass 14, count 2 2006.285.23:29:36.60#ibcon#about to read 4, iclass 14, count 2 2006.285.23:29:36.60#ibcon#read 4, iclass 14, count 2 2006.285.23:29:36.60#ibcon#about to read 5, iclass 14, count 2 2006.285.23:29:36.60#ibcon#read 5, iclass 14, count 2 2006.285.23:29:36.60#ibcon#about to read 6, iclass 14, count 2 2006.285.23:29:36.60#ibcon#read 6, iclass 14, count 2 2006.285.23:29:36.60#ibcon#end of sib2, iclass 14, count 2 2006.285.23:29:36.60#ibcon#*mode == 0, iclass 14, count 2 2006.285.23:29:36.60#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.23:29:36.60#ibcon#[25=AT08-03\r\n] 2006.285.23:29:36.60#ibcon#*before write, iclass 14, count 2 2006.285.23:29:36.60#ibcon#enter sib2, iclass 14, count 2 2006.285.23:29:36.60#ibcon#flushed, iclass 14, count 2 2006.285.23:29:36.60#ibcon#about to write, iclass 14, count 2 2006.285.23:29:36.60#ibcon#wrote, iclass 14, count 2 2006.285.23:29:36.60#ibcon#about to read 3, iclass 14, count 2 2006.285.23:29:36.63#ibcon#read 3, iclass 14, count 2 2006.285.23:29:36.63#ibcon#about to read 4, iclass 14, count 2 2006.285.23:29:36.63#ibcon#read 4, iclass 14, count 2 2006.285.23:29:36.63#ibcon#about to read 5, iclass 14, count 2 2006.285.23:29:36.63#ibcon#read 5, iclass 14, count 2 2006.285.23:29:36.63#ibcon#about to read 6, iclass 14, count 2 2006.285.23:29:36.63#ibcon#read 6, iclass 14, count 2 2006.285.23:29:36.63#ibcon#end of sib2, iclass 14, count 2 2006.285.23:29:36.63#ibcon#*after write, iclass 14, count 2 2006.285.23:29:36.63#ibcon#*before return 0, iclass 14, count 2 2006.285.23:29:36.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.23:29:36.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.23:29:36.63#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.23:29:36.63#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:36.63#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.23:29:36.75#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.23:29:36.75#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.23:29:36.75#ibcon#enter wrdev, iclass 14, count 0 2006.285.23:29:36.75#ibcon#first serial, iclass 14, count 0 2006.285.23:29:36.75#ibcon#enter sib2, iclass 14, count 0 2006.285.23:29:36.75#ibcon#flushed, iclass 14, count 0 2006.285.23:29:36.75#ibcon#about to write, iclass 14, count 0 2006.285.23:29:36.75#ibcon#wrote, iclass 14, count 0 2006.285.23:29:36.75#ibcon#about to read 3, iclass 14, count 0 2006.285.23:29:36.77#ibcon#read 3, iclass 14, count 0 2006.285.23:29:36.77#ibcon#about to read 4, iclass 14, count 0 2006.285.23:29:36.77#ibcon#read 4, iclass 14, count 0 2006.285.23:29:36.77#ibcon#about to read 5, iclass 14, count 0 2006.285.23:29:36.77#ibcon#read 5, iclass 14, count 0 2006.285.23:29:36.77#ibcon#about to read 6, iclass 14, count 0 2006.285.23:29:36.77#ibcon#read 6, iclass 14, count 0 2006.285.23:29:36.77#ibcon#end of sib2, iclass 14, count 0 2006.285.23:29:36.77#ibcon#*mode == 0, iclass 14, count 0 2006.285.23:29:36.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.23:29:36.77#ibcon#[25=USB\r\n] 2006.285.23:29:36.77#ibcon#*before write, iclass 14, count 0 2006.285.23:29:36.77#ibcon#enter sib2, iclass 14, count 0 2006.285.23:29:36.77#ibcon#flushed, iclass 14, count 0 2006.285.23:29:36.77#ibcon#about to write, iclass 14, count 0 2006.285.23:29:36.77#ibcon#wrote, iclass 14, count 0 2006.285.23:29:36.77#ibcon#about to read 3, iclass 14, count 0 2006.285.23:29:36.80#ibcon#read 3, iclass 14, count 0 2006.285.23:29:36.80#ibcon#about to read 4, iclass 14, count 0 2006.285.23:29:36.80#ibcon#read 4, iclass 14, count 0 2006.285.23:29:36.80#ibcon#about to read 5, iclass 14, count 0 2006.285.23:29:36.80#ibcon#read 5, iclass 14, count 0 2006.285.23:29:36.80#ibcon#about to read 6, iclass 14, count 0 2006.285.23:29:36.80#ibcon#read 6, iclass 14, count 0 2006.285.23:29:36.80#ibcon#end of sib2, iclass 14, count 0 2006.285.23:29:36.80#ibcon#*after write, iclass 14, count 0 2006.285.23:29:36.80#ibcon#*before return 0, iclass 14, count 0 2006.285.23:29:36.80#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.23:29:36.80#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.23:29:36.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.23:29:36.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.23:29:36.80$vck44/vblo=1,629.99 2006.285.23:29:36.80#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.23:29:36.80#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.23:29:36.80#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:36.80#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:29:36.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:29:36.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:29:36.80#ibcon#enter wrdev, iclass 16, count 0 2006.285.23:29:36.80#ibcon#first serial, iclass 16, count 0 2006.285.23:29:36.80#ibcon#enter sib2, iclass 16, count 0 2006.285.23:29:36.80#ibcon#flushed, iclass 16, count 0 2006.285.23:29:36.80#ibcon#about to write, iclass 16, count 0 2006.285.23:29:36.80#ibcon#wrote, iclass 16, count 0 2006.285.23:29:36.80#ibcon#about to read 3, iclass 16, count 0 2006.285.23:29:36.82#ibcon#read 3, iclass 16, count 0 2006.285.23:29:36.82#ibcon#about to read 4, iclass 16, count 0 2006.285.23:29:36.82#ibcon#read 4, iclass 16, count 0 2006.285.23:29:36.82#ibcon#about to read 5, iclass 16, count 0 2006.285.23:29:36.82#ibcon#read 5, iclass 16, count 0 2006.285.23:29:36.82#ibcon#about to read 6, iclass 16, count 0 2006.285.23:29:36.82#ibcon#read 6, iclass 16, count 0 2006.285.23:29:36.82#ibcon#end of sib2, iclass 16, count 0 2006.285.23:29:36.82#ibcon#*mode == 0, iclass 16, count 0 2006.285.23:29:36.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.23:29:36.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.23:29:36.82#ibcon#*before write, iclass 16, count 0 2006.285.23:29:36.82#ibcon#enter sib2, iclass 16, count 0 2006.285.23:29:36.82#ibcon#flushed, iclass 16, count 0 2006.285.23:29:36.82#ibcon#about to write, iclass 16, count 0 2006.285.23:29:36.82#ibcon#wrote, iclass 16, count 0 2006.285.23:29:36.82#ibcon#about to read 3, iclass 16, count 0 2006.285.23:29:36.86#ibcon#read 3, iclass 16, count 0 2006.285.23:29:36.86#ibcon#about to read 4, iclass 16, count 0 2006.285.23:29:36.86#ibcon#read 4, iclass 16, count 0 2006.285.23:29:36.86#ibcon#about to read 5, iclass 16, count 0 2006.285.23:29:36.86#ibcon#read 5, iclass 16, count 0 2006.285.23:29:36.86#ibcon#about to read 6, iclass 16, count 0 2006.285.23:29:36.86#ibcon#read 6, iclass 16, count 0 2006.285.23:29:36.86#ibcon#end of sib2, iclass 16, count 0 2006.285.23:29:36.86#ibcon#*after write, iclass 16, count 0 2006.285.23:29:36.86#ibcon#*before return 0, iclass 16, count 0 2006.285.23:29:36.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:29:36.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:29:36.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.23:29:36.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.23:29:36.86$vck44/vb=1,4 2006.285.23:29:36.86#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.23:29:36.86#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.23:29:36.86#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:36.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:29:36.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:29:36.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:29:36.86#ibcon#enter wrdev, iclass 18, count 2 2006.285.23:29:36.86#ibcon#first serial, iclass 18, count 2 2006.285.23:29:36.86#ibcon#enter sib2, iclass 18, count 2 2006.285.23:29:36.86#ibcon#flushed, iclass 18, count 2 2006.285.23:29:36.86#ibcon#about to write, iclass 18, count 2 2006.285.23:29:36.86#ibcon#wrote, iclass 18, count 2 2006.285.23:29:36.86#ibcon#about to read 3, iclass 18, count 2 2006.285.23:29:36.88#ibcon#read 3, iclass 18, count 2 2006.285.23:29:36.88#ibcon#about to read 4, iclass 18, count 2 2006.285.23:29:36.88#ibcon#read 4, iclass 18, count 2 2006.285.23:29:36.88#ibcon#about to read 5, iclass 18, count 2 2006.285.23:29:36.88#ibcon#read 5, iclass 18, count 2 2006.285.23:29:36.88#ibcon#about to read 6, iclass 18, count 2 2006.285.23:29:36.88#ibcon#read 6, iclass 18, count 2 2006.285.23:29:36.88#ibcon#end of sib2, iclass 18, count 2 2006.285.23:29:36.88#ibcon#*mode == 0, iclass 18, count 2 2006.285.23:29:36.88#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.23:29:36.88#ibcon#[27=AT01-04\r\n] 2006.285.23:29:36.88#ibcon#*before write, iclass 18, count 2 2006.285.23:29:36.88#ibcon#enter sib2, iclass 18, count 2 2006.285.23:29:36.88#ibcon#flushed, iclass 18, count 2 2006.285.23:29:36.88#ibcon#about to write, iclass 18, count 2 2006.285.23:29:36.88#ibcon#wrote, iclass 18, count 2 2006.285.23:29:36.88#ibcon#about to read 3, iclass 18, count 2 2006.285.23:29:36.91#ibcon#read 3, iclass 18, count 2 2006.285.23:29:36.91#ibcon#about to read 4, iclass 18, count 2 2006.285.23:29:36.91#ibcon#read 4, iclass 18, count 2 2006.285.23:29:36.91#ibcon#about to read 5, iclass 18, count 2 2006.285.23:29:36.91#ibcon#read 5, iclass 18, count 2 2006.285.23:29:36.91#ibcon#about to read 6, iclass 18, count 2 2006.285.23:29:36.91#ibcon#read 6, iclass 18, count 2 2006.285.23:29:36.91#ibcon#end of sib2, iclass 18, count 2 2006.285.23:29:36.91#ibcon#*after write, iclass 18, count 2 2006.285.23:29:36.91#ibcon#*before return 0, iclass 18, count 2 2006.285.23:29:36.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:29:36.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:29:36.91#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.23:29:36.91#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:36.91#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:29:37.03#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:29:37.03#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:29:37.03#ibcon#enter wrdev, iclass 18, count 0 2006.285.23:29:37.03#ibcon#first serial, iclass 18, count 0 2006.285.23:29:37.03#ibcon#enter sib2, iclass 18, count 0 2006.285.23:29:37.03#ibcon#flushed, iclass 18, count 0 2006.285.23:29:37.03#ibcon#about to write, iclass 18, count 0 2006.285.23:29:37.03#ibcon#wrote, iclass 18, count 0 2006.285.23:29:37.03#ibcon#about to read 3, iclass 18, count 0 2006.285.23:29:37.05#ibcon#read 3, iclass 18, count 0 2006.285.23:29:37.05#ibcon#about to read 4, iclass 18, count 0 2006.285.23:29:37.05#ibcon#read 4, iclass 18, count 0 2006.285.23:29:37.05#ibcon#about to read 5, iclass 18, count 0 2006.285.23:29:37.05#ibcon#read 5, iclass 18, count 0 2006.285.23:29:37.05#ibcon#about to read 6, iclass 18, count 0 2006.285.23:29:37.05#ibcon#read 6, iclass 18, count 0 2006.285.23:29:37.05#ibcon#end of sib2, iclass 18, count 0 2006.285.23:29:37.05#ibcon#*mode == 0, iclass 18, count 0 2006.285.23:29:37.05#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.23:29:37.05#ibcon#[27=USB\r\n] 2006.285.23:29:37.05#ibcon#*before write, iclass 18, count 0 2006.285.23:29:37.05#ibcon#enter sib2, iclass 18, count 0 2006.285.23:29:37.05#ibcon#flushed, iclass 18, count 0 2006.285.23:29:37.05#ibcon#about to write, iclass 18, count 0 2006.285.23:29:37.05#ibcon#wrote, iclass 18, count 0 2006.285.23:29:37.05#ibcon#about to read 3, iclass 18, count 0 2006.285.23:29:37.08#ibcon#read 3, iclass 18, count 0 2006.285.23:29:37.08#ibcon#about to read 4, iclass 18, count 0 2006.285.23:29:37.08#ibcon#read 4, iclass 18, count 0 2006.285.23:29:37.08#ibcon#about to read 5, iclass 18, count 0 2006.285.23:29:37.08#ibcon#read 5, iclass 18, count 0 2006.285.23:29:37.08#ibcon#about to read 6, iclass 18, count 0 2006.285.23:29:37.08#ibcon#read 6, iclass 18, count 0 2006.285.23:29:37.08#ibcon#end of sib2, iclass 18, count 0 2006.285.23:29:37.08#ibcon#*after write, iclass 18, count 0 2006.285.23:29:37.08#ibcon#*before return 0, iclass 18, count 0 2006.285.23:29:37.08#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:29:37.08#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:29:37.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.23:29:37.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.23:29:37.08$vck44/vblo=2,634.99 2006.285.23:29:37.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.23:29:37.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.23:29:37.08#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:37.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:29:37.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:29:37.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:29:37.08#ibcon#enter wrdev, iclass 20, count 0 2006.285.23:29:37.08#ibcon#first serial, iclass 20, count 0 2006.285.23:29:37.08#ibcon#enter sib2, iclass 20, count 0 2006.285.23:29:37.08#ibcon#flushed, iclass 20, count 0 2006.285.23:29:37.08#ibcon#about to write, iclass 20, count 0 2006.285.23:29:37.08#ibcon#wrote, iclass 20, count 0 2006.285.23:29:37.08#ibcon#about to read 3, iclass 20, count 0 2006.285.23:29:37.10#ibcon#read 3, iclass 20, count 0 2006.285.23:29:37.10#ibcon#about to read 4, iclass 20, count 0 2006.285.23:29:37.10#ibcon#read 4, iclass 20, count 0 2006.285.23:29:37.10#ibcon#about to read 5, iclass 20, count 0 2006.285.23:29:37.10#ibcon#read 5, iclass 20, count 0 2006.285.23:29:37.10#ibcon#about to read 6, iclass 20, count 0 2006.285.23:29:37.10#ibcon#read 6, iclass 20, count 0 2006.285.23:29:37.10#ibcon#end of sib2, iclass 20, count 0 2006.285.23:29:37.10#ibcon#*mode == 0, iclass 20, count 0 2006.285.23:29:37.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.23:29:37.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.23:29:37.10#ibcon#*before write, iclass 20, count 0 2006.285.23:29:37.10#ibcon#enter sib2, iclass 20, count 0 2006.285.23:29:37.10#ibcon#flushed, iclass 20, count 0 2006.285.23:29:37.10#ibcon#about to write, iclass 20, count 0 2006.285.23:29:37.10#ibcon#wrote, iclass 20, count 0 2006.285.23:29:37.10#ibcon#about to read 3, iclass 20, count 0 2006.285.23:29:37.14#ibcon#read 3, iclass 20, count 0 2006.285.23:29:37.14#ibcon#about to read 4, iclass 20, count 0 2006.285.23:29:37.14#ibcon#read 4, iclass 20, count 0 2006.285.23:29:37.14#ibcon#about to read 5, iclass 20, count 0 2006.285.23:29:37.14#ibcon#read 5, iclass 20, count 0 2006.285.23:29:37.14#ibcon#about to read 6, iclass 20, count 0 2006.285.23:29:37.14#ibcon#read 6, iclass 20, count 0 2006.285.23:29:37.14#ibcon#end of sib2, iclass 20, count 0 2006.285.23:29:37.14#ibcon#*after write, iclass 20, count 0 2006.285.23:29:37.14#ibcon#*before return 0, iclass 20, count 0 2006.285.23:29:37.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:29:37.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:29:37.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.23:29:37.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.23:29:37.14$vck44/vb=2,5 2006.285.23:29:37.14#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.23:29:37.14#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.23:29:37.14#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:37.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:29:37.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:29:37.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:29:37.20#ibcon#enter wrdev, iclass 22, count 2 2006.285.23:29:37.20#ibcon#first serial, iclass 22, count 2 2006.285.23:29:37.20#ibcon#enter sib2, iclass 22, count 2 2006.285.23:29:37.20#ibcon#flushed, iclass 22, count 2 2006.285.23:29:37.20#ibcon#about to write, iclass 22, count 2 2006.285.23:29:37.20#ibcon#wrote, iclass 22, count 2 2006.285.23:29:37.20#ibcon#about to read 3, iclass 22, count 2 2006.285.23:29:37.22#ibcon#read 3, iclass 22, count 2 2006.285.23:29:37.22#ibcon#about to read 4, iclass 22, count 2 2006.285.23:29:37.22#ibcon#read 4, iclass 22, count 2 2006.285.23:29:37.22#ibcon#about to read 5, iclass 22, count 2 2006.285.23:29:37.22#ibcon#read 5, iclass 22, count 2 2006.285.23:29:37.22#ibcon#about to read 6, iclass 22, count 2 2006.285.23:29:37.22#ibcon#read 6, iclass 22, count 2 2006.285.23:29:37.22#ibcon#end of sib2, iclass 22, count 2 2006.285.23:29:37.22#ibcon#*mode == 0, iclass 22, count 2 2006.285.23:29:37.22#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.23:29:37.22#ibcon#[27=AT02-05\r\n] 2006.285.23:29:37.22#ibcon#*before write, iclass 22, count 2 2006.285.23:29:37.22#ibcon#enter sib2, iclass 22, count 2 2006.285.23:29:37.22#ibcon#flushed, iclass 22, count 2 2006.285.23:29:37.22#ibcon#about to write, iclass 22, count 2 2006.285.23:29:37.22#ibcon#wrote, iclass 22, count 2 2006.285.23:29:37.22#ibcon#about to read 3, iclass 22, count 2 2006.285.23:29:37.25#ibcon#read 3, iclass 22, count 2 2006.285.23:29:37.25#ibcon#about to read 4, iclass 22, count 2 2006.285.23:29:37.25#ibcon#read 4, iclass 22, count 2 2006.285.23:29:37.25#ibcon#about to read 5, iclass 22, count 2 2006.285.23:29:37.25#ibcon#read 5, iclass 22, count 2 2006.285.23:29:37.25#ibcon#about to read 6, iclass 22, count 2 2006.285.23:29:37.25#ibcon#read 6, iclass 22, count 2 2006.285.23:29:37.25#ibcon#end of sib2, iclass 22, count 2 2006.285.23:29:37.25#ibcon#*after write, iclass 22, count 2 2006.285.23:29:37.25#ibcon#*before return 0, iclass 22, count 2 2006.285.23:29:37.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:29:37.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:29:37.25#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.23:29:37.25#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:37.25#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:29:37.37#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:29:37.37#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:29:37.37#ibcon#enter wrdev, iclass 22, count 0 2006.285.23:29:37.37#ibcon#first serial, iclass 22, count 0 2006.285.23:29:37.37#ibcon#enter sib2, iclass 22, count 0 2006.285.23:29:37.37#ibcon#flushed, iclass 22, count 0 2006.285.23:29:37.37#ibcon#about to write, iclass 22, count 0 2006.285.23:29:37.37#ibcon#wrote, iclass 22, count 0 2006.285.23:29:37.37#ibcon#about to read 3, iclass 22, count 0 2006.285.23:29:37.39#ibcon#read 3, iclass 22, count 0 2006.285.23:29:37.39#ibcon#about to read 4, iclass 22, count 0 2006.285.23:29:37.39#ibcon#read 4, iclass 22, count 0 2006.285.23:29:37.39#ibcon#about to read 5, iclass 22, count 0 2006.285.23:29:37.39#ibcon#read 5, iclass 22, count 0 2006.285.23:29:37.39#ibcon#about to read 6, iclass 22, count 0 2006.285.23:29:37.39#ibcon#read 6, iclass 22, count 0 2006.285.23:29:37.39#ibcon#end of sib2, iclass 22, count 0 2006.285.23:29:37.39#ibcon#*mode == 0, iclass 22, count 0 2006.285.23:29:37.39#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.23:29:37.39#ibcon#[27=USB\r\n] 2006.285.23:29:37.39#ibcon#*before write, iclass 22, count 0 2006.285.23:29:37.39#ibcon#enter sib2, iclass 22, count 0 2006.285.23:29:37.39#ibcon#flushed, iclass 22, count 0 2006.285.23:29:37.39#ibcon#about to write, iclass 22, count 0 2006.285.23:29:37.39#ibcon#wrote, iclass 22, count 0 2006.285.23:29:37.39#ibcon#about to read 3, iclass 22, count 0 2006.285.23:29:37.42#ibcon#read 3, iclass 22, count 0 2006.285.23:29:37.42#ibcon#about to read 4, iclass 22, count 0 2006.285.23:29:37.42#ibcon#read 4, iclass 22, count 0 2006.285.23:29:37.42#ibcon#about to read 5, iclass 22, count 0 2006.285.23:29:37.42#ibcon#read 5, iclass 22, count 0 2006.285.23:29:37.42#ibcon#about to read 6, iclass 22, count 0 2006.285.23:29:37.42#ibcon#read 6, iclass 22, count 0 2006.285.23:29:37.42#ibcon#end of sib2, iclass 22, count 0 2006.285.23:29:37.42#ibcon#*after write, iclass 22, count 0 2006.285.23:29:37.42#ibcon#*before return 0, iclass 22, count 0 2006.285.23:29:37.42#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:29:37.42#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:29:37.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.23:29:37.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.23:29:37.42$vck44/vblo=3,649.99 2006.285.23:29:37.42#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.23:29:37.42#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.23:29:37.42#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:37.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:29:37.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:29:37.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:29:37.42#ibcon#enter wrdev, iclass 24, count 0 2006.285.23:29:37.42#ibcon#first serial, iclass 24, count 0 2006.285.23:29:37.42#ibcon#enter sib2, iclass 24, count 0 2006.285.23:29:37.42#ibcon#flushed, iclass 24, count 0 2006.285.23:29:37.42#ibcon#about to write, iclass 24, count 0 2006.285.23:29:37.42#ibcon#wrote, iclass 24, count 0 2006.285.23:29:37.42#ibcon#about to read 3, iclass 24, count 0 2006.285.23:29:37.44#ibcon#read 3, iclass 24, count 0 2006.285.23:29:37.44#ibcon#about to read 4, iclass 24, count 0 2006.285.23:29:37.44#ibcon#read 4, iclass 24, count 0 2006.285.23:29:37.44#ibcon#about to read 5, iclass 24, count 0 2006.285.23:29:37.44#ibcon#read 5, iclass 24, count 0 2006.285.23:29:37.44#ibcon#about to read 6, iclass 24, count 0 2006.285.23:29:37.44#ibcon#read 6, iclass 24, count 0 2006.285.23:29:37.44#ibcon#end of sib2, iclass 24, count 0 2006.285.23:29:37.44#ibcon#*mode == 0, iclass 24, count 0 2006.285.23:29:37.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.23:29:37.44#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.23:29:37.44#ibcon#*before write, iclass 24, count 0 2006.285.23:29:37.44#ibcon#enter sib2, iclass 24, count 0 2006.285.23:29:37.44#ibcon#flushed, iclass 24, count 0 2006.285.23:29:37.44#ibcon#about to write, iclass 24, count 0 2006.285.23:29:37.44#ibcon#wrote, iclass 24, count 0 2006.285.23:29:37.44#ibcon#about to read 3, iclass 24, count 0 2006.285.23:29:37.48#ibcon#read 3, iclass 24, count 0 2006.285.23:29:37.48#ibcon#about to read 4, iclass 24, count 0 2006.285.23:29:37.48#ibcon#read 4, iclass 24, count 0 2006.285.23:29:37.48#ibcon#about to read 5, iclass 24, count 0 2006.285.23:29:37.48#ibcon#read 5, iclass 24, count 0 2006.285.23:29:37.48#ibcon#about to read 6, iclass 24, count 0 2006.285.23:29:37.48#ibcon#read 6, iclass 24, count 0 2006.285.23:29:37.48#ibcon#end of sib2, iclass 24, count 0 2006.285.23:29:37.48#ibcon#*after write, iclass 24, count 0 2006.285.23:29:37.48#ibcon#*before return 0, iclass 24, count 0 2006.285.23:29:37.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:29:37.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:29:37.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.23:29:37.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.23:29:37.48$vck44/vb=3,4 2006.285.23:29:37.48#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.23:29:37.48#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.23:29:37.48#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:37.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:29:37.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:29:37.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:29:37.54#ibcon#enter wrdev, iclass 26, count 2 2006.285.23:29:37.54#ibcon#first serial, iclass 26, count 2 2006.285.23:29:37.54#ibcon#enter sib2, iclass 26, count 2 2006.285.23:29:37.54#ibcon#flushed, iclass 26, count 2 2006.285.23:29:37.54#ibcon#about to write, iclass 26, count 2 2006.285.23:29:37.54#ibcon#wrote, iclass 26, count 2 2006.285.23:29:37.54#ibcon#about to read 3, iclass 26, count 2 2006.285.23:29:37.56#ibcon#read 3, iclass 26, count 2 2006.285.23:29:37.56#ibcon#about to read 4, iclass 26, count 2 2006.285.23:29:37.56#ibcon#read 4, iclass 26, count 2 2006.285.23:29:37.56#ibcon#about to read 5, iclass 26, count 2 2006.285.23:29:37.56#ibcon#read 5, iclass 26, count 2 2006.285.23:29:37.56#ibcon#about to read 6, iclass 26, count 2 2006.285.23:29:37.56#ibcon#read 6, iclass 26, count 2 2006.285.23:29:37.56#ibcon#end of sib2, iclass 26, count 2 2006.285.23:29:37.56#ibcon#*mode == 0, iclass 26, count 2 2006.285.23:29:37.56#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.23:29:37.56#ibcon#[27=AT03-04\r\n] 2006.285.23:29:37.56#ibcon#*before write, iclass 26, count 2 2006.285.23:29:37.56#ibcon#enter sib2, iclass 26, count 2 2006.285.23:29:37.56#ibcon#flushed, iclass 26, count 2 2006.285.23:29:37.56#ibcon#about to write, iclass 26, count 2 2006.285.23:29:37.56#ibcon#wrote, iclass 26, count 2 2006.285.23:29:37.56#ibcon#about to read 3, iclass 26, count 2 2006.285.23:29:37.59#ibcon#read 3, iclass 26, count 2 2006.285.23:29:37.59#ibcon#about to read 4, iclass 26, count 2 2006.285.23:29:37.59#ibcon#read 4, iclass 26, count 2 2006.285.23:29:37.59#ibcon#about to read 5, iclass 26, count 2 2006.285.23:29:37.59#ibcon#read 5, iclass 26, count 2 2006.285.23:29:37.59#ibcon#about to read 6, iclass 26, count 2 2006.285.23:29:37.59#ibcon#read 6, iclass 26, count 2 2006.285.23:29:37.59#ibcon#end of sib2, iclass 26, count 2 2006.285.23:29:37.59#ibcon#*after write, iclass 26, count 2 2006.285.23:29:37.59#ibcon#*before return 0, iclass 26, count 2 2006.285.23:29:37.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:29:37.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:29:37.59#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.23:29:37.59#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:37.59#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:29:37.71#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:29:37.71#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:29:37.71#ibcon#enter wrdev, iclass 26, count 0 2006.285.23:29:37.71#ibcon#first serial, iclass 26, count 0 2006.285.23:29:37.71#ibcon#enter sib2, iclass 26, count 0 2006.285.23:29:37.71#ibcon#flushed, iclass 26, count 0 2006.285.23:29:37.71#ibcon#about to write, iclass 26, count 0 2006.285.23:29:37.71#ibcon#wrote, iclass 26, count 0 2006.285.23:29:37.71#ibcon#about to read 3, iclass 26, count 0 2006.285.23:29:37.73#ibcon#read 3, iclass 26, count 0 2006.285.23:29:37.73#ibcon#about to read 4, iclass 26, count 0 2006.285.23:29:37.73#ibcon#read 4, iclass 26, count 0 2006.285.23:29:37.73#ibcon#about to read 5, iclass 26, count 0 2006.285.23:29:37.73#ibcon#read 5, iclass 26, count 0 2006.285.23:29:37.73#ibcon#about to read 6, iclass 26, count 0 2006.285.23:29:37.73#ibcon#read 6, iclass 26, count 0 2006.285.23:29:37.73#ibcon#end of sib2, iclass 26, count 0 2006.285.23:29:37.73#ibcon#*mode == 0, iclass 26, count 0 2006.285.23:29:37.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.23:29:37.73#ibcon#[27=USB\r\n] 2006.285.23:29:37.73#ibcon#*before write, iclass 26, count 0 2006.285.23:29:37.73#ibcon#enter sib2, iclass 26, count 0 2006.285.23:29:37.73#ibcon#flushed, iclass 26, count 0 2006.285.23:29:37.73#ibcon#about to write, iclass 26, count 0 2006.285.23:29:37.73#ibcon#wrote, iclass 26, count 0 2006.285.23:29:37.73#ibcon#about to read 3, iclass 26, count 0 2006.285.23:29:37.76#ibcon#read 3, iclass 26, count 0 2006.285.23:29:37.76#ibcon#about to read 4, iclass 26, count 0 2006.285.23:29:37.76#ibcon#read 4, iclass 26, count 0 2006.285.23:29:37.76#ibcon#about to read 5, iclass 26, count 0 2006.285.23:29:37.76#ibcon#read 5, iclass 26, count 0 2006.285.23:29:37.76#ibcon#about to read 6, iclass 26, count 0 2006.285.23:29:37.76#ibcon#read 6, iclass 26, count 0 2006.285.23:29:37.76#ibcon#end of sib2, iclass 26, count 0 2006.285.23:29:37.76#ibcon#*after write, iclass 26, count 0 2006.285.23:29:37.76#ibcon#*before return 0, iclass 26, count 0 2006.285.23:29:37.76#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:29:37.76#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:29:37.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.23:29:37.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.23:29:37.76$vck44/vblo=4,679.99 2006.285.23:29:37.76#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.23:29:37.76#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.23:29:37.76#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:37.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:29:37.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:29:37.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:29:37.76#ibcon#enter wrdev, iclass 28, count 0 2006.285.23:29:37.76#ibcon#first serial, iclass 28, count 0 2006.285.23:29:37.76#ibcon#enter sib2, iclass 28, count 0 2006.285.23:29:37.76#ibcon#flushed, iclass 28, count 0 2006.285.23:29:37.76#ibcon#about to write, iclass 28, count 0 2006.285.23:29:37.76#ibcon#wrote, iclass 28, count 0 2006.285.23:29:37.76#ibcon#about to read 3, iclass 28, count 0 2006.285.23:29:37.78#ibcon#read 3, iclass 28, count 0 2006.285.23:29:37.78#ibcon#about to read 4, iclass 28, count 0 2006.285.23:29:37.78#ibcon#read 4, iclass 28, count 0 2006.285.23:29:37.78#ibcon#about to read 5, iclass 28, count 0 2006.285.23:29:37.78#ibcon#read 5, iclass 28, count 0 2006.285.23:29:37.78#ibcon#about to read 6, iclass 28, count 0 2006.285.23:29:37.78#ibcon#read 6, iclass 28, count 0 2006.285.23:29:37.78#ibcon#end of sib2, iclass 28, count 0 2006.285.23:29:37.78#ibcon#*mode == 0, iclass 28, count 0 2006.285.23:29:37.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.23:29:37.78#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:29:37.78#ibcon#*before write, iclass 28, count 0 2006.285.23:29:37.78#ibcon#enter sib2, iclass 28, count 0 2006.285.23:29:37.78#ibcon#flushed, iclass 28, count 0 2006.285.23:29:37.78#ibcon#about to write, iclass 28, count 0 2006.285.23:29:37.78#ibcon#wrote, iclass 28, count 0 2006.285.23:29:37.78#ibcon#about to read 3, iclass 28, count 0 2006.285.23:29:37.82#ibcon#read 3, iclass 28, count 0 2006.285.23:29:37.82#ibcon#about to read 4, iclass 28, count 0 2006.285.23:29:37.82#ibcon#read 4, iclass 28, count 0 2006.285.23:29:37.82#ibcon#about to read 5, iclass 28, count 0 2006.285.23:29:37.82#ibcon#read 5, iclass 28, count 0 2006.285.23:29:37.82#ibcon#about to read 6, iclass 28, count 0 2006.285.23:29:37.82#ibcon#read 6, iclass 28, count 0 2006.285.23:29:37.82#ibcon#end of sib2, iclass 28, count 0 2006.285.23:29:37.82#ibcon#*after write, iclass 28, count 0 2006.285.23:29:37.82#ibcon#*before return 0, iclass 28, count 0 2006.285.23:29:37.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:29:37.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:29:37.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.23:29:37.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.23:29:37.82$vck44/vb=4,5 2006.285.23:29:37.82#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.23:29:37.82#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.23:29:37.82#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:37.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:29:37.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:29:37.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:29:37.88#ibcon#enter wrdev, iclass 30, count 2 2006.285.23:29:37.88#ibcon#first serial, iclass 30, count 2 2006.285.23:29:37.88#ibcon#enter sib2, iclass 30, count 2 2006.285.23:29:37.88#ibcon#flushed, iclass 30, count 2 2006.285.23:29:37.88#ibcon#about to write, iclass 30, count 2 2006.285.23:29:37.88#ibcon#wrote, iclass 30, count 2 2006.285.23:29:37.88#ibcon#about to read 3, iclass 30, count 2 2006.285.23:29:37.90#ibcon#read 3, iclass 30, count 2 2006.285.23:29:37.90#ibcon#about to read 4, iclass 30, count 2 2006.285.23:29:37.90#ibcon#read 4, iclass 30, count 2 2006.285.23:29:37.90#ibcon#about to read 5, iclass 30, count 2 2006.285.23:29:37.90#ibcon#read 5, iclass 30, count 2 2006.285.23:29:37.90#ibcon#about to read 6, iclass 30, count 2 2006.285.23:29:37.90#ibcon#read 6, iclass 30, count 2 2006.285.23:29:37.90#ibcon#end of sib2, iclass 30, count 2 2006.285.23:29:37.90#ibcon#*mode == 0, iclass 30, count 2 2006.285.23:29:37.90#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.23:29:37.90#ibcon#[27=AT04-05\r\n] 2006.285.23:29:37.90#ibcon#*before write, iclass 30, count 2 2006.285.23:29:37.90#ibcon#enter sib2, iclass 30, count 2 2006.285.23:29:37.90#ibcon#flushed, iclass 30, count 2 2006.285.23:29:37.90#ibcon#about to write, iclass 30, count 2 2006.285.23:29:37.90#ibcon#wrote, iclass 30, count 2 2006.285.23:29:37.90#ibcon#about to read 3, iclass 30, count 2 2006.285.23:29:37.93#ibcon#read 3, iclass 30, count 2 2006.285.23:29:37.93#ibcon#about to read 4, iclass 30, count 2 2006.285.23:29:37.93#ibcon#read 4, iclass 30, count 2 2006.285.23:29:37.93#ibcon#about to read 5, iclass 30, count 2 2006.285.23:29:37.93#ibcon#read 5, iclass 30, count 2 2006.285.23:29:37.93#ibcon#about to read 6, iclass 30, count 2 2006.285.23:29:37.93#ibcon#read 6, iclass 30, count 2 2006.285.23:29:37.93#ibcon#end of sib2, iclass 30, count 2 2006.285.23:29:37.93#ibcon#*after write, iclass 30, count 2 2006.285.23:29:37.93#ibcon#*before return 0, iclass 30, count 2 2006.285.23:29:37.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:29:37.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:29:37.93#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.23:29:37.93#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:37.93#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:29:38.05#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:29:38.05#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:29:38.05#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:29:38.05#ibcon#first serial, iclass 30, count 0 2006.285.23:29:38.05#ibcon#enter sib2, iclass 30, count 0 2006.285.23:29:38.05#ibcon#flushed, iclass 30, count 0 2006.285.23:29:38.05#ibcon#about to write, iclass 30, count 0 2006.285.23:29:38.05#ibcon#wrote, iclass 30, count 0 2006.285.23:29:38.05#ibcon#about to read 3, iclass 30, count 0 2006.285.23:29:38.07#ibcon#read 3, iclass 30, count 0 2006.285.23:29:38.07#ibcon#about to read 4, iclass 30, count 0 2006.285.23:29:38.07#ibcon#read 4, iclass 30, count 0 2006.285.23:29:38.07#ibcon#about to read 5, iclass 30, count 0 2006.285.23:29:38.07#ibcon#read 5, iclass 30, count 0 2006.285.23:29:38.07#ibcon#about to read 6, iclass 30, count 0 2006.285.23:29:38.07#ibcon#read 6, iclass 30, count 0 2006.285.23:29:38.07#ibcon#end of sib2, iclass 30, count 0 2006.285.23:29:38.07#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:29:38.07#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:29:38.07#ibcon#[27=USB\r\n] 2006.285.23:29:38.07#ibcon#*before write, iclass 30, count 0 2006.285.23:29:38.07#ibcon#enter sib2, iclass 30, count 0 2006.285.23:29:38.07#ibcon#flushed, iclass 30, count 0 2006.285.23:29:38.07#ibcon#about to write, iclass 30, count 0 2006.285.23:29:38.07#ibcon#wrote, iclass 30, count 0 2006.285.23:29:38.07#ibcon#about to read 3, iclass 30, count 0 2006.285.23:29:38.10#ibcon#read 3, iclass 30, count 0 2006.285.23:29:38.10#ibcon#about to read 4, iclass 30, count 0 2006.285.23:29:38.10#ibcon#read 4, iclass 30, count 0 2006.285.23:29:38.10#ibcon#about to read 5, iclass 30, count 0 2006.285.23:29:38.10#ibcon#read 5, iclass 30, count 0 2006.285.23:29:38.10#ibcon#about to read 6, iclass 30, count 0 2006.285.23:29:38.10#ibcon#read 6, iclass 30, count 0 2006.285.23:29:38.10#ibcon#end of sib2, iclass 30, count 0 2006.285.23:29:38.10#ibcon#*after write, iclass 30, count 0 2006.285.23:29:38.10#ibcon#*before return 0, iclass 30, count 0 2006.285.23:29:38.10#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:29:38.10#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:29:38.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:29:38.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:29:38.10$vck44/vblo=5,709.99 2006.285.23:29:38.10#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.23:29:38.10#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.23:29:38.10#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:38.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:29:38.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:29:38.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:29:38.10#ibcon#enter wrdev, iclass 32, count 0 2006.285.23:29:38.10#ibcon#first serial, iclass 32, count 0 2006.285.23:29:38.10#ibcon#enter sib2, iclass 32, count 0 2006.285.23:29:38.10#ibcon#flushed, iclass 32, count 0 2006.285.23:29:38.10#ibcon#about to write, iclass 32, count 0 2006.285.23:29:38.10#ibcon#wrote, iclass 32, count 0 2006.285.23:29:38.10#ibcon#about to read 3, iclass 32, count 0 2006.285.23:29:38.12#ibcon#read 3, iclass 32, count 0 2006.285.23:29:38.12#ibcon#about to read 4, iclass 32, count 0 2006.285.23:29:38.12#ibcon#read 4, iclass 32, count 0 2006.285.23:29:38.12#ibcon#about to read 5, iclass 32, count 0 2006.285.23:29:38.12#ibcon#read 5, iclass 32, count 0 2006.285.23:29:38.12#ibcon#about to read 6, iclass 32, count 0 2006.285.23:29:38.12#ibcon#read 6, iclass 32, count 0 2006.285.23:29:38.12#ibcon#end of sib2, iclass 32, count 0 2006.285.23:29:38.12#ibcon#*mode == 0, iclass 32, count 0 2006.285.23:29:38.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.23:29:38.12#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:29:38.12#ibcon#*before write, iclass 32, count 0 2006.285.23:29:38.12#ibcon#enter sib2, iclass 32, count 0 2006.285.23:29:38.12#ibcon#flushed, iclass 32, count 0 2006.285.23:29:38.12#ibcon#about to write, iclass 32, count 0 2006.285.23:29:38.12#ibcon#wrote, iclass 32, count 0 2006.285.23:29:38.12#ibcon#about to read 3, iclass 32, count 0 2006.285.23:29:38.16#ibcon#read 3, iclass 32, count 0 2006.285.23:29:38.16#ibcon#about to read 4, iclass 32, count 0 2006.285.23:29:38.16#ibcon#read 4, iclass 32, count 0 2006.285.23:29:38.16#ibcon#about to read 5, iclass 32, count 0 2006.285.23:29:38.16#ibcon#read 5, iclass 32, count 0 2006.285.23:29:38.16#ibcon#about to read 6, iclass 32, count 0 2006.285.23:29:38.16#ibcon#read 6, iclass 32, count 0 2006.285.23:29:38.16#ibcon#end of sib2, iclass 32, count 0 2006.285.23:29:38.16#ibcon#*after write, iclass 32, count 0 2006.285.23:29:38.16#ibcon#*before return 0, iclass 32, count 0 2006.285.23:29:38.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:29:38.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:29:38.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.23:29:38.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.23:29:38.16$vck44/vb=5,4 2006.285.23:29:38.16#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.23:29:38.16#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.23:29:38.16#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:38.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:29:38.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:29:38.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:29:38.22#ibcon#enter wrdev, iclass 34, count 2 2006.285.23:29:38.22#ibcon#first serial, iclass 34, count 2 2006.285.23:29:38.22#ibcon#enter sib2, iclass 34, count 2 2006.285.23:29:38.22#ibcon#flushed, iclass 34, count 2 2006.285.23:29:38.22#ibcon#about to write, iclass 34, count 2 2006.285.23:29:38.22#ibcon#wrote, iclass 34, count 2 2006.285.23:29:38.22#ibcon#about to read 3, iclass 34, count 2 2006.285.23:29:38.24#ibcon#read 3, iclass 34, count 2 2006.285.23:29:38.24#ibcon#about to read 4, iclass 34, count 2 2006.285.23:29:38.24#ibcon#read 4, iclass 34, count 2 2006.285.23:29:38.24#ibcon#about to read 5, iclass 34, count 2 2006.285.23:29:38.24#ibcon#read 5, iclass 34, count 2 2006.285.23:29:38.24#ibcon#about to read 6, iclass 34, count 2 2006.285.23:29:38.24#ibcon#read 6, iclass 34, count 2 2006.285.23:29:38.24#ibcon#end of sib2, iclass 34, count 2 2006.285.23:29:38.24#ibcon#*mode == 0, iclass 34, count 2 2006.285.23:29:38.24#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.23:29:38.24#ibcon#[27=AT05-04\r\n] 2006.285.23:29:38.24#ibcon#*before write, iclass 34, count 2 2006.285.23:29:38.24#ibcon#enter sib2, iclass 34, count 2 2006.285.23:29:38.24#ibcon#flushed, iclass 34, count 2 2006.285.23:29:38.24#ibcon#about to write, iclass 34, count 2 2006.285.23:29:38.24#ibcon#wrote, iclass 34, count 2 2006.285.23:29:38.24#ibcon#about to read 3, iclass 34, count 2 2006.285.23:29:38.27#ibcon#read 3, iclass 34, count 2 2006.285.23:29:38.27#ibcon#about to read 4, iclass 34, count 2 2006.285.23:29:38.27#ibcon#read 4, iclass 34, count 2 2006.285.23:29:38.27#ibcon#about to read 5, iclass 34, count 2 2006.285.23:29:38.27#ibcon#read 5, iclass 34, count 2 2006.285.23:29:38.27#ibcon#about to read 6, iclass 34, count 2 2006.285.23:29:38.27#ibcon#read 6, iclass 34, count 2 2006.285.23:29:38.27#ibcon#end of sib2, iclass 34, count 2 2006.285.23:29:38.27#ibcon#*after write, iclass 34, count 2 2006.285.23:29:38.27#ibcon#*before return 0, iclass 34, count 2 2006.285.23:29:38.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:29:38.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:29:38.27#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.23:29:38.27#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:38.27#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:29:38.39#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:29:38.39#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:29:38.39#ibcon#enter wrdev, iclass 34, count 0 2006.285.23:29:38.39#ibcon#first serial, iclass 34, count 0 2006.285.23:29:38.39#ibcon#enter sib2, iclass 34, count 0 2006.285.23:29:38.39#ibcon#flushed, iclass 34, count 0 2006.285.23:29:38.39#ibcon#about to write, iclass 34, count 0 2006.285.23:29:38.39#ibcon#wrote, iclass 34, count 0 2006.285.23:29:38.39#ibcon#about to read 3, iclass 34, count 0 2006.285.23:29:38.41#ibcon#read 3, iclass 34, count 0 2006.285.23:29:38.41#ibcon#about to read 4, iclass 34, count 0 2006.285.23:29:38.41#ibcon#read 4, iclass 34, count 0 2006.285.23:29:38.41#ibcon#about to read 5, iclass 34, count 0 2006.285.23:29:38.41#ibcon#read 5, iclass 34, count 0 2006.285.23:29:38.41#ibcon#about to read 6, iclass 34, count 0 2006.285.23:29:38.41#ibcon#read 6, iclass 34, count 0 2006.285.23:29:38.41#ibcon#end of sib2, iclass 34, count 0 2006.285.23:29:38.41#ibcon#*mode == 0, iclass 34, count 0 2006.285.23:29:38.41#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.23:29:38.41#ibcon#[27=USB\r\n] 2006.285.23:29:38.41#ibcon#*before write, iclass 34, count 0 2006.285.23:29:38.41#ibcon#enter sib2, iclass 34, count 0 2006.285.23:29:38.41#ibcon#flushed, iclass 34, count 0 2006.285.23:29:38.41#ibcon#about to write, iclass 34, count 0 2006.285.23:29:38.41#ibcon#wrote, iclass 34, count 0 2006.285.23:29:38.41#ibcon#about to read 3, iclass 34, count 0 2006.285.23:29:38.44#ibcon#read 3, iclass 34, count 0 2006.285.23:29:38.44#ibcon#about to read 4, iclass 34, count 0 2006.285.23:29:38.44#ibcon#read 4, iclass 34, count 0 2006.285.23:29:38.44#ibcon#about to read 5, iclass 34, count 0 2006.285.23:29:38.44#ibcon#read 5, iclass 34, count 0 2006.285.23:29:38.44#ibcon#about to read 6, iclass 34, count 0 2006.285.23:29:38.44#ibcon#read 6, iclass 34, count 0 2006.285.23:29:38.44#ibcon#end of sib2, iclass 34, count 0 2006.285.23:29:38.44#ibcon#*after write, iclass 34, count 0 2006.285.23:29:38.44#ibcon#*before return 0, iclass 34, count 0 2006.285.23:29:38.44#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:29:38.44#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:29:38.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.23:29:38.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.23:29:38.44$vck44/vblo=6,719.99 2006.285.23:29:38.44#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.23:29:38.44#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.23:29:38.44#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:38.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:29:38.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:29:38.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:29:38.44#ibcon#enter wrdev, iclass 36, count 0 2006.285.23:29:38.44#ibcon#first serial, iclass 36, count 0 2006.285.23:29:38.44#ibcon#enter sib2, iclass 36, count 0 2006.285.23:29:38.44#ibcon#flushed, iclass 36, count 0 2006.285.23:29:38.44#ibcon#about to write, iclass 36, count 0 2006.285.23:29:38.44#ibcon#wrote, iclass 36, count 0 2006.285.23:29:38.44#ibcon#about to read 3, iclass 36, count 0 2006.285.23:29:38.46#ibcon#read 3, iclass 36, count 0 2006.285.23:29:38.46#ibcon#about to read 4, iclass 36, count 0 2006.285.23:29:38.46#ibcon#read 4, iclass 36, count 0 2006.285.23:29:38.46#ibcon#about to read 5, iclass 36, count 0 2006.285.23:29:38.46#ibcon#read 5, iclass 36, count 0 2006.285.23:29:38.46#ibcon#about to read 6, iclass 36, count 0 2006.285.23:29:38.46#ibcon#read 6, iclass 36, count 0 2006.285.23:29:38.46#ibcon#end of sib2, iclass 36, count 0 2006.285.23:29:38.46#ibcon#*mode == 0, iclass 36, count 0 2006.285.23:29:38.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.23:29:38.46#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:29:38.46#ibcon#*before write, iclass 36, count 0 2006.285.23:29:38.46#ibcon#enter sib2, iclass 36, count 0 2006.285.23:29:38.46#ibcon#flushed, iclass 36, count 0 2006.285.23:29:38.46#ibcon#about to write, iclass 36, count 0 2006.285.23:29:38.46#ibcon#wrote, iclass 36, count 0 2006.285.23:29:38.46#ibcon#about to read 3, iclass 36, count 0 2006.285.23:29:38.50#ibcon#read 3, iclass 36, count 0 2006.285.23:29:38.50#ibcon#about to read 4, iclass 36, count 0 2006.285.23:29:38.50#ibcon#read 4, iclass 36, count 0 2006.285.23:29:38.50#ibcon#about to read 5, iclass 36, count 0 2006.285.23:29:38.50#ibcon#read 5, iclass 36, count 0 2006.285.23:29:38.50#ibcon#about to read 6, iclass 36, count 0 2006.285.23:29:38.50#ibcon#read 6, iclass 36, count 0 2006.285.23:29:38.50#ibcon#end of sib2, iclass 36, count 0 2006.285.23:29:38.50#ibcon#*after write, iclass 36, count 0 2006.285.23:29:38.50#ibcon#*before return 0, iclass 36, count 0 2006.285.23:29:38.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:29:38.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:29:38.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.23:29:38.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.23:29:38.50$vck44/vb=6,3 2006.285.23:29:38.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.23:29:38.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.23:29:38.50#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:38.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:29:38.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:29:38.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:29:38.56#ibcon#enter wrdev, iclass 38, count 2 2006.285.23:29:38.56#ibcon#first serial, iclass 38, count 2 2006.285.23:29:38.56#ibcon#enter sib2, iclass 38, count 2 2006.285.23:29:38.56#ibcon#flushed, iclass 38, count 2 2006.285.23:29:38.56#ibcon#about to write, iclass 38, count 2 2006.285.23:29:38.56#ibcon#wrote, iclass 38, count 2 2006.285.23:29:38.56#ibcon#about to read 3, iclass 38, count 2 2006.285.23:29:38.58#ibcon#read 3, iclass 38, count 2 2006.285.23:29:38.58#ibcon#about to read 4, iclass 38, count 2 2006.285.23:29:38.58#ibcon#read 4, iclass 38, count 2 2006.285.23:29:38.58#ibcon#about to read 5, iclass 38, count 2 2006.285.23:29:38.58#ibcon#read 5, iclass 38, count 2 2006.285.23:29:38.58#ibcon#about to read 6, iclass 38, count 2 2006.285.23:29:38.58#ibcon#read 6, iclass 38, count 2 2006.285.23:29:38.58#ibcon#end of sib2, iclass 38, count 2 2006.285.23:29:38.58#ibcon#*mode == 0, iclass 38, count 2 2006.285.23:29:38.58#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.23:29:38.58#ibcon#[27=AT06-03\r\n] 2006.285.23:29:38.58#ibcon#*before write, iclass 38, count 2 2006.285.23:29:38.58#ibcon#enter sib2, iclass 38, count 2 2006.285.23:29:38.58#ibcon#flushed, iclass 38, count 2 2006.285.23:29:38.58#ibcon#about to write, iclass 38, count 2 2006.285.23:29:38.58#ibcon#wrote, iclass 38, count 2 2006.285.23:29:38.58#ibcon#about to read 3, iclass 38, count 2 2006.285.23:29:38.61#ibcon#read 3, iclass 38, count 2 2006.285.23:29:38.61#ibcon#about to read 4, iclass 38, count 2 2006.285.23:29:38.61#ibcon#read 4, iclass 38, count 2 2006.285.23:29:38.61#ibcon#about to read 5, iclass 38, count 2 2006.285.23:29:38.61#ibcon#read 5, iclass 38, count 2 2006.285.23:29:38.61#ibcon#about to read 6, iclass 38, count 2 2006.285.23:29:38.61#ibcon#read 6, iclass 38, count 2 2006.285.23:29:38.61#ibcon#end of sib2, iclass 38, count 2 2006.285.23:29:38.61#ibcon#*after write, iclass 38, count 2 2006.285.23:29:38.61#ibcon#*before return 0, iclass 38, count 2 2006.285.23:29:38.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:29:38.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:29:38.61#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.23:29:38.61#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:38.61#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:29:38.73#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:29:38.73#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:29:38.73#ibcon#enter wrdev, iclass 38, count 0 2006.285.23:29:38.73#ibcon#first serial, iclass 38, count 0 2006.285.23:29:38.73#ibcon#enter sib2, iclass 38, count 0 2006.285.23:29:38.73#ibcon#flushed, iclass 38, count 0 2006.285.23:29:38.73#ibcon#about to write, iclass 38, count 0 2006.285.23:29:38.73#ibcon#wrote, iclass 38, count 0 2006.285.23:29:38.73#ibcon#about to read 3, iclass 38, count 0 2006.285.23:29:38.75#ibcon#read 3, iclass 38, count 0 2006.285.23:29:38.75#ibcon#about to read 4, iclass 38, count 0 2006.285.23:29:38.75#ibcon#read 4, iclass 38, count 0 2006.285.23:29:38.75#ibcon#about to read 5, iclass 38, count 0 2006.285.23:29:38.75#ibcon#read 5, iclass 38, count 0 2006.285.23:29:38.75#ibcon#about to read 6, iclass 38, count 0 2006.285.23:29:38.75#ibcon#read 6, iclass 38, count 0 2006.285.23:29:38.75#ibcon#end of sib2, iclass 38, count 0 2006.285.23:29:38.75#ibcon#*mode == 0, iclass 38, count 0 2006.285.23:29:38.75#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.23:29:38.75#ibcon#[27=USB\r\n] 2006.285.23:29:38.75#ibcon#*before write, iclass 38, count 0 2006.285.23:29:38.75#ibcon#enter sib2, iclass 38, count 0 2006.285.23:29:38.75#ibcon#flushed, iclass 38, count 0 2006.285.23:29:38.75#ibcon#about to write, iclass 38, count 0 2006.285.23:29:38.75#ibcon#wrote, iclass 38, count 0 2006.285.23:29:38.75#ibcon#about to read 3, iclass 38, count 0 2006.285.23:29:38.78#ibcon#read 3, iclass 38, count 0 2006.285.23:29:38.78#ibcon#about to read 4, iclass 38, count 0 2006.285.23:29:38.78#ibcon#read 4, iclass 38, count 0 2006.285.23:29:38.78#ibcon#about to read 5, iclass 38, count 0 2006.285.23:29:38.78#ibcon#read 5, iclass 38, count 0 2006.285.23:29:38.78#ibcon#about to read 6, iclass 38, count 0 2006.285.23:29:38.78#ibcon#read 6, iclass 38, count 0 2006.285.23:29:38.78#ibcon#end of sib2, iclass 38, count 0 2006.285.23:29:38.78#ibcon#*after write, iclass 38, count 0 2006.285.23:29:38.78#ibcon#*before return 0, iclass 38, count 0 2006.285.23:29:38.78#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:29:38.78#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:29:38.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.23:29:38.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.23:29:38.78$vck44/vblo=7,734.99 2006.285.23:29:38.78#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.23:29:38.78#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.23:29:38.78#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:38.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:29:38.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:29:38.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:29:38.78#ibcon#enter wrdev, iclass 40, count 0 2006.285.23:29:38.78#ibcon#first serial, iclass 40, count 0 2006.285.23:29:38.78#ibcon#enter sib2, iclass 40, count 0 2006.285.23:29:38.78#ibcon#flushed, iclass 40, count 0 2006.285.23:29:38.78#ibcon#about to write, iclass 40, count 0 2006.285.23:29:38.78#ibcon#wrote, iclass 40, count 0 2006.285.23:29:38.78#ibcon#about to read 3, iclass 40, count 0 2006.285.23:29:38.80#ibcon#read 3, iclass 40, count 0 2006.285.23:29:38.80#ibcon#about to read 4, iclass 40, count 0 2006.285.23:29:38.80#ibcon#read 4, iclass 40, count 0 2006.285.23:29:38.80#ibcon#about to read 5, iclass 40, count 0 2006.285.23:29:38.80#ibcon#read 5, iclass 40, count 0 2006.285.23:29:38.80#ibcon#about to read 6, iclass 40, count 0 2006.285.23:29:38.80#ibcon#read 6, iclass 40, count 0 2006.285.23:29:38.80#ibcon#end of sib2, iclass 40, count 0 2006.285.23:29:38.80#ibcon#*mode == 0, iclass 40, count 0 2006.285.23:29:38.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.23:29:38.80#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:29:38.80#ibcon#*before write, iclass 40, count 0 2006.285.23:29:38.80#ibcon#enter sib2, iclass 40, count 0 2006.285.23:29:38.80#ibcon#flushed, iclass 40, count 0 2006.285.23:29:38.80#ibcon#about to write, iclass 40, count 0 2006.285.23:29:38.80#ibcon#wrote, iclass 40, count 0 2006.285.23:29:38.80#ibcon#about to read 3, iclass 40, count 0 2006.285.23:29:38.84#ibcon#read 3, iclass 40, count 0 2006.285.23:29:38.84#ibcon#about to read 4, iclass 40, count 0 2006.285.23:29:38.84#ibcon#read 4, iclass 40, count 0 2006.285.23:29:38.84#ibcon#about to read 5, iclass 40, count 0 2006.285.23:29:38.84#ibcon#read 5, iclass 40, count 0 2006.285.23:29:38.84#ibcon#about to read 6, iclass 40, count 0 2006.285.23:29:38.84#ibcon#read 6, iclass 40, count 0 2006.285.23:29:38.84#ibcon#end of sib2, iclass 40, count 0 2006.285.23:29:38.84#ibcon#*after write, iclass 40, count 0 2006.285.23:29:38.84#ibcon#*before return 0, iclass 40, count 0 2006.285.23:29:38.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:29:38.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:29:38.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.23:29:38.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.23:29:38.84$vck44/vb=7,4 2006.285.23:29:38.84#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.23:29:38.84#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.23:29:38.84#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:38.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:29:38.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:29:38.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:29:38.90#ibcon#enter wrdev, iclass 4, count 2 2006.285.23:29:38.90#ibcon#first serial, iclass 4, count 2 2006.285.23:29:38.90#ibcon#enter sib2, iclass 4, count 2 2006.285.23:29:38.90#ibcon#flushed, iclass 4, count 2 2006.285.23:29:38.90#ibcon#about to write, iclass 4, count 2 2006.285.23:29:38.90#ibcon#wrote, iclass 4, count 2 2006.285.23:29:38.90#ibcon#about to read 3, iclass 4, count 2 2006.285.23:29:38.92#ibcon#read 3, iclass 4, count 2 2006.285.23:29:38.92#ibcon#about to read 4, iclass 4, count 2 2006.285.23:29:38.92#ibcon#read 4, iclass 4, count 2 2006.285.23:29:38.92#ibcon#about to read 5, iclass 4, count 2 2006.285.23:29:38.92#ibcon#read 5, iclass 4, count 2 2006.285.23:29:38.92#ibcon#about to read 6, iclass 4, count 2 2006.285.23:29:38.92#ibcon#read 6, iclass 4, count 2 2006.285.23:29:38.92#ibcon#end of sib2, iclass 4, count 2 2006.285.23:29:38.92#ibcon#*mode == 0, iclass 4, count 2 2006.285.23:29:38.92#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.23:29:38.92#ibcon#[27=AT07-04\r\n] 2006.285.23:29:38.92#ibcon#*before write, iclass 4, count 2 2006.285.23:29:38.92#ibcon#enter sib2, iclass 4, count 2 2006.285.23:29:38.92#ibcon#flushed, iclass 4, count 2 2006.285.23:29:38.92#ibcon#about to write, iclass 4, count 2 2006.285.23:29:38.92#ibcon#wrote, iclass 4, count 2 2006.285.23:29:38.92#ibcon#about to read 3, iclass 4, count 2 2006.285.23:29:38.95#ibcon#read 3, iclass 4, count 2 2006.285.23:29:38.95#ibcon#about to read 4, iclass 4, count 2 2006.285.23:29:38.95#ibcon#read 4, iclass 4, count 2 2006.285.23:29:38.95#ibcon#about to read 5, iclass 4, count 2 2006.285.23:29:38.95#ibcon#read 5, iclass 4, count 2 2006.285.23:29:38.95#ibcon#about to read 6, iclass 4, count 2 2006.285.23:29:38.95#ibcon#read 6, iclass 4, count 2 2006.285.23:29:38.95#ibcon#end of sib2, iclass 4, count 2 2006.285.23:29:38.95#ibcon#*after write, iclass 4, count 2 2006.285.23:29:38.95#ibcon#*before return 0, iclass 4, count 2 2006.285.23:29:38.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:29:38.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:29:38.95#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.23:29:38.95#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:38.95#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:29:39.07#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:29:39.07#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:29:39.07#ibcon#enter wrdev, iclass 4, count 0 2006.285.23:29:39.07#ibcon#first serial, iclass 4, count 0 2006.285.23:29:39.07#ibcon#enter sib2, iclass 4, count 0 2006.285.23:29:39.07#ibcon#flushed, iclass 4, count 0 2006.285.23:29:39.07#ibcon#about to write, iclass 4, count 0 2006.285.23:29:39.07#ibcon#wrote, iclass 4, count 0 2006.285.23:29:39.07#ibcon#about to read 3, iclass 4, count 0 2006.285.23:29:39.09#ibcon#read 3, iclass 4, count 0 2006.285.23:29:39.09#ibcon#about to read 4, iclass 4, count 0 2006.285.23:29:39.09#ibcon#read 4, iclass 4, count 0 2006.285.23:29:39.09#ibcon#about to read 5, iclass 4, count 0 2006.285.23:29:39.09#ibcon#read 5, iclass 4, count 0 2006.285.23:29:39.09#ibcon#about to read 6, iclass 4, count 0 2006.285.23:29:39.09#ibcon#read 6, iclass 4, count 0 2006.285.23:29:39.09#ibcon#end of sib2, iclass 4, count 0 2006.285.23:29:39.09#ibcon#*mode == 0, iclass 4, count 0 2006.285.23:29:39.09#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.23:29:39.09#ibcon#[27=USB\r\n] 2006.285.23:29:39.09#ibcon#*before write, iclass 4, count 0 2006.285.23:29:39.09#ibcon#enter sib2, iclass 4, count 0 2006.285.23:29:39.09#ibcon#flushed, iclass 4, count 0 2006.285.23:29:39.09#ibcon#about to write, iclass 4, count 0 2006.285.23:29:39.09#ibcon#wrote, iclass 4, count 0 2006.285.23:29:39.09#ibcon#about to read 3, iclass 4, count 0 2006.285.23:29:39.12#ibcon#read 3, iclass 4, count 0 2006.285.23:29:39.12#ibcon#about to read 4, iclass 4, count 0 2006.285.23:29:39.12#ibcon#read 4, iclass 4, count 0 2006.285.23:29:39.12#ibcon#about to read 5, iclass 4, count 0 2006.285.23:29:39.12#ibcon#read 5, iclass 4, count 0 2006.285.23:29:39.12#ibcon#about to read 6, iclass 4, count 0 2006.285.23:29:39.12#ibcon#read 6, iclass 4, count 0 2006.285.23:29:39.12#ibcon#end of sib2, iclass 4, count 0 2006.285.23:29:39.12#ibcon#*after write, iclass 4, count 0 2006.285.23:29:39.12#ibcon#*before return 0, iclass 4, count 0 2006.285.23:29:39.12#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:29:39.12#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:29:39.12#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.23:29:39.12#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.23:29:39.12$vck44/vblo=8,744.99 2006.285.23:29:39.12#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.23:29:39.12#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.23:29:39.12#ibcon#ireg 17 cls_cnt 0 2006.285.23:29:39.12#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:29:39.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:29:39.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:29:39.12#ibcon#enter wrdev, iclass 6, count 0 2006.285.23:29:39.12#ibcon#first serial, iclass 6, count 0 2006.285.23:29:39.12#ibcon#enter sib2, iclass 6, count 0 2006.285.23:29:39.12#ibcon#flushed, iclass 6, count 0 2006.285.23:29:39.12#ibcon#about to write, iclass 6, count 0 2006.285.23:29:39.12#ibcon#wrote, iclass 6, count 0 2006.285.23:29:39.12#ibcon#about to read 3, iclass 6, count 0 2006.285.23:29:39.14#ibcon#read 3, iclass 6, count 0 2006.285.23:29:39.14#ibcon#about to read 4, iclass 6, count 0 2006.285.23:29:39.14#ibcon#read 4, iclass 6, count 0 2006.285.23:29:39.14#ibcon#about to read 5, iclass 6, count 0 2006.285.23:29:39.14#ibcon#read 5, iclass 6, count 0 2006.285.23:29:39.14#ibcon#about to read 6, iclass 6, count 0 2006.285.23:29:39.14#ibcon#read 6, iclass 6, count 0 2006.285.23:29:39.14#ibcon#end of sib2, iclass 6, count 0 2006.285.23:29:39.14#ibcon#*mode == 0, iclass 6, count 0 2006.285.23:29:39.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.23:29:39.14#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:29:39.14#ibcon#*before write, iclass 6, count 0 2006.285.23:29:39.14#ibcon#enter sib2, iclass 6, count 0 2006.285.23:29:39.14#ibcon#flushed, iclass 6, count 0 2006.285.23:29:39.14#ibcon#about to write, iclass 6, count 0 2006.285.23:29:39.14#ibcon#wrote, iclass 6, count 0 2006.285.23:29:39.14#ibcon#about to read 3, iclass 6, count 0 2006.285.23:29:39.18#ibcon#read 3, iclass 6, count 0 2006.285.23:29:39.18#ibcon#about to read 4, iclass 6, count 0 2006.285.23:29:39.18#ibcon#read 4, iclass 6, count 0 2006.285.23:29:39.18#ibcon#about to read 5, iclass 6, count 0 2006.285.23:29:39.18#ibcon#read 5, iclass 6, count 0 2006.285.23:29:39.18#ibcon#about to read 6, iclass 6, count 0 2006.285.23:29:39.18#ibcon#read 6, iclass 6, count 0 2006.285.23:29:39.18#ibcon#end of sib2, iclass 6, count 0 2006.285.23:29:39.18#ibcon#*after write, iclass 6, count 0 2006.285.23:29:39.18#ibcon#*before return 0, iclass 6, count 0 2006.285.23:29:39.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:29:39.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:29:39.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.23:29:39.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.23:29:39.18$vck44/vb=8,4 2006.285.23:29:39.18#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.23:29:39.18#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.23:29:39.18#ibcon#ireg 11 cls_cnt 2 2006.285.23:29:39.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:29:39.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:29:39.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:29:39.24#ibcon#enter wrdev, iclass 10, count 2 2006.285.23:29:39.24#ibcon#first serial, iclass 10, count 2 2006.285.23:29:39.24#ibcon#enter sib2, iclass 10, count 2 2006.285.23:29:39.24#ibcon#flushed, iclass 10, count 2 2006.285.23:29:39.24#ibcon#about to write, iclass 10, count 2 2006.285.23:29:39.24#ibcon#wrote, iclass 10, count 2 2006.285.23:29:39.24#ibcon#about to read 3, iclass 10, count 2 2006.285.23:29:39.26#ibcon#read 3, iclass 10, count 2 2006.285.23:29:39.26#ibcon#about to read 4, iclass 10, count 2 2006.285.23:29:39.26#ibcon#read 4, iclass 10, count 2 2006.285.23:29:39.26#ibcon#about to read 5, iclass 10, count 2 2006.285.23:29:39.26#ibcon#read 5, iclass 10, count 2 2006.285.23:29:39.26#ibcon#about to read 6, iclass 10, count 2 2006.285.23:29:39.26#ibcon#read 6, iclass 10, count 2 2006.285.23:29:39.26#ibcon#end of sib2, iclass 10, count 2 2006.285.23:29:39.26#ibcon#*mode == 0, iclass 10, count 2 2006.285.23:29:39.26#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.23:29:39.26#ibcon#[27=AT08-04\r\n] 2006.285.23:29:39.26#ibcon#*before write, iclass 10, count 2 2006.285.23:29:39.26#ibcon#enter sib2, iclass 10, count 2 2006.285.23:29:39.26#ibcon#flushed, iclass 10, count 2 2006.285.23:29:39.26#ibcon#about to write, iclass 10, count 2 2006.285.23:29:39.26#ibcon#wrote, iclass 10, count 2 2006.285.23:29:39.26#ibcon#about to read 3, iclass 10, count 2 2006.285.23:29:39.29#ibcon#read 3, iclass 10, count 2 2006.285.23:29:39.29#ibcon#about to read 4, iclass 10, count 2 2006.285.23:29:39.29#ibcon#read 4, iclass 10, count 2 2006.285.23:29:39.29#ibcon#about to read 5, iclass 10, count 2 2006.285.23:29:39.29#ibcon#read 5, iclass 10, count 2 2006.285.23:29:39.29#ibcon#about to read 6, iclass 10, count 2 2006.285.23:29:39.29#ibcon#read 6, iclass 10, count 2 2006.285.23:29:39.29#ibcon#end of sib2, iclass 10, count 2 2006.285.23:29:39.29#ibcon#*after write, iclass 10, count 2 2006.285.23:29:39.29#ibcon#*before return 0, iclass 10, count 2 2006.285.23:29:39.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:29:39.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:29:39.29#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.23:29:39.29#ibcon#ireg 7 cls_cnt 0 2006.285.23:29:39.29#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:29:39.41#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:29:39.41#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:29:39.41#ibcon#enter wrdev, iclass 10, count 0 2006.285.23:29:39.41#ibcon#first serial, iclass 10, count 0 2006.285.23:29:39.41#ibcon#enter sib2, iclass 10, count 0 2006.285.23:29:39.41#ibcon#flushed, iclass 10, count 0 2006.285.23:29:39.41#ibcon#about to write, iclass 10, count 0 2006.285.23:29:39.41#ibcon#wrote, iclass 10, count 0 2006.285.23:29:39.41#ibcon#about to read 3, iclass 10, count 0 2006.285.23:29:39.43#ibcon#read 3, iclass 10, count 0 2006.285.23:29:39.43#ibcon#about to read 4, iclass 10, count 0 2006.285.23:29:39.43#ibcon#read 4, iclass 10, count 0 2006.285.23:29:39.43#ibcon#about to read 5, iclass 10, count 0 2006.285.23:29:39.43#ibcon#read 5, iclass 10, count 0 2006.285.23:29:39.43#ibcon#about to read 6, iclass 10, count 0 2006.285.23:29:39.43#ibcon#read 6, iclass 10, count 0 2006.285.23:29:39.43#ibcon#end of sib2, iclass 10, count 0 2006.285.23:29:39.43#ibcon#*mode == 0, iclass 10, count 0 2006.285.23:29:39.43#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.23:29:39.43#ibcon#[27=USB\r\n] 2006.285.23:29:39.43#ibcon#*before write, iclass 10, count 0 2006.285.23:29:39.43#ibcon#enter sib2, iclass 10, count 0 2006.285.23:29:39.43#ibcon#flushed, iclass 10, count 0 2006.285.23:29:39.43#ibcon#about to write, iclass 10, count 0 2006.285.23:29:39.43#ibcon#wrote, iclass 10, count 0 2006.285.23:29:39.43#ibcon#about to read 3, iclass 10, count 0 2006.285.23:29:39.46#ibcon#read 3, iclass 10, count 0 2006.285.23:29:39.46#ibcon#about to read 4, iclass 10, count 0 2006.285.23:29:39.46#ibcon#read 4, iclass 10, count 0 2006.285.23:29:39.46#ibcon#about to read 5, iclass 10, count 0 2006.285.23:29:39.46#ibcon#read 5, iclass 10, count 0 2006.285.23:29:39.46#ibcon#about to read 6, iclass 10, count 0 2006.285.23:29:39.46#ibcon#read 6, iclass 10, count 0 2006.285.23:29:39.46#ibcon#end of sib2, iclass 10, count 0 2006.285.23:29:39.46#ibcon#*after write, iclass 10, count 0 2006.285.23:29:39.46#ibcon#*before return 0, iclass 10, count 0 2006.285.23:29:39.46#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:29:39.46#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:29:39.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.23:29:39.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.23:29:39.46$vck44/vabw=wide 2006.285.23:29:39.46#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.23:29:39.46#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.23:29:39.46#ibcon#ireg 8 cls_cnt 0 2006.285.23:29:39.46#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:29:39.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:29:39.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:29:39.46#ibcon#enter wrdev, iclass 12, count 0 2006.285.23:29:39.46#ibcon#first serial, iclass 12, count 0 2006.285.23:29:39.46#ibcon#enter sib2, iclass 12, count 0 2006.285.23:29:39.46#ibcon#flushed, iclass 12, count 0 2006.285.23:29:39.46#ibcon#about to write, iclass 12, count 0 2006.285.23:29:39.46#ibcon#wrote, iclass 12, count 0 2006.285.23:29:39.46#ibcon#about to read 3, iclass 12, count 0 2006.285.23:29:39.48#ibcon#read 3, iclass 12, count 0 2006.285.23:29:39.48#ibcon#about to read 4, iclass 12, count 0 2006.285.23:29:39.48#ibcon#read 4, iclass 12, count 0 2006.285.23:29:39.48#ibcon#about to read 5, iclass 12, count 0 2006.285.23:29:39.48#ibcon#read 5, iclass 12, count 0 2006.285.23:29:39.48#ibcon#about to read 6, iclass 12, count 0 2006.285.23:29:39.48#ibcon#read 6, iclass 12, count 0 2006.285.23:29:39.48#ibcon#end of sib2, iclass 12, count 0 2006.285.23:29:39.48#ibcon#*mode == 0, iclass 12, count 0 2006.285.23:29:39.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.23:29:39.48#ibcon#[25=BW32\r\n] 2006.285.23:29:39.48#ibcon#*before write, iclass 12, count 0 2006.285.23:29:39.48#ibcon#enter sib2, iclass 12, count 0 2006.285.23:29:39.48#ibcon#flushed, iclass 12, count 0 2006.285.23:29:39.48#ibcon#about to write, iclass 12, count 0 2006.285.23:29:39.48#ibcon#wrote, iclass 12, count 0 2006.285.23:29:39.48#ibcon#about to read 3, iclass 12, count 0 2006.285.23:29:39.51#ibcon#read 3, iclass 12, count 0 2006.285.23:29:39.51#ibcon#about to read 4, iclass 12, count 0 2006.285.23:29:39.51#ibcon#read 4, iclass 12, count 0 2006.285.23:29:39.51#ibcon#about to read 5, iclass 12, count 0 2006.285.23:29:39.51#ibcon#read 5, iclass 12, count 0 2006.285.23:29:39.51#ibcon#about to read 6, iclass 12, count 0 2006.285.23:29:39.51#ibcon#read 6, iclass 12, count 0 2006.285.23:29:39.51#ibcon#end of sib2, iclass 12, count 0 2006.285.23:29:39.51#ibcon#*after write, iclass 12, count 0 2006.285.23:29:39.51#ibcon#*before return 0, iclass 12, count 0 2006.285.23:29:39.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:29:39.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:29:39.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.23:29:39.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.23:29:39.51$vck44/vbbw=wide 2006.285.23:29:39.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.23:29:39.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.23:29:39.51#ibcon#ireg 8 cls_cnt 0 2006.285.23:29:39.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:29:39.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:29:39.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:29:39.58#ibcon#enter wrdev, iclass 14, count 0 2006.285.23:29:39.58#ibcon#first serial, iclass 14, count 0 2006.285.23:29:39.58#ibcon#enter sib2, iclass 14, count 0 2006.285.23:29:39.58#ibcon#flushed, iclass 14, count 0 2006.285.23:29:39.58#ibcon#about to write, iclass 14, count 0 2006.285.23:29:39.58#ibcon#wrote, iclass 14, count 0 2006.285.23:29:39.58#ibcon#about to read 3, iclass 14, count 0 2006.285.23:29:39.60#ibcon#read 3, iclass 14, count 0 2006.285.23:29:39.60#ibcon#about to read 4, iclass 14, count 0 2006.285.23:29:39.60#ibcon#read 4, iclass 14, count 0 2006.285.23:29:39.60#ibcon#about to read 5, iclass 14, count 0 2006.285.23:29:39.60#ibcon#read 5, iclass 14, count 0 2006.285.23:29:39.60#ibcon#about to read 6, iclass 14, count 0 2006.285.23:29:39.60#ibcon#read 6, iclass 14, count 0 2006.285.23:29:39.60#ibcon#end of sib2, iclass 14, count 0 2006.285.23:29:39.60#ibcon#*mode == 0, iclass 14, count 0 2006.285.23:29:39.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.23:29:39.60#ibcon#[27=BW32\r\n] 2006.285.23:29:39.60#ibcon#*before write, iclass 14, count 0 2006.285.23:29:39.60#ibcon#enter sib2, iclass 14, count 0 2006.285.23:29:39.60#ibcon#flushed, iclass 14, count 0 2006.285.23:29:39.60#ibcon#about to write, iclass 14, count 0 2006.285.23:29:39.60#ibcon#wrote, iclass 14, count 0 2006.285.23:29:39.60#ibcon#about to read 3, iclass 14, count 0 2006.285.23:29:39.63#ibcon#read 3, iclass 14, count 0 2006.285.23:29:39.63#ibcon#about to read 4, iclass 14, count 0 2006.285.23:29:39.63#ibcon#read 4, iclass 14, count 0 2006.285.23:29:39.63#ibcon#about to read 5, iclass 14, count 0 2006.285.23:29:39.63#ibcon#read 5, iclass 14, count 0 2006.285.23:29:39.63#ibcon#about to read 6, iclass 14, count 0 2006.285.23:29:39.63#ibcon#read 6, iclass 14, count 0 2006.285.23:29:39.63#ibcon#end of sib2, iclass 14, count 0 2006.285.23:29:39.63#ibcon#*after write, iclass 14, count 0 2006.285.23:29:39.63#ibcon#*before return 0, iclass 14, count 0 2006.285.23:29:39.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:29:39.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:29:39.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.23:29:39.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.23:29:39.63$setupk4/ifdk4 2006.285.23:29:39.63$ifdk4/lo= 2006.285.23:29:39.63$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:29:39.63$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:29:39.63$ifdk4/patch= 2006.285.23:29:39.63$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:29:39.63$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:29:39.63$setupk4/!*+20s 2006.285.23:29:41.15#abcon#<5=/03 3.4 6.4 19.32 881016.5\r\n> 2006.285.23:29:41.17#abcon#{5=INTERFACE CLEAR} 2006.285.23:29:41.23#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:29:43.14#trakl#Source acquired 2006.285.23:29:44.14#flagr#flagr/antenna,acquired 2006.285.23:29:51.32#abcon#<5=/03 3.4 6.4 19.33 881016.4\r\n> 2006.285.23:29:51.34#abcon#{5=INTERFACE CLEAR} 2006.285.23:29:51.40#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:29:54.14$setupk4/"tpicd 2006.285.23:29:54.14$setupk4/echo=off 2006.285.23:29:54.14$setupk4/xlog=off 2006.285.23:29:54.14:!2006.285.23:30:01 2006.285.23:30:01.00:preob 2006.285.23:30:01.14/onsource/TRACKING 2006.285.23:30:01.14:!2006.285.23:30:11 2006.285.23:30:11.00:"tape 2006.285.23:30:11.00:"st=record 2006.285.23:30:11.00:data_valid=on 2006.285.23:30:11.00:midob 2006.285.23:30:11.14/onsource/TRACKING 2006.285.23:30:11.14/wx/19.33,1016.4,88 2006.285.23:30:11.35/cable/+6.5093E-03 2006.285.23:30:12.44/va/01,07,usb,yes,33,36 2006.285.23:30:12.44/va/02,06,usb,yes,34,34 2006.285.23:30:12.44/va/03,07,usb,yes,33,35 2006.285.23:30:12.44/va/04,06,usb,yes,34,36 2006.285.23:30:12.44/va/05,03,usb,yes,34,34 2006.285.23:30:12.44/va/06,04,usb,yes,31,30 2006.285.23:30:12.44/va/07,04,usb,yes,31,32 2006.285.23:30:12.44/va/08,03,usb,yes,32,39 2006.285.23:30:12.67/valo/01,524.99,yes,locked 2006.285.23:30:12.67/valo/02,534.99,yes,locked 2006.285.23:30:12.67/valo/03,564.99,yes,locked 2006.285.23:30:12.67/valo/04,624.99,yes,locked 2006.285.23:30:12.67/valo/05,734.99,yes,locked 2006.285.23:30:12.67/valo/06,814.99,yes,locked 2006.285.23:30:12.67/valo/07,864.99,yes,locked 2006.285.23:30:12.67/valo/08,884.99,yes,locked 2006.285.23:30:13.76/vb/01,04,usb,yes,31,29 2006.285.23:30:13.76/vb/02,05,usb,yes,29,29 2006.285.23:30:13.76/vb/03,04,usb,yes,30,33 2006.285.23:30:13.76/vb/04,05,usb,yes,30,29 2006.285.23:30:13.76/vb/05,04,usb,yes,27,30 2006.285.23:30:13.76/vb/06,03,usb,yes,39,35 2006.285.23:30:13.76/vb/07,04,usb,yes,31,31 2006.285.23:30:13.76/vb/08,04,usb,yes,28,32 2006.285.23:30:13.99/vblo/01,629.99,yes,locked 2006.285.23:30:13.99/vblo/02,634.99,yes,locked 2006.285.23:30:13.99/vblo/03,649.99,yes,locked 2006.285.23:30:13.99/vblo/04,679.99,yes,locked 2006.285.23:30:13.99/vblo/05,709.99,yes,locked 2006.285.23:30:13.99/vblo/06,719.99,yes,locked 2006.285.23:30:13.99/vblo/07,734.99,yes,locked 2006.285.23:30:13.99/vblo/08,744.99,yes,locked 2006.285.23:30:14.14/vabw/8 2006.285.23:30:14.29/vbbw/8 2006.285.23:30:14.49/xfe/off,on,12.0 2006.285.23:30:14.86/ifatt/23,28,28,28 2006.285.23:30:15.08/fmout-gps/S +2.73E-07 2006.285.23:30:15.10:!2006.285.23:36:11 2006.285.23:36:11.00:data_valid=off 2006.285.23:36:11.00:"et 2006.285.23:36:11.00:!+3s 2006.285.23:36:14.01:"tape 2006.285.23:36:14.01:postob 2006.285.23:36:14.16/cable/+6.5078E-03 2006.285.23:36:14.16/wx/19.40,1016.5,88 2006.285.23:36:15.07/fmout-gps/S +2.81E-07 2006.285.23:36:15.07:scan_name=285-2341,jd0610,70 2006.285.23:36:15.07:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.285.23:36:15.14#flagr#flagr/antenna,new-source 2006.285.23:36:16.14:checkk5 2006.285.23:36:16.52/chk_autoobs//k5ts1/ autoobs is running! 2006.285.23:36:16.92/chk_autoobs//k5ts2/ autoobs is running! 2006.285.23:36:17.36/chk_autoobs//k5ts3/ autoobs is running! 2006.285.23:36:17.75/chk_autoobs//k5ts4/ autoobs is running! 2006.285.23:36:18.16/chk_obsdata//k5ts1/T2852330??a.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.285.23:36:18.71/chk_obsdata//k5ts2/T2852330??b.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.285.23:36:19.29/chk_obsdata//k5ts3/T2852330??c.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.285.23:36:19.64/chk_obsdata//k5ts4/T2852330??d.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.285.23:36:20.39/k5log//k5ts1_log_newline 2006.285.23:36:21.16/k5log//k5ts2_log_newline 2006.285.23:36:21.95/k5log//k5ts3_log_newline 2006.285.23:36:22.71/k5log//k5ts4_log_newline 2006.285.23:36:22.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.23:36:22.73:setupk4=1 2006.285.23:36:22.73$setupk4/echo=on 2006.285.23:36:22.73$setupk4/pcalon 2006.285.23:36:22.73$pcalon/"no phase cal control is implemented here 2006.285.23:36:22.73$setupk4/"tpicd=stop 2006.285.23:36:22.73$setupk4/"rec=synch_on 2006.285.23:36:22.73$setupk4/"rec_mode=128 2006.285.23:36:22.73$setupk4/!* 2006.285.23:36:22.73$setupk4/recpk4 2006.285.23:36:22.73$recpk4/recpatch= 2006.285.23:36:22.74$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.23:36:22.74$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.23:36:22.74$setupk4/vck44 2006.285.23:36:22.74$vck44/valo=1,524.99 2006.285.23:36:22.74#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.23:36:22.74#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.23:36:22.74#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:22.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:36:22.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:36:22.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:36:22.74#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:36:22.74#ibcon#first serial, iclass 35, count 0 2006.285.23:36:22.74#ibcon#enter sib2, iclass 35, count 0 2006.285.23:36:22.74#ibcon#flushed, iclass 35, count 0 2006.285.23:36:22.74#ibcon#about to write, iclass 35, count 0 2006.285.23:36:22.74#ibcon#wrote, iclass 35, count 0 2006.285.23:36:22.74#ibcon#about to read 3, iclass 35, count 0 2006.285.23:36:22.76#ibcon#read 3, iclass 35, count 0 2006.285.23:36:22.76#ibcon#about to read 4, iclass 35, count 0 2006.285.23:36:22.76#ibcon#read 4, iclass 35, count 0 2006.285.23:36:22.76#ibcon#about to read 5, iclass 35, count 0 2006.285.23:36:22.76#ibcon#read 5, iclass 35, count 0 2006.285.23:36:22.76#ibcon#about to read 6, iclass 35, count 0 2006.285.23:36:22.76#ibcon#read 6, iclass 35, count 0 2006.285.23:36:22.76#ibcon#end of sib2, iclass 35, count 0 2006.285.23:36:22.76#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:36:22.76#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:36:22.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.23:36:22.76#ibcon#*before write, iclass 35, count 0 2006.285.23:36:22.76#ibcon#enter sib2, iclass 35, count 0 2006.285.23:36:22.76#ibcon#flushed, iclass 35, count 0 2006.285.23:36:22.76#ibcon#about to write, iclass 35, count 0 2006.285.23:36:22.76#ibcon#wrote, iclass 35, count 0 2006.285.23:36:22.76#ibcon#about to read 3, iclass 35, count 0 2006.285.23:36:22.81#ibcon#read 3, iclass 35, count 0 2006.285.23:36:22.81#ibcon#about to read 4, iclass 35, count 0 2006.285.23:36:22.81#ibcon#read 4, iclass 35, count 0 2006.285.23:36:22.81#ibcon#about to read 5, iclass 35, count 0 2006.285.23:36:22.81#ibcon#read 5, iclass 35, count 0 2006.285.23:36:22.81#ibcon#about to read 6, iclass 35, count 0 2006.285.23:36:22.81#ibcon#read 6, iclass 35, count 0 2006.285.23:36:22.81#ibcon#end of sib2, iclass 35, count 0 2006.285.23:36:22.81#ibcon#*after write, iclass 35, count 0 2006.285.23:36:22.81#ibcon#*before return 0, iclass 35, count 0 2006.285.23:36:22.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:36:22.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:36:22.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:36:22.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:36:22.81$vck44/va=1,7 2006.285.23:36:22.81#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.23:36:22.81#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.23:36:22.81#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:22.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:36:22.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:36:22.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:36:22.81#ibcon#enter wrdev, iclass 37, count 2 2006.285.23:36:22.81#ibcon#first serial, iclass 37, count 2 2006.285.23:36:22.81#ibcon#enter sib2, iclass 37, count 2 2006.285.23:36:22.81#ibcon#flushed, iclass 37, count 2 2006.285.23:36:22.81#ibcon#about to write, iclass 37, count 2 2006.285.23:36:22.81#ibcon#wrote, iclass 37, count 2 2006.285.23:36:22.81#ibcon#about to read 3, iclass 37, count 2 2006.285.23:36:22.83#ibcon#read 3, iclass 37, count 2 2006.285.23:36:22.83#ibcon#about to read 4, iclass 37, count 2 2006.285.23:36:22.83#ibcon#read 4, iclass 37, count 2 2006.285.23:36:22.83#ibcon#about to read 5, iclass 37, count 2 2006.285.23:36:22.83#ibcon#read 5, iclass 37, count 2 2006.285.23:36:22.83#ibcon#about to read 6, iclass 37, count 2 2006.285.23:36:22.83#ibcon#read 6, iclass 37, count 2 2006.285.23:36:22.83#ibcon#end of sib2, iclass 37, count 2 2006.285.23:36:22.83#ibcon#*mode == 0, iclass 37, count 2 2006.285.23:36:22.83#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.23:36:22.83#ibcon#[25=AT01-07\r\n] 2006.285.23:36:22.83#ibcon#*before write, iclass 37, count 2 2006.285.23:36:22.83#ibcon#enter sib2, iclass 37, count 2 2006.285.23:36:22.83#ibcon#flushed, iclass 37, count 2 2006.285.23:36:22.83#ibcon#about to write, iclass 37, count 2 2006.285.23:36:22.83#ibcon#wrote, iclass 37, count 2 2006.285.23:36:22.83#ibcon#about to read 3, iclass 37, count 2 2006.285.23:36:22.86#ibcon#read 3, iclass 37, count 2 2006.285.23:36:22.86#ibcon#about to read 4, iclass 37, count 2 2006.285.23:36:22.86#ibcon#read 4, iclass 37, count 2 2006.285.23:36:22.86#ibcon#about to read 5, iclass 37, count 2 2006.285.23:36:22.86#ibcon#read 5, iclass 37, count 2 2006.285.23:36:22.86#ibcon#about to read 6, iclass 37, count 2 2006.285.23:36:22.86#ibcon#read 6, iclass 37, count 2 2006.285.23:36:22.86#ibcon#end of sib2, iclass 37, count 2 2006.285.23:36:22.86#ibcon#*after write, iclass 37, count 2 2006.285.23:36:22.86#ibcon#*before return 0, iclass 37, count 2 2006.285.23:36:22.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:36:22.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:36:22.86#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.23:36:22.86#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:22.86#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:36:22.98#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:36:22.98#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:36:22.98#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:36:22.98#ibcon#first serial, iclass 37, count 0 2006.285.23:36:22.98#ibcon#enter sib2, iclass 37, count 0 2006.285.23:36:22.98#ibcon#flushed, iclass 37, count 0 2006.285.23:36:22.98#ibcon#about to write, iclass 37, count 0 2006.285.23:36:22.98#ibcon#wrote, iclass 37, count 0 2006.285.23:36:22.98#ibcon#about to read 3, iclass 37, count 0 2006.285.23:36:23.00#ibcon#read 3, iclass 37, count 0 2006.285.23:36:23.00#ibcon#about to read 4, iclass 37, count 0 2006.285.23:36:23.00#ibcon#read 4, iclass 37, count 0 2006.285.23:36:23.00#ibcon#about to read 5, iclass 37, count 0 2006.285.23:36:23.00#ibcon#read 5, iclass 37, count 0 2006.285.23:36:23.00#ibcon#about to read 6, iclass 37, count 0 2006.285.23:36:23.00#ibcon#read 6, iclass 37, count 0 2006.285.23:36:23.00#ibcon#end of sib2, iclass 37, count 0 2006.285.23:36:23.00#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:36:23.00#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:36:23.00#ibcon#[25=USB\r\n] 2006.285.23:36:23.00#ibcon#*before write, iclass 37, count 0 2006.285.23:36:23.00#ibcon#enter sib2, iclass 37, count 0 2006.285.23:36:23.00#ibcon#flushed, iclass 37, count 0 2006.285.23:36:23.00#ibcon#about to write, iclass 37, count 0 2006.285.23:36:23.00#ibcon#wrote, iclass 37, count 0 2006.285.23:36:23.00#ibcon#about to read 3, iclass 37, count 0 2006.285.23:36:23.03#ibcon#read 3, iclass 37, count 0 2006.285.23:36:23.03#ibcon#about to read 4, iclass 37, count 0 2006.285.23:36:23.03#ibcon#read 4, iclass 37, count 0 2006.285.23:36:23.03#ibcon#about to read 5, iclass 37, count 0 2006.285.23:36:23.03#ibcon#read 5, iclass 37, count 0 2006.285.23:36:23.03#ibcon#about to read 6, iclass 37, count 0 2006.285.23:36:23.03#ibcon#read 6, iclass 37, count 0 2006.285.23:36:23.03#ibcon#end of sib2, iclass 37, count 0 2006.285.23:36:23.03#ibcon#*after write, iclass 37, count 0 2006.285.23:36:23.03#ibcon#*before return 0, iclass 37, count 0 2006.285.23:36:23.03#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:36:23.03#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:36:23.03#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:36:23.03#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:36:23.03$vck44/valo=2,534.99 2006.285.23:36:23.03#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.23:36:23.03#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.23:36:23.03#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:23.03#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:36:23.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:36:23.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:36:23.03#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:36:23.03#ibcon#first serial, iclass 39, count 0 2006.285.23:36:23.03#ibcon#enter sib2, iclass 39, count 0 2006.285.23:36:23.03#ibcon#flushed, iclass 39, count 0 2006.285.23:36:23.03#ibcon#about to write, iclass 39, count 0 2006.285.23:36:23.03#ibcon#wrote, iclass 39, count 0 2006.285.23:36:23.03#ibcon#about to read 3, iclass 39, count 0 2006.285.23:36:23.05#ibcon#read 3, iclass 39, count 0 2006.285.23:36:23.05#ibcon#about to read 4, iclass 39, count 0 2006.285.23:36:23.05#ibcon#read 4, iclass 39, count 0 2006.285.23:36:23.05#ibcon#about to read 5, iclass 39, count 0 2006.285.23:36:23.05#ibcon#read 5, iclass 39, count 0 2006.285.23:36:23.05#ibcon#about to read 6, iclass 39, count 0 2006.285.23:36:23.05#ibcon#read 6, iclass 39, count 0 2006.285.23:36:23.05#ibcon#end of sib2, iclass 39, count 0 2006.285.23:36:23.05#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:36:23.05#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:36:23.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.23:36:23.05#ibcon#*before write, iclass 39, count 0 2006.285.23:36:23.05#ibcon#enter sib2, iclass 39, count 0 2006.285.23:36:23.05#ibcon#flushed, iclass 39, count 0 2006.285.23:36:23.05#ibcon#about to write, iclass 39, count 0 2006.285.23:36:23.05#ibcon#wrote, iclass 39, count 0 2006.285.23:36:23.05#ibcon#about to read 3, iclass 39, count 0 2006.285.23:36:23.09#ibcon#read 3, iclass 39, count 0 2006.285.23:36:23.09#ibcon#about to read 4, iclass 39, count 0 2006.285.23:36:23.09#ibcon#read 4, iclass 39, count 0 2006.285.23:36:23.09#ibcon#about to read 5, iclass 39, count 0 2006.285.23:36:23.09#ibcon#read 5, iclass 39, count 0 2006.285.23:36:23.09#ibcon#about to read 6, iclass 39, count 0 2006.285.23:36:23.09#ibcon#read 6, iclass 39, count 0 2006.285.23:36:23.09#ibcon#end of sib2, iclass 39, count 0 2006.285.23:36:23.09#ibcon#*after write, iclass 39, count 0 2006.285.23:36:23.09#ibcon#*before return 0, iclass 39, count 0 2006.285.23:36:23.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:36:23.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:36:23.09#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:36:23.09#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:36:23.09$vck44/va=2,6 2006.285.23:36:23.09#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.23:36:23.09#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.23:36:23.09#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:23.09#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:36:23.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:36:23.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:36:23.15#ibcon#enter wrdev, iclass 3, count 2 2006.285.23:36:23.15#ibcon#first serial, iclass 3, count 2 2006.285.23:36:23.15#ibcon#enter sib2, iclass 3, count 2 2006.285.23:36:23.15#ibcon#flushed, iclass 3, count 2 2006.285.23:36:23.15#ibcon#about to write, iclass 3, count 2 2006.285.23:36:23.15#ibcon#wrote, iclass 3, count 2 2006.285.23:36:23.15#ibcon#about to read 3, iclass 3, count 2 2006.285.23:36:23.17#ibcon#read 3, iclass 3, count 2 2006.285.23:36:23.17#ibcon#about to read 4, iclass 3, count 2 2006.285.23:36:23.17#ibcon#read 4, iclass 3, count 2 2006.285.23:36:23.17#ibcon#about to read 5, iclass 3, count 2 2006.285.23:36:23.17#ibcon#read 5, iclass 3, count 2 2006.285.23:36:23.17#ibcon#about to read 6, iclass 3, count 2 2006.285.23:36:23.17#ibcon#read 6, iclass 3, count 2 2006.285.23:36:23.17#ibcon#end of sib2, iclass 3, count 2 2006.285.23:36:23.17#ibcon#*mode == 0, iclass 3, count 2 2006.285.23:36:23.17#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.23:36:23.17#ibcon#[25=AT02-06\r\n] 2006.285.23:36:23.17#ibcon#*before write, iclass 3, count 2 2006.285.23:36:23.17#ibcon#enter sib2, iclass 3, count 2 2006.285.23:36:23.17#ibcon#flushed, iclass 3, count 2 2006.285.23:36:23.17#ibcon#about to write, iclass 3, count 2 2006.285.23:36:23.17#ibcon#wrote, iclass 3, count 2 2006.285.23:36:23.17#ibcon#about to read 3, iclass 3, count 2 2006.285.23:36:23.20#ibcon#read 3, iclass 3, count 2 2006.285.23:36:23.20#ibcon#about to read 4, iclass 3, count 2 2006.285.23:36:23.20#ibcon#read 4, iclass 3, count 2 2006.285.23:36:23.20#ibcon#about to read 5, iclass 3, count 2 2006.285.23:36:23.20#ibcon#read 5, iclass 3, count 2 2006.285.23:36:23.20#ibcon#about to read 6, iclass 3, count 2 2006.285.23:36:23.20#ibcon#read 6, iclass 3, count 2 2006.285.23:36:23.20#ibcon#end of sib2, iclass 3, count 2 2006.285.23:36:23.20#ibcon#*after write, iclass 3, count 2 2006.285.23:36:23.20#ibcon#*before return 0, iclass 3, count 2 2006.285.23:36:23.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:36:23.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:36:23.20#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.23:36:23.20#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:23.20#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:36:23.32#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:36:23.32#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:36:23.32#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:36:23.32#ibcon#first serial, iclass 3, count 0 2006.285.23:36:23.32#ibcon#enter sib2, iclass 3, count 0 2006.285.23:36:23.32#ibcon#flushed, iclass 3, count 0 2006.285.23:36:23.32#ibcon#about to write, iclass 3, count 0 2006.285.23:36:23.32#ibcon#wrote, iclass 3, count 0 2006.285.23:36:23.32#ibcon#about to read 3, iclass 3, count 0 2006.285.23:36:23.34#ibcon#read 3, iclass 3, count 0 2006.285.23:36:23.34#ibcon#about to read 4, iclass 3, count 0 2006.285.23:36:23.34#ibcon#read 4, iclass 3, count 0 2006.285.23:36:23.34#ibcon#about to read 5, iclass 3, count 0 2006.285.23:36:23.34#ibcon#read 5, iclass 3, count 0 2006.285.23:36:23.34#ibcon#about to read 6, iclass 3, count 0 2006.285.23:36:23.34#ibcon#read 6, iclass 3, count 0 2006.285.23:36:23.34#ibcon#end of sib2, iclass 3, count 0 2006.285.23:36:23.34#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:36:23.34#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:36:23.34#ibcon#[25=USB\r\n] 2006.285.23:36:23.34#ibcon#*before write, iclass 3, count 0 2006.285.23:36:23.34#ibcon#enter sib2, iclass 3, count 0 2006.285.23:36:23.34#ibcon#flushed, iclass 3, count 0 2006.285.23:36:23.34#ibcon#about to write, iclass 3, count 0 2006.285.23:36:23.34#ibcon#wrote, iclass 3, count 0 2006.285.23:36:23.34#ibcon#about to read 3, iclass 3, count 0 2006.285.23:36:23.37#ibcon#read 3, iclass 3, count 0 2006.285.23:36:23.37#ibcon#about to read 4, iclass 3, count 0 2006.285.23:36:23.37#ibcon#read 4, iclass 3, count 0 2006.285.23:36:23.37#ibcon#about to read 5, iclass 3, count 0 2006.285.23:36:23.37#ibcon#read 5, iclass 3, count 0 2006.285.23:36:23.37#ibcon#about to read 6, iclass 3, count 0 2006.285.23:36:23.37#ibcon#read 6, iclass 3, count 0 2006.285.23:36:23.37#ibcon#end of sib2, iclass 3, count 0 2006.285.23:36:23.37#ibcon#*after write, iclass 3, count 0 2006.285.23:36:23.37#ibcon#*before return 0, iclass 3, count 0 2006.285.23:36:23.37#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:36:23.37#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:36:23.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:36:23.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:36:23.37$vck44/valo=3,564.99 2006.285.23:36:23.37#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.23:36:23.37#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.23:36:23.37#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:23.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:36:23.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:36:23.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:36:23.37#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:36:23.37#ibcon#first serial, iclass 5, count 0 2006.285.23:36:23.37#ibcon#enter sib2, iclass 5, count 0 2006.285.23:36:23.37#ibcon#flushed, iclass 5, count 0 2006.285.23:36:23.37#ibcon#about to write, iclass 5, count 0 2006.285.23:36:23.37#ibcon#wrote, iclass 5, count 0 2006.285.23:36:23.37#ibcon#about to read 3, iclass 5, count 0 2006.285.23:36:23.39#ibcon#read 3, iclass 5, count 0 2006.285.23:36:23.39#ibcon#about to read 4, iclass 5, count 0 2006.285.23:36:23.39#ibcon#read 4, iclass 5, count 0 2006.285.23:36:23.39#ibcon#about to read 5, iclass 5, count 0 2006.285.23:36:23.39#ibcon#read 5, iclass 5, count 0 2006.285.23:36:23.39#ibcon#about to read 6, iclass 5, count 0 2006.285.23:36:23.39#ibcon#read 6, iclass 5, count 0 2006.285.23:36:23.39#ibcon#end of sib2, iclass 5, count 0 2006.285.23:36:23.39#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:36:23.39#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:36:23.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.23:36:23.39#ibcon#*before write, iclass 5, count 0 2006.285.23:36:23.39#ibcon#enter sib2, iclass 5, count 0 2006.285.23:36:23.39#ibcon#flushed, iclass 5, count 0 2006.285.23:36:23.39#ibcon#about to write, iclass 5, count 0 2006.285.23:36:23.39#ibcon#wrote, iclass 5, count 0 2006.285.23:36:23.39#ibcon#about to read 3, iclass 5, count 0 2006.285.23:36:23.43#ibcon#read 3, iclass 5, count 0 2006.285.23:36:23.43#ibcon#about to read 4, iclass 5, count 0 2006.285.23:36:23.43#ibcon#read 4, iclass 5, count 0 2006.285.23:36:23.43#ibcon#about to read 5, iclass 5, count 0 2006.285.23:36:23.43#ibcon#read 5, iclass 5, count 0 2006.285.23:36:23.43#ibcon#about to read 6, iclass 5, count 0 2006.285.23:36:23.43#ibcon#read 6, iclass 5, count 0 2006.285.23:36:23.43#ibcon#end of sib2, iclass 5, count 0 2006.285.23:36:23.43#ibcon#*after write, iclass 5, count 0 2006.285.23:36:23.43#ibcon#*before return 0, iclass 5, count 0 2006.285.23:36:23.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:36:23.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:36:23.43#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:36:23.43#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:36:23.43$vck44/va=3,7 2006.285.23:36:23.43#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.23:36:23.43#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.23:36:23.43#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:23.43#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:36:23.49#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:36:23.49#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:36:23.49#ibcon#enter wrdev, iclass 7, count 2 2006.285.23:36:23.49#ibcon#first serial, iclass 7, count 2 2006.285.23:36:23.49#ibcon#enter sib2, iclass 7, count 2 2006.285.23:36:23.49#ibcon#flushed, iclass 7, count 2 2006.285.23:36:23.49#ibcon#about to write, iclass 7, count 2 2006.285.23:36:23.49#ibcon#wrote, iclass 7, count 2 2006.285.23:36:23.49#ibcon#about to read 3, iclass 7, count 2 2006.285.23:36:23.51#ibcon#read 3, iclass 7, count 2 2006.285.23:36:23.51#ibcon#about to read 4, iclass 7, count 2 2006.285.23:36:23.51#ibcon#read 4, iclass 7, count 2 2006.285.23:36:23.51#ibcon#about to read 5, iclass 7, count 2 2006.285.23:36:23.51#ibcon#read 5, iclass 7, count 2 2006.285.23:36:23.51#ibcon#about to read 6, iclass 7, count 2 2006.285.23:36:23.51#ibcon#read 6, iclass 7, count 2 2006.285.23:36:23.51#ibcon#end of sib2, iclass 7, count 2 2006.285.23:36:23.51#ibcon#*mode == 0, iclass 7, count 2 2006.285.23:36:23.51#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.23:36:23.51#ibcon#[25=AT03-07\r\n] 2006.285.23:36:23.51#ibcon#*before write, iclass 7, count 2 2006.285.23:36:23.51#ibcon#enter sib2, iclass 7, count 2 2006.285.23:36:23.51#ibcon#flushed, iclass 7, count 2 2006.285.23:36:23.51#ibcon#about to write, iclass 7, count 2 2006.285.23:36:23.51#ibcon#wrote, iclass 7, count 2 2006.285.23:36:23.51#ibcon#about to read 3, iclass 7, count 2 2006.285.23:36:23.54#ibcon#read 3, iclass 7, count 2 2006.285.23:36:23.54#ibcon#about to read 4, iclass 7, count 2 2006.285.23:36:23.54#ibcon#read 4, iclass 7, count 2 2006.285.23:36:23.54#ibcon#about to read 5, iclass 7, count 2 2006.285.23:36:23.54#ibcon#read 5, iclass 7, count 2 2006.285.23:36:23.54#ibcon#about to read 6, iclass 7, count 2 2006.285.23:36:23.54#ibcon#read 6, iclass 7, count 2 2006.285.23:36:23.54#ibcon#end of sib2, iclass 7, count 2 2006.285.23:36:23.54#ibcon#*after write, iclass 7, count 2 2006.285.23:36:23.54#ibcon#*before return 0, iclass 7, count 2 2006.285.23:36:23.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:36:23.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:36:23.54#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.23:36:23.54#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:23.54#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:36:23.66#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:36:23.66#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:36:23.66#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:36:23.66#ibcon#first serial, iclass 7, count 0 2006.285.23:36:23.66#ibcon#enter sib2, iclass 7, count 0 2006.285.23:36:23.66#ibcon#flushed, iclass 7, count 0 2006.285.23:36:23.66#ibcon#about to write, iclass 7, count 0 2006.285.23:36:23.66#ibcon#wrote, iclass 7, count 0 2006.285.23:36:23.66#ibcon#about to read 3, iclass 7, count 0 2006.285.23:36:23.68#ibcon#read 3, iclass 7, count 0 2006.285.23:36:23.68#ibcon#about to read 4, iclass 7, count 0 2006.285.23:36:23.68#ibcon#read 4, iclass 7, count 0 2006.285.23:36:23.68#ibcon#about to read 5, iclass 7, count 0 2006.285.23:36:23.68#ibcon#read 5, iclass 7, count 0 2006.285.23:36:23.68#ibcon#about to read 6, iclass 7, count 0 2006.285.23:36:23.68#ibcon#read 6, iclass 7, count 0 2006.285.23:36:23.68#ibcon#end of sib2, iclass 7, count 0 2006.285.23:36:23.68#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:36:23.68#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:36:23.68#ibcon#[25=USB\r\n] 2006.285.23:36:23.68#ibcon#*before write, iclass 7, count 0 2006.285.23:36:23.68#ibcon#enter sib2, iclass 7, count 0 2006.285.23:36:23.68#ibcon#flushed, iclass 7, count 0 2006.285.23:36:23.68#ibcon#about to write, iclass 7, count 0 2006.285.23:36:23.68#ibcon#wrote, iclass 7, count 0 2006.285.23:36:23.68#ibcon#about to read 3, iclass 7, count 0 2006.285.23:36:23.71#ibcon#read 3, iclass 7, count 0 2006.285.23:36:23.71#ibcon#about to read 4, iclass 7, count 0 2006.285.23:36:23.71#ibcon#read 4, iclass 7, count 0 2006.285.23:36:23.71#ibcon#about to read 5, iclass 7, count 0 2006.285.23:36:23.71#ibcon#read 5, iclass 7, count 0 2006.285.23:36:23.71#ibcon#about to read 6, iclass 7, count 0 2006.285.23:36:23.71#ibcon#read 6, iclass 7, count 0 2006.285.23:36:23.71#ibcon#end of sib2, iclass 7, count 0 2006.285.23:36:23.71#ibcon#*after write, iclass 7, count 0 2006.285.23:36:23.71#ibcon#*before return 0, iclass 7, count 0 2006.285.23:36:23.71#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:36:23.71#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:36:23.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:36:23.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:36:23.71$vck44/valo=4,624.99 2006.285.23:36:23.71#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.23:36:23.71#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.23:36:23.71#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:23.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:36:23.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:36:23.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:36:23.71#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:36:23.71#ibcon#first serial, iclass 11, count 0 2006.285.23:36:23.71#ibcon#enter sib2, iclass 11, count 0 2006.285.23:36:23.71#ibcon#flushed, iclass 11, count 0 2006.285.23:36:23.71#ibcon#about to write, iclass 11, count 0 2006.285.23:36:23.71#ibcon#wrote, iclass 11, count 0 2006.285.23:36:23.71#ibcon#about to read 3, iclass 11, count 0 2006.285.23:36:23.73#ibcon#read 3, iclass 11, count 0 2006.285.23:36:23.73#ibcon#about to read 4, iclass 11, count 0 2006.285.23:36:23.73#ibcon#read 4, iclass 11, count 0 2006.285.23:36:23.73#ibcon#about to read 5, iclass 11, count 0 2006.285.23:36:23.73#ibcon#read 5, iclass 11, count 0 2006.285.23:36:23.73#ibcon#about to read 6, iclass 11, count 0 2006.285.23:36:23.73#ibcon#read 6, iclass 11, count 0 2006.285.23:36:23.73#ibcon#end of sib2, iclass 11, count 0 2006.285.23:36:23.73#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:36:23.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:36:23.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.23:36:23.73#ibcon#*before write, iclass 11, count 0 2006.285.23:36:23.73#ibcon#enter sib2, iclass 11, count 0 2006.285.23:36:23.73#ibcon#flushed, iclass 11, count 0 2006.285.23:36:23.73#ibcon#about to write, iclass 11, count 0 2006.285.23:36:23.73#ibcon#wrote, iclass 11, count 0 2006.285.23:36:23.73#ibcon#about to read 3, iclass 11, count 0 2006.285.23:36:23.77#ibcon#read 3, iclass 11, count 0 2006.285.23:36:23.77#ibcon#about to read 4, iclass 11, count 0 2006.285.23:36:23.77#ibcon#read 4, iclass 11, count 0 2006.285.23:36:23.77#ibcon#about to read 5, iclass 11, count 0 2006.285.23:36:23.77#ibcon#read 5, iclass 11, count 0 2006.285.23:36:23.77#ibcon#about to read 6, iclass 11, count 0 2006.285.23:36:23.77#ibcon#read 6, iclass 11, count 0 2006.285.23:36:23.77#ibcon#end of sib2, iclass 11, count 0 2006.285.23:36:23.77#ibcon#*after write, iclass 11, count 0 2006.285.23:36:23.77#ibcon#*before return 0, iclass 11, count 0 2006.285.23:36:23.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:36:23.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:36:23.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:36:23.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:36:23.77$vck44/va=4,6 2006.285.23:36:23.77#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.23:36:23.77#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.23:36:23.77#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:23.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:36:23.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:36:23.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:36:23.83#ibcon#enter wrdev, iclass 13, count 2 2006.285.23:36:23.83#ibcon#first serial, iclass 13, count 2 2006.285.23:36:23.83#ibcon#enter sib2, iclass 13, count 2 2006.285.23:36:23.83#ibcon#flushed, iclass 13, count 2 2006.285.23:36:23.83#ibcon#about to write, iclass 13, count 2 2006.285.23:36:23.83#ibcon#wrote, iclass 13, count 2 2006.285.23:36:23.83#ibcon#about to read 3, iclass 13, count 2 2006.285.23:36:23.85#ibcon#read 3, iclass 13, count 2 2006.285.23:36:23.85#ibcon#about to read 4, iclass 13, count 2 2006.285.23:36:23.85#ibcon#read 4, iclass 13, count 2 2006.285.23:36:23.85#ibcon#about to read 5, iclass 13, count 2 2006.285.23:36:23.85#ibcon#read 5, iclass 13, count 2 2006.285.23:36:23.85#ibcon#about to read 6, iclass 13, count 2 2006.285.23:36:23.85#ibcon#read 6, iclass 13, count 2 2006.285.23:36:23.85#ibcon#end of sib2, iclass 13, count 2 2006.285.23:36:23.85#ibcon#*mode == 0, iclass 13, count 2 2006.285.23:36:23.85#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.23:36:23.85#ibcon#[25=AT04-06\r\n] 2006.285.23:36:23.85#ibcon#*before write, iclass 13, count 2 2006.285.23:36:23.85#ibcon#enter sib2, iclass 13, count 2 2006.285.23:36:23.85#ibcon#flushed, iclass 13, count 2 2006.285.23:36:23.85#ibcon#about to write, iclass 13, count 2 2006.285.23:36:23.85#ibcon#wrote, iclass 13, count 2 2006.285.23:36:23.85#ibcon#about to read 3, iclass 13, count 2 2006.285.23:36:23.88#ibcon#read 3, iclass 13, count 2 2006.285.23:36:23.88#ibcon#about to read 4, iclass 13, count 2 2006.285.23:36:23.88#ibcon#read 4, iclass 13, count 2 2006.285.23:36:23.88#ibcon#about to read 5, iclass 13, count 2 2006.285.23:36:23.88#ibcon#read 5, iclass 13, count 2 2006.285.23:36:23.88#ibcon#about to read 6, iclass 13, count 2 2006.285.23:36:23.88#ibcon#read 6, iclass 13, count 2 2006.285.23:36:23.88#ibcon#end of sib2, iclass 13, count 2 2006.285.23:36:23.88#ibcon#*after write, iclass 13, count 2 2006.285.23:36:23.88#ibcon#*before return 0, iclass 13, count 2 2006.285.23:36:23.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:36:23.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:36:23.88#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.23:36:23.88#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:23.88#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:36:24.00#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:36:24.00#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:36:24.00#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:36:24.00#ibcon#first serial, iclass 13, count 0 2006.285.23:36:24.00#ibcon#enter sib2, iclass 13, count 0 2006.285.23:36:24.00#ibcon#flushed, iclass 13, count 0 2006.285.23:36:24.00#ibcon#about to write, iclass 13, count 0 2006.285.23:36:24.00#ibcon#wrote, iclass 13, count 0 2006.285.23:36:24.00#ibcon#about to read 3, iclass 13, count 0 2006.285.23:36:24.02#ibcon#read 3, iclass 13, count 0 2006.285.23:36:24.02#ibcon#about to read 4, iclass 13, count 0 2006.285.23:36:24.02#ibcon#read 4, iclass 13, count 0 2006.285.23:36:24.02#ibcon#about to read 5, iclass 13, count 0 2006.285.23:36:24.02#ibcon#read 5, iclass 13, count 0 2006.285.23:36:24.02#ibcon#about to read 6, iclass 13, count 0 2006.285.23:36:24.02#ibcon#read 6, iclass 13, count 0 2006.285.23:36:24.02#ibcon#end of sib2, iclass 13, count 0 2006.285.23:36:24.02#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:36:24.02#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:36:24.02#ibcon#[25=USB\r\n] 2006.285.23:36:24.02#ibcon#*before write, iclass 13, count 0 2006.285.23:36:24.02#ibcon#enter sib2, iclass 13, count 0 2006.285.23:36:24.02#ibcon#flushed, iclass 13, count 0 2006.285.23:36:24.02#ibcon#about to write, iclass 13, count 0 2006.285.23:36:24.02#ibcon#wrote, iclass 13, count 0 2006.285.23:36:24.02#ibcon#about to read 3, iclass 13, count 0 2006.285.23:36:24.05#ibcon#read 3, iclass 13, count 0 2006.285.23:36:24.05#ibcon#about to read 4, iclass 13, count 0 2006.285.23:36:24.05#ibcon#read 4, iclass 13, count 0 2006.285.23:36:24.05#ibcon#about to read 5, iclass 13, count 0 2006.285.23:36:24.05#ibcon#read 5, iclass 13, count 0 2006.285.23:36:24.05#ibcon#about to read 6, iclass 13, count 0 2006.285.23:36:24.05#ibcon#read 6, iclass 13, count 0 2006.285.23:36:24.05#ibcon#end of sib2, iclass 13, count 0 2006.285.23:36:24.05#ibcon#*after write, iclass 13, count 0 2006.285.23:36:24.05#ibcon#*before return 0, iclass 13, count 0 2006.285.23:36:24.05#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:36:24.05#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:36:24.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:36:24.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:36:24.05$vck44/valo=5,734.99 2006.285.23:36:24.05#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.23:36:24.05#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.23:36:24.05#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:24.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:36:24.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:36:24.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:36:24.05#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:36:24.05#ibcon#first serial, iclass 15, count 0 2006.285.23:36:24.05#ibcon#enter sib2, iclass 15, count 0 2006.285.23:36:24.05#ibcon#flushed, iclass 15, count 0 2006.285.23:36:24.05#ibcon#about to write, iclass 15, count 0 2006.285.23:36:24.05#ibcon#wrote, iclass 15, count 0 2006.285.23:36:24.05#ibcon#about to read 3, iclass 15, count 0 2006.285.23:36:24.07#ibcon#read 3, iclass 15, count 0 2006.285.23:36:24.07#ibcon#about to read 4, iclass 15, count 0 2006.285.23:36:24.07#ibcon#read 4, iclass 15, count 0 2006.285.23:36:24.07#ibcon#about to read 5, iclass 15, count 0 2006.285.23:36:24.07#ibcon#read 5, iclass 15, count 0 2006.285.23:36:24.07#ibcon#about to read 6, iclass 15, count 0 2006.285.23:36:24.07#ibcon#read 6, iclass 15, count 0 2006.285.23:36:24.07#ibcon#end of sib2, iclass 15, count 0 2006.285.23:36:24.07#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:36:24.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:36:24.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.23:36:24.07#ibcon#*before write, iclass 15, count 0 2006.285.23:36:24.07#ibcon#enter sib2, iclass 15, count 0 2006.285.23:36:24.07#ibcon#flushed, iclass 15, count 0 2006.285.23:36:24.07#ibcon#about to write, iclass 15, count 0 2006.285.23:36:24.07#ibcon#wrote, iclass 15, count 0 2006.285.23:36:24.07#ibcon#about to read 3, iclass 15, count 0 2006.285.23:36:24.11#ibcon#read 3, iclass 15, count 0 2006.285.23:36:24.11#ibcon#about to read 4, iclass 15, count 0 2006.285.23:36:24.11#ibcon#read 4, iclass 15, count 0 2006.285.23:36:24.11#ibcon#about to read 5, iclass 15, count 0 2006.285.23:36:24.11#ibcon#read 5, iclass 15, count 0 2006.285.23:36:24.11#ibcon#about to read 6, iclass 15, count 0 2006.285.23:36:24.11#ibcon#read 6, iclass 15, count 0 2006.285.23:36:24.11#ibcon#end of sib2, iclass 15, count 0 2006.285.23:36:24.11#ibcon#*after write, iclass 15, count 0 2006.285.23:36:24.11#ibcon#*before return 0, iclass 15, count 0 2006.285.23:36:24.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:36:24.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:36:24.11#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:36:24.11#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:36:24.11$vck44/va=5,3 2006.285.23:36:24.11#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.23:36:24.11#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.23:36:24.11#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:24.11#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:36:24.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:36:24.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:36:24.17#ibcon#enter wrdev, iclass 17, count 2 2006.285.23:36:24.17#ibcon#first serial, iclass 17, count 2 2006.285.23:36:24.17#ibcon#enter sib2, iclass 17, count 2 2006.285.23:36:24.17#ibcon#flushed, iclass 17, count 2 2006.285.23:36:24.17#ibcon#about to write, iclass 17, count 2 2006.285.23:36:24.17#ibcon#wrote, iclass 17, count 2 2006.285.23:36:24.17#ibcon#about to read 3, iclass 17, count 2 2006.285.23:36:24.19#ibcon#read 3, iclass 17, count 2 2006.285.23:36:24.19#ibcon#about to read 4, iclass 17, count 2 2006.285.23:36:24.19#ibcon#read 4, iclass 17, count 2 2006.285.23:36:24.19#ibcon#about to read 5, iclass 17, count 2 2006.285.23:36:24.19#ibcon#read 5, iclass 17, count 2 2006.285.23:36:24.19#ibcon#about to read 6, iclass 17, count 2 2006.285.23:36:24.19#ibcon#read 6, iclass 17, count 2 2006.285.23:36:24.19#ibcon#end of sib2, iclass 17, count 2 2006.285.23:36:24.19#ibcon#*mode == 0, iclass 17, count 2 2006.285.23:36:24.19#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.23:36:24.19#ibcon#[25=AT05-03\r\n] 2006.285.23:36:24.19#ibcon#*before write, iclass 17, count 2 2006.285.23:36:24.19#ibcon#enter sib2, iclass 17, count 2 2006.285.23:36:24.19#ibcon#flushed, iclass 17, count 2 2006.285.23:36:24.19#ibcon#about to write, iclass 17, count 2 2006.285.23:36:24.19#ibcon#wrote, iclass 17, count 2 2006.285.23:36:24.19#ibcon#about to read 3, iclass 17, count 2 2006.285.23:36:24.22#ibcon#read 3, iclass 17, count 2 2006.285.23:36:24.22#ibcon#about to read 4, iclass 17, count 2 2006.285.23:36:24.22#ibcon#read 4, iclass 17, count 2 2006.285.23:36:24.22#ibcon#about to read 5, iclass 17, count 2 2006.285.23:36:24.22#ibcon#read 5, iclass 17, count 2 2006.285.23:36:24.22#ibcon#about to read 6, iclass 17, count 2 2006.285.23:36:24.22#ibcon#read 6, iclass 17, count 2 2006.285.23:36:24.22#ibcon#end of sib2, iclass 17, count 2 2006.285.23:36:24.22#ibcon#*after write, iclass 17, count 2 2006.285.23:36:24.22#ibcon#*before return 0, iclass 17, count 2 2006.285.23:36:24.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:36:24.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:36:24.22#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.23:36:24.22#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:24.22#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:36:24.34#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:36:24.34#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:36:24.34#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:36:24.34#ibcon#first serial, iclass 17, count 0 2006.285.23:36:24.34#ibcon#enter sib2, iclass 17, count 0 2006.285.23:36:24.34#ibcon#flushed, iclass 17, count 0 2006.285.23:36:24.34#ibcon#about to write, iclass 17, count 0 2006.285.23:36:24.34#ibcon#wrote, iclass 17, count 0 2006.285.23:36:24.34#ibcon#about to read 3, iclass 17, count 0 2006.285.23:36:24.36#ibcon#read 3, iclass 17, count 0 2006.285.23:36:24.36#ibcon#about to read 4, iclass 17, count 0 2006.285.23:36:24.36#ibcon#read 4, iclass 17, count 0 2006.285.23:36:24.36#ibcon#about to read 5, iclass 17, count 0 2006.285.23:36:24.36#ibcon#read 5, iclass 17, count 0 2006.285.23:36:24.36#ibcon#about to read 6, iclass 17, count 0 2006.285.23:36:24.36#ibcon#read 6, iclass 17, count 0 2006.285.23:36:24.36#ibcon#end of sib2, iclass 17, count 0 2006.285.23:36:24.36#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:36:24.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:36:24.36#ibcon#[25=USB\r\n] 2006.285.23:36:24.36#ibcon#*before write, iclass 17, count 0 2006.285.23:36:24.36#ibcon#enter sib2, iclass 17, count 0 2006.285.23:36:24.36#ibcon#flushed, iclass 17, count 0 2006.285.23:36:24.36#ibcon#about to write, iclass 17, count 0 2006.285.23:36:24.36#ibcon#wrote, iclass 17, count 0 2006.285.23:36:24.36#ibcon#about to read 3, iclass 17, count 0 2006.285.23:36:24.39#ibcon#read 3, iclass 17, count 0 2006.285.23:36:24.39#ibcon#about to read 4, iclass 17, count 0 2006.285.23:36:24.39#ibcon#read 4, iclass 17, count 0 2006.285.23:36:24.39#ibcon#about to read 5, iclass 17, count 0 2006.285.23:36:24.39#ibcon#read 5, iclass 17, count 0 2006.285.23:36:24.39#ibcon#about to read 6, iclass 17, count 0 2006.285.23:36:24.39#ibcon#read 6, iclass 17, count 0 2006.285.23:36:24.39#ibcon#end of sib2, iclass 17, count 0 2006.285.23:36:24.39#ibcon#*after write, iclass 17, count 0 2006.285.23:36:24.39#ibcon#*before return 0, iclass 17, count 0 2006.285.23:36:24.39#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:36:24.39#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:36:24.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:36:24.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:36:24.39$vck44/valo=6,814.99 2006.285.23:36:24.39#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.23:36:24.39#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.23:36:24.39#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:24.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:36:24.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:36:24.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:36:24.39#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:36:24.39#ibcon#first serial, iclass 19, count 0 2006.285.23:36:24.39#ibcon#enter sib2, iclass 19, count 0 2006.285.23:36:24.39#ibcon#flushed, iclass 19, count 0 2006.285.23:36:24.39#ibcon#about to write, iclass 19, count 0 2006.285.23:36:24.39#ibcon#wrote, iclass 19, count 0 2006.285.23:36:24.39#ibcon#about to read 3, iclass 19, count 0 2006.285.23:36:24.41#ibcon#read 3, iclass 19, count 0 2006.285.23:36:24.41#ibcon#about to read 4, iclass 19, count 0 2006.285.23:36:24.41#ibcon#read 4, iclass 19, count 0 2006.285.23:36:24.41#ibcon#about to read 5, iclass 19, count 0 2006.285.23:36:24.41#ibcon#read 5, iclass 19, count 0 2006.285.23:36:24.41#ibcon#about to read 6, iclass 19, count 0 2006.285.23:36:24.41#ibcon#read 6, iclass 19, count 0 2006.285.23:36:24.41#ibcon#end of sib2, iclass 19, count 0 2006.285.23:36:24.41#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:36:24.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:36:24.41#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.23:36:24.41#ibcon#*before write, iclass 19, count 0 2006.285.23:36:24.41#ibcon#enter sib2, iclass 19, count 0 2006.285.23:36:24.41#ibcon#flushed, iclass 19, count 0 2006.285.23:36:24.41#ibcon#about to write, iclass 19, count 0 2006.285.23:36:24.41#ibcon#wrote, iclass 19, count 0 2006.285.23:36:24.41#ibcon#about to read 3, iclass 19, count 0 2006.285.23:36:24.45#ibcon#read 3, iclass 19, count 0 2006.285.23:36:24.45#ibcon#about to read 4, iclass 19, count 0 2006.285.23:36:24.45#ibcon#read 4, iclass 19, count 0 2006.285.23:36:24.45#ibcon#about to read 5, iclass 19, count 0 2006.285.23:36:24.45#ibcon#read 5, iclass 19, count 0 2006.285.23:36:24.45#ibcon#about to read 6, iclass 19, count 0 2006.285.23:36:24.45#ibcon#read 6, iclass 19, count 0 2006.285.23:36:24.45#ibcon#end of sib2, iclass 19, count 0 2006.285.23:36:24.45#ibcon#*after write, iclass 19, count 0 2006.285.23:36:24.45#ibcon#*before return 0, iclass 19, count 0 2006.285.23:36:24.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:36:24.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:36:24.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:36:24.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:36:24.45$vck44/va=6,4 2006.285.23:36:24.45#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.23:36:24.45#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.23:36:24.45#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:24.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:36:24.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:36:24.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:36:24.51#ibcon#enter wrdev, iclass 21, count 2 2006.285.23:36:24.51#ibcon#first serial, iclass 21, count 2 2006.285.23:36:24.51#ibcon#enter sib2, iclass 21, count 2 2006.285.23:36:24.51#ibcon#flushed, iclass 21, count 2 2006.285.23:36:24.51#ibcon#about to write, iclass 21, count 2 2006.285.23:36:24.51#ibcon#wrote, iclass 21, count 2 2006.285.23:36:24.51#ibcon#about to read 3, iclass 21, count 2 2006.285.23:36:24.53#ibcon#read 3, iclass 21, count 2 2006.285.23:36:24.53#ibcon#about to read 4, iclass 21, count 2 2006.285.23:36:24.53#ibcon#read 4, iclass 21, count 2 2006.285.23:36:24.53#ibcon#about to read 5, iclass 21, count 2 2006.285.23:36:24.53#ibcon#read 5, iclass 21, count 2 2006.285.23:36:24.53#ibcon#about to read 6, iclass 21, count 2 2006.285.23:36:24.53#ibcon#read 6, iclass 21, count 2 2006.285.23:36:24.53#ibcon#end of sib2, iclass 21, count 2 2006.285.23:36:24.53#ibcon#*mode == 0, iclass 21, count 2 2006.285.23:36:24.53#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.23:36:24.53#ibcon#[25=AT06-04\r\n] 2006.285.23:36:24.53#ibcon#*before write, iclass 21, count 2 2006.285.23:36:24.53#ibcon#enter sib2, iclass 21, count 2 2006.285.23:36:24.53#ibcon#flushed, iclass 21, count 2 2006.285.23:36:24.53#ibcon#about to write, iclass 21, count 2 2006.285.23:36:24.53#ibcon#wrote, iclass 21, count 2 2006.285.23:36:24.53#ibcon#about to read 3, iclass 21, count 2 2006.285.23:36:24.56#ibcon#read 3, iclass 21, count 2 2006.285.23:36:24.56#ibcon#about to read 4, iclass 21, count 2 2006.285.23:36:24.56#ibcon#read 4, iclass 21, count 2 2006.285.23:36:24.56#ibcon#about to read 5, iclass 21, count 2 2006.285.23:36:24.56#ibcon#read 5, iclass 21, count 2 2006.285.23:36:24.56#ibcon#about to read 6, iclass 21, count 2 2006.285.23:36:24.56#ibcon#read 6, iclass 21, count 2 2006.285.23:36:24.56#ibcon#end of sib2, iclass 21, count 2 2006.285.23:36:24.56#ibcon#*after write, iclass 21, count 2 2006.285.23:36:24.56#ibcon#*before return 0, iclass 21, count 2 2006.285.23:36:24.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:36:24.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:36:24.56#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.23:36:24.56#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:24.56#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:36:24.68#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:36:24.68#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:36:24.68#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:36:24.68#ibcon#first serial, iclass 21, count 0 2006.285.23:36:24.68#ibcon#enter sib2, iclass 21, count 0 2006.285.23:36:24.68#ibcon#flushed, iclass 21, count 0 2006.285.23:36:24.68#ibcon#about to write, iclass 21, count 0 2006.285.23:36:24.68#ibcon#wrote, iclass 21, count 0 2006.285.23:36:24.68#ibcon#about to read 3, iclass 21, count 0 2006.285.23:36:24.70#ibcon#read 3, iclass 21, count 0 2006.285.23:36:24.70#ibcon#about to read 4, iclass 21, count 0 2006.285.23:36:24.70#ibcon#read 4, iclass 21, count 0 2006.285.23:36:24.70#ibcon#about to read 5, iclass 21, count 0 2006.285.23:36:24.70#ibcon#read 5, iclass 21, count 0 2006.285.23:36:24.70#ibcon#about to read 6, iclass 21, count 0 2006.285.23:36:24.70#ibcon#read 6, iclass 21, count 0 2006.285.23:36:24.70#ibcon#end of sib2, iclass 21, count 0 2006.285.23:36:24.70#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:36:24.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:36:24.70#ibcon#[25=USB\r\n] 2006.285.23:36:24.70#ibcon#*before write, iclass 21, count 0 2006.285.23:36:24.70#ibcon#enter sib2, iclass 21, count 0 2006.285.23:36:24.70#ibcon#flushed, iclass 21, count 0 2006.285.23:36:24.70#ibcon#about to write, iclass 21, count 0 2006.285.23:36:24.70#ibcon#wrote, iclass 21, count 0 2006.285.23:36:24.70#ibcon#about to read 3, iclass 21, count 0 2006.285.23:36:24.73#ibcon#read 3, iclass 21, count 0 2006.285.23:36:24.73#ibcon#about to read 4, iclass 21, count 0 2006.285.23:36:24.73#ibcon#read 4, iclass 21, count 0 2006.285.23:36:24.73#ibcon#about to read 5, iclass 21, count 0 2006.285.23:36:24.73#ibcon#read 5, iclass 21, count 0 2006.285.23:36:24.73#ibcon#about to read 6, iclass 21, count 0 2006.285.23:36:24.73#ibcon#read 6, iclass 21, count 0 2006.285.23:36:24.73#ibcon#end of sib2, iclass 21, count 0 2006.285.23:36:24.73#ibcon#*after write, iclass 21, count 0 2006.285.23:36:24.73#ibcon#*before return 0, iclass 21, count 0 2006.285.23:36:24.73#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:36:24.73#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:36:24.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:36:24.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:36:24.73$vck44/valo=7,864.99 2006.285.23:36:24.73#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.23:36:24.73#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.23:36:24.73#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:24.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:36:24.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:36:24.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:36:24.73#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:36:24.73#ibcon#first serial, iclass 23, count 0 2006.285.23:36:24.73#ibcon#enter sib2, iclass 23, count 0 2006.285.23:36:24.73#ibcon#flushed, iclass 23, count 0 2006.285.23:36:24.73#ibcon#about to write, iclass 23, count 0 2006.285.23:36:24.73#ibcon#wrote, iclass 23, count 0 2006.285.23:36:24.73#ibcon#about to read 3, iclass 23, count 0 2006.285.23:36:24.75#ibcon#read 3, iclass 23, count 0 2006.285.23:36:24.75#ibcon#about to read 4, iclass 23, count 0 2006.285.23:36:24.75#ibcon#read 4, iclass 23, count 0 2006.285.23:36:24.75#ibcon#about to read 5, iclass 23, count 0 2006.285.23:36:24.75#ibcon#read 5, iclass 23, count 0 2006.285.23:36:24.75#ibcon#about to read 6, iclass 23, count 0 2006.285.23:36:24.75#ibcon#read 6, iclass 23, count 0 2006.285.23:36:24.75#ibcon#end of sib2, iclass 23, count 0 2006.285.23:36:24.75#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:36:24.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:36:24.75#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.23:36:24.75#ibcon#*before write, iclass 23, count 0 2006.285.23:36:24.75#ibcon#enter sib2, iclass 23, count 0 2006.285.23:36:24.75#ibcon#flushed, iclass 23, count 0 2006.285.23:36:24.75#ibcon#about to write, iclass 23, count 0 2006.285.23:36:24.75#ibcon#wrote, iclass 23, count 0 2006.285.23:36:24.75#ibcon#about to read 3, iclass 23, count 0 2006.285.23:36:24.79#ibcon#read 3, iclass 23, count 0 2006.285.23:36:24.79#ibcon#about to read 4, iclass 23, count 0 2006.285.23:36:24.79#ibcon#read 4, iclass 23, count 0 2006.285.23:36:24.79#ibcon#about to read 5, iclass 23, count 0 2006.285.23:36:24.79#ibcon#read 5, iclass 23, count 0 2006.285.23:36:24.79#ibcon#about to read 6, iclass 23, count 0 2006.285.23:36:24.79#ibcon#read 6, iclass 23, count 0 2006.285.23:36:24.79#ibcon#end of sib2, iclass 23, count 0 2006.285.23:36:24.79#ibcon#*after write, iclass 23, count 0 2006.285.23:36:24.79#ibcon#*before return 0, iclass 23, count 0 2006.285.23:36:24.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:36:24.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:36:24.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:36:24.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:36:24.79$vck44/va=7,4 2006.285.23:36:24.79#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.23:36:24.79#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.23:36:24.79#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:24.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:36:24.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:36:24.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:36:24.85#ibcon#enter wrdev, iclass 25, count 2 2006.285.23:36:24.85#ibcon#first serial, iclass 25, count 2 2006.285.23:36:24.85#ibcon#enter sib2, iclass 25, count 2 2006.285.23:36:24.85#ibcon#flushed, iclass 25, count 2 2006.285.23:36:24.85#ibcon#about to write, iclass 25, count 2 2006.285.23:36:24.85#ibcon#wrote, iclass 25, count 2 2006.285.23:36:24.85#ibcon#about to read 3, iclass 25, count 2 2006.285.23:36:24.87#ibcon#read 3, iclass 25, count 2 2006.285.23:36:24.87#ibcon#about to read 4, iclass 25, count 2 2006.285.23:36:24.87#ibcon#read 4, iclass 25, count 2 2006.285.23:36:24.87#ibcon#about to read 5, iclass 25, count 2 2006.285.23:36:24.87#ibcon#read 5, iclass 25, count 2 2006.285.23:36:24.87#ibcon#about to read 6, iclass 25, count 2 2006.285.23:36:24.87#ibcon#read 6, iclass 25, count 2 2006.285.23:36:24.87#ibcon#end of sib2, iclass 25, count 2 2006.285.23:36:24.87#ibcon#*mode == 0, iclass 25, count 2 2006.285.23:36:24.87#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.23:36:24.87#ibcon#[25=AT07-04\r\n] 2006.285.23:36:24.87#ibcon#*before write, iclass 25, count 2 2006.285.23:36:24.87#ibcon#enter sib2, iclass 25, count 2 2006.285.23:36:24.87#ibcon#flushed, iclass 25, count 2 2006.285.23:36:24.87#ibcon#about to write, iclass 25, count 2 2006.285.23:36:24.87#ibcon#wrote, iclass 25, count 2 2006.285.23:36:24.87#ibcon#about to read 3, iclass 25, count 2 2006.285.23:36:24.90#ibcon#read 3, iclass 25, count 2 2006.285.23:36:24.90#ibcon#about to read 4, iclass 25, count 2 2006.285.23:36:24.90#ibcon#read 4, iclass 25, count 2 2006.285.23:36:24.90#ibcon#about to read 5, iclass 25, count 2 2006.285.23:36:24.90#ibcon#read 5, iclass 25, count 2 2006.285.23:36:24.90#ibcon#about to read 6, iclass 25, count 2 2006.285.23:36:24.90#ibcon#read 6, iclass 25, count 2 2006.285.23:36:24.90#ibcon#end of sib2, iclass 25, count 2 2006.285.23:36:24.90#ibcon#*after write, iclass 25, count 2 2006.285.23:36:24.90#ibcon#*before return 0, iclass 25, count 2 2006.285.23:36:24.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:36:24.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:36:24.90#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.23:36:24.90#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:24.90#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:36:25.02#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:36:25.02#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:36:25.02#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:36:25.02#ibcon#first serial, iclass 25, count 0 2006.285.23:36:25.02#ibcon#enter sib2, iclass 25, count 0 2006.285.23:36:25.02#ibcon#flushed, iclass 25, count 0 2006.285.23:36:25.02#ibcon#about to write, iclass 25, count 0 2006.285.23:36:25.02#ibcon#wrote, iclass 25, count 0 2006.285.23:36:25.02#ibcon#about to read 3, iclass 25, count 0 2006.285.23:36:25.04#ibcon#read 3, iclass 25, count 0 2006.285.23:36:25.04#ibcon#about to read 4, iclass 25, count 0 2006.285.23:36:25.04#ibcon#read 4, iclass 25, count 0 2006.285.23:36:25.04#ibcon#about to read 5, iclass 25, count 0 2006.285.23:36:25.04#ibcon#read 5, iclass 25, count 0 2006.285.23:36:25.04#ibcon#about to read 6, iclass 25, count 0 2006.285.23:36:25.04#ibcon#read 6, iclass 25, count 0 2006.285.23:36:25.04#ibcon#end of sib2, iclass 25, count 0 2006.285.23:36:25.04#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:36:25.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:36:25.04#ibcon#[25=USB\r\n] 2006.285.23:36:25.04#ibcon#*before write, iclass 25, count 0 2006.285.23:36:25.04#ibcon#enter sib2, iclass 25, count 0 2006.285.23:36:25.04#ibcon#flushed, iclass 25, count 0 2006.285.23:36:25.04#ibcon#about to write, iclass 25, count 0 2006.285.23:36:25.04#ibcon#wrote, iclass 25, count 0 2006.285.23:36:25.04#ibcon#about to read 3, iclass 25, count 0 2006.285.23:36:25.07#ibcon#read 3, iclass 25, count 0 2006.285.23:36:25.07#ibcon#about to read 4, iclass 25, count 0 2006.285.23:36:25.07#ibcon#read 4, iclass 25, count 0 2006.285.23:36:25.07#ibcon#about to read 5, iclass 25, count 0 2006.285.23:36:25.07#ibcon#read 5, iclass 25, count 0 2006.285.23:36:25.07#ibcon#about to read 6, iclass 25, count 0 2006.285.23:36:25.07#ibcon#read 6, iclass 25, count 0 2006.285.23:36:25.07#ibcon#end of sib2, iclass 25, count 0 2006.285.23:36:25.07#ibcon#*after write, iclass 25, count 0 2006.285.23:36:25.07#ibcon#*before return 0, iclass 25, count 0 2006.285.23:36:25.07#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:36:25.07#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:36:25.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:36:25.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:36:25.07$vck44/valo=8,884.99 2006.285.23:36:25.07#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.23:36:25.07#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.23:36:25.07#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:25.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:36:25.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:36:25.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:36:25.07#ibcon#enter wrdev, iclass 27, count 0 2006.285.23:36:25.07#ibcon#first serial, iclass 27, count 0 2006.285.23:36:25.07#ibcon#enter sib2, iclass 27, count 0 2006.285.23:36:25.07#ibcon#flushed, iclass 27, count 0 2006.285.23:36:25.07#ibcon#about to write, iclass 27, count 0 2006.285.23:36:25.07#ibcon#wrote, iclass 27, count 0 2006.285.23:36:25.07#ibcon#about to read 3, iclass 27, count 0 2006.285.23:36:25.09#ibcon#read 3, iclass 27, count 0 2006.285.23:36:25.09#ibcon#about to read 4, iclass 27, count 0 2006.285.23:36:25.09#ibcon#read 4, iclass 27, count 0 2006.285.23:36:25.09#ibcon#about to read 5, iclass 27, count 0 2006.285.23:36:25.09#ibcon#read 5, iclass 27, count 0 2006.285.23:36:25.09#ibcon#about to read 6, iclass 27, count 0 2006.285.23:36:25.09#ibcon#read 6, iclass 27, count 0 2006.285.23:36:25.09#ibcon#end of sib2, iclass 27, count 0 2006.285.23:36:25.09#ibcon#*mode == 0, iclass 27, count 0 2006.285.23:36:25.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.23:36:25.09#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.23:36:25.09#ibcon#*before write, iclass 27, count 0 2006.285.23:36:25.09#ibcon#enter sib2, iclass 27, count 0 2006.285.23:36:25.09#ibcon#flushed, iclass 27, count 0 2006.285.23:36:25.09#ibcon#about to write, iclass 27, count 0 2006.285.23:36:25.09#ibcon#wrote, iclass 27, count 0 2006.285.23:36:25.09#ibcon#about to read 3, iclass 27, count 0 2006.285.23:36:25.13#ibcon#read 3, iclass 27, count 0 2006.285.23:36:25.13#ibcon#about to read 4, iclass 27, count 0 2006.285.23:36:25.13#ibcon#read 4, iclass 27, count 0 2006.285.23:36:25.13#ibcon#about to read 5, iclass 27, count 0 2006.285.23:36:25.13#ibcon#read 5, iclass 27, count 0 2006.285.23:36:25.13#ibcon#about to read 6, iclass 27, count 0 2006.285.23:36:25.13#ibcon#read 6, iclass 27, count 0 2006.285.23:36:25.13#ibcon#end of sib2, iclass 27, count 0 2006.285.23:36:25.13#ibcon#*after write, iclass 27, count 0 2006.285.23:36:25.13#ibcon#*before return 0, iclass 27, count 0 2006.285.23:36:25.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:36:25.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:36:25.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.23:36:25.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.23:36:25.13$vck44/va=8,3 2006.285.23:36:25.13#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.23:36:25.13#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.23:36:25.13#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:25.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:36:25.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:36:25.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:36:25.19#ibcon#enter wrdev, iclass 29, count 2 2006.285.23:36:25.19#ibcon#first serial, iclass 29, count 2 2006.285.23:36:25.19#ibcon#enter sib2, iclass 29, count 2 2006.285.23:36:25.19#ibcon#flushed, iclass 29, count 2 2006.285.23:36:25.19#ibcon#about to write, iclass 29, count 2 2006.285.23:36:25.19#ibcon#wrote, iclass 29, count 2 2006.285.23:36:25.19#ibcon#about to read 3, iclass 29, count 2 2006.285.23:36:25.21#ibcon#read 3, iclass 29, count 2 2006.285.23:36:25.21#ibcon#about to read 4, iclass 29, count 2 2006.285.23:36:25.21#ibcon#read 4, iclass 29, count 2 2006.285.23:36:25.21#ibcon#about to read 5, iclass 29, count 2 2006.285.23:36:25.21#ibcon#read 5, iclass 29, count 2 2006.285.23:36:25.21#ibcon#about to read 6, iclass 29, count 2 2006.285.23:36:25.21#ibcon#read 6, iclass 29, count 2 2006.285.23:36:25.21#ibcon#end of sib2, iclass 29, count 2 2006.285.23:36:25.21#ibcon#*mode == 0, iclass 29, count 2 2006.285.23:36:25.21#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.23:36:25.21#ibcon#[25=AT08-03\r\n] 2006.285.23:36:25.21#ibcon#*before write, iclass 29, count 2 2006.285.23:36:25.21#ibcon#enter sib2, iclass 29, count 2 2006.285.23:36:25.21#ibcon#flushed, iclass 29, count 2 2006.285.23:36:25.21#ibcon#about to write, iclass 29, count 2 2006.285.23:36:25.21#ibcon#wrote, iclass 29, count 2 2006.285.23:36:25.21#ibcon#about to read 3, iclass 29, count 2 2006.285.23:36:25.24#ibcon#read 3, iclass 29, count 2 2006.285.23:36:25.24#ibcon#about to read 4, iclass 29, count 2 2006.285.23:36:25.24#ibcon#read 4, iclass 29, count 2 2006.285.23:36:25.24#ibcon#about to read 5, iclass 29, count 2 2006.285.23:36:25.24#ibcon#read 5, iclass 29, count 2 2006.285.23:36:25.24#ibcon#about to read 6, iclass 29, count 2 2006.285.23:36:25.24#ibcon#read 6, iclass 29, count 2 2006.285.23:36:25.24#ibcon#end of sib2, iclass 29, count 2 2006.285.23:36:25.24#ibcon#*after write, iclass 29, count 2 2006.285.23:36:25.24#ibcon#*before return 0, iclass 29, count 2 2006.285.23:36:25.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:36:25.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:36:25.24#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.23:36:25.24#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:25.24#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:36:25.36#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:36:25.36#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:36:25.36#ibcon#enter wrdev, iclass 29, count 0 2006.285.23:36:25.36#ibcon#first serial, iclass 29, count 0 2006.285.23:36:25.36#ibcon#enter sib2, iclass 29, count 0 2006.285.23:36:25.36#ibcon#flushed, iclass 29, count 0 2006.285.23:36:25.36#ibcon#about to write, iclass 29, count 0 2006.285.23:36:25.36#ibcon#wrote, iclass 29, count 0 2006.285.23:36:25.36#ibcon#about to read 3, iclass 29, count 0 2006.285.23:36:25.38#ibcon#read 3, iclass 29, count 0 2006.285.23:36:25.38#ibcon#about to read 4, iclass 29, count 0 2006.285.23:36:25.38#ibcon#read 4, iclass 29, count 0 2006.285.23:36:25.38#ibcon#about to read 5, iclass 29, count 0 2006.285.23:36:25.38#ibcon#read 5, iclass 29, count 0 2006.285.23:36:25.38#ibcon#about to read 6, iclass 29, count 0 2006.285.23:36:25.38#ibcon#read 6, iclass 29, count 0 2006.285.23:36:25.38#ibcon#end of sib2, iclass 29, count 0 2006.285.23:36:25.38#ibcon#*mode == 0, iclass 29, count 0 2006.285.23:36:25.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.23:36:25.38#ibcon#[25=USB\r\n] 2006.285.23:36:25.38#ibcon#*before write, iclass 29, count 0 2006.285.23:36:25.38#ibcon#enter sib2, iclass 29, count 0 2006.285.23:36:25.38#ibcon#flushed, iclass 29, count 0 2006.285.23:36:25.38#ibcon#about to write, iclass 29, count 0 2006.285.23:36:25.38#ibcon#wrote, iclass 29, count 0 2006.285.23:36:25.38#ibcon#about to read 3, iclass 29, count 0 2006.285.23:36:25.41#ibcon#read 3, iclass 29, count 0 2006.285.23:36:25.41#ibcon#about to read 4, iclass 29, count 0 2006.285.23:36:25.41#ibcon#read 4, iclass 29, count 0 2006.285.23:36:25.41#ibcon#about to read 5, iclass 29, count 0 2006.285.23:36:25.41#ibcon#read 5, iclass 29, count 0 2006.285.23:36:25.41#ibcon#about to read 6, iclass 29, count 0 2006.285.23:36:25.41#ibcon#read 6, iclass 29, count 0 2006.285.23:36:25.41#ibcon#end of sib2, iclass 29, count 0 2006.285.23:36:25.41#ibcon#*after write, iclass 29, count 0 2006.285.23:36:25.41#ibcon#*before return 0, iclass 29, count 0 2006.285.23:36:25.41#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:36:25.41#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:36:25.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.23:36:25.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.23:36:25.41$vck44/vblo=1,629.99 2006.285.23:36:25.41#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.23:36:25.41#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.23:36:25.41#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:25.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:36:25.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:36:25.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:36:25.41#ibcon#enter wrdev, iclass 31, count 0 2006.285.23:36:25.41#ibcon#first serial, iclass 31, count 0 2006.285.23:36:25.41#ibcon#enter sib2, iclass 31, count 0 2006.285.23:36:25.41#ibcon#flushed, iclass 31, count 0 2006.285.23:36:25.41#ibcon#about to write, iclass 31, count 0 2006.285.23:36:25.41#ibcon#wrote, iclass 31, count 0 2006.285.23:36:25.41#ibcon#about to read 3, iclass 31, count 0 2006.285.23:36:25.43#ibcon#read 3, iclass 31, count 0 2006.285.23:36:25.43#ibcon#about to read 4, iclass 31, count 0 2006.285.23:36:25.43#ibcon#read 4, iclass 31, count 0 2006.285.23:36:25.43#ibcon#about to read 5, iclass 31, count 0 2006.285.23:36:25.43#ibcon#read 5, iclass 31, count 0 2006.285.23:36:25.43#ibcon#about to read 6, iclass 31, count 0 2006.285.23:36:25.43#ibcon#read 6, iclass 31, count 0 2006.285.23:36:25.43#ibcon#end of sib2, iclass 31, count 0 2006.285.23:36:25.43#ibcon#*mode == 0, iclass 31, count 0 2006.285.23:36:25.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.23:36:25.43#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.23:36:25.43#ibcon#*before write, iclass 31, count 0 2006.285.23:36:25.43#ibcon#enter sib2, iclass 31, count 0 2006.285.23:36:25.43#ibcon#flushed, iclass 31, count 0 2006.285.23:36:25.43#ibcon#about to write, iclass 31, count 0 2006.285.23:36:25.43#ibcon#wrote, iclass 31, count 0 2006.285.23:36:25.43#ibcon#about to read 3, iclass 31, count 0 2006.285.23:36:25.47#ibcon#read 3, iclass 31, count 0 2006.285.23:36:25.47#ibcon#about to read 4, iclass 31, count 0 2006.285.23:36:25.47#ibcon#read 4, iclass 31, count 0 2006.285.23:36:25.47#ibcon#about to read 5, iclass 31, count 0 2006.285.23:36:25.47#ibcon#read 5, iclass 31, count 0 2006.285.23:36:25.47#ibcon#about to read 6, iclass 31, count 0 2006.285.23:36:25.47#ibcon#read 6, iclass 31, count 0 2006.285.23:36:25.47#ibcon#end of sib2, iclass 31, count 0 2006.285.23:36:25.47#ibcon#*after write, iclass 31, count 0 2006.285.23:36:25.47#ibcon#*before return 0, iclass 31, count 0 2006.285.23:36:25.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:36:25.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:36:25.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.23:36:25.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.23:36:25.47$vck44/vb=1,4 2006.285.23:36:25.47#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.23:36:25.47#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.23:36:25.47#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:25.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:36:25.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:36:25.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:36:25.47#ibcon#enter wrdev, iclass 33, count 2 2006.285.23:36:25.47#ibcon#first serial, iclass 33, count 2 2006.285.23:36:25.47#ibcon#enter sib2, iclass 33, count 2 2006.285.23:36:25.47#ibcon#flushed, iclass 33, count 2 2006.285.23:36:25.47#ibcon#about to write, iclass 33, count 2 2006.285.23:36:25.47#ibcon#wrote, iclass 33, count 2 2006.285.23:36:25.47#ibcon#about to read 3, iclass 33, count 2 2006.285.23:36:25.49#ibcon#read 3, iclass 33, count 2 2006.285.23:36:25.49#ibcon#about to read 4, iclass 33, count 2 2006.285.23:36:25.49#ibcon#read 4, iclass 33, count 2 2006.285.23:36:25.49#ibcon#about to read 5, iclass 33, count 2 2006.285.23:36:25.49#ibcon#read 5, iclass 33, count 2 2006.285.23:36:25.49#ibcon#about to read 6, iclass 33, count 2 2006.285.23:36:25.49#ibcon#read 6, iclass 33, count 2 2006.285.23:36:25.49#ibcon#end of sib2, iclass 33, count 2 2006.285.23:36:25.49#ibcon#*mode == 0, iclass 33, count 2 2006.285.23:36:25.49#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.23:36:25.49#ibcon#[27=AT01-04\r\n] 2006.285.23:36:25.49#ibcon#*before write, iclass 33, count 2 2006.285.23:36:25.49#ibcon#enter sib2, iclass 33, count 2 2006.285.23:36:25.49#ibcon#flushed, iclass 33, count 2 2006.285.23:36:25.49#ibcon#about to write, iclass 33, count 2 2006.285.23:36:25.49#ibcon#wrote, iclass 33, count 2 2006.285.23:36:25.49#ibcon#about to read 3, iclass 33, count 2 2006.285.23:36:25.52#ibcon#read 3, iclass 33, count 2 2006.285.23:36:25.52#ibcon#about to read 4, iclass 33, count 2 2006.285.23:36:25.52#ibcon#read 4, iclass 33, count 2 2006.285.23:36:25.52#ibcon#about to read 5, iclass 33, count 2 2006.285.23:36:25.52#ibcon#read 5, iclass 33, count 2 2006.285.23:36:25.52#ibcon#about to read 6, iclass 33, count 2 2006.285.23:36:25.52#ibcon#read 6, iclass 33, count 2 2006.285.23:36:25.52#ibcon#end of sib2, iclass 33, count 2 2006.285.23:36:25.52#ibcon#*after write, iclass 33, count 2 2006.285.23:36:25.52#ibcon#*before return 0, iclass 33, count 2 2006.285.23:36:25.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:36:25.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:36:25.52#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.23:36:25.52#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:25.52#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:36:25.64#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:36:25.64#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:36:25.64#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:36:25.64#ibcon#first serial, iclass 33, count 0 2006.285.23:36:25.64#ibcon#enter sib2, iclass 33, count 0 2006.285.23:36:25.64#ibcon#flushed, iclass 33, count 0 2006.285.23:36:25.64#ibcon#about to write, iclass 33, count 0 2006.285.23:36:25.64#ibcon#wrote, iclass 33, count 0 2006.285.23:36:25.64#ibcon#about to read 3, iclass 33, count 0 2006.285.23:36:25.66#ibcon#read 3, iclass 33, count 0 2006.285.23:36:25.66#ibcon#about to read 4, iclass 33, count 0 2006.285.23:36:25.66#ibcon#read 4, iclass 33, count 0 2006.285.23:36:25.66#ibcon#about to read 5, iclass 33, count 0 2006.285.23:36:25.66#ibcon#read 5, iclass 33, count 0 2006.285.23:36:25.66#ibcon#about to read 6, iclass 33, count 0 2006.285.23:36:25.66#ibcon#read 6, iclass 33, count 0 2006.285.23:36:25.66#ibcon#end of sib2, iclass 33, count 0 2006.285.23:36:25.66#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:36:25.66#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:36:25.66#ibcon#[27=USB\r\n] 2006.285.23:36:25.66#ibcon#*before write, iclass 33, count 0 2006.285.23:36:25.66#ibcon#enter sib2, iclass 33, count 0 2006.285.23:36:25.66#ibcon#flushed, iclass 33, count 0 2006.285.23:36:25.66#ibcon#about to write, iclass 33, count 0 2006.285.23:36:25.66#ibcon#wrote, iclass 33, count 0 2006.285.23:36:25.66#ibcon#about to read 3, iclass 33, count 0 2006.285.23:36:25.69#ibcon#read 3, iclass 33, count 0 2006.285.23:36:25.69#ibcon#about to read 4, iclass 33, count 0 2006.285.23:36:25.69#ibcon#read 4, iclass 33, count 0 2006.285.23:36:25.69#ibcon#about to read 5, iclass 33, count 0 2006.285.23:36:25.69#ibcon#read 5, iclass 33, count 0 2006.285.23:36:25.69#ibcon#about to read 6, iclass 33, count 0 2006.285.23:36:25.69#ibcon#read 6, iclass 33, count 0 2006.285.23:36:25.69#ibcon#end of sib2, iclass 33, count 0 2006.285.23:36:25.69#ibcon#*after write, iclass 33, count 0 2006.285.23:36:25.69#ibcon#*before return 0, iclass 33, count 0 2006.285.23:36:25.69#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:36:25.69#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:36:25.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:36:25.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:36:25.69$vck44/vblo=2,634.99 2006.285.23:36:25.69#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.23:36:25.69#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.23:36:25.69#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:25.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:36:25.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:36:25.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:36:25.69#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:36:25.69#ibcon#first serial, iclass 35, count 0 2006.285.23:36:25.69#ibcon#enter sib2, iclass 35, count 0 2006.285.23:36:25.69#ibcon#flushed, iclass 35, count 0 2006.285.23:36:25.69#ibcon#about to write, iclass 35, count 0 2006.285.23:36:25.69#ibcon#wrote, iclass 35, count 0 2006.285.23:36:25.69#ibcon#about to read 3, iclass 35, count 0 2006.285.23:36:25.71#ibcon#read 3, iclass 35, count 0 2006.285.23:36:25.71#ibcon#about to read 4, iclass 35, count 0 2006.285.23:36:25.71#ibcon#read 4, iclass 35, count 0 2006.285.23:36:25.71#ibcon#about to read 5, iclass 35, count 0 2006.285.23:36:25.71#ibcon#read 5, iclass 35, count 0 2006.285.23:36:25.71#ibcon#about to read 6, iclass 35, count 0 2006.285.23:36:25.71#ibcon#read 6, iclass 35, count 0 2006.285.23:36:25.71#ibcon#end of sib2, iclass 35, count 0 2006.285.23:36:25.71#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:36:25.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:36:25.71#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.23:36:25.71#ibcon#*before write, iclass 35, count 0 2006.285.23:36:25.71#ibcon#enter sib2, iclass 35, count 0 2006.285.23:36:25.71#ibcon#flushed, iclass 35, count 0 2006.285.23:36:25.71#ibcon#about to write, iclass 35, count 0 2006.285.23:36:25.71#ibcon#wrote, iclass 35, count 0 2006.285.23:36:25.71#ibcon#about to read 3, iclass 35, count 0 2006.285.23:36:25.75#ibcon#read 3, iclass 35, count 0 2006.285.23:36:25.75#ibcon#about to read 4, iclass 35, count 0 2006.285.23:36:25.75#ibcon#read 4, iclass 35, count 0 2006.285.23:36:25.75#ibcon#about to read 5, iclass 35, count 0 2006.285.23:36:25.75#ibcon#read 5, iclass 35, count 0 2006.285.23:36:25.75#ibcon#about to read 6, iclass 35, count 0 2006.285.23:36:25.75#ibcon#read 6, iclass 35, count 0 2006.285.23:36:25.75#ibcon#end of sib2, iclass 35, count 0 2006.285.23:36:25.75#ibcon#*after write, iclass 35, count 0 2006.285.23:36:25.75#ibcon#*before return 0, iclass 35, count 0 2006.285.23:36:25.75#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:36:25.75#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:36:25.75#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:36:25.75#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:36:25.75$vck44/vb=2,5 2006.285.23:36:25.75#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.23:36:25.75#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.23:36:25.75#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:25.75#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:36:25.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:36:25.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:36:25.81#ibcon#enter wrdev, iclass 37, count 2 2006.285.23:36:25.81#ibcon#first serial, iclass 37, count 2 2006.285.23:36:25.81#ibcon#enter sib2, iclass 37, count 2 2006.285.23:36:25.81#ibcon#flushed, iclass 37, count 2 2006.285.23:36:25.81#ibcon#about to write, iclass 37, count 2 2006.285.23:36:25.81#ibcon#wrote, iclass 37, count 2 2006.285.23:36:25.81#ibcon#about to read 3, iclass 37, count 2 2006.285.23:36:25.83#ibcon#read 3, iclass 37, count 2 2006.285.23:36:25.83#ibcon#about to read 4, iclass 37, count 2 2006.285.23:36:25.83#ibcon#read 4, iclass 37, count 2 2006.285.23:36:25.83#ibcon#about to read 5, iclass 37, count 2 2006.285.23:36:25.83#ibcon#read 5, iclass 37, count 2 2006.285.23:36:25.83#ibcon#about to read 6, iclass 37, count 2 2006.285.23:36:25.83#ibcon#read 6, iclass 37, count 2 2006.285.23:36:25.83#ibcon#end of sib2, iclass 37, count 2 2006.285.23:36:25.83#ibcon#*mode == 0, iclass 37, count 2 2006.285.23:36:25.83#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.23:36:25.83#ibcon#[27=AT02-05\r\n] 2006.285.23:36:25.83#ibcon#*before write, iclass 37, count 2 2006.285.23:36:25.83#ibcon#enter sib2, iclass 37, count 2 2006.285.23:36:25.83#ibcon#flushed, iclass 37, count 2 2006.285.23:36:25.83#ibcon#about to write, iclass 37, count 2 2006.285.23:36:25.83#ibcon#wrote, iclass 37, count 2 2006.285.23:36:25.83#ibcon#about to read 3, iclass 37, count 2 2006.285.23:36:25.86#ibcon#read 3, iclass 37, count 2 2006.285.23:36:25.86#ibcon#about to read 4, iclass 37, count 2 2006.285.23:36:25.86#ibcon#read 4, iclass 37, count 2 2006.285.23:36:25.86#ibcon#about to read 5, iclass 37, count 2 2006.285.23:36:25.86#ibcon#read 5, iclass 37, count 2 2006.285.23:36:25.86#ibcon#about to read 6, iclass 37, count 2 2006.285.23:36:25.86#ibcon#read 6, iclass 37, count 2 2006.285.23:36:25.86#ibcon#end of sib2, iclass 37, count 2 2006.285.23:36:25.86#ibcon#*after write, iclass 37, count 2 2006.285.23:36:25.86#ibcon#*before return 0, iclass 37, count 2 2006.285.23:36:25.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:36:25.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:36:25.86#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.23:36:25.86#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:25.86#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:36:25.98#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:36:25.98#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:36:25.98#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:36:25.98#ibcon#first serial, iclass 37, count 0 2006.285.23:36:25.98#ibcon#enter sib2, iclass 37, count 0 2006.285.23:36:25.98#ibcon#flushed, iclass 37, count 0 2006.285.23:36:25.98#ibcon#about to write, iclass 37, count 0 2006.285.23:36:25.98#ibcon#wrote, iclass 37, count 0 2006.285.23:36:25.98#ibcon#about to read 3, iclass 37, count 0 2006.285.23:36:26.00#ibcon#read 3, iclass 37, count 0 2006.285.23:36:26.00#ibcon#about to read 4, iclass 37, count 0 2006.285.23:36:26.00#ibcon#read 4, iclass 37, count 0 2006.285.23:36:26.00#ibcon#about to read 5, iclass 37, count 0 2006.285.23:36:26.00#ibcon#read 5, iclass 37, count 0 2006.285.23:36:26.00#ibcon#about to read 6, iclass 37, count 0 2006.285.23:36:26.00#ibcon#read 6, iclass 37, count 0 2006.285.23:36:26.00#ibcon#end of sib2, iclass 37, count 0 2006.285.23:36:26.00#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:36:26.00#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:36:26.00#ibcon#[27=USB\r\n] 2006.285.23:36:26.00#ibcon#*before write, iclass 37, count 0 2006.285.23:36:26.00#ibcon#enter sib2, iclass 37, count 0 2006.285.23:36:26.00#ibcon#flushed, iclass 37, count 0 2006.285.23:36:26.00#ibcon#about to write, iclass 37, count 0 2006.285.23:36:26.00#ibcon#wrote, iclass 37, count 0 2006.285.23:36:26.00#ibcon#about to read 3, iclass 37, count 0 2006.285.23:36:26.03#ibcon#read 3, iclass 37, count 0 2006.285.23:36:26.03#ibcon#about to read 4, iclass 37, count 0 2006.285.23:36:26.03#ibcon#read 4, iclass 37, count 0 2006.285.23:36:26.03#ibcon#about to read 5, iclass 37, count 0 2006.285.23:36:26.03#ibcon#read 5, iclass 37, count 0 2006.285.23:36:26.03#ibcon#about to read 6, iclass 37, count 0 2006.285.23:36:26.03#ibcon#read 6, iclass 37, count 0 2006.285.23:36:26.03#ibcon#end of sib2, iclass 37, count 0 2006.285.23:36:26.03#ibcon#*after write, iclass 37, count 0 2006.285.23:36:26.03#ibcon#*before return 0, iclass 37, count 0 2006.285.23:36:26.03#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:36:26.03#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:36:26.03#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:36:26.03#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:36:26.03$vck44/vblo=3,649.99 2006.285.23:36:26.03#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.23:36:26.03#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.23:36:26.03#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:26.03#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:36:26.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:36:26.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:36:26.03#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:36:26.03#ibcon#first serial, iclass 39, count 0 2006.285.23:36:26.03#ibcon#enter sib2, iclass 39, count 0 2006.285.23:36:26.03#ibcon#flushed, iclass 39, count 0 2006.285.23:36:26.03#ibcon#about to write, iclass 39, count 0 2006.285.23:36:26.03#ibcon#wrote, iclass 39, count 0 2006.285.23:36:26.03#ibcon#about to read 3, iclass 39, count 0 2006.285.23:36:26.05#ibcon#read 3, iclass 39, count 0 2006.285.23:36:26.05#ibcon#about to read 4, iclass 39, count 0 2006.285.23:36:26.05#ibcon#read 4, iclass 39, count 0 2006.285.23:36:26.05#ibcon#about to read 5, iclass 39, count 0 2006.285.23:36:26.05#ibcon#read 5, iclass 39, count 0 2006.285.23:36:26.05#ibcon#about to read 6, iclass 39, count 0 2006.285.23:36:26.05#ibcon#read 6, iclass 39, count 0 2006.285.23:36:26.05#ibcon#end of sib2, iclass 39, count 0 2006.285.23:36:26.05#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:36:26.05#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:36:26.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.23:36:26.05#ibcon#*before write, iclass 39, count 0 2006.285.23:36:26.05#ibcon#enter sib2, iclass 39, count 0 2006.285.23:36:26.05#ibcon#flushed, iclass 39, count 0 2006.285.23:36:26.05#ibcon#about to write, iclass 39, count 0 2006.285.23:36:26.05#ibcon#wrote, iclass 39, count 0 2006.285.23:36:26.05#ibcon#about to read 3, iclass 39, count 0 2006.285.23:36:26.09#ibcon#read 3, iclass 39, count 0 2006.285.23:36:26.09#ibcon#about to read 4, iclass 39, count 0 2006.285.23:36:26.09#ibcon#read 4, iclass 39, count 0 2006.285.23:36:26.09#ibcon#about to read 5, iclass 39, count 0 2006.285.23:36:26.09#ibcon#read 5, iclass 39, count 0 2006.285.23:36:26.09#ibcon#about to read 6, iclass 39, count 0 2006.285.23:36:26.09#ibcon#read 6, iclass 39, count 0 2006.285.23:36:26.09#ibcon#end of sib2, iclass 39, count 0 2006.285.23:36:26.09#ibcon#*after write, iclass 39, count 0 2006.285.23:36:26.09#ibcon#*before return 0, iclass 39, count 0 2006.285.23:36:26.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:36:26.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:36:26.09#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:36:26.09#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:36:26.09$vck44/vb=3,4 2006.285.23:36:26.09#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.23:36:26.09#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.23:36:26.09#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:26.09#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:36:26.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:36:26.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:36:26.15#ibcon#enter wrdev, iclass 3, count 2 2006.285.23:36:26.15#ibcon#first serial, iclass 3, count 2 2006.285.23:36:26.15#ibcon#enter sib2, iclass 3, count 2 2006.285.23:36:26.15#ibcon#flushed, iclass 3, count 2 2006.285.23:36:26.15#ibcon#about to write, iclass 3, count 2 2006.285.23:36:26.15#ibcon#wrote, iclass 3, count 2 2006.285.23:36:26.15#ibcon#about to read 3, iclass 3, count 2 2006.285.23:36:26.17#ibcon#read 3, iclass 3, count 2 2006.285.23:36:26.17#ibcon#about to read 4, iclass 3, count 2 2006.285.23:36:26.17#ibcon#read 4, iclass 3, count 2 2006.285.23:36:26.17#ibcon#about to read 5, iclass 3, count 2 2006.285.23:36:26.17#ibcon#read 5, iclass 3, count 2 2006.285.23:36:26.17#ibcon#about to read 6, iclass 3, count 2 2006.285.23:36:26.17#ibcon#read 6, iclass 3, count 2 2006.285.23:36:26.17#ibcon#end of sib2, iclass 3, count 2 2006.285.23:36:26.17#ibcon#*mode == 0, iclass 3, count 2 2006.285.23:36:26.17#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.23:36:26.17#ibcon#[27=AT03-04\r\n] 2006.285.23:36:26.17#ibcon#*before write, iclass 3, count 2 2006.285.23:36:26.17#ibcon#enter sib2, iclass 3, count 2 2006.285.23:36:26.17#ibcon#flushed, iclass 3, count 2 2006.285.23:36:26.17#ibcon#about to write, iclass 3, count 2 2006.285.23:36:26.17#ibcon#wrote, iclass 3, count 2 2006.285.23:36:26.17#ibcon#about to read 3, iclass 3, count 2 2006.285.23:36:26.20#ibcon#read 3, iclass 3, count 2 2006.285.23:36:26.20#ibcon#about to read 4, iclass 3, count 2 2006.285.23:36:26.20#ibcon#read 4, iclass 3, count 2 2006.285.23:36:26.20#ibcon#about to read 5, iclass 3, count 2 2006.285.23:36:26.20#ibcon#read 5, iclass 3, count 2 2006.285.23:36:26.20#ibcon#about to read 6, iclass 3, count 2 2006.285.23:36:26.20#ibcon#read 6, iclass 3, count 2 2006.285.23:36:26.20#ibcon#end of sib2, iclass 3, count 2 2006.285.23:36:26.20#ibcon#*after write, iclass 3, count 2 2006.285.23:36:26.20#ibcon#*before return 0, iclass 3, count 2 2006.285.23:36:26.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:36:26.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:36:26.20#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.23:36:26.20#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:26.20#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:36:26.32#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:36:26.32#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:36:26.32#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:36:26.32#ibcon#first serial, iclass 3, count 0 2006.285.23:36:26.32#ibcon#enter sib2, iclass 3, count 0 2006.285.23:36:26.32#ibcon#flushed, iclass 3, count 0 2006.285.23:36:26.32#ibcon#about to write, iclass 3, count 0 2006.285.23:36:26.32#ibcon#wrote, iclass 3, count 0 2006.285.23:36:26.32#ibcon#about to read 3, iclass 3, count 0 2006.285.23:36:26.34#ibcon#read 3, iclass 3, count 0 2006.285.23:36:26.34#ibcon#about to read 4, iclass 3, count 0 2006.285.23:36:26.34#ibcon#read 4, iclass 3, count 0 2006.285.23:36:26.34#ibcon#about to read 5, iclass 3, count 0 2006.285.23:36:26.34#ibcon#read 5, iclass 3, count 0 2006.285.23:36:26.34#ibcon#about to read 6, iclass 3, count 0 2006.285.23:36:26.34#ibcon#read 6, iclass 3, count 0 2006.285.23:36:26.34#ibcon#end of sib2, iclass 3, count 0 2006.285.23:36:26.34#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:36:26.34#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:36:26.34#ibcon#[27=USB\r\n] 2006.285.23:36:26.34#ibcon#*before write, iclass 3, count 0 2006.285.23:36:26.34#ibcon#enter sib2, iclass 3, count 0 2006.285.23:36:26.34#ibcon#flushed, iclass 3, count 0 2006.285.23:36:26.34#ibcon#about to write, iclass 3, count 0 2006.285.23:36:26.34#ibcon#wrote, iclass 3, count 0 2006.285.23:36:26.34#ibcon#about to read 3, iclass 3, count 0 2006.285.23:36:26.37#ibcon#read 3, iclass 3, count 0 2006.285.23:36:26.37#ibcon#about to read 4, iclass 3, count 0 2006.285.23:36:26.37#ibcon#read 4, iclass 3, count 0 2006.285.23:36:26.37#ibcon#about to read 5, iclass 3, count 0 2006.285.23:36:26.37#ibcon#read 5, iclass 3, count 0 2006.285.23:36:26.37#ibcon#about to read 6, iclass 3, count 0 2006.285.23:36:26.37#ibcon#read 6, iclass 3, count 0 2006.285.23:36:26.37#ibcon#end of sib2, iclass 3, count 0 2006.285.23:36:26.37#ibcon#*after write, iclass 3, count 0 2006.285.23:36:26.37#ibcon#*before return 0, iclass 3, count 0 2006.285.23:36:26.37#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:36:26.37#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:36:26.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:36:26.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:36:26.37$vck44/vblo=4,679.99 2006.285.23:36:26.37#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.23:36:26.37#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.23:36:26.37#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:26.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:36:26.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:36:26.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:36:26.37#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:36:26.37#ibcon#first serial, iclass 5, count 0 2006.285.23:36:26.37#ibcon#enter sib2, iclass 5, count 0 2006.285.23:36:26.37#ibcon#flushed, iclass 5, count 0 2006.285.23:36:26.37#ibcon#about to write, iclass 5, count 0 2006.285.23:36:26.37#ibcon#wrote, iclass 5, count 0 2006.285.23:36:26.37#ibcon#about to read 3, iclass 5, count 0 2006.285.23:36:26.39#ibcon#read 3, iclass 5, count 0 2006.285.23:36:26.39#ibcon#about to read 4, iclass 5, count 0 2006.285.23:36:26.39#ibcon#read 4, iclass 5, count 0 2006.285.23:36:26.39#ibcon#about to read 5, iclass 5, count 0 2006.285.23:36:26.39#ibcon#read 5, iclass 5, count 0 2006.285.23:36:26.39#ibcon#about to read 6, iclass 5, count 0 2006.285.23:36:26.39#ibcon#read 6, iclass 5, count 0 2006.285.23:36:26.39#ibcon#end of sib2, iclass 5, count 0 2006.285.23:36:26.39#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:36:26.39#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:36:26.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:36:26.39#ibcon#*before write, iclass 5, count 0 2006.285.23:36:26.39#ibcon#enter sib2, iclass 5, count 0 2006.285.23:36:26.39#ibcon#flushed, iclass 5, count 0 2006.285.23:36:26.39#ibcon#about to write, iclass 5, count 0 2006.285.23:36:26.39#ibcon#wrote, iclass 5, count 0 2006.285.23:36:26.39#ibcon#about to read 3, iclass 5, count 0 2006.285.23:36:26.43#ibcon#read 3, iclass 5, count 0 2006.285.23:36:26.43#ibcon#about to read 4, iclass 5, count 0 2006.285.23:36:26.43#ibcon#read 4, iclass 5, count 0 2006.285.23:36:26.43#ibcon#about to read 5, iclass 5, count 0 2006.285.23:36:26.43#ibcon#read 5, iclass 5, count 0 2006.285.23:36:26.43#ibcon#about to read 6, iclass 5, count 0 2006.285.23:36:26.43#ibcon#read 6, iclass 5, count 0 2006.285.23:36:26.43#ibcon#end of sib2, iclass 5, count 0 2006.285.23:36:26.43#ibcon#*after write, iclass 5, count 0 2006.285.23:36:26.43#ibcon#*before return 0, iclass 5, count 0 2006.285.23:36:26.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:36:26.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:36:26.43#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:36:26.43#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:36:26.43$vck44/vb=4,5 2006.285.23:36:26.43#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.23:36:26.43#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.23:36:26.43#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:26.43#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:36:26.49#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:36:26.49#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:36:26.49#ibcon#enter wrdev, iclass 7, count 2 2006.285.23:36:26.49#ibcon#first serial, iclass 7, count 2 2006.285.23:36:26.49#ibcon#enter sib2, iclass 7, count 2 2006.285.23:36:26.49#ibcon#flushed, iclass 7, count 2 2006.285.23:36:26.49#ibcon#about to write, iclass 7, count 2 2006.285.23:36:26.49#ibcon#wrote, iclass 7, count 2 2006.285.23:36:26.49#ibcon#about to read 3, iclass 7, count 2 2006.285.23:36:26.51#ibcon#read 3, iclass 7, count 2 2006.285.23:36:26.51#ibcon#about to read 4, iclass 7, count 2 2006.285.23:36:26.51#ibcon#read 4, iclass 7, count 2 2006.285.23:36:26.51#ibcon#about to read 5, iclass 7, count 2 2006.285.23:36:26.51#ibcon#read 5, iclass 7, count 2 2006.285.23:36:26.51#ibcon#about to read 6, iclass 7, count 2 2006.285.23:36:26.51#ibcon#read 6, iclass 7, count 2 2006.285.23:36:26.51#ibcon#end of sib2, iclass 7, count 2 2006.285.23:36:26.51#ibcon#*mode == 0, iclass 7, count 2 2006.285.23:36:26.51#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.23:36:26.51#ibcon#[27=AT04-05\r\n] 2006.285.23:36:26.51#ibcon#*before write, iclass 7, count 2 2006.285.23:36:26.51#ibcon#enter sib2, iclass 7, count 2 2006.285.23:36:26.51#ibcon#flushed, iclass 7, count 2 2006.285.23:36:26.51#ibcon#about to write, iclass 7, count 2 2006.285.23:36:26.51#ibcon#wrote, iclass 7, count 2 2006.285.23:36:26.51#ibcon#about to read 3, iclass 7, count 2 2006.285.23:36:26.54#ibcon#read 3, iclass 7, count 2 2006.285.23:36:26.54#ibcon#about to read 4, iclass 7, count 2 2006.285.23:36:26.54#ibcon#read 4, iclass 7, count 2 2006.285.23:36:26.54#ibcon#about to read 5, iclass 7, count 2 2006.285.23:36:26.54#ibcon#read 5, iclass 7, count 2 2006.285.23:36:26.54#ibcon#about to read 6, iclass 7, count 2 2006.285.23:36:26.54#ibcon#read 6, iclass 7, count 2 2006.285.23:36:26.54#ibcon#end of sib2, iclass 7, count 2 2006.285.23:36:26.54#ibcon#*after write, iclass 7, count 2 2006.285.23:36:26.54#ibcon#*before return 0, iclass 7, count 2 2006.285.23:36:26.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:36:26.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:36:26.54#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.23:36:26.54#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:26.54#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:36:26.66#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:36:26.66#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:36:26.66#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:36:26.66#ibcon#first serial, iclass 7, count 0 2006.285.23:36:26.66#ibcon#enter sib2, iclass 7, count 0 2006.285.23:36:26.66#ibcon#flushed, iclass 7, count 0 2006.285.23:36:26.66#ibcon#about to write, iclass 7, count 0 2006.285.23:36:26.66#ibcon#wrote, iclass 7, count 0 2006.285.23:36:26.66#ibcon#about to read 3, iclass 7, count 0 2006.285.23:36:26.68#ibcon#read 3, iclass 7, count 0 2006.285.23:36:26.68#ibcon#about to read 4, iclass 7, count 0 2006.285.23:36:26.68#ibcon#read 4, iclass 7, count 0 2006.285.23:36:26.68#ibcon#about to read 5, iclass 7, count 0 2006.285.23:36:26.68#ibcon#read 5, iclass 7, count 0 2006.285.23:36:26.68#ibcon#about to read 6, iclass 7, count 0 2006.285.23:36:26.68#ibcon#read 6, iclass 7, count 0 2006.285.23:36:26.68#ibcon#end of sib2, iclass 7, count 0 2006.285.23:36:26.68#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:36:26.68#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:36:26.68#ibcon#[27=USB\r\n] 2006.285.23:36:26.68#ibcon#*before write, iclass 7, count 0 2006.285.23:36:26.68#ibcon#enter sib2, iclass 7, count 0 2006.285.23:36:26.68#ibcon#flushed, iclass 7, count 0 2006.285.23:36:26.68#ibcon#about to write, iclass 7, count 0 2006.285.23:36:26.68#ibcon#wrote, iclass 7, count 0 2006.285.23:36:26.68#ibcon#about to read 3, iclass 7, count 0 2006.285.23:36:26.71#ibcon#read 3, iclass 7, count 0 2006.285.23:36:26.71#ibcon#about to read 4, iclass 7, count 0 2006.285.23:36:26.71#ibcon#read 4, iclass 7, count 0 2006.285.23:36:26.71#ibcon#about to read 5, iclass 7, count 0 2006.285.23:36:26.71#ibcon#read 5, iclass 7, count 0 2006.285.23:36:26.71#ibcon#about to read 6, iclass 7, count 0 2006.285.23:36:26.71#ibcon#read 6, iclass 7, count 0 2006.285.23:36:26.71#ibcon#end of sib2, iclass 7, count 0 2006.285.23:36:26.71#ibcon#*after write, iclass 7, count 0 2006.285.23:36:26.71#ibcon#*before return 0, iclass 7, count 0 2006.285.23:36:26.71#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:36:26.71#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:36:26.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:36:26.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:36:26.71$vck44/vblo=5,709.99 2006.285.23:36:26.71#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.23:36:26.71#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.23:36:26.71#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:26.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:36:26.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:36:26.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:36:26.71#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:36:26.71#ibcon#first serial, iclass 11, count 0 2006.285.23:36:26.71#ibcon#enter sib2, iclass 11, count 0 2006.285.23:36:26.71#ibcon#flushed, iclass 11, count 0 2006.285.23:36:26.71#ibcon#about to write, iclass 11, count 0 2006.285.23:36:26.71#ibcon#wrote, iclass 11, count 0 2006.285.23:36:26.71#ibcon#about to read 3, iclass 11, count 0 2006.285.23:36:26.73#ibcon#read 3, iclass 11, count 0 2006.285.23:36:26.73#ibcon#about to read 4, iclass 11, count 0 2006.285.23:36:26.73#ibcon#read 4, iclass 11, count 0 2006.285.23:36:26.73#ibcon#about to read 5, iclass 11, count 0 2006.285.23:36:26.73#ibcon#read 5, iclass 11, count 0 2006.285.23:36:26.73#ibcon#about to read 6, iclass 11, count 0 2006.285.23:36:26.73#ibcon#read 6, iclass 11, count 0 2006.285.23:36:26.73#ibcon#end of sib2, iclass 11, count 0 2006.285.23:36:26.73#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:36:26.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:36:26.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:36:26.73#ibcon#*before write, iclass 11, count 0 2006.285.23:36:26.73#ibcon#enter sib2, iclass 11, count 0 2006.285.23:36:26.73#ibcon#flushed, iclass 11, count 0 2006.285.23:36:26.73#ibcon#about to write, iclass 11, count 0 2006.285.23:36:26.73#ibcon#wrote, iclass 11, count 0 2006.285.23:36:26.73#ibcon#about to read 3, iclass 11, count 0 2006.285.23:36:26.77#ibcon#read 3, iclass 11, count 0 2006.285.23:36:26.77#ibcon#about to read 4, iclass 11, count 0 2006.285.23:36:26.77#ibcon#read 4, iclass 11, count 0 2006.285.23:36:26.77#ibcon#about to read 5, iclass 11, count 0 2006.285.23:36:26.77#ibcon#read 5, iclass 11, count 0 2006.285.23:36:26.77#ibcon#about to read 6, iclass 11, count 0 2006.285.23:36:26.77#ibcon#read 6, iclass 11, count 0 2006.285.23:36:26.77#ibcon#end of sib2, iclass 11, count 0 2006.285.23:36:26.77#ibcon#*after write, iclass 11, count 0 2006.285.23:36:26.77#ibcon#*before return 0, iclass 11, count 0 2006.285.23:36:26.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:36:26.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:36:26.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:36:26.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:36:26.77$vck44/vb=5,4 2006.285.23:36:26.77#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.23:36:26.77#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.23:36:26.77#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:26.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:36:26.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:36:26.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:36:26.83#ibcon#enter wrdev, iclass 13, count 2 2006.285.23:36:26.83#ibcon#first serial, iclass 13, count 2 2006.285.23:36:26.83#ibcon#enter sib2, iclass 13, count 2 2006.285.23:36:26.83#ibcon#flushed, iclass 13, count 2 2006.285.23:36:26.83#ibcon#about to write, iclass 13, count 2 2006.285.23:36:26.83#ibcon#wrote, iclass 13, count 2 2006.285.23:36:26.83#ibcon#about to read 3, iclass 13, count 2 2006.285.23:36:26.85#ibcon#read 3, iclass 13, count 2 2006.285.23:36:26.85#ibcon#about to read 4, iclass 13, count 2 2006.285.23:36:26.85#ibcon#read 4, iclass 13, count 2 2006.285.23:36:26.85#ibcon#about to read 5, iclass 13, count 2 2006.285.23:36:26.85#ibcon#read 5, iclass 13, count 2 2006.285.23:36:26.85#ibcon#about to read 6, iclass 13, count 2 2006.285.23:36:26.85#ibcon#read 6, iclass 13, count 2 2006.285.23:36:26.85#ibcon#end of sib2, iclass 13, count 2 2006.285.23:36:26.85#ibcon#*mode == 0, iclass 13, count 2 2006.285.23:36:26.85#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.23:36:26.85#ibcon#[27=AT05-04\r\n] 2006.285.23:36:26.85#ibcon#*before write, iclass 13, count 2 2006.285.23:36:26.85#ibcon#enter sib2, iclass 13, count 2 2006.285.23:36:26.85#ibcon#flushed, iclass 13, count 2 2006.285.23:36:26.85#ibcon#about to write, iclass 13, count 2 2006.285.23:36:26.85#ibcon#wrote, iclass 13, count 2 2006.285.23:36:26.85#ibcon#about to read 3, iclass 13, count 2 2006.285.23:36:26.88#ibcon#read 3, iclass 13, count 2 2006.285.23:36:26.88#ibcon#about to read 4, iclass 13, count 2 2006.285.23:36:26.88#ibcon#read 4, iclass 13, count 2 2006.285.23:36:26.88#ibcon#about to read 5, iclass 13, count 2 2006.285.23:36:26.88#ibcon#read 5, iclass 13, count 2 2006.285.23:36:26.88#ibcon#about to read 6, iclass 13, count 2 2006.285.23:36:26.88#ibcon#read 6, iclass 13, count 2 2006.285.23:36:26.88#ibcon#end of sib2, iclass 13, count 2 2006.285.23:36:26.88#ibcon#*after write, iclass 13, count 2 2006.285.23:36:26.88#ibcon#*before return 0, iclass 13, count 2 2006.285.23:36:26.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:36:26.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:36:26.88#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.23:36:26.88#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:26.88#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:36:27.00#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:36:27.00#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:36:27.00#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:36:27.00#ibcon#first serial, iclass 13, count 0 2006.285.23:36:27.00#ibcon#enter sib2, iclass 13, count 0 2006.285.23:36:27.00#ibcon#flushed, iclass 13, count 0 2006.285.23:36:27.00#ibcon#about to write, iclass 13, count 0 2006.285.23:36:27.00#ibcon#wrote, iclass 13, count 0 2006.285.23:36:27.00#ibcon#about to read 3, iclass 13, count 0 2006.285.23:36:27.02#ibcon#read 3, iclass 13, count 0 2006.285.23:36:27.02#ibcon#about to read 4, iclass 13, count 0 2006.285.23:36:27.02#ibcon#read 4, iclass 13, count 0 2006.285.23:36:27.02#ibcon#about to read 5, iclass 13, count 0 2006.285.23:36:27.02#ibcon#read 5, iclass 13, count 0 2006.285.23:36:27.02#ibcon#about to read 6, iclass 13, count 0 2006.285.23:36:27.02#ibcon#read 6, iclass 13, count 0 2006.285.23:36:27.02#ibcon#end of sib2, iclass 13, count 0 2006.285.23:36:27.02#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:36:27.02#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:36:27.02#ibcon#[27=USB\r\n] 2006.285.23:36:27.02#ibcon#*before write, iclass 13, count 0 2006.285.23:36:27.02#ibcon#enter sib2, iclass 13, count 0 2006.285.23:36:27.02#ibcon#flushed, iclass 13, count 0 2006.285.23:36:27.02#ibcon#about to write, iclass 13, count 0 2006.285.23:36:27.02#ibcon#wrote, iclass 13, count 0 2006.285.23:36:27.02#ibcon#about to read 3, iclass 13, count 0 2006.285.23:36:27.05#ibcon#read 3, iclass 13, count 0 2006.285.23:36:27.05#ibcon#about to read 4, iclass 13, count 0 2006.285.23:36:27.05#ibcon#read 4, iclass 13, count 0 2006.285.23:36:27.05#ibcon#about to read 5, iclass 13, count 0 2006.285.23:36:27.05#ibcon#read 5, iclass 13, count 0 2006.285.23:36:27.05#ibcon#about to read 6, iclass 13, count 0 2006.285.23:36:27.05#ibcon#read 6, iclass 13, count 0 2006.285.23:36:27.05#ibcon#end of sib2, iclass 13, count 0 2006.285.23:36:27.05#ibcon#*after write, iclass 13, count 0 2006.285.23:36:27.05#ibcon#*before return 0, iclass 13, count 0 2006.285.23:36:27.05#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:36:27.05#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:36:27.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:36:27.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:36:27.05$vck44/vblo=6,719.99 2006.285.23:36:27.05#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.23:36:27.05#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.23:36:27.05#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:27.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:36:27.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:36:27.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:36:27.05#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:36:27.05#ibcon#first serial, iclass 15, count 0 2006.285.23:36:27.05#ibcon#enter sib2, iclass 15, count 0 2006.285.23:36:27.05#ibcon#flushed, iclass 15, count 0 2006.285.23:36:27.05#ibcon#about to write, iclass 15, count 0 2006.285.23:36:27.05#ibcon#wrote, iclass 15, count 0 2006.285.23:36:27.05#ibcon#about to read 3, iclass 15, count 0 2006.285.23:36:27.07#ibcon#read 3, iclass 15, count 0 2006.285.23:36:27.07#ibcon#about to read 4, iclass 15, count 0 2006.285.23:36:27.07#ibcon#read 4, iclass 15, count 0 2006.285.23:36:27.07#ibcon#about to read 5, iclass 15, count 0 2006.285.23:36:27.07#ibcon#read 5, iclass 15, count 0 2006.285.23:36:27.07#ibcon#about to read 6, iclass 15, count 0 2006.285.23:36:27.07#ibcon#read 6, iclass 15, count 0 2006.285.23:36:27.07#ibcon#end of sib2, iclass 15, count 0 2006.285.23:36:27.07#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:36:27.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:36:27.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:36:27.07#ibcon#*before write, iclass 15, count 0 2006.285.23:36:27.07#ibcon#enter sib2, iclass 15, count 0 2006.285.23:36:27.07#ibcon#flushed, iclass 15, count 0 2006.285.23:36:27.07#ibcon#about to write, iclass 15, count 0 2006.285.23:36:27.07#ibcon#wrote, iclass 15, count 0 2006.285.23:36:27.07#ibcon#about to read 3, iclass 15, count 0 2006.285.23:36:27.11#ibcon#read 3, iclass 15, count 0 2006.285.23:36:27.11#ibcon#about to read 4, iclass 15, count 0 2006.285.23:36:27.11#ibcon#read 4, iclass 15, count 0 2006.285.23:36:27.11#ibcon#about to read 5, iclass 15, count 0 2006.285.23:36:27.11#ibcon#read 5, iclass 15, count 0 2006.285.23:36:27.11#ibcon#about to read 6, iclass 15, count 0 2006.285.23:36:27.11#ibcon#read 6, iclass 15, count 0 2006.285.23:36:27.11#ibcon#end of sib2, iclass 15, count 0 2006.285.23:36:27.11#ibcon#*after write, iclass 15, count 0 2006.285.23:36:27.11#ibcon#*before return 0, iclass 15, count 0 2006.285.23:36:27.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:36:27.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:36:27.11#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:36:27.11#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:36:27.11$vck44/vb=6,3 2006.285.23:36:27.11#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.23:36:27.11#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.23:36:27.11#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:27.11#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:36:27.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:36:27.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:36:27.17#ibcon#enter wrdev, iclass 17, count 2 2006.285.23:36:27.17#ibcon#first serial, iclass 17, count 2 2006.285.23:36:27.17#ibcon#enter sib2, iclass 17, count 2 2006.285.23:36:27.17#ibcon#flushed, iclass 17, count 2 2006.285.23:36:27.17#ibcon#about to write, iclass 17, count 2 2006.285.23:36:27.17#ibcon#wrote, iclass 17, count 2 2006.285.23:36:27.17#ibcon#about to read 3, iclass 17, count 2 2006.285.23:36:27.19#ibcon#read 3, iclass 17, count 2 2006.285.23:36:27.19#ibcon#about to read 4, iclass 17, count 2 2006.285.23:36:27.19#ibcon#read 4, iclass 17, count 2 2006.285.23:36:27.19#ibcon#about to read 5, iclass 17, count 2 2006.285.23:36:27.19#ibcon#read 5, iclass 17, count 2 2006.285.23:36:27.19#ibcon#about to read 6, iclass 17, count 2 2006.285.23:36:27.19#ibcon#read 6, iclass 17, count 2 2006.285.23:36:27.19#ibcon#end of sib2, iclass 17, count 2 2006.285.23:36:27.19#ibcon#*mode == 0, iclass 17, count 2 2006.285.23:36:27.19#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.23:36:27.19#ibcon#[27=AT06-03\r\n] 2006.285.23:36:27.19#ibcon#*before write, iclass 17, count 2 2006.285.23:36:27.19#ibcon#enter sib2, iclass 17, count 2 2006.285.23:36:27.19#ibcon#flushed, iclass 17, count 2 2006.285.23:36:27.19#ibcon#about to write, iclass 17, count 2 2006.285.23:36:27.19#ibcon#wrote, iclass 17, count 2 2006.285.23:36:27.19#ibcon#about to read 3, iclass 17, count 2 2006.285.23:36:27.22#ibcon#read 3, iclass 17, count 2 2006.285.23:36:27.22#ibcon#about to read 4, iclass 17, count 2 2006.285.23:36:27.22#ibcon#read 4, iclass 17, count 2 2006.285.23:36:27.22#ibcon#about to read 5, iclass 17, count 2 2006.285.23:36:27.22#ibcon#read 5, iclass 17, count 2 2006.285.23:36:27.22#ibcon#about to read 6, iclass 17, count 2 2006.285.23:36:27.22#ibcon#read 6, iclass 17, count 2 2006.285.23:36:27.22#ibcon#end of sib2, iclass 17, count 2 2006.285.23:36:27.22#ibcon#*after write, iclass 17, count 2 2006.285.23:36:27.22#ibcon#*before return 0, iclass 17, count 2 2006.285.23:36:27.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:36:27.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:36:27.22#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.23:36:27.22#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:27.22#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:36:27.34#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:36:27.34#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:36:27.34#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:36:27.34#ibcon#first serial, iclass 17, count 0 2006.285.23:36:27.34#ibcon#enter sib2, iclass 17, count 0 2006.285.23:36:27.34#ibcon#flushed, iclass 17, count 0 2006.285.23:36:27.34#ibcon#about to write, iclass 17, count 0 2006.285.23:36:27.34#ibcon#wrote, iclass 17, count 0 2006.285.23:36:27.34#ibcon#about to read 3, iclass 17, count 0 2006.285.23:36:27.36#ibcon#read 3, iclass 17, count 0 2006.285.23:36:27.36#ibcon#about to read 4, iclass 17, count 0 2006.285.23:36:27.36#ibcon#read 4, iclass 17, count 0 2006.285.23:36:27.36#ibcon#about to read 5, iclass 17, count 0 2006.285.23:36:27.36#ibcon#read 5, iclass 17, count 0 2006.285.23:36:27.36#ibcon#about to read 6, iclass 17, count 0 2006.285.23:36:27.36#ibcon#read 6, iclass 17, count 0 2006.285.23:36:27.36#ibcon#end of sib2, iclass 17, count 0 2006.285.23:36:27.36#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:36:27.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:36:27.36#ibcon#[27=USB\r\n] 2006.285.23:36:27.36#ibcon#*before write, iclass 17, count 0 2006.285.23:36:27.36#ibcon#enter sib2, iclass 17, count 0 2006.285.23:36:27.36#ibcon#flushed, iclass 17, count 0 2006.285.23:36:27.36#ibcon#about to write, iclass 17, count 0 2006.285.23:36:27.36#ibcon#wrote, iclass 17, count 0 2006.285.23:36:27.36#ibcon#about to read 3, iclass 17, count 0 2006.285.23:36:27.39#ibcon#read 3, iclass 17, count 0 2006.285.23:36:27.39#ibcon#about to read 4, iclass 17, count 0 2006.285.23:36:27.39#ibcon#read 4, iclass 17, count 0 2006.285.23:36:27.39#ibcon#about to read 5, iclass 17, count 0 2006.285.23:36:27.39#ibcon#read 5, iclass 17, count 0 2006.285.23:36:27.39#ibcon#about to read 6, iclass 17, count 0 2006.285.23:36:27.39#ibcon#read 6, iclass 17, count 0 2006.285.23:36:27.39#ibcon#end of sib2, iclass 17, count 0 2006.285.23:36:27.39#ibcon#*after write, iclass 17, count 0 2006.285.23:36:27.39#ibcon#*before return 0, iclass 17, count 0 2006.285.23:36:27.39#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:36:27.39#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:36:27.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:36:27.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:36:27.39$vck44/vblo=7,734.99 2006.285.23:36:27.39#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.23:36:27.39#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.23:36:27.39#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:27.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:36:27.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:36:27.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:36:27.39#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:36:27.39#ibcon#first serial, iclass 19, count 0 2006.285.23:36:27.39#ibcon#enter sib2, iclass 19, count 0 2006.285.23:36:27.39#ibcon#flushed, iclass 19, count 0 2006.285.23:36:27.39#ibcon#about to write, iclass 19, count 0 2006.285.23:36:27.39#ibcon#wrote, iclass 19, count 0 2006.285.23:36:27.39#ibcon#about to read 3, iclass 19, count 0 2006.285.23:36:27.41#ibcon#read 3, iclass 19, count 0 2006.285.23:36:27.41#ibcon#about to read 4, iclass 19, count 0 2006.285.23:36:27.41#ibcon#read 4, iclass 19, count 0 2006.285.23:36:27.41#ibcon#about to read 5, iclass 19, count 0 2006.285.23:36:27.41#ibcon#read 5, iclass 19, count 0 2006.285.23:36:27.41#ibcon#about to read 6, iclass 19, count 0 2006.285.23:36:27.41#ibcon#read 6, iclass 19, count 0 2006.285.23:36:27.41#ibcon#end of sib2, iclass 19, count 0 2006.285.23:36:27.41#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:36:27.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:36:27.41#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:36:27.41#ibcon#*before write, iclass 19, count 0 2006.285.23:36:27.41#ibcon#enter sib2, iclass 19, count 0 2006.285.23:36:27.41#ibcon#flushed, iclass 19, count 0 2006.285.23:36:27.41#ibcon#about to write, iclass 19, count 0 2006.285.23:36:27.41#ibcon#wrote, iclass 19, count 0 2006.285.23:36:27.41#ibcon#about to read 3, iclass 19, count 0 2006.285.23:36:27.45#ibcon#read 3, iclass 19, count 0 2006.285.23:36:27.45#ibcon#about to read 4, iclass 19, count 0 2006.285.23:36:27.45#ibcon#read 4, iclass 19, count 0 2006.285.23:36:27.45#ibcon#about to read 5, iclass 19, count 0 2006.285.23:36:27.45#ibcon#read 5, iclass 19, count 0 2006.285.23:36:27.45#ibcon#about to read 6, iclass 19, count 0 2006.285.23:36:27.45#ibcon#read 6, iclass 19, count 0 2006.285.23:36:27.45#ibcon#end of sib2, iclass 19, count 0 2006.285.23:36:27.45#ibcon#*after write, iclass 19, count 0 2006.285.23:36:27.45#ibcon#*before return 0, iclass 19, count 0 2006.285.23:36:27.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:36:27.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:36:27.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:36:27.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:36:27.45$vck44/vb=7,4 2006.285.23:36:27.45#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.23:36:27.45#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.23:36:27.45#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:27.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:36:27.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:36:27.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:36:27.51#ibcon#enter wrdev, iclass 21, count 2 2006.285.23:36:27.51#ibcon#first serial, iclass 21, count 2 2006.285.23:36:27.51#ibcon#enter sib2, iclass 21, count 2 2006.285.23:36:27.51#ibcon#flushed, iclass 21, count 2 2006.285.23:36:27.51#ibcon#about to write, iclass 21, count 2 2006.285.23:36:27.51#ibcon#wrote, iclass 21, count 2 2006.285.23:36:27.51#ibcon#about to read 3, iclass 21, count 2 2006.285.23:36:27.53#ibcon#read 3, iclass 21, count 2 2006.285.23:36:27.53#ibcon#about to read 4, iclass 21, count 2 2006.285.23:36:27.53#ibcon#read 4, iclass 21, count 2 2006.285.23:36:27.53#ibcon#about to read 5, iclass 21, count 2 2006.285.23:36:27.53#ibcon#read 5, iclass 21, count 2 2006.285.23:36:27.53#ibcon#about to read 6, iclass 21, count 2 2006.285.23:36:27.53#ibcon#read 6, iclass 21, count 2 2006.285.23:36:27.53#ibcon#end of sib2, iclass 21, count 2 2006.285.23:36:27.53#ibcon#*mode == 0, iclass 21, count 2 2006.285.23:36:27.53#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.23:36:27.53#ibcon#[27=AT07-04\r\n] 2006.285.23:36:27.53#ibcon#*before write, iclass 21, count 2 2006.285.23:36:27.53#ibcon#enter sib2, iclass 21, count 2 2006.285.23:36:27.53#ibcon#flushed, iclass 21, count 2 2006.285.23:36:27.53#ibcon#about to write, iclass 21, count 2 2006.285.23:36:27.53#ibcon#wrote, iclass 21, count 2 2006.285.23:36:27.53#ibcon#about to read 3, iclass 21, count 2 2006.285.23:36:27.56#ibcon#read 3, iclass 21, count 2 2006.285.23:36:27.56#ibcon#about to read 4, iclass 21, count 2 2006.285.23:36:27.56#ibcon#read 4, iclass 21, count 2 2006.285.23:36:27.56#ibcon#about to read 5, iclass 21, count 2 2006.285.23:36:27.56#ibcon#read 5, iclass 21, count 2 2006.285.23:36:27.56#ibcon#about to read 6, iclass 21, count 2 2006.285.23:36:27.56#ibcon#read 6, iclass 21, count 2 2006.285.23:36:27.56#ibcon#end of sib2, iclass 21, count 2 2006.285.23:36:27.56#ibcon#*after write, iclass 21, count 2 2006.285.23:36:27.56#ibcon#*before return 0, iclass 21, count 2 2006.285.23:36:27.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:36:27.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:36:27.56#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.23:36:27.56#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:27.56#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:36:27.68#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:36:27.68#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:36:27.68#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:36:27.68#ibcon#first serial, iclass 21, count 0 2006.285.23:36:27.68#ibcon#enter sib2, iclass 21, count 0 2006.285.23:36:27.68#ibcon#flushed, iclass 21, count 0 2006.285.23:36:27.68#ibcon#about to write, iclass 21, count 0 2006.285.23:36:27.68#ibcon#wrote, iclass 21, count 0 2006.285.23:36:27.68#ibcon#about to read 3, iclass 21, count 0 2006.285.23:36:27.70#ibcon#read 3, iclass 21, count 0 2006.285.23:36:27.70#ibcon#about to read 4, iclass 21, count 0 2006.285.23:36:27.70#ibcon#read 4, iclass 21, count 0 2006.285.23:36:27.70#ibcon#about to read 5, iclass 21, count 0 2006.285.23:36:27.70#ibcon#read 5, iclass 21, count 0 2006.285.23:36:27.70#ibcon#about to read 6, iclass 21, count 0 2006.285.23:36:27.70#ibcon#read 6, iclass 21, count 0 2006.285.23:36:27.70#ibcon#end of sib2, iclass 21, count 0 2006.285.23:36:27.70#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:36:27.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:36:27.70#ibcon#[27=USB\r\n] 2006.285.23:36:27.70#ibcon#*before write, iclass 21, count 0 2006.285.23:36:27.70#ibcon#enter sib2, iclass 21, count 0 2006.285.23:36:27.70#ibcon#flushed, iclass 21, count 0 2006.285.23:36:27.70#ibcon#about to write, iclass 21, count 0 2006.285.23:36:27.70#ibcon#wrote, iclass 21, count 0 2006.285.23:36:27.70#ibcon#about to read 3, iclass 21, count 0 2006.285.23:36:27.73#ibcon#read 3, iclass 21, count 0 2006.285.23:36:27.73#ibcon#about to read 4, iclass 21, count 0 2006.285.23:36:27.73#ibcon#read 4, iclass 21, count 0 2006.285.23:36:27.73#ibcon#about to read 5, iclass 21, count 0 2006.285.23:36:27.73#ibcon#read 5, iclass 21, count 0 2006.285.23:36:27.73#ibcon#about to read 6, iclass 21, count 0 2006.285.23:36:27.73#ibcon#read 6, iclass 21, count 0 2006.285.23:36:27.73#ibcon#end of sib2, iclass 21, count 0 2006.285.23:36:27.73#ibcon#*after write, iclass 21, count 0 2006.285.23:36:27.73#ibcon#*before return 0, iclass 21, count 0 2006.285.23:36:27.73#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:36:27.73#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:36:27.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:36:27.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:36:27.73$vck44/vblo=8,744.99 2006.285.23:36:27.73#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.23:36:27.73#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.23:36:27.73#ibcon#ireg 17 cls_cnt 0 2006.285.23:36:27.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:36:27.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:36:27.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:36:27.73#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:36:27.73#ibcon#first serial, iclass 23, count 0 2006.285.23:36:27.73#ibcon#enter sib2, iclass 23, count 0 2006.285.23:36:27.73#ibcon#flushed, iclass 23, count 0 2006.285.23:36:27.73#ibcon#about to write, iclass 23, count 0 2006.285.23:36:27.73#ibcon#wrote, iclass 23, count 0 2006.285.23:36:27.73#ibcon#about to read 3, iclass 23, count 0 2006.285.23:36:27.75#ibcon#read 3, iclass 23, count 0 2006.285.23:36:27.75#ibcon#about to read 4, iclass 23, count 0 2006.285.23:36:27.75#ibcon#read 4, iclass 23, count 0 2006.285.23:36:27.75#ibcon#about to read 5, iclass 23, count 0 2006.285.23:36:27.75#ibcon#read 5, iclass 23, count 0 2006.285.23:36:27.75#ibcon#about to read 6, iclass 23, count 0 2006.285.23:36:27.75#ibcon#read 6, iclass 23, count 0 2006.285.23:36:27.75#ibcon#end of sib2, iclass 23, count 0 2006.285.23:36:27.75#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:36:27.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:36:27.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:36:27.75#ibcon#*before write, iclass 23, count 0 2006.285.23:36:27.75#ibcon#enter sib2, iclass 23, count 0 2006.285.23:36:27.75#ibcon#flushed, iclass 23, count 0 2006.285.23:36:27.75#ibcon#about to write, iclass 23, count 0 2006.285.23:36:27.75#ibcon#wrote, iclass 23, count 0 2006.285.23:36:27.75#ibcon#about to read 3, iclass 23, count 0 2006.285.23:36:27.79#ibcon#read 3, iclass 23, count 0 2006.285.23:36:27.79#ibcon#about to read 4, iclass 23, count 0 2006.285.23:36:27.79#ibcon#read 4, iclass 23, count 0 2006.285.23:36:27.79#ibcon#about to read 5, iclass 23, count 0 2006.285.23:36:27.79#ibcon#read 5, iclass 23, count 0 2006.285.23:36:27.79#ibcon#about to read 6, iclass 23, count 0 2006.285.23:36:27.79#ibcon#read 6, iclass 23, count 0 2006.285.23:36:27.79#ibcon#end of sib2, iclass 23, count 0 2006.285.23:36:27.79#ibcon#*after write, iclass 23, count 0 2006.285.23:36:27.79#ibcon#*before return 0, iclass 23, count 0 2006.285.23:36:27.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:36:27.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:36:27.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:36:27.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:36:27.79$vck44/vb=8,4 2006.285.23:36:27.79#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.23:36:27.79#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.23:36:27.79#ibcon#ireg 11 cls_cnt 2 2006.285.23:36:27.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:36:27.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:36:27.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:36:27.85#ibcon#enter wrdev, iclass 25, count 2 2006.285.23:36:27.85#ibcon#first serial, iclass 25, count 2 2006.285.23:36:27.85#ibcon#enter sib2, iclass 25, count 2 2006.285.23:36:27.85#ibcon#flushed, iclass 25, count 2 2006.285.23:36:27.85#ibcon#about to write, iclass 25, count 2 2006.285.23:36:27.85#ibcon#wrote, iclass 25, count 2 2006.285.23:36:27.85#ibcon#about to read 3, iclass 25, count 2 2006.285.23:36:27.87#ibcon#read 3, iclass 25, count 2 2006.285.23:36:27.87#ibcon#about to read 4, iclass 25, count 2 2006.285.23:36:27.87#ibcon#read 4, iclass 25, count 2 2006.285.23:36:27.87#ibcon#about to read 5, iclass 25, count 2 2006.285.23:36:27.87#ibcon#read 5, iclass 25, count 2 2006.285.23:36:27.87#ibcon#about to read 6, iclass 25, count 2 2006.285.23:36:27.87#ibcon#read 6, iclass 25, count 2 2006.285.23:36:27.87#ibcon#end of sib2, iclass 25, count 2 2006.285.23:36:27.87#ibcon#*mode == 0, iclass 25, count 2 2006.285.23:36:27.87#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.23:36:27.87#ibcon#[27=AT08-04\r\n] 2006.285.23:36:27.87#ibcon#*before write, iclass 25, count 2 2006.285.23:36:27.87#ibcon#enter sib2, iclass 25, count 2 2006.285.23:36:27.87#ibcon#flushed, iclass 25, count 2 2006.285.23:36:27.87#ibcon#about to write, iclass 25, count 2 2006.285.23:36:27.87#ibcon#wrote, iclass 25, count 2 2006.285.23:36:27.87#ibcon#about to read 3, iclass 25, count 2 2006.285.23:36:27.90#ibcon#read 3, iclass 25, count 2 2006.285.23:36:27.90#ibcon#about to read 4, iclass 25, count 2 2006.285.23:36:27.90#ibcon#read 4, iclass 25, count 2 2006.285.23:36:27.90#ibcon#about to read 5, iclass 25, count 2 2006.285.23:36:27.90#ibcon#read 5, iclass 25, count 2 2006.285.23:36:27.90#ibcon#about to read 6, iclass 25, count 2 2006.285.23:36:27.90#ibcon#read 6, iclass 25, count 2 2006.285.23:36:27.90#ibcon#end of sib2, iclass 25, count 2 2006.285.23:36:27.90#ibcon#*after write, iclass 25, count 2 2006.285.23:36:27.90#ibcon#*before return 0, iclass 25, count 2 2006.285.23:36:27.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:36:27.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:36:27.90#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.23:36:27.90#ibcon#ireg 7 cls_cnt 0 2006.285.23:36:27.90#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:36:28.02#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:36:28.02#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:36:28.02#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:36:28.02#ibcon#first serial, iclass 25, count 0 2006.285.23:36:28.02#ibcon#enter sib2, iclass 25, count 0 2006.285.23:36:28.02#ibcon#flushed, iclass 25, count 0 2006.285.23:36:28.02#ibcon#about to write, iclass 25, count 0 2006.285.23:36:28.02#ibcon#wrote, iclass 25, count 0 2006.285.23:36:28.02#ibcon#about to read 3, iclass 25, count 0 2006.285.23:36:28.04#ibcon#read 3, iclass 25, count 0 2006.285.23:36:28.04#ibcon#about to read 4, iclass 25, count 0 2006.285.23:36:28.04#ibcon#read 4, iclass 25, count 0 2006.285.23:36:28.04#ibcon#about to read 5, iclass 25, count 0 2006.285.23:36:28.04#ibcon#read 5, iclass 25, count 0 2006.285.23:36:28.04#ibcon#about to read 6, iclass 25, count 0 2006.285.23:36:28.04#ibcon#read 6, iclass 25, count 0 2006.285.23:36:28.04#ibcon#end of sib2, iclass 25, count 0 2006.285.23:36:28.04#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:36:28.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:36:28.04#ibcon#[27=USB\r\n] 2006.285.23:36:28.04#ibcon#*before write, iclass 25, count 0 2006.285.23:36:28.04#ibcon#enter sib2, iclass 25, count 0 2006.285.23:36:28.04#ibcon#flushed, iclass 25, count 0 2006.285.23:36:28.04#ibcon#about to write, iclass 25, count 0 2006.285.23:36:28.04#ibcon#wrote, iclass 25, count 0 2006.285.23:36:28.04#ibcon#about to read 3, iclass 25, count 0 2006.285.23:36:28.07#ibcon#read 3, iclass 25, count 0 2006.285.23:36:28.07#ibcon#about to read 4, iclass 25, count 0 2006.285.23:36:28.07#ibcon#read 4, iclass 25, count 0 2006.285.23:36:28.07#ibcon#about to read 5, iclass 25, count 0 2006.285.23:36:28.07#ibcon#read 5, iclass 25, count 0 2006.285.23:36:28.07#ibcon#about to read 6, iclass 25, count 0 2006.285.23:36:28.07#ibcon#read 6, iclass 25, count 0 2006.285.23:36:28.07#ibcon#end of sib2, iclass 25, count 0 2006.285.23:36:28.07#ibcon#*after write, iclass 25, count 0 2006.285.23:36:28.07#ibcon#*before return 0, iclass 25, count 0 2006.285.23:36:28.07#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:36:28.07#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:36:28.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:36:28.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:36:28.07$vck44/vabw=wide 2006.285.23:36:28.07#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.23:36:28.07#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.23:36:28.07#ibcon#ireg 8 cls_cnt 0 2006.285.23:36:28.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:36:28.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:36:28.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:36:28.07#ibcon#enter wrdev, iclass 27, count 0 2006.285.23:36:28.07#ibcon#first serial, iclass 27, count 0 2006.285.23:36:28.07#ibcon#enter sib2, iclass 27, count 0 2006.285.23:36:28.07#ibcon#flushed, iclass 27, count 0 2006.285.23:36:28.07#ibcon#about to write, iclass 27, count 0 2006.285.23:36:28.07#ibcon#wrote, iclass 27, count 0 2006.285.23:36:28.07#ibcon#about to read 3, iclass 27, count 0 2006.285.23:36:28.09#ibcon#read 3, iclass 27, count 0 2006.285.23:36:28.09#ibcon#about to read 4, iclass 27, count 0 2006.285.23:36:28.09#ibcon#read 4, iclass 27, count 0 2006.285.23:36:28.09#ibcon#about to read 5, iclass 27, count 0 2006.285.23:36:28.09#ibcon#read 5, iclass 27, count 0 2006.285.23:36:28.09#ibcon#about to read 6, iclass 27, count 0 2006.285.23:36:28.09#ibcon#read 6, iclass 27, count 0 2006.285.23:36:28.09#ibcon#end of sib2, iclass 27, count 0 2006.285.23:36:28.09#ibcon#*mode == 0, iclass 27, count 0 2006.285.23:36:28.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.23:36:28.09#ibcon#[25=BW32\r\n] 2006.285.23:36:28.09#ibcon#*before write, iclass 27, count 0 2006.285.23:36:28.09#ibcon#enter sib2, iclass 27, count 0 2006.285.23:36:28.09#ibcon#flushed, iclass 27, count 0 2006.285.23:36:28.09#ibcon#about to write, iclass 27, count 0 2006.285.23:36:28.09#ibcon#wrote, iclass 27, count 0 2006.285.23:36:28.09#ibcon#about to read 3, iclass 27, count 0 2006.285.23:36:28.12#ibcon#read 3, iclass 27, count 0 2006.285.23:36:28.12#ibcon#about to read 4, iclass 27, count 0 2006.285.23:36:28.12#ibcon#read 4, iclass 27, count 0 2006.285.23:36:28.12#ibcon#about to read 5, iclass 27, count 0 2006.285.23:36:28.12#ibcon#read 5, iclass 27, count 0 2006.285.23:36:28.12#ibcon#about to read 6, iclass 27, count 0 2006.285.23:36:28.12#ibcon#read 6, iclass 27, count 0 2006.285.23:36:28.12#ibcon#end of sib2, iclass 27, count 0 2006.285.23:36:28.12#ibcon#*after write, iclass 27, count 0 2006.285.23:36:28.12#ibcon#*before return 0, iclass 27, count 0 2006.285.23:36:28.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:36:28.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:36:28.12#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.23:36:28.12#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.23:36:28.12$vck44/vbbw=wide 2006.285.23:36:28.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.23:36:28.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.23:36:28.12#ibcon#ireg 8 cls_cnt 0 2006.285.23:36:28.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:36:28.17#abcon#<5=/03 3.5 9.2 19.40 891016.5\r\n> 2006.285.23:36:28.19#abcon#{5=INTERFACE CLEAR} 2006.285.23:36:28.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:36:28.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:36:28.19#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:36:28.19#ibcon#first serial, iclass 30, count 0 2006.285.23:36:28.19#ibcon#enter sib2, iclass 30, count 0 2006.285.23:36:28.19#ibcon#flushed, iclass 30, count 0 2006.285.23:36:28.19#ibcon#about to write, iclass 30, count 0 2006.285.23:36:28.19#ibcon#wrote, iclass 30, count 0 2006.285.23:36:28.19#ibcon#about to read 3, iclass 30, count 0 2006.285.23:36:28.21#ibcon#read 3, iclass 30, count 0 2006.285.23:36:28.21#ibcon#about to read 4, iclass 30, count 0 2006.285.23:36:28.21#ibcon#read 4, iclass 30, count 0 2006.285.23:36:28.21#ibcon#about to read 5, iclass 30, count 0 2006.285.23:36:28.21#ibcon#read 5, iclass 30, count 0 2006.285.23:36:28.21#ibcon#about to read 6, iclass 30, count 0 2006.285.23:36:28.21#ibcon#read 6, iclass 30, count 0 2006.285.23:36:28.21#ibcon#end of sib2, iclass 30, count 0 2006.285.23:36:28.21#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:36:28.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:36:28.21#ibcon#[27=BW32\r\n] 2006.285.23:36:28.21#ibcon#*before write, iclass 30, count 0 2006.285.23:36:28.21#ibcon#enter sib2, iclass 30, count 0 2006.285.23:36:28.21#ibcon#flushed, iclass 30, count 0 2006.285.23:36:28.21#ibcon#about to write, iclass 30, count 0 2006.285.23:36:28.21#ibcon#wrote, iclass 30, count 0 2006.285.23:36:28.21#ibcon#about to read 3, iclass 30, count 0 2006.285.23:36:28.24#ibcon#read 3, iclass 30, count 0 2006.285.23:36:28.24#ibcon#about to read 4, iclass 30, count 0 2006.285.23:36:28.24#ibcon#read 4, iclass 30, count 0 2006.285.23:36:28.24#ibcon#about to read 5, iclass 30, count 0 2006.285.23:36:28.24#ibcon#read 5, iclass 30, count 0 2006.285.23:36:28.24#ibcon#about to read 6, iclass 30, count 0 2006.285.23:36:28.24#ibcon#read 6, iclass 30, count 0 2006.285.23:36:28.24#ibcon#end of sib2, iclass 30, count 0 2006.285.23:36:28.24#ibcon#*after write, iclass 30, count 0 2006.285.23:36:28.24#ibcon#*before return 0, iclass 30, count 0 2006.285.23:36:28.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:36:28.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:36:28.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:36:28.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:36:28.24$setupk4/ifdk4 2006.285.23:36:28.24$ifdk4/lo= 2006.285.23:36:28.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:36:28.24$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:36:28.24$ifdk4/patch= 2006.285.23:36:28.24$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:36:28.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:36:28.24$setupk4/!*+20s 2006.285.23:36:28.25#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:36:38.34#abcon#<5=/03 3.5 9.2 19.40 891016.5\r\n> 2006.285.23:36:38.36#abcon#{5=INTERFACE CLEAR} 2006.285.23:36:38.42#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:36:42.74$setupk4/"tpicd 2006.285.23:36:42.74$setupk4/echo=off 2006.285.23:36:42.74$setupk4/xlog=off 2006.285.23:36:42.74:!2006.285.23:41:38 2006.285.23:36:53.14#trakl#Source acquired 2006.285.23:36:54.14#flagr#flagr/antenna,acquired 2006.285.23:41:38.02:preob 2006.285.23:41:39.14/onsource/TRACKING 2006.285.23:41:39.14:!2006.285.23:41:48 2006.285.23:41:48.01:"tape 2006.285.23:41:48.02:"st=record 2006.285.23:41:48.02:data_valid=on 2006.285.23:41:48.02:midob 2006.285.23:41:49.14/onsource/TRACKING 2006.285.23:41:49.14/wx/19.42,1016.5,88 2006.285.23:41:49.35/cable/+6.5095E-03 2006.285.23:41:50.44/va/01,07,usb,yes,33,36 2006.285.23:41:50.44/va/02,06,usb,yes,33,34 2006.285.23:41:50.44/va/03,07,usb,yes,33,35 2006.285.23:41:50.44/va/04,06,usb,yes,34,36 2006.285.23:41:50.44/va/05,03,usb,yes,34,34 2006.285.23:41:50.44/va/06,04,usb,yes,30,30 2006.285.23:41:50.44/va/07,04,usb,yes,31,32 2006.285.23:41:50.44/va/08,03,usb,yes,32,39 2006.285.23:41:50.67/valo/01,524.99,yes,locked 2006.285.23:41:50.67/valo/02,534.99,yes,locked 2006.285.23:41:50.67/valo/03,564.99,yes,locked 2006.285.23:41:50.67/valo/04,624.99,yes,locked 2006.285.23:41:50.67/valo/05,734.99,yes,locked 2006.285.23:41:50.67/valo/06,814.99,yes,locked 2006.285.23:41:50.67/valo/07,864.99,yes,locked 2006.285.23:41:50.67/valo/08,884.99,yes,locked 2006.285.23:41:51.76/vb/01,04,usb,yes,31,29 2006.285.23:41:51.76/vb/02,05,usb,yes,29,29 2006.285.23:41:51.76/vb/03,04,usb,yes,30,33 2006.285.23:41:51.76/vb/04,05,usb,yes,30,29 2006.285.23:41:51.76/vb/05,04,usb,yes,27,29 2006.285.23:41:51.76/vb/06,03,usb,yes,38,34 2006.285.23:41:51.76/vb/07,04,usb,yes,31,31 2006.285.23:41:51.76/vb/08,04,usb,yes,28,32 2006.285.23:41:51.99/vblo/01,629.99,yes,locked 2006.285.23:41:51.99/vblo/02,634.99,yes,locked 2006.285.23:41:51.99/vblo/03,649.99,yes,locked 2006.285.23:41:51.99/vblo/04,679.99,yes,locked 2006.285.23:41:51.99/vblo/05,709.99,yes,locked 2006.285.23:41:51.99/vblo/06,719.99,yes,locked 2006.285.23:41:51.99/vblo/07,734.99,yes,locked 2006.285.23:41:51.99/vblo/08,744.99,yes,locked 2006.285.23:41:52.14/vabw/8 2006.285.23:41:52.29/vbbw/8 2006.285.23:41:52.46/xfe/off,on,12.0 2006.285.23:41:52.83/ifatt/23,28,28,28 2006.285.23:41:53.07/fmout-gps/S +2.73E-07 2006.285.23:41:53.09:!2006.285.23:42:58 2006.285.23:42:58.00:data_valid=off 2006.285.23:42:58.00:"et 2006.285.23:42:58.01:!+3s 2006.285.23:43:01.03:"tape 2006.285.23:43:01.03:postob 2006.285.23:43:01.26/cable/+6.5091E-03 2006.285.23:43:01.27/wx/19.44,1016.5,88 2006.285.23:43:01.32/fmout-gps/S +2.72E-07 2006.285.23:43:01.32:scan_name=285-2345,jd0610,120 2006.285.23:43:01.33:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.285.23:43:02.13#flagr#flagr/antenna,new-source 2006.285.23:43:02.14:checkk5 2006.285.23:43:02.54/chk_autoobs//k5ts1/ autoobs is running! 2006.285.23:43:03.21/chk_autoobs//k5ts2/ autoobs is running! 2006.285.23:43:03.61/chk_autoobs//k5ts3/ autoobs is running! 2006.285.23:43:04.25/chk_autoobs//k5ts4/ autoobs is running! 2006.285.23:43:04.61/chk_obsdata//k5ts1/T2852341??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.23:43:05.07/chk_obsdata//k5ts2/T2852341??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.23:43:05.85/chk_obsdata//k5ts3/T2852341??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.23:43:06.26/chk_obsdata//k5ts4/T2852341??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.285.23:43:07.11/k5log//k5ts1_log_newline 2006.285.23:43:08.00/k5log//k5ts2_log_newline 2006.285.23:43:08.69/k5log//k5ts3_log_newline 2006.285.23:43:09.41/k5log//k5ts4_log_newline 2006.285.23:43:09.43/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.23:43:09.43:setupk4=1 2006.285.23:43:09.43$setupk4/echo=on 2006.285.23:43:09.43$setupk4/pcalon 2006.285.23:43:09.43$pcalon/"no phase cal control is implemented here 2006.285.23:43:09.43$setupk4/"tpicd=stop 2006.285.23:43:09.43$setupk4/"rec=synch_on 2006.285.23:43:09.43$setupk4/"rec_mode=128 2006.285.23:43:09.43$setupk4/!* 2006.285.23:43:09.43$setupk4/recpk4 2006.285.23:43:09.43$recpk4/recpatch= 2006.285.23:43:09.43$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.23:43:09.43$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.23:43:09.43$setupk4/vck44 2006.285.23:43:09.43$vck44/valo=1,524.99 2006.285.23:43:09.43#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.23:43:09.43#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.23:43:09.43#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:09.43#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:43:09.43#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:43:09.43#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:43:09.43#ibcon#enter wrdev, iclass 14, count 0 2006.285.23:43:09.43#ibcon#first serial, iclass 14, count 0 2006.285.23:43:09.43#ibcon#enter sib2, iclass 14, count 0 2006.285.23:43:09.43#ibcon#flushed, iclass 14, count 0 2006.285.23:43:09.43#ibcon#about to write, iclass 14, count 0 2006.285.23:43:09.43#ibcon#wrote, iclass 14, count 0 2006.285.23:43:09.43#ibcon#about to read 3, iclass 14, count 0 2006.285.23:43:09.44#ibcon#read 3, iclass 14, count 0 2006.285.23:43:09.44#ibcon#about to read 4, iclass 14, count 0 2006.285.23:43:09.44#ibcon#read 4, iclass 14, count 0 2006.285.23:43:09.44#ibcon#about to read 5, iclass 14, count 0 2006.285.23:43:09.44#ibcon#read 5, iclass 14, count 0 2006.285.23:43:09.44#ibcon#about to read 6, iclass 14, count 0 2006.285.23:43:09.44#ibcon#read 6, iclass 14, count 0 2006.285.23:43:09.44#ibcon#end of sib2, iclass 14, count 0 2006.285.23:43:09.44#ibcon#*mode == 0, iclass 14, count 0 2006.285.23:43:09.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.23:43:09.44#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.23:43:09.44#ibcon#*before write, iclass 14, count 0 2006.285.23:43:09.44#ibcon#enter sib2, iclass 14, count 0 2006.285.23:43:09.44#ibcon#flushed, iclass 14, count 0 2006.285.23:43:09.44#ibcon#about to write, iclass 14, count 0 2006.285.23:43:09.44#ibcon#wrote, iclass 14, count 0 2006.285.23:43:09.44#ibcon#about to read 3, iclass 14, count 0 2006.285.23:43:09.49#ibcon#read 3, iclass 14, count 0 2006.285.23:43:09.49#ibcon#about to read 4, iclass 14, count 0 2006.285.23:43:09.49#ibcon#read 4, iclass 14, count 0 2006.285.23:43:09.49#ibcon#about to read 5, iclass 14, count 0 2006.285.23:43:09.49#ibcon#read 5, iclass 14, count 0 2006.285.23:43:09.49#ibcon#about to read 6, iclass 14, count 0 2006.285.23:43:09.49#ibcon#read 6, iclass 14, count 0 2006.285.23:43:09.49#ibcon#end of sib2, iclass 14, count 0 2006.285.23:43:09.49#ibcon#*after write, iclass 14, count 0 2006.285.23:43:09.49#ibcon#*before return 0, iclass 14, count 0 2006.285.23:43:09.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:43:09.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:43:09.49#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.23:43:09.49#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.23:43:09.49$vck44/va=1,7 2006.285.23:43:09.49#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.23:43:09.49#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.23:43:09.49#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:09.49#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:43:09.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:43:09.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:43:09.49#ibcon#enter wrdev, iclass 16, count 2 2006.285.23:43:09.49#ibcon#first serial, iclass 16, count 2 2006.285.23:43:09.49#ibcon#enter sib2, iclass 16, count 2 2006.285.23:43:09.49#ibcon#flushed, iclass 16, count 2 2006.285.23:43:09.49#ibcon#about to write, iclass 16, count 2 2006.285.23:43:09.49#ibcon#wrote, iclass 16, count 2 2006.285.23:43:09.49#ibcon#about to read 3, iclass 16, count 2 2006.285.23:43:09.51#ibcon#read 3, iclass 16, count 2 2006.285.23:43:09.51#ibcon#about to read 4, iclass 16, count 2 2006.285.23:43:09.51#ibcon#read 4, iclass 16, count 2 2006.285.23:43:09.51#ibcon#about to read 5, iclass 16, count 2 2006.285.23:43:09.51#ibcon#read 5, iclass 16, count 2 2006.285.23:43:09.51#ibcon#about to read 6, iclass 16, count 2 2006.285.23:43:09.51#ibcon#read 6, iclass 16, count 2 2006.285.23:43:09.51#ibcon#end of sib2, iclass 16, count 2 2006.285.23:43:09.51#ibcon#*mode == 0, iclass 16, count 2 2006.285.23:43:09.51#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.23:43:09.51#ibcon#[25=AT01-07\r\n] 2006.285.23:43:09.51#ibcon#*before write, iclass 16, count 2 2006.285.23:43:09.51#ibcon#enter sib2, iclass 16, count 2 2006.285.23:43:09.51#ibcon#flushed, iclass 16, count 2 2006.285.23:43:09.51#ibcon#about to write, iclass 16, count 2 2006.285.23:43:09.51#ibcon#wrote, iclass 16, count 2 2006.285.23:43:09.51#ibcon#about to read 3, iclass 16, count 2 2006.285.23:43:09.54#ibcon#read 3, iclass 16, count 2 2006.285.23:43:09.54#ibcon#about to read 4, iclass 16, count 2 2006.285.23:43:09.54#ibcon#read 4, iclass 16, count 2 2006.285.23:43:09.54#ibcon#about to read 5, iclass 16, count 2 2006.285.23:43:09.54#ibcon#read 5, iclass 16, count 2 2006.285.23:43:09.54#ibcon#about to read 6, iclass 16, count 2 2006.285.23:43:09.54#ibcon#read 6, iclass 16, count 2 2006.285.23:43:09.54#ibcon#end of sib2, iclass 16, count 2 2006.285.23:43:09.54#ibcon#*after write, iclass 16, count 2 2006.285.23:43:09.54#ibcon#*before return 0, iclass 16, count 2 2006.285.23:43:09.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:43:09.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:43:09.54#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.23:43:09.54#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:09.54#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:43:09.66#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:43:09.66#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:43:09.66#ibcon#enter wrdev, iclass 16, count 0 2006.285.23:43:09.66#ibcon#first serial, iclass 16, count 0 2006.285.23:43:09.66#ibcon#enter sib2, iclass 16, count 0 2006.285.23:43:09.66#ibcon#flushed, iclass 16, count 0 2006.285.23:43:09.66#ibcon#about to write, iclass 16, count 0 2006.285.23:43:09.66#ibcon#wrote, iclass 16, count 0 2006.285.23:43:09.66#ibcon#about to read 3, iclass 16, count 0 2006.285.23:43:09.68#ibcon#read 3, iclass 16, count 0 2006.285.23:43:09.68#ibcon#about to read 4, iclass 16, count 0 2006.285.23:43:09.68#ibcon#read 4, iclass 16, count 0 2006.285.23:43:09.68#ibcon#about to read 5, iclass 16, count 0 2006.285.23:43:09.68#ibcon#read 5, iclass 16, count 0 2006.285.23:43:09.68#ibcon#about to read 6, iclass 16, count 0 2006.285.23:43:09.68#ibcon#read 6, iclass 16, count 0 2006.285.23:43:09.68#ibcon#end of sib2, iclass 16, count 0 2006.285.23:43:09.68#ibcon#*mode == 0, iclass 16, count 0 2006.285.23:43:09.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.23:43:09.68#ibcon#[25=USB\r\n] 2006.285.23:43:09.68#ibcon#*before write, iclass 16, count 0 2006.285.23:43:09.68#ibcon#enter sib2, iclass 16, count 0 2006.285.23:43:09.68#ibcon#flushed, iclass 16, count 0 2006.285.23:43:09.68#ibcon#about to write, iclass 16, count 0 2006.285.23:43:09.68#ibcon#wrote, iclass 16, count 0 2006.285.23:43:09.68#ibcon#about to read 3, iclass 16, count 0 2006.285.23:43:09.71#ibcon#read 3, iclass 16, count 0 2006.285.23:43:09.71#ibcon#about to read 4, iclass 16, count 0 2006.285.23:43:09.71#ibcon#read 4, iclass 16, count 0 2006.285.23:43:09.71#ibcon#about to read 5, iclass 16, count 0 2006.285.23:43:09.71#ibcon#read 5, iclass 16, count 0 2006.285.23:43:09.71#ibcon#about to read 6, iclass 16, count 0 2006.285.23:43:09.71#ibcon#read 6, iclass 16, count 0 2006.285.23:43:09.71#ibcon#end of sib2, iclass 16, count 0 2006.285.23:43:09.71#ibcon#*after write, iclass 16, count 0 2006.285.23:43:09.71#ibcon#*before return 0, iclass 16, count 0 2006.285.23:43:09.71#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:43:09.71#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:43:09.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.23:43:09.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.23:43:09.71$vck44/valo=2,534.99 2006.285.23:43:09.71#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.23:43:09.71#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.23:43:09.71#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:09.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:43:09.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:43:09.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:43:09.71#ibcon#enter wrdev, iclass 18, count 0 2006.285.23:43:09.71#ibcon#first serial, iclass 18, count 0 2006.285.23:43:09.71#ibcon#enter sib2, iclass 18, count 0 2006.285.23:43:09.71#ibcon#flushed, iclass 18, count 0 2006.285.23:43:09.71#ibcon#about to write, iclass 18, count 0 2006.285.23:43:09.71#ibcon#wrote, iclass 18, count 0 2006.285.23:43:09.71#ibcon#about to read 3, iclass 18, count 0 2006.285.23:43:09.73#ibcon#read 3, iclass 18, count 0 2006.285.23:43:09.73#ibcon#about to read 4, iclass 18, count 0 2006.285.23:43:09.73#ibcon#read 4, iclass 18, count 0 2006.285.23:43:09.73#ibcon#about to read 5, iclass 18, count 0 2006.285.23:43:09.73#ibcon#read 5, iclass 18, count 0 2006.285.23:43:09.73#ibcon#about to read 6, iclass 18, count 0 2006.285.23:43:09.73#ibcon#read 6, iclass 18, count 0 2006.285.23:43:09.73#ibcon#end of sib2, iclass 18, count 0 2006.285.23:43:09.73#ibcon#*mode == 0, iclass 18, count 0 2006.285.23:43:09.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.23:43:09.73#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.23:43:09.73#ibcon#*before write, iclass 18, count 0 2006.285.23:43:09.73#ibcon#enter sib2, iclass 18, count 0 2006.285.23:43:09.73#ibcon#flushed, iclass 18, count 0 2006.285.23:43:09.73#ibcon#about to write, iclass 18, count 0 2006.285.23:43:09.73#ibcon#wrote, iclass 18, count 0 2006.285.23:43:09.73#ibcon#about to read 3, iclass 18, count 0 2006.285.23:43:09.77#ibcon#read 3, iclass 18, count 0 2006.285.23:43:09.77#ibcon#about to read 4, iclass 18, count 0 2006.285.23:43:09.77#ibcon#read 4, iclass 18, count 0 2006.285.23:43:09.77#ibcon#about to read 5, iclass 18, count 0 2006.285.23:43:09.77#ibcon#read 5, iclass 18, count 0 2006.285.23:43:09.77#ibcon#about to read 6, iclass 18, count 0 2006.285.23:43:09.77#ibcon#read 6, iclass 18, count 0 2006.285.23:43:09.77#ibcon#end of sib2, iclass 18, count 0 2006.285.23:43:09.77#ibcon#*after write, iclass 18, count 0 2006.285.23:43:09.77#ibcon#*before return 0, iclass 18, count 0 2006.285.23:43:09.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:43:09.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:43:09.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.23:43:09.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.23:43:09.77$vck44/va=2,6 2006.285.23:43:09.77#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.23:43:09.77#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.23:43:09.77#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:09.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:43:09.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:43:09.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:43:09.83#ibcon#enter wrdev, iclass 20, count 2 2006.285.23:43:09.83#ibcon#first serial, iclass 20, count 2 2006.285.23:43:09.83#ibcon#enter sib2, iclass 20, count 2 2006.285.23:43:09.83#ibcon#flushed, iclass 20, count 2 2006.285.23:43:09.83#ibcon#about to write, iclass 20, count 2 2006.285.23:43:09.83#ibcon#wrote, iclass 20, count 2 2006.285.23:43:09.83#ibcon#about to read 3, iclass 20, count 2 2006.285.23:43:09.85#ibcon#read 3, iclass 20, count 2 2006.285.23:43:09.85#ibcon#about to read 4, iclass 20, count 2 2006.285.23:43:09.85#ibcon#read 4, iclass 20, count 2 2006.285.23:43:09.85#ibcon#about to read 5, iclass 20, count 2 2006.285.23:43:09.85#ibcon#read 5, iclass 20, count 2 2006.285.23:43:09.85#ibcon#about to read 6, iclass 20, count 2 2006.285.23:43:09.85#ibcon#read 6, iclass 20, count 2 2006.285.23:43:09.85#ibcon#end of sib2, iclass 20, count 2 2006.285.23:43:09.85#ibcon#*mode == 0, iclass 20, count 2 2006.285.23:43:09.85#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.23:43:09.85#ibcon#[25=AT02-06\r\n] 2006.285.23:43:09.85#ibcon#*before write, iclass 20, count 2 2006.285.23:43:09.85#ibcon#enter sib2, iclass 20, count 2 2006.285.23:43:09.85#ibcon#flushed, iclass 20, count 2 2006.285.23:43:09.85#ibcon#about to write, iclass 20, count 2 2006.285.23:43:09.85#ibcon#wrote, iclass 20, count 2 2006.285.23:43:09.85#ibcon#about to read 3, iclass 20, count 2 2006.285.23:43:09.88#ibcon#read 3, iclass 20, count 2 2006.285.23:43:09.88#ibcon#about to read 4, iclass 20, count 2 2006.285.23:43:09.88#ibcon#read 4, iclass 20, count 2 2006.285.23:43:09.88#ibcon#about to read 5, iclass 20, count 2 2006.285.23:43:09.88#ibcon#read 5, iclass 20, count 2 2006.285.23:43:09.88#ibcon#about to read 6, iclass 20, count 2 2006.285.23:43:09.88#ibcon#read 6, iclass 20, count 2 2006.285.23:43:09.88#ibcon#end of sib2, iclass 20, count 2 2006.285.23:43:09.88#ibcon#*after write, iclass 20, count 2 2006.285.23:43:09.88#ibcon#*before return 0, iclass 20, count 2 2006.285.23:43:09.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:43:09.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:43:09.88#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.23:43:09.88#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:09.88#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:43:10.00#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:43:10.00#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:43:10.00#ibcon#enter wrdev, iclass 20, count 0 2006.285.23:43:10.00#ibcon#first serial, iclass 20, count 0 2006.285.23:43:10.00#ibcon#enter sib2, iclass 20, count 0 2006.285.23:43:10.00#ibcon#flushed, iclass 20, count 0 2006.285.23:43:10.00#ibcon#about to write, iclass 20, count 0 2006.285.23:43:10.00#ibcon#wrote, iclass 20, count 0 2006.285.23:43:10.00#ibcon#about to read 3, iclass 20, count 0 2006.285.23:43:10.02#ibcon#read 3, iclass 20, count 0 2006.285.23:43:10.02#ibcon#about to read 4, iclass 20, count 0 2006.285.23:43:10.02#ibcon#read 4, iclass 20, count 0 2006.285.23:43:10.02#ibcon#about to read 5, iclass 20, count 0 2006.285.23:43:10.02#ibcon#read 5, iclass 20, count 0 2006.285.23:43:10.02#ibcon#about to read 6, iclass 20, count 0 2006.285.23:43:10.02#ibcon#read 6, iclass 20, count 0 2006.285.23:43:10.02#ibcon#end of sib2, iclass 20, count 0 2006.285.23:43:10.02#ibcon#*mode == 0, iclass 20, count 0 2006.285.23:43:10.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.23:43:10.02#ibcon#[25=USB\r\n] 2006.285.23:43:10.02#ibcon#*before write, iclass 20, count 0 2006.285.23:43:10.02#ibcon#enter sib2, iclass 20, count 0 2006.285.23:43:10.02#ibcon#flushed, iclass 20, count 0 2006.285.23:43:10.02#ibcon#about to write, iclass 20, count 0 2006.285.23:43:10.02#ibcon#wrote, iclass 20, count 0 2006.285.23:43:10.02#ibcon#about to read 3, iclass 20, count 0 2006.285.23:43:10.05#ibcon#read 3, iclass 20, count 0 2006.285.23:43:10.05#ibcon#about to read 4, iclass 20, count 0 2006.285.23:43:10.05#ibcon#read 4, iclass 20, count 0 2006.285.23:43:10.05#ibcon#about to read 5, iclass 20, count 0 2006.285.23:43:10.05#ibcon#read 5, iclass 20, count 0 2006.285.23:43:10.05#ibcon#about to read 6, iclass 20, count 0 2006.285.23:43:10.05#ibcon#read 6, iclass 20, count 0 2006.285.23:43:10.05#ibcon#end of sib2, iclass 20, count 0 2006.285.23:43:10.05#ibcon#*after write, iclass 20, count 0 2006.285.23:43:10.05#ibcon#*before return 0, iclass 20, count 0 2006.285.23:43:10.05#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:43:10.05#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:43:10.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.23:43:10.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.23:43:10.05$vck44/valo=3,564.99 2006.285.23:43:10.05#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.23:43:10.05#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.23:43:10.05#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:10.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:43:10.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:43:10.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:43:10.05#ibcon#enter wrdev, iclass 22, count 0 2006.285.23:43:10.05#ibcon#first serial, iclass 22, count 0 2006.285.23:43:10.05#ibcon#enter sib2, iclass 22, count 0 2006.285.23:43:10.05#ibcon#flushed, iclass 22, count 0 2006.285.23:43:10.05#ibcon#about to write, iclass 22, count 0 2006.285.23:43:10.05#ibcon#wrote, iclass 22, count 0 2006.285.23:43:10.05#ibcon#about to read 3, iclass 22, count 0 2006.285.23:43:10.07#ibcon#read 3, iclass 22, count 0 2006.285.23:43:10.07#ibcon#about to read 4, iclass 22, count 0 2006.285.23:43:10.07#ibcon#read 4, iclass 22, count 0 2006.285.23:43:10.07#ibcon#about to read 5, iclass 22, count 0 2006.285.23:43:10.07#ibcon#read 5, iclass 22, count 0 2006.285.23:43:10.07#ibcon#about to read 6, iclass 22, count 0 2006.285.23:43:10.07#ibcon#read 6, iclass 22, count 0 2006.285.23:43:10.07#ibcon#end of sib2, iclass 22, count 0 2006.285.23:43:10.07#ibcon#*mode == 0, iclass 22, count 0 2006.285.23:43:10.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.23:43:10.07#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.23:43:10.07#ibcon#*before write, iclass 22, count 0 2006.285.23:43:10.07#ibcon#enter sib2, iclass 22, count 0 2006.285.23:43:10.07#ibcon#flushed, iclass 22, count 0 2006.285.23:43:10.07#ibcon#about to write, iclass 22, count 0 2006.285.23:43:10.07#ibcon#wrote, iclass 22, count 0 2006.285.23:43:10.07#ibcon#about to read 3, iclass 22, count 0 2006.285.23:43:10.11#ibcon#read 3, iclass 22, count 0 2006.285.23:43:10.11#ibcon#about to read 4, iclass 22, count 0 2006.285.23:43:10.11#ibcon#read 4, iclass 22, count 0 2006.285.23:43:10.11#ibcon#about to read 5, iclass 22, count 0 2006.285.23:43:10.11#ibcon#read 5, iclass 22, count 0 2006.285.23:43:10.11#ibcon#about to read 6, iclass 22, count 0 2006.285.23:43:10.11#ibcon#read 6, iclass 22, count 0 2006.285.23:43:10.11#ibcon#end of sib2, iclass 22, count 0 2006.285.23:43:10.11#ibcon#*after write, iclass 22, count 0 2006.285.23:43:10.11#ibcon#*before return 0, iclass 22, count 0 2006.285.23:43:10.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:43:10.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:43:10.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.23:43:10.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.23:43:10.11$vck44/va=3,7 2006.285.23:43:10.11#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.23:43:10.11#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.23:43:10.11#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:10.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:43:10.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:43:10.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:43:10.17#ibcon#enter wrdev, iclass 24, count 2 2006.285.23:43:10.17#ibcon#first serial, iclass 24, count 2 2006.285.23:43:10.17#ibcon#enter sib2, iclass 24, count 2 2006.285.23:43:10.17#ibcon#flushed, iclass 24, count 2 2006.285.23:43:10.17#ibcon#about to write, iclass 24, count 2 2006.285.23:43:10.17#ibcon#wrote, iclass 24, count 2 2006.285.23:43:10.17#ibcon#about to read 3, iclass 24, count 2 2006.285.23:43:10.19#ibcon#read 3, iclass 24, count 2 2006.285.23:43:10.19#ibcon#about to read 4, iclass 24, count 2 2006.285.23:43:10.19#ibcon#read 4, iclass 24, count 2 2006.285.23:43:10.19#ibcon#about to read 5, iclass 24, count 2 2006.285.23:43:10.19#ibcon#read 5, iclass 24, count 2 2006.285.23:43:10.19#ibcon#about to read 6, iclass 24, count 2 2006.285.23:43:10.19#ibcon#read 6, iclass 24, count 2 2006.285.23:43:10.19#ibcon#end of sib2, iclass 24, count 2 2006.285.23:43:10.19#ibcon#*mode == 0, iclass 24, count 2 2006.285.23:43:10.19#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.23:43:10.19#ibcon#[25=AT03-07\r\n] 2006.285.23:43:10.19#ibcon#*before write, iclass 24, count 2 2006.285.23:43:10.19#ibcon#enter sib2, iclass 24, count 2 2006.285.23:43:10.19#ibcon#flushed, iclass 24, count 2 2006.285.23:43:10.19#ibcon#about to write, iclass 24, count 2 2006.285.23:43:10.19#ibcon#wrote, iclass 24, count 2 2006.285.23:43:10.19#ibcon#about to read 3, iclass 24, count 2 2006.285.23:43:10.22#ibcon#read 3, iclass 24, count 2 2006.285.23:43:10.22#ibcon#about to read 4, iclass 24, count 2 2006.285.23:43:10.22#ibcon#read 4, iclass 24, count 2 2006.285.23:43:10.22#ibcon#about to read 5, iclass 24, count 2 2006.285.23:43:10.22#ibcon#read 5, iclass 24, count 2 2006.285.23:43:10.22#ibcon#about to read 6, iclass 24, count 2 2006.285.23:43:10.22#ibcon#read 6, iclass 24, count 2 2006.285.23:43:10.22#ibcon#end of sib2, iclass 24, count 2 2006.285.23:43:10.22#ibcon#*after write, iclass 24, count 2 2006.285.23:43:10.22#ibcon#*before return 0, iclass 24, count 2 2006.285.23:43:10.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:43:10.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:43:10.22#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.23:43:10.22#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:10.22#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:43:10.34#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:43:10.34#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:43:10.34#ibcon#enter wrdev, iclass 24, count 0 2006.285.23:43:10.34#ibcon#first serial, iclass 24, count 0 2006.285.23:43:10.34#ibcon#enter sib2, iclass 24, count 0 2006.285.23:43:10.34#ibcon#flushed, iclass 24, count 0 2006.285.23:43:10.34#ibcon#about to write, iclass 24, count 0 2006.285.23:43:10.34#ibcon#wrote, iclass 24, count 0 2006.285.23:43:10.34#ibcon#about to read 3, iclass 24, count 0 2006.285.23:43:10.36#ibcon#read 3, iclass 24, count 0 2006.285.23:43:10.36#ibcon#about to read 4, iclass 24, count 0 2006.285.23:43:10.36#ibcon#read 4, iclass 24, count 0 2006.285.23:43:10.36#ibcon#about to read 5, iclass 24, count 0 2006.285.23:43:10.36#ibcon#read 5, iclass 24, count 0 2006.285.23:43:10.36#ibcon#about to read 6, iclass 24, count 0 2006.285.23:43:10.36#ibcon#read 6, iclass 24, count 0 2006.285.23:43:10.36#ibcon#end of sib2, iclass 24, count 0 2006.285.23:43:10.36#ibcon#*mode == 0, iclass 24, count 0 2006.285.23:43:10.36#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.23:43:10.36#ibcon#[25=USB\r\n] 2006.285.23:43:10.36#ibcon#*before write, iclass 24, count 0 2006.285.23:43:10.36#ibcon#enter sib2, iclass 24, count 0 2006.285.23:43:10.36#ibcon#flushed, iclass 24, count 0 2006.285.23:43:10.36#ibcon#about to write, iclass 24, count 0 2006.285.23:43:10.36#ibcon#wrote, iclass 24, count 0 2006.285.23:43:10.36#ibcon#about to read 3, iclass 24, count 0 2006.285.23:43:10.39#ibcon#read 3, iclass 24, count 0 2006.285.23:43:10.39#ibcon#about to read 4, iclass 24, count 0 2006.285.23:43:10.39#ibcon#read 4, iclass 24, count 0 2006.285.23:43:10.39#ibcon#about to read 5, iclass 24, count 0 2006.285.23:43:10.39#ibcon#read 5, iclass 24, count 0 2006.285.23:43:10.39#ibcon#about to read 6, iclass 24, count 0 2006.285.23:43:10.39#ibcon#read 6, iclass 24, count 0 2006.285.23:43:10.39#ibcon#end of sib2, iclass 24, count 0 2006.285.23:43:10.39#ibcon#*after write, iclass 24, count 0 2006.285.23:43:10.39#ibcon#*before return 0, iclass 24, count 0 2006.285.23:43:10.39#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:43:10.39#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:43:10.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.23:43:10.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.23:43:10.39$vck44/valo=4,624.99 2006.285.23:43:10.39#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.23:43:10.39#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.23:43:10.39#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:10.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:43:10.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:43:10.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:43:10.39#ibcon#enter wrdev, iclass 26, count 0 2006.285.23:43:10.39#ibcon#first serial, iclass 26, count 0 2006.285.23:43:10.39#ibcon#enter sib2, iclass 26, count 0 2006.285.23:43:10.39#ibcon#flushed, iclass 26, count 0 2006.285.23:43:10.39#ibcon#about to write, iclass 26, count 0 2006.285.23:43:10.39#ibcon#wrote, iclass 26, count 0 2006.285.23:43:10.39#ibcon#about to read 3, iclass 26, count 0 2006.285.23:43:10.41#ibcon#read 3, iclass 26, count 0 2006.285.23:43:10.41#ibcon#about to read 4, iclass 26, count 0 2006.285.23:43:10.41#ibcon#read 4, iclass 26, count 0 2006.285.23:43:10.41#ibcon#about to read 5, iclass 26, count 0 2006.285.23:43:10.41#ibcon#read 5, iclass 26, count 0 2006.285.23:43:10.41#ibcon#about to read 6, iclass 26, count 0 2006.285.23:43:10.41#ibcon#read 6, iclass 26, count 0 2006.285.23:43:10.41#ibcon#end of sib2, iclass 26, count 0 2006.285.23:43:10.41#ibcon#*mode == 0, iclass 26, count 0 2006.285.23:43:10.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.23:43:10.41#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.23:43:10.41#ibcon#*before write, iclass 26, count 0 2006.285.23:43:10.41#ibcon#enter sib2, iclass 26, count 0 2006.285.23:43:10.41#ibcon#flushed, iclass 26, count 0 2006.285.23:43:10.41#ibcon#about to write, iclass 26, count 0 2006.285.23:43:10.41#ibcon#wrote, iclass 26, count 0 2006.285.23:43:10.41#ibcon#about to read 3, iclass 26, count 0 2006.285.23:43:10.45#ibcon#read 3, iclass 26, count 0 2006.285.23:43:10.45#ibcon#about to read 4, iclass 26, count 0 2006.285.23:43:10.45#ibcon#read 4, iclass 26, count 0 2006.285.23:43:10.45#ibcon#about to read 5, iclass 26, count 0 2006.285.23:43:10.45#ibcon#read 5, iclass 26, count 0 2006.285.23:43:10.45#ibcon#about to read 6, iclass 26, count 0 2006.285.23:43:10.45#ibcon#read 6, iclass 26, count 0 2006.285.23:43:10.45#ibcon#end of sib2, iclass 26, count 0 2006.285.23:43:10.45#ibcon#*after write, iclass 26, count 0 2006.285.23:43:10.45#ibcon#*before return 0, iclass 26, count 0 2006.285.23:43:10.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:43:10.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:43:10.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.23:43:10.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.23:43:10.45$vck44/va=4,6 2006.285.23:43:10.45#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.23:43:10.45#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.23:43:10.45#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:10.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:43:10.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:43:10.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:43:10.51#ibcon#enter wrdev, iclass 28, count 2 2006.285.23:43:10.51#ibcon#first serial, iclass 28, count 2 2006.285.23:43:10.51#ibcon#enter sib2, iclass 28, count 2 2006.285.23:43:10.51#ibcon#flushed, iclass 28, count 2 2006.285.23:43:10.51#ibcon#about to write, iclass 28, count 2 2006.285.23:43:10.51#ibcon#wrote, iclass 28, count 2 2006.285.23:43:10.51#ibcon#about to read 3, iclass 28, count 2 2006.285.23:43:10.53#ibcon#read 3, iclass 28, count 2 2006.285.23:43:10.53#ibcon#about to read 4, iclass 28, count 2 2006.285.23:43:10.53#ibcon#read 4, iclass 28, count 2 2006.285.23:43:10.53#ibcon#about to read 5, iclass 28, count 2 2006.285.23:43:10.53#ibcon#read 5, iclass 28, count 2 2006.285.23:43:10.53#ibcon#about to read 6, iclass 28, count 2 2006.285.23:43:10.53#ibcon#read 6, iclass 28, count 2 2006.285.23:43:10.53#ibcon#end of sib2, iclass 28, count 2 2006.285.23:43:10.53#ibcon#*mode == 0, iclass 28, count 2 2006.285.23:43:10.53#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.23:43:10.53#ibcon#[25=AT04-06\r\n] 2006.285.23:43:10.53#ibcon#*before write, iclass 28, count 2 2006.285.23:43:10.53#ibcon#enter sib2, iclass 28, count 2 2006.285.23:43:10.53#ibcon#flushed, iclass 28, count 2 2006.285.23:43:10.53#ibcon#about to write, iclass 28, count 2 2006.285.23:43:10.53#ibcon#wrote, iclass 28, count 2 2006.285.23:43:10.53#ibcon#about to read 3, iclass 28, count 2 2006.285.23:43:10.56#ibcon#read 3, iclass 28, count 2 2006.285.23:43:10.56#ibcon#about to read 4, iclass 28, count 2 2006.285.23:43:10.56#ibcon#read 4, iclass 28, count 2 2006.285.23:43:10.56#ibcon#about to read 5, iclass 28, count 2 2006.285.23:43:10.56#ibcon#read 5, iclass 28, count 2 2006.285.23:43:10.56#ibcon#about to read 6, iclass 28, count 2 2006.285.23:43:10.56#ibcon#read 6, iclass 28, count 2 2006.285.23:43:10.56#ibcon#end of sib2, iclass 28, count 2 2006.285.23:43:10.56#ibcon#*after write, iclass 28, count 2 2006.285.23:43:10.56#ibcon#*before return 0, iclass 28, count 2 2006.285.23:43:10.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:43:10.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:43:10.56#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.23:43:10.56#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:10.56#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:43:10.68#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:43:10.68#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:43:10.68#ibcon#enter wrdev, iclass 28, count 0 2006.285.23:43:10.68#ibcon#first serial, iclass 28, count 0 2006.285.23:43:10.68#ibcon#enter sib2, iclass 28, count 0 2006.285.23:43:10.68#ibcon#flushed, iclass 28, count 0 2006.285.23:43:10.68#ibcon#about to write, iclass 28, count 0 2006.285.23:43:10.68#ibcon#wrote, iclass 28, count 0 2006.285.23:43:10.68#ibcon#about to read 3, iclass 28, count 0 2006.285.23:43:10.70#ibcon#read 3, iclass 28, count 0 2006.285.23:43:10.70#ibcon#about to read 4, iclass 28, count 0 2006.285.23:43:10.70#ibcon#read 4, iclass 28, count 0 2006.285.23:43:10.70#ibcon#about to read 5, iclass 28, count 0 2006.285.23:43:10.70#ibcon#read 5, iclass 28, count 0 2006.285.23:43:10.70#ibcon#about to read 6, iclass 28, count 0 2006.285.23:43:10.70#ibcon#read 6, iclass 28, count 0 2006.285.23:43:10.70#ibcon#end of sib2, iclass 28, count 0 2006.285.23:43:10.70#ibcon#*mode == 0, iclass 28, count 0 2006.285.23:43:10.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.23:43:10.70#ibcon#[25=USB\r\n] 2006.285.23:43:10.70#ibcon#*before write, iclass 28, count 0 2006.285.23:43:10.70#ibcon#enter sib2, iclass 28, count 0 2006.285.23:43:10.70#ibcon#flushed, iclass 28, count 0 2006.285.23:43:10.70#ibcon#about to write, iclass 28, count 0 2006.285.23:43:10.70#ibcon#wrote, iclass 28, count 0 2006.285.23:43:10.70#ibcon#about to read 3, iclass 28, count 0 2006.285.23:43:10.73#ibcon#read 3, iclass 28, count 0 2006.285.23:43:10.73#ibcon#about to read 4, iclass 28, count 0 2006.285.23:43:10.73#ibcon#read 4, iclass 28, count 0 2006.285.23:43:10.73#ibcon#about to read 5, iclass 28, count 0 2006.285.23:43:10.73#ibcon#read 5, iclass 28, count 0 2006.285.23:43:10.73#ibcon#about to read 6, iclass 28, count 0 2006.285.23:43:10.73#ibcon#read 6, iclass 28, count 0 2006.285.23:43:10.73#ibcon#end of sib2, iclass 28, count 0 2006.285.23:43:10.73#ibcon#*after write, iclass 28, count 0 2006.285.23:43:10.73#ibcon#*before return 0, iclass 28, count 0 2006.285.23:43:10.73#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:43:10.73#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:43:10.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.23:43:10.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.23:43:10.73$vck44/valo=5,734.99 2006.285.23:43:10.73#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.23:43:10.73#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.23:43:10.73#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:10.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:43:10.73#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:43:10.73#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:43:10.73#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:43:10.73#ibcon#first serial, iclass 30, count 0 2006.285.23:43:10.73#ibcon#enter sib2, iclass 30, count 0 2006.285.23:43:10.73#ibcon#flushed, iclass 30, count 0 2006.285.23:43:10.73#ibcon#about to write, iclass 30, count 0 2006.285.23:43:10.73#ibcon#wrote, iclass 30, count 0 2006.285.23:43:10.73#ibcon#about to read 3, iclass 30, count 0 2006.285.23:43:10.75#ibcon#read 3, iclass 30, count 0 2006.285.23:43:10.75#ibcon#about to read 4, iclass 30, count 0 2006.285.23:43:10.75#ibcon#read 4, iclass 30, count 0 2006.285.23:43:10.75#ibcon#about to read 5, iclass 30, count 0 2006.285.23:43:10.75#ibcon#read 5, iclass 30, count 0 2006.285.23:43:10.75#ibcon#about to read 6, iclass 30, count 0 2006.285.23:43:10.75#ibcon#read 6, iclass 30, count 0 2006.285.23:43:10.75#ibcon#end of sib2, iclass 30, count 0 2006.285.23:43:10.75#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:43:10.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:43:10.75#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.23:43:10.75#ibcon#*before write, iclass 30, count 0 2006.285.23:43:10.75#ibcon#enter sib2, iclass 30, count 0 2006.285.23:43:10.75#ibcon#flushed, iclass 30, count 0 2006.285.23:43:10.75#ibcon#about to write, iclass 30, count 0 2006.285.23:43:10.75#ibcon#wrote, iclass 30, count 0 2006.285.23:43:10.75#ibcon#about to read 3, iclass 30, count 0 2006.285.23:43:10.79#ibcon#read 3, iclass 30, count 0 2006.285.23:43:10.79#ibcon#about to read 4, iclass 30, count 0 2006.285.23:43:10.79#ibcon#read 4, iclass 30, count 0 2006.285.23:43:10.79#ibcon#about to read 5, iclass 30, count 0 2006.285.23:43:10.79#ibcon#read 5, iclass 30, count 0 2006.285.23:43:10.79#ibcon#about to read 6, iclass 30, count 0 2006.285.23:43:10.79#ibcon#read 6, iclass 30, count 0 2006.285.23:43:10.79#ibcon#end of sib2, iclass 30, count 0 2006.285.23:43:10.79#ibcon#*after write, iclass 30, count 0 2006.285.23:43:10.79#ibcon#*before return 0, iclass 30, count 0 2006.285.23:43:10.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:43:10.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:43:10.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:43:10.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:43:10.79$vck44/va=5,3 2006.285.23:43:10.79#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.23:43:10.79#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.23:43:10.79#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:10.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:43:10.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:43:10.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:43:10.85#ibcon#enter wrdev, iclass 32, count 2 2006.285.23:43:10.85#ibcon#first serial, iclass 32, count 2 2006.285.23:43:10.85#ibcon#enter sib2, iclass 32, count 2 2006.285.23:43:10.85#ibcon#flushed, iclass 32, count 2 2006.285.23:43:10.85#ibcon#about to write, iclass 32, count 2 2006.285.23:43:10.85#ibcon#wrote, iclass 32, count 2 2006.285.23:43:10.85#ibcon#about to read 3, iclass 32, count 2 2006.285.23:43:10.87#ibcon#read 3, iclass 32, count 2 2006.285.23:43:10.87#ibcon#about to read 4, iclass 32, count 2 2006.285.23:43:10.87#ibcon#read 4, iclass 32, count 2 2006.285.23:43:10.87#ibcon#about to read 5, iclass 32, count 2 2006.285.23:43:10.87#ibcon#read 5, iclass 32, count 2 2006.285.23:43:10.87#ibcon#about to read 6, iclass 32, count 2 2006.285.23:43:10.87#ibcon#read 6, iclass 32, count 2 2006.285.23:43:10.87#ibcon#end of sib2, iclass 32, count 2 2006.285.23:43:10.87#ibcon#*mode == 0, iclass 32, count 2 2006.285.23:43:10.87#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.23:43:10.87#ibcon#[25=AT05-03\r\n] 2006.285.23:43:10.87#ibcon#*before write, iclass 32, count 2 2006.285.23:43:10.87#ibcon#enter sib2, iclass 32, count 2 2006.285.23:43:10.87#ibcon#flushed, iclass 32, count 2 2006.285.23:43:10.87#ibcon#about to write, iclass 32, count 2 2006.285.23:43:10.87#ibcon#wrote, iclass 32, count 2 2006.285.23:43:10.87#ibcon#about to read 3, iclass 32, count 2 2006.285.23:43:10.90#ibcon#read 3, iclass 32, count 2 2006.285.23:43:10.90#ibcon#about to read 4, iclass 32, count 2 2006.285.23:43:10.90#ibcon#read 4, iclass 32, count 2 2006.285.23:43:10.90#ibcon#about to read 5, iclass 32, count 2 2006.285.23:43:10.90#ibcon#read 5, iclass 32, count 2 2006.285.23:43:10.90#ibcon#about to read 6, iclass 32, count 2 2006.285.23:43:10.90#ibcon#read 6, iclass 32, count 2 2006.285.23:43:10.90#ibcon#end of sib2, iclass 32, count 2 2006.285.23:43:10.90#ibcon#*after write, iclass 32, count 2 2006.285.23:43:10.90#ibcon#*before return 0, iclass 32, count 2 2006.285.23:43:10.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:43:10.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:43:10.90#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.23:43:10.90#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:10.90#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:43:11.02#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:43:11.02#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:43:11.02#ibcon#enter wrdev, iclass 32, count 0 2006.285.23:43:11.02#ibcon#first serial, iclass 32, count 0 2006.285.23:43:11.02#ibcon#enter sib2, iclass 32, count 0 2006.285.23:43:11.02#ibcon#flushed, iclass 32, count 0 2006.285.23:43:11.02#ibcon#about to write, iclass 32, count 0 2006.285.23:43:11.02#ibcon#wrote, iclass 32, count 0 2006.285.23:43:11.02#ibcon#about to read 3, iclass 32, count 0 2006.285.23:43:11.04#ibcon#read 3, iclass 32, count 0 2006.285.23:43:11.04#ibcon#about to read 4, iclass 32, count 0 2006.285.23:43:11.04#ibcon#read 4, iclass 32, count 0 2006.285.23:43:11.04#ibcon#about to read 5, iclass 32, count 0 2006.285.23:43:11.04#ibcon#read 5, iclass 32, count 0 2006.285.23:43:11.04#ibcon#about to read 6, iclass 32, count 0 2006.285.23:43:11.04#ibcon#read 6, iclass 32, count 0 2006.285.23:43:11.04#ibcon#end of sib2, iclass 32, count 0 2006.285.23:43:11.04#ibcon#*mode == 0, iclass 32, count 0 2006.285.23:43:11.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.23:43:11.04#ibcon#[25=USB\r\n] 2006.285.23:43:11.04#ibcon#*before write, iclass 32, count 0 2006.285.23:43:11.04#ibcon#enter sib2, iclass 32, count 0 2006.285.23:43:11.04#ibcon#flushed, iclass 32, count 0 2006.285.23:43:11.04#ibcon#about to write, iclass 32, count 0 2006.285.23:43:11.04#ibcon#wrote, iclass 32, count 0 2006.285.23:43:11.04#ibcon#about to read 3, iclass 32, count 0 2006.285.23:43:11.07#ibcon#read 3, iclass 32, count 0 2006.285.23:43:11.07#ibcon#about to read 4, iclass 32, count 0 2006.285.23:43:11.07#ibcon#read 4, iclass 32, count 0 2006.285.23:43:11.07#ibcon#about to read 5, iclass 32, count 0 2006.285.23:43:11.07#ibcon#read 5, iclass 32, count 0 2006.285.23:43:11.07#ibcon#about to read 6, iclass 32, count 0 2006.285.23:43:11.07#ibcon#read 6, iclass 32, count 0 2006.285.23:43:11.07#ibcon#end of sib2, iclass 32, count 0 2006.285.23:43:11.07#ibcon#*after write, iclass 32, count 0 2006.285.23:43:11.07#ibcon#*before return 0, iclass 32, count 0 2006.285.23:43:11.07#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:43:11.07#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:43:11.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.23:43:11.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.23:43:11.07$vck44/valo=6,814.99 2006.285.23:43:11.07#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.23:43:11.07#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.23:43:11.07#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:11.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:43:11.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:43:11.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:43:11.07#ibcon#enter wrdev, iclass 34, count 0 2006.285.23:43:11.07#ibcon#first serial, iclass 34, count 0 2006.285.23:43:11.07#ibcon#enter sib2, iclass 34, count 0 2006.285.23:43:11.07#ibcon#flushed, iclass 34, count 0 2006.285.23:43:11.07#ibcon#about to write, iclass 34, count 0 2006.285.23:43:11.07#ibcon#wrote, iclass 34, count 0 2006.285.23:43:11.07#ibcon#about to read 3, iclass 34, count 0 2006.285.23:43:11.09#ibcon#read 3, iclass 34, count 0 2006.285.23:43:11.09#ibcon#about to read 4, iclass 34, count 0 2006.285.23:43:11.09#ibcon#read 4, iclass 34, count 0 2006.285.23:43:11.09#ibcon#about to read 5, iclass 34, count 0 2006.285.23:43:11.09#ibcon#read 5, iclass 34, count 0 2006.285.23:43:11.09#ibcon#about to read 6, iclass 34, count 0 2006.285.23:43:11.09#ibcon#read 6, iclass 34, count 0 2006.285.23:43:11.09#ibcon#end of sib2, iclass 34, count 0 2006.285.23:43:11.09#ibcon#*mode == 0, iclass 34, count 0 2006.285.23:43:11.09#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.23:43:11.09#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.23:43:11.09#ibcon#*before write, iclass 34, count 0 2006.285.23:43:11.09#ibcon#enter sib2, iclass 34, count 0 2006.285.23:43:11.09#ibcon#flushed, iclass 34, count 0 2006.285.23:43:11.09#ibcon#about to write, iclass 34, count 0 2006.285.23:43:11.09#ibcon#wrote, iclass 34, count 0 2006.285.23:43:11.09#ibcon#about to read 3, iclass 34, count 0 2006.285.23:43:11.13#ibcon#read 3, iclass 34, count 0 2006.285.23:43:11.13#ibcon#about to read 4, iclass 34, count 0 2006.285.23:43:11.13#ibcon#read 4, iclass 34, count 0 2006.285.23:43:11.13#ibcon#about to read 5, iclass 34, count 0 2006.285.23:43:11.13#ibcon#read 5, iclass 34, count 0 2006.285.23:43:11.13#ibcon#about to read 6, iclass 34, count 0 2006.285.23:43:11.13#ibcon#read 6, iclass 34, count 0 2006.285.23:43:11.13#ibcon#end of sib2, iclass 34, count 0 2006.285.23:43:11.13#ibcon#*after write, iclass 34, count 0 2006.285.23:43:11.13#ibcon#*before return 0, iclass 34, count 0 2006.285.23:43:11.13#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:43:11.13#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:43:11.13#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.23:43:11.13#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.23:43:11.13$vck44/va=6,4 2006.285.23:43:11.13#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.23:43:11.13#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.23:43:11.13#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:11.13#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:43:11.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:43:11.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:43:11.19#ibcon#enter wrdev, iclass 36, count 2 2006.285.23:43:11.19#ibcon#first serial, iclass 36, count 2 2006.285.23:43:11.19#ibcon#enter sib2, iclass 36, count 2 2006.285.23:43:11.19#ibcon#flushed, iclass 36, count 2 2006.285.23:43:11.19#ibcon#about to write, iclass 36, count 2 2006.285.23:43:11.19#ibcon#wrote, iclass 36, count 2 2006.285.23:43:11.19#ibcon#about to read 3, iclass 36, count 2 2006.285.23:43:11.21#ibcon#read 3, iclass 36, count 2 2006.285.23:43:11.21#ibcon#about to read 4, iclass 36, count 2 2006.285.23:43:11.21#ibcon#read 4, iclass 36, count 2 2006.285.23:43:11.21#ibcon#about to read 5, iclass 36, count 2 2006.285.23:43:11.21#ibcon#read 5, iclass 36, count 2 2006.285.23:43:11.21#ibcon#about to read 6, iclass 36, count 2 2006.285.23:43:11.21#ibcon#read 6, iclass 36, count 2 2006.285.23:43:11.21#ibcon#end of sib2, iclass 36, count 2 2006.285.23:43:11.21#ibcon#*mode == 0, iclass 36, count 2 2006.285.23:43:11.21#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.23:43:11.21#ibcon#[25=AT06-04\r\n] 2006.285.23:43:11.21#ibcon#*before write, iclass 36, count 2 2006.285.23:43:11.21#ibcon#enter sib2, iclass 36, count 2 2006.285.23:43:11.21#ibcon#flushed, iclass 36, count 2 2006.285.23:43:11.21#ibcon#about to write, iclass 36, count 2 2006.285.23:43:11.21#ibcon#wrote, iclass 36, count 2 2006.285.23:43:11.21#ibcon#about to read 3, iclass 36, count 2 2006.285.23:43:11.24#ibcon#read 3, iclass 36, count 2 2006.285.23:43:11.24#ibcon#about to read 4, iclass 36, count 2 2006.285.23:43:11.24#ibcon#read 4, iclass 36, count 2 2006.285.23:43:11.24#ibcon#about to read 5, iclass 36, count 2 2006.285.23:43:11.24#ibcon#read 5, iclass 36, count 2 2006.285.23:43:11.24#ibcon#about to read 6, iclass 36, count 2 2006.285.23:43:11.24#ibcon#read 6, iclass 36, count 2 2006.285.23:43:11.24#ibcon#end of sib2, iclass 36, count 2 2006.285.23:43:11.24#ibcon#*after write, iclass 36, count 2 2006.285.23:43:11.24#ibcon#*before return 0, iclass 36, count 2 2006.285.23:43:11.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:43:11.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:43:11.24#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.23:43:11.24#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:11.24#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:43:11.36#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:43:11.36#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:43:11.36#ibcon#enter wrdev, iclass 36, count 0 2006.285.23:43:11.36#ibcon#first serial, iclass 36, count 0 2006.285.23:43:11.36#ibcon#enter sib2, iclass 36, count 0 2006.285.23:43:11.36#ibcon#flushed, iclass 36, count 0 2006.285.23:43:11.36#ibcon#about to write, iclass 36, count 0 2006.285.23:43:11.36#ibcon#wrote, iclass 36, count 0 2006.285.23:43:11.36#ibcon#about to read 3, iclass 36, count 0 2006.285.23:43:11.38#ibcon#read 3, iclass 36, count 0 2006.285.23:43:11.38#ibcon#about to read 4, iclass 36, count 0 2006.285.23:43:11.38#ibcon#read 4, iclass 36, count 0 2006.285.23:43:11.38#ibcon#about to read 5, iclass 36, count 0 2006.285.23:43:11.38#ibcon#read 5, iclass 36, count 0 2006.285.23:43:11.38#ibcon#about to read 6, iclass 36, count 0 2006.285.23:43:11.38#ibcon#read 6, iclass 36, count 0 2006.285.23:43:11.38#ibcon#end of sib2, iclass 36, count 0 2006.285.23:43:11.38#ibcon#*mode == 0, iclass 36, count 0 2006.285.23:43:11.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.23:43:11.38#ibcon#[25=USB\r\n] 2006.285.23:43:11.38#ibcon#*before write, iclass 36, count 0 2006.285.23:43:11.38#ibcon#enter sib2, iclass 36, count 0 2006.285.23:43:11.38#ibcon#flushed, iclass 36, count 0 2006.285.23:43:11.38#ibcon#about to write, iclass 36, count 0 2006.285.23:43:11.38#ibcon#wrote, iclass 36, count 0 2006.285.23:43:11.38#ibcon#about to read 3, iclass 36, count 0 2006.285.23:43:11.41#ibcon#read 3, iclass 36, count 0 2006.285.23:43:11.41#ibcon#about to read 4, iclass 36, count 0 2006.285.23:43:11.41#ibcon#read 4, iclass 36, count 0 2006.285.23:43:11.41#ibcon#about to read 5, iclass 36, count 0 2006.285.23:43:11.41#ibcon#read 5, iclass 36, count 0 2006.285.23:43:11.41#ibcon#about to read 6, iclass 36, count 0 2006.285.23:43:11.41#ibcon#read 6, iclass 36, count 0 2006.285.23:43:11.41#ibcon#end of sib2, iclass 36, count 0 2006.285.23:43:11.41#ibcon#*after write, iclass 36, count 0 2006.285.23:43:11.41#ibcon#*before return 0, iclass 36, count 0 2006.285.23:43:11.41#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:43:11.41#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:43:11.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.23:43:11.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.23:43:11.41$vck44/valo=7,864.99 2006.285.23:43:11.41#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.23:43:11.41#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.23:43:11.41#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:11.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:43:11.41#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:43:11.41#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:43:11.41#ibcon#enter wrdev, iclass 38, count 0 2006.285.23:43:11.41#ibcon#first serial, iclass 38, count 0 2006.285.23:43:11.41#ibcon#enter sib2, iclass 38, count 0 2006.285.23:43:11.41#ibcon#flushed, iclass 38, count 0 2006.285.23:43:11.41#ibcon#about to write, iclass 38, count 0 2006.285.23:43:11.41#ibcon#wrote, iclass 38, count 0 2006.285.23:43:11.41#ibcon#about to read 3, iclass 38, count 0 2006.285.23:43:11.43#ibcon#read 3, iclass 38, count 0 2006.285.23:43:11.43#ibcon#about to read 4, iclass 38, count 0 2006.285.23:43:11.43#ibcon#read 4, iclass 38, count 0 2006.285.23:43:11.43#ibcon#about to read 5, iclass 38, count 0 2006.285.23:43:11.43#ibcon#read 5, iclass 38, count 0 2006.285.23:43:11.43#ibcon#about to read 6, iclass 38, count 0 2006.285.23:43:11.43#ibcon#read 6, iclass 38, count 0 2006.285.23:43:11.43#ibcon#end of sib2, iclass 38, count 0 2006.285.23:43:11.43#ibcon#*mode == 0, iclass 38, count 0 2006.285.23:43:11.43#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.23:43:11.43#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.23:43:11.43#ibcon#*before write, iclass 38, count 0 2006.285.23:43:11.43#ibcon#enter sib2, iclass 38, count 0 2006.285.23:43:11.43#ibcon#flushed, iclass 38, count 0 2006.285.23:43:11.43#ibcon#about to write, iclass 38, count 0 2006.285.23:43:11.43#ibcon#wrote, iclass 38, count 0 2006.285.23:43:11.43#ibcon#about to read 3, iclass 38, count 0 2006.285.23:43:11.47#ibcon#read 3, iclass 38, count 0 2006.285.23:43:11.47#ibcon#about to read 4, iclass 38, count 0 2006.285.23:43:11.47#ibcon#read 4, iclass 38, count 0 2006.285.23:43:11.47#ibcon#about to read 5, iclass 38, count 0 2006.285.23:43:11.47#ibcon#read 5, iclass 38, count 0 2006.285.23:43:11.47#ibcon#about to read 6, iclass 38, count 0 2006.285.23:43:11.47#ibcon#read 6, iclass 38, count 0 2006.285.23:43:11.47#ibcon#end of sib2, iclass 38, count 0 2006.285.23:43:11.47#ibcon#*after write, iclass 38, count 0 2006.285.23:43:11.47#ibcon#*before return 0, iclass 38, count 0 2006.285.23:43:11.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:43:11.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:43:11.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.23:43:11.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.23:43:11.47$vck44/va=7,4 2006.285.23:43:11.47#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.23:43:11.47#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.23:43:11.47#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:11.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:43:11.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:43:11.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:43:11.53#ibcon#enter wrdev, iclass 40, count 2 2006.285.23:43:11.53#ibcon#first serial, iclass 40, count 2 2006.285.23:43:11.53#ibcon#enter sib2, iclass 40, count 2 2006.285.23:43:11.53#ibcon#flushed, iclass 40, count 2 2006.285.23:43:11.53#ibcon#about to write, iclass 40, count 2 2006.285.23:43:11.53#ibcon#wrote, iclass 40, count 2 2006.285.23:43:11.53#ibcon#about to read 3, iclass 40, count 2 2006.285.23:43:11.55#ibcon#read 3, iclass 40, count 2 2006.285.23:43:11.55#ibcon#about to read 4, iclass 40, count 2 2006.285.23:43:11.55#ibcon#read 4, iclass 40, count 2 2006.285.23:43:11.55#ibcon#about to read 5, iclass 40, count 2 2006.285.23:43:11.55#ibcon#read 5, iclass 40, count 2 2006.285.23:43:11.55#ibcon#about to read 6, iclass 40, count 2 2006.285.23:43:11.55#ibcon#read 6, iclass 40, count 2 2006.285.23:43:11.55#ibcon#end of sib2, iclass 40, count 2 2006.285.23:43:11.55#ibcon#*mode == 0, iclass 40, count 2 2006.285.23:43:11.55#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.23:43:11.55#ibcon#[25=AT07-04\r\n] 2006.285.23:43:11.55#ibcon#*before write, iclass 40, count 2 2006.285.23:43:11.55#ibcon#enter sib2, iclass 40, count 2 2006.285.23:43:11.55#ibcon#flushed, iclass 40, count 2 2006.285.23:43:11.55#ibcon#about to write, iclass 40, count 2 2006.285.23:43:11.55#ibcon#wrote, iclass 40, count 2 2006.285.23:43:11.55#ibcon#about to read 3, iclass 40, count 2 2006.285.23:43:11.58#ibcon#read 3, iclass 40, count 2 2006.285.23:43:11.58#ibcon#about to read 4, iclass 40, count 2 2006.285.23:43:11.58#ibcon#read 4, iclass 40, count 2 2006.285.23:43:11.58#ibcon#about to read 5, iclass 40, count 2 2006.285.23:43:11.58#ibcon#read 5, iclass 40, count 2 2006.285.23:43:11.58#ibcon#about to read 6, iclass 40, count 2 2006.285.23:43:11.58#ibcon#read 6, iclass 40, count 2 2006.285.23:43:11.58#ibcon#end of sib2, iclass 40, count 2 2006.285.23:43:11.58#ibcon#*after write, iclass 40, count 2 2006.285.23:43:11.58#ibcon#*before return 0, iclass 40, count 2 2006.285.23:43:11.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:43:11.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:43:11.58#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.23:43:11.58#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:11.58#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:43:11.70#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:43:11.70#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:43:11.70#ibcon#enter wrdev, iclass 40, count 0 2006.285.23:43:11.70#ibcon#first serial, iclass 40, count 0 2006.285.23:43:11.70#ibcon#enter sib2, iclass 40, count 0 2006.285.23:43:11.70#ibcon#flushed, iclass 40, count 0 2006.285.23:43:11.70#ibcon#about to write, iclass 40, count 0 2006.285.23:43:11.70#ibcon#wrote, iclass 40, count 0 2006.285.23:43:11.70#ibcon#about to read 3, iclass 40, count 0 2006.285.23:43:11.72#ibcon#read 3, iclass 40, count 0 2006.285.23:43:11.72#ibcon#about to read 4, iclass 40, count 0 2006.285.23:43:11.72#ibcon#read 4, iclass 40, count 0 2006.285.23:43:11.72#ibcon#about to read 5, iclass 40, count 0 2006.285.23:43:11.72#ibcon#read 5, iclass 40, count 0 2006.285.23:43:11.72#ibcon#about to read 6, iclass 40, count 0 2006.285.23:43:11.72#ibcon#read 6, iclass 40, count 0 2006.285.23:43:11.72#ibcon#end of sib2, iclass 40, count 0 2006.285.23:43:11.72#ibcon#*mode == 0, iclass 40, count 0 2006.285.23:43:11.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.23:43:11.72#ibcon#[25=USB\r\n] 2006.285.23:43:11.72#ibcon#*before write, iclass 40, count 0 2006.285.23:43:11.72#ibcon#enter sib2, iclass 40, count 0 2006.285.23:43:11.72#ibcon#flushed, iclass 40, count 0 2006.285.23:43:11.72#ibcon#about to write, iclass 40, count 0 2006.285.23:43:11.72#ibcon#wrote, iclass 40, count 0 2006.285.23:43:11.72#ibcon#about to read 3, iclass 40, count 0 2006.285.23:43:11.75#ibcon#read 3, iclass 40, count 0 2006.285.23:43:11.75#ibcon#about to read 4, iclass 40, count 0 2006.285.23:43:11.75#ibcon#read 4, iclass 40, count 0 2006.285.23:43:11.75#ibcon#about to read 5, iclass 40, count 0 2006.285.23:43:11.75#ibcon#read 5, iclass 40, count 0 2006.285.23:43:11.75#ibcon#about to read 6, iclass 40, count 0 2006.285.23:43:11.75#ibcon#read 6, iclass 40, count 0 2006.285.23:43:11.75#ibcon#end of sib2, iclass 40, count 0 2006.285.23:43:11.75#ibcon#*after write, iclass 40, count 0 2006.285.23:43:11.75#ibcon#*before return 0, iclass 40, count 0 2006.285.23:43:11.75#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:43:11.75#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:43:11.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.23:43:11.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.23:43:11.75$vck44/valo=8,884.99 2006.285.23:43:11.75#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.23:43:11.75#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.23:43:11.75#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:11.75#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:43:11.75#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:43:11.75#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:43:11.75#ibcon#enter wrdev, iclass 4, count 0 2006.285.23:43:11.75#ibcon#first serial, iclass 4, count 0 2006.285.23:43:11.75#ibcon#enter sib2, iclass 4, count 0 2006.285.23:43:11.75#ibcon#flushed, iclass 4, count 0 2006.285.23:43:11.75#ibcon#about to write, iclass 4, count 0 2006.285.23:43:11.75#ibcon#wrote, iclass 4, count 0 2006.285.23:43:11.75#ibcon#about to read 3, iclass 4, count 0 2006.285.23:43:11.77#ibcon#read 3, iclass 4, count 0 2006.285.23:43:11.77#ibcon#about to read 4, iclass 4, count 0 2006.285.23:43:11.77#ibcon#read 4, iclass 4, count 0 2006.285.23:43:11.77#ibcon#about to read 5, iclass 4, count 0 2006.285.23:43:11.77#ibcon#read 5, iclass 4, count 0 2006.285.23:43:11.77#ibcon#about to read 6, iclass 4, count 0 2006.285.23:43:11.77#ibcon#read 6, iclass 4, count 0 2006.285.23:43:11.77#ibcon#end of sib2, iclass 4, count 0 2006.285.23:43:11.77#ibcon#*mode == 0, iclass 4, count 0 2006.285.23:43:11.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.23:43:11.77#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.23:43:11.77#ibcon#*before write, iclass 4, count 0 2006.285.23:43:11.77#ibcon#enter sib2, iclass 4, count 0 2006.285.23:43:11.77#ibcon#flushed, iclass 4, count 0 2006.285.23:43:11.77#ibcon#about to write, iclass 4, count 0 2006.285.23:43:11.77#ibcon#wrote, iclass 4, count 0 2006.285.23:43:11.77#ibcon#about to read 3, iclass 4, count 0 2006.285.23:43:11.81#ibcon#read 3, iclass 4, count 0 2006.285.23:43:11.81#ibcon#about to read 4, iclass 4, count 0 2006.285.23:43:11.81#ibcon#read 4, iclass 4, count 0 2006.285.23:43:11.81#ibcon#about to read 5, iclass 4, count 0 2006.285.23:43:11.81#ibcon#read 5, iclass 4, count 0 2006.285.23:43:11.81#ibcon#about to read 6, iclass 4, count 0 2006.285.23:43:11.81#ibcon#read 6, iclass 4, count 0 2006.285.23:43:11.81#ibcon#end of sib2, iclass 4, count 0 2006.285.23:43:11.81#ibcon#*after write, iclass 4, count 0 2006.285.23:43:11.81#ibcon#*before return 0, iclass 4, count 0 2006.285.23:43:11.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:43:11.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:43:11.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.23:43:11.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.23:43:11.81$vck44/va=8,3 2006.285.23:43:11.81#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.285.23:43:11.81#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.285.23:43:11.81#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:11.81#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.23:43:11.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.285.23:43:11.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.23:43:11.87#ibcon#enter wrdev, iclass 6, count 2 2006.285.23:43:11.87#ibcon#first serial, iclass 6, count 2 2006.285.23:43:11.87#ibcon#enter sib2, iclass 6, count 2 2006.285.23:43:11.87#ibcon#flushed, iclass 6, count 2 2006.285.23:43:11.87#ibcon#about to write, iclass 6, count 2 2006.285.23:43:11.87#ibcon#wrote, iclass 6, count 2 2006.285.23:43:11.87#ibcon#about to read 3, iclass 6, count 2 2006.285.23:43:11.89#ibcon#read 3, iclass 6, count 2 2006.285.23:43:11.89#ibcon#about to read 4, iclass 6, count 2 2006.285.23:43:11.89#ibcon#read 4, iclass 6, count 2 2006.285.23:43:11.89#ibcon#about to read 5, iclass 6, count 2 2006.285.23:43:11.89#ibcon#read 5, iclass 6, count 2 2006.285.23:43:11.89#ibcon#about to read 6, iclass 6, count 2 2006.285.23:43:11.89#ibcon#read 6, iclass 6, count 2 2006.285.23:43:11.89#ibcon#end of sib2, iclass 6, count 2 2006.285.23:43:11.89#ibcon#*mode == 0, iclass 6, count 2 2006.285.23:43:11.89#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.285.23:43:11.89#ibcon#[25=AT08-03\r\n] 2006.285.23:43:11.89#ibcon#*before write, iclass 6, count 2 2006.285.23:43:11.89#ibcon#enter sib2, iclass 6, count 2 2006.285.23:43:11.89#ibcon#flushed, iclass 6, count 2 2006.285.23:43:11.89#ibcon#about to write, iclass 6, count 2 2006.285.23:43:11.89#ibcon#wrote, iclass 6, count 2 2006.285.23:43:11.89#ibcon#about to read 3, iclass 6, count 2 2006.285.23:43:11.92#ibcon#read 3, iclass 6, count 2 2006.285.23:43:11.92#ibcon#about to read 4, iclass 6, count 2 2006.285.23:43:11.92#ibcon#read 4, iclass 6, count 2 2006.285.23:43:11.92#ibcon#about to read 5, iclass 6, count 2 2006.285.23:43:11.92#ibcon#read 5, iclass 6, count 2 2006.285.23:43:11.92#ibcon#about to read 6, iclass 6, count 2 2006.285.23:43:11.92#ibcon#read 6, iclass 6, count 2 2006.285.23:43:11.92#ibcon#end of sib2, iclass 6, count 2 2006.285.23:43:11.92#ibcon#*after write, iclass 6, count 2 2006.285.23:43:11.92#ibcon#*before return 0, iclass 6, count 2 2006.285.23:43:11.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.285.23:43:11.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.285.23:43:11.92#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.285.23:43:11.92#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:11.92#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.23:43:12.04#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.285.23:43:12.04#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.23:43:12.04#ibcon#enter wrdev, iclass 6, count 0 2006.285.23:43:12.04#ibcon#first serial, iclass 6, count 0 2006.285.23:43:12.04#ibcon#enter sib2, iclass 6, count 0 2006.285.23:43:12.04#ibcon#flushed, iclass 6, count 0 2006.285.23:43:12.04#ibcon#about to write, iclass 6, count 0 2006.285.23:43:12.04#ibcon#wrote, iclass 6, count 0 2006.285.23:43:12.04#ibcon#about to read 3, iclass 6, count 0 2006.285.23:43:12.06#ibcon#read 3, iclass 6, count 0 2006.285.23:43:12.06#ibcon#about to read 4, iclass 6, count 0 2006.285.23:43:12.06#ibcon#read 4, iclass 6, count 0 2006.285.23:43:12.06#ibcon#about to read 5, iclass 6, count 0 2006.285.23:43:12.06#ibcon#read 5, iclass 6, count 0 2006.285.23:43:12.06#ibcon#about to read 6, iclass 6, count 0 2006.285.23:43:12.06#ibcon#read 6, iclass 6, count 0 2006.285.23:43:12.06#ibcon#end of sib2, iclass 6, count 0 2006.285.23:43:12.06#ibcon#*mode == 0, iclass 6, count 0 2006.285.23:43:12.06#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.23:43:12.06#ibcon#[25=USB\r\n] 2006.285.23:43:12.06#ibcon#*before write, iclass 6, count 0 2006.285.23:43:12.06#ibcon#enter sib2, iclass 6, count 0 2006.285.23:43:12.06#ibcon#flushed, iclass 6, count 0 2006.285.23:43:12.06#ibcon#about to write, iclass 6, count 0 2006.285.23:43:12.06#ibcon#wrote, iclass 6, count 0 2006.285.23:43:12.06#ibcon#about to read 3, iclass 6, count 0 2006.285.23:43:12.09#ibcon#read 3, iclass 6, count 0 2006.285.23:43:12.09#ibcon#about to read 4, iclass 6, count 0 2006.285.23:43:12.09#ibcon#read 4, iclass 6, count 0 2006.285.23:43:12.09#ibcon#about to read 5, iclass 6, count 0 2006.285.23:43:12.09#ibcon#read 5, iclass 6, count 0 2006.285.23:43:12.09#ibcon#about to read 6, iclass 6, count 0 2006.285.23:43:12.09#ibcon#read 6, iclass 6, count 0 2006.285.23:43:12.09#ibcon#end of sib2, iclass 6, count 0 2006.285.23:43:12.09#ibcon#*after write, iclass 6, count 0 2006.285.23:43:12.09#ibcon#*before return 0, iclass 6, count 0 2006.285.23:43:12.09#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.285.23:43:12.09#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.285.23:43:12.09#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.23:43:12.09#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.23:43:12.09$vck44/vblo=1,629.99 2006.285.23:43:12.09#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.285.23:43:12.09#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.285.23:43:12.09#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:12.09#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.23:43:12.09#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.285.23:43:12.09#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.23:43:12.09#ibcon#enter wrdev, iclass 10, count 0 2006.285.23:43:12.09#ibcon#first serial, iclass 10, count 0 2006.285.23:43:12.09#ibcon#enter sib2, iclass 10, count 0 2006.285.23:43:12.09#ibcon#flushed, iclass 10, count 0 2006.285.23:43:12.09#ibcon#about to write, iclass 10, count 0 2006.285.23:43:12.09#ibcon#wrote, iclass 10, count 0 2006.285.23:43:12.09#ibcon#about to read 3, iclass 10, count 0 2006.285.23:43:12.11#ibcon#read 3, iclass 10, count 0 2006.285.23:43:12.11#ibcon#about to read 4, iclass 10, count 0 2006.285.23:43:12.11#ibcon#read 4, iclass 10, count 0 2006.285.23:43:12.11#ibcon#about to read 5, iclass 10, count 0 2006.285.23:43:12.11#ibcon#read 5, iclass 10, count 0 2006.285.23:43:12.11#ibcon#about to read 6, iclass 10, count 0 2006.285.23:43:12.11#ibcon#read 6, iclass 10, count 0 2006.285.23:43:12.11#ibcon#end of sib2, iclass 10, count 0 2006.285.23:43:12.11#ibcon#*mode == 0, iclass 10, count 0 2006.285.23:43:12.11#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.23:43:12.11#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.23:43:12.11#ibcon#*before write, iclass 10, count 0 2006.285.23:43:12.11#ibcon#enter sib2, iclass 10, count 0 2006.285.23:43:12.11#ibcon#flushed, iclass 10, count 0 2006.285.23:43:12.11#ibcon#about to write, iclass 10, count 0 2006.285.23:43:12.11#ibcon#wrote, iclass 10, count 0 2006.285.23:43:12.11#ibcon#about to read 3, iclass 10, count 0 2006.285.23:43:12.15#ibcon#read 3, iclass 10, count 0 2006.285.23:43:12.15#ibcon#about to read 4, iclass 10, count 0 2006.285.23:43:12.15#ibcon#read 4, iclass 10, count 0 2006.285.23:43:12.15#ibcon#about to read 5, iclass 10, count 0 2006.285.23:43:12.15#ibcon#read 5, iclass 10, count 0 2006.285.23:43:12.15#ibcon#about to read 6, iclass 10, count 0 2006.285.23:43:12.15#ibcon#read 6, iclass 10, count 0 2006.285.23:43:12.15#ibcon#end of sib2, iclass 10, count 0 2006.285.23:43:12.15#ibcon#*after write, iclass 10, count 0 2006.285.23:43:12.15#ibcon#*before return 0, iclass 10, count 0 2006.285.23:43:12.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.285.23:43:12.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.285.23:43:12.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.23:43:12.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.23:43:12.15$vck44/vb=1,4 2006.285.23:43:12.15#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.285.23:43:12.15#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.285.23:43:12.15#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:12.15#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.23:43:12.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.285.23:43:12.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.23:43:12.15#ibcon#enter wrdev, iclass 12, count 2 2006.285.23:43:12.15#ibcon#first serial, iclass 12, count 2 2006.285.23:43:12.15#ibcon#enter sib2, iclass 12, count 2 2006.285.23:43:12.15#ibcon#flushed, iclass 12, count 2 2006.285.23:43:12.15#ibcon#about to write, iclass 12, count 2 2006.285.23:43:12.15#ibcon#wrote, iclass 12, count 2 2006.285.23:43:12.15#ibcon#about to read 3, iclass 12, count 2 2006.285.23:43:12.17#ibcon#read 3, iclass 12, count 2 2006.285.23:43:12.17#ibcon#about to read 4, iclass 12, count 2 2006.285.23:43:12.17#ibcon#read 4, iclass 12, count 2 2006.285.23:43:12.17#ibcon#about to read 5, iclass 12, count 2 2006.285.23:43:12.17#ibcon#read 5, iclass 12, count 2 2006.285.23:43:12.17#ibcon#about to read 6, iclass 12, count 2 2006.285.23:43:12.17#ibcon#read 6, iclass 12, count 2 2006.285.23:43:12.17#ibcon#end of sib2, iclass 12, count 2 2006.285.23:43:12.17#ibcon#*mode == 0, iclass 12, count 2 2006.285.23:43:12.17#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.285.23:43:12.17#ibcon#[27=AT01-04\r\n] 2006.285.23:43:12.17#ibcon#*before write, iclass 12, count 2 2006.285.23:43:12.17#ibcon#enter sib2, iclass 12, count 2 2006.285.23:43:12.17#ibcon#flushed, iclass 12, count 2 2006.285.23:43:12.17#ibcon#about to write, iclass 12, count 2 2006.285.23:43:12.17#ibcon#wrote, iclass 12, count 2 2006.285.23:43:12.17#ibcon#about to read 3, iclass 12, count 2 2006.285.23:43:12.20#ibcon#read 3, iclass 12, count 2 2006.285.23:43:12.20#ibcon#about to read 4, iclass 12, count 2 2006.285.23:43:12.20#ibcon#read 4, iclass 12, count 2 2006.285.23:43:12.20#ibcon#about to read 5, iclass 12, count 2 2006.285.23:43:12.20#ibcon#read 5, iclass 12, count 2 2006.285.23:43:12.20#ibcon#about to read 6, iclass 12, count 2 2006.285.23:43:12.20#ibcon#read 6, iclass 12, count 2 2006.285.23:43:12.20#ibcon#end of sib2, iclass 12, count 2 2006.285.23:43:12.20#ibcon#*after write, iclass 12, count 2 2006.285.23:43:12.20#ibcon#*before return 0, iclass 12, count 2 2006.285.23:43:12.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.285.23:43:12.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.285.23:43:12.20#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.285.23:43:12.20#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:12.20#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.23:43:12.32#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.285.23:43:12.32#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.23:43:12.32#ibcon#enter wrdev, iclass 12, count 0 2006.285.23:43:12.32#ibcon#first serial, iclass 12, count 0 2006.285.23:43:12.32#ibcon#enter sib2, iclass 12, count 0 2006.285.23:43:12.32#ibcon#flushed, iclass 12, count 0 2006.285.23:43:12.32#ibcon#about to write, iclass 12, count 0 2006.285.23:43:12.32#ibcon#wrote, iclass 12, count 0 2006.285.23:43:12.32#ibcon#about to read 3, iclass 12, count 0 2006.285.23:43:12.34#ibcon#read 3, iclass 12, count 0 2006.285.23:43:12.34#ibcon#about to read 4, iclass 12, count 0 2006.285.23:43:12.34#ibcon#read 4, iclass 12, count 0 2006.285.23:43:12.34#ibcon#about to read 5, iclass 12, count 0 2006.285.23:43:12.34#ibcon#read 5, iclass 12, count 0 2006.285.23:43:12.34#ibcon#about to read 6, iclass 12, count 0 2006.285.23:43:12.34#ibcon#read 6, iclass 12, count 0 2006.285.23:43:12.34#ibcon#end of sib2, iclass 12, count 0 2006.285.23:43:12.34#ibcon#*mode == 0, iclass 12, count 0 2006.285.23:43:12.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.23:43:12.34#ibcon#[27=USB\r\n] 2006.285.23:43:12.34#ibcon#*before write, iclass 12, count 0 2006.285.23:43:12.34#ibcon#enter sib2, iclass 12, count 0 2006.285.23:43:12.34#ibcon#flushed, iclass 12, count 0 2006.285.23:43:12.34#ibcon#about to write, iclass 12, count 0 2006.285.23:43:12.34#ibcon#wrote, iclass 12, count 0 2006.285.23:43:12.34#ibcon#about to read 3, iclass 12, count 0 2006.285.23:43:12.37#ibcon#read 3, iclass 12, count 0 2006.285.23:43:12.37#ibcon#about to read 4, iclass 12, count 0 2006.285.23:43:12.37#ibcon#read 4, iclass 12, count 0 2006.285.23:43:12.37#ibcon#about to read 5, iclass 12, count 0 2006.285.23:43:12.37#ibcon#read 5, iclass 12, count 0 2006.285.23:43:12.37#ibcon#about to read 6, iclass 12, count 0 2006.285.23:43:12.37#ibcon#read 6, iclass 12, count 0 2006.285.23:43:12.37#ibcon#end of sib2, iclass 12, count 0 2006.285.23:43:12.37#ibcon#*after write, iclass 12, count 0 2006.285.23:43:12.37#ibcon#*before return 0, iclass 12, count 0 2006.285.23:43:12.37#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.285.23:43:12.37#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.285.23:43:12.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.23:43:12.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.23:43:12.37$vck44/vblo=2,634.99 2006.285.23:43:12.37#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.285.23:43:12.37#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.285.23:43:12.37#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:12.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:43:12.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:43:12.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:43:12.37#ibcon#enter wrdev, iclass 14, count 0 2006.285.23:43:12.37#ibcon#first serial, iclass 14, count 0 2006.285.23:43:12.37#ibcon#enter sib2, iclass 14, count 0 2006.285.23:43:12.37#ibcon#flushed, iclass 14, count 0 2006.285.23:43:12.37#ibcon#about to write, iclass 14, count 0 2006.285.23:43:12.37#ibcon#wrote, iclass 14, count 0 2006.285.23:43:12.37#ibcon#about to read 3, iclass 14, count 0 2006.285.23:43:12.39#ibcon#read 3, iclass 14, count 0 2006.285.23:43:12.39#ibcon#about to read 4, iclass 14, count 0 2006.285.23:43:12.39#ibcon#read 4, iclass 14, count 0 2006.285.23:43:12.39#ibcon#about to read 5, iclass 14, count 0 2006.285.23:43:12.39#ibcon#read 5, iclass 14, count 0 2006.285.23:43:12.39#ibcon#about to read 6, iclass 14, count 0 2006.285.23:43:12.39#ibcon#read 6, iclass 14, count 0 2006.285.23:43:12.39#ibcon#end of sib2, iclass 14, count 0 2006.285.23:43:12.39#ibcon#*mode == 0, iclass 14, count 0 2006.285.23:43:12.39#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.23:43:12.39#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.23:43:12.39#ibcon#*before write, iclass 14, count 0 2006.285.23:43:12.39#ibcon#enter sib2, iclass 14, count 0 2006.285.23:43:12.39#ibcon#flushed, iclass 14, count 0 2006.285.23:43:12.39#ibcon#about to write, iclass 14, count 0 2006.285.23:43:12.39#ibcon#wrote, iclass 14, count 0 2006.285.23:43:12.39#ibcon#about to read 3, iclass 14, count 0 2006.285.23:43:12.43#ibcon#read 3, iclass 14, count 0 2006.285.23:43:12.43#ibcon#about to read 4, iclass 14, count 0 2006.285.23:43:12.43#ibcon#read 4, iclass 14, count 0 2006.285.23:43:12.43#ibcon#about to read 5, iclass 14, count 0 2006.285.23:43:12.43#ibcon#read 5, iclass 14, count 0 2006.285.23:43:12.43#ibcon#about to read 6, iclass 14, count 0 2006.285.23:43:12.43#ibcon#read 6, iclass 14, count 0 2006.285.23:43:12.43#ibcon#end of sib2, iclass 14, count 0 2006.285.23:43:12.43#ibcon#*after write, iclass 14, count 0 2006.285.23:43:12.43#ibcon#*before return 0, iclass 14, count 0 2006.285.23:43:12.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:43:12.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.285.23:43:12.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.23:43:12.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.23:43:12.43$vck44/vb=2,5 2006.285.23:43:12.43#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.285.23:43:12.43#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.285.23:43:12.43#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:12.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:43:12.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:43:12.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:43:12.49#ibcon#enter wrdev, iclass 16, count 2 2006.285.23:43:12.49#ibcon#first serial, iclass 16, count 2 2006.285.23:43:12.49#ibcon#enter sib2, iclass 16, count 2 2006.285.23:43:12.49#ibcon#flushed, iclass 16, count 2 2006.285.23:43:12.49#ibcon#about to write, iclass 16, count 2 2006.285.23:43:12.49#ibcon#wrote, iclass 16, count 2 2006.285.23:43:12.49#ibcon#about to read 3, iclass 16, count 2 2006.285.23:43:12.51#ibcon#read 3, iclass 16, count 2 2006.285.23:43:12.51#ibcon#about to read 4, iclass 16, count 2 2006.285.23:43:12.51#ibcon#read 4, iclass 16, count 2 2006.285.23:43:12.51#ibcon#about to read 5, iclass 16, count 2 2006.285.23:43:12.51#ibcon#read 5, iclass 16, count 2 2006.285.23:43:12.51#ibcon#about to read 6, iclass 16, count 2 2006.285.23:43:12.51#ibcon#read 6, iclass 16, count 2 2006.285.23:43:12.51#ibcon#end of sib2, iclass 16, count 2 2006.285.23:43:12.51#ibcon#*mode == 0, iclass 16, count 2 2006.285.23:43:12.51#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.285.23:43:12.51#ibcon#[27=AT02-05\r\n] 2006.285.23:43:12.51#ibcon#*before write, iclass 16, count 2 2006.285.23:43:12.51#ibcon#enter sib2, iclass 16, count 2 2006.285.23:43:12.51#ibcon#flushed, iclass 16, count 2 2006.285.23:43:12.51#ibcon#about to write, iclass 16, count 2 2006.285.23:43:12.51#ibcon#wrote, iclass 16, count 2 2006.285.23:43:12.51#ibcon#about to read 3, iclass 16, count 2 2006.285.23:43:12.54#ibcon#read 3, iclass 16, count 2 2006.285.23:43:12.54#ibcon#about to read 4, iclass 16, count 2 2006.285.23:43:12.54#ibcon#read 4, iclass 16, count 2 2006.285.23:43:12.54#ibcon#about to read 5, iclass 16, count 2 2006.285.23:43:12.54#ibcon#read 5, iclass 16, count 2 2006.285.23:43:12.54#ibcon#about to read 6, iclass 16, count 2 2006.285.23:43:12.54#ibcon#read 6, iclass 16, count 2 2006.285.23:43:12.54#ibcon#end of sib2, iclass 16, count 2 2006.285.23:43:12.54#ibcon#*after write, iclass 16, count 2 2006.285.23:43:12.54#ibcon#*before return 0, iclass 16, count 2 2006.285.23:43:12.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:43:12.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.285.23:43:12.54#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.285.23:43:12.54#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:12.54#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:43:12.66#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:43:12.66#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:43:12.66#ibcon#enter wrdev, iclass 16, count 0 2006.285.23:43:12.66#ibcon#first serial, iclass 16, count 0 2006.285.23:43:12.66#ibcon#enter sib2, iclass 16, count 0 2006.285.23:43:12.66#ibcon#flushed, iclass 16, count 0 2006.285.23:43:12.66#ibcon#about to write, iclass 16, count 0 2006.285.23:43:12.66#ibcon#wrote, iclass 16, count 0 2006.285.23:43:12.66#ibcon#about to read 3, iclass 16, count 0 2006.285.23:43:12.68#ibcon#read 3, iclass 16, count 0 2006.285.23:43:12.68#ibcon#about to read 4, iclass 16, count 0 2006.285.23:43:12.68#ibcon#read 4, iclass 16, count 0 2006.285.23:43:12.68#ibcon#about to read 5, iclass 16, count 0 2006.285.23:43:12.68#ibcon#read 5, iclass 16, count 0 2006.285.23:43:12.68#ibcon#about to read 6, iclass 16, count 0 2006.285.23:43:12.68#ibcon#read 6, iclass 16, count 0 2006.285.23:43:12.68#ibcon#end of sib2, iclass 16, count 0 2006.285.23:43:12.68#ibcon#*mode == 0, iclass 16, count 0 2006.285.23:43:12.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.23:43:12.68#ibcon#[27=USB\r\n] 2006.285.23:43:12.68#ibcon#*before write, iclass 16, count 0 2006.285.23:43:12.68#ibcon#enter sib2, iclass 16, count 0 2006.285.23:43:12.68#ibcon#flushed, iclass 16, count 0 2006.285.23:43:12.68#ibcon#about to write, iclass 16, count 0 2006.285.23:43:12.68#ibcon#wrote, iclass 16, count 0 2006.285.23:43:12.68#ibcon#about to read 3, iclass 16, count 0 2006.285.23:43:12.71#ibcon#read 3, iclass 16, count 0 2006.285.23:43:12.71#ibcon#about to read 4, iclass 16, count 0 2006.285.23:43:12.71#ibcon#read 4, iclass 16, count 0 2006.285.23:43:12.71#ibcon#about to read 5, iclass 16, count 0 2006.285.23:43:12.71#ibcon#read 5, iclass 16, count 0 2006.285.23:43:12.71#ibcon#about to read 6, iclass 16, count 0 2006.285.23:43:12.71#ibcon#read 6, iclass 16, count 0 2006.285.23:43:12.71#ibcon#end of sib2, iclass 16, count 0 2006.285.23:43:12.71#ibcon#*after write, iclass 16, count 0 2006.285.23:43:12.71#ibcon#*before return 0, iclass 16, count 0 2006.285.23:43:12.71#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:43:12.71#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.285.23:43:12.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.23:43:12.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.23:43:12.71$vck44/vblo=3,649.99 2006.285.23:43:12.71#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.285.23:43:12.71#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.285.23:43:12.71#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:12.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:43:12.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:43:12.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:43:12.71#ibcon#enter wrdev, iclass 18, count 0 2006.285.23:43:12.71#ibcon#first serial, iclass 18, count 0 2006.285.23:43:12.71#ibcon#enter sib2, iclass 18, count 0 2006.285.23:43:12.71#ibcon#flushed, iclass 18, count 0 2006.285.23:43:12.71#ibcon#about to write, iclass 18, count 0 2006.285.23:43:12.71#ibcon#wrote, iclass 18, count 0 2006.285.23:43:12.71#ibcon#about to read 3, iclass 18, count 0 2006.285.23:43:12.73#ibcon#read 3, iclass 18, count 0 2006.285.23:43:12.73#ibcon#about to read 4, iclass 18, count 0 2006.285.23:43:12.73#ibcon#read 4, iclass 18, count 0 2006.285.23:43:12.73#ibcon#about to read 5, iclass 18, count 0 2006.285.23:43:12.73#ibcon#read 5, iclass 18, count 0 2006.285.23:43:12.73#ibcon#about to read 6, iclass 18, count 0 2006.285.23:43:12.73#ibcon#read 6, iclass 18, count 0 2006.285.23:43:12.73#ibcon#end of sib2, iclass 18, count 0 2006.285.23:43:12.73#ibcon#*mode == 0, iclass 18, count 0 2006.285.23:43:12.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.23:43:12.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.23:43:12.73#ibcon#*before write, iclass 18, count 0 2006.285.23:43:12.73#ibcon#enter sib2, iclass 18, count 0 2006.285.23:43:12.73#ibcon#flushed, iclass 18, count 0 2006.285.23:43:12.73#ibcon#about to write, iclass 18, count 0 2006.285.23:43:12.73#ibcon#wrote, iclass 18, count 0 2006.285.23:43:12.73#ibcon#about to read 3, iclass 18, count 0 2006.285.23:43:12.77#ibcon#read 3, iclass 18, count 0 2006.285.23:43:12.77#ibcon#about to read 4, iclass 18, count 0 2006.285.23:43:12.77#ibcon#read 4, iclass 18, count 0 2006.285.23:43:12.77#ibcon#about to read 5, iclass 18, count 0 2006.285.23:43:12.77#ibcon#read 5, iclass 18, count 0 2006.285.23:43:12.77#ibcon#about to read 6, iclass 18, count 0 2006.285.23:43:12.77#ibcon#read 6, iclass 18, count 0 2006.285.23:43:12.77#ibcon#end of sib2, iclass 18, count 0 2006.285.23:43:12.77#ibcon#*after write, iclass 18, count 0 2006.285.23:43:12.77#ibcon#*before return 0, iclass 18, count 0 2006.285.23:43:12.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:43:12.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.285.23:43:12.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.23:43:12.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.23:43:12.77$vck44/vb=3,4 2006.285.23:43:12.77#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.285.23:43:12.77#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.285.23:43:12.77#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:12.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:43:12.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:43:12.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:43:12.83#ibcon#enter wrdev, iclass 20, count 2 2006.285.23:43:12.83#ibcon#first serial, iclass 20, count 2 2006.285.23:43:12.83#ibcon#enter sib2, iclass 20, count 2 2006.285.23:43:12.83#ibcon#flushed, iclass 20, count 2 2006.285.23:43:12.83#ibcon#about to write, iclass 20, count 2 2006.285.23:43:12.83#ibcon#wrote, iclass 20, count 2 2006.285.23:43:12.83#ibcon#about to read 3, iclass 20, count 2 2006.285.23:43:12.85#ibcon#read 3, iclass 20, count 2 2006.285.23:43:12.85#ibcon#about to read 4, iclass 20, count 2 2006.285.23:43:12.85#ibcon#read 4, iclass 20, count 2 2006.285.23:43:12.85#ibcon#about to read 5, iclass 20, count 2 2006.285.23:43:12.85#ibcon#read 5, iclass 20, count 2 2006.285.23:43:12.85#ibcon#about to read 6, iclass 20, count 2 2006.285.23:43:12.85#ibcon#read 6, iclass 20, count 2 2006.285.23:43:12.85#ibcon#end of sib2, iclass 20, count 2 2006.285.23:43:12.85#ibcon#*mode == 0, iclass 20, count 2 2006.285.23:43:12.85#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.285.23:43:12.85#ibcon#[27=AT03-04\r\n] 2006.285.23:43:12.85#ibcon#*before write, iclass 20, count 2 2006.285.23:43:12.85#ibcon#enter sib2, iclass 20, count 2 2006.285.23:43:12.85#ibcon#flushed, iclass 20, count 2 2006.285.23:43:12.85#ibcon#about to write, iclass 20, count 2 2006.285.23:43:12.85#ibcon#wrote, iclass 20, count 2 2006.285.23:43:12.85#ibcon#about to read 3, iclass 20, count 2 2006.285.23:43:12.88#ibcon#read 3, iclass 20, count 2 2006.285.23:43:12.88#ibcon#about to read 4, iclass 20, count 2 2006.285.23:43:12.88#ibcon#read 4, iclass 20, count 2 2006.285.23:43:12.88#ibcon#about to read 5, iclass 20, count 2 2006.285.23:43:12.88#ibcon#read 5, iclass 20, count 2 2006.285.23:43:12.88#ibcon#about to read 6, iclass 20, count 2 2006.285.23:43:12.88#ibcon#read 6, iclass 20, count 2 2006.285.23:43:12.88#ibcon#end of sib2, iclass 20, count 2 2006.285.23:43:12.88#ibcon#*after write, iclass 20, count 2 2006.285.23:43:12.88#ibcon#*before return 0, iclass 20, count 2 2006.285.23:43:12.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:43:12.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.285.23:43:12.88#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.285.23:43:12.88#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:12.88#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:43:13.00#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:43:13.00#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:43:13.00#ibcon#enter wrdev, iclass 20, count 0 2006.285.23:43:13.00#ibcon#first serial, iclass 20, count 0 2006.285.23:43:13.00#ibcon#enter sib2, iclass 20, count 0 2006.285.23:43:13.00#ibcon#flushed, iclass 20, count 0 2006.285.23:43:13.00#ibcon#about to write, iclass 20, count 0 2006.285.23:43:13.00#ibcon#wrote, iclass 20, count 0 2006.285.23:43:13.00#ibcon#about to read 3, iclass 20, count 0 2006.285.23:43:13.02#ibcon#read 3, iclass 20, count 0 2006.285.23:43:13.02#ibcon#about to read 4, iclass 20, count 0 2006.285.23:43:13.02#ibcon#read 4, iclass 20, count 0 2006.285.23:43:13.02#ibcon#about to read 5, iclass 20, count 0 2006.285.23:43:13.02#ibcon#read 5, iclass 20, count 0 2006.285.23:43:13.02#ibcon#about to read 6, iclass 20, count 0 2006.285.23:43:13.02#ibcon#read 6, iclass 20, count 0 2006.285.23:43:13.02#ibcon#end of sib2, iclass 20, count 0 2006.285.23:43:13.02#ibcon#*mode == 0, iclass 20, count 0 2006.285.23:43:13.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.23:43:13.02#ibcon#[27=USB\r\n] 2006.285.23:43:13.02#ibcon#*before write, iclass 20, count 0 2006.285.23:43:13.02#ibcon#enter sib2, iclass 20, count 0 2006.285.23:43:13.02#ibcon#flushed, iclass 20, count 0 2006.285.23:43:13.02#ibcon#about to write, iclass 20, count 0 2006.285.23:43:13.02#ibcon#wrote, iclass 20, count 0 2006.285.23:43:13.02#ibcon#about to read 3, iclass 20, count 0 2006.285.23:43:13.05#ibcon#read 3, iclass 20, count 0 2006.285.23:43:13.05#ibcon#about to read 4, iclass 20, count 0 2006.285.23:43:13.05#ibcon#read 4, iclass 20, count 0 2006.285.23:43:13.05#ibcon#about to read 5, iclass 20, count 0 2006.285.23:43:13.05#ibcon#read 5, iclass 20, count 0 2006.285.23:43:13.05#ibcon#about to read 6, iclass 20, count 0 2006.285.23:43:13.05#ibcon#read 6, iclass 20, count 0 2006.285.23:43:13.05#ibcon#end of sib2, iclass 20, count 0 2006.285.23:43:13.05#ibcon#*after write, iclass 20, count 0 2006.285.23:43:13.05#ibcon#*before return 0, iclass 20, count 0 2006.285.23:43:13.05#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:43:13.05#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.285.23:43:13.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.23:43:13.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.23:43:13.05$vck44/vblo=4,679.99 2006.285.23:43:13.05#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.285.23:43:13.05#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.285.23:43:13.05#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:13.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:43:13.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:43:13.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:43:13.05#ibcon#enter wrdev, iclass 22, count 0 2006.285.23:43:13.05#ibcon#first serial, iclass 22, count 0 2006.285.23:43:13.05#ibcon#enter sib2, iclass 22, count 0 2006.285.23:43:13.05#ibcon#flushed, iclass 22, count 0 2006.285.23:43:13.05#ibcon#about to write, iclass 22, count 0 2006.285.23:43:13.05#ibcon#wrote, iclass 22, count 0 2006.285.23:43:13.05#ibcon#about to read 3, iclass 22, count 0 2006.285.23:43:13.07#ibcon#read 3, iclass 22, count 0 2006.285.23:43:13.07#ibcon#about to read 4, iclass 22, count 0 2006.285.23:43:13.07#ibcon#read 4, iclass 22, count 0 2006.285.23:43:13.07#ibcon#about to read 5, iclass 22, count 0 2006.285.23:43:13.07#ibcon#read 5, iclass 22, count 0 2006.285.23:43:13.07#ibcon#about to read 6, iclass 22, count 0 2006.285.23:43:13.07#ibcon#read 6, iclass 22, count 0 2006.285.23:43:13.07#ibcon#end of sib2, iclass 22, count 0 2006.285.23:43:13.07#ibcon#*mode == 0, iclass 22, count 0 2006.285.23:43:13.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.23:43:13.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:43:13.07#ibcon#*before write, iclass 22, count 0 2006.285.23:43:13.07#ibcon#enter sib2, iclass 22, count 0 2006.285.23:43:13.07#ibcon#flushed, iclass 22, count 0 2006.285.23:43:13.07#ibcon#about to write, iclass 22, count 0 2006.285.23:43:13.07#ibcon#wrote, iclass 22, count 0 2006.285.23:43:13.07#ibcon#about to read 3, iclass 22, count 0 2006.285.23:43:13.11#ibcon#read 3, iclass 22, count 0 2006.285.23:43:13.11#ibcon#about to read 4, iclass 22, count 0 2006.285.23:43:13.11#ibcon#read 4, iclass 22, count 0 2006.285.23:43:13.11#ibcon#about to read 5, iclass 22, count 0 2006.285.23:43:13.11#ibcon#read 5, iclass 22, count 0 2006.285.23:43:13.11#ibcon#about to read 6, iclass 22, count 0 2006.285.23:43:13.11#ibcon#read 6, iclass 22, count 0 2006.285.23:43:13.11#ibcon#end of sib2, iclass 22, count 0 2006.285.23:43:13.11#ibcon#*after write, iclass 22, count 0 2006.285.23:43:13.11#ibcon#*before return 0, iclass 22, count 0 2006.285.23:43:13.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:43:13.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.285.23:43:13.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.23:43:13.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.23:43:13.11$vck44/vb=4,5 2006.285.23:43:13.11#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.285.23:43:13.11#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.285.23:43:13.11#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:13.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:43:13.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:43:13.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:43:13.17#ibcon#enter wrdev, iclass 24, count 2 2006.285.23:43:13.17#ibcon#first serial, iclass 24, count 2 2006.285.23:43:13.17#ibcon#enter sib2, iclass 24, count 2 2006.285.23:43:13.17#ibcon#flushed, iclass 24, count 2 2006.285.23:43:13.17#ibcon#about to write, iclass 24, count 2 2006.285.23:43:13.17#ibcon#wrote, iclass 24, count 2 2006.285.23:43:13.17#ibcon#about to read 3, iclass 24, count 2 2006.285.23:43:13.19#ibcon#read 3, iclass 24, count 2 2006.285.23:43:13.19#ibcon#about to read 4, iclass 24, count 2 2006.285.23:43:13.19#ibcon#read 4, iclass 24, count 2 2006.285.23:43:13.19#ibcon#about to read 5, iclass 24, count 2 2006.285.23:43:13.19#ibcon#read 5, iclass 24, count 2 2006.285.23:43:13.19#ibcon#about to read 6, iclass 24, count 2 2006.285.23:43:13.19#ibcon#read 6, iclass 24, count 2 2006.285.23:43:13.19#ibcon#end of sib2, iclass 24, count 2 2006.285.23:43:13.19#ibcon#*mode == 0, iclass 24, count 2 2006.285.23:43:13.19#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.285.23:43:13.19#ibcon#[27=AT04-05\r\n] 2006.285.23:43:13.19#ibcon#*before write, iclass 24, count 2 2006.285.23:43:13.19#ibcon#enter sib2, iclass 24, count 2 2006.285.23:43:13.19#ibcon#flushed, iclass 24, count 2 2006.285.23:43:13.19#ibcon#about to write, iclass 24, count 2 2006.285.23:43:13.19#ibcon#wrote, iclass 24, count 2 2006.285.23:43:13.19#ibcon#about to read 3, iclass 24, count 2 2006.285.23:43:13.22#ibcon#read 3, iclass 24, count 2 2006.285.23:43:13.22#ibcon#about to read 4, iclass 24, count 2 2006.285.23:43:13.22#ibcon#read 4, iclass 24, count 2 2006.285.23:43:13.22#ibcon#about to read 5, iclass 24, count 2 2006.285.23:43:13.22#ibcon#read 5, iclass 24, count 2 2006.285.23:43:13.22#ibcon#about to read 6, iclass 24, count 2 2006.285.23:43:13.22#ibcon#read 6, iclass 24, count 2 2006.285.23:43:13.22#ibcon#end of sib2, iclass 24, count 2 2006.285.23:43:13.22#ibcon#*after write, iclass 24, count 2 2006.285.23:43:13.22#ibcon#*before return 0, iclass 24, count 2 2006.285.23:43:13.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:43:13.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.285.23:43:13.22#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.285.23:43:13.22#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:13.22#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:43:13.34#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:43:13.34#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:43:13.34#ibcon#enter wrdev, iclass 24, count 0 2006.285.23:43:13.34#ibcon#first serial, iclass 24, count 0 2006.285.23:43:13.34#ibcon#enter sib2, iclass 24, count 0 2006.285.23:43:13.34#ibcon#flushed, iclass 24, count 0 2006.285.23:43:13.34#ibcon#about to write, iclass 24, count 0 2006.285.23:43:13.34#ibcon#wrote, iclass 24, count 0 2006.285.23:43:13.34#ibcon#about to read 3, iclass 24, count 0 2006.285.23:43:13.36#ibcon#read 3, iclass 24, count 0 2006.285.23:43:13.36#ibcon#about to read 4, iclass 24, count 0 2006.285.23:43:13.36#ibcon#read 4, iclass 24, count 0 2006.285.23:43:13.36#ibcon#about to read 5, iclass 24, count 0 2006.285.23:43:13.36#ibcon#read 5, iclass 24, count 0 2006.285.23:43:13.36#ibcon#about to read 6, iclass 24, count 0 2006.285.23:43:13.36#ibcon#read 6, iclass 24, count 0 2006.285.23:43:13.36#ibcon#end of sib2, iclass 24, count 0 2006.285.23:43:13.36#ibcon#*mode == 0, iclass 24, count 0 2006.285.23:43:13.36#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.23:43:13.36#ibcon#[27=USB\r\n] 2006.285.23:43:13.36#ibcon#*before write, iclass 24, count 0 2006.285.23:43:13.36#ibcon#enter sib2, iclass 24, count 0 2006.285.23:43:13.36#ibcon#flushed, iclass 24, count 0 2006.285.23:43:13.36#ibcon#about to write, iclass 24, count 0 2006.285.23:43:13.36#ibcon#wrote, iclass 24, count 0 2006.285.23:43:13.36#ibcon#about to read 3, iclass 24, count 0 2006.285.23:43:13.39#ibcon#read 3, iclass 24, count 0 2006.285.23:43:13.39#ibcon#about to read 4, iclass 24, count 0 2006.285.23:43:13.39#ibcon#read 4, iclass 24, count 0 2006.285.23:43:13.39#ibcon#about to read 5, iclass 24, count 0 2006.285.23:43:13.39#ibcon#read 5, iclass 24, count 0 2006.285.23:43:13.39#ibcon#about to read 6, iclass 24, count 0 2006.285.23:43:13.39#ibcon#read 6, iclass 24, count 0 2006.285.23:43:13.39#ibcon#end of sib2, iclass 24, count 0 2006.285.23:43:13.39#ibcon#*after write, iclass 24, count 0 2006.285.23:43:13.39#ibcon#*before return 0, iclass 24, count 0 2006.285.23:43:13.39#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:43:13.39#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.285.23:43:13.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.23:43:13.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.23:43:13.39$vck44/vblo=5,709.99 2006.285.23:43:13.39#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.23:43:13.39#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.23:43:13.39#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:13.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:43:13.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:43:13.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:43:13.39#ibcon#enter wrdev, iclass 26, count 0 2006.285.23:43:13.39#ibcon#first serial, iclass 26, count 0 2006.285.23:43:13.39#ibcon#enter sib2, iclass 26, count 0 2006.285.23:43:13.39#ibcon#flushed, iclass 26, count 0 2006.285.23:43:13.39#ibcon#about to write, iclass 26, count 0 2006.285.23:43:13.39#ibcon#wrote, iclass 26, count 0 2006.285.23:43:13.39#ibcon#about to read 3, iclass 26, count 0 2006.285.23:43:13.41#ibcon#read 3, iclass 26, count 0 2006.285.23:43:13.41#ibcon#about to read 4, iclass 26, count 0 2006.285.23:43:13.41#ibcon#read 4, iclass 26, count 0 2006.285.23:43:13.41#ibcon#about to read 5, iclass 26, count 0 2006.285.23:43:13.41#ibcon#read 5, iclass 26, count 0 2006.285.23:43:13.41#ibcon#about to read 6, iclass 26, count 0 2006.285.23:43:13.41#ibcon#read 6, iclass 26, count 0 2006.285.23:43:13.41#ibcon#end of sib2, iclass 26, count 0 2006.285.23:43:13.41#ibcon#*mode == 0, iclass 26, count 0 2006.285.23:43:13.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.23:43:13.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:43:13.41#ibcon#*before write, iclass 26, count 0 2006.285.23:43:13.41#ibcon#enter sib2, iclass 26, count 0 2006.285.23:43:13.41#ibcon#flushed, iclass 26, count 0 2006.285.23:43:13.41#ibcon#about to write, iclass 26, count 0 2006.285.23:43:13.41#ibcon#wrote, iclass 26, count 0 2006.285.23:43:13.41#ibcon#about to read 3, iclass 26, count 0 2006.285.23:43:13.45#ibcon#read 3, iclass 26, count 0 2006.285.23:43:13.45#ibcon#about to read 4, iclass 26, count 0 2006.285.23:43:13.45#ibcon#read 4, iclass 26, count 0 2006.285.23:43:13.45#ibcon#about to read 5, iclass 26, count 0 2006.285.23:43:13.45#ibcon#read 5, iclass 26, count 0 2006.285.23:43:13.45#ibcon#about to read 6, iclass 26, count 0 2006.285.23:43:13.45#ibcon#read 6, iclass 26, count 0 2006.285.23:43:13.45#ibcon#end of sib2, iclass 26, count 0 2006.285.23:43:13.45#ibcon#*after write, iclass 26, count 0 2006.285.23:43:13.45#ibcon#*before return 0, iclass 26, count 0 2006.285.23:43:13.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:43:13.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:43:13.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.23:43:13.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.23:43:13.45$vck44/vb=5,4 2006.285.23:43:13.45#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.285.23:43:13.45#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.285.23:43:13.45#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:13.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:43:13.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:43:13.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:43:13.51#ibcon#enter wrdev, iclass 28, count 2 2006.285.23:43:13.51#ibcon#first serial, iclass 28, count 2 2006.285.23:43:13.51#ibcon#enter sib2, iclass 28, count 2 2006.285.23:43:13.51#ibcon#flushed, iclass 28, count 2 2006.285.23:43:13.51#ibcon#about to write, iclass 28, count 2 2006.285.23:43:13.51#ibcon#wrote, iclass 28, count 2 2006.285.23:43:13.51#ibcon#about to read 3, iclass 28, count 2 2006.285.23:43:13.53#ibcon#read 3, iclass 28, count 2 2006.285.23:43:13.53#ibcon#about to read 4, iclass 28, count 2 2006.285.23:43:13.53#ibcon#read 4, iclass 28, count 2 2006.285.23:43:13.53#ibcon#about to read 5, iclass 28, count 2 2006.285.23:43:13.53#ibcon#read 5, iclass 28, count 2 2006.285.23:43:13.53#ibcon#about to read 6, iclass 28, count 2 2006.285.23:43:13.53#ibcon#read 6, iclass 28, count 2 2006.285.23:43:13.53#ibcon#end of sib2, iclass 28, count 2 2006.285.23:43:13.53#ibcon#*mode == 0, iclass 28, count 2 2006.285.23:43:13.53#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.285.23:43:13.53#ibcon#[27=AT05-04\r\n] 2006.285.23:43:13.53#ibcon#*before write, iclass 28, count 2 2006.285.23:43:13.53#ibcon#enter sib2, iclass 28, count 2 2006.285.23:43:13.53#ibcon#flushed, iclass 28, count 2 2006.285.23:43:13.53#ibcon#about to write, iclass 28, count 2 2006.285.23:43:13.53#ibcon#wrote, iclass 28, count 2 2006.285.23:43:13.53#ibcon#about to read 3, iclass 28, count 2 2006.285.23:43:13.56#ibcon#read 3, iclass 28, count 2 2006.285.23:43:13.56#ibcon#about to read 4, iclass 28, count 2 2006.285.23:43:13.56#ibcon#read 4, iclass 28, count 2 2006.285.23:43:13.56#ibcon#about to read 5, iclass 28, count 2 2006.285.23:43:13.56#ibcon#read 5, iclass 28, count 2 2006.285.23:43:13.56#ibcon#about to read 6, iclass 28, count 2 2006.285.23:43:13.56#ibcon#read 6, iclass 28, count 2 2006.285.23:43:13.56#ibcon#end of sib2, iclass 28, count 2 2006.285.23:43:13.56#ibcon#*after write, iclass 28, count 2 2006.285.23:43:13.56#ibcon#*before return 0, iclass 28, count 2 2006.285.23:43:13.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:43:13.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.285.23:43:13.56#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.285.23:43:13.56#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:13.56#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:43:13.68#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:43:13.68#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:43:13.68#ibcon#enter wrdev, iclass 28, count 0 2006.285.23:43:13.68#ibcon#first serial, iclass 28, count 0 2006.285.23:43:13.68#ibcon#enter sib2, iclass 28, count 0 2006.285.23:43:13.68#ibcon#flushed, iclass 28, count 0 2006.285.23:43:13.68#ibcon#about to write, iclass 28, count 0 2006.285.23:43:13.68#ibcon#wrote, iclass 28, count 0 2006.285.23:43:13.68#ibcon#about to read 3, iclass 28, count 0 2006.285.23:43:13.70#ibcon#read 3, iclass 28, count 0 2006.285.23:43:13.70#ibcon#about to read 4, iclass 28, count 0 2006.285.23:43:13.70#ibcon#read 4, iclass 28, count 0 2006.285.23:43:13.70#ibcon#about to read 5, iclass 28, count 0 2006.285.23:43:13.70#ibcon#read 5, iclass 28, count 0 2006.285.23:43:13.70#ibcon#about to read 6, iclass 28, count 0 2006.285.23:43:13.70#ibcon#read 6, iclass 28, count 0 2006.285.23:43:13.70#ibcon#end of sib2, iclass 28, count 0 2006.285.23:43:13.70#ibcon#*mode == 0, iclass 28, count 0 2006.285.23:43:13.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.23:43:13.70#ibcon#[27=USB\r\n] 2006.285.23:43:13.70#ibcon#*before write, iclass 28, count 0 2006.285.23:43:13.70#ibcon#enter sib2, iclass 28, count 0 2006.285.23:43:13.70#ibcon#flushed, iclass 28, count 0 2006.285.23:43:13.70#ibcon#about to write, iclass 28, count 0 2006.285.23:43:13.70#ibcon#wrote, iclass 28, count 0 2006.285.23:43:13.70#ibcon#about to read 3, iclass 28, count 0 2006.285.23:43:13.73#ibcon#read 3, iclass 28, count 0 2006.285.23:43:13.73#ibcon#about to read 4, iclass 28, count 0 2006.285.23:43:13.73#ibcon#read 4, iclass 28, count 0 2006.285.23:43:13.73#ibcon#about to read 5, iclass 28, count 0 2006.285.23:43:13.73#ibcon#read 5, iclass 28, count 0 2006.285.23:43:13.73#ibcon#about to read 6, iclass 28, count 0 2006.285.23:43:13.73#ibcon#read 6, iclass 28, count 0 2006.285.23:43:13.73#ibcon#end of sib2, iclass 28, count 0 2006.285.23:43:13.73#ibcon#*after write, iclass 28, count 0 2006.285.23:43:13.73#ibcon#*before return 0, iclass 28, count 0 2006.285.23:43:13.73#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:43:13.73#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.285.23:43:13.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.23:43:13.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.23:43:13.73$vck44/vblo=6,719.99 2006.285.23:43:13.73#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.285.23:43:13.73#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.285.23:43:13.73#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:13.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:43:13.73#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:43:13.73#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:43:13.73#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:43:13.73#ibcon#first serial, iclass 30, count 0 2006.285.23:43:13.73#ibcon#enter sib2, iclass 30, count 0 2006.285.23:43:13.73#ibcon#flushed, iclass 30, count 0 2006.285.23:43:13.73#ibcon#about to write, iclass 30, count 0 2006.285.23:43:13.73#ibcon#wrote, iclass 30, count 0 2006.285.23:43:13.73#ibcon#about to read 3, iclass 30, count 0 2006.285.23:43:13.75#ibcon#read 3, iclass 30, count 0 2006.285.23:43:13.75#ibcon#about to read 4, iclass 30, count 0 2006.285.23:43:13.75#ibcon#read 4, iclass 30, count 0 2006.285.23:43:13.75#ibcon#about to read 5, iclass 30, count 0 2006.285.23:43:13.75#ibcon#read 5, iclass 30, count 0 2006.285.23:43:13.75#ibcon#about to read 6, iclass 30, count 0 2006.285.23:43:13.75#ibcon#read 6, iclass 30, count 0 2006.285.23:43:13.75#ibcon#end of sib2, iclass 30, count 0 2006.285.23:43:13.75#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:43:13.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:43:13.75#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:43:13.75#ibcon#*before write, iclass 30, count 0 2006.285.23:43:13.75#ibcon#enter sib2, iclass 30, count 0 2006.285.23:43:13.75#ibcon#flushed, iclass 30, count 0 2006.285.23:43:13.75#ibcon#about to write, iclass 30, count 0 2006.285.23:43:13.75#ibcon#wrote, iclass 30, count 0 2006.285.23:43:13.75#ibcon#about to read 3, iclass 30, count 0 2006.285.23:43:13.79#ibcon#read 3, iclass 30, count 0 2006.285.23:43:13.79#ibcon#about to read 4, iclass 30, count 0 2006.285.23:43:13.79#ibcon#read 4, iclass 30, count 0 2006.285.23:43:13.79#ibcon#about to read 5, iclass 30, count 0 2006.285.23:43:13.79#ibcon#read 5, iclass 30, count 0 2006.285.23:43:13.79#ibcon#about to read 6, iclass 30, count 0 2006.285.23:43:13.79#ibcon#read 6, iclass 30, count 0 2006.285.23:43:13.79#ibcon#end of sib2, iclass 30, count 0 2006.285.23:43:13.79#ibcon#*after write, iclass 30, count 0 2006.285.23:43:13.79#ibcon#*before return 0, iclass 30, count 0 2006.285.23:43:13.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:43:13.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.285.23:43:13.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:43:13.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:43:13.79$vck44/vb=6,3 2006.285.23:43:13.79#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.285.23:43:13.79#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.285.23:43:13.79#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:13.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:43:13.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:43:13.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:43:13.85#ibcon#enter wrdev, iclass 32, count 2 2006.285.23:43:13.85#ibcon#first serial, iclass 32, count 2 2006.285.23:43:13.85#ibcon#enter sib2, iclass 32, count 2 2006.285.23:43:13.85#ibcon#flushed, iclass 32, count 2 2006.285.23:43:13.85#ibcon#about to write, iclass 32, count 2 2006.285.23:43:13.85#ibcon#wrote, iclass 32, count 2 2006.285.23:43:13.85#ibcon#about to read 3, iclass 32, count 2 2006.285.23:43:13.87#ibcon#read 3, iclass 32, count 2 2006.285.23:43:13.87#ibcon#about to read 4, iclass 32, count 2 2006.285.23:43:13.87#ibcon#read 4, iclass 32, count 2 2006.285.23:43:13.87#ibcon#about to read 5, iclass 32, count 2 2006.285.23:43:13.87#ibcon#read 5, iclass 32, count 2 2006.285.23:43:13.87#ibcon#about to read 6, iclass 32, count 2 2006.285.23:43:13.87#ibcon#read 6, iclass 32, count 2 2006.285.23:43:13.87#ibcon#end of sib2, iclass 32, count 2 2006.285.23:43:13.87#ibcon#*mode == 0, iclass 32, count 2 2006.285.23:43:13.87#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.285.23:43:13.87#ibcon#[27=AT06-03\r\n] 2006.285.23:43:13.87#ibcon#*before write, iclass 32, count 2 2006.285.23:43:13.87#ibcon#enter sib2, iclass 32, count 2 2006.285.23:43:13.87#ibcon#flushed, iclass 32, count 2 2006.285.23:43:13.87#ibcon#about to write, iclass 32, count 2 2006.285.23:43:13.87#ibcon#wrote, iclass 32, count 2 2006.285.23:43:13.87#ibcon#about to read 3, iclass 32, count 2 2006.285.23:43:13.90#ibcon#read 3, iclass 32, count 2 2006.285.23:43:13.90#ibcon#about to read 4, iclass 32, count 2 2006.285.23:43:13.90#ibcon#read 4, iclass 32, count 2 2006.285.23:43:13.90#ibcon#about to read 5, iclass 32, count 2 2006.285.23:43:13.90#ibcon#read 5, iclass 32, count 2 2006.285.23:43:13.90#ibcon#about to read 6, iclass 32, count 2 2006.285.23:43:13.90#ibcon#read 6, iclass 32, count 2 2006.285.23:43:13.90#ibcon#end of sib2, iclass 32, count 2 2006.285.23:43:13.90#ibcon#*after write, iclass 32, count 2 2006.285.23:43:13.90#ibcon#*before return 0, iclass 32, count 2 2006.285.23:43:13.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:43:13.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.285.23:43:13.90#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.285.23:43:13.90#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:13.90#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:43:14.02#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:43:14.02#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:43:14.02#ibcon#enter wrdev, iclass 32, count 0 2006.285.23:43:14.02#ibcon#first serial, iclass 32, count 0 2006.285.23:43:14.02#ibcon#enter sib2, iclass 32, count 0 2006.285.23:43:14.02#ibcon#flushed, iclass 32, count 0 2006.285.23:43:14.02#ibcon#about to write, iclass 32, count 0 2006.285.23:43:14.02#ibcon#wrote, iclass 32, count 0 2006.285.23:43:14.02#ibcon#about to read 3, iclass 32, count 0 2006.285.23:43:14.04#ibcon#read 3, iclass 32, count 0 2006.285.23:43:14.04#ibcon#about to read 4, iclass 32, count 0 2006.285.23:43:14.04#ibcon#read 4, iclass 32, count 0 2006.285.23:43:14.04#ibcon#about to read 5, iclass 32, count 0 2006.285.23:43:14.04#ibcon#read 5, iclass 32, count 0 2006.285.23:43:14.04#ibcon#about to read 6, iclass 32, count 0 2006.285.23:43:14.04#ibcon#read 6, iclass 32, count 0 2006.285.23:43:14.04#ibcon#end of sib2, iclass 32, count 0 2006.285.23:43:14.04#ibcon#*mode == 0, iclass 32, count 0 2006.285.23:43:14.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.23:43:14.04#ibcon#[27=USB\r\n] 2006.285.23:43:14.04#ibcon#*before write, iclass 32, count 0 2006.285.23:43:14.04#ibcon#enter sib2, iclass 32, count 0 2006.285.23:43:14.04#ibcon#flushed, iclass 32, count 0 2006.285.23:43:14.04#ibcon#about to write, iclass 32, count 0 2006.285.23:43:14.04#ibcon#wrote, iclass 32, count 0 2006.285.23:43:14.04#ibcon#about to read 3, iclass 32, count 0 2006.285.23:43:14.07#ibcon#read 3, iclass 32, count 0 2006.285.23:43:14.07#ibcon#about to read 4, iclass 32, count 0 2006.285.23:43:14.07#ibcon#read 4, iclass 32, count 0 2006.285.23:43:14.07#ibcon#about to read 5, iclass 32, count 0 2006.285.23:43:14.07#ibcon#read 5, iclass 32, count 0 2006.285.23:43:14.07#ibcon#about to read 6, iclass 32, count 0 2006.285.23:43:14.07#ibcon#read 6, iclass 32, count 0 2006.285.23:43:14.07#ibcon#end of sib2, iclass 32, count 0 2006.285.23:43:14.07#ibcon#*after write, iclass 32, count 0 2006.285.23:43:14.07#ibcon#*before return 0, iclass 32, count 0 2006.285.23:43:14.07#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:43:14.07#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.285.23:43:14.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.23:43:14.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.23:43:14.07$vck44/vblo=7,734.99 2006.285.23:43:14.07#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.23:43:14.07#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.23:43:14.07#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:14.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:43:14.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:43:14.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:43:14.07#ibcon#enter wrdev, iclass 34, count 0 2006.285.23:43:14.07#ibcon#first serial, iclass 34, count 0 2006.285.23:43:14.07#ibcon#enter sib2, iclass 34, count 0 2006.285.23:43:14.07#ibcon#flushed, iclass 34, count 0 2006.285.23:43:14.07#ibcon#about to write, iclass 34, count 0 2006.285.23:43:14.07#ibcon#wrote, iclass 34, count 0 2006.285.23:43:14.07#ibcon#about to read 3, iclass 34, count 0 2006.285.23:43:14.09#ibcon#read 3, iclass 34, count 0 2006.285.23:43:14.09#ibcon#about to read 4, iclass 34, count 0 2006.285.23:43:14.09#ibcon#read 4, iclass 34, count 0 2006.285.23:43:14.09#ibcon#about to read 5, iclass 34, count 0 2006.285.23:43:14.09#ibcon#read 5, iclass 34, count 0 2006.285.23:43:14.09#ibcon#about to read 6, iclass 34, count 0 2006.285.23:43:14.09#ibcon#read 6, iclass 34, count 0 2006.285.23:43:14.09#ibcon#end of sib2, iclass 34, count 0 2006.285.23:43:14.09#ibcon#*mode == 0, iclass 34, count 0 2006.285.23:43:14.09#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.23:43:14.09#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:43:14.09#ibcon#*before write, iclass 34, count 0 2006.285.23:43:14.09#ibcon#enter sib2, iclass 34, count 0 2006.285.23:43:14.09#ibcon#flushed, iclass 34, count 0 2006.285.23:43:14.09#ibcon#about to write, iclass 34, count 0 2006.285.23:43:14.09#ibcon#wrote, iclass 34, count 0 2006.285.23:43:14.09#ibcon#about to read 3, iclass 34, count 0 2006.285.23:43:14.13#ibcon#read 3, iclass 34, count 0 2006.285.23:43:14.13#ibcon#about to read 4, iclass 34, count 0 2006.285.23:43:14.13#ibcon#read 4, iclass 34, count 0 2006.285.23:43:14.13#ibcon#about to read 5, iclass 34, count 0 2006.285.23:43:14.13#ibcon#read 5, iclass 34, count 0 2006.285.23:43:14.13#ibcon#about to read 6, iclass 34, count 0 2006.285.23:43:14.13#ibcon#read 6, iclass 34, count 0 2006.285.23:43:14.13#ibcon#end of sib2, iclass 34, count 0 2006.285.23:43:14.13#ibcon#*after write, iclass 34, count 0 2006.285.23:43:14.13#ibcon#*before return 0, iclass 34, count 0 2006.285.23:43:14.13#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:43:14.13#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:43:14.13#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.23:43:14.13#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.23:43:14.13$vck44/vb=7,4 2006.285.23:43:14.13#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.285.23:43:14.13#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.285.23:43:14.13#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:14.13#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:43:14.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:43:14.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:43:14.19#ibcon#enter wrdev, iclass 36, count 2 2006.285.23:43:14.19#ibcon#first serial, iclass 36, count 2 2006.285.23:43:14.19#ibcon#enter sib2, iclass 36, count 2 2006.285.23:43:14.19#ibcon#flushed, iclass 36, count 2 2006.285.23:43:14.19#ibcon#about to write, iclass 36, count 2 2006.285.23:43:14.19#ibcon#wrote, iclass 36, count 2 2006.285.23:43:14.19#ibcon#about to read 3, iclass 36, count 2 2006.285.23:43:14.21#ibcon#read 3, iclass 36, count 2 2006.285.23:43:14.21#ibcon#about to read 4, iclass 36, count 2 2006.285.23:43:14.21#ibcon#read 4, iclass 36, count 2 2006.285.23:43:14.21#ibcon#about to read 5, iclass 36, count 2 2006.285.23:43:14.21#ibcon#read 5, iclass 36, count 2 2006.285.23:43:14.21#ibcon#about to read 6, iclass 36, count 2 2006.285.23:43:14.21#ibcon#read 6, iclass 36, count 2 2006.285.23:43:14.21#ibcon#end of sib2, iclass 36, count 2 2006.285.23:43:14.21#ibcon#*mode == 0, iclass 36, count 2 2006.285.23:43:14.21#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.285.23:43:14.21#ibcon#[27=AT07-04\r\n] 2006.285.23:43:14.21#ibcon#*before write, iclass 36, count 2 2006.285.23:43:14.21#ibcon#enter sib2, iclass 36, count 2 2006.285.23:43:14.21#ibcon#flushed, iclass 36, count 2 2006.285.23:43:14.21#ibcon#about to write, iclass 36, count 2 2006.285.23:43:14.21#ibcon#wrote, iclass 36, count 2 2006.285.23:43:14.21#ibcon#about to read 3, iclass 36, count 2 2006.285.23:43:14.24#ibcon#read 3, iclass 36, count 2 2006.285.23:43:14.24#ibcon#about to read 4, iclass 36, count 2 2006.285.23:43:14.24#ibcon#read 4, iclass 36, count 2 2006.285.23:43:14.24#ibcon#about to read 5, iclass 36, count 2 2006.285.23:43:14.24#ibcon#read 5, iclass 36, count 2 2006.285.23:43:14.24#ibcon#about to read 6, iclass 36, count 2 2006.285.23:43:14.24#ibcon#read 6, iclass 36, count 2 2006.285.23:43:14.24#ibcon#end of sib2, iclass 36, count 2 2006.285.23:43:14.24#ibcon#*after write, iclass 36, count 2 2006.285.23:43:14.24#ibcon#*before return 0, iclass 36, count 2 2006.285.23:43:14.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:43:14.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.285.23:43:14.24#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.285.23:43:14.24#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:14.24#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:43:14.36#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:43:14.36#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:43:14.36#ibcon#enter wrdev, iclass 36, count 0 2006.285.23:43:14.36#ibcon#first serial, iclass 36, count 0 2006.285.23:43:14.36#ibcon#enter sib2, iclass 36, count 0 2006.285.23:43:14.36#ibcon#flushed, iclass 36, count 0 2006.285.23:43:14.36#ibcon#about to write, iclass 36, count 0 2006.285.23:43:14.36#ibcon#wrote, iclass 36, count 0 2006.285.23:43:14.36#ibcon#about to read 3, iclass 36, count 0 2006.285.23:43:14.38#ibcon#read 3, iclass 36, count 0 2006.285.23:43:14.38#ibcon#about to read 4, iclass 36, count 0 2006.285.23:43:14.38#ibcon#read 4, iclass 36, count 0 2006.285.23:43:14.38#ibcon#about to read 5, iclass 36, count 0 2006.285.23:43:14.38#ibcon#read 5, iclass 36, count 0 2006.285.23:43:14.38#ibcon#about to read 6, iclass 36, count 0 2006.285.23:43:14.38#ibcon#read 6, iclass 36, count 0 2006.285.23:43:14.38#ibcon#end of sib2, iclass 36, count 0 2006.285.23:43:14.38#ibcon#*mode == 0, iclass 36, count 0 2006.285.23:43:14.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.23:43:14.38#ibcon#[27=USB\r\n] 2006.285.23:43:14.38#ibcon#*before write, iclass 36, count 0 2006.285.23:43:14.38#ibcon#enter sib2, iclass 36, count 0 2006.285.23:43:14.38#ibcon#flushed, iclass 36, count 0 2006.285.23:43:14.38#ibcon#about to write, iclass 36, count 0 2006.285.23:43:14.38#ibcon#wrote, iclass 36, count 0 2006.285.23:43:14.38#ibcon#about to read 3, iclass 36, count 0 2006.285.23:43:14.41#ibcon#read 3, iclass 36, count 0 2006.285.23:43:14.41#ibcon#about to read 4, iclass 36, count 0 2006.285.23:43:14.41#ibcon#read 4, iclass 36, count 0 2006.285.23:43:14.41#ibcon#about to read 5, iclass 36, count 0 2006.285.23:43:14.41#ibcon#read 5, iclass 36, count 0 2006.285.23:43:14.41#ibcon#about to read 6, iclass 36, count 0 2006.285.23:43:14.41#ibcon#read 6, iclass 36, count 0 2006.285.23:43:14.41#ibcon#end of sib2, iclass 36, count 0 2006.285.23:43:14.41#ibcon#*after write, iclass 36, count 0 2006.285.23:43:14.41#ibcon#*before return 0, iclass 36, count 0 2006.285.23:43:14.41#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:43:14.41#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.285.23:43:14.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.23:43:14.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.23:43:14.41$vck44/vblo=8,744.99 2006.285.23:43:14.41#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.285.23:43:14.41#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.285.23:43:14.41#ibcon#ireg 17 cls_cnt 0 2006.285.23:43:14.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:43:14.41#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:43:14.41#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:43:14.41#ibcon#enter wrdev, iclass 38, count 0 2006.285.23:43:14.41#ibcon#first serial, iclass 38, count 0 2006.285.23:43:14.41#ibcon#enter sib2, iclass 38, count 0 2006.285.23:43:14.41#ibcon#flushed, iclass 38, count 0 2006.285.23:43:14.41#ibcon#about to write, iclass 38, count 0 2006.285.23:43:14.41#ibcon#wrote, iclass 38, count 0 2006.285.23:43:14.41#ibcon#about to read 3, iclass 38, count 0 2006.285.23:43:14.43#ibcon#read 3, iclass 38, count 0 2006.285.23:43:14.43#ibcon#about to read 4, iclass 38, count 0 2006.285.23:43:14.43#ibcon#read 4, iclass 38, count 0 2006.285.23:43:14.43#ibcon#about to read 5, iclass 38, count 0 2006.285.23:43:14.43#ibcon#read 5, iclass 38, count 0 2006.285.23:43:14.43#ibcon#about to read 6, iclass 38, count 0 2006.285.23:43:14.43#ibcon#read 6, iclass 38, count 0 2006.285.23:43:14.43#ibcon#end of sib2, iclass 38, count 0 2006.285.23:43:14.43#ibcon#*mode == 0, iclass 38, count 0 2006.285.23:43:14.43#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.23:43:14.43#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:43:14.43#ibcon#*before write, iclass 38, count 0 2006.285.23:43:14.43#ibcon#enter sib2, iclass 38, count 0 2006.285.23:43:14.43#ibcon#flushed, iclass 38, count 0 2006.285.23:43:14.43#ibcon#about to write, iclass 38, count 0 2006.285.23:43:14.43#ibcon#wrote, iclass 38, count 0 2006.285.23:43:14.43#ibcon#about to read 3, iclass 38, count 0 2006.285.23:43:14.47#ibcon#read 3, iclass 38, count 0 2006.285.23:43:14.47#ibcon#about to read 4, iclass 38, count 0 2006.285.23:43:14.47#ibcon#read 4, iclass 38, count 0 2006.285.23:43:14.47#ibcon#about to read 5, iclass 38, count 0 2006.285.23:43:14.47#ibcon#read 5, iclass 38, count 0 2006.285.23:43:14.47#ibcon#about to read 6, iclass 38, count 0 2006.285.23:43:14.47#ibcon#read 6, iclass 38, count 0 2006.285.23:43:14.47#ibcon#end of sib2, iclass 38, count 0 2006.285.23:43:14.47#ibcon#*after write, iclass 38, count 0 2006.285.23:43:14.47#ibcon#*before return 0, iclass 38, count 0 2006.285.23:43:14.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:43:14.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.285.23:43:14.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.23:43:14.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.23:43:14.47$vck44/vb=8,4 2006.285.23:43:14.47#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.285.23:43:14.47#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.285.23:43:14.47#ibcon#ireg 11 cls_cnt 2 2006.285.23:43:14.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:43:14.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:43:14.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:43:14.53#ibcon#enter wrdev, iclass 40, count 2 2006.285.23:43:14.53#ibcon#first serial, iclass 40, count 2 2006.285.23:43:14.53#ibcon#enter sib2, iclass 40, count 2 2006.285.23:43:14.53#ibcon#flushed, iclass 40, count 2 2006.285.23:43:14.53#ibcon#about to write, iclass 40, count 2 2006.285.23:43:14.53#ibcon#wrote, iclass 40, count 2 2006.285.23:43:14.53#ibcon#about to read 3, iclass 40, count 2 2006.285.23:43:14.55#ibcon#read 3, iclass 40, count 2 2006.285.23:43:14.55#ibcon#about to read 4, iclass 40, count 2 2006.285.23:43:14.55#ibcon#read 4, iclass 40, count 2 2006.285.23:43:14.55#ibcon#about to read 5, iclass 40, count 2 2006.285.23:43:14.55#ibcon#read 5, iclass 40, count 2 2006.285.23:43:14.55#ibcon#about to read 6, iclass 40, count 2 2006.285.23:43:14.55#ibcon#read 6, iclass 40, count 2 2006.285.23:43:14.55#ibcon#end of sib2, iclass 40, count 2 2006.285.23:43:14.55#ibcon#*mode == 0, iclass 40, count 2 2006.285.23:43:14.55#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.285.23:43:14.55#ibcon#[27=AT08-04\r\n] 2006.285.23:43:14.55#ibcon#*before write, iclass 40, count 2 2006.285.23:43:14.55#ibcon#enter sib2, iclass 40, count 2 2006.285.23:43:14.55#ibcon#flushed, iclass 40, count 2 2006.285.23:43:14.55#ibcon#about to write, iclass 40, count 2 2006.285.23:43:14.55#ibcon#wrote, iclass 40, count 2 2006.285.23:43:14.55#ibcon#about to read 3, iclass 40, count 2 2006.285.23:43:14.58#ibcon#read 3, iclass 40, count 2 2006.285.23:43:14.58#ibcon#about to read 4, iclass 40, count 2 2006.285.23:43:14.58#ibcon#read 4, iclass 40, count 2 2006.285.23:43:14.58#ibcon#about to read 5, iclass 40, count 2 2006.285.23:43:14.58#ibcon#read 5, iclass 40, count 2 2006.285.23:43:14.58#ibcon#about to read 6, iclass 40, count 2 2006.285.23:43:14.58#ibcon#read 6, iclass 40, count 2 2006.285.23:43:14.58#ibcon#end of sib2, iclass 40, count 2 2006.285.23:43:14.58#ibcon#*after write, iclass 40, count 2 2006.285.23:43:14.58#ibcon#*before return 0, iclass 40, count 2 2006.285.23:43:14.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:43:14.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.285.23:43:14.58#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.285.23:43:14.58#ibcon#ireg 7 cls_cnt 0 2006.285.23:43:14.58#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:43:14.70#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:43:14.70#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:43:14.70#ibcon#enter wrdev, iclass 40, count 0 2006.285.23:43:14.70#ibcon#first serial, iclass 40, count 0 2006.285.23:43:14.70#ibcon#enter sib2, iclass 40, count 0 2006.285.23:43:14.70#ibcon#flushed, iclass 40, count 0 2006.285.23:43:14.70#ibcon#about to write, iclass 40, count 0 2006.285.23:43:14.70#ibcon#wrote, iclass 40, count 0 2006.285.23:43:14.70#ibcon#about to read 3, iclass 40, count 0 2006.285.23:43:14.72#ibcon#read 3, iclass 40, count 0 2006.285.23:43:14.72#ibcon#about to read 4, iclass 40, count 0 2006.285.23:43:14.72#ibcon#read 4, iclass 40, count 0 2006.285.23:43:14.72#ibcon#about to read 5, iclass 40, count 0 2006.285.23:43:14.72#ibcon#read 5, iclass 40, count 0 2006.285.23:43:14.72#ibcon#about to read 6, iclass 40, count 0 2006.285.23:43:14.72#ibcon#read 6, iclass 40, count 0 2006.285.23:43:14.72#ibcon#end of sib2, iclass 40, count 0 2006.285.23:43:14.72#ibcon#*mode == 0, iclass 40, count 0 2006.285.23:43:14.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.23:43:14.72#ibcon#[27=USB\r\n] 2006.285.23:43:14.72#ibcon#*before write, iclass 40, count 0 2006.285.23:43:14.72#ibcon#enter sib2, iclass 40, count 0 2006.285.23:43:14.72#ibcon#flushed, iclass 40, count 0 2006.285.23:43:14.72#ibcon#about to write, iclass 40, count 0 2006.285.23:43:14.72#ibcon#wrote, iclass 40, count 0 2006.285.23:43:14.72#ibcon#about to read 3, iclass 40, count 0 2006.285.23:43:14.75#ibcon#read 3, iclass 40, count 0 2006.285.23:43:14.75#ibcon#about to read 4, iclass 40, count 0 2006.285.23:43:14.75#ibcon#read 4, iclass 40, count 0 2006.285.23:43:14.75#ibcon#about to read 5, iclass 40, count 0 2006.285.23:43:14.75#ibcon#read 5, iclass 40, count 0 2006.285.23:43:14.75#ibcon#about to read 6, iclass 40, count 0 2006.285.23:43:14.75#ibcon#read 6, iclass 40, count 0 2006.285.23:43:14.75#ibcon#end of sib2, iclass 40, count 0 2006.285.23:43:14.75#ibcon#*after write, iclass 40, count 0 2006.285.23:43:14.75#ibcon#*before return 0, iclass 40, count 0 2006.285.23:43:14.75#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:43:14.75#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.285.23:43:14.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.23:43:14.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.23:43:14.75$vck44/vabw=wide 2006.285.23:43:14.75#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.285.23:43:14.75#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.285.23:43:14.75#ibcon#ireg 8 cls_cnt 0 2006.285.23:43:14.75#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:43:14.75#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:43:14.75#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:43:14.75#ibcon#enter wrdev, iclass 4, count 0 2006.285.23:43:14.75#ibcon#first serial, iclass 4, count 0 2006.285.23:43:14.75#ibcon#enter sib2, iclass 4, count 0 2006.285.23:43:14.75#ibcon#flushed, iclass 4, count 0 2006.285.23:43:14.75#ibcon#about to write, iclass 4, count 0 2006.285.23:43:14.75#ibcon#wrote, iclass 4, count 0 2006.285.23:43:14.75#ibcon#about to read 3, iclass 4, count 0 2006.285.23:43:14.77#ibcon#read 3, iclass 4, count 0 2006.285.23:43:14.77#ibcon#about to read 4, iclass 4, count 0 2006.285.23:43:14.77#ibcon#read 4, iclass 4, count 0 2006.285.23:43:14.77#ibcon#about to read 5, iclass 4, count 0 2006.285.23:43:14.77#ibcon#read 5, iclass 4, count 0 2006.285.23:43:14.77#ibcon#about to read 6, iclass 4, count 0 2006.285.23:43:14.77#ibcon#read 6, iclass 4, count 0 2006.285.23:43:14.77#ibcon#end of sib2, iclass 4, count 0 2006.285.23:43:14.77#ibcon#*mode == 0, iclass 4, count 0 2006.285.23:43:14.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.23:43:14.77#ibcon#[25=BW32\r\n] 2006.285.23:43:14.77#ibcon#*before write, iclass 4, count 0 2006.285.23:43:14.77#ibcon#enter sib2, iclass 4, count 0 2006.285.23:43:14.77#ibcon#flushed, iclass 4, count 0 2006.285.23:43:14.77#ibcon#about to write, iclass 4, count 0 2006.285.23:43:14.77#ibcon#wrote, iclass 4, count 0 2006.285.23:43:14.77#ibcon#about to read 3, iclass 4, count 0 2006.285.23:43:14.80#ibcon#read 3, iclass 4, count 0 2006.285.23:43:14.80#ibcon#about to read 4, iclass 4, count 0 2006.285.23:43:14.80#ibcon#read 4, iclass 4, count 0 2006.285.23:43:14.80#ibcon#about to read 5, iclass 4, count 0 2006.285.23:43:14.80#ibcon#read 5, iclass 4, count 0 2006.285.23:43:14.80#ibcon#about to read 6, iclass 4, count 0 2006.285.23:43:14.80#ibcon#read 6, iclass 4, count 0 2006.285.23:43:14.80#ibcon#end of sib2, iclass 4, count 0 2006.285.23:43:14.80#ibcon#*after write, iclass 4, count 0 2006.285.23:43:14.80#ibcon#*before return 0, iclass 4, count 0 2006.285.23:43:14.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:43:14.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.285.23:43:14.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.23:43:14.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.23:43:14.80$vck44/vbbw=wide 2006.285.23:43:14.80#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.23:43:14.80#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.23:43:14.80#ibcon#ireg 8 cls_cnt 0 2006.285.23:43:14.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:43:14.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:43:14.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:43:14.87#ibcon#enter wrdev, iclass 6, count 0 2006.285.23:43:14.87#ibcon#first serial, iclass 6, count 0 2006.285.23:43:14.87#ibcon#enter sib2, iclass 6, count 0 2006.285.23:43:14.87#ibcon#flushed, iclass 6, count 0 2006.285.23:43:14.87#ibcon#about to write, iclass 6, count 0 2006.285.23:43:14.87#ibcon#wrote, iclass 6, count 0 2006.285.23:43:14.87#ibcon#about to read 3, iclass 6, count 0 2006.285.23:43:14.89#ibcon#read 3, iclass 6, count 0 2006.285.23:43:14.89#ibcon#about to read 4, iclass 6, count 0 2006.285.23:43:14.89#ibcon#read 4, iclass 6, count 0 2006.285.23:43:14.89#ibcon#about to read 5, iclass 6, count 0 2006.285.23:43:14.89#ibcon#read 5, iclass 6, count 0 2006.285.23:43:14.89#ibcon#about to read 6, iclass 6, count 0 2006.285.23:43:14.89#ibcon#read 6, iclass 6, count 0 2006.285.23:43:14.89#ibcon#end of sib2, iclass 6, count 0 2006.285.23:43:14.89#ibcon#*mode == 0, iclass 6, count 0 2006.285.23:43:14.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.23:43:14.89#ibcon#[27=BW32\r\n] 2006.285.23:43:14.89#ibcon#*before write, iclass 6, count 0 2006.285.23:43:14.89#ibcon#enter sib2, iclass 6, count 0 2006.285.23:43:14.89#ibcon#flushed, iclass 6, count 0 2006.285.23:43:14.89#ibcon#about to write, iclass 6, count 0 2006.285.23:43:14.89#ibcon#wrote, iclass 6, count 0 2006.285.23:43:14.89#ibcon#about to read 3, iclass 6, count 0 2006.285.23:43:14.92#ibcon#read 3, iclass 6, count 0 2006.285.23:43:14.92#ibcon#about to read 4, iclass 6, count 0 2006.285.23:43:14.92#ibcon#read 4, iclass 6, count 0 2006.285.23:43:14.92#ibcon#about to read 5, iclass 6, count 0 2006.285.23:43:14.92#ibcon#read 5, iclass 6, count 0 2006.285.23:43:14.92#ibcon#about to read 6, iclass 6, count 0 2006.285.23:43:14.92#ibcon#read 6, iclass 6, count 0 2006.285.23:43:14.92#ibcon#end of sib2, iclass 6, count 0 2006.285.23:43:14.92#ibcon#*after write, iclass 6, count 0 2006.285.23:43:14.92#ibcon#*before return 0, iclass 6, count 0 2006.285.23:43:14.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:43:14.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:43:14.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.23:43:14.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.23:43:14.92$setupk4/ifdk4 2006.285.23:43:14.92$ifdk4/lo= 2006.285.23:43:14.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:43:14.93$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:43:14.93$ifdk4/patch= 2006.285.23:43:14.93$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:43:14.93$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:43:14.93$setupk4/!*+20s 2006.285.23:43:14.96#abcon#<5=/03 3.8 9.2 19.45 881016.6\r\n> 2006.285.23:43:14.98#abcon#{5=INTERFACE CLEAR} 2006.285.23:43:15.04#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:43:25.13#trakl#Source acquired 2006.285.23:43:25.13#flagr#flagr/antenna,acquired 2006.285.23:43:25.22#abcon#<5=/03 3.8 9.2 19.46 881016.5\r\n> 2006.285.23:43:25.24#abcon#{5=INTERFACE CLEAR} 2006.285.23:43:25.30#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:43:29.45$setupk4/"tpicd 2006.285.23:43:29.45$setupk4/echo=off 2006.285.23:43:29.45$setupk4/xlog=off 2006.285.23:43:29.45:!2006.285.23:44:55 2006.285.23:44:55.00:preob 2006.285.23:44:56.14/onsource/TRACKING 2006.285.23:44:56.14:!2006.285.23:45:05 2006.285.23:45:05.00:"tape 2006.285.23:45:05.00:"st=record 2006.285.23:45:05.00:data_valid=on 2006.285.23:45:05.00:midob 2006.285.23:45:05.14/onsource/TRACKING 2006.285.23:45:05.15/wx/19.49,1016.5,87 2006.285.23:45:05.22/cable/+6.5093E-03 2006.285.23:45:06.31/va/01,07,usb,yes,34,37 2006.285.23:45:06.31/va/02,06,usb,yes,34,34 2006.285.23:45:06.31/va/03,07,usb,yes,33,35 2006.285.23:45:06.31/va/04,06,usb,yes,35,36 2006.285.23:45:06.31/va/05,03,usb,yes,34,35 2006.285.23:45:06.31/va/06,04,usb,yes,31,30 2006.285.23:45:06.31/va/07,04,usb,yes,32,32 2006.285.23:45:06.31/va/08,03,usb,yes,32,39 2006.285.23:45:06.54/valo/01,524.99,yes,locked 2006.285.23:45:06.54/valo/02,534.99,yes,locked 2006.285.23:45:06.54/valo/03,564.99,yes,locked 2006.285.23:45:06.54/valo/04,624.99,yes,locked 2006.285.23:45:06.54/valo/05,734.99,yes,locked 2006.285.23:45:06.54/valo/06,814.99,yes,locked 2006.285.23:45:06.54/valo/07,864.99,yes,locked 2006.285.23:45:06.54/valo/08,884.99,yes,locked 2006.285.23:45:07.63/vb/01,04,usb,yes,31,29 2006.285.23:45:07.63/vb/02,05,usb,yes,30,30 2006.285.23:45:07.63/vb/03,04,usb,yes,31,34 2006.285.23:45:07.63/vb/04,05,usb,yes,31,30 2006.285.23:45:07.63/vb/05,04,usb,yes,27,30 2006.285.23:45:07.63/vb/06,03,usb,yes,39,35 2006.285.23:45:07.63/vb/07,04,usb,yes,32,32 2006.285.23:45:07.63/vb/08,04,usb,yes,29,32 2006.285.23:45:07.86/vblo/01,629.99,yes,locked 2006.285.23:45:07.86/vblo/02,634.99,yes,locked 2006.285.23:45:07.86/vblo/03,649.99,yes,locked 2006.285.23:45:07.86/vblo/04,679.99,yes,locked 2006.285.23:45:07.86/vblo/05,709.99,yes,locked 2006.285.23:45:07.86/vblo/06,719.99,yes,locked 2006.285.23:45:07.86/vblo/07,734.99,yes,locked 2006.285.23:45:07.86/vblo/08,744.99,yes,locked 2006.285.23:45:08.01/vabw/8 2006.285.23:45:08.16/vbbw/8 2006.285.23:45:08.25/xfe/off,on,12.0 2006.285.23:45:08.62/ifatt/23,28,28,28 2006.285.23:45:09.07/fmout-gps/S +2.70E-07 2006.285.23:45:09.09:!2006.285.23:47:05 2006.285.23:47:05.00:data_valid=off 2006.285.23:47:05.00:"et 2006.285.23:47:05.00:!+3s 2006.285.23:47:08.01:"tape 2006.285.23:47:08.01:postob 2006.285.23:47:08.22/cable/+6.5092E-03 2006.285.23:47:08.22/wx/19.51,1016.5,87 2006.285.23:47:09.07/fmout-gps/S +2.69E-07 2006.285.23:47:09.07:scan_name=285-2349,jd0610,200 2006.285.23:47:09.07:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.285.23:47:09.14#flagr#flagr/antenna,new-source 2006.285.23:47:10.14:checkk5 2006.285.23:47:10.56/chk_autoobs//k5ts1/ autoobs is running! 2006.285.23:47:10.94/chk_autoobs//k5ts2/ autoobs is running! 2006.285.23:47:11.71/chk_autoobs//k5ts3/ autoobs is running! 2006.285.23:47:12.34/chk_autoobs//k5ts4/ autoobs is running! 2006.285.23:47:12.69/chk_obsdata//k5ts1/T2852345??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.23:47:13.05/chk_obsdata//k5ts2/T2852345??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.23:47:13.47/chk_obsdata//k5ts3/T2852345??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.23:47:13.85/chk_obsdata//k5ts4/T2852345??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.285.23:47:14.51/k5log//k5ts1_log_newline 2006.285.23:47:15.27/k5log//k5ts2_log_newline 2006.285.23:47:16.03/k5log//k5ts3_log_newline 2006.285.23:47:17.10/k5log//k5ts4_log_newline 2006.285.23:47:17.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.23:47:17.12:setupk4=1 2006.285.23:47:17.12$setupk4/echo=on 2006.285.23:47:17.12$setupk4/pcalon 2006.285.23:47:17.12$pcalon/"no phase cal control is implemented here 2006.285.23:47:17.12$setupk4/"tpicd=stop 2006.285.23:47:17.12$setupk4/"rec=synch_on 2006.285.23:47:17.12$setupk4/"rec_mode=128 2006.285.23:47:17.12$setupk4/!* 2006.285.23:47:17.12$setupk4/recpk4 2006.285.23:47:17.12$recpk4/recpatch= 2006.285.23:47:17.12$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.23:47:17.12$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.23:47:17.12$setupk4/vck44 2006.285.23:47:17.12$vck44/valo=1,524.99 2006.285.23:47:17.13#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.23:47:17.13#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.23:47:17.13#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:17.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:47:17.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:47:17.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:47:17.13#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:47:17.13#ibcon#first serial, iclass 37, count 0 2006.285.23:47:17.13#ibcon#enter sib2, iclass 37, count 0 2006.285.23:47:17.13#ibcon#flushed, iclass 37, count 0 2006.285.23:47:17.13#ibcon#about to write, iclass 37, count 0 2006.285.23:47:17.13#ibcon#wrote, iclass 37, count 0 2006.285.23:47:17.13#ibcon#about to read 3, iclass 37, count 0 2006.285.23:47:17.14#ibcon#read 3, iclass 37, count 0 2006.285.23:47:17.14#ibcon#about to read 4, iclass 37, count 0 2006.285.23:47:17.14#ibcon#read 4, iclass 37, count 0 2006.285.23:47:17.14#ibcon#about to read 5, iclass 37, count 0 2006.285.23:47:17.14#ibcon#read 5, iclass 37, count 0 2006.285.23:47:17.14#ibcon#about to read 6, iclass 37, count 0 2006.285.23:47:17.14#ibcon#read 6, iclass 37, count 0 2006.285.23:47:17.14#ibcon#end of sib2, iclass 37, count 0 2006.285.23:47:17.14#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:47:17.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:47:17.14#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.23:47:17.14#ibcon#*before write, iclass 37, count 0 2006.285.23:47:17.14#ibcon#enter sib2, iclass 37, count 0 2006.285.23:47:17.14#ibcon#flushed, iclass 37, count 0 2006.285.23:47:17.14#ibcon#about to write, iclass 37, count 0 2006.285.23:47:17.14#ibcon#wrote, iclass 37, count 0 2006.285.23:47:17.14#ibcon#about to read 3, iclass 37, count 0 2006.285.23:47:17.19#ibcon#read 3, iclass 37, count 0 2006.285.23:47:17.19#ibcon#about to read 4, iclass 37, count 0 2006.285.23:47:17.19#ibcon#read 4, iclass 37, count 0 2006.285.23:47:17.19#ibcon#about to read 5, iclass 37, count 0 2006.285.23:47:17.19#ibcon#read 5, iclass 37, count 0 2006.285.23:47:17.19#ibcon#about to read 6, iclass 37, count 0 2006.285.23:47:17.19#ibcon#read 6, iclass 37, count 0 2006.285.23:47:17.19#ibcon#end of sib2, iclass 37, count 0 2006.285.23:47:17.19#ibcon#*after write, iclass 37, count 0 2006.285.23:47:17.19#ibcon#*before return 0, iclass 37, count 0 2006.285.23:47:17.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:47:17.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:47:17.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:47:17.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:47:17.20$vck44/va=1,7 2006.285.23:47:17.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.23:47:17.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.23:47:17.20#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:17.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:47:17.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:47:17.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:47:17.20#ibcon#enter wrdev, iclass 39, count 2 2006.285.23:47:17.20#ibcon#first serial, iclass 39, count 2 2006.285.23:47:17.20#ibcon#enter sib2, iclass 39, count 2 2006.285.23:47:17.20#ibcon#flushed, iclass 39, count 2 2006.285.23:47:17.20#ibcon#about to write, iclass 39, count 2 2006.285.23:47:17.20#ibcon#wrote, iclass 39, count 2 2006.285.23:47:17.20#ibcon#about to read 3, iclass 39, count 2 2006.285.23:47:17.21#ibcon#read 3, iclass 39, count 2 2006.285.23:47:17.21#ibcon#about to read 4, iclass 39, count 2 2006.285.23:47:17.21#ibcon#read 4, iclass 39, count 2 2006.285.23:47:17.21#ibcon#about to read 5, iclass 39, count 2 2006.285.23:47:17.21#ibcon#read 5, iclass 39, count 2 2006.285.23:47:17.21#ibcon#about to read 6, iclass 39, count 2 2006.285.23:47:17.21#ibcon#read 6, iclass 39, count 2 2006.285.23:47:17.21#ibcon#end of sib2, iclass 39, count 2 2006.285.23:47:17.21#ibcon#*mode == 0, iclass 39, count 2 2006.285.23:47:17.21#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.23:47:17.21#ibcon#[25=AT01-07\r\n] 2006.285.23:47:17.21#ibcon#*before write, iclass 39, count 2 2006.285.23:47:17.21#ibcon#enter sib2, iclass 39, count 2 2006.285.23:47:17.21#ibcon#flushed, iclass 39, count 2 2006.285.23:47:17.21#ibcon#about to write, iclass 39, count 2 2006.285.23:47:17.21#ibcon#wrote, iclass 39, count 2 2006.285.23:47:17.21#ibcon#about to read 3, iclass 39, count 2 2006.285.23:47:17.24#ibcon#read 3, iclass 39, count 2 2006.285.23:47:17.24#ibcon#about to read 4, iclass 39, count 2 2006.285.23:47:17.24#ibcon#read 4, iclass 39, count 2 2006.285.23:47:17.24#ibcon#about to read 5, iclass 39, count 2 2006.285.23:47:17.24#ibcon#read 5, iclass 39, count 2 2006.285.23:47:17.24#ibcon#about to read 6, iclass 39, count 2 2006.285.23:47:17.24#ibcon#read 6, iclass 39, count 2 2006.285.23:47:17.24#ibcon#end of sib2, iclass 39, count 2 2006.285.23:47:17.24#ibcon#*after write, iclass 39, count 2 2006.285.23:47:17.24#ibcon#*before return 0, iclass 39, count 2 2006.285.23:47:17.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:47:17.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:47:17.24#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.23:47:17.24#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:17.24#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:47:17.36#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:47:17.36#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:47:17.36#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:47:17.36#ibcon#first serial, iclass 39, count 0 2006.285.23:47:17.36#ibcon#enter sib2, iclass 39, count 0 2006.285.23:47:17.36#ibcon#flushed, iclass 39, count 0 2006.285.23:47:17.36#ibcon#about to write, iclass 39, count 0 2006.285.23:47:17.36#ibcon#wrote, iclass 39, count 0 2006.285.23:47:17.36#ibcon#about to read 3, iclass 39, count 0 2006.285.23:47:17.38#ibcon#read 3, iclass 39, count 0 2006.285.23:47:17.38#ibcon#about to read 4, iclass 39, count 0 2006.285.23:47:17.38#ibcon#read 4, iclass 39, count 0 2006.285.23:47:17.38#ibcon#about to read 5, iclass 39, count 0 2006.285.23:47:17.38#ibcon#read 5, iclass 39, count 0 2006.285.23:47:17.38#ibcon#about to read 6, iclass 39, count 0 2006.285.23:47:17.38#ibcon#read 6, iclass 39, count 0 2006.285.23:47:17.38#ibcon#end of sib2, iclass 39, count 0 2006.285.23:47:17.38#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:47:17.38#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:47:17.38#ibcon#[25=USB\r\n] 2006.285.23:47:17.38#ibcon#*before write, iclass 39, count 0 2006.285.23:47:17.38#ibcon#enter sib2, iclass 39, count 0 2006.285.23:47:17.38#ibcon#flushed, iclass 39, count 0 2006.285.23:47:17.38#ibcon#about to write, iclass 39, count 0 2006.285.23:47:17.38#ibcon#wrote, iclass 39, count 0 2006.285.23:47:17.38#ibcon#about to read 3, iclass 39, count 0 2006.285.23:47:17.41#ibcon#read 3, iclass 39, count 0 2006.285.23:47:17.41#ibcon#about to read 4, iclass 39, count 0 2006.285.23:47:17.41#ibcon#read 4, iclass 39, count 0 2006.285.23:47:17.41#ibcon#about to read 5, iclass 39, count 0 2006.285.23:47:17.41#ibcon#read 5, iclass 39, count 0 2006.285.23:47:17.41#ibcon#about to read 6, iclass 39, count 0 2006.285.23:47:17.41#ibcon#read 6, iclass 39, count 0 2006.285.23:47:17.41#ibcon#end of sib2, iclass 39, count 0 2006.285.23:47:17.41#ibcon#*after write, iclass 39, count 0 2006.285.23:47:17.41#ibcon#*before return 0, iclass 39, count 0 2006.285.23:47:17.41#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:47:17.41#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:47:17.41#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:47:17.41#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:47:17.41$vck44/valo=2,534.99 2006.285.23:47:17.41#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.23:47:17.41#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.23:47:17.41#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:17.41#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:47:17.41#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:47:17.41#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:47:17.41#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:47:17.41#ibcon#first serial, iclass 3, count 0 2006.285.23:47:17.41#ibcon#enter sib2, iclass 3, count 0 2006.285.23:47:17.41#ibcon#flushed, iclass 3, count 0 2006.285.23:47:17.41#ibcon#about to write, iclass 3, count 0 2006.285.23:47:17.41#ibcon#wrote, iclass 3, count 0 2006.285.23:47:17.41#ibcon#about to read 3, iclass 3, count 0 2006.285.23:47:17.43#ibcon#read 3, iclass 3, count 0 2006.285.23:47:17.43#ibcon#about to read 4, iclass 3, count 0 2006.285.23:47:17.43#ibcon#read 4, iclass 3, count 0 2006.285.23:47:17.43#ibcon#about to read 5, iclass 3, count 0 2006.285.23:47:17.43#ibcon#read 5, iclass 3, count 0 2006.285.23:47:17.43#ibcon#about to read 6, iclass 3, count 0 2006.285.23:47:17.43#ibcon#read 6, iclass 3, count 0 2006.285.23:47:17.43#ibcon#end of sib2, iclass 3, count 0 2006.285.23:47:17.43#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:47:17.43#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:47:17.43#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.23:47:17.43#ibcon#*before write, iclass 3, count 0 2006.285.23:47:17.43#ibcon#enter sib2, iclass 3, count 0 2006.285.23:47:17.43#ibcon#flushed, iclass 3, count 0 2006.285.23:47:17.43#ibcon#about to write, iclass 3, count 0 2006.285.23:47:17.43#ibcon#wrote, iclass 3, count 0 2006.285.23:47:17.43#ibcon#about to read 3, iclass 3, count 0 2006.285.23:47:17.47#ibcon#read 3, iclass 3, count 0 2006.285.23:47:17.47#ibcon#about to read 4, iclass 3, count 0 2006.285.23:47:17.47#ibcon#read 4, iclass 3, count 0 2006.285.23:47:17.47#ibcon#about to read 5, iclass 3, count 0 2006.285.23:47:17.47#ibcon#read 5, iclass 3, count 0 2006.285.23:47:17.47#ibcon#about to read 6, iclass 3, count 0 2006.285.23:47:17.47#ibcon#read 6, iclass 3, count 0 2006.285.23:47:17.47#ibcon#end of sib2, iclass 3, count 0 2006.285.23:47:17.47#ibcon#*after write, iclass 3, count 0 2006.285.23:47:17.47#ibcon#*before return 0, iclass 3, count 0 2006.285.23:47:17.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:47:17.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:47:17.47#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:47:17.47#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:47:17.47$vck44/va=2,6 2006.285.23:47:17.47#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.23:47:17.47#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.23:47:17.47#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:17.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:47:17.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:47:17.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:47:17.53#ibcon#enter wrdev, iclass 5, count 2 2006.285.23:47:17.53#ibcon#first serial, iclass 5, count 2 2006.285.23:47:17.53#ibcon#enter sib2, iclass 5, count 2 2006.285.23:47:17.53#ibcon#flushed, iclass 5, count 2 2006.285.23:47:17.53#ibcon#about to write, iclass 5, count 2 2006.285.23:47:17.53#ibcon#wrote, iclass 5, count 2 2006.285.23:47:17.53#ibcon#about to read 3, iclass 5, count 2 2006.285.23:47:17.55#ibcon#read 3, iclass 5, count 2 2006.285.23:47:17.55#ibcon#about to read 4, iclass 5, count 2 2006.285.23:47:17.55#ibcon#read 4, iclass 5, count 2 2006.285.23:47:17.55#ibcon#about to read 5, iclass 5, count 2 2006.285.23:47:17.55#ibcon#read 5, iclass 5, count 2 2006.285.23:47:17.55#ibcon#about to read 6, iclass 5, count 2 2006.285.23:47:17.55#ibcon#read 6, iclass 5, count 2 2006.285.23:47:17.55#ibcon#end of sib2, iclass 5, count 2 2006.285.23:47:17.55#ibcon#*mode == 0, iclass 5, count 2 2006.285.23:47:17.55#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.23:47:17.55#ibcon#[25=AT02-06\r\n] 2006.285.23:47:17.55#ibcon#*before write, iclass 5, count 2 2006.285.23:47:17.55#ibcon#enter sib2, iclass 5, count 2 2006.285.23:47:17.55#ibcon#flushed, iclass 5, count 2 2006.285.23:47:17.55#ibcon#about to write, iclass 5, count 2 2006.285.23:47:17.55#ibcon#wrote, iclass 5, count 2 2006.285.23:47:17.55#ibcon#about to read 3, iclass 5, count 2 2006.285.23:47:17.58#ibcon#read 3, iclass 5, count 2 2006.285.23:47:17.58#ibcon#about to read 4, iclass 5, count 2 2006.285.23:47:17.58#ibcon#read 4, iclass 5, count 2 2006.285.23:47:17.58#ibcon#about to read 5, iclass 5, count 2 2006.285.23:47:17.58#ibcon#read 5, iclass 5, count 2 2006.285.23:47:17.58#ibcon#about to read 6, iclass 5, count 2 2006.285.23:47:17.58#ibcon#read 6, iclass 5, count 2 2006.285.23:47:17.58#ibcon#end of sib2, iclass 5, count 2 2006.285.23:47:17.58#ibcon#*after write, iclass 5, count 2 2006.285.23:47:17.58#ibcon#*before return 0, iclass 5, count 2 2006.285.23:47:17.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:47:17.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:47:17.58#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.23:47:17.58#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:17.58#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:47:17.70#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:47:17.70#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:47:17.70#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:47:17.70#ibcon#first serial, iclass 5, count 0 2006.285.23:47:17.70#ibcon#enter sib2, iclass 5, count 0 2006.285.23:47:17.70#ibcon#flushed, iclass 5, count 0 2006.285.23:47:17.70#ibcon#about to write, iclass 5, count 0 2006.285.23:47:17.70#ibcon#wrote, iclass 5, count 0 2006.285.23:47:17.70#ibcon#about to read 3, iclass 5, count 0 2006.285.23:47:17.72#ibcon#read 3, iclass 5, count 0 2006.285.23:47:17.72#ibcon#about to read 4, iclass 5, count 0 2006.285.23:47:17.72#ibcon#read 4, iclass 5, count 0 2006.285.23:47:17.72#ibcon#about to read 5, iclass 5, count 0 2006.285.23:47:17.72#ibcon#read 5, iclass 5, count 0 2006.285.23:47:17.72#ibcon#about to read 6, iclass 5, count 0 2006.285.23:47:17.72#ibcon#read 6, iclass 5, count 0 2006.285.23:47:17.72#ibcon#end of sib2, iclass 5, count 0 2006.285.23:47:17.72#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:47:17.72#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:47:17.72#ibcon#[25=USB\r\n] 2006.285.23:47:17.72#ibcon#*before write, iclass 5, count 0 2006.285.23:47:17.72#ibcon#enter sib2, iclass 5, count 0 2006.285.23:47:17.72#ibcon#flushed, iclass 5, count 0 2006.285.23:47:17.72#ibcon#about to write, iclass 5, count 0 2006.285.23:47:17.72#ibcon#wrote, iclass 5, count 0 2006.285.23:47:17.72#ibcon#about to read 3, iclass 5, count 0 2006.285.23:47:17.75#ibcon#read 3, iclass 5, count 0 2006.285.23:47:17.75#ibcon#about to read 4, iclass 5, count 0 2006.285.23:47:17.75#ibcon#read 4, iclass 5, count 0 2006.285.23:47:17.75#ibcon#about to read 5, iclass 5, count 0 2006.285.23:47:17.75#ibcon#read 5, iclass 5, count 0 2006.285.23:47:17.75#ibcon#about to read 6, iclass 5, count 0 2006.285.23:47:17.75#ibcon#read 6, iclass 5, count 0 2006.285.23:47:17.75#ibcon#end of sib2, iclass 5, count 0 2006.285.23:47:17.75#ibcon#*after write, iclass 5, count 0 2006.285.23:47:17.75#ibcon#*before return 0, iclass 5, count 0 2006.285.23:47:17.75#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:47:17.75#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:47:17.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:47:17.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:47:17.75$vck44/valo=3,564.99 2006.285.23:47:17.75#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.23:47:17.75#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.23:47:17.75#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:17.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:47:17.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:47:17.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:47:17.75#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:47:17.75#ibcon#first serial, iclass 7, count 0 2006.285.23:47:17.75#ibcon#enter sib2, iclass 7, count 0 2006.285.23:47:17.75#ibcon#flushed, iclass 7, count 0 2006.285.23:47:17.75#ibcon#about to write, iclass 7, count 0 2006.285.23:47:17.75#ibcon#wrote, iclass 7, count 0 2006.285.23:47:17.75#ibcon#about to read 3, iclass 7, count 0 2006.285.23:47:17.77#ibcon#read 3, iclass 7, count 0 2006.285.23:47:17.77#ibcon#about to read 4, iclass 7, count 0 2006.285.23:47:17.77#ibcon#read 4, iclass 7, count 0 2006.285.23:47:17.77#ibcon#about to read 5, iclass 7, count 0 2006.285.23:47:17.77#ibcon#read 5, iclass 7, count 0 2006.285.23:47:17.77#ibcon#about to read 6, iclass 7, count 0 2006.285.23:47:17.77#ibcon#read 6, iclass 7, count 0 2006.285.23:47:17.77#ibcon#end of sib2, iclass 7, count 0 2006.285.23:47:17.77#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:47:17.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:47:17.77#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.23:47:17.77#ibcon#*before write, iclass 7, count 0 2006.285.23:47:17.77#ibcon#enter sib2, iclass 7, count 0 2006.285.23:47:17.77#ibcon#flushed, iclass 7, count 0 2006.285.23:47:17.77#ibcon#about to write, iclass 7, count 0 2006.285.23:47:17.77#ibcon#wrote, iclass 7, count 0 2006.285.23:47:17.77#ibcon#about to read 3, iclass 7, count 0 2006.285.23:47:17.81#ibcon#read 3, iclass 7, count 0 2006.285.23:47:17.81#ibcon#about to read 4, iclass 7, count 0 2006.285.23:47:17.81#ibcon#read 4, iclass 7, count 0 2006.285.23:47:17.81#ibcon#about to read 5, iclass 7, count 0 2006.285.23:47:17.81#ibcon#read 5, iclass 7, count 0 2006.285.23:47:17.81#ibcon#about to read 6, iclass 7, count 0 2006.285.23:47:17.81#ibcon#read 6, iclass 7, count 0 2006.285.23:47:17.81#ibcon#end of sib2, iclass 7, count 0 2006.285.23:47:17.81#ibcon#*after write, iclass 7, count 0 2006.285.23:47:17.81#ibcon#*before return 0, iclass 7, count 0 2006.285.23:47:17.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:47:17.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:47:17.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:47:17.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:47:17.81$vck44/va=3,7 2006.285.23:47:17.81#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.23:47:17.81#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.23:47:17.81#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:17.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:47:17.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:47:17.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:47:17.87#ibcon#enter wrdev, iclass 11, count 2 2006.285.23:47:17.87#ibcon#first serial, iclass 11, count 2 2006.285.23:47:17.87#ibcon#enter sib2, iclass 11, count 2 2006.285.23:47:17.87#ibcon#flushed, iclass 11, count 2 2006.285.23:47:17.87#ibcon#about to write, iclass 11, count 2 2006.285.23:47:17.87#ibcon#wrote, iclass 11, count 2 2006.285.23:47:17.87#ibcon#about to read 3, iclass 11, count 2 2006.285.23:47:17.89#ibcon#read 3, iclass 11, count 2 2006.285.23:47:17.89#ibcon#about to read 4, iclass 11, count 2 2006.285.23:47:17.89#ibcon#read 4, iclass 11, count 2 2006.285.23:47:17.89#ibcon#about to read 5, iclass 11, count 2 2006.285.23:47:17.89#ibcon#read 5, iclass 11, count 2 2006.285.23:47:17.89#ibcon#about to read 6, iclass 11, count 2 2006.285.23:47:17.89#ibcon#read 6, iclass 11, count 2 2006.285.23:47:17.89#ibcon#end of sib2, iclass 11, count 2 2006.285.23:47:17.89#ibcon#*mode == 0, iclass 11, count 2 2006.285.23:47:17.89#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.23:47:17.89#ibcon#[25=AT03-07\r\n] 2006.285.23:47:17.89#ibcon#*before write, iclass 11, count 2 2006.285.23:47:17.89#ibcon#enter sib2, iclass 11, count 2 2006.285.23:47:17.89#ibcon#flushed, iclass 11, count 2 2006.285.23:47:17.89#ibcon#about to write, iclass 11, count 2 2006.285.23:47:17.89#ibcon#wrote, iclass 11, count 2 2006.285.23:47:17.89#ibcon#about to read 3, iclass 11, count 2 2006.285.23:47:17.92#ibcon#read 3, iclass 11, count 2 2006.285.23:47:17.92#ibcon#about to read 4, iclass 11, count 2 2006.285.23:47:17.92#ibcon#read 4, iclass 11, count 2 2006.285.23:47:17.92#ibcon#about to read 5, iclass 11, count 2 2006.285.23:47:17.92#ibcon#read 5, iclass 11, count 2 2006.285.23:47:17.92#ibcon#about to read 6, iclass 11, count 2 2006.285.23:47:17.92#ibcon#read 6, iclass 11, count 2 2006.285.23:47:17.92#ibcon#end of sib2, iclass 11, count 2 2006.285.23:47:17.92#ibcon#*after write, iclass 11, count 2 2006.285.23:47:17.92#ibcon#*before return 0, iclass 11, count 2 2006.285.23:47:17.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:47:17.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:47:17.92#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.23:47:17.92#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:17.92#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:47:18.04#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:47:18.04#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:47:18.04#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:47:18.04#ibcon#first serial, iclass 11, count 0 2006.285.23:47:18.04#ibcon#enter sib2, iclass 11, count 0 2006.285.23:47:18.04#ibcon#flushed, iclass 11, count 0 2006.285.23:47:18.04#ibcon#about to write, iclass 11, count 0 2006.285.23:47:18.04#ibcon#wrote, iclass 11, count 0 2006.285.23:47:18.04#ibcon#about to read 3, iclass 11, count 0 2006.285.23:47:18.06#ibcon#read 3, iclass 11, count 0 2006.285.23:47:18.06#ibcon#about to read 4, iclass 11, count 0 2006.285.23:47:18.06#ibcon#read 4, iclass 11, count 0 2006.285.23:47:18.06#ibcon#about to read 5, iclass 11, count 0 2006.285.23:47:18.06#ibcon#read 5, iclass 11, count 0 2006.285.23:47:18.06#ibcon#about to read 6, iclass 11, count 0 2006.285.23:47:18.06#ibcon#read 6, iclass 11, count 0 2006.285.23:47:18.06#ibcon#end of sib2, iclass 11, count 0 2006.285.23:47:18.06#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:47:18.06#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:47:18.06#ibcon#[25=USB\r\n] 2006.285.23:47:18.06#ibcon#*before write, iclass 11, count 0 2006.285.23:47:18.06#ibcon#enter sib2, iclass 11, count 0 2006.285.23:47:18.06#ibcon#flushed, iclass 11, count 0 2006.285.23:47:18.06#ibcon#about to write, iclass 11, count 0 2006.285.23:47:18.06#ibcon#wrote, iclass 11, count 0 2006.285.23:47:18.06#ibcon#about to read 3, iclass 11, count 0 2006.285.23:47:18.09#ibcon#read 3, iclass 11, count 0 2006.285.23:47:18.09#ibcon#about to read 4, iclass 11, count 0 2006.285.23:47:18.09#ibcon#read 4, iclass 11, count 0 2006.285.23:47:18.09#ibcon#about to read 5, iclass 11, count 0 2006.285.23:47:18.09#ibcon#read 5, iclass 11, count 0 2006.285.23:47:18.09#ibcon#about to read 6, iclass 11, count 0 2006.285.23:47:18.09#ibcon#read 6, iclass 11, count 0 2006.285.23:47:18.09#ibcon#end of sib2, iclass 11, count 0 2006.285.23:47:18.09#ibcon#*after write, iclass 11, count 0 2006.285.23:47:18.09#ibcon#*before return 0, iclass 11, count 0 2006.285.23:47:18.09#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:47:18.09#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:47:18.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:47:18.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:47:18.09$vck44/valo=4,624.99 2006.285.23:47:18.09#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.23:47:18.09#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.23:47:18.09#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:18.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:47:18.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:47:18.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:47:18.09#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:47:18.09#ibcon#first serial, iclass 13, count 0 2006.285.23:47:18.09#ibcon#enter sib2, iclass 13, count 0 2006.285.23:47:18.09#ibcon#flushed, iclass 13, count 0 2006.285.23:47:18.09#ibcon#about to write, iclass 13, count 0 2006.285.23:47:18.09#ibcon#wrote, iclass 13, count 0 2006.285.23:47:18.09#ibcon#about to read 3, iclass 13, count 0 2006.285.23:47:18.11#ibcon#read 3, iclass 13, count 0 2006.285.23:47:18.11#ibcon#about to read 4, iclass 13, count 0 2006.285.23:47:18.11#ibcon#read 4, iclass 13, count 0 2006.285.23:47:18.11#ibcon#about to read 5, iclass 13, count 0 2006.285.23:47:18.11#ibcon#read 5, iclass 13, count 0 2006.285.23:47:18.11#ibcon#about to read 6, iclass 13, count 0 2006.285.23:47:18.11#ibcon#read 6, iclass 13, count 0 2006.285.23:47:18.11#ibcon#end of sib2, iclass 13, count 0 2006.285.23:47:18.11#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:47:18.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:47:18.11#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.23:47:18.11#ibcon#*before write, iclass 13, count 0 2006.285.23:47:18.11#ibcon#enter sib2, iclass 13, count 0 2006.285.23:47:18.11#ibcon#flushed, iclass 13, count 0 2006.285.23:47:18.11#ibcon#about to write, iclass 13, count 0 2006.285.23:47:18.11#ibcon#wrote, iclass 13, count 0 2006.285.23:47:18.11#ibcon#about to read 3, iclass 13, count 0 2006.285.23:47:18.15#ibcon#read 3, iclass 13, count 0 2006.285.23:47:18.15#ibcon#about to read 4, iclass 13, count 0 2006.285.23:47:18.15#ibcon#read 4, iclass 13, count 0 2006.285.23:47:18.15#ibcon#about to read 5, iclass 13, count 0 2006.285.23:47:18.15#ibcon#read 5, iclass 13, count 0 2006.285.23:47:18.15#ibcon#about to read 6, iclass 13, count 0 2006.285.23:47:18.15#ibcon#read 6, iclass 13, count 0 2006.285.23:47:18.15#ibcon#end of sib2, iclass 13, count 0 2006.285.23:47:18.15#ibcon#*after write, iclass 13, count 0 2006.285.23:47:18.15#ibcon#*before return 0, iclass 13, count 0 2006.285.23:47:18.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:47:18.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:47:18.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:47:18.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:47:18.15$vck44/va=4,6 2006.285.23:47:18.15#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.23:47:18.15#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.23:47:18.15#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:18.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:47:18.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:47:18.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:47:18.21#ibcon#enter wrdev, iclass 15, count 2 2006.285.23:47:18.21#ibcon#first serial, iclass 15, count 2 2006.285.23:47:18.21#ibcon#enter sib2, iclass 15, count 2 2006.285.23:47:18.21#ibcon#flushed, iclass 15, count 2 2006.285.23:47:18.21#ibcon#about to write, iclass 15, count 2 2006.285.23:47:18.21#ibcon#wrote, iclass 15, count 2 2006.285.23:47:18.21#ibcon#about to read 3, iclass 15, count 2 2006.285.23:47:18.23#ibcon#read 3, iclass 15, count 2 2006.285.23:47:18.23#ibcon#about to read 4, iclass 15, count 2 2006.285.23:47:18.23#ibcon#read 4, iclass 15, count 2 2006.285.23:47:18.23#ibcon#about to read 5, iclass 15, count 2 2006.285.23:47:18.23#ibcon#read 5, iclass 15, count 2 2006.285.23:47:18.23#ibcon#about to read 6, iclass 15, count 2 2006.285.23:47:18.23#ibcon#read 6, iclass 15, count 2 2006.285.23:47:18.23#ibcon#end of sib2, iclass 15, count 2 2006.285.23:47:18.23#ibcon#*mode == 0, iclass 15, count 2 2006.285.23:47:18.23#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.23:47:18.23#ibcon#[25=AT04-06\r\n] 2006.285.23:47:18.23#ibcon#*before write, iclass 15, count 2 2006.285.23:47:18.23#ibcon#enter sib2, iclass 15, count 2 2006.285.23:47:18.23#ibcon#flushed, iclass 15, count 2 2006.285.23:47:18.23#ibcon#about to write, iclass 15, count 2 2006.285.23:47:18.23#ibcon#wrote, iclass 15, count 2 2006.285.23:47:18.23#ibcon#about to read 3, iclass 15, count 2 2006.285.23:47:18.26#ibcon#read 3, iclass 15, count 2 2006.285.23:47:18.26#ibcon#about to read 4, iclass 15, count 2 2006.285.23:47:18.26#ibcon#read 4, iclass 15, count 2 2006.285.23:47:18.26#ibcon#about to read 5, iclass 15, count 2 2006.285.23:47:18.26#ibcon#read 5, iclass 15, count 2 2006.285.23:47:18.26#ibcon#about to read 6, iclass 15, count 2 2006.285.23:47:18.26#ibcon#read 6, iclass 15, count 2 2006.285.23:47:18.26#ibcon#end of sib2, iclass 15, count 2 2006.285.23:47:18.26#ibcon#*after write, iclass 15, count 2 2006.285.23:47:18.26#ibcon#*before return 0, iclass 15, count 2 2006.285.23:47:18.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:47:18.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:47:18.26#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.23:47:18.26#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:18.26#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:47:18.38#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:47:18.38#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:47:18.38#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:47:18.38#ibcon#first serial, iclass 15, count 0 2006.285.23:47:18.38#ibcon#enter sib2, iclass 15, count 0 2006.285.23:47:18.38#ibcon#flushed, iclass 15, count 0 2006.285.23:47:18.38#ibcon#about to write, iclass 15, count 0 2006.285.23:47:18.38#ibcon#wrote, iclass 15, count 0 2006.285.23:47:18.38#ibcon#about to read 3, iclass 15, count 0 2006.285.23:47:18.40#ibcon#read 3, iclass 15, count 0 2006.285.23:47:18.40#ibcon#about to read 4, iclass 15, count 0 2006.285.23:47:18.40#ibcon#read 4, iclass 15, count 0 2006.285.23:47:18.40#ibcon#about to read 5, iclass 15, count 0 2006.285.23:47:18.40#ibcon#read 5, iclass 15, count 0 2006.285.23:47:18.40#ibcon#about to read 6, iclass 15, count 0 2006.285.23:47:18.40#ibcon#read 6, iclass 15, count 0 2006.285.23:47:18.40#ibcon#end of sib2, iclass 15, count 0 2006.285.23:47:18.40#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:47:18.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:47:18.40#ibcon#[25=USB\r\n] 2006.285.23:47:18.40#ibcon#*before write, iclass 15, count 0 2006.285.23:47:18.40#ibcon#enter sib2, iclass 15, count 0 2006.285.23:47:18.40#ibcon#flushed, iclass 15, count 0 2006.285.23:47:18.40#ibcon#about to write, iclass 15, count 0 2006.285.23:47:18.40#ibcon#wrote, iclass 15, count 0 2006.285.23:47:18.40#ibcon#about to read 3, iclass 15, count 0 2006.285.23:47:18.43#ibcon#read 3, iclass 15, count 0 2006.285.23:47:18.43#ibcon#about to read 4, iclass 15, count 0 2006.285.23:47:18.43#ibcon#read 4, iclass 15, count 0 2006.285.23:47:18.43#ibcon#about to read 5, iclass 15, count 0 2006.285.23:47:18.43#ibcon#read 5, iclass 15, count 0 2006.285.23:47:18.43#ibcon#about to read 6, iclass 15, count 0 2006.285.23:47:18.43#ibcon#read 6, iclass 15, count 0 2006.285.23:47:18.43#ibcon#end of sib2, iclass 15, count 0 2006.285.23:47:18.43#ibcon#*after write, iclass 15, count 0 2006.285.23:47:18.43#ibcon#*before return 0, iclass 15, count 0 2006.285.23:47:18.43#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:47:18.43#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:47:18.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:47:18.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:47:18.43$vck44/valo=5,734.99 2006.285.23:47:18.43#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.23:47:18.43#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.23:47:18.43#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:18.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:47:18.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:47:18.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:47:18.43#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:47:18.43#ibcon#first serial, iclass 17, count 0 2006.285.23:47:18.43#ibcon#enter sib2, iclass 17, count 0 2006.285.23:47:18.43#ibcon#flushed, iclass 17, count 0 2006.285.23:47:18.43#ibcon#about to write, iclass 17, count 0 2006.285.23:47:18.43#ibcon#wrote, iclass 17, count 0 2006.285.23:47:18.43#ibcon#about to read 3, iclass 17, count 0 2006.285.23:47:18.45#ibcon#read 3, iclass 17, count 0 2006.285.23:47:18.45#ibcon#about to read 4, iclass 17, count 0 2006.285.23:47:18.45#ibcon#read 4, iclass 17, count 0 2006.285.23:47:18.45#ibcon#about to read 5, iclass 17, count 0 2006.285.23:47:18.45#ibcon#read 5, iclass 17, count 0 2006.285.23:47:18.45#ibcon#about to read 6, iclass 17, count 0 2006.285.23:47:18.45#ibcon#read 6, iclass 17, count 0 2006.285.23:47:18.45#ibcon#end of sib2, iclass 17, count 0 2006.285.23:47:18.45#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:47:18.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:47:18.45#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.23:47:18.45#ibcon#*before write, iclass 17, count 0 2006.285.23:47:18.45#ibcon#enter sib2, iclass 17, count 0 2006.285.23:47:18.45#ibcon#flushed, iclass 17, count 0 2006.285.23:47:18.45#ibcon#about to write, iclass 17, count 0 2006.285.23:47:18.45#ibcon#wrote, iclass 17, count 0 2006.285.23:47:18.45#ibcon#about to read 3, iclass 17, count 0 2006.285.23:47:18.49#ibcon#read 3, iclass 17, count 0 2006.285.23:47:18.49#ibcon#about to read 4, iclass 17, count 0 2006.285.23:47:18.49#ibcon#read 4, iclass 17, count 0 2006.285.23:47:18.49#ibcon#about to read 5, iclass 17, count 0 2006.285.23:47:18.49#ibcon#read 5, iclass 17, count 0 2006.285.23:47:18.49#ibcon#about to read 6, iclass 17, count 0 2006.285.23:47:18.49#ibcon#read 6, iclass 17, count 0 2006.285.23:47:18.49#ibcon#end of sib2, iclass 17, count 0 2006.285.23:47:18.49#ibcon#*after write, iclass 17, count 0 2006.285.23:47:18.49#ibcon#*before return 0, iclass 17, count 0 2006.285.23:47:18.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:47:18.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:47:18.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:47:18.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:47:18.49$vck44/va=5,3 2006.285.23:47:18.49#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.23:47:18.49#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.23:47:18.49#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:18.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:47:18.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:47:18.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:47:18.55#ibcon#enter wrdev, iclass 19, count 2 2006.285.23:47:18.55#ibcon#first serial, iclass 19, count 2 2006.285.23:47:18.55#ibcon#enter sib2, iclass 19, count 2 2006.285.23:47:18.55#ibcon#flushed, iclass 19, count 2 2006.285.23:47:18.55#ibcon#about to write, iclass 19, count 2 2006.285.23:47:18.55#ibcon#wrote, iclass 19, count 2 2006.285.23:47:18.55#ibcon#about to read 3, iclass 19, count 2 2006.285.23:47:18.57#ibcon#read 3, iclass 19, count 2 2006.285.23:47:18.57#ibcon#about to read 4, iclass 19, count 2 2006.285.23:47:18.57#ibcon#read 4, iclass 19, count 2 2006.285.23:47:18.57#ibcon#about to read 5, iclass 19, count 2 2006.285.23:47:18.57#ibcon#read 5, iclass 19, count 2 2006.285.23:47:18.57#ibcon#about to read 6, iclass 19, count 2 2006.285.23:47:18.57#ibcon#read 6, iclass 19, count 2 2006.285.23:47:18.57#ibcon#end of sib2, iclass 19, count 2 2006.285.23:47:18.57#ibcon#*mode == 0, iclass 19, count 2 2006.285.23:47:18.57#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.23:47:18.57#ibcon#[25=AT05-03\r\n] 2006.285.23:47:18.57#ibcon#*before write, iclass 19, count 2 2006.285.23:47:18.57#ibcon#enter sib2, iclass 19, count 2 2006.285.23:47:18.57#ibcon#flushed, iclass 19, count 2 2006.285.23:47:18.57#ibcon#about to write, iclass 19, count 2 2006.285.23:47:18.57#ibcon#wrote, iclass 19, count 2 2006.285.23:47:18.57#ibcon#about to read 3, iclass 19, count 2 2006.285.23:47:18.60#ibcon#read 3, iclass 19, count 2 2006.285.23:47:18.60#ibcon#about to read 4, iclass 19, count 2 2006.285.23:47:18.60#ibcon#read 4, iclass 19, count 2 2006.285.23:47:18.60#ibcon#about to read 5, iclass 19, count 2 2006.285.23:47:18.60#ibcon#read 5, iclass 19, count 2 2006.285.23:47:18.60#ibcon#about to read 6, iclass 19, count 2 2006.285.23:47:18.60#ibcon#read 6, iclass 19, count 2 2006.285.23:47:18.60#ibcon#end of sib2, iclass 19, count 2 2006.285.23:47:18.60#ibcon#*after write, iclass 19, count 2 2006.285.23:47:18.60#ibcon#*before return 0, iclass 19, count 2 2006.285.23:47:18.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:47:18.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:47:18.60#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.23:47:18.60#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:18.60#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:47:18.72#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:47:18.72#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:47:18.72#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:47:18.72#ibcon#first serial, iclass 19, count 0 2006.285.23:47:18.72#ibcon#enter sib2, iclass 19, count 0 2006.285.23:47:18.72#ibcon#flushed, iclass 19, count 0 2006.285.23:47:18.72#ibcon#about to write, iclass 19, count 0 2006.285.23:47:18.72#ibcon#wrote, iclass 19, count 0 2006.285.23:47:18.72#ibcon#about to read 3, iclass 19, count 0 2006.285.23:47:18.74#ibcon#read 3, iclass 19, count 0 2006.285.23:47:18.74#ibcon#about to read 4, iclass 19, count 0 2006.285.23:47:18.74#ibcon#read 4, iclass 19, count 0 2006.285.23:47:18.74#ibcon#about to read 5, iclass 19, count 0 2006.285.23:47:18.74#ibcon#read 5, iclass 19, count 0 2006.285.23:47:18.74#ibcon#about to read 6, iclass 19, count 0 2006.285.23:47:18.74#ibcon#read 6, iclass 19, count 0 2006.285.23:47:18.74#ibcon#end of sib2, iclass 19, count 0 2006.285.23:47:18.74#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:47:18.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:47:18.74#ibcon#[25=USB\r\n] 2006.285.23:47:18.74#ibcon#*before write, iclass 19, count 0 2006.285.23:47:18.74#ibcon#enter sib2, iclass 19, count 0 2006.285.23:47:18.74#ibcon#flushed, iclass 19, count 0 2006.285.23:47:18.74#ibcon#about to write, iclass 19, count 0 2006.285.23:47:18.74#ibcon#wrote, iclass 19, count 0 2006.285.23:47:18.74#ibcon#about to read 3, iclass 19, count 0 2006.285.23:47:18.77#ibcon#read 3, iclass 19, count 0 2006.285.23:47:18.77#ibcon#about to read 4, iclass 19, count 0 2006.285.23:47:18.77#ibcon#read 4, iclass 19, count 0 2006.285.23:47:18.77#ibcon#about to read 5, iclass 19, count 0 2006.285.23:47:18.77#ibcon#read 5, iclass 19, count 0 2006.285.23:47:18.77#ibcon#about to read 6, iclass 19, count 0 2006.285.23:47:18.77#ibcon#read 6, iclass 19, count 0 2006.285.23:47:18.77#ibcon#end of sib2, iclass 19, count 0 2006.285.23:47:18.77#ibcon#*after write, iclass 19, count 0 2006.285.23:47:18.77#ibcon#*before return 0, iclass 19, count 0 2006.285.23:47:18.77#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:47:18.77#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:47:18.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:47:18.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:47:18.77$vck44/valo=6,814.99 2006.285.23:47:18.77#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.23:47:18.77#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.23:47:18.77#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:18.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:47:18.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:47:18.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:47:18.77#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:47:18.77#ibcon#first serial, iclass 21, count 0 2006.285.23:47:18.77#ibcon#enter sib2, iclass 21, count 0 2006.285.23:47:18.77#ibcon#flushed, iclass 21, count 0 2006.285.23:47:18.77#ibcon#about to write, iclass 21, count 0 2006.285.23:47:18.77#ibcon#wrote, iclass 21, count 0 2006.285.23:47:18.77#ibcon#about to read 3, iclass 21, count 0 2006.285.23:47:18.79#ibcon#read 3, iclass 21, count 0 2006.285.23:47:18.79#ibcon#about to read 4, iclass 21, count 0 2006.285.23:47:18.79#ibcon#read 4, iclass 21, count 0 2006.285.23:47:18.79#ibcon#about to read 5, iclass 21, count 0 2006.285.23:47:18.79#ibcon#read 5, iclass 21, count 0 2006.285.23:47:18.79#ibcon#about to read 6, iclass 21, count 0 2006.285.23:47:18.79#ibcon#read 6, iclass 21, count 0 2006.285.23:47:18.79#ibcon#end of sib2, iclass 21, count 0 2006.285.23:47:18.79#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:47:18.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:47:18.79#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.23:47:18.79#ibcon#*before write, iclass 21, count 0 2006.285.23:47:18.79#ibcon#enter sib2, iclass 21, count 0 2006.285.23:47:18.79#ibcon#flushed, iclass 21, count 0 2006.285.23:47:18.79#ibcon#about to write, iclass 21, count 0 2006.285.23:47:18.79#ibcon#wrote, iclass 21, count 0 2006.285.23:47:18.79#ibcon#about to read 3, iclass 21, count 0 2006.285.23:47:18.83#ibcon#read 3, iclass 21, count 0 2006.285.23:47:18.83#ibcon#about to read 4, iclass 21, count 0 2006.285.23:47:18.83#ibcon#read 4, iclass 21, count 0 2006.285.23:47:18.83#ibcon#about to read 5, iclass 21, count 0 2006.285.23:47:18.83#ibcon#read 5, iclass 21, count 0 2006.285.23:47:18.83#ibcon#about to read 6, iclass 21, count 0 2006.285.23:47:18.83#ibcon#read 6, iclass 21, count 0 2006.285.23:47:18.83#ibcon#end of sib2, iclass 21, count 0 2006.285.23:47:18.83#ibcon#*after write, iclass 21, count 0 2006.285.23:47:18.83#ibcon#*before return 0, iclass 21, count 0 2006.285.23:47:18.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:47:18.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:47:18.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:47:18.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:47:18.83$vck44/va=6,4 2006.285.23:47:18.83#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.23:47:18.83#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.23:47:18.83#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:18.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:47:18.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:47:18.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:47:18.89#ibcon#enter wrdev, iclass 23, count 2 2006.285.23:47:18.89#ibcon#first serial, iclass 23, count 2 2006.285.23:47:18.89#ibcon#enter sib2, iclass 23, count 2 2006.285.23:47:18.89#ibcon#flushed, iclass 23, count 2 2006.285.23:47:18.89#ibcon#about to write, iclass 23, count 2 2006.285.23:47:18.89#ibcon#wrote, iclass 23, count 2 2006.285.23:47:18.89#ibcon#about to read 3, iclass 23, count 2 2006.285.23:47:18.91#ibcon#read 3, iclass 23, count 2 2006.285.23:47:18.91#ibcon#about to read 4, iclass 23, count 2 2006.285.23:47:18.91#ibcon#read 4, iclass 23, count 2 2006.285.23:47:18.91#ibcon#about to read 5, iclass 23, count 2 2006.285.23:47:18.91#ibcon#read 5, iclass 23, count 2 2006.285.23:47:18.91#ibcon#about to read 6, iclass 23, count 2 2006.285.23:47:18.91#ibcon#read 6, iclass 23, count 2 2006.285.23:47:18.91#ibcon#end of sib2, iclass 23, count 2 2006.285.23:47:18.91#ibcon#*mode == 0, iclass 23, count 2 2006.285.23:47:18.91#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.23:47:18.91#ibcon#[25=AT06-04\r\n] 2006.285.23:47:18.91#ibcon#*before write, iclass 23, count 2 2006.285.23:47:18.91#ibcon#enter sib2, iclass 23, count 2 2006.285.23:47:18.91#ibcon#flushed, iclass 23, count 2 2006.285.23:47:18.91#ibcon#about to write, iclass 23, count 2 2006.285.23:47:18.91#ibcon#wrote, iclass 23, count 2 2006.285.23:47:18.91#ibcon#about to read 3, iclass 23, count 2 2006.285.23:47:18.94#ibcon#read 3, iclass 23, count 2 2006.285.23:47:18.94#ibcon#about to read 4, iclass 23, count 2 2006.285.23:47:18.94#ibcon#read 4, iclass 23, count 2 2006.285.23:47:18.94#ibcon#about to read 5, iclass 23, count 2 2006.285.23:47:18.94#ibcon#read 5, iclass 23, count 2 2006.285.23:47:18.94#ibcon#about to read 6, iclass 23, count 2 2006.285.23:47:18.94#ibcon#read 6, iclass 23, count 2 2006.285.23:47:18.94#ibcon#end of sib2, iclass 23, count 2 2006.285.23:47:18.94#ibcon#*after write, iclass 23, count 2 2006.285.23:47:18.94#ibcon#*before return 0, iclass 23, count 2 2006.285.23:47:18.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:47:18.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:47:18.94#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.23:47:18.94#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:18.94#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:47:19.06#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:47:19.06#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:47:19.06#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:47:19.06#ibcon#first serial, iclass 23, count 0 2006.285.23:47:19.06#ibcon#enter sib2, iclass 23, count 0 2006.285.23:47:19.06#ibcon#flushed, iclass 23, count 0 2006.285.23:47:19.06#ibcon#about to write, iclass 23, count 0 2006.285.23:47:19.06#ibcon#wrote, iclass 23, count 0 2006.285.23:47:19.06#ibcon#about to read 3, iclass 23, count 0 2006.285.23:47:19.08#ibcon#read 3, iclass 23, count 0 2006.285.23:47:19.08#ibcon#about to read 4, iclass 23, count 0 2006.285.23:47:19.08#ibcon#read 4, iclass 23, count 0 2006.285.23:47:19.08#ibcon#about to read 5, iclass 23, count 0 2006.285.23:47:19.08#ibcon#read 5, iclass 23, count 0 2006.285.23:47:19.08#ibcon#about to read 6, iclass 23, count 0 2006.285.23:47:19.08#ibcon#read 6, iclass 23, count 0 2006.285.23:47:19.08#ibcon#end of sib2, iclass 23, count 0 2006.285.23:47:19.08#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:47:19.08#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:47:19.08#ibcon#[25=USB\r\n] 2006.285.23:47:19.08#ibcon#*before write, iclass 23, count 0 2006.285.23:47:19.08#ibcon#enter sib2, iclass 23, count 0 2006.285.23:47:19.08#ibcon#flushed, iclass 23, count 0 2006.285.23:47:19.08#ibcon#about to write, iclass 23, count 0 2006.285.23:47:19.08#ibcon#wrote, iclass 23, count 0 2006.285.23:47:19.08#ibcon#about to read 3, iclass 23, count 0 2006.285.23:47:19.11#ibcon#read 3, iclass 23, count 0 2006.285.23:47:19.11#ibcon#about to read 4, iclass 23, count 0 2006.285.23:47:19.11#ibcon#read 4, iclass 23, count 0 2006.285.23:47:19.11#ibcon#about to read 5, iclass 23, count 0 2006.285.23:47:19.11#ibcon#read 5, iclass 23, count 0 2006.285.23:47:19.11#ibcon#about to read 6, iclass 23, count 0 2006.285.23:47:19.11#ibcon#read 6, iclass 23, count 0 2006.285.23:47:19.11#ibcon#end of sib2, iclass 23, count 0 2006.285.23:47:19.11#ibcon#*after write, iclass 23, count 0 2006.285.23:47:19.11#ibcon#*before return 0, iclass 23, count 0 2006.285.23:47:19.11#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:47:19.11#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:47:19.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:47:19.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:47:19.11$vck44/valo=7,864.99 2006.285.23:47:19.11#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.285.23:47:19.11#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.285.23:47:19.11#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:19.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:47:19.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:47:19.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:47:19.11#ibcon#enter wrdev, iclass 26, count 0 2006.285.23:47:19.11#ibcon#first serial, iclass 26, count 0 2006.285.23:47:19.11#ibcon#enter sib2, iclass 26, count 0 2006.285.23:47:19.11#ibcon#flushed, iclass 26, count 0 2006.285.23:47:19.11#ibcon#about to write, iclass 26, count 0 2006.285.23:47:19.11#ibcon#wrote, iclass 26, count 0 2006.285.23:47:19.11#ibcon#about to read 3, iclass 26, count 0 2006.285.23:47:19.13#ibcon#read 3, iclass 26, count 0 2006.285.23:47:19.13#ibcon#about to read 4, iclass 26, count 0 2006.285.23:47:19.13#ibcon#read 4, iclass 26, count 0 2006.285.23:47:19.13#ibcon#about to read 5, iclass 26, count 0 2006.285.23:47:19.13#ibcon#read 5, iclass 26, count 0 2006.285.23:47:19.13#ibcon#about to read 6, iclass 26, count 0 2006.285.23:47:19.13#ibcon#read 6, iclass 26, count 0 2006.285.23:47:19.13#ibcon#end of sib2, iclass 26, count 0 2006.285.23:47:19.13#ibcon#*mode == 0, iclass 26, count 0 2006.285.23:47:19.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.23:47:19.13#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.23:47:19.13#ibcon#*before write, iclass 26, count 0 2006.285.23:47:19.13#ibcon#enter sib2, iclass 26, count 0 2006.285.23:47:19.13#ibcon#flushed, iclass 26, count 0 2006.285.23:47:19.13#ibcon#about to write, iclass 26, count 0 2006.285.23:47:19.13#ibcon#wrote, iclass 26, count 0 2006.285.23:47:19.13#ibcon#about to read 3, iclass 26, count 0 2006.285.23:47:19.13#abcon#<5=/03 3.8 8.1 19.52 871016.5\r\n> 2006.285.23:47:19.15#abcon#{5=INTERFACE CLEAR} 2006.285.23:47:19.17#ibcon#read 3, iclass 26, count 0 2006.285.23:47:19.17#ibcon#about to read 4, iclass 26, count 0 2006.285.23:47:19.17#ibcon#read 4, iclass 26, count 0 2006.285.23:47:19.17#ibcon#about to read 5, iclass 26, count 0 2006.285.23:47:19.17#ibcon#read 5, iclass 26, count 0 2006.285.23:47:19.17#ibcon#about to read 6, iclass 26, count 0 2006.285.23:47:19.17#ibcon#read 6, iclass 26, count 0 2006.285.23:47:19.17#ibcon#end of sib2, iclass 26, count 0 2006.285.23:47:19.17#ibcon#*after write, iclass 26, count 0 2006.285.23:47:19.17#ibcon#*before return 0, iclass 26, count 0 2006.285.23:47:19.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:47:19.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.285.23:47:19.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.23:47:19.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.23:47:19.17$vck44/va=7,4 2006.285.23:47:19.17#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.23:47:19.17#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.23:47:19.17#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:19.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:47:19.21#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:47:19.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:47:19.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:47:19.23#ibcon#enter wrdev, iclass 30, count 2 2006.285.23:47:19.23#ibcon#first serial, iclass 30, count 2 2006.285.23:47:19.23#ibcon#enter sib2, iclass 30, count 2 2006.285.23:47:19.23#ibcon#flushed, iclass 30, count 2 2006.285.23:47:19.23#ibcon#about to write, iclass 30, count 2 2006.285.23:47:19.23#ibcon#wrote, iclass 30, count 2 2006.285.23:47:19.23#ibcon#about to read 3, iclass 30, count 2 2006.285.23:47:19.25#ibcon#read 3, iclass 30, count 2 2006.285.23:47:19.25#ibcon#about to read 4, iclass 30, count 2 2006.285.23:47:19.25#ibcon#read 4, iclass 30, count 2 2006.285.23:47:19.25#ibcon#about to read 5, iclass 30, count 2 2006.285.23:47:19.25#ibcon#read 5, iclass 30, count 2 2006.285.23:47:19.25#ibcon#about to read 6, iclass 30, count 2 2006.285.23:47:19.25#ibcon#read 6, iclass 30, count 2 2006.285.23:47:19.25#ibcon#end of sib2, iclass 30, count 2 2006.285.23:47:19.25#ibcon#*mode == 0, iclass 30, count 2 2006.285.23:47:19.25#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.23:47:19.25#ibcon#[25=AT07-04\r\n] 2006.285.23:47:19.25#ibcon#*before write, iclass 30, count 2 2006.285.23:47:19.25#ibcon#enter sib2, iclass 30, count 2 2006.285.23:47:19.25#ibcon#flushed, iclass 30, count 2 2006.285.23:47:19.25#ibcon#about to write, iclass 30, count 2 2006.285.23:47:19.25#ibcon#wrote, iclass 30, count 2 2006.285.23:47:19.25#ibcon#about to read 3, iclass 30, count 2 2006.285.23:47:19.28#ibcon#read 3, iclass 30, count 2 2006.285.23:47:19.28#ibcon#about to read 4, iclass 30, count 2 2006.285.23:47:19.28#ibcon#read 4, iclass 30, count 2 2006.285.23:47:19.28#ibcon#about to read 5, iclass 30, count 2 2006.285.23:47:19.28#ibcon#read 5, iclass 30, count 2 2006.285.23:47:19.28#ibcon#about to read 6, iclass 30, count 2 2006.285.23:47:19.28#ibcon#read 6, iclass 30, count 2 2006.285.23:47:19.28#ibcon#end of sib2, iclass 30, count 2 2006.285.23:47:19.28#ibcon#*after write, iclass 30, count 2 2006.285.23:47:19.28#ibcon#*before return 0, iclass 30, count 2 2006.285.23:47:19.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:47:19.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:47:19.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.23:47:19.28#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:19.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:47:19.40#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:47:19.40#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:47:19.40#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:47:19.40#ibcon#first serial, iclass 30, count 0 2006.285.23:47:19.40#ibcon#enter sib2, iclass 30, count 0 2006.285.23:47:19.40#ibcon#flushed, iclass 30, count 0 2006.285.23:47:19.40#ibcon#about to write, iclass 30, count 0 2006.285.23:47:19.40#ibcon#wrote, iclass 30, count 0 2006.285.23:47:19.40#ibcon#about to read 3, iclass 30, count 0 2006.285.23:47:19.42#ibcon#read 3, iclass 30, count 0 2006.285.23:47:19.42#ibcon#about to read 4, iclass 30, count 0 2006.285.23:47:19.42#ibcon#read 4, iclass 30, count 0 2006.285.23:47:19.42#ibcon#about to read 5, iclass 30, count 0 2006.285.23:47:19.42#ibcon#read 5, iclass 30, count 0 2006.285.23:47:19.42#ibcon#about to read 6, iclass 30, count 0 2006.285.23:47:19.42#ibcon#read 6, iclass 30, count 0 2006.285.23:47:19.42#ibcon#end of sib2, iclass 30, count 0 2006.285.23:47:19.42#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:47:19.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:47:19.42#ibcon#[25=USB\r\n] 2006.285.23:47:19.42#ibcon#*before write, iclass 30, count 0 2006.285.23:47:19.42#ibcon#enter sib2, iclass 30, count 0 2006.285.23:47:19.42#ibcon#flushed, iclass 30, count 0 2006.285.23:47:19.42#ibcon#about to write, iclass 30, count 0 2006.285.23:47:19.42#ibcon#wrote, iclass 30, count 0 2006.285.23:47:19.42#ibcon#about to read 3, iclass 30, count 0 2006.285.23:47:19.45#ibcon#read 3, iclass 30, count 0 2006.285.23:47:19.45#ibcon#about to read 4, iclass 30, count 0 2006.285.23:47:19.45#ibcon#read 4, iclass 30, count 0 2006.285.23:47:19.45#ibcon#about to read 5, iclass 30, count 0 2006.285.23:47:19.45#ibcon#read 5, iclass 30, count 0 2006.285.23:47:19.45#ibcon#about to read 6, iclass 30, count 0 2006.285.23:47:19.45#ibcon#read 6, iclass 30, count 0 2006.285.23:47:19.45#ibcon#end of sib2, iclass 30, count 0 2006.285.23:47:19.45#ibcon#*after write, iclass 30, count 0 2006.285.23:47:19.45#ibcon#*before return 0, iclass 30, count 0 2006.285.23:47:19.45#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:47:19.45#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:47:19.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:47:19.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:47:19.45$vck44/valo=8,884.99 2006.285.23:47:19.45#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.23:47:19.45#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.23:47:19.45#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:19.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:47:19.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:47:19.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:47:19.45#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:47:19.45#ibcon#first serial, iclass 33, count 0 2006.285.23:47:19.45#ibcon#enter sib2, iclass 33, count 0 2006.285.23:47:19.45#ibcon#flushed, iclass 33, count 0 2006.285.23:47:19.45#ibcon#about to write, iclass 33, count 0 2006.285.23:47:19.45#ibcon#wrote, iclass 33, count 0 2006.285.23:47:19.45#ibcon#about to read 3, iclass 33, count 0 2006.285.23:47:19.47#ibcon#read 3, iclass 33, count 0 2006.285.23:47:19.47#ibcon#about to read 4, iclass 33, count 0 2006.285.23:47:19.47#ibcon#read 4, iclass 33, count 0 2006.285.23:47:19.47#ibcon#about to read 5, iclass 33, count 0 2006.285.23:47:19.47#ibcon#read 5, iclass 33, count 0 2006.285.23:47:19.47#ibcon#about to read 6, iclass 33, count 0 2006.285.23:47:19.47#ibcon#read 6, iclass 33, count 0 2006.285.23:47:19.47#ibcon#end of sib2, iclass 33, count 0 2006.285.23:47:19.47#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:47:19.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:47:19.47#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.23:47:19.47#ibcon#*before write, iclass 33, count 0 2006.285.23:47:19.47#ibcon#enter sib2, iclass 33, count 0 2006.285.23:47:19.47#ibcon#flushed, iclass 33, count 0 2006.285.23:47:19.47#ibcon#about to write, iclass 33, count 0 2006.285.23:47:19.47#ibcon#wrote, iclass 33, count 0 2006.285.23:47:19.47#ibcon#about to read 3, iclass 33, count 0 2006.285.23:47:19.51#ibcon#read 3, iclass 33, count 0 2006.285.23:47:19.51#ibcon#about to read 4, iclass 33, count 0 2006.285.23:47:19.51#ibcon#read 4, iclass 33, count 0 2006.285.23:47:19.51#ibcon#about to read 5, iclass 33, count 0 2006.285.23:47:19.51#ibcon#read 5, iclass 33, count 0 2006.285.23:47:19.51#ibcon#about to read 6, iclass 33, count 0 2006.285.23:47:19.51#ibcon#read 6, iclass 33, count 0 2006.285.23:47:19.51#ibcon#end of sib2, iclass 33, count 0 2006.285.23:47:19.51#ibcon#*after write, iclass 33, count 0 2006.285.23:47:19.51#ibcon#*before return 0, iclass 33, count 0 2006.285.23:47:19.51#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:47:19.51#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:47:19.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:47:19.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:47:19.51$vck44/va=8,3 2006.285.23:47:19.51#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.285.23:47:19.51#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.285.23:47:19.51#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:19.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.23:47:19.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.285.23:47:19.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.23:47:19.57#ibcon#enter wrdev, iclass 35, count 2 2006.285.23:47:19.57#ibcon#first serial, iclass 35, count 2 2006.285.23:47:19.57#ibcon#enter sib2, iclass 35, count 2 2006.285.23:47:19.57#ibcon#flushed, iclass 35, count 2 2006.285.23:47:19.57#ibcon#about to write, iclass 35, count 2 2006.285.23:47:19.57#ibcon#wrote, iclass 35, count 2 2006.285.23:47:19.57#ibcon#about to read 3, iclass 35, count 2 2006.285.23:47:19.59#ibcon#read 3, iclass 35, count 2 2006.285.23:47:19.59#ibcon#about to read 4, iclass 35, count 2 2006.285.23:47:19.59#ibcon#read 4, iclass 35, count 2 2006.285.23:47:19.59#ibcon#about to read 5, iclass 35, count 2 2006.285.23:47:19.59#ibcon#read 5, iclass 35, count 2 2006.285.23:47:19.59#ibcon#about to read 6, iclass 35, count 2 2006.285.23:47:19.59#ibcon#read 6, iclass 35, count 2 2006.285.23:47:19.59#ibcon#end of sib2, iclass 35, count 2 2006.285.23:47:19.59#ibcon#*mode == 0, iclass 35, count 2 2006.285.23:47:19.59#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.285.23:47:19.59#ibcon#[25=AT08-03\r\n] 2006.285.23:47:19.59#ibcon#*before write, iclass 35, count 2 2006.285.23:47:19.59#ibcon#enter sib2, iclass 35, count 2 2006.285.23:47:19.59#ibcon#flushed, iclass 35, count 2 2006.285.23:47:19.59#ibcon#about to write, iclass 35, count 2 2006.285.23:47:19.59#ibcon#wrote, iclass 35, count 2 2006.285.23:47:19.59#ibcon#about to read 3, iclass 35, count 2 2006.285.23:47:19.62#ibcon#read 3, iclass 35, count 2 2006.285.23:47:19.62#ibcon#about to read 4, iclass 35, count 2 2006.285.23:47:19.62#ibcon#read 4, iclass 35, count 2 2006.285.23:47:19.62#ibcon#about to read 5, iclass 35, count 2 2006.285.23:47:19.62#ibcon#read 5, iclass 35, count 2 2006.285.23:47:19.62#ibcon#about to read 6, iclass 35, count 2 2006.285.23:47:19.62#ibcon#read 6, iclass 35, count 2 2006.285.23:47:19.62#ibcon#end of sib2, iclass 35, count 2 2006.285.23:47:19.62#ibcon#*after write, iclass 35, count 2 2006.285.23:47:19.62#ibcon#*before return 0, iclass 35, count 2 2006.285.23:47:19.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.285.23:47:19.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.285.23:47:19.62#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.285.23:47:19.62#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:19.62#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.23:47:19.74#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.285.23:47:19.74#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.23:47:19.74#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:47:19.74#ibcon#first serial, iclass 35, count 0 2006.285.23:47:19.74#ibcon#enter sib2, iclass 35, count 0 2006.285.23:47:19.74#ibcon#flushed, iclass 35, count 0 2006.285.23:47:19.74#ibcon#about to write, iclass 35, count 0 2006.285.23:47:19.74#ibcon#wrote, iclass 35, count 0 2006.285.23:47:19.74#ibcon#about to read 3, iclass 35, count 0 2006.285.23:47:19.76#ibcon#read 3, iclass 35, count 0 2006.285.23:47:19.76#ibcon#about to read 4, iclass 35, count 0 2006.285.23:47:19.76#ibcon#read 4, iclass 35, count 0 2006.285.23:47:19.76#ibcon#about to read 5, iclass 35, count 0 2006.285.23:47:19.76#ibcon#read 5, iclass 35, count 0 2006.285.23:47:19.76#ibcon#about to read 6, iclass 35, count 0 2006.285.23:47:19.76#ibcon#read 6, iclass 35, count 0 2006.285.23:47:19.76#ibcon#end of sib2, iclass 35, count 0 2006.285.23:47:19.76#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:47:19.76#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:47:19.76#ibcon#[25=USB\r\n] 2006.285.23:47:19.76#ibcon#*before write, iclass 35, count 0 2006.285.23:47:19.76#ibcon#enter sib2, iclass 35, count 0 2006.285.23:47:19.76#ibcon#flushed, iclass 35, count 0 2006.285.23:47:19.76#ibcon#about to write, iclass 35, count 0 2006.285.23:47:19.76#ibcon#wrote, iclass 35, count 0 2006.285.23:47:19.76#ibcon#about to read 3, iclass 35, count 0 2006.285.23:47:19.79#ibcon#read 3, iclass 35, count 0 2006.285.23:47:19.79#ibcon#about to read 4, iclass 35, count 0 2006.285.23:47:19.79#ibcon#read 4, iclass 35, count 0 2006.285.23:47:19.79#ibcon#about to read 5, iclass 35, count 0 2006.285.23:47:19.79#ibcon#read 5, iclass 35, count 0 2006.285.23:47:19.79#ibcon#about to read 6, iclass 35, count 0 2006.285.23:47:19.79#ibcon#read 6, iclass 35, count 0 2006.285.23:47:19.79#ibcon#end of sib2, iclass 35, count 0 2006.285.23:47:19.79#ibcon#*after write, iclass 35, count 0 2006.285.23:47:19.79#ibcon#*before return 0, iclass 35, count 0 2006.285.23:47:19.79#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.285.23:47:19.79#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.285.23:47:19.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:47:19.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:47:19.79$vck44/vblo=1,629.99 2006.285.23:47:19.79#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.285.23:47:19.79#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.285.23:47:19.79#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:19.79#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:47:19.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:47:19.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:47:19.79#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:47:19.79#ibcon#first serial, iclass 37, count 0 2006.285.23:47:19.79#ibcon#enter sib2, iclass 37, count 0 2006.285.23:47:19.79#ibcon#flushed, iclass 37, count 0 2006.285.23:47:19.79#ibcon#about to write, iclass 37, count 0 2006.285.23:47:19.79#ibcon#wrote, iclass 37, count 0 2006.285.23:47:19.79#ibcon#about to read 3, iclass 37, count 0 2006.285.23:47:19.81#ibcon#read 3, iclass 37, count 0 2006.285.23:47:19.81#ibcon#about to read 4, iclass 37, count 0 2006.285.23:47:19.81#ibcon#read 4, iclass 37, count 0 2006.285.23:47:19.81#ibcon#about to read 5, iclass 37, count 0 2006.285.23:47:19.81#ibcon#read 5, iclass 37, count 0 2006.285.23:47:19.81#ibcon#about to read 6, iclass 37, count 0 2006.285.23:47:19.81#ibcon#read 6, iclass 37, count 0 2006.285.23:47:19.81#ibcon#end of sib2, iclass 37, count 0 2006.285.23:47:19.81#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:47:19.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:47:19.81#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.23:47:19.81#ibcon#*before write, iclass 37, count 0 2006.285.23:47:19.81#ibcon#enter sib2, iclass 37, count 0 2006.285.23:47:19.81#ibcon#flushed, iclass 37, count 0 2006.285.23:47:19.81#ibcon#about to write, iclass 37, count 0 2006.285.23:47:19.81#ibcon#wrote, iclass 37, count 0 2006.285.23:47:19.81#ibcon#about to read 3, iclass 37, count 0 2006.285.23:47:19.85#ibcon#read 3, iclass 37, count 0 2006.285.23:47:19.85#ibcon#about to read 4, iclass 37, count 0 2006.285.23:47:19.85#ibcon#read 4, iclass 37, count 0 2006.285.23:47:19.85#ibcon#about to read 5, iclass 37, count 0 2006.285.23:47:19.85#ibcon#read 5, iclass 37, count 0 2006.285.23:47:19.85#ibcon#about to read 6, iclass 37, count 0 2006.285.23:47:19.85#ibcon#read 6, iclass 37, count 0 2006.285.23:47:19.85#ibcon#end of sib2, iclass 37, count 0 2006.285.23:47:19.85#ibcon#*after write, iclass 37, count 0 2006.285.23:47:19.85#ibcon#*before return 0, iclass 37, count 0 2006.285.23:47:19.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:47:19.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.285.23:47:19.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:47:19.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:47:19.85$vck44/vb=1,4 2006.285.23:47:19.85#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.285.23:47:19.85#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.285.23:47:19.85#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:19.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:47:19.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:47:19.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:47:19.85#ibcon#enter wrdev, iclass 39, count 2 2006.285.23:47:19.85#ibcon#first serial, iclass 39, count 2 2006.285.23:47:19.85#ibcon#enter sib2, iclass 39, count 2 2006.285.23:47:19.85#ibcon#flushed, iclass 39, count 2 2006.285.23:47:19.85#ibcon#about to write, iclass 39, count 2 2006.285.23:47:19.85#ibcon#wrote, iclass 39, count 2 2006.285.23:47:19.85#ibcon#about to read 3, iclass 39, count 2 2006.285.23:47:19.87#ibcon#read 3, iclass 39, count 2 2006.285.23:47:19.87#ibcon#about to read 4, iclass 39, count 2 2006.285.23:47:19.87#ibcon#read 4, iclass 39, count 2 2006.285.23:47:19.87#ibcon#about to read 5, iclass 39, count 2 2006.285.23:47:19.87#ibcon#read 5, iclass 39, count 2 2006.285.23:47:19.87#ibcon#about to read 6, iclass 39, count 2 2006.285.23:47:19.87#ibcon#read 6, iclass 39, count 2 2006.285.23:47:19.87#ibcon#end of sib2, iclass 39, count 2 2006.285.23:47:19.87#ibcon#*mode == 0, iclass 39, count 2 2006.285.23:47:19.87#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.285.23:47:19.87#ibcon#[27=AT01-04\r\n] 2006.285.23:47:19.87#ibcon#*before write, iclass 39, count 2 2006.285.23:47:19.87#ibcon#enter sib2, iclass 39, count 2 2006.285.23:47:19.87#ibcon#flushed, iclass 39, count 2 2006.285.23:47:19.87#ibcon#about to write, iclass 39, count 2 2006.285.23:47:19.87#ibcon#wrote, iclass 39, count 2 2006.285.23:47:19.87#ibcon#about to read 3, iclass 39, count 2 2006.285.23:47:19.90#ibcon#read 3, iclass 39, count 2 2006.285.23:47:19.90#ibcon#about to read 4, iclass 39, count 2 2006.285.23:47:19.90#ibcon#read 4, iclass 39, count 2 2006.285.23:47:19.90#ibcon#about to read 5, iclass 39, count 2 2006.285.23:47:19.90#ibcon#read 5, iclass 39, count 2 2006.285.23:47:19.90#ibcon#about to read 6, iclass 39, count 2 2006.285.23:47:19.90#ibcon#read 6, iclass 39, count 2 2006.285.23:47:19.90#ibcon#end of sib2, iclass 39, count 2 2006.285.23:47:19.90#ibcon#*after write, iclass 39, count 2 2006.285.23:47:19.90#ibcon#*before return 0, iclass 39, count 2 2006.285.23:47:19.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:47:19.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.285.23:47:19.90#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.285.23:47:19.90#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:19.90#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:47:20.02#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:47:20.02#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:47:20.02#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:47:20.02#ibcon#first serial, iclass 39, count 0 2006.285.23:47:20.02#ibcon#enter sib2, iclass 39, count 0 2006.285.23:47:20.02#ibcon#flushed, iclass 39, count 0 2006.285.23:47:20.02#ibcon#about to write, iclass 39, count 0 2006.285.23:47:20.02#ibcon#wrote, iclass 39, count 0 2006.285.23:47:20.02#ibcon#about to read 3, iclass 39, count 0 2006.285.23:47:20.04#ibcon#read 3, iclass 39, count 0 2006.285.23:47:20.04#ibcon#about to read 4, iclass 39, count 0 2006.285.23:47:20.04#ibcon#read 4, iclass 39, count 0 2006.285.23:47:20.04#ibcon#about to read 5, iclass 39, count 0 2006.285.23:47:20.04#ibcon#read 5, iclass 39, count 0 2006.285.23:47:20.04#ibcon#about to read 6, iclass 39, count 0 2006.285.23:47:20.04#ibcon#read 6, iclass 39, count 0 2006.285.23:47:20.04#ibcon#end of sib2, iclass 39, count 0 2006.285.23:47:20.04#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:47:20.04#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:47:20.04#ibcon#[27=USB\r\n] 2006.285.23:47:20.04#ibcon#*before write, iclass 39, count 0 2006.285.23:47:20.04#ibcon#enter sib2, iclass 39, count 0 2006.285.23:47:20.04#ibcon#flushed, iclass 39, count 0 2006.285.23:47:20.04#ibcon#about to write, iclass 39, count 0 2006.285.23:47:20.04#ibcon#wrote, iclass 39, count 0 2006.285.23:47:20.04#ibcon#about to read 3, iclass 39, count 0 2006.285.23:47:20.07#ibcon#read 3, iclass 39, count 0 2006.285.23:47:20.07#ibcon#about to read 4, iclass 39, count 0 2006.285.23:47:20.07#ibcon#read 4, iclass 39, count 0 2006.285.23:47:20.07#ibcon#about to read 5, iclass 39, count 0 2006.285.23:47:20.07#ibcon#read 5, iclass 39, count 0 2006.285.23:47:20.07#ibcon#about to read 6, iclass 39, count 0 2006.285.23:47:20.07#ibcon#read 6, iclass 39, count 0 2006.285.23:47:20.07#ibcon#end of sib2, iclass 39, count 0 2006.285.23:47:20.07#ibcon#*after write, iclass 39, count 0 2006.285.23:47:20.07#ibcon#*before return 0, iclass 39, count 0 2006.285.23:47:20.07#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:47:20.07#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.285.23:47:20.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:47:20.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:47:20.07$vck44/vblo=2,634.99 2006.285.23:47:20.07#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.285.23:47:20.07#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.285.23:47:20.07#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:20.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:47:20.07#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:47:20.07#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:47:20.07#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:47:20.07#ibcon#first serial, iclass 3, count 0 2006.285.23:47:20.07#ibcon#enter sib2, iclass 3, count 0 2006.285.23:47:20.07#ibcon#flushed, iclass 3, count 0 2006.285.23:47:20.07#ibcon#about to write, iclass 3, count 0 2006.285.23:47:20.07#ibcon#wrote, iclass 3, count 0 2006.285.23:47:20.07#ibcon#about to read 3, iclass 3, count 0 2006.285.23:47:20.09#ibcon#read 3, iclass 3, count 0 2006.285.23:47:20.09#ibcon#about to read 4, iclass 3, count 0 2006.285.23:47:20.09#ibcon#read 4, iclass 3, count 0 2006.285.23:47:20.09#ibcon#about to read 5, iclass 3, count 0 2006.285.23:47:20.09#ibcon#read 5, iclass 3, count 0 2006.285.23:47:20.09#ibcon#about to read 6, iclass 3, count 0 2006.285.23:47:20.09#ibcon#read 6, iclass 3, count 0 2006.285.23:47:20.09#ibcon#end of sib2, iclass 3, count 0 2006.285.23:47:20.09#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:47:20.09#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:47:20.09#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.23:47:20.09#ibcon#*before write, iclass 3, count 0 2006.285.23:47:20.09#ibcon#enter sib2, iclass 3, count 0 2006.285.23:47:20.09#ibcon#flushed, iclass 3, count 0 2006.285.23:47:20.09#ibcon#about to write, iclass 3, count 0 2006.285.23:47:20.09#ibcon#wrote, iclass 3, count 0 2006.285.23:47:20.09#ibcon#about to read 3, iclass 3, count 0 2006.285.23:47:20.13#ibcon#read 3, iclass 3, count 0 2006.285.23:47:20.13#ibcon#about to read 4, iclass 3, count 0 2006.285.23:47:20.13#ibcon#read 4, iclass 3, count 0 2006.285.23:47:20.13#ibcon#about to read 5, iclass 3, count 0 2006.285.23:47:20.13#ibcon#read 5, iclass 3, count 0 2006.285.23:47:20.13#ibcon#about to read 6, iclass 3, count 0 2006.285.23:47:20.13#ibcon#read 6, iclass 3, count 0 2006.285.23:47:20.13#ibcon#end of sib2, iclass 3, count 0 2006.285.23:47:20.13#ibcon#*after write, iclass 3, count 0 2006.285.23:47:20.13#ibcon#*before return 0, iclass 3, count 0 2006.285.23:47:20.13#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:47:20.13#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.285.23:47:20.13#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:47:20.13#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:47:20.13$vck44/vb=2,5 2006.285.23:47:20.13#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.285.23:47:20.13#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.285.23:47:20.13#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:20.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:47:20.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:47:20.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:47:20.19#ibcon#enter wrdev, iclass 5, count 2 2006.285.23:47:20.19#ibcon#first serial, iclass 5, count 2 2006.285.23:47:20.19#ibcon#enter sib2, iclass 5, count 2 2006.285.23:47:20.19#ibcon#flushed, iclass 5, count 2 2006.285.23:47:20.19#ibcon#about to write, iclass 5, count 2 2006.285.23:47:20.19#ibcon#wrote, iclass 5, count 2 2006.285.23:47:20.19#ibcon#about to read 3, iclass 5, count 2 2006.285.23:47:20.21#ibcon#read 3, iclass 5, count 2 2006.285.23:47:20.21#ibcon#about to read 4, iclass 5, count 2 2006.285.23:47:20.21#ibcon#read 4, iclass 5, count 2 2006.285.23:47:20.21#ibcon#about to read 5, iclass 5, count 2 2006.285.23:47:20.21#ibcon#read 5, iclass 5, count 2 2006.285.23:47:20.21#ibcon#about to read 6, iclass 5, count 2 2006.285.23:47:20.21#ibcon#read 6, iclass 5, count 2 2006.285.23:47:20.21#ibcon#end of sib2, iclass 5, count 2 2006.285.23:47:20.21#ibcon#*mode == 0, iclass 5, count 2 2006.285.23:47:20.21#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.285.23:47:20.21#ibcon#[27=AT02-05\r\n] 2006.285.23:47:20.21#ibcon#*before write, iclass 5, count 2 2006.285.23:47:20.21#ibcon#enter sib2, iclass 5, count 2 2006.285.23:47:20.21#ibcon#flushed, iclass 5, count 2 2006.285.23:47:20.21#ibcon#about to write, iclass 5, count 2 2006.285.23:47:20.21#ibcon#wrote, iclass 5, count 2 2006.285.23:47:20.21#ibcon#about to read 3, iclass 5, count 2 2006.285.23:47:20.24#ibcon#read 3, iclass 5, count 2 2006.285.23:47:20.24#ibcon#about to read 4, iclass 5, count 2 2006.285.23:47:20.24#ibcon#read 4, iclass 5, count 2 2006.285.23:47:20.24#ibcon#about to read 5, iclass 5, count 2 2006.285.23:47:20.24#ibcon#read 5, iclass 5, count 2 2006.285.23:47:20.24#ibcon#about to read 6, iclass 5, count 2 2006.285.23:47:20.24#ibcon#read 6, iclass 5, count 2 2006.285.23:47:20.24#ibcon#end of sib2, iclass 5, count 2 2006.285.23:47:20.24#ibcon#*after write, iclass 5, count 2 2006.285.23:47:20.24#ibcon#*before return 0, iclass 5, count 2 2006.285.23:47:20.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:47:20.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.285.23:47:20.24#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.285.23:47:20.24#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:20.24#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:47:20.36#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:47:20.36#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:47:20.36#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:47:20.36#ibcon#first serial, iclass 5, count 0 2006.285.23:47:20.36#ibcon#enter sib2, iclass 5, count 0 2006.285.23:47:20.36#ibcon#flushed, iclass 5, count 0 2006.285.23:47:20.36#ibcon#about to write, iclass 5, count 0 2006.285.23:47:20.36#ibcon#wrote, iclass 5, count 0 2006.285.23:47:20.36#ibcon#about to read 3, iclass 5, count 0 2006.285.23:47:20.38#ibcon#read 3, iclass 5, count 0 2006.285.23:47:20.38#ibcon#about to read 4, iclass 5, count 0 2006.285.23:47:20.38#ibcon#read 4, iclass 5, count 0 2006.285.23:47:20.38#ibcon#about to read 5, iclass 5, count 0 2006.285.23:47:20.38#ibcon#read 5, iclass 5, count 0 2006.285.23:47:20.38#ibcon#about to read 6, iclass 5, count 0 2006.285.23:47:20.38#ibcon#read 6, iclass 5, count 0 2006.285.23:47:20.38#ibcon#end of sib2, iclass 5, count 0 2006.285.23:47:20.38#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:47:20.38#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:47:20.38#ibcon#[27=USB\r\n] 2006.285.23:47:20.38#ibcon#*before write, iclass 5, count 0 2006.285.23:47:20.38#ibcon#enter sib2, iclass 5, count 0 2006.285.23:47:20.38#ibcon#flushed, iclass 5, count 0 2006.285.23:47:20.38#ibcon#about to write, iclass 5, count 0 2006.285.23:47:20.38#ibcon#wrote, iclass 5, count 0 2006.285.23:47:20.38#ibcon#about to read 3, iclass 5, count 0 2006.285.23:47:20.41#ibcon#read 3, iclass 5, count 0 2006.285.23:47:20.41#ibcon#about to read 4, iclass 5, count 0 2006.285.23:47:20.41#ibcon#read 4, iclass 5, count 0 2006.285.23:47:20.41#ibcon#about to read 5, iclass 5, count 0 2006.285.23:47:20.41#ibcon#read 5, iclass 5, count 0 2006.285.23:47:20.41#ibcon#about to read 6, iclass 5, count 0 2006.285.23:47:20.41#ibcon#read 6, iclass 5, count 0 2006.285.23:47:20.41#ibcon#end of sib2, iclass 5, count 0 2006.285.23:47:20.41#ibcon#*after write, iclass 5, count 0 2006.285.23:47:20.41#ibcon#*before return 0, iclass 5, count 0 2006.285.23:47:20.41#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:47:20.41#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.285.23:47:20.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:47:20.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:47:20.41$vck44/vblo=3,649.99 2006.285.23:47:20.41#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.285.23:47:20.41#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.285.23:47:20.41#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:20.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:47:20.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:47:20.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:47:20.41#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:47:20.41#ibcon#first serial, iclass 7, count 0 2006.285.23:47:20.41#ibcon#enter sib2, iclass 7, count 0 2006.285.23:47:20.41#ibcon#flushed, iclass 7, count 0 2006.285.23:47:20.41#ibcon#about to write, iclass 7, count 0 2006.285.23:47:20.41#ibcon#wrote, iclass 7, count 0 2006.285.23:47:20.41#ibcon#about to read 3, iclass 7, count 0 2006.285.23:47:20.43#ibcon#read 3, iclass 7, count 0 2006.285.23:47:20.43#ibcon#about to read 4, iclass 7, count 0 2006.285.23:47:20.43#ibcon#read 4, iclass 7, count 0 2006.285.23:47:20.43#ibcon#about to read 5, iclass 7, count 0 2006.285.23:47:20.43#ibcon#read 5, iclass 7, count 0 2006.285.23:47:20.43#ibcon#about to read 6, iclass 7, count 0 2006.285.23:47:20.43#ibcon#read 6, iclass 7, count 0 2006.285.23:47:20.43#ibcon#end of sib2, iclass 7, count 0 2006.285.23:47:20.43#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:47:20.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:47:20.43#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.23:47:20.43#ibcon#*before write, iclass 7, count 0 2006.285.23:47:20.43#ibcon#enter sib2, iclass 7, count 0 2006.285.23:47:20.43#ibcon#flushed, iclass 7, count 0 2006.285.23:47:20.43#ibcon#about to write, iclass 7, count 0 2006.285.23:47:20.43#ibcon#wrote, iclass 7, count 0 2006.285.23:47:20.43#ibcon#about to read 3, iclass 7, count 0 2006.285.23:47:20.47#ibcon#read 3, iclass 7, count 0 2006.285.23:47:20.47#ibcon#about to read 4, iclass 7, count 0 2006.285.23:47:20.47#ibcon#read 4, iclass 7, count 0 2006.285.23:47:20.47#ibcon#about to read 5, iclass 7, count 0 2006.285.23:47:20.47#ibcon#read 5, iclass 7, count 0 2006.285.23:47:20.47#ibcon#about to read 6, iclass 7, count 0 2006.285.23:47:20.47#ibcon#read 6, iclass 7, count 0 2006.285.23:47:20.47#ibcon#end of sib2, iclass 7, count 0 2006.285.23:47:20.47#ibcon#*after write, iclass 7, count 0 2006.285.23:47:20.47#ibcon#*before return 0, iclass 7, count 0 2006.285.23:47:20.47#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:47:20.47#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.285.23:47:20.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:47:20.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:47:20.47$vck44/vb=3,4 2006.285.23:47:20.47#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.23:47:20.47#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.23:47:20.47#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:20.47#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:47:20.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:47:20.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:47:20.53#ibcon#enter wrdev, iclass 11, count 2 2006.285.23:47:20.53#ibcon#first serial, iclass 11, count 2 2006.285.23:47:20.53#ibcon#enter sib2, iclass 11, count 2 2006.285.23:47:20.53#ibcon#flushed, iclass 11, count 2 2006.285.23:47:20.53#ibcon#about to write, iclass 11, count 2 2006.285.23:47:20.53#ibcon#wrote, iclass 11, count 2 2006.285.23:47:20.53#ibcon#about to read 3, iclass 11, count 2 2006.285.23:47:20.55#ibcon#read 3, iclass 11, count 2 2006.285.23:47:20.55#ibcon#about to read 4, iclass 11, count 2 2006.285.23:47:20.55#ibcon#read 4, iclass 11, count 2 2006.285.23:47:20.55#ibcon#about to read 5, iclass 11, count 2 2006.285.23:47:20.55#ibcon#read 5, iclass 11, count 2 2006.285.23:47:20.55#ibcon#about to read 6, iclass 11, count 2 2006.285.23:47:20.55#ibcon#read 6, iclass 11, count 2 2006.285.23:47:20.55#ibcon#end of sib2, iclass 11, count 2 2006.285.23:47:20.55#ibcon#*mode == 0, iclass 11, count 2 2006.285.23:47:20.55#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.23:47:20.55#ibcon#[27=AT03-04\r\n] 2006.285.23:47:20.55#ibcon#*before write, iclass 11, count 2 2006.285.23:47:20.55#ibcon#enter sib2, iclass 11, count 2 2006.285.23:47:20.55#ibcon#flushed, iclass 11, count 2 2006.285.23:47:20.55#ibcon#about to write, iclass 11, count 2 2006.285.23:47:20.55#ibcon#wrote, iclass 11, count 2 2006.285.23:47:20.55#ibcon#about to read 3, iclass 11, count 2 2006.285.23:47:20.58#ibcon#read 3, iclass 11, count 2 2006.285.23:47:20.58#ibcon#about to read 4, iclass 11, count 2 2006.285.23:47:20.58#ibcon#read 4, iclass 11, count 2 2006.285.23:47:20.58#ibcon#about to read 5, iclass 11, count 2 2006.285.23:47:20.58#ibcon#read 5, iclass 11, count 2 2006.285.23:47:20.58#ibcon#about to read 6, iclass 11, count 2 2006.285.23:47:20.58#ibcon#read 6, iclass 11, count 2 2006.285.23:47:20.58#ibcon#end of sib2, iclass 11, count 2 2006.285.23:47:20.58#ibcon#*after write, iclass 11, count 2 2006.285.23:47:20.58#ibcon#*before return 0, iclass 11, count 2 2006.285.23:47:20.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:47:20.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:47:20.58#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.23:47:20.58#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:20.58#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:47:20.70#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:47:20.70#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:47:20.70#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:47:20.70#ibcon#first serial, iclass 11, count 0 2006.285.23:47:20.70#ibcon#enter sib2, iclass 11, count 0 2006.285.23:47:20.70#ibcon#flushed, iclass 11, count 0 2006.285.23:47:20.70#ibcon#about to write, iclass 11, count 0 2006.285.23:47:20.70#ibcon#wrote, iclass 11, count 0 2006.285.23:47:20.70#ibcon#about to read 3, iclass 11, count 0 2006.285.23:47:20.72#ibcon#read 3, iclass 11, count 0 2006.285.23:47:20.72#ibcon#about to read 4, iclass 11, count 0 2006.285.23:47:20.72#ibcon#read 4, iclass 11, count 0 2006.285.23:47:20.72#ibcon#about to read 5, iclass 11, count 0 2006.285.23:47:20.72#ibcon#read 5, iclass 11, count 0 2006.285.23:47:20.72#ibcon#about to read 6, iclass 11, count 0 2006.285.23:47:20.72#ibcon#read 6, iclass 11, count 0 2006.285.23:47:20.72#ibcon#end of sib2, iclass 11, count 0 2006.285.23:47:20.72#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:47:20.72#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:47:20.72#ibcon#[27=USB\r\n] 2006.285.23:47:20.72#ibcon#*before write, iclass 11, count 0 2006.285.23:47:20.72#ibcon#enter sib2, iclass 11, count 0 2006.285.23:47:20.72#ibcon#flushed, iclass 11, count 0 2006.285.23:47:20.72#ibcon#about to write, iclass 11, count 0 2006.285.23:47:20.72#ibcon#wrote, iclass 11, count 0 2006.285.23:47:20.72#ibcon#about to read 3, iclass 11, count 0 2006.285.23:47:20.75#ibcon#read 3, iclass 11, count 0 2006.285.23:47:20.75#ibcon#about to read 4, iclass 11, count 0 2006.285.23:47:20.75#ibcon#read 4, iclass 11, count 0 2006.285.23:47:20.75#ibcon#about to read 5, iclass 11, count 0 2006.285.23:47:20.75#ibcon#read 5, iclass 11, count 0 2006.285.23:47:20.75#ibcon#about to read 6, iclass 11, count 0 2006.285.23:47:20.75#ibcon#read 6, iclass 11, count 0 2006.285.23:47:20.75#ibcon#end of sib2, iclass 11, count 0 2006.285.23:47:20.75#ibcon#*after write, iclass 11, count 0 2006.285.23:47:20.75#ibcon#*before return 0, iclass 11, count 0 2006.285.23:47:20.75#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:47:20.75#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:47:20.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:47:20.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:47:20.75$vck44/vblo=4,679.99 2006.285.23:47:20.75#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.285.23:47:20.75#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.285.23:47:20.75#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:20.75#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:47:20.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:47:20.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:47:20.75#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:47:20.75#ibcon#first serial, iclass 13, count 0 2006.285.23:47:20.75#ibcon#enter sib2, iclass 13, count 0 2006.285.23:47:20.75#ibcon#flushed, iclass 13, count 0 2006.285.23:47:20.75#ibcon#about to write, iclass 13, count 0 2006.285.23:47:20.75#ibcon#wrote, iclass 13, count 0 2006.285.23:47:20.75#ibcon#about to read 3, iclass 13, count 0 2006.285.23:47:20.77#ibcon#read 3, iclass 13, count 0 2006.285.23:47:20.77#ibcon#about to read 4, iclass 13, count 0 2006.285.23:47:20.77#ibcon#read 4, iclass 13, count 0 2006.285.23:47:20.77#ibcon#about to read 5, iclass 13, count 0 2006.285.23:47:20.77#ibcon#read 5, iclass 13, count 0 2006.285.23:47:20.77#ibcon#about to read 6, iclass 13, count 0 2006.285.23:47:20.77#ibcon#read 6, iclass 13, count 0 2006.285.23:47:20.77#ibcon#end of sib2, iclass 13, count 0 2006.285.23:47:20.77#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:47:20.77#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:47:20.77#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:47:20.77#ibcon#*before write, iclass 13, count 0 2006.285.23:47:20.77#ibcon#enter sib2, iclass 13, count 0 2006.285.23:47:20.77#ibcon#flushed, iclass 13, count 0 2006.285.23:47:20.77#ibcon#about to write, iclass 13, count 0 2006.285.23:47:20.77#ibcon#wrote, iclass 13, count 0 2006.285.23:47:20.77#ibcon#about to read 3, iclass 13, count 0 2006.285.23:47:20.81#ibcon#read 3, iclass 13, count 0 2006.285.23:47:20.81#ibcon#about to read 4, iclass 13, count 0 2006.285.23:47:20.81#ibcon#read 4, iclass 13, count 0 2006.285.23:47:20.81#ibcon#about to read 5, iclass 13, count 0 2006.285.23:47:20.81#ibcon#read 5, iclass 13, count 0 2006.285.23:47:20.81#ibcon#about to read 6, iclass 13, count 0 2006.285.23:47:20.81#ibcon#read 6, iclass 13, count 0 2006.285.23:47:20.81#ibcon#end of sib2, iclass 13, count 0 2006.285.23:47:20.81#ibcon#*after write, iclass 13, count 0 2006.285.23:47:20.81#ibcon#*before return 0, iclass 13, count 0 2006.285.23:47:20.81#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:47:20.81#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.285.23:47:20.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:47:20.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:47:20.81$vck44/vb=4,5 2006.285.23:47:20.81#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.285.23:47:20.81#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.285.23:47:20.81#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:20.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:47:20.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:47:20.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:47:20.87#ibcon#enter wrdev, iclass 15, count 2 2006.285.23:47:20.87#ibcon#first serial, iclass 15, count 2 2006.285.23:47:20.87#ibcon#enter sib2, iclass 15, count 2 2006.285.23:47:20.87#ibcon#flushed, iclass 15, count 2 2006.285.23:47:20.87#ibcon#about to write, iclass 15, count 2 2006.285.23:47:20.87#ibcon#wrote, iclass 15, count 2 2006.285.23:47:20.87#ibcon#about to read 3, iclass 15, count 2 2006.285.23:47:20.89#ibcon#read 3, iclass 15, count 2 2006.285.23:47:20.89#ibcon#about to read 4, iclass 15, count 2 2006.285.23:47:20.89#ibcon#read 4, iclass 15, count 2 2006.285.23:47:20.89#ibcon#about to read 5, iclass 15, count 2 2006.285.23:47:20.89#ibcon#read 5, iclass 15, count 2 2006.285.23:47:20.89#ibcon#about to read 6, iclass 15, count 2 2006.285.23:47:20.89#ibcon#read 6, iclass 15, count 2 2006.285.23:47:20.89#ibcon#end of sib2, iclass 15, count 2 2006.285.23:47:20.89#ibcon#*mode == 0, iclass 15, count 2 2006.285.23:47:20.89#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.285.23:47:20.89#ibcon#[27=AT04-05\r\n] 2006.285.23:47:20.89#ibcon#*before write, iclass 15, count 2 2006.285.23:47:20.89#ibcon#enter sib2, iclass 15, count 2 2006.285.23:47:20.89#ibcon#flushed, iclass 15, count 2 2006.285.23:47:20.89#ibcon#about to write, iclass 15, count 2 2006.285.23:47:20.89#ibcon#wrote, iclass 15, count 2 2006.285.23:47:20.89#ibcon#about to read 3, iclass 15, count 2 2006.285.23:47:20.92#ibcon#read 3, iclass 15, count 2 2006.285.23:47:20.92#ibcon#about to read 4, iclass 15, count 2 2006.285.23:47:20.92#ibcon#read 4, iclass 15, count 2 2006.285.23:47:20.92#ibcon#about to read 5, iclass 15, count 2 2006.285.23:47:20.92#ibcon#read 5, iclass 15, count 2 2006.285.23:47:20.92#ibcon#about to read 6, iclass 15, count 2 2006.285.23:47:20.92#ibcon#read 6, iclass 15, count 2 2006.285.23:47:20.92#ibcon#end of sib2, iclass 15, count 2 2006.285.23:47:20.92#ibcon#*after write, iclass 15, count 2 2006.285.23:47:20.92#ibcon#*before return 0, iclass 15, count 2 2006.285.23:47:20.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:47:20.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.285.23:47:20.92#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.285.23:47:20.92#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:20.92#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:47:21.04#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:47:21.04#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:47:21.04#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:47:21.04#ibcon#first serial, iclass 15, count 0 2006.285.23:47:21.04#ibcon#enter sib2, iclass 15, count 0 2006.285.23:47:21.04#ibcon#flushed, iclass 15, count 0 2006.285.23:47:21.04#ibcon#about to write, iclass 15, count 0 2006.285.23:47:21.04#ibcon#wrote, iclass 15, count 0 2006.285.23:47:21.04#ibcon#about to read 3, iclass 15, count 0 2006.285.23:47:21.06#ibcon#read 3, iclass 15, count 0 2006.285.23:47:21.06#ibcon#about to read 4, iclass 15, count 0 2006.285.23:47:21.06#ibcon#read 4, iclass 15, count 0 2006.285.23:47:21.06#ibcon#about to read 5, iclass 15, count 0 2006.285.23:47:21.06#ibcon#read 5, iclass 15, count 0 2006.285.23:47:21.06#ibcon#about to read 6, iclass 15, count 0 2006.285.23:47:21.06#ibcon#read 6, iclass 15, count 0 2006.285.23:47:21.06#ibcon#end of sib2, iclass 15, count 0 2006.285.23:47:21.06#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:47:21.06#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:47:21.06#ibcon#[27=USB\r\n] 2006.285.23:47:21.06#ibcon#*before write, iclass 15, count 0 2006.285.23:47:21.06#ibcon#enter sib2, iclass 15, count 0 2006.285.23:47:21.06#ibcon#flushed, iclass 15, count 0 2006.285.23:47:21.06#ibcon#about to write, iclass 15, count 0 2006.285.23:47:21.06#ibcon#wrote, iclass 15, count 0 2006.285.23:47:21.06#ibcon#about to read 3, iclass 15, count 0 2006.285.23:47:21.09#ibcon#read 3, iclass 15, count 0 2006.285.23:47:21.09#ibcon#about to read 4, iclass 15, count 0 2006.285.23:47:21.09#ibcon#read 4, iclass 15, count 0 2006.285.23:47:21.09#ibcon#about to read 5, iclass 15, count 0 2006.285.23:47:21.09#ibcon#read 5, iclass 15, count 0 2006.285.23:47:21.09#ibcon#about to read 6, iclass 15, count 0 2006.285.23:47:21.09#ibcon#read 6, iclass 15, count 0 2006.285.23:47:21.09#ibcon#end of sib2, iclass 15, count 0 2006.285.23:47:21.09#ibcon#*after write, iclass 15, count 0 2006.285.23:47:21.09#ibcon#*before return 0, iclass 15, count 0 2006.285.23:47:21.09#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:47:21.09#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.285.23:47:21.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:47:21.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:47:21.09$vck44/vblo=5,709.99 2006.285.23:47:21.09#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.285.23:47:21.09#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.285.23:47:21.09#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:21.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:47:21.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:47:21.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:47:21.09#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:47:21.09#ibcon#first serial, iclass 17, count 0 2006.285.23:47:21.09#ibcon#enter sib2, iclass 17, count 0 2006.285.23:47:21.09#ibcon#flushed, iclass 17, count 0 2006.285.23:47:21.09#ibcon#about to write, iclass 17, count 0 2006.285.23:47:21.09#ibcon#wrote, iclass 17, count 0 2006.285.23:47:21.09#ibcon#about to read 3, iclass 17, count 0 2006.285.23:47:21.11#ibcon#read 3, iclass 17, count 0 2006.285.23:47:21.11#ibcon#about to read 4, iclass 17, count 0 2006.285.23:47:21.11#ibcon#read 4, iclass 17, count 0 2006.285.23:47:21.11#ibcon#about to read 5, iclass 17, count 0 2006.285.23:47:21.11#ibcon#read 5, iclass 17, count 0 2006.285.23:47:21.11#ibcon#about to read 6, iclass 17, count 0 2006.285.23:47:21.11#ibcon#read 6, iclass 17, count 0 2006.285.23:47:21.11#ibcon#end of sib2, iclass 17, count 0 2006.285.23:47:21.11#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:47:21.11#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:47:21.11#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:47:21.11#ibcon#*before write, iclass 17, count 0 2006.285.23:47:21.11#ibcon#enter sib2, iclass 17, count 0 2006.285.23:47:21.11#ibcon#flushed, iclass 17, count 0 2006.285.23:47:21.11#ibcon#about to write, iclass 17, count 0 2006.285.23:47:21.11#ibcon#wrote, iclass 17, count 0 2006.285.23:47:21.11#ibcon#about to read 3, iclass 17, count 0 2006.285.23:47:21.15#ibcon#read 3, iclass 17, count 0 2006.285.23:47:21.15#ibcon#about to read 4, iclass 17, count 0 2006.285.23:47:21.15#ibcon#read 4, iclass 17, count 0 2006.285.23:47:21.15#ibcon#about to read 5, iclass 17, count 0 2006.285.23:47:21.15#ibcon#read 5, iclass 17, count 0 2006.285.23:47:21.15#ibcon#about to read 6, iclass 17, count 0 2006.285.23:47:21.15#ibcon#read 6, iclass 17, count 0 2006.285.23:47:21.15#ibcon#end of sib2, iclass 17, count 0 2006.285.23:47:21.15#ibcon#*after write, iclass 17, count 0 2006.285.23:47:21.15#ibcon#*before return 0, iclass 17, count 0 2006.285.23:47:21.15#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:47:21.15#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.285.23:47:21.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:47:21.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:47:21.15$vck44/vb=5,4 2006.285.23:47:21.15#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.285.23:47:21.15#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.285.23:47:21.15#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:21.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:47:21.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:47:21.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:47:21.21#ibcon#enter wrdev, iclass 19, count 2 2006.285.23:47:21.21#ibcon#first serial, iclass 19, count 2 2006.285.23:47:21.21#ibcon#enter sib2, iclass 19, count 2 2006.285.23:47:21.21#ibcon#flushed, iclass 19, count 2 2006.285.23:47:21.21#ibcon#about to write, iclass 19, count 2 2006.285.23:47:21.21#ibcon#wrote, iclass 19, count 2 2006.285.23:47:21.21#ibcon#about to read 3, iclass 19, count 2 2006.285.23:47:21.23#ibcon#read 3, iclass 19, count 2 2006.285.23:47:21.23#ibcon#about to read 4, iclass 19, count 2 2006.285.23:47:21.23#ibcon#read 4, iclass 19, count 2 2006.285.23:47:21.23#ibcon#about to read 5, iclass 19, count 2 2006.285.23:47:21.23#ibcon#read 5, iclass 19, count 2 2006.285.23:47:21.23#ibcon#about to read 6, iclass 19, count 2 2006.285.23:47:21.23#ibcon#read 6, iclass 19, count 2 2006.285.23:47:21.23#ibcon#end of sib2, iclass 19, count 2 2006.285.23:47:21.23#ibcon#*mode == 0, iclass 19, count 2 2006.285.23:47:21.23#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.285.23:47:21.23#ibcon#[27=AT05-04\r\n] 2006.285.23:47:21.23#ibcon#*before write, iclass 19, count 2 2006.285.23:47:21.23#ibcon#enter sib2, iclass 19, count 2 2006.285.23:47:21.23#ibcon#flushed, iclass 19, count 2 2006.285.23:47:21.23#ibcon#about to write, iclass 19, count 2 2006.285.23:47:21.23#ibcon#wrote, iclass 19, count 2 2006.285.23:47:21.23#ibcon#about to read 3, iclass 19, count 2 2006.285.23:47:21.26#ibcon#read 3, iclass 19, count 2 2006.285.23:47:21.26#ibcon#about to read 4, iclass 19, count 2 2006.285.23:47:21.26#ibcon#read 4, iclass 19, count 2 2006.285.23:47:21.26#ibcon#about to read 5, iclass 19, count 2 2006.285.23:47:21.26#ibcon#read 5, iclass 19, count 2 2006.285.23:47:21.26#ibcon#about to read 6, iclass 19, count 2 2006.285.23:47:21.26#ibcon#read 6, iclass 19, count 2 2006.285.23:47:21.26#ibcon#end of sib2, iclass 19, count 2 2006.285.23:47:21.26#ibcon#*after write, iclass 19, count 2 2006.285.23:47:21.26#ibcon#*before return 0, iclass 19, count 2 2006.285.23:47:21.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:47:21.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.285.23:47:21.26#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.285.23:47:21.26#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:21.26#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:47:21.38#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:47:21.38#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:47:21.38#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:47:21.38#ibcon#first serial, iclass 19, count 0 2006.285.23:47:21.38#ibcon#enter sib2, iclass 19, count 0 2006.285.23:47:21.38#ibcon#flushed, iclass 19, count 0 2006.285.23:47:21.38#ibcon#about to write, iclass 19, count 0 2006.285.23:47:21.38#ibcon#wrote, iclass 19, count 0 2006.285.23:47:21.38#ibcon#about to read 3, iclass 19, count 0 2006.285.23:47:21.40#ibcon#read 3, iclass 19, count 0 2006.285.23:47:21.40#ibcon#about to read 4, iclass 19, count 0 2006.285.23:47:21.40#ibcon#read 4, iclass 19, count 0 2006.285.23:47:21.40#ibcon#about to read 5, iclass 19, count 0 2006.285.23:47:21.40#ibcon#read 5, iclass 19, count 0 2006.285.23:47:21.40#ibcon#about to read 6, iclass 19, count 0 2006.285.23:47:21.40#ibcon#read 6, iclass 19, count 0 2006.285.23:47:21.40#ibcon#end of sib2, iclass 19, count 0 2006.285.23:47:21.40#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:47:21.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:47:21.40#ibcon#[27=USB\r\n] 2006.285.23:47:21.40#ibcon#*before write, iclass 19, count 0 2006.285.23:47:21.40#ibcon#enter sib2, iclass 19, count 0 2006.285.23:47:21.40#ibcon#flushed, iclass 19, count 0 2006.285.23:47:21.40#ibcon#about to write, iclass 19, count 0 2006.285.23:47:21.40#ibcon#wrote, iclass 19, count 0 2006.285.23:47:21.40#ibcon#about to read 3, iclass 19, count 0 2006.285.23:47:21.43#ibcon#read 3, iclass 19, count 0 2006.285.23:47:21.43#ibcon#about to read 4, iclass 19, count 0 2006.285.23:47:21.43#ibcon#read 4, iclass 19, count 0 2006.285.23:47:21.43#ibcon#about to read 5, iclass 19, count 0 2006.285.23:47:21.43#ibcon#read 5, iclass 19, count 0 2006.285.23:47:21.43#ibcon#about to read 6, iclass 19, count 0 2006.285.23:47:21.43#ibcon#read 6, iclass 19, count 0 2006.285.23:47:21.43#ibcon#end of sib2, iclass 19, count 0 2006.285.23:47:21.43#ibcon#*after write, iclass 19, count 0 2006.285.23:47:21.43#ibcon#*before return 0, iclass 19, count 0 2006.285.23:47:21.43#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:47:21.43#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.285.23:47:21.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:47:21.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:47:21.43$vck44/vblo=6,719.99 2006.285.23:47:21.43#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.285.23:47:21.43#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.285.23:47:21.43#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:21.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:47:21.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:47:21.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:47:21.43#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:47:21.43#ibcon#first serial, iclass 21, count 0 2006.285.23:47:21.43#ibcon#enter sib2, iclass 21, count 0 2006.285.23:47:21.43#ibcon#flushed, iclass 21, count 0 2006.285.23:47:21.43#ibcon#about to write, iclass 21, count 0 2006.285.23:47:21.43#ibcon#wrote, iclass 21, count 0 2006.285.23:47:21.43#ibcon#about to read 3, iclass 21, count 0 2006.285.23:47:21.45#ibcon#read 3, iclass 21, count 0 2006.285.23:47:21.45#ibcon#about to read 4, iclass 21, count 0 2006.285.23:47:21.45#ibcon#read 4, iclass 21, count 0 2006.285.23:47:21.45#ibcon#about to read 5, iclass 21, count 0 2006.285.23:47:21.45#ibcon#read 5, iclass 21, count 0 2006.285.23:47:21.45#ibcon#about to read 6, iclass 21, count 0 2006.285.23:47:21.45#ibcon#read 6, iclass 21, count 0 2006.285.23:47:21.45#ibcon#end of sib2, iclass 21, count 0 2006.285.23:47:21.45#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:47:21.45#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:47:21.45#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:47:21.45#ibcon#*before write, iclass 21, count 0 2006.285.23:47:21.45#ibcon#enter sib2, iclass 21, count 0 2006.285.23:47:21.45#ibcon#flushed, iclass 21, count 0 2006.285.23:47:21.45#ibcon#about to write, iclass 21, count 0 2006.285.23:47:21.45#ibcon#wrote, iclass 21, count 0 2006.285.23:47:21.45#ibcon#about to read 3, iclass 21, count 0 2006.285.23:47:21.49#ibcon#read 3, iclass 21, count 0 2006.285.23:47:21.49#ibcon#about to read 4, iclass 21, count 0 2006.285.23:47:21.49#ibcon#read 4, iclass 21, count 0 2006.285.23:47:21.49#ibcon#about to read 5, iclass 21, count 0 2006.285.23:47:21.49#ibcon#read 5, iclass 21, count 0 2006.285.23:47:21.49#ibcon#about to read 6, iclass 21, count 0 2006.285.23:47:21.49#ibcon#read 6, iclass 21, count 0 2006.285.23:47:21.49#ibcon#end of sib2, iclass 21, count 0 2006.285.23:47:21.49#ibcon#*after write, iclass 21, count 0 2006.285.23:47:21.49#ibcon#*before return 0, iclass 21, count 0 2006.285.23:47:21.49#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:47:21.49#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.285.23:47:21.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:47:21.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:47:21.49$vck44/vb=6,3 2006.285.23:47:21.49#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.285.23:47:21.49#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.285.23:47:21.49#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:21.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:47:21.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:47:21.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:47:21.55#ibcon#enter wrdev, iclass 23, count 2 2006.285.23:47:21.55#ibcon#first serial, iclass 23, count 2 2006.285.23:47:21.55#ibcon#enter sib2, iclass 23, count 2 2006.285.23:47:21.55#ibcon#flushed, iclass 23, count 2 2006.285.23:47:21.55#ibcon#about to write, iclass 23, count 2 2006.285.23:47:21.55#ibcon#wrote, iclass 23, count 2 2006.285.23:47:21.55#ibcon#about to read 3, iclass 23, count 2 2006.285.23:47:21.57#ibcon#read 3, iclass 23, count 2 2006.285.23:47:21.57#ibcon#about to read 4, iclass 23, count 2 2006.285.23:47:21.57#ibcon#read 4, iclass 23, count 2 2006.285.23:47:21.57#ibcon#about to read 5, iclass 23, count 2 2006.285.23:47:21.57#ibcon#read 5, iclass 23, count 2 2006.285.23:47:21.57#ibcon#about to read 6, iclass 23, count 2 2006.285.23:47:21.57#ibcon#read 6, iclass 23, count 2 2006.285.23:47:21.57#ibcon#end of sib2, iclass 23, count 2 2006.285.23:47:21.57#ibcon#*mode == 0, iclass 23, count 2 2006.285.23:47:21.57#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.285.23:47:21.57#ibcon#[27=AT06-03\r\n] 2006.285.23:47:21.57#ibcon#*before write, iclass 23, count 2 2006.285.23:47:21.57#ibcon#enter sib2, iclass 23, count 2 2006.285.23:47:21.57#ibcon#flushed, iclass 23, count 2 2006.285.23:47:21.57#ibcon#about to write, iclass 23, count 2 2006.285.23:47:21.57#ibcon#wrote, iclass 23, count 2 2006.285.23:47:21.57#ibcon#about to read 3, iclass 23, count 2 2006.285.23:47:21.60#ibcon#read 3, iclass 23, count 2 2006.285.23:47:21.60#ibcon#about to read 4, iclass 23, count 2 2006.285.23:47:21.60#ibcon#read 4, iclass 23, count 2 2006.285.23:47:21.60#ibcon#about to read 5, iclass 23, count 2 2006.285.23:47:21.60#ibcon#read 5, iclass 23, count 2 2006.285.23:47:21.60#ibcon#about to read 6, iclass 23, count 2 2006.285.23:47:21.60#ibcon#read 6, iclass 23, count 2 2006.285.23:47:21.60#ibcon#end of sib2, iclass 23, count 2 2006.285.23:47:21.60#ibcon#*after write, iclass 23, count 2 2006.285.23:47:21.60#ibcon#*before return 0, iclass 23, count 2 2006.285.23:47:21.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:47:21.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.285.23:47:21.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.285.23:47:21.60#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:21.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:47:21.72#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:47:21.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:47:21.72#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:47:21.72#ibcon#first serial, iclass 23, count 0 2006.285.23:47:21.72#ibcon#enter sib2, iclass 23, count 0 2006.285.23:47:21.72#ibcon#flushed, iclass 23, count 0 2006.285.23:47:21.72#ibcon#about to write, iclass 23, count 0 2006.285.23:47:21.72#ibcon#wrote, iclass 23, count 0 2006.285.23:47:21.72#ibcon#about to read 3, iclass 23, count 0 2006.285.23:47:21.74#ibcon#read 3, iclass 23, count 0 2006.285.23:47:21.74#ibcon#about to read 4, iclass 23, count 0 2006.285.23:47:21.74#ibcon#read 4, iclass 23, count 0 2006.285.23:47:21.74#ibcon#about to read 5, iclass 23, count 0 2006.285.23:47:21.74#ibcon#read 5, iclass 23, count 0 2006.285.23:47:21.74#ibcon#about to read 6, iclass 23, count 0 2006.285.23:47:21.74#ibcon#read 6, iclass 23, count 0 2006.285.23:47:21.74#ibcon#end of sib2, iclass 23, count 0 2006.285.23:47:21.74#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:47:21.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:47:21.74#ibcon#[27=USB\r\n] 2006.285.23:47:21.74#ibcon#*before write, iclass 23, count 0 2006.285.23:47:21.74#ibcon#enter sib2, iclass 23, count 0 2006.285.23:47:21.74#ibcon#flushed, iclass 23, count 0 2006.285.23:47:21.74#ibcon#about to write, iclass 23, count 0 2006.285.23:47:21.74#ibcon#wrote, iclass 23, count 0 2006.285.23:47:21.74#ibcon#about to read 3, iclass 23, count 0 2006.285.23:47:21.77#ibcon#read 3, iclass 23, count 0 2006.285.23:47:21.77#ibcon#about to read 4, iclass 23, count 0 2006.285.23:47:21.77#ibcon#read 4, iclass 23, count 0 2006.285.23:47:21.77#ibcon#about to read 5, iclass 23, count 0 2006.285.23:47:21.77#ibcon#read 5, iclass 23, count 0 2006.285.23:47:21.77#ibcon#about to read 6, iclass 23, count 0 2006.285.23:47:21.77#ibcon#read 6, iclass 23, count 0 2006.285.23:47:21.77#ibcon#end of sib2, iclass 23, count 0 2006.285.23:47:21.77#ibcon#*after write, iclass 23, count 0 2006.285.23:47:21.77#ibcon#*before return 0, iclass 23, count 0 2006.285.23:47:21.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:47:21.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.285.23:47:21.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:47:21.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:47:21.77$vck44/vblo=7,734.99 2006.285.23:47:21.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.23:47:21.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.23:47:21.77#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:21.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:47:21.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:47:21.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:47:21.77#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:47:21.77#ibcon#first serial, iclass 25, count 0 2006.285.23:47:21.77#ibcon#enter sib2, iclass 25, count 0 2006.285.23:47:21.77#ibcon#flushed, iclass 25, count 0 2006.285.23:47:21.77#ibcon#about to write, iclass 25, count 0 2006.285.23:47:21.77#ibcon#wrote, iclass 25, count 0 2006.285.23:47:21.77#ibcon#about to read 3, iclass 25, count 0 2006.285.23:47:21.79#ibcon#read 3, iclass 25, count 0 2006.285.23:47:21.79#ibcon#about to read 4, iclass 25, count 0 2006.285.23:47:21.79#ibcon#read 4, iclass 25, count 0 2006.285.23:47:21.79#ibcon#about to read 5, iclass 25, count 0 2006.285.23:47:21.79#ibcon#read 5, iclass 25, count 0 2006.285.23:47:21.79#ibcon#about to read 6, iclass 25, count 0 2006.285.23:47:21.79#ibcon#read 6, iclass 25, count 0 2006.285.23:47:21.79#ibcon#end of sib2, iclass 25, count 0 2006.285.23:47:21.79#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:47:21.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:47:21.79#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:47:21.79#ibcon#*before write, iclass 25, count 0 2006.285.23:47:21.79#ibcon#enter sib2, iclass 25, count 0 2006.285.23:47:21.79#ibcon#flushed, iclass 25, count 0 2006.285.23:47:21.79#ibcon#about to write, iclass 25, count 0 2006.285.23:47:21.79#ibcon#wrote, iclass 25, count 0 2006.285.23:47:21.79#ibcon#about to read 3, iclass 25, count 0 2006.285.23:47:21.83#ibcon#read 3, iclass 25, count 0 2006.285.23:47:21.83#ibcon#about to read 4, iclass 25, count 0 2006.285.23:47:21.83#ibcon#read 4, iclass 25, count 0 2006.285.23:47:21.83#ibcon#about to read 5, iclass 25, count 0 2006.285.23:47:21.83#ibcon#read 5, iclass 25, count 0 2006.285.23:47:21.83#ibcon#about to read 6, iclass 25, count 0 2006.285.23:47:21.83#ibcon#read 6, iclass 25, count 0 2006.285.23:47:21.83#ibcon#end of sib2, iclass 25, count 0 2006.285.23:47:21.83#ibcon#*after write, iclass 25, count 0 2006.285.23:47:21.83#ibcon#*before return 0, iclass 25, count 0 2006.285.23:47:21.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:47:21.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:47:21.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:47:21.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:47:21.83$vck44/vb=7,4 2006.285.23:47:21.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.285.23:47:21.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.285.23:47:21.83#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:21.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:47:21.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:47:21.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:47:21.89#ibcon#enter wrdev, iclass 27, count 2 2006.285.23:47:21.89#ibcon#first serial, iclass 27, count 2 2006.285.23:47:21.89#ibcon#enter sib2, iclass 27, count 2 2006.285.23:47:21.89#ibcon#flushed, iclass 27, count 2 2006.285.23:47:21.89#ibcon#about to write, iclass 27, count 2 2006.285.23:47:21.89#ibcon#wrote, iclass 27, count 2 2006.285.23:47:21.89#ibcon#about to read 3, iclass 27, count 2 2006.285.23:47:21.91#ibcon#read 3, iclass 27, count 2 2006.285.23:47:21.91#ibcon#about to read 4, iclass 27, count 2 2006.285.23:47:21.91#ibcon#read 4, iclass 27, count 2 2006.285.23:47:21.91#ibcon#about to read 5, iclass 27, count 2 2006.285.23:47:21.91#ibcon#read 5, iclass 27, count 2 2006.285.23:47:21.91#ibcon#about to read 6, iclass 27, count 2 2006.285.23:47:21.91#ibcon#read 6, iclass 27, count 2 2006.285.23:47:21.91#ibcon#end of sib2, iclass 27, count 2 2006.285.23:47:21.91#ibcon#*mode == 0, iclass 27, count 2 2006.285.23:47:21.91#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.285.23:47:21.91#ibcon#[27=AT07-04\r\n] 2006.285.23:47:21.91#ibcon#*before write, iclass 27, count 2 2006.285.23:47:21.91#ibcon#enter sib2, iclass 27, count 2 2006.285.23:47:21.91#ibcon#flushed, iclass 27, count 2 2006.285.23:47:21.91#ibcon#about to write, iclass 27, count 2 2006.285.23:47:21.91#ibcon#wrote, iclass 27, count 2 2006.285.23:47:21.91#ibcon#about to read 3, iclass 27, count 2 2006.285.23:47:21.94#ibcon#read 3, iclass 27, count 2 2006.285.23:47:21.94#ibcon#about to read 4, iclass 27, count 2 2006.285.23:47:21.94#ibcon#read 4, iclass 27, count 2 2006.285.23:47:21.94#ibcon#about to read 5, iclass 27, count 2 2006.285.23:47:21.94#ibcon#read 5, iclass 27, count 2 2006.285.23:47:21.94#ibcon#about to read 6, iclass 27, count 2 2006.285.23:47:21.94#ibcon#read 6, iclass 27, count 2 2006.285.23:47:21.94#ibcon#end of sib2, iclass 27, count 2 2006.285.23:47:21.94#ibcon#*after write, iclass 27, count 2 2006.285.23:47:21.94#ibcon#*before return 0, iclass 27, count 2 2006.285.23:47:21.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:47:21.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.285.23:47:21.94#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.285.23:47:21.94#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:21.94#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:47:22.06#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:47:22.06#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:47:22.06#ibcon#enter wrdev, iclass 27, count 0 2006.285.23:47:22.06#ibcon#first serial, iclass 27, count 0 2006.285.23:47:22.06#ibcon#enter sib2, iclass 27, count 0 2006.285.23:47:22.06#ibcon#flushed, iclass 27, count 0 2006.285.23:47:22.06#ibcon#about to write, iclass 27, count 0 2006.285.23:47:22.06#ibcon#wrote, iclass 27, count 0 2006.285.23:47:22.06#ibcon#about to read 3, iclass 27, count 0 2006.285.23:47:22.08#ibcon#read 3, iclass 27, count 0 2006.285.23:47:22.08#ibcon#about to read 4, iclass 27, count 0 2006.285.23:47:22.08#ibcon#read 4, iclass 27, count 0 2006.285.23:47:22.08#ibcon#about to read 5, iclass 27, count 0 2006.285.23:47:22.08#ibcon#read 5, iclass 27, count 0 2006.285.23:47:22.08#ibcon#about to read 6, iclass 27, count 0 2006.285.23:47:22.08#ibcon#read 6, iclass 27, count 0 2006.285.23:47:22.08#ibcon#end of sib2, iclass 27, count 0 2006.285.23:47:22.08#ibcon#*mode == 0, iclass 27, count 0 2006.285.23:47:22.08#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.23:47:22.08#ibcon#[27=USB\r\n] 2006.285.23:47:22.08#ibcon#*before write, iclass 27, count 0 2006.285.23:47:22.08#ibcon#enter sib2, iclass 27, count 0 2006.285.23:47:22.08#ibcon#flushed, iclass 27, count 0 2006.285.23:47:22.08#ibcon#about to write, iclass 27, count 0 2006.285.23:47:22.08#ibcon#wrote, iclass 27, count 0 2006.285.23:47:22.08#ibcon#about to read 3, iclass 27, count 0 2006.285.23:47:22.11#ibcon#read 3, iclass 27, count 0 2006.285.23:47:22.11#ibcon#about to read 4, iclass 27, count 0 2006.285.23:47:22.11#ibcon#read 4, iclass 27, count 0 2006.285.23:47:22.11#ibcon#about to read 5, iclass 27, count 0 2006.285.23:47:22.11#ibcon#read 5, iclass 27, count 0 2006.285.23:47:22.11#ibcon#about to read 6, iclass 27, count 0 2006.285.23:47:22.11#ibcon#read 6, iclass 27, count 0 2006.285.23:47:22.11#ibcon#end of sib2, iclass 27, count 0 2006.285.23:47:22.11#ibcon#*after write, iclass 27, count 0 2006.285.23:47:22.11#ibcon#*before return 0, iclass 27, count 0 2006.285.23:47:22.11#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:47:22.11#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.285.23:47:22.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.23:47:22.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.23:47:22.11$vck44/vblo=8,744.99 2006.285.23:47:22.11#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.285.23:47:22.11#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.285.23:47:22.11#ibcon#ireg 17 cls_cnt 0 2006.285.23:47:22.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.23:47:22.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.285.23:47:22.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.23:47:22.11#ibcon#enter wrdev, iclass 29, count 0 2006.285.23:47:22.11#ibcon#first serial, iclass 29, count 0 2006.285.23:47:22.11#ibcon#enter sib2, iclass 29, count 0 2006.285.23:47:22.11#ibcon#flushed, iclass 29, count 0 2006.285.23:47:22.11#ibcon#about to write, iclass 29, count 0 2006.285.23:47:22.11#ibcon#wrote, iclass 29, count 0 2006.285.23:47:22.11#ibcon#about to read 3, iclass 29, count 0 2006.285.23:47:22.13#ibcon#read 3, iclass 29, count 0 2006.285.23:47:22.13#ibcon#about to read 4, iclass 29, count 0 2006.285.23:47:22.13#ibcon#read 4, iclass 29, count 0 2006.285.23:47:22.13#ibcon#about to read 5, iclass 29, count 0 2006.285.23:47:22.13#ibcon#read 5, iclass 29, count 0 2006.285.23:47:22.13#ibcon#about to read 6, iclass 29, count 0 2006.285.23:47:22.13#ibcon#read 6, iclass 29, count 0 2006.285.23:47:22.13#ibcon#end of sib2, iclass 29, count 0 2006.285.23:47:22.13#ibcon#*mode == 0, iclass 29, count 0 2006.285.23:47:22.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.23:47:22.13#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:47:22.13#ibcon#*before write, iclass 29, count 0 2006.285.23:47:22.13#ibcon#enter sib2, iclass 29, count 0 2006.285.23:47:22.13#ibcon#flushed, iclass 29, count 0 2006.285.23:47:22.13#ibcon#about to write, iclass 29, count 0 2006.285.23:47:22.13#ibcon#wrote, iclass 29, count 0 2006.285.23:47:22.13#ibcon#about to read 3, iclass 29, count 0 2006.285.23:47:22.17#ibcon#read 3, iclass 29, count 0 2006.285.23:47:22.17#ibcon#about to read 4, iclass 29, count 0 2006.285.23:47:22.17#ibcon#read 4, iclass 29, count 0 2006.285.23:47:22.17#ibcon#about to read 5, iclass 29, count 0 2006.285.23:47:22.17#ibcon#read 5, iclass 29, count 0 2006.285.23:47:22.17#ibcon#about to read 6, iclass 29, count 0 2006.285.23:47:22.17#ibcon#read 6, iclass 29, count 0 2006.285.23:47:22.17#ibcon#end of sib2, iclass 29, count 0 2006.285.23:47:22.17#ibcon#*after write, iclass 29, count 0 2006.285.23:47:22.17#ibcon#*before return 0, iclass 29, count 0 2006.285.23:47:22.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.285.23:47:22.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.285.23:47:22.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.23:47:22.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.23:47:22.17$vck44/vb=8,4 2006.285.23:47:22.17#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.285.23:47:22.17#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.285.23:47:22.17#ibcon#ireg 11 cls_cnt 2 2006.285.23:47:22.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.23:47:22.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.285.23:47:22.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.23:47:22.23#ibcon#enter wrdev, iclass 31, count 2 2006.285.23:47:22.23#ibcon#first serial, iclass 31, count 2 2006.285.23:47:22.23#ibcon#enter sib2, iclass 31, count 2 2006.285.23:47:22.23#ibcon#flushed, iclass 31, count 2 2006.285.23:47:22.23#ibcon#about to write, iclass 31, count 2 2006.285.23:47:22.23#ibcon#wrote, iclass 31, count 2 2006.285.23:47:22.23#ibcon#about to read 3, iclass 31, count 2 2006.285.23:47:22.25#ibcon#read 3, iclass 31, count 2 2006.285.23:47:22.25#ibcon#about to read 4, iclass 31, count 2 2006.285.23:47:22.25#ibcon#read 4, iclass 31, count 2 2006.285.23:47:22.25#ibcon#about to read 5, iclass 31, count 2 2006.285.23:47:22.25#ibcon#read 5, iclass 31, count 2 2006.285.23:47:22.25#ibcon#about to read 6, iclass 31, count 2 2006.285.23:47:22.25#ibcon#read 6, iclass 31, count 2 2006.285.23:47:22.25#ibcon#end of sib2, iclass 31, count 2 2006.285.23:47:22.25#ibcon#*mode == 0, iclass 31, count 2 2006.285.23:47:22.25#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.285.23:47:22.25#ibcon#[27=AT08-04\r\n] 2006.285.23:47:22.25#ibcon#*before write, iclass 31, count 2 2006.285.23:47:22.25#ibcon#enter sib2, iclass 31, count 2 2006.285.23:47:22.25#ibcon#flushed, iclass 31, count 2 2006.285.23:47:22.25#ibcon#about to write, iclass 31, count 2 2006.285.23:47:22.25#ibcon#wrote, iclass 31, count 2 2006.285.23:47:22.25#ibcon#about to read 3, iclass 31, count 2 2006.285.23:47:22.28#ibcon#read 3, iclass 31, count 2 2006.285.23:47:22.28#ibcon#about to read 4, iclass 31, count 2 2006.285.23:47:22.28#ibcon#read 4, iclass 31, count 2 2006.285.23:47:22.28#ibcon#about to read 5, iclass 31, count 2 2006.285.23:47:22.28#ibcon#read 5, iclass 31, count 2 2006.285.23:47:22.28#ibcon#about to read 6, iclass 31, count 2 2006.285.23:47:22.28#ibcon#read 6, iclass 31, count 2 2006.285.23:47:22.28#ibcon#end of sib2, iclass 31, count 2 2006.285.23:47:22.28#ibcon#*after write, iclass 31, count 2 2006.285.23:47:22.28#ibcon#*before return 0, iclass 31, count 2 2006.285.23:47:22.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.285.23:47:22.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.285.23:47:22.28#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.285.23:47:22.28#ibcon#ireg 7 cls_cnt 0 2006.285.23:47:22.28#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.23:47:22.40#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.285.23:47:22.40#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.23:47:22.40#ibcon#enter wrdev, iclass 31, count 0 2006.285.23:47:22.40#ibcon#first serial, iclass 31, count 0 2006.285.23:47:22.40#ibcon#enter sib2, iclass 31, count 0 2006.285.23:47:22.40#ibcon#flushed, iclass 31, count 0 2006.285.23:47:22.40#ibcon#about to write, iclass 31, count 0 2006.285.23:47:22.40#ibcon#wrote, iclass 31, count 0 2006.285.23:47:22.40#ibcon#about to read 3, iclass 31, count 0 2006.285.23:47:22.42#ibcon#read 3, iclass 31, count 0 2006.285.23:47:22.42#ibcon#about to read 4, iclass 31, count 0 2006.285.23:47:22.42#ibcon#read 4, iclass 31, count 0 2006.285.23:47:22.42#ibcon#about to read 5, iclass 31, count 0 2006.285.23:47:22.42#ibcon#read 5, iclass 31, count 0 2006.285.23:47:22.42#ibcon#about to read 6, iclass 31, count 0 2006.285.23:47:22.42#ibcon#read 6, iclass 31, count 0 2006.285.23:47:22.42#ibcon#end of sib2, iclass 31, count 0 2006.285.23:47:22.42#ibcon#*mode == 0, iclass 31, count 0 2006.285.23:47:22.42#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.23:47:22.42#ibcon#[27=USB\r\n] 2006.285.23:47:22.42#ibcon#*before write, iclass 31, count 0 2006.285.23:47:22.42#ibcon#enter sib2, iclass 31, count 0 2006.285.23:47:22.42#ibcon#flushed, iclass 31, count 0 2006.285.23:47:22.42#ibcon#about to write, iclass 31, count 0 2006.285.23:47:22.42#ibcon#wrote, iclass 31, count 0 2006.285.23:47:22.42#ibcon#about to read 3, iclass 31, count 0 2006.285.23:47:22.45#ibcon#read 3, iclass 31, count 0 2006.285.23:47:22.45#ibcon#about to read 4, iclass 31, count 0 2006.285.23:47:22.45#ibcon#read 4, iclass 31, count 0 2006.285.23:47:22.45#ibcon#about to read 5, iclass 31, count 0 2006.285.23:47:22.45#ibcon#read 5, iclass 31, count 0 2006.285.23:47:22.45#ibcon#about to read 6, iclass 31, count 0 2006.285.23:47:22.45#ibcon#read 6, iclass 31, count 0 2006.285.23:47:22.45#ibcon#end of sib2, iclass 31, count 0 2006.285.23:47:22.45#ibcon#*after write, iclass 31, count 0 2006.285.23:47:22.45#ibcon#*before return 0, iclass 31, count 0 2006.285.23:47:22.45#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.285.23:47:22.45#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.285.23:47:22.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.23:47:22.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.23:47:22.45$vck44/vabw=wide 2006.285.23:47:22.45#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.285.23:47:22.45#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.285.23:47:22.45#ibcon#ireg 8 cls_cnt 0 2006.285.23:47:22.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:47:22.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:47:22.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:47:22.45#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:47:22.45#ibcon#first serial, iclass 33, count 0 2006.285.23:47:22.45#ibcon#enter sib2, iclass 33, count 0 2006.285.23:47:22.45#ibcon#flushed, iclass 33, count 0 2006.285.23:47:22.45#ibcon#about to write, iclass 33, count 0 2006.285.23:47:22.45#ibcon#wrote, iclass 33, count 0 2006.285.23:47:22.45#ibcon#about to read 3, iclass 33, count 0 2006.285.23:47:22.47#ibcon#read 3, iclass 33, count 0 2006.285.23:47:22.47#ibcon#about to read 4, iclass 33, count 0 2006.285.23:47:22.47#ibcon#read 4, iclass 33, count 0 2006.285.23:47:22.47#ibcon#about to read 5, iclass 33, count 0 2006.285.23:47:22.47#ibcon#read 5, iclass 33, count 0 2006.285.23:47:22.47#ibcon#about to read 6, iclass 33, count 0 2006.285.23:47:22.47#ibcon#read 6, iclass 33, count 0 2006.285.23:47:22.47#ibcon#end of sib2, iclass 33, count 0 2006.285.23:47:22.47#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:47:22.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:47:22.47#ibcon#[25=BW32\r\n] 2006.285.23:47:22.47#ibcon#*before write, iclass 33, count 0 2006.285.23:47:22.47#ibcon#enter sib2, iclass 33, count 0 2006.285.23:47:22.47#ibcon#flushed, iclass 33, count 0 2006.285.23:47:22.47#ibcon#about to write, iclass 33, count 0 2006.285.23:47:22.47#ibcon#wrote, iclass 33, count 0 2006.285.23:47:22.47#ibcon#about to read 3, iclass 33, count 0 2006.285.23:47:22.50#ibcon#read 3, iclass 33, count 0 2006.285.23:47:22.50#ibcon#about to read 4, iclass 33, count 0 2006.285.23:47:22.50#ibcon#read 4, iclass 33, count 0 2006.285.23:47:22.50#ibcon#about to read 5, iclass 33, count 0 2006.285.23:47:22.50#ibcon#read 5, iclass 33, count 0 2006.285.23:47:22.50#ibcon#about to read 6, iclass 33, count 0 2006.285.23:47:22.50#ibcon#read 6, iclass 33, count 0 2006.285.23:47:22.50#ibcon#end of sib2, iclass 33, count 0 2006.285.23:47:22.50#ibcon#*after write, iclass 33, count 0 2006.285.23:47:22.50#ibcon#*before return 0, iclass 33, count 0 2006.285.23:47:22.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:47:22.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.285.23:47:22.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:47:22.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:47:22.50$vck44/vbbw=wide 2006.285.23:47:22.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.23:47:22.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.23:47:22.50#ibcon#ireg 8 cls_cnt 0 2006.285.23:47:22.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:47:22.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:47:22.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:47:22.57#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:47:22.57#ibcon#first serial, iclass 35, count 0 2006.285.23:47:22.57#ibcon#enter sib2, iclass 35, count 0 2006.285.23:47:22.57#ibcon#flushed, iclass 35, count 0 2006.285.23:47:22.57#ibcon#about to write, iclass 35, count 0 2006.285.23:47:22.57#ibcon#wrote, iclass 35, count 0 2006.285.23:47:22.57#ibcon#about to read 3, iclass 35, count 0 2006.285.23:47:22.59#ibcon#read 3, iclass 35, count 0 2006.285.23:47:22.59#ibcon#about to read 4, iclass 35, count 0 2006.285.23:47:22.59#ibcon#read 4, iclass 35, count 0 2006.285.23:47:22.59#ibcon#about to read 5, iclass 35, count 0 2006.285.23:47:22.59#ibcon#read 5, iclass 35, count 0 2006.285.23:47:22.59#ibcon#about to read 6, iclass 35, count 0 2006.285.23:47:22.59#ibcon#read 6, iclass 35, count 0 2006.285.23:47:22.59#ibcon#end of sib2, iclass 35, count 0 2006.285.23:47:22.59#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:47:22.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:47:22.59#ibcon#[27=BW32\r\n] 2006.285.23:47:22.59#ibcon#*before write, iclass 35, count 0 2006.285.23:47:22.59#ibcon#enter sib2, iclass 35, count 0 2006.285.23:47:22.59#ibcon#flushed, iclass 35, count 0 2006.285.23:47:22.59#ibcon#about to write, iclass 35, count 0 2006.285.23:47:22.59#ibcon#wrote, iclass 35, count 0 2006.285.23:47:22.59#ibcon#about to read 3, iclass 35, count 0 2006.285.23:47:22.62#ibcon#read 3, iclass 35, count 0 2006.285.23:47:22.62#ibcon#about to read 4, iclass 35, count 0 2006.285.23:47:22.62#ibcon#read 4, iclass 35, count 0 2006.285.23:47:22.62#ibcon#about to read 5, iclass 35, count 0 2006.285.23:47:22.62#ibcon#read 5, iclass 35, count 0 2006.285.23:47:22.62#ibcon#about to read 6, iclass 35, count 0 2006.285.23:47:22.62#ibcon#read 6, iclass 35, count 0 2006.285.23:47:22.62#ibcon#end of sib2, iclass 35, count 0 2006.285.23:47:22.62#ibcon#*after write, iclass 35, count 0 2006.285.23:47:22.62#ibcon#*before return 0, iclass 35, count 0 2006.285.23:47:22.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:47:22.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:47:22.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:47:22.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:47:22.62$setupk4/ifdk4 2006.285.23:47:22.62$ifdk4/lo= 2006.285.23:47:22.62$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:47:22.63$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:47:22.63$ifdk4/patch= 2006.285.23:47:22.63$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:47:22.63$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:47:22.63$setupk4/!*+20s 2006.285.23:47:29.30#abcon#<5=/03 3.8 8.1 19.52 871016.5\r\n> 2006.285.23:47:29.32#abcon#{5=INTERFACE CLEAR} 2006.285.23:47:29.38#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:47:37.14$setupk4/"tpicd 2006.285.23:47:37.14$setupk4/echo=off 2006.285.23:47:37.14$setupk4/xlog=off 2006.285.23:47:37.14:!2006.285.23:49:44 2006.285.23:47:47.14#trakl#Source acquired 2006.285.23:47:48.14#flagr#flagr/antenna,acquired 2006.285.23:49:44.00:preob 2006.285.23:49:44.14/onsource/TRACKING 2006.285.23:49:44.14:!2006.285.23:49:54 2006.285.23:49:54.00:"tape 2006.285.23:49:54.00:"st=record 2006.285.23:49:54.00:data_valid=on 2006.285.23:49:54.00:midob 2006.285.23:49:54.13/onsource/TRACKING 2006.285.23:49:54.13/wx/19.53,1016.6,88 2006.285.23:49:54.23/cable/+6.5094E-03 2006.285.23:49:55.32/va/01,07,usb,yes,31,34 2006.285.23:49:55.32/va/02,06,usb,yes,32,32 2006.285.23:49:55.32/va/03,07,usb,yes,31,33 2006.285.23:49:55.32/va/04,06,usb,yes,32,34 2006.285.23:49:55.32/va/05,03,usb,yes,32,32 2006.285.23:49:55.32/va/06,04,usb,yes,29,28 2006.285.23:49:55.32/va/07,04,usb,yes,29,30 2006.285.23:49:55.32/va/08,03,usb,yes,30,37 2006.285.23:49:55.55/valo/01,524.99,yes,locked 2006.285.23:49:55.55/valo/02,534.99,yes,locked 2006.285.23:49:55.55/valo/03,564.99,yes,locked 2006.285.23:49:55.55/valo/04,624.99,yes,locked 2006.285.23:49:55.55/valo/05,734.99,yes,locked 2006.285.23:49:55.55/valo/06,814.99,yes,locked 2006.285.23:49:55.55/valo/07,864.99,yes,locked 2006.285.23:49:55.55/valo/08,884.99,yes,locked 2006.285.23:49:56.64/vb/01,04,usb,yes,30,28 2006.285.23:49:56.64/vb/02,05,usb,yes,28,28 2006.285.23:49:56.64/vb/03,04,usb,yes,29,32 2006.285.23:49:56.64/vb/04,05,usb,yes,29,28 2006.285.23:49:56.64/vb/05,04,usb,yes,26,28 2006.285.23:49:56.64/vb/06,03,usb,yes,37,33 2006.285.23:49:56.64/vb/07,04,usb,yes,30,30 2006.285.23:49:56.64/vb/08,04,usb,yes,27,30 2006.285.23:49:56.87/vblo/01,629.99,yes,locked 2006.285.23:49:56.87/vblo/02,634.99,yes,locked 2006.285.23:49:56.87/vblo/03,649.99,yes,locked 2006.285.23:49:56.87/vblo/04,679.99,yes,locked 2006.285.23:49:56.87/vblo/05,709.99,yes,locked 2006.285.23:49:56.87/vblo/06,719.99,yes,locked 2006.285.23:49:56.87/vblo/07,734.99,yes,locked 2006.285.23:49:56.87/vblo/08,744.99,yes,locked 2006.285.23:49:57.02/vabw/8 2006.285.23:49:57.17/vbbw/8 2006.285.23:49:57.26/xfe/off,on,12.0 2006.285.23:49:57.63/ifatt/23,28,28,28 2006.285.23:49:58.07/fmout-gps/S +2.72E-07 2006.285.23:49:58.09:!2006.285.23:53:14 2006.285.23:53:14.01:data_valid=off 2006.285.23:53:14.01:"et 2006.285.23:53:14.01:!+3s 2006.285.23:53:17.02:"tape 2006.285.23:53:17.02:postob 2006.285.23:53:17.18/cable/+6.5080E-03 2006.285.23:53:17.18/wx/19.56,1016.6,87 2006.285.23:53:17.24/fmout-gps/S +2.72E-07 2006.285.23:53:17.24:scan_name=285-2356,jd0610,60 2006.285.23:53:17.24:source=1611+343,161341.06,341247.9,2000.0,cw 2006.285.23:53:18.14#flagr#flagr/antenna,new-source 2006.285.23:53:18.14:checkk5 2006.285.23:53:18.57/chk_autoobs//k5ts1/ autoobs is running! 2006.285.23:53:19.16/chk_autoobs//k5ts2/ autoobs is running! 2006.285.23:53:19.59/chk_autoobs//k5ts3/ autoobs is running! 2006.285.23:53:19.98/chk_autoobs//k5ts4/ autoobs is running! 2006.285.23:53:20.38/chk_obsdata//k5ts1/T2852349??a.dat file size is correct (nominal:800MB, actual:796MB). 2006.285.23:53:20.76/chk_obsdata//k5ts2/T2852349??b.dat file size is correct (nominal:800MB, actual:796MB). 2006.285.23:53:21.17/chk_obsdata//k5ts3/T2852349??c.dat file size is correct (nominal:800MB, actual:796MB). 2006.285.23:53:21.57/chk_obsdata//k5ts4/T2852349??d.dat file size is correct (nominal:800MB, actual:796MB). 2006.285.23:53:22.36/k5log//k5ts1_log_newline 2006.285.23:53:23.09/k5log//k5ts2_log_newline 2006.285.23:53:23.86/k5log//k5ts3_log_newline 2006.285.23:53:24.76/k5log//k5ts4_log_newline 2006.285.23:53:24.78/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.23:53:24.78:setupk4=1 2006.285.23:53:24.78$setupk4/echo=on 2006.285.23:53:24.78$setupk4/pcalon 2006.285.23:53:24.78$pcalon/"no phase cal control is implemented here 2006.285.23:53:24.78$setupk4/"tpicd=stop 2006.285.23:53:24.78$setupk4/"rec=synch_on 2006.285.23:53:24.78$setupk4/"rec_mode=128 2006.285.23:53:24.78$setupk4/!* 2006.285.23:53:24.78$setupk4/recpk4 2006.285.23:53:24.78$recpk4/recpatch= 2006.285.23:53:24.78$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.23:53:24.78$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.23:53:24.78$setupk4/vck44 2006.285.23:53:24.78$vck44/valo=1,524.99 2006.285.23:53:24.79#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.23:53:24.79#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.23:53:24.79#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:24.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:53:24.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:53:24.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:53:24.79#ibcon#enter wrdev, iclass 36, count 0 2006.285.23:53:24.79#ibcon#first serial, iclass 36, count 0 2006.285.23:53:24.79#ibcon#enter sib2, iclass 36, count 0 2006.285.23:53:24.79#ibcon#flushed, iclass 36, count 0 2006.285.23:53:24.79#ibcon#about to write, iclass 36, count 0 2006.285.23:53:24.79#ibcon#wrote, iclass 36, count 0 2006.285.23:53:24.79#ibcon#about to read 3, iclass 36, count 0 2006.285.23:53:24.80#ibcon#read 3, iclass 36, count 0 2006.285.23:53:24.80#ibcon#about to read 4, iclass 36, count 0 2006.285.23:53:24.80#ibcon#read 4, iclass 36, count 0 2006.285.23:53:24.80#ibcon#about to read 5, iclass 36, count 0 2006.285.23:53:24.80#ibcon#read 5, iclass 36, count 0 2006.285.23:53:24.80#ibcon#about to read 6, iclass 36, count 0 2006.285.23:53:24.80#ibcon#read 6, iclass 36, count 0 2006.285.23:53:24.80#ibcon#end of sib2, iclass 36, count 0 2006.285.23:53:24.80#ibcon#*mode == 0, iclass 36, count 0 2006.285.23:53:24.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.23:53:24.80#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.23:53:24.80#ibcon#*before write, iclass 36, count 0 2006.285.23:53:24.80#ibcon#enter sib2, iclass 36, count 0 2006.285.23:53:24.80#ibcon#flushed, iclass 36, count 0 2006.285.23:53:24.80#ibcon#about to write, iclass 36, count 0 2006.285.23:53:24.80#ibcon#wrote, iclass 36, count 0 2006.285.23:53:24.80#ibcon#about to read 3, iclass 36, count 0 2006.285.23:53:24.85#ibcon#read 3, iclass 36, count 0 2006.285.23:53:24.85#ibcon#about to read 4, iclass 36, count 0 2006.285.23:53:24.85#ibcon#read 4, iclass 36, count 0 2006.285.23:53:24.85#ibcon#about to read 5, iclass 36, count 0 2006.285.23:53:24.85#ibcon#read 5, iclass 36, count 0 2006.285.23:53:24.85#ibcon#about to read 6, iclass 36, count 0 2006.285.23:53:24.85#ibcon#read 6, iclass 36, count 0 2006.285.23:53:24.85#ibcon#end of sib2, iclass 36, count 0 2006.285.23:53:24.85#ibcon#*after write, iclass 36, count 0 2006.285.23:53:24.85#ibcon#*before return 0, iclass 36, count 0 2006.285.23:53:24.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:53:24.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:53:24.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.23:53:24.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.23:53:24.85$vck44/va=1,7 2006.285.23:53:24.85#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.23:53:24.85#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.23:53:24.86#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:24.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:53:24.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:53:24.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:53:24.86#ibcon#enter wrdev, iclass 38, count 2 2006.285.23:53:24.86#ibcon#first serial, iclass 38, count 2 2006.285.23:53:24.86#ibcon#enter sib2, iclass 38, count 2 2006.285.23:53:24.86#ibcon#flushed, iclass 38, count 2 2006.285.23:53:24.86#ibcon#about to write, iclass 38, count 2 2006.285.23:53:24.86#ibcon#wrote, iclass 38, count 2 2006.285.23:53:24.86#ibcon#about to read 3, iclass 38, count 2 2006.285.23:53:24.87#ibcon#read 3, iclass 38, count 2 2006.285.23:53:24.87#ibcon#about to read 4, iclass 38, count 2 2006.285.23:53:24.87#ibcon#read 4, iclass 38, count 2 2006.285.23:53:24.87#ibcon#about to read 5, iclass 38, count 2 2006.285.23:53:24.87#ibcon#read 5, iclass 38, count 2 2006.285.23:53:24.87#ibcon#about to read 6, iclass 38, count 2 2006.285.23:53:24.87#ibcon#read 6, iclass 38, count 2 2006.285.23:53:24.87#ibcon#end of sib2, iclass 38, count 2 2006.285.23:53:24.87#ibcon#*mode == 0, iclass 38, count 2 2006.285.23:53:24.87#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.23:53:24.87#ibcon#[25=AT01-07\r\n] 2006.285.23:53:24.87#ibcon#*before write, iclass 38, count 2 2006.285.23:53:24.87#ibcon#enter sib2, iclass 38, count 2 2006.285.23:53:24.87#ibcon#flushed, iclass 38, count 2 2006.285.23:53:24.87#ibcon#about to write, iclass 38, count 2 2006.285.23:53:24.87#ibcon#wrote, iclass 38, count 2 2006.285.23:53:24.87#ibcon#about to read 3, iclass 38, count 2 2006.285.23:53:24.90#ibcon#read 3, iclass 38, count 2 2006.285.23:53:24.90#ibcon#about to read 4, iclass 38, count 2 2006.285.23:53:24.90#ibcon#read 4, iclass 38, count 2 2006.285.23:53:24.90#ibcon#about to read 5, iclass 38, count 2 2006.285.23:53:24.90#ibcon#read 5, iclass 38, count 2 2006.285.23:53:24.90#ibcon#about to read 6, iclass 38, count 2 2006.285.23:53:24.90#ibcon#read 6, iclass 38, count 2 2006.285.23:53:24.90#ibcon#end of sib2, iclass 38, count 2 2006.285.23:53:24.90#ibcon#*after write, iclass 38, count 2 2006.285.23:53:24.90#ibcon#*before return 0, iclass 38, count 2 2006.285.23:53:24.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:53:24.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:53:24.90#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.23:53:24.90#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:24.90#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:53:25.02#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:53:25.02#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:53:25.02#ibcon#enter wrdev, iclass 38, count 0 2006.285.23:53:25.02#ibcon#first serial, iclass 38, count 0 2006.285.23:53:25.02#ibcon#enter sib2, iclass 38, count 0 2006.285.23:53:25.02#ibcon#flushed, iclass 38, count 0 2006.285.23:53:25.02#ibcon#about to write, iclass 38, count 0 2006.285.23:53:25.02#ibcon#wrote, iclass 38, count 0 2006.285.23:53:25.02#ibcon#about to read 3, iclass 38, count 0 2006.285.23:53:25.04#ibcon#read 3, iclass 38, count 0 2006.285.23:53:25.04#ibcon#about to read 4, iclass 38, count 0 2006.285.23:53:25.04#ibcon#read 4, iclass 38, count 0 2006.285.23:53:25.04#ibcon#about to read 5, iclass 38, count 0 2006.285.23:53:25.04#ibcon#read 5, iclass 38, count 0 2006.285.23:53:25.04#ibcon#about to read 6, iclass 38, count 0 2006.285.23:53:25.04#ibcon#read 6, iclass 38, count 0 2006.285.23:53:25.04#ibcon#end of sib2, iclass 38, count 0 2006.285.23:53:25.04#ibcon#*mode == 0, iclass 38, count 0 2006.285.23:53:25.04#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.23:53:25.04#ibcon#[25=USB\r\n] 2006.285.23:53:25.04#ibcon#*before write, iclass 38, count 0 2006.285.23:53:25.04#ibcon#enter sib2, iclass 38, count 0 2006.285.23:53:25.04#ibcon#flushed, iclass 38, count 0 2006.285.23:53:25.04#ibcon#about to write, iclass 38, count 0 2006.285.23:53:25.04#ibcon#wrote, iclass 38, count 0 2006.285.23:53:25.04#ibcon#about to read 3, iclass 38, count 0 2006.285.23:53:25.07#ibcon#read 3, iclass 38, count 0 2006.285.23:53:25.07#ibcon#about to read 4, iclass 38, count 0 2006.285.23:53:25.07#ibcon#read 4, iclass 38, count 0 2006.285.23:53:25.07#ibcon#about to read 5, iclass 38, count 0 2006.285.23:53:25.07#ibcon#read 5, iclass 38, count 0 2006.285.23:53:25.07#ibcon#about to read 6, iclass 38, count 0 2006.285.23:53:25.07#ibcon#read 6, iclass 38, count 0 2006.285.23:53:25.07#ibcon#end of sib2, iclass 38, count 0 2006.285.23:53:25.07#ibcon#*after write, iclass 38, count 0 2006.285.23:53:25.07#ibcon#*before return 0, iclass 38, count 0 2006.285.23:53:25.07#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:53:25.07#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:53:25.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.23:53:25.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.23:53:25.07$vck44/valo=2,534.99 2006.285.23:53:25.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.23:53:25.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.23:53:25.07#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:25.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:53:25.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:53:25.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:53:25.07#ibcon#enter wrdev, iclass 40, count 0 2006.285.23:53:25.07#ibcon#first serial, iclass 40, count 0 2006.285.23:53:25.07#ibcon#enter sib2, iclass 40, count 0 2006.285.23:53:25.07#ibcon#flushed, iclass 40, count 0 2006.285.23:53:25.07#ibcon#about to write, iclass 40, count 0 2006.285.23:53:25.07#ibcon#wrote, iclass 40, count 0 2006.285.23:53:25.07#ibcon#about to read 3, iclass 40, count 0 2006.285.23:53:25.09#ibcon#read 3, iclass 40, count 0 2006.285.23:53:25.09#ibcon#about to read 4, iclass 40, count 0 2006.285.23:53:25.09#ibcon#read 4, iclass 40, count 0 2006.285.23:53:25.09#ibcon#about to read 5, iclass 40, count 0 2006.285.23:53:25.09#ibcon#read 5, iclass 40, count 0 2006.285.23:53:25.09#ibcon#about to read 6, iclass 40, count 0 2006.285.23:53:25.09#ibcon#read 6, iclass 40, count 0 2006.285.23:53:25.09#ibcon#end of sib2, iclass 40, count 0 2006.285.23:53:25.09#ibcon#*mode == 0, iclass 40, count 0 2006.285.23:53:25.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.23:53:25.09#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.23:53:25.09#ibcon#*before write, iclass 40, count 0 2006.285.23:53:25.09#ibcon#enter sib2, iclass 40, count 0 2006.285.23:53:25.09#ibcon#flushed, iclass 40, count 0 2006.285.23:53:25.09#ibcon#about to write, iclass 40, count 0 2006.285.23:53:25.09#ibcon#wrote, iclass 40, count 0 2006.285.23:53:25.09#ibcon#about to read 3, iclass 40, count 0 2006.285.23:53:25.13#ibcon#read 3, iclass 40, count 0 2006.285.23:53:25.13#ibcon#about to read 4, iclass 40, count 0 2006.285.23:53:25.13#ibcon#read 4, iclass 40, count 0 2006.285.23:53:25.13#ibcon#about to read 5, iclass 40, count 0 2006.285.23:53:25.13#ibcon#read 5, iclass 40, count 0 2006.285.23:53:25.13#ibcon#about to read 6, iclass 40, count 0 2006.285.23:53:25.13#ibcon#read 6, iclass 40, count 0 2006.285.23:53:25.13#ibcon#end of sib2, iclass 40, count 0 2006.285.23:53:25.13#ibcon#*after write, iclass 40, count 0 2006.285.23:53:25.13#ibcon#*before return 0, iclass 40, count 0 2006.285.23:53:25.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:53:25.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:53:25.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.23:53:25.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.23:53:25.13$vck44/va=2,6 2006.285.23:53:25.13#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.23:53:25.13#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.23:53:25.13#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:25.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:53:25.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:53:25.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:53:25.19#ibcon#enter wrdev, iclass 4, count 2 2006.285.23:53:25.19#ibcon#first serial, iclass 4, count 2 2006.285.23:53:25.19#ibcon#enter sib2, iclass 4, count 2 2006.285.23:53:25.19#ibcon#flushed, iclass 4, count 2 2006.285.23:53:25.19#ibcon#about to write, iclass 4, count 2 2006.285.23:53:25.19#ibcon#wrote, iclass 4, count 2 2006.285.23:53:25.19#ibcon#about to read 3, iclass 4, count 2 2006.285.23:53:25.21#ibcon#read 3, iclass 4, count 2 2006.285.23:53:25.21#ibcon#about to read 4, iclass 4, count 2 2006.285.23:53:25.21#ibcon#read 4, iclass 4, count 2 2006.285.23:53:25.21#ibcon#about to read 5, iclass 4, count 2 2006.285.23:53:25.21#ibcon#read 5, iclass 4, count 2 2006.285.23:53:25.21#ibcon#about to read 6, iclass 4, count 2 2006.285.23:53:25.21#ibcon#read 6, iclass 4, count 2 2006.285.23:53:25.21#ibcon#end of sib2, iclass 4, count 2 2006.285.23:53:25.21#ibcon#*mode == 0, iclass 4, count 2 2006.285.23:53:25.21#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.23:53:25.21#ibcon#[25=AT02-06\r\n] 2006.285.23:53:25.21#ibcon#*before write, iclass 4, count 2 2006.285.23:53:25.21#ibcon#enter sib2, iclass 4, count 2 2006.285.23:53:25.21#ibcon#flushed, iclass 4, count 2 2006.285.23:53:25.21#ibcon#about to write, iclass 4, count 2 2006.285.23:53:25.21#ibcon#wrote, iclass 4, count 2 2006.285.23:53:25.21#ibcon#about to read 3, iclass 4, count 2 2006.285.23:53:25.24#ibcon#read 3, iclass 4, count 2 2006.285.23:53:25.24#ibcon#about to read 4, iclass 4, count 2 2006.285.23:53:25.24#ibcon#read 4, iclass 4, count 2 2006.285.23:53:25.24#ibcon#about to read 5, iclass 4, count 2 2006.285.23:53:25.24#ibcon#read 5, iclass 4, count 2 2006.285.23:53:25.24#ibcon#about to read 6, iclass 4, count 2 2006.285.23:53:25.24#ibcon#read 6, iclass 4, count 2 2006.285.23:53:25.24#ibcon#end of sib2, iclass 4, count 2 2006.285.23:53:25.24#ibcon#*after write, iclass 4, count 2 2006.285.23:53:25.24#ibcon#*before return 0, iclass 4, count 2 2006.285.23:53:25.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:53:25.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:53:25.24#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.23:53:25.24#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:25.24#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:53:25.36#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:53:25.36#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:53:25.36#ibcon#enter wrdev, iclass 4, count 0 2006.285.23:53:25.36#ibcon#first serial, iclass 4, count 0 2006.285.23:53:25.36#ibcon#enter sib2, iclass 4, count 0 2006.285.23:53:25.36#ibcon#flushed, iclass 4, count 0 2006.285.23:53:25.36#ibcon#about to write, iclass 4, count 0 2006.285.23:53:25.36#ibcon#wrote, iclass 4, count 0 2006.285.23:53:25.36#ibcon#about to read 3, iclass 4, count 0 2006.285.23:53:25.38#ibcon#read 3, iclass 4, count 0 2006.285.23:53:25.38#ibcon#about to read 4, iclass 4, count 0 2006.285.23:53:25.38#ibcon#read 4, iclass 4, count 0 2006.285.23:53:25.38#ibcon#about to read 5, iclass 4, count 0 2006.285.23:53:25.38#ibcon#read 5, iclass 4, count 0 2006.285.23:53:25.38#ibcon#about to read 6, iclass 4, count 0 2006.285.23:53:25.38#ibcon#read 6, iclass 4, count 0 2006.285.23:53:25.38#ibcon#end of sib2, iclass 4, count 0 2006.285.23:53:25.38#ibcon#*mode == 0, iclass 4, count 0 2006.285.23:53:25.38#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.23:53:25.38#ibcon#[25=USB\r\n] 2006.285.23:53:25.38#ibcon#*before write, iclass 4, count 0 2006.285.23:53:25.38#ibcon#enter sib2, iclass 4, count 0 2006.285.23:53:25.38#ibcon#flushed, iclass 4, count 0 2006.285.23:53:25.38#ibcon#about to write, iclass 4, count 0 2006.285.23:53:25.38#ibcon#wrote, iclass 4, count 0 2006.285.23:53:25.38#ibcon#about to read 3, iclass 4, count 0 2006.285.23:53:25.41#ibcon#read 3, iclass 4, count 0 2006.285.23:53:25.41#ibcon#about to read 4, iclass 4, count 0 2006.285.23:53:25.41#ibcon#read 4, iclass 4, count 0 2006.285.23:53:25.41#ibcon#about to read 5, iclass 4, count 0 2006.285.23:53:25.41#ibcon#read 5, iclass 4, count 0 2006.285.23:53:25.41#ibcon#about to read 6, iclass 4, count 0 2006.285.23:53:25.41#ibcon#read 6, iclass 4, count 0 2006.285.23:53:25.41#ibcon#end of sib2, iclass 4, count 0 2006.285.23:53:25.41#ibcon#*after write, iclass 4, count 0 2006.285.23:53:25.41#ibcon#*before return 0, iclass 4, count 0 2006.285.23:53:25.41#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:53:25.41#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:53:25.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.23:53:25.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.23:53:25.41$vck44/valo=3,564.99 2006.285.23:53:25.41#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.23:53:25.41#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.23:53:25.41#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:25.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:53:25.41#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:53:25.41#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:53:25.41#ibcon#enter wrdev, iclass 6, count 0 2006.285.23:53:25.41#ibcon#first serial, iclass 6, count 0 2006.285.23:53:25.41#ibcon#enter sib2, iclass 6, count 0 2006.285.23:53:25.41#ibcon#flushed, iclass 6, count 0 2006.285.23:53:25.41#ibcon#about to write, iclass 6, count 0 2006.285.23:53:25.41#ibcon#wrote, iclass 6, count 0 2006.285.23:53:25.41#ibcon#about to read 3, iclass 6, count 0 2006.285.23:53:25.43#ibcon#read 3, iclass 6, count 0 2006.285.23:53:25.43#ibcon#about to read 4, iclass 6, count 0 2006.285.23:53:25.43#ibcon#read 4, iclass 6, count 0 2006.285.23:53:25.43#ibcon#about to read 5, iclass 6, count 0 2006.285.23:53:25.43#ibcon#read 5, iclass 6, count 0 2006.285.23:53:25.43#ibcon#about to read 6, iclass 6, count 0 2006.285.23:53:25.43#ibcon#read 6, iclass 6, count 0 2006.285.23:53:25.43#ibcon#end of sib2, iclass 6, count 0 2006.285.23:53:25.43#ibcon#*mode == 0, iclass 6, count 0 2006.285.23:53:25.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.23:53:25.43#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.23:53:25.43#ibcon#*before write, iclass 6, count 0 2006.285.23:53:25.43#ibcon#enter sib2, iclass 6, count 0 2006.285.23:53:25.43#ibcon#flushed, iclass 6, count 0 2006.285.23:53:25.43#ibcon#about to write, iclass 6, count 0 2006.285.23:53:25.43#ibcon#wrote, iclass 6, count 0 2006.285.23:53:25.43#ibcon#about to read 3, iclass 6, count 0 2006.285.23:53:25.47#ibcon#read 3, iclass 6, count 0 2006.285.23:53:25.47#ibcon#about to read 4, iclass 6, count 0 2006.285.23:53:25.47#ibcon#read 4, iclass 6, count 0 2006.285.23:53:25.47#ibcon#about to read 5, iclass 6, count 0 2006.285.23:53:25.47#ibcon#read 5, iclass 6, count 0 2006.285.23:53:25.47#ibcon#about to read 6, iclass 6, count 0 2006.285.23:53:25.47#ibcon#read 6, iclass 6, count 0 2006.285.23:53:25.47#ibcon#end of sib2, iclass 6, count 0 2006.285.23:53:25.47#ibcon#*after write, iclass 6, count 0 2006.285.23:53:25.47#ibcon#*before return 0, iclass 6, count 0 2006.285.23:53:25.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:53:25.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:53:25.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.23:53:25.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.23:53:25.47$vck44/va=3,7 2006.285.23:53:25.47#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.285.23:53:25.47#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.285.23:53:25.47#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:25.47#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:53:25.52#abcon#<5=/03 4.5 8.1 19.56 871016.6\r\n> 2006.285.23:53:25.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:53:25.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:53:25.53#ibcon#enter wrdev, iclass 11, count 2 2006.285.23:53:25.53#ibcon#first serial, iclass 11, count 2 2006.285.23:53:25.53#ibcon#enter sib2, iclass 11, count 2 2006.285.23:53:25.53#ibcon#flushed, iclass 11, count 2 2006.285.23:53:25.53#ibcon#about to write, iclass 11, count 2 2006.285.23:53:25.53#ibcon#wrote, iclass 11, count 2 2006.285.23:53:25.53#ibcon#about to read 3, iclass 11, count 2 2006.285.23:53:25.54#abcon#{5=INTERFACE CLEAR} 2006.285.23:53:25.55#ibcon#read 3, iclass 11, count 2 2006.285.23:53:25.55#ibcon#about to read 4, iclass 11, count 2 2006.285.23:53:25.55#ibcon#read 4, iclass 11, count 2 2006.285.23:53:25.55#ibcon#about to read 5, iclass 11, count 2 2006.285.23:53:25.55#ibcon#read 5, iclass 11, count 2 2006.285.23:53:25.55#ibcon#about to read 6, iclass 11, count 2 2006.285.23:53:25.55#ibcon#read 6, iclass 11, count 2 2006.285.23:53:25.55#ibcon#end of sib2, iclass 11, count 2 2006.285.23:53:25.55#ibcon#*mode == 0, iclass 11, count 2 2006.285.23:53:25.55#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.285.23:53:25.55#ibcon#[25=AT03-07\r\n] 2006.285.23:53:25.55#ibcon#*before write, iclass 11, count 2 2006.285.23:53:25.55#ibcon#enter sib2, iclass 11, count 2 2006.285.23:53:25.55#ibcon#flushed, iclass 11, count 2 2006.285.23:53:25.55#ibcon#about to write, iclass 11, count 2 2006.285.23:53:25.55#ibcon#wrote, iclass 11, count 2 2006.285.23:53:25.55#ibcon#about to read 3, iclass 11, count 2 2006.285.23:53:25.58#ibcon#read 3, iclass 11, count 2 2006.285.23:53:25.58#ibcon#about to read 4, iclass 11, count 2 2006.285.23:53:25.58#ibcon#read 4, iclass 11, count 2 2006.285.23:53:25.58#ibcon#about to read 5, iclass 11, count 2 2006.285.23:53:25.58#ibcon#read 5, iclass 11, count 2 2006.285.23:53:25.58#ibcon#about to read 6, iclass 11, count 2 2006.285.23:53:25.58#ibcon#read 6, iclass 11, count 2 2006.285.23:53:25.58#ibcon#end of sib2, iclass 11, count 2 2006.285.23:53:25.58#ibcon#*after write, iclass 11, count 2 2006.285.23:53:25.58#ibcon#*before return 0, iclass 11, count 2 2006.285.23:53:25.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:53:25.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.285.23:53:25.58#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.285.23:53:25.58#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:25.58#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:53:25.60#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:53:25.70#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:53:25.70#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:53:25.70#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:53:25.70#ibcon#first serial, iclass 11, count 0 2006.285.23:53:25.70#ibcon#enter sib2, iclass 11, count 0 2006.285.23:53:25.70#ibcon#flushed, iclass 11, count 0 2006.285.23:53:25.70#ibcon#about to write, iclass 11, count 0 2006.285.23:53:25.70#ibcon#wrote, iclass 11, count 0 2006.285.23:53:25.70#ibcon#about to read 3, iclass 11, count 0 2006.285.23:53:25.72#ibcon#read 3, iclass 11, count 0 2006.285.23:53:25.72#ibcon#about to read 4, iclass 11, count 0 2006.285.23:53:25.72#ibcon#read 4, iclass 11, count 0 2006.285.23:53:25.72#ibcon#about to read 5, iclass 11, count 0 2006.285.23:53:25.72#ibcon#read 5, iclass 11, count 0 2006.285.23:53:25.72#ibcon#about to read 6, iclass 11, count 0 2006.285.23:53:25.72#ibcon#read 6, iclass 11, count 0 2006.285.23:53:25.72#ibcon#end of sib2, iclass 11, count 0 2006.285.23:53:25.72#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:53:25.72#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:53:25.72#ibcon#[25=USB\r\n] 2006.285.23:53:25.72#ibcon#*before write, iclass 11, count 0 2006.285.23:53:25.72#ibcon#enter sib2, iclass 11, count 0 2006.285.23:53:25.72#ibcon#flushed, iclass 11, count 0 2006.285.23:53:25.72#ibcon#about to write, iclass 11, count 0 2006.285.23:53:25.72#ibcon#wrote, iclass 11, count 0 2006.285.23:53:25.72#ibcon#about to read 3, iclass 11, count 0 2006.285.23:53:25.75#ibcon#read 3, iclass 11, count 0 2006.285.23:53:25.75#ibcon#about to read 4, iclass 11, count 0 2006.285.23:53:25.75#ibcon#read 4, iclass 11, count 0 2006.285.23:53:25.75#ibcon#about to read 5, iclass 11, count 0 2006.285.23:53:25.75#ibcon#read 5, iclass 11, count 0 2006.285.23:53:25.75#ibcon#about to read 6, iclass 11, count 0 2006.285.23:53:25.75#ibcon#read 6, iclass 11, count 0 2006.285.23:53:25.75#ibcon#end of sib2, iclass 11, count 0 2006.285.23:53:25.75#ibcon#*after write, iclass 11, count 0 2006.285.23:53:25.75#ibcon#*before return 0, iclass 11, count 0 2006.285.23:53:25.75#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:53:25.75#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.285.23:53:25.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:53:25.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:53:25.75$vck44/valo=4,624.99 2006.285.23:53:25.75#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.23:53:25.75#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.23:53:25.75#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:25.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:53:25.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:53:25.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:53:25.75#ibcon#enter wrdev, iclass 16, count 0 2006.285.23:53:25.75#ibcon#first serial, iclass 16, count 0 2006.285.23:53:25.75#ibcon#enter sib2, iclass 16, count 0 2006.285.23:53:25.75#ibcon#flushed, iclass 16, count 0 2006.285.23:53:25.75#ibcon#about to write, iclass 16, count 0 2006.285.23:53:25.75#ibcon#wrote, iclass 16, count 0 2006.285.23:53:25.75#ibcon#about to read 3, iclass 16, count 0 2006.285.23:53:25.77#ibcon#read 3, iclass 16, count 0 2006.285.23:53:25.77#ibcon#about to read 4, iclass 16, count 0 2006.285.23:53:25.77#ibcon#read 4, iclass 16, count 0 2006.285.23:53:25.77#ibcon#about to read 5, iclass 16, count 0 2006.285.23:53:25.77#ibcon#read 5, iclass 16, count 0 2006.285.23:53:25.77#ibcon#about to read 6, iclass 16, count 0 2006.285.23:53:25.77#ibcon#read 6, iclass 16, count 0 2006.285.23:53:25.77#ibcon#end of sib2, iclass 16, count 0 2006.285.23:53:25.77#ibcon#*mode == 0, iclass 16, count 0 2006.285.23:53:25.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.23:53:25.77#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.23:53:25.77#ibcon#*before write, iclass 16, count 0 2006.285.23:53:25.77#ibcon#enter sib2, iclass 16, count 0 2006.285.23:53:25.77#ibcon#flushed, iclass 16, count 0 2006.285.23:53:25.77#ibcon#about to write, iclass 16, count 0 2006.285.23:53:25.77#ibcon#wrote, iclass 16, count 0 2006.285.23:53:25.77#ibcon#about to read 3, iclass 16, count 0 2006.285.23:53:25.81#ibcon#read 3, iclass 16, count 0 2006.285.23:53:25.81#ibcon#about to read 4, iclass 16, count 0 2006.285.23:53:25.81#ibcon#read 4, iclass 16, count 0 2006.285.23:53:25.81#ibcon#about to read 5, iclass 16, count 0 2006.285.23:53:25.81#ibcon#read 5, iclass 16, count 0 2006.285.23:53:25.81#ibcon#about to read 6, iclass 16, count 0 2006.285.23:53:25.81#ibcon#read 6, iclass 16, count 0 2006.285.23:53:25.81#ibcon#end of sib2, iclass 16, count 0 2006.285.23:53:25.81#ibcon#*after write, iclass 16, count 0 2006.285.23:53:25.81#ibcon#*before return 0, iclass 16, count 0 2006.285.23:53:25.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:53:25.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:53:25.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.23:53:25.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.23:53:25.81$vck44/va=4,6 2006.285.23:53:25.81#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.23:53:25.81#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.23:53:25.81#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:25.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:53:25.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:53:25.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:53:25.87#ibcon#enter wrdev, iclass 18, count 2 2006.285.23:53:25.87#ibcon#first serial, iclass 18, count 2 2006.285.23:53:25.87#ibcon#enter sib2, iclass 18, count 2 2006.285.23:53:25.87#ibcon#flushed, iclass 18, count 2 2006.285.23:53:25.87#ibcon#about to write, iclass 18, count 2 2006.285.23:53:25.87#ibcon#wrote, iclass 18, count 2 2006.285.23:53:25.87#ibcon#about to read 3, iclass 18, count 2 2006.285.23:53:25.89#ibcon#read 3, iclass 18, count 2 2006.285.23:53:25.89#ibcon#about to read 4, iclass 18, count 2 2006.285.23:53:25.89#ibcon#read 4, iclass 18, count 2 2006.285.23:53:25.89#ibcon#about to read 5, iclass 18, count 2 2006.285.23:53:25.89#ibcon#read 5, iclass 18, count 2 2006.285.23:53:25.89#ibcon#about to read 6, iclass 18, count 2 2006.285.23:53:25.89#ibcon#read 6, iclass 18, count 2 2006.285.23:53:25.89#ibcon#end of sib2, iclass 18, count 2 2006.285.23:53:25.89#ibcon#*mode == 0, iclass 18, count 2 2006.285.23:53:25.89#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.23:53:25.89#ibcon#[25=AT04-06\r\n] 2006.285.23:53:25.89#ibcon#*before write, iclass 18, count 2 2006.285.23:53:25.89#ibcon#enter sib2, iclass 18, count 2 2006.285.23:53:25.89#ibcon#flushed, iclass 18, count 2 2006.285.23:53:25.89#ibcon#about to write, iclass 18, count 2 2006.285.23:53:25.89#ibcon#wrote, iclass 18, count 2 2006.285.23:53:25.89#ibcon#about to read 3, iclass 18, count 2 2006.285.23:53:25.92#ibcon#read 3, iclass 18, count 2 2006.285.23:53:25.92#ibcon#about to read 4, iclass 18, count 2 2006.285.23:53:25.92#ibcon#read 4, iclass 18, count 2 2006.285.23:53:25.92#ibcon#about to read 5, iclass 18, count 2 2006.285.23:53:25.92#ibcon#read 5, iclass 18, count 2 2006.285.23:53:25.92#ibcon#about to read 6, iclass 18, count 2 2006.285.23:53:25.92#ibcon#read 6, iclass 18, count 2 2006.285.23:53:25.92#ibcon#end of sib2, iclass 18, count 2 2006.285.23:53:25.92#ibcon#*after write, iclass 18, count 2 2006.285.23:53:25.92#ibcon#*before return 0, iclass 18, count 2 2006.285.23:53:25.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:53:25.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:53:25.92#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.23:53:25.92#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:25.92#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:53:26.04#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:53:26.04#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:53:26.04#ibcon#enter wrdev, iclass 18, count 0 2006.285.23:53:26.04#ibcon#first serial, iclass 18, count 0 2006.285.23:53:26.04#ibcon#enter sib2, iclass 18, count 0 2006.285.23:53:26.04#ibcon#flushed, iclass 18, count 0 2006.285.23:53:26.04#ibcon#about to write, iclass 18, count 0 2006.285.23:53:26.04#ibcon#wrote, iclass 18, count 0 2006.285.23:53:26.04#ibcon#about to read 3, iclass 18, count 0 2006.285.23:53:26.06#ibcon#read 3, iclass 18, count 0 2006.285.23:53:26.06#ibcon#about to read 4, iclass 18, count 0 2006.285.23:53:26.06#ibcon#read 4, iclass 18, count 0 2006.285.23:53:26.06#ibcon#about to read 5, iclass 18, count 0 2006.285.23:53:26.06#ibcon#read 5, iclass 18, count 0 2006.285.23:53:26.06#ibcon#about to read 6, iclass 18, count 0 2006.285.23:53:26.06#ibcon#read 6, iclass 18, count 0 2006.285.23:53:26.06#ibcon#end of sib2, iclass 18, count 0 2006.285.23:53:26.06#ibcon#*mode == 0, iclass 18, count 0 2006.285.23:53:26.06#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.23:53:26.06#ibcon#[25=USB\r\n] 2006.285.23:53:26.06#ibcon#*before write, iclass 18, count 0 2006.285.23:53:26.06#ibcon#enter sib2, iclass 18, count 0 2006.285.23:53:26.06#ibcon#flushed, iclass 18, count 0 2006.285.23:53:26.06#ibcon#about to write, iclass 18, count 0 2006.285.23:53:26.06#ibcon#wrote, iclass 18, count 0 2006.285.23:53:26.06#ibcon#about to read 3, iclass 18, count 0 2006.285.23:53:26.09#ibcon#read 3, iclass 18, count 0 2006.285.23:53:26.09#ibcon#about to read 4, iclass 18, count 0 2006.285.23:53:26.09#ibcon#read 4, iclass 18, count 0 2006.285.23:53:26.09#ibcon#about to read 5, iclass 18, count 0 2006.285.23:53:26.09#ibcon#read 5, iclass 18, count 0 2006.285.23:53:26.09#ibcon#about to read 6, iclass 18, count 0 2006.285.23:53:26.09#ibcon#read 6, iclass 18, count 0 2006.285.23:53:26.09#ibcon#end of sib2, iclass 18, count 0 2006.285.23:53:26.09#ibcon#*after write, iclass 18, count 0 2006.285.23:53:26.09#ibcon#*before return 0, iclass 18, count 0 2006.285.23:53:26.09#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:53:26.09#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:53:26.09#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.23:53:26.09#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.23:53:26.09$vck44/valo=5,734.99 2006.285.23:53:26.09#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.23:53:26.09#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.23:53:26.09#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:26.09#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:53:26.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:53:26.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:53:26.09#ibcon#enter wrdev, iclass 20, count 0 2006.285.23:53:26.09#ibcon#first serial, iclass 20, count 0 2006.285.23:53:26.09#ibcon#enter sib2, iclass 20, count 0 2006.285.23:53:26.09#ibcon#flushed, iclass 20, count 0 2006.285.23:53:26.09#ibcon#about to write, iclass 20, count 0 2006.285.23:53:26.09#ibcon#wrote, iclass 20, count 0 2006.285.23:53:26.09#ibcon#about to read 3, iclass 20, count 0 2006.285.23:53:26.11#ibcon#read 3, iclass 20, count 0 2006.285.23:53:26.11#ibcon#about to read 4, iclass 20, count 0 2006.285.23:53:26.11#ibcon#read 4, iclass 20, count 0 2006.285.23:53:26.11#ibcon#about to read 5, iclass 20, count 0 2006.285.23:53:26.11#ibcon#read 5, iclass 20, count 0 2006.285.23:53:26.11#ibcon#about to read 6, iclass 20, count 0 2006.285.23:53:26.11#ibcon#read 6, iclass 20, count 0 2006.285.23:53:26.11#ibcon#end of sib2, iclass 20, count 0 2006.285.23:53:26.11#ibcon#*mode == 0, iclass 20, count 0 2006.285.23:53:26.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.23:53:26.11#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.23:53:26.11#ibcon#*before write, iclass 20, count 0 2006.285.23:53:26.11#ibcon#enter sib2, iclass 20, count 0 2006.285.23:53:26.11#ibcon#flushed, iclass 20, count 0 2006.285.23:53:26.11#ibcon#about to write, iclass 20, count 0 2006.285.23:53:26.11#ibcon#wrote, iclass 20, count 0 2006.285.23:53:26.11#ibcon#about to read 3, iclass 20, count 0 2006.285.23:53:26.15#ibcon#read 3, iclass 20, count 0 2006.285.23:53:26.15#ibcon#about to read 4, iclass 20, count 0 2006.285.23:53:26.15#ibcon#read 4, iclass 20, count 0 2006.285.23:53:26.15#ibcon#about to read 5, iclass 20, count 0 2006.285.23:53:26.15#ibcon#read 5, iclass 20, count 0 2006.285.23:53:26.15#ibcon#about to read 6, iclass 20, count 0 2006.285.23:53:26.15#ibcon#read 6, iclass 20, count 0 2006.285.23:53:26.15#ibcon#end of sib2, iclass 20, count 0 2006.285.23:53:26.15#ibcon#*after write, iclass 20, count 0 2006.285.23:53:26.15#ibcon#*before return 0, iclass 20, count 0 2006.285.23:53:26.15#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:53:26.15#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:53:26.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.23:53:26.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.23:53:26.15$vck44/va=5,3 2006.285.23:53:26.15#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.23:53:26.15#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.23:53:26.15#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:26.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:53:26.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:53:26.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:53:26.21#ibcon#enter wrdev, iclass 22, count 2 2006.285.23:53:26.21#ibcon#first serial, iclass 22, count 2 2006.285.23:53:26.21#ibcon#enter sib2, iclass 22, count 2 2006.285.23:53:26.21#ibcon#flushed, iclass 22, count 2 2006.285.23:53:26.21#ibcon#about to write, iclass 22, count 2 2006.285.23:53:26.21#ibcon#wrote, iclass 22, count 2 2006.285.23:53:26.21#ibcon#about to read 3, iclass 22, count 2 2006.285.23:53:26.23#ibcon#read 3, iclass 22, count 2 2006.285.23:53:26.23#ibcon#about to read 4, iclass 22, count 2 2006.285.23:53:26.23#ibcon#read 4, iclass 22, count 2 2006.285.23:53:26.23#ibcon#about to read 5, iclass 22, count 2 2006.285.23:53:26.23#ibcon#read 5, iclass 22, count 2 2006.285.23:53:26.23#ibcon#about to read 6, iclass 22, count 2 2006.285.23:53:26.23#ibcon#read 6, iclass 22, count 2 2006.285.23:53:26.23#ibcon#end of sib2, iclass 22, count 2 2006.285.23:53:26.23#ibcon#*mode == 0, iclass 22, count 2 2006.285.23:53:26.23#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.23:53:26.23#ibcon#[25=AT05-03\r\n] 2006.285.23:53:26.23#ibcon#*before write, iclass 22, count 2 2006.285.23:53:26.23#ibcon#enter sib2, iclass 22, count 2 2006.285.23:53:26.23#ibcon#flushed, iclass 22, count 2 2006.285.23:53:26.23#ibcon#about to write, iclass 22, count 2 2006.285.23:53:26.23#ibcon#wrote, iclass 22, count 2 2006.285.23:53:26.23#ibcon#about to read 3, iclass 22, count 2 2006.285.23:53:26.26#ibcon#read 3, iclass 22, count 2 2006.285.23:53:26.26#ibcon#about to read 4, iclass 22, count 2 2006.285.23:53:26.26#ibcon#read 4, iclass 22, count 2 2006.285.23:53:26.26#ibcon#about to read 5, iclass 22, count 2 2006.285.23:53:26.26#ibcon#read 5, iclass 22, count 2 2006.285.23:53:26.26#ibcon#about to read 6, iclass 22, count 2 2006.285.23:53:26.26#ibcon#read 6, iclass 22, count 2 2006.285.23:53:26.26#ibcon#end of sib2, iclass 22, count 2 2006.285.23:53:26.26#ibcon#*after write, iclass 22, count 2 2006.285.23:53:26.26#ibcon#*before return 0, iclass 22, count 2 2006.285.23:53:26.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:53:26.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:53:26.26#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.23:53:26.26#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:26.26#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:53:26.38#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:53:26.38#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:53:26.38#ibcon#enter wrdev, iclass 22, count 0 2006.285.23:53:26.38#ibcon#first serial, iclass 22, count 0 2006.285.23:53:26.38#ibcon#enter sib2, iclass 22, count 0 2006.285.23:53:26.38#ibcon#flushed, iclass 22, count 0 2006.285.23:53:26.38#ibcon#about to write, iclass 22, count 0 2006.285.23:53:26.38#ibcon#wrote, iclass 22, count 0 2006.285.23:53:26.38#ibcon#about to read 3, iclass 22, count 0 2006.285.23:53:26.40#ibcon#read 3, iclass 22, count 0 2006.285.23:53:26.40#ibcon#about to read 4, iclass 22, count 0 2006.285.23:53:26.40#ibcon#read 4, iclass 22, count 0 2006.285.23:53:26.40#ibcon#about to read 5, iclass 22, count 0 2006.285.23:53:26.40#ibcon#read 5, iclass 22, count 0 2006.285.23:53:26.40#ibcon#about to read 6, iclass 22, count 0 2006.285.23:53:26.40#ibcon#read 6, iclass 22, count 0 2006.285.23:53:26.40#ibcon#end of sib2, iclass 22, count 0 2006.285.23:53:26.40#ibcon#*mode == 0, iclass 22, count 0 2006.285.23:53:26.40#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.23:53:26.40#ibcon#[25=USB\r\n] 2006.285.23:53:26.40#ibcon#*before write, iclass 22, count 0 2006.285.23:53:26.40#ibcon#enter sib2, iclass 22, count 0 2006.285.23:53:26.40#ibcon#flushed, iclass 22, count 0 2006.285.23:53:26.40#ibcon#about to write, iclass 22, count 0 2006.285.23:53:26.40#ibcon#wrote, iclass 22, count 0 2006.285.23:53:26.40#ibcon#about to read 3, iclass 22, count 0 2006.285.23:53:26.43#ibcon#read 3, iclass 22, count 0 2006.285.23:53:26.43#ibcon#about to read 4, iclass 22, count 0 2006.285.23:53:26.43#ibcon#read 4, iclass 22, count 0 2006.285.23:53:26.43#ibcon#about to read 5, iclass 22, count 0 2006.285.23:53:26.43#ibcon#read 5, iclass 22, count 0 2006.285.23:53:26.43#ibcon#about to read 6, iclass 22, count 0 2006.285.23:53:26.43#ibcon#read 6, iclass 22, count 0 2006.285.23:53:26.43#ibcon#end of sib2, iclass 22, count 0 2006.285.23:53:26.43#ibcon#*after write, iclass 22, count 0 2006.285.23:53:26.43#ibcon#*before return 0, iclass 22, count 0 2006.285.23:53:26.43#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:53:26.43#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:53:26.43#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.23:53:26.43#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.23:53:26.43$vck44/valo=6,814.99 2006.285.23:53:26.43#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.23:53:26.43#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.23:53:26.43#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:26.43#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:53:26.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:53:26.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:53:26.43#ibcon#enter wrdev, iclass 24, count 0 2006.285.23:53:26.43#ibcon#first serial, iclass 24, count 0 2006.285.23:53:26.43#ibcon#enter sib2, iclass 24, count 0 2006.285.23:53:26.43#ibcon#flushed, iclass 24, count 0 2006.285.23:53:26.43#ibcon#about to write, iclass 24, count 0 2006.285.23:53:26.43#ibcon#wrote, iclass 24, count 0 2006.285.23:53:26.43#ibcon#about to read 3, iclass 24, count 0 2006.285.23:53:26.45#ibcon#read 3, iclass 24, count 0 2006.285.23:53:26.45#ibcon#about to read 4, iclass 24, count 0 2006.285.23:53:26.45#ibcon#read 4, iclass 24, count 0 2006.285.23:53:26.45#ibcon#about to read 5, iclass 24, count 0 2006.285.23:53:26.45#ibcon#read 5, iclass 24, count 0 2006.285.23:53:26.45#ibcon#about to read 6, iclass 24, count 0 2006.285.23:53:26.45#ibcon#read 6, iclass 24, count 0 2006.285.23:53:26.45#ibcon#end of sib2, iclass 24, count 0 2006.285.23:53:26.45#ibcon#*mode == 0, iclass 24, count 0 2006.285.23:53:26.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.23:53:26.45#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.23:53:26.45#ibcon#*before write, iclass 24, count 0 2006.285.23:53:26.45#ibcon#enter sib2, iclass 24, count 0 2006.285.23:53:26.45#ibcon#flushed, iclass 24, count 0 2006.285.23:53:26.45#ibcon#about to write, iclass 24, count 0 2006.285.23:53:26.45#ibcon#wrote, iclass 24, count 0 2006.285.23:53:26.45#ibcon#about to read 3, iclass 24, count 0 2006.285.23:53:26.49#ibcon#read 3, iclass 24, count 0 2006.285.23:53:26.49#ibcon#about to read 4, iclass 24, count 0 2006.285.23:53:26.49#ibcon#read 4, iclass 24, count 0 2006.285.23:53:26.49#ibcon#about to read 5, iclass 24, count 0 2006.285.23:53:26.49#ibcon#read 5, iclass 24, count 0 2006.285.23:53:26.49#ibcon#about to read 6, iclass 24, count 0 2006.285.23:53:26.49#ibcon#read 6, iclass 24, count 0 2006.285.23:53:26.49#ibcon#end of sib2, iclass 24, count 0 2006.285.23:53:26.49#ibcon#*after write, iclass 24, count 0 2006.285.23:53:26.49#ibcon#*before return 0, iclass 24, count 0 2006.285.23:53:26.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:53:26.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:53:26.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.23:53:26.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.23:53:26.49$vck44/va=6,4 2006.285.23:53:26.49#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.23:53:26.49#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.23:53:26.49#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:26.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:53:26.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:53:26.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:53:26.55#ibcon#enter wrdev, iclass 26, count 2 2006.285.23:53:26.55#ibcon#first serial, iclass 26, count 2 2006.285.23:53:26.55#ibcon#enter sib2, iclass 26, count 2 2006.285.23:53:26.55#ibcon#flushed, iclass 26, count 2 2006.285.23:53:26.55#ibcon#about to write, iclass 26, count 2 2006.285.23:53:26.55#ibcon#wrote, iclass 26, count 2 2006.285.23:53:26.55#ibcon#about to read 3, iclass 26, count 2 2006.285.23:53:26.57#ibcon#read 3, iclass 26, count 2 2006.285.23:53:26.57#ibcon#about to read 4, iclass 26, count 2 2006.285.23:53:26.57#ibcon#read 4, iclass 26, count 2 2006.285.23:53:26.57#ibcon#about to read 5, iclass 26, count 2 2006.285.23:53:26.57#ibcon#read 5, iclass 26, count 2 2006.285.23:53:26.57#ibcon#about to read 6, iclass 26, count 2 2006.285.23:53:26.57#ibcon#read 6, iclass 26, count 2 2006.285.23:53:26.57#ibcon#end of sib2, iclass 26, count 2 2006.285.23:53:26.57#ibcon#*mode == 0, iclass 26, count 2 2006.285.23:53:26.57#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.23:53:26.57#ibcon#[25=AT06-04\r\n] 2006.285.23:53:26.57#ibcon#*before write, iclass 26, count 2 2006.285.23:53:26.57#ibcon#enter sib2, iclass 26, count 2 2006.285.23:53:26.57#ibcon#flushed, iclass 26, count 2 2006.285.23:53:26.57#ibcon#about to write, iclass 26, count 2 2006.285.23:53:26.57#ibcon#wrote, iclass 26, count 2 2006.285.23:53:26.57#ibcon#about to read 3, iclass 26, count 2 2006.285.23:53:26.60#ibcon#read 3, iclass 26, count 2 2006.285.23:53:26.60#ibcon#about to read 4, iclass 26, count 2 2006.285.23:53:26.60#ibcon#read 4, iclass 26, count 2 2006.285.23:53:26.60#ibcon#about to read 5, iclass 26, count 2 2006.285.23:53:26.60#ibcon#read 5, iclass 26, count 2 2006.285.23:53:26.60#ibcon#about to read 6, iclass 26, count 2 2006.285.23:53:26.60#ibcon#read 6, iclass 26, count 2 2006.285.23:53:26.60#ibcon#end of sib2, iclass 26, count 2 2006.285.23:53:26.60#ibcon#*after write, iclass 26, count 2 2006.285.23:53:26.60#ibcon#*before return 0, iclass 26, count 2 2006.285.23:53:26.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:53:26.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:53:26.60#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.23:53:26.60#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:26.60#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:53:26.72#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:53:26.72#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:53:26.72#ibcon#enter wrdev, iclass 26, count 0 2006.285.23:53:26.72#ibcon#first serial, iclass 26, count 0 2006.285.23:53:26.72#ibcon#enter sib2, iclass 26, count 0 2006.285.23:53:26.72#ibcon#flushed, iclass 26, count 0 2006.285.23:53:26.72#ibcon#about to write, iclass 26, count 0 2006.285.23:53:26.72#ibcon#wrote, iclass 26, count 0 2006.285.23:53:26.72#ibcon#about to read 3, iclass 26, count 0 2006.285.23:53:26.74#ibcon#read 3, iclass 26, count 0 2006.285.23:53:26.74#ibcon#about to read 4, iclass 26, count 0 2006.285.23:53:26.74#ibcon#read 4, iclass 26, count 0 2006.285.23:53:26.74#ibcon#about to read 5, iclass 26, count 0 2006.285.23:53:26.74#ibcon#read 5, iclass 26, count 0 2006.285.23:53:26.74#ibcon#about to read 6, iclass 26, count 0 2006.285.23:53:26.74#ibcon#read 6, iclass 26, count 0 2006.285.23:53:26.74#ibcon#end of sib2, iclass 26, count 0 2006.285.23:53:26.74#ibcon#*mode == 0, iclass 26, count 0 2006.285.23:53:26.74#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.23:53:26.74#ibcon#[25=USB\r\n] 2006.285.23:53:26.74#ibcon#*before write, iclass 26, count 0 2006.285.23:53:26.74#ibcon#enter sib2, iclass 26, count 0 2006.285.23:53:26.74#ibcon#flushed, iclass 26, count 0 2006.285.23:53:26.74#ibcon#about to write, iclass 26, count 0 2006.285.23:53:26.74#ibcon#wrote, iclass 26, count 0 2006.285.23:53:26.74#ibcon#about to read 3, iclass 26, count 0 2006.285.23:53:26.77#ibcon#read 3, iclass 26, count 0 2006.285.23:53:26.77#ibcon#about to read 4, iclass 26, count 0 2006.285.23:53:26.77#ibcon#read 4, iclass 26, count 0 2006.285.23:53:26.77#ibcon#about to read 5, iclass 26, count 0 2006.285.23:53:26.77#ibcon#read 5, iclass 26, count 0 2006.285.23:53:26.77#ibcon#about to read 6, iclass 26, count 0 2006.285.23:53:26.77#ibcon#read 6, iclass 26, count 0 2006.285.23:53:26.77#ibcon#end of sib2, iclass 26, count 0 2006.285.23:53:26.77#ibcon#*after write, iclass 26, count 0 2006.285.23:53:26.77#ibcon#*before return 0, iclass 26, count 0 2006.285.23:53:26.77#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:53:26.77#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:53:26.77#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.23:53:26.77#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.23:53:26.77$vck44/valo=7,864.99 2006.285.23:53:26.77#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.23:53:26.77#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.23:53:26.77#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:26.77#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:53:26.77#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:53:26.77#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:53:26.77#ibcon#enter wrdev, iclass 28, count 0 2006.285.23:53:26.77#ibcon#first serial, iclass 28, count 0 2006.285.23:53:26.77#ibcon#enter sib2, iclass 28, count 0 2006.285.23:53:26.77#ibcon#flushed, iclass 28, count 0 2006.285.23:53:26.77#ibcon#about to write, iclass 28, count 0 2006.285.23:53:26.77#ibcon#wrote, iclass 28, count 0 2006.285.23:53:26.77#ibcon#about to read 3, iclass 28, count 0 2006.285.23:53:26.79#ibcon#read 3, iclass 28, count 0 2006.285.23:53:26.79#ibcon#about to read 4, iclass 28, count 0 2006.285.23:53:26.79#ibcon#read 4, iclass 28, count 0 2006.285.23:53:26.79#ibcon#about to read 5, iclass 28, count 0 2006.285.23:53:26.79#ibcon#read 5, iclass 28, count 0 2006.285.23:53:26.79#ibcon#about to read 6, iclass 28, count 0 2006.285.23:53:26.79#ibcon#read 6, iclass 28, count 0 2006.285.23:53:26.79#ibcon#end of sib2, iclass 28, count 0 2006.285.23:53:26.79#ibcon#*mode == 0, iclass 28, count 0 2006.285.23:53:26.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.23:53:26.79#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.23:53:26.79#ibcon#*before write, iclass 28, count 0 2006.285.23:53:26.79#ibcon#enter sib2, iclass 28, count 0 2006.285.23:53:26.79#ibcon#flushed, iclass 28, count 0 2006.285.23:53:26.79#ibcon#about to write, iclass 28, count 0 2006.285.23:53:26.79#ibcon#wrote, iclass 28, count 0 2006.285.23:53:26.79#ibcon#about to read 3, iclass 28, count 0 2006.285.23:53:26.83#ibcon#read 3, iclass 28, count 0 2006.285.23:53:26.83#ibcon#about to read 4, iclass 28, count 0 2006.285.23:53:26.83#ibcon#read 4, iclass 28, count 0 2006.285.23:53:26.83#ibcon#about to read 5, iclass 28, count 0 2006.285.23:53:26.83#ibcon#read 5, iclass 28, count 0 2006.285.23:53:26.83#ibcon#about to read 6, iclass 28, count 0 2006.285.23:53:26.83#ibcon#read 6, iclass 28, count 0 2006.285.23:53:26.83#ibcon#end of sib2, iclass 28, count 0 2006.285.23:53:26.83#ibcon#*after write, iclass 28, count 0 2006.285.23:53:26.83#ibcon#*before return 0, iclass 28, count 0 2006.285.23:53:26.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:53:26.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:53:26.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.23:53:26.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.23:53:26.83$vck44/va=7,4 2006.285.23:53:26.83#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.23:53:26.83#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.23:53:26.83#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:26.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:53:26.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:53:26.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:53:26.89#ibcon#enter wrdev, iclass 30, count 2 2006.285.23:53:26.89#ibcon#first serial, iclass 30, count 2 2006.285.23:53:26.89#ibcon#enter sib2, iclass 30, count 2 2006.285.23:53:26.89#ibcon#flushed, iclass 30, count 2 2006.285.23:53:26.89#ibcon#about to write, iclass 30, count 2 2006.285.23:53:26.89#ibcon#wrote, iclass 30, count 2 2006.285.23:53:26.89#ibcon#about to read 3, iclass 30, count 2 2006.285.23:53:26.91#ibcon#read 3, iclass 30, count 2 2006.285.23:53:26.91#ibcon#about to read 4, iclass 30, count 2 2006.285.23:53:26.91#ibcon#read 4, iclass 30, count 2 2006.285.23:53:26.91#ibcon#about to read 5, iclass 30, count 2 2006.285.23:53:26.91#ibcon#read 5, iclass 30, count 2 2006.285.23:53:26.91#ibcon#about to read 6, iclass 30, count 2 2006.285.23:53:26.91#ibcon#read 6, iclass 30, count 2 2006.285.23:53:26.91#ibcon#end of sib2, iclass 30, count 2 2006.285.23:53:26.91#ibcon#*mode == 0, iclass 30, count 2 2006.285.23:53:26.91#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.23:53:26.91#ibcon#[25=AT07-04\r\n] 2006.285.23:53:26.91#ibcon#*before write, iclass 30, count 2 2006.285.23:53:26.91#ibcon#enter sib2, iclass 30, count 2 2006.285.23:53:26.91#ibcon#flushed, iclass 30, count 2 2006.285.23:53:26.91#ibcon#about to write, iclass 30, count 2 2006.285.23:53:26.91#ibcon#wrote, iclass 30, count 2 2006.285.23:53:26.91#ibcon#about to read 3, iclass 30, count 2 2006.285.23:53:26.94#ibcon#read 3, iclass 30, count 2 2006.285.23:53:26.94#ibcon#about to read 4, iclass 30, count 2 2006.285.23:53:26.94#ibcon#read 4, iclass 30, count 2 2006.285.23:53:26.94#ibcon#about to read 5, iclass 30, count 2 2006.285.23:53:26.94#ibcon#read 5, iclass 30, count 2 2006.285.23:53:26.94#ibcon#about to read 6, iclass 30, count 2 2006.285.23:53:26.94#ibcon#read 6, iclass 30, count 2 2006.285.23:53:26.94#ibcon#end of sib2, iclass 30, count 2 2006.285.23:53:26.94#ibcon#*after write, iclass 30, count 2 2006.285.23:53:26.94#ibcon#*before return 0, iclass 30, count 2 2006.285.23:53:26.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:53:26.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:53:26.94#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.23:53:26.94#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:26.94#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:53:27.06#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:53:27.06#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:53:27.06#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:53:27.06#ibcon#first serial, iclass 30, count 0 2006.285.23:53:27.06#ibcon#enter sib2, iclass 30, count 0 2006.285.23:53:27.06#ibcon#flushed, iclass 30, count 0 2006.285.23:53:27.06#ibcon#about to write, iclass 30, count 0 2006.285.23:53:27.06#ibcon#wrote, iclass 30, count 0 2006.285.23:53:27.06#ibcon#about to read 3, iclass 30, count 0 2006.285.23:53:27.08#ibcon#read 3, iclass 30, count 0 2006.285.23:53:27.08#ibcon#about to read 4, iclass 30, count 0 2006.285.23:53:27.08#ibcon#read 4, iclass 30, count 0 2006.285.23:53:27.08#ibcon#about to read 5, iclass 30, count 0 2006.285.23:53:27.08#ibcon#read 5, iclass 30, count 0 2006.285.23:53:27.08#ibcon#about to read 6, iclass 30, count 0 2006.285.23:53:27.08#ibcon#read 6, iclass 30, count 0 2006.285.23:53:27.08#ibcon#end of sib2, iclass 30, count 0 2006.285.23:53:27.08#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:53:27.08#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:53:27.08#ibcon#[25=USB\r\n] 2006.285.23:53:27.08#ibcon#*before write, iclass 30, count 0 2006.285.23:53:27.08#ibcon#enter sib2, iclass 30, count 0 2006.285.23:53:27.08#ibcon#flushed, iclass 30, count 0 2006.285.23:53:27.08#ibcon#about to write, iclass 30, count 0 2006.285.23:53:27.08#ibcon#wrote, iclass 30, count 0 2006.285.23:53:27.08#ibcon#about to read 3, iclass 30, count 0 2006.285.23:53:27.11#ibcon#read 3, iclass 30, count 0 2006.285.23:53:27.11#ibcon#about to read 4, iclass 30, count 0 2006.285.23:53:27.11#ibcon#read 4, iclass 30, count 0 2006.285.23:53:27.11#ibcon#about to read 5, iclass 30, count 0 2006.285.23:53:27.11#ibcon#read 5, iclass 30, count 0 2006.285.23:53:27.11#ibcon#about to read 6, iclass 30, count 0 2006.285.23:53:27.11#ibcon#read 6, iclass 30, count 0 2006.285.23:53:27.11#ibcon#end of sib2, iclass 30, count 0 2006.285.23:53:27.11#ibcon#*after write, iclass 30, count 0 2006.285.23:53:27.11#ibcon#*before return 0, iclass 30, count 0 2006.285.23:53:27.11#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:53:27.11#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:53:27.11#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:53:27.11#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:53:27.11$vck44/valo=8,884.99 2006.285.23:53:27.11#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.23:53:27.11#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.23:53:27.11#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:27.11#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:53:27.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:53:27.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:53:27.11#ibcon#enter wrdev, iclass 32, count 0 2006.285.23:53:27.11#ibcon#first serial, iclass 32, count 0 2006.285.23:53:27.11#ibcon#enter sib2, iclass 32, count 0 2006.285.23:53:27.11#ibcon#flushed, iclass 32, count 0 2006.285.23:53:27.11#ibcon#about to write, iclass 32, count 0 2006.285.23:53:27.11#ibcon#wrote, iclass 32, count 0 2006.285.23:53:27.11#ibcon#about to read 3, iclass 32, count 0 2006.285.23:53:27.13#ibcon#read 3, iclass 32, count 0 2006.285.23:53:27.13#ibcon#about to read 4, iclass 32, count 0 2006.285.23:53:27.13#ibcon#read 4, iclass 32, count 0 2006.285.23:53:27.13#ibcon#about to read 5, iclass 32, count 0 2006.285.23:53:27.13#ibcon#read 5, iclass 32, count 0 2006.285.23:53:27.13#ibcon#about to read 6, iclass 32, count 0 2006.285.23:53:27.13#ibcon#read 6, iclass 32, count 0 2006.285.23:53:27.13#ibcon#end of sib2, iclass 32, count 0 2006.285.23:53:27.13#ibcon#*mode == 0, iclass 32, count 0 2006.285.23:53:27.13#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.23:53:27.13#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.23:53:27.13#ibcon#*before write, iclass 32, count 0 2006.285.23:53:27.13#ibcon#enter sib2, iclass 32, count 0 2006.285.23:53:27.13#ibcon#flushed, iclass 32, count 0 2006.285.23:53:27.13#ibcon#about to write, iclass 32, count 0 2006.285.23:53:27.13#ibcon#wrote, iclass 32, count 0 2006.285.23:53:27.13#ibcon#about to read 3, iclass 32, count 0 2006.285.23:53:27.17#ibcon#read 3, iclass 32, count 0 2006.285.23:53:27.17#ibcon#about to read 4, iclass 32, count 0 2006.285.23:53:27.17#ibcon#read 4, iclass 32, count 0 2006.285.23:53:27.17#ibcon#about to read 5, iclass 32, count 0 2006.285.23:53:27.17#ibcon#read 5, iclass 32, count 0 2006.285.23:53:27.17#ibcon#about to read 6, iclass 32, count 0 2006.285.23:53:27.17#ibcon#read 6, iclass 32, count 0 2006.285.23:53:27.17#ibcon#end of sib2, iclass 32, count 0 2006.285.23:53:27.17#ibcon#*after write, iclass 32, count 0 2006.285.23:53:27.17#ibcon#*before return 0, iclass 32, count 0 2006.285.23:53:27.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:53:27.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:53:27.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.23:53:27.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.23:53:27.17$vck44/va=8,3 2006.285.23:53:27.17#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.285.23:53:27.17#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.285.23:53:27.17#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:27.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:53:27.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:53:27.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:53:27.23#ibcon#enter wrdev, iclass 34, count 2 2006.285.23:53:27.23#ibcon#first serial, iclass 34, count 2 2006.285.23:53:27.23#ibcon#enter sib2, iclass 34, count 2 2006.285.23:53:27.23#ibcon#flushed, iclass 34, count 2 2006.285.23:53:27.23#ibcon#about to write, iclass 34, count 2 2006.285.23:53:27.23#ibcon#wrote, iclass 34, count 2 2006.285.23:53:27.23#ibcon#about to read 3, iclass 34, count 2 2006.285.23:53:27.25#ibcon#read 3, iclass 34, count 2 2006.285.23:53:27.25#ibcon#about to read 4, iclass 34, count 2 2006.285.23:53:27.25#ibcon#read 4, iclass 34, count 2 2006.285.23:53:27.25#ibcon#about to read 5, iclass 34, count 2 2006.285.23:53:27.25#ibcon#read 5, iclass 34, count 2 2006.285.23:53:27.25#ibcon#about to read 6, iclass 34, count 2 2006.285.23:53:27.25#ibcon#read 6, iclass 34, count 2 2006.285.23:53:27.25#ibcon#end of sib2, iclass 34, count 2 2006.285.23:53:27.25#ibcon#*mode == 0, iclass 34, count 2 2006.285.23:53:27.25#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.285.23:53:27.25#ibcon#[25=AT08-03\r\n] 2006.285.23:53:27.25#ibcon#*before write, iclass 34, count 2 2006.285.23:53:27.25#ibcon#enter sib2, iclass 34, count 2 2006.285.23:53:27.25#ibcon#flushed, iclass 34, count 2 2006.285.23:53:27.25#ibcon#about to write, iclass 34, count 2 2006.285.23:53:27.25#ibcon#wrote, iclass 34, count 2 2006.285.23:53:27.25#ibcon#about to read 3, iclass 34, count 2 2006.285.23:53:27.28#ibcon#read 3, iclass 34, count 2 2006.285.23:53:27.28#ibcon#about to read 4, iclass 34, count 2 2006.285.23:53:27.28#ibcon#read 4, iclass 34, count 2 2006.285.23:53:27.28#ibcon#about to read 5, iclass 34, count 2 2006.285.23:53:27.28#ibcon#read 5, iclass 34, count 2 2006.285.23:53:27.28#ibcon#about to read 6, iclass 34, count 2 2006.285.23:53:27.28#ibcon#read 6, iclass 34, count 2 2006.285.23:53:27.28#ibcon#end of sib2, iclass 34, count 2 2006.285.23:53:27.28#ibcon#*after write, iclass 34, count 2 2006.285.23:53:27.28#ibcon#*before return 0, iclass 34, count 2 2006.285.23:53:27.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:53:27.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.285.23:53:27.28#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.285.23:53:27.28#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:27.28#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:53:27.40#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:53:27.40#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:53:27.40#ibcon#enter wrdev, iclass 34, count 0 2006.285.23:53:27.40#ibcon#first serial, iclass 34, count 0 2006.285.23:53:27.40#ibcon#enter sib2, iclass 34, count 0 2006.285.23:53:27.40#ibcon#flushed, iclass 34, count 0 2006.285.23:53:27.40#ibcon#about to write, iclass 34, count 0 2006.285.23:53:27.40#ibcon#wrote, iclass 34, count 0 2006.285.23:53:27.40#ibcon#about to read 3, iclass 34, count 0 2006.285.23:53:27.42#ibcon#read 3, iclass 34, count 0 2006.285.23:53:27.42#ibcon#about to read 4, iclass 34, count 0 2006.285.23:53:27.42#ibcon#read 4, iclass 34, count 0 2006.285.23:53:27.42#ibcon#about to read 5, iclass 34, count 0 2006.285.23:53:27.42#ibcon#read 5, iclass 34, count 0 2006.285.23:53:27.42#ibcon#about to read 6, iclass 34, count 0 2006.285.23:53:27.42#ibcon#read 6, iclass 34, count 0 2006.285.23:53:27.42#ibcon#end of sib2, iclass 34, count 0 2006.285.23:53:27.42#ibcon#*mode == 0, iclass 34, count 0 2006.285.23:53:27.42#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.23:53:27.42#ibcon#[25=USB\r\n] 2006.285.23:53:27.42#ibcon#*before write, iclass 34, count 0 2006.285.23:53:27.42#ibcon#enter sib2, iclass 34, count 0 2006.285.23:53:27.42#ibcon#flushed, iclass 34, count 0 2006.285.23:53:27.42#ibcon#about to write, iclass 34, count 0 2006.285.23:53:27.42#ibcon#wrote, iclass 34, count 0 2006.285.23:53:27.42#ibcon#about to read 3, iclass 34, count 0 2006.285.23:53:27.45#ibcon#read 3, iclass 34, count 0 2006.285.23:53:27.45#ibcon#about to read 4, iclass 34, count 0 2006.285.23:53:27.45#ibcon#read 4, iclass 34, count 0 2006.285.23:53:27.45#ibcon#about to read 5, iclass 34, count 0 2006.285.23:53:27.45#ibcon#read 5, iclass 34, count 0 2006.285.23:53:27.45#ibcon#about to read 6, iclass 34, count 0 2006.285.23:53:27.45#ibcon#read 6, iclass 34, count 0 2006.285.23:53:27.45#ibcon#end of sib2, iclass 34, count 0 2006.285.23:53:27.45#ibcon#*after write, iclass 34, count 0 2006.285.23:53:27.45#ibcon#*before return 0, iclass 34, count 0 2006.285.23:53:27.45#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:53:27.45#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.285.23:53:27.45#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.23:53:27.45#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.23:53:27.45$vck44/vblo=1,629.99 2006.285.23:53:27.45#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.285.23:53:27.45#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.285.23:53:27.45#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:27.45#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:53:27.45#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:53:27.45#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:53:27.45#ibcon#enter wrdev, iclass 36, count 0 2006.285.23:53:27.45#ibcon#first serial, iclass 36, count 0 2006.285.23:53:27.45#ibcon#enter sib2, iclass 36, count 0 2006.285.23:53:27.45#ibcon#flushed, iclass 36, count 0 2006.285.23:53:27.45#ibcon#about to write, iclass 36, count 0 2006.285.23:53:27.45#ibcon#wrote, iclass 36, count 0 2006.285.23:53:27.45#ibcon#about to read 3, iclass 36, count 0 2006.285.23:53:27.47#ibcon#read 3, iclass 36, count 0 2006.285.23:53:27.47#ibcon#about to read 4, iclass 36, count 0 2006.285.23:53:27.47#ibcon#read 4, iclass 36, count 0 2006.285.23:53:27.47#ibcon#about to read 5, iclass 36, count 0 2006.285.23:53:27.47#ibcon#read 5, iclass 36, count 0 2006.285.23:53:27.47#ibcon#about to read 6, iclass 36, count 0 2006.285.23:53:27.47#ibcon#read 6, iclass 36, count 0 2006.285.23:53:27.47#ibcon#end of sib2, iclass 36, count 0 2006.285.23:53:27.47#ibcon#*mode == 0, iclass 36, count 0 2006.285.23:53:27.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.285.23:53:27.47#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.23:53:27.47#ibcon#*before write, iclass 36, count 0 2006.285.23:53:27.47#ibcon#enter sib2, iclass 36, count 0 2006.285.23:53:27.47#ibcon#flushed, iclass 36, count 0 2006.285.23:53:27.47#ibcon#about to write, iclass 36, count 0 2006.285.23:53:27.47#ibcon#wrote, iclass 36, count 0 2006.285.23:53:27.47#ibcon#about to read 3, iclass 36, count 0 2006.285.23:53:27.51#ibcon#read 3, iclass 36, count 0 2006.285.23:53:27.51#ibcon#about to read 4, iclass 36, count 0 2006.285.23:53:27.51#ibcon#read 4, iclass 36, count 0 2006.285.23:53:27.51#ibcon#about to read 5, iclass 36, count 0 2006.285.23:53:27.51#ibcon#read 5, iclass 36, count 0 2006.285.23:53:27.51#ibcon#about to read 6, iclass 36, count 0 2006.285.23:53:27.51#ibcon#read 6, iclass 36, count 0 2006.285.23:53:27.51#ibcon#end of sib2, iclass 36, count 0 2006.285.23:53:27.51#ibcon#*after write, iclass 36, count 0 2006.285.23:53:27.51#ibcon#*before return 0, iclass 36, count 0 2006.285.23:53:27.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:53:27.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.285.23:53:27.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.285.23:53:27.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.285.23:53:27.51$vck44/vb=1,4 2006.285.23:53:27.51#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.285.23:53:27.51#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.285.23:53:27.51#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:27.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:53:27.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:53:27.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:53:27.51#ibcon#enter wrdev, iclass 38, count 2 2006.285.23:53:27.51#ibcon#first serial, iclass 38, count 2 2006.285.23:53:27.51#ibcon#enter sib2, iclass 38, count 2 2006.285.23:53:27.51#ibcon#flushed, iclass 38, count 2 2006.285.23:53:27.51#ibcon#about to write, iclass 38, count 2 2006.285.23:53:27.51#ibcon#wrote, iclass 38, count 2 2006.285.23:53:27.51#ibcon#about to read 3, iclass 38, count 2 2006.285.23:53:27.53#ibcon#read 3, iclass 38, count 2 2006.285.23:53:27.53#ibcon#about to read 4, iclass 38, count 2 2006.285.23:53:27.53#ibcon#read 4, iclass 38, count 2 2006.285.23:53:27.53#ibcon#about to read 5, iclass 38, count 2 2006.285.23:53:27.53#ibcon#read 5, iclass 38, count 2 2006.285.23:53:27.53#ibcon#about to read 6, iclass 38, count 2 2006.285.23:53:27.53#ibcon#read 6, iclass 38, count 2 2006.285.23:53:27.53#ibcon#end of sib2, iclass 38, count 2 2006.285.23:53:27.53#ibcon#*mode == 0, iclass 38, count 2 2006.285.23:53:27.53#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.285.23:53:27.53#ibcon#[27=AT01-04\r\n] 2006.285.23:53:27.53#ibcon#*before write, iclass 38, count 2 2006.285.23:53:27.53#ibcon#enter sib2, iclass 38, count 2 2006.285.23:53:27.53#ibcon#flushed, iclass 38, count 2 2006.285.23:53:27.53#ibcon#about to write, iclass 38, count 2 2006.285.23:53:27.53#ibcon#wrote, iclass 38, count 2 2006.285.23:53:27.53#ibcon#about to read 3, iclass 38, count 2 2006.285.23:53:27.56#ibcon#read 3, iclass 38, count 2 2006.285.23:53:27.56#ibcon#about to read 4, iclass 38, count 2 2006.285.23:53:27.56#ibcon#read 4, iclass 38, count 2 2006.285.23:53:27.56#ibcon#about to read 5, iclass 38, count 2 2006.285.23:53:27.56#ibcon#read 5, iclass 38, count 2 2006.285.23:53:27.56#ibcon#about to read 6, iclass 38, count 2 2006.285.23:53:27.56#ibcon#read 6, iclass 38, count 2 2006.285.23:53:27.56#ibcon#end of sib2, iclass 38, count 2 2006.285.23:53:27.56#ibcon#*after write, iclass 38, count 2 2006.285.23:53:27.56#ibcon#*before return 0, iclass 38, count 2 2006.285.23:53:27.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:53:27.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.285.23:53:27.56#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.285.23:53:27.56#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:27.56#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:53:27.68#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:53:27.68#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:53:27.68#ibcon#enter wrdev, iclass 38, count 0 2006.285.23:53:27.68#ibcon#first serial, iclass 38, count 0 2006.285.23:53:27.68#ibcon#enter sib2, iclass 38, count 0 2006.285.23:53:27.68#ibcon#flushed, iclass 38, count 0 2006.285.23:53:27.68#ibcon#about to write, iclass 38, count 0 2006.285.23:53:27.68#ibcon#wrote, iclass 38, count 0 2006.285.23:53:27.68#ibcon#about to read 3, iclass 38, count 0 2006.285.23:53:27.70#ibcon#read 3, iclass 38, count 0 2006.285.23:53:27.70#ibcon#about to read 4, iclass 38, count 0 2006.285.23:53:27.70#ibcon#read 4, iclass 38, count 0 2006.285.23:53:27.70#ibcon#about to read 5, iclass 38, count 0 2006.285.23:53:27.70#ibcon#read 5, iclass 38, count 0 2006.285.23:53:27.70#ibcon#about to read 6, iclass 38, count 0 2006.285.23:53:27.70#ibcon#read 6, iclass 38, count 0 2006.285.23:53:27.70#ibcon#end of sib2, iclass 38, count 0 2006.285.23:53:27.70#ibcon#*mode == 0, iclass 38, count 0 2006.285.23:53:27.70#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.285.23:53:27.70#ibcon#[27=USB\r\n] 2006.285.23:53:27.70#ibcon#*before write, iclass 38, count 0 2006.285.23:53:27.70#ibcon#enter sib2, iclass 38, count 0 2006.285.23:53:27.70#ibcon#flushed, iclass 38, count 0 2006.285.23:53:27.70#ibcon#about to write, iclass 38, count 0 2006.285.23:53:27.70#ibcon#wrote, iclass 38, count 0 2006.285.23:53:27.70#ibcon#about to read 3, iclass 38, count 0 2006.285.23:53:27.73#ibcon#read 3, iclass 38, count 0 2006.285.23:53:27.73#ibcon#about to read 4, iclass 38, count 0 2006.285.23:53:27.73#ibcon#read 4, iclass 38, count 0 2006.285.23:53:27.73#ibcon#about to read 5, iclass 38, count 0 2006.285.23:53:27.73#ibcon#read 5, iclass 38, count 0 2006.285.23:53:27.73#ibcon#about to read 6, iclass 38, count 0 2006.285.23:53:27.73#ibcon#read 6, iclass 38, count 0 2006.285.23:53:27.73#ibcon#end of sib2, iclass 38, count 0 2006.285.23:53:27.73#ibcon#*after write, iclass 38, count 0 2006.285.23:53:27.73#ibcon#*before return 0, iclass 38, count 0 2006.285.23:53:27.73#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:53:27.73#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.285.23:53:27.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.285.23:53:27.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.285.23:53:27.73$vck44/vblo=2,634.99 2006.285.23:53:27.73#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.285.23:53:27.73#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.285.23:53:27.73#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:27.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:53:27.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:53:27.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:53:27.73#ibcon#enter wrdev, iclass 40, count 0 2006.285.23:53:27.73#ibcon#first serial, iclass 40, count 0 2006.285.23:53:27.73#ibcon#enter sib2, iclass 40, count 0 2006.285.23:53:27.73#ibcon#flushed, iclass 40, count 0 2006.285.23:53:27.73#ibcon#about to write, iclass 40, count 0 2006.285.23:53:27.73#ibcon#wrote, iclass 40, count 0 2006.285.23:53:27.73#ibcon#about to read 3, iclass 40, count 0 2006.285.23:53:27.75#ibcon#read 3, iclass 40, count 0 2006.285.23:53:27.75#ibcon#about to read 4, iclass 40, count 0 2006.285.23:53:27.75#ibcon#read 4, iclass 40, count 0 2006.285.23:53:27.75#ibcon#about to read 5, iclass 40, count 0 2006.285.23:53:27.75#ibcon#read 5, iclass 40, count 0 2006.285.23:53:27.75#ibcon#about to read 6, iclass 40, count 0 2006.285.23:53:27.75#ibcon#read 6, iclass 40, count 0 2006.285.23:53:27.75#ibcon#end of sib2, iclass 40, count 0 2006.285.23:53:27.75#ibcon#*mode == 0, iclass 40, count 0 2006.285.23:53:27.75#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.285.23:53:27.75#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.23:53:27.75#ibcon#*before write, iclass 40, count 0 2006.285.23:53:27.75#ibcon#enter sib2, iclass 40, count 0 2006.285.23:53:27.75#ibcon#flushed, iclass 40, count 0 2006.285.23:53:27.75#ibcon#about to write, iclass 40, count 0 2006.285.23:53:27.75#ibcon#wrote, iclass 40, count 0 2006.285.23:53:27.75#ibcon#about to read 3, iclass 40, count 0 2006.285.23:53:27.79#ibcon#read 3, iclass 40, count 0 2006.285.23:53:27.79#ibcon#about to read 4, iclass 40, count 0 2006.285.23:53:27.79#ibcon#read 4, iclass 40, count 0 2006.285.23:53:27.79#ibcon#about to read 5, iclass 40, count 0 2006.285.23:53:27.79#ibcon#read 5, iclass 40, count 0 2006.285.23:53:27.79#ibcon#about to read 6, iclass 40, count 0 2006.285.23:53:27.79#ibcon#read 6, iclass 40, count 0 2006.285.23:53:27.79#ibcon#end of sib2, iclass 40, count 0 2006.285.23:53:27.79#ibcon#*after write, iclass 40, count 0 2006.285.23:53:27.79#ibcon#*before return 0, iclass 40, count 0 2006.285.23:53:27.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:53:27.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.285.23:53:27.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.285.23:53:27.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.285.23:53:27.79$vck44/vb=2,5 2006.285.23:53:27.79#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.285.23:53:27.79#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.285.23:53:27.79#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:27.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:53:27.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:53:27.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:53:27.85#ibcon#enter wrdev, iclass 4, count 2 2006.285.23:53:27.85#ibcon#first serial, iclass 4, count 2 2006.285.23:53:27.85#ibcon#enter sib2, iclass 4, count 2 2006.285.23:53:27.85#ibcon#flushed, iclass 4, count 2 2006.285.23:53:27.85#ibcon#about to write, iclass 4, count 2 2006.285.23:53:27.85#ibcon#wrote, iclass 4, count 2 2006.285.23:53:27.85#ibcon#about to read 3, iclass 4, count 2 2006.285.23:53:27.87#ibcon#read 3, iclass 4, count 2 2006.285.23:53:27.87#ibcon#about to read 4, iclass 4, count 2 2006.285.23:53:27.87#ibcon#read 4, iclass 4, count 2 2006.285.23:53:27.87#ibcon#about to read 5, iclass 4, count 2 2006.285.23:53:27.87#ibcon#read 5, iclass 4, count 2 2006.285.23:53:27.87#ibcon#about to read 6, iclass 4, count 2 2006.285.23:53:27.87#ibcon#read 6, iclass 4, count 2 2006.285.23:53:27.87#ibcon#end of sib2, iclass 4, count 2 2006.285.23:53:27.87#ibcon#*mode == 0, iclass 4, count 2 2006.285.23:53:27.87#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.285.23:53:27.87#ibcon#[27=AT02-05\r\n] 2006.285.23:53:27.87#ibcon#*before write, iclass 4, count 2 2006.285.23:53:27.87#ibcon#enter sib2, iclass 4, count 2 2006.285.23:53:27.87#ibcon#flushed, iclass 4, count 2 2006.285.23:53:27.87#ibcon#about to write, iclass 4, count 2 2006.285.23:53:27.87#ibcon#wrote, iclass 4, count 2 2006.285.23:53:27.87#ibcon#about to read 3, iclass 4, count 2 2006.285.23:53:27.90#ibcon#read 3, iclass 4, count 2 2006.285.23:53:27.90#ibcon#about to read 4, iclass 4, count 2 2006.285.23:53:27.90#ibcon#read 4, iclass 4, count 2 2006.285.23:53:27.90#ibcon#about to read 5, iclass 4, count 2 2006.285.23:53:27.90#ibcon#read 5, iclass 4, count 2 2006.285.23:53:27.90#ibcon#about to read 6, iclass 4, count 2 2006.285.23:53:27.90#ibcon#read 6, iclass 4, count 2 2006.285.23:53:27.90#ibcon#end of sib2, iclass 4, count 2 2006.285.23:53:27.90#ibcon#*after write, iclass 4, count 2 2006.285.23:53:27.90#ibcon#*before return 0, iclass 4, count 2 2006.285.23:53:27.90#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:53:27.90#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.285.23:53:27.90#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.285.23:53:27.90#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:27.90#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:53:28.02#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:53:28.02#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:53:28.02#ibcon#enter wrdev, iclass 4, count 0 2006.285.23:53:28.02#ibcon#first serial, iclass 4, count 0 2006.285.23:53:28.02#ibcon#enter sib2, iclass 4, count 0 2006.285.23:53:28.02#ibcon#flushed, iclass 4, count 0 2006.285.23:53:28.02#ibcon#about to write, iclass 4, count 0 2006.285.23:53:28.02#ibcon#wrote, iclass 4, count 0 2006.285.23:53:28.02#ibcon#about to read 3, iclass 4, count 0 2006.285.23:53:28.04#ibcon#read 3, iclass 4, count 0 2006.285.23:53:28.04#ibcon#about to read 4, iclass 4, count 0 2006.285.23:53:28.04#ibcon#read 4, iclass 4, count 0 2006.285.23:53:28.04#ibcon#about to read 5, iclass 4, count 0 2006.285.23:53:28.04#ibcon#read 5, iclass 4, count 0 2006.285.23:53:28.04#ibcon#about to read 6, iclass 4, count 0 2006.285.23:53:28.04#ibcon#read 6, iclass 4, count 0 2006.285.23:53:28.04#ibcon#end of sib2, iclass 4, count 0 2006.285.23:53:28.04#ibcon#*mode == 0, iclass 4, count 0 2006.285.23:53:28.04#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.285.23:53:28.04#ibcon#[27=USB\r\n] 2006.285.23:53:28.04#ibcon#*before write, iclass 4, count 0 2006.285.23:53:28.04#ibcon#enter sib2, iclass 4, count 0 2006.285.23:53:28.04#ibcon#flushed, iclass 4, count 0 2006.285.23:53:28.04#ibcon#about to write, iclass 4, count 0 2006.285.23:53:28.04#ibcon#wrote, iclass 4, count 0 2006.285.23:53:28.04#ibcon#about to read 3, iclass 4, count 0 2006.285.23:53:28.07#ibcon#read 3, iclass 4, count 0 2006.285.23:53:28.07#ibcon#about to read 4, iclass 4, count 0 2006.285.23:53:28.07#ibcon#read 4, iclass 4, count 0 2006.285.23:53:28.07#ibcon#about to read 5, iclass 4, count 0 2006.285.23:53:28.07#ibcon#read 5, iclass 4, count 0 2006.285.23:53:28.07#ibcon#about to read 6, iclass 4, count 0 2006.285.23:53:28.07#ibcon#read 6, iclass 4, count 0 2006.285.23:53:28.07#ibcon#end of sib2, iclass 4, count 0 2006.285.23:53:28.07#ibcon#*after write, iclass 4, count 0 2006.285.23:53:28.07#ibcon#*before return 0, iclass 4, count 0 2006.285.23:53:28.07#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:53:28.07#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.285.23:53:28.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.285.23:53:28.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.285.23:53:28.07$vck44/vblo=3,649.99 2006.285.23:53:28.07#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.285.23:53:28.07#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.285.23:53:28.07#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:28.07#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:53:28.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:53:28.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:53:28.07#ibcon#enter wrdev, iclass 6, count 0 2006.285.23:53:28.07#ibcon#first serial, iclass 6, count 0 2006.285.23:53:28.07#ibcon#enter sib2, iclass 6, count 0 2006.285.23:53:28.07#ibcon#flushed, iclass 6, count 0 2006.285.23:53:28.07#ibcon#about to write, iclass 6, count 0 2006.285.23:53:28.07#ibcon#wrote, iclass 6, count 0 2006.285.23:53:28.07#ibcon#about to read 3, iclass 6, count 0 2006.285.23:53:28.09#ibcon#read 3, iclass 6, count 0 2006.285.23:53:28.09#ibcon#about to read 4, iclass 6, count 0 2006.285.23:53:28.09#ibcon#read 4, iclass 6, count 0 2006.285.23:53:28.09#ibcon#about to read 5, iclass 6, count 0 2006.285.23:53:28.09#ibcon#read 5, iclass 6, count 0 2006.285.23:53:28.09#ibcon#about to read 6, iclass 6, count 0 2006.285.23:53:28.09#ibcon#read 6, iclass 6, count 0 2006.285.23:53:28.09#ibcon#end of sib2, iclass 6, count 0 2006.285.23:53:28.09#ibcon#*mode == 0, iclass 6, count 0 2006.285.23:53:28.09#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.285.23:53:28.09#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.23:53:28.09#ibcon#*before write, iclass 6, count 0 2006.285.23:53:28.09#ibcon#enter sib2, iclass 6, count 0 2006.285.23:53:28.09#ibcon#flushed, iclass 6, count 0 2006.285.23:53:28.09#ibcon#about to write, iclass 6, count 0 2006.285.23:53:28.09#ibcon#wrote, iclass 6, count 0 2006.285.23:53:28.09#ibcon#about to read 3, iclass 6, count 0 2006.285.23:53:28.13#ibcon#read 3, iclass 6, count 0 2006.285.23:53:28.13#ibcon#about to read 4, iclass 6, count 0 2006.285.23:53:28.13#ibcon#read 4, iclass 6, count 0 2006.285.23:53:28.13#ibcon#about to read 5, iclass 6, count 0 2006.285.23:53:28.13#ibcon#read 5, iclass 6, count 0 2006.285.23:53:28.13#ibcon#about to read 6, iclass 6, count 0 2006.285.23:53:28.13#ibcon#read 6, iclass 6, count 0 2006.285.23:53:28.13#ibcon#end of sib2, iclass 6, count 0 2006.285.23:53:28.13#ibcon#*after write, iclass 6, count 0 2006.285.23:53:28.13#ibcon#*before return 0, iclass 6, count 0 2006.285.23:53:28.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:53:28.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.285.23:53:28.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.285.23:53:28.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.285.23:53:28.13$vck44/vb=3,4 2006.285.23:53:28.13#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.285.23:53:28.13#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.285.23:53:28.13#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:28.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:53:28.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:53:28.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:53:28.19#ibcon#enter wrdev, iclass 10, count 2 2006.285.23:53:28.19#ibcon#first serial, iclass 10, count 2 2006.285.23:53:28.19#ibcon#enter sib2, iclass 10, count 2 2006.285.23:53:28.19#ibcon#flushed, iclass 10, count 2 2006.285.23:53:28.19#ibcon#about to write, iclass 10, count 2 2006.285.23:53:28.19#ibcon#wrote, iclass 10, count 2 2006.285.23:53:28.19#ibcon#about to read 3, iclass 10, count 2 2006.285.23:53:28.21#ibcon#read 3, iclass 10, count 2 2006.285.23:53:28.21#ibcon#about to read 4, iclass 10, count 2 2006.285.23:53:28.21#ibcon#read 4, iclass 10, count 2 2006.285.23:53:28.21#ibcon#about to read 5, iclass 10, count 2 2006.285.23:53:28.21#ibcon#read 5, iclass 10, count 2 2006.285.23:53:28.21#ibcon#about to read 6, iclass 10, count 2 2006.285.23:53:28.21#ibcon#read 6, iclass 10, count 2 2006.285.23:53:28.21#ibcon#end of sib2, iclass 10, count 2 2006.285.23:53:28.21#ibcon#*mode == 0, iclass 10, count 2 2006.285.23:53:28.21#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.285.23:53:28.21#ibcon#[27=AT03-04\r\n] 2006.285.23:53:28.21#ibcon#*before write, iclass 10, count 2 2006.285.23:53:28.21#ibcon#enter sib2, iclass 10, count 2 2006.285.23:53:28.21#ibcon#flushed, iclass 10, count 2 2006.285.23:53:28.21#ibcon#about to write, iclass 10, count 2 2006.285.23:53:28.21#ibcon#wrote, iclass 10, count 2 2006.285.23:53:28.21#ibcon#about to read 3, iclass 10, count 2 2006.285.23:53:28.24#ibcon#read 3, iclass 10, count 2 2006.285.23:53:28.24#ibcon#about to read 4, iclass 10, count 2 2006.285.23:53:28.24#ibcon#read 4, iclass 10, count 2 2006.285.23:53:28.24#ibcon#about to read 5, iclass 10, count 2 2006.285.23:53:28.24#ibcon#read 5, iclass 10, count 2 2006.285.23:53:28.24#ibcon#about to read 6, iclass 10, count 2 2006.285.23:53:28.24#ibcon#read 6, iclass 10, count 2 2006.285.23:53:28.24#ibcon#end of sib2, iclass 10, count 2 2006.285.23:53:28.24#ibcon#*after write, iclass 10, count 2 2006.285.23:53:28.24#ibcon#*before return 0, iclass 10, count 2 2006.285.23:53:28.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:53:28.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.285.23:53:28.24#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.285.23:53:28.24#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:28.24#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:53:28.36#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:53:28.36#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:53:28.36#ibcon#enter wrdev, iclass 10, count 0 2006.285.23:53:28.36#ibcon#first serial, iclass 10, count 0 2006.285.23:53:28.36#ibcon#enter sib2, iclass 10, count 0 2006.285.23:53:28.36#ibcon#flushed, iclass 10, count 0 2006.285.23:53:28.36#ibcon#about to write, iclass 10, count 0 2006.285.23:53:28.36#ibcon#wrote, iclass 10, count 0 2006.285.23:53:28.36#ibcon#about to read 3, iclass 10, count 0 2006.285.23:53:28.38#ibcon#read 3, iclass 10, count 0 2006.285.23:53:28.38#ibcon#about to read 4, iclass 10, count 0 2006.285.23:53:28.38#ibcon#read 4, iclass 10, count 0 2006.285.23:53:28.38#ibcon#about to read 5, iclass 10, count 0 2006.285.23:53:28.38#ibcon#read 5, iclass 10, count 0 2006.285.23:53:28.38#ibcon#about to read 6, iclass 10, count 0 2006.285.23:53:28.38#ibcon#read 6, iclass 10, count 0 2006.285.23:53:28.38#ibcon#end of sib2, iclass 10, count 0 2006.285.23:53:28.38#ibcon#*mode == 0, iclass 10, count 0 2006.285.23:53:28.38#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.285.23:53:28.38#ibcon#[27=USB\r\n] 2006.285.23:53:28.38#ibcon#*before write, iclass 10, count 0 2006.285.23:53:28.38#ibcon#enter sib2, iclass 10, count 0 2006.285.23:53:28.38#ibcon#flushed, iclass 10, count 0 2006.285.23:53:28.38#ibcon#about to write, iclass 10, count 0 2006.285.23:53:28.38#ibcon#wrote, iclass 10, count 0 2006.285.23:53:28.38#ibcon#about to read 3, iclass 10, count 0 2006.285.23:53:28.41#ibcon#read 3, iclass 10, count 0 2006.285.23:53:28.41#ibcon#about to read 4, iclass 10, count 0 2006.285.23:53:28.41#ibcon#read 4, iclass 10, count 0 2006.285.23:53:28.41#ibcon#about to read 5, iclass 10, count 0 2006.285.23:53:28.41#ibcon#read 5, iclass 10, count 0 2006.285.23:53:28.41#ibcon#about to read 6, iclass 10, count 0 2006.285.23:53:28.41#ibcon#read 6, iclass 10, count 0 2006.285.23:53:28.41#ibcon#end of sib2, iclass 10, count 0 2006.285.23:53:28.41#ibcon#*after write, iclass 10, count 0 2006.285.23:53:28.41#ibcon#*before return 0, iclass 10, count 0 2006.285.23:53:28.41#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:53:28.41#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.285.23:53:28.41#ibcon#about to clear, iclass 10 cls_cnt 0 2006.285.23:53:28.41#ibcon#cleared, iclass 10 cls_cnt 0 2006.285.23:53:28.41$vck44/vblo=4,679.99 2006.285.23:53:28.41#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.285.23:53:28.41#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.285.23:53:28.41#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:28.41#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:53:28.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:53:28.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:53:28.41#ibcon#enter wrdev, iclass 12, count 0 2006.285.23:53:28.41#ibcon#first serial, iclass 12, count 0 2006.285.23:53:28.41#ibcon#enter sib2, iclass 12, count 0 2006.285.23:53:28.41#ibcon#flushed, iclass 12, count 0 2006.285.23:53:28.41#ibcon#about to write, iclass 12, count 0 2006.285.23:53:28.41#ibcon#wrote, iclass 12, count 0 2006.285.23:53:28.41#ibcon#about to read 3, iclass 12, count 0 2006.285.23:53:28.43#ibcon#read 3, iclass 12, count 0 2006.285.23:53:28.43#ibcon#about to read 4, iclass 12, count 0 2006.285.23:53:28.43#ibcon#read 4, iclass 12, count 0 2006.285.23:53:28.43#ibcon#about to read 5, iclass 12, count 0 2006.285.23:53:28.43#ibcon#read 5, iclass 12, count 0 2006.285.23:53:28.43#ibcon#about to read 6, iclass 12, count 0 2006.285.23:53:28.43#ibcon#read 6, iclass 12, count 0 2006.285.23:53:28.43#ibcon#end of sib2, iclass 12, count 0 2006.285.23:53:28.43#ibcon#*mode == 0, iclass 12, count 0 2006.285.23:53:28.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.285.23:53:28.43#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:53:28.43#ibcon#*before write, iclass 12, count 0 2006.285.23:53:28.43#ibcon#enter sib2, iclass 12, count 0 2006.285.23:53:28.43#ibcon#flushed, iclass 12, count 0 2006.285.23:53:28.43#ibcon#about to write, iclass 12, count 0 2006.285.23:53:28.43#ibcon#wrote, iclass 12, count 0 2006.285.23:53:28.43#ibcon#about to read 3, iclass 12, count 0 2006.285.23:53:28.47#ibcon#read 3, iclass 12, count 0 2006.285.23:53:28.47#ibcon#about to read 4, iclass 12, count 0 2006.285.23:53:28.47#ibcon#read 4, iclass 12, count 0 2006.285.23:53:28.47#ibcon#about to read 5, iclass 12, count 0 2006.285.23:53:28.47#ibcon#read 5, iclass 12, count 0 2006.285.23:53:28.47#ibcon#about to read 6, iclass 12, count 0 2006.285.23:53:28.47#ibcon#read 6, iclass 12, count 0 2006.285.23:53:28.47#ibcon#end of sib2, iclass 12, count 0 2006.285.23:53:28.47#ibcon#*after write, iclass 12, count 0 2006.285.23:53:28.47#ibcon#*before return 0, iclass 12, count 0 2006.285.23:53:28.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:53:28.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.285.23:53:28.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.285.23:53:28.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.285.23:53:28.47$vck44/vb=4,5 2006.285.23:53:28.47#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.285.23:53:28.47#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.285.23:53:28.47#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:28.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.23:53:28.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.285.23:53:28.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.23:53:28.53#ibcon#enter wrdev, iclass 14, count 2 2006.285.23:53:28.53#ibcon#first serial, iclass 14, count 2 2006.285.23:53:28.53#ibcon#enter sib2, iclass 14, count 2 2006.285.23:53:28.53#ibcon#flushed, iclass 14, count 2 2006.285.23:53:28.53#ibcon#about to write, iclass 14, count 2 2006.285.23:53:28.53#ibcon#wrote, iclass 14, count 2 2006.285.23:53:28.53#ibcon#about to read 3, iclass 14, count 2 2006.285.23:53:28.55#ibcon#read 3, iclass 14, count 2 2006.285.23:53:28.55#ibcon#about to read 4, iclass 14, count 2 2006.285.23:53:28.55#ibcon#read 4, iclass 14, count 2 2006.285.23:53:28.55#ibcon#about to read 5, iclass 14, count 2 2006.285.23:53:28.55#ibcon#read 5, iclass 14, count 2 2006.285.23:53:28.55#ibcon#about to read 6, iclass 14, count 2 2006.285.23:53:28.55#ibcon#read 6, iclass 14, count 2 2006.285.23:53:28.55#ibcon#end of sib2, iclass 14, count 2 2006.285.23:53:28.55#ibcon#*mode == 0, iclass 14, count 2 2006.285.23:53:28.55#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.285.23:53:28.55#ibcon#[27=AT04-05\r\n] 2006.285.23:53:28.55#ibcon#*before write, iclass 14, count 2 2006.285.23:53:28.55#ibcon#enter sib2, iclass 14, count 2 2006.285.23:53:28.55#ibcon#flushed, iclass 14, count 2 2006.285.23:53:28.55#ibcon#about to write, iclass 14, count 2 2006.285.23:53:28.55#ibcon#wrote, iclass 14, count 2 2006.285.23:53:28.55#ibcon#about to read 3, iclass 14, count 2 2006.285.23:53:28.58#ibcon#read 3, iclass 14, count 2 2006.285.23:53:28.58#ibcon#about to read 4, iclass 14, count 2 2006.285.23:53:28.58#ibcon#read 4, iclass 14, count 2 2006.285.23:53:28.58#ibcon#about to read 5, iclass 14, count 2 2006.285.23:53:28.58#ibcon#read 5, iclass 14, count 2 2006.285.23:53:28.58#ibcon#about to read 6, iclass 14, count 2 2006.285.23:53:28.58#ibcon#read 6, iclass 14, count 2 2006.285.23:53:28.58#ibcon#end of sib2, iclass 14, count 2 2006.285.23:53:28.58#ibcon#*after write, iclass 14, count 2 2006.285.23:53:28.58#ibcon#*before return 0, iclass 14, count 2 2006.285.23:53:28.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.285.23:53:28.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.285.23:53:28.58#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.285.23:53:28.58#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:28.58#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.23:53:28.70#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.285.23:53:28.70#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.23:53:28.70#ibcon#enter wrdev, iclass 14, count 0 2006.285.23:53:28.70#ibcon#first serial, iclass 14, count 0 2006.285.23:53:28.70#ibcon#enter sib2, iclass 14, count 0 2006.285.23:53:28.70#ibcon#flushed, iclass 14, count 0 2006.285.23:53:28.70#ibcon#about to write, iclass 14, count 0 2006.285.23:53:28.70#ibcon#wrote, iclass 14, count 0 2006.285.23:53:28.70#ibcon#about to read 3, iclass 14, count 0 2006.285.23:53:28.72#ibcon#read 3, iclass 14, count 0 2006.285.23:53:28.72#ibcon#about to read 4, iclass 14, count 0 2006.285.23:53:28.72#ibcon#read 4, iclass 14, count 0 2006.285.23:53:28.72#ibcon#about to read 5, iclass 14, count 0 2006.285.23:53:28.72#ibcon#read 5, iclass 14, count 0 2006.285.23:53:28.72#ibcon#about to read 6, iclass 14, count 0 2006.285.23:53:28.72#ibcon#read 6, iclass 14, count 0 2006.285.23:53:28.72#ibcon#end of sib2, iclass 14, count 0 2006.285.23:53:28.72#ibcon#*mode == 0, iclass 14, count 0 2006.285.23:53:28.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.285.23:53:28.72#ibcon#[27=USB\r\n] 2006.285.23:53:28.72#ibcon#*before write, iclass 14, count 0 2006.285.23:53:28.72#ibcon#enter sib2, iclass 14, count 0 2006.285.23:53:28.72#ibcon#flushed, iclass 14, count 0 2006.285.23:53:28.72#ibcon#about to write, iclass 14, count 0 2006.285.23:53:28.72#ibcon#wrote, iclass 14, count 0 2006.285.23:53:28.72#ibcon#about to read 3, iclass 14, count 0 2006.285.23:53:28.75#ibcon#read 3, iclass 14, count 0 2006.285.23:53:28.75#ibcon#about to read 4, iclass 14, count 0 2006.285.23:53:28.75#ibcon#read 4, iclass 14, count 0 2006.285.23:53:28.75#ibcon#about to read 5, iclass 14, count 0 2006.285.23:53:28.75#ibcon#read 5, iclass 14, count 0 2006.285.23:53:28.75#ibcon#about to read 6, iclass 14, count 0 2006.285.23:53:28.75#ibcon#read 6, iclass 14, count 0 2006.285.23:53:28.75#ibcon#end of sib2, iclass 14, count 0 2006.285.23:53:28.75#ibcon#*after write, iclass 14, count 0 2006.285.23:53:28.75#ibcon#*before return 0, iclass 14, count 0 2006.285.23:53:28.75#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.285.23:53:28.75#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.285.23:53:28.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.285.23:53:28.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.285.23:53:28.75$vck44/vblo=5,709.99 2006.285.23:53:28.75#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.285.23:53:28.75#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.285.23:53:28.75#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:28.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:53:28.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:53:28.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:53:28.75#ibcon#enter wrdev, iclass 16, count 0 2006.285.23:53:28.75#ibcon#first serial, iclass 16, count 0 2006.285.23:53:28.75#ibcon#enter sib2, iclass 16, count 0 2006.285.23:53:28.75#ibcon#flushed, iclass 16, count 0 2006.285.23:53:28.75#ibcon#about to write, iclass 16, count 0 2006.285.23:53:28.75#ibcon#wrote, iclass 16, count 0 2006.285.23:53:28.75#ibcon#about to read 3, iclass 16, count 0 2006.285.23:53:28.77#ibcon#read 3, iclass 16, count 0 2006.285.23:53:28.77#ibcon#about to read 4, iclass 16, count 0 2006.285.23:53:28.77#ibcon#read 4, iclass 16, count 0 2006.285.23:53:28.77#ibcon#about to read 5, iclass 16, count 0 2006.285.23:53:28.77#ibcon#read 5, iclass 16, count 0 2006.285.23:53:28.77#ibcon#about to read 6, iclass 16, count 0 2006.285.23:53:28.77#ibcon#read 6, iclass 16, count 0 2006.285.23:53:28.77#ibcon#end of sib2, iclass 16, count 0 2006.285.23:53:28.77#ibcon#*mode == 0, iclass 16, count 0 2006.285.23:53:28.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.285.23:53:28.77#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:53:28.77#ibcon#*before write, iclass 16, count 0 2006.285.23:53:28.77#ibcon#enter sib2, iclass 16, count 0 2006.285.23:53:28.77#ibcon#flushed, iclass 16, count 0 2006.285.23:53:28.77#ibcon#about to write, iclass 16, count 0 2006.285.23:53:28.77#ibcon#wrote, iclass 16, count 0 2006.285.23:53:28.77#ibcon#about to read 3, iclass 16, count 0 2006.285.23:53:28.81#ibcon#read 3, iclass 16, count 0 2006.285.23:53:28.81#ibcon#about to read 4, iclass 16, count 0 2006.285.23:53:28.81#ibcon#read 4, iclass 16, count 0 2006.285.23:53:28.81#ibcon#about to read 5, iclass 16, count 0 2006.285.23:53:28.81#ibcon#read 5, iclass 16, count 0 2006.285.23:53:28.81#ibcon#about to read 6, iclass 16, count 0 2006.285.23:53:28.81#ibcon#read 6, iclass 16, count 0 2006.285.23:53:28.81#ibcon#end of sib2, iclass 16, count 0 2006.285.23:53:28.81#ibcon#*after write, iclass 16, count 0 2006.285.23:53:28.81#ibcon#*before return 0, iclass 16, count 0 2006.285.23:53:28.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:53:28.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.285.23:53:28.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.285.23:53:28.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.285.23:53:28.81$vck44/vb=5,4 2006.285.23:53:28.81#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.285.23:53:28.81#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.285.23:53:28.81#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:28.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:53:28.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:53:28.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:53:28.87#ibcon#enter wrdev, iclass 18, count 2 2006.285.23:53:28.87#ibcon#first serial, iclass 18, count 2 2006.285.23:53:28.87#ibcon#enter sib2, iclass 18, count 2 2006.285.23:53:28.87#ibcon#flushed, iclass 18, count 2 2006.285.23:53:28.87#ibcon#about to write, iclass 18, count 2 2006.285.23:53:28.87#ibcon#wrote, iclass 18, count 2 2006.285.23:53:28.87#ibcon#about to read 3, iclass 18, count 2 2006.285.23:53:28.89#ibcon#read 3, iclass 18, count 2 2006.285.23:53:28.89#ibcon#about to read 4, iclass 18, count 2 2006.285.23:53:28.89#ibcon#read 4, iclass 18, count 2 2006.285.23:53:28.89#ibcon#about to read 5, iclass 18, count 2 2006.285.23:53:28.89#ibcon#read 5, iclass 18, count 2 2006.285.23:53:28.89#ibcon#about to read 6, iclass 18, count 2 2006.285.23:53:28.89#ibcon#read 6, iclass 18, count 2 2006.285.23:53:28.89#ibcon#end of sib2, iclass 18, count 2 2006.285.23:53:28.89#ibcon#*mode == 0, iclass 18, count 2 2006.285.23:53:28.89#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.285.23:53:28.89#ibcon#[27=AT05-04\r\n] 2006.285.23:53:28.89#ibcon#*before write, iclass 18, count 2 2006.285.23:53:28.89#ibcon#enter sib2, iclass 18, count 2 2006.285.23:53:28.89#ibcon#flushed, iclass 18, count 2 2006.285.23:53:28.89#ibcon#about to write, iclass 18, count 2 2006.285.23:53:28.89#ibcon#wrote, iclass 18, count 2 2006.285.23:53:28.89#ibcon#about to read 3, iclass 18, count 2 2006.285.23:53:28.92#ibcon#read 3, iclass 18, count 2 2006.285.23:53:28.92#ibcon#about to read 4, iclass 18, count 2 2006.285.23:53:28.92#ibcon#read 4, iclass 18, count 2 2006.285.23:53:28.92#ibcon#about to read 5, iclass 18, count 2 2006.285.23:53:28.92#ibcon#read 5, iclass 18, count 2 2006.285.23:53:28.92#ibcon#about to read 6, iclass 18, count 2 2006.285.23:53:28.92#ibcon#read 6, iclass 18, count 2 2006.285.23:53:28.92#ibcon#end of sib2, iclass 18, count 2 2006.285.23:53:28.92#ibcon#*after write, iclass 18, count 2 2006.285.23:53:28.92#ibcon#*before return 0, iclass 18, count 2 2006.285.23:53:28.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:53:28.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.285.23:53:28.92#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.285.23:53:28.92#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:28.92#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:53:29.04#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:53:29.04#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:53:29.04#ibcon#enter wrdev, iclass 18, count 0 2006.285.23:53:29.04#ibcon#first serial, iclass 18, count 0 2006.285.23:53:29.04#ibcon#enter sib2, iclass 18, count 0 2006.285.23:53:29.04#ibcon#flushed, iclass 18, count 0 2006.285.23:53:29.04#ibcon#about to write, iclass 18, count 0 2006.285.23:53:29.04#ibcon#wrote, iclass 18, count 0 2006.285.23:53:29.04#ibcon#about to read 3, iclass 18, count 0 2006.285.23:53:29.06#ibcon#read 3, iclass 18, count 0 2006.285.23:53:29.06#ibcon#about to read 4, iclass 18, count 0 2006.285.23:53:29.06#ibcon#read 4, iclass 18, count 0 2006.285.23:53:29.06#ibcon#about to read 5, iclass 18, count 0 2006.285.23:53:29.06#ibcon#read 5, iclass 18, count 0 2006.285.23:53:29.06#ibcon#about to read 6, iclass 18, count 0 2006.285.23:53:29.06#ibcon#read 6, iclass 18, count 0 2006.285.23:53:29.06#ibcon#end of sib2, iclass 18, count 0 2006.285.23:53:29.06#ibcon#*mode == 0, iclass 18, count 0 2006.285.23:53:29.06#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.285.23:53:29.06#ibcon#[27=USB\r\n] 2006.285.23:53:29.06#ibcon#*before write, iclass 18, count 0 2006.285.23:53:29.06#ibcon#enter sib2, iclass 18, count 0 2006.285.23:53:29.06#ibcon#flushed, iclass 18, count 0 2006.285.23:53:29.06#ibcon#about to write, iclass 18, count 0 2006.285.23:53:29.06#ibcon#wrote, iclass 18, count 0 2006.285.23:53:29.06#ibcon#about to read 3, iclass 18, count 0 2006.285.23:53:29.09#ibcon#read 3, iclass 18, count 0 2006.285.23:53:29.09#ibcon#about to read 4, iclass 18, count 0 2006.285.23:53:29.09#ibcon#read 4, iclass 18, count 0 2006.285.23:53:29.09#ibcon#about to read 5, iclass 18, count 0 2006.285.23:53:29.09#ibcon#read 5, iclass 18, count 0 2006.285.23:53:29.09#ibcon#about to read 6, iclass 18, count 0 2006.285.23:53:29.09#ibcon#read 6, iclass 18, count 0 2006.285.23:53:29.09#ibcon#end of sib2, iclass 18, count 0 2006.285.23:53:29.09#ibcon#*after write, iclass 18, count 0 2006.285.23:53:29.09#ibcon#*before return 0, iclass 18, count 0 2006.285.23:53:29.09#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:53:29.09#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.285.23:53:29.09#ibcon#about to clear, iclass 18 cls_cnt 0 2006.285.23:53:29.09#ibcon#cleared, iclass 18 cls_cnt 0 2006.285.23:53:29.09$vck44/vblo=6,719.99 2006.285.23:53:29.09#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.285.23:53:29.09#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.285.23:53:29.09#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:29.09#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:53:29.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:53:29.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:53:29.09#ibcon#enter wrdev, iclass 20, count 0 2006.285.23:53:29.09#ibcon#first serial, iclass 20, count 0 2006.285.23:53:29.09#ibcon#enter sib2, iclass 20, count 0 2006.285.23:53:29.09#ibcon#flushed, iclass 20, count 0 2006.285.23:53:29.09#ibcon#about to write, iclass 20, count 0 2006.285.23:53:29.09#ibcon#wrote, iclass 20, count 0 2006.285.23:53:29.09#ibcon#about to read 3, iclass 20, count 0 2006.285.23:53:29.11#ibcon#read 3, iclass 20, count 0 2006.285.23:53:29.11#ibcon#about to read 4, iclass 20, count 0 2006.285.23:53:29.11#ibcon#read 4, iclass 20, count 0 2006.285.23:53:29.11#ibcon#about to read 5, iclass 20, count 0 2006.285.23:53:29.11#ibcon#read 5, iclass 20, count 0 2006.285.23:53:29.11#ibcon#about to read 6, iclass 20, count 0 2006.285.23:53:29.11#ibcon#read 6, iclass 20, count 0 2006.285.23:53:29.11#ibcon#end of sib2, iclass 20, count 0 2006.285.23:53:29.11#ibcon#*mode == 0, iclass 20, count 0 2006.285.23:53:29.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.285.23:53:29.11#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:53:29.11#ibcon#*before write, iclass 20, count 0 2006.285.23:53:29.11#ibcon#enter sib2, iclass 20, count 0 2006.285.23:53:29.11#ibcon#flushed, iclass 20, count 0 2006.285.23:53:29.11#ibcon#about to write, iclass 20, count 0 2006.285.23:53:29.11#ibcon#wrote, iclass 20, count 0 2006.285.23:53:29.11#ibcon#about to read 3, iclass 20, count 0 2006.285.23:53:29.15#ibcon#read 3, iclass 20, count 0 2006.285.23:53:29.15#ibcon#about to read 4, iclass 20, count 0 2006.285.23:53:29.15#ibcon#read 4, iclass 20, count 0 2006.285.23:53:29.15#ibcon#about to read 5, iclass 20, count 0 2006.285.23:53:29.15#ibcon#read 5, iclass 20, count 0 2006.285.23:53:29.15#ibcon#about to read 6, iclass 20, count 0 2006.285.23:53:29.15#ibcon#read 6, iclass 20, count 0 2006.285.23:53:29.15#ibcon#end of sib2, iclass 20, count 0 2006.285.23:53:29.15#ibcon#*after write, iclass 20, count 0 2006.285.23:53:29.15#ibcon#*before return 0, iclass 20, count 0 2006.285.23:53:29.15#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:53:29.15#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.285.23:53:29.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.285.23:53:29.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.285.23:53:29.15$vck44/vb=6,3 2006.285.23:53:29.15#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.285.23:53:29.15#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.285.23:53:29.15#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:29.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:53:29.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:53:29.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:53:29.21#ibcon#enter wrdev, iclass 22, count 2 2006.285.23:53:29.21#ibcon#first serial, iclass 22, count 2 2006.285.23:53:29.21#ibcon#enter sib2, iclass 22, count 2 2006.285.23:53:29.21#ibcon#flushed, iclass 22, count 2 2006.285.23:53:29.21#ibcon#about to write, iclass 22, count 2 2006.285.23:53:29.21#ibcon#wrote, iclass 22, count 2 2006.285.23:53:29.21#ibcon#about to read 3, iclass 22, count 2 2006.285.23:53:29.23#ibcon#read 3, iclass 22, count 2 2006.285.23:53:29.23#ibcon#about to read 4, iclass 22, count 2 2006.285.23:53:29.23#ibcon#read 4, iclass 22, count 2 2006.285.23:53:29.23#ibcon#about to read 5, iclass 22, count 2 2006.285.23:53:29.23#ibcon#read 5, iclass 22, count 2 2006.285.23:53:29.23#ibcon#about to read 6, iclass 22, count 2 2006.285.23:53:29.23#ibcon#read 6, iclass 22, count 2 2006.285.23:53:29.23#ibcon#end of sib2, iclass 22, count 2 2006.285.23:53:29.23#ibcon#*mode == 0, iclass 22, count 2 2006.285.23:53:29.23#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.285.23:53:29.23#ibcon#[27=AT06-03\r\n] 2006.285.23:53:29.23#ibcon#*before write, iclass 22, count 2 2006.285.23:53:29.23#ibcon#enter sib2, iclass 22, count 2 2006.285.23:53:29.23#ibcon#flushed, iclass 22, count 2 2006.285.23:53:29.23#ibcon#about to write, iclass 22, count 2 2006.285.23:53:29.23#ibcon#wrote, iclass 22, count 2 2006.285.23:53:29.23#ibcon#about to read 3, iclass 22, count 2 2006.285.23:53:29.26#ibcon#read 3, iclass 22, count 2 2006.285.23:53:29.26#ibcon#about to read 4, iclass 22, count 2 2006.285.23:53:29.26#ibcon#read 4, iclass 22, count 2 2006.285.23:53:29.26#ibcon#about to read 5, iclass 22, count 2 2006.285.23:53:29.26#ibcon#read 5, iclass 22, count 2 2006.285.23:53:29.26#ibcon#about to read 6, iclass 22, count 2 2006.285.23:53:29.26#ibcon#read 6, iclass 22, count 2 2006.285.23:53:29.26#ibcon#end of sib2, iclass 22, count 2 2006.285.23:53:29.26#ibcon#*after write, iclass 22, count 2 2006.285.23:53:29.26#ibcon#*before return 0, iclass 22, count 2 2006.285.23:53:29.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:53:29.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.285.23:53:29.26#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.285.23:53:29.26#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:29.26#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:53:29.38#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:53:29.38#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:53:29.38#ibcon#enter wrdev, iclass 22, count 0 2006.285.23:53:29.38#ibcon#first serial, iclass 22, count 0 2006.285.23:53:29.38#ibcon#enter sib2, iclass 22, count 0 2006.285.23:53:29.38#ibcon#flushed, iclass 22, count 0 2006.285.23:53:29.38#ibcon#about to write, iclass 22, count 0 2006.285.23:53:29.38#ibcon#wrote, iclass 22, count 0 2006.285.23:53:29.38#ibcon#about to read 3, iclass 22, count 0 2006.285.23:53:29.40#ibcon#read 3, iclass 22, count 0 2006.285.23:53:29.40#ibcon#about to read 4, iclass 22, count 0 2006.285.23:53:29.40#ibcon#read 4, iclass 22, count 0 2006.285.23:53:29.40#ibcon#about to read 5, iclass 22, count 0 2006.285.23:53:29.40#ibcon#read 5, iclass 22, count 0 2006.285.23:53:29.40#ibcon#about to read 6, iclass 22, count 0 2006.285.23:53:29.40#ibcon#read 6, iclass 22, count 0 2006.285.23:53:29.40#ibcon#end of sib2, iclass 22, count 0 2006.285.23:53:29.40#ibcon#*mode == 0, iclass 22, count 0 2006.285.23:53:29.40#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.285.23:53:29.40#ibcon#[27=USB\r\n] 2006.285.23:53:29.40#ibcon#*before write, iclass 22, count 0 2006.285.23:53:29.40#ibcon#enter sib2, iclass 22, count 0 2006.285.23:53:29.40#ibcon#flushed, iclass 22, count 0 2006.285.23:53:29.40#ibcon#about to write, iclass 22, count 0 2006.285.23:53:29.40#ibcon#wrote, iclass 22, count 0 2006.285.23:53:29.40#ibcon#about to read 3, iclass 22, count 0 2006.285.23:53:29.43#ibcon#read 3, iclass 22, count 0 2006.285.23:53:29.43#ibcon#about to read 4, iclass 22, count 0 2006.285.23:53:29.43#ibcon#read 4, iclass 22, count 0 2006.285.23:53:29.43#ibcon#about to read 5, iclass 22, count 0 2006.285.23:53:29.43#ibcon#read 5, iclass 22, count 0 2006.285.23:53:29.43#ibcon#about to read 6, iclass 22, count 0 2006.285.23:53:29.43#ibcon#read 6, iclass 22, count 0 2006.285.23:53:29.43#ibcon#end of sib2, iclass 22, count 0 2006.285.23:53:29.43#ibcon#*after write, iclass 22, count 0 2006.285.23:53:29.43#ibcon#*before return 0, iclass 22, count 0 2006.285.23:53:29.43#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:53:29.43#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.285.23:53:29.43#ibcon#about to clear, iclass 22 cls_cnt 0 2006.285.23:53:29.43#ibcon#cleared, iclass 22 cls_cnt 0 2006.285.23:53:29.43$vck44/vblo=7,734.99 2006.285.23:53:29.43#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.285.23:53:29.43#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.285.23:53:29.43#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:29.43#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:53:29.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:53:29.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:53:29.43#ibcon#enter wrdev, iclass 24, count 0 2006.285.23:53:29.43#ibcon#first serial, iclass 24, count 0 2006.285.23:53:29.43#ibcon#enter sib2, iclass 24, count 0 2006.285.23:53:29.43#ibcon#flushed, iclass 24, count 0 2006.285.23:53:29.43#ibcon#about to write, iclass 24, count 0 2006.285.23:53:29.43#ibcon#wrote, iclass 24, count 0 2006.285.23:53:29.43#ibcon#about to read 3, iclass 24, count 0 2006.285.23:53:29.45#ibcon#read 3, iclass 24, count 0 2006.285.23:53:29.45#ibcon#about to read 4, iclass 24, count 0 2006.285.23:53:29.45#ibcon#read 4, iclass 24, count 0 2006.285.23:53:29.45#ibcon#about to read 5, iclass 24, count 0 2006.285.23:53:29.45#ibcon#read 5, iclass 24, count 0 2006.285.23:53:29.45#ibcon#about to read 6, iclass 24, count 0 2006.285.23:53:29.45#ibcon#read 6, iclass 24, count 0 2006.285.23:53:29.45#ibcon#end of sib2, iclass 24, count 0 2006.285.23:53:29.45#ibcon#*mode == 0, iclass 24, count 0 2006.285.23:53:29.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.285.23:53:29.45#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:53:29.45#ibcon#*before write, iclass 24, count 0 2006.285.23:53:29.45#ibcon#enter sib2, iclass 24, count 0 2006.285.23:53:29.45#ibcon#flushed, iclass 24, count 0 2006.285.23:53:29.45#ibcon#about to write, iclass 24, count 0 2006.285.23:53:29.45#ibcon#wrote, iclass 24, count 0 2006.285.23:53:29.45#ibcon#about to read 3, iclass 24, count 0 2006.285.23:53:29.49#ibcon#read 3, iclass 24, count 0 2006.285.23:53:29.49#ibcon#about to read 4, iclass 24, count 0 2006.285.23:53:29.49#ibcon#read 4, iclass 24, count 0 2006.285.23:53:29.49#ibcon#about to read 5, iclass 24, count 0 2006.285.23:53:29.49#ibcon#read 5, iclass 24, count 0 2006.285.23:53:29.49#ibcon#about to read 6, iclass 24, count 0 2006.285.23:53:29.49#ibcon#read 6, iclass 24, count 0 2006.285.23:53:29.49#ibcon#end of sib2, iclass 24, count 0 2006.285.23:53:29.49#ibcon#*after write, iclass 24, count 0 2006.285.23:53:29.49#ibcon#*before return 0, iclass 24, count 0 2006.285.23:53:29.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:53:29.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.285.23:53:29.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.285.23:53:29.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.285.23:53:29.49$vck44/vb=7,4 2006.285.23:53:29.49#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.285.23:53:29.49#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.285.23:53:29.49#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:29.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:53:29.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:53:29.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:53:29.55#ibcon#enter wrdev, iclass 26, count 2 2006.285.23:53:29.55#ibcon#first serial, iclass 26, count 2 2006.285.23:53:29.55#ibcon#enter sib2, iclass 26, count 2 2006.285.23:53:29.55#ibcon#flushed, iclass 26, count 2 2006.285.23:53:29.55#ibcon#about to write, iclass 26, count 2 2006.285.23:53:29.55#ibcon#wrote, iclass 26, count 2 2006.285.23:53:29.55#ibcon#about to read 3, iclass 26, count 2 2006.285.23:53:29.57#ibcon#read 3, iclass 26, count 2 2006.285.23:53:29.57#ibcon#about to read 4, iclass 26, count 2 2006.285.23:53:29.57#ibcon#read 4, iclass 26, count 2 2006.285.23:53:29.57#ibcon#about to read 5, iclass 26, count 2 2006.285.23:53:29.57#ibcon#read 5, iclass 26, count 2 2006.285.23:53:29.57#ibcon#about to read 6, iclass 26, count 2 2006.285.23:53:29.57#ibcon#read 6, iclass 26, count 2 2006.285.23:53:29.57#ibcon#end of sib2, iclass 26, count 2 2006.285.23:53:29.57#ibcon#*mode == 0, iclass 26, count 2 2006.285.23:53:29.57#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.285.23:53:29.57#ibcon#[27=AT07-04\r\n] 2006.285.23:53:29.57#ibcon#*before write, iclass 26, count 2 2006.285.23:53:29.57#ibcon#enter sib2, iclass 26, count 2 2006.285.23:53:29.57#ibcon#flushed, iclass 26, count 2 2006.285.23:53:29.57#ibcon#about to write, iclass 26, count 2 2006.285.23:53:29.57#ibcon#wrote, iclass 26, count 2 2006.285.23:53:29.57#ibcon#about to read 3, iclass 26, count 2 2006.285.23:53:29.60#ibcon#read 3, iclass 26, count 2 2006.285.23:53:29.60#ibcon#about to read 4, iclass 26, count 2 2006.285.23:53:29.60#ibcon#read 4, iclass 26, count 2 2006.285.23:53:29.60#ibcon#about to read 5, iclass 26, count 2 2006.285.23:53:29.60#ibcon#read 5, iclass 26, count 2 2006.285.23:53:29.60#ibcon#about to read 6, iclass 26, count 2 2006.285.23:53:29.60#ibcon#read 6, iclass 26, count 2 2006.285.23:53:29.60#ibcon#end of sib2, iclass 26, count 2 2006.285.23:53:29.60#ibcon#*after write, iclass 26, count 2 2006.285.23:53:29.60#ibcon#*before return 0, iclass 26, count 2 2006.285.23:53:29.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:53:29.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.285.23:53:29.60#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.285.23:53:29.60#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:29.60#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:53:29.72#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:53:29.72#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:53:29.72#ibcon#enter wrdev, iclass 26, count 0 2006.285.23:53:29.72#ibcon#first serial, iclass 26, count 0 2006.285.23:53:29.72#ibcon#enter sib2, iclass 26, count 0 2006.285.23:53:29.72#ibcon#flushed, iclass 26, count 0 2006.285.23:53:29.72#ibcon#about to write, iclass 26, count 0 2006.285.23:53:29.72#ibcon#wrote, iclass 26, count 0 2006.285.23:53:29.72#ibcon#about to read 3, iclass 26, count 0 2006.285.23:53:29.74#ibcon#read 3, iclass 26, count 0 2006.285.23:53:29.74#ibcon#about to read 4, iclass 26, count 0 2006.285.23:53:29.74#ibcon#read 4, iclass 26, count 0 2006.285.23:53:29.74#ibcon#about to read 5, iclass 26, count 0 2006.285.23:53:29.74#ibcon#read 5, iclass 26, count 0 2006.285.23:53:29.74#ibcon#about to read 6, iclass 26, count 0 2006.285.23:53:29.74#ibcon#read 6, iclass 26, count 0 2006.285.23:53:29.74#ibcon#end of sib2, iclass 26, count 0 2006.285.23:53:29.74#ibcon#*mode == 0, iclass 26, count 0 2006.285.23:53:29.74#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.285.23:53:29.74#ibcon#[27=USB\r\n] 2006.285.23:53:29.74#ibcon#*before write, iclass 26, count 0 2006.285.23:53:29.74#ibcon#enter sib2, iclass 26, count 0 2006.285.23:53:29.74#ibcon#flushed, iclass 26, count 0 2006.285.23:53:29.74#ibcon#about to write, iclass 26, count 0 2006.285.23:53:29.74#ibcon#wrote, iclass 26, count 0 2006.285.23:53:29.74#ibcon#about to read 3, iclass 26, count 0 2006.285.23:53:29.77#ibcon#read 3, iclass 26, count 0 2006.285.23:53:29.77#ibcon#about to read 4, iclass 26, count 0 2006.285.23:53:29.77#ibcon#read 4, iclass 26, count 0 2006.285.23:53:29.77#ibcon#about to read 5, iclass 26, count 0 2006.285.23:53:29.77#ibcon#read 5, iclass 26, count 0 2006.285.23:53:29.77#ibcon#about to read 6, iclass 26, count 0 2006.285.23:53:29.77#ibcon#read 6, iclass 26, count 0 2006.285.23:53:29.77#ibcon#end of sib2, iclass 26, count 0 2006.285.23:53:29.77#ibcon#*after write, iclass 26, count 0 2006.285.23:53:29.77#ibcon#*before return 0, iclass 26, count 0 2006.285.23:53:29.77#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:53:29.77#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.285.23:53:29.77#ibcon#about to clear, iclass 26 cls_cnt 0 2006.285.23:53:29.77#ibcon#cleared, iclass 26 cls_cnt 0 2006.285.23:53:29.77$vck44/vblo=8,744.99 2006.285.23:53:29.77#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.285.23:53:29.77#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.285.23:53:29.77#ibcon#ireg 17 cls_cnt 0 2006.285.23:53:29.77#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:53:29.77#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:53:29.77#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:53:29.77#ibcon#enter wrdev, iclass 28, count 0 2006.285.23:53:29.77#ibcon#first serial, iclass 28, count 0 2006.285.23:53:29.77#ibcon#enter sib2, iclass 28, count 0 2006.285.23:53:29.77#ibcon#flushed, iclass 28, count 0 2006.285.23:53:29.77#ibcon#about to write, iclass 28, count 0 2006.285.23:53:29.77#ibcon#wrote, iclass 28, count 0 2006.285.23:53:29.77#ibcon#about to read 3, iclass 28, count 0 2006.285.23:53:29.79#ibcon#read 3, iclass 28, count 0 2006.285.23:53:29.79#ibcon#about to read 4, iclass 28, count 0 2006.285.23:53:29.79#ibcon#read 4, iclass 28, count 0 2006.285.23:53:29.79#ibcon#about to read 5, iclass 28, count 0 2006.285.23:53:29.79#ibcon#read 5, iclass 28, count 0 2006.285.23:53:29.79#ibcon#about to read 6, iclass 28, count 0 2006.285.23:53:29.79#ibcon#read 6, iclass 28, count 0 2006.285.23:53:29.79#ibcon#end of sib2, iclass 28, count 0 2006.285.23:53:29.79#ibcon#*mode == 0, iclass 28, count 0 2006.285.23:53:29.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.285.23:53:29.79#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:53:29.79#ibcon#*before write, iclass 28, count 0 2006.285.23:53:29.79#ibcon#enter sib2, iclass 28, count 0 2006.285.23:53:29.79#ibcon#flushed, iclass 28, count 0 2006.285.23:53:29.79#ibcon#about to write, iclass 28, count 0 2006.285.23:53:29.79#ibcon#wrote, iclass 28, count 0 2006.285.23:53:29.79#ibcon#about to read 3, iclass 28, count 0 2006.285.23:53:29.83#ibcon#read 3, iclass 28, count 0 2006.285.23:53:29.83#ibcon#about to read 4, iclass 28, count 0 2006.285.23:53:29.83#ibcon#read 4, iclass 28, count 0 2006.285.23:53:29.83#ibcon#about to read 5, iclass 28, count 0 2006.285.23:53:29.83#ibcon#read 5, iclass 28, count 0 2006.285.23:53:29.83#ibcon#about to read 6, iclass 28, count 0 2006.285.23:53:29.83#ibcon#read 6, iclass 28, count 0 2006.285.23:53:29.83#ibcon#end of sib2, iclass 28, count 0 2006.285.23:53:29.83#ibcon#*after write, iclass 28, count 0 2006.285.23:53:29.83#ibcon#*before return 0, iclass 28, count 0 2006.285.23:53:29.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:53:29.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.285.23:53:29.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.285.23:53:29.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.285.23:53:29.83$vck44/vb=8,4 2006.285.23:53:29.83#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.285.23:53:29.83#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.285.23:53:29.83#ibcon#ireg 11 cls_cnt 2 2006.285.23:53:29.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:53:29.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:53:29.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:53:29.89#ibcon#enter wrdev, iclass 30, count 2 2006.285.23:53:29.89#ibcon#first serial, iclass 30, count 2 2006.285.23:53:29.89#ibcon#enter sib2, iclass 30, count 2 2006.285.23:53:29.89#ibcon#flushed, iclass 30, count 2 2006.285.23:53:29.89#ibcon#about to write, iclass 30, count 2 2006.285.23:53:29.89#ibcon#wrote, iclass 30, count 2 2006.285.23:53:29.89#ibcon#about to read 3, iclass 30, count 2 2006.285.23:53:29.91#ibcon#read 3, iclass 30, count 2 2006.285.23:53:29.91#ibcon#about to read 4, iclass 30, count 2 2006.285.23:53:29.91#ibcon#read 4, iclass 30, count 2 2006.285.23:53:29.91#ibcon#about to read 5, iclass 30, count 2 2006.285.23:53:29.91#ibcon#read 5, iclass 30, count 2 2006.285.23:53:29.91#ibcon#about to read 6, iclass 30, count 2 2006.285.23:53:29.91#ibcon#read 6, iclass 30, count 2 2006.285.23:53:29.91#ibcon#end of sib2, iclass 30, count 2 2006.285.23:53:29.91#ibcon#*mode == 0, iclass 30, count 2 2006.285.23:53:29.91#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.285.23:53:29.91#ibcon#[27=AT08-04\r\n] 2006.285.23:53:29.91#ibcon#*before write, iclass 30, count 2 2006.285.23:53:29.91#ibcon#enter sib2, iclass 30, count 2 2006.285.23:53:29.91#ibcon#flushed, iclass 30, count 2 2006.285.23:53:29.91#ibcon#about to write, iclass 30, count 2 2006.285.23:53:29.91#ibcon#wrote, iclass 30, count 2 2006.285.23:53:29.91#ibcon#about to read 3, iclass 30, count 2 2006.285.23:53:29.94#ibcon#read 3, iclass 30, count 2 2006.285.23:53:29.94#ibcon#about to read 4, iclass 30, count 2 2006.285.23:53:29.94#ibcon#read 4, iclass 30, count 2 2006.285.23:53:29.94#ibcon#about to read 5, iclass 30, count 2 2006.285.23:53:29.94#ibcon#read 5, iclass 30, count 2 2006.285.23:53:29.94#ibcon#about to read 6, iclass 30, count 2 2006.285.23:53:29.94#ibcon#read 6, iclass 30, count 2 2006.285.23:53:29.94#ibcon#end of sib2, iclass 30, count 2 2006.285.23:53:29.94#ibcon#*after write, iclass 30, count 2 2006.285.23:53:29.94#ibcon#*before return 0, iclass 30, count 2 2006.285.23:53:29.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:53:29.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.285.23:53:29.94#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.285.23:53:29.94#ibcon#ireg 7 cls_cnt 0 2006.285.23:53:29.94#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:53:30.06#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:53:30.06#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:53:30.06#ibcon#enter wrdev, iclass 30, count 0 2006.285.23:53:30.06#ibcon#first serial, iclass 30, count 0 2006.285.23:53:30.06#ibcon#enter sib2, iclass 30, count 0 2006.285.23:53:30.06#ibcon#flushed, iclass 30, count 0 2006.285.23:53:30.06#ibcon#about to write, iclass 30, count 0 2006.285.23:53:30.06#ibcon#wrote, iclass 30, count 0 2006.285.23:53:30.06#ibcon#about to read 3, iclass 30, count 0 2006.285.23:53:30.08#ibcon#read 3, iclass 30, count 0 2006.285.23:53:30.08#ibcon#about to read 4, iclass 30, count 0 2006.285.23:53:30.08#ibcon#read 4, iclass 30, count 0 2006.285.23:53:30.08#ibcon#about to read 5, iclass 30, count 0 2006.285.23:53:30.08#ibcon#read 5, iclass 30, count 0 2006.285.23:53:30.08#ibcon#about to read 6, iclass 30, count 0 2006.285.23:53:30.08#ibcon#read 6, iclass 30, count 0 2006.285.23:53:30.08#ibcon#end of sib2, iclass 30, count 0 2006.285.23:53:30.08#ibcon#*mode == 0, iclass 30, count 0 2006.285.23:53:30.08#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.285.23:53:30.08#ibcon#[27=USB\r\n] 2006.285.23:53:30.08#ibcon#*before write, iclass 30, count 0 2006.285.23:53:30.08#ibcon#enter sib2, iclass 30, count 0 2006.285.23:53:30.08#ibcon#flushed, iclass 30, count 0 2006.285.23:53:30.08#ibcon#about to write, iclass 30, count 0 2006.285.23:53:30.08#ibcon#wrote, iclass 30, count 0 2006.285.23:53:30.08#ibcon#about to read 3, iclass 30, count 0 2006.285.23:53:30.11#ibcon#read 3, iclass 30, count 0 2006.285.23:53:30.11#ibcon#about to read 4, iclass 30, count 0 2006.285.23:53:30.11#ibcon#read 4, iclass 30, count 0 2006.285.23:53:30.11#ibcon#about to read 5, iclass 30, count 0 2006.285.23:53:30.11#ibcon#read 5, iclass 30, count 0 2006.285.23:53:30.11#ibcon#about to read 6, iclass 30, count 0 2006.285.23:53:30.11#ibcon#read 6, iclass 30, count 0 2006.285.23:53:30.11#ibcon#end of sib2, iclass 30, count 0 2006.285.23:53:30.11#ibcon#*after write, iclass 30, count 0 2006.285.23:53:30.11#ibcon#*before return 0, iclass 30, count 0 2006.285.23:53:30.11#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:53:30.11#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.285.23:53:30.11#ibcon#about to clear, iclass 30 cls_cnt 0 2006.285.23:53:30.11#ibcon#cleared, iclass 30 cls_cnt 0 2006.285.23:53:30.11$vck44/vabw=wide 2006.285.23:53:30.11#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.285.23:53:30.11#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.285.23:53:30.11#ibcon#ireg 8 cls_cnt 0 2006.285.23:53:30.11#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:53:30.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:53:30.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:53:30.11#ibcon#enter wrdev, iclass 32, count 0 2006.285.23:53:30.11#ibcon#first serial, iclass 32, count 0 2006.285.23:53:30.11#ibcon#enter sib2, iclass 32, count 0 2006.285.23:53:30.11#ibcon#flushed, iclass 32, count 0 2006.285.23:53:30.11#ibcon#about to write, iclass 32, count 0 2006.285.23:53:30.11#ibcon#wrote, iclass 32, count 0 2006.285.23:53:30.11#ibcon#about to read 3, iclass 32, count 0 2006.285.23:53:30.13#ibcon#read 3, iclass 32, count 0 2006.285.23:53:30.13#ibcon#about to read 4, iclass 32, count 0 2006.285.23:53:30.13#ibcon#read 4, iclass 32, count 0 2006.285.23:53:30.13#ibcon#about to read 5, iclass 32, count 0 2006.285.23:53:30.13#ibcon#read 5, iclass 32, count 0 2006.285.23:53:30.13#ibcon#about to read 6, iclass 32, count 0 2006.285.23:53:30.13#ibcon#read 6, iclass 32, count 0 2006.285.23:53:30.13#ibcon#end of sib2, iclass 32, count 0 2006.285.23:53:30.13#ibcon#*mode == 0, iclass 32, count 0 2006.285.23:53:30.13#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.285.23:53:30.13#ibcon#[25=BW32\r\n] 2006.285.23:53:30.13#ibcon#*before write, iclass 32, count 0 2006.285.23:53:30.13#ibcon#enter sib2, iclass 32, count 0 2006.285.23:53:30.13#ibcon#flushed, iclass 32, count 0 2006.285.23:53:30.13#ibcon#about to write, iclass 32, count 0 2006.285.23:53:30.13#ibcon#wrote, iclass 32, count 0 2006.285.23:53:30.13#ibcon#about to read 3, iclass 32, count 0 2006.285.23:53:30.16#ibcon#read 3, iclass 32, count 0 2006.285.23:53:30.16#ibcon#about to read 4, iclass 32, count 0 2006.285.23:53:30.16#ibcon#read 4, iclass 32, count 0 2006.285.23:53:30.16#ibcon#about to read 5, iclass 32, count 0 2006.285.23:53:30.16#ibcon#read 5, iclass 32, count 0 2006.285.23:53:30.16#ibcon#about to read 6, iclass 32, count 0 2006.285.23:53:30.16#ibcon#read 6, iclass 32, count 0 2006.285.23:53:30.16#ibcon#end of sib2, iclass 32, count 0 2006.285.23:53:30.16#ibcon#*after write, iclass 32, count 0 2006.285.23:53:30.16#ibcon#*before return 0, iclass 32, count 0 2006.285.23:53:30.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:53:30.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.285.23:53:30.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.285.23:53:30.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.285.23:53:30.16$vck44/vbbw=wide 2006.285.23:53:30.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.285.23:53:30.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.285.23:53:30.16#ibcon#ireg 8 cls_cnt 0 2006.285.23:53:30.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:53:30.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:53:30.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:53:30.23#ibcon#enter wrdev, iclass 34, count 0 2006.285.23:53:30.23#ibcon#first serial, iclass 34, count 0 2006.285.23:53:30.23#ibcon#enter sib2, iclass 34, count 0 2006.285.23:53:30.23#ibcon#flushed, iclass 34, count 0 2006.285.23:53:30.23#ibcon#about to write, iclass 34, count 0 2006.285.23:53:30.23#ibcon#wrote, iclass 34, count 0 2006.285.23:53:30.23#ibcon#about to read 3, iclass 34, count 0 2006.285.23:53:30.25#ibcon#read 3, iclass 34, count 0 2006.285.23:53:30.25#ibcon#about to read 4, iclass 34, count 0 2006.285.23:53:30.25#ibcon#read 4, iclass 34, count 0 2006.285.23:53:30.25#ibcon#about to read 5, iclass 34, count 0 2006.285.23:53:30.25#ibcon#read 5, iclass 34, count 0 2006.285.23:53:30.25#ibcon#about to read 6, iclass 34, count 0 2006.285.23:53:30.25#ibcon#read 6, iclass 34, count 0 2006.285.23:53:30.25#ibcon#end of sib2, iclass 34, count 0 2006.285.23:53:30.25#ibcon#*mode == 0, iclass 34, count 0 2006.285.23:53:30.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.285.23:53:30.25#ibcon#[27=BW32\r\n] 2006.285.23:53:30.25#ibcon#*before write, iclass 34, count 0 2006.285.23:53:30.25#ibcon#enter sib2, iclass 34, count 0 2006.285.23:53:30.25#ibcon#flushed, iclass 34, count 0 2006.285.23:53:30.25#ibcon#about to write, iclass 34, count 0 2006.285.23:53:30.25#ibcon#wrote, iclass 34, count 0 2006.285.23:53:30.25#ibcon#about to read 3, iclass 34, count 0 2006.285.23:53:30.28#ibcon#read 3, iclass 34, count 0 2006.285.23:53:30.28#ibcon#about to read 4, iclass 34, count 0 2006.285.23:53:30.28#ibcon#read 4, iclass 34, count 0 2006.285.23:53:30.28#ibcon#about to read 5, iclass 34, count 0 2006.285.23:53:30.28#ibcon#read 5, iclass 34, count 0 2006.285.23:53:30.28#ibcon#about to read 6, iclass 34, count 0 2006.285.23:53:30.28#ibcon#read 6, iclass 34, count 0 2006.285.23:53:30.28#ibcon#end of sib2, iclass 34, count 0 2006.285.23:53:30.28#ibcon#*after write, iclass 34, count 0 2006.285.23:53:30.28#ibcon#*before return 0, iclass 34, count 0 2006.285.23:53:30.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:53:30.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.285.23:53:30.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.285.23:53:30.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.285.23:53:30.28$setupk4/ifdk4 2006.285.23:53:30.28$ifdk4/lo= 2006.285.23:53:30.28$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:53:30.28$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:53:30.28$ifdk4/patch= 2006.285.23:53:30.28$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:53:30.28$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:53:30.28$setupk4/!*+20s 2006.285.23:53:35.69#abcon#<5=/03 4.5 8.1 19.56 861016.5\r\n> 2006.285.23:53:35.71#abcon#{5=INTERFACE CLEAR} 2006.285.23:53:35.77#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:53:44.79$setupk4/"tpicd 2006.285.23:53:44.79$setupk4/echo=off 2006.285.23:53:44.79$setupk4/xlog=off 2006.285.23:53:44.79:!2006.285.23:56:21 2006.285.23:53:49.14#trakl#Source acquired 2006.285.23:53:49.14#flagr#flagr/antenna,acquired 2006.285.23:56:21.00:preob 2006.285.23:56:21.14/onsource/TRACKING 2006.285.23:56:21.14:!2006.285.23:56:31 2006.285.23:56:31.00:"tape 2006.285.23:56:31.00:"st=record 2006.285.23:56:31.00:data_valid=on 2006.285.23:56:31.00:midob 2006.285.23:56:31.14/onsource/TRACKING 2006.285.23:56:31.14/wx/19.57,1016.6,87 2006.285.23:56:31.22/cable/+6.5060E-03 2006.285.23:56:32.31/va/01,07,usb,yes,33,36 2006.285.23:56:32.31/va/02,06,usb,yes,34,34 2006.285.23:56:32.31/va/03,07,usb,yes,33,35 2006.285.23:56:32.31/va/04,06,usb,yes,35,36 2006.285.23:56:32.31/va/05,03,usb,yes,34,35 2006.285.23:56:32.31/va/06,04,usb,yes,31,30 2006.285.23:56:32.31/va/07,04,usb,yes,31,32 2006.285.23:56:32.31/va/08,03,usb,yes,32,39 2006.285.23:56:32.54/valo/01,524.99,yes,locked 2006.285.23:56:32.54/valo/02,534.99,yes,locked 2006.285.23:56:32.54/valo/03,564.99,yes,locked 2006.285.23:56:32.54/valo/04,624.99,yes,locked 2006.285.23:56:32.54/valo/05,734.99,yes,locked 2006.285.23:56:32.54/valo/06,814.99,yes,locked 2006.285.23:56:32.54/valo/07,864.99,yes,locked 2006.285.23:56:32.54/valo/08,884.99,yes,locked 2006.285.23:56:33.63/vb/01,04,usb,yes,31,29 2006.285.23:56:33.63/vb/02,05,usb,yes,29,29 2006.285.23:56:33.63/vb/03,04,usb,yes,30,33 2006.285.23:56:33.63/vb/04,05,usb,yes,31,30 2006.285.23:56:33.63/vb/05,04,usb,yes,27,29 2006.285.23:56:33.63/vb/06,03,usb,yes,38,34 2006.285.23:56:33.63/vb/07,04,usb,yes,31,31 2006.285.23:56:33.63/vb/08,04,usb,yes,28,32 2006.285.23:56:33.86/vblo/01,629.99,yes,locked 2006.285.23:56:33.86/vblo/02,634.99,yes,locked 2006.285.23:56:33.86/vblo/03,649.99,yes,locked 2006.285.23:56:33.86/vblo/04,679.99,yes,locked 2006.285.23:56:33.86/vblo/05,709.99,yes,locked 2006.285.23:56:33.86/vblo/06,719.99,yes,locked 2006.285.23:56:33.86/vblo/07,734.99,yes,locked 2006.285.23:56:33.86/vblo/08,744.99,yes,locked 2006.285.23:56:34.01/vabw/8 2006.285.23:56:34.16/vbbw/8 2006.285.23:56:34.25/xfe/off,on,12.0 2006.285.23:56:34.64/ifatt/23,28,28,28 2006.285.23:56:35.07/fmout-gps/S +2.81E-07 2006.285.23:56:35.09:!2006.285.23:57:31 2006.285.23:57:31.00:data_valid=off 2006.285.23:57:31.00:"et 2006.285.23:57:31.00:!+3s 2006.285.23:57:34.01:"tape 2006.285.23:57:34.01:postob 2006.285.23:57:34.14/cable/+6.5066E-03 2006.285.23:57:34.14/wx/19.59,1016.5,87 2006.285.23:57:35.07/fmout-gps/S +2.82E-07 2006.285.23:57:35.07:scan_name=286-0004,jd0610,80 2006.285.23:57:35.07:source=3c274,123049.42,122328.0,2000.0,cw 2006.285.23:57:35.14#flagr#flagr/antenna,new-source 2006.285.23:57:36.14:checkk5 2006.285.23:57:36.55/chk_autoobs//k5ts1/ autoobs is running! 2006.285.23:57:36.96/chk_autoobs//k5ts2/ autoobs is running! 2006.285.23:57:37.38/chk_autoobs//k5ts3/ autoobs is running! 2006.285.23:57:37.97/chk_autoobs//k5ts4/ autoobs is running! 2006.285.23:57:38.57/chk_obsdata//k5ts1/T2852356??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.23:57:38.92/chk_obsdata//k5ts2/T2852356??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.23:57:39.31/chk_obsdata//k5ts3/T2852356??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.23:57:39.75/chk_obsdata//k5ts4/T2852356??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.285.23:57:40.69/k5log//k5ts1_log_newline 2006.285.23:57:41.40/k5log//k5ts2_log_newline 2006.285.23:57:42.13/k5log//k5ts3_log_newline 2006.285.23:57:42.84/k5log//k5ts4_log_newline 2006.285.23:57:42.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.285.23:57:42.86:setupk4=1 2006.285.23:57:42.86$setupk4/echo=on 2006.285.23:57:42.87$setupk4/pcalon 2006.285.23:57:42.87$pcalon/"no phase cal control is implemented here 2006.285.23:57:42.87$setupk4/"tpicd=stop 2006.285.23:57:42.87$setupk4/"rec=synch_on 2006.285.23:57:42.87$setupk4/"rec_mode=128 2006.285.23:57:42.87$setupk4/!* 2006.285.23:57:42.87$setupk4/recpk4 2006.285.23:57:42.87$recpk4/recpatch= 2006.285.23:57:42.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.285.23:57:42.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.285.23:57:42.87$setupk4/vck44 2006.285.23:57:42.87$vck44/valo=1,524.99 2006.285.23:57:42.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.23:57:42.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.23:57:42.87#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:42.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:57:42.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:57:42.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:57:42.87#ibcon#enter wrdev, iclass 31, count 0 2006.285.23:57:42.87#ibcon#first serial, iclass 31, count 0 2006.285.23:57:42.87#ibcon#enter sib2, iclass 31, count 0 2006.285.23:57:42.87#ibcon#flushed, iclass 31, count 0 2006.285.23:57:42.87#ibcon#about to write, iclass 31, count 0 2006.285.23:57:42.87#ibcon#wrote, iclass 31, count 0 2006.285.23:57:42.87#ibcon#about to read 3, iclass 31, count 0 2006.285.23:57:42.89#ibcon#read 3, iclass 31, count 0 2006.285.23:57:42.89#ibcon#about to read 4, iclass 31, count 0 2006.285.23:57:42.89#ibcon#read 4, iclass 31, count 0 2006.285.23:57:42.89#ibcon#about to read 5, iclass 31, count 0 2006.285.23:57:42.89#ibcon#read 5, iclass 31, count 0 2006.285.23:57:42.89#ibcon#about to read 6, iclass 31, count 0 2006.285.23:57:42.89#ibcon#read 6, iclass 31, count 0 2006.285.23:57:42.89#ibcon#end of sib2, iclass 31, count 0 2006.285.23:57:42.89#ibcon#*mode == 0, iclass 31, count 0 2006.285.23:57:42.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.23:57:42.89#ibcon#[26=FRQ=01,524.99\r\n] 2006.285.23:57:42.89#ibcon#*before write, iclass 31, count 0 2006.285.23:57:42.89#ibcon#enter sib2, iclass 31, count 0 2006.285.23:57:42.89#ibcon#flushed, iclass 31, count 0 2006.285.23:57:42.89#ibcon#about to write, iclass 31, count 0 2006.285.23:57:42.89#ibcon#wrote, iclass 31, count 0 2006.285.23:57:42.89#ibcon#about to read 3, iclass 31, count 0 2006.285.23:57:42.94#ibcon#read 3, iclass 31, count 0 2006.285.23:57:42.94#ibcon#about to read 4, iclass 31, count 0 2006.285.23:57:42.94#ibcon#read 4, iclass 31, count 0 2006.285.23:57:42.94#ibcon#about to read 5, iclass 31, count 0 2006.285.23:57:42.94#ibcon#read 5, iclass 31, count 0 2006.285.23:57:42.94#ibcon#about to read 6, iclass 31, count 0 2006.285.23:57:42.94#ibcon#read 6, iclass 31, count 0 2006.285.23:57:42.94#ibcon#end of sib2, iclass 31, count 0 2006.285.23:57:42.94#ibcon#*after write, iclass 31, count 0 2006.285.23:57:42.94#ibcon#*before return 0, iclass 31, count 0 2006.285.23:57:42.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:57:42.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:57:42.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.23:57:42.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.23:57:42.94$vck44/va=1,7 2006.285.23:57:42.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.23:57:42.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.23:57:42.94#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:42.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:57:42.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:57:42.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:57:42.94#ibcon#enter wrdev, iclass 33, count 2 2006.285.23:57:42.94#ibcon#first serial, iclass 33, count 2 2006.285.23:57:42.94#ibcon#enter sib2, iclass 33, count 2 2006.285.23:57:42.94#ibcon#flushed, iclass 33, count 2 2006.285.23:57:42.94#ibcon#about to write, iclass 33, count 2 2006.285.23:57:42.94#ibcon#wrote, iclass 33, count 2 2006.285.23:57:42.94#ibcon#about to read 3, iclass 33, count 2 2006.285.23:57:42.96#ibcon#read 3, iclass 33, count 2 2006.285.23:57:42.96#ibcon#about to read 4, iclass 33, count 2 2006.285.23:57:42.96#ibcon#read 4, iclass 33, count 2 2006.285.23:57:42.96#ibcon#about to read 5, iclass 33, count 2 2006.285.23:57:42.96#ibcon#read 5, iclass 33, count 2 2006.285.23:57:42.96#ibcon#about to read 6, iclass 33, count 2 2006.285.23:57:42.96#ibcon#read 6, iclass 33, count 2 2006.285.23:57:42.96#ibcon#end of sib2, iclass 33, count 2 2006.285.23:57:42.96#ibcon#*mode == 0, iclass 33, count 2 2006.285.23:57:42.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.23:57:42.96#ibcon#[25=AT01-07\r\n] 2006.285.23:57:42.96#ibcon#*before write, iclass 33, count 2 2006.285.23:57:42.96#ibcon#enter sib2, iclass 33, count 2 2006.285.23:57:42.96#ibcon#flushed, iclass 33, count 2 2006.285.23:57:42.96#ibcon#about to write, iclass 33, count 2 2006.285.23:57:42.96#ibcon#wrote, iclass 33, count 2 2006.285.23:57:42.96#ibcon#about to read 3, iclass 33, count 2 2006.285.23:57:42.99#ibcon#read 3, iclass 33, count 2 2006.285.23:57:42.99#ibcon#about to read 4, iclass 33, count 2 2006.285.23:57:42.99#ibcon#read 4, iclass 33, count 2 2006.285.23:57:42.99#ibcon#about to read 5, iclass 33, count 2 2006.285.23:57:42.99#ibcon#read 5, iclass 33, count 2 2006.285.23:57:42.99#ibcon#about to read 6, iclass 33, count 2 2006.285.23:57:42.99#ibcon#read 6, iclass 33, count 2 2006.285.23:57:42.99#ibcon#end of sib2, iclass 33, count 2 2006.285.23:57:42.99#ibcon#*after write, iclass 33, count 2 2006.285.23:57:42.99#ibcon#*before return 0, iclass 33, count 2 2006.285.23:57:42.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:57:42.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:57:42.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.23:57:42.99#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:42.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:57:43.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:57:43.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:57:43.11#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:57:43.11#ibcon#first serial, iclass 33, count 0 2006.285.23:57:43.11#ibcon#enter sib2, iclass 33, count 0 2006.285.23:57:43.11#ibcon#flushed, iclass 33, count 0 2006.285.23:57:43.11#ibcon#about to write, iclass 33, count 0 2006.285.23:57:43.11#ibcon#wrote, iclass 33, count 0 2006.285.23:57:43.11#ibcon#about to read 3, iclass 33, count 0 2006.285.23:57:43.13#ibcon#read 3, iclass 33, count 0 2006.285.23:57:43.13#ibcon#about to read 4, iclass 33, count 0 2006.285.23:57:43.13#ibcon#read 4, iclass 33, count 0 2006.285.23:57:43.13#ibcon#about to read 5, iclass 33, count 0 2006.285.23:57:43.13#ibcon#read 5, iclass 33, count 0 2006.285.23:57:43.13#ibcon#about to read 6, iclass 33, count 0 2006.285.23:57:43.13#ibcon#read 6, iclass 33, count 0 2006.285.23:57:43.13#ibcon#end of sib2, iclass 33, count 0 2006.285.23:57:43.13#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:57:43.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:57:43.13#ibcon#[25=USB\r\n] 2006.285.23:57:43.13#ibcon#*before write, iclass 33, count 0 2006.285.23:57:43.13#ibcon#enter sib2, iclass 33, count 0 2006.285.23:57:43.13#ibcon#flushed, iclass 33, count 0 2006.285.23:57:43.13#ibcon#about to write, iclass 33, count 0 2006.285.23:57:43.13#ibcon#wrote, iclass 33, count 0 2006.285.23:57:43.13#ibcon#about to read 3, iclass 33, count 0 2006.285.23:57:43.16#ibcon#read 3, iclass 33, count 0 2006.285.23:57:43.16#ibcon#about to read 4, iclass 33, count 0 2006.285.23:57:43.16#ibcon#read 4, iclass 33, count 0 2006.285.23:57:43.16#ibcon#about to read 5, iclass 33, count 0 2006.285.23:57:43.16#ibcon#read 5, iclass 33, count 0 2006.285.23:57:43.16#ibcon#about to read 6, iclass 33, count 0 2006.285.23:57:43.16#ibcon#read 6, iclass 33, count 0 2006.285.23:57:43.16#ibcon#end of sib2, iclass 33, count 0 2006.285.23:57:43.16#ibcon#*after write, iclass 33, count 0 2006.285.23:57:43.16#ibcon#*before return 0, iclass 33, count 0 2006.285.23:57:43.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:57:43.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:57:43.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:57:43.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:57:43.16$vck44/valo=2,534.99 2006.285.23:57:43.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.23:57:43.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.23:57:43.16#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:43.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:57:43.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:57:43.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:57:43.16#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:57:43.16#ibcon#first serial, iclass 35, count 0 2006.285.23:57:43.16#ibcon#enter sib2, iclass 35, count 0 2006.285.23:57:43.16#ibcon#flushed, iclass 35, count 0 2006.285.23:57:43.16#ibcon#about to write, iclass 35, count 0 2006.285.23:57:43.16#ibcon#wrote, iclass 35, count 0 2006.285.23:57:43.16#ibcon#about to read 3, iclass 35, count 0 2006.285.23:57:43.18#ibcon#read 3, iclass 35, count 0 2006.285.23:57:43.18#ibcon#about to read 4, iclass 35, count 0 2006.285.23:57:43.18#ibcon#read 4, iclass 35, count 0 2006.285.23:57:43.18#ibcon#about to read 5, iclass 35, count 0 2006.285.23:57:43.18#ibcon#read 5, iclass 35, count 0 2006.285.23:57:43.18#ibcon#about to read 6, iclass 35, count 0 2006.285.23:57:43.18#ibcon#read 6, iclass 35, count 0 2006.285.23:57:43.18#ibcon#end of sib2, iclass 35, count 0 2006.285.23:57:43.18#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:57:43.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:57:43.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.285.23:57:43.18#ibcon#*before write, iclass 35, count 0 2006.285.23:57:43.18#ibcon#enter sib2, iclass 35, count 0 2006.285.23:57:43.18#ibcon#flushed, iclass 35, count 0 2006.285.23:57:43.18#ibcon#about to write, iclass 35, count 0 2006.285.23:57:43.18#ibcon#wrote, iclass 35, count 0 2006.285.23:57:43.18#ibcon#about to read 3, iclass 35, count 0 2006.285.23:57:43.22#ibcon#read 3, iclass 35, count 0 2006.285.23:57:43.22#ibcon#about to read 4, iclass 35, count 0 2006.285.23:57:43.22#ibcon#read 4, iclass 35, count 0 2006.285.23:57:43.22#ibcon#about to read 5, iclass 35, count 0 2006.285.23:57:43.22#ibcon#read 5, iclass 35, count 0 2006.285.23:57:43.22#ibcon#about to read 6, iclass 35, count 0 2006.285.23:57:43.22#ibcon#read 6, iclass 35, count 0 2006.285.23:57:43.22#ibcon#end of sib2, iclass 35, count 0 2006.285.23:57:43.22#ibcon#*after write, iclass 35, count 0 2006.285.23:57:43.22#ibcon#*before return 0, iclass 35, count 0 2006.285.23:57:43.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:57:43.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:57:43.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:57:43.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:57:43.22$vck44/va=2,6 2006.285.23:57:43.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.23:57:43.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.23:57:43.22#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:43.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:57:43.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:57:43.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:57:43.28#ibcon#enter wrdev, iclass 37, count 2 2006.285.23:57:43.28#ibcon#first serial, iclass 37, count 2 2006.285.23:57:43.28#ibcon#enter sib2, iclass 37, count 2 2006.285.23:57:43.28#ibcon#flushed, iclass 37, count 2 2006.285.23:57:43.28#ibcon#about to write, iclass 37, count 2 2006.285.23:57:43.28#ibcon#wrote, iclass 37, count 2 2006.285.23:57:43.28#ibcon#about to read 3, iclass 37, count 2 2006.285.23:57:43.30#ibcon#read 3, iclass 37, count 2 2006.285.23:57:43.30#ibcon#about to read 4, iclass 37, count 2 2006.285.23:57:43.30#ibcon#read 4, iclass 37, count 2 2006.285.23:57:43.30#ibcon#about to read 5, iclass 37, count 2 2006.285.23:57:43.30#ibcon#read 5, iclass 37, count 2 2006.285.23:57:43.30#ibcon#about to read 6, iclass 37, count 2 2006.285.23:57:43.30#ibcon#read 6, iclass 37, count 2 2006.285.23:57:43.30#ibcon#end of sib2, iclass 37, count 2 2006.285.23:57:43.30#ibcon#*mode == 0, iclass 37, count 2 2006.285.23:57:43.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.23:57:43.30#ibcon#[25=AT02-06\r\n] 2006.285.23:57:43.30#ibcon#*before write, iclass 37, count 2 2006.285.23:57:43.30#ibcon#enter sib2, iclass 37, count 2 2006.285.23:57:43.30#ibcon#flushed, iclass 37, count 2 2006.285.23:57:43.30#ibcon#about to write, iclass 37, count 2 2006.285.23:57:43.30#ibcon#wrote, iclass 37, count 2 2006.285.23:57:43.30#ibcon#about to read 3, iclass 37, count 2 2006.285.23:57:43.33#ibcon#read 3, iclass 37, count 2 2006.285.23:57:43.33#ibcon#about to read 4, iclass 37, count 2 2006.285.23:57:43.33#ibcon#read 4, iclass 37, count 2 2006.285.23:57:43.33#ibcon#about to read 5, iclass 37, count 2 2006.285.23:57:43.33#ibcon#read 5, iclass 37, count 2 2006.285.23:57:43.33#ibcon#about to read 6, iclass 37, count 2 2006.285.23:57:43.33#ibcon#read 6, iclass 37, count 2 2006.285.23:57:43.33#ibcon#end of sib2, iclass 37, count 2 2006.285.23:57:43.33#ibcon#*after write, iclass 37, count 2 2006.285.23:57:43.33#ibcon#*before return 0, iclass 37, count 2 2006.285.23:57:43.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:57:43.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:57:43.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.23:57:43.33#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:43.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:57:43.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:57:43.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:57:43.45#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:57:43.45#ibcon#first serial, iclass 37, count 0 2006.285.23:57:43.45#ibcon#enter sib2, iclass 37, count 0 2006.285.23:57:43.45#ibcon#flushed, iclass 37, count 0 2006.285.23:57:43.45#ibcon#about to write, iclass 37, count 0 2006.285.23:57:43.45#ibcon#wrote, iclass 37, count 0 2006.285.23:57:43.45#ibcon#about to read 3, iclass 37, count 0 2006.285.23:57:43.47#ibcon#read 3, iclass 37, count 0 2006.285.23:57:43.47#ibcon#about to read 4, iclass 37, count 0 2006.285.23:57:43.47#ibcon#read 4, iclass 37, count 0 2006.285.23:57:43.47#ibcon#about to read 5, iclass 37, count 0 2006.285.23:57:43.47#ibcon#read 5, iclass 37, count 0 2006.285.23:57:43.47#ibcon#about to read 6, iclass 37, count 0 2006.285.23:57:43.47#ibcon#read 6, iclass 37, count 0 2006.285.23:57:43.47#ibcon#end of sib2, iclass 37, count 0 2006.285.23:57:43.47#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:57:43.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:57:43.47#ibcon#[25=USB\r\n] 2006.285.23:57:43.47#ibcon#*before write, iclass 37, count 0 2006.285.23:57:43.47#ibcon#enter sib2, iclass 37, count 0 2006.285.23:57:43.47#ibcon#flushed, iclass 37, count 0 2006.285.23:57:43.47#ibcon#about to write, iclass 37, count 0 2006.285.23:57:43.47#ibcon#wrote, iclass 37, count 0 2006.285.23:57:43.47#ibcon#about to read 3, iclass 37, count 0 2006.285.23:57:43.50#ibcon#read 3, iclass 37, count 0 2006.285.23:57:43.50#ibcon#about to read 4, iclass 37, count 0 2006.285.23:57:43.50#ibcon#read 4, iclass 37, count 0 2006.285.23:57:43.50#ibcon#about to read 5, iclass 37, count 0 2006.285.23:57:43.50#ibcon#read 5, iclass 37, count 0 2006.285.23:57:43.50#ibcon#about to read 6, iclass 37, count 0 2006.285.23:57:43.50#ibcon#read 6, iclass 37, count 0 2006.285.23:57:43.50#ibcon#end of sib2, iclass 37, count 0 2006.285.23:57:43.50#ibcon#*after write, iclass 37, count 0 2006.285.23:57:43.50#ibcon#*before return 0, iclass 37, count 0 2006.285.23:57:43.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:57:43.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:57:43.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:57:43.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:57:43.50$vck44/valo=3,564.99 2006.285.23:57:43.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.23:57:43.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.23:57:43.50#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:43.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:57:43.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:57:43.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:57:43.50#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:57:43.50#ibcon#first serial, iclass 39, count 0 2006.285.23:57:43.50#ibcon#enter sib2, iclass 39, count 0 2006.285.23:57:43.50#ibcon#flushed, iclass 39, count 0 2006.285.23:57:43.50#ibcon#about to write, iclass 39, count 0 2006.285.23:57:43.50#ibcon#wrote, iclass 39, count 0 2006.285.23:57:43.50#ibcon#about to read 3, iclass 39, count 0 2006.285.23:57:43.52#ibcon#read 3, iclass 39, count 0 2006.285.23:57:43.52#ibcon#about to read 4, iclass 39, count 0 2006.285.23:57:43.52#ibcon#read 4, iclass 39, count 0 2006.285.23:57:43.52#ibcon#about to read 5, iclass 39, count 0 2006.285.23:57:43.52#ibcon#read 5, iclass 39, count 0 2006.285.23:57:43.52#ibcon#about to read 6, iclass 39, count 0 2006.285.23:57:43.52#ibcon#read 6, iclass 39, count 0 2006.285.23:57:43.52#ibcon#end of sib2, iclass 39, count 0 2006.285.23:57:43.52#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:57:43.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:57:43.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.285.23:57:43.52#ibcon#*before write, iclass 39, count 0 2006.285.23:57:43.52#ibcon#enter sib2, iclass 39, count 0 2006.285.23:57:43.52#ibcon#flushed, iclass 39, count 0 2006.285.23:57:43.52#ibcon#about to write, iclass 39, count 0 2006.285.23:57:43.52#ibcon#wrote, iclass 39, count 0 2006.285.23:57:43.52#ibcon#about to read 3, iclass 39, count 0 2006.285.23:57:43.56#ibcon#read 3, iclass 39, count 0 2006.285.23:57:43.56#ibcon#about to read 4, iclass 39, count 0 2006.285.23:57:43.56#ibcon#read 4, iclass 39, count 0 2006.285.23:57:43.56#ibcon#about to read 5, iclass 39, count 0 2006.285.23:57:43.56#ibcon#read 5, iclass 39, count 0 2006.285.23:57:43.56#ibcon#about to read 6, iclass 39, count 0 2006.285.23:57:43.56#ibcon#read 6, iclass 39, count 0 2006.285.23:57:43.56#ibcon#end of sib2, iclass 39, count 0 2006.285.23:57:43.56#ibcon#*after write, iclass 39, count 0 2006.285.23:57:43.56#ibcon#*before return 0, iclass 39, count 0 2006.285.23:57:43.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:57:43.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:57:43.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:57:43.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:57:43.56$vck44/va=3,7 2006.285.23:57:43.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.23:57:43.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.23:57:43.56#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:43.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:57:43.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:57:43.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:57:43.62#ibcon#enter wrdev, iclass 3, count 2 2006.285.23:57:43.62#ibcon#first serial, iclass 3, count 2 2006.285.23:57:43.62#ibcon#enter sib2, iclass 3, count 2 2006.285.23:57:43.62#ibcon#flushed, iclass 3, count 2 2006.285.23:57:43.62#ibcon#about to write, iclass 3, count 2 2006.285.23:57:43.62#ibcon#wrote, iclass 3, count 2 2006.285.23:57:43.62#ibcon#about to read 3, iclass 3, count 2 2006.285.23:57:43.64#ibcon#read 3, iclass 3, count 2 2006.285.23:57:43.64#ibcon#about to read 4, iclass 3, count 2 2006.285.23:57:43.64#ibcon#read 4, iclass 3, count 2 2006.285.23:57:43.64#ibcon#about to read 5, iclass 3, count 2 2006.285.23:57:43.64#ibcon#read 5, iclass 3, count 2 2006.285.23:57:43.64#ibcon#about to read 6, iclass 3, count 2 2006.285.23:57:43.64#ibcon#read 6, iclass 3, count 2 2006.285.23:57:43.64#ibcon#end of sib2, iclass 3, count 2 2006.285.23:57:43.64#ibcon#*mode == 0, iclass 3, count 2 2006.285.23:57:43.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.23:57:43.64#ibcon#[25=AT03-07\r\n] 2006.285.23:57:43.64#ibcon#*before write, iclass 3, count 2 2006.285.23:57:43.64#ibcon#enter sib2, iclass 3, count 2 2006.285.23:57:43.64#ibcon#flushed, iclass 3, count 2 2006.285.23:57:43.64#ibcon#about to write, iclass 3, count 2 2006.285.23:57:43.64#ibcon#wrote, iclass 3, count 2 2006.285.23:57:43.64#ibcon#about to read 3, iclass 3, count 2 2006.285.23:57:43.67#ibcon#read 3, iclass 3, count 2 2006.285.23:57:43.67#ibcon#about to read 4, iclass 3, count 2 2006.285.23:57:43.67#ibcon#read 4, iclass 3, count 2 2006.285.23:57:43.67#ibcon#about to read 5, iclass 3, count 2 2006.285.23:57:43.67#ibcon#read 5, iclass 3, count 2 2006.285.23:57:43.67#ibcon#about to read 6, iclass 3, count 2 2006.285.23:57:43.67#ibcon#read 6, iclass 3, count 2 2006.285.23:57:43.67#ibcon#end of sib2, iclass 3, count 2 2006.285.23:57:43.67#ibcon#*after write, iclass 3, count 2 2006.285.23:57:43.67#ibcon#*before return 0, iclass 3, count 2 2006.285.23:57:43.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:57:43.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:57:43.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.23:57:43.67#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:43.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:57:43.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:57:43.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:57:43.79#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:57:43.79#ibcon#first serial, iclass 3, count 0 2006.285.23:57:43.79#ibcon#enter sib2, iclass 3, count 0 2006.285.23:57:43.79#ibcon#flushed, iclass 3, count 0 2006.285.23:57:43.79#ibcon#about to write, iclass 3, count 0 2006.285.23:57:43.79#ibcon#wrote, iclass 3, count 0 2006.285.23:57:43.79#ibcon#about to read 3, iclass 3, count 0 2006.285.23:57:43.81#ibcon#read 3, iclass 3, count 0 2006.285.23:57:43.81#ibcon#about to read 4, iclass 3, count 0 2006.285.23:57:43.81#ibcon#read 4, iclass 3, count 0 2006.285.23:57:43.81#ibcon#about to read 5, iclass 3, count 0 2006.285.23:57:43.81#ibcon#read 5, iclass 3, count 0 2006.285.23:57:43.81#ibcon#about to read 6, iclass 3, count 0 2006.285.23:57:43.81#ibcon#read 6, iclass 3, count 0 2006.285.23:57:43.81#ibcon#end of sib2, iclass 3, count 0 2006.285.23:57:43.81#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:57:43.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:57:43.81#ibcon#[25=USB\r\n] 2006.285.23:57:43.81#ibcon#*before write, iclass 3, count 0 2006.285.23:57:43.81#ibcon#enter sib2, iclass 3, count 0 2006.285.23:57:43.81#ibcon#flushed, iclass 3, count 0 2006.285.23:57:43.81#ibcon#about to write, iclass 3, count 0 2006.285.23:57:43.81#ibcon#wrote, iclass 3, count 0 2006.285.23:57:43.81#ibcon#about to read 3, iclass 3, count 0 2006.285.23:57:43.84#ibcon#read 3, iclass 3, count 0 2006.285.23:57:43.84#ibcon#about to read 4, iclass 3, count 0 2006.285.23:57:43.84#ibcon#read 4, iclass 3, count 0 2006.285.23:57:43.84#ibcon#about to read 5, iclass 3, count 0 2006.285.23:57:43.84#ibcon#read 5, iclass 3, count 0 2006.285.23:57:43.84#ibcon#about to read 6, iclass 3, count 0 2006.285.23:57:43.84#ibcon#read 6, iclass 3, count 0 2006.285.23:57:43.84#ibcon#end of sib2, iclass 3, count 0 2006.285.23:57:43.84#ibcon#*after write, iclass 3, count 0 2006.285.23:57:43.84#ibcon#*before return 0, iclass 3, count 0 2006.285.23:57:43.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:57:43.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:57:43.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:57:43.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:57:43.84$vck44/valo=4,624.99 2006.285.23:57:43.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.23:57:43.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.23:57:43.84#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:43.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:57:43.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:57:43.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:57:43.84#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:57:43.84#ibcon#first serial, iclass 5, count 0 2006.285.23:57:43.84#ibcon#enter sib2, iclass 5, count 0 2006.285.23:57:43.84#ibcon#flushed, iclass 5, count 0 2006.285.23:57:43.84#ibcon#about to write, iclass 5, count 0 2006.285.23:57:43.84#ibcon#wrote, iclass 5, count 0 2006.285.23:57:43.84#ibcon#about to read 3, iclass 5, count 0 2006.285.23:57:43.86#ibcon#read 3, iclass 5, count 0 2006.285.23:57:43.86#ibcon#about to read 4, iclass 5, count 0 2006.285.23:57:43.86#ibcon#read 4, iclass 5, count 0 2006.285.23:57:43.86#ibcon#about to read 5, iclass 5, count 0 2006.285.23:57:43.86#ibcon#read 5, iclass 5, count 0 2006.285.23:57:43.86#ibcon#about to read 6, iclass 5, count 0 2006.285.23:57:43.86#ibcon#read 6, iclass 5, count 0 2006.285.23:57:43.86#ibcon#end of sib2, iclass 5, count 0 2006.285.23:57:43.86#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:57:43.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:57:43.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.285.23:57:43.86#ibcon#*before write, iclass 5, count 0 2006.285.23:57:43.86#ibcon#enter sib2, iclass 5, count 0 2006.285.23:57:43.86#ibcon#flushed, iclass 5, count 0 2006.285.23:57:43.86#ibcon#about to write, iclass 5, count 0 2006.285.23:57:43.86#ibcon#wrote, iclass 5, count 0 2006.285.23:57:43.86#ibcon#about to read 3, iclass 5, count 0 2006.285.23:57:43.90#ibcon#read 3, iclass 5, count 0 2006.285.23:57:43.90#ibcon#about to read 4, iclass 5, count 0 2006.285.23:57:43.90#ibcon#read 4, iclass 5, count 0 2006.285.23:57:43.90#ibcon#about to read 5, iclass 5, count 0 2006.285.23:57:43.90#ibcon#read 5, iclass 5, count 0 2006.285.23:57:43.90#ibcon#about to read 6, iclass 5, count 0 2006.285.23:57:43.90#ibcon#read 6, iclass 5, count 0 2006.285.23:57:43.90#ibcon#end of sib2, iclass 5, count 0 2006.285.23:57:43.90#ibcon#*after write, iclass 5, count 0 2006.285.23:57:43.90#ibcon#*before return 0, iclass 5, count 0 2006.285.23:57:43.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:57:43.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:57:43.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:57:43.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:57:43.90$vck44/va=4,6 2006.285.23:57:43.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.23:57:43.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.23:57:43.90#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:43.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:57:43.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:57:43.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:57:43.96#ibcon#enter wrdev, iclass 7, count 2 2006.285.23:57:43.96#ibcon#first serial, iclass 7, count 2 2006.285.23:57:43.96#ibcon#enter sib2, iclass 7, count 2 2006.285.23:57:43.96#ibcon#flushed, iclass 7, count 2 2006.285.23:57:43.96#ibcon#about to write, iclass 7, count 2 2006.285.23:57:43.96#ibcon#wrote, iclass 7, count 2 2006.285.23:57:43.96#ibcon#about to read 3, iclass 7, count 2 2006.285.23:57:43.98#ibcon#read 3, iclass 7, count 2 2006.285.23:57:43.98#ibcon#about to read 4, iclass 7, count 2 2006.285.23:57:43.98#ibcon#read 4, iclass 7, count 2 2006.285.23:57:43.98#ibcon#about to read 5, iclass 7, count 2 2006.285.23:57:43.98#ibcon#read 5, iclass 7, count 2 2006.285.23:57:43.98#ibcon#about to read 6, iclass 7, count 2 2006.285.23:57:43.98#ibcon#read 6, iclass 7, count 2 2006.285.23:57:43.98#ibcon#end of sib2, iclass 7, count 2 2006.285.23:57:43.98#ibcon#*mode == 0, iclass 7, count 2 2006.285.23:57:43.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.23:57:43.98#ibcon#[25=AT04-06\r\n] 2006.285.23:57:43.98#ibcon#*before write, iclass 7, count 2 2006.285.23:57:43.98#ibcon#enter sib2, iclass 7, count 2 2006.285.23:57:43.98#ibcon#flushed, iclass 7, count 2 2006.285.23:57:43.98#ibcon#about to write, iclass 7, count 2 2006.285.23:57:43.98#ibcon#wrote, iclass 7, count 2 2006.285.23:57:43.98#ibcon#about to read 3, iclass 7, count 2 2006.285.23:57:44.01#ibcon#read 3, iclass 7, count 2 2006.285.23:57:44.01#ibcon#about to read 4, iclass 7, count 2 2006.285.23:57:44.01#ibcon#read 4, iclass 7, count 2 2006.285.23:57:44.01#ibcon#about to read 5, iclass 7, count 2 2006.285.23:57:44.01#ibcon#read 5, iclass 7, count 2 2006.285.23:57:44.01#ibcon#about to read 6, iclass 7, count 2 2006.285.23:57:44.01#ibcon#read 6, iclass 7, count 2 2006.285.23:57:44.01#ibcon#end of sib2, iclass 7, count 2 2006.285.23:57:44.01#ibcon#*after write, iclass 7, count 2 2006.285.23:57:44.01#ibcon#*before return 0, iclass 7, count 2 2006.285.23:57:44.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:57:44.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:57:44.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.23:57:44.01#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:44.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:57:44.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:57:44.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:57:44.13#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:57:44.13#ibcon#first serial, iclass 7, count 0 2006.285.23:57:44.13#ibcon#enter sib2, iclass 7, count 0 2006.285.23:57:44.13#ibcon#flushed, iclass 7, count 0 2006.285.23:57:44.13#ibcon#about to write, iclass 7, count 0 2006.285.23:57:44.13#ibcon#wrote, iclass 7, count 0 2006.285.23:57:44.13#ibcon#about to read 3, iclass 7, count 0 2006.285.23:57:44.15#ibcon#read 3, iclass 7, count 0 2006.285.23:57:44.15#ibcon#about to read 4, iclass 7, count 0 2006.285.23:57:44.15#ibcon#read 4, iclass 7, count 0 2006.285.23:57:44.15#ibcon#about to read 5, iclass 7, count 0 2006.285.23:57:44.15#ibcon#read 5, iclass 7, count 0 2006.285.23:57:44.15#ibcon#about to read 6, iclass 7, count 0 2006.285.23:57:44.15#ibcon#read 6, iclass 7, count 0 2006.285.23:57:44.15#ibcon#end of sib2, iclass 7, count 0 2006.285.23:57:44.15#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:57:44.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:57:44.15#ibcon#[25=USB\r\n] 2006.285.23:57:44.15#ibcon#*before write, iclass 7, count 0 2006.285.23:57:44.15#ibcon#enter sib2, iclass 7, count 0 2006.285.23:57:44.15#ibcon#flushed, iclass 7, count 0 2006.285.23:57:44.15#ibcon#about to write, iclass 7, count 0 2006.285.23:57:44.15#ibcon#wrote, iclass 7, count 0 2006.285.23:57:44.15#ibcon#about to read 3, iclass 7, count 0 2006.285.23:57:44.18#ibcon#read 3, iclass 7, count 0 2006.285.23:57:44.18#ibcon#about to read 4, iclass 7, count 0 2006.285.23:57:44.18#ibcon#read 4, iclass 7, count 0 2006.285.23:57:44.18#ibcon#about to read 5, iclass 7, count 0 2006.285.23:57:44.18#ibcon#read 5, iclass 7, count 0 2006.285.23:57:44.18#ibcon#about to read 6, iclass 7, count 0 2006.285.23:57:44.18#ibcon#read 6, iclass 7, count 0 2006.285.23:57:44.18#ibcon#end of sib2, iclass 7, count 0 2006.285.23:57:44.18#ibcon#*after write, iclass 7, count 0 2006.285.23:57:44.18#ibcon#*before return 0, iclass 7, count 0 2006.285.23:57:44.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:57:44.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:57:44.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:57:44.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:57:44.18$vck44/valo=5,734.99 2006.285.23:57:44.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.23:57:44.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.23:57:44.18#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:44.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:57:44.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:57:44.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:57:44.18#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:57:44.18#ibcon#first serial, iclass 11, count 0 2006.285.23:57:44.18#ibcon#enter sib2, iclass 11, count 0 2006.285.23:57:44.18#ibcon#flushed, iclass 11, count 0 2006.285.23:57:44.18#ibcon#about to write, iclass 11, count 0 2006.285.23:57:44.18#ibcon#wrote, iclass 11, count 0 2006.285.23:57:44.18#ibcon#about to read 3, iclass 11, count 0 2006.285.23:57:44.20#ibcon#read 3, iclass 11, count 0 2006.285.23:57:44.20#ibcon#about to read 4, iclass 11, count 0 2006.285.23:57:44.20#ibcon#read 4, iclass 11, count 0 2006.285.23:57:44.20#ibcon#about to read 5, iclass 11, count 0 2006.285.23:57:44.20#ibcon#read 5, iclass 11, count 0 2006.285.23:57:44.20#ibcon#about to read 6, iclass 11, count 0 2006.285.23:57:44.20#ibcon#read 6, iclass 11, count 0 2006.285.23:57:44.20#ibcon#end of sib2, iclass 11, count 0 2006.285.23:57:44.20#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:57:44.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:57:44.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.285.23:57:44.20#ibcon#*before write, iclass 11, count 0 2006.285.23:57:44.20#ibcon#enter sib2, iclass 11, count 0 2006.285.23:57:44.20#ibcon#flushed, iclass 11, count 0 2006.285.23:57:44.20#ibcon#about to write, iclass 11, count 0 2006.285.23:57:44.20#ibcon#wrote, iclass 11, count 0 2006.285.23:57:44.20#ibcon#about to read 3, iclass 11, count 0 2006.285.23:57:44.24#ibcon#read 3, iclass 11, count 0 2006.285.23:57:44.24#ibcon#about to read 4, iclass 11, count 0 2006.285.23:57:44.24#ibcon#read 4, iclass 11, count 0 2006.285.23:57:44.24#ibcon#about to read 5, iclass 11, count 0 2006.285.23:57:44.24#ibcon#read 5, iclass 11, count 0 2006.285.23:57:44.24#ibcon#about to read 6, iclass 11, count 0 2006.285.23:57:44.24#ibcon#read 6, iclass 11, count 0 2006.285.23:57:44.24#ibcon#end of sib2, iclass 11, count 0 2006.285.23:57:44.24#ibcon#*after write, iclass 11, count 0 2006.285.23:57:44.24#ibcon#*before return 0, iclass 11, count 0 2006.285.23:57:44.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:57:44.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:57:44.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:57:44.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:57:44.24$vck44/va=5,3 2006.285.23:57:44.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.23:57:44.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.23:57:44.24#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:44.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:57:44.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:57:44.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:57:44.30#ibcon#enter wrdev, iclass 13, count 2 2006.285.23:57:44.30#ibcon#first serial, iclass 13, count 2 2006.285.23:57:44.30#ibcon#enter sib2, iclass 13, count 2 2006.285.23:57:44.30#ibcon#flushed, iclass 13, count 2 2006.285.23:57:44.30#ibcon#about to write, iclass 13, count 2 2006.285.23:57:44.30#ibcon#wrote, iclass 13, count 2 2006.285.23:57:44.30#ibcon#about to read 3, iclass 13, count 2 2006.285.23:57:44.32#ibcon#read 3, iclass 13, count 2 2006.285.23:57:44.32#ibcon#about to read 4, iclass 13, count 2 2006.285.23:57:44.32#ibcon#read 4, iclass 13, count 2 2006.285.23:57:44.32#ibcon#about to read 5, iclass 13, count 2 2006.285.23:57:44.32#ibcon#read 5, iclass 13, count 2 2006.285.23:57:44.32#ibcon#about to read 6, iclass 13, count 2 2006.285.23:57:44.32#ibcon#read 6, iclass 13, count 2 2006.285.23:57:44.32#ibcon#end of sib2, iclass 13, count 2 2006.285.23:57:44.32#ibcon#*mode == 0, iclass 13, count 2 2006.285.23:57:44.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.23:57:44.32#ibcon#[25=AT05-03\r\n] 2006.285.23:57:44.32#ibcon#*before write, iclass 13, count 2 2006.285.23:57:44.32#ibcon#enter sib2, iclass 13, count 2 2006.285.23:57:44.32#ibcon#flushed, iclass 13, count 2 2006.285.23:57:44.32#ibcon#about to write, iclass 13, count 2 2006.285.23:57:44.32#ibcon#wrote, iclass 13, count 2 2006.285.23:57:44.32#ibcon#about to read 3, iclass 13, count 2 2006.285.23:57:44.35#ibcon#read 3, iclass 13, count 2 2006.285.23:57:44.35#ibcon#about to read 4, iclass 13, count 2 2006.285.23:57:44.35#ibcon#read 4, iclass 13, count 2 2006.285.23:57:44.35#ibcon#about to read 5, iclass 13, count 2 2006.285.23:57:44.35#ibcon#read 5, iclass 13, count 2 2006.285.23:57:44.35#ibcon#about to read 6, iclass 13, count 2 2006.285.23:57:44.35#ibcon#read 6, iclass 13, count 2 2006.285.23:57:44.35#ibcon#end of sib2, iclass 13, count 2 2006.285.23:57:44.35#ibcon#*after write, iclass 13, count 2 2006.285.23:57:44.35#ibcon#*before return 0, iclass 13, count 2 2006.285.23:57:44.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:57:44.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:57:44.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.23:57:44.35#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:44.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:57:44.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:57:44.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:57:44.47#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:57:44.47#ibcon#first serial, iclass 13, count 0 2006.285.23:57:44.47#ibcon#enter sib2, iclass 13, count 0 2006.285.23:57:44.47#ibcon#flushed, iclass 13, count 0 2006.285.23:57:44.47#ibcon#about to write, iclass 13, count 0 2006.285.23:57:44.47#ibcon#wrote, iclass 13, count 0 2006.285.23:57:44.47#ibcon#about to read 3, iclass 13, count 0 2006.285.23:57:44.49#ibcon#read 3, iclass 13, count 0 2006.285.23:57:44.49#ibcon#about to read 4, iclass 13, count 0 2006.285.23:57:44.49#ibcon#read 4, iclass 13, count 0 2006.285.23:57:44.49#ibcon#about to read 5, iclass 13, count 0 2006.285.23:57:44.49#ibcon#read 5, iclass 13, count 0 2006.285.23:57:44.49#ibcon#about to read 6, iclass 13, count 0 2006.285.23:57:44.49#ibcon#read 6, iclass 13, count 0 2006.285.23:57:44.49#ibcon#end of sib2, iclass 13, count 0 2006.285.23:57:44.49#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:57:44.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:57:44.49#ibcon#[25=USB\r\n] 2006.285.23:57:44.49#ibcon#*before write, iclass 13, count 0 2006.285.23:57:44.49#ibcon#enter sib2, iclass 13, count 0 2006.285.23:57:44.49#ibcon#flushed, iclass 13, count 0 2006.285.23:57:44.49#ibcon#about to write, iclass 13, count 0 2006.285.23:57:44.49#ibcon#wrote, iclass 13, count 0 2006.285.23:57:44.49#ibcon#about to read 3, iclass 13, count 0 2006.285.23:57:44.52#ibcon#read 3, iclass 13, count 0 2006.285.23:57:44.52#ibcon#about to read 4, iclass 13, count 0 2006.285.23:57:44.52#ibcon#read 4, iclass 13, count 0 2006.285.23:57:44.52#ibcon#about to read 5, iclass 13, count 0 2006.285.23:57:44.52#ibcon#read 5, iclass 13, count 0 2006.285.23:57:44.52#ibcon#about to read 6, iclass 13, count 0 2006.285.23:57:44.52#ibcon#read 6, iclass 13, count 0 2006.285.23:57:44.52#ibcon#end of sib2, iclass 13, count 0 2006.285.23:57:44.52#ibcon#*after write, iclass 13, count 0 2006.285.23:57:44.52#ibcon#*before return 0, iclass 13, count 0 2006.285.23:57:44.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:57:44.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:57:44.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:57:44.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:57:44.52$vck44/valo=6,814.99 2006.285.23:57:44.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.23:57:44.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.23:57:44.52#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:44.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:57:44.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:57:44.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:57:44.52#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:57:44.52#ibcon#first serial, iclass 15, count 0 2006.285.23:57:44.52#ibcon#enter sib2, iclass 15, count 0 2006.285.23:57:44.52#ibcon#flushed, iclass 15, count 0 2006.285.23:57:44.52#ibcon#about to write, iclass 15, count 0 2006.285.23:57:44.52#ibcon#wrote, iclass 15, count 0 2006.285.23:57:44.52#ibcon#about to read 3, iclass 15, count 0 2006.285.23:57:44.54#ibcon#read 3, iclass 15, count 0 2006.285.23:57:44.54#ibcon#about to read 4, iclass 15, count 0 2006.285.23:57:44.54#ibcon#read 4, iclass 15, count 0 2006.285.23:57:44.54#ibcon#about to read 5, iclass 15, count 0 2006.285.23:57:44.54#ibcon#read 5, iclass 15, count 0 2006.285.23:57:44.54#ibcon#about to read 6, iclass 15, count 0 2006.285.23:57:44.54#ibcon#read 6, iclass 15, count 0 2006.285.23:57:44.54#ibcon#end of sib2, iclass 15, count 0 2006.285.23:57:44.54#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:57:44.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:57:44.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.285.23:57:44.54#ibcon#*before write, iclass 15, count 0 2006.285.23:57:44.54#ibcon#enter sib2, iclass 15, count 0 2006.285.23:57:44.54#ibcon#flushed, iclass 15, count 0 2006.285.23:57:44.54#ibcon#about to write, iclass 15, count 0 2006.285.23:57:44.54#ibcon#wrote, iclass 15, count 0 2006.285.23:57:44.54#ibcon#about to read 3, iclass 15, count 0 2006.285.23:57:44.58#ibcon#read 3, iclass 15, count 0 2006.285.23:57:44.58#ibcon#about to read 4, iclass 15, count 0 2006.285.23:57:44.58#ibcon#read 4, iclass 15, count 0 2006.285.23:57:44.58#ibcon#about to read 5, iclass 15, count 0 2006.285.23:57:44.58#ibcon#read 5, iclass 15, count 0 2006.285.23:57:44.58#ibcon#about to read 6, iclass 15, count 0 2006.285.23:57:44.58#ibcon#read 6, iclass 15, count 0 2006.285.23:57:44.58#ibcon#end of sib2, iclass 15, count 0 2006.285.23:57:44.58#ibcon#*after write, iclass 15, count 0 2006.285.23:57:44.58#ibcon#*before return 0, iclass 15, count 0 2006.285.23:57:44.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:57:44.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:57:44.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:57:44.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:57:44.58$vck44/va=6,4 2006.285.23:57:44.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.23:57:44.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.23:57:44.58#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:44.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:57:44.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:57:44.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:57:44.64#ibcon#enter wrdev, iclass 17, count 2 2006.285.23:57:44.64#ibcon#first serial, iclass 17, count 2 2006.285.23:57:44.64#ibcon#enter sib2, iclass 17, count 2 2006.285.23:57:44.64#ibcon#flushed, iclass 17, count 2 2006.285.23:57:44.64#ibcon#about to write, iclass 17, count 2 2006.285.23:57:44.64#ibcon#wrote, iclass 17, count 2 2006.285.23:57:44.64#ibcon#about to read 3, iclass 17, count 2 2006.285.23:57:44.66#ibcon#read 3, iclass 17, count 2 2006.285.23:57:44.66#ibcon#about to read 4, iclass 17, count 2 2006.285.23:57:44.66#ibcon#read 4, iclass 17, count 2 2006.285.23:57:44.66#ibcon#about to read 5, iclass 17, count 2 2006.285.23:57:44.66#ibcon#read 5, iclass 17, count 2 2006.285.23:57:44.66#ibcon#about to read 6, iclass 17, count 2 2006.285.23:57:44.66#ibcon#read 6, iclass 17, count 2 2006.285.23:57:44.66#ibcon#end of sib2, iclass 17, count 2 2006.285.23:57:44.66#ibcon#*mode == 0, iclass 17, count 2 2006.285.23:57:44.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.23:57:44.66#ibcon#[25=AT06-04\r\n] 2006.285.23:57:44.66#ibcon#*before write, iclass 17, count 2 2006.285.23:57:44.66#ibcon#enter sib2, iclass 17, count 2 2006.285.23:57:44.66#ibcon#flushed, iclass 17, count 2 2006.285.23:57:44.66#ibcon#about to write, iclass 17, count 2 2006.285.23:57:44.66#ibcon#wrote, iclass 17, count 2 2006.285.23:57:44.66#ibcon#about to read 3, iclass 17, count 2 2006.285.23:57:44.69#ibcon#read 3, iclass 17, count 2 2006.285.23:57:44.69#ibcon#about to read 4, iclass 17, count 2 2006.285.23:57:44.69#ibcon#read 4, iclass 17, count 2 2006.285.23:57:44.69#ibcon#about to read 5, iclass 17, count 2 2006.285.23:57:44.69#ibcon#read 5, iclass 17, count 2 2006.285.23:57:44.69#ibcon#about to read 6, iclass 17, count 2 2006.285.23:57:44.69#ibcon#read 6, iclass 17, count 2 2006.285.23:57:44.69#ibcon#end of sib2, iclass 17, count 2 2006.285.23:57:44.69#ibcon#*after write, iclass 17, count 2 2006.285.23:57:44.69#ibcon#*before return 0, iclass 17, count 2 2006.285.23:57:44.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:57:44.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:57:44.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.23:57:44.69#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:44.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:57:44.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:57:44.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:57:44.81#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:57:44.81#ibcon#first serial, iclass 17, count 0 2006.285.23:57:44.81#ibcon#enter sib2, iclass 17, count 0 2006.285.23:57:44.81#ibcon#flushed, iclass 17, count 0 2006.285.23:57:44.81#ibcon#about to write, iclass 17, count 0 2006.285.23:57:44.81#ibcon#wrote, iclass 17, count 0 2006.285.23:57:44.81#ibcon#about to read 3, iclass 17, count 0 2006.285.23:57:44.83#ibcon#read 3, iclass 17, count 0 2006.285.23:57:44.83#ibcon#about to read 4, iclass 17, count 0 2006.285.23:57:44.83#ibcon#read 4, iclass 17, count 0 2006.285.23:57:44.83#ibcon#about to read 5, iclass 17, count 0 2006.285.23:57:44.83#ibcon#read 5, iclass 17, count 0 2006.285.23:57:44.83#ibcon#about to read 6, iclass 17, count 0 2006.285.23:57:44.83#ibcon#read 6, iclass 17, count 0 2006.285.23:57:44.83#ibcon#end of sib2, iclass 17, count 0 2006.285.23:57:44.83#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:57:44.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:57:44.83#ibcon#[25=USB\r\n] 2006.285.23:57:44.83#ibcon#*before write, iclass 17, count 0 2006.285.23:57:44.83#ibcon#enter sib2, iclass 17, count 0 2006.285.23:57:44.83#ibcon#flushed, iclass 17, count 0 2006.285.23:57:44.83#ibcon#about to write, iclass 17, count 0 2006.285.23:57:44.83#ibcon#wrote, iclass 17, count 0 2006.285.23:57:44.83#ibcon#about to read 3, iclass 17, count 0 2006.285.23:57:44.86#ibcon#read 3, iclass 17, count 0 2006.285.23:57:44.86#ibcon#about to read 4, iclass 17, count 0 2006.285.23:57:44.86#ibcon#read 4, iclass 17, count 0 2006.285.23:57:44.86#ibcon#about to read 5, iclass 17, count 0 2006.285.23:57:44.86#ibcon#read 5, iclass 17, count 0 2006.285.23:57:44.86#ibcon#about to read 6, iclass 17, count 0 2006.285.23:57:44.86#ibcon#read 6, iclass 17, count 0 2006.285.23:57:44.86#ibcon#end of sib2, iclass 17, count 0 2006.285.23:57:44.86#ibcon#*after write, iclass 17, count 0 2006.285.23:57:44.86#ibcon#*before return 0, iclass 17, count 0 2006.285.23:57:44.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:57:44.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:57:44.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:57:44.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:57:44.86$vck44/valo=7,864.99 2006.285.23:57:44.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.23:57:44.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.23:57:44.86#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:44.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:57:44.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:57:44.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:57:44.86#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:57:44.86#ibcon#first serial, iclass 19, count 0 2006.285.23:57:44.86#ibcon#enter sib2, iclass 19, count 0 2006.285.23:57:44.86#ibcon#flushed, iclass 19, count 0 2006.285.23:57:44.86#ibcon#about to write, iclass 19, count 0 2006.285.23:57:44.86#ibcon#wrote, iclass 19, count 0 2006.285.23:57:44.86#ibcon#about to read 3, iclass 19, count 0 2006.285.23:57:44.88#ibcon#read 3, iclass 19, count 0 2006.285.23:57:44.88#ibcon#about to read 4, iclass 19, count 0 2006.285.23:57:44.88#ibcon#read 4, iclass 19, count 0 2006.285.23:57:44.88#ibcon#about to read 5, iclass 19, count 0 2006.285.23:57:44.88#ibcon#read 5, iclass 19, count 0 2006.285.23:57:44.88#ibcon#about to read 6, iclass 19, count 0 2006.285.23:57:44.88#ibcon#read 6, iclass 19, count 0 2006.285.23:57:44.88#ibcon#end of sib2, iclass 19, count 0 2006.285.23:57:44.88#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:57:44.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:57:44.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.285.23:57:44.88#ibcon#*before write, iclass 19, count 0 2006.285.23:57:44.88#ibcon#enter sib2, iclass 19, count 0 2006.285.23:57:44.88#ibcon#flushed, iclass 19, count 0 2006.285.23:57:44.88#ibcon#about to write, iclass 19, count 0 2006.285.23:57:44.88#ibcon#wrote, iclass 19, count 0 2006.285.23:57:44.88#ibcon#about to read 3, iclass 19, count 0 2006.285.23:57:44.92#ibcon#read 3, iclass 19, count 0 2006.285.23:57:44.92#ibcon#about to read 4, iclass 19, count 0 2006.285.23:57:44.92#ibcon#read 4, iclass 19, count 0 2006.285.23:57:44.92#ibcon#about to read 5, iclass 19, count 0 2006.285.23:57:44.92#ibcon#read 5, iclass 19, count 0 2006.285.23:57:44.92#ibcon#about to read 6, iclass 19, count 0 2006.285.23:57:44.92#ibcon#read 6, iclass 19, count 0 2006.285.23:57:44.92#ibcon#end of sib2, iclass 19, count 0 2006.285.23:57:44.92#ibcon#*after write, iclass 19, count 0 2006.285.23:57:44.92#ibcon#*before return 0, iclass 19, count 0 2006.285.23:57:44.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:57:44.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:57:44.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:57:44.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:57:44.92$vck44/va=7,4 2006.285.23:57:44.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.23:57:44.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.23:57:44.92#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:44.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:57:44.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:57:44.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:57:44.98#ibcon#enter wrdev, iclass 21, count 2 2006.285.23:57:44.98#ibcon#first serial, iclass 21, count 2 2006.285.23:57:44.98#ibcon#enter sib2, iclass 21, count 2 2006.285.23:57:44.98#ibcon#flushed, iclass 21, count 2 2006.285.23:57:44.98#ibcon#about to write, iclass 21, count 2 2006.285.23:57:44.98#ibcon#wrote, iclass 21, count 2 2006.285.23:57:44.98#ibcon#about to read 3, iclass 21, count 2 2006.285.23:57:45.00#ibcon#read 3, iclass 21, count 2 2006.285.23:57:45.00#ibcon#about to read 4, iclass 21, count 2 2006.285.23:57:45.00#ibcon#read 4, iclass 21, count 2 2006.285.23:57:45.00#ibcon#about to read 5, iclass 21, count 2 2006.285.23:57:45.00#ibcon#read 5, iclass 21, count 2 2006.285.23:57:45.00#ibcon#about to read 6, iclass 21, count 2 2006.285.23:57:45.00#ibcon#read 6, iclass 21, count 2 2006.285.23:57:45.00#ibcon#end of sib2, iclass 21, count 2 2006.285.23:57:45.00#ibcon#*mode == 0, iclass 21, count 2 2006.285.23:57:45.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.23:57:45.00#ibcon#[25=AT07-04\r\n] 2006.285.23:57:45.00#ibcon#*before write, iclass 21, count 2 2006.285.23:57:45.00#ibcon#enter sib2, iclass 21, count 2 2006.285.23:57:45.00#ibcon#flushed, iclass 21, count 2 2006.285.23:57:45.00#ibcon#about to write, iclass 21, count 2 2006.285.23:57:45.00#ibcon#wrote, iclass 21, count 2 2006.285.23:57:45.00#ibcon#about to read 3, iclass 21, count 2 2006.285.23:57:45.03#ibcon#read 3, iclass 21, count 2 2006.285.23:57:45.03#ibcon#about to read 4, iclass 21, count 2 2006.285.23:57:45.03#ibcon#read 4, iclass 21, count 2 2006.285.23:57:45.03#ibcon#about to read 5, iclass 21, count 2 2006.285.23:57:45.03#ibcon#read 5, iclass 21, count 2 2006.285.23:57:45.03#ibcon#about to read 6, iclass 21, count 2 2006.285.23:57:45.03#ibcon#read 6, iclass 21, count 2 2006.285.23:57:45.03#ibcon#end of sib2, iclass 21, count 2 2006.285.23:57:45.03#ibcon#*after write, iclass 21, count 2 2006.285.23:57:45.03#ibcon#*before return 0, iclass 21, count 2 2006.285.23:57:45.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:57:45.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:57:45.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.23:57:45.03#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:45.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:57:45.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:57:45.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:57:45.15#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:57:45.15#ibcon#first serial, iclass 21, count 0 2006.285.23:57:45.15#ibcon#enter sib2, iclass 21, count 0 2006.285.23:57:45.15#ibcon#flushed, iclass 21, count 0 2006.285.23:57:45.15#ibcon#about to write, iclass 21, count 0 2006.285.23:57:45.15#ibcon#wrote, iclass 21, count 0 2006.285.23:57:45.15#ibcon#about to read 3, iclass 21, count 0 2006.285.23:57:45.17#ibcon#read 3, iclass 21, count 0 2006.285.23:57:45.17#ibcon#about to read 4, iclass 21, count 0 2006.285.23:57:45.17#ibcon#read 4, iclass 21, count 0 2006.285.23:57:45.17#ibcon#about to read 5, iclass 21, count 0 2006.285.23:57:45.17#ibcon#read 5, iclass 21, count 0 2006.285.23:57:45.17#ibcon#about to read 6, iclass 21, count 0 2006.285.23:57:45.17#ibcon#read 6, iclass 21, count 0 2006.285.23:57:45.17#ibcon#end of sib2, iclass 21, count 0 2006.285.23:57:45.17#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:57:45.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:57:45.17#ibcon#[25=USB\r\n] 2006.285.23:57:45.17#ibcon#*before write, iclass 21, count 0 2006.285.23:57:45.17#ibcon#enter sib2, iclass 21, count 0 2006.285.23:57:45.17#ibcon#flushed, iclass 21, count 0 2006.285.23:57:45.17#ibcon#about to write, iclass 21, count 0 2006.285.23:57:45.17#ibcon#wrote, iclass 21, count 0 2006.285.23:57:45.17#ibcon#about to read 3, iclass 21, count 0 2006.285.23:57:45.20#ibcon#read 3, iclass 21, count 0 2006.285.23:57:45.20#ibcon#about to read 4, iclass 21, count 0 2006.285.23:57:45.20#ibcon#read 4, iclass 21, count 0 2006.285.23:57:45.20#ibcon#about to read 5, iclass 21, count 0 2006.285.23:57:45.20#ibcon#read 5, iclass 21, count 0 2006.285.23:57:45.20#ibcon#about to read 6, iclass 21, count 0 2006.285.23:57:45.20#ibcon#read 6, iclass 21, count 0 2006.285.23:57:45.20#ibcon#end of sib2, iclass 21, count 0 2006.285.23:57:45.20#ibcon#*after write, iclass 21, count 0 2006.285.23:57:45.20#ibcon#*before return 0, iclass 21, count 0 2006.285.23:57:45.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:57:45.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:57:45.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:57:45.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:57:45.20$vck44/valo=8,884.99 2006.285.23:57:45.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.23:57:45.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.23:57:45.20#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:45.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:57:45.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:57:45.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:57:45.20#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:57:45.20#ibcon#first serial, iclass 23, count 0 2006.285.23:57:45.20#ibcon#enter sib2, iclass 23, count 0 2006.285.23:57:45.20#ibcon#flushed, iclass 23, count 0 2006.285.23:57:45.20#ibcon#about to write, iclass 23, count 0 2006.285.23:57:45.20#ibcon#wrote, iclass 23, count 0 2006.285.23:57:45.20#ibcon#about to read 3, iclass 23, count 0 2006.285.23:57:45.22#ibcon#read 3, iclass 23, count 0 2006.285.23:57:45.22#ibcon#about to read 4, iclass 23, count 0 2006.285.23:57:45.22#ibcon#read 4, iclass 23, count 0 2006.285.23:57:45.22#ibcon#about to read 5, iclass 23, count 0 2006.285.23:57:45.22#ibcon#read 5, iclass 23, count 0 2006.285.23:57:45.22#ibcon#about to read 6, iclass 23, count 0 2006.285.23:57:45.22#ibcon#read 6, iclass 23, count 0 2006.285.23:57:45.22#ibcon#end of sib2, iclass 23, count 0 2006.285.23:57:45.22#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:57:45.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:57:45.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.285.23:57:45.22#ibcon#*before write, iclass 23, count 0 2006.285.23:57:45.22#ibcon#enter sib2, iclass 23, count 0 2006.285.23:57:45.22#ibcon#flushed, iclass 23, count 0 2006.285.23:57:45.22#ibcon#about to write, iclass 23, count 0 2006.285.23:57:45.22#ibcon#wrote, iclass 23, count 0 2006.285.23:57:45.22#ibcon#about to read 3, iclass 23, count 0 2006.285.23:57:45.26#ibcon#read 3, iclass 23, count 0 2006.285.23:57:45.26#ibcon#about to read 4, iclass 23, count 0 2006.285.23:57:45.26#ibcon#read 4, iclass 23, count 0 2006.285.23:57:45.26#ibcon#about to read 5, iclass 23, count 0 2006.285.23:57:45.26#ibcon#read 5, iclass 23, count 0 2006.285.23:57:45.26#ibcon#about to read 6, iclass 23, count 0 2006.285.23:57:45.26#ibcon#read 6, iclass 23, count 0 2006.285.23:57:45.26#ibcon#end of sib2, iclass 23, count 0 2006.285.23:57:45.26#ibcon#*after write, iclass 23, count 0 2006.285.23:57:45.26#ibcon#*before return 0, iclass 23, count 0 2006.285.23:57:45.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:57:45.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:57:45.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:57:45.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:57:45.26$vck44/va=8,3 2006.285.23:57:45.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.285.23:57:45.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.285.23:57:45.26#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:45.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:57:45.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:57:45.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:57:45.32#ibcon#enter wrdev, iclass 25, count 2 2006.285.23:57:45.32#ibcon#first serial, iclass 25, count 2 2006.285.23:57:45.32#ibcon#enter sib2, iclass 25, count 2 2006.285.23:57:45.32#ibcon#flushed, iclass 25, count 2 2006.285.23:57:45.32#ibcon#about to write, iclass 25, count 2 2006.285.23:57:45.32#ibcon#wrote, iclass 25, count 2 2006.285.23:57:45.32#ibcon#about to read 3, iclass 25, count 2 2006.285.23:57:45.34#ibcon#read 3, iclass 25, count 2 2006.285.23:57:45.34#ibcon#about to read 4, iclass 25, count 2 2006.285.23:57:45.34#ibcon#read 4, iclass 25, count 2 2006.285.23:57:45.34#ibcon#about to read 5, iclass 25, count 2 2006.285.23:57:45.34#ibcon#read 5, iclass 25, count 2 2006.285.23:57:45.34#ibcon#about to read 6, iclass 25, count 2 2006.285.23:57:45.34#ibcon#read 6, iclass 25, count 2 2006.285.23:57:45.34#ibcon#end of sib2, iclass 25, count 2 2006.285.23:57:45.34#ibcon#*mode == 0, iclass 25, count 2 2006.285.23:57:45.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.285.23:57:45.34#ibcon#[25=AT08-03\r\n] 2006.285.23:57:45.34#ibcon#*before write, iclass 25, count 2 2006.285.23:57:45.34#ibcon#enter sib2, iclass 25, count 2 2006.285.23:57:45.34#ibcon#flushed, iclass 25, count 2 2006.285.23:57:45.34#ibcon#about to write, iclass 25, count 2 2006.285.23:57:45.34#ibcon#wrote, iclass 25, count 2 2006.285.23:57:45.34#ibcon#about to read 3, iclass 25, count 2 2006.285.23:57:45.37#ibcon#read 3, iclass 25, count 2 2006.285.23:57:45.37#ibcon#about to read 4, iclass 25, count 2 2006.285.23:57:45.37#ibcon#read 4, iclass 25, count 2 2006.285.23:57:45.37#ibcon#about to read 5, iclass 25, count 2 2006.285.23:57:45.37#ibcon#read 5, iclass 25, count 2 2006.285.23:57:45.37#ibcon#about to read 6, iclass 25, count 2 2006.285.23:57:45.37#ibcon#read 6, iclass 25, count 2 2006.285.23:57:45.37#ibcon#end of sib2, iclass 25, count 2 2006.285.23:57:45.37#ibcon#*after write, iclass 25, count 2 2006.285.23:57:45.37#ibcon#*before return 0, iclass 25, count 2 2006.285.23:57:45.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:57:45.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.285.23:57:45.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.285.23:57:45.37#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:45.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:57:45.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:57:45.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:57:45.49#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:57:45.49#ibcon#first serial, iclass 25, count 0 2006.285.23:57:45.49#ibcon#enter sib2, iclass 25, count 0 2006.285.23:57:45.49#ibcon#flushed, iclass 25, count 0 2006.285.23:57:45.49#ibcon#about to write, iclass 25, count 0 2006.285.23:57:45.49#ibcon#wrote, iclass 25, count 0 2006.285.23:57:45.49#ibcon#about to read 3, iclass 25, count 0 2006.285.23:57:45.51#ibcon#read 3, iclass 25, count 0 2006.285.23:57:45.51#ibcon#about to read 4, iclass 25, count 0 2006.285.23:57:45.51#ibcon#read 4, iclass 25, count 0 2006.285.23:57:45.51#ibcon#about to read 5, iclass 25, count 0 2006.285.23:57:45.51#ibcon#read 5, iclass 25, count 0 2006.285.23:57:45.51#ibcon#about to read 6, iclass 25, count 0 2006.285.23:57:45.51#ibcon#read 6, iclass 25, count 0 2006.285.23:57:45.51#ibcon#end of sib2, iclass 25, count 0 2006.285.23:57:45.51#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:57:45.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:57:45.51#ibcon#[25=USB\r\n] 2006.285.23:57:45.51#ibcon#*before write, iclass 25, count 0 2006.285.23:57:45.51#ibcon#enter sib2, iclass 25, count 0 2006.285.23:57:45.51#ibcon#flushed, iclass 25, count 0 2006.285.23:57:45.51#ibcon#about to write, iclass 25, count 0 2006.285.23:57:45.51#ibcon#wrote, iclass 25, count 0 2006.285.23:57:45.51#ibcon#about to read 3, iclass 25, count 0 2006.285.23:57:45.54#ibcon#read 3, iclass 25, count 0 2006.285.23:57:45.54#ibcon#about to read 4, iclass 25, count 0 2006.285.23:57:45.54#ibcon#read 4, iclass 25, count 0 2006.285.23:57:45.54#ibcon#about to read 5, iclass 25, count 0 2006.285.23:57:45.54#ibcon#read 5, iclass 25, count 0 2006.285.23:57:45.54#ibcon#about to read 6, iclass 25, count 0 2006.285.23:57:45.54#ibcon#read 6, iclass 25, count 0 2006.285.23:57:45.54#ibcon#end of sib2, iclass 25, count 0 2006.285.23:57:45.54#ibcon#*after write, iclass 25, count 0 2006.285.23:57:45.54#ibcon#*before return 0, iclass 25, count 0 2006.285.23:57:45.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:57:45.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.285.23:57:45.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:57:45.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:57:45.54$vck44/vblo=1,629.99 2006.285.23:57:45.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.285.23:57:45.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.285.23:57:45.54#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:45.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:57:45.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:57:45.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:57:45.54#ibcon#enter wrdev, iclass 27, count 0 2006.285.23:57:45.54#ibcon#first serial, iclass 27, count 0 2006.285.23:57:45.54#ibcon#enter sib2, iclass 27, count 0 2006.285.23:57:45.54#ibcon#flushed, iclass 27, count 0 2006.285.23:57:45.54#ibcon#about to write, iclass 27, count 0 2006.285.23:57:45.54#ibcon#wrote, iclass 27, count 0 2006.285.23:57:45.54#ibcon#about to read 3, iclass 27, count 0 2006.285.23:57:45.56#ibcon#read 3, iclass 27, count 0 2006.285.23:57:45.56#ibcon#about to read 4, iclass 27, count 0 2006.285.23:57:45.56#ibcon#read 4, iclass 27, count 0 2006.285.23:57:45.56#ibcon#about to read 5, iclass 27, count 0 2006.285.23:57:45.56#ibcon#read 5, iclass 27, count 0 2006.285.23:57:45.56#ibcon#about to read 6, iclass 27, count 0 2006.285.23:57:45.56#ibcon#read 6, iclass 27, count 0 2006.285.23:57:45.56#ibcon#end of sib2, iclass 27, count 0 2006.285.23:57:45.56#ibcon#*mode == 0, iclass 27, count 0 2006.285.23:57:45.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.285.23:57:45.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.285.23:57:45.56#ibcon#*before write, iclass 27, count 0 2006.285.23:57:45.56#ibcon#enter sib2, iclass 27, count 0 2006.285.23:57:45.56#ibcon#flushed, iclass 27, count 0 2006.285.23:57:45.56#ibcon#about to write, iclass 27, count 0 2006.285.23:57:45.56#ibcon#wrote, iclass 27, count 0 2006.285.23:57:45.56#ibcon#about to read 3, iclass 27, count 0 2006.285.23:57:45.60#ibcon#read 3, iclass 27, count 0 2006.285.23:57:45.60#ibcon#about to read 4, iclass 27, count 0 2006.285.23:57:45.60#ibcon#read 4, iclass 27, count 0 2006.285.23:57:45.60#ibcon#about to read 5, iclass 27, count 0 2006.285.23:57:45.60#ibcon#read 5, iclass 27, count 0 2006.285.23:57:45.60#ibcon#about to read 6, iclass 27, count 0 2006.285.23:57:45.60#ibcon#read 6, iclass 27, count 0 2006.285.23:57:45.60#ibcon#end of sib2, iclass 27, count 0 2006.285.23:57:45.60#ibcon#*after write, iclass 27, count 0 2006.285.23:57:45.60#ibcon#*before return 0, iclass 27, count 0 2006.285.23:57:45.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:57:45.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.285.23:57:45.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.285.23:57:45.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.285.23:57:45.60$vck44/vb=1,4 2006.285.23:57:45.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.285.23:57:45.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.285.23:57:45.60#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:45.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:57:45.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:57:45.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:57:45.60#ibcon#enter wrdev, iclass 29, count 2 2006.285.23:57:45.60#ibcon#first serial, iclass 29, count 2 2006.285.23:57:45.60#ibcon#enter sib2, iclass 29, count 2 2006.285.23:57:45.60#ibcon#flushed, iclass 29, count 2 2006.285.23:57:45.60#ibcon#about to write, iclass 29, count 2 2006.285.23:57:45.60#ibcon#wrote, iclass 29, count 2 2006.285.23:57:45.60#ibcon#about to read 3, iclass 29, count 2 2006.285.23:57:45.62#ibcon#read 3, iclass 29, count 2 2006.285.23:57:45.62#ibcon#about to read 4, iclass 29, count 2 2006.285.23:57:45.62#ibcon#read 4, iclass 29, count 2 2006.285.23:57:45.62#ibcon#about to read 5, iclass 29, count 2 2006.285.23:57:45.62#ibcon#read 5, iclass 29, count 2 2006.285.23:57:45.62#ibcon#about to read 6, iclass 29, count 2 2006.285.23:57:45.62#ibcon#read 6, iclass 29, count 2 2006.285.23:57:45.62#ibcon#end of sib2, iclass 29, count 2 2006.285.23:57:45.62#ibcon#*mode == 0, iclass 29, count 2 2006.285.23:57:45.62#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.285.23:57:45.62#ibcon#[27=AT01-04\r\n] 2006.285.23:57:45.62#ibcon#*before write, iclass 29, count 2 2006.285.23:57:45.62#ibcon#enter sib2, iclass 29, count 2 2006.285.23:57:45.62#ibcon#flushed, iclass 29, count 2 2006.285.23:57:45.62#ibcon#about to write, iclass 29, count 2 2006.285.23:57:45.62#ibcon#wrote, iclass 29, count 2 2006.285.23:57:45.62#ibcon#about to read 3, iclass 29, count 2 2006.285.23:57:45.65#ibcon#read 3, iclass 29, count 2 2006.285.23:57:45.65#ibcon#about to read 4, iclass 29, count 2 2006.285.23:57:45.65#ibcon#read 4, iclass 29, count 2 2006.285.23:57:45.65#ibcon#about to read 5, iclass 29, count 2 2006.285.23:57:45.65#ibcon#read 5, iclass 29, count 2 2006.285.23:57:45.65#ibcon#about to read 6, iclass 29, count 2 2006.285.23:57:45.65#ibcon#read 6, iclass 29, count 2 2006.285.23:57:45.65#ibcon#end of sib2, iclass 29, count 2 2006.285.23:57:45.65#ibcon#*after write, iclass 29, count 2 2006.285.23:57:45.65#ibcon#*before return 0, iclass 29, count 2 2006.285.23:57:45.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:57:45.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.285.23:57:45.65#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.285.23:57:45.65#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:45.65#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:57:45.77#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:57:45.77#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:57:45.77#ibcon#enter wrdev, iclass 29, count 0 2006.285.23:57:45.77#ibcon#first serial, iclass 29, count 0 2006.285.23:57:45.77#ibcon#enter sib2, iclass 29, count 0 2006.285.23:57:45.77#ibcon#flushed, iclass 29, count 0 2006.285.23:57:45.77#ibcon#about to write, iclass 29, count 0 2006.285.23:57:45.77#ibcon#wrote, iclass 29, count 0 2006.285.23:57:45.77#ibcon#about to read 3, iclass 29, count 0 2006.285.23:57:45.79#ibcon#read 3, iclass 29, count 0 2006.285.23:57:45.79#ibcon#about to read 4, iclass 29, count 0 2006.285.23:57:45.79#ibcon#read 4, iclass 29, count 0 2006.285.23:57:45.79#ibcon#about to read 5, iclass 29, count 0 2006.285.23:57:45.79#ibcon#read 5, iclass 29, count 0 2006.285.23:57:45.79#ibcon#about to read 6, iclass 29, count 0 2006.285.23:57:45.79#ibcon#read 6, iclass 29, count 0 2006.285.23:57:45.79#ibcon#end of sib2, iclass 29, count 0 2006.285.23:57:45.79#ibcon#*mode == 0, iclass 29, count 0 2006.285.23:57:45.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.285.23:57:45.79#ibcon#[27=USB\r\n] 2006.285.23:57:45.79#ibcon#*before write, iclass 29, count 0 2006.285.23:57:45.79#ibcon#enter sib2, iclass 29, count 0 2006.285.23:57:45.79#ibcon#flushed, iclass 29, count 0 2006.285.23:57:45.79#ibcon#about to write, iclass 29, count 0 2006.285.23:57:45.79#ibcon#wrote, iclass 29, count 0 2006.285.23:57:45.79#ibcon#about to read 3, iclass 29, count 0 2006.285.23:57:45.82#ibcon#read 3, iclass 29, count 0 2006.285.23:57:45.82#ibcon#about to read 4, iclass 29, count 0 2006.285.23:57:45.82#ibcon#read 4, iclass 29, count 0 2006.285.23:57:45.82#ibcon#about to read 5, iclass 29, count 0 2006.285.23:57:45.82#ibcon#read 5, iclass 29, count 0 2006.285.23:57:45.82#ibcon#about to read 6, iclass 29, count 0 2006.285.23:57:45.82#ibcon#read 6, iclass 29, count 0 2006.285.23:57:45.82#ibcon#end of sib2, iclass 29, count 0 2006.285.23:57:45.82#ibcon#*after write, iclass 29, count 0 2006.285.23:57:45.82#ibcon#*before return 0, iclass 29, count 0 2006.285.23:57:45.82#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:57:45.82#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.285.23:57:45.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.285.23:57:45.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.285.23:57:45.82$vck44/vblo=2,634.99 2006.285.23:57:45.82#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.285.23:57:45.82#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.285.23:57:45.82#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:45.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:57:45.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:57:45.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:57:45.82#ibcon#enter wrdev, iclass 31, count 0 2006.285.23:57:45.82#ibcon#first serial, iclass 31, count 0 2006.285.23:57:45.82#ibcon#enter sib2, iclass 31, count 0 2006.285.23:57:45.82#ibcon#flushed, iclass 31, count 0 2006.285.23:57:45.82#ibcon#about to write, iclass 31, count 0 2006.285.23:57:45.82#ibcon#wrote, iclass 31, count 0 2006.285.23:57:45.82#ibcon#about to read 3, iclass 31, count 0 2006.285.23:57:45.84#ibcon#read 3, iclass 31, count 0 2006.285.23:57:45.84#ibcon#about to read 4, iclass 31, count 0 2006.285.23:57:45.84#ibcon#read 4, iclass 31, count 0 2006.285.23:57:45.84#ibcon#about to read 5, iclass 31, count 0 2006.285.23:57:45.84#ibcon#read 5, iclass 31, count 0 2006.285.23:57:45.84#ibcon#about to read 6, iclass 31, count 0 2006.285.23:57:45.84#ibcon#read 6, iclass 31, count 0 2006.285.23:57:45.84#ibcon#end of sib2, iclass 31, count 0 2006.285.23:57:45.84#ibcon#*mode == 0, iclass 31, count 0 2006.285.23:57:45.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.285.23:57:45.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.285.23:57:45.84#ibcon#*before write, iclass 31, count 0 2006.285.23:57:45.84#ibcon#enter sib2, iclass 31, count 0 2006.285.23:57:45.84#ibcon#flushed, iclass 31, count 0 2006.285.23:57:45.84#ibcon#about to write, iclass 31, count 0 2006.285.23:57:45.84#ibcon#wrote, iclass 31, count 0 2006.285.23:57:45.84#ibcon#about to read 3, iclass 31, count 0 2006.285.23:57:45.88#ibcon#read 3, iclass 31, count 0 2006.285.23:57:45.88#ibcon#about to read 4, iclass 31, count 0 2006.285.23:57:45.88#ibcon#read 4, iclass 31, count 0 2006.285.23:57:45.88#ibcon#about to read 5, iclass 31, count 0 2006.285.23:57:45.88#ibcon#read 5, iclass 31, count 0 2006.285.23:57:45.88#ibcon#about to read 6, iclass 31, count 0 2006.285.23:57:45.88#ibcon#read 6, iclass 31, count 0 2006.285.23:57:45.88#ibcon#end of sib2, iclass 31, count 0 2006.285.23:57:45.88#ibcon#*after write, iclass 31, count 0 2006.285.23:57:45.88#ibcon#*before return 0, iclass 31, count 0 2006.285.23:57:45.88#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:57:45.88#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.285.23:57:45.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.285.23:57:45.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.285.23:57:45.88$vck44/vb=2,5 2006.285.23:57:45.88#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.285.23:57:45.88#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.285.23:57:45.88#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:45.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:57:45.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:57:45.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:57:45.94#ibcon#enter wrdev, iclass 33, count 2 2006.285.23:57:45.94#ibcon#first serial, iclass 33, count 2 2006.285.23:57:45.94#ibcon#enter sib2, iclass 33, count 2 2006.285.23:57:45.94#ibcon#flushed, iclass 33, count 2 2006.285.23:57:45.94#ibcon#about to write, iclass 33, count 2 2006.285.23:57:45.94#ibcon#wrote, iclass 33, count 2 2006.285.23:57:45.94#ibcon#about to read 3, iclass 33, count 2 2006.285.23:57:45.96#ibcon#read 3, iclass 33, count 2 2006.285.23:57:45.96#ibcon#about to read 4, iclass 33, count 2 2006.285.23:57:45.96#ibcon#read 4, iclass 33, count 2 2006.285.23:57:45.96#ibcon#about to read 5, iclass 33, count 2 2006.285.23:57:45.96#ibcon#read 5, iclass 33, count 2 2006.285.23:57:45.96#ibcon#about to read 6, iclass 33, count 2 2006.285.23:57:45.96#ibcon#read 6, iclass 33, count 2 2006.285.23:57:45.96#ibcon#end of sib2, iclass 33, count 2 2006.285.23:57:45.96#ibcon#*mode == 0, iclass 33, count 2 2006.285.23:57:45.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.285.23:57:45.96#ibcon#[27=AT02-05\r\n] 2006.285.23:57:45.96#ibcon#*before write, iclass 33, count 2 2006.285.23:57:45.96#ibcon#enter sib2, iclass 33, count 2 2006.285.23:57:45.96#ibcon#flushed, iclass 33, count 2 2006.285.23:57:45.96#ibcon#about to write, iclass 33, count 2 2006.285.23:57:45.96#ibcon#wrote, iclass 33, count 2 2006.285.23:57:45.96#ibcon#about to read 3, iclass 33, count 2 2006.285.23:57:45.99#ibcon#read 3, iclass 33, count 2 2006.285.23:57:45.99#ibcon#about to read 4, iclass 33, count 2 2006.285.23:57:45.99#ibcon#read 4, iclass 33, count 2 2006.285.23:57:45.99#ibcon#about to read 5, iclass 33, count 2 2006.285.23:57:45.99#ibcon#read 5, iclass 33, count 2 2006.285.23:57:45.99#ibcon#about to read 6, iclass 33, count 2 2006.285.23:57:45.99#ibcon#read 6, iclass 33, count 2 2006.285.23:57:45.99#ibcon#end of sib2, iclass 33, count 2 2006.285.23:57:45.99#ibcon#*after write, iclass 33, count 2 2006.285.23:57:45.99#ibcon#*before return 0, iclass 33, count 2 2006.285.23:57:45.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:57:45.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.285.23:57:45.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.285.23:57:45.99#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:45.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:57:46.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:57:46.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:57:46.11#ibcon#enter wrdev, iclass 33, count 0 2006.285.23:57:46.11#ibcon#first serial, iclass 33, count 0 2006.285.23:57:46.11#ibcon#enter sib2, iclass 33, count 0 2006.285.23:57:46.11#ibcon#flushed, iclass 33, count 0 2006.285.23:57:46.11#ibcon#about to write, iclass 33, count 0 2006.285.23:57:46.11#ibcon#wrote, iclass 33, count 0 2006.285.23:57:46.11#ibcon#about to read 3, iclass 33, count 0 2006.285.23:57:46.13#ibcon#read 3, iclass 33, count 0 2006.285.23:57:46.13#ibcon#about to read 4, iclass 33, count 0 2006.285.23:57:46.13#ibcon#read 4, iclass 33, count 0 2006.285.23:57:46.13#ibcon#about to read 5, iclass 33, count 0 2006.285.23:57:46.13#ibcon#read 5, iclass 33, count 0 2006.285.23:57:46.13#ibcon#about to read 6, iclass 33, count 0 2006.285.23:57:46.13#ibcon#read 6, iclass 33, count 0 2006.285.23:57:46.13#ibcon#end of sib2, iclass 33, count 0 2006.285.23:57:46.13#ibcon#*mode == 0, iclass 33, count 0 2006.285.23:57:46.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.285.23:57:46.13#ibcon#[27=USB\r\n] 2006.285.23:57:46.13#ibcon#*before write, iclass 33, count 0 2006.285.23:57:46.13#ibcon#enter sib2, iclass 33, count 0 2006.285.23:57:46.13#ibcon#flushed, iclass 33, count 0 2006.285.23:57:46.13#ibcon#about to write, iclass 33, count 0 2006.285.23:57:46.13#ibcon#wrote, iclass 33, count 0 2006.285.23:57:46.13#ibcon#about to read 3, iclass 33, count 0 2006.285.23:57:46.16#ibcon#read 3, iclass 33, count 0 2006.285.23:57:46.16#ibcon#about to read 4, iclass 33, count 0 2006.285.23:57:46.16#ibcon#read 4, iclass 33, count 0 2006.285.23:57:46.16#ibcon#about to read 5, iclass 33, count 0 2006.285.23:57:46.16#ibcon#read 5, iclass 33, count 0 2006.285.23:57:46.16#ibcon#about to read 6, iclass 33, count 0 2006.285.23:57:46.16#ibcon#read 6, iclass 33, count 0 2006.285.23:57:46.16#ibcon#end of sib2, iclass 33, count 0 2006.285.23:57:46.16#ibcon#*after write, iclass 33, count 0 2006.285.23:57:46.16#ibcon#*before return 0, iclass 33, count 0 2006.285.23:57:46.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:57:46.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.285.23:57:46.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.285.23:57:46.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.285.23:57:46.16$vck44/vblo=3,649.99 2006.285.23:57:46.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.285.23:57:46.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.285.23:57:46.16#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:46.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:57:46.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:57:46.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:57:46.16#ibcon#enter wrdev, iclass 35, count 0 2006.285.23:57:46.16#ibcon#first serial, iclass 35, count 0 2006.285.23:57:46.16#ibcon#enter sib2, iclass 35, count 0 2006.285.23:57:46.16#ibcon#flushed, iclass 35, count 0 2006.285.23:57:46.16#ibcon#about to write, iclass 35, count 0 2006.285.23:57:46.16#ibcon#wrote, iclass 35, count 0 2006.285.23:57:46.16#ibcon#about to read 3, iclass 35, count 0 2006.285.23:57:46.18#ibcon#read 3, iclass 35, count 0 2006.285.23:57:46.18#ibcon#about to read 4, iclass 35, count 0 2006.285.23:57:46.18#ibcon#read 4, iclass 35, count 0 2006.285.23:57:46.18#ibcon#about to read 5, iclass 35, count 0 2006.285.23:57:46.18#ibcon#read 5, iclass 35, count 0 2006.285.23:57:46.18#ibcon#about to read 6, iclass 35, count 0 2006.285.23:57:46.18#ibcon#read 6, iclass 35, count 0 2006.285.23:57:46.18#ibcon#end of sib2, iclass 35, count 0 2006.285.23:57:46.18#ibcon#*mode == 0, iclass 35, count 0 2006.285.23:57:46.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.285.23:57:46.18#ibcon#[28=FRQ=03,649.99\r\n] 2006.285.23:57:46.18#ibcon#*before write, iclass 35, count 0 2006.285.23:57:46.18#ibcon#enter sib2, iclass 35, count 0 2006.285.23:57:46.18#ibcon#flushed, iclass 35, count 0 2006.285.23:57:46.18#ibcon#about to write, iclass 35, count 0 2006.285.23:57:46.18#ibcon#wrote, iclass 35, count 0 2006.285.23:57:46.18#ibcon#about to read 3, iclass 35, count 0 2006.285.23:57:46.22#ibcon#read 3, iclass 35, count 0 2006.285.23:57:46.22#ibcon#about to read 4, iclass 35, count 0 2006.285.23:57:46.22#ibcon#read 4, iclass 35, count 0 2006.285.23:57:46.22#ibcon#about to read 5, iclass 35, count 0 2006.285.23:57:46.22#ibcon#read 5, iclass 35, count 0 2006.285.23:57:46.22#ibcon#about to read 6, iclass 35, count 0 2006.285.23:57:46.22#ibcon#read 6, iclass 35, count 0 2006.285.23:57:46.22#ibcon#end of sib2, iclass 35, count 0 2006.285.23:57:46.22#ibcon#*after write, iclass 35, count 0 2006.285.23:57:46.22#ibcon#*before return 0, iclass 35, count 0 2006.285.23:57:46.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:57:46.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.285.23:57:46.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.285.23:57:46.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.285.23:57:46.22$vck44/vb=3,4 2006.285.23:57:46.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.285.23:57:46.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.285.23:57:46.22#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:46.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:57:46.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:57:46.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:57:46.28#ibcon#enter wrdev, iclass 37, count 2 2006.285.23:57:46.28#ibcon#first serial, iclass 37, count 2 2006.285.23:57:46.28#ibcon#enter sib2, iclass 37, count 2 2006.285.23:57:46.28#ibcon#flushed, iclass 37, count 2 2006.285.23:57:46.28#ibcon#about to write, iclass 37, count 2 2006.285.23:57:46.28#ibcon#wrote, iclass 37, count 2 2006.285.23:57:46.28#ibcon#about to read 3, iclass 37, count 2 2006.285.23:57:46.30#ibcon#read 3, iclass 37, count 2 2006.285.23:57:46.30#ibcon#about to read 4, iclass 37, count 2 2006.285.23:57:46.30#ibcon#read 4, iclass 37, count 2 2006.285.23:57:46.30#ibcon#about to read 5, iclass 37, count 2 2006.285.23:57:46.30#ibcon#read 5, iclass 37, count 2 2006.285.23:57:46.30#ibcon#about to read 6, iclass 37, count 2 2006.285.23:57:46.30#ibcon#read 6, iclass 37, count 2 2006.285.23:57:46.30#ibcon#end of sib2, iclass 37, count 2 2006.285.23:57:46.30#ibcon#*mode == 0, iclass 37, count 2 2006.285.23:57:46.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.285.23:57:46.30#ibcon#[27=AT03-04\r\n] 2006.285.23:57:46.30#ibcon#*before write, iclass 37, count 2 2006.285.23:57:46.30#ibcon#enter sib2, iclass 37, count 2 2006.285.23:57:46.30#ibcon#flushed, iclass 37, count 2 2006.285.23:57:46.30#ibcon#about to write, iclass 37, count 2 2006.285.23:57:46.30#ibcon#wrote, iclass 37, count 2 2006.285.23:57:46.30#ibcon#about to read 3, iclass 37, count 2 2006.285.23:57:46.33#ibcon#read 3, iclass 37, count 2 2006.285.23:57:46.33#ibcon#about to read 4, iclass 37, count 2 2006.285.23:57:46.33#ibcon#read 4, iclass 37, count 2 2006.285.23:57:46.33#ibcon#about to read 5, iclass 37, count 2 2006.285.23:57:46.33#ibcon#read 5, iclass 37, count 2 2006.285.23:57:46.33#ibcon#about to read 6, iclass 37, count 2 2006.285.23:57:46.33#ibcon#read 6, iclass 37, count 2 2006.285.23:57:46.33#ibcon#end of sib2, iclass 37, count 2 2006.285.23:57:46.33#ibcon#*after write, iclass 37, count 2 2006.285.23:57:46.33#ibcon#*before return 0, iclass 37, count 2 2006.285.23:57:46.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:57:46.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.285.23:57:46.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.285.23:57:46.33#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:46.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:57:46.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:57:46.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:57:46.45#ibcon#enter wrdev, iclass 37, count 0 2006.285.23:57:46.45#ibcon#first serial, iclass 37, count 0 2006.285.23:57:46.45#ibcon#enter sib2, iclass 37, count 0 2006.285.23:57:46.45#ibcon#flushed, iclass 37, count 0 2006.285.23:57:46.45#ibcon#about to write, iclass 37, count 0 2006.285.23:57:46.45#ibcon#wrote, iclass 37, count 0 2006.285.23:57:46.45#ibcon#about to read 3, iclass 37, count 0 2006.285.23:57:46.47#ibcon#read 3, iclass 37, count 0 2006.285.23:57:46.47#ibcon#about to read 4, iclass 37, count 0 2006.285.23:57:46.47#ibcon#read 4, iclass 37, count 0 2006.285.23:57:46.47#ibcon#about to read 5, iclass 37, count 0 2006.285.23:57:46.47#ibcon#read 5, iclass 37, count 0 2006.285.23:57:46.47#ibcon#about to read 6, iclass 37, count 0 2006.285.23:57:46.47#ibcon#read 6, iclass 37, count 0 2006.285.23:57:46.47#ibcon#end of sib2, iclass 37, count 0 2006.285.23:57:46.47#ibcon#*mode == 0, iclass 37, count 0 2006.285.23:57:46.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.285.23:57:46.47#ibcon#[27=USB\r\n] 2006.285.23:57:46.47#ibcon#*before write, iclass 37, count 0 2006.285.23:57:46.47#ibcon#enter sib2, iclass 37, count 0 2006.285.23:57:46.47#ibcon#flushed, iclass 37, count 0 2006.285.23:57:46.47#ibcon#about to write, iclass 37, count 0 2006.285.23:57:46.47#ibcon#wrote, iclass 37, count 0 2006.285.23:57:46.47#ibcon#about to read 3, iclass 37, count 0 2006.285.23:57:46.50#ibcon#read 3, iclass 37, count 0 2006.285.23:57:46.50#ibcon#about to read 4, iclass 37, count 0 2006.285.23:57:46.50#ibcon#read 4, iclass 37, count 0 2006.285.23:57:46.50#ibcon#about to read 5, iclass 37, count 0 2006.285.23:57:46.50#ibcon#read 5, iclass 37, count 0 2006.285.23:57:46.50#ibcon#about to read 6, iclass 37, count 0 2006.285.23:57:46.50#ibcon#read 6, iclass 37, count 0 2006.285.23:57:46.50#ibcon#end of sib2, iclass 37, count 0 2006.285.23:57:46.50#ibcon#*after write, iclass 37, count 0 2006.285.23:57:46.50#ibcon#*before return 0, iclass 37, count 0 2006.285.23:57:46.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:57:46.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.285.23:57:46.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.285.23:57:46.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.285.23:57:46.50$vck44/vblo=4,679.99 2006.285.23:57:46.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.285.23:57:46.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.285.23:57:46.50#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:46.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:57:46.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:57:46.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:57:46.50#ibcon#enter wrdev, iclass 39, count 0 2006.285.23:57:46.50#ibcon#first serial, iclass 39, count 0 2006.285.23:57:46.50#ibcon#enter sib2, iclass 39, count 0 2006.285.23:57:46.50#ibcon#flushed, iclass 39, count 0 2006.285.23:57:46.50#ibcon#about to write, iclass 39, count 0 2006.285.23:57:46.50#ibcon#wrote, iclass 39, count 0 2006.285.23:57:46.50#ibcon#about to read 3, iclass 39, count 0 2006.285.23:57:46.52#ibcon#read 3, iclass 39, count 0 2006.285.23:57:46.52#ibcon#about to read 4, iclass 39, count 0 2006.285.23:57:46.52#ibcon#read 4, iclass 39, count 0 2006.285.23:57:46.52#ibcon#about to read 5, iclass 39, count 0 2006.285.23:57:46.52#ibcon#read 5, iclass 39, count 0 2006.285.23:57:46.52#ibcon#about to read 6, iclass 39, count 0 2006.285.23:57:46.52#ibcon#read 6, iclass 39, count 0 2006.285.23:57:46.52#ibcon#end of sib2, iclass 39, count 0 2006.285.23:57:46.52#ibcon#*mode == 0, iclass 39, count 0 2006.285.23:57:46.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.285.23:57:46.52#ibcon#[28=FRQ=04,679.99\r\n] 2006.285.23:57:46.52#ibcon#*before write, iclass 39, count 0 2006.285.23:57:46.52#ibcon#enter sib2, iclass 39, count 0 2006.285.23:57:46.52#ibcon#flushed, iclass 39, count 0 2006.285.23:57:46.52#ibcon#about to write, iclass 39, count 0 2006.285.23:57:46.52#ibcon#wrote, iclass 39, count 0 2006.285.23:57:46.52#ibcon#about to read 3, iclass 39, count 0 2006.285.23:57:46.56#ibcon#read 3, iclass 39, count 0 2006.285.23:57:46.56#ibcon#about to read 4, iclass 39, count 0 2006.285.23:57:46.56#ibcon#read 4, iclass 39, count 0 2006.285.23:57:46.56#ibcon#about to read 5, iclass 39, count 0 2006.285.23:57:46.56#ibcon#read 5, iclass 39, count 0 2006.285.23:57:46.56#ibcon#about to read 6, iclass 39, count 0 2006.285.23:57:46.56#ibcon#read 6, iclass 39, count 0 2006.285.23:57:46.56#ibcon#end of sib2, iclass 39, count 0 2006.285.23:57:46.56#ibcon#*after write, iclass 39, count 0 2006.285.23:57:46.56#ibcon#*before return 0, iclass 39, count 0 2006.285.23:57:46.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:57:46.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.285.23:57:46.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.285.23:57:46.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.285.23:57:46.56$vck44/vb=4,5 2006.285.23:57:46.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.285.23:57:46.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.285.23:57:46.56#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:46.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:57:46.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:57:46.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:57:46.62#ibcon#enter wrdev, iclass 3, count 2 2006.285.23:57:46.62#ibcon#first serial, iclass 3, count 2 2006.285.23:57:46.62#ibcon#enter sib2, iclass 3, count 2 2006.285.23:57:46.62#ibcon#flushed, iclass 3, count 2 2006.285.23:57:46.62#ibcon#about to write, iclass 3, count 2 2006.285.23:57:46.62#ibcon#wrote, iclass 3, count 2 2006.285.23:57:46.62#ibcon#about to read 3, iclass 3, count 2 2006.285.23:57:46.64#ibcon#read 3, iclass 3, count 2 2006.285.23:57:46.64#ibcon#about to read 4, iclass 3, count 2 2006.285.23:57:46.64#ibcon#read 4, iclass 3, count 2 2006.285.23:57:46.64#ibcon#about to read 5, iclass 3, count 2 2006.285.23:57:46.64#ibcon#read 5, iclass 3, count 2 2006.285.23:57:46.64#ibcon#about to read 6, iclass 3, count 2 2006.285.23:57:46.64#ibcon#read 6, iclass 3, count 2 2006.285.23:57:46.64#ibcon#end of sib2, iclass 3, count 2 2006.285.23:57:46.64#ibcon#*mode == 0, iclass 3, count 2 2006.285.23:57:46.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.285.23:57:46.64#ibcon#[27=AT04-05\r\n] 2006.285.23:57:46.64#ibcon#*before write, iclass 3, count 2 2006.285.23:57:46.64#ibcon#enter sib2, iclass 3, count 2 2006.285.23:57:46.64#ibcon#flushed, iclass 3, count 2 2006.285.23:57:46.64#ibcon#about to write, iclass 3, count 2 2006.285.23:57:46.64#ibcon#wrote, iclass 3, count 2 2006.285.23:57:46.64#ibcon#about to read 3, iclass 3, count 2 2006.285.23:57:46.67#ibcon#read 3, iclass 3, count 2 2006.285.23:57:46.67#ibcon#about to read 4, iclass 3, count 2 2006.285.23:57:46.67#ibcon#read 4, iclass 3, count 2 2006.285.23:57:46.67#ibcon#about to read 5, iclass 3, count 2 2006.285.23:57:46.67#ibcon#read 5, iclass 3, count 2 2006.285.23:57:46.67#ibcon#about to read 6, iclass 3, count 2 2006.285.23:57:46.67#ibcon#read 6, iclass 3, count 2 2006.285.23:57:46.67#ibcon#end of sib2, iclass 3, count 2 2006.285.23:57:46.67#ibcon#*after write, iclass 3, count 2 2006.285.23:57:46.67#ibcon#*before return 0, iclass 3, count 2 2006.285.23:57:46.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:57:46.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.285.23:57:46.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.285.23:57:46.67#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:46.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:57:46.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:57:46.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:57:46.79#ibcon#enter wrdev, iclass 3, count 0 2006.285.23:57:46.79#ibcon#first serial, iclass 3, count 0 2006.285.23:57:46.79#ibcon#enter sib2, iclass 3, count 0 2006.285.23:57:46.79#ibcon#flushed, iclass 3, count 0 2006.285.23:57:46.79#ibcon#about to write, iclass 3, count 0 2006.285.23:57:46.79#ibcon#wrote, iclass 3, count 0 2006.285.23:57:46.79#ibcon#about to read 3, iclass 3, count 0 2006.285.23:57:46.81#ibcon#read 3, iclass 3, count 0 2006.285.23:57:46.81#ibcon#about to read 4, iclass 3, count 0 2006.285.23:57:46.81#ibcon#read 4, iclass 3, count 0 2006.285.23:57:46.81#ibcon#about to read 5, iclass 3, count 0 2006.285.23:57:46.81#ibcon#read 5, iclass 3, count 0 2006.285.23:57:46.81#ibcon#about to read 6, iclass 3, count 0 2006.285.23:57:46.81#ibcon#read 6, iclass 3, count 0 2006.285.23:57:46.81#ibcon#end of sib2, iclass 3, count 0 2006.285.23:57:46.81#ibcon#*mode == 0, iclass 3, count 0 2006.285.23:57:46.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.285.23:57:46.81#ibcon#[27=USB\r\n] 2006.285.23:57:46.81#ibcon#*before write, iclass 3, count 0 2006.285.23:57:46.81#ibcon#enter sib2, iclass 3, count 0 2006.285.23:57:46.81#ibcon#flushed, iclass 3, count 0 2006.285.23:57:46.81#ibcon#about to write, iclass 3, count 0 2006.285.23:57:46.81#ibcon#wrote, iclass 3, count 0 2006.285.23:57:46.81#ibcon#about to read 3, iclass 3, count 0 2006.285.23:57:46.84#ibcon#read 3, iclass 3, count 0 2006.285.23:57:46.84#ibcon#about to read 4, iclass 3, count 0 2006.285.23:57:46.84#ibcon#read 4, iclass 3, count 0 2006.285.23:57:46.84#ibcon#about to read 5, iclass 3, count 0 2006.285.23:57:46.84#ibcon#read 5, iclass 3, count 0 2006.285.23:57:46.84#ibcon#about to read 6, iclass 3, count 0 2006.285.23:57:46.84#ibcon#read 6, iclass 3, count 0 2006.285.23:57:46.84#ibcon#end of sib2, iclass 3, count 0 2006.285.23:57:46.84#ibcon#*after write, iclass 3, count 0 2006.285.23:57:46.84#ibcon#*before return 0, iclass 3, count 0 2006.285.23:57:46.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:57:46.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.285.23:57:46.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.285.23:57:46.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.285.23:57:46.84$vck44/vblo=5,709.99 2006.285.23:57:46.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.285.23:57:46.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.285.23:57:46.84#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:46.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:57:46.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:57:46.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:57:46.84#ibcon#enter wrdev, iclass 5, count 0 2006.285.23:57:46.84#ibcon#first serial, iclass 5, count 0 2006.285.23:57:46.84#ibcon#enter sib2, iclass 5, count 0 2006.285.23:57:46.84#ibcon#flushed, iclass 5, count 0 2006.285.23:57:46.84#ibcon#about to write, iclass 5, count 0 2006.285.23:57:46.84#ibcon#wrote, iclass 5, count 0 2006.285.23:57:46.84#ibcon#about to read 3, iclass 5, count 0 2006.285.23:57:46.86#ibcon#read 3, iclass 5, count 0 2006.285.23:57:46.86#ibcon#about to read 4, iclass 5, count 0 2006.285.23:57:46.86#ibcon#read 4, iclass 5, count 0 2006.285.23:57:46.86#ibcon#about to read 5, iclass 5, count 0 2006.285.23:57:46.86#ibcon#read 5, iclass 5, count 0 2006.285.23:57:46.86#ibcon#about to read 6, iclass 5, count 0 2006.285.23:57:46.86#ibcon#read 6, iclass 5, count 0 2006.285.23:57:46.86#ibcon#end of sib2, iclass 5, count 0 2006.285.23:57:46.86#ibcon#*mode == 0, iclass 5, count 0 2006.285.23:57:46.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.285.23:57:46.86#ibcon#[28=FRQ=05,709.99\r\n] 2006.285.23:57:46.86#ibcon#*before write, iclass 5, count 0 2006.285.23:57:46.86#ibcon#enter sib2, iclass 5, count 0 2006.285.23:57:46.86#ibcon#flushed, iclass 5, count 0 2006.285.23:57:46.86#ibcon#about to write, iclass 5, count 0 2006.285.23:57:46.86#ibcon#wrote, iclass 5, count 0 2006.285.23:57:46.86#ibcon#about to read 3, iclass 5, count 0 2006.285.23:57:46.90#ibcon#read 3, iclass 5, count 0 2006.285.23:57:46.90#ibcon#about to read 4, iclass 5, count 0 2006.285.23:57:46.90#ibcon#read 4, iclass 5, count 0 2006.285.23:57:46.90#ibcon#about to read 5, iclass 5, count 0 2006.285.23:57:46.90#ibcon#read 5, iclass 5, count 0 2006.285.23:57:46.90#ibcon#about to read 6, iclass 5, count 0 2006.285.23:57:46.90#ibcon#read 6, iclass 5, count 0 2006.285.23:57:46.90#ibcon#end of sib2, iclass 5, count 0 2006.285.23:57:46.90#ibcon#*after write, iclass 5, count 0 2006.285.23:57:46.90#ibcon#*before return 0, iclass 5, count 0 2006.285.23:57:46.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:57:46.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.285.23:57:46.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.285.23:57:46.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.285.23:57:46.90$vck44/vb=5,4 2006.285.23:57:46.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.285.23:57:46.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.285.23:57:46.90#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:46.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:57:46.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:57:46.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:57:46.96#ibcon#enter wrdev, iclass 7, count 2 2006.285.23:57:46.96#ibcon#first serial, iclass 7, count 2 2006.285.23:57:46.96#ibcon#enter sib2, iclass 7, count 2 2006.285.23:57:46.96#ibcon#flushed, iclass 7, count 2 2006.285.23:57:46.96#ibcon#about to write, iclass 7, count 2 2006.285.23:57:46.96#ibcon#wrote, iclass 7, count 2 2006.285.23:57:46.96#ibcon#about to read 3, iclass 7, count 2 2006.285.23:57:46.98#ibcon#read 3, iclass 7, count 2 2006.285.23:57:46.98#ibcon#about to read 4, iclass 7, count 2 2006.285.23:57:46.98#ibcon#read 4, iclass 7, count 2 2006.285.23:57:46.98#ibcon#about to read 5, iclass 7, count 2 2006.285.23:57:46.98#ibcon#read 5, iclass 7, count 2 2006.285.23:57:46.98#ibcon#about to read 6, iclass 7, count 2 2006.285.23:57:46.98#ibcon#read 6, iclass 7, count 2 2006.285.23:57:46.98#ibcon#end of sib2, iclass 7, count 2 2006.285.23:57:46.98#ibcon#*mode == 0, iclass 7, count 2 2006.285.23:57:46.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.285.23:57:46.98#ibcon#[27=AT05-04\r\n] 2006.285.23:57:46.98#ibcon#*before write, iclass 7, count 2 2006.285.23:57:46.98#ibcon#enter sib2, iclass 7, count 2 2006.285.23:57:46.98#ibcon#flushed, iclass 7, count 2 2006.285.23:57:46.98#ibcon#about to write, iclass 7, count 2 2006.285.23:57:46.98#ibcon#wrote, iclass 7, count 2 2006.285.23:57:46.98#ibcon#about to read 3, iclass 7, count 2 2006.285.23:57:47.01#ibcon#read 3, iclass 7, count 2 2006.285.23:57:47.01#ibcon#about to read 4, iclass 7, count 2 2006.285.23:57:47.01#ibcon#read 4, iclass 7, count 2 2006.285.23:57:47.01#ibcon#about to read 5, iclass 7, count 2 2006.285.23:57:47.01#ibcon#read 5, iclass 7, count 2 2006.285.23:57:47.01#ibcon#about to read 6, iclass 7, count 2 2006.285.23:57:47.01#ibcon#read 6, iclass 7, count 2 2006.285.23:57:47.01#ibcon#end of sib2, iclass 7, count 2 2006.285.23:57:47.01#ibcon#*after write, iclass 7, count 2 2006.285.23:57:47.01#ibcon#*before return 0, iclass 7, count 2 2006.285.23:57:47.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:57:47.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.285.23:57:47.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.285.23:57:47.01#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:47.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:57:47.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:57:47.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:57:47.13#ibcon#enter wrdev, iclass 7, count 0 2006.285.23:57:47.13#ibcon#first serial, iclass 7, count 0 2006.285.23:57:47.13#ibcon#enter sib2, iclass 7, count 0 2006.285.23:57:47.13#ibcon#flushed, iclass 7, count 0 2006.285.23:57:47.13#ibcon#about to write, iclass 7, count 0 2006.285.23:57:47.13#ibcon#wrote, iclass 7, count 0 2006.285.23:57:47.13#ibcon#about to read 3, iclass 7, count 0 2006.285.23:57:47.15#ibcon#read 3, iclass 7, count 0 2006.285.23:57:47.15#ibcon#about to read 4, iclass 7, count 0 2006.285.23:57:47.15#ibcon#read 4, iclass 7, count 0 2006.285.23:57:47.15#ibcon#about to read 5, iclass 7, count 0 2006.285.23:57:47.15#ibcon#read 5, iclass 7, count 0 2006.285.23:57:47.15#ibcon#about to read 6, iclass 7, count 0 2006.285.23:57:47.15#ibcon#read 6, iclass 7, count 0 2006.285.23:57:47.15#ibcon#end of sib2, iclass 7, count 0 2006.285.23:57:47.15#ibcon#*mode == 0, iclass 7, count 0 2006.285.23:57:47.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.285.23:57:47.15#ibcon#[27=USB\r\n] 2006.285.23:57:47.15#ibcon#*before write, iclass 7, count 0 2006.285.23:57:47.15#ibcon#enter sib2, iclass 7, count 0 2006.285.23:57:47.15#ibcon#flushed, iclass 7, count 0 2006.285.23:57:47.15#ibcon#about to write, iclass 7, count 0 2006.285.23:57:47.15#ibcon#wrote, iclass 7, count 0 2006.285.23:57:47.15#ibcon#about to read 3, iclass 7, count 0 2006.285.23:57:47.18#ibcon#read 3, iclass 7, count 0 2006.285.23:57:47.18#ibcon#about to read 4, iclass 7, count 0 2006.285.23:57:47.18#ibcon#read 4, iclass 7, count 0 2006.285.23:57:47.18#ibcon#about to read 5, iclass 7, count 0 2006.285.23:57:47.18#ibcon#read 5, iclass 7, count 0 2006.285.23:57:47.18#ibcon#about to read 6, iclass 7, count 0 2006.285.23:57:47.18#ibcon#read 6, iclass 7, count 0 2006.285.23:57:47.18#ibcon#end of sib2, iclass 7, count 0 2006.285.23:57:47.18#ibcon#*after write, iclass 7, count 0 2006.285.23:57:47.18#ibcon#*before return 0, iclass 7, count 0 2006.285.23:57:47.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:57:47.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.285.23:57:47.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.285.23:57:47.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.285.23:57:47.18$vck44/vblo=6,719.99 2006.285.23:57:47.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.285.23:57:47.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.285.23:57:47.18#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:47.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:57:47.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:57:47.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:57:47.18#ibcon#enter wrdev, iclass 11, count 0 2006.285.23:57:47.18#ibcon#first serial, iclass 11, count 0 2006.285.23:57:47.18#ibcon#enter sib2, iclass 11, count 0 2006.285.23:57:47.18#ibcon#flushed, iclass 11, count 0 2006.285.23:57:47.18#ibcon#about to write, iclass 11, count 0 2006.285.23:57:47.18#ibcon#wrote, iclass 11, count 0 2006.285.23:57:47.18#ibcon#about to read 3, iclass 11, count 0 2006.285.23:57:47.20#ibcon#read 3, iclass 11, count 0 2006.285.23:57:47.20#ibcon#about to read 4, iclass 11, count 0 2006.285.23:57:47.20#ibcon#read 4, iclass 11, count 0 2006.285.23:57:47.20#ibcon#about to read 5, iclass 11, count 0 2006.285.23:57:47.20#ibcon#read 5, iclass 11, count 0 2006.285.23:57:47.20#ibcon#about to read 6, iclass 11, count 0 2006.285.23:57:47.20#ibcon#read 6, iclass 11, count 0 2006.285.23:57:47.20#ibcon#end of sib2, iclass 11, count 0 2006.285.23:57:47.20#ibcon#*mode == 0, iclass 11, count 0 2006.285.23:57:47.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.285.23:57:47.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.285.23:57:47.20#ibcon#*before write, iclass 11, count 0 2006.285.23:57:47.20#ibcon#enter sib2, iclass 11, count 0 2006.285.23:57:47.20#ibcon#flushed, iclass 11, count 0 2006.285.23:57:47.20#ibcon#about to write, iclass 11, count 0 2006.285.23:57:47.20#ibcon#wrote, iclass 11, count 0 2006.285.23:57:47.20#ibcon#about to read 3, iclass 11, count 0 2006.285.23:57:47.24#ibcon#read 3, iclass 11, count 0 2006.285.23:57:47.24#ibcon#about to read 4, iclass 11, count 0 2006.285.23:57:47.24#ibcon#read 4, iclass 11, count 0 2006.285.23:57:47.24#ibcon#about to read 5, iclass 11, count 0 2006.285.23:57:47.24#ibcon#read 5, iclass 11, count 0 2006.285.23:57:47.24#ibcon#about to read 6, iclass 11, count 0 2006.285.23:57:47.24#ibcon#read 6, iclass 11, count 0 2006.285.23:57:47.24#ibcon#end of sib2, iclass 11, count 0 2006.285.23:57:47.24#ibcon#*after write, iclass 11, count 0 2006.285.23:57:47.24#ibcon#*before return 0, iclass 11, count 0 2006.285.23:57:47.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:57:47.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.285.23:57:47.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.285.23:57:47.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.285.23:57:47.24$vck44/vb=6,3 2006.285.23:57:47.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.285.23:57:47.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.285.23:57:47.24#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:47.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:57:47.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:57:47.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:57:47.30#ibcon#enter wrdev, iclass 13, count 2 2006.285.23:57:47.30#ibcon#first serial, iclass 13, count 2 2006.285.23:57:47.30#ibcon#enter sib2, iclass 13, count 2 2006.285.23:57:47.30#ibcon#flushed, iclass 13, count 2 2006.285.23:57:47.30#ibcon#about to write, iclass 13, count 2 2006.285.23:57:47.30#ibcon#wrote, iclass 13, count 2 2006.285.23:57:47.30#ibcon#about to read 3, iclass 13, count 2 2006.285.23:57:47.32#ibcon#read 3, iclass 13, count 2 2006.285.23:57:47.32#ibcon#about to read 4, iclass 13, count 2 2006.285.23:57:47.32#ibcon#read 4, iclass 13, count 2 2006.285.23:57:47.32#ibcon#about to read 5, iclass 13, count 2 2006.285.23:57:47.32#ibcon#read 5, iclass 13, count 2 2006.285.23:57:47.32#ibcon#about to read 6, iclass 13, count 2 2006.285.23:57:47.32#ibcon#read 6, iclass 13, count 2 2006.285.23:57:47.32#ibcon#end of sib2, iclass 13, count 2 2006.285.23:57:47.32#ibcon#*mode == 0, iclass 13, count 2 2006.285.23:57:47.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.285.23:57:47.32#ibcon#[27=AT06-03\r\n] 2006.285.23:57:47.32#ibcon#*before write, iclass 13, count 2 2006.285.23:57:47.32#ibcon#enter sib2, iclass 13, count 2 2006.285.23:57:47.32#ibcon#flushed, iclass 13, count 2 2006.285.23:57:47.32#ibcon#about to write, iclass 13, count 2 2006.285.23:57:47.32#ibcon#wrote, iclass 13, count 2 2006.285.23:57:47.32#ibcon#about to read 3, iclass 13, count 2 2006.285.23:57:47.35#ibcon#read 3, iclass 13, count 2 2006.285.23:57:47.35#ibcon#about to read 4, iclass 13, count 2 2006.285.23:57:47.35#ibcon#read 4, iclass 13, count 2 2006.285.23:57:47.35#ibcon#about to read 5, iclass 13, count 2 2006.285.23:57:47.35#ibcon#read 5, iclass 13, count 2 2006.285.23:57:47.35#ibcon#about to read 6, iclass 13, count 2 2006.285.23:57:47.35#ibcon#read 6, iclass 13, count 2 2006.285.23:57:47.35#ibcon#end of sib2, iclass 13, count 2 2006.285.23:57:47.35#ibcon#*after write, iclass 13, count 2 2006.285.23:57:47.35#ibcon#*before return 0, iclass 13, count 2 2006.285.23:57:47.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:57:47.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.285.23:57:47.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.285.23:57:47.35#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:47.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:57:47.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:57:47.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:57:47.47#ibcon#enter wrdev, iclass 13, count 0 2006.285.23:57:47.47#ibcon#first serial, iclass 13, count 0 2006.285.23:57:47.47#ibcon#enter sib2, iclass 13, count 0 2006.285.23:57:47.47#ibcon#flushed, iclass 13, count 0 2006.285.23:57:47.47#ibcon#about to write, iclass 13, count 0 2006.285.23:57:47.47#ibcon#wrote, iclass 13, count 0 2006.285.23:57:47.47#ibcon#about to read 3, iclass 13, count 0 2006.285.23:57:47.49#ibcon#read 3, iclass 13, count 0 2006.285.23:57:47.49#ibcon#about to read 4, iclass 13, count 0 2006.285.23:57:47.49#ibcon#read 4, iclass 13, count 0 2006.285.23:57:47.49#ibcon#about to read 5, iclass 13, count 0 2006.285.23:57:47.49#ibcon#read 5, iclass 13, count 0 2006.285.23:57:47.49#ibcon#about to read 6, iclass 13, count 0 2006.285.23:57:47.49#ibcon#read 6, iclass 13, count 0 2006.285.23:57:47.49#ibcon#end of sib2, iclass 13, count 0 2006.285.23:57:47.49#ibcon#*mode == 0, iclass 13, count 0 2006.285.23:57:47.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.285.23:57:47.49#ibcon#[27=USB\r\n] 2006.285.23:57:47.49#ibcon#*before write, iclass 13, count 0 2006.285.23:57:47.49#ibcon#enter sib2, iclass 13, count 0 2006.285.23:57:47.49#ibcon#flushed, iclass 13, count 0 2006.285.23:57:47.49#ibcon#about to write, iclass 13, count 0 2006.285.23:57:47.49#ibcon#wrote, iclass 13, count 0 2006.285.23:57:47.49#ibcon#about to read 3, iclass 13, count 0 2006.285.23:57:47.52#ibcon#read 3, iclass 13, count 0 2006.285.23:57:47.52#ibcon#about to read 4, iclass 13, count 0 2006.285.23:57:47.52#ibcon#read 4, iclass 13, count 0 2006.285.23:57:47.52#ibcon#about to read 5, iclass 13, count 0 2006.285.23:57:47.52#ibcon#read 5, iclass 13, count 0 2006.285.23:57:47.52#ibcon#about to read 6, iclass 13, count 0 2006.285.23:57:47.52#ibcon#read 6, iclass 13, count 0 2006.285.23:57:47.52#ibcon#end of sib2, iclass 13, count 0 2006.285.23:57:47.52#ibcon#*after write, iclass 13, count 0 2006.285.23:57:47.52#ibcon#*before return 0, iclass 13, count 0 2006.285.23:57:47.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:57:47.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.285.23:57:47.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.285.23:57:47.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.285.23:57:47.52$vck44/vblo=7,734.99 2006.285.23:57:47.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.285.23:57:47.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.285.23:57:47.52#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:47.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:57:47.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:57:47.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:57:47.52#ibcon#enter wrdev, iclass 15, count 0 2006.285.23:57:47.52#ibcon#first serial, iclass 15, count 0 2006.285.23:57:47.52#ibcon#enter sib2, iclass 15, count 0 2006.285.23:57:47.52#ibcon#flushed, iclass 15, count 0 2006.285.23:57:47.52#ibcon#about to write, iclass 15, count 0 2006.285.23:57:47.52#ibcon#wrote, iclass 15, count 0 2006.285.23:57:47.52#ibcon#about to read 3, iclass 15, count 0 2006.285.23:57:47.54#ibcon#read 3, iclass 15, count 0 2006.285.23:57:47.54#ibcon#about to read 4, iclass 15, count 0 2006.285.23:57:47.54#ibcon#read 4, iclass 15, count 0 2006.285.23:57:47.54#ibcon#about to read 5, iclass 15, count 0 2006.285.23:57:47.54#ibcon#read 5, iclass 15, count 0 2006.285.23:57:47.54#ibcon#about to read 6, iclass 15, count 0 2006.285.23:57:47.54#ibcon#read 6, iclass 15, count 0 2006.285.23:57:47.54#ibcon#end of sib2, iclass 15, count 0 2006.285.23:57:47.54#ibcon#*mode == 0, iclass 15, count 0 2006.285.23:57:47.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.285.23:57:47.54#ibcon#[28=FRQ=07,734.99\r\n] 2006.285.23:57:47.54#ibcon#*before write, iclass 15, count 0 2006.285.23:57:47.54#ibcon#enter sib2, iclass 15, count 0 2006.285.23:57:47.54#ibcon#flushed, iclass 15, count 0 2006.285.23:57:47.54#ibcon#about to write, iclass 15, count 0 2006.285.23:57:47.54#ibcon#wrote, iclass 15, count 0 2006.285.23:57:47.54#ibcon#about to read 3, iclass 15, count 0 2006.285.23:57:47.58#ibcon#read 3, iclass 15, count 0 2006.285.23:57:47.58#ibcon#about to read 4, iclass 15, count 0 2006.285.23:57:47.58#ibcon#read 4, iclass 15, count 0 2006.285.23:57:47.58#ibcon#about to read 5, iclass 15, count 0 2006.285.23:57:47.58#ibcon#read 5, iclass 15, count 0 2006.285.23:57:47.58#ibcon#about to read 6, iclass 15, count 0 2006.285.23:57:47.58#ibcon#read 6, iclass 15, count 0 2006.285.23:57:47.58#ibcon#end of sib2, iclass 15, count 0 2006.285.23:57:47.58#ibcon#*after write, iclass 15, count 0 2006.285.23:57:47.58#ibcon#*before return 0, iclass 15, count 0 2006.285.23:57:47.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:57:47.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.285.23:57:47.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.285.23:57:47.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.285.23:57:47.58$vck44/vb=7,4 2006.285.23:57:47.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.285.23:57:47.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.285.23:57:47.58#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:47.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:57:47.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:57:47.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:57:47.64#ibcon#enter wrdev, iclass 17, count 2 2006.285.23:57:47.64#ibcon#first serial, iclass 17, count 2 2006.285.23:57:47.64#ibcon#enter sib2, iclass 17, count 2 2006.285.23:57:47.64#ibcon#flushed, iclass 17, count 2 2006.285.23:57:47.64#ibcon#about to write, iclass 17, count 2 2006.285.23:57:47.64#ibcon#wrote, iclass 17, count 2 2006.285.23:57:47.64#ibcon#about to read 3, iclass 17, count 2 2006.285.23:57:47.66#ibcon#read 3, iclass 17, count 2 2006.285.23:57:47.66#ibcon#about to read 4, iclass 17, count 2 2006.285.23:57:47.66#ibcon#read 4, iclass 17, count 2 2006.285.23:57:47.66#ibcon#about to read 5, iclass 17, count 2 2006.285.23:57:47.66#ibcon#read 5, iclass 17, count 2 2006.285.23:57:47.66#ibcon#about to read 6, iclass 17, count 2 2006.285.23:57:47.66#ibcon#read 6, iclass 17, count 2 2006.285.23:57:47.66#ibcon#end of sib2, iclass 17, count 2 2006.285.23:57:47.66#ibcon#*mode == 0, iclass 17, count 2 2006.285.23:57:47.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.285.23:57:47.66#ibcon#[27=AT07-04\r\n] 2006.285.23:57:47.66#ibcon#*before write, iclass 17, count 2 2006.285.23:57:47.66#ibcon#enter sib2, iclass 17, count 2 2006.285.23:57:47.66#ibcon#flushed, iclass 17, count 2 2006.285.23:57:47.66#ibcon#about to write, iclass 17, count 2 2006.285.23:57:47.66#ibcon#wrote, iclass 17, count 2 2006.285.23:57:47.66#ibcon#about to read 3, iclass 17, count 2 2006.285.23:57:47.69#ibcon#read 3, iclass 17, count 2 2006.285.23:57:47.69#ibcon#about to read 4, iclass 17, count 2 2006.285.23:57:47.69#ibcon#read 4, iclass 17, count 2 2006.285.23:57:47.69#ibcon#about to read 5, iclass 17, count 2 2006.285.23:57:47.69#ibcon#read 5, iclass 17, count 2 2006.285.23:57:47.69#ibcon#about to read 6, iclass 17, count 2 2006.285.23:57:47.69#ibcon#read 6, iclass 17, count 2 2006.285.23:57:47.69#ibcon#end of sib2, iclass 17, count 2 2006.285.23:57:47.69#ibcon#*after write, iclass 17, count 2 2006.285.23:57:47.69#ibcon#*before return 0, iclass 17, count 2 2006.285.23:57:47.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:57:47.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.285.23:57:47.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.285.23:57:47.69#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:47.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:57:47.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:57:47.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:57:47.81#ibcon#enter wrdev, iclass 17, count 0 2006.285.23:57:47.81#ibcon#first serial, iclass 17, count 0 2006.285.23:57:47.81#ibcon#enter sib2, iclass 17, count 0 2006.285.23:57:47.81#ibcon#flushed, iclass 17, count 0 2006.285.23:57:47.81#ibcon#about to write, iclass 17, count 0 2006.285.23:57:47.81#ibcon#wrote, iclass 17, count 0 2006.285.23:57:47.81#ibcon#about to read 3, iclass 17, count 0 2006.285.23:57:47.83#ibcon#read 3, iclass 17, count 0 2006.285.23:57:47.83#ibcon#about to read 4, iclass 17, count 0 2006.285.23:57:47.83#ibcon#read 4, iclass 17, count 0 2006.285.23:57:47.83#ibcon#about to read 5, iclass 17, count 0 2006.285.23:57:47.83#ibcon#read 5, iclass 17, count 0 2006.285.23:57:47.83#ibcon#about to read 6, iclass 17, count 0 2006.285.23:57:47.83#ibcon#read 6, iclass 17, count 0 2006.285.23:57:47.83#ibcon#end of sib2, iclass 17, count 0 2006.285.23:57:47.83#ibcon#*mode == 0, iclass 17, count 0 2006.285.23:57:47.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.285.23:57:47.83#ibcon#[27=USB\r\n] 2006.285.23:57:47.83#ibcon#*before write, iclass 17, count 0 2006.285.23:57:47.83#ibcon#enter sib2, iclass 17, count 0 2006.285.23:57:47.83#ibcon#flushed, iclass 17, count 0 2006.285.23:57:47.83#ibcon#about to write, iclass 17, count 0 2006.285.23:57:47.83#ibcon#wrote, iclass 17, count 0 2006.285.23:57:47.83#ibcon#about to read 3, iclass 17, count 0 2006.285.23:57:47.86#ibcon#read 3, iclass 17, count 0 2006.285.23:57:47.86#ibcon#about to read 4, iclass 17, count 0 2006.285.23:57:47.86#ibcon#read 4, iclass 17, count 0 2006.285.23:57:47.86#ibcon#about to read 5, iclass 17, count 0 2006.285.23:57:47.86#ibcon#read 5, iclass 17, count 0 2006.285.23:57:47.86#ibcon#about to read 6, iclass 17, count 0 2006.285.23:57:47.86#ibcon#read 6, iclass 17, count 0 2006.285.23:57:47.86#ibcon#end of sib2, iclass 17, count 0 2006.285.23:57:47.86#ibcon#*after write, iclass 17, count 0 2006.285.23:57:47.86#ibcon#*before return 0, iclass 17, count 0 2006.285.23:57:47.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:57:47.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.285.23:57:47.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.285.23:57:47.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.285.23:57:47.86$vck44/vblo=8,744.99 2006.285.23:57:47.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.285.23:57:47.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.285.23:57:47.86#ibcon#ireg 17 cls_cnt 0 2006.285.23:57:47.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:57:47.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:57:47.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:57:47.86#ibcon#enter wrdev, iclass 19, count 0 2006.285.23:57:47.86#ibcon#first serial, iclass 19, count 0 2006.285.23:57:47.86#ibcon#enter sib2, iclass 19, count 0 2006.285.23:57:47.86#ibcon#flushed, iclass 19, count 0 2006.285.23:57:47.86#ibcon#about to write, iclass 19, count 0 2006.285.23:57:47.86#ibcon#wrote, iclass 19, count 0 2006.285.23:57:47.86#ibcon#about to read 3, iclass 19, count 0 2006.285.23:57:47.88#ibcon#read 3, iclass 19, count 0 2006.285.23:57:47.88#ibcon#about to read 4, iclass 19, count 0 2006.285.23:57:47.88#ibcon#read 4, iclass 19, count 0 2006.285.23:57:47.88#ibcon#about to read 5, iclass 19, count 0 2006.285.23:57:47.88#ibcon#read 5, iclass 19, count 0 2006.285.23:57:47.88#ibcon#about to read 6, iclass 19, count 0 2006.285.23:57:47.88#ibcon#read 6, iclass 19, count 0 2006.285.23:57:47.88#ibcon#end of sib2, iclass 19, count 0 2006.285.23:57:47.88#ibcon#*mode == 0, iclass 19, count 0 2006.285.23:57:47.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.285.23:57:47.88#ibcon#[28=FRQ=08,744.99\r\n] 2006.285.23:57:47.88#ibcon#*before write, iclass 19, count 0 2006.285.23:57:47.88#ibcon#enter sib2, iclass 19, count 0 2006.285.23:57:47.88#ibcon#flushed, iclass 19, count 0 2006.285.23:57:47.88#ibcon#about to write, iclass 19, count 0 2006.285.23:57:47.88#ibcon#wrote, iclass 19, count 0 2006.285.23:57:47.88#ibcon#about to read 3, iclass 19, count 0 2006.285.23:57:47.92#ibcon#read 3, iclass 19, count 0 2006.285.23:57:47.92#ibcon#about to read 4, iclass 19, count 0 2006.285.23:57:47.92#ibcon#read 4, iclass 19, count 0 2006.285.23:57:47.92#ibcon#about to read 5, iclass 19, count 0 2006.285.23:57:47.92#ibcon#read 5, iclass 19, count 0 2006.285.23:57:47.92#ibcon#about to read 6, iclass 19, count 0 2006.285.23:57:47.92#ibcon#read 6, iclass 19, count 0 2006.285.23:57:47.92#ibcon#end of sib2, iclass 19, count 0 2006.285.23:57:47.92#ibcon#*after write, iclass 19, count 0 2006.285.23:57:47.92#ibcon#*before return 0, iclass 19, count 0 2006.285.23:57:47.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:57:47.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.285.23:57:47.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.285.23:57:47.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.285.23:57:47.92$vck44/vb=8,4 2006.285.23:57:47.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.285.23:57:47.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.285.23:57:47.92#ibcon#ireg 11 cls_cnt 2 2006.285.23:57:47.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:57:47.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:57:47.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:57:47.98#ibcon#enter wrdev, iclass 21, count 2 2006.285.23:57:47.98#ibcon#first serial, iclass 21, count 2 2006.285.23:57:47.98#ibcon#enter sib2, iclass 21, count 2 2006.285.23:57:47.98#ibcon#flushed, iclass 21, count 2 2006.285.23:57:47.98#ibcon#about to write, iclass 21, count 2 2006.285.23:57:47.98#ibcon#wrote, iclass 21, count 2 2006.285.23:57:47.98#ibcon#about to read 3, iclass 21, count 2 2006.285.23:57:48.00#ibcon#read 3, iclass 21, count 2 2006.285.23:57:48.00#ibcon#about to read 4, iclass 21, count 2 2006.285.23:57:48.00#ibcon#read 4, iclass 21, count 2 2006.285.23:57:48.00#ibcon#about to read 5, iclass 21, count 2 2006.285.23:57:48.00#ibcon#read 5, iclass 21, count 2 2006.285.23:57:48.00#ibcon#about to read 6, iclass 21, count 2 2006.285.23:57:48.00#ibcon#read 6, iclass 21, count 2 2006.285.23:57:48.00#ibcon#end of sib2, iclass 21, count 2 2006.285.23:57:48.00#ibcon#*mode == 0, iclass 21, count 2 2006.285.23:57:48.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.285.23:57:48.00#ibcon#[27=AT08-04\r\n] 2006.285.23:57:48.00#ibcon#*before write, iclass 21, count 2 2006.285.23:57:48.00#ibcon#enter sib2, iclass 21, count 2 2006.285.23:57:48.00#ibcon#flushed, iclass 21, count 2 2006.285.23:57:48.00#ibcon#about to write, iclass 21, count 2 2006.285.23:57:48.00#ibcon#wrote, iclass 21, count 2 2006.285.23:57:48.00#ibcon#about to read 3, iclass 21, count 2 2006.285.23:57:48.03#ibcon#read 3, iclass 21, count 2 2006.285.23:57:48.03#ibcon#about to read 4, iclass 21, count 2 2006.285.23:57:48.03#ibcon#read 4, iclass 21, count 2 2006.285.23:57:48.03#ibcon#about to read 5, iclass 21, count 2 2006.285.23:57:48.03#ibcon#read 5, iclass 21, count 2 2006.285.23:57:48.03#ibcon#about to read 6, iclass 21, count 2 2006.285.23:57:48.03#ibcon#read 6, iclass 21, count 2 2006.285.23:57:48.03#ibcon#end of sib2, iclass 21, count 2 2006.285.23:57:48.03#ibcon#*after write, iclass 21, count 2 2006.285.23:57:48.03#ibcon#*before return 0, iclass 21, count 2 2006.285.23:57:48.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:57:48.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.285.23:57:48.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.285.23:57:48.03#ibcon#ireg 7 cls_cnt 0 2006.285.23:57:48.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:57:48.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:57:48.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:57:48.15#ibcon#enter wrdev, iclass 21, count 0 2006.285.23:57:48.15#ibcon#first serial, iclass 21, count 0 2006.285.23:57:48.15#ibcon#enter sib2, iclass 21, count 0 2006.285.23:57:48.15#ibcon#flushed, iclass 21, count 0 2006.285.23:57:48.15#ibcon#about to write, iclass 21, count 0 2006.285.23:57:48.15#ibcon#wrote, iclass 21, count 0 2006.285.23:57:48.15#ibcon#about to read 3, iclass 21, count 0 2006.285.23:57:48.17#ibcon#read 3, iclass 21, count 0 2006.285.23:57:48.17#ibcon#about to read 4, iclass 21, count 0 2006.285.23:57:48.17#ibcon#read 4, iclass 21, count 0 2006.285.23:57:48.17#ibcon#about to read 5, iclass 21, count 0 2006.285.23:57:48.17#ibcon#read 5, iclass 21, count 0 2006.285.23:57:48.17#ibcon#about to read 6, iclass 21, count 0 2006.285.23:57:48.17#ibcon#read 6, iclass 21, count 0 2006.285.23:57:48.17#ibcon#end of sib2, iclass 21, count 0 2006.285.23:57:48.17#ibcon#*mode == 0, iclass 21, count 0 2006.285.23:57:48.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.285.23:57:48.17#ibcon#[27=USB\r\n] 2006.285.23:57:48.17#ibcon#*before write, iclass 21, count 0 2006.285.23:57:48.17#ibcon#enter sib2, iclass 21, count 0 2006.285.23:57:48.17#ibcon#flushed, iclass 21, count 0 2006.285.23:57:48.17#ibcon#about to write, iclass 21, count 0 2006.285.23:57:48.17#ibcon#wrote, iclass 21, count 0 2006.285.23:57:48.17#ibcon#about to read 3, iclass 21, count 0 2006.285.23:57:48.20#ibcon#read 3, iclass 21, count 0 2006.285.23:57:48.20#ibcon#about to read 4, iclass 21, count 0 2006.285.23:57:48.20#ibcon#read 4, iclass 21, count 0 2006.285.23:57:48.20#ibcon#about to read 5, iclass 21, count 0 2006.285.23:57:48.20#ibcon#read 5, iclass 21, count 0 2006.285.23:57:48.20#ibcon#about to read 6, iclass 21, count 0 2006.285.23:57:48.20#ibcon#read 6, iclass 21, count 0 2006.285.23:57:48.20#ibcon#end of sib2, iclass 21, count 0 2006.285.23:57:48.20#ibcon#*after write, iclass 21, count 0 2006.285.23:57:48.20#ibcon#*before return 0, iclass 21, count 0 2006.285.23:57:48.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:57:48.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.285.23:57:48.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.285.23:57:48.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.285.23:57:48.20$vck44/vabw=wide 2006.285.23:57:48.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.285.23:57:48.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.285.23:57:48.20#ibcon#ireg 8 cls_cnt 0 2006.285.23:57:48.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:57:48.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:57:48.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:57:48.20#ibcon#enter wrdev, iclass 23, count 0 2006.285.23:57:48.20#ibcon#first serial, iclass 23, count 0 2006.285.23:57:48.20#ibcon#enter sib2, iclass 23, count 0 2006.285.23:57:48.20#ibcon#flushed, iclass 23, count 0 2006.285.23:57:48.20#ibcon#about to write, iclass 23, count 0 2006.285.23:57:48.20#ibcon#wrote, iclass 23, count 0 2006.285.23:57:48.20#ibcon#about to read 3, iclass 23, count 0 2006.285.23:57:48.22#ibcon#read 3, iclass 23, count 0 2006.285.23:57:48.22#ibcon#about to read 4, iclass 23, count 0 2006.285.23:57:48.22#ibcon#read 4, iclass 23, count 0 2006.285.23:57:48.22#ibcon#about to read 5, iclass 23, count 0 2006.285.23:57:48.22#ibcon#read 5, iclass 23, count 0 2006.285.23:57:48.22#ibcon#about to read 6, iclass 23, count 0 2006.285.23:57:48.22#ibcon#read 6, iclass 23, count 0 2006.285.23:57:48.22#ibcon#end of sib2, iclass 23, count 0 2006.285.23:57:48.22#ibcon#*mode == 0, iclass 23, count 0 2006.285.23:57:48.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.285.23:57:48.22#ibcon#[25=BW32\r\n] 2006.285.23:57:48.22#ibcon#*before write, iclass 23, count 0 2006.285.23:57:48.22#ibcon#enter sib2, iclass 23, count 0 2006.285.23:57:48.22#ibcon#flushed, iclass 23, count 0 2006.285.23:57:48.22#ibcon#about to write, iclass 23, count 0 2006.285.23:57:48.22#ibcon#wrote, iclass 23, count 0 2006.285.23:57:48.22#ibcon#about to read 3, iclass 23, count 0 2006.285.23:57:48.25#ibcon#read 3, iclass 23, count 0 2006.285.23:57:48.25#ibcon#about to read 4, iclass 23, count 0 2006.285.23:57:48.25#ibcon#read 4, iclass 23, count 0 2006.285.23:57:48.25#ibcon#about to read 5, iclass 23, count 0 2006.285.23:57:48.25#ibcon#read 5, iclass 23, count 0 2006.285.23:57:48.25#ibcon#about to read 6, iclass 23, count 0 2006.285.23:57:48.25#ibcon#read 6, iclass 23, count 0 2006.285.23:57:48.25#ibcon#end of sib2, iclass 23, count 0 2006.285.23:57:48.25#ibcon#*after write, iclass 23, count 0 2006.285.23:57:48.25#ibcon#*before return 0, iclass 23, count 0 2006.285.23:57:48.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:57:48.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.285.23:57:48.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.285.23:57:48.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.285.23:57:48.25$vck44/vbbw=wide 2006.285.23:57:48.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.285.23:57:48.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.285.23:57:48.25#ibcon#ireg 8 cls_cnt 0 2006.285.23:57:48.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:57:48.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:57:48.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:57:48.32#ibcon#enter wrdev, iclass 25, count 0 2006.285.23:57:48.32#ibcon#first serial, iclass 25, count 0 2006.285.23:57:48.32#ibcon#enter sib2, iclass 25, count 0 2006.285.23:57:48.32#ibcon#flushed, iclass 25, count 0 2006.285.23:57:48.32#ibcon#about to write, iclass 25, count 0 2006.285.23:57:48.32#ibcon#wrote, iclass 25, count 0 2006.285.23:57:48.32#ibcon#about to read 3, iclass 25, count 0 2006.285.23:57:48.34#ibcon#read 3, iclass 25, count 0 2006.285.23:57:48.34#ibcon#about to read 4, iclass 25, count 0 2006.285.23:57:48.34#ibcon#read 4, iclass 25, count 0 2006.285.23:57:48.34#ibcon#about to read 5, iclass 25, count 0 2006.285.23:57:48.34#ibcon#read 5, iclass 25, count 0 2006.285.23:57:48.34#ibcon#about to read 6, iclass 25, count 0 2006.285.23:57:48.34#ibcon#read 6, iclass 25, count 0 2006.285.23:57:48.34#ibcon#end of sib2, iclass 25, count 0 2006.285.23:57:48.34#ibcon#*mode == 0, iclass 25, count 0 2006.285.23:57:48.34#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.285.23:57:48.34#ibcon#[27=BW32\r\n] 2006.285.23:57:48.34#ibcon#*before write, iclass 25, count 0 2006.285.23:57:48.34#ibcon#enter sib2, iclass 25, count 0 2006.285.23:57:48.34#ibcon#flushed, iclass 25, count 0 2006.285.23:57:48.34#ibcon#about to write, iclass 25, count 0 2006.285.23:57:48.34#ibcon#wrote, iclass 25, count 0 2006.285.23:57:48.34#ibcon#about to read 3, iclass 25, count 0 2006.285.23:57:48.37#ibcon#read 3, iclass 25, count 0 2006.285.23:57:48.37#ibcon#about to read 4, iclass 25, count 0 2006.285.23:57:48.37#ibcon#read 4, iclass 25, count 0 2006.285.23:57:48.37#ibcon#about to read 5, iclass 25, count 0 2006.285.23:57:48.37#ibcon#read 5, iclass 25, count 0 2006.285.23:57:48.37#ibcon#about to read 6, iclass 25, count 0 2006.285.23:57:48.37#ibcon#read 6, iclass 25, count 0 2006.285.23:57:48.37#ibcon#end of sib2, iclass 25, count 0 2006.285.23:57:48.37#ibcon#*after write, iclass 25, count 0 2006.285.23:57:48.37#ibcon#*before return 0, iclass 25, count 0 2006.285.23:57:48.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:57:48.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.285.23:57:48.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.285.23:57:48.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.285.23:57:48.37$setupk4/ifdk4 2006.285.23:57:48.37$ifdk4/lo= 2006.285.23:57:48.37$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.285.23:57:48.37$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.285.23:57:48.37$ifdk4/patch= 2006.285.23:57:48.37$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.285.23:57:48.37$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.285.23:57:48.37$setupk4/!*+20s 2006.285.23:57:50.03#abcon#<5=/03 4.1 7.9 19.59 871016.5\r\n> 2006.285.23:57:50.05#abcon#{5=INTERFACE CLEAR} 2006.285.23:57:50.11#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:58:00.20#abcon#<5=/03 4.0 7.9 19.59 871016.5\r\n> 2006.285.23:58:00.22#abcon#{5=INTERFACE CLEAR} 2006.285.23:58:00.28#abcon#[5=S1D000X0/0*\r\n] 2006.285.23:58:02.88$setupk4/"tpicd 2006.285.23:58:02.88$setupk4/echo=off 2006.285.23:58:02.88$setupk4/xlog=off 2006.285.23:58:02.88:!2006.286.00:04:48 2006.285.23:58:05.14#trakl#Source acquired 2006.285.23:58:05.14#flagr#flagr/antenna,acquired 2006.286.00:00:55.14#trakl#Off source 2006.286.00:00:55.14?ERROR st -7 Antenna off-source! 2006.286.00:00:55.14#trakl#az 128.710 el 56.608 azerr*cos(el) 0.0006 elerr 0.0173 2006.286.00:00:56.14#flagr#flagr/antenna,off-source 2006.286.00:01:01.14#trakl#Source re-acquired 2006.286.00:01:02.14#flagr#flagr/antenna,re-acquired 2006.286.00:04:48.00:preob 2006.286.00:04:48.14/onsource/TRACKING 2006.286.00:04:48.14:!2006.286.00:04:58 2006.286.00:04:58.00:"tape 2006.286.00:04:58.00:"st=record 2006.286.00:04:58.00:data_valid=on 2006.286.00:04:58.00:midob 2006.286.00:04:59.14/onsource/TRACKING 2006.286.00:04:59.14/wx/19.69,1016.4,86 2006.286.00:04:59.23/cable/+6.5078E-03 2006.286.00:05:00.32/va/01,07,usb,yes,36,38 2006.286.00:05:00.32/va/02,06,usb,yes,36,35 2006.286.00:05:00.32/va/03,07,usb,yes,34,36 2006.286.00:05:00.32/va/04,06,usb,yes,36,37 2006.286.00:05:00.32/va/05,03,usb,yes,35,36 2006.286.00:05:00.32/va/06,04,usb,yes,32,31 2006.286.00:05:00.32/va/07,04,usb,yes,32,33 2006.286.00:05:00.32/va/08,03,usb,yes,33,40 2006.286.00:05:00.55/valo/01,524.99,yes,locked 2006.286.00:05:00.55/valo/02,534.99,yes,locked 2006.286.00:05:00.55/valo/03,564.99,yes,locked 2006.286.00:05:00.55/valo/04,624.99,yes,locked 2006.286.00:05:00.55/valo/05,734.99,yes,locked 2006.286.00:05:00.55/valo/06,814.99,yes,locked 2006.286.00:05:00.55/valo/07,864.99,yes,locked 2006.286.00:05:00.55/valo/08,884.99,yes,locked 2006.286.00:05:01.64/vb/01,04,usb,yes,38,35 2006.286.00:05:01.64/vb/02,05,usb,yes,36,35 2006.286.00:05:01.64/vb/03,04,usb,yes,37,40 2006.286.00:05:01.64/vb/04,05,usb,yes,37,36 2006.286.00:05:01.64/vb/05,04,usb,yes,33,36 2006.286.00:05:01.64/vb/06,03,usb,yes,46,41 2006.286.00:05:01.64/vb/07,04,usb,yes,37,38 2006.286.00:05:01.64/vb/08,04,usb,yes,34,38 2006.286.00:05:01.87/vblo/01,629.99,yes,locked 2006.286.00:05:01.87/vblo/02,634.99,yes,locked 2006.286.00:05:01.87/vblo/03,649.99,yes,locked 2006.286.00:05:01.87/vblo/04,679.99,yes,locked 2006.286.00:05:01.87/vblo/05,709.99,yes,locked 2006.286.00:05:01.87/vblo/06,719.99,yes,locked 2006.286.00:05:01.87/vblo/07,734.99,yes,locked 2006.286.00:05:01.87/vblo/08,744.99,yes,locked 2006.286.00:05:02.02/vabw/8 2006.286.00:05:02.17/vbbw/8 2006.286.00:05:02.26/xfe/off,on,12.0 2006.286.00:05:02.63/ifatt/23,28,28,28 2006.286.00:05:03.07/fmout-gps/S +2.86E-07 2006.286.00:05:03.09:!2006.286.00:06:18 2006.286.00:06:18.00:data_valid=off 2006.286.00:06:18.00:"et 2006.286.00:06:18.00:!+3s 2006.286.00:06:21.01:"tape 2006.286.00:06:21.01:postob 2006.286.00:06:21.12/cable/+6.5065E-03 2006.286.00:06:21.12/wx/19.69,1016.4,87 2006.286.00:06:22.08/fmout-gps/S +2.86E-07 2006.286.00:06:22.08:scan_name=286-0010,jd0610,290 2006.286.00:06:22.08:source=oj287,085448.87,200630.6,2000.0,cw 2006.286.00:06:23.14#flagr#flagr/antenna,new-source 2006.286.00:06:23.14:checkk5 2006.286.00:06:23.53/chk_autoobs//k5ts1/ autoobs is running! 2006.286.00:06:23.92/chk_autoobs//k5ts2/ autoobs is running! 2006.286.00:06:24.37/chk_autoobs//k5ts3/ autoobs is running! 2006.286.00:06:24.79/chk_autoobs//k5ts4/ autoobs is running! 2006.286.00:06:25.24/chk_obsdata//k5ts1/T2860004??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.286.00:06:25.57/chk_obsdata//k5ts2/T2860004??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.286.00:06:25.91/chk_obsdata//k5ts3/T2860004??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.286.00:06:26.48/chk_obsdata//k5ts4/T2860004??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.286.00:06:27.55/k5log//k5ts1_log_newline 2006.286.00:06:28.24/k5log//k5ts2_log_newline 2006.286.00:06:28.93/k5log//k5ts3_log_newline 2006.286.00:06:30.03/k5log//k5ts4_log_newline 2006.286.00:06:30.05/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.00:06:30.05:setupk4=1 2006.286.00:06:30.05$setupk4/echo=on 2006.286.00:06:30.05$setupk4/pcalon 2006.286.00:06:30.05$pcalon/"no phase cal control is implemented here 2006.286.00:06:30.05$setupk4/"tpicd=stop 2006.286.00:06:30.05$setupk4/"rec=synch_on 2006.286.00:06:30.05$setupk4/"rec_mode=128 2006.286.00:06:30.05$setupk4/!* 2006.286.00:06:30.05$setupk4/recpk4 2006.286.00:06:30.05$recpk4/recpatch= 2006.286.00:06:30.05$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.00:06:30.05$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.00:06:30.06$setupk4/vck44 2006.286.00:06:30.06$vck44/valo=1,524.99 2006.286.00:06:30.06#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.00:06:30.06#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.00:06:30.06#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:30.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:06:30.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:06:30.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:06:30.06#ibcon#enter wrdev, iclass 24, count 0 2006.286.00:06:30.06#ibcon#first serial, iclass 24, count 0 2006.286.00:06:30.06#ibcon#enter sib2, iclass 24, count 0 2006.286.00:06:30.06#ibcon#flushed, iclass 24, count 0 2006.286.00:06:30.06#ibcon#about to write, iclass 24, count 0 2006.286.00:06:30.06#ibcon#wrote, iclass 24, count 0 2006.286.00:06:30.06#ibcon#about to read 3, iclass 24, count 0 2006.286.00:06:30.07#ibcon#read 3, iclass 24, count 0 2006.286.00:06:30.07#ibcon#about to read 4, iclass 24, count 0 2006.286.00:06:30.07#ibcon#read 4, iclass 24, count 0 2006.286.00:06:30.07#ibcon#about to read 5, iclass 24, count 0 2006.286.00:06:30.07#ibcon#read 5, iclass 24, count 0 2006.286.00:06:30.07#ibcon#about to read 6, iclass 24, count 0 2006.286.00:06:30.07#ibcon#read 6, iclass 24, count 0 2006.286.00:06:30.07#ibcon#end of sib2, iclass 24, count 0 2006.286.00:06:30.07#ibcon#*mode == 0, iclass 24, count 0 2006.286.00:06:30.07#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.00:06:30.07#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.00:06:30.07#ibcon#*before write, iclass 24, count 0 2006.286.00:06:30.07#ibcon#enter sib2, iclass 24, count 0 2006.286.00:06:30.07#ibcon#flushed, iclass 24, count 0 2006.286.00:06:30.07#ibcon#about to write, iclass 24, count 0 2006.286.00:06:30.07#ibcon#wrote, iclass 24, count 0 2006.286.00:06:30.07#ibcon#about to read 3, iclass 24, count 0 2006.286.00:06:30.12#ibcon#read 3, iclass 24, count 0 2006.286.00:06:30.12#ibcon#about to read 4, iclass 24, count 0 2006.286.00:06:30.12#ibcon#read 4, iclass 24, count 0 2006.286.00:06:30.12#ibcon#about to read 5, iclass 24, count 0 2006.286.00:06:30.12#ibcon#read 5, iclass 24, count 0 2006.286.00:06:30.12#ibcon#about to read 6, iclass 24, count 0 2006.286.00:06:30.12#ibcon#read 6, iclass 24, count 0 2006.286.00:06:30.12#ibcon#end of sib2, iclass 24, count 0 2006.286.00:06:30.12#ibcon#*after write, iclass 24, count 0 2006.286.00:06:30.12#ibcon#*before return 0, iclass 24, count 0 2006.286.00:06:30.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:06:30.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:06:30.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.00:06:30.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.00:06:30.12$vck44/va=1,7 2006.286.00:06:30.12#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.00:06:30.12#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.00:06:30.12#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:30.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:06:30.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:06:30.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:06:30.12#ibcon#enter wrdev, iclass 26, count 2 2006.286.00:06:30.12#ibcon#first serial, iclass 26, count 2 2006.286.00:06:30.12#ibcon#enter sib2, iclass 26, count 2 2006.286.00:06:30.12#ibcon#flushed, iclass 26, count 2 2006.286.00:06:30.12#ibcon#about to write, iclass 26, count 2 2006.286.00:06:30.12#ibcon#wrote, iclass 26, count 2 2006.286.00:06:30.12#ibcon#about to read 3, iclass 26, count 2 2006.286.00:06:30.14#ibcon#read 3, iclass 26, count 2 2006.286.00:06:30.14#ibcon#about to read 4, iclass 26, count 2 2006.286.00:06:30.14#ibcon#read 4, iclass 26, count 2 2006.286.00:06:30.14#ibcon#about to read 5, iclass 26, count 2 2006.286.00:06:30.14#ibcon#read 5, iclass 26, count 2 2006.286.00:06:30.14#ibcon#about to read 6, iclass 26, count 2 2006.286.00:06:30.14#ibcon#read 6, iclass 26, count 2 2006.286.00:06:30.14#ibcon#end of sib2, iclass 26, count 2 2006.286.00:06:30.14#ibcon#*mode == 0, iclass 26, count 2 2006.286.00:06:30.14#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.00:06:30.14#ibcon#[25=AT01-07\r\n] 2006.286.00:06:30.14#ibcon#*before write, iclass 26, count 2 2006.286.00:06:30.14#ibcon#enter sib2, iclass 26, count 2 2006.286.00:06:30.14#ibcon#flushed, iclass 26, count 2 2006.286.00:06:30.14#ibcon#about to write, iclass 26, count 2 2006.286.00:06:30.14#ibcon#wrote, iclass 26, count 2 2006.286.00:06:30.14#ibcon#about to read 3, iclass 26, count 2 2006.286.00:06:30.17#ibcon#read 3, iclass 26, count 2 2006.286.00:06:30.17#ibcon#about to read 4, iclass 26, count 2 2006.286.00:06:30.17#ibcon#read 4, iclass 26, count 2 2006.286.00:06:30.17#ibcon#about to read 5, iclass 26, count 2 2006.286.00:06:30.17#ibcon#read 5, iclass 26, count 2 2006.286.00:06:30.17#ibcon#about to read 6, iclass 26, count 2 2006.286.00:06:30.17#ibcon#read 6, iclass 26, count 2 2006.286.00:06:30.17#ibcon#end of sib2, iclass 26, count 2 2006.286.00:06:30.17#ibcon#*after write, iclass 26, count 2 2006.286.00:06:30.17#ibcon#*before return 0, iclass 26, count 2 2006.286.00:06:30.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:06:30.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:06:30.17#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.00:06:30.17#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:30.17#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:06:30.29#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:06:30.29#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:06:30.29#ibcon#enter wrdev, iclass 26, count 0 2006.286.00:06:30.29#ibcon#first serial, iclass 26, count 0 2006.286.00:06:30.29#ibcon#enter sib2, iclass 26, count 0 2006.286.00:06:30.29#ibcon#flushed, iclass 26, count 0 2006.286.00:06:30.29#ibcon#about to write, iclass 26, count 0 2006.286.00:06:30.29#ibcon#wrote, iclass 26, count 0 2006.286.00:06:30.29#ibcon#about to read 3, iclass 26, count 0 2006.286.00:06:30.31#ibcon#read 3, iclass 26, count 0 2006.286.00:06:30.31#ibcon#about to read 4, iclass 26, count 0 2006.286.00:06:30.31#ibcon#read 4, iclass 26, count 0 2006.286.00:06:30.31#ibcon#about to read 5, iclass 26, count 0 2006.286.00:06:30.31#ibcon#read 5, iclass 26, count 0 2006.286.00:06:30.31#ibcon#about to read 6, iclass 26, count 0 2006.286.00:06:30.31#ibcon#read 6, iclass 26, count 0 2006.286.00:06:30.31#ibcon#end of sib2, iclass 26, count 0 2006.286.00:06:30.31#ibcon#*mode == 0, iclass 26, count 0 2006.286.00:06:30.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.00:06:30.31#ibcon#[25=USB\r\n] 2006.286.00:06:30.31#ibcon#*before write, iclass 26, count 0 2006.286.00:06:30.31#ibcon#enter sib2, iclass 26, count 0 2006.286.00:06:30.31#ibcon#flushed, iclass 26, count 0 2006.286.00:06:30.31#ibcon#about to write, iclass 26, count 0 2006.286.00:06:30.31#ibcon#wrote, iclass 26, count 0 2006.286.00:06:30.31#ibcon#about to read 3, iclass 26, count 0 2006.286.00:06:30.34#ibcon#read 3, iclass 26, count 0 2006.286.00:06:30.34#ibcon#about to read 4, iclass 26, count 0 2006.286.00:06:30.34#ibcon#read 4, iclass 26, count 0 2006.286.00:06:30.34#ibcon#about to read 5, iclass 26, count 0 2006.286.00:06:30.34#ibcon#read 5, iclass 26, count 0 2006.286.00:06:30.34#ibcon#about to read 6, iclass 26, count 0 2006.286.00:06:30.34#ibcon#read 6, iclass 26, count 0 2006.286.00:06:30.34#ibcon#end of sib2, iclass 26, count 0 2006.286.00:06:30.34#ibcon#*after write, iclass 26, count 0 2006.286.00:06:30.34#ibcon#*before return 0, iclass 26, count 0 2006.286.00:06:30.34#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:06:30.34#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:06:30.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.00:06:30.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.00:06:30.34$vck44/valo=2,534.99 2006.286.00:06:30.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.00:06:30.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.00:06:30.34#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:30.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:06:30.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:06:30.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:06:30.34#ibcon#enter wrdev, iclass 28, count 0 2006.286.00:06:30.34#ibcon#first serial, iclass 28, count 0 2006.286.00:06:30.34#ibcon#enter sib2, iclass 28, count 0 2006.286.00:06:30.34#ibcon#flushed, iclass 28, count 0 2006.286.00:06:30.34#ibcon#about to write, iclass 28, count 0 2006.286.00:06:30.34#ibcon#wrote, iclass 28, count 0 2006.286.00:06:30.34#ibcon#about to read 3, iclass 28, count 0 2006.286.00:06:30.36#ibcon#read 3, iclass 28, count 0 2006.286.00:06:30.36#ibcon#about to read 4, iclass 28, count 0 2006.286.00:06:30.36#ibcon#read 4, iclass 28, count 0 2006.286.00:06:30.36#ibcon#about to read 5, iclass 28, count 0 2006.286.00:06:30.36#ibcon#read 5, iclass 28, count 0 2006.286.00:06:30.36#ibcon#about to read 6, iclass 28, count 0 2006.286.00:06:30.36#ibcon#read 6, iclass 28, count 0 2006.286.00:06:30.36#ibcon#end of sib2, iclass 28, count 0 2006.286.00:06:30.36#ibcon#*mode == 0, iclass 28, count 0 2006.286.00:06:30.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.00:06:30.36#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.00:06:30.36#ibcon#*before write, iclass 28, count 0 2006.286.00:06:30.36#ibcon#enter sib2, iclass 28, count 0 2006.286.00:06:30.36#ibcon#flushed, iclass 28, count 0 2006.286.00:06:30.36#ibcon#about to write, iclass 28, count 0 2006.286.00:06:30.36#ibcon#wrote, iclass 28, count 0 2006.286.00:06:30.36#ibcon#about to read 3, iclass 28, count 0 2006.286.00:06:30.40#ibcon#read 3, iclass 28, count 0 2006.286.00:06:30.40#ibcon#about to read 4, iclass 28, count 0 2006.286.00:06:30.40#ibcon#read 4, iclass 28, count 0 2006.286.00:06:30.40#ibcon#about to read 5, iclass 28, count 0 2006.286.00:06:30.40#ibcon#read 5, iclass 28, count 0 2006.286.00:06:30.40#ibcon#about to read 6, iclass 28, count 0 2006.286.00:06:30.40#ibcon#read 6, iclass 28, count 0 2006.286.00:06:30.40#ibcon#end of sib2, iclass 28, count 0 2006.286.00:06:30.40#ibcon#*after write, iclass 28, count 0 2006.286.00:06:30.40#ibcon#*before return 0, iclass 28, count 0 2006.286.00:06:30.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:06:30.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:06:30.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.00:06:30.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.00:06:30.40$vck44/va=2,6 2006.286.00:06:30.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.00:06:30.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.00:06:30.40#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:30.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:06:30.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:06:30.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:06:30.46#ibcon#enter wrdev, iclass 30, count 2 2006.286.00:06:30.46#ibcon#first serial, iclass 30, count 2 2006.286.00:06:30.46#ibcon#enter sib2, iclass 30, count 2 2006.286.00:06:30.46#ibcon#flushed, iclass 30, count 2 2006.286.00:06:30.46#ibcon#about to write, iclass 30, count 2 2006.286.00:06:30.46#ibcon#wrote, iclass 30, count 2 2006.286.00:06:30.46#ibcon#about to read 3, iclass 30, count 2 2006.286.00:06:30.48#ibcon#read 3, iclass 30, count 2 2006.286.00:06:30.48#ibcon#about to read 4, iclass 30, count 2 2006.286.00:06:30.48#ibcon#read 4, iclass 30, count 2 2006.286.00:06:30.48#ibcon#about to read 5, iclass 30, count 2 2006.286.00:06:30.48#ibcon#read 5, iclass 30, count 2 2006.286.00:06:30.48#ibcon#about to read 6, iclass 30, count 2 2006.286.00:06:30.48#ibcon#read 6, iclass 30, count 2 2006.286.00:06:30.48#ibcon#end of sib2, iclass 30, count 2 2006.286.00:06:30.48#ibcon#*mode == 0, iclass 30, count 2 2006.286.00:06:30.48#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.00:06:30.48#ibcon#[25=AT02-06\r\n] 2006.286.00:06:30.48#ibcon#*before write, iclass 30, count 2 2006.286.00:06:30.48#ibcon#enter sib2, iclass 30, count 2 2006.286.00:06:30.48#ibcon#flushed, iclass 30, count 2 2006.286.00:06:30.48#ibcon#about to write, iclass 30, count 2 2006.286.00:06:30.48#ibcon#wrote, iclass 30, count 2 2006.286.00:06:30.48#ibcon#about to read 3, iclass 30, count 2 2006.286.00:06:30.51#ibcon#read 3, iclass 30, count 2 2006.286.00:06:30.51#ibcon#about to read 4, iclass 30, count 2 2006.286.00:06:30.51#ibcon#read 4, iclass 30, count 2 2006.286.00:06:30.51#ibcon#about to read 5, iclass 30, count 2 2006.286.00:06:30.51#ibcon#read 5, iclass 30, count 2 2006.286.00:06:30.51#ibcon#about to read 6, iclass 30, count 2 2006.286.00:06:30.51#ibcon#read 6, iclass 30, count 2 2006.286.00:06:30.51#ibcon#end of sib2, iclass 30, count 2 2006.286.00:06:30.51#ibcon#*after write, iclass 30, count 2 2006.286.00:06:30.51#ibcon#*before return 0, iclass 30, count 2 2006.286.00:06:30.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:06:30.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:06:30.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.00:06:30.51#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:30.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:06:30.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:06:30.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:06:30.63#ibcon#enter wrdev, iclass 30, count 0 2006.286.00:06:30.63#ibcon#first serial, iclass 30, count 0 2006.286.00:06:30.63#ibcon#enter sib2, iclass 30, count 0 2006.286.00:06:30.63#ibcon#flushed, iclass 30, count 0 2006.286.00:06:30.63#ibcon#about to write, iclass 30, count 0 2006.286.00:06:30.63#ibcon#wrote, iclass 30, count 0 2006.286.00:06:30.63#ibcon#about to read 3, iclass 30, count 0 2006.286.00:06:30.65#ibcon#read 3, iclass 30, count 0 2006.286.00:06:30.65#ibcon#about to read 4, iclass 30, count 0 2006.286.00:06:30.65#ibcon#read 4, iclass 30, count 0 2006.286.00:06:30.65#ibcon#about to read 5, iclass 30, count 0 2006.286.00:06:30.65#ibcon#read 5, iclass 30, count 0 2006.286.00:06:30.65#ibcon#about to read 6, iclass 30, count 0 2006.286.00:06:30.65#ibcon#read 6, iclass 30, count 0 2006.286.00:06:30.65#ibcon#end of sib2, iclass 30, count 0 2006.286.00:06:30.65#ibcon#*mode == 0, iclass 30, count 0 2006.286.00:06:30.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.00:06:30.65#ibcon#[25=USB\r\n] 2006.286.00:06:30.65#ibcon#*before write, iclass 30, count 0 2006.286.00:06:30.65#ibcon#enter sib2, iclass 30, count 0 2006.286.00:06:30.65#ibcon#flushed, iclass 30, count 0 2006.286.00:06:30.65#ibcon#about to write, iclass 30, count 0 2006.286.00:06:30.65#ibcon#wrote, iclass 30, count 0 2006.286.00:06:30.65#ibcon#about to read 3, iclass 30, count 0 2006.286.00:06:30.68#ibcon#read 3, iclass 30, count 0 2006.286.00:06:30.68#ibcon#about to read 4, iclass 30, count 0 2006.286.00:06:30.68#ibcon#read 4, iclass 30, count 0 2006.286.00:06:30.68#ibcon#about to read 5, iclass 30, count 0 2006.286.00:06:30.68#ibcon#read 5, iclass 30, count 0 2006.286.00:06:30.68#ibcon#about to read 6, iclass 30, count 0 2006.286.00:06:30.68#ibcon#read 6, iclass 30, count 0 2006.286.00:06:30.68#ibcon#end of sib2, iclass 30, count 0 2006.286.00:06:30.68#ibcon#*after write, iclass 30, count 0 2006.286.00:06:30.68#ibcon#*before return 0, iclass 30, count 0 2006.286.00:06:30.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:06:30.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:06:30.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.00:06:30.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.00:06:30.68$vck44/valo=3,564.99 2006.286.00:06:30.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.00:06:30.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.00:06:30.68#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:30.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:06:30.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:06:30.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:06:30.68#ibcon#enter wrdev, iclass 32, count 0 2006.286.00:06:30.68#ibcon#first serial, iclass 32, count 0 2006.286.00:06:30.68#ibcon#enter sib2, iclass 32, count 0 2006.286.00:06:30.68#ibcon#flushed, iclass 32, count 0 2006.286.00:06:30.68#ibcon#about to write, iclass 32, count 0 2006.286.00:06:30.68#ibcon#wrote, iclass 32, count 0 2006.286.00:06:30.68#ibcon#about to read 3, iclass 32, count 0 2006.286.00:06:30.70#ibcon#read 3, iclass 32, count 0 2006.286.00:06:30.70#ibcon#about to read 4, iclass 32, count 0 2006.286.00:06:30.70#ibcon#read 4, iclass 32, count 0 2006.286.00:06:30.70#ibcon#about to read 5, iclass 32, count 0 2006.286.00:06:30.70#ibcon#read 5, iclass 32, count 0 2006.286.00:06:30.70#ibcon#about to read 6, iclass 32, count 0 2006.286.00:06:30.70#ibcon#read 6, iclass 32, count 0 2006.286.00:06:30.70#ibcon#end of sib2, iclass 32, count 0 2006.286.00:06:30.70#ibcon#*mode == 0, iclass 32, count 0 2006.286.00:06:30.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.00:06:30.70#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.00:06:30.70#ibcon#*before write, iclass 32, count 0 2006.286.00:06:30.70#ibcon#enter sib2, iclass 32, count 0 2006.286.00:06:30.70#ibcon#flushed, iclass 32, count 0 2006.286.00:06:30.70#ibcon#about to write, iclass 32, count 0 2006.286.00:06:30.70#ibcon#wrote, iclass 32, count 0 2006.286.00:06:30.70#ibcon#about to read 3, iclass 32, count 0 2006.286.00:06:30.74#ibcon#read 3, iclass 32, count 0 2006.286.00:06:30.74#ibcon#about to read 4, iclass 32, count 0 2006.286.00:06:30.74#ibcon#read 4, iclass 32, count 0 2006.286.00:06:30.74#ibcon#about to read 5, iclass 32, count 0 2006.286.00:06:30.74#ibcon#read 5, iclass 32, count 0 2006.286.00:06:30.74#ibcon#about to read 6, iclass 32, count 0 2006.286.00:06:30.74#ibcon#read 6, iclass 32, count 0 2006.286.00:06:30.74#ibcon#end of sib2, iclass 32, count 0 2006.286.00:06:30.74#ibcon#*after write, iclass 32, count 0 2006.286.00:06:30.74#ibcon#*before return 0, iclass 32, count 0 2006.286.00:06:30.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:06:30.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:06:30.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.00:06:30.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.00:06:30.74$vck44/va=3,7 2006.286.00:06:30.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.00:06:30.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.00:06:30.74#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:30.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:06:30.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:06:30.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:06:30.80#ibcon#enter wrdev, iclass 34, count 2 2006.286.00:06:30.80#ibcon#first serial, iclass 34, count 2 2006.286.00:06:30.80#ibcon#enter sib2, iclass 34, count 2 2006.286.00:06:30.80#ibcon#flushed, iclass 34, count 2 2006.286.00:06:30.80#ibcon#about to write, iclass 34, count 2 2006.286.00:06:30.80#ibcon#wrote, iclass 34, count 2 2006.286.00:06:30.80#ibcon#about to read 3, iclass 34, count 2 2006.286.00:06:30.82#ibcon#read 3, iclass 34, count 2 2006.286.00:06:30.82#ibcon#about to read 4, iclass 34, count 2 2006.286.00:06:30.82#ibcon#read 4, iclass 34, count 2 2006.286.00:06:30.82#ibcon#about to read 5, iclass 34, count 2 2006.286.00:06:30.82#ibcon#read 5, iclass 34, count 2 2006.286.00:06:30.82#ibcon#about to read 6, iclass 34, count 2 2006.286.00:06:30.82#ibcon#read 6, iclass 34, count 2 2006.286.00:06:30.82#ibcon#end of sib2, iclass 34, count 2 2006.286.00:06:30.82#ibcon#*mode == 0, iclass 34, count 2 2006.286.00:06:30.82#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.00:06:30.82#ibcon#[25=AT03-07\r\n] 2006.286.00:06:30.82#ibcon#*before write, iclass 34, count 2 2006.286.00:06:30.82#ibcon#enter sib2, iclass 34, count 2 2006.286.00:06:30.82#ibcon#flushed, iclass 34, count 2 2006.286.00:06:30.82#ibcon#about to write, iclass 34, count 2 2006.286.00:06:30.82#ibcon#wrote, iclass 34, count 2 2006.286.00:06:30.82#ibcon#about to read 3, iclass 34, count 2 2006.286.00:06:30.85#ibcon#read 3, iclass 34, count 2 2006.286.00:06:30.85#ibcon#about to read 4, iclass 34, count 2 2006.286.00:06:30.85#ibcon#read 4, iclass 34, count 2 2006.286.00:06:30.85#ibcon#about to read 5, iclass 34, count 2 2006.286.00:06:30.85#ibcon#read 5, iclass 34, count 2 2006.286.00:06:30.85#ibcon#about to read 6, iclass 34, count 2 2006.286.00:06:30.85#ibcon#read 6, iclass 34, count 2 2006.286.00:06:30.85#ibcon#end of sib2, iclass 34, count 2 2006.286.00:06:30.85#ibcon#*after write, iclass 34, count 2 2006.286.00:06:30.85#ibcon#*before return 0, iclass 34, count 2 2006.286.00:06:30.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:06:30.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:06:30.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.00:06:30.85#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:30.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:06:30.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:06:30.97#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:06:30.97#ibcon#enter wrdev, iclass 34, count 0 2006.286.00:06:30.97#ibcon#first serial, iclass 34, count 0 2006.286.00:06:30.97#ibcon#enter sib2, iclass 34, count 0 2006.286.00:06:30.97#ibcon#flushed, iclass 34, count 0 2006.286.00:06:30.97#ibcon#about to write, iclass 34, count 0 2006.286.00:06:30.97#ibcon#wrote, iclass 34, count 0 2006.286.00:06:30.97#ibcon#about to read 3, iclass 34, count 0 2006.286.00:06:30.99#ibcon#read 3, iclass 34, count 0 2006.286.00:06:30.99#ibcon#about to read 4, iclass 34, count 0 2006.286.00:06:30.99#ibcon#read 4, iclass 34, count 0 2006.286.00:06:30.99#ibcon#about to read 5, iclass 34, count 0 2006.286.00:06:30.99#ibcon#read 5, iclass 34, count 0 2006.286.00:06:30.99#ibcon#about to read 6, iclass 34, count 0 2006.286.00:06:30.99#ibcon#read 6, iclass 34, count 0 2006.286.00:06:30.99#ibcon#end of sib2, iclass 34, count 0 2006.286.00:06:30.99#ibcon#*mode == 0, iclass 34, count 0 2006.286.00:06:30.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.00:06:30.99#ibcon#[25=USB\r\n] 2006.286.00:06:30.99#ibcon#*before write, iclass 34, count 0 2006.286.00:06:30.99#ibcon#enter sib2, iclass 34, count 0 2006.286.00:06:30.99#ibcon#flushed, iclass 34, count 0 2006.286.00:06:30.99#ibcon#about to write, iclass 34, count 0 2006.286.00:06:30.99#ibcon#wrote, iclass 34, count 0 2006.286.00:06:30.99#ibcon#about to read 3, iclass 34, count 0 2006.286.00:06:31.02#ibcon#read 3, iclass 34, count 0 2006.286.00:06:31.02#ibcon#about to read 4, iclass 34, count 0 2006.286.00:06:31.02#ibcon#read 4, iclass 34, count 0 2006.286.00:06:31.02#ibcon#about to read 5, iclass 34, count 0 2006.286.00:06:31.02#ibcon#read 5, iclass 34, count 0 2006.286.00:06:31.02#ibcon#about to read 6, iclass 34, count 0 2006.286.00:06:31.02#ibcon#read 6, iclass 34, count 0 2006.286.00:06:31.02#ibcon#end of sib2, iclass 34, count 0 2006.286.00:06:31.02#ibcon#*after write, iclass 34, count 0 2006.286.00:06:31.02#ibcon#*before return 0, iclass 34, count 0 2006.286.00:06:31.02#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:06:31.02#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:06:31.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.00:06:31.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.00:06:31.02$vck44/valo=4,624.99 2006.286.00:06:31.02#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.00:06:31.02#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.00:06:31.02#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:31.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:06:31.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:06:31.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:06:31.02#ibcon#enter wrdev, iclass 36, count 0 2006.286.00:06:31.02#ibcon#first serial, iclass 36, count 0 2006.286.00:06:31.02#ibcon#enter sib2, iclass 36, count 0 2006.286.00:06:31.02#ibcon#flushed, iclass 36, count 0 2006.286.00:06:31.02#ibcon#about to write, iclass 36, count 0 2006.286.00:06:31.02#ibcon#wrote, iclass 36, count 0 2006.286.00:06:31.02#ibcon#about to read 3, iclass 36, count 0 2006.286.00:06:31.04#ibcon#read 3, iclass 36, count 0 2006.286.00:06:31.04#ibcon#about to read 4, iclass 36, count 0 2006.286.00:06:31.04#ibcon#read 4, iclass 36, count 0 2006.286.00:06:31.04#ibcon#about to read 5, iclass 36, count 0 2006.286.00:06:31.04#ibcon#read 5, iclass 36, count 0 2006.286.00:06:31.04#ibcon#about to read 6, iclass 36, count 0 2006.286.00:06:31.04#ibcon#read 6, iclass 36, count 0 2006.286.00:06:31.04#ibcon#end of sib2, iclass 36, count 0 2006.286.00:06:31.04#ibcon#*mode == 0, iclass 36, count 0 2006.286.00:06:31.04#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.00:06:31.04#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.00:06:31.04#ibcon#*before write, iclass 36, count 0 2006.286.00:06:31.04#ibcon#enter sib2, iclass 36, count 0 2006.286.00:06:31.04#ibcon#flushed, iclass 36, count 0 2006.286.00:06:31.04#ibcon#about to write, iclass 36, count 0 2006.286.00:06:31.04#ibcon#wrote, iclass 36, count 0 2006.286.00:06:31.04#ibcon#about to read 3, iclass 36, count 0 2006.286.00:06:31.08#ibcon#read 3, iclass 36, count 0 2006.286.00:06:31.08#ibcon#about to read 4, iclass 36, count 0 2006.286.00:06:31.08#ibcon#read 4, iclass 36, count 0 2006.286.00:06:31.08#ibcon#about to read 5, iclass 36, count 0 2006.286.00:06:31.08#ibcon#read 5, iclass 36, count 0 2006.286.00:06:31.08#ibcon#about to read 6, iclass 36, count 0 2006.286.00:06:31.08#ibcon#read 6, iclass 36, count 0 2006.286.00:06:31.08#ibcon#end of sib2, iclass 36, count 0 2006.286.00:06:31.08#ibcon#*after write, iclass 36, count 0 2006.286.00:06:31.08#ibcon#*before return 0, iclass 36, count 0 2006.286.00:06:31.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:06:31.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:06:31.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.00:06:31.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.00:06:31.08$vck44/va=4,6 2006.286.00:06:31.08#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.00:06:31.08#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.00:06:31.08#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:31.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:06:31.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:06:31.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:06:31.14#ibcon#enter wrdev, iclass 38, count 2 2006.286.00:06:31.14#ibcon#first serial, iclass 38, count 2 2006.286.00:06:31.14#ibcon#enter sib2, iclass 38, count 2 2006.286.00:06:31.14#ibcon#flushed, iclass 38, count 2 2006.286.00:06:31.14#ibcon#about to write, iclass 38, count 2 2006.286.00:06:31.14#ibcon#wrote, iclass 38, count 2 2006.286.00:06:31.14#ibcon#about to read 3, iclass 38, count 2 2006.286.00:06:31.16#ibcon#read 3, iclass 38, count 2 2006.286.00:06:31.16#ibcon#about to read 4, iclass 38, count 2 2006.286.00:06:31.16#ibcon#read 4, iclass 38, count 2 2006.286.00:06:31.16#ibcon#about to read 5, iclass 38, count 2 2006.286.00:06:31.16#ibcon#read 5, iclass 38, count 2 2006.286.00:06:31.16#ibcon#about to read 6, iclass 38, count 2 2006.286.00:06:31.16#ibcon#read 6, iclass 38, count 2 2006.286.00:06:31.16#ibcon#end of sib2, iclass 38, count 2 2006.286.00:06:31.16#ibcon#*mode == 0, iclass 38, count 2 2006.286.00:06:31.16#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.00:06:31.16#ibcon#[25=AT04-06\r\n] 2006.286.00:06:31.16#ibcon#*before write, iclass 38, count 2 2006.286.00:06:31.16#ibcon#enter sib2, iclass 38, count 2 2006.286.00:06:31.16#ibcon#flushed, iclass 38, count 2 2006.286.00:06:31.16#ibcon#about to write, iclass 38, count 2 2006.286.00:06:31.16#ibcon#wrote, iclass 38, count 2 2006.286.00:06:31.16#ibcon#about to read 3, iclass 38, count 2 2006.286.00:06:31.19#ibcon#read 3, iclass 38, count 2 2006.286.00:06:31.19#ibcon#about to read 4, iclass 38, count 2 2006.286.00:06:31.19#ibcon#read 4, iclass 38, count 2 2006.286.00:06:31.19#ibcon#about to read 5, iclass 38, count 2 2006.286.00:06:31.19#ibcon#read 5, iclass 38, count 2 2006.286.00:06:31.19#ibcon#about to read 6, iclass 38, count 2 2006.286.00:06:31.19#ibcon#read 6, iclass 38, count 2 2006.286.00:06:31.19#ibcon#end of sib2, iclass 38, count 2 2006.286.00:06:31.19#ibcon#*after write, iclass 38, count 2 2006.286.00:06:31.19#ibcon#*before return 0, iclass 38, count 2 2006.286.00:06:31.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:06:31.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:06:31.19#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.00:06:31.19#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:31.19#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:06:31.31#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:06:31.31#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:06:31.31#ibcon#enter wrdev, iclass 38, count 0 2006.286.00:06:31.31#ibcon#first serial, iclass 38, count 0 2006.286.00:06:31.31#ibcon#enter sib2, iclass 38, count 0 2006.286.00:06:31.31#ibcon#flushed, iclass 38, count 0 2006.286.00:06:31.31#ibcon#about to write, iclass 38, count 0 2006.286.00:06:31.31#ibcon#wrote, iclass 38, count 0 2006.286.00:06:31.31#ibcon#about to read 3, iclass 38, count 0 2006.286.00:06:31.33#ibcon#read 3, iclass 38, count 0 2006.286.00:06:31.33#ibcon#about to read 4, iclass 38, count 0 2006.286.00:06:31.33#ibcon#read 4, iclass 38, count 0 2006.286.00:06:31.33#ibcon#about to read 5, iclass 38, count 0 2006.286.00:06:31.33#ibcon#read 5, iclass 38, count 0 2006.286.00:06:31.33#ibcon#about to read 6, iclass 38, count 0 2006.286.00:06:31.33#ibcon#read 6, iclass 38, count 0 2006.286.00:06:31.33#ibcon#end of sib2, iclass 38, count 0 2006.286.00:06:31.33#ibcon#*mode == 0, iclass 38, count 0 2006.286.00:06:31.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.00:06:31.33#ibcon#[25=USB\r\n] 2006.286.00:06:31.33#ibcon#*before write, iclass 38, count 0 2006.286.00:06:31.33#ibcon#enter sib2, iclass 38, count 0 2006.286.00:06:31.33#ibcon#flushed, iclass 38, count 0 2006.286.00:06:31.33#ibcon#about to write, iclass 38, count 0 2006.286.00:06:31.33#ibcon#wrote, iclass 38, count 0 2006.286.00:06:31.33#ibcon#about to read 3, iclass 38, count 0 2006.286.00:06:31.36#ibcon#read 3, iclass 38, count 0 2006.286.00:06:31.36#ibcon#about to read 4, iclass 38, count 0 2006.286.00:06:31.36#ibcon#read 4, iclass 38, count 0 2006.286.00:06:31.36#ibcon#about to read 5, iclass 38, count 0 2006.286.00:06:31.36#ibcon#read 5, iclass 38, count 0 2006.286.00:06:31.36#ibcon#about to read 6, iclass 38, count 0 2006.286.00:06:31.36#ibcon#read 6, iclass 38, count 0 2006.286.00:06:31.36#ibcon#end of sib2, iclass 38, count 0 2006.286.00:06:31.36#ibcon#*after write, iclass 38, count 0 2006.286.00:06:31.36#ibcon#*before return 0, iclass 38, count 0 2006.286.00:06:31.36#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:06:31.36#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:06:31.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.00:06:31.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.00:06:31.36$vck44/valo=5,734.99 2006.286.00:06:31.36#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.00:06:31.36#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.00:06:31.36#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:31.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:06:31.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:06:31.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:06:31.36#ibcon#enter wrdev, iclass 40, count 0 2006.286.00:06:31.36#ibcon#first serial, iclass 40, count 0 2006.286.00:06:31.36#ibcon#enter sib2, iclass 40, count 0 2006.286.00:06:31.36#ibcon#flushed, iclass 40, count 0 2006.286.00:06:31.36#ibcon#about to write, iclass 40, count 0 2006.286.00:06:31.36#ibcon#wrote, iclass 40, count 0 2006.286.00:06:31.36#ibcon#about to read 3, iclass 40, count 0 2006.286.00:06:31.38#ibcon#read 3, iclass 40, count 0 2006.286.00:06:31.38#ibcon#about to read 4, iclass 40, count 0 2006.286.00:06:31.38#ibcon#read 4, iclass 40, count 0 2006.286.00:06:31.38#ibcon#about to read 5, iclass 40, count 0 2006.286.00:06:31.38#ibcon#read 5, iclass 40, count 0 2006.286.00:06:31.38#ibcon#about to read 6, iclass 40, count 0 2006.286.00:06:31.38#ibcon#read 6, iclass 40, count 0 2006.286.00:06:31.38#ibcon#end of sib2, iclass 40, count 0 2006.286.00:06:31.38#ibcon#*mode == 0, iclass 40, count 0 2006.286.00:06:31.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.00:06:31.38#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.00:06:31.38#ibcon#*before write, iclass 40, count 0 2006.286.00:06:31.38#ibcon#enter sib2, iclass 40, count 0 2006.286.00:06:31.38#ibcon#flushed, iclass 40, count 0 2006.286.00:06:31.38#ibcon#about to write, iclass 40, count 0 2006.286.00:06:31.38#ibcon#wrote, iclass 40, count 0 2006.286.00:06:31.38#ibcon#about to read 3, iclass 40, count 0 2006.286.00:06:31.42#ibcon#read 3, iclass 40, count 0 2006.286.00:06:31.42#ibcon#about to read 4, iclass 40, count 0 2006.286.00:06:31.42#ibcon#read 4, iclass 40, count 0 2006.286.00:06:31.42#ibcon#about to read 5, iclass 40, count 0 2006.286.00:06:31.42#ibcon#read 5, iclass 40, count 0 2006.286.00:06:31.42#ibcon#about to read 6, iclass 40, count 0 2006.286.00:06:31.42#ibcon#read 6, iclass 40, count 0 2006.286.00:06:31.42#ibcon#end of sib2, iclass 40, count 0 2006.286.00:06:31.42#ibcon#*after write, iclass 40, count 0 2006.286.00:06:31.42#ibcon#*before return 0, iclass 40, count 0 2006.286.00:06:31.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:06:31.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:06:31.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.00:06:31.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.00:06:31.42$vck44/va=5,3 2006.286.00:06:31.42#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.00:06:31.42#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.00:06:31.42#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:31.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:06:31.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:06:31.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:06:31.48#ibcon#enter wrdev, iclass 4, count 2 2006.286.00:06:31.48#ibcon#first serial, iclass 4, count 2 2006.286.00:06:31.48#ibcon#enter sib2, iclass 4, count 2 2006.286.00:06:31.48#ibcon#flushed, iclass 4, count 2 2006.286.00:06:31.48#ibcon#about to write, iclass 4, count 2 2006.286.00:06:31.48#ibcon#wrote, iclass 4, count 2 2006.286.00:06:31.48#ibcon#about to read 3, iclass 4, count 2 2006.286.00:06:31.50#ibcon#read 3, iclass 4, count 2 2006.286.00:06:31.50#ibcon#about to read 4, iclass 4, count 2 2006.286.00:06:31.50#ibcon#read 4, iclass 4, count 2 2006.286.00:06:31.50#ibcon#about to read 5, iclass 4, count 2 2006.286.00:06:31.50#ibcon#read 5, iclass 4, count 2 2006.286.00:06:31.50#ibcon#about to read 6, iclass 4, count 2 2006.286.00:06:31.50#ibcon#read 6, iclass 4, count 2 2006.286.00:06:31.50#ibcon#end of sib2, iclass 4, count 2 2006.286.00:06:31.50#ibcon#*mode == 0, iclass 4, count 2 2006.286.00:06:31.50#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.00:06:31.50#ibcon#[25=AT05-03\r\n] 2006.286.00:06:31.50#ibcon#*before write, iclass 4, count 2 2006.286.00:06:31.50#ibcon#enter sib2, iclass 4, count 2 2006.286.00:06:31.50#ibcon#flushed, iclass 4, count 2 2006.286.00:06:31.50#ibcon#about to write, iclass 4, count 2 2006.286.00:06:31.50#ibcon#wrote, iclass 4, count 2 2006.286.00:06:31.50#ibcon#about to read 3, iclass 4, count 2 2006.286.00:06:31.53#ibcon#read 3, iclass 4, count 2 2006.286.00:06:31.53#ibcon#about to read 4, iclass 4, count 2 2006.286.00:06:31.53#ibcon#read 4, iclass 4, count 2 2006.286.00:06:31.53#ibcon#about to read 5, iclass 4, count 2 2006.286.00:06:31.53#ibcon#read 5, iclass 4, count 2 2006.286.00:06:31.53#ibcon#about to read 6, iclass 4, count 2 2006.286.00:06:31.53#ibcon#read 6, iclass 4, count 2 2006.286.00:06:31.53#ibcon#end of sib2, iclass 4, count 2 2006.286.00:06:31.53#ibcon#*after write, iclass 4, count 2 2006.286.00:06:31.53#ibcon#*before return 0, iclass 4, count 2 2006.286.00:06:31.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:06:31.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:06:31.53#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.00:06:31.53#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:31.53#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:06:31.65#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:06:31.65#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:06:31.65#ibcon#enter wrdev, iclass 4, count 0 2006.286.00:06:31.65#ibcon#first serial, iclass 4, count 0 2006.286.00:06:31.65#ibcon#enter sib2, iclass 4, count 0 2006.286.00:06:31.65#ibcon#flushed, iclass 4, count 0 2006.286.00:06:31.65#ibcon#about to write, iclass 4, count 0 2006.286.00:06:31.65#ibcon#wrote, iclass 4, count 0 2006.286.00:06:31.65#ibcon#about to read 3, iclass 4, count 0 2006.286.00:06:31.67#ibcon#read 3, iclass 4, count 0 2006.286.00:06:31.67#ibcon#about to read 4, iclass 4, count 0 2006.286.00:06:31.67#ibcon#read 4, iclass 4, count 0 2006.286.00:06:31.67#ibcon#about to read 5, iclass 4, count 0 2006.286.00:06:31.67#ibcon#read 5, iclass 4, count 0 2006.286.00:06:31.67#ibcon#about to read 6, iclass 4, count 0 2006.286.00:06:31.67#ibcon#read 6, iclass 4, count 0 2006.286.00:06:31.67#ibcon#end of sib2, iclass 4, count 0 2006.286.00:06:31.67#ibcon#*mode == 0, iclass 4, count 0 2006.286.00:06:31.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.00:06:31.67#ibcon#[25=USB\r\n] 2006.286.00:06:31.67#ibcon#*before write, iclass 4, count 0 2006.286.00:06:31.67#ibcon#enter sib2, iclass 4, count 0 2006.286.00:06:31.67#ibcon#flushed, iclass 4, count 0 2006.286.00:06:31.67#ibcon#about to write, iclass 4, count 0 2006.286.00:06:31.67#ibcon#wrote, iclass 4, count 0 2006.286.00:06:31.67#ibcon#about to read 3, iclass 4, count 0 2006.286.00:06:31.70#ibcon#read 3, iclass 4, count 0 2006.286.00:06:31.70#ibcon#about to read 4, iclass 4, count 0 2006.286.00:06:31.70#ibcon#read 4, iclass 4, count 0 2006.286.00:06:31.70#ibcon#about to read 5, iclass 4, count 0 2006.286.00:06:31.70#ibcon#read 5, iclass 4, count 0 2006.286.00:06:31.70#ibcon#about to read 6, iclass 4, count 0 2006.286.00:06:31.70#ibcon#read 6, iclass 4, count 0 2006.286.00:06:31.70#ibcon#end of sib2, iclass 4, count 0 2006.286.00:06:31.70#ibcon#*after write, iclass 4, count 0 2006.286.00:06:31.70#ibcon#*before return 0, iclass 4, count 0 2006.286.00:06:31.70#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:06:31.70#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:06:31.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.00:06:31.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.00:06:31.70$vck44/valo=6,814.99 2006.286.00:06:31.70#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.00:06:31.70#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.00:06:31.70#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:31.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:06:31.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:06:31.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:06:31.70#ibcon#enter wrdev, iclass 6, count 0 2006.286.00:06:31.70#ibcon#first serial, iclass 6, count 0 2006.286.00:06:31.70#ibcon#enter sib2, iclass 6, count 0 2006.286.00:06:31.70#ibcon#flushed, iclass 6, count 0 2006.286.00:06:31.70#ibcon#about to write, iclass 6, count 0 2006.286.00:06:31.70#ibcon#wrote, iclass 6, count 0 2006.286.00:06:31.70#ibcon#about to read 3, iclass 6, count 0 2006.286.00:06:31.72#ibcon#read 3, iclass 6, count 0 2006.286.00:06:31.72#ibcon#about to read 4, iclass 6, count 0 2006.286.00:06:31.72#ibcon#read 4, iclass 6, count 0 2006.286.00:06:31.72#ibcon#about to read 5, iclass 6, count 0 2006.286.00:06:31.72#ibcon#read 5, iclass 6, count 0 2006.286.00:06:31.72#ibcon#about to read 6, iclass 6, count 0 2006.286.00:06:31.72#ibcon#read 6, iclass 6, count 0 2006.286.00:06:31.72#ibcon#end of sib2, iclass 6, count 0 2006.286.00:06:31.72#ibcon#*mode == 0, iclass 6, count 0 2006.286.00:06:31.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.00:06:31.72#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.00:06:31.72#ibcon#*before write, iclass 6, count 0 2006.286.00:06:31.72#ibcon#enter sib2, iclass 6, count 0 2006.286.00:06:31.72#ibcon#flushed, iclass 6, count 0 2006.286.00:06:31.72#ibcon#about to write, iclass 6, count 0 2006.286.00:06:31.72#ibcon#wrote, iclass 6, count 0 2006.286.00:06:31.72#ibcon#about to read 3, iclass 6, count 0 2006.286.00:06:31.76#ibcon#read 3, iclass 6, count 0 2006.286.00:06:31.76#ibcon#about to read 4, iclass 6, count 0 2006.286.00:06:31.76#ibcon#read 4, iclass 6, count 0 2006.286.00:06:31.76#ibcon#about to read 5, iclass 6, count 0 2006.286.00:06:31.76#ibcon#read 5, iclass 6, count 0 2006.286.00:06:31.76#ibcon#about to read 6, iclass 6, count 0 2006.286.00:06:31.76#ibcon#read 6, iclass 6, count 0 2006.286.00:06:31.76#ibcon#end of sib2, iclass 6, count 0 2006.286.00:06:31.76#ibcon#*after write, iclass 6, count 0 2006.286.00:06:31.76#ibcon#*before return 0, iclass 6, count 0 2006.286.00:06:31.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:06:31.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:06:31.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.00:06:31.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.00:06:31.76$vck44/va=6,4 2006.286.00:06:31.76#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.00:06:31.76#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.00:06:31.76#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:31.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:06:31.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:06:31.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:06:31.82#ibcon#enter wrdev, iclass 10, count 2 2006.286.00:06:31.82#ibcon#first serial, iclass 10, count 2 2006.286.00:06:31.82#ibcon#enter sib2, iclass 10, count 2 2006.286.00:06:31.82#ibcon#flushed, iclass 10, count 2 2006.286.00:06:31.82#ibcon#about to write, iclass 10, count 2 2006.286.00:06:31.82#ibcon#wrote, iclass 10, count 2 2006.286.00:06:31.82#ibcon#about to read 3, iclass 10, count 2 2006.286.00:06:31.84#ibcon#read 3, iclass 10, count 2 2006.286.00:06:31.84#ibcon#about to read 4, iclass 10, count 2 2006.286.00:06:31.84#ibcon#read 4, iclass 10, count 2 2006.286.00:06:31.84#ibcon#about to read 5, iclass 10, count 2 2006.286.00:06:31.84#ibcon#read 5, iclass 10, count 2 2006.286.00:06:31.84#ibcon#about to read 6, iclass 10, count 2 2006.286.00:06:31.84#ibcon#read 6, iclass 10, count 2 2006.286.00:06:31.84#ibcon#end of sib2, iclass 10, count 2 2006.286.00:06:31.84#ibcon#*mode == 0, iclass 10, count 2 2006.286.00:06:31.84#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.00:06:31.84#ibcon#[25=AT06-04\r\n] 2006.286.00:06:31.84#ibcon#*before write, iclass 10, count 2 2006.286.00:06:31.84#ibcon#enter sib2, iclass 10, count 2 2006.286.00:06:31.84#ibcon#flushed, iclass 10, count 2 2006.286.00:06:31.84#ibcon#about to write, iclass 10, count 2 2006.286.00:06:31.84#ibcon#wrote, iclass 10, count 2 2006.286.00:06:31.84#ibcon#about to read 3, iclass 10, count 2 2006.286.00:06:31.87#ibcon#read 3, iclass 10, count 2 2006.286.00:06:31.87#ibcon#about to read 4, iclass 10, count 2 2006.286.00:06:31.87#ibcon#read 4, iclass 10, count 2 2006.286.00:06:31.87#ibcon#about to read 5, iclass 10, count 2 2006.286.00:06:31.87#ibcon#read 5, iclass 10, count 2 2006.286.00:06:31.87#ibcon#about to read 6, iclass 10, count 2 2006.286.00:06:31.87#ibcon#read 6, iclass 10, count 2 2006.286.00:06:31.87#ibcon#end of sib2, iclass 10, count 2 2006.286.00:06:31.87#ibcon#*after write, iclass 10, count 2 2006.286.00:06:31.87#ibcon#*before return 0, iclass 10, count 2 2006.286.00:06:31.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:06:31.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:06:31.87#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.00:06:31.87#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:31.87#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:06:31.99#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:06:31.99#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:06:31.99#ibcon#enter wrdev, iclass 10, count 0 2006.286.00:06:31.99#ibcon#first serial, iclass 10, count 0 2006.286.00:06:31.99#ibcon#enter sib2, iclass 10, count 0 2006.286.00:06:31.99#ibcon#flushed, iclass 10, count 0 2006.286.00:06:31.99#ibcon#about to write, iclass 10, count 0 2006.286.00:06:31.99#ibcon#wrote, iclass 10, count 0 2006.286.00:06:31.99#ibcon#about to read 3, iclass 10, count 0 2006.286.00:06:32.01#ibcon#read 3, iclass 10, count 0 2006.286.00:06:32.01#ibcon#about to read 4, iclass 10, count 0 2006.286.00:06:32.01#ibcon#read 4, iclass 10, count 0 2006.286.00:06:32.01#ibcon#about to read 5, iclass 10, count 0 2006.286.00:06:32.01#ibcon#read 5, iclass 10, count 0 2006.286.00:06:32.01#ibcon#about to read 6, iclass 10, count 0 2006.286.00:06:32.01#ibcon#read 6, iclass 10, count 0 2006.286.00:06:32.01#ibcon#end of sib2, iclass 10, count 0 2006.286.00:06:32.01#ibcon#*mode == 0, iclass 10, count 0 2006.286.00:06:32.01#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.00:06:32.01#ibcon#[25=USB\r\n] 2006.286.00:06:32.01#ibcon#*before write, iclass 10, count 0 2006.286.00:06:32.01#ibcon#enter sib2, iclass 10, count 0 2006.286.00:06:32.01#ibcon#flushed, iclass 10, count 0 2006.286.00:06:32.01#ibcon#about to write, iclass 10, count 0 2006.286.00:06:32.01#ibcon#wrote, iclass 10, count 0 2006.286.00:06:32.01#ibcon#about to read 3, iclass 10, count 0 2006.286.00:06:32.04#ibcon#read 3, iclass 10, count 0 2006.286.00:06:32.04#ibcon#about to read 4, iclass 10, count 0 2006.286.00:06:32.04#ibcon#read 4, iclass 10, count 0 2006.286.00:06:32.04#ibcon#about to read 5, iclass 10, count 0 2006.286.00:06:32.04#ibcon#read 5, iclass 10, count 0 2006.286.00:06:32.04#ibcon#about to read 6, iclass 10, count 0 2006.286.00:06:32.04#ibcon#read 6, iclass 10, count 0 2006.286.00:06:32.04#ibcon#end of sib2, iclass 10, count 0 2006.286.00:06:32.04#ibcon#*after write, iclass 10, count 0 2006.286.00:06:32.04#ibcon#*before return 0, iclass 10, count 0 2006.286.00:06:32.04#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:06:32.04#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:06:32.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.00:06:32.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.00:06:32.04$vck44/valo=7,864.99 2006.286.00:06:32.04#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.00:06:32.04#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.00:06:32.04#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:32.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:06:32.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:06:32.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:06:32.04#ibcon#enter wrdev, iclass 12, count 0 2006.286.00:06:32.04#ibcon#first serial, iclass 12, count 0 2006.286.00:06:32.04#ibcon#enter sib2, iclass 12, count 0 2006.286.00:06:32.04#ibcon#flushed, iclass 12, count 0 2006.286.00:06:32.04#ibcon#about to write, iclass 12, count 0 2006.286.00:06:32.04#ibcon#wrote, iclass 12, count 0 2006.286.00:06:32.04#ibcon#about to read 3, iclass 12, count 0 2006.286.00:06:32.06#ibcon#read 3, iclass 12, count 0 2006.286.00:06:32.06#ibcon#about to read 4, iclass 12, count 0 2006.286.00:06:32.06#ibcon#read 4, iclass 12, count 0 2006.286.00:06:32.06#ibcon#about to read 5, iclass 12, count 0 2006.286.00:06:32.06#ibcon#read 5, iclass 12, count 0 2006.286.00:06:32.06#ibcon#about to read 6, iclass 12, count 0 2006.286.00:06:32.06#ibcon#read 6, iclass 12, count 0 2006.286.00:06:32.06#ibcon#end of sib2, iclass 12, count 0 2006.286.00:06:32.06#ibcon#*mode == 0, iclass 12, count 0 2006.286.00:06:32.06#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.00:06:32.06#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.00:06:32.06#ibcon#*before write, iclass 12, count 0 2006.286.00:06:32.06#ibcon#enter sib2, iclass 12, count 0 2006.286.00:06:32.06#ibcon#flushed, iclass 12, count 0 2006.286.00:06:32.06#ibcon#about to write, iclass 12, count 0 2006.286.00:06:32.06#ibcon#wrote, iclass 12, count 0 2006.286.00:06:32.06#ibcon#about to read 3, iclass 12, count 0 2006.286.00:06:32.10#ibcon#read 3, iclass 12, count 0 2006.286.00:06:32.10#ibcon#about to read 4, iclass 12, count 0 2006.286.00:06:32.10#ibcon#read 4, iclass 12, count 0 2006.286.00:06:32.10#ibcon#about to read 5, iclass 12, count 0 2006.286.00:06:32.10#ibcon#read 5, iclass 12, count 0 2006.286.00:06:32.10#ibcon#about to read 6, iclass 12, count 0 2006.286.00:06:32.10#ibcon#read 6, iclass 12, count 0 2006.286.00:06:32.10#ibcon#end of sib2, iclass 12, count 0 2006.286.00:06:32.10#ibcon#*after write, iclass 12, count 0 2006.286.00:06:32.10#ibcon#*before return 0, iclass 12, count 0 2006.286.00:06:32.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:06:32.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:06:32.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.00:06:32.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.00:06:32.10$vck44/va=7,4 2006.286.00:06:32.10#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.00:06:32.10#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.00:06:32.10#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:32.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:06:32.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:06:32.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:06:32.16#ibcon#enter wrdev, iclass 14, count 2 2006.286.00:06:32.16#ibcon#first serial, iclass 14, count 2 2006.286.00:06:32.16#ibcon#enter sib2, iclass 14, count 2 2006.286.00:06:32.16#ibcon#flushed, iclass 14, count 2 2006.286.00:06:32.16#ibcon#about to write, iclass 14, count 2 2006.286.00:06:32.16#ibcon#wrote, iclass 14, count 2 2006.286.00:06:32.16#ibcon#about to read 3, iclass 14, count 2 2006.286.00:06:32.18#ibcon#read 3, iclass 14, count 2 2006.286.00:06:32.18#ibcon#about to read 4, iclass 14, count 2 2006.286.00:06:32.18#ibcon#read 4, iclass 14, count 2 2006.286.00:06:32.18#ibcon#about to read 5, iclass 14, count 2 2006.286.00:06:32.18#ibcon#read 5, iclass 14, count 2 2006.286.00:06:32.18#ibcon#about to read 6, iclass 14, count 2 2006.286.00:06:32.18#ibcon#read 6, iclass 14, count 2 2006.286.00:06:32.18#ibcon#end of sib2, iclass 14, count 2 2006.286.00:06:32.18#ibcon#*mode == 0, iclass 14, count 2 2006.286.00:06:32.18#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.00:06:32.18#ibcon#[25=AT07-04\r\n] 2006.286.00:06:32.18#ibcon#*before write, iclass 14, count 2 2006.286.00:06:32.18#ibcon#enter sib2, iclass 14, count 2 2006.286.00:06:32.18#ibcon#flushed, iclass 14, count 2 2006.286.00:06:32.18#ibcon#about to write, iclass 14, count 2 2006.286.00:06:32.18#ibcon#wrote, iclass 14, count 2 2006.286.00:06:32.18#ibcon#about to read 3, iclass 14, count 2 2006.286.00:06:32.21#ibcon#read 3, iclass 14, count 2 2006.286.00:06:32.21#ibcon#about to read 4, iclass 14, count 2 2006.286.00:06:32.21#ibcon#read 4, iclass 14, count 2 2006.286.00:06:32.21#ibcon#about to read 5, iclass 14, count 2 2006.286.00:06:32.21#ibcon#read 5, iclass 14, count 2 2006.286.00:06:32.21#ibcon#about to read 6, iclass 14, count 2 2006.286.00:06:32.21#ibcon#read 6, iclass 14, count 2 2006.286.00:06:32.21#ibcon#end of sib2, iclass 14, count 2 2006.286.00:06:32.21#ibcon#*after write, iclass 14, count 2 2006.286.00:06:32.21#ibcon#*before return 0, iclass 14, count 2 2006.286.00:06:32.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:06:32.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:06:32.21#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.00:06:32.21#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:32.21#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:06:32.33#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:06:32.33#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:06:32.33#ibcon#enter wrdev, iclass 14, count 0 2006.286.00:06:32.33#ibcon#first serial, iclass 14, count 0 2006.286.00:06:32.33#ibcon#enter sib2, iclass 14, count 0 2006.286.00:06:32.33#ibcon#flushed, iclass 14, count 0 2006.286.00:06:32.33#ibcon#about to write, iclass 14, count 0 2006.286.00:06:32.33#ibcon#wrote, iclass 14, count 0 2006.286.00:06:32.33#ibcon#about to read 3, iclass 14, count 0 2006.286.00:06:32.35#ibcon#read 3, iclass 14, count 0 2006.286.00:06:32.35#ibcon#about to read 4, iclass 14, count 0 2006.286.00:06:32.35#ibcon#read 4, iclass 14, count 0 2006.286.00:06:32.35#ibcon#about to read 5, iclass 14, count 0 2006.286.00:06:32.35#ibcon#read 5, iclass 14, count 0 2006.286.00:06:32.35#ibcon#about to read 6, iclass 14, count 0 2006.286.00:06:32.35#ibcon#read 6, iclass 14, count 0 2006.286.00:06:32.35#ibcon#end of sib2, iclass 14, count 0 2006.286.00:06:32.35#ibcon#*mode == 0, iclass 14, count 0 2006.286.00:06:32.35#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.00:06:32.35#ibcon#[25=USB\r\n] 2006.286.00:06:32.35#ibcon#*before write, iclass 14, count 0 2006.286.00:06:32.35#ibcon#enter sib2, iclass 14, count 0 2006.286.00:06:32.35#ibcon#flushed, iclass 14, count 0 2006.286.00:06:32.35#ibcon#about to write, iclass 14, count 0 2006.286.00:06:32.35#ibcon#wrote, iclass 14, count 0 2006.286.00:06:32.35#ibcon#about to read 3, iclass 14, count 0 2006.286.00:06:32.38#ibcon#read 3, iclass 14, count 0 2006.286.00:06:32.38#ibcon#about to read 4, iclass 14, count 0 2006.286.00:06:32.38#ibcon#read 4, iclass 14, count 0 2006.286.00:06:32.38#ibcon#about to read 5, iclass 14, count 0 2006.286.00:06:32.38#ibcon#read 5, iclass 14, count 0 2006.286.00:06:32.38#ibcon#about to read 6, iclass 14, count 0 2006.286.00:06:32.38#ibcon#read 6, iclass 14, count 0 2006.286.00:06:32.38#ibcon#end of sib2, iclass 14, count 0 2006.286.00:06:32.38#ibcon#*after write, iclass 14, count 0 2006.286.00:06:32.38#ibcon#*before return 0, iclass 14, count 0 2006.286.00:06:32.38#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:06:32.38#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:06:32.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.00:06:32.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.00:06:32.38$vck44/valo=8,884.99 2006.286.00:06:32.38#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.00:06:32.38#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.00:06:32.38#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:32.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:06:32.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:06:32.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:06:32.38#ibcon#enter wrdev, iclass 16, count 0 2006.286.00:06:32.38#ibcon#first serial, iclass 16, count 0 2006.286.00:06:32.38#ibcon#enter sib2, iclass 16, count 0 2006.286.00:06:32.38#ibcon#flushed, iclass 16, count 0 2006.286.00:06:32.38#ibcon#about to write, iclass 16, count 0 2006.286.00:06:32.38#ibcon#wrote, iclass 16, count 0 2006.286.00:06:32.38#ibcon#about to read 3, iclass 16, count 0 2006.286.00:06:32.40#ibcon#read 3, iclass 16, count 0 2006.286.00:06:32.40#ibcon#about to read 4, iclass 16, count 0 2006.286.00:06:32.40#ibcon#read 4, iclass 16, count 0 2006.286.00:06:32.40#ibcon#about to read 5, iclass 16, count 0 2006.286.00:06:32.40#ibcon#read 5, iclass 16, count 0 2006.286.00:06:32.40#ibcon#about to read 6, iclass 16, count 0 2006.286.00:06:32.40#ibcon#read 6, iclass 16, count 0 2006.286.00:06:32.40#ibcon#end of sib2, iclass 16, count 0 2006.286.00:06:32.40#ibcon#*mode == 0, iclass 16, count 0 2006.286.00:06:32.40#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.00:06:32.40#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.00:06:32.40#ibcon#*before write, iclass 16, count 0 2006.286.00:06:32.40#ibcon#enter sib2, iclass 16, count 0 2006.286.00:06:32.40#ibcon#flushed, iclass 16, count 0 2006.286.00:06:32.40#ibcon#about to write, iclass 16, count 0 2006.286.00:06:32.40#ibcon#wrote, iclass 16, count 0 2006.286.00:06:32.40#ibcon#about to read 3, iclass 16, count 0 2006.286.00:06:32.44#ibcon#read 3, iclass 16, count 0 2006.286.00:06:32.44#ibcon#about to read 4, iclass 16, count 0 2006.286.00:06:32.44#ibcon#read 4, iclass 16, count 0 2006.286.00:06:32.44#ibcon#about to read 5, iclass 16, count 0 2006.286.00:06:32.44#ibcon#read 5, iclass 16, count 0 2006.286.00:06:32.44#ibcon#about to read 6, iclass 16, count 0 2006.286.00:06:32.44#ibcon#read 6, iclass 16, count 0 2006.286.00:06:32.44#ibcon#end of sib2, iclass 16, count 0 2006.286.00:06:32.44#ibcon#*after write, iclass 16, count 0 2006.286.00:06:32.44#ibcon#*before return 0, iclass 16, count 0 2006.286.00:06:32.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:06:32.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:06:32.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.00:06:32.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.00:06:32.44$vck44/va=8,3 2006.286.00:06:32.44#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.00:06:32.44#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.00:06:32.44#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:32.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:06:32.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:06:32.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:06:32.50#ibcon#enter wrdev, iclass 18, count 2 2006.286.00:06:32.50#ibcon#first serial, iclass 18, count 2 2006.286.00:06:32.50#ibcon#enter sib2, iclass 18, count 2 2006.286.00:06:32.50#ibcon#flushed, iclass 18, count 2 2006.286.00:06:32.50#ibcon#about to write, iclass 18, count 2 2006.286.00:06:32.50#ibcon#wrote, iclass 18, count 2 2006.286.00:06:32.50#ibcon#about to read 3, iclass 18, count 2 2006.286.00:06:32.52#ibcon#read 3, iclass 18, count 2 2006.286.00:06:32.52#ibcon#about to read 4, iclass 18, count 2 2006.286.00:06:32.52#ibcon#read 4, iclass 18, count 2 2006.286.00:06:32.52#ibcon#about to read 5, iclass 18, count 2 2006.286.00:06:32.52#ibcon#read 5, iclass 18, count 2 2006.286.00:06:32.52#ibcon#about to read 6, iclass 18, count 2 2006.286.00:06:32.52#ibcon#read 6, iclass 18, count 2 2006.286.00:06:32.52#ibcon#end of sib2, iclass 18, count 2 2006.286.00:06:32.52#ibcon#*mode == 0, iclass 18, count 2 2006.286.00:06:32.52#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.00:06:32.52#ibcon#[25=AT08-03\r\n] 2006.286.00:06:32.52#ibcon#*before write, iclass 18, count 2 2006.286.00:06:32.52#ibcon#enter sib2, iclass 18, count 2 2006.286.00:06:32.52#ibcon#flushed, iclass 18, count 2 2006.286.00:06:32.52#ibcon#about to write, iclass 18, count 2 2006.286.00:06:32.52#ibcon#wrote, iclass 18, count 2 2006.286.00:06:32.52#ibcon#about to read 3, iclass 18, count 2 2006.286.00:06:32.55#ibcon#read 3, iclass 18, count 2 2006.286.00:06:32.55#ibcon#about to read 4, iclass 18, count 2 2006.286.00:06:32.55#ibcon#read 4, iclass 18, count 2 2006.286.00:06:32.55#ibcon#about to read 5, iclass 18, count 2 2006.286.00:06:32.55#ibcon#read 5, iclass 18, count 2 2006.286.00:06:32.55#ibcon#about to read 6, iclass 18, count 2 2006.286.00:06:32.55#ibcon#read 6, iclass 18, count 2 2006.286.00:06:32.55#ibcon#end of sib2, iclass 18, count 2 2006.286.00:06:32.55#ibcon#*after write, iclass 18, count 2 2006.286.00:06:32.55#ibcon#*before return 0, iclass 18, count 2 2006.286.00:06:32.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:06:32.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:06:32.55#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.00:06:32.55#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:32.55#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:06:32.67#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:06:32.67#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:06:32.67#ibcon#enter wrdev, iclass 18, count 0 2006.286.00:06:32.67#ibcon#first serial, iclass 18, count 0 2006.286.00:06:32.67#ibcon#enter sib2, iclass 18, count 0 2006.286.00:06:32.67#ibcon#flushed, iclass 18, count 0 2006.286.00:06:32.67#ibcon#about to write, iclass 18, count 0 2006.286.00:06:32.67#ibcon#wrote, iclass 18, count 0 2006.286.00:06:32.67#ibcon#about to read 3, iclass 18, count 0 2006.286.00:06:32.69#ibcon#read 3, iclass 18, count 0 2006.286.00:06:32.69#ibcon#about to read 4, iclass 18, count 0 2006.286.00:06:32.69#ibcon#read 4, iclass 18, count 0 2006.286.00:06:32.69#ibcon#about to read 5, iclass 18, count 0 2006.286.00:06:32.69#ibcon#read 5, iclass 18, count 0 2006.286.00:06:32.69#ibcon#about to read 6, iclass 18, count 0 2006.286.00:06:32.69#ibcon#read 6, iclass 18, count 0 2006.286.00:06:32.69#ibcon#end of sib2, iclass 18, count 0 2006.286.00:06:32.69#ibcon#*mode == 0, iclass 18, count 0 2006.286.00:06:32.69#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.00:06:32.69#ibcon#[25=USB\r\n] 2006.286.00:06:32.69#ibcon#*before write, iclass 18, count 0 2006.286.00:06:32.69#ibcon#enter sib2, iclass 18, count 0 2006.286.00:06:32.69#ibcon#flushed, iclass 18, count 0 2006.286.00:06:32.69#ibcon#about to write, iclass 18, count 0 2006.286.00:06:32.69#ibcon#wrote, iclass 18, count 0 2006.286.00:06:32.69#ibcon#about to read 3, iclass 18, count 0 2006.286.00:06:32.72#ibcon#read 3, iclass 18, count 0 2006.286.00:06:32.72#ibcon#about to read 4, iclass 18, count 0 2006.286.00:06:32.72#ibcon#read 4, iclass 18, count 0 2006.286.00:06:32.72#ibcon#about to read 5, iclass 18, count 0 2006.286.00:06:32.72#ibcon#read 5, iclass 18, count 0 2006.286.00:06:32.72#ibcon#about to read 6, iclass 18, count 0 2006.286.00:06:32.72#ibcon#read 6, iclass 18, count 0 2006.286.00:06:32.72#ibcon#end of sib2, iclass 18, count 0 2006.286.00:06:32.72#ibcon#*after write, iclass 18, count 0 2006.286.00:06:32.72#ibcon#*before return 0, iclass 18, count 0 2006.286.00:06:32.72#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:06:32.72#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:06:32.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.00:06:32.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.00:06:32.72$vck44/vblo=1,629.99 2006.286.00:06:32.72#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.00:06:32.72#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.00:06:32.72#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:32.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.00:06:32.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.00:06:32.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.00:06:32.72#ibcon#enter wrdev, iclass 20, count 0 2006.286.00:06:32.72#ibcon#first serial, iclass 20, count 0 2006.286.00:06:32.72#ibcon#enter sib2, iclass 20, count 0 2006.286.00:06:32.72#ibcon#flushed, iclass 20, count 0 2006.286.00:06:32.72#ibcon#about to write, iclass 20, count 0 2006.286.00:06:32.72#ibcon#wrote, iclass 20, count 0 2006.286.00:06:32.72#ibcon#about to read 3, iclass 20, count 0 2006.286.00:06:32.74#ibcon#read 3, iclass 20, count 0 2006.286.00:06:32.74#ibcon#about to read 4, iclass 20, count 0 2006.286.00:06:32.74#ibcon#read 4, iclass 20, count 0 2006.286.00:06:32.74#ibcon#about to read 5, iclass 20, count 0 2006.286.00:06:32.74#ibcon#read 5, iclass 20, count 0 2006.286.00:06:32.74#ibcon#about to read 6, iclass 20, count 0 2006.286.00:06:32.74#ibcon#read 6, iclass 20, count 0 2006.286.00:06:32.74#ibcon#end of sib2, iclass 20, count 0 2006.286.00:06:32.74#ibcon#*mode == 0, iclass 20, count 0 2006.286.00:06:32.74#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.00:06:32.74#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.00:06:32.74#ibcon#*before write, iclass 20, count 0 2006.286.00:06:32.74#ibcon#enter sib2, iclass 20, count 0 2006.286.00:06:32.74#ibcon#flushed, iclass 20, count 0 2006.286.00:06:32.74#ibcon#about to write, iclass 20, count 0 2006.286.00:06:32.74#ibcon#wrote, iclass 20, count 0 2006.286.00:06:32.74#ibcon#about to read 3, iclass 20, count 0 2006.286.00:06:32.78#ibcon#read 3, iclass 20, count 0 2006.286.00:06:32.78#ibcon#about to read 4, iclass 20, count 0 2006.286.00:06:32.78#ibcon#read 4, iclass 20, count 0 2006.286.00:06:32.78#ibcon#about to read 5, iclass 20, count 0 2006.286.00:06:32.78#ibcon#read 5, iclass 20, count 0 2006.286.00:06:32.78#ibcon#about to read 6, iclass 20, count 0 2006.286.00:06:32.78#ibcon#read 6, iclass 20, count 0 2006.286.00:06:32.78#ibcon#end of sib2, iclass 20, count 0 2006.286.00:06:32.78#ibcon#*after write, iclass 20, count 0 2006.286.00:06:32.78#ibcon#*before return 0, iclass 20, count 0 2006.286.00:06:32.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.00:06:32.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.00:06:32.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.00:06:32.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.00:06:32.78$vck44/vb=1,4 2006.286.00:06:32.78#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.00:06:32.78#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.00:06:32.78#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:32.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.00:06:32.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.00:06:32.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.00:06:32.78#ibcon#enter wrdev, iclass 22, count 2 2006.286.00:06:32.78#ibcon#first serial, iclass 22, count 2 2006.286.00:06:32.78#ibcon#enter sib2, iclass 22, count 2 2006.286.00:06:32.78#ibcon#flushed, iclass 22, count 2 2006.286.00:06:32.78#ibcon#about to write, iclass 22, count 2 2006.286.00:06:32.78#ibcon#wrote, iclass 22, count 2 2006.286.00:06:32.78#ibcon#about to read 3, iclass 22, count 2 2006.286.00:06:32.80#ibcon#read 3, iclass 22, count 2 2006.286.00:06:32.80#ibcon#about to read 4, iclass 22, count 2 2006.286.00:06:32.80#ibcon#read 4, iclass 22, count 2 2006.286.00:06:32.80#ibcon#about to read 5, iclass 22, count 2 2006.286.00:06:32.80#ibcon#read 5, iclass 22, count 2 2006.286.00:06:32.80#ibcon#about to read 6, iclass 22, count 2 2006.286.00:06:32.80#ibcon#read 6, iclass 22, count 2 2006.286.00:06:32.80#ibcon#end of sib2, iclass 22, count 2 2006.286.00:06:32.80#ibcon#*mode == 0, iclass 22, count 2 2006.286.00:06:32.80#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.00:06:32.80#ibcon#[27=AT01-04\r\n] 2006.286.00:06:32.80#ibcon#*before write, iclass 22, count 2 2006.286.00:06:32.80#ibcon#enter sib2, iclass 22, count 2 2006.286.00:06:32.80#ibcon#flushed, iclass 22, count 2 2006.286.00:06:32.80#ibcon#about to write, iclass 22, count 2 2006.286.00:06:32.80#ibcon#wrote, iclass 22, count 2 2006.286.00:06:32.80#ibcon#about to read 3, iclass 22, count 2 2006.286.00:06:32.83#ibcon#read 3, iclass 22, count 2 2006.286.00:06:32.83#ibcon#about to read 4, iclass 22, count 2 2006.286.00:06:32.83#ibcon#read 4, iclass 22, count 2 2006.286.00:06:32.83#ibcon#about to read 5, iclass 22, count 2 2006.286.00:06:32.83#ibcon#read 5, iclass 22, count 2 2006.286.00:06:32.83#ibcon#about to read 6, iclass 22, count 2 2006.286.00:06:32.83#ibcon#read 6, iclass 22, count 2 2006.286.00:06:32.83#ibcon#end of sib2, iclass 22, count 2 2006.286.00:06:32.83#ibcon#*after write, iclass 22, count 2 2006.286.00:06:32.83#ibcon#*before return 0, iclass 22, count 2 2006.286.00:06:32.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.00:06:32.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.00:06:32.83#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.00:06:32.83#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:32.83#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.00:06:32.95#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.00:06:32.95#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.00:06:32.95#ibcon#enter wrdev, iclass 22, count 0 2006.286.00:06:32.95#ibcon#first serial, iclass 22, count 0 2006.286.00:06:32.95#ibcon#enter sib2, iclass 22, count 0 2006.286.00:06:32.95#ibcon#flushed, iclass 22, count 0 2006.286.00:06:32.95#ibcon#about to write, iclass 22, count 0 2006.286.00:06:32.95#ibcon#wrote, iclass 22, count 0 2006.286.00:06:32.95#ibcon#about to read 3, iclass 22, count 0 2006.286.00:06:32.97#ibcon#read 3, iclass 22, count 0 2006.286.00:06:32.97#ibcon#about to read 4, iclass 22, count 0 2006.286.00:06:32.97#ibcon#read 4, iclass 22, count 0 2006.286.00:06:32.97#ibcon#about to read 5, iclass 22, count 0 2006.286.00:06:32.97#ibcon#read 5, iclass 22, count 0 2006.286.00:06:32.97#ibcon#about to read 6, iclass 22, count 0 2006.286.00:06:32.97#ibcon#read 6, iclass 22, count 0 2006.286.00:06:32.97#ibcon#end of sib2, iclass 22, count 0 2006.286.00:06:32.97#ibcon#*mode == 0, iclass 22, count 0 2006.286.00:06:32.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.00:06:32.97#ibcon#[27=USB\r\n] 2006.286.00:06:32.97#ibcon#*before write, iclass 22, count 0 2006.286.00:06:32.97#ibcon#enter sib2, iclass 22, count 0 2006.286.00:06:32.97#ibcon#flushed, iclass 22, count 0 2006.286.00:06:32.97#ibcon#about to write, iclass 22, count 0 2006.286.00:06:32.97#ibcon#wrote, iclass 22, count 0 2006.286.00:06:32.97#ibcon#about to read 3, iclass 22, count 0 2006.286.00:06:33.00#ibcon#read 3, iclass 22, count 0 2006.286.00:06:33.00#ibcon#about to read 4, iclass 22, count 0 2006.286.00:06:33.00#ibcon#read 4, iclass 22, count 0 2006.286.00:06:33.00#ibcon#about to read 5, iclass 22, count 0 2006.286.00:06:33.00#ibcon#read 5, iclass 22, count 0 2006.286.00:06:33.00#ibcon#about to read 6, iclass 22, count 0 2006.286.00:06:33.00#ibcon#read 6, iclass 22, count 0 2006.286.00:06:33.00#ibcon#end of sib2, iclass 22, count 0 2006.286.00:06:33.00#ibcon#*after write, iclass 22, count 0 2006.286.00:06:33.00#ibcon#*before return 0, iclass 22, count 0 2006.286.00:06:33.00#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.00:06:33.00#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.00:06:33.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.00:06:33.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.00:06:33.00$vck44/vblo=2,634.99 2006.286.00:06:33.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.00:06:33.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.00:06:33.00#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:33.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:06:33.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:06:33.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:06:33.00#ibcon#enter wrdev, iclass 24, count 0 2006.286.00:06:33.00#ibcon#first serial, iclass 24, count 0 2006.286.00:06:33.00#ibcon#enter sib2, iclass 24, count 0 2006.286.00:06:33.00#ibcon#flushed, iclass 24, count 0 2006.286.00:06:33.00#ibcon#about to write, iclass 24, count 0 2006.286.00:06:33.00#ibcon#wrote, iclass 24, count 0 2006.286.00:06:33.00#ibcon#about to read 3, iclass 24, count 0 2006.286.00:06:33.02#ibcon#read 3, iclass 24, count 0 2006.286.00:06:33.02#ibcon#about to read 4, iclass 24, count 0 2006.286.00:06:33.02#ibcon#read 4, iclass 24, count 0 2006.286.00:06:33.02#ibcon#about to read 5, iclass 24, count 0 2006.286.00:06:33.02#ibcon#read 5, iclass 24, count 0 2006.286.00:06:33.02#ibcon#about to read 6, iclass 24, count 0 2006.286.00:06:33.02#ibcon#read 6, iclass 24, count 0 2006.286.00:06:33.02#ibcon#end of sib2, iclass 24, count 0 2006.286.00:06:33.02#ibcon#*mode == 0, iclass 24, count 0 2006.286.00:06:33.02#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.00:06:33.02#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.00:06:33.02#ibcon#*before write, iclass 24, count 0 2006.286.00:06:33.02#ibcon#enter sib2, iclass 24, count 0 2006.286.00:06:33.02#ibcon#flushed, iclass 24, count 0 2006.286.00:06:33.02#ibcon#about to write, iclass 24, count 0 2006.286.00:06:33.02#ibcon#wrote, iclass 24, count 0 2006.286.00:06:33.02#ibcon#about to read 3, iclass 24, count 0 2006.286.00:06:33.06#ibcon#read 3, iclass 24, count 0 2006.286.00:06:33.06#ibcon#about to read 4, iclass 24, count 0 2006.286.00:06:33.06#ibcon#read 4, iclass 24, count 0 2006.286.00:06:33.06#ibcon#about to read 5, iclass 24, count 0 2006.286.00:06:33.06#ibcon#read 5, iclass 24, count 0 2006.286.00:06:33.06#ibcon#about to read 6, iclass 24, count 0 2006.286.00:06:33.06#ibcon#read 6, iclass 24, count 0 2006.286.00:06:33.06#ibcon#end of sib2, iclass 24, count 0 2006.286.00:06:33.06#ibcon#*after write, iclass 24, count 0 2006.286.00:06:33.06#ibcon#*before return 0, iclass 24, count 0 2006.286.00:06:33.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:06:33.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:06:33.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.00:06:33.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.00:06:33.06$vck44/vb=2,5 2006.286.00:06:33.06#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.00:06:33.06#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.00:06:33.06#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:33.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:06:33.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:06:33.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:06:33.12#ibcon#enter wrdev, iclass 26, count 2 2006.286.00:06:33.12#ibcon#first serial, iclass 26, count 2 2006.286.00:06:33.12#ibcon#enter sib2, iclass 26, count 2 2006.286.00:06:33.12#ibcon#flushed, iclass 26, count 2 2006.286.00:06:33.12#ibcon#about to write, iclass 26, count 2 2006.286.00:06:33.12#ibcon#wrote, iclass 26, count 2 2006.286.00:06:33.12#ibcon#about to read 3, iclass 26, count 2 2006.286.00:06:33.14#ibcon#read 3, iclass 26, count 2 2006.286.00:06:33.14#ibcon#about to read 4, iclass 26, count 2 2006.286.00:06:33.14#ibcon#read 4, iclass 26, count 2 2006.286.00:06:33.14#ibcon#about to read 5, iclass 26, count 2 2006.286.00:06:33.14#ibcon#read 5, iclass 26, count 2 2006.286.00:06:33.14#ibcon#about to read 6, iclass 26, count 2 2006.286.00:06:33.14#ibcon#read 6, iclass 26, count 2 2006.286.00:06:33.14#ibcon#end of sib2, iclass 26, count 2 2006.286.00:06:33.14#ibcon#*mode == 0, iclass 26, count 2 2006.286.00:06:33.14#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.00:06:33.14#ibcon#[27=AT02-05\r\n] 2006.286.00:06:33.14#ibcon#*before write, iclass 26, count 2 2006.286.00:06:33.14#ibcon#enter sib2, iclass 26, count 2 2006.286.00:06:33.14#ibcon#flushed, iclass 26, count 2 2006.286.00:06:33.14#ibcon#about to write, iclass 26, count 2 2006.286.00:06:33.14#ibcon#wrote, iclass 26, count 2 2006.286.00:06:33.14#ibcon#about to read 3, iclass 26, count 2 2006.286.00:06:33.17#ibcon#read 3, iclass 26, count 2 2006.286.00:06:33.17#ibcon#about to read 4, iclass 26, count 2 2006.286.00:06:33.17#ibcon#read 4, iclass 26, count 2 2006.286.00:06:33.17#ibcon#about to read 5, iclass 26, count 2 2006.286.00:06:33.17#ibcon#read 5, iclass 26, count 2 2006.286.00:06:33.17#ibcon#about to read 6, iclass 26, count 2 2006.286.00:06:33.17#ibcon#read 6, iclass 26, count 2 2006.286.00:06:33.17#ibcon#end of sib2, iclass 26, count 2 2006.286.00:06:33.17#ibcon#*after write, iclass 26, count 2 2006.286.00:06:33.17#ibcon#*before return 0, iclass 26, count 2 2006.286.00:06:33.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:06:33.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:06:33.17#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.00:06:33.17#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:33.17#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:06:33.29#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:06:33.29#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:06:33.29#ibcon#enter wrdev, iclass 26, count 0 2006.286.00:06:33.29#ibcon#first serial, iclass 26, count 0 2006.286.00:06:33.29#ibcon#enter sib2, iclass 26, count 0 2006.286.00:06:33.29#ibcon#flushed, iclass 26, count 0 2006.286.00:06:33.29#ibcon#about to write, iclass 26, count 0 2006.286.00:06:33.29#ibcon#wrote, iclass 26, count 0 2006.286.00:06:33.29#ibcon#about to read 3, iclass 26, count 0 2006.286.00:06:33.31#ibcon#read 3, iclass 26, count 0 2006.286.00:06:33.31#ibcon#about to read 4, iclass 26, count 0 2006.286.00:06:33.31#ibcon#read 4, iclass 26, count 0 2006.286.00:06:33.31#ibcon#about to read 5, iclass 26, count 0 2006.286.00:06:33.31#ibcon#read 5, iclass 26, count 0 2006.286.00:06:33.31#ibcon#about to read 6, iclass 26, count 0 2006.286.00:06:33.31#ibcon#read 6, iclass 26, count 0 2006.286.00:06:33.31#ibcon#end of sib2, iclass 26, count 0 2006.286.00:06:33.31#ibcon#*mode == 0, iclass 26, count 0 2006.286.00:06:33.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.00:06:33.31#ibcon#[27=USB\r\n] 2006.286.00:06:33.31#ibcon#*before write, iclass 26, count 0 2006.286.00:06:33.31#ibcon#enter sib2, iclass 26, count 0 2006.286.00:06:33.31#ibcon#flushed, iclass 26, count 0 2006.286.00:06:33.31#ibcon#about to write, iclass 26, count 0 2006.286.00:06:33.31#ibcon#wrote, iclass 26, count 0 2006.286.00:06:33.31#ibcon#about to read 3, iclass 26, count 0 2006.286.00:06:33.34#ibcon#read 3, iclass 26, count 0 2006.286.00:06:33.34#ibcon#about to read 4, iclass 26, count 0 2006.286.00:06:33.34#ibcon#read 4, iclass 26, count 0 2006.286.00:06:33.34#ibcon#about to read 5, iclass 26, count 0 2006.286.00:06:33.34#ibcon#read 5, iclass 26, count 0 2006.286.00:06:33.34#ibcon#about to read 6, iclass 26, count 0 2006.286.00:06:33.34#ibcon#read 6, iclass 26, count 0 2006.286.00:06:33.34#ibcon#end of sib2, iclass 26, count 0 2006.286.00:06:33.34#ibcon#*after write, iclass 26, count 0 2006.286.00:06:33.34#ibcon#*before return 0, iclass 26, count 0 2006.286.00:06:33.34#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:06:33.34#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:06:33.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.00:06:33.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.00:06:33.34$vck44/vblo=3,649.99 2006.286.00:06:33.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.00:06:33.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.00:06:33.34#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:33.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:06:33.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:06:33.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:06:33.34#ibcon#enter wrdev, iclass 28, count 0 2006.286.00:06:33.34#ibcon#first serial, iclass 28, count 0 2006.286.00:06:33.34#ibcon#enter sib2, iclass 28, count 0 2006.286.00:06:33.34#ibcon#flushed, iclass 28, count 0 2006.286.00:06:33.34#ibcon#about to write, iclass 28, count 0 2006.286.00:06:33.34#ibcon#wrote, iclass 28, count 0 2006.286.00:06:33.34#ibcon#about to read 3, iclass 28, count 0 2006.286.00:06:33.36#ibcon#read 3, iclass 28, count 0 2006.286.00:06:33.36#ibcon#about to read 4, iclass 28, count 0 2006.286.00:06:33.36#ibcon#read 4, iclass 28, count 0 2006.286.00:06:33.36#ibcon#about to read 5, iclass 28, count 0 2006.286.00:06:33.36#ibcon#read 5, iclass 28, count 0 2006.286.00:06:33.36#ibcon#about to read 6, iclass 28, count 0 2006.286.00:06:33.36#ibcon#read 6, iclass 28, count 0 2006.286.00:06:33.36#ibcon#end of sib2, iclass 28, count 0 2006.286.00:06:33.36#ibcon#*mode == 0, iclass 28, count 0 2006.286.00:06:33.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.00:06:33.36#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.00:06:33.36#ibcon#*before write, iclass 28, count 0 2006.286.00:06:33.36#ibcon#enter sib2, iclass 28, count 0 2006.286.00:06:33.36#ibcon#flushed, iclass 28, count 0 2006.286.00:06:33.36#ibcon#about to write, iclass 28, count 0 2006.286.00:06:33.36#ibcon#wrote, iclass 28, count 0 2006.286.00:06:33.36#ibcon#about to read 3, iclass 28, count 0 2006.286.00:06:33.40#ibcon#read 3, iclass 28, count 0 2006.286.00:06:33.40#ibcon#about to read 4, iclass 28, count 0 2006.286.00:06:33.40#ibcon#read 4, iclass 28, count 0 2006.286.00:06:33.40#ibcon#about to read 5, iclass 28, count 0 2006.286.00:06:33.40#ibcon#read 5, iclass 28, count 0 2006.286.00:06:33.40#ibcon#about to read 6, iclass 28, count 0 2006.286.00:06:33.40#ibcon#read 6, iclass 28, count 0 2006.286.00:06:33.40#ibcon#end of sib2, iclass 28, count 0 2006.286.00:06:33.40#ibcon#*after write, iclass 28, count 0 2006.286.00:06:33.40#ibcon#*before return 0, iclass 28, count 0 2006.286.00:06:33.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:06:33.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:06:33.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.00:06:33.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.00:06:33.40$vck44/vb=3,4 2006.286.00:06:33.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.00:06:33.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.00:06:33.40#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:33.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:06:33.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:06:33.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:06:33.46#ibcon#enter wrdev, iclass 30, count 2 2006.286.00:06:33.46#ibcon#first serial, iclass 30, count 2 2006.286.00:06:33.46#ibcon#enter sib2, iclass 30, count 2 2006.286.00:06:33.46#ibcon#flushed, iclass 30, count 2 2006.286.00:06:33.46#ibcon#about to write, iclass 30, count 2 2006.286.00:06:33.46#ibcon#wrote, iclass 30, count 2 2006.286.00:06:33.46#ibcon#about to read 3, iclass 30, count 2 2006.286.00:06:33.48#ibcon#read 3, iclass 30, count 2 2006.286.00:06:33.48#ibcon#about to read 4, iclass 30, count 2 2006.286.00:06:33.48#ibcon#read 4, iclass 30, count 2 2006.286.00:06:33.48#ibcon#about to read 5, iclass 30, count 2 2006.286.00:06:33.48#ibcon#read 5, iclass 30, count 2 2006.286.00:06:33.48#ibcon#about to read 6, iclass 30, count 2 2006.286.00:06:33.48#ibcon#read 6, iclass 30, count 2 2006.286.00:06:33.48#ibcon#end of sib2, iclass 30, count 2 2006.286.00:06:33.48#ibcon#*mode == 0, iclass 30, count 2 2006.286.00:06:33.48#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.00:06:33.48#ibcon#[27=AT03-04\r\n] 2006.286.00:06:33.48#ibcon#*before write, iclass 30, count 2 2006.286.00:06:33.48#ibcon#enter sib2, iclass 30, count 2 2006.286.00:06:33.48#ibcon#flushed, iclass 30, count 2 2006.286.00:06:33.48#ibcon#about to write, iclass 30, count 2 2006.286.00:06:33.48#ibcon#wrote, iclass 30, count 2 2006.286.00:06:33.48#ibcon#about to read 3, iclass 30, count 2 2006.286.00:06:33.51#ibcon#read 3, iclass 30, count 2 2006.286.00:06:33.51#ibcon#about to read 4, iclass 30, count 2 2006.286.00:06:33.51#ibcon#read 4, iclass 30, count 2 2006.286.00:06:33.51#ibcon#about to read 5, iclass 30, count 2 2006.286.00:06:33.51#ibcon#read 5, iclass 30, count 2 2006.286.00:06:33.51#ibcon#about to read 6, iclass 30, count 2 2006.286.00:06:33.51#ibcon#read 6, iclass 30, count 2 2006.286.00:06:33.51#ibcon#end of sib2, iclass 30, count 2 2006.286.00:06:33.51#ibcon#*after write, iclass 30, count 2 2006.286.00:06:33.51#ibcon#*before return 0, iclass 30, count 2 2006.286.00:06:33.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:06:33.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:06:33.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.00:06:33.51#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:33.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:06:33.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:06:33.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:06:33.63#ibcon#enter wrdev, iclass 30, count 0 2006.286.00:06:33.63#ibcon#first serial, iclass 30, count 0 2006.286.00:06:33.63#ibcon#enter sib2, iclass 30, count 0 2006.286.00:06:33.63#ibcon#flushed, iclass 30, count 0 2006.286.00:06:33.63#ibcon#about to write, iclass 30, count 0 2006.286.00:06:33.63#ibcon#wrote, iclass 30, count 0 2006.286.00:06:33.63#ibcon#about to read 3, iclass 30, count 0 2006.286.00:06:33.65#ibcon#read 3, iclass 30, count 0 2006.286.00:06:33.65#ibcon#about to read 4, iclass 30, count 0 2006.286.00:06:33.65#ibcon#read 4, iclass 30, count 0 2006.286.00:06:33.65#ibcon#about to read 5, iclass 30, count 0 2006.286.00:06:33.65#ibcon#read 5, iclass 30, count 0 2006.286.00:06:33.65#ibcon#about to read 6, iclass 30, count 0 2006.286.00:06:33.65#ibcon#read 6, iclass 30, count 0 2006.286.00:06:33.65#ibcon#end of sib2, iclass 30, count 0 2006.286.00:06:33.65#ibcon#*mode == 0, iclass 30, count 0 2006.286.00:06:33.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.00:06:33.65#ibcon#[27=USB\r\n] 2006.286.00:06:33.65#ibcon#*before write, iclass 30, count 0 2006.286.00:06:33.65#ibcon#enter sib2, iclass 30, count 0 2006.286.00:06:33.65#ibcon#flushed, iclass 30, count 0 2006.286.00:06:33.65#ibcon#about to write, iclass 30, count 0 2006.286.00:06:33.65#ibcon#wrote, iclass 30, count 0 2006.286.00:06:33.65#ibcon#about to read 3, iclass 30, count 0 2006.286.00:06:33.68#ibcon#read 3, iclass 30, count 0 2006.286.00:06:33.68#ibcon#about to read 4, iclass 30, count 0 2006.286.00:06:33.68#ibcon#read 4, iclass 30, count 0 2006.286.00:06:33.68#ibcon#about to read 5, iclass 30, count 0 2006.286.00:06:33.68#ibcon#read 5, iclass 30, count 0 2006.286.00:06:33.68#ibcon#about to read 6, iclass 30, count 0 2006.286.00:06:33.68#ibcon#read 6, iclass 30, count 0 2006.286.00:06:33.68#ibcon#end of sib2, iclass 30, count 0 2006.286.00:06:33.68#ibcon#*after write, iclass 30, count 0 2006.286.00:06:33.68#ibcon#*before return 0, iclass 30, count 0 2006.286.00:06:33.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:06:33.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:06:33.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.00:06:33.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.00:06:33.68$vck44/vblo=4,679.99 2006.286.00:06:33.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.00:06:33.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.00:06:33.68#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:33.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:06:33.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:06:33.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:06:33.68#ibcon#enter wrdev, iclass 32, count 0 2006.286.00:06:33.68#ibcon#first serial, iclass 32, count 0 2006.286.00:06:33.68#ibcon#enter sib2, iclass 32, count 0 2006.286.00:06:33.68#ibcon#flushed, iclass 32, count 0 2006.286.00:06:33.68#ibcon#about to write, iclass 32, count 0 2006.286.00:06:33.68#ibcon#wrote, iclass 32, count 0 2006.286.00:06:33.68#ibcon#about to read 3, iclass 32, count 0 2006.286.00:06:33.70#ibcon#read 3, iclass 32, count 0 2006.286.00:06:33.70#ibcon#about to read 4, iclass 32, count 0 2006.286.00:06:33.70#ibcon#read 4, iclass 32, count 0 2006.286.00:06:33.70#ibcon#about to read 5, iclass 32, count 0 2006.286.00:06:33.70#ibcon#read 5, iclass 32, count 0 2006.286.00:06:33.70#ibcon#about to read 6, iclass 32, count 0 2006.286.00:06:33.70#ibcon#read 6, iclass 32, count 0 2006.286.00:06:33.70#ibcon#end of sib2, iclass 32, count 0 2006.286.00:06:33.70#ibcon#*mode == 0, iclass 32, count 0 2006.286.00:06:33.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.00:06:33.70#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.00:06:33.70#ibcon#*before write, iclass 32, count 0 2006.286.00:06:33.70#ibcon#enter sib2, iclass 32, count 0 2006.286.00:06:33.70#ibcon#flushed, iclass 32, count 0 2006.286.00:06:33.70#ibcon#about to write, iclass 32, count 0 2006.286.00:06:33.70#ibcon#wrote, iclass 32, count 0 2006.286.00:06:33.70#ibcon#about to read 3, iclass 32, count 0 2006.286.00:06:33.74#ibcon#read 3, iclass 32, count 0 2006.286.00:06:33.74#ibcon#about to read 4, iclass 32, count 0 2006.286.00:06:33.74#ibcon#read 4, iclass 32, count 0 2006.286.00:06:33.74#ibcon#about to read 5, iclass 32, count 0 2006.286.00:06:33.74#ibcon#read 5, iclass 32, count 0 2006.286.00:06:33.74#ibcon#about to read 6, iclass 32, count 0 2006.286.00:06:33.74#ibcon#read 6, iclass 32, count 0 2006.286.00:06:33.74#ibcon#end of sib2, iclass 32, count 0 2006.286.00:06:33.74#ibcon#*after write, iclass 32, count 0 2006.286.00:06:33.74#ibcon#*before return 0, iclass 32, count 0 2006.286.00:06:33.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:06:33.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:06:33.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.00:06:33.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.00:06:33.74$vck44/vb=4,5 2006.286.00:06:33.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.00:06:33.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.00:06:33.74#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:33.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:06:33.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:06:33.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:06:33.80#ibcon#enter wrdev, iclass 34, count 2 2006.286.00:06:33.80#ibcon#first serial, iclass 34, count 2 2006.286.00:06:33.80#ibcon#enter sib2, iclass 34, count 2 2006.286.00:06:33.80#ibcon#flushed, iclass 34, count 2 2006.286.00:06:33.80#ibcon#about to write, iclass 34, count 2 2006.286.00:06:33.80#ibcon#wrote, iclass 34, count 2 2006.286.00:06:33.80#ibcon#about to read 3, iclass 34, count 2 2006.286.00:06:33.82#ibcon#read 3, iclass 34, count 2 2006.286.00:06:33.82#ibcon#about to read 4, iclass 34, count 2 2006.286.00:06:33.82#ibcon#read 4, iclass 34, count 2 2006.286.00:06:33.82#ibcon#about to read 5, iclass 34, count 2 2006.286.00:06:33.82#ibcon#read 5, iclass 34, count 2 2006.286.00:06:33.82#ibcon#about to read 6, iclass 34, count 2 2006.286.00:06:33.82#ibcon#read 6, iclass 34, count 2 2006.286.00:06:33.82#ibcon#end of sib2, iclass 34, count 2 2006.286.00:06:33.82#ibcon#*mode == 0, iclass 34, count 2 2006.286.00:06:33.82#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.00:06:33.82#ibcon#[27=AT04-05\r\n] 2006.286.00:06:33.82#ibcon#*before write, iclass 34, count 2 2006.286.00:06:33.82#ibcon#enter sib2, iclass 34, count 2 2006.286.00:06:33.82#ibcon#flushed, iclass 34, count 2 2006.286.00:06:33.82#ibcon#about to write, iclass 34, count 2 2006.286.00:06:33.82#ibcon#wrote, iclass 34, count 2 2006.286.00:06:33.82#ibcon#about to read 3, iclass 34, count 2 2006.286.00:06:33.85#ibcon#read 3, iclass 34, count 2 2006.286.00:06:33.85#ibcon#about to read 4, iclass 34, count 2 2006.286.00:06:33.85#ibcon#read 4, iclass 34, count 2 2006.286.00:06:33.85#ibcon#about to read 5, iclass 34, count 2 2006.286.00:06:33.85#ibcon#read 5, iclass 34, count 2 2006.286.00:06:33.85#ibcon#about to read 6, iclass 34, count 2 2006.286.00:06:33.85#ibcon#read 6, iclass 34, count 2 2006.286.00:06:33.85#ibcon#end of sib2, iclass 34, count 2 2006.286.00:06:33.85#ibcon#*after write, iclass 34, count 2 2006.286.00:06:33.85#ibcon#*before return 0, iclass 34, count 2 2006.286.00:06:33.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:06:33.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:06:33.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.00:06:33.85#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:33.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:06:33.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:06:33.97#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:06:33.97#ibcon#enter wrdev, iclass 34, count 0 2006.286.00:06:33.97#ibcon#first serial, iclass 34, count 0 2006.286.00:06:33.97#ibcon#enter sib2, iclass 34, count 0 2006.286.00:06:33.97#ibcon#flushed, iclass 34, count 0 2006.286.00:06:33.97#ibcon#about to write, iclass 34, count 0 2006.286.00:06:33.97#ibcon#wrote, iclass 34, count 0 2006.286.00:06:33.97#ibcon#about to read 3, iclass 34, count 0 2006.286.00:06:33.99#ibcon#read 3, iclass 34, count 0 2006.286.00:06:33.99#ibcon#about to read 4, iclass 34, count 0 2006.286.00:06:33.99#ibcon#read 4, iclass 34, count 0 2006.286.00:06:33.99#ibcon#about to read 5, iclass 34, count 0 2006.286.00:06:33.99#ibcon#read 5, iclass 34, count 0 2006.286.00:06:33.99#ibcon#about to read 6, iclass 34, count 0 2006.286.00:06:33.99#ibcon#read 6, iclass 34, count 0 2006.286.00:06:33.99#ibcon#end of sib2, iclass 34, count 0 2006.286.00:06:33.99#ibcon#*mode == 0, iclass 34, count 0 2006.286.00:06:33.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.00:06:33.99#ibcon#[27=USB\r\n] 2006.286.00:06:33.99#ibcon#*before write, iclass 34, count 0 2006.286.00:06:33.99#ibcon#enter sib2, iclass 34, count 0 2006.286.00:06:33.99#ibcon#flushed, iclass 34, count 0 2006.286.00:06:33.99#ibcon#about to write, iclass 34, count 0 2006.286.00:06:33.99#ibcon#wrote, iclass 34, count 0 2006.286.00:06:33.99#ibcon#about to read 3, iclass 34, count 0 2006.286.00:06:34.02#ibcon#read 3, iclass 34, count 0 2006.286.00:06:34.02#ibcon#about to read 4, iclass 34, count 0 2006.286.00:06:34.02#ibcon#read 4, iclass 34, count 0 2006.286.00:06:34.02#ibcon#about to read 5, iclass 34, count 0 2006.286.00:06:34.02#ibcon#read 5, iclass 34, count 0 2006.286.00:06:34.02#ibcon#about to read 6, iclass 34, count 0 2006.286.00:06:34.02#ibcon#read 6, iclass 34, count 0 2006.286.00:06:34.02#ibcon#end of sib2, iclass 34, count 0 2006.286.00:06:34.02#ibcon#*after write, iclass 34, count 0 2006.286.00:06:34.02#ibcon#*before return 0, iclass 34, count 0 2006.286.00:06:34.02#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:06:34.02#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:06:34.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.00:06:34.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.00:06:34.02$vck44/vblo=5,709.99 2006.286.00:06:34.02#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.00:06:34.02#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.00:06:34.02#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:34.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:06:34.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:06:34.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:06:34.02#ibcon#enter wrdev, iclass 36, count 0 2006.286.00:06:34.02#ibcon#first serial, iclass 36, count 0 2006.286.00:06:34.02#ibcon#enter sib2, iclass 36, count 0 2006.286.00:06:34.02#ibcon#flushed, iclass 36, count 0 2006.286.00:06:34.02#ibcon#about to write, iclass 36, count 0 2006.286.00:06:34.02#ibcon#wrote, iclass 36, count 0 2006.286.00:06:34.02#ibcon#about to read 3, iclass 36, count 0 2006.286.00:06:34.04#ibcon#read 3, iclass 36, count 0 2006.286.00:06:34.04#ibcon#about to read 4, iclass 36, count 0 2006.286.00:06:34.04#ibcon#read 4, iclass 36, count 0 2006.286.00:06:34.04#ibcon#about to read 5, iclass 36, count 0 2006.286.00:06:34.04#ibcon#read 5, iclass 36, count 0 2006.286.00:06:34.04#ibcon#about to read 6, iclass 36, count 0 2006.286.00:06:34.04#ibcon#read 6, iclass 36, count 0 2006.286.00:06:34.04#ibcon#end of sib2, iclass 36, count 0 2006.286.00:06:34.04#ibcon#*mode == 0, iclass 36, count 0 2006.286.00:06:34.04#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.00:06:34.04#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.00:06:34.04#ibcon#*before write, iclass 36, count 0 2006.286.00:06:34.04#ibcon#enter sib2, iclass 36, count 0 2006.286.00:06:34.04#ibcon#flushed, iclass 36, count 0 2006.286.00:06:34.04#ibcon#about to write, iclass 36, count 0 2006.286.00:06:34.04#ibcon#wrote, iclass 36, count 0 2006.286.00:06:34.04#ibcon#about to read 3, iclass 36, count 0 2006.286.00:06:34.08#ibcon#read 3, iclass 36, count 0 2006.286.00:06:34.08#ibcon#about to read 4, iclass 36, count 0 2006.286.00:06:34.08#ibcon#read 4, iclass 36, count 0 2006.286.00:06:34.08#ibcon#about to read 5, iclass 36, count 0 2006.286.00:06:34.08#ibcon#read 5, iclass 36, count 0 2006.286.00:06:34.08#ibcon#about to read 6, iclass 36, count 0 2006.286.00:06:34.08#ibcon#read 6, iclass 36, count 0 2006.286.00:06:34.08#ibcon#end of sib2, iclass 36, count 0 2006.286.00:06:34.08#ibcon#*after write, iclass 36, count 0 2006.286.00:06:34.08#ibcon#*before return 0, iclass 36, count 0 2006.286.00:06:34.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:06:34.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:06:34.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.00:06:34.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.00:06:34.08$vck44/vb=5,4 2006.286.00:06:34.08#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.00:06:34.08#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.00:06:34.08#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:34.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:06:34.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:06:34.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:06:34.14#ibcon#enter wrdev, iclass 38, count 2 2006.286.00:06:34.14#ibcon#first serial, iclass 38, count 2 2006.286.00:06:34.14#ibcon#enter sib2, iclass 38, count 2 2006.286.00:06:34.14#ibcon#flushed, iclass 38, count 2 2006.286.00:06:34.14#ibcon#about to write, iclass 38, count 2 2006.286.00:06:34.14#ibcon#wrote, iclass 38, count 2 2006.286.00:06:34.14#ibcon#about to read 3, iclass 38, count 2 2006.286.00:06:34.16#ibcon#read 3, iclass 38, count 2 2006.286.00:06:34.16#ibcon#about to read 4, iclass 38, count 2 2006.286.00:06:34.16#ibcon#read 4, iclass 38, count 2 2006.286.00:06:34.16#ibcon#about to read 5, iclass 38, count 2 2006.286.00:06:34.16#ibcon#read 5, iclass 38, count 2 2006.286.00:06:34.16#ibcon#about to read 6, iclass 38, count 2 2006.286.00:06:34.16#ibcon#read 6, iclass 38, count 2 2006.286.00:06:34.16#ibcon#end of sib2, iclass 38, count 2 2006.286.00:06:34.16#ibcon#*mode == 0, iclass 38, count 2 2006.286.00:06:34.16#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.00:06:34.16#ibcon#[27=AT05-04\r\n] 2006.286.00:06:34.16#ibcon#*before write, iclass 38, count 2 2006.286.00:06:34.16#ibcon#enter sib2, iclass 38, count 2 2006.286.00:06:34.16#ibcon#flushed, iclass 38, count 2 2006.286.00:06:34.16#ibcon#about to write, iclass 38, count 2 2006.286.00:06:34.16#ibcon#wrote, iclass 38, count 2 2006.286.00:06:34.16#ibcon#about to read 3, iclass 38, count 2 2006.286.00:06:34.19#ibcon#read 3, iclass 38, count 2 2006.286.00:06:34.19#ibcon#about to read 4, iclass 38, count 2 2006.286.00:06:34.19#ibcon#read 4, iclass 38, count 2 2006.286.00:06:34.19#ibcon#about to read 5, iclass 38, count 2 2006.286.00:06:34.19#ibcon#read 5, iclass 38, count 2 2006.286.00:06:34.19#ibcon#about to read 6, iclass 38, count 2 2006.286.00:06:34.19#ibcon#read 6, iclass 38, count 2 2006.286.00:06:34.19#ibcon#end of sib2, iclass 38, count 2 2006.286.00:06:34.19#ibcon#*after write, iclass 38, count 2 2006.286.00:06:34.19#ibcon#*before return 0, iclass 38, count 2 2006.286.00:06:34.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:06:34.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:06:34.19#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.00:06:34.19#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:34.19#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:06:34.31#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:06:34.31#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:06:34.31#ibcon#enter wrdev, iclass 38, count 0 2006.286.00:06:34.31#ibcon#first serial, iclass 38, count 0 2006.286.00:06:34.31#ibcon#enter sib2, iclass 38, count 0 2006.286.00:06:34.31#ibcon#flushed, iclass 38, count 0 2006.286.00:06:34.31#ibcon#about to write, iclass 38, count 0 2006.286.00:06:34.31#ibcon#wrote, iclass 38, count 0 2006.286.00:06:34.31#ibcon#about to read 3, iclass 38, count 0 2006.286.00:06:34.33#ibcon#read 3, iclass 38, count 0 2006.286.00:06:34.33#ibcon#about to read 4, iclass 38, count 0 2006.286.00:06:34.33#ibcon#read 4, iclass 38, count 0 2006.286.00:06:34.33#ibcon#about to read 5, iclass 38, count 0 2006.286.00:06:34.33#ibcon#read 5, iclass 38, count 0 2006.286.00:06:34.33#ibcon#about to read 6, iclass 38, count 0 2006.286.00:06:34.33#ibcon#read 6, iclass 38, count 0 2006.286.00:06:34.33#ibcon#end of sib2, iclass 38, count 0 2006.286.00:06:34.33#ibcon#*mode == 0, iclass 38, count 0 2006.286.00:06:34.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.00:06:34.33#ibcon#[27=USB\r\n] 2006.286.00:06:34.33#ibcon#*before write, iclass 38, count 0 2006.286.00:06:34.33#ibcon#enter sib2, iclass 38, count 0 2006.286.00:06:34.33#ibcon#flushed, iclass 38, count 0 2006.286.00:06:34.33#ibcon#about to write, iclass 38, count 0 2006.286.00:06:34.33#ibcon#wrote, iclass 38, count 0 2006.286.00:06:34.33#ibcon#about to read 3, iclass 38, count 0 2006.286.00:06:34.36#ibcon#read 3, iclass 38, count 0 2006.286.00:06:34.36#ibcon#about to read 4, iclass 38, count 0 2006.286.00:06:34.36#ibcon#read 4, iclass 38, count 0 2006.286.00:06:34.36#ibcon#about to read 5, iclass 38, count 0 2006.286.00:06:34.36#ibcon#read 5, iclass 38, count 0 2006.286.00:06:34.36#ibcon#about to read 6, iclass 38, count 0 2006.286.00:06:34.36#ibcon#read 6, iclass 38, count 0 2006.286.00:06:34.36#ibcon#end of sib2, iclass 38, count 0 2006.286.00:06:34.36#ibcon#*after write, iclass 38, count 0 2006.286.00:06:34.36#ibcon#*before return 0, iclass 38, count 0 2006.286.00:06:34.36#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:06:34.36#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:06:34.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.00:06:34.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.00:06:34.36$vck44/vblo=6,719.99 2006.286.00:06:34.36#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.00:06:34.36#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.00:06:34.36#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:34.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:06:34.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:06:34.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:06:34.36#ibcon#enter wrdev, iclass 40, count 0 2006.286.00:06:34.36#ibcon#first serial, iclass 40, count 0 2006.286.00:06:34.36#ibcon#enter sib2, iclass 40, count 0 2006.286.00:06:34.36#ibcon#flushed, iclass 40, count 0 2006.286.00:06:34.36#ibcon#about to write, iclass 40, count 0 2006.286.00:06:34.36#ibcon#wrote, iclass 40, count 0 2006.286.00:06:34.36#ibcon#about to read 3, iclass 40, count 0 2006.286.00:06:34.38#ibcon#read 3, iclass 40, count 0 2006.286.00:06:34.38#ibcon#about to read 4, iclass 40, count 0 2006.286.00:06:34.38#ibcon#read 4, iclass 40, count 0 2006.286.00:06:34.38#ibcon#about to read 5, iclass 40, count 0 2006.286.00:06:34.38#ibcon#read 5, iclass 40, count 0 2006.286.00:06:34.38#ibcon#about to read 6, iclass 40, count 0 2006.286.00:06:34.38#ibcon#read 6, iclass 40, count 0 2006.286.00:06:34.38#ibcon#end of sib2, iclass 40, count 0 2006.286.00:06:34.38#ibcon#*mode == 0, iclass 40, count 0 2006.286.00:06:34.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.00:06:34.38#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.00:06:34.38#ibcon#*before write, iclass 40, count 0 2006.286.00:06:34.38#ibcon#enter sib2, iclass 40, count 0 2006.286.00:06:34.38#ibcon#flushed, iclass 40, count 0 2006.286.00:06:34.38#ibcon#about to write, iclass 40, count 0 2006.286.00:06:34.38#ibcon#wrote, iclass 40, count 0 2006.286.00:06:34.38#ibcon#about to read 3, iclass 40, count 0 2006.286.00:06:34.42#ibcon#read 3, iclass 40, count 0 2006.286.00:06:34.42#ibcon#about to read 4, iclass 40, count 0 2006.286.00:06:34.42#ibcon#read 4, iclass 40, count 0 2006.286.00:06:34.42#ibcon#about to read 5, iclass 40, count 0 2006.286.00:06:34.42#ibcon#read 5, iclass 40, count 0 2006.286.00:06:34.42#ibcon#about to read 6, iclass 40, count 0 2006.286.00:06:34.42#ibcon#read 6, iclass 40, count 0 2006.286.00:06:34.42#ibcon#end of sib2, iclass 40, count 0 2006.286.00:06:34.42#ibcon#*after write, iclass 40, count 0 2006.286.00:06:34.42#ibcon#*before return 0, iclass 40, count 0 2006.286.00:06:34.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:06:34.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:06:34.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.00:06:34.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.00:06:34.42$vck44/vb=6,3 2006.286.00:06:34.42#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.00:06:34.42#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.00:06:34.42#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:34.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:06:34.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:06:34.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:06:34.48#ibcon#enter wrdev, iclass 4, count 2 2006.286.00:06:34.48#ibcon#first serial, iclass 4, count 2 2006.286.00:06:34.48#ibcon#enter sib2, iclass 4, count 2 2006.286.00:06:34.48#ibcon#flushed, iclass 4, count 2 2006.286.00:06:34.48#ibcon#about to write, iclass 4, count 2 2006.286.00:06:34.48#ibcon#wrote, iclass 4, count 2 2006.286.00:06:34.48#ibcon#about to read 3, iclass 4, count 2 2006.286.00:06:34.50#ibcon#read 3, iclass 4, count 2 2006.286.00:06:34.50#ibcon#about to read 4, iclass 4, count 2 2006.286.00:06:34.50#ibcon#read 4, iclass 4, count 2 2006.286.00:06:34.50#ibcon#about to read 5, iclass 4, count 2 2006.286.00:06:34.50#ibcon#read 5, iclass 4, count 2 2006.286.00:06:34.50#ibcon#about to read 6, iclass 4, count 2 2006.286.00:06:34.50#ibcon#read 6, iclass 4, count 2 2006.286.00:06:34.50#ibcon#end of sib2, iclass 4, count 2 2006.286.00:06:34.50#ibcon#*mode == 0, iclass 4, count 2 2006.286.00:06:34.50#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.00:06:34.50#ibcon#[27=AT06-03\r\n] 2006.286.00:06:34.50#ibcon#*before write, iclass 4, count 2 2006.286.00:06:34.50#ibcon#enter sib2, iclass 4, count 2 2006.286.00:06:34.50#ibcon#flushed, iclass 4, count 2 2006.286.00:06:34.50#ibcon#about to write, iclass 4, count 2 2006.286.00:06:34.50#ibcon#wrote, iclass 4, count 2 2006.286.00:06:34.50#ibcon#about to read 3, iclass 4, count 2 2006.286.00:06:34.53#ibcon#read 3, iclass 4, count 2 2006.286.00:06:34.53#ibcon#about to read 4, iclass 4, count 2 2006.286.00:06:34.53#ibcon#read 4, iclass 4, count 2 2006.286.00:06:34.53#ibcon#about to read 5, iclass 4, count 2 2006.286.00:06:34.53#ibcon#read 5, iclass 4, count 2 2006.286.00:06:34.53#ibcon#about to read 6, iclass 4, count 2 2006.286.00:06:34.53#ibcon#read 6, iclass 4, count 2 2006.286.00:06:34.53#ibcon#end of sib2, iclass 4, count 2 2006.286.00:06:34.53#ibcon#*after write, iclass 4, count 2 2006.286.00:06:34.53#ibcon#*before return 0, iclass 4, count 2 2006.286.00:06:34.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:06:34.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:06:34.53#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.00:06:34.53#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:34.53#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:06:34.65#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:06:34.65#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:06:34.65#ibcon#enter wrdev, iclass 4, count 0 2006.286.00:06:34.65#ibcon#first serial, iclass 4, count 0 2006.286.00:06:34.65#ibcon#enter sib2, iclass 4, count 0 2006.286.00:06:34.65#ibcon#flushed, iclass 4, count 0 2006.286.00:06:34.65#ibcon#about to write, iclass 4, count 0 2006.286.00:06:34.65#ibcon#wrote, iclass 4, count 0 2006.286.00:06:34.65#ibcon#about to read 3, iclass 4, count 0 2006.286.00:06:34.67#ibcon#read 3, iclass 4, count 0 2006.286.00:06:34.67#ibcon#about to read 4, iclass 4, count 0 2006.286.00:06:34.67#ibcon#read 4, iclass 4, count 0 2006.286.00:06:34.67#ibcon#about to read 5, iclass 4, count 0 2006.286.00:06:34.67#ibcon#read 5, iclass 4, count 0 2006.286.00:06:34.67#ibcon#about to read 6, iclass 4, count 0 2006.286.00:06:34.67#ibcon#read 6, iclass 4, count 0 2006.286.00:06:34.67#ibcon#end of sib2, iclass 4, count 0 2006.286.00:06:34.67#ibcon#*mode == 0, iclass 4, count 0 2006.286.00:06:34.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.00:06:34.67#ibcon#[27=USB\r\n] 2006.286.00:06:34.67#ibcon#*before write, iclass 4, count 0 2006.286.00:06:34.67#ibcon#enter sib2, iclass 4, count 0 2006.286.00:06:34.67#ibcon#flushed, iclass 4, count 0 2006.286.00:06:34.67#ibcon#about to write, iclass 4, count 0 2006.286.00:06:34.67#ibcon#wrote, iclass 4, count 0 2006.286.00:06:34.67#ibcon#about to read 3, iclass 4, count 0 2006.286.00:06:34.70#ibcon#read 3, iclass 4, count 0 2006.286.00:06:34.70#ibcon#about to read 4, iclass 4, count 0 2006.286.00:06:34.70#ibcon#read 4, iclass 4, count 0 2006.286.00:06:34.70#ibcon#about to read 5, iclass 4, count 0 2006.286.00:06:34.70#ibcon#read 5, iclass 4, count 0 2006.286.00:06:34.70#ibcon#about to read 6, iclass 4, count 0 2006.286.00:06:34.70#ibcon#read 6, iclass 4, count 0 2006.286.00:06:34.70#ibcon#end of sib2, iclass 4, count 0 2006.286.00:06:34.70#ibcon#*after write, iclass 4, count 0 2006.286.00:06:34.70#ibcon#*before return 0, iclass 4, count 0 2006.286.00:06:34.70#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:06:34.70#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:06:34.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.00:06:34.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.00:06:34.70$vck44/vblo=7,734.99 2006.286.00:06:34.70#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.00:06:34.70#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.00:06:34.70#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:34.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:06:34.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:06:34.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:06:34.70#ibcon#enter wrdev, iclass 6, count 0 2006.286.00:06:34.70#ibcon#first serial, iclass 6, count 0 2006.286.00:06:34.70#ibcon#enter sib2, iclass 6, count 0 2006.286.00:06:34.70#ibcon#flushed, iclass 6, count 0 2006.286.00:06:34.70#ibcon#about to write, iclass 6, count 0 2006.286.00:06:34.70#ibcon#wrote, iclass 6, count 0 2006.286.00:06:34.70#ibcon#about to read 3, iclass 6, count 0 2006.286.00:06:34.72#ibcon#read 3, iclass 6, count 0 2006.286.00:06:34.72#ibcon#about to read 4, iclass 6, count 0 2006.286.00:06:34.72#ibcon#read 4, iclass 6, count 0 2006.286.00:06:34.72#ibcon#about to read 5, iclass 6, count 0 2006.286.00:06:34.72#ibcon#read 5, iclass 6, count 0 2006.286.00:06:34.72#ibcon#about to read 6, iclass 6, count 0 2006.286.00:06:34.72#ibcon#read 6, iclass 6, count 0 2006.286.00:06:34.72#ibcon#end of sib2, iclass 6, count 0 2006.286.00:06:34.72#ibcon#*mode == 0, iclass 6, count 0 2006.286.00:06:34.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.00:06:34.72#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.00:06:34.72#ibcon#*before write, iclass 6, count 0 2006.286.00:06:34.72#ibcon#enter sib2, iclass 6, count 0 2006.286.00:06:34.72#ibcon#flushed, iclass 6, count 0 2006.286.00:06:34.72#ibcon#about to write, iclass 6, count 0 2006.286.00:06:34.72#ibcon#wrote, iclass 6, count 0 2006.286.00:06:34.72#ibcon#about to read 3, iclass 6, count 0 2006.286.00:06:34.76#ibcon#read 3, iclass 6, count 0 2006.286.00:06:34.76#ibcon#about to read 4, iclass 6, count 0 2006.286.00:06:34.76#ibcon#read 4, iclass 6, count 0 2006.286.00:06:34.76#ibcon#about to read 5, iclass 6, count 0 2006.286.00:06:34.76#ibcon#read 5, iclass 6, count 0 2006.286.00:06:34.76#ibcon#about to read 6, iclass 6, count 0 2006.286.00:06:34.76#ibcon#read 6, iclass 6, count 0 2006.286.00:06:34.76#ibcon#end of sib2, iclass 6, count 0 2006.286.00:06:34.76#ibcon#*after write, iclass 6, count 0 2006.286.00:06:34.76#ibcon#*before return 0, iclass 6, count 0 2006.286.00:06:34.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:06:34.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:06:34.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.00:06:34.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.00:06:34.76$vck44/vb=7,4 2006.286.00:06:34.76#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.00:06:34.76#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.00:06:34.76#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:34.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:06:34.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:06:34.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:06:34.82#ibcon#enter wrdev, iclass 10, count 2 2006.286.00:06:34.82#ibcon#first serial, iclass 10, count 2 2006.286.00:06:34.82#ibcon#enter sib2, iclass 10, count 2 2006.286.00:06:34.82#ibcon#flushed, iclass 10, count 2 2006.286.00:06:34.82#ibcon#about to write, iclass 10, count 2 2006.286.00:06:34.82#ibcon#wrote, iclass 10, count 2 2006.286.00:06:34.82#ibcon#about to read 3, iclass 10, count 2 2006.286.00:06:34.84#ibcon#read 3, iclass 10, count 2 2006.286.00:06:34.84#ibcon#about to read 4, iclass 10, count 2 2006.286.00:06:34.84#ibcon#read 4, iclass 10, count 2 2006.286.00:06:34.84#ibcon#about to read 5, iclass 10, count 2 2006.286.00:06:34.84#ibcon#read 5, iclass 10, count 2 2006.286.00:06:34.84#ibcon#about to read 6, iclass 10, count 2 2006.286.00:06:34.84#ibcon#read 6, iclass 10, count 2 2006.286.00:06:34.84#ibcon#end of sib2, iclass 10, count 2 2006.286.00:06:34.84#ibcon#*mode == 0, iclass 10, count 2 2006.286.00:06:34.84#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.00:06:34.84#ibcon#[27=AT07-04\r\n] 2006.286.00:06:34.84#ibcon#*before write, iclass 10, count 2 2006.286.00:06:34.84#ibcon#enter sib2, iclass 10, count 2 2006.286.00:06:34.84#ibcon#flushed, iclass 10, count 2 2006.286.00:06:34.84#ibcon#about to write, iclass 10, count 2 2006.286.00:06:34.84#ibcon#wrote, iclass 10, count 2 2006.286.00:06:34.84#ibcon#about to read 3, iclass 10, count 2 2006.286.00:06:34.87#ibcon#read 3, iclass 10, count 2 2006.286.00:06:34.87#ibcon#about to read 4, iclass 10, count 2 2006.286.00:06:34.87#ibcon#read 4, iclass 10, count 2 2006.286.00:06:34.87#ibcon#about to read 5, iclass 10, count 2 2006.286.00:06:34.87#ibcon#read 5, iclass 10, count 2 2006.286.00:06:34.87#ibcon#about to read 6, iclass 10, count 2 2006.286.00:06:34.87#ibcon#read 6, iclass 10, count 2 2006.286.00:06:34.87#ibcon#end of sib2, iclass 10, count 2 2006.286.00:06:34.87#ibcon#*after write, iclass 10, count 2 2006.286.00:06:34.87#ibcon#*before return 0, iclass 10, count 2 2006.286.00:06:34.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:06:34.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:06:34.87#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.00:06:34.87#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:34.87#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:06:34.99#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:06:34.99#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:06:34.99#ibcon#enter wrdev, iclass 10, count 0 2006.286.00:06:34.99#ibcon#first serial, iclass 10, count 0 2006.286.00:06:34.99#ibcon#enter sib2, iclass 10, count 0 2006.286.00:06:34.99#ibcon#flushed, iclass 10, count 0 2006.286.00:06:34.99#ibcon#about to write, iclass 10, count 0 2006.286.00:06:34.99#ibcon#wrote, iclass 10, count 0 2006.286.00:06:34.99#ibcon#about to read 3, iclass 10, count 0 2006.286.00:06:35.01#ibcon#read 3, iclass 10, count 0 2006.286.00:06:35.01#ibcon#about to read 4, iclass 10, count 0 2006.286.00:06:35.01#ibcon#read 4, iclass 10, count 0 2006.286.00:06:35.01#ibcon#about to read 5, iclass 10, count 0 2006.286.00:06:35.01#ibcon#read 5, iclass 10, count 0 2006.286.00:06:35.01#ibcon#about to read 6, iclass 10, count 0 2006.286.00:06:35.01#ibcon#read 6, iclass 10, count 0 2006.286.00:06:35.01#ibcon#end of sib2, iclass 10, count 0 2006.286.00:06:35.01#ibcon#*mode == 0, iclass 10, count 0 2006.286.00:06:35.01#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.00:06:35.01#ibcon#[27=USB\r\n] 2006.286.00:06:35.01#ibcon#*before write, iclass 10, count 0 2006.286.00:06:35.01#ibcon#enter sib2, iclass 10, count 0 2006.286.00:06:35.01#ibcon#flushed, iclass 10, count 0 2006.286.00:06:35.01#ibcon#about to write, iclass 10, count 0 2006.286.00:06:35.01#ibcon#wrote, iclass 10, count 0 2006.286.00:06:35.01#ibcon#about to read 3, iclass 10, count 0 2006.286.00:06:35.04#ibcon#read 3, iclass 10, count 0 2006.286.00:06:35.04#ibcon#about to read 4, iclass 10, count 0 2006.286.00:06:35.04#ibcon#read 4, iclass 10, count 0 2006.286.00:06:35.04#ibcon#about to read 5, iclass 10, count 0 2006.286.00:06:35.04#ibcon#read 5, iclass 10, count 0 2006.286.00:06:35.04#ibcon#about to read 6, iclass 10, count 0 2006.286.00:06:35.04#ibcon#read 6, iclass 10, count 0 2006.286.00:06:35.04#ibcon#end of sib2, iclass 10, count 0 2006.286.00:06:35.04#ibcon#*after write, iclass 10, count 0 2006.286.00:06:35.04#ibcon#*before return 0, iclass 10, count 0 2006.286.00:06:35.04#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:06:35.04#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:06:35.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.00:06:35.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.00:06:35.04$vck44/vblo=8,744.99 2006.286.00:06:35.04#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.00:06:35.04#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.00:06:35.04#ibcon#ireg 17 cls_cnt 0 2006.286.00:06:35.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:06:35.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:06:35.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:06:35.04#ibcon#enter wrdev, iclass 12, count 0 2006.286.00:06:35.04#ibcon#first serial, iclass 12, count 0 2006.286.00:06:35.04#ibcon#enter sib2, iclass 12, count 0 2006.286.00:06:35.04#ibcon#flushed, iclass 12, count 0 2006.286.00:06:35.04#ibcon#about to write, iclass 12, count 0 2006.286.00:06:35.04#ibcon#wrote, iclass 12, count 0 2006.286.00:06:35.04#ibcon#about to read 3, iclass 12, count 0 2006.286.00:06:35.06#ibcon#read 3, iclass 12, count 0 2006.286.00:06:35.06#ibcon#about to read 4, iclass 12, count 0 2006.286.00:06:35.06#ibcon#read 4, iclass 12, count 0 2006.286.00:06:35.06#ibcon#about to read 5, iclass 12, count 0 2006.286.00:06:35.06#ibcon#read 5, iclass 12, count 0 2006.286.00:06:35.06#ibcon#about to read 6, iclass 12, count 0 2006.286.00:06:35.06#ibcon#read 6, iclass 12, count 0 2006.286.00:06:35.06#ibcon#end of sib2, iclass 12, count 0 2006.286.00:06:35.06#ibcon#*mode == 0, iclass 12, count 0 2006.286.00:06:35.06#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.00:06:35.06#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.00:06:35.06#ibcon#*before write, iclass 12, count 0 2006.286.00:06:35.06#ibcon#enter sib2, iclass 12, count 0 2006.286.00:06:35.06#ibcon#flushed, iclass 12, count 0 2006.286.00:06:35.06#ibcon#about to write, iclass 12, count 0 2006.286.00:06:35.06#ibcon#wrote, iclass 12, count 0 2006.286.00:06:35.06#ibcon#about to read 3, iclass 12, count 0 2006.286.00:06:35.10#ibcon#read 3, iclass 12, count 0 2006.286.00:06:35.10#ibcon#about to read 4, iclass 12, count 0 2006.286.00:06:35.10#ibcon#read 4, iclass 12, count 0 2006.286.00:06:35.10#ibcon#about to read 5, iclass 12, count 0 2006.286.00:06:35.10#ibcon#read 5, iclass 12, count 0 2006.286.00:06:35.10#ibcon#about to read 6, iclass 12, count 0 2006.286.00:06:35.10#ibcon#read 6, iclass 12, count 0 2006.286.00:06:35.10#ibcon#end of sib2, iclass 12, count 0 2006.286.00:06:35.10#ibcon#*after write, iclass 12, count 0 2006.286.00:06:35.10#ibcon#*before return 0, iclass 12, count 0 2006.286.00:06:35.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:06:35.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:06:35.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.00:06:35.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.00:06:35.10$vck44/vb=8,4 2006.286.00:06:35.10#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.00:06:35.10#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.00:06:35.10#ibcon#ireg 11 cls_cnt 2 2006.286.00:06:35.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:06:35.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:06:35.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:06:35.16#ibcon#enter wrdev, iclass 14, count 2 2006.286.00:06:35.16#ibcon#first serial, iclass 14, count 2 2006.286.00:06:35.16#ibcon#enter sib2, iclass 14, count 2 2006.286.00:06:35.16#ibcon#flushed, iclass 14, count 2 2006.286.00:06:35.16#ibcon#about to write, iclass 14, count 2 2006.286.00:06:35.16#ibcon#wrote, iclass 14, count 2 2006.286.00:06:35.16#ibcon#about to read 3, iclass 14, count 2 2006.286.00:06:35.18#ibcon#read 3, iclass 14, count 2 2006.286.00:06:35.18#ibcon#about to read 4, iclass 14, count 2 2006.286.00:06:35.18#ibcon#read 4, iclass 14, count 2 2006.286.00:06:35.18#ibcon#about to read 5, iclass 14, count 2 2006.286.00:06:35.18#ibcon#read 5, iclass 14, count 2 2006.286.00:06:35.18#ibcon#about to read 6, iclass 14, count 2 2006.286.00:06:35.18#ibcon#read 6, iclass 14, count 2 2006.286.00:06:35.18#ibcon#end of sib2, iclass 14, count 2 2006.286.00:06:35.18#ibcon#*mode == 0, iclass 14, count 2 2006.286.00:06:35.18#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.00:06:35.18#ibcon#[27=AT08-04\r\n] 2006.286.00:06:35.18#ibcon#*before write, iclass 14, count 2 2006.286.00:06:35.18#ibcon#enter sib2, iclass 14, count 2 2006.286.00:06:35.18#ibcon#flushed, iclass 14, count 2 2006.286.00:06:35.18#ibcon#about to write, iclass 14, count 2 2006.286.00:06:35.18#ibcon#wrote, iclass 14, count 2 2006.286.00:06:35.18#ibcon#about to read 3, iclass 14, count 2 2006.286.00:06:35.21#ibcon#read 3, iclass 14, count 2 2006.286.00:06:35.21#ibcon#about to read 4, iclass 14, count 2 2006.286.00:06:35.21#ibcon#read 4, iclass 14, count 2 2006.286.00:06:35.21#ibcon#about to read 5, iclass 14, count 2 2006.286.00:06:35.21#ibcon#read 5, iclass 14, count 2 2006.286.00:06:35.21#ibcon#about to read 6, iclass 14, count 2 2006.286.00:06:35.21#ibcon#read 6, iclass 14, count 2 2006.286.00:06:35.21#ibcon#end of sib2, iclass 14, count 2 2006.286.00:06:35.21#ibcon#*after write, iclass 14, count 2 2006.286.00:06:35.21#ibcon#*before return 0, iclass 14, count 2 2006.286.00:06:35.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:06:35.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:06:35.21#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.00:06:35.21#ibcon#ireg 7 cls_cnt 0 2006.286.00:06:35.21#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:06:35.33#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:06:35.33#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:06:35.33#ibcon#enter wrdev, iclass 14, count 0 2006.286.00:06:35.33#ibcon#first serial, iclass 14, count 0 2006.286.00:06:35.33#ibcon#enter sib2, iclass 14, count 0 2006.286.00:06:35.33#ibcon#flushed, iclass 14, count 0 2006.286.00:06:35.33#ibcon#about to write, iclass 14, count 0 2006.286.00:06:35.33#ibcon#wrote, iclass 14, count 0 2006.286.00:06:35.33#ibcon#about to read 3, iclass 14, count 0 2006.286.00:06:35.35#ibcon#read 3, iclass 14, count 0 2006.286.00:06:35.35#ibcon#about to read 4, iclass 14, count 0 2006.286.00:06:35.35#ibcon#read 4, iclass 14, count 0 2006.286.00:06:35.35#ibcon#about to read 5, iclass 14, count 0 2006.286.00:06:35.35#ibcon#read 5, iclass 14, count 0 2006.286.00:06:35.35#ibcon#about to read 6, iclass 14, count 0 2006.286.00:06:35.35#ibcon#read 6, iclass 14, count 0 2006.286.00:06:35.35#ibcon#end of sib2, iclass 14, count 0 2006.286.00:06:35.35#ibcon#*mode == 0, iclass 14, count 0 2006.286.00:06:35.35#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.00:06:35.35#ibcon#[27=USB\r\n] 2006.286.00:06:35.35#ibcon#*before write, iclass 14, count 0 2006.286.00:06:35.35#ibcon#enter sib2, iclass 14, count 0 2006.286.00:06:35.35#ibcon#flushed, iclass 14, count 0 2006.286.00:06:35.35#ibcon#about to write, iclass 14, count 0 2006.286.00:06:35.35#ibcon#wrote, iclass 14, count 0 2006.286.00:06:35.35#ibcon#about to read 3, iclass 14, count 0 2006.286.00:06:35.38#ibcon#read 3, iclass 14, count 0 2006.286.00:06:35.38#ibcon#about to read 4, iclass 14, count 0 2006.286.00:06:35.38#ibcon#read 4, iclass 14, count 0 2006.286.00:06:35.38#ibcon#about to read 5, iclass 14, count 0 2006.286.00:06:35.38#ibcon#read 5, iclass 14, count 0 2006.286.00:06:35.38#ibcon#about to read 6, iclass 14, count 0 2006.286.00:06:35.38#ibcon#read 6, iclass 14, count 0 2006.286.00:06:35.38#ibcon#end of sib2, iclass 14, count 0 2006.286.00:06:35.38#ibcon#*after write, iclass 14, count 0 2006.286.00:06:35.38#ibcon#*before return 0, iclass 14, count 0 2006.286.00:06:35.38#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:06:35.38#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:06:35.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.00:06:35.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.00:06:35.38$vck44/vabw=wide 2006.286.00:06:35.38#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.00:06:35.38#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.00:06:35.38#ibcon#ireg 8 cls_cnt 0 2006.286.00:06:35.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:06:35.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:06:35.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:06:35.38#ibcon#enter wrdev, iclass 16, count 0 2006.286.00:06:35.38#ibcon#first serial, iclass 16, count 0 2006.286.00:06:35.38#ibcon#enter sib2, iclass 16, count 0 2006.286.00:06:35.38#ibcon#flushed, iclass 16, count 0 2006.286.00:06:35.38#ibcon#about to write, iclass 16, count 0 2006.286.00:06:35.38#ibcon#wrote, iclass 16, count 0 2006.286.00:06:35.38#ibcon#about to read 3, iclass 16, count 0 2006.286.00:06:35.40#ibcon#read 3, iclass 16, count 0 2006.286.00:06:35.40#ibcon#about to read 4, iclass 16, count 0 2006.286.00:06:35.40#ibcon#read 4, iclass 16, count 0 2006.286.00:06:35.40#ibcon#about to read 5, iclass 16, count 0 2006.286.00:06:35.40#ibcon#read 5, iclass 16, count 0 2006.286.00:06:35.40#ibcon#about to read 6, iclass 16, count 0 2006.286.00:06:35.40#ibcon#read 6, iclass 16, count 0 2006.286.00:06:35.40#ibcon#end of sib2, iclass 16, count 0 2006.286.00:06:35.40#ibcon#*mode == 0, iclass 16, count 0 2006.286.00:06:35.40#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.00:06:35.40#ibcon#[25=BW32\r\n] 2006.286.00:06:35.40#ibcon#*before write, iclass 16, count 0 2006.286.00:06:35.40#ibcon#enter sib2, iclass 16, count 0 2006.286.00:06:35.40#ibcon#flushed, iclass 16, count 0 2006.286.00:06:35.40#ibcon#about to write, iclass 16, count 0 2006.286.00:06:35.40#ibcon#wrote, iclass 16, count 0 2006.286.00:06:35.40#ibcon#about to read 3, iclass 16, count 0 2006.286.00:06:35.43#ibcon#read 3, iclass 16, count 0 2006.286.00:06:35.43#ibcon#about to read 4, iclass 16, count 0 2006.286.00:06:35.43#ibcon#read 4, iclass 16, count 0 2006.286.00:06:35.43#ibcon#about to read 5, iclass 16, count 0 2006.286.00:06:35.43#ibcon#read 5, iclass 16, count 0 2006.286.00:06:35.43#ibcon#about to read 6, iclass 16, count 0 2006.286.00:06:35.43#ibcon#read 6, iclass 16, count 0 2006.286.00:06:35.43#ibcon#end of sib2, iclass 16, count 0 2006.286.00:06:35.43#ibcon#*after write, iclass 16, count 0 2006.286.00:06:35.43#ibcon#*before return 0, iclass 16, count 0 2006.286.00:06:35.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:06:35.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:06:35.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.00:06:35.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.00:06:35.43$vck44/vbbw=wide 2006.286.00:06:35.43#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.00:06:35.43#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.00:06:35.43#ibcon#ireg 8 cls_cnt 0 2006.286.00:06:35.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:06:35.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:06:35.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:06:35.50#ibcon#enter wrdev, iclass 18, count 0 2006.286.00:06:35.50#ibcon#first serial, iclass 18, count 0 2006.286.00:06:35.50#ibcon#enter sib2, iclass 18, count 0 2006.286.00:06:35.50#ibcon#flushed, iclass 18, count 0 2006.286.00:06:35.50#ibcon#about to write, iclass 18, count 0 2006.286.00:06:35.50#ibcon#wrote, iclass 18, count 0 2006.286.00:06:35.50#ibcon#about to read 3, iclass 18, count 0 2006.286.00:06:35.52#ibcon#read 3, iclass 18, count 0 2006.286.00:06:35.52#ibcon#about to read 4, iclass 18, count 0 2006.286.00:06:35.52#ibcon#read 4, iclass 18, count 0 2006.286.00:06:35.52#ibcon#about to read 5, iclass 18, count 0 2006.286.00:06:35.52#ibcon#read 5, iclass 18, count 0 2006.286.00:06:35.52#ibcon#about to read 6, iclass 18, count 0 2006.286.00:06:35.52#ibcon#read 6, iclass 18, count 0 2006.286.00:06:35.52#ibcon#end of sib2, iclass 18, count 0 2006.286.00:06:35.52#ibcon#*mode == 0, iclass 18, count 0 2006.286.00:06:35.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.00:06:35.52#ibcon#[27=BW32\r\n] 2006.286.00:06:35.52#ibcon#*before write, iclass 18, count 0 2006.286.00:06:35.52#ibcon#enter sib2, iclass 18, count 0 2006.286.00:06:35.52#ibcon#flushed, iclass 18, count 0 2006.286.00:06:35.52#ibcon#about to write, iclass 18, count 0 2006.286.00:06:35.52#ibcon#wrote, iclass 18, count 0 2006.286.00:06:35.52#ibcon#about to read 3, iclass 18, count 0 2006.286.00:06:35.55#ibcon#read 3, iclass 18, count 0 2006.286.00:06:35.55#ibcon#about to read 4, iclass 18, count 0 2006.286.00:06:35.55#ibcon#read 4, iclass 18, count 0 2006.286.00:06:35.55#ibcon#about to read 5, iclass 18, count 0 2006.286.00:06:35.55#ibcon#read 5, iclass 18, count 0 2006.286.00:06:35.55#ibcon#about to read 6, iclass 18, count 0 2006.286.00:06:35.55#ibcon#read 6, iclass 18, count 0 2006.286.00:06:35.55#ibcon#end of sib2, iclass 18, count 0 2006.286.00:06:35.55#ibcon#*after write, iclass 18, count 0 2006.286.00:06:35.55#ibcon#*before return 0, iclass 18, count 0 2006.286.00:06:35.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:06:35.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:06:35.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.00:06:35.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.00:06:35.55$setupk4/ifdk4 2006.286.00:06:35.55$ifdk4/lo= 2006.286.00:06:35.55$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.00:06:35.55$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.00:06:35.55$ifdk4/patch= 2006.286.00:06:35.55$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.00:06:35.55$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.00:06:35.55$setupk4/!*+20s 2006.286.00:06:39.10#abcon#<5=/03 3.6 7.2 19.70 871016.4\r\n> 2006.286.00:06:39.12#abcon#{5=INTERFACE CLEAR} 2006.286.00:06:39.18#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:06:49.27#abcon#<5=/03 3.6 7.2 19.70 871016.4\r\n> 2006.286.00:06:49.29#abcon#{5=INTERFACE CLEAR} 2006.286.00:06:49.35#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:06:50.06$setupk4/"tpicd 2006.286.00:06:50.06$setupk4/echo=off 2006.286.00:06:50.06$setupk4/xlog=off 2006.286.00:06:50.06:!2006.286.00:10:22 2006.286.00:07:08.13#trakl#Source acquired 2006.286.00:07:10.13#flagr#flagr/antenna,acquired 2006.286.00:10:22.00:preob 2006.286.00:10:23.14/onsource/TRACKING 2006.286.00:10:23.14:!2006.286.00:10:32 2006.286.00:10:32.00:"tape 2006.286.00:10:32.00:"st=record 2006.286.00:10:32.00:data_valid=on 2006.286.00:10:32.00:midob 2006.286.00:10:32.14/onsource/TRACKING 2006.286.00:10:32.14/wx/19.75,1016.4,87 2006.286.00:10:32.35/cable/+6.5081E-03 2006.286.00:10:33.44/va/01,07,usb,yes,31,34 2006.286.00:10:33.44/va/02,06,usb,yes,32,32 2006.286.00:10:33.44/va/03,07,usb,yes,31,33 2006.286.00:10:33.44/va/04,06,usb,yes,32,34 2006.286.00:10:33.44/va/05,03,usb,yes,32,32 2006.286.00:10:33.44/va/06,04,usb,yes,29,28 2006.286.00:10:33.44/va/07,04,usb,yes,29,30 2006.286.00:10:33.44/va/08,03,usb,yes,30,37 2006.286.00:10:33.67/valo/01,524.99,yes,locked 2006.286.00:10:33.67/valo/02,534.99,yes,locked 2006.286.00:10:33.67/valo/03,564.99,yes,locked 2006.286.00:10:33.67/valo/04,624.99,yes,locked 2006.286.00:10:33.67/valo/05,734.99,yes,locked 2006.286.00:10:33.67/valo/06,814.99,yes,locked 2006.286.00:10:33.67/valo/07,864.99,yes,locked 2006.286.00:10:33.67/valo/08,884.99,yes,locked 2006.286.00:10:34.76/vb/01,04,usb,yes,29,27 2006.286.00:10:34.76/vb/02,05,usb,yes,28,28 2006.286.00:10:34.76/vb/03,04,usb,yes,29,32 2006.286.00:10:34.76/vb/04,05,usb,yes,29,28 2006.286.00:10:34.76/vb/05,04,usb,yes,25,28 2006.286.00:10:34.76/vb/06,03,usb,yes,37,33 2006.286.00:10:34.76/vb/07,04,usb,yes,30,30 2006.286.00:10:34.76/vb/08,04,usb,yes,27,30 2006.286.00:10:34.99/vblo/01,629.99,yes,locked 2006.286.00:10:34.99/vblo/02,634.99,yes,locked 2006.286.00:10:34.99/vblo/03,649.99,yes,locked 2006.286.00:10:34.99/vblo/04,679.99,yes,locked 2006.286.00:10:34.99/vblo/05,709.99,yes,locked 2006.286.00:10:34.99/vblo/06,719.99,yes,locked 2006.286.00:10:34.99/vblo/07,734.99,yes,locked 2006.286.00:10:34.99/vblo/08,744.99,yes,locked 2006.286.00:10:35.14/vabw/8 2006.286.00:10:35.29/vbbw/8 2006.286.00:10:35.38/xfe/off,on,12.0 2006.286.00:10:35.75/ifatt/23,28,28,28 2006.286.00:10:36.08/fmout-gps/S +2.84E-07 2006.286.00:10:36.10:!2006.286.00:15:22 2006.286.00:15:22.00:data_valid=off 2006.286.00:15:22.00:"et 2006.286.00:15:22.00:!+3s 2006.286.00:15:25.01:"tape 2006.286.00:15:25.01:postob 2006.286.00:15:25.16/cable/+6.5063E-03 2006.286.00:15:25.16/wx/19.82,1016.5,86 2006.286.00:15:26.08/fmout-gps/S +2.81E-07 2006.286.00:15:26.08:scan_name=286-0019,jd0610,50 2006.286.00:15:26.08:source=0552+398,055530.81,394849.2,2000.0,cw 2006.286.00:15:27.13#flagr#flagr/antenna,new-source 2006.286.00:15:27.13:checkk5 2006.286.00:15:27.52/chk_autoobs//k5ts1/ autoobs is running! 2006.286.00:15:28.16/chk_autoobs//k5ts2/ autoobs is running! 2006.286.00:15:28.52/chk_autoobs//k5ts3/ autoobs is running! 2006.286.00:15:28.92/chk_autoobs//k5ts4/ autoobs is running! 2006.286.00:15:29.52/chk_obsdata//k5ts1/T2860010??a.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.286.00:15:34.85/chk_obsdata//k5ts2/T2860010??b.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.286.00:15:35.31/chk_obsdata//k5ts3/T2860010??c.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.286.00:15:35.70/chk_obsdata//k5ts4/T2860010??d.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.286.00:15:36.67/k5log//k5ts1_log_newline 2006.286.00:15:37.48/k5log//k5ts2_log_newline 2006.286.00:15:38.59/k5log//k5ts3_log_newline 2006.286.00:15:39.55/k5log//k5ts4_log_newline 2006.286.00:15:39.57/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.00:15:39.57:setupk4=1 2006.286.00:15:39.57$setupk4/echo=on 2006.286.00:15:39.57$setupk4/pcalon 2006.286.00:15:39.57$pcalon/"no phase cal control is implemented here 2006.286.00:15:39.57$setupk4/"tpicd=stop 2006.286.00:15:39.57$setupk4/"rec=synch_on 2006.286.00:15:39.57$setupk4/"rec_mode=128 2006.286.00:15:39.57$setupk4/!* 2006.286.00:15:39.57$setupk4/recpk4 2006.286.00:15:39.57$recpk4/recpatch= 2006.286.00:15:39.57$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.00:15:39.57$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.00:15:39.57$setupk4/vck44 2006.286.00:15:39.57$vck44/valo=1,524.99 2006.286.00:15:39.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.00:15:39.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.00:15:39.58#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:39.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:15:39.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:15:39.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:15:39.58#ibcon#enter wrdev, iclass 23, count 0 2006.286.00:15:39.58#ibcon#first serial, iclass 23, count 0 2006.286.00:15:39.58#ibcon#enter sib2, iclass 23, count 0 2006.286.00:15:39.58#ibcon#flushed, iclass 23, count 0 2006.286.00:15:39.58#ibcon#about to write, iclass 23, count 0 2006.286.00:15:39.58#ibcon#wrote, iclass 23, count 0 2006.286.00:15:39.58#ibcon#about to read 3, iclass 23, count 0 2006.286.00:15:39.60#ibcon#read 3, iclass 23, count 0 2006.286.00:15:39.60#ibcon#about to read 4, iclass 23, count 0 2006.286.00:15:39.60#ibcon#read 4, iclass 23, count 0 2006.286.00:15:39.60#ibcon#about to read 5, iclass 23, count 0 2006.286.00:15:39.60#ibcon#read 5, iclass 23, count 0 2006.286.00:15:39.60#ibcon#about to read 6, iclass 23, count 0 2006.286.00:15:39.60#ibcon#read 6, iclass 23, count 0 2006.286.00:15:39.60#ibcon#end of sib2, iclass 23, count 0 2006.286.00:15:39.60#ibcon#*mode == 0, iclass 23, count 0 2006.286.00:15:39.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.00:15:39.60#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.00:15:39.60#ibcon#*before write, iclass 23, count 0 2006.286.00:15:39.60#ibcon#enter sib2, iclass 23, count 0 2006.286.00:15:39.60#ibcon#flushed, iclass 23, count 0 2006.286.00:15:39.60#ibcon#about to write, iclass 23, count 0 2006.286.00:15:39.60#ibcon#wrote, iclass 23, count 0 2006.286.00:15:39.60#ibcon#about to read 3, iclass 23, count 0 2006.286.00:15:39.65#ibcon#read 3, iclass 23, count 0 2006.286.00:15:39.65#ibcon#about to read 4, iclass 23, count 0 2006.286.00:15:39.65#ibcon#read 4, iclass 23, count 0 2006.286.00:15:39.65#ibcon#about to read 5, iclass 23, count 0 2006.286.00:15:39.65#ibcon#read 5, iclass 23, count 0 2006.286.00:15:39.65#ibcon#about to read 6, iclass 23, count 0 2006.286.00:15:39.65#ibcon#read 6, iclass 23, count 0 2006.286.00:15:39.65#ibcon#end of sib2, iclass 23, count 0 2006.286.00:15:39.65#ibcon#*after write, iclass 23, count 0 2006.286.00:15:39.65#ibcon#*before return 0, iclass 23, count 0 2006.286.00:15:39.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:15:39.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:15:39.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.00:15:39.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.00:15:39.65$vck44/va=1,7 2006.286.00:15:39.65#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.00:15:39.65#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.00:15:39.65#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:39.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:15:39.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:15:39.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:15:39.65#ibcon#enter wrdev, iclass 25, count 2 2006.286.00:15:39.65#ibcon#first serial, iclass 25, count 2 2006.286.00:15:39.65#ibcon#enter sib2, iclass 25, count 2 2006.286.00:15:39.65#ibcon#flushed, iclass 25, count 2 2006.286.00:15:39.65#ibcon#about to write, iclass 25, count 2 2006.286.00:15:39.65#ibcon#wrote, iclass 25, count 2 2006.286.00:15:39.65#ibcon#about to read 3, iclass 25, count 2 2006.286.00:15:39.67#ibcon#read 3, iclass 25, count 2 2006.286.00:15:39.67#ibcon#about to read 4, iclass 25, count 2 2006.286.00:15:39.67#ibcon#read 4, iclass 25, count 2 2006.286.00:15:39.67#ibcon#about to read 5, iclass 25, count 2 2006.286.00:15:39.67#ibcon#read 5, iclass 25, count 2 2006.286.00:15:39.67#ibcon#about to read 6, iclass 25, count 2 2006.286.00:15:39.67#ibcon#read 6, iclass 25, count 2 2006.286.00:15:39.67#ibcon#end of sib2, iclass 25, count 2 2006.286.00:15:39.67#ibcon#*mode == 0, iclass 25, count 2 2006.286.00:15:39.67#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.00:15:39.67#ibcon#[25=AT01-07\r\n] 2006.286.00:15:39.67#ibcon#*before write, iclass 25, count 2 2006.286.00:15:39.67#ibcon#enter sib2, iclass 25, count 2 2006.286.00:15:39.67#ibcon#flushed, iclass 25, count 2 2006.286.00:15:39.67#ibcon#about to write, iclass 25, count 2 2006.286.00:15:39.67#ibcon#wrote, iclass 25, count 2 2006.286.00:15:39.67#ibcon#about to read 3, iclass 25, count 2 2006.286.00:15:39.70#ibcon#read 3, iclass 25, count 2 2006.286.00:15:39.70#ibcon#about to read 4, iclass 25, count 2 2006.286.00:15:39.70#ibcon#read 4, iclass 25, count 2 2006.286.00:15:39.70#ibcon#about to read 5, iclass 25, count 2 2006.286.00:15:39.70#ibcon#read 5, iclass 25, count 2 2006.286.00:15:39.70#ibcon#about to read 6, iclass 25, count 2 2006.286.00:15:39.70#ibcon#read 6, iclass 25, count 2 2006.286.00:15:39.70#ibcon#end of sib2, iclass 25, count 2 2006.286.00:15:39.70#ibcon#*after write, iclass 25, count 2 2006.286.00:15:39.70#ibcon#*before return 0, iclass 25, count 2 2006.286.00:15:39.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:15:39.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:15:39.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.00:15:39.70#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:39.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:15:39.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:15:39.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:15:39.82#ibcon#enter wrdev, iclass 25, count 0 2006.286.00:15:39.82#ibcon#first serial, iclass 25, count 0 2006.286.00:15:39.82#ibcon#enter sib2, iclass 25, count 0 2006.286.00:15:39.82#ibcon#flushed, iclass 25, count 0 2006.286.00:15:39.82#ibcon#about to write, iclass 25, count 0 2006.286.00:15:39.82#ibcon#wrote, iclass 25, count 0 2006.286.00:15:39.82#ibcon#about to read 3, iclass 25, count 0 2006.286.00:15:39.84#ibcon#read 3, iclass 25, count 0 2006.286.00:15:39.84#ibcon#about to read 4, iclass 25, count 0 2006.286.00:15:39.84#ibcon#read 4, iclass 25, count 0 2006.286.00:15:39.84#ibcon#about to read 5, iclass 25, count 0 2006.286.00:15:39.84#ibcon#read 5, iclass 25, count 0 2006.286.00:15:39.84#ibcon#about to read 6, iclass 25, count 0 2006.286.00:15:39.84#ibcon#read 6, iclass 25, count 0 2006.286.00:15:39.84#ibcon#end of sib2, iclass 25, count 0 2006.286.00:15:39.84#ibcon#*mode == 0, iclass 25, count 0 2006.286.00:15:39.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.00:15:39.84#ibcon#[25=USB\r\n] 2006.286.00:15:39.84#ibcon#*before write, iclass 25, count 0 2006.286.00:15:39.84#ibcon#enter sib2, iclass 25, count 0 2006.286.00:15:39.84#ibcon#flushed, iclass 25, count 0 2006.286.00:15:39.84#ibcon#about to write, iclass 25, count 0 2006.286.00:15:39.84#ibcon#wrote, iclass 25, count 0 2006.286.00:15:39.84#ibcon#about to read 3, iclass 25, count 0 2006.286.00:15:39.87#ibcon#read 3, iclass 25, count 0 2006.286.00:15:39.87#ibcon#about to read 4, iclass 25, count 0 2006.286.00:15:39.87#ibcon#read 4, iclass 25, count 0 2006.286.00:15:39.87#ibcon#about to read 5, iclass 25, count 0 2006.286.00:15:39.87#ibcon#read 5, iclass 25, count 0 2006.286.00:15:39.87#ibcon#about to read 6, iclass 25, count 0 2006.286.00:15:39.87#ibcon#read 6, iclass 25, count 0 2006.286.00:15:39.87#ibcon#end of sib2, iclass 25, count 0 2006.286.00:15:39.87#ibcon#*after write, iclass 25, count 0 2006.286.00:15:39.87#ibcon#*before return 0, iclass 25, count 0 2006.286.00:15:39.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:15:39.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:15:39.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.00:15:39.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.00:15:39.87$vck44/valo=2,534.99 2006.286.00:15:39.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.00:15:39.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.00:15:39.87#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:39.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:15:39.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:15:39.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:15:39.87#ibcon#enter wrdev, iclass 27, count 0 2006.286.00:15:39.87#ibcon#first serial, iclass 27, count 0 2006.286.00:15:39.87#ibcon#enter sib2, iclass 27, count 0 2006.286.00:15:39.87#ibcon#flushed, iclass 27, count 0 2006.286.00:15:39.87#ibcon#about to write, iclass 27, count 0 2006.286.00:15:39.87#ibcon#wrote, iclass 27, count 0 2006.286.00:15:39.87#ibcon#about to read 3, iclass 27, count 0 2006.286.00:15:39.89#ibcon#read 3, iclass 27, count 0 2006.286.00:15:39.89#ibcon#about to read 4, iclass 27, count 0 2006.286.00:15:39.89#ibcon#read 4, iclass 27, count 0 2006.286.00:15:39.89#ibcon#about to read 5, iclass 27, count 0 2006.286.00:15:39.89#ibcon#read 5, iclass 27, count 0 2006.286.00:15:39.89#ibcon#about to read 6, iclass 27, count 0 2006.286.00:15:39.89#ibcon#read 6, iclass 27, count 0 2006.286.00:15:39.89#ibcon#end of sib2, iclass 27, count 0 2006.286.00:15:39.89#ibcon#*mode == 0, iclass 27, count 0 2006.286.00:15:39.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.00:15:39.89#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.00:15:39.89#ibcon#*before write, iclass 27, count 0 2006.286.00:15:39.89#ibcon#enter sib2, iclass 27, count 0 2006.286.00:15:39.89#ibcon#flushed, iclass 27, count 0 2006.286.00:15:39.89#ibcon#about to write, iclass 27, count 0 2006.286.00:15:39.89#ibcon#wrote, iclass 27, count 0 2006.286.00:15:39.89#ibcon#about to read 3, iclass 27, count 0 2006.286.00:15:39.93#ibcon#read 3, iclass 27, count 0 2006.286.00:15:39.93#ibcon#about to read 4, iclass 27, count 0 2006.286.00:15:39.93#ibcon#read 4, iclass 27, count 0 2006.286.00:15:39.93#ibcon#about to read 5, iclass 27, count 0 2006.286.00:15:39.93#ibcon#read 5, iclass 27, count 0 2006.286.00:15:39.93#ibcon#about to read 6, iclass 27, count 0 2006.286.00:15:39.93#ibcon#read 6, iclass 27, count 0 2006.286.00:15:39.93#ibcon#end of sib2, iclass 27, count 0 2006.286.00:15:39.93#ibcon#*after write, iclass 27, count 0 2006.286.00:15:39.93#ibcon#*before return 0, iclass 27, count 0 2006.286.00:15:39.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:15:39.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:15:39.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.00:15:39.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.00:15:39.93$vck44/va=2,6 2006.286.00:15:39.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.00:15:39.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.00:15:39.93#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:39.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:15:39.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:15:39.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:15:39.99#ibcon#enter wrdev, iclass 29, count 2 2006.286.00:15:39.99#ibcon#first serial, iclass 29, count 2 2006.286.00:15:39.99#ibcon#enter sib2, iclass 29, count 2 2006.286.00:15:39.99#ibcon#flushed, iclass 29, count 2 2006.286.00:15:39.99#ibcon#about to write, iclass 29, count 2 2006.286.00:15:39.99#ibcon#wrote, iclass 29, count 2 2006.286.00:15:39.99#ibcon#about to read 3, iclass 29, count 2 2006.286.00:15:40.01#ibcon#read 3, iclass 29, count 2 2006.286.00:15:40.01#ibcon#about to read 4, iclass 29, count 2 2006.286.00:15:40.01#ibcon#read 4, iclass 29, count 2 2006.286.00:15:40.01#ibcon#about to read 5, iclass 29, count 2 2006.286.00:15:40.01#ibcon#read 5, iclass 29, count 2 2006.286.00:15:40.01#ibcon#about to read 6, iclass 29, count 2 2006.286.00:15:40.01#ibcon#read 6, iclass 29, count 2 2006.286.00:15:40.01#ibcon#end of sib2, iclass 29, count 2 2006.286.00:15:40.01#ibcon#*mode == 0, iclass 29, count 2 2006.286.00:15:40.01#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.00:15:40.01#ibcon#[25=AT02-06\r\n] 2006.286.00:15:40.01#ibcon#*before write, iclass 29, count 2 2006.286.00:15:40.01#ibcon#enter sib2, iclass 29, count 2 2006.286.00:15:40.01#ibcon#flushed, iclass 29, count 2 2006.286.00:15:40.01#ibcon#about to write, iclass 29, count 2 2006.286.00:15:40.01#ibcon#wrote, iclass 29, count 2 2006.286.00:15:40.01#ibcon#about to read 3, iclass 29, count 2 2006.286.00:15:40.04#ibcon#read 3, iclass 29, count 2 2006.286.00:15:40.04#ibcon#about to read 4, iclass 29, count 2 2006.286.00:15:40.04#ibcon#read 4, iclass 29, count 2 2006.286.00:15:40.04#ibcon#about to read 5, iclass 29, count 2 2006.286.00:15:40.04#ibcon#read 5, iclass 29, count 2 2006.286.00:15:40.04#ibcon#about to read 6, iclass 29, count 2 2006.286.00:15:40.04#ibcon#read 6, iclass 29, count 2 2006.286.00:15:40.04#ibcon#end of sib2, iclass 29, count 2 2006.286.00:15:40.04#ibcon#*after write, iclass 29, count 2 2006.286.00:15:40.04#ibcon#*before return 0, iclass 29, count 2 2006.286.00:15:40.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:15:40.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:15:40.04#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.00:15:40.04#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:40.04#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:15:40.16#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:15:40.16#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:15:40.16#ibcon#enter wrdev, iclass 29, count 0 2006.286.00:15:40.16#ibcon#first serial, iclass 29, count 0 2006.286.00:15:40.16#ibcon#enter sib2, iclass 29, count 0 2006.286.00:15:40.16#ibcon#flushed, iclass 29, count 0 2006.286.00:15:40.16#ibcon#about to write, iclass 29, count 0 2006.286.00:15:40.16#ibcon#wrote, iclass 29, count 0 2006.286.00:15:40.16#ibcon#about to read 3, iclass 29, count 0 2006.286.00:15:40.19#ibcon#read 3, iclass 29, count 0 2006.286.00:15:40.19#ibcon#about to read 4, iclass 29, count 0 2006.286.00:15:40.19#ibcon#read 4, iclass 29, count 0 2006.286.00:15:40.19#ibcon#about to read 5, iclass 29, count 0 2006.286.00:15:40.19#ibcon#read 5, iclass 29, count 0 2006.286.00:15:40.19#ibcon#about to read 6, iclass 29, count 0 2006.286.00:15:40.19#ibcon#read 6, iclass 29, count 0 2006.286.00:15:40.19#ibcon#end of sib2, iclass 29, count 0 2006.286.00:15:40.19#ibcon#*mode == 0, iclass 29, count 0 2006.286.00:15:40.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.00:15:40.19#ibcon#[25=USB\r\n] 2006.286.00:15:40.19#ibcon#*before write, iclass 29, count 0 2006.286.00:15:40.19#ibcon#enter sib2, iclass 29, count 0 2006.286.00:15:40.19#ibcon#flushed, iclass 29, count 0 2006.286.00:15:40.19#ibcon#about to write, iclass 29, count 0 2006.286.00:15:40.19#ibcon#wrote, iclass 29, count 0 2006.286.00:15:40.19#ibcon#about to read 3, iclass 29, count 0 2006.286.00:15:40.22#ibcon#read 3, iclass 29, count 0 2006.286.00:15:40.22#ibcon#about to read 4, iclass 29, count 0 2006.286.00:15:40.22#ibcon#read 4, iclass 29, count 0 2006.286.00:15:40.22#ibcon#about to read 5, iclass 29, count 0 2006.286.00:15:40.22#ibcon#read 5, iclass 29, count 0 2006.286.00:15:40.22#ibcon#about to read 6, iclass 29, count 0 2006.286.00:15:40.22#ibcon#read 6, iclass 29, count 0 2006.286.00:15:40.22#ibcon#end of sib2, iclass 29, count 0 2006.286.00:15:40.22#ibcon#*after write, iclass 29, count 0 2006.286.00:15:40.22#ibcon#*before return 0, iclass 29, count 0 2006.286.00:15:40.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:15:40.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:15:40.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.00:15:40.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.00:15:40.22$vck44/valo=3,564.99 2006.286.00:15:40.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.00:15:40.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.00:15:40.22#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:40.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:15:40.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:15:40.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:15:40.22#ibcon#enter wrdev, iclass 31, count 0 2006.286.00:15:40.22#ibcon#first serial, iclass 31, count 0 2006.286.00:15:40.22#ibcon#enter sib2, iclass 31, count 0 2006.286.00:15:40.22#ibcon#flushed, iclass 31, count 0 2006.286.00:15:40.22#ibcon#about to write, iclass 31, count 0 2006.286.00:15:40.22#ibcon#wrote, iclass 31, count 0 2006.286.00:15:40.22#ibcon#about to read 3, iclass 31, count 0 2006.286.00:15:40.24#ibcon#read 3, iclass 31, count 0 2006.286.00:15:40.24#ibcon#about to read 4, iclass 31, count 0 2006.286.00:15:40.24#ibcon#read 4, iclass 31, count 0 2006.286.00:15:40.24#ibcon#about to read 5, iclass 31, count 0 2006.286.00:15:40.24#ibcon#read 5, iclass 31, count 0 2006.286.00:15:40.24#ibcon#about to read 6, iclass 31, count 0 2006.286.00:15:40.24#ibcon#read 6, iclass 31, count 0 2006.286.00:15:40.24#ibcon#end of sib2, iclass 31, count 0 2006.286.00:15:40.24#ibcon#*mode == 0, iclass 31, count 0 2006.286.00:15:40.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.00:15:40.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.00:15:40.24#ibcon#*before write, iclass 31, count 0 2006.286.00:15:40.24#ibcon#enter sib2, iclass 31, count 0 2006.286.00:15:40.24#ibcon#flushed, iclass 31, count 0 2006.286.00:15:40.24#ibcon#about to write, iclass 31, count 0 2006.286.00:15:40.24#ibcon#wrote, iclass 31, count 0 2006.286.00:15:40.24#ibcon#about to read 3, iclass 31, count 0 2006.286.00:15:40.28#ibcon#read 3, iclass 31, count 0 2006.286.00:15:40.28#ibcon#about to read 4, iclass 31, count 0 2006.286.00:15:40.28#ibcon#read 4, iclass 31, count 0 2006.286.00:15:40.28#ibcon#about to read 5, iclass 31, count 0 2006.286.00:15:40.28#ibcon#read 5, iclass 31, count 0 2006.286.00:15:40.28#ibcon#about to read 6, iclass 31, count 0 2006.286.00:15:40.28#ibcon#read 6, iclass 31, count 0 2006.286.00:15:40.28#ibcon#end of sib2, iclass 31, count 0 2006.286.00:15:40.28#ibcon#*after write, iclass 31, count 0 2006.286.00:15:40.28#ibcon#*before return 0, iclass 31, count 0 2006.286.00:15:40.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:15:40.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:15:40.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.00:15:40.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.00:15:40.28$vck44/va=3,7 2006.286.00:15:40.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.00:15:40.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.00:15:40.28#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:40.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:15:40.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:15:40.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:15:40.34#ibcon#enter wrdev, iclass 33, count 2 2006.286.00:15:40.34#ibcon#first serial, iclass 33, count 2 2006.286.00:15:40.34#ibcon#enter sib2, iclass 33, count 2 2006.286.00:15:40.34#ibcon#flushed, iclass 33, count 2 2006.286.00:15:40.34#ibcon#about to write, iclass 33, count 2 2006.286.00:15:40.34#ibcon#wrote, iclass 33, count 2 2006.286.00:15:40.34#ibcon#about to read 3, iclass 33, count 2 2006.286.00:15:40.36#ibcon#read 3, iclass 33, count 2 2006.286.00:15:40.36#ibcon#about to read 4, iclass 33, count 2 2006.286.00:15:40.36#ibcon#read 4, iclass 33, count 2 2006.286.00:15:40.36#ibcon#about to read 5, iclass 33, count 2 2006.286.00:15:40.36#ibcon#read 5, iclass 33, count 2 2006.286.00:15:40.36#ibcon#about to read 6, iclass 33, count 2 2006.286.00:15:40.36#ibcon#read 6, iclass 33, count 2 2006.286.00:15:40.36#ibcon#end of sib2, iclass 33, count 2 2006.286.00:15:40.36#ibcon#*mode == 0, iclass 33, count 2 2006.286.00:15:40.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.00:15:40.36#ibcon#[25=AT03-07\r\n] 2006.286.00:15:40.36#ibcon#*before write, iclass 33, count 2 2006.286.00:15:40.36#ibcon#enter sib2, iclass 33, count 2 2006.286.00:15:40.36#ibcon#flushed, iclass 33, count 2 2006.286.00:15:40.36#ibcon#about to write, iclass 33, count 2 2006.286.00:15:40.36#ibcon#wrote, iclass 33, count 2 2006.286.00:15:40.36#ibcon#about to read 3, iclass 33, count 2 2006.286.00:15:40.39#ibcon#read 3, iclass 33, count 2 2006.286.00:15:40.39#ibcon#about to read 4, iclass 33, count 2 2006.286.00:15:40.39#ibcon#read 4, iclass 33, count 2 2006.286.00:15:40.39#ibcon#about to read 5, iclass 33, count 2 2006.286.00:15:40.39#ibcon#read 5, iclass 33, count 2 2006.286.00:15:40.39#ibcon#about to read 6, iclass 33, count 2 2006.286.00:15:40.39#ibcon#read 6, iclass 33, count 2 2006.286.00:15:40.39#ibcon#end of sib2, iclass 33, count 2 2006.286.00:15:40.39#ibcon#*after write, iclass 33, count 2 2006.286.00:15:40.39#ibcon#*before return 0, iclass 33, count 2 2006.286.00:15:40.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:15:40.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:15:40.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.00:15:40.39#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:40.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:15:40.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:15:40.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:15:40.51#ibcon#enter wrdev, iclass 33, count 0 2006.286.00:15:40.51#ibcon#first serial, iclass 33, count 0 2006.286.00:15:40.51#ibcon#enter sib2, iclass 33, count 0 2006.286.00:15:40.51#ibcon#flushed, iclass 33, count 0 2006.286.00:15:40.51#ibcon#about to write, iclass 33, count 0 2006.286.00:15:40.51#ibcon#wrote, iclass 33, count 0 2006.286.00:15:40.51#ibcon#about to read 3, iclass 33, count 0 2006.286.00:15:40.53#ibcon#read 3, iclass 33, count 0 2006.286.00:15:40.53#ibcon#about to read 4, iclass 33, count 0 2006.286.00:15:40.53#ibcon#read 4, iclass 33, count 0 2006.286.00:15:40.53#ibcon#about to read 5, iclass 33, count 0 2006.286.00:15:40.53#ibcon#read 5, iclass 33, count 0 2006.286.00:15:40.53#ibcon#about to read 6, iclass 33, count 0 2006.286.00:15:40.53#ibcon#read 6, iclass 33, count 0 2006.286.00:15:40.53#ibcon#end of sib2, iclass 33, count 0 2006.286.00:15:40.53#ibcon#*mode == 0, iclass 33, count 0 2006.286.00:15:40.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.00:15:40.53#ibcon#[25=USB\r\n] 2006.286.00:15:40.53#ibcon#*before write, iclass 33, count 0 2006.286.00:15:40.53#ibcon#enter sib2, iclass 33, count 0 2006.286.00:15:40.53#ibcon#flushed, iclass 33, count 0 2006.286.00:15:40.53#ibcon#about to write, iclass 33, count 0 2006.286.00:15:40.53#ibcon#wrote, iclass 33, count 0 2006.286.00:15:40.53#ibcon#about to read 3, iclass 33, count 0 2006.286.00:15:40.56#ibcon#read 3, iclass 33, count 0 2006.286.00:15:40.56#ibcon#about to read 4, iclass 33, count 0 2006.286.00:15:40.56#ibcon#read 4, iclass 33, count 0 2006.286.00:15:40.56#ibcon#about to read 5, iclass 33, count 0 2006.286.00:15:40.56#ibcon#read 5, iclass 33, count 0 2006.286.00:15:40.56#ibcon#about to read 6, iclass 33, count 0 2006.286.00:15:40.56#ibcon#read 6, iclass 33, count 0 2006.286.00:15:40.56#ibcon#end of sib2, iclass 33, count 0 2006.286.00:15:40.56#ibcon#*after write, iclass 33, count 0 2006.286.00:15:40.56#ibcon#*before return 0, iclass 33, count 0 2006.286.00:15:40.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:15:40.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:15:40.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.00:15:40.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.00:15:40.56$vck44/valo=4,624.99 2006.286.00:15:40.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.00:15:40.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.00:15:40.56#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:40.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:15:40.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:15:40.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:15:40.56#ibcon#enter wrdev, iclass 35, count 0 2006.286.00:15:40.56#ibcon#first serial, iclass 35, count 0 2006.286.00:15:40.56#ibcon#enter sib2, iclass 35, count 0 2006.286.00:15:40.56#ibcon#flushed, iclass 35, count 0 2006.286.00:15:40.56#ibcon#about to write, iclass 35, count 0 2006.286.00:15:40.56#ibcon#wrote, iclass 35, count 0 2006.286.00:15:40.56#ibcon#about to read 3, iclass 35, count 0 2006.286.00:15:40.58#ibcon#read 3, iclass 35, count 0 2006.286.00:15:40.58#ibcon#about to read 4, iclass 35, count 0 2006.286.00:15:40.58#ibcon#read 4, iclass 35, count 0 2006.286.00:15:40.58#ibcon#about to read 5, iclass 35, count 0 2006.286.00:15:40.58#ibcon#read 5, iclass 35, count 0 2006.286.00:15:40.58#ibcon#about to read 6, iclass 35, count 0 2006.286.00:15:40.58#ibcon#read 6, iclass 35, count 0 2006.286.00:15:40.58#ibcon#end of sib2, iclass 35, count 0 2006.286.00:15:40.58#ibcon#*mode == 0, iclass 35, count 0 2006.286.00:15:40.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.00:15:40.58#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.00:15:40.58#ibcon#*before write, iclass 35, count 0 2006.286.00:15:40.58#ibcon#enter sib2, iclass 35, count 0 2006.286.00:15:40.58#ibcon#flushed, iclass 35, count 0 2006.286.00:15:40.58#ibcon#about to write, iclass 35, count 0 2006.286.00:15:40.58#ibcon#wrote, iclass 35, count 0 2006.286.00:15:40.58#ibcon#about to read 3, iclass 35, count 0 2006.286.00:15:40.62#ibcon#read 3, iclass 35, count 0 2006.286.00:15:40.62#ibcon#about to read 4, iclass 35, count 0 2006.286.00:15:40.62#ibcon#read 4, iclass 35, count 0 2006.286.00:15:40.62#ibcon#about to read 5, iclass 35, count 0 2006.286.00:15:40.62#ibcon#read 5, iclass 35, count 0 2006.286.00:15:40.62#ibcon#about to read 6, iclass 35, count 0 2006.286.00:15:40.62#ibcon#read 6, iclass 35, count 0 2006.286.00:15:40.62#ibcon#end of sib2, iclass 35, count 0 2006.286.00:15:40.62#ibcon#*after write, iclass 35, count 0 2006.286.00:15:40.62#ibcon#*before return 0, iclass 35, count 0 2006.286.00:15:40.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:15:40.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:15:40.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.00:15:40.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.00:15:40.62$vck44/va=4,6 2006.286.00:15:40.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.00:15:40.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.00:15:40.62#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:40.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:15:40.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:15:40.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:15:40.68#ibcon#enter wrdev, iclass 37, count 2 2006.286.00:15:40.68#ibcon#first serial, iclass 37, count 2 2006.286.00:15:40.68#ibcon#enter sib2, iclass 37, count 2 2006.286.00:15:40.68#ibcon#flushed, iclass 37, count 2 2006.286.00:15:40.68#ibcon#about to write, iclass 37, count 2 2006.286.00:15:40.68#ibcon#wrote, iclass 37, count 2 2006.286.00:15:40.68#ibcon#about to read 3, iclass 37, count 2 2006.286.00:15:40.70#ibcon#read 3, iclass 37, count 2 2006.286.00:15:40.70#ibcon#about to read 4, iclass 37, count 2 2006.286.00:15:40.70#ibcon#read 4, iclass 37, count 2 2006.286.00:15:40.70#ibcon#about to read 5, iclass 37, count 2 2006.286.00:15:40.70#ibcon#read 5, iclass 37, count 2 2006.286.00:15:40.70#ibcon#about to read 6, iclass 37, count 2 2006.286.00:15:40.70#ibcon#read 6, iclass 37, count 2 2006.286.00:15:40.70#ibcon#end of sib2, iclass 37, count 2 2006.286.00:15:40.70#ibcon#*mode == 0, iclass 37, count 2 2006.286.00:15:40.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.00:15:40.70#ibcon#[25=AT04-06\r\n] 2006.286.00:15:40.70#ibcon#*before write, iclass 37, count 2 2006.286.00:15:40.70#ibcon#enter sib2, iclass 37, count 2 2006.286.00:15:40.70#ibcon#flushed, iclass 37, count 2 2006.286.00:15:40.70#ibcon#about to write, iclass 37, count 2 2006.286.00:15:40.70#ibcon#wrote, iclass 37, count 2 2006.286.00:15:40.70#ibcon#about to read 3, iclass 37, count 2 2006.286.00:15:40.73#ibcon#read 3, iclass 37, count 2 2006.286.00:15:40.73#ibcon#about to read 4, iclass 37, count 2 2006.286.00:15:40.73#ibcon#read 4, iclass 37, count 2 2006.286.00:15:40.73#ibcon#about to read 5, iclass 37, count 2 2006.286.00:15:40.73#ibcon#read 5, iclass 37, count 2 2006.286.00:15:40.73#ibcon#about to read 6, iclass 37, count 2 2006.286.00:15:40.73#ibcon#read 6, iclass 37, count 2 2006.286.00:15:40.73#ibcon#end of sib2, iclass 37, count 2 2006.286.00:15:40.73#ibcon#*after write, iclass 37, count 2 2006.286.00:15:40.73#ibcon#*before return 0, iclass 37, count 2 2006.286.00:15:40.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:15:40.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:15:40.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.00:15:40.73#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:40.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:15:40.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:15:40.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:15:40.85#ibcon#enter wrdev, iclass 37, count 0 2006.286.00:15:40.85#ibcon#first serial, iclass 37, count 0 2006.286.00:15:40.85#ibcon#enter sib2, iclass 37, count 0 2006.286.00:15:40.85#ibcon#flushed, iclass 37, count 0 2006.286.00:15:40.85#ibcon#about to write, iclass 37, count 0 2006.286.00:15:40.85#ibcon#wrote, iclass 37, count 0 2006.286.00:15:40.85#ibcon#about to read 3, iclass 37, count 0 2006.286.00:15:40.87#ibcon#read 3, iclass 37, count 0 2006.286.00:15:40.87#ibcon#about to read 4, iclass 37, count 0 2006.286.00:15:40.87#ibcon#read 4, iclass 37, count 0 2006.286.00:15:40.87#ibcon#about to read 5, iclass 37, count 0 2006.286.00:15:40.87#ibcon#read 5, iclass 37, count 0 2006.286.00:15:40.87#ibcon#about to read 6, iclass 37, count 0 2006.286.00:15:40.87#ibcon#read 6, iclass 37, count 0 2006.286.00:15:40.87#ibcon#end of sib2, iclass 37, count 0 2006.286.00:15:40.87#ibcon#*mode == 0, iclass 37, count 0 2006.286.00:15:40.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.00:15:40.87#ibcon#[25=USB\r\n] 2006.286.00:15:40.87#ibcon#*before write, iclass 37, count 0 2006.286.00:15:40.87#ibcon#enter sib2, iclass 37, count 0 2006.286.00:15:40.87#ibcon#flushed, iclass 37, count 0 2006.286.00:15:40.87#ibcon#about to write, iclass 37, count 0 2006.286.00:15:40.87#ibcon#wrote, iclass 37, count 0 2006.286.00:15:40.87#ibcon#about to read 3, iclass 37, count 0 2006.286.00:15:40.90#ibcon#read 3, iclass 37, count 0 2006.286.00:15:40.90#ibcon#about to read 4, iclass 37, count 0 2006.286.00:15:40.90#ibcon#read 4, iclass 37, count 0 2006.286.00:15:40.90#ibcon#about to read 5, iclass 37, count 0 2006.286.00:15:40.90#ibcon#read 5, iclass 37, count 0 2006.286.00:15:40.90#ibcon#about to read 6, iclass 37, count 0 2006.286.00:15:40.90#ibcon#read 6, iclass 37, count 0 2006.286.00:15:40.90#ibcon#end of sib2, iclass 37, count 0 2006.286.00:15:40.90#ibcon#*after write, iclass 37, count 0 2006.286.00:15:40.90#ibcon#*before return 0, iclass 37, count 0 2006.286.00:15:40.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:15:40.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:15:40.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.00:15:40.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.00:15:40.90$vck44/valo=5,734.99 2006.286.00:15:40.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.00:15:40.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.00:15:40.90#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:40.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:15:40.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:15:40.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:15:40.90#ibcon#enter wrdev, iclass 39, count 0 2006.286.00:15:40.90#ibcon#first serial, iclass 39, count 0 2006.286.00:15:40.90#ibcon#enter sib2, iclass 39, count 0 2006.286.00:15:40.90#ibcon#flushed, iclass 39, count 0 2006.286.00:15:40.90#ibcon#about to write, iclass 39, count 0 2006.286.00:15:40.90#ibcon#wrote, iclass 39, count 0 2006.286.00:15:40.90#ibcon#about to read 3, iclass 39, count 0 2006.286.00:15:40.92#ibcon#read 3, iclass 39, count 0 2006.286.00:15:40.92#ibcon#about to read 4, iclass 39, count 0 2006.286.00:15:40.92#ibcon#read 4, iclass 39, count 0 2006.286.00:15:40.92#ibcon#about to read 5, iclass 39, count 0 2006.286.00:15:40.92#ibcon#read 5, iclass 39, count 0 2006.286.00:15:40.92#ibcon#about to read 6, iclass 39, count 0 2006.286.00:15:40.92#ibcon#read 6, iclass 39, count 0 2006.286.00:15:40.92#ibcon#end of sib2, iclass 39, count 0 2006.286.00:15:40.92#ibcon#*mode == 0, iclass 39, count 0 2006.286.00:15:40.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.00:15:40.92#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.00:15:40.92#ibcon#*before write, iclass 39, count 0 2006.286.00:15:40.92#ibcon#enter sib2, iclass 39, count 0 2006.286.00:15:40.92#ibcon#flushed, iclass 39, count 0 2006.286.00:15:40.92#ibcon#about to write, iclass 39, count 0 2006.286.00:15:40.92#ibcon#wrote, iclass 39, count 0 2006.286.00:15:40.92#ibcon#about to read 3, iclass 39, count 0 2006.286.00:15:40.96#ibcon#read 3, iclass 39, count 0 2006.286.00:15:40.96#ibcon#about to read 4, iclass 39, count 0 2006.286.00:15:40.96#ibcon#read 4, iclass 39, count 0 2006.286.00:15:40.96#ibcon#about to read 5, iclass 39, count 0 2006.286.00:15:40.96#ibcon#read 5, iclass 39, count 0 2006.286.00:15:40.96#ibcon#about to read 6, iclass 39, count 0 2006.286.00:15:40.96#ibcon#read 6, iclass 39, count 0 2006.286.00:15:40.96#ibcon#end of sib2, iclass 39, count 0 2006.286.00:15:40.96#ibcon#*after write, iclass 39, count 0 2006.286.00:15:40.96#ibcon#*before return 0, iclass 39, count 0 2006.286.00:15:40.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:15:40.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:15:40.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.00:15:40.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.00:15:40.96$vck44/va=5,3 2006.286.00:15:40.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.00:15:40.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.00:15:40.96#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:40.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:15:41.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:15:41.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:15:41.02#ibcon#enter wrdev, iclass 3, count 2 2006.286.00:15:41.02#ibcon#first serial, iclass 3, count 2 2006.286.00:15:41.02#ibcon#enter sib2, iclass 3, count 2 2006.286.00:15:41.02#ibcon#flushed, iclass 3, count 2 2006.286.00:15:41.02#ibcon#about to write, iclass 3, count 2 2006.286.00:15:41.02#ibcon#wrote, iclass 3, count 2 2006.286.00:15:41.02#ibcon#about to read 3, iclass 3, count 2 2006.286.00:15:41.04#ibcon#read 3, iclass 3, count 2 2006.286.00:15:41.04#ibcon#about to read 4, iclass 3, count 2 2006.286.00:15:41.04#ibcon#read 4, iclass 3, count 2 2006.286.00:15:41.04#ibcon#about to read 5, iclass 3, count 2 2006.286.00:15:41.04#ibcon#read 5, iclass 3, count 2 2006.286.00:15:41.04#ibcon#about to read 6, iclass 3, count 2 2006.286.00:15:41.04#ibcon#read 6, iclass 3, count 2 2006.286.00:15:41.04#ibcon#end of sib2, iclass 3, count 2 2006.286.00:15:41.04#ibcon#*mode == 0, iclass 3, count 2 2006.286.00:15:41.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.00:15:41.04#ibcon#[25=AT05-03\r\n] 2006.286.00:15:41.04#ibcon#*before write, iclass 3, count 2 2006.286.00:15:41.04#ibcon#enter sib2, iclass 3, count 2 2006.286.00:15:41.04#ibcon#flushed, iclass 3, count 2 2006.286.00:15:41.04#ibcon#about to write, iclass 3, count 2 2006.286.00:15:41.04#ibcon#wrote, iclass 3, count 2 2006.286.00:15:41.04#ibcon#about to read 3, iclass 3, count 2 2006.286.00:15:41.07#ibcon#read 3, iclass 3, count 2 2006.286.00:15:41.07#ibcon#about to read 4, iclass 3, count 2 2006.286.00:15:41.07#ibcon#read 4, iclass 3, count 2 2006.286.00:15:41.07#ibcon#about to read 5, iclass 3, count 2 2006.286.00:15:41.07#ibcon#read 5, iclass 3, count 2 2006.286.00:15:41.07#ibcon#about to read 6, iclass 3, count 2 2006.286.00:15:41.07#ibcon#read 6, iclass 3, count 2 2006.286.00:15:41.07#ibcon#end of sib2, iclass 3, count 2 2006.286.00:15:41.07#ibcon#*after write, iclass 3, count 2 2006.286.00:15:41.07#ibcon#*before return 0, iclass 3, count 2 2006.286.00:15:41.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:15:41.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:15:41.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.00:15:41.07#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:41.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:15:41.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:15:41.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:15:41.19#ibcon#enter wrdev, iclass 3, count 0 2006.286.00:15:41.19#ibcon#first serial, iclass 3, count 0 2006.286.00:15:41.19#ibcon#enter sib2, iclass 3, count 0 2006.286.00:15:41.19#ibcon#flushed, iclass 3, count 0 2006.286.00:15:41.19#ibcon#about to write, iclass 3, count 0 2006.286.00:15:41.19#ibcon#wrote, iclass 3, count 0 2006.286.00:15:41.19#ibcon#about to read 3, iclass 3, count 0 2006.286.00:15:41.21#ibcon#read 3, iclass 3, count 0 2006.286.00:15:41.21#ibcon#about to read 4, iclass 3, count 0 2006.286.00:15:41.21#ibcon#read 4, iclass 3, count 0 2006.286.00:15:41.21#ibcon#about to read 5, iclass 3, count 0 2006.286.00:15:41.21#ibcon#read 5, iclass 3, count 0 2006.286.00:15:41.21#ibcon#about to read 6, iclass 3, count 0 2006.286.00:15:41.21#ibcon#read 6, iclass 3, count 0 2006.286.00:15:41.21#ibcon#end of sib2, iclass 3, count 0 2006.286.00:15:41.21#ibcon#*mode == 0, iclass 3, count 0 2006.286.00:15:41.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.00:15:41.21#ibcon#[25=USB\r\n] 2006.286.00:15:41.21#ibcon#*before write, iclass 3, count 0 2006.286.00:15:41.21#ibcon#enter sib2, iclass 3, count 0 2006.286.00:15:41.21#ibcon#flushed, iclass 3, count 0 2006.286.00:15:41.21#ibcon#about to write, iclass 3, count 0 2006.286.00:15:41.21#ibcon#wrote, iclass 3, count 0 2006.286.00:15:41.21#ibcon#about to read 3, iclass 3, count 0 2006.286.00:15:41.24#ibcon#read 3, iclass 3, count 0 2006.286.00:15:41.24#ibcon#about to read 4, iclass 3, count 0 2006.286.00:15:41.24#ibcon#read 4, iclass 3, count 0 2006.286.00:15:41.24#ibcon#about to read 5, iclass 3, count 0 2006.286.00:15:41.24#ibcon#read 5, iclass 3, count 0 2006.286.00:15:41.24#ibcon#about to read 6, iclass 3, count 0 2006.286.00:15:41.24#ibcon#read 6, iclass 3, count 0 2006.286.00:15:41.24#ibcon#end of sib2, iclass 3, count 0 2006.286.00:15:41.24#ibcon#*after write, iclass 3, count 0 2006.286.00:15:41.24#ibcon#*before return 0, iclass 3, count 0 2006.286.00:15:41.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:15:41.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:15:41.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.00:15:41.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.00:15:41.24$vck44/valo=6,814.99 2006.286.00:15:41.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.00:15:41.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.00:15:41.24#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:41.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:15:41.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:15:41.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:15:41.24#ibcon#enter wrdev, iclass 5, count 0 2006.286.00:15:41.24#ibcon#first serial, iclass 5, count 0 2006.286.00:15:41.24#ibcon#enter sib2, iclass 5, count 0 2006.286.00:15:41.24#ibcon#flushed, iclass 5, count 0 2006.286.00:15:41.24#ibcon#about to write, iclass 5, count 0 2006.286.00:15:41.24#ibcon#wrote, iclass 5, count 0 2006.286.00:15:41.24#ibcon#about to read 3, iclass 5, count 0 2006.286.00:15:41.26#ibcon#read 3, iclass 5, count 0 2006.286.00:15:41.26#ibcon#about to read 4, iclass 5, count 0 2006.286.00:15:41.26#ibcon#read 4, iclass 5, count 0 2006.286.00:15:41.26#ibcon#about to read 5, iclass 5, count 0 2006.286.00:15:41.26#ibcon#read 5, iclass 5, count 0 2006.286.00:15:41.26#ibcon#about to read 6, iclass 5, count 0 2006.286.00:15:41.26#ibcon#read 6, iclass 5, count 0 2006.286.00:15:41.26#ibcon#end of sib2, iclass 5, count 0 2006.286.00:15:41.26#ibcon#*mode == 0, iclass 5, count 0 2006.286.00:15:41.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.00:15:41.26#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.00:15:41.26#ibcon#*before write, iclass 5, count 0 2006.286.00:15:41.26#ibcon#enter sib2, iclass 5, count 0 2006.286.00:15:41.26#ibcon#flushed, iclass 5, count 0 2006.286.00:15:41.26#ibcon#about to write, iclass 5, count 0 2006.286.00:15:41.26#ibcon#wrote, iclass 5, count 0 2006.286.00:15:41.26#ibcon#about to read 3, iclass 5, count 0 2006.286.00:15:41.30#ibcon#read 3, iclass 5, count 0 2006.286.00:15:41.30#ibcon#about to read 4, iclass 5, count 0 2006.286.00:15:41.30#ibcon#read 4, iclass 5, count 0 2006.286.00:15:41.30#ibcon#about to read 5, iclass 5, count 0 2006.286.00:15:41.30#ibcon#read 5, iclass 5, count 0 2006.286.00:15:41.30#ibcon#about to read 6, iclass 5, count 0 2006.286.00:15:41.30#ibcon#read 6, iclass 5, count 0 2006.286.00:15:41.30#ibcon#end of sib2, iclass 5, count 0 2006.286.00:15:41.30#ibcon#*after write, iclass 5, count 0 2006.286.00:15:41.30#ibcon#*before return 0, iclass 5, count 0 2006.286.00:15:41.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:15:41.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:15:41.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.00:15:41.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.00:15:41.30$vck44/va=6,4 2006.286.00:15:41.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.00:15:41.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.00:15:41.30#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:41.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:15:41.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:15:41.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:15:41.36#ibcon#enter wrdev, iclass 7, count 2 2006.286.00:15:41.36#ibcon#first serial, iclass 7, count 2 2006.286.00:15:41.36#ibcon#enter sib2, iclass 7, count 2 2006.286.00:15:41.36#ibcon#flushed, iclass 7, count 2 2006.286.00:15:41.36#ibcon#about to write, iclass 7, count 2 2006.286.00:15:41.36#ibcon#wrote, iclass 7, count 2 2006.286.00:15:41.36#ibcon#about to read 3, iclass 7, count 2 2006.286.00:15:41.38#ibcon#read 3, iclass 7, count 2 2006.286.00:15:41.38#ibcon#about to read 4, iclass 7, count 2 2006.286.00:15:41.38#ibcon#read 4, iclass 7, count 2 2006.286.00:15:41.38#ibcon#about to read 5, iclass 7, count 2 2006.286.00:15:41.38#ibcon#read 5, iclass 7, count 2 2006.286.00:15:41.38#ibcon#about to read 6, iclass 7, count 2 2006.286.00:15:41.38#ibcon#read 6, iclass 7, count 2 2006.286.00:15:41.38#ibcon#end of sib2, iclass 7, count 2 2006.286.00:15:41.38#ibcon#*mode == 0, iclass 7, count 2 2006.286.00:15:41.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.00:15:41.38#ibcon#[25=AT06-04\r\n] 2006.286.00:15:41.38#ibcon#*before write, iclass 7, count 2 2006.286.00:15:41.38#ibcon#enter sib2, iclass 7, count 2 2006.286.00:15:41.38#ibcon#flushed, iclass 7, count 2 2006.286.00:15:41.38#ibcon#about to write, iclass 7, count 2 2006.286.00:15:41.38#ibcon#wrote, iclass 7, count 2 2006.286.00:15:41.38#ibcon#about to read 3, iclass 7, count 2 2006.286.00:15:41.41#ibcon#read 3, iclass 7, count 2 2006.286.00:15:41.41#ibcon#about to read 4, iclass 7, count 2 2006.286.00:15:41.41#ibcon#read 4, iclass 7, count 2 2006.286.00:15:41.41#ibcon#about to read 5, iclass 7, count 2 2006.286.00:15:41.41#ibcon#read 5, iclass 7, count 2 2006.286.00:15:41.41#ibcon#about to read 6, iclass 7, count 2 2006.286.00:15:41.41#ibcon#read 6, iclass 7, count 2 2006.286.00:15:41.41#ibcon#end of sib2, iclass 7, count 2 2006.286.00:15:41.41#ibcon#*after write, iclass 7, count 2 2006.286.00:15:41.41#ibcon#*before return 0, iclass 7, count 2 2006.286.00:15:41.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:15:41.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:15:41.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.00:15:41.41#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:41.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:15:41.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:15:41.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:15:41.53#ibcon#enter wrdev, iclass 7, count 0 2006.286.00:15:41.53#ibcon#first serial, iclass 7, count 0 2006.286.00:15:41.53#ibcon#enter sib2, iclass 7, count 0 2006.286.00:15:41.53#ibcon#flushed, iclass 7, count 0 2006.286.00:15:41.53#ibcon#about to write, iclass 7, count 0 2006.286.00:15:41.53#ibcon#wrote, iclass 7, count 0 2006.286.00:15:41.53#ibcon#about to read 3, iclass 7, count 0 2006.286.00:15:41.55#ibcon#read 3, iclass 7, count 0 2006.286.00:15:41.55#ibcon#about to read 4, iclass 7, count 0 2006.286.00:15:41.55#ibcon#read 4, iclass 7, count 0 2006.286.00:15:41.55#ibcon#about to read 5, iclass 7, count 0 2006.286.00:15:41.55#ibcon#read 5, iclass 7, count 0 2006.286.00:15:41.55#ibcon#about to read 6, iclass 7, count 0 2006.286.00:15:41.55#ibcon#read 6, iclass 7, count 0 2006.286.00:15:41.55#ibcon#end of sib2, iclass 7, count 0 2006.286.00:15:41.55#ibcon#*mode == 0, iclass 7, count 0 2006.286.00:15:41.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.00:15:41.55#ibcon#[25=USB\r\n] 2006.286.00:15:41.55#ibcon#*before write, iclass 7, count 0 2006.286.00:15:41.55#ibcon#enter sib2, iclass 7, count 0 2006.286.00:15:41.55#ibcon#flushed, iclass 7, count 0 2006.286.00:15:41.55#ibcon#about to write, iclass 7, count 0 2006.286.00:15:41.55#ibcon#wrote, iclass 7, count 0 2006.286.00:15:41.55#ibcon#about to read 3, iclass 7, count 0 2006.286.00:15:41.58#ibcon#read 3, iclass 7, count 0 2006.286.00:15:41.58#ibcon#about to read 4, iclass 7, count 0 2006.286.00:15:41.58#ibcon#read 4, iclass 7, count 0 2006.286.00:15:41.58#ibcon#about to read 5, iclass 7, count 0 2006.286.00:15:41.58#ibcon#read 5, iclass 7, count 0 2006.286.00:15:41.58#ibcon#about to read 6, iclass 7, count 0 2006.286.00:15:41.58#ibcon#read 6, iclass 7, count 0 2006.286.00:15:41.58#ibcon#end of sib2, iclass 7, count 0 2006.286.00:15:41.58#ibcon#*after write, iclass 7, count 0 2006.286.00:15:41.58#ibcon#*before return 0, iclass 7, count 0 2006.286.00:15:41.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:15:41.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:15:41.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.00:15:41.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.00:15:41.58$vck44/valo=7,864.99 2006.286.00:15:41.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.00:15:41.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.00:15:41.58#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:41.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:15:41.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:15:41.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:15:41.58#ibcon#enter wrdev, iclass 11, count 0 2006.286.00:15:41.58#ibcon#first serial, iclass 11, count 0 2006.286.00:15:41.58#ibcon#enter sib2, iclass 11, count 0 2006.286.00:15:41.58#ibcon#flushed, iclass 11, count 0 2006.286.00:15:41.58#ibcon#about to write, iclass 11, count 0 2006.286.00:15:41.58#ibcon#wrote, iclass 11, count 0 2006.286.00:15:41.58#ibcon#about to read 3, iclass 11, count 0 2006.286.00:15:41.60#ibcon#read 3, iclass 11, count 0 2006.286.00:15:41.60#ibcon#about to read 4, iclass 11, count 0 2006.286.00:15:41.60#ibcon#read 4, iclass 11, count 0 2006.286.00:15:41.60#ibcon#about to read 5, iclass 11, count 0 2006.286.00:15:41.60#ibcon#read 5, iclass 11, count 0 2006.286.00:15:41.60#ibcon#about to read 6, iclass 11, count 0 2006.286.00:15:41.60#ibcon#read 6, iclass 11, count 0 2006.286.00:15:41.60#ibcon#end of sib2, iclass 11, count 0 2006.286.00:15:41.60#ibcon#*mode == 0, iclass 11, count 0 2006.286.00:15:41.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.00:15:41.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.00:15:41.60#ibcon#*before write, iclass 11, count 0 2006.286.00:15:41.60#ibcon#enter sib2, iclass 11, count 0 2006.286.00:15:41.60#ibcon#flushed, iclass 11, count 0 2006.286.00:15:41.60#ibcon#about to write, iclass 11, count 0 2006.286.00:15:41.60#ibcon#wrote, iclass 11, count 0 2006.286.00:15:41.60#ibcon#about to read 3, iclass 11, count 0 2006.286.00:15:41.64#ibcon#read 3, iclass 11, count 0 2006.286.00:15:41.64#ibcon#about to read 4, iclass 11, count 0 2006.286.00:15:41.64#ibcon#read 4, iclass 11, count 0 2006.286.00:15:41.64#ibcon#about to read 5, iclass 11, count 0 2006.286.00:15:41.64#ibcon#read 5, iclass 11, count 0 2006.286.00:15:41.64#ibcon#about to read 6, iclass 11, count 0 2006.286.00:15:41.64#ibcon#read 6, iclass 11, count 0 2006.286.00:15:41.64#ibcon#end of sib2, iclass 11, count 0 2006.286.00:15:41.64#ibcon#*after write, iclass 11, count 0 2006.286.00:15:41.64#ibcon#*before return 0, iclass 11, count 0 2006.286.00:15:41.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:15:41.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:15:41.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.00:15:41.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.00:15:41.64$vck44/va=7,4 2006.286.00:15:41.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.00:15:41.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.00:15:41.64#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:41.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:15:41.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:15:41.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:15:41.70#ibcon#enter wrdev, iclass 13, count 2 2006.286.00:15:41.70#ibcon#first serial, iclass 13, count 2 2006.286.00:15:41.70#ibcon#enter sib2, iclass 13, count 2 2006.286.00:15:41.70#ibcon#flushed, iclass 13, count 2 2006.286.00:15:41.70#ibcon#about to write, iclass 13, count 2 2006.286.00:15:41.70#ibcon#wrote, iclass 13, count 2 2006.286.00:15:41.70#ibcon#about to read 3, iclass 13, count 2 2006.286.00:15:41.72#ibcon#read 3, iclass 13, count 2 2006.286.00:15:41.72#ibcon#about to read 4, iclass 13, count 2 2006.286.00:15:41.72#ibcon#read 4, iclass 13, count 2 2006.286.00:15:41.72#ibcon#about to read 5, iclass 13, count 2 2006.286.00:15:41.72#ibcon#read 5, iclass 13, count 2 2006.286.00:15:41.72#ibcon#about to read 6, iclass 13, count 2 2006.286.00:15:41.72#ibcon#read 6, iclass 13, count 2 2006.286.00:15:41.72#ibcon#end of sib2, iclass 13, count 2 2006.286.00:15:41.72#ibcon#*mode == 0, iclass 13, count 2 2006.286.00:15:41.72#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.00:15:41.72#ibcon#[25=AT07-04\r\n] 2006.286.00:15:41.72#ibcon#*before write, iclass 13, count 2 2006.286.00:15:41.72#ibcon#enter sib2, iclass 13, count 2 2006.286.00:15:41.72#ibcon#flushed, iclass 13, count 2 2006.286.00:15:41.72#ibcon#about to write, iclass 13, count 2 2006.286.00:15:41.72#ibcon#wrote, iclass 13, count 2 2006.286.00:15:41.72#ibcon#about to read 3, iclass 13, count 2 2006.286.00:15:41.75#ibcon#read 3, iclass 13, count 2 2006.286.00:15:41.75#ibcon#about to read 4, iclass 13, count 2 2006.286.00:15:41.75#ibcon#read 4, iclass 13, count 2 2006.286.00:15:41.75#ibcon#about to read 5, iclass 13, count 2 2006.286.00:15:41.75#ibcon#read 5, iclass 13, count 2 2006.286.00:15:41.75#ibcon#about to read 6, iclass 13, count 2 2006.286.00:15:41.75#ibcon#read 6, iclass 13, count 2 2006.286.00:15:41.75#ibcon#end of sib2, iclass 13, count 2 2006.286.00:15:41.75#ibcon#*after write, iclass 13, count 2 2006.286.00:15:41.75#ibcon#*before return 0, iclass 13, count 2 2006.286.00:15:41.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:15:41.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:15:41.75#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.00:15:41.75#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:41.75#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:15:41.87#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:15:41.87#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:15:41.87#ibcon#enter wrdev, iclass 13, count 0 2006.286.00:15:41.87#ibcon#first serial, iclass 13, count 0 2006.286.00:15:41.87#ibcon#enter sib2, iclass 13, count 0 2006.286.00:15:41.87#ibcon#flushed, iclass 13, count 0 2006.286.00:15:41.87#ibcon#about to write, iclass 13, count 0 2006.286.00:15:41.87#ibcon#wrote, iclass 13, count 0 2006.286.00:15:41.87#ibcon#about to read 3, iclass 13, count 0 2006.286.00:15:41.89#ibcon#read 3, iclass 13, count 0 2006.286.00:15:41.89#ibcon#about to read 4, iclass 13, count 0 2006.286.00:15:41.89#ibcon#read 4, iclass 13, count 0 2006.286.00:15:41.89#ibcon#about to read 5, iclass 13, count 0 2006.286.00:15:41.89#ibcon#read 5, iclass 13, count 0 2006.286.00:15:41.89#ibcon#about to read 6, iclass 13, count 0 2006.286.00:15:41.89#ibcon#read 6, iclass 13, count 0 2006.286.00:15:41.89#ibcon#end of sib2, iclass 13, count 0 2006.286.00:15:41.89#ibcon#*mode == 0, iclass 13, count 0 2006.286.00:15:41.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.00:15:41.89#ibcon#[25=USB\r\n] 2006.286.00:15:41.89#ibcon#*before write, iclass 13, count 0 2006.286.00:15:41.89#ibcon#enter sib2, iclass 13, count 0 2006.286.00:15:41.89#ibcon#flushed, iclass 13, count 0 2006.286.00:15:41.89#ibcon#about to write, iclass 13, count 0 2006.286.00:15:41.89#ibcon#wrote, iclass 13, count 0 2006.286.00:15:41.89#ibcon#about to read 3, iclass 13, count 0 2006.286.00:15:41.92#ibcon#read 3, iclass 13, count 0 2006.286.00:15:41.92#ibcon#about to read 4, iclass 13, count 0 2006.286.00:15:41.92#ibcon#read 4, iclass 13, count 0 2006.286.00:15:41.92#ibcon#about to read 5, iclass 13, count 0 2006.286.00:15:41.92#ibcon#read 5, iclass 13, count 0 2006.286.00:15:41.92#ibcon#about to read 6, iclass 13, count 0 2006.286.00:15:41.92#ibcon#read 6, iclass 13, count 0 2006.286.00:15:41.92#ibcon#end of sib2, iclass 13, count 0 2006.286.00:15:41.92#ibcon#*after write, iclass 13, count 0 2006.286.00:15:41.92#ibcon#*before return 0, iclass 13, count 0 2006.286.00:15:41.92#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:15:41.92#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:15:41.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.00:15:41.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.00:15:41.92$vck44/valo=8,884.99 2006.286.00:15:41.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.00:15:41.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.00:15:41.92#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:41.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:15:41.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:15:41.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:15:41.92#ibcon#enter wrdev, iclass 15, count 0 2006.286.00:15:41.92#ibcon#first serial, iclass 15, count 0 2006.286.00:15:41.92#ibcon#enter sib2, iclass 15, count 0 2006.286.00:15:41.92#ibcon#flushed, iclass 15, count 0 2006.286.00:15:41.92#ibcon#about to write, iclass 15, count 0 2006.286.00:15:41.92#ibcon#wrote, iclass 15, count 0 2006.286.00:15:41.92#ibcon#about to read 3, iclass 15, count 0 2006.286.00:15:41.94#ibcon#read 3, iclass 15, count 0 2006.286.00:15:41.94#ibcon#about to read 4, iclass 15, count 0 2006.286.00:15:41.94#ibcon#read 4, iclass 15, count 0 2006.286.00:15:41.94#ibcon#about to read 5, iclass 15, count 0 2006.286.00:15:41.94#ibcon#read 5, iclass 15, count 0 2006.286.00:15:41.94#ibcon#about to read 6, iclass 15, count 0 2006.286.00:15:41.94#ibcon#read 6, iclass 15, count 0 2006.286.00:15:41.94#ibcon#end of sib2, iclass 15, count 0 2006.286.00:15:41.94#ibcon#*mode == 0, iclass 15, count 0 2006.286.00:15:41.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.00:15:41.94#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.00:15:41.94#ibcon#*before write, iclass 15, count 0 2006.286.00:15:41.94#ibcon#enter sib2, iclass 15, count 0 2006.286.00:15:41.94#ibcon#flushed, iclass 15, count 0 2006.286.00:15:41.94#ibcon#about to write, iclass 15, count 0 2006.286.00:15:41.94#ibcon#wrote, iclass 15, count 0 2006.286.00:15:41.94#ibcon#about to read 3, iclass 15, count 0 2006.286.00:15:41.98#ibcon#read 3, iclass 15, count 0 2006.286.00:15:41.98#ibcon#about to read 4, iclass 15, count 0 2006.286.00:15:41.98#ibcon#read 4, iclass 15, count 0 2006.286.00:15:41.98#ibcon#about to read 5, iclass 15, count 0 2006.286.00:15:41.98#ibcon#read 5, iclass 15, count 0 2006.286.00:15:41.98#ibcon#about to read 6, iclass 15, count 0 2006.286.00:15:41.98#ibcon#read 6, iclass 15, count 0 2006.286.00:15:41.98#ibcon#end of sib2, iclass 15, count 0 2006.286.00:15:41.98#ibcon#*after write, iclass 15, count 0 2006.286.00:15:41.98#ibcon#*before return 0, iclass 15, count 0 2006.286.00:15:41.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:15:41.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:15:41.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.00:15:41.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.00:15:41.98$vck44/va=8,3 2006.286.00:15:41.98#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.00:15:41.98#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.00:15:41.98#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:41.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:15:42.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:15:42.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:15:42.04#ibcon#enter wrdev, iclass 17, count 2 2006.286.00:15:42.04#ibcon#first serial, iclass 17, count 2 2006.286.00:15:42.04#ibcon#enter sib2, iclass 17, count 2 2006.286.00:15:42.04#ibcon#flushed, iclass 17, count 2 2006.286.00:15:42.04#ibcon#about to write, iclass 17, count 2 2006.286.00:15:42.04#ibcon#wrote, iclass 17, count 2 2006.286.00:15:42.04#ibcon#about to read 3, iclass 17, count 2 2006.286.00:15:42.06#ibcon#read 3, iclass 17, count 2 2006.286.00:15:42.06#ibcon#about to read 4, iclass 17, count 2 2006.286.00:15:42.06#ibcon#read 4, iclass 17, count 2 2006.286.00:15:42.06#ibcon#about to read 5, iclass 17, count 2 2006.286.00:15:42.06#ibcon#read 5, iclass 17, count 2 2006.286.00:15:42.06#ibcon#about to read 6, iclass 17, count 2 2006.286.00:15:42.06#ibcon#read 6, iclass 17, count 2 2006.286.00:15:42.06#ibcon#end of sib2, iclass 17, count 2 2006.286.00:15:42.06#ibcon#*mode == 0, iclass 17, count 2 2006.286.00:15:42.06#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.00:15:42.06#ibcon#[25=AT08-03\r\n] 2006.286.00:15:42.06#ibcon#*before write, iclass 17, count 2 2006.286.00:15:42.06#ibcon#enter sib2, iclass 17, count 2 2006.286.00:15:42.06#ibcon#flushed, iclass 17, count 2 2006.286.00:15:42.06#ibcon#about to write, iclass 17, count 2 2006.286.00:15:42.06#ibcon#wrote, iclass 17, count 2 2006.286.00:15:42.06#ibcon#about to read 3, iclass 17, count 2 2006.286.00:15:42.09#ibcon#read 3, iclass 17, count 2 2006.286.00:15:42.09#ibcon#about to read 4, iclass 17, count 2 2006.286.00:15:42.09#ibcon#read 4, iclass 17, count 2 2006.286.00:15:42.09#ibcon#about to read 5, iclass 17, count 2 2006.286.00:15:42.09#ibcon#read 5, iclass 17, count 2 2006.286.00:15:42.09#ibcon#about to read 6, iclass 17, count 2 2006.286.00:15:42.09#ibcon#read 6, iclass 17, count 2 2006.286.00:15:42.09#ibcon#end of sib2, iclass 17, count 2 2006.286.00:15:42.09#ibcon#*after write, iclass 17, count 2 2006.286.00:15:42.09#ibcon#*before return 0, iclass 17, count 2 2006.286.00:15:42.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:15:42.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:15:42.09#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.00:15:42.09#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:42.09#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:15:42.21#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:15:42.21#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:15:42.21#ibcon#enter wrdev, iclass 17, count 0 2006.286.00:15:42.21#ibcon#first serial, iclass 17, count 0 2006.286.00:15:42.21#ibcon#enter sib2, iclass 17, count 0 2006.286.00:15:42.21#ibcon#flushed, iclass 17, count 0 2006.286.00:15:42.21#ibcon#about to write, iclass 17, count 0 2006.286.00:15:42.21#ibcon#wrote, iclass 17, count 0 2006.286.00:15:42.21#ibcon#about to read 3, iclass 17, count 0 2006.286.00:15:42.23#ibcon#read 3, iclass 17, count 0 2006.286.00:15:42.23#ibcon#about to read 4, iclass 17, count 0 2006.286.00:15:42.23#ibcon#read 4, iclass 17, count 0 2006.286.00:15:42.23#ibcon#about to read 5, iclass 17, count 0 2006.286.00:15:42.23#ibcon#read 5, iclass 17, count 0 2006.286.00:15:42.23#ibcon#about to read 6, iclass 17, count 0 2006.286.00:15:42.23#ibcon#read 6, iclass 17, count 0 2006.286.00:15:42.23#ibcon#end of sib2, iclass 17, count 0 2006.286.00:15:42.23#ibcon#*mode == 0, iclass 17, count 0 2006.286.00:15:42.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.00:15:42.23#ibcon#[25=USB\r\n] 2006.286.00:15:42.23#ibcon#*before write, iclass 17, count 0 2006.286.00:15:42.23#ibcon#enter sib2, iclass 17, count 0 2006.286.00:15:42.23#ibcon#flushed, iclass 17, count 0 2006.286.00:15:42.23#ibcon#about to write, iclass 17, count 0 2006.286.00:15:42.23#ibcon#wrote, iclass 17, count 0 2006.286.00:15:42.23#ibcon#about to read 3, iclass 17, count 0 2006.286.00:15:42.26#ibcon#read 3, iclass 17, count 0 2006.286.00:15:42.26#ibcon#about to read 4, iclass 17, count 0 2006.286.00:15:42.26#ibcon#read 4, iclass 17, count 0 2006.286.00:15:42.26#ibcon#about to read 5, iclass 17, count 0 2006.286.00:15:42.26#ibcon#read 5, iclass 17, count 0 2006.286.00:15:42.26#ibcon#about to read 6, iclass 17, count 0 2006.286.00:15:42.26#ibcon#read 6, iclass 17, count 0 2006.286.00:15:42.26#ibcon#end of sib2, iclass 17, count 0 2006.286.00:15:42.26#ibcon#*after write, iclass 17, count 0 2006.286.00:15:42.26#ibcon#*before return 0, iclass 17, count 0 2006.286.00:15:42.26#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:15:42.26#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:15:42.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.00:15:42.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.00:15:42.26$vck44/vblo=1,629.99 2006.286.00:15:42.26#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.00:15:42.26#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.00:15:42.26#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:42.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:15:42.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:15:42.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:15:42.26#ibcon#enter wrdev, iclass 19, count 0 2006.286.00:15:42.26#ibcon#first serial, iclass 19, count 0 2006.286.00:15:42.26#ibcon#enter sib2, iclass 19, count 0 2006.286.00:15:42.26#ibcon#flushed, iclass 19, count 0 2006.286.00:15:42.26#ibcon#about to write, iclass 19, count 0 2006.286.00:15:42.26#ibcon#wrote, iclass 19, count 0 2006.286.00:15:42.26#ibcon#about to read 3, iclass 19, count 0 2006.286.00:15:42.28#ibcon#read 3, iclass 19, count 0 2006.286.00:15:42.28#ibcon#about to read 4, iclass 19, count 0 2006.286.00:15:42.28#ibcon#read 4, iclass 19, count 0 2006.286.00:15:42.28#ibcon#about to read 5, iclass 19, count 0 2006.286.00:15:42.28#ibcon#read 5, iclass 19, count 0 2006.286.00:15:42.28#ibcon#about to read 6, iclass 19, count 0 2006.286.00:15:42.28#ibcon#read 6, iclass 19, count 0 2006.286.00:15:42.28#ibcon#end of sib2, iclass 19, count 0 2006.286.00:15:42.28#ibcon#*mode == 0, iclass 19, count 0 2006.286.00:15:42.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.00:15:42.28#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.00:15:42.28#ibcon#*before write, iclass 19, count 0 2006.286.00:15:42.28#ibcon#enter sib2, iclass 19, count 0 2006.286.00:15:42.28#ibcon#flushed, iclass 19, count 0 2006.286.00:15:42.28#ibcon#about to write, iclass 19, count 0 2006.286.00:15:42.28#ibcon#wrote, iclass 19, count 0 2006.286.00:15:42.28#ibcon#about to read 3, iclass 19, count 0 2006.286.00:15:42.32#ibcon#read 3, iclass 19, count 0 2006.286.00:15:42.32#ibcon#about to read 4, iclass 19, count 0 2006.286.00:15:42.32#ibcon#read 4, iclass 19, count 0 2006.286.00:15:42.32#ibcon#about to read 5, iclass 19, count 0 2006.286.00:15:42.32#ibcon#read 5, iclass 19, count 0 2006.286.00:15:42.32#ibcon#about to read 6, iclass 19, count 0 2006.286.00:15:42.32#ibcon#read 6, iclass 19, count 0 2006.286.00:15:42.32#ibcon#end of sib2, iclass 19, count 0 2006.286.00:15:42.32#ibcon#*after write, iclass 19, count 0 2006.286.00:15:42.32#ibcon#*before return 0, iclass 19, count 0 2006.286.00:15:42.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:15:42.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:15:42.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.00:15:42.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.00:15:42.32$vck44/vb=1,4 2006.286.00:15:42.32#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.00:15:42.32#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.00:15:42.32#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:42.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:15:42.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:15:42.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:15:42.32#ibcon#enter wrdev, iclass 21, count 2 2006.286.00:15:42.32#ibcon#first serial, iclass 21, count 2 2006.286.00:15:42.32#ibcon#enter sib2, iclass 21, count 2 2006.286.00:15:42.32#ibcon#flushed, iclass 21, count 2 2006.286.00:15:42.32#ibcon#about to write, iclass 21, count 2 2006.286.00:15:42.32#ibcon#wrote, iclass 21, count 2 2006.286.00:15:42.32#ibcon#about to read 3, iclass 21, count 2 2006.286.00:15:42.34#ibcon#read 3, iclass 21, count 2 2006.286.00:15:42.34#ibcon#about to read 4, iclass 21, count 2 2006.286.00:15:42.34#ibcon#read 4, iclass 21, count 2 2006.286.00:15:42.34#ibcon#about to read 5, iclass 21, count 2 2006.286.00:15:42.34#ibcon#read 5, iclass 21, count 2 2006.286.00:15:42.34#ibcon#about to read 6, iclass 21, count 2 2006.286.00:15:42.34#ibcon#read 6, iclass 21, count 2 2006.286.00:15:42.34#ibcon#end of sib2, iclass 21, count 2 2006.286.00:15:42.34#ibcon#*mode == 0, iclass 21, count 2 2006.286.00:15:42.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.00:15:42.34#ibcon#[27=AT01-04\r\n] 2006.286.00:15:42.34#ibcon#*before write, iclass 21, count 2 2006.286.00:15:42.34#ibcon#enter sib2, iclass 21, count 2 2006.286.00:15:42.34#ibcon#flushed, iclass 21, count 2 2006.286.00:15:42.34#ibcon#about to write, iclass 21, count 2 2006.286.00:15:42.34#ibcon#wrote, iclass 21, count 2 2006.286.00:15:42.34#ibcon#about to read 3, iclass 21, count 2 2006.286.00:15:42.37#ibcon#read 3, iclass 21, count 2 2006.286.00:15:42.37#ibcon#about to read 4, iclass 21, count 2 2006.286.00:15:42.37#ibcon#read 4, iclass 21, count 2 2006.286.00:15:42.37#ibcon#about to read 5, iclass 21, count 2 2006.286.00:15:42.37#ibcon#read 5, iclass 21, count 2 2006.286.00:15:42.37#ibcon#about to read 6, iclass 21, count 2 2006.286.00:15:42.37#ibcon#read 6, iclass 21, count 2 2006.286.00:15:42.37#ibcon#end of sib2, iclass 21, count 2 2006.286.00:15:42.37#ibcon#*after write, iclass 21, count 2 2006.286.00:15:42.37#ibcon#*before return 0, iclass 21, count 2 2006.286.00:15:42.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:15:42.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:15:42.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.00:15:42.37#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:42.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:15:42.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:15:42.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:15:42.49#ibcon#enter wrdev, iclass 21, count 0 2006.286.00:15:42.49#ibcon#first serial, iclass 21, count 0 2006.286.00:15:42.49#ibcon#enter sib2, iclass 21, count 0 2006.286.00:15:42.49#ibcon#flushed, iclass 21, count 0 2006.286.00:15:42.49#ibcon#about to write, iclass 21, count 0 2006.286.00:15:42.49#ibcon#wrote, iclass 21, count 0 2006.286.00:15:42.49#ibcon#about to read 3, iclass 21, count 0 2006.286.00:15:42.51#ibcon#read 3, iclass 21, count 0 2006.286.00:15:42.51#ibcon#about to read 4, iclass 21, count 0 2006.286.00:15:42.51#ibcon#read 4, iclass 21, count 0 2006.286.00:15:42.51#ibcon#about to read 5, iclass 21, count 0 2006.286.00:15:42.51#ibcon#read 5, iclass 21, count 0 2006.286.00:15:42.51#ibcon#about to read 6, iclass 21, count 0 2006.286.00:15:42.51#ibcon#read 6, iclass 21, count 0 2006.286.00:15:42.51#ibcon#end of sib2, iclass 21, count 0 2006.286.00:15:42.51#ibcon#*mode == 0, iclass 21, count 0 2006.286.00:15:42.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.00:15:42.51#ibcon#[27=USB\r\n] 2006.286.00:15:42.51#ibcon#*before write, iclass 21, count 0 2006.286.00:15:42.51#ibcon#enter sib2, iclass 21, count 0 2006.286.00:15:42.51#ibcon#flushed, iclass 21, count 0 2006.286.00:15:42.51#ibcon#about to write, iclass 21, count 0 2006.286.00:15:42.51#ibcon#wrote, iclass 21, count 0 2006.286.00:15:42.51#ibcon#about to read 3, iclass 21, count 0 2006.286.00:15:42.54#ibcon#read 3, iclass 21, count 0 2006.286.00:15:42.54#ibcon#about to read 4, iclass 21, count 0 2006.286.00:15:42.54#ibcon#read 4, iclass 21, count 0 2006.286.00:15:42.54#ibcon#about to read 5, iclass 21, count 0 2006.286.00:15:42.54#ibcon#read 5, iclass 21, count 0 2006.286.00:15:42.54#ibcon#about to read 6, iclass 21, count 0 2006.286.00:15:42.54#ibcon#read 6, iclass 21, count 0 2006.286.00:15:42.54#ibcon#end of sib2, iclass 21, count 0 2006.286.00:15:42.54#ibcon#*after write, iclass 21, count 0 2006.286.00:15:42.54#ibcon#*before return 0, iclass 21, count 0 2006.286.00:15:42.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:15:42.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:15:42.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.00:15:42.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.00:15:42.54$vck44/vblo=2,634.99 2006.286.00:15:42.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.00:15:42.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.00:15:42.54#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:42.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:15:42.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:15:42.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:15:42.54#ibcon#enter wrdev, iclass 23, count 0 2006.286.00:15:42.54#ibcon#first serial, iclass 23, count 0 2006.286.00:15:42.54#ibcon#enter sib2, iclass 23, count 0 2006.286.00:15:42.54#ibcon#flushed, iclass 23, count 0 2006.286.00:15:42.54#ibcon#about to write, iclass 23, count 0 2006.286.00:15:42.54#ibcon#wrote, iclass 23, count 0 2006.286.00:15:42.54#ibcon#about to read 3, iclass 23, count 0 2006.286.00:15:42.56#ibcon#read 3, iclass 23, count 0 2006.286.00:15:42.56#ibcon#about to read 4, iclass 23, count 0 2006.286.00:15:42.56#ibcon#read 4, iclass 23, count 0 2006.286.00:15:42.56#ibcon#about to read 5, iclass 23, count 0 2006.286.00:15:42.56#ibcon#read 5, iclass 23, count 0 2006.286.00:15:42.56#ibcon#about to read 6, iclass 23, count 0 2006.286.00:15:42.56#ibcon#read 6, iclass 23, count 0 2006.286.00:15:42.56#ibcon#end of sib2, iclass 23, count 0 2006.286.00:15:42.56#ibcon#*mode == 0, iclass 23, count 0 2006.286.00:15:42.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.00:15:42.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.00:15:42.56#ibcon#*before write, iclass 23, count 0 2006.286.00:15:42.56#ibcon#enter sib2, iclass 23, count 0 2006.286.00:15:42.56#ibcon#flushed, iclass 23, count 0 2006.286.00:15:42.56#ibcon#about to write, iclass 23, count 0 2006.286.00:15:42.56#ibcon#wrote, iclass 23, count 0 2006.286.00:15:42.56#ibcon#about to read 3, iclass 23, count 0 2006.286.00:15:42.60#ibcon#read 3, iclass 23, count 0 2006.286.00:15:42.60#ibcon#about to read 4, iclass 23, count 0 2006.286.00:15:42.60#ibcon#read 4, iclass 23, count 0 2006.286.00:15:42.60#ibcon#about to read 5, iclass 23, count 0 2006.286.00:15:42.60#ibcon#read 5, iclass 23, count 0 2006.286.00:15:42.60#ibcon#about to read 6, iclass 23, count 0 2006.286.00:15:42.60#ibcon#read 6, iclass 23, count 0 2006.286.00:15:42.60#ibcon#end of sib2, iclass 23, count 0 2006.286.00:15:42.60#ibcon#*after write, iclass 23, count 0 2006.286.00:15:42.60#ibcon#*before return 0, iclass 23, count 0 2006.286.00:15:42.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:15:42.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:15:42.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.00:15:42.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.00:15:42.60$vck44/vb=2,5 2006.286.00:15:42.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.00:15:42.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.00:15:42.60#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:42.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:15:42.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:15:42.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:15:42.66#ibcon#enter wrdev, iclass 25, count 2 2006.286.00:15:42.66#ibcon#first serial, iclass 25, count 2 2006.286.00:15:42.66#ibcon#enter sib2, iclass 25, count 2 2006.286.00:15:42.66#ibcon#flushed, iclass 25, count 2 2006.286.00:15:42.66#ibcon#about to write, iclass 25, count 2 2006.286.00:15:42.66#ibcon#wrote, iclass 25, count 2 2006.286.00:15:42.66#ibcon#about to read 3, iclass 25, count 2 2006.286.00:15:42.68#ibcon#read 3, iclass 25, count 2 2006.286.00:15:42.68#ibcon#about to read 4, iclass 25, count 2 2006.286.00:15:42.68#ibcon#read 4, iclass 25, count 2 2006.286.00:15:42.68#ibcon#about to read 5, iclass 25, count 2 2006.286.00:15:42.68#ibcon#read 5, iclass 25, count 2 2006.286.00:15:42.68#ibcon#about to read 6, iclass 25, count 2 2006.286.00:15:42.68#ibcon#read 6, iclass 25, count 2 2006.286.00:15:42.68#ibcon#end of sib2, iclass 25, count 2 2006.286.00:15:42.68#ibcon#*mode == 0, iclass 25, count 2 2006.286.00:15:42.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.00:15:42.68#ibcon#[27=AT02-05\r\n] 2006.286.00:15:42.68#ibcon#*before write, iclass 25, count 2 2006.286.00:15:42.68#ibcon#enter sib2, iclass 25, count 2 2006.286.00:15:42.68#ibcon#flushed, iclass 25, count 2 2006.286.00:15:42.68#ibcon#about to write, iclass 25, count 2 2006.286.00:15:42.68#ibcon#wrote, iclass 25, count 2 2006.286.00:15:42.68#ibcon#about to read 3, iclass 25, count 2 2006.286.00:15:42.71#ibcon#read 3, iclass 25, count 2 2006.286.00:15:42.71#ibcon#about to read 4, iclass 25, count 2 2006.286.00:15:42.71#ibcon#read 4, iclass 25, count 2 2006.286.00:15:42.71#ibcon#about to read 5, iclass 25, count 2 2006.286.00:15:42.71#ibcon#read 5, iclass 25, count 2 2006.286.00:15:42.71#ibcon#about to read 6, iclass 25, count 2 2006.286.00:15:42.71#ibcon#read 6, iclass 25, count 2 2006.286.00:15:42.71#ibcon#end of sib2, iclass 25, count 2 2006.286.00:15:42.71#ibcon#*after write, iclass 25, count 2 2006.286.00:15:42.71#ibcon#*before return 0, iclass 25, count 2 2006.286.00:15:42.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:15:42.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:15:42.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.00:15:42.71#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:42.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:15:42.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:15:42.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:15:42.83#ibcon#enter wrdev, iclass 25, count 0 2006.286.00:15:42.83#ibcon#first serial, iclass 25, count 0 2006.286.00:15:42.83#ibcon#enter sib2, iclass 25, count 0 2006.286.00:15:42.83#ibcon#flushed, iclass 25, count 0 2006.286.00:15:42.83#ibcon#about to write, iclass 25, count 0 2006.286.00:15:42.83#ibcon#wrote, iclass 25, count 0 2006.286.00:15:42.83#ibcon#about to read 3, iclass 25, count 0 2006.286.00:15:42.85#ibcon#read 3, iclass 25, count 0 2006.286.00:15:42.85#ibcon#about to read 4, iclass 25, count 0 2006.286.00:15:42.85#ibcon#read 4, iclass 25, count 0 2006.286.00:15:42.85#ibcon#about to read 5, iclass 25, count 0 2006.286.00:15:42.85#ibcon#read 5, iclass 25, count 0 2006.286.00:15:42.85#ibcon#about to read 6, iclass 25, count 0 2006.286.00:15:42.85#ibcon#read 6, iclass 25, count 0 2006.286.00:15:42.85#ibcon#end of sib2, iclass 25, count 0 2006.286.00:15:42.85#ibcon#*mode == 0, iclass 25, count 0 2006.286.00:15:42.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.00:15:42.85#ibcon#[27=USB\r\n] 2006.286.00:15:42.85#ibcon#*before write, iclass 25, count 0 2006.286.00:15:42.85#ibcon#enter sib2, iclass 25, count 0 2006.286.00:15:42.85#ibcon#flushed, iclass 25, count 0 2006.286.00:15:42.85#ibcon#about to write, iclass 25, count 0 2006.286.00:15:42.85#ibcon#wrote, iclass 25, count 0 2006.286.00:15:42.85#ibcon#about to read 3, iclass 25, count 0 2006.286.00:15:42.88#ibcon#read 3, iclass 25, count 0 2006.286.00:15:42.88#ibcon#about to read 4, iclass 25, count 0 2006.286.00:15:42.88#ibcon#read 4, iclass 25, count 0 2006.286.00:15:42.88#ibcon#about to read 5, iclass 25, count 0 2006.286.00:15:42.88#ibcon#read 5, iclass 25, count 0 2006.286.00:15:42.88#ibcon#about to read 6, iclass 25, count 0 2006.286.00:15:42.88#ibcon#read 6, iclass 25, count 0 2006.286.00:15:42.88#ibcon#end of sib2, iclass 25, count 0 2006.286.00:15:42.88#ibcon#*after write, iclass 25, count 0 2006.286.00:15:42.88#ibcon#*before return 0, iclass 25, count 0 2006.286.00:15:42.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:15:42.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:15:42.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.00:15:42.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.00:15:42.88$vck44/vblo=3,649.99 2006.286.00:15:42.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.00:15:42.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.00:15:42.88#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:42.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:15:42.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:15:42.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:15:42.88#ibcon#enter wrdev, iclass 27, count 0 2006.286.00:15:42.88#ibcon#first serial, iclass 27, count 0 2006.286.00:15:42.88#ibcon#enter sib2, iclass 27, count 0 2006.286.00:15:42.88#ibcon#flushed, iclass 27, count 0 2006.286.00:15:42.88#ibcon#about to write, iclass 27, count 0 2006.286.00:15:42.88#ibcon#wrote, iclass 27, count 0 2006.286.00:15:42.88#ibcon#about to read 3, iclass 27, count 0 2006.286.00:15:42.90#ibcon#read 3, iclass 27, count 0 2006.286.00:15:42.90#ibcon#about to read 4, iclass 27, count 0 2006.286.00:15:42.90#ibcon#read 4, iclass 27, count 0 2006.286.00:15:42.90#ibcon#about to read 5, iclass 27, count 0 2006.286.00:15:42.90#ibcon#read 5, iclass 27, count 0 2006.286.00:15:42.90#ibcon#about to read 6, iclass 27, count 0 2006.286.00:15:42.90#ibcon#read 6, iclass 27, count 0 2006.286.00:15:42.90#ibcon#end of sib2, iclass 27, count 0 2006.286.00:15:42.90#ibcon#*mode == 0, iclass 27, count 0 2006.286.00:15:42.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.00:15:42.90#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.00:15:42.90#ibcon#*before write, iclass 27, count 0 2006.286.00:15:42.90#ibcon#enter sib2, iclass 27, count 0 2006.286.00:15:42.90#ibcon#flushed, iclass 27, count 0 2006.286.00:15:42.90#ibcon#about to write, iclass 27, count 0 2006.286.00:15:42.90#ibcon#wrote, iclass 27, count 0 2006.286.00:15:42.90#ibcon#about to read 3, iclass 27, count 0 2006.286.00:15:42.94#ibcon#read 3, iclass 27, count 0 2006.286.00:15:42.94#ibcon#about to read 4, iclass 27, count 0 2006.286.00:15:42.94#ibcon#read 4, iclass 27, count 0 2006.286.00:15:42.94#ibcon#about to read 5, iclass 27, count 0 2006.286.00:15:42.94#ibcon#read 5, iclass 27, count 0 2006.286.00:15:42.94#ibcon#about to read 6, iclass 27, count 0 2006.286.00:15:42.94#ibcon#read 6, iclass 27, count 0 2006.286.00:15:42.94#ibcon#end of sib2, iclass 27, count 0 2006.286.00:15:42.94#ibcon#*after write, iclass 27, count 0 2006.286.00:15:42.94#ibcon#*before return 0, iclass 27, count 0 2006.286.00:15:42.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:15:42.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:15:42.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.00:15:42.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.00:15:42.94$vck44/vb=3,4 2006.286.00:15:42.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.00:15:42.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.00:15:42.94#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:42.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:15:43.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:15:43.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:15:43.00#ibcon#enter wrdev, iclass 29, count 2 2006.286.00:15:43.00#ibcon#first serial, iclass 29, count 2 2006.286.00:15:43.00#ibcon#enter sib2, iclass 29, count 2 2006.286.00:15:43.00#ibcon#flushed, iclass 29, count 2 2006.286.00:15:43.00#ibcon#about to write, iclass 29, count 2 2006.286.00:15:43.00#ibcon#wrote, iclass 29, count 2 2006.286.00:15:43.00#ibcon#about to read 3, iclass 29, count 2 2006.286.00:15:43.02#ibcon#read 3, iclass 29, count 2 2006.286.00:15:43.02#ibcon#about to read 4, iclass 29, count 2 2006.286.00:15:43.02#ibcon#read 4, iclass 29, count 2 2006.286.00:15:43.02#ibcon#about to read 5, iclass 29, count 2 2006.286.00:15:43.02#ibcon#read 5, iclass 29, count 2 2006.286.00:15:43.02#ibcon#about to read 6, iclass 29, count 2 2006.286.00:15:43.02#ibcon#read 6, iclass 29, count 2 2006.286.00:15:43.02#ibcon#end of sib2, iclass 29, count 2 2006.286.00:15:43.02#ibcon#*mode == 0, iclass 29, count 2 2006.286.00:15:43.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.00:15:43.02#ibcon#[27=AT03-04\r\n] 2006.286.00:15:43.02#ibcon#*before write, iclass 29, count 2 2006.286.00:15:43.02#ibcon#enter sib2, iclass 29, count 2 2006.286.00:15:43.02#ibcon#flushed, iclass 29, count 2 2006.286.00:15:43.02#ibcon#about to write, iclass 29, count 2 2006.286.00:15:43.02#ibcon#wrote, iclass 29, count 2 2006.286.00:15:43.02#ibcon#about to read 3, iclass 29, count 2 2006.286.00:15:43.05#ibcon#read 3, iclass 29, count 2 2006.286.00:15:43.05#ibcon#about to read 4, iclass 29, count 2 2006.286.00:15:43.05#ibcon#read 4, iclass 29, count 2 2006.286.00:15:43.05#ibcon#about to read 5, iclass 29, count 2 2006.286.00:15:43.05#ibcon#read 5, iclass 29, count 2 2006.286.00:15:43.05#ibcon#about to read 6, iclass 29, count 2 2006.286.00:15:43.05#ibcon#read 6, iclass 29, count 2 2006.286.00:15:43.05#ibcon#end of sib2, iclass 29, count 2 2006.286.00:15:43.05#ibcon#*after write, iclass 29, count 2 2006.286.00:15:43.05#ibcon#*before return 0, iclass 29, count 2 2006.286.00:15:43.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:15:43.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:15:43.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.00:15:43.05#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:43.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:15:43.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:15:43.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:15:43.17#ibcon#enter wrdev, iclass 29, count 0 2006.286.00:15:43.17#ibcon#first serial, iclass 29, count 0 2006.286.00:15:43.17#ibcon#enter sib2, iclass 29, count 0 2006.286.00:15:43.17#ibcon#flushed, iclass 29, count 0 2006.286.00:15:43.17#ibcon#about to write, iclass 29, count 0 2006.286.00:15:43.17#ibcon#wrote, iclass 29, count 0 2006.286.00:15:43.17#ibcon#about to read 3, iclass 29, count 0 2006.286.00:15:43.19#ibcon#read 3, iclass 29, count 0 2006.286.00:15:43.19#ibcon#about to read 4, iclass 29, count 0 2006.286.00:15:43.19#ibcon#read 4, iclass 29, count 0 2006.286.00:15:43.19#ibcon#about to read 5, iclass 29, count 0 2006.286.00:15:43.19#ibcon#read 5, iclass 29, count 0 2006.286.00:15:43.19#ibcon#about to read 6, iclass 29, count 0 2006.286.00:15:43.19#ibcon#read 6, iclass 29, count 0 2006.286.00:15:43.19#ibcon#end of sib2, iclass 29, count 0 2006.286.00:15:43.19#ibcon#*mode == 0, iclass 29, count 0 2006.286.00:15:43.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.00:15:43.19#ibcon#[27=USB\r\n] 2006.286.00:15:43.19#ibcon#*before write, iclass 29, count 0 2006.286.00:15:43.19#ibcon#enter sib2, iclass 29, count 0 2006.286.00:15:43.19#ibcon#flushed, iclass 29, count 0 2006.286.00:15:43.19#ibcon#about to write, iclass 29, count 0 2006.286.00:15:43.19#ibcon#wrote, iclass 29, count 0 2006.286.00:15:43.19#ibcon#about to read 3, iclass 29, count 0 2006.286.00:15:43.22#ibcon#read 3, iclass 29, count 0 2006.286.00:15:43.22#ibcon#about to read 4, iclass 29, count 0 2006.286.00:15:43.22#ibcon#read 4, iclass 29, count 0 2006.286.00:15:43.22#ibcon#about to read 5, iclass 29, count 0 2006.286.00:15:43.22#ibcon#read 5, iclass 29, count 0 2006.286.00:15:43.22#ibcon#about to read 6, iclass 29, count 0 2006.286.00:15:43.22#ibcon#read 6, iclass 29, count 0 2006.286.00:15:43.22#ibcon#end of sib2, iclass 29, count 0 2006.286.00:15:43.22#ibcon#*after write, iclass 29, count 0 2006.286.00:15:43.22#ibcon#*before return 0, iclass 29, count 0 2006.286.00:15:43.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:15:43.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:15:43.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.00:15:43.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.00:15:43.22$vck44/vblo=4,679.99 2006.286.00:15:43.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.00:15:43.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.00:15:43.22#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:43.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:15:43.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:15:43.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:15:43.22#ibcon#enter wrdev, iclass 31, count 0 2006.286.00:15:43.22#ibcon#first serial, iclass 31, count 0 2006.286.00:15:43.22#ibcon#enter sib2, iclass 31, count 0 2006.286.00:15:43.22#ibcon#flushed, iclass 31, count 0 2006.286.00:15:43.22#ibcon#about to write, iclass 31, count 0 2006.286.00:15:43.22#ibcon#wrote, iclass 31, count 0 2006.286.00:15:43.22#ibcon#about to read 3, iclass 31, count 0 2006.286.00:15:43.24#ibcon#read 3, iclass 31, count 0 2006.286.00:15:43.24#ibcon#about to read 4, iclass 31, count 0 2006.286.00:15:43.24#ibcon#read 4, iclass 31, count 0 2006.286.00:15:43.24#ibcon#about to read 5, iclass 31, count 0 2006.286.00:15:43.24#ibcon#read 5, iclass 31, count 0 2006.286.00:15:43.24#ibcon#about to read 6, iclass 31, count 0 2006.286.00:15:43.24#ibcon#read 6, iclass 31, count 0 2006.286.00:15:43.24#ibcon#end of sib2, iclass 31, count 0 2006.286.00:15:43.24#ibcon#*mode == 0, iclass 31, count 0 2006.286.00:15:43.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.00:15:43.24#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.00:15:43.24#ibcon#*before write, iclass 31, count 0 2006.286.00:15:43.24#ibcon#enter sib2, iclass 31, count 0 2006.286.00:15:43.24#ibcon#flushed, iclass 31, count 0 2006.286.00:15:43.24#ibcon#about to write, iclass 31, count 0 2006.286.00:15:43.24#ibcon#wrote, iclass 31, count 0 2006.286.00:15:43.24#ibcon#about to read 3, iclass 31, count 0 2006.286.00:15:43.28#ibcon#read 3, iclass 31, count 0 2006.286.00:15:43.28#ibcon#about to read 4, iclass 31, count 0 2006.286.00:15:43.28#ibcon#read 4, iclass 31, count 0 2006.286.00:15:43.28#ibcon#about to read 5, iclass 31, count 0 2006.286.00:15:43.28#ibcon#read 5, iclass 31, count 0 2006.286.00:15:43.28#ibcon#about to read 6, iclass 31, count 0 2006.286.00:15:43.28#ibcon#read 6, iclass 31, count 0 2006.286.00:15:43.28#ibcon#end of sib2, iclass 31, count 0 2006.286.00:15:43.28#ibcon#*after write, iclass 31, count 0 2006.286.00:15:43.28#ibcon#*before return 0, iclass 31, count 0 2006.286.00:15:43.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:15:43.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:15:43.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.00:15:43.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.00:15:43.28$vck44/vb=4,5 2006.286.00:15:43.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.00:15:43.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.00:15:43.28#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:43.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:15:43.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:15:43.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:15:43.34#ibcon#enter wrdev, iclass 33, count 2 2006.286.00:15:43.34#ibcon#first serial, iclass 33, count 2 2006.286.00:15:43.34#ibcon#enter sib2, iclass 33, count 2 2006.286.00:15:43.34#ibcon#flushed, iclass 33, count 2 2006.286.00:15:43.34#ibcon#about to write, iclass 33, count 2 2006.286.00:15:43.34#ibcon#wrote, iclass 33, count 2 2006.286.00:15:43.34#ibcon#about to read 3, iclass 33, count 2 2006.286.00:15:43.36#ibcon#read 3, iclass 33, count 2 2006.286.00:15:43.36#ibcon#about to read 4, iclass 33, count 2 2006.286.00:15:43.36#ibcon#read 4, iclass 33, count 2 2006.286.00:15:43.36#ibcon#about to read 5, iclass 33, count 2 2006.286.00:15:43.36#ibcon#read 5, iclass 33, count 2 2006.286.00:15:43.36#ibcon#about to read 6, iclass 33, count 2 2006.286.00:15:43.36#ibcon#read 6, iclass 33, count 2 2006.286.00:15:43.36#ibcon#end of sib2, iclass 33, count 2 2006.286.00:15:43.36#ibcon#*mode == 0, iclass 33, count 2 2006.286.00:15:43.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.00:15:43.36#ibcon#[27=AT04-05\r\n] 2006.286.00:15:43.36#ibcon#*before write, iclass 33, count 2 2006.286.00:15:43.36#ibcon#enter sib2, iclass 33, count 2 2006.286.00:15:43.36#ibcon#flushed, iclass 33, count 2 2006.286.00:15:43.36#ibcon#about to write, iclass 33, count 2 2006.286.00:15:43.36#ibcon#wrote, iclass 33, count 2 2006.286.00:15:43.36#ibcon#about to read 3, iclass 33, count 2 2006.286.00:15:43.39#ibcon#read 3, iclass 33, count 2 2006.286.00:15:43.39#ibcon#about to read 4, iclass 33, count 2 2006.286.00:15:43.39#ibcon#read 4, iclass 33, count 2 2006.286.00:15:43.39#ibcon#about to read 5, iclass 33, count 2 2006.286.00:15:43.39#ibcon#read 5, iclass 33, count 2 2006.286.00:15:43.39#ibcon#about to read 6, iclass 33, count 2 2006.286.00:15:43.39#ibcon#read 6, iclass 33, count 2 2006.286.00:15:43.39#ibcon#end of sib2, iclass 33, count 2 2006.286.00:15:43.39#ibcon#*after write, iclass 33, count 2 2006.286.00:15:43.39#ibcon#*before return 0, iclass 33, count 2 2006.286.00:15:43.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:15:43.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:15:43.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.00:15:43.39#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:43.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:15:43.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:15:43.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:15:43.51#ibcon#enter wrdev, iclass 33, count 0 2006.286.00:15:43.51#ibcon#first serial, iclass 33, count 0 2006.286.00:15:43.51#ibcon#enter sib2, iclass 33, count 0 2006.286.00:15:43.51#ibcon#flushed, iclass 33, count 0 2006.286.00:15:43.51#ibcon#about to write, iclass 33, count 0 2006.286.00:15:43.51#ibcon#wrote, iclass 33, count 0 2006.286.00:15:43.51#ibcon#about to read 3, iclass 33, count 0 2006.286.00:15:43.53#ibcon#read 3, iclass 33, count 0 2006.286.00:15:43.53#ibcon#about to read 4, iclass 33, count 0 2006.286.00:15:43.53#ibcon#read 4, iclass 33, count 0 2006.286.00:15:43.53#ibcon#about to read 5, iclass 33, count 0 2006.286.00:15:43.53#ibcon#read 5, iclass 33, count 0 2006.286.00:15:43.53#ibcon#about to read 6, iclass 33, count 0 2006.286.00:15:43.53#ibcon#read 6, iclass 33, count 0 2006.286.00:15:43.53#ibcon#end of sib2, iclass 33, count 0 2006.286.00:15:43.53#ibcon#*mode == 0, iclass 33, count 0 2006.286.00:15:43.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.00:15:43.53#ibcon#[27=USB\r\n] 2006.286.00:15:43.53#ibcon#*before write, iclass 33, count 0 2006.286.00:15:43.53#ibcon#enter sib2, iclass 33, count 0 2006.286.00:15:43.53#ibcon#flushed, iclass 33, count 0 2006.286.00:15:43.53#ibcon#about to write, iclass 33, count 0 2006.286.00:15:43.53#ibcon#wrote, iclass 33, count 0 2006.286.00:15:43.53#ibcon#about to read 3, iclass 33, count 0 2006.286.00:15:43.56#ibcon#read 3, iclass 33, count 0 2006.286.00:15:43.56#ibcon#about to read 4, iclass 33, count 0 2006.286.00:15:43.56#ibcon#read 4, iclass 33, count 0 2006.286.00:15:43.56#ibcon#about to read 5, iclass 33, count 0 2006.286.00:15:43.56#ibcon#read 5, iclass 33, count 0 2006.286.00:15:43.56#ibcon#about to read 6, iclass 33, count 0 2006.286.00:15:43.56#ibcon#read 6, iclass 33, count 0 2006.286.00:15:43.56#ibcon#end of sib2, iclass 33, count 0 2006.286.00:15:43.56#ibcon#*after write, iclass 33, count 0 2006.286.00:15:43.56#ibcon#*before return 0, iclass 33, count 0 2006.286.00:15:43.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:15:43.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:15:43.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.00:15:43.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.00:15:43.56$vck44/vblo=5,709.99 2006.286.00:15:43.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.00:15:43.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.00:15:43.56#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:43.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:15:43.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:15:43.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:15:43.56#ibcon#enter wrdev, iclass 35, count 0 2006.286.00:15:43.56#ibcon#first serial, iclass 35, count 0 2006.286.00:15:43.56#ibcon#enter sib2, iclass 35, count 0 2006.286.00:15:43.56#ibcon#flushed, iclass 35, count 0 2006.286.00:15:43.56#ibcon#about to write, iclass 35, count 0 2006.286.00:15:43.56#ibcon#wrote, iclass 35, count 0 2006.286.00:15:43.56#ibcon#about to read 3, iclass 35, count 0 2006.286.00:15:43.58#ibcon#read 3, iclass 35, count 0 2006.286.00:15:43.58#ibcon#about to read 4, iclass 35, count 0 2006.286.00:15:43.58#ibcon#read 4, iclass 35, count 0 2006.286.00:15:43.58#ibcon#about to read 5, iclass 35, count 0 2006.286.00:15:43.58#ibcon#read 5, iclass 35, count 0 2006.286.00:15:43.58#ibcon#about to read 6, iclass 35, count 0 2006.286.00:15:43.58#ibcon#read 6, iclass 35, count 0 2006.286.00:15:43.58#ibcon#end of sib2, iclass 35, count 0 2006.286.00:15:43.58#ibcon#*mode == 0, iclass 35, count 0 2006.286.00:15:43.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.00:15:43.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.00:15:43.58#ibcon#*before write, iclass 35, count 0 2006.286.00:15:43.58#ibcon#enter sib2, iclass 35, count 0 2006.286.00:15:43.58#ibcon#flushed, iclass 35, count 0 2006.286.00:15:43.58#ibcon#about to write, iclass 35, count 0 2006.286.00:15:43.58#ibcon#wrote, iclass 35, count 0 2006.286.00:15:43.58#ibcon#about to read 3, iclass 35, count 0 2006.286.00:15:43.62#ibcon#read 3, iclass 35, count 0 2006.286.00:15:43.62#ibcon#about to read 4, iclass 35, count 0 2006.286.00:15:43.62#ibcon#read 4, iclass 35, count 0 2006.286.00:15:43.62#ibcon#about to read 5, iclass 35, count 0 2006.286.00:15:43.62#ibcon#read 5, iclass 35, count 0 2006.286.00:15:43.62#ibcon#about to read 6, iclass 35, count 0 2006.286.00:15:43.62#ibcon#read 6, iclass 35, count 0 2006.286.00:15:43.62#ibcon#end of sib2, iclass 35, count 0 2006.286.00:15:43.62#ibcon#*after write, iclass 35, count 0 2006.286.00:15:43.62#ibcon#*before return 0, iclass 35, count 0 2006.286.00:15:43.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:15:43.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:15:43.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.00:15:43.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.00:15:43.62$vck44/vb=5,4 2006.286.00:15:43.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.00:15:43.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.00:15:43.62#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:43.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:15:43.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:15:43.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:15:43.68#ibcon#enter wrdev, iclass 37, count 2 2006.286.00:15:43.68#ibcon#first serial, iclass 37, count 2 2006.286.00:15:43.68#ibcon#enter sib2, iclass 37, count 2 2006.286.00:15:43.68#ibcon#flushed, iclass 37, count 2 2006.286.00:15:43.68#ibcon#about to write, iclass 37, count 2 2006.286.00:15:43.68#ibcon#wrote, iclass 37, count 2 2006.286.00:15:43.68#ibcon#about to read 3, iclass 37, count 2 2006.286.00:15:43.70#ibcon#read 3, iclass 37, count 2 2006.286.00:15:43.70#ibcon#about to read 4, iclass 37, count 2 2006.286.00:15:43.70#ibcon#read 4, iclass 37, count 2 2006.286.00:15:43.70#ibcon#about to read 5, iclass 37, count 2 2006.286.00:15:43.70#ibcon#read 5, iclass 37, count 2 2006.286.00:15:43.70#ibcon#about to read 6, iclass 37, count 2 2006.286.00:15:43.70#ibcon#read 6, iclass 37, count 2 2006.286.00:15:43.70#ibcon#end of sib2, iclass 37, count 2 2006.286.00:15:43.70#ibcon#*mode == 0, iclass 37, count 2 2006.286.00:15:43.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.00:15:43.70#ibcon#[27=AT05-04\r\n] 2006.286.00:15:43.70#ibcon#*before write, iclass 37, count 2 2006.286.00:15:43.70#ibcon#enter sib2, iclass 37, count 2 2006.286.00:15:43.70#ibcon#flushed, iclass 37, count 2 2006.286.00:15:43.70#ibcon#about to write, iclass 37, count 2 2006.286.00:15:43.70#ibcon#wrote, iclass 37, count 2 2006.286.00:15:43.70#ibcon#about to read 3, iclass 37, count 2 2006.286.00:15:43.73#ibcon#read 3, iclass 37, count 2 2006.286.00:15:43.73#ibcon#about to read 4, iclass 37, count 2 2006.286.00:15:43.73#ibcon#read 4, iclass 37, count 2 2006.286.00:15:43.73#ibcon#about to read 5, iclass 37, count 2 2006.286.00:15:43.73#ibcon#read 5, iclass 37, count 2 2006.286.00:15:43.73#ibcon#about to read 6, iclass 37, count 2 2006.286.00:15:43.73#ibcon#read 6, iclass 37, count 2 2006.286.00:15:43.73#ibcon#end of sib2, iclass 37, count 2 2006.286.00:15:43.73#ibcon#*after write, iclass 37, count 2 2006.286.00:15:43.73#ibcon#*before return 0, iclass 37, count 2 2006.286.00:15:43.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:15:43.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:15:43.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.00:15:43.73#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:43.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:15:43.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:15:43.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:15:43.85#ibcon#enter wrdev, iclass 37, count 0 2006.286.00:15:43.85#ibcon#first serial, iclass 37, count 0 2006.286.00:15:43.85#ibcon#enter sib2, iclass 37, count 0 2006.286.00:15:43.85#ibcon#flushed, iclass 37, count 0 2006.286.00:15:43.85#ibcon#about to write, iclass 37, count 0 2006.286.00:15:43.85#ibcon#wrote, iclass 37, count 0 2006.286.00:15:43.85#ibcon#about to read 3, iclass 37, count 0 2006.286.00:15:43.87#ibcon#read 3, iclass 37, count 0 2006.286.00:15:43.87#ibcon#about to read 4, iclass 37, count 0 2006.286.00:15:43.87#ibcon#read 4, iclass 37, count 0 2006.286.00:15:43.87#ibcon#about to read 5, iclass 37, count 0 2006.286.00:15:43.87#ibcon#read 5, iclass 37, count 0 2006.286.00:15:43.87#ibcon#about to read 6, iclass 37, count 0 2006.286.00:15:43.87#ibcon#read 6, iclass 37, count 0 2006.286.00:15:43.87#ibcon#end of sib2, iclass 37, count 0 2006.286.00:15:43.87#ibcon#*mode == 0, iclass 37, count 0 2006.286.00:15:43.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.00:15:43.87#ibcon#[27=USB\r\n] 2006.286.00:15:43.87#ibcon#*before write, iclass 37, count 0 2006.286.00:15:43.87#ibcon#enter sib2, iclass 37, count 0 2006.286.00:15:43.87#ibcon#flushed, iclass 37, count 0 2006.286.00:15:43.87#ibcon#about to write, iclass 37, count 0 2006.286.00:15:43.87#ibcon#wrote, iclass 37, count 0 2006.286.00:15:43.87#ibcon#about to read 3, iclass 37, count 0 2006.286.00:15:43.90#ibcon#read 3, iclass 37, count 0 2006.286.00:15:43.90#ibcon#about to read 4, iclass 37, count 0 2006.286.00:15:43.90#ibcon#read 4, iclass 37, count 0 2006.286.00:15:43.90#ibcon#about to read 5, iclass 37, count 0 2006.286.00:15:43.90#ibcon#read 5, iclass 37, count 0 2006.286.00:15:43.90#ibcon#about to read 6, iclass 37, count 0 2006.286.00:15:43.90#ibcon#read 6, iclass 37, count 0 2006.286.00:15:43.90#ibcon#end of sib2, iclass 37, count 0 2006.286.00:15:43.90#ibcon#*after write, iclass 37, count 0 2006.286.00:15:43.90#ibcon#*before return 0, iclass 37, count 0 2006.286.00:15:43.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:15:43.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:15:43.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.00:15:43.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.00:15:43.90$vck44/vblo=6,719.99 2006.286.00:15:43.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.00:15:43.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.00:15:43.90#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:43.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:15:43.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:15:43.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:15:43.90#ibcon#enter wrdev, iclass 39, count 0 2006.286.00:15:43.90#ibcon#first serial, iclass 39, count 0 2006.286.00:15:43.90#ibcon#enter sib2, iclass 39, count 0 2006.286.00:15:43.90#ibcon#flushed, iclass 39, count 0 2006.286.00:15:43.90#ibcon#about to write, iclass 39, count 0 2006.286.00:15:43.90#ibcon#wrote, iclass 39, count 0 2006.286.00:15:43.90#ibcon#about to read 3, iclass 39, count 0 2006.286.00:15:43.92#ibcon#read 3, iclass 39, count 0 2006.286.00:15:43.92#ibcon#about to read 4, iclass 39, count 0 2006.286.00:15:43.92#ibcon#read 4, iclass 39, count 0 2006.286.00:15:43.92#ibcon#about to read 5, iclass 39, count 0 2006.286.00:15:43.92#ibcon#read 5, iclass 39, count 0 2006.286.00:15:43.92#ibcon#about to read 6, iclass 39, count 0 2006.286.00:15:43.92#ibcon#read 6, iclass 39, count 0 2006.286.00:15:43.92#ibcon#end of sib2, iclass 39, count 0 2006.286.00:15:43.92#ibcon#*mode == 0, iclass 39, count 0 2006.286.00:15:43.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.00:15:43.92#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.00:15:43.92#ibcon#*before write, iclass 39, count 0 2006.286.00:15:43.92#ibcon#enter sib2, iclass 39, count 0 2006.286.00:15:43.92#ibcon#flushed, iclass 39, count 0 2006.286.00:15:43.92#ibcon#about to write, iclass 39, count 0 2006.286.00:15:43.92#ibcon#wrote, iclass 39, count 0 2006.286.00:15:43.92#ibcon#about to read 3, iclass 39, count 0 2006.286.00:15:43.96#ibcon#read 3, iclass 39, count 0 2006.286.00:15:43.96#ibcon#about to read 4, iclass 39, count 0 2006.286.00:15:43.96#ibcon#read 4, iclass 39, count 0 2006.286.00:15:43.96#ibcon#about to read 5, iclass 39, count 0 2006.286.00:15:43.96#ibcon#read 5, iclass 39, count 0 2006.286.00:15:43.96#ibcon#about to read 6, iclass 39, count 0 2006.286.00:15:43.96#ibcon#read 6, iclass 39, count 0 2006.286.00:15:43.96#ibcon#end of sib2, iclass 39, count 0 2006.286.00:15:43.96#ibcon#*after write, iclass 39, count 0 2006.286.00:15:43.96#ibcon#*before return 0, iclass 39, count 0 2006.286.00:15:43.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:15:43.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:15:43.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.00:15:43.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.00:15:43.96$vck44/vb=6,3 2006.286.00:15:43.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.00:15:43.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.00:15:43.96#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:43.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:15:44.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:15:44.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:15:44.02#ibcon#enter wrdev, iclass 3, count 2 2006.286.00:15:44.02#ibcon#first serial, iclass 3, count 2 2006.286.00:15:44.02#ibcon#enter sib2, iclass 3, count 2 2006.286.00:15:44.02#ibcon#flushed, iclass 3, count 2 2006.286.00:15:44.02#ibcon#about to write, iclass 3, count 2 2006.286.00:15:44.02#ibcon#wrote, iclass 3, count 2 2006.286.00:15:44.02#ibcon#about to read 3, iclass 3, count 2 2006.286.00:15:44.04#ibcon#read 3, iclass 3, count 2 2006.286.00:15:44.04#ibcon#about to read 4, iclass 3, count 2 2006.286.00:15:44.04#ibcon#read 4, iclass 3, count 2 2006.286.00:15:44.04#ibcon#about to read 5, iclass 3, count 2 2006.286.00:15:44.04#ibcon#read 5, iclass 3, count 2 2006.286.00:15:44.04#ibcon#about to read 6, iclass 3, count 2 2006.286.00:15:44.04#ibcon#read 6, iclass 3, count 2 2006.286.00:15:44.04#ibcon#end of sib2, iclass 3, count 2 2006.286.00:15:44.04#ibcon#*mode == 0, iclass 3, count 2 2006.286.00:15:44.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.00:15:44.04#ibcon#[27=AT06-03\r\n] 2006.286.00:15:44.04#ibcon#*before write, iclass 3, count 2 2006.286.00:15:44.04#ibcon#enter sib2, iclass 3, count 2 2006.286.00:15:44.04#ibcon#flushed, iclass 3, count 2 2006.286.00:15:44.04#ibcon#about to write, iclass 3, count 2 2006.286.00:15:44.04#ibcon#wrote, iclass 3, count 2 2006.286.00:15:44.04#ibcon#about to read 3, iclass 3, count 2 2006.286.00:15:44.07#ibcon#read 3, iclass 3, count 2 2006.286.00:15:44.07#ibcon#about to read 4, iclass 3, count 2 2006.286.00:15:44.07#ibcon#read 4, iclass 3, count 2 2006.286.00:15:44.07#ibcon#about to read 5, iclass 3, count 2 2006.286.00:15:44.07#ibcon#read 5, iclass 3, count 2 2006.286.00:15:44.07#ibcon#about to read 6, iclass 3, count 2 2006.286.00:15:44.07#ibcon#read 6, iclass 3, count 2 2006.286.00:15:44.07#ibcon#end of sib2, iclass 3, count 2 2006.286.00:15:44.07#ibcon#*after write, iclass 3, count 2 2006.286.00:15:44.07#ibcon#*before return 0, iclass 3, count 2 2006.286.00:15:44.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:15:44.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:15:44.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.00:15:44.07#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:44.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:15:44.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:15:44.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:15:44.19#ibcon#enter wrdev, iclass 3, count 0 2006.286.00:15:44.19#ibcon#first serial, iclass 3, count 0 2006.286.00:15:44.19#ibcon#enter sib2, iclass 3, count 0 2006.286.00:15:44.19#ibcon#flushed, iclass 3, count 0 2006.286.00:15:44.19#ibcon#about to write, iclass 3, count 0 2006.286.00:15:44.19#ibcon#wrote, iclass 3, count 0 2006.286.00:15:44.19#ibcon#about to read 3, iclass 3, count 0 2006.286.00:15:44.21#ibcon#read 3, iclass 3, count 0 2006.286.00:15:44.21#ibcon#about to read 4, iclass 3, count 0 2006.286.00:15:44.21#ibcon#read 4, iclass 3, count 0 2006.286.00:15:44.21#ibcon#about to read 5, iclass 3, count 0 2006.286.00:15:44.21#ibcon#read 5, iclass 3, count 0 2006.286.00:15:44.21#ibcon#about to read 6, iclass 3, count 0 2006.286.00:15:44.21#ibcon#read 6, iclass 3, count 0 2006.286.00:15:44.21#ibcon#end of sib2, iclass 3, count 0 2006.286.00:15:44.21#ibcon#*mode == 0, iclass 3, count 0 2006.286.00:15:44.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.00:15:44.21#ibcon#[27=USB\r\n] 2006.286.00:15:44.21#ibcon#*before write, iclass 3, count 0 2006.286.00:15:44.21#ibcon#enter sib2, iclass 3, count 0 2006.286.00:15:44.21#ibcon#flushed, iclass 3, count 0 2006.286.00:15:44.21#ibcon#about to write, iclass 3, count 0 2006.286.00:15:44.21#ibcon#wrote, iclass 3, count 0 2006.286.00:15:44.21#ibcon#about to read 3, iclass 3, count 0 2006.286.00:15:44.24#ibcon#read 3, iclass 3, count 0 2006.286.00:15:44.24#ibcon#about to read 4, iclass 3, count 0 2006.286.00:15:44.24#ibcon#read 4, iclass 3, count 0 2006.286.00:15:44.24#ibcon#about to read 5, iclass 3, count 0 2006.286.00:15:44.24#ibcon#read 5, iclass 3, count 0 2006.286.00:15:44.24#ibcon#about to read 6, iclass 3, count 0 2006.286.00:15:44.24#ibcon#read 6, iclass 3, count 0 2006.286.00:15:44.24#ibcon#end of sib2, iclass 3, count 0 2006.286.00:15:44.24#ibcon#*after write, iclass 3, count 0 2006.286.00:15:44.24#ibcon#*before return 0, iclass 3, count 0 2006.286.00:15:44.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:15:44.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:15:44.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.00:15:44.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.00:15:44.24$vck44/vblo=7,734.99 2006.286.00:15:44.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.00:15:44.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.00:15:44.24#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:44.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:15:44.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:15:44.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:15:44.24#ibcon#enter wrdev, iclass 5, count 0 2006.286.00:15:44.24#ibcon#first serial, iclass 5, count 0 2006.286.00:15:44.24#ibcon#enter sib2, iclass 5, count 0 2006.286.00:15:44.24#ibcon#flushed, iclass 5, count 0 2006.286.00:15:44.24#ibcon#about to write, iclass 5, count 0 2006.286.00:15:44.24#ibcon#wrote, iclass 5, count 0 2006.286.00:15:44.24#ibcon#about to read 3, iclass 5, count 0 2006.286.00:15:44.26#ibcon#read 3, iclass 5, count 0 2006.286.00:15:44.26#ibcon#about to read 4, iclass 5, count 0 2006.286.00:15:44.26#ibcon#read 4, iclass 5, count 0 2006.286.00:15:44.26#ibcon#about to read 5, iclass 5, count 0 2006.286.00:15:44.26#ibcon#read 5, iclass 5, count 0 2006.286.00:15:44.26#ibcon#about to read 6, iclass 5, count 0 2006.286.00:15:44.26#ibcon#read 6, iclass 5, count 0 2006.286.00:15:44.26#ibcon#end of sib2, iclass 5, count 0 2006.286.00:15:44.26#ibcon#*mode == 0, iclass 5, count 0 2006.286.00:15:44.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.00:15:44.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.00:15:44.26#ibcon#*before write, iclass 5, count 0 2006.286.00:15:44.26#ibcon#enter sib2, iclass 5, count 0 2006.286.00:15:44.26#ibcon#flushed, iclass 5, count 0 2006.286.00:15:44.26#ibcon#about to write, iclass 5, count 0 2006.286.00:15:44.26#ibcon#wrote, iclass 5, count 0 2006.286.00:15:44.26#ibcon#about to read 3, iclass 5, count 0 2006.286.00:15:44.30#ibcon#read 3, iclass 5, count 0 2006.286.00:15:44.30#ibcon#about to read 4, iclass 5, count 0 2006.286.00:15:44.30#ibcon#read 4, iclass 5, count 0 2006.286.00:15:44.30#ibcon#about to read 5, iclass 5, count 0 2006.286.00:15:44.30#ibcon#read 5, iclass 5, count 0 2006.286.00:15:44.30#ibcon#about to read 6, iclass 5, count 0 2006.286.00:15:44.30#ibcon#read 6, iclass 5, count 0 2006.286.00:15:44.30#ibcon#end of sib2, iclass 5, count 0 2006.286.00:15:44.30#ibcon#*after write, iclass 5, count 0 2006.286.00:15:44.30#ibcon#*before return 0, iclass 5, count 0 2006.286.00:15:44.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:15:44.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:15:44.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.00:15:44.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.00:15:44.30$vck44/vb=7,4 2006.286.00:15:44.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.00:15:44.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.00:15:44.30#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:44.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:15:44.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:15:44.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:15:44.36#ibcon#enter wrdev, iclass 7, count 2 2006.286.00:15:44.36#ibcon#first serial, iclass 7, count 2 2006.286.00:15:44.36#ibcon#enter sib2, iclass 7, count 2 2006.286.00:15:44.36#ibcon#flushed, iclass 7, count 2 2006.286.00:15:44.36#ibcon#about to write, iclass 7, count 2 2006.286.00:15:44.36#ibcon#wrote, iclass 7, count 2 2006.286.00:15:44.36#ibcon#about to read 3, iclass 7, count 2 2006.286.00:15:44.38#ibcon#read 3, iclass 7, count 2 2006.286.00:15:44.38#ibcon#about to read 4, iclass 7, count 2 2006.286.00:15:44.38#ibcon#read 4, iclass 7, count 2 2006.286.00:15:44.38#ibcon#about to read 5, iclass 7, count 2 2006.286.00:15:44.38#ibcon#read 5, iclass 7, count 2 2006.286.00:15:44.38#ibcon#about to read 6, iclass 7, count 2 2006.286.00:15:44.38#ibcon#read 6, iclass 7, count 2 2006.286.00:15:44.38#ibcon#end of sib2, iclass 7, count 2 2006.286.00:15:44.38#ibcon#*mode == 0, iclass 7, count 2 2006.286.00:15:44.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.00:15:44.38#ibcon#[27=AT07-04\r\n] 2006.286.00:15:44.38#ibcon#*before write, iclass 7, count 2 2006.286.00:15:44.38#ibcon#enter sib2, iclass 7, count 2 2006.286.00:15:44.38#ibcon#flushed, iclass 7, count 2 2006.286.00:15:44.38#ibcon#about to write, iclass 7, count 2 2006.286.00:15:44.38#ibcon#wrote, iclass 7, count 2 2006.286.00:15:44.38#ibcon#about to read 3, iclass 7, count 2 2006.286.00:15:44.41#ibcon#read 3, iclass 7, count 2 2006.286.00:15:44.41#ibcon#about to read 4, iclass 7, count 2 2006.286.00:15:44.41#ibcon#read 4, iclass 7, count 2 2006.286.00:15:44.41#ibcon#about to read 5, iclass 7, count 2 2006.286.00:15:44.41#ibcon#read 5, iclass 7, count 2 2006.286.00:15:44.41#ibcon#about to read 6, iclass 7, count 2 2006.286.00:15:44.41#ibcon#read 6, iclass 7, count 2 2006.286.00:15:44.41#ibcon#end of sib2, iclass 7, count 2 2006.286.00:15:44.41#ibcon#*after write, iclass 7, count 2 2006.286.00:15:44.41#ibcon#*before return 0, iclass 7, count 2 2006.286.00:15:44.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:15:44.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:15:44.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.00:15:44.41#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:44.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:15:44.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:15:44.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:15:44.53#ibcon#enter wrdev, iclass 7, count 0 2006.286.00:15:44.53#ibcon#first serial, iclass 7, count 0 2006.286.00:15:44.53#ibcon#enter sib2, iclass 7, count 0 2006.286.00:15:44.53#ibcon#flushed, iclass 7, count 0 2006.286.00:15:44.53#ibcon#about to write, iclass 7, count 0 2006.286.00:15:44.53#ibcon#wrote, iclass 7, count 0 2006.286.00:15:44.53#ibcon#about to read 3, iclass 7, count 0 2006.286.00:15:44.55#ibcon#read 3, iclass 7, count 0 2006.286.00:15:44.55#ibcon#about to read 4, iclass 7, count 0 2006.286.00:15:44.55#ibcon#read 4, iclass 7, count 0 2006.286.00:15:44.55#ibcon#about to read 5, iclass 7, count 0 2006.286.00:15:44.55#ibcon#read 5, iclass 7, count 0 2006.286.00:15:44.55#ibcon#about to read 6, iclass 7, count 0 2006.286.00:15:44.55#ibcon#read 6, iclass 7, count 0 2006.286.00:15:44.55#ibcon#end of sib2, iclass 7, count 0 2006.286.00:15:44.55#ibcon#*mode == 0, iclass 7, count 0 2006.286.00:15:44.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.00:15:44.55#ibcon#[27=USB\r\n] 2006.286.00:15:44.55#ibcon#*before write, iclass 7, count 0 2006.286.00:15:44.55#ibcon#enter sib2, iclass 7, count 0 2006.286.00:15:44.55#ibcon#flushed, iclass 7, count 0 2006.286.00:15:44.55#ibcon#about to write, iclass 7, count 0 2006.286.00:15:44.55#ibcon#wrote, iclass 7, count 0 2006.286.00:15:44.55#ibcon#about to read 3, iclass 7, count 0 2006.286.00:15:44.58#ibcon#read 3, iclass 7, count 0 2006.286.00:15:44.58#ibcon#about to read 4, iclass 7, count 0 2006.286.00:15:44.58#ibcon#read 4, iclass 7, count 0 2006.286.00:15:44.58#ibcon#about to read 5, iclass 7, count 0 2006.286.00:15:44.58#ibcon#read 5, iclass 7, count 0 2006.286.00:15:44.58#ibcon#about to read 6, iclass 7, count 0 2006.286.00:15:44.58#ibcon#read 6, iclass 7, count 0 2006.286.00:15:44.58#ibcon#end of sib2, iclass 7, count 0 2006.286.00:15:44.58#ibcon#*after write, iclass 7, count 0 2006.286.00:15:44.58#ibcon#*before return 0, iclass 7, count 0 2006.286.00:15:44.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:15:44.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:15:44.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.00:15:44.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.00:15:44.58$vck44/vblo=8,744.99 2006.286.00:15:44.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.00:15:44.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.00:15:44.58#ibcon#ireg 17 cls_cnt 0 2006.286.00:15:44.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:15:44.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:15:44.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:15:44.58#ibcon#enter wrdev, iclass 11, count 0 2006.286.00:15:44.58#ibcon#first serial, iclass 11, count 0 2006.286.00:15:44.58#ibcon#enter sib2, iclass 11, count 0 2006.286.00:15:44.58#ibcon#flushed, iclass 11, count 0 2006.286.00:15:44.58#ibcon#about to write, iclass 11, count 0 2006.286.00:15:44.58#ibcon#wrote, iclass 11, count 0 2006.286.00:15:44.58#ibcon#about to read 3, iclass 11, count 0 2006.286.00:15:44.60#ibcon#read 3, iclass 11, count 0 2006.286.00:15:44.60#ibcon#about to read 4, iclass 11, count 0 2006.286.00:15:44.60#ibcon#read 4, iclass 11, count 0 2006.286.00:15:44.60#ibcon#about to read 5, iclass 11, count 0 2006.286.00:15:44.60#ibcon#read 5, iclass 11, count 0 2006.286.00:15:44.60#ibcon#about to read 6, iclass 11, count 0 2006.286.00:15:44.60#ibcon#read 6, iclass 11, count 0 2006.286.00:15:44.60#ibcon#end of sib2, iclass 11, count 0 2006.286.00:15:44.60#ibcon#*mode == 0, iclass 11, count 0 2006.286.00:15:44.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.00:15:44.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.00:15:44.60#ibcon#*before write, iclass 11, count 0 2006.286.00:15:44.60#ibcon#enter sib2, iclass 11, count 0 2006.286.00:15:44.60#ibcon#flushed, iclass 11, count 0 2006.286.00:15:44.60#ibcon#about to write, iclass 11, count 0 2006.286.00:15:44.60#ibcon#wrote, iclass 11, count 0 2006.286.00:15:44.60#ibcon#about to read 3, iclass 11, count 0 2006.286.00:15:44.64#ibcon#read 3, iclass 11, count 0 2006.286.00:15:44.64#ibcon#about to read 4, iclass 11, count 0 2006.286.00:15:44.64#ibcon#read 4, iclass 11, count 0 2006.286.00:15:44.64#ibcon#about to read 5, iclass 11, count 0 2006.286.00:15:44.64#ibcon#read 5, iclass 11, count 0 2006.286.00:15:44.64#ibcon#about to read 6, iclass 11, count 0 2006.286.00:15:44.64#ibcon#read 6, iclass 11, count 0 2006.286.00:15:44.64#ibcon#end of sib2, iclass 11, count 0 2006.286.00:15:44.64#ibcon#*after write, iclass 11, count 0 2006.286.00:15:44.64#ibcon#*before return 0, iclass 11, count 0 2006.286.00:15:44.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:15:44.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:15:44.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.00:15:44.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.00:15:44.64$vck44/vb=8,4 2006.286.00:15:44.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.00:15:44.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.00:15:44.64#ibcon#ireg 11 cls_cnt 2 2006.286.00:15:44.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:15:44.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:15:44.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:15:44.70#ibcon#enter wrdev, iclass 13, count 2 2006.286.00:15:44.70#ibcon#first serial, iclass 13, count 2 2006.286.00:15:44.70#ibcon#enter sib2, iclass 13, count 2 2006.286.00:15:44.70#ibcon#flushed, iclass 13, count 2 2006.286.00:15:44.70#ibcon#about to write, iclass 13, count 2 2006.286.00:15:44.70#ibcon#wrote, iclass 13, count 2 2006.286.00:15:44.70#ibcon#about to read 3, iclass 13, count 2 2006.286.00:15:44.72#ibcon#read 3, iclass 13, count 2 2006.286.00:15:44.72#ibcon#about to read 4, iclass 13, count 2 2006.286.00:15:44.72#ibcon#read 4, iclass 13, count 2 2006.286.00:15:44.72#ibcon#about to read 5, iclass 13, count 2 2006.286.00:15:44.72#ibcon#read 5, iclass 13, count 2 2006.286.00:15:44.72#ibcon#about to read 6, iclass 13, count 2 2006.286.00:15:44.72#ibcon#read 6, iclass 13, count 2 2006.286.00:15:44.72#ibcon#end of sib2, iclass 13, count 2 2006.286.00:15:44.72#ibcon#*mode == 0, iclass 13, count 2 2006.286.00:15:44.72#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.00:15:44.72#ibcon#[27=AT08-04\r\n] 2006.286.00:15:44.72#ibcon#*before write, iclass 13, count 2 2006.286.00:15:44.72#ibcon#enter sib2, iclass 13, count 2 2006.286.00:15:44.72#ibcon#flushed, iclass 13, count 2 2006.286.00:15:44.72#ibcon#about to write, iclass 13, count 2 2006.286.00:15:44.72#ibcon#wrote, iclass 13, count 2 2006.286.00:15:44.72#ibcon#about to read 3, iclass 13, count 2 2006.286.00:15:44.75#ibcon#read 3, iclass 13, count 2 2006.286.00:15:44.75#ibcon#about to read 4, iclass 13, count 2 2006.286.00:15:44.75#ibcon#read 4, iclass 13, count 2 2006.286.00:15:44.75#ibcon#about to read 5, iclass 13, count 2 2006.286.00:15:44.75#ibcon#read 5, iclass 13, count 2 2006.286.00:15:44.75#ibcon#about to read 6, iclass 13, count 2 2006.286.00:15:44.75#ibcon#read 6, iclass 13, count 2 2006.286.00:15:44.75#ibcon#end of sib2, iclass 13, count 2 2006.286.00:15:44.75#ibcon#*after write, iclass 13, count 2 2006.286.00:15:44.75#ibcon#*before return 0, iclass 13, count 2 2006.286.00:15:44.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:15:44.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:15:44.75#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.00:15:44.75#ibcon#ireg 7 cls_cnt 0 2006.286.00:15:44.75#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:15:44.87#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:15:44.87#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:15:44.87#ibcon#enter wrdev, iclass 13, count 0 2006.286.00:15:44.87#ibcon#first serial, iclass 13, count 0 2006.286.00:15:44.87#ibcon#enter sib2, iclass 13, count 0 2006.286.00:15:44.87#ibcon#flushed, iclass 13, count 0 2006.286.00:15:44.87#ibcon#about to write, iclass 13, count 0 2006.286.00:15:44.87#ibcon#wrote, iclass 13, count 0 2006.286.00:15:44.87#ibcon#about to read 3, iclass 13, count 0 2006.286.00:15:44.89#ibcon#read 3, iclass 13, count 0 2006.286.00:15:44.89#ibcon#about to read 4, iclass 13, count 0 2006.286.00:15:44.89#ibcon#read 4, iclass 13, count 0 2006.286.00:15:44.89#ibcon#about to read 5, iclass 13, count 0 2006.286.00:15:44.89#ibcon#read 5, iclass 13, count 0 2006.286.00:15:44.89#ibcon#about to read 6, iclass 13, count 0 2006.286.00:15:44.89#ibcon#read 6, iclass 13, count 0 2006.286.00:15:44.89#ibcon#end of sib2, iclass 13, count 0 2006.286.00:15:44.89#ibcon#*mode == 0, iclass 13, count 0 2006.286.00:15:44.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.00:15:44.89#ibcon#[27=USB\r\n] 2006.286.00:15:44.89#ibcon#*before write, iclass 13, count 0 2006.286.00:15:44.89#ibcon#enter sib2, iclass 13, count 0 2006.286.00:15:44.89#ibcon#flushed, iclass 13, count 0 2006.286.00:15:44.89#ibcon#about to write, iclass 13, count 0 2006.286.00:15:44.89#ibcon#wrote, iclass 13, count 0 2006.286.00:15:44.89#ibcon#about to read 3, iclass 13, count 0 2006.286.00:15:44.92#ibcon#read 3, iclass 13, count 0 2006.286.00:15:44.92#ibcon#about to read 4, iclass 13, count 0 2006.286.00:15:44.92#ibcon#read 4, iclass 13, count 0 2006.286.00:15:44.92#ibcon#about to read 5, iclass 13, count 0 2006.286.00:15:44.92#ibcon#read 5, iclass 13, count 0 2006.286.00:15:44.92#ibcon#about to read 6, iclass 13, count 0 2006.286.00:15:44.92#ibcon#read 6, iclass 13, count 0 2006.286.00:15:44.92#ibcon#end of sib2, iclass 13, count 0 2006.286.00:15:44.92#ibcon#*after write, iclass 13, count 0 2006.286.00:15:44.92#ibcon#*before return 0, iclass 13, count 0 2006.286.00:15:44.92#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:15:44.92#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:15:44.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.00:15:44.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.00:15:44.92$vck44/vabw=wide 2006.286.00:15:44.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.00:15:44.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.00:15:44.92#ibcon#ireg 8 cls_cnt 0 2006.286.00:15:44.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:15:44.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:15:44.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:15:44.92#ibcon#enter wrdev, iclass 15, count 0 2006.286.00:15:44.92#ibcon#first serial, iclass 15, count 0 2006.286.00:15:44.92#ibcon#enter sib2, iclass 15, count 0 2006.286.00:15:44.92#ibcon#flushed, iclass 15, count 0 2006.286.00:15:44.92#ibcon#about to write, iclass 15, count 0 2006.286.00:15:44.92#ibcon#wrote, iclass 15, count 0 2006.286.00:15:44.92#ibcon#about to read 3, iclass 15, count 0 2006.286.00:15:44.94#ibcon#read 3, iclass 15, count 0 2006.286.00:15:44.94#ibcon#about to read 4, iclass 15, count 0 2006.286.00:15:44.94#ibcon#read 4, iclass 15, count 0 2006.286.00:15:44.94#ibcon#about to read 5, iclass 15, count 0 2006.286.00:15:44.94#ibcon#read 5, iclass 15, count 0 2006.286.00:15:44.94#ibcon#about to read 6, iclass 15, count 0 2006.286.00:15:44.94#ibcon#read 6, iclass 15, count 0 2006.286.00:15:44.94#ibcon#end of sib2, iclass 15, count 0 2006.286.00:15:44.94#ibcon#*mode == 0, iclass 15, count 0 2006.286.00:15:44.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.00:15:44.94#ibcon#[25=BW32\r\n] 2006.286.00:15:44.94#ibcon#*before write, iclass 15, count 0 2006.286.00:15:44.94#ibcon#enter sib2, iclass 15, count 0 2006.286.00:15:44.94#ibcon#flushed, iclass 15, count 0 2006.286.00:15:44.94#ibcon#about to write, iclass 15, count 0 2006.286.00:15:44.94#ibcon#wrote, iclass 15, count 0 2006.286.00:15:44.94#ibcon#about to read 3, iclass 15, count 0 2006.286.00:15:44.97#ibcon#read 3, iclass 15, count 0 2006.286.00:15:44.97#ibcon#about to read 4, iclass 15, count 0 2006.286.00:15:44.97#ibcon#read 4, iclass 15, count 0 2006.286.00:15:44.97#ibcon#about to read 5, iclass 15, count 0 2006.286.00:15:44.97#ibcon#read 5, iclass 15, count 0 2006.286.00:15:44.97#ibcon#about to read 6, iclass 15, count 0 2006.286.00:15:44.97#ibcon#read 6, iclass 15, count 0 2006.286.00:15:44.97#ibcon#end of sib2, iclass 15, count 0 2006.286.00:15:44.97#ibcon#*after write, iclass 15, count 0 2006.286.00:15:44.97#ibcon#*before return 0, iclass 15, count 0 2006.286.00:15:44.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:15:44.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:15:44.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.00:15:44.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.00:15:44.97$vck44/vbbw=wide 2006.286.00:15:44.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.00:15:44.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.00:15:44.97#ibcon#ireg 8 cls_cnt 0 2006.286.00:15:44.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:15:45.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:15:45.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:15:45.04#ibcon#enter wrdev, iclass 17, count 0 2006.286.00:15:45.04#ibcon#first serial, iclass 17, count 0 2006.286.00:15:45.04#ibcon#enter sib2, iclass 17, count 0 2006.286.00:15:45.04#ibcon#flushed, iclass 17, count 0 2006.286.00:15:45.04#ibcon#about to write, iclass 17, count 0 2006.286.00:15:45.04#ibcon#wrote, iclass 17, count 0 2006.286.00:15:45.04#ibcon#about to read 3, iclass 17, count 0 2006.286.00:15:45.06#ibcon#read 3, iclass 17, count 0 2006.286.00:15:45.06#ibcon#about to read 4, iclass 17, count 0 2006.286.00:15:45.06#ibcon#read 4, iclass 17, count 0 2006.286.00:15:45.06#ibcon#about to read 5, iclass 17, count 0 2006.286.00:15:45.06#ibcon#read 5, iclass 17, count 0 2006.286.00:15:45.06#ibcon#about to read 6, iclass 17, count 0 2006.286.00:15:45.06#ibcon#read 6, iclass 17, count 0 2006.286.00:15:45.06#ibcon#end of sib2, iclass 17, count 0 2006.286.00:15:45.06#ibcon#*mode == 0, iclass 17, count 0 2006.286.00:15:45.06#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.00:15:45.06#ibcon#[27=BW32\r\n] 2006.286.00:15:45.06#ibcon#*before write, iclass 17, count 0 2006.286.00:15:45.06#ibcon#enter sib2, iclass 17, count 0 2006.286.00:15:45.06#ibcon#flushed, iclass 17, count 0 2006.286.00:15:45.06#ibcon#about to write, iclass 17, count 0 2006.286.00:15:45.06#ibcon#wrote, iclass 17, count 0 2006.286.00:15:45.06#ibcon#about to read 3, iclass 17, count 0 2006.286.00:15:45.09#ibcon#read 3, iclass 17, count 0 2006.286.00:15:45.09#ibcon#about to read 4, iclass 17, count 0 2006.286.00:15:45.09#ibcon#read 4, iclass 17, count 0 2006.286.00:15:45.09#ibcon#about to read 5, iclass 17, count 0 2006.286.00:15:45.09#ibcon#read 5, iclass 17, count 0 2006.286.00:15:45.09#ibcon#about to read 6, iclass 17, count 0 2006.286.00:15:45.09#ibcon#read 6, iclass 17, count 0 2006.286.00:15:45.09#ibcon#end of sib2, iclass 17, count 0 2006.286.00:15:45.09#ibcon#*after write, iclass 17, count 0 2006.286.00:15:45.09#ibcon#*before return 0, iclass 17, count 0 2006.286.00:15:45.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:15:45.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:15:45.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.00:15:45.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.00:15:45.09$setupk4/ifdk4 2006.286.00:15:45.09$ifdk4/lo= 2006.286.00:15:45.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.00:15:45.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.00:15:45.09$ifdk4/patch= 2006.286.00:15:45.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.00:15:45.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.00:15:45.09$setupk4/!*+20s 2006.286.00:15:48.42#abcon#<5=/03 2.9 6.5 19.83 851016.5\r\n> 2006.286.00:15:48.44#abcon#{5=INTERFACE CLEAR} 2006.286.00:15:48.50#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:15:52.13#trakl#Source acquired 2006.286.00:15:53.13#flagr#flagr/antenna,acquired 2006.286.00:15:58.59#abcon#<5=/03 2.9 6.5 19.83 851016.4\r\n> 2006.286.00:15:58.61#abcon#{5=INTERFACE CLEAR} 2006.286.00:15:58.67#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:15:59.58$setupk4/"tpicd 2006.286.00:15:59.58$setupk4/echo=off 2006.286.00:15:59.58$setupk4/xlog=off 2006.286.00:15:59.58:!2006.286.00:19:29 2006.286.00:19:29.01:preob 2006.286.00:19:30.14/onsource/TRACKING 2006.286.00:19:30.15:!2006.286.00:19:39 2006.286.00:19:39.01:"tape 2006.286.00:19:39.01:"st=record 2006.286.00:19:39.02:data_valid=on 2006.286.00:19:39.02:midob 2006.286.00:19:40.14/onsource/TRACKING 2006.286.00:19:40.15/wx/19.84,1016.4,86 2006.286.00:19:40.33/cable/+6.5065E-03 2006.286.00:19:41.42/va/01,07,usb,yes,33,35 2006.286.00:19:41.42/va/02,06,usb,yes,33,33 2006.286.00:19:41.42/va/03,07,usb,yes,32,34 2006.286.00:19:41.42/va/04,06,usb,yes,34,35 2006.286.00:19:41.42/va/05,03,usb,yes,33,34 2006.286.00:19:41.42/va/06,04,usb,yes,30,29 2006.286.00:19:41.42/va/07,04,usb,yes,31,31 2006.286.00:19:41.42/va/08,03,usb,yes,31,38 2006.286.00:19:41.65/valo/01,524.99,yes,locked 2006.286.00:19:41.65/valo/02,534.99,yes,locked 2006.286.00:19:41.65/valo/03,564.99,yes,locked 2006.286.00:19:41.65/valo/04,624.99,yes,locked 2006.286.00:19:41.65/valo/05,734.99,yes,locked 2006.286.00:19:41.65/valo/06,814.99,yes,locked 2006.286.00:19:41.65/valo/07,864.99,yes,locked 2006.286.00:19:41.65/valo/08,884.99,yes,locked 2006.286.00:19:42.74/vb/01,04,usb,yes,31,29 2006.286.00:19:42.74/vb/02,05,usb,yes,29,29 2006.286.00:19:42.74/vb/03,04,usb,yes,30,33 2006.286.00:19:42.74/vb/04,05,usb,yes,30,29 2006.286.00:19:42.74/vb/05,04,usb,yes,27,29 2006.286.00:19:42.74/vb/06,03,usb,yes,38,34 2006.286.00:19:42.74/vb/07,04,usb,yes,31,31 2006.286.00:19:42.74/vb/08,04,usb,yes,28,32 2006.286.00:19:42.97/vblo/01,629.99,yes,locked 2006.286.00:19:42.97/vblo/02,634.99,yes,locked 2006.286.00:19:42.97/vblo/03,649.99,yes,locked 2006.286.00:19:42.97/vblo/04,679.99,yes,locked 2006.286.00:19:42.97/vblo/05,709.99,yes,locked 2006.286.00:19:42.97/vblo/06,719.99,yes,locked 2006.286.00:19:42.97/vblo/07,734.99,yes,locked 2006.286.00:19:42.97/vblo/08,744.99,yes,locked 2006.286.00:19:43.12/vabw/8 2006.286.00:19:43.27/vbbw/8 2006.286.00:19:43.36/xfe/off,on,12.0 2006.286.00:19:43.73/ifatt/23,28,28,28 2006.286.00:19:44.07/fmout-gps/S +2.79E-07 2006.286.00:19:44.09:!2006.286.00:20:29 2006.286.00:20:29.00:data_valid=off 2006.286.00:20:29.00:"et 2006.286.00:20:29.01:!+3s 2006.286.00:20:32.03:"tape 2006.286.00:20:32.03:postob 2006.286.00:20:32.11/cable/+6.5059E-03 2006.286.00:20:32.11/wx/19.85,1016.4,86 2006.286.00:20:32.16/fmout-gps/S +2.77E-07 2006.286.00:20:32.16:scan_name=286-0023,jd0610,70 2006.286.00:20:32.17:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.286.00:20:34.14#flagr#flagr/antenna,new-source 2006.286.00:20:34.15:checkk5 2006.286.00:20:34.54/chk_autoobs//k5ts1/ autoobs is running! 2006.286.00:20:34.90/chk_autoobs//k5ts2/ autoobs is running! 2006.286.00:20:35.34/chk_autoobs//k5ts3/ autoobs is running! 2006.286.00:20:35.76/chk_autoobs//k5ts4/ autoobs is running! 2006.286.00:20:36.12/chk_obsdata//k5ts1/T2860019??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.00:20:36.59/chk_obsdata//k5ts2/T2860019??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.00:20:37.01/chk_obsdata//k5ts3/T2860019??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.00:20:37.38/chk_obsdata//k5ts4/T2860019??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.00:20:38.15/k5log//k5ts1_log_newline 2006.286.00:20:38.92/k5log//k5ts2_log_newline 2006.286.00:20:39.73/k5log//k5ts3_log_newline 2006.286.00:20:40.56/k5log//k5ts4_log_newline 2006.286.00:20:40.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.00:20:40.58:setupk4=1 2006.286.00:20:40.58$setupk4/echo=on 2006.286.00:20:40.58$setupk4/pcalon 2006.286.00:20:40.58$pcalon/"no phase cal control is implemented here 2006.286.00:20:40.58$setupk4/"tpicd=stop 2006.286.00:20:40.58$setupk4/"rec=synch_on 2006.286.00:20:40.58$setupk4/"rec_mode=128 2006.286.00:20:40.58$setupk4/!* 2006.286.00:20:40.58$setupk4/recpk4 2006.286.00:20:40.58$recpk4/recpatch= 2006.286.00:20:40.58$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.00:20:40.58$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.00:20:40.58$setupk4/vck44 2006.286.00:20:40.59$vck44/valo=1,524.99 2006.286.00:20:40.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.00:20:40.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.00:20:40.59#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:40.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:20:40.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:20:40.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:20:40.59#ibcon#enter wrdev, iclass 30, count 0 2006.286.00:20:40.59#ibcon#first serial, iclass 30, count 0 2006.286.00:20:40.59#ibcon#enter sib2, iclass 30, count 0 2006.286.00:20:40.59#ibcon#flushed, iclass 30, count 0 2006.286.00:20:40.59#ibcon#about to write, iclass 30, count 0 2006.286.00:20:40.59#ibcon#wrote, iclass 30, count 0 2006.286.00:20:40.59#ibcon#about to read 3, iclass 30, count 0 2006.286.00:20:40.60#ibcon#read 3, iclass 30, count 0 2006.286.00:20:40.60#ibcon#about to read 4, iclass 30, count 0 2006.286.00:20:40.60#ibcon#read 4, iclass 30, count 0 2006.286.00:20:40.60#ibcon#about to read 5, iclass 30, count 0 2006.286.00:20:40.60#ibcon#read 5, iclass 30, count 0 2006.286.00:20:40.60#ibcon#about to read 6, iclass 30, count 0 2006.286.00:20:40.60#ibcon#read 6, iclass 30, count 0 2006.286.00:20:40.60#ibcon#end of sib2, iclass 30, count 0 2006.286.00:20:40.60#ibcon#*mode == 0, iclass 30, count 0 2006.286.00:20:40.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.00:20:40.60#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.00:20:40.60#ibcon#*before write, iclass 30, count 0 2006.286.00:20:40.60#ibcon#enter sib2, iclass 30, count 0 2006.286.00:20:40.60#ibcon#flushed, iclass 30, count 0 2006.286.00:20:40.60#ibcon#about to write, iclass 30, count 0 2006.286.00:20:40.60#ibcon#wrote, iclass 30, count 0 2006.286.00:20:40.60#ibcon#about to read 3, iclass 30, count 0 2006.286.00:20:40.65#ibcon#read 3, iclass 30, count 0 2006.286.00:20:40.65#ibcon#about to read 4, iclass 30, count 0 2006.286.00:20:40.65#ibcon#read 4, iclass 30, count 0 2006.286.00:20:40.65#ibcon#about to read 5, iclass 30, count 0 2006.286.00:20:40.65#ibcon#read 5, iclass 30, count 0 2006.286.00:20:40.65#ibcon#about to read 6, iclass 30, count 0 2006.286.00:20:40.65#ibcon#read 6, iclass 30, count 0 2006.286.00:20:40.65#ibcon#end of sib2, iclass 30, count 0 2006.286.00:20:40.65#ibcon#*after write, iclass 30, count 0 2006.286.00:20:40.65#ibcon#*before return 0, iclass 30, count 0 2006.286.00:20:40.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:20:40.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:20:40.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.00:20:40.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.00:20:40.65$vck44/va=1,7 2006.286.00:20:40.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.00:20:40.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.00:20:40.65#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:40.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.00:20:40.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.00:20:40.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.00:20:40.65#ibcon#enter wrdev, iclass 32, count 2 2006.286.00:20:40.65#ibcon#first serial, iclass 32, count 2 2006.286.00:20:40.65#ibcon#enter sib2, iclass 32, count 2 2006.286.00:20:40.65#ibcon#flushed, iclass 32, count 2 2006.286.00:20:40.65#ibcon#about to write, iclass 32, count 2 2006.286.00:20:40.65#ibcon#wrote, iclass 32, count 2 2006.286.00:20:40.65#ibcon#about to read 3, iclass 32, count 2 2006.286.00:20:40.67#ibcon#read 3, iclass 32, count 2 2006.286.00:20:40.67#ibcon#about to read 4, iclass 32, count 2 2006.286.00:20:40.67#ibcon#read 4, iclass 32, count 2 2006.286.00:20:40.67#ibcon#about to read 5, iclass 32, count 2 2006.286.00:20:40.67#ibcon#read 5, iclass 32, count 2 2006.286.00:20:40.67#ibcon#about to read 6, iclass 32, count 2 2006.286.00:20:40.67#ibcon#read 6, iclass 32, count 2 2006.286.00:20:40.67#ibcon#end of sib2, iclass 32, count 2 2006.286.00:20:40.67#ibcon#*mode == 0, iclass 32, count 2 2006.286.00:20:40.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.00:20:40.67#ibcon#[25=AT01-07\r\n] 2006.286.00:20:40.67#ibcon#*before write, iclass 32, count 2 2006.286.00:20:40.67#ibcon#enter sib2, iclass 32, count 2 2006.286.00:20:40.67#ibcon#flushed, iclass 32, count 2 2006.286.00:20:40.67#ibcon#about to write, iclass 32, count 2 2006.286.00:20:40.67#ibcon#wrote, iclass 32, count 2 2006.286.00:20:40.67#ibcon#about to read 3, iclass 32, count 2 2006.286.00:20:40.70#ibcon#read 3, iclass 32, count 2 2006.286.00:20:40.70#ibcon#about to read 4, iclass 32, count 2 2006.286.00:20:40.70#ibcon#read 4, iclass 32, count 2 2006.286.00:20:40.70#ibcon#about to read 5, iclass 32, count 2 2006.286.00:20:40.70#ibcon#read 5, iclass 32, count 2 2006.286.00:20:40.70#ibcon#about to read 6, iclass 32, count 2 2006.286.00:20:40.70#ibcon#read 6, iclass 32, count 2 2006.286.00:20:40.70#ibcon#end of sib2, iclass 32, count 2 2006.286.00:20:40.70#ibcon#*after write, iclass 32, count 2 2006.286.00:20:40.70#ibcon#*before return 0, iclass 32, count 2 2006.286.00:20:40.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.00:20:40.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.00:20:40.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.00:20:40.70#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:40.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.00:20:40.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.00:20:40.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.00:20:40.82#ibcon#enter wrdev, iclass 32, count 0 2006.286.00:20:40.82#ibcon#first serial, iclass 32, count 0 2006.286.00:20:40.82#ibcon#enter sib2, iclass 32, count 0 2006.286.00:20:40.82#ibcon#flushed, iclass 32, count 0 2006.286.00:20:40.82#ibcon#about to write, iclass 32, count 0 2006.286.00:20:40.82#ibcon#wrote, iclass 32, count 0 2006.286.00:20:40.82#ibcon#about to read 3, iclass 32, count 0 2006.286.00:20:40.84#ibcon#read 3, iclass 32, count 0 2006.286.00:20:40.84#ibcon#about to read 4, iclass 32, count 0 2006.286.00:20:40.84#ibcon#read 4, iclass 32, count 0 2006.286.00:20:40.84#ibcon#about to read 5, iclass 32, count 0 2006.286.00:20:40.84#ibcon#read 5, iclass 32, count 0 2006.286.00:20:40.84#ibcon#about to read 6, iclass 32, count 0 2006.286.00:20:40.84#ibcon#read 6, iclass 32, count 0 2006.286.00:20:40.84#ibcon#end of sib2, iclass 32, count 0 2006.286.00:20:40.84#ibcon#*mode == 0, iclass 32, count 0 2006.286.00:20:40.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.00:20:40.84#ibcon#[25=USB\r\n] 2006.286.00:20:40.84#ibcon#*before write, iclass 32, count 0 2006.286.00:20:40.84#ibcon#enter sib2, iclass 32, count 0 2006.286.00:20:40.84#ibcon#flushed, iclass 32, count 0 2006.286.00:20:40.84#ibcon#about to write, iclass 32, count 0 2006.286.00:20:40.84#ibcon#wrote, iclass 32, count 0 2006.286.00:20:40.84#ibcon#about to read 3, iclass 32, count 0 2006.286.00:20:40.87#ibcon#read 3, iclass 32, count 0 2006.286.00:20:40.87#ibcon#about to read 4, iclass 32, count 0 2006.286.00:20:40.87#ibcon#read 4, iclass 32, count 0 2006.286.00:20:40.87#ibcon#about to read 5, iclass 32, count 0 2006.286.00:20:40.87#ibcon#read 5, iclass 32, count 0 2006.286.00:20:40.87#ibcon#about to read 6, iclass 32, count 0 2006.286.00:20:40.87#ibcon#read 6, iclass 32, count 0 2006.286.00:20:40.87#ibcon#end of sib2, iclass 32, count 0 2006.286.00:20:40.87#ibcon#*after write, iclass 32, count 0 2006.286.00:20:40.87#ibcon#*before return 0, iclass 32, count 0 2006.286.00:20:40.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.00:20:40.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.00:20:40.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.00:20:40.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.00:20:40.87$vck44/valo=2,534.99 2006.286.00:20:40.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.00:20:40.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.00:20:40.87#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:40.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:20:40.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:20:40.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:20:40.87#ibcon#enter wrdev, iclass 34, count 0 2006.286.00:20:40.87#ibcon#first serial, iclass 34, count 0 2006.286.00:20:40.87#ibcon#enter sib2, iclass 34, count 0 2006.286.00:20:40.87#ibcon#flushed, iclass 34, count 0 2006.286.00:20:40.87#ibcon#about to write, iclass 34, count 0 2006.286.00:20:40.87#ibcon#wrote, iclass 34, count 0 2006.286.00:20:40.87#ibcon#about to read 3, iclass 34, count 0 2006.286.00:20:40.89#ibcon#read 3, iclass 34, count 0 2006.286.00:20:40.89#ibcon#about to read 4, iclass 34, count 0 2006.286.00:20:40.89#ibcon#read 4, iclass 34, count 0 2006.286.00:20:40.89#ibcon#about to read 5, iclass 34, count 0 2006.286.00:20:40.89#ibcon#read 5, iclass 34, count 0 2006.286.00:20:40.89#ibcon#about to read 6, iclass 34, count 0 2006.286.00:20:40.89#ibcon#read 6, iclass 34, count 0 2006.286.00:20:40.89#ibcon#end of sib2, iclass 34, count 0 2006.286.00:20:40.89#ibcon#*mode == 0, iclass 34, count 0 2006.286.00:20:40.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.00:20:40.89#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.00:20:40.89#ibcon#*before write, iclass 34, count 0 2006.286.00:20:40.89#ibcon#enter sib2, iclass 34, count 0 2006.286.00:20:40.89#ibcon#flushed, iclass 34, count 0 2006.286.00:20:40.89#ibcon#about to write, iclass 34, count 0 2006.286.00:20:40.89#ibcon#wrote, iclass 34, count 0 2006.286.00:20:40.89#ibcon#about to read 3, iclass 34, count 0 2006.286.00:20:40.93#ibcon#read 3, iclass 34, count 0 2006.286.00:20:40.93#ibcon#about to read 4, iclass 34, count 0 2006.286.00:20:40.93#ibcon#read 4, iclass 34, count 0 2006.286.00:20:40.93#ibcon#about to read 5, iclass 34, count 0 2006.286.00:20:40.93#ibcon#read 5, iclass 34, count 0 2006.286.00:20:40.93#ibcon#about to read 6, iclass 34, count 0 2006.286.00:20:40.93#ibcon#read 6, iclass 34, count 0 2006.286.00:20:40.93#ibcon#end of sib2, iclass 34, count 0 2006.286.00:20:40.93#ibcon#*after write, iclass 34, count 0 2006.286.00:20:40.93#ibcon#*before return 0, iclass 34, count 0 2006.286.00:20:40.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:20:40.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:20:40.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.00:20:40.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.00:20:40.93$vck44/va=2,6 2006.286.00:20:40.93#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.00:20:40.93#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.00:20:40.93#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:40.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:20:40.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:20:40.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:20:40.99#ibcon#enter wrdev, iclass 36, count 2 2006.286.00:20:40.99#ibcon#first serial, iclass 36, count 2 2006.286.00:20:40.99#ibcon#enter sib2, iclass 36, count 2 2006.286.00:20:40.99#ibcon#flushed, iclass 36, count 2 2006.286.00:20:40.99#ibcon#about to write, iclass 36, count 2 2006.286.00:20:40.99#ibcon#wrote, iclass 36, count 2 2006.286.00:20:40.99#ibcon#about to read 3, iclass 36, count 2 2006.286.00:20:41.01#ibcon#read 3, iclass 36, count 2 2006.286.00:20:41.01#ibcon#about to read 4, iclass 36, count 2 2006.286.00:20:41.01#ibcon#read 4, iclass 36, count 2 2006.286.00:20:41.01#ibcon#about to read 5, iclass 36, count 2 2006.286.00:20:41.01#ibcon#read 5, iclass 36, count 2 2006.286.00:20:41.01#ibcon#about to read 6, iclass 36, count 2 2006.286.00:20:41.01#ibcon#read 6, iclass 36, count 2 2006.286.00:20:41.01#ibcon#end of sib2, iclass 36, count 2 2006.286.00:20:41.01#ibcon#*mode == 0, iclass 36, count 2 2006.286.00:20:41.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.00:20:41.01#ibcon#[25=AT02-06\r\n] 2006.286.00:20:41.01#ibcon#*before write, iclass 36, count 2 2006.286.00:20:41.01#ibcon#enter sib2, iclass 36, count 2 2006.286.00:20:41.01#ibcon#flushed, iclass 36, count 2 2006.286.00:20:41.01#ibcon#about to write, iclass 36, count 2 2006.286.00:20:41.01#ibcon#wrote, iclass 36, count 2 2006.286.00:20:41.01#ibcon#about to read 3, iclass 36, count 2 2006.286.00:20:41.04#ibcon#read 3, iclass 36, count 2 2006.286.00:20:41.04#ibcon#about to read 4, iclass 36, count 2 2006.286.00:20:41.04#ibcon#read 4, iclass 36, count 2 2006.286.00:20:41.04#ibcon#about to read 5, iclass 36, count 2 2006.286.00:20:41.04#ibcon#read 5, iclass 36, count 2 2006.286.00:20:41.04#ibcon#about to read 6, iclass 36, count 2 2006.286.00:20:41.04#ibcon#read 6, iclass 36, count 2 2006.286.00:20:41.04#ibcon#end of sib2, iclass 36, count 2 2006.286.00:20:41.04#ibcon#*after write, iclass 36, count 2 2006.286.00:20:41.04#ibcon#*before return 0, iclass 36, count 2 2006.286.00:20:41.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:20:41.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:20:41.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.00:20:41.04#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:41.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:20:41.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:20:41.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:20:41.16#ibcon#enter wrdev, iclass 36, count 0 2006.286.00:20:41.16#ibcon#first serial, iclass 36, count 0 2006.286.00:20:41.16#ibcon#enter sib2, iclass 36, count 0 2006.286.00:20:41.16#ibcon#flushed, iclass 36, count 0 2006.286.00:20:41.16#ibcon#about to write, iclass 36, count 0 2006.286.00:20:41.16#ibcon#wrote, iclass 36, count 0 2006.286.00:20:41.16#ibcon#about to read 3, iclass 36, count 0 2006.286.00:20:41.18#ibcon#read 3, iclass 36, count 0 2006.286.00:20:41.18#ibcon#about to read 4, iclass 36, count 0 2006.286.00:20:41.18#ibcon#read 4, iclass 36, count 0 2006.286.00:20:41.18#ibcon#about to read 5, iclass 36, count 0 2006.286.00:20:41.18#ibcon#read 5, iclass 36, count 0 2006.286.00:20:41.18#ibcon#about to read 6, iclass 36, count 0 2006.286.00:20:41.18#ibcon#read 6, iclass 36, count 0 2006.286.00:20:41.18#ibcon#end of sib2, iclass 36, count 0 2006.286.00:20:41.18#ibcon#*mode == 0, iclass 36, count 0 2006.286.00:20:41.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.00:20:41.18#ibcon#[25=USB\r\n] 2006.286.00:20:41.18#ibcon#*before write, iclass 36, count 0 2006.286.00:20:41.18#ibcon#enter sib2, iclass 36, count 0 2006.286.00:20:41.18#ibcon#flushed, iclass 36, count 0 2006.286.00:20:41.18#ibcon#about to write, iclass 36, count 0 2006.286.00:20:41.18#ibcon#wrote, iclass 36, count 0 2006.286.00:20:41.18#ibcon#about to read 3, iclass 36, count 0 2006.286.00:20:41.21#ibcon#read 3, iclass 36, count 0 2006.286.00:20:41.21#ibcon#about to read 4, iclass 36, count 0 2006.286.00:20:41.21#ibcon#read 4, iclass 36, count 0 2006.286.00:20:41.21#ibcon#about to read 5, iclass 36, count 0 2006.286.00:20:41.21#ibcon#read 5, iclass 36, count 0 2006.286.00:20:41.21#ibcon#about to read 6, iclass 36, count 0 2006.286.00:20:41.21#ibcon#read 6, iclass 36, count 0 2006.286.00:20:41.21#ibcon#end of sib2, iclass 36, count 0 2006.286.00:20:41.21#ibcon#*after write, iclass 36, count 0 2006.286.00:20:41.21#ibcon#*before return 0, iclass 36, count 0 2006.286.00:20:41.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:20:41.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:20:41.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.00:20:41.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.00:20:41.21$vck44/valo=3,564.99 2006.286.00:20:41.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.00:20:41.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.00:20:41.21#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:41.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:20:41.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:20:41.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:20:41.21#ibcon#enter wrdev, iclass 38, count 0 2006.286.00:20:41.21#ibcon#first serial, iclass 38, count 0 2006.286.00:20:41.21#ibcon#enter sib2, iclass 38, count 0 2006.286.00:20:41.21#ibcon#flushed, iclass 38, count 0 2006.286.00:20:41.21#ibcon#about to write, iclass 38, count 0 2006.286.00:20:41.21#ibcon#wrote, iclass 38, count 0 2006.286.00:20:41.21#ibcon#about to read 3, iclass 38, count 0 2006.286.00:20:41.23#ibcon#read 3, iclass 38, count 0 2006.286.00:20:41.23#ibcon#about to read 4, iclass 38, count 0 2006.286.00:20:41.23#ibcon#read 4, iclass 38, count 0 2006.286.00:20:41.23#ibcon#about to read 5, iclass 38, count 0 2006.286.00:20:41.23#ibcon#read 5, iclass 38, count 0 2006.286.00:20:41.23#ibcon#about to read 6, iclass 38, count 0 2006.286.00:20:41.23#ibcon#read 6, iclass 38, count 0 2006.286.00:20:41.23#ibcon#end of sib2, iclass 38, count 0 2006.286.00:20:41.23#ibcon#*mode == 0, iclass 38, count 0 2006.286.00:20:41.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.00:20:41.23#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.00:20:41.23#ibcon#*before write, iclass 38, count 0 2006.286.00:20:41.23#ibcon#enter sib2, iclass 38, count 0 2006.286.00:20:41.23#ibcon#flushed, iclass 38, count 0 2006.286.00:20:41.23#ibcon#about to write, iclass 38, count 0 2006.286.00:20:41.23#ibcon#wrote, iclass 38, count 0 2006.286.00:20:41.23#ibcon#about to read 3, iclass 38, count 0 2006.286.00:20:41.27#ibcon#read 3, iclass 38, count 0 2006.286.00:20:41.27#ibcon#about to read 4, iclass 38, count 0 2006.286.00:20:41.27#ibcon#read 4, iclass 38, count 0 2006.286.00:20:41.27#ibcon#about to read 5, iclass 38, count 0 2006.286.00:20:41.27#ibcon#read 5, iclass 38, count 0 2006.286.00:20:41.27#ibcon#about to read 6, iclass 38, count 0 2006.286.00:20:41.27#ibcon#read 6, iclass 38, count 0 2006.286.00:20:41.27#ibcon#end of sib2, iclass 38, count 0 2006.286.00:20:41.27#ibcon#*after write, iclass 38, count 0 2006.286.00:20:41.27#ibcon#*before return 0, iclass 38, count 0 2006.286.00:20:41.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:20:41.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:20:41.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.00:20:41.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.00:20:41.27$vck44/va=3,7 2006.286.00:20:41.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.00:20:41.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.00:20:41.27#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:41.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:20:41.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:20:41.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:20:41.33#ibcon#enter wrdev, iclass 40, count 2 2006.286.00:20:41.33#ibcon#first serial, iclass 40, count 2 2006.286.00:20:41.33#ibcon#enter sib2, iclass 40, count 2 2006.286.00:20:41.33#ibcon#flushed, iclass 40, count 2 2006.286.00:20:41.33#ibcon#about to write, iclass 40, count 2 2006.286.00:20:41.33#ibcon#wrote, iclass 40, count 2 2006.286.00:20:41.33#ibcon#about to read 3, iclass 40, count 2 2006.286.00:20:41.35#ibcon#read 3, iclass 40, count 2 2006.286.00:20:41.35#ibcon#about to read 4, iclass 40, count 2 2006.286.00:20:41.35#ibcon#read 4, iclass 40, count 2 2006.286.00:20:41.35#ibcon#about to read 5, iclass 40, count 2 2006.286.00:20:41.35#ibcon#read 5, iclass 40, count 2 2006.286.00:20:41.35#ibcon#about to read 6, iclass 40, count 2 2006.286.00:20:41.35#ibcon#read 6, iclass 40, count 2 2006.286.00:20:41.35#ibcon#end of sib2, iclass 40, count 2 2006.286.00:20:41.35#ibcon#*mode == 0, iclass 40, count 2 2006.286.00:20:41.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.00:20:41.35#ibcon#[25=AT03-07\r\n] 2006.286.00:20:41.35#ibcon#*before write, iclass 40, count 2 2006.286.00:20:41.35#ibcon#enter sib2, iclass 40, count 2 2006.286.00:20:41.35#ibcon#flushed, iclass 40, count 2 2006.286.00:20:41.35#ibcon#about to write, iclass 40, count 2 2006.286.00:20:41.35#ibcon#wrote, iclass 40, count 2 2006.286.00:20:41.35#ibcon#about to read 3, iclass 40, count 2 2006.286.00:20:41.38#ibcon#read 3, iclass 40, count 2 2006.286.00:20:41.38#ibcon#about to read 4, iclass 40, count 2 2006.286.00:20:41.38#ibcon#read 4, iclass 40, count 2 2006.286.00:20:41.38#ibcon#about to read 5, iclass 40, count 2 2006.286.00:20:41.38#ibcon#read 5, iclass 40, count 2 2006.286.00:20:41.38#ibcon#about to read 6, iclass 40, count 2 2006.286.00:20:41.38#ibcon#read 6, iclass 40, count 2 2006.286.00:20:41.38#ibcon#end of sib2, iclass 40, count 2 2006.286.00:20:41.38#ibcon#*after write, iclass 40, count 2 2006.286.00:20:41.38#ibcon#*before return 0, iclass 40, count 2 2006.286.00:20:41.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:20:41.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:20:41.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.00:20:41.38#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:41.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:20:41.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:20:41.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:20:41.50#ibcon#enter wrdev, iclass 40, count 0 2006.286.00:20:41.50#ibcon#first serial, iclass 40, count 0 2006.286.00:20:41.50#ibcon#enter sib2, iclass 40, count 0 2006.286.00:20:41.50#ibcon#flushed, iclass 40, count 0 2006.286.00:20:41.50#ibcon#about to write, iclass 40, count 0 2006.286.00:20:41.50#ibcon#wrote, iclass 40, count 0 2006.286.00:20:41.50#ibcon#about to read 3, iclass 40, count 0 2006.286.00:20:41.52#ibcon#read 3, iclass 40, count 0 2006.286.00:20:41.52#ibcon#about to read 4, iclass 40, count 0 2006.286.00:20:41.52#ibcon#read 4, iclass 40, count 0 2006.286.00:20:41.52#ibcon#about to read 5, iclass 40, count 0 2006.286.00:20:41.52#ibcon#read 5, iclass 40, count 0 2006.286.00:20:41.52#ibcon#about to read 6, iclass 40, count 0 2006.286.00:20:41.52#ibcon#read 6, iclass 40, count 0 2006.286.00:20:41.52#ibcon#end of sib2, iclass 40, count 0 2006.286.00:20:41.52#ibcon#*mode == 0, iclass 40, count 0 2006.286.00:20:41.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.00:20:41.52#ibcon#[25=USB\r\n] 2006.286.00:20:41.52#ibcon#*before write, iclass 40, count 0 2006.286.00:20:41.52#ibcon#enter sib2, iclass 40, count 0 2006.286.00:20:41.52#ibcon#flushed, iclass 40, count 0 2006.286.00:20:41.52#ibcon#about to write, iclass 40, count 0 2006.286.00:20:41.52#ibcon#wrote, iclass 40, count 0 2006.286.00:20:41.52#ibcon#about to read 3, iclass 40, count 0 2006.286.00:20:41.55#ibcon#read 3, iclass 40, count 0 2006.286.00:20:41.55#ibcon#about to read 4, iclass 40, count 0 2006.286.00:20:41.55#ibcon#read 4, iclass 40, count 0 2006.286.00:20:41.55#ibcon#about to read 5, iclass 40, count 0 2006.286.00:20:41.55#ibcon#read 5, iclass 40, count 0 2006.286.00:20:41.55#ibcon#about to read 6, iclass 40, count 0 2006.286.00:20:41.55#ibcon#read 6, iclass 40, count 0 2006.286.00:20:41.55#ibcon#end of sib2, iclass 40, count 0 2006.286.00:20:41.55#ibcon#*after write, iclass 40, count 0 2006.286.00:20:41.55#ibcon#*before return 0, iclass 40, count 0 2006.286.00:20:41.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:20:41.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:20:41.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.00:20:41.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.00:20:41.55$vck44/valo=4,624.99 2006.286.00:20:41.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.00:20:41.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.00:20:41.55#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:41.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:20:41.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:20:41.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:20:41.55#ibcon#enter wrdev, iclass 4, count 0 2006.286.00:20:41.55#ibcon#first serial, iclass 4, count 0 2006.286.00:20:41.55#ibcon#enter sib2, iclass 4, count 0 2006.286.00:20:41.55#ibcon#flushed, iclass 4, count 0 2006.286.00:20:41.55#ibcon#about to write, iclass 4, count 0 2006.286.00:20:41.55#ibcon#wrote, iclass 4, count 0 2006.286.00:20:41.55#ibcon#about to read 3, iclass 4, count 0 2006.286.00:20:41.57#ibcon#read 3, iclass 4, count 0 2006.286.00:20:41.57#ibcon#about to read 4, iclass 4, count 0 2006.286.00:20:41.57#ibcon#read 4, iclass 4, count 0 2006.286.00:20:41.57#ibcon#about to read 5, iclass 4, count 0 2006.286.00:20:41.57#ibcon#read 5, iclass 4, count 0 2006.286.00:20:41.57#ibcon#about to read 6, iclass 4, count 0 2006.286.00:20:41.57#ibcon#read 6, iclass 4, count 0 2006.286.00:20:41.57#ibcon#end of sib2, iclass 4, count 0 2006.286.00:20:41.57#ibcon#*mode == 0, iclass 4, count 0 2006.286.00:20:41.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.00:20:41.57#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.00:20:41.57#ibcon#*before write, iclass 4, count 0 2006.286.00:20:41.57#ibcon#enter sib2, iclass 4, count 0 2006.286.00:20:41.57#ibcon#flushed, iclass 4, count 0 2006.286.00:20:41.57#ibcon#about to write, iclass 4, count 0 2006.286.00:20:41.57#ibcon#wrote, iclass 4, count 0 2006.286.00:20:41.57#ibcon#about to read 3, iclass 4, count 0 2006.286.00:20:41.61#ibcon#read 3, iclass 4, count 0 2006.286.00:20:41.61#ibcon#about to read 4, iclass 4, count 0 2006.286.00:20:41.61#ibcon#read 4, iclass 4, count 0 2006.286.00:20:41.61#ibcon#about to read 5, iclass 4, count 0 2006.286.00:20:41.61#ibcon#read 5, iclass 4, count 0 2006.286.00:20:41.61#ibcon#about to read 6, iclass 4, count 0 2006.286.00:20:41.61#ibcon#read 6, iclass 4, count 0 2006.286.00:20:41.61#ibcon#end of sib2, iclass 4, count 0 2006.286.00:20:41.61#ibcon#*after write, iclass 4, count 0 2006.286.00:20:41.61#ibcon#*before return 0, iclass 4, count 0 2006.286.00:20:41.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:20:41.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:20:41.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.00:20:41.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.00:20:41.61$vck44/va=4,6 2006.286.00:20:41.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.00:20:41.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.00:20:41.61#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:41.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:20:41.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:20:41.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:20:41.67#ibcon#enter wrdev, iclass 6, count 2 2006.286.00:20:41.67#ibcon#first serial, iclass 6, count 2 2006.286.00:20:41.67#ibcon#enter sib2, iclass 6, count 2 2006.286.00:20:41.67#ibcon#flushed, iclass 6, count 2 2006.286.00:20:41.67#ibcon#about to write, iclass 6, count 2 2006.286.00:20:41.67#ibcon#wrote, iclass 6, count 2 2006.286.00:20:41.67#ibcon#about to read 3, iclass 6, count 2 2006.286.00:20:41.69#ibcon#read 3, iclass 6, count 2 2006.286.00:20:41.69#ibcon#about to read 4, iclass 6, count 2 2006.286.00:20:41.69#ibcon#read 4, iclass 6, count 2 2006.286.00:20:41.69#ibcon#about to read 5, iclass 6, count 2 2006.286.00:20:41.69#ibcon#read 5, iclass 6, count 2 2006.286.00:20:41.69#ibcon#about to read 6, iclass 6, count 2 2006.286.00:20:41.69#ibcon#read 6, iclass 6, count 2 2006.286.00:20:41.69#ibcon#end of sib2, iclass 6, count 2 2006.286.00:20:41.69#ibcon#*mode == 0, iclass 6, count 2 2006.286.00:20:41.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.00:20:41.69#ibcon#[25=AT04-06\r\n] 2006.286.00:20:41.69#ibcon#*before write, iclass 6, count 2 2006.286.00:20:41.69#ibcon#enter sib2, iclass 6, count 2 2006.286.00:20:41.69#ibcon#flushed, iclass 6, count 2 2006.286.00:20:41.69#ibcon#about to write, iclass 6, count 2 2006.286.00:20:41.69#ibcon#wrote, iclass 6, count 2 2006.286.00:20:41.69#ibcon#about to read 3, iclass 6, count 2 2006.286.00:20:41.72#ibcon#read 3, iclass 6, count 2 2006.286.00:20:41.72#ibcon#about to read 4, iclass 6, count 2 2006.286.00:20:41.72#ibcon#read 4, iclass 6, count 2 2006.286.00:20:41.72#ibcon#about to read 5, iclass 6, count 2 2006.286.00:20:41.72#ibcon#read 5, iclass 6, count 2 2006.286.00:20:41.72#ibcon#about to read 6, iclass 6, count 2 2006.286.00:20:41.72#ibcon#read 6, iclass 6, count 2 2006.286.00:20:41.72#ibcon#end of sib2, iclass 6, count 2 2006.286.00:20:41.72#ibcon#*after write, iclass 6, count 2 2006.286.00:20:41.72#ibcon#*before return 0, iclass 6, count 2 2006.286.00:20:41.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:20:41.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:20:41.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.00:20:41.72#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:41.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:20:41.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:20:41.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:20:41.84#ibcon#enter wrdev, iclass 6, count 0 2006.286.00:20:41.84#ibcon#first serial, iclass 6, count 0 2006.286.00:20:41.84#ibcon#enter sib2, iclass 6, count 0 2006.286.00:20:41.84#ibcon#flushed, iclass 6, count 0 2006.286.00:20:41.84#ibcon#about to write, iclass 6, count 0 2006.286.00:20:41.84#ibcon#wrote, iclass 6, count 0 2006.286.00:20:41.84#ibcon#about to read 3, iclass 6, count 0 2006.286.00:20:41.86#ibcon#read 3, iclass 6, count 0 2006.286.00:20:41.86#ibcon#about to read 4, iclass 6, count 0 2006.286.00:20:41.86#ibcon#read 4, iclass 6, count 0 2006.286.00:20:41.86#ibcon#about to read 5, iclass 6, count 0 2006.286.00:20:41.86#ibcon#read 5, iclass 6, count 0 2006.286.00:20:41.86#ibcon#about to read 6, iclass 6, count 0 2006.286.00:20:41.86#ibcon#read 6, iclass 6, count 0 2006.286.00:20:41.86#ibcon#end of sib2, iclass 6, count 0 2006.286.00:20:41.86#ibcon#*mode == 0, iclass 6, count 0 2006.286.00:20:41.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.00:20:41.86#ibcon#[25=USB\r\n] 2006.286.00:20:41.86#ibcon#*before write, iclass 6, count 0 2006.286.00:20:41.86#ibcon#enter sib2, iclass 6, count 0 2006.286.00:20:41.86#ibcon#flushed, iclass 6, count 0 2006.286.00:20:41.86#ibcon#about to write, iclass 6, count 0 2006.286.00:20:41.86#ibcon#wrote, iclass 6, count 0 2006.286.00:20:41.86#ibcon#about to read 3, iclass 6, count 0 2006.286.00:20:41.89#ibcon#read 3, iclass 6, count 0 2006.286.00:20:41.89#ibcon#about to read 4, iclass 6, count 0 2006.286.00:20:41.89#ibcon#read 4, iclass 6, count 0 2006.286.00:20:41.89#ibcon#about to read 5, iclass 6, count 0 2006.286.00:20:41.89#ibcon#read 5, iclass 6, count 0 2006.286.00:20:41.89#ibcon#about to read 6, iclass 6, count 0 2006.286.00:20:41.89#ibcon#read 6, iclass 6, count 0 2006.286.00:20:41.89#ibcon#end of sib2, iclass 6, count 0 2006.286.00:20:41.89#ibcon#*after write, iclass 6, count 0 2006.286.00:20:41.89#ibcon#*before return 0, iclass 6, count 0 2006.286.00:20:41.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:20:41.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:20:41.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.00:20:41.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.00:20:41.89$vck44/valo=5,734.99 2006.286.00:20:41.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.00:20:41.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.00:20:41.89#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:41.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:20:41.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:20:41.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:20:41.89#ibcon#enter wrdev, iclass 10, count 0 2006.286.00:20:41.89#ibcon#first serial, iclass 10, count 0 2006.286.00:20:41.89#ibcon#enter sib2, iclass 10, count 0 2006.286.00:20:41.89#ibcon#flushed, iclass 10, count 0 2006.286.00:20:41.89#ibcon#about to write, iclass 10, count 0 2006.286.00:20:41.89#ibcon#wrote, iclass 10, count 0 2006.286.00:20:41.89#ibcon#about to read 3, iclass 10, count 0 2006.286.00:20:41.91#ibcon#read 3, iclass 10, count 0 2006.286.00:20:41.91#ibcon#about to read 4, iclass 10, count 0 2006.286.00:20:41.91#ibcon#read 4, iclass 10, count 0 2006.286.00:20:41.91#ibcon#about to read 5, iclass 10, count 0 2006.286.00:20:41.91#ibcon#read 5, iclass 10, count 0 2006.286.00:20:41.91#ibcon#about to read 6, iclass 10, count 0 2006.286.00:20:41.91#ibcon#read 6, iclass 10, count 0 2006.286.00:20:41.91#ibcon#end of sib2, iclass 10, count 0 2006.286.00:20:41.91#ibcon#*mode == 0, iclass 10, count 0 2006.286.00:20:41.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.00:20:41.91#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.00:20:41.91#ibcon#*before write, iclass 10, count 0 2006.286.00:20:41.91#ibcon#enter sib2, iclass 10, count 0 2006.286.00:20:41.91#ibcon#flushed, iclass 10, count 0 2006.286.00:20:41.91#ibcon#about to write, iclass 10, count 0 2006.286.00:20:41.91#ibcon#wrote, iclass 10, count 0 2006.286.00:20:41.91#ibcon#about to read 3, iclass 10, count 0 2006.286.00:20:41.95#ibcon#read 3, iclass 10, count 0 2006.286.00:20:41.95#ibcon#about to read 4, iclass 10, count 0 2006.286.00:20:41.95#ibcon#read 4, iclass 10, count 0 2006.286.00:20:41.95#ibcon#about to read 5, iclass 10, count 0 2006.286.00:20:41.95#ibcon#read 5, iclass 10, count 0 2006.286.00:20:41.95#ibcon#about to read 6, iclass 10, count 0 2006.286.00:20:41.95#ibcon#read 6, iclass 10, count 0 2006.286.00:20:41.95#ibcon#end of sib2, iclass 10, count 0 2006.286.00:20:41.95#ibcon#*after write, iclass 10, count 0 2006.286.00:20:41.95#ibcon#*before return 0, iclass 10, count 0 2006.286.00:20:41.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:20:41.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:20:41.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.00:20:41.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.00:20:41.95$vck44/va=5,3 2006.286.00:20:41.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.00:20:41.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.00:20:41.95#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:41.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:20:42.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:20:42.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:20:42.01#ibcon#enter wrdev, iclass 12, count 2 2006.286.00:20:42.01#ibcon#first serial, iclass 12, count 2 2006.286.00:20:42.01#ibcon#enter sib2, iclass 12, count 2 2006.286.00:20:42.01#ibcon#flushed, iclass 12, count 2 2006.286.00:20:42.01#ibcon#about to write, iclass 12, count 2 2006.286.00:20:42.01#ibcon#wrote, iclass 12, count 2 2006.286.00:20:42.01#ibcon#about to read 3, iclass 12, count 2 2006.286.00:20:42.03#ibcon#read 3, iclass 12, count 2 2006.286.00:20:42.03#ibcon#about to read 4, iclass 12, count 2 2006.286.00:20:42.03#ibcon#read 4, iclass 12, count 2 2006.286.00:20:42.03#ibcon#about to read 5, iclass 12, count 2 2006.286.00:20:42.03#ibcon#read 5, iclass 12, count 2 2006.286.00:20:42.03#ibcon#about to read 6, iclass 12, count 2 2006.286.00:20:42.03#ibcon#read 6, iclass 12, count 2 2006.286.00:20:42.03#ibcon#end of sib2, iclass 12, count 2 2006.286.00:20:42.03#ibcon#*mode == 0, iclass 12, count 2 2006.286.00:20:42.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.00:20:42.03#ibcon#[25=AT05-03\r\n] 2006.286.00:20:42.03#ibcon#*before write, iclass 12, count 2 2006.286.00:20:42.03#ibcon#enter sib2, iclass 12, count 2 2006.286.00:20:42.03#ibcon#flushed, iclass 12, count 2 2006.286.00:20:42.03#ibcon#about to write, iclass 12, count 2 2006.286.00:20:42.03#ibcon#wrote, iclass 12, count 2 2006.286.00:20:42.03#ibcon#about to read 3, iclass 12, count 2 2006.286.00:20:42.06#ibcon#read 3, iclass 12, count 2 2006.286.00:20:42.06#ibcon#about to read 4, iclass 12, count 2 2006.286.00:20:42.06#ibcon#read 4, iclass 12, count 2 2006.286.00:20:42.06#ibcon#about to read 5, iclass 12, count 2 2006.286.00:20:42.06#ibcon#read 5, iclass 12, count 2 2006.286.00:20:42.06#ibcon#about to read 6, iclass 12, count 2 2006.286.00:20:42.06#ibcon#read 6, iclass 12, count 2 2006.286.00:20:42.06#ibcon#end of sib2, iclass 12, count 2 2006.286.00:20:42.06#ibcon#*after write, iclass 12, count 2 2006.286.00:20:42.06#ibcon#*before return 0, iclass 12, count 2 2006.286.00:20:42.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:20:42.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:20:42.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.00:20:42.06#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:42.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:20:42.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:20:42.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:20:42.18#ibcon#enter wrdev, iclass 12, count 0 2006.286.00:20:42.18#ibcon#first serial, iclass 12, count 0 2006.286.00:20:42.18#ibcon#enter sib2, iclass 12, count 0 2006.286.00:20:42.18#ibcon#flushed, iclass 12, count 0 2006.286.00:20:42.18#ibcon#about to write, iclass 12, count 0 2006.286.00:20:42.18#ibcon#wrote, iclass 12, count 0 2006.286.00:20:42.18#ibcon#about to read 3, iclass 12, count 0 2006.286.00:20:42.20#ibcon#read 3, iclass 12, count 0 2006.286.00:20:42.20#ibcon#about to read 4, iclass 12, count 0 2006.286.00:20:42.20#ibcon#read 4, iclass 12, count 0 2006.286.00:20:42.20#ibcon#about to read 5, iclass 12, count 0 2006.286.00:20:42.20#ibcon#read 5, iclass 12, count 0 2006.286.00:20:42.20#ibcon#about to read 6, iclass 12, count 0 2006.286.00:20:42.20#ibcon#read 6, iclass 12, count 0 2006.286.00:20:42.20#ibcon#end of sib2, iclass 12, count 0 2006.286.00:20:42.20#ibcon#*mode == 0, iclass 12, count 0 2006.286.00:20:42.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.00:20:42.20#ibcon#[25=USB\r\n] 2006.286.00:20:42.20#ibcon#*before write, iclass 12, count 0 2006.286.00:20:42.20#ibcon#enter sib2, iclass 12, count 0 2006.286.00:20:42.20#ibcon#flushed, iclass 12, count 0 2006.286.00:20:42.20#ibcon#about to write, iclass 12, count 0 2006.286.00:20:42.20#ibcon#wrote, iclass 12, count 0 2006.286.00:20:42.20#ibcon#about to read 3, iclass 12, count 0 2006.286.00:20:42.23#ibcon#read 3, iclass 12, count 0 2006.286.00:20:42.23#ibcon#about to read 4, iclass 12, count 0 2006.286.00:20:42.23#ibcon#read 4, iclass 12, count 0 2006.286.00:20:42.23#ibcon#about to read 5, iclass 12, count 0 2006.286.00:20:42.23#ibcon#read 5, iclass 12, count 0 2006.286.00:20:42.23#ibcon#about to read 6, iclass 12, count 0 2006.286.00:20:42.23#ibcon#read 6, iclass 12, count 0 2006.286.00:20:42.23#ibcon#end of sib2, iclass 12, count 0 2006.286.00:20:42.23#ibcon#*after write, iclass 12, count 0 2006.286.00:20:42.23#ibcon#*before return 0, iclass 12, count 0 2006.286.00:20:42.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:20:42.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:20:42.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.00:20:42.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.00:20:42.23$vck44/valo=6,814.99 2006.286.00:20:42.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.00:20:42.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.00:20:42.23#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:42.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:20:42.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:20:42.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:20:42.23#ibcon#enter wrdev, iclass 14, count 0 2006.286.00:20:42.23#ibcon#first serial, iclass 14, count 0 2006.286.00:20:42.23#ibcon#enter sib2, iclass 14, count 0 2006.286.00:20:42.23#ibcon#flushed, iclass 14, count 0 2006.286.00:20:42.23#ibcon#about to write, iclass 14, count 0 2006.286.00:20:42.23#ibcon#wrote, iclass 14, count 0 2006.286.00:20:42.23#ibcon#about to read 3, iclass 14, count 0 2006.286.00:20:42.25#ibcon#read 3, iclass 14, count 0 2006.286.00:20:42.25#ibcon#about to read 4, iclass 14, count 0 2006.286.00:20:42.25#ibcon#read 4, iclass 14, count 0 2006.286.00:20:42.25#ibcon#about to read 5, iclass 14, count 0 2006.286.00:20:42.25#ibcon#read 5, iclass 14, count 0 2006.286.00:20:42.25#ibcon#about to read 6, iclass 14, count 0 2006.286.00:20:42.25#ibcon#read 6, iclass 14, count 0 2006.286.00:20:42.25#ibcon#end of sib2, iclass 14, count 0 2006.286.00:20:42.25#ibcon#*mode == 0, iclass 14, count 0 2006.286.00:20:42.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.00:20:42.25#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.00:20:42.25#ibcon#*before write, iclass 14, count 0 2006.286.00:20:42.25#ibcon#enter sib2, iclass 14, count 0 2006.286.00:20:42.25#ibcon#flushed, iclass 14, count 0 2006.286.00:20:42.25#ibcon#about to write, iclass 14, count 0 2006.286.00:20:42.25#ibcon#wrote, iclass 14, count 0 2006.286.00:20:42.25#ibcon#about to read 3, iclass 14, count 0 2006.286.00:20:42.29#ibcon#read 3, iclass 14, count 0 2006.286.00:20:42.29#ibcon#about to read 4, iclass 14, count 0 2006.286.00:20:42.29#ibcon#read 4, iclass 14, count 0 2006.286.00:20:42.29#ibcon#about to read 5, iclass 14, count 0 2006.286.00:20:42.29#ibcon#read 5, iclass 14, count 0 2006.286.00:20:42.29#ibcon#about to read 6, iclass 14, count 0 2006.286.00:20:42.29#ibcon#read 6, iclass 14, count 0 2006.286.00:20:42.29#ibcon#end of sib2, iclass 14, count 0 2006.286.00:20:42.29#ibcon#*after write, iclass 14, count 0 2006.286.00:20:42.29#ibcon#*before return 0, iclass 14, count 0 2006.286.00:20:42.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:20:42.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:20:42.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.00:20:42.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.00:20:42.29$vck44/va=6,4 2006.286.00:20:42.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.00:20:42.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.00:20:42.29#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:42.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:20:42.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:20:42.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:20:42.35#ibcon#enter wrdev, iclass 16, count 2 2006.286.00:20:42.35#ibcon#first serial, iclass 16, count 2 2006.286.00:20:42.35#ibcon#enter sib2, iclass 16, count 2 2006.286.00:20:42.35#ibcon#flushed, iclass 16, count 2 2006.286.00:20:42.35#ibcon#about to write, iclass 16, count 2 2006.286.00:20:42.35#ibcon#wrote, iclass 16, count 2 2006.286.00:20:42.35#ibcon#about to read 3, iclass 16, count 2 2006.286.00:20:42.37#ibcon#read 3, iclass 16, count 2 2006.286.00:20:42.37#ibcon#about to read 4, iclass 16, count 2 2006.286.00:20:42.37#ibcon#read 4, iclass 16, count 2 2006.286.00:20:42.37#ibcon#about to read 5, iclass 16, count 2 2006.286.00:20:42.37#ibcon#read 5, iclass 16, count 2 2006.286.00:20:42.37#ibcon#about to read 6, iclass 16, count 2 2006.286.00:20:42.37#ibcon#read 6, iclass 16, count 2 2006.286.00:20:42.37#ibcon#end of sib2, iclass 16, count 2 2006.286.00:20:42.37#ibcon#*mode == 0, iclass 16, count 2 2006.286.00:20:42.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.00:20:42.37#ibcon#[25=AT06-04\r\n] 2006.286.00:20:42.37#ibcon#*before write, iclass 16, count 2 2006.286.00:20:42.37#ibcon#enter sib2, iclass 16, count 2 2006.286.00:20:42.37#ibcon#flushed, iclass 16, count 2 2006.286.00:20:42.37#ibcon#about to write, iclass 16, count 2 2006.286.00:20:42.37#ibcon#wrote, iclass 16, count 2 2006.286.00:20:42.37#ibcon#about to read 3, iclass 16, count 2 2006.286.00:20:42.40#ibcon#read 3, iclass 16, count 2 2006.286.00:20:42.40#ibcon#about to read 4, iclass 16, count 2 2006.286.00:20:42.40#ibcon#read 4, iclass 16, count 2 2006.286.00:20:42.40#ibcon#about to read 5, iclass 16, count 2 2006.286.00:20:42.40#ibcon#read 5, iclass 16, count 2 2006.286.00:20:42.40#ibcon#about to read 6, iclass 16, count 2 2006.286.00:20:42.40#ibcon#read 6, iclass 16, count 2 2006.286.00:20:42.40#ibcon#end of sib2, iclass 16, count 2 2006.286.00:20:42.40#ibcon#*after write, iclass 16, count 2 2006.286.00:20:42.40#ibcon#*before return 0, iclass 16, count 2 2006.286.00:20:42.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:20:42.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:20:42.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.00:20:42.40#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:42.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:20:42.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:20:42.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:20:42.52#ibcon#enter wrdev, iclass 16, count 0 2006.286.00:20:42.52#ibcon#first serial, iclass 16, count 0 2006.286.00:20:42.52#ibcon#enter sib2, iclass 16, count 0 2006.286.00:20:42.52#ibcon#flushed, iclass 16, count 0 2006.286.00:20:42.52#ibcon#about to write, iclass 16, count 0 2006.286.00:20:42.52#ibcon#wrote, iclass 16, count 0 2006.286.00:20:42.52#ibcon#about to read 3, iclass 16, count 0 2006.286.00:20:42.54#ibcon#read 3, iclass 16, count 0 2006.286.00:20:42.54#ibcon#about to read 4, iclass 16, count 0 2006.286.00:20:42.54#ibcon#read 4, iclass 16, count 0 2006.286.00:20:42.54#ibcon#about to read 5, iclass 16, count 0 2006.286.00:20:42.54#ibcon#read 5, iclass 16, count 0 2006.286.00:20:42.54#ibcon#about to read 6, iclass 16, count 0 2006.286.00:20:42.54#ibcon#read 6, iclass 16, count 0 2006.286.00:20:42.54#ibcon#end of sib2, iclass 16, count 0 2006.286.00:20:42.54#ibcon#*mode == 0, iclass 16, count 0 2006.286.00:20:42.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.00:20:42.54#ibcon#[25=USB\r\n] 2006.286.00:20:42.54#ibcon#*before write, iclass 16, count 0 2006.286.00:20:42.54#ibcon#enter sib2, iclass 16, count 0 2006.286.00:20:42.54#ibcon#flushed, iclass 16, count 0 2006.286.00:20:42.54#ibcon#about to write, iclass 16, count 0 2006.286.00:20:42.54#ibcon#wrote, iclass 16, count 0 2006.286.00:20:42.54#ibcon#about to read 3, iclass 16, count 0 2006.286.00:20:42.57#ibcon#read 3, iclass 16, count 0 2006.286.00:20:42.57#ibcon#about to read 4, iclass 16, count 0 2006.286.00:20:42.57#ibcon#read 4, iclass 16, count 0 2006.286.00:20:42.57#ibcon#about to read 5, iclass 16, count 0 2006.286.00:20:42.57#ibcon#read 5, iclass 16, count 0 2006.286.00:20:42.57#ibcon#about to read 6, iclass 16, count 0 2006.286.00:20:42.57#ibcon#read 6, iclass 16, count 0 2006.286.00:20:42.57#ibcon#end of sib2, iclass 16, count 0 2006.286.00:20:42.57#ibcon#*after write, iclass 16, count 0 2006.286.00:20:42.57#ibcon#*before return 0, iclass 16, count 0 2006.286.00:20:42.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:20:42.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:20:42.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.00:20:42.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.00:20:42.57$vck44/valo=7,864.99 2006.286.00:20:42.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.00:20:42.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.00:20:42.57#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:42.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:20:42.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:20:42.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:20:42.57#ibcon#enter wrdev, iclass 18, count 0 2006.286.00:20:42.57#ibcon#first serial, iclass 18, count 0 2006.286.00:20:42.57#ibcon#enter sib2, iclass 18, count 0 2006.286.00:20:42.57#ibcon#flushed, iclass 18, count 0 2006.286.00:20:42.57#ibcon#about to write, iclass 18, count 0 2006.286.00:20:42.57#ibcon#wrote, iclass 18, count 0 2006.286.00:20:42.57#ibcon#about to read 3, iclass 18, count 0 2006.286.00:20:42.59#ibcon#read 3, iclass 18, count 0 2006.286.00:20:42.59#ibcon#about to read 4, iclass 18, count 0 2006.286.00:20:42.59#ibcon#read 4, iclass 18, count 0 2006.286.00:20:42.59#ibcon#about to read 5, iclass 18, count 0 2006.286.00:20:42.59#ibcon#read 5, iclass 18, count 0 2006.286.00:20:42.59#ibcon#about to read 6, iclass 18, count 0 2006.286.00:20:42.59#ibcon#read 6, iclass 18, count 0 2006.286.00:20:42.59#ibcon#end of sib2, iclass 18, count 0 2006.286.00:20:42.59#ibcon#*mode == 0, iclass 18, count 0 2006.286.00:20:42.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.00:20:42.59#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.00:20:42.59#ibcon#*before write, iclass 18, count 0 2006.286.00:20:42.59#ibcon#enter sib2, iclass 18, count 0 2006.286.00:20:42.59#ibcon#flushed, iclass 18, count 0 2006.286.00:20:42.59#ibcon#about to write, iclass 18, count 0 2006.286.00:20:42.59#ibcon#wrote, iclass 18, count 0 2006.286.00:20:42.59#ibcon#about to read 3, iclass 18, count 0 2006.286.00:20:42.63#ibcon#read 3, iclass 18, count 0 2006.286.00:20:42.63#ibcon#about to read 4, iclass 18, count 0 2006.286.00:20:42.63#ibcon#read 4, iclass 18, count 0 2006.286.00:20:42.63#ibcon#about to read 5, iclass 18, count 0 2006.286.00:20:42.63#ibcon#read 5, iclass 18, count 0 2006.286.00:20:42.63#ibcon#about to read 6, iclass 18, count 0 2006.286.00:20:42.63#ibcon#read 6, iclass 18, count 0 2006.286.00:20:42.63#ibcon#end of sib2, iclass 18, count 0 2006.286.00:20:42.63#ibcon#*after write, iclass 18, count 0 2006.286.00:20:42.63#ibcon#*before return 0, iclass 18, count 0 2006.286.00:20:42.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:20:42.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:20:42.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.00:20:42.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.00:20:42.63$vck44/va=7,4 2006.286.00:20:42.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.00:20:42.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.00:20:42.63#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:42.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:20:42.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:20:42.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:20:42.69#ibcon#enter wrdev, iclass 20, count 2 2006.286.00:20:42.69#ibcon#first serial, iclass 20, count 2 2006.286.00:20:42.69#ibcon#enter sib2, iclass 20, count 2 2006.286.00:20:42.69#ibcon#flushed, iclass 20, count 2 2006.286.00:20:42.69#ibcon#about to write, iclass 20, count 2 2006.286.00:20:42.69#ibcon#wrote, iclass 20, count 2 2006.286.00:20:42.69#ibcon#about to read 3, iclass 20, count 2 2006.286.00:20:42.71#ibcon#read 3, iclass 20, count 2 2006.286.00:20:42.71#ibcon#about to read 4, iclass 20, count 2 2006.286.00:20:42.71#ibcon#read 4, iclass 20, count 2 2006.286.00:20:42.71#ibcon#about to read 5, iclass 20, count 2 2006.286.00:20:42.71#ibcon#read 5, iclass 20, count 2 2006.286.00:20:42.71#ibcon#about to read 6, iclass 20, count 2 2006.286.00:20:42.71#ibcon#read 6, iclass 20, count 2 2006.286.00:20:42.71#ibcon#end of sib2, iclass 20, count 2 2006.286.00:20:42.71#ibcon#*mode == 0, iclass 20, count 2 2006.286.00:20:42.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.00:20:42.71#ibcon#[25=AT07-04\r\n] 2006.286.00:20:42.71#ibcon#*before write, iclass 20, count 2 2006.286.00:20:42.71#ibcon#enter sib2, iclass 20, count 2 2006.286.00:20:42.71#ibcon#flushed, iclass 20, count 2 2006.286.00:20:42.71#ibcon#about to write, iclass 20, count 2 2006.286.00:20:42.71#ibcon#wrote, iclass 20, count 2 2006.286.00:20:42.71#ibcon#about to read 3, iclass 20, count 2 2006.286.00:20:42.74#ibcon#read 3, iclass 20, count 2 2006.286.00:20:42.74#ibcon#about to read 4, iclass 20, count 2 2006.286.00:20:42.74#ibcon#read 4, iclass 20, count 2 2006.286.00:20:42.74#ibcon#about to read 5, iclass 20, count 2 2006.286.00:20:42.74#ibcon#read 5, iclass 20, count 2 2006.286.00:20:42.74#ibcon#about to read 6, iclass 20, count 2 2006.286.00:20:42.74#ibcon#read 6, iclass 20, count 2 2006.286.00:20:42.74#ibcon#end of sib2, iclass 20, count 2 2006.286.00:20:42.74#ibcon#*after write, iclass 20, count 2 2006.286.00:20:42.74#ibcon#*before return 0, iclass 20, count 2 2006.286.00:20:42.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:20:42.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:20:42.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.00:20:42.74#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:42.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:20:42.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:20:42.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:20:42.86#ibcon#enter wrdev, iclass 20, count 0 2006.286.00:20:42.86#ibcon#first serial, iclass 20, count 0 2006.286.00:20:42.86#ibcon#enter sib2, iclass 20, count 0 2006.286.00:20:42.86#ibcon#flushed, iclass 20, count 0 2006.286.00:20:42.86#ibcon#about to write, iclass 20, count 0 2006.286.00:20:42.86#ibcon#wrote, iclass 20, count 0 2006.286.00:20:42.86#ibcon#about to read 3, iclass 20, count 0 2006.286.00:20:42.88#ibcon#read 3, iclass 20, count 0 2006.286.00:20:42.88#ibcon#about to read 4, iclass 20, count 0 2006.286.00:20:42.88#ibcon#read 4, iclass 20, count 0 2006.286.00:20:42.88#ibcon#about to read 5, iclass 20, count 0 2006.286.00:20:42.88#ibcon#read 5, iclass 20, count 0 2006.286.00:20:42.88#ibcon#about to read 6, iclass 20, count 0 2006.286.00:20:42.88#ibcon#read 6, iclass 20, count 0 2006.286.00:20:42.88#ibcon#end of sib2, iclass 20, count 0 2006.286.00:20:42.88#ibcon#*mode == 0, iclass 20, count 0 2006.286.00:20:42.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.00:20:42.88#ibcon#[25=USB\r\n] 2006.286.00:20:42.88#ibcon#*before write, iclass 20, count 0 2006.286.00:20:42.88#ibcon#enter sib2, iclass 20, count 0 2006.286.00:20:42.88#ibcon#flushed, iclass 20, count 0 2006.286.00:20:42.88#ibcon#about to write, iclass 20, count 0 2006.286.00:20:42.88#ibcon#wrote, iclass 20, count 0 2006.286.00:20:42.88#ibcon#about to read 3, iclass 20, count 0 2006.286.00:20:42.91#ibcon#read 3, iclass 20, count 0 2006.286.00:20:42.91#ibcon#about to read 4, iclass 20, count 0 2006.286.00:20:42.91#ibcon#read 4, iclass 20, count 0 2006.286.00:20:42.91#ibcon#about to read 5, iclass 20, count 0 2006.286.00:20:42.91#ibcon#read 5, iclass 20, count 0 2006.286.00:20:42.91#ibcon#about to read 6, iclass 20, count 0 2006.286.00:20:42.91#ibcon#read 6, iclass 20, count 0 2006.286.00:20:42.91#ibcon#end of sib2, iclass 20, count 0 2006.286.00:20:42.91#ibcon#*after write, iclass 20, count 0 2006.286.00:20:42.91#ibcon#*before return 0, iclass 20, count 0 2006.286.00:20:42.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:20:42.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:20:42.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.00:20:42.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.00:20:42.91$vck44/valo=8,884.99 2006.286.00:20:42.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.00:20:42.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.00:20:42.91#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:42.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:20:42.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:20:42.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:20:42.91#ibcon#enter wrdev, iclass 22, count 0 2006.286.00:20:42.91#ibcon#first serial, iclass 22, count 0 2006.286.00:20:42.91#ibcon#enter sib2, iclass 22, count 0 2006.286.00:20:42.91#ibcon#flushed, iclass 22, count 0 2006.286.00:20:42.91#ibcon#about to write, iclass 22, count 0 2006.286.00:20:42.91#ibcon#wrote, iclass 22, count 0 2006.286.00:20:42.91#ibcon#about to read 3, iclass 22, count 0 2006.286.00:20:42.93#ibcon#read 3, iclass 22, count 0 2006.286.00:20:42.93#ibcon#about to read 4, iclass 22, count 0 2006.286.00:20:42.93#ibcon#read 4, iclass 22, count 0 2006.286.00:20:42.93#ibcon#about to read 5, iclass 22, count 0 2006.286.00:20:42.93#ibcon#read 5, iclass 22, count 0 2006.286.00:20:42.93#ibcon#about to read 6, iclass 22, count 0 2006.286.00:20:42.93#ibcon#read 6, iclass 22, count 0 2006.286.00:20:42.93#ibcon#end of sib2, iclass 22, count 0 2006.286.00:20:42.93#ibcon#*mode == 0, iclass 22, count 0 2006.286.00:20:42.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.00:20:42.93#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.00:20:42.93#ibcon#*before write, iclass 22, count 0 2006.286.00:20:42.93#ibcon#enter sib2, iclass 22, count 0 2006.286.00:20:42.93#ibcon#flushed, iclass 22, count 0 2006.286.00:20:42.93#ibcon#about to write, iclass 22, count 0 2006.286.00:20:42.93#ibcon#wrote, iclass 22, count 0 2006.286.00:20:42.93#ibcon#about to read 3, iclass 22, count 0 2006.286.00:20:42.97#ibcon#read 3, iclass 22, count 0 2006.286.00:20:42.97#ibcon#about to read 4, iclass 22, count 0 2006.286.00:20:42.97#ibcon#read 4, iclass 22, count 0 2006.286.00:20:42.97#ibcon#about to read 5, iclass 22, count 0 2006.286.00:20:42.97#ibcon#read 5, iclass 22, count 0 2006.286.00:20:42.97#ibcon#about to read 6, iclass 22, count 0 2006.286.00:20:42.97#ibcon#read 6, iclass 22, count 0 2006.286.00:20:42.97#ibcon#end of sib2, iclass 22, count 0 2006.286.00:20:42.97#ibcon#*after write, iclass 22, count 0 2006.286.00:20:42.97#ibcon#*before return 0, iclass 22, count 0 2006.286.00:20:42.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:20:42.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:20:42.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.00:20:42.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.00:20:42.97$vck44/va=8,3 2006.286.00:20:42.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.00:20:42.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.00:20:42.97#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:42.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:20:43.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:20:43.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:20:43.03#ibcon#enter wrdev, iclass 24, count 2 2006.286.00:20:43.03#ibcon#first serial, iclass 24, count 2 2006.286.00:20:43.03#ibcon#enter sib2, iclass 24, count 2 2006.286.00:20:43.03#ibcon#flushed, iclass 24, count 2 2006.286.00:20:43.03#ibcon#about to write, iclass 24, count 2 2006.286.00:20:43.03#ibcon#wrote, iclass 24, count 2 2006.286.00:20:43.03#ibcon#about to read 3, iclass 24, count 2 2006.286.00:20:43.05#ibcon#read 3, iclass 24, count 2 2006.286.00:20:43.05#ibcon#about to read 4, iclass 24, count 2 2006.286.00:20:43.05#ibcon#read 4, iclass 24, count 2 2006.286.00:20:43.05#ibcon#about to read 5, iclass 24, count 2 2006.286.00:20:43.05#ibcon#read 5, iclass 24, count 2 2006.286.00:20:43.05#ibcon#about to read 6, iclass 24, count 2 2006.286.00:20:43.05#ibcon#read 6, iclass 24, count 2 2006.286.00:20:43.05#ibcon#end of sib2, iclass 24, count 2 2006.286.00:20:43.05#ibcon#*mode == 0, iclass 24, count 2 2006.286.00:20:43.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.00:20:43.05#ibcon#[25=AT08-03\r\n] 2006.286.00:20:43.05#ibcon#*before write, iclass 24, count 2 2006.286.00:20:43.05#ibcon#enter sib2, iclass 24, count 2 2006.286.00:20:43.05#ibcon#flushed, iclass 24, count 2 2006.286.00:20:43.05#ibcon#about to write, iclass 24, count 2 2006.286.00:20:43.05#ibcon#wrote, iclass 24, count 2 2006.286.00:20:43.05#ibcon#about to read 3, iclass 24, count 2 2006.286.00:20:43.08#ibcon#read 3, iclass 24, count 2 2006.286.00:20:43.08#ibcon#about to read 4, iclass 24, count 2 2006.286.00:20:43.08#ibcon#read 4, iclass 24, count 2 2006.286.00:20:43.08#ibcon#about to read 5, iclass 24, count 2 2006.286.00:20:43.08#ibcon#read 5, iclass 24, count 2 2006.286.00:20:43.08#ibcon#about to read 6, iclass 24, count 2 2006.286.00:20:43.08#ibcon#read 6, iclass 24, count 2 2006.286.00:20:43.08#ibcon#end of sib2, iclass 24, count 2 2006.286.00:20:43.08#ibcon#*after write, iclass 24, count 2 2006.286.00:20:43.08#ibcon#*before return 0, iclass 24, count 2 2006.286.00:20:43.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:20:43.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:20:43.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.00:20:43.08#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:43.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:20:43.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:20:43.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:20:43.20#ibcon#enter wrdev, iclass 24, count 0 2006.286.00:20:43.20#ibcon#first serial, iclass 24, count 0 2006.286.00:20:43.20#ibcon#enter sib2, iclass 24, count 0 2006.286.00:20:43.20#ibcon#flushed, iclass 24, count 0 2006.286.00:20:43.20#ibcon#about to write, iclass 24, count 0 2006.286.00:20:43.20#ibcon#wrote, iclass 24, count 0 2006.286.00:20:43.20#ibcon#about to read 3, iclass 24, count 0 2006.286.00:20:43.22#ibcon#read 3, iclass 24, count 0 2006.286.00:20:43.22#ibcon#about to read 4, iclass 24, count 0 2006.286.00:20:43.22#ibcon#read 4, iclass 24, count 0 2006.286.00:20:43.22#ibcon#about to read 5, iclass 24, count 0 2006.286.00:20:43.22#ibcon#read 5, iclass 24, count 0 2006.286.00:20:43.22#ibcon#about to read 6, iclass 24, count 0 2006.286.00:20:43.22#ibcon#read 6, iclass 24, count 0 2006.286.00:20:43.22#ibcon#end of sib2, iclass 24, count 0 2006.286.00:20:43.22#ibcon#*mode == 0, iclass 24, count 0 2006.286.00:20:43.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.00:20:43.22#ibcon#[25=USB\r\n] 2006.286.00:20:43.22#ibcon#*before write, iclass 24, count 0 2006.286.00:20:43.22#ibcon#enter sib2, iclass 24, count 0 2006.286.00:20:43.22#ibcon#flushed, iclass 24, count 0 2006.286.00:20:43.22#ibcon#about to write, iclass 24, count 0 2006.286.00:20:43.22#ibcon#wrote, iclass 24, count 0 2006.286.00:20:43.22#ibcon#about to read 3, iclass 24, count 0 2006.286.00:20:43.25#ibcon#read 3, iclass 24, count 0 2006.286.00:20:43.25#ibcon#about to read 4, iclass 24, count 0 2006.286.00:20:43.25#ibcon#read 4, iclass 24, count 0 2006.286.00:20:43.25#ibcon#about to read 5, iclass 24, count 0 2006.286.00:20:43.25#ibcon#read 5, iclass 24, count 0 2006.286.00:20:43.25#ibcon#about to read 6, iclass 24, count 0 2006.286.00:20:43.25#ibcon#read 6, iclass 24, count 0 2006.286.00:20:43.25#ibcon#end of sib2, iclass 24, count 0 2006.286.00:20:43.25#ibcon#*after write, iclass 24, count 0 2006.286.00:20:43.25#ibcon#*before return 0, iclass 24, count 0 2006.286.00:20:43.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:20:43.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:20:43.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.00:20:43.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.00:20:43.25$vck44/vblo=1,629.99 2006.286.00:20:43.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.00:20:43.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.00:20:43.25#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:43.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:20:43.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:20:43.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:20:43.25#ibcon#enter wrdev, iclass 26, count 0 2006.286.00:20:43.25#ibcon#first serial, iclass 26, count 0 2006.286.00:20:43.25#ibcon#enter sib2, iclass 26, count 0 2006.286.00:20:43.25#ibcon#flushed, iclass 26, count 0 2006.286.00:20:43.25#ibcon#about to write, iclass 26, count 0 2006.286.00:20:43.25#ibcon#wrote, iclass 26, count 0 2006.286.00:20:43.25#ibcon#about to read 3, iclass 26, count 0 2006.286.00:20:43.27#ibcon#read 3, iclass 26, count 0 2006.286.00:20:43.27#ibcon#about to read 4, iclass 26, count 0 2006.286.00:20:43.27#ibcon#read 4, iclass 26, count 0 2006.286.00:20:43.27#ibcon#about to read 5, iclass 26, count 0 2006.286.00:20:43.27#ibcon#read 5, iclass 26, count 0 2006.286.00:20:43.27#ibcon#about to read 6, iclass 26, count 0 2006.286.00:20:43.27#ibcon#read 6, iclass 26, count 0 2006.286.00:20:43.27#ibcon#end of sib2, iclass 26, count 0 2006.286.00:20:43.27#ibcon#*mode == 0, iclass 26, count 0 2006.286.00:20:43.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.00:20:43.27#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.00:20:43.27#ibcon#*before write, iclass 26, count 0 2006.286.00:20:43.27#ibcon#enter sib2, iclass 26, count 0 2006.286.00:20:43.27#ibcon#flushed, iclass 26, count 0 2006.286.00:20:43.27#ibcon#about to write, iclass 26, count 0 2006.286.00:20:43.27#ibcon#wrote, iclass 26, count 0 2006.286.00:20:43.27#ibcon#about to read 3, iclass 26, count 0 2006.286.00:20:43.31#ibcon#read 3, iclass 26, count 0 2006.286.00:20:43.31#ibcon#about to read 4, iclass 26, count 0 2006.286.00:20:43.31#ibcon#read 4, iclass 26, count 0 2006.286.00:20:43.31#ibcon#about to read 5, iclass 26, count 0 2006.286.00:20:43.31#ibcon#read 5, iclass 26, count 0 2006.286.00:20:43.31#ibcon#about to read 6, iclass 26, count 0 2006.286.00:20:43.31#ibcon#read 6, iclass 26, count 0 2006.286.00:20:43.31#ibcon#end of sib2, iclass 26, count 0 2006.286.00:20:43.31#ibcon#*after write, iclass 26, count 0 2006.286.00:20:43.31#ibcon#*before return 0, iclass 26, count 0 2006.286.00:20:43.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:20:43.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:20:43.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.00:20:43.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.00:20:43.31$vck44/vb=1,4 2006.286.00:20:43.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.00:20:43.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.00:20:43.31#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:43.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:20:43.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:20:43.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:20:43.31#ibcon#enter wrdev, iclass 29, count 2 2006.286.00:20:43.31#ibcon#first serial, iclass 29, count 2 2006.286.00:20:43.31#ibcon#enter sib2, iclass 29, count 2 2006.286.00:20:43.31#ibcon#flushed, iclass 29, count 2 2006.286.00:20:43.31#ibcon#about to write, iclass 29, count 2 2006.286.00:20:43.31#ibcon#wrote, iclass 29, count 2 2006.286.00:20:43.31#ibcon#about to read 3, iclass 29, count 2 2006.286.00:20:43.33#ibcon#read 3, iclass 29, count 2 2006.286.00:20:43.33#ibcon#about to read 4, iclass 29, count 2 2006.286.00:20:43.33#ibcon#read 4, iclass 29, count 2 2006.286.00:20:43.33#ibcon#about to read 5, iclass 29, count 2 2006.286.00:20:43.33#ibcon#read 5, iclass 29, count 2 2006.286.00:20:43.33#ibcon#about to read 6, iclass 29, count 2 2006.286.00:20:43.33#ibcon#read 6, iclass 29, count 2 2006.286.00:20:43.33#ibcon#end of sib2, iclass 29, count 2 2006.286.00:20:43.33#ibcon#*mode == 0, iclass 29, count 2 2006.286.00:20:43.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.00:20:43.33#ibcon#[27=AT01-04\r\n] 2006.286.00:20:43.33#ibcon#*before write, iclass 29, count 2 2006.286.00:20:43.33#ibcon#enter sib2, iclass 29, count 2 2006.286.00:20:43.33#ibcon#flushed, iclass 29, count 2 2006.286.00:20:43.33#ibcon#about to write, iclass 29, count 2 2006.286.00:20:43.33#ibcon#wrote, iclass 29, count 2 2006.286.00:20:43.33#ibcon#about to read 3, iclass 29, count 2 2006.286.00:20:43.34#abcon#<5=/03 3.1 6.5 19.85 851016.4\r\n> 2006.286.00:20:43.36#abcon#{5=INTERFACE CLEAR} 2006.286.00:20:43.36#ibcon#read 3, iclass 29, count 2 2006.286.00:20:43.36#ibcon#about to read 4, iclass 29, count 2 2006.286.00:20:43.36#ibcon#read 4, iclass 29, count 2 2006.286.00:20:43.36#ibcon#about to read 5, iclass 29, count 2 2006.286.00:20:43.36#ibcon#read 5, iclass 29, count 2 2006.286.00:20:43.36#ibcon#about to read 6, iclass 29, count 2 2006.286.00:20:43.36#ibcon#read 6, iclass 29, count 2 2006.286.00:20:43.36#ibcon#end of sib2, iclass 29, count 2 2006.286.00:20:43.36#ibcon#*after write, iclass 29, count 2 2006.286.00:20:43.36#ibcon#*before return 0, iclass 29, count 2 2006.286.00:20:43.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:20:43.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:20:43.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.00:20:43.36#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:43.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:20:43.42#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:20:43.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:20:43.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:20:43.48#ibcon#enter wrdev, iclass 29, count 0 2006.286.00:20:43.48#ibcon#first serial, iclass 29, count 0 2006.286.00:20:43.48#ibcon#enter sib2, iclass 29, count 0 2006.286.00:20:43.48#ibcon#flushed, iclass 29, count 0 2006.286.00:20:43.48#ibcon#about to write, iclass 29, count 0 2006.286.00:20:43.48#ibcon#wrote, iclass 29, count 0 2006.286.00:20:43.48#ibcon#about to read 3, iclass 29, count 0 2006.286.00:20:43.50#ibcon#read 3, iclass 29, count 0 2006.286.00:20:43.50#ibcon#about to read 4, iclass 29, count 0 2006.286.00:20:43.50#ibcon#read 4, iclass 29, count 0 2006.286.00:20:43.50#ibcon#about to read 5, iclass 29, count 0 2006.286.00:20:43.50#ibcon#read 5, iclass 29, count 0 2006.286.00:20:43.50#ibcon#about to read 6, iclass 29, count 0 2006.286.00:20:43.50#ibcon#read 6, iclass 29, count 0 2006.286.00:20:43.50#ibcon#end of sib2, iclass 29, count 0 2006.286.00:20:43.50#ibcon#*mode == 0, iclass 29, count 0 2006.286.00:20:43.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.00:20:43.50#ibcon#[27=USB\r\n] 2006.286.00:20:43.50#ibcon#*before write, iclass 29, count 0 2006.286.00:20:43.50#ibcon#enter sib2, iclass 29, count 0 2006.286.00:20:43.50#ibcon#flushed, iclass 29, count 0 2006.286.00:20:43.50#ibcon#about to write, iclass 29, count 0 2006.286.00:20:43.50#ibcon#wrote, iclass 29, count 0 2006.286.00:20:43.50#ibcon#about to read 3, iclass 29, count 0 2006.286.00:20:43.53#ibcon#read 3, iclass 29, count 0 2006.286.00:20:43.53#ibcon#about to read 4, iclass 29, count 0 2006.286.00:20:43.53#ibcon#read 4, iclass 29, count 0 2006.286.00:20:43.53#ibcon#about to read 5, iclass 29, count 0 2006.286.00:20:43.53#ibcon#read 5, iclass 29, count 0 2006.286.00:20:43.53#ibcon#about to read 6, iclass 29, count 0 2006.286.00:20:43.53#ibcon#read 6, iclass 29, count 0 2006.286.00:20:43.53#ibcon#end of sib2, iclass 29, count 0 2006.286.00:20:43.53#ibcon#*after write, iclass 29, count 0 2006.286.00:20:43.53#ibcon#*before return 0, iclass 29, count 0 2006.286.00:20:43.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:20:43.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:20:43.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.00:20:43.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.00:20:43.53$vck44/vblo=2,634.99 2006.286.00:20:43.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.00:20:43.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.00:20:43.53#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:43.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:20:43.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:20:43.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:20:43.53#ibcon#enter wrdev, iclass 34, count 0 2006.286.00:20:43.53#ibcon#first serial, iclass 34, count 0 2006.286.00:20:43.53#ibcon#enter sib2, iclass 34, count 0 2006.286.00:20:43.53#ibcon#flushed, iclass 34, count 0 2006.286.00:20:43.53#ibcon#about to write, iclass 34, count 0 2006.286.00:20:43.53#ibcon#wrote, iclass 34, count 0 2006.286.00:20:43.53#ibcon#about to read 3, iclass 34, count 0 2006.286.00:20:43.55#ibcon#read 3, iclass 34, count 0 2006.286.00:20:43.55#ibcon#about to read 4, iclass 34, count 0 2006.286.00:20:43.55#ibcon#read 4, iclass 34, count 0 2006.286.00:20:43.55#ibcon#about to read 5, iclass 34, count 0 2006.286.00:20:43.55#ibcon#read 5, iclass 34, count 0 2006.286.00:20:43.55#ibcon#about to read 6, iclass 34, count 0 2006.286.00:20:43.55#ibcon#read 6, iclass 34, count 0 2006.286.00:20:43.55#ibcon#end of sib2, iclass 34, count 0 2006.286.00:20:43.55#ibcon#*mode == 0, iclass 34, count 0 2006.286.00:20:43.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.00:20:43.55#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.00:20:43.55#ibcon#*before write, iclass 34, count 0 2006.286.00:20:43.55#ibcon#enter sib2, iclass 34, count 0 2006.286.00:20:43.55#ibcon#flushed, iclass 34, count 0 2006.286.00:20:43.55#ibcon#about to write, iclass 34, count 0 2006.286.00:20:43.55#ibcon#wrote, iclass 34, count 0 2006.286.00:20:43.55#ibcon#about to read 3, iclass 34, count 0 2006.286.00:20:43.59#ibcon#read 3, iclass 34, count 0 2006.286.00:20:43.59#ibcon#about to read 4, iclass 34, count 0 2006.286.00:20:43.59#ibcon#read 4, iclass 34, count 0 2006.286.00:20:43.59#ibcon#about to read 5, iclass 34, count 0 2006.286.00:20:43.59#ibcon#read 5, iclass 34, count 0 2006.286.00:20:43.59#ibcon#about to read 6, iclass 34, count 0 2006.286.00:20:43.59#ibcon#read 6, iclass 34, count 0 2006.286.00:20:43.59#ibcon#end of sib2, iclass 34, count 0 2006.286.00:20:43.59#ibcon#*after write, iclass 34, count 0 2006.286.00:20:43.59#ibcon#*before return 0, iclass 34, count 0 2006.286.00:20:43.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:20:43.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:20:43.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.00:20:43.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.00:20:43.59$vck44/vb=2,5 2006.286.00:20:43.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.00:20:43.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.00:20:43.59#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:43.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:20:43.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:20:43.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:20:43.65#ibcon#enter wrdev, iclass 36, count 2 2006.286.00:20:43.65#ibcon#first serial, iclass 36, count 2 2006.286.00:20:43.65#ibcon#enter sib2, iclass 36, count 2 2006.286.00:20:43.65#ibcon#flushed, iclass 36, count 2 2006.286.00:20:43.65#ibcon#about to write, iclass 36, count 2 2006.286.00:20:43.65#ibcon#wrote, iclass 36, count 2 2006.286.00:20:43.65#ibcon#about to read 3, iclass 36, count 2 2006.286.00:20:43.67#ibcon#read 3, iclass 36, count 2 2006.286.00:20:43.67#ibcon#about to read 4, iclass 36, count 2 2006.286.00:20:43.67#ibcon#read 4, iclass 36, count 2 2006.286.00:20:43.67#ibcon#about to read 5, iclass 36, count 2 2006.286.00:20:43.67#ibcon#read 5, iclass 36, count 2 2006.286.00:20:43.67#ibcon#about to read 6, iclass 36, count 2 2006.286.00:20:43.67#ibcon#read 6, iclass 36, count 2 2006.286.00:20:43.67#ibcon#end of sib2, iclass 36, count 2 2006.286.00:20:43.67#ibcon#*mode == 0, iclass 36, count 2 2006.286.00:20:43.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.00:20:43.67#ibcon#[27=AT02-05\r\n] 2006.286.00:20:43.67#ibcon#*before write, iclass 36, count 2 2006.286.00:20:43.67#ibcon#enter sib2, iclass 36, count 2 2006.286.00:20:43.67#ibcon#flushed, iclass 36, count 2 2006.286.00:20:43.67#ibcon#about to write, iclass 36, count 2 2006.286.00:20:43.67#ibcon#wrote, iclass 36, count 2 2006.286.00:20:43.67#ibcon#about to read 3, iclass 36, count 2 2006.286.00:20:43.70#ibcon#read 3, iclass 36, count 2 2006.286.00:20:43.70#ibcon#about to read 4, iclass 36, count 2 2006.286.00:20:43.70#ibcon#read 4, iclass 36, count 2 2006.286.00:20:43.70#ibcon#about to read 5, iclass 36, count 2 2006.286.00:20:43.70#ibcon#read 5, iclass 36, count 2 2006.286.00:20:43.70#ibcon#about to read 6, iclass 36, count 2 2006.286.00:20:43.70#ibcon#read 6, iclass 36, count 2 2006.286.00:20:43.70#ibcon#end of sib2, iclass 36, count 2 2006.286.00:20:43.70#ibcon#*after write, iclass 36, count 2 2006.286.00:20:43.70#ibcon#*before return 0, iclass 36, count 2 2006.286.00:20:43.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:20:43.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:20:43.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.00:20:43.70#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:43.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:20:43.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:20:43.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:20:43.82#ibcon#enter wrdev, iclass 36, count 0 2006.286.00:20:43.82#ibcon#first serial, iclass 36, count 0 2006.286.00:20:43.82#ibcon#enter sib2, iclass 36, count 0 2006.286.00:20:43.82#ibcon#flushed, iclass 36, count 0 2006.286.00:20:43.82#ibcon#about to write, iclass 36, count 0 2006.286.00:20:43.82#ibcon#wrote, iclass 36, count 0 2006.286.00:20:43.82#ibcon#about to read 3, iclass 36, count 0 2006.286.00:20:43.84#ibcon#read 3, iclass 36, count 0 2006.286.00:20:43.84#ibcon#about to read 4, iclass 36, count 0 2006.286.00:20:43.84#ibcon#read 4, iclass 36, count 0 2006.286.00:20:43.84#ibcon#about to read 5, iclass 36, count 0 2006.286.00:20:43.84#ibcon#read 5, iclass 36, count 0 2006.286.00:20:43.84#ibcon#about to read 6, iclass 36, count 0 2006.286.00:20:43.84#ibcon#read 6, iclass 36, count 0 2006.286.00:20:43.84#ibcon#end of sib2, iclass 36, count 0 2006.286.00:20:43.84#ibcon#*mode == 0, iclass 36, count 0 2006.286.00:20:43.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.00:20:43.84#ibcon#[27=USB\r\n] 2006.286.00:20:43.84#ibcon#*before write, iclass 36, count 0 2006.286.00:20:43.84#ibcon#enter sib2, iclass 36, count 0 2006.286.00:20:43.84#ibcon#flushed, iclass 36, count 0 2006.286.00:20:43.84#ibcon#about to write, iclass 36, count 0 2006.286.00:20:43.84#ibcon#wrote, iclass 36, count 0 2006.286.00:20:43.84#ibcon#about to read 3, iclass 36, count 0 2006.286.00:20:43.87#ibcon#read 3, iclass 36, count 0 2006.286.00:20:43.87#ibcon#about to read 4, iclass 36, count 0 2006.286.00:20:43.87#ibcon#read 4, iclass 36, count 0 2006.286.00:20:43.87#ibcon#about to read 5, iclass 36, count 0 2006.286.00:20:43.87#ibcon#read 5, iclass 36, count 0 2006.286.00:20:43.87#ibcon#about to read 6, iclass 36, count 0 2006.286.00:20:43.87#ibcon#read 6, iclass 36, count 0 2006.286.00:20:43.87#ibcon#end of sib2, iclass 36, count 0 2006.286.00:20:43.87#ibcon#*after write, iclass 36, count 0 2006.286.00:20:43.87#ibcon#*before return 0, iclass 36, count 0 2006.286.00:20:43.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:20:43.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:20:43.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.00:20:43.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.00:20:43.87$vck44/vblo=3,649.99 2006.286.00:20:43.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.00:20:43.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.00:20:43.87#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:43.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:20:43.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:20:43.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:20:43.87#ibcon#enter wrdev, iclass 38, count 0 2006.286.00:20:43.87#ibcon#first serial, iclass 38, count 0 2006.286.00:20:43.87#ibcon#enter sib2, iclass 38, count 0 2006.286.00:20:43.87#ibcon#flushed, iclass 38, count 0 2006.286.00:20:43.87#ibcon#about to write, iclass 38, count 0 2006.286.00:20:43.87#ibcon#wrote, iclass 38, count 0 2006.286.00:20:43.87#ibcon#about to read 3, iclass 38, count 0 2006.286.00:20:43.89#ibcon#read 3, iclass 38, count 0 2006.286.00:20:43.89#ibcon#about to read 4, iclass 38, count 0 2006.286.00:20:43.89#ibcon#read 4, iclass 38, count 0 2006.286.00:20:43.89#ibcon#about to read 5, iclass 38, count 0 2006.286.00:20:43.89#ibcon#read 5, iclass 38, count 0 2006.286.00:20:43.89#ibcon#about to read 6, iclass 38, count 0 2006.286.00:20:43.89#ibcon#read 6, iclass 38, count 0 2006.286.00:20:43.89#ibcon#end of sib2, iclass 38, count 0 2006.286.00:20:43.89#ibcon#*mode == 0, iclass 38, count 0 2006.286.00:20:43.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.00:20:43.89#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.00:20:43.89#ibcon#*before write, iclass 38, count 0 2006.286.00:20:43.89#ibcon#enter sib2, iclass 38, count 0 2006.286.00:20:43.89#ibcon#flushed, iclass 38, count 0 2006.286.00:20:43.89#ibcon#about to write, iclass 38, count 0 2006.286.00:20:43.89#ibcon#wrote, iclass 38, count 0 2006.286.00:20:43.89#ibcon#about to read 3, iclass 38, count 0 2006.286.00:20:43.93#ibcon#read 3, iclass 38, count 0 2006.286.00:20:43.93#ibcon#about to read 4, iclass 38, count 0 2006.286.00:20:43.93#ibcon#read 4, iclass 38, count 0 2006.286.00:20:43.93#ibcon#about to read 5, iclass 38, count 0 2006.286.00:20:43.93#ibcon#read 5, iclass 38, count 0 2006.286.00:20:43.93#ibcon#about to read 6, iclass 38, count 0 2006.286.00:20:43.93#ibcon#read 6, iclass 38, count 0 2006.286.00:20:43.93#ibcon#end of sib2, iclass 38, count 0 2006.286.00:20:43.93#ibcon#*after write, iclass 38, count 0 2006.286.00:20:43.93#ibcon#*before return 0, iclass 38, count 0 2006.286.00:20:43.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:20:43.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:20:43.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.00:20:43.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.00:20:43.93$vck44/vb=3,4 2006.286.00:20:43.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.00:20:43.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.00:20:43.93#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:43.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:20:43.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:20:43.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:20:43.99#ibcon#enter wrdev, iclass 40, count 2 2006.286.00:20:43.99#ibcon#first serial, iclass 40, count 2 2006.286.00:20:43.99#ibcon#enter sib2, iclass 40, count 2 2006.286.00:20:43.99#ibcon#flushed, iclass 40, count 2 2006.286.00:20:43.99#ibcon#about to write, iclass 40, count 2 2006.286.00:20:43.99#ibcon#wrote, iclass 40, count 2 2006.286.00:20:43.99#ibcon#about to read 3, iclass 40, count 2 2006.286.00:20:44.01#ibcon#read 3, iclass 40, count 2 2006.286.00:20:44.01#ibcon#about to read 4, iclass 40, count 2 2006.286.00:20:44.01#ibcon#read 4, iclass 40, count 2 2006.286.00:20:44.01#ibcon#about to read 5, iclass 40, count 2 2006.286.00:20:44.01#ibcon#read 5, iclass 40, count 2 2006.286.00:20:44.01#ibcon#about to read 6, iclass 40, count 2 2006.286.00:20:44.01#ibcon#read 6, iclass 40, count 2 2006.286.00:20:44.01#ibcon#end of sib2, iclass 40, count 2 2006.286.00:20:44.01#ibcon#*mode == 0, iclass 40, count 2 2006.286.00:20:44.01#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.00:20:44.01#ibcon#[27=AT03-04\r\n] 2006.286.00:20:44.01#ibcon#*before write, iclass 40, count 2 2006.286.00:20:44.01#ibcon#enter sib2, iclass 40, count 2 2006.286.00:20:44.01#ibcon#flushed, iclass 40, count 2 2006.286.00:20:44.01#ibcon#about to write, iclass 40, count 2 2006.286.00:20:44.01#ibcon#wrote, iclass 40, count 2 2006.286.00:20:44.01#ibcon#about to read 3, iclass 40, count 2 2006.286.00:20:44.04#ibcon#read 3, iclass 40, count 2 2006.286.00:20:44.04#ibcon#about to read 4, iclass 40, count 2 2006.286.00:20:44.04#ibcon#read 4, iclass 40, count 2 2006.286.00:20:44.04#ibcon#about to read 5, iclass 40, count 2 2006.286.00:20:44.04#ibcon#read 5, iclass 40, count 2 2006.286.00:20:44.04#ibcon#about to read 6, iclass 40, count 2 2006.286.00:20:44.04#ibcon#read 6, iclass 40, count 2 2006.286.00:20:44.04#ibcon#end of sib2, iclass 40, count 2 2006.286.00:20:44.04#ibcon#*after write, iclass 40, count 2 2006.286.00:20:44.04#ibcon#*before return 0, iclass 40, count 2 2006.286.00:20:44.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:20:44.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:20:44.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.00:20:44.04#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:44.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:20:44.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:20:44.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:20:44.16#ibcon#enter wrdev, iclass 40, count 0 2006.286.00:20:44.16#ibcon#first serial, iclass 40, count 0 2006.286.00:20:44.16#ibcon#enter sib2, iclass 40, count 0 2006.286.00:20:44.16#ibcon#flushed, iclass 40, count 0 2006.286.00:20:44.16#ibcon#about to write, iclass 40, count 0 2006.286.00:20:44.16#ibcon#wrote, iclass 40, count 0 2006.286.00:20:44.16#ibcon#about to read 3, iclass 40, count 0 2006.286.00:20:44.18#ibcon#read 3, iclass 40, count 0 2006.286.00:20:44.18#ibcon#about to read 4, iclass 40, count 0 2006.286.00:20:44.18#ibcon#read 4, iclass 40, count 0 2006.286.00:20:44.18#ibcon#about to read 5, iclass 40, count 0 2006.286.00:20:44.18#ibcon#read 5, iclass 40, count 0 2006.286.00:20:44.18#ibcon#about to read 6, iclass 40, count 0 2006.286.00:20:44.18#ibcon#read 6, iclass 40, count 0 2006.286.00:20:44.18#ibcon#end of sib2, iclass 40, count 0 2006.286.00:20:44.18#ibcon#*mode == 0, iclass 40, count 0 2006.286.00:20:44.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.00:20:44.18#ibcon#[27=USB\r\n] 2006.286.00:20:44.18#ibcon#*before write, iclass 40, count 0 2006.286.00:20:44.18#ibcon#enter sib2, iclass 40, count 0 2006.286.00:20:44.18#ibcon#flushed, iclass 40, count 0 2006.286.00:20:44.18#ibcon#about to write, iclass 40, count 0 2006.286.00:20:44.18#ibcon#wrote, iclass 40, count 0 2006.286.00:20:44.18#ibcon#about to read 3, iclass 40, count 0 2006.286.00:20:44.21#ibcon#read 3, iclass 40, count 0 2006.286.00:20:44.21#ibcon#about to read 4, iclass 40, count 0 2006.286.00:20:44.21#ibcon#read 4, iclass 40, count 0 2006.286.00:20:44.21#ibcon#about to read 5, iclass 40, count 0 2006.286.00:20:44.21#ibcon#read 5, iclass 40, count 0 2006.286.00:20:44.21#ibcon#about to read 6, iclass 40, count 0 2006.286.00:20:44.21#ibcon#read 6, iclass 40, count 0 2006.286.00:20:44.21#ibcon#end of sib2, iclass 40, count 0 2006.286.00:20:44.21#ibcon#*after write, iclass 40, count 0 2006.286.00:20:44.21#ibcon#*before return 0, iclass 40, count 0 2006.286.00:20:44.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:20:44.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:20:44.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.00:20:44.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.00:20:44.21$vck44/vblo=4,679.99 2006.286.00:20:44.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.00:20:44.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.00:20:44.21#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:44.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:20:44.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:20:44.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:20:44.21#ibcon#enter wrdev, iclass 4, count 0 2006.286.00:20:44.21#ibcon#first serial, iclass 4, count 0 2006.286.00:20:44.21#ibcon#enter sib2, iclass 4, count 0 2006.286.00:20:44.21#ibcon#flushed, iclass 4, count 0 2006.286.00:20:44.21#ibcon#about to write, iclass 4, count 0 2006.286.00:20:44.21#ibcon#wrote, iclass 4, count 0 2006.286.00:20:44.21#ibcon#about to read 3, iclass 4, count 0 2006.286.00:20:44.23#ibcon#read 3, iclass 4, count 0 2006.286.00:20:44.23#ibcon#about to read 4, iclass 4, count 0 2006.286.00:20:44.23#ibcon#read 4, iclass 4, count 0 2006.286.00:20:44.23#ibcon#about to read 5, iclass 4, count 0 2006.286.00:20:44.23#ibcon#read 5, iclass 4, count 0 2006.286.00:20:44.23#ibcon#about to read 6, iclass 4, count 0 2006.286.00:20:44.23#ibcon#read 6, iclass 4, count 0 2006.286.00:20:44.23#ibcon#end of sib2, iclass 4, count 0 2006.286.00:20:44.23#ibcon#*mode == 0, iclass 4, count 0 2006.286.00:20:44.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.00:20:44.23#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.00:20:44.23#ibcon#*before write, iclass 4, count 0 2006.286.00:20:44.23#ibcon#enter sib2, iclass 4, count 0 2006.286.00:20:44.23#ibcon#flushed, iclass 4, count 0 2006.286.00:20:44.23#ibcon#about to write, iclass 4, count 0 2006.286.00:20:44.23#ibcon#wrote, iclass 4, count 0 2006.286.00:20:44.23#ibcon#about to read 3, iclass 4, count 0 2006.286.00:20:44.27#ibcon#read 3, iclass 4, count 0 2006.286.00:20:44.27#ibcon#about to read 4, iclass 4, count 0 2006.286.00:20:44.27#ibcon#read 4, iclass 4, count 0 2006.286.00:20:44.27#ibcon#about to read 5, iclass 4, count 0 2006.286.00:20:44.27#ibcon#read 5, iclass 4, count 0 2006.286.00:20:44.27#ibcon#about to read 6, iclass 4, count 0 2006.286.00:20:44.27#ibcon#read 6, iclass 4, count 0 2006.286.00:20:44.27#ibcon#end of sib2, iclass 4, count 0 2006.286.00:20:44.27#ibcon#*after write, iclass 4, count 0 2006.286.00:20:44.27#ibcon#*before return 0, iclass 4, count 0 2006.286.00:20:44.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:20:44.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:20:44.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.00:20:44.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.00:20:44.27$vck44/vb=4,5 2006.286.00:20:44.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.00:20:44.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.00:20:44.27#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:44.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:20:44.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:20:44.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:20:44.33#ibcon#enter wrdev, iclass 6, count 2 2006.286.00:20:44.33#ibcon#first serial, iclass 6, count 2 2006.286.00:20:44.33#ibcon#enter sib2, iclass 6, count 2 2006.286.00:20:44.33#ibcon#flushed, iclass 6, count 2 2006.286.00:20:44.33#ibcon#about to write, iclass 6, count 2 2006.286.00:20:44.33#ibcon#wrote, iclass 6, count 2 2006.286.00:20:44.33#ibcon#about to read 3, iclass 6, count 2 2006.286.00:20:44.35#ibcon#read 3, iclass 6, count 2 2006.286.00:20:44.35#ibcon#about to read 4, iclass 6, count 2 2006.286.00:20:44.35#ibcon#read 4, iclass 6, count 2 2006.286.00:20:44.35#ibcon#about to read 5, iclass 6, count 2 2006.286.00:20:44.35#ibcon#read 5, iclass 6, count 2 2006.286.00:20:44.35#ibcon#about to read 6, iclass 6, count 2 2006.286.00:20:44.35#ibcon#read 6, iclass 6, count 2 2006.286.00:20:44.35#ibcon#end of sib2, iclass 6, count 2 2006.286.00:20:44.35#ibcon#*mode == 0, iclass 6, count 2 2006.286.00:20:44.35#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.00:20:44.35#ibcon#[27=AT04-05\r\n] 2006.286.00:20:44.35#ibcon#*before write, iclass 6, count 2 2006.286.00:20:44.35#ibcon#enter sib2, iclass 6, count 2 2006.286.00:20:44.35#ibcon#flushed, iclass 6, count 2 2006.286.00:20:44.35#ibcon#about to write, iclass 6, count 2 2006.286.00:20:44.35#ibcon#wrote, iclass 6, count 2 2006.286.00:20:44.35#ibcon#about to read 3, iclass 6, count 2 2006.286.00:20:44.38#ibcon#read 3, iclass 6, count 2 2006.286.00:20:44.38#ibcon#about to read 4, iclass 6, count 2 2006.286.00:20:44.38#ibcon#read 4, iclass 6, count 2 2006.286.00:20:44.38#ibcon#about to read 5, iclass 6, count 2 2006.286.00:20:44.38#ibcon#read 5, iclass 6, count 2 2006.286.00:20:44.38#ibcon#about to read 6, iclass 6, count 2 2006.286.00:20:44.38#ibcon#read 6, iclass 6, count 2 2006.286.00:20:44.38#ibcon#end of sib2, iclass 6, count 2 2006.286.00:20:44.38#ibcon#*after write, iclass 6, count 2 2006.286.00:20:44.38#ibcon#*before return 0, iclass 6, count 2 2006.286.00:20:44.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:20:44.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:20:44.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.00:20:44.38#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:44.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:20:44.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:20:44.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:20:44.50#ibcon#enter wrdev, iclass 6, count 0 2006.286.00:20:44.50#ibcon#first serial, iclass 6, count 0 2006.286.00:20:44.50#ibcon#enter sib2, iclass 6, count 0 2006.286.00:20:44.50#ibcon#flushed, iclass 6, count 0 2006.286.00:20:44.50#ibcon#about to write, iclass 6, count 0 2006.286.00:20:44.50#ibcon#wrote, iclass 6, count 0 2006.286.00:20:44.50#ibcon#about to read 3, iclass 6, count 0 2006.286.00:20:44.52#ibcon#read 3, iclass 6, count 0 2006.286.00:20:44.52#ibcon#about to read 4, iclass 6, count 0 2006.286.00:20:44.52#ibcon#read 4, iclass 6, count 0 2006.286.00:20:44.52#ibcon#about to read 5, iclass 6, count 0 2006.286.00:20:44.52#ibcon#read 5, iclass 6, count 0 2006.286.00:20:44.52#ibcon#about to read 6, iclass 6, count 0 2006.286.00:20:44.52#ibcon#read 6, iclass 6, count 0 2006.286.00:20:44.52#ibcon#end of sib2, iclass 6, count 0 2006.286.00:20:44.52#ibcon#*mode == 0, iclass 6, count 0 2006.286.00:20:44.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.00:20:44.52#ibcon#[27=USB\r\n] 2006.286.00:20:44.52#ibcon#*before write, iclass 6, count 0 2006.286.00:20:44.52#ibcon#enter sib2, iclass 6, count 0 2006.286.00:20:44.52#ibcon#flushed, iclass 6, count 0 2006.286.00:20:44.52#ibcon#about to write, iclass 6, count 0 2006.286.00:20:44.52#ibcon#wrote, iclass 6, count 0 2006.286.00:20:44.52#ibcon#about to read 3, iclass 6, count 0 2006.286.00:20:44.55#ibcon#read 3, iclass 6, count 0 2006.286.00:20:44.55#ibcon#about to read 4, iclass 6, count 0 2006.286.00:20:44.55#ibcon#read 4, iclass 6, count 0 2006.286.00:20:44.55#ibcon#about to read 5, iclass 6, count 0 2006.286.00:20:44.55#ibcon#read 5, iclass 6, count 0 2006.286.00:20:44.55#ibcon#about to read 6, iclass 6, count 0 2006.286.00:20:44.55#ibcon#read 6, iclass 6, count 0 2006.286.00:20:44.55#ibcon#end of sib2, iclass 6, count 0 2006.286.00:20:44.55#ibcon#*after write, iclass 6, count 0 2006.286.00:20:44.55#ibcon#*before return 0, iclass 6, count 0 2006.286.00:20:44.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:20:44.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:20:44.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.00:20:44.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.00:20:44.55$vck44/vblo=5,709.99 2006.286.00:20:44.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.00:20:44.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.00:20:44.55#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:44.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:20:44.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:20:44.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:20:44.55#ibcon#enter wrdev, iclass 10, count 0 2006.286.00:20:44.55#ibcon#first serial, iclass 10, count 0 2006.286.00:20:44.55#ibcon#enter sib2, iclass 10, count 0 2006.286.00:20:44.55#ibcon#flushed, iclass 10, count 0 2006.286.00:20:44.55#ibcon#about to write, iclass 10, count 0 2006.286.00:20:44.55#ibcon#wrote, iclass 10, count 0 2006.286.00:20:44.55#ibcon#about to read 3, iclass 10, count 0 2006.286.00:20:44.57#ibcon#read 3, iclass 10, count 0 2006.286.00:20:44.57#ibcon#about to read 4, iclass 10, count 0 2006.286.00:20:44.57#ibcon#read 4, iclass 10, count 0 2006.286.00:20:44.57#ibcon#about to read 5, iclass 10, count 0 2006.286.00:20:44.57#ibcon#read 5, iclass 10, count 0 2006.286.00:20:44.57#ibcon#about to read 6, iclass 10, count 0 2006.286.00:20:44.57#ibcon#read 6, iclass 10, count 0 2006.286.00:20:44.57#ibcon#end of sib2, iclass 10, count 0 2006.286.00:20:44.57#ibcon#*mode == 0, iclass 10, count 0 2006.286.00:20:44.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.00:20:44.57#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.00:20:44.57#ibcon#*before write, iclass 10, count 0 2006.286.00:20:44.57#ibcon#enter sib2, iclass 10, count 0 2006.286.00:20:44.57#ibcon#flushed, iclass 10, count 0 2006.286.00:20:44.57#ibcon#about to write, iclass 10, count 0 2006.286.00:20:44.57#ibcon#wrote, iclass 10, count 0 2006.286.00:20:44.57#ibcon#about to read 3, iclass 10, count 0 2006.286.00:20:44.61#ibcon#read 3, iclass 10, count 0 2006.286.00:20:44.61#ibcon#about to read 4, iclass 10, count 0 2006.286.00:20:44.61#ibcon#read 4, iclass 10, count 0 2006.286.00:20:44.61#ibcon#about to read 5, iclass 10, count 0 2006.286.00:20:44.61#ibcon#read 5, iclass 10, count 0 2006.286.00:20:44.61#ibcon#about to read 6, iclass 10, count 0 2006.286.00:20:44.61#ibcon#read 6, iclass 10, count 0 2006.286.00:20:44.61#ibcon#end of sib2, iclass 10, count 0 2006.286.00:20:44.61#ibcon#*after write, iclass 10, count 0 2006.286.00:20:44.61#ibcon#*before return 0, iclass 10, count 0 2006.286.00:20:44.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:20:44.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:20:44.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.00:20:44.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.00:20:44.61$vck44/vb=5,4 2006.286.00:20:44.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.00:20:44.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.00:20:44.61#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:44.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:20:44.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:20:44.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:20:44.67#ibcon#enter wrdev, iclass 12, count 2 2006.286.00:20:44.67#ibcon#first serial, iclass 12, count 2 2006.286.00:20:44.67#ibcon#enter sib2, iclass 12, count 2 2006.286.00:20:44.67#ibcon#flushed, iclass 12, count 2 2006.286.00:20:44.67#ibcon#about to write, iclass 12, count 2 2006.286.00:20:44.67#ibcon#wrote, iclass 12, count 2 2006.286.00:20:44.67#ibcon#about to read 3, iclass 12, count 2 2006.286.00:20:44.69#ibcon#read 3, iclass 12, count 2 2006.286.00:20:44.69#ibcon#about to read 4, iclass 12, count 2 2006.286.00:20:44.69#ibcon#read 4, iclass 12, count 2 2006.286.00:20:44.69#ibcon#about to read 5, iclass 12, count 2 2006.286.00:20:44.69#ibcon#read 5, iclass 12, count 2 2006.286.00:20:44.69#ibcon#about to read 6, iclass 12, count 2 2006.286.00:20:44.69#ibcon#read 6, iclass 12, count 2 2006.286.00:20:44.69#ibcon#end of sib2, iclass 12, count 2 2006.286.00:20:44.69#ibcon#*mode == 0, iclass 12, count 2 2006.286.00:20:44.69#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.00:20:44.69#ibcon#[27=AT05-04\r\n] 2006.286.00:20:44.69#ibcon#*before write, iclass 12, count 2 2006.286.00:20:44.69#ibcon#enter sib2, iclass 12, count 2 2006.286.00:20:44.69#ibcon#flushed, iclass 12, count 2 2006.286.00:20:44.69#ibcon#about to write, iclass 12, count 2 2006.286.00:20:44.69#ibcon#wrote, iclass 12, count 2 2006.286.00:20:44.69#ibcon#about to read 3, iclass 12, count 2 2006.286.00:20:44.72#ibcon#read 3, iclass 12, count 2 2006.286.00:20:44.72#ibcon#about to read 4, iclass 12, count 2 2006.286.00:20:44.72#ibcon#read 4, iclass 12, count 2 2006.286.00:20:44.72#ibcon#about to read 5, iclass 12, count 2 2006.286.00:20:44.72#ibcon#read 5, iclass 12, count 2 2006.286.00:20:44.72#ibcon#about to read 6, iclass 12, count 2 2006.286.00:20:44.72#ibcon#read 6, iclass 12, count 2 2006.286.00:20:44.72#ibcon#end of sib2, iclass 12, count 2 2006.286.00:20:44.72#ibcon#*after write, iclass 12, count 2 2006.286.00:20:44.72#ibcon#*before return 0, iclass 12, count 2 2006.286.00:20:44.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:20:44.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:20:44.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.00:20:44.72#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:44.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:20:44.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:20:44.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:20:44.84#ibcon#enter wrdev, iclass 12, count 0 2006.286.00:20:44.84#ibcon#first serial, iclass 12, count 0 2006.286.00:20:44.84#ibcon#enter sib2, iclass 12, count 0 2006.286.00:20:44.84#ibcon#flushed, iclass 12, count 0 2006.286.00:20:44.84#ibcon#about to write, iclass 12, count 0 2006.286.00:20:44.84#ibcon#wrote, iclass 12, count 0 2006.286.00:20:44.84#ibcon#about to read 3, iclass 12, count 0 2006.286.00:20:44.86#ibcon#read 3, iclass 12, count 0 2006.286.00:20:44.86#ibcon#about to read 4, iclass 12, count 0 2006.286.00:20:44.86#ibcon#read 4, iclass 12, count 0 2006.286.00:20:44.86#ibcon#about to read 5, iclass 12, count 0 2006.286.00:20:44.86#ibcon#read 5, iclass 12, count 0 2006.286.00:20:44.86#ibcon#about to read 6, iclass 12, count 0 2006.286.00:20:44.86#ibcon#read 6, iclass 12, count 0 2006.286.00:20:44.86#ibcon#end of sib2, iclass 12, count 0 2006.286.00:20:44.86#ibcon#*mode == 0, iclass 12, count 0 2006.286.00:20:44.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.00:20:44.86#ibcon#[27=USB\r\n] 2006.286.00:20:44.86#ibcon#*before write, iclass 12, count 0 2006.286.00:20:44.86#ibcon#enter sib2, iclass 12, count 0 2006.286.00:20:44.86#ibcon#flushed, iclass 12, count 0 2006.286.00:20:44.86#ibcon#about to write, iclass 12, count 0 2006.286.00:20:44.86#ibcon#wrote, iclass 12, count 0 2006.286.00:20:44.86#ibcon#about to read 3, iclass 12, count 0 2006.286.00:20:44.89#ibcon#read 3, iclass 12, count 0 2006.286.00:20:44.89#ibcon#about to read 4, iclass 12, count 0 2006.286.00:20:44.89#ibcon#read 4, iclass 12, count 0 2006.286.00:20:44.89#ibcon#about to read 5, iclass 12, count 0 2006.286.00:20:44.89#ibcon#read 5, iclass 12, count 0 2006.286.00:20:44.89#ibcon#about to read 6, iclass 12, count 0 2006.286.00:20:44.89#ibcon#read 6, iclass 12, count 0 2006.286.00:20:44.89#ibcon#end of sib2, iclass 12, count 0 2006.286.00:20:44.89#ibcon#*after write, iclass 12, count 0 2006.286.00:20:44.89#ibcon#*before return 0, iclass 12, count 0 2006.286.00:20:44.89#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:20:44.89#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:20:44.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.00:20:44.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.00:20:44.89$vck44/vblo=6,719.99 2006.286.00:20:44.89#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.00:20:44.89#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.00:20:44.89#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:44.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:20:44.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:20:44.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:20:44.89#ibcon#enter wrdev, iclass 14, count 0 2006.286.00:20:44.89#ibcon#first serial, iclass 14, count 0 2006.286.00:20:44.89#ibcon#enter sib2, iclass 14, count 0 2006.286.00:20:44.89#ibcon#flushed, iclass 14, count 0 2006.286.00:20:44.89#ibcon#about to write, iclass 14, count 0 2006.286.00:20:44.89#ibcon#wrote, iclass 14, count 0 2006.286.00:20:44.89#ibcon#about to read 3, iclass 14, count 0 2006.286.00:20:44.91#ibcon#read 3, iclass 14, count 0 2006.286.00:20:44.91#ibcon#about to read 4, iclass 14, count 0 2006.286.00:20:44.91#ibcon#read 4, iclass 14, count 0 2006.286.00:20:44.91#ibcon#about to read 5, iclass 14, count 0 2006.286.00:20:44.91#ibcon#read 5, iclass 14, count 0 2006.286.00:20:44.91#ibcon#about to read 6, iclass 14, count 0 2006.286.00:20:44.91#ibcon#read 6, iclass 14, count 0 2006.286.00:20:44.91#ibcon#end of sib2, iclass 14, count 0 2006.286.00:20:44.91#ibcon#*mode == 0, iclass 14, count 0 2006.286.00:20:44.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.00:20:44.91#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.00:20:44.91#ibcon#*before write, iclass 14, count 0 2006.286.00:20:44.91#ibcon#enter sib2, iclass 14, count 0 2006.286.00:20:44.91#ibcon#flushed, iclass 14, count 0 2006.286.00:20:44.91#ibcon#about to write, iclass 14, count 0 2006.286.00:20:44.91#ibcon#wrote, iclass 14, count 0 2006.286.00:20:44.91#ibcon#about to read 3, iclass 14, count 0 2006.286.00:20:44.95#ibcon#read 3, iclass 14, count 0 2006.286.00:20:44.95#ibcon#about to read 4, iclass 14, count 0 2006.286.00:20:44.95#ibcon#read 4, iclass 14, count 0 2006.286.00:20:44.95#ibcon#about to read 5, iclass 14, count 0 2006.286.00:20:44.95#ibcon#read 5, iclass 14, count 0 2006.286.00:20:44.95#ibcon#about to read 6, iclass 14, count 0 2006.286.00:20:44.95#ibcon#read 6, iclass 14, count 0 2006.286.00:20:44.95#ibcon#end of sib2, iclass 14, count 0 2006.286.00:20:44.95#ibcon#*after write, iclass 14, count 0 2006.286.00:20:44.95#ibcon#*before return 0, iclass 14, count 0 2006.286.00:20:44.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:20:44.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:20:44.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.00:20:44.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.00:20:44.95$vck44/vb=6,3 2006.286.00:20:44.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.00:20:44.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.00:20:44.95#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:44.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:20:45.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:20:45.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:20:45.01#ibcon#enter wrdev, iclass 16, count 2 2006.286.00:20:45.01#ibcon#first serial, iclass 16, count 2 2006.286.00:20:45.01#ibcon#enter sib2, iclass 16, count 2 2006.286.00:20:45.01#ibcon#flushed, iclass 16, count 2 2006.286.00:20:45.01#ibcon#about to write, iclass 16, count 2 2006.286.00:20:45.01#ibcon#wrote, iclass 16, count 2 2006.286.00:20:45.01#ibcon#about to read 3, iclass 16, count 2 2006.286.00:20:45.03#ibcon#read 3, iclass 16, count 2 2006.286.00:20:45.03#ibcon#about to read 4, iclass 16, count 2 2006.286.00:20:45.03#ibcon#read 4, iclass 16, count 2 2006.286.00:20:45.03#ibcon#about to read 5, iclass 16, count 2 2006.286.00:20:45.03#ibcon#read 5, iclass 16, count 2 2006.286.00:20:45.03#ibcon#about to read 6, iclass 16, count 2 2006.286.00:20:45.03#ibcon#read 6, iclass 16, count 2 2006.286.00:20:45.03#ibcon#end of sib2, iclass 16, count 2 2006.286.00:20:45.03#ibcon#*mode == 0, iclass 16, count 2 2006.286.00:20:45.03#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.00:20:45.03#ibcon#[27=AT06-03\r\n] 2006.286.00:20:45.03#ibcon#*before write, iclass 16, count 2 2006.286.00:20:45.03#ibcon#enter sib2, iclass 16, count 2 2006.286.00:20:45.03#ibcon#flushed, iclass 16, count 2 2006.286.00:20:45.03#ibcon#about to write, iclass 16, count 2 2006.286.00:20:45.03#ibcon#wrote, iclass 16, count 2 2006.286.00:20:45.03#ibcon#about to read 3, iclass 16, count 2 2006.286.00:20:45.06#ibcon#read 3, iclass 16, count 2 2006.286.00:20:45.06#ibcon#about to read 4, iclass 16, count 2 2006.286.00:20:45.06#ibcon#read 4, iclass 16, count 2 2006.286.00:20:45.06#ibcon#about to read 5, iclass 16, count 2 2006.286.00:20:45.06#ibcon#read 5, iclass 16, count 2 2006.286.00:20:45.06#ibcon#about to read 6, iclass 16, count 2 2006.286.00:20:45.06#ibcon#read 6, iclass 16, count 2 2006.286.00:20:45.06#ibcon#end of sib2, iclass 16, count 2 2006.286.00:20:45.06#ibcon#*after write, iclass 16, count 2 2006.286.00:20:45.06#ibcon#*before return 0, iclass 16, count 2 2006.286.00:20:45.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:20:45.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:20:45.06#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.00:20:45.06#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:45.06#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:20:45.18#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:20:45.18#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:20:45.18#ibcon#enter wrdev, iclass 16, count 0 2006.286.00:20:45.18#ibcon#first serial, iclass 16, count 0 2006.286.00:20:45.18#ibcon#enter sib2, iclass 16, count 0 2006.286.00:20:45.18#ibcon#flushed, iclass 16, count 0 2006.286.00:20:45.18#ibcon#about to write, iclass 16, count 0 2006.286.00:20:45.18#ibcon#wrote, iclass 16, count 0 2006.286.00:20:45.18#ibcon#about to read 3, iclass 16, count 0 2006.286.00:20:45.20#ibcon#read 3, iclass 16, count 0 2006.286.00:20:45.20#ibcon#about to read 4, iclass 16, count 0 2006.286.00:20:45.20#ibcon#read 4, iclass 16, count 0 2006.286.00:20:45.20#ibcon#about to read 5, iclass 16, count 0 2006.286.00:20:45.20#ibcon#read 5, iclass 16, count 0 2006.286.00:20:45.20#ibcon#about to read 6, iclass 16, count 0 2006.286.00:20:45.20#ibcon#read 6, iclass 16, count 0 2006.286.00:20:45.20#ibcon#end of sib2, iclass 16, count 0 2006.286.00:20:45.20#ibcon#*mode == 0, iclass 16, count 0 2006.286.00:20:45.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.00:20:45.20#ibcon#[27=USB\r\n] 2006.286.00:20:45.20#ibcon#*before write, iclass 16, count 0 2006.286.00:20:45.20#ibcon#enter sib2, iclass 16, count 0 2006.286.00:20:45.20#ibcon#flushed, iclass 16, count 0 2006.286.00:20:45.20#ibcon#about to write, iclass 16, count 0 2006.286.00:20:45.20#ibcon#wrote, iclass 16, count 0 2006.286.00:20:45.20#ibcon#about to read 3, iclass 16, count 0 2006.286.00:20:45.23#ibcon#read 3, iclass 16, count 0 2006.286.00:20:45.23#ibcon#about to read 4, iclass 16, count 0 2006.286.00:20:45.23#ibcon#read 4, iclass 16, count 0 2006.286.00:20:45.23#ibcon#about to read 5, iclass 16, count 0 2006.286.00:20:45.23#ibcon#read 5, iclass 16, count 0 2006.286.00:20:45.23#ibcon#about to read 6, iclass 16, count 0 2006.286.00:20:45.23#ibcon#read 6, iclass 16, count 0 2006.286.00:20:45.23#ibcon#end of sib2, iclass 16, count 0 2006.286.00:20:45.23#ibcon#*after write, iclass 16, count 0 2006.286.00:20:45.23#ibcon#*before return 0, iclass 16, count 0 2006.286.00:20:45.23#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:20:45.23#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:20:45.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.00:20:45.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.00:20:45.23$vck44/vblo=7,734.99 2006.286.00:20:45.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.00:20:45.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.00:20:45.23#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:45.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:20:45.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:20:45.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:20:45.23#ibcon#enter wrdev, iclass 18, count 0 2006.286.00:20:45.23#ibcon#first serial, iclass 18, count 0 2006.286.00:20:45.23#ibcon#enter sib2, iclass 18, count 0 2006.286.00:20:45.23#ibcon#flushed, iclass 18, count 0 2006.286.00:20:45.23#ibcon#about to write, iclass 18, count 0 2006.286.00:20:45.23#ibcon#wrote, iclass 18, count 0 2006.286.00:20:45.23#ibcon#about to read 3, iclass 18, count 0 2006.286.00:20:45.25#ibcon#read 3, iclass 18, count 0 2006.286.00:20:45.25#ibcon#about to read 4, iclass 18, count 0 2006.286.00:20:45.25#ibcon#read 4, iclass 18, count 0 2006.286.00:20:45.25#ibcon#about to read 5, iclass 18, count 0 2006.286.00:20:45.25#ibcon#read 5, iclass 18, count 0 2006.286.00:20:45.25#ibcon#about to read 6, iclass 18, count 0 2006.286.00:20:45.25#ibcon#read 6, iclass 18, count 0 2006.286.00:20:45.25#ibcon#end of sib2, iclass 18, count 0 2006.286.00:20:45.25#ibcon#*mode == 0, iclass 18, count 0 2006.286.00:20:45.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.00:20:45.25#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.00:20:45.25#ibcon#*before write, iclass 18, count 0 2006.286.00:20:45.25#ibcon#enter sib2, iclass 18, count 0 2006.286.00:20:45.25#ibcon#flushed, iclass 18, count 0 2006.286.00:20:45.25#ibcon#about to write, iclass 18, count 0 2006.286.00:20:45.25#ibcon#wrote, iclass 18, count 0 2006.286.00:20:45.25#ibcon#about to read 3, iclass 18, count 0 2006.286.00:20:45.29#ibcon#read 3, iclass 18, count 0 2006.286.00:20:45.29#ibcon#about to read 4, iclass 18, count 0 2006.286.00:20:45.29#ibcon#read 4, iclass 18, count 0 2006.286.00:20:45.29#ibcon#about to read 5, iclass 18, count 0 2006.286.00:20:45.29#ibcon#read 5, iclass 18, count 0 2006.286.00:20:45.29#ibcon#about to read 6, iclass 18, count 0 2006.286.00:20:45.29#ibcon#read 6, iclass 18, count 0 2006.286.00:20:45.29#ibcon#end of sib2, iclass 18, count 0 2006.286.00:20:45.29#ibcon#*after write, iclass 18, count 0 2006.286.00:20:45.29#ibcon#*before return 0, iclass 18, count 0 2006.286.00:20:45.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:20:45.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:20:45.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.00:20:45.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.00:20:45.29$vck44/vb=7,4 2006.286.00:20:45.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.00:20:45.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.00:20:45.29#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:45.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:20:45.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:20:45.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:20:45.35#ibcon#enter wrdev, iclass 20, count 2 2006.286.00:20:45.35#ibcon#first serial, iclass 20, count 2 2006.286.00:20:45.35#ibcon#enter sib2, iclass 20, count 2 2006.286.00:20:45.35#ibcon#flushed, iclass 20, count 2 2006.286.00:20:45.35#ibcon#about to write, iclass 20, count 2 2006.286.00:20:45.35#ibcon#wrote, iclass 20, count 2 2006.286.00:20:45.35#ibcon#about to read 3, iclass 20, count 2 2006.286.00:20:45.37#ibcon#read 3, iclass 20, count 2 2006.286.00:20:45.37#ibcon#about to read 4, iclass 20, count 2 2006.286.00:20:45.37#ibcon#read 4, iclass 20, count 2 2006.286.00:20:45.37#ibcon#about to read 5, iclass 20, count 2 2006.286.00:20:45.37#ibcon#read 5, iclass 20, count 2 2006.286.00:20:45.37#ibcon#about to read 6, iclass 20, count 2 2006.286.00:20:45.37#ibcon#read 6, iclass 20, count 2 2006.286.00:20:45.37#ibcon#end of sib2, iclass 20, count 2 2006.286.00:20:45.37#ibcon#*mode == 0, iclass 20, count 2 2006.286.00:20:45.37#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.00:20:45.37#ibcon#[27=AT07-04\r\n] 2006.286.00:20:45.37#ibcon#*before write, iclass 20, count 2 2006.286.00:20:45.37#ibcon#enter sib2, iclass 20, count 2 2006.286.00:20:45.37#ibcon#flushed, iclass 20, count 2 2006.286.00:20:45.37#ibcon#about to write, iclass 20, count 2 2006.286.00:20:45.37#ibcon#wrote, iclass 20, count 2 2006.286.00:20:45.37#ibcon#about to read 3, iclass 20, count 2 2006.286.00:20:45.40#ibcon#read 3, iclass 20, count 2 2006.286.00:20:45.40#ibcon#about to read 4, iclass 20, count 2 2006.286.00:20:45.40#ibcon#read 4, iclass 20, count 2 2006.286.00:20:45.40#ibcon#about to read 5, iclass 20, count 2 2006.286.00:20:45.40#ibcon#read 5, iclass 20, count 2 2006.286.00:20:45.40#ibcon#about to read 6, iclass 20, count 2 2006.286.00:20:45.40#ibcon#read 6, iclass 20, count 2 2006.286.00:20:45.40#ibcon#end of sib2, iclass 20, count 2 2006.286.00:20:45.40#ibcon#*after write, iclass 20, count 2 2006.286.00:20:45.40#ibcon#*before return 0, iclass 20, count 2 2006.286.00:20:45.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:20:45.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:20:45.40#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.00:20:45.40#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:45.40#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:20:45.52#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:20:45.52#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:20:45.52#ibcon#enter wrdev, iclass 20, count 0 2006.286.00:20:45.52#ibcon#first serial, iclass 20, count 0 2006.286.00:20:45.52#ibcon#enter sib2, iclass 20, count 0 2006.286.00:20:45.52#ibcon#flushed, iclass 20, count 0 2006.286.00:20:45.52#ibcon#about to write, iclass 20, count 0 2006.286.00:20:45.52#ibcon#wrote, iclass 20, count 0 2006.286.00:20:45.52#ibcon#about to read 3, iclass 20, count 0 2006.286.00:20:45.54#ibcon#read 3, iclass 20, count 0 2006.286.00:20:45.54#ibcon#about to read 4, iclass 20, count 0 2006.286.00:20:45.54#ibcon#read 4, iclass 20, count 0 2006.286.00:20:45.54#ibcon#about to read 5, iclass 20, count 0 2006.286.00:20:45.54#ibcon#read 5, iclass 20, count 0 2006.286.00:20:45.54#ibcon#about to read 6, iclass 20, count 0 2006.286.00:20:45.54#ibcon#read 6, iclass 20, count 0 2006.286.00:20:45.54#ibcon#end of sib2, iclass 20, count 0 2006.286.00:20:45.54#ibcon#*mode == 0, iclass 20, count 0 2006.286.00:20:45.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.00:20:45.54#ibcon#[27=USB\r\n] 2006.286.00:20:45.54#ibcon#*before write, iclass 20, count 0 2006.286.00:20:45.54#ibcon#enter sib2, iclass 20, count 0 2006.286.00:20:45.54#ibcon#flushed, iclass 20, count 0 2006.286.00:20:45.54#ibcon#about to write, iclass 20, count 0 2006.286.00:20:45.54#ibcon#wrote, iclass 20, count 0 2006.286.00:20:45.54#ibcon#about to read 3, iclass 20, count 0 2006.286.00:20:45.57#ibcon#read 3, iclass 20, count 0 2006.286.00:20:45.57#ibcon#about to read 4, iclass 20, count 0 2006.286.00:20:45.57#ibcon#read 4, iclass 20, count 0 2006.286.00:20:45.57#ibcon#about to read 5, iclass 20, count 0 2006.286.00:20:45.57#ibcon#read 5, iclass 20, count 0 2006.286.00:20:45.57#ibcon#about to read 6, iclass 20, count 0 2006.286.00:20:45.57#ibcon#read 6, iclass 20, count 0 2006.286.00:20:45.57#ibcon#end of sib2, iclass 20, count 0 2006.286.00:20:45.57#ibcon#*after write, iclass 20, count 0 2006.286.00:20:45.57#ibcon#*before return 0, iclass 20, count 0 2006.286.00:20:45.57#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:20:45.57#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:20:45.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.00:20:45.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.00:20:45.57$vck44/vblo=8,744.99 2006.286.00:20:45.57#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.00:20:45.57#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.00:20:45.57#ibcon#ireg 17 cls_cnt 0 2006.286.00:20:45.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:20:45.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:20:45.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:20:45.57#ibcon#enter wrdev, iclass 22, count 0 2006.286.00:20:45.57#ibcon#first serial, iclass 22, count 0 2006.286.00:20:45.57#ibcon#enter sib2, iclass 22, count 0 2006.286.00:20:45.57#ibcon#flushed, iclass 22, count 0 2006.286.00:20:45.57#ibcon#about to write, iclass 22, count 0 2006.286.00:20:45.57#ibcon#wrote, iclass 22, count 0 2006.286.00:20:45.57#ibcon#about to read 3, iclass 22, count 0 2006.286.00:20:45.59#ibcon#read 3, iclass 22, count 0 2006.286.00:20:45.59#ibcon#about to read 4, iclass 22, count 0 2006.286.00:20:45.59#ibcon#read 4, iclass 22, count 0 2006.286.00:20:45.59#ibcon#about to read 5, iclass 22, count 0 2006.286.00:20:45.59#ibcon#read 5, iclass 22, count 0 2006.286.00:20:45.59#ibcon#about to read 6, iclass 22, count 0 2006.286.00:20:45.59#ibcon#read 6, iclass 22, count 0 2006.286.00:20:45.59#ibcon#end of sib2, iclass 22, count 0 2006.286.00:20:45.59#ibcon#*mode == 0, iclass 22, count 0 2006.286.00:20:45.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.00:20:45.59#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.00:20:45.59#ibcon#*before write, iclass 22, count 0 2006.286.00:20:45.59#ibcon#enter sib2, iclass 22, count 0 2006.286.00:20:45.59#ibcon#flushed, iclass 22, count 0 2006.286.00:20:45.59#ibcon#about to write, iclass 22, count 0 2006.286.00:20:45.59#ibcon#wrote, iclass 22, count 0 2006.286.00:20:45.59#ibcon#about to read 3, iclass 22, count 0 2006.286.00:20:45.63#ibcon#read 3, iclass 22, count 0 2006.286.00:20:45.63#ibcon#about to read 4, iclass 22, count 0 2006.286.00:20:45.63#ibcon#read 4, iclass 22, count 0 2006.286.00:20:45.63#ibcon#about to read 5, iclass 22, count 0 2006.286.00:20:45.63#ibcon#read 5, iclass 22, count 0 2006.286.00:20:45.63#ibcon#about to read 6, iclass 22, count 0 2006.286.00:20:45.63#ibcon#read 6, iclass 22, count 0 2006.286.00:20:45.63#ibcon#end of sib2, iclass 22, count 0 2006.286.00:20:45.63#ibcon#*after write, iclass 22, count 0 2006.286.00:20:45.63#ibcon#*before return 0, iclass 22, count 0 2006.286.00:20:45.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:20:45.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:20:45.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.00:20:45.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.00:20:45.63$vck44/vb=8,4 2006.286.00:20:45.63#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.00:20:45.63#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.00:20:45.63#ibcon#ireg 11 cls_cnt 2 2006.286.00:20:45.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:20:45.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:20:45.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:20:45.69#ibcon#enter wrdev, iclass 24, count 2 2006.286.00:20:45.69#ibcon#first serial, iclass 24, count 2 2006.286.00:20:45.69#ibcon#enter sib2, iclass 24, count 2 2006.286.00:20:45.69#ibcon#flushed, iclass 24, count 2 2006.286.00:20:45.69#ibcon#about to write, iclass 24, count 2 2006.286.00:20:45.69#ibcon#wrote, iclass 24, count 2 2006.286.00:20:45.69#ibcon#about to read 3, iclass 24, count 2 2006.286.00:20:45.71#ibcon#read 3, iclass 24, count 2 2006.286.00:20:45.71#ibcon#about to read 4, iclass 24, count 2 2006.286.00:20:45.71#ibcon#read 4, iclass 24, count 2 2006.286.00:20:45.71#ibcon#about to read 5, iclass 24, count 2 2006.286.00:20:45.71#ibcon#read 5, iclass 24, count 2 2006.286.00:20:45.71#ibcon#about to read 6, iclass 24, count 2 2006.286.00:20:45.71#ibcon#read 6, iclass 24, count 2 2006.286.00:20:45.71#ibcon#end of sib2, iclass 24, count 2 2006.286.00:20:45.71#ibcon#*mode == 0, iclass 24, count 2 2006.286.00:20:45.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.00:20:45.71#ibcon#[27=AT08-04\r\n] 2006.286.00:20:45.71#ibcon#*before write, iclass 24, count 2 2006.286.00:20:45.71#ibcon#enter sib2, iclass 24, count 2 2006.286.00:20:45.71#ibcon#flushed, iclass 24, count 2 2006.286.00:20:45.71#ibcon#about to write, iclass 24, count 2 2006.286.00:20:45.71#ibcon#wrote, iclass 24, count 2 2006.286.00:20:45.71#ibcon#about to read 3, iclass 24, count 2 2006.286.00:20:45.74#ibcon#read 3, iclass 24, count 2 2006.286.00:20:45.74#ibcon#about to read 4, iclass 24, count 2 2006.286.00:20:45.74#ibcon#read 4, iclass 24, count 2 2006.286.00:20:45.74#ibcon#about to read 5, iclass 24, count 2 2006.286.00:20:45.74#ibcon#read 5, iclass 24, count 2 2006.286.00:20:45.74#ibcon#about to read 6, iclass 24, count 2 2006.286.00:20:45.74#ibcon#read 6, iclass 24, count 2 2006.286.00:20:45.74#ibcon#end of sib2, iclass 24, count 2 2006.286.00:20:45.74#ibcon#*after write, iclass 24, count 2 2006.286.00:20:45.74#ibcon#*before return 0, iclass 24, count 2 2006.286.00:20:45.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:20:45.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:20:45.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.00:20:45.74#ibcon#ireg 7 cls_cnt 0 2006.286.00:20:45.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:20:45.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:20:45.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:20:45.86#ibcon#enter wrdev, iclass 24, count 0 2006.286.00:20:45.86#ibcon#first serial, iclass 24, count 0 2006.286.00:20:45.86#ibcon#enter sib2, iclass 24, count 0 2006.286.00:20:45.86#ibcon#flushed, iclass 24, count 0 2006.286.00:20:45.86#ibcon#about to write, iclass 24, count 0 2006.286.00:20:45.86#ibcon#wrote, iclass 24, count 0 2006.286.00:20:45.86#ibcon#about to read 3, iclass 24, count 0 2006.286.00:20:45.88#ibcon#read 3, iclass 24, count 0 2006.286.00:20:45.88#ibcon#about to read 4, iclass 24, count 0 2006.286.00:20:45.88#ibcon#read 4, iclass 24, count 0 2006.286.00:20:45.88#ibcon#about to read 5, iclass 24, count 0 2006.286.00:20:45.88#ibcon#read 5, iclass 24, count 0 2006.286.00:20:45.88#ibcon#about to read 6, iclass 24, count 0 2006.286.00:20:45.88#ibcon#read 6, iclass 24, count 0 2006.286.00:20:45.88#ibcon#end of sib2, iclass 24, count 0 2006.286.00:20:45.88#ibcon#*mode == 0, iclass 24, count 0 2006.286.00:20:45.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.00:20:45.88#ibcon#[27=USB\r\n] 2006.286.00:20:45.88#ibcon#*before write, iclass 24, count 0 2006.286.00:20:45.88#ibcon#enter sib2, iclass 24, count 0 2006.286.00:20:45.88#ibcon#flushed, iclass 24, count 0 2006.286.00:20:45.88#ibcon#about to write, iclass 24, count 0 2006.286.00:20:45.88#ibcon#wrote, iclass 24, count 0 2006.286.00:20:45.88#ibcon#about to read 3, iclass 24, count 0 2006.286.00:20:45.91#ibcon#read 3, iclass 24, count 0 2006.286.00:20:45.91#ibcon#about to read 4, iclass 24, count 0 2006.286.00:20:45.91#ibcon#read 4, iclass 24, count 0 2006.286.00:20:45.91#ibcon#about to read 5, iclass 24, count 0 2006.286.00:20:45.91#ibcon#read 5, iclass 24, count 0 2006.286.00:20:45.91#ibcon#about to read 6, iclass 24, count 0 2006.286.00:20:45.91#ibcon#read 6, iclass 24, count 0 2006.286.00:20:45.91#ibcon#end of sib2, iclass 24, count 0 2006.286.00:20:45.91#ibcon#*after write, iclass 24, count 0 2006.286.00:20:45.91#ibcon#*before return 0, iclass 24, count 0 2006.286.00:20:45.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:20:45.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:20:45.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.00:20:45.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.00:20:45.91$vck44/vabw=wide 2006.286.00:20:45.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.00:20:45.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.00:20:45.91#ibcon#ireg 8 cls_cnt 0 2006.286.00:20:45.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:20:45.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:20:45.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:20:45.91#ibcon#enter wrdev, iclass 26, count 0 2006.286.00:20:45.91#ibcon#first serial, iclass 26, count 0 2006.286.00:20:45.91#ibcon#enter sib2, iclass 26, count 0 2006.286.00:20:45.91#ibcon#flushed, iclass 26, count 0 2006.286.00:20:45.91#ibcon#about to write, iclass 26, count 0 2006.286.00:20:45.91#ibcon#wrote, iclass 26, count 0 2006.286.00:20:45.91#ibcon#about to read 3, iclass 26, count 0 2006.286.00:20:45.93#ibcon#read 3, iclass 26, count 0 2006.286.00:20:45.93#ibcon#about to read 4, iclass 26, count 0 2006.286.00:20:45.93#ibcon#read 4, iclass 26, count 0 2006.286.00:20:45.93#ibcon#about to read 5, iclass 26, count 0 2006.286.00:20:45.93#ibcon#read 5, iclass 26, count 0 2006.286.00:20:45.93#ibcon#about to read 6, iclass 26, count 0 2006.286.00:20:45.93#ibcon#read 6, iclass 26, count 0 2006.286.00:20:45.93#ibcon#end of sib2, iclass 26, count 0 2006.286.00:20:45.93#ibcon#*mode == 0, iclass 26, count 0 2006.286.00:20:45.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.00:20:45.93#ibcon#[25=BW32\r\n] 2006.286.00:20:45.93#ibcon#*before write, iclass 26, count 0 2006.286.00:20:45.93#ibcon#enter sib2, iclass 26, count 0 2006.286.00:20:45.93#ibcon#flushed, iclass 26, count 0 2006.286.00:20:45.93#ibcon#about to write, iclass 26, count 0 2006.286.00:20:45.93#ibcon#wrote, iclass 26, count 0 2006.286.00:20:45.93#ibcon#about to read 3, iclass 26, count 0 2006.286.00:20:45.96#ibcon#read 3, iclass 26, count 0 2006.286.00:20:45.96#ibcon#about to read 4, iclass 26, count 0 2006.286.00:20:45.96#ibcon#read 4, iclass 26, count 0 2006.286.00:20:45.96#ibcon#about to read 5, iclass 26, count 0 2006.286.00:20:45.96#ibcon#read 5, iclass 26, count 0 2006.286.00:20:45.96#ibcon#about to read 6, iclass 26, count 0 2006.286.00:20:45.96#ibcon#read 6, iclass 26, count 0 2006.286.00:20:45.96#ibcon#end of sib2, iclass 26, count 0 2006.286.00:20:45.96#ibcon#*after write, iclass 26, count 0 2006.286.00:20:45.96#ibcon#*before return 0, iclass 26, count 0 2006.286.00:20:45.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:20:45.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:20:45.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.00:20:45.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.00:20:45.96$vck44/vbbw=wide 2006.286.00:20:45.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.00:20:45.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.00:20:45.96#ibcon#ireg 8 cls_cnt 0 2006.286.00:20:45.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:20:46.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:20:46.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:20:46.03#ibcon#enter wrdev, iclass 28, count 0 2006.286.00:20:46.03#ibcon#first serial, iclass 28, count 0 2006.286.00:20:46.03#ibcon#enter sib2, iclass 28, count 0 2006.286.00:20:46.03#ibcon#flushed, iclass 28, count 0 2006.286.00:20:46.03#ibcon#about to write, iclass 28, count 0 2006.286.00:20:46.03#ibcon#wrote, iclass 28, count 0 2006.286.00:20:46.03#ibcon#about to read 3, iclass 28, count 0 2006.286.00:20:46.05#ibcon#read 3, iclass 28, count 0 2006.286.00:20:46.05#ibcon#about to read 4, iclass 28, count 0 2006.286.00:20:46.05#ibcon#read 4, iclass 28, count 0 2006.286.00:20:46.05#ibcon#about to read 5, iclass 28, count 0 2006.286.00:20:46.05#ibcon#read 5, iclass 28, count 0 2006.286.00:20:46.05#ibcon#about to read 6, iclass 28, count 0 2006.286.00:20:46.05#ibcon#read 6, iclass 28, count 0 2006.286.00:20:46.05#ibcon#end of sib2, iclass 28, count 0 2006.286.00:20:46.05#ibcon#*mode == 0, iclass 28, count 0 2006.286.00:20:46.05#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.00:20:46.05#ibcon#[27=BW32\r\n] 2006.286.00:20:46.05#ibcon#*before write, iclass 28, count 0 2006.286.00:20:46.05#ibcon#enter sib2, iclass 28, count 0 2006.286.00:20:46.05#ibcon#flushed, iclass 28, count 0 2006.286.00:20:46.05#ibcon#about to write, iclass 28, count 0 2006.286.00:20:46.05#ibcon#wrote, iclass 28, count 0 2006.286.00:20:46.05#ibcon#about to read 3, iclass 28, count 0 2006.286.00:20:46.08#ibcon#read 3, iclass 28, count 0 2006.286.00:20:46.08#ibcon#about to read 4, iclass 28, count 0 2006.286.00:20:46.08#ibcon#read 4, iclass 28, count 0 2006.286.00:20:46.08#ibcon#about to read 5, iclass 28, count 0 2006.286.00:20:46.08#ibcon#read 5, iclass 28, count 0 2006.286.00:20:46.08#ibcon#about to read 6, iclass 28, count 0 2006.286.00:20:46.08#ibcon#read 6, iclass 28, count 0 2006.286.00:20:46.08#ibcon#end of sib2, iclass 28, count 0 2006.286.00:20:46.08#ibcon#*after write, iclass 28, count 0 2006.286.00:20:46.08#ibcon#*before return 0, iclass 28, count 0 2006.286.00:20:46.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:20:46.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:20:46.08#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.00:20:46.08#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.00:20:46.08$setupk4/ifdk4 2006.286.00:20:46.08$ifdk4/lo= 2006.286.00:20:46.08$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.00:20:46.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.00:20:46.09$ifdk4/patch= 2006.286.00:20:46.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.00:20:46.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.00:20:46.09$setupk4/!*+20s 2006.286.00:20:53.51#abcon#<5=/03 3.1 7.0 19.85 851016.4\r\n> 2006.286.00:20:53.53#abcon#{5=INTERFACE CLEAR} 2006.286.00:20:53.59#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:21:00.60$setupk4/"tpicd 2006.286.00:21:00.60$setupk4/echo=off 2006.286.00:21:00.60$setupk4/xlog=off 2006.286.00:21:00.60:!2006.286.00:23:18 2006.286.00:21:03.14#trakl#Source acquired 2006.286.00:21:05.14#flagr#flagr/antenna,acquired 2006.286.00:23:18.00:preob 2006.286.00:23:18.14/onsource/TRACKING 2006.286.00:23:18.14:!2006.286.00:23:28 2006.286.00:23:28.00:"tape 2006.286.00:23:28.00:"st=record 2006.286.00:23:28.00:data_valid=on 2006.286.00:23:28.00:midob 2006.286.00:23:29.14/onsource/TRACKING 2006.286.00:23:29.14/wx/19.86,1016.4,86 2006.286.00:23:29.30/cable/+6.5069E-03 2006.286.00:23:30.39/va/01,07,usb,yes,34,37 2006.286.00:23:30.39/va/02,06,usb,yes,34,34 2006.286.00:23:30.39/va/03,07,usb,yes,34,35 2006.286.00:23:30.39/va/04,06,usb,yes,35,37 2006.286.00:23:30.39/va/05,03,usb,yes,35,35 2006.286.00:23:30.39/va/06,04,usb,yes,31,31 2006.286.00:23:30.39/va/07,04,usb,yes,32,33 2006.286.00:23:30.39/va/08,03,usb,yes,32,40 2006.286.00:23:30.62/valo/01,524.99,yes,locked 2006.286.00:23:30.62/valo/02,534.99,yes,locked 2006.286.00:23:30.62/valo/03,564.99,yes,locked 2006.286.00:23:30.62/valo/04,624.99,yes,locked 2006.286.00:23:30.62/valo/05,734.99,yes,locked 2006.286.00:23:30.62/valo/06,814.99,yes,locked 2006.286.00:23:30.62/valo/07,864.99,yes,locked 2006.286.00:23:30.62/valo/08,884.99,yes,locked 2006.286.00:23:31.71/vb/01,04,usb,yes,32,29 2006.286.00:23:31.71/vb/02,05,usb,yes,30,30 2006.286.00:23:31.71/vb/03,04,usb,yes,31,34 2006.286.00:23:31.71/vb/04,05,usb,yes,31,30 2006.286.00:23:31.71/vb/05,04,usb,yes,27,30 2006.286.00:23:31.71/vb/06,03,usb,yes,39,35 2006.286.00:23:31.71/vb/07,04,usb,yes,32,32 2006.286.00:23:31.71/vb/08,04,usb,yes,29,33 2006.286.00:23:31.94/vblo/01,629.99,yes,locked 2006.286.00:23:31.94/vblo/02,634.99,yes,locked 2006.286.00:23:31.94/vblo/03,649.99,yes,locked 2006.286.00:23:31.94/vblo/04,679.99,yes,locked 2006.286.00:23:31.94/vblo/05,709.99,yes,locked 2006.286.00:23:31.94/vblo/06,719.99,yes,locked 2006.286.00:23:31.94/vblo/07,734.99,yes,locked 2006.286.00:23:31.94/vblo/08,744.99,yes,locked 2006.286.00:23:32.09/vabw/8 2006.286.00:23:32.24/vbbw/8 2006.286.00:23:32.33/xfe/off,on,12.0 2006.286.00:23:32.71/ifatt/23,28,28,28 2006.286.00:23:33.07/fmout-gps/S +2.68E-07 2006.286.00:23:33.09:!2006.286.00:24:38 2006.286.00:24:38.00:data_valid=off 2006.286.00:24:38.00:"et 2006.286.00:24:38.00:!+3s 2006.286.00:24:41.01:"tape 2006.286.00:24:41.01:postob 2006.286.00:24:41.14/cable/+6.5070E-03 2006.286.00:24:41.14/wx/19.87,1016.4,85 2006.286.00:24:42.07/fmout-gps/S +2.69E-07 2006.286.00:24:42.07:scan_name=286-0027,jd0610,150 2006.286.00:24:42.07:source=0528+134,053056.42,133155.1,2000.0,cw 2006.286.00:24:43.13#flagr#flagr/antenna,new-source 2006.286.00:24:43.13:checkk5 2006.286.00:24:43.54/chk_autoobs//k5ts1/ autoobs is running! 2006.286.00:24:43.93/chk_autoobs//k5ts2/ autoobs is running! 2006.286.00:24:44.31/chk_autoobs//k5ts3/ autoobs is running! 2006.286.00:24:44.73/chk_autoobs//k5ts4/ autoobs is running! 2006.286.00:24:45.10/chk_obsdata//k5ts1/T2860023??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.286.00:24:45.51/chk_obsdata//k5ts2/T2860023??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.286.00:24:45.87/chk_obsdata//k5ts3/T2860023??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.286.00:24:46.49/chk_obsdata//k5ts4/T2860023??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.286.00:24:47.30/k5log//k5ts1_log_newline 2006.286.00:24:48.26/k5log//k5ts2_log_newline 2006.286.00:24:48.98/k5log//k5ts3_log_newline 2006.286.00:24:49.81/k5log//k5ts4_log_newline 2006.286.00:24:49.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.00:24:49.83:setupk4=1 2006.286.00:24:49.83$setupk4/echo=on 2006.286.00:24:49.83$setupk4/pcalon 2006.286.00:24:49.83$pcalon/"no phase cal control is implemented here 2006.286.00:24:49.83$setupk4/"tpicd=stop 2006.286.00:24:49.83$setupk4/"rec=synch_on 2006.286.00:24:49.83$setupk4/"rec_mode=128 2006.286.00:24:49.83$setupk4/!* 2006.286.00:24:49.83$setupk4/recpk4 2006.286.00:24:49.83$recpk4/recpatch= 2006.286.00:24:49.83$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.00:24:49.83$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.00:24:49.83$setupk4/vck44 2006.286.00:24:49.83$vck44/valo=1,524.99 2006.286.00:24:49.83#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.00:24:49.83#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.00:24:49.83#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:49.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:24:49.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:24:49.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:24:49.83#ibcon#enter wrdev, iclass 21, count 0 2006.286.00:24:49.83#ibcon#first serial, iclass 21, count 0 2006.286.00:24:49.83#ibcon#enter sib2, iclass 21, count 0 2006.286.00:24:49.83#ibcon#flushed, iclass 21, count 0 2006.286.00:24:49.83#ibcon#about to write, iclass 21, count 0 2006.286.00:24:49.83#ibcon#wrote, iclass 21, count 0 2006.286.00:24:49.83#ibcon#about to read 3, iclass 21, count 0 2006.286.00:24:49.85#ibcon#read 3, iclass 21, count 0 2006.286.00:24:49.85#ibcon#about to read 4, iclass 21, count 0 2006.286.00:24:49.85#ibcon#read 4, iclass 21, count 0 2006.286.00:24:49.85#ibcon#about to read 5, iclass 21, count 0 2006.286.00:24:49.85#ibcon#read 5, iclass 21, count 0 2006.286.00:24:49.85#ibcon#about to read 6, iclass 21, count 0 2006.286.00:24:49.85#ibcon#read 6, iclass 21, count 0 2006.286.00:24:49.85#ibcon#end of sib2, iclass 21, count 0 2006.286.00:24:49.85#ibcon#*mode == 0, iclass 21, count 0 2006.286.00:24:49.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.00:24:49.85#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.00:24:49.85#ibcon#*before write, iclass 21, count 0 2006.286.00:24:49.85#ibcon#enter sib2, iclass 21, count 0 2006.286.00:24:49.85#ibcon#flushed, iclass 21, count 0 2006.286.00:24:49.85#ibcon#about to write, iclass 21, count 0 2006.286.00:24:49.85#ibcon#wrote, iclass 21, count 0 2006.286.00:24:49.85#ibcon#about to read 3, iclass 21, count 0 2006.286.00:24:49.90#ibcon#read 3, iclass 21, count 0 2006.286.00:24:49.90#ibcon#about to read 4, iclass 21, count 0 2006.286.00:24:49.90#ibcon#read 4, iclass 21, count 0 2006.286.00:24:49.90#ibcon#about to read 5, iclass 21, count 0 2006.286.00:24:49.90#ibcon#read 5, iclass 21, count 0 2006.286.00:24:49.90#ibcon#about to read 6, iclass 21, count 0 2006.286.00:24:49.90#ibcon#read 6, iclass 21, count 0 2006.286.00:24:49.90#ibcon#end of sib2, iclass 21, count 0 2006.286.00:24:49.90#ibcon#*after write, iclass 21, count 0 2006.286.00:24:49.90#ibcon#*before return 0, iclass 21, count 0 2006.286.00:24:49.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:24:49.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:24:49.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.00:24:49.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.00:24:49.90$vck44/va=1,7 2006.286.00:24:49.90#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.00:24:49.90#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.00:24:49.90#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:49.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:24:49.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:24:49.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:24:49.90#ibcon#enter wrdev, iclass 23, count 2 2006.286.00:24:49.90#ibcon#first serial, iclass 23, count 2 2006.286.00:24:49.90#ibcon#enter sib2, iclass 23, count 2 2006.286.00:24:49.90#ibcon#flushed, iclass 23, count 2 2006.286.00:24:49.90#ibcon#about to write, iclass 23, count 2 2006.286.00:24:49.90#ibcon#wrote, iclass 23, count 2 2006.286.00:24:49.90#ibcon#about to read 3, iclass 23, count 2 2006.286.00:24:49.92#ibcon#read 3, iclass 23, count 2 2006.286.00:24:49.92#ibcon#about to read 4, iclass 23, count 2 2006.286.00:24:49.92#ibcon#read 4, iclass 23, count 2 2006.286.00:24:49.92#ibcon#about to read 5, iclass 23, count 2 2006.286.00:24:49.92#ibcon#read 5, iclass 23, count 2 2006.286.00:24:49.92#ibcon#about to read 6, iclass 23, count 2 2006.286.00:24:49.92#ibcon#read 6, iclass 23, count 2 2006.286.00:24:49.92#ibcon#end of sib2, iclass 23, count 2 2006.286.00:24:49.92#ibcon#*mode == 0, iclass 23, count 2 2006.286.00:24:49.92#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.00:24:49.92#ibcon#[25=AT01-07\r\n] 2006.286.00:24:49.92#ibcon#*before write, iclass 23, count 2 2006.286.00:24:49.92#ibcon#enter sib2, iclass 23, count 2 2006.286.00:24:49.92#ibcon#flushed, iclass 23, count 2 2006.286.00:24:49.92#ibcon#about to write, iclass 23, count 2 2006.286.00:24:49.92#ibcon#wrote, iclass 23, count 2 2006.286.00:24:49.92#ibcon#about to read 3, iclass 23, count 2 2006.286.00:24:49.95#ibcon#read 3, iclass 23, count 2 2006.286.00:24:49.95#ibcon#about to read 4, iclass 23, count 2 2006.286.00:24:49.95#ibcon#read 4, iclass 23, count 2 2006.286.00:24:49.95#ibcon#about to read 5, iclass 23, count 2 2006.286.00:24:49.95#ibcon#read 5, iclass 23, count 2 2006.286.00:24:49.95#ibcon#about to read 6, iclass 23, count 2 2006.286.00:24:49.95#ibcon#read 6, iclass 23, count 2 2006.286.00:24:49.95#ibcon#end of sib2, iclass 23, count 2 2006.286.00:24:49.95#ibcon#*after write, iclass 23, count 2 2006.286.00:24:49.95#ibcon#*before return 0, iclass 23, count 2 2006.286.00:24:49.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:24:49.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:24:49.95#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.00:24:49.95#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:49.95#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:24:50.07#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:24:50.07#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:24:50.07#ibcon#enter wrdev, iclass 23, count 0 2006.286.00:24:50.07#ibcon#first serial, iclass 23, count 0 2006.286.00:24:50.07#ibcon#enter sib2, iclass 23, count 0 2006.286.00:24:50.07#ibcon#flushed, iclass 23, count 0 2006.286.00:24:50.07#ibcon#about to write, iclass 23, count 0 2006.286.00:24:50.07#ibcon#wrote, iclass 23, count 0 2006.286.00:24:50.07#ibcon#about to read 3, iclass 23, count 0 2006.286.00:24:50.09#ibcon#read 3, iclass 23, count 0 2006.286.00:24:50.09#ibcon#about to read 4, iclass 23, count 0 2006.286.00:24:50.09#ibcon#read 4, iclass 23, count 0 2006.286.00:24:50.09#ibcon#about to read 5, iclass 23, count 0 2006.286.00:24:50.09#ibcon#read 5, iclass 23, count 0 2006.286.00:24:50.09#ibcon#about to read 6, iclass 23, count 0 2006.286.00:24:50.09#ibcon#read 6, iclass 23, count 0 2006.286.00:24:50.09#ibcon#end of sib2, iclass 23, count 0 2006.286.00:24:50.09#ibcon#*mode == 0, iclass 23, count 0 2006.286.00:24:50.09#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.00:24:50.09#ibcon#[25=USB\r\n] 2006.286.00:24:50.09#ibcon#*before write, iclass 23, count 0 2006.286.00:24:50.09#ibcon#enter sib2, iclass 23, count 0 2006.286.00:24:50.09#ibcon#flushed, iclass 23, count 0 2006.286.00:24:50.09#ibcon#about to write, iclass 23, count 0 2006.286.00:24:50.09#ibcon#wrote, iclass 23, count 0 2006.286.00:24:50.09#ibcon#about to read 3, iclass 23, count 0 2006.286.00:24:50.12#ibcon#read 3, iclass 23, count 0 2006.286.00:24:50.12#ibcon#about to read 4, iclass 23, count 0 2006.286.00:24:50.12#ibcon#read 4, iclass 23, count 0 2006.286.00:24:50.12#ibcon#about to read 5, iclass 23, count 0 2006.286.00:24:50.12#ibcon#read 5, iclass 23, count 0 2006.286.00:24:50.12#ibcon#about to read 6, iclass 23, count 0 2006.286.00:24:50.12#ibcon#read 6, iclass 23, count 0 2006.286.00:24:50.12#ibcon#end of sib2, iclass 23, count 0 2006.286.00:24:50.12#ibcon#*after write, iclass 23, count 0 2006.286.00:24:50.12#ibcon#*before return 0, iclass 23, count 0 2006.286.00:24:50.12#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:24:50.12#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:24:50.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.00:24:50.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.00:24:50.12$vck44/valo=2,534.99 2006.286.00:24:50.12#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.00:24:50.12#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.00:24:50.12#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:50.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:24:50.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:24:50.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:24:50.12#ibcon#enter wrdev, iclass 25, count 0 2006.286.00:24:50.12#ibcon#first serial, iclass 25, count 0 2006.286.00:24:50.12#ibcon#enter sib2, iclass 25, count 0 2006.286.00:24:50.12#ibcon#flushed, iclass 25, count 0 2006.286.00:24:50.12#ibcon#about to write, iclass 25, count 0 2006.286.00:24:50.12#ibcon#wrote, iclass 25, count 0 2006.286.00:24:50.12#ibcon#about to read 3, iclass 25, count 0 2006.286.00:24:50.14#ibcon#read 3, iclass 25, count 0 2006.286.00:24:50.14#ibcon#about to read 4, iclass 25, count 0 2006.286.00:24:50.14#ibcon#read 4, iclass 25, count 0 2006.286.00:24:50.14#ibcon#about to read 5, iclass 25, count 0 2006.286.00:24:50.14#ibcon#read 5, iclass 25, count 0 2006.286.00:24:50.14#ibcon#about to read 6, iclass 25, count 0 2006.286.00:24:50.14#ibcon#read 6, iclass 25, count 0 2006.286.00:24:50.14#ibcon#end of sib2, iclass 25, count 0 2006.286.00:24:50.14#ibcon#*mode == 0, iclass 25, count 0 2006.286.00:24:50.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.00:24:50.14#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.00:24:50.14#ibcon#*before write, iclass 25, count 0 2006.286.00:24:50.14#ibcon#enter sib2, iclass 25, count 0 2006.286.00:24:50.14#ibcon#flushed, iclass 25, count 0 2006.286.00:24:50.14#ibcon#about to write, iclass 25, count 0 2006.286.00:24:50.14#ibcon#wrote, iclass 25, count 0 2006.286.00:24:50.14#ibcon#about to read 3, iclass 25, count 0 2006.286.00:24:50.18#ibcon#read 3, iclass 25, count 0 2006.286.00:24:50.18#ibcon#about to read 4, iclass 25, count 0 2006.286.00:24:50.18#ibcon#read 4, iclass 25, count 0 2006.286.00:24:50.18#ibcon#about to read 5, iclass 25, count 0 2006.286.00:24:50.18#ibcon#read 5, iclass 25, count 0 2006.286.00:24:50.18#ibcon#about to read 6, iclass 25, count 0 2006.286.00:24:50.18#ibcon#read 6, iclass 25, count 0 2006.286.00:24:50.18#ibcon#end of sib2, iclass 25, count 0 2006.286.00:24:50.18#ibcon#*after write, iclass 25, count 0 2006.286.00:24:50.18#ibcon#*before return 0, iclass 25, count 0 2006.286.00:24:50.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:24:50.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:24:50.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.00:24:50.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.00:24:50.18$vck44/va=2,6 2006.286.00:24:50.18#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.00:24:50.18#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.00:24:50.18#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:50.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:24:50.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:24:50.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:24:50.24#ibcon#enter wrdev, iclass 27, count 2 2006.286.00:24:50.24#ibcon#first serial, iclass 27, count 2 2006.286.00:24:50.24#ibcon#enter sib2, iclass 27, count 2 2006.286.00:24:50.24#ibcon#flushed, iclass 27, count 2 2006.286.00:24:50.24#ibcon#about to write, iclass 27, count 2 2006.286.00:24:50.24#ibcon#wrote, iclass 27, count 2 2006.286.00:24:50.24#ibcon#about to read 3, iclass 27, count 2 2006.286.00:24:50.26#ibcon#read 3, iclass 27, count 2 2006.286.00:24:50.26#ibcon#about to read 4, iclass 27, count 2 2006.286.00:24:50.26#ibcon#read 4, iclass 27, count 2 2006.286.00:24:50.26#ibcon#about to read 5, iclass 27, count 2 2006.286.00:24:50.26#ibcon#read 5, iclass 27, count 2 2006.286.00:24:50.26#ibcon#about to read 6, iclass 27, count 2 2006.286.00:24:50.26#ibcon#read 6, iclass 27, count 2 2006.286.00:24:50.26#ibcon#end of sib2, iclass 27, count 2 2006.286.00:24:50.26#ibcon#*mode == 0, iclass 27, count 2 2006.286.00:24:50.26#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.00:24:50.26#ibcon#[25=AT02-06\r\n] 2006.286.00:24:50.26#ibcon#*before write, iclass 27, count 2 2006.286.00:24:50.26#ibcon#enter sib2, iclass 27, count 2 2006.286.00:24:50.26#ibcon#flushed, iclass 27, count 2 2006.286.00:24:50.26#ibcon#about to write, iclass 27, count 2 2006.286.00:24:50.26#ibcon#wrote, iclass 27, count 2 2006.286.00:24:50.26#ibcon#about to read 3, iclass 27, count 2 2006.286.00:24:50.29#ibcon#read 3, iclass 27, count 2 2006.286.00:24:50.29#ibcon#about to read 4, iclass 27, count 2 2006.286.00:24:50.29#ibcon#read 4, iclass 27, count 2 2006.286.00:24:50.29#ibcon#about to read 5, iclass 27, count 2 2006.286.00:24:50.29#ibcon#read 5, iclass 27, count 2 2006.286.00:24:50.29#ibcon#about to read 6, iclass 27, count 2 2006.286.00:24:50.29#ibcon#read 6, iclass 27, count 2 2006.286.00:24:50.29#ibcon#end of sib2, iclass 27, count 2 2006.286.00:24:50.29#ibcon#*after write, iclass 27, count 2 2006.286.00:24:50.29#ibcon#*before return 0, iclass 27, count 2 2006.286.00:24:50.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:24:50.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:24:50.29#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.00:24:50.29#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:50.29#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:24:50.41#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:24:50.41#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:24:50.41#ibcon#enter wrdev, iclass 27, count 0 2006.286.00:24:50.41#ibcon#first serial, iclass 27, count 0 2006.286.00:24:50.41#ibcon#enter sib2, iclass 27, count 0 2006.286.00:24:50.41#ibcon#flushed, iclass 27, count 0 2006.286.00:24:50.41#ibcon#about to write, iclass 27, count 0 2006.286.00:24:50.41#ibcon#wrote, iclass 27, count 0 2006.286.00:24:50.41#ibcon#about to read 3, iclass 27, count 0 2006.286.00:24:50.43#ibcon#read 3, iclass 27, count 0 2006.286.00:24:50.43#ibcon#about to read 4, iclass 27, count 0 2006.286.00:24:50.43#ibcon#read 4, iclass 27, count 0 2006.286.00:24:50.43#ibcon#about to read 5, iclass 27, count 0 2006.286.00:24:50.43#ibcon#read 5, iclass 27, count 0 2006.286.00:24:50.43#ibcon#about to read 6, iclass 27, count 0 2006.286.00:24:50.43#ibcon#read 6, iclass 27, count 0 2006.286.00:24:50.43#ibcon#end of sib2, iclass 27, count 0 2006.286.00:24:50.43#ibcon#*mode == 0, iclass 27, count 0 2006.286.00:24:50.43#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.00:24:50.43#ibcon#[25=USB\r\n] 2006.286.00:24:50.43#ibcon#*before write, iclass 27, count 0 2006.286.00:24:50.43#ibcon#enter sib2, iclass 27, count 0 2006.286.00:24:50.43#ibcon#flushed, iclass 27, count 0 2006.286.00:24:50.43#ibcon#about to write, iclass 27, count 0 2006.286.00:24:50.43#ibcon#wrote, iclass 27, count 0 2006.286.00:24:50.43#ibcon#about to read 3, iclass 27, count 0 2006.286.00:24:50.46#ibcon#read 3, iclass 27, count 0 2006.286.00:24:50.46#ibcon#about to read 4, iclass 27, count 0 2006.286.00:24:50.46#ibcon#read 4, iclass 27, count 0 2006.286.00:24:50.46#ibcon#about to read 5, iclass 27, count 0 2006.286.00:24:50.46#ibcon#read 5, iclass 27, count 0 2006.286.00:24:50.46#ibcon#about to read 6, iclass 27, count 0 2006.286.00:24:50.46#ibcon#read 6, iclass 27, count 0 2006.286.00:24:50.46#ibcon#end of sib2, iclass 27, count 0 2006.286.00:24:50.46#ibcon#*after write, iclass 27, count 0 2006.286.00:24:50.46#ibcon#*before return 0, iclass 27, count 0 2006.286.00:24:50.46#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:24:50.46#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:24:50.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.00:24:50.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.00:24:50.46$vck44/valo=3,564.99 2006.286.00:24:50.46#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.00:24:50.46#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.00:24:50.46#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:50.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:24:50.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:24:50.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:24:50.46#ibcon#enter wrdev, iclass 29, count 0 2006.286.00:24:50.46#ibcon#first serial, iclass 29, count 0 2006.286.00:24:50.46#ibcon#enter sib2, iclass 29, count 0 2006.286.00:24:50.46#ibcon#flushed, iclass 29, count 0 2006.286.00:24:50.46#ibcon#about to write, iclass 29, count 0 2006.286.00:24:50.46#ibcon#wrote, iclass 29, count 0 2006.286.00:24:50.46#ibcon#about to read 3, iclass 29, count 0 2006.286.00:24:50.48#ibcon#read 3, iclass 29, count 0 2006.286.00:24:50.48#ibcon#about to read 4, iclass 29, count 0 2006.286.00:24:50.48#ibcon#read 4, iclass 29, count 0 2006.286.00:24:50.48#ibcon#about to read 5, iclass 29, count 0 2006.286.00:24:50.48#ibcon#read 5, iclass 29, count 0 2006.286.00:24:50.48#ibcon#about to read 6, iclass 29, count 0 2006.286.00:24:50.48#ibcon#read 6, iclass 29, count 0 2006.286.00:24:50.48#ibcon#end of sib2, iclass 29, count 0 2006.286.00:24:50.48#ibcon#*mode == 0, iclass 29, count 0 2006.286.00:24:50.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.00:24:50.48#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.00:24:50.48#ibcon#*before write, iclass 29, count 0 2006.286.00:24:50.48#ibcon#enter sib2, iclass 29, count 0 2006.286.00:24:50.48#ibcon#flushed, iclass 29, count 0 2006.286.00:24:50.48#ibcon#about to write, iclass 29, count 0 2006.286.00:24:50.48#ibcon#wrote, iclass 29, count 0 2006.286.00:24:50.48#ibcon#about to read 3, iclass 29, count 0 2006.286.00:24:50.52#ibcon#read 3, iclass 29, count 0 2006.286.00:24:50.52#ibcon#about to read 4, iclass 29, count 0 2006.286.00:24:50.52#ibcon#read 4, iclass 29, count 0 2006.286.00:24:50.52#ibcon#about to read 5, iclass 29, count 0 2006.286.00:24:50.52#ibcon#read 5, iclass 29, count 0 2006.286.00:24:50.52#ibcon#about to read 6, iclass 29, count 0 2006.286.00:24:50.52#ibcon#read 6, iclass 29, count 0 2006.286.00:24:50.52#ibcon#end of sib2, iclass 29, count 0 2006.286.00:24:50.52#ibcon#*after write, iclass 29, count 0 2006.286.00:24:50.52#ibcon#*before return 0, iclass 29, count 0 2006.286.00:24:50.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:24:50.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:24:50.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.00:24:50.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.00:24:50.52$vck44/va=3,7 2006.286.00:24:50.52#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.00:24:50.52#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.00:24:50.52#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:50.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:24:50.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:24:50.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:24:50.58#ibcon#enter wrdev, iclass 31, count 2 2006.286.00:24:50.58#ibcon#first serial, iclass 31, count 2 2006.286.00:24:50.58#ibcon#enter sib2, iclass 31, count 2 2006.286.00:24:50.58#ibcon#flushed, iclass 31, count 2 2006.286.00:24:50.58#ibcon#about to write, iclass 31, count 2 2006.286.00:24:50.58#ibcon#wrote, iclass 31, count 2 2006.286.00:24:50.58#ibcon#about to read 3, iclass 31, count 2 2006.286.00:24:50.60#ibcon#read 3, iclass 31, count 2 2006.286.00:24:50.60#ibcon#about to read 4, iclass 31, count 2 2006.286.00:24:50.60#ibcon#read 4, iclass 31, count 2 2006.286.00:24:50.60#ibcon#about to read 5, iclass 31, count 2 2006.286.00:24:50.60#ibcon#read 5, iclass 31, count 2 2006.286.00:24:50.60#ibcon#about to read 6, iclass 31, count 2 2006.286.00:24:50.60#ibcon#read 6, iclass 31, count 2 2006.286.00:24:50.60#ibcon#end of sib2, iclass 31, count 2 2006.286.00:24:50.60#ibcon#*mode == 0, iclass 31, count 2 2006.286.00:24:50.60#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.00:24:50.60#ibcon#[25=AT03-07\r\n] 2006.286.00:24:50.60#ibcon#*before write, iclass 31, count 2 2006.286.00:24:50.60#ibcon#enter sib2, iclass 31, count 2 2006.286.00:24:50.60#ibcon#flushed, iclass 31, count 2 2006.286.00:24:50.60#ibcon#about to write, iclass 31, count 2 2006.286.00:24:50.60#ibcon#wrote, iclass 31, count 2 2006.286.00:24:50.60#ibcon#about to read 3, iclass 31, count 2 2006.286.00:24:50.63#ibcon#read 3, iclass 31, count 2 2006.286.00:24:50.63#ibcon#about to read 4, iclass 31, count 2 2006.286.00:24:50.63#ibcon#read 4, iclass 31, count 2 2006.286.00:24:50.63#ibcon#about to read 5, iclass 31, count 2 2006.286.00:24:50.63#ibcon#read 5, iclass 31, count 2 2006.286.00:24:50.63#ibcon#about to read 6, iclass 31, count 2 2006.286.00:24:50.63#ibcon#read 6, iclass 31, count 2 2006.286.00:24:50.63#ibcon#end of sib2, iclass 31, count 2 2006.286.00:24:50.63#ibcon#*after write, iclass 31, count 2 2006.286.00:24:50.63#ibcon#*before return 0, iclass 31, count 2 2006.286.00:24:50.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:24:50.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:24:50.63#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.00:24:50.63#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:50.63#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:24:50.75#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:24:50.75#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:24:50.75#ibcon#enter wrdev, iclass 31, count 0 2006.286.00:24:50.75#ibcon#first serial, iclass 31, count 0 2006.286.00:24:50.75#ibcon#enter sib2, iclass 31, count 0 2006.286.00:24:50.75#ibcon#flushed, iclass 31, count 0 2006.286.00:24:50.75#ibcon#about to write, iclass 31, count 0 2006.286.00:24:50.75#ibcon#wrote, iclass 31, count 0 2006.286.00:24:50.75#ibcon#about to read 3, iclass 31, count 0 2006.286.00:24:50.77#ibcon#read 3, iclass 31, count 0 2006.286.00:24:50.77#ibcon#about to read 4, iclass 31, count 0 2006.286.00:24:50.77#ibcon#read 4, iclass 31, count 0 2006.286.00:24:50.77#ibcon#about to read 5, iclass 31, count 0 2006.286.00:24:50.77#ibcon#read 5, iclass 31, count 0 2006.286.00:24:50.77#ibcon#about to read 6, iclass 31, count 0 2006.286.00:24:50.77#ibcon#read 6, iclass 31, count 0 2006.286.00:24:50.77#ibcon#end of sib2, iclass 31, count 0 2006.286.00:24:50.77#ibcon#*mode == 0, iclass 31, count 0 2006.286.00:24:50.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.00:24:50.77#ibcon#[25=USB\r\n] 2006.286.00:24:50.77#ibcon#*before write, iclass 31, count 0 2006.286.00:24:50.77#ibcon#enter sib2, iclass 31, count 0 2006.286.00:24:50.77#ibcon#flushed, iclass 31, count 0 2006.286.00:24:50.77#ibcon#about to write, iclass 31, count 0 2006.286.00:24:50.77#ibcon#wrote, iclass 31, count 0 2006.286.00:24:50.77#ibcon#about to read 3, iclass 31, count 0 2006.286.00:24:50.80#ibcon#read 3, iclass 31, count 0 2006.286.00:24:50.80#ibcon#about to read 4, iclass 31, count 0 2006.286.00:24:50.80#ibcon#read 4, iclass 31, count 0 2006.286.00:24:50.80#ibcon#about to read 5, iclass 31, count 0 2006.286.00:24:50.80#ibcon#read 5, iclass 31, count 0 2006.286.00:24:50.80#ibcon#about to read 6, iclass 31, count 0 2006.286.00:24:50.80#ibcon#read 6, iclass 31, count 0 2006.286.00:24:50.80#ibcon#end of sib2, iclass 31, count 0 2006.286.00:24:50.80#ibcon#*after write, iclass 31, count 0 2006.286.00:24:50.80#ibcon#*before return 0, iclass 31, count 0 2006.286.00:24:50.80#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:24:50.80#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:24:50.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.00:24:50.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.00:24:50.80$vck44/valo=4,624.99 2006.286.00:24:50.80#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.00:24:50.80#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.00:24:50.80#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:50.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:24:50.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:24:50.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:24:50.80#ibcon#enter wrdev, iclass 33, count 0 2006.286.00:24:50.80#ibcon#first serial, iclass 33, count 0 2006.286.00:24:50.80#ibcon#enter sib2, iclass 33, count 0 2006.286.00:24:50.80#ibcon#flushed, iclass 33, count 0 2006.286.00:24:50.80#ibcon#about to write, iclass 33, count 0 2006.286.00:24:50.80#ibcon#wrote, iclass 33, count 0 2006.286.00:24:50.80#ibcon#about to read 3, iclass 33, count 0 2006.286.00:24:50.82#ibcon#read 3, iclass 33, count 0 2006.286.00:24:50.82#ibcon#about to read 4, iclass 33, count 0 2006.286.00:24:50.82#ibcon#read 4, iclass 33, count 0 2006.286.00:24:50.82#ibcon#about to read 5, iclass 33, count 0 2006.286.00:24:50.82#ibcon#read 5, iclass 33, count 0 2006.286.00:24:50.82#ibcon#about to read 6, iclass 33, count 0 2006.286.00:24:50.82#ibcon#read 6, iclass 33, count 0 2006.286.00:24:50.82#ibcon#end of sib2, iclass 33, count 0 2006.286.00:24:50.82#ibcon#*mode == 0, iclass 33, count 0 2006.286.00:24:50.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.00:24:50.82#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.00:24:50.82#ibcon#*before write, iclass 33, count 0 2006.286.00:24:50.82#ibcon#enter sib2, iclass 33, count 0 2006.286.00:24:50.82#ibcon#flushed, iclass 33, count 0 2006.286.00:24:50.82#ibcon#about to write, iclass 33, count 0 2006.286.00:24:50.82#ibcon#wrote, iclass 33, count 0 2006.286.00:24:50.82#ibcon#about to read 3, iclass 33, count 0 2006.286.00:24:50.86#ibcon#read 3, iclass 33, count 0 2006.286.00:24:50.86#ibcon#about to read 4, iclass 33, count 0 2006.286.00:24:50.86#ibcon#read 4, iclass 33, count 0 2006.286.00:24:50.86#ibcon#about to read 5, iclass 33, count 0 2006.286.00:24:50.86#ibcon#read 5, iclass 33, count 0 2006.286.00:24:50.86#ibcon#about to read 6, iclass 33, count 0 2006.286.00:24:50.86#ibcon#read 6, iclass 33, count 0 2006.286.00:24:50.86#ibcon#end of sib2, iclass 33, count 0 2006.286.00:24:50.86#ibcon#*after write, iclass 33, count 0 2006.286.00:24:50.86#ibcon#*before return 0, iclass 33, count 0 2006.286.00:24:50.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:24:50.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:24:50.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.00:24:50.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.00:24:50.86$vck44/va=4,6 2006.286.00:24:50.86#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.00:24:50.86#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.00:24:50.86#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:50.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:24:50.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:24:50.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:24:50.92#ibcon#enter wrdev, iclass 35, count 2 2006.286.00:24:50.92#ibcon#first serial, iclass 35, count 2 2006.286.00:24:50.92#ibcon#enter sib2, iclass 35, count 2 2006.286.00:24:50.92#ibcon#flushed, iclass 35, count 2 2006.286.00:24:50.92#ibcon#about to write, iclass 35, count 2 2006.286.00:24:50.92#ibcon#wrote, iclass 35, count 2 2006.286.00:24:50.92#ibcon#about to read 3, iclass 35, count 2 2006.286.00:24:50.94#ibcon#read 3, iclass 35, count 2 2006.286.00:24:50.94#ibcon#about to read 4, iclass 35, count 2 2006.286.00:24:50.94#ibcon#read 4, iclass 35, count 2 2006.286.00:24:50.94#ibcon#about to read 5, iclass 35, count 2 2006.286.00:24:50.94#ibcon#read 5, iclass 35, count 2 2006.286.00:24:50.94#ibcon#about to read 6, iclass 35, count 2 2006.286.00:24:50.94#ibcon#read 6, iclass 35, count 2 2006.286.00:24:50.94#ibcon#end of sib2, iclass 35, count 2 2006.286.00:24:50.94#ibcon#*mode == 0, iclass 35, count 2 2006.286.00:24:50.94#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.00:24:50.94#ibcon#[25=AT04-06\r\n] 2006.286.00:24:50.94#ibcon#*before write, iclass 35, count 2 2006.286.00:24:50.94#ibcon#enter sib2, iclass 35, count 2 2006.286.00:24:50.94#ibcon#flushed, iclass 35, count 2 2006.286.00:24:50.94#ibcon#about to write, iclass 35, count 2 2006.286.00:24:50.94#ibcon#wrote, iclass 35, count 2 2006.286.00:24:50.94#ibcon#about to read 3, iclass 35, count 2 2006.286.00:24:50.97#ibcon#read 3, iclass 35, count 2 2006.286.00:24:50.97#ibcon#about to read 4, iclass 35, count 2 2006.286.00:24:50.97#ibcon#read 4, iclass 35, count 2 2006.286.00:24:50.97#ibcon#about to read 5, iclass 35, count 2 2006.286.00:24:50.97#ibcon#read 5, iclass 35, count 2 2006.286.00:24:50.97#ibcon#about to read 6, iclass 35, count 2 2006.286.00:24:50.97#ibcon#read 6, iclass 35, count 2 2006.286.00:24:50.97#ibcon#end of sib2, iclass 35, count 2 2006.286.00:24:50.97#ibcon#*after write, iclass 35, count 2 2006.286.00:24:50.97#ibcon#*before return 0, iclass 35, count 2 2006.286.00:24:50.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:24:50.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:24:50.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.00:24:50.97#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:50.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:24:51.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:24:51.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:24:51.09#ibcon#enter wrdev, iclass 35, count 0 2006.286.00:24:51.09#ibcon#first serial, iclass 35, count 0 2006.286.00:24:51.09#ibcon#enter sib2, iclass 35, count 0 2006.286.00:24:51.09#ibcon#flushed, iclass 35, count 0 2006.286.00:24:51.09#ibcon#about to write, iclass 35, count 0 2006.286.00:24:51.09#ibcon#wrote, iclass 35, count 0 2006.286.00:24:51.09#ibcon#about to read 3, iclass 35, count 0 2006.286.00:24:51.11#ibcon#read 3, iclass 35, count 0 2006.286.00:24:51.11#ibcon#about to read 4, iclass 35, count 0 2006.286.00:24:51.11#ibcon#read 4, iclass 35, count 0 2006.286.00:24:51.11#ibcon#about to read 5, iclass 35, count 0 2006.286.00:24:51.11#ibcon#read 5, iclass 35, count 0 2006.286.00:24:51.11#ibcon#about to read 6, iclass 35, count 0 2006.286.00:24:51.11#ibcon#read 6, iclass 35, count 0 2006.286.00:24:51.11#ibcon#end of sib2, iclass 35, count 0 2006.286.00:24:51.11#ibcon#*mode == 0, iclass 35, count 0 2006.286.00:24:51.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.00:24:51.11#ibcon#[25=USB\r\n] 2006.286.00:24:51.11#ibcon#*before write, iclass 35, count 0 2006.286.00:24:51.11#ibcon#enter sib2, iclass 35, count 0 2006.286.00:24:51.11#ibcon#flushed, iclass 35, count 0 2006.286.00:24:51.11#ibcon#about to write, iclass 35, count 0 2006.286.00:24:51.11#ibcon#wrote, iclass 35, count 0 2006.286.00:24:51.11#ibcon#about to read 3, iclass 35, count 0 2006.286.00:24:51.14#ibcon#read 3, iclass 35, count 0 2006.286.00:24:51.14#ibcon#about to read 4, iclass 35, count 0 2006.286.00:24:51.14#ibcon#read 4, iclass 35, count 0 2006.286.00:24:51.14#ibcon#about to read 5, iclass 35, count 0 2006.286.00:24:51.14#ibcon#read 5, iclass 35, count 0 2006.286.00:24:51.14#ibcon#about to read 6, iclass 35, count 0 2006.286.00:24:51.14#ibcon#read 6, iclass 35, count 0 2006.286.00:24:51.14#ibcon#end of sib2, iclass 35, count 0 2006.286.00:24:51.14#ibcon#*after write, iclass 35, count 0 2006.286.00:24:51.14#ibcon#*before return 0, iclass 35, count 0 2006.286.00:24:51.14#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:24:51.14#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:24:51.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.00:24:51.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.00:24:51.14$vck44/valo=5,734.99 2006.286.00:24:51.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.00:24:51.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.00:24:51.14#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:51.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:24:51.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:24:51.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:24:51.14#ibcon#enter wrdev, iclass 37, count 0 2006.286.00:24:51.14#ibcon#first serial, iclass 37, count 0 2006.286.00:24:51.14#ibcon#enter sib2, iclass 37, count 0 2006.286.00:24:51.14#ibcon#flushed, iclass 37, count 0 2006.286.00:24:51.14#ibcon#about to write, iclass 37, count 0 2006.286.00:24:51.14#ibcon#wrote, iclass 37, count 0 2006.286.00:24:51.14#ibcon#about to read 3, iclass 37, count 0 2006.286.00:24:51.16#ibcon#read 3, iclass 37, count 0 2006.286.00:24:51.16#ibcon#about to read 4, iclass 37, count 0 2006.286.00:24:51.16#ibcon#read 4, iclass 37, count 0 2006.286.00:24:51.16#ibcon#about to read 5, iclass 37, count 0 2006.286.00:24:51.16#ibcon#read 5, iclass 37, count 0 2006.286.00:24:51.16#ibcon#about to read 6, iclass 37, count 0 2006.286.00:24:51.16#ibcon#read 6, iclass 37, count 0 2006.286.00:24:51.16#ibcon#end of sib2, iclass 37, count 0 2006.286.00:24:51.16#ibcon#*mode == 0, iclass 37, count 0 2006.286.00:24:51.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.00:24:51.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.00:24:51.16#ibcon#*before write, iclass 37, count 0 2006.286.00:24:51.16#ibcon#enter sib2, iclass 37, count 0 2006.286.00:24:51.16#ibcon#flushed, iclass 37, count 0 2006.286.00:24:51.16#ibcon#about to write, iclass 37, count 0 2006.286.00:24:51.16#ibcon#wrote, iclass 37, count 0 2006.286.00:24:51.16#ibcon#about to read 3, iclass 37, count 0 2006.286.00:24:51.20#ibcon#read 3, iclass 37, count 0 2006.286.00:24:51.20#ibcon#about to read 4, iclass 37, count 0 2006.286.00:24:51.20#ibcon#read 4, iclass 37, count 0 2006.286.00:24:51.20#ibcon#about to read 5, iclass 37, count 0 2006.286.00:24:51.20#ibcon#read 5, iclass 37, count 0 2006.286.00:24:51.20#ibcon#about to read 6, iclass 37, count 0 2006.286.00:24:51.20#ibcon#read 6, iclass 37, count 0 2006.286.00:24:51.20#ibcon#end of sib2, iclass 37, count 0 2006.286.00:24:51.20#ibcon#*after write, iclass 37, count 0 2006.286.00:24:51.20#ibcon#*before return 0, iclass 37, count 0 2006.286.00:24:51.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:24:51.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:24:51.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.00:24:51.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.00:24:51.20$vck44/va=5,3 2006.286.00:24:51.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.00:24:51.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.00:24:51.20#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:51.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:24:51.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:24:51.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:24:51.26#ibcon#enter wrdev, iclass 39, count 2 2006.286.00:24:51.26#ibcon#first serial, iclass 39, count 2 2006.286.00:24:51.26#ibcon#enter sib2, iclass 39, count 2 2006.286.00:24:51.26#ibcon#flushed, iclass 39, count 2 2006.286.00:24:51.26#ibcon#about to write, iclass 39, count 2 2006.286.00:24:51.26#ibcon#wrote, iclass 39, count 2 2006.286.00:24:51.26#ibcon#about to read 3, iclass 39, count 2 2006.286.00:24:51.28#ibcon#read 3, iclass 39, count 2 2006.286.00:24:51.28#ibcon#about to read 4, iclass 39, count 2 2006.286.00:24:51.28#ibcon#read 4, iclass 39, count 2 2006.286.00:24:51.28#ibcon#about to read 5, iclass 39, count 2 2006.286.00:24:51.28#ibcon#read 5, iclass 39, count 2 2006.286.00:24:51.28#ibcon#about to read 6, iclass 39, count 2 2006.286.00:24:51.28#ibcon#read 6, iclass 39, count 2 2006.286.00:24:51.28#ibcon#end of sib2, iclass 39, count 2 2006.286.00:24:51.28#ibcon#*mode == 0, iclass 39, count 2 2006.286.00:24:51.28#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.00:24:51.28#ibcon#[25=AT05-03\r\n] 2006.286.00:24:51.28#ibcon#*before write, iclass 39, count 2 2006.286.00:24:51.28#ibcon#enter sib2, iclass 39, count 2 2006.286.00:24:51.28#ibcon#flushed, iclass 39, count 2 2006.286.00:24:51.28#ibcon#about to write, iclass 39, count 2 2006.286.00:24:51.28#ibcon#wrote, iclass 39, count 2 2006.286.00:24:51.28#ibcon#about to read 3, iclass 39, count 2 2006.286.00:24:51.31#ibcon#read 3, iclass 39, count 2 2006.286.00:24:51.31#ibcon#about to read 4, iclass 39, count 2 2006.286.00:24:51.31#ibcon#read 4, iclass 39, count 2 2006.286.00:24:51.31#ibcon#about to read 5, iclass 39, count 2 2006.286.00:24:51.31#ibcon#read 5, iclass 39, count 2 2006.286.00:24:51.31#ibcon#about to read 6, iclass 39, count 2 2006.286.00:24:51.31#ibcon#read 6, iclass 39, count 2 2006.286.00:24:51.31#ibcon#end of sib2, iclass 39, count 2 2006.286.00:24:51.31#ibcon#*after write, iclass 39, count 2 2006.286.00:24:51.31#ibcon#*before return 0, iclass 39, count 2 2006.286.00:24:51.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:24:51.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:24:51.31#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.00:24:51.31#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:51.31#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:24:51.43#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:24:51.43#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:24:51.43#ibcon#enter wrdev, iclass 39, count 0 2006.286.00:24:51.43#ibcon#first serial, iclass 39, count 0 2006.286.00:24:51.43#ibcon#enter sib2, iclass 39, count 0 2006.286.00:24:51.43#ibcon#flushed, iclass 39, count 0 2006.286.00:24:51.43#ibcon#about to write, iclass 39, count 0 2006.286.00:24:51.43#ibcon#wrote, iclass 39, count 0 2006.286.00:24:51.43#ibcon#about to read 3, iclass 39, count 0 2006.286.00:24:51.45#ibcon#read 3, iclass 39, count 0 2006.286.00:24:51.45#ibcon#about to read 4, iclass 39, count 0 2006.286.00:24:51.45#ibcon#read 4, iclass 39, count 0 2006.286.00:24:51.45#ibcon#about to read 5, iclass 39, count 0 2006.286.00:24:51.45#ibcon#read 5, iclass 39, count 0 2006.286.00:24:51.45#ibcon#about to read 6, iclass 39, count 0 2006.286.00:24:51.45#ibcon#read 6, iclass 39, count 0 2006.286.00:24:51.45#ibcon#end of sib2, iclass 39, count 0 2006.286.00:24:51.45#ibcon#*mode == 0, iclass 39, count 0 2006.286.00:24:51.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.00:24:51.45#ibcon#[25=USB\r\n] 2006.286.00:24:51.45#ibcon#*before write, iclass 39, count 0 2006.286.00:24:51.45#ibcon#enter sib2, iclass 39, count 0 2006.286.00:24:51.45#ibcon#flushed, iclass 39, count 0 2006.286.00:24:51.45#ibcon#about to write, iclass 39, count 0 2006.286.00:24:51.45#ibcon#wrote, iclass 39, count 0 2006.286.00:24:51.45#ibcon#about to read 3, iclass 39, count 0 2006.286.00:24:51.48#ibcon#read 3, iclass 39, count 0 2006.286.00:24:51.48#ibcon#about to read 4, iclass 39, count 0 2006.286.00:24:51.48#ibcon#read 4, iclass 39, count 0 2006.286.00:24:51.48#ibcon#about to read 5, iclass 39, count 0 2006.286.00:24:51.48#ibcon#read 5, iclass 39, count 0 2006.286.00:24:51.48#ibcon#about to read 6, iclass 39, count 0 2006.286.00:24:51.48#ibcon#read 6, iclass 39, count 0 2006.286.00:24:51.48#ibcon#end of sib2, iclass 39, count 0 2006.286.00:24:51.48#ibcon#*after write, iclass 39, count 0 2006.286.00:24:51.48#ibcon#*before return 0, iclass 39, count 0 2006.286.00:24:51.48#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:24:51.48#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:24:51.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.00:24:51.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.00:24:51.48$vck44/valo=6,814.99 2006.286.00:24:51.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.00:24:51.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.00:24:51.48#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:51.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:24:51.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:24:51.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:24:51.48#ibcon#enter wrdev, iclass 3, count 0 2006.286.00:24:51.48#ibcon#first serial, iclass 3, count 0 2006.286.00:24:51.48#ibcon#enter sib2, iclass 3, count 0 2006.286.00:24:51.48#ibcon#flushed, iclass 3, count 0 2006.286.00:24:51.48#ibcon#about to write, iclass 3, count 0 2006.286.00:24:51.48#ibcon#wrote, iclass 3, count 0 2006.286.00:24:51.48#ibcon#about to read 3, iclass 3, count 0 2006.286.00:24:51.50#ibcon#read 3, iclass 3, count 0 2006.286.00:24:51.50#ibcon#about to read 4, iclass 3, count 0 2006.286.00:24:51.50#ibcon#read 4, iclass 3, count 0 2006.286.00:24:51.50#ibcon#about to read 5, iclass 3, count 0 2006.286.00:24:51.50#ibcon#read 5, iclass 3, count 0 2006.286.00:24:51.50#ibcon#about to read 6, iclass 3, count 0 2006.286.00:24:51.50#ibcon#read 6, iclass 3, count 0 2006.286.00:24:51.50#ibcon#end of sib2, iclass 3, count 0 2006.286.00:24:51.50#ibcon#*mode == 0, iclass 3, count 0 2006.286.00:24:51.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.00:24:51.50#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.00:24:51.50#ibcon#*before write, iclass 3, count 0 2006.286.00:24:51.50#ibcon#enter sib2, iclass 3, count 0 2006.286.00:24:51.50#ibcon#flushed, iclass 3, count 0 2006.286.00:24:51.50#ibcon#about to write, iclass 3, count 0 2006.286.00:24:51.50#ibcon#wrote, iclass 3, count 0 2006.286.00:24:51.50#ibcon#about to read 3, iclass 3, count 0 2006.286.00:24:51.54#ibcon#read 3, iclass 3, count 0 2006.286.00:24:51.54#ibcon#about to read 4, iclass 3, count 0 2006.286.00:24:51.54#ibcon#read 4, iclass 3, count 0 2006.286.00:24:51.54#ibcon#about to read 5, iclass 3, count 0 2006.286.00:24:51.54#ibcon#read 5, iclass 3, count 0 2006.286.00:24:51.54#ibcon#about to read 6, iclass 3, count 0 2006.286.00:24:51.54#ibcon#read 6, iclass 3, count 0 2006.286.00:24:51.54#ibcon#end of sib2, iclass 3, count 0 2006.286.00:24:51.54#ibcon#*after write, iclass 3, count 0 2006.286.00:24:51.54#ibcon#*before return 0, iclass 3, count 0 2006.286.00:24:51.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:24:51.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:24:51.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.00:24:51.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.00:24:51.54$vck44/va=6,4 2006.286.00:24:51.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.00:24:51.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.00:24:51.54#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:51.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:24:51.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:24:51.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:24:51.60#ibcon#enter wrdev, iclass 5, count 2 2006.286.00:24:51.60#ibcon#first serial, iclass 5, count 2 2006.286.00:24:51.60#ibcon#enter sib2, iclass 5, count 2 2006.286.00:24:51.60#ibcon#flushed, iclass 5, count 2 2006.286.00:24:51.60#ibcon#about to write, iclass 5, count 2 2006.286.00:24:51.60#ibcon#wrote, iclass 5, count 2 2006.286.00:24:51.60#ibcon#about to read 3, iclass 5, count 2 2006.286.00:24:51.62#ibcon#read 3, iclass 5, count 2 2006.286.00:24:51.62#ibcon#about to read 4, iclass 5, count 2 2006.286.00:24:51.62#ibcon#read 4, iclass 5, count 2 2006.286.00:24:51.62#ibcon#about to read 5, iclass 5, count 2 2006.286.00:24:51.62#ibcon#read 5, iclass 5, count 2 2006.286.00:24:51.62#ibcon#about to read 6, iclass 5, count 2 2006.286.00:24:51.62#ibcon#read 6, iclass 5, count 2 2006.286.00:24:51.62#ibcon#end of sib2, iclass 5, count 2 2006.286.00:24:51.62#ibcon#*mode == 0, iclass 5, count 2 2006.286.00:24:51.62#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.00:24:51.62#ibcon#[25=AT06-04\r\n] 2006.286.00:24:51.62#ibcon#*before write, iclass 5, count 2 2006.286.00:24:51.62#ibcon#enter sib2, iclass 5, count 2 2006.286.00:24:51.62#ibcon#flushed, iclass 5, count 2 2006.286.00:24:51.62#ibcon#about to write, iclass 5, count 2 2006.286.00:24:51.62#ibcon#wrote, iclass 5, count 2 2006.286.00:24:51.62#ibcon#about to read 3, iclass 5, count 2 2006.286.00:24:51.65#ibcon#read 3, iclass 5, count 2 2006.286.00:24:51.65#ibcon#about to read 4, iclass 5, count 2 2006.286.00:24:51.65#ibcon#read 4, iclass 5, count 2 2006.286.00:24:51.65#ibcon#about to read 5, iclass 5, count 2 2006.286.00:24:51.65#ibcon#read 5, iclass 5, count 2 2006.286.00:24:51.65#ibcon#about to read 6, iclass 5, count 2 2006.286.00:24:51.65#ibcon#read 6, iclass 5, count 2 2006.286.00:24:51.65#ibcon#end of sib2, iclass 5, count 2 2006.286.00:24:51.65#ibcon#*after write, iclass 5, count 2 2006.286.00:24:51.65#ibcon#*before return 0, iclass 5, count 2 2006.286.00:24:51.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:24:51.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:24:51.65#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.00:24:51.65#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:51.65#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:24:51.77#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:24:51.77#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:24:51.77#ibcon#enter wrdev, iclass 5, count 0 2006.286.00:24:51.77#ibcon#first serial, iclass 5, count 0 2006.286.00:24:51.77#ibcon#enter sib2, iclass 5, count 0 2006.286.00:24:51.77#ibcon#flushed, iclass 5, count 0 2006.286.00:24:51.77#ibcon#about to write, iclass 5, count 0 2006.286.00:24:51.77#ibcon#wrote, iclass 5, count 0 2006.286.00:24:51.77#ibcon#about to read 3, iclass 5, count 0 2006.286.00:24:51.79#ibcon#read 3, iclass 5, count 0 2006.286.00:24:51.79#ibcon#about to read 4, iclass 5, count 0 2006.286.00:24:51.79#ibcon#read 4, iclass 5, count 0 2006.286.00:24:51.79#ibcon#about to read 5, iclass 5, count 0 2006.286.00:24:51.79#ibcon#read 5, iclass 5, count 0 2006.286.00:24:51.79#ibcon#about to read 6, iclass 5, count 0 2006.286.00:24:51.79#ibcon#read 6, iclass 5, count 0 2006.286.00:24:51.79#ibcon#end of sib2, iclass 5, count 0 2006.286.00:24:51.79#ibcon#*mode == 0, iclass 5, count 0 2006.286.00:24:51.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.00:24:51.79#ibcon#[25=USB\r\n] 2006.286.00:24:51.79#ibcon#*before write, iclass 5, count 0 2006.286.00:24:51.79#ibcon#enter sib2, iclass 5, count 0 2006.286.00:24:51.79#ibcon#flushed, iclass 5, count 0 2006.286.00:24:51.79#ibcon#about to write, iclass 5, count 0 2006.286.00:24:51.79#ibcon#wrote, iclass 5, count 0 2006.286.00:24:51.79#ibcon#about to read 3, iclass 5, count 0 2006.286.00:24:51.82#ibcon#read 3, iclass 5, count 0 2006.286.00:24:51.82#ibcon#about to read 4, iclass 5, count 0 2006.286.00:24:51.82#ibcon#read 4, iclass 5, count 0 2006.286.00:24:51.82#ibcon#about to read 5, iclass 5, count 0 2006.286.00:24:51.82#ibcon#read 5, iclass 5, count 0 2006.286.00:24:51.82#ibcon#about to read 6, iclass 5, count 0 2006.286.00:24:51.82#ibcon#read 6, iclass 5, count 0 2006.286.00:24:51.82#ibcon#end of sib2, iclass 5, count 0 2006.286.00:24:51.82#ibcon#*after write, iclass 5, count 0 2006.286.00:24:51.82#ibcon#*before return 0, iclass 5, count 0 2006.286.00:24:51.82#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:24:51.82#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:24:51.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.00:24:51.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.00:24:51.82$vck44/valo=7,864.99 2006.286.00:24:51.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.00:24:51.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.00:24:51.82#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:51.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:24:51.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:24:51.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:24:51.82#ibcon#enter wrdev, iclass 7, count 0 2006.286.00:24:51.82#ibcon#first serial, iclass 7, count 0 2006.286.00:24:51.82#ibcon#enter sib2, iclass 7, count 0 2006.286.00:24:51.82#ibcon#flushed, iclass 7, count 0 2006.286.00:24:51.82#ibcon#about to write, iclass 7, count 0 2006.286.00:24:51.82#ibcon#wrote, iclass 7, count 0 2006.286.00:24:51.82#ibcon#about to read 3, iclass 7, count 0 2006.286.00:24:51.84#ibcon#read 3, iclass 7, count 0 2006.286.00:24:51.84#ibcon#about to read 4, iclass 7, count 0 2006.286.00:24:51.84#ibcon#read 4, iclass 7, count 0 2006.286.00:24:51.84#ibcon#about to read 5, iclass 7, count 0 2006.286.00:24:51.84#ibcon#read 5, iclass 7, count 0 2006.286.00:24:51.84#ibcon#about to read 6, iclass 7, count 0 2006.286.00:24:51.84#ibcon#read 6, iclass 7, count 0 2006.286.00:24:51.84#ibcon#end of sib2, iclass 7, count 0 2006.286.00:24:51.84#ibcon#*mode == 0, iclass 7, count 0 2006.286.00:24:51.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.00:24:51.84#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.00:24:51.84#ibcon#*before write, iclass 7, count 0 2006.286.00:24:51.84#ibcon#enter sib2, iclass 7, count 0 2006.286.00:24:51.84#ibcon#flushed, iclass 7, count 0 2006.286.00:24:51.84#ibcon#about to write, iclass 7, count 0 2006.286.00:24:51.84#ibcon#wrote, iclass 7, count 0 2006.286.00:24:51.84#ibcon#about to read 3, iclass 7, count 0 2006.286.00:24:51.88#ibcon#read 3, iclass 7, count 0 2006.286.00:24:51.88#ibcon#about to read 4, iclass 7, count 0 2006.286.00:24:51.88#ibcon#read 4, iclass 7, count 0 2006.286.00:24:51.88#ibcon#about to read 5, iclass 7, count 0 2006.286.00:24:51.88#ibcon#read 5, iclass 7, count 0 2006.286.00:24:51.88#ibcon#about to read 6, iclass 7, count 0 2006.286.00:24:51.88#ibcon#read 6, iclass 7, count 0 2006.286.00:24:51.88#ibcon#end of sib2, iclass 7, count 0 2006.286.00:24:51.88#ibcon#*after write, iclass 7, count 0 2006.286.00:24:51.88#ibcon#*before return 0, iclass 7, count 0 2006.286.00:24:51.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:24:51.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:24:51.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.00:24:51.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.00:24:51.88$vck44/va=7,4 2006.286.00:24:51.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.00:24:51.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.00:24:51.88#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:51.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:24:51.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:24:51.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:24:51.94#ibcon#enter wrdev, iclass 11, count 2 2006.286.00:24:51.94#ibcon#first serial, iclass 11, count 2 2006.286.00:24:51.94#ibcon#enter sib2, iclass 11, count 2 2006.286.00:24:51.94#ibcon#flushed, iclass 11, count 2 2006.286.00:24:51.94#ibcon#about to write, iclass 11, count 2 2006.286.00:24:51.94#ibcon#wrote, iclass 11, count 2 2006.286.00:24:51.94#ibcon#about to read 3, iclass 11, count 2 2006.286.00:24:51.96#ibcon#read 3, iclass 11, count 2 2006.286.00:24:51.96#ibcon#about to read 4, iclass 11, count 2 2006.286.00:24:51.96#ibcon#read 4, iclass 11, count 2 2006.286.00:24:51.96#ibcon#about to read 5, iclass 11, count 2 2006.286.00:24:51.96#ibcon#read 5, iclass 11, count 2 2006.286.00:24:51.96#ibcon#about to read 6, iclass 11, count 2 2006.286.00:24:51.96#ibcon#read 6, iclass 11, count 2 2006.286.00:24:51.96#ibcon#end of sib2, iclass 11, count 2 2006.286.00:24:51.96#ibcon#*mode == 0, iclass 11, count 2 2006.286.00:24:51.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.00:24:51.96#ibcon#[25=AT07-04\r\n] 2006.286.00:24:51.96#ibcon#*before write, iclass 11, count 2 2006.286.00:24:51.96#ibcon#enter sib2, iclass 11, count 2 2006.286.00:24:51.96#ibcon#flushed, iclass 11, count 2 2006.286.00:24:51.96#ibcon#about to write, iclass 11, count 2 2006.286.00:24:51.96#ibcon#wrote, iclass 11, count 2 2006.286.00:24:51.96#ibcon#about to read 3, iclass 11, count 2 2006.286.00:24:51.99#ibcon#read 3, iclass 11, count 2 2006.286.00:24:51.99#ibcon#about to read 4, iclass 11, count 2 2006.286.00:24:51.99#ibcon#read 4, iclass 11, count 2 2006.286.00:24:51.99#ibcon#about to read 5, iclass 11, count 2 2006.286.00:24:51.99#ibcon#read 5, iclass 11, count 2 2006.286.00:24:51.99#ibcon#about to read 6, iclass 11, count 2 2006.286.00:24:51.99#ibcon#read 6, iclass 11, count 2 2006.286.00:24:51.99#ibcon#end of sib2, iclass 11, count 2 2006.286.00:24:51.99#ibcon#*after write, iclass 11, count 2 2006.286.00:24:51.99#ibcon#*before return 0, iclass 11, count 2 2006.286.00:24:51.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:24:51.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:24:51.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.00:24:51.99#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:51.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:24:52.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:24:52.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:24:52.11#ibcon#enter wrdev, iclass 11, count 0 2006.286.00:24:52.11#ibcon#first serial, iclass 11, count 0 2006.286.00:24:52.11#ibcon#enter sib2, iclass 11, count 0 2006.286.00:24:52.11#ibcon#flushed, iclass 11, count 0 2006.286.00:24:52.11#ibcon#about to write, iclass 11, count 0 2006.286.00:24:52.11#ibcon#wrote, iclass 11, count 0 2006.286.00:24:52.11#ibcon#about to read 3, iclass 11, count 0 2006.286.00:24:52.13#ibcon#read 3, iclass 11, count 0 2006.286.00:24:52.13#ibcon#about to read 4, iclass 11, count 0 2006.286.00:24:52.13#ibcon#read 4, iclass 11, count 0 2006.286.00:24:52.13#ibcon#about to read 5, iclass 11, count 0 2006.286.00:24:52.13#ibcon#read 5, iclass 11, count 0 2006.286.00:24:52.13#ibcon#about to read 6, iclass 11, count 0 2006.286.00:24:52.13#ibcon#read 6, iclass 11, count 0 2006.286.00:24:52.13#ibcon#end of sib2, iclass 11, count 0 2006.286.00:24:52.13#ibcon#*mode == 0, iclass 11, count 0 2006.286.00:24:52.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.00:24:52.13#ibcon#[25=USB\r\n] 2006.286.00:24:52.13#ibcon#*before write, iclass 11, count 0 2006.286.00:24:52.13#ibcon#enter sib2, iclass 11, count 0 2006.286.00:24:52.13#ibcon#flushed, iclass 11, count 0 2006.286.00:24:52.13#ibcon#about to write, iclass 11, count 0 2006.286.00:24:52.13#ibcon#wrote, iclass 11, count 0 2006.286.00:24:52.13#ibcon#about to read 3, iclass 11, count 0 2006.286.00:24:52.16#ibcon#read 3, iclass 11, count 0 2006.286.00:24:52.16#ibcon#about to read 4, iclass 11, count 0 2006.286.00:24:52.16#ibcon#read 4, iclass 11, count 0 2006.286.00:24:52.16#ibcon#about to read 5, iclass 11, count 0 2006.286.00:24:52.16#ibcon#read 5, iclass 11, count 0 2006.286.00:24:52.16#ibcon#about to read 6, iclass 11, count 0 2006.286.00:24:52.16#ibcon#read 6, iclass 11, count 0 2006.286.00:24:52.16#ibcon#end of sib2, iclass 11, count 0 2006.286.00:24:52.16#ibcon#*after write, iclass 11, count 0 2006.286.00:24:52.16#ibcon#*before return 0, iclass 11, count 0 2006.286.00:24:52.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:24:52.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:24:52.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.00:24:52.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.00:24:52.16$vck44/valo=8,884.99 2006.286.00:24:52.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.00:24:52.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.00:24:52.16#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:52.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:24:52.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:24:52.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:24:52.16#ibcon#enter wrdev, iclass 13, count 0 2006.286.00:24:52.16#ibcon#first serial, iclass 13, count 0 2006.286.00:24:52.16#ibcon#enter sib2, iclass 13, count 0 2006.286.00:24:52.16#ibcon#flushed, iclass 13, count 0 2006.286.00:24:52.16#ibcon#about to write, iclass 13, count 0 2006.286.00:24:52.16#ibcon#wrote, iclass 13, count 0 2006.286.00:24:52.16#ibcon#about to read 3, iclass 13, count 0 2006.286.00:24:52.18#ibcon#read 3, iclass 13, count 0 2006.286.00:24:52.18#ibcon#about to read 4, iclass 13, count 0 2006.286.00:24:52.18#ibcon#read 4, iclass 13, count 0 2006.286.00:24:52.18#ibcon#about to read 5, iclass 13, count 0 2006.286.00:24:52.18#ibcon#read 5, iclass 13, count 0 2006.286.00:24:52.18#ibcon#about to read 6, iclass 13, count 0 2006.286.00:24:52.18#ibcon#read 6, iclass 13, count 0 2006.286.00:24:52.18#ibcon#end of sib2, iclass 13, count 0 2006.286.00:24:52.18#ibcon#*mode == 0, iclass 13, count 0 2006.286.00:24:52.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.00:24:52.18#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.00:24:52.18#ibcon#*before write, iclass 13, count 0 2006.286.00:24:52.18#ibcon#enter sib2, iclass 13, count 0 2006.286.00:24:52.18#ibcon#flushed, iclass 13, count 0 2006.286.00:24:52.18#ibcon#about to write, iclass 13, count 0 2006.286.00:24:52.18#ibcon#wrote, iclass 13, count 0 2006.286.00:24:52.18#ibcon#about to read 3, iclass 13, count 0 2006.286.00:24:52.22#ibcon#read 3, iclass 13, count 0 2006.286.00:24:52.22#ibcon#about to read 4, iclass 13, count 0 2006.286.00:24:52.22#ibcon#read 4, iclass 13, count 0 2006.286.00:24:52.22#ibcon#about to read 5, iclass 13, count 0 2006.286.00:24:52.22#ibcon#read 5, iclass 13, count 0 2006.286.00:24:52.22#ibcon#about to read 6, iclass 13, count 0 2006.286.00:24:52.22#ibcon#read 6, iclass 13, count 0 2006.286.00:24:52.22#ibcon#end of sib2, iclass 13, count 0 2006.286.00:24:52.22#ibcon#*after write, iclass 13, count 0 2006.286.00:24:52.22#ibcon#*before return 0, iclass 13, count 0 2006.286.00:24:52.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:24:52.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:24:52.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.00:24:52.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.00:24:52.22$vck44/va=8,3 2006.286.00:24:52.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.00:24:52.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.00:24:52.22#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:52.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:24:52.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:24:52.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:24:52.28#ibcon#enter wrdev, iclass 15, count 2 2006.286.00:24:52.28#ibcon#first serial, iclass 15, count 2 2006.286.00:24:52.28#ibcon#enter sib2, iclass 15, count 2 2006.286.00:24:52.28#ibcon#flushed, iclass 15, count 2 2006.286.00:24:52.28#ibcon#about to write, iclass 15, count 2 2006.286.00:24:52.28#ibcon#wrote, iclass 15, count 2 2006.286.00:24:52.28#ibcon#about to read 3, iclass 15, count 2 2006.286.00:24:52.30#ibcon#read 3, iclass 15, count 2 2006.286.00:24:52.30#ibcon#about to read 4, iclass 15, count 2 2006.286.00:24:52.30#ibcon#read 4, iclass 15, count 2 2006.286.00:24:52.30#ibcon#about to read 5, iclass 15, count 2 2006.286.00:24:52.30#ibcon#read 5, iclass 15, count 2 2006.286.00:24:52.30#ibcon#about to read 6, iclass 15, count 2 2006.286.00:24:52.30#ibcon#read 6, iclass 15, count 2 2006.286.00:24:52.30#ibcon#end of sib2, iclass 15, count 2 2006.286.00:24:52.30#ibcon#*mode == 0, iclass 15, count 2 2006.286.00:24:52.30#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.00:24:52.30#ibcon#[25=AT08-03\r\n] 2006.286.00:24:52.30#ibcon#*before write, iclass 15, count 2 2006.286.00:24:52.30#ibcon#enter sib2, iclass 15, count 2 2006.286.00:24:52.30#ibcon#flushed, iclass 15, count 2 2006.286.00:24:52.30#ibcon#about to write, iclass 15, count 2 2006.286.00:24:52.30#ibcon#wrote, iclass 15, count 2 2006.286.00:24:52.30#ibcon#about to read 3, iclass 15, count 2 2006.286.00:24:52.33#ibcon#read 3, iclass 15, count 2 2006.286.00:24:52.33#ibcon#about to read 4, iclass 15, count 2 2006.286.00:24:52.33#ibcon#read 4, iclass 15, count 2 2006.286.00:24:52.33#ibcon#about to read 5, iclass 15, count 2 2006.286.00:24:52.33#ibcon#read 5, iclass 15, count 2 2006.286.00:24:52.33#ibcon#about to read 6, iclass 15, count 2 2006.286.00:24:52.33#ibcon#read 6, iclass 15, count 2 2006.286.00:24:52.33#ibcon#end of sib2, iclass 15, count 2 2006.286.00:24:52.33#ibcon#*after write, iclass 15, count 2 2006.286.00:24:52.33#ibcon#*before return 0, iclass 15, count 2 2006.286.00:24:52.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:24:52.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:24:52.33#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.00:24:52.33#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:52.33#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:24:52.45#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:24:52.45#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:24:52.45#ibcon#enter wrdev, iclass 15, count 0 2006.286.00:24:52.45#ibcon#first serial, iclass 15, count 0 2006.286.00:24:52.45#ibcon#enter sib2, iclass 15, count 0 2006.286.00:24:52.45#ibcon#flushed, iclass 15, count 0 2006.286.00:24:52.45#ibcon#about to write, iclass 15, count 0 2006.286.00:24:52.45#ibcon#wrote, iclass 15, count 0 2006.286.00:24:52.45#ibcon#about to read 3, iclass 15, count 0 2006.286.00:24:52.47#ibcon#read 3, iclass 15, count 0 2006.286.00:24:52.47#ibcon#about to read 4, iclass 15, count 0 2006.286.00:24:52.47#ibcon#read 4, iclass 15, count 0 2006.286.00:24:52.47#ibcon#about to read 5, iclass 15, count 0 2006.286.00:24:52.47#ibcon#read 5, iclass 15, count 0 2006.286.00:24:52.47#ibcon#about to read 6, iclass 15, count 0 2006.286.00:24:52.47#ibcon#read 6, iclass 15, count 0 2006.286.00:24:52.47#ibcon#end of sib2, iclass 15, count 0 2006.286.00:24:52.47#ibcon#*mode == 0, iclass 15, count 0 2006.286.00:24:52.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.00:24:52.47#ibcon#[25=USB\r\n] 2006.286.00:24:52.47#ibcon#*before write, iclass 15, count 0 2006.286.00:24:52.47#ibcon#enter sib2, iclass 15, count 0 2006.286.00:24:52.47#ibcon#flushed, iclass 15, count 0 2006.286.00:24:52.47#ibcon#about to write, iclass 15, count 0 2006.286.00:24:52.47#ibcon#wrote, iclass 15, count 0 2006.286.00:24:52.47#ibcon#about to read 3, iclass 15, count 0 2006.286.00:24:52.50#ibcon#read 3, iclass 15, count 0 2006.286.00:24:52.50#ibcon#about to read 4, iclass 15, count 0 2006.286.00:24:52.50#ibcon#read 4, iclass 15, count 0 2006.286.00:24:52.50#ibcon#about to read 5, iclass 15, count 0 2006.286.00:24:52.50#ibcon#read 5, iclass 15, count 0 2006.286.00:24:52.50#ibcon#about to read 6, iclass 15, count 0 2006.286.00:24:52.50#ibcon#read 6, iclass 15, count 0 2006.286.00:24:52.50#ibcon#end of sib2, iclass 15, count 0 2006.286.00:24:52.50#ibcon#*after write, iclass 15, count 0 2006.286.00:24:52.50#ibcon#*before return 0, iclass 15, count 0 2006.286.00:24:52.50#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:24:52.50#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:24:52.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.00:24:52.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.00:24:52.50$vck44/vblo=1,629.99 2006.286.00:24:52.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.00:24:52.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.00:24:52.50#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:52.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:24:52.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:24:52.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:24:52.50#ibcon#enter wrdev, iclass 17, count 0 2006.286.00:24:52.50#ibcon#first serial, iclass 17, count 0 2006.286.00:24:52.50#ibcon#enter sib2, iclass 17, count 0 2006.286.00:24:52.50#ibcon#flushed, iclass 17, count 0 2006.286.00:24:52.50#ibcon#about to write, iclass 17, count 0 2006.286.00:24:52.50#ibcon#wrote, iclass 17, count 0 2006.286.00:24:52.50#ibcon#about to read 3, iclass 17, count 0 2006.286.00:24:52.52#ibcon#read 3, iclass 17, count 0 2006.286.00:24:52.52#ibcon#about to read 4, iclass 17, count 0 2006.286.00:24:52.52#ibcon#read 4, iclass 17, count 0 2006.286.00:24:52.52#ibcon#about to read 5, iclass 17, count 0 2006.286.00:24:52.52#ibcon#read 5, iclass 17, count 0 2006.286.00:24:52.52#ibcon#about to read 6, iclass 17, count 0 2006.286.00:24:52.52#ibcon#read 6, iclass 17, count 0 2006.286.00:24:52.52#ibcon#end of sib2, iclass 17, count 0 2006.286.00:24:52.52#ibcon#*mode == 0, iclass 17, count 0 2006.286.00:24:52.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.00:24:52.52#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.00:24:52.52#ibcon#*before write, iclass 17, count 0 2006.286.00:24:52.52#ibcon#enter sib2, iclass 17, count 0 2006.286.00:24:52.52#ibcon#flushed, iclass 17, count 0 2006.286.00:24:52.52#ibcon#about to write, iclass 17, count 0 2006.286.00:24:52.52#ibcon#wrote, iclass 17, count 0 2006.286.00:24:52.52#ibcon#about to read 3, iclass 17, count 0 2006.286.00:24:52.56#ibcon#read 3, iclass 17, count 0 2006.286.00:24:52.56#ibcon#about to read 4, iclass 17, count 0 2006.286.00:24:52.56#ibcon#read 4, iclass 17, count 0 2006.286.00:24:52.56#ibcon#about to read 5, iclass 17, count 0 2006.286.00:24:52.56#ibcon#read 5, iclass 17, count 0 2006.286.00:24:52.56#ibcon#about to read 6, iclass 17, count 0 2006.286.00:24:52.56#ibcon#read 6, iclass 17, count 0 2006.286.00:24:52.56#ibcon#end of sib2, iclass 17, count 0 2006.286.00:24:52.56#ibcon#*after write, iclass 17, count 0 2006.286.00:24:52.56#ibcon#*before return 0, iclass 17, count 0 2006.286.00:24:52.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:24:52.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:24:52.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.00:24:52.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.00:24:52.56$vck44/vb=1,4 2006.286.00:24:52.56#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.00:24:52.56#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.00:24:52.56#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:52.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:24:52.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:24:52.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:24:52.56#ibcon#enter wrdev, iclass 19, count 2 2006.286.00:24:52.56#ibcon#first serial, iclass 19, count 2 2006.286.00:24:52.56#ibcon#enter sib2, iclass 19, count 2 2006.286.00:24:52.56#ibcon#flushed, iclass 19, count 2 2006.286.00:24:52.56#ibcon#about to write, iclass 19, count 2 2006.286.00:24:52.56#ibcon#wrote, iclass 19, count 2 2006.286.00:24:52.56#ibcon#about to read 3, iclass 19, count 2 2006.286.00:24:52.58#ibcon#read 3, iclass 19, count 2 2006.286.00:24:52.58#ibcon#about to read 4, iclass 19, count 2 2006.286.00:24:52.58#ibcon#read 4, iclass 19, count 2 2006.286.00:24:52.58#ibcon#about to read 5, iclass 19, count 2 2006.286.00:24:52.58#ibcon#read 5, iclass 19, count 2 2006.286.00:24:52.58#ibcon#about to read 6, iclass 19, count 2 2006.286.00:24:52.58#ibcon#read 6, iclass 19, count 2 2006.286.00:24:52.58#ibcon#end of sib2, iclass 19, count 2 2006.286.00:24:52.58#ibcon#*mode == 0, iclass 19, count 2 2006.286.00:24:52.58#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.00:24:52.58#ibcon#[27=AT01-04\r\n] 2006.286.00:24:52.58#ibcon#*before write, iclass 19, count 2 2006.286.00:24:52.58#ibcon#enter sib2, iclass 19, count 2 2006.286.00:24:52.58#ibcon#flushed, iclass 19, count 2 2006.286.00:24:52.58#ibcon#about to write, iclass 19, count 2 2006.286.00:24:52.58#ibcon#wrote, iclass 19, count 2 2006.286.00:24:52.58#ibcon#about to read 3, iclass 19, count 2 2006.286.00:24:52.61#ibcon#read 3, iclass 19, count 2 2006.286.00:24:52.61#ibcon#about to read 4, iclass 19, count 2 2006.286.00:24:52.61#ibcon#read 4, iclass 19, count 2 2006.286.00:24:52.61#ibcon#about to read 5, iclass 19, count 2 2006.286.00:24:52.61#ibcon#read 5, iclass 19, count 2 2006.286.00:24:52.61#ibcon#about to read 6, iclass 19, count 2 2006.286.00:24:52.61#ibcon#read 6, iclass 19, count 2 2006.286.00:24:52.61#ibcon#end of sib2, iclass 19, count 2 2006.286.00:24:52.61#ibcon#*after write, iclass 19, count 2 2006.286.00:24:52.61#ibcon#*before return 0, iclass 19, count 2 2006.286.00:24:52.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:24:52.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:24:52.61#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.00:24:52.61#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:52.61#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:24:52.73#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:24:52.73#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:24:52.73#ibcon#enter wrdev, iclass 19, count 0 2006.286.00:24:52.73#ibcon#first serial, iclass 19, count 0 2006.286.00:24:52.73#ibcon#enter sib2, iclass 19, count 0 2006.286.00:24:52.73#ibcon#flushed, iclass 19, count 0 2006.286.00:24:52.73#ibcon#about to write, iclass 19, count 0 2006.286.00:24:52.73#ibcon#wrote, iclass 19, count 0 2006.286.00:24:52.73#ibcon#about to read 3, iclass 19, count 0 2006.286.00:24:52.75#ibcon#read 3, iclass 19, count 0 2006.286.00:24:52.75#ibcon#about to read 4, iclass 19, count 0 2006.286.00:24:52.75#ibcon#read 4, iclass 19, count 0 2006.286.00:24:52.75#ibcon#about to read 5, iclass 19, count 0 2006.286.00:24:52.75#ibcon#read 5, iclass 19, count 0 2006.286.00:24:52.75#ibcon#about to read 6, iclass 19, count 0 2006.286.00:24:52.75#ibcon#read 6, iclass 19, count 0 2006.286.00:24:52.75#ibcon#end of sib2, iclass 19, count 0 2006.286.00:24:52.75#ibcon#*mode == 0, iclass 19, count 0 2006.286.00:24:52.75#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.00:24:52.75#ibcon#[27=USB\r\n] 2006.286.00:24:52.75#ibcon#*before write, iclass 19, count 0 2006.286.00:24:52.75#ibcon#enter sib2, iclass 19, count 0 2006.286.00:24:52.75#ibcon#flushed, iclass 19, count 0 2006.286.00:24:52.75#ibcon#about to write, iclass 19, count 0 2006.286.00:24:52.75#ibcon#wrote, iclass 19, count 0 2006.286.00:24:52.75#ibcon#about to read 3, iclass 19, count 0 2006.286.00:24:52.78#ibcon#read 3, iclass 19, count 0 2006.286.00:24:52.78#ibcon#about to read 4, iclass 19, count 0 2006.286.00:24:52.78#ibcon#read 4, iclass 19, count 0 2006.286.00:24:52.78#ibcon#about to read 5, iclass 19, count 0 2006.286.00:24:52.78#ibcon#read 5, iclass 19, count 0 2006.286.00:24:52.78#ibcon#about to read 6, iclass 19, count 0 2006.286.00:24:52.78#ibcon#read 6, iclass 19, count 0 2006.286.00:24:52.78#ibcon#end of sib2, iclass 19, count 0 2006.286.00:24:52.78#ibcon#*after write, iclass 19, count 0 2006.286.00:24:52.78#ibcon#*before return 0, iclass 19, count 0 2006.286.00:24:52.78#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:24:52.78#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:24:52.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.00:24:52.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.00:24:52.78$vck44/vblo=2,634.99 2006.286.00:24:52.78#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.00:24:52.78#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.00:24:52.78#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:52.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:24:52.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:24:52.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:24:52.78#ibcon#enter wrdev, iclass 21, count 0 2006.286.00:24:52.78#ibcon#first serial, iclass 21, count 0 2006.286.00:24:52.78#ibcon#enter sib2, iclass 21, count 0 2006.286.00:24:52.78#ibcon#flushed, iclass 21, count 0 2006.286.00:24:52.78#ibcon#about to write, iclass 21, count 0 2006.286.00:24:52.78#ibcon#wrote, iclass 21, count 0 2006.286.00:24:52.78#ibcon#about to read 3, iclass 21, count 0 2006.286.00:24:52.80#ibcon#read 3, iclass 21, count 0 2006.286.00:24:52.80#ibcon#about to read 4, iclass 21, count 0 2006.286.00:24:52.80#ibcon#read 4, iclass 21, count 0 2006.286.00:24:52.80#ibcon#about to read 5, iclass 21, count 0 2006.286.00:24:52.80#ibcon#read 5, iclass 21, count 0 2006.286.00:24:52.80#ibcon#about to read 6, iclass 21, count 0 2006.286.00:24:52.80#ibcon#read 6, iclass 21, count 0 2006.286.00:24:52.80#ibcon#end of sib2, iclass 21, count 0 2006.286.00:24:52.80#ibcon#*mode == 0, iclass 21, count 0 2006.286.00:24:52.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.00:24:52.80#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.00:24:52.80#ibcon#*before write, iclass 21, count 0 2006.286.00:24:52.80#ibcon#enter sib2, iclass 21, count 0 2006.286.00:24:52.80#ibcon#flushed, iclass 21, count 0 2006.286.00:24:52.80#ibcon#about to write, iclass 21, count 0 2006.286.00:24:52.80#ibcon#wrote, iclass 21, count 0 2006.286.00:24:52.80#ibcon#about to read 3, iclass 21, count 0 2006.286.00:24:52.84#ibcon#read 3, iclass 21, count 0 2006.286.00:24:52.84#ibcon#about to read 4, iclass 21, count 0 2006.286.00:24:52.84#ibcon#read 4, iclass 21, count 0 2006.286.00:24:52.84#ibcon#about to read 5, iclass 21, count 0 2006.286.00:24:52.84#ibcon#read 5, iclass 21, count 0 2006.286.00:24:52.84#ibcon#about to read 6, iclass 21, count 0 2006.286.00:24:52.84#ibcon#read 6, iclass 21, count 0 2006.286.00:24:52.84#ibcon#end of sib2, iclass 21, count 0 2006.286.00:24:52.84#ibcon#*after write, iclass 21, count 0 2006.286.00:24:52.84#ibcon#*before return 0, iclass 21, count 0 2006.286.00:24:52.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:24:52.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:24:52.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.00:24:52.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.00:24:52.84$vck44/vb=2,5 2006.286.00:24:52.84#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.00:24:52.84#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.00:24:52.84#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:52.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:24:52.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:24:52.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:24:52.90#ibcon#enter wrdev, iclass 23, count 2 2006.286.00:24:52.90#ibcon#first serial, iclass 23, count 2 2006.286.00:24:52.90#ibcon#enter sib2, iclass 23, count 2 2006.286.00:24:52.90#ibcon#flushed, iclass 23, count 2 2006.286.00:24:52.90#ibcon#about to write, iclass 23, count 2 2006.286.00:24:52.90#ibcon#wrote, iclass 23, count 2 2006.286.00:24:52.90#ibcon#about to read 3, iclass 23, count 2 2006.286.00:24:52.92#ibcon#read 3, iclass 23, count 2 2006.286.00:24:52.92#ibcon#about to read 4, iclass 23, count 2 2006.286.00:24:52.92#ibcon#read 4, iclass 23, count 2 2006.286.00:24:52.92#ibcon#about to read 5, iclass 23, count 2 2006.286.00:24:52.92#ibcon#read 5, iclass 23, count 2 2006.286.00:24:52.92#ibcon#about to read 6, iclass 23, count 2 2006.286.00:24:52.92#ibcon#read 6, iclass 23, count 2 2006.286.00:24:52.92#ibcon#end of sib2, iclass 23, count 2 2006.286.00:24:52.92#ibcon#*mode == 0, iclass 23, count 2 2006.286.00:24:52.92#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.00:24:52.92#ibcon#[27=AT02-05\r\n] 2006.286.00:24:52.92#ibcon#*before write, iclass 23, count 2 2006.286.00:24:52.92#ibcon#enter sib2, iclass 23, count 2 2006.286.00:24:52.92#ibcon#flushed, iclass 23, count 2 2006.286.00:24:52.92#ibcon#about to write, iclass 23, count 2 2006.286.00:24:52.92#ibcon#wrote, iclass 23, count 2 2006.286.00:24:52.92#ibcon#about to read 3, iclass 23, count 2 2006.286.00:24:52.95#ibcon#read 3, iclass 23, count 2 2006.286.00:24:52.95#ibcon#about to read 4, iclass 23, count 2 2006.286.00:24:52.95#ibcon#read 4, iclass 23, count 2 2006.286.00:24:52.95#ibcon#about to read 5, iclass 23, count 2 2006.286.00:24:52.95#ibcon#read 5, iclass 23, count 2 2006.286.00:24:52.95#ibcon#about to read 6, iclass 23, count 2 2006.286.00:24:52.95#ibcon#read 6, iclass 23, count 2 2006.286.00:24:52.95#ibcon#end of sib2, iclass 23, count 2 2006.286.00:24:52.95#ibcon#*after write, iclass 23, count 2 2006.286.00:24:52.95#ibcon#*before return 0, iclass 23, count 2 2006.286.00:24:52.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:24:52.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:24:52.95#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.00:24:52.95#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:52.95#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:24:53.07#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:24:53.07#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:24:53.07#ibcon#enter wrdev, iclass 23, count 0 2006.286.00:24:53.07#ibcon#first serial, iclass 23, count 0 2006.286.00:24:53.07#ibcon#enter sib2, iclass 23, count 0 2006.286.00:24:53.07#ibcon#flushed, iclass 23, count 0 2006.286.00:24:53.07#ibcon#about to write, iclass 23, count 0 2006.286.00:24:53.07#ibcon#wrote, iclass 23, count 0 2006.286.00:24:53.07#ibcon#about to read 3, iclass 23, count 0 2006.286.00:24:53.09#ibcon#read 3, iclass 23, count 0 2006.286.00:24:53.09#ibcon#about to read 4, iclass 23, count 0 2006.286.00:24:53.09#ibcon#read 4, iclass 23, count 0 2006.286.00:24:53.09#ibcon#about to read 5, iclass 23, count 0 2006.286.00:24:53.09#ibcon#read 5, iclass 23, count 0 2006.286.00:24:53.09#ibcon#about to read 6, iclass 23, count 0 2006.286.00:24:53.09#ibcon#read 6, iclass 23, count 0 2006.286.00:24:53.09#ibcon#end of sib2, iclass 23, count 0 2006.286.00:24:53.09#ibcon#*mode == 0, iclass 23, count 0 2006.286.00:24:53.09#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.00:24:53.09#ibcon#[27=USB\r\n] 2006.286.00:24:53.09#ibcon#*before write, iclass 23, count 0 2006.286.00:24:53.09#ibcon#enter sib2, iclass 23, count 0 2006.286.00:24:53.09#ibcon#flushed, iclass 23, count 0 2006.286.00:24:53.09#ibcon#about to write, iclass 23, count 0 2006.286.00:24:53.09#ibcon#wrote, iclass 23, count 0 2006.286.00:24:53.09#ibcon#about to read 3, iclass 23, count 0 2006.286.00:24:53.12#ibcon#read 3, iclass 23, count 0 2006.286.00:24:53.12#ibcon#about to read 4, iclass 23, count 0 2006.286.00:24:53.12#ibcon#read 4, iclass 23, count 0 2006.286.00:24:53.12#ibcon#about to read 5, iclass 23, count 0 2006.286.00:24:53.12#ibcon#read 5, iclass 23, count 0 2006.286.00:24:53.12#ibcon#about to read 6, iclass 23, count 0 2006.286.00:24:53.12#ibcon#read 6, iclass 23, count 0 2006.286.00:24:53.12#ibcon#end of sib2, iclass 23, count 0 2006.286.00:24:53.12#ibcon#*after write, iclass 23, count 0 2006.286.00:24:53.12#ibcon#*before return 0, iclass 23, count 0 2006.286.00:24:53.12#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:24:53.12#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:24:53.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.00:24:53.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.00:24:53.12$vck44/vblo=3,649.99 2006.286.00:24:53.12#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.00:24:53.12#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.00:24:53.12#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:53.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:24:53.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:24:53.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:24:53.12#ibcon#enter wrdev, iclass 25, count 0 2006.286.00:24:53.12#ibcon#first serial, iclass 25, count 0 2006.286.00:24:53.12#ibcon#enter sib2, iclass 25, count 0 2006.286.00:24:53.12#ibcon#flushed, iclass 25, count 0 2006.286.00:24:53.12#ibcon#about to write, iclass 25, count 0 2006.286.00:24:53.12#ibcon#wrote, iclass 25, count 0 2006.286.00:24:53.12#ibcon#about to read 3, iclass 25, count 0 2006.286.00:24:53.14#ibcon#read 3, iclass 25, count 0 2006.286.00:24:53.14#ibcon#about to read 4, iclass 25, count 0 2006.286.00:24:53.14#ibcon#read 4, iclass 25, count 0 2006.286.00:24:53.14#ibcon#about to read 5, iclass 25, count 0 2006.286.00:24:53.14#ibcon#read 5, iclass 25, count 0 2006.286.00:24:53.14#ibcon#about to read 6, iclass 25, count 0 2006.286.00:24:53.14#ibcon#read 6, iclass 25, count 0 2006.286.00:24:53.14#ibcon#end of sib2, iclass 25, count 0 2006.286.00:24:53.14#ibcon#*mode == 0, iclass 25, count 0 2006.286.00:24:53.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.00:24:53.14#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.00:24:53.14#ibcon#*before write, iclass 25, count 0 2006.286.00:24:53.14#ibcon#enter sib2, iclass 25, count 0 2006.286.00:24:53.14#ibcon#flushed, iclass 25, count 0 2006.286.00:24:53.14#ibcon#about to write, iclass 25, count 0 2006.286.00:24:53.14#ibcon#wrote, iclass 25, count 0 2006.286.00:24:53.14#ibcon#about to read 3, iclass 25, count 0 2006.286.00:24:53.18#ibcon#read 3, iclass 25, count 0 2006.286.00:24:53.18#ibcon#about to read 4, iclass 25, count 0 2006.286.00:24:53.18#ibcon#read 4, iclass 25, count 0 2006.286.00:24:53.18#ibcon#about to read 5, iclass 25, count 0 2006.286.00:24:53.18#ibcon#read 5, iclass 25, count 0 2006.286.00:24:53.18#ibcon#about to read 6, iclass 25, count 0 2006.286.00:24:53.18#ibcon#read 6, iclass 25, count 0 2006.286.00:24:53.18#ibcon#end of sib2, iclass 25, count 0 2006.286.00:24:53.18#ibcon#*after write, iclass 25, count 0 2006.286.00:24:53.18#ibcon#*before return 0, iclass 25, count 0 2006.286.00:24:53.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:24:53.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:24:53.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.00:24:53.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.00:24:53.18$vck44/vb=3,4 2006.286.00:24:53.18#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.00:24:53.18#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.00:24:53.18#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:53.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:24:53.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:24:53.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:24:53.24#ibcon#enter wrdev, iclass 27, count 2 2006.286.00:24:53.24#ibcon#first serial, iclass 27, count 2 2006.286.00:24:53.24#ibcon#enter sib2, iclass 27, count 2 2006.286.00:24:53.24#ibcon#flushed, iclass 27, count 2 2006.286.00:24:53.24#ibcon#about to write, iclass 27, count 2 2006.286.00:24:53.24#ibcon#wrote, iclass 27, count 2 2006.286.00:24:53.24#ibcon#about to read 3, iclass 27, count 2 2006.286.00:24:53.26#ibcon#read 3, iclass 27, count 2 2006.286.00:24:53.26#ibcon#about to read 4, iclass 27, count 2 2006.286.00:24:53.26#ibcon#read 4, iclass 27, count 2 2006.286.00:24:53.26#ibcon#about to read 5, iclass 27, count 2 2006.286.00:24:53.26#ibcon#read 5, iclass 27, count 2 2006.286.00:24:53.26#ibcon#about to read 6, iclass 27, count 2 2006.286.00:24:53.26#ibcon#read 6, iclass 27, count 2 2006.286.00:24:53.26#ibcon#end of sib2, iclass 27, count 2 2006.286.00:24:53.26#ibcon#*mode == 0, iclass 27, count 2 2006.286.00:24:53.26#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.00:24:53.26#ibcon#[27=AT03-04\r\n] 2006.286.00:24:53.26#ibcon#*before write, iclass 27, count 2 2006.286.00:24:53.26#ibcon#enter sib2, iclass 27, count 2 2006.286.00:24:53.26#ibcon#flushed, iclass 27, count 2 2006.286.00:24:53.26#ibcon#about to write, iclass 27, count 2 2006.286.00:24:53.26#ibcon#wrote, iclass 27, count 2 2006.286.00:24:53.26#ibcon#about to read 3, iclass 27, count 2 2006.286.00:24:53.29#ibcon#read 3, iclass 27, count 2 2006.286.00:24:53.29#ibcon#about to read 4, iclass 27, count 2 2006.286.00:24:53.29#ibcon#read 4, iclass 27, count 2 2006.286.00:24:53.29#ibcon#about to read 5, iclass 27, count 2 2006.286.00:24:53.29#ibcon#read 5, iclass 27, count 2 2006.286.00:24:53.29#ibcon#about to read 6, iclass 27, count 2 2006.286.00:24:53.29#ibcon#read 6, iclass 27, count 2 2006.286.00:24:53.29#ibcon#end of sib2, iclass 27, count 2 2006.286.00:24:53.29#ibcon#*after write, iclass 27, count 2 2006.286.00:24:53.29#ibcon#*before return 0, iclass 27, count 2 2006.286.00:24:53.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:24:53.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:24:53.29#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.00:24:53.29#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:53.29#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:24:53.41#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:24:53.41#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:24:53.41#ibcon#enter wrdev, iclass 27, count 0 2006.286.00:24:53.41#ibcon#first serial, iclass 27, count 0 2006.286.00:24:53.41#ibcon#enter sib2, iclass 27, count 0 2006.286.00:24:53.41#ibcon#flushed, iclass 27, count 0 2006.286.00:24:53.41#ibcon#about to write, iclass 27, count 0 2006.286.00:24:53.41#ibcon#wrote, iclass 27, count 0 2006.286.00:24:53.41#ibcon#about to read 3, iclass 27, count 0 2006.286.00:24:53.43#ibcon#read 3, iclass 27, count 0 2006.286.00:24:53.43#ibcon#about to read 4, iclass 27, count 0 2006.286.00:24:53.43#ibcon#read 4, iclass 27, count 0 2006.286.00:24:53.43#ibcon#about to read 5, iclass 27, count 0 2006.286.00:24:53.43#ibcon#read 5, iclass 27, count 0 2006.286.00:24:53.43#ibcon#about to read 6, iclass 27, count 0 2006.286.00:24:53.43#ibcon#read 6, iclass 27, count 0 2006.286.00:24:53.43#ibcon#end of sib2, iclass 27, count 0 2006.286.00:24:53.43#ibcon#*mode == 0, iclass 27, count 0 2006.286.00:24:53.43#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.00:24:53.43#ibcon#[27=USB\r\n] 2006.286.00:24:53.43#ibcon#*before write, iclass 27, count 0 2006.286.00:24:53.43#ibcon#enter sib2, iclass 27, count 0 2006.286.00:24:53.43#ibcon#flushed, iclass 27, count 0 2006.286.00:24:53.43#ibcon#about to write, iclass 27, count 0 2006.286.00:24:53.43#ibcon#wrote, iclass 27, count 0 2006.286.00:24:53.43#ibcon#about to read 3, iclass 27, count 0 2006.286.00:24:53.46#ibcon#read 3, iclass 27, count 0 2006.286.00:24:53.46#ibcon#about to read 4, iclass 27, count 0 2006.286.00:24:53.46#ibcon#read 4, iclass 27, count 0 2006.286.00:24:53.46#ibcon#about to read 5, iclass 27, count 0 2006.286.00:24:53.46#ibcon#read 5, iclass 27, count 0 2006.286.00:24:53.46#ibcon#about to read 6, iclass 27, count 0 2006.286.00:24:53.46#ibcon#read 6, iclass 27, count 0 2006.286.00:24:53.46#ibcon#end of sib2, iclass 27, count 0 2006.286.00:24:53.46#ibcon#*after write, iclass 27, count 0 2006.286.00:24:53.46#ibcon#*before return 0, iclass 27, count 0 2006.286.00:24:53.46#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:24:53.46#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:24:53.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.00:24:53.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.00:24:53.46$vck44/vblo=4,679.99 2006.286.00:24:53.46#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.00:24:53.46#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.00:24:53.46#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:53.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:24:53.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:24:53.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:24:53.46#ibcon#enter wrdev, iclass 29, count 0 2006.286.00:24:53.46#ibcon#first serial, iclass 29, count 0 2006.286.00:24:53.46#ibcon#enter sib2, iclass 29, count 0 2006.286.00:24:53.46#ibcon#flushed, iclass 29, count 0 2006.286.00:24:53.46#ibcon#about to write, iclass 29, count 0 2006.286.00:24:53.46#ibcon#wrote, iclass 29, count 0 2006.286.00:24:53.46#ibcon#about to read 3, iclass 29, count 0 2006.286.00:24:53.48#ibcon#read 3, iclass 29, count 0 2006.286.00:24:53.48#ibcon#about to read 4, iclass 29, count 0 2006.286.00:24:53.48#ibcon#read 4, iclass 29, count 0 2006.286.00:24:53.48#ibcon#about to read 5, iclass 29, count 0 2006.286.00:24:53.48#ibcon#read 5, iclass 29, count 0 2006.286.00:24:53.48#ibcon#about to read 6, iclass 29, count 0 2006.286.00:24:53.48#ibcon#read 6, iclass 29, count 0 2006.286.00:24:53.48#ibcon#end of sib2, iclass 29, count 0 2006.286.00:24:53.48#ibcon#*mode == 0, iclass 29, count 0 2006.286.00:24:53.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.00:24:53.48#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.00:24:53.48#ibcon#*before write, iclass 29, count 0 2006.286.00:24:53.48#ibcon#enter sib2, iclass 29, count 0 2006.286.00:24:53.48#ibcon#flushed, iclass 29, count 0 2006.286.00:24:53.48#ibcon#about to write, iclass 29, count 0 2006.286.00:24:53.48#ibcon#wrote, iclass 29, count 0 2006.286.00:24:53.48#ibcon#about to read 3, iclass 29, count 0 2006.286.00:24:53.52#ibcon#read 3, iclass 29, count 0 2006.286.00:24:53.52#ibcon#about to read 4, iclass 29, count 0 2006.286.00:24:53.52#ibcon#read 4, iclass 29, count 0 2006.286.00:24:53.52#ibcon#about to read 5, iclass 29, count 0 2006.286.00:24:53.52#ibcon#read 5, iclass 29, count 0 2006.286.00:24:53.52#ibcon#about to read 6, iclass 29, count 0 2006.286.00:24:53.52#ibcon#read 6, iclass 29, count 0 2006.286.00:24:53.52#ibcon#end of sib2, iclass 29, count 0 2006.286.00:24:53.52#ibcon#*after write, iclass 29, count 0 2006.286.00:24:53.52#ibcon#*before return 0, iclass 29, count 0 2006.286.00:24:53.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:24:53.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:24:53.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.00:24:53.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.00:24:53.52$vck44/vb=4,5 2006.286.00:24:53.52#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.00:24:53.52#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.00:24:53.52#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:53.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:24:53.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:24:53.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:24:53.58#ibcon#enter wrdev, iclass 31, count 2 2006.286.00:24:53.58#ibcon#first serial, iclass 31, count 2 2006.286.00:24:53.58#ibcon#enter sib2, iclass 31, count 2 2006.286.00:24:53.58#ibcon#flushed, iclass 31, count 2 2006.286.00:24:53.58#ibcon#about to write, iclass 31, count 2 2006.286.00:24:53.58#ibcon#wrote, iclass 31, count 2 2006.286.00:24:53.58#ibcon#about to read 3, iclass 31, count 2 2006.286.00:24:53.60#ibcon#read 3, iclass 31, count 2 2006.286.00:24:53.60#ibcon#about to read 4, iclass 31, count 2 2006.286.00:24:53.60#ibcon#read 4, iclass 31, count 2 2006.286.00:24:53.60#ibcon#about to read 5, iclass 31, count 2 2006.286.00:24:53.60#ibcon#read 5, iclass 31, count 2 2006.286.00:24:53.60#ibcon#about to read 6, iclass 31, count 2 2006.286.00:24:53.60#ibcon#read 6, iclass 31, count 2 2006.286.00:24:53.60#ibcon#end of sib2, iclass 31, count 2 2006.286.00:24:53.60#ibcon#*mode == 0, iclass 31, count 2 2006.286.00:24:53.60#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.00:24:53.60#ibcon#[27=AT04-05\r\n] 2006.286.00:24:53.60#ibcon#*before write, iclass 31, count 2 2006.286.00:24:53.60#ibcon#enter sib2, iclass 31, count 2 2006.286.00:24:53.60#ibcon#flushed, iclass 31, count 2 2006.286.00:24:53.60#ibcon#about to write, iclass 31, count 2 2006.286.00:24:53.60#ibcon#wrote, iclass 31, count 2 2006.286.00:24:53.60#ibcon#about to read 3, iclass 31, count 2 2006.286.00:24:53.63#ibcon#read 3, iclass 31, count 2 2006.286.00:24:53.63#ibcon#about to read 4, iclass 31, count 2 2006.286.00:24:53.63#ibcon#read 4, iclass 31, count 2 2006.286.00:24:53.63#ibcon#about to read 5, iclass 31, count 2 2006.286.00:24:53.63#ibcon#read 5, iclass 31, count 2 2006.286.00:24:53.63#ibcon#about to read 6, iclass 31, count 2 2006.286.00:24:53.63#ibcon#read 6, iclass 31, count 2 2006.286.00:24:53.63#ibcon#end of sib2, iclass 31, count 2 2006.286.00:24:53.63#ibcon#*after write, iclass 31, count 2 2006.286.00:24:53.63#ibcon#*before return 0, iclass 31, count 2 2006.286.00:24:53.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:24:53.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:24:53.63#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.00:24:53.63#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:53.63#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:24:53.75#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:24:53.75#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:24:53.75#ibcon#enter wrdev, iclass 31, count 0 2006.286.00:24:53.75#ibcon#first serial, iclass 31, count 0 2006.286.00:24:53.75#ibcon#enter sib2, iclass 31, count 0 2006.286.00:24:53.75#ibcon#flushed, iclass 31, count 0 2006.286.00:24:53.75#ibcon#about to write, iclass 31, count 0 2006.286.00:24:53.75#ibcon#wrote, iclass 31, count 0 2006.286.00:24:53.75#ibcon#about to read 3, iclass 31, count 0 2006.286.00:24:53.77#ibcon#read 3, iclass 31, count 0 2006.286.00:24:53.77#ibcon#about to read 4, iclass 31, count 0 2006.286.00:24:53.77#ibcon#read 4, iclass 31, count 0 2006.286.00:24:53.77#ibcon#about to read 5, iclass 31, count 0 2006.286.00:24:53.77#ibcon#read 5, iclass 31, count 0 2006.286.00:24:53.77#ibcon#about to read 6, iclass 31, count 0 2006.286.00:24:53.77#ibcon#read 6, iclass 31, count 0 2006.286.00:24:53.77#ibcon#end of sib2, iclass 31, count 0 2006.286.00:24:53.77#ibcon#*mode == 0, iclass 31, count 0 2006.286.00:24:53.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.00:24:53.77#ibcon#[27=USB\r\n] 2006.286.00:24:53.77#ibcon#*before write, iclass 31, count 0 2006.286.00:24:53.77#ibcon#enter sib2, iclass 31, count 0 2006.286.00:24:53.77#ibcon#flushed, iclass 31, count 0 2006.286.00:24:53.77#ibcon#about to write, iclass 31, count 0 2006.286.00:24:53.77#ibcon#wrote, iclass 31, count 0 2006.286.00:24:53.77#ibcon#about to read 3, iclass 31, count 0 2006.286.00:24:53.80#ibcon#read 3, iclass 31, count 0 2006.286.00:24:53.80#ibcon#about to read 4, iclass 31, count 0 2006.286.00:24:53.80#ibcon#read 4, iclass 31, count 0 2006.286.00:24:53.80#ibcon#about to read 5, iclass 31, count 0 2006.286.00:24:53.80#ibcon#read 5, iclass 31, count 0 2006.286.00:24:53.80#ibcon#about to read 6, iclass 31, count 0 2006.286.00:24:53.80#ibcon#read 6, iclass 31, count 0 2006.286.00:24:53.80#ibcon#end of sib2, iclass 31, count 0 2006.286.00:24:53.80#ibcon#*after write, iclass 31, count 0 2006.286.00:24:53.80#ibcon#*before return 0, iclass 31, count 0 2006.286.00:24:53.80#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:24:53.80#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:24:53.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.00:24:53.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.00:24:53.80$vck44/vblo=5,709.99 2006.286.00:24:53.80#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.00:24:53.80#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.00:24:53.80#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:53.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:24:53.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:24:53.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:24:53.80#ibcon#enter wrdev, iclass 33, count 0 2006.286.00:24:53.80#ibcon#first serial, iclass 33, count 0 2006.286.00:24:53.80#ibcon#enter sib2, iclass 33, count 0 2006.286.00:24:53.80#ibcon#flushed, iclass 33, count 0 2006.286.00:24:53.80#ibcon#about to write, iclass 33, count 0 2006.286.00:24:53.80#ibcon#wrote, iclass 33, count 0 2006.286.00:24:53.80#ibcon#about to read 3, iclass 33, count 0 2006.286.00:24:53.82#ibcon#read 3, iclass 33, count 0 2006.286.00:24:53.82#ibcon#about to read 4, iclass 33, count 0 2006.286.00:24:53.82#ibcon#read 4, iclass 33, count 0 2006.286.00:24:53.82#ibcon#about to read 5, iclass 33, count 0 2006.286.00:24:53.82#ibcon#read 5, iclass 33, count 0 2006.286.00:24:53.82#ibcon#about to read 6, iclass 33, count 0 2006.286.00:24:53.82#ibcon#read 6, iclass 33, count 0 2006.286.00:24:53.82#ibcon#end of sib2, iclass 33, count 0 2006.286.00:24:53.82#ibcon#*mode == 0, iclass 33, count 0 2006.286.00:24:53.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.00:24:53.82#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.00:24:53.82#ibcon#*before write, iclass 33, count 0 2006.286.00:24:53.82#ibcon#enter sib2, iclass 33, count 0 2006.286.00:24:53.82#ibcon#flushed, iclass 33, count 0 2006.286.00:24:53.82#ibcon#about to write, iclass 33, count 0 2006.286.00:24:53.82#ibcon#wrote, iclass 33, count 0 2006.286.00:24:53.82#ibcon#about to read 3, iclass 33, count 0 2006.286.00:24:53.86#ibcon#read 3, iclass 33, count 0 2006.286.00:24:53.86#ibcon#about to read 4, iclass 33, count 0 2006.286.00:24:53.86#ibcon#read 4, iclass 33, count 0 2006.286.00:24:53.86#ibcon#about to read 5, iclass 33, count 0 2006.286.00:24:53.86#ibcon#read 5, iclass 33, count 0 2006.286.00:24:53.86#ibcon#about to read 6, iclass 33, count 0 2006.286.00:24:53.86#ibcon#read 6, iclass 33, count 0 2006.286.00:24:53.86#ibcon#end of sib2, iclass 33, count 0 2006.286.00:24:53.86#ibcon#*after write, iclass 33, count 0 2006.286.00:24:53.86#ibcon#*before return 0, iclass 33, count 0 2006.286.00:24:53.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:24:53.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:24:53.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.00:24:53.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.00:24:53.86$vck44/vb=5,4 2006.286.00:24:53.86#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.00:24:53.86#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.00:24:53.86#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:53.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:24:53.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:24:53.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:24:53.92#ibcon#enter wrdev, iclass 35, count 2 2006.286.00:24:53.92#ibcon#first serial, iclass 35, count 2 2006.286.00:24:53.92#ibcon#enter sib2, iclass 35, count 2 2006.286.00:24:53.92#ibcon#flushed, iclass 35, count 2 2006.286.00:24:53.92#ibcon#about to write, iclass 35, count 2 2006.286.00:24:53.92#ibcon#wrote, iclass 35, count 2 2006.286.00:24:53.92#ibcon#about to read 3, iclass 35, count 2 2006.286.00:24:53.94#ibcon#read 3, iclass 35, count 2 2006.286.00:24:53.94#ibcon#about to read 4, iclass 35, count 2 2006.286.00:24:53.94#ibcon#read 4, iclass 35, count 2 2006.286.00:24:53.94#ibcon#about to read 5, iclass 35, count 2 2006.286.00:24:53.94#ibcon#read 5, iclass 35, count 2 2006.286.00:24:53.94#ibcon#about to read 6, iclass 35, count 2 2006.286.00:24:53.94#ibcon#read 6, iclass 35, count 2 2006.286.00:24:53.94#ibcon#end of sib2, iclass 35, count 2 2006.286.00:24:53.94#ibcon#*mode == 0, iclass 35, count 2 2006.286.00:24:53.94#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.00:24:53.94#ibcon#[27=AT05-04\r\n] 2006.286.00:24:53.94#ibcon#*before write, iclass 35, count 2 2006.286.00:24:53.94#ibcon#enter sib2, iclass 35, count 2 2006.286.00:24:53.94#ibcon#flushed, iclass 35, count 2 2006.286.00:24:53.94#ibcon#about to write, iclass 35, count 2 2006.286.00:24:53.94#ibcon#wrote, iclass 35, count 2 2006.286.00:24:53.94#ibcon#about to read 3, iclass 35, count 2 2006.286.00:24:53.97#ibcon#read 3, iclass 35, count 2 2006.286.00:24:53.97#ibcon#about to read 4, iclass 35, count 2 2006.286.00:24:53.97#ibcon#read 4, iclass 35, count 2 2006.286.00:24:53.97#ibcon#about to read 5, iclass 35, count 2 2006.286.00:24:53.97#ibcon#read 5, iclass 35, count 2 2006.286.00:24:53.97#ibcon#about to read 6, iclass 35, count 2 2006.286.00:24:53.97#ibcon#read 6, iclass 35, count 2 2006.286.00:24:53.97#ibcon#end of sib2, iclass 35, count 2 2006.286.00:24:53.97#ibcon#*after write, iclass 35, count 2 2006.286.00:24:53.97#ibcon#*before return 0, iclass 35, count 2 2006.286.00:24:53.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:24:53.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:24:53.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.00:24:53.97#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:53.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:24:54.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:24:54.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:24:54.09#ibcon#enter wrdev, iclass 35, count 0 2006.286.00:24:54.09#ibcon#first serial, iclass 35, count 0 2006.286.00:24:54.09#ibcon#enter sib2, iclass 35, count 0 2006.286.00:24:54.09#ibcon#flushed, iclass 35, count 0 2006.286.00:24:54.09#ibcon#about to write, iclass 35, count 0 2006.286.00:24:54.09#ibcon#wrote, iclass 35, count 0 2006.286.00:24:54.09#ibcon#about to read 3, iclass 35, count 0 2006.286.00:24:54.11#ibcon#read 3, iclass 35, count 0 2006.286.00:24:54.11#ibcon#about to read 4, iclass 35, count 0 2006.286.00:24:54.11#ibcon#read 4, iclass 35, count 0 2006.286.00:24:54.11#ibcon#about to read 5, iclass 35, count 0 2006.286.00:24:54.11#ibcon#read 5, iclass 35, count 0 2006.286.00:24:54.11#ibcon#about to read 6, iclass 35, count 0 2006.286.00:24:54.11#ibcon#read 6, iclass 35, count 0 2006.286.00:24:54.11#ibcon#end of sib2, iclass 35, count 0 2006.286.00:24:54.11#ibcon#*mode == 0, iclass 35, count 0 2006.286.00:24:54.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.00:24:54.11#ibcon#[27=USB\r\n] 2006.286.00:24:54.11#ibcon#*before write, iclass 35, count 0 2006.286.00:24:54.11#ibcon#enter sib2, iclass 35, count 0 2006.286.00:24:54.11#ibcon#flushed, iclass 35, count 0 2006.286.00:24:54.11#ibcon#about to write, iclass 35, count 0 2006.286.00:24:54.11#ibcon#wrote, iclass 35, count 0 2006.286.00:24:54.11#ibcon#about to read 3, iclass 35, count 0 2006.286.00:24:54.14#ibcon#read 3, iclass 35, count 0 2006.286.00:24:54.14#ibcon#about to read 4, iclass 35, count 0 2006.286.00:24:54.14#ibcon#read 4, iclass 35, count 0 2006.286.00:24:54.14#ibcon#about to read 5, iclass 35, count 0 2006.286.00:24:54.14#ibcon#read 5, iclass 35, count 0 2006.286.00:24:54.14#ibcon#about to read 6, iclass 35, count 0 2006.286.00:24:54.14#ibcon#read 6, iclass 35, count 0 2006.286.00:24:54.14#ibcon#end of sib2, iclass 35, count 0 2006.286.00:24:54.14#ibcon#*after write, iclass 35, count 0 2006.286.00:24:54.14#ibcon#*before return 0, iclass 35, count 0 2006.286.00:24:54.14#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:24:54.14#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:24:54.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.00:24:54.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.00:24:54.14$vck44/vblo=6,719.99 2006.286.00:24:54.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.00:24:54.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.00:24:54.14#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:54.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:24:54.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:24:54.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:24:54.14#ibcon#enter wrdev, iclass 37, count 0 2006.286.00:24:54.14#ibcon#first serial, iclass 37, count 0 2006.286.00:24:54.14#ibcon#enter sib2, iclass 37, count 0 2006.286.00:24:54.14#ibcon#flushed, iclass 37, count 0 2006.286.00:24:54.14#ibcon#about to write, iclass 37, count 0 2006.286.00:24:54.14#ibcon#wrote, iclass 37, count 0 2006.286.00:24:54.14#ibcon#about to read 3, iclass 37, count 0 2006.286.00:24:54.16#ibcon#read 3, iclass 37, count 0 2006.286.00:24:54.16#ibcon#about to read 4, iclass 37, count 0 2006.286.00:24:54.16#ibcon#read 4, iclass 37, count 0 2006.286.00:24:54.16#ibcon#about to read 5, iclass 37, count 0 2006.286.00:24:54.16#ibcon#read 5, iclass 37, count 0 2006.286.00:24:54.16#ibcon#about to read 6, iclass 37, count 0 2006.286.00:24:54.16#ibcon#read 6, iclass 37, count 0 2006.286.00:24:54.16#ibcon#end of sib2, iclass 37, count 0 2006.286.00:24:54.16#ibcon#*mode == 0, iclass 37, count 0 2006.286.00:24:54.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.00:24:54.16#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.00:24:54.16#ibcon#*before write, iclass 37, count 0 2006.286.00:24:54.16#ibcon#enter sib2, iclass 37, count 0 2006.286.00:24:54.16#ibcon#flushed, iclass 37, count 0 2006.286.00:24:54.16#ibcon#about to write, iclass 37, count 0 2006.286.00:24:54.16#ibcon#wrote, iclass 37, count 0 2006.286.00:24:54.16#ibcon#about to read 3, iclass 37, count 0 2006.286.00:24:54.20#ibcon#read 3, iclass 37, count 0 2006.286.00:24:54.20#ibcon#about to read 4, iclass 37, count 0 2006.286.00:24:54.20#ibcon#read 4, iclass 37, count 0 2006.286.00:24:54.20#ibcon#about to read 5, iclass 37, count 0 2006.286.00:24:54.20#ibcon#read 5, iclass 37, count 0 2006.286.00:24:54.20#ibcon#about to read 6, iclass 37, count 0 2006.286.00:24:54.20#ibcon#read 6, iclass 37, count 0 2006.286.00:24:54.20#ibcon#end of sib2, iclass 37, count 0 2006.286.00:24:54.20#ibcon#*after write, iclass 37, count 0 2006.286.00:24:54.20#ibcon#*before return 0, iclass 37, count 0 2006.286.00:24:54.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:24:54.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:24:54.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.00:24:54.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.00:24:54.20$vck44/vb=6,3 2006.286.00:24:54.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.00:24:54.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.00:24:54.20#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:54.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:24:54.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:24:54.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:24:54.26#ibcon#enter wrdev, iclass 39, count 2 2006.286.00:24:54.26#ibcon#first serial, iclass 39, count 2 2006.286.00:24:54.26#ibcon#enter sib2, iclass 39, count 2 2006.286.00:24:54.26#ibcon#flushed, iclass 39, count 2 2006.286.00:24:54.26#ibcon#about to write, iclass 39, count 2 2006.286.00:24:54.26#ibcon#wrote, iclass 39, count 2 2006.286.00:24:54.26#ibcon#about to read 3, iclass 39, count 2 2006.286.00:24:54.28#ibcon#read 3, iclass 39, count 2 2006.286.00:24:54.28#ibcon#about to read 4, iclass 39, count 2 2006.286.00:24:54.28#ibcon#read 4, iclass 39, count 2 2006.286.00:24:54.28#ibcon#about to read 5, iclass 39, count 2 2006.286.00:24:54.28#ibcon#read 5, iclass 39, count 2 2006.286.00:24:54.28#ibcon#about to read 6, iclass 39, count 2 2006.286.00:24:54.28#ibcon#read 6, iclass 39, count 2 2006.286.00:24:54.28#ibcon#end of sib2, iclass 39, count 2 2006.286.00:24:54.28#ibcon#*mode == 0, iclass 39, count 2 2006.286.00:24:54.28#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.00:24:54.28#ibcon#[27=AT06-03\r\n] 2006.286.00:24:54.28#ibcon#*before write, iclass 39, count 2 2006.286.00:24:54.28#ibcon#enter sib2, iclass 39, count 2 2006.286.00:24:54.28#ibcon#flushed, iclass 39, count 2 2006.286.00:24:54.28#ibcon#about to write, iclass 39, count 2 2006.286.00:24:54.28#ibcon#wrote, iclass 39, count 2 2006.286.00:24:54.28#ibcon#about to read 3, iclass 39, count 2 2006.286.00:24:54.31#ibcon#read 3, iclass 39, count 2 2006.286.00:24:54.31#ibcon#about to read 4, iclass 39, count 2 2006.286.00:24:54.31#ibcon#read 4, iclass 39, count 2 2006.286.00:24:54.31#ibcon#about to read 5, iclass 39, count 2 2006.286.00:24:54.31#ibcon#read 5, iclass 39, count 2 2006.286.00:24:54.31#ibcon#about to read 6, iclass 39, count 2 2006.286.00:24:54.31#ibcon#read 6, iclass 39, count 2 2006.286.00:24:54.31#ibcon#end of sib2, iclass 39, count 2 2006.286.00:24:54.31#ibcon#*after write, iclass 39, count 2 2006.286.00:24:54.31#ibcon#*before return 0, iclass 39, count 2 2006.286.00:24:54.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:24:54.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:24:54.31#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.00:24:54.31#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:54.31#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:24:54.43#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:24:54.43#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:24:54.43#ibcon#enter wrdev, iclass 39, count 0 2006.286.00:24:54.43#ibcon#first serial, iclass 39, count 0 2006.286.00:24:54.43#ibcon#enter sib2, iclass 39, count 0 2006.286.00:24:54.43#ibcon#flushed, iclass 39, count 0 2006.286.00:24:54.43#ibcon#about to write, iclass 39, count 0 2006.286.00:24:54.43#ibcon#wrote, iclass 39, count 0 2006.286.00:24:54.43#ibcon#about to read 3, iclass 39, count 0 2006.286.00:24:54.45#ibcon#read 3, iclass 39, count 0 2006.286.00:24:54.45#ibcon#about to read 4, iclass 39, count 0 2006.286.00:24:54.45#ibcon#read 4, iclass 39, count 0 2006.286.00:24:54.45#ibcon#about to read 5, iclass 39, count 0 2006.286.00:24:54.45#ibcon#read 5, iclass 39, count 0 2006.286.00:24:54.45#ibcon#about to read 6, iclass 39, count 0 2006.286.00:24:54.45#ibcon#read 6, iclass 39, count 0 2006.286.00:24:54.45#ibcon#end of sib2, iclass 39, count 0 2006.286.00:24:54.45#ibcon#*mode == 0, iclass 39, count 0 2006.286.00:24:54.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.00:24:54.45#ibcon#[27=USB\r\n] 2006.286.00:24:54.45#ibcon#*before write, iclass 39, count 0 2006.286.00:24:54.45#ibcon#enter sib2, iclass 39, count 0 2006.286.00:24:54.45#ibcon#flushed, iclass 39, count 0 2006.286.00:24:54.45#ibcon#about to write, iclass 39, count 0 2006.286.00:24:54.45#ibcon#wrote, iclass 39, count 0 2006.286.00:24:54.45#ibcon#about to read 3, iclass 39, count 0 2006.286.00:24:54.48#ibcon#read 3, iclass 39, count 0 2006.286.00:24:54.48#ibcon#about to read 4, iclass 39, count 0 2006.286.00:24:54.48#ibcon#read 4, iclass 39, count 0 2006.286.00:24:54.48#ibcon#about to read 5, iclass 39, count 0 2006.286.00:24:54.48#ibcon#read 5, iclass 39, count 0 2006.286.00:24:54.48#ibcon#about to read 6, iclass 39, count 0 2006.286.00:24:54.48#ibcon#read 6, iclass 39, count 0 2006.286.00:24:54.48#ibcon#end of sib2, iclass 39, count 0 2006.286.00:24:54.48#ibcon#*after write, iclass 39, count 0 2006.286.00:24:54.48#ibcon#*before return 0, iclass 39, count 0 2006.286.00:24:54.48#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:24:54.48#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:24:54.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.00:24:54.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.00:24:54.48$vck44/vblo=7,734.99 2006.286.00:24:54.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.00:24:54.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.00:24:54.48#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:54.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:24:54.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:24:54.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:24:54.48#ibcon#enter wrdev, iclass 3, count 0 2006.286.00:24:54.48#ibcon#first serial, iclass 3, count 0 2006.286.00:24:54.48#ibcon#enter sib2, iclass 3, count 0 2006.286.00:24:54.48#ibcon#flushed, iclass 3, count 0 2006.286.00:24:54.48#ibcon#about to write, iclass 3, count 0 2006.286.00:24:54.48#ibcon#wrote, iclass 3, count 0 2006.286.00:24:54.48#ibcon#about to read 3, iclass 3, count 0 2006.286.00:24:54.50#ibcon#read 3, iclass 3, count 0 2006.286.00:24:54.50#ibcon#about to read 4, iclass 3, count 0 2006.286.00:24:54.50#ibcon#read 4, iclass 3, count 0 2006.286.00:24:54.50#ibcon#about to read 5, iclass 3, count 0 2006.286.00:24:54.50#ibcon#read 5, iclass 3, count 0 2006.286.00:24:54.50#ibcon#about to read 6, iclass 3, count 0 2006.286.00:24:54.50#ibcon#read 6, iclass 3, count 0 2006.286.00:24:54.50#ibcon#end of sib2, iclass 3, count 0 2006.286.00:24:54.50#ibcon#*mode == 0, iclass 3, count 0 2006.286.00:24:54.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.00:24:54.50#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.00:24:54.50#ibcon#*before write, iclass 3, count 0 2006.286.00:24:54.50#ibcon#enter sib2, iclass 3, count 0 2006.286.00:24:54.50#ibcon#flushed, iclass 3, count 0 2006.286.00:24:54.50#ibcon#about to write, iclass 3, count 0 2006.286.00:24:54.50#ibcon#wrote, iclass 3, count 0 2006.286.00:24:54.50#ibcon#about to read 3, iclass 3, count 0 2006.286.00:24:54.54#ibcon#read 3, iclass 3, count 0 2006.286.00:24:54.54#ibcon#about to read 4, iclass 3, count 0 2006.286.00:24:54.54#ibcon#read 4, iclass 3, count 0 2006.286.00:24:54.54#ibcon#about to read 5, iclass 3, count 0 2006.286.00:24:54.54#ibcon#read 5, iclass 3, count 0 2006.286.00:24:54.54#ibcon#about to read 6, iclass 3, count 0 2006.286.00:24:54.54#ibcon#read 6, iclass 3, count 0 2006.286.00:24:54.54#ibcon#end of sib2, iclass 3, count 0 2006.286.00:24:54.54#ibcon#*after write, iclass 3, count 0 2006.286.00:24:54.54#ibcon#*before return 0, iclass 3, count 0 2006.286.00:24:54.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:24:54.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:24:54.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.00:24:54.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.00:24:54.54$vck44/vb=7,4 2006.286.00:24:54.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.00:24:54.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.00:24:54.54#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:54.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:24:54.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:24:54.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:24:54.60#ibcon#enter wrdev, iclass 5, count 2 2006.286.00:24:54.60#ibcon#first serial, iclass 5, count 2 2006.286.00:24:54.60#ibcon#enter sib2, iclass 5, count 2 2006.286.00:24:54.60#ibcon#flushed, iclass 5, count 2 2006.286.00:24:54.60#ibcon#about to write, iclass 5, count 2 2006.286.00:24:54.60#ibcon#wrote, iclass 5, count 2 2006.286.00:24:54.60#ibcon#about to read 3, iclass 5, count 2 2006.286.00:24:54.62#ibcon#read 3, iclass 5, count 2 2006.286.00:24:54.62#ibcon#about to read 4, iclass 5, count 2 2006.286.00:24:54.62#ibcon#read 4, iclass 5, count 2 2006.286.00:24:54.62#ibcon#about to read 5, iclass 5, count 2 2006.286.00:24:54.62#ibcon#read 5, iclass 5, count 2 2006.286.00:24:54.62#ibcon#about to read 6, iclass 5, count 2 2006.286.00:24:54.62#ibcon#read 6, iclass 5, count 2 2006.286.00:24:54.62#ibcon#end of sib2, iclass 5, count 2 2006.286.00:24:54.62#ibcon#*mode == 0, iclass 5, count 2 2006.286.00:24:54.62#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.00:24:54.62#ibcon#[27=AT07-04\r\n] 2006.286.00:24:54.62#ibcon#*before write, iclass 5, count 2 2006.286.00:24:54.62#ibcon#enter sib2, iclass 5, count 2 2006.286.00:24:54.62#ibcon#flushed, iclass 5, count 2 2006.286.00:24:54.62#ibcon#about to write, iclass 5, count 2 2006.286.00:24:54.62#ibcon#wrote, iclass 5, count 2 2006.286.00:24:54.62#ibcon#about to read 3, iclass 5, count 2 2006.286.00:24:54.65#ibcon#read 3, iclass 5, count 2 2006.286.00:24:54.65#ibcon#about to read 4, iclass 5, count 2 2006.286.00:24:54.65#ibcon#read 4, iclass 5, count 2 2006.286.00:24:54.65#ibcon#about to read 5, iclass 5, count 2 2006.286.00:24:54.65#ibcon#read 5, iclass 5, count 2 2006.286.00:24:54.65#ibcon#about to read 6, iclass 5, count 2 2006.286.00:24:54.65#ibcon#read 6, iclass 5, count 2 2006.286.00:24:54.65#ibcon#end of sib2, iclass 5, count 2 2006.286.00:24:54.65#ibcon#*after write, iclass 5, count 2 2006.286.00:24:54.65#ibcon#*before return 0, iclass 5, count 2 2006.286.00:24:54.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:24:54.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:24:54.65#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.00:24:54.65#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:54.65#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:24:54.77#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:24:54.77#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:24:54.77#ibcon#enter wrdev, iclass 5, count 0 2006.286.00:24:54.77#ibcon#first serial, iclass 5, count 0 2006.286.00:24:54.77#ibcon#enter sib2, iclass 5, count 0 2006.286.00:24:54.77#ibcon#flushed, iclass 5, count 0 2006.286.00:24:54.77#ibcon#about to write, iclass 5, count 0 2006.286.00:24:54.77#ibcon#wrote, iclass 5, count 0 2006.286.00:24:54.77#ibcon#about to read 3, iclass 5, count 0 2006.286.00:24:54.79#ibcon#read 3, iclass 5, count 0 2006.286.00:24:54.79#ibcon#about to read 4, iclass 5, count 0 2006.286.00:24:54.79#ibcon#read 4, iclass 5, count 0 2006.286.00:24:54.79#ibcon#about to read 5, iclass 5, count 0 2006.286.00:24:54.79#ibcon#read 5, iclass 5, count 0 2006.286.00:24:54.79#ibcon#about to read 6, iclass 5, count 0 2006.286.00:24:54.79#ibcon#read 6, iclass 5, count 0 2006.286.00:24:54.79#ibcon#end of sib2, iclass 5, count 0 2006.286.00:24:54.79#ibcon#*mode == 0, iclass 5, count 0 2006.286.00:24:54.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.00:24:54.79#ibcon#[27=USB\r\n] 2006.286.00:24:54.79#ibcon#*before write, iclass 5, count 0 2006.286.00:24:54.79#ibcon#enter sib2, iclass 5, count 0 2006.286.00:24:54.79#ibcon#flushed, iclass 5, count 0 2006.286.00:24:54.79#ibcon#about to write, iclass 5, count 0 2006.286.00:24:54.79#ibcon#wrote, iclass 5, count 0 2006.286.00:24:54.79#ibcon#about to read 3, iclass 5, count 0 2006.286.00:24:54.82#ibcon#read 3, iclass 5, count 0 2006.286.00:24:54.82#ibcon#about to read 4, iclass 5, count 0 2006.286.00:24:54.82#ibcon#read 4, iclass 5, count 0 2006.286.00:24:54.82#ibcon#about to read 5, iclass 5, count 0 2006.286.00:24:54.82#ibcon#read 5, iclass 5, count 0 2006.286.00:24:54.82#ibcon#about to read 6, iclass 5, count 0 2006.286.00:24:54.82#ibcon#read 6, iclass 5, count 0 2006.286.00:24:54.82#ibcon#end of sib2, iclass 5, count 0 2006.286.00:24:54.82#ibcon#*after write, iclass 5, count 0 2006.286.00:24:54.82#ibcon#*before return 0, iclass 5, count 0 2006.286.00:24:54.82#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:24:54.82#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:24:54.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.00:24:54.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.00:24:54.82$vck44/vblo=8,744.99 2006.286.00:24:54.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.00:24:54.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.00:24:54.82#ibcon#ireg 17 cls_cnt 0 2006.286.00:24:54.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:24:54.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:24:54.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:24:54.82#ibcon#enter wrdev, iclass 7, count 0 2006.286.00:24:54.82#ibcon#first serial, iclass 7, count 0 2006.286.00:24:54.82#ibcon#enter sib2, iclass 7, count 0 2006.286.00:24:54.82#ibcon#flushed, iclass 7, count 0 2006.286.00:24:54.82#ibcon#about to write, iclass 7, count 0 2006.286.00:24:54.82#ibcon#wrote, iclass 7, count 0 2006.286.00:24:54.82#ibcon#about to read 3, iclass 7, count 0 2006.286.00:24:54.84#ibcon#read 3, iclass 7, count 0 2006.286.00:24:54.84#ibcon#about to read 4, iclass 7, count 0 2006.286.00:24:54.84#ibcon#read 4, iclass 7, count 0 2006.286.00:24:54.84#ibcon#about to read 5, iclass 7, count 0 2006.286.00:24:54.84#ibcon#read 5, iclass 7, count 0 2006.286.00:24:54.84#ibcon#about to read 6, iclass 7, count 0 2006.286.00:24:54.84#ibcon#read 6, iclass 7, count 0 2006.286.00:24:54.84#ibcon#end of sib2, iclass 7, count 0 2006.286.00:24:54.84#ibcon#*mode == 0, iclass 7, count 0 2006.286.00:24:54.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.00:24:54.84#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.00:24:54.84#ibcon#*before write, iclass 7, count 0 2006.286.00:24:54.84#ibcon#enter sib2, iclass 7, count 0 2006.286.00:24:54.84#ibcon#flushed, iclass 7, count 0 2006.286.00:24:54.84#ibcon#about to write, iclass 7, count 0 2006.286.00:24:54.84#ibcon#wrote, iclass 7, count 0 2006.286.00:24:54.84#ibcon#about to read 3, iclass 7, count 0 2006.286.00:24:54.88#ibcon#read 3, iclass 7, count 0 2006.286.00:24:54.88#ibcon#about to read 4, iclass 7, count 0 2006.286.00:24:54.88#ibcon#read 4, iclass 7, count 0 2006.286.00:24:54.88#ibcon#about to read 5, iclass 7, count 0 2006.286.00:24:54.88#ibcon#read 5, iclass 7, count 0 2006.286.00:24:54.88#ibcon#about to read 6, iclass 7, count 0 2006.286.00:24:54.88#ibcon#read 6, iclass 7, count 0 2006.286.00:24:54.88#ibcon#end of sib2, iclass 7, count 0 2006.286.00:24:54.88#ibcon#*after write, iclass 7, count 0 2006.286.00:24:54.88#ibcon#*before return 0, iclass 7, count 0 2006.286.00:24:54.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:24:54.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:24:54.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.00:24:54.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.00:24:54.88$vck44/vb=8,4 2006.286.00:24:54.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.00:24:54.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.00:24:54.88#ibcon#ireg 11 cls_cnt 2 2006.286.00:24:54.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:24:54.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:24:54.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:24:54.94#ibcon#enter wrdev, iclass 11, count 2 2006.286.00:24:54.94#ibcon#first serial, iclass 11, count 2 2006.286.00:24:54.94#ibcon#enter sib2, iclass 11, count 2 2006.286.00:24:54.94#ibcon#flushed, iclass 11, count 2 2006.286.00:24:54.94#ibcon#about to write, iclass 11, count 2 2006.286.00:24:54.94#ibcon#wrote, iclass 11, count 2 2006.286.00:24:54.94#ibcon#about to read 3, iclass 11, count 2 2006.286.00:24:54.96#ibcon#read 3, iclass 11, count 2 2006.286.00:24:54.96#ibcon#about to read 4, iclass 11, count 2 2006.286.00:24:54.96#ibcon#read 4, iclass 11, count 2 2006.286.00:24:54.96#ibcon#about to read 5, iclass 11, count 2 2006.286.00:24:54.96#ibcon#read 5, iclass 11, count 2 2006.286.00:24:54.96#ibcon#about to read 6, iclass 11, count 2 2006.286.00:24:54.96#ibcon#read 6, iclass 11, count 2 2006.286.00:24:54.96#ibcon#end of sib2, iclass 11, count 2 2006.286.00:24:54.96#ibcon#*mode == 0, iclass 11, count 2 2006.286.00:24:54.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.00:24:54.96#ibcon#[27=AT08-04\r\n] 2006.286.00:24:54.96#ibcon#*before write, iclass 11, count 2 2006.286.00:24:54.96#ibcon#enter sib2, iclass 11, count 2 2006.286.00:24:54.96#ibcon#flushed, iclass 11, count 2 2006.286.00:24:54.96#ibcon#about to write, iclass 11, count 2 2006.286.00:24:54.96#ibcon#wrote, iclass 11, count 2 2006.286.00:24:54.96#ibcon#about to read 3, iclass 11, count 2 2006.286.00:24:54.99#ibcon#read 3, iclass 11, count 2 2006.286.00:24:54.99#ibcon#about to read 4, iclass 11, count 2 2006.286.00:24:54.99#ibcon#read 4, iclass 11, count 2 2006.286.00:24:54.99#ibcon#about to read 5, iclass 11, count 2 2006.286.00:24:54.99#ibcon#read 5, iclass 11, count 2 2006.286.00:24:54.99#ibcon#about to read 6, iclass 11, count 2 2006.286.00:24:54.99#ibcon#read 6, iclass 11, count 2 2006.286.00:24:54.99#ibcon#end of sib2, iclass 11, count 2 2006.286.00:24:54.99#ibcon#*after write, iclass 11, count 2 2006.286.00:24:54.99#ibcon#*before return 0, iclass 11, count 2 2006.286.00:24:54.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:24:54.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:24:54.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.00:24:54.99#ibcon#ireg 7 cls_cnt 0 2006.286.00:24:54.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:24:55.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:24:55.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:24:55.11#ibcon#enter wrdev, iclass 11, count 0 2006.286.00:24:55.11#ibcon#first serial, iclass 11, count 0 2006.286.00:24:55.11#ibcon#enter sib2, iclass 11, count 0 2006.286.00:24:55.11#ibcon#flushed, iclass 11, count 0 2006.286.00:24:55.11#ibcon#about to write, iclass 11, count 0 2006.286.00:24:55.11#ibcon#wrote, iclass 11, count 0 2006.286.00:24:55.11#ibcon#about to read 3, iclass 11, count 0 2006.286.00:24:55.13#ibcon#read 3, iclass 11, count 0 2006.286.00:24:55.13#ibcon#about to read 4, iclass 11, count 0 2006.286.00:24:55.13#ibcon#read 4, iclass 11, count 0 2006.286.00:24:55.13#ibcon#about to read 5, iclass 11, count 0 2006.286.00:24:55.13#ibcon#read 5, iclass 11, count 0 2006.286.00:24:55.13#ibcon#about to read 6, iclass 11, count 0 2006.286.00:24:55.13#ibcon#read 6, iclass 11, count 0 2006.286.00:24:55.13#ibcon#end of sib2, iclass 11, count 0 2006.286.00:24:55.13#ibcon#*mode == 0, iclass 11, count 0 2006.286.00:24:55.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.00:24:55.13#ibcon#[27=USB\r\n] 2006.286.00:24:55.13#ibcon#*before write, iclass 11, count 0 2006.286.00:24:55.13#ibcon#enter sib2, iclass 11, count 0 2006.286.00:24:55.13#ibcon#flushed, iclass 11, count 0 2006.286.00:24:55.13#ibcon#about to write, iclass 11, count 0 2006.286.00:24:55.13#ibcon#wrote, iclass 11, count 0 2006.286.00:24:55.13#ibcon#about to read 3, iclass 11, count 0 2006.286.00:24:55.16#ibcon#read 3, iclass 11, count 0 2006.286.00:24:55.16#ibcon#about to read 4, iclass 11, count 0 2006.286.00:24:55.16#ibcon#read 4, iclass 11, count 0 2006.286.00:24:55.16#ibcon#about to read 5, iclass 11, count 0 2006.286.00:24:55.16#ibcon#read 5, iclass 11, count 0 2006.286.00:24:55.16#ibcon#about to read 6, iclass 11, count 0 2006.286.00:24:55.16#ibcon#read 6, iclass 11, count 0 2006.286.00:24:55.16#ibcon#end of sib2, iclass 11, count 0 2006.286.00:24:55.16#ibcon#*after write, iclass 11, count 0 2006.286.00:24:55.16#ibcon#*before return 0, iclass 11, count 0 2006.286.00:24:55.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:24:55.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:24:55.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.00:24:55.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.00:24:55.16$vck44/vabw=wide 2006.286.00:24:55.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.00:24:55.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.00:24:55.16#ibcon#ireg 8 cls_cnt 0 2006.286.00:24:55.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:24:55.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:24:55.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:24:55.16#ibcon#enter wrdev, iclass 13, count 0 2006.286.00:24:55.16#ibcon#first serial, iclass 13, count 0 2006.286.00:24:55.16#ibcon#enter sib2, iclass 13, count 0 2006.286.00:24:55.16#ibcon#flushed, iclass 13, count 0 2006.286.00:24:55.16#ibcon#about to write, iclass 13, count 0 2006.286.00:24:55.16#ibcon#wrote, iclass 13, count 0 2006.286.00:24:55.16#ibcon#about to read 3, iclass 13, count 0 2006.286.00:24:55.18#ibcon#read 3, iclass 13, count 0 2006.286.00:24:55.18#ibcon#about to read 4, iclass 13, count 0 2006.286.00:24:55.18#ibcon#read 4, iclass 13, count 0 2006.286.00:24:55.18#ibcon#about to read 5, iclass 13, count 0 2006.286.00:24:55.18#ibcon#read 5, iclass 13, count 0 2006.286.00:24:55.18#ibcon#about to read 6, iclass 13, count 0 2006.286.00:24:55.18#ibcon#read 6, iclass 13, count 0 2006.286.00:24:55.18#ibcon#end of sib2, iclass 13, count 0 2006.286.00:24:55.18#ibcon#*mode == 0, iclass 13, count 0 2006.286.00:24:55.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.00:24:55.18#ibcon#[25=BW32\r\n] 2006.286.00:24:55.18#ibcon#*before write, iclass 13, count 0 2006.286.00:24:55.18#ibcon#enter sib2, iclass 13, count 0 2006.286.00:24:55.18#ibcon#flushed, iclass 13, count 0 2006.286.00:24:55.18#ibcon#about to write, iclass 13, count 0 2006.286.00:24:55.18#ibcon#wrote, iclass 13, count 0 2006.286.00:24:55.18#ibcon#about to read 3, iclass 13, count 0 2006.286.00:24:55.21#ibcon#read 3, iclass 13, count 0 2006.286.00:24:55.21#ibcon#about to read 4, iclass 13, count 0 2006.286.00:24:55.21#ibcon#read 4, iclass 13, count 0 2006.286.00:24:55.21#ibcon#about to read 5, iclass 13, count 0 2006.286.00:24:55.21#ibcon#read 5, iclass 13, count 0 2006.286.00:24:55.21#ibcon#about to read 6, iclass 13, count 0 2006.286.00:24:55.21#ibcon#read 6, iclass 13, count 0 2006.286.00:24:55.21#ibcon#end of sib2, iclass 13, count 0 2006.286.00:24:55.21#ibcon#*after write, iclass 13, count 0 2006.286.00:24:55.21#ibcon#*before return 0, iclass 13, count 0 2006.286.00:24:55.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:24:55.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:24:55.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.00:24:55.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.00:24:55.21$vck44/vbbw=wide 2006.286.00:24:55.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.00:24:55.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.00:24:55.21#ibcon#ireg 8 cls_cnt 0 2006.286.00:24:55.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:24:55.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:24:55.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:24:55.28#ibcon#enter wrdev, iclass 15, count 0 2006.286.00:24:55.28#ibcon#first serial, iclass 15, count 0 2006.286.00:24:55.28#ibcon#enter sib2, iclass 15, count 0 2006.286.00:24:55.28#ibcon#flushed, iclass 15, count 0 2006.286.00:24:55.28#ibcon#about to write, iclass 15, count 0 2006.286.00:24:55.28#ibcon#wrote, iclass 15, count 0 2006.286.00:24:55.28#ibcon#about to read 3, iclass 15, count 0 2006.286.00:24:55.30#ibcon#read 3, iclass 15, count 0 2006.286.00:24:55.30#ibcon#about to read 4, iclass 15, count 0 2006.286.00:24:55.30#ibcon#read 4, iclass 15, count 0 2006.286.00:24:55.30#ibcon#about to read 5, iclass 15, count 0 2006.286.00:24:55.30#ibcon#read 5, iclass 15, count 0 2006.286.00:24:55.30#ibcon#about to read 6, iclass 15, count 0 2006.286.00:24:55.30#ibcon#read 6, iclass 15, count 0 2006.286.00:24:55.30#ibcon#end of sib2, iclass 15, count 0 2006.286.00:24:55.30#ibcon#*mode == 0, iclass 15, count 0 2006.286.00:24:55.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.00:24:55.30#ibcon#[27=BW32\r\n] 2006.286.00:24:55.30#ibcon#*before write, iclass 15, count 0 2006.286.00:24:55.30#ibcon#enter sib2, iclass 15, count 0 2006.286.00:24:55.30#ibcon#flushed, iclass 15, count 0 2006.286.00:24:55.30#ibcon#about to write, iclass 15, count 0 2006.286.00:24:55.30#ibcon#wrote, iclass 15, count 0 2006.286.00:24:55.30#ibcon#about to read 3, iclass 15, count 0 2006.286.00:24:55.33#ibcon#read 3, iclass 15, count 0 2006.286.00:24:55.33#ibcon#about to read 4, iclass 15, count 0 2006.286.00:24:55.33#ibcon#read 4, iclass 15, count 0 2006.286.00:24:55.33#ibcon#about to read 5, iclass 15, count 0 2006.286.00:24:55.33#ibcon#read 5, iclass 15, count 0 2006.286.00:24:55.33#ibcon#about to read 6, iclass 15, count 0 2006.286.00:24:55.33#ibcon#read 6, iclass 15, count 0 2006.286.00:24:55.33#ibcon#end of sib2, iclass 15, count 0 2006.286.00:24:55.33#ibcon#*after write, iclass 15, count 0 2006.286.00:24:55.33#ibcon#*before return 0, iclass 15, count 0 2006.286.00:24:55.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:24:55.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:24:55.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.00:24:55.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.00:24:55.33$setupk4/ifdk4 2006.286.00:24:55.33$ifdk4/lo= 2006.286.00:24:55.33$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.00:24:55.33$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.00:24:55.33$ifdk4/patch= 2006.286.00:24:55.33$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.00:24:55.33$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.00:24:55.33$setupk4/!*+20s 2006.286.00:24:57.72#abcon#<5=/03 3.3 7.0 19.87 861016.4\r\n> 2006.286.00:24:57.74#abcon#{5=INTERFACE CLEAR} 2006.286.00:24:57.80#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:25:05.13#trakl#Source acquired 2006.286.00:25:05.13#flagr#flagr/antenna,acquired 2006.286.00:25:07.89#abcon#<5=/03 3.3 7.0 19.87 851016.4\r\n> 2006.286.00:25:07.91#abcon#{5=INTERFACE CLEAR} 2006.286.00:25:07.97#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:25:09.84$setupk4/"tpicd 2006.286.00:25:09.84$setupk4/echo=off 2006.286.00:25:09.84$setupk4/xlog=off 2006.286.00:25:09.84:!2006.286.00:26:55 2006.286.00:26:55.00:preob 2006.286.00:26:55.14/onsource/TRACKING 2006.286.00:26:55.14:!2006.286.00:27:05 2006.286.00:27:05.00:"tape 2006.286.00:27:05.00:"st=record 2006.286.00:27:05.00:data_valid=on 2006.286.00:27:05.00:midob 2006.286.00:27:05.14/onsource/TRACKING 2006.286.00:27:05.14/wx/19.89,1016.4,85 2006.286.00:27:05.22/cable/+6.5084E-03 2006.286.00:27:06.31/va/01,07,usb,yes,36,39 2006.286.00:27:06.31/va/02,06,usb,yes,37,37 2006.286.00:27:06.31/va/03,07,usb,yes,36,38 2006.286.00:27:06.31/va/04,06,usb,yes,38,39 2006.286.00:27:06.31/va/05,03,usb,yes,37,38 2006.286.00:27:06.31/va/06,04,usb,yes,33,33 2006.286.00:27:06.31/va/07,04,usb,yes,34,35 2006.286.00:27:06.31/va/08,03,usb,yes,35,42 2006.286.00:27:06.54/valo/01,524.99,yes,locked 2006.286.00:27:06.54/valo/02,534.99,yes,locked 2006.286.00:27:06.54/valo/03,564.99,yes,locked 2006.286.00:27:06.54/valo/04,624.99,yes,locked 2006.286.00:27:06.54/valo/05,734.99,yes,locked 2006.286.00:27:06.54/valo/06,814.99,yes,locked 2006.286.00:27:06.54/valo/07,864.99,yes,locked 2006.286.00:27:06.54/valo/08,884.99,yes,locked 2006.286.00:27:07.63/vb/01,04,usb,yes,32,30 2006.286.00:27:07.63/vb/02,05,usb,yes,31,30 2006.286.00:27:07.63/vb/03,04,usb,yes,33,35 2006.286.00:27:07.63/vb/04,05,usb,yes,32,31 2006.286.00:27:07.63/vb/05,04,usb,yes,28,31 2006.286.00:27:07.63/vb/06,03,usb,yes,40,36 2006.286.00:27:07.63/vb/07,04,usb,yes,33,33 2006.286.00:27:07.63/vb/08,04,usb,yes,30,34 2006.286.00:27:07.86/vblo/01,629.99,yes,locked 2006.286.00:27:07.86/vblo/02,634.99,yes,locked 2006.286.00:27:07.86/vblo/03,649.99,yes,locked 2006.286.00:27:07.86/vblo/04,679.99,yes,locked 2006.286.00:27:07.86/vblo/05,709.99,yes,locked 2006.286.00:27:07.86/vblo/06,719.99,yes,locked 2006.286.00:27:07.86/vblo/07,734.99,yes,locked 2006.286.00:27:07.86/vblo/08,744.99,yes,locked 2006.286.00:27:08.01/vabw/8 2006.286.00:27:08.16/vbbw/8 2006.286.00:27:08.25/xfe/off,on,12.0 2006.286.00:27:08.62/ifatt/23,28,28,28 2006.286.00:27:09.07/fmout-gps/S +2.69E-07 2006.286.00:27:09.09:!2006.286.00:29:35 2006.286.00:29:35.00:data_valid=off 2006.286.00:29:35.00:"et 2006.286.00:29:35.00:!+3s 2006.286.00:29:38.01:"tape 2006.286.00:29:38.01:postob 2006.286.00:29:38.12/cable/+6.5078E-03 2006.286.00:29:38.12/wx/19.89,1016.4,85 2006.286.00:29:39.07/fmout-gps/S +2.69E-07 2006.286.00:29:39.07:scan_name=286-0033,jd0610,450 2006.286.00:29:39.07:source=0804+499,080839.67,495036.5,2000.0,cw 2006.286.00:29:39.14#flagr#flagr/antenna,new-source 2006.286.00:29:40.14:checkk5 2006.286.00:29:40.53/chk_autoobs//k5ts1/ autoobs is running! 2006.286.00:29:40.90/chk_autoobs//k5ts2/ autoobs is running! 2006.286.00:29:41.33/chk_autoobs//k5ts3/ autoobs is running! 2006.286.00:29:41.92/chk_autoobs//k5ts4/ autoobs is running! 2006.286.00:29:42.51/chk_obsdata//k5ts1/T2860027??a.dat file size is correct (nominal:600MB, actual:596MB). 2006.286.00:29:42.94/chk_obsdata//k5ts2/T2860027??b.dat file size is correct (nominal:600MB, actual:596MB). 2006.286.00:29:43.51/chk_obsdata//k5ts3/T2860027??c.dat file size is correct (nominal:600MB, actual:596MB). 2006.286.00:29:43.95/chk_obsdata//k5ts4/T2860027??d.dat file size is correct (nominal:600MB, actual:596MB). 2006.286.00:29:44.91/k5log//k5ts1_log_newline 2006.286.00:29:45.81/k5log//k5ts2_log_newline 2006.286.00:29:46.58/k5log//k5ts3_log_newline 2006.286.00:29:47.44/k5log//k5ts4_log_newline 2006.286.00:29:47.46/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.00:29:47.46:setupk4=1 2006.286.00:29:47.46$setupk4/echo=on 2006.286.00:29:47.46$setupk4/pcalon 2006.286.00:29:47.46$pcalon/"no phase cal control is implemented here 2006.286.00:29:47.46$setupk4/"tpicd=stop 2006.286.00:29:47.46$setupk4/"rec=synch_on 2006.286.00:29:47.46$setupk4/"rec_mode=128 2006.286.00:29:47.46$setupk4/!* 2006.286.00:29:47.46$setupk4/recpk4 2006.286.00:29:47.46$recpk4/recpatch= 2006.286.00:29:47.46$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.00:29:47.46$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.00:29:47.46$setupk4/vck44 2006.286.00:29:47.46$vck44/valo=1,524.99 2006.286.00:29:47.46#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.00:29:47.46#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.00:29:47.46#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:47.46#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:29:47.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:29:47.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:29:47.46#ibcon#enter wrdev, iclass 28, count 0 2006.286.00:29:47.46#ibcon#first serial, iclass 28, count 0 2006.286.00:29:47.46#ibcon#enter sib2, iclass 28, count 0 2006.286.00:29:47.46#ibcon#flushed, iclass 28, count 0 2006.286.00:29:47.46#ibcon#about to write, iclass 28, count 0 2006.286.00:29:47.46#ibcon#wrote, iclass 28, count 0 2006.286.00:29:47.46#ibcon#about to read 3, iclass 28, count 0 2006.286.00:29:47.48#ibcon#read 3, iclass 28, count 0 2006.286.00:29:47.48#ibcon#about to read 4, iclass 28, count 0 2006.286.00:29:47.48#ibcon#read 4, iclass 28, count 0 2006.286.00:29:47.48#ibcon#about to read 5, iclass 28, count 0 2006.286.00:29:47.48#ibcon#read 5, iclass 28, count 0 2006.286.00:29:47.48#ibcon#about to read 6, iclass 28, count 0 2006.286.00:29:47.48#ibcon#read 6, iclass 28, count 0 2006.286.00:29:47.48#ibcon#end of sib2, iclass 28, count 0 2006.286.00:29:47.48#ibcon#*mode == 0, iclass 28, count 0 2006.286.00:29:47.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.00:29:47.48#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.00:29:47.48#ibcon#*before write, iclass 28, count 0 2006.286.00:29:47.48#ibcon#enter sib2, iclass 28, count 0 2006.286.00:29:47.48#ibcon#flushed, iclass 28, count 0 2006.286.00:29:47.48#ibcon#about to write, iclass 28, count 0 2006.286.00:29:47.48#ibcon#wrote, iclass 28, count 0 2006.286.00:29:47.48#ibcon#about to read 3, iclass 28, count 0 2006.286.00:29:47.53#ibcon#read 3, iclass 28, count 0 2006.286.00:29:47.53#ibcon#about to read 4, iclass 28, count 0 2006.286.00:29:47.53#ibcon#read 4, iclass 28, count 0 2006.286.00:29:47.53#ibcon#about to read 5, iclass 28, count 0 2006.286.00:29:47.53#ibcon#read 5, iclass 28, count 0 2006.286.00:29:47.53#ibcon#about to read 6, iclass 28, count 0 2006.286.00:29:47.53#ibcon#read 6, iclass 28, count 0 2006.286.00:29:47.53#ibcon#end of sib2, iclass 28, count 0 2006.286.00:29:47.53#ibcon#*after write, iclass 28, count 0 2006.286.00:29:47.53#ibcon#*before return 0, iclass 28, count 0 2006.286.00:29:47.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:29:47.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:29:47.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.00:29:47.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.00:29:47.53$vck44/va=1,7 2006.286.00:29:47.53#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.00:29:47.53#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.00:29:47.53#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:47.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:29:47.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:29:47.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:29:47.53#ibcon#enter wrdev, iclass 30, count 2 2006.286.00:29:47.53#ibcon#first serial, iclass 30, count 2 2006.286.00:29:47.53#ibcon#enter sib2, iclass 30, count 2 2006.286.00:29:47.53#ibcon#flushed, iclass 30, count 2 2006.286.00:29:47.53#ibcon#about to write, iclass 30, count 2 2006.286.00:29:47.53#ibcon#wrote, iclass 30, count 2 2006.286.00:29:47.53#ibcon#about to read 3, iclass 30, count 2 2006.286.00:29:47.55#ibcon#read 3, iclass 30, count 2 2006.286.00:29:47.55#ibcon#about to read 4, iclass 30, count 2 2006.286.00:29:47.55#ibcon#read 4, iclass 30, count 2 2006.286.00:29:47.55#ibcon#about to read 5, iclass 30, count 2 2006.286.00:29:47.55#ibcon#read 5, iclass 30, count 2 2006.286.00:29:47.55#ibcon#about to read 6, iclass 30, count 2 2006.286.00:29:47.55#ibcon#read 6, iclass 30, count 2 2006.286.00:29:47.55#ibcon#end of sib2, iclass 30, count 2 2006.286.00:29:47.55#ibcon#*mode == 0, iclass 30, count 2 2006.286.00:29:47.55#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.00:29:47.55#ibcon#[25=AT01-07\r\n] 2006.286.00:29:47.55#ibcon#*before write, iclass 30, count 2 2006.286.00:29:47.55#ibcon#enter sib2, iclass 30, count 2 2006.286.00:29:47.55#ibcon#flushed, iclass 30, count 2 2006.286.00:29:47.55#ibcon#about to write, iclass 30, count 2 2006.286.00:29:47.55#ibcon#wrote, iclass 30, count 2 2006.286.00:29:47.55#ibcon#about to read 3, iclass 30, count 2 2006.286.00:29:47.58#ibcon#read 3, iclass 30, count 2 2006.286.00:29:47.58#ibcon#about to read 4, iclass 30, count 2 2006.286.00:29:47.58#ibcon#read 4, iclass 30, count 2 2006.286.00:29:47.58#ibcon#about to read 5, iclass 30, count 2 2006.286.00:29:47.58#ibcon#read 5, iclass 30, count 2 2006.286.00:29:47.58#ibcon#about to read 6, iclass 30, count 2 2006.286.00:29:47.58#ibcon#read 6, iclass 30, count 2 2006.286.00:29:47.58#ibcon#end of sib2, iclass 30, count 2 2006.286.00:29:47.58#ibcon#*after write, iclass 30, count 2 2006.286.00:29:47.58#ibcon#*before return 0, iclass 30, count 2 2006.286.00:29:47.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:29:47.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:29:47.58#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.00:29:47.58#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:47.58#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:29:47.70#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:29:47.70#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:29:47.70#ibcon#enter wrdev, iclass 30, count 0 2006.286.00:29:47.70#ibcon#first serial, iclass 30, count 0 2006.286.00:29:47.70#ibcon#enter sib2, iclass 30, count 0 2006.286.00:29:47.70#ibcon#flushed, iclass 30, count 0 2006.286.00:29:47.70#ibcon#about to write, iclass 30, count 0 2006.286.00:29:47.70#ibcon#wrote, iclass 30, count 0 2006.286.00:29:47.70#ibcon#about to read 3, iclass 30, count 0 2006.286.00:29:47.72#ibcon#read 3, iclass 30, count 0 2006.286.00:29:47.72#ibcon#about to read 4, iclass 30, count 0 2006.286.00:29:47.72#ibcon#read 4, iclass 30, count 0 2006.286.00:29:47.72#ibcon#about to read 5, iclass 30, count 0 2006.286.00:29:47.72#ibcon#read 5, iclass 30, count 0 2006.286.00:29:47.72#ibcon#about to read 6, iclass 30, count 0 2006.286.00:29:47.72#ibcon#read 6, iclass 30, count 0 2006.286.00:29:47.72#ibcon#end of sib2, iclass 30, count 0 2006.286.00:29:47.72#ibcon#*mode == 0, iclass 30, count 0 2006.286.00:29:47.72#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.00:29:47.72#ibcon#[25=USB\r\n] 2006.286.00:29:47.72#ibcon#*before write, iclass 30, count 0 2006.286.00:29:47.72#ibcon#enter sib2, iclass 30, count 0 2006.286.00:29:47.72#ibcon#flushed, iclass 30, count 0 2006.286.00:29:47.72#ibcon#about to write, iclass 30, count 0 2006.286.00:29:47.72#ibcon#wrote, iclass 30, count 0 2006.286.00:29:47.72#ibcon#about to read 3, iclass 30, count 0 2006.286.00:29:47.75#ibcon#read 3, iclass 30, count 0 2006.286.00:29:47.75#ibcon#about to read 4, iclass 30, count 0 2006.286.00:29:47.75#ibcon#read 4, iclass 30, count 0 2006.286.00:29:47.75#ibcon#about to read 5, iclass 30, count 0 2006.286.00:29:47.75#ibcon#read 5, iclass 30, count 0 2006.286.00:29:47.75#ibcon#about to read 6, iclass 30, count 0 2006.286.00:29:47.75#ibcon#read 6, iclass 30, count 0 2006.286.00:29:47.75#ibcon#end of sib2, iclass 30, count 0 2006.286.00:29:47.75#ibcon#*after write, iclass 30, count 0 2006.286.00:29:47.75#ibcon#*before return 0, iclass 30, count 0 2006.286.00:29:47.75#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:29:47.75#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:29:47.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.00:29:47.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.00:29:47.75$vck44/valo=2,534.99 2006.286.00:29:47.75#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.00:29:47.75#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.00:29:47.75#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:47.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:29:47.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:29:47.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:29:47.75#ibcon#enter wrdev, iclass 32, count 0 2006.286.00:29:47.75#ibcon#first serial, iclass 32, count 0 2006.286.00:29:47.75#ibcon#enter sib2, iclass 32, count 0 2006.286.00:29:47.75#ibcon#flushed, iclass 32, count 0 2006.286.00:29:47.75#ibcon#about to write, iclass 32, count 0 2006.286.00:29:47.75#ibcon#wrote, iclass 32, count 0 2006.286.00:29:47.75#ibcon#about to read 3, iclass 32, count 0 2006.286.00:29:47.77#ibcon#read 3, iclass 32, count 0 2006.286.00:29:47.77#ibcon#about to read 4, iclass 32, count 0 2006.286.00:29:47.77#ibcon#read 4, iclass 32, count 0 2006.286.00:29:47.77#ibcon#about to read 5, iclass 32, count 0 2006.286.00:29:47.77#ibcon#read 5, iclass 32, count 0 2006.286.00:29:47.77#ibcon#about to read 6, iclass 32, count 0 2006.286.00:29:47.77#ibcon#read 6, iclass 32, count 0 2006.286.00:29:47.77#ibcon#end of sib2, iclass 32, count 0 2006.286.00:29:47.77#ibcon#*mode == 0, iclass 32, count 0 2006.286.00:29:47.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.00:29:47.77#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.00:29:47.77#ibcon#*before write, iclass 32, count 0 2006.286.00:29:47.77#ibcon#enter sib2, iclass 32, count 0 2006.286.00:29:47.77#ibcon#flushed, iclass 32, count 0 2006.286.00:29:47.77#ibcon#about to write, iclass 32, count 0 2006.286.00:29:47.77#ibcon#wrote, iclass 32, count 0 2006.286.00:29:47.77#ibcon#about to read 3, iclass 32, count 0 2006.286.00:29:47.81#ibcon#read 3, iclass 32, count 0 2006.286.00:29:47.81#ibcon#about to read 4, iclass 32, count 0 2006.286.00:29:47.81#ibcon#read 4, iclass 32, count 0 2006.286.00:29:47.81#ibcon#about to read 5, iclass 32, count 0 2006.286.00:29:47.81#ibcon#read 5, iclass 32, count 0 2006.286.00:29:47.81#ibcon#about to read 6, iclass 32, count 0 2006.286.00:29:47.81#ibcon#read 6, iclass 32, count 0 2006.286.00:29:47.81#ibcon#end of sib2, iclass 32, count 0 2006.286.00:29:47.81#ibcon#*after write, iclass 32, count 0 2006.286.00:29:47.81#ibcon#*before return 0, iclass 32, count 0 2006.286.00:29:47.81#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:29:47.81#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:29:47.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.00:29:47.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.00:29:47.81$vck44/va=2,6 2006.286.00:29:47.81#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.00:29:47.81#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.00:29:47.81#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:47.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:29:47.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:29:47.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:29:47.87#ibcon#enter wrdev, iclass 34, count 2 2006.286.00:29:47.87#ibcon#first serial, iclass 34, count 2 2006.286.00:29:47.87#ibcon#enter sib2, iclass 34, count 2 2006.286.00:29:47.87#ibcon#flushed, iclass 34, count 2 2006.286.00:29:47.87#ibcon#about to write, iclass 34, count 2 2006.286.00:29:47.87#ibcon#wrote, iclass 34, count 2 2006.286.00:29:47.87#ibcon#about to read 3, iclass 34, count 2 2006.286.00:29:47.89#ibcon#read 3, iclass 34, count 2 2006.286.00:29:47.89#ibcon#about to read 4, iclass 34, count 2 2006.286.00:29:47.89#ibcon#read 4, iclass 34, count 2 2006.286.00:29:47.89#ibcon#about to read 5, iclass 34, count 2 2006.286.00:29:47.89#ibcon#read 5, iclass 34, count 2 2006.286.00:29:47.89#ibcon#about to read 6, iclass 34, count 2 2006.286.00:29:47.89#ibcon#read 6, iclass 34, count 2 2006.286.00:29:47.89#ibcon#end of sib2, iclass 34, count 2 2006.286.00:29:47.89#ibcon#*mode == 0, iclass 34, count 2 2006.286.00:29:47.89#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.00:29:47.89#ibcon#[25=AT02-06\r\n] 2006.286.00:29:47.89#ibcon#*before write, iclass 34, count 2 2006.286.00:29:47.89#ibcon#enter sib2, iclass 34, count 2 2006.286.00:29:47.89#ibcon#flushed, iclass 34, count 2 2006.286.00:29:47.89#ibcon#about to write, iclass 34, count 2 2006.286.00:29:47.89#ibcon#wrote, iclass 34, count 2 2006.286.00:29:47.89#ibcon#about to read 3, iclass 34, count 2 2006.286.00:29:47.92#ibcon#read 3, iclass 34, count 2 2006.286.00:29:47.92#ibcon#about to read 4, iclass 34, count 2 2006.286.00:29:47.92#ibcon#read 4, iclass 34, count 2 2006.286.00:29:47.92#ibcon#about to read 5, iclass 34, count 2 2006.286.00:29:47.92#ibcon#read 5, iclass 34, count 2 2006.286.00:29:47.92#ibcon#about to read 6, iclass 34, count 2 2006.286.00:29:47.92#ibcon#read 6, iclass 34, count 2 2006.286.00:29:47.92#ibcon#end of sib2, iclass 34, count 2 2006.286.00:29:47.92#ibcon#*after write, iclass 34, count 2 2006.286.00:29:47.92#ibcon#*before return 0, iclass 34, count 2 2006.286.00:29:47.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:29:47.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:29:47.92#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.00:29:47.92#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:47.92#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:29:48.04#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:29:48.04#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:29:48.04#ibcon#enter wrdev, iclass 34, count 0 2006.286.00:29:48.04#ibcon#first serial, iclass 34, count 0 2006.286.00:29:48.04#ibcon#enter sib2, iclass 34, count 0 2006.286.00:29:48.04#ibcon#flushed, iclass 34, count 0 2006.286.00:29:48.04#ibcon#about to write, iclass 34, count 0 2006.286.00:29:48.04#ibcon#wrote, iclass 34, count 0 2006.286.00:29:48.04#ibcon#about to read 3, iclass 34, count 0 2006.286.00:29:48.06#ibcon#read 3, iclass 34, count 0 2006.286.00:29:48.06#ibcon#about to read 4, iclass 34, count 0 2006.286.00:29:48.06#ibcon#read 4, iclass 34, count 0 2006.286.00:29:48.06#ibcon#about to read 5, iclass 34, count 0 2006.286.00:29:48.06#ibcon#read 5, iclass 34, count 0 2006.286.00:29:48.06#ibcon#about to read 6, iclass 34, count 0 2006.286.00:29:48.06#ibcon#read 6, iclass 34, count 0 2006.286.00:29:48.06#ibcon#end of sib2, iclass 34, count 0 2006.286.00:29:48.06#ibcon#*mode == 0, iclass 34, count 0 2006.286.00:29:48.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.00:29:48.06#ibcon#[25=USB\r\n] 2006.286.00:29:48.06#ibcon#*before write, iclass 34, count 0 2006.286.00:29:48.06#ibcon#enter sib2, iclass 34, count 0 2006.286.00:29:48.06#ibcon#flushed, iclass 34, count 0 2006.286.00:29:48.06#ibcon#about to write, iclass 34, count 0 2006.286.00:29:48.06#ibcon#wrote, iclass 34, count 0 2006.286.00:29:48.06#ibcon#about to read 3, iclass 34, count 0 2006.286.00:29:48.09#ibcon#read 3, iclass 34, count 0 2006.286.00:29:48.09#ibcon#about to read 4, iclass 34, count 0 2006.286.00:29:48.09#ibcon#read 4, iclass 34, count 0 2006.286.00:29:48.09#ibcon#about to read 5, iclass 34, count 0 2006.286.00:29:48.09#ibcon#read 5, iclass 34, count 0 2006.286.00:29:48.09#ibcon#about to read 6, iclass 34, count 0 2006.286.00:29:48.09#ibcon#read 6, iclass 34, count 0 2006.286.00:29:48.09#ibcon#end of sib2, iclass 34, count 0 2006.286.00:29:48.09#ibcon#*after write, iclass 34, count 0 2006.286.00:29:48.09#ibcon#*before return 0, iclass 34, count 0 2006.286.00:29:48.09#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:29:48.09#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:29:48.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.00:29:48.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.00:29:48.09$vck44/valo=3,564.99 2006.286.00:29:48.09#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.00:29:48.09#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.00:29:48.09#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:48.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:29:48.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:29:48.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:29:48.09#ibcon#enter wrdev, iclass 36, count 0 2006.286.00:29:48.09#ibcon#first serial, iclass 36, count 0 2006.286.00:29:48.09#ibcon#enter sib2, iclass 36, count 0 2006.286.00:29:48.09#ibcon#flushed, iclass 36, count 0 2006.286.00:29:48.09#ibcon#about to write, iclass 36, count 0 2006.286.00:29:48.09#ibcon#wrote, iclass 36, count 0 2006.286.00:29:48.09#ibcon#about to read 3, iclass 36, count 0 2006.286.00:29:48.11#ibcon#read 3, iclass 36, count 0 2006.286.00:29:48.11#ibcon#about to read 4, iclass 36, count 0 2006.286.00:29:48.11#ibcon#read 4, iclass 36, count 0 2006.286.00:29:48.11#ibcon#about to read 5, iclass 36, count 0 2006.286.00:29:48.11#ibcon#read 5, iclass 36, count 0 2006.286.00:29:48.11#ibcon#about to read 6, iclass 36, count 0 2006.286.00:29:48.11#ibcon#read 6, iclass 36, count 0 2006.286.00:29:48.11#ibcon#end of sib2, iclass 36, count 0 2006.286.00:29:48.11#ibcon#*mode == 0, iclass 36, count 0 2006.286.00:29:48.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.00:29:48.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.00:29:48.11#ibcon#*before write, iclass 36, count 0 2006.286.00:29:48.11#ibcon#enter sib2, iclass 36, count 0 2006.286.00:29:48.11#ibcon#flushed, iclass 36, count 0 2006.286.00:29:48.11#ibcon#about to write, iclass 36, count 0 2006.286.00:29:48.11#ibcon#wrote, iclass 36, count 0 2006.286.00:29:48.11#ibcon#about to read 3, iclass 36, count 0 2006.286.00:29:48.15#ibcon#read 3, iclass 36, count 0 2006.286.00:29:48.15#ibcon#about to read 4, iclass 36, count 0 2006.286.00:29:48.15#ibcon#read 4, iclass 36, count 0 2006.286.00:29:48.15#ibcon#about to read 5, iclass 36, count 0 2006.286.00:29:48.15#ibcon#read 5, iclass 36, count 0 2006.286.00:29:48.15#ibcon#about to read 6, iclass 36, count 0 2006.286.00:29:48.15#ibcon#read 6, iclass 36, count 0 2006.286.00:29:48.15#ibcon#end of sib2, iclass 36, count 0 2006.286.00:29:48.15#ibcon#*after write, iclass 36, count 0 2006.286.00:29:48.15#ibcon#*before return 0, iclass 36, count 0 2006.286.00:29:48.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:29:48.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:29:48.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.00:29:48.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.00:29:48.15$vck44/va=3,7 2006.286.00:29:48.15#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.00:29:48.15#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.00:29:48.15#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:48.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:29:48.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:29:48.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:29:48.21#ibcon#enter wrdev, iclass 38, count 2 2006.286.00:29:48.21#ibcon#first serial, iclass 38, count 2 2006.286.00:29:48.21#ibcon#enter sib2, iclass 38, count 2 2006.286.00:29:48.21#ibcon#flushed, iclass 38, count 2 2006.286.00:29:48.21#ibcon#about to write, iclass 38, count 2 2006.286.00:29:48.21#ibcon#wrote, iclass 38, count 2 2006.286.00:29:48.21#ibcon#about to read 3, iclass 38, count 2 2006.286.00:29:48.23#ibcon#read 3, iclass 38, count 2 2006.286.00:29:48.23#ibcon#about to read 4, iclass 38, count 2 2006.286.00:29:48.23#ibcon#read 4, iclass 38, count 2 2006.286.00:29:48.23#ibcon#about to read 5, iclass 38, count 2 2006.286.00:29:48.23#ibcon#read 5, iclass 38, count 2 2006.286.00:29:48.23#ibcon#about to read 6, iclass 38, count 2 2006.286.00:29:48.23#ibcon#read 6, iclass 38, count 2 2006.286.00:29:48.23#ibcon#end of sib2, iclass 38, count 2 2006.286.00:29:48.23#ibcon#*mode == 0, iclass 38, count 2 2006.286.00:29:48.23#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.00:29:48.23#ibcon#[25=AT03-07\r\n] 2006.286.00:29:48.23#ibcon#*before write, iclass 38, count 2 2006.286.00:29:48.23#ibcon#enter sib2, iclass 38, count 2 2006.286.00:29:48.23#ibcon#flushed, iclass 38, count 2 2006.286.00:29:48.23#ibcon#about to write, iclass 38, count 2 2006.286.00:29:48.23#ibcon#wrote, iclass 38, count 2 2006.286.00:29:48.23#ibcon#about to read 3, iclass 38, count 2 2006.286.00:29:48.26#ibcon#read 3, iclass 38, count 2 2006.286.00:29:48.26#ibcon#about to read 4, iclass 38, count 2 2006.286.00:29:48.26#ibcon#read 4, iclass 38, count 2 2006.286.00:29:48.26#ibcon#about to read 5, iclass 38, count 2 2006.286.00:29:48.26#ibcon#read 5, iclass 38, count 2 2006.286.00:29:48.26#ibcon#about to read 6, iclass 38, count 2 2006.286.00:29:48.26#ibcon#read 6, iclass 38, count 2 2006.286.00:29:48.26#ibcon#end of sib2, iclass 38, count 2 2006.286.00:29:48.26#ibcon#*after write, iclass 38, count 2 2006.286.00:29:48.26#ibcon#*before return 0, iclass 38, count 2 2006.286.00:29:48.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:29:48.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:29:48.26#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.00:29:48.26#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:48.26#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:29:48.38#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:29:48.38#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:29:48.38#ibcon#enter wrdev, iclass 38, count 0 2006.286.00:29:48.38#ibcon#first serial, iclass 38, count 0 2006.286.00:29:48.38#ibcon#enter sib2, iclass 38, count 0 2006.286.00:29:48.38#ibcon#flushed, iclass 38, count 0 2006.286.00:29:48.38#ibcon#about to write, iclass 38, count 0 2006.286.00:29:48.38#ibcon#wrote, iclass 38, count 0 2006.286.00:29:48.38#ibcon#about to read 3, iclass 38, count 0 2006.286.00:29:48.40#ibcon#read 3, iclass 38, count 0 2006.286.00:29:48.40#ibcon#about to read 4, iclass 38, count 0 2006.286.00:29:48.40#ibcon#read 4, iclass 38, count 0 2006.286.00:29:48.40#ibcon#about to read 5, iclass 38, count 0 2006.286.00:29:48.40#ibcon#read 5, iclass 38, count 0 2006.286.00:29:48.40#ibcon#about to read 6, iclass 38, count 0 2006.286.00:29:48.40#ibcon#read 6, iclass 38, count 0 2006.286.00:29:48.40#ibcon#end of sib2, iclass 38, count 0 2006.286.00:29:48.40#ibcon#*mode == 0, iclass 38, count 0 2006.286.00:29:48.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.00:29:48.40#ibcon#[25=USB\r\n] 2006.286.00:29:48.40#ibcon#*before write, iclass 38, count 0 2006.286.00:29:48.40#ibcon#enter sib2, iclass 38, count 0 2006.286.00:29:48.40#ibcon#flushed, iclass 38, count 0 2006.286.00:29:48.40#ibcon#about to write, iclass 38, count 0 2006.286.00:29:48.40#ibcon#wrote, iclass 38, count 0 2006.286.00:29:48.40#ibcon#about to read 3, iclass 38, count 0 2006.286.00:29:48.43#ibcon#read 3, iclass 38, count 0 2006.286.00:29:48.43#ibcon#about to read 4, iclass 38, count 0 2006.286.00:29:48.43#ibcon#read 4, iclass 38, count 0 2006.286.00:29:48.43#ibcon#about to read 5, iclass 38, count 0 2006.286.00:29:48.43#ibcon#read 5, iclass 38, count 0 2006.286.00:29:48.43#ibcon#about to read 6, iclass 38, count 0 2006.286.00:29:48.43#ibcon#read 6, iclass 38, count 0 2006.286.00:29:48.43#ibcon#end of sib2, iclass 38, count 0 2006.286.00:29:48.43#ibcon#*after write, iclass 38, count 0 2006.286.00:29:48.43#ibcon#*before return 0, iclass 38, count 0 2006.286.00:29:48.43#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:29:48.43#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:29:48.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.00:29:48.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.00:29:48.43$vck44/valo=4,624.99 2006.286.00:29:48.43#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.00:29:48.43#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.00:29:48.43#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:48.43#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:29:48.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:29:48.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:29:48.43#ibcon#enter wrdev, iclass 40, count 0 2006.286.00:29:48.43#ibcon#first serial, iclass 40, count 0 2006.286.00:29:48.43#ibcon#enter sib2, iclass 40, count 0 2006.286.00:29:48.43#ibcon#flushed, iclass 40, count 0 2006.286.00:29:48.43#ibcon#about to write, iclass 40, count 0 2006.286.00:29:48.43#ibcon#wrote, iclass 40, count 0 2006.286.00:29:48.43#ibcon#about to read 3, iclass 40, count 0 2006.286.00:29:48.45#ibcon#read 3, iclass 40, count 0 2006.286.00:29:48.45#ibcon#about to read 4, iclass 40, count 0 2006.286.00:29:48.45#ibcon#read 4, iclass 40, count 0 2006.286.00:29:48.45#ibcon#about to read 5, iclass 40, count 0 2006.286.00:29:48.45#ibcon#read 5, iclass 40, count 0 2006.286.00:29:48.45#ibcon#about to read 6, iclass 40, count 0 2006.286.00:29:48.45#ibcon#read 6, iclass 40, count 0 2006.286.00:29:48.45#ibcon#end of sib2, iclass 40, count 0 2006.286.00:29:48.45#ibcon#*mode == 0, iclass 40, count 0 2006.286.00:29:48.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.00:29:48.45#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.00:29:48.45#ibcon#*before write, iclass 40, count 0 2006.286.00:29:48.45#ibcon#enter sib2, iclass 40, count 0 2006.286.00:29:48.45#ibcon#flushed, iclass 40, count 0 2006.286.00:29:48.45#ibcon#about to write, iclass 40, count 0 2006.286.00:29:48.45#ibcon#wrote, iclass 40, count 0 2006.286.00:29:48.45#ibcon#about to read 3, iclass 40, count 0 2006.286.00:29:48.49#ibcon#read 3, iclass 40, count 0 2006.286.00:29:48.49#ibcon#about to read 4, iclass 40, count 0 2006.286.00:29:48.49#ibcon#read 4, iclass 40, count 0 2006.286.00:29:48.49#ibcon#about to read 5, iclass 40, count 0 2006.286.00:29:48.49#ibcon#read 5, iclass 40, count 0 2006.286.00:29:48.49#ibcon#about to read 6, iclass 40, count 0 2006.286.00:29:48.49#ibcon#read 6, iclass 40, count 0 2006.286.00:29:48.49#ibcon#end of sib2, iclass 40, count 0 2006.286.00:29:48.49#ibcon#*after write, iclass 40, count 0 2006.286.00:29:48.49#ibcon#*before return 0, iclass 40, count 0 2006.286.00:29:48.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:29:48.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:29:48.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.00:29:48.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.00:29:48.49$vck44/va=4,6 2006.286.00:29:48.49#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.00:29:48.49#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.00:29:48.49#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:48.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:29:48.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:29:48.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:29:48.55#ibcon#enter wrdev, iclass 4, count 2 2006.286.00:29:48.55#ibcon#first serial, iclass 4, count 2 2006.286.00:29:48.55#ibcon#enter sib2, iclass 4, count 2 2006.286.00:29:48.55#ibcon#flushed, iclass 4, count 2 2006.286.00:29:48.55#ibcon#about to write, iclass 4, count 2 2006.286.00:29:48.55#ibcon#wrote, iclass 4, count 2 2006.286.00:29:48.55#ibcon#about to read 3, iclass 4, count 2 2006.286.00:29:48.57#ibcon#read 3, iclass 4, count 2 2006.286.00:29:48.57#ibcon#about to read 4, iclass 4, count 2 2006.286.00:29:48.57#ibcon#read 4, iclass 4, count 2 2006.286.00:29:48.57#ibcon#about to read 5, iclass 4, count 2 2006.286.00:29:48.57#ibcon#read 5, iclass 4, count 2 2006.286.00:29:48.57#ibcon#about to read 6, iclass 4, count 2 2006.286.00:29:48.57#ibcon#read 6, iclass 4, count 2 2006.286.00:29:48.57#ibcon#end of sib2, iclass 4, count 2 2006.286.00:29:48.57#ibcon#*mode == 0, iclass 4, count 2 2006.286.00:29:48.57#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.00:29:48.57#ibcon#[25=AT04-06\r\n] 2006.286.00:29:48.57#ibcon#*before write, iclass 4, count 2 2006.286.00:29:48.57#ibcon#enter sib2, iclass 4, count 2 2006.286.00:29:48.57#ibcon#flushed, iclass 4, count 2 2006.286.00:29:48.57#ibcon#about to write, iclass 4, count 2 2006.286.00:29:48.57#ibcon#wrote, iclass 4, count 2 2006.286.00:29:48.57#ibcon#about to read 3, iclass 4, count 2 2006.286.00:29:48.60#ibcon#read 3, iclass 4, count 2 2006.286.00:29:48.60#ibcon#about to read 4, iclass 4, count 2 2006.286.00:29:48.60#ibcon#read 4, iclass 4, count 2 2006.286.00:29:48.60#ibcon#about to read 5, iclass 4, count 2 2006.286.00:29:48.60#ibcon#read 5, iclass 4, count 2 2006.286.00:29:48.60#ibcon#about to read 6, iclass 4, count 2 2006.286.00:29:48.60#ibcon#read 6, iclass 4, count 2 2006.286.00:29:48.60#ibcon#end of sib2, iclass 4, count 2 2006.286.00:29:48.60#ibcon#*after write, iclass 4, count 2 2006.286.00:29:48.60#ibcon#*before return 0, iclass 4, count 2 2006.286.00:29:48.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:29:48.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:29:48.60#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.00:29:48.60#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:48.60#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:29:48.72#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:29:48.72#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:29:48.72#ibcon#enter wrdev, iclass 4, count 0 2006.286.00:29:48.72#ibcon#first serial, iclass 4, count 0 2006.286.00:29:48.72#ibcon#enter sib2, iclass 4, count 0 2006.286.00:29:48.72#ibcon#flushed, iclass 4, count 0 2006.286.00:29:48.72#ibcon#about to write, iclass 4, count 0 2006.286.00:29:48.72#ibcon#wrote, iclass 4, count 0 2006.286.00:29:48.72#ibcon#about to read 3, iclass 4, count 0 2006.286.00:29:48.74#ibcon#read 3, iclass 4, count 0 2006.286.00:29:48.74#ibcon#about to read 4, iclass 4, count 0 2006.286.00:29:48.74#ibcon#read 4, iclass 4, count 0 2006.286.00:29:48.74#ibcon#about to read 5, iclass 4, count 0 2006.286.00:29:48.74#ibcon#read 5, iclass 4, count 0 2006.286.00:29:48.74#ibcon#about to read 6, iclass 4, count 0 2006.286.00:29:48.74#ibcon#read 6, iclass 4, count 0 2006.286.00:29:48.74#ibcon#end of sib2, iclass 4, count 0 2006.286.00:29:48.74#ibcon#*mode == 0, iclass 4, count 0 2006.286.00:29:48.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.00:29:48.74#ibcon#[25=USB\r\n] 2006.286.00:29:48.74#ibcon#*before write, iclass 4, count 0 2006.286.00:29:48.74#ibcon#enter sib2, iclass 4, count 0 2006.286.00:29:48.74#ibcon#flushed, iclass 4, count 0 2006.286.00:29:48.74#ibcon#about to write, iclass 4, count 0 2006.286.00:29:48.74#ibcon#wrote, iclass 4, count 0 2006.286.00:29:48.74#ibcon#about to read 3, iclass 4, count 0 2006.286.00:29:48.77#ibcon#read 3, iclass 4, count 0 2006.286.00:29:48.77#ibcon#about to read 4, iclass 4, count 0 2006.286.00:29:48.77#ibcon#read 4, iclass 4, count 0 2006.286.00:29:48.77#ibcon#about to read 5, iclass 4, count 0 2006.286.00:29:48.77#ibcon#read 5, iclass 4, count 0 2006.286.00:29:48.77#ibcon#about to read 6, iclass 4, count 0 2006.286.00:29:48.77#ibcon#read 6, iclass 4, count 0 2006.286.00:29:48.77#ibcon#end of sib2, iclass 4, count 0 2006.286.00:29:48.77#ibcon#*after write, iclass 4, count 0 2006.286.00:29:48.77#ibcon#*before return 0, iclass 4, count 0 2006.286.00:29:48.77#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:29:48.77#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:29:48.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.00:29:48.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.00:29:48.77$vck44/valo=5,734.99 2006.286.00:29:48.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.00:29:48.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.00:29:48.77#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:48.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:29:48.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:29:48.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:29:48.77#ibcon#enter wrdev, iclass 6, count 0 2006.286.00:29:48.77#ibcon#first serial, iclass 6, count 0 2006.286.00:29:48.77#ibcon#enter sib2, iclass 6, count 0 2006.286.00:29:48.77#ibcon#flushed, iclass 6, count 0 2006.286.00:29:48.77#ibcon#about to write, iclass 6, count 0 2006.286.00:29:48.77#ibcon#wrote, iclass 6, count 0 2006.286.00:29:48.77#ibcon#about to read 3, iclass 6, count 0 2006.286.00:29:48.79#ibcon#read 3, iclass 6, count 0 2006.286.00:29:48.79#ibcon#about to read 4, iclass 6, count 0 2006.286.00:29:48.79#ibcon#read 4, iclass 6, count 0 2006.286.00:29:48.79#ibcon#about to read 5, iclass 6, count 0 2006.286.00:29:48.79#ibcon#read 5, iclass 6, count 0 2006.286.00:29:48.79#ibcon#about to read 6, iclass 6, count 0 2006.286.00:29:48.79#ibcon#read 6, iclass 6, count 0 2006.286.00:29:48.79#ibcon#end of sib2, iclass 6, count 0 2006.286.00:29:48.79#ibcon#*mode == 0, iclass 6, count 0 2006.286.00:29:48.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.00:29:48.79#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.00:29:48.79#ibcon#*before write, iclass 6, count 0 2006.286.00:29:48.79#ibcon#enter sib2, iclass 6, count 0 2006.286.00:29:48.79#ibcon#flushed, iclass 6, count 0 2006.286.00:29:48.79#ibcon#about to write, iclass 6, count 0 2006.286.00:29:48.79#ibcon#wrote, iclass 6, count 0 2006.286.00:29:48.79#ibcon#about to read 3, iclass 6, count 0 2006.286.00:29:48.83#ibcon#read 3, iclass 6, count 0 2006.286.00:29:48.83#ibcon#about to read 4, iclass 6, count 0 2006.286.00:29:48.83#ibcon#read 4, iclass 6, count 0 2006.286.00:29:48.83#ibcon#about to read 5, iclass 6, count 0 2006.286.00:29:48.83#ibcon#read 5, iclass 6, count 0 2006.286.00:29:48.83#ibcon#about to read 6, iclass 6, count 0 2006.286.00:29:48.83#ibcon#read 6, iclass 6, count 0 2006.286.00:29:48.83#ibcon#end of sib2, iclass 6, count 0 2006.286.00:29:48.83#ibcon#*after write, iclass 6, count 0 2006.286.00:29:48.83#ibcon#*before return 0, iclass 6, count 0 2006.286.00:29:48.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:29:48.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:29:48.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.00:29:48.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.00:29:48.83$vck44/va=5,3 2006.286.00:29:48.83#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.00:29:48.83#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.00:29:48.83#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:48.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:29:48.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:29:48.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:29:48.89#ibcon#enter wrdev, iclass 10, count 2 2006.286.00:29:48.89#ibcon#first serial, iclass 10, count 2 2006.286.00:29:48.89#ibcon#enter sib2, iclass 10, count 2 2006.286.00:29:48.89#ibcon#flushed, iclass 10, count 2 2006.286.00:29:48.89#ibcon#about to write, iclass 10, count 2 2006.286.00:29:48.89#ibcon#wrote, iclass 10, count 2 2006.286.00:29:48.89#ibcon#about to read 3, iclass 10, count 2 2006.286.00:29:48.91#ibcon#read 3, iclass 10, count 2 2006.286.00:29:48.91#ibcon#about to read 4, iclass 10, count 2 2006.286.00:29:48.91#ibcon#read 4, iclass 10, count 2 2006.286.00:29:48.91#ibcon#about to read 5, iclass 10, count 2 2006.286.00:29:48.91#ibcon#read 5, iclass 10, count 2 2006.286.00:29:48.91#ibcon#about to read 6, iclass 10, count 2 2006.286.00:29:48.91#ibcon#read 6, iclass 10, count 2 2006.286.00:29:48.91#ibcon#end of sib2, iclass 10, count 2 2006.286.00:29:48.91#ibcon#*mode == 0, iclass 10, count 2 2006.286.00:29:48.91#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.00:29:48.91#ibcon#[25=AT05-03\r\n] 2006.286.00:29:48.91#ibcon#*before write, iclass 10, count 2 2006.286.00:29:48.91#ibcon#enter sib2, iclass 10, count 2 2006.286.00:29:48.91#ibcon#flushed, iclass 10, count 2 2006.286.00:29:48.91#ibcon#about to write, iclass 10, count 2 2006.286.00:29:48.91#ibcon#wrote, iclass 10, count 2 2006.286.00:29:48.91#ibcon#about to read 3, iclass 10, count 2 2006.286.00:29:48.94#ibcon#read 3, iclass 10, count 2 2006.286.00:29:48.94#ibcon#about to read 4, iclass 10, count 2 2006.286.00:29:48.94#ibcon#read 4, iclass 10, count 2 2006.286.00:29:48.94#ibcon#about to read 5, iclass 10, count 2 2006.286.00:29:48.94#ibcon#read 5, iclass 10, count 2 2006.286.00:29:48.94#ibcon#about to read 6, iclass 10, count 2 2006.286.00:29:48.94#ibcon#read 6, iclass 10, count 2 2006.286.00:29:48.94#ibcon#end of sib2, iclass 10, count 2 2006.286.00:29:48.94#ibcon#*after write, iclass 10, count 2 2006.286.00:29:48.94#ibcon#*before return 0, iclass 10, count 2 2006.286.00:29:48.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:29:48.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:29:48.94#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.00:29:48.94#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:48.94#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:29:49.06#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:29:49.06#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:29:49.06#ibcon#enter wrdev, iclass 10, count 0 2006.286.00:29:49.06#ibcon#first serial, iclass 10, count 0 2006.286.00:29:49.06#ibcon#enter sib2, iclass 10, count 0 2006.286.00:29:49.06#ibcon#flushed, iclass 10, count 0 2006.286.00:29:49.06#ibcon#about to write, iclass 10, count 0 2006.286.00:29:49.06#ibcon#wrote, iclass 10, count 0 2006.286.00:29:49.06#ibcon#about to read 3, iclass 10, count 0 2006.286.00:29:49.08#ibcon#read 3, iclass 10, count 0 2006.286.00:29:49.08#ibcon#about to read 4, iclass 10, count 0 2006.286.00:29:49.08#ibcon#read 4, iclass 10, count 0 2006.286.00:29:49.08#ibcon#about to read 5, iclass 10, count 0 2006.286.00:29:49.08#ibcon#read 5, iclass 10, count 0 2006.286.00:29:49.08#ibcon#about to read 6, iclass 10, count 0 2006.286.00:29:49.08#ibcon#read 6, iclass 10, count 0 2006.286.00:29:49.08#ibcon#end of sib2, iclass 10, count 0 2006.286.00:29:49.08#ibcon#*mode == 0, iclass 10, count 0 2006.286.00:29:49.08#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.00:29:49.08#ibcon#[25=USB\r\n] 2006.286.00:29:49.08#ibcon#*before write, iclass 10, count 0 2006.286.00:29:49.08#ibcon#enter sib2, iclass 10, count 0 2006.286.00:29:49.08#ibcon#flushed, iclass 10, count 0 2006.286.00:29:49.08#ibcon#about to write, iclass 10, count 0 2006.286.00:29:49.08#ibcon#wrote, iclass 10, count 0 2006.286.00:29:49.08#ibcon#about to read 3, iclass 10, count 0 2006.286.00:29:49.11#ibcon#read 3, iclass 10, count 0 2006.286.00:29:49.11#ibcon#about to read 4, iclass 10, count 0 2006.286.00:29:49.11#ibcon#read 4, iclass 10, count 0 2006.286.00:29:49.11#ibcon#about to read 5, iclass 10, count 0 2006.286.00:29:49.11#ibcon#read 5, iclass 10, count 0 2006.286.00:29:49.11#ibcon#about to read 6, iclass 10, count 0 2006.286.00:29:49.11#ibcon#read 6, iclass 10, count 0 2006.286.00:29:49.11#ibcon#end of sib2, iclass 10, count 0 2006.286.00:29:49.11#ibcon#*after write, iclass 10, count 0 2006.286.00:29:49.11#ibcon#*before return 0, iclass 10, count 0 2006.286.00:29:49.11#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:29:49.11#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:29:49.11#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.00:29:49.11#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.00:29:49.11$vck44/valo=6,814.99 2006.286.00:29:49.11#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.00:29:49.11#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.00:29:49.11#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:49.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:29:49.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:29:49.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:29:49.11#ibcon#enter wrdev, iclass 12, count 0 2006.286.00:29:49.11#ibcon#first serial, iclass 12, count 0 2006.286.00:29:49.11#ibcon#enter sib2, iclass 12, count 0 2006.286.00:29:49.11#ibcon#flushed, iclass 12, count 0 2006.286.00:29:49.11#ibcon#about to write, iclass 12, count 0 2006.286.00:29:49.11#ibcon#wrote, iclass 12, count 0 2006.286.00:29:49.11#ibcon#about to read 3, iclass 12, count 0 2006.286.00:29:49.13#ibcon#read 3, iclass 12, count 0 2006.286.00:29:49.13#ibcon#about to read 4, iclass 12, count 0 2006.286.00:29:49.13#ibcon#read 4, iclass 12, count 0 2006.286.00:29:49.13#ibcon#about to read 5, iclass 12, count 0 2006.286.00:29:49.13#ibcon#read 5, iclass 12, count 0 2006.286.00:29:49.13#ibcon#about to read 6, iclass 12, count 0 2006.286.00:29:49.13#ibcon#read 6, iclass 12, count 0 2006.286.00:29:49.13#ibcon#end of sib2, iclass 12, count 0 2006.286.00:29:49.13#ibcon#*mode == 0, iclass 12, count 0 2006.286.00:29:49.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.00:29:49.13#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.00:29:49.13#ibcon#*before write, iclass 12, count 0 2006.286.00:29:49.13#ibcon#enter sib2, iclass 12, count 0 2006.286.00:29:49.13#ibcon#flushed, iclass 12, count 0 2006.286.00:29:49.13#ibcon#about to write, iclass 12, count 0 2006.286.00:29:49.13#ibcon#wrote, iclass 12, count 0 2006.286.00:29:49.13#ibcon#about to read 3, iclass 12, count 0 2006.286.00:29:49.17#ibcon#read 3, iclass 12, count 0 2006.286.00:29:49.17#ibcon#about to read 4, iclass 12, count 0 2006.286.00:29:49.17#ibcon#read 4, iclass 12, count 0 2006.286.00:29:49.17#ibcon#about to read 5, iclass 12, count 0 2006.286.00:29:49.17#ibcon#read 5, iclass 12, count 0 2006.286.00:29:49.17#ibcon#about to read 6, iclass 12, count 0 2006.286.00:29:49.17#ibcon#read 6, iclass 12, count 0 2006.286.00:29:49.17#ibcon#end of sib2, iclass 12, count 0 2006.286.00:29:49.17#ibcon#*after write, iclass 12, count 0 2006.286.00:29:49.17#ibcon#*before return 0, iclass 12, count 0 2006.286.00:29:49.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:29:49.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:29:49.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.00:29:49.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.00:29:49.17$vck44/va=6,4 2006.286.00:29:49.17#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.00:29:49.17#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.00:29:49.17#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:49.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:29:49.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:29:49.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:29:49.23#ibcon#enter wrdev, iclass 14, count 2 2006.286.00:29:49.23#ibcon#first serial, iclass 14, count 2 2006.286.00:29:49.23#ibcon#enter sib2, iclass 14, count 2 2006.286.00:29:49.23#ibcon#flushed, iclass 14, count 2 2006.286.00:29:49.23#ibcon#about to write, iclass 14, count 2 2006.286.00:29:49.23#ibcon#wrote, iclass 14, count 2 2006.286.00:29:49.23#ibcon#about to read 3, iclass 14, count 2 2006.286.00:29:49.25#ibcon#read 3, iclass 14, count 2 2006.286.00:29:49.25#ibcon#about to read 4, iclass 14, count 2 2006.286.00:29:49.25#ibcon#read 4, iclass 14, count 2 2006.286.00:29:49.25#ibcon#about to read 5, iclass 14, count 2 2006.286.00:29:49.25#ibcon#read 5, iclass 14, count 2 2006.286.00:29:49.25#ibcon#about to read 6, iclass 14, count 2 2006.286.00:29:49.25#ibcon#read 6, iclass 14, count 2 2006.286.00:29:49.25#ibcon#end of sib2, iclass 14, count 2 2006.286.00:29:49.25#ibcon#*mode == 0, iclass 14, count 2 2006.286.00:29:49.25#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.00:29:49.25#ibcon#[25=AT06-04\r\n] 2006.286.00:29:49.25#ibcon#*before write, iclass 14, count 2 2006.286.00:29:49.25#ibcon#enter sib2, iclass 14, count 2 2006.286.00:29:49.25#ibcon#flushed, iclass 14, count 2 2006.286.00:29:49.25#ibcon#about to write, iclass 14, count 2 2006.286.00:29:49.25#ibcon#wrote, iclass 14, count 2 2006.286.00:29:49.25#ibcon#about to read 3, iclass 14, count 2 2006.286.00:29:49.28#ibcon#read 3, iclass 14, count 2 2006.286.00:29:49.28#ibcon#about to read 4, iclass 14, count 2 2006.286.00:29:49.28#ibcon#read 4, iclass 14, count 2 2006.286.00:29:49.28#ibcon#about to read 5, iclass 14, count 2 2006.286.00:29:49.28#ibcon#read 5, iclass 14, count 2 2006.286.00:29:49.28#ibcon#about to read 6, iclass 14, count 2 2006.286.00:29:49.28#ibcon#read 6, iclass 14, count 2 2006.286.00:29:49.28#ibcon#end of sib2, iclass 14, count 2 2006.286.00:29:49.28#ibcon#*after write, iclass 14, count 2 2006.286.00:29:49.28#ibcon#*before return 0, iclass 14, count 2 2006.286.00:29:49.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:29:49.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:29:49.28#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.00:29:49.28#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:49.28#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:29:49.40#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:29:49.40#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:29:49.40#ibcon#enter wrdev, iclass 14, count 0 2006.286.00:29:49.40#ibcon#first serial, iclass 14, count 0 2006.286.00:29:49.40#ibcon#enter sib2, iclass 14, count 0 2006.286.00:29:49.40#ibcon#flushed, iclass 14, count 0 2006.286.00:29:49.40#ibcon#about to write, iclass 14, count 0 2006.286.00:29:49.40#ibcon#wrote, iclass 14, count 0 2006.286.00:29:49.40#ibcon#about to read 3, iclass 14, count 0 2006.286.00:29:49.42#ibcon#read 3, iclass 14, count 0 2006.286.00:29:49.42#ibcon#about to read 4, iclass 14, count 0 2006.286.00:29:49.42#ibcon#read 4, iclass 14, count 0 2006.286.00:29:49.42#ibcon#about to read 5, iclass 14, count 0 2006.286.00:29:49.42#ibcon#read 5, iclass 14, count 0 2006.286.00:29:49.42#ibcon#about to read 6, iclass 14, count 0 2006.286.00:29:49.42#ibcon#read 6, iclass 14, count 0 2006.286.00:29:49.42#ibcon#end of sib2, iclass 14, count 0 2006.286.00:29:49.42#ibcon#*mode == 0, iclass 14, count 0 2006.286.00:29:49.42#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.00:29:49.42#ibcon#[25=USB\r\n] 2006.286.00:29:49.42#ibcon#*before write, iclass 14, count 0 2006.286.00:29:49.42#ibcon#enter sib2, iclass 14, count 0 2006.286.00:29:49.42#ibcon#flushed, iclass 14, count 0 2006.286.00:29:49.42#ibcon#about to write, iclass 14, count 0 2006.286.00:29:49.42#ibcon#wrote, iclass 14, count 0 2006.286.00:29:49.42#ibcon#about to read 3, iclass 14, count 0 2006.286.00:29:49.45#ibcon#read 3, iclass 14, count 0 2006.286.00:29:49.45#ibcon#about to read 4, iclass 14, count 0 2006.286.00:29:49.45#ibcon#read 4, iclass 14, count 0 2006.286.00:29:49.45#ibcon#about to read 5, iclass 14, count 0 2006.286.00:29:49.45#ibcon#read 5, iclass 14, count 0 2006.286.00:29:49.45#ibcon#about to read 6, iclass 14, count 0 2006.286.00:29:49.45#ibcon#read 6, iclass 14, count 0 2006.286.00:29:49.45#ibcon#end of sib2, iclass 14, count 0 2006.286.00:29:49.45#ibcon#*after write, iclass 14, count 0 2006.286.00:29:49.45#ibcon#*before return 0, iclass 14, count 0 2006.286.00:29:49.45#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:29:49.45#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:29:49.45#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.00:29:49.45#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.00:29:49.45$vck44/valo=7,864.99 2006.286.00:29:49.45#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.00:29:49.45#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.00:29:49.45#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:49.45#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:29:49.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:29:49.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:29:49.45#ibcon#enter wrdev, iclass 16, count 0 2006.286.00:29:49.45#ibcon#first serial, iclass 16, count 0 2006.286.00:29:49.45#ibcon#enter sib2, iclass 16, count 0 2006.286.00:29:49.45#ibcon#flushed, iclass 16, count 0 2006.286.00:29:49.45#ibcon#about to write, iclass 16, count 0 2006.286.00:29:49.45#ibcon#wrote, iclass 16, count 0 2006.286.00:29:49.45#ibcon#about to read 3, iclass 16, count 0 2006.286.00:29:49.47#ibcon#read 3, iclass 16, count 0 2006.286.00:29:49.47#ibcon#about to read 4, iclass 16, count 0 2006.286.00:29:49.47#ibcon#read 4, iclass 16, count 0 2006.286.00:29:49.47#ibcon#about to read 5, iclass 16, count 0 2006.286.00:29:49.47#ibcon#read 5, iclass 16, count 0 2006.286.00:29:49.47#ibcon#about to read 6, iclass 16, count 0 2006.286.00:29:49.47#ibcon#read 6, iclass 16, count 0 2006.286.00:29:49.47#ibcon#end of sib2, iclass 16, count 0 2006.286.00:29:49.47#ibcon#*mode == 0, iclass 16, count 0 2006.286.00:29:49.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.00:29:49.47#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.00:29:49.47#ibcon#*before write, iclass 16, count 0 2006.286.00:29:49.47#ibcon#enter sib2, iclass 16, count 0 2006.286.00:29:49.47#ibcon#flushed, iclass 16, count 0 2006.286.00:29:49.47#ibcon#about to write, iclass 16, count 0 2006.286.00:29:49.47#ibcon#wrote, iclass 16, count 0 2006.286.00:29:49.47#ibcon#about to read 3, iclass 16, count 0 2006.286.00:29:49.51#ibcon#read 3, iclass 16, count 0 2006.286.00:29:49.51#ibcon#about to read 4, iclass 16, count 0 2006.286.00:29:49.51#ibcon#read 4, iclass 16, count 0 2006.286.00:29:49.51#ibcon#about to read 5, iclass 16, count 0 2006.286.00:29:49.51#ibcon#read 5, iclass 16, count 0 2006.286.00:29:49.51#ibcon#about to read 6, iclass 16, count 0 2006.286.00:29:49.51#ibcon#read 6, iclass 16, count 0 2006.286.00:29:49.51#ibcon#end of sib2, iclass 16, count 0 2006.286.00:29:49.51#ibcon#*after write, iclass 16, count 0 2006.286.00:29:49.51#ibcon#*before return 0, iclass 16, count 0 2006.286.00:29:49.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:29:49.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:29:49.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.00:29:49.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.00:29:49.51$vck44/va=7,4 2006.286.00:29:49.51#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.00:29:49.51#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.00:29:49.51#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:49.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:29:49.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:29:49.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:29:49.57#ibcon#enter wrdev, iclass 18, count 2 2006.286.00:29:49.57#ibcon#first serial, iclass 18, count 2 2006.286.00:29:49.57#ibcon#enter sib2, iclass 18, count 2 2006.286.00:29:49.57#ibcon#flushed, iclass 18, count 2 2006.286.00:29:49.57#ibcon#about to write, iclass 18, count 2 2006.286.00:29:49.57#ibcon#wrote, iclass 18, count 2 2006.286.00:29:49.57#ibcon#about to read 3, iclass 18, count 2 2006.286.00:29:49.59#ibcon#read 3, iclass 18, count 2 2006.286.00:29:49.59#ibcon#about to read 4, iclass 18, count 2 2006.286.00:29:49.59#ibcon#read 4, iclass 18, count 2 2006.286.00:29:49.59#ibcon#about to read 5, iclass 18, count 2 2006.286.00:29:49.59#ibcon#read 5, iclass 18, count 2 2006.286.00:29:49.59#ibcon#about to read 6, iclass 18, count 2 2006.286.00:29:49.59#ibcon#read 6, iclass 18, count 2 2006.286.00:29:49.59#ibcon#end of sib2, iclass 18, count 2 2006.286.00:29:49.59#ibcon#*mode == 0, iclass 18, count 2 2006.286.00:29:49.59#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.00:29:49.59#ibcon#[25=AT07-04\r\n] 2006.286.00:29:49.59#ibcon#*before write, iclass 18, count 2 2006.286.00:29:49.59#ibcon#enter sib2, iclass 18, count 2 2006.286.00:29:49.59#ibcon#flushed, iclass 18, count 2 2006.286.00:29:49.59#ibcon#about to write, iclass 18, count 2 2006.286.00:29:49.59#ibcon#wrote, iclass 18, count 2 2006.286.00:29:49.59#ibcon#about to read 3, iclass 18, count 2 2006.286.00:29:49.62#ibcon#read 3, iclass 18, count 2 2006.286.00:29:49.62#ibcon#about to read 4, iclass 18, count 2 2006.286.00:29:49.62#ibcon#read 4, iclass 18, count 2 2006.286.00:29:49.62#ibcon#about to read 5, iclass 18, count 2 2006.286.00:29:49.62#ibcon#read 5, iclass 18, count 2 2006.286.00:29:49.62#ibcon#about to read 6, iclass 18, count 2 2006.286.00:29:49.62#ibcon#read 6, iclass 18, count 2 2006.286.00:29:49.62#ibcon#end of sib2, iclass 18, count 2 2006.286.00:29:49.62#ibcon#*after write, iclass 18, count 2 2006.286.00:29:49.62#ibcon#*before return 0, iclass 18, count 2 2006.286.00:29:49.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:29:49.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:29:49.62#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.00:29:49.62#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:49.62#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:29:49.74#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:29:49.74#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:29:49.74#ibcon#enter wrdev, iclass 18, count 0 2006.286.00:29:49.74#ibcon#first serial, iclass 18, count 0 2006.286.00:29:49.74#ibcon#enter sib2, iclass 18, count 0 2006.286.00:29:49.74#ibcon#flushed, iclass 18, count 0 2006.286.00:29:49.74#ibcon#about to write, iclass 18, count 0 2006.286.00:29:49.74#ibcon#wrote, iclass 18, count 0 2006.286.00:29:49.74#ibcon#about to read 3, iclass 18, count 0 2006.286.00:29:49.76#ibcon#read 3, iclass 18, count 0 2006.286.00:29:49.76#ibcon#about to read 4, iclass 18, count 0 2006.286.00:29:49.76#ibcon#read 4, iclass 18, count 0 2006.286.00:29:49.76#ibcon#about to read 5, iclass 18, count 0 2006.286.00:29:49.76#ibcon#read 5, iclass 18, count 0 2006.286.00:29:49.76#ibcon#about to read 6, iclass 18, count 0 2006.286.00:29:49.76#ibcon#read 6, iclass 18, count 0 2006.286.00:29:49.76#ibcon#end of sib2, iclass 18, count 0 2006.286.00:29:49.76#ibcon#*mode == 0, iclass 18, count 0 2006.286.00:29:49.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.00:29:49.76#ibcon#[25=USB\r\n] 2006.286.00:29:49.76#ibcon#*before write, iclass 18, count 0 2006.286.00:29:49.76#ibcon#enter sib2, iclass 18, count 0 2006.286.00:29:49.76#ibcon#flushed, iclass 18, count 0 2006.286.00:29:49.76#ibcon#about to write, iclass 18, count 0 2006.286.00:29:49.76#ibcon#wrote, iclass 18, count 0 2006.286.00:29:49.76#ibcon#about to read 3, iclass 18, count 0 2006.286.00:29:49.79#ibcon#read 3, iclass 18, count 0 2006.286.00:29:49.79#ibcon#about to read 4, iclass 18, count 0 2006.286.00:29:49.79#ibcon#read 4, iclass 18, count 0 2006.286.00:29:49.79#ibcon#about to read 5, iclass 18, count 0 2006.286.00:29:49.79#ibcon#read 5, iclass 18, count 0 2006.286.00:29:49.79#ibcon#about to read 6, iclass 18, count 0 2006.286.00:29:49.79#ibcon#read 6, iclass 18, count 0 2006.286.00:29:49.79#ibcon#end of sib2, iclass 18, count 0 2006.286.00:29:49.79#ibcon#*after write, iclass 18, count 0 2006.286.00:29:49.79#ibcon#*before return 0, iclass 18, count 0 2006.286.00:29:49.79#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:29:49.79#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:29:49.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.00:29:49.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.00:29:49.79$vck44/valo=8,884.99 2006.286.00:29:49.79#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.00:29:49.79#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.00:29:49.79#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:49.79#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.00:29:49.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.00:29:49.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.00:29:49.79#ibcon#enter wrdev, iclass 20, count 0 2006.286.00:29:49.79#ibcon#first serial, iclass 20, count 0 2006.286.00:29:49.79#ibcon#enter sib2, iclass 20, count 0 2006.286.00:29:49.79#ibcon#flushed, iclass 20, count 0 2006.286.00:29:49.79#ibcon#about to write, iclass 20, count 0 2006.286.00:29:49.79#ibcon#wrote, iclass 20, count 0 2006.286.00:29:49.79#ibcon#about to read 3, iclass 20, count 0 2006.286.00:29:49.81#ibcon#read 3, iclass 20, count 0 2006.286.00:29:49.81#ibcon#about to read 4, iclass 20, count 0 2006.286.00:29:49.81#ibcon#read 4, iclass 20, count 0 2006.286.00:29:49.81#ibcon#about to read 5, iclass 20, count 0 2006.286.00:29:49.81#ibcon#read 5, iclass 20, count 0 2006.286.00:29:49.81#ibcon#about to read 6, iclass 20, count 0 2006.286.00:29:49.81#ibcon#read 6, iclass 20, count 0 2006.286.00:29:49.81#ibcon#end of sib2, iclass 20, count 0 2006.286.00:29:49.81#ibcon#*mode == 0, iclass 20, count 0 2006.286.00:29:49.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.00:29:49.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.00:29:49.81#ibcon#*before write, iclass 20, count 0 2006.286.00:29:49.81#ibcon#enter sib2, iclass 20, count 0 2006.286.00:29:49.81#ibcon#flushed, iclass 20, count 0 2006.286.00:29:49.81#ibcon#about to write, iclass 20, count 0 2006.286.00:29:49.81#ibcon#wrote, iclass 20, count 0 2006.286.00:29:49.81#ibcon#about to read 3, iclass 20, count 0 2006.286.00:29:49.85#ibcon#read 3, iclass 20, count 0 2006.286.00:29:49.85#ibcon#about to read 4, iclass 20, count 0 2006.286.00:29:49.85#ibcon#read 4, iclass 20, count 0 2006.286.00:29:49.85#ibcon#about to read 5, iclass 20, count 0 2006.286.00:29:49.85#ibcon#read 5, iclass 20, count 0 2006.286.00:29:49.85#ibcon#about to read 6, iclass 20, count 0 2006.286.00:29:49.85#ibcon#read 6, iclass 20, count 0 2006.286.00:29:49.85#ibcon#end of sib2, iclass 20, count 0 2006.286.00:29:49.85#ibcon#*after write, iclass 20, count 0 2006.286.00:29:49.85#ibcon#*before return 0, iclass 20, count 0 2006.286.00:29:49.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.00:29:49.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.00:29:49.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.00:29:49.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.00:29:49.85$vck44/va=8,3 2006.286.00:29:49.85#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.00:29:49.85#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.00:29:49.85#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:49.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.00:29:49.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.00:29:49.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.00:29:49.91#ibcon#enter wrdev, iclass 22, count 2 2006.286.00:29:49.91#ibcon#first serial, iclass 22, count 2 2006.286.00:29:49.91#ibcon#enter sib2, iclass 22, count 2 2006.286.00:29:49.91#ibcon#flushed, iclass 22, count 2 2006.286.00:29:49.91#ibcon#about to write, iclass 22, count 2 2006.286.00:29:49.91#ibcon#wrote, iclass 22, count 2 2006.286.00:29:49.91#ibcon#about to read 3, iclass 22, count 2 2006.286.00:29:49.93#ibcon#read 3, iclass 22, count 2 2006.286.00:29:49.93#ibcon#about to read 4, iclass 22, count 2 2006.286.00:29:49.93#ibcon#read 4, iclass 22, count 2 2006.286.00:29:49.93#ibcon#about to read 5, iclass 22, count 2 2006.286.00:29:49.93#ibcon#read 5, iclass 22, count 2 2006.286.00:29:49.93#ibcon#about to read 6, iclass 22, count 2 2006.286.00:29:49.93#ibcon#read 6, iclass 22, count 2 2006.286.00:29:49.93#ibcon#end of sib2, iclass 22, count 2 2006.286.00:29:49.93#ibcon#*mode == 0, iclass 22, count 2 2006.286.00:29:49.93#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.00:29:49.93#ibcon#[25=AT08-03\r\n] 2006.286.00:29:49.93#ibcon#*before write, iclass 22, count 2 2006.286.00:29:49.93#ibcon#enter sib2, iclass 22, count 2 2006.286.00:29:49.93#ibcon#flushed, iclass 22, count 2 2006.286.00:29:49.93#ibcon#about to write, iclass 22, count 2 2006.286.00:29:49.93#ibcon#wrote, iclass 22, count 2 2006.286.00:29:49.93#ibcon#about to read 3, iclass 22, count 2 2006.286.00:29:49.96#ibcon#read 3, iclass 22, count 2 2006.286.00:29:49.96#ibcon#about to read 4, iclass 22, count 2 2006.286.00:29:49.96#ibcon#read 4, iclass 22, count 2 2006.286.00:29:49.96#ibcon#about to read 5, iclass 22, count 2 2006.286.00:29:49.96#ibcon#read 5, iclass 22, count 2 2006.286.00:29:49.96#ibcon#about to read 6, iclass 22, count 2 2006.286.00:29:49.96#ibcon#read 6, iclass 22, count 2 2006.286.00:29:49.96#ibcon#end of sib2, iclass 22, count 2 2006.286.00:29:49.96#ibcon#*after write, iclass 22, count 2 2006.286.00:29:49.96#ibcon#*before return 0, iclass 22, count 2 2006.286.00:29:49.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.00:29:49.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.00:29:49.96#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.00:29:49.96#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:49.96#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.00:29:50.08#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.00:29:50.08#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.00:29:50.08#ibcon#enter wrdev, iclass 22, count 0 2006.286.00:29:50.08#ibcon#first serial, iclass 22, count 0 2006.286.00:29:50.08#ibcon#enter sib2, iclass 22, count 0 2006.286.00:29:50.08#ibcon#flushed, iclass 22, count 0 2006.286.00:29:50.08#ibcon#about to write, iclass 22, count 0 2006.286.00:29:50.08#ibcon#wrote, iclass 22, count 0 2006.286.00:29:50.08#ibcon#about to read 3, iclass 22, count 0 2006.286.00:29:50.10#ibcon#read 3, iclass 22, count 0 2006.286.00:29:50.10#ibcon#about to read 4, iclass 22, count 0 2006.286.00:29:50.10#ibcon#read 4, iclass 22, count 0 2006.286.00:29:50.10#ibcon#about to read 5, iclass 22, count 0 2006.286.00:29:50.10#ibcon#read 5, iclass 22, count 0 2006.286.00:29:50.10#ibcon#about to read 6, iclass 22, count 0 2006.286.00:29:50.10#ibcon#read 6, iclass 22, count 0 2006.286.00:29:50.10#ibcon#end of sib2, iclass 22, count 0 2006.286.00:29:50.10#ibcon#*mode == 0, iclass 22, count 0 2006.286.00:29:50.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.00:29:50.10#ibcon#[25=USB\r\n] 2006.286.00:29:50.10#ibcon#*before write, iclass 22, count 0 2006.286.00:29:50.10#ibcon#enter sib2, iclass 22, count 0 2006.286.00:29:50.10#ibcon#flushed, iclass 22, count 0 2006.286.00:29:50.10#ibcon#about to write, iclass 22, count 0 2006.286.00:29:50.10#ibcon#wrote, iclass 22, count 0 2006.286.00:29:50.10#ibcon#about to read 3, iclass 22, count 0 2006.286.00:29:50.13#ibcon#read 3, iclass 22, count 0 2006.286.00:29:50.13#ibcon#about to read 4, iclass 22, count 0 2006.286.00:29:50.13#ibcon#read 4, iclass 22, count 0 2006.286.00:29:50.13#ibcon#about to read 5, iclass 22, count 0 2006.286.00:29:50.13#ibcon#read 5, iclass 22, count 0 2006.286.00:29:50.13#ibcon#about to read 6, iclass 22, count 0 2006.286.00:29:50.13#ibcon#read 6, iclass 22, count 0 2006.286.00:29:50.13#ibcon#end of sib2, iclass 22, count 0 2006.286.00:29:50.13#ibcon#*after write, iclass 22, count 0 2006.286.00:29:50.13#ibcon#*before return 0, iclass 22, count 0 2006.286.00:29:50.13#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.00:29:50.13#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.00:29:50.13#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.00:29:50.13#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.00:29:50.13$vck44/vblo=1,629.99 2006.286.00:29:50.13#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.00:29:50.13#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.00:29:50.13#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:50.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:29:50.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:29:50.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:29:50.13#ibcon#enter wrdev, iclass 24, count 0 2006.286.00:29:50.13#ibcon#first serial, iclass 24, count 0 2006.286.00:29:50.13#ibcon#enter sib2, iclass 24, count 0 2006.286.00:29:50.13#ibcon#flushed, iclass 24, count 0 2006.286.00:29:50.13#ibcon#about to write, iclass 24, count 0 2006.286.00:29:50.13#ibcon#wrote, iclass 24, count 0 2006.286.00:29:50.13#ibcon#about to read 3, iclass 24, count 0 2006.286.00:29:50.15#ibcon#read 3, iclass 24, count 0 2006.286.00:29:50.15#ibcon#about to read 4, iclass 24, count 0 2006.286.00:29:50.15#ibcon#read 4, iclass 24, count 0 2006.286.00:29:50.15#ibcon#about to read 5, iclass 24, count 0 2006.286.00:29:50.15#ibcon#read 5, iclass 24, count 0 2006.286.00:29:50.15#ibcon#about to read 6, iclass 24, count 0 2006.286.00:29:50.15#ibcon#read 6, iclass 24, count 0 2006.286.00:29:50.15#ibcon#end of sib2, iclass 24, count 0 2006.286.00:29:50.15#ibcon#*mode == 0, iclass 24, count 0 2006.286.00:29:50.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.00:29:50.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.00:29:50.15#ibcon#*before write, iclass 24, count 0 2006.286.00:29:50.15#ibcon#enter sib2, iclass 24, count 0 2006.286.00:29:50.15#ibcon#flushed, iclass 24, count 0 2006.286.00:29:50.15#ibcon#about to write, iclass 24, count 0 2006.286.00:29:50.15#ibcon#wrote, iclass 24, count 0 2006.286.00:29:50.15#ibcon#about to read 3, iclass 24, count 0 2006.286.00:29:50.19#ibcon#read 3, iclass 24, count 0 2006.286.00:29:50.19#ibcon#about to read 4, iclass 24, count 0 2006.286.00:29:50.19#ibcon#read 4, iclass 24, count 0 2006.286.00:29:50.19#ibcon#about to read 5, iclass 24, count 0 2006.286.00:29:50.19#ibcon#read 5, iclass 24, count 0 2006.286.00:29:50.19#ibcon#about to read 6, iclass 24, count 0 2006.286.00:29:50.19#ibcon#read 6, iclass 24, count 0 2006.286.00:29:50.19#ibcon#end of sib2, iclass 24, count 0 2006.286.00:29:50.19#ibcon#*after write, iclass 24, count 0 2006.286.00:29:50.19#ibcon#*before return 0, iclass 24, count 0 2006.286.00:29:50.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:29:50.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:29:50.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.00:29:50.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.00:29:50.19$vck44/vb=1,4 2006.286.00:29:50.19#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.00:29:50.19#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.00:29:50.19#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:50.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:29:50.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:29:50.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:29:50.19#ibcon#enter wrdev, iclass 26, count 2 2006.286.00:29:50.19#ibcon#first serial, iclass 26, count 2 2006.286.00:29:50.19#ibcon#enter sib2, iclass 26, count 2 2006.286.00:29:50.19#ibcon#flushed, iclass 26, count 2 2006.286.00:29:50.19#ibcon#about to write, iclass 26, count 2 2006.286.00:29:50.19#ibcon#wrote, iclass 26, count 2 2006.286.00:29:50.19#ibcon#about to read 3, iclass 26, count 2 2006.286.00:29:50.21#ibcon#read 3, iclass 26, count 2 2006.286.00:29:50.21#ibcon#about to read 4, iclass 26, count 2 2006.286.00:29:50.21#ibcon#read 4, iclass 26, count 2 2006.286.00:29:50.21#ibcon#about to read 5, iclass 26, count 2 2006.286.00:29:50.21#ibcon#read 5, iclass 26, count 2 2006.286.00:29:50.21#ibcon#about to read 6, iclass 26, count 2 2006.286.00:29:50.21#ibcon#read 6, iclass 26, count 2 2006.286.00:29:50.21#ibcon#end of sib2, iclass 26, count 2 2006.286.00:29:50.21#ibcon#*mode == 0, iclass 26, count 2 2006.286.00:29:50.21#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.00:29:50.21#ibcon#[27=AT01-04\r\n] 2006.286.00:29:50.21#ibcon#*before write, iclass 26, count 2 2006.286.00:29:50.21#ibcon#enter sib2, iclass 26, count 2 2006.286.00:29:50.21#ibcon#flushed, iclass 26, count 2 2006.286.00:29:50.21#ibcon#about to write, iclass 26, count 2 2006.286.00:29:50.21#ibcon#wrote, iclass 26, count 2 2006.286.00:29:50.21#ibcon#about to read 3, iclass 26, count 2 2006.286.00:29:50.24#ibcon#read 3, iclass 26, count 2 2006.286.00:29:50.24#ibcon#about to read 4, iclass 26, count 2 2006.286.00:29:50.24#ibcon#read 4, iclass 26, count 2 2006.286.00:29:50.24#ibcon#about to read 5, iclass 26, count 2 2006.286.00:29:50.24#ibcon#read 5, iclass 26, count 2 2006.286.00:29:50.24#ibcon#about to read 6, iclass 26, count 2 2006.286.00:29:50.24#ibcon#read 6, iclass 26, count 2 2006.286.00:29:50.24#ibcon#end of sib2, iclass 26, count 2 2006.286.00:29:50.24#ibcon#*after write, iclass 26, count 2 2006.286.00:29:50.24#ibcon#*before return 0, iclass 26, count 2 2006.286.00:29:50.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:29:50.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.00:29:50.24#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.00:29:50.24#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:50.24#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:29:50.36#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:29:50.36#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:29:50.36#ibcon#enter wrdev, iclass 26, count 0 2006.286.00:29:50.36#ibcon#first serial, iclass 26, count 0 2006.286.00:29:50.36#ibcon#enter sib2, iclass 26, count 0 2006.286.00:29:50.36#ibcon#flushed, iclass 26, count 0 2006.286.00:29:50.36#ibcon#about to write, iclass 26, count 0 2006.286.00:29:50.36#ibcon#wrote, iclass 26, count 0 2006.286.00:29:50.36#ibcon#about to read 3, iclass 26, count 0 2006.286.00:29:50.38#ibcon#read 3, iclass 26, count 0 2006.286.00:29:50.38#ibcon#about to read 4, iclass 26, count 0 2006.286.00:29:50.38#ibcon#read 4, iclass 26, count 0 2006.286.00:29:50.38#ibcon#about to read 5, iclass 26, count 0 2006.286.00:29:50.38#ibcon#read 5, iclass 26, count 0 2006.286.00:29:50.38#ibcon#about to read 6, iclass 26, count 0 2006.286.00:29:50.38#ibcon#read 6, iclass 26, count 0 2006.286.00:29:50.38#ibcon#end of sib2, iclass 26, count 0 2006.286.00:29:50.38#ibcon#*mode == 0, iclass 26, count 0 2006.286.00:29:50.38#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.00:29:50.38#ibcon#[27=USB\r\n] 2006.286.00:29:50.38#ibcon#*before write, iclass 26, count 0 2006.286.00:29:50.38#ibcon#enter sib2, iclass 26, count 0 2006.286.00:29:50.38#ibcon#flushed, iclass 26, count 0 2006.286.00:29:50.38#ibcon#about to write, iclass 26, count 0 2006.286.00:29:50.38#ibcon#wrote, iclass 26, count 0 2006.286.00:29:50.38#ibcon#about to read 3, iclass 26, count 0 2006.286.00:29:50.41#ibcon#read 3, iclass 26, count 0 2006.286.00:29:50.41#ibcon#about to read 4, iclass 26, count 0 2006.286.00:29:50.41#ibcon#read 4, iclass 26, count 0 2006.286.00:29:50.41#ibcon#about to read 5, iclass 26, count 0 2006.286.00:29:50.41#ibcon#read 5, iclass 26, count 0 2006.286.00:29:50.41#ibcon#about to read 6, iclass 26, count 0 2006.286.00:29:50.41#ibcon#read 6, iclass 26, count 0 2006.286.00:29:50.41#ibcon#end of sib2, iclass 26, count 0 2006.286.00:29:50.41#ibcon#*after write, iclass 26, count 0 2006.286.00:29:50.41#ibcon#*before return 0, iclass 26, count 0 2006.286.00:29:50.41#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:29:50.41#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.00:29:50.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.00:29:50.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.00:29:50.41$vck44/vblo=2,634.99 2006.286.00:29:50.41#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.00:29:50.41#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.00:29:50.41#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:50.41#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:29:50.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:29:50.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:29:50.41#ibcon#enter wrdev, iclass 28, count 0 2006.286.00:29:50.41#ibcon#first serial, iclass 28, count 0 2006.286.00:29:50.41#ibcon#enter sib2, iclass 28, count 0 2006.286.00:29:50.41#ibcon#flushed, iclass 28, count 0 2006.286.00:29:50.41#ibcon#about to write, iclass 28, count 0 2006.286.00:29:50.41#ibcon#wrote, iclass 28, count 0 2006.286.00:29:50.41#ibcon#about to read 3, iclass 28, count 0 2006.286.00:29:50.43#ibcon#read 3, iclass 28, count 0 2006.286.00:29:50.43#ibcon#about to read 4, iclass 28, count 0 2006.286.00:29:50.43#ibcon#read 4, iclass 28, count 0 2006.286.00:29:50.43#ibcon#about to read 5, iclass 28, count 0 2006.286.00:29:50.43#ibcon#read 5, iclass 28, count 0 2006.286.00:29:50.43#ibcon#about to read 6, iclass 28, count 0 2006.286.00:29:50.43#ibcon#read 6, iclass 28, count 0 2006.286.00:29:50.43#ibcon#end of sib2, iclass 28, count 0 2006.286.00:29:50.43#ibcon#*mode == 0, iclass 28, count 0 2006.286.00:29:50.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.00:29:50.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.00:29:50.43#ibcon#*before write, iclass 28, count 0 2006.286.00:29:50.43#ibcon#enter sib2, iclass 28, count 0 2006.286.00:29:50.43#ibcon#flushed, iclass 28, count 0 2006.286.00:29:50.43#ibcon#about to write, iclass 28, count 0 2006.286.00:29:50.43#ibcon#wrote, iclass 28, count 0 2006.286.00:29:50.43#ibcon#about to read 3, iclass 28, count 0 2006.286.00:29:50.47#ibcon#read 3, iclass 28, count 0 2006.286.00:29:50.47#ibcon#about to read 4, iclass 28, count 0 2006.286.00:29:50.47#ibcon#read 4, iclass 28, count 0 2006.286.00:29:50.47#ibcon#about to read 5, iclass 28, count 0 2006.286.00:29:50.47#ibcon#read 5, iclass 28, count 0 2006.286.00:29:50.47#ibcon#about to read 6, iclass 28, count 0 2006.286.00:29:50.47#ibcon#read 6, iclass 28, count 0 2006.286.00:29:50.47#ibcon#end of sib2, iclass 28, count 0 2006.286.00:29:50.47#ibcon#*after write, iclass 28, count 0 2006.286.00:29:50.47#ibcon#*before return 0, iclass 28, count 0 2006.286.00:29:50.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:29:50.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.00:29:50.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.00:29:50.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.00:29:50.47$vck44/vb=2,5 2006.286.00:29:50.47#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.00:29:50.47#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.00:29:50.47#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:50.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:29:50.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:29:50.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:29:50.53#ibcon#enter wrdev, iclass 30, count 2 2006.286.00:29:50.53#ibcon#first serial, iclass 30, count 2 2006.286.00:29:50.53#ibcon#enter sib2, iclass 30, count 2 2006.286.00:29:50.53#ibcon#flushed, iclass 30, count 2 2006.286.00:29:50.53#ibcon#about to write, iclass 30, count 2 2006.286.00:29:50.53#ibcon#wrote, iclass 30, count 2 2006.286.00:29:50.53#ibcon#about to read 3, iclass 30, count 2 2006.286.00:29:50.55#ibcon#read 3, iclass 30, count 2 2006.286.00:29:50.55#ibcon#about to read 4, iclass 30, count 2 2006.286.00:29:50.55#ibcon#read 4, iclass 30, count 2 2006.286.00:29:50.55#ibcon#about to read 5, iclass 30, count 2 2006.286.00:29:50.55#ibcon#read 5, iclass 30, count 2 2006.286.00:29:50.55#ibcon#about to read 6, iclass 30, count 2 2006.286.00:29:50.55#ibcon#read 6, iclass 30, count 2 2006.286.00:29:50.55#ibcon#end of sib2, iclass 30, count 2 2006.286.00:29:50.55#ibcon#*mode == 0, iclass 30, count 2 2006.286.00:29:50.55#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.00:29:50.55#ibcon#[27=AT02-05\r\n] 2006.286.00:29:50.55#ibcon#*before write, iclass 30, count 2 2006.286.00:29:50.55#ibcon#enter sib2, iclass 30, count 2 2006.286.00:29:50.55#ibcon#flushed, iclass 30, count 2 2006.286.00:29:50.55#ibcon#about to write, iclass 30, count 2 2006.286.00:29:50.55#ibcon#wrote, iclass 30, count 2 2006.286.00:29:50.55#ibcon#about to read 3, iclass 30, count 2 2006.286.00:29:50.58#ibcon#read 3, iclass 30, count 2 2006.286.00:29:50.58#ibcon#about to read 4, iclass 30, count 2 2006.286.00:29:50.58#ibcon#read 4, iclass 30, count 2 2006.286.00:29:50.58#ibcon#about to read 5, iclass 30, count 2 2006.286.00:29:50.58#ibcon#read 5, iclass 30, count 2 2006.286.00:29:50.58#ibcon#about to read 6, iclass 30, count 2 2006.286.00:29:50.58#ibcon#read 6, iclass 30, count 2 2006.286.00:29:50.58#ibcon#end of sib2, iclass 30, count 2 2006.286.00:29:50.58#ibcon#*after write, iclass 30, count 2 2006.286.00:29:50.58#ibcon#*before return 0, iclass 30, count 2 2006.286.00:29:50.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:29:50.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.00:29:50.58#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.00:29:50.58#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:50.58#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:29:50.70#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:29:50.70#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:29:50.70#ibcon#enter wrdev, iclass 30, count 0 2006.286.00:29:50.70#ibcon#first serial, iclass 30, count 0 2006.286.00:29:50.70#ibcon#enter sib2, iclass 30, count 0 2006.286.00:29:50.70#ibcon#flushed, iclass 30, count 0 2006.286.00:29:50.70#ibcon#about to write, iclass 30, count 0 2006.286.00:29:50.70#ibcon#wrote, iclass 30, count 0 2006.286.00:29:50.70#ibcon#about to read 3, iclass 30, count 0 2006.286.00:29:50.72#ibcon#read 3, iclass 30, count 0 2006.286.00:29:50.72#ibcon#about to read 4, iclass 30, count 0 2006.286.00:29:50.72#ibcon#read 4, iclass 30, count 0 2006.286.00:29:50.72#ibcon#about to read 5, iclass 30, count 0 2006.286.00:29:50.72#ibcon#read 5, iclass 30, count 0 2006.286.00:29:50.72#ibcon#about to read 6, iclass 30, count 0 2006.286.00:29:50.72#ibcon#read 6, iclass 30, count 0 2006.286.00:29:50.72#ibcon#end of sib2, iclass 30, count 0 2006.286.00:29:50.72#ibcon#*mode == 0, iclass 30, count 0 2006.286.00:29:50.72#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.00:29:50.72#ibcon#[27=USB\r\n] 2006.286.00:29:50.72#ibcon#*before write, iclass 30, count 0 2006.286.00:29:50.72#ibcon#enter sib2, iclass 30, count 0 2006.286.00:29:50.72#ibcon#flushed, iclass 30, count 0 2006.286.00:29:50.72#ibcon#about to write, iclass 30, count 0 2006.286.00:29:50.72#ibcon#wrote, iclass 30, count 0 2006.286.00:29:50.72#ibcon#about to read 3, iclass 30, count 0 2006.286.00:29:50.75#ibcon#read 3, iclass 30, count 0 2006.286.00:29:50.75#ibcon#about to read 4, iclass 30, count 0 2006.286.00:29:50.75#ibcon#read 4, iclass 30, count 0 2006.286.00:29:50.75#ibcon#about to read 5, iclass 30, count 0 2006.286.00:29:50.75#ibcon#read 5, iclass 30, count 0 2006.286.00:29:50.75#ibcon#about to read 6, iclass 30, count 0 2006.286.00:29:50.75#ibcon#read 6, iclass 30, count 0 2006.286.00:29:50.75#ibcon#end of sib2, iclass 30, count 0 2006.286.00:29:50.75#ibcon#*after write, iclass 30, count 0 2006.286.00:29:50.75#ibcon#*before return 0, iclass 30, count 0 2006.286.00:29:50.75#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:29:50.75#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.00:29:50.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.00:29:50.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.00:29:50.75$vck44/vblo=3,649.99 2006.286.00:29:50.75#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.00:29:50.75#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.00:29:50.75#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:50.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:29:50.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:29:50.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:29:50.75#ibcon#enter wrdev, iclass 32, count 0 2006.286.00:29:50.75#ibcon#first serial, iclass 32, count 0 2006.286.00:29:50.75#ibcon#enter sib2, iclass 32, count 0 2006.286.00:29:50.75#ibcon#flushed, iclass 32, count 0 2006.286.00:29:50.75#ibcon#about to write, iclass 32, count 0 2006.286.00:29:50.75#ibcon#wrote, iclass 32, count 0 2006.286.00:29:50.75#ibcon#about to read 3, iclass 32, count 0 2006.286.00:29:50.77#ibcon#read 3, iclass 32, count 0 2006.286.00:29:50.77#ibcon#about to read 4, iclass 32, count 0 2006.286.00:29:50.77#ibcon#read 4, iclass 32, count 0 2006.286.00:29:50.77#ibcon#about to read 5, iclass 32, count 0 2006.286.00:29:50.77#ibcon#read 5, iclass 32, count 0 2006.286.00:29:50.77#ibcon#about to read 6, iclass 32, count 0 2006.286.00:29:50.77#ibcon#read 6, iclass 32, count 0 2006.286.00:29:50.77#ibcon#end of sib2, iclass 32, count 0 2006.286.00:29:50.77#ibcon#*mode == 0, iclass 32, count 0 2006.286.00:29:50.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.00:29:50.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.00:29:50.77#ibcon#*before write, iclass 32, count 0 2006.286.00:29:50.77#ibcon#enter sib2, iclass 32, count 0 2006.286.00:29:50.77#ibcon#flushed, iclass 32, count 0 2006.286.00:29:50.77#ibcon#about to write, iclass 32, count 0 2006.286.00:29:50.77#ibcon#wrote, iclass 32, count 0 2006.286.00:29:50.77#ibcon#about to read 3, iclass 32, count 0 2006.286.00:29:50.81#ibcon#read 3, iclass 32, count 0 2006.286.00:29:50.81#ibcon#about to read 4, iclass 32, count 0 2006.286.00:29:50.81#ibcon#read 4, iclass 32, count 0 2006.286.00:29:50.81#ibcon#about to read 5, iclass 32, count 0 2006.286.00:29:50.81#ibcon#read 5, iclass 32, count 0 2006.286.00:29:50.81#ibcon#about to read 6, iclass 32, count 0 2006.286.00:29:50.81#ibcon#read 6, iclass 32, count 0 2006.286.00:29:50.81#ibcon#end of sib2, iclass 32, count 0 2006.286.00:29:50.81#ibcon#*after write, iclass 32, count 0 2006.286.00:29:50.81#ibcon#*before return 0, iclass 32, count 0 2006.286.00:29:50.81#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:29:50.81#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:29:50.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.00:29:50.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.00:29:50.81$vck44/vb=3,4 2006.286.00:29:50.81#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.00:29:50.81#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.00:29:50.81#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:50.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:29:50.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:29:50.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:29:50.87#ibcon#enter wrdev, iclass 34, count 2 2006.286.00:29:50.87#ibcon#first serial, iclass 34, count 2 2006.286.00:29:50.87#ibcon#enter sib2, iclass 34, count 2 2006.286.00:29:50.87#ibcon#flushed, iclass 34, count 2 2006.286.00:29:50.87#ibcon#about to write, iclass 34, count 2 2006.286.00:29:50.87#ibcon#wrote, iclass 34, count 2 2006.286.00:29:50.87#ibcon#about to read 3, iclass 34, count 2 2006.286.00:29:50.89#ibcon#read 3, iclass 34, count 2 2006.286.00:29:50.89#ibcon#about to read 4, iclass 34, count 2 2006.286.00:29:50.89#ibcon#read 4, iclass 34, count 2 2006.286.00:29:50.89#ibcon#about to read 5, iclass 34, count 2 2006.286.00:29:50.89#ibcon#read 5, iclass 34, count 2 2006.286.00:29:50.89#ibcon#about to read 6, iclass 34, count 2 2006.286.00:29:50.89#ibcon#read 6, iclass 34, count 2 2006.286.00:29:50.89#ibcon#end of sib2, iclass 34, count 2 2006.286.00:29:50.89#ibcon#*mode == 0, iclass 34, count 2 2006.286.00:29:50.89#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.00:29:50.89#ibcon#[27=AT03-04\r\n] 2006.286.00:29:50.89#ibcon#*before write, iclass 34, count 2 2006.286.00:29:50.89#ibcon#enter sib2, iclass 34, count 2 2006.286.00:29:50.89#ibcon#flushed, iclass 34, count 2 2006.286.00:29:50.89#ibcon#about to write, iclass 34, count 2 2006.286.00:29:50.89#ibcon#wrote, iclass 34, count 2 2006.286.00:29:50.89#ibcon#about to read 3, iclass 34, count 2 2006.286.00:29:50.92#ibcon#read 3, iclass 34, count 2 2006.286.00:29:50.92#ibcon#about to read 4, iclass 34, count 2 2006.286.00:29:50.92#ibcon#read 4, iclass 34, count 2 2006.286.00:29:50.92#ibcon#about to read 5, iclass 34, count 2 2006.286.00:29:50.92#ibcon#read 5, iclass 34, count 2 2006.286.00:29:50.92#ibcon#about to read 6, iclass 34, count 2 2006.286.00:29:50.92#ibcon#read 6, iclass 34, count 2 2006.286.00:29:50.92#ibcon#end of sib2, iclass 34, count 2 2006.286.00:29:50.92#ibcon#*after write, iclass 34, count 2 2006.286.00:29:50.92#ibcon#*before return 0, iclass 34, count 2 2006.286.00:29:50.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:29:50.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.00:29:50.92#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.00:29:50.92#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:50.92#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:29:51.04#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:29:51.04#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:29:51.04#ibcon#enter wrdev, iclass 34, count 0 2006.286.00:29:51.04#ibcon#first serial, iclass 34, count 0 2006.286.00:29:51.04#ibcon#enter sib2, iclass 34, count 0 2006.286.00:29:51.04#ibcon#flushed, iclass 34, count 0 2006.286.00:29:51.04#ibcon#about to write, iclass 34, count 0 2006.286.00:29:51.04#ibcon#wrote, iclass 34, count 0 2006.286.00:29:51.04#ibcon#about to read 3, iclass 34, count 0 2006.286.00:29:51.06#ibcon#read 3, iclass 34, count 0 2006.286.00:29:51.06#ibcon#about to read 4, iclass 34, count 0 2006.286.00:29:51.06#ibcon#read 4, iclass 34, count 0 2006.286.00:29:51.06#ibcon#about to read 5, iclass 34, count 0 2006.286.00:29:51.06#ibcon#read 5, iclass 34, count 0 2006.286.00:29:51.06#ibcon#about to read 6, iclass 34, count 0 2006.286.00:29:51.06#ibcon#read 6, iclass 34, count 0 2006.286.00:29:51.06#ibcon#end of sib2, iclass 34, count 0 2006.286.00:29:51.06#ibcon#*mode == 0, iclass 34, count 0 2006.286.00:29:51.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.00:29:51.06#ibcon#[27=USB\r\n] 2006.286.00:29:51.06#ibcon#*before write, iclass 34, count 0 2006.286.00:29:51.06#ibcon#enter sib2, iclass 34, count 0 2006.286.00:29:51.06#ibcon#flushed, iclass 34, count 0 2006.286.00:29:51.06#ibcon#about to write, iclass 34, count 0 2006.286.00:29:51.06#ibcon#wrote, iclass 34, count 0 2006.286.00:29:51.06#ibcon#about to read 3, iclass 34, count 0 2006.286.00:29:51.09#ibcon#read 3, iclass 34, count 0 2006.286.00:29:51.09#ibcon#about to read 4, iclass 34, count 0 2006.286.00:29:51.09#ibcon#read 4, iclass 34, count 0 2006.286.00:29:51.09#ibcon#about to read 5, iclass 34, count 0 2006.286.00:29:51.09#ibcon#read 5, iclass 34, count 0 2006.286.00:29:51.09#ibcon#about to read 6, iclass 34, count 0 2006.286.00:29:51.09#ibcon#read 6, iclass 34, count 0 2006.286.00:29:51.09#ibcon#end of sib2, iclass 34, count 0 2006.286.00:29:51.09#ibcon#*after write, iclass 34, count 0 2006.286.00:29:51.09#ibcon#*before return 0, iclass 34, count 0 2006.286.00:29:51.09#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:29:51.09#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.00:29:51.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.00:29:51.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.00:29:51.09$vck44/vblo=4,679.99 2006.286.00:29:51.09#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.00:29:51.09#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.00:29:51.09#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:51.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:29:51.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:29:51.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:29:51.09#ibcon#enter wrdev, iclass 36, count 0 2006.286.00:29:51.09#ibcon#first serial, iclass 36, count 0 2006.286.00:29:51.09#ibcon#enter sib2, iclass 36, count 0 2006.286.00:29:51.09#ibcon#flushed, iclass 36, count 0 2006.286.00:29:51.09#ibcon#about to write, iclass 36, count 0 2006.286.00:29:51.09#ibcon#wrote, iclass 36, count 0 2006.286.00:29:51.09#ibcon#about to read 3, iclass 36, count 0 2006.286.00:29:51.11#ibcon#read 3, iclass 36, count 0 2006.286.00:29:51.11#ibcon#about to read 4, iclass 36, count 0 2006.286.00:29:51.11#ibcon#read 4, iclass 36, count 0 2006.286.00:29:51.11#ibcon#about to read 5, iclass 36, count 0 2006.286.00:29:51.11#ibcon#read 5, iclass 36, count 0 2006.286.00:29:51.11#ibcon#about to read 6, iclass 36, count 0 2006.286.00:29:51.11#ibcon#read 6, iclass 36, count 0 2006.286.00:29:51.11#ibcon#end of sib2, iclass 36, count 0 2006.286.00:29:51.11#ibcon#*mode == 0, iclass 36, count 0 2006.286.00:29:51.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.00:29:51.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.00:29:51.11#ibcon#*before write, iclass 36, count 0 2006.286.00:29:51.11#ibcon#enter sib2, iclass 36, count 0 2006.286.00:29:51.11#ibcon#flushed, iclass 36, count 0 2006.286.00:29:51.11#ibcon#about to write, iclass 36, count 0 2006.286.00:29:51.11#ibcon#wrote, iclass 36, count 0 2006.286.00:29:51.11#ibcon#about to read 3, iclass 36, count 0 2006.286.00:29:51.15#ibcon#read 3, iclass 36, count 0 2006.286.00:29:51.15#ibcon#about to read 4, iclass 36, count 0 2006.286.00:29:51.15#ibcon#read 4, iclass 36, count 0 2006.286.00:29:51.15#ibcon#about to read 5, iclass 36, count 0 2006.286.00:29:51.15#ibcon#read 5, iclass 36, count 0 2006.286.00:29:51.15#ibcon#about to read 6, iclass 36, count 0 2006.286.00:29:51.15#ibcon#read 6, iclass 36, count 0 2006.286.00:29:51.15#ibcon#end of sib2, iclass 36, count 0 2006.286.00:29:51.15#ibcon#*after write, iclass 36, count 0 2006.286.00:29:51.15#ibcon#*before return 0, iclass 36, count 0 2006.286.00:29:51.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:29:51.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.00:29:51.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.00:29:51.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.00:29:51.15$vck44/vb=4,5 2006.286.00:29:51.15#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.00:29:51.15#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.00:29:51.15#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:51.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:29:51.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:29:51.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:29:51.21#ibcon#enter wrdev, iclass 38, count 2 2006.286.00:29:51.21#ibcon#first serial, iclass 38, count 2 2006.286.00:29:51.21#ibcon#enter sib2, iclass 38, count 2 2006.286.00:29:51.21#ibcon#flushed, iclass 38, count 2 2006.286.00:29:51.21#ibcon#about to write, iclass 38, count 2 2006.286.00:29:51.21#ibcon#wrote, iclass 38, count 2 2006.286.00:29:51.21#ibcon#about to read 3, iclass 38, count 2 2006.286.00:29:51.23#ibcon#read 3, iclass 38, count 2 2006.286.00:29:51.23#ibcon#about to read 4, iclass 38, count 2 2006.286.00:29:51.23#ibcon#read 4, iclass 38, count 2 2006.286.00:29:51.23#ibcon#about to read 5, iclass 38, count 2 2006.286.00:29:51.23#ibcon#read 5, iclass 38, count 2 2006.286.00:29:51.23#ibcon#about to read 6, iclass 38, count 2 2006.286.00:29:51.23#ibcon#read 6, iclass 38, count 2 2006.286.00:29:51.23#ibcon#end of sib2, iclass 38, count 2 2006.286.00:29:51.23#ibcon#*mode == 0, iclass 38, count 2 2006.286.00:29:51.23#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.00:29:51.23#ibcon#[27=AT04-05\r\n] 2006.286.00:29:51.23#ibcon#*before write, iclass 38, count 2 2006.286.00:29:51.23#ibcon#enter sib2, iclass 38, count 2 2006.286.00:29:51.23#ibcon#flushed, iclass 38, count 2 2006.286.00:29:51.23#ibcon#about to write, iclass 38, count 2 2006.286.00:29:51.23#ibcon#wrote, iclass 38, count 2 2006.286.00:29:51.23#ibcon#about to read 3, iclass 38, count 2 2006.286.00:29:51.26#ibcon#read 3, iclass 38, count 2 2006.286.00:29:51.26#ibcon#about to read 4, iclass 38, count 2 2006.286.00:29:51.26#ibcon#read 4, iclass 38, count 2 2006.286.00:29:51.26#ibcon#about to read 5, iclass 38, count 2 2006.286.00:29:51.26#ibcon#read 5, iclass 38, count 2 2006.286.00:29:51.26#ibcon#about to read 6, iclass 38, count 2 2006.286.00:29:51.26#ibcon#read 6, iclass 38, count 2 2006.286.00:29:51.26#ibcon#end of sib2, iclass 38, count 2 2006.286.00:29:51.26#ibcon#*after write, iclass 38, count 2 2006.286.00:29:51.26#ibcon#*before return 0, iclass 38, count 2 2006.286.00:29:51.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:29:51.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.00:29:51.26#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.00:29:51.26#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:51.26#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:29:51.38#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:29:51.38#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:29:51.38#ibcon#enter wrdev, iclass 38, count 0 2006.286.00:29:51.38#ibcon#first serial, iclass 38, count 0 2006.286.00:29:51.38#ibcon#enter sib2, iclass 38, count 0 2006.286.00:29:51.38#ibcon#flushed, iclass 38, count 0 2006.286.00:29:51.38#ibcon#about to write, iclass 38, count 0 2006.286.00:29:51.38#ibcon#wrote, iclass 38, count 0 2006.286.00:29:51.38#ibcon#about to read 3, iclass 38, count 0 2006.286.00:29:51.40#ibcon#read 3, iclass 38, count 0 2006.286.00:29:51.40#ibcon#about to read 4, iclass 38, count 0 2006.286.00:29:51.40#ibcon#read 4, iclass 38, count 0 2006.286.00:29:51.40#ibcon#about to read 5, iclass 38, count 0 2006.286.00:29:51.40#ibcon#read 5, iclass 38, count 0 2006.286.00:29:51.40#ibcon#about to read 6, iclass 38, count 0 2006.286.00:29:51.40#ibcon#read 6, iclass 38, count 0 2006.286.00:29:51.40#ibcon#end of sib2, iclass 38, count 0 2006.286.00:29:51.40#ibcon#*mode == 0, iclass 38, count 0 2006.286.00:29:51.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.00:29:51.40#ibcon#[27=USB\r\n] 2006.286.00:29:51.40#ibcon#*before write, iclass 38, count 0 2006.286.00:29:51.40#ibcon#enter sib2, iclass 38, count 0 2006.286.00:29:51.40#ibcon#flushed, iclass 38, count 0 2006.286.00:29:51.40#ibcon#about to write, iclass 38, count 0 2006.286.00:29:51.40#ibcon#wrote, iclass 38, count 0 2006.286.00:29:51.40#ibcon#about to read 3, iclass 38, count 0 2006.286.00:29:51.43#ibcon#read 3, iclass 38, count 0 2006.286.00:29:51.43#ibcon#about to read 4, iclass 38, count 0 2006.286.00:29:51.43#ibcon#read 4, iclass 38, count 0 2006.286.00:29:51.43#ibcon#about to read 5, iclass 38, count 0 2006.286.00:29:51.43#ibcon#read 5, iclass 38, count 0 2006.286.00:29:51.43#ibcon#about to read 6, iclass 38, count 0 2006.286.00:29:51.43#ibcon#read 6, iclass 38, count 0 2006.286.00:29:51.43#ibcon#end of sib2, iclass 38, count 0 2006.286.00:29:51.43#ibcon#*after write, iclass 38, count 0 2006.286.00:29:51.43#ibcon#*before return 0, iclass 38, count 0 2006.286.00:29:51.43#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:29:51.43#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.00:29:51.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.00:29:51.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.00:29:51.43$vck44/vblo=5,709.99 2006.286.00:29:51.43#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.00:29:51.43#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.00:29:51.43#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:51.43#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:29:51.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:29:51.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:29:51.43#ibcon#enter wrdev, iclass 40, count 0 2006.286.00:29:51.43#ibcon#first serial, iclass 40, count 0 2006.286.00:29:51.43#ibcon#enter sib2, iclass 40, count 0 2006.286.00:29:51.43#ibcon#flushed, iclass 40, count 0 2006.286.00:29:51.43#ibcon#about to write, iclass 40, count 0 2006.286.00:29:51.43#ibcon#wrote, iclass 40, count 0 2006.286.00:29:51.43#ibcon#about to read 3, iclass 40, count 0 2006.286.00:29:51.45#ibcon#read 3, iclass 40, count 0 2006.286.00:29:51.45#ibcon#about to read 4, iclass 40, count 0 2006.286.00:29:51.45#ibcon#read 4, iclass 40, count 0 2006.286.00:29:51.45#ibcon#about to read 5, iclass 40, count 0 2006.286.00:29:51.45#ibcon#read 5, iclass 40, count 0 2006.286.00:29:51.45#ibcon#about to read 6, iclass 40, count 0 2006.286.00:29:51.45#ibcon#read 6, iclass 40, count 0 2006.286.00:29:51.45#ibcon#end of sib2, iclass 40, count 0 2006.286.00:29:51.45#ibcon#*mode == 0, iclass 40, count 0 2006.286.00:29:51.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.00:29:51.45#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.00:29:51.45#ibcon#*before write, iclass 40, count 0 2006.286.00:29:51.45#ibcon#enter sib2, iclass 40, count 0 2006.286.00:29:51.45#ibcon#flushed, iclass 40, count 0 2006.286.00:29:51.45#ibcon#about to write, iclass 40, count 0 2006.286.00:29:51.45#ibcon#wrote, iclass 40, count 0 2006.286.00:29:51.45#ibcon#about to read 3, iclass 40, count 0 2006.286.00:29:51.49#ibcon#read 3, iclass 40, count 0 2006.286.00:29:51.49#ibcon#about to read 4, iclass 40, count 0 2006.286.00:29:51.49#ibcon#read 4, iclass 40, count 0 2006.286.00:29:51.49#ibcon#about to read 5, iclass 40, count 0 2006.286.00:29:51.49#ibcon#read 5, iclass 40, count 0 2006.286.00:29:51.49#ibcon#about to read 6, iclass 40, count 0 2006.286.00:29:51.49#ibcon#read 6, iclass 40, count 0 2006.286.00:29:51.49#ibcon#end of sib2, iclass 40, count 0 2006.286.00:29:51.49#ibcon#*after write, iclass 40, count 0 2006.286.00:29:51.49#ibcon#*before return 0, iclass 40, count 0 2006.286.00:29:51.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:29:51.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.00:29:51.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.00:29:51.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.00:29:51.49$vck44/vb=5,4 2006.286.00:29:51.49#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.00:29:51.49#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.00:29:51.49#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:51.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:29:51.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:29:51.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:29:51.55#ibcon#enter wrdev, iclass 4, count 2 2006.286.00:29:51.55#ibcon#first serial, iclass 4, count 2 2006.286.00:29:51.55#ibcon#enter sib2, iclass 4, count 2 2006.286.00:29:51.55#ibcon#flushed, iclass 4, count 2 2006.286.00:29:51.55#ibcon#about to write, iclass 4, count 2 2006.286.00:29:51.55#ibcon#wrote, iclass 4, count 2 2006.286.00:29:51.55#ibcon#about to read 3, iclass 4, count 2 2006.286.00:29:51.57#ibcon#read 3, iclass 4, count 2 2006.286.00:29:51.57#ibcon#about to read 4, iclass 4, count 2 2006.286.00:29:51.57#ibcon#read 4, iclass 4, count 2 2006.286.00:29:51.57#ibcon#about to read 5, iclass 4, count 2 2006.286.00:29:51.57#ibcon#read 5, iclass 4, count 2 2006.286.00:29:51.57#ibcon#about to read 6, iclass 4, count 2 2006.286.00:29:51.57#ibcon#read 6, iclass 4, count 2 2006.286.00:29:51.57#ibcon#end of sib2, iclass 4, count 2 2006.286.00:29:51.57#ibcon#*mode == 0, iclass 4, count 2 2006.286.00:29:51.57#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.00:29:51.57#ibcon#[27=AT05-04\r\n] 2006.286.00:29:51.57#ibcon#*before write, iclass 4, count 2 2006.286.00:29:51.57#ibcon#enter sib2, iclass 4, count 2 2006.286.00:29:51.57#ibcon#flushed, iclass 4, count 2 2006.286.00:29:51.57#ibcon#about to write, iclass 4, count 2 2006.286.00:29:51.57#ibcon#wrote, iclass 4, count 2 2006.286.00:29:51.57#ibcon#about to read 3, iclass 4, count 2 2006.286.00:29:51.60#ibcon#read 3, iclass 4, count 2 2006.286.00:29:51.60#ibcon#about to read 4, iclass 4, count 2 2006.286.00:29:51.60#ibcon#read 4, iclass 4, count 2 2006.286.00:29:51.60#ibcon#about to read 5, iclass 4, count 2 2006.286.00:29:51.60#ibcon#read 5, iclass 4, count 2 2006.286.00:29:51.60#ibcon#about to read 6, iclass 4, count 2 2006.286.00:29:51.60#ibcon#read 6, iclass 4, count 2 2006.286.00:29:51.60#ibcon#end of sib2, iclass 4, count 2 2006.286.00:29:51.60#ibcon#*after write, iclass 4, count 2 2006.286.00:29:51.60#ibcon#*before return 0, iclass 4, count 2 2006.286.00:29:51.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:29:51.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.00:29:51.60#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.00:29:51.60#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:51.60#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:29:51.72#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:29:51.72#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:29:51.72#ibcon#enter wrdev, iclass 4, count 0 2006.286.00:29:51.72#ibcon#first serial, iclass 4, count 0 2006.286.00:29:51.72#ibcon#enter sib2, iclass 4, count 0 2006.286.00:29:51.72#ibcon#flushed, iclass 4, count 0 2006.286.00:29:51.72#ibcon#about to write, iclass 4, count 0 2006.286.00:29:51.72#ibcon#wrote, iclass 4, count 0 2006.286.00:29:51.72#ibcon#about to read 3, iclass 4, count 0 2006.286.00:29:51.74#ibcon#read 3, iclass 4, count 0 2006.286.00:29:51.74#ibcon#about to read 4, iclass 4, count 0 2006.286.00:29:51.74#ibcon#read 4, iclass 4, count 0 2006.286.00:29:51.74#ibcon#about to read 5, iclass 4, count 0 2006.286.00:29:51.74#ibcon#read 5, iclass 4, count 0 2006.286.00:29:51.74#ibcon#about to read 6, iclass 4, count 0 2006.286.00:29:51.74#ibcon#read 6, iclass 4, count 0 2006.286.00:29:51.74#ibcon#end of sib2, iclass 4, count 0 2006.286.00:29:51.74#ibcon#*mode == 0, iclass 4, count 0 2006.286.00:29:51.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.00:29:51.74#ibcon#[27=USB\r\n] 2006.286.00:29:51.74#ibcon#*before write, iclass 4, count 0 2006.286.00:29:51.74#ibcon#enter sib2, iclass 4, count 0 2006.286.00:29:51.74#ibcon#flushed, iclass 4, count 0 2006.286.00:29:51.74#ibcon#about to write, iclass 4, count 0 2006.286.00:29:51.74#ibcon#wrote, iclass 4, count 0 2006.286.00:29:51.74#ibcon#about to read 3, iclass 4, count 0 2006.286.00:29:51.77#ibcon#read 3, iclass 4, count 0 2006.286.00:29:51.77#ibcon#about to read 4, iclass 4, count 0 2006.286.00:29:51.77#ibcon#read 4, iclass 4, count 0 2006.286.00:29:51.77#ibcon#about to read 5, iclass 4, count 0 2006.286.00:29:51.77#ibcon#read 5, iclass 4, count 0 2006.286.00:29:51.77#ibcon#about to read 6, iclass 4, count 0 2006.286.00:29:51.77#ibcon#read 6, iclass 4, count 0 2006.286.00:29:51.77#ibcon#end of sib2, iclass 4, count 0 2006.286.00:29:51.77#ibcon#*after write, iclass 4, count 0 2006.286.00:29:51.77#ibcon#*before return 0, iclass 4, count 0 2006.286.00:29:51.77#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:29:51.77#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.00:29:51.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.00:29:51.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.00:29:51.77$vck44/vblo=6,719.99 2006.286.00:29:51.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.00:29:51.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.00:29:51.77#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:51.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:29:51.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:29:51.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:29:51.77#ibcon#enter wrdev, iclass 6, count 0 2006.286.00:29:51.77#ibcon#first serial, iclass 6, count 0 2006.286.00:29:51.77#ibcon#enter sib2, iclass 6, count 0 2006.286.00:29:51.77#ibcon#flushed, iclass 6, count 0 2006.286.00:29:51.77#ibcon#about to write, iclass 6, count 0 2006.286.00:29:51.77#ibcon#wrote, iclass 6, count 0 2006.286.00:29:51.77#ibcon#about to read 3, iclass 6, count 0 2006.286.00:29:51.79#ibcon#read 3, iclass 6, count 0 2006.286.00:29:51.79#ibcon#about to read 4, iclass 6, count 0 2006.286.00:29:51.79#ibcon#read 4, iclass 6, count 0 2006.286.00:29:51.79#ibcon#about to read 5, iclass 6, count 0 2006.286.00:29:51.79#ibcon#read 5, iclass 6, count 0 2006.286.00:29:51.79#ibcon#about to read 6, iclass 6, count 0 2006.286.00:29:51.79#ibcon#read 6, iclass 6, count 0 2006.286.00:29:51.79#ibcon#end of sib2, iclass 6, count 0 2006.286.00:29:51.79#ibcon#*mode == 0, iclass 6, count 0 2006.286.00:29:51.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.00:29:51.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.00:29:51.79#ibcon#*before write, iclass 6, count 0 2006.286.00:29:51.79#ibcon#enter sib2, iclass 6, count 0 2006.286.00:29:51.79#ibcon#flushed, iclass 6, count 0 2006.286.00:29:51.79#ibcon#about to write, iclass 6, count 0 2006.286.00:29:51.79#ibcon#wrote, iclass 6, count 0 2006.286.00:29:51.79#ibcon#about to read 3, iclass 6, count 0 2006.286.00:29:51.83#ibcon#read 3, iclass 6, count 0 2006.286.00:29:51.83#ibcon#about to read 4, iclass 6, count 0 2006.286.00:29:51.83#ibcon#read 4, iclass 6, count 0 2006.286.00:29:51.83#ibcon#about to read 5, iclass 6, count 0 2006.286.00:29:51.83#ibcon#read 5, iclass 6, count 0 2006.286.00:29:51.83#ibcon#about to read 6, iclass 6, count 0 2006.286.00:29:51.83#ibcon#read 6, iclass 6, count 0 2006.286.00:29:51.83#ibcon#end of sib2, iclass 6, count 0 2006.286.00:29:51.83#ibcon#*after write, iclass 6, count 0 2006.286.00:29:51.83#ibcon#*before return 0, iclass 6, count 0 2006.286.00:29:51.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:29:51.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.00:29:51.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.00:29:51.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.00:29:51.83$vck44/vb=6,3 2006.286.00:29:51.83#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.00:29:51.83#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.00:29:51.83#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:51.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:29:51.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:29:51.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:29:51.89#ibcon#enter wrdev, iclass 10, count 2 2006.286.00:29:51.89#ibcon#first serial, iclass 10, count 2 2006.286.00:29:51.89#ibcon#enter sib2, iclass 10, count 2 2006.286.00:29:51.89#ibcon#flushed, iclass 10, count 2 2006.286.00:29:51.89#ibcon#about to write, iclass 10, count 2 2006.286.00:29:51.89#ibcon#wrote, iclass 10, count 2 2006.286.00:29:51.89#ibcon#about to read 3, iclass 10, count 2 2006.286.00:29:51.91#ibcon#read 3, iclass 10, count 2 2006.286.00:29:51.91#ibcon#about to read 4, iclass 10, count 2 2006.286.00:29:51.91#ibcon#read 4, iclass 10, count 2 2006.286.00:29:51.91#ibcon#about to read 5, iclass 10, count 2 2006.286.00:29:51.91#ibcon#read 5, iclass 10, count 2 2006.286.00:29:51.91#ibcon#about to read 6, iclass 10, count 2 2006.286.00:29:51.91#ibcon#read 6, iclass 10, count 2 2006.286.00:29:51.91#ibcon#end of sib2, iclass 10, count 2 2006.286.00:29:51.91#ibcon#*mode == 0, iclass 10, count 2 2006.286.00:29:51.91#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.00:29:51.91#ibcon#[27=AT06-03\r\n] 2006.286.00:29:51.91#ibcon#*before write, iclass 10, count 2 2006.286.00:29:51.91#ibcon#enter sib2, iclass 10, count 2 2006.286.00:29:51.91#ibcon#flushed, iclass 10, count 2 2006.286.00:29:51.91#ibcon#about to write, iclass 10, count 2 2006.286.00:29:51.91#ibcon#wrote, iclass 10, count 2 2006.286.00:29:51.91#ibcon#about to read 3, iclass 10, count 2 2006.286.00:29:51.94#ibcon#read 3, iclass 10, count 2 2006.286.00:29:51.94#ibcon#about to read 4, iclass 10, count 2 2006.286.00:29:51.94#ibcon#read 4, iclass 10, count 2 2006.286.00:29:51.94#ibcon#about to read 5, iclass 10, count 2 2006.286.00:29:51.94#ibcon#read 5, iclass 10, count 2 2006.286.00:29:51.94#ibcon#about to read 6, iclass 10, count 2 2006.286.00:29:51.94#ibcon#read 6, iclass 10, count 2 2006.286.00:29:51.94#ibcon#end of sib2, iclass 10, count 2 2006.286.00:29:51.94#ibcon#*after write, iclass 10, count 2 2006.286.00:29:51.94#ibcon#*before return 0, iclass 10, count 2 2006.286.00:29:51.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:29:51.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.00:29:51.94#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.00:29:51.94#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:51.94#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:29:52.06#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:29:52.06#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:29:52.06#ibcon#enter wrdev, iclass 10, count 0 2006.286.00:29:52.06#ibcon#first serial, iclass 10, count 0 2006.286.00:29:52.06#ibcon#enter sib2, iclass 10, count 0 2006.286.00:29:52.06#ibcon#flushed, iclass 10, count 0 2006.286.00:29:52.06#ibcon#about to write, iclass 10, count 0 2006.286.00:29:52.06#ibcon#wrote, iclass 10, count 0 2006.286.00:29:52.06#ibcon#about to read 3, iclass 10, count 0 2006.286.00:29:52.08#ibcon#read 3, iclass 10, count 0 2006.286.00:29:52.08#ibcon#about to read 4, iclass 10, count 0 2006.286.00:29:52.08#ibcon#read 4, iclass 10, count 0 2006.286.00:29:52.08#ibcon#about to read 5, iclass 10, count 0 2006.286.00:29:52.08#ibcon#read 5, iclass 10, count 0 2006.286.00:29:52.08#ibcon#about to read 6, iclass 10, count 0 2006.286.00:29:52.08#ibcon#read 6, iclass 10, count 0 2006.286.00:29:52.08#ibcon#end of sib2, iclass 10, count 0 2006.286.00:29:52.08#ibcon#*mode == 0, iclass 10, count 0 2006.286.00:29:52.08#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.00:29:52.08#ibcon#[27=USB\r\n] 2006.286.00:29:52.08#ibcon#*before write, iclass 10, count 0 2006.286.00:29:52.08#ibcon#enter sib2, iclass 10, count 0 2006.286.00:29:52.08#ibcon#flushed, iclass 10, count 0 2006.286.00:29:52.08#ibcon#about to write, iclass 10, count 0 2006.286.00:29:52.08#ibcon#wrote, iclass 10, count 0 2006.286.00:29:52.08#ibcon#about to read 3, iclass 10, count 0 2006.286.00:29:52.11#ibcon#read 3, iclass 10, count 0 2006.286.00:29:52.11#ibcon#about to read 4, iclass 10, count 0 2006.286.00:29:52.11#ibcon#read 4, iclass 10, count 0 2006.286.00:29:52.11#ibcon#about to read 5, iclass 10, count 0 2006.286.00:29:52.11#ibcon#read 5, iclass 10, count 0 2006.286.00:29:52.11#ibcon#about to read 6, iclass 10, count 0 2006.286.00:29:52.11#ibcon#read 6, iclass 10, count 0 2006.286.00:29:52.11#ibcon#end of sib2, iclass 10, count 0 2006.286.00:29:52.11#ibcon#*after write, iclass 10, count 0 2006.286.00:29:52.11#ibcon#*before return 0, iclass 10, count 0 2006.286.00:29:52.11#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:29:52.11#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.00:29:52.11#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.00:29:52.11#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.00:29:52.11$vck44/vblo=7,734.99 2006.286.00:29:52.11#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.00:29:52.11#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.00:29:52.11#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:52.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:29:52.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:29:52.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:29:52.11#ibcon#enter wrdev, iclass 12, count 0 2006.286.00:29:52.11#ibcon#first serial, iclass 12, count 0 2006.286.00:29:52.11#ibcon#enter sib2, iclass 12, count 0 2006.286.00:29:52.11#ibcon#flushed, iclass 12, count 0 2006.286.00:29:52.11#ibcon#about to write, iclass 12, count 0 2006.286.00:29:52.11#ibcon#wrote, iclass 12, count 0 2006.286.00:29:52.11#ibcon#about to read 3, iclass 12, count 0 2006.286.00:29:52.13#ibcon#read 3, iclass 12, count 0 2006.286.00:29:52.13#ibcon#about to read 4, iclass 12, count 0 2006.286.00:29:52.13#ibcon#read 4, iclass 12, count 0 2006.286.00:29:52.13#ibcon#about to read 5, iclass 12, count 0 2006.286.00:29:52.13#ibcon#read 5, iclass 12, count 0 2006.286.00:29:52.13#ibcon#about to read 6, iclass 12, count 0 2006.286.00:29:52.13#ibcon#read 6, iclass 12, count 0 2006.286.00:29:52.13#ibcon#end of sib2, iclass 12, count 0 2006.286.00:29:52.13#ibcon#*mode == 0, iclass 12, count 0 2006.286.00:29:52.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.00:29:52.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.00:29:52.13#ibcon#*before write, iclass 12, count 0 2006.286.00:29:52.13#ibcon#enter sib2, iclass 12, count 0 2006.286.00:29:52.13#ibcon#flushed, iclass 12, count 0 2006.286.00:29:52.13#ibcon#about to write, iclass 12, count 0 2006.286.00:29:52.13#ibcon#wrote, iclass 12, count 0 2006.286.00:29:52.13#ibcon#about to read 3, iclass 12, count 0 2006.286.00:29:52.17#ibcon#read 3, iclass 12, count 0 2006.286.00:29:52.17#ibcon#about to read 4, iclass 12, count 0 2006.286.00:29:52.17#ibcon#read 4, iclass 12, count 0 2006.286.00:29:52.17#ibcon#about to read 5, iclass 12, count 0 2006.286.00:29:52.17#ibcon#read 5, iclass 12, count 0 2006.286.00:29:52.17#ibcon#about to read 6, iclass 12, count 0 2006.286.00:29:52.17#ibcon#read 6, iclass 12, count 0 2006.286.00:29:52.17#ibcon#end of sib2, iclass 12, count 0 2006.286.00:29:52.17#ibcon#*after write, iclass 12, count 0 2006.286.00:29:52.17#ibcon#*before return 0, iclass 12, count 0 2006.286.00:29:52.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:29:52.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.00:29:52.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.00:29:52.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.00:29:52.17$vck44/vb=7,4 2006.286.00:29:52.17#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.00:29:52.17#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.00:29:52.17#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:52.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:29:52.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:29:52.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:29:52.23#ibcon#enter wrdev, iclass 14, count 2 2006.286.00:29:52.23#ibcon#first serial, iclass 14, count 2 2006.286.00:29:52.23#ibcon#enter sib2, iclass 14, count 2 2006.286.00:29:52.23#ibcon#flushed, iclass 14, count 2 2006.286.00:29:52.23#ibcon#about to write, iclass 14, count 2 2006.286.00:29:52.23#ibcon#wrote, iclass 14, count 2 2006.286.00:29:52.23#ibcon#about to read 3, iclass 14, count 2 2006.286.00:29:52.25#ibcon#read 3, iclass 14, count 2 2006.286.00:29:52.25#ibcon#about to read 4, iclass 14, count 2 2006.286.00:29:52.25#ibcon#read 4, iclass 14, count 2 2006.286.00:29:52.25#ibcon#about to read 5, iclass 14, count 2 2006.286.00:29:52.25#ibcon#read 5, iclass 14, count 2 2006.286.00:29:52.25#ibcon#about to read 6, iclass 14, count 2 2006.286.00:29:52.25#ibcon#read 6, iclass 14, count 2 2006.286.00:29:52.25#ibcon#end of sib2, iclass 14, count 2 2006.286.00:29:52.25#ibcon#*mode == 0, iclass 14, count 2 2006.286.00:29:52.25#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.00:29:52.25#ibcon#[27=AT07-04\r\n] 2006.286.00:29:52.25#ibcon#*before write, iclass 14, count 2 2006.286.00:29:52.25#ibcon#enter sib2, iclass 14, count 2 2006.286.00:29:52.25#ibcon#flushed, iclass 14, count 2 2006.286.00:29:52.25#ibcon#about to write, iclass 14, count 2 2006.286.00:29:52.25#ibcon#wrote, iclass 14, count 2 2006.286.00:29:52.25#ibcon#about to read 3, iclass 14, count 2 2006.286.00:29:52.28#ibcon#read 3, iclass 14, count 2 2006.286.00:29:52.28#ibcon#about to read 4, iclass 14, count 2 2006.286.00:29:52.28#ibcon#read 4, iclass 14, count 2 2006.286.00:29:52.28#ibcon#about to read 5, iclass 14, count 2 2006.286.00:29:52.28#ibcon#read 5, iclass 14, count 2 2006.286.00:29:52.28#ibcon#about to read 6, iclass 14, count 2 2006.286.00:29:52.28#ibcon#read 6, iclass 14, count 2 2006.286.00:29:52.28#ibcon#end of sib2, iclass 14, count 2 2006.286.00:29:52.28#ibcon#*after write, iclass 14, count 2 2006.286.00:29:52.28#ibcon#*before return 0, iclass 14, count 2 2006.286.00:29:52.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:29:52.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.00:29:52.28#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.00:29:52.28#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:52.28#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:29:52.40#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:29:52.40#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:29:52.40#ibcon#enter wrdev, iclass 14, count 0 2006.286.00:29:52.40#ibcon#first serial, iclass 14, count 0 2006.286.00:29:52.40#ibcon#enter sib2, iclass 14, count 0 2006.286.00:29:52.40#ibcon#flushed, iclass 14, count 0 2006.286.00:29:52.40#ibcon#about to write, iclass 14, count 0 2006.286.00:29:52.40#ibcon#wrote, iclass 14, count 0 2006.286.00:29:52.40#ibcon#about to read 3, iclass 14, count 0 2006.286.00:29:52.42#ibcon#read 3, iclass 14, count 0 2006.286.00:29:52.42#ibcon#about to read 4, iclass 14, count 0 2006.286.00:29:52.42#ibcon#read 4, iclass 14, count 0 2006.286.00:29:52.42#ibcon#about to read 5, iclass 14, count 0 2006.286.00:29:52.42#ibcon#read 5, iclass 14, count 0 2006.286.00:29:52.42#ibcon#about to read 6, iclass 14, count 0 2006.286.00:29:52.42#ibcon#read 6, iclass 14, count 0 2006.286.00:29:52.42#ibcon#end of sib2, iclass 14, count 0 2006.286.00:29:52.42#ibcon#*mode == 0, iclass 14, count 0 2006.286.00:29:52.42#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.00:29:52.42#ibcon#[27=USB\r\n] 2006.286.00:29:52.42#ibcon#*before write, iclass 14, count 0 2006.286.00:29:52.42#ibcon#enter sib2, iclass 14, count 0 2006.286.00:29:52.42#ibcon#flushed, iclass 14, count 0 2006.286.00:29:52.42#ibcon#about to write, iclass 14, count 0 2006.286.00:29:52.42#ibcon#wrote, iclass 14, count 0 2006.286.00:29:52.42#ibcon#about to read 3, iclass 14, count 0 2006.286.00:29:52.45#ibcon#read 3, iclass 14, count 0 2006.286.00:29:52.45#ibcon#about to read 4, iclass 14, count 0 2006.286.00:29:52.45#ibcon#read 4, iclass 14, count 0 2006.286.00:29:52.45#ibcon#about to read 5, iclass 14, count 0 2006.286.00:29:52.45#ibcon#read 5, iclass 14, count 0 2006.286.00:29:52.45#ibcon#about to read 6, iclass 14, count 0 2006.286.00:29:52.45#ibcon#read 6, iclass 14, count 0 2006.286.00:29:52.45#ibcon#end of sib2, iclass 14, count 0 2006.286.00:29:52.45#ibcon#*after write, iclass 14, count 0 2006.286.00:29:52.45#ibcon#*before return 0, iclass 14, count 0 2006.286.00:29:52.45#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:29:52.45#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.00:29:52.45#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.00:29:52.45#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.00:29:52.45$vck44/vblo=8,744.99 2006.286.00:29:52.45#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.00:29:52.45#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.00:29:52.45#ibcon#ireg 17 cls_cnt 0 2006.286.00:29:52.45#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:29:52.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:29:52.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:29:52.45#ibcon#enter wrdev, iclass 16, count 0 2006.286.00:29:52.45#ibcon#first serial, iclass 16, count 0 2006.286.00:29:52.45#ibcon#enter sib2, iclass 16, count 0 2006.286.00:29:52.45#ibcon#flushed, iclass 16, count 0 2006.286.00:29:52.45#ibcon#about to write, iclass 16, count 0 2006.286.00:29:52.45#ibcon#wrote, iclass 16, count 0 2006.286.00:29:52.45#ibcon#about to read 3, iclass 16, count 0 2006.286.00:29:52.47#ibcon#read 3, iclass 16, count 0 2006.286.00:29:52.47#ibcon#about to read 4, iclass 16, count 0 2006.286.00:29:52.47#ibcon#read 4, iclass 16, count 0 2006.286.00:29:52.47#ibcon#about to read 5, iclass 16, count 0 2006.286.00:29:52.47#ibcon#read 5, iclass 16, count 0 2006.286.00:29:52.47#ibcon#about to read 6, iclass 16, count 0 2006.286.00:29:52.47#ibcon#read 6, iclass 16, count 0 2006.286.00:29:52.47#ibcon#end of sib2, iclass 16, count 0 2006.286.00:29:52.47#ibcon#*mode == 0, iclass 16, count 0 2006.286.00:29:52.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.00:29:52.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.00:29:52.47#ibcon#*before write, iclass 16, count 0 2006.286.00:29:52.47#ibcon#enter sib2, iclass 16, count 0 2006.286.00:29:52.47#ibcon#flushed, iclass 16, count 0 2006.286.00:29:52.47#ibcon#about to write, iclass 16, count 0 2006.286.00:29:52.47#ibcon#wrote, iclass 16, count 0 2006.286.00:29:52.47#ibcon#about to read 3, iclass 16, count 0 2006.286.00:29:52.51#ibcon#read 3, iclass 16, count 0 2006.286.00:29:52.51#ibcon#about to read 4, iclass 16, count 0 2006.286.00:29:52.51#ibcon#read 4, iclass 16, count 0 2006.286.00:29:52.51#ibcon#about to read 5, iclass 16, count 0 2006.286.00:29:52.51#ibcon#read 5, iclass 16, count 0 2006.286.00:29:52.51#ibcon#about to read 6, iclass 16, count 0 2006.286.00:29:52.51#ibcon#read 6, iclass 16, count 0 2006.286.00:29:52.51#ibcon#end of sib2, iclass 16, count 0 2006.286.00:29:52.51#ibcon#*after write, iclass 16, count 0 2006.286.00:29:52.51#ibcon#*before return 0, iclass 16, count 0 2006.286.00:29:52.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:29:52.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.00:29:52.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.00:29:52.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.00:29:52.51$vck44/vb=8,4 2006.286.00:29:52.51#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.00:29:52.51#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.00:29:52.51#ibcon#ireg 11 cls_cnt 2 2006.286.00:29:52.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:29:52.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:29:52.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:29:52.57#ibcon#enter wrdev, iclass 18, count 2 2006.286.00:29:52.57#ibcon#first serial, iclass 18, count 2 2006.286.00:29:52.57#ibcon#enter sib2, iclass 18, count 2 2006.286.00:29:52.57#ibcon#flushed, iclass 18, count 2 2006.286.00:29:52.57#ibcon#about to write, iclass 18, count 2 2006.286.00:29:52.57#ibcon#wrote, iclass 18, count 2 2006.286.00:29:52.57#ibcon#about to read 3, iclass 18, count 2 2006.286.00:29:52.59#ibcon#read 3, iclass 18, count 2 2006.286.00:29:52.59#ibcon#about to read 4, iclass 18, count 2 2006.286.00:29:52.59#ibcon#read 4, iclass 18, count 2 2006.286.00:29:52.59#ibcon#about to read 5, iclass 18, count 2 2006.286.00:29:52.59#ibcon#read 5, iclass 18, count 2 2006.286.00:29:52.59#ibcon#about to read 6, iclass 18, count 2 2006.286.00:29:52.59#ibcon#read 6, iclass 18, count 2 2006.286.00:29:52.59#ibcon#end of sib2, iclass 18, count 2 2006.286.00:29:52.59#ibcon#*mode == 0, iclass 18, count 2 2006.286.00:29:52.59#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.00:29:52.59#ibcon#[27=AT08-04\r\n] 2006.286.00:29:52.59#ibcon#*before write, iclass 18, count 2 2006.286.00:29:52.59#ibcon#enter sib2, iclass 18, count 2 2006.286.00:29:52.59#ibcon#flushed, iclass 18, count 2 2006.286.00:29:52.59#ibcon#about to write, iclass 18, count 2 2006.286.00:29:52.59#ibcon#wrote, iclass 18, count 2 2006.286.00:29:52.59#ibcon#about to read 3, iclass 18, count 2 2006.286.00:29:52.62#ibcon#read 3, iclass 18, count 2 2006.286.00:29:52.62#ibcon#about to read 4, iclass 18, count 2 2006.286.00:29:52.62#ibcon#read 4, iclass 18, count 2 2006.286.00:29:52.62#ibcon#about to read 5, iclass 18, count 2 2006.286.00:29:52.62#ibcon#read 5, iclass 18, count 2 2006.286.00:29:52.62#ibcon#about to read 6, iclass 18, count 2 2006.286.00:29:52.62#ibcon#read 6, iclass 18, count 2 2006.286.00:29:52.62#ibcon#end of sib2, iclass 18, count 2 2006.286.00:29:52.62#ibcon#*after write, iclass 18, count 2 2006.286.00:29:52.62#ibcon#*before return 0, iclass 18, count 2 2006.286.00:29:52.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:29:52.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.00:29:52.62#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.00:29:52.62#ibcon#ireg 7 cls_cnt 0 2006.286.00:29:52.62#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:29:52.65#abcon#<5=/03 3.3 7.4 19.90 851016.4\r\n> 2006.286.00:29:52.67#abcon#{5=INTERFACE CLEAR} 2006.286.00:29:52.73#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:29:52.74#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:29:52.74#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:29:52.74#ibcon#enter wrdev, iclass 18, count 0 2006.286.00:29:52.74#ibcon#first serial, iclass 18, count 0 2006.286.00:29:52.74#ibcon#enter sib2, iclass 18, count 0 2006.286.00:29:52.74#ibcon#flushed, iclass 18, count 0 2006.286.00:29:52.74#ibcon#about to write, iclass 18, count 0 2006.286.00:29:52.74#ibcon#wrote, iclass 18, count 0 2006.286.00:29:52.74#ibcon#about to read 3, iclass 18, count 0 2006.286.00:29:52.76#ibcon#read 3, iclass 18, count 0 2006.286.00:29:52.76#ibcon#about to read 4, iclass 18, count 0 2006.286.00:29:52.76#ibcon#read 4, iclass 18, count 0 2006.286.00:29:52.76#ibcon#about to read 5, iclass 18, count 0 2006.286.00:29:52.76#ibcon#read 5, iclass 18, count 0 2006.286.00:29:52.76#ibcon#about to read 6, iclass 18, count 0 2006.286.00:29:52.76#ibcon#read 6, iclass 18, count 0 2006.286.00:29:52.76#ibcon#end of sib2, iclass 18, count 0 2006.286.00:29:52.76#ibcon#*mode == 0, iclass 18, count 0 2006.286.00:29:52.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.00:29:52.76#ibcon#[27=USB\r\n] 2006.286.00:29:52.76#ibcon#*before write, iclass 18, count 0 2006.286.00:29:52.76#ibcon#enter sib2, iclass 18, count 0 2006.286.00:29:52.76#ibcon#flushed, iclass 18, count 0 2006.286.00:29:52.76#ibcon#about to write, iclass 18, count 0 2006.286.00:29:52.76#ibcon#wrote, iclass 18, count 0 2006.286.00:29:52.76#ibcon#about to read 3, iclass 18, count 0 2006.286.00:29:52.79#ibcon#read 3, iclass 18, count 0 2006.286.00:29:52.79#ibcon#about to read 4, iclass 18, count 0 2006.286.00:29:52.79#ibcon#read 4, iclass 18, count 0 2006.286.00:29:52.79#ibcon#about to read 5, iclass 18, count 0 2006.286.00:29:52.79#ibcon#read 5, iclass 18, count 0 2006.286.00:29:52.79#ibcon#about to read 6, iclass 18, count 0 2006.286.00:29:52.79#ibcon#read 6, iclass 18, count 0 2006.286.00:29:52.79#ibcon#end of sib2, iclass 18, count 0 2006.286.00:29:52.79#ibcon#*after write, iclass 18, count 0 2006.286.00:29:52.79#ibcon#*before return 0, iclass 18, count 0 2006.286.00:29:52.79#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:29:52.79#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.00:29:52.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.00:29:52.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.00:29:52.79$vck44/vabw=wide 2006.286.00:29:52.79#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.00:29:52.79#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.00:29:52.79#ibcon#ireg 8 cls_cnt 0 2006.286.00:29:52.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:29:52.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:29:52.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:29:52.79#ibcon#enter wrdev, iclass 24, count 0 2006.286.00:29:52.79#ibcon#first serial, iclass 24, count 0 2006.286.00:29:52.79#ibcon#enter sib2, iclass 24, count 0 2006.286.00:29:52.79#ibcon#flushed, iclass 24, count 0 2006.286.00:29:52.79#ibcon#about to write, iclass 24, count 0 2006.286.00:29:52.79#ibcon#wrote, iclass 24, count 0 2006.286.00:29:52.79#ibcon#about to read 3, iclass 24, count 0 2006.286.00:29:52.81#ibcon#read 3, iclass 24, count 0 2006.286.00:29:52.81#ibcon#about to read 4, iclass 24, count 0 2006.286.00:29:52.81#ibcon#read 4, iclass 24, count 0 2006.286.00:29:52.81#ibcon#about to read 5, iclass 24, count 0 2006.286.00:29:52.81#ibcon#read 5, iclass 24, count 0 2006.286.00:29:52.81#ibcon#about to read 6, iclass 24, count 0 2006.286.00:29:52.81#ibcon#read 6, iclass 24, count 0 2006.286.00:29:52.81#ibcon#end of sib2, iclass 24, count 0 2006.286.00:29:52.81#ibcon#*mode == 0, iclass 24, count 0 2006.286.00:29:52.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.00:29:52.81#ibcon#[25=BW32\r\n] 2006.286.00:29:52.81#ibcon#*before write, iclass 24, count 0 2006.286.00:29:52.81#ibcon#enter sib2, iclass 24, count 0 2006.286.00:29:52.81#ibcon#flushed, iclass 24, count 0 2006.286.00:29:52.81#ibcon#about to write, iclass 24, count 0 2006.286.00:29:52.81#ibcon#wrote, iclass 24, count 0 2006.286.00:29:52.81#ibcon#about to read 3, iclass 24, count 0 2006.286.00:29:52.84#ibcon#read 3, iclass 24, count 0 2006.286.00:29:52.84#ibcon#about to read 4, iclass 24, count 0 2006.286.00:29:52.84#ibcon#read 4, iclass 24, count 0 2006.286.00:29:52.84#ibcon#about to read 5, iclass 24, count 0 2006.286.00:29:52.84#ibcon#read 5, iclass 24, count 0 2006.286.00:29:52.84#ibcon#about to read 6, iclass 24, count 0 2006.286.00:29:52.84#ibcon#read 6, iclass 24, count 0 2006.286.00:29:52.84#ibcon#end of sib2, iclass 24, count 0 2006.286.00:29:52.84#ibcon#*after write, iclass 24, count 0 2006.286.00:29:52.84#ibcon#*before return 0, iclass 24, count 0 2006.286.00:29:52.84#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:29:52.84#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.00:29:52.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.00:29:52.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.00:29:52.84$vck44/vbbw=wide 2006.286.00:29:52.84#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.00:29:52.84#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.00:29:52.84#ibcon#ireg 8 cls_cnt 0 2006.286.00:29:52.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:29:52.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:29:52.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:29:52.91#ibcon#enter wrdev, iclass 26, count 0 2006.286.00:29:52.91#ibcon#first serial, iclass 26, count 0 2006.286.00:29:52.91#ibcon#enter sib2, iclass 26, count 0 2006.286.00:29:52.91#ibcon#flushed, iclass 26, count 0 2006.286.00:29:52.91#ibcon#about to write, iclass 26, count 0 2006.286.00:29:52.91#ibcon#wrote, iclass 26, count 0 2006.286.00:29:52.91#ibcon#about to read 3, iclass 26, count 0 2006.286.00:29:52.93#ibcon#read 3, iclass 26, count 0 2006.286.00:29:52.93#ibcon#about to read 4, iclass 26, count 0 2006.286.00:29:52.93#ibcon#read 4, iclass 26, count 0 2006.286.00:29:52.93#ibcon#about to read 5, iclass 26, count 0 2006.286.00:29:52.93#ibcon#read 5, iclass 26, count 0 2006.286.00:29:52.93#ibcon#about to read 6, iclass 26, count 0 2006.286.00:29:52.93#ibcon#read 6, iclass 26, count 0 2006.286.00:29:52.93#ibcon#end of sib2, iclass 26, count 0 2006.286.00:29:52.93#ibcon#*mode == 0, iclass 26, count 0 2006.286.00:29:52.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.00:29:52.93#ibcon#[27=BW32\r\n] 2006.286.00:29:52.93#ibcon#*before write, iclass 26, count 0 2006.286.00:29:52.93#ibcon#enter sib2, iclass 26, count 0 2006.286.00:29:52.93#ibcon#flushed, iclass 26, count 0 2006.286.00:29:52.93#ibcon#about to write, iclass 26, count 0 2006.286.00:29:52.93#ibcon#wrote, iclass 26, count 0 2006.286.00:29:52.93#ibcon#about to read 3, iclass 26, count 0 2006.286.00:29:52.96#ibcon#read 3, iclass 26, count 0 2006.286.00:29:52.96#ibcon#about to read 4, iclass 26, count 0 2006.286.00:29:52.96#ibcon#read 4, iclass 26, count 0 2006.286.00:29:52.96#ibcon#about to read 5, iclass 26, count 0 2006.286.00:29:52.96#ibcon#read 5, iclass 26, count 0 2006.286.00:29:52.96#ibcon#about to read 6, iclass 26, count 0 2006.286.00:29:52.96#ibcon#read 6, iclass 26, count 0 2006.286.00:29:52.96#ibcon#end of sib2, iclass 26, count 0 2006.286.00:29:52.96#ibcon#*after write, iclass 26, count 0 2006.286.00:29:52.96#ibcon#*before return 0, iclass 26, count 0 2006.286.00:29:52.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:29:52.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:29:52.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.00:29:52.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.00:29:52.96$setupk4/ifdk4 2006.286.00:29:52.96$ifdk4/lo= 2006.286.00:29:52.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.00:29:52.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.00:29:52.96$ifdk4/patch= 2006.286.00:29:52.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.00:29:52.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.00:29:52.97$setupk4/!*+20s 2006.286.00:30:02.82#abcon#<5=/03 3.4 7.4 19.90 851016.4\r\n> 2006.286.00:30:02.84#abcon#{5=INTERFACE CLEAR} 2006.286.00:30:02.90#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:30:04.14#trakl#Source acquired 2006.286.00:30:06.14#flagr#flagr/antenna,acquired 2006.286.00:30:07.48$setupk4/"tpicd 2006.286.00:30:07.48$setupk4/echo=off 2006.286.00:30:07.48$setupk4/xlog=off 2006.286.00:30:07.48:!2006.286.00:33:22 2006.286.00:33:22.00:preob 2006.286.00:33:22.13/onsource/TRACKING 2006.286.00:33:22.13:!2006.286.00:33:32 2006.286.00:33:32.00:"tape 2006.286.00:33:32.00:"st=record 2006.286.00:33:32.00:data_valid=on 2006.286.00:33:32.00:midob 2006.286.00:33:33.13/onsource/TRACKING 2006.286.00:33:33.13/wx/19.91,1016.4,85 2006.286.00:33:33.34/cable/+6.5068E-03 2006.286.00:33:34.43/va/01,07,usb,yes,31,34 2006.286.00:33:34.43/va/02,06,usb,yes,32,32 2006.286.00:33:34.43/va/03,07,usb,yes,31,33 2006.286.00:33:34.43/va/04,06,usb,yes,32,34 2006.286.00:33:34.43/va/05,03,usb,yes,32,32 2006.286.00:33:34.43/va/06,04,usb,yes,29,28 2006.286.00:33:34.43/va/07,04,usb,yes,29,30 2006.286.00:33:34.43/va/08,03,usb,yes,30,37 2006.286.00:33:34.66/valo/01,524.99,yes,locked 2006.286.00:33:34.66/valo/02,534.99,yes,locked 2006.286.00:33:34.66/valo/03,564.99,yes,locked 2006.286.00:33:34.66/valo/04,624.99,yes,locked 2006.286.00:33:34.66/valo/05,734.99,yes,locked 2006.286.00:33:34.66/valo/06,814.99,yes,locked 2006.286.00:33:34.66/valo/07,864.99,yes,locked 2006.286.00:33:34.66/valo/08,884.99,yes,locked 2006.286.00:33:35.75/vb/01,04,usb,yes,30,28 2006.286.00:33:35.75/vb/02,05,usb,yes,28,28 2006.286.00:33:35.75/vb/03,04,usb,yes,29,32 2006.286.00:33:35.75/vb/04,05,usb,yes,30,29 2006.286.00:33:35.75/vb/05,04,usb,yes,26,28 2006.286.00:33:35.75/vb/06,03,usb,yes,37,33 2006.286.00:33:35.75/vb/07,04,usb,yes,30,30 2006.286.00:33:35.75/vb/08,04,usb,yes,27,31 2006.286.00:33:35.98/vblo/01,629.99,yes,locked 2006.286.00:33:35.98/vblo/02,634.99,yes,locked 2006.286.00:33:35.98/vblo/03,649.99,yes,locked 2006.286.00:33:35.98/vblo/04,679.99,yes,locked 2006.286.00:33:35.98/vblo/05,709.99,yes,locked 2006.286.00:33:35.98/vblo/06,719.99,yes,locked 2006.286.00:33:35.98/vblo/07,734.99,yes,locked 2006.286.00:33:35.98/vblo/08,744.99,yes,locked 2006.286.00:33:36.13/vabw/8 2006.286.00:33:36.28/vbbw/8 2006.286.00:33:36.37/xfe/off,on,12.0 2006.286.00:33:36.74/ifatt/23,28,28,28 2006.286.00:33:37.07/fmout-gps/S +2.72E-07 2006.286.00:33:37.09:!2006.286.00:41:02 2006.286.00:41:02.00:data_valid=off 2006.286.00:41:02.00:"et 2006.286.00:41:02.00:!+3s 2006.286.00:41:05.01:"tape 2006.286.00:41:05.01:postob 2006.286.00:41:05.12/cable/+6.5054E-03 2006.286.00:41:05.12/wx/19.97,1016.4,87 2006.286.00:41:06.07/fmout-gps/S +2.81E-07 2006.286.00:41:06.07:scan_name=286-0046,jd0610,190 2006.286.00:41:06.07:source=0059+581,010245.76,582411.1,2000.0,cw 2006.286.00:41:06.13#flagr#flagr/antenna,new-source 2006.286.00:41:07.13:checkk5 2006.286.00:41:07.67/chk_autoobs//k5ts1/ autoobs is running! 2006.286.00:41:08.06/chk_autoobs//k5ts2/ autoobs is running! 2006.286.00:41:08.45/chk_autoobs//k5ts3/ autoobs is running! 2006.286.00:41:08.79/chk_autoobs//k5ts4/ autoobs is running! 2006.286.00:41:09.17/chk_obsdata//k5ts1/T2860033??a.dat file size is correct (nominal:1800MB, actual:1796MB). 2006.286.00:41:09.56/chk_obsdata//k5ts2/T2860033??b.dat file size is correct (nominal:1800MB, actual:1796MB). 2006.286.00:41:09.94/chk_obsdata//k5ts3/T2860033??c.dat file size is correct (nominal:1800MB, actual:1796MB). 2006.286.00:41:10.34/chk_obsdata//k5ts4/T2860033??d.dat file size is correct (nominal:1800MB, actual:1796MB). 2006.286.00:41:11.19/k5log//k5ts1_log_newline 2006.286.00:41:12.20/k5log//k5ts2_log_newline 2006.286.00:41:15.96/k5log//k5ts3_log_newline 2006.286.00:41:16.91/k5log//k5ts4_log_newline 2006.286.00:41:16.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.00:41:16.93:setupk4=1 2006.286.00:41:16.93$setupk4/echo=on 2006.286.00:41:16.93$setupk4/pcalon 2006.286.00:41:16.93$pcalon/"no phase cal control is implemented here 2006.286.00:41:16.93$setupk4/"tpicd=stop 2006.286.00:41:16.93$setupk4/"rec=synch_on 2006.286.00:41:16.93$setupk4/"rec_mode=128 2006.286.00:41:16.93$setupk4/!* 2006.286.00:41:16.93$setupk4/recpk4 2006.286.00:41:16.93$recpk4/recpatch= 2006.286.00:41:16.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.00:41:16.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.00:41:16.93$setupk4/vck44 2006.286.00:41:16.93$vck44/valo=1,524.99 2006.286.00:41:16.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.00:41:16.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.00:41:16.93#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:16.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:41:16.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:41:16.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:41:16.94#ibcon#enter wrdev, iclass 11, count 0 2006.286.00:41:16.94#ibcon#first serial, iclass 11, count 0 2006.286.00:41:16.94#ibcon#enter sib2, iclass 11, count 0 2006.286.00:41:16.94#ibcon#flushed, iclass 11, count 0 2006.286.00:41:16.94#ibcon#about to write, iclass 11, count 0 2006.286.00:41:16.94#ibcon#wrote, iclass 11, count 0 2006.286.00:41:16.94#ibcon#about to read 3, iclass 11, count 0 2006.286.00:41:16.95#ibcon#read 3, iclass 11, count 0 2006.286.00:41:16.95#ibcon#about to read 4, iclass 11, count 0 2006.286.00:41:16.95#ibcon#read 4, iclass 11, count 0 2006.286.00:41:16.95#ibcon#about to read 5, iclass 11, count 0 2006.286.00:41:16.95#ibcon#read 5, iclass 11, count 0 2006.286.00:41:16.95#ibcon#about to read 6, iclass 11, count 0 2006.286.00:41:16.95#ibcon#read 6, iclass 11, count 0 2006.286.00:41:16.95#ibcon#end of sib2, iclass 11, count 0 2006.286.00:41:16.95#ibcon#*mode == 0, iclass 11, count 0 2006.286.00:41:16.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.00:41:16.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.00:41:16.95#ibcon#*before write, iclass 11, count 0 2006.286.00:41:16.95#ibcon#enter sib2, iclass 11, count 0 2006.286.00:41:16.95#ibcon#flushed, iclass 11, count 0 2006.286.00:41:16.95#ibcon#about to write, iclass 11, count 0 2006.286.00:41:16.95#ibcon#wrote, iclass 11, count 0 2006.286.00:41:16.95#ibcon#about to read 3, iclass 11, count 0 2006.286.00:41:17.00#ibcon#read 3, iclass 11, count 0 2006.286.00:41:17.00#ibcon#about to read 4, iclass 11, count 0 2006.286.00:41:17.00#ibcon#read 4, iclass 11, count 0 2006.286.00:41:17.00#ibcon#about to read 5, iclass 11, count 0 2006.286.00:41:17.00#ibcon#read 5, iclass 11, count 0 2006.286.00:41:17.00#ibcon#about to read 6, iclass 11, count 0 2006.286.00:41:17.00#ibcon#read 6, iclass 11, count 0 2006.286.00:41:17.00#ibcon#end of sib2, iclass 11, count 0 2006.286.00:41:17.00#ibcon#*after write, iclass 11, count 0 2006.286.00:41:17.00#ibcon#*before return 0, iclass 11, count 0 2006.286.00:41:17.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:41:17.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:41:17.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.00:41:17.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.00:41:17.00$vck44/va=1,7 2006.286.00:41:17.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.00:41:17.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.00:41:17.00#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:17.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:41:17.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:41:17.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:41:17.00#ibcon#enter wrdev, iclass 13, count 2 2006.286.00:41:17.00#ibcon#first serial, iclass 13, count 2 2006.286.00:41:17.00#ibcon#enter sib2, iclass 13, count 2 2006.286.00:41:17.00#ibcon#flushed, iclass 13, count 2 2006.286.00:41:17.00#ibcon#about to write, iclass 13, count 2 2006.286.00:41:17.00#ibcon#wrote, iclass 13, count 2 2006.286.00:41:17.00#ibcon#about to read 3, iclass 13, count 2 2006.286.00:41:17.02#ibcon#read 3, iclass 13, count 2 2006.286.00:41:17.02#ibcon#about to read 4, iclass 13, count 2 2006.286.00:41:17.02#ibcon#read 4, iclass 13, count 2 2006.286.00:41:17.02#ibcon#about to read 5, iclass 13, count 2 2006.286.00:41:17.02#ibcon#read 5, iclass 13, count 2 2006.286.00:41:17.02#ibcon#about to read 6, iclass 13, count 2 2006.286.00:41:17.02#ibcon#read 6, iclass 13, count 2 2006.286.00:41:17.02#ibcon#end of sib2, iclass 13, count 2 2006.286.00:41:17.02#ibcon#*mode == 0, iclass 13, count 2 2006.286.00:41:17.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.00:41:17.02#ibcon#[25=AT01-07\r\n] 2006.286.00:41:17.02#ibcon#*before write, iclass 13, count 2 2006.286.00:41:17.02#ibcon#enter sib2, iclass 13, count 2 2006.286.00:41:17.02#ibcon#flushed, iclass 13, count 2 2006.286.00:41:17.02#ibcon#about to write, iclass 13, count 2 2006.286.00:41:17.02#ibcon#wrote, iclass 13, count 2 2006.286.00:41:17.02#ibcon#about to read 3, iclass 13, count 2 2006.286.00:41:17.05#ibcon#read 3, iclass 13, count 2 2006.286.00:41:17.05#ibcon#about to read 4, iclass 13, count 2 2006.286.00:41:17.05#ibcon#read 4, iclass 13, count 2 2006.286.00:41:17.05#ibcon#about to read 5, iclass 13, count 2 2006.286.00:41:17.05#ibcon#read 5, iclass 13, count 2 2006.286.00:41:17.05#ibcon#about to read 6, iclass 13, count 2 2006.286.00:41:17.05#ibcon#read 6, iclass 13, count 2 2006.286.00:41:17.05#ibcon#end of sib2, iclass 13, count 2 2006.286.00:41:17.05#ibcon#*after write, iclass 13, count 2 2006.286.00:41:17.05#ibcon#*before return 0, iclass 13, count 2 2006.286.00:41:17.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:41:17.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:41:17.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.00:41:17.05#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:17.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:41:17.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:41:17.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:41:17.17#ibcon#enter wrdev, iclass 13, count 0 2006.286.00:41:17.17#ibcon#first serial, iclass 13, count 0 2006.286.00:41:17.17#ibcon#enter sib2, iclass 13, count 0 2006.286.00:41:17.17#ibcon#flushed, iclass 13, count 0 2006.286.00:41:17.17#ibcon#about to write, iclass 13, count 0 2006.286.00:41:17.17#ibcon#wrote, iclass 13, count 0 2006.286.00:41:17.17#ibcon#about to read 3, iclass 13, count 0 2006.286.00:41:17.19#ibcon#read 3, iclass 13, count 0 2006.286.00:41:17.19#ibcon#about to read 4, iclass 13, count 0 2006.286.00:41:17.19#ibcon#read 4, iclass 13, count 0 2006.286.00:41:17.19#ibcon#about to read 5, iclass 13, count 0 2006.286.00:41:17.19#ibcon#read 5, iclass 13, count 0 2006.286.00:41:17.19#ibcon#about to read 6, iclass 13, count 0 2006.286.00:41:17.19#ibcon#read 6, iclass 13, count 0 2006.286.00:41:17.19#ibcon#end of sib2, iclass 13, count 0 2006.286.00:41:17.19#ibcon#*mode == 0, iclass 13, count 0 2006.286.00:41:17.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.00:41:17.19#ibcon#[25=USB\r\n] 2006.286.00:41:17.19#ibcon#*before write, iclass 13, count 0 2006.286.00:41:17.19#ibcon#enter sib2, iclass 13, count 0 2006.286.00:41:17.19#ibcon#flushed, iclass 13, count 0 2006.286.00:41:17.19#ibcon#about to write, iclass 13, count 0 2006.286.00:41:17.19#ibcon#wrote, iclass 13, count 0 2006.286.00:41:17.19#ibcon#about to read 3, iclass 13, count 0 2006.286.00:41:17.22#ibcon#read 3, iclass 13, count 0 2006.286.00:41:17.22#ibcon#about to read 4, iclass 13, count 0 2006.286.00:41:17.22#ibcon#read 4, iclass 13, count 0 2006.286.00:41:17.22#ibcon#about to read 5, iclass 13, count 0 2006.286.00:41:17.22#ibcon#read 5, iclass 13, count 0 2006.286.00:41:17.22#ibcon#about to read 6, iclass 13, count 0 2006.286.00:41:17.22#ibcon#read 6, iclass 13, count 0 2006.286.00:41:17.22#ibcon#end of sib2, iclass 13, count 0 2006.286.00:41:17.22#ibcon#*after write, iclass 13, count 0 2006.286.00:41:17.22#ibcon#*before return 0, iclass 13, count 0 2006.286.00:41:17.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:41:17.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:41:17.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.00:41:17.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.00:41:17.22$vck44/valo=2,534.99 2006.286.00:41:17.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.00:41:17.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.00:41:17.22#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:17.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:41:17.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:41:17.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:41:17.22#ibcon#enter wrdev, iclass 15, count 0 2006.286.00:41:17.22#ibcon#first serial, iclass 15, count 0 2006.286.00:41:17.22#ibcon#enter sib2, iclass 15, count 0 2006.286.00:41:17.22#ibcon#flushed, iclass 15, count 0 2006.286.00:41:17.22#ibcon#about to write, iclass 15, count 0 2006.286.00:41:17.22#ibcon#wrote, iclass 15, count 0 2006.286.00:41:17.22#ibcon#about to read 3, iclass 15, count 0 2006.286.00:41:17.24#ibcon#read 3, iclass 15, count 0 2006.286.00:41:17.24#ibcon#about to read 4, iclass 15, count 0 2006.286.00:41:17.24#ibcon#read 4, iclass 15, count 0 2006.286.00:41:17.24#ibcon#about to read 5, iclass 15, count 0 2006.286.00:41:17.24#ibcon#read 5, iclass 15, count 0 2006.286.00:41:17.24#ibcon#about to read 6, iclass 15, count 0 2006.286.00:41:17.24#ibcon#read 6, iclass 15, count 0 2006.286.00:41:17.24#ibcon#end of sib2, iclass 15, count 0 2006.286.00:41:17.24#ibcon#*mode == 0, iclass 15, count 0 2006.286.00:41:17.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.00:41:17.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.00:41:17.24#ibcon#*before write, iclass 15, count 0 2006.286.00:41:17.24#ibcon#enter sib2, iclass 15, count 0 2006.286.00:41:17.24#ibcon#flushed, iclass 15, count 0 2006.286.00:41:17.24#ibcon#about to write, iclass 15, count 0 2006.286.00:41:17.24#ibcon#wrote, iclass 15, count 0 2006.286.00:41:17.24#ibcon#about to read 3, iclass 15, count 0 2006.286.00:41:17.28#ibcon#read 3, iclass 15, count 0 2006.286.00:41:17.28#ibcon#about to read 4, iclass 15, count 0 2006.286.00:41:17.28#ibcon#read 4, iclass 15, count 0 2006.286.00:41:17.28#ibcon#about to read 5, iclass 15, count 0 2006.286.00:41:17.28#ibcon#read 5, iclass 15, count 0 2006.286.00:41:17.28#ibcon#about to read 6, iclass 15, count 0 2006.286.00:41:17.28#ibcon#read 6, iclass 15, count 0 2006.286.00:41:17.28#ibcon#end of sib2, iclass 15, count 0 2006.286.00:41:17.28#ibcon#*after write, iclass 15, count 0 2006.286.00:41:17.28#ibcon#*before return 0, iclass 15, count 0 2006.286.00:41:17.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:41:17.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:41:17.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.00:41:17.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.00:41:17.28$vck44/va=2,6 2006.286.00:41:17.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.00:41:17.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.00:41:17.28#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:17.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:41:17.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:41:17.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:41:17.34#ibcon#enter wrdev, iclass 17, count 2 2006.286.00:41:17.34#ibcon#first serial, iclass 17, count 2 2006.286.00:41:17.34#ibcon#enter sib2, iclass 17, count 2 2006.286.00:41:17.34#ibcon#flushed, iclass 17, count 2 2006.286.00:41:17.34#ibcon#about to write, iclass 17, count 2 2006.286.00:41:17.34#ibcon#wrote, iclass 17, count 2 2006.286.00:41:17.34#ibcon#about to read 3, iclass 17, count 2 2006.286.00:41:17.36#ibcon#read 3, iclass 17, count 2 2006.286.00:41:17.36#ibcon#about to read 4, iclass 17, count 2 2006.286.00:41:17.36#ibcon#read 4, iclass 17, count 2 2006.286.00:41:17.36#ibcon#about to read 5, iclass 17, count 2 2006.286.00:41:17.36#ibcon#read 5, iclass 17, count 2 2006.286.00:41:17.36#ibcon#about to read 6, iclass 17, count 2 2006.286.00:41:17.36#ibcon#read 6, iclass 17, count 2 2006.286.00:41:17.36#ibcon#end of sib2, iclass 17, count 2 2006.286.00:41:17.36#ibcon#*mode == 0, iclass 17, count 2 2006.286.00:41:17.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.00:41:17.36#ibcon#[25=AT02-06\r\n] 2006.286.00:41:17.36#ibcon#*before write, iclass 17, count 2 2006.286.00:41:17.36#ibcon#enter sib2, iclass 17, count 2 2006.286.00:41:17.36#ibcon#flushed, iclass 17, count 2 2006.286.00:41:17.36#ibcon#about to write, iclass 17, count 2 2006.286.00:41:17.36#ibcon#wrote, iclass 17, count 2 2006.286.00:41:17.36#ibcon#about to read 3, iclass 17, count 2 2006.286.00:41:17.39#ibcon#read 3, iclass 17, count 2 2006.286.00:41:17.39#ibcon#about to read 4, iclass 17, count 2 2006.286.00:41:17.39#ibcon#read 4, iclass 17, count 2 2006.286.00:41:17.39#ibcon#about to read 5, iclass 17, count 2 2006.286.00:41:17.39#ibcon#read 5, iclass 17, count 2 2006.286.00:41:17.39#ibcon#about to read 6, iclass 17, count 2 2006.286.00:41:17.39#ibcon#read 6, iclass 17, count 2 2006.286.00:41:17.39#ibcon#end of sib2, iclass 17, count 2 2006.286.00:41:17.39#ibcon#*after write, iclass 17, count 2 2006.286.00:41:17.39#ibcon#*before return 0, iclass 17, count 2 2006.286.00:41:17.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:41:17.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:41:17.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.00:41:17.39#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:17.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:41:17.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:41:17.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:41:17.51#ibcon#enter wrdev, iclass 17, count 0 2006.286.00:41:17.51#ibcon#first serial, iclass 17, count 0 2006.286.00:41:17.51#ibcon#enter sib2, iclass 17, count 0 2006.286.00:41:17.51#ibcon#flushed, iclass 17, count 0 2006.286.00:41:17.51#ibcon#about to write, iclass 17, count 0 2006.286.00:41:17.51#ibcon#wrote, iclass 17, count 0 2006.286.00:41:17.51#ibcon#about to read 3, iclass 17, count 0 2006.286.00:41:17.53#ibcon#read 3, iclass 17, count 0 2006.286.00:41:17.53#ibcon#about to read 4, iclass 17, count 0 2006.286.00:41:17.53#ibcon#read 4, iclass 17, count 0 2006.286.00:41:17.53#ibcon#about to read 5, iclass 17, count 0 2006.286.00:41:17.53#ibcon#read 5, iclass 17, count 0 2006.286.00:41:17.53#ibcon#about to read 6, iclass 17, count 0 2006.286.00:41:17.53#ibcon#read 6, iclass 17, count 0 2006.286.00:41:17.53#ibcon#end of sib2, iclass 17, count 0 2006.286.00:41:17.53#ibcon#*mode == 0, iclass 17, count 0 2006.286.00:41:17.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.00:41:17.53#ibcon#[25=USB\r\n] 2006.286.00:41:17.53#ibcon#*before write, iclass 17, count 0 2006.286.00:41:17.53#ibcon#enter sib2, iclass 17, count 0 2006.286.00:41:17.53#ibcon#flushed, iclass 17, count 0 2006.286.00:41:17.53#ibcon#about to write, iclass 17, count 0 2006.286.00:41:17.53#ibcon#wrote, iclass 17, count 0 2006.286.00:41:17.53#ibcon#about to read 3, iclass 17, count 0 2006.286.00:41:17.56#ibcon#read 3, iclass 17, count 0 2006.286.00:41:17.56#ibcon#about to read 4, iclass 17, count 0 2006.286.00:41:17.56#ibcon#read 4, iclass 17, count 0 2006.286.00:41:17.56#ibcon#about to read 5, iclass 17, count 0 2006.286.00:41:17.56#ibcon#read 5, iclass 17, count 0 2006.286.00:41:17.56#ibcon#about to read 6, iclass 17, count 0 2006.286.00:41:17.56#ibcon#read 6, iclass 17, count 0 2006.286.00:41:17.56#ibcon#end of sib2, iclass 17, count 0 2006.286.00:41:17.56#ibcon#*after write, iclass 17, count 0 2006.286.00:41:17.56#ibcon#*before return 0, iclass 17, count 0 2006.286.00:41:17.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:41:17.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:41:17.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.00:41:17.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.00:41:17.56$vck44/valo=3,564.99 2006.286.00:41:17.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.00:41:17.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.00:41:17.56#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:17.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:41:17.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:41:17.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:41:17.56#ibcon#enter wrdev, iclass 19, count 0 2006.286.00:41:17.56#ibcon#first serial, iclass 19, count 0 2006.286.00:41:17.56#ibcon#enter sib2, iclass 19, count 0 2006.286.00:41:17.56#ibcon#flushed, iclass 19, count 0 2006.286.00:41:17.56#ibcon#about to write, iclass 19, count 0 2006.286.00:41:17.56#ibcon#wrote, iclass 19, count 0 2006.286.00:41:17.56#ibcon#about to read 3, iclass 19, count 0 2006.286.00:41:17.58#ibcon#read 3, iclass 19, count 0 2006.286.00:41:17.58#ibcon#about to read 4, iclass 19, count 0 2006.286.00:41:17.58#ibcon#read 4, iclass 19, count 0 2006.286.00:41:17.58#ibcon#about to read 5, iclass 19, count 0 2006.286.00:41:17.58#ibcon#read 5, iclass 19, count 0 2006.286.00:41:17.58#ibcon#about to read 6, iclass 19, count 0 2006.286.00:41:17.58#ibcon#read 6, iclass 19, count 0 2006.286.00:41:17.58#ibcon#end of sib2, iclass 19, count 0 2006.286.00:41:17.58#ibcon#*mode == 0, iclass 19, count 0 2006.286.00:41:17.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.00:41:17.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.00:41:17.58#ibcon#*before write, iclass 19, count 0 2006.286.00:41:17.58#ibcon#enter sib2, iclass 19, count 0 2006.286.00:41:17.58#ibcon#flushed, iclass 19, count 0 2006.286.00:41:17.58#ibcon#about to write, iclass 19, count 0 2006.286.00:41:17.58#ibcon#wrote, iclass 19, count 0 2006.286.00:41:17.58#ibcon#about to read 3, iclass 19, count 0 2006.286.00:41:17.62#ibcon#read 3, iclass 19, count 0 2006.286.00:41:17.62#ibcon#about to read 4, iclass 19, count 0 2006.286.00:41:17.62#ibcon#read 4, iclass 19, count 0 2006.286.00:41:17.62#ibcon#about to read 5, iclass 19, count 0 2006.286.00:41:17.62#ibcon#read 5, iclass 19, count 0 2006.286.00:41:17.62#ibcon#about to read 6, iclass 19, count 0 2006.286.00:41:17.62#ibcon#read 6, iclass 19, count 0 2006.286.00:41:17.62#ibcon#end of sib2, iclass 19, count 0 2006.286.00:41:17.62#ibcon#*after write, iclass 19, count 0 2006.286.00:41:17.62#ibcon#*before return 0, iclass 19, count 0 2006.286.00:41:17.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:41:17.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:41:17.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.00:41:17.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.00:41:17.62$vck44/va=3,7 2006.286.00:41:17.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.00:41:17.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.00:41:17.62#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:17.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:41:17.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:41:17.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:41:17.68#ibcon#enter wrdev, iclass 21, count 2 2006.286.00:41:17.68#ibcon#first serial, iclass 21, count 2 2006.286.00:41:17.68#ibcon#enter sib2, iclass 21, count 2 2006.286.00:41:17.68#ibcon#flushed, iclass 21, count 2 2006.286.00:41:17.68#ibcon#about to write, iclass 21, count 2 2006.286.00:41:17.68#ibcon#wrote, iclass 21, count 2 2006.286.00:41:17.68#ibcon#about to read 3, iclass 21, count 2 2006.286.00:41:17.70#ibcon#read 3, iclass 21, count 2 2006.286.00:41:17.70#ibcon#about to read 4, iclass 21, count 2 2006.286.00:41:17.70#ibcon#read 4, iclass 21, count 2 2006.286.00:41:17.70#ibcon#about to read 5, iclass 21, count 2 2006.286.00:41:17.70#ibcon#read 5, iclass 21, count 2 2006.286.00:41:17.70#ibcon#about to read 6, iclass 21, count 2 2006.286.00:41:17.70#ibcon#read 6, iclass 21, count 2 2006.286.00:41:17.70#ibcon#end of sib2, iclass 21, count 2 2006.286.00:41:17.70#ibcon#*mode == 0, iclass 21, count 2 2006.286.00:41:17.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.00:41:17.70#ibcon#[25=AT03-07\r\n] 2006.286.00:41:17.70#ibcon#*before write, iclass 21, count 2 2006.286.00:41:17.70#ibcon#enter sib2, iclass 21, count 2 2006.286.00:41:17.70#ibcon#flushed, iclass 21, count 2 2006.286.00:41:17.70#ibcon#about to write, iclass 21, count 2 2006.286.00:41:17.70#ibcon#wrote, iclass 21, count 2 2006.286.00:41:17.70#ibcon#about to read 3, iclass 21, count 2 2006.286.00:41:17.73#ibcon#read 3, iclass 21, count 2 2006.286.00:41:17.73#ibcon#about to read 4, iclass 21, count 2 2006.286.00:41:17.73#ibcon#read 4, iclass 21, count 2 2006.286.00:41:17.73#ibcon#about to read 5, iclass 21, count 2 2006.286.00:41:17.73#ibcon#read 5, iclass 21, count 2 2006.286.00:41:17.73#ibcon#about to read 6, iclass 21, count 2 2006.286.00:41:17.73#ibcon#read 6, iclass 21, count 2 2006.286.00:41:17.73#ibcon#end of sib2, iclass 21, count 2 2006.286.00:41:17.73#ibcon#*after write, iclass 21, count 2 2006.286.00:41:17.73#ibcon#*before return 0, iclass 21, count 2 2006.286.00:41:17.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:41:17.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:41:17.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.00:41:17.73#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:17.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:41:17.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:41:17.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:41:17.85#ibcon#enter wrdev, iclass 21, count 0 2006.286.00:41:17.85#ibcon#first serial, iclass 21, count 0 2006.286.00:41:17.85#ibcon#enter sib2, iclass 21, count 0 2006.286.00:41:17.85#ibcon#flushed, iclass 21, count 0 2006.286.00:41:17.85#ibcon#about to write, iclass 21, count 0 2006.286.00:41:17.85#ibcon#wrote, iclass 21, count 0 2006.286.00:41:17.85#ibcon#about to read 3, iclass 21, count 0 2006.286.00:41:17.87#ibcon#read 3, iclass 21, count 0 2006.286.00:41:17.87#ibcon#about to read 4, iclass 21, count 0 2006.286.00:41:17.87#ibcon#read 4, iclass 21, count 0 2006.286.00:41:17.87#ibcon#about to read 5, iclass 21, count 0 2006.286.00:41:17.87#ibcon#read 5, iclass 21, count 0 2006.286.00:41:17.87#ibcon#about to read 6, iclass 21, count 0 2006.286.00:41:17.87#ibcon#read 6, iclass 21, count 0 2006.286.00:41:17.87#ibcon#end of sib2, iclass 21, count 0 2006.286.00:41:17.87#ibcon#*mode == 0, iclass 21, count 0 2006.286.00:41:17.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.00:41:17.87#ibcon#[25=USB\r\n] 2006.286.00:41:17.87#ibcon#*before write, iclass 21, count 0 2006.286.00:41:17.87#ibcon#enter sib2, iclass 21, count 0 2006.286.00:41:17.87#ibcon#flushed, iclass 21, count 0 2006.286.00:41:17.87#ibcon#about to write, iclass 21, count 0 2006.286.00:41:17.87#ibcon#wrote, iclass 21, count 0 2006.286.00:41:17.87#ibcon#about to read 3, iclass 21, count 0 2006.286.00:41:17.90#ibcon#read 3, iclass 21, count 0 2006.286.00:41:17.90#ibcon#about to read 4, iclass 21, count 0 2006.286.00:41:17.90#ibcon#read 4, iclass 21, count 0 2006.286.00:41:17.90#ibcon#about to read 5, iclass 21, count 0 2006.286.00:41:17.90#ibcon#read 5, iclass 21, count 0 2006.286.00:41:17.90#ibcon#about to read 6, iclass 21, count 0 2006.286.00:41:17.90#ibcon#read 6, iclass 21, count 0 2006.286.00:41:17.90#ibcon#end of sib2, iclass 21, count 0 2006.286.00:41:17.90#ibcon#*after write, iclass 21, count 0 2006.286.00:41:17.90#ibcon#*before return 0, iclass 21, count 0 2006.286.00:41:17.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:41:17.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:41:17.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.00:41:17.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.00:41:17.90$vck44/valo=4,624.99 2006.286.00:41:17.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.00:41:17.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.00:41:17.90#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:17.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:41:17.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:41:17.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:41:17.90#ibcon#enter wrdev, iclass 23, count 0 2006.286.00:41:17.90#ibcon#first serial, iclass 23, count 0 2006.286.00:41:17.90#ibcon#enter sib2, iclass 23, count 0 2006.286.00:41:17.90#ibcon#flushed, iclass 23, count 0 2006.286.00:41:17.90#ibcon#about to write, iclass 23, count 0 2006.286.00:41:17.90#ibcon#wrote, iclass 23, count 0 2006.286.00:41:17.90#ibcon#about to read 3, iclass 23, count 0 2006.286.00:41:17.92#ibcon#read 3, iclass 23, count 0 2006.286.00:41:17.92#ibcon#about to read 4, iclass 23, count 0 2006.286.00:41:17.92#ibcon#read 4, iclass 23, count 0 2006.286.00:41:17.92#ibcon#about to read 5, iclass 23, count 0 2006.286.00:41:17.92#ibcon#read 5, iclass 23, count 0 2006.286.00:41:17.92#ibcon#about to read 6, iclass 23, count 0 2006.286.00:41:17.92#ibcon#read 6, iclass 23, count 0 2006.286.00:41:17.92#ibcon#end of sib2, iclass 23, count 0 2006.286.00:41:17.92#ibcon#*mode == 0, iclass 23, count 0 2006.286.00:41:17.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.00:41:17.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.00:41:17.92#ibcon#*before write, iclass 23, count 0 2006.286.00:41:17.92#ibcon#enter sib2, iclass 23, count 0 2006.286.00:41:17.92#ibcon#flushed, iclass 23, count 0 2006.286.00:41:17.92#ibcon#about to write, iclass 23, count 0 2006.286.00:41:17.92#ibcon#wrote, iclass 23, count 0 2006.286.00:41:17.92#ibcon#about to read 3, iclass 23, count 0 2006.286.00:41:17.96#ibcon#read 3, iclass 23, count 0 2006.286.00:41:17.96#ibcon#about to read 4, iclass 23, count 0 2006.286.00:41:17.96#ibcon#read 4, iclass 23, count 0 2006.286.00:41:17.96#ibcon#about to read 5, iclass 23, count 0 2006.286.00:41:17.96#ibcon#read 5, iclass 23, count 0 2006.286.00:41:17.96#ibcon#about to read 6, iclass 23, count 0 2006.286.00:41:17.96#ibcon#read 6, iclass 23, count 0 2006.286.00:41:17.96#ibcon#end of sib2, iclass 23, count 0 2006.286.00:41:17.96#ibcon#*after write, iclass 23, count 0 2006.286.00:41:17.96#ibcon#*before return 0, iclass 23, count 0 2006.286.00:41:17.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:41:17.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:41:17.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.00:41:17.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.00:41:17.96$vck44/va=4,6 2006.286.00:41:17.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.00:41:17.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.00:41:17.96#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:17.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:41:18.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:41:18.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:41:18.02#ibcon#enter wrdev, iclass 25, count 2 2006.286.00:41:18.02#ibcon#first serial, iclass 25, count 2 2006.286.00:41:18.02#ibcon#enter sib2, iclass 25, count 2 2006.286.00:41:18.02#ibcon#flushed, iclass 25, count 2 2006.286.00:41:18.02#ibcon#about to write, iclass 25, count 2 2006.286.00:41:18.02#ibcon#wrote, iclass 25, count 2 2006.286.00:41:18.02#ibcon#about to read 3, iclass 25, count 2 2006.286.00:41:18.04#ibcon#read 3, iclass 25, count 2 2006.286.00:41:18.04#ibcon#about to read 4, iclass 25, count 2 2006.286.00:41:18.04#ibcon#read 4, iclass 25, count 2 2006.286.00:41:18.04#ibcon#about to read 5, iclass 25, count 2 2006.286.00:41:18.04#ibcon#read 5, iclass 25, count 2 2006.286.00:41:18.04#ibcon#about to read 6, iclass 25, count 2 2006.286.00:41:18.04#ibcon#read 6, iclass 25, count 2 2006.286.00:41:18.04#ibcon#end of sib2, iclass 25, count 2 2006.286.00:41:18.04#ibcon#*mode == 0, iclass 25, count 2 2006.286.00:41:18.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.00:41:18.04#ibcon#[25=AT04-06\r\n] 2006.286.00:41:18.04#ibcon#*before write, iclass 25, count 2 2006.286.00:41:18.04#ibcon#enter sib2, iclass 25, count 2 2006.286.00:41:18.04#ibcon#flushed, iclass 25, count 2 2006.286.00:41:18.04#ibcon#about to write, iclass 25, count 2 2006.286.00:41:18.04#ibcon#wrote, iclass 25, count 2 2006.286.00:41:18.04#ibcon#about to read 3, iclass 25, count 2 2006.286.00:41:18.07#ibcon#read 3, iclass 25, count 2 2006.286.00:41:18.07#ibcon#about to read 4, iclass 25, count 2 2006.286.00:41:18.07#ibcon#read 4, iclass 25, count 2 2006.286.00:41:18.07#ibcon#about to read 5, iclass 25, count 2 2006.286.00:41:18.07#ibcon#read 5, iclass 25, count 2 2006.286.00:41:18.07#ibcon#about to read 6, iclass 25, count 2 2006.286.00:41:18.07#ibcon#read 6, iclass 25, count 2 2006.286.00:41:18.07#ibcon#end of sib2, iclass 25, count 2 2006.286.00:41:18.07#ibcon#*after write, iclass 25, count 2 2006.286.00:41:18.07#ibcon#*before return 0, iclass 25, count 2 2006.286.00:41:18.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:41:18.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:41:18.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.00:41:18.07#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:18.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:41:18.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:41:18.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:41:18.19#ibcon#enter wrdev, iclass 25, count 0 2006.286.00:41:18.19#ibcon#first serial, iclass 25, count 0 2006.286.00:41:18.19#ibcon#enter sib2, iclass 25, count 0 2006.286.00:41:18.19#ibcon#flushed, iclass 25, count 0 2006.286.00:41:18.19#ibcon#about to write, iclass 25, count 0 2006.286.00:41:18.19#ibcon#wrote, iclass 25, count 0 2006.286.00:41:18.19#ibcon#about to read 3, iclass 25, count 0 2006.286.00:41:18.21#ibcon#read 3, iclass 25, count 0 2006.286.00:41:18.21#ibcon#about to read 4, iclass 25, count 0 2006.286.00:41:18.21#ibcon#read 4, iclass 25, count 0 2006.286.00:41:18.21#ibcon#about to read 5, iclass 25, count 0 2006.286.00:41:18.21#ibcon#read 5, iclass 25, count 0 2006.286.00:41:18.21#ibcon#about to read 6, iclass 25, count 0 2006.286.00:41:18.21#ibcon#read 6, iclass 25, count 0 2006.286.00:41:18.21#ibcon#end of sib2, iclass 25, count 0 2006.286.00:41:18.21#ibcon#*mode == 0, iclass 25, count 0 2006.286.00:41:18.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.00:41:18.21#ibcon#[25=USB\r\n] 2006.286.00:41:18.21#ibcon#*before write, iclass 25, count 0 2006.286.00:41:18.21#ibcon#enter sib2, iclass 25, count 0 2006.286.00:41:18.21#ibcon#flushed, iclass 25, count 0 2006.286.00:41:18.21#ibcon#about to write, iclass 25, count 0 2006.286.00:41:18.21#ibcon#wrote, iclass 25, count 0 2006.286.00:41:18.21#ibcon#about to read 3, iclass 25, count 0 2006.286.00:41:18.24#ibcon#read 3, iclass 25, count 0 2006.286.00:41:18.24#ibcon#about to read 4, iclass 25, count 0 2006.286.00:41:18.24#ibcon#read 4, iclass 25, count 0 2006.286.00:41:18.24#ibcon#about to read 5, iclass 25, count 0 2006.286.00:41:18.24#ibcon#read 5, iclass 25, count 0 2006.286.00:41:18.24#ibcon#about to read 6, iclass 25, count 0 2006.286.00:41:18.24#ibcon#read 6, iclass 25, count 0 2006.286.00:41:18.24#ibcon#end of sib2, iclass 25, count 0 2006.286.00:41:18.24#ibcon#*after write, iclass 25, count 0 2006.286.00:41:18.24#ibcon#*before return 0, iclass 25, count 0 2006.286.00:41:18.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:41:18.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:41:18.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.00:41:18.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.00:41:18.24$vck44/valo=5,734.99 2006.286.00:41:18.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.00:41:18.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.00:41:18.24#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:18.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:41:18.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:41:18.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:41:18.24#ibcon#enter wrdev, iclass 27, count 0 2006.286.00:41:18.24#ibcon#first serial, iclass 27, count 0 2006.286.00:41:18.24#ibcon#enter sib2, iclass 27, count 0 2006.286.00:41:18.24#ibcon#flushed, iclass 27, count 0 2006.286.00:41:18.24#ibcon#about to write, iclass 27, count 0 2006.286.00:41:18.24#ibcon#wrote, iclass 27, count 0 2006.286.00:41:18.24#ibcon#about to read 3, iclass 27, count 0 2006.286.00:41:18.26#ibcon#read 3, iclass 27, count 0 2006.286.00:41:18.26#ibcon#about to read 4, iclass 27, count 0 2006.286.00:41:18.26#ibcon#read 4, iclass 27, count 0 2006.286.00:41:18.26#ibcon#about to read 5, iclass 27, count 0 2006.286.00:41:18.26#ibcon#read 5, iclass 27, count 0 2006.286.00:41:18.26#ibcon#about to read 6, iclass 27, count 0 2006.286.00:41:18.26#ibcon#read 6, iclass 27, count 0 2006.286.00:41:18.26#ibcon#end of sib2, iclass 27, count 0 2006.286.00:41:18.26#ibcon#*mode == 0, iclass 27, count 0 2006.286.00:41:18.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.00:41:18.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.00:41:18.26#ibcon#*before write, iclass 27, count 0 2006.286.00:41:18.26#ibcon#enter sib2, iclass 27, count 0 2006.286.00:41:18.26#ibcon#flushed, iclass 27, count 0 2006.286.00:41:18.26#ibcon#about to write, iclass 27, count 0 2006.286.00:41:18.26#ibcon#wrote, iclass 27, count 0 2006.286.00:41:18.26#ibcon#about to read 3, iclass 27, count 0 2006.286.00:41:18.30#ibcon#read 3, iclass 27, count 0 2006.286.00:41:18.30#ibcon#about to read 4, iclass 27, count 0 2006.286.00:41:18.30#ibcon#read 4, iclass 27, count 0 2006.286.00:41:18.30#ibcon#about to read 5, iclass 27, count 0 2006.286.00:41:18.30#ibcon#read 5, iclass 27, count 0 2006.286.00:41:18.30#ibcon#about to read 6, iclass 27, count 0 2006.286.00:41:18.30#ibcon#read 6, iclass 27, count 0 2006.286.00:41:18.30#ibcon#end of sib2, iclass 27, count 0 2006.286.00:41:18.30#ibcon#*after write, iclass 27, count 0 2006.286.00:41:18.30#ibcon#*before return 0, iclass 27, count 0 2006.286.00:41:18.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:41:18.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:41:18.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.00:41:18.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.00:41:18.30$vck44/va=5,3 2006.286.00:41:18.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.00:41:18.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.00:41:18.30#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:18.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:41:18.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:41:18.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:41:18.36#ibcon#enter wrdev, iclass 29, count 2 2006.286.00:41:18.36#ibcon#first serial, iclass 29, count 2 2006.286.00:41:18.36#ibcon#enter sib2, iclass 29, count 2 2006.286.00:41:18.36#ibcon#flushed, iclass 29, count 2 2006.286.00:41:18.36#ibcon#about to write, iclass 29, count 2 2006.286.00:41:18.36#ibcon#wrote, iclass 29, count 2 2006.286.00:41:18.36#ibcon#about to read 3, iclass 29, count 2 2006.286.00:41:18.38#ibcon#read 3, iclass 29, count 2 2006.286.00:41:18.38#ibcon#about to read 4, iclass 29, count 2 2006.286.00:41:18.38#ibcon#read 4, iclass 29, count 2 2006.286.00:41:18.38#ibcon#about to read 5, iclass 29, count 2 2006.286.00:41:18.38#ibcon#read 5, iclass 29, count 2 2006.286.00:41:18.38#ibcon#about to read 6, iclass 29, count 2 2006.286.00:41:18.38#ibcon#read 6, iclass 29, count 2 2006.286.00:41:18.38#ibcon#end of sib2, iclass 29, count 2 2006.286.00:41:18.38#ibcon#*mode == 0, iclass 29, count 2 2006.286.00:41:18.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.00:41:18.38#ibcon#[25=AT05-03\r\n] 2006.286.00:41:18.38#ibcon#*before write, iclass 29, count 2 2006.286.00:41:18.38#ibcon#enter sib2, iclass 29, count 2 2006.286.00:41:18.38#ibcon#flushed, iclass 29, count 2 2006.286.00:41:18.38#ibcon#about to write, iclass 29, count 2 2006.286.00:41:18.38#ibcon#wrote, iclass 29, count 2 2006.286.00:41:18.38#ibcon#about to read 3, iclass 29, count 2 2006.286.00:41:18.41#ibcon#read 3, iclass 29, count 2 2006.286.00:41:18.41#ibcon#about to read 4, iclass 29, count 2 2006.286.00:41:18.41#ibcon#read 4, iclass 29, count 2 2006.286.00:41:18.41#ibcon#about to read 5, iclass 29, count 2 2006.286.00:41:18.41#ibcon#read 5, iclass 29, count 2 2006.286.00:41:18.41#ibcon#about to read 6, iclass 29, count 2 2006.286.00:41:18.41#ibcon#read 6, iclass 29, count 2 2006.286.00:41:18.41#ibcon#end of sib2, iclass 29, count 2 2006.286.00:41:18.41#ibcon#*after write, iclass 29, count 2 2006.286.00:41:18.41#ibcon#*before return 0, iclass 29, count 2 2006.286.00:41:18.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:41:18.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:41:18.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.00:41:18.41#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:18.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:41:18.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:41:18.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:41:18.53#ibcon#enter wrdev, iclass 29, count 0 2006.286.00:41:18.53#ibcon#first serial, iclass 29, count 0 2006.286.00:41:18.53#ibcon#enter sib2, iclass 29, count 0 2006.286.00:41:18.53#ibcon#flushed, iclass 29, count 0 2006.286.00:41:18.53#ibcon#about to write, iclass 29, count 0 2006.286.00:41:18.53#ibcon#wrote, iclass 29, count 0 2006.286.00:41:18.53#ibcon#about to read 3, iclass 29, count 0 2006.286.00:41:18.55#ibcon#read 3, iclass 29, count 0 2006.286.00:41:18.55#ibcon#about to read 4, iclass 29, count 0 2006.286.00:41:18.55#ibcon#read 4, iclass 29, count 0 2006.286.00:41:18.55#ibcon#about to read 5, iclass 29, count 0 2006.286.00:41:18.55#ibcon#read 5, iclass 29, count 0 2006.286.00:41:18.55#ibcon#about to read 6, iclass 29, count 0 2006.286.00:41:18.55#ibcon#read 6, iclass 29, count 0 2006.286.00:41:18.55#ibcon#end of sib2, iclass 29, count 0 2006.286.00:41:18.55#ibcon#*mode == 0, iclass 29, count 0 2006.286.00:41:18.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.00:41:18.55#ibcon#[25=USB\r\n] 2006.286.00:41:18.55#ibcon#*before write, iclass 29, count 0 2006.286.00:41:18.55#ibcon#enter sib2, iclass 29, count 0 2006.286.00:41:18.55#ibcon#flushed, iclass 29, count 0 2006.286.00:41:18.55#ibcon#about to write, iclass 29, count 0 2006.286.00:41:18.55#ibcon#wrote, iclass 29, count 0 2006.286.00:41:18.55#ibcon#about to read 3, iclass 29, count 0 2006.286.00:41:18.58#ibcon#read 3, iclass 29, count 0 2006.286.00:41:18.58#ibcon#about to read 4, iclass 29, count 0 2006.286.00:41:18.58#ibcon#read 4, iclass 29, count 0 2006.286.00:41:18.58#ibcon#about to read 5, iclass 29, count 0 2006.286.00:41:18.58#ibcon#read 5, iclass 29, count 0 2006.286.00:41:18.58#ibcon#about to read 6, iclass 29, count 0 2006.286.00:41:18.58#ibcon#read 6, iclass 29, count 0 2006.286.00:41:18.58#ibcon#end of sib2, iclass 29, count 0 2006.286.00:41:18.58#ibcon#*after write, iclass 29, count 0 2006.286.00:41:18.58#ibcon#*before return 0, iclass 29, count 0 2006.286.00:41:18.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:41:18.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:41:18.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.00:41:18.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.00:41:18.58$vck44/valo=6,814.99 2006.286.00:41:18.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.00:41:18.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.00:41:18.58#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:18.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:41:18.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:41:18.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:41:18.58#ibcon#enter wrdev, iclass 31, count 0 2006.286.00:41:18.58#ibcon#first serial, iclass 31, count 0 2006.286.00:41:18.58#ibcon#enter sib2, iclass 31, count 0 2006.286.00:41:18.58#ibcon#flushed, iclass 31, count 0 2006.286.00:41:18.58#ibcon#about to write, iclass 31, count 0 2006.286.00:41:18.58#ibcon#wrote, iclass 31, count 0 2006.286.00:41:18.58#ibcon#about to read 3, iclass 31, count 0 2006.286.00:41:18.60#ibcon#read 3, iclass 31, count 0 2006.286.00:41:18.60#ibcon#about to read 4, iclass 31, count 0 2006.286.00:41:18.60#ibcon#read 4, iclass 31, count 0 2006.286.00:41:18.60#ibcon#about to read 5, iclass 31, count 0 2006.286.00:41:18.60#ibcon#read 5, iclass 31, count 0 2006.286.00:41:18.60#ibcon#about to read 6, iclass 31, count 0 2006.286.00:41:18.60#ibcon#read 6, iclass 31, count 0 2006.286.00:41:18.60#ibcon#end of sib2, iclass 31, count 0 2006.286.00:41:18.60#ibcon#*mode == 0, iclass 31, count 0 2006.286.00:41:18.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.00:41:18.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.00:41:18.60#ibcon#*before write, iclass 31, count 0 2006.286.00:41:18.60#ibcon#enter sib2, iclass 31, count 0 2006.286.00:41:18.60#ibcon#flushed, iclass 31, count 0 2006.286.00:41:18.60#ibcon#about to write, iclass 31, count 0 2006.286.00:41:18.60#ibcon#wrote, iclass 31, count 0 2006.286.00:41:18.60#ibcon#about to read 3, iclass 31, count 0 2006.286.00:41:18.64#ibcon#read 3, iclass 31, count 0 2006.286.00:41:18.64#ibcon#about to read 4, iclass 31, count 0 2006.286.00:41:18.64#ibcon#read 4, iclass 31, count 0 2006.286.00:41:18.64#ibcon#about to read 5, iclass 31, count 0 2006.286.00:41:18.64#ibcon#read 5, iclass 31, count 0 2006.286.00:41:18.64#ibcon#about to read 6, iclass 31, count 0 2006.286.00:41:18.64#ibcon#read 6, iclass 31, count 0 2006.286.00:41:18.64#ibcon#end of sib2, iclass 31, count 0 2006.286.00:41:18.64#ibcon#*after write, iclass 31, count 0 2006.286.00:41:18.64#ibcon#*before return 0, iclass 31, count 0 2006.286.00:41:18.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:41:18.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:41:18.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.00:41:18.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.00:41:18.64$vck44/va=6,4 2006.286.00:41:18.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.00:41:18.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.00:41:18.64#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:18.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:41:18.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:41:18.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:41:18.70#ibcon#enter wrdev, iclass 33, count 2 2006.286.00:41:18.70#ibcon#first serial, iclass 33, count 2 2006.286.00:41:18.70#ibcon#enter sib2, iclass 33, count 2 2006.286.00:41:18.70#ibcon#flushed, iclass 33, count 2 2006.286.00:41:18.70#ibcon#about to write, iclass 33, count 2 2006.286.00:41:18.70#ibcon#wrote, iclass 33, count 2 2006.286.00:41:18.70#ibcon#about to read 3, iclass 33, count 2 2006.286.00:41:18.72#ibcon#read 3, iclass 33, count 2 2006.286.00:41:18.72#ibcon#about to read 4, iclass 33, count 2 2006.286.00:41:18.72#ibcon#read 4, iclass 33, count 2 2006.286.00:41:18.72#ibcon#about to read 5, iclass 33, count 2 2006.286.00:41:18.72#ibcon#read 5, iclass 33, count 2 2006.286.00:41:18.72#ibcon#about to read 6, iclass 33, count 2 2006.286.00:41:18.72#ibcon#read 6, iclass 33, count 2 2006.286.00:41:18.72#ibcon#end of sib2, iclass 33, count 2 2006.286.00:41:18.72#ibcon#*mode == 0, iclass 33, count 2 2006.286.00:41:18.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.00:41:18.72#ibcon#[25=AT06-04\r\n] 2006.286.00:41:18.72#ibcon#*before write, iclass 33, count 2 2006.286.00:41:18.72#ibcon#enter sib2, iclass 33, count 2 2006.286.00:41:18.72#ibcon#flushed, iclass 33, count 2 2006.286.00:41:18.72#ibcon#about to write, iclass 33, count 2 2006.286.00:41:18.72#ibcon#wrote, iclass 33, count 2 2006.286.00:41:18.72#ibcon#about to read 3, iclass 33, count 2 2006.286.00:41:18.75#ibcon#read 3, iclass 33, count 2 2006.286.00:41:18.75#ibcon#about to read 4, iclass 33, count 2 2006.286.00:41:18.75#ibcon#read 4, iclass 33, count 2 2006.286.00:41:18.75#ibcon#about to read 5, iclass 33, count 2 2006.286.00:41:18.75#ibcon#read 5, iclass 33, count 2 2006.286.00:41:18.75#ibcon#about to read 6, iclass 33, count 2 2006.286.00:41:18.75#ibcon#read 6, iclass 33, count 2 2006.286.00:41:18.75#ibcon#end of sib2, iclass 33, count 2 2006.286.00:41:18.75#ibcon#*after write, iclass 33, count 2 2006.286.00:41:18.75#ibcon#*before return 0, iclass 33, count 2 2006.286.00:41:18.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:41:18.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:41:18.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.00:41:18.75#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:18.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:41:18.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:41:18.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:41:18.87#ibcon#enter wrdev, iclass 33, count 0 2006.286.00:41:18.87#ibcon#first serial, iclass 33, count 0 2006.286.00:41:18.87#ibcon#enter sib2, iclass 33, count 0 2006.286.00:41:18.87#ibcon#flushed, iclass 33, count 0 2006.286.00:41:18.87#ibcon#about to write, iclass 33, count 0 2006.286.00:41:18.87#ibcon#wrote, iclass 33, count 0 2006.286.00:41:18.87#ibcon#about to read 3, iclass 33, count 0 2006.286.00:41:18.89#ibcon#read 3, iclass 33, count 0 2006.286.00:41:18.89#ibcon#about to read 4, iclass 33, count 0 2006.286.00:41:18.89#ibcon#read 4, iclass 33, count 0 2006.286.00:41:18.89#ibcon#about to read 5, iclass 33, count 0 2006.286.00:41:18.89#ibcon#read 5, iclass 33, count 0 2006.286.00:41:18.89#ibcon#about to read 6, iclass 33, count 0 2006.286.00:41:18.89#ibcon#read 6, iclass 33, count 0 2006.286.00:41:18.89#ibcon#end of sib2, iclass 33, count 0 2006.286.00:41:18.89#ibcon#*mode == 0, iclass 33, count 0 2006.286.00:41:18.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.00:41:18.89#ibcon#[25=USB\r\n] 2006.286.00:41:18.89#ibcon#*before write, iclass 33, count 0 2006.286.00:41:18.89#ibcon#enter sib2, iclass 33, count 0 2006.286.00:41:18.89#ibcon#flushed, iclass 33, count 0 2006.286.00:41:18.89#ibcon#about to write, iclass 33, count 0 2006.286.00:41:18.89#ibcon#wrote, iclass 33, count 0 2006.286.00:41:18.89#ibcon#about to read 3, iclass 33, count 0 2006.286.00:41:18.92#ibcon#read 3, iclass 33, count 0 2006.286.00:41:18.92#ibcon#about to read 4, iclass 33, count 0 2006.286.00:41:18.92#ibcon#read 4, iclass 33, count 0 2006.286.00:41:18.92#ibcon#about to read 5, iclass 33, count 0 2006.286.00:41:18.92#ibcon#read 5, iclass 33, count 0 2006.286.00:41:18.92#ibcon#about to read 6, iclass 33, count 0 2006.286.00:41:18.92#ibcon#read 6, iclass 33, count 0 2006.286.00:41:18.92#ibcon#end of sib2, iclass 33, count 0 2006.286.00:41:18.92#ibcon#*after write, iclass 33, count 0 2006.286.00:41:18.92#ibcon#*before return 0, iclass 33, count 0 2006.286.00:41:18.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:41:18.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:41:18.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.00:41:18.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.00:41:18.92$vck44/valo=7,864.99 2006.286.00:41:18.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.00:41:18.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.00:41:18.92#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:18.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:41:18.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:41:18.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:41:18.92#ibcon#enter wrdev, iclass 35, count 0 2006.286.00:41:18.92#ibcon#first serial, iclass 35, count 0 2006.286.00:41:18.92#ibcon#enter sib2, iclass 35, count 0 2006.286.00:41:18.92#ibcon#flushed, iclass 35, count 0 2006.286.00:41:18.92#ibcon#about to write, iclass 35, count 0 2006.286.00:41:18.92#ibcon#wrote, iclass 35, count 0 2006.286.00:41:18.92#ibcon#about to read 3, iclass 35, count 0 2006.286.00:41:18.94#ibcon#read 3, iclass 35, count 0 2006.286.00:41:18.94#ibcon#about to read 4, iclass 35, count 0 2006.286.00:41:18.94#ibcon#read 4, iclass 35, count 0 2006.286.00:41:18.94#ibcon#about to read 5, iclass 35, count 0 2006.286.00:41:18.94#ibcon#read 5, iclass 35, count 0 2006.286.00:41:18.94#ibcon#about to read 6, iclass 35, count 0 2006.286.00:41:18.94#ibcon#read 6, iclass 35, count 0 2006.286.00:41:18.94#ibcon#end of sib2, iclass 35, count 0 2006.286.00:41:18.94#ibcon#*mode == 0, iclass 35, count 0 2006.286.00:41:18.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.00:41:18.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.00:41:18.94#ibcon#*before write, iclass 35, count 0 2006.286.00:41:18.94#ibcon#enter sib2, iclass 35, count 0 2006.286.00:41:18.94#ibcon#flushed, iclass 35, count 0 2006.286.00:41:18.94#ibcon#about to write, iclass 35, count 0 2006.286.00:41:18.94#ibcon#wrote, iclass 35, count 0 2006.286.00:41:18.94#ibcon#about to read 3, iclass 35, count 0 2006.286.00:41:18.98#ibcon#read 3, iclass 35, count 0 2006.286.00:41:18.98#ibcon#about to read 4, iclass 35, count 0 2006.286.00:41:18.98#ibcon#read 4, iclass 35, count 0 2006.286.00:41:18.98#ibcon#about to read 5, iclass 35, count 0 2006.286.00:41:18.98#ibcon#read 5, iclass 35, count 0 2006.286.00:41:18.98#ibcon#about to read 6, iclass 35, count 0 2006.286.00:41:18.98#ibcon#read 6, iclass 35, count 0 2006.286.00:41:18.98#ibcon#end of sib2, iclass 35, count 0 2006.286.00:41:18.98#ibcon#*after write, iclass 35, count 0 2006.286.00:41:18.98#ibcon#*before return 0, iclass 35, count 0 2006.286.00:41:18.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:41:18.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:41:18.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.00:41:18.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.00:41:18.98$vck44/va=7,4 2006.286.00:41:18.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.00:41:18.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.00:41:18.98#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:18.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:41:19.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:41:19.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:41:19.04#ibcon#enter wrdev, iclass 37, count 2 2006.286.00:41:19.04#ibcon#first serial, iclass 37, count 2 2006.286.00:41:19.04#ibcon#enter sib2, iclass 37, count 2 2006.286.00:41:19.04#ibcon#flushed, iclass 37, count 2 2006.286.00:41:19.04#ibcon#about to write, iclass 37, count 2 2006.286.00:41:19.04#ibcon#wrote, iclass 37, count 2 2006.286.00:41:19.04#ibcon#about to read 3, iclass 37, count 2 2006.286.00:41:19.06#ibcon#read 3, iclass 37, count 2 2006.286.00:41:19.06#ibcon#about to read 4, iclass 37, count 2 2006.286.00:41:19.06#ibcon#read 4, iclass 37, count 2 2006.286.00:41:19.06#ibcon#about to read 5, iclass 37, count 2 2006.286.00:41:19.06#ibcon#read 5, iclass 37, count 2 2006.286.00:41:19.06#ibcon#about to read 6, iclass 37, count 2 2006.286.00:41:19.06#ibcon#read 6, iclass 37, count 2 2006.286.00:41:19.06#ibcon#end of sib2, iclass 37, count 2 2006.286.00:41:19.06#ibcon#*mode == 0, iclass 37, count 2 2006.286.00:41:19.06#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.00:41:19.06#ibcon#[25=AT07-04\r\n] 2006.286.00:41:19.06#ibcon#*before write, iclass 37, count 2 2006.286.00:41:19.06#ibcon#enter sib2, iclass 37, count 2 2006.286.00:41:19.06#ibcon#flushed, iclass 37, count 2 2006.286.00:41:19.06#ibcon#about to write, iclass 37, count 2 2006.286.00:41:19.06#ibcon#wrote, iclass 37, count 2 2006.286.00:41:19.06#ibcon#about to read 3, iclass 37, count 2 2006.286.00:41:19.09#ibcon#read 3, iclass 37, count 2 2006.286.00:41:19.09#ibcon#about to read 4, iclass 37, count 2 2006.286.00:41:19.09#ibcon#read 4, iclass 37, count 2 2006.286.00:41:19.09#ibcon#about to read 5, iclass 37, count 2 2006.286.00:41:19.09#ibcon#read 5, iclass 37, count 2 2006.286.00:41:19.09#ibcon#about to read 6, iclass 37, count 2 2006.286.00:41:19.09#ibcon#read 6, iclass 37, count 2 2006.286.00:41:19.09#ibcon#end of sib2, iclass 37, count 2 2006.286.00:41:19.09#ibcon#*after write, iclass 37, count 2 2006.286.00:41:19.09#ibcon#*before return 0, iclass 37, count 2 2006.286.00:41:19.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:41:19.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:41:19.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.00:41:19.09#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:19.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:41:19.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:41:19.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:41:19.21#ibcon#enter wrdev, iclass 37, count 0 2006.286.00:41:19.21#ibcon#first serial, iclass 37, count 0 2006.286.00:41:19.21#ibcon#enter sib2, iclass 37, count 0 2006.286.00:41:19.21#ibcon#flushed, iclass 37, count 0 2006.286.00:41:19.21#ibcon#about to write, iclass 37, count 0 2006.286.00:41:19.21#ibcon#wrote, iclass 37, count 0 2006.286.00:41:19.21#ibcon#about to read 3, iclass 37, count 0 2006.286.00:41:19.23#ibcon#read 3, iclass 37, count 0 2006.286.00:41:19.23#ibcon#about to read 4, iclass 37, count 0 2006.286.00:41:19.23#ibcon#read 4, iclass 37, count 0 2006.286.00:41:19.23#ibcon#about to read 5, iclass 37, count 0 2006.286.00:41:19.23#ibcon#read 5, iclass 37, count 0 2006.286.00:41:19.23#ibcon#about to read 6, iclass 37, count 0 2006.286.00:41:19.23#ibcon#read 6, iclass 37, count 0 2006.286.00:41:19.23#ibcon#end of sib2, iclass 37, count 0 2006.286.00:41:19.23#ibcon#*mode == 0, iclass 37, count 0 2006.286.00:41:19.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.00:41:19.23#ibcon#[25=USB\r\n] 2006.286.00:41:19.23#ibcon#*before write, iclass 37, count 0 2006.286.00:41:19.23#ibcon#enter sib2, iclass 37, count 0 2006.286.00:41:19.23#ibcon#flushed, iclass 37, count 0 2006.286.00:41:19.23#ibcon#about to write, iclass 37, count 0 2006.286.00:41:19.23#ibcon#wrote, iclass 37, count 0 2006.286.00:41:19.23#ibcon#about to read 3, iclass 37, count 0 2006.286.00:41:19.26#ibcon#read 3, iclass 37, count 0 2006.286.00:41:19.26#ibcon#about to read 4, iclass 37, count 0 2006.286.00:41:19.26#ibcon#read 4, iclass 37, count 0 2006.286.00:41:19.26#ibcon#about to read 5, iclass 37, count 0 2006.286.00:41:19.26#ibcon#read 5, iclass 37, count 0 2006.286.00:41:19.26#ibcon#about to read 6, iclass 37, count 0 2006.286.00:41:19.26#ibcon#read 6, iclass 37, count 0 2006.286.00:41:19.26#ibcon#end of sib2, iclass 37, count 0 2006.286.00:41:19.26#ibcon#*after write, iclass 37, count 0 2006.286.00:41:19.26#ibcon#*before return 0, iclass 37, count 0 2006.286.00:41:19.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:41:19.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:41:19.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.00:41:19.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.00:41:19.26$vck44/valo=8,884.99 2006.286.00:41:19.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.00:41:19.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.00:41:19.26#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:19.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:41:19.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:41:19.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:41:19.26#ibcon#enter wrdev, iclass 39, count 0 2006.286.00:41:19.26#ibcon#first serial, iclass 39, count 0 2006.286.00:41:19.26#ibcon#enter sib2, iclass 39, count 0 2006.286.00:41:19.26#ibcon#flushed, iclass 39, count 0 2006.286.00:41:19.26#ibcon#about to write, iclass 39, count 0 2006.286.00:41:19.26#ibcon#wrote, iclass 39, count 0 2006.286.00:41:19.26#ibcon#about to read 3, iclass 39, count 0 2006.286.00:41:19.28#ibcon#read 3, iclass 39, count 0 2006.286.00:41:19.28#ibcon#about to read 4, iclass 39, count 0 2006.286.00:41:19.28#ibcon#read 4, iclass 39, count 0 2006.286.00:41:19.28#ibcon#about to read 5, iclass 39, count 0 2006.286.00:41:19.28#ibcon#read 5, iclass 39, count 0 2006.286.00:41:19.28#ibcon#about to read 6, iclass 39, count 0 2006.286.00:41:19.28#ibcon#read 6, iclass 39, count 0 2006.286.00:41:19.28#ibcon#end of sib2, iclass 39, count 0 2006.286.00:41:19.28#ibcon#*mode == 0, iclass 39, count 0 2006.286.00:41:19.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.00:41:19.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.00:41:19.28#ibcon#*before write, iclass 39, count 0 2006.286.00:41:19.28#ibcon#enter sib2, iclass 39, count 0 2006.286.00:41:19.28#ibcon#flushed, iclass 39, count 0 2006.286.00:41:19.28#ibcon#about to write, iclass 39, count 0 2006.286.00:41:19.28#ibcon#wrote, iclass 39, count 0 2006.286.00:41:19.28#ibcon#about to read 3, iclass 39, count 0 2006.286.00:41:19.32#ibcon#read 3, iclass 39, count 0 2006.286.00:41:19.32#ibcon#about to read 4, iclass 39, count 0 2006.286.00:41:19.32#ibcon#read 4, iclass 39, count 0 2006.286.00:41:19.32#ibcon#about to read 5, iclass 39, count 0 2006.286.00:41:19.32#ibcon#read 5, iclass 39, count 0 2006.286.00:41:19.32#ibcon#about to read 6, iclass 39, count 0 2006.286.00:41:19.32#ibcon#read 6, iclass 39, count 0 2006.286.00:41:19.32#ibcon#end of sib2, iclass 39, count 0 2006.286.00:41:19.32#ibcon#*after write, iclass 39, count 0 2006.286.00:41:19.32#ibcon#*before return 0, iclass 39, count 0 2006.286.00:41:19.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:41:19.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:41:19.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.00:41:19.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.00:41:19.32$vck44/va=8,3 2006.286.00:41:19.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.00:41:19.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.00:41:19.32#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:19.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:41:19.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:41:19.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:41:19.38#ibcon#enter wrdev, iclass 3, count 2 2006.286.00:41:19.38#ibcon#first serial, iclass 3, count 2 2006.286.00:41:19.38#ibcon#enter sib2, iclass 3, count 2 2006.286.00:41:19.38#ibcon#flushed, iclass 3, count 2 2006.286.00:41:19.38#ibcon#about to write, iclass 3, count 2 2006.286.00:41:19.38#ibcon#wrote, iclass 3, count 2 2006.286.00:41:19.38#ibcon#about to read 3, iclass 3, count 2 2006.286.00:41:19.40#ibcon#read 3, iclass 3, count 2 2006.286.00:41:19.40#ibcon#about to read 4, iclass 3, count 2 2006.286.00:41:19.40#ibcon#read 4, iclass 3, count 2 2006.286.00:41:19.40#ibcon#about to read 5, iclass 3, count 2 2006.286.00:41:19.40#ibcon#read 5, iclass 3, count 2 2006.286.00:41:19.40#ibcon#about to read 6, iclass 3, count 2 2006.286.00:41:19.40#ibcon#read 6, iclass 3, count 2 2006.286.00:41:19.40#ibcon#end of sib2, iclass 3, count 2 2006.286.00:41:19.40#ibcon#*mode == 0, iclass 3, count 2 2006.286.00:41:19.40#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.00:41:19.40#ibcon#[25=AT08-03\r\n] 2006.286.00:41:19.40#ibcon#*before write, iclass 3, count 2 2006.286.00:41:19.40#ibcon#enter sib2, iclass 3, count 2 2006.286.00:41:19.40#ibcon#flushed, iclass 3, count 2 2006.286.00:41:19.40#ibcon#about to write, iclass 3, count 2 2006.286.00:41:19.40#ibcon#wrote, iclass 3, count 2 2006.286.00:41:19.40#ibcon#about to read 3, iclass 3, count 2 2006.286.00:41:19.43#ibcon#read 3, iclass 3, count 2 2006.286.00:41:19.43#ibcon#about to read 4, iclass 3, count 2 2006.286.00:41:19.43#ibcon#read 4, iclass 3, count 2 2006.286.00:41:19.43#ibcon#about to read 5, iclass 3, count 2 2006.286.00:41:19.43#ibcon#read 5, iclass 3, count 2 2006.286.00:41:19.43#ibcon#about to read 6, iclass 3, count 2 2006.286.00:41:19.43#ibcon#read 6, iclass 3, count 2 2006.286.00:41:19.43#ibcon#end of sib2, iclass 3, count 2 2006.286.00:41:19.43#ibcon#*after write, iclass 3, count 2 2006.286.00:41:19.43#ibcon#*before return 0, iclass 3, count 2 2006.286.00:41:19.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:41:19.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.00:41:19.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.00:41:19.43#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:19.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:41:19.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:41:19.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:41:19.55#ibcon#enter wrdev, iclass 3, count 0 2006.286.00:41:19.55#ibcon#first serial, iclass 3, count 0 2006.286.00:41:19.55#ibcon#enter sib2, iclass 3, count 0 2006.286.00:41:19.55#ibcon#flushed, iclass 3, count 0 2006.286.00:41:19.55#ibcon#about to write, iclass 3, count 0 2006.286.00:41:19.55#ibcon#wrote, iclass 3, count 0 2006.286.00:41:19.55#ibcon#about to read 3, iclass 3, count 0 2006.286.00:41:19.57#ibcon#read 3, iclass 3, count 0 2006.286.00:41:19.57#ibcon#about to read 4, iclass 3, count 0 2006.286.00:41:19.57#ibcon#read 4, iclass 3, count 0 2006.286.00:41:19.57#ibcon#about to read 5, iclass 3, count 0 2006.286.00:41:19.57#ibcon#read 5, iclass 3, count 0 2006.286.00:41:19.57#ibcon#about to read 6, iclass 3, count 0 2006.286.00:41:19.57#ibcon#read 6, iclass 3, count 0 2006.286.00:41:19.57#ibcon#end of sib2, iclass 3, count 0 2006.286.00:41:19.57#ibcon#*mode == 0, iclass 3, count 0 2006.286.00:41:19.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.00:41:19.57#ibcon#[25=USB\r\n] 2006.286.00:41:19.57#ibcon#*before write, iclass 3, count 0 2006.286.00:41:19.57#ibcon#enter sib2, iclass 3, count 0 2006.286.00:41:19.57#ibcon#flushed, iclass 3, count 0 2006.286.00:41:19.57#ibcon#about to write, iclass 3, count 0 2006.286.00:41:19.57#ibcon#wrote, iclass 3, count 0 2006.286.00:41:19.57#ibcon#about to read 3, iclass 3, count 0 2006.286.00:41:19.60#ibcon#read 3, iclass 3, count 0 2006.286.00:41:19.60#ibcon#about to read 4, iclass 3, count 0 2006.286.00:41:19.60#ibcon#read 4, iclass 3, count 0 2006.286.00:41:19.60#ibcon#about to read 5, iclass 3, count 0 2006.286.00:41:19.60#ibcon#read 5, iclass 3, count 0 2006.286.00:41:19.60#ibcon#about to read 6, iclass 3, count 0 2006.286.00:41:19.60#ibcon#read 6, iclass 3, count 0 2006.286.00:41:19.60#ibcon#end of sib2, iclass 3, count 0 2006.286.00:41:19.60#ibcon#*after write, iclass 3, count 0 2006.286.00:41:19.60#ibcon#*before return 0, iclass 3, count 0 2006.286.00:41:19.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:41:19.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.00:41:19.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.00:41:19.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.00:41:19.60$vck44/vblo=1,629.99 2006.286.00:41:19.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.00:41:19.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.00:41:19.60#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:19.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:41:19.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:41:19.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:41:19.60#ibcon#enter wrdev, iclass 5, count 0 2006.286.00:41:19.60#ibcon#first serial, iclass 5, count 0 2006.286.00:41:19.60#ibcon#enter sib2, iclass 5, count 0 2006.286.00:41:19.60#ibcon#flushed, iclass 5, count 0 2006.286.00:41:19.60#ibcon#about to write, iclass 5, count 0 2006.286.00:41:19.60#ibcon#wrote, iclass 5, count 0 2006.286.00:41:19.60#ibcon#about to read 3, iclass 5, count 0 2006.286.00:41:19.62#ibcon#read 3, iclass 5, count 0 2006.286.00:41:19.62#ibcon#about to read 4, iclass 5, count 0 2006.286.00:41:19.62#ibcon#read 4, iclass 5, count 0 2006.286.00:41:19.62#ibcon#about to read 5, iclass 5, count 0 2006.286.00:41:19.62#ibcon#read 5, iclass 5, count 0 2006.286.00:41:19.62#ibcon#about to read 6, iclass 5, count 0 2006.286.00:41:19.62#ibcon#read 6, iclass 5, count 0 2006.286.00:41:19.62#ibcon#end of sib2, iclass 5, count 0 2006.286.00:41:19.62#ibcon#*mode == 0, iclass 5, count 0 2006.286.00:41:19.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.00:41:19.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.00:41:19.62#ibcon#*before write, iclass 5, count 0 2006.286.00:41:19.62#ibcon#enter sib2, iclass 5, count 0 2006.286.00:41:19.62#ibcon#flushed, iclass 5, count 0 2006.286.00:41:19.62#ibcon#about to write, iclass 5, count 0 2006.286.00:41:19.62#ibcon#wrote, iclass 5, count 0 2006.286.00:41:19.62#ibcon#about to read 3, iclass 5, count 0 2006.286.00:41:19.66#ibcon#read 3, iclass 5, count 0 2006.286.00:41:19.66#ibcon#about to read 4, iclass 5, count 0 2006.286.00:41:19.66#ibcon#read 4, iclass 5, count 0 2006.286.00:41:19.66#ibcon#about to read 5, iclass 5, count 0 2006.286.00:41:19.66#ibcon#read 5, iclass 5, count 0 2006.286.00:41:19.66#ibcon#about to read 6, iclass 5, count 0 2006.286.00:41:19.66#ibcon#read 6, iclass 5, count 0 2006.286.00:41:19.66#ibcon#end of sib2, iclass 5, count 0 2006.286.00:41:19.66#ibcon#*after write, iclass 5, count 0 2006.286.00:41:19.66#ibcon#*before return 0, iclass 5, count 0 2006.286.00:41:19.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:41:19.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.00:41:19.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.00:41:19.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.00:41:19.66$vck44/vb=1,4 2006.286.00:41:19.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.00:41:19.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.00:41:19.66#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:19.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:41:19.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:41:19.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:41:19.66#ibcon#enter wrdev, iclass 7, count 2 2006.286.00:41:19.66#ibcon#first serial, iclass 7, count 2 2006.286.00:41:19.66#ibcon#enter sib2, iclass 7, count 2 2006.286.00:41:19.66#ibcon#flushed, iclass 7, count 2 2006.286.00:41:19.66#ibcon#about to write, iclass 7, count 2 2006.286.00:41:19.66#ibcon#wrote, iclass 7, count 2 2006.286.00:41:19.66#ibcon#about to read 3, iclass 7, count 2 2006.286.00:41:19.68#ibcon#read 3, iclass 7, count 2 2006.286.00:41:19.68#ibcon#about to read 4, iclass 7, count 2 2006.286.00:41:19.68#ibcon#read 4, iclass 7, count 2 2006.286.00:41:19.68#ibcon#about to read 5, iclass 7, count 2 2006.286.00:41:19.68#ibcon#read 5, iclass 7, count 2 2006.286.00:41:19.68#ibcon#about to read 6, iclass 7, count 2 2006.286.00:41:19.68#ibcon#read 6, iclass 7, count 2 2006.286.00:41:19.68#ibcon#end of sib2, iclass 7, count 2 2006.286.00:41:19.68#ibcon#*mode == 0, iclass 7, count 2 2006.286.00:41:19.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.00:41:19.68#ibcon#[27=AT01-04\r\n] 2006.286.00:41:19.68#ibcon#*before write, iclass 7, count 2 2006.286.00:41:19.68#ibcon#enter sib2, iclass 7, count 2 2006.286.00:41:19.68#ibcon#flushed, iclass 7, count 2 2006.286.00:41:19.68#ibcon#about to write, iclass 7, count 2 2006.286.00:41:19.68#ibcon#wrote, iclass 7, count 2 2006.286.00:41:19.68#ibcon#about to read 3, iclass 7, count 2 2006.286.00:41:19.71#ibcon#read 3, iclass 7, count 2 2006.286.00:41:19.71#ibcon#about to read 4, iclass 7, count 2 2006.286.00:41:19.71#ibcon#read 4, iclass 7, count 2 2006.286.00:41:19.71#ibcon#about to read 5, iclass 7, count 2 2006.286.00:41:19.71#ibcon#read 5, iclass 7, count 2 2006.286.00:41:19.71#ibcon#about to read 6, iclass 7, count 2 2006.286.00:41:19.71#ibcon#read 6, iclass 7, count 2 2006.286.00:41:19.71#ibcon#end of sib2, iclass 7, count 2 2006.286.00:41:19.71#ibcon#*after write, iclass 7, count 2 2006.286.00:41:19.71#ibcon#*before return 0, iclass 7, count 2 2006.286.00:41:19.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:41:19.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.00:41:19.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.00:41:19.71#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:19.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:41:19.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:41:19.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:41:19.83#ibcon#enter wrdev, iclass 7, count 0 2006.286.00:41:19.83#ibcon#first serial, iclass 7, count 0 2006.286.00:41:19.83#ibcon#enter sib2, iclass 7, count 0 2006.286.00:41:19.83#ibcon#flushed, iclass 7, count 0 2006.286.00:41:19.83#ibcon#about to write, iclass 7, count 0 2006.286.00:41:19.83#ibcon#wrote, iclass 7, count 0 2006.286.00:41:19.83#ibcon#about to read 3, iclass 7, count 0 2006.286.00:41:19.85#ibcon#read 3, iclass 7, count 0 2006.286.00:41:19.85#ibcon#about to read 4, iclass 7, count 0 2006.286.00:41:19.85#ibcon#read 4, iclass 7, count 0 2006.286.00:41:19.85#ibcon#about to read 5, iclass 7, count 0 2006.286.00:41:19.85#ibcon#read 5, iclass 7, count 0 2006.286.00:41:19.85#ibcon#about to read 6, iclass 7, count 0 2006.286.00:41:19.85#ibcon#read 6, iclass 7, count 0 2006.286.00:41:19.85#ibcon#end of sib2, iclass 7, count 0 2006.286.00:41:19.85#ibcon#*mode == 0, iclass 7, count 0 2006.286.00:41:19.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.00:41:19.85#ibcon#[27=USB\r\n] 2006.286.00:41:19.85#ibcon#*before write, iclass 7, count 0 2006.286.00:41:19.85#ibcon#enter sib2, iclass 7, count 0 2006.286.00:41:19.85#ibcon#flushed, iclass 7, count 0 2006.286.00:41:19.85#ibcon#about to write, iclass 7, count 0 2006.286.00:41:19.85#ibcon#wrote, iclass 7, count 0 2006.286.00:41:19.85#ibcon#about to read 3, iclass 7, count 0 2006.286.00:41:19.88#ibcon#read 3, iclass 7, count 0 2006.286.00:41:19.88#ibcon#about to read 4, iclass 7, count 0 2006.286.00:41:19.88#ibcon#read 4, iclass 7, count 0 2006.286.00:41:19.88#ibcon#about to read 5, iclass 7, count 0 2006.286.00:41:19.88#ibcon#read 5, iclass 7, count 0 2006.286.00:41:19.88#ibcon#about to read 6, iclass 7, count 0 2006.286.00:41:19.88#ibcon#read 6, iclass 7, count 0 2006.286.00:41:19.88#ibcon#end of sib2, iclass 7, count 0 2006.286.00:41:19.88#ibcon#*after write, iclass 7, count 0 2006.286.00:41:19.88#ibcon#*before return 0, iclass 7, count 0 2006.286.00:41:19.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:41:19.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.00:41:19.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.00:41:19.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.00:41:19.88$vck44/vblo=2,634.99 2006.286.00:41:19.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.00:41:19.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.00:41:19.88#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:19.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:41:19.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:41:19.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:41:19.88#ibcon#enter wrdev, iclass 11, count 0 2006.286.00:41:19.88#ibcon#first serial, iclass 11, count 0 2006.286.00:41:19.88#ibcon#enter sib2, iclass 11, count 0 2006.286.00:41:19.88#ibcon#flushed, iclass 11, count 0 2006.286.00:41:19.88#ibcon#about to write, iclass 11, count 0 2006.286.00:41:19.88#ibcon#wrote, iclass 11, count 0 2006.286.00:41:19.88#ibcon#about to read 3, iclass 11, count 0 2006.286.00:41:19.90#ibcon#read 3, iclass 11, count 0 2006.286.00:41:19.90#ibcon#about to read 4, iclass 11, count 0 2006.286.00:41:19.90#ibcon#read 4, iclass 11, count 0 2006.286.00:41:19.90#ibcon#about to read 5, iclass 11, count 0 2006.286.00:41:19.90#ibcon#read 5, iclass 11, count 0 2006.286.00:41:19.90#ibcon#about to read 6, iclass 11, count 0 2006.286.00:41:19.90#ibcon#read 6, iclass 11, count 0 2006.286.00:41:19.90#ibcon#end of sib2, iclass 11, count 0 2006.286.00:41:19.90#ibcon#*mode == 0, iclass 11, count 0 2006.286.00:41:19.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.00:41:19.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.00:41:19.90#ibcon#*before write, iclass 11, count 0 2006.286.00:41:19.90#ibcon#enter sib2, iclass 11, count 0 2006.286.00:41:19.90#ibcon#flushed, iclass 11, count 0 2006.286.00:41:19.90#ibcon#about to write, iclass 11, count 0 2006.286.00:41:19.90#ibcon#wrote, iclass 11, count 0 2006.286.00:41:19.90#ibcon#about to read 3, iclass 11, count 0 2006.286.00:41:19.94#ibcon#read 3, iclass 11, count 0 2006.286.00:41:19.94#ibcon#about to read 4, iclass 11, count 0 2006.286.00:41:19.94#ibcon#read 4, iclass 11, count 0 2006.286.00:41:19.94#ibcon#about to read 5, iclass 11, count 0 2006.286.00:41:19.94#ibcon#read 5, iclass 11, count 0 2006.286.00:41:19.94#ibcon#about to read 6, iclass 11, count 0 2006.286.00:41:19.94#ibcon#read 6, iclass 11, count 0 2006.286.00:41:19.94#ibcon#end of sib2, iclass 11, count 0 2006.286.00:41:19.94#ibcon#*after write, iclass 11, count 0 2006.286.00:41:19.94#ibcon#*before return 0, iclass 11, count 0 2006.286.00:41:19.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:41:19.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.00:41:19.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.00:41:19.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.00:41:19.94$vck44/vb=2,5 2006.286.00:41:19.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.00:41:19.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.00:41:19.94#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:19.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:41:20.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:41:20.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:41:20.00#ibcon#enter wrdev, iclass 13, count 2 2006.286.00:41:20.00#ibcon#first serial, iclass 13, count 2 2006.286.00:41:20.00#ibcon#enter sib2, iclass 13, count 2 2006.286.00:41:20.00#ibcon#flushed, iclass 13, count 2 2006.286.00:41:20.00#ibcon#about to write, iclass 13, count 2 2006.286.00:41:20.00#ibcon#wrote, iclass 13, count 2 2006.286.00:41:20.00#ibcon#about to read 3, iclass 13, count 2 2006.286.00:41:20.02#ibcon#read 3, iclass 13, count 2 2006.286.00:41:20.02#ibcon#about to read 4, iclass 13, count 2 2006.286.00:41:20.02#ibcon#read 4, iclass 13, count 2 2006.286.00:41:20.02#ibcon#about to read 5, iclass 13, count 2 2006.286.00:41:20.02#ibcon#read 5, iclass 13, count 2 2006.286.00:41:20.02#ibcon#about to read 6, iclass 13, count 2 2006.286.00:41:20.02#ibcon#read 6, iclass 13, count 2 2006.286.00:41:20.02#ibcon#end of sib2, iclass 13, count 2 2006.286.00:41:20.02#ibcon#*mode == 0, iclass 13, count 2 2006.286.00:41:20.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.00:41:20.02#ibcon#[27=AT02-05\r\n] 2006.286.00:41:20.02#ibcon#*before write, iclass 13, count 2 2006.286.00:41:20.02#ibcon#enter sib2, iclass 13, count 2 2006.286.00:41:20.02#ibcon#flushed, iclass 13, count 2 2006.286.00:41:20.02#ibcon#about to write, iclass 13, count 2 2006.286.00:41:20.02#ibcon#wrote, iclass 13, count 2 2006.286.00:41:20.02#ibcon#about to read 3, iclass 13, count 2 2006.286.00:41:20.05#ibcon#read 3, iclass 13, count 2 2006.286.00:41:20.05#ibcon#about to read 4, iclass 13, count 2 2006.286.00:41:20.05#ibcon#read 4, iclass 13, count 2 2006.286.00:41:20.05#ibcon#about to read 5, iclass 13, count 2 2006.286.00:41:20.05#ibcon#read 5, iclass 13, count 2 2006.286.00:41:20.05#ibcon#about to read 6, iclass 13, count 2 2006.286.00:41:20.05#ibcon#read 6, iclass 13, count 2 2006.286.00:41:20.05#ibcon#end of sib2, iclass 13, count 2 2006.286.00:41:20.05#ibcon#*after write, iclass 13, count 2 2006.286.00:41:20.05#ibcon#*before return 0, iclass 13, count 2 2006.286.00:41:20.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:41:20.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.00:41:20.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.00:41:20.05#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:20.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:41:20.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:41:20.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:41:20.17#ibcon#enter wrdev, iclass 13, count 0 2006.286.00:41:20.17#ibcon#first serial, iclass 13, count 0 2006.286.00:41:20.17#ibcon#enter sib2, iclass 13, count 0 2006.286.00:41:20.17#ibcon#flushed, iclass 13, count 0 2006.286.00:41:20.17#ibcon#about to write, iclass 13, count 0 2006.286.00:41:20.17#ibcon#wrote, iclass 13, count 0 2006.286.00:41:20.17#ibcon#about to read 3, iclass 13, count 0 2006.286.00:41:20.19#ibcon#read 3, iclass 13, count 0 2006.286.00:41:20.19#ibcon#about to read 4, iclass 13, count 0 2006.286.00:41:20.19#ibcon#read 4, iclass 13, count 0 2006.286.00:41:20.19#ibcon#about to read 5, iclass 13, count 0 2006.286.00:41:20.19#ibcon#read 5, iclass 13, count 0 2006.286.00:41:20.19#ibcon#about to read 6, iclass 13, count 0 2006.286.00:41:20.19#ibcon#read 6, iclass 13, count 0 2006.286.00:41:20.19#ibcon#end of sib2, iclass 13, count 0 2006.286.00:41:20.19#ibcon#*mode == 0, iclass 13, count 0 2006.286.00:41:20.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.00:41:20.19#ibcon#[27=USB\r\n] 2006.286.00:41:20.19#ibcon#*before write, iclass 13, count 0 2006.286.00:41:20.19#ibcon#enter sib2, iclass 13, count 0 2006.286.00:41:20.19#ibcon#flushed, iclass 13, count 0 2006.286.00:41:20.19#ibcon#about to write, iclass 13, count 0 2006.286.00:41:20.19#ibcon#wrote, iclass 13, count 0 2006.286.00:41:20.19#ibcon#about to read 3, iclass 13, count 0 2006.286.00:41:20.22#ibcon#read 3, iclass 13, count 0 2006.286.00:41:20.22#ibcon#about to read 4, iclass 13, count 0 2006.286.00:41:20.22#ibcon#read 4, iclass 13, count 0 2006.286.00:41:20.22#ibcon#about to read 5, iclass 13, count 0 2006.286.00:41:20.22#ibcon#read 5, iclass 13, count 0 2006.286.00:41:20.22#ibcon#about to read 6, iclass 13, count 0 2006.286.00:41:20.22#ibcon#read 6, iclass 13, count 0 2006.286.00:41:20.22#ibcon#end of sib2, iclass 13, count 0 2006.286.00:41:20.22#ibcon#*after write, iclass 13, count 0 2006.286.00:41:20.22#ibcon#*before return 0, iclass 13, count 0 2006.286.00:41:20.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:41:20.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.00:41:20.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.00:41:20.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.00:41:20.22$vck44/vblo=3,649.99 2006.286.00:41:20.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.00:41:20.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.00:41:20.22#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:20.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:41:20.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:41:20.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:41:20.22#ibcon#enter wrdev, iclass 15, count 0 2006.286.00:41:20.22#ibcon#first serial, iclass 15, count 0 2006.286.00:41:20.22#ibcon#enter sib2, iclass 15, count 0 2006.286.00:41:20.22#ibcon#flushed, iclass 15, count 0 2006.286.00:41:20.22#ibcon#about to write, iclass 15, count 0 2006.286.00:41:20.22#ibcon#wrote, iclass 15, count 0 2006.286.00:41:20.22#ibcon#about to read 3, iclass 15, count 0 2006.286.00:41:20.24#ibcon#read 3, iclass 15, count 0 2006.286.00:41:20.24#ibcon#about to read 4, iclass 15, count 0 2006.286.00:41:20.24#ibcon#read 4, iclass 15, count 0 2006.286.00:41:20.24#ibcon#about to read 5, iclass 15, count 0 2006.286.00:41:20.24#ibcon#read 5, iclass 15, count 0 2006.286.00:41:20.24#ibcon#about to read 6, iclass 15, count 0 2006.286.00:41:20.24#ibcon#read 6, iclass 15, count 0 2006.286.00:41:20.24#ibcon#end of sib2, iclass 15, count 0 2006.286.00:41:20.24#ibcon#*mode == 0, iclass 15, count 0 2006.286.00:41:20.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.00:41:20.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.00:41:20.24#ibcon#*before write, iclass 15, count 0 2006.286.00:41:20.24#ibcon#enter sib2, iclass 15, count 0 2006.286.00:41:20.24#ibcon#flushed, iclass 15, count 0 2006.286.00:41:20.24#ibcon#about to write, iclass 15, count 0 2006.286.00:41:20.24#ibcon#wrote, iclass 15, count 0 2006.286.00:41:20.24#ibcon#about to read 3, iclass 15, count 0 2006.286.00:41:20.28#ibcon#read 3, iclass 15, count 0 2006.286.00:41:20.28#ibcon#about to read 4, iclass 15, count 0 2006.286.00:41:20.28#ibcon#read 4, iclass 15, count 0 2006.286.00:41:20.28#ibcon#about to read 5, iclass 15, count 0 2006.286.00:41:20.28#ibcon#read 5, iclass 15, count 0 2006.286.00:41:20.28#ibcon#about to read 6, iclass 15, count 0 2006.286.00:41:20.28#ibcon#read 6, iclass 15, count 0 2006.286.00:41:20.28#ibcon#end of sib2, iclass 15, count 0 2006.286.00:41:20.28#ibcon#*after write, iclass 15, count 0 2006.286.00:41:20.28#ibcon#*before return 0, iclass 15, count 0 2006.286.00:41:20.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:41:20.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.00:41:20.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.00:41:20.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.00:41:20.28$vck44/vb=3,4 2006.286.00:41:20.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.00:41:20.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.00:41:20.28#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:20.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:41:20.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:41:20.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:41:20.34#ibcon#enter wrdev, iclass 17, count 2 2006.286.00:41:20.34#ibcon#first serial, iclass 17, count 2 2006.286.00:41:20.34#ibcon#enter sib2, iclass 17, count 2 2006.286.00:41:20.34#ibcon#flushed, iclass 17, count 2 2006.286.00:41:20.34#ibcon#about to write, iclass 17, count 2 2006.286.00:41:20.34#ibcon#wrote, iclass 17, count 2 2006.286.00:41:20.34#ibcon#about to read 3, iclass 17, count 2 2006.286.00:41:20.36#ibcon#read 3, iclass 17, count 2 2006.286.00:41:20.36#ibcon#about to read 4, iclass 17, count 2 2006.286.00:41:20.36#ibcon#read 4, iclass 17, count 2 2006.286.00:41:20.36#ibcon#about to read 5, iclass 17, count 2 2006.286.00:41:20.36#ibcon#read 5, iclass 17, count 2 2006.286.00:41:20.36#ibcon#about to read 6, iclass 17, count 2 2006.286.00:41:20.36#ibcon#read 6, iclass 17, count 2 2006.286.00:41:20.36#ibcon#end of sib2, iclass 17, count 2 2006.286.00:41:20.36#ibcon#*mode == 0, iclass 17, count 2 2006.286.00:41:20.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.00:41:20.36#ibcon#[27=AT03-04\r\n] 2006.286.00:41:20.36#ibcon#*before write, iclass 17, count 2 2006.286.00:41:20.36#ibcon#enter sib2, iclass 17, count 2 2006.286.00:41:20.36#ibcon#flushed, iclass 17, count 2 2006.286.00:41:20.36#ibcon#about to write, iclass 17, count 2 2006.286.00:41:20.36#ibcon#wrote, iclass 17, count 2 2006.286.00:41:20.36#ibcon#about to read 3, iclass 17, count 2 2006.286.00:41:20.39#ibcon#read 3, iclass 17, count 2 2006.286.00:41:20.39#ibcon#about to read 4, iclass 17, count 2 2006.286.00:41:20.39#ibcon#read 4, iclass 17, count 2 2006.286.00:41:20.39#ibcon#about to read 5, iclass 17, count 2 2006.286.00:41:20.39#ibcon#read 5, iclass 17, count 2 2006.286.00:41:20.39#ibcon#about to read 6, iclass 17, count 2 2006.286.00:41:20.39#ibcon#read 6, iclass 17, count 2 2006.286.00:41:20.39#ibcon#end of sib2, iclass 17, count 2 2006.286.00:41:20.39#ibcon#*after write, iclass 17, count 2 2006.286.00:41:20.39#ibcon#*before return 0, iclass 17, count 2 2006.286.00:41:20.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:41:20.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.00:41:20.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.00:41:20.39#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:20.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:41:20.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:41:20.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:41:20.51#ibcon#enter wrdev, iclass 17, count 0 2006.286.00:41:20.51#ibcon#first serial, iclass 17, count 0 2006.286.00:41:20.51#ibcon#enter sib2, iclass 17, count 0 2006.286.00:41:20.51#ibcon#flushed, iclass 17, count 0 2006.286.00:41:20.51#ibcon#about to write, iclass 17, count 0 2006.286.00:41:20.51#ibcon#wrote, iclass 17, count 0 2006.286.00:41:20.51#ibcon#about to read 3, iclass 17, count 0 2006.286.00:41:20.53#ibcon#read 3, iclass 17, count 0 2006.286.00:41:20.53#ibcon#about to read 4, iclass 17, count 0 2006.286.00:41:20.53#ibcon#read 4, iclass 17, count 0 2006.286.00:41:20.53#ibcon#about to read 5, iclass 17, count 0 2006.286.00:41:20.53#ibcon#read 5, iclass 17, count 0 2006.286.00:41:20.53#ibcon#about to read 6, iclass 17, count 0 2006.286.00:41:20.53#ibcon#read 6, iclass 17, count 0 2006.286.00:41:20.53#ibcon#end of sib2, iclass 17, count 0 2006.286.00:41:20.53#ibcon#*mode == 0, iclass 17, count 0 2006.286.00:41:20.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.00:41:20.53#ibcon#[27=USB\r\n] 2006.286.00:41:20.53#ibcon#*before write, iclass 17, count 0 2006.286.00:41:20.53#ibcon#enter sib2, iclass 17, count 0 2006.286.00:41:20.53#ibcon#flushed, iclass 17, count 0 2006.286.00:41:20.53#ibcon#about to write, iclass 17, count 0 2006.286.00:41:20.53#ibcon#wrote, iclass 17, count 0 2006.286.00:41:20.53#ibcon#about to read 3, iclass 17, count 0 2006.286.00:41:20.56#ibcon#read 3, iclass 17, count 0 2006.286.00:41:20.56#ibcon#about to read 4, iclass 17, count 0 2006.286.00:41:20.56#ibcon#read 4, iclass 17, count 0 2006.286.00:41:20.56#ibcon#about to read 5, iclass 17, count 0 2006.286.00:41:20.56#ibcon#read 5, iclass 17, count 0 2006.286.00:41:20.56#ibcon#about to read 6, iclass 17, count 0 2006.286.00:41:20.56#ibcon#read 6, iclass 17, count 0 2006.286.00:41:20.56#ibcon#end of sib2, iclass 17, count 0 2006.286.00:41:20.56#ibcon#*after write, iclass 17, count 0 2006.286.00:41:20.56#ibcon#*before return 0, iclass 17, count 0 2006.286.00:41:20.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:41:20.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.00:41:20.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.00:41:20.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.00:41:20.56$vck44/vblo=4,679.99 2006.286.00:41:20.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.00:41:20.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.00:41:20.56#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:20.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:41:20.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:41:20.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:41:20.56#ibcon#enter wrdev, iclass 19, count 0 2006.286.00:41:20.56#ibcon#first serial, iclass 19, count 0 2006.286.00:41:20.56#ibcon#enter sib2, iclass 19, count 0 2006.286.00:41:20.56#ibcon#flushed, iclass 19, count 0 2006.286.00:41:20.56#ibcon#about to write, iclass 19, count 0 2006.286.00:41:20.56#ibcon#wrote, iclass 19, count 0 2006.286.00:41:20.56#ibcon#about to read 3, iclass 19, count 0 2006.286.00:41:20.58#ibcon#read 3, iclass 19, count 0 2006.286.00:41:20.58#ibcon#about to read 4, iclass 19, count 0 2006.286.00:41:20.58#ibcon#read 4, iclass 19, count 0 2006.286.00:41:20.58#ibcon#about to read 5, iclass 19, count 0 2006.286.00:41:20.58#ibcon#read 5, iclass 19, count 0 2006.286.00:41:20.58#ibcon#about to read 6, iclass 19, count 0 2006.286.00:41:20.58#ibcon#read 6, iclass 19, count 0 2006.286.00:41:20.58#ibcon#end of sib2, iclass 19, count 0 2006.286.00:41:20.58#ibcon#*mode == 0, iclass 19, count 0 2006.286.00:41:20.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.00:41:20.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.00:41:20.58#ibcon#*before write, iclass 19, count 0 2006.286.00:41:20.58#ibcon#enter sib2, iclass 19, count 0 2006.286.00:41:20.58#ibcon#flushed, iclass 19, count 0 2006.286.00:41:20.58#ibcon#about to write, iclass 19, count 0 2006.286.00:41:20.58#ibcon#wrote, iclass 19, count 0 2006.286.00:41:20.58#ibcon#about to read 3, iclass 19, count 0 2006.286.00:41:20.62#ibcon#read 3, iclass 19, count 0 2006.286.00:41:20.62#ibcon#about to read 4, iclass 19, count 0 2006.286.00:41:20.62#ibcon#read 4, iclass 19, count 0 2006.286.00:41:20.62#ibcon#about to read 5, iclass 19, count 0 2006.286.00:41:20.62#ibcon#read 5, iclass 19, count 0 2006.286.00:41:20.62#ibcon#about to read 6, iclass 19, count 0 2006.286.00:41:20.62#ibcon#read 6, iclass 19, count 0 2006.286.00:41:20.62#ibcon#end of sib2, iclass 19, count 0 2006.286.00:41:20.62#ibcon#*after write, iclass 19, count 0 2006.286.00:41:20.62#ibcon#*before return 0, iclass 19, count 0 2006.286.00:41:20.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:41:20.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.00:41:20.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.00:41:20.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.00:41:20.62$vck44/vb=4,5 2006.286.00:41:20.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.00:41:20.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.00:41:20.62#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:20.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:41:20.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:41:20.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:41:20.68#ibcon#enter wrdev, iclass 21, count 2 2006.286.00:41:20.68#ibcon#first serial, iclass 21, count 2 2006.286.00:41:20.68#ibcon#enter sib2, iclass 21, count 2 2006.286.00:41:20.68#ibcon#flushed, iclass 21, count 2 2006.286.00:41:20.68#ibcon#about to write, iclass 21, count 2 2006.286.00:41:20.68#ibcon#wrote, iclass 21, count 2 2006.286.00:41:20.68#ibcon#about to read 3, iclass 21, count 2 2006.286.00:41:20.70#ibcon#read 3, iclass 21, count 2 2006.286.00:41:20.70#ibcon#about to read 4, iclass 21, count 2 2006.286.00:41:20.70#ibcon#read 4, iclass 21, count 2 2006.286.00:41:20.70#ibcon#about to read 5, iclass 21, count 2 2006.286.00:41:20.70#ibcon#read 5, iclass 21, count 2 2006.286.00:41:20.70#ibcon#about to read 6, iclass 21, count 2 2006.286.00:41:20.70#ibcon#read 6, iclass 21, count 2 2006.286.00:41:20.70#ibcon#end of sib2, iclass 21, count 2 2006.286.00:41:20.70#ibcon#*mode == 0, iclass 21, count 2 2006.286.00:41:20.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.00:41:20.70#ibcon#[27=AT04-05\r\n] 2006.286.00:41:20.70#ibcon#*before write, iclass 21, count 2 2006.286.00:41:20.70#ibcon#enter sib2, iclass 21, count 2 2006.286.00:41:20.70#ibcon#flushed, iclass 21, count 2 2006.286.00:41:20.70#ibcon#about to write, iclass 21, count 2 2006.286.00:41:20.70#ibcon#wrote, iclass 21, count 2 2006.286.00:41:20.70#ibcon#about to read 3, iclass 21, count 2 2006.286.00:41:20.73#ibcon#read 3, iclass 21, count 2 2006.286.00:41:20.73#ibcon#about to read 4, iclass 21, count 2 2006.286.00:41:20.73#ibcon#read 4, iclass 21, count 2 2006.286.00:41:20.73#ibcon#about to read 5, iclass 21, count 2 2006.286.00:41:20.73#ibcon#read 5, iclass 21, count 2 2006.286.00:41:20.73#ibcon#about to read 6, iclass 21, count 2 2006.286.00:41:20.73#ibcon#read 6, iclass 21, count 2 2006.286.00:41:20.73#ibcon#end of sib2, iclass 21, count 2 2006.286.00:41:20.73#ibcon#*after write, iclass 21, count 2 2006.286.00:41:20.73#ibcon#*before return 0, iclass 21, count 2 2006.286.00:41:20.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:41:20.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.00:41:20.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.00:41:20.73#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:20.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:41:20.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:41:20.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:41:20.85#ibcon#enter wrdev, iclass 21, count 0 2006.286.00:41:20.85#ibcon#first serial, iclass 21, count 0 2006.286.00:41:20.85#ibcon#enter sib2, iclass 21, count 0 2006.286.00:41:20.85#ibcon#flushed, iclass 21, count 0 2006.286.00:41:20.85#ibcon#about to write, iclass 21, count 0 2006.286.00:41:20.85#ibcon#wrote, iclass 21, count 0 2006.286.00:41:20.85#ibcon#about to read 3, iclass 21, count 0 2006.286.00:41:20.87#ibcon#read 3, iclass 21, count 0 2006.286.00:41:20.87#ibcon#about to read 4, iclass 21, count 0 2006.286.00:41:20.87#ibcon#read 4, iclass 21, count 0 2006.286.00:41:20.87#ibcon#about to read 5, iclass 21, count 0 2006.286.00:41:20.87#ibcon#read 5, iclass 21, count 0 2006.286.00:41:20.87#ibcon#about to read 6, iclass 21, count 0 2006.286.00:41:20.87#ibcon#read 6, iclass 21, count 0 2006.286.00:41:20.87#ibcon#end of sib2, iclass 21, count 0 2006.286.00:41:20.87#ibcon#*mode == 0, iclass 21, count 0 2006.286.00:41:20.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.00:41:20.87#ibcon#[27=USB\r\n] 2006.286.00:41:20.87#ibcon#*before write, iclass 21, count 0 2006.286.00:41:20.87#ibcon#enter sib2, iclass 21, count 0 2006.286.00:41:20.87#ibcon#flushed, iclass 21, count 0 2006.286.00:41:20.87#ibcon#about to write, iclass 21, count 0 2006.286.00:41:20.87#ibcon#wrote, iclass 21, count 0 2006.286.00:41:20.87#ibcon#about to read 3, iclass 21, count 0 2006.286.00:41:20.90#ibcon#read 3, iclass 21, count 0 2006.286.00:41:20.90#ibcon#about to read 4, iclass 21, count 0 2006.286.00:41:20.90#ibcon#read 4, iclass 21, count 0 2006.286.00:41:20.90#ibcon#about to read 5, iclass 21, count 0 2006.286.00:41:20.90#ibcon#read 5, iclass 21, count 0 2006.286.00:41:20.90#ibcon#about to read 6, iclass 21, count 0 2006.286.00:41:20.90#ibcon#read 6, iclass 21, count 0 2006.286.00:41:20.90#ibcon#end of sib2, iclass 21, count 0 2006.286.00:41:20.90#ibcon#*after write, iclass 21, count 0 2006.286.00:41:20.90#ibcon#*before return 0, iclass 21, count 0 2006.286.00:41:20.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:41:20.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.00:41:20.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.00:41:20.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.00:41:20.90$vck44/vblo=5,709.99 2006.286.00:41:20.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.00:41:20.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.00:41:20.90#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:20.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:41:20.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:41:20.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:41:20.90#ibcon#enter wrdev, iclass 23, count 0 2006.286.00:41:20.90#ibcon#first serial, iclass 23, count 0 2006.286.00:41:20.90#ibcon#enter sib2, iclass 23, count 0 2006.286.00:41:20.90#ibcon#flushed, iclass 23, count 0 2006.286.00:41:20.90#ibcon#about to write, iclass 23, count 0 2006.286.00:41:20.90#ibcon#wrote, iclass 23, count 0 2006.286.00:41:20.90#ibcon#about to read 3, iclass 23, count 0 2006.286.00:41:20.92#ibcon#read 3, iclass 23, count 0 2006.286.00:41:20.92#ibcon#about to read 4, iclass 23, count 0 2006.286.00:41:20.92#ibcon#read 4, iclass 23, count 0 2006.286.00:41:20.92#ibcon#about to read 5, iclass 23, count 0 2006.286.00:41:20.92#ibcon#read 5, iclass 23, count 0 2006.286.00:41:20.92#ibcon#about to read 6, iclass 23, count 0 2006.286.00:41:20.92#ibcon#read 6, iclass 23, count 0 2006.286.00:41:20.92#ibcon#end of sib2, iclass 23, count 0 2006.286.00:41:20.92#ibcon#*mode == 0, iclass 23, count 0 2006.286.00:41:20.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.00:41:20.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.00:41:20.92#ibcon#*before write, iclass 23, count 0 2006.286.00:41:20.92#ibcon#enter sib2, iclass 23, count 0 2006.286.00:41:20.92#ibcon#flushed, iclass 23, count 0 2006.286.00:41:20.92#ibcon#about to write, iclass 23, count 0 2006.286.00:41:20.92#ibcon#wrote, iclass 23, count 0 2006.286.00:41:20.92#ibcon#about to read 3, iclass 23, count 0 2006.286.00:41:20.96#ibcon#read 3, iclass 23, count 0 2006.286.00:41:20.96#ibcon#about to read 4, iclass 23, count 0 2006.286.00:41:20.96#ibcon#read 4, iclass 23, count 0 2006.286.00:41:20.96#ibcon#about to read 5, iclass 23, count 0 2006.286.00:41:20.96#ibcon#read 5, iclass 23, count 0 2006.286.00:41:20.96#ibcon#about to read 6, iclass 23, count 0 2006.286.00:41:20.96#ibcon#read 6, iclass 23, count 0 2006.286.00:41:20.96#ibcon#end of sib2, iclass 23, count 0 2006.286.00:41:20.96#ibcon#*after write, iclass 23, count 0 2006.286.00:41:20.96#ibcon#*before return 0, iclass 23, count 0 2006.286.00:41:20.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:41:20.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.00:41:20.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.00:41:20.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.00:41:20.96$vck44/vb=5,4 2006.286.00:41:20.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.00:41:20.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.00:41:20.96#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:20.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:41:21.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:41:21.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:41:21.02#ibcon#enter wrdev, iclass 25, count 2 2006.286.00:41:21.02#ibcon#first serial, iclass 25, count 2 2006.286.00:41:21.02#ibcon#enter sib2, iclass 25, count 2 2006.286.00:41:21.02#ibcon#flushed, iclass 25, count 2 2006.286.00:41:21.02#ibcon#about to write, iclass 25, count 2 2006.286.00:41:21.02#ibcon#wrote, iclass 25, count 2 2006.286.00:41:21.02#ibcon#about to read 3, iclass 25, count 2 2006.286.00:41:21.04#ibcon#read 3, iclass 25, count 2 2006.286.00:41:21.04#ibcon#about to read 4, iclass 25, count 2 2006.286.00:41:21.04#ibcon#read 4, iclass 25, count 2 2006.286.00:41:21.04#ibcon#about to read 5, iclass 25, count 2 2006.286.00:41:21.04#ibcon#read 5, iclass 25, count 2 2006.286.00:41:21.04#ibcon#about to read 6, iclass 25, count 2 2006.286.00:41:21.04#ibcon#read 6, iclass 25, count 2 2006.286.00:41:21.04#ibcon#end of sib2, iclass 25, count 2 2006.286.00:41:21.04#ibcon#*mode == 0, iclass 25, count 2 2006.286.00:41:21.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.00:41:21.04#ibcon#[27=AT05-04\r\n] 2006.286.00:41:21.04#ibcon#*before write, iclass 25, count 2 2006.286.00:41:21.04#ibcon#enter sib2, iclass 25, count 2 2006.286.00:41:21.04#ibcon#flushed, iclass 25, count 2 2006.286.00:41:21.04#ibcon#about to write, iclass 25, count 2 2006.286.00:41:21.04#ibcon#wrote, iclass 25, count 2 2006.286.00:41:21.04#ibcon#about to read 3, iclass 25, count 2 2006.286.00:41:21.07#ibcon#read 3, iclass 25, count 2 2006.286.00:41:21.07#ibcon#about to read 4, iclass 25, count 2 2006.286.00:41:21.07#ibcon#read 4, iclass 25, count 2 2006.286.00:41:21.07#ibcon#about to read 5, iclass 25, count 2 2006.286.00:41:21.07#ibcon#read 5, iclass 25, count 2 2006.286.00:41:21.07#ibcon#about to read 6, iclass 25, count 2 2006.286.00:41:21.07#ibcon#read 6, iclass 25, count 2 2006.286.00:41:21.07#ibcon#end of sib2, iclass 25, count 2 2006.286.00:41:21.07#ibcon#*after write, iclass 25, count 2 2006.286.00:41:21.07#ibcon#*before return 0, iclass 25, count 2 2006.286.00:41:21.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:41:21.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.00:41:21.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.00:41:21.07#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:21.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:41:21.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:41:21.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:41:21.19#ibcon#enter wrdev, iclass 25, count 0 2006.286.00:41:21.19#ibcon#first serial, iclass 25, count 0 2006.286.00:41:21.19#ibcon#enter sib2, iclass 25, count 0 2006.286.00:41:21.19#ibcon#flushed, iclass 25, count 0 2006.286.00:41:21.19#ibcon#about to write, iclass 25, count 0 2006.286.00:41:21.19#ibcon#wrote, iclass 25, count 0 2006.286.00:41:21.19#ibcon#about to read 3, iclass 25, count 0 2006.286.00:41:21.21#ibcon#read 3, iclass 25, count 0 2006.286.00:41:21.21#ibcon#about to read 4, iclass 25, count 0 2006.286.00:41:21.21#ibcon#read 4, iclass 25, count 0 2006.286.00:41:21.21#ibcon#about to read 5, iclass 25, count 0 2006.286.00:41:21.21#ibcon#read 5, iclass 25, count 0 2006.286.00:41:21.21#ibcon#about to read 6, iclass 25, count 0 2006.286.00:41:21.21#ibcon#read 6, iclass 25, count 0 2006.286.00:41:21.21#ibcon#end of sib2, iclass 25, count 0 2006.286.00:41:21.21#ibcon#*mode == 0, iclass 25, count 0 2006.286.00:41:21.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.00:41:21.21#ibcon#[27=USB\r\n] 2006.286.00:41:21.21#ibcon#*before write, iclass 25, count 0 2006.286.00:41:21.21#ibcon#enter sib2, iclass 25, count 0 2006.286.00:41:21.21#ibcon#flushed, iclass 25, count 0 2006.286.00:41:21.21#ibcon#about to write, iclass 25, count 0 2006.286.00:41:21.21#ibcon#wrote, iclass 25, count 0 2006.286.00:41:21.21#ibcon#about to read 3, iclass 25, count 0 2006.286.00:41:21.24#ibcon#read 3, iclass 25, count 0 2006.286.00:41:21.24#ibcon#about to read 4, iclass 25, count 0 2006.286.00:41:21.24#ibcon#read 4, iclass 25, count 0 2006.286.00:41:21.24#ibcon#about to read 5, iclass 25, count 0 2006.286.00:41:21.24#ibcon#read 5, iclass 25, count 0 2006.286.00:41:21.24#ibcon#about to read 6, iclass 25, count 0 2006.286.00:41:21.24#ibcon#read 6, iclass 25, count 0 2006.286.00:41:21.24#ibcon#end of sib2, iclass 25, count 0 2006.286.00:41:21.24#ibcon#*after write, iclass 25, count 0 2006.286.00:41:21.24#ibcon#*before return 0, iclass 25, count 0 2006.286.00:41:21.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:41:21.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.00:41:21.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.00:41:21.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.00:41:21.24$vck44/vblo=6,719.99 2006.286.00:41:21.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.00:41:21.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.00:41:21.24#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:21.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:41:21.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:41:21.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:41:21.24#ibcon#enter wrdev, iclass 27, count 0 2006.286.00:41:21.24#ibcon#first serial, iclass 27, count 0 2006.286.00:41:21.24#ibcon#enter sib2, iclass 27, count 0 2006.286.00:41:21.24#ibcon#flushed, iclass 27, count 0 2006.286.00:41:21.24#ibcon#about to write, iclass 27, count 0 2006.286.00:41:21.24#ibcon#wrote, iclass 27, count 0 2006.286.00:41:21.24#ibcon#about to read 3, iclass 27, count 0 2006.286.00:41:21.26#ibcon#read 3, iclass 27, count 0 2006.286.00:41:21.26#ibcon#about to read 4, iclass 27, count 0 2006.286.00:41:21.26#ibcon#read 4, iclass 27, count 0 2006.286.00:41:21.26#ibcon#about to read 5, iclass 27, count 0 2006.286.00:41:21.26#ibcon#read 5, iclass 27, count 0 2006.286.00:41:21.26#ibcon#about to read 6, iclass 27, count 0 2006.286.00:41:21.26#ibcon#read 6, iclass 27, count 0 2006.286.00:41:21.26#ibcon#end of sib2, iclass 27, count 0 2006.286.00:41:21.26#ibcon#*mode == 0, iclass 27, count 0 2006.286.00:41:21.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.00:41:21.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.00:41:21.26#ibcon#*before write, iclass 27, count 0 2006.286.00:41:21.26#ibcon#enter sib2, iclass 27, count 0 2006.286.00:41:21.26#ibcon#flushed, iclass 27, count 0 2006.286.00:41:21.26#ibcon#about to write, iclass 27, count 0 2006.286.00:41:21.26#ibcon#wrote, iclass 27, count 0 2006.286.00:41:21.26#ibcon#about to read 3, iclass 27, count 0 2006.286.00:41:21.30#ibcon#read 3, iclass 27, count 0 2006.286.00:41:21.30#ibcon#about to read 4, iclass 27, count 0 2006.286.00:41:21.30#ibcon#read 4, iclass 27, count 0 2006.286.00:41:21.30#ibcon#about to read 5, iclass 27, count 0 2006.286.00:41:21.30#ibcon#read 5, iclass 27, count 0 2006.286.00:41:21.30#ibcon#about to read 6, iclass 27, count 0 2006.286.00:41:21.30#ibcon#read 6, iclass 27, count 0 2006.286.00:41:21.30#ibcon#end of sib2, iclass 27, count 0 2006.286.00:41:21.30#ibcon#*after write, iclass 27, count 0 2006.286.00:41:21.30#ibcon#*before return 0, iclass 27, count 0 2006.286.00:41:21.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:41:21.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.00:41:21.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.00:41:21.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.00:41:21.30$vck44/vb=6,3 2006.286.00:41:21.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.00:41:21.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.00:41:21.30#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:21.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:41:21.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:41:21.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:41:21.36#ibcon#enter wrdev, iclass 29, count 2 2006.286.00:41:21.36#ibcon#first serial, iclass 29, count 2 2006.286.00:41:21.36#ibcon#enter sib2, iclass 29, count 2 2006.286.00:41:21.36#ibcon#flushed, iclass 29, count 2 2006.286.00:41:21.36#ibcon#about to write, iclass 29, count 2 2006.286.00:41:21.36#ibcon#wrote, iclass 29, count 2 2006.286.00:41:21.36#ibcon#about to read 3, iclass 29, count 2 2006.286.00:41:21.38#ibcon#read 3, iclass 29, count 2 2006.286.00:41:21.38#ibcon#about to read 4, iclass 29, count 2 2006.286.00:41:21.38#ibcon#read 4, iclass 29, count 2 2006.286.00:41:21.38#ibcon#about to read 5, iclass 29, count 2 2006.286.00:41:21.38#ibcon#read 5, iclass 29, count 2 2006.286.00:41:21.38#ibcon#about to read 6, iclass 29, count 2 2006.286.00:41:21.38#ibcon#read 6, iclass 29, count 2 2006.286.00:41:21.38#ibcon#end of sib2, iclass 29, count 2 2006.286.00:41:21.38#ibcon#*mode == 0, iclass 29, count 2 2006.286.00:41:21.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.00:41:21.38#ibcon#[27=AT06-03\r\n] 2006.286.00:41:21.38#ibcon#*before write, iclass 29, count 2 2006.286.00:41:21.38#ibcon#enter sib2, iclass 29, count 2 2006.286.00:41:21.38#ibcon#flushed, iclass 29, count 2 2006.286.00:41:21.38#ibcon#about to write, iclass 29, count 2 2006.286.00:41:21.38#ibcon#wrote, iclass 29, count 2 2006.286.00:41:21.38#ibcon#about to read 3, iclass 29, count 2 2006.286.00:41:21.41#ibcon#read 3, iclass 29, count 2 2006.286.00:41:21.41#ibcon#about to read 4, iclass 29, count 2 2006.286.00:41:21.41#ibcon#read 4, iclass 29, count 2 2006.286.00:41:21.41#ibcon#about to read 5, iclass 29, count 2 2006.286.00:41:21.41#ibcon#read 5, iclass 29, count 2 2006.286.00:41:21.41#ibcon#about to read 6, iclass 29, count 2 2006.286.00:41:21.41#ibcon#read 6, iclass 29, count 2 2006.286.00:41:21.41#ibcon#end of sib2, iclass 29, count 2 2006.286.00:41:21.41#ibcon#*after write, iclass 29, count 2 2006.286.00:41:21.41#ibcon#*before return 0, iclass 29, count 2 2006.286.00:41:21.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:41:21.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.00:41:21.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.00:41:21.41#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:21.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:41:21.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:41:21.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:41:21.53#ibcon#enter wrdev, iclass 29, count 0 2006.286.00:41:21.53#ibcon#first serial, iclass 29, count 0 2006.286.00:41:21.53#ibcon#enter sib2, iclass 29, count 0 2006.286.00:41:21.53#ibcon#flushed, iclass 29, count 0 2006.286.00:41:21.53#ibcon#about to write, iclass 29, count 0 2006.286.00:41:21.53#ibcon#wrote, iclass 29, count 0 2006.286.00:41:21.53#ibcon#about to read 3, iclass 29, count 0 2006.286.00:41:21.55#ibcon#read 3, iclass 29, count 0 2006.286.00:41:21.55#ibcon#about to read 4, iclass 29, count 0 2006.286.00:41:21.55#ibcon#read 4, iclass 29, count 0 2006.286.00:41:21.55#ibcon#about to read 5, iclass 29, count 0 2006.286.00:41:21.55#ibcon#read 5, iclass 29, count 0 2006.286.00:41:21.55#ibcon#about to read 6, iclass 29, count 0 2006.286.00:41:21.55#ibcon#read 6, iclass 29, count 0 2006.286.00:41:21.55#ibcon#end of sib2, iclass 29, count 0 2006.286.00:41:21.55#ibcon#*mode == 0, iclass 29, count 0 2006.286.00:41:21.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.00:41:21.55#ibcon#[27=USB\r\n] 2006.286.00:41:21.55#ibcon#*before write, iclass 29, count 0 2006.286.00:41:21.55#ibcon#enter sib2, iclass 29, count 0 2006.286.00:41:21.55#ibcon#flushed, iclass 29, count 0 2006.286.00:41:21.55#ibcon#about to write, iclass 29, count 0 2006.286.00:41:21.55#ibcon#wrote, iclass 29, count 0 2006.286.00:41:21.55#ibcon#about to read 3, iclass 29, count 0 2006.286.00:41:21.58#ibcon#read 3, iclass 29, count 0 2006.286.00:41:21.58#ibcon#about to read 4, iclass 29, count 0 2006.286.00:41:21.58#ibcon#read 4, iclass 29, count 0 2006.286.00:41:21.58#ibcon#about to read 5, iclass 29, count 0 2006.286.00:41:21.58#ibcon#read 5, iclass 29, count 0 2006.286.00:41:21.58#ibcon#about to read 6, iclass 29, count 0 2006.286.00:41:21.58#ibcon#read 6, iclass 29, count 0 2006.286.00:41:21.58#ibcon#end of sib2, iclass 29, count 0 2006.286.00:41:21.58#ibcon#*after write, iclass 29, count 0 2006.286.00:41:21.58#ibcon#*before return 0, iclass 29, count 0 2006.286.00:41:21.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:41:21.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.00:41:21.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.00:41:21.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.00:41:21.58$vck44/vblo=7,734.99 2006.286.00:41:21.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.00:41:21.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.00:41:21.58#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:21.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:41:21.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:41:21.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:41:21.58#ibcon#enter wrdev, iclass 31, count 0 2006.286.00:41:21.58#ibcon#first serial, iclass 31, count 0 2006.286.00:41:21.58#ibcon#enter sib2, iclass 31, count 0 2006.286.00:41:21.58#ibcon#flushed, iclass 31, count 0 2006.286.00:41:21.58#ibcon#about to write, iclass 31, count 0 2006.286.00:41:21.58#ibcon#wrote, iclass 31, count 0 2006.286.00:41:21.58#ibcon#about to read 3, iclass 31, count 0 2006.286.00:41:21.60#ibcon#read 3, iclass 31, count 0 2006.286.00:41:21.60#ibcon#about to read 4, iclass 31, count 0 2006.286.00:41:21.60#ibcon#read 4, iclass 31, count 0 2006.286.00:41:21.60#ibcon#about to read 5, iclass 31, count 0 2006.286.00:41:21.60#ibcon#read 5, iclass 31, count 0 2006.286.00:41:21.60#ibcon#about to read 6, iclass 31, count 0 2006.286.00:41:21.60#ibcon#read 6, iclass 31, count 0 2006.286.00:41:21.60#ibcon#end of sib2, iclass 31, count 0 2006.286.00:41:21.60#ibcon#*mode == 0, iclass 31, count 0 2006.286.00:41:21.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.00:41:21.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.00:41:21.60#ibcon#*before write, iclass 31, count 0 2006.286.00:41:21.60#ibcon#enter sib2, iclass 31, count 0 2006.286.00:41:21.60#ibcon#flushed, iclass 31, count 0 2006.286.00:41:21.60#ibcon#about to write, iclass 31, count 0 2006.286.00:41:21.60#ibcon#wrote, iclass 31, count 0 2006.286.00:41:21.60#ibcon#about to read 3, iclass 31, count 0 2006.286.00:41:21.64#ibcon#read 3, iclass 31, count 0 2006.286.00:41:21.64#ibcon#about to read 4, iclass 31, count 0 2006.286.00:41:21.64#ibcon#read 4, iclass 31, count 0 2006.286.00:41:21.64#ibcon#about to read 5, iclass 31, count 0 2006.286.00:41:21.64#ibcon#read 5, iclass 31, count 0 2006.286.00:41:21.64#ibcon#about to read 6, iclass 31, count 0 2006.286.00:41:21.64#ibcon#read 6, iclass 31, count 0 2006.286.00:41:21.64#ibcon#end of sib2, iclass 31, count 0 2006.286.00:41:21.64#ibcon#*after write, iclass 31, count 0 2006.286.00:41:21.64#ibcon#*before return 0, iclass 31, count 0 2006.286.00:41:21.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:41:21.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:41:21.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.00:41:21.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.00:41:21.64$vck44/vb=7,4 2006.286.00:41:21.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.00:41:21.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.00:41:21.64#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:21.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:41:21.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:41:21.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:41:21.70#ibcon#enter wrdev, iclass 33, count 2 2006.286.00:41:21.70#ibcon#first serial, iclass 33, count 2 2006.286.00:41:21.70#ibcon#enter sib2, iclass 33, count 2 2006.286.00:41:21.70#ibcon#flushed, iclass 33, count 2 2006.286.00:41:21.70#ibcon#about to write, iclass 33, count 2 2006.286.00:41:21.70#ibcon#wrote, iclass 33, count 2 2006.286.00:41:21.70#ibcon#about to read 3, iclass 33, count 2 2006.286.00:41:21.72#ibcon#read 3, iclass 33, count 2 2006.286.00:41:21.72#ibcon#about to read 4, iclass 33, count 2 2006.286.00:41:21.72#ibcon#read 4, iclass 33, count 2 2006.286.00:41:21.72#ibcon#about to read 5, iclass 33, count 2 2006.286.00:41:21.72#ibcon#read 5, iclass 33, count 2 2006.286.00:41:21.72#ibcon#about to read 6, iclass 33, count 2 2006.286.00:41:21.72#ibcon#read 6, iclass 33, count 2 2006.286.00:41:21.72#ibcon#end of sib2, iclass 33, count 2 2006.286.00:41:21.72#ibcon#*mode == 0, iclass 33, count 2 2006.286.00:41:21.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.00:41:21.72#ibcon#[27=AT07-04\r\n] 2006.286.00:41:21.72#ibcon#*before write, iclass 33, count 2 2006.286.00:41:21.72#ibcon#enter sib2, iclass 33, count 2 2006.286.00:41:21.72#ibcon#flushed, iclass 33, count 2 2006.286.00:41:21.72#ibcon#about to write, iclass 33, count 2 2006.286.00:41:21.72#ibcon#wrote, iclass 33, count 2 2006.286.00:41:21.72#ibcon#about to read 3, iclass 33, count 2 2006.286.00:41:21.75#ibcon#read 3, iclass 33, count 2 2006.286.00:41:21.75#ibcon#about to read 4, iclass 33, count 2 2006.286.00:41:21.75#ibcon#read 4, iclass 33, count 2 2006.286.00:41:21.75#ibcon#about to read 5, iclass 33, count 2 2006.286.00:41:21.75#ibcon#read 5, iclass 33, count 2 2006.286.00:41:21.75#ibcon#about to read 6, iclass 33, count 2 2006.286.00:41:21.75#ibcon#read 6, iclass 33, count 2 2006.286.00:41:21.75#ibcon#end of sib2, iclass 33, count 2 2006.286.00:41:21.75#ibcon#*after write, iclass 33, count 2 2006.286.00:41:21.75#ibcon#*before return 0, iclass 33, count 2 2006.286.00:41:21.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:41:21.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.00:41:21.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.00:41:21.75#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:21.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:41:21.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:41:21.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:41:21.87#ibcon#enter wrdev, iclass 33, count 0 2006.286.00:41:21.87#ibcon#first serial, iclass 33, count 0 2006.286.00:41:21.87#ibcon#enter sib2, iclass 33, count 0 2006.286.00:41:21.87#ibcon#flushed, iclass 33, count 0 2006.286.00:41:21.87#ibcon#about to write, iclass 33, count 0 2006.286.00:41:21.87#ibcon#wrote, iclass 33, count 0 2006.286.00:41:21.87#ibcon#about to read 3, iclass 33, count 0 2006.286.00:41:21.89#ibcon#read 3, iclass 33, count 0 2006.286.00:41:21.89#ibcon#about to read 4, iclass 33, count 0 2006.286.00:41:21.89#ibcon#read 4, iclass 33, count 0 2006.286.00:41:21.89#ibcon#about to read 5, iclass 33, count 0 2006.286.00:41:21.89#ibcon#read 5, iclass 33, count 0 2006.286.00:41:21.89#ibcon#about to read 6, iclass 33, count 0 2006.286.00:41:21.89#ibcon#read 6, iclass 33, count 0 2006.286.00:41:21.89#ibcon#end of sib2, iclass 33, count 0 2006.286.00:41:21.89#ibcon#*mode == 0, iclass 33, count 0 2006.286.00:41:21.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.00:41:21.89#ibcon#[27=USB\r\n] 2006.286.00:41:21.89#ibcon#*before write, iclass 33, count 0 2006.286.00:41:21.89#ibcon#enter sib2, iclass 33, count 0 2006.286.00:41:21.89#ibcon#flushed, iclass 33, count 0 2006.286.00:41:21.89#ibcon#about to write, iclass 33, count 0 2006.286.00:41:21.89#ibcon#wrote, iclass 33, count 0 2006.286.00:41:21.89#ibcon#about to read 3, iclass 33, count 0 2006.286.00:41:21.92#ibcon#read 3, iclass 33, count 0 2006.286.00:41:21.92#ibcon#about to read 4, iclass 33, count 0 2006.286.00:41:21.92#ibcon#read 4, iclass 33, count 0 2006.286.00:41:21.92#ibcon#about to read 5, iclass 33, count 0 2006.286.00:41:21.92#ibcon#read 5, iclass 33, count 0 2006.286.00:41:21.92#ibcon#about to read 6, iclass 33, count 0 2006.286.00:41:21.92#ibcon#read 6, iclass 33, count 0 2006.286.00:41:21.92#ibcon#end of sib2, iclass 33, count 0 2006.286.00:41:21.92#ibcon#*after write, iclass 33, count 0 2006.286.00:41:21.92#ibcon#*before return 0, iclass 33, count 0 2006.286.00:41:21.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:41:21.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.00:41:21.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.00:41:21.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.00:41:21.92$vck44/vblo=8,744.99 2006.286.00:41:21.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.00:41:21.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.00:41:21.92#ibcon#ireg 17 cls_cnt 0 2006.286.00:41:21.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:41:21.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:41:21.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:41:21.92#ibcon#enter wrdev, iclass 35, count 0 2006.286.00:41:21.92#ibcon#first serial, iclass 35, count 0 2006.286.00:41:21.92#ibcon#enter sib2, iclass 35, count 0 2006.286.00:41:21.92#ibcon#flushed, iclass 35, count 0 2006.286.00:41:21.92#ibcon#about to write, iclass 35, count 0 2006.286.00:41:21.92#ibcon#wrote, iclass 35, count 0 2006.286.00:41:21.92#ibcon#about to read 3, iclass 35, count 0 2006.286.00:41:21.94#ibcon#read 3, iclass 35, count 0 2006.286.00:41:21.94#ibcon#about to read 4, iclass 35, count 0 2006.286.00:41:21.94#ibcon#read 4, iclass 35, count 0 2006.286.00:41:21.94#ibcon#about to read 5, iclass 35, count 0 2006.286.00:41:21.94#ibcon#read 5, iclass 35, count 0 2006.286.00:41:21.94#ibcon#about to read 6, iclass 35, count 0 2006.286.00:41:21.94#ibcon#read 6, iclass 35, count 0 2006.286.00:41:21.94#ibcon#end of sib2, iclass 35, count 0 2006.286.00:41:21.94#ibcon#*mode == 0, iclass 35, count 0 2006.286.00:41:21.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.00:41:21.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.00:41:21.94#ibcon#*before write, iclass 35, count 0 2006.286.00:41:21.94#ibcon#enter sib2, iclass 35, count 0 2006.286.00:41:21.94#ibcon#flushed, iclass 35, count 0 2006.286.00:41:21.94#ibcon#about to write, iclass 35, count 0 2006.286.00:41:21.94#ibcon#wrote, iclass 35, count 0 2006.286.00:41:21.94#ibcon#about to read 3, iclass 35, count 0 2006.286.00:41:21.98#ibcon#read 3, iclass 35, count 0 2006.286.00:41:21.98#ibcon#about to read 4, iclass 35, count 0 2006.286.00:41:21.98#ibcon#read 4, iclass 35, count 0 2006.286.00:41:21.98#ibcon#about to read 5, iclass 35, count 0 2006.286.00:41:21.98#ibcon#read 5, iclass 35, count 0 2006.286.00:41:21.98#ibcon#about to read 6, iclass 35, count 0 2006.286.00:41:21.98#ibcon#read 6, iclass 35, count 0 2006.286.00:41:21.98#ibcon#end of sib2, iclass 35, count 0 2006.286.00:41:21.98#ibcon#*after write, iclass 35, count 0 2006.286.00:41:21.98#ibcon#*before return 0, iclass 35, count 0 2006.286.00:41:21.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:41:21.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.00:41:21.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.00:41:21.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.00:41:21.98$vck44/vb=8,4 2006.286.00:41:21.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.00:41:21.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.00:41:21.98#ibcon#ireg 11 cls_cnt 2 2006.286.00:41:21.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:41:22.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:41:22.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:41:22.04#ibcon#enter wrdev, iclass 37, count 2 2006.286.00:41:22.04#ibcon#first serial, iclass 37, count 2 2006.286.00:41:22.04#ibcon#enter sib2, iclass 37, count 2 2006.286.00:41:22.04#ibcon#flushed, iclass 37, count 2 2006.286.00:41:22.04#ibcon#about to write, iclass 37, count 2 2006.286.00:41:22.04#ibcon#wrote, iclass 37, count 2 2006.286.00:41:22.04#ibcon#about to read 3, iclass 37, count 2 2006.286.00:41:22.06#ibcon#read 3, iclass 37, count 2 2006.286.00:41:22.06#ibcon#about to read 4, iclass 37, count 2 2006.286.00:41:22.06#ibcon#read 4, iclass 37, count 2 2006.286.00:41:22.06#ibcon#about to read 5, iclass 37, count 2 2006.286.00:41:22.06#ibcon#read 5, iclass 37, count 2 2006.286.00:41:22.06#ibcon#about to read 6, iclass 37, count 2 2006.286.00:41:22.06#ibcon#read 6, iclass 37, count 2 2006.286.00:41:22.06#ibcon#end of sib2, iclass 37, count 2 2006.286.00:41:22.06#ibcon#*mode == 0, iclass 37, count 2 2006.286.00:41:22.06#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.00:41:22.06#ibcon#[27=AT08-04\r\n] 2006.286.00:41:22.06#ibcon#*before write, iclass 37, count 2 2006.286.00:41:22.06#ibcon#enter sib2, iclass 37, count 2 2006.286.00:41:22.06#ibcon#flushed, iclass 37, count 2 2006.286.00:41:22.06#ibcon#about to write, iclass 37, count 2 2006.286.00:41:22.06#ibcon#wrote, iclass 37, count 2 2006.286.00:41:22.06#ibcon#about to read 3, iclass 37, count 2 2006.286.00:41:22.09#ibcon#read 3, iclass 37, count 2 2006.286.00:41:22.09#ibcon#about to read 4, iclass 37, count 2 2006.286.00:41:22.09#ibcon#read 4, iclass 37, count 2 2006.286.00:41:22.09#ibcon#about to read 5, iclass 37, count 2 2006.286.00:41:22.09#ibcon#read 5, iclass 37, count 2 2006.286.00:41:22.09#ibcon#about to read 6, iclass 37, count 2 2006.286.00:41:22.09#ibcon#read 6, iclass 37, count 2 2006.286.00:41:22.09#ibcon#end of sib2, iclass 37, count 2 2006.286.00:41:22.09#ibcon#*after write, iclass 37, count 2 2006.286.00:41:22.09#ibcon#*before return 0, iclass 37, count 2 2006.286.00:41:22.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:41:22.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.00:41:22.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.00:41:22.09#ibcon#ireg 7 cls_cnt 0 2006.286.00:41:22.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:41:22.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:41:22.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:41:22.21#ibcon#enter wrdev, iclass 37, count 0 2006.286.00:41:22.21#ibcon#first serial, iclass 37, count 0 2006.286.00:41:22.21#ibcon#enter sib2, iclass 37, count 0 2006.286.00:41:22.21#ibcon#flushed, iclass 37, count 0 2006.286.00:41:22.21#ibcon#about to write, iclass 37, count 0 2006.286.00:41:22.21#ibcon#wrote, iclass 37, count 0 2006.286.00:41:22.21#ibcon#about to read 3, iclass 37, count 0 2006.286.00:41:22.23#ibcon#read 3, iclass 37, count 0 2006.286.00:41:22.23#ibcon#about to read 4, iclass 37, count 0 2006.286.00:41:22.23#ibcon#read 4, iclass 37, count 0 2006.286.00:41:22.23#ibcon#about to read 5, iclass 37, count 0 2006.286.00:41:22.23#ibcon#read 5, iclass 37, count 0 2006.286.00:41:22.23#ibcon#about to read 6, iclass 37, count 0 2006.286.00:41:22.23#ibcon#read 6, iclass 37, count 0 2006.286.00:41:22.23#ibcon#end of sib2, iclass 37, count 0 2006.286.00:41:22.23#ibcon#*mode == 0, iclass 37, count 0 2006.286.00:41:22.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.00:41:22.23#ibcon#[27=USB\r\n] 2006.286.00:41:22.23#ibcon#*before write, iclass 37, count 0 2006.286.00:41:22.23#ibcon#enter sib2, iclass 37, count 0 2006.286.00:41:22.23#ibcon#flushed, iclass 37, count 0 2006.286.00:41:22.23#ibcon#about to write, iclass 37, count 0 2006.286.00:41:22.23#ibcon#wrote, iclass 37, count 0 2006.286.00:41:22.23#ibcon#about to read 3, iclass 37, count 0 2006.286.00:41:22.26#ibcon#read 3, iclass 37, count 0 2006.286.00:41:22.26#ibcon#about to read 4, iclass 37, count 0 2006.286.00:41:22.26#ibcon#read 4, iclass 37, count 0 2006.286.00:41:22.26#ibcon#about to read 5, iclass 37, count 0 2006.286.00:41:22.26#ibcon#read 5, iclass 37, count 0 2006.286.00:41:22.26#ibcon#about to read 6, iclass 37, count 0 2006.286.00:41:22.26#ibcon#read 6, iclass 37, count 0 2006.286.00:41:22.26#ibcon#end of sib2, iclass 37, count 0 2006.286.00:41:22.26#ibcon#*after write, iclass 37, count 0 2006.286.00:41:22.26#ibcon#*before return 0, iclass 37, count 0 2006.286.00:41:22.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:41:22.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.00:41:22.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.00:41:22.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.00:41:22.26$vck44/vabw=wide 2006.286.00:41:22.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.00:41:22.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.00:41:22.26#ibcon#ireg 8 cls_cnt 0 2006.286.00:41:22.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:41:22.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:41:22.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:41:22.26#ibcon#enter wrdev, iclass 39, count 0 2006.286.00:41:22.26#ibcon#first serial, iclass 39, count 0 2006.286.00:41:22.26#ibcon#enter sib2, iclass 39, count 0 2006.286.00:41:22.26#ibcon#flushed, iclass 39, count 0 2006.286.00:41:22.26#ibcon#about to write, iclass 39, count 0 2006.286.00:41:22.26#ibcon#wrote, iclass 39, count 0 2006.286.00:41:22.26#ibcon#about to read 3, iclass 39, count 0 2006.286.00:41:22.28#ibcon#read 3, iclass 39, count 0 2006.286.00:41:22.28#ibcon#about to read 4, iclass 39, count 0 2006.286.00:41:22.28#ibcon#read 4, iclass 39, count 0 2006.286.00:41:22.28#ibcon#about to read 5, iclass 39, count 0 2006.286.00:41:22.28#ibcon#read 5, iclass 39, count 0 2006.286.00:41:22.28#ibcon#about to read 6, iclass 39, count 0 2006.286.00:41:22.28#ibcon#read 6, iclass 39, count 0 2006.286.00:41:22.28#ibcon#end of sib2, iclass 39, count 0 2006.286.00:41:22.28#ibcon#*mode == 0, iclass 39, count 0 2006.286.00:41:22.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.00:41:22.28#ibcon#[25=BW32\r\n] 2006.286.00:41:22.28#ibcon#*before write, iclass 39, count 0 2006.286.00:41:22.28#ibcon#enter sib2, iclass 39, count 0 2006.286.00:41:22.28#ibcon#flushed, iclass 39, count 0 2006.286.00:41:22.28#ibcon#about to write, iclass 39, count 0 2006.286.00:41:22.28#ibcon#wrote, iclass 39, count 0 2006.286.00:41:22.28#ibcon#about to read 3, iclass 39, count 0 2006.286.00:41:22.31#ibcon#read 3, iclass 39, count 0 2006.286.00:41:22.31#ibcon#about to read 4, iclass 39, count 0 2006.286.00:41:22.31#ibcon#read 4, iclass 39, count 0 2006.286.00:41:22.31#ibcon#about to read 5, iclass 39, count 0 2006.286.00:41:22.31#ibcon#read 5, iclass 39, count 0 2006.286.00:41:22.31#ibcon#about to read 6, iclass 39, count 0 2006.286.00:41:22.31#ibcon#read 6, iclass 39, count 0 2006.286.00:41:22.31#ibcon#end of sib2, iclass 39, count 0 2006.286.00:41:22.31#ibcon#*after write, iclass 39, count 0 2006.286.00:41:22.31#ibcon#*before return 0, iclass 39, count 0 2006.286.00:41:22.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:41:22.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.00:41:22.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.00:41:22.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.00:41:22.31$vck44/vbbw=wide 2006.286.00:41:22.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.00:41:22.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.00:41:22.31#ibcon#ireg 8 cls_cnt 0 2006.286.00:41:22.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:41:22.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:41:22.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:41:22.38#ibcon#enter wrdev, iclass 3, count 0 2006.286.00:41:22.38#ibcon#first serial, iclass 3, count 0 2006.286.00:41:22.38#ibcon#enter sib2, iclass 3, count 0 2006.286.00:41:22.38#ibcon#flushed, iclass 3, count 0 2006.286.00:41:22.38#ibcon#about to write, iclass 3, count 0 2006.286.00:41:22.38#ibcon#wrote, iclass 3, count 0 2006.286.00:41:22.38#ibcon#about to read 3, iclass 3, count 0 2006.286.00:41:22.40#ibcon#read 3, iclass 3, count 0 2006.286.00:41:22.40#ibcon#about to read 4, iclass 3, count 0 2006.286.00:41:22.40#ibcon#read 4, iclass 3, count 0 2006.286.00:41:22.40#ibcon#about to read 5, iclass 3, count 0 2006.286.00:41:22.40#ibcon#read 5, iclass 3, count 0 2006.286.00:41:22.40#ibcon#about to read 6, iclass 3, count 0 2006.286.00:41:22.40#ibcon#read 6, iclass 3, count 0 2006.286.00:41:22.40#ibcon#end of sib2, iclass 3, count 0 2006.286.00:41:22.40#ibcon#*mode == 0, iclass 3, count 0 2006.286.00:41:22.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.00:41:22.40#ibcon#[27=BW32\r\n] 2006.286.00:41:22.40#ibcon#*before write, iclass 3, count 0 2006.286.00:41:22.40#ibcon#enter sib2, iclass 3, count 0 2006.286.00:41:22.40#ibcon#flushed, iclass 3, count 0 2006.286.00:41:22.40#ibcon#about to write, iclass 3, count 0 2006.286.00:41:22.40#ibcon#wrote, iclass 3, count 0 2006.286.00:41:22.40#ibcon#about to read 3, iclass 3, count 0 2006.286.00:41:22.43#ibcon#read 3, iclass 3, count 0 2006.286.00:41:22.43#ibcon#about to read 4, iclass 3, count 0 2006.286.00:41:22.43#ibcon#read 4, iclass 3, count 0 2006.286.00:41:22.43#ibcon#about to read 5, iclass 3, count 0 2006.286.00:41:22.43#ibcon#read 5, iclass 3, count 0 2006.286.00:41:22.43#ibcon#about to read 6, iclass 3, count 0 2006.286.00:41:22.43#ibcon#read 6, iclass 3, count 0 2006.286.00:41:22.43#ibcon#end of sib2, iclass 3, count 0 2006.286.00:41:22.43#ibcon#*after write, iclass 3, count 0 2006.286.00:41:22.43#ibcon#*before return 0, iclass 3, count 0 2006.286.00:41:22.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:41:22.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:41:22.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.00:41:22.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.00:41:22.43$setupk4/ifdk4 2006.286.00:41:22.43$ifdk4/lo= 2006.286.00:41:22.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.00:41:22.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.00:41:22.43$ifdk4/patch= 2006.286.00:41:22.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.00:41:22.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.00:41:22.43$setupk4/!*+20s 2006.286.00:41:24.61#abcon#<5=/03 3.6 8.0 19.98 871016.4\r\n> 2006.286.00:41:24.63#abcon#{5=INTERFACE CLEAR} 2006.286.00:41:24.69#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:41:34.13#trakl#Source acquired 2006.286.00:41:34.78#abcon#<5=/03 3.6 8.0 19.98 861016.4\r\n> 2006.286.00:41:34.80#abcon#{5=INTERFACE CLEAR} 2006.286.00:41:34.86#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:41:36.13#flagr#flagr/antenna,acquired 2006.286.00:41:36.94$setupk4/"tpicd 2006.286.00:41:36.94$setupk4/echo=off 2006.286.00:41:36.94$setupk4/xlog=off 2006.286.00:41:36.94:!2006.286.00:46:28 2006.286.00:46:28.00:preob 2006.286.00:46:28.14/onsource/TRACKING 2006.286.00:46:28.14:!2006.286.00:46:38 2006.286.00:46:38.00:"tape 2006.286.00:46:38.00:"st=record 2006.286.00:46:38.00:data_valid=on 2006.286.00:46:38.00:midob 2006.286.00:46:39.14/onsource/TRACKING 2006.286.00:46:39.14/wx/20.15,1016.4,85 2006.286.00:46:39.22/cable/+6.5052E-03 2006.286.00:46:40.31/va/01,07,usb,yes,40,44 2006.286.00:46:40.31/va/02,06,usb,yes,41,41 2006.286.00:46:40.31/va/03,07,usb,yes,40,42 2006.286.00:46:40.31/va/04,06,usb,yes,42,44 2006.286.00:46:40.31/va/05,03,usb,yes,41,42 2006.286.00:46:40.31/va/06,04,usb,yes,38,37 2006.286.00:46:40.31/va/07,04,usb,yes,38,39 2006.286.00:46:40.31/va/08,03,usb,yes,39,47 2006.286.00:46:40.54/valo/01,524.99,yes,locked 2006.286.00:46:40.54/valo/02,534.99,yes,locked 2006.286.00:46:40.54/valo/03,564.99,yes,locked 2006.286.00:46:40.54/valo/04,624.99,yes,locked 2006.286.00:46:40.54/valo/05,734.99,yes,locked 2006.286.00:46:40.54/valo/06,814.99,yes,locked 2006.286.00:46:40.54/valo/07,864.99,yes,locked 2006.286.00:46:40.54/valo/08,884.99,yes,locked 2006.286.00:46:41.63/vb/01,04,usb,yes,36,39 2006.286.00:46:41.63/vb/02,05,usb,yes,32,42 2006.286.00:46:41.63/vb/03,04,usb,yes,33,37 2006.286.00:46:41.63/vb/04,05,usb,yes,34,33 2006.286.00:46:41.63/vb/05,04,usb,yes,31,34 2006.286.00:46:41.63/vb/06,03,usb,yes,46,42 2006.286.00:46:41.63/vb/07,04,usb,yes,36,36 2006.286.00:46:41.63/vb/08,04,usb,yes,33,37 2006.286.00:46:41.86/vblo/01,629.99,yes,locked 2006.286.00:46:41.86/vblo/02,634.99,yes,locked 2006.286.00:46:41.86/vblo/03,649.99,yes,locked 2006.286.00:46:41.86/vblo/04,679.99,yes,locked 2006.286.00:46:41.86/vblo/05,709.99,yes,locked 2006.286.00:46:41.86/vblo/06,719.99,yes,locked 2006.286.00:46:41.86/vblo/07,734.99,yes,locked 2006.286.00:46:41.86/vblo/08,744.99,yes,locked 2006.286.00:46:42.01/vabw/8 2006.286.00:46:42.16/vbbw/8 2006.286.00:46:42.25/xfe/off,on,12.2 2006.286.00:46:42.68/ifatt/23,28,28,28 2006.286.00:46:43.08/fmout-gps/S +2.86E-07 2006.286.00:46:43.10:!2006.286.00:49:48 2006.286.00:49:48.00:data_valid=off 2006.286.00:49:48.00:"et 2006.286.00:49:48.00:!+3s 2006.286.00:49:51.01:"tape 2006.286.00:49:51.01:postob 2006.286.00:49:51.11/cable/+6.5050E-03 2006.286.00:49:51.11/wx/20.31,1016.3,85 2006.286.00:49:52.08/fmout-gps/S +2.75E-07 2006.286.00:49:52.08:scan_name=286-0052,jd0610,50 2006.286.00:49:52.08:source=1611+343,161341.06,341247.9,2000.0,cw 2006.286.00:49:53.13#flagr#flagr/antenna,new-source 2006.286.00:49:53.13:checkk5 2006.286.00:49:53.52/chk_autoobs//k5ts1/ autoobs is running! 2006.286.00:49:53.88/chk_autoobs//k5ts2/ autoobs is running! 2006.286.00:49:54.32/chk_autoobs//k5ts3/ autoobs is running! 2006.286.00:49:54.80/chk_autoobs//k5ts4/ autoobs is running! 2006.286.00:49:55.28/chk_obsdata//k5ts1/T2860046??a.dat file size is correct (nominal:760MB, actual:760MB). 2006.286.00:49:55.69/chk_obsdata//k5ts2/T2860046??b.dat file size is correct (nominal:760MB, actual:760MB). 2006.286.00:49:56.10/chk_obsdata//k5ts3/T2860046??c.dat file size is correct (nominal:760MB, actual:760MB). 2006.286.00:49:56.44/chk_obsdata//k5ts4/T2860046??d.dat file size is correct (nominal:760MB, actual:760MB). 2006.286.00:49:57.33/k5log//k5ts1_log_newline 2006.286.00:49:58.17/k5log//k5ts2_log_newline 2006.286.00:49:59.14/k5log//k5ts3_log_newline 2006.286.00:49:59.96/k5log//k5ts4_log_newline 2006.286.00:49:59.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.00:49:59.98:setupk4=1 2006.286.00:49:59.98$setupk4/echo=on 2006.286.00:49:59.98$setupk4/pcalon 2006.286.00:49:59.98$pcalon/"no phase cal control is implemented here 2006.286.00:49:59.98$setupk4/"tpicd=stop 2006.286.00:49:59.98$setupk4/"rec=synch_on 2006.286.00:49:59.98$setupk4/"rec_mode=128 2006.286.00:49:59.98$setupk4/!* 2006.286.00:49:59.98$setupk4/recpk4 2006.286.00:49:59.98$recpk4/recpatch= 2006.286.00:49:59.99$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.00:49:59.99$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.00:49:59.99$setupk4/vck44 2006.286.00:49:59.99$vck44/valo=1,524.99 2006.286.00:49:59.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.00:49:59.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.00:49:59.99#ibcon#ireg 17 cls_cnt 0 2006.286.00:49:59.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:49:59.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:49:59.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:49:59.99#ibcon#enter wrdev, iclass 34, count 0 2006.286.00:49:59.99#ibcon#first serial, iclass 34, count 0 2006.286.00:49:59.99#ibcon#enter sib2, iclass 34, count 0 2006.286.00:49:59.99#ibcon#flushed, iclass 34, count 0 2006.286.00:49:59.99#ibcon#about to write, iclass 34, count 0 2006.286.00:49:59.99#ibcon#wrote, iclass 34, count 0 2006.286.00:49:59.99#ibcon#about to read 3, iclass 34, count 0 2006.286.00:50:00.01#ibcon#read 3, iclass 34, count 0 2006.286.00:50:00.01#ibcon#about to read 4, iclass 34, count 0 2006.286.00:50:00.01#ibcon#read 4, iclass 34, count 0 2006.286.00:50:00.01#ibcon#about to read 5, iclass 34, count 0 2006.286.00:50:00.01#ibcon#read 5, iclass 34, count 0 2006.286.00:50:00.01#ibcon#about to read 6, iclass 34, count 0 2006.286.00:50:00.01#ibcon#read 6, iclass 34, count 0 2006.286.00:50:00.01#ibcon#end of sib2, iclass 34, count 0 2006.286.00:50:00.01#ibcon#*mode == 0, iclass 34, count 0 2006.286.00:50:00.01#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.00:50:00.01#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.00:50:00.01#ibcon#*before write, iclass 34, count 0 2006.286.00:50:00.01#ibcon#enter sib2, iclass 34, count 0 2006.286.00:50:00.01#ibcon#flushed, iclass 34, count 0 2006.286.00:50:00.01#ibcon#about to write, iclass 34, count 0 2006.286.00:50:00.01#ibcon#wrote, iclass 34, count 0 2006.286.00:50:00.01#ibcon#about to read 3, iclass 34, count 0 2006.286.00:50:00.06#ibcon#read 3, iclass 34, count 0 2006.286.00:50:00.06#ibcon#about to read 4, iclass 34, count 0 2006.286.00:50:00.06#ibcon#read 4, iclass 34, count 0 2006.286.00:50:00.06#ibcon#about to read 5, iclass 34, count 0 2006.286.00:50:00.06#ibcon#read 5, iclass 34, count 0 2006.286.00:50:00.06#ibcon#about to read 6, iclass 34, count 0 2006.286.00:50:00.06#ibcon#read 6, iclass 34, count 0 2006.286.00:50:00.06#ibcon#end of sib2, iclass 34, count 0 2006.286.00:50:00.06#ibcon#*after write, iclass 34, count 0 2006.286.00:50:00.06#ibcon#*before return 0, iclass 34, count 0 2006.286.00:50:00.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:50:00.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:50:00.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.00:50:00.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.00:50:00.06$vck44/va=1,7 2006.286.00:50:00.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.00:50:00.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.00:50:00.06#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:00.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:50:00.06#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:50:00.06#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:50:00.06#ibcon#enter wrdev, iclass 36, count 2 2006.286.00:50:00.06#ibcon#first serial, iclass 36, count 2 2006.286.00:50:00.06#ibcon#enter sib2, iclass 36, count 2 2006.286.00:50:00.06#ibcon#flushed, iclass 36, count 2 2006.286.00:50:00.06#ibcon#about to write, iclass 36, count 2 2006.286.00:50:00.06#ibcon#wrote, iclass 36, count 2 2006.286.00:50:00.06#ibcon#about to read 3, iclass 36, count 2 2006.286.00:50:00.08#ibcon#read 3, iclass 36, count 2 2006.286.00:50:00.08#ibcon#about to read 4, iclass 36, count 2 2006.286.00:50:00.08#ibcon#read 4, iclass 36, count 2 2006.286.00:50:00.08#ibcon#about to read 5, iclass 36, count 2 2006.286.00:50:00.08#ibcon#read 5, iclass 36, count 2 2006.286.00:50:00.08#ibcon#about to read 6, iclass 36, count 2 2006.286.00:50:00.08#ibcon#read 6, iclass 36, count 2 2006.286.00:50:00.08#ibcon#end of sib2, iclass 36, count 2 2006.286.00:50:00.08#ibcon#*mode == 0, iclass 36, count 2 2006.286.00:50:00.08#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.00:50:00.08#ibcon#[25=AT01-07\r\n] 2006.286.00:50:00.08#ibcon#*before write, iclass 36, count 2 2006.286.00:50:00.08#ibcon#enter sib2, iclass 36, count 2 2006.286.00:50:00.08#ibcon#flushed, iclass 36, count 2 2006.286.00:50:00.08#ibcon#about to write, iclass 36, count 2 2006.286.00:50:00.08#ibcon#wrote, iclass 36, count 2 2006.286.00:50:00.08#ibcon#about to read 3, iclass 36, count 2 2006.286.00:50:00.11#ibcon#read 3, iclass 36, count 2 2006.286.00:50:00.11#ibcon#about to read 4, iclass 36, count 2 2006.286.00:50:00.11#ibcon#read 4, iclass 36, count 2 2006.286.00:50:00.11#ibcon#about to read 5, iclass 36, count 2 2006.286.00:50:00.11#ibcon#read 5, iclass 36, count 2 2006.286.00:50:00.11#ibcon#about to read 6, iclass 36, count 2 2006.286.00:50:00.11#ibcon#read 6, iclass 36, count 2 2006.286.00:50:00.11#ibcon#end of sib2, iclass 36, count 2 2006.286.00:50:00.11#ibcon#*after write, iclass 36, count 2 2006.286.00:50:00.11#ibcon#*before return 0, iclass 36, count 2 2006.286.00:50:00.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:50:00.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:50:00.11#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.00:50:00.11#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:00.11#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:50:00.23#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:50:00.23#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:50:00.23#ibcon#enter wrdev, iclass 36, count 0 2006.286.00:50:00.23#ibcon#first serial, iclass 36, count 0 2006.286.00:50:00.23#ibcon#enter sib2, iclass 36, count 0 2006.286.00:50:00.23#ibcon#flushed, iclass 36, count 0 2006.286.00:50:00.23#ibcon#about to write, iclass 36, count 0 2006.286.00:50:00.23#ibcon#wrote, iclass 36, count 0 2006.286.00:50:00.23#ibcon#about to read 3, iclass 36, count 0 2006.286.00:50:00.25#ibcon#read 3, iclass 36, count 0 2006.286.00:50:00.25#ibcon#about to read 4, iclass 36, count 0 2006.286.00:50:00.25#ibcon#read 4, iclass 36, count 0 2006.286.00:50:00.25#ibcon#about to read 5, iclass 36, count 0 2006.286.00:50:00.25#ibcon#read 5, iclass 36, count 0 2006.286.00:50:00.25#ibcon#about to read 6, iclass 36, count 0 2006.286.00:50:00.25#ibcon#read 6, iclass 36, count 0 2006.286.00:50:00.25#ibcon#end of sib2, iclass 36, count 0 2006.286.00:50:00.25#ibcon#*mode == 0, iclass 36, count 0 2006.286.00:50:00.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.00:50:00.25#ibcon#[25=USB\r\n] 2006.286.00:50:00.25#ibcon#*before write, iclass 36, count 0 2006.286.00:50:00.25#ibcon#enter sib2, iclass 36, count 0 2006.286.00:50:00.25#ibcon#flushed, iclass 36, count 0 2006.286.00:50:00.25#ibcon#about to write, iclass 36, count 0 2006.286.00:50:00.25#ibcon#wrote, iclass 36, count 0 2006.286.00:50:00.25#ibcon#about to read 3, iclass 36, count 0 2006.286.00:50:00.28#ibcon#read 3, iclass 36, count 0 2006.286.00:50:00.28#ibcon#about to read 4, iclass 36, count 0 2006.286.00:50:00.28#ibcon#read 4, iclass 36, count 0 2006.286.00:50:00.28#ibcon#about to read 5, iclass 36, count 0 2006.286.00:50:00.28#ibcon#read 5, iclass 36, count 0 2006.286.00:50:00.28#ibcon#about to read 6, iclass 36, count 0 2006.286.00:50:00.28#ibcon#read 6, iclass 36, count 0 2006.286.00:50:00.28#ibcon#end of sib2, iclass 36, count 0 2006.286.00:50:00.28#ibcon#*after write, iclass 36, count 0 2006.286.00:50:00.28#ibcon#*before return 0, iclass 36, count 0 2006.286.00:50:00.28#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:50:00.28#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:50:00.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.00:50:00.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.00:50:00.28$vck44/valo=2,534.99 2006.286.00:50:00.28#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.00:50:00.28#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.00:50:00.28#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:00.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:50:00.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:50:00.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:50:00.28#ibcon#enter wrdev, iclass 38, count 0 2006.286.00:50:00.28#ibcon#first serial, iclass 38, count 0 2006.286.00:50:00.28#ibcon#enter sib2, iclass 38, count 0 2006.286.00:50:00.28#ibcon#flushed, iclass 38, count 0 2006.286.00:50:00.28#ibcon#about to write, iclass 38, count 0 2006.286.00:50:00.28#ibcon#wrote, iclass 38, count 0 2006.286.00:50:00.28#ibcon#about to read 3, iclass 38, count 0 2006.286.00:50:00.30#ibcon#read 3, iclass 38, count 0 2006.286.00:50:00.30#ibcon#about to read 4, iclass 38, count 0 2006.286.00:50:00.30#ibcon#read 4, iclass 38, count 0 2006.286.00:50:00.30#ibcon#about to read 5, iclass 38, count 0 2006.286.00:50:00.30#ibcon#read 5, iclass 38, count 0 2006.286.00:50:00.30#ibcon#about to read 6, iclass 38, count 0 2006.286.00:50:00.30#ibcon#read 6, iclass 38, count 0 2006.286.00:50:00.30#ibcon#end of sib2, iclass 38, count 0 2006.286.00:50:00.30#ibcon#*mode == 0, iclass 38, count 0 2006.286.00:50:00.30#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.00:50:00.30#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.00:50:00.30#ibcon#*before write, iclass 38, count 0 2006.286.00:50:00.30#ibcon#enter sib2, iclass 38, count 0 2006.286.00:50:00.30#ibcon#flushed, iclass 38, count 0 2006.286.00:50:00.30#ibcon#about to write, iclass 38, count 0 2006.286.00:50:00.30#ibcon#wrote, iclass 38, count 0 2006.286.00:50:00.30#ibcon#about to read 3, iclass 38, count 0 2006.286.00:50:00.34#ibcon#read 3, iclass 38, count 0 2006.286.00:50:00.34#ibcon#about to read 4, iclass 38, count 0 2006.286.00:50:00.34#ibcon#read 4, iclass 38, count 0 2006.286.00:50:00.34#ibcon#about to read 5, iclass 38, count 0 2006.286.00:50:00.34#ibcon#read 5, iclass 38, count 0 2006.286.00:50:00.34#ibcon#about to read 6, iclass 38, count 0 2006.286.00:50:00.34#ibcon#read 6, iclass 38, count 0 2006.286.00:50:00.34#ibcon#end of sib2, iclass 38, count 0 2006.286.00:50:00.34#ibcon#*after write, iclass 38, count 0 2006.286.00:50:00.34#ibcon#*before return 0, iclass 38, count 0 2006.286.00:50:00.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:50:00.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:50:00.34#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.00:50:00.34#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.00:50:00.34$vck44/va=2,6 2006.286.00:50:00.34#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.00:50:00.34#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.00:50:00.34#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:00.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:50:00.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:50:00.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:50:00.40#ibcon#enter wrdev, iclass 40, count 2 2006.286.00:50:00.40#ibcon#first serial, iclass 40, count 2 2006.286.00:50:00.40#ibcon#enter sib2, iclass 40, count 2 2006.286.00:50:00.40#ibcon#flushed, iclass 40, count 2 2006.286.00:50:00.40#ibcon#about to write, iclass 40, count 2 2006.286.00:50:00.40#ibcon#wrote, iclass 40, count 2 2006.286.00:50:00.40#ibcon#about to read 3, iclass 40, count 2 2006.286.00:50:00.42#ibcon#read 3, iclass 40, count 2 2006.286.00:50:00.42#ibcon#about to read 4, iclass 40, count 2 2006.286.00:50:00.42#ibcon#read 4, iclass 40, count 2 2006.286.00:50:00.42#ibcon#about to read 5, iclass 40, count 2 2006.286.00:50:00.42#ibcon#read 5, iclass 40, count 2 2006.286.00:50:00.42#ibcon#about to read 6, iclass 40, count 2 2006.286.00:50:00.42#ibcon#read 6, iclass 40, count 2 2006.286.00:50:00.42#ibcon#end of sib2, iclass 40, count 2 2006.286.00:50:00.42#ibcon#*mode == 0, iclass 40, count 2 2006.286.00:50:00.42#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.00:50:00.42#ibcon#[25=AT02-06\r\n] 2006.286.00:50:00.42#ibcon#*before write, iclass 40, count 2 2006.286.00:50:00.42#ibcon#enter sib2, iclass 40, count 2 2006.286.00:50:00.42#ibcon#flushed, iclass 40, count 2 2006.286.00:50:00.42#ibcon#about to write, iclass 40, count 2 2006.286.00:50:00.42#ibcon#wrote, iclass 40, count 2 2006.286.00:50:00.42#ibcon#about to read 3, iclass 40, count 2 2006.286.00:50:00.45#ibcon#read 3, iclass 40, count 2 2006.286.00:50:00.45#ibcon#about to read 4, iclass 40, count 2 2006.286.00:50:00.45#ibcon#read 4, iclass 40, count 2 2006.286.00:50:00.45#ibcon#about to read 5, iclass 40, count 2 2006.286.00:50:00.45#ibcon#read 5, iclass 40, count 2 2006.286.00:50:00.45#ibcon#about to read 6, iclass 40, count 2 2006.286.00:50:00.45#ibcon#read 6, iclass 40, count 2 2006.286.00:50:00.45#ibcon#end of sib2, iclass 40, count 2 2006.286.00:50:00.45#ibcon#*after write, iclass 40, count 2 2006.286.00:50:00.45#ibcon#*before return 0, iclass 40, count 2 2006.286.00:50:00.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:50:00.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.00:50:00.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.00:50:00.45#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:00.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:50:00.57#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:50:00.57#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:50:00.57#ibcon#enter wrdev, iclass 40, count 0 2006.286.00:50:00.57#ibcon#first serial, iclass 40, count 0 2006.286.00:50:00.57#ibcon#enter sib2, iclass 40, count 0 2006.286.00:50:00.57#ibcon#flushed, iclass 40, count 0 2006.286.00:50:00.57#ibcon#about to write, iclass 40, count 0 2006.286.00:50:00.57#ibcon#wrote, iclass 40, count 0 2006.286.00:50:00.57#ibcon#about to read 3, iclass 40, count 0 2006.286.00:50:00.59#ibcon#read 3, iclass 40, count 0 2006.286.00:50:00.59#ibcon#about to read 4, iclass 40, count 0 2006.286.00:50:00.59#ibcon#read 4, iclass 40, count 0 2006.286.00:50:00.59#ibcon#about to read 5, iclass 40, count 0 2006.286.00:50:00.59#ibcon#read 5, iclass 40, count 0 2006.286.00:50:00.59#ibcon#about to read 6, iclass 40, count 0 2006.286.00:50:00.59#ibcon#read 6, iclass 40, count 0 2006.286.00:50:00.59#ibcon#end of sib2, iclass 40, count 0 2006.286.00:50:00.59#ibcon#*mode == 0, iclass 40, count 0 2006.286.00:50:00.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.00:50:00.59#ibcon#[25=USB\r\n] 2006.286.00:50:00.59#ibcon#*before write, iclass 40, count 0 2006.286.00:50:00.59#ibcon#enter sib2, iclass 40, count 0 2006.286.00:50:00.59#ibcon#flushed, iclass 40, count 0 2006.286.00:50:00.59#ibcon#about to write, iclass 40, count 0 2006.286.00:50:00.59#ibcon#wrote, iclass 40, count 0 2006.286.00:50:00.59#ibcon#about to read 3, iclass 40, count 0 2006.286.00:50:00.62#ibcon#read 3, iclass 40, count 0 2006.286.00:50:00.62#ibcon#about to read 4, iclass 40, count 0 2006.286.00:50:00.62#ibcon#read 4, iclass 40, count 0 2006.286.00:50:00.62#ibcon#about to read 5, iclass 40, count 0 2006.286.00:50:00.62#ibcon#read 5, iclass 40, count 0 2006.286.00:50:00.62#ibcon#about to read 6, iclass 40, count 0 2006.286.00:50:00.62#ibcon#read 6, iclass 40, count 0 2006.286.00:50:00.62#ibcon#end of sib2, iclass 40, count 0 2006.286.00:50:00.62#ibcon#*after write, iclass 40, count 0 2006.286.00:50:00.62#ibcon#*before return 0, iclass 40, count 0 2006.286.00:50:00.62#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:50:00.62#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.00:50:00.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.00:50:00.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.00:50:00.62$vck44/valo=3,564.99 2006.286.00:50:00.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.00:50:00.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.00:50:00.62#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:00.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:50:00.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:50:00.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:50:00.62#ibcon#enter wrdev, iclass 4, count 0 2006.286.00:50:00.62#ibcon#first serial, iclass 4, count 0 2006.286.00:50:00.62#ibcon#enter sib2, iclass 4, count 0 2006.286.00:50:00.62#ibcon#flushed, iclass 4, count 0 2006.286.00:50:00.62#ibcon#about to write, iclass 4, count 0 2006.286.00:50:00.62#ibcon#wrote, iclass 4, count 0 2006.286.00:50:00.62#ibcon#about to read 3, iclass 4, count 0 2006.286.00:50:00.64#ibcon#read 3, iclass 4, count 0 2006.286.00:50:00.64#ibcon#about to read 4, iclass 4, count 0 2006.286.00:50:00.64#ibcon#read 4, iclass 4, count 0 2006.286.00:50:00.64#ibcon#about to read 5, iclass 4, count 0 2006.286.00:50:00.64#ibcon#read 5, iclass 4, count 0 2006.286.00:50:00.64#ibcon#about to read 6, iclass 4, count 0 2006.286.00:50:00.64#ibcon#read 6, iclass 4, count 0 2006.286.00:50:00.64#ibcon#end of sib2, iclass 4, count 0 2006.286.00:50:00.64#ibcon#*mode == 0, iclass 4, count 0 2006.286.00:50:00.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.00:50:00.64#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.00:50:00.64#ibcon#*before write, iclass 4, count 0 2006.286.00:50:00.64#ibcon#enter sib2, iclass 4, count 0 2006.286.00:50:00.64#ibcon#flushed, iclass 4, count 0 2006.286.00:50:00.64#ibcon#about to write, iclass 4, count 0 2006.286.00:50:00.64#ibcon#wrote, iclass 4, count 0 2006.286.00:50:00.64#ibcon#about to read 3, iclass 4, count 0 2006.286.00:50:00.68#ibcon#read 3, iclass 4, count 0 2006.286.00:50:00.68#ibcon#about to read 4, iclass 4, count 0 2006.286.00:50:00.68#ibcon#read 4, iclass 4, count 0 2006.286.00:50:00.68#ibcon#about to read 5, iclass 4, count 0 2006.286.00:50:00.68#ibcon#read 5, iclass 4, count 0 2006.286.00:50:00.68#ibcon#about to read 6, iclass 4, count 0 2006.286.00:50:00.68#ibcon#read 6, iclass 4, count 0 2006.286.00:50:00.68#ibcon#end of sib2, iclass 4, count 0 2006.286.00:50:00.68#ibcon#*after write, iclass 4, count 0 2006.286.00:50:00.68#ibcon#*before return 0, iclass 4, count 0 2006.286.00:50:00.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:50:00.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.00:50:00.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.00:50:00.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.00:50:00.68$vck44/va=3,7 2006.286.00:50:00.68#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.00:50:00.68#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.00:50:00.68#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:00.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:50:00.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:50:00.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:50:00.74#ibcon#enter wrdev, iclass 6, count 2 2006.286.00:50:00.74#ibcon#first serial, iclass 6, count 2 2006.286.00:50:00.74#ibcon#enter sib2, iclass 6, count 2 2006.286.00:50:00.74#ibcon#flushed, iclass 6, count 2 2006.286.00:50:00.74#ibcon#about to write, iclass 6, count 2 2006.286.00:50:00.74#ibcon#wrote, iclass 6, count 2 2006.286.00:50:00.74#ibcon#about to read 3, iclass 6, count 2 2006.286.00:50:00.76#ibcon#read 3, iclass 6, count 2 2006.286.00:50:00.76#ibcon#about to read 4, iclass 6, count 2 2006.286.00:50:00.76#ibcon#read 4, iclass 6, count 2 2006.286.00:50:00.76#ibcon#about to read 5, iclass 6, count 2 2006.286.00:50:00.76#ibcon#read 5, iclass 6, count 2 2006.286.00:50:00.76#ibcon#about to read 6, iclass 6, count 2 2006.286.00:50:00.76#ibcon#read 6, iclass 6, count 2 2006.286.00:50:00.76#ibcon#end of sib2, iclass 6, count 2 2006.286.00:50:00.76#ibcon#*mode == 0, iclass 6, count 2 2006.286.00:50:00.76#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.00:50:00.76#ibcon#[25=AT03-07\r\n] 2006.286.00:50:00.76#ibcon#*before write, iclass 6, count 2 2006.286.00:50:00.76#ibcon#enter sib2, iclass 6, count 2 2006.286.00:50:00.76#ibcon#flushed, iclass 6, count 2 2006.286.00:50:00.76#ibcon#about to write, iclass 6, count 2 2006.286.00:50:00.76#ibcon#wrote, iclass 6, count 2 2006.286.00:50:00.76#ibcon#about to read 3, iclass 6, count 2 2006.286.00:50:00.79#ibcon#read 3, iclass 6, count 2 2006.286.00:50:00.79#ibcon#about to read 4, iclass 6, count 2 2006.286.00:50:00.79#ibcon#read 4, iclass 6, count 2 2006.286.00:50:00.79#ibcon#about to read 5, iclass 6, count 2 2006.286.00:50:00.79#ibcon#read 5, iclass 6, count 2 2006.286.00:50:00.79#ibcon#about to read 6, iclass 6, count 2 2006.286.00:50:00.79#ibcon#read 6, iclass 6, count 2 2006.286.00:50:00.79#ibcon#end of sib2, iclass 6, count 2 2006.286.00:50:00.79#ibcon#*after write, iclass 6, count 2 2006.286.00:50:00.79#ibcon#*before return 0, iclass 6, count 2 2006.286.00:50:00.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:50:00.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:50:00.79#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.00:50:00.79#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:00.79#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:50:00.91#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:50:00.91#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:50:00.91#ibcon#enter wrdev, iclass 6, count 0 2006.286.00:50:00.91#ibcon#first serial, iclass 6, count 0 2006.286.00:50:00.91#ibcon#enter sib2, iclass 6, count 0 2006.286.00:50:00.91#ibcon#flushed, iclass 6, count 0 2006.286.00:50:00.91#ibcon#about to write, iclass 6, count 0 2006.286.00:50:00.91#ibcon#wrote, iclass 6, count 0 2006.286.00:50:00.91#ibcon#about to read 3, iclass 6, count 0 2006.286.00:50:00.93#ibcon#read 3, iclass 6, count 0 2006.286.00:50:00.93#ibcon#about to read 4, iclass 6, count 0 2006.286.00:50:00.93#ibcon#read 4, iclass 6, count 0 2006.286.00:50:00.93#ibcon#about to read 5, iclass 6, count 0 2006.286.00:50:00.93#ibcon#read 5, iclass 6, count 0 2006.286.00:50:00.93#ibcon#about to read 6, iclass 6, count 0 2006.286.00:50:00.93#ibcon#read 6, iclass 6, count 0 2006.286.00:50:00.93#ibcon#end of sib2, iclass 6, count 0 2006.286.00:50:00.93#ibcon#*mode == 0, iclass 6, count 0 2006.286.00:50:00.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.00:50:00.93#ibcon#[25=USB\r\n] 2006.286.00:50:00.93#ibcon#*before write, iclass 6, count 0 2006.286.00:50:00.93#ibcon#enter sib2, iclass 6, count 0 2006.286.00:50:00.93#ibcon#flushed, iclass 6, count 0 2006.286.00:50:00.93#ibcon#about to write, iclass 6, count 0 2006.286.00:50:00.93#ibcon#wrote, iclass 6, count 0 2006.286.00:50:00.93#ibcon#about to read 3, iclass 6, count 0 2006.286.00:50:00.96#ibcon#read 3, iclass 6, count 0 2006.286.00:50:00.96#ibcon#about to read 4, iclass 6, count 0 2006.286.00:50:00.96#ibcon#read 4, iclass 6, count 0 2006.286.00:50:00.96#ibcon#about to read 5, iclass 6, count 0 2006.286.00:50:00.96#ibcon#read 5, iclass 6, count 0 2006.286.00:50:00.96#ibcon#about to read 6, iclass 6, count 0 2006.286.00:50:00.96#ibcon#read 6, iclass 6, count 0 2006.286.00:50:00.96#ibcon#end of sib2, iclass 6, count 0 2006.286.00:50:00.96#ibcon#*after write, iclass 6, count 0 2006.286.00:50:00.96#ibcon#*before return 0, iclass 6, count 0 2006.286.00:50:00.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:50:00.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:50:00.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.00:50:00.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.00:50:00.96$vck44/valo=4,624.99 2006.286.00:50:00.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.00:50:00.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.00:50:00.96#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:00.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:50:00.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:50:00.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:50:00.96#ibcon#enter wrdev, iclass 10, count 0 2006.286.00:50:00.96#ibcon#first serial, iclass 10, count 0 2006.286.00:50:00.96#ibcon#enter sib2, iclass 10, count 0 2006.286.00:50:00.96#ibcon#flushed, iclass 10, count 0 2006.286.00:50:00.96#ibcon#about to write, iclass 10, count 0 2006.286.00:50:00.96#ibcon#wrote, iclass 10, count 0 2006.286.00:50:00.96#ibcon#about to read 3, iclass 10, count 0 2006.286.00:50:00.98#ibcon#read 3, iclass 10, count 0 2006.286.00:50:00.98#ibcon#about to read 4, iclass 10, count 0 2006.286.00:50:00.98#ibcon#read 4, iclass 10, count 0 2006.286.00:50:00.98#ibcon#about to read 5, iclass 10, count 0 2006.286.00:50:00.98#ibcon#read 5, iclass 10, count 0 2006.286.00:50:00.98#ibcon#about to read 6, iclass 10, count 0 2006.286.00:50:00.98#ibcon#read 6, iclass 10, count 0 2006.286.00:50:00.98#ibcon#end of sib2, iclass 10, count 0 2006.286.00:50:00.98#ibcon#*mode == 0, iclass 10, count 0 2006.286.00:50:00.98#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.00:50:00.98#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.00:50:00.98#ibcon#*before write, iclass 10, count 0 2006.286.00:50:00.98#ibcon#enter sib2, iclass 10, count 0 2006.286.00:50:00.98#ibcon#flushed, iclass 10, count 0 2006.286.00:50:00.98#ibcon#about to write, iclass 10, count 0 2006.286.00:50:00.98#ibcon#wrote, iclass 10, count 0 2006.286.00:50:00.98#ibcon#about to read 3, iclass 10, count 0 2006.286.00:50:01.02#ibcon#read 3, iclass 10, count 0 2006.286.00:50:01.02#ibcon#about to read 4, iclass 10, count 0 2006.286.00:50:01.02#ibcon#read 4, iclass 10, count 0 2006.286.00:50:01.02#ibcon#about to read 5, iclass 10, count 0 2006.286.00:50:01.02#ibcon#read 5, iclass 10, count 0 2006.286.00:50:01.02#ibcon#about to read 6, iclass 10, count 0 2006.286.00:50:01.02#ibcon#read 6, iclass 10, count 0 2006.286.00:50:01.02#ibcon#end of sib2, iclass 10, count 0 2006.286.00:50:01.02#ibcon#*after write, iclass 10, count 0 2006.286.00:50:01.02#ibcon#*before return 0, iclass 10, count 0 2006.286.00:50:01.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:50:01.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:50:01.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.00:50:01.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.00:50:01.02$vck44/va=4,6 2006.286.00:50:01.02#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.00:50:01.02#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.00:50:01.02#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:01.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:50:01.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:50:01.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:50:01.08#ibcon#enter wrdev, iclass 12, count 2 2006.286.00:50:01.08#ibcon#first serial, iclass 12, count 2 2006.286.00:50:01.08#ibcon#enter sib2, iclass 12, count 2 2006.286.00:50:01.08#ibcon#flushed, iclass 12, count 2 2006.286.00:50:01.08#ibcon#about to write, iclass 12, count 2 2006.286.00:50:01.08#ibcon#wrote, iclass 12, count 2 2006.286.00:50:01.08#ibcon#about to read 3, iclass 12, count 2 2006.286.00:50:01.10#ibcon#read 3, iclass 12, count 2 2006.286.00:50:01.10#ibcon#about to read 4, iclass 12, count 2 2006.286.00:50:01.10#ibcon#read 4, iclass 12, count 2 2006.286.00:50:01.10#ibcon#about to read 5, iclass 12, count 2 2006.286.00:50:01.10#ibcon#read 5, iclass 12, count 2 2006.286.00:50:01.10#ibcon#about to read 6, iclass 12, count 2 2006.286.00:50:01.10#ibcon#read 6, iclass 12, count 2 2006.286.00:50:01.10#ibcon#end of sib2, iclass 12, count 2 2006.286.00:50:01.10#ibcon#*mode == 0, iclass 12, count 2 2006.286.00:50:01.10#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.00:50:01.10#ibcon#[25=AT04-06\r\n] 2006.286.00:50:01.10#ibcon#*before write, iclass 12, count 2 2006.286.00:50:01.10#ibcon#enter sib2, iclass 12, count 2 2006.286.00:50:01.10#ibcon#flushed, iclass 12, count 2 2006.286.00:50:01.10#ibcon#about to write, iclass 12, count 2 2006.286.00:50:01.10#ibcon#wrote, iclass 12, count 2 2006.286.00:50:01.10#ibcon#about to read 3, iclass 12, count 2 2006.286.00:50:01.13#ibcon#read 3, iclass 12, count 2 2006.286.00:50:01.13#ibcon#about to read 4, iclass 12, count 2 2006.286.00:50:01.13#ibcon#read 4, iclass 12, count 2 2006.286.00:50:01.13#ibcon#about to read 5, iclass 12, count 2 2006.286.00:50:01.13#ibcon#read 5, iclass 12, count 2 2006.286.00:50:01.13#ibcon#about to read 6, iclass 12, count 2 2006.286.00:50:01.13#ibcon#read 6, iclass 12, count 2 2006.286.00:50:01.13#ibcon#end of sib2, iclass 12, count 2 2006.286.00:50:01.13#ibcon#*after write, iclass 12, count 2 2006.286.00:50:01.13#ibcon#*before return 0, iclass 12, count 2 2006.286.00:50:01.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:50:01.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:50:01.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.00:50:01.13#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:01.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:50:01.25#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:50:01.25#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:50:01.25#ibcon#enter wrdev, iclass 12, count 0 2006.286.00:50:01.25#ibcon#first serial, iclass 12, count 0 2006.286.00:50:01.25#ibcon#enter sib2, iclass 12, count 0 2006.286.00:50:01.25#ibcon#flushed, iclass 12, count 0 2006.286.00:50:01.25#ibcon#about to write, iclass 12, count 0 2006.286.00:50:01.25#ibcon#wrote, iclass 12, count 0 2006.286.00:50:01.25#ibcon#about to read 3, iclass 12, count 0 2006.286.00:50:01.27#ibcon#read 3, iclass 12, count 0 2006.286.00:50:01.27#ibcon#about to read 4, iclass 12, count 0 2006.286.00:50:01.27#ibcon#read 4, iclass 12, count 0 2006.286.00:50:01.27#ibcon#about to read 5, iclass 12, count 0 2006.286.00:50:01.27#ibcon#read 5, iclass 12, count 0 2006.286.00:50:01.27#ibcon#about to read 6, iclass 12, count 0 2006.286.00:50:01.27#ibcon#read 6, iclass 12, count 0 2006.286.00:50:01.27#ibcon#end of sib2, iclass 12, count 0 2006.286.00:50:01.27#ibcon#*mode == 0, iclass 12, count 0 2006.286.00:50:01.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.00:50:01.27#ibcon#[25=USB\r\n] 2006.286.00:50:01.27#ibcon#*before write, iclass 12, count 0 2006.286.00:50:01.27#ibcon#enter sib2, iclass 12, count 0 2006.286.00:50:01.27#ibcon#flushed, iclass 12, count 0 2006.286.00:50:01.27#ibcon#about to write, iclass 12, count 0 2006.286.00:50:01.27#ibcon#wrote, iclass 12, count 0 2006.286.00:50:01.27#ibcon#about to read 3, iclass 12, count 0 2006.286.00:50:01.30#ibcon#read 3, iclass 12, count 0 2006.286.00:50:01.30#ibcon#about to read 4, iclass 12, count 0 2006.286.00:50:01.30#ibcon#read 4, iclass 12, count 0 2006.286.00:50:01.30#ibcon#about to read 5, iclass 12, count 0 2006.286.00:50:01.30#ibcon#read 5, iclass 12, count 0 2006.286.00:50:01.30#ibcon#about to read 6, iclass 12, count 0 2006.286.00:50:01.30#ibcon#read 6, iclass 12, count 0 2006.286.00:50:01.30#ibcon#end of sib2, iclass 12, count 0 2006.286.00:50:01.30#ibcon#*after write, iclass 12, count 0 2006.286.00:50:01.30#ibcon#*before return 0, iclass 12, count 0 2006.286.00:50:01.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:50:01.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:50:01.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.00:50:01.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.00:50:01.30$vck44/valo=5,734.99 2006.286.00:50:01.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.00:50:01.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.00:50:01.30#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:01.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:50:01.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:50:01.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:50:01.30#ibcon#enter wrdev, iclass 14, count 0 2006.286.00:50:01.30#ibcon#first serial, iclass 14, count 0 2006.286.00:50:01.30#ibcon#enter sib2, iclass 14, count 0 2006.286.00:50:01.30#ibcon#flushed, iclass 14, count 0 2006.286.00:50:01.30#ibcon#about to write, iclass 14, count 0 2006.286.00:50:01.30#ibcon#wrote, iclass 14, count 0 2006.286.00:50:01.30#ibcon#about to read 3, iclass 14, count 0 2006.286.00:50:01.32#ibcon#read 3, iclass 14, count 0 2006.286.00:50:01.32#ibcon#about to read 4, iclass 14, count 0 2006.286.00:50:01.32#ibcon#read 4, iclass 14, count 0 2006.286.00:50:01.32#ibcon#about to read 5, iclass 14, count 0 2006.286.00:50:01.32#ibcon#read 5, iclass 14, count 0 2006.286.00:50:01.32#ibcon#about to read 6, iclass 14, count 0 2006.286.00:50:01.32#ibcon#read 6, iclass 14, count 0 2006.286.00:50:01.32#ibcon#end of sib2, iclass 14, count 0 2006.286.00:50:01.32#ibcon#*mode == 0, iclass 14, count 0 2006.286.00:50:01.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.00:50:01.32#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.00:50:01.32#ibcon#*before write, iclass 14, count 0 2006.286.00:50:01.32#ibcon#enter sib2, iclass 14, count 0 2006.286.00:50:01.32#ibcon#flushed, iclass 14, count 0 2006.286.00:50:01.32#ibcon#about to write, iclass 14, count 0 2006.286.00:50:01.32#ibcon#wrote, iclass 14, count 0 2006.286.00:50:01.32#ibcon#about to read 3, iclass 14, count 0 2006.286.00:50:01.36#ibcon#read 3, iclass 14, count 0 2006.286.00:50:01.36#ibcon#about to read 4, iclass 14, count 0 2006.286.00:50:01.36#ibcon#read 4, iclass 14, count 0 2006.286.00:50:01.36#ibcon#about to read 5, iclass 14, count 0 2006.286.00:50:01.36#ibcon#read 5, iclass 14, count 0 2006.286.00:50:01.36#ibcon#about to read 6, iclass 14, count 0 2006.286.00:50:01.36#ibcon#read 6, iclass 14, count 0 2006.286.00:50:01.36#ibcon#end of sib2, iclass 14, count 0 2006.286.00:50:01.36#ibcon#*after write, iclass 14, count 0 2006.286.00:50:01.36#ibcon#*before return 0, iclass 14, count 0 2006.286.00:50:01.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:50:01.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:50:01.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.00:50:01.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.00:50:01.36$vck44/va=5,3 2006.286.00:50:01.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.00:50:01.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.00:50:01.36#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:01.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:50:01.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:50:01.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:50:01.42#ibcon#enter wrdev, iclass 16, count 2 2006.286.00:50:01.42#ibcon#first serial, iclass 16, count 2 2006.286.00:50:01.42#ibcon#enter sib2, iclass 16, count 2 2006.286.00:50:01.42#ibcon#flushed, iclass 16, count 2 2006.286.00:50:01.42#ibcon#about to write, iclass 16, count 2 2006.286.00:50:01.42#ibcon#wrote, iclass 16, count 2 2006.286.00:50:01.42#ibcon#about to read 3, iclass 16, count 2 2006.286.00:50:01.44#ibcon#read 3, iclass 16, count 2 2006.286.00:50:01.44#ibcon#about to read 4, iclass 16, count 2 2006.286.00:50:01.44#ibcon#read 4, iclass 16, count 2 2006.286.00:50:01.44#ibcon#about to read 5, iclass 16, count 2 2006.286.00:50:01.44#ibcon#read 5, iclass 16, count 2 2006.286.00:50:01.44#ibcon#about to read 6, iclass 16, count 2 2006.286.00:50:01.44#ibcon#read 6, iclass 16, count 2 2006.286.00:50:01.44#ibcon#end of sib2, iclass 16, count 2 2006.286.00:50:01.44#ibcon#*mode == 0, iclass 16, count 2 2006.286.00:50:01.44#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.00:50:01.44#ibcon#[25=AT05-03\r\n] 2006.286.00:50:01.44#ibcon#*before write, iclass 16, count 2 2006.286.00:50:01.44#ibcon#enter sib2, iclass 16, count 2 2006.286.00:50:01.44#ibcon#flushed, iclass 16, count 2 2006.286.00:50:01.44#ibcon#about to write, iclass 16, count 2 2006.286.00:50:01.44#ibcon#wrote, iclass 16, count 2 2006.286.00:50:01.44#ibcon#about to read 3, iclass 16, count 2 2006.286.00:50:01.47#ibcon#read 3, iclass 16, count 2 2006.286.00:50:01.47#ibcon#about to read 4, iclass 16, count 2 2006.286.00:50:01.47#ibcon#read 4, iclass 16, count 2 2006.286.00:50:01.47#ibcon#about to read 5, iclass 16, count 2 2006.286.00:50:01.47#ibcon#read 5, iclass 16, count 2 2006.286.00:50:01.47#ibcon#about to read 6, iclass 16, count 2 2006.286.00:50:01.47#ibcon#read 6, iclass 16, count 2 2006.286.00:50:01.47#ibcon#end of sib2, iclass 16, count 2 2006.286.00:50:01.47#ibcon#*after write, iclass 16, count 2 2006.286.00:50:01.47#ibcon#*before return 0, iclass 16, count 2 2006.286.00:50:01.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:50:01.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:50:01.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.00:50:01.47#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:01.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:50:01.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:50:01.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:50:01.59#ibcon#enter wrdev, iclass 16, count 0 2006.286.00:50:01.59#ibcon#first serial, iclass 16, count 0 2006.286.00:50:01.59#ibcon#enter sib2, iclass 16, count 0 2006.286.00:50:01.59#ibcon#flushed, iclass 16, count 0 2006.286.00:50:01.59#ibcon#about to write, iclass 16, count 0 2006.286.00:50:01.59#ibcon#wrote, iclass 16, count 0 2006.286.00:50:01.59#ibcon#about to read 3, iclass 16, count 0 2006.286.00:50:01.61#ibcon#read 3, iclass 16, count 0 2006.286.00:50:01.61#ibcon#about to read 4, iclass 16, count 0 2006.286.00:50:01.61#ibcon#read 4, iclass 16, count 0 2006.286.00:50:01.61#ibcon#about to read 5, iclass 16, count 0 2006.286.00:50:01.61#ibcon#read 5, iclass 16, count 0 2006.286.00:50:01.61#ibcon#about to read 6, iclass 16, count 0 2006.286.00:50:01.61#ibcon#read 6, iclass 16, count 0 2006.286.00:50:01.61#ibcon#end of sib2, iclass 16, count 0 2006.286.00:50:01.61#ibcon#*mode == 0, iclass 16, count 0 2006.286.00:50:01.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.00:50:01.61#ibcon#[25=USB\r\n] 2006.286.00:50:01.61#ibcon#*before write, iclass 16, count 0 2006.286.00:50:01.61#ibcon#enter sib2, iclass 16, count 0 2006.286.00:50:01.61#ibcon#flushed, iclass 16, count 0 2006.286.00:50:01.61#ibcon#about to write, iclass 16, count 0 2006.286.00:50:01.61#ibcon#wrote, iclass 16, count 0 2006.286.00:50:01.61#ibcon#about to read 3, iclass 16, count 0 2006.286.00:50:01.64#ibcon#read 3, iclass 16, count 0 2006.286.00:50:01.64#ibcon#about to read 4, iclass 16, count 0 2006.286.00:50:01.64#ibcon#read 4, iclass 16, count 0 2006.286.00:50:01.64#ibcon#about to read 5, iclass 16, count 0 2006.286.00:50:01.64#ibcon#read 5, iclass 16, count 0 2006.286.00:50:01.64#ibcon#about to read 6, iclass 16, count 0 2006.286.00:50:01.64#ibcon#read 6, iclass 16, count 0 2006.286.00:50:01.64#ibcon#end of sib2, iclass 16, count 0 2006.286.00:50:01.64#ibcon#*after write, iclass 16, count 0 2006.286.00:50:01.64#ibcon#*before return 0, iclass 16, count 0 2006.286.00:50:01.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:50:01.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:50:01.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.00:50:01.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.00:50:01.64$vck44/valo=6,814.99 2006.286.00:50:01.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.00:50:01.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.00:50:01.64#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:01.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:50:01.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:50:01.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:50:01.64#ibcon#enter wrdev, iclass 18, count 0 2006.286.00:50:01.64#ibcon#first serial, iclass 18, count 0 2006.286.00:50:01.64#ibcon#enter sib2, iclass 18, count 0 2006.286.00:50:01.64#ibcon#flushed, iclass 18, count 0 2006.286.00:50:01.64#ibcon#about to write, iclass 18, count 0 2006.286.00:50:01.64#ibcon#wrote, iclass 18, count 0 2006.286.00:50:01.64#ibcon#about to read 3, iclass 18, count 0 2006.286.00:50:01.66#ibcon#read 3, iclass 18, count 0 2006.286.00:50:01.66#ibcon#about to read 4, iclass 18, count 0 2006.286.00:50:01.66#ibcon#read 4, iclass 18, count 0 2006.286.00:50:01.66#ibcon#about to read 5, iclass 18, count 0 2006.286.00:50:01.66#ibcon#read 5, iclass 18, count 0 2006.286.00:50:01.66#ibcon#about to read 6, iclass 18, count 0 2006.286.00:50:01.66#ibcon#read 6, iclass 18, count 0 2006.286.00:50:01.66#ibcon#end of sib2, iclass 18, count 0 2006.286.00:50:01.66#ibcon#*mode == 0, iclass 18, count 0 2006.286.00:50:01.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.00:50:01.66#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.00:50:01.66#ibcon#*before write, iclass 18, count 0 2006.286.00:50:01.66#ibcon#enter sib2, iclass 18, count 0 2006.286.00:50:01.66#ibcon#flushed, iclass 18, count 0 2006.286.00:50:01.66#ibcon#about to write, iclass 18, count 0 2006.286.00:50:01.66#ibcon#wrote, iclass 18, count 0 2006.286.00:50:01.66#ibcon#about to read 3, iclass 18, count 0 2006.286.00:50:01.70#ibcon#read 3, iclass 18, count 0 2006.286.00:50:01.70#ibcon#about to read 4, iclass 18, count 0 2006.286.00:50:01.70#ibcon#read 4, iclass 18, count 0 2006.286.00:50:01.70#ibcon#about to read 5, iclass 18, count 0 2006.286.00:50:01.70#ibcon#read 5, iclass 18, count 0 2006.286.00:50:01.70#ibcon#about to read 6, iclass 18, count 0 2006.286.00:50:01.70#ibcon#read 6, iclass 18, count 0 2006.286.00:50:01.70#ibcon#end of sib2, iclass 18, count 0 2006.286.00:50:01.70#ibcon#*after write, iclass 18, count 0 2006.286.00:50:01.70#ibcon#*before return 0, iclass 18, count 0 2006.286.00:50:01.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:50:01.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:50:01.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.00:50:01.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.00:50:01.70$vck44/va=6,4 2006.286.00:50:01.70#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.00:50:01.70#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.00:50:01.70#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:01.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:50:01.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:50:01.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:50:01.76#ibcon#enter wrdev, iclass 20, count 2 2006.286.00:50:01.76#ibcon#first serial, iclass 20, count 2 2006.286.00:50:01.76#ibcon#enter sib2, iclass 20, count 2 2006.286.00:50:01.76#ibcon#flushed, iclass 20, count 2 2006.286.00:50:01.76#ibcon#about to write, iclass 20, count 2 2006.286.00:50:01.76#ibcon#wrote, iclass 20, count 2 2006.286.00:50:01.76#ibcon#about to read 3, iclass 20, count 2 2006.286.00:50:01.78#ibcon#read 3, iclass 20, count 2 2006.286.00:50:01.78#ibcon#about to read 4, iclass 20, count 2 2006.286.00:50:01.78#ibcon#read 4, iclass 20, count 2 2006.286.00:50:01.78#ibcon#about to read 5, iclass 20, count 2 2006.286.00:50:01.78#ibcon#read 5, iclass 20, count 2 2006.286.00:50:01.78#ibcon#about to read 6, iclass 20, count 2 2006.286.00:50:01.78#ibcon#read 6, iclass 20, count 2 2006.286.00:50:01.78#ibcon#end of sib2, iclass 20, count 2 2006.286.00:50:01.78#ibcon#*mode == 0, iclass 20, count 2 2006.286.00:50:01.78#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.00:50:01.78#ibcon#[25=AT06-04\r\n] 2006.286.00:50:01.78#ibcon#*before write, iclass 20, count 2 2006.286.00:50:01.78#ibcon#enter sib2, iclass 20, count 2 2006.286.00:50:01.78#ibcon#flushed, iclass 20, count 2 2006.286.00:50:01.78#ibcon#about to write, iclass 20, count 2 2006.286.00:50:01.78#ibcon#wrote, iclass 20, count 2 2006.286.00:50:01.78#ibcon#about to read 3, iclass 20, count 2 2006.286.00:50:01.81#ibcon#read 3, iclass 20, count 2 2006.286.00:50:01.81#ibcon#about to read 4, iclass 20, count 2 2006.286.00:50:01.81#ibcon#read 4, iclass 20, count 2 2006.286.00:50:01.81#ibcon#about to read 5, iclass 20, count 2 2006.286.00:50:01.81#ibcon#read 5, iclass 20, count 2 2006.286.00:50:01.81#ibcon#about to read 6, iclass 20, count 2 2006.286.00:50:01.81#ibcon#read 6, iclass 20, count 2 2006.286.00:50:01.81#ibcon#end of sib2, iclass 20, count 2 2006.286.00:50:01.81#ibcon#*after write, iclass 20, count 2 2006.286.00:50:01.81#ibcon#*before return 0, iclass 20, count 2 2006.286.00:50:01.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:50:01.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:50:01.81#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.00:50:01.81#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:01.81#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:50:01.93#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:50:01.93#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:50:01.93#ibcon#enter wrdev, iclass 20, count 0 2006.286.00:50:01.93#ibcon#first serial, iclass 20, count 0 2006.286.00:50:01.93#ibcon#enter sib2, iclass 20, count 0 2006.286.00:50:01.93#ibcon#flushed, iclass 20, count 0 2006.286.00:50:01.93#ibcon#about to write, iclass 20, count 0 2006.286.00:50:01.93#ibcon#wrote, iclass 20, count 0 2006.286.00:50:01.93#ibcon#about to read 3, iclass 20, count 0 2006.286.00:50:01.95#ibcon#read 3, iclass 20, count 0 2006.286.00:50:01.95#ibcon#about to read 4, iclass 20, count 0 2006.286.00:50:01.95#ibcon#read 4, iclass 20, count 0 2006.286.00:50:01.95#ibcon#about to read 5, iclass 20, count 0 2006.286.00:50:01.95#ibcon#read 5, iclass 20, count 0 2006.286.00:50:01.95#ibcon#about to read 6, iclass 20, count 0 2006.286.00:50:01.95#ibcon#read 6, iclass 20, count 0 2006.286.00:50:01.95#ibcon#end of sib2, iclass 20, count 0 2006.286.00:50:01.95#ibcon#*mode == 0, iclass 20, count 0 2006.286.00:50:01.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.00:50:01.95#ibcon#[25=USB\r\n] 2006.286.00:50:01.95#ibcon#*before write, iclass 20, count 0 2006.286.00:50:01.95#ibcon#enter sib2, iclass 20, count 0 2006.286.00:50:01.95#ibcon#flushed, iclass 20, count 0 2006.286.00:50:01.95#ibcon#about to write, iclass 20, count 0 2006.286.00:50:01.95#ibcon#wrote, iclass 20, count 0 2006.286.00:50:01.95#ibcon#about to read 3, iclass 20, count 0 2006.286.00:50:01.98#ibcon#read 3, iclass 20, count 0 2006.286.00:50:01.98#ibcon#about to read 4, iclass 20, count 0 2006.286.00:50:01.98#ibcon#read 4, iclass 20, count 0 2006.286.00:50:01.98#ibcon#about to read 5, iclass 20, count 0 2006.286.00:50:01.98#ibcon#read 5, iclass 20, count 0 2006.286.00:50:01.98#ibcon#about to read 6, iclass 20, count 0 2006.286.00:50:01.98#ibcon#read 6, iclass 20, count 0 2006.286.00:50:01.98#ibcon#end of sib2, iclass 20, count 0 2006.286.00:50:01.98#ibcon#*after write, iclass 20, count 0 2006.286.00:50:01.98#ibcon#*before return 0, iclass 20, count 0 2006.286.00:50:01.98#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:50:01.98#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:50:01.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.00:50:01.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.00:50:01.98$vck44/valo=7,864.99 2006.286.00:50:01.98#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.00:50:01.98#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.00:50:01.98#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:01.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:50:01.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:50:01.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:50:01.98#ibcon#enter wrdev, iclass 22, count 0 2006.286.00:50:01.98#ibcon#first serial, iclass 22, count 0 2006.286.00:50:01.98#ibcon#enter sib2, iclass 22, count 0 2006.286.00:50:01.98#ibcon#flushed, iclass 22, count 0 2006.286.00:50:01.98#ibcon#about to write, iclass 22, count 0 2006.286.00:50:01.98#ibcon#wrote, iclass 22, count 0 2006.286.00:50:01.98#ibcon#about to read 3, iclass 22, count 0 2006.286.00:50:02.00#ibcon#read 3, iclass 22, count 0 2006.286.00:50:02.00#ibcon#about to read 4, iclass 22, count 0 2006.286.00:50:02.00#ibcon#read 4, iclass 22, count 0 2006.286.00:50:02.00#ibcon#about to read 5, iclass 22, count 0 2006.286.00:50:02.00#ibcon#read 5, iclass 22, count 0 2006.286.00:50:02.00#ibcon#about to read 6, iclass 22, count 0 2006.286.00:50:02.00#ibcon#read 6, iclass 22, count 0 2006.286.00:50:02.00#ibcon#end of sib2, iclass 22, count 0 2006.286.00:50:02.00#ibcon#*mode == 0, iclass 22, count 0 2006.286.00:50:02.00#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.00:50:02.00#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.00:50:02.00#ibcon#*before write, iclass 22, count 0 2006.286.00:50:02.00#ibcon#enter sib2, iclass 22, count 0 2006.286.00:50:02.00#ibcon#flushed, iclass 22, count 0 2006.286.00:50:02.00#ibcon#about to write, iclass 22, count 0 2006.286.00:50:02.00#ibcon#wrote, iclass 22, count 0 2006.286.00:50:02.00#ibcon#about to read 3, iclass 22, count 0 2006.286.00:50:02.04#ibcon#read 3, iclass 22, count 0 2006.286.00:50:02.04#ibcon#about to read 4, iclass 22, count 0 2006.286.00:50:02.04#ibcon#read 4, iclass 22, count 0 2006.286.00:50:02.04#ibcon#about to read 5, iclass 22, count 0 2006.286.00:50:02.04#ibcon#read 5, iclass 22, count 0 2006.286.00:50:02.04#ibcon#about to read 6, iclass 22, count 0 2006.286.00:50:02.04#ibcon#read 6, iclass 22, count 0 2006.286.00:50:02.04#ibcon#end of sib2, iclass 22, count 0 2006.286.00:50:02.04#ibcon#*after write, iclass 22, count 0 2006.286.00:50:02.04#ibcon#*before return 0, iclass 22, count 0 2006.286.00:50:02.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:50:02.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:50:02.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.00:50:02.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.00:50:02.04$vck44/va=7,4 2006.286.00:50:02.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.00:50:02.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.00:50:02.04#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:02.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:50:02.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:50:02.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:50:02.10#ibcon#enter wrdev, iclass 24, count 2 2006.286.00:50:02.10#ibcon#first serial, iclass 24, count 2 2006.286.00:50:02.10#ibcon#enter sib2, iclass 24, count 2 2006.286.00:50:02.10#ibcon#flushed, iclass 24, count 2 2006.286.00:50:02.10#ibcon#about to write, iclass 24, count 2 2006.286.00:50:02.10#ibcon#wrote, iclass 24, count 2 2006.286.00:50:02.10#ibcon#about to read 3, iclass 24, count 2 2006.286.00:50:02.12#ibcon#read 3, iclass 24, count 2 2006.286.00:50:02.12#ibcon#about to read 4, iclass 24, count 2 2006.286.00:50:02.12#ibcon#read 4, iclass 24, count 2 2006.286.00:50:02.12#ibcon#about to read 5, iclass 24, count 2 2006.286.00:50:02.12#ibcon#read 5, iclass 24, count 2 2006.286.00:50:02.12#ibcon#about to read 6, iclass 24, count 2 2006.286.00:50:02.12#ibcon#read 6, iclass 24, count 2 2006.286.00:50:02.12#ibcon#end of sib2, iclass 24, count 2 2006.286.00:50:02.12#ibcon#*mode == 0, iclass 24, count 2 2006.286.00:50:02.12#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.00:50:02.12#ibcon#[25=AT07-04\r\n] 2006.286.00:50:02.12#ibcon#*before write, iclass 24, count 2 2006.286.00:50:02.12#ibcon#enter sib2, iclass 24, count 2 2006.286.00:50:02.12#ibcon#flushed, iclass 24, count 2 2006.286.00:50:02.12#ibcon#about to write, iclass 24, count 2 2006.286.00:50:02.12#ibcon#wrote, iclass 24, count 2 2006.286.00:50:02.12#ibcon#about to read 3, iclass 24, count 2 2006.286.00:50:02.15#ibcon#read 3, iclass 24, count 2 2006.286.00:50:02.15#ibcon#about to read 4, iclass 24, count 2 2006.286.00:50:02.15#ibcon#read 4, iclass 24, count 2 2006.286.00:50:02.15#ibcon#about to read 5, iclass 24, count 2 2006.286.00:50:02.15#ibcon#read 5, iclass 24, count 2 2006.286.00:50:02.15#ibcon#about to read 6, iclass 24, count 2 2006.286.00:50:02.15#ibcon#read 6, iclass 24, count 2 2006.286.00:50:02.15#ibcon#end of sib2, iclass 24, count 2 2006.286.00:50:02.15#ibcon#*after write, iclass 24, count 2 2006.286.00:50:02.15#ibcon#*before return 0, iclass 24, count 2 2006.286.00:50:02.15#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:50:02.15#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:50:02.15#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.00:50:02.15#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:02.15#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:50:02.27#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:50:02.27#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:50:02.27#ibcon#enter wrdev, iclass 24, count 0 2006.286.00:50:02.27#ibcon#first serial, iclass 24, count 0 2006.286.00:50:02.27#ibcon#enter sib2, iclass 24, count 0 2006.286.00:50:02.27#ibcon#flushed, iclass 24, count 0 2006.286.00:50:02.27#ibcon#about to write, iclass 24, count 0 2006.286.00:50:02.27#ibcon#wrote, iclass 24, count 0 2006.286.00:50:02.27#ibcon#about to read 3, iclass 24, count 0 2006.286.00:50:02.29#ibcon#read 3, iclass 24, count 0 2006.286.00:50:02.29#ibcon#about to read 4, iclass 24, count 0 2006.286.00:50:02.29#ibcon#read 4, iclass 24, count 0 2006.286.00:50:02.29#ibcon#about to read 5, iclass 24, count 0 2006.286.00:50:02.29#ibcon#read 5, iclass 24, count 0 2006.286.00:50:02.29#ibcon#about to read 6, iclass 24, count 0 2006.286.00:50:02.29#ibcon#read 6, iclass 24, count 0 2006.286.00:50:02.29#ibcon#end of sib2, iclass 24, count 0 2006.286.00:50:02.29#ibcon#*mode == 0, iclass 24, count 0 2006.286.00:50:02.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.00:50:02.29#ibcon#[25=USB\r\n] 2006.286.00:50:02.29#ibcon#*before write, iclass 24, count 0 2006.286.00:50:02.29#ibcon#enter sib2, iclass 24, count 0 2006.286.00:50:02.29#ibcon#flushed, iclass 24, count 0 2006.286.00:50:02.29#ibcon#about to write, iclass 24, count 0 2006.286.00:50:02.29#ibcon#wrote, iclass 24, count 0 2006.286.00:50:02.29#ibcon#about to read 3, iclass 24, count 0 2006.286.00:50:02.32#ibcon#read 3, iclass 24, count 0 2006.286.00:50:02.32#ibcon#about to read 4, iclass 24, count 0 2006.286.00:50:02.32#ibcon#read 4, iclass 24, count 0 2006.286.00:50:02.32#ibcon#about to read 5, iclass 24, count 0 2006.286.00:50:02.32#ibcon#read 5, iclass 24, count 0 2006.286.00:50:02.32#ibcon#about to read 6, iclass 24, count 0 2006.286.00:50:02.32#ibcon#read 6, iclass 24, count 0 2006.286.00:50:02.32#ibcon#end of sib2, iclass 24, count 0 2006.286.00:50:02.32#ibcon#*after write, iclass 24, count 0 2006.286.00:50:02.32#ibcon#*before return 0, iclass 24, count 0 2006.286.00:50:02.32#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:50:02.32#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:50:02.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.00:50:02.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.00:50:02.32$vck44/valo=8,884.99 2006.286.00:50:02.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.00:50:02.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.00:50:02.32#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:02.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:50:02.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:50:02.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:50:02.32#ibcon#enter wrdev, iclass 26, count 0 2006.286.00:50:02.32#ibcon#first serial, iclass 26, count 0 2006.286.00:50:02.32#ibcon#enter sib2, iclass 26, count 0 2006.286.00:50:02.32#ibcon#flushed, iclass 26, count 0 2006.286.00:50:02.32#ibcon#about to write, iclass 26, count 0 2006.286.00:50:02.32#ibcon#wrote, iclass 26, count 0 2006.286.00:50:02.32#ibcon#about to read 3, iclass 26, count 0 2006.286.00:50:02.34#ibcon#read 3, iclass 26, count 0 2006.286.00:50:02.34#ibcon#about to read 4, iclass 26, count 0 2006.286.00:50:02.34#ibcon#read 4, iclass 26, count 0 2006.286.00:50:02.34#ibcon#about to read 5, iclass 26, count 0 2006.286.00:50:02.34#ibcon#read 5, iclass 26, count 0 2006.286.00:50:02.34#ibcon#about to read 6, iclass 26, count 0 2006.286.00:50:02.34#ibcon#read 6, iclass 26, count 0 2006.286.00:50:02.34#ibcon#end of sib2, iclass 26, count 0 2006.286.00:50:02.34#ibcon#*mode == 0, iclass 26, count 0 2006.286.00:50:02.34#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.00:50:02.34#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.00:50:02.34#ibcon#*before write, iclass 26, count 0 2006.286.00:50:02.34#ibcon#enter sib2, iclass 26, count 0 2006.286.00:50:02.34#ibcon#flushed, iclass 26, count 0 2006.286.00:50:02.34#ibcon#about to write, iclass 26, count 0 2006.286.00:50:02.34#ibcon#wrote, iclass 26, count 0 2006.286.00:50:02.34#ibcon#about to read 3, iclass 26, count 0 2006.286.00:50:02.38#ibcon#read 3, iclass 26, count 0 2006.286.00:50:02.38#ibcon#about to read 4, iclass 26, count 0 2006.286.00:50:02.38#ibcon#read 4, iclass 26, count 0 2006.286.00:50:02.38#ibcon#about to read 5, iclass 26, count 0 2006.286.00:50:02.38#ibcon#read 5, iclass 26, count 0 2006.286.00:50:02.38#ibcon#about to read 6, iclass 26, count 0 2006.286.00:50:02.38#ibcon#read 6, iclass 26, count 0 2006.286.00:50:02.38#ibcon#end of sib2, iclass 26, count 0 2006.286.00:50:02.38#ibcon#*after write, iclass 26, count 0 2006.286.00:50:02.38#ibcon#*before return 0, iclass 26, count 0 2006.286.00:50:02.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:50:02.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:50:02.38#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.00:50:02.38#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.00:50:02.38$vck44/va=8,3 2006.286.00:50:02.38#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.00:50:02.38#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.00:50:02.38#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:02.38#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.00:50:02.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.00:50:02.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.00:50:02.44#ibcon#enter wrdev, iclass 28, count 2 2006.286.00:50:02.44#ibcon#first serial, iclass 28, count 2 2006.286.00:50:02.44#ibcon#enter sib2, iclass 28, count 2 2006.286.00:50:02.44#ibcon#flushed, iclass 28, count 2 2006.286.00:50:02.44#ibcon#about to write, iclass 28, count 2 2006.286.00:50:02.44#ibcon#wrote, iclass 28, count 2 2006.286.00:50:02.44#ibcon#about to read 3, iclass 28, count 2 2006.286.00:50:02.46#ibcon#read 3, iclass 28, count 2 2006.286.00:50:02.46#ibcon#about to read 4, iclass 28, count 2 2006.286.00:50:02.46#ibcon#read 4, iclass 28, count 2 2006.286.00:50:02.46#ibcon#about to read 5, iclass 28, count 2 2006.286.00:50:02.46#ibcon#read 5, iclass 28, count 2 2006.286.00:50:02.46#ibcon#about to read 6, iclass 28, count 2 2006.286.00:50:02.46#ibcon#read 6, iclass 28, count 2 2006.286.00:50:02.46#ibcon#end of sib2, iclass 28, count 2 2006.286.00:50:02.46#ibcon#*mode == 0, iclass 28, count 2 2006.286.00:50:02.46#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.00:50:02.46#ibcon#[25=AT08-03\r\n] 2006.286.00:50:02.46#ibcon#*before write, iclass 28, count 2 2006.286.00:50:02.46#ibcon#enter sib2, iclass 28, count 2 2006.286.00:50:02.46#ibcon#flushed, iclass 28, count 2 2006.286.00:50:02.46#ibcon#about to write, iclass 28, count 2 2006.286.00:50:02.46#ibcon#wrote, iclass 28, count 2 2006.286.00:50:02.46#ibcon#about to read 3, iclass 28, count 2 2006.286.00:50:02.49#ibcon#read 3, iclass 28, count 2 2006.286.00:50:02.49#ibcon#about to read 4, iclass 28, count 2 2006.286.00:50:02.49#ibcon#read 4, iclass 28, count 2 2006.286.00:50:02.49#ibcon#about to read 5, iclass 28, count 2 2006.286.00:50:02.49#ibcon#read 5, iclass 28, count 2 2006.286.00:50:02.49#ibcon#about to read 6, iclass 28, count 2 2006.286.00:50:02.49#ibcon#read 6, iclass 28, count 2 2006.286.00:50:02.49#ibcon#end of sib2, iclass 28, count 2 2006.286.00:50:02.49#ibcon#*after write, iclass 28, count 2 2006.286.00:50:02.49#ibcon#*before return 0, iclass 28, count 2 2006.286.00:50:02.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.00:50:02.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.00:50:02.49#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.00:50:02.49#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:02.49#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.00:50:02.61#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.00:50:02.61#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.00:50:02.61#ibcon#enter wrdev, iclass 28, count 0 2006.286.00:50:02.61#ibcon#first serial, iclass 28, count 0 2006.286.00:50:02.61#ibcon#enter sib2, iclass 28, count 0 2006.286.00:50:02.61#ibcon#flushed, iclass 28, count 0 2006.286.00:50:02.61#ibcon#about to write, iclass 28, count 0 2006.286.00:50:02.61#ibcon#wrote, iclass 28, count 0 2006.286.00:50:02.61#ibcon#about to read 3, iclass 28, count 0 2006.286.00:50:02.63#ibcon#read 3, iclass 28, count 0 2006.286.00:50:02.63#ibcon#about to read 4, iclass 28, count 0 2006.286.00:50:02.63#ibcon#read 4, iclass 28, count 0 2006.286.00:50:02.63#ibcon#about to read 5, iclass 28, count 0 2006.286.00:50:02.63#ibcon#read 5, iclass 28, count 0 2006.286.00:50:02.63#ibcon#about to read 6, iclass 28, count 0 2006.286.00:50:02.63#ibcon#read 6, iclass 28, count 0 2006.286.00:50:02.63#ibcon#end of sib2, iclass 28, count 0 2006.286.00:50:02.63#ibcon#*mode == 0, iclass 28, count 0 2006.286.00:50:02.63#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.00:50:02.63#ibcon#[25=USB\r\n] 2006.286.00:50:02.63#ibcon#*before write, iclass 28, count 0 2006.286.00:50:02.63#ibcon#enter sib2, iclass 28, count 0 2006.286.00:50:02.63#ibcon#flushed, iclass 28, count 0 2006.286.00:50:02.63#ibcon#about to write, iclass 28, count 0 2006.286.00:50:02.63#ibcon#wrote, iclass 28, count 0 2006.286.00:50:02.63#ibcon#about to read 3, iclass 28, count 0 2006.286.00:50:02.66#ibcon#read 3, iclass 28, count 0 2006.286.00:50:02.66#ibcon#about to read 4, iclass 28, count 0 2006.286.00:50:02.66#ibcon#read 4, iclass 28, count 0 2006.286.00:50:02.66#ibcon#about to read 5, iclass 28, count 0 2006.286.00:50:02.66#ibcon#read 5, iclass 28, count 0 2006.286.00:50:02.66#ibcon#about to read 6, iclass 28, count 0 2006.286.00:50:02.66#ibcon#read 6, iclass 28, count 0 2006.286.00:50:02.66#ibcon#end of sib2, iclass 28, count 0 2006.286.00:50:02.66#ibcon#*after write, iclass 28, count 0 2006.286.00:50:02.66#ibcon#*before return 0, iclass 28, count 0 2006.286.00:50:02.66#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.00:50:02.66#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.00:50:02.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.00:50:02.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.00:50:02.66$vck44/vblo=1,629.99 2006.286.00:50:02.66#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.00:50:02.66#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.00:50:02.66#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:02.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:50:02.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:50:02.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:50:02.66#ibcon#enter wrdev, iclass 30, count 0 2006.286.00:50:02.66#ibcon#first serial, iclass 30, count 0 2006.286.00:50:02.66#ibcon#enter sib2, iclass 30, count 0 2006.286.00:50:02.66#ibcon#flushed, iclass 30, count 0 2006.286.00:50:02.66#ibcon#about to write, iclass 30, count 0 2006.286.00:50:02.66#ibcon#wrote, iclass 30, count 0 2006.286.00:50:02.66#ibcon#about to read 3, iclass 30, count 0 2006.286.00:50:02.68#ibcon#read 3, iclass 30, count 0 2006.286.00:50:02.68#ibcon#about to read 4, iclass 30, count 0 2006.286.00:50:02.68#ibcon#read 4, iclass 30, count 0 2006.286.00:50:02.68#ibcon#about to read 5, iclass 30, count 0 2006.286.00:50:02.68#ibcon#read 5, iclass 30, count 0 2006.286.00:50:02.68#ibcon#about to read 6, iclass 30, count 0 2006.286.00:50:02.68#ibcon#read 6, iclass 30, count 0 2006.286.00:50:02.68#ibcon#end of sib2, iclass 30, count 0 2006.286.00:50:02.68#ibcon#*mode == 0, iclass 30, count 0 2006.286.00:50:02.68#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.00:50:02.68#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.00:50:02.68#ibcon#*before write, iclass 30, count 0 2006.286.00:50:02.68#ibcon#enter sib2, iclass 30, count 0 2006.286.00:50:02.68#ibcon#flushed, iclass 30, count 0 2006.286.00:50:02.68#ibcon#about to write, iclass 30, count 0 2006.286.00:50:02.68#ibcon#wrote, iclass 30, count 0 2006.286.00:50:02.68#ibcon#about to read 3, iclass 30, count 0 2006.286.00:50:02.72#ibcon#read 3, iclass 30, count 0 2006.286.00:50:02.72#ibcon#about to read 4, iclass 30, count 0 2006.286.00:50:02.72#ibcon#read 4, iclass 30, count 0 2006.286.00:50:02.72#ibcon#about to read 5, iclass 30, count 0 2006.286.00:50:02.72#ibcon#read 5, iclass 30, count 0 2006.286.00:50:02.72#ibcon#about to read 6, iclass 30, count 0 2006.286.00:50:02.72#ibcon#read 6, iclass 30, count 0 2006.286.00:50:02.72#ibcon#end of sib2, iclass 30, count 0 2006.286.00:50:02.72#ibcon#*after write, iclass 30, count 0 2006.286.00:50:02.72#ibcon#*before return 0, iclass 30, count 0 2006.286.00:50:02.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:50:02.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:50:02.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.00:50:02.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.00:50:02.72$vck44/vb=1,4 2006.286.00:50:02.72#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.00:50:02.72#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.00:50:02.72#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:02.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.00:50:02.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.00:50:02.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.00:50:02.72#ibcon#enter wrdev, iclass 32, count 2 2006.286.00:50:02.72#ibcon#first serial, iclass 32, count 2 2006.286.00:50:02.72#ibcon#enter sib2, iclass 32, count 2 2006.286.00:50:02.72#ibcon#flushed, iclass 32, count 2 2006.286.00:50:02.72#ibcon#about to write, iclass 32, count 2 2006.286.00:50:02.72#ibcon#wrote, iclass 32, count 2 2006.286.00:50:02.72#ibcon#about to read 3, iclass 32, count 2 2006.286.00:50:02.74#ibcon#read 3, iclass 32, count 2 2006.286.00:50:02.74#ibcon#about to read 4, iclass 32, count 2 2006.286.00:50:02.74#ibcon#read 4, iclass 32, count 2 2006.286.00:50:02.74#ibcon#about to read 5, iclass 32, count 2 2006.286.00:50:02.74#ibcon#read 5, iclass 32, count 2 2006.286.00:50:02.74#ibcon#about to read 6, iclass 32, count 2 2006.286.00:50:02.74#ibcon#read 6, iclass 32, count 2 2006.286.00:50:02.74#ibcon#end of sib2, iclass 32, count 2 2006.286.00:50:02.74#ibcon#*mode == 0, iclass 32, count 2 2006.286.00:50:02.74#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.00:50:02.74#ibcon#[27=AT01-04\r\n] 2006.286.00:50:02.74#ibcon#*before write, iclass 32, count 2 2006.286.00:50:02.74#ibcon#enter sib2, iclass 32, count 2 2006.286.00:50:02.74#ibcon#flushed, iclass 32, count 2 2006.286.00:50:02.74#ibcon#about to write, iclass 32, count 2 2006.286.00:50:02.74#ibcon#wrote, iclass 32, count 2 2006.286.00:50:02.74#ibcon#about to read 3, iclass 32, count 2 2006.286.00:50:02.77#ibcon#read 3, iclass 32, count 2 2006.286.00:50:02.77#ibcon#about to read 4, iclass 32, count 2 2006.286.00:50:02.77#ibcon#read 4, iclass 32, count 2 2006.286.00:50:02.77#ibcon#about to read 5, iclass 32, count 2 2006.286.00:50:02.77#ibcon#read 5, iclass 32, count 2 2006.286.00:50:02.77#ibcon#about to read 6, iclass 32, count 2 2006.286.00:50:02.77#ibcon#read 6, iclass 32, count 2 2006.286.00:50:02.77#ibcon#end of sib2, iclass 32, count 2 2006.286.00:50:02.77#ibcon#*after write, iclass 32, count 2 2006.286.00:50:02.77#ibcon#*before return 0, iclass 32, count 2 2006.286.00:50:02.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.00:50:02.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.00:50:02.77#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.00:50:02.77#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:02.77#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.00:50:02.89#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.00:50:02.89#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.00:50:02.89#ibcon#enter wrdev, iclass 32, count 0 2006.286.00:50:02.89#ibcon#first serial, iclass 32, count 0 2006.286.00:50:02.89#ibcon#enter sib2, iclass 32, count 0 2006.286.00:50:02.89#ibcon#flushed, iclass 32, count 0 2006.286.00:50:02.89#ibcon#about to write, iclass 32, count 0 2006.286.00:50:02.89#ibcon#wrote, iclass 32, count 0 2006.286.00:50:02.89#ibcon#about to read 3, iclass 32, count 0 2006.286.00:50:02.91#ibcon#read 3, iclass 32, count 0 2006.286.00:50:02.91#ibcon#about to read 4, iclass 32, count 0 2006.286.00:50:02.91#ibcon#read 4, iclass 32, count 0 2006.286.00:50:02.91#ibcon#about to read 5, iclass 32, count 0 2006.286.00:50:02.91#ibcon#read 5, iclass 32, count 0 2006.286.00:50:02.91#ibcon#about to read 6, iclass 32, count 0 2006.286.00:50:02.91#ibcon#read 6, iclass 32, count 0 2006.286.00:50:02.91#ibcon#end of sib2, iclass 32, count 0 2006.286.00:50:02.91#ibcon#*mode == 0, iclass 32, count 0 2006.286.00:50:02.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.00:50:02.91#ibcon#[27=USB\r\n] 2006.286.00:50:02.91#ibcon#*before write, iclass 32, count 0 2006.286.00:50:02.91#ibcon#enter sib2, iclass 32, count 0 2006.286.00:50:02.91#ibcon#flushed, iclass 32, count 0 2006.286.00:50:02.91#ibcon#about to write, iclass 32, count 0 2006.286.00:50:02.91#ibcon#wrote, iclass 32, count 0 2006.286.00:50:02.91#ibcon#about to read 3, iclass 32, count 0 2006.286.00:50:02.94#ibcon#read 3, iclass 32, count 0 2006.286.00:50:02.94#ibcon#about to read 4, iclass 32, count 0 2006.286.00:50:02.94#ibcon#read 4, iclass 32, count 0 2006.286.00:50:02.94#ibcon#about to read 5, iclass 32, count 0 2006.286.00:50:02.94#ibcon#read 5, iclass 32, count 0 2006.286.00:50:02.94#ibcon#about to read 6, iclass 32, count 0 2006.286.00:50:02.94#ibcon#read 6, iclass 32, count 0 2006.286.00:50:02.94#ibcon#end of sib2, iclass 32, count 0 2006.286.00:50:02.94#ibcon#*after write, iclass 32, count 0 2006.286.00:50:02.94#ibcon#*before return 0, iclass 32, count 0 2006.286.00:50:02.94#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.00:50:02.94#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.00:50:02.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.00:50:02.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.00:50:02.94$vck44/vblo=2,634.99 2006.286.00:50:02.94#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.00:50:02.94#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.00:50:02.94#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:02.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:50:02.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:50:02.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:50:02.94#ibcon#enter wrdev, iclass 34, count 0 2006.286.00:50:02.94#ibcon#first serial, iclass 34, count 0 2006.286.00:50:02.94#ibcon#enter sib2, iclass 34, count 0 2006.286.00:50:02.94#ibcon#flushed, iclass 34, count 0 2006.286.00:50:02.94#ibcon#about to write, iclass 34, count 0 2006.286.00:50:02.94#ibcon#wrote, iclass 34, count 0 2006.286.00:50:02.94#ibcon#about to read 3, iclass 34, count 0 2006.286.00:50:02.96#ibcon#read 3, iclass 34, count 0 2006.286.00:50:02.96#ibcon#about to read 4, iclass 34, count 0 2006.286.00:50:02.96#ibcon#read 4, iclass 34, count 0 2006.286.00:50:02.96#ibcon#about to read 5, iclass 34, count 0 2006.286.00:50:02.96#ibcon#read 5, iclass 34, count 0 2006.286.00:50:02.96#ibcon#about to read 6, iclass 34, count 0 2006.286.00:50:02.96#ibcon#read 6, iclass 34, count 0 2006.286.00:50:02.96#ibcon#end of sib2, iclass 34, count 0 2006.286.00:50:02.96#ibcon#*mode == 0, iclass 34, count 0 2006.286.00:50:02.96#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.00:50:02.96#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.00:50:02.96#ibcon#*before write, iclass 34, count 0 2006.286.00:50:02.96#ibcon#enter sib2, iclass 34, count 0 2006.286.00:50:02.96#ibcon#flushed, iclass 34, count 0 2006.286.00:50:02.96#ibcon#about to write, iclass 34, count 0 2006.286.00:50:02.96#ibcon#wrote, iclass 34, count 0 2006.286.00:50:02.96#ibcon#about to read 3, iclass 34, count 0 2006.286.00:50:03.00#ibcon#read 3, iclass 34, count 0 2006.286.00:50:03.00#ibcon#about to read 4, iclass 34, count 0 2006.286.00:50:03.00#ibcon#read 4, iclass 34, count 0 2006.286.00:50:03.00#ibcon#about to read 5, iclass 34, count 0 2006.286.00:50:03.00#ibcon#read 5, iclass 34, count 0 2006.286.00:50:03.00#ibcon#about to read 6, iclass 34, count 0 2006.286.00:50:03.00#ibcon#read 6, iclass 34, count 0 2006.286.00:50:03.00#ibcon#end of sib2, iclass 34, count 0 2006.286.00:50:03.00#ibcon#*after write, iclass 34, count 0 2006.286.00:50:03.00#ibcon#*before return 0, iclass 34, count 0 2006.286.00:50:03.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:50:03.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.00:50:03.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.00:50:03.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.00:50:03.00$vck44/vb=2,5 2006.286.00:50:03.00#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.00:50:03.00#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.00:50:03.00#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:03.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:50:03.06#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:50:03.06#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:50:03.06#ibcon#enter wrdev, iclass 36, count 2 2006.286.00:50:03.06#ibcon#first serial, iclass 36, count 2 2006.286.00:50:03.06#ibcon#enter sib2, iclass 36, count 2 2006.286.00:50:03.06#ibcon#flushed, iclass 36, count 2 2006.286.00:50:03.06#ibcon#about to write, iclass 36, count 2 2006.286.00:50:03.06#ibcon#wrote, iclass 36, count 2 2006.286.00:50:03.06#ibcon#about to read 3, iclass 36, count 2 2006.286.00:50:03.08#ibcon#read 3, iclass 36, count 2 2006.286.00:50:03.08#ibcon#about to read 4, iclass 36, count 2 2006.286.00:50:03.08#ibcon#read 4, iclass 36, count 2 2006.286.00:50:03.08#ibcon#about to read 5, iclass 36, count 2 2006.286.00:50:03.08#ibcon#read 5, iclass 36, count 2 2006.286.00:50:03.08#ibcon#about to read 6, iclass 36, count 2 2006.286.00:50:03.08#ibcon#read 6, iclass 36, count 2 2006.286.00:50:03.08#ibcon#end of sib2, iclass 36, count 2 2006.286.00:50:03.08#ibcon#*mode == 0, iclass 36, count 2 2006.286.00:50:03.08#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.00:50:03.08#ibcon#[27=AT02-05\r\n] 2006.286.00:50:03.08#ibcon#*before write, iclass 36, count 2 2006.286.00:50:03.08#ibcon#enter sib2, iclass 36, count 2 2006.286.00:50:03.08#ibcon#flushed, iclass 36, count 2 2006.286.00:50:03.08#ibcon#about to write, iclass 36, count 2 2006.286.00:50:03.08#ibcon#wrote, iclass 36, count 2 2006.286.00:50:03.08#ibcon#about to read 3, iclass 36, count 2 2006.286.00:50:03.11#ibcon#read 3, iclass 36, count 2 2006.286.00:50:03.11#ibcon#about to read 4, iclass 36, count 2 2006.286.00:50:03.11#ibcon#read 4, iclass 36, count 2 2006.286.00:50:03.11#ibcon#about to read 5, iclass 36, count 2 2006.286.00:50:03.11#ibcon#read 5, iclass 36, count 2 2006.286.00:50:03.11#ibcon#about to read 6, iclass 36, count 2 2006.286.00:50:03.11#ibcon#read 6, iclass 36, count 2 2006.286.00:50:03.11#ibcon#end of sib2, iclass 36, count 2 2006.286.00:50:03.11#ibcon#*after write, iclass 36, count 2 2006.286.00:50:03.11#ibcon#*before return 0, iclass 36, count 2 2006.286.00:50:03.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:50:03.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.00:50:03.11#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.00:50:03.11#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:03.11#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:50:03.23#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:50:03.23#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:50:03.23#ibcon#enter wrdev, iclass 36, count 0 2006.286.00:50:03.23#ibcon#first serial, iclass 36, count 0 2006.286.00:50:03.23#ibcon#enter sib2, iclass 36, count 0 2006.286.00:50:03.23#ibcon#flushed, iclass 36, count 0 2006.286.00:50:03.23#ibcon#about to write, iclass 36, count 0 2006.286.00:50:03.23#ibcon#wrote, iclass 36, count 0 2006.286.00:50:03.23#ibcon#about to read 3, iclass 36, count 0 2006.286.00:50:03.25#ibcon#read 3, iclass 36, count 0 2006.286.00:50:03.25#ibcon#about to read 4, iclass 36, count 0 2006.286.00:50:03.25#ibcon#read 4, iclass 36, count 0 2006.286.00:50:03.25#ibcon#about to read 5, iclass 36, count 0 2006.286.00:50:03.25#ibcon#read 5, iclass 36, count 0 2006.286.00:50:03.25#ibcon#about to read 6, iclass 36, count 0 2006.286.00:50:03.25#ibcon#read 6, iclass 36, count 0 2006.286.00:50:03.25#ibcon#end of sib2, iclass 36, count 0 2006.286.00:50:03.25#ibcon#*mode == 0, iclass 36, count 0 2006.286.00:50:03.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.00:50:03.25#ibcon#[27=USB\r\n] 2006.286.00:50:03.25#ibcon#*before write, iclass 36, count 0 2006.286.00:50:03.25#ibcon#enter sib2, iclass 36, count 0 2006.286.00:50:03.25#ibcon#flushed, iclass 36, count 0 2006.286.00:50:03.25#ibcon#about to write, iclass 36, count 0 2006.286.00:50:03.25#ibcon#wrote, iclass 36, count 0 2006.286.00:50:03.25#ibcon#about to read 3, iclass 36, count 0 2006.286.00:50:03.28#ibcon#read 3, iclass 36, count 0 2006.286.00:50:03.28#ibcon#about to read 4, iclass 36, count 0 2006.286.00:50:03.28#ibcon#read 4, iclass 36, count 0 2006.286.00:50:03.28#ibcon#about to read 5, iclass 36, count 0 2006.286.00:50:03.28#ibcon#read 5, iclass 36, count 0 2006.286.00:50:03.28#ibcon#about to read 6, iclass 36, count 0 2006.286.00:50:03.28#ibcon#read 6, iclass 36, count 0 2006.286.00:50:03.28#ibcon#end of sib2, iclass 36, count 0 2006.286.00:50:03.28#ibcon#*after write, iclass 36, count 0 2006.286.00:50:03.28#ibcon#*before return 0, iclass 36, count 0 2006.286.00:50:03.28#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:50:03.28#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.00:50:03.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.00:50:03.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.00:50:03.28$vck44/vblo=3,649.99 2006.286.00:50:03.28#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.00:50:03.28#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.00:50:03.28#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:03.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:50:03.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:50:03.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:50:03.28#ibcon#enter wrdev, iclass 38, count 0 2006.286.00:50:03.28#ibcon#first serial, iclass 38, count 0 2006.286.00:50:03.28#ibcon#enter sib2, iclass 38, count 0 2006.286.00:50:03.28#ibcon#flushed, iclass 38, count 0 2006.286.00:50:03.28#ibcon#about to write, iclass 38, count 0 2006.286.00:50:03.28#ibcon#wrote, iclass 38, count 0 2006.286.00:50:03.28#ibcon#about to read 3, iclass 38, count 0 2006.286.00:50:03.30#ibcon#read 3, iclass 38, count 0 2006.286.00:50:03.30#ibcon#about to read 4, iclass 38, count 0 2006.286.00:50:03.30#ibcon#read 4, iclass 38, count 0 2006.286.00:50:03.30#ibcon#about to read 5, iclass 38, count 0 2006.286.00:50:03.30#ibcon#read 5, iclass 38, count 0 2006.286.00:50:03.30#ibcon#about to read 6, iclass 38, count 0 2006.286.00:50:03.30#ibcon#read 6, iclass 38, count 0 2006.286.00:50:03.30#ibcon#end of sib2, iclass 38, count 0 2006.286.00:50:03.30#ibcon#*mode == 0, iclass 38, count 0 2006.286.00:50:03.30#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.00:50:03.30#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.00:50:03.30#ibcon#*before write, iclass 38, count 0 2006.286.00:50:03.30#ibcon#enter sib2, iclass 38, count 0 2006.286.00:50:03.30#ibcon#flushed, iclass 38, count 0 2006.286.00:50:03.30#ibcon#about to write, iclass 38, count 0 2006.286.00:50:03.30#ibcon#wrote, iclass 38, count 0 2006.286.00:50:03.30#ibcon#about to read 3, iclass 38, count 0 2006.286.00:50:03.34#abcon#<5=/03 2.8 6.5 20.33 851016.3\r\n> 2006.286.00:50:03.34#ibcon#read 3, iclass 38, count 0 2006.286.00:50:03.34#ibcon#about to read 4, iclass 38, count 0 2006.286.00:50:03.34#ibcon#read 4, iclass 38, count 0 2006.286.00:50:03.34#ibcon#about to read 5, iclass 38, count 0 2006.286.00:50:03.34#ibcon#read 5, iclass 38, count 0 2006.286.00:50:03.34#ibcon#about to read 6, iclass 38, count 0 2006.286.00:50:03.34#ibcon#read 6, iclass 38, count 0 2006.286.00:50:03.34#ibcon#end of sib2, iclass 38, count 0 2006.286.00:50:03.34#ibcon#*after write, iclass 38, count 0 2006.286.00:50:03.34#ibcon#*before return 0, iclass 38, count 0 2006.286.00:50:03.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:50:03.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.00:50:03.34#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.00:50:03.34#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.00:50:03.34$vck44/vb=3,4 2006.286.00:50:03.34#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.00:50:03.34#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.00:50:03.34#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:03.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:50:03.36#abcon#{5=INTERFACE CLEAR} 2006.286.00:50:03.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:50:03.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:50:03.40#ibcon#enter wrdev, iclass 5, count 2 2006.286.00:50:03.40#ibcon#first serial, iclass 5, count 2 2006.286.00:50:03.40#ibcon#enter sib2, iclass 5, count 2 2006.286.00:50:03.40#ibcon#flushed, iclass 5, count 2 2006.286.00:50:03.40#ibcon#about to write, iclass 5, count 2 2006.286.00:50:03.40#ibcon#wrote, iclass 5, count 2 2006.286.00:50:03.40#ibcon#about to read 3, iclass 5, count 2 2006.286.00:50:03.42#ibcon#read 3, iclass 5, count 2 2006.286.00:50:03.42#ibcon#about to read 4, iclass 5, count 2 2006.286.00:50:03.42#ibcon#read 4, iclass 5, count 2 2006.286.00:50:03.42#ibcon#about to read 5, iclass 5, count 2 2006.286.00:50:03.42#ibcon#read 5, iclass 5, count 2 2006.286.00:50:03.42#ibcon#about to read 6, iclass 5, count 2 2006.286.00:50:03.42#ibcon#read 6, iclass 5, count 2 2006.286.00:50:03.42#ibcon#end of sib2, iclass 5, count 2 2006.286.00:50:03.42#ibcon#*mode == 0, iclass 5, count 2 2006.286.00:50:03.42#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.00:50:03.42#ibcon#[27=AT03-04\r\n] 2006.286.00:50:03.42#ibcon#*before write, iclass 5, count 2 2006.286.00:50:03.42#ibcon#enter sib2, iclass 5, count 2 2006.286.00:50:03.42#ibcon#flushed, iclass 5, count 2 2006.286.00:50:03.42#ibcon#about to write, iclass 5, count 2 2006.286.00:50:03.42#ibcon#wrote, iclass 5, count 2 2006.286.00:50:03.42#ibcon#about to read 3, iclass 5, count 2 2006.286.00:50:03.42#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:50:03.45#ibcon#read 3, iclass 5, count 2 2006.286.00:50:03.45#ibcon#about to read 4, iclass 5, count 2 2006.286.00:50:03.45#ibcon#read 4, iclass 5, count 2 2006.286.00:50:03.45#ibcon#about to read 5, iclass 5, count 2 2006.286.00:50:03.45#ibcon#read 5, iclass 5, count 2 2006.286.00:50:03.45#ibcon#about to read 6, iclass 5, count 2 2006.286.00:50:03.45#ibcon#read 6, iclass 5, count 2 2006.286.00:50:03.45#ibcon#end of sib2, iclass 5, count 2 2006.286.00:50:03.45#ibcon#*after write, iclass 5, count 2 2006.286.00:50:03.45#ibcon#*before return 0, iclass 5, count 2 2006.286.00:50:03.45#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:50:03.45#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:50:03.45#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.00:50:03.45#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:03.45#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:50:03.57#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:50:03.57#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:50:03.57#ibcon#enter wrdev, iclass 5, count 0 2006.286.00:50:03.57#ibcon#first serial, iclass 5, count 0 2006.286.00:50:03.57#ibcon#enter sib2, iclass 5, count 0 2006.286.00:50:03.57#ibcon#flushed, iclass 5, count 0 2006.286.00:50:03.57#ibcon#about to write, iclass 5, count 0 2006.286.00:50:03.57#ibcon#wrote, iclass 5, count 0 2006.286.00:50:03.57#ibcon#about to read 3, iclass 5, count 0 2006.286.00:50:03.59#ibcon#read 3, iclass 5, count 0 2006.286.00:50:03.59#ibcon#about to read 4, iclass 5, count 0 2006.286.00:50:03.59#ibcon#read 4, iclass 5, count 0 2006.286.00:50:03.59#ibcon#about to read 5, iclass 5, count 0 2006.286.00:50:03.59#ibcon#read 5, iclass 5, count 0 2006.286.00:50:03.59#ibcon#about to read 6, iclass 5, count 0 2006.286.00:50:03.59#ibcon#read 6, iclass 5, count 0 2006.286.00:50:03.59#ibcon#end of sib2, iclass 5, count 0 2006.286.00:50:03.59#ibcon#*mode == 0, iclass 5, count 0 2006.286.00:50:03.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.00:50:03.59#ibcon#[27=USB\r\n] 2006.286.00:50:03.59#ibcon#*before write, iclass 5, count 0 2006.286.00:50:03.59#ibcon#enter sib2, iclass 5, count 0 2006.286.00:50:03.59#ibcon#flushed, iclass 5, count 0 2006.286.00:50:03.59#ibcon#about to write, iclass 5, count 0 2006.286.00:50:03.59#ibcon#wrote, iclass 5, count 0 2006.286.00:50:03.59#ibcon#about to read 3, iclass 5, count 0 2006.286.00:50:03.62#ibcon#read 3, iclass 5, count 0 2006.286.00:50:03.62#ibcon#about to read 4, iclass 5, count 0 2006.286.00:50:03.62#ibcon#read 4, iclass 5, count 0 2006.286.00:50:03.62#ibcon#about to read 5, iclass 5, count 0 2006.286.00:50:03.62#ibcon#read 5, iclass 5, count 0 2006.286.00:50:03.62#ibcon#about to read 6, iclass 5, count 0 2006.286.00:50:03.62#ibcon#read 6, iclass 5, count 0 2006.286.00:50:03.62#ibcon#end of sib2, iclass 5, count 0 2006.286.00:50:03.62#ibcon#*after write, iclass 5, count 0 2006.286.00:50:03.62#ibcon#*before return 0, iclass 5, count 0 2006.286.00:50:03.62#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:50:03.62#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:50:03.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.00:50:03.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.00:50:03.62$vck44/vblo=4,679.99 2006.286.00:50:03.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.00:50:03.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.00:50:03.62#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:03.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:50:03.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:50:03.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:50:03.62#ibcon#enter wrdev, iclass 10, count 0 2006.286.00:50:03.62#ibcon#first serial, iclass 10, count 0 2006.286.00:50:03.62#ibcon#enter sib2, iclass 10, count 0 2006.286.00:50:03.62#ibcon#flushed, iclass 10, count 0 2006.286.00:50:03.62#ibcon#about to write, iclass 10, count 0 2006.286.00:50:03.62#ibcon#wrote, iclass 10, count 0 2006.286.00:50:03.62#ibcon#about to read 3, iclass 10, count 0 2006.286.00:50:03.64#ibcon#read 3, iclass 10, count 0 2006.286.00:50:03.64#ibcon#about to read 4, iclass 10, count 0 2006.286.00:50:03.64#ibcon#read 4, iclass 10, count 0 2006.286.00:50:03.64#ibcon#about to read 5, iclass 10, count 0 2006.286.00:50:03.64#ibcon#read 5, iclass 10, count 0 2006.286.00:50:03.64#ibcon#about to read 6, iclass 10, count 0 2006.286.00:50:03.64#ibcon#read 6, iclass 10, count 0 2006.286.00:50:03.64#ibcon#end of sib2, iclass 10, count 0 2006.286.00:50:03.64#ibcon#*mode == 0, iclass 10, count 0 2006.286.00:50:03.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.00:50:03.64#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.00:50:03.64#ibcon#*before write, iclass 10, count 0 2006.286.00:50:03.64#ibcon#enter sib2, iclass 10, count 0 2006.286.00:50:03.64#ibcon#flushed, iclass 10, count 0 2006.286.00:50:03.64#ibcon#about to write, iclass 10, count 0 2006.286.00:50:03.64#ibcon#wrote, iclass 10, count 0 2006.286.00:50:03.64#ibcon#about to read 3, iclass 10, count 0 2006.286.00:50:03.68#ibcon#read 3, iclass 10, count 0 2006.286.00:50:03.68#ibcon#about to read 4, iclass 10, count 0 2006.286.00:50:03.68#ibcon#read 4, iclass 10, count 0 2006.286.00:50:03.68#ibcon#about to read 5, iclass 10, count 0 2006.286.00:50:03.68#ibcon#read 5, iclass 10, count 0 2006.286.00:50:03.68#ibcon#about to read 6, iclass 10, count 0 2006.286.00:50:03.68#ibcon#read 6, iclass 10, count 0 2006.286.00:50:03.68#ibcon#end of sib2, iclass 10, count 0 2006.286.00:50:03.68#ibcon#*after write, iclass 10, count 0 2006.286.00:50:03.68#ibcon#*before return 0, iclass 10, count 0 2006.286.00:50:03.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:50:03.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.00:50:03.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.00:50:03.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.00:50:03.68$vck44/vb=4,5 2006.286.00:50:03.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.00:50:03.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.00:50:03.68#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:03.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:50:03.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:50:03.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:50:03.74#ibcon#enter wrdev, iclass 12, count 2 2006.286.00:50:03.74#ibcon#first serial, iclass 12, count 2 2006.286.00:50:03.74#ibcon#enter sib2, iclass 12, count 2 2006.286.00:50:03.74#ibcon#flushed, iclass 12, count 2 2006.286.00:50:03.74#ibcon#about to write, iclass 12, count 2 2006.286.00:50:03.74#ibcon#wrote, iclass 12, count 2 2006.286.00:50:03.74#ibcon#about to read 3, iclass 12, count 2 2006.286.00:50:03.76#ibcon#read 3, iclass 12, count 2 2006.286.00:50:03.76#ibcon#about to read 4, iclass 12, count 2 2006.286.00:50:03.76#ibcon#read 4, iclass 12, count 2 2006.286.00:50:03.76#ibcon#about to read 5, iclass 12, count 2 2006.286.00:50:03.76#ibcon#read 5, iclass 12, count 2 2006.286.00:50:03.76#ibcon#about to read 6, iclass 12, count 2 2006.286.00:50:03.76#ibcon#read 6, iclass 12, count 2 2006.286.00:50:03.76#ibcon#end of sib2, iclass 12, count 2 2006.286.00:50:03.76#ibcon#*mode == 0, iclass 12, count 2 2006.286.00:50:03.76#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.00:50:03.76#ibcon#[27=AT04-05\r\n] 2006.286.00:50:03.76#ibcon#*before write, iclass 12, count 2 2006.286.00:50:03.76#ibcon#enter sib2, iclass 12, count 2 2006.286.00:50:03.76#ibcon#flushed, iclass 12, count 2 2006.286.00:50:03.76#ibcon#about to write, iclass 12, count 2 2006.286.00:50:03.76#ibcon#wrote, iclass 12, count 2 2006.286.00:50:03.76#ibcon#about to read 3, iclass 12, count 2 2006.286.00:50:03.79#ibcon#read 3, iclass 12, count 2 2006.286.00:50:03.79#ibcon#about to read 4, iclass 12, count 2 2006.286.00:50:03.79#ibcon#read 4, iclass 12, count 2 2006.286.00:50:03.79#ibcon#about to read 5, iclass 12, count 2 2006.286.00:50:03.79#ibcon#read 5, iclass 12, count 2 2006.286.00:50:03.79#ibcon#about to read 6, iclass 12, count 2 2006.286.00:50:03.79#ibcon#read 6, iclass 12, count 2 2006.286.00:50:03.79#ibcon#end of sib2, iclass 12, count 2 2006.286.00:50:03.79#ibcon#*after write, iclass 12, count 2 2006.286.00:50:03.79#ibcon#*before return 0, iclass 12, count 2 2006.286.00:50:03.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:50:03.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.00:50:03.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.00:50:03.79#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:03.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:50:03.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:50:03.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:50:03.91#ibcon#enter wrdev, iclass 12, count 0 2006.286.00:50:03.91#ibcon#first serial, iclass 12, count 0 2006.286.00:50:03.91#ibcon#enter sib2, iclass 12, count 0 2006.286.00:50:03.91#ibcon#flushed, iclass 12, count 0 2006.286.00:50:03.91#ibcon#about to write, iclass 12, count 0 2006.286.00:50:03.91#ibcon#wrote, iclass 12, count 0 2006.286.00:50:03.91#ibcon#about to read 3, iclass 12, count 0 2006.286.00:50:03.93#ibcon#read 3, iclass 12, count 0 2006.286.00:50:03.93#ibcon#about to read 4, iclass 12, count 0 2006.286.00:50:03.93#ibcon#read 4, iclass 12, count 0 2006.286.00:50:03.93#ibcon#about to read 5, iclass 12, count 0 2006.286.00:50:03.93#ibcon#read 5, iclass 12, count 0 2006.286.00:50:03.93#ibcon#about to read 6, iclass 12, count 0 2006.286.00:50:03.93#ibcon#read 6, iclass 12, count 0 2006.286.00:50:03.93#ibcon#end of sib2, iclass 12, count 0 2006.286.00:50:03.93#ibcon#*mode == 0, iclass 12, count 0 2006.286.00:50:03.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.00:50:03.93#ibcon#[27=USB\r\n] 2006.286.00:50:03.93#ibcon#*before write, iclass 12, count 0 2006.286.00:50:03.93#ibcon#enter sib2, iclass 12, count 0 2006.286.00:50:03.93#ibcon#flushed, iclass 12, count 0 2006.286.00:50:03.93#ibcon#about to write, iclass 12, count 0 2006.286.00:50:03.93#ibcon#wrote, iclass 12, count 0 2006.286.00:50:03.93#ibcon#about to read 3, iclass 12, count 0 2006.286.00:50:03.96#ibcon#read 3, iclass 12, count 0 2006.286.00:50:03.96#ibcon#about to read 4, iclass 12, count 0 2006.286.00:50:03.96#ibcon#read 4, iclass 12, count 0 2006.286.00:50:03.96#ibcon#about to read 5, iclass 12, count 0 2006.286.00:50:03.96#ibcon#read 5, iclass 12, count 0 2006.286.00:50:03.96#ibcon#about to read 6, iclass 12, count 0 2006.286.00:50:03.96#ibcon#read 6, iclass 12, count 0 2006.286.00:50:03.96#ibcon#end of sib2, iclass 12, count 0 2006.286.00:50:03.96#ibcon#*after write, iclass 12, count 0 2006.286.00:50:03.96#ibcon#*before return 0, iclass 12, count 0 2006.286.00:50:03.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:50:03.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.00:50:03.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.00:50:03.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.00:50:03.96$vck44/vblo=5,709.99 2006.286.00:50:03.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.00:50:03.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.00:50:03.96#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:03.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:50:03.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:50:03.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:50:03.96#ibcon#enter wrdev, iclass 14, count 0 2006.286.00:50:03.96#ibcon#first serial, iclass 14, count 0 2006.286.00:50:03.96#ibcon#enter sib2, iclass 14, count 0 2006.286.00:50:03.96#ibcon#flushed, iclass 14, count 0 2006.286.00:50:03.96#ibcon#about to write, iclass 14, count 0 2006.286.00:50:03.96#ibcon#wrote, iclass 14, count 0 2006.286.00:50:03.96#ibcon#about to read 3, iclass 14, count 0 2006.286.00:50:03.98#ibcon#read 3, iclass 14, count 0 2006.286.00:50:03.98#ibcon#about to read 4, iclass 14, count 0 2006.286.00:50:03.98#ibcon#read 4, iclass 14, count 0 2006.286.00:50:03.98#ibcon#about to read 5, iclass 14, count 0 2006.286.00:50:03.98#ibcon#read 5, iclass 14, count 0 2006.286.00:50:03.98#ibcon#about to read 6, iclass 14, count 0 2006.286.00:50:03.98#ibcon#read 6, iclass 14, count 0 2006.286.00:50:03.98#ibcon#end of sib2, iclass 14, count 0 2006.286.00:50:03.98#ibcon#*mode == 0, iclass 14, count 0 2006.286.00:50:03.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.00:50:03.98#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.00:50:03.98#ibcon#*before write, iclass 14, count 0 2006.286.00:50:03.98#ibcon#enter sib2, iclass 14, count 0 2006.286.00:50:03.98#ibcon#flushed, iclass 14, count 0 2006.286.00:50:03.98#ibcon#about to write, iclass 14, count 0 2006.286.00:50:03.98#ibcon#wrote, iclass 14, count 0 2006.286.00:50:03.98#ibcon#about to read 3, iclass 14, count 0 2006.286.00:50:04.02#ibcon#read 3, iclass 14, count 0 2006.286.00:50:04.02#ibcon#about to read 4, iclass 14, count 0 2006.286.00:50:04.02#ibcon#read 4, iclass 14, count 0 2006.286.00:50:04.02#ibcon#about to read 5, iclass 14, count 0 2006.286.00:50:04.02#ibcon#read 5, iclass 14, count 0 2006.286.00:50:04.02#ibcon#about to read 6, iclass 14, count 0 2006.286.00:50:04.02#ibcon#read 6, iclass 14, count 0 2006.286.00:50:04.02#ibcon#end of sib2, iclass 14, count 0 2006.286.00:50:04.02#ibcon#*after write, iclass 14, count 0 2006.286.00:50:04.02#ibcon#*before return 0, iclass 14, count 0 2006.286.00:50:04.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:50:04.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.00:50:04.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.00:50:04.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.00:50:04.02$vck44/vb=5,4 2006.286.00:50:04.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.00:50:04.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.00:50:04.02#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:04.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:50:04.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:50:04.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:50:04.08#ibcon#enter wrdev, iclass 16, count 2 2006.286.00:50:04.08#ibcon#first serial, iclass 16, count 2 2006.286.00:50:04.08#ibcon#enter sib2, iclass 16, count 2 2006.286.00:50:04.08#ibcon#flushed, iclass 16, count 2 2006.286.00:50:04.08#ibcon#about to write, iclass 16, count 2 2006.286.00:50:04.08#ibcon#wrote, iclass 16, count 2 2006.286.00:50:04.08#ibcon#about to read 3, iclass 16, count 2 2006.286.00:50:04.10#ibcon#read 3, iclass 16, count 2 2006.286.00:50:04.10#ibcon#about to read 4, iclass 16, count 2 2006.286.00:50:04.10#ibcon#read 4, iclass 16, count 2 2006.286.00:50:04.10#ibcon#about to read 5, iclass 16, count 2 2006.286.00:50:04.10#ibcon#read 5, iclass 16, count 2 2006.286.00:50:04.10#ibcon#about to read 6, iclass 16, count 2 2006.286.00:50:04.10#ibcon#read 6, iclass 16, count 2 2006.286.00:50:04.10#ibcon#end of sib2, iclass 16, count 2 2006.286.00:50:04.10#ibcon#*mode == 0, iclass 16, count 2 2006.286.00:50:04.10#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.00:50:04.10#ibcon#[27=AT05-04\r\n] 2006.286.00:50:04.10#ibcon#*before write, iclass 16, count 2 2006.286.00:50:04.10#ibcon#enter sib2, iclass 16, count 2 2006.286.00:50:04.10#ibcon#flushed, iclass 16, count 2 2006.286.00:50:04.10#ibcon#about to write, iclass 16, count 2 2006.286.00:50:04.10#ibcon#wrote, iclass 16, count 2 2006.286.00:50:04.10#ibcon#about to read 3, iclass 16, count 2 2006.286.00:50:04.13#ibcon#read 3, iclass 16, count 2 2006.286.00:50:04.13#ibcon#about to read 4, iclass 16, count 2 2006.286.00:50:04.13#ibcon#read 4, iclass 16, count 2 2006.286.00:50:04.13#ibcon#about to read 5, iclass 16, count 2 2006.286.00:50:04.13#ibcon#read 5, iclass 16, count 2 2006.286.00:50:04.13#ibcon#about to read 6, iclass 16, count 2 2006.286.00:50:04.13#ibcon#read 6, iclass 16, count 2 2006.286.00:50:04.13#ibcon#end of sib2, iclass 16, count 2 2006.286.00:50:04.13#ibcon#*after write, iclass 16, count 2 2006.286.00:50:04.13#ibcon#*before return 0, iclass 16, count 2 2006.286.00:50:04.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:50:04.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.00:50:04.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.00:50:04.13#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:04.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:50:04.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:50:04.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:50:04.25#ibcon#enter wrdev, iclass 16, count 0 2006.286.00:50:04.25#ibcon#first serial, iclass 16, count 0 2006.286.00:50:04.25#ibcon#enter sib2, iclass 16, count 0 2006.286.00:50:04.25#ibcon#flushed, iclass 16, count 0 2006.286.00:50:04.25#ibcon#about to write, iclass 16, count 0 2006.286.00:50:04.25#ibcon#wrote, iclass 16, count 0 2006.286.00:50:04.25#ibcon#about to read 3, iclass 16, count 0 2006.286.00:50:04.27#ibcon#read 3, iclass 16, count 0 2006.286.00:50:04.27#ibcon#about to read 4, iclass 16, count 0 2006.286.00:50:04.27#ibcon#read 4, iclass 16, count 0 2006.286.00:50:04.27#ibcon#about to read 5, iclass 16, count 0 2006.286.00:50:04.27#ibcon#read 5, iclass 16, count 0 2006.286.00:50:04.27#ibcon#about to read 6, iclass 16, count 0 2006.286.00:50:04.27#ibcon#read 6, iclass 16, count 0 2006.286.00:50:04.27#ibcon#end of sib2, iclass 16, count 0 2006.286.00:50:04.27#ibcon#*mode == 0, iclass 16, count 0 2006.286.00:50:04.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.00:50:04.27#ibcon#[27=USB\r\n] 2006.286.00:50:04.27#ibcon#*before write, iclass 16, count 0 2006.286.00:50:04.27#ibcon#enter sib2, iclass 16, count 0 2006.286.00:50:04.27#ibcon#flushed, iclass 16, count 0 2006.286.00:50:04.27#ibcon#about to write, iclass 16, count 0 2006.286.00:50:04.27#ibcon#wrote, iclass 16, count 0 2006.286.00:50:04.27#ibcon#about to read 3, iclass 16, count 0 2006.286.00:50:04.30#ibcon#read 3, iclass 16, count 0 2006.286.00:50:04.30#ibcon#about to read 4, iclass 16, count 0 2006.286.00:50:04.30#ibcon#read 4, iclass 16, count 0 2006.286.00:50:04.30#ibcon#about to read 5, iclass 16, count 0 2006.286.00:50:04.30#ibcon#read 5, iclass 16, count 0 2006.286.00:50:04.30#ibcon#about to read 6, iclass 16, count 0 2006.286.00:50:04.30#ibcon#read 6, iclass 16, count 0 2006.286.00:50:04.30#ibcon#end of sib2, iclass 16, count 0 2006.286.00:50:04.30#ibcon#*after write, iclass 16, count 0 2006.286.00:50:04.30#ibcon#*before return 0, iclass 16, count 0 2006.286.00:50:04.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:50:04.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.00:50:04.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.00:50:04.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.00:50:04.30$vck44/vblo=6,719.99 2006.286.00:50:04.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.00:50:04.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.00:50:04.30#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:04.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:50:04.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:50:04.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:50:04.30#ibcon#enter wrdev, iclass 18, count 0 2006.286.00:50:04.30#ibcon#first serial, iclass 18, count 0 2006.286.00:50:04.30#ibcon#enter sib2, iclass 18, count 0 2006.286.00:50:04.30#ibcon#flushed, iclass 18, count 0 2006.286.00:50:04.30#ibcon#about to write, iclass 18, count 0 2006.286.00:50:04.30#ibcon#wrote, iclass 18, count 0 2006.286.00:50:04.30#ibcon#about to read 3, iclass 18, count 0 2006.286.00:50:04.32#ibcon#read 3, iclass 18, count 0 2006.286.00:50:04.32#ibcon#about to read 4, iclass 18, count 0 2006.286.00:50:04.32#ibcon#read 4, iclass 18, count 0 2006.286.00:50:04.32#ibcon#about to read 5, iclass 18, count 0 2006.286.00:50:04.32#ibcon#read 5, iclass 18, count 0 2006.286.00:50:04.32#ibcon#about to read 6, iclass 18, count 0 2006.286.00:50:04.32#ibcon#read 6, iclass 18, count 0 2006.286.00:50:04.32#ibcon#end of sib2, iclass 18, count 0 2006.286.00:50:04.32#ibcon#*mode == 0, iclass 18, count 0 2006.286.00:50:04.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.00:50:04.32#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.00:50:04.32#ibcon#*before write, iclass 18, count 0 2006.286.00:50:04.32#ibcon#enter sib2, iclass 18, count 0 2006.286.00:50:04.32#ibcon#flushed, iclass 18, count 0 2006.286.00:50:04.32#ibcon#about to write, iclass 18, count 0 2006.286.00:50:04.32#ibcon#wrote, iclass 18, count 0 2006.286.00:50:04.32#ibcon#about to read 3, iclass 18, count 0 2006.286.00:50:04.36#ibcon#read 3, iclass 18, count 0 2006.286.00:50:04.36#ibcon#about to read 4, iclass 18, count 0 2006.286.00:50:04.36#ibcon#read 4, iclass 18, count 0 2006.286.00:50:04.36#ibcon#about to read 5, iclass 18, count 0 2006.286.00:50:04.36#ibcon#read 5, iclass 18, count 0 2006.286.00:50:04.36#ibcon#about to read 6, iclass 18, count 0 2006.286.00:50:04.36#ibcon#read 6, iclass 18, count 0 2006.286.00:50:04.36#ibcon#end of sib2, iclass 18, count 0 2006.286.00:50:04.36#ibcon#*after write, iclass 18, count 0 2006.286.00:50:04.36#ibcon#*before return 0, iclass 18, count 0 2006.286.00:50:04.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:50:04.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.00:50:04.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.00:50:04.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.00:50:04.36$vck44/vb=6,3 2006.286.00:50:04.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.00:50:04.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.00:50:04.36#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:04.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:50:04.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:50:04.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:50:04.42#ibcon#enter wrdev, iclass 20, count 2 2006.286.00:50:04.42#ibcon#first serial, iclass 20, count 2 2006.286.00:50:04.42#ibcon#enter sib2, iclass 20, count 2 2006.286.00:50:04.42#ibcon#flushed, iclass 20, count 2 2006.286.00:50:04.42#ibcon#about to write, iclass 20, count 2 2006.286.00:50:04.42#ibcon#wrote, iclass 20, count 2 2006.286.00:50:04.42#ibcon#about to read 3, iclass 20, count 2 2006.286.00:50:04.44#ibcon#read 3, iclass 20, count 2 2006.286.00:50:04.44#ibcon#about to read 4, iclass 20, count 2 2006.286.00:50:04.44#ibcon#read 4, iclass 20, count 2 2006.286.00:50:04.44#ibcon#about to read 5, iclass 20, count 2 2006.286.00:50:04.44#ibcon#read 5, iclass 20, count 2 2006.286.00:50:04.44#ibcon#about to read 6, iclass 20, count 2 2006.286.00:50:04.44#ibcon#read 6, iclass 20, count 2 2006.286.00:50:04.44#ibcon#end of sib2, iclass 20, count 2 2006.286.00:50:04.44#ibcon#*mode == 0, iclass 20, count 2 2006.286.00:50:04.44#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.00:50:04.44#ibcon#[27=AT06-03\r\n] 2006.286.00:50:04.44#ibcon#*before write, iclass 20, count 2 2006.286.00:50:04.44#ibcon#enter sib2, iclass 20, count 2 2006.286.00:50:04.44#ibcon#flushed, iclass 20, count 2 2006.286.00:50:04.44#ibcon#about to write, iclass 20, count 2 2006.286.00:50:04.44#ibcon#wrote, iclass 20, count 2 2006.286.00:50:04.44#ibcon#about to read 3, iclass 20, count 2 2006.286.00:50:04.47#ibcon#read 3, iclass 20, count 2 2006.286.00:50:04.47#ibcon#about to read 4, iclass 20, count 2 2006.286.00:50:04.47#ibcon#read 4, iclass 20, count 2 2006.286.00:50:04.47#ibcon#about to read 5, iclass 20, count 2 2006.286.00:50:04.47#ibcon#read 5, iclass 20, count 2 2006.286.00:50:04.47#ibcon#about to read 6, iclass 20, count 2 2006.286.00:50:04.47#ibcon#read 6, iclass 20, count 2 2006.286.00:50:04.47#ibcon#end of sib2, iclass 20, count 2 2006.286.00:50:04.47#ibcon#*after write, iclass 20, count 2 2006.286.00:50:04.47#ibcon#*before return 0, iclass 20, count 2 2006.286.00:50:04.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:50:04.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.00:50:04.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.00:50:04.47#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:04.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:50:04.59#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:50:04.59#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:50:04.59#ibcon#enter wrdev, iclass 20, count 0 2006.286.00:50:04.59#ibcon#first serial, iclass 20, count 0 2006.286.00:50:04.59#ibcon#enter sib2, iclass 20, count 0 2006.286.00:50:04.59#ibcon#flushed, iclass 20, count 0 2006.286.00:50:04.59#ibcon#about to write, iclass 20, count 0 2006.286.00:50:04.59#ibcon#wrote, iclass 20, count 0 2006.286.00:50:04.59#ibcon#about to read 3, iclass 20, count 0 2006.286.00:50:04.61#ibcon#read 3, iclass 20, count 0 2006.286.00:50:04.61#ibcon#about to read 4, iclass 20, count 0 2006.286.00:50:04.61#ibcon#read 4, iclass 20, count 0 2006.286.00:50:04.61#ibcon#about to read 5, iclass 20, count 0 2006.286.00:50:04.61#ibcon#read 5, iclass 20, count 0 2006.286.00:50:04.61#ibcon#about to read 6, iclass 20, count 0 2006.286.00:50:04.61#ibcon#read 6, iclass 20, count 0 2006.286.00:50:04.61#ibcon#end of sib2, iclass 20, count 0 2006.286.00:50:04.61#ibcon#*mode == 0, iclass 20, count 0 2006.286.00:50:04.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.00:50:04.61#ibcon#[27=USB\r\n] 2006.286.00:50:04.61#ibcon#*before write, iclass 20, count 0 2006.286.00:50:04.61#ibcon#enter sib2, iclass 20, count 0 2006.286.00:50:04.61#ibcon#flushed, iclass 20, count 0 2006.286.00:50:04.61#ibcon#about to write, iclass 20, count 0 2006.286.00:50:04.61#ibcon#wrote, iclass 20, count 0 2006.286.00:50:04.61#ibcon#about to read 3, iclass 20, count 0 2006.286.00:50:04.64#ibcon#read 3, iclass 20, count 0 2006.286.00:50:04.64#ibcon#about to read 4, iclass 20, count 0 2006.286.00:50:04.64#ibcon#read 4, iclass 20, count 0 2006.286.00:50:04.64#ibcon#about to read 5, iclass 20, count 0 2006.286.00:50:04.64#ibcon#read 5, iclass 20, count 0 2006.286.00:50:04.64#ibcon#about to read 6, iclass 20, count 0 2006.286.00:50:04.64#ibcon#read 6, iclass 20, count 0 2006.286.00:50:04.64#ibcon#end of sib2, iclass 20, count 0 2006.286.00:50:04.64#ibcon#*after write, iclass 20, count 0 2006.286.00:50:04.64#ibcon#*before return 0, iclass 20, count 0 2006.286.00:50:04.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:50:04.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.00:50:04.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.00:50:04.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.00:50:04.64$vck44/vblo=7,734.99 2006.286.00:50:04.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.00:50:04.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.00:50:04.64#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:04.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:50:04.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:50:04.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:50:04.64#ibcon#enter wrdev, iclass 22, count 0 2006.286.00:50:04.64#ibcon#first serial, iclass 22, count 0 2006.286.00:50:04.64#ibcon#enter sib2, iclass 22, count 0 2006.286.00:50:04.64#ibcon#flushed, iclass 22, count 0 2006.286.00:50:04.64#ibcon#about to write, iclass 22, count 0 2006.286.00:50:04.64#ibcon#wrote, iclass 22, count 0 2006.286.00:50:04.64#ibcon#about to read 3, iclass 22, count 0 2006.286.00:50:04.66#ibcon#read 3, iclass 22, count 0 2006.286.00:50:04.66#ibcon#about to read 4, iclass 22, count 0 2006.286.00:50:04.66#ibcon#read 4, iclass 22, count 0 2006.286.00:50:04.66#ibcon#about to read 5, iclass 22, count 0 2006.286.00:50:04.66#ibcon#read 5, iclass 22, count 0 2006.286.00:50:04.66#ibcon#about to read 6, iclass 22, count 0 2006.286.00:50:04.66#ibcon#read 6, iclass 22, count 0 2006.286.00:50:04.66#ibcon#end of sib2, iclass 22, count 0 2006.286.00:50:04.66#ibcon#*mode == 0, iclass 22, count 0 2006.286.00:50:04.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.00:50:04.66#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.00:50:04.66#ibcon#*before write, iclass 22, count 0 2006.286.00:50:04.66#ibcon#enter sib2, iclass 22, count 0 2006.286.00:50:04.66#ibcon#flushed, iclass 22, count 0 2006.286.00:50:04.66#ibcon#about to write, iclass 22, count 0 2006.286.00:50:04.66#ibcon#wrote, iclass 22, count 0 2006.286.00:50:04.66#ibcon#about to read 3, iclass 22, count 0 2006.286.00:50:04.70#ibcon#read 3, iclass 22, count 0 2006.286.00:50:04.70#ibcon#about to read 4, iclass 22, count 0 2006.286.00:50:04.70#ibcon#read 4, iclass 22, count 0 2006.286.00:50:04.70#ibcon#about to read 5, iclass 22, count 0 2006.286.00:50:04.70#ibcon#read 5, iclass 22, count 0 2006.286.00:50:04.70#ibcon#about to read 6, iclass 22, count 0 2006.286.00:50:04.70#ibcon#read 6, iclass 22, count 0 2006.286.00:50:04.70#ibcon#end of sib2, iclass 22, count 0 2006.286.00:50:04.70#ibcon#*after write, iclass 22, count 0 2006.286.00:50:04.70#ibcon#*before return 0, iclass 22, count 0 2006.286.00:50:04.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:50:04.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.00:50:04.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.00:50:04.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.00:50:04.70$vck44/vb=7,4 2006.286.00:50:04.70#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.00:50:04.70#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.00:50:04.70#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:04.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:50:04.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:50:04.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:50:04.76#ibcon#enter wrdev, iclass 24, count 2 2006.286.00:50:04.76#ibcon#first serial, iclass 24, count 2 2006.286.00:50:04.76#ibcon#enter sib2, iclass 24, count 2 2006.286.00:50:04.76#ibcon#flushed, iclass 24, count 2 2006.286.00:50:04.76#ibcon#about to write, iclass 24, count 2 2006.286.00:50:04.76#ibcon#wrote, iclass 24, count 2 2006.286.00:50:04.76#ibcon#about to read 3, iclass 24, count 2 2006.286.00:50:04.78#ibcon#read 3, iclass 24, count 2 2006.286.00:50:04.78#ibcon#about to read 4, iclass 24, count 2 2006.286.00:50:04.78#ibcon#read 4, iclass 24, count 2 2006.286.00:50:04.78#ibcon#about to read 5, iclass 24, count 2 2006.286.00:50:04.78#ibcon#read 5, iclass 24, count 2 2006.286.00:50:04.78#ibcon#about to read 6, iclass 24, count 2 2006.286.00:50:04.78#ibcon#read 6, iclass 24, count 2 2006.286.00:50:04.78#ibcon#end of sib2, iclass 24, count 2 2006.286.00:50:04.78#ibcon#*mode == 0, iclass 24, count 2 2006.286.00:50:04.78#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.00:50:04.78#ibcon#[27=AT07-04\r\n] 2006.286.00:50:04.78#ibcon#*before write, iclass 24, count 2 2006.286.00:50:04.78#ibcon#enter sib2, iclass 24, count 2 2006.286.00:50:04.78#ibcon#flushed, iclass 24, count 2 2006.286.00:50:04.78#ibcon#about to write, iclass 24, count 2 2006.286.00:50:04.78#ibcon#wrote, iclass 24, count 2 2006.286.00:50:04.78#ibcon#about to read 3, iclass 24, count 2 2006.286.00:50:04.81#ibcon#read 3, iclass 24, count 2 2006.286.00:50:04.81#ibcon#about to read 4, iclass 24, count 2 2006.286.00:50:04.81#ibcon#read 4, iclass 24, count 2 2006.286.00:50:04.81#ibcon#about to read 5, iclass 24, count 2 2006.286.00:50:04.81#ibcon#read 5, iclass 24, count 2 2006.286.00:50:04.81#ibcon#about to read 6, iclass 24, count 2 2006.286.00:50:04.81#ibcon#read 6, iclass 24, count 2 2006.286.00:50:04.81#ibcon#end of sib2, iclass 24, count 2 2006.286.00:50:04.81#ibcon#*after write, iclass 24, count 2 2006.286.00:50:04.81#ibcon#*before return 0, iclass 24, count 2 2006.286.00:50:04.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:50:04.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.00:50:04.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.00:50:04.81#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:04.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:50:04.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:50:04.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:50:04.93#ibcon#enter wrdev, iclass 24, count 0 2006.286.00:50:04.93#ibcon#first serial, iclass 24, count 0 2006.286.00:50:04.93#ibcon#enter sib2, iclass 24, count 0 2006.286.00:50:04.93#ibcon#flushed, iclass 24, count 0 2006.286.00:50:04.93#ibcon#about to write, iclass 24, count 0 2006.286.00:50:04.93#ibcon#wrote, iclass 24, count 0 2006.286.00:50:04.93#ibcon#about to read 3, iclass 24, count 0 2006.286.00:50:04.95#ibcon#read 3, iclass 24, count 0 2006.286.00:50:04.95#ibcon#about to read 4, iclass 24, count 0 2006.286.00:50:04.95#ibcon#read 4, iclass 24, count 0 2006.286.00:50:04.95#ibcon#about to read 5, iclass 24, count 0 2006.286.00:50:04.95#ibcon#read 5, iclass 24, count 0 2006.286.00:50:04.95#ibcon#about to read 6, iclass 24, count 0 2006.286.00:50:04.95#ibcon#read 6, iclass 24, count 0 2006.286.00:50:04.95#ibcon#end of sib2, iclass 24, count 0 2006.286.00:50:04.95#ibcon#*mode == 0, iclass 24, count 0 2006.286.00:50:04.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.00:50:04.95#ibcon#[27=USB\r\n] 2006.286.00:50:04.95#ibcon#*before write, iclass 24, count 0 2006.286.00:50:04.95#ibcon#enter sib2, iclass 24, count 0 2006.286.00:50:04.95#ibcon#flushed, iclass 24, count 0 2006.286.00:50:04.95#ibcon#about to write, iclass 24, count 0 2006.286.00:50:04.95#ibcon#wrote, iclass 24, count 0 2006.286.00:50:04.95#ibcon#about to read 3, iclass 24, count 0 2006.286.00:50:04.98#ibcon#read 3, iclass 24, count 0 2006.286.00:50:04.98#ibcon#about to read 4, iclass 24, count 0 2006.286.00:50:04.98#ibcon#read 4, iclass 24, count 0 2006.286.00:50:04.98#ibcon#about to read 5, iclass 24, count 0 2006.286.00:50:04.98#ibcon#read 5, iclass 24, count 0 2006.286.00:50:04.98#ibcon#about to read 6, iclass 24, count 0 2006.286.00:50:04.98#ibcon#read 6, iclass 24, count 0 2006.286.00:50:04.98#ibcon#end of sib2, iclass 24, count 0 2006.286.00:50:04.98#ibcon#*after write, iclass 24, count 0 2006.286.00:50:04.98#ibcon#*before return 0, iclass 24, count 0 2006.286.00:50:04.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:50:04.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.00:50:04.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.00:50:04.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.00:50:04.98$vck44/vblo=8,744.99 2006.286.00:50:04.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.00:50:04.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.00:50:04.98#ibcon#ireg 17 cls_cnt 0 2006.286.00:50:04.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:50:04.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:50:04.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:50:04.98#ibcon#enter wrdev, iclass 26, count 0 2006.286.00:50:04.98#ibcon#first serial, iclass 26, count 0 2006.286.00:50:04.98#ibcon#enter sib2, iclass 26, count 0 2006.286.00:50:04.98#ibcon#flushed, iclass 26, count 0 2006.286.00:50:04.98#ibcon#about to write, iclass 26, count 0 2006.286.00:50:04.98#ibcon#wrote, iclass 26, count 0 2006.286.00:50:04.98#ibcon#about to read 3, iclass 26, count 0 2006.286.00:50:05.00#ibcon#read 3, iclass 26, count 0 2006.286.00:50:05.00#ibcon#about to read 4, iclass 26, count 0 2006.286.00:50:05.00#ibcon#read 4, iclass 26, count 0 2006.286.00:50:05.00#ibcon#about to read 5, iclass 26, count 0 2006.286.00:50:05.00#ibcon#read 5, iclass 26, count 0 2006.286.00:50:05.00#ibcon#about to read 6, iclass 26, count 0 2006.286.00:50:05.00#ibcon#read 6, iclass 26, count 0 2006.286.00:50:05.00#ibcon#end of sib2, iclass 26, count 0 2006.286.00:50:05.00#ibcon#*mode == 0, iclass 26, count 0 2006.286.00:50:05.00#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.00:50:05.00#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.00:50:05.00#ibcon#*before write, iclass 26, count 0 2006.286.00:50:05.00#ibcon#enter sib2, iclass 26, count 0 2006.286.00:50:05.00#ibcon#flushed, iclass 26, count 0 2006.286.00:50:05.00#ibcon#about to write, iclass 26, count 0 2006.286.00:50:05.00#ibcon#wrote, iclass 26, count 0 2006.286.00:50:05.00#ibcon#about to read 3, iclass 26, count 0 2006.286.00:50:05.04#ibcon#read 3, iclass 26, count 0 2006.286.00:50:05.04#ibcon#about to read 4, iclass 26, count 0 2006.286.00:50:05.04#ibcon#read 4, iclass 26, count 0 2006.286.00:50:05.04#ibcon#about to read 5, iclass 26, count 0 2006.286.00:50:05.04#ibcon#read 5, iclass 26, count 0 2006.286.00:50:05.04#ibcon#about to read 6, iclass 26, count 0 2006.286.00:50:05.04#ibcon#read 6, iclass 26, count 0 2006.286.00:50:05.04#ibcon#end of sib2, iclass 26, count 0 2006.286.00:50:05.04#ibcon#*after write, iclass 26, count 0 2006.286.00:50:05.04#ibcon#*before return 0, iclass 26, count 0 2006.286.00:50:05.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:50:05.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.00:50:05.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.00:50:05.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.00:50:05.04$vck44/vb=8,4 2006.286.00:50:05.04#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.00:50:05.04#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.00:50:05.04#ibcon#ireg 11 cls_cnt 2 2006.286.00:50:05.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.00:50:05.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.00:50:05.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.00:50:05.10#ibcon#enter wrdev, iclass 28, count 2 2006.286.00:50:05.10#ibcon#first serial, iclass 28, count 2 2006.286.00:50:05.10#ibcon#enter sib2, iclass 28, count 2 2006.286.00:50:05.10#ibcon#flushed, iclass 28, count 2 2006.286.00:50:05.10#ibcon#about to write, iclass 28, count 2 2006.286.00:50:05.10#ibcon#wrote, iclass 28, count 2 2006.286.00:50:05.10#ibcon#about to read 3, iclass 28, count 2 2006.286.00:50:05.12#ibcon#read 3, iclass 28, count 2 2006.286.00:50:05.12#ibcon#about to read 4, iclass 28, count 2 2006.286.00:50:05.12#ibcon#read 4, iclass 28, count 2 2006.286.00:50:05.12#ibcon#about to read 5, iclass 28, count 2 2006.286.00:50:05.12#ibcon#read 5, iclass 28, count 2 2006.286.00:50:05.12#ibcon#about to read 6, iclass 28, count 2 2006.286.00:50:05.12#ibcon#read 6, iclass 28, count 2 2006.286.00:50:05.12#ibcon#end of sib2, iclass 28, count 2 2006.286.00:50:05.12#ibcon#*mode == 0, iclass 28, count 2 2006.286.00:50:05.12#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.00:50:05.12#ibcon#[27=AT08-04\r\n] 2006.286.00:50:05.12#ibcon#*before write, iclass 28, count 2 2006.286.00:50:05.12#ibcon#enter sib2, iclass 28, count 2 2006.286.00:50:05.12#ibcon#flushed, iclass 28, count 2 2006.286.00:50:05.12#ibcon#about to write, iclass 28, count 2 2006.286.00:50:05.12#ibcon#wrote, iclass 28, count 2 2006.286.00:50:05.12#ibcon#about to read 3, iclass 28, count 2 2006.286.00:50:05.15#ibcon#read 3, iclass 28, count 2 2006.286.00:50:05.15#ibcon#about to read 4, iclass 28, count 2 2006.286.00:50:05.15#ibcon#read 4, iclass 28, count 2 2006.286.00:50:05.15#ibcon#about to read 5, iclass 28, count 2 2006.286.00:50:05.15#ibcon#read 5, iclass 28, count 2 2006.286.00:50:05.15#ibcon#about to read 6, iclass 28, count 2 2006.286.00:50:05.15#ibcon#read 6, iclass 28, count 2 2006.286.00:50:05.15#ibcon#end of sib2, iclass 28, count 2 2006.286.00:50:05.15#ibcon#*after write, iclass 28, count 2 2006.286.00:50:05.15#ibcon#*before return 0, iclass 28, count 2 2006.286.00:50:05.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.00:50:05.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.00:50:05.15#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.00:50:05.15#ibcon#ireg 7 cls_cnt 0 2006.286.00:50:05.15#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.00:50:05.27#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.00:50:05.27#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.00:50:05.27#ibcon#enter wrdev, iclass 28, count 0 2006.286.00:50:05.27#ibcon#first serial, iclass 28, count 0 2006.286.00:50:05.27#ibcon#enter sib2, iclass 28, count 0 2006.286.00:50:05.27#ibcon#flushed, iclass 28, count 0 2006.286.00:50:05.27#ibcon#about to write, iclass 28, count 0 2006.286.00:50:05.27#ibcon#wrote, iclass 28, count 0 2006.286.00:50:05.27#ibcon#about to read 3, iclass 28, count 0 2006.286.00:50:05.29#ibcon#read 3, iclass 28, count 0 2006.286.00:50:05.29#ibcon#about to read 4, iclass 28, count 0 2006.286.00:50:05.29#ibcon#read 4, iclass 28, count 0 2006.286.00:50:05.29#ibcon#about to read 5, iclass 28, count 0 2006.286.00:50:05.29#ibcon#read 5, iclass 28, count 0 2006.286.00:50:05.29#ibcon#about to read 6, iclass 28, count 0 2006.286.00:50:05.29#ibcon#read 6, iclass 28, count 0 2006.286.00:50:05.29#ibcon#end of sib2, iclass 28, count 0 2006.286.00:50:05.29#ibcon#*mode == 0, iclass 28, count 0 2006.286.00:50:05.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.00:50:05.29#ibcon#[27=USB\r\n] 2006.286.00:50:05.29#ibcon#*before write, iclass 28, count 0 2006.286.00:50:05.29#ibcon#enter sib2, iclass 28, count 0 2006.286.00:50:05.29#ibcon#flushed, iclass 28, count 0 2006.286.00:50:05.29#ibcon#about to write, iclass 28, count 0 2006.286.00:50:05.29#ibcon#wrote, iclass 28, count 0 2006.286.00:50:05.29#ibcon#about to read 3, iclass 28, count 0 2006.286.00:50:05.32#ibcon#read 3, iclass 28, count 0 2006.286.00:50:05.32#ibcon#about to read 4, iclass 28, count 0 2006.286.00:50:05.32#ibcon#read 4, iclass 28, count 0 2006.286.00:50:05.32#ibcon#about to read 5, iclass 28, count 0 2006.286.00:50:05.32#ibcon#read 5, iclass 28, count 0 2006.286.00:50:05.32#ibcon#about to read 6, iclass 28, count 0 2006.286.00:50:05.32#ibcon#read 6, iclass 28, count 0 2006.286.00:50:05.32#ibcon#end of sib2, iclass 28, count 0 2006.286.00:50:05.32#ibcon#*after write, iclass 28, count 0 2006.286.00:50:05.32#ibcon#*before return 0, iclass 28, count 0 2006.286.00:50:05.32#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.00:50:05.32#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.00:50:05.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.00:50:05.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.00:50:05.32$vck44/vabw=wide 2006.286.00:50:05.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.00:50:05.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.00:50:05.32#ibcon#ireg 8 cls_cnt 0 2006.286.00:50:05.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:50:05.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:50:05.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:50:05.32#ibcon#enter wrdev, iclass 30, count 0 2006.286.00:50:05.32#ibcon#first serial, iclass 30, count 0 2006.286.00:50:05.32#ibcon#enter sib2, iclass 30, count 0 2006.286.00:50:05.32#ibcon#flushed, iclass 30, count 0 2006.286.00:50:05.32#ibcon#about to write, iclass 30, count 0 2006.286.00:50:05.32#ibcon#wrote, iclass 30, count 0 2006.286.00:50:05.32#ibcon#about to read 3, iclass 30, count 0 2006.286.00:50:05.34#ibcon#read 3, iclass 30, count 0 2006.286.00:50:05.34#ibcon#about to read 4, iclass 30, count 0 2006.286.00:50:05.34#ibcon#read 4, iclass 30, count 0 2006.286.00:50:05.34#ibcon#about to read 5, iclass 30, count 0 2006.286.00:50:05.34#ibcon#read 5, iclass 30, count 0 2006.286.00:50:05.34#ibcon#about to read 6, iclass 30, count 0 2006.286.00:50:05.34#ibcon#read 6, iclass 30, count 0 2006.286.00:50:05.34#ibcon#end of sib2, iclass 30, count 0 2006.286.00:50:05.34#ibcon#*mode == 0, iclass 30, count 0 2006.286.00:50:05.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.00:50:05.34#ibcon#[25=BW32\r\n] 2006.286.00:50:05.34#ibcon#*before write, iclass 30, count 0 2006.286.00:50:05.34#ibcon#enter sib2, iclass 30, count 0 2006.286.00:50:05.34#ibcon#flushed, iclass 30, count 0 2006.286.00:50:05.34#ibcon#about to write, iclass 30, count 0 2006.286.00:50:05.34#ibcon#wrote, iclass 30, count 0 2006.286.00:50:05.34#ibcon#about to read 3, iclass 30, count 0 2006.286.00:50:05.37#ibcon#read 3, iclass 30, count 0 2006.286.00:50:05.37#ibcon#about to read 4, iclass 30, count 0 2006.286.00:50:05.37#ibcon#read 4, iclass 30, count 0 2006.286.00:50:05.37#ibcon#about to read 5, iclass 30, count 0 2006.286.00:50:05.37#ibcon#read 5, iclass 30, count 0 2006.286.00:50:05.37#ibcon#about to read 6, iclass 30, count 0 2006.286.00:50:05.37#ibcon#read 6, iclass 30, count 0 2006.286.00:50:05.37#ibcon#end of sib2, iclass 30, count 0 2006.286.00:50:05.37#ibcon#*after write, iclass 30, count 0 2006.286.00:50:05.37#ibcon#*before return 0, iclass 30, count 0 2006.286.00:50:05.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:50:05.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.00:50:05.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.00:50:05.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.00:50:05.37$vck44/vbbw=wide 2006.286.00:50:05.37#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.00:50:05.37#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.00:50:05.37#ibcon#ireg 8 cls_cnt 0 2006.286.00:50:05.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:50:05.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:50:05.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:50:05.44#ibcon#enter wrdev, iclass 32, count 0 2006.286.00:50:05.44#ibcon#first serial, iclass 32, count 0 2006.286.00:50:05.44#ibcon#enter sib2, iclass 32, count 0 2006.286.00:50:05.44#ibcon#flushed, iclass 32, count 0 2006.286.00:50:05.44#ibcon#about to write, iclass 32, count 0 2006.286.00:50:05.44#ibcon#wrote, iclass 32, count 0 2006.286.00:50:05.44#ibcon#about to read 3, iclass 32, count 0 2006.286.00:50:05.46#ibcon#read 3, iclass 32, count 0 2006.286.00:50:05.46#ibcon#about to read 4, iclass 32, count 0 2006.286.00:50:05.46#ibcon#read 4, iclass 32, count 0 2006.286.00:50:05.46#ibcon#about to read 5, iclass 32, count 0 2006.286.00:50:05.46#ibcon#read 5, iclass 32, count 0 2006.286.00:50:05.46#ibcon#about to read 6, iclass 32, count 0 2006.286.00:50:05.46#ibcon#read 6, iclass 32, count 0 2006.286.00:50:05.46#ibcon#end of sib2, iclass 32, count 0 2006.286.00:50:05.46#ibcon#*mode == 0, iclass 32, count 0 2006.286.00:50:05.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.00:50:05.46#ibcon#[27=BW32\r\n] 2006.286.00:50:05.46#ibcon#*before write, iclass 32, count 0 2006.286.00:50:05.46#ibcon#enter sib2, iclass 32, count 0 2006.286.00:50:05.46#ibcon#flushed, iclass 32, count 0 2006.286.00:50:05.46#ibcon#about to write, iclass 32, count 0 2006.286.00:50:05.46#ibcon#wrote, iclass 32, count 0 2006.286.00:50:05.46#ibcon#about to read 3, iclass 32, count 0 2006.286.00:50:05.49#ibcon#read 3, iclass 32, count 0 2006.286.00:50:05.49#ibcon#about to read 4, iclass 32, count 0 2006.286.00:50:05.49#ibcon#read 4, iclass 32, count 0 2006.286.00:50:05.49#ibcon#about to read 5, iclass 32, count 0 2006.286.00:50:05.49#ibcon#read 5, iclass 32, count 0 2006.286.00:50:05.49#ibcon#about to read 6, iclass 32, count 0 2006.286.00:50:05.49#ibcon#read 6, iclass 32, count 0 2006.286.00:50:05.49#ibcon#end of sib2, iclass 32, count 0 2006.286.00:50:05.49#ibcon#*after write, iclass 32, count 0 2006.286.00:50:05.49#ibcon#*before return 0, iclass 32, count 0 2006.286.00:50:05.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:50:05.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.00:50:05.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.00:50:05.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.00:50:05.49$setupk4/ifdk4 2006.286.00:50:05.49$ifdk4/lo= 2006.286.00:50:05.49$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.00:50:05.49$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.00:50:05.49$ifdk4/patch= 2006.286.00:50:05.49$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.00:50:05.49$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.00:50:05.49$setupk4/!*+20s 2006.286.00:50:13.51#abcon#<5=/03 2.8 6.5 20.34 841016.3\r\n> 2006.286.00:50:13.53#abcon#{5=INTERFACE CLEAR} 2006.286.00:50:13.59#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:50:19.99$setupk4/"tpicd 2006.286.00:50:19.99$setupk4/echo=off 2006.286.00:50:19.99$setupk4/xlog=off 2006.286.00:50:19.99:!2006.286.00:51:51 2006.286.00:51:31.12#trakl#Source acquired 2006.286.00:51:33.14#flagr#flagr/antenna,acquired 2006.286.00:51:51.02:preob 2006.286.00:51:52.15/onsource/TRACKING 2006.286.00:51:52.15:!2006.286.00:52:01 2006.286.00:52:01.02:"tape 2006.286.00:52:01.02:"st=record 2006.286.00:52:01.02:data_valid=on 2006.286.00:52:01.02:midob 2006.286.00:52:02.15/onsource/TRACKING 2006.286.00:52:02.15/wx/20.44,1016.3,83 2006.286.00:52:02.27/cable/+6.5047E-03 2006.286.00:52:03.36/va/01,07,usb,yes,32,35 2006.286.00:52:03.37/va/02,06,usb,yes,33,33 2006.286.00:52:03.37/va/03,07,usb,yes,32,34 2006.286.00:52:03.37/va/04,06,usb,yes,33,35 2006.286.00:52:03.37/va/05,03,usb,yes,33,33 2006.286.00:52:03.37/va/06,04,usb,yes,30,29 2006.286.00:52:03.37/va/07,04,usb,yes,30,31 2006.286.00:52:03.37/va/08,03,usb,yes,31,38 2006.286.00:52:03.59/valo/01,524.99,yes,locked 2006.286.00:52:03.59/valo/02,534.99,yes,locked 2006.286.00:52:03.59/valo/03,564.99,yes,locked 2006.286.00:52:03.60/valo/04,624.99,yes,locked 2006.286.00:52:03.60/valo/05,734.99,yes,locked 2006.286.00:52:03.60/valo/06,814.99,yes,locked 2006.286.00:52:03.60/valo/07,864.99,yes,locked 2006.286.00:52:03.60/valo/08,884.99,yes,locked 2006.286.00:52:04.68/vb/01,04,usb,yes,30,28 2006.286.00:52:04.69/vb/02,05,usb,yes,29,29 2006.286.00:52:04.69/vb/03,04,usb,yes,30,33 2006.286.00:52:04.69/vb/04,05,usb,yes,30,29 2006.286.00:52:04.69/vb/05,04,usb,yes,26,29 2006.286.00:52:04.69/vb/06,03,usb,yes,38,33 2006.286.00:52:04.69/vb/07,04,usb,yes,30,30 2006.286.00:52:04.69/vb/08,04,usb,yes,28,31 2006.286.00:52:04.92/vblo/01,629.99,yes,locked 2006.286.00:52:04.92/vblo/02,634.99,yes,locked 2006.286.00:52:04.92/vblo/03,649.99,yes,locked 2006.286.00:52:04.92/vblo/04,679.99,yes,locked 2006.286.00:52:04.92/vblo/05,709.99,yes,locked 2006.286.00:52:04.92/vblo/06,719.99,yes,locked 2006.286.00:52:04.92/vblo/07,734.99,yes,locked 2006.286.00:52:04.92/vblo/08,744.99,yes,locked 2006.286.00:52:05.06/vabw/8 2006.286.00:52:05.21/vbbw/8 2006.286.00:52:05.30/xfe/off,on,12.0 2006.286.00:52:05.68/ifatt/23,28,28,28 2006.286.00:52:06.07/fmout-gps/S +2.71E-07 2006.286.00:52:06.09:!2006.286.00:52:51 2006.286.00:52:51.00:data_valid=off 2006.286.00:52:51.01:"et 2006.286.00:52:51.01:!+3s 2006.286.00:52:54.02:"tape 2006.286.00:52:54.02:postob 2006.286.00:52:54.07/cable/+6.5047E-03 2006.286.00:52:54.08/wx/20.48,1016.3,83 2006.286.00:52:55.07/fmout-gps/S +2.73E-07 2006.286.00:52:55.08:scan_name=286-0058,jd0610,250 2006.286.00:52:55.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.286.00:52:56.15#flagr#flagr/antenna,new-source 2006.286.00:52:56.15:checkk5 2006.286.00:52:56.53/chk_autoobs//k5ts1/ autoobs is running! 2006.286.00:52:56.92/chk_autoobs//k5ts2/ autoobs is running! 2006.286.00:52:57.33/chk_autoobs//k5ts3/ autoobs is running! 2006.286.00:52:57.76/chk_autoobs//k5ts4/ autoobs is running! 2006.286.00:52:58.10/chk_obsdata//k5ts1/T2860052??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.00:52:58.58/chk_obsdata//k5ts2/T2860052??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.00:52:58.97/chk_obsdata//k5ts3/T2860052??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.00:52:59.62/chk_obsdata//k5ts4/T2860052??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.00:53:00.40/k5log//k5ts1_log_newline 2006.286.00:53:01.33/k5log//k5ts2_log_newline 2006.286.00:53:02.11/k5log//k5ts3_log_newline 2006.286.00:53:03.13/k5log//k5ts4_log_newline 2006.286.00:53:03.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.00:53:03.15:setupk4=1 2006.286.00:53:03.15$setupk4/echo=on 2006.286.00:53:03.15$setupk4/pcalon 2006.286.00:53:03.15$pcalon/"no phase cal control is implemented here 2006.286.00:53:03.15$setupk4/"tpicd=stop 2006.286.00:53:03.15$setupk4/"rec=synch_on 2006.286.00:53:03.15$setupk4/"rec_mode=128 2006.286.00:53:03.15$setupk4/!* 2006.286.00:53:03.15$setupk4/recpk4 2006.286.00:53:03.15$recpk4/recpatch= 2006.286.00:53:03.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.00:53:03.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.00:53:03.16$setupk4/vck44 2006.286.00:53:03.16$vck44/valo=1,524.99 2006.286.00:53:03.16#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.00:53:03.16#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.00:53:03.16#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:03.16#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:53:03.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:53:03.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:53:03.16#ibcon#enter wrdev, iclass 33, count 0 2006.286.00:53:03.16#ibcon#first serial, iclass 33, count 0 2006.286.00:53:03.16#ibcon#enter sib2, iclass 33, count 0 2006.286.00:53:03.16#ibcon#flushed, iclass 33, count 0 2006.286.00:53:03.16#ibcon#about to write, iclass 33, count 0 2006.286.00:53:03.16#ibcon#wrote, iclass 33, count 0 2006.286.00:53:03.16#ibcon#about to read 3, iclass 33, count 0 2006.286.00:53:03.17#ibcon#read 3, iclass 33, count 0 2006.286.00:53:03.17#ibcon#about to read 4, iclass 33, count 0 2006.286.00:53:03.17#ibcon#read 4, iclass 33, count 0 2006.286.00:53:03.17#ibcon#about to read 5, iclass 33, count 0 2006.286.00:53:03.17#ibcon#read 5, iclass 33, count 0 2006.286.00:53:03.17#ibcon#about to read 6, iclass 33, count 0 2006.286.00:53:03.17#ibcon#read 6, iclass 33, count 0 2006.286.00:53:03.17#ibcon#end of sib2, iclass 33, count 0 2006.286.00:53:03.17#ibcon#*mode == 0, iclass 33, count 0 2006.286.00:53:03.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.00:53:03.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.00:53:03.17#ibcon#*before write, iclass 33, count 0 2006.286.00:53:03.17#ibcon#enter sib2, iclass 33, count 0 2006.286.00:53:03.17#ibcon#flushed, iclass 33, count 0 2006.286.00:53:03.17#ibcon#about to write, iclass 33, count 0 2006.286.00:53:03.17#ibcon#wrote, iclass 33, count 0 2006.286.00:53:03.17#ibcon#about to read 3, iclass 33, count 0 2006.286.00:53:03.22#ibcon#read 3, iclass 33, count 0 2006.286.00:53:03.22#ibcon#about to read 4, iclass 33, count 0 2006.286.00:53:03.22#ibcon#read 4, iclass 33, count 0 2006.286.00:53:03.22#ibcon#about to read 5, iclass 33, count 0 2006.286.00:53:03.22#ibcon#read 5, iclass 33, count 0 2006.286.00:53:03.22#ibcon#about to read 6, iclass 33, count 0 2006.286.00:53:03.22#ibcon#read 6, iclass 33, count 0 2006.286.00:53:03.22#ibcon#end of sib2, iclass 33, count 0 2006.286.00:53:03.22#ibcon#*after write, iclass 33, count 0 2006.286.00:53:03.22#ibcon#*before return 0, iclass 33, count 0 2006.286.00:53:03.22#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:53:03.22#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:53:03.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.00:53:03.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.00:53:03.23$vck44/va=1,7 2006.286.00:53:03.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.00:53:03.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.00:53:03.23#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:03.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:53:03.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:53:03.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:53:03.23#ibcon#enter wrdev, iclass 35, count 2 2006.286.00:53:03.23#ibcon#first serial, iclass 35, count 2 2006.286.00:53:03.23#ibcon#enter sib2, iclass 35, count 2 2006.286.00:53:03.23#ibcon#flushed, iclass 35, count 2 2006.286.00:53:03.23#ibcon#about to write, iclass 35, count 2 2006.286.00:53:03.23#ibcon#wrote, iclass 35, count 2 2006.286.00:53:03.23#ibcon#about to read 3, iclass 35, count 2 2006.286.00:53:03.24#ibcon#read 3, iclass 35, count 2 2006.286.00:53:03.24#ibcon#about to read 4, iclass 35, count 2 2006.286.00:53:03.24#ibcon#read 4, iclass 35, count 2 2006.286.00:53:03.24#ibcon#about to read 5, iclass 35, count 2 2006.286.00:53:03.24#ibcon#read 5, iclass 35, count 2 2006.286.00:53:03.24#ibcon#about to read 6, iclass 35, count 2 2006.286.00:53:03.24#ibcon#read 6, iclass 35, count 2 2006.286.00:53:03.24#ibcon#end of sib2, iclass 35, count 2 2006.286.00:53:03.24#ibcon#*mode == 0, iclass 35, count 2 2006.286.00:53:03.24#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.00:53:03.24#ibcon#[25=AT01-07\r\n] 2006.286.00:53:03.24#ibcon#*before write, iclass 35, count 2 2006.286.00:53:03.24#ibcon#enter sib2, iclass 35, count 2 2006.286.00:53:03.24#ibcon#flushed, iclass 35, count 2 2006.286.00:53:03.24#ibcon#about to write, iclass 35, count 2 2006.286.00:53:03.24#ibcon#wrote, iclass 35, count 2 2006.286.00:53:03.24#ibcon#about to read 3, iclass 35, count 2 2006.286.00:53:03.27#ibcon#read 3, iclass 35, count 2 2006.286.00:53:03.27#ibcon#about to read 4, iclass 35, count 2 2006.286.00:53:03.27#ibcon#read 4, iclass 35, count 2 2006.286.00:53:03.27#ibcon#about to read 5, iclass 35, count 2 2006.286.00:53:03.27#ibcon#read 5, iclass 35, count 2 2006.286.00:53:03.27#ibcon#about to read 6, iclass 35, count 2 2006.286.00:53:03.27#ibcon#read 6, iclass 35, count 2 2006.286.00:53:03.27#ibcon#end of sib2, iclass 35, count 2 2006.286.00:53:03.27#ibcon#*after write, iclass 35, count 2 2006.286.00:53:03.27#ibcon#*before return 0, iclass 35, count 2 2006.286.00:53:03.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:53:03.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:53:03.27#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.00:53:03.27#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:03.27#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:53:03.39#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:53:03.39#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:53:03.39#ibcon#enter wrdev, iclass 35, count 0 2006.286.00:53:03.39#ibcon#first serial, iclass 35, count 0 2006.286.00:53:03.39#ibcon#enter sib2, iclass 35, count 0 2006.286.00:53:03.39#ibcon#flushed, iclass 35, count 0 2006.286.00:53:03.39#ibcon#about to write, iclass 35, count 0 2006.286.00:53:03.39#ibcon#wrote, iclass 35, count 0 2006.286.00:53:03.39#ibcon#about to read 3, iclass 35, count 0 2006.286.00:53:03.41#ibcon#read 3, iclass 35, count 0 2006.286.00:53:03.41#ibcon#about to read 4, iclass 35, count 0 2006.286.00:53:03.41#ibcon#read 4, iclass 35, count 0 2006.286.00:53:03.41#ibcon#about to read 5, iclass 35, count 0 2006.286.00:53:03.41#ibcon#read 5, iclass 35, count 0 2006.286.00:53:03.41#ibcon#about to read 6, iclass 35, count 0 2006.286.00:53:03.41#ibcon#read 6, iclass 35, count 0 2006.286.00:53:03.41#ibcon#end of sib2, iclass 35, count 0 2006.286.00:53:03.41#ibcon#*mode == 0, iclass 35, count 0 2006.286.00:53:03.41#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.00:53:03.41#ibcon#[25=USB\r\n] 2006.286.00:53:03.41#ibcon#*before write, iclass 35, count 0 2006.286.00:53:03.41#ibcon#enter sib2, iclass 35, count 0 2006.286.00:53:03.41#ibcon#flushed, iclass 35, count 0 2006.286.00:53:03.41#ibcon#about to write, iclass 35, count 0 2006.286.00:53:03.41#ibcon#wrote, iclass 35, count 0 2006.286.00:53:03.41#ibcon#about to read 3, iclass 35, count 0 2006.286.00:53:03.44#ibcon#read 3, iclass 35, count 0 2006.286.00:53:03.44#ibcon#about to read 4, iclass 35, count 0 2006.286.00:53:03.44#ibcon#read 4, iclass 35, count 0 2006.286.00:53:03.44#ibcon#about to read 5, iclass 35, count 0 2006.286.00:53:03.44#ibcon#read 5, iclass 35, count 0 2006.286.00:53:03.44#ibcon#about to read 6, iclass 35, count 0 2006.286.00:53:03.44#ibcon#read 6, iclass 35, count 0 2006.286.00:53:03.44#ibcon#end of sib2, iclass 35, count 0 2006.286.00:53:03.44#ibcon#*after write, iclass 35, count 0 2006.286.00:53:03.44#ibcon#*before return 0, iclass 35, count 0 2006.286.00:53:03.44#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:53:03.44#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:53:03.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.00:53:03.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.00:53:03.45$vck44/valo=2,534.99 2006.286.00:53:03.45#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.00:53:03.45#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.00:53:03.45#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:03.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:53:03.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:53:03.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:53:03.45#ibcon#enter wrdev, iclass 37, count 0 2006.286.00:53:03.45#ibcon#first serial, iclass 37, count 0 2006.286.00:53:03.45#ibcon#enter sib2, iclass 37, count 0 2006.286.00:53:03.45#ibcon#flushed, iclass 37, count 0 2006.286.00:53:03.45#ibcon#about to write, iclass 37, count 0 2006.286.00:53:03.45#ibcon#wrote, iclass 37, count 0 2006.286.00:53:03.45#ibcon#about to read 3, iclass 37, count 0 2006.286.00:53:03.46#ibcon#read 3, iclass 37, count 0 2006.286.00:53:03.46#ibcon#about to read 4, iclass 37, count 0 2006.286.00:53:03.46#ibcon#read 4, iclass 37, count 0 2006.286.00:53:03.46#ibcon#about to read 5, iclass 37, count 0 2006.286.00:53:03.46#ibcon#read 5, iclass 37, count 0 2006.286.00:53:03.46#ibcon#about to read 6, iclass 37, count 0 2006.286.00:53:03.46#ibcon#read 6, iclass 37, count 0 2006.286.00:53:03.46#ibcon#end of sib2, iclass 37, count 0 2006.286.00:53:03.46#ibcon#*mode == 0, iclass 37, count 0 2006.286.00:53:03.46#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.00:53:03.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.00:53:03.46#ibcon#*before write, iclass 37, count 0 2006.286.00:53:03.46#ibcon#enter sib2, iclass 37, count 0 2006.286.00:53:03.46#ibcon#flushed, iclass 37, count 0 2006.286.00:53:03.46#ibcon#about to write, iclass 37, count 0 2006.286.00:53:03.46#ibcon#wrote, iclass 37, count 0 2006.286.00:53:03.46#ibcon#about to read 3, iclass 37, count 0 2006.286.00:53:03.50#ibcon#read 3, iclass 37, count 0 2006.286.00:53:03.50#ibcon#about to read 4, iclass 37, count 0 2006.286.00:53:03.50#ibcon#read 4, iclass 37, count 0 2006.286.00:53:03.50#ibcon#about to read 5, iclass 37, count 0 2006.286.00:53:03.50#ibcon#read 5, iclass 37, count 0 2006.286.00:53:03.50#ibcon#about to read 6, iclass 37, count 0 2006.286.00:53:03.50#ibcon#read 6, iclass 37, count 0 2006.286.00:53:03.50#ibcon#end of sib2, iclass 37, count 0 2006.286.00:53:03.50#ibcon#*after write, iclass 37, count 0 2006.286.00:53:03.50#ibcon#*before return 0, iclass 37, count 0 2006.286.00:53:03.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:53:03.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:53:03.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.00:53:03.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.00:53:03.51$vck44/va=2,6 2006.286.00:53:03.51#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.00:53:03.51#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.00:53:03.51#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:03.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:53:03.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:53:03.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:53:03.55#ibcon#enter wrdev, iclass 39, count 2 2006.286.00:53:03.55#ibcon#first serial, iclass 39, count 2 2006.286.00:53:03.55#ibcon#enter sib2, iclass 39, count 2 2006.286.00:53:03.55#ibcon#flushed, iclass 39, count 2 2006.286.00:53:03.55#ibcon#about to write, iclass 39, count 2 2006.286.00:53:03.55#ibcon#wrote, iclass 39, count 2 2006.286.00:53:03.55#ibcon#about to read 3, iclass 39, count 2 2006.286.00:53:03.57#ibcon#read 3, iclass 39, count 2 2006.286.00:53:03.57#ibcon#about to read 4, iclass 39, count 2 2006.286.00:53:03.57#ibcon#read 4, iclass 39, count 2 2006.286.00:53:03.57#ibcon#about to read 5, iclass 39, count 2 2006.286.00:53:03.57#ibcon#read 5, iclass 39, count 2 2006.286.00:53:03.57#ibcon#about to read 6, iclass 39, count 2 2006.286.00:53:03.57#ibcon#read 6, iclass 39, count 2 2006.286.00:53:03.57#ibcon#end of sib2, iclass 39, count 2 2006.286.00:53:03.57#ibcon#*mode == 0, iclass 39, count 2 2006.286.00:53:03.57#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.00:53:03.57#ibcon#[25=AT02-06\r\n] 2006.286.00:53:03.57#ibcon#*before write, iclass 39, count 2 2006.286.00:53:03.57#ibcon#enter sib2, iclass 39, count 2 2006.286.00:53:03.57#ibcon#flushed, iclass 39, count 2 2006.286.00:53:03.57#ibcon#about to write, iclass 39, count 2 2006.286.00:53:03.57#ibcon#wrote, iclass 39, count 2 2006.286.00:53:03.57#ibcon#about to read 3, iclass 39, count 2 2006.286.00:53:03.60#ibcon#read 3, iclass 39, count 2 2006.286.00:53:03.60#ibcon#about to read 4, iclass 39, count 2 2006.286.00:53:03.60#ibcon#read 4, iclass 39, count 2 2006.286.00:53:03.60#ibcon#about to read 5, iclass 39, count 2 2006.286.00:53:03.60#ibcon#read 5, iclass 39, count 2 2006.286.00:53:03.60#ibcon#about to read 6, iclass 39, count 2 2006.286.00:53:03.60#ibcon#read 6, iclass 39, count 2 2006.286.00:53:03.60#ibcon#end of sib2, iclass 39, count 2 2006.286.00:53:03.60#ibcon#*after write, iclass 39, count 2 2006.286.00:53:03.60#ibcon#*before return 0, iclass 39, count 2 2006.286.00:53:03.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:53:03.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:53:03.60#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.00:53:03.60#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:03.60#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:53:03.72#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:53:03.72#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:53:03.72#ibcon#enter wrdev, iclass 39, count 0 2006.286.00:53:03.72#ibcon#first serial, iclass 39, count 0 2006.286.00:53:03.72#ibcon#enter sib2, iclass 39, count 0 2006.286.00:53:03.72#ibcon#flushed, iclass 39, count 0 2006.286.00:53:03.72#ibcon#about to write, iclass 39, count 0 2006.286.00:53:03.72#ibcon#wrote, iclass 39, count 0 2006.286.00:53:03.72#ibcon#about to read 3, iclass 39, count 0 2006.286.00:53:03.74#ibcon#read 3, iclass 39, count 0 2006.286.00:53:03.74#ibcon#about to read 4, iclass 39, count 0 2006.286.00:53:03.74#ibcon#read 4, iclass 39, count 0 2006.286.00:53:03.74#ibcon#about to read 5, iclass 39, count 0 2006.286.00:53:03.74#ibcon#read 5, iclass 39, count 0 2006.286.00:53:03.74#ibcon#about to read 6, iclass 39, count 0 2006.286.00:53:03.74#ibcon#read 6, iclass 39, count 0 2006.286.00:53:03.74#ibcon#end of sib2, iclass 39, count 0 2006.286.00:53:03.74#ibcon#*mode == 0, iclass 39, count 0 2006.286.00:53:03.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.00:53:03.74#ibcon#[25=USB\r\n] 2006.286.00:53:03.74#ibcon#*before write, iclass 39, count 0 2006.286.00:53:03.74#ibcon#enter sib2, iclass 39, count 0 2006.286.00:53:03.74#ibcon#flushed, iclass 39, count 0 2006.286.00:53:03.74#ibcon#about to write, iclass 39, count 0 2006.286.00:53:03.74#ibcon#wrote, iclass 39, count 0 2006.286.00:53:03.74#ibcon#about to read 3, iclass 39, count 0 2006.286.00:53:03.77#ibcon#read 3, iclass 39, count 0 2006.286.00:53:03.77#ibcon#about to read 4, iclass 39, count 0 2006.286.00:53:03.77#ibcon#read 4, iclass 39, count 0 2006.286.00:53:03.77#ibcon#about to read 5, iclass 39, count 0 2006.286.00:53:03.77#ibcon#read 5, iclass 39, count 0 2006.286.00:53:03.77#ibcon#about to read 6, iclass 39, count 0 2006.286.00:53:03.77#ibcon#read 6, iclass 39, count 0 2006.286.00:53:03.77#ibcon#end of sib2, iclass 39, count 0 2006.286.00:53:03.77#ibcon#*after write, iclass 39, count 0 2006.286.00:53:03.77#ibcon#*before return 0, iclass 39, count 0 2006.286.00:53:03.77#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:53:03.77#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:53:03.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.00:53:03.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.00:53:03.78$vck44/valo=3,564.99 2006.286.00:53:03.78#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.00:53:03.78#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.00:53:03.78#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:03.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:53:03.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:53:03.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:53:03.78#ibcon#enter wrdev, iclass 3, count 0 2006.286.00:53:03.78#ibcon#first serial, iclass 3, count 0 2006.286.00:53:03.78#ibcon#enter sib2, iclass 3, count 0 2006.286.00:53:03.78#ibcon#flushed, iclass 3, count 0 2006.286.00:53:03.78#ibcon#about to write, iclass 3, count 0 2006.286.00:53:03.78#ibcon#wrote, iclass 3, count 0 2006.286.00:53:03.78#ibcon#about to read 3, iclass 3, count 0 2006.286.00:53:03.79#ibcon#read 3, iclass 3, count 0 2006.286.00:53:03.79#ibcon#about to read 4, iclass 3, count 0 2006.286.00:53:03.79#ibcon#read 4, iclass 3, count 0 2006.286.00:53:03.79#ibcon#about to read 5, iclass 3, count 0 2006.286.00:53:03.79#ibcon#read 5, iclass 3, count 0 2006.286.00:53:03.79#ibcon#about to read 6, iclass 3, count 0 2006.286.00:53:03.79#ibcon#read 6, iclass 3, count 0 2006.286.00:53:03.79#ibcon#end of sib2, iclass 3, count 0 2006.286.00:53:03.79#ibcon#*mode == 0, iclass 3, count 0 2006.286.00:53:03.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.00:53:03.79#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.00:53:03.79#ibcon#*before write, iclass 3, count 0 2006.286.00:53:03.79#ibcon#enter sib2, iclass 3, count 0 2006.286.00:53:03.79#ibcon#flushed, iclass 3, count 0 2006.286.00:53:03.79#ibcon#about to write, iclass 3, count 0 2006.286.00:53:03.79#ibcon#wrote, iclass 3, count 0 2006.286.00:53:03.79#ibcon#about to read 3, iclass 3, count 0 2006.286.00:53:03.83#ibcon#read 3, iclass 3, count 0 2006.286.00:53:03.83#ibcon#about to read 4, iclass 3, count 0 2006.286.00:53:03.83#ibcon#read 4, iclass 3, count 0 2006.286.00:53:03.83#ibcon#about to read 5, iclass 3, count 0 2006.286.00:53:03.83#ibcon#read 5, iclass 3, count 0 2006.286.00:53:03.83#ibcon#about to read 6, iclass 3, count 0 2006.286.00:53:03.83#ibcon#read 6, iclass 3, count 0 2006.286.00:53:03.83#ibcon#end of sib2, iclass 3, count 0 2006.286.00:53:03.83#ibcon#*after write, iclass 3, count 0 2006.286.00:53:03.83#ibcon#*before return 0, iclass 3, count 0 2006.286.00:53:03.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:53:03.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:53:03.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.00:53:03.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.00:53:03.84$vck44/va=3,7 2006.286.00:53:03.84#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.00:53:03.84#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.00:53:03.84#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:03.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:53:03.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:53:03.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:53:03.88#ibcon#enter wrdev, iclass 5, count 2 2006.286.00:53:03.88#ibcon#first serial, iclass 5, count 2 2006.286.00:53:03.88#ibcon#enter sib2, iclass 5, count 2 2006.286.00:53:03.88#ibcon#flushed, iclass 5, count 2 2006.286.00:53:03.88#ibcon#about to write, iclass 5, count 2 2006.286.00:53:03.88#ibcon#wrote, iclass 5, count 2 2006.286.00:53:03.88#ibcon#about to read 3, iclass 5, count 2 2006.286.00:53:03.90#ibcon#read 3, iclass 5, count 2 2006.286.00:53:03.90#ibcon#about to read 4, iclass 5, count 2 2006.286.00:53:03.90#ibcon#read 4, iclass 5, count 2 2006.286.00:53:03.90#ibcon#about to read 5, iclass 5, count 2 2006.286.00:53:03.90#ibcon#read 5, iclass 5, count 2 2006.286.00:53:03.90#ibcon#about to read 6, iclass 5, count 2 2006.286.00:53:03.90#ibcon#read 6, iclass 5, count 2 2006.286.00:53:03.90#ibcon#end of sib2, iclass 5, count 2 2006.286.00:53:03.90#ibcon#*mode == 0, iclass 5, count 2 2006.286.00:53:03.90#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.00:53:03.90#ibcon#[25=AT03-07\r\n] 2006.286.00:53:03.90#ibcon#*before write, iclass 5, count 2 2006.286.00:53:03.90#ibcon#enter sib2, iclass 5, count 2 2006.286.00:53:03.90#ibcon#flushed, iclass 5, count 2 2006.286.00:53:03.90#ibcon#about to write, iclass 5, count 2 2006.286.00:53:03.90#ibcon#wrote, iclass 5, count 2 2006.286.00:53:03.90#ibcon#about to read 3, iclass 5, count 2 2006.286.00:53:03.93#ibcon#read 3, iclass 5, count 2 2006.286.00:53:03.93#ibcon#about to read 4, iclass 5, count 2 2006.286.00:53:03.93#ibcon#read 4, iclass 5, count 2 2006.286.00:53:03.93#ibcon#about to read 5, iclass 5, count 2 2006.286.00:53:03.93#ibcon#read 5, iclass 5, count 2 2006.286.00:53:03.93#ibcon#about to read 6, iclass 5, count 2 2006.286.00:53:03.93#ibcon#read 6, iclass 5, count 2 2006.286.00:53:03.93#ibcon#end of sib2, iclass 5, count 2 2006.286.00:53:03.93#ibcon#*after write, iclass 5, count 2 2006.286.00:53:03.93#ibcon#*before return 0, iclass 5, count 2 2006.286.00:53:03.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:53:03.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.00:53:03.93#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.00:53:03.93#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:03.93#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:53:04.05#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:53:04.05#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:53:04.05#ibcon#enter wrdev, iclass 5, count 0 2006.286.00:53:04.05#ibcon#first serial, iclass 5, count 0 2006.286.00:53:04.05#ibcon#enter sib2, iclass 5, count 0 2006.286.00:53:04.05#ibcon#flushed, iclass 5, count 0 2006.286.00:53:04.05#ibcon#about to write, iclass 5, count 0 2006.286.00:53:04.05#ibcon#wrote, iclass 5, count 0 2006.286.00:53:04.05#ibcon#about to read 3, iclass 5, count 0 2006.286.00:53:04.07#ibcon#read 3, iclass 5, count 0 2006.286.00:53:04.07#ibcon#about to read 4, iclass 5, count 0 2006.286.00:53:04.07#ibcon#read 4, iclass 5, count 0 2006.286.00:53:04.07#ibcon#about to read 5, iclass 5, count 0 2006.286.00:53:04.07#ibcon#read 5, iclass 5, count 0 2006.286.00:53:04.07#ibcon#about to read 6, iclass 5, count 0 2006.286.00:53:04.07#ibcon#read 6, iclass 5, count 0 2006.286.00:53:04.07#ibcon#end of sib2, iclass 5, count 0 2006.286.00:53:04.07#ibcon#*mode == 0, iclass 5, count 0 2006.286.00:53:04.07#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.00:53:04.07#ibcon#[25=USB\r\n] 2006.286.00:53:04.07#ibcon#*before write, iclass 5, count 0 2006.286.00:53:04.07#ibcon#enter sib2, iclass 5, count 0 2006.286.00:53:04.07#ibcon#flushed, iclass 5, count 0 2006.286.00:53:04.07#ibcon#about to write, iclass 5, count 0 2006.286.00:53:04.07#ibcon#wrote, iclass 5, count 0 2006.286.00:53:04.07#ibcon#about to read 3, iclass 5, count 0 2006.286.00:53:04.10#ibcon#read 3, iclass 5, count 0 2006.286.00:53:04.10#ibcon#about to read 4, iclass 5, count 0 2006.286.00:53:04.10#ibcon#read 4, iclass 5, count 0 2006.286.00:53:04.10#ibcon#about to read 5, iclass 5, count 0 2006.286.00:53:04.10#ibcon#read 5, iclass 5, count 0 2006.286.00:53:04.10#ibcon#about to read 6, iclass 5, count 0 2006.286.00:53:04.10#ibcon#read 6, iclass 5, count 0 2006.286.00:53:04.10#ibcon#end of sib2, iclass 5, count 0 2006.286.00:53:04.10#ibcon#*after write, iclass 5, count 0 2006.286.00:53:04.10#ibcon#*before return 0, iclass 5, count 0 2006.286.00:53:04.10#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:53:04.10#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.00:53:04.10#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.00:53:04.10#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.00:53:04.11$vck44/valo=4,624.99 2006.286.00:53:04.11#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.00:53:04.11#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.00:53:04.11#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:04.11#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:53:04.11#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:53:04.11#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:53:04.11#ibcon#enter wrdev, iclass 7, count 0 2006.286.00:53:04.11#ibcon#first serial, iclass 7, count 0 2006.286.00:53:04.11#ibcon#enter sib2, iclass 7, count 0 2006.286.00:53:04.11#ibcon#flushed, iclass 7, count 0 2006.286.00:53:04.11#ibcon#about to write, iclass 7, count 0 2006.286.00:53:04.11#ibcon#wrote, iclass 7, count 0 2006.286.00:53:04.11#ibcon#about to read 3, iclass 7, count 0 2006.286.00:53:04.12#ibcon#read 3, iclass 7, count 0 2006.286.00:53:04.12#ibcon#about to read 4, iclass 7, count 0 2006.286.00:53:04.12#ibcon#read 4, iclass 7, count 0 2006.286.00:53:04.12#ibcon#about to read 5, iclass 7, count 0 2006.286.00:53:04.12#ibcon#read 5, iclass 7, count 0 2006.286.00:53:04.12#ibcon#about to read 6, iclass 7, count 0 2006.286.00:53:04.12#ibcon#read 6, iclass 7, count 0 2006.286.00:53:04.12#ibcon#end of sib2, iclass 7, count 0 2006.286.00:53:04.12#ibcon#*mode == 0, iclass 7, count 0 2006.286.00:53:04.12#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.00:53:04.12#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.00:53:04.12#ibcon#*before write, iclass 7, count 0 2006.286.00:53:04.12#ibcon#enter sib2, iclass 7, count 0 2006.286.00:53:04.12#ibcon#flushed, iclass 7, count 0 2006.286.00:53:04.12#ibcon#about to write, iclass 7, count 0 2006.286.00:53:04.12#ibcon#wrote, iclass 7, count 0 2006.286.00:53:04.12#ibcon#about to read 3, iclass 7, count 0 2006.286.00:53:04.16#ibcon#read 3, iclass 7, count 0 2006.286.00:53:04.16#ibcon#about to read 4, iclass 7, count 0 2006.286.00:53:04.16#ibcon#read 4, iclass 7, count 0 2006.286.00:53:04.16#ibcon#about to read 5, iclass 7, count 0 2006.286.00:53:04.16#ibcon#read 5, iclass 7, count 0 2006.286.00:53:04.16#ibcon#about to read 6, iclass 7, count 0 2006.286.00:53:04.16#ibcon#read 6, iclass 7, count 0 2006.286.00:53:04.16#ibcon#end of sib2, iclass 7, count 0 2006.286.00:53:04.16#ibcon#*after write, iclass 7, count 0 2006.286.00:53:04.16#ibcon#*before return 0, iclass 7, count 0 2006.286.00:53:04.16#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:53:04.16#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.00:53:04.16#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.00:53:04.16#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.00:53:04.17$vck44/va=4,6 2006.286.00:53:04.17#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.00:53:04.17#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.00:53:04.17#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:04.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:53:04.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:53:04.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:53:04.21#ibcon#enter wrdev, iclass 11, count 2 2006.286.00:53:04.21#ibcon#first serial, iclass 11, count 2 2006.286.00:53:04.21#ibcon#enter sib2, iclass 11, count 2 2006.286.00:53:04.21#ibcon#flushed, iclass 11, count 2 2006.286.00:53:04.21#ibcon#about to write, iclass 11, count 2 2006.286.00:53:04.21#ibcon#wrote, iclass 11, count 2 2006.286.00:53:04.21#ibcon#about to read 3, iclass 11, count 2 2006.286.00:53:04.23#ibcon#read 3, iclass 11, count 2 2006.286.00:53:04.23#ibcon#about to read 4, iclass 11, count 2 2006.286.00:53:04.23#ibcon#read 4, iclass 11, count 2 2006.286.00:53:04.23#ibcon#about to read 5, iclass 11, count 2 2006.286.00:53:04.23#ibcon#read 5, iclass 11, count 2 2006.286.00:53:04.23#ibcon#about to read 6, iclass 11, count 2 2006.286.00:53:04.23#ibcon#read 6, iclass 11, count 2 2006.286.00:53:04.23#ibcon#end of sib2, iclass 11, count 2 2006.286.00:53:04.23#ibcon#*mode == 0, iclass 11, count 2 2006.286.00:53:04.23#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.00:53:04.23#ibcon#[25=AT04-06\r\n] 2006.286.00:53:04.23#ibcon#*before write, iclass 11, count 2 2006.286.00:53:04.23#ibcon#enter sib2, iclass 11, count 2 2006.286.00:53:04.23#ibcon#flushed, iclass 11, count 2 2006.286.00:53:04.23#ibcon#about to write, iclass 11, count 2 2006.286.00:53:04.23#ibcon#wrote, iclass 11, count 2 2006.286.00:53:04.23#ibcon#about to read 3, iclass 11, count 2 2006.286.00:53:04.26#ibcon#read 3, iclass 11, count 2 2006.286.00:53:04.26#ibcon#about to read 4, iclass 11, count 2 2006.286.00:53:04.26#ibcon#read 4, iclass 11, count 2 2006.286.00:53:04.26#ibcon#about to read 5, iclass 11, count 2 2006.286.00:53:04.26#ibcon#read 5, iclass 11, count 2 2006.286.00:53:04.26#ibcon#about to read 6, iclass 11, count 2 2006.286.00:53:04.26#ibcon#read 6, iclass 11, count 2 2006.286.00:53:04.26#ibcon#end of sib2, iclass 11, count 2 2006.286.00:53:04.26#ibcon#*after write, iclass 11, count 2 2006.286.00:53:04.26#ibcon#*before return 0, iclass 11, count 2 2006.286.00:53:04.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:53:04.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.00:53:04.26#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.00:53:04.26#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:04.26#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:53:04.38#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:53:04.38#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:53:04.38#ibcon#enter wrdev, iclass 11, count 0 2006.286.00:53:04.38#ibcon#first serial, iclass 11, count 0 2006.286.00:53:04.38#ibcon#enter sib2, iclass 11, count 0 2006.286.00:53:04.38#ibcon#flushed, iclass 11, count 0 2006.286.00:53:04.38#ibcon#about to write, iclass 11, count 0 2006.286.00:53:04.38#ibcon#wrote, iclass 11, count 0 2006.286.00:53:04.38#ibcon#about to read 3, iclass 11, count 0 2006.286.00:53:04.40#ibcon#read 3, iclass 11, count 0 2006.286.00:53:04.40#ibcon#about to read 4, iclass 11, count 0 2006.286.00:53:04.40#ibcon#read 4, iclass 11, count 0 2006.286.00:53:04.40#ibcon#about to read 5, iclass 11, count 0 2006.286.00:53:04.40#ibcon#read 5, iclass 11, count 0 2006.286.00:53:04.40#ibcon#about to read 6, iclass 11, count 0 2006.286.00:53:04.40#ibcon#read 6, iclass 11, count 0 2006.286.00:53:04.40#ibcon#end of sib2, iclass 11, count 0 2006.286.00:53:04.40#ibcon#*mode == 0, iclass 11, count 0 2006.286.00:53:04.40#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.00:53:04.40#ibcon#[25=USB\r\n] 2006.286.00:53:04.40#ibcon#*before write, iclass 11, count 0 2006.286.00:53:04.40#ibcon#enter sib2, iclass 11, count 0 2006.286.00:53:04.40#ibcon#flushed, iclass 11, count 0 2006.286.00:53:04.40#ibcon#about to write, iclass 11, count 0 2006.286.00:53:04.40#ibcon#wrote, iclass 11, count 0 2006.286.00:53:04.40#ibcon#about to read 3, iclass 11, count 0 2006.286.00:53:04.43#ibcon#read 3, iclass 11, count 0 2006.286.00:53:04.43#ibcon#about to read 4, iclass 11, count 0 2006.286.00:53:04.43#ibcon#read 4, iclass 11, count 0 2006.286.00:53:04.43#ibcon#about to read 5, iclass 11, count 0 2006.286.00:53:04.43#ibcon#read 5, iclass 11, count 0 2006.286.00:53:04.43#ibcon#about to read 6, iclass 11, count 0 2006.286.00:53:04.43#ibcon#read 6, iclass 11, count 0 2006.286.00:53:04.43#ibcon#end of sib2, iclass 11, count 0 2006.286.00:53:04.43#ibcon#*after write, iclass 11, count 0 2006.286.00:53:04.43#ibcon#*before return 0, iclass 11, count 0 2006.286.00:53:04.43#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:53:04.43#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.00:53:04.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.00:53:04.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.00:53:04.44$vck44/valo=5,734.99 2006.286.00:53:04.44#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.00:53:04.44#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.00:53:04.44#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:04.44#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:53:04.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:53:04.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:53:04.44#ibcon#enter wrdev, iclass 13, count 0 2006.286.00:53:04.44#ibcon#first serial, iclass 13, count 0 2006.286.00:53:04.44#ibcon#enter sib2, iclass 13, count 0 2006.286.00:53:04.44#ibcon#flushed, iclass 13, count 0 2006.286.00:53:04.44#ibcon#about to write, iclass 13, count 0 2006.286.00:53:04.44#ibcon#wrote, iclass 13, count 0 2006.286.00:53:04.44#ibcon#about to read 3, iclass 13, count 0 2006.286.00:53:04.45#ibcon#read 3, iclass 13, count 0 2006.286.00:53:04.45#ibcon#about to read 4, iclass 13, count 0 2006.286.00:53:04.45#ibcon#read 4, iclass 13, count 0 2006.286.00:53:04.45#ibcon#about to read 5, iclass 13, count 0 2006.286.00:53:04.45#ibcon#read 5, iclass 13, count 0 2006.286.00:53:04.45#ibcon#about to read 6, iclass 13, count 0 2006.286.00:53:04.45#ibcon#read 6, iclass 13, count 0 2006.286.00:53:04.45#ibcon#end of sib2, iclass 13, count 0 2006.286.00:53:04.45#ibcon#*mode == 0, iclass 13, count 0 2006.286.00:53:04.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.00:53:04.45#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.00:53:04.45#ibcon#*before write, iclass 13, count 0 2006.286.00:53:04.45#ibcon#enter sib2, iclass 13, count 0 2006.286.00:53:04.45#ibcon#flushed, iclass 13, count 0 2006.286.00:53:04.45#ibcon#about to write, iclass 13, count 0 2006.286.00:53:04.45#ibcon#wrote, iclass 13, count 0 2006.286.00:53:04.45#ibcon#about to read 3, iclass 13, count 0 2006.286.00:53:04.49#ibcon#read 3, iclass 13, count 0 2006.286.00:53:04.49#ibcon#about to read 4, iclass 13, count 0 2006.286.00:53:04.49#ibcon#read 4, iclass 13, count 0 2006.286.00:53:04.49#ibcon#about to read 5, iclass 13, count 0 2006.286.00:53:04.49#ibcon#read 5, iclass 13, count 0 2006.286.00:53:04.49#ibcon#about to read 6, iclass 13, count 0 2006.286.00:53:04.49#ibcon#read 6, iclass 13, count 0 2006.286.00:53:04.49#ibcon#end of sib2, iclass 13, count 0 2006.286.00:53:04.49#ibcon#*after write, iclass 13, count 0 2006.286.00:53:04.49#ibcon#*before return 0, iclass 13, count 0 2006.286.00:53:04.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:53:04.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:53:04.49#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.00:53:04.49#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.00:53:04.50$vck44/va=5,3 2006.286.00:53:04.50#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.00:53:04.50#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.00:53:04.50#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:04.50#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:53:04.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:53:04.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:53:04.54#ibcon#enter wrdev, iclass 15, count 2 2006.286.00:53:04.54#ibcon#first serial, iclass 15, count 2 2006.286.00:53:04.54#ibcon#enter sib2, iclass 15, count 2 2006.286.00:53:04.54#ibcon#flushed, iclass 15, count 2 2006.286.00:53:04.54#ibcon#about to write, iclass 15, count 2 2006.286.00:53:04.54#ibcon#wrote, iclass 15, count 2 2006.286.00:53:04.54#ibcon#about to read 3, iclass 15, count 2 2006.286.00:53:04.56#ibcon#read 3, iclass 15, count 2 2006.286.00:53:04.56#ibcon#about to read 4, iclass 15, count 2 2006.286.00:53:04.56#ibcon#read 4, iclass 15, count 2 2006.286.00:53:04.56#ibcon#about to read 5, iclass 15, count 2 2006.286.00:53:04.56#ibcon#read 5, iclass 15, count 2 2006.286.00:53:04.56#ibcon#about to read 6, iclass 15, count 2 2006.286.00:53:04.56#ibcon#read 6, iclass 15, count 2 2006.286.00:53:04.56#ibcon#end of sib2, iclass 15, count 2 2006.286.00:53:04.56#ibcon#*mode == 0, iclass 15, count 2 2006.286.00:53:04.56#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.00:53:04.56#ibcon#[25=AT05-03\r\n] 2006.286.00:53:04.56#ibcon#*before write, iclass 15, count 2 2006.286.00:53:04.56#ibcon#enter sib2, iclass 15, count 2 2006.286.00:53:04.56#ibcon#flushed, iclass 15, count 2 2006.286.00:53:04.56#ibcon#about to write, iclass 15, count 2 2006.286.00:53:04.56#ibcon#wrote, iclass 15, count 2 2006.286.00:53:04.56#ibcon#about to read 3, iclass 15, count 2 2006.286.00:53:04.59#ibcon#read 3, iclass 15, count 2 2006.286.00:53:04.59#ibcon#about to read 4, iclass 15, count 2 2006.286.00:53:04.59#ibcon#read 4, iclass 15, count 2 2006.286.00:53:04.59#ibcon#about to read 5, iclass 15, count 2 2006.286.00:53:04.59#ibcon#read 5, iclass 15, count 2 2006.286.00:53:04.59#ibcon#about to read 6, iclass 15, count 2 2006.286.00:53:04.59#ibcon#read 6, iclass 15, count 2 2006.286.00:53:04.59#ibcon#end of sib2, iclass 15, count 2 2006.286.00:53:04.59#ibcon#*after write, iclass 15, count 2 2006.286.00:53:04.59#ibcon#*before return 0, iclass 15, count 2 2006.286.00:53:04.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:53:04.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:53:04.59#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.00:53:04.59#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:04.59#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:53:04.71#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:53:04.71#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:53:04.71#ibcon#enter wrdev, iclass 15, count 0 2006.286.00:53:04.71#ibcon#first serial, iclass 15, count 0 2006.286.00:53:04.71#ibcon#enter sib2, iclass 15, count 0 2006.286.00:53:04.71#ibcon#flushed, iclass 15, count 0 2006.286.00:53:04.71#ibcon#about to write, iclass 15, count 0 2006.286.00:53:04.71#ibcon#wrote, iclass 15, count 0 2006.286.00:53:04.71#ibcon#about to read 3, iclass 15, count 0 2006.286.00:53:04.73#ibcon#read 3, iclass 15, count 0 2006.286.00:53:04.73#ibcon#about to read 4, iclass 15, count 0 2006.286.00:53:04.73#ibcon#read 4, iclass 15, count 0 2006.286.00:53:04.73#ibcon#about to read 5, iclass 15, count 0 2006.286.00:53:04.73#ibcon#read 5, iclass 15, count 0 2006.286.00:53:04.73#ibcon#about to read 6, iclass 15, count 0 2006.286.00:53:04.73#ibcon#read 6, iclass 15, count 0 2006.286.00:53:04.73#ibcon#end of sib2, iclass 15, count 0 2006.286.00:53:04.73#ibcon#*mode == 0, iclass 15, count 0 2006.286.00:53:04.73#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.00:53:04.73#ibcon#[25=USB\r\n] 2006.286.00:53:04.73#ibcon#*before write, iclass 15, count 0 2006.286.00:53:04.73#ibcon#enter sib2, iclass 15, count 0 2006.286.00:53:04.73#ibcon#flushed, iclass 15, count 0 2006.286.00:53:04.73#ibcon#about to write, iclass 15, count 0 2006.286.00:53:04.73#ibcon#wrote, iclass 15, count 0 2006.286.00:53:04.73#ibcon#about to read 3, iclass 15, count 0 2006.286.00:53:04.76#ibcon#read 3, iclass 15, count 0 2006.286.00:53:04.76#ibcon#about to read 4, iclass 15, count 0 2006.286.00:53:04.76#ibcon#read 4, iclass 15, count 0 2006.286.00:53:04.76#ibcon#about to read 5, iclass 15, count 0 2006.286.00:53:04.76#ibcon#read 5, iclass 15, count 0 2006.286.00:53:04.76#ibcon#about to read 6, iclass 15, count 0 2006.286.00:53:04.76#ibcon#read 6, iclass 15, count 0 2006.286.00:53:04.76#ibcon#end of sib2, iclass 15, count 0 2006.286.00:53:04.76#ibcon#*after write, iclass 15, count 0 2006.286.00:53:04.76#ibcon#*before return 0, iclass 15, count 0 2006.286.00:53:04.76#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:53:04.76#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:53:04.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.00:53:04.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.00:53:04.77$vck44/valo=6,814.99 2006.286.00:53:04.77#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.00:53:04.77#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.00:53:04.77#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:04.77#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:53:04.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:53:04.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:53:04.77#ibcon#enter wrdev, iclass 17, count 0 2006.286.00:53:04.77#ibcon#first serial, iclass 17, count 0 2006.286.00:53:04.77#ibcon#enter sib2, iclass 17, count 0 2006.286.00:53:04.77#ibcon#flushed, iclass 17, count 0 2006.286.00:53:04.77#ibcon#about to write, iclass 17, count 0 2006.286.00:53:04.77#ibcon#wrote, iclass 17, count 0 2006.286.00:53:04.77#ibcon#about to read 3, iclass 17, count 0 2006.286.00:53:04.78#ibcon#read 3, iclass 17, count 0 2006.286.00:53:04.78#ibcon#about to read 4, iclass 17, count 0 2006.286.00:53:04.78#ibcon#read 4, iclass 17, count 0 2006.286.00:53:04.78#ibcon#about to read 5, iclass 17, count 0 2006.286.00:53:04.78#ibcon#read 5, iclass 17, count 0 2006.286.00:53:04.78#ibcon#about to read 6, iclass 17, count 0 2006.286.00:53:04.78#ibcon#read 6, iclass 17, count 0 2006.286.00:53:04.78#ibcon#end of sib2, iclass 17, count 0 2006.286.00:53:04.78#ibcon#*mode == 0, iclass 17, count 0 2006.286.00:53:04.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.00:53:04.78#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.00:53:04.78#ibcon#*before write, iclass 17, count 0 2006.286.00:53:04.78#ibcon#enter sib2, iclass 17, count 0 2006.286.00:53:04.78#ibcon#flushed, iclass 17, count 0 2006.286.00:53:04.78#ibcon#about to write, iclass 17, count 0 2006.286.00:53:04.78#ibcon#wrote, iclass 17, count 0 2006.286.00:53:04.78#ibcon#about to read 3, iclass 17, count 0 2006.286.00:53:04.82#ibcon#read 3, iclass 17, count 0 2006.286.00:53:04.82#ibcon#about to read 4, iclass 17, count 0 2006.286.00:53:04.82#ibcon#read 4, iclass 17, count 0 2006.286.00:53:04.82#ibcon#about to read 5, iclass 17, count 0 2006.286.00:53:04.82#ibcon#read 5, iclass 17, count 0 2006.286.00:53:04.82#ibcon#about to read 6, iclass 17, count 0 2006.286.00:53:04.82#ibcon#read 6, iclass 17, count 0 2006.286.00:53:04.82#ibcon#end of sib2, iclass 17, count 0 2006.286.00:53:04.82#ibcon#*after write, iclass 17, count 0 2006.286.00:53:04.82#ibcon#*before return 0, iclass 17, count 0 2006.286.00:53:04.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:53:04.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:53:04.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.00:53:04.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.00:53:04.83$vck44/va=6,4 2006.286.00:53:04.83#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.00:53:04.83#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.00:53:04.83#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:04.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:53:04.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:53:04.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:53:04.87#ibcon#enter wrdev, iclass 19, count 2 2006.286.00:53:04.87#ibcon#first serial, iclass 19, count 2 2006.286.00:53:04.87#ibcon#enter sib2, iclass 19, count 2 2006.286.00:53:04.87#ibcon#flushed, iclass 19, count 2 2006.286.00:53:04.87#ibcon#about to write, iclass 19, count 2 2006.286.00:53:04.87#ibcon#wrote, iclass 19, count 2 2006.286.00:53:04.87#ibcon#about to read 3, iclass 19, count 2 2006.286.00:53:04.89#ibcon#read 3, iclass 19, count 2 2006.286.00:53:04.89#ibcon#about to read 4, iclass 19, count 2 2006.286.00:53:04.89#ibcon#read 4, iclass 19, count 2 2006.286.00:53:04.89#ibcon#about to read 5, iclass 19, count 2 2006.286.00:53:04.89#ibcon#read 5, iclass 19, count 2 2006.286.00:53:04.89#ibcon#about to read 6, iclass 19, count 2 2006.286.00:53:04.89#ibcon#read 6, iclass 19, count 2 2006.286.00:53:04.89#ibcon#end of sib2, iclass 19, count 2 2006.286.00:53:04.89#ibcon#*mode == 0, iclass 19, count 2 2006.286.00:53:04.89#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.00:53:04.89#ibcon#[25=AT06-04\r\n] 2006.286.00:53:04.89#ibcon#*before write, iclass 19, count 2 2006.286.00:53:04.89#ibcon#enter sib2, iclass 19, count 2 2006.286.00:53:04.89#ibcon#flushed, iclass 19, count 2 2006.286.00:53:04.89#ibcon#about to write, iclass 19, count 2 2006.286.00:53:04.89#ibcon#wrote, iclass 19, count 2 2006.286.00:53:04.89#ibcon#about to read 3, iclass 19, count 2 2006.286.00:53:04.92#ibcon#read 3, iclass 19, count 2 2006.286.00:53:04.92#ibcon#about to read 4, iclass 19, count 2 2006.286.00:53:04.92#ibcon#read 4, iclass 19, count 2 2006.286.00:53:04.92#ibcon#about to read 5, iclass 19, count 2 2006.286.00:53:04.92#ibcon#read 5, iclass 19, count 2 2006.286.00:53:04.92#ibcon#about to read 6, iclass 19, count 2 2006.286.00:53:04.92#ibcon#read 6, iclass 19, count 2 2006.286.00:53:04.92#ibcon#end of sib2, iclass 19, count 2 2006.286.00:53:04.92#ibcon#*after write, iclass 19, count 2 2006.286.00:53:04.92#ibcon#*before return 0, iclass 19, count 2 2006.286.00:53:04.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:53:04.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:53:04.92#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.00:53:04.92#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:04.92#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:53:05.04#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:53:05.04#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:53:05.04#ibcon#enter wrdev, iclass 19, count 0 2006.286.00:53:05.04#ibcon#first serial, iclass 19, count 0 2006.286.00:53:05.04#ibcon#enter sib2, iclass 19, count 0 2006.286.00:53:05.04#ibcon#flushed, iclass 19, count 0 2006.286.00:53:05.04#ibcon#about to write, iclass 19, count 0 2006.286.00:53:05.04#ibcon#wrote, iclass 19, count 0 2006.286.00:53:05.04#ibcon#about to read 3, iclass 19, count 0 2006.286.00:53:05.06#ibcon#read 3, iclass 19, count 0 2006.286.00:53:05.06#ibcon#about to read 4, iclass 19, count 0 2006.286.00:53:05.06#ibcon#read 4, iclass 19, count 0 2006.286.00:53:05.06#ibcon#about to read 5, iclass 19, count 0 2006.286.00:53:05.06#ibcon#read 5, iclass 19, count 0 2006.286.00:53:05.06#ibcon#about to read 6, iclass 19, count 0 2006.286.00:53:05.06#ibcon#read 6, iclass 19, count 0 2006.286.00:53:05.06#ibcon#end of sib2, iclass 19, count 0 2006.286.00:53:05.06#ibcon#*mode == 0, iclass 19, count 0 2006.286.00:53:05.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.00:53:05.06#ibcon#[25=USB\r\n] 2006.286.00:53:05.06#ibcon#*before write, iclass 19, count 0 2006.286.00:53:05.06#ibcon#enter sib2, iclass 19, count 0 2006.286.00:53:05.06#ibcon#flushed, iclass 19, count 0 2006.286.00:53:05.06#ibcon#about to write, iclass 19, count 0 2006.286.00:53:05.06#ibcon#wrote, iclass 19, count 0 2006.286.00:53:05.06#ibcon#about to read 3, iclass 19, count 0 2006.286.00:53:05.09#ibcon#read 3, iclass 19, count 0 2006.286.00:53:05.09#ibcon#about to read 4, iclass 19, count 0 2006.286.00:53:05.09#ibcon#read 4, iclass 19, count 0 2006.286.00:53:05.09#ibcon#about to read 5, iclass 19, count 0 2006.286.00:53:05.09#ibcon#read 5, iclass 19, count 0 2006.286.00:53:05.09#ibcon#about to read 6, iclass 19, count 0 2006.286.00:53:05.09#ibcon#read 6, iclass 19, count 0 2006.286.00:53:05.09#ibcon#end of sib2, iclass 19, count 0 2006.286.00:53:05.09#ibcon#*after write, iclass 19, count 0 2006.286.00:53:05.09#ibcon#*before return 0, iclass 19, count 0 2006.286.00:53:05.09#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:53:05.09#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:53:05.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.00:53:05.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.00:53:05.10$vck44/valo=7,864.99 2006.286.00:53:05.10#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.00:53:05.10#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.00:53:05.10#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:05.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:53:05.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:53:05.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:53:05.10#ibcon#enter wrdev, iclass 21, count 0 2006.286.00:53:05.10#ibcon#first serial, iclass 21, count 0 2006.286.00:53:05.10#ibcon#enter sib2, iclass 21, count 0 2006.286.00:53:05.10#ibcon#flushed, iclass 21, count 0 2006.286.00:53:05.10#ibcon#about to write, iclass 21, count 0 2006.286.00:53:05.10#ibcon#wrote, iclass 21, count 0 2006.286.00:53:05.10#ibcon#about to read 3, iclass 21, count 0 2006.286.00:53:05.11#ibcon#read 3, iclass 21, count 0 2006.286.00:53:05.11#ibcon#about to read 4, iclass 21, count 0 2006.286.00:53:05.11#ibcon#read 4, iclass 21, count 0 2006.286.00:53:05.11#ibcon#about to read 5, iclass 21, count 0 2006.286.00:53:05.11#ibcon#read 5, iclass 21, count 0 2006.286.00:53:05.11#ibcon#about to read 6, iclass 21, count 0 2006.286.00:53:05.11#ibcon#read 6, iclass 21, count 0 2006.286.00:53:05.11#ibcon#end of sib2, iclass 21, count 0 2006.286.00:53:05.11#ibcon#*mode == 0, iclass 21, count 0 2006.286.00:53:05.11#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.00:53:05.11#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.00:53:05.11#ibcon#*before write, iclass 21, count 0 2006.286.00:53:05.11#ibcon#enter sib2, iclass 21, count 0 2006.286.00:53:05.11#ibcon#flushed, iclass 21, count 0 2006.286.00:53:05.11#ibcon#about to write, iclass 21, count 0 2006.286.00:53:05.11#ibcon#wrote, iclass 21, count 0 2006.286.00:53:05.11#ibcon#about to read 3, iclass 21, count 0 2006.286.00:53:05.15#ibcon#read 3, iclass 21, count 0 2006.286.00:53:05.15#ibcon#about to read 4, iclass 21, count 0 2006.286.00:53:05.15#ibcon#read 4, iclass 21, count 0 2006.286.00:53:05.15#ibcon#about to read 5, iclass 21, count 0 2006.286.00:53:05.15#ibcon#read 5, iclass 21, count 0 2006.286.00:53:05.15#ibcon#about to read 6, iclass 21, count 0 2006.286.00:53:05.15#ibcon#read 6, iclass 21, count 0 2006.286.00:53:05.15#ibcon#end of sib2, iclass 21, count 0 2006.286.00:53:05.15#ibcon#*after write, iclass 21, count 0 2006.286.00:53:05.15#ibcon#*before return 0, iclass 21, count 0 2006.286.00:53:05.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:53:05.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:53:05.15#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.00:53:05.15#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.00:53:05.16$vck44/va=7,4 2006.286.00:53:05.16#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.00:53:05.16#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.00:53:05.16#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:05.16#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:53:05.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:53:05.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:53:05.20#ibcon#enter wrdev, iclass 23, count 2 2006.286.00:53:05.20#ibcon#first serial, iclass 23, count 2 2006.286.00:53:05.20#ibcon#enter sib2, iclass 23, count 2 2006.286.00:53:05.20#ibcon#flushed, iclass 23, count 2 2006.286.00:53:05.20#ibcon#about to write, iclass 23, count 2 2006.286.00:53:05.20#ibcon#wrote, iclass 23, count 2 2006.286.00:53:05.20#ibcon#about to read 3, iclass 23, count 2 2006.286.00:53:05.22#ibcon#read 3, iclass 23, count 2 2006.286.00:53:05.22#ibcon#about to read 4, iclass 23, count 2 2006.286.00:53:05.22#ibcon#read 4, iclass 23, count 2 2006.286.00:53:05.22#ibcon#about to read 5, iclass 23, count 2 2006.286.00:53:05.22#ibcon#read 5, iclass 23, count 2 2006.286.00:53:05.22#ibcon#about to read 6, iclass 23, count 2 2006.286.00:53:05.22#ibcon#read 6, iclass 23, count 2 2006.286.00:53:05.22#ibcon#end of sib2, iclass 23, count 2 2006.286.00:53:05.22#ibcon#*mode == 0, iclass 23, count 2 2006.286.00:53:05.22#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.00:53:05.22#ibcon#[25=AT07-04\r\n] 2006.286.00:53:05.22#ibcon#*before write, iclass 23, count 2 2006.286.00:53:05.22#ibcon#enter sib2, iclass 23, count 2 2006.286.00:53:05.22#ibcon#flushed, iclass 23, count 2 2006.286.00:53:05.22#ibcon#about to write, iclass 23, count 2 2006.286.00:53:05.22#ibcon#wrote, iclass 23, count 2 2006.286.00:53:05.22#ibcon#about to read 3, iclass 23, count 2 2006.286.00:53:05.25#ibcon#read 3, iclass 23, count 2 2006.286.00:53:05.25#ibcon#about to read 4, iclass 23, count 2 2006.286.00:53:05.25#ibcon#read 4, iclass 23, count 2 2006.286.00:53:05.25#ibcon#about to read 5, iclass 23, count 2 2006.286.00:53:05.25#ibcon#read 5, iclass 23, count 2 2006.286.00:53:05.25#ibcon#about to read 6, iclass 23, count 2 2006.286.00:53:05.25#ibcon#read 6, iclass 23, count 2 2006.286.00:53:05.25#ibcon#end of sib2, iclass 23, count 2 2006.286.00:53:05.25#ibcon#*after write, iclass 23, count 2 2006.286.00:53:05.25#ibcon#*before return 0, iclass 23, count 2 2006.286.00:53:05.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:53:05.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:53:05.25#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.00:53:05.25#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:05.25#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:53:05.37#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:53:05.37#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:53:05.37#ibcon#enter wrdev, iclass 23, count 0 2006.286.00:53:05.37#ibcon#first serial, iclass 23, count 0 2006.286.00:53:05.37#ibcon#enter sib2, iclass 23, count 0 2006.286.00:53:05.37#ibcon#flushed, iclass 23, count 0 2006.286.00:53:05.37#ibcon#about to write, iclass 23, count 0 2006.286.00:53:05.37#ibcon#wrote, iclass 23, count 0 2006.286.00:53:05.37#ibcon#about to read 3, iclass 23, count 0 2006.286.00:53:05.39#ibcon#read 3, iclass 23, count 0 2006.286.00:53:05.39#ibcon#about to read 4, iclass 23, count 0 2006.286.00:53:05.39#ibcon#read 4, iclass 23, count 0 2006.286.00:53:05.39#ibcon#about to read 5, iclass 23, count 0 2006.286.00:53:05.39#ibcon#read 5, iclass 23, count 0 2006.286.00:53:05.39#ibcon#about to read 6, iclass 23, count 0 2006.286.00:53:05.39#ibcon#read 6, iclass 23, count 0 2006.286.00:53:05.39#ibcon#end of sib2, iclass 23, count 0 2006.286.00:53:05.39#ibcon#*mode == 0, iclass 23, count 0 2006.286.00:53:05.39#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.00:53:05.39#ibcon#[25=USB\r\n] 2006.286.00:53:05.39#ibcon#*before write, iclass 23, count 0 2006.286.00:53:05.39#ibcon#enter sib2, iclass 23, count 0 2006.286.00:53:05.39#ibcon#flushed, iclass 23, count 0 2006.286.00:53:05.39#ibcon#about to write, iclass 23, count 0 2006.286.00:53:05.39#ibcon#wrote, iclass 23, count 0 2006.286.00:53:05.39#ibcon#about to read 3, iclass 23, count 0 2006.286.00:53:05.42#ibcon#read 3, iclass 23, count 0 2006.286.00:53:05.42#ibcon#about to read 4, iclass 23, count 0 2006.286.00:53:05.42#ibcon#read 4, iclass 23, count 0 2006.286.00:53:05.42#ibcon#about to read 5, iclass 23, count 0 2006.286.00:53:05.42#ibcon#read 5, iclass 23, count 0 2006.286.00:53:05.42#ibcon#about to read 6, iclass 23, count 0 2006.286.00:53:05.42#ibcon#read 6, iclass 23, count 0 2006.286.00:53:05.42#ibcon#end of sib2, iclass 23, count 0 2006.286.00:53:05.42#ibcon#*after write, iclass 23, count 0 2006.286.00:53:05.42#ibcon#*before return 0, iclass 23, count 0 2006.286.00:53:05.42#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:53:05.42#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:53:05.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.00:53:05.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.00:53:05.43$vck44/valo=8,884.99 2006.286.00:53:05.43#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.00:53:05.43#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.00:53:05.43#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:05.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:53:05.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:53:05.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:53:05.43#ibcon#enter wrdev, iclass 25, count 0 2006.286.00:53:05.43#ibcon#first serial, iclass 25, count 0 2006.286.00:53:05.43#ibcon#enter sib2, iclass 25, count 0 2006.286.00:53:05.43#ibcon#flushed, iclass 25, count 0 2006.286.00:53:05.43#ibcon#about to write, iclass 25, count 0 2006.286.00:53:05.43#ibcon#wrote, iclass 25, count 0 2006.286.00:53:05.43#ibcon#about to read 3, iclass 25, count 0 2006.286.00:53:05.44#ibcon#read 3, iclass 25, count 0 2006.286.00:53:05.44#ibcon#about to read 4, iclass 25, count 0 2006.286.00:53:05.44#ibcon#read 4, iclass 25, count 0 2006.286.00:53:05.44#ibcon#about to read 5, iclass 25, count 0 2006.286.00:53:05.44#ibcon#read 5, iclass 25, count 0 2006.286.00:53:05.44#ibcon#about to read 6, iclass 25, count 0 2006.286.00:53:05.44#ibcon#read 6, iclass 25, count 0 2006.286.00:53:05.44#ibcon#end of sib2, iclass 25, count 0 2006.286.00:53:05.44#ibcon#*mode == 0, iclass 25, count 0 2006.286.00:53:05.44#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.00:53:05.44#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.00:53:05.44#ibcon#*before write, iclass 25, count 0 2006.286.00:53:05.44#ibcon#enter sib2, iclass 25, count 0 2006.286.00:53:05.44#ibcon#flushed, iclass 25, count 0 2006.286.00:53:05.44#ibcon#about to write, iclass 25, count 0 2006.286.00:53:05.44#ibcon#wrote, iclass 25, count 0 2006.286.00:53:05.44#ibcon#about to read 3, iclass 25, count 0 2006.286.00:53:05.48#ibcon#read 3, iclass 25, count 0 2006.286.00:53:05.48#ibcon#about to read 4, iclass 25, count 0 2006.286.00:53:05.48#ibcon#read 4, iclass 25, count 0 2006.286.00:53:05.48#ibcon#about to read 5, iclass 25, count 0 2006.286.00:53:05.48#ibcon#read 5, iclass 25, count 0 2006.286.00:53:05.48#ibcon#about to read 6, iclass 25, count 0 2006.286.00:53:05.48#ibcon#read 6, iclass 25, count 0 2006.286.00:53:05.48#ibcon#end of sib2, iclass 25, count 0 2006.286.00:53:05.48#ibcon#*after write, iclass 25, count 0 2006.286.00:53:05.48#ibcon#*before return 0, iclass 25, count 0 2006.286.00:53:05.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:53:05.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:53:05.48#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.00:53:05.48#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.00:53:05.49$vck44/va=8,3 2006.286.00:53:05.49#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.00:53:05.49#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.00:53:05.49#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:05.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:53:05.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:53:05.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:53:05.53#ibcon#enter wrdev, iclass 27, count 2 2006.286.00:53:05.53#ibcon#first serial, iclass 27, count 2 2006.286.00:53:05.53#ibcon#enter sib2, iclass 27, count 2 2006.286.00:53:05.53#ibcon#flushed, iclass 27, count 2 2006.286.00:53:05.53#ibcon#about to write, iclass 27, count 2 2006.286.00:53:05.53#ibcon#wrote, iclass 27, count 2 2006.286.00:53:05.53#ibcon#about to read 3, iclass 27, count 2 2006.286.00:53:05.55#ibcon#read 3, iclass 27, count 2 2006.286.00:53:05.55#ibcon#about to read 4, iclass 27, count 2 2006.286.00:53:05.55#ibcon#read 4, iclass 27, count 2 2006.286.00:53:05.55#ibcon#about to read 5, iclass 27, count 2 2006.286.00:53:05.55#ibcon#read 5, iclass 27, count 2 2006.286.00:53:05.55#ibcon#about to read 6, iclass 27, count 2 2006.286.00:53:05.55#ibcon#read 6, iclass 27, count 2 2006.286.00:53:05.55#ibcon#end of sib2, iclass 27, count 2 2006.286.00:53:05.55#ibcon#*mode == 0, iclass 27, count 2 2006.286.00:53:05.55#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.00:53:05.55#ibcon#[25=AT08-03\r\n] 2006.286.00:53:05.55#ibcon#*before write, iclass 27, count 2 2006.286.00:53:05.55#ibcon#enter sib2, iclass 27, count 2 2006.286.00:53:05.55#ibcon#flushed, iclass 27, count 2 2006.286.00:53:05.55#ibcon#about to write, iclass 27, count 2 2006.286.00:53:05.55#ibcon#wrote, iclass 27, count 2 2006.286.00:53:05.55#ibcon#about to read 3, iclass 27, count 2 2006.286.00:53:05.58#ibcon#read 3, iclass 27, count 2 2006.286.00:53:05.58#ibcon#about to read 4, iclass 27, count 2 2006.286.00:53:05.58#ibcon#read 4, iclass 27, count 2 2006.286.00:53:05.58#ibcon#about to read 5, iclass 27, count 2 2006.286.00:53:05.58#ibcon#read 5, iclass 27, count 2 2006.286.00:53:05.58#ibcon#about to read 6, iclass 27, count 2 2006.286.00:53:05.58#ibcon#read 6, iclass 27, count 2 2006.286.00:53:05.58#ibcon#end of sib2, iclass 27, count 2 2006.286.00:53:05.58#ibcon#*after write, iclass 27, count 2 2006.286.00:53:05.58#ibcon#*before return 0, iclass 27, count 2 2006.286.00:53:05.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:53:05.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:53:05.58#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.00:53:05.58#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:05.58#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:53:05.70#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:53:05.70#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:53:05.70#ibcon#enter wrdev, iclass 27, count 0 2006.286.00:53:05.70#ibcon#first serial, iclass 27, count 0 2006.286.00:53:05.70#ibcon#enter sib2, iclass 27, count 0 2006.286.00:53:05.70#ibcon#flushed, iclass 27, count 0 2006.286.00:53:05.70#ibcon#about to write, iclass 27, count 0 2006.286.00:53:05.70#ibcon#wrote, iclass 27, count 0 2006.286.00:53:05.70#ibcon#about to read 3, iclass 27, count 0 2006.286.00:53:05.72#ibcon#read 3, iclass 27, count 0 2006.286.00:53:05.72#ibcon#about to read 4, iclass 27, count 0 2006.286.00:53:05.72#ibcon#read 4, iclass 27, count 0 2006.286.00:53:05.72#ibcon#about to read 5, iclass 27, count 0 2006.286.00:53:05.72#ibcon#read 5, iclass 27, count 0 2006.286.00:53:05.72#ibcon#about to read 6, iclass 27, count 0 2006.286.00:53:05.72#ibcon#read 6, iclass 27, count 0 2006.286.00:53:05.72#ibcon#end of sib2, iclass 27, count 0 2006.286.00:53:05.72#ibcon#*mode == 0, iclass 27, count 0 2006.286.00:53:05.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.00:53:05.72#ibcon#[25=USB\r\n] 2006.286.00:53:05.72#ibcon#*before write, iclass 27, count 0 2006.286.00:53:05.72#ibcon#enter sib2, iclass 27, count 0 2006.286.00:53:05.72#ibcon#flushed, iclass 27, count 0 2006.286.00:53:05.72#ibcon#about to write, iclass 27, count 0 2006.286.00:53:05.72#ibcon#wrote, iclass 27, count 0 2006.286.00:53:05.72#ibcon#about to read 3, iclass 27, count 0 2006.286.00:53:05.75#ibcon#read 3, iclass 27, count 0 2006.286.00:53:05.75#ibcon#about to read 4, iclass 27, count 0 2006.286.00:53:05.75#ibcon#read 4, iclass 27, count 0 2006.286.00:53:05.75#ibcon#about to read 5, iclass 27, count 0 2006.286.00:53:05.75#ibcon#read 5, iclass 27, count 0 2006.286.00:53:05.75#ibcon#about to read 6, iclass 27, count 0 2006.286.00:53:05.75#ibcon#read 6, iclass 27, count 0 2006.286.00:53:05.75#ibcon#end of sib2, iclass 27, count 0 2006.286.00:53:05.75#ibcon#*after write, iclass 27, count 0 2006.286.00:53:05.75#ibcon#*before return 0, iclass 27, count 0 2006.286.00:53:05.75#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:53:05.75#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:53:05.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.00:53:05.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.00:53:05.76$vck44/vblo=1,629.99 2006.286.00:53:05.76#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.00:53:05.76#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.00:53:05.76#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:05.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:53:05.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:53:05.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:53:05.76#ibcon#enter wrdev, iclass 29, count 0 2006.286.00:53:05.76#ibcon#first serial, iclass 29, count 0 2006.286.00:53:05.76#ibcon#enter sib2, iclass 29, count 0 2006.286.00:53:05.76#ibcon#flushed, iclass 29, count 0 2006.286.00:53:05.76#ibcon#about to write, iclass 29, count 0 2006.286.00:53:05.76#ibcon#wrote, iclass 29, count 0 2006.286.00:53:05.76#ibcon#about to read 3, iclass 29, count 0 2006.286.00:53:05.77#ibcon#read 3, iclass 29, count 0 2006.286.00:53:05.77#ibcon#about to read 4, iclass 29, count 0 2006.286.00:53:05.77#ibcon#read 4, iclass 29, count 0 2006.286.00:53:05.77#ibcon#about to read 5, iclass 29, count 0 2006.286.00:53:05.77#ibcon#read 5, iclass 29, count 0 2006.286.00:53:05.77#ibcon#about to read 6, iclass 29, count 0 2006.286.00:53:05.77#ibcon#read 6, iclass 29, count 0 2006.286.00:53:05.77#ibcon#end of sib2, iclass 29, count 0 2006.286.00:53:05.77#ibcon#*mode == 0, iclass 29, count 0 2006.286.00:53:05.77#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.00:53:05.77#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.00:53:05.77#ibcon#*before write, iclass 29, count 0 2006.286.00:53:05.77#ibcon#enter sib2, iclass 29, count 0 2006.286.00:53:05.77#ibcon#flushed, iclass 29, count 0 2006.286.00:53:05.77#ibcon#about to write, iclass 29, count 0 2006.286.00:53:05.77#ibcon#wrote, iclass 29, count 0 2006.286.00:53:05.77#ibcon#about to read 3, iclass 29, count 0 2006.286.00:53:05.81#ibcon#read 3, iclass 29, count 0 2006.286.00:53:05.81#ibcon#about to read 4, iclass 29, count 0 2006.286.00:53:05.81#ibcon#read 4, iclass 29, count 0 2006.286.00:53:05.81#ibcon#about to read 5, iclass 29, count 0 2006.286.00:53:05.81#ibcon#read 5, iclass 29, count 0 2006.286.00:53:05.81#ibcon#about to read 6, iclass 29, count 0 2006.286.00:53:05.81#ibcon#read 6, iclass 29, count 0 2006.286.00:53:05.81#ibcon#end of sib2, iclass 29, count 0 2006.286.00:53:05.81#ibcon#*after write, iclass 29, count 0 2006.286.00:53:05.81#ibcon#*before return 0, iclass 29, count 0 2006.286.00:53:05.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:53:05.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:53:05.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.00:53:05.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.00:53:05.82$vck44/vb=1,4 2006.286.00:53:05.82#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.00:53:05.82#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.00:53:05.82#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:05.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:53:05.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:53:05.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:53:05.82#ibcon#enter wrdev, iclass 31, count 2 2006.286.00:53:05.82#ibcon#first serial, iclass 31, count 2 2006.286.00:53:05.82#ibcon#enter sib2, iclass 31, count 2 2006.286.00:53:05.82#ibcon#flushed, iclass 31, count 2 2006.286.00:53:05.82#ibcon#about to write, iclass 31, count 2 2006.286.00:53:05.82#ibcon#wrote, iclass 31, count 2 2006.286.00:53:05.82#ibcon#about to read 3, iclass 31, count 2 2006.286.00:53:05.83#ibcon#read 3, iclass 31, count 2 2006.286.00:53:05.83#ibcon#about to read 4, iclass 31, count 2 2006.286.00:53:05.83#ibcon#read 4, iclass 31, count 2 2006.286.00:53:05.83#ibcon#about to read 5, iclass 31, count 2 2006.286.00:53:05.83#ibcon#read 5, iclass 31, count 2 2006.286.00:53:05.83#ibcon#about to read 6, iclass 31, count 2 2006.286.00:53:05.83#ibcon#read 6, iclass 31, count 2 2006.286.00:53:05.83#ibcon#end of sib2, iclass 31, count 2 2006.286.00:53:05.83#ibcon#*mode == 0, iclass 31, count 2 2006.286.00:53:05.83#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.00:53:05.83#ibcon#[27=AT01-04\r\n] 2006.286.00:53:05.83#ibcon#*before write, iclass 31, count 2 2006.286.00:53:05.83#ibcon#enter sib2, iclass 31, count 2 2006.286.00:53:05.83#ibcon#flushed, iclass 31, count 2 2006.286.00:53:05.83#ibcon#about to write, iclass 31, count 2 2006.286.00:53:05.83#ibcon#wrote, iclass 31, count 2 2006.286.00:53:05.83#ibcon#about to read 3, iclass 31, count 2 2006.286.00:53:05.86#ibcon#read 3, iclass 31, count 2 2006.286.00:53:05.86#ibcon#about to read 4, iclass 31, count 2 2006.286.00:53:05.86#ibcon#read 4, iclass 31, count 2 2006.286.00:53:05.86#ibcon#about to read 5, iclass 31, count 2 2006.286.00:53:05.86#ibcon#read 5, iclass 31, count 2 2006.286.00:53:05.86#ibcon#about to read 6, iclass 31, count 2 2006.286.00:53:05.86#ibcon#read 6, iclass 31, count 2 2006.286.00:53:05.86#ibcon#end of sib2, iclass 31, count 2 2006.286.00:53:05.86#ibcon#*after write, iclass 31, count 2 2006.286.00:53:05.86#ibcon#*before return 0, iclass 31, count 2 2006.286.00:53:05.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:53:05.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.00:53:05.86#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.00:53:05.86#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:05.86#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:53:05.98#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:53:05.98#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:53:05.98#ibcon#enter wrdev, iclass 31, count 0 2006.286.00:53:05.98#ibcon#first serial, iclass 31, count 0 2006.286.00:53:05.98#ibcon#enter sib2, iclass 31, count 0 2006.286.00:53:05.98#ibcon#flushed, iclass 31, count 0 2006.286.00:53:05.98#ibcon#about to write, iclass 31, count 0 2006.286.00:53:05.98#ibcon#wrote, iclass 31, count 0 2006.286.00:53:05.98#ibcon#about to read 3, iclass 31, count 0 2006.286.00:53:06.00#ibcon#read 3, iclass 31, count 0 2006.286.00:53:06.00#ibcon#about to read 4, iclass 31, count 0 2006.286.00:53:06.00#ibcon#read 4, iclass 31, count 0 2006.286.00:53:06.00#ibcon#about to read 5, iclass 31, count 0 2006.286.00:53:06.00#ibcon#read 5, iclass 31, count 0 2006.286.00:53:06.00#ibcon#about to read 6, iclass 31, count 0 2006.286.00:53:06.00#ibcon#read 6, iclass 31, count 0 2006.286.00:53:06.00#ibcon#end of sib2, iclass 31, count 0 2006.286.00:53:06.00#ibcon#*mode == 0, iclass 31, count 0 2006.286.00:53:06.00#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.00:53:06.00#ibcon#[27=USB\r\n] 2006.286.00:53:06.00#ibcon#*before write, iclass 31, count 0 2006.286.00:53:06.00#ibcon#enter sib2, iclass 31, count 0 2006.286.00:53:06.00#ibcon#flushed, iclass 31, count 0 2006.286.00:53:06.00#ibcon#about to write, iclass 31, count 0 2006.286.00:53:06.00#ibcon#wrote, iclass 31, count 0 2006.286.00:53:06.00#ibcon#about to read 3, iclass 31, count 0 2006.286.00:53:06.03#ibcon#read 3, iclass 31, count 0 2006.286.00:53:06.03#ibcon#about to read 4, iclass 31, count 0 2006.286.00:53:06.03#ibcon#read 4, iclass 31, count 0 2006.286.00:53:06.03#ibcon#about to read 5, iclass 31, count 0 2006.286.00:53:06.03#ibcon#read 5, iclass 31, count 0 2006.286.00:53:06.03#ibcon#about to read 6, iclass 31, count 0 2006.286.00:53:06.03#ibcon#read 6, iclass 31, count 0 2006.286.00:53:06.03#ibcon#end of sib2, iclass 31, count 0 2006.286.00:53:06.03#ibcon#*after write, iclass 31, count 0 2006.286.00:53:06.03#ibcon#*before return 0, iclass 31, count 0 2006.286.00:53:06.03#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:53:06.03#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.00:53:06.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.00:53:06.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.00:53:06.04$vck44/vblo=2,634.99 2006.286.00:53:06.04#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.00:53:06.04#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.00:53:06.04#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:06.04#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:53:06.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:53:06.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:53:06.04#ibcon#enter wrdev, iclass 33, count 0 2006.286.00:53:06.04#ibcon#first serial, iclass 33, count 0 2006.286.00:53:06.04#ibcon#enter sib2, iclass 33, count 0 2006.286.00:53:06.04#ibcon#flushed, iclass 33, count 0 2006.286.00:53:06.04#ibcon#about to write, iclass 33, count 0 2006.286.00:53:06.04#ibcon#wrote, iclass 33, count 0 2006.286.00:53:06.04#ibcon#about to read 3, iclass 33, count 0 2006.286.00:53:06.05#ibcon#read 3, iclass 33, count 0 2006.286.00:53:06.05#ibcon#about to read 4, iclass 33, count 0 2006.286.00:53:06.05#ibcon#read 4, iclass 33, count 0 2006.286.00:53:06.05#ibcon#about to read 5, iclass 33, count 0 2006.286.00:53:06.05#ibcon#read 5, iclass 33, count 0 2006.286.00:53:06.05#ibcon#about to read 6, iclass 33, count 0 2006.286.00:53:06.05#ibcon#read 6, iclass 33, count 0 2006.286.00:53:06.05#ibcon#end of sib2, iclass 33, count 0 2006.286.00:53:06.05#ibcon#*mode == 0, iclass 33, count 0 2006.286.00:53:06.05#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.00:53:06.05#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.00:53:06.05#ibcon#*before write, iclass 33, count 0 2006.286.00:53:06.05#ibcon#enter sib2, iclass 33, count 0 2006.286.00:53:06.05#ibcon#flushed, iclass 33, count 0 2006.286.00:53:06.05#ibcon#about to write, iclass 33, count 0 2006.286.00:53:06.05#ibcon#wrote, iclass 33, count 0 2006.286.00:53:06.05#ibcon#about to read 3, iclass 33, count 0 2006.286.00:53:06.09#ibcon#read 3, iclass 33, count 0 2006.286.00:53:06.09#ibcon#about to read 4, iclass 33, count 0 2006.286.00:53:06.09#ibcon#read 4, iclass 33, count 0 2006.286.00:53:06.09#ibcon#about to read 5, iclass 33, count 0 2006.286.00:53:06.09#ibcon#read 5, iclass 33, count 0 2006.286.00:53:06.09#ibcon#about to read 6, iclass 33, count 0 2006.286.00:53:06.09#ibcon#read 6, iclass 33, count 0 2006.286.00:53:06.09#ibcon#end of sib2, iclass 33, count 0 2006.286.00:53:06.09#ibcon#*after write, iclass 33, count 0 2006.286.00:53:06.09#ibcon#*before return 0, iclass 33, count 0 2006.286.00:53:06.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:53:06.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.00:53:06.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.00:53:06.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.00:53:06.10$vck44/vb=2,5 2006.286.00:53:06.10#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.00:53:06.10#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.00:53:06.10#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:06.10#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:53:06.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:53:06.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:53:06.15#ibcon#enter wrdev, iclass 35, count 2 2006.286.00:53:06.15#ibcon#first serial, iclass 35, count 2 2006.286.00:53:06.15#ibcon#enter sib2, iclass 35, count 2 2006.286.00:53:06.15#ibcon#flushed, iclass 35, count 2 2006.286.00:53:06.15#ibcon#about to write, iclass 35, count 2 2006.286.00:53:06.15#ibcon#wrote, iclass 35, count 2 2006.286.00:53:06.15#ibcon#about to read 3, iclass 35, count 2 2006.286.00:53:06.16#ibcon#read 3, iclass 35, count 2 2006.286.00:53:06.16#ibcon#about to read 4, iclass 35, count 2 2006.286.00:53:06.16#ibcon#read 4, iclass 35, count 2 2006.286.00:53:06.16#ibcon#about to read 5, iclass 35, count 2 2006.286.00:53:06.16#ibcon#read 5, iclass 35, count 2 2006.286.00:53:06.16#ibcon#about to read 6, iclass 35, count 2 2006.286.00:53:06.16#ibcon#read 6, iclass 35, count 2 2006.286.00:53:06.16#ibcon#end of sib2, iclass 35, count 2 2006.286.00:53:06.16#ibcon#*mode == 0, iclass 35, count 2 2006.286.00:53:06.16#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.00:53:06.16#ibcon#[27=AT02-05\r\n] 2006.286.00:53:06.16#ibcon#*before write, iclass 35, count 2 2006.286.00:53:06.16#ibcon#enter sib2, iclass 35, count 2 2006.286.00:53:06.16#ibcon#flushed, iclass 35, count 2 2006.286.00:53:06.16#ibcon#about to write, iclass 35, count 2 2006.286.00:53:06.16#ibcon#wrote, iclass 35, count 2 2006.286.00:53:06.16#ibcon#about to read 3, iclass 35, count 2 2006.286.00:53:06.19#ibcon#read 3, iclass 35, count 2 2006.286.00:53:06.19#ibcon#about to read 4, iclass 35, count 2 2006.286.00:53:06.19#ibcon#read 4, iclass 35, count 2 2006.286.00:53:06.19#ibcon#about to read 5, iclass 35, count 2 2006.286.00:53:06.19#ibcon#read 5, iclass 35, count 2 2006.286.00:53:06.19#ibcon#about to read 6, iclass 35, count 2 2006.286.00:53:06.19#ibcon#read 6, iclass 35, count 2 2006.286.00:53:06.19#ibcon#end of sib2, iclass 35, count 2 2006.286.00:53:06.19#ibcon#*after write, iclass 35, count 2 2006.286.00:53:06.19#ibcon#*before return 0, iclass 35, count 2 2006.286.00:53:06.19#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:53:06.19#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.00:53:06.19#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.00:53:06.19#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:06.19#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:53:06.31#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:53:06.31#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:53:06.31#ibcon#enter wrdev, iclass 35, count 0 2006.286.00:53:06.31#ibcon#first serial, iclass 35, count 0 2006.286.00:53:06.31#ibcon#enter sib2, iclass 35, count 0 2006.286.00:53:06.31#ibcon#flushed, iclass 35, count 0 2006.286.00:53:06.31#ibcon#about to write, iclass 35, count 0 2006.286.00:53:06.31#ibcon#wrote, iclass 35, count 0 2006.286.00:53:06.31#ibcon#about to read 3, iclass 35, count 0 2006.286.00:53:06.33#ibcon#read 3, iclass 35, count 0 2006.286.00:53:06.33#ibcon#about to read 4, iclass 35, count 0 2006.286.00:53:06.33#ibcon#read 4, iclass 35, count 0 2006.286.00:53:06.33#ibcon#about to read 5, iclass 35, count 0 2006.286.00:53:06.33#ibcon#read 5, iclass 35, count 0 2006.286.00:53:06.33#ibcon#about to read 6, iclass 35, count 0 2006.286.00:53:06.33#ibcon#read 6, iclass 35, count 0 2006.286.00:53:06.33#ibcon#end of sib2, iclass 35, count 0 2006.286.00:53:06.33#ibcon#*mode == 0, iclass 35, count 0 2006.286.00:53:06.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.00:53:06.33#ibcon#[27=USB\r\n] 2006.286.00:53:06.33#ibcon#*before write, iclass 35, count 0 2006.286.00:53:06.33#ibcon#enter sib2, iclass 35, count 0 2006.286.00:53:06.33#ibcon#flushed, iclass 35, count 0 2006.286.00:53:06.33#ibcon#about to write, iclass 35, count 0 2006.286.00:53:06.33#ibcon#wrote, iclass 35, count 0 2006.286.00:53:06.33#ibcon#about to read 3, iclass 35, count 0 2006.286.00:53:06.36#ibcon#read 3, iclass 35, count 0 2006.286.00:53:06.36#ibcon#about to read 4, iclass 35, count 0 2006.286.00:53:06.36#ibcon#read 4, iclass 35, count 0 2006.286.00:53:06.36#ibcon#about to read 5, iclass 35, count 0 2006.286.00:53:06.36#ibcon#read 5, iclass 35, count 0 2006.286.00:53:06.36#ibcon#about to read 6, iclass 35, count 0 2006.286.00:53:06.36#ibcon#read 6, iclass 35, count 0 2006.286.00:53:06.36#ibcon#end of sib2, iclass 35, count 0 2006.286.00:53:06.36#ibcon#*after write, iclass 35, count 0 2006.286.00:53:06.36#ibcon#*before return 0, iclass 35, count 0 2006.286.00:53:06.36#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:53:06.36#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.00:53:06.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.00:53:06.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.00:53:06.37$vck44/vblo=3,649.99 2006.286.00:53:06.37#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.00:53:06.37#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.00:53:06.37#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:06.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:53:06.37#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:53:06.37#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:53:06.37#ibcon#enter wrdev, iclass 37, count 0 2006.286.00:53:06.37#ibcon#first serial, iclass 37, count 0 2006.286.00:53:06.37#ibcon#enter sib2, iclass 37, count 0 2006.286.00:53:06.37#ibcon#flushed, iclass 37, count 0 2006.286.00:53:06.37#ibcon#about to write, iclass 37, count 0 2006.286.00:53:06.37#ibcon#wrote, iclass 37, count 0 2006.286.00:53:06.37#ibcon#about to read 3, iclass 37, count 0 2006.286.00:53:06.38#ibcon#read 3, iclass 37, count 0 2006.286.00:53:06.38#ibcon#about to read 4, iclass 37, count 0 2006.286.00:53:06.38#ibcon#read 4, iclass 37, count 0 2006.286.00:53:06.38#ibcon#about to read 5, iclass 37, count 0 2006.286.00:53:06.38#ibcon#read 5, iclass 37, count 0 2006.286.00:53:06.38#ibcon#about to read 6, iclass 37, count 0 2006.286.00:53:06.38#ibcon#read 6, iclass 37, count 0 2006.286.00:53:06.38#ibcon#end of sib2, iclass 37, count 0 2006.286.00:53:06.38#ibcon#*mode == 0, iclass 37, count 0 2006.286.00:53:06.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.00:53:06.38#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.00:53:06.38#ibcon#*before write, iclass 37, count 0 2006.286.00:53:06.38#ibcon#enter sib2, iclass 37, count 0 2006.286.00:53:06.38#ibcon#flushed, iclass 37, count 0 2006.286.00:53:06.38#ibcon#about to write, iclass 37, count 0 2006.286.00:53:06.38#ibcon#wrote, iclass 37, count 0 2006.286.00:53:06.38#ibcon#about to read 3, iclass 37, count 0 2006.286.00:53:06.42#ibcon#read 3, iclass 37, count 0 2006.286.00:53:06.42#ibcon#about to read 4, iclass 37, count 0 2006.286.00:53:06.42#ibcon#read 4, iclass 37, count 0 2006.286.00:53:06.42#ibcon#about to read 5, iclass 37, count 0 2006.286.00:53:06.42#ibcon#read 5, iclass 37, count 0 2006.286.00:53:06.42#ibcon#about to read 6, iclass 37, count 0 2006.286.00:53:06.42#ibcon#read 6, iclass 37, count 0 2006.286.00:53:06.42#ibcon#end of sib2, iclass 37, count 0 2006.286.00:53:06.42#ibcon#*after write, iclass 37, count 0 2006.286.00:53:06.42#ibcon#*before return 0, iclass 37, count 0 2006.286.00:53:06.42#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:53:06.42#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.00:53:06.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.00:53:06.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.00:53:06.42$vck44/vb=3,4 2006.286.00:53:06.43#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.00:53:06.43#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.00:53:06.43#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:06.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:53:06.47#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:53:06.47#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:53:06.47#ibcon#enter wrdev, iclass 39, count 2 2006.286.00:53:06.47#ibcon#first serial, iclass 39, count 2 2006.286.00:53:06.47#ibcon#enter sib2, iclass 39, count 2 2006.286.00:53:06.47#ibcon#flushed, iclass 39, count 2 2006.286.00:53:06.47#ibcon#about to write, iclass 39, count 2 2006.286.00:53:06.47#ibcon#wrote, iclass 39, count 2 2006.286.00:53:06.47#ibcon#about to read 3, iclass 39, count 2 2006.286.00:53:06.49#ibcon#read 3, iclass 39, count 2 2006.286.00:53:06.49#ibcon#about to read 4, iclass 39, count 2 2006.286.00:53:06.49#ibcon#read 4, iclass 39, count 2 2006.286.00:53:06.49#ibcon#about to read 5, iclass 39, count 2 2006.286.00:53:06.49#ibcon#read 5, iclass 39, count 2 2006.286.00:53:06.49#ibcon#about to read 6, iclass 39, count 2 2006.286.00:53:06.49#ibcon#read 6, iclass 39, count 2 2006.286.00:53:06.49#ibcon#end of sib2, iclass 39, count 2 2006.286.00:53:06.49#ibcon#*mode == 0, iclass 39, count 2 2006.286.00:53:06.49#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.00:53:06.49#ibcon#[27=AT03-04\r\n] 2006.286.00:53:06.49#ibcon#*before write, iclass 39, count 2 2006.286.00:53:06.49#ibcon#enter sib2, iclass 39, count 2 2006.286.00:53:06.49#ibcon#flushed, iclass 39, count 2 2006.286.00:53:06.49#ibcon#about to write, iclass 39, count 2 2006.286.00:53:06.49#ibcon#wrote, iclass 39, count 2 2006.286.00:53:06.49#ibcon#about to read 3, iclass 39, count 2 2006.286.00:53:06.52#ibcon#read 3, iclass 39, count 2 2006.286.00:53:06.52#ibcon#about to read 4, iclass 39, count 2 2006.286.00:53:06.52#ibcon#read 4, iclass 39, count 2 2006.286.00:53:06.52#ibcon#about to read 5, iclass 39, count 2 2006.286.00:53:06.52#ibcon#read 5, iclass 39, count 2 2006.286.00:53:06.52#ibcon#about to read 6, iclass 39, count 2 2006.286.00:53:06.52#ibcon#read 6, iclass 39, count 2 2006.286.00:53:06.52#ibcon#end of sib2, iclass 39, count 2 2006.286.00:53:06.52#ibcon#*after write, iclass 39, count 2 2006.286.00:53:06.52#ibcon#*before return 0, iclass 39, count 2 2006.286.00:53:06.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:53:06.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.00:53:06.52#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.00:53:06.52#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:06.52#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:53:06.64#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:53:06.64#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:53:06.64#ibcon#enter wrdev, iclass 39, count 0 2006.286.00:53:06.64#ibcon#first serial, iclass 39, count 0 2006.286.00:53:06.64#ibcon#enter sib2, iclass 39, count 0 2006.286.00:53:06.64#ibcon#flushed, iclass 39, count 0 2006.286.00:53:06.64#ibcon#about to write, iclass 39, count 0 2006.286.00:53:06.64#ibcon#wrote, iclass 39, count 0 2006.286.00:53:06.64#ibcon#about to read 3, iclass 39, count 0 2006.286.00:53:06.66#ibcon#read 3, iclass 39, count 0 2006.286.00:53:06.66#ibcon#about to read 4, iclass 39, count 0 2006.286.00:53:06.66#ibcon#read 4, iclass 39, count 0 2006.286.00:53:06.66#ibcon#about to read 5, iclass 39, count 0 2006.286.00:53:06.66#ibcon#read 5, iclass 39, count 0 2006.286.00:53:06.66#ibcon#about to read 6, iclass 39, count 0 2006.286.00:53:06.66#ibcon#read 6, iclass 39, count 0 2006.286.00:53:06.66#ibcon#end of sib2, iclass 39, count 0 2006.286.00:53:06.66#ibcon#*mode == 0, iclass 39, count 0 2006.286.00:53:06.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.00:53:06.66#ibcon#[27=USB\r\n] 2006.286.00:53:06.66#ibcon#*before write, iclass 39, count 0 2006.286.00:53:06.66#ibcon#enter sib2, iclass 39, count 0 2006.286.00:53:06.66#ibcon#flushed, iclass 39, count 0 2006.286.00:53:06.66#ibcon#about to write, iclass 39, count 0 2006.286.00:53:06.66#ibcon#wrote, iclass 39, count 0 2006.286.00:53:06.66#ibcon#about to read 3, iclass 39, count 0 2006.286.00:53:06.69#ibcon#read 3, iclass 39, count 0 2006.286.00:53:06.69#ibcon#about to read 4, iclass 39, count 0 2006.286.00:53:06.69#ibcon#read 4, iclass 39, count 0 2006.286.00:53:06.69#ibcon#about to read 5, iclass 39, count 0 2006.286.00:53:06.69#ibcon#read 5, iclass 39, count 0 2006.286.00:53:06.69#ibcon#about to read 6, iclass 39, count 0 2006.286.00:53:06.69#ibcon#read 6, iclass 39, count 0 2006.286.00:53:06.69#ibcon#end of sib2, iclass 39, count 0 2006.286.00:53:06.69#ibcon#*after write, iclass 39, count 0 2006.286.00:53:06.69#ibcon#*before return 0, iclass 39, count 0 2006.286.00:53:06.69#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:53:06.69#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.00:53:06.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.00:53:06.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.00:53:06.69$vck44/vblo=4,679.99 2006.286.00:53:06.70#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.00:53:06.70#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.00:53:06.70#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:06.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:53:06.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:53:06.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:53:06.70#ibcon#enter wrdev, iclass 3, count 0 2006.286.00:53:06.70#ibcon#first serial, iclass 3, count 0 2006.286.00:53:06.70#ibcon#enter sib2, iclass 3, count 0 2006.286.00:53:06.70#ibcon#flushed, iclass 3, count 0 2006.286.00:53:06.70#ibcon#about to write, iclass 3, count 0 2006.286.00:53:06.70#ibcon#wrote, iclass 3, count 0 2006.286.00:53:06.70#ibcon#about to read 3, iclass 3, count 0 2006.286.00:53:06.71#ibcon#read 3, iclass 3, count 0 2006.286.00:53:06.71#ibcon#about to read 4, iclass 3, count 0 2006.286.00:53:06.71#ibcon#read 4, iclass 3, count 0 2006.286.00:53:06.71#ibcon#about to read 5, iclass 3, count 0 2006.286.00:53:06.71#ibcon#read 5, iclass 3, count 0 2006.286.00:53:06.71#ibcon#about to read 6, iclass 3, count 0 2006.286.00:53:06.71#ibcon#read 6, iclass 3, count 0 2006.286.00:53:06.71#ibcon#end of sib2, iclass 3, count 0 2006.286.00:53:06.71#ibcon#*mode == 0, iclass 3, count 0 2006.286.00:53:06.71#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.00:53:06.71#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.00:53:06.71#ibcon#*before write, iclass 3, count 0 2006.286.00:53:06.71#ibcon#enter sib2, iclass 3, count 0 2006.286.00:53:06.71#ibcon#flushed, iclass 3, count 0 2006.286.00:53:06.71#ibcon#about to write, iclass 3, count 0 2006.286.00:53:06.71#ibcon#wrote, iclass 3, count 0 2006.286.00:53:06.72#ibcon#about to read 3, iclass 3, count 0 2006.286.00:53:06.75#ibcon#read 3, iclass 3, count 0 2006.286.00:53:06.75#ibcon#about to read 4, iclass 3, count 0 2006.286.00:53:06.75#ibcon#read 4, iclass 3, count 0 2006.286.00:53:06.75#ibcon#about to read 5, iclass 3, count 0 2006.286.00:53:06.75#ibcon#read 5, iclass 3, count 0 2006.286.00:53:06.75#ibcon#about to read 6, iclass 3, count 0 2006.286.00:53:06.75#ibcon#read 6, iclass 3, count 0 2006.286.00:53:06.75#ibcon#end of sib2, iclass 3, count 0 2006.286.00:53:06.75#ibcon#*after write, iclass 3, count 0 2006.286.00:53:06.75#ibcon#*before return 0, iclass 3, count 0 2006.286.00:53:06.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:53:06.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.00:53:06.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.00:53:06.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.00:53:06.76$vck44/vb=4,5 2006.286.00:53:06.76#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.00:53:06.76#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.00:53:06.76#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:06.76#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:53:06.76#abcon#<5=/03 3.1 6.5 20.50 841016.3\r\n> 2006.286.00:53:06.78#abcon#{5=INTERFACE CLEAR} 2006.286.00:53:06.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:53:06.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:53:06.80#ibcon#enter wrdev, iclass 6, count 2 2006.286.00:53:06.80#ibcon#first serial, iclass 6, count 2 2006.286.00:53:06.80#ibcon#enter sib2, iclass 6, count 2 2006.286.00:53:06.80#ibcon#flushed, iclass 6, count 2 2006.286.00:53:06.80#ibcon#about to write, iclass 6, count 2 2006.286.00:53:06.80#ibcon#wrote, iclass 6, count 2 2006.286.00:53:06.80#ibcon#about to read 3, iclass 6, count 2 2006.286.00:53:06.82#ibcon#read 3, iclass 6, count 2 2006.286.00:53:06.82#ibcon#about to read 4, iclass 6, count 2 2006.286.00:53:06.82#ibcon#read 4, iclass 6, count 2 2006.286.00:53:06.82#ibcon#about to read 5, iclass 6, count 2 2006.286.00:53:06.82#ibcon#read 5, iclass 6, count 2 2006.286.00:53:06.82#ibcon#about to read 6, iclass 6, count 2 2006.286.00:53:06.82#ibcon#read 6, iclass 6, count 2 2006.286.00:53:06.82#ibcon#end of sib2, iclass 6, count 2 2006.286.00:53:06.82#ibcon#*mode == 0, iclass 6, count 2 2006.286.00:53:06.82#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.00:53:06.82#ibcon#[27=AT04-05\r\n] 2006.286.00:53:06.82#ibcon#*before write, iclass 6, count 2 2006.286.00:53:06.82#ibcon#enter sib2, iclass 6, count 2 2006.286.00:53:06.82#ibcon#flushed, iclass 6, count 2 2006.286.00:53:06.82#ibcon#about to write, iclass 6, count 2 2006.286.00:53:06.82#ibcon#wrote, iclass 6, count 2 2006.286.00:53:06.82#ibcon#about to read 3, iclass 6, count 2 2006.286.00:53:06.84#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:53:06.85#ibcon#read 3, iclass 6, count 2 2006.286.00:53:06.85#ibcon#about to read 4, iclass 6, count 2 2006.286.00:53:06.85#ibcon#read 4, iclass 6, count 2 2006.286.00:53:06.85#ibcon#about to read 5, iclass 6, count 2 2006.286.00:53:06.85#ibcon#read 5, iclass 6, count 2 2006.286.00:53:06.85#ibcon#about to read 6, iclass 6, count 2 2006.286.00:53:06.85#ibcon#read 6, iclass 6, count 2 2006.286.00:53:06.85#ibcon#end of sib2, iclass 6, count 2 2006.286.00:53:06.85#ibcon#*after write, iclass 6, count 2 2006.286.00:53:06.85#ibcon#*before return 0, iclass 6, count 2 2006.286.00:53:06.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:53:06.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.00:53:06.85#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.00:53:06.85#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:06.85#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:53:06.97#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:53:06.97#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:53:06.97#ibcon#enter wrdev, iclass 6, count 0 2006.286.00:53:06.97#ibcon#first serial, iclass 6, count 0 2006.286.00:53:06.97#ibcon#enter sib2, iclass 6, count 0 2006.286.00:53:06.97#ibcon#flushed, iclass 6, count 0 2006.286.00:53:06.97#ibcon#about to write, iclass 6, count 0 2006.286.00:53:06.97#ibcon#wrote, iclass 6, count 0 2006.286.00:53:06.97#ibcon#about to read 3, iclass 6, count 0 2006.286.00:53:06.99#ibcon#read 3, iclass 6, count 0 2006.286.00:53:06.99#ibcon#about to read 4, iclass 6, count 0 2006.286.00:53:06.99#ibcon#read 4, iclass 6, count 0 2006.286.00:53:06.99#ibcon#about to read 5, iclass 6, count 0 2006.286.00:53:06.99#ibcon#read 5, iclass 6, count 0 2006.286.00:53:06.99#ibcon#about to read 6, iclass 6, count 0 2006.286.00:53:06.99#ibcon#read 6, iclass 6, count 0 2006.286.00:53:06.99#ibcon#end of sib2, iclass 6, count 0 2006.286.00:53:06.99#ibcon#*mode == 0, iclass 6, count 0 2006.286.00:53:06.99#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.00:53:06.99#ibcon#[27=USB\r\n] 2006.286.00:53:06.99#ibcon#*before write, iclass 6, count 0 2006.286.00:53:06.99#ibcon#enter sib2, iclass 6, count 0 2006.286.00:53:06.99#ibcon#flushed, iclass 6, count 0 2006.286.00:53:06.99#ibcon#about to write, iclass 6, count 0 2006.286.00:53:06.99#ibcon#wrote, iclass 6, count 0 2006.286.00:53:06.99#ibcon#about to read 3, iclass 6, count 0 2006.286.00:53:07.02#ibcon#read 3, iclass 6, count 0 2006.286.00:53:07.02#ibcon#about to read 4, iclass 6, count 0 2006.286.00:53:07.02#ibcon#read 4, iclass 6, count 0 2006.286.00:53:07.02#ibcon#about to read 5, iclass 6, count 0 2006.286.00:53:07.02#ibcon#read 5, iclass 6, count 0 2006.286.00:53:07.02#ibcon#about to read 6, iclass 6, count 0 2006.286.00:53:07.02#ibcon#read 6, iclass 6, count 0 2006.286.00:53:07.02#ibcon#end of sib2, iclass 6, count 0 2006.286.00:53:07.02#ibcon#*after write, iclass 6, count 0 2006.286.00:53:07.02#ibcon#*before return 0, iclass 6, count 0 2006.286.00:53:07.02#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:53:07.02#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.00:53:07.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.00:53:07.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.00:53:07.03$vck44/vblo=5,709.99 2006.286.00:53:07.03#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.00:53:07.03#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.00:53:07.03#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:07.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:53:07.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:53:07.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:53:07.03#ibcon#enter wrdev, iclass 13, count 0 2006.286.00:53:07.03#ibcon#first serial, iclass 13, count 0 2006.286.00:53:07.03#ibcon#enter sib2, iclass 13, count 0 2006.286.00:53:07.03#ibcon#flushed, iclass 13, count 0 2006.286.00:53:07.03#ibcon#about to write, iclass 13, count 0 2006.286.00:53:07.03#ibcon#wrote, iclass 13, count 0 2006.286.00:53:07.03#ibcon#about to read 3, iclass 13, count 0 2006.286.00:53:07.04#ibcon#read 3, iclass 13, count 0 2006.286.00:53:07.04#ibcon#about to read 4, iclass 13, count 0 2006.286.00:53:07.04#ibcon#read 4, iclass 13, count 0 2006.286.00:53:07.04#ibcon#about to read 5, iclass 13, count 0 2006.286.00:53:07.04#ibcon#read 5, iclass 13, count 0 2006.286.00:53:07.04#ibcon#about to read 6, iclass 13, count 0 2006.286.00:53:07.04#ibcon#read 6, iclass 13, count 0 2006.286.00:53:07.04#ibcon#end of sib2, iclass 13, count 0 2006.286.00:53:07.04#ibcon#*mode == 0, iclass 13, count 0 2006.286.00:53:07.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.00:53:07.04#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.00:53:07.04#ibcon#*before write, iclass 13, count 0 2006.286.00:53:07.04#ibcon#enter sib2, iclass 13, count 0 2006.286.00:53:07.04#ibcon#flushed, iclass 13, count 0 2006.286.00:53:07.04#ibcon#about to write, iclass 13, count 0 2006.286.00:53:07.04#ibcon#wrote, iclass 13, count 0 2006.286.00:53:07.04#ibcon#about to read 3, iclass 13, count 0 2006.286.00:53:07.08#ibcon#read 3, iclass 13, count 0 2006.286.00:53:07.08#ibcon#about to read 4, iclass 13, count 0 2006.286.00:53:07.08#ibcon#read 4, iclass 13, count 0 2006.286.00:53:07.08#ibcon#about to read 5, iclass 13, count 0 2006.286.00:53:07.08#ibcon#read 5, iclass 13, count 0 2006.286.00:53:07.08#ibcon#about to read 6, iclass 13, count 0 2006.286.00:53:07.08#ibcon#read 6, iclass 13, count 0 2006.286.00:53:07.08#ibcon#end of sib2, iclass 13, count 0 2006.286.00:53:07.08#ibcon#*after write, iclass 13, count 0 2006.286.00:53:07.08#ibcon#*before return 0, iclass 13, count 0 2006.286.00:53:07.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:53:07.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.00:53:07.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.00:53:07.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.00:53:07.09$vck44/vb=5,4 2006.286.00:53:07.09#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.00:53:07.09#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.00:53:07.09#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:07.09#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:53:07.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:53:07.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:53:07.13#ibcon#enter wrdev, iclass 15, count 2 2006.286.00:53:07.13#ibcon#first serial, iclass 15, count 2 2006.286.00:53:07.13#ibcon#enter sib2, iclass 15, count 2 2006.286.00:53:07.13#ibcon#flushed, iclass 15, count 2 2006.286.00:53:07.13#ibcon#about to write, iclass 15, count 2 2006.286.00:53:07.13#ibcon#wrote, iclass 15, count 2 2006.286.00:53:07.13#ibcon#about to read 3, iclass 15, count 2 2006.286.00:53:07.15#ibcon#read 3, iclass 15, count 2 2006.286.00:53:07.15#ibcon#about to read 4, iclass 15, count 2 2006.286.00:53:07.15#ibcon#read 4, iclass 15, count 2 2006.286.00:53:07.15#ibcon#about to read 5, iclass 15, count 2 2006.286.00:53:07.15#ibcon#read 5, iclass 15, count 2 2006.286.00:53:07.15#ibcon#about to read 6, iclass 15, count 2 2006.286.00:53:07.15#ibcon#read 6, iclass 15, count 2 2006.286.00:53:07.15#ibcon#end of sib2, iclass 15, count 2 2006.286.00:53:07.15#ibcon#*mode == 0, iclass 15, count 2 2006.286.00:53:07.15#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.00:53:07.15#ibcon#[27=AT05-04\r\n] 2006.286.00:53:07.15#ibcon#*before write, iclass 15, count 2 2006.286.00:53:07.15#ibcon#enter sib2, iclass 15, count 2 2006.286.00:53:07.15#ibcon#flushed, iclass 15, count 2 2006.286.00:53:07.15#ibcon#about to write, iclass 15, count 2 2006.286.00:53:07.15#ibcon#wrote, iclass 15, count 2 2006.286.00:53:07.15#ibcon#about to read 3, iclass 15, count 2 2006.286.00:53:07.18#ibcon#read 3, iclass 15, count 2 2006.286.00:53:07.18#ibcon#about to read 4, iclass 15, count 2 2006.286.00:53:07.18#ibcon#read 4, iclass 15, count 2 2006.286.00:53:07.18#ibcon#about to read 5, iclass 15, count 2 2006.286.00:53:07.18#ibcon#read 5, iclass 15, count 2 2006.286.00:53:07.18#ibcon#about to read 6, iclass 15, count 2 2006.286.00:53:07.18#ibcon#read 6, iclass 15, count 2 2006.286.00:53:07.18#ibcon#end of sib2, iclass 15, count 2 2006.286.00:53:07.18#ibcon#*after write, iclass 15, count 2 2006.286.00:53:07.18#ibcon#*before return 0, iclass 15, count 2 2006.286.00:53:07.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:53:07.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.00:53:07.18#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.00:53:07.18#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:07.18#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:53:07.30#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:53:07.30#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:53:07.30#ibcon#enter wrdev, iclass 15, count 0 2006.286.00:53:07.30#ibcon#first serial, iclass 15, count 0 2006.286.00:53:07.30#ibcon#enter sib2, iclass 15, count 0 2006.286.00:53:07.30#ibcon#flushed, iclass 15, count 0 2006.286.00:53:07.30#ibcon#about to write, iclass 15, count 0 2006.286.00:53:07.30#ibcon#wrote, iclass 15, count 0 2006.286.00:53:07.30#ibcon#about to read 3, iclass 15, count 0 2006.286.00:53:07.32#ibcon#read 3, iclass 15, count 0 2006.286.00:53:07.32#ibcon#about to read 4, iclass 15, count 0 2006.286.00:53:07.32#ibcon#read 4, iclass 15, count 0 2006.286.00:53:07.32#ibcon#about to read 5, iclass 15, count 0 2006.286.00:53:07.32#ibcon#read 5, iclass 15, count 0 2006.286.00:53:07.32#ibcon#about to read 6, iclass 15, count 0 2006.286.00:53:07.32#ibcon#read 6, iclass 15, count 0 2006.286.00:53:07.32#ibcon#end of sib2, iclass 15, count 0 2006.286.00:53:07.32#ibcon#*mode == 0, iclass 15, count 0 2006.286.00:53:07.32#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.00:53:07.32#ibcon#[27=USB\r\n] 2006.286.00:53:07.32#ibcon#*before write, iclass 15, count 0 2006.286.00:53:07.32#ibcon#enter sib2, iclass 15, count 0 2006.286.00:53:07.32#ibcon#flushed, iclass 15, count 0 2006.286.00:53:07.32#ibcon#about to write, iclass 15, count 0 2006.286.00:53:07.32#ibcon#wrote, iclass 15, count 0 2006.286.00:53:07.32#ibcon#about to read 3, iclass 15, count 0 2006.286.00:53:07.35#ibcon#read 3, iclass 15, count 0 2006.286.00:53:07.35#ibcon#about to read 4, iclass 15, count 0 2006.286.00:53:07.35#ibcon#read 4, iclass 15, count 0 2006.286.00:53:07.35#ibcon#about to read 5, iclass 15, count 0 2006.286.00:53:07.35#ibcon#read 5, iclass 15, count 0 2006.286.00:53:07.35#ibcon#about to read 6, iclass 15, count 0 2006.286.00:53:07.35#ibcon#read 6, iclass 15, count 0 2006.286.00:53:07.35#ibcon#end of sib2, iclass 15, count 0 2006.286.00:53:07.35#ibcon#*after write, iclass 15, count 0 2006.286.00:53:07.35#ibcon#*before return 0, iclass 15, count 0 2006.286.00:53:07.35#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:53:07.35#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.00:53:07.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.00:53:07.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.00:53:07.35$vck44/vblo=6,719.99 2006.286.00:53:07.36#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.00:53:07.36#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.00:53:07.36#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:07.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:53:07.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:53:07.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:53:07.36#ibcon#enter wrdev, iclass 17, count 0 2006.286.00:53:07.36#ibcon#first serial, iclass 17, count 0 2006.286.00:53:07.36#ibcon#enter sib2, iclass 17, count 0 2006.286.00:53:07.36#ibcon#flushed, iclass 17, count 0 2006.286.00:53:07.36#ibcon#about to write, iclass 17, count 0 2006.286.00:53:07.36#ibcon#wrote, iclass 17, count 0 2006.286.00:53:07.36#ibcon#about to read 3, iclass 17, count 0 2006.286.00:53:07.37#ibcon#read 3, iclass 17, count 0 2006.286.00:53:07.37#ibcon#about to read 4, iclass 17, count 0 2006.286.00:53:07.37#ibcon#read 4, iclass 17, count 0 2006.286.00:53:07.37#ibcon#about to read 5, iclass 17, count 0 2006.286.00:53:07.37#ibcon#read 5, iclass 17, count 0 2006.286.00:53:07.37#ibcon#about to read 6, iclass 17, count 0 2006.286.00:53:07.37#ibcon#read 6, iclass 17, count 0 2006.286.00:53:07.37#ibcon#end of sib2, iclass 17, count 0 2006.286.00:53:07.37#ibcon#*mode == 0, iclass 17, count 0 2006.286.00:53:07.37#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.00:53:07.37#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.00:53:07.37#ibcon#*before write, iclass 17, count 0 2006.286.00:53:07.37#ibcon#enter sib2, iclass 17, count 0 2006.286.00:53:07.37#ibcon#flushed, iclass 17, count 0 2006.286.00:53:07.37#ibcon#about to write, iclass 17, count 0 2006.286.00:53:07.37#ibcon#wrote, iclass 17, count 0 2006.286.00:53:07.37#ibcon#about to read 3, iclass 17, count 0 2006.286.00:53:07.41#ibcon#read 3, iclass 17, count 0 2006.286.00:53:07.41#ibcon#about to read 4, iclass 17, count 0 2006.286.00:53:07.41#ibcon#read 4, iclass 17, count 0 2006.286.00:53:07.41#ibcon#about to read 5, iclass 17, count 0 2006.286.00:53:07.41#ibcon#read 5, iclass 17, count 0 2006.286.00:53:07.41#ibcon#about to read 6, iclass 17, count 0 2006.286.00:53:07.41#ibcon#read 6, iclass 17, count 0 2006.286.00:53:07.41#ibcon#end of sib2, iclass 17, count 0 2006.286.00:53:07.41#ibcon#*after write, iclass 17, count 0 2006.286.00:53:07.41#ibcon#*before return 0, iclass 17, count 0 2006.286.00:53:07.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:53:07.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.00:53:07.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.00:53:07.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.00:53:07.41$vck44/vb=6,3 2006.286.00:53:07.42#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.00:53:07.42#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.00:53:07.42#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:07.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:53:07.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:53:07.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:53:07.46#ibcon#enter wrdev, iclass 19, count 2 2006.286.00:53:07.46#ibcon#first serial, iclass 19, count 2 2006.286.00:53:07.46#ibcon#enter sib2, iclass 19, count 2 2006.286.00:53:07.46#ibcon#flushed, iclass 19, count 2 2006.286.00:53:07.46#ibcon#about to write, iclass 19, count 2 2006.286.00:53:07.46#ibcon#wrote, iclass 19, count 2 2006.286.00:53:07.46#ibcon#about to read 3, iclass 19, count 2 2006.286.00:53:07.48#ibcon#read 3, iclass 19, count 2 2006.286.00:53:07.48#ibcon#about to read 4, iclass 19, count 2 2006.286.00:53:07.48#ibcon#read 4, iclass 19, count 2 2006.286.00:53:07.48#ibcon#about to read 5, iclass 19, count 2 2006.286.00:53:07.48#ibcon#read 5, iclass 19, count 2 2006.286.00:53:07.48#ibcon#about to read 6, iclass 19, count 2 2006.286.00:53:07.48#ibcon#read 6, iclass 19, count 2 2006.286.00:53:07.48#ibcon#end of sib2, iclass 19, count 2 2006.286.00:53:07.48#ibcon#*mode == 0, iclass 19, count 2 2006.286.00:53:07.48#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.00:53:07.48#ibcon#[27=AT06-03\r\n] 2006.286.00:53:07.48#ibcon#*before write, iclass 19, count 2 2006.286.00:53:07.48#ibcon#enter sib2, iclass 19, count 2 2006.286.00:53:07.48#ibcon#flushed, iclass 19, count 2 2006.286.00:53:07.48#ibcon#about to write, iclass 19, count 2 2006.286.00:53:07.48#ibcon#wrote, iclass 19, count 2 2006.286.00:53:07.48#ibcon#about to read 3, iclass 19, count 2 2006.286.00:53:07.51#ibcon#read 3, iclass 19, count 2 2006.286.00:53:07.51#ibcon#about to read 4, iclass 19, count 2 2006.286.00:53:07.51#ibcon#read 4, iclass 19, count 2 2006.286.00:53:07.51#ibcon#about to read 5, iclass 19, count 2 2006.286.00:53:07.51#ibcon#read 5, iclass 19, count 2 2006.286.00:53:07.51#ibcon#about to read 6, iclass 19, count 2 2006.286.00:53:07.51#ibcon#read 6, iclass 19, count 2 2006.286.00:53:07.51#ibcon#end of sib2, iclass 19, count 2 2006.286.00:53:07.51#ibcon#*after write, iclass 19, count 2 2006.286.00:53:07.51#ibcon#*before return 0, iclass 19, count 2 2006.286.00:53:07.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:53:07.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.00:53:07.51#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.00:53:07.51#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:07.51#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:53:07.63#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:53:07.63#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:53:07.63#ibcon#enter wrdev, iclass 19, count 0 2006.286.00:53:07.63#ibcon#first serial, iclass 19, count 0 2006.286.00:53:07.63#ibcon#enter sib2, iclass 19, count 0 2006.286.00:53:07.63#ibcon#flushed, iclass 19, count 0 2006.286.00:53:07.63#ibcon#about to write, iclass 19, count 0 2006.286.00:53:07.63#ibcon#wrote, iclass 19, count 0 2006.286.00:53:07.63#ibcon#about to read 3, iclass 19, count 0 2006.286.00:53:07.65#ibcon#read 3, iclass 19, count 0 2006.286.00:53:07.65#ibcon#about to read 4, iclass 19, count 0 2006.286.00:53:07.65#ibcon#read 4, iclass 19, count 0 2006.286.00:53:07.65#ibcon#about to read 5, iclass 19, count 0 2006.286.00:53:07.65#ibcon#read 5, iclass 19, count 0 2006.286.00:53:07.65#ibcon#about to read 6, iclass 19, count 0 2006.286.00:53:07.65#ibcon#read 6, iclass 19, count 0 2006.286.00:53:07.65#ibcon#end of sib2, iclass 19, count 0 2006.286.00:53:07.65#ibcon#*mode == 0, iclass 19, count 0 2006.286.00:53:07.65#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.00:53:07.65#ibcon#[27=USB\r\n] 2006.286.00:53:07.65#ibcon#*before write, iclass 19, count 0 2006.286.00:53:07.65#ibcon#enter sib2, iclass 19, count 0 2006.286.00:53:07.65#ibcon#flushed, iclass 19, count 0 2006.286.00:53:07.65#ibcon#about to write, iclass 19, count 0 2006.286.00:53:07.65#ibcon#wrote, iclass 19, count 0 2006.286.00:53:07.65#ibcon#about to read 3, iclass 19, count 0 2006.286.00:53:07.68#ibcon#read 3, iclass 19, count 0 2006.286.00:53:07.68#ibcon#about to read 4, iclass 19, count 0 2006.286.00:53:07.68#ibcon#read 4, iclass 19, count 0 2006.286.00:53:07.68#ibcon#about to read 5, iclass 19, count 0 2006.286.00:53:07.68#ibcon#read 5, iclass 19, count 0 2006.286.00:53:07.68#ibcon#about to read 6, iclass 19, count 0 2006.286.00:53:07.68#ibcon#read 6, iclass 19, count 0 2006.286.00:53:07.68#ibcon#end of sib2, iclass 19, count 0 2006.286.00:53:07.68#ibcon#*after write, iclass 19, count 0 2006.286.00:53:07.68#ibcon#*before return 0, iclass 19, count 0 2006.286.00:53:07.68#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:53:07.68#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.00:53:07.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.00:53:07.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.00:53:07.68$vck44/vblo=7,734.99 2006.286.00:53:07.69#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.00:53:07.69#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.00:53:07.69#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:07.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:53:07.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:53:07.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:53:07.69#ibcon#enter wrdev, iclass 21, count 0 2006.286.00:53:07.69#ibcon#first serial, iclass 21, count 0 2006.286.00:53:07.69#ibcon#enter sib2, iclass 21, count 0 2006.286.00:53:07.69#ibcon#flushed, iclass 21, count 0 2006.286.00:53:07.69#ibcon#about to write, iclass 21, count 0 2006.286.00:53:07.69#ibcon#wrote, iclass 21, count 0 2006.286.00:53:07.69#ibcon#about to read 3, iclass 21, count 0 2006.286.00:53:07.70#ibcon#read 3, iclass 21, count 0 2006.286.00:53:07.70#ibcon#about to read 4, iclass 21, count 0 2006.286.00:53:07.70#ibcon#read 4, iclass 21, count 0 2006.286.00:53:07.70#ibcon#about to read 5, iclass 21, count 0 2006.286.00:53:07.70#ibcon#read 5, iclass 21, count 0 2006.286.00:53:07.70#ibcon#about to read 6, iclass 21, count 0 2006.286.00:53:07.70#ibcon#read 6, iclass 21, count 0 2006.286.00:53:07.70#ibcon#end of sib2, iclass 21, count 0 2006.286.00:53:07.70#ibcon#*mode == 0, iclass 21, count 0 2006.286.00:53:07.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.00:53:07.70#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.00:53:07.70#ibcon#*before write, iclass 21, count 0 2006.286.00:53:07.70#ibcon#enter sib2, iclass 21, count 0 2006.286.00:53:07.70#ibcon#flushed, iclass 21, count 0 2006.286.00:53:07.70#ibcon#about to write, iclass 21, count 0 2006.286.00:53:07.70#ibcon#wrote, iclass 21, count 0 2006.286.00:53:07.70#ibcon#about to read 3, iclass 21, count 0 2006.286.00:53:07.74#ibcon#read 3, iclass 21, count 0 2006.286.00:53:07.74#ibcon#about to read 4, iclass 21, count 0 2006.286.00:53:07.74#ibcon#read 4, iclass 21, count 0 2006.286.00:53:07.74#ibcon#about to read 5, iclass 21, count 0 2006.286.00:53:07.74#ibcon#read 5, iclass 21, count 0 2006.286.00:53:07.74#ibcon#about to read 6, iclass 21, count 0 2006.286.00:53:07.74#ibcon#read 6, iclass 21, count 0 2006.286.00:53:07.74#ibcon#end of sib2, iclass 21, count 0 2006.286.00:53:07.74#ibcon#*after write, iclass 21, count 0 2006.286.00:53:07.74#ibcon#*before return 0, iclass 21, count 0 2006.286.00:53:07.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:53:07.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.00:53:07.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.00:53:07.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.00:53:07.74$vck44/vb=7,4 2006.286.00:53:07.75#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.00:53:07.75#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.00:53:07.75#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:07.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:53:07.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:53:07.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:53:07.79#ibcon#enter wrdev, iclass 23, count 2 2006.286.00:53:07.79#ibcon#first serial, iclass 23, count 2 2006.286.00:53:07.79#ibcon#enter sib2, iclass 23, count 2 2006.286.00:53:07.79#ibcon#flushed, iclass 23, count 2 2006.286.00:53:07.79#ibcon#about to write, iclass 23, count 2 2006.286.00:53:07.79#ibcon#wrote, iclass 23, count 2 2006.286.00:53:07.79#ibcon#about to read 3, iclass 23, count 2 2006.286.00:53:07.81#ibcon#read 3, iclass 23, count 2 2006.286.00:53:07.81#ibcon#about to read 4, iclass 23, count 2 2006.286.00:53:07.81#ibcon#read 4, iclass 23, count 2 2006.286.00:53:07.81#ibcon#about to read 5, iclass 23, count 2 2006.286.00:53:07.81#ibcon#read 5, iclass 23, count 2 2006.286.00:53:07.81#ibcon#about to read 6, iclass 23, count 2 2006.286.00:53:07.81#ibcon#read 6, iclass 23, count 2 2006.286.00:53:07.81#ibcon#end of sib2, iclass 23, count 2 2006.286.00:53:07.81#ibcon#*mode == 0, iclass 23, count 2 2006.286.00:53:07.81#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.00:53:07.81#ibcon#[27=AT07-04\r\n] 2006.286.00:53:07.81#ibcon#*before write, iclass 23, count 2 2006.286.00:53:07.81#ibcon#enter sib2, iclass 23, count 2 2006.286.00:53:07.81#ibcon#flushed, iclass 23, count 2 2006.286.00:53:07.81#ibcon#about to write, iclass 23, count 2 2006.286.00:53:07.81#ibcon#wrote, iclass 23, count 2 2006.286.00:53:07.81#ibcon#about to read 3, iclass 23, count 2 2006.286.00:53:07.84#ibcon#read 3, iclass 23, count 2 2006.286.00:53:07.84#ibcon#about to read 4, iclass 23, count 2 2006.286.00:53:07.84#ibcon#read 4, iclass 23, count 2 2006.286.00:53:07.84#ibcon#about to read 5, iclass 23, count 2 2006.286.00:53:07.84#ibcon#read 5, iclass 23, count 2 2006.286.00:53:07.84#ibcon#about to read 6, iclass 23, count 2 2006.286.00:53:07.84#ibcon#read 6, iclass 23, count 2 2006.286.00:53:07.84#ibcon#end of sib2, iclass 23, count 2 2006.286.00:53:07.84#ibcon#*after write, iclass 23, count 2 2006.286.00:53:07.84#ibcon#*before return 0, iclass 23, count 2 2006.286.00:53:07.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:53:07.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.00:53:07.84#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.00:53:07.84#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:07.84#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:53:07.96#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:53:07.96#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:53:07.96#ibcon#enter wrdev, iclass 23, count 0 2006.286.00:53:07.96#ibcon#first serial, iclass 23, count 0 2006.286.00:53:07.96#ibcon#enter sib2, iclass 23, count 0 2006.286.00:53:07.96#ibcon#flushed, iclass 23, count 0 2006.286.00:53:07.96#ibcon#about to write, iclass 23, count 0 2006.286.00:53:07.96#ibcon#wrote, iclass 23, count 0 2006.286.00:53:07.96#ibcon#about to read 3, iclass 23, count 0 2006.286.00:53:07.98#ibcon#read 3, iclass 23, count 0 2006.286.00:53:07.98#ibcon#about to read 4, iclass 23, count 0 2006.286.00:53:07.98#ibcon#read 4, iclass 23, count 0 2006.286.00:53:07.98#ibcon#about to read 5, iclass 23, count 0 2006.286.00:53:07.98#ibcon#read 5, iclass 23, count 0 2006.286.00:53:07.98#ibcon#about to read 6, iclass 23, count 0 2006.286.00:53:07.98#ibcon#read 6, iclass 23, count 0 2006.286.00:53:07.98#ibcon#end of sib2, iclass 23, count 0 2006.286.00:53:07.98#ibcon#*mode == 0, iclass 23, count 0 2006.286.00:53:07.98#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.00:53:07.98#ibcon#[27=USB\r\n] 2006.286.00:53:07.98#ibcon#*before write, iclass 23, count 0 2006.286.00:53:07.98#ibcon#enter sib2, iclass 23, count 0 2006.286.00:53:07.98#ibcon#flushed, iclass 23, count 0 2006.286.00:53:07.98#ibcon#about to write, iclass 23, count 0 2006.286.00:53:07.98#ibcon#wrote, iclass 23, count 0 2006.286.00:53:07.98#ibcon#about to read 3, iclass 23, count 0 2006.286.00:53:08.01#ibcon#read 3, iclass 23, count 0 2006.286.00:53:08.01#ibcon#about to read 4, iclass 23, count 0 2006.286.00:53:08.01#ibcon#read 4, iclass 23, count 0 2006.286.00:53:08.01#ibcon#about to read 5, iclass 23, count 0 2006.286.00:53:08.01#ibcon#read 5, iclass 23, count 0 2006.286.00:53:08.01#ibcon#about to read 6, iclass 23, count 0 2006.286.00:53:08.01#ibcon#read 6, iclass 23, count 0 2006.286.00:53:08.01#ibcon#end of sib2, iclass 23, count 0 2006.286.00:53:08.01#ibcon#*after write, iclass 23, count 0 2006.286.00:53:08.01#ibcon#*before return 0, iclass 23, count 0 2006.286.00:53:08.01#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:53:08.01#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.00:53:08.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.00:53:08.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.00:53:08.02$vck44/vblo=8,744.99 2006.286.00:53:08.02#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.00:53:08.02#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.00:53:08.02#ibcon#ireg 17 cls_cnt 0 2006.286.00:53:08.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:53:08.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:53:08.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:53:08.02#ibcon#enter wrdev, iclass 25, count 0 2006.286.00:53:08.02#ibcon#first serial, iclass 25, count 0 2006.286.00:53:08.02#ibcon#enter sib2, iclass 25, count 0 2006.286.00:53:08.02#ibcon#flushed, iclass 25, count 0 2006.286.00:53:08.02#ibcon#about to write, iclass 25, count 0 2006.286.00:53:08.02#ibcon#wrote, iclass 25, count 0 2006.286.00:53:08.02#ibcon#about to read 3, iclass 25, count 0 2006.286.00:53:08.03#ibcon#read 3, iclass 25, count 0 2006.286.00:53:08.03#ibcon#about to read 4, iclass 25, count 0 2006.286.00:53:08.03#ibcon#read 4, iclass 25, count 0 2006.286.00:53:08.03#ibcon#about to read 5, iclass 25, count 0 2006.286.00:53:08.03#ibcon#read 5, iclass 25, count 0 2006.286.00:53:08.03#ibcon#about to read 6, iclass 25, count 0 2006.286.00:53:08.03#ibcon#read 6, iclass 25, count 0 2006.286.00:53:08.03#ibcon#end of sib2, iclass 25, count 0 2006.286.00:53:08.03#ibcon#*mode == 0, iclass 25, count 0 2006.286.00:53:08.03#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.00:53:08.03#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.00:53:08.03#ibcon#*before write, iclass 25, count 0 2006.286.00:53:08.03#ibcon#enter sib2, iclass 25, count 0 2006.286.00:53:08.03#ibcon#flushed, iclass 25, count 0 2006.286.00:53:08.03#ibcon#about to write, iclass 25, count 0 2006.286.00:53:08.03#ibcon#wrote, iclass 25, count 0 2006.286.00:53:08.03#ibcon#about to read 3, iclass 25, count 0 2006.286.00:53:08.07#ibcon#read 3, iclass 25, count 0 2006.286.00:53:08.07#ibcon#about to read 4, iclass 25, count 0 2006.286.00:53:08.07#ibcon#read 4, iclass 25, count 0 2006.286.00:53:08.07#ibcon#about to read 5, iclass 25, count 0 2006.286.00:53:08.07#ibcon#read 5, iclass 25, count 0 2006.286.00:53:08.07#ibcon#about to read 6, iclass 25, count 0 2006.286.00:53:08.07#ibcon#read 6, iclass 25, count 0 2006.286.00:53:08.07#ibcon#end of sib2, iclass 25, count 0 2006.286.00:53:08.07#ibcon#*after write, iclass 25, count 0 2006.286.00:53:08.07#ibcon#*before return 0, iclass 25, count 0 2006.286.00:53:08.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:53:08.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.00:53:08.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.00:53:08.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.00:53:08.08$vck44/vb=8,4 2006.286.00:53:08.08#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.00:53:08.08#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.00:53:08.08#ibcon#ireg 11 cls_cnt 2 2006.286.00:53:08.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:53:08.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:53:08.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:53:08.12#ibcon#enter wrdev, iclass 27, count 2 2006.286.00:53:08.12#ibcon#first serial, iclass 27, count 2 2006.286.00:53:08.12#ibcon#enter sib2, iclass 27, count 2 2006.286.00:53:08.12#ibcon#flushed, iclass 27, count 2 2006.286.00:53:08.12#ibcon#about to write, iclass 27, count 2 2006.286.00:53:08.12#ibcon#wrote, iclass 27, count 2 2006.286.00:53:08.12#ibcon#about to read 3, iclass 27, count 2 2006.286.00:53:08.14#ibcon#read 3, iclass 27, count 2 2006.286.00:53:08.14#ibcon#about to read 4, iclass 27, count 2 2006.286.00:53:08.14#ibcon#read 4, iclass 27, count 2 2006.286.00:53:08.14#ibcon#about to read 5, iclass 27, count 2 2006.286.00:53:08.14#ibcon#read 5, iclass 27, count 2 2006.286.00:53:08.14#ibcon#about to read 6, iclass 27, count 2 2006.286.00:53:08.14#ibcon#read 6, iclass 27, count 2 2006.286.00:53:08.14#ibcon#end of sib2, iclass 27, count 2 2006.286.00:53:08.14#ibcon#*mode == 0, iclass 27, count 2 2006.286.00:53:08.14#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.00:53:08.14#ibcon#[27=AT08-04\r\n] 2006.286.00:53:08.14#ibcon#*before write, iclass 27, count 2 2006.286.00:53:08.14#ibcon#enter sib2, iclass 27, count 2 2006.286.00:53:08.14#ibcon#flushed, iclass 27, count 2 2006.286.00:53:08.14#ibcon#about to write, iclass 27, count 2 2006.286.00:53:08.14#ibcon#wrote, iclass 27, count 2 2006.286.00:53:08.14#ibcon#about to read 3, iclass 27, count 2 2006.286.00:53:08.17#ibcon#read 3, iclass 27, count 2 2006.286.00:53:08.17#ibcon#about to read 4, iclass 27, count 2 2006.286.00:53:08.17#ibcon#read 4, iclass 27, count 2 2006.286.00:53:08.17#ibcon#about to read 5, iclass 27, count 2 2006.286.00:53:08.17#ibcon#read 5, iclass 27, count 2 2006.286.00:53:08.17#ibcon#about to read 6, iclass 27, count 2 2006.286.00:53:08.17#ibcon#read 6, iclass 27, count 2 2006.286.00:53:08.17#ibcon#end of sib2, iclass 27, count 2 2006.286.00:53:08.17#ibcon#*after write, iclass 27, count 2 2006.286.00:53:08.17#ibcon#*before return 0, iclass 27, count 2 2006.286.00:53:08.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:53:08.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.00:53:08.17#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.00:53:08.17#ibcon#ireg 7 cls_cnt 0 2006.286.00:53:08.17#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:53:08.29#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:53:08.29#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:53:08.29#ibcon#enter wrdev, iclass 27, count 0 2006.286.00:53:08.29#ibcon#first serial, iclass 27, count 0 2006.286.00:53:08.29#ibcon#enter sib2, iclass 27, count 0 2006.286.00:53:08.29#ibcon#flushed, iclass 27, count 0 2006.286.00:53:08.29#ibcon#about to write, iclass 27, count 0 2006.286.00:53:08.29#ibcon#wrote, iclass 27, count 0 2006.286.00:53:08.29#ibcon#about to read 3, iclass 27, count 0 2006.286.00:53:08.31#ibcon#read 3, iclass 27, count 0 2006.286.00:53:08.31#ibcon#about to read 4, iclass 27, count 0 2006.286.00:53:08.31#ibcon#read 4, iclass 27, count 0 2006.286.00:53:08.31#ibcon#about to read 5, iclass 27, count 0 2006.286.00:53:08.31#ibcon#read 5, iclass 27, count 0 2006.286.00:53:08.31#ibcon#about to read 6, iclass 27, count 0 2006.286.00:53:08.31#ibcon#read 6, iclass 27, count 0 2006.286.00:53:08.31#ibcon#end of sib2, iclass 27, count 0 2006.286.00:53:08.31#ibcon#*mode == 0, iclass 27, count 0 2006.286.00:53:08.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.00:53:08.31#ibcon#[27=USB\r\n] 2006.286.00:53:08.31#ibcon#*before write, iclass 27, count 0 2006.286.00:53:08.31#ibcon#enter sib2, iclass 27, count 0 2006.286.00:53:08.31#ibcon#flushed, iclass 27, count 0 2006.286.00:53:08.31#ibcon#about to write, iclass 27, count 0 2006.286.00:53:08.31#ibcon#wrote, iclass 27, count 0 2006.286.00:53:08.31#ibcon#about to read 3, iclass 27, count 0 2006.286.00:53:08.34#ibcon#read 3, iclass 27, count 0 2006.286.00:53:08.34#ibcon#about to read 4, iclass 27, count 0 2006.286.00:53:08.34#ibcon#read 4, iclass 27, count 0 2006.286.00:53:08.34#ibcon#about to read 5, iclass 27, count 0 2006.286.00:53:08.34#ibcon#read 5, iclass 27, count 0 2006.286.00:53:08.34#ibcon#about to read 6, iclass 27, count 0 2006.286.00:53:08.34#ibcon#read 6, iclass 27, count 0 2006.286.00:53:08.34#ibcon#end of sib2, iclass 27, count 0 2006.286.00:53:08.34#ibcon#*after write, iclass 27, count 0 2006.286.00:53:08.34#ibcon#*before return 0, iclass 27, count 0 2006.286.00:53:08.34#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:53:08.34#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.00:53:08.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.00:53:08.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.00:53:08.35$vck44/vabw=wide 2006.286.00:53:08.35#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.00:53:08.35#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.00:53:08.35#ibcon#ireg 8 cls_cnt 0 2006.286.00:53:08.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:53:08.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:53:08.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:53:08.35#ibcon#enter wrdev, iclass 29, count 0 2006.286.00:53:08.35#ibcon#first serial, iclass 29, count 0 2006.286.00:53:08.35#ibcon#enter sib2, iclass 29, count 0 2006.286.00:53:08.35#ibcon#flushed, iclass 29, count 0 2006.286.00:53:08.35#ibcon#about to write, iclass 29, count 0 2006.286.00:53:08.35#ibcon#wrote, iclass 29, count 0 2006.286.00:53:08.35#ibcon#about to read 3, iclass 29, count 0 2006.286.00:53:08.36#ibcon#read 3, iclass 29, count 0 2006.286.00:53:08.36#ibcon#about to read 4, iclass 29, count 0 2006.286.00:53:08.36#ibcon#read 4, iclass 29, count 0 2006.286.00:53:08.36#ibcon#about to read 5, iclass 29, count 0 2006.286.00:53:08.36#ibcon#read 5, iclass 29, count 0 2006.286.00:53:08.36#ibcon#about to read 6, iclass 29, count 0 2006.286.00:53:08.36#ibcon#read 6, iclass 29, count 0 2006.286.00:53:08.36#ibcon#end of sib2, iclass 29, count 0 2006.286.00:53:08.36#ibcon#*mode == 0, iclass 29, count 0 2006.286.00:53:08.36#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.00:53:08.36#ibcon#[25=BW32\r\n] 2006.286.00:53:08.36#ibcon#*before write, iclass 29, count 0 2006.286.00:53:08.36#ibcon#enter sib2, iclass 29, count 0 2006.286.00:53:08.36#ibcon#flushed, iclass 29, count 0 2006.286.00:53:08.36#ibcon#about to write, iclass 29, count 0 2006.286.00:53:08.36#ibcon#wrote, iclass 29, count 0 2006.286.00:53:08.36#ibcon#about to read 3, iclass 29, count 0 2006.286.00:53:08.39#ibcon#read 3, iclass 29, count 0 2006.286.00:53:08.39#ibcon#about to read 4, iclass 29, count 0 2006.286.00:53:08.39#ibcon#read 4, iclass 29, count 0 2006.286.00:53:08.39#ibcon#about to read 5, iclass 29, count 0 2006.286.00:53:08.39#ibcon#read 5, iclass 29, count 0 2006.286.00:53:08.39#ibcon#about to read 6, iclass 29, count 0 2006.286.00:53:08.39#ibcon#read 6, iclass 29, count 0 2006.286.00:53:08.39#ibcon#end of sib2, iclass 29, count 0 2006.286.00:53:08.39#ibcon#*after write, iclass 29, count 0 2006.286.00:53:08.39#ibcon#*before return 0, iclass 29, count 0 2006.286.00:53:08.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:53:08.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.00:53:08.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.00:53:08.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.00:53:08.39$vck44/vbbw=wide 2006.286.00:53:08.40#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.00:53:08.40#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.00:53:08.40#ibcon#ireg 8 cls_cnt 0 2006.286.00:53:08.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:53:08.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:53:08.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:53:08.45#ibcon#enter wrdev, iclass 31, count 0 2006.286.00:53:08.45#ibcon#first serial, iclass 31, count 0 2006.286.00:53:08.45#ibcon#enter sib2, iclass 31, count 0 2006.286.00:53:08.45#ibcon#flushed, iclass 31, count 0 2006.286.00:53:08.45#ibcon#about to write, iclass 31, count 0 2006.286.00:53:08.45#ibcon#wrote, iclass 31, count 0 2006.286.00:53:08.45#ibcon#about to read 3, iclass 31, count 0 2006.286.00:53:08.47#ibcon#read 3, iclass 31, count 0 2006.286.00:53:08.47#ibcon#about to read 4, iclass 31, count 0 2006.286.00:53:08.47#ibcon#read 4, iclass 31, count 0 2006.286.00:53:08.47#ibcon#about to read 5, iclass 31, count 0 2006.286.00:53:08.47#ibcon#read 5, iclass 31, count 0 2006.286.00:53:08.47#ibcon#about to read 6, iclass 31, count 0 2006.286.00:53:08.47#ibcon#read 6, iclass 31, count 0 2006.286.00:53:08.47#ibcon#end of sib2, iclass 31, count 0 2006.286.00:53:08.47#ibcon#*mode == 0, iclass 31, count 0 2006.286.00:53:08.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.00:53:08.47#ibcon#[27=BW32\r\n] 2006.286.00:53:08.47#ibcon#*before write, iclass 31, count 0 2006.286.00:53:08.47#ibcon#enter sib2, iclass 31, count 0 2006.286.00:53:08.47#ibcon#flushed, iclass 31, count 0 2006.286.00:53:08.47#ibcon#about to write, iclass 31, count 0 2006.286.00:53:08.47#ibcon#wrote, iclass 31, count 0 2006.286.00:53:08.47#ibcon#about to read 3, iclass 31, count 0 2006.286.00:53:08.50#ibcon#read 3, iclass 31, count 0 2006.286.00:53:08.50#ibcon#about to read 4, iclass 31, count 0 2006.286.00:53:08.50#ibcon#read 4, iclass 31, count 0 2006.286.00:53:08.50#ibcon#about to read 5, iclass 31, count 0 2006.286.00:53:08.50#ibcon#read 5, iclass 31, count 0 2006.286.00:53:08.50#ibcon#about to read 6, iclass 31, count 0 2006.286.00:53:08.50#ibcon#read 6, iclass 31, count 0 2006.286.00:53:08.50#ibcon#end of sib2, iclass 31, count 0 2006.286.00:53:08.50#ibcon#*after write, iclass 31, count 0 2006.286.00:53:08.50#ibcon#*before return 0, iclass 31, count 0 2006.286.00:53:08.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:53:08.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.00:53:08.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.00:53:08.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.00:53:08.51$setupk4/ifdk4 2006.286.00:53:08.51$ifdk4/lo= 2006.286.00:53:08.51$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.00:53:08.51$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.00:53:08.51$ifdk4/patch= 2006.286.00:53:08.51$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.00:53:08.51$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.00:53:08.51$setupk4/!*+20s 2006.286.00:53:16.93#abcon#<5=/03 3.0 6.5 20.51 841016.3\r\n> 2006.286.00:53:16.95#abcon#{5=INTERFACE CLEAR} 2006.286.00:53:17.01#abcon#[5=S1D000X0/0*\r\n] 2006.286.00:53:23.14#trakl#Source acquired 2006.286.00:53:23.17$setupk4/"tpicd 2006.286.00:53:23.17$setupk4/echo=off 2006.286.00:53:23.17$setupk4/xlog=off 2006.286.00:53:23.17:!2006.286.00:58:38 2006.286.00:53:24.14#flagr#flagr/antenna,acquired 2006.286.00:58:38.00:preob 2006.286.00:58:38.13/onsource/TRACKING 2006.286.00:58:38.13:!2006.286.00:58:48 2006.286.00:58:48.00:"tape 2006.286.00:58:48.00:"st=record 2006.286.00:58:48.00:data_valid=on 2006.286.00:58:48.00:midob 2006.286.00:58:48.13/onsource/TRACKING 2006.286.00:58:48.13/wx/20.79,1016.3,83 2006.286.00:58:48.34/cable/+6.5051E-03 2006.286.00:58:49.43/va/01,07,usb,yes,32,35 2006.286.00:58:49.43/va/02,06,usb,yes,32,33 2006.286.00:58:49.43/va/03,07,usb,yes,32,34 2006.286.00:58:49.43/va/04,06,usb,yes,33,35 2006.286.00:58:49.43/va/05,03,usb,yes,33,33 2006.286.00:58:49.43/va/06,04,usb,yes,30,29 2006.286.00:58:49.43/va/07,04,usb,yes,30,31 2006.286.00:58:49.43/va/08,03,usb,yes,31,38 2006.286.00:58:49.66/valo/01,524.99,yes,locked 2006.286.00:58:49.66/valo/02,534.99,yes,locked 2006.286.00:58:49.66/valo/03,564.99,yes,locked 2006.286.00:58:49.66/valo/04,624.99,yes,locked 2006.286.00:58:49.66/valo/05,734.99,yes,locked 2006.286.00:58:49.66/valo/06,814.99,yes,locked 2006.286.00:58:49.66/valo/07,864.99,yes,locked 2006.286.00:58:49.66/valo/08,884.99,yes,locked 2006.286.00:58:50.75/vb/01,04,usb,yes,30,29 2006.286.00:58:50.75/vb/02,05,usb,yes,29,29 2006.286.00:58:50.75/vb/03,04,usb,yes,30,33 2006.286.00:58:50.75/vb/04,05,usb,yes,30,29 2006.286.00:58:50.75/vb/05,04,usb,yes,26,29 2006.286.00:58:50.75/vb/06,03,usb,yes,38,34 2006.286.00:58:50.75/vb/07,04,usb,yes,31,31 2006.286.00:58:50.75/vb/08,04,usb,yes,28,32 2006.286.00:58:50.98/vblo/01,629.99,yes,locked 2006.286.00:58:50.98/vblo/02,634.99,yes,locked 2006.286.00:58:50.98/vblo/03,649.99,yes,locked 2006.286.00:58:50.98/vblo/04,679.99,yes,locked 2006.286.00:58:50.98/vblo/05,709.99,yes,locked 2006.286.00:58:50.98/vblo/06,719.99,yes,locked 2006.286.00:58:50.98/vblo/07,734.99,yes,locked 2006.286.00:58:50.98/vblo/08,744.99,yes,locked 2006.286.00:58:51.13/vabw/8 2006.286.00:58:51.28/vbbw/8 2006.286.00:58:51.48/xfe/off,on,12.0 2006.286.00:58:51.89/ifatt/23,28,28,28 2006.286.00:58:52.07/fmout-gps/S +2.75E-07 2006.286.00:58:52.09:!2006.286.01:02:58 2006.286.01:02:58.00:data_valid=off 2006.286.01:02:58.00:"et 2006.286.01:02:58.00:!+3s 2006.286.01:03:01.01:"tape 2006.286.01:03:01.01:postob 2006.286.01:03:01.14/cable/+6.5041E-03 2006.286.01:03:01.14/wx/20.93,1016.2,81 2006.286.01:03:02.07/fmout-gps/S +2.79E-07 2006.286.01:03:02.07:scan_name=286-0112,jd0610,60 2006.286.01:03:02.07:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.286.01:03:03.14#flagr#flagr/antenna,new-source 2006.286.01:03:03.14:checkk5 2006.286.01:03:03.58/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:03:03.95/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:03:04.33/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:03:04.76/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:03:05.12/chk_obsdata//k5ts1/T2860058??a.dat file size is correct (nominal:1000MB, actual:996MB). 2006.286.01:03:05.60/chk_obsdata//k5ts2/T2860058??b.dat file size is correct (nominal:1000MB, actual:996MB). 2006.286.01:03:05.94/chk_obsdata//k5ts3/T2860058??c.dat file size is correct (nominal:1000MB, actual:996MB). 2006.286.01:03:06.37/chk_obsdata//k5ts4/T2860058??d.dat file size is correct (nominal:1000MB, actual:996MB). 2006.286.01:03:07.21/k5log//k5ts1_log_newline 2006.286.01:03:07.99/k5log//k5ts2_log_newline 2006.286.01:03:08.76/k5log//k5ts3_log_newline 2006.286.01:03:09.47/k5log//k5ts4_log_newline 2006.286.01:03:09.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:03:09.49:setupk4=1 2006.286.01:03:09.50$setupk4/echo=on 2006.286.01:03:09.50$setupk4/pcalon 2006.286.01:03:09.50$pcalon/"no phase cal control is implemented here 2006.286.01:03:09.50$setupk4/"tpicd=stop 2006.286.01:03:09.50$setupk4/"rec=synch_on 2006.286.01:03:09.50$setupk4/"rec_mode=128 2006.286.01:03:09.50$setupk4/!* 2006.286.01:03:09.50$setupk4/recpk4 2006.286.01:03:09.50$recpk4/recpatch= 2006.286.01:03:09.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:03:09.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:03:09.50$setupk4/vck44 2006.286.01:03:09.50$vck44/valo=1,524.99 2006.286.01:03:09.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.01:03:09.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.01:03:09.50#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:09.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:03:09.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:03:09.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:03:09.50#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:03:09.50#ibcon#first serial, iclass 20, count 0 2006.286.01:03:09.50#ibcon#enter sib2, iclass 20, count 0 2006.286.01:03:09.50#ibcon#flushed, iclass 20, count 0 2006.286.01:03:09.50#ibcon#about to write, iclass 20, count 0 2006.286.01:03:09.50#ibcon#wrote, iclass 20, count 0 2006.286.01:03:09.50#ibcon#about to read 3, iclass 20, count 0 2006.286.01:03:09.51#ibcon#read 3, iclass 20, count 0 2006.286.01:03:09.51#ibcon#about to read 4, iclass 20, count 0 2006.286.01:03:09.51#ibcon#read 4, iclass 20, count 0 2006.286.01:03:09.51#ibcon#about to read 5, iclass 20, count 0 2006.286.01:03:09.51#ibcon#read 5, iclass 20, count 0 2006.286.01:03:09.51#ibcon#about to read 6, iclass 20, count 0 2006.286.01:03:09.51#ibcon#read 6, iclass 20, count 0 2006.286.01:03:09.51#ibcon#end of sib2, iclass 20, count 0 2006.286.01:03:09.51#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:03:09.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:03:09.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:03:09.51#ibcon#*before write, iclass 20, count 0 2006.286.01:03:09.51#ibcon#enter sib2, iclass 20, count 0 2006.286.01:03:09.51#ibcon#flushed, iclass 20, count 0 2006.286.01:03:09.51#ibcon#about to write, iclass 20, count 0 2006.286.01:03:09.51#ibcon#wrote, iclass 20, count 0 2006.286.01:03:09.51#ibcon#about to read 3, iclass 20, count 0 2006.286.01:03:09.56#ibcon#read 3, iclass 20, count 0 2006.286.01:03:09.56#ibcon#about to read 4, iclass 20, count 0 2006.286.01:03:09.56#ibcon#read 4, iclass 20, count 0 2006.286.01:03:09.56#ibcon#about to read 5, iclass 20, count 0 2006.286.01:03:09.56#ibcon#read 5, iclass 20, count 0 2006.286.01:03:09.56#ibcon#about to read 6, iclass 20, count 0 2006.286.01:03:09.56#ibcon#read 6, iclass 20, count 0 2006.286.01:03:09.56#ibcon#end of sib2, iclass 20, count 0 2006.286.01:03:09.56#ibcon#*after write, iclass 20, count 0 2006.286.01:03:09.56#ibcon#*before return 0, iclass 20, count 0 2006.286.01:03:09.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:03:09.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:03:09.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:03:09.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:03:09.56$vck44/va=1,7 2006.286.01:03:09.56#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.01:03:09.56#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.01:03:09.56#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:09.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:03:09.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:03:09.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:03:09.56#ibcon#enter wrdev, iclass 22, count 2 2006.286.01:03:09.56#ibcon#first serial, iclass 22, count 2 2006.286.01:03:09.56#ibcon#enter sib2, iclass 22, count 2 2006.286.01:03:09.56#ibcon#flushed, iclass 22, count 2 2006.286.01:03:09.56#ibcon#about to write, iclass 22, count 2 2006.286.01:03:09.56#ibcon#wrote, iclass 22, count 2 2006.286.01:03:09.56#ibcon#about to read 3, iclass 22, count 2 2006.286.01:03:09.58#ibcon#read 3, iclass 22, count 2 2006.286.01:03:09.58#ibcon#about to read 4, iclass 22, count 2 2006.286.01:03:09.58#ibcon#read 4, iclass 22, count 2 2006.286.01:03:09.58#ibcon#about to read 5, iclass 22, count 2 2006.286.01:03:09.58#ibcon#read 5, iclass 22, count 2 2006.286.01:03:09.58#ibcon#about to read 6, iclass 22, count 2 2006.286.01:03:09.58#ibcon#read 6, iclass 22, count 2 2006.286.01:03:09.58#ibcon#end of sib2, iclass 22, count 2 2006.286.01:03:09.58#ibcon#*mode == 0, iclass 22, count 2 2006.286.01:03:09.58#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.01:03:09.58#ibcon#[25=AT01-07\r\n] 2006.286.01:03:09.58#ibcon#*before write, iclass 22, count 2 2006.286.01:03:09.58#ibcon#enter sib2, iclass 22, count 2 2006.286.01:03:09.58#ibcon#flushed, iclass 22, count 2 2006.286.01:03:09.58#ibcon#about to write, iclass 22, count 2 2006.286.01:03:09.58#ibcon#wrote, iclass 22, count 2 2006.286.01:03:09.58#ibcon#about to read 3, iclass 22, count 2 2006.286.01:03:09.61#ibcon#read 3, iclass 22, count 2 2006.286.01:03:09.61#ibcon#about to read 4, iclass 22, count 2 2006.286.01:03:09.61#ibcon#read 4, iclass 22, count 2 2006.286.01:03:09.61#ibcon#about to read 5, iclass 22, count 2 2006.286.01:03:09.61#ibcon#read 5, iclass 22, count 2 2006.286.01:03:09.61#ibcon#about to read 6, iclass 22, count 2 2006.286.01:03:09.61#ibcon#read 6, iclass 22, count 2 2006.286.01:03:09.61#ibcon#end of sib2, iclass 22, count 2 2006.286.01:03:09.61#ibcon#*after write, iclass 22, count 2 2006.286.01:03:09.61#ibcon#*before return 0, iclass 22, count 2 2006.286.01:03:09.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:03:09.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:03:09.61#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.01:03:09.61#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:09.61#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:03:09.73#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:03:09.73#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:03:09.73#ibcon#enter wrdev, iclass 22, count 0 2006.286.01:03:09.73#ibcon#first serial, iclass 22, count 0 2006.286.01:03:09.73#ibcon#enter sib2, iclass 22, count 0 2006.286.01:03:09.73#ibcon#flushed, iclass 22, count 0 2006.286.01:03:09.73#ibcon#about to write, iclass 22, count 0 2006.286.01:03:09.73#ibcon#wrote, iclass 22, count 0 2006.286.01:03:09.73#ibcon#about to read 3, iclass 22, count 0 2006.286.01:03:09.75#ibcon#read 3, iclass 22, count 0 2006.286.01:03:09.75#ibcon#about to read 4, iclass 22, count 0 2006.286.01:03:09.75#ibcon#read 4, iclass 22, count 0 2006.286.01:03:09.75#ibcon#about to read 5, iclass 22, count 0 2006.286.01:03:09.75#ibcon#read 5, iclass 22, count 0 2006.286.01:03:09.75#ibcon#about to read 6, iclass 22, count 0 2006.286.01:03:09.75#ibcon#read 6, iclass 22, count 0 2006.286.01:03:09.75#ibcon#end of sib2, iclass 22, count 0 2006.286.01:03:09.75#ibcon#*mode == 0, iclass 22, count 0 2006.286.01:03:09.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.01:03:09.75#ibcon#[25=USB\r\n] 2006.286.01:03:09.75#ibcon#*before write, iclass 22, count 0 2006.286.01:03:09.75#ibcon#enter sib2, iclass 22, count 0 2006.286.01:03:09.75#ibcon#flushed, iclass 22, count 0 2006.286.01:03:09.75#ibcon#about to write, iclass 22, count 0 2006.286.01:03:09.75#ibcon#wrote, iclass 22, count 0 2006.286.01:03:09.75#ibcon#about to read 3, iclass 22, count 0 2006.286.01:03:09.78#ibcon#read 3, iclass 22, count 0 2006.286.01:03:09.78#ibcon#about to read 4, iclass 22, count 0 2006.286.01:03:09.78#ibcon#read 4, iclass 22, count 0 2006.286.01:03:09.78#ibcon#about to read 5, iclass 22, count 0 2006.286.01:03:09.78#ibcon#read 5, iclass 22, count 0 2006.286.01:03:09.78#ibcon#about to read 6, iclass 22, count 0 2006.286.01:03:09.78#ibcon#read 6, iclass 22, count 0 2006.286.01:03:09.78#ibcon#end of sib2, iclass 22, count 0 2006.286.01:03:09.78#ibcon#*after write, iclass 22, count 0 2006.286.01:03:09.78#ibcon#*before return 0, iclass 22, count 0 2006.286.01:03:09.78#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:03:09.78#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:03:09.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.01:03:09.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.01:03:09.78$vck44/valo=2,534.99 2006.286.01:03:09.78#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.01:03:09.78#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.01:03:09.78#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:09.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:03:09.78#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:03:09.78#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:03:09.78#ibcon#enter wrdev, iclass 24, count 0 2006.286.01:03:09.78#ibcon#first serial, iclass 24, count 0 2006.286.01:03:09.78#ibcon#enter sib2, iclass 24, count 0 2006.286.01:03:09.78#ibcon#flushed, iclass 24, count 0 2006.286.01:03:09.78#ibcon#about to write, iclass 24, count 0 2006.286.01:03:09.78#ibcon#wrote, iclass 24, count 0 2006.286.01:03:09.78#ibcon#about to read 3, iclass 24, count 0 2006.286.01:03:09.80#ibcon#read 3, iclass 24, count 0 2006.286.01:03:09.80#ibcon#about to read 4, iclass 24, count 0 2006.286.01:03:09.80#ibcon#read 4, iclass 24, count 0 2006.286.01:03:09.80#ibcon#about to read 5, iclass 24, count 0 2006.286.01:03:09.80#ibcon#read 5, iclass 24, count 0 2006.286.01:03:09.80#ibcon#about to read 6, iclass 24, count 0 2006.286.01:03:09.80#ibcon#read 6, iclass 24, count 0 2006.286.01:03:09.80#ibcon#end of sib2, iclass 24, count 0 2006.286.01:03:09.80#ibcon#*mode == 0, iclass 24, count 0 2006.286.01:03:09.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.01:03:09.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:03:09.80#ibcon#*before write, iclass 24, count 0 2006.286.01:03:09.80#ibcon#enter sib2, iclass 24, count 0 2006.286.01:03:09.80#ibcon#flushed, iclass 24, count 0 2006.286.01:03:09.80#ibcon#about to write, iclass 24, count 0 2006.286.01:03:09.80#ibcon#wrote, iclass 24, count 0 2006.286.01:03:09.80#ibcon#about to read 3, iclass 24, count 0 2006.286.01:03:09.84#ibcon#read 3, iclass 24, count 0 2006.286.01:03:09.84#ibcon#about to read 4, iclass 24, count 0 2006.286.01:03:09.84#ibcon#read 4, iclass 24, count 0 2006.286.01:03:09.84#ibcon#about to read 5, iclass 24, count 0 2006.286.01:03:09.84#ibcon#read 5, iclass 24, count 0 2006.286.01:03:09.84#ibcon#about to read 6, iclass 24, count 0 2006.286.01:03:09.84#ibcon#read 6, iclass 24, count 0 2006.286.01:03:09.84#ibcon#end of sib2, iclass 24, count 0 2006.286.01:03:09.84#ibcon#*after write, iclass 24, count 0 2006.286.01:03:09.84#ibcon#*before return 0, iclass 24, count 0 2006.286.01:03:09.84#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:03:09.84#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:03:09.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.01:03:09.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.01:03:09.84$vck44/va=2,6 2006.286.01:03:09.84#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.01:03:09.84#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.01:03:09.84#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:09.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:03:09.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:03:09.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:03:09.90#ibcon#enter wrdev, iclass 26, count 2 2006.286.01:03:09.90#ibcon#first serial, iclass 26, count 2 2006.286.01:03:09.90#ibcon#enter sib2, iclass 26, count 2 2006.286.01:03:09.90#ibcon#flushed, iclass 26, count 2 2006.286.01:03:09.90#ibcon#about to write, iclass 26, count 2 2006.286.01:03:09.90#ibcon#wrote, iclass 26, count 2 2006.286.01:03:09.90#ibcon#about to read 3, iclass 26, count 2 2006.286.01:03:09.92#ibcon#read 3, iclass 26, count 2 2006.286.01:03:09.92#ibcon#about to read 4, iclass 26, count 2 2006.286.01:03:09.92#ibcon#read 4, iclass 26, count 2 2006.286.01:03:09.92#ibcon#about to read 5, iclass 26, count 2 2006.286.01:03:09.92#ibcon#read 5, iclass 26, count 2 2006.286.01:03:09.92#ibcon#about to read 6, iclass 26, count 2 2006.286.01:03:09.92#ibcon#read 6, iclass 26, count 2 2006.286.01:03:09.92#ibcon#end of sib2, iclass 26, count 2 2006.286.01:03:09.92#ibcon#*mode == 0, iclass 26, count 2 2006.286.01:03:09.92#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.01:03:09.92#ibcon#[25=AT02-06\r\n] 2006.286.01:03:09.92#ibcon#*before write, iclass 26, count 2 2006.286.01:03:09.92#ibcon#enter sib2, iclass 26, count 2 2006.286.01:03:09.92#ibcon#flushed, iclass 26, count 2 2006.286.01:03:09.92#ibcon#about to write, iclass 26, count 2 2006.286.01:03:09.92#ibcon#wrote, iclass 26, count 2 2006.286.01:03:09.92#ibcon#about to read 3, iclass 26, count 2 2006.286.01:03:09.95#ibcon#read 3, iclass 26, count 2 2006.286.01:03:09.95#ibcon#about to read 4, iclass 26, count 2 2006.286.01:03:09.95#ibcon#read 4, iclass 26, count 2 2006.286.01:03:09.95#ibcon#about to read 5, iclass 26, count 2 2006.286.01:03:09.95#ibcon#read 5, iclass 26, count 2 2006.286.01:03:09.95#ibcon#about to read 6, iclass 26, count 2 2006.286.01:03:09.95#ibcon#read 6, iclass 26, count 2 2006.286.01:03:09.95#ibcon#end of sib2, iclass 26, count 2 2006.286.01:03:09.95#ibcon#*after write, iclass 26, count 2 2006.286.01:03:09.95#ibcon#*before return 0, iclass 26, count 2 2006.286.01:03:09.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:03:09.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:03:09.95#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.01:03:09.95#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:09.95#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:03:10.07#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:03:10.07#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:03:10.07#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:03:10.07#ibcon#first serial, iclass 26, count 0 2006.286.01:03:10.07#ibcon#enter sib2, iclass 26, count 0 2006.286.01:03:10.07#ibcon#flushed, iclass 26, count 0 2006.286.01:03:10.07#ibcon#about to write, iclass 26, count 0 2006.286.01:03:10.07#ibcon#wrote, iclass 26, count 0 2006.286.01:03:10.07#ibcon#about to read 3, iclass 26, count 0 2006.286.01:03:10.09#ibcon#read 3, iclass 26, count 0 2006.286.01:03:10.09#ibcon#about to read 4, iclass 26, count 0 2006.286.01:03:10.09#ibcon#read 4, iclass 26, count 0 2006.286.01:03:10.09#ibcon#about to read 5, iclass 26, count 0 2006.286.01:03:10.09#ibcon#read 5, iclass 26, count 0 2006.286.01:03:10.09#ibcon#about to read 6, iclass 26, count 0 2006.286.01:03:10.09#ibcon#read 6, iclass 26, count 0 2006.286.01:03:10.09#ibcon#end of sib2, iclass 26, count 0 2006.286.01:03:10.09#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:03:10.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:03:10.09#ibcon#[25=USB\r\n] 2006.286.01:03:10.09#ibcon#*before write, iclass 26, count 0 2006.286.01:03:10.09#ibcon#enter sib2, iclass 26, count 0 2006.286.01:03:10.09#ibcon#flushed, iclass 26, count 0 2006.286.01:03:10.09#ibcon#about to write, iclass 26, count 0 2006.286.01:03:10.09#ibcon#wrote, iclass 26, count 0 2006.286.01:03:10.09#ibcon#about to read 3, iclass 26, count 0 2006.286.01:03:10.12#ibcon#read 3, iclass 26, count 0 2006.286.01:03:10.12#ibcon#about to read 4, iclass 26, count 0 2006.286.01:03:10.12#ibcon#read 4, iclass 26, count 0 2006.286.01:03:10.12#ibcon#about to read 5, iclass 26, count 0 2006.286.01:03:10.12#ibcon#read 5, iclass 26, count 0 2006.286.01:03:10.12#ibcon#about to read 6, iclass 26, count 0 2006.286.01:03:10.12#ibcon#read 6, iclass 26, count 0 2006.286.01:03:10.12#ibcon#end of sib2, iclass 26, count 0 2006.286.01:03:10.12#ibcon#*after write, iclass 26, count 0 2006.286.01:03:10.12#ibcon#*before return 0, iclass 26, count 0 2006.286.01:03:10.12#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:03:10.12#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:03:10.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:03:10.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:03:10.12$vck44/valo=3,564.99 2006.286.01:03:10.12#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.01:03:10.12#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.01:03:10.12#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:10.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:03:10.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:03:10.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:03:10.12#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:03:10.12#ibcon#first serial, iclass 28, count 0 2006.286.01:03:10.12#ibcon#enter sib2, iclass 28, count 0 2006.286.01:03:10.12#ibcon#flushed, iclass 28, count 0 2006.286.01:03:10.12#ibcon#about to write, iclass 28, count 0 2006.286.01:03:10.12#ibcon#wrote, iclass 28, count 0 2006.286.01:03:10.12#ibcon#about to read 3, iclass 28, count 0 2006.286.01:03:10.14#ibcon#read 3, iclass 28, count 0 2006.286.01:03:10.14#ibcon#about to read 4, iclass 28, count 0 2006.286.01:03:10.14#ibcon#read 4, iclass 28, count 0 2006.286.01:03:10.14#ibcon#about to read 5, iclass 28, count 0 2006.286.01:03:10.14#ibcon#read 5, iclass 28, count 0 2006.286.01:03:10.14#ibcon#about to read 6, iclass 28, count 0 2006.286.01:03:10.14#ibcon#read 6, iclass 28, count 0 2006.286.01:03:10.14#ibcon#end of sib2, iclass 28, count 0 2006.286.01:03:10.14#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:03:10.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:03:10.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:03:10.14#ibcon#*before write, iclass 28, count 0 2006.286.01:03:10.14#ibcon#enter sib2, iclass 28, count 0 2006.286.01:03:10.14#ibcon#flushed, iclass 28, count 0 2006.286.01:03:10.14#ibcon#about to write, iclass 28, count 0 2006.286.01:03:10.14#ibcon#wrote, iclass 28, count 0 2006.286.01:03:10.14#ibcon#about to read 3, iclass 28, count 0 2006.286.01:03:10.18#ibcon#read 3, iclass 28, count 0 2006.286.01:03:10.18#ibcon#about to read 4, iclass 28, count 0 2006.286.01:03:10.18#ibcon#read 4, iclass 28, count 0 2006.286.01:03:10.18#ibcon#about to read 5, iclass 28, count 0 2006.286.01:03:10.18#ibcon#read 5, iclass 28, count 0 2006.286.01:03:10.18#ibcon#about to read 6, iclass 28, count 0 2006.286.01:03:10.18#ibcon#read 6, iclass 28, count 0 2006.286.01:03:10.18#ibcon#end of sib2, iclass 28, count 0 2006.286.01:03:10.18#ibcon#*after write, iclass 28, count 0 2006.286.01:03:10.18#ibcon#*before return 0, iclass 28, count 0 2006.286.01:03:10.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:03:10.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:03:10.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:03:10.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:03:10.18$vck44/va=3,7 2006.286.01:03:10.18#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.01:03:10.18#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.01:03:10.18#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:10.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:03:10.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:03:10.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:03:10.24#ibcon#enter wrdev, iclass 30, count 2 2006.286.01:03:10.24#ibcon#first serial, iclass 30, count 2 2006.286.01:03:10.24#ibcon#enter sib2, iclass 30, count 2 2006.286.01:03:10.24#ibcon#flushed, iclass 30, count 2 2006.286.01:03:10.24#ibcon#about to write, iclass 30, count 2 2006.286.01:03:10.24#ibcon#wrote, iclass 30, count 2 2006.286.01:03:10.24#ibcon#about to read 3, iclass 30, count 2 2006.286.01:03:10.26#ibcon#read 3, iclass 30, count 2 2006.286.01:03:10.26#ibcon#about to read 4, iclass 30, count 2 2006.286.01:03:10.26#ibcon#read 4, iclass 30, count 2 2006.286.01:03:10.26#ibcon#about to read 5, iclass 30, count 2 2006.286.01:03:10.26#ibcon#read 5, iclass 30, count 2 2006.286.01:03:10.26#ibcon#about to read 6, iclass 30, count 2 2006.286.01:03:10.26#ibcon#read 6, iclass 30, count 2 2006.286.01:03:10.26#ibcon#end of sib2, iclass 30, count 2 2006.286.01:03:10.26#ibcon#*mode == 0, iclass 30, count 2 2006.286.01:03:10.26#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.01:03:10.26#ibcon#[25=AT03-07\r\n] 2006.286.01:03:10.26#ibcon#*before write, iclass 30, count 2 2006.286.01:03:10.26#ibcon#enter sib2, iclass 30, count 2 2006.286.01:03:10.26#ibcon#flushed, iclass 30, count 2 2006.286.01:03:10.26#ibcon#about to write, iclass 30, count 2 2006.286.01:03:10.26#ibcon#wrote, iclass 30, count 2 2006.286.01:03:10.26#ibcon#about to read 3, iclass 30, count 2 2006.286.01:03:10.29#ibcon#read 3, iclass 30, count 2 2006.286.01:03:10.29#ibcon#about to read 4, iclass 30, count 2 2006.286.01:03:10.29#ibcon#read 4, iclass 30, count 2 2006.286.01:03:10.29#ibcon#about to read 5, iclass 30, count 2 2006.286.01:03:10.29#ibcon#read 5, iclass 30, count 2 2006.286.01:03:10.29#ibcon#about to read 6, iclass 30, count 2 2006.286.01:03:10.29#ibcon#read 6, iclass 30, count 2 2006.286.01:03:10.29#ibcon#end of sib2, iclass 30, count 2 2006.286.01:03:10.29#ibcon#*after write, iclass 30, count 2 2006.286.01:03:10.29#ibcon#*before return 0, iclass 30, count 2 2006.286.01:03:10.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:03:10.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:03:10.29#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.01:03:10.29#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:10.29#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:03:10.41#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:03:10.41#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:03:10.41#ibcon#enter wrdev, iclass 30, count 0 2006.286.01:03:10.41#ibcon#first serial, iclass 30, count 0 2006.286.01:03:10.41#ibcon#enter sib2, iclass 30, count 0 2006.286.01:03:10.41#ibcon#flushed, iclass 30, count 0 2006.286.01:03:10.41#ibcon#about to write, iclass 30, count 0 2006.286.01:03:10.41#ibcon#wrote, iclass 30, count 0 2006.286.01:03:10.41#ibcon#about to read 3, iclass 30, count 0 2006.286.01:03:10.43#ibcon#read 3, iclass 30, count 0 2006.286.01:03:10.43#ibcon#about to read 4, iclass 30, count 0 2006.286.01:03:10.43#ibcon#read 4, iclass 30, count 0 2006.286.01:03:10.43#ibcon#about to read 5, iclass 30, count 0 2006.286.01:03:10.43#ibcon#read 5, iclass 30, count 0 2006.286.01:03:10.43#ibcon#about to read 6, iclass 30, count 0 2006.286.01:03:10.43#ibcon#read 6, iclass 30, count 0 2006.286.01:03:10.43#ibcon#end of sib2, iclass 30, count 0 2006.286.01:03:10.43#ibcon#*mode == 0, iclass 30, count 0 2006.286.01:03:10.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.01:03:10.43#ibcon#[25=USB\r\n] 2006.286.01:03:10.43#ibcon#*before write, iclass 30, count 0 2006.286.01:03:10.43#ibcon#enter sib2, iclass 30, count 0 2006.286.01:03:10.43#ibcon#flushed, iclass 30, count 0 2006.286.01:03:10.43#ibcon#about to write, iclass 30, count 0 2006.286.01:03:10.43#ibcon#wrote, iclass 30, count 0 2006.286.01:03:10.43#ibcon#about to read 3, iclass 30, count 0 2006.286.01:03:10.46#ibcon#read 3, iclass 30, count 0 2006.286.01:03:10.46#ibcon#about to read 4, iclass 30, count 0 2006.286.01:03:10.46#ibcon#read 4, iclass 30, count 0 2006.286.01:03:10.46#ibcon#about to read 5, iclass 30, count 0 2006.286.01:03:10.46#ibcon#read 5, iclass 30, count 0 2006.286.01:03:10.46#ibcon#about to read 6, iclass 30, count 0 2006.286.01:03:10.46#ibcon#read 6, iclass 30, count 0 2006.286.01:03:10.46#ibcon#end of sib2, iclass 30, count 0 2006.286.01:03:10.46#ibcon#*after write, iclass 30, count 0 2006.286.01:03:10.46#ibcon#*before return 0, iclass 30, count 0 2006.286.01:03:10.46#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:03:10.46#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:03:10.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.01:03:10.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.01:03:10.46$vck44/valo=4,624.99 2006.286.01:03:10.46#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.01:03:10.46#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.01:03:10.46#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:10.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:03:10.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:03:10.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:03:10.46#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:03:10.46#ibcon#first serial, iclass 32, count 0 2006.286.01:03:10.46#ibcon#enter sib2, iclass 32, count 0 2006.286.01:03:10.46#ibcon#flushed, iclass 32, count 0 2006.286.01:03:10.46#ibcon#about to write, iclass 32, count 0 2006.286.01:03:10.46#ibcon#wrote, iclass 32, count 0 2006.286.01:03:10.46#ibcon#about to read 3, iclass 32, count 0 2006.286.01:03:10.48#ibcon#read 3, iclass 32, count 0 2006.286.01:03:10.48#ibcon#about to read 4, iclass 32, count 0 2006.286.01:03:10.48#ibcon#read 4, iclass 32, count 0 2006.286.01:03:10.48#ibcon#about to read 5, iclass 32, count 0 2006.286.01:03:10.48#ibcon#read 5, iclass 32, count 0 2006.286.01:03:10.48#ibcon#about to read 6, iclass 32, count 0 2006.286.01:03:10.48#ibcon#read 6, iclass 32, count 0 2006.286.01:03:10.48#ibcon#end of sib2, iclass 32, count 0 2006.286.01:03:10.48#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:03:10.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:03:10.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:03:10.48#ibcon#*before write, iclass 32, count 0 2006.286.01:03:10.48#ibcon#enter sib2, iclass 32, count 0 2006.286.01:03:10.48#ibcon#flushed, iclass 32, count 0 2006.286.01:03:10.48#ibcon#about to write, iclass 32, count 0 2006.286.01:03:10.48#ibcon#wrote, iclass 32, count 0 2006.286.01:03:10.48#ibcon#about to read 3, iclass 32, count 0 2006.286.01:03:10.52#ibcon#read 3, iclass 32, count 0 2006.286.01:03:10.52#ibcon#about to read 4, iclass 32, count 0 2006.286.01:03:10.52#ibcon#read 4, iclass 32, count 0 2006.286.01:03:10.52#ibcon#about to read 5, iclass 32, count 0 2006.286.01:03:10.52#ibcon#read 5, iclass 32, count 0 2006.286.01:03:10.52#ibcon#about to read 6, iclass 32, count 0 2006.286.01:03:10.52#ibcon#read 6, iclass 32, count 0 2006.286.01:03:10.52#ibcon#end of sib2, iclass 32, count 0 2006.286.01:03:10.52#ibcon#*after write, iclass 32, count 0 2006.286.01:03:10.52#ibcon#*before return 0, iclass 32, count 0 2006.286.01:03:10.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:03:10.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:03:10.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:03:10.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:03:10.52$vck44/va=4,6 2006.286.01:03:10.52#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.01:03:10.52#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.01:03:10.52#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:10.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:03:10.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:03:10.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:03:10.58#ibcon#enter wrdev, iclass 34, count 2 2006.286.01:03:10.58#ibcon#first serial, iclass 34, count 2 2006.286.01:03:10.58#ibcon#enter sib2, iclass 34, count 2 2006.286.01:03:10.58#ibcon#flushed, iclass 34, count 2 2006.286.01:03:10.58#ibcon#about to write, iclass 34, count 2 2006.286.01:03:10.58#ibcon#wrote, iclass 34, count 2 2006.286.01:03:10.58#ibcon#about to read 3, iclass 34, count 2 2006.286.01:03:10.60#ibcon#read 3, iclass 34, count 2 2006.286.01:03:10.60#ibcon#about to read 4, iclass 34, count 2 2006.286.01:03:10.60#ibcon#read 4, iclass 34, count 2 2006.286.01:03:10.60#ibcon#about to read 5, iclass 34, count 2 2006.286.01:03:10.60#ibcon#read 5, iclass 34, count 2 2006.286.01:03:10.60#ibcon#about to read 6, iclass 34, count 2 2006.286.01:03:10.60#ibcon#read 6, iclass 34, count 2 2006.286.01:03:10.60#ibcon#end of sib2, iclass 34, count 2 2006.286.01:03:10.60#ibcon#*mode == 0, iclass 34, count 2 2006.286.01:03:10.60#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.01:03:10.60#ibcon#[25=AT04-06\r\n] 2006.286.01:03:10.60#ibcon#*before write, iclass 34, count 2 2006.286.01:03:10.60#ibcon#enter sib2, iclass 34, count 2 2006.286.01:03:10.60#ibcon#flushed, iclass 34, count 2 2006.286.01:03:10.60#ibcon#about to write, iclass 34, count 2 2006.286.01:03:10.60#ibcon#wrote, iclass 34, count 2 2006.286.01:03:10.60#ibcon#about to read 3, iclass 34, count 2 2006.286.01:03:10.63#ibcon#read 3, iclass 34, count 2 2006.286.01:03:10.63#ibcon#about to read 4, iclass 34, count 2 2006.286.01:03:10.63#ibcon#read 4, iclass 34, count 2 2006.286.01:03:10.63#ibcon#about to read 5, iclass 34, count 2 2006.286.01:03:10.63#ibcon#read 5, iclass 34, count 2 2006.286.01:03:10.63#ibcon#about to read 6, iclass 34, count 2 2006.286.01:03:10.63#ibcon#read 6, iclass 34, count 2 2006.286.01:03:10.63#ibcon#end of sib2, iclass 34, count 2 2006.286.01:03:10.63#ibcon#*after write, iclass 34, count 2 2006.286.01:03:10.63#ibcon#*before return 0, iclass 34, count 2 2006.286.01:03:10.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:03:10.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:03:10.63#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.01:03:10.63#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:10.63#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:03:10.75#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:03:10.75#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:03:10.75#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:03:10.75#ibcon#first serial, iclass 34, count 0 2006.286.01:03:10.75#ibcon#enter sib2, iclass 34, count 0 2006.286.01:03:10.75#ibcon#flushed, iclass 34, count 0 2006.286.01:03:10.75#ibcon#about to write, iclass 34, count 0 2006.286.01:03:10.75#ibcon#wrote, iclass 34, count 0 2006.286.01:03:10.75#ibcon#about to read 3, iclass 34, count 0 2006.286.01:03:10.77#ibcon#read 3, iclass 34, count 0 2006.286.01:03:10.77#ibcon#about to read 4, iclass 34, count 0 2006.286.01:03:10.77#ibcon#read 4, iclass 34, count 0 2006.286.01:03:10.77#ibcon#about to read 5, iclass 34, count 0 2006.286.01:03:10.77#ibcon#read 5, iclass 34, count 0 2006.286.01:03:10.77#ibcon#about to read 6, iclass 34, count 0 2006.286.01:03:10.77#ibcon#read 6, iclass 34, count 0 2006.286.01:03:10.77#ibcon#end of sib2, iclass 34, count 0 2006.286.01:03:10.77#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:03:10.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:03:10.77#ibcon#[25=USB\r\n] 2006.286.01:03:10.77#ibcon#*before write, iclass 34, count 0 2006.286.01:03:10.77#ibcon#enter sib2, iclass 34, count 0 2006.286.01:03:10.77#ibcon#flushed, iclass 34, count 0 2006.286.01:03:10.77#ibcon#about to write, iclass 34, count 0 2006.286.01:03:10.77#ibcon#wrote, iclass 34, count 0 2006.286.01:03:10.77#ibcon#about to read 3, iclass 34, count 0 2006.286.01:03:10.80#ibcon#read 3, iclass 34, count 0 2006.286.01:03:10.80#ibcon#about to read 4, iclass 34, count 0 2006.286.01:03:10.80#ibcon#read 4, iclass 34, count 0 2006.286.01:03:10.80#ibcon#about to read 5, iclass 34, count 0 2006.286.01:03:10.80#ibcon#read 5, iclass 34, count 0 2006.286.01:03:10.80#ibcon#about to read 6, iclass 34, count 0 2006.286.01:03:10.80#ibcon#read 6, iclass 34, count 0 2006.286.01:03:10.80#ibcon#end of sib2, iclass 34, count 0 2006.286.01:03:10.80#ibcon#*after write, iclass 34, count 0 2006.286.01:03:10.80#ibcon#*before return 0, iclass 34, count 0 2006.286.01:03:10.80#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:03:10.80#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:03:10.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:03:10.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:03:10.80$vck44/valo=5,734.99 2006.286.01:03:10.80#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.01:03:10.80#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.01:03:10.80#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:10.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:03:10.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:03:10.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:03:10.80#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:03:10.80#ibcon#first serial, iclass 36, count 0 2006.286.01:03:10.80#ibcon#enter sib2, iclass 36, count 0 2006.286.01:03:10.80#ibcon#flushed, iclass 36, count 0 2006.286.01:03:10.80#ibcon#about to write, iclass 36, count 0 2006.286.01:03:10.80#ibcon#wrote, iclass 36, count 0 2006.286.01:03:10.80#ibcon#about to read 3, iclass 36, count 0 2006.286.01:03:10.82#ibcon#read 3, iclass 36, count 0 2006.286.01:03:10.82#ibcon#about to read 4, iclass 36, count 0 2006.286.01:03:10.82#ibcon#read 4, iclass 36, count 0 2006.286.01:03:10.82#ibcon#about to read 5, iclass 36, count 0 2006.286.01:03:10.82#ibcon#read 5, iclass 36, count 0 2006.286.01:03:10.82#ibcon#about to read 6, iclass 36, count 0 2006.286.01:03:10.82#ibcon#read 6, iclass 36, count 0 2006.286.01:03:10.82#ibcon#end of sib2, iclass 36, count 0 2006.286.01:03:10.82#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:03:10.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:03:10.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:03:10.82#ibcon#*before write, iclass 36, count 0 2006.286.01:03:10.82#ibcon#enter sib2, iclass 36, count 0 2006.286.01:03:10.82#ibcon#flushed, iclass 36, count 0 2006.286.01:03:10.82#ibcon#about to write, iclass 36, count 0 2006.286.01:03:10.82#ibcon#wrote, iclass 36, count 0 2006.286.01:03:10.82#ibcon#about to read 3, iclass 36, count 0 2006.286.01:03:10.86#ibcon#read 3, iclass 36, count 0 2006.286.01:03:10.86#ibcon#about to read 4, iclass 36, count 0 2006.286.01:03:10.86#ibcon#read 4, iclass 36, count 0 2006.286.01:03:10.86#ibcon#about to read 5, iclass 36, count 0 2006.286.01:03:10.86#ibcon#read 5, iclass 36, count 0 2006.286.01:03:10.86#ibcon#about to read 6, iclass 36, count 0 2006.286.01:03:10.86#ibcon#read 6, iclass 36, count 0 2006.286.01:03:10.86#ibcon#end of sib2, iclass 36, count 0 2006.286.01:03:10.86#ibcon#*after write, iclass 36, count 0 2006.286.01:03:10.86#ibcon#*before return 0, iclass 36, count 0 2006.286.01:03:10.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:03:10.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:03:10.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:03:10.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:03:10.86$vck44/va=5,3 2006.286.01:03:10.86#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.01:03:10.86#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.01:03:10.86#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:10.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:03:10.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:03:10.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:03:10.92#ibcon#enter wrdev, iclass 38, count 2 2006.286.01:03:10.92#ibcon#first serial, iclass 38, count 2 2006.286.01:03:10.92#ibcon#enter sib2, iclass 38, count 2 2006.286.01:03:10.92#ibcon#flushed, iclass 38, count 2 2006.286.01:03:10.92#ibcon#about to write, iclass 38, count 2 2006.286.01:03:10.92#ibcon#wrote, iclass 38, count 2 2006.286.01:03:10.92#ibcon#about to read 3, iclass 38, count 2 2006.286.01:03:10.94#ibcon#read 3, iclass 38, count 2 2006.286.01:03:10.94#ibcon#about to read 4, iclass 38, count 2 2006.286.01:03:10.94#ibcon#read 4, iclass 38, count 2 2006.286.01:03:10.94#ibcon#about to read 5, iclass 38, count 2 2006.286.01:03:10.94#ibcon#read 5, iclass 38, count 2 2006.286.01:03:10.94#ibcon#about to read 6, iclass 38, count 2 2006.286.01:03:10.94#ibcon#read 6, iclass 38, count 2 2006.286.01:03:10.94#ibcon#end of sib2, iclass 38, count 2 2006.286.01:03:10.94#ibcon#*mode == 0, iclass 38, count 2 2006.286.01:03:10.94#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.01:03:10.94#ibcon#[25=AT05-03\r\n] 2006.286.01:03:10.94#ibcon#*before write, iclass 38, count 2 2006.286.01:03:10.94#ibcon#enter sib2, iclass 38, count 2 2006.286.01:03:10.94#ibcon#flushed, iclass 38, count 2 2006.286.01:03:10.94#ibcon#about to write, iclass 38, count 2 2006.286.01:03:10.94#ibcon#wrote, iclass 38, count 2 2006.286.01:03:10.94#ibcon#about to read 3, iclass 38, count 2 2006.286.01:03:10.97#ibcon#read 3, iclass 38, count 2 2006.286.01:03:10.97#ibcon#about to read 4, iclass 38, count 2 2006.286.01:03:10.97#ibcon#read 4, iclass 38, count 2 2006.286.01:03:10.97#ibcon#about to read 5, iclass 38, count 2 2006.286.01:03:10.97#ibcon#read 5, iclass 38, count 2 2006.286.01:03:10.97#ibcon#about to read 6, iclass 38, count 2 2006.286.01:03:10.97#ibcon#read 6, iclass 38, count 2 2006.286.01:03:10.97#ibcon#end of sib2, iclass 38, count 2 2006.286.01:03:10.97#ibcon#*after write, iclass 38, count 2 2006.286.01:03:10.97#ibcon#*before return 0, iclass 38, count 2 2006.286.01:03:10.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:03:10.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:03:10.97#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.01:03:10.97#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:10.97#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:03:11.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:03:11.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:03:11.09#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:03:11.09#ibcon#first serial, iclass 38, count 0 2006.286.01:03:11.09#ibcon#enter sib2, iclass 38, count 0 2006.286.01:03:11.09#ibcon#flushed, iclass 38, count 0 2006.286.01:03:11.09#ibcon#about to write, iclass 38, count 0 2006.286.01:03:11.09#ibcon#wrote, iclass 38, count 0 2006.286.01:03:11.09#ibcon#about to read 3, iclass 38, count 0 2006.286.01:03:11.11#ibcon#read 3, iclass 38, count 0 2006.286.01:03:11.11#ibcon#about to read 4, iclass 38, count 0 2006.286.01:03:11.11#ibcon#read 4, iclass 38, count 0 2006.286.01:03:11.11#ibcon#about to read 5, iclass 38, count 0 2006.286.01:03:11.11#ibcon#read 5, iclass 38, count 0 2006.286.01:03:11.11#ibcon#about to read 6, iclass 38, count 0 2006.286.01:03:11.11#ibcon#read 6, iclass 38, count 0 2006.286.01:03:11.11#ibcon#end of sib2, iclass 38, count 0 2006.286.01:03:11.11#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:03:11.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:03:11.11#ibcon#[25=USB\r\n] 2006.286.01:03:11.11#ibcon#*before write, iclass 38, count 0 2006.286.01:03:11.11#ibcon#enter sib2, iclass 38, count 0 2006.286.01:03:11.11#ibcon#flushed, iclass 38, count 0 2006.286.01:03:11.11#ibcon#about to write, iclass 38, count 0 2006.286.01:03:11.11#ibcon#wrote, iclass 38, count 0 2006.286.01:03:11.11#ibcon#about to read 3, iclass 38, count 0 2006.286.01:03:11.14#ibcon#read 3, iclass 38, count 0 2006.286.01:03:11.14#ibcon#about to read 4, iclass 38, count 0 2006.286.01:03:11.14#ibcon#read 4, iclass 38, count 0 2006.286.01:03:11.14#ibcon#about to read 5, iclass 38, count 0 2006.286.01:03:11.14#ibcon#read 5, iclass 38, count 0 2006.286.01:03:11.14#ibcon#about to read 6, iclass 38, count 0 2006.286.01:03:11.14#ibcon#read 6, iclass 38, count 0 2006.286.01:03:11.14#ibcon#end of sib2, iclass 38, count 0 2006.286.01:03:11.14#ibcon#*after write, iclass 38, count 0 2006.286.01:03:11.14#ibcon#*before return 0, iclass 38, count 0 2006.286.01:03:11.14#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:03:11.14#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:03:11.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:03:11.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:03:11.14$vck44/valo=6,814.99 2006.286.01:03:11.14#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.01:03:11.14#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.01:03:11.14#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:11.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:03:11.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:03:11.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:03:11.14#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:03:11.14#ibcon#first serial, iclass 40, count 0 2006.286.01:03:11.14#ibcon#enter sib2, iclass 40, count 0 2006.286.01:03:11.14#ibcon#flushed, iclass 40, count 0 2006.286.01:03:11.14#ibcon#about to write, iclass 40, count 0 2006.286.01:03:11.14#ibcon#wrote, iclass 40, count 0 2006.286.01:03:11.14#ibcon#about to read 3, iclass 40, count 0 2006.286.01:03:11.16#ibcon#read 3, iclass 40, count 0 2006.286.01:03:11.16#ibcon#about to read 4, iclass 40, count 0 2006.286.01:03:11.16#ibcon#read 4, iclass 40, count 0 2006.286.01:03:11.16#ibcon#about to read 5, iclass 40, count 0 2006.286.01:03:11.16#ibcon#read 5, iclass 40, count 0 2006.286.01:03:11.16#ibcon#about to read 6, iclass 40, count 0 2006.286.01:03:11.16#ibcon#read 6, iclass 40, count 0 2006.286.01:03:11.16#ibcon#end of sib2, iclass 40, count 0 2006.286.01:03:11.16#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:03:11.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:03:11.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:03:11.16#ibcon#*before write, iclass 40, count 0 2006.286.01:03:11.16#ibcon#enter sib2, iclass 40, count 0 2006.286.01:03:11.16#ibcon#flushed, iclass 40, count 0 2006.286.01:03:11.16#ibcon#about to write, iclass 40, count 0 2006.286.01:03:11.16#ibcon#wrote, iclass 40, count 0 2006.286.01:03:11.16#ibcon#about to read 3, iclass 40, count 0 2006.286.01:03:11.20#ibcon#read 3, iclass 40, count 0 2006.286.01:03:11.20#ibcon#about to read 4, iclass 40, count 0 2006.286.01:03:11.20#ibcon#read 4, iclass 40, count 0 2006.286.01:03:11.20#ibcon#about to read 5, iclass 40, count 0 2006.286.01:03:11.20#ibcon#read 5, iclass 40, count 0 2006.286.01:03:11.20#ibcon#about to read 6, iclass 40, count 0 2006.286.01:03:11.20#ibcon#read 6, iclass 40, count 0 2006.286.01:03:11.20#ibcon#end of sib2, iclass 40, count 0 2006.286.01:03:11.20#ibcon#*after write, iclass 40, count 0 2006.286.01:03:11.20#ibcon#*before return 0, iclass 40, count 0 2006.286.01:03:11.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:03:11.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:03:11.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:03:11.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:03:11.20$vck44/va=6,4 2006.286.01:03:11.20#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.01:03:11.20#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.01:03:11.20#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:11.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:03:11.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:03:11.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:03:11.26#ibcon#enter wrdev, iclass 4, count 2 2006.286.01:03:11.26#ibcon#first serial, iclass 4, count 2 2006.286.01:03:11.26#ibcon#enter sib2, iclass 4, count 2 2006.286.01:03:11.26#ibcon#flushed, iclass 4, count 2 2006.286.01:03:11.26#ibcon#about to write, iclass 4, count 2 2006.286.01:03:11.26#ibcon#wrote, iclass 4, count 2 2006.286.01:03:11.26#ibcon#about to read 3, iclass 4, count 2 2006.286.01:03:11.28#ibcon#read 3, iclass 4, count 2 2006.286.01:03:11.28#ibcon#about to read 4, iclass 4, count 2 2006.286.01:03:11.28#ibcon#read 4, iclass 4, count 2 2006.286.01:03:11.28#ibcon#about to read 5, iclass 4, count 2 2006.286.01:03:11.28#ibcon#read 5, iclass 4, count 2 2006.286.01:03:11.28#ibcon#about to read 6, iclass 4, count 2 2006.286.01:03:11.28#ibcon#read 6, iclass 4, count 2 2006.286.01:03:11.28#ibcon#end of sib2, iclass 4, count 2 2006.286.01:03:11.28#ibcon#*mode == 0, iclass 4, count 2 2006.286.01:03:11.28#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.01:03:11.28#ibcon#[25=AT06-04\r\n] 2006.286.01:03:11.28#ibcon#*before write, iclass 4, count 2 2006.286.01:03:11.28#ibcon#enter sib2, iclass 4, count 2 2006.286.01:03:11.28#ibcon#flushed, iclass 4, count 2 2006.286.01:03:11.28#ibcon#about to write, iclass 4, count 2 2006.286.01:03:11.28#ibcon#wrote, iclass 4, count 2 2006.286.01:03:11.28#ibcon#about to read 3, iclass 4, count 2 2006.286.01:03:11.31#ibcon#read 3, iclass 4, count 2 2006.286.01:03:11.31#ibcon#about to read 4, iclass 4, count 2 2006.286.01:03:11.31#ibcon#read 4, iclass 4, count 2 2006.286.01:03:11.31#ibcon#about to read 5, iclass 4, count 2 2006.286.01:03:11.31#ibcon#read 5, iclass 4, count 2 2006.286.01:03:11.31#ibcon#about to read 6, iclass 4, count 2 2006.286.01:03:11.31#ibcon#read 6, iclass 4, count 2 2006.286.01:03:11.31#ibcon#end of sib2, iclass 4, count 2 2006.286.01:03:11.31#ibcon#*after write, iclass 4, count 2 2006.286.01:03:11.31#ibcon#*before return 0, iclass 4, count 2 2006.286.01:03:11.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:03:11.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:03:11.31#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.01:03:11.31#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:11.31#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:03:11.43#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:03:11.43#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:03:11.43#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:03:11.43#ibcon#first serial, iclass 4, count 0 2006.286.01:03:11.43#ibcon#enter sib2, iclass 4, count 0 2006.286.01:03:11.43#ibcon#flushed, iclass 4, count 0 2006.286.01:03:11.43#ibcon#about to write, iclass 4, count 0 2006.286.01:03:11.43#ibcon#wrote, iclass 4, count 0 2006.286.01:03:11.43#ibcon#about to read 3, iclass 4, count 0 2006.286.01:03:11.45#ibcon#read 3, iclass 4, count 0 2006.286.01:03:11.45#ibcon#about to read 4, iclass 4, count 0 2006.286.01:03:11.45#ibcon#read 4, iclass 4, count 0 2006.286.01:03:11.45#ibcon#about to read 5, iclass 4, count 0 2006.286.01:03:11.45#ibcon#read 5, iclass 4, count 0 2006.286.01:03:11.45#ibcon#about to read 6, iclass 4, count 0 2006.286.01:03:11.45#ibcon#read 6, iclass 4, count 0 2006.286.01:03:11.45#ibcon#end of sib2, iclass 4, count 0 2006.286.01:03:11.45#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:03:11.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:03:11.45#ibcon#[25=USB\r\n] 2006.286.01:03:11.45#ibcon#*before write, iclass 4, count 0 2006.286.01:03:11.45#ibcon#enter sib2, iclass 4, count 0 2006.286.01:03:11.45#ibcon#flushed, iclass 4, count 0 2006.286.01:03:11.45#ibcon#about to write, iclass 4, count 0 2006.286.01:03:11.45#ibcon#wrote, iclass 4, count 0 2006.286.01:03:11.45#ibcon#about to read 3, iclass 4, count 0 2006.286.01:03:11.48#ibcon#read 3, iclass 4, count 0 2006.286.01:03:11.48#ibcon#about to read 4, iclass 4, count 0 2006.286.01:03:11.48#ibcon#read 4, iclass 4, count 0 2006.286.01:03:11.48#ibcon#about to read 5, iclass 4, count 0 2006.286.01:03:11.48#ibcon#read 5, iclass 4, count 0 2006.286.01:03:11.48#ibcon#about to read 6, iclass 4, count 0 2006.286.01:03:11.48#ibcon#read 6, iclass 4, count 0 2006.286.01:03:11.48#ibcon#end of sib2, iclass 4, count 0 2006.286.01:03:11.48#ibcon#*after write, iclass 4, count 0 2006.286.01:03:11.48#ibcon#*before return 0, iclass 4, count 0 2006.286.01:03:11.48#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:03:11.48#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:03:11.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:03:11.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:03:11.48$vck44/valo=7,864.99 2006.286.01:03:11.48#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.01:03:11.48#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.01:03:11.48#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:11.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:03:11.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:03:11.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:03:11.48#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:03:11.48#ibcon#first serial, iclass 6, count 0 2006.286.01:03:11.48#ibcon#enter sib2, iclass 6, count 0 2006.286.01:03:11.48#ibcon#flushed, iclass 6, count 0 2006.286.01:03:11.48#ibcon#about to write, iclass 6, count 0 2006.286.01:03:11.48#ibcon#wrote, iclass 6, count 0 2006.286.01:03:11.48#ibcon#about to read 3, iclass 6, count 0 2006.286.01:03:11.50#ibcon#read 3, iclass 6, count 0 2006.286.01:03:11.50#ibcon#about to read 4, iclass 6, count 0 2006.286.01:03:11.50#ibcon#read 4, iclass 6, count 0 2006.286.01:03:11.50#ibcon#about to read 5, iclass 6, count 0 2006.286.01:03:11.50#ibcon#read 5, iclass 6, count 0 2006.286.01:03:11.50#ibcon#about to read 6, iclass 6, count 0 2006.286.01:03:11.50#ibcon#read 6, iclass 6, count 0 2006.286.01:03:11.50#ibcon#end of sib2, iclass 6, count 0 2006.286.01:03:11.50#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:03:11.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:03:11.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:03:11.50#ibcon#*before write, iclass 6, count 0 2006.286.01:03:11.50#ibcon#enter sib2, iclass 6, count 0 2006.286.01:03:11.50#ibcon#flushed, iclass 6, count 0 2006.286.01:03:11.50#ibcon#about to write, iclass 6, count 0 2006.286.01:03:11.50#ibcon#wrote, iclass 6, count 0 2006.286.01:03:11.50#ibcon#about to read 3, iclass 6, count 0 2006.286.01:03:11.54#ibcon#read 3, iclass 6, count 0 2006.286.01:03:11.54#ibcon#about to read 4, iclass 6, count 0 2006.286.01:03:11.54#ibcon#read 4, iclass 6, count 0 2006.286.01:03:11.54#ibcon#about to read 5, iclass 6, count 0 2006.286.01:03:11.54#ibcon#read 5, iclass 6, count 0 2006.286.01:03:11.54#ibcon#about to read 6, iclass 6, count 0 2006.286.01:03:11.54#ibcon#read 6, iclass 6, count 0 2006.286.01:03:11.54#ibcon#end of sib2, iclass 6, count 0 2006.286.01:03:11.54#ibcon#*after write, iclass 6, count 0 2006.286.01:03:11.54#ibcon#*before return 0, iclass 6, count 0 2006.286.01:03:11.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:03:11.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:03:11.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:03:11.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:03:11.54$vck44/va=7,4 2006.286.01:03:11.54#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.01:03:11.54#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.01:03:11.54#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:11.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:03:11.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:03:11.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:03:11.60#ibcon#enter wrdev, iclass 10, count 2 2006.286.01:03:11.60#ibcon#first serial, iclass 10, count 2 2006.286.01:03:11.60#ibcon#enter sib2, iclass 10, count 2 2006.286.01:03:11.60#ibcon#flushed, iclass 10, count 2 2006.286.01:03:11.60#ibcon#about to write, iclass 10, count 2 2006.286.01:03:11.60#ibcon#wrote, iclass 10, count 2 2006.286.01:03:11.60#ibcon#about to read 3, iclass 10, count 2 2006.286.01:03:11.62#ibcon#read 3, iclass 10, count 2 2006.286.01:03:11.62#ibcon#about to read 4, iclass 10, count 2 2006.286.01:03:11.62#ibcon#read 4, iclass 10, count 2 2006.286.01:03:11.62#ibcon#about to read 5, iclass 10, count 2 2006.286.01:03:11.62#ibcon#read 5, iclass 10, count 2 2006.286.01:03:11.62#ibcon#about to read 6, iclass 10, count 2 2006.286.01:03:11.62#ibcon#read 6, iclass 10, count 2 2006.286.01:03:11.62#ibcon#end of sib2, iclass 10, count 2 2006.286.01:03:11.62#ibcon#*mode == 0, iclass 10, count 2 2006.286.01:03:11.62#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.01:03:11.62#ibcon#[25=AT07-04\r\n] 2006.286.01:03:11.62#ibcon#*before write, iclass 10, count 2 2006.286.01:03:11.62#ibcon#enter sib2, iclass 10, count 2 2006.286.01:03:11.62#ibcon#flushed, iclass 10, count 2 2006.286.01:03:11.62#ibcon#about to write, iclass 10, count 2 2006.286.01:03:11.62#ibcon#wrote, iclass 10, count 2 2006.286.01:03:11.62#ibcon#about to read 3, iclass 10, count 2 2006.286.01:03:11.65#ibcon#read 3, iclass 10, count 2 2006.286.01:03:11.65#ibcon#about to read 4, iclass 10, count 2 2006.286.01:03:11.65#ibcon#read 4, iclass 10, count 2 2006.286.01:03:11.65#ibcon#about to read 5, iclass 10, count 2 2006.286.01:03:11.65#ibcon#read 5, iclass 10, count 2 2006.286.01:03:11.65#ibcon#about to read 6, iclass 10, count 2 2006.286.01:03:11.65#ibcon#read 6, iclass 10, count 2 2006.286.01:03:11.65#ibcon#end of sib2, iclass 10, count 2 2006.286.01:03:11.65#ibcon#*after write, iclass 10, count 2 2006.286.01:03:11.65#ibcon#*before return 0, iclass 10, count 2 2006.286.01:03:11.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:03:11.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:03:11.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.01:03:11.65#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:11.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:03:11.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:03:11.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:03:11.77#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:03:11.77#ibcon#first serial, iclass 10, count 0 2006.286.01:03:11.77#ibcon#enter sib2, iclass 10, count 0 2006.286.01:03:11.77#ibcon#flushed, iclass 10, count 0 2006.286.01:03:11.77#ibcon#about to write, iclass 10, count 0 2006.286.01:03:11.77#ibcon#wrote, iclass 10, count 0 2006.286.01:03:11.77#ibcon#about to read 3, iclass 10, count 0 2006.286.01:03:11.79#ibcon#read 3, iclass 10, count 0 2006.286.01:03:11.79#ibcon#about to read 4, iclass 10, count 0 2006.286.01:03:11.79#ibcon#read 4, iclass 10, count 0 2006.286.01:03:11.79#ibcon#about to read 5, iclass 10, count 0 2006.286.01:03:11.79#ibcon#read 5, iclass 10, count 0 2006.286.01:03:11.79#ibcon#about to read 6, iclass 10, count 0 2006.286.01:03:11.79#ibcon#read 6, iclass 10, count 0 2006.286.01:03:11.79#ibcon#end of sib2, iclass 10, count 0 2006.286.01:03:11.79#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:03:11.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:03:11.79#ibcon#[25=USB\r\n] 2006.286.01:03:11.79#ibcon#*before write, iclass 10, count 0 2006.286.01:03:11.79#ibcon#enter sib2, iclass 10, count 0 2006.286.01:03:11.79#ibcon#flushed, iclass 10, count 0 2006.286.01:03:11.79#ibcon#about to write, iclass 10, count 0 2006.286.01:03:11.79#ibcon#wrote, iclass 10, count 0 2006.286.01:03:11.79#ibcon#about to read 3, iclass 10, count 0 2006.286.01:03:11.82#ibcon#read 3, iclass 10, count 0 2006.286.01:03:11.82#ibcon#about to read 4, iclass 10, count 0 2006.286.01:03:11.82#ibcon#read 4, iclass 10, count 0 2006.286.01:03:11.82#ibcon#about to read 5, iclass 10, count 0 2006.286.01:03:11.82#ibcon#read 5, iclass 10, count 0 2006.286.01:03:11.82#ibcon#about to read 6, iclass 10, count 0 2006.286.01:03:11.82#ibcon#read 6, iclass 10, count 0 2006.286.01:03:11.82#ibcon#end of sib2, iclass 10, count 0 2006.286.01:03:11.82#ibcon#*after write, iclass 10, count 0 2006.286.01:03:11.82#ibcon#*before return 0, iclass 10, count 0 2006.286.01:03:11.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:03:11.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:03:11.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:03:11.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:03:11.82$vck44/valo=8,884.99 2006.286.01:03:11.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.01:03:11.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.01:03:11.82#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:11.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:03:11.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:03:11.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:03:11.82#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:03:11.82#ibcon#first serial, iclass 12, count 0 2006.286.01:03:11.82#ibcon#enter sib2, iclass 12, count 0 2006.286.01:03:11.82#ibcon#flushed, iclass 12, count 0 2006.286.01:03:11.82#ibcon#about to write, iclass 12, count 0 2006.286.01:03:11.82#ibcon#wrote, iclass 12, count 0 2006.286.01:03:11.82#ibcon#about to read 3, iclass 12, count 0 2006.286.01:03:11.84#ibcon#read 3, iclass 12, count 0 2006.286.01:03:11.84#ibcon#about to read 4, iclass 12, count 0 2006.286.01:03:11.84#ibcon#read 4, iclass 12, count 0 2006.286.01:03:11.84#ibcon#about to read 5, iclass 12, count 0 2006.286.01:03:11.84#ibcon#read 5, iclass 12, count 0 2006.286.01:03:11.84#ibcon#about to read 6, iclass 12, count 0 2006.286.01:03:11.84#ibcon#read 6, iclass 12, count 0 2006.286.01:03:11.84#ibcon#end of sib2, iclass 12, count 0 2006.286.01:03:11.84#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:03:11.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:03:11.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:03:11.84#ibcon#*before write, iclass 12, count 0 2006.286.01:03:11.84#ibcon#enter sib2, iclass 12, count 0 2006.286.01:03:11.84#ibcon#flushed, iclass 12, count 0 2006.286.01:03:11.84#ibcon#about to write, iclass 12, count 0 2006.286.01:03:11.84#ibcon#wrote, iclass 12, count 0 2006.286.01:03:11.84#ibcon#about to read 3, iclass 12, count 0 2006.286.01:03:11.88#ibcon#read 3, iclass 12, count 0 2006.286.01:03:11.88#ibcon#about to read 4, iclass 12, count 0 2006.286.01:03:11.88#ibcon#read 4, iclass 12, count 0 2006.286.01:03:11.88#ibcon#about to read 5, iclass 12, count 0 2006.286.01:03:11.88#ibcon#read 5, iclass 12, count 0 2006.286.01:03:11.88#ibcon#about to read 6, iclass 12, count 0 2006.286.01:03:11.88#ibcon#read 6, iclass 12, count 0 2006.286.01:03:11.88#ibcon#end of sib2, iclass 12, count 0 2006.286.01:03:11.88#ibcon#*after write, iclass 12, count 0 2006.286.01:03:11.88#ibcon#*before return 0, iclass 12, count 0 2006.286.01:03:11.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:03:11.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:03:11.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:03:11.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:03:11.88$vck44/va=8,3 2006.286.01:03:11.88#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.01:03:11.88#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.01:03:11.88#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:11.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:03:11.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:03:11.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:03:11.94#ibcon#enter wrdev, iclass 14, count 2 2006.286.01:03:11.94#ibcon#first serial, iclass 14, count 2 2006.286.01:03:11.94#ibcon#enter sib2, iclass 14, count 2 2006.286.01:03:11.94#ibcon#flushed, iclass 14, count 2 2006.286.01:03:11.94#ibcon#about to write, iclass 14, count 2 2006.286.01:03:11.94#ibcon#wrote, iclass 14, count 2 2006.286.01:03:11.94#ibcon#about to read 3, iclass 14, count 2 2006.286.01:03:11.96#ibcon#read 3, iclass 14, count 2 2006.286.01:03:11.96#ibcon#about to read 4, iclass 14, count 2 2006.286.01:03:11.96#ibcon#read 4, iclass 14, count 2 2006.286.01:03:11.96#ibcon#about to read 5, iclass 14, count 2 2006.286.01:03:11.96#ibcon#read 5, iclass 14, count 2 2006.286.01:03:11.96#ibcon#about to read 6, iclass 14, count 2 2006.286.01:03:11.96#ibcon#read 6, iclass 14, count 2 2006.286.01:03:11.96#ibcon#end of sib2, iclass 14, count 2 2006.286.01:03:11.96#ibcon#*mode == 0, iclass 14, count 2 2006.286.01:03:11.96#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.01:03:11.96#ibcon#[25=AT08-03\r\n] 2006.286.01:03:11.96#ibcon#*before write, iclass 14, count 2 2006.286.01:03:11.96#ibcon#enter sib2, iclass 14, count 2 2006.286.01:03:11.96#ibcon#flushed, iclass 14, count 2 2006.286.01:03:11.96#ibcon#about to write, iclass 14, count 2 2006.286.01:03:11.96#ibcon#wrote, iclass 14, count 2 2006.286.01:03:11.96#ibcon#about to read 3, iclass 14, count 2 2006.286.01:03:11.99#ibcon#read 3, iclass 14, count 2 2006.286.01:03:11.99#ibcon#about to read 4, iclass 14, count 2 2006.286.01:03:11.99#ibcon#read 4, iclass 14, count 2 2006.286.01:03:11.99#ibcon#about to read 5, iclass 14, count 2 2006.286.01:03:11.99#ibcon#read 5, iclass 14, count 2 2006.286.01:03:11.99#ibcon#about to read 6, iclass 14, count 2 2006.286.01:03:11.99#ibcon#read 6, iclass 14, count 2 2006.286.01:03:11.99#ibcon#end of sib2, iclass 14, count 2 2006.286.01:03:11.99#ibcon#*after write, iclass 14, count 2 2006.286.01:03:11.99#ibcon#*before return 0, iclass 14, count 2 2006.286.01:03:11.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:03:11.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:03:11.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.01:03:11.99#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:11.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:03:12.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:03:12.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:03:12.11#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:03:12.11#ibcon#first serial, iclass 14, count 0 2006.286.01:03:12.11#ibcon#enter sib2, iclass 14, count 0 2006.286.01:03:12.11#ibcon#flushed, iclass 14, count 0 2006.286.01:03:12.11#ibcon#about to write, iclass 14, count 0 2006.286.01:03:12.11#ibcon#wrote, iclass 14, count 0 2006.286.01:03:12.11#ibcon#about to read 3, iclass 14, count 0 2006.286.01:03:12.13#ibcon#read 3, iclass 14, count 0 2006.286.01:03:12.13#ibcon#about to read 4, iclass 14, count 0 2006.286.01:03:12.13#ibcon#read 4, iclass 14, count 0 2006.286.01:03:12.13#ibcon#about to read 5, iclass 14, count 0 2006.286.01:03:12.13#ibcon#read 5, iclass 14, count 0 2006.286.01:03:12.13#ibcon#about to read 6, iclass 14, count 0 2006.286.01:03:12.13#ibcon#read 6, iclass 14, count 0 2006.286.01:03:12.13#ibcon#end of sib2, iclass 14, count 0 2006.286.01:03:12.13#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:03:12.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:03:12.13#ibcon#[25=USB\r\n] 2006.286.01:03:12.13#ibcon#*before write, iclass 14, count 0 2006.286.01:03:12.13#ibcon#enter sib2, iclass 14, count 0 2006.286.01:03:12.13#ibcon#flushed, iclass 14, count 0 2006.286.01:03:12.13#ibcon#about to write, iclass 14, count 0 2006.286.01:03:12.13#ibcon#wrote, iclass 14, count 0 2006.286.01:03:12.13#ibcon#about to read 3, iclass 14, count 0 2006.286.01:03:12.16#ibcon#read 3, iclass 14, count 0 2006.286.01:03:12.16#ibcon#about to read 4, iclass 14, count 0 2006.286.01:03:12.16#ibcon#read 4, iclass 14, count 0 2006.286.01:03:12.16#ibcon#about to read 5, iclass 14, count 0 2006.286.01:03:12.16#ibcon#read 5, iclass 14, count 0 2006.286.01:03:12.16#ibcon#about to read 6, iclass 14, count 0 2006.286.01:03:12.16#ibcon#read 6, iclass 14, count 0 2006.286.01:03:12.16#ibcon#end of sib2, iclass 14, count 0 2006.286.01:03:12.16#ibcon#*after write, iclass 14, count 0 2006.286.01:03:12.16#ibcon#*before return 0, iclass 14, count 0 2006.286.01:03:12.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:03:12.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:03:12.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:03:12.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:03:12.16$vck44/vblo=1,629.99 2006.286.01:03:12.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.01:03:12.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.01:03:12.16#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:12.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:03:12.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:03:12.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:03:12.16#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:03:12.16#ibcon#first serial, iclass 16, count 0 2006.286.01:03:12.16#ibcon#enter sib2, iclass 16, count 0 2006.286.01:03:12.16#ibcon#flushed, iclass 16, count 0 2006.286.01:03:12.16#ibcon#about to write, iclass 16, count 0 2006.286.01:03:12.16#ibcon#wrote, iclass 16, count 0 2006.286.01:03:12.16#ibcon#about to read 3, iclass 16, count 0 2006.286.01:03:12.18#ibcon#read 3, iclass 16, count 0 2006.286.01:03:12.18#ibcon#about to read 4, iclass 16, count 0 2006.286.01:03:12.18#ibcon#read 4, iclass 16, count 0 2006.286.01:03:12.18#ibcon#about to read 5, iclass 16, count 0 2006.286.01:03:12.18#ibcon#read 5, iclass 16, count 0 2006.286.01:03:12.18#ibcon#about to read 6, iclass 16, count 0 2006.286.01:03:12.18#ibcon#read 6, iclass 16, count 0 2006.286.01:03:12.18#ibcon#end of sib2, iclass 16, count 0 2006.286.01:03:12.18#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:03:12.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:03:12.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:03:12.18#ibcon#*before write, iclass 16, count 0 2006.286.01:03:12.18#ibcon#enter sib2, iclass 16, count 0 2006.286.01:03:12.18#ibcon#flushed, iclass 16, count 0 2006.286.01:03:12.18#ibcon#about to write, iclass 16, count 0 2006.286.01:03:12.18#ibcon#wrote, iclass 16, count 0 2006.286.01:03:12.18#ibcon#about to read 3, iclass 16, count 0 2006.286.01:03:12.22#ibcon#read 3, iclass 16, count 0 2006.286.01:03:12.22#ibcon#about to read 4, iclass 16, count 0 2006.286.01:03:12.22#ibcon#read 4, iclass 16, count 0 2006.286.01:03:12.22#ibcon#about to read 5, iclass 16, count 0 2006.286.01:03:12.22#ibcon#read 5, iclass 16, count 0 2006.286.01:03:12.22#ibcon#about to read 6, iclass 16, count 0 2006.286.01:03:12.22#ibcon#read 6, iclass 16, count 0 2006.286.01:03:12.22#ibcon#end of sib2, iclass 16, count 0 2006.286.01:03:12.22#ibcon#*after write, iclass 16, count 0 2006.286.01:03:12.22#ibcon#*before return 0, iclass 16, count 0 2006.286.01:03:12.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:03:12.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:03:12.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:03:12.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:03:12.22$vck44/vb=1,4 2006.286.01:03:12.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.01:03:12.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.01:03:12.22#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:12.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:03:12.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:03:12.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:03:12.22#ibcon#enter wrdev, iclass 18, count 2 2006.286.01:03:12.22#ibcon#first serial, iclass 18, count 2 2006.286.01:03:12.22#ibcon#enter sib2, iclass 18, count 2 2006.286.01:03:12.22#ibcon#flushed, iclass 18, count 2 2006.286.01:03:12.22#ibcon#about to write, iclass 18, count 2 2006.286.01:03:12.22#ibcon#wrote, iclass 18, count 2 2006.286.01:03:12.22#ibcon#about to read 3, iclass 18, count 2 2006.286.01:03:12.24#ibcon#read 3, iclass 18, count 2 2006.286.01:03:12.24#ibcon#about to read 4, iclass 18, count 2 2006.286.01:03:12.24#ibcon#read 4, iclass 18, count 2 2006.286.01:03:12.24#ibcon#about to read 5, iclass 18, count 2 2006.286.01:03:12.24#ibcon#read 5, iclass 18, count 2 2006.286.01:03:12.24#ibcon#about to read 6, iclass 18, count 2 2006.286.01:03:12.24#ibcon#read 6, iclass 18, count 2 2006.286.01:03:12.24#ibcon#end of sib2, iclass 18, count 2 2006.286.01:03:12.24#ibcon#*mode == 0, iclass 18, count 2 2006.286.01:03:12.24#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.01:03:12.24#ibcon#[27=AT01-04\r\n] 2006.286.01:03:12.24#ibcon#*before write, iclass 18, count 2 2006.286.01:03:12.24#ibcon#enter sib2, iclass 18, count 2 2006.286.01:03:12.24#ibcon#flushed, iclass 18, count 2 2006.286.01:03:12.24#ibcon#about to write, iclass 18, count 2 2006.286.01:03:12.24#ibcon#wrote, iclass 18, count 2 2006.286.01:03:12.24#ibcon#about to read 3, iclass 18, count 2 2006.286.01:03:12.27#ibcon#read 3, iclass 18, count 2 2006.286.01:03:12.27#ibcon#about to read 4, iclass 18, count 2 2006.286.01:03:12.27#ibcon#read 4, iclass 18, count 2 2006.286.01:03:12.27#ibcon#about to read 5, iclass 18, count 2 2006.286.01:03:12.27#ibcon#read 5, iclass 18, count 2 2006.286.01:03:12.27#ibcon#about to read 6, iclass 18, count 2 2006.286.01:03:12.27#ibcon#read 6, iclass 18, count 2 2006.286.01:03:12.27#ibcon#end of sib2, iclass 18, count 2 2006.286.01:03:12.27#ibcon#*after write, iclass 18, count 2 2006.286.01:03:12.27#ibcon#*before return 0, iclass 18, count 2 2006.286.01:03:12.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:03:12.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:03:12.27#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.01:03:12.27#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:12.27#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:03:12.39#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:03:12.39#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:03:12.39#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:03:12.39#ibcon#first serial, iclass 18, count 0 2006.286.01:03:12.39#ibcon#enter sib2, iclass 18, count 0 2006.286.01:03:12.39#ibcon#flushed, iclass 18, count 0 2006.286.01:03:12.39#ibcon#about to write, iclass 18, count 0 2006.286.01:03:12.39#ibcon#wrote, iclass 18, count 0 2006.286.01:03:12.39#ibcon#about to read 3, iclass 18, count 0 2006.286.01:03:12.41#ibcon#read 3, iclass 18, count 0 2006.286.01:03:12.41#ibcon#about to read 4, iclass 18, count 0 2006.286.01:03:12.41#ibcon#read 4, iclass 18, count 0 2006.286.01:03:12.41#ibcon#about to read 5, iclass 18, count 0 2006.286.01:03:12.41#ibcon#read 5, iclass 18, count 0 2006.286.01:03:12.41#ibcon#about to read 6, iclass 18, count 0 2006.286.01:03:12.41#ibcon#read 6, iclass 18, count 0 2006.286.01:03:12.41#ibcon#end of sib2, iclass 18, count 0 2006.286.01:03:12.41#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:03:12.41#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:03:12.41#ibcon#[27=USB\r\n] 2006.286.01:03:12.41#ibcon#*before write, iclass 18, count 0 2006.286.01:03:12.41#ibcon#enter sib2, iclass 18, count 0 2006.286.01:03:12.41#ibcon#flushed, iclass 18, count 0 2006.286.01:03:12.41#ibcon#about to write, iclass 18, count 0 2006.286.01:03:12.41#ibcon#wrote, iclass 18, count 0 2006.286.01:03:12.41#ibcon#about to read 3, iclass 18, count 0 2006.286.01:03:12.44#ibcon#read 3, iclass 18, count 0 2006.286.01:03:12.44#ibcon#about to read 4, iclass 18, count 0 2006.286.01:03:12.44#ibcon#read 4, iclass 18, count 0 2006.286.01:03:12.44#ibcon#about to read 5, iclass 18, count 0 2006.286.01:03:12.44#ibcon#read 5, iclass 18, count 0 2006.286.01:03:12.44#ibcon#about to read 6, iclass 18, count 0 2006.286.01:03:12.44#ibcon#read 6, iclass 18, count 0 2006.286.01:03:12.44#ibcon#end of sib2, iclass 18, count 0 2006.286.01:03:12.44#ibcon#*after write, iclass 18, count 0 2006.286.01:03:12.44#ibcon#*before return 0, iclass 18, count 0 2006.286.01:03:12.44#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:03:12.44#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:03:12.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:03:12.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:03:12.44$vck44/vblo=2,634.99 2006.286.01:03:12.44#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.01:03:12.44#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.01:03:12.44#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:12.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:03:12.44#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:03:12.44#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:03:12.44#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:03:12.44#ibcon#first serial, iclass 20, count 0 2006.286.01:03:12.44#ibcon#enter sib2, iclass 20, count 0 2006.286.01:03:12.44#ibcon#flushed, iclass 20, count 0 2006.286.01:03:12.44#ibcon#about to write, iclass 20, count 0 2006.286.01:03:12.44#ibcon#wrote, iclass 20, count 0 2006.286.01:03:12.44#ibcon#about to read 3, iclass 20, count 0 2006.286.01:03:12.46#ibcon#read 3, iclass 20, count 0 2006.286.01:03:12.46#ibcon#about to read 4, iclass 20, count 0 2006.286.01:03:12.46#ibcon#read 4, iclass 20, count 0 2006.286.01:03:12.46#ibcon#about to read 5, iclass 20, count 0 2006.286.01:03:12.46#ibcon#read 5, iclass 20, count 0 2006.286.01:03:12.46#ibcon#about to read 6, iclass 20, count 0 2006.286.01:03:12.46#ibcon#read 6, iclass 20, count 0 2006.286.01:03:12.46#ibcon#end of sib2, iclass 20, count 0 2006.286.01:03:12.46#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:03:12.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:03:12.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:03:12.46#ibcon#*before write, iclass 20, count 0 2006.286.01:03:12.46#ibcon#enter sib2, iclass 20, count 0 2006.286.01:03:12.46#ibcon#flushed, iclass 20, count 0 2006.286.01:03:12.46#ibcon#about to write, iclass 20, count 0 2006.286.01:03:12.46#ibcon#wrote, iclass 20, count 0 2006.286.01:03:12.46#ibcon#about to read 3, iclass 20, count 0 2006.286.01:03:12.50#ibcon#read 3, iclass 20, count 0 2006.286.01:03:12.50#ibcon#about to read 4, iclass 20, count 0 2006.286.01:03:12.50#ibcon#read 4, iclass 20, count 0 2006.286.01:03:12.50#ibcon#about to read 5, iclass 20, count 0 2006.286.01:03:12.50#ibcon#read 5, iclass 20, count 0 2006.286.01:03:12.50#ibcon#about to read 6, iclass 20, count 0 2006.286.01:03:12.50#ibcon#read 6, iclass 20, count 0 2006.286.01:03:12.50#ibcon#end of sib2, iclass 20, count 0 2006.286.01:03:12.50#ibcon#*after write, iclass 20, count 0 2006.286.01:03:12.50#ibcon#*before return 0, iclass 20, count 0 2006.286.01:03:12.50#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:03:12.50#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:03:12.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:03:12.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:03:12.50$vck44/vb=2,5 2006.286.01:03:12.50#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.01:03:12.50#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.01:03:12.50#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:12.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:03:12.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:03:12.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:03:12.56#ibcon#enter wrdev, iclass 22, count 2 2006.286.01:03:12.56#ibcon#first serial, iclass 22, count 2 2006.286.01:03:12.56#ibcon#enter sib2, iclass 22, count 2 2006.286.01:03:12.56#ibcon#flushed, iclass 22, count 2 2006.286.01:03:12.56#ibcon#about to write, iclass 22, count 2 2006.286.01:03:12.56#ibcon#wrote, iclass 22, count 2 2006.286.01:03:12.56#ibcon#about to read 3, iclass 22, count 2 2006.286.01:03:12.58#ibcon#read 3, iclass 22, count 2 2006.286.01:03:12.58#ibcon#about to read 4, iclass 22, count 2 2006.286.01:03:12.58#ibcon#read 4, iclass 22, count 2 2006.286.01:03:12.58#ibcon#about to read 5, iclass 22, count 2 2006.286.01:03:12.58#ibcon#read 5, iclass 22, count 2 2006.286.01:03:12.58#ibcon#about to read 6, iclass 22, count 2 2006.286.01:03:12.58#ibcon#read 6, iclass 22, count 2 2006.286.01:03:12.58#ibcon#end of sib2, iclass 22, count 2 2006.286.01:03:12.58#ibcon#*mode == 0, iclass 22, count 2 2006.286.01:03:12.58#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.01:03:12.58#ibcon#[27=AT02-05\r\n] 2006.286.01:03:12.58#ibcon#*before write, iclass 22, count 2 2006.286.01:03:12.58#ibcon#enter sib2, iclass 22, count 2 2006.286.01:03:12.58#ibcon#flushed, iclass 22, count 2 2006.286.01:03:12.58#ibcon#about to write, iclass 22, count 2 2006.286.01:03:12.58#ibcon#wrote, iclass 22, count 2 2006.286.01:03:12.58#ibcon#about to read 3, iclass 22, count 2 2006.286.01:03:12.61#ibcon#read 3, iclass 22, count 2 2006.286.01:03:12.61#ibcon#about to read 4, iclass 22, count 2 2006.286.01:03:12.61#ibcon#read 4, iclass 22, count 2 2006.286.01:03:12.61#ibcon#about to read 5, iclass 22, count 2 2006.286.01:03:12.61#ibcon#read 5, iclass 22, count 2 2006.286.01:03:12.61#ibcon#about to read 6, iclass 22, count 2 2006.286.01:03:12.61#ibcon#read 6, iclass 22, count 2 2006.286.01:03:12.61#ibcon#end of sib2, iclass 22, count 2 2006.286.01:03:12.61#ibcon#*after write, iclass 22, count 2 2006.286.01:03:12.61#ibcon#*before return 0, iclass 22, count 2 2006.286.01:03:12.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:03:12.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:03:12.61#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.01:03:12.61#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:12.61#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:03:12.73#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:03:12.73#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:03:12.73#ibcon#enter wrdev, iclass 22, count 0 2006.286.01:03:12.73#ibcon#first serial, iclass 22, count 0 2006.286.01:03:12.73#ibcon#enter sib2, iclass 22, count 0 2006.286.01:03:12.73#ibcon#flushed, iclass 22, count 0 2006.286.01:03:12.73#ibcon#about to write, iclass 22, count 0 2006.286.01:03:12.73#ibcon#wrote, iclass 22, count 0 2006.286.01:03:12.73#ibcon#about to read 3, iclass 22, count 0 2006.286.01:03:12.75#ibcon#read 3, iclass 22, count 0 2006.286.01:03:12.75#ibcon#about to read 4, iclass 22, count 0 2006.286.01:03:12.75#ibcon#read 4, iclass 22, count 0 2006.286.01:03:12.75#ibcon#about to read 5, iclass 22, count 0 2006.286.01:03:12.75#ibcon#read 5, iclass 22, count 0 2006.286.01:03:12.75#ibcon#about to read 6, iclass 22, count 0 2006.286.01:03:12.75#ibcon#read 6, iclass 22, count 0 2006.286.01:03:12.75#ibcon#end of sib2, iclass 22, count 0 2006.286.01:03:12.75#ibcon#*mode == 0, iclass 22, count 0 2006.286.01:03:12.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.01:03:12.75#ibcon#[27=USB\r\n] 2006.286.01:03:12.75#ibcon#*before write, iclass 22, count 0 2006.286.01:03:12.75#ibcon#enter sib2, iclass 22, count 0 2006.286.01:03:12.75#ibcon#flushed, iclass 22, count 0 2006.286.01:03:12.75#ibcon#about to write, iclass 22, count 0 2006.286.01:03:12.75#ibcon#wrote, iclass 22, count 0 2006.286.01:03:12.75#ibcon#about to read 3, iclass 22, count 0 2006.286.01:03:12.78#ibcon#read 3, iclass 22, count 0 2006.286.01:03:12.78#ibcon#about to read 4, iclass 22, count 0 2006.286.01:03:12.78#ibcon#read 4, iclass 22, count 0 2006.286.01:03:12.78#ibcon#about to read 5, iclass 22, count 0 2006.286.01:03:12.78#ibcon#read 5, iclass 22, count 0 2006.286.01:03:12.78#ibcon#about to read 6, iclass 22, count 0 2006.286.01:03:12.78#ibcon#read 6, iclass 22, count 0 2006.286.01:03:12.78#ibcon#end of sib2, iclass 22, count 0 2006.286.01:03:12.78#ibcon#*after write, iclass 22, count 0 2006.286.01:03:12.78#ibcon#*before return 0, iclass 22, count 0 2006.286.01:03:12.78#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:03:12.78#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:03:12.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.01:03:12.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.01:03:12.78$vck44/vblo=3,649.99 2006.286.01:03:12.78#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.01:03:12.78#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.01:03:12.78#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:12.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:03:12.78#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:03:12.78#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:03:12.78#ibcon#enter wrdev, iclass 24, count 0 2006.286.01:03:12.78#ibcon#first serial, iclass 24, count 0 2006.286.01:03:12.78#ibcon#enter sib2, iclass 24, count 0 2006.286.01:03:12.78#ibcon#flushed, iclass 24, count 0 2006.286.01:03:12.78#ibcon#about to write, iclass 24, count 0 2006.286.01:03:12.78#ibcon#wrote, iclass 24, count 0 2006.286.01:03:12.78#ibcon#about to read 3, iclass 24, count 0 2006.286.01:03:12.80#ibcon#read 3, iclass 24, count 0 2006.286.01:03:12.80#ibcon#about to read 4, iclass 24, count 0 2006.286.01:03:12.80#ibcon#read 4, iclass 24, count 0 2006.286.01:03:12.80#ibcon#about to read 5, iclass 24, count 0 2006.286.01:03:12.80#ibcon#read 5, iclass 24, count 0 2006.286.01:03:12.80#ibcon#about to read 6, iclass 24, count 0 2006.286.01:03:12.80#ibcon#read 6, iclass 24, count 0 2006.286.01:03:12.80#ibcon#end of sib2, iclass 24, count 0 2006.286.01:03:12.80#ibcon#*mode == 0, iclass 24, count 0 2006.286.01:03:12.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.01:03:12.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:03:12.80#ibcon#*before write, iclass 24, count 0 2006.286.01:03:12.80#ibcon#enter sib2, iclass 24, count 0 2006.286.01:03:12.80#ibcon#flushed, iclass 24, count 0 2006.286.01:03:12.80#ibcon#about to write, iclass 24, count 0 2006.286.01:03:12.80#ibcon#wrote, iclass 24, count 0 2006.286.01:03:12.80#ibcon#about to read 3, iclass 24, count 0 2006.286.01:03:12.84#ibcon#read 3, iclass 24, count 0 2006.286.01:03:12.84#ibcon#about to read 4, iclass 24, count 0 2006.286.01:03:12.84#ibcon#read 4, iclass 24, count 0 2006.286.01:03:12.84#ibcon#about to read 5, iclass 24, count 0 2006.286.01:03:12.84#ibcon#read 5, iclass 24, count 0 2006.286.01:03:12.84#ibcon#about to read 6, iclass 24, count 0 2006.286.01:03:12.84#ibcon#read 6, iclass 24, count 0 2006.286.01:03:12.84#ibcon#end of sib2, iclass 24, count 0 2006.286.01:03:12.84#ibcon#*after write, iclass 24, count 0 2006.286.01:03:12.84#ibcon#*before return 0, iclass 24, count 0 2006.286.01:03:12.84#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:03:12.84#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:03:12.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.01:03:12.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.01:03:12.84$vck44/vb=3,4 2006.286.01:03:12.84#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.01:03:12.84#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.01:03:12.84#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:12.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:03:12.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:03:12.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:03:12.90#ibcon#enter wrdev, iclass 26, count 2 2006.286.01:03:12.90#ibcon#first serial, iclass 26, count 2 2006.286.01:03:12.90#ibcon#enter sib2, iclass 26, count 2 2006.286.01:03:12.90#ibcon#flushed, iclass 26, count 2 2006.286.01:03:12.90#ibcon#about to write, iclass 26, count 2 2006.286.01:03:12.90#ibcon#wrote, iclass 26, count 2 2006.286.01:03:12.90#ibcon#about to read 3, iclass 26, count 2 2006.286.01:03:12.92#ibcon#read 3, iclass 26, count 2 2006.286.01:03:12.92#ibcon#about to read 4, iclass 26, count 2 2006.286.01:03:12.92#ibcon#read 4, iclass 26, count 2 2006.286.01:03:12.92#ibcon#about to read 5, iclass 26, count 2 2006.286.01:03:12.92#ibcon#read 5, iclass 26, count 2 2006.286.01:03:12.92#ibcon#about to read 6, iclass 26, count 2 2006.286.01:03:12.92#ibcon#read 6, iclass 26, count 2 2006.286.01:03:12.92#ibcon#end of sib2, iclass 26, count 2 2006.286.01:03:12.92#ibcon#*mode == 0, iclass 26, count 2 2006.286.01:03:12.92#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.01:03:12.92#ibcon#[27=AT03-04\r\n] 2006.286.01:03:12.92#ibcon#*before write, iclass 26, count 2 2006.286.01:03:12.92#ibcon#enter sib2, iclass 26, count 2 2006.286.01:03:12.92#ibcon#flushed, iclass 26, count 2 2006.286.01:03:12.92#ibcon#about to write, iclass 26, count 2 2006.286.01:03:12.92#ibcon#wrote, iclass 26, count 2 2006.286.01:03:12.92#ibcon#about to read 3, iclass 26, count 2 2006.286.01:03:12.95#ibcon#read 3, iclass 26, count 2 2006.286.01:03:12.95#ibcon#about to read 4, iclass 26, count 2 2006.286.01:03:12.95#ibcon#read 4, iclass 26, count 2 2006.286.01:03:12.95#ibcon#about to read 5, iclass 26, count 2 2006.286.01:03:12.95#ibcon#read 5, iclass 26, count 2 2006.286.01:03:12.95#ibcon#about to read 6, iclass 26, count 2 2006.286.01:03:12.95#ibcon#read 6, iclass 26, count 2 2006.286.01:03:12.95#ibcon#end of sib2, iclass 26, count 2 2006.286.01:03:12.95#ibcon#*after write, iclass 26, count 2 2006.286.01:03:12.95#ibcon#*before return 0, iclass 26, count 2 2006.286.01:03:12.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:03:12.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:03:12.95#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.01:03:12.95#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:12.95#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:03:13.07#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:03:13.07#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:03:13.07#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:03:13.07#ibcon#first serial, iclass 26, count 0 2006.286.01:03:13.07#ibcon#enter sib2, iclass 26, count 0 2006.286.01:03:13.07#ibcon#flushed, iclass 26, count 0 2006.286.01:03:13.07#ibcon#about to write, iclass 26, count 0 2006.286.01:03:13.07#ibcon#wrote, iclass 26, count 0 2006.286.01:03:13.07#ibcon#about to read 3, iclass 26, count 0 2006.286.01:03:13.09#ibcon#read 3, iclass 26, count 0 2006.286.01:03:13.09#ibcon#about to read 4, iclass 26, count 0 2006.286.01:03:13.09#ibcon#read 4, iclass 26, count 0 2006.286.01:03:13.09#ibcon#about to read 5, iclass 26, count 0 2006.286.01:03:13.09#ibcon#read 5, iclass 26, count 0 2006.286.01:03:13.09#ibcon#about to read 6, iclass 26, count 0 2006.286.01:03:13.09#ibcon#read 6, iclass 26, count 0 2006.286.01:03:13.09#ibcon#end of sib2, iclass 26, count 0 2006.286.01:03:13.09#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:03:13.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:03:13.09#ibcon#[27=USB\r\n] 2006.286.01:03:13.09#ibcon#*before write, iclass 26, count 0 2006.286.01:03:13.09#ibcon#enter sib2, iclass 26, count 0 2006.286.01:03:13.09#ibcon#flushed, iclass 26, count 0 2006.286.01:03:13.09#ibcon#about to write, iclass 26, count 0 2006.286.01:03:13.09#ibcon#wrote, iclass 26, count 0 2006.286.01:03:13.09#ibcon#about to read 3, iclass 26, count 0 2006.286.01:03:13.12#ibcon#read 3, iclass 26, count 0 2006.286.01:03:13.12#ibcon#about to read 4, iclass 26, count 0 2006.286.01:03:13.12#ibcon#read 4, iclass 26, count 0 2006.286.01:03:13.12#ibcon#about to read 5, iclass 26, count 0 2006.286.01:03:13.12#ibcon#read 5, iclass 26, count 0 2006.286.01:03:13.12#ibcon#about to read 6, iclass 26, count 0 2006.286.01:03:13.12#ibcon#read 6, iclass 26, count 0 2006.286.01:03:13.12#ibcon#end of sib2, iclass 26, count 0 2006.286.01:03:13.12#ibcon#*after write, iclass 26, count 0 2006.286.01:03:13.12#ibcon#*before return 0, iclass 26, count 0 2006.286.01:03:13.12#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:03:13.12#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:03:13.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:03:13.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:03:13.12$vck44/vblo=4,679.99 2006.286.01:03:13.12#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.01:03:13.12#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.01:03:13.12#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:13.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:03:13.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:03:13.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:03:13.12#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:03:13.12#ibcon#first serial, iclass 28, count 0 2006.286.01:03:13.12#ibcon#enter sib2, iclass 28, count 0 2006.286.01:03:13.12#ibcon#flushed, iclass 28, count 0 2006.286.01:03:13.12#ibcon#about to write, iclass 28, count 0 2006.286.01:03:13.12#ibcon#wrote, iclass 28, count 0 2006.286.01:03:13.12#ibcon#about to read 3, iclass 28, count 0 2006.286.01:03:13.14#ibcon#read 3, iclass 28, count 0 2006.286.01:03:13.14#ibcon#about to read 4, iclass 28, count 0 2006.286.01:03:13.14#ibcon#read 4, iclass 28, count 0 2006.286.01:03:13.14#ibcon#about to read 5, iclass 28, count 0 2006.286.01:03:13.14#ibcon#read 5, iclass 28, count 0 2006.286.01:03:13.14#ibcon#about to read 6, iclass 28, count 0 2006.286.01:03:13.14#ibcon#read 6, iclass 28, count 0 2006.286.01:03:13.14#ibcon#end of sib2, iclass 28, count 0 2006.286.01:03:13.14#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:03:13.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:03:13.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:03:13.14#ibcon#*before write, iclass 28, count 0 2006.286.01:03:13.14#ibcon#enter sib2, iclass 28, count 0 2006.286.01:03:13.14#ibcon#flushed, iclass 28, count 0 2006.286.01:03:13.14#ibcon#about to write, iclass 28, count 0 2006.286.01:03:13.14#ibcon#wrote, iclass 28, count 0 2006.286.01:03:13.14#ibcon#about to read 3, iclass 28, count 0 2006.286.01:03:13.18#ibcon#read 3, iclass 28, count 0 2006.286.01:03:13.18#ibcon#about to read 4, iclass 28, count 0 2006.286.01:03:13.18#ibcon#read 4, iclass 28, count 0 2006.286.01:03:13.18#ibcon#about to read 5, iclass 28, count 0 2006.286.01:03:13.18#ibcon#read 5, iclass 28, count 0 2006.286.01:03:13.18#ibcon#about to read 6, iclass 28, count 0 2006.286.01:03:13.18#ibcon#read 6, iclass 28, count 0 2006.286.01:03:13.18#ibcon#end of sib2, iclass 28, count 0 2006.286.01:03:13.18#ibcon#*after write, iclass 28, count 0 2006.286.01:03:13.18#ibcon#*before return 0, iclass 28, count 0 2006.286.01:03:13.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:03:13.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:03:13.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:03:13.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:03:13.18$vck44/vb=4,5 2006.286.01:03:13.18#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.01:03:13.18#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.01:03:13.18#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:13.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:03:13.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:03:13.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:03:13.24#ibcon#enter wrdev, iclass 30, count 2 2006.286.01:03:13.24#ibcon#first serial, iclass 30, count 2 2006.286.01:03:13.24#ibcon#enter sib2, iclass 30, count 2 2006.286.01:03:13.24#ibcon#flushed, iclass 30, count 2 2006.286.01:03:13.24#ibcon#about to write, iclass 30, count 2 2006.286.01:03:13.24#ibcon#wrote, iclass 30, count 2 2006.286.01:03:13.24#ibcon#about to read 3, iclass 30, count 2 2006.286.01:03:13.26#ibcon#read 3, iclass 30, count 2 2006.286.01:03:13.26#ibcon#about to read 4, iclass 30, count 2 2006.286.01:03:13.26#ibcon#read 4, iclass 30, count 2 2006.286.01:03:13.26#ibcon#about to read 5, iclass 30, count 2 2006.286.01:03:13.26#ibcon#read 5, iclass 30, count 2 2006.286.01:03:13.26#ibcon#about to read 6, iclass 30, count 2 2006.286.01:03:13.26#ibcon#read 6, iclass 30, count 2 2006.286.01:03:13.26#ibcon#end of sib2, iclass 30, count 2 2006.286.01:03:13.26#ibcon#*mode == 0, iclass 30, count 2 2006.286.01:03:13.26#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.01:03:13.26#ibcon#[27=AT04-05\r\n] 2006.286.01:03:13.26#ibcon#*before write, iclass 30, count 2 2006.286.01:03:13.26#ibcon#enter sib2, iclass 30, count 2 2006.286.01:03:13.26#ibcon#flushed, iclass 30, count 2 2006.286.01:03:13.26#ibcon#about to write, iclass 30, count 2 2006.286.01:03:13.26#ibcon#wrote, iclass 30, count 2 2006.286.01:03:13.26#ibcon#about to read 3, iclass 30, count 2 2006.286.01:03:13.29#ibcon#read 3, iclass 30, count 2 2006.286.01:03:13.29#ibcon#about to read 4, iclass 30, count 2 2006.286.01:03:13.29#ibcon#read 4, iclass 30, count 2 2006.286.01:03:13.29#ibcon#about to read 5, iclass 30, count 2 2006.286.01:03:13.29#ibcon#read 5, iclass 30, count 2 2006.286.01:03:13.29#ibcon#about to read 6, iclass 30, count 2 2006.286.01:03:13.29#ibcon#read 6, iclass 30, count 2 2006.286.01:03:13.29#ibcon#end of sib2, iclass 30, count 2 2006.286.01:03:13.29#ibcon#*after write, iclass 30, count 2 2006.286.01:03:13.29#ibcon#*before return 0, iclass 30, count 2 2006.286.01:03:13.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:03:13.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:03:13.29#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.01:03:13.29#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:13.29#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:03:13.41#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:03:13.41#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:03:13.41#ibcon#enter wrdev, iclass 30, count 0 2006.286.01:03:13.41#ibcon#first serial, iclass 30, count 0 2006.286.01:03:13.41#ibcon#enter sib2, iclass 30, count 0 2006.286.01:03:13.41#ibcon#flushed, iclass 30, count 0 2006.286.01:03:13.41#ibcon#about to write, iclass 30, count 0 2006.286.01:03:13.41#ibcon#wrote, iclass 30, count 0 2006.286.01:03:13.41#ibcon#about to read 3, iclass 30, count 0 2006.286.01:03:13.43#ibcon#read 3, iclass 30, count 0 2006.286.01:03:13.43#ibcon#about to read 4, iclass 30, count 0 2006.286.01:03:13.43#ibcon#read 4, iclass 30, count 0 2006.286.01:03:13.43#ibcon#about to read 5, iclass 30, count 0 2006.286.01:03:13.43#ibcon#read 5, iclass 30, count 0 2006.286.01:03:13.43#ibcon#about to read 6, iclass 30, count 0 2006.286.01:03:13.43#ibcon#read 6, iclass 30, count 0 2006.286.01:03:13.43#ibcon#end of sib2, iclass 30, count 0 2006.286.01:03:13.43#ibcon#*mode == 0, iclass 30, count 0 2006.286.01:03:13.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.01:03:13.43#ibcon#[27=USB\r\n] 2006.286.01:03:13.43#ibcon#*before write, iclass 30, count 0 2006.286.01:03:13.43#ibcon#enter sib2, iclass 30, count 0 2006.286.01:03:13.43#ibcon#flushed, iclass 30, count 0 2006.286.01:03:13.43#ibcon#about to write, iclass 30, count 0 2006.286.01:03:13.43#ibcon#wrote, iclass 30, count 0 2006.286.01:03:13.43#ibcon#about to read 3, iclass 30, count 0 2006.286.01:03:13.46#ibcon#read 3, iclass 30, count 0 2006.286.01:03:13.46#ibcon#about to read 4, iclass 30, count 0 2006.286.01:03:13.46#ibcon#read 4, iclass 30, count 0 2006.286.01:03:13.46#ibcon#about to read 5, iclass 30, count 0 2006.286.01:03:13.46#ibcon#read 5, iclass 30, count 0 2006.286.01:03:13.46#ibcon#about to read 6, iclass 30, count 0 2006.286.01:03:13.46#ibcon#read 6, iclass 30, count 0 2006.286.01:03:13.46#ibcon#end of sib2, iclass 30, count 0 2006.286.01:03:13.46#ibcon#*after write, iclass 30, count 0 2006.286.01:03:13.46#ibcon#*before return 0, iclass 30, count 0 2006.286.01:03:13.46#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:03:13.46#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:03:13.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.01:03:13.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.01:03:13.46$vck44/vblo=5,709.99 2006.286.01:03:13.46#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.01:03:13.46#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.01:03:13.46#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:13.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:03:13.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:03:13.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:03:13.46#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:03:13.46#ibcon#first serial, iclass 32, count 0 2006.286.01:03:13.46#ibcon#enter sib2, iclass 32, count 0 2006.286.01:03:13.46#ibcon#flushed, iclass 32, count 0 2006.286.01:03:13.46#ibcon#about to write, iclass 32, count 0 2006.286.01:03:13.46#ibcon#wrote, iclass 32, count 0 2006.286.01:03:13.46#ibcon#about to read 3, iclass 32, count 0 2006.286.01:03:13.48#ibcon#read 3, iclass 32, count 0 2006.286.01:03:13.48#ibcon#about to read 4, iclass 32, count 0 2006.286.01:03:13.48#ibcon#read 4, iclass 32, count 0 2006.286.01:03:13.48#ibcon#about to read 5, iclass 32, count 0 2006.286.01:03:13.48#ibcon#read 5, iclass 32, count 0 2006.286.01:03:13.48#ibcon#about to read 6, iclass 32, count 0 2006.286.01:03:13.48#ibcon#read 6, iclass 32, count 0 2006.286.01:03:13.48#ibcon#end of sib2, iclass 32, count 0 2006.286.01:03:13.48#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:03:13.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:03:13.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:03:13.48#ibcon#*before write, iclass 32, count 0 2006.286.01:03:13.48#ibcon#enter sib2, iclass 32, count 0 2006.286.01:03:13.48#ibcon#flushed, iclass 32, count 0 2006.286.01:03:13.48#ibcon#about to write, iclass 32, count 0 2006.286.01:03:13.48#ibcon#wrote, iclass 32, count 0 2006.286.01:03:13.48#ibcon#about to read 3, iclass 32, count 0 2006.286.01:03:13.52#ibcon#read 3, iclass 32, count 0 2006.286.01:03:13.52#ibcon#about to read 4, iclass 32, count 0 2006.286.01:03:13.52#ibcon#read 4, iclass 32, count 0 2006.286.01:03:13.52#ibcon#about to read 5, iclass 32, count 0 2006.286.01:03:13.52#ibcon#read 5, iclass 32, count 0 2006.286.01:03:13.52#ibcon#about to read 6, iclass 32, count 0 2006.286.01:03:13.52#ibcon#read 6, iclass 32, count 0 2006.286.01:03:13.52#ibcon#end of sib2, iclass 32, count 0 2006.286.01:03:13.52#ibcon#*after write, iclass 32, count 0 2006.286.01:03:13.52#ibcon#*before return 0, iclass 32, count 0 2006.286.01:03:13.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:03:13.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:03:13.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:03:13.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:03:13.52$vck44/vb=5,4 2006.286.01:03:13.52#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.01:03:13.52#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.01:03:13.52#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:13.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:03:13.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:03:13.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:03:13.58#ibcon#enter wrdev, iclass 34, count 2 2006.286.01:03:13.58#ibcon#first serial, iclass 34, count 2 2006.286.01:03:13.58#ibcon#enter sib2, iclass 34, count 2 2006.286.01:03:13.58#ibcon#flushed, iclass 34, count 2 2006.286.01:03:13.58#ibcon#about to write, iclass 34, count 2 2006.286.01:03:13.58#ibcon#wrote, iclass 34, count 2 2006.286.01:03:13.58#ibcon#about to read 3, iclass 34, count 2 2006.286.01:03:13.60#ibcon#read 3, iclass 34, count 2 2006.286.01:03:13.60#ibcon#about to read 4, iclass 34, count 2 2006.286.01:03:13.60#ibcon#read 4, iclass 34, count 2 2006.286.01:03:13.60#ibcon#about to read 5, iclass 34, count 2 2006.286.01:03:13.60#ibcon#read 5, iclass 34, count 2 2006.286.01:03:13.60#ibcon#about to read 6, iclass 34, count 2 2006.286.01:03:13.60#ibcon#read 6, iclass 34, count 2 2006.286.01:03:13.60#ibcon#end of sib2, iclass 34, count 2 2006.286.01:03:13.60#ibcon#*mode == 0, iclass 34, count 2 2006.286.01:03:13.60#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.01:03:13.60#ibcon#[27=AT05-04\r\n] 2006.286.01:03:13.60#ibcon#*before write, iclass 34, count 2 2006.286.01:03:13.60#ibcon#enter sib2, iclass 34, count 2 2006.286.01:03:13.60#ibcon#flushed, iclass 34, count 2 2006.286.01:03:13.60#ibcon#about to write, iclass 34, count 2 2006.286.01:03:13.60#ibcon#wrote, iclass 34, count 2 2006.286.01:03:13.60#ibcon#about to read 3, iclass 34, count 2 2006.286.01:03:13.63#ibcon#read 3, iclass 34, count 2 2006.286.01:03:13.63#ibcon#about to read 4, iclass 34, count 2 2006.286.01:03:13.63#ibcon#read 4, iclass 34, count 2 2006.286.01:03:13.63#ibcon#about to read 5, iclass 34, count 2 2006.286.01:03:13.63#ibcon#read 5, iclass 34, count 2 2006.286.01:03:13.63#ibcon#about to read 6, iclass 34, count 2 2006.286.01:03:13.63#ibcon#read 6, iclass 34, count 2 2006.286.01:03:13.63#ibcon#end of sib2, iclass 34, count 2 2006.286.01:03:13.63#ibcon#*after write, iclass 34, count 2 2006.286.01:03:13.63#ibcon#*before return 0, iclass 34, count 2 2006.286.01:03:13.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:03:13.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:03:13.63#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.01:03:13.63#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:13.63#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:03:13.75#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:03:13.75#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:03:13.75#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:03:13.75#ibcon#first serial, iclass 34, count 0 2006.286.01:03:13.75#ibcon#enter sib2, iclass 34, count 0 2006.286.01:03:13.75#ibcon#flushed, iclass 34, count 0 2006.286.01:03:13.75#ibcon#about to write, iclass 34, count 0 2006.286.01:03:13.75#ibcon#wrote, iclass 34, count 0 2006.286.01:03:13.75#ibcon#about to read 3, iclass 34, count 0 2006.286.01:03:13.77#ibcon#read 3, iclass 34, count 0 2006.286.01:03:13.77#ibcon#about to read 4, iclass 34, count 0 2006.286.01:03:13.77#ibcon#read 4, iclass 34, count 0 2006.286.01:03:13.77#ibcon#about to read 5, iclass 34, count 0 2006.286.01:03:13.77#ibcon#read 5, iclass 34, count 0 2006.286.01:03:13.77#ibcon#about to read 6, iclass 34, count 0 2006.286.01:03:13.77#ibcon#read 6, iclass 34, count 0 2006.286.01:03:13.77#ibcon#end of sib2, iclass 34, count 0 2006.286.01:03:13.77#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:03:13.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:03:13.77#ibcon#[27=USB\r\n] 2006.286.01:03:13.77#ibcon#*before write, iclass 34, count 0 2006.286.01:03:13.77#ibcon#enter sib2, iclass 34, count 0 2006.286.01:03:13.77#ibcon#flushed, iclass 34, count 0 2006.286.01:03:13.77#ibcon#about to write, iclass 34, count 0 2006.286.01:03:13.77#ibcon#wrote, iclass 34, count 0 2006.286.01:03:13.77#ibcon#about to read 3, iclass 34, count 0 2006.286.01:03:13.80#ibcon#read 3, iclass 34, count 0 2006.286.01:03:13.80#ibcon#about to read 4, iclass 34, count 0 2006.286.01:03:13.80#ibcon#read 4, iclass 34, count 0 2006.286.01:03:13.80#ibcon#about to read 5, iclass 34, count 0 2006.286.01:03:13.80#ibcon#read 5, iclass 34, count 0 2006.286.01:03:13.80#ibcon#about to read 6, iclass 34, count 0 2006.286.01:03:13.80#ibcon#read 6, iclass 34, count 0 2006.286.01:03:13.80#ibcon#end of sib2, iclass 34, count 0 2006.286.01:03:13.80#ibcon#*after write, iclass 34, count 0 2006.286.01:03:13.80#ibcon#*before return 0, iclass 34, count 0 2006.286.01:03:13.80#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:03:13.80#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:03:13.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:03:13.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:03:13.80$vck44/vblo=6,719.99 2006.286.01:03:13.80#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.01:03:13.80#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.01:03:13.80#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:13.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:03:13.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:03:13.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:03:13.80#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:03:13.80#ibcon#first serial, iclass 36, count 0 2006.286.01:03:13.80#ibcon#enter sib2, iclass 36, count 0 2006.286.01:03:13.80#ibcon#flushed, iclass 36, count 0 2006.286.01:03:13.80#ibcon#about to write, iclass 36, count 0 2006.286.01:03:13.80#ibcon#wrote, iclass 36, count 0 2006.286.01:03:13.80#ibcon#about to read 3, iclass 36, count 0 2006.286.01:03:13.82#ibcon#read 3, iclass 36, count 0 2006.286.01:03:13.82#ibcon#about to read 4, iclass 36, count 0 2006.286.01:03:13.82#ibcon#read 4, iclass 36, count 0 2006.286.01:03:13.82#ibcon#about to read 5, iclass 36, count 0 2006.286.01:03:13.82#ibcon#read 5, iclass 36, count 0 2006.286.01:03:13.82#ibcon#about to read 6, iclass 36, count 0 2006.286.01:03:13.82#ibcon#read 6, iclass 36, count 0 2006.286.01:03:13.82#ibcon#end of sib2, iclass 36, count 0 2006.286.01:03:13.82#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:03:13.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:03:13.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:03:13.82#ibcon#*before write, iclass 36, count 0 2006.286.01:03:13.82#ibcon#enter sib2, iclass 36, count 0 2006.286.01:03:13.82#ibcon#flushed, iclass 36, count 0 2006.286.01:03:13.82#ibcon#about to write, iclass 36, count 0 2006.286.01:03:13.82#ibcon#wrote, iclass 36, count 0 2006.286.01:03:13.82#ibcon#about to read 3, iclass 36, count 0 2006.286.01:03:13.86#ibcon#read 3, iclass 36, count 0 2006.286.01:03:13.86#ibcon#about to read 4, iclass 36, count 0 2006.286.01:03:13.86#ibcon#read 4, iclass 36, count 0 2006.286.01:03:13.86#ibcon#about to read 5, iclass 36, count 0 2006.286.01:03:13.86#ibcon#read 5, iclass 36, count 0 2006.286.01:03:13.86#ibcon#about to read 6, iclass 36, count 0 2006.286.01:03:13.86#ibcon#read 6, iclass 36, count 0 2006.286.01:03:13.86#ibcon#end of sib2, iclass 36, count 0 2006.286.01:03:13.86#ibcon#*after write, iclass 36, count 0 2006.286.01:03:13.86#ibcon#*before return 0, iclass 36, count 0 2006.286.01:03:13.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:03:13.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:03:13.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:03:13.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:03:13.86$vck44/vb=6,3 2006.286.01:03:13.86#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.01:03:13.86#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.01:03:13.86#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:13.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:03:13.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:03:13.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:03:13.92#ibcon#enter wrdev, iclass 38, count 2 2006.286.01:03:13.92#ibcon#first serial, iclass 38, count 2 2006.286.01:03:13.92#ibcon#enter sib2, iclass 38, count 2 2006.286.01:03:13.92#ibcon#flushed, iclass 38, count 2 2006.286.01:03:13.92#ibcon#about to write, iclass 38, count 2 2006.286.01:03:13.92#ibcon#wrote, iclass 38, count 2 2006.286.01:03:13.92#ibcon#about to read 3, iclass 38, count 2 2006.286.01:03:13.94#ibcon#read 3, iclass 38, count 2 2006.286.01:03:13.94#ibcon#about to read 4, iclass 38, count 2 2006.286.01:03:13.94#ibcon#read 4, iclass 38, count 2 2006.286.01:03:13.94#ibcon#about to read 5, iclass 38, count 2 2006.286.01:03:13.94#ibcon#read 5, iclass 38, count 2 2006.286.01:03:13.94#ibcon#about to read 6, iclass 38, count 2 2006.286.01:03:13.94#ibcon#read 6, iclass 38, count 2 2006.286.01:03:13.94#ibcon#end of sib2, iclass 38, count 2 2006.286.01:03:13.94#ibcon#*mode == 0, iclass 38, count 2 2006.286.01:03:13.94#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.01:03:13.94#ibcon#[27=AT06-03\r\n] 2006.286.01:03:13.94#ibcon#*before write, iclass 38, count 2 2006.286.01:03:13.94#ibcon#enter sib2, iclass 38, count 2 2006.286.01:03:13.94#ibcon#flushed, iclass 38, count 2 2006.286.01:03:13.94#ibcon#about to write, iclass 38, count 2 2006.286.01:03:13.94#ibcon#wrote, iclass 38, count 2 2006.286.01:03:13.94#ibcon#about to read 3, iclass 38, count 2 2006.286.01:03:13.97#ibcon#read 3, iclass 38, count 2 2006.286.01:03:13.97#ibcon#about to read 4, iclass 38, count 2 2006.286.01:03:13.97#ibcon#read 4, iclass 38, count 2 2006.286.01:03:13.97#ibcon#about to read 5, iclass 38, count 2 2006.286.01:03:13.97#ibcon#read 5, iclass 38, count 2 2006.286.01:03:13.97#ibcon#about to read 6, iclass 38, count 2 2006.286.01:03:13.97#ibcon#read 6, iclass 38, count 2 2006.286.01:03:13.97#ibcon#end of sib2, iclass 38, count 2 2006.286.01:03:13.97#ibcon#*after write, iclass 38, count 2 2006.286.01:03:13.97#ibcon#*before return 0, iclass 38, count 2 2006.286.01:03:13.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:03:13.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:03:13.97#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.01:03:13.97#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:13.97#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:03:14.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:03:14.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:03:14.09#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:03:14.09#ibcon#first serial, iclass 38, count 0 2006.286.01:03:14.09#ibcon#enter sib2, iclass 38, count 0 2006.286.01:03:14.09#ibcon#flushed, iclass 38, count 0 2006.286.01:03:14.09#ibcon#about to write, iclass 38, count 0 2006.286.01:03:14.09#ibcon#wrote, iclass 38, count 0 2006.286.01:03:14.09#ibcon#about to read 3, iclass 38, count 0 2006.286.01:03:14.11#ibcon#read 3, iclass 38, count 0 2006.286.01:03:14.11#ibcon#about to read 4, iclass 38, count 0 2006.286.01:03:14.11#ibcon#read 4, iclass 38, count 0 2006.286.01:03:14.11#ibcon#about to read 5, iclass 38, count 0 2006.286.01:03:14.11#ibcon#read 5, iclass 38, count 0 2006.286.01:03:14.11#ibcon#about to read 6, iclass 38, count 0 2006.286.01:03:14.11#ibcon#read 6, iclass 38, count 0 2006.286.01:03:14.11#ibcon#end of sib2, iclass 38, count 0 2006.286.01:03:14.11#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:03:14.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:03:14.11#ibcon#[27=USB\r\n] 2006.286.01:03:14.11#ibcon#*before write, iclass 38, count 0 2006.286.01:03:14.11#ibcon#enter sib2, iclass 38, count 0 2006.286.01:03:14.11#ibcon#flushed, iclass 38, count 0 2006.286.01:03:14.11#ibcon#about to write, iclass 38, count 0 2006.286.01:03:14.11#ibcon#wrote, iclass 38, count 0 2006.286.01:03:14.11#ibcon#about to read 3, iclass 38, count 0 2006.286.01:03:14.14#ibcon#read 3, iclass 38, count 0 2006.286.01:03:14.14#ibcon#about to read 4, iclass 38, count 0 2006.286.01:03:14.14#ibcon#read 4, iclass 38, count 0 2006.286.01:03:14.14#ibcon#about to read 5, iclass 38, count 0 2006.286.01:03:14.14#ibcon#read 5, iclass 38, count 0 2006.286.01:03:14.14#ibcon#about to read 6, iclass 38, count 0 2006.286.01:03:14.14#ibcon#read 6, iclass 38, count 0 2006.286.01:03:14.14#ibcon#end of sib2, iclass 38, count 0 2006.286.01:03:14.14#ibcon#*after write, iclass 38, count 0 2006.286.01:03:14.14#ibcon#*before return 0, iclass 38, count 0 2006.286.01:03:14.14#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:03:14.14#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:03:14.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:03:14.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:03:14.14$vck44/vblo=7,734.99 2006.286.01:03:14.14#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.01:03:14.14#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.01:03:14.14#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:14.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:03:14.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:03:14.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:03:14.14#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:03:14.14#ibcon#first serial, iclass 40, count 0 2006.286.01:03:14.14#ibcon#enter sib2, iclass 40, count 0 2006.286.01:03:14.14#ibcon#flushed, iclass 40, count 0 2006.286.01:03:14.14#ibcon#about to write, iclass 40, count 0 2006.286.01:03:14.14#ibcon#wrote, iclass 40, count 0 2006.286.01:03:14.14#ibcon#about to read 3, iclass 40, count 0 2006.286.01:03:14.16#ibcon#read 3, iclass 40, count 0 2006.286.01:03:14.16#ibcon#about to read 4, iclass 40, count 0 2006.286.01:03:14.16#ibcon#read 4, iclass 40, count 0 2006.286.01:03:14.16#ibcon#about to read 5, iclass 40, count 0 2006.286.01:03:14.16#ibcon#read 5, iclass 40, count 0 2006.286.01:03:14.16#ibcon#about to read 6, iclass 40, count 0 2006.286.01:03:14.16#ibcon#read 6, iclass 40, count 0 2006.286.01:03:14.16#ibcon#end of sib2, iclass 40, count 0 2006.286.01:03:14.16#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:03:14.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:03:14.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:03:14.16#ibcon#*before write, iclass 40, count 0 2006.286.01:03:14.16#ibcon#enter sib2, iclass 40, count 0 2006.286.01:03:14.16#ibcon#flushed, iclass 40, count 0 2006.286.01:03:14.16#ibcon#about to write, iclass 40, count 0 2006.286.01:03:14.16#ibcon#wrote, iclass 40, count 0 2006.286.01:03:14.16#ibcon#about to read 3, iclass 40, count 0 2006.286.01:03:14.20#ibcon#read 3, iclass 40, count 0 2006.286.01:03:14.20#ibcon#about to read 4, iclass 40, count 0 2006.286.01:03:14.20#ibcon#read 4, iclass 40, count 0 2006.286.01:03:14.20#ibcon#about to read 5, iclass 40, count 0 2006.286.01:03:14.20#ibcon#read 5, iclass 40, count 0 2006.286.01:03:14.20#ibcon#about to read 6, iclass 40, count 0 2006.286.01:03:14.20#ibcon#read 6, iclass 40, count 0 2006.286.01:03:14.20#ibcon#end of sib2, iclass 40, count 0 2006.286.01:03:14.20#ibcon#*after write, iclass 40, count 0 2006.286.01:03:14.20#ibcon#*before return 0, iclass 40, count 0 2006.286.01:03:14.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:03:14.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:03:14.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:03:14.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:03:14.20$vck44/vb=7,4 2006.286.01:03:14.20#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.01:03:14.20#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.01:03:14.20#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:14.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:03:14.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:03:14.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:03:14.26#ibcon#enter wrdev, iclass 4, count 2 2006.286.01:03:14.26#ibcon#first serial, iclass 4, count 2 2006.286.01:03:14.26#ibcon#enter sib2, iclass 4, count 2 2006.286.01:03:14.26#ibcon#flushed, iclass 4, count 2 2006.286.01:03:14.26#ibcon#about to write, iclass 4, count 2 2006.286.01:03:14.26#ibcon#wrote, iclass 4, count 2 2006.286.01:03:14.26#ibcon#about to read 3, iclass 4, count 2 2006.286.01:03:14.28#ibcon#read 3, iclass 4, count 2 2006.286.01:03:14.28#ibcon#about to read 4, iclass 4, count 2 2006.286.01:03:14.28#ibcon#read 4, iclass 4, count 2 2006.286.01:03:14.28#ibcon#about to read 5, iclass 4, count 2 2006.286.01:03:14.28#ibcon#read 5, iclass 4, count 2 2006.286.01:03:14.28#ibcon#about to read 6, iclass 4, count 2 2006.286.01:03:14.28#ibcon#read 6, iclass 4, count 2 2006.286.01:03:14.28#ibcon#end of sib2, iclass 4, count 2 2006.286.01:03:14.28#ibcon#*mode == 0, iclass 4, count 2 2006.286.01:03:14.28#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.01:03:14.28#ibcon#[27=AT07-04\r\n] 2006.286.01:03:14.28#ibcon#*before write, iclass 4, count 2 2006.286.01:03:14.28#ibcon#enter sib2, iclass 4, count 2 2006.286.01:03:14.28#ibcon#flushed, iclass 4, count 2 2006.286.01:03:14.28#ibcon#about to write, iclass 4, count 2 2006.286.01:03:14.28#ibcon#wrote, iclass 4, count 2 2006.286.01:03:14.28#ibcon#about to read 3, iclass 4, count 2 2006.286.01:03:14.31#ibcon#read 3, iclass 4, count 2 2006.286.01:03:14.31#ibcon#about to read 4, iclass 4, count 2 2006.286.01:03:14.31#ibcon#read 4, iclass 4, count 2 2006.286.01:03:14.31#ibcon#about to read 5, iclass 4, count 2 2006.286.01:03:14.31#ibcon#read 5, iclass 4, count 2 2006.286.01:03:14.31#ibcon#about to read 6, iclass 4, count 2 2006.286.01:03:14.31#ibcon#read 6, iclass 4, count 2 2006.286.01:03:14.31#ibcon#end of sib2, iclass 4, count 2 2006.286.01:03:14.31#ibcon#*after write, iclass 4, count 2 2006.286.01:03:14.31#ibcon#*before return 0, iclass 4, count 2 2006.286.01:03:14.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:03:14.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:03:14.31#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.01:03:14.31#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:14.31#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:03:14.43#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:03:14.43#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:03:14.43#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:03:14.43#ibcon#first serial, iclass 4, count 0 2006.286.01:03:14.43#ibcon#enter sib2, iclass 4, count 0 2006.286.01:03:14.43#ibcon#flushed, iclass 4, count 0 2006.286.01:03:14.43#ibcon#about to write, iclass 4, count 0 2006.286.01:03:14.43#ibcon#wrote, iclass 4, count 0 2006.286.01:03:14.43#ibcon#about to read 3, iclass 4, count 0 2006.286.01:03:14.45#ibcon#read 3, iclass 4, count 0 2006.286.01:03:14.45#ibcon#about to read 4, iclass 4, count 0 2006.286.01:03:14.45#ibcon#read 4, iclass 4, count 0 2006.286.01:03:14.45#ibcon#about to read 5, iclass 4, count 0 2006.286.01:03:14.45#ibcon#read 5, iclass 4, count 0 2006.286.01:03:14.45#ibcon#about to read 6, iclass 4, count 0 2006.286.01:03:14.45#ibcon#read 6, iclass 4, count 0 2006.286.01:03:14.45#ibcon#end of sib2, iclass 4, count 0 2006.286.01:03:14.45#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:03:14.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:03:14.45#ibcon#[27=USB\r\n] 2006.286.01:03:14.45#ibcon#*before write, iclass 4, count 0 2006.286.01:03:14.45#ibcon#enter sib2, iclass 4, count 0 2006.286.01:03:14.45#ibcon#flushed, iclass 4, count 0 2006.286.01:03:14.45#ibcon#about to write, iclass 4, count 0 2006.286.01:03:14.45#ibcon#wrote, iclass 4, count 0 2006.286.01:03:14.45#ibcon#about to read 3, iclass 4, count 0 2006.286.01:03:14.48#ibcon#read 3, iclass 4, count 0 2006.286.01:03:14.48#ibcon#about to read 4, iclass 4, count 0 2006.286.01:03:14.48#ibcon#read 4, iclass 4, count 0 2006.286.01:03:14.48#ibcon#about to read 5, iclass 4, count 0 2006.286.01:03:14.48#ibcon#read 5, iclass 4, count 0 2006.286.01:03:14.48#ibcon#about to read 6, iclass 4, count 0 2006.286.01:03:14.48#ibcon#read 6, iclass 4, count 0 2006.286.01:03:14.48#ibcon#end of sib2, iclass 4, count 0 2006.286.01:03:14.48#ibcon#*after write, iclass 4, count 0 2006.286.01:03:14.48#ibcon#*before return 0, iclass 4, count 0 2006.286.01:03:14.48#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:03:14.48#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:03:14.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:03:14.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:03:14.48$vck44/vblo=8,744.99 2006.286.01:03:14.48#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.01:03:14.48#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.01:03:14.48#ibcon#ireg 17 cls_cnt 0 2006.286.01:03:14.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:03:14.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:03:14.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:03:14.48#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:03:14.48#ibcon#first serial, iclass 6, count 0 2006.286.01:03:14.48#ibcon#enter sib2, iclass 6, count 0 2006.286.01:03:14.48#ibcon#flushed, iclass 6, count 0 2006.286.01:03:14.48#ibcon#about to write, iclass 6, count 0 2006.286.01:03:14.48#ibcon#wrote, iclass 6, count 0 2006.286.01:03:14.48#ibcon#about to read 3, iclass 6, count 0 2006.286.01:03:14.50#ibcon#read 3, iclass 6, count 0 2006.286.01:03:14.50#ibcon#about to read 4, iclass 6, count 0 2006.286.01:03:14.50#ibcon#read 4, iclass 6, count 0 2006.286.01:03:14.50#ibcon#about to read 5, iclass 6, count 0 2006.286.01:03:14.50#ibcon#read 5, iclass 6, count 0 2006.286.01:03:14.50#ibcon#about to read 6, iclass 6, count 0 2006.286.01:03:14.50#ibcon#read 6, iclass 6, count 0 2006.286.01:03:14.50#ibcon#end of sib2, iclass 6, count 0 2006.286.01:03:14.50#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:03:14.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:03:14.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:03:14.50#ibcon#*before write, iclass 6, count 0 2006.286.01:03:14.50#ibcon#enter sib2, iclass 6, count 0 2006.286.01:03:14.50#ibcon#flushed, iclass 6, count 0 2006.286.01:03:14.50#ibcon#about to write, iclass 6, count 0 2006.286.01:03:14.50#ibcon#wrote, iclass 6, count 0 2006.286.01:03:14.50#ibcon#about to read 3, iclass 6, count 0 2006.286.01:03:14.54#ibcon#read 3, iclass 6, count 0 2006.286.01:03:14.54#ibcon#about to read 4, iclass 6, count 0 2006.286.01:03:14.54#ibcon#read 4, iclass 6, count 0 2006.286.01:03:14.54#ibcon#about to read 5, iclass 6, count 0 2006.286.01:03:14.54#ibcon#read 5, iclass 6, count 0 2006.286.01:03:14.54#ibcon#about to read 6, iclass 6, count 0 2006.286.01:03:14.54#ibcon#read 6, iclass 6, count 0 2006.286.01:03:14.54#ibcon#end of sib2, iclass 6, count 0 2006.286.01:03:14.54#ibcon#*after write, iclass 6, count 0 2006.286.01:03:14.54#ibcon#*before return 0, iclass 6, count 0 2006.286.01:03:14.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:03:14.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:03:14.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:03:14.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:03:14.54$vck44/vb=8,4 2006.286.01:03:14.54#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.01:03:14.54#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.01:03:14.54#ibcon#ireg 11 cls_cnt 2 2006.286.01:03:14.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:03:14.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:03:14.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:03:14.60#ibcon#enter wrdev, iclass 10, count 2 2006.286.01:03:14.60#ibcon#first serial, iclass 10, count 2 2006.286.01:03:14.60#ibcon#enter sib2, iclass 10, count 2 2006.286.01:03:14.60#ibcon#flushed, iclass 10, count 2 2006.286.01:03:14.60#ibcon#about to write, iclass 10, count 2 2006.286.01:03:14.60#ibcon#wrote, iclass 10, count 2 2006.286.01:03:14.60#ibcon#about to read 3, iclass 10, count 2 2006.286.01:03:14.62#ibcon#read 3, iclass 10, count 2 2006.286.01:03:14.62#ibcon#about to read 4, iclass 10, count 2 2006.286.01:03:14.62#ibcon#read 4, iclass 10, count 2 2006.286.01:03:14.62#ibcon#about to read 5, iclass 10, count 2 2006.286.01:03:14.62#ibcon#read 5, iclass 10, count 2 2006.286.01:03:14.62#ibcon#about to read 6, iclass 10, count 2 2006.286.01:03:14.62#ibcon#read 6, iclass 10, count 2 2006.286.01:03:14.62#ibcon#end of sib2, iclass 10, count 2 2006.286.01:03:14.62#ibcon#*mode == 0, iclass 10, count 2 2006.286.01:03:14.62#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.01:03:14.62#ibcon#[27=AT08-04\r\n] 2006.286.01:03:14.62#ibcon#*before write, iclass 10, count 2 2006.286.01:03:14.62#ibcon#enter sib2, iclass 10, count 2 2006.286.01:03:14.62#ibcon#flushed, iclass 10, count 2 2006.286.01:03:14.62#ibcon#about to write, iclass 10, count 2 2006.286.01:03:14.62#ibcon#wrote, iclass 10, count 2 2006.286.01:03:14.62#ibcon#about to read 3, iclass 10, count 2 2006.286.01:03:14.65#ibcon#read 3, iclass 10, count 2 2006.286.01:03:14.65#ibcon#about to read 4, iclass 10, count 2 2006.286.01:03:14.65#ibcon#read 4, iclass 10, count 2 2006.286.01:03:14.65#ibcon#about to read 5, iclass 10, count 2 2006.286.01:03:14.65#ibcon#read 5, iclass 10, count 2 2006.286.01:03:14.65#ibcon#about to read 6, iclass 10, count 2 2006.286.01:03:14.65#ibcon#read 6, iclass 10, count 2 2006.286.01:03:14.65#ibcon#end of sib2, iclass 10, count 2 2006.286.01:03:14.65#ibcon#*after write, iclass 10, count 2 2006.286.01:03:14.65#ibcon#*before return 0, iclass 10, count 2 2006.286.01:03:14.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:03:14.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:03:14.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.01:03:14.65#ibcon#ireg 7 cls_cnt 0 2006.286.01:03:14.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:03:14.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:03:14.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:03:14.77#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:03:14.77#ibcon#first serial, iclass 10, count 0 2006.286.01:03:14.77#ibcon#enter sib2, iclass 10, count 0 2006.286.01:03:14.77#ibcon#flushed, iclass 10, count 0 2006.286.01:03:14.77#ibcon#about to write, iclass 10, count 0 2006.286.01:03:14.77#ibcon#wrote, iclass 10, count 0 2006.286.01:03:14.77#ibcon#about to read 3, iclass 10, count 0 2006.286.01:03:14.79#ibcon#read 3, iclass 10, count 0 2006.286.01:03:14.79#ibcon#about to read 4, iclass 10, count 0 2006.286.01:03:14.79#ibcon#read 4, iclass 10, count 0 2006.286.01:03:14.79#ibcon#about to read 5, iclass 10, count 0 2006.286.01:03:14.79#ibcon#read 5, iclass 10, count 0 2006.286.01:03:14.79#ibcon#about to read 6, iclass 10, count 0 2006.286.01:03:14.79#ibcon#read 6, iclass 10, count 0 2006.286.01:03:14.79#ibcon#end of sib2, iclass 10, count 0 2006.286.01:03:14.79#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:03:14.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:03:14.79#ibcon#[27=USB\r\n] 2006.286.01:03:14.79#ibcon#*before write, iclass 10, count 0 2006.286.01:03:14.79#ibcon#enter sib2, iclass 10, count 0 2006.286.01:03:14.79#ibcon#flushed, iclass 10, count 0 2006.286.01:03:14.79#ibcon#about to write, iclass 10, count 0 2006.286.01:03:14.79#ibcon#wrote, iclass 10, count 0 2006.286.01:03:14.79#ibcon#about to read 3, iclass 10, count 0 2006.286.01:03:14.82#ibcon#read 3, iclass 10, count 0 2006.286.01:03:14.82#ibcon#about to read 4, iclass 10, count 0 2006.286.01:03:14.82#ibcon#read 4, iclass 10, count 0 2006.286.01:03:14.82#ibcon#about to read 5, iclass 10, count 0 2006.286.01:03:14.82#ibcon#read 5, iclass 10, count 0 2006.286.01:03:14.82#ibcon#about to read 6, iclass 10, count 0 2006.286.01:03:14.82#ibcon#read 6, iclass 10, count 0 2006.286.01:03:14.82#ibcon#end of sib2, iclass 10, count 0 2006.286.01:03:14.82#ibcon#*after write, iclass 10, count 0 2006.286.01:03:14.82#ibcon#*before return 0, iclass 10, count 0 2006.286.01:03:14.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:03:14.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:03:14.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:03:14.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:03:14.82$vck44/vabw=wide 2006.286.01:03:14.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.01:03:14.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.01:03:14.82#ibcon#ireg 8 cls_cnt 0 2006.286.01:03:14.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:03:14.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:03:14.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:03:14.82#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:03:14.82#ibcon#first serial, iclass 12, count 0 2006.286.01:03:14.82#ibcon#enter sib2, iclass 12, count 0 2006.286.01:03:14.82#ibcon#flushed, iclass 12, count 0 2006.286.01:03:14.82#ibcon#about to write, iclass 12, count 0 2006.286.01:03:14.82#ibcon#wrote, iclass 12, count 0 2006.286.01:03:14.82#ibcon#about to read 3, iclass 12, count 0 2006.286.01:03:14.84#ibcon#read 3, iclass 12, count 0 2006.286.01:03:14.84#ibcon#about to read 4, iclass 12, count 0 2006.286.01:03:14.84#ibcon#read 4, iclass 12, count 0 2006.286.01:03:14.84#ibcon#about to read 5, iclass 12, count 0 2006.286.01:03:14.84#ibcon#read 5, iclass 12, count 0 2006.286.01:03:14.84#ibcon#about to read 6, iclass 12, count 0 2006.286.01:03:14.84#ibcon#read 6, iclass 12, count 0 2006.286.01:03:14.84#ibcon#end of sib2, iclass 12, count 0 2006.286.01:03:14.84#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:03:14.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:03:14.84#ibcon#[25=BW32\r\n] 2006.286.01:03:14.84#ibcon#*before write, iclass 12, count 0 2006.286.01:03:14.84#ibcon#enter sib2, iclass 12, count 0 2006.286.01:03:14.84#ibcon#flushed, iclass 12, count 0 2006.286.01:03:14.84#ibcon#about to write, iclass 12, count 0 2006.286.01:03:14.84#ibcon#wrote, iclass 12, count 0 2006.286.01:03:14.84#ibcon#about to read 3, iclass 12, count 0 2006.286.01:03:14.87#ibcon#read 3, iclass 12, count 0 2006.286.01:03:14.87#ibcon#about to read 4, iclass 12, count 0 2006.286.01:03:14.87#ibcon#read 4, iclass 12, count 0 2006.286.01:03:14.87#ibcon#about to read 5, iclass 12, count 0 2006.286.01:03:14.87#ibcon#read 5, iclass 12, count 0 2006.286.01:03:14.87#ibcon#about to read 6, iclass 12, count 0 2006.286.01:03:14.87#ibcon#read 6, iclass 12, count 0 2006.286.01:03:14.87#ibcon#end of sib2, iclass 12, count 0 2006.286.01:03:14.87#ibcon#*after write, iclass 12, count 0 2006.286.01:03:14.87#ibcon#*before return 0, iclass 12, count 0 2006.286.01:03:14.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:03:14.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:03:14.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:03:14.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:03:14.87$vck44/vbbw=wide 2006.286.01:03:14.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.01:03:14.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.01:03:14.87#ibcon#ireg 8 cls_cnt 0 2006.286.01:03:14.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:03:14.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:03:14.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:03:14.94#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:03:14.94#ibcon#first serial, iclass 14, count 0 2006.286.01:03:14.94#ibcon#enter sib2, iclass 14, count 0 2006.286.01:03:14.94#ibcon#flushed, iclass 14, count 0 2006.286.01:03:14.94#ibcon#about to write, iclass 14, count 0 2006.286.01:03:14.94#ibcon#wrote, iclass 14, count 0 2006.286.01:03:14.94#ibcon#about to read 3, iclass 14, count 0 2006.286.01:03:14.96#ibcon#read 3, iclass 14, count 0 2006.286.01:03:14.96#ibcon#about to read 4, iclass 14, count 0 2006.286.01:03:14.96#ibcon#read 4, iclass 14, count 0 2006.286.01:03:14.96#ibcon#about to read 5, iclass 14, count 0 2006.286.01:03:14.96#ibcon#read 5, iclass 14, count 0 2006.286.01:03:14.96#ibcon#about to read 6, iclass 14, count 0 2006.286.01:03:14.96#ibcon#read 6, iclass 14, count 0 2006.286.01:03:14.96#ibcon#end of sib2, iclass 14, count 0 2006.286.01:03:14.96#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:03:14.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:03:14.96#ibcon#[27=BW32\r\n] 2006.286.01:03:14.96#ibcon#*before write, iclass 14, count 0 2006.286.01:03:14.96#ibcon#enter sib2, iclass 14, count 0 2006.286.01:03:14.96#ibcon#flushed, iclass 14, count 0 2006.286.01:03:14.96#ibcon#about to write, iclass 14, count 0 2006.286.01:03:14.96#ibcon#wrote, iclass 14, count 0 2006.286.01:03:14.96#ibcon#about to read 3, iclass 14, count 0 2006.286.01:03:14.99#ibcon#read 3, iclass 14, count 0 2006.286.01:03:14.99#ibcon#about to read 4, iclass 14, count 0 2006.286.01:03:14.99#ibcon#read 4, iclass 14, count 0 2006.286.01:03:14.99#ibcon#about to read 5, iclass 14, count 0 2006.286.01:03:14.99#ibcon#read 5, iclass 14, count 0 2006.286.01:03:14.99#ibcon#about to read 6, iclass 14, count 0 2006.286.01:03:14.99#ibcon#read 6, iclass 14, count 0 2006.286.01:03:14.99#ibcon#end of sib2, iclass 14, count 0 2006.286.01:03:14.99#ibcon#*after write, iclass 14, count 0 2006.286.01:03:14.99#ibcon#*before return 0, iclass 14, count 0 2006.286.01:03:14.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:03:14.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:03:14.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:03:14.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:03:14.99$setupk4/ifdk4 2006.286.01:03:14.99$ifdk4/lo= 2006.286.01:03:14.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:03:14.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:03:14.99$ifdk4/patch= 2006.286.01:03:14.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:03:14.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:03:14.99$setupk4/!*+20s 2006.286.01:03:17.22#abcon#<5=/03 3.0 6.3 20.93 811016.2\r\n> 2006.286.01:03:17.24#abcon#{5=INTERFACE CLEAR} 2006.286.01:03:17.30#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:03:27.39#abcon#<5=/03 3.0 6.3 20.93 821016.2\r\n> 2006.286.01:03:27.41#abcon#{5=INTERFACE CLEAR} 2006.286.01:03:27.47#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:03:29.51$setupk4/"tpicd 2006.286.01:03:29.51$setupk4/echo=off 2006.286.01:03:29.51$setupk4/xlog=off 2006.286.01:03:29.51:!2006.286.01:12:32 2006.286.01:03:35.14#trakl#Source acquired 2006.286.01:03:37.14#flagr#flagr/antenna,acquired 2006.286.01:12:32.00:preob 2006.286.01:12:32.14/onsource/TRACKING 2006.286.01:12:32.14:!2006.286.01:12:42 2006.286.01:12:42.00:"tape 2006.286.01:12:42.00:"st=record 2006.286.01:12:42.00:data_valid=on 2006.286.01:12:42.00:midob 2006.286.01:12:43.14/onsource/TRACKING 2006.286.01:12:43.14/wx/20.98,1016.2,82 2006.286.01:12:43.23/cable/+6.5048E-03 2006.286.01:12:44.32/va/01,07,usb,yes,33,36 2006.286.01:12:44.32/va/02,06,usb,yes,34,34 2006.286.01:12:44.32/va/03,07,usb,yes,33,35 2006.286.01:12:44.32/va/04,06,usb,yes,35,36 2006.286.01:12:44.32/va/05,03,usb,yes,34,35 2006.286.01:12:44.32/va/06,04,usb,yes,31,30 2006.286.01:12:44.32/va/07,04,usb,yes,31,32 2006.286.01:12:44.32/va/08,03,usb,yes,32,39 2006.286.01:12:44.55/valo/01,524.99,yes,locked 2006.286.01:12:44.55/valo/02,534.99,yes,locked 2006.286.01:12:44.55/valo/03,564.99,yes,locked 2006.286.01:12:44.55/valo/04,624.99,yes,locked 2006.286.01:12:44.55/valo/05,734.99,yes,locked 2006.286.01:12:44.55/valo/06,814.99,yes,locked 2006.286.01:12:44.55/valo/07,864.99,yes,locked 2006.286.01:12:44.55/valo/08,884.99,yes,locked 2006.286.01:12:45.64/vb/01,04,usb,yes,32,29 2006.286.01:12:45.64/vb/02,05,usb,yes,30,30 2006.286.01:12:45.64/vb/03,04,usb,yes,31,34 2006.286.01:12:45.64/vb/04,05,usb,yes,31,30 2006.286.01:12:45.64/vb/05,04,usb,yes,27,30 2006.286.01:12:45.64/vb/06,03,usb,yes,39,35 2006.286.01:12:45.64/vb/07,04,usb,yes,32,32 2006.286.01:12:45.64/vb/08,04,usb,yes,29,33 2006.286.01:12:45.87/vblo/01,629.99,yes,locked 2006.286.01:12:45.87/vblo/02,634.99,yes,locked 2006.286.01:12:45.87/vblo/03,649.99,yes,locked 2006.286.01:12:45.87/vblo/04,679.99,yes,locked 2006.286.01:12:45.87/vblo/05,709.99,yes,locked 2006.286.01:12:45.87/vblo/06,719.99,yes,locked 2006.286.01:12:45.87/vblo/07,734.99,yes,locked 2006.286.01:12:45.87/vblo/08,744.99,yes,locked 2006.286.01:12:46.02/vabw/8 2006.286.01:12:46.17/vbbw/8 2006.286.01:12:46.26/xfe/off,on,12.0 2006.286.01:12:46.63/ifatt/23,28,28,28 2006.286.01:12:47.07/fmout-gps/S +2.73E-07 2006.286.01:12:47.09:!2006.286.01:13:42 2006.286.01:13:42.00:data_valid=off 2006.286.01:13:42.00:"et 2006.286.01:13:42.00:!+3s 2006.286.01:13:45.01:"tape 2006.286.01:13:45.01:postob 2006.286.01:13:45.10/cable/+6.5029E-03 2006.286.01:13:45.10/wx/20.98,1016.2,83 2006.286.01:13:46.07/fmout-gps/S +2.74E-07 2006.286.01:13:46.07:scan_name=286-0117,jd0610,40 2006.286.01:13:46.07:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.286.01:13:46.14#flagr#flagr/antenna,new-source 2006.286.01:13:47.14:checkk5 2006.286.01:13:47.55/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:13:47.96/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:13:48.33/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:13:48.72/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:13:49.31/chk_obsdata//k5ts1/T2860112??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.286.01:13:49.68/chk_obsdata//k5ts2/T2860112??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.286.01:13:50.07/chk_obsdata//k5ts3/T2860112??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.286.01:13:50.45/chk_obsdata//k5ts4/T2860112??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.286.01:13:51.52/k5log//k5ts1_log_newline 2006.286.01:13:52.32/k5log//k5ts2_log_newline 2006.286.01:13:53.20/k5log//k5ts3_log_newline 2006.286.01:13:53.98/k5log//k5ts4_log_newline 2006.286.01:13:54.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:13:54.00:setupk4=1 2006.286.01:13:54.00$setupk4/echo=on 2006.286.01:13:54.00$setupk4/pcalon 2006.286.01:13:54.00$pcalon/"no phase cal control is implemented here 2006.286.01:13:54.00$setupk4/"tpicd=stop 2006.286.01:13:54.00$setupk4/"rec=synch_on 2006.286.01:13:54.00$setupk4/"rec_mode=128 2006.286.01:13:54.00$setupk4/!* 2006.286.01:13:54.00$setupk4/recpk4 2006.286.01:13:54.00$recpk4/recpatch= 2006.286.01:13:54.00$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:13:54.00$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:13:54.00$setupk4/vck44 2006.286.01:13:54.00$vck44/valo=1,524.99 2006.286.01:13:54.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.01:13:54.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.01:13:54.00#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:54.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:13:54.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:13:54.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:13:54.00#ibcon#enter wrdev, iclass 19, count 0 2006.286.01:13:54.00#ibcon#first serial, iclass 19, count 0 2006.286.01:13:54.00#ibcon#enter sib2, iclass 19, count 0 2006.286.01:13:54.00#ibcon#flushed, iclass 19, count 0 2006.286.01:13:54.00#ibcon#about to write, iclass 19, count 0 2006.286.01:13:54.00#ibcon#wrote, iclass 19, count 0 2006.286.01:13:54.00#ibcon#about to read 3, iclass 19, count 0 2006.286.01:13:54.02#ibcon#read 3, iclass 19, count 0 2006.286.01:13:54.02#ibcon#about to read 4, iclass 19, count 0 2006.286.01:13:54.02#ibcon#read 4, iclass 19, count 0 2006.286.01:13:54.02#ibcon#about to read 5, iclass 19, count 0 2006.286.01:13:54.02#ibcon#read 5, iclass 19, count 0 2006.286.01:13:54.02#ibcon#about to read 6, iclass 19, count 0 2006.286.01:13:54.02#ibcon#read 6, iclass 19, count 0 2006.286.01:13:54.02#ibcon#end of sib2, iclass 19, count 0 2006.286.01:13:54.02#ibcon#*mode == 0, iclass 19, count 0 2006.286.01:13:54.02#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.01:13:54.02#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:13:54.02#ibcon#*before write, iclass 19, count 0 2006.286.01:13:54.02#ibcon#enter sib2, iclass 19, count 0 2006.286.01:13:54.02#ibcon#flushed, iclass 19, count 0 2006.286.01:13:54.02#ibcon#about to write, iclass 19, count 0 2006.286.01:13:54.02#ibcon#wrote, iclass 19, count 0 2006.286.01:13:54.02#ibcon#about to read 3, iclass 19, count 0 2006.286.01:13:54.07#ibcon#read 3, iclass 19, count 0 2006.286.01:13:54.07#ibcon#about to read 4, iclass 19, count 0 2006.286.01:13:54.07#ibcon#read 4, iclass 19, count 0 2006.286.01:13:54.07#ibcon#about to read 5, iclass 19, count 0 2006.286.01:13:54.07#ibcon#read 5, iclass 19, count 0 2006.286.01:13:54.07#ibcon#about to read 6, iclass 19, count 0 2006.286.01:13:54.07#ibcon#read 6, iclass 19, count 0 2006.286.01:13:54.07#ibcon#end of sib2, iclass 19, count 0 2006.286.01:13:54.07#ibcon#*after write, iclass 19, count 0 2006.286.01:13:54.07#ibcon#*before return 0, iclass 19, count 0 2006.286.01:13:54.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:13:54.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:13:54.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.01:13:54.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.01:13:54.07$vck44/va=1,7 2006.286.01:13:54.07#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.01:13:54.07#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.01:13:54.07#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:54.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:13:54.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:13:54.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:13:54.07#ibcon#enter wrdev, iclass 21, count 2 2006.286.01:13:54.07#ibcon#first serial, iclass 21, count 2 2006.286.01:13:54.07#ibcon#enter sib2, iclass 21, count 2 2006.286.01:13:54.07#ibcon#flushed, iclass 21, count 2 2006.286.01:13:54.07#ibcon#about to write, iclass 21, count 2 2006.286.01:13:54.07#ibcon#wrote, iclass 21, count 2 2006.286.01:13:54.07#ibcon#about to read 3, iclass 21, count 2 2006.286.01:13:54.09#ibcon#read 3, iclass 21, count 2 2006.286.01:13:54.09#ibcon#about to read 4, iclass 21, count 2 2006.286.01:13:54.09#ibcon#read 4, iclass 21, count 2 2006.286.01:13:54.09#ibcon#about to read 5, iclass 21, count 2 2006.286.01:13:54.09#ibcon#read 5, iclass 21, count 2 2006.286.01:13:54.09#ibcon#about to read 6, iclass 21, count 2 2006.286.01:13:54.09#ibcon#read 6, iclass 21, count 2 2006.286.01:13:54.09#ibcon#end of sib2, iclass 21, count 2 2006.286.01:13:54.09#ibcon#*mode == 0, iclass 21, count 2 2006.286.01:13:54.09#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.01:13:54.09#ibcon#[25=AT01-07\r\n] 2006.286.01:13:54.09#ibcon#*before write, iclass 21, count 2 2006.286.01:13:54.09#ibcon#enter sib2, iclass 21, count 2 2006.286.01:13:54.09#ibcon#flushed, iclass 21, count 2 2006.286.01:13:54.09#ibcon#about to write, iclass 21, count 2 2006.286.01:13:54.09#ibcon#wrote, iclass 21, count 2 2006.286.01:13:54.09#ibcon#about to read 3, iclass 21, count 2 2006.286.01:13:54.12#ibcon#read 3, iclass 21, count 2 2006.286.01:13:54.12#ibcon#about to read 4, iclass 21, count 2 2006.286.01:13:54.12#ibcon#read 4, iclass 21, count 2 2006.286.01:13:54.12#ibcon#about to read 5, iclass 21, count 2 2006.286.01:13:54.12#ibcon#read 5, iclass 21, count 2 2006.286.01:13:54.12#ibcon#about to read 6, iclass 21, count 2 2006.286.01:13:54.12#ibcon#read 6, iclass 21, count 2 2006.286.01:13:54.12#ibcon#end of sib2, iclass 21, count 2 2006.286.01:13:54.12#ibcon#*after write, iclass 21, count 2 2006.286.01:13:54.12#ibcon#*before return 0, iclass 21, count 2 2006.286.01:13:54.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:13:54.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:13:54.12#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.01:13:54.12#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:54.12#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:13:54.24#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:13:54.24#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:13:54.24#ibcon#enter wrdev, iclass 21, count 0 2006.286.01:13:54.24#ibcon#first serial, iclass 21, count 0 2006.286.01:13:54.24#ibcon#enter sib2, iclass 21, count 0 2006.286.01:13:54.24#ibcon#flushed, iclass 21, count 0 2006.286.01:13:54.24#ibcon#about to write, iclass 21, count 0 2006.286.01:13:54.24#ibcon#wrote, iclass 21, count 0 2006.286.01:13:54.24#ibcon#about to read 3, iclass 21, count 0 2006.286.01:13:54.26#ibcon#read 3, iclass 21, count 0 2006.286.01:13:54.26#ibcon#about to read 4, iclass 21, count 0 2006.286.01:13:54.26#ibcon#read 4, iclass 21, count 0 2006.286.01:13:54.26#ibcon#about to read 5, iclass 21, count 0 2006.286.01:13:54.26#ibcon#read 5, iclass 21, count 0 2006.286.01:13:54.26#ibcon#about to read 6, iclass 21, count 0 2006.286.01:13:54.26#ibcon#read 6, iclass 21, count 0 2006.286.01:13:54.26#ibcon#end of sib2, iclass 21, count 0 2006.286.01:13:54.26#ibcon#*mode == 0, iclass 21, count 0 2006.286.01:13:54.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.01:13:54.26#ibcon#[25=USB\r\n] 2006.286.01:13:54.26#ibcon#*before write, iclass 21, count 0 2006.286.01:13:54.26#ibcon#enter sib2, iclass 21, count 0 2006.286.01:13:54.26#ibcon#flushed, iclass 21, count 0 2006.286.01:13:54.26#ibcon#about to write, iclass 21, count 0 2006.286.01:13:54.26#ibcon#wrote, iclass 21, count 0 2006.286.01:13:54.26#ibcon#about to read 3, iclass 21, count 0 2006.286.01:13:54.29#ibcon#read 3, iclass 21, count 0 2006.286.01:13:54.29#ibcon#about to read 4, iclass 21, count 0 2006.286.01:13:54.29#ibcon#read 4, iclass 21, count 0 2006.286.01:13:54.29#ibcon#about to read 5, iclass 21, count 0 2006.286.01:13:54.29#ibcon#read 5, iclass 21, count 0 2006.286.01:13:54.29#ibcon#about to read 6, iclass 21, count 0 2006.286.01:13:54.29#ibcon#read 6, iclass 21, count 0 2006.286.01:13:54.29#ibcon#end of sib2, iclass 21, count 0 2006.286.01:13:54.29#ibcon#*after write, iclass 21, count 0 2006.286.01:13:54.29#ibcon#*before return 0, iclass 21, count 0 2006.286.01:13:54.29#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:13:54.29#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:13:54.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.01:13:54.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.01:13:54.29$vck44/valo=2,534.99 2006.286.01:13:54.29#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.01:13:54.29#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.01:13:54.29#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:54.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:13:54.29#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:13:54.29#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:13:54.29#ibcon#enter wrdev, iclass 23, count 0 2006.286.01:13:54.29#ibcon#first serial, iclass 23, count 0 2006.286.01:13:54.29#ibcon#enter sib2, iclass 23, count 0 2006.286.01:13:54.29#ibcon#flushed, iclass 23, count 0 2006.286.01:13:54.29#ibcon#about to write, iclass 23, count 0 2006.286.01:13:54.29#ibcon#wrote, iclass 23, count 0 2006.286.01:13:54.29#ibcon#about to read 3, iclass 23, count 0 2006.286.01:13:54.31#ibcon#read 3, iclass 23, count 0 2006.286.01:13:54.31#ibcon#about to read 4, iclass 23, count 0 2006.286.01:13:54.31#ibcon#read 4, iclass 23, count 0 2006.286.01:13:54.31#ibcon#about to read 5, iclass 23, count 0 2006.286.01:13:54.31#ibcon#read 5, iclass 23, count 0 2006.286.01:13:54.31#ibcon#about to read 6, iclass 23, count 0 2006.286.01:13:54.31#ibcon#read 6, iclass 23, count 0 2006.286.01:13:54.31#ibcon#end of sib2, iclass 23, count 0 2006.286.01:13:54.31#ibcon#*mode == 0, iclass 23, count 0 2006.286.01:13:54.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.01:13:54.31#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:13:54.31#ibcon#*before write, iclass 23, count 0 2006.286.01:13:54.31#ibcon#enter sib2, iclass 23, count 0 2006.286.01:13:54.31#ibcon#flushed, iclass 23, count 0 2006.286.01:13:54.31#ibcon#about to write, iclass 23, count 0 2006.286.01:13:54.31#ibcon#wrote, iclass 23, count 0 2006.286.01:13:54.31#ibcon#about to read 3, iclass 23, count 0 2006.286.01:13:54.35#ibcon#read 3, iclass 23, count 0 2006.286.01:13:54.35#ibcon#about to read 4, iclass 23, count 0 2006.286.01:13:54.35#ibcon#read 4, iclass 23, count 0 2006.286.01:13:54.35#ibcon#about to read 5, iclass 23, count 0 2006.286.01:13:54.35#ibcon#read 5, iclass 23, count 0 2006.286.01:13:54.35#ibcon#about to read 6, iclass 23, count 0 2006.286.01:13:54.35#ibcon#read 6, iclass 23, count 0 2006.286.01:13:54.35#ibcon#end of sib2, iclass 23, count 0 2006.286.01:13:54.35#ibcon#*after write, iclass 23, count 0 2006.286.01:13:54.35#ibcon#*before return 0, iclass 23, count 0 2006.286.01:13:54.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:13:54.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:13:54.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.01:13:54.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.01:13:54.35$vck44/va=2,6 2006.286.01:13:54.35#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.01:13:54.35#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.01:13:54.35#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:54.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:13:54.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:13:54.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:13:54.41#ibcon#enter wrdev, iclass 25, count 2 2006.286.01:13:54.41#ibcon#first serial, iclass 25, count 2 2006.286.01:13:54.41#ibcon#enter sib2, iclass 25, count 2 2006.286.01:13:54.41#ibcon#flushed, iclass 25, count 2 2006.286.01:13:54.41#ibcon#about to write, iclass 25, count 2 2006.286.01:13:54.41#ibcon#wrote, iclass 25, count 2 2006.286.01:13:54.41#ibcon#about to read 3, iclass 25, count 2 2006.286.01:13:54.43#ibcon#read 3, iclass 25, count 2 2006.286.01:13:54.43#ibcon#about to read 4, iclass 25, count 2 2006.286.01:13:54.43#ibcon#read 4, iclass 25, count 2 2006.286.01:13:54.43#ibcon#about to read 5, iclass 25, count 2 2006.286.01:13:54.43#ibcon#read 5, iclass 25, count 2 2006.286.01:13:54.43#ibcon#about to read 6, iclass 25, count 2 2006.286.01:13:54.43#ibcon#read 6, iclass 25, count 2 2006.286.01:13:54.43#ibcon#end of sib2, iclass 25, count 2 2006.286.01:13:54.43#ibcon#*mode == 0, iclass 25, count 2 2006.286.01:13:54.43#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.01:13:54.43#ibcon#[25=AT02-06\r\n] 2006.286.01:13:54.43#ibcon#*before write, iclass 25, count 2 2006.286.01:13:54.43#ibcon#enter sib2, iclass 25, count 2 2006.286.01:13:54.43#ibcon#flushed, iclass 25, count 2 2006.286.01:13:54.43#ibcon#about to write, iclass 25, count 2 2006.286.01:13:54.43#ibcon#wrote, iclass 25, count 2 2006.286.01:13:54.43#ibcon#about to read 3, iclass 25, count 2 2006.286.01:13:54.46#ibcon#read 3, iclass 25, count 2 2006.286.01:13:54.46#ibcon#about to read 4, iclass 25, count 2 2006.286.01:13:54.46#ibcon#read 4, iclass 25, count 2 2006.286.01:13:54.46#ibcon#about to read 5, iclass 25, count 2 2006.286.01:13:54.46#ibcon#read 5, iclass 25, count 2 2006.286.01:13:54.46#ibcon#about to read 6, iclass 25, count 2 2006.286.01:13:54.46#ibcon#read 6, iclass 25, count 2 2006.286.01:13:54.46#ibcon#end of sib2, iclass 25, count 2 2006.286.01:13:54.46#ibcon#*after write, iclass 25, count 2 2006.286.01:13:54.46#ibcon#*before return 0, iclass 25, count 2 2006.286.01:13:54.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:13:54.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:13:54.46#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.01:13:54.46#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:54.46#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:13:54.58#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:13:54.58#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:13:54.58#ibcon#enter wrdev, iclass 25, count 0 2006.286.01:13:54.58#ibcon#first serial, iclass 25, count 0 2006.286.01:13:54.58#ibcon#enter sib2, iclass 25, count 0 2006.286.01:13:54.58#ibcon#flushed, iclass 25, count 0 2006.286.01:13:54.58#ibcon#about to write, iclass 25, count 0 2006.286.01:13:54.58#ibcon#wrote, iclass 25, count 0 2006.286.01:13:54.58#ibcon#about to read 3, iclass 25, count 0 2006.286.01:13:54.60#ibcon#read 3, iclass 25, count 0 2006.286.01:13:54.60#ibcon#about to read 4, iclass 25, count 0 2006.286.01:13:54.60#ibcon#read 4, iclass 25, count 0 2006.286.01:13:54.60#ibcon#about to read 5, iclass 25, count 0 2006.286.01:13:54.60#ibcon#read 5, iclass 25, count 0 2006.286.01:13:54.60#ibcon#about to read 6, iclass 25, count 0 2006.286.01:13:54.60#ibcon#read 6, iclass 25, count 0 2006.286.01:13:54.60#ibcon#end of sib2, iclass 25, count 0 2006.286.01:13:54.60#ibcon#*mode == 0, iclass 25, count 0 2006.286.01:13:54.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.01:13:54.60#ibcon#[25=USB\r\n] 2006.286.01:13:54.60#ibcon#*before write, iclass 25, count 0 2006.286.01:13:54.60#ibcon#enter sib2, iclass 25, count 0 2006.286.01:13:54.60#ibcon#flushed, iclass 25, count 0 2006.286.01:13:54.60#ibcon#about to write, iclass 25, count 0 2006.286.01:13:54.60#ibcon#wrote, iclass 25, count 0 2006.286.01:13:54.60#ibcon#about to read 3, iclass 25, count 0 2006.286.01:13:54.63#ibcon#read 3, iclass 25, count 0 2006.286.01:13:54.63#ibcon#about to read 4, iclass 25, count 0 2006.286.01:13:54.63#ibcon#read 4, iclass 25, count 0 2006.286.01:13:54.63#ibcon#about to read 5, iclass 25, count 0 2006.286.01:13:54.63#ibcon#read 5, iclass 25, count 0 2006.286.01:13:54.63#ibcon#about to read 6, iclass 25, count 0 2006.286.01:13:54.63#ibcon#read 6, iclass 25, count 0 2006.286.01:13:54.63#ibcon#end of sib2, iclass 25, count 0 2006.286.01:13:54.63#ibcon#*after write, iclass 25, count 0 2006.286.01:13:54.63#ibcon#*before return 0, iclass 25, count 0 2006.286.01:13:54.63#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:13:54.63#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:13:54.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.01:13:54.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.01:13:54.63$vck44/valo=3,564.99 2006.286.01:13:54.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.01:13:54.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.01:13:54.63#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:54.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:13:54.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:13:54.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:13:54.63#ibcon#enter wrdev, iclass 27, count 0 2006.286.01:13:54.63#ibcon#first serial, iclass 27, count 0 2006.286.01:13:54.63#ibcon#enter sib2, iclass 27, count 0 2006.286.01:13:54.63#ibcon#flushed, iclass 27, count 0 2006.286.01:13:54.63#ibcon#about to write, iclass 27, count 0 2006.286.01:13:54.63#ibcon#wrote, iclass 27, count 0 2006.286.01:13:54.63#ibcon#about to read 3, iclass 27, count 0 2006.286.01:13:54.65#ibcon#read 3, iclass 27, count 0 2006.286.01:13:54.65#ibcon#about to read 4, iclass 27, count 0 2006.286.01:13:54.65#ibcon#read 4, iclass 27, count 0 2006.286.01:13:54.65#ibcon#about to read 5, iclass 27, count 0 2006.286.01:13:54.65#ibcon#read 5, iclass 27, count 0 2006.286.01:13:54.65#ibcon#about to read 6, iclass 27, count 0 2006.286.01:13:54.65#ibcon#read 6, iclass 27, count 0 2006.286.01:13:54.65#ibcon#end of sib2, iclass 27, count 0 2006.286.01:13:54.65#ibcon#*mode == 0, iclass 27, count 0 2006.286.01:13:54.65#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.01:13:54.65#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:13:54.65#ibcon#*before write, iclass 27, count 0 2006.286.01:13:54.65#ibcon#enter sib2, iclass 27, count 0 2006.286.01:13:54.65#ibcon#flushed, iclass 27, count 0 2006.286.01:13:54.65#ibcon#about to write, iclass 27, count 0 2006.286.01:13:54.65#ibcon#wrote, iclass 27, count 0 2006.286.01:13:54.65#ibcon#about to read 3, iclass 27, count 0 2006.286.01:13:54.69#ibcon#read 3, iclass 27, count 0 2006.286.01:13:54.69#ibcon#about to read 4, iclass 27, count 0 2006.286.01:13:54.69#ibcon#read 4, iclass 27, count 0 2006.286.01:13:54.69#ibcon#about to read 5, iclass 27, count 0 2006.286.01:13:54.69#ibcon#read 5, iclass 27, count 0 2006.286.01:13:54.69#ibcon#about to read 6, iclass 27, count 0 2006.286.01:13:54.69#ibcon#read 6, iclass 27, count 0 2006.286.01:13:54.69#ibcon#end of sib2, iclass 27, count 0 2006.286.01:13:54.69#ibcon#*after write, iclass 27, count 0 2006.286.01:13:54.69#ibcon#*before return 0, iclass 27, count 0 2006.286.01:13:54.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:13:54.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:13:54.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.01:13:54.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.01:13:54.69$vck44/va=3,7 2006.286.01:13:54.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.01:13:54.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.01:13:54.69#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:54.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:13:54.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:13:54.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:13:54.75#ibcon#enter wrdev, iclass 29, count 2 2006.286.01:13:54.75#ibcon#first serial, iclass 29, count 2 2006.286.01:13:54.75#ibcon#enter sib2, iclass 29, count 2 2006.286.01:13:54.75#ibcon#flushed, iclass 29, count 2 2006.286.01:13:54.75#ibcon#about to write, iclass 29, count 2 2006.286.01:13:54.75#ibcon#wrote, iclass 29, count 2 2006.286.01:13:54.75#ibcon#about to read 3, iclass 29, count 2 2006.286.01:13:54.77#ibcon#read 3, iclass 29, count 2 2006.286.01:13:54.77#ibcon#about to read 4, iclass 29, count 2 2006.286.01:13:54.77#ibcon#read 4, iclass 29, count 2 2006.286.01:13:54.77#ibcon#about to read 5, iclass 29, count 2 2006.286.01:13:54.77#ibcon#read 5, iclass 29, count 2 2006.286.01:13:54.77#ibcon#about to read 6, iclass 29, count 2 2006.286.01:13:54.77#ibcon#read 6, iclass 29, count 2 2006.286.01:13:54.77#ibcon#end of sib2, iclass 29, count 2 2006.286.01:13:54.77#ibcon#*mode == 0, iclass 29, count 2 2006.286.01:13:54.77#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.01:13:54.77#ibcon#[25=AT03-07\r\n] 2006.286.01:13:54.77#ibcon#*before write, iclass 29, count 2 2006.286.01:13:54.77#ibcon#enter sib2, iclass 29, count 2 2006.286.01:13:54.77#ibcon#flushed, iclass 29, count 2 2006.286.01:13:54.77#ibcon#about to write, iclass 29, count 2 2006.286.01:13:54.77#ibcon#wrote, iclass 29, count 2 2006.286.01:13:54.77#ibcon#about to read 3, iclass 29, count 2 2006.286.01:13:54.80#ibcon#read 3, iclass 29, count 2 2006.286.01:13:54.80#ibcon#about to read 4, iclass 29, count 2 2006.286.01:13:54.80#ibcon#read 4, iclass 29, count 2 2006.286.01:13:54.80#ibcon#about to read 5, iclass 29, count 2 2006.286.01:13:54.80#ibcon#read 5, iclass 29, count 2 2006.286.01:13:54.80#ibcon#about to read 6, iclass 29, count 2 2006.286.01:13:54.80#ibcon#read 6, iclass 29, count 2 2006.286.01:13:54.80#ibcon#end of sib2, iclass 29, count 2 2006.286.01:13:54.80#ibcon#*after write, iclass 29, count 2 2006.286.01:13:54.80#ibcon#*before return 0, iclass 29, count 2 2006.286.01:13:54.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:13:54.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:13:54.80#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.01:13:54.80#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:54.80#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:13:54.92#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:13:54.92#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:13:54.92#ibcon#enter wrdev, iclass 29, count 0 2006.286.01:13:54.92#ibcon#first serial, iclass 29, count 0 2006.286.01:13:54.92#ibcon#enter sib2, iclass 29, count 0 2006.286.01:13:54.92#ibcon#flushed, iclass 29, count 0 2006.286.01:13:54.92#ibcon#about to write, iclass 29, count 0 2006.286.01:13:54.92#ibcon#wrote, iclass 29, count 0 2006.286.01:13:54.92#ibcon#about to read 3, iclass 29, count 0 2006.286.01:13:54.94#ibcon#read 3, iclass 29, count 0 2006.286.01:13:54.94#ibcon#about to read 4, iclass 29, count 0 2006.286.01:13:54.94#ibcon#read 4, iclass 29, count 0 2006.286.01:13:54.94#ibcon#about to read 5, iclass 29, count 0 2006.286.01:13:54.94#ibcon#read 5, iclass 29, count 0 2006.286.01:13:54.94#ibcon#about to read 6, iclass 29, count 0 2006.286.01:13:54.94#ibcon#read 6, iclass 29, count 0 2006.286.01:13:54.94#ibcon#end of sib2, iclass 29, count 0 2006.286.01:13:54.94#ibcon#*mode == 0, iclass 29, count 0 2006.286.01:13:54.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.01:13:54.94#ibcon#[25=USB\r\n] 2006.286.01:13:54.94#ibcon#*before write, iclass 29, count 0 2006.286.01:13:54.94#ibcon#enter sib2, iclass 29, count 0 2006.286.01:13:54.94#ibcon#flushed, iclass 29, count 0 2006.286.01:13:54.94#ibcon#about to write, iclass 29, count 0 2006.286.01:13:54.94#ibcon#wrote, iclass 29, count 0 2006.286.01:13:54.94#ibcon#about to read 3, iclass 29, count 0 2006.286.01:13:54.97#ibcon#read 3, iclass 29, count 0 2006.286.01:13:54.97#ibcon#about to read 4, iclass 29, count 0 2006.286.01:13:54.97#ibcon#read 4, iclass 29, count 0 2006.286.01:13:54.97#ibcon#about to read 5, iclass 29, count 0 2006.286.01:13:54.97#ibcon#read 5, iclass 29, count 0 2006.286.01:13:54.97#ibcon#about to read 6, iclass 29, count 0 2006.286.01:13:54.97#ibcon#read 6, iclass 29, count 0 2006.286.01:13:54.97#ibcon#end of sib2, iclass 29, count 0 2006.286.01:13:54.97#ibcon#*after write, iclass 29, count 0 2006.286.01:13:54.97#ibcon#*before return 0, iclass 29, count 0 2006.286.01:13:54.97#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:13:54.97#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:13:54.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.01:13:54.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.01:13:54.97$vck44/valo=4,624.99 2006.286.01:13:54.97#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.01:13:54.97#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.01:13:54.97#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:54.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:13:54.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:13:54.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:13:54.97#ibcon#enter wrdev, iclass 31, count 0 2006.286.01:13:54.97#ibcon#first serial, iclass 31, count 0 2006.286.01:13:54.97#ibcon#enter sib2, iclass 31, count 0 2006.286.01:13:54.97#ibcon#flushed, iclass 31, count 0 2006.286.01:13:54.97#ibcon#about to write, iclass 31, count 0 2006.286.01:13:54.97#ibcon#wrote, iclass 31, count 0 2006.286.01:13:54.97#ibcon#about to read 3, iclass 31, count 0 2006.286.01:13:54.99#ibcon#read 3, iclass 31, count 0 2006.286.01:13:54.99#ibcon#about to read 4, iclass 31, count 0 2006.286.01:13:54.99#ibcon#read 4, iclass 31, count 0 2006.286.01:13:54.99#ibcon#about to read 5, iclass 31, count 0 2006.286.01:13:54.99#ibcon#read 5, iclass 31, count 0 2006.286.01:13:54.99#ibcon#about to read 6, iclass 31, count 0 2006.286.01:13:54.99#ibcon#read 6, iclass 31, count 0 2006.286.01:13:54.99#ibcon#end of sib2, iclass 31, count 0 2006.286.01:13:54.99#ibcon#*mode == 0, iclass 31, count 0 2006.286.01:13:54.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.01:13:54.99#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:13:54.99#ibcon#*before write, iclass 31, count 0 2006.286.01:13:54.99#ibcon#enter sib2, iclass 31, count 0 2006.286.01:13:54.99#ibcon#flushed, iclass 31, count 0 2006.286.01:13:54.99#ibcon#about to write, iclass 31, count 0 2006.286.01:13:54.99#ibcon#wrote, iclass 31, count 0 2006.286.01:13:54.99#ibcon#about to read 3, iclass 31, count 0 2006.286.01:13:55.03#ibcon#read 3, iclass 31, count 0 2006.286.01:13:55.03#ibcon#about to read 4, iclass 31, count 0 2006.286.01:13:55.03#ibcon#read 4, iclass 31, count 0 2006.286.01:13:55.03#ibcon#about to read 5, iclass 31, count 0 2006.286.01:13:55.03#ibcon#read 5, iclass 31, count 0 2006.286.01:13:55.03#ibcon#about to read 6, iclass 31, count 0 2006.286.01:13:55.03#ibcon#read 6, iclass 31, count 0 2006.286.01:13:55.03#ibcon#end of sib2, iclass 31, count 0 2006.286.01:13:55.03#ibcon#*after write, iclass 31, count 0 2006.286.01:13:55.03#ibcon#*before return 0, iclass 31, count 0 2006.286.01:13:55.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:13:55.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:13:55.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.01:13:55.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.01:13:55.03$vck44/va=4,6 2006.286.01:13:55.03#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.01:13:55.03#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.01:13:55.03#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:55.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:13:55.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:13:55.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:13:55.09#ibcon#enter wrdev, iclass 33, count 2 2006.286.01:13:55.09#ibcon#first serial, iclass 33, count 2 2006.286.01:13:55.09#ibcon#enter sib2, iclass 33, count 2 2006.286.01:13:55.09#ibcon#flushed, iclass 33, count 2 2006.286.01:13:55.09#ibcon#about to write, iclass 33, count 2 2006.286.01:13:55.09#ibcon#wrote, iclass 33, count 2 2006.286.01:13:55.09#ibcon#about to read 3, iclass 33, count 2 2006.286.01:13:55.11#ibcon#read 3, iclass 33, count 2 2006.286.01:13:55.11#ibcon#about to read 4, iclass 33, count 2 2006.286.01:13:55.11#ibcon#read 4, iclass 33, count 2 2006.286.01:13:55.11#ibcon#about to read 5, iclass 33, count 2 2006.286.01:13:55.11#ibcon#read 5, iclass 33, count 2 2006.286.01:13:55.11#ibcon#about to read 6, iclass 33, count 2 2006.286.01:13:55.11#ibcon#read 6, iclass 33, count 2 2006.286.01:13:55.11#ibcon#end of sib2, iclass 33, count 2 2006.286.01:13:55.11#ibcon#*mode == 0, iclass 33, count 2 2006.286.01:13:55.11#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.01:13:55.11#ibcon#[25=AT04-06\r\n] 2006.286.01:13:55.11#ibcon#*before write, iclass 33, count 2 2006.286.01:13:55.11#ibcon#enter sib2, iclass 33, count 2 2006.286.01:13:55.11#ibcon#flushed, iclass 33, count 2 2006.286.01:13:55.11#ibcon#about to write, iclass 33, count 2 2006.286.01:13:55.11#ibcon#wrote, iclass 33, count 2 2006.286.01:13:55.11#ibcon#about to read 3, iclass 33, count 2 2006.286.01:13:55.14#ibcon#read 3, iclass 33, count 2 2006.286.01:13:55.14#ibcon#about to read 4, iclass 33, count 2 2006.286.01:13:55.14#ibcon#read 4, iclass 33, count 2 2006.286.01:13:55.14#ibcon#about to read 5, iclass 33, count 2 2006.286.01:13:55.14#ibcon#read 5, iclass 33, count 2 2006.286.01:13:55.14#ibcon#about to read 6, iclass 33, count 2 2006.286.01:13:55.14#ibcon#read 6, iclass 33, count 2 2006.286.01:13:55.14#ibcon#end of sib2, iclass 33, count 2 2006.286.01:13:55.14#ibcon#*after write, iclass 33, count 2 2006.286.01:13:55.14#ibcon#*before return 0, iclass 33, count 2 2006.286.01:13:55.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:13:55.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:13:55.14#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.01:13:55.14#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:55.14#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:13:55.26#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:13:55.26#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:13:55.26#ibcon#enter wrdev, iclass 33, count 0 2006.286.01:13:55.26#ibcon#first serial, iclass 33, count 0 2006.286.01:13:55.26#ibcon#enter sib2, iclass 33, count 0 2006.286.01:13:55.26#ibcon#flushed, iclass 33, count 0 2006.286.01:13:55.26#ibcon#about to write, iclass 33, count 0 2006.286.01:13:55.26#ibcon#wrote, iclass 33, count 0 2006.286.01:13:55.26#ibcon#about to read 3, iclass 33, count 0 2006.286.01:13:55.28#ibcon#read 3, iclass 33, count 0 2006.286.01:13:55.28#ibcon#about to read 4, iclass 33, count 0 2006.286.01:13:55.28#ibcon#read 4, iclass 33, count 0 2006.286.01:13:55.28#ibcon#about to read 5, iclass 33, count 0 2006.286.01:13:55.28#ibcon#read 5, iclass 33, count 0 2006.286.01:13:55.28#ibcon#about to read 6, iclass 33, count 0 2006.286.01:13:55.28#ibcon#read 6, iclass 33, count 0 2006.286.01:13:55.28#ibcon#end of sib2, iclass 33, count 0 2006.286.01:13:55.28#ibcon#*mode == 0, iclass 33, count 0 2006.286.01:13:55.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.01:13:55.28#ibcon#[25=USB\r\n] 2006.286.01:13:55.28#ibcon#*before write, iclass 33, count 0 2006.286.01:13:55.28#ibcon#enter sib2, iclass 33, count 0 2006.286.01:13:55.28#ibcon#flushed, iclass 33, count 0 2006.286.01:13:55.28#ibcon#about to write, iclass 33, count 0 2006.286.01:13:55.28#ibcon#wrote, iclass 33, count 0 2006.286.01:13:55.28#ibcon#about to read 3, iclass 33, count 0 2006.286.01:13:55.31#ibcon#read 3, iclass 33, count 0 2006.286.01:13:55.31#ibcon#about to read 4, iclass 33, count 0 2006.286.01:13:55.31#ibcon#read 4, iclass 33, count 0 2006.286.01:13:55.31#ibcon#about to read 5, iclass 33, count 0 2006.286.01:13:55.31#ibcon#read 5, iclass 33, count 0 2006.286.01:13:55.31#ibcon#about to read 6, iclass 33, count 0 2006.286.01:13:55.31#ibcon#read 6, iclass 33, count 0 2006.286.01:13:55.31#ibcon#end of sib2, iclass 33, count 0 2006.286.01:13:55.31#ibcon#*after write, iclass 33, count 0 2006.286.01:13:55.31#ibcon#*before return 0, iclass 33, count 0 2006.286.01:13:55.31#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:13:55.31#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:13:55.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.01:13:55.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.01:13:55.31$vck44/valo=5,734.99 2006.286.01:13:55.31#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.01:13:55.31#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.01:13:55.31#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:55.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:13:55.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:13:55.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:13:55.31#ibcon#enter wrdev, iclass 35, count 0 2006.286.01:13:55.31#ibcon#first serial, iclass 35, count 0 2006.286.01:13:55.31#ibcon#enter sib2, iclass 35, count 0 2006.286.01:13:55.31#ibcon#flushed, iclass 35, count 0 2006.286.01:13:55.31#ibcon#about to write, iclass 35, count 0 2006.286.01:13:55.31#ibcon#wrote, iclass 35, count 0 2006.286.01:13:55.31#ibcon#about to read 3, iclass 35, count 0 2006.286.01:13:55.33#ibcon#read 3, iclass 35, count 0 2006.286.01:13:55.33#ibcon#about to read 4, iclass 35, count 0 2006.286.01:13:55.33#ibcon#read 4, iclass 35, count 0 2006.286.01:13:55.33#ibcon#about to read 5, iclass 35, count 0 2006.286.01:13:55.33#ibcon#read 5, iclass 35, count 0 2006.286.01:13:55.33#ibcon#about to read 6, iclass 35, count 0 2006.286.01:13:55.33#ibcon#read 6, iclass 35, count 0 2006.286.01:13:55.33#ibcon#end of sib2, iclass 35, count 0 2006.286.01:13:55.33#ibcon#*mode == 0, iclass 35, count 0 2006.286.01:13:55.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.01:13:55.33#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:13:55.33#ibcon#*before write, iclass 35, count 0 2006.286.01:13:55.33#ibcon#enter sib2, iclass 35, count 0 2006.286.01:13:55.33#ibcon#flushed, iclass 35, count 0 2006.286.01:13:55.33#ibcon#about to write, iclass 35, count 0 2006.286.01:13:55.33#ibcon#wrote, iclass 35, count 0 2006.286.01:13:55.33#ibcon#about to read 3, iclass 35, count 0 2006.286.01:13:55.37#ibcon#read 3, iclass 35, count 0 2006.286.01:13:55.37#ibcon#about to read 4, iclass 35, count 0 2006.286.01:13:55.37#ibcon#read 4, iclass 35, count 0 2006.286.01:13:55.37#ibcon#about to read 5, iclass 35, count 0 2006.286.01:13:55.37#ibcon#read 5, iclass 35, count 0 2006.286.01:13:55.37#ibcon#about to read 6, iclass 35, count 0 2006.286.01:13:55.37#ibcon#read 6, iclass 35, count 0 2006.286.01:13:55.37#ibcon#end of sib2, iclass 35, count 0 2006.286.01:13:55.37#ibcon#*after write, iclass 35, count 0 2006.286.01:13:55.37#ibcon#*before return 0, iclass 35, count 0 2006.286.01:13:55.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:13:55.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:13:55.37#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.01:13:55.37#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.01:13:55.37$vck44/va=5,3 2006.286.01:13:55.37#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.01:13:55.37#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.01:13:55.37#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:55.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:13:55.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:13:55.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:13:55.43#ibcon#enter wrdev, iclass 37, count 2 2006.286.01:13:55.43#ibcon#first serial, iclass 37, count 2 2006.286.01:13:55.43#ibcon#enter sib2, iclass 37, count 2 2006.286.01:13:55.43#ibcon#flushed, iclass 37, count 2 2006.286.01:13:55.43#ibcon#about to write, iclass 37, count 2 2006.286.01:13:55.43#ibcon#wrote, iclass 37, count 2 2006.286.01:13:55.43#ibcon#about to read 3, iclass 37, count 2 2006.286.01:13:55.45#ibcon#read 3, iclass 37, count 2 2006.286.01:13:55.45#ibcon#about to read 4, iclass 37, count 2 2006.286.01:13:55.45#ibcon#read 4, iclass 37, count 2 2006.286.01:13:55.45#ibcon#about to read 5, iclass 37, count 2 2006.286.01:13:55.45#ibcon#read 5, iclass 37, count 2 2006.286.01:13:55.45#ibcon#about to read 6, iclass 37, count 2 2006.286.01:13:55.45#ibcon#read 6, iclass 37, count 2 2006.286.01:13:55.45#ibcon#end of sib2, iclass 37, count 2 2006.286.01:13:55.45#ibcon#*mode == 0, iclass 37, count 2 2006.286.01:13:55.45#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.01:13:55.45#ibcon#[25=AT05-03\r\n] 2006.286.01:13:55.45#ibcon#*before write, iclass 37, count 2 2006.286.01:13:55.45#ibcon#enter sib2, iclass 37, count 2 2006.286.01:13:55.45#ibcon#flushed, iclass 37, count 2 2006.286.01:13:55.45#ibcon#about to write, iclass 37, count 2 2006.286.01:13:55.45#ibcon#wrote, iclass 37, count 2 2006.286.01:13:55.45#ibcon#about to read 3, iclass 37, count 2 2006.286.01:13:55.48#ibcon#read 3, iclass 37, count 2 2006.286.01:13:55.48#ibcon#about to read 4, iclass 37, count 2 2006.286.01:13:55.48#ibcon#read 4, iclass 37, count 2 2006.286.01:13:55.48#ibcon#about to read 5, iclass 37, count 2 2006.286.01:13:55.48#ibcon#read 5, iclass 37, count 2 2006.286.01:13:55.48#ibcon#about to read 6, iclass 37, count 2 2006.286.01:13:55.48#ibcon#read 6, iclass 37, count 2 2006.286.01:13:55.48#ibcon#end of sib2, iclass 37, count 2 2006.286.01:13:55.48#ibcon#*after write, iclass 37, count 2 2006.286.01:13:55.48#ibcon#*before return 0, iclass 37, count 2 2006.286.01:13:55.48#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:13:55.48#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:13:55.48#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.01:13:55.48#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:55.48#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:13:55.60#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:13:55.60#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:13:55.60#ibcon#enter wrdev, iclass 37, count 0 2006.286.01:13:55.60#ibcon#first serial, iclass 37, count 0 2006.286.01:13:55.60#ibcon#enter sib2, iclass 37, count 0 2006.286.01:13:55.60#ibcon#flushed, iclass 37, count 0 2006.286.01:13:55.60#ibcon#about to write, iclass 37, count 0 2006.286.01:13:55.60#ibcon#wrote, iclass 37, count 0 2006.286.01:13:55.60#ibcon#about to read 3, iclass 37, count 0 2006.286.01:13:55.62#ibcon#read 3, iclass 37, count 0 2006.286.01:13:55.62#ibcon#about to read 4, iclass 37, count 0 2006.286.01:13:55.62#ibcon#read 4, iclass 37, count 0 2006.286.01:13:55.62#ibcon#about to read 5, iclass 37, count 0 2006.286.01:13:55.62#ibcon#read 5, iclass 37, count 0 2006.286.01:13:55.62#ibcon#about to read 6, iclass 37, count 0 2006.286.01:13:55.62#ibcon#read 6, iclass 37, count 0 2006.286.01:13:55.62#ibcon#end of sib2, iclass 37, count 0 2006.286.01:13:55.62#ibcon#*mode == 0, iclass 37, count 0 2006.286.01:13:55.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.01:13:55.62#ibcon#[25=USB\r\n] 2006.286.01:13:55.62#ibcon#*before write, iclass 37, count 0 2006.286.01:13:55.62#ibcon#enter sib2, iclass 37, count 0 2006.286.01:13:55.62#ibcon#flushed, iclass 37, count 0 2006.286.01:13:55.62#ibcon#about to write, iclass 37, count 0 2006.286.01:13:55.62#ibcon#wrote, iclass 37, count 0 2006.286.01:13:55.62#ibcon#about to read 3, iclass 37, count 0 2006.286.01:13:55.65#ibcon#read 3, iclass 37, count 0 2006.286.01:13:55.65#ibcon#about to read 4, iclass 37, count 0 2006.286.01:13:55.65#ibcon#read 4, iclass 37, count 0 2006.286.01:13:55.65#ibcon#about to read 5, iclass 37, count 0 2006.286.01:13:55.65#ibcon#read 5, iclass 37, count 0 2006.286.01:13:55.65#ibcon#about to read 6, iclass 37, count 0 2006.286.01:13:55.65#ibcon#read 6, iclass 37, count 0 2006.286.01:13:55.65#ibcon#end of sib2, iclass 37, count 0 2006.286.01:13:55.65#ibcon#*after write, iclass 37, count 0 2006.286.01:13:55.65#ibcon#*before return 0, iclass 37, count 0 2006.286.01:13:55.65#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:13:55.65#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:13:55.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.01:13:55.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.01:13:55.65$vck44/valo=6,814.99 2006.286.01:13:55.65#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.01:13:55.65#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.01:13:55.65#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:55.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:13:55.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:13:55.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:13:55.65#ibcon#enter wrdev, iclass 39, count 0 2006.286.01:13:55.65#ibcon#first serial, iclass 39, count 0 2006.286.01:13:55.65#ibcon#enter sib2, iclass 39, count 0 2006.286.01:13:55.65#ibcon#flushed, iclass 39, count 0 2006.286.01:13:55.65#ibcon#about to write, iclass 39, count 0 2006.286.01:13:55.65#ibcon#wrote, iclass 39, count 0 2006.286.01:13:55.65#ibcon#about to read 3, iclass 39, count 0 2006.286.01:13:55.67#ibcon#read 3, iclass 39, count 0 2006.286.01:13:55.67#ibcon#about to read 4, iclass 39, count 0 2006.286.01:13:55.67#ibcon#read 4, iclass 39, count 0 2006.286.01:13:55.67#ibcon#about to read 5, iclass 39, count 0 2006.286.01:13:55.67#ibcon#read 5, iclass 39, count 0 2006.286.01:13:55.67#ibcon#about to read 6, iclass 39, count 0 2006.286.01:13:55.67#ibcon#read 6, iclass 39, count 0 2006.286.01:13:55.67#ibcon#end of sib2, iclass 39, count 0 2006.286.01:13:55.67#ibcon#*mode == 0, iclass 39, count 0 2006.286.01:13:55.67#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.01:13:55.67#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:13:55.67#ibcon#*before write, iclass 39, count 0 2006.286.01:13:55.67#ibcon#enter sib2, iclass 39, count 0 2006.286.01:13:55.67#ibcon#flushed, iclass 39, count 0 2006.286.01:13:55.67#ibcon#about to write, iclass 39, count 0 2006.286.01:13:55.67#ibcon#wrote, iclass 39, count 0 2006.286.01:13:55.67#ibcon#about to read 3, iclass 39, count 0 2006.286.01:13:55.71#ibcon#read 3, iclass 39, count 0 2006.286.01:13:55.71#ibcon#about to read 4, iclass 39, count 0 2006.286.01:13:55.71#ibcon#read 4, iclass 39, count 0 2006.286.01:13:55.71#ibcon#about to read 5, iclass 39, count 0 2006.286.01:13:55.71#ibcon#read 5, iclass 39, count 0 2006.286.01:13:55.71#ibcon#about to read 6, iclass 39, count 0 2006.286.01:13:55.71#ibcon#read 6, iclass 39, count 0 2006.286.01:13:55.71#ibcon#end of sib2, iclass 39, count 0 2006.286.01:13:55.71#ibcon#*after write, iclass 39, count 0 2006.286.01:13:55.71#ibcon#*before return 0, iclass 39, count 0 2006.286.01:13:55.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:13:55.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:13:55.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.01:13:55.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.01:13:55.71$vck44/va=6,4 2006.286.01:13:55.71#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.01:13:55.71#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.01:13:55.71#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:55.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:13:55.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:13:55.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:13:55.77#ibcon#enter wrdev, iclass 3, count 2 2006.286.01:13:55.77#ibcon#first serial, iclass 3, count 2 2006.286.01:13:55.77#ibcon#enter sib2, iclass 3, count 2 2006.286.01:13:55.77#ibcon#flushed, iclass 3, count 2 2006.286.01:13:55.77#ibcon#about to write, iclass 3, count 2 2006.286.01:13:55.77#ibcon#wrote, iclass 3, count 2 2006.286.01:13:55.77#ibcon#about to read 3, iclass 3, count 2 2006.286.01:13:55.79#ibcon#read 3, iclass 3, count 2 2006.286.01:13:55.79#ibcon#about to read 4, iclass 3, count 2 2006.286.01:13:55.79#ibcon#read 4, iclass 3, count 2 2006.286.01:13:55.79#ibcon#about to read 5, iclass 3, count 2 2006.286.01:13:55.79#ibcon#read 5, iclass 3, count 2 2006.286.01:13:55.79#ibcon#about to read 6, iclass 3, count 2 2006.286.01:13:55.79#ibcon#read 6, iclass 3, count 2 2006.286.01:13:55.79#ibcon#end of sib2, iclass 3, count 2 2006.286.01:13:55.79#ibcon#*mode == 0, iclass 3, count 2 2006.286.01:13:55.79#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.01:13:55.79#ibcon#[25=AT06-04\r\n] 2006.286.01:13:55.79#ibcon#*before write, iclass 3, count 2 2006.286.01:13:55.79#ibcon#enter sib2, iclass 3, count 2 2006.286.01:13:55.79#ibcon#flushed, iclass 3, count 2 2006.286.01:13:55.79#ibcon#about to write, iclass 3, count 2 2006.286.01:13:55.79#ibcon#wrote, iclass 3, count 2 2006.286.01:13:55.79#ibcon#about to read 3, iclass 3, count 2 2006.286.01:13:55.82#ibcon#read 3, iclass 3, count 2 2006.286.01:13:55.82#ibcon#about to read 4, iclass 3, count 2 2006.286.01:13:55.82#ibcon#read 4, iclass 3, count 2 2006.286.01:13:55.82#ibcon#about to read 5, iclass 3, count 2 2006.286.01:13:55.82#ibcon#read 5, iclass 3, count 2 2006.286.01:13:55.82#ibcon#about to read 6, iclass 3, count 2 2006.286.01:13:55.82#ibcon#read 6, iclass 3, count 2 2006.286.01:13:55.82#ibcon#end of sib2, iclass 3, count 2 2006.286.01:13:55.82#ibcon#*after write, iclass 3, count 2 2006.286.01:13:55.82#ibcon#*before return 0, iclass 3, count 2 2006.286.01:13:55.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:13:55.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:13:55.82#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.01:13:55.82#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:55.82#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:13:55.94#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:13:55.94#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:13:55.94#ibcon#enter wrdev, iclass 3, count 0 2006.286.01:13:55.94#ibcon#first serial, iclass 3, count 0 2006.286.01:13:55.94#ibcon#enter sib2, iclass 3, count 0 2006.286.01:13:55.94#ibcon#flushed, iclass 3, count 0 2006.286.01:13:55.94#ibcon#about to write, iclass 3, count 0 2006.286.01:13:55.94#ibcon#wrote, iclass 3, count 0 2006.286.01:13:55.94#ibcon#about to read 3, iclass 3, count 0 2006.286.01:13:55.96#ibcon#read 3, iclass 3, count 0 2006.286.01:13:55.96#ibcon#about to read 4, iclass 3, count 0 2006.286.01:13:55.96#ibcon#read 4, iclass 3, count 0 2006.286.01:13:55.96#ibcon#about to read 5, iclass 3, count 0 2006.286.01:13:55.96#ibcon#read 5, iclass 3, count 0 2006.286.01:13:55.96#ibcon#about to read 6, iclass 3, count 0 2006.286.01:13:55.96#ibcon#read 6, iclass 3, count 0 2006.286.01:13:55.96#ibcon#end of sib2, iclass 3, count 0 2006.286.01:13:55.96#ibcon#*mode == 0, iclass 3, count 0 2006.286.01:13:55.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.01:13:55.96#ibcon#[25=USB\r\n] 2006.286.01:13:55.96#ibcon#*before write, iclass 3, count 0 2006.286.01:13:55.96#ibcon#enter sib2, iclass 3, count 0 2006.286.01:13:55.96#ibcon#flushed, iclass 3, count 0 2006.286.01:13:55.96#ibcon#about to write, iclass 3, count 0 2006.286.01:13:55.96#ibcon#wrote, iclass 3, count 0 2006.286.01:13:55.96#ibcon#about to read 3, iclass 3, count 0 2006.286.01:13:55.99#ibcon#read 3, iclass 3, count 0 2006.286.01:13:55.99#ibcon#about to read 4, iclass 3, count 0 2006.286.01:13:55.99#ibcon#read 4, iclass 3, count 0 2006.286.01:13:55.99#ibcon#about to read 5, iclass 3, count 0 2006.286.01:13:55.99#ibcon#read 5, iclass 3, count 0 2006.286.01:13:55.99#ibcon#about to read 6, iclass 3, count 0 2006.286.01:13:55.99#ibcon#read 6, iclass 3, count 0 2006.286.01:13:55.99#ibcon#end of sib2, iclass 3, count 0 2006.286.01:13:55.99#ibcon#*after write, iclass 3, count 0 2006.286.01:13:55.99#ibcon#*before return 0, iclass 3, count 0 2006.286.01:13:55.99#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:13:55.99#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:13:55.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.01:13:55.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.01:13:55.99$vck44/valo=7,864.99 2006.286.01:13:55.99#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.01:13:55.99#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.01:13:55.99#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:55.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:13:55.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:13:55.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:13:55.99#ibcon#enter wrdev, iclass 5, count 0 2006.286.01:13:55.99#ibcon#first serial, iclass 5, count 0 2006.286.01:13:55.99#ibcon#enter sib2, iclass 5, count 0 2006.286.01:13:55.99#ibcon#flushed, iclass 5, count 0 2006.286.01:13:55.99#ibcon#about to write, iclass 5, count 0 2006.286.01:13:55.99#ibcon#wrote, iclass 5, count 0 2006.286.01:13:55.99#ibcon#about to read 3, iclass 5, count 0 2006.286.01:13:56.01#ibcon#read 3, iclass 5, count 0 2006.286.01:13:56.01#ibcon#about to read 4, iclass 5, count 0 2006.286.01:13:56.01#ibcon#read 4, iclass 5, count 0 2006.286.01:13:56.01#ibcon#about to read 5, iclass 5, count 0 2006.286.01:13:56.01#ibcon#read 5, iclass 5, count 0 2006.286.01:13:56.01#ibcon#about to read 6, iclass 5, count 0 2006.286.01:13:56.01#ibcon#read 6, iclass 5, count 0 2006.286.01:13:56.01#ibcon#end of sib2, iclass 5, count 0 2006.286.01:13:56.01#ibcon#*mode == 0, iclass 5, count 0 2006.286.01:13:56.01#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.01:13:56.01#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:13:56.01#ibcon#*before write, iclass 5, count 0 2006.286.01:13:56.01#ibcon#enter sib2, iclass 5, count 0 2006.286.01:13:56.01#ibcon#flushed, iclass 5, count 0 2006.286.01:13:56.01#ibcon#about to write, iclass 5, count 0 2006.286.01:13:56.01#ibcon#wrote, iclass 5, count 0 2006.286.01:13:56.01#ibcon#about to read 3, iclass 5, count 0 2006.286.01:13:56.05#ibcon#read 3, iclass 5, count 0 2006.286.01:13:56.05#ibcon#about to read 4, iclass 5, count 0 2006.286.01:13:56.05#ibcon#read 4, iclass 5, count 0 2006.286.01:13:56.05#ibcon#about to read 5, iclass 5, count 0 2006.286.01:13:56.05#ibcon#read 5, iclass 5, count 0 2006.286.01:13:56.05#ibcon#about to read 6, iclass 5, count 0 2006.286.01:13:56.05#ibcon#read 6, iclass 5, count 0 2006.286.01:13:56.05#ibcon#end of sib2, iclass 5, count 0 2006.286.01:13:56.05#ibcon#*after write, iclass 5, count 0 2006.286.01:13:56.05#ibcon#*before return 0, iclass 5, count 0 2006.286.01:13:56.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:13:56.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:13:56.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.01:13:56.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.01:13:56.05$vck44/va=7,4 2006.286.01:13:56.05#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.01:13:56.05#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.01:13:56.05#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:56.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:13:56.11#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:13:56.11#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:13:56.11#ibcon#enter wrdev, iclass 7, count 2 2006.286.01:13:56.11#ibcon#first serial, iclass 7, count 2 2006.286.01:13:56.11#ibcon#enter sib2, iclass 7, count 2 2006.286.01:13:56.11#ibcon#flushed, iclass 7, count 2 2006.286.01:13:56.11#ibcon#about to write, iclass 7, count 2 2006.286.01:13:56.11#ibcon#wrote, iclass 7, count 2 2006.286.01:13:56.11#ibcon#about to read 3, iclass 7, count 2 2006.286.01:13:56.13#ibcon#read 3, iclass 7, count 2 2006.286.01:13:56.13#ibcon#about to read 4, iclass 7, count 2 2006.286.01:13:56.13#ibcon#read 4, iclass 7, count 2 2006.286.01:13:56.13#ibcon#about to read 5, iclass 7, count 2 2006.286.01:13:56.13#ibcon#read 5, iclass 7, count 2 2006.286.01:13:56.13#ibcon#about to read 6, iclass 7, count 2 2006.286.01:13:56.13#ibcon#read 6, iclass 7, count 2 2006.286.01:13:56.13#ibcon#end of sib2, iclass 7, count 2 2006.286.01:13:56.13#ibcon#*mode == 0, iclass 7, count 2 2006.286.01:13:56.13#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.01:13:56.13#ibcon#[25=AT07-04\r\n] 2006.286.01:13:56.13#ibcon#*before write, iclass 7, count 2 2006.286.01:13:56.13#ibcon#enter sib2, iclass 7, count 2 2006.286.01:13:56.13#ibcon#flushed, iclass 7, count 2 2006.286.01:13:56.13#ibcon#about to write, iclass 7, count 2 2006.286.01:13:56.13#ibcon#wrote, iclass 7, count 2 2006.286.01:13:56.13#ibcon#about to read 3, iclass 7, count 2 2006.286.01:13:56.16#ibcon#read 3, iclass 7, count 2 2006.286.01:13:56.16#ibcon#about to read 4, iclass 7, count 2 2006.286.01:13:56.16#ibcon#read 4, iclass 7, count 2 2006.286.01:13:56.16#ibcon#about to read 5, iclass 7, count 2 2006.286.01:13:56.16#ibcon#read 5, iclass 7, count 2 2006.286.01:13:56.16#ibcon#about to read 6, iclass 7, count 2 2006.286.01:13:56.16#ibcon#read 6, iclass 7, count 2 2006.286.01:13:56.16#ibcon#end of sib2, iclass 7, count 2 2006.286.01:13:56.16#ibcon#*after write, iclass 7, count 2 2006.286.01:13:56.16#ibcon#*before return 0, iclass 7, count 2 2006.286.01:13:56.16#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:13:56.16#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:13:56.16#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.01:13:56.16#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:56.16#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:13:56.28#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:13:56.28#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:13:56.28#ibcon#enter wrdev, iclass 7, count 0 2006.286.01:13:56.28#ibcon#first serial, iclass 7, count 0 2006.286.01:13:56.28#ibcon#enter sib2, iclass 7, count 0 2006.286.01:13:56.28#ibcon#flushed, iclass 7, count 0 2006.286.01:13:56.28#ibcon#about to write, iclass 7, count 0 2006.286.01:13:56.28#ibcon#wrote, iclass 7, count 0 2006.286.01:13:56.28#ibcon#about to read 3, iclass 7, count 0 2006.286.01:13:56.30#ibcon#read 3, iclass 7, count 0 2006.286.01:13:56.30#ibcon#about to read 4, iclass 7, count 0 2006.286.01:13:56.30#ibcon#read 4, iclass 7, count 0 2006.286.01:13:56.30#ibcon#about to read 5, iclass 7, count 0 2006.286.01:13:56.30#ibcon#read 5, iclass 7, count 0 2006.286.01:13:56.30#ibcon#about to read 6, iclass 7, count 0 2006.286.01:13:56.30#ibcon#read 6, iclass 7, count 0 2006.286.01:13:56.30#ibcon#end of sib2, iclass 7, count 0 2006.286.01:13:56.30#ibcon#*mode == 0, iclass 7, count 0 2006.286.01:13:56.30#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.01:13:56.30#ibcon#[25=USB\r\n] 2006.286.01:13:56.30#ibcon#*before write, iclass 7, count 0 2006.286.01:13:56.30#ibcon#enter sib2, iclass 7, count 0 2006.286.01:13:56.30#ibcon#flushed, iclass 7, count 0 2006.286.01:13:56.30#ibcon#about to write, iclass 7, count 0 2006.286.01:13:56.30#ibcon#wrote, iclass 7, count 0 2006.286.01:13:56.30#ibcon#about to read 3, iclass 7, count 0 2006.286.01:13:56.33#ibcon#read 3, iclass 7, count 0 2006.286.01:13:56.33#ibcon#about to read 4, iclass 7, count 0 2006.286.01:13:56.33#ibcon#read 4, iclass 7, count 0 2006.286.01:13:56.33#ibcon#about to read 5, iclass 7, count 0 2006.286.01:13:56.33#ibcon#read 5, iclass 7, count 0 2006.286.01:13:56.33#ibcon#about to read 6, iclass 7, count 0 2006.286.01:13:56.33#ibcon#read 6, iclass 7, count 0 2006.286.01:13:56.33#ibcon#end of sib2, iclass 7, count 0 2006.286.01:13:56.33#ibcon#*after write, iclass 7, count 0 2006.286.01:13:56.33#ibcon#*before return 0, iclass 7, count 0 2006.286.01:13:56.33#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:13:56.33#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:13:56.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.01:13:56.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.01:13:56.33$vck44/valo=8,884.99 2006.286.01:13:56.33#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.01:13:56.33#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.01:13:56.33#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:56.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:13:56.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:13:56.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:13:56.33#ibcon#enter wrdev, iclass 11, count 0 2006.286.01:13:56.33#ibcon#first serial, iclass 11, count 0 2006.286.01:13:56.33#ibcon#enter sib2, iclass 11, count 0 2006.286.01:13:56.33#ibcon#flushed, iclass 11, count 0 2006.286.01:13:56.33#ibcon#about to write, iclass 11, count 0 2006.286.01:13:56.33#ibcon#wrote, iclass 11, count 0 2006.286.01:13:56.33#ibcon#about to read 3, iclass 11, count 0 2006.286.01:13:56.35#ibcon#read 3, iclass 11, count 0 2006.286.01:13:56.35#ibcon#about to read 4, iclass 11, count 0 2006.286.01:13:56.35#ibcon#read 4, iclass 11, count 0 2006.286.01:13:56.35#ibcon#about to read 5, iclass 11, count 0 2006.286.01:13:56.35#ibcon#read 5, iclass 11, count 0 2006.286.01:13:56.35#ibcon#about to read 6, iclass 11, count 0 2006.286.01:13:56.35#ibcon#read 6, iclass 11, count 0 2006.286.01:13:56.35#ibcon#end of sib2, iclass 11, count 0 2006.286.01:13:56.35#ibcon#*mode == 0, iclass 11, count 0 2006.286.01:13:56.35#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.01:13:56.35#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:13:56.35#ibcon#*before write, iclass 11, count 0 2006.286.01:13:56.35#ibcon#enter sib2, iclass 11, count 0 2006.286.01:13:56.35#ibcon#flushed, iclass 11, count 0 2006.286.01:13:56.35#ibcon#about to write, iclass 11, count 0 2006.286.01:13:56.35#ibcon#wrote, iclass 11, count 0 2006.286.01:13:56.35#ibcon#about to read 3, iclass 11, count 0 2006.286.01:13:56.39#ibcon#read 3, iclass 11, count 0 2006.286.01:13:56.39#ibcon#about to read 4, iclass 11, count 0 2006.286.01:13:56.39#ibcon#read 4, iclass 11, count 0 2006.286.01:13:56.39#ibcon#about to read 5, iclass 11, count 0 2006.286.01:13:56.39#ibcon#read 5, iclass 11, count 0 2006.286.01:13:56.39#ibcon#about to read 6, iclass 11, count 0 2006.286.01:13:56.39#ibcon#read 6, iclass 11, count 0 2006.286.01:13:56.39#ibcon#end of sib2, iclass 11, count 0 2006.286.01:13:56.39#ibcon#*after write, iclass 11, count 0 2006.286.01:13:56.39#ibcon#*before return 0, iclass 11, count 0 2006.286.01:13:56.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:13:56.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:13:56.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.01:13:56.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.01:13:56.39$vck44/va=8,3 2006.286.01:13:56.39#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.01:13:56.39#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.01:13:56.39#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:56.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:13:56.45#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:13:56.45#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:13:56.45#ibcon#enter wrdev, iclass 13, count 2 2006.286.01:13:56.45#ibcon#first serial, iclass 13, count 2 2006.286.01:13:56.45#ibcon#enter sib2, iclass 13, count 2 2006.286.01:13:56.45#ibcon#flushed, iclass 13, count 2 2006.286.01:13:56.45#ibcon#about to write, iclass 13, count 2 2006.286.01:13:56.45#ibcon#wrote, iclass 13, count 2 2006.286.01:13:56.45#ibcon#about to read 3, iclass 13, count 2 2006.286.01:13:56.47#ibcon#read 3, iclass 13, count 2 2006.286.01:13:56.47#ibcon#about to read 4, iclass 13, count 2 2006.286.01:13:56.47#ibcon#read 4, iclass 13, count 2 2006.286.01:13:56.47#ibcon#about to read 5, iclass 13, count 2 2006.286.01:13:56.47#ibcon#read 5, iclass 13, count 2 2006.286.01:13:56.47#ibcon#about to read 6, iclass 13, count 2 2006.286.01:13:56.47#ibcon#read 6, iclass 13, count 2 2006.286.01:13:56.47#ibcon#end of sib2, iclass 13, count 2 2006.286.01:13:56.47#ibcon#*mode == 0, iclass 13, count 2 2006.286.01:13:56.47#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.01:13:56.47#ibcon#[25=AT08-03\r\n] 2006.286.01:13:56.47#ibcon#*before write, iclass 13, count 2 2006.286.01:13:56.47#ibcon#enter sib2, iclass 13, count 2 2006.286.01:13:56.47#ibcon#flushed, iclass 13, count 2 2006.286.01:13:56.47#ibcon#about to write, iclass 13, count 2 2006.286.01:13:56.47#ibcon#wrote, iclass 13, count 2 2006.286.01:13:56.47#ibcon#about to read 3, iclass 13, count 2 2006.286.01:13:56.50#ibcon#read 3, iclass 13, count 2 2006.286.01:13:56.50#ibcon#about to read 4, iclass 13, count 2 2006.286.01:13:56.50#ibcon#read 4, iclass 13, count 2 2006.286.01:13:56.50#ibcon#about to read 5, iclass 13, count 2 2006.286.01:13:56.50#ibcon#read 5, iclass 13, count 2 2006.286.01:13:56.50#ibcon#about to read 6, iclass 13, count 2 2006.286.01:13:56.50#ibcon#read 6, iclass 13, count 2 2006.286.01:13:56.50#ibcon#end of sib2, iclass 13, count 2 2006.286.01:13:56.50#ibcon#*after write, iclass 13, count 2 2006.286.01:13:56.50#ibcon#*before return 0, iclass 13, count 2 2006.286.01:13:56.50#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:13:56.50#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:13:56.50#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.01:13:56.50#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:56.50#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:13:56.62#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:13:56.62#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:13:56.62#ibcon#enter wrdev, iclass 13, count 0 2006.286.01:13:56.62#ibcon#first serial, iclass 13, count 0 2006.286.01:13:56.62#ibcon#enter sib2, iclass 13, count 0 2006.286.01:13:56.62#ibcon#flushed, iclass 13, count 0 2006.286.01:13:56.62#ibcon#about to write, iclass 13, count 0 2006.286.01:13:56.62#ibcon#wrote, iclass 13, count 0 2006.286.01:13:56.62#ibcon#about to read 3, iclass 13, count 0 2006.286.01:13:56.64#ibcon#read 3, iclass 13, count 0 2006.286.01:13:56.64#ibcon#about to read 4, iclass 13, count 0 2006.286.01:13:56.64#ibcon#read 4, iclass 13, count 0 2006.286.01:13:56.64#ibcon#about to read 5, iclass 13, count 0 2006.286.01:13:56.64#ibcon#read 5, iclass 13, count 0 2006.286.01:13:56.64#ibcon#about to read 6, iclass 13, count 0 2006.286.01:13:56.64#ibcon#read 6, iclass 13, count 0 2006.286.01:13:56.64#ibcon#end of sib2, iclass 13, count 0 2006.286.01:13:56.64#ibcon#*mode == 0, iclass 13, count 0 2006.286.01:13:56.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.01:13:56.64#ibcon#[25=USB\r\n] 2006.286.01:13:56.64#ibcon#*before write, iclass 13, count 0 2006.286.01:13:56.64#ibcon#enter sib2, iclass 13, count 0 2006.286.01:13:56.64#ibcon#flushed, iclass 13, count 0 2006.286.01:13:56.64#ibcon#about to write, iclass 13, count 0 2006.286.01:13:56.64#ibcon#wrote, iclass 13, count 0 2006.286.01:13:56.64#ibcon#about to read 3, iclass 13, count 0 2006.286.01:13:56.67#ibcon#read 3, iclass 13, count 0 2006.286.01:13:56.67#ibcon#about to read 4, iclass 13, count 0 2006.286.01:13:56.67#ibcon#read 4, iclass 13, count 0 2006.286.01:13:56.67#ibcon#about to read 5, iclass 13, count 0 2006.286.01:13:56.67#ibcon#read 5, iclass 13, count 0 2006.286.01:13:56.67#ibcon#about to read 6, iclass 13, count 0 2006.286.01:13:56.67#ibcon#read 6, iclass 13, count 0 2006.286.01:13:56.67#ibcon#end of sib2, iclass 13, count 0 2006.286.01:13:56.67#ibcon#*after write, iclass 13, count 0 2006.286.01:13:56.67#ibcon#*before return 0, iclass 13, count 0 2006.286.01:13:56.67#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:13:56.67#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:13:56.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.01:13:56.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.01:13:56.67$vck44/vblo=1,629.99 2006.286.01:13:56.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.01:13:56.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.01:13:56.67#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:56.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:13:56.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:13:56.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:13:56.67#ibcon#enter wrdev, iclass 15, count 0 2006.286.01:13:56.67#ibcon#first serial, iclass 15, count 0 2006.286.01:13:56.67#ibcon#enter sib2, iclass 15, count 0 2006.286.01:13:56.67#ibcon#flushed, iclass 15, count 0 2006.286.01:13:56.67#ibcon#about to write, iclass 15, count 0 2006.286.01:13:56.67#ibcon#wrote, iclass 15, count 0 2006.286.01:13:56.67#ibcon#about to read 3, iclass 15, count 0 2006.286.01:13:56.69#ibcon#read 3, iclass 15, count 0 2006.286.01:13:56.69#ibcon#about to read 4, iclass 15, count 0 2006.286.01:13:56.69#ibcon#read 4, iclass 15, count 0 2006.286.01:13:56.69#ibcon#about to read 5, iclass 15, count 0 2006.286.01:13:56.69#ibcon#read 5, iclass 15, count 0 2006.286.01:13:56.69#ibcon#about to read 6, iclass 15, count 0 2006.286.01:13:56.69#ibcon#read 6, iclass 15, count 0 2006.286.01:13:56.69#ibcon#end of sib2, iclass 15, count 0 2006.286.01:13:56.69#ibcon#*mode == 0, iclass 15, count 0 2006.286.01:13:56.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.01:13:56.69#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:13:56.69#ibcon#*before write, iclass 15, count 0 2006.286.01:13:56.69#ibcon#enter sib2, iclass 15, count 0 2006.286.01:13:56.69#ibcon#flushed, iclass 15, count 0 2006.286.01:13:56.69#ibcon#about to write, iclass 15, count 0 2006.286.01:13:56.69#ibcon#wrote, iclass 15, count 0 2006.286.01:13:56.69#ibcon#about to read 3, iclass 15, count 0 2006.286.01:13:56.73#ibcon#read 3, iclass 15, count 0 2006.286.01:13:56.73#ibcon#about to read 4, iclass 15, count 0 2006.286.01:13:56.73#ibcon#read 4, iclass 15, count 0 2006.286.01:13:56.73#ibcon#about to read 5, iclass 15, count 0 2006.286.01:13:56.73#ibcon#read 5, iclass 15, count 0 2006.286.01:13:56.73#ibcon#about to read 6, iclass 15, count 0 2006.286.01:13:56.73#ibcon#read 6, iclass 15, count 0 2006.286.01:13:56.73#ibcon#end of sib2, iclass 15, count 0 2006.286.01:13:56.73#ibcon#*after write, iclass 15, count 0 2006.286.01:13:56.73#ibcon#*before return 0, iclass 15, count 0 2006.286.01:13:56.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:13:56.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:13:56.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.01:13:56.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.01:13:56.73$vck44/vb=1,4 2006.286.01:13:56.73#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.01:13:56.73#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.01:13:56.73#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:56.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:13:56.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:13:56.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:13:56.73#ibcon#enter wrdev, iclass 17, count 2 2006.286.01:13:56.73#ibcon#first serial, iclass 17, count 2 2006.286.01:13:56.73#ibcon#enter sib2, iclass 17, count 2 2006.286.01:13:56.73#ibcon#flushed, iclass 17, count 2 2006.286.01:13:56.73#ibcon#about to write, iclass 17, count 2 2006.286.01:13:56.73#ibcon#wrote, iclass 17, count 2 2006.286.01:13:56.73#ibcon#about to read 3, iclass 17, count 2 2006.286.01:13:56.75#ibcon#read 3, iclass 17, count 2 2006.286.01:13:56.75#ibcon#about to read 4, iclass 17, count 2 2006.286.01:13:56.75#ibcon#read 4, iclass 17, count 2 2006.286.01:13:56.75#ibcon#about to read 5, iclass 17, count 2 2006.286.01:13:56.75#ibcon#read 5, iclass 17, count 2 2006.286.01:13:56.75#ibcon#about to read 6, iclass 17, count 2 2006.286.01:13:56.75#ibcon#read 6, iclass 17, count 2 2006.286.01:13:56.75#ibcon#end of sib2, iclass 17, count 2 2006.286.01:13:56.75#ibcon#*mode == 0, iclass 17, count 2 2006.286.01:13:56.75#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.01:13:56.75#ibcon#[27=AT01-04\r\n] 2006.286.01:13:56.75#ibcon#*before write, iclass 17, count 2 2006.286.01:13:56.75#ibcon#enter sib2, iclass 17, count 2 2006.286.01:13:56.75#ibcon#flushed, iclass 17, count 2 2006.286.01:13:56.75#ibcon#about to write, iclass 17, count 2 2006.286.01:13:56.75#ibcon#wrote, iclass 17, count 2 2006.286.01:13:56.75#ibcon#about to read 3, iclass 17, count 2 2006.286.01:13:56.78#ibcon#read 3, iclass 17, count 2 2006.286.01:13:56.78#ibcon#about to read 4, iclass 17, count 2 2006.286.01:13:56.78#ibcon#read 4, iclass 17, count 2 2006.286.01:13:56.78#ibcon#about to read 5, iclass 17, count 2 2006.286.01:13:56.78#ibcon#read 5, iclass 17, count 2 2006.286.01:13:56.78#ibcon#about to read 6, iclass 17, count 2 2006.286.01:13:56.78#ibcon#read 6, iclass 17, count 2 2006.286.01:13:56.78#ibcon#end of sib2, iclass 17, count 2 2006.286.01:13:56.78#ibcon#*after write, iclass 17, count 2 2006.286.01:13:56.78#ibcon#*before return 0, iclass 17, count 2 2006.286.01:13:56.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:13:56.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:13:56.78#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.01:13:56.78#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:56.78#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:13:56.90#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:13:56.90#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:13:56.90#ibcon#enter wrdev, iclass 17, count 0 2006.286.01:13:56.90#ibcon#first serial, iclass 17, count 0 2006.286.01:13:56.90#ibcon#enter sib2, iclass 17, count 0 2006.286.01:13:56.90#ibcon#flushed, iclass 17, count 0 2006.286.01:13:56.90#ibcon#about to write, iclass 17, count 0 2006.286.01:13:56.90#ibcon#wrote, iclass 17, count 0 2006.286.01:13:56.90#ibcon#about to read 3, iclass 17, count 0 2006.286.01:13:56.92#ibcon#read 3, iclass 17, count 0 2006.286.01:13:56.92#ibcon#about to read 4, iclass 17, count 0 2006.286.01:13:56.92#ibcon#read 4, iclass 17, count 0 2006.286.01:13:56.92#ibcon#about to read 5, iclass 17, count 0 2006.286.01:13:56.92#ibcon#read 5, iclass 17, count 0 2006.286.01:13:56.92#ibcon#about to read 6, iclass 17, count 0 2006.286.01:13:56.92#ibcon#read 6, iclass 17, count 0 2006.286.01:13:56.92#ibcon#end of sib2, iclass 17, count 0 2006.286.01:13:56.92#ibcon#*mode == 0, iclass 17, count 0 2006.286.01:13:56.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.01:13:56.92#ibcon#[27=USB\r\n] 2006.286.01:13:56.92#ibcon#*before write, iclass 17, count 0 2006.286.01:13:56.92#ibcon#enter sib2, iclass 17, count 0 2006.286.01:13:56.92#ibcon#flushed, iclass 17, count 0 2006.286.01:13:56.92#ibcon#about to write, iclass 17, count 0 2006.286.01:13:56.92#ibcon#wrote, iclass 17, count 0 2006.286.01:13:56.92#ibcon#about to read 3, iclass 17, count 0 2006.286.01:13:56.95#ibcon#read 3, iclass 17, count 0 2006.286.01:13:56.95#ibcon#about to read 4, iclass 17, count 0 2006.286.01:13:56.95#ibcon#read 4, iclass 17, count 0 2006.286.01:13:56.95#ibcon#about to read 5, iclass 17, count 0 2006.286.01:13:56.95#ibcon#read 5, iclass 17, count 0 2006.286.01:13:56.95#ibcon#about to read 6, iclass 17, count 0 2006.286.01:13:56.95#ibcon#read 6, iclass 17, count 0 2006.286.01:13:56.95#ibcon#end of sib2, iclass 17, count 0 2006.286.01:13:56.95#ibcon#*after write, iclass 17, count 0 2006.286.01:13:56.95#ibcon#*before return 0, iclass 17, count 0 2006.286.01:13:56.95#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:13:56.95#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:13:56.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.01:13:56.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.01:13:56.95$vck44/vblo=2,634.99 2006.286.01:13:56.95#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.01:13:56.95#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.01:13:56.95#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:56.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:13:56.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:13:56.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:13:56.95#ibcon#enter wrdev, iclass 19, count 0 2006.286.01:13:56.95#ibcon#first serial, iclass 19, count 0 2006.286.01:13:56.95#ibcon#enter sib2, iclass 19, count 0 2006.286.01:13:56.95#ibcon#flushed, iclass 19, count 0 2006.286.01:13:56.95#ibcon#about to write, iclass 19, count 0 2006.286.01:13:56.95#ibcon#wrote, iclass 19, count 0 2006.286.01:13:56.95#ibcon#about to read 3, iclass 19, count 0 2006.286.01:13:56.97#ibcon#read 3, iclass 19, count 0 2006.286.01:13:56.97#ibcon#about to read 4, iclass 19, count 0 2006.286.01:13:56.97#ibcon#read 4, iclass 19, count 0 2006.286.01:13:56.97#ibcon#about to read 5, iclass 19, count 0 2006.286.01:13:56.97#ibcon#read 5, iclass 19, count 0 2006.286.01:13:56.97#ibcon#about to read 6, iclass 19, count 0 2006.286.01:13:56.97#ibcon#read 6, iclass 19, count 0 2006.286.01:13:56.97#ibcon#end of sib2, iclass 19, count 0 2006.286.01:13:56.97#ibcon#*mode == 0, iclass 19, count 0 2006.286.01:13:56.97#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.01:13:56.97#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:13:56.97#ibcon#*before write, iclass 19, count 0 2006.286.01:13:56.97#ibcon#enter sib2, iclass 19, count 0 2006.286.01:13:56.97#ibcon#flushed, iclass 19, count 0 2006.286.01:13:56.97#ibcon#about to write, iclass 19, count 0 2006.286.01:13:56.97#ibcon#wrote, iclass 19, count 0 2006.286.01:13:56.97#ibcon#about to read 3, iclass 19, count 0 2006.286.01:13:57.01#ibcon#read 3, iclass 19, count 0 2006.286.01:13:57.01#ibcon#about to read 4, iclass 19, count 0 2006.286.01:13:57.01#ibcon#read 4, iclass 19, count 0 2006.286.01:13:57.01#ibcon#about to read 5, iclass 19, count 0 2006.286.01:13:57.01#ibcon#read 5, iclass 19, count 0 2006.286.01:13:57.01#ibcon#about to read 6, iclass 19, count 0 2006.286.01:13:57.01#ibcon#read 6, iclass 19, count 0 2006.286.01:13:57.01#ibcon#end of sib2, iclass 19, count 0 2006.286.01:13:57.01#ibcon#*after write, iclass 19, count 0 2006.286.01:13:57.01#ibcon#*before return 0, iclass 19, count 0 2006.286.01:13:57.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:13:57.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:13:57.01#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.01:13:57.01#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.01:13:57.01$vck44/vb=2,5 2006.286.01:13:57.01#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.01:13:57.01#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.01:13:57.01#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:57.01#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:13:57.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:13:57.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:13:57.07#ibcon#enter wrdev, iclass 21, count 2 2006.286.01:13:57.07#ibcon#first serial, iclass 21, count 2 2006.286.01:13:57.07#ibcon#enter sib2, iclass 21, count 2 2006.286.01:13:57.07#ibcon#flushed, iclass 21, count 2 2006.286.01:13:57.07#ibcon#about to write, iclass 21, count 2 2006.286.01:13:57.07#ibcon#wrote, iclass 21, count 2 2006.286.01:13:57.07#ibcon#about to read 3, iclass 21, count 2 2006.286.01:13:57.09#ibcon#read 3, iclass 21, count 2 2006.286.01:13:57.09#ibcon#about to read 4, iclass 21, count 2 2006.286.01:13:57.09#ibcon#read 4, iclass 21, count 2 2006.286.01:13:57.09#ibcon#about to read 5, iclass 21, count 2 2006.286.01:13:57.09#ibcon#read 5, iclass 21, count 2 2006.286.01:13:57.09#ibcon#about to read 6, iclass 21, count 2 2006.286.01:13:57.09#ibcon#read 6, iclass 21, count 2 2006.286.01:13:57.09#ibcon#end of sib2, iclass 21, count 2 2006.286.01:13:57.09#ibcon#*mode == 0, iclass 21, count 2 2006.286.01:13:57.09#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.01:13:57.09#ibcon#[27=AT02-05\r\n] 2006.286.01:13:57.09#ibcon#*before write, iclass 21, count 2 2006.286.01:13:57.09#ibcon#enter sib2, iclass 21, count 2 2006.286.01:13:57.09#ibcon#flushed, iclass 21, count 2 2006.286.01:13:57.09#ibcon#about to write, iclass 21, count 2 2006.286.01:13:57.09#ibcon#wrote, iclass 21, count 2 2006.286.01:13:57.09#ibcon#about to read 3, iclass 21, count 2 2006.286.01:13:57.12#ibcon#read 3, iclass 21, count 2 2006.286.01:13:57.12#ibcon#about to read 4, iclass 21, count 2 2006.286.01:13:57.12#ibcon#read 4, iclass 21, count 2 2006.286.01:13:57.12#ibcon#about to read 5, iclass 21, count 2 2006.286.01:13:57.12#ibcon#read 5, iclass 21, count 2 2006.286.01:13:57.12#ibcon#about to read 6, iclass 21, count 2 2006.286.01:13:57.12#ibcon#read 6, iclass 21, count 2 2006.286.01:13:57.12#ibcon#end of sib2, iclass 21, count 2 2006.286.01:13:57.12#ibcon#*after write, iclass 21, count 2 2006.286.01:13:57.12#ibcon#*before return 0, iclass 21, count 2 2006.286.01:13:57.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:13:57.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:13:57.12#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.01:13:57.12#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:57.12#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:13:57.24#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:13:57.24#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:13:57.24#ibcon#enter wrdev, iclass 21, count 0 2006.286.01:13:57.24#ibcon#first serial, iclass 21, count 0 2006.286.01:13:57.24#ibcon#enter sib2, iclass 21, count 0 2006.286.01:13:57.24#ibcon#flushed, iclass 21, count 0 2006.286.01:13:57.24#ibcon#about to write, iclass 21, count 0 2006.286.01:13:57.24#ibcon#wrote, iclass 21, count 0 2006.286.01:13:57.24#ibcon#about to read 3, iclass 21, count 0 2006.286.01:13:57.26#ibcon#read 3, iclass 21, count 0 2006.286.01:13:57.26#ibcon#about to read 4, iclass 21, count 0 2006.286.01:13:57.26#ibcon#read 4, iclass 21, count 0 2006.286.01:13:57.26#ibcon#about to read 5, iclass 21, count 0 2006.286.01:13:57.26#ibcon#read 5, iclass 21, count 0 2006.286.01:13:57.26#ibcon#about to read 6, iclass 21, count 0 2006.286.01:13:57.26#ibcon#read 6, iclass 21, count 0 2006.286.01:13:57.26#ibcon#end of sib2, iclass 21, count 0 2006.286.01:13:57.26#ibcon#*mode == 0, iclass 21, count 0 2006.286.01:13:57.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.01:13:57.26#ibcon#[27=USB\r\n] 2006.286.01:13:57.26#ibcon#*before write, iclass 21, count 0 2006.286.01:13:57.26#ibcon#enter sib2, iclass 21, count 0 2006.286.01:13:57.26#ibcon#flushed, iclass 21, count 0 2006.286.01:13:57.26#ibcon#about to write, iclass 21, count 0 2006.286.01:13:57.26#ibcon#wrote, iclass 21, count 0 2006.286.01:13:57.26#ibcon#about to read 3, iclass 21, count 0 2006.286.01:13:57.29#ibcon#read 3, iclass 21, count 0 2006.286.01:13:57.29#ibcon#about to read 4, iclass 21, count 0 2006.286.01:13:57.29#ibcon#read 4, iclass 21, count 0 2006.286.01:13:57.29#ibcon#about to read 5, iclass 21, count 0 2006.286.01:13:57.29#ibcon#read 5, iclass 21, count 0 2006.286.01:13:57.29#ibcon#about to read 6, iclass 21, count 0 2006.286.01:13:57.29#ibcon#read 6, iclass 21, count 0 2006.286.01:13:57.29#ibcon#end of sib2, iclass 21, count 0 2006.286.01:13:57.29#ibcon#*after write, iclass 21, count 0 2006.286.01:13:57.29#ibcon#*before return 0, iclass 21, count 0 2006.286.01:13:57.29#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:13:57.29#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:13:57.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.01:13:57.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.01:13:57.29$vck44/vblo=3,649.99 2006.286.01:13:57.29#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.01:13:57.29#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.01:13:57.29#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:57.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:13:57.29#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:13:57.29#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:13:57.29#ibcon#enter wrdev, iclass 23, count 0 2006.286.01:13:57.29#ibcon#first serial, iclass 23, count 0 2006.286.01:13:57.29#ibcon#enter sib2, iclass 23, count 0 2006.286.01:13:57.29#ibcon#flushed, iclass 23, count 0 2006.286.01:13:57.29#ibcon#about to write, iclass 23, count 0 2006.286.01:13:57.29#ibcon#wrote, iclass 23, count 0 2006.286.01:13:57.29#ibcon#about to read 3, iclass 23, count 0 2006.286.01:13:57.31#ibcon#read 3, iclass 23, count 0 2006.286.01:13:57.31#ibcon#about to read 4, iclass 23, count 0 2006.286.01:13:57.31#ibcon#read 4, iclass 23, count 0 2006.286.01:13:57.31#ibcon#about to read 5, iclass 23, count 0 2006.286.01:13:57.31#ibcon#read 5, iclass 23, count 0 2006.286.01:13:57.31#ibcon#about to read 6, iclass 23, count 0 2006.286.01:13:57.31#ibcon#read 6, iclass 23, count 0 2006.286.01:13:57.31#ibcon#end of sib2, iclass 23, count 0 2006.286.01:13:57.31#ibcon#*mode == 0, iclass 23, count 0 2006.286.01:13:57.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.01:13:57.31#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:13:57.31#ibcon#*before write, iclass 23, count 0 2006.286.01:13:57.31#ibcon#enter sib2, iclass 23, count 0 2006.286.01:13:57.31#ibcon#flushed, iclass 23, count 0 2006.286.01:13:57.31#ibcon#about to write, iclass 23, count 0 2006.286.01:13:57.31#ibcon#wrote, iclass 23, count 0 2006.286.01:13:57.31#ibcon#about to read 3, iclass 23, count 0 2006.286.01:13:57.35#ibcon#read 3, iclass 23, count 0 2006.286.01:13:57.35#ibcon#about to read 4, iclass 23, count 0 2006.286.01:13:57.35#ibcon#read 4, iclass 23, count 0 2006.286.01:13:57.35#ibcon#about to read 5, iclass 23, count 0 2006.286.01:13:57.35#ibcon#read 5, iclass 23, count 0 2006.286.01:13:57.35#ibcon#about to read 6, iclass 23, count 0 2006.286.01:13:57.35#ibcon#read 6, iclass 23, count 0 2006.286.01:13:57.35#ibcon#end of sib2, iclass 23, count 0 2006.286.01:13:57.35#ibcon#*after write, iclass 23, count 0 2006.286.01:13:57.35#ibcon#*before return 0, iclass 23, count 0 2006.286.01:13:57.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:13:57.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:13:57.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.01:13:57.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.01:13:57.35$vck44/vb=3,4 2006.286.01:13:57.35#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.01:13:57.35#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.01:13:57.35#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:57.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:13:57.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:13:57.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:13:57.41#ibcon#enter wrdev, iclass 25, count 2 2006.286.01:13:57.41#ibcon#first serial, iclass 25, count 2 2006.286.01:13:57.41#ibcon#enter sib2, iclass 25, count 2 2006.286.01:13:57.41#ibcon#flushed, iclass 25, count 2 2006.286.01:13:57.41#ibcon#about to write, iclass 25, count 2 2006.286.01:13:57.41#ibcon#wrote, iclass 25, count 2 2006.286.01:13:57.41#ibcon#about to read 3, iclass 25, count 2 2006.286.01:13:57.43#ibcon#read 3, iclass 25, count 2 2006.286.01:13:57.43#ibcon#about to read 4, iclass 25, count 2 2006.286.01:13:57.43#ibcon#read 4, iclass 25, count 2 2006.286.01:13:57.43#ibcon#about to read 5, iclass 25, count 2 2006.286.01:13:57.43#ibcon#read 5, iclass 25, count 2 2006.286.01:13:57.43#ibcon#about to read 6, iclass 25, count 2 2006.286.01:13:57.43#ibcon#read 6, iclass 25, count 2 2006.286.01:13:57.43#ibcon#end of sib2, iclass 25, count 2 2006.286.01:13:57.43#ibcon#*mode == 0, iclass 25, count 2 2006.286.01:13:57.43#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.01:13:57.43#ibcon#[27=AT03-04\r\n] 2006.286.01:13:57.43#ibcon#*before write, iclass 25, count 2 2006.286.01:13:57.43#ibcon#enter sib2, iclass 25, count 2 2006.286.01:13:57.43#ibcon#flushed, iclass 25, count 2 2006.286.01:13:57.43#ibcon#about to write, iclass 25, count 2 2006.286.01:13:57.43#ibcon#wrote, iclass 25, count 2 2006.286.01:13:57.43#ibcon#about to read 3, iclass 25, count 2 2006.286.01:13:57.46#ibcon#read 3, iclass 25, count 2 2006.286.01:13:57.46#ibcon#about to read 4, iclass 25, count 2 2006.286.01:13:57.46#ibcon#read 4, iclass 25, count 2 2006.286.01:13:57.46#ibcon#about to read 5, iclass 25, count 2 2006.286.01:13:57.46#ibcon#read 5, iclass 25, count 2 2006.286.01:13:57.46#ibcon#about to read 6, iclass 25, count 2 2006.286.01:13:57.46#ibcon#read 6, iclass 25, count 2 2006.286.01:13:57.46#ibcon#end of sib2, iclass 25, count 2 2006.286.01:13:57.46#ibcon#*after write, iclass 25, count 2 2006.286.01:13:57.46#ibcon#*before return 0, iclass 25, count 2 2006.286.01:13:57.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:13:57.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:13:57.46#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.01:13:57.46#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:57.46#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:13:57.58#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:13:57.58#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:13:57.58#ibcon#enter wrdev, iclass 25, count 0 2006.286.01:13:57.58#ibcon#first serial, iclass 25, count 0 2006.286.01:13:57.58#ibcon#enter sib2, iclass 25, count 0 2006.286.01:13:57.58#ibcon#flushed, iclass 25, count 0 2006.286.01:13:57.58#ibcon#about to write, iclass 25, count 0 2006.286.01:13:57.58#ibcon#wrote, iclass 25, count 0 2006.286.01:13:57.58#ibcon#about to read 3, iclass 25, count 0 2006.286.01:13:57.60#ibcon#read 3, iclass 25, count 0 2006.286.01:13:57.60#ibcon#about to read 4, iclass 25, count 0 2006.286.01:13:57.60#ibcon#read 4, iclass 25, count 0 2006.286.01:13:57.60#ibcon#about to read 5, iclass 25, count 0 2006.286.01:13:57.60#ibcon#read 5, iclass 25, count 0 2006.286.01:13:57.60#ibcon#about to read 6, iclass 25, count 0 2006.286.01:13:57.60#ibcon#read 6, iclass 25, count 0 2006.286.01:13:57.60#ibcon#end of sib2, iclass 25, count 0 2006.286.01:13:57.60#ibcon#*mode == 0, iclass 25, count 0 2006.286.01:13:57.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.01:13:57.60#ibcon#[27=USB\r\n] 2006.286.01:13:57.60#ibcon#*before write, iclass 25, count 0 2006.286.01:13:57.60#ibcon#enter sib2, iclass 25, count 0 2006.286.01:13:57.60#ibcon#flushed, iclass 25, count 0 2006.286.01:13:57.60#ibcon#about to write, iclass 25, count 0 2006.286.01:13:57.60#ibcon#wrote, iclass 25, count 0 2006.286.01:13:57.60#ibcon#about to read 3, iclass 25, count 0 2006.286.01:13:57.63#ibcon#read 3, iclass 25, count 0 2006.286.01:13:57.63#ibcon#about to read 4, iclass 25, count 0 2006.286.01:13:57.63#ibcon#read 4, iclass 25, count 0 2006.286.01:13:57.63#ibcon#about to read 5, iclass 25, count 0 2006.286.01:13:57.63#ibcon#read 5, iclass 25, count 0 2006.286.01:13:57.63#ibcon#about to read 6, iclass 25, count 0 2006.286.01:13:57.63#ibcon#read 6, iclass 25, count 0 2006.286.01:13:57.63#ibcon#end of sib2, iclass 25, count 0 2006.286.01:13:57.63#ibcon#*after write, iclass 25, count 0 2006.286.01:13:57.63#ibcon#*before return 0, iclass 25, count 0 2006.286.01:13:57.63#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:13:57.63#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:13:57.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.01:13:57.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.01:13:57.63$vck44/vblo=4,679.99 2006.286.01:13:57.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.01:13:57.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.01:13:57.63#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:57.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:13:57.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:13:57.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:13:57.63#ibcon#enter wrdev, iclass 27, count 0 2006.286.01:13:57.63#ibcon#first serial, iclass 27, count 0 2006.286.01:13:57.63#ibcon#enter sib2, iclass 27, count 0 2006.286.01:13:57.63#ibcon#flushed, iclass 27, count 0 2006.286.01:13:57.63#ibcon#about to write, iclass 27, count 0 2006.286.01:13:57.63#ibcon#wrote, iclass 27, count 0 2006.286.01:13:57.63#ibcon#about to read 3, iclass 27, count 0 2006.286.01:13:57.65#ibcon#read 3, iclass 27, count 0 2006.286.01:13:57.65#ibcon#about to read 4, iclass 27, count 0 2006.286.01:13:57.65#ibcon#read 4, iclass 27, count 0 2006.286.01:13:57.65#ibcon#about to read 5, iclass 27, count 0 2006.286.01:13:57.65#ibcon#read 5, iclass 27, count 0 2006.286.01:13:57.65#ibcon#about to read 6, iclass 27, count 0 2006.286.01:13:57.65#ibcon#read 6, iclass 27, count 0 2006.286.01:13:57.65#ibcon#end of sib2, iclass 27, count 0 2006.286.01:13:57.65#ibcon#*mode == 0, iclass 27, count 0 2006.286.01:13:57.65#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.01:13:57.65#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:13:57.65#ibcon#*before write, iclass 27, count 0 2006.286.01:13:57.65#ibcon#enter sib2, iclass 27, count 0 2006.286.01:13:57.65#ibcon#flushed, iclass 27, count 0 2006.286.01:13:57.65#ibcon#about to write, iclass 27, count 0 2006.286.01:13:57.65#ibcon#wrote, iclass 27, count 0 2006.286.01:13:57.65#ibcon#about to read 3, iclass 27, count 0 2006.286.01:13:57.69#ibcon#read 3, iclass 27, count 0 2006.286.01:13:57.69#ibcon#about to read 4, iclass 27, count 0 2006.286.01:13:57.69#ibcon#read 4, iclass 27, count 0 2006.286.01:13:57.69#ibcon#about to read 5, iclass 27, count 0 2006.286.01:13:57.69#ibcon#read 5, iclass 27, count 0 2006.286.01:13:57.69#ibcon#about to read 6, iclass 27, count 0 2006.286.01:13:57.69#ibcon#read 6, iclass 27, count 0 2006.286.01:13:57.69#ibcon#end of sib2, iclass 27, count 0 2006.286.01:13:57.69#ibcon#*after write, iclass 27, count 0 2006.286.01:13:57.69#ibcon#*before return 0, iclass 27, count 0 2006.286.01:13:57.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:13:57.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:13:57.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.01:13:57.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.01:13:57.69$vck44/vb=4,5 2006.286.01:13:57.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.01:13:57.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.01:13:57.69#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:57.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:13:57.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:13:57.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:13:57.75#ibcon#enter wrdev, iclass 29, count 2 2006.286.01:13:57.75#ibcon#first serial, iclass 29, count 2 2006.286.01:13:57.75#ibcon#enter sib2, iclass 29, count 2 2006.286.01:13:57.75#ibcon#flushed, iclass 29, count 2 2006.286.01:13:57.75#ibcon#about to write, iclass 29, count 2 2006.286.01:13:57.75#ibcon#wrote, iclass 29, count 2 2006.286.01:13:57.75#ibcon#about to read 3, iclass 29, count 2 2006.286.01:13:57.77#ibcon#read 3, iclass 29, count 2 2006.286.01:13:57.77#ibcon#about to read 4, iclass 29, count 2 2006.286.01:13:57.77#ibcon#read 4, iclass 29, count 2 2006.286.01:13:57.77#ibcon#about to read 5, iclass 29, count 2 2006.286.01:13:57.77#ibcon#read 5, iclass 29, count 2 2006.286.01:13:57.77#ibcon#about to read 6, iclass 29, count 2 2006.286.01:13:57.77#ibcon#read 6, iclass 29, count 2 2006.286.01:13:57.77#ibcon#end of sib2, iclass 29, count 2 2006.286.01:13:57.77#ibcon#*mode == 0, iclass 29, count 2 2006.286.01:13:57.77#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.01:13:57.77#ibcon#[27=AT04-05\r\n] 2006.286.01:13:57.77#ibcon#*before write, iclass 29, count 2 2006.286.01:13:57.77#ibcon#enter sib2, iclass 29, count 2 2006.286.01:13:57.77#ibcon#flushed, iclass 29, count 2 2006.286.01:13:57.77#ibcon#about to write, iclass 29, count 2 2006.286.01:13:57.77#ibcon#wrote, iclass 29, count 2 2006.286.01:13:57.77#ibcon#about to read 3, iclass 29, count 2 2006.286.01:13:57.80#ibcon#read 3, iclass 29, count 2 2006.286.01:13:57.80#ibcon#about to read 4, iclass 29, count 2 2006.286.01:13:57.80#ibcon#read 4, iclass 29, count 2 2006.286.01:13:57.80#ibcon#about to read 5, iclass 29, count 2 2006.286.01:13:57.80#ibcon#read 5, iclass 29, count 2 2006.286.01:13:57.80#ibcon#about to read 6, iclass 29, count 2 2006.286.01:13:57.80#ibcon#read 6, iclass 29, count 2 2006.286.01:13:57.80#ibcon#end of sib2, iclass 29, count 2 2006.286.01:13:57.80#ibcon#*after write, iclass 29, count 2 2006.286.01:13:57.80#ibcon#*before return 0, iclass 29, count 2 2006.286.01:13:57.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:13:57.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:13:57.80#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.01:13:57.80#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:57.80#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:13:57.92#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:13:57.92#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:13:57.92#ibcon#enter wrdev, iclass 29, count 0 2006.286.01:13:57.92#ibcon#first serial, iclass 29, count 0 2006.286.01:13:57.92#ibcon#enter sib2, iclass 29, count 0 2006.286.01:13:57.92#ibcon#flushed, iclass 29, count 0 2006.286.01:13:57.92#ibcon#about to write, iclass 29, count 0 2006.286.01:13:57.92#ibcon#wrote, iclass 29, count 0 2006.286.01:13:57.92#ibcon#about to read 3, iclass 29, count 0 2006.286.01:13:57.94#ibcon#read 3, iclass 29, count 0 2006.286.01:13:57.94#ibcon#about to read 4, iclass 29, count 0 2006.286.01:13:57.94#ibcon#read 4, iclass 29, count 0 2006.286.01:13:57.94#ibcon#about to read 5, iclass 29, count 0 2006.286.01:13:57.94#ibcon#read 5, iclass 29, count 0 2006.286.01:13:57.94#ibcon#about to read 6, iclass 29, count 0 2006.286.01:13:57.94#ibcon#read 6, iclass 29, count 0 2006.286.01:13:57.94#ibcon#end of sib2, iclass 29, count 0 2006.286.01:13:57.94#ibcon#*mode == 0, iclass 29, count 0 2006.286.01:13:57.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.01:13:57.94#ibcon#[27=USB\r\n] 2006.286.01:13:57.94#ibcon#*before write, iclass 29, count 0 2006.286.01:13:57.94#ibcon#enter sib2, iclass 29, count 0 2006.286.01:13:57.94#ibcon#flushed, iclass 29, count 0 2006.286.01:13:57.94#ibcon#about to write, iclass 29, count 0 2006.286.01:13:57.94#ibcon#wrote, iclass 29, count 0 2006.286.01:13:57.94#ibcon#about to read 3, iclass 29, count 0 2006.286.01:13:57.97#ibcon#read 3, iclass 29, count 0 2006.286.01:13:57.97#ibcon#about to read 4, iclass 29, count 0 2006.286.01:13:57.97#ibcon#read 4, iclass 29, count 0 2006.286.01:13:57.97#ibcon#about to read 5, iclass 29, count 0 2006.286.01:13:57.97#ibcon#read 5, iclass 29, count 0 2006.286.01:13:57.97#ibcon#about to read 6, iclass 29, count 0 2006.286.01:13:57.97#ibcon#read 6, iclass 29, count 0 2006.286.01:13:57.97#ibcon#end of sib2, iclass 29, count 0 2006.286.01:13:57.97#ibcon#*after write, iclass 29, count 0 2006.286.01:13:57.97#ibcon#*before return 0, iclass 29, count 0 2006.286.01:13:57.97#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:13:57.97#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:13:57.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.01:13:57.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.01:13:57.97$vck44/vblo=5,709.99 2006.286.01:13:57.97#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.01:13:57.97#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.01:13:57.97#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:57.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:13:57.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:13:57.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:13:57.97#ibcon#enter wrdev, iclass 31, count 0 2006.286.01:13:57.97#ibcon#first serial, iclass 31, count 0 2006.286.01:13:57.97#ibcon#enter sib2, iclass 31, count 0 2006.286.01:13:57.97#ibcon#flushed, iclass 31, count 0 2006.286.01:13:57.97#ibcon#about to write, iclass 31, count 0 2006.286.01:13:57.97#ibcon#wrote, iclass 31, count 0 2006.286.01:13:57.97#ibcon#about to read 3, iclass 31, count 0 2006.286.01:13:57.99#ibcon#read 3, iclass 31, count 0 2006.286.01:13:57.99#ibcon#about to read 4, iclass 31, count 0 2006.286.01:13:57.99#ibcon#read 4, iclass 31, count 0 2006.286.01:13:57.99#ibcon#about to read 5, iclass 31, count 0 2006.286.01:13:57.99#ibcon#read 5, iclass 31, count 0 2006.286.01:13:57.99#ibcon#about to read 6, iclass 31, count 0 2006.286.01:13:57.99#ibcon#read 6, iclass 31, count 0 2006.286.01:13:57.99#ibcon#end of sib2, iclass 31, count 0 2006.286.01:13:57.99#ibcon#*mode == 0, iclass 31, count 0 2006.286.01:13:57.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.01:13:57.99#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:13:57.99#ibcon#*before write, iclass 31, count 0 2006.286.01:13:57.99#ibcon#enter sib2, iclass 31, count 0 2006.286.01:13:57.99#ibcon#flushed, iclass 31, count 0 2006.286.01:13:57.99#ibcon#about to write, iclass 31, count 0 2006.286.01:13:57.99#ibcon#wrote, iclass 31, count 0 2006.286.01:13:57.99#ibcon#about to read 3, iclass 31, count 0 2006.286.01:13:58.03#ibcon#read 3, iclass 31, count 0 2006.286.01:13:58.03#ibcon#about to read 4, iclass 31, count 0 2006.286.01:13:58.03#ibcon#read 4, iclass 31, count 0 2006.286.01:13:58.03#ibcon#about to read 5, iclass 31, count 0 2006.286.01:13:58.03#ibcon#read 5, iclass 31, count 0 2006.286.01:13:58.03#ibcon#about to read 6, iclass 31, count 0 2006.286.01:13:58.03#ibcon#read 6, iclass 31, count 0 2006.286.01:13:58.03#ibcon#end of sib2, iclass 31, count 0 2006.286.01:13:58.03#ibcon#*after write, iclass 31, count 0 2006.286.01:13:58.03#ibcon#*before return 0, iclass 31, count 0 2006.286.01:13:58.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:13:58.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:13:58.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.01:13:58.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.01:13:58.03$vck44/vb=5,4 2006.286.01:13:58.03#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.01:13:58.03#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.01:13:58.03#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:58.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:13:58.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:13:58.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:13:58.09#ibcon#enter wrdev, iclass 33, count 2 2006.286.01:13:58.09#ibcon#first serial, iclass 33, count 2 2006.286.01:13:58.09#ibcon#enter sib2, iclass 33, count 2 2006.286.01:13:58.09#ibcon#flushed, iclass 33, count 2 2006.286.01:13:58.09#ibcon#about to write, iclass 33, count 2 2006.286.01:13:58.09#ibcon#wrote, iclass 33, count 2 2006.286.01:13:58.09#ibcon#about to read 3, iclass 33, count 2 2006.286.01:13:58.11#ibcon#read 3, iclass 33, count 2 2006.286.01:13:58.11#ibcon#about to read 4, iclass 33, count 2 2006.286.01:13:58.11#ibcon#read 4, iclass 33, count 2 2006.286.01:13:58.11#ibcon#about to read 5, iclass 33, count 2 2006.286.01:13:58.11#ibcon#read 5, iclass 33, count 2 2006.286.01:13:58.11#ibcon#about to read 6, iclass 33, count 2 2006.286.01:13:58.11#ibcon#read 6, iclass 33, count 2 2006.286.01:13:58.11#ibcon#end of sib2, iclass 33, count 2 2006.286.01:13:58.11#ibcon#*mode == 0, iclass 33, count 2 2006.286.01:13:58.11#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.01:13:58.11#ibcon#[27=AT05-04\r\n] 2006.286.01:13:58.11#ibcon#*before write, iclass 33, count 2 2006.286.01:13:58.11#ibcon#enter sib2, iclass 33, count 2 2006.286.01:13:58.11#ibcon#flushed, iclass 33, count 2 2006.286.01:13:58.11#ibcon#about to write, iclass 33, count 2 2006.286.01:13:58.11#ibcon#wrote, iclass 33, count 2 2006.286.01:13:58.11#ibcon#about to read 3, iclass 33, count 2 2006.286.01:13:58.14#ibcon#read 3, iclass 33, count 2 2006.286.01:13:58.14#ibcon#about to read 4, iclass 33, count 2 2006.286.01:13:58.14#ibcon#read 4, iclass 33, count 2 2006.286.01:13:58.14#ibcon#about to read 5, iclass 33, count 2 2006.286.01:13:58.14#ibcon#read 5, iclass 33, count 2 2006.286.01:13:58.14#ibcon#about to read 6, iclass 33, count 2 2006.286.01:13:58.14#ibcon#read 6, iclass 33, count 2 2006.286.01:13:58.14#ibcon#end of sib2, iclass 33, count 2 2006.286.01:13:58.14#ibcon#*after write, iclass 33, count 2 2006.286.01:13:58.14#ibcon#*before return 0, iclass 33, count 2 2006.286.01:13:58.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:13:58.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:13:58.14#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.01:13:58.14#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:58.14#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:13:58.23#abcon#<5=/03 3.3 6.7 20.99 831016.2\r\n> 2006.286.01:13:58.25#abcon#{5=INTERFACE CLEAR} 2006.286.01:13:58.26#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:13:58.26#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:13:58.26#ibcon#enter wrdev, iclass 33, count 0 2006.286.01:13:58.26#ibcon#first serial, iclass 33, count 0 2006.286.01:13:58.26#ibcon#enter sib2, iclass 33, count 0 2006.286.01:13:58.26#ibcon#flushed, iclass 33, count 0 2006.286.01:13:58.26#ibcon#about to write, iclass 33, count 0 2006.286.01:13:58.26#ibcon#wrote, iclass 33, count 0 2006.286.01:13:58.26#ibcon#about to read 3, iclass 33, count 0 2006.286.01:13:58.28#ibcon#read 3, iclass 33, count 0 2006.286.01:13:58.28#ibcon#about to read 4, iclass 33, count 0 2006.286.01:13:58.28#ibcon#read 4, iclass 33, count 0 2006.286.01:13:58.28#ibcon#about to read 5, iclass 33, count 0 2006.286.01:13:58.28#ibcon#read 5, iclass 33, count 0 2006.286.01:13:58.28#ibcon#about to read 6, iclass 33, count 0 2006.286.01:13:58.28#ibcon#read 6, iclass 33, count 0 2006.286.01:13:58.28#ibcon#end of sib2, iclass 33, count 0 2006.286.01:13:58.28#ibcon#*mode == 0, iclass 33, count 0 2006.286.01:13:58.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.01:13:58.28#ibcon#[27=USB\r\n] 2006.286.01:13:58.28#ibcon#*before write, iclass 33, count 0 2006.286.01:13:58.28#ibcon#enter sib2, iclass 33, count 0 2006.286.01:13:58.28#ibcon#flushed, iclass 33, count 0 2006.286.01:13:58.28#ibcon#about to write, iclass 33, count 0 2006.286.01:13:58.28#ibcon#wrote, iclass 33, count 0 2006.286.01:13:58.28#ibcon#about to read 3, iclass 33, count 0 2006.286.01:13:58.31#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:13:58.31#ibcon#read 3, iclass 33, count 0 2006.286.01:13:58.31#ibcon#about to read 4, iclass 33, count 0 2006.286.01:13:58.31#ibcon#read 4, iclass 33, count 0 2006.286.01:13:58.31#ibcon#about to read 5, iclass 33, count 0 2006.286.01:13:58.31#ibcon#read 5, iclass 33, count 0 2006.286.01:13:58.31#ibcon#about to read 6, iclass 33, count 0 2006.286.01:13:58.31#ibcon#read 6, iclass 33, count 0 2006.286.01:13:58.31#ibcon#end of sib2, iclass 33, count 0 2006.286.01:13:58.31#ibcon#*after write, iclass 33, count 0 2006.286.01:13:58.31#ibcon#*before return 0, iclass 33, count 0 2006.286.01:13:58.31#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:13:58.31#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:13:58.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.01:13:58.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.01:13:58.31$vck44/vblo=6,719.99 2006.286.01:13:58.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.01:13:58.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.01:13:58.31#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:58.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:13:58.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:13:58.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:13:58.31#ibcon#enter wrdev, iclass 39, count 0 2006.286.01:13:58.31#ibcon#first serial, iclass 39, count 0 2006.286.01:13:58.31#ibcon#enter sib2, iclass 39, count 0 2006.286.01:13:58.31#ibcon#flushed, iclass 39, count 0 2006.286.01:13:58.31#ibcon#about to write, iclass 39, count 0 2006.286.01:13:58.31#ibcon#wrote, iclass 39, count 0 2006.286.01:13:58.31#ibcon#about to read 3, iclass 39, count 0 2006.286.01:13:58.33#ibcon#read 3, iclass 39, count 0 2006.286.01:13:58.33#ibcon#about to read 4, iclass 39, count 0 2006.286.01:13:58.33#ibcon#read 4, iclass 39, count 0 2006.286.01:13:58.33#ibcon#about to read 5, iclass 39, count 0 2006.286.01:13:58.33#ibcon#read 5, iclass 39, count 0 2006.286.01:13:58.33#ibcon#about to read 6, iclass 39, count 0 2006.286.01:13:58.33#ibcon#read 6, iclass 39, count 0 2006.286.01:13:58.33#ibcon#end of sib2, iclass 39, count 0 2006.286.01:13:58.33#ibcon#*mode == 0, iclass 39, count 0 2006.286.01:13:58.33#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.01:13:58.33#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:13:58.33#ibcon#*before write, iclass 39, count 0 2006.286.01:13:58.33#ibcon#enter sib2, iclass 39, count 0 2006.286.01:13:58.33#ibcon#flushed, iclass 39, count 0 2006.286.01:13:58.33#ibcon#about to write, iclass 39, count 0 2006.286.01:13:58.33#ibcon#wrote, iclass 39, count 0 2006.286.01:13:58.33#ibcon#about to read 3, iclass 39, count 0 2006.286.01:13:58.37#ibcon#read 3, iclass 39, count 0 2006.286.01:13:58.37#ibcon#about to read 4, iclass 39, count 0 2006.286.01:13:58.37#ibcon#read 4, iclass 39, count 0 2006.286.01:13:58.37#ibcon#about to read 5, iclass 39, count 0 2006.286.01:13:58.37#ibcon#read 5, iclass 39, count 0 2006.286.01:13:58.37#ibcon#about to read 6, iclass 39, count 0 2006.286.01:13:58.37#ibcon#read 6, iclass 39, count 0 2006.286.01:13:58.37#ibcon#end of sib2, iclass 39, count 0 2006.286.01:13:58.37#ibcon#*after write, iclass 39, count 0 2006.286.01:13:58.37#ibcon#*before return 0, iclass 39, count 0 2006.286.01:13:58.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:13:58.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:13:58.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.01:13:58.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.01:13:58.37$vck44/vb=6,3 2006.286.01:13:58.37#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.01:13:58.37#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.01:13:58.37#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:58.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:13:58.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:13:58.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:13:58.43#ibcon#enter wrdev, iclass 3, count 2 2006.286.01:13:58.43#ibcon#first serial, iclass 3, count 2 2006.286.01:13:58.43#ibcon#enter sib2, iclass 3, count 2 2006.286.01:13:58.43#ibcon#flushed, iclass 3, count 2 2006.286.01:13:58.43#ibcon#about to write, iclass 3, count 2 2006.286.01:13:58.43#ibcon#wrote, iclass 3, count 2 2006.286.01:13:58.43#ibcon#about to read 3, iclass 3, count 2 2006.286.01:13:58.45#ibcon#read 3, iclass 3, count 2 2006.286.01:13:58.45#ibcon#about to read 4, iclass 3, count 2 2006.286.01:13:58.45#ibcon#read 4, iclass 3, count 2 2006.286.01:13:58.45#ibcon#about to read 5, iclass 3, count 2 2006.286.01:13:58.45#ibcon#read 5, iclass 3, count 2 2006.286.01:13:58.45#ibcon#about to read 6, iclass 3, count 2 2006.286.01:13:58.45#ibcon#read 6, iclass 3, count 2 2006.286.01:13:58.45#ibcon#end of sib2, iclass 3, count 2 2006.286.01:13:58.45#ibcon#*mode == 0, iclass 3, count 2 2006.286.01:13:58.45#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.01:13:58.45#ibcon#[27=AT06-03\r\n] 2006.286.01:13:58.45#ibcon#*before write, iclass 3, count 2 2006.286.01:13:58.45#ibcon#enter sib2, iclass 3, count 2 2006.286.01:13:58.45#ibcon#flushed, iclass 3, count 2 2006.286.01:13:58.45#ibcon#about to write, iclass 3, count 2 2006.286.01:13:58.45#ibcon#wrote, iclass 3, count 2 2006.286.01:13:58.45#ibcon#about to read 3, iclass 3, count 2 2006.286.01:13:58.48#ibcon#read 3, iclass 3, count 2 2006.286.01:13:58.48#ibcon#about to read 4, iclass 3, count 2 2006.286.01:13:58.48#ibcon#read 4, iclass 3, count 2 2006.286.01:13:58.48#ibcon#about to read 5, iclass 3, count 2 2006.286.01:13:58.48#ibcon#read 5, iclass 3, count 2 2006.286.01:13:58.48#ibcon#about to read 6, iclass 3, count 2 2006.286.01:13:58.48#ibcon#read 6, iclass 3, count 2 2006.286.01:13:58.48#ibcon#end of sib2, iclass 3, count 2 2006.286.01:13:58.48#ibcon#*after write, iclass 3, count 2 2006.286.01:13:58.48#ibcon#*before return 0, iclass 3, count 2 2006.286.01:13:58.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:13:58.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:13:58.48#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.01:13:58.48#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:58.48#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:13:58.60#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:13:58.60#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:13:58.60#ibcon#enter wrdev, iclass 3, count 0 2006.286.01:13:58.60#ibcon#first serial, iclass 3, count 0 2006.286.01:13:58.60#ibcon#enter sib2, iclass 3, count 0 2006.286.01:13:58.60#ibcon#flushed, iclass 3, count 0 2006.286.01:13:58.60#ibcon#about to write, iclass 3, count 0 2006.286.01:13:58.60#ibcon#wrote, iclass 3, count 0 2006.286.01:13:58.60#ibcon#about to read 3, iclass 3, count 0 2006.286.01:13:58.62#ibcon#read 3, iclass 3, count 0 2006.286.01:13:58.62#ibcon#about to read 4, iclass 3, count 0 2006.286.01:13:58.62#ibcon#read 4, iclass 3, count 0 2006.286.01:13:58.62#ibcon#about to read 5, iclass 3, count 0 2006.286.01:13:58.62#ibcon#read 5, iclass 3, count 0 2006.286.01:13:58.62#ibcon#about to read 6, iclass 3, count 0 2006.286.01:13:58.62#ibcon#read 6, iclass 3, count 0 2006.286.01:13:58.62#ibcon#end of sib2, iclass 3, count 0 2006.286.01:13:58.62#ibcon#*mode == 0, iclass 3, count 0 2006.286.01:13:58.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.01:13:58.62#ibcon#[27=USB\r\n] 2006.286.01:13:58.62#ibcon#*before write, iclass 3, count 0 2006.286.01:13:58.62#ibcon#enter sib2, iclass 3, count 0 2006.286.01:13:58.62#ibcon#flushed, iclass 3, count 0 2006.286.01:13:58.62#ibcon#about to write, iclass 3, count 0 2006.286.01:13:58.62#ibcon#wrote, iclass 3, count 0 2006.286.01:13:58.62#ibcon#about to read 3, iclass 3, count 0 2006.286.01:13:58.65#ibcon#read 3, iclass 3, count 0 2006.286.01:13:58.65#ibcon#about to read 4, iclass 3, count 0 2006.286.01:13:58.65#ibcon#read 4, iclass 3, count 0 2006.286.01:13:58.65#ibcon#about to read 5, iclass 3, count 0 2006.286.01:13:58.65#ibcon#read 5, iclass 3, count 0 2006.286.01:13:58.65#ibcon#about to read 6, iclass 3, count 0 2006.286.01:13:58.65#ibcon#read 6, iclass 3, count 0 2006.286.01:13:58.65#ibcon#end of sib2, iclass 3, count 0 2006.286.01:13:58.65#ibcon#*after write, iclass 3, count 0 2006.286.01:13:58.65#ibcon#*before return 0, iclass 3, count 0 2006.286.01:13:58.65#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:13:58.65#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:13:58.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.01:13:58.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.01:13:58.65$vck44/vblo=7,734.99 2006.286.01:13:58.65#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.01:13:58.65#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.01:13:58.65#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:58.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:13:58.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:13:58.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:13:58.65#ibcon#enter wrdev, iclass 5, count 0 2006.286.01:13:58.65#ibcon#first serial, iclass 5, count 0 2006.286.01:13:58.65#ibcon#enter sib2, iclass 5, count 0 2006.286.01:13:58.65#ibcon#flushed, iclass 5, count 0 2006.286.01:13:58.65#ibcon#about to write, iclass 5, count 0 2006.286.01:13:58.65#ibcon#wrote, iclass 5, count 0 2006.286.01:13:58.65#ibcon#about to read 3, iclass 5, count 0 2006.286.01:13:58.67#ibcon#read 3, iclass 5, count 0 2006.286.01:13:58.67#ibcon#about to read 4, iclass 5, count 0 2006.286.01:13:58.67#ibcon#read 4, iclass 5, count 0 2006.286.01:13:58.67#ibcon#about to read 5, iclass 5, count 0 2006.286.01:13:58.67#ibcon#read 5, iclass 5, count 0 2006.286.01:13:58.67#ibcon#about to read 6, iclass 5, count 0 2006.286.01:13:58.67#ibcon#read 6, iclass 5, count 0 2006.286.01:13:58.67#ibcon#end of sib2, iclass 5, count 0 2006.286.01:13:58.67#ibcon#*mode == 0, iclass 5, count 0 2006.286.01:13:58.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.01:13:58.67#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:13:58.67#ibcon#*before write, iclass 5, count 0 2006.286.01:13:58.67#ibcon#enter sib2, iclass 5, count 0 2006.286.01:13:58.67#ibcon#flushed, iclass 5, count 0 2006.286.01:13:58.67#ibcon#about to write, iclass 5, count 0 2006.286.01:13:58.67#ibcon#wrote, iclass 5, count 0 2006.286.01:13:58.67#ibcon#about to read 3, iclass 5, count 0 2006.286.01:13:58.71#ibcon#read 3, iclass 5, count 0 2006.286.01:13:58.71#ibcon#about to read 4, iclass 5, count 0 2006.286.01:13:58.71#ibcon#read 4, iclass 5, count 0 2006.286.01:13:58.71#ibcon#about to read 5, iclass 5, count 0 2006.286.01:13:58.71#ibcon#read 5, iclass 5, count 0 2006.286.01:13:58.71#ibcon#about to read 6, iclass 5, count 0 2006.286.01:13:58.71#ibcon#read 6, iclass 5, count 0 2006.286.01:13:58.71#ibcon#end of sib2, iclass 5, count 0 2006.286.01:13:58.71#ibcon#*after write, iclass 5, count 0 2006.286.01:13:58.71#ibcon#*before return 0, iclass 5, count 0 2006.286.01:13:58.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:13:58.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:13:58.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.01:13:58.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.01:13:58.71$vck44/vb=7,4 2006.286.01:13:58.71#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.01:13:58.71#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.01:13:58.71#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:58.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:13:58.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:13:58.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:13:58.77#ibcon#enter wrdev, iclass 7, count 2 2006.286.01:13:58.77#ibcon#first serial, iclass 7, count 2 2006.286.01:13:58.77#ibcon#enter sib2, iclass 7, count 2 2006.286.01:13:58.77#ibcon#flushed, iclass 7, count 2 2006.286.01:13:58.77#ibcon#about to write, iclass 7, count 2 2006.286.01:13:58.77#ibcon#wrote, iclass 7, count 2 2006.286.01:13:58.77#ibcon#about to read 3, iclass 7, count 2 2006.286.01:13:58.79#ibcon#read 3, iclass 7, count 2 2006.286.01:13:58.79#ibcon#about to read 4, iclass 7, count 2 2006.286.01:13:58.79#ibcon#read 4, iclass 7, count 2 2006.286.01:13:58.79#ibcon#about to read 5, iclass 7, count 2 2006.286.01:13:58.79#ibcon#read 5, iclass 7, count 2 2006.286.01:13:58.79#ibcon#about to read 6, iclass 7, count 2 2006.286.01:13:58.79#ibcon#read 6, iclass 7, count 2 2006.286.01:13:58.79#ibcon#end of sib2, iclass 7, count 2 2006.286.01:13:58.79#ibcon#*mode == 0, iclass 7, count 2 2006.286.01:13:58.79#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.01:13:58.79#ibcon#[27=AT07-04\r\n] 2006.286.01:13:58.79#ibcon#*before write, iclass 7, count 2 2006.286.01:13:58.79#ibcon#enter sib2, iclass 7, count 2 2006.286.01:13:58.79#ibcon#flushed, iclass 7, count 2 2006.286.01:13:58.79#ibcon#about to write, iclass 7, count 2 2006.286.01:13:58.79#ibcon#wrote, iclass 7, count 2 2006.286.01:13:58.79#ibcon#about to read 3, iclass 7, count 2 2006.286.01:13:58.82#ibcon#read 3, iclass 7, count 2 2006.286.01:13:58.82#ibcon#about to read 4, iclass 7, count 2 2006.286.01:13:58.82#ibcon#read 4, iclass 7, count 2 2006.286.01:13:58.82#ibcon#about to read 5, iclass 7, count 2 2006.286.01:13:58.82#ibcon#read 5, iclass 7, count 2 2006.286.01:13:58.82#ibcon#about to read 6, iclass 7, count 2 2006.286.01:13:58.82#ibcon#read 6, iclass 7, count 2 2006.286.01:13:58.82#ibcon#end of sib2, iclass 7, count 2 2006.286.01:13:58.82#ibcon#*after write, iclass 7, count 2 2006.286.01:13:58.82#ibcon#*before return 0, iclass 7, count 2 2006.286.01:13:58.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:13:58.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:13:58.82#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.01:13:58.82#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:58.82#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:13:58.94#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:13:58.94#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:13:58.94#ibcon#enter wrdev, iclass 7, count 0 2006.286.01:13:58.94#ibcon#first serial, iclass 7, count 0 2006.286.01:13:58.94#ibcon#enter sib2, iclass 7, count 0 2006.286.01:13:58.94#ibcon#flushed, iclass 7, count 0 2006.286.01:13:58.94#ibcon#about to write, iclass 7, count 0 2006.286.01:13:58.94#ibcon#wrote, iclass 7, count 0 2006.286.01:13:58.94#ibcon#about to read 3, iclass 7, count 0 2006.286.01:13:58.96#ibcon#read 3, iclass 7, count 0 2006.286.01:13:58.96#ibcon#about to read 4, iclass 7, count 0 2006.286.01:13:58.96#ibcon#read 4, iclass 7, count 0 2006.286.01:13:58.96#ibcon#about to read 5, iclass 7, count 0 2006.286.01:13:58.96#ibcon#read 5, iclass 7, count 0 2006.286.01:13:58.96#ibcon#about to read 6, iclass 7, count 0 2006.286.01:13:58.96#ibcon#read 6, iclass 7, count 0 2006.286.01:13:58.96#ibcon#end of sib2, iclass 7, count 0 2006.286.01:13:58.96#ibcon#*mode == 0, iclass 7, count 0 2006.286.01:13:58.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.01:13:58.96#ibcon#[27=USB\r\n] 2006.286.01:13:58.96#ibcon#*before write, iclass 7, count 0 2006.286.01:13:58.96#ibcon#enter sib2, iclass 7, count 0 2006.286.01:13:58.96#ibcon#flushed, iclass 7, count 0 2006.286.01:13:58.96#ibcon#about to write, iclass 7, count 0 2006.286.01:13:58.96#ibcon#wrote, iclass 7, count 0 2006.286.01:13:58.96#ibcon#about to read 3, iclass 7, count 0 2006.286.01:13:58.99#ibcon#read 3, iclass 7, count 0 2006.286.01:13:58.99#ibcon#about to read 4, iclass 7, count 0 2006.286.01:13:58.99#ibcon#read 4, iclass 7, count 0 2006.286.01:13:58.99#ibcon#about to read 5, iclass 7, count 0 2006.286.01:13:58.99#ibcon#read 5, iclass 7, count 0 2006.286.01:13:58.99#ibcon#about to read 6, iclass 7, count 0 2006.286.01:13:58.99#ibcon#read 6, iclass 7, count 0 2006.286.01:13:58.99#ibcon#end of sib2, iclass 7, count 0 2006.286.01:13:58.99#ibcon#*after write, iclass 7, count 0 2006.286.01:13:58.99#ibcon#*before return 0, iclass 7, count 0 2006.286.01:13:58.99#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:13:58.99#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:13:58.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.01:13:58.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.01:13:58.99$vck44/vblo=8,744.99 2006.286.01:13:58.99#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.01:13:58.99#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.01:13:58.99#ibcon#ireg 17 cls_cnt 0 2006.286.01:13:58.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:13:58.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:13:58.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:13:58.99#ibcon#enter wrdev, iclass 11, count 0 2006.286.01:13:58.99#ibcon#first serial, iclass 11, count 0 2006.286.01:13:58.99#ibcon#enter sib2, iclass 11, count 0 2006.286.01:13:58.99#ibcon#flushed, iclass 11, count 0 2006.286.01:13:58.99#ibcon#about to write, iclass 11, count 0 2006.286.01:13:58.99#ibcon#wrote, iclass 11, count 0 2006.286.01:13:58.99#ibcon#about to read 3, iclass 11, count 0 2006.286.01:13:59.01#ibcon#read 3, iclass 11, count 0 2006.286.01:13:59.01#ibcon#about to read 4, iclass 11, count 0 2006.286.01:13:59.01#ibcon#read 4, iclass 11, count 0 2006.286.01:13:59.01#ibcon#about to read 5, iclass 11, count 0 2006.286.01:13:59.01#ibcon#read 5, iclass 11, count 0 2006.286.01:13:59.01#ibcon#about to read 6, iclass 11, count 0 2006.286.01:13:59.01#ibcon#read 6, iclass 11, count 0 2006.286.01:13:59.01#ibcon#end of sib2, iclass 11, count 0 2006.286.01:13:59.01#ibcon#*mode == 0, iclass 11, count 0 2006.286.01:13:59.01#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.01:13:59.01#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:13:59.01#ibcon#*before write, iclass 11, count 0 2006.286.01:13:59.01#ibcon#enter sib2, iclass 11, count 0 2006.286.01:13:59.01#ibcon#flushed, iclass 11, count 0 2006.286.01:13:59.01#ibcon#about to write, iclass 11, count 0 2006.286.01:13:59.01#ibcon#wrote, iclass 11, count 0 2006.286.01:13:59.01#ibcon#about to read 3, iclass 11, count 0 2006.286.01:13:59.05#ibcon#read 3, iclass 11, count 0 2006.286.01:13:59.05#ibcon#about to read 4, iclass 11, count 0 2006.286.01:13:59.05#ibcon#read 4, iclass 11, count 0 2006.286.01:13:59.05#ibcon#about to read 5, iclass 11, count 0 2006.286.01:13:59.05#ibcon#read 5, iclass 11, count 0 2006.286.01:13:59.05#ibcon#about to read 6, iclass 11, count 0 2006.286.01:13:59.05#ibcon#read 6, iclass 11, count 0 2006.286.01:13:59.05#ibcon#end of sib2, iclass 11, count 0 2006.286.01:13:59.05#ibcon#*after write, iclass 11, count 0 2006.286.01:13:59.05#ibcon#*before return 0, iclass 11, count 0 2006.286.01:13:59.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:13:59.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:13:59.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.01:13:59.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.01:13:59.05$vck44/vb=8,4 2006.286.01:13:59.05#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.01:13:59.05#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.01:13:59.05#ibcon#ireg 11 cls_cnt 2 2006.286.01:13:59.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:13:59.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:13:59.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:13:59.11#ibcon#enter wrdev, iclass 13, count 2 2006.286.01:13:59.11#ibcon#first serial, iclass 13, count 2 2006.286.01:13:59.11#ibcon#enter sib2, iclass 13, count 2 2006.286.01:13:59.11#ibcon#flushed, iclass 13, count 2 2006.286.01:13:59.11#ibcon#about to write, iclass 13, count 2 2006.286.01:13:59.11#ibcon#wrote, iclass 13, count 2 2006.286.01:13:59.11#ibcon#about to read 3, iclass 13, count 2 2006.286.01:13:59.13#ibcon#read 3, iclass 13, count 2 2006.286.01:13:59.13#ibcon#about to read 4, iclass 13, count 2 2006.286.01:13:59.13#ibcon#read 4, iclass 13, count 2 2006.286.01:13:59.13#ibcon#about to read 5, iclass 13, count 2 2006.286.01:13:59.13#ibcon#read 5, iclass 13, count 2 2006.286.01:13:59.13#ibcon#about to read 6, iclass 13, count 2 2006.286.01:13:59.13#ibcon#read 6, iclass 13, count 2 2006.286.01:13:59.13#ibcon#end of sib2, iclass 13, count 2 2006.286.01:13:59.13#ibcon#*mode == 0, iclass 13, count 2 2006.286.01:13:59.13#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.01:13:59.13#ibcon#[27=AT08-04\r\n] 2006.286.01:13:59.13#ibcon#*before write, iclass 13, count 2 2006.286.01:13:59.13#ibcon#enter sib2, iclass 13, count 2 2006.286.01:13:59.13#ibcon#flushed, iclass 13, count 2 2006.286.01:13:59.13#ibcon#about to write, iclass 13, count 2 2006.286.01:13:59.13#ibcon#wrote, iclass 13, count 2 2006.286.01:13:59.13#ibcon#about to read 3, iclass 13, count 2 2006.286.01:13:59.16#ibcon#read 3, iclass 13, count 2 2006.286.01:13:59.16#ibcon#about to read 4, iclass 13, count 2 2006.286.01:13:59.16#ibcon#read 4, iclass 13, count 2 2006.286.01:13:59.16#ibcon#about to read 5, iclass 13, count 2 2006.286.01:13:59.16#ibcon#read 5, iclass 13, count 2 2006.286.01:13:59.16#ibcon#about to read 6, iclass 13, count 2 2006.286.01:13:59.16#ibcon#read 6, iclass 13, count 2 2006.286.01:13:59.16#ibcon#end of sib2, iclass 13, count 2 2006.286.01:13:59.16#ibcon#*after write, iclass 13, count 2 2006.286.01:13:59.16#ibcon#*before return 0, iclass 13, count 2 2006.286.01:13:59.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:13:59.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:13:59.16#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.01:13:59.16#ibcon#ireg 7 cls_cnt 0 2006.286.01:13:59.16#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:13:59.28#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:13:59.28#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:13:59.28#ibcon#enter wrdev, iclass 13, count 0 2006.286.01:13:59.28#ibcon#first serial, iclass 13, count 0 2006.286.01:13:59.28#ibcon#enter sib2, iclass 13, count 0 2006.286.01:13:59.28#ibcon#flushed, iclass 13, count 0 2006.286.01:13:59.28#ibcon#about to write, iclass 13, count 0 2006.286.01:13:59.28#ibcon#wrote, iclass 13, count 0 2006.286.01:13:59.28#ibcon#about to read 3, iclass 13, count 0 2006.286.01:13:59.30#ibcon#read 3, iclass 13, count 0 2006.286.01:13:59.30#ibcon#about to read 4, iclass 13, count 0 2006.286.01:13:59.30#ibcon#read 4, iclass 13, count 0 2006.286.01:13:59.30#ibcon#about to read 5, iclass 13, count 0 2006.286.01:13:59.30#ibcon#read 5, iclass 13, count 0 2006.286.01:13:59.30#ibcon#about to read 6, iclass 13, count 0 2006.286.01:13:59.30#ibcon#read 6, iclass 13, count 0 2006.286.01:13:59.30#ibcon#end of sib2, iclass 13, count 0 2006.286.01:13:59.30#ibcon#*mode == 0, iclass 13, count 0 2006.286.01:13:59.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.01:13:59.30#ibcon#[27=USB\r\n] 2006.286.01:13:59.30#ibcon#*before write, iclass 13, count 0 2006.286.01:13:59.30#ibcon#enter sib2, iclass 13, count 0 2006.286.01:13:59.30#ibcon#flushed, iclass 13, count 0 2006.286.01:13:59.30#ibcon#about to write, iclass 13, count 0 2006.286.01:13:59.30#ibcon#wrote, iclass 13, count 0 2006.286.01:13:59.30#ibcon#about to read 3, iclass 13, count 0 2006.286.01:13:59.33#ibcon#read 3, iclass 13, count 0 2006.286.01:13:59.33#ibcon#about to read 4, iclass 13, count 0 2006.286.01:13:59.33#ibcon#read 4, iclass 13, count 0 2006.286.01:13:59.33#ibcon#about to read 5, iclass 13, count 0 2006.286.01:13:59.33#ibcon#read 5, iclass 13, count 0 2006.286.01:13:59.33#ibcon#about to read 6, iclass 13, count 0 2006.286.01:13:59.33#ibcon#read 6, iclass 13, count 0 2006.286.01:13:59.33#ibcon#end of sib2, iclass 13, count 0 2006.286.01:13:59.33#ibcon#*after write, iclass 13, count 0 2006.286.01:13:59.33#ibcon#*before return 0, iclass 13, count 0 2006.286.01:13:59.33#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:13:59.33#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:13:59.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.01:13:59.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.01:13:59.33$vck44/vabw=wide 2006.286.01:13:59.33#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.01:13:59.33#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.01:13:59.33#ibcon#ireg 8 cls_cnt 0 2006.286.01:13:59.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:13:59.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:13:59.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:13:59.33#ibcon#enter wrdev, iclass 15, count 0 2006.286.01:13:59.33#ibcon#first serial, iclass 15, count 0 2006.286.01:13:59.33#ibcon#enter sib2, iclass 15, count 0 2006.286.01:13:59.33#ibcon#flushed, iclass 15, count 0 2006.286.01:13:59.33#ibcon#about to write, iclass 15, count 0 2006.286.01:13:59.33#ibcon#wrote, iclass 15, count 0 2006.286.01:13:59.33#ibcon#about to read 3, iclass 15, count 0 2006.286.01:13:59.35#ibcon#read 3, iclass 15, count 0 2006.286.01:13:59.35#ibcon#about to read 4, iclass 15, count 0 2006.286.01:13:59.35#ibcon#read 4, iclass 15, count 0 2006.286.01:13:59.35#ibcon#about to read 5, iclass 15, count 0 2006.286.01:13:59.35#ibcon#read 5, iclass 15, count 0 2006.286.01:13:59.35#ibcon#about to read 6, iclass 15, count 0 2006.286.01:13:59.35#ibcon#read 6, iclass 15, count 0 2006.286.01:13:59.35#ibcon#end of sib2, iclass 15, count 0 2006.286.01:13:59.35#ibcon#*mode == 0, iclass 15, count 0 2006.286.01:13:59.35#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.01:13:59.35#ibcon#[25=BW32\r\n] 2006.286.01:13:59.35#ibcon#*before write, iclass 15, count 0 2006.286.01:13:59.35#ibcon#enter sib2, iclass 15, count 0 2006.286.01:13:59.35#ibcon#flushed, iclass 15, count 0 2006.286.01:13:59.35#ibcon#about to write, iclass 15, count 0 2006.286.01:13:59.35#ibcon#wrote, iclass 15, count 0 2006.286.01:13:59.35#ibcon#about to read 3, iclass 15, count 0 2006.286.01:13:59.38#ibcon#read 3, iclass 15, count 0 2006.286.01:13:59.38#ibcon#about to read 4, iclass 15, count 0 2006.286.01:13:59.38#ibcon#read 4, iclass 15, count 0 2006.286.01:13:59.38#ibcon#about to read 5, iclass 15, count 0 2006.286.01:13:59.38#ibcon#read 5, iclass 15, count 0 2006.286.01:13:59.38#ibcon#about to read 6, iclass 15, count 0 2006.286.01:13:59.38#ibcon#read 6, iclass 15, count 0 2006.286.01:13:59.38#ibcon#end of sib2, iclass 15, count 0 2006.286.01:13:59.38#ibcon#*after write, iclass 15, count 0 2006.286.01:13:59.38#ibcon#*before return 0, iclass 15, count 0 2006.286.01:13:59.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:13:59.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:13:59.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.01:13:59.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.01:13:59.38$vck44/vbbw=wide 2006.286.01:13:59.38#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.01:13:59.38#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.01:13:59.38#ibcon#ireg 8 cls_cnt 0 2006.286.01:13:59.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:13:59.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:13:59.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:13:59.45#ibcon#enter wrdev, iclass 17, count 0 2006.286.01:13:59.45#ibcon#first serial, iclass 17, count 0 2006.286.01:13:59.45#ibcon#enter sib2, iclass 17, count 0 2006.286.01:13:59.45#ibcon#flushed, iclass 17, count 0 2006.286.01:13:59.45#ibcon#about to write, iclass 17, count 0 2006.286.01:13:59.45#ibcon#wrote, iclass 17, count 0 2006.286.01:13:59.45#ibcon#about to read 3, iclass 17, count 0 2006.286.01:13:59.47#ibcon#read 3, iclass 17, count 0 2006.286.01:13:59.47#ibcon#about to read 4, iclass 17, count 0 2006.286.01:13:59.47#ibcon#read 4, iclass 17, count 0 2006.286.01:13:59.47#ibcon#about to read 5, iclass 17, count 0 2006.286.01:13:59.47#ibcon#read 5, iclass 17, count 0 2006.286.01:13:59.47#ibcon#about to read 6, iclass 17, count 0 2006.286.01:13:59.47#ibcon#read 6, iclass 17, count 0 2006.286.01:13:59.47#ibcon#end of sib2, iclass 17, count 0 2006.286.01:13:59.47#ibcon#*mode == 0, iclass 17, count 0 2006.286.01:13:59.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.01:13:59.47#ibcon#[27=BW32\r\n] 2006.286.01:13:59.47#ibcon#*before write, iclass 17, count 0 2006.286.01:13:59.47#ibcon#enter sib2, iclass 17, count 0 2006.286.01:13:59.47#ibcon#flushed, iclass 17, count 0 2006.286.01:13:59.47#ibcon#about to write, iclass 17, count 0 2006.286.01:13:59.47#ibcon#wrote, iclass 17, count 0 2006.286.01:13:59.47#ibcon#about to read 3, iclass 17, count 0 2006.286.01:13:59.50#ibcon#read 3, iclass 17, count 0 2006.286.01:13:59.50#ibcon#about to read 4, iclass 17, count 0 2006.286.01:13:59.50#ibcon#read 4, iclass 17, count 0 2006.286.01:13:59.50#ibcon#about to read 5, iclass 17, count 0 2006.286.01:13:59.50#ibcon#read 5, iclass 17, count 0 2006.286.01:13:59.50#ibcon#about to read 6, iclass 17, count 0 2006.286.01:13:59.50#ibcon#read 6, iclass 17, count 0 2006.286.01:13:59.50#ibcon#end of sib2, iclass 17, count 0 2006.286.01:13:59.50#ibcon#*after write, iclass 17, count 0 2006.286.01:13:59.50#ibcon#*before return 0, iclass 17, count 0 2006.286.01:13:59.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:13:59.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:13:59.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.01:13:59.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.01:13:59.50$setupk4/ifdk4 2006.286.01:13:59.50$ifdk4/lo= 2006.286.01:13:59.50$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:13:59.50$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:13:59.50$ifdk4/patch= 2006.286.01:13:59.50$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:13:59.50$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:13:59.50$setupk4/!*+20s 2006.286.01:14:08.40#abcon#<5=/03 3.3 6.7 20.99 841016.2\r\n> 2006.286.01:14:08.42#abcon#{5=INTERFACE CLEAR} 2006.286.01:14:08.48#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:14:14.01$setupk4/"tpicd 2006.286.01:14:14.01$setupk4/echo=off 2006.286.01:14:14.01$setupk4/xlog=off 2006.286.01:14:14.01:!2006.286.01:16:59 2006.286.01:14:14.14#trakl#Source acquired 2006.286.01:14:16.14#flagr#flagr/antenna,acquired 2006.286.01:16:59.00:preob 2006.286.01:16:59.13/onsource/TRACKING 2006.286.01:16:59.13:!2006.286.01:17:09 2006.286.01:17:09.00:"tape 2006.286.01:17:09.00:"st=record 2006.286.01:17:09.00:data_valid=on 2006.286.01:17:09.00:midob 2006.286.01:17:10.14/onsource/TRACKING 2006.286.01:17:10.14/wx/21.04,1016.2,84 2006.286.01:17:10.30/cable/+6.5061E-03 2006.286.01:17:11.39/va/01,07,usb,yes,37,40 2006.286.01:17:11.39/va/02,06,usb,yes,38,38 2006.286.01:17:11.39/va/03,07,usb,yes,37,39 2006.286.01:17:11.39/va/04,06,usb,yes,39,41 2006.286.01:17:11.39/va/05,03,usb,yes,38,39 2006.286.01:17:11.39/va/06,04,usb,yes,35,34 2006.286.01:17:11.39/va/07,04,usb,yes,35,36 2006.286.01:17:11.39/va/08,03,usb,yes,36,43 2006.286.01:17:11.62/valo/01,524.99,yes,locked 2006.286.01:17:11.62/valo/02,534.99,yes,locked 2006.286.01:17:11.62/valo/03,564.99,yes,locked 2006.286.01:17:11.62/valo/04,624.99,yes,locked 2006.286.01:17:11.62/valo/05,734.99,yes,locked 2006.286.01:17:11.62/valo/06,814.99,yes,locked 2006.286.01:17:11.62/valo/07,864.99,yes,locked 2006.286.01:17:11.62/valo/08,884.99,yes,locked 2006.286.01:17:12.71/vb/01,04,usb,yes,34,31 2006.286.01:17:12.71/vb/02,05,usb,yes,32,32 2006.286.01:17:12.71/vb/03,04,usb,yes,33,36 2006.286.01:17:12.71/vb/04,05,usb,yes,33,32 2006.286.01:17:12.71/vb/05,04,usb,yes,29,32 2006.286.01:17:12.71/vb/06,03,usb,yes,42,37 2006.286.01:17:12.71/vb/07,04,usb,yes,34,34 2006.286.01:17:12.71/vb/08,04,usb,yes,31,35 2006.286.01:17:12.94/vblo/01,629.99,yes,locked 2006.286.01:17:12.94/vblo/02,634.99,yes,locked 2006.286.01:17:12.94/vblo/03,649.99,yes,locked 2006.286.01:17:12.94/vblo/04,679.99,yes,locked 2006.286.01:17:12.94/vblo/05,709.99,yes,locked 2006.286.01:17:12.94/vblo/06,719.99,yes,locked 2006.286.01:17:12.94/vblo/07,734.99,yes,locked 2006.286.01:17:12.94/vblo/08,744.99,yes,locked 2006.286.01:17:13.09/vabw/8 2006.286.01:17:13.24/vbbw/8 2006.286.01:17:13.33/xfe/off,on,12.0 2006.286.01:17:13.70/ifatt/23,28,28,28 2006.286.01:17:14.08/fmout-gps/S +2.72E-07 2006.286.01:17:14.10:!2006.286.01:17:49 2006.286.01:17:49.00:data_valid=off 2006.286.01:17:49.00:"et 2006.286.01:17:49.00:!+3s 2006.286.01:17:52.01:"tape 2006.286.01:17:52.01:postob 2006.286.01:17:52.08/cable/+6.5045E-03 2006.286.01:17:52.08/wx/21.06,1016.2,83 2006.286.01:17:53.08/fmout-gps/S +2.73E-07 2006.286.01:17:53.08:scan_name=286-0122,jd0610,80 2006.286.01:17:53.08:source=3c274,123049.42,122328.0,2000.0,ccw 2006.286.01:17:54.14#flagr#flagr/antenna,new-source 2006.286.01:17:54.14:checkk5 2006.286.01:17:54.56/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:17:54.93/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:17:55.32/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:17:55.72/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:17:56.33/chk_obsdata//k5ts1/T2860117??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:17:56.80/chk_obsdata//k5ts2/T2860117??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:17:57.19/chk_obsdata//k5ts3/T2860117??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:17:57.78/chk_obsdata//k5ts4/T2860117??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:17:58.62/k5log//k5ts1_log_newline 2006.286.01:17:59.35/k5log//k5ts2_log_newline 2006.286.01:18:00.32/k5log//k5ts3_log_newline 2006.286.01:18:01.05/k5log//k5ts4_log_newline 2006.286.01:18:01.07/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:18:01.07:setupk4=1 2006.286.01:18:01.07$setupk4/echo=on 2006.286.01:18:01.07$setupk4/pcalon 2006.286.01:18:01.07$pcalon/"no phase cal control is implemented here 2006.286.01:18:01.07$setupk4/"tpicd=stop 2006.286.01:18:01.07$setupk4/"rec=synch_on 2006.286.01:18:01.07$setupk4/"rec_mode=128 2006.286.01:18:01.07$setupk4/!* 2006.286.01:18:01.07$setupk4/recpk4 2006.286.01:18:01.07$recpk4/recpatch= 2006.286.01:18:01.07$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:18:01.07$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:18:01.07$setupk4/vck44 2006.286.01:18:01.07$vck44/valo=1,524.99 2006.286.01:18:01.07#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.01:18:01.07#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.01:18:01.07#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:01.07#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:18:01.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:18:01.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:18:01.08#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:18:01.08#ibcon#first serial, iclass 4, count 0 2006.286.01:18:01.08#ibcon#enter sib2, iclass 4, count 0 2006.286.01:18:01.08#ibcon#flushed, iclass 4, count 0 2006.286.01:18:01.08#ibcon#about to write, iclass 4, count 0 2006.286.01:18:01.08#ibcon#wrote, iclass 4, count 0 2006.286.01:18:01.08#ibcon#about to read 3, iclass 4, count 0 2006.286.01:18:01.09#ibcon#read 3, iclass 4, count 0 2006.286.01:18:01.09#ibcon#about to read 4, iclass 4, count 0 2006.286.01:18:01.09#ibcon#read 4, iclass 4, count 0 2006.286.01:18:01.09#ibcon#about to read 5, iclass 4, count 0 2006.286.01:18:01.09#ibcon#read 5, iclass 4, count 0 2006.286.01:18:01.09#ibcon#about to read 6, iclass 4, count 0 2006.286.01:18:01.09#ibcon#read 6, iclass 4, count 0 2006.286.01:18:01.09#ibcon#end of sib2, iclass 4, count 0 2006.286.01:18:01.09#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:18:01.09#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:18:01.09#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:18:01.09#ibcon#*before write, iclass 4, count 0 2006.286.01:18:01.09#ibcon#enter sib2, iclass 4, count 0 2006.286.01:18:01.09#ibcon#flushed, iclass 4, count 0 2006.286.01:18:01.09#ibcon#about to write, iclass 4, count 0 2006.286.01:18:01.09#ibcon#wrote, iclass 4, count 0 2006.286.01:18:01.09#ibcon#about to read 3, iclass 4, count 0 2006.286.01:18:01.14#ibcon#read 3, iclass 4, count 0 2006.286.01:18:01.14#ibcon#about to read 4, iclass 4, count 0 2006.286.01:18:01.14#ibcon#read 4, iclass 4, count 0 2006.286.01:18:01.14#ibcon#about to read 5, iclass 4, count 0 2006.286.01:18:01.14#ibcon#read 5, iclass 4, count 0 2006.286.01:18:01.14#ibcon#about to read 6, iclass 4, count 0 2006.286.01:18:01.14#ibcon#read 6, iclass 4, count 0 2006.286.01:18:01.14#ibcon#end of sib2, iclass 4, count 0 2006.286.01:18:01.14#ibcon#*after write, iclass 4, count 0 2006.286.01:18:01.14#ibcon#*before return 0, iclass 4, count 0 2006.286.01:18:01.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:18:01.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:18:01.14#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:18:01.14#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:18:01.14$vck44/va=1,7 2006.286.01:18:01.14#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.01:18:01.14#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.01:18:01.14#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:01.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:18:01.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:18:01.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:18:01.14#ibcon#enter wrdev, iclass 6, count 2 2006.286.01:18:01.14#ibcon#first serial, iclass 6, count 2 2006.286.01:18:01.14#ibcon#enter sib2, iclass 6, count 2 2006.286.01:18:01.14#ibcon#flushed, iclass 6, count 2 2006.286.01:18:01.14#ibcon#about to write, iclass 6, count 2 2006.286.01:18:01.14#ibcon#wrote, iclass 6, count 2 2006.286.01:18:01.14#ibcon#about to read 3, iclass 6, count 2 2006.286.01:18:01.16#ibcon#read 3, iclass 6, count 2 2006.286.01:18:01.16#ibcon#about to read 4, iclass 6, count 2 2006.286.01:18:01.16#ibcon#read 4, iclass 6, count 2 2006.286.01:18:01.16#ibcon#about to read 5, iclass 6, count 2 2006.286.01:18:01.16#ibcon#read 5, iclass 6, count 2 2006.286.01:18:01.16#ibcon#about to read 6, iclass 6, count 2 2006.286.01:18:01.16#ibcon#read 6, iclass 6, count 2 2006.286.01:18:01.16#ibcon#end of sib2, iclass 6, count 2 2006.286.01:18:01.16#ibcon#*mode == 0, iclass 6, count 2 2006.286.01:18:01.16#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.01:18:01.16#ibcon#[25=AT01-07\r\n] 2006.286.01:18:01.16#ibcon#*before write, iclass 6, count 2 2006.286.01:18:01.16#ibcon#enter sib2, iclass 6, count 2 2006.286.01:18:01.16#ibcon#flushed, iclass 6, count 2 2006.286.01:18:01.16#ibcon#about to write, iclass 6, count 2 2006.286.01:18:01.16#ibcon#wrote, iclass 6, count 2 2006.286.01:18:01.16#ibcon#about to read 3, iclass 6, count 2 2006.286.01:18:01.19#ibcon#read 3, iclass 6, count 2 2006.286.01:18:01.19#ibcon#about to read 4, iclass 6, count 2 2006.286.01:18:01.19#ibcon#read 4, iclass 6, count 2 2006.286.01:18:01.19#ibcon#about to read 5, iclass 6, count 2 2006.286.01:18:01.19#ibcon#read 5, iclass 6, count 2 2006.286.01:18:01.19#ibcon#about to read 6, iclass 6, count 2 2006.286.01:18:01.19#ibcon#read 6, iclass 6, count 2 2006.286.01:18:01.19#ibcon#end of sib2, iclass 6, count 2 2006.286.01:18:01.19#ibcon#*after write, iclass 6, count 2 2006.286.01:18:01.19#ibcon#*before return 0, iclass 6, count 2 2006.286.01:18:01.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:18:01.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:18:01.19#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.01:18:01.19#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:01.19#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:18:01.31#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:18:01.31#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:18:01.31#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:18:01.31#ibcon#first serial, iclass 6, count 0 2006.286.01:18:01.31#ibcon#enter sib2, iclass 6, count 0 2006.286.01:18:01.31#ibcon#flushed, iclass 6, count 0 2006.286.01:18:01.31#ibcon#about to write, iclass 6, count 0 2006.286.01:18:01.31#ibcon#wrote, iclass 6, count 0 2006.286.01:18:01.31#ibcon#about to read 3, iclass 6, count 0 2006.286.01:18:01.33#ibcon#read 3, iclass 6, count 0 2006.286.01:18:01.33#ibcon#about to read 4, iclass 6, count 0 2006.286.01:18:01.33#ibcon#read 4, iclass 6, count 0 2006.286.01:18:01.33#ibcon#about to read 5, iclass 6, count 0 2006.286.01:18:01.33#ibcon#read 5, iclass 6, count 0 2006.286.01:18:01.33#ibcon#about to read 6, iclass 6, count 0 2006.286.01:18:01.33#ibcon#read 6, iclass 6, count 0 2006.286.01:18:01.33#ibcon#end of sib2, iclass 6, count 0 2006.286.01:18:01.33#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:18:01.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:18:01.33#ibcon#[25=USB\r\n] 2006.286.01:18:01.33#ibcon#*before write, iclass 6, count 0 2006.286.01:18:01.33#ibcon#enter sib2, iclass 6, count 0 2006.286.01:18:01.33#ibcon#flushed, iclass 6, count 0 2006.286.01:18:01.33#ibcon#about to write, iclass 6, count 0 2006.286.01:18:01.33#ibcon#wrote, iclass 6, count 0 2006.286.01:18:01.33#ibcon#about to read 3, iclass 6, count 0 2006.286.01:18:01.36#ibcon#read 3, iclass 6, count 0 2006.286.01:18:01.36#ibcon#about to read 4, iclass 6, count 0 2006.286.01:18:01.36#ibcon#read 4, iclass 6, count 0 2006.286.01:18:01.36#ibcon#about to read 5, iclass 6, count 0 2006.286.01:18:01.36#ibcon#read 5, iclass 6, count 0 2006.286.01:18:01.36#ibcon#about to read 6, iclass 6, count 0 2006.286.01:18:01.36#ibcon#read 6, iclass 6, count 0 2006.286.01:18:01.36#ibcon#end of sib2, iclass 6, count 0 2006.286.01:18:01.36#ibcon#*after write, iclass 6, count 0 2006.286.01:18:01.36#ibcon#*before return 0, iclass 6, count 0 2006.286.01:18:01.36#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:18:01.36#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:18:01.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:18:01.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:18:01.36$vck44/valo=2,534.99 2006.286.01:18:01.36#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.01:18:01.36#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.01:18:01.36#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:01.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:18:01.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:18:01.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:18:01.36#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:18:01.36#ibcon#first serial, iclass 10, count 0 2006.286.01:18:01.36#ibcon#enter sib2, iclass 10, count 0 2006.286.01:18:01.36#ibcon#flushed, iclass 10, count 0 2006.286.01:18:01.36#ibcon#about to write, iclass 10, count 0 2006.286.01:18:01.36#ibcon#wrote, iclass 10, count 0 2006.286.01:18:01.36#ibcon#about to read 3, iclass 10, count 0 2006.286.01:18:01.38#ibcon#read 3, iclass 10, count 0 2006.286.01:18:01.38#ibcon#about to read 4, iclass 10, count 0 2006.286.01:18:01.38#ibcon#read 4, iclass 10, count 0 2006.286.01:18:01.38#ibcon#about to read 5, iclass 10, count 0 2006.286.01:18:01.38#ibcon#read 5, iclass 10, count 0 2006.286.01:18:01.38#ibcon#about to read 6, iclass 10, count 0 2006.286.01:18:01.38#ibcon#read 6, iclass 10, count 0 2006.286.01:18:01.38#ibcon#end of sib2, iclass 10, count 0 2006.286.01:18:01.38#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:18:01.38#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:18:01.38#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:18:01.38#ibcon#*before write, iclass 10, count 0 2006.286.01:18:01.38#ibcon#enter sib2, iclass 10, count 0 2006.286.01:18:01.38#ibcon#flushed, iclass 10, count 0 2006.286.01:18:01.38#ibcon#about to write, iclass 10, count 0 2006.286.01:18:01.38#ibcon#wrote, iclass 10, count 0 2006.286.01:18:01.38#ibcon#about to read 3, iclass 10, count 0 2006.286.01:18:01.42#ibcon#read 3, iclass 10, count 0 2006.286.01:18:01.42#ibcon#about to read 4, iclass 10, count 0 2006.286.01:18:01.42#ibcon#read 4, iclass 10, count 0 2006.286.01:18:01.42#ibcon#about to read 5, iclass 10, count 0 2006.286.01:18:01.42#ibcon#read 5, iclass 10, count 0 2006.286.01:18:01.42#ibcon#about to read 6, iclass 10, count 0 2006.286.01:18:01.42#ibcon#read 6, iclass 10, count 0 2006.286.01:18:01.42#ibcon#end of sib2, iclass 10, count 0 2006.286.01:18:01.42#ibcon#*after write, iclass 10, count 0 2006.286.01:18:01.42#ibcon#*before return 0, iclass 10, count 0 2006.286.01:18:01.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:18:01.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:18:01.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:18:01.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:18:01.42$vck44/va=2,6 2006.286.01:18:01.42#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.01:18:01.42#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.01:18:01.42#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:01.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:18:01.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:18:01.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:18:01.48#ibcon#enter wrdev, iclass 12, count 2 2006.286.01:18:01.48#ibcon#first serial, iclass 12, count 2 2006.286.01:18:01.48#ibcon#enter sib2, iclass 12, count 2 2006.286.01:18:01.48#ibcon#flushed, iclass 12, count 2 2006.286.01:18:01.48#ibcon#about to write, iclass 12, count 2 2006.286.01:18:01.48#ibcon#wrote, iclass 12, count 2 2006.286.01:18:01.48#ibcon#about to read 3, iclass 12, count 2 2006.286.01:18:01.50#ibcon#read 3, iclass 12, count 2 2006.286.01:18:01.50#ibcon#about to read 4, iclass 12, count 2 2006.286.01:18:01.50#ibcon#read 4, iclass 12, count 2 2006.286.01:18:01.50#ibcon#about to read 5, iclass 12, count 2 2006.286.01:18:01.50#ibcon#read 5, iclass 12, count 2 2006.286.01:18:01.50#ibcon#about to read 6, iclass 12, count 2 2006.286.01:18:01.50#ibcon#read 6, iclass 12, count 2 2006.286.01:18:01.50#ibcon#end of sib2, iclass 12, count 2 2006.286.01:18:01.50#ibcon#*mode == 0, iclass 12, count 2 2006.286.01:18:01.50#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.01:18:01.50#ibcon#[25=AT02-06\r\n] 2006.286.01:18:01.50#ibcon#*before write, iclass 12, count 2 2006.286.01:18:01.50#ibcon#enter sib2, iclass 12, count 2 2006.286.01:18:01.50#ibcon#flushed, iclass 12, count 2 2006.286.01:18:01.50#ibcon#about to write, iclass 12, count 2 2006.286.01:18:01.50#ibcon#wrote, iclass 12, count 2 2006.286.01:18:01.50#ibcon#about to read 3, iclass 12, count 2 2006.286.01:18:01.53#ibcon#read 3, iclass 12, count 2 2006.286.01:18:01.53#ibcon#about to read 4, iclass 12, count 2 2006.286.01:18:01.53#ibcon#read 4, iclass 12, count 2 2006.286.01:18:01.53#ibcon#about to read 5, iclass 12, count 2 2006.286.01:18:01.53#ibcon#read 5, iclass 12, count 2 2006.286.01:18:01.53#ibcon#about to read 6, iclass 12, count 2 2006.286.01:18:01.53#ibcon#read 6, iclass 12, count 2 2006.286.01:18:01.53#ibcon#end of sib2, iclass 12, count 2 2006.286.01:18:01.53#ibcon#*after write, iclass 12, count 2 2006.286.01:18:01.53#ibcon#*before return 0, iclass 12, count 2 2006.286.01:18:01.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:18:01.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:18:01.53#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.01:18:01.53#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:01.53#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:18:01.65#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:18:01.65#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:18:01.65#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:18:01.65#ibcon#first serial, iclass 12, count 0 2006.286.01:18:01.65#ibcon#enter sib2, iclass 12, count 0 2006.286.01:18:01.65#ibcon#flushed, iclass 12, count 0 2006.286.01:18:01.65#ibcon#about to write, iclass 12, count 0 2006.286.01:18:01.65#ibcon#wrote, iclass 12, count 0 2006.286.01:18:01.65#ibcon#about to read 3, iclass 12, count 0 2006.286.01:18:01.67#ibcon#read 3, iclass 12, count 0 2006.286.01:18:01.67#ibcon#about to read 4, iclass 12, count 0 2006.286.01:18:01.67#ibcon#read 4, iclass 12, count 0 2006.286.01:18:01.67#ibcon#about to read 5, iclass 12, count 0 2006.286.01:18:01.67#ibcon#read 5, iclass 12, count 0 2006.286.01:18:01.67#ibcon#about to read 6, iclass 12, count 0 2006.286.01:18:01.67#ibcon#read 6, iclass 12, count 0 2006.286.01:18:01.67#ibcon#end of sib2, iclass 12, count 0 2006.286.01:18:01.67#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:18:01.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:18:01.67#ibcon#[25=USB\r\n] 2006.286.01:18:01.67#ibcon#*before write, iclass 12, count 0 2006.286.01:18:01.67#ibcon#enter sib2, iclass 12, count 0 2006.286.01:18:01.67#ibcon#flushed, iclass 12, count 0 2006.286.01:18:01.67#ibcon#about to write, iclass 12, count 0 2006.286.01:18:01.67#ibcon#wrote, iclass 12, count 0 2006.286.01:18:01.67#ibcon#about to read 3, iclass 12, count 0 2006.286.01:18:01.70#ibcon#read 3, iclass 12, count 0 2006.286.01:18:01.70#ibcon#about to read 4, iclass 12, count 0 2006.286.01:18:01.70#ibcon#read 4, iclass 12, count 0 2006.286.01:18:01.70#ibcon#about to read 5, iclass 12, count 0 2006.286.01:18:01.70#ibcon#read 5, iclass 12, count 0 2006.286.01:18:01.70#ibcon#about to read 6, iclass 12, count 0 2006.286.01:18:01.70#ibcon#read 6, iclass 12, count 0 2006.286.01:18:01.70#ibcon#end of sib2, iclass 12, count 0 2006.286.01:18:01.70#ibcon#*after write, iclass 12, count 0 2006.286.01:18:01.70#ibcon#*before return 0, iclass 12, count 0 2006.286.01:18:01.70#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:18:01.70#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:18:01.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:18:01.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:18:01.70$vck44/valo=3,564.99 2006.286.01:18:01.70#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.01:18:01.70#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.01:18:01.70#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:01.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:18:01.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:18:01.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:18:01.70#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:18:01.70#ibcon#first serial, iclass 14, count 0 2006.286.01:18:01.70#ibcon#enter sib2, iclass 14, count 0 2006.286.01:18:01.70#ibcon#flushed, iclass 14, count 0 2006.286.01:18:01.70#ibcon#about to write, iclass 14, count 0 2006.286.01:18:01.70#ibcon#wrote, iclass 14, count 0 2006.286.01:18:01.70#ibcon#about to read 3, iclass 14, count 0 2006.286.01:18:01.72#ibcon#read 3, iclass 14, count 0 2006.286.01:18:01.72#ibcon#about to read 4, iclass 14, count 0 2006.286.01:18:01.72#ibcon#read 4, iclass 14, count 0 2006.286.01:18:01.72#ibcon#about to read 5, iclass 14, count 0 2006.286.01:18:01.72#ibcon#read 5, iclass 14, count 0 2006.286.01:18:01.72#ibcon#about to read 6, iclass 14, count 0 2006.286.01:18:01.72#ibcon#read 6, iclass 14, count 0 2006.286.01:18:01.72#ibcon#end of sib2, iclass 14, count 0 2006.286.01:18:01.72#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:18:01.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:18:01.72#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:18:01.72#ibcon#*before write, iclass 14, count 0 2006.286.01:18:01.72#ibcon#enter sib2, iclass 14, count 0 2006.286.01:18:01.72#ibcon#flushed, iclass 14, count 0 2006.286.01:18:01.72#ibcon#about to write, iclass 14, count 0 2006.286.01:18:01.72#ibcon#wrote, iclass 14, count 0 2006.286.01:18:01.72#ibcon#about to read 3, iclass 14, count 0 2006.286.01:18:01.76#ibcon#read 3, iclass 14, count 0 2006.286.01:18:01.76#ibcon#about to read 4, iclass 14, count 0 2006.286.01:18:01.76#ibcon#read 4, iclass 14, count 0 2006.286.01:18:01.76#ibcon#about to read 5, iclass 14, count 0 2006.286.01:18:01.76#ibcon#read 5, iclass 14, count 0 2006.286.01:18:01.76#ibcon#about to read 6, iclass 14, count 0 2006.286.01:18:01.76#ibcon#read 6, iclass 14, count 0 2006.286.01:18:01.76#ibcon#end of sib2, iclass 14, count 0 2006.286.01:18:01.76#ibcon#*after write, iclass 14, count 0 2006.286.01:18:01.76#ibcon#*before return 0, iclass 14, count 0 2006.286.01:18:01.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:18:01.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:18:01.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:18:01.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:18:01.76$vck44/va=3,7 2006.286.01:18:01.76#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.01:18:01.76#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.01:18:01.76#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:01.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:18:01.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:18:01.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:18:01.82#ibcon#enter wrdev, iclass 16, count 2 2006.286.01:18:01.82#ibcon#first serial, iclass 16, count 2 2006.286.01:18:01.82#ibcon#enter sib2, iclass 16, count 2 2006.286.01:18:01.82#ibcon#flushed, iclass 16, count 2 2006.286.01:18:01.82#ibcon#about to write, iclass 16, count 2 2006.286.01:18:01.82#ibcon#wrote, iclass 16, count 2 2006.286.01:18:01.82#ibcon#about to read 3, iclass 16, count 2 2006.286.01:18:01.84#ibcon#read 3, iclass 16, count 2 2006.286.01:18:01.84#ibcon#about to read 4, iclass 16, count 2 2006.286.01:18:01.84#ibcon#read 4, iclass 16, count 2 2006.286.01:18:01.84#ibcon#about to read 5, iclass 16, count 2 2006.286.01:18:01.84#ibcon#read 5, iclass 16, count 2 2006.286.01:18:01.84#ibcon#about to read 6, iclass 16, count 2 2006.286.01:18:01.84#ibcon#read 6, iclass 16, count 2 2006.286.01:18:01.84#ibcon#end of sib2, iclass 16, count 2 2006.286.01:18:01.84#ibcon#*mode == 0, iclass 16, count 2 2006.286.01:18:01.84#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.01:18:01.84#ibcon#[25=AT03-07\r\n] 2006.286.01:18:01.84#ibcon#*before write, iclass 16, count 2 2006.286.01:18:01.84#ibcon#enter sib2, iclass 16, count 2 2006.286.01:18:01.84#ibcon#flushed, iclass 16, count 2 2006.286.01:18:01.84#ibcon#about to write, iclass 16, count 2 2006.286.01:18:01.84#ibcon#wrote, iclass 16, count 2 2006.286.01:18:01.84#ibcon#about to read 3, iclass 16, count 2 2006.286.01:18:01.87#ibcon#read 3, iclass 16, count 2 2006.286.01:18:01.87#ibcon#about to read 4, iclass 16, count 2 2006.286.01:18:01.87#ibcon#read 4, iclass 16, count 2 2006.286.01:18:01.87#ibcon#about to read 5, iclass 16, count 2 2006.286.01:18:01.87#ibcon#read 5, iclass 16, count 2 2006.286.01:18:01.87#ibcon#about to read 6, iclass 16, count 2 2006.286.01:18:01.87#ibcon#read 6, iclass 16, count 2 2006.286.01:18:01.87#ibcon#end of sib2, iclass 16, count 2 2006.286.01:18:01.87#ibcon#*after write, iclass 16, count 2 2006.286.01:18:01.87#ibcon#*before return 0, iclass 16, count 2 2006.286.01:18:01.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:18:01.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:18:01.87#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.01:18:01.87#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:01.87#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:18:01.99#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:18:01.99#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:18:01.99#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:18:01.99#ibcon#first serial, iclass 16, count 0 2006.286.01:18:01.99#ibcon#enter sib2, iclass 16, count 0 2006.286.01:18:01.99#ibcon#flushed, iclass 16, count 0 2006.286.01:18:01.99#ibcon#about to write, iclass 16, count 0 2006.286.01:18:01.99#ibcon#wrote, iclass 16, count 0 2006.286.01:18:01.99#ibcon#about to read 3, iclass 16, count 0 2006.286.01:18:02.01#ibcon#read 3, iclass 16, count 0 2006.286.01:18:02.01#ibcon#about to read 4, iclass 16, count 0 2006.286.01:18:02.01#ibcon#read 4, iclass 16, count 0 2006.286.01:18:02.01#ibcon#about to read 5, iclass 16, count 0 2006.286.01:18:02.01#ibcon#read 5, iclass 16, count 0 2006.286.01:18:02.01#ibcon#about to read 6, iclass 16, count 0 2006.286.01:18:02.01#ibcon#read 6, iclass 16, count 0 2006.286.01:18:02.01#ibcon#end of sib2, iclass 16, count 0 2006.286.01:18:02.01#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:18:02.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:18:02.01#ibcon#[25=USB\r\n] 2006.286.01:18:02.01#ibcon#*before write, iclass 16, count 0 2006.286.01:18:02.01#ibcon#enter sib2, iclass 16, count 0 2006.286.01:18:02.01#ibcon#flushed, iclass 16, count 0 2006.286.01:18:02.01#ibcon#about to write, iclass 16, count 0 2006.286.01:18:02.01#ibcon#wrote, iclass 16, count 0 2006.286.01:18:02.01#ibcon#about to read 3, iclass 16, count 0 2006.286.01:18:02.04#ibcon#read 3, iclass 16, count 0 2006.286.01:18:02.04#ibcon#about to read 4, iclass 16, count 0 2006.286.01:18:02.04#ibcon#read 4, iclass 16, count 0 2006.286.01:18:02.04#ibcon#about to read 5, iclass 16, count 0 2006.286.01:18:02.04#ibcon#read 5, iclass 16, count 0 2006.286.01:18:02.04#ibcon#about to read 6, iclass 16, count 0 2006.286.01:18:02.04#ibcon#read 6, iclass 16, count 0 2006.286.01:18:02.04#ibcon#end of sib2, iclass 16, count 0 2006.286.01:18:02.04#ibcon#*after write, iclass 16, count 0 2006.286.01:18:02.04#ibcon#*before return 0, iclass 16, count 0 2006.286.01:18:02.04#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:18:02.04#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:18:02.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:18:02.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:18:02.04$vck44/valo=4,624.99 2006.286.01:18:02.04#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.01:18:02.04#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.01:18:02.04#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:02.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:18:02.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:18:02.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:18:02.04#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:18:02.04#ibcon#first serial, iclass 18, count 0 2006.286.01:18:02.04#ibcon#enter sib2, iclass 18, count 0 2006.286.01:18:02.04#ibcon#flushed, iclass 18, count 0 2006.286.01:18:02.04#ibcon#about to write, iclass 18, count 0 2006.286.01:18:02.04#ibcon#wrote, iclass 18, count 0 2006.286.01:18:02.04#ibcon#about to read 3, iclass 18, count 0 2006.286.01:18:02.06#ibcon#read 3, iclass 18, count 0 2006.286.01:18:02.06#ibcon#about to read 4, iclass 18, count 0 2006.286.01:18:02.06#ibcon#read 4, iclass 18, count 0 2006.286.01:18:02.06#ibcon#about to read 5, iclass 18, count 0 2006.286.01:18:02.06#ibcon#read 5, iclass 18, count 0 2006.286.01:18:02.06#ibcon#about to read 6, iclass 18, count 0 2006.286.01:18:02.06#ibcon#read 6, iclass 18, count 0 2006.286.01:18:02.06#ibcon#end of sib2, iclass 18, count 0 2006.286.01:18:02.06#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:18:02.06#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:18:02.06#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:18:02.06#ibcon#*before write, iclass 18, count 0 2006.286.01:18:02.06#ibcon#enter sib2, iclass 18, count 0 2006.286.01:18:02.06#ibcon#flushed, iclass 18, count 0 2006.286.01:18:02.06#ibcon#about to write, iclass 18, count 0 2006.286.01:18:02.06#ibcon#wrote, iclass 18, count 0 2006.286.01:18:02.06#ibcon#about to read 3, iclass 18, count 0 2006.286.01:18:02.10#ibcon#read 3, iclass 18, count 0 2006.286.01:18:02.10#ibcon#about to read 4, iclass 18, count 0 2006.286.01:18:02.10#ibcon#read 4, iclass 18, count 0 2006.286.01:18:02.10#ibcon#about to read 5, iclass 18, count 0 2006.286.01:18:02.10#ibcon#read 5, iclass 18, count 0 2006.286.01:18:02.10#ibcon#about to read 6, iclass 18, count 0 2006.286.01:18:02.10#ibcon#read 6, iclass 18, count 0 2006.286.01:18:02.10#ibcon#end of sib2, iclass 18, count 0 2006.286.01:18:02.10#ibcon#*after write, iclass 18, count 0 2006.286.01:18:02.10#ibcon#*before return 0, iclass 18, count 0 2006.286.01:18:02.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:18:02.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:18:02.10#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:18:02.10#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:18:02.10$vck44/va=4,6 2006.286.01:18:02.10#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.01:18:02.10#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.01:18:02.10#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:02.10#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:18:02.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:18:02.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:18:02.16#ibcon#enter wrdev, iclass 20, count 2 2006.286.01:18:02.16#ibcon#first serial, iclass 20, count 2 2006.286.01:18:02.16#ibcon#enter sib2, iclass 20, count 2 2006.286.01:18:02.16#ibcon#flushed, iclass 20, count 2 2006.286.01:18:02.16#ibcon#about to write, iclass 20, count 2 2006.286.01:18:02.16#ibcon#wrote, iclass 20, count 2 2006.286.01:18:02.16#ibcon#about to read 3, iclass 20, count 2 2006.286.01:18:02.18#ibcon#read 3, iclass 20, count 2 2006.286.01:18:02.18#ibcon#about to read 4, iclass 20, count 2 2006.286.01:18:02.18#ibcon#read 4, iclass 20, count 2 2006.286.01:18:02.18#ibcon#about to read 5, iclass 20, count 2 2006.286.01:18:02.18#ibcon#read 5, iclass 20, count 2 2006.286.01:18:02.18#ibcon#about to read 6, iclass 20, count 2 2006.286.01:18:02.18#ibcon#read 6, iclass 20, count 2 2006.286.01:18:02.18#ibcon#end of sib2, iclass 20, count 2 2006.286.01:18:02.18#ibcon#*mode == 0, iclass 20, count 2 2006.286.01:18:02.18#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.01:18:02.18#ibcon#[25=AT04-06\r\n] 2006.286.01:18:02.18#ibcon#*before write, iclass 20, count 2 2006.286.01:18:02.18#ibcon#enter sib2, iclass 20, count 2 2006.286.01:18:02.18#ibcon#flushed, iclass 20, count 2 2006.286.01:18:02.18#ibcon#about to write, iclass 20, count 2 2006.286.01:18:02.18#ibcon#wrote, iclass 20, count 2 2006.286.01:18:02.18#ibcon#about to read 3, iclass 20, count 2 2006.286.01:18:02.21#ibcon#read 3, iclass 20, count 2 2006.286.01:18:02.21#ibcon#about to read 4, iclass 20, count 2 2006.286.01:18:02.21#ibcon#read 4, iclass 20, count 2 2006.286.01:18:02.21#ibcon#about to read 5, iclass 20, count 2 2006.286.01:18:02.21#ibcon#read 5, iclass 20, count 2 2006.286.01:18:02.21#ibcon#about to read 6, iclass 20, count 2 2006.286.01:18:02.21#ibcon#read 6, iclass 20, count 2 2006.286.01:18:02.21#ibcon#end of sib2, iclass 20, count 2 2006.286.01:18:02.21#ibcon#*after write, iclass 20, count 2 2006.286.01:18:02.21#ibcon#*before return 0, iclass 20, count 2 2006.286.01:18:02.21#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:18:02.21#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:18:02.21#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.01:18:02.21#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:02.21#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:18:02.31#abcon#<5=/03 2.7 6.1 21.07 831016.2\r\n> 2006.286.01:18:02.33#abcon#{5=INTERFACE CLEAR} 2006.286.01:18:02.33#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:18:02.33#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:18:02.33#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:18:02.33#ibcon#first serial, iclass 20, count 0 2006.286.01:18:02.33#ibcon#enter sib2, iclass 20, count 0 2006.286.01:18:02.33#ibcon#flushed, iclass 20, count 0 2006.286.01:18:02.33#ibcon#about to write, iclass 20, count 0 2006.286.01:18:02.33#ibcon#wrote, iclass 20, count 0 2006.286.01:18:02.33#ibcon#about to read 3, iclass 20, count 0 2006.286.01:18:02.35#ibcon#read 3, iclass 20, count 0 2006.286.01:18:02.35#ibcon#about to read 4, iclass 20, count 0 2006.286.01:18:02.35#ibcon#read 4, iclass 20, count 0 2006.286.01:18:02.35#ibcon#about to read 5, iclass 20, count 0 2006.286.01:18:02.35#ibcon#read 5, iclass 20, count 0 2006.286.01:18:02.35#ibcon#about to read 6, iclass 20, count 0 2006.286.01:18:02.35#ibcon#read 6, iclass 20, count 0 2006.286.01:18:02.35#ibcon#end of sib2, iclass 20, count 0 2006.286.01:18:02.35#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:18:02.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:18:02.35#ibcon#[25=USB\r\n] 2006.286.01:18:02.35#ibcon#*before write, iclass 20, count 0 2006.286.01:18:02.35#ibcon#enter sib2, iclass 20, count 0 2006.286.01:18:02.35#ibcon#flushed, iclass 20, count 0 2006.286.01:18:02.35#ibcon#about to write, iclass 20, count 0 2006.286.01:18:02.35#ibcon#wrote, iclass 20, count 0 2006.286.01:18:02.35#ibcon#about to read 3, iclass 20, count 0 2006.286.01:18:02.38#ibcon#read 3, iclass 20, count 0 2006.286.01:18:02.38#ibcon#about to read 4, iclass 20, count 0 2006.286.01:18:02.38#ibcon#read 4, iclass 20, count 0 2006.286.01:18:02.38#ibcon#about to read 5, iclass 20, count 0 2006.286.01:18:02.38#ibcon#read 5, iclass 20, count 0 2006.286.01:18:02.38#ibcon#about to read 6, iclass 20, count 0 2006.286.01:18:02.38#ibcon#read 6, iclass 20, count 0 2006.286.01:18:02.38#ibcon#end of sib2, iclass 20, count 0 2006.286.01:18:02.38#ibcon#*after write, iclass 20, count 0 2006.286.01:18:02.38#ibcon#*before return 0, iclass 20, count 0 2006.286.01:18:02.38#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:18:02.38#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:18:02.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:18:02.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:18:02.38$vck44/valo=5,734.99 2006.286.01:18:02.38#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.01:18:02.38#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.01:18:02.38#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:02.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:18:02.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:18:02.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:18:02.38#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:18:02.38#ibcon#first serial, iclass 26, count 0 2006.286.01:18:02.38#ibcon#enter sib2, iclass 26, count 0 2006.286.01:18:02.38#ibcon#flushed, iclass 26, count 0 2006.286.01:18:02.38#ibcon#about to write, iclass 26, count 0 2006.286.01:18:02.38#ibcon#wrote, iclass 26, count 0 2006.286.01:18:02.38#ibcon#about to read 3, iclass 26, count 0 2006.286.01:18:02.39#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:18:02.40#ibcon#read 3, iclass 26, count 0 2006.286.01:18:02.40#ibcon#about to read 4, iclass 26, count 0 2006.286.01:18:02.40#ibcon#read 4, iclass 26, count 0 2006.286.01:18:02.40#ibcon#about to read 5, iclass 26, count 0 2006.286.01:18:02.40#ibcon#read 5, iclass 26, count 0 2006.286.01:18:02.40#ibcon#about to read 6, iclass 26, count 0 2006.286.01:18:02.40#ibcon#read 6, iclass 26, count 0 2006.286.01:18:02.40#ibcon#end of sib2, iclass 26, count 0 2006.286.01:18:02.40#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:18:02.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:18:02.40#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:18:02.40#ibcon#*before write, iclass 26, count 0 2006.286.01:18:02.40#ibcon#enter sib2, iclass 26, count 0 2006.286.01:18:02.40#ibcon#flushed, iclass 26, count 0 2006.286.01:18:02.40#ibcon#about to write, iclass 26, count 0 2006.286.01:18:02.40#ibcon#wrote, iclass 26, count 0 2006.286.01:18:02.40#ibcon#about to read 3, iclass 26, count 0 2006.286.01:18:02.44#ibcon#read 3, iclass 26, count 0 2006.286.01:18:02.44#ibcon#about to read 4, iclass 26, count 0 2006.286.01:18:02.44#ibcon#read 4, iclass 26, count 0 2006.286.01:18:02.44#ibcon#about to read 5, iclass 26, count 0 2006.286.01:18:02.44#ibcon#read 5, iclass 26, count 0 2006.286.01:18:02.44#ibcon#about to read 6, iclass 26, count 0 2006.286.01:18:02.44#ibcon#read 6, iclass 26, count 0 2006.286.01:18:02.44#ibcon#end of sib2, iclass 26, count 0 2006.286.01:18:02.44#ibcon#*after write, iclass 26, count 0 2006.286.01:18:02.44#ibcon#*before return 0, iclass 26, count 0 2006.286.01:18:02.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:18:02.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:18:02.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:18:02.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:18:02.44$vck44/va=5,3 2006.286.01:18:02.44#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.01:18:02.44#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.01:18:02.44#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:02.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:18:02.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:18:02.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:18:02.50#ibcon#enter wrdev, iclass 28, count 2 2006.286.01:18:02.50#ibcon#first serial, iclass 28, count 2 2006.286.01:18:02.50#ibcon#enter sib2, iclass 28, count 2 2006.286.01:18:02.50#ibcon#flushed, iclass 28, count 2 2006.286.01:18:02.50#ibcon#about to write, iclass 28, count 2 2006.286.01:18:02.50#ibcon#wrote, iclass 28, count 2 2006.286.01:18:02.50#ibcon#about to read 3, iclass 28, count 2 2006.286.01:18:02.52#ibcon#read 3, iclass 28, count 2 2006.286.01:18:02.52#ibcon#about to read 4, iclass 28, count 2 2006.286.01:18:02.52#ibcon#read 4, iclass 28, count 2 2006.286.01:18:02.52#ibcon#about to read 5, iclass 28, count 2 2006.286.01:18:02.52#ibcon#read 5, iclass 28, count 2 2006.286.01:18:02.52#ibcon#about to read 6, iclass 28, count 2 2006.286.01:18:02.52#ibcon#read 6, iclass 28, count 2 2006.286.01:18:02.52#ibcon#end of sib2, iclass 28, count 2 2006.286.01:18:02.52#ibcon#*mode == 0, iclass 28, count 2 2006.286.01:18:02.52#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.01:18:02.52#ibcon#[25=AT05-03\r\n] 2006.286.01:18:02.52#ibcon#*before write, iclass 28, count 2 2006.286.01:18:02.52#ibcon#enter sib2, iclass 28, count 2 2006.286.01:18:02.52#ibcon#flushed, iclass 28, count 2 2006.286.01:18:02.52#ibcon#about to write, iclass 28, count 2 2006.286.01:18:02.52#ibcon#wrote, iclass 28, count 2 2006.286.01:18:02.52#ibcon#about to read 3, iclass 28, count 2 2006.286.01:18:02.55#ibcon#read 3, iclass 28, count 2 2006.286.01:18:02.55#ibcon#about to read 4, iclass 28, count 2 2006.286.01:18:02.55#ibcon#read 4, iclass 28, count 2 2006.286.01:18:02.55#ibcon#about to read 5, iclass 28, count 2 2006.286.01:18:02.55#ibcon#read 5, iclass 28, count 2 2006.286.01:18:02.55#ibcon#about to read 6, iclass 28, count 2 2006.286.01:18:02.55#ibcon#read 6, iclass 28, count 2 2006.286.01:18:02.55#ibcon#end of sib2, iclass 28, count 2 2006.286.01:18:02.55#ibcon#*after write, iclass 28, count 2 2006.286.01:18:02.55#ibcon#*before return 0, iclass 28, count 2 2006.286.01:18:02.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:18:02.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:18:02.55#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.01:18:02.55#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:02.55#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:18:02.67#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:18:02.67#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:18:02.67#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:18:02.67#ibcon#first serial, iclass 28, count 0 2006.286.01:18:02.67#ibcon#enter sib2, iclass 28, count 0 2006.286.01:18:02.67#ibcon#flushed, iclass 28, count 0 2006.286.01:18:02.67#ibcon#about to write, iclass 28, count 0 2006.286.01:18:02.67#ibcon#wrote, iclass 28, count 0 2006.286.01:18:02.67#ibcon#about to read 3, iclass 28, count 0 2006.286.01:18:02.69#ibcon#read 3, iclass 28, count 0 2006.286.01:18:02.69#ibcon#about to read 4, iclass 28, count 0 2006.286.01:18:02.69#ibcon#read 4, iclass 28, count 0 2006.286.01:18:02.69#ibcon#about to read 5, iclass 28, count 0 2006.286.01:18:02.69#ibcon#read 5, iclass 28, count 0 2006.286.01:18:02.69#ibcon#about to read 6, iclass 28, count 0 2006.286.01:18:02.69#ibcon#read 6, iclass 28, count 0 2006.286.01:18:02.69#ibcon#end of sib2, iclass 28, count 0 2006.286.01:18:02.69#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:18:02.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:18:02.69#ibcon#[25=USB\r\n] 2006.286.01:18:02.69#ibcon#*before write, iclass 28, count 0 2006.286.01:18:02.69#ibcon#enter sib2, iclass 28, count 0 2006.286.01:18:02.69#ibcon#flushed, iclass 28, count 0 2006.286.01:18:02.69#ibcon#about to write, iclass 28, count 0 2006.286.01:18:02.69#ibcon#wrote, iclass 28, count 0 2006.286.01:18:02.69#ibcon#about to read 3, iclass 28, count 0 2006.286.01:18:02.72#ibcon#read 3, iclass 28, count 0 2006.286.01:18:02.72#ibcon#about to read 4, iclass 28, count 0 2006.286.01:18:02.72#ibcon#read 4, iclass 28, count 0 2006.286.01:18:02.72#ibcon#about to read 5, iclass 28, count 0 2006.286.01:18:02.72#ibcon#read 5, iclass 28, count 0 2006.286.01:18:02.72#ibcon#about to read 6, iclass 28, count 0 2006.286.01:18:02.72#ibcon#read 6, iclass 28, count 0 2006.286.01:18:02.72#ibcon#end of sib2, iclass 28, count 0 2006.286.01:18:02.72#ibcon#*after write, iclass 28, count 0 2006.286.01:18:02.72#ibcon#*before return 0, iclass 28, count 0 2006.286.01:18:02.72#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:18:02.72#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:18:02.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:18:02.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:18:02.72$vck44/valo=6,814.99 2006.286.01:18:02.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.01:18:02.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.01:18:02.72#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:02.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:18:02.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:18:02.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:18:02.72#ibcon#enter wrdev, iclass 30, count 0 2006.286.01:18:02.72#ibcon#first serial, iclass 30, count 0 2006.286.01:18:02.72#ibcon#enter sib2, iclass 30, count 0 2006.286.01:18:02.72#ibcon#flushed, iclass 30, count 0 2006.286.01:18:02.72#ibcon#about to write, iclass 30, count 0 2006.286.01:18:02.72#ibcon#wrote, iclass 30, count 0 2006.286.01:18:02.72#ibcon#about to read 3, iclass 30, count 0 2006.286.01:18:02.74#ibcon#read 3, iclass 30, count 0 2006.286.01:18:02.74#ibcon#about to read 4, iclass 30, count 0 2006.286.01:18:02.74#ibcon#read 4, iclass 30, count 0 2006.286.01:18:02.74#ibcon#about to read 5, iclass 30, count 0 2006.286.01:18:02.74#ibcon#read 5, iclass 30, count 0 2006.286.01:18:02.74#ibcon#about to read 6, iclass 30, count 0 2006.286.01:18:02.74#ibcon#read 6, iclass 30, count 0 2006.286.01:18:02.74#ibcon#end of sib2, iclass 30, count 0 2006.286.01:18:02.74#ibcon#*mode == 0, iclass 30, count 0 2006.286.01:18:02.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.01:18:02.74#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:18:02.74#ibcon#*before write, iclass 30, count 0 2006.286.01:18:02.74#ibcon#enter sib2, iclass 30, count 0 2006.286.01:18:02.74#ibcon#flushed, iclass 30, count 0 2006.286.01:18:02.74#ibcon#about to write, iclass 30, count 0 2006.286.01:18:02.74#ibcon#wrote, iclass 30, count 0 2006.286.01:18:02.74#ibcon#about to read 3, iclass 30, count 0 2006.286.01:18:02.78#ibcon#read 3, iclass 30, count 0 2006.286.01:18:02.78#ibcon#about to read 4, iclass 30, count 0 2006.286.01:18:02.78#ibcon#read 4, iclass 30, count 0 2006.286.01:18:02.78#ibcon#about to read 5, iclass 30, count 0 2006.286.01:18:02.78#ibcon#read 5, iclass 30, count 0 2006.286.01:18:02.78#ibcon#about to read 6, iclass 30, count 0 2006.286.01:18:02.78#ibcon#read 6, iclass 30, count 0 2006.286.01:18:02.78#ibcon#end of sib2, iclass 30, count 0 2006.286.01:18:02.78#ibcon#*after write, iclass 30, count 0 2006.286.01:18:02.78#ibcon#*before return 0, iclass 30, count 0 2006.286.01:18:02.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:18:02.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:18:02.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.01:18:02.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.01:18:02.78$vck44/va=6,4 2006.286.01:18:02.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.01:18:02.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.01:18:02.78#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:02.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:18:02.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:18:02.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:18:02.84#ibcon#enter wrdev, iclass 32, count 2 2006.286.01:18:02.84#ibcon#first serial, iclass 32, count 2 2006.286.01:18:02.84#ibcon#enter sib2, iclass 32, count 2 2006.286.01:18:02.84#ibcon#flushed, iclass 32, count 2 2006.286.01:18:02.84#ibcon#about to write, iclass 32, count 2 2006.286.01:18:02.84#ibcon#wrote, iclass 32, count 2 2006.286.01:18:02.84#ibcon#about to read 3, iclass 32, count 2 2006.286.01:18:02.86#ibcon#read 3, iclass 32, count 2 2006.286.01:18:02.86#ibcon#about to read 4, iclass 32, count 2 2006.286.01:18:02.86#ibcon#read 4, iclass 32, count 2 2006.286.01:18:02.86#ibcon#about to read 5, iclass 32, count 2 2006.286.01:18:02.86#ibcon#read 5, iclass 32, count 2 2006.286.01:18:02.86#ibcon#about to read 6, iclass 32, count 2 2006.286.01:18:02.86#ibcon#read 6, iclass 32, count 2 2006.286.01:18:02.86#ibcon#end of sib2, iclass 32, count 2 2006.286.01:18:02.86#ibcon#*mode == 0, iclass 32, count 2 2006.286.01:18:02.86#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.01:18:02.86#ibcon#[25=AT06-04\r\n] 2006.286.01:18:02.86#ibcon#*before write, iclass 32, count 2 2006.286.01:18:02.86#ibcon#enter sib2, iclass 32, count 2 2006.286.01:18:02.86#ibcon#flushed, iclass 32, count 2 2006.286.01:18:02.86#ibcon#about to write, iclass 32, count 2 2006.286.01:18:02.86#ibcon#wrote, iclass 32, count 2 2006.286.01:18:02.86#ibcon#about to read 3, iclass 32, count 2 2006.286.01:18:02.89#ibcon#read 3, iclass 32, count 2 2006.286.01:18:02.89#ibcon#about to read 4, iclass 32, count 2 2006.286.01:18:02.89#ibcon#read 4, iclass 32, count 2 2006.286.01:18:02.89#ibcon#about to read 5, iclass 32, count 2 2006.286.01:18:02.89#ibcon#read 5, iclass 32, count 2 2006.286.01:18:02.89#ibcon#about to read 6, iclass 32, count 2 2006.286.01:18:02.89#ibcon#read 6, iclass 32, count 2 2006.286.01:18:02.89#ibcon#end of sib2, iclass 32, count 2 2006.286.01:18:02.89#ibcon#*after write, iclass 32, count 2 2006.286.01:18:02.89#ibcon#*before return 0, iclass 32, count 2 2006.286.01:18:02.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:18:02.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:18:02.89#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.01:18:02.89#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:02.89#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:18:03.01#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:18:03.01#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:18:03.01#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:18:03.01#ibcon#first serial, iclass 32, count 0 2006.286.01:18:03.01#ibcon#enter sib2, iclass 32, count 0 2006.286.01:18:03.01#ibcon#flushed, iclass 32, count 0 2006.286.01:18:03.01#ibcon#about to write, iclass 32, count 0 2006.286.01:18:03.01#ibcon#wrote, iclass 32, count 0 2006.286.01:18:03.01#ibcon#about to read 3, iclass 32, count 0 2006.286.01:18:03.03#ibcon#read 3, iclass 32, count 0 2006.286.01:18:03.03#ibcon#about to read 4, iclass 32, count 0 2006.286.01:18:03.03#ibcon#read 4, iclass 32, count 0 2006.286.01:18:03.03#ibcon#about to read 5, iclass 32, count 0 2006.286.01:18:03.03#ibcon#read 5, iclass 32, count 0 2006.286.01:18:03.03#ibcon#about to read 6, iclass 32, count 0 2006.286.01:18:03.03#ibcon#read 6, iclass 32, count 0 2006.286.01:18:03.03#ibcon#end of sib2, iclass 32, count 0 2006.286.01:18:03.03#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:18:03.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:18:03.03#ibcon#[25=USB\r\n] 2006.286.01:18:03.03#ibcon#*before write, iclass 32, count 0 2006.286.01:18:03.03#ibcon#enter sib2, iclass 32, count 0 2006.286.01:18:03.03#ibcon#flushed, iclass 32, count 0 2006.286.01:18:03.03#ibcon#about to write, iclass 32, count 0 2006.286.01:18:03.03#ibcon#wrote, iclass 32, count 0 2006.286.01:18:03.03#ibcon#about to read 3, iclass 32, count 0 2006.286.01:18:03.06#ibcon#read 3, iclass 32, count 0 2006.286.01:18:03.06#ibcon#about to read 4, iclass 32, count 0 2006.286.01:18:03.06#ibcon#read 4, iclass 32, count 0 2006.286.01:18:03.06#ibcon#about to read 5, iclass 32, count 0 2006.286.01:18:03.06#ibcon#read 5, iclass 32, count 0 2006.286.01:18:03.06#ibcon#about to read 6, iclass 32, count 0 2006.286.01:18:03.06#ibcon#read 6, iclass 32, count 0 2006.286.01:18:03.06#ibcon#end of sib2, iclass 32, count 0 2006.286.01:18:03.06#ibcon#*after write, iclass 32, count 0 2006.286.01:18:03.06#ibcon#*before return 0, iclass 32, count 0 2006.286.01:18:03.06#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:18:03.06#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:18:03.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:18:03.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:18:03.06$vck44/valo=7,864.99 2006.286.01:18:03.06#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.01:18:03.06#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.01:18:03.06#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:03.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:18:03.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:18:03.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:18:03.06#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:18:03.06#ibcon#first serial, iclass 34, count 0 2006.286.01:18:03.06#ibcon#enter sib2, iclass 34, count 0 2006.286.01:18:03.06#ibcon#flushed, iclass 34, count 0 2006.286.01:18:03.06#ibcon#about to write, iclass 34, count 0 2006.286.01:18:03.06#ibcon#wrote, iclass 34, count 0 2006.286.01:18:03.06#ibcon#about to read 3, iclass 34, count 0 2006.286.01:18:03.08#ibcon#read 3, iclass 34, count 0 2006.286.01:18:03.08#ibcon#about to read 4, iclass 34, count 0 2006.286.01:18:03.08#ibcon#read 4, iclass 34, count 0 2006.286.01:18:03.08#ibcon#about to read 5, iclass 34, count 0 2006.286.01:18:03.08#ibcon#read 5, iclass 34, count 0 2006.286.01:18:03.08#ibcon#about to read 6, iclass 34, count 0 2006.286.01:18:03.08#ibcon#read 6, iclass 34, count 0 2006.286.01:18:03.08#ibcon#end of sib2, iclass 34, count 0 2006.286.01:18:03.08#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:18:03.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:18:03.08#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:18:03.08#ibcon#*before write, iclass 34, count 0 2006.286.01:18:03.08#ibcon#enter sib2, iclass 34, count 0 2006.286.01:18:03.08#ibcon#flushed, iclass 34, count 0 2006.286.01:18:03.08#ibcon#about to write, iclass 34, count 0 2006.286.01:18:03.08#ibcon#wrote, iclass 34, count 0 2006.286.01:18:03.08#ibcon#about to read 3, iclass 34, count 0 2006.286.01:18:03.12#ibcon#read 3, iclass 34, count 0 2006.286.01:18:03.12#ibcon#about to read 4, iclass 34, count 0 2006.286.01:18:03.12#ibcon#read 4, iclass 34, count 0 2006.286.01:18:03.12#ibcon#about to read 5, iclass 34, count 0 2006.286.01:18:03.12#ibcon#read 5, iclass 34, count 0 2006.286.01:18:03.12#ibcon#about to read 6, iclass 34, count 0 2006.286.01:18:03.12#ibcon#read 6, iclass 34, count 0 2006.286.01:18:03.12#ibcon#end of sib2, iclass 34, count 0 2006.286.01:18:03.12#ibcon#*after write, iclass 34, count 0 2006.286.01:18:03.12#ibcon#*before return 0, iclass 34, count 0 2006.286.01:18:03.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:18:03.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:18:03.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:18:03.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:18:03.12$vck44/va=7,4 2006.286.01:18:03.12#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.01:18:03.12#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.01:18:03.12#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:03.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:18:03.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:18:03.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:18:03.18#ibcon#enter wrdev, iclass 36, count 2 2006.286.01:18:03.18#ibcon#first serial, iclass 36, count 2 2006.286.01:18:03.18#ibcon#enter sib2, iclass 36, count 2 2006.286.01:18:03.18#ibcon#flushed, iclass 36, count 2 2006.286.01:18:03.18#ibcon#about to write, iclass 36, count 2 2006.286.01:18:03.18#ibcon#wrote, iclass 36, count 2 2006.286.01:18:03.18#ibcon#about to read 3, iclass 36, count 2 2006.286.01:18:03.20#ibcon#read 3, iclass 36, count 2 2006.286.01:18:03.20#ibcon#about to read 4, iclass 36, count 2 2006.286.01:18:03.20#ibcon#read 4, iclass 36, count 2 2006.286.01:18:03.20#ibcon#about to read 5, iclass 36, count 2 2006.286.01:18:03.20#ibcon#read 5, iclass 36, count 2 2006.286.01:18:03.20#ibcon#about to read 6, iclass 36, count 2 2006.286.01:18:03.20#ibcon#read 6, iclass 36, count 2 2006.286.01:18:03.20#ibcon#end of sib2, iclass 36, count 2 2006.286.01:18:03.20#ibcon#*mode == 0, iclass 36, count 2 2006.286.01:18:03.20#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.01:18:03.20#ibcon#[25=AT07-04\r\n] 2006.286.01:18:03.20#ibcon#*before write, iclass 36, count 2 2006.286.01:18:03.20#ibcon#enter sib2, iclass 36, count 2 2006.286.01:18:03.20#ibcon#flushed, iclass 36, count 2 2006.286.01:18:03.20#ibcon#about to write, iclass 36, count 2 2006.286.01:18:03.20#ibcon#wrote, iclass 36, count 2 2006.286.01:18:03.20#ibcon#about to read 3, iclass 36, count 2 2006.286.01:18:03.23#ibcon#read 3, iclass 36, count 2 2006.286.01:18:03.23#ibcon#about to read 4, iclass 36, count 2 2006.286.01:18:03.23#ibcon#read 4, iclass 36, count 2 2006.286.01:18:03.23#ibcon#about to read 5, iclass 36, count 2 2006.286.01:18:03.23#ibcon#read 5, iclass 36, count 2 2006.286.01:18:03.23#ibcon#about to read 6, iclass 36, count 2 2006.286.01:18:03.23#ibcon#read 6, iclass 36, count 2 2006.286.01:18:03.23#ibcon#end of sib2, iclass 36, count 2 2006.286.01:18:03.23#ibcon#*after write, iclass 36, count 2 2006.286.01:18:03.23#ibcon#*before return 0, iclass 36, count 2 2006.286.01:18:03.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:18:03.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:18:03.23#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.01:18:03.23#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:03.23#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:18:03.35#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:18:03.35#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:18:03.35#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:18:03.35#ibcon#first serial, iclass 36, count 0 2006.286.01:18:03.35#ibcon#enter sib2, iclass 36, count 0 2006.286.01:18:03.35#ibcon#flushed, iclass 36, count 0 2006.286.01:18:03.35#ibcon#about to write, iclass 36, count 0 2006.286.01:18:03.35#ibcon#wrote, iclass 36, count 0 2006.286.01:18:03.35#ibcon#about to read 3, iclass 36, count 0 2006.286.01:18:03.37#ibcon#read 3, iclass 36, count 0 2006.286.01:18:03.37#ibcon#about to read 4, iclass 36, count 0 2006.286.01:18:03.37#ibcon#read 4, iclass 36, count 0 2006.286.01:18:03.37#ibcon#about to read 5, iclass 36, count 0 2006.286.01:18:03.37#ibcon#read 5, iclass 36, count 0 2006.286.01:18:03.37#ibcon#about to read 6, iclass 36, count 0 2006.286.01:18:03.37#ibcon#read 6, iclass 36, count 0 2006.286.01:18:03.37#ibcon#end of sib2, iclass 36, count 0 2006.286.01:18:03.37#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:18:03.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:18:03.37#ibcon#[25=USB\r\n] 2006.286.01:18:03.37#ibcon#*before write, iclass 36, count 0 2006.286.01:18:03.37#ibcon#enter sib2, iclass 36, count 0 2006.286.01:18:03.37#ibcon#flushed, iclass 36, count 0 2006.286.01:18:03.37#ibcon#about to write, iclass 36, count 0 2006.286.01:18:03.37#ibcon#wrote, iclass 36, count 0 2006.286.01:18:03.37#ibcon#about to read 3, iclass 36, count 0 2006.286.01:18:03.40#ibcon#read 3, iclass 36, count 0 2006.286.01:18:03.40#ibcon#about to read 4, iclass 36, count 0 2006.286.01:18:03.40#ibcon#read 4, iclass 36, count 0 2006.286.01:18:03.40#ibcon#about to read 5, iclass 36, count 0 2006.286.01:18:03.40#ibcon#read 5, iclass 36, count 0 2006.286.01:18:03.40#ibcon#about to read 6, iclass 36, count 0 2006.286.01:18:03.40#ibcon#read 6, iclass 36, count 0 2006.286.01:18:03.40#ibcon#end of sib2, iclass 36, count 0 2006.286.01:18:03.40#ibcon#*after write, iclass 36, count 0 2006.286.01:18:03.40#ibcon#*before return 0, iclass 36, count 0 2006.286.01:18:03.40#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:18:03.40#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:18:03.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:18:03.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:18:03.40$vck44/valo=8,884.99 2006.286.01:18:03.40#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.01:18:03.40#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.01:18:03.40#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:03.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:18:03.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:18:03.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:18:03.40#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:18:03.40#ibcon#first serial, iclass 38, count 0 2006.286.01:18:03.40#ibcon#enter sib2, iclass 38, count 0 2006.286.01:18:03.40#ibcon#flushed, iclass 38, count 0 2006.286.01:18:03.40#ibcon#about to write, iclass 38, count 0 2006.286.01:18:03.40#ibcon#wrote, iclass 38, count 0 2006.286.01:18:03.40#ibcon#about to read 3, iclass 38, count 0 2006.286.01:18:03.42#ibcon#read 3, iclass 38, count 0 2006.286.01:18:03.42#ibcon#about to read 4, iclass 38, count 0 2006.286.01:18:03.42#ibcon#read 4, iclass 38, count 0 2006.286.01:18:03.42#ibcon#about to read 5, iclass 38, count 0 2006.286.01:18:03.42#ibcon#read 5, iclass 38, count 0 2006.286.01:18:03.42#ibcon#about to read 6, iclass 38, count 0 2006.286.01:18:03.42#ibcon#read 6, iclass 38, count 0 2006.286.01:18:03.42#ibcon#end of sib2, iclass 38, count 0 2006.286.01:18:03.42#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:18:03.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:18:03.42#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:18:03.42#ibcon#*before write, iclass 38, count 0 2006.286.01:18:03.42#ibcon#enter sib2, iclass 38, count 0 2006.286.01:18:03.42#ibcon#flushed, iclass 38, count 0 2006.286.01:18:03.42#ibcon#about to write, iclass 38, count 0 2006.286.01:18:03.42#ibcon#wrote, iclass 38, count 0 2006.286.01:18:03.42#ibcon#about to read 3, iclass 38, count 0 2006.286.01:18:03.46#ibcon#read 3, iclass 38, count 0 2006.286.01:18:03.46#ibcon#about to read 4, iclass 38, count 0 2006.286.01:18:03.46#ibcon#read 4, iclass 38, count 0 2006.286.01:18:03.46#ibcon#about to read 5, iclass 38, count 0 2006.286.01:18:03.46#ibcon#read 5, iclass 38, count 0 2006.286.01:18:03.46#ibcon#about to read 6, iclass 38, count 0 2006.286.01:18:03.46#ibcon#read 6, iclass 38, count 0 2006.286.01:18:03.46#ibcon#end of sib2, iclass 38, count 0 2006.286.01:18:03.46#ibcon#*after write, iclass 38, count 0 2006.286.01:18:03.46#ibcon#*before return 0, iclass 38, count 0 2006.286.01:18:03.46#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:18:03.46#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:18:03.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:18:03.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:18:03.46$vck44/va=8,3 2006.286.01:18:03.46#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.01:18:03.46#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.01:18:03.46#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:03.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:18:03.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:18:03.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:18:03.52#ibcon#enter wrdev, iclass 40, count 2 2006.286.01:18:03.52#ibcon#first serial, iclass 40, count 2 2006.286.01:18:03.52#ibcon#enter sib2, iclass 40, count 2 2006.286.01:18:03.52#ibcon#flushed, iclass 40, count 2 2006.286.01:18:03.52#ibcon#about to write, iclass 40, count 2 2006.286.01:18:03.52#ibcon#wrote, iclass 40, count 2 2006.286.01:18:03.52#ibcon#about to read 3, iclass 40, count 2 2006.286.01:18:03.54#ibcon#read 3, iclass 40, count 2 2006.286.01:18:03.54#ibcon#about to read 4, iclass 40, count 2 2006.286.01:18:03.54#ibcon#read 4, iclass 40, count 2 2006.286.01:18:03.54#ibcon#about to read 5, iclass 40, count 2 2006.286.01:18:03.54#ibcon#read 5, iclass 40, count 2 2006.286.01:18:03.54#ibcon#about to read 6, iclass 40, count 2 2006.286.01:18:03.54#ibcon#read 6, iclass 40, count 2 2006.286.01:18:03.54#ibcon#end of sib2, iclass 40, count 2 2006.286.01:18:03.54#ibcon#*mode == 0, iclass 40, count 2 2006.286.01:18:03.54#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.01:18:03.54#ibcon#[25=AT08-03\r\n] 2006.286.01:18:03.54#ibcon#*before write, iclass 40, count 2 2006.286.01:18:03.54#ibcon#enter sib2, iclass 40, count 2 2006.286.01:18:03.54#ibcon#flushed, iclass 40, count 2 2006.286.01:18:03.54#ibcon#about to write, iclass 40, count 2 2006.286.01:18:03.54#ibcon#wrote, iclass 40, count 2 2006.286.01:18:03.54#ibcon#about to read 3, iclass 40, count 2 2006.286.01:18:03.57#ibcon#read 3, iclass 40, count 2 2006.286.01:18:03.57#ibcon#about to read 4, iclass 40, count 2 2006.286.01:18:03.57#ibcon#read 4, iclass 40, count 2 2006.286.01:18:03.57#ibcon#about to read 5, iclass 40, count 2 2006.286.01:18:03.57#ibcon#read 5, iclass 40, count 2 2006.286.01:18:03.57#ibcon#about to read 6, iclass 40, count 2 2006.286.01:18:03.57#ibcon#read 6, iclass 40, count 2 2006.286.01:18:03.57#ibcon#end of sib2, iclass 40, count 2 2006.286.01:18:03.57#ibcon#*after write, iclass 40, count 2 2006.286.01:18:03.57#ibcon#*before return 0, iclass 40, count 2 2006.286.01:18:03.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:18:03.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:18:03.57#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.01:18:03.57#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:03.57#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:18:03.69#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:18:03.69#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:18:03.69#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:18:03.69#ibcon#first serial, iclass 40, count 0 2006.286.01:18:03.69#ibcon#enter sib2, iclass 40, count 0 2006.286.01:18:03.69#ibcon#flushed, iclass 40, count 0 2006.286.01:18:03.69#ibcon#about to write, iclass 40, count 0 2006.286.01:18:03.69#ibcon#wrote, iclass 40, count 0 2006.286.01:18:03.69#ibcon#about to read 3, iclass 40, count 0 2006.286.01:18:03.71#ibcon#read 3, iclass 40, count 0 2006.286.01:18:03.71#ibcon#about to read 4, iclass 40, count 0 2006.286.01:18:03.71#ibcon#read 4, iclass 40, count 0 2006.286.01:18:03.71#ibcon#about to read 5, iclass 40, count 0 2006.286.01:18:03.71#ibcon#read 5, iclass 40, count 0 2006.286.01:18:03.71#ibcon#about to read 6, iclass 40, count 0 2006.286.01:18:03.71#ibcon#read 6, iclass 40, count 0 2006.286.01:18:03.71#ibcon#end of sib2, iclass 40, count 0 2006.286.01:18:03.71#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:18:03.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:18:03.71#ibcon#[25=USB\r\n] 2006.286.01:18:03.71#ibcon#*before write, iclass 40, count 0 2006.286.01:18:03.71#ibcon#enter sib2, iclass 40, count 0 2006.286.01:18:03.71#ibcon#flushed, iclass 40, count 0 2006.286.01:18:03.71#ibcon#about to write, iclass 40, count 0 2006.286.01:18:03.71#ibcon#wrote, iclass 40, count 0 2006.286.01:18:03.71#ibcon#about to read 3, iclass 40, count 0 2006.286.01:18:03.74#ibcon#read 3, iclass 40, count 0 2006.286.01:18:03.74#ibcon#about to read 4, iclass 40, count 0 2006.286.01:18:03.74#ibcon#read 4, iclass 40, count 0 2006.286.01:18:03.74#ibcon#about to read 5, iclass 40, count 0 2006.286.01:18:03.74#ibcon#read 5, iclass 40, count 0 2006.286.01:18:03.74#ibcon#about to read 6, iclass 40, count 0 2006.286.01:18:03.74#ibcon#read 6, iclass 40, count 0 2006.286.01:18:03.74#ibcon#end of sib2, iclass 40, count 0 2006.286.01:18:03.74#ibcon#*after write, iclass 40, count 0 2006.286.01:18:03.74#ibcon#*before return 0, iclass 40, count 0 2006.286.01:18:03.74#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:18:03.74#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:18:03.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:18:03.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:18:03.74$vck44/vblo=1,629.99 2006.286.01:18:03.74#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.01:18:03.74#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.01:18:03.74#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:03.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:18:03.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:18:03.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:18:03.74#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:18:03.74#ibcon#first serial, iclass 4, count 0 2006.286.01:18:03.74#ibcon#enter sib2, iclass 4, count 0 2006.286.01:18:03.74#ibcon#flushed, iclass 4, count 0 2006.286.01:18:03.74#ibcon#about to write, iclass 4, count 0 2006.286.01:18:03.74#ibcon#wrote, iclass 4, count 0 2006.286.01:18:03.74#ibcon#about to read 3, iclass 4, count 0 2006.286.01:18:03.76#ibcon#read 3, iclass 4, count 0 2006.286.01:18:03.76#ibcon#about to read 4, iclass 4, count 0 2006.286.01:18:03.76#ibcon#read 4, iclass 4, count 0 2006.286.01:18:03.76#ibcon#about to read 5, iclass 4, count 0 2006.286.01:18:03.76#ibcon#read 5, iclass 4, count 0 2006.286.01:18:03.76#ibcon#about to read 6, iclass 4, count 0 2006.286.01:18:03.76#ibcon#read 6, iclass 4, count 0 2006.286.01:18:03.76#ibcon#end of sib2, iclass 4, count 0 2006.286.01:18:03.76#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:18:03.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:18:03.76#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:18:03.76#ibcon#*before write, iclass 4, count 0 2006.286.01:18:03.76#ibcon#enter sib2, iclass 4, count 0 2006.286.01:18:03.76#ibcon#flushed, iclass 4, count 0 2006.286.01:18:03.76#ibcon#about to write, iclass 4, count 0 2006.286.01:18:03.76#ibcon#wrote, iclass 4, count 0 2006.286.01:18:03.76#ibcon#about to read 3, iclass 4, count 0 2006.286.01:18:03.80#ibcon#read 3, iclass 4, count 0 2006.286.01:18:03.80#ibcon#about to read 4, iclass 4, count 0 2006.286.01:18:03.80#ibcon#read 4, iclass 4, count 0 2006.286.01:18:03.80#ibcon#about to read 5, iclass 4, count 0 2006.286.01:18:03.80#ibcon#read 5, iclass 4, count 0 2006.286.01:18:03.80#ibcon#about to read 6, iclass 4, count 0 2006.286.01:18:03.80#ibcon#read 6, iclass 4, count 0 2006.286.01:18:03.80#ibcon#end of sib2, iclass 4, count 0 2006.286.01:18:03.80#ibcon#*after write, iclass 4, count 0 2006.286.01:18:03.80#ibcon#*before return 0, iclass 4, count 0 2006.286.01:18:03.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:18:03.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:18:03.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:18:03.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:18:03.80$vck44/vb=1,4 2006.286.01:18:03.80#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.01:18:03.80#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.01:18:03.80#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:03.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:18:03.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:18:03.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:18:03.80#ibcon#enter wrdev, iclass 6, count 2 2006.286.01:18:03.80#ibcon#first serial, iclass 6, count 2 2006.286.01:18:03.80#ibcon#enter sib2, iclass 6, count 2 2006.286.01:18:03.80#ibcon#flushed, iclass 6, count 2 2006.286.01:18:03.80#ibcon#about to write, iclass 6, count 2 2006.286.01:18:03.80#ibcon#wrote, iclass 6, count 2 2006.286.01:18:03.80#ibcon#about to read 3, iclass 6, count 2 2006.286.01:18:03.82#ibcon#read 3, iclass 6, count 2 2006.286.01:18:03.82#ibcon#about to read 4, iclass 6, count 2 2006.286.01:18:03.82#ibcon#read 4, iclass 6, count 2 2006.286.01:18:03.82#ibcon#about to read 5, iclass 6, count 2 2006.286.01:18:03.82#ibcon#read 5, iclass 6, count 2 2006.286.01:18:03.82#ibcon#about to read 6, iclass 6, count 2 2006.286.01:18:03.82#ibcon#read 6, iclass 6, count 2 2006.286.01:18:03.82#ibcon#end of sib2, iclass 6, count 2 2006.286.01:18:03.82#ibcon#*mode == 0, iclass 6, count 2 2006.286.01:18:03.82#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.01:18:03.82#ibcon#[27=AT01-04\r\n] 2006.286.01:18:03.82#ibcon#*before write, iclass 6, count 2 2006.286.01:18:03.82#ibcon#enter sib2, iclass 6, count 2 2006.286.01:18:03.82#ibcon#flushed, iclass 6, count 2 2006.286.01:18:03.82#ibcon#about to write, iclass 6, count 2 2006.286.01:18:03.82#ibcon#wrote, iclass 6, count 2 2006.286.01:18:03.82#ibcon#about to read 3, iclass 6, count 2 2006.286.01:18:03.85#ibcon#read 3, iclass 6, count 2 2006.286.01:18:03.85#ibcon#about to read 4, iclass 6, count 2 2006.286.01:18:03.85#ibcon#read 4, iclass 6, count 2 2006.286.01:18:03.85#ibcon#about to read 5, iclass 6, count 2 2006.286.01:18:03.85#ibcon#read 5, iclass 6, count 2 2006.286.01:18:03.85#ibcon#about to read 6, iclass 6, count 2 2006.286.01:18:03.85#ibcon#read 6, iclass 6, count 2 2006.286.01:18:03.85#ibcon#end of sib2, iclass 6, count 2 2006.286.01:18:03.85#ibcon#*after write, iclass 6, count 2 2006.286.01:18:03.85#ibcon#*before return 0, iclass 6, count 2 2006.286.01:18:03.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:18:03.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:18:03.85#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.01:18:03.85#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:03.85#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:18:03.97#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:18:03.97#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:18:03.97#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:18:03.97#ibcon#first serial, iclass 6, count 0 2006.286.01:18:03.97#ibcon#enter sib2, iclass 6, count 0 2006.286.01:18:03.97#ibcon#flushed, iclass 6, count 0 2006.286.01:18:03.97#ibcon#about to write, iclass 6, count 0 2006.286.01:18:03.97#ibcon#wrote, iclass 6, count 0 2006.286.01:18:03.97#ibcon#about to read 3, iclass 6, count 0 2006.286.01:18:03.99#ibcon#read 3, iclass 6, count 0 2006.286.01:18:03.99#ibcon#about to read 4, iclass 6, count 0 2006.286.01:18:03.99#ibcon#read 4, iclass 6, count 0 2006.286.01:18:03.99#ibcon#about to read 5, iclass 6, count 0 2006.286.01:18:03.99#ibcon#read 5, iclass 6, count 0 2006.286.01:18:03.99#ibcon#about to read 6, iclass 6, count 0 2006.286.01:18:03.99#ibcon#read 6, iclass 6, count 0 2006.286.01:18:03.99#ibcon#end of sib2, iclass 6, count 0 2006.286.01:18:03.99#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:18:03.99#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:18:03.99#ibcon#[27=USB\r\n] 2006.286.01:18:03.99#ibcon#*before write, iclass 6, count 0 2006.286.01:18:03.99#ibcon#enter sib2, iclass 6, count 0 2006.286.01:18:03.99#ibcon#flushed, iclass 6, count 0 2006.286.01:18:03.99#ibcon#about to write, iclass 6, count 0 2006.286.01:18:03.99#ibcon#wrote, iclass 6, count 0 2006.286.01:18:03.99#ibcon#about to read 3, iclass 6, count 0 2006.286.01:18:04.02#ibcon#read 3, iclass 6, count 0 2006.286.01:18:04.02#ibcon#about to read 4, iclass 6, count 0 2006.286.01:18:04.02#ibcon#read 4, iclass 6, count 0 2006.286.01:18:04.02#ibcon#about to read 5, iclass 6, count 0 2006.286.01:18:04.02#ibcon#read 5, iclass 6, count 0 2006.286.01:18:04.02#ibcon#about to read 6, iclass 6, count 0 2006.286.01:18:04.02#ibcon#read 6, iclass 6, count 0 2006.286.01:18:04.02#ibcon#end of sib2, iclass 6, count 0 2006.286.01:18:04.02#ibcon#*after write, iclass 6, count 0 2006.286.01:18:04.02#ibcon#*before return 0, iclass 6, count 0 2006.286.01:18:04.02#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:18:04.02#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:18:04.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:18:04.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:18:04.02$vck44/vblo=2,634.99 2006.286.01:18:04.02#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.01:18:04.02#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.01:18:04.02#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:04.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:18:04.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:18:04.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:18:04.02#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:18:04.02#ibcon#first serial, iclass 10, count 0 2006.286.01:18:04.02#ibcon#enter sib2, iclass 10, count 0 2006.286.01:18:04.02#ibcon#flushed, iclass 10, count 0 2006.286.01:18:04.02#ibcon#about to write, iclass 10, count 0 2006.286.01:18:04.02#ibcon#wrote, iclass 10, count 0 2006.286.01:18:04.02#ibcon#about to read 3, iclass 10, count 0 2006.286.01:18:04.04#ibcon#read 3, iclass 10, count 0 2006.286.01:18:04.04#ibcon#about to read 4, iclass 10, count 0 2006.286.01:18:04.04#ibcon#read 4, iclass 10, count 0 2006.286.01:18:04.04#ibcon#about to read 5, iclass 10, count 0 2006.286.01:18:04.04#ibcon#read 5, iclass 10, count 0 2006.286.01:18:04.04#ibcon#about to read 6, iclass 10, count 0 2006.286.01:18:04.04#ibcon#read 6, iclass 10, count 0 2006.286.01:18:04.04#ibcon#end of sib2, iclass 10, count 0 2006.286.01:18:04.04#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:18:04.04#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:18:04.04#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:18:04.04#ibcon#*before write, iclass 10, count 0 2006.286.01:18:04.04#ibcon#enter sib2, iclass 10, count 0 2006.286.01:18:04.04#ibcon#flushed, iclass 10, count 0 2006.286.01:18:04.04#ibcon#about to write, iclass 10, count 0 2006.286.01:18:04.04#ibcon#wrote, iclass 10, count 0 2006.286.01:18:04.04#ibcon#about to read 3, iclass 10, count 0 2006.286.01:18:04.08#ibcon#read 3, iclass 10, count 0 2006.286.01:18:04.08#ibcon#about to read 4, iclass 10, count 0 2006.286.01:18:04.08#ibcon#read 4, iclass 10, count 0 2006.286.01:18:04.08#ibcon#about to read 5, iclass 10, count 0 2006.286.01:18:04.08#ibcon#read 5, iclass 10, count 0 2006.286.01:18:04.08#ibcon#about to read 6, iclass 10, count 0 2006.286.01:18:04.08#ibcon#read 6, iclass 10, count 0 2006.286.01:18:04.08#ibcon#end of sib2, iclass 10, count 0 2006.286.01:18:04.08#ibcon#*after write, iclass 10, count 0 2006.286.01:18:04.08#ibcon#*before return 0, iclass 10, count 0 2006.286.01:18:04.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:18:04.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:18:04.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:18:04.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:18:04.08$vck44/vb=2,5 2006.286.01:18:04.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.01:18:04.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.01:18:04.08#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:04.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:18:04.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:18:04.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:18:04.14#ibcon#enter wrdev, iclass 12, count 2 2006.286.01:18:04.14#ibcon#first serial, iclass 12, count 2 2006.286.01:18:04.14#ibcon#enter sib2, iclass 12, count 2 2006.286.01:18:04.14#ibcon#flushed, iclass 12, count 2 2006.286.01:18:04.14#ibcon#about to write, iclass 12, count 2 2006.286.01:18:04.14#ibcon#wrote, iclass 12, count 2 2006.286.01:18:04.14#ibcon#about to read 3, iclass 12, count 2 2006.286.01:18:04.16#ibcon#read 3, iclass 12, count 2 2006.286.01:18:04.16#ibcon#about to read 4, iclass 12, count 2 2006.286.01:18:04.16#ibcon#read 4, iclass 12, count 2 2006.286.01:18:04.16#ibcon#about to read 5, iclass 12, count 2 2006.286.01:18:04.16#ibcon#read 5, iclass 12, count 2 2006.286.01:18:04.16#ibcon#about to read 6, iclass 12, count 2 2006.286.01:18:04.16#ibcon#read 6, iclass 12, count 2 2006.286.01:18:04.16#ibcon#end of sib2, iclass 12, count 2 2006.286.01:18:04.16#ibcon#*mode == 0, iclass 12, count 2 2006.286.01:18:04.16#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.01:18:04.16#ibcon#[27=AT02-05\r\n] 2006.286.01:18:04.16#ibcon#*before write, iclass 12, count 2 2006.286.01:18:04.16#ibcon#enter sib2, iclass 12, count 2 2006.286.01:18:04.16#ibcon#flushed, iclass 12, count 2 2006.286.01:18:04.16#ibcon#about to write, iclass 12, count 2 2006.286.01:18:04.16#ibcon#wrote, iclass 12, count 2 2006.286.01:18:04.16#ibcon#about to read 3, iclass 12, count 2 2006.286.01:18:04.19#ibcon#read 3, iclass 12, count 2 2006.286.01:18:04.19#ibcon#about to read 4, iclass 12, count 2 2006.286.01:18:04.19#ibcon#read 4, iclass 12, count 2 2006.286.01:18:04.19#ibcon#about to read 5, iclass 12, count 2 2006.286.01:18:04.19#ibcon#read 5, iclass 12, count 2 2006.286.01:18:04.19#ibcon#about to read 6, iclass 12, count 2 2006.286.01:18:04.19#ibcon#read 6, iclass 12, count 2 2006.286.01:18:04.19#ibcon#end of sib2, iclass 12, count 2 2006.286.01:18:04.19#ibcon#*after write, iclass 12, count 2 2006.286.01:18:04.19#ibcon#*before return 0, iclass 12, count 2 2006.286.01:18:04.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:18:04.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:18:04.19#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.01:18:04.19#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:04.19#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:18:04.31#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:18:04.31#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:18:04.31#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:18:04.31#ibcon#first serial, iclass 12, count 0 2006.286.01:18:04.31#ibcon#enter sib2, iclass 12, count 0 2006.286.01:18:04.31#ibcon#flushed, iclass 12, count 0 2006.286.01:18:04.31#ibcon#about to write, iclass 12, count 0 2006.286.01:18:04.31#ibcon#wrote, iclass 12, count 0 2006.286.01:18:04.31#ibcon#about to read 3, iclass 12, count 0 2006.286.01:18:04.33#ibcon#read 3, iclass 12, count 0 2006.286.01:18:04.33#ibcon#about to read 4, iclass 12, count 0 2006.286.01:18:04.33#ibcon#read 4, iclass 12, count 0 2006.286.01:18:04.33#ibcon#about to read 5, iclass 12, count 0 2006.286.01:18:04.33#ibcon#read 5, iclass 12, count 0 2006.286.01:18:04.33#ibcon#about to read 6, iclass 12, count 0 2006.286.01:18:04.33#ibcon#read 6, iclass 12, count 0 2006.286.01:18:04.33#ibcon#end of sib2, iclass 12, count 0 2006.286.01:18:04.33#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:18:04.33#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:18:04.33#ibcon#[27=USB\r\n] 2006.286.01:18:04.33#ibcon#*before write, iclass 12, count 0 2006.286.01:18:04.33#ibcon#enter sib2, iclass 12, count 0 2006.286.01:18:04.33#ibcon#flushed, iclass 12, count 0 2006.286.01:18:04.33#ibcon#about to write, iclass 12, count 0 2006.286.01:18:04.33#ibcon#wrote, iclass 12, count 0 2006.286.01:18:04.33#ibcon#about to read 3, iclass 12, count 0 2006.286.01:18:04.36#ibcon#read 3, iclass 12, count 0 2006.286.01:18:04.36#ibcon#about to read 4, iclass 12, count 0 2006.286.01:18:04.36#ibcon#read 4, iclass 12, count 0 2006.286.01:18:04.36#ibcon#about to read 5, iclass 12, count 0 2006.286.01:18:04.36#ibcon#read 5, iclass 12, count 0 2006.286.01:18:04.36#ibcon#about to read 6, iclass 12, count 0 2006.286.01:18:04.36#ibcon#read 6, iclass 12, count 0 2006.286.01:18:04.36#ibcon#end of sib2, iclass 12, count 0 2006.286.01:18:04.36#ibcon#*after write, iclass 12, count 0 2006.286.01:18:04.36#ibcon#*before return 0, iclass 12, count 0 2006.286.01:18:04.36#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:18:04.36#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:18:04.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:18:04.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:18:04.36$vck44/vblo=3,649.99 2006.286.01:18:04.36#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.01:18:04.36#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.01:18:04.36#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:04.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:18:04.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:18:04.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:18:04.36#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:18:04.36#ibcon#first serial, iclass 14, count 0 2006.286.01:18:04.36#ibcon#enter sib2, iclass 14, count 0 2006.286.01:18:04.36#ibcon#flushed, iclass 14, count 0 2006.286.01:18:04.36#ibcon#about to write, iclass 14, count 0 2006.286.01:18:04.36#ibcon#wrote, iclass 14, count 0 2006.286.01:18:04.36#ibcon#about to read 3, iclass 14, count 0 2006.286.01:18:04.38#ibcon#read 3, iclass 14, count 0 2006.286.01:18:04.38#ibcon#about to read 4, iclass 14, count 0 2006.286.01:18:04.38#ibcon#read 4, iclass 14, count 0 2006.286.01:18:04.38#ibcon#about to read 5, iclass 14, count 0 2006.286.01:18:04.38#ibcon#read 5, iclass 14, count 0 2006.286.01:18:04.38#ibcon#about to read 6, iclass 14, count 0 2006.286.01:18:04.38#ibcon#read 6, iclass 14, count 0 2006.286.01:18:04.38#ibcon#end of sib2, iclass 14, count 0 2006.286.01:18:04.38#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:18:04.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:18:04.38#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:18:04.38#ibcon#*before write, iclass 14, count 0 2006.286.01:18:04.38#ibcon#enter sib2, iclass 14, count 0 2006.286.01:18:04.38#ibcon#flushed, iclass 14, count 0 2006.286.01:18:04.38#ibcon#about to write, iclass 14, count 0 2006.286.01:18:04.38#ibcon#wrote, iclass 14, count 0 2006.286.01:18:04.38#ibcon#about to read 3, iclass 14, count 0 2006.286.01:18:04.42#ibcon#read 3, iclass 14, count 0 2006.286.01:18:04.42#ibcon#about to read 4, iclass 14, count 0 2006.286.01:18:04.42#ibcon#read 4, iclass 14, count 0 2006.286.01:18:04.42#ibcon#about to read 5, iclass 14, count 0 2006.286.01:18:04.42#ibcon#read 5, iclass 14, count 0 2006.286.01:18:04.42#ibcon#about to read 6, iclass 14, count 0 2006.286.01:18:04.42#ibcon#read 6, iclass 14, count 0 2006.286.01:18:04.42#ibcon#end of sib2, iclass 14, count 0 2006.286.01:18:04.42#ibcon#*after write, iclass 14, count 0 2006.286.01:18:04.42#ibcon#*before return 0, iclass 14, count 0 2006.286.01:18:04.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:18:04.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:18:04.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:18:04.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:18:04.42$vck44/vb=3,4 2006.286.01:18:04.42#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.01:18:04.42#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.01:18:04.42#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:04.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:18:04.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:18:04.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:18:04.48#ibcon#enter wrdev, iclass 16, count 2 2006.286.01:18:04.48#ibcon#first serial, iclass 16, count 2 2006.286.01:18:04.48#ibcon#enter sib2, iclass 16, count 2 2006.286.01:18:04.48#ibcon#flushed, iclass 16, count 2 2006.286.01:18:04.48#ibcon#about to write, iclass 16, count 2 2006.286.01:18:04.48#ibcon#wrote, iclass 16, count 2 2006.286.01:18:04.48#ibcon#about to read 3, iclass 16, count 2 2006.286.01:18:04.50#ibcon#read 3, iclass 16, count 2 2006.286.01:18:04.50#ibcon#about to read 4, iclass 16, count 2 2006.286.01:18:04.50#ibcon#read 4, iclass 16, count 2 2006.286.01:18:04.50#ibcon#about to read 5, iclass 16, count 2 2006.286.01:18:04.50#ibcon#read 5, iclass 16, count 2 2006.286.01:18:04.50#ibcon#about to read 6, iclass 16, count 2 2006.286.01:18:04.50#ibcon#read 6, iclass 16, count 2 2006.286.01:18:04.50#ibcon#end of sib2, iclass 16, count 2 2006.286.01:18:04.50#ibcon#*mode == 0, iclass 16, count 2 2006.286.01:18:04.50#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.01:18:04.50#ibcon#[27=AT03-04\r\n] 2006.286.01:18:04.50#ibcon#*before write, iclass 16, count 2 2006.286.01:18:04.50#ibcon#enter sib2, iclass 16, count 2 2006.286.01:18:04.50#ibcon#flushed, iclass 16, count 2 2006.286.01:18:04.50#ibcon#about to write, iclass 16, count 2 2006.286.01:18:04.50#ibcon#wrote, iclass 16, count 2 2006.286.01:18:04.50#ibcon#about to read 3, iclass 16, count 2 2006.286.01:18:04.53#ibcon#read 3, iclass 16, count 2 2006.286.01:18:04.53#ibcon#about to read 4, iclass 16, count 2 2006.286.01:18:04.53#ibcon#read 4, iclass 16, count 2 2006.286.01:18:04.53#ibcon#about to read 5, iclass 16, count 2 2006.286.01:18:04.53#ibcon#read 5, iclass 16, count 2 2006.286.01:18:04.53#ibcon#about to read 6, iclass 16, count 2 2006.286.01:18:04.53#ibcon#read 6, iclass 16, count 2 2006.286.01:18:04.53#ibcon#end of sib2, iclass 16, count 2 2006.286.01:18:04.53#ibcon#*after write, iclass 16, count 2 2006.286.01:18:04.53#ibcon#*before return 0, iclass 16, count 2 2006.286.01:18:04.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:18:04.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:18:04.53#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.01:18:04.53#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:04.53#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:18:04.65#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:18:04.65#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:18:04.65#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:18:04.65#ibcon#first serial, iclass 16, count 0 2006.286.01:18:04.65#ibcon#enter sib2, iclass 16, count 0 2006.286.01:18:04.65#ibcon#flushed, iclass 16, count 0 2006.286.01:18:04.65#ibcon#about to write, iclass 16, count 0 2006.286.01:18:04.65#ibcon#wrote, iclass 16, count 0 2006.286.01:18:04.65#ibcon#about to read 3, iclass 16, count 0 2006.286.01:18:04.67#ibcon#read 3, iclass 16, count 0 2006.286.01:18:04.67#ibcon#about to read 4, iclass 16, count 0 2006.286.01:18:04.67#ibcon#read 4, iclass 16, count 0 2006.286.01:18:04.67#ibcon#about to read 5, iclass 16, count 0 2006.286.01:18:04.67#ibcon#read 5, iclass 16, count 0 2006.286.01:18:04.67#ibcon#about to read 6, iclass 16, count 0 2006.286.01:18:04.67#ibcon#read 6, iclass 16, count 0 2006.286.01:18:04.67#ibcon#end of sib2, iclass 16, count 0 2006.286.01:18:04.67#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:18:04.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:18:04.67#ibcon#[27=USB\r\n] 2006.286.01:18:04.67#ibcon#*before write, iclass 16, count 0 2006.286.01:18:04.67#ibcon#enter sib2, iclass 16, count 0 2006.286.01:18:04.67#ibcon#flushed, iclass 16, count 0 2006.286.01:18:04.67#ibcon#about to write, iclass 16, count 0 2006.286.01:18:04.67#ibcon#wrote, iclass 16, count 0 2006.286.01:18:04.67#ibcon#about to read 3, iclass 16, count 0 2006.286.01:18:04.70#ibcon#read 3, iclass 16, count 0 2006.286.01:18:04.70#ibcon#about to read 4, iclass 16, count 0 2006.286.01:18:04.70#ibcon#read 4, iclass 16, count 0 2006.286.01:18:04.70#ibcon#about to read 5, iclass 16, count 0 2006.286.01:18:04.70#ibcon#read 5, iclass 16, count 0 2006.286.01:18:04.70#ibcon#about to read 6, iclass 16, count 0 2006.286.01:18:04.70#ibcon#read 6, iclass 16, count 0 2006.286.01:18:04.70#ibcon#end of sib2, iclass 16, count 0 2006.286.01:18:04.70#ibcon#*after write, iclass 16, count 0 2006.286.01:18:04.70#ibcon#*before return 0, iclass 16, count 0 2006.286.01:18:04.70#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:18:04.70#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:18:04.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:18:04.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:18:04.70$vck44/vblo=4,679.99 2006.286.01:18:04.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.01:18:04.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.01:18:04.70#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:04.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:18:04.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:18:04.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:18:04.70#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:18:04.70#ibcon#first serial, iclass 18, count 0 2006.286.01:18:04.70#ibcon#enter sib2, iclass 18, count 0 2006.286.01:18:04.70#ibcon#flushed, iclass 18, count 0 2006.286.01:18:04.70#ibcon#about to write, iclass 18, count 0 2006.286.01:18:04.70#ibcon#wrote, iclass 18, count 0 2006.286.01:18:04.70#ibcon#about to read 3, iclass 18, count 0 2006.286.01:18:04.72#ibcon#read 3, iclass 18, count 0 2006.286.01:18:04.72#ibcon#about to read 4, iclass 18, count 0 2006.286.01:18:04.72#ibcon#read 4, iclass 18, count 0 2006.286.01:18:04.72#ibcon#about to read 5, iclass 18, count 0 2006.286.01:18:04.72#ibcon#read 5, iclass 18, count 0 2006.286.01:18:04.72#ibcon#about to read 6, iclass 18, count 0 2006.286.01:18:04.72#ibcon#read 6, iclass 18, count 0 2006.286.01:18:04.72#ibcon#end of sib2, iclass 18, count 0 2006.286.01:18:04.72#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:18:04.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:18:04.72#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:18:04.72#ibcon#*before write, iclass 18, count 0 2006.286.01:18:04.72#ibcon#enter sib2, iclass 18, count 0 2006.286.01:18:04.72#ibcon#flushed, iclass 18, count 0 2006.286.01:18:04.72#ibcon#about to write, iclass 18, count 0 2006.286.01:18:04.72#ibcon#wrote, iclass 18, count 0 2006.286.01:18:04.72#ibcon#about to read 3, iclass 18, count 0 2006.286.01:18:04.76#ibcon#read 3, iclass 18, count 0 2006.286.01:18:04.76#ibcon#about to read 4, iclass 18, count 0 2006.286.01:18:04.76#ibcon#read 4, iclass 18, count 0 2006.286.01:18:04.76#ibcon#about to read 5, iclass 18, count 0 2006.286.01:18:04.76#ibcon#read 5, iclass 18, count 0 2006.286.01:18:04.76#ibcon#about to read 6, iclass 18, count 0 2006.286.01:18:04.76#ibcon#read 6, iclass 18, count 0 2006.286.01:18:04.76#ibcon#end of sib2, iclass 18, count 0 2006.286.01:18:04.76#ibcon#*after write, iclass 18, count 0 2006.286.01:18:04.76#ibcon#*before return 0, iclass 18, count 0 2006.286.01:18:04.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:18:04.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:18:04.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:18:04.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:18:04.76$vck44/vb=4,5 2006.286.01:18:04.76#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.01:18:04.76#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.01:18:04.76#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:04.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:18:04.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:18:04.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:18:04.82#ibcon#enter wrdev, iclass 20, count 2 2006.286.01:18:04.82#ibcon#first serial, iclass 20, count 2 2006.286.01:18:04.82#ibcon#enter sib2, iclass 20, count 2 2006.286.01:18:04.82#ibcon#flushed, iclass 20, count 2 2006.286.01:18:04.82#ibcon#about to write, iclass 20, count 2 2006.286.01:18:04.82#ibcon#wrote, iclass 20, count 2 2006.286.01:18:04.82#ibcon#about to read 3, iclass 20, count 2 2006.286.01:18:04.84#ibcon#read 3, iclass 20, count 2 2006.286.01:18:04.84#ibcon#about to read 4, iclass 20, count 2 2006.286.01:18:04.84#ibcon#read 4, iclass 20, count 2 2006.286.01:18:04.84#ibcon#about to read 5, iclass 20, count 2 2006.286.01:18:04.84#ibcon#read 5, iclass 20, count 2 2006.286.01:18:04.84#ibcon#about to read 6, iclass 20, count 2 2006.286.01:18:04.84#ibcon#read 6, iclass 20, count 2 2006.286.01:18:04.84#ibcon#end of sib2, iclass 20, count 2 2006.286.01:18:04.84#ibcon#*mode == 0, iclass 20, count 2 2006.286.01:18:04.84#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.01:18:04.84#ibcon#[27=AT04-05\r\n] 2006.286.01:18:04.84#ibcon#*before write, iclass 20, count 2 2006.286.01:18:04.84#ibcon#enter sib2, iclass 20, count 2 2006.286.01:18:04.84#ibcon#flushed, iclass 20, count 2 2006.286.01:18:04.84#ibcon#about to write, iclass 20, count 2 2006.286.01:18:04.84#ibcon#wrote, iclass 20, count 2 2006.286.01:18:04.84#ibcon#about to read 3, iclass 20, count 2 2006.286.01:18:04.87#ibcon#read 3, iclass 20, count 2 2006.286.01:18:04.87#ibcon#about to read 4, iclass 20, count 2 2006.286.01:18:04.87#ibcon#read 4, iclass 20, count 2 2006.286.01:18:04.87#ibcon#about to read 5, iclass 20, count 2 2006.286.01:18:04.87#ibcon#read 5, iclass 20, count 2 2006.286.01:18:04.87#ibcon#about to read 6, iclass 20, count 2 2006.286.01:18:04.87#ibcon#read 6, iclass 20, count 2 2006.286.01:18:04.87#ibcon#end of sib2, iclass 20, count 2 2006.286.01:18:04.87#ibcon#*after write, iclass 20, count 2 2006.286.01:18:04.87#ibcon#*before return 0, iclass 20, count 2 2006.286.01:18:04.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:18:04.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:18:04.87#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.01:18:04.87#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:04.87#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:18:04.99#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:18:04.99#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:18:04.99#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:18:04.99#ibcon#first serial, iclass 20, count 0 2006.286.01:18:04.99#ibcon#enter sib2, iclass 20, count 0 2006.286.01:18:04.99#ibcon#flushed, iclass 20, count 0 2006.286.01:18:04.99#ibcon#about to write, iclass 20, count 0 2006.286.01:18:04.99#ibcon#wrote, iclass 20, count 0 2006.286.01:18:04.99#ibcon#about to read 3, iclass 20, count 0 2006.286.01:18:05.01#ibcon#read 3, iclass 20, count 0 2006.286.01:18:05.01#ibcon#about to read 4, iclass 20, count 0 2006.286.01:18:05.01#ibcon#read 4, iclass 20, count 0 2006.286.01:18:05.01#ibcon#about to read 5, iclass 20, count 0 2006.286.01:18:05.01#ibcon#read 5, iclass 20, count 0 2006.286.01:18:05.01#ibcon#about to read 6, iclass 20, count 0 2006.286.01:18:05.01#ibcon#read 6, iclass 20, count 0 2006.286.01:18:05.01#ibcon#end of sib2, iclass 20, count 0 2006.286.01:18:05.01#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:18:05.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:18:05.01#ibcon#[27=USB\r\n] 2006.286.01:18:05.01#ibcon#*before write, iclass 20, count 0 2006.286.01:18:05.01#ibcon#enter sib2, iclass 20, count 0 2006.286.01:18:05.01#ibcon#flushed, iclass 20, count 0 2006.286.01:18:05.01#ibcon#about to write, iclass 20, count 0 2006.286.01:18:05.01#ibcon#wrote, iclass 20, count 0 2006.286.01:18:05.01#ibcon#about to read 3, iclass 20, count 0 2006.286.01:18:05.04#ibcon#read 3, iclass 20, count 0 2006.286.01:18:05.04#ibcon#about to read 4, iclass 20, count 0 2006.286.01:18:05.04#ibcon#read 4, iclass 20, count 0 2006.286.01:18:05.04#ibcon#about to read 5, iclass 20, count 0 2006.286.01:18:05.04#ibcon#read 5, iclass 20, count 0 2006.286.01:18:05.04#ibcon#about to read 6, iclass 20, count 0 2006.286.01:18:05.04#ibcon#read 6, iclass 20, count 0 2006.286.01:18:05.04#ibcon#end of sib2, iclass 20, count 0 2006.286.01:18:05.04#ibcon#*after write, iclass 20, count 0 2006.286.01:18:05.04#ibcon#*before return 0, iclass 20, count 0 2006.286.01:18:05.04#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:18:05.04#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:18:05.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:18:05.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:18:05.04$vck44/vblo=5,709.99 2006.286.01:18:05.04#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.01:18:05.04#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.01:18:05.04#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:05.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:18:05.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:18:05.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:18:05.04#ibcon#enter wrdev, iclass 22, count 0 2006.286.01:18:05.04#ibcon#first serial, iclass 22, count 0 2006.286.01:18:05.04#ibcon#enter sib2, iclass 22, count 0 2006.286.01:18:05.04#ibcon#flushed, iclass 22, count 0 2006.286.01:18:05.04#ibcon#about to write, iclass 22, count 0 2006.286.01:18:05.04#ibcon#wrote, iclass 22, count 0 2006.286.01:18:05.04#ibcon#about to read 3, iclass 22, count 0 2006.286.01:18:05.06#ibcon#read 3, iclass 22, count 0 2006.286.01:18:05.06#ibcon#about to read 4, iclass 22, count 0 2006.286.01:18:05.06#ibcon#read 4, iclass 22, count 0 2006.286.01:18:05.06#ibcon#about to read 5, iclass 22, count 0 2006.286.01:18:05.06#ibcon#read 5, iclass 22, count 0 2006.286.01:18:05.06#ibcon#about to read 6, iclass 22, count 0 2006.286.01:18:05.06#ibcon#read 6, iclass 22, count 0 2006.286.01:18:05.06#ibcon#end of sib2, iclass 22, count 0 2006.286.01:18:05.06#ibcon#*mode == 0, iclass 22, count 0 2006.286.01:18:05.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.01:18:05.06#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:18:05.06#ibcon#*before write, iclass 22, count 0 2006.286.01:18:05.06#ibcon#enter sib2, iclass 22, count 0 2006.286.01:18:05.06#ibcon#flushed, iclass 22, count 0 2006.286.01:18:05.06#ibcon#about to write, iclass 22, count 0 2006.286.01:18:05.06#ibcon#wrote, iclass 22, count 0 2006.286.01:18:05.06#ibcon#about to read 3, iclass 22, count 0 2006.286.01:18:05.10#ibcon#read 3, iclass 22, count 0 2006.286.01:18:05.10#ibcon#about to read 4, iclass 22, count 0 2006.286.01:18:05.10#ibcon#read 4, iclass 22, count 0 2006.286.01:18:05.10#ibcon#about to read 5, iclass 22, count 0 2006.286.01:18:05.10#ibcon#read 5, iclass 22, count 0 2006.286.01:18:05.10#ibcon#about to read 6, iclass 22, count 0 2006.286.01:18:05.10#ibcon#read 6, iclass 22, count 0 2006.286.01:18:05.10#ibcon#end of sib2, iclass 22, count 0 2006.286.01:18:05.10#ibcon#*after write, iclass 22, count 0 2006.286.01:18:05.10#ibcon#*before return 0, iclass 22, count 0 2006.286.01:18:05.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:18:05.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:18:05.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.01:18:05.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.01:18:05.10$vck44/vb=5,4 2006.286.01:18:05.10#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.01:18:05.10#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.01:18:05.10#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:05.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:18:05.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:18:05.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:18:05.16#ibcon#enter wrdev, iclass 24, count 2 2006.286.01:18:05.16#ibcon#first serial, iclass 24, count 2 2006.286.01:18:05.16#ibcon#enter sib2, iclass 24, count 2 2006.286.01:18:05.16#ibcon#flushed, iclass 24, count 2 2006.286.01:18:05.16#ibcon#about to write, iclass 24, count 2 2006.286.01:18:05.16#ibcon#wrote, iclass 24, count 2 2006.286.01:18:05.16#ibcon#about to read 3, iclass 24, count 2 2006.286.01:18:05.18#ibcon#read 3, iclass 24, count 2 2006.286.01:18:05.18#ibcon#about to read 4, iclass 24, count 2 2006.286.01:18:05.18#ibcon#read 4, iclass 24, count 2 2006.286.01:18:05.18#ibcon#about to read 5, iclass 24, count 2 2006.286.01:18:05.18#ibcon#read 5, iclass 24, count 2 2006.286.01:18:05.18#ibcon#about to read 6, iclass 24, count 2 2006.286.01:18:05.18#ibcon#read 6, iclass 24, count 2 2006.286.01:18:05.18#ibcon#end of sib2, iclass 24, count 2 2006.286.01:18:05.18#ibcon#*mode == 0, iclass 24, count 2 2006.286.01:18:05.18#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.01:18:05.18#ibcon#[27=AT05-04\r\n] 2006.286.01:18:05.18#ibcon#*before write, iclass 24, count 2 2006.286.01:18:05.18#ibcon#enter sib2, iclass 24, count 2 2006.286.01:18:05.18#ibcon#flushed, iclass 24, count 2 2006.286.01:18:05.18#ibcon#about to write, iclass 24, count 2 2006.286.01:18:05.18#ibcon#wrote, iclass 24, count 2 2006.286.01:18:05.18#ibcon#about to read 3, iclass 24, count 2 2006.286.01:18:05.21#ibcon#read 3, iclass 24, count 2 2006.286.01:18:05.21#ibcon#about to read 4, iclass 24, count 2 2006.286.01:18:05.21#ibcon#read 4, iclass 24, count 2 2006.286.01:18:05.21#ibcon#about to read 5, iclass 24, count 2 2006.286.01:18:05.21#ibcon#read 5, iclass 24, count 2 2006.286.01:18:05.21#ibcon#about to read 6, iclass 24, count 2 2006.286.01:18:05.21#ibcon#read 6, iclass 24, count 2 2006.286.01:18:05.21#ibcon#end of sib2, iclass 24, count 2 2006.286.01:18:05.21#ibcon#*after write, iclass 24, count 2 2006.286.01:18:05.21#ibcon#*before return 0, iclass 24, count 2 2006.286.01:18:05.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:18:05.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:18:05.21#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.01:18:05.21#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:05.21#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:18:05.33#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:18:05.33#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:18:05.33#ibcon#enter wrdev, iclass 24, count 0 2006.286.01:18:05.33#ibcon#first serial, iclass 24, count 0 2006.286.01:18:05.33#ibcon#enter sib2, iclass 24, count 0 2006.286.01:18:05.33#ibcon#flushed, iclass 24, count 0 2006.286.01:18:05.33#ibcon#about to write, iclass 24, count 0 2006.286.01:18:05.33#ibcon#wrote, iclass 24, count 0 2006.286.01:18:05.33#ibcon#about to read 3, iclass 24, count 0 2006.286.01:18:05.35#ibcon#read 3, iclass 24, count 0 2006.286.01:18:05.35#ibcon#about to read 4, iclass 24, count 0 2006.286.01:18:05.35#ibcon#read 4, iclass 24, count 0 2006.286.01:18:05.35#ibcon#about to read 5, iclass 24, count 0 2006.286.01:18:05.35#ibcon#read 5, iclass 24, count 0 2006.286.01:18:05.35#ibcon#about to read 6, iclass 24, count 0 2006.286.01:18:05.35#ibcon#read 6, iclass 24, count 0 2006.286.01:18:05.35#ibcon#end of sib2, iclass 24, count 0 2006.286.01:18:05.35#ibcon#*mode == 0, iclass 24, count 0 2006.286.01:18:05.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.01:18:05.35#ibcon#[27=USB\r\n] 2006.286.01:18:05.35#ibcon#*before write, iclass 24, count 0 2006.286.01:18:05.35#ibcon#enter sib2, iclass 24, count 0 2006.286.01:18:05.35#ibcon#flushed, iclass 24, count 0 2006.286.01:18:05.35#ibcon#about to write, iclass 24, count 0 2006.286.01:18:05.35#ibcon#wrote, iclass 24, count 0 2006.286.01:18:05.35#ibcon#about to read 3, iclass 24, count 0 2006.286.01:18:05.38#ibcon#read 3, iclass 24, count 0 2006.286.01:18:05.38#ibcon#about to read 4, iclass 24, count 0 2006.286.01:18:05.38#ibcon#read 4, iclass 24, count 0 2006.286.01:18:05.38#ibcon#about to read 5, iclass 24, count 0 2006.286.01:18:05.38#ibcon#read 5, iclass 24, count 0 2006.286.01:18:05.38#ibcon#about to read 6, iclass 24, count 0 2006.286.01:18:05.38#ibcon#read 6, iclass 24, count 0 2006.286.01:18:05.38#ibcon#end of sib2, iclass 24, count 0 2006.286.01:18:05.38#ibcon#*after write, iclass 24, count 0 2006.286.01:18:05.38#ibcon#*before return 0, iclass 24, count 0 2006.286.01:18:05.38#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:18:05.38#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:18:05.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.01:18:05.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.01:18:05.38$vck44/vblo=6,719.99 2006.286.01:18:05.38#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.01:18:05.38#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.01:18:05.38#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:05.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:18:05.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:18:05.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:18:05.38#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:18:05.38#ibcon#first serial, iclass 26, count 0 2006.286.01:18:05.38#ibcon#enter sib2, iclass 26, count 0 2006.286.01:18:05.38#ibcon#flushed, iclass 26, count 0 2006.286.01:18:05.38#ibcon#about to write, iclass 26, count 0 2006.286.01:18:05.38#ibcon#wrote, iclass 26, count 0 2006.286.01:18:05.38#ibcon#about to read 3, iclass 26, count 0 2006.286.01:18:05.40#ibcon#read 3, iclass 26, count 0 2006.286.01:18:05.40#ibcon#about to read 4, iclass 26, count 0 2006.286.01:18:05.40#ibcon#read 4, iclass 26, count 0 2006.286.01:18:05.40#ibcon#about to read 5, iclass 26, count 0 2006.286.01:18:05.40#ibcon#read 5, iclass 26, count 0 2006.286.01:18:05.40#ibcon#about to read 6, iclass 26, count 0 2006.286.01:18:05.40#ibcon#read 6, iclass 26, count 0 2006.286.01:18:05.40#ibcon#end of sib2, iclass 26, count 0 2006.286.01:18:05.40#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:18:05.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:18:05.40#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:18:05.40#ibcon#*before write, iclass 26, count 0 2006.286.01:18:05.40#ibcon#enter sib2, iclass 26, count 0 2006.286.01:18:05.40#ibcon#flushed, iclass 26, count 0 2006.286.01:18:05.40#ibcon#about to write, iclass 26, count 0 2006.286.01:18:05.40#ibcon#wrote, iclass 26, count 0 2006.286.01:18:05.40#ibcon#about to read 3, iclass 26, count 0 2006.286.01:18:05.44#ibcon#read 3, iclass 26, count 0 2006.286.01:18:05.44#ibcon#about to read 4, iclass 26, count 0 2006.286.01:18:05.44#ibcon#read 4, iclass 26, count 0 2006.286.01:18:05.44#ibcon#about to read 5, iclass 26, count 0 2006.286.01:18:05.44#ibcon#read 5, iclass 26, count 0 2006.286.01:18:05.44#ibcon#about to read 6, iclass 26, count 0 2006.286.01:18:05.44#ibcon#read 6, iclass 26, count 0 2006.286.01:18:05.44#ibcon#end of sib2, iclass 26, count 0 2006.286.01:18:05.44#ibcon#*after write, iclass 26, count 0 2006.286.01:18:05.44#ibcon#*before return 0, iclass 26, count 0 2006.286.01:18:05.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:18:05.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:18:05.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:18:05.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:18:05.44$vck44/vb=6,3 2006.286.01:18:05.44#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.01:18:05.44#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.01:18:05.44#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:05.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:18:05.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:18:05.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:18:05.50#ibcon#enter wrdev, iclass 28, count 2 2006.286.01:18:05.50#ibcon#first serial, iclass 28, count 2 2006.286.01:18:05.50#ibcon#enter sib2, iclass 28, count 2 2006.286.01:18:05.50#ibcon#flushed, iclass 28, count 2 2006.286.01:18:05.50#ibcon#about to write, iclass 28, count 2 2006.286.01:18:05.50#ibcon#wrote, iclass 28, count 2 2006.286.01:18:05.50#ibcon#about to read 3, iclass 28, count 2 2006.286.01:18:05.52#ibcon#read 3, iclass 28, count 2 2006.286.01:18:05.52#ibcon#about to read 4, iclass 28, count 2 2006.286.01:18:05.52#ibcon#read 4, iclass 28, count 2 2006.286.01:18:05.52#ibcon#about to read 5, iclass 28, count 2 2006.286.01:18:05.52#ibcon#read 5, iclass 28, count 2 2006.286.01:18:05.52#ibcon#about to read 6, iclass 28, count 2 2006.286.01:18:05.52#ibcon#read 6, iclass 28, count 2 2006.286.01:18:05.52#ibcon#end of sib2, iclass 28, count 2 2006.286.01:18:05.52#ibcon#*mode == 0, iclass 28, count 2 2006.286.01:18:05.52#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.01:18:05.52#ibcon#[27=AT06-03\r\n] 2006.286.01:18:05.52#ibcon#*before write, iclass 28, count 2 2006.286.01:18:05.52#ibcon#enter sib2, iclass 28, count 2 2006.286.01:18:05.52#ibcon#flushed, iclass 28, count 2 2006.286.01:18:05.52#ibcon#about to write, iclass 28, count 2 2006.286.01:18:05.52#ibcon#wrote, iclass 28, count 2 2006.286.01:18:05.52#ibcon#about to read 3, iclass 28, count 2 2006.286.01:18:05.55#ibcon#read 3, iclass 28, count 2 2006.286.01:18:05.55#ibcon#about to read 4, iclass 28, count 2 2006.286.01:18:05.55#ibcon#read 4, iclass 28, count 2 2006.286.01:18:05.55#ibcon#about to read 5, iclass 28, count 2 2006.286.01:18:05.55#ibcon#read 5, iclass 28, count 2 2006.286.01:18:05.55#ibcon#about to read 6, iclass 28, count 2 2006.286.01:18:05.55#ibcon#read 6, iclass 28, count 2 2006.286.01:18:05.55#ibcon#end of sib2, iclass 28, count 2 2006.286.01:18:05.55#ibcon#*after write, iclass 28, count 2 2006.286.01:18:05.55#ibcon#*before return 0, iclass 28, count 2 2006.286.01:18:05.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:18:05.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:18:05.55#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.01:18:05.55#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:05.55#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:18:05.67#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:18:05.67#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:18:05.67#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:18:05.67#ibcon#first serial, iclass 28, count 0 2006.286.01:18:05.67#ibcon#enter sib2, iclass 28, count 0 2006.286.01:18:05.67#ibcon#flushed, iclass 28, count 0 2006.286.01:18:05.67#ibcon#about to write, iclass 28, count 0 2006.286.01:18:05.67#ibcon#wrote, iclass 28, count 0 2006.286.01:18:05.67#ibcon#about to read 3, iclass 28, count 0 2006.286.01:18:05.69#ibcon#read 3, iclass 28, count 0 2006.286.01:18:05.69#ibcon#about to read 4, iclass 28, count 0 2006.286.01:18:05.69#ibcon#read 4, iclass 28, count 0 2006.286.01:18:05.69#ibcon#about to read 5, iclass 28, count 0 2006.286.01:18:05.69#ibcon#read 5, iclass 28, count 0 2006.286.01:18:05.69#ibcon#about to read 6, iclass 28, count 0 2006.286.01:18:05.69#ibcon#read 6, iclass 28, count 0 2006.286.01:18:05.69#ibcon#end of sib2, iclass 28, count 0 2006.286.01:18:05.69#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:18:05.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:18:05.69#ibcon#[27=USB\r\n] 2006.286.01:18:05.69#ibcon#*before write, iclass 28, count 0 2006.286.01:18:05.69#ibcon#enter sib2, iclass 28, count 0 2006.286.01:18:05.69#ibcon#flushed, iclass 28, count 0 2006.286.01:18:05.69#ibcon#about to write, iclass 28, count 0 2006.286.01:18:05.69#ibcon#wrote, iclass 28, count 0 2006.286.01:18:05.69#ibcon#about to read 3, iclass 28, count 0 2006.286.01:18:05.72#ibcon#read 3, iclass 28, count 0 2006.286.01:18:05.72#ibcon#about to read 4, iclass 28, count 0 2006.286.01:18:05.72#ibcon#read 4, iclass 28, count 0 2006.286.01:18:05.72#ibcon#about to read 5, iclass 28, count 0 2006.286.01:18:05.72#ibcon#read 5, iclass 28, count 0 2006.286.01:18:05.72#ibcon#about to read 6, iclass 28, count 0 2006.286.01:18:05.72#ibcon#read 6, iclass 28, count 0 2006.286.01:18:05.72#ibcon#end of sib2, iclass 28, count 0 2006.286.01:18:05.72#ibcon#*after write, iclass 28, count 0 2006.286.01:18:05.72#ibcon#*before return 0, iclass 28, count 0 2006.286.01:18:05.72#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:18:05.72#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:18:05.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:18:05.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:18:05.72$vck44/vblo=7,734.99 2006.286.01:18:05.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.01:18:05.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.01:18:05.72#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:05.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:18:05.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:18:05.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:18:05.72#ibcon#enter wrdev, iclass 30, count 0 2006.286.01:18:05.72#ibcon#first serial, iclass 30, count 0 2006.286.01:18:05.72#ibcon#enter sib2, iclass 30, count 0 2006.286.01:18:05.72#ibcon#flushed, iclass 30, count 0 2006.286.01:18:05.72#ibcon#about to write, iclass 30, count 0 2006.286.01:18:05.72#ibcon#wrote, iclass 30, count 0 2006.286.01:18:05.72#ibcon#about to read 3, iclass 30, count 0 2006.286.01:18:05.74#ibcon#read 3, iclass 30, count 0 2006.286.01:18:05.74#ibcon#about to read 4, iclass 30, count 0 2006.286.01:18:05.74#ibcon#read 4, iclass 30, count 0 2006.286.01:18:05.74#ibcon#about to read 5, iclass 30, count 0 2006.286.01:18:05.74#ibcon#read 5, iclass 30, count 0 2006.286.01:18:05.74#ibcon#about to read 6, iclass 30, count 0 2006.286.01:18:05.74#ibcon#read 6, iclass 30, count 0 2006.286.01:18:05.74#ibcon#end of sib2, iclass 30, count 0 2006.286.01:18:05.74#ibcon#*mode == 0, iclass 30, count 0 2006.286.01:18:05.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.01:18:05.74#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:18:05.74#ibcon#*before write, iclass 30, count 0 2006.286.01:18:05.74#ibcon#enter sib2, iclass 30, count 0 2006.286.01:18:05.74#ibcon#flushed, iclass 30, count 0 2006.286.01:18:05.74#ibcon#about to write, iclass 30, count 0 2006.286.01:18:05.74#ibcon#wrote, iclass 30, count 0 2006.286.01:18:05.74#ibcon#about to read 3, iclass 30, count 0 2006.286.01:18:05.78#ibcon#read 3, iclass 30, count 0 2006.286.01:18:05.78#ibcon#about to read 4, iclass 30, count 0 2006.286.01:18:05.78#ibcon#read 4, iclass 30, count 0 2006.286.01:18:05.78#ibcon#about to read 5, iclass 30, count 0 2006.286.01:18:05.78#ibcon#read 5, iclass 30, count 0 2006.286.01:18:05.78#ibcon#about to read 6, iclass 30, count 0 2006.286.01:18:05.78#ibcon#read 6, iclass 30, count 0 2006.286.01:18:05.78#ibcon#end of sib2, iclass 30, count 0 2006.286.01:18:05.78#ibcon#*after write, iclass 30, count 0 2006.286.01:18:05.78#ibcon#*before return 0, iclass 30, count 0 2006.286.01:18:05.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:18:05.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:18:05.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.01:18:05.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.01:18:05.78$vck44/vb=7,4 2006.286.01:18:05.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.01:18:05.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.01:18:05.78#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:05.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:18:05.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:18:05.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:18:05.84#ibcon#enter wrdev, iclass 32, count 2 2006.286.01:18:05.84#ibcon#first serial, iclass 32, count 2 2006.286.01:18:05.84#ibcon#enter sib2, iclass 32, count 2 2006.286.01:18:05.84#ibcon#flushed, iclass 32, count 2 2006.286.01:18:05.84#ibcon#about to write, iclass 32, count 2 2006.286.01:18:05.84#ibcon#wrote, iclass 32, count 2 2006.286.01:18:05.84#ibcon#about to read 3, iclass 32, count 2 2006.286.01:18:05.86#ibcon#read 3, iclass 32, count 2 2006.286.01:18:05.86#ibcon#about to read 4, iclass 32, count 2 2006.286.01:18:05.86#ibcon#read 4, iclass 32, count 2 2006.286.01:18:05.86#ibcon#about to read 5, iclass 32, count 2 2006.286.01:18:05.86#ibcon#read 5, iclass 32, count 2 2006.286.01:18:05.86#ibcon#about to read 6, iclass 32, count 2 2006.286.01:18:05.86#ibcon#read 6, iclass 32, count 2 2006.286.01:18:05.86#ibcon#end of sib2, iclass 32, count 2 2006.286.01:18:05.86#ibcon#*mode == 0, iclass 32, count 2 2006.286.01:18:05.86#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.01:18:05.86#ibcon#[27=AT07-04\r\n] 2006.286.01:18:05.86#ibcon#*before write, iclass 32, count 2 2006.286.01:18:05.86#ibcon#enter sib2, iclass 32, count 2 2006.286.01:18:05.86#ibcon#flushed, iclass 32, count 2 2006.286.01:18:05.86#ibcon#about to write, iclass 32, count 2 2006.286.01:18:05.86#ibcon#wrote, iclass 32, count 2 2006.286.01:18:05.86#ibcon#about to read 3, iclass 32, count 2 2006.286.01:18:05.89#ibcon#read 3, iclass 32, count 2 2006.286.01:18:05.89#ibcon#about to read 4, iclass 32, count 2 2006.286.01:18:05.89#ibcon#read 4, iclass 32, count 2 2006.286.01:18:05.89#ibcon#about to read 5, iclass 32, count 2 2006.286.01:18:05.89#ibcon#read 5, iclass 32, count 2 2006.286.01:18:05.89#ibcon#about to read 6, iclass 32, count 2 2006.286.01:18:05.89#ibcon#read 6, iclass 32, count 2 2006.286.01:18:05.89#ibcon#end of sib2, iclass 32, count 2 2006.286.01:18:05.89#ibcon#*after write, iclass 32, count 2 2006.286.01:18:05.89#ibcon#*before return 0, iclass 32, count 2 2006.286.01:18:05.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:18:05.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:18:05.89#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.01:18:05.89#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:05.89#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:18:06.01#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:18:06.01#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:18:06.01#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:18:06.01#ibcon#first serial, iclass 32, count 0 2006.286.01:18:06.01#ibcon#enter sib2, iclass 32, count 0 2006.286.01:18:06.01#ibcon#flushed, iclass 32, count 0 2006.286.01:18:06.01#ibcon#about to write, iclass 32, count 0 2006.286.01:18:06.01#ibcon#wrote, iclass 32, count 0 2006.286.01:18:06.01#ibcon#about to read 3, iclass 32, count 0 2006.286.01:18:06.03#ibcon#read 3, iclass 32, count 0 2006.286.01:18:06.03#ibcon#about to read 4, iclass 32, count 0 2006.286.01:18:06.03#ibcon#read 4, iclass 32, count 0 2006.286.01:18:06.03#ibcon#about to read 5, iclass 32, count 0 2006.286.01:18:06.03#ibcon#read 5, iclass 32, count 0 2006.286.01:18:06.03#ibcon#about to read 6, iclass 32, count 0 2006.286.01:18:06.03#ibcon#read 6, iclass 32, count 0 2006.286.01:18:06.03#ibcon#end of sib2, iclass 32, count 0 2006.286.01:18:06.03#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:18:06.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:18:06.03#ibcon#[27=USB\r\n] 2006.286.01:18:06.03#ibcon#*before write, iclass 32, count 0 2006.286.01:18:06.03#ibcon#enter sib2, iclass 32, count 0 2006.286.01:18:06.03#ibcon#flushed, iclass 32, count 0 2006.286.01:18:06.03#ibcon#about to write, iclass 32, count 0 2006.286.01:18:06.03#ibcon#wrote, iclass 32, count 0 2006.286.01:18:06.03#ibcon#about to read 3, iclass 32, count 0 2006.286.01:18:06.06#ibcon#read 3, iclass 32, count 0 2006.286.01:18:06.06#ibcon#about to read 4, iclass 32, count 0 2006.286.01:18:06.06#ibcon#read 4, iclass 32, count 0 2006.286.01:18:06.06#ibcon#about to read 5, iclass 32, count 0 2006.286.01:18:06.06#ibcon#read 5, iclass 32, count 0 2006.286.01:18:06.06#ibcon#about to read 6, iclass 32, count 0 2006.286.01:18:06.06#ibcon#read 6, iclass 32, count 0 2006.286.01:18:06.06#ibcon#end of sib2, iclass 32, count 0 2006.286.01:18:06.06#ibcon#*after write, iclass 32, count 0 2006.286.01:18:06.06#ibcon#*before return 0, iclass 32, count 0 2006.286.01:18:06.06#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:18:06.06#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:18:06.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:18:06.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:18:06.06$vck44/vblo=8,744.99 2006.286.01:18:06.06#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.01:18:06.06#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.01:18:06.06#ibcon#ireg 17 cls_cnt 0 2006.286.01:18:06.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:18:06.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:18:06.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:18:06.06#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:18:06.06#ibcon#first serial, iclass 34, count 0 2006.286.01:18:06.06#ibcon#enter sib2, iclass 34, count 0 2006.286.01:18:06.06#ibcon#flushed, iclass 34, count 0 2006.286.01:18:06.06#ibcon#about to write, iclass 34, count 0 2006.286.01:18:06.06#ibcon#wrote, iclass 34, count 0 2006.286.01:18:06.06#ibcon#about to read 3, iclass 34, count 0 2006.286.01:18:06.08#ibcon#read 3, iclass 34, count 0 2006.286.01:18:06.08#ibcon#about to read 4, iclass 34, count 0 2006.286.01:18:06.08#ibcon#read 4, iclass 34, count 0 2006.286.01:18:06.08#ibcon#about to read 5, iclass 34, count 0 2006.286.01:18:06.08#ibcon#read 5, iclass 34, count 0 2006.286.01:18:06.08#ibcon#about to read 6, iclass 34, count 0 2006.286.01:18:06.08#ibcon#read 6, iclass 34, count 0 2006.286.01:18:06.08#ibcon#end of sib2, iclass 34, count 0 2006.286.01:18:06.08#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:18:06.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:18:06.08#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:18:06.08#ibcon#*before write, iclass 34, count 0 2006.286.01:18:06.08#ibcon#enter sib2, iclass 34, count 0 2006.286.01:18:06.08#ibcon#flushed, iclass 34, count 0 2006.286.01:18:06.08#ibcon#about to write, iclass 34, count 0 2006.286.01:18:06.08#ibcon#wrote, iclass 34, count 0 2006.286.01:18:06.08#ibcon#about to read 3, iclass 34, count 0 2006.286.01:18:06.12#ibcon#read 3, iclass 34, count 0 2006.286.01:18:06.12#ibcon#about to read 4, iclass 34, count 0 2006.286.01:18:06.12#ibcon#read 4, iclass 34, count 0 2006.286.01:18:06.12#ibcon#about to read 5, iclass 34, count 0 2006.286.01:18:06.12#ibcon#read 5, iclass 34, count 0 2006.286.01:18:06.12#ibcon#about to read 6, iclass 34, count 0 2006.286.01:18:06.12#ibcon#read 6, iclass 34, count 0 2006.286.01:18:06.12#ibcon#end of sib2, iclass 34, count 0 2006.286.01:18:06.12#ibcon#*after write, iclass 34, count 0 2006.286.01:18:06.12#ibcon#*before return 0, iclass 34, count 0 2006.286.01:18:06.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:18:06.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:18:06.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:18:06.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:18:06.12$vck44/vb=8,4 2006.286.01:18:06.12#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.01:18:06.12#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.01:18:06.12#ibcon#ireg 11 cls_cnt 2 2006.286.01:18:06.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:18:06.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:18:06.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:18:06.18#ibcon#enter wrdev, iclass 36, count 2 2006.286.01:18:06.18#ibcon#first serial, iclass 36, count 2 2006.286.01:18:06.18#ibcon#enter sib2, iclass 36, count 2 2006.286.01:18:06.18#ibcon#flushed, iclass 36, count 2 2006.286.01:18:06.18#ibcon#about to write, iclass 36, count 2 2006.286.01:18:06.18#ibcon#wrote, iclass 36, count 2 2006.286.01:18:06.18#ibcon#about to read 3, iclass 36, count 2 2006.286.01:18:06.20#ibcon#read 3, iclass 36, count 2 2006.286.01:18:06.20#ibcon#about to read 4, iclass 36, count 2 2006.286.01:18:06.20#ibcon#read 4, iclass 36, count 2 2006.286.01:18:06.20#ibcon#about to read 5, iclass 36, count 2 2006.286.01:18:06.20#ibcon#read 5, iclass 36, count 2 2006.286.01:18:06.20#ibcon#about to read 6, iclass 36, count 2 2006.286.01:18:06.20#ibcon#read 6, iclass 36, count 2 2006.286.01:18:06.20#ibcon#end of sib2, iclass 36, count 2 2006.286.01:18:06.20#ibcon#*mode == 0, iclass 36, count 2 2006.286.01:18:06.20#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.01:18:06.20#ibcon#[27=AT08-04\r\n] 2006.286.01:18:06.20#ibcon#*before write, iclass 36, count 2 2006.286.01:18:06.20#ibcon#enter sib2, iclass 36, count 2 2006.286.01:18:06.20#ibcon#flushed, iclass 36, count 2 2006.286.01:18:06.20#ibcon#about to write, iclass 36, count 2 2006.286.01:18:06.20#ibcon#wrote, iclass 36, count 2 2006.286.01:18:06.20#ibcon#about to read 3, iclass 36, count 2 2006.286.01:18:06.23#ibcon#read 3, iclass 36, count 2 2006.286.01:18:06.23#ibcon#about to read 4, iclass 36, count 2 2006.286.01:18:06.23#ibcon#read 4, iclass 36, count 2 2006.286.01:18:06.23#ibcon#about to read 5, iclass 36, count 2 2006.286.01:18:06.23#ibcon#read 5, iclass 36, count 2 2006.286.01:18:06.23#ibcon#about to read 6, iclass 36, count 2 2006.286.01:18:06.23#ibcon#read 6, iclass 36, count 2 2006.286.01:18:06.23#ibcon#end of sib2, iclass 36, count 2 2006.286.01:18:06.23#ibcon#*after write, iclass 36, count 2 2006.286.01:18:06.23#ibcon#*before return 0, iclass 36, count 2 2006.286.01:18:06.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:18:06.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:18:06.23#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.01:18:06.23#ibcon#ireg 7 cls_cnt 0 2006.286.01:18:06.23#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:18:06.35#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:18:06.35#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:18:06.35#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:18:06.35#ibcon#first serial, iclass 36, count 0 2006.286.01:18:06.35#ibcon#enter sib2, iclass 36, count 0 2006.286.01:18:06.35#ibcon#flushed, iclass 36, count 0 2006.286.01:18:06.35#ibcon#about to write, iclass 36, count 0 2006.286.01:18:06.35#ibcon#wrote, iclass 36, count 0 2006.286.01:18:06.35#ibcon#about to read 3, iclass 36, count 0 2006.286.01:18:06.37#ibcon#read 3, iclass 36, count 0 2006.286.01:18:06.37#ibcon#about to read 4, iclass 36, count 0 2006.286.01:18:06.37#ibcon#read 4, iclass 36, count 0 2006.286.01:18:06.37#ibcon#about to read 5, iclass 36, count 0 2006.286.01:18:06.37#ibcon#read 5, iclass 36, count 0 2006.286.01:18:06.37#ibcon#about to read 6, iclass 36, count 0 2006.286.01:18:06.37#ibcon#read 6, iclass 36, count 0 2006.286.01:18:06.37#ibcon#end of sib2, iclass 36, count 0 2006.286.01:18:06.37#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:18:06.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:18:06.37#ibcon#[27=USB\r\n] 2006.286.01:18:06.37#ibcon#*before write, iclass 36, count 0 2006.286.01:18:06.37#ibcon#enter sib2, iclass 36, count 0 2006.286.01:18:06.37#ibcon#flushed, iclass 36, count 0 2006.286.01:18:06.37#ibcon#about to write, iclass 36, count 0 2006.286.01:18:06.37#ibcon#wrote, iclass 36, count 0 2006.286.01:18:06.37#ibcon#about to read 3, iclass 36, count 0 2006.286.01:18:06.40#ibcon#read 3, iclass 36, count 0 2006.286.01:18:06.40#ibcon#about to read 4, iclass 36, count 0 2006.286.01:18:06.40#ibcon#read 4, iclass 36, count 0 2006.286.01:18:06.40#ibcon#about to read 5, iclass 36, count 0 2006.286.01:18:06.40#ibcon#read 5, iclass 36, count 0 2006.286.01:18:06.40#ibcon#about to read 6, iclass 36, count 0 2006.286.01:18:06.40#ibcon#read 6, iclass 36, count 0 2006.286.01:18:06.40#ibcon#end of sib2, iclass 36, count 0 2006.286.01:18:06.40#ibcon#*after write, iclass 36, count 0 2006.286.01:18:06.40#ibcon#*before return 0, iclass 36, count 0 2006.286.01:18:06.40#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:18:06.40#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:18:06.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:18:06.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:18:06.40$vck44/vabw=wide 2006.286.01:18:06.40#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.01:18:06.40#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.01:18:06.40#ibcon#ireg 8 cls_cnt 0 2006.286.01:18:06.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:18:06.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:18:06.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:18:06.40#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:18:06.40#ibcon#first serial, iclass 38, count 0 2006.286.01:18:06.40#ibcon#enter sib2, iclass 38, count 0 2006.286.01:18:06.40#ibcon#flushed, iclass 38, count 0 2006.286.01:18:06.40#ibcon#about to write, iclass 38, count 0 2006.286.01:18:06.40#ibcon#wrote, iclass 38, count 0 2006.286.01:18:06.40#ibcon#about to read 3, iclass 38, count 0 2006.286.01:18:06.42#ibcon#read 3, iclass 38, count 0 2006.286.01:18:06.42#ibcon#about to read 4, iclass 38, count 0 2006.286.01:18:06.42#ibcon#read 4, iclass 38, count 0 2006.286.01:18:06.42#ibcon#about to read 5, iclass 38, count 0 2006.286.01:18:06.42#ibcon#read 5, iclass 38, count 0 2006.286.01:18:06.42#ibcon#about to read 6, iclass 38, count 0 2006.286.01:18:06.42#ibcon#read 6, iclass 38, count 0 2006.286.01:18:06.42#ibcon#end of sib2, iclass 38, count 0 2006.286.01:18:06.42#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:18:06.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:18:06.42#ibcon#[25=BW32\r\n] 2006.286.01:18:06.42#ibcon#*before write, iclass 38, count 0 2006.286.01:18:06.42#ibcon#enter sib2, iclass 38, count 0 2006.286.01:18:06.42#ibcon#flushed, iclass 38, count 0 2006.286.01:18:06.42#ibcon#about to write, iclass 38, count 0 2006.286.01:18:06.42#ibcon#wrote, iclass 38, count 0 2006.286.01:18:06.42#ibcon#about to read 3, iclass 38, count 0 2006.286.01:18:06.45#ibcon#read 3, iclass 38, count 0 2006.286.01:18:06.45#ibcon#about to read 4, iclass 38, count 0 2006.286.01:18:06.45#ibcon#read 4, iclass 38, count 0 2006.286.01:18:06.45#ibcon#about to read 5, iclass 38, count 0 2006.286.01:18:06.45#ibcon#read 5, iclass 38, count 0 2006.286.01:18:06.45#ibcon#about to read 6, iclass 38, count 0 2006.286.01:18:06.45#ibcon#read 6, iclass 38, count 0 2006.286.01:18:06.45#ibcon#end of sib2, iclass 38, count 0 2006.286.01:18:06.45#ibcon#*after write, iclass 38, count 0 2006.286.01:18:06.45#ibcon#*before return 0, iclass 38, count 0 2006.286.01:18:06.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:18:06.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:18:06.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:18:06.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:18:06.45$vck44/vbbw=wide 2006.286.01:18:06.45#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.01:18:06.45#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.01:18:06.45#ibcon#ireg 8 cls_cnt 0 2006.286.01:18:06.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:18:06.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:18:06.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:18:06.52#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:18:06.52#ibcon#first serial, iclass 40, count 0 2006.286.01:18:06.52#ibcon#enter sib2, iclass 40, count 0 2006.286.01:18:06.52#ibcon#flushed, iclass 40, count 0 2006.286.01:18:06.52#ibcon#about to write, iclass 40, count 0 2006.286.01:18:06.52#ibcon#wrote, iclass 40, count 0 2006.286.01:18:06.52#ibcon#about to read 3, iclass 40, count 0 2006.286.01:18:06.54#ibcon#read 3, iclass 40, count 0 2006.286.01:18:06.54#ibcon#about to read 4, iclass 40, count 0 2006.286.01:18:06.54#ibcon#read 4, iclass 40, count 0 2006.286.01:18:06.54#ibcon#about to read 5, iclass 40, count 0 2006.286.01:18:06.54#ibcon#read 5, iclass 40, count 0 2006.286.01:18:06.54#ibcon#about to read 6, iclass 40, count 0 2006.286.01:18:06.54#ibcon#read 6, iclass 40, count 0 2006.286.01:18:06.54#ibcon#end of sib2, iclass 40, count 0 2006.286.01:18:06.54#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:18:06.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:18:06.54#ibcon#[27=BW32\r\n] 2006.286.01:18:06.54#ibcon#*before write, iclass 40, count 0 2006.286.01:18:06.54#ibcon#enter sib2, iclass 40, count 0 2006.286.01:18:06.54#ibcon#flushed, iclass 40, count 0 2006.286.01:18:06.54#ibcon#about to write, iclass 40, count 0 2006.286.01:18:06.54#ibcon#wrote, iclass 40, count 0 2006.286.01:18:06.54#ibcon#about to read 3, iclass 40, count 0 2006.286.01:18:06.57#ibcon#read 3, iclass 40, count 0 2006.286.01:18:06.57#ibcon#about to read 4, iclass 40, count 0 2006.286.01:18:06.57#ibcon#read 4, iclass 40, count 0 2006.286.01:18:06.57#ibcon#about to read 5, iclass 40, count 0 2006.286.01:18:06.57#ibcon#read 5, iclass 40, count 0 2006.286.01:18:06.57#ibcon#about to read 6, iclass 40, count 0 2006.286.01:18:06.57#ibcon#read 6, iclass 40, count 0 2006.286.01:18:06.57#ibcon#end of sib2, iclass 40, count 0 2006.286.01:18:06.57#ibcon#*after write, iclass 40, count 0 2006.286.01:18:06.57#ibcon#*before return 0, iclass 40, count 0 2006.286.01:18:06.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:18:06.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:18:06.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:18:06.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:18:06.57$setupk4/ifdk4 2006.286.01:18:06.57$ifdk4/lo= 2006.286.01:18:06.57$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:18:06.57$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:18:06.57$ifdk4/patch= 2006.286.01:18:06.57$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:18:06.57$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:18:06.57$setupk4/!*+20s 2006.286.01:18:12.48#abcon#<5=/03 2.7 6.1 21.07 831016.2\r\n> 2006.286.01:18:12.50#abcon#{5=INTERFACE CLEAR} 2006.286.01:18:12.56#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:18:21.08$setupk4/"tpicd 2006.286.01:18:21.08$setupk4/echo=off 2006.286.01:18:21.08$setupk4/xlog=off 2006.286.01:18:21.08:!2006.286.01:21:50 2006.286.01:18:29.14#trakl#Source acquired 2006.286.01:18:31.14#flagr#flagr/antenna,acquired 2006.286.01:21:50.00:preob 2006.286.01:21:50.14/onsource/TRACKING 2006.286.01:21:50.14:!2006.286.01:22:00 2006.286.01:22:00.00:"tape 2006.286.01:22:00.00:"st=record 2006.286.01:22:00.00:data_valid=on 2006.286.01:22:00.00:midob 2006.286.01:22:01.14/onsource/TRACKING 2006.286.01:22:01.14/wx/21.11,1016.2,82 2006.286.01:22:01.27/cable/+6.5030E-03 2006.286.01:22:02.36/va/01,07,usb,yes,34,37 2006.286.01:22:02.36/va/02,06,usb,yes,35,35 2006.286.01:22:02.36/va/03,07,usb,yes,34,36 2006.286.01:22:02.36/va/04,06,usb,yes,36,37 2006.286.01:22:02.36/va/05,03,usb,yes,35,35 2006.286.01:22:02.36/va/06,04,usb,yes,32,31 2006.286.01:22:02.36/va/07,04,usb,yes,32,33 2006.286.01:22:02.36/va/08,03,usb,yes,33,40 2006.286.01:22:02.59/valo/01,524.99,yes,locked 2006.286.01:22:02.59/valo/02,534.99,yes,locked 2006.286.01:22:02.59/valo/03,564.99,yes,locked 2006.286.01:22:02.59/valo/04,624.99,yes,locked 2006.286.01:22:02.59/valo/05,734.99,yes,locked 2006.286.01:22:02.59/valo/06,814.99,yes,locked 2006.286.01:22:02.59/valo/07,864.99,yes,locked 2006.286.01:22:02.59/valo/08,884.99,yes,locked 2006.286.01:22:03.68/vb/01,04,usb,yes,38,35 2006.286.01:22:03.68/vb/02,05,usb,yes,36,36 2006.286.01:22:03.68/vb/03,04,usb,yes,37,41 2006.286.01:22:03.68/vb/04,05,usb,yes,37,36 2006.286.01:22:03.68/vb/05,04,usb,yes,33,36 2006.286.01:22:03.68/vb/06,03,usb,yes,46,41 2006.286.01:22:03.68/vb/07,04,usb,yes,37,38 2006.286.01:22:03.68/vb/08,04,usb,yes,34,38 2006.286.01:22:03.91/vblo/01,629.99,yes,locked 2006.286.01:22:03.91/vblo/02,634.99,yes,locked 2006.286.01:22:03.91/vblo/03,649.99,yes,locked 2006.286.01:22:03.91/vblo/04,679.99,yes,locked 2006.286.01:22:03.91/vblo/05,709.99,yes,locked 2006.286.01:22:03.91/vblo/06,719.99,yes,locked 2006.286.01:22:03.91/vblo/07,734.99,yes,locked 2006.286.01:22:03.91/vblo/08,744.99,yes,locked 2006.286.01:22:04.06/vabw/8 2006.286.01:22:04.21/vbbw/8 2006.286.01:22:04.30/xfe/off,on,12.0 2006.286.01:22:04.74/ifatt/23,28,28,28 2006.286.01:22:05.08/fmout-gps/S +2.75E-07 2006.286.01:22:05.10:!2006.286.01:23:20 2006.286.01:23:20.00:data_valid=off 2006.286.01:23:20.00:"et 2006.286.01:23:20.00:!+3s 2006.286.01:23:23.01:"tape 2006.286.01:23:23.01:postob 2006.286.01:23:23.19/cable/+6.5022E-03 2006.286.01:23:23.19/wx/21.10,1016.2,83 2006.286.01:23:24.08/fmout-gps/S +2.76E-07 2006.286.01:23:24.08:scan_name=286-0126,jd0610,40 2006.286.01:23:24.08:source=1424-418,142756.30,-420619.4,2000.0,ccw 2006.286.01:23:25.14#flagr#flagr/antenna,new-source 2006.286.01:23:25.14:checkk5 2006.286.01:23:25.56/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:23:26.21/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:23:26.56/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:23:26.95/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:23:27.34/chk_obsdata//k5ts1/T2860122??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.01:23:27.75/chk_obsdata//k5ts2/T2860122??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.01:23:28.11/chk_obsdata//k5ts3/T2860122??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.01:23:28.51/chk_obsdata//k5ts4/T2860122??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.01:23:29.32/k5log//k5ts1_log_newline 2006.286.01:23:30.07/k5log//k5ts2_log_newline 2006.286.01:23:30.85/k5log//k5ts3_log_newline 2006.286.01:23:31.62/k5log//k5ts4_log_newline 2006.286.01:23:31.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:23:31.64:setupk4=1 2006.286.01:23:31.64$setupk4/echo=on 2006.286.01:23:31.64$setupk4/pcalon 2006.286.01:23:31.65$pcalon/"no phase cal control is implemented here 2006.286.01:23:31.65$setupk4/"tpicd=stop 2006.286.01:23:31.65$setupk4/"rec=synch_on 2006.286.01:23:31.65$setupk4/"rec_mode=128 2006.286.01:23:31.65$setupk4/!* 2006.286.01:23:31.65$setupk4/recpk4 2006.286.01:23:31.65$recpk4/recpatch= 2006.286.01:23:31.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:23:31.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:23:31.65$setupk4/vck44 2006.286.01:23:31.65$vck44/valo=1,524.99 2006.286.01:23:31.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.01:23:31.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.01:23:31.65#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:31.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:23:31.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:23:31.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:23:31.65#ibcon#enter wrdev, iclass 29, count 0 2006.286.01:23:31.65#ibcon#first serial, iclass 29, count 0 2006.286.01:23:31.65#ibcon#enter sib2, iclass 29, count 0 2006.286.01:23:31.65#ibcon#flushed, iclass 29, count 0 2006.286.01:23:31.65#ibcon#about to write, iclass 29, count 0 2006.286.01:23:31.65#ibcon#wrote, iclass 29, count 0 2006.286.01:23:31.65#ibcon#about to read 3, iclass 29, count 0 2006.286.01:23:31.67#ibcon#read 3, iclass 29, count 0 2006.286.01:23:31.67#ibcon#about to read 4, iclass 29, count 0 2006.286.01:23:31.67#ibcon#read 4, iclass 29, count 0 2006.286.01:23:31.67#ibcon#about to read 5, iclass 29, count 0 2006.286.01:23:31.67#ibcon#read 5, iclass 29, count 0 2006.286.01:23:31.67#ibcon#about to read 6, iclass 29, count 0 2006.286.01:23:31.67#ibcon#read 6, iclass 29, count 0 2006.286.01:23:31.67#ibcon#end of sib2, iclass 29, count 0 2006.286.01:23:31.67#ibcon#*mode == 0, iclass 29, count 0 2006.286.01:23:31.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.01:23:31.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:23:31.67#ibcon#*before write, iclass 29, count 0 2006.286.01:23:31.67#ibcon#enter sib2, iclass 29, count 0 2006.286.01:23:31.67#ibcon#flushed, iclass 29, count 0 2006.286.01:23:31.67#ibcon#about to write, iclass 29, count 0 2006.286.01:23:31.67#ibcon#wrote, iclass 29, count 0 2006.286.01:23:31.67#ibcon#about to read 3, iclass 29, count 0 2006.286.01:23:31.72#ibcon#read 3, iclass 29, count 0 2006.286.01:23:31.72#ibcon#about to read 4, iclass 29, count 0 2006.286.01:23:31.72#ibcon#read 4, iclass 29, count 0 2006.286.01:23:31.72#ibcon#about to read 5, iclass 29, count 0 2006.286.01:23:31.72#ibcon#read 5, iclass 29, count 0 2006.286.01:23:31.72#ibcon#about to read 6, iclass 29, count 0 2006.286.01:23:31.72#ibcon#read 6, iclass 29, count 0 2006.286.01:23:31.72#ibcon#end of sib2, iclass 29, count 0 2006.286.01:23:31.72#ibcon#*after write, iclass 29, count 0 2006.286.01:23:31.72#ibcon#*before return 0, iclass 29, count 0 2006.286.01:23:31.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:23:31.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:23:31.72#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.01:23:31.72#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.01:23:31.72$vck44/va=1,7 2006.286.01:23:31.72#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.01:23:31.72#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.01:23:31.72#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:31.72#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:23:31.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:23:31.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:23:31.72#ibcon#enter wrdev, iclass 31, count 2 2006.286.01:23:31.72#ibcon#first serial, iclass 31, count 2 2006.286.01:23:31.72#ibcon#enter sib2, iclass 31, count 2 2006.286.01:23:31.72#ibcon#flushed, iclass 31, count 2 2006.286.01:23:31.72#ibcon#about to write, iclass 31, count 2 2006.286.01:23:31.72#ibcon#wrote, iclass 31, count 2 2006.286.01:23:31.72#ibcon#about to read 3, iclass 31, count 2 2006.286.01:23:31.74#ibcon#read 3, iclass 31, count 2 2006.286.01:23:31.74#ibcon#about to read 4, iclass 31, count 2 2006.286.01:23:31.74#ibcon#read 4, iclass 31, count 2 2006.286.01:23:31.74#ibcon#about to read 5, iclass 31, count 2 2006.286.01:23:31.74#ibcon#read 5, iclass 31, count 2 2006.286.01:23:31.74#ibcon#about to read 6, iclass 31, count 2 2006.286.01:23:31.74#ibcon#read 6, iclass 31, count 2 2006.286.01:23:31.74#ibcon#end of sib2, iclass 31, count 2 2006.286.01:23:31.74#ibcon#*mode == 0, iclass 31, count 2 2006.286.01:23:31.74#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.01:23:31.74#ibcon#[25=AT01-07\r\n] 2006.286.01:23:31.74#ibcon#*before write, iclass 31, count 2 2006.286.01:23:31.74#ibcon#enter sib2, iclass 31, count 2 2006.286.01:23:31.74#ibcon#flushed, iclass 31, count 2 2006.286.01:23:31.74#ibcon#about to write, iclass 31, count 2 2006.286.01:23:31.74#ibcon#wrote, iclass 31, count 2 2006.286.01:23:31.74#ibcon#about to read 3, iclass 31, count 2 2006.286.01:23:31.77#ibcon#read 3, iclass 31, count 2 2006.286.01:23:31.77#ibcon#about to read 4, iclass 31, count 2 2006.286.01:23:31.77#ibcon#read 4, iclass 31, count 2 2006.286.01:23:31.77#ibcon#about to read 5, iclass 31, count 2 2006.286.01:23:31.77#ibcon#read 5, iclass 31, count 2 2006.286.01:23:31.77#ibcon#about to read 6, iclass 31, count 2 2006.286.01:23:31.77#ibcon#read 6, iclass 31, count 2 2006.286.01:23:31.77#ibcon#end of sib2, iclass 31, count 2 2006.286.01:23:31.77#ibcon#*after write, iclass 31, count 2 2006.286.01:23:31.77#ibcon#*before return 0, iclass 31, count 2 2006.286.01:23:31.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:23:31.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:23:31.77#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.01:23:31.77#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:31.77#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:23:31.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:23:31.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:23:31.89#ibcon#enter wrdev, iclass 31, count 0 2006.286.01:23:31.89#ibcon#first serial, iclass 31, count 0 2006.286.01:23:31.89#ibcon#enter sib2, iclass 31, count 0 2006.286.01:23:31.89#ibcon#flushed, iclass 31, count 0 2006.286.01:23:31.89#ibcon#about to write, iclass 31, count 0 2006.286.01:23:31.89#ibcon#wrote, iclass 31, count 0 2006.286.01:23:31.89#ibcon#about to read 3, iclass 31, count 0 2006.286.01:23:31.91#ibcon#read 3, iclass 31, count 0 2006.286.01:23:31.91#ibcon#about to read 4, iclass 31, count 0 2006.286.01:23:31.91#ibcon#read 4, iclass 31, count 0 2006.286.01:23:31.91#ibcon#about to read 5, iclass 31, count 0 2006.286.01:23:31.91#ibcon#read 5, iclass 31, count 0 2006.286.01:23:31.91#ibcon#about to read 6, iclass 31, count 0 2006.286.01:23:31.91#ibcon#read 6, iclass 31, count 0 2006.286.01:23:31.91#ibcon#end of sib2, iclass 31, count 0 2006.286.01:23:31.91#ibcon#*mode == 0, iclass 31, count 0 2006.286.01:23:31.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.01:23:31.91#ibcon#[25=USB\r\n] 2006.286.01:23:31.91#ibcon#*before write, iclass 31, count 0 2006.286.01:23:31.91#ibcon#enter sib2, iclass 31, count 0 2006.286.01:23:31.91#ibcon#flushed, iclass 31, count 0 2006.286.01:23:31.91#ibcon#about to write, iclass 31, count 0 2006.286.01:23:31.91#ibcon#wrote, iclass 31, count 0 2006.286.01:23:31.91#ibcon#about to read 3, iclass 31, count 0 2006.286.01:23:31.94#ibcon#read 3, iclass 31, count 0 2006.286.01:23:31.94#ibcon#about to read 4, iclass 31, count 0 2006.286.01:23:31.94#ibcon#read 4, iclass 31, count 0 2006.286.01:23:31.94#ibcon#about to read 5, iclass 31, count 0 2006.286.01:23:31.94#ibcon#read 5, iclass 31, count 0 2006.286.01:23:31.94#ibcon#about to read 6, iclass 31, count 0 2006.286.01:23:31.94#ibcon#read 6, iclass 31, count 0 2006.286.01:23:31.94#ibcon#end of sib2, iclass 31, count 0 2006.286.01:23:31.94#ibcon#*after write, iclass 31, count 0 2006.286.01:23:31.94#ibcon#*before return 0, iclass 31, count 0 2006.286.01:23:31.94#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:23:31.94#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:23:31.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.01:23:31.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.01:23:31.94$vck44/valo=2,534.99 2006.286.01:23:31.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.01:23:31.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.01:23:31.94#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:31.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:23:31.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:23:31.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:23:31.94#ibcon#enter wrdev, iclass 33, count 0 2006.286.01:23:31.94#ibcon#first serial, iclass 33, count 0 2006.286.01:23:31.94#ibcon#enter sib2, iclass 33, count 0 2006.286.01:23:31.94#ibcon#flushed, iclass 33, count 0 2006.286.01:23:31.94#ibcon#about to write, iclass 33, count 0 2006.286.01:23:31.94#ibcon#wrote, iclass 33, count 0 2006.286.01:23:31.94#ibcon#about to read 3, iclass 33, count 0 2006.286.01:23:31.96#ibcon#read 3, iclass 33, count 0 2006.286.01:23:31.96#ibcon#about to read 4, iclass 33, count 0 2006.286.01:23:31.96#ibcon#read 4, iclass 33, count 0 2006.286.01:23:31.96#ibcon#about to read 5, iclass 33, count 0 2006.286.01:23:31.96#ibcon#read 5, iclass 33, count 0 2006.286.01:23:31.96#ibcon#about to read 6, iclass 33, count 0 2006.286.01:23:31.96#ibcon#read 6, iclass 33, count 0 2006.286.01:23:31.96#ibcon#end of sib2, iclass 33, count 0 2006.286.01:23:31.96#ibcon#*mode == 0, iclass 33, count 0 2006.286.01:23:31.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.01:23:31.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:23:31.96#ibcon#*before write, iclass 33, count 0 2006.286.01:23:31.96#ibcon#enter sib2, iclass 33, count 0 2006.286.01:23:31.96#ibcon#flushed, iclass 33, count 0 2006.286.01:23:31.96#ibcon#about to write, iclass 33, count 0 2006.286.01:23:31.96#ibcon#wrote, iclass 33, count 0 2006.286.01:23:31.96#ibcon#about to read 3, iclass 33, count 0 2006.286.01:23:32.00#ibcon#read 3, iclass 33, count 0 2006.286.01:23:32.00#ibcon#about to read 4, iclass 33, count 0 2006.286.01:23:32.00#ibcon#read 4, iclass 33, count 0 2006.286.01:23:32.00#ibcon#about to read 5, iclass 33, count 0 2006.286.01:23:32.00#ibcon#read 5, iclass 33, count 0 2006.286.01:23:32.00#ibcon#about to read 6, iclass 33, count 0 2006.286.01:23:32.00#ibcon#read 6, iclass 33, count 0 2006.286.01:23:32.00#ibcon#end of sib2, iclass 33, count 0 2006.286.01:23:32.00#ibcon#*after write, iclass 33, count 0 2006.286.01:23:32.00#ibcon#*before return 0, iclass 33, count 0 2006.286.01:23:32.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:23:32.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:23:32.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.01:23:32.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.01:23:32.00$vck44/va=2,6 2006.286.01:23:32.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.01:23:32.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.01:23:32.00#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:32.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:23:32.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:23:32.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:23:32.06#ibcon#enter wrdev, iclass 35, count 2 2006.286.01:23:32.06#ibcon#first serial, iclass 35, count 2 2006.286.01:23:32.06#ibcon#enter sib2, iclass 35, count 2 2006.286.01:23:32.06#ibcon#flushed, iclass 35, count 2 2006.286.01:23:32.06#ibcon#about to write, iclass 35, count 2 2006.286.01:23:32.06#ibcon#wrote, iclass 35, count 2 2006.286.01:23:32.06#ibcon#about to read 3, iclass 35, count 2 2006.286.01:23:32.08#ibcon#read 3, iclass 35, count 2 2006.286.01:23:32.08#ibcon#about to read 4, iclass 35, count 2 2006.286.01:23:32.08#ibcon#read 4, iclass 35, count 2 2006.286.01:23:32.08#ibcon#about to read 5, iclass 35, count 2 2006.286.01:23:32.08#ibcon#read 5, iclass 35, count 2 2006.286.01:23:32.08#ibcon#about to read 6, iclass 35, count 2 2006.286.01:23:32.08#ibcon#read 6, iclass 35, count 2 2006.286.01:23:32.08#ibcon#end of sib2, iclass 35, count 2 2006.286.01:23:32.08#ibcon#*mode == 0, iclass 35, count 2 2006.286.01:23:32.08#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.01:23:32.08#ibcon#[25=AT02-06\r\n] 2006.286.01:23:32.08#ibcon#*before write, iclass 35, count 2 2006.286.01:23:32.08#ibcon#enter sib2, iclass 35, count 2 2006.286.01:23:32.08#ibcon#flushed, iclass 35, count 2 2006.286.01:23:32.08#ibcon#about to write, iclass 35, count 2 2006.286.01:23:32.08#ibcon#wrote, iclass 35, count 2 2006.286.01:23:32.08#ibcon#about to read 3, iclass 35, count 2 2006.286.01:23:32.11#ibcon#read 3, iclass 35, count 2 2006.286.01:23:32.11#ibcon#about to read 4, iclass 35, count 2 2006.286.01:23:32.11#ibcon#read 4, iclass 35, count 2 2006.286.01:23:32.11#ibcon#about to read 5, iclass 35, count 2 2006.286.01:23:32.11#ibcon#read 5, iclass 35, count 2 2006.286.01:23:32.11#ibcon#about to read 6, iclass 35, count 2 2006.286.01:23:32.11#ibcon#read 6, iclass 35, count 2 2006.286.01:23:32.11#ibcon#end of sib2, iclass 35, count 2 2006.286.01:23:32.11#ibcon#*after write, iclass 35, count 2 2006.286.01:23:32.11#ibcon#*before return 0, iclass 35, count 2 2006.286.01:23:32.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:23:32.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:23:32.11#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.01:23:32.11#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:32.11#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:23:32.23#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:23:32.23#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:23:32.23#ibcon#enter wrdev, iclass 35, count 0 2006.286.01:23:32.23#ibcon#first serial, iclass 35, count 0 2006.286.01:23:32.23#ibcon#enter sib2, iclass 35, count 0 2006.286.01:23:32.23#ibcon#flushed, iclass 35, count 0 2006.286.01:23:32.23#ibcon#about to write, iclass 35, count 0 2006.286.01:23:32.23#ibcon#wrote, iclass 35, count 0 2006.286.01:23:32.23#ibcon#about to read 3, iclass 35, count 0 2006.286.01:23:32.25#ibcon#read 3, iclass 35, count 0 2006.286.01:23:32.25#ibcon#about to read 4, iclass 35, count 0 2006.286.01:23:32.25#ibcon#read 4, iclass 35, count 0 2006.286.01:23:32.25#ibcon#about to read 5, iclass 35, count 0 2006.286.01:23:32.25#ibcon#read 5, iclass 35, count 0 2006.286.01:23:32.25#ibcon#about to read 6, iclass 35, count 0 2006.286.01:23:32.25#ibcon#read 6, iclass 35, count 0 2006.286.01:23:32.25#ibcon#end of sib2, iclass 35, count 0 2006.286.01:23:32.25#ibcon#*mode == 0, iclass 35, count 0 2006.286.01:23:32.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.01:23:32.25#ibcon#[25=USB\r\n] 2006.286.01:23:32.25#ibcon#*before write, iclass 35, count 0 2006.286.01:23:32.25#ibcon#enter sib2, iclass 35, count 0 2006.286.01:23:32.25#ibcon#flushed, iclass 35, count 0 2006.286.01:23:32.25#ibcon#about to write, iclass 35, count 0 2006.286.01:23:32.25#ibcon#wrote, iclass 35, count 0 2006.286.01:23:32.25#ibcon#about to read 3, iclass 35, count 0 2006.286.01:23:32.28#ibcon#read 3, iclass 35, count 0 2006.286.01:23:32.28#ibcon#about to read 4, iclass 35, count 0 2006.286.01:23:32.28#ibcon#read 4, iclass 35, count 0 2006.286.01:23:32.28#ibcon#about to read 5, iclass 35, count 0 2006.286.01:23:32.28#ibcon#read 5, iclass 35, count 0 2006.286.01:23:32.28#ibcon#about to read 6, iclass 35, count 0 2006.286.01:23:32.28#ibcon#read 6, iclass 35, count 0 2006.286.01:23:32.28#ibcon#end of sib2, iclass 35, count 0 2006.286.01:23:32.28#ibcon#*after write, iclass 35, count 0 2006.286.01:23:32.28#ibcon#*before return 0, iclass 35, count 0 2006.286.01:23:32.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:23:32.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:23:32.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.01:23:32.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.01:23:32.28$vck44/valo=3,564.99 2006.286.01:23:32.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.01:23:32.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.01:23:32.28#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:32.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:23:32.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:23:32.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:23:32.28#ibcon#enter wrdev, iclass 37, count 0 2006.286.01:23:32.28#ibcon#first serial, iclass 37, count 0 2006.286.01:23:32.28#ibcon#enter sib2, iclass 37, count 0 2006.286.01:23:32.28#ibcon#flushed, iclass 37, count 0 2006.286.01:23:32.28#ibcon#about to write, iclass 37, count 0 2006.286.01:23:32.28#ibcon#wrote, iclass 37, count 0 2006.286.01:23:32.28#ibcon#about to read 3, iclass 37, count 0 2006.286.01:23:32.30#ibcon#read 3, iclass 37, count 0 2006.286.01:23:32.30#ibcon#about to read 4, iclass 37, count 0 2006.286.01:23:32.30#ibcon#read 4, iclass 37, count 0 2006.286.01:23:32.30#ibcon#about to read 5, iclass 37, count 0 2006.286.01:23:32.30#ibcon#read 5, iclass 37, count 0 2006.286.01:23:32.30#ibcon#about to read 6, iclass 37, count 0 2006.286.01:23:32.30#ibcon#read 6, iclass 37, count 0 2006.286.01:23:32.30#ibcon#end of sib2, iclass 37, count 0 2006.286.01:23:32.30#ibcon#*mode == 0, iclass 37, count 0 2006.286.01:23:32.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.01:23:32.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:23:32.30#ibcon#*before write, iclass 37, count 0 2006.286.01:23:32.30#ibcon#enter sib2, iclass 37, count 0 2006.286.01:23:32.30#ibcon#flushed, iclass 37, count 0 2006.286.01:23:32.30#ibcon#about to write, iclass 37, count 0 2006.286.01:23:32.30#ibcon#wrote, iclass 37, count 0 2006.286.01:23:32.30#ibcon#about to read 3, iclass 37, count 0 2006.286.01:23:32.34#ibcon#read 3, iclass 37, count 0 2006.286.01:23:32.34#ibcon#about to read 4, iclass 37, count 0 2006.286.01:23:32.34#ibcon#read 4, iclass 37, count 0 2006.286.01:23:32.34#ibcon#about to read 5, iclass 37, count 0 2006.286.01:23:32.34#ibcon#read 5, iclass 37, count 0 2006.286.01:23:32.34#ibcon#about to read 6, iclass 37, count 0 2006.286.01:23:32.34#ibcon#read 6, iclass 37, count 0 2006.286.01:23:32.34#ibcon#end of sib2, iclass 37, count 0 2006.286.01:23:32.34#ibcon#*after write, iclass 37, count 0 2006.286.01:23:32.34#ibcon#*before return 0, iclass 37, count 0 2006.286.01:23:32.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:23:32.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:23:32.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.01:23:32.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.01:23:32.34$vck44/va=3,7 2006.286.01:23:32.34#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.01:23:32.34#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.01:23:32.34#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:32.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:23:32.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:23:32.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:23:32.40#ibcon#enter wrdev, iclass 39, count 2 2006.286.01:23:32.40#ibcon#first serial, iclass 39, count 2 2006.286.01:23:32.40#ibcon#enter sib2, iclass 39, count 2 2006.286.01:23:32.40#ibcon#flushed, iclass 39, count 2 2006.286.01:23:32.40#ibcon#about to write, iclass 39, count 2 2006.286.01:23:32.40#ibcon#wrote, iclass 39, count 2 2006.286.01:23:32.40#ibcon#about to read 3, iclass 39, count 2 2006.286.01:23:32.42#ibcon#read 3, iclass 39, count 2 2006.286.01:23:32.42#ibcon#about to read 4, iclass 39, count 2 2006.286.01:23:32.42#ibcon#read 4, iclass 39, count 2 2006.286.01:23:32.42#ibcon#about to read 5, iclass 39, count 2 2006.286.01:23:32.42#ibcon#read 5, iclass 39, count 2 2006.286.01:23:32.42#ibcon#about to read 6, iclass 39, count 2 2006.286.01:23:32.42#ibcon#read 6, iclass 39, count 2 2006.286.01:23:32.42#ibcon#end of sib2, iclass 39, count 2 2006.286.01:23:32.42#ibcon#*mode == 0, iclass 39, count 2 2006.286.01:23:32.42#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.01:23:32.42#ibcon#[25=AT03-07\r\n] 2006.286.01:23:32.42#ibcon#*before write, iclass 39, count 2 2006.286.01:23:32.42#ibcon#enter sib2, iclass 39, count 2 2006.286.01:23:32.42#ibcon#flushed, iclass 39, count 2 2006.286.01:23:32.42#ibcon#about to write, iclass 39, count 2 2006.286.01:23:32.42#ibcon#wrote, iclass 39, count 2 2006.286.01:23:32.42#ibcon#about to read 3, iclass 39, count 2 2006.286.01:23:32.45#ibcon#read 3, iclass 39, count 2 2006.286.01:23:32.45#ibcon#about to read 4, iclass 39, count 2 2006.286.01:23:32.45#ibcon#read 4, iclass 39, count 2 2006.286.01:23:32.45#ibcon#about to read 5, iclass 39, count 2 2006.286.01:23:32.45#ibcon#read 5, iclass 39, count 2 2006.286.01:23:32.45#ibcon#about to read 6, iclass 39, count 2 2006.286.01:23:32.45#ibcon#read 6, iclass 39, count 2 2006.286.01:23:32.45#ibcon#end of sib2, iclass 39, count 2 2006.286.01:23:32.45#ibcon#*after write, iclass 39, count 2 2006.286.01:23:32.45#ibcon#*before return 0, iclass 39, count 2 2006.286.01:23:32.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:23:32.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:23:32.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.01:23:32.45#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:32.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:23:32.57#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:23:32.57#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:23:32.57#ibcon#enter wrdev, iclass 39, count 0 2006.286.01:23:32.57#ibcon#first serial, iclass 39, count 0 2006.286.01:23:32.57#ibcon#enter sib2, iclass 39, count 0 2006.286.01:23:32.57#ibcon#flushed, iclass 39, count 0 2006.286.01:23:32.57#ibcon#about to write, iclass 39, count 0 2006.286.01:23:32.57#ibcon#wrote, iclass 39, count 0 2006.286.01:23:32.57#ibcon#about to read 3, iclass 39, count 0 2006.286.01:23:32.59#ibcon#read 3, iclass 39, count 0 2006.286.01:23:32.59#ibcon#about to read 4, iclass 39, count 0 2006.286.01:23:32.59#ibcon#read 4, iclass 39, count 0 2006.286.01:23:32.59#ibcon#about to read 5, iclass 39, count 0 2006.286.01:23:32.59#ibcon#read 5, iclass 39, count 0 2006.286.01:23:32.59#ibcon#about to read 6, iclass 39, count 0 2006.286.01:23:32.59#ibcon#read 6, iclass 39, count 0 2006.286.01:23:32.59#ibcon#end of sib2, iclass 39, count 0 2006.286.01:23:32.59#ibcon#*mode == 0, iclass 39, count 0 2006.286.01:23:32.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.01:23:32.59#ibcon#[25=USB\r\n] 2006.286.01:23:32.59#ibcon#*before write, iclass 39, count 0 2006.286.01:23:32.59#ibcon#enter sib2, iclass 39, count 0 2006.286.01:23:32.59#ibcon#flushed, iclass 39, count 0 2006.286.01:23:32.59#ibcon#about to write, iclass 39, count 0 2006.286.01:23:32.59#ibcon#wrote, iclass 39, count 0 2006.286.01:23:32.59#ibcon#about to read 3, iclass 39, count 0 2006.286.01:23:32.62#ibcon#read 3, iclass 39, count 0 2006.286.01:23:32.62#ibcon#about to read 4, iclass 39, count 0 2006.286.01:23:32.62#ibcon#read 4, iclass 39, count 0 2006.286.01:23:32.62#ibcon#about to read 5, iclass 39, count 0 2006.286.01:23:32.62#ibcon#read 5, iclass 39, count 0 2006.286.01:23:32.62#ibcon#about to read 6, iclass 39, count 0 2006.286.01:23:32.62#ibcon#read 6, iclass 39, count 0 2006.286.01:23:32.62#ibcon#end of sib2, iclass 39, count 0 2006.286.01:23:32.62#ibcon#*after write, iclass 39, count 0 2006.286.01:23:32.62#ibcon#*before return 0, iclass 39, count 0 2006.286.01:23:32.62#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:23:32.62#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:23:32.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.01:23:32.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.01:23:32.62$vck44/valo=4,624.99 2006.286.01:23:32.62#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.01:23:32.62#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.01:23:32.62#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:32.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:23:32.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:23:32.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:23:32.62#ibcon#enter wrdev, iclass 3, count 0 2006.286.01:23:32.62#ibcon#first serial, iclass 3, count 0 2006.286.01:23:32.62#ibcon#enter sib2, iclass 3, count 0 2006.286.01:23:32.62#ibcon#flushed, iclass 3, count 0 2006.286.01:23:32.62#ibcon#about to write, iclass 3, count 0 2006.286.01:23:32.62#ibcon#wrote, iclass 3, count 0 2006.286.01:23:32.62#ibcon#about to read 3, iclass 3, count 0 2006.286.01:23:32.64#ibcon#read 3, iclass 3, count 0 2006.286.01:23:32.64#ibcon#about to read 4, iclass 3, count 0 2006.286.01:23:32.64#ibcon#read 4, iclass 3, count 0 2006.286.01:23:32.64#ibcon#about to read 5, iclass 3, count 0 2006.286.01:23:32.64#ibcon#read 5, iclass 3, count 0 2006.286.01:23:32.64#ibcon#about to read 6, iclass 3, count 0 2006.286.01:23:32.64#ibcon#read 6, iclass 3, count 0 2006.286.01:23:32.64#ibcon#end of sib2, iclass 3, count 0 2006.286.01:23:32.64#ibcon#*mode == 0, iclass 3, count 0 2006.286.01:23:32.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.01:23:32.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:23:32.64#ibcon#*before write, iclass 3, count 0 2006.286.01:23:32.64#ibcon#enter sib2, iclass 3, count 0 2006.286.01:23:32.64#ibcon#flushed, iclass 3, count 0 2006.286.01:23:32.64#ibcon#about to write, iclass 3, count 0 2006.286.01:23:32.64#ibcon#wrote, iclass 3, count 0 2006.286.01:23:32.64#ibcon#about to read 3, iclass 3, count 0 2006.286.01:23:32.68#ibcon#read 3, iclass 3, count 0 2006.286.01:23:32.68#ibcon#about to read 4, iclass 3, count 0 2006.286.01:23:32.68#ibcon#read 4, iclass 3, count 0 2006.286.01:23:32.68#ibcon#about to read 5, iclass 3, count 0 2006.286.01:23:32.68#ibcon#read 5, iclass 3, count 0 2006.286.01:23:32.68#ibcon#about to read 6, iclass 3, count 0 2006.286.01:23:32.68#ibcon#read 6, iclass 3, count 0 2006.286.01:23:32.68#ibcon#end of sib2, iclass 3, count 0 2006.286.01:23:32.68#ibcon#*after write, iclass 3, count 0 2006.286.01:23:32.68#ibcon#*before return 0, iclass 3, count 0 2006.286.01:23:32.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:23:32.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:23:32.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.01:23:32.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.01:23:32.68$vck44/va=4,6 2006.286.01:23:32.68#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.01:23:32.68#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.01:23:32.68#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:32.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:23:32.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:23:32.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:23:32.74#ibcon#enter wrdev, iclass 5, count 2 2006.286.01:23:32.74#ibcon#first serial, iclass 5, count 2 2006.286.01:23:32.74#ibcon#enter sib2, iclass 5, count 2 2006.286.01:23:32.74#ibcon#flushed, iclass 5, count 2 2006.286.01:23:32.74#ibcon#about to write, iclass 5, count 2 2006.286.01:23:32.74#ibcon#wrote, iclass 5, count 2 2006.286.01:23:32.74#ibcon#about to read 3, iclass 5, count 2 2006.286.01:23:32.76#ibcon#read 3, iclass 5, count 2 2006.286.01:23:32.76#ibcon#about to read 4, iclass 5, count 2 2006.286.01:23:32.76#ibcon#read 4, iclass 5, count 2 2006.286.01:23:32.76#ibcon#about to read 5, iclass 5, count 2 2006.286.01:23:32.76#ibcon#read 5, iclass 5, count 2 2006.286.01:23:32.76#ibcon#about to read 6, iclass 5, count 2 2006.286.01:23:32.76#ibcon#read 6, iclass 5, count 2 2006.286.01:23:32.76#ibcon#end of sib2, iclass 5, count 2 2006.286.01:23:32.76#ibcon#*mode == 0, iclass 5, count 2 2006.286.01:23:32.76#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.01:23:32.76#ibcon#[25=AT04-06\r\n] 2006.286.01:23:32.76#ibcon#*before write, iclass 5, count 2 2006.286.01:23:32.76#ibcon#enter sib2, iclass 5, count 2 2006.286.01:23:32.76#ibcon#flushed, iclass 5, count 2 2006.286.01:23:32.76#ibcon#about to write, iclass 5, count 2 2006.286.01:23:32.76#ibcon#wrote, iclass 5, count 2 2006.286.01:23:32.76#ibcon#about to read 3, iclass 5, count 2 2006.286.01:23:32.79#ibcon#read 3, iclass 5, count 2 2006.286.01:23:32.79#ibcon#about to read 4, iclass 5, count 2 2006.286.01:23:32.79#ibcon#read 4, iclass 5, count 2 2006.286.01:23:32.79#ibcon#about to read 5, iclass 5, count 2 2006.286.01:23:32.79#ibcon#read 5, iclass 5, count 2 2006.286.01:23:32.79#ibcon#about to read 6, iclass 5, count 2 2006.286.01:23:32.79#ibcon#read 6, iclass 5, count 2 2006.286.01:23:32.79#ibcon#end of sib2, iclass 5, count 2 2006.286.01:23:32.79#ibcon#*after write, iclass 5, count 2 2006.286.01:23:32.79#ibcon#*before return 0, iclass 5, count 2 2006.286.01:23:32.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:23:32.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:23:32.79#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.01:23:32.79#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:32.79#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:23:32.91#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:23:32.91#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:23:32.91#ibcon#enter wrdev, iclass 5, count 0 2006.286.01:23:32.91#ibcon#first serial, iclass 5, count 0 2006.286.01:23:32.91#ibcon#enter sib2, iclass 5, count 0 2006.286.01:23:32.91#ibcon#flushed, iclass 5, count 0 2006.286.01:23:32.91#ibcon#about to write, iclass 5, count 0 2006.286.01:23:32.91#ibcon#wrote, iclass 5, count 0 2006.286.01:23:32.91#ibcon#about to read 3, iclass 5, count 0 2006.286.01:23:32.93#ibcon#read 3, iclass 5, count 0 2006.286.01:23:32.93#ibcon#about to read 4, iclass 5, count 0 2006.286.01:23:32.93#ibcon#read 4, iclass 5, count 0 2006.286.01:23:32.93#ibcon#about to read 5, iclass 5, count 0 2006.286.01:23:32.93#ibcon#read 5, iclass 5, count 0 2006.286.01:23:32.93#ibcon#about to read 6, iclass 5, count 0 2006.286.01:23:32.93#ibcon#read 6, iclass 5, count 0 2006.286.01:23:32.93#ibcon#end of sib2, iclass 5, count 0 2006.286.01:23:32.93#ibcon#*mode == 0, iclass 5, count 0 2006.286.01:23:32.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.01:23:32.93#ibcon#[25=USB\r\n] 2006.286.01:23:32.93#ibcon#*before write, iclass 5, count 0 2006.286.01:23:32.93#ibcon#enter sib2, iclass 5, count 0 2006.286.01:23:32.93#ibcon#flushed, iclass 5, count 0 2006.286.01:23:32.93#ibcon#about to write, iclass 5, count 0 2006.286.01:23:32.93#ibcon#wrote, iclass 5, count 0 2006.286.01:23:32.93#ibcon#about to read 3, iclass 5, count 0 2006.286.01:23:32.96#ibcon#read 3, iclass 5, count 0 2006.286.01:23:32.96#ibcon#about to read 4, iclass 5, count 0 2006.286.01:23:32.96#ibcon#read 4, iclass 5, count 0 2006.286.01:23:32.96#ibcon#about to read 5, iclass 5, count 0 2006.286.01:23:32.96#ibcon#read 5, iclass 5, count 0 2006.286.01:23:32.96#ibcon#about to read 6, iclass 5, count 0 2006.286.01:23:32.96#ibcon#read 6, iclass 5, count 0 2006.286.01:23:32.96#ibcon#end of sib2, iclass 5, count 0 2006.286.01:23:32.96#ibcon#*after write, iclass 5, count 0 2006.286.01:23:32.96#ibcon#*before return 0, iclass 5, count 0 2006.286.01:23:32.96#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:23:32.96#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:23:32.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.01:23:32.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.01:23:32.96$vck44/valo=5,734.99 2006.286.01:23:32.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.01:23:32.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.01:23:32.96#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:32.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:23:32.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:23:32.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:23:32.96#ibcon#enter wrdev, iclass 7, count 0 2006.286.01:23:32.96#ibcon#first serial, iclass 7, count 0 2006.286.01:23:32.96#ibcon#enter sib2, iclass 7, count 0 2006.286.01:23:32.96#ibcon#flushed, iclass 7, count 0 2006.286.01:23:32.96#ibcon#about to write, iclass 7, count 0 2006.286.01:23:32.96#ibcon#wrote, iclass 7, count 0 2006.286.01:23:32.96#ibcon#about to read 3, iclass 7, count 0 2006.286.01:23:32.98#ibcon#read 3, iclass 7, count 0 2006.286.01:23:32.98#ibcon#about to read 4, iclass 7, count 0 2006.286.01:23:32.98#ibcon#read 4, iclass 7, count 0 2006.286.01:23:32.98#ibcon#about to read 5, iclass 7, count 0 2006.286.01:23:32.98#ibcon#read 5, iclass 7, count 0 2006.286.01:23:32.98#ibcon#about to read 6, iclass 7, count 0 2006.286.01:23:32.98#ibcon#read 6, iclass 7, count 0 2006.286.01:23:32.98#ibcon#end of sib2, iclass 7, count 0 2006.286.01:23:32.98#ibcon#*mode == 0, iclass 7, count 0 2006.286.01:23:32.98#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.01:23:32.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:23:32.98#ibcon#*before write, iclass 7, count 0 2006.286.01:23:32.98#ibcon#enter sib2, iclass 7, count 0 2006.286.01:23:32.98#ibcon#flushed, iclass 7, count 0 2006.286.01:23:32.98#ibcon#about to write, iclass 7, count 0 2006.286.01:23:32.98#ibcon#wrote, iclass 7, count 0 2006.286.01:23:32.98#ibcon#about to read 3, iclass 7, count 0 2006.286.01:23:33.02#ibcon#read 3, iclass 7, count 0 2006.286.01:23:33.02#ibcon#about to read 4, iclass 7, count 0 2006.286.01:23:33.02#ibcon#read 4, iclass 7, count 0 2006.286.01:23:33.02#ibcon#about to read 5, iclass 7, count 0 2006.286.01:23:33.02#ibcon#read 5, iclass 7, count 0 2006.286.01:23:33.02#ibcon#about to read 6, iclass 7, count 0 2006.286.01:23:33.02#ibcon#read 6, iclass 7, count 0 2006.286.01:23:33.02#ibcon#end of sib2, iclass 7, count 0 2006.286.01:23:33.02#ibcon#*after write, iclass 7, count 0 2006.286.01:23:33.02#ibcon#*before return 0, iclass 7, count 0 2006.286.01:23:33.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:23:33.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:23:33.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.01:23:33.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.01:23:33.02$vck44/va=5,3 2006.286.01:23:33.02#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.01:23:33.02#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.01:23:33.02#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:33.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:23:33.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:23:33.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:23:33.08#ibcon#enter wrdev, iclass 11, count 2 2006.286.01:23:33.08#ibcon#first serial, iclass 11, count 2 2006.286.01:23:33.08#ibcon#enter sib2, iclass 11, count 2 2006.286.01:23:33.08#ibcon#flushed, iclass 11, count 2 2006.286.01:23:33.08#ibcon#about to write, iclass 11, count 2 2006.286.01:23:33.08#ibcon#wrote, iclass 11, count 2 2006.286.01:23:33.08#ibcon#about to read 3, iclass 11, count 2 2006.286.01:23:33.10#ibcon#read 3, iclass 11, count 2 2006.286.01:23:33.10#ibcon#about to read 4, iclass 11, count 2 2006.286.01:23:33.10#ibcon#read 4, iclass 11, count 2 2006.286.01:23:33.10#ibcon#about to read 5, iclass 11, count 2 2006.286.01:23:33.10#ibcon#read 5, iclass 11, count 2 2006.286.01:23:33.10#ibcon#about to read 6, iclass 11, count 2 2006.286.01:23:33.10#ibcon#read 6, iclass 11, count 2 2006.286.01:23:33.10#ibcon#end of sib2, iclass 11, count 2 2006.286.01:23:33.10#ibcon#*mode == 0, iclass 11, count 2 2006.286.01:23:33.10#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.01:23:33.10#ibcon#[25=AT05-03\r\n] 2006.286.01:23:33.10#ibcon#*before write, iclass 11, count 2 2006.286.01:23:33.10#ibcon#enter sib2, iclass 11, count 2 2006.286.01:23:33.10#ibcon#flushed, iclass 11, count 2 2006.286.01:23:33.10#ibcon#about to write, iclass 11, count 2 2006.286.01:23:33.10#ibcon#wrote, iclass 11, count 2 2006.286.01:23:33.10#ibcon#about to read 3, iclass 11, count 2 2006.286.01:23:33.13#ibcon#read 3, iclass 11, count 2 2006.286.01:23:33.13#ibcon#about to read 4, iclass 11, count 2 2006.286.01:23:33.13#ibcon#read 4, iclass 11, count 2 2006.286.01:23:33.13#ibcon#about to read 5, iclass 11, count 2 2006.286.01:23:33.13#ibcon#read 5, iclass 11, count 2 2006.286.01:23:33.13#ibcon#about to read 6, iclass 11, count 2 2006.286.01:23:33.13#ibcon#read 6, iclass 11, count 2 2006.286.01:23:33.13#ibcon#end of sib2, iclass 11, count 2 2006.286.01:23:33.13#ibcon#*after write, iclass 11, count 2 2006.286.01:23:33.13#ibcon#*before return 0, iclass 11, count 2 2006.286.01:23:33.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:23:33.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:23:33.13#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.01:23:33.13#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:33.13#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:23:33.25#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:23:33.25#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:23:33.25#ibcon#enter wrdev, iclass 11, count 0 2006.286.01:23:33.25#ibcon#first serial, iclass 11, count 0 2006.286.01:23:33.25#ibcon#enter sib2, iclass 11, count 0 2006.286.01:23:33.25#ibcon#flushed, iclass 11, count 0 2006.286.01:23:33.25#ibcon#about to write, iclass 11, count 0 2006.286.01:23:33.25#ibcon#wrote, iclass 11, count 0 2006.286.01:23:33.25#ibcon#about to read 3, iclass 11, count 0 2006.286.01:23:33.27#ibcon#read 3, iclass 11, count 0 2006.286.01:23:33.27#ibcon#about to read 4, iclass 11, count 0 2006.286.01:23:33.27#ibcon#read 4, iclass 11, count 0 2006.286.01:23:33.27#ibcon#about to read 5, iclass 11, count 0 2006.286.01:23:33.27#ibcon#read 5, iclass 11, count 0 2006.286.01:23:33.27#ibcon#about to read 6, iclass 11, count 0 2006.286.01:23:33.27#ibcon#read 6, iclass 11, count 0 2006.286.01:23:33.27#ibcon#end of sib2, iclass 11, count 0 2006.286.01:23:33.27#ibcon#*mode == 0, iclass 11, count 0 2006.286.01:23:33.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.01:23:33.27#ibcon#[25=USB\r\n] 2006.286.01:23:33.27#ibcon#*before write, iclass 11, count 0 2006.286.01:23:33.27#ibcon#enter sib2, iclass 11, count 0 2006.286.01:23:33.27#ibcon#flushed, iclass 11, count 0 2006.286.01:23:33.27#ibcon#about to write, iclass 11, count 0 2006.286.01:23:33.27#ibcon#wrote, iclass 11, count 0 2006.286.01:23:33.27#ibcon#about to read 3, iclass 11, count 0 2006.286.01:23:33.30#ibcon#read 3, iclass 11, count 0 2006.286.01:23:33.30#ibcon#about to read 4, iclass 11, count 0 2006.286.01:23:33.30#ibcon#read 4, iclass 11, count 0 2006.286.01:23:33.30#ibcon#about to read 5, iclass 11, count 0 2006.286.01:23:33.30#ibcon#read 5, iclass 11, count 0 2006.286.01:23:33.30#ibcon#about to read 6, iclass 11, count 0 2006.286.01:23:33.30#ibcon#read 6, iclass 11, count 0 2006.286.01:23:33.30#ibcon#end of sib2, iclass 11, count 0 2006.286.01:23:33.30#ibcon#*after write, iclass 11, count 0 2006.286.01:23:33.30#ibcon#*before return 0, iclass 11, count 0 2006.286.01:23:33.30#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:23:33.30#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:23:33.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.01:23:33.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.01:23:33.30$vck44/valo=6,814.99 2006.286.01:23:33.30#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.01:23:33.30#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.01:23:33.30#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:33.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:23:33.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:23:33.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:23:33.30#ibcon#enter wrdev, iclass 13, count 0 2006.286.01:23:33.30#ibcon#first serial, iclass 13, count 0 2006.286.01:23:33.30#ibcon#enter sib2, iclass 13, count 0 2006.286.01:23:33.30#ibcon#flushed, iclass 13, count 0 2006.286.01:23:33.30#ibcon#about to write, iclass 13, count 0 2006.286.01:23:33.30#ibcon#wrote, iclass 13, count 0 2006.286.01:23:33.30#ibcon#about to read 3, iclass 13, count 0 2006.286.01:23:33.32#ibcon#read 3, iclass 13, count 0 2006.286.01:23:33.32#ibcon#about to read 4, iclass 13, count 0 2006.286.01:23:33.32#ibcon#read 4, iclass 13, count 0 2006.286.01:23:33.32#ibcon#about to read 5, iclass 13, count 0 2006.286.01:23:33.32#ibcon#read 5, iclass 13, count 0 2006.286.01:23:33.32#ibcon#about to read 6, iclass 13, count 0 2006.286.01:23:33.32#ibcon#read 6, iclass 13, count 0 2006.286.01:23:33.32#ibcon#end of sib2, iclass 13, count 0 2006.286.01:23:33.32#ibcon#*mode == 0, iclass 13, count 0 2006.286.01:23:33.32#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.01:23:33.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:23:33.32#ibcon#*before write, iclass 13, count 0 2006.286.01:23:33.32#ibcon#enter sib2, iclass 13, count 0 2006.286.01:23:33.32#ibcon#flushed, iclass 13, count 0 2006.286.01:23:33.32#ibcon#about to write, iclass 13, count 0 2006.286.01:23:33.32#ibcon#wrote, iclass 13, count 0 2006.286.01:23:33.32#ibcon#about to read 3, iclass 13, count 0 2006.286.01:23:33.36#ibcon#read 3, iclass 13, count 0 2006.286.01:23:33.36#ibcon#about to read 4, iclass 13, count 0 2006.286.01:23:33.36#ibcon#read 4, iclass 13, count 0 2006.286.01:23:33.36#ibcon#about to read 5, iclass 13, count 0 2006.286.01:23:33.36#ibcon#read 5, iclass 13, count 0 2006.286.01:23:33.36#ibcon#about to read 6, iclass 13, count 0 2006.286.01:23:33.36#ibcon#read 6, iclass 13, count 0 2006.286.01:23:33.36#ibcon#end of sib2, iclass 13, count 0 2006.286.01:23:33.36#ibcon#*after write, iclass 13, count 0 2006.286.01:23:33.36#ibcon#*before return 0, iclass 13, count 0 2006.286.01:23:33.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:23:33.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:23:33.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.01:23:33.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.01:23:33.36$vck44/va=6,4 2006.286.01:23:33.36#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.01:23:33.36#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.01:23:33.36#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:33.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:23:33.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:23:33.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:23:33.42#ibcon#enter wrdev, iclass 15, count 2 2006.286.01:23:33.42#ibcon#first serial, iclass 15, count 2 2006.286.01:23:33.42#ibcon#enter sib2, iclass 15, count 2 2006.286.01:23:33.42#ibcon#flushed, iclass 15, count 2 2006.286.01:23:33.42#ibcon#about to write, iclass 15, count 2 2006.286.01:23:33.42#ibcon#wrote, iclass 15, count 2 2006.286.01:23:33.42#ibcon#about to read 3, iclass 15, count 2 2006.286.01:23:33.44#ibcon#read 3, iclass 15, count 2 2006.286.01:23:33.44#ibcon#about to read 4, iclass 15, count 2 2006.286.01:23:33.44#ibcon#read 4, iclass 15, count 2 2006.286.01:23:33.44#ibcon#about to read 5, iclass 15, count 2 2006.286.01:23:33.44#ibcon#read 5, iclass 15, count 2 2006.286.01:23:33.44#ibcon#about to read 6, iclass 15, count 2 2006.286.01:23:33.44#ibcon#read 6, iclass 15, count 2 2006.286.01:23:33.44#ibcon#end of sib2, iclass 15, count 2 2006.286.01:23:33.44#ibcon#*mode == 0, iclass 15, count 2 2006.286.01:23:33.44#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.01:23:33.44#ibcon#[25=AT06-04\r\n] 2006.286.01:23:33.44#ibcon#*before write, iclass 15, count 2 2006.286.01:23:33.44#ibcon#enter sib2, iclass 15, count 2 2006.286.01:23:33.44#ibcon#flushed, iclass 15, count 2 2006.286.01:23:33.44#ibcon#about to write, iclass 15, count 2 2006.286.01:23:33.44#ibcon#wrote, iclass 15, count 2 2006.286.01:23:33.44#ibcon#about to read 3, iclass 15, count 2 2006.286.01:23:33.47#ibcon#read 3, iclass 15, count 2 2006.286.01:23:33.47#ibcon#about to read 4, iclass 15, count 2 2006.286.01:23:33.47#ibcon#read 4, iclass 15, count 2 2006.286.01:23:33.47#ibcon#about to read 5, iclass 15, count 2 2006.286.01:23:33.47#ibcon#read 5, iclass 15, count 2 2006.286.01:23:33.47#ibcon#about to read 6, iclass 15, count 2 2006.286.01:23:33.47#ibcon#read 6, iclass 15, count 2 2006.286.01:23:33.47#ibcon#end of sib2, iclass 15, count 2 2006.286.01:23:33.47#ibcon#*after write, iclass 15, count 2 2006.286.01:23:33.47#ibcon#*before return 0, iclass 15, count 2 2006.286.01:23:33.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:23:33.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:23:33.47#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.01:23:33.47#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:33.47#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:23:33.59#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:23:33.59#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:23:33.59#ibcon#enter wrdev, iclass 15, count 0 2006.286.01:23:33.59#ibcon#first serial, iclass 15, count 0 2006.286.01:23:33.59#ibcon#enter sib2, iclass 15, count 0 2006.286.01:23:33.59#ibcon#flushed, iclass 15, count 0 2006.286.01:23:33.59#ibcon#about to write, iclass 15, count 0 2006.286.01:23:33.59#ibcon#wrote, iclass 15, count 0 2006.286.01:23:33.59#ibcon#about to read 3, iclass 15, count 0 2006.286.01:23:33.61#ibcon#read 3, iclass 15, count 0 2006.286.01:23:33.61#ibcon#about to read 4, iclass 15, count 0 2006.286.01:23:33.61#ibcon#read 4, iclass 15, count 0 2006.286.01:23:33.61#ibcon#about to read 5, iclass 15, count 0 2006.286.01:23:33.61#ibcon#read 5, iclass 15, count 0 2006.286.01:23:33.61#ibcon#about to read 6, iclass 15, count 0 2006.286.01:23:33.61#ibcon#read 6, iclass 15, count 0 2006.286.01:23:33.61#ibcon#end of sib2, iclass 15, count 0 2006.286.01:23:33.61#ibcon#*mode == 0, iclass 15, count 0 2006.286.01:23:33.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.01:23:33.61#ibcon#[25=USB\r\n] 2006.286.01:23:33.61#ibcon#*before write, iclass 15, count 0 2006.286.01:23:33.61#ibcon#enter sib2, iclass 15, count 0 2006.286.01:23:33.61#ibcon#flushed, iclass 15, count 0 2006.286.01:23:33.61#ibcon#about to write, iclass 15, count 0 2006.286.01:23:33.61#ibcon#wrote, iclass 15, count 0 2006.286.01:23:33.61#ibcon#about to read 3, iclass 15, count 0 2006.286.01:23:33.64#ibcon#read 3, iclass 15, count 0 2006.286.01:23:33.64#ibcon#about to read 4, iclass 15, count 0 2006.286.01:23:33.64#ibcon#read 4, iclass 15, count 0 2006.286.01:23:33.64#ibcon#about to read 5, iclass 15, count 0 2006.286.01:23:33.64#ibcon#read 5, iclass 15, count 0 2006.286.01:23:33.64#ibcon#about to read 6, iclass 15, count 0 2006.286.01:23:33.64#ibcon#read 6, iclass 15, count 0 2006.286.01:23:33.64#ibcon#end of sib2, iclass 15, count 0 2006.286.01:23:33.64#ibcon#*after write, iclass 15, count 0 2006.286.01:23:33.64#ibcon#*before return 0, iclass 15, count 0 2006.286.01:23:33.64#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:23:33.64#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:23:33.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.01:23:33.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.01:23:33.64$vck44/valo=7,864.99 2006.286.01:23:33.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.01:23:33.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.01:23:33.64#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:33.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:23:33.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:23:33.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:23:33.64#ibcon#enter wrdev, iclass 17, count 0 2006.286.01:23:33.64#ibcon#first serial, iclass 17, count 0 2006.286.01:23:33.64#ibcon#enter sib2, iclass 17, count 0 2006.286.01:23:33.64#ibcon#flushed, iclass 17, count 0 2006.286.01:23:33.64#ibcon#about to write, iclass 17, count 0 2006.286.01:23:33.64#ibcon#wrote, iclass 17, count 0 2006.286.01:23:33.64#ibcon#about to read 3, iclass 17, count 0 2006.286.01:23:33.66#ibcon#read 3, iclass 17, count 0 2006.286.01:23:33.66#ibcon#about to read 4, iclass 17, count 0 2006.286.01:23:33.66#ibcon#read 4, iclass 17, count 0 2006.286.01:23:33.66#ibcon#about to read 5, iclass 17, count 0 2006.286.01:23:33.66#ibcon#read 5, iclass 17, count 0 2006.286.01:23:33.66#ibcon#about to read 6, iclass 17, count 0 2006.286.01:23:33.66#ibcon#read 6, iclass 17, count 0 2006.286.01:23:33.66#ibcon#end of sib2, iclass 17, count 0 2006.286.01:23:33.66#ibcon#*mode == 0, iclass 17, count 0 2006.286.01:23:33.66#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.01:23:33.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:23:33.66#ibcon#*before write, iclass 17, count 0 2006.286.01:23:33.66#ibcon#enter sib2, iclass 17, count 0 2006.286.01:23:33.66#ibcon#flushed, iclass 17, count 0 2006.286.01:23:33.66#ibcon#about to write, iclass 17, count 0 2006.286.01:23:33.66#ibcon#wrote, iclass 17, count 0 2006.286.01:23:33.66#ibcon#about to read 3, iclass 17, count 0 2006.286.01:23:33.70#ibcon#read 3, iclass 17, count 0 2006.286.01:23:33.70#ibcon#about to read 4, iclass 17, count 0 2006.286.01:23:33.70#ibcon#read 4, iclass 17, count 0 2006.286.01:23:33.70#ibcon#about to read 5, iclass 17, count 0 2006.286.01:23:33.70#ibcon#read 5, iclass 17, count 0 2006.286.01:23:33.70#ibcon#about to read 6, iclass 17, count 0 2006.286.01:23:33.70#ibcon#read 6, iclass 17, count 0 2006.286.01:23:33.70#ibcon#end of sib2, iclass 17, count 0 2006.286.01:23:33.70#ibcon#*after write, iclass 17, count 0 2006.286.01:23:33.70#ibcon#*before return 0, iclass 17, count 0 2006.286.01:23:33.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:23:33.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:23:33.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.01:23:33.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.01:23:33.70$vck44/va=7,4 2006.286.01:23:33.70#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.01:23:33.70#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.01:23:33.70#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:33.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:23:33.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:23:33.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:23:33.76#ibcon#enter wrdev, iclass 19, count 2 2006.286.01:23:33.76#ibcon#first serial, iclass 19, count 2 2006.286.01:23:33.76#ibcon#enter sib2, iclass 19, count 2 2006.286.01:23:33.76#ibcon#flushed, iclass 19, count 2 2006.286.01:23:33.76#ibcon#about to write, iclass 19, count 2 2006.286.01:23:33.76#ibcon#wrote, iclass 19, count 2 2006.286.01:23:33.76#ibcon#about to read 3, iclass 19, count 2 2006.286.01:23:33.78#ibcon#read 3, iclass 19, count 2 2006.286.01:23:33.78#ibcon#about to read 4, iclass 19, count 2 2006.286.01:23:33.78#ibcon#read 4, iclass 19, count 2 2006.286.01:23:33.78#ibcon#about to read 5, iclass 19, count 2 2006.286.01:23:33.78#ibcon#read 5, iclass 19, count 2 2006.286.01:23:33.78#ibcon#about to read 6, iclass 19, count 2 2006.286.01:23:33.78#ibcon#read 6, iclass 19, count 2 2006.286.01:23:33.78#ibcon#end of sib2, iclass 19, count 2 2006.286.01:23:33.78#ibcon#*mode == 0, iclass 19, count 2 2006.286.01:23:33.78#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.01:23:33.78#ibcon#[25=AT07-04\r\n] 2006.286.01:23:33.78#ibcon#*before write, iclass 19, count 2 2006.286.01:23:33.78#ibcon#enter sib2, iclass 19, count 2 2006.286.01:23:33.78#ibcon#flushed, iclass 19, count 2 2006.286.01:23:33.78#ibcon#about to write, iclass 19, count 2 2006.286.01:23:33.78#ibcon#wrote, iclass 19, count 2 2006.286.01:23:33.78#ibcon#about to read 3, iclass 19, count 2 2006.286.01:23:33.81#ibcon#read 3, iclass 19, count 2 2006.286.01:23:33.81#ibcon#about to read 4, iclass 19, count 2 2006.286.01:23:33.81#ibcon#read 4, iclass 19, count 2 2006.286.01:23:33.81#ibcon#about to read 5, iclass 19, count 2 2006.286.01:23:33.81#ibcon#read 5, iclass 19, count 2 2006.286.01:23:33.81#ibcon#about to read 6, iclass 19, count 2 2006.286.01:23:33.81#ibcon#read 6, iclass 19, count 2 2006.286.01:23:33.81#ibcon#end of sib2, iclass 19, count 2 2006.286.01:23:33.81#ibcon#*after write, iclass 19, count 2 2006.286.01:23:33.81#ibcon#*before return 0, iclass 19, count 2 2006.286.01:23:33.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:23:33.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:23:33.81#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.01:23:33.81#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:33.81#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:23:33.93#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:23:33.93#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:23:33.93#ibcon#enter wrdev, iclass 19, count 0 2006.286.01:23:33.93#ibcon#first serial, iclass 19, count 0 2006.286.01:23:33.93#ibcon#enter sib2, iclass 19, count 0 2006.286.01:23:33.93#ibcon#flushed, iclass 19, count 0 2006.286.01:23:33.93#ibcon#about to write, iclass 19, count 0 2006.286.01:23:33.93#ibcon#wrote, iclass 19, count 0 2006.286.01:23:33.93#ibcon#about to read 3, iclass 19, count 0 2006.286.01:23:33.95#ibcon#read 3, iclass 19, count 0 2006.286.01:23:33.95#ibcon#about to read 4, iclass 19, count 0 2006.286.01:23:33.95#ibcon#read 4, iclass 19, count 0 2006.286.01:23:33.95#ibcon#about to read 5, iclass 19, count 0 2006.286.01:23:33.95#ibcon#read 5, iclass 19, count 0 2006.286.01:23:33.95#ibcon#about to read 6, iclass 19, count 0 2006.286.01:23:33.95#ibcon#read 6, iclass 19, count 0 2006.286.01:23:33.95#ibcon#end of sib2, iclass 19, count 0 2006.286.01:23:33.95#ibcon#*mode == 0, iclass 19, count 0 2006.286.01:23:33.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.01:23:33.95#ibcon#[25=USB\r\n] 2006.286.01:23:33.95#ibcon#*before write, iclass 19, count 0 2006.286.01:23:33.95#ibcon#enter sib2, iclass 19, count 0 2006.286.01:23:33.95#ibcon#flushed, iclass 19, count 0 2006.286.01:23:33.95#ibcon#about to write, iclass 19, count 0 2006.286.01:23:33.95#ibcon#wrote, iclass 19, count 0 2006.286.01:23:33.95#ibcon#about to read 3, iclass 19, count 0 2006.286.01:23:33.98#ibcon#read 3, iclass 19, count 0 2006.286.01:23:33.98#ibcon#about to read 4, iclass 19, count 0 2006.286.01:23:33.98#ibcon#read 4, iclass 19, count 0 2006.286.01:23:33.98#ibcon#about to read 5, iclass 19, count 0 2006.286.01:23:33.98#ibcon#read 5, iclass 19, count 0 2006.286.01:23:33.98#ibcon#about to read 6, iclass 19, count 0 2006.286.01:23:33.98#ibcon#read 6, iclass 19, count 0 2006.286.01:23:33.98#ibcon#end of sib2, iclass 19, count 0 2006.286.01:23:33.98#ibcon#*after write, iclass 19, count 0 2006.286.01:23:33.98#ibcon#*before return 0, iclass 19, count 0 2006.286.01:23:33.98#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:23:33.98#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:23:33.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.01:23:33.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.01:23:33.98$vck44/valo=8,884.99 2006.286.01:23:33.98#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.01:23:33.98#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.01:23:33.98#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:33.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:23:33.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:23:33.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:23:33.98#ibcon#enter wrdev, iclass 21, count 0 2006.286.01:23:33.98#ibcon#first serial, iclass 21, count 0 2006.286.01:23:33.98#ibcon#enter sib2, iclass 21, count 0 2006.286.01:23:33.98#ibcon#flushed, iclass 21, count 0 2006.286.01:23:33.98#ibcon#about to write, iclass 21, count 0 2006.286.01:23:33.98#ibcon#wrote, iclass 21, count 0 2006.286.01:23:33.98#ibcon#about to read 3, iclass 21, count 0 2006.286.01:23:34.00#ibcon#read 3, iclass 21, count 0 2006.286.01:23:34.00#ibcon#about to read 4, iclass 21, count 0 2006.286.01:23:34.00#ibcon#read 4, iclass 21, count 0 2006.286.01:23:34.00#ibcon#about to read 5, iclass 21, count 0 2006.286.01:23:34.00#ibcon#read 5, iclass 21, count 0 2006.286.01:23:34.00#ibcon#about to read 6, iclass 21, count 0 2006.286.01:23:34.00#ibcon#read 6, iclass 21, count 0 2006.286.01:23:34.00#ibcon#end of sib2, iclass 21, count 0 2006.286.01:23:34.00#ibcon#*mode == 0, iclass 21, count 0 2006.286.01:23:34.00#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.01:23:34.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:23:34.00#ibcon#*before write, iclass 21, count 0 2006.286.01:23:34.00#ibcon#enter sib2, iclass 21, count 0 2006.286.01:23:34.00#ibcon#flushed, iclass 21, count 0 2006.286.01:23:34.00#ibcon#about to write, iclass 21, count 0 2006.286.01:23:34.00#ibcon#wrote, iclass 21, count 0 2006.286.01:23:34.00#ibcon#about to read 3, iclass 21, count 0 2006.286.01:23:34.04#ibcon#read 3, iclass 21, count 0 2006.286.01:23:34.04#ibcon#about to read 4, iclass 21, count 0 2006.286.01:23:34.04#ibcon#read 4, iclass 21, count 0 2006.286.01:23:34.04#ibcon#about to read 5, iclass 21, count 0 2006.286.01:23:34.04#ibcon#read 5, iclass 21, count 0 2006.286.01:23:34.04#ibcon#about to read 6, iclass 21, count 0 2006.286.01:23:34.04#ibcon#read 6, iclass 21, count 0 2006.286.01:23:34.04#ibcon#end of sib2, iclass 21, count 0 2006.286.01:23:34.04#ibcon#*after write, iclass 21, count 0 2006.286.01:23:34.04#ibcon#*before return 0, iclass 21, count 0 2006.286.01:23:34.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:23:34.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:23:34.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.01:23:34.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.01:23:34.04$vck44/va=8,3 2006.286.01:23:34.04#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.01:23:34.04#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.01:23:34.04#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:34.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.01:23:34.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.01:23:34.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.01:23:34.10#ibcon#enter wrdev, iclass 23, count 2 2006.286.01:23:34.10#ibcon#first serial, iclass 23, count 2 2006.286.01:23:34.10#ibcon#enter sib2, iclass 23, count 2 2006.286.01:23:34.10#ibcon#flushed, iclass 23, count 2 2006.286.01:23:34.10#ibcon#about to write, iclass 23, count 2 2006.286.01:23:34.10#ibcon#wrote, iclass 23, count 2 2006.286.01:23:34.10#ibcon#about to read 3, iclass 23, count 2 2006.286.01:23:34.12#ibcon#read 3, iclass 23, count 2 2006.286.01:23:34.12#ibcon#about to read 4, iclass 23, count 2 2006.286.01:23:34.12#ibcon#read 4, iclass 23, count 2 2006.286.01:23:34.12#ibcon#about to read 5, iclass 23, count 2 2006.286.01:23:34.12#ibcon#read 5, iclass 23, count 2 2006.286.01:23:34.12#ibcon#about to read 6, iclass 23, count 2 2006.286.01:23:34.12#ibcon#read 6, iclass 23, count 2 2006.286.01:23:34.12#ibcon#end of sib2, iclass 23, count 2 2006.286.01:23:34.12#ibcon#*mode == 0, iclass 23, count 2 2006.286.01:23:34.12#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.01:23:34.12#ibcon#[25=AT08-03\r\n] 2006.286.01:23:34.12#ibcon#*before write, iclass 23, count 2 2006.286.01:23:34.12#ibcon#enter sib2, iclass 23, count 2 2006.286.01:23:34.12#ibcon#flushed, iclass 23, count 2 2006.286.01:23:34.12#ibcon#about to write, iclass 23, count 2 2006.286.01:23:34.12#ibcon#wrote, iclass 23, count 2 2006.286.01:23:34.12#ibcon#about to read 3, iclass 23, count 2 2006.286.01:23:34.15#ibcon#read 3, iclass 23, count 2 2006.286.01:23:34.15#ibcon#about to read 4, iclass 23, count 2 2006.286.01:23:34.15#ibcon#read 4, iclass 23, count 2 2006.286.01:23:34.15#ibcon#about to read 5, iclass 23, count 2 2006.286.01:23:34.15#ibcon#read 5, iclass 23, count 2 2006.286.01:23:34.15#ibcon#about to read 6, iclass 23, count 2 2006.286.01:23:34.15#ibcon#read 6, iclass 23, count 2 2006.286.01:23:34.15#ibcon#end of sib2, iclass 23, count 2 2006.286.01:23:34.15#ibcon#*after write, iclass 23, count 2 2006.286.01:23:34.15#ibcon#*before return 0, iclass 23, count 2 2006.286.01:23:34.15#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.01:23:34.15#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.01:23:34.15#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.01:23:34.15#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:34.15#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.01:23:34.27#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.01:23:34.27#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.01:23:34.27#ibcon#enter wrdev, iclass 23, count 0 2006.286.01:23:34.27#ibcon#first serial, iclass 23, count 0 2006.286.01:23:34.27#ibcon#enter sib2, iclass 23, count 0 2006.286.01:23:34.27#ibcon#flushed, iclass 23, count 0 2006.286.01:23:34.27#ibcon#about to write, iclass 23, count 0 2006.286.01:23:34.27#ibcon#wrote, iclass 23, count 0 2006.286.01:23:34.27#ibcon#about to read 3, iclass 23, count 0 2006.286.01:23:34.29#ibcon#read 3, iclass 23, count 0 2006.286.01:23:34.29#ibcon#about to read 4, iclass 23, count 0 2006.286.01:23:34.29#ibcon#read 4, iclass 23, count 0 2006.286.01:23:34.29#ibcon#about to read 5, iclass 23, count 0 2006.286.01:23:34.29#ibcon#read 5, iclass 23, count 0 2006.286.01:23:34.29#ibcon#about to read 6, iclass 23, count 0 2006.286.01:23:34.29#ibcon#read 6, iclass 23, count 0 2006.286.01:23:34.29#ibcon#end of sib2, iclass 23, count 0 2006.286.01:23:34.29#ibcon#*mode == 0, iclass 23, count 0 2006.286.01:23:34.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.01:23:34.29#ibcon#[25=USB\r\n] 2006.286.01:23:34.29#ibcon#*before write, iclass 23, count 0 2006.286.01:23:34.29#ibcon#enter sib2, iclass 23, count 0 2006.286.01:23:34.29#ibcon#flushed, iclass 23, count 0 2006.286.01:23:34.29#ibcon#about to write, iclass 23, count 0 2006.286.01:23:34.29#ibcon#wrote, iclass 23, count 0 2006.286.01:23:34.29#ibcon#about to read 3, iclass 23, count 0 2006.286.01:23:34.32#ibcon#read 3, iclass 23, count 0 2006.286.01:23:34.32#ibcon#about to read 4, iclass 23, count 0 2006.286.01:23:34.32#ibcon#read 4, iclass 23, count 0 2006.286.01:23:34.32#ibcon#about to read 5, iclass 23, count 0 2006.286.01:23:34.32#ibcon#read 5, iclass 23, count 0 2006.286.01:23:34.32#ibcon#about to read 6, iclass 23, count 0 2006.286.01:23:34.32#ibcon#read 6, iclass 23, count 0 2006.286.01:23:34.32#ibcon#end of sib2, iclass 23, count 0 2006.286.01:23:34.32#ibcon#*after write, iclass 23, count 0 2006.286.01:23:34.32#ibcon#*before return 0, iclass 23, count 0 2006.286.01:23:34.32#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.01:23:34.32#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.01:23:34.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.01:23:34.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.01:23:34.32$vck44/vblo=1,629.99 2006.286.01:23:34.32#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.01:23:34.32#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.01:23:34.32#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:34.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.01:23:34.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.01:23:34.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.01:23:34.32#ibcon#enter wrdev, iclass 25, count 0 2006.286.01:23:34.32#ibcon#first serial, iclass 25, count 0 2006.286.01:23:34.32#ibcon#enter sib2, iclass 25, count 0 2006.286.01:23:34.32#ibcon#flushed, iclass 25, count 0 2006.286.01:23:34.32#ibcon#about to write, iclass 25, count 0 2006.286.01:23:34.32#ibcon#wrote, iclass 25, count 0 2006.286.01:23:34.32#ibcon#about to read 3, iclass 25, count 0 2006.286.01:23:34.34#ibcon#read 3, iclass 25, count 0 2006.286.01:23:34.34#ibcon#about to read 4, iclass 25, count 0 2006.286.01:23:34.34#ibcon#read 4, iclass 25, count 0 2006.286.01:23:34.34#ibcon#about to read 5, iclass 25, count 0 2006.286.01:23:34.34#ibcon#read 5, iclass 25, count 0 2006.286.01:23:34.34#ibcon#about to read 6, iclass 25, count 0 2006.286.01:23:34.34#ibcon#read 6, iclass 25, count 0 2006.286.01:23:34.34#ibcon#end of sib2, iclass 25, count 0 2006.286.01:23:34.34#ibcon#*mode == 0, iclass 25, count 0 2006.286.01:23:34.34#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.01:23:34.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:23:34.34#ibcon#*before write, iclass 25, count 0 2006.286.01:23:34.34#ibcon#enter sib2, iclass 25, count 0 2006.286.01:23:34.34#ibcon#flushed, iclass 25, count 0 2006.286.01:23:34.34#ibcon#about to write, iclass 25, count 0 2006.286.01:23:34.34#ibcon#wrote, iclass 25, count 0 2006.286.01:23:34.34#ibcon#about to read 3, iclass 25, count 0 2006.286.01:23:34.38#ibcon#read 3, iclass 25, count 0 2006.286.01:23:34.38#ibcon#about to read 4, iclass 25, count 0 2006.286.01:23:34.38#ibcon#read 4, iclass 25, count 0 2006.286.01:23:34.38#ibcon#about to read 5, iclass 25, count 0 2006.286.01:23:34.38#ibcon#read 5, iclass 25, count 0 2006.286.01:23:34.38#ibcon#about to read 6, iclass 25, count 0 2006.286.01:23:34.38#ibcon#read 6, iclass 25, count 0 2006.286.01:23:34.38#ibcon#end of sib2, iclass 25, count 0 2006.286.01:23:34.38#ibcon#*after write, iclass 25, count 0 2006.286.01:23:34.38#ibcon#*before return 0, iclass 25, count 0 2006.286.01:23:34.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.01:23:34.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.01:23:34.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.01:23:34.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.01:23:34.38$vck44/vb=1,4 2006.286.01:23:34.38#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.01:23:34.38#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.01:23:34.38#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:34.38#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.01:23:34.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.01:23:34.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.01:23:34.38#ibcon#enter wrdev, iclass 27, count 2 2006.286.01:23:34.38#ibcon#first serial, iclass 27, count 2 2006.286.01:23:34.38#ibcon#enter sib2, iclass 27, count 2 2006.286.01:23:34.38#ibcon#flushed, iclass 27, count 2 2006.286.01:23:34.38#ibcon#about to write, iclass 27, count 2 2006.286.01:23:34.38#ibcon#wrote, iclass 27, count 2 2006.286.01:23:34.38#ibcon#about to read 3, iclass 27, count 2 2006.286.01:23:34.40#ibcon#read 3, iclass 27, count 2 2006.286.01:23:34.40#ibcon#about to read 4, iclass 27, count 2 2006.286.01:23:34.40#ibcon#read 4, iclass 27, count 2 2006.286.01:23:34.40#ibcon#about to read 5, iclass 27, count 2 2006.286.01:23:34.40#ibcon#read 5, iclass 27, count 2 2006.286.01:23:34.40#ibcon#about to read 6, iclass 27, count 2 2006.286.01:23:34.40#ibcon#read 6, iclass 27, count 2 2006.286.01:23:34.40#ibcon#end of sib2, iclass 27, count 2 2006.286.01:23:34.40#ibcon#*mode == 0, iclass 27, count 2 2006.286.01:23:34.40#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.01:23:34.40#ibcon#[27=AT01-04\r\n] 2006.286.01:23:34.40#ibcon#*before write, iclass 27, count 2 2006.286.01:23:34.40#ibcon#enter sib2, iclass 27, count 2 2006.286.01:23:34.40#ibcon#flushed, iclass 27, count 2 2006.286.01:23:34.40#ibcon#about to write, iclass 27, count 2 2006.286.01:23:34.40#ibcon#wrote, iclass 27, count 2 2006.286.01:23:34.40#ibcon#about to read 3, iclass 27, count 2 2006.286.01:23:34.43#ibcon#read 3, iclass 27, count 2 2006.286.01:23:34.43#ibcon#about to read 4, iclass 27, count 2 2006.286.01:23:34.43#ibcon#read 4, iclass 27, count 2 2006.286.01:23:34.43#ibcon#about to read 5, iclass 27, count 2 2006.286.01:23:34.43#ibcon#read 5, iclass 27, count 2 2006.286.01:23:34.43#ibcon#about to read 6, iclass 27, count 2 2006.286.01:23:34.43#ibcon#read 6, iclass 27, count 2 2006.286.01:23:34.43#ibcon#end of sib2, iclass 27, count 2 2006.286.01:23:34.43#ibcon#*after write, iclass 27, count 2 2006.286.01:23:34.43#ibcon#*before return 0, iclass 27, count 2 2006.286.01:23:34.43#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.01:23:34.43#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.01:23:34.43#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.01:23:34.43#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:34.43#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.01:23:34.55#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.01:23:34.55#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.01:23:34.55#ibcon#enter wrdev, iclass 27, count 0 2006.286.01:23:34.55#ibcon#first serial, iclass 27, count 0 2006.286.01:23:34.55#ibcon#enter sib2, iclass 27, count 0 2006.286.01:23:34.55#ibcon#flushed, iclass 27, count 0 2006.286.01:23:34.55#ibcon#about to write, iclass 27, count 0 2006.286.01:23:34.55#ibcon#wrote, iclass 27, count 0 2006.286.01:23:34.55#ibcon#about to read 3, iclass 27, count 0 2006.286.01:23:34.57#ibcon#read 3, iclass 27, count 0 2006.286.01:23:34.57#ibcon#about to read 4, iclass 27, count 0 2006.286.01:23:34.57#ibcon#read 4, iclass 27, count 0 2006.286.01:23:34.57#ibcon#about to read 5, iclass 27, count 0 2006.286.01:23:34.57#ibcon#read 5, iclass 27, count 0 2006.286.01:23:34.57#ibcon#about to read 6, iclass 27, count 0 2006.286.01:23:34.57#ibcon#read 6, iclass 27, count 0 2006.286.01:23:34.57#ibcon#end of sib2, iclass 27, count 0 2006.286.01:23:34.57#ibcon#*mode == 0, iclass 27, count 0 2006.286.01:23:34.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.01:23:34.57#ibcon#[27=USB\r\n] 2006.286.01:23:34.57#ibcon#*before write, iclass 27, count 0 2006.286.01:23:34.57#ibcon#enter sib2, iclass 27, count 0 2006.286.01:23:34.57#ibcon#flushed, iclass 27, count 0 2006.286.01:23:34.57#ibcon#about to write, iclass 27, count 0 2006.286.01:23:34.57#ibcon#wrote, iclass 27, count 0 2006.286.01:23:34.57#ibcon#about to read 3, iclass 27, count 0 2006.286.01:23:34.60#ibcon#read 3, iclass 27, count 0 2006.286.01:23:34.60#ibcon#about to read 4, iclass 27, count 0 2006.286.01:23:34.60#ibcon#read 4, iclass 27, count 0 2006.286.01:23:34.60#ibcon#about to read 5, iclass 27, count 0 2006.286.01:23:34.60#ibcon#read 5, iclass 27, count 0 2006.286.01:23:34.60#ibcon#about to read 6, iclass 27, count 0 2006.286.01:23:34.60#ibcon#read 6, iclass 27, count 0 2006.286.01:23:34.60#ibcon#end of sib2, iclass 27, count 0 2006.286.01:23:34.60#ibcon#*after write, iclass 27, count 0 2006.286.01:23:34.60#ibcon#*before return 0, iclass 27, count 0 2006.286.01:23:34.60#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.01:23:34.60#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.01:23:34.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.01:23:34.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.01:23:34.60$vck44/vblo=2,634.99 2006.286.01:23:34.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.01:23:34.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.01:23:34.60#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:34.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:23:34.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:23:34.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:23:34.60#ibcon#enter wrdev, iclass 29, count 0 2006.286.01:23:34.60#ibcon#first serial, iclass 29, count 0 2006.286.01:23:34.60#ibcon#enter sib2, iclass 29, count 0 2006.286.01:23:34.60#ibcon#flushed, iclass 29, count 0 2006.286.01:23:34.60#ibcon#about to write, iclass 29, count 0 2006.286.01:23:34.60#ibcon#wrote, iclass 29, count 0 2006.286.01:23:34.60#ibcon#about to read 3, iclass 29, count 0 2006.286.01:23:34.62#ibcon#read 3, iclass 29, count 0 2006.286.01:23:34.62#ibcon#about to read 4, iclass 29, count 0 2006.286.01:23:34.62#ibcon#read 4, iclass 29, count 0 2006.286.01:23:34.62#ibcon#about to read 5, iclass 29, count 0 2006.286.01:23:34.62#ibcon#read 5, iclass 29, count 0 2006.286.01:23:34.62#ibcon#about to read 6, iclass 29, count 0 2006.286.01:23:34.62#ibcon#read 6, iclass 29, count 0 2006.286.01:23:34.62#ibcon#end of sib2, iclass 29, count 0 2006.286.01:23:34.62#ibcon#*mode == 0, iclass 29, count 0 2006.286.01:23:34.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.01:23:34.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:23:34.62#ibcon#*before write, iclass 29, count 0 2006.286.01:23:34.62#ibcon#enter sib2, iclass 29, count 0 2006.286.01:23:34.62#ibcon#flushed, iclass 29, count 0 2006.286.01:23:34.62#ibcon#about to write, iclass 29, count 0 2006.286.01:23:34.62#ibcon#wrote, iclass 29, count 0 2006.286.01:23:34.62#ibcon#about to read 3, iclass 29, count 0 2006.286.01:23:34.66#ibcon#read 3, iclass 29, count 0 2006.286.01:23:34.66#ibcon#about to read 4, iclass 29, count 0 2006.286.01:23:34.66#ibcon#read 4, iclass 29, count 0 2006.286.01:23:34.66#ibcon#about to read 5, iclass 29, count 0 2006.286.01:23:34.66#ibcon#read 5, iclass 29, count 0 2006.286.01:23:34.66#ibcon#about to read 6, iclass 29, count 0 2006.286.01:23:34.66#ibcon#read 6, iclass 29, count 0 2006.286.01:23:34.66#ibcon#end of sib2, iclass 29, count 0 2006.286.01:23:34.66#ibcon#*after write, iclass 29, count 0 2006.286.01:23:34.66#ibcon#*before return 0, iclass 29, count 0 2006.286.01:23:34.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:23:34.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:23:34.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.01:23:34.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.01:23:34.66$vck44/vb=2,5 2006.286.01:23:34.66#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.01:23:34.66#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.01:23:34.66#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:34.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:23:34.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:23:34.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:23:34.72#ibcon#enter wrdev, iclass 31, count 2 2006.286.01:23:34.72#ibcon#first serial, iclass 31, count 2 2006.286.01:23:34.72#ibcon#enter sib2, iclass 31, count 2 2006.286.01:23:34.72#ibcon#flushed, iclass 31, count 2 2006.286.01:23:34.72#ibcon#about to write, iclass 31, count 2 2006.286.01:23:34.72#ibcon#wrote, iclass 31, count 2 2006.286.01:23:34.72#ibcon#about to read 3, iclass 31, count 2 2006.286.01:23:34.74#ibcon#read 3, iclass 31, count 2 2006.286.01:23:34.74#ibcon#about to read 4, iclass 31, count 2 2006.286.01:23:34.74#ibcon#read 4, iclass 31, count 2 2006.286.01:23:34.74#ibcon#about to read 5, iclass 31, count 2 2006.286.01:23:34.74#ibcon#read 5, iclass 31, count 2 2006.286.01:23:34.74#ibcon#about to read 6, iclass 31, count 2 2006.286.01:23:34.74#ibcon#read 6, iclass 31, count 2 2006.286.01:23:34.74#ibcon#end of sib2, iclass 31, count 2 2006.286.01:23:34.74#ibcon#*mode == 0, iclass 31, count 2 2006.286.01:23:34.74#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.01:23:34.74#ibcon#[27=AT02-05\r\n] 2006.286.01:23:34.74#ibcon#*before write, iclass 31, count 2 2006.286.01:23:34.74#ibcon#enter sib2, iclass 31, count 2 2006.286.01:23:34.74#ibcon#flushed, iclass 31, count 2 2006.286.01:23:34.74#ibcon#about to write, iclass 31, count 2 2006.286.01:23:34.74#ibcon#wrote, iclass 31, count 2 2006.286.01:23:34.74#ibcon#about to read 3, iclass 31, count 2 2006.286.01:23:34.77#ibcon#read 3, iclass 31, count 2 2006.286.01:23:34.77#ibcon#about to read 4, iclass 31, count 2 2006.286.01:23:34.77#ibcon#read 4, iclass 31, count 2 2006.286.01:23:34.77#ibcon#about to read 5, iclass 31, count 2 2006.286.01:23:34.77#ibcon#read 5, iclass 31, count 2 2006.286.01:23:34.77#ibcon#about to read 6, iclass 31, count 2 2006.286.01:23:34.77#ibcon#read 6, iclass 31, count 2 2006.286.01:23:34.77#ibcon#end of sib2, iclass 31, count 2 2006.286.01:23:34.77#ibcon#*after write, iclass 31, count 2 2006.286.01:23:34.77#ibcon#*before return 0, iclass 31, count 2 2006.286.01:23:34.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:23:34.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:23:34.77#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.01:23:34.77#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:34.77#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:23:34.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:23:34.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:23:34.89#ibcon#enter wrdev, iclass 31, count 0 2006.286.01:23:34.89#ibcon#first serial, iclass 31, count 0 2006.286.01:23:34.89#ibcon#enter sib2, iclass 31, count 0 2006.286.01:23:34.89#ibcon#flushed, iclass 31, count 0 2006.286.01:23:34.89#ibcon#about to write, iclass 31, count 0 2006.286.01:23:34.89#ibcon#wrote, iclass 31, count 0 2006.286.01:23:34.89#ibcon#about to read 3, iclass 31, count 0 2006.286.01:23:34.91#ibcon#read 3, iclass 31, count 0 2006.286.01:23:34.91#ibcon#about to read 4, iclass 31, count 0 2006.286.01:23:34.91#ibcon#read 4, iclass 31, count 0 2006.286.01:23:34.91#ibcon#about to read 5, iclass 31, count 0 2006.286.01:23:34.91#ibcon#read 5, iclass 31, count 0 2006.286.01:23:34.91#ibcon#about to read 6, iclass 31, count 0 2006.286.01:23:34.91#ibcon#read 6, iclass 31, count 0 2006.286.01:23:34.91#ibcon#end of sib2, iclass 31, count 0 2006.286.01:23:34.91#ibcon#*mode == 0, iclass 31, count 0 2006.286.01:23:34.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.01:23:34.91#ibcon#[27=USB\r\n] 2006.286.01:23:34.91#ibcon#*before write, iclass 31, count 0 2006.286.01:23:34.91#ibcon#enter sib2, iclass 31, count 0 2006.286.01:23:34.91#ibcon#flushed, iclass 31, count 0 2006.286.01:23:34.91#ibcon#about to write, iclass 31, count 0 2006.286.01:23:34.91#ibcon#wrote, iclass 31, count 0 2006.286.01:23:34.91#ibcon#about to read 3, iclass 31, count 0 2006.286.01:23:34.94#ibcon#read 3, iclass 31, count 0 2006.286.01:23:34.94#ibcon#about to read 4, iclass 31, count 0 2006.286.01:23:34.94#ibcon#read 4, iclass 31, count 0 2006.286.01:23:34.94#ibcon#about to read 5, iclass 31, count 0 2006.286.01:23:34.94#ibcon#read 5, iclass 31, count 0 2006.286.01:23:34.94#ibcon#about to read 6, iclass 31, count 0 2006.286.01:23:34.94#ibcon#read 6, iclass 31, count 0 2006.286.01:23:34.94#ibcon#end of sib2, iclass 31, count 0 2006.286.01:23:34.94#ibcon#*after write, iclass 31, count 0 2006.286.01:23:34.94#ibcon#*before return 0, iclass 31, count 0 2006.286.01:23:34.94#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:23:34.94#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:23:34.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.01:23:34.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.01:23:34.94$vck44/vblo=3,649.99 2006.286.01:23:34.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.01:23:34.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.01:23:34.94#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:34.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:23:34.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:23:34.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:23:34.94#ibcon#enter wrdev, iclass 33, count 0 2006.286.01:23:34.94#ibcon#first serial, iclass 33, count 0 2006.286.01:23:34.94#ibcon#enter sib2, iclass 33, count 0 2006.286.01:23:34.94#ibcon#flushed, iclass 33, count 0 2006.286.01:23:34.94#ibcon#about to write, iclass 33, count 0 2006.286.01:23:34.94#ibcon#wrote, iclass 33, count 0 2006.286.01:23:34.94#ibcon#about to read 3, iclass 33, count 0 2006.286.01:23:34.96#ibcon#read 3, iclass 33, count 0 2006.286.01:23:34.96#ibcon#about to read 4, iclass 33, count 0 2006.286.01:23:34.96#ibcon#read 4, iclass 33, count 0 2006.286.01:23:34.96#ibcon#about to read 5, iclass 33, count 0 2006.286.01:23:34.96#ibcon#read 5, iclass 33, count 0 2006.286.01:23:34.96#ibcon#about to read 6, iclass 33, count 0 2006.286.01:23:34.96#ibcon#read 6, iclass 33, count 0 2006.286.01:23:34.96#ibcon#end of sib2, iclass 33, count 0 2006.286.01:23:34.96#ibcon#*mode == 0, iclass 33, count 0 2006.286.01:23:34.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.01:23:34.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:23:34.96#ibcon#*before write, iclass 33, count 0 2006.286.01:23:34.96#ibcon#enter sib2, iclass 33, count 0 2006.286.01:23:34.96#ibcon#flushed, iclass 33, count 0 2006.286.01:23:34.96#ibcon#about to write, iclass 33, count 0 2006.286.01:23:34.96#ibcon#wrote, iclass 33, count 0 2006.286.01:23:34.96#ibcon#about to read 3, iclass 33, count 0 2006.286.01:23:35.00#ibcon#read 3, iclass 33, count 0 2006.286.01:23:35.00#ibcon#about to read 4, iclass 33, count 0 2006.286.01:23:35.00#ibcon#read 4, iclass 33, count 0 2006.286.01:23:35.00#ibcon#about to read 5, iclass 33, count 0 2006.286.01:23:35.00#ibcon#read 5, iclass 33, count 0 2006.286.01:23:35.00#ibcon#about to read 6, iclass 33, count 0 2006.286.01:23:35.00#ibcon#read 6, iclass 33, count 0 2006.286.01:23:35.00#ibcon#end of sib2, iclass 33, count 0 2006.286.01:23:35.00#ibcon#*after write, iclass 33, count 0 2006.286.01:23:35.00#ibcon#*before return 0, iclass 33, count 0 2006.286.01:23:35.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:23:35.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:23:35.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.01:23:35.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.01:23:35.00$vck44/vb=3,4 2006.286.01:23:35.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.01:23:35.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.01:23:35.00#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:35.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:23:35.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:23:35.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:23:35.06#ibcon#enter wrdev, iclass 35, count 2 2006.286.01:23:35.06#ibcon#first serial, iclass 35, count 2 2006.286.01:23:35.06#ibcon#enter sib2, iclass 35, count 2 2006.286.01:23:35.06#ibcon#flushed, iclass 35, count 2 2006.286.01:23:35.06#ibcon#about to write, iclass 35, count 2 2006.286.01:23:35.06#ibcon#wrote, iclass 35, count 2 2006.286.01:23:35.06#ibcon#about to read 3, iclass 35, count 2 2006.286.01:23:35.08#ibcon#read 3, iclass 35, count 2 2006.286.01:23:35.08#ibcon#about to read 4, iclass 35, count 2 2006.286.01:23:35.08#ibcon#read 4, iclass 35, count 2 2006.286.01:23:35.08#ibcon#about to read 5, iclass 35, count 2 2006.286.01:23:35.08#ibcon#read 5, iclass 35, count 2 2006.286.01:23:35.08#ibcon#about to read 6, iclass 35, count 2 2006.286.01:23:35.08#ibcon#read 6, iclass 35, count 2 2006.286.01:23:35.08#ibcon#end of sib2, iclass 35, count 2 2006.286.01:23:35.08#ibcon#*mode == 0, iclass 35, count 2 2006.286.01:23:35.08#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.01:23:35.08#ibcon#[27=AT03-04\r\n] 2006.286.01:23:35.08#ibcon#*before write, iclass 35, count 2 2006.286.01:23:35.08#ibcon#enter sib2, iclass 35, count 2 2006.286.01:23:35.08#ibcon#flushed, iclass 35, count 2 2006.286.01:23:35.08#ibcon#about to write, iclass 35, count 2 2006.286.01:23:35.08#ibcon#wrote, iclass 35, count 2 2006.286.01:23:35.08#ibcon#about to read 3, iclass 35, count 2 2006.286.01:23:35.11#ibcon#read 3, iclass 35, count 2 2006.286.01:23:35.11#ibcon#about to read 4, iclass 35, count 2 2006.286.01:23:35.11#ibcon#read 4, iclass 35, count 2 2006.286.01:23:35.11#ibcon#about to read 5, iclass 35, count 2 2006.286.01:23:35.11#ibcon#read 5, iclass 35, count 2 2006.286.01:23:35.11#ibcon#about to read 6, iclass 35, count 2 2006.286.01:23:35.11#ibcon#read 6, iclass 35, count 2 2006.286.01:23:35.11#ibcon#end of sib2, iclass 35, count 2 2006.286.01:23:35.11#ibcon#*after write, iclass 35, count 2 2006.286.01:23:35.11#ibcon#*before return 0, iclass 35, count 2 2006.286.01:23:35.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:23:35.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:23:35.11#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.01:23:35.11#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:35.11#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:23:35.23#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:23:35.23#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:23:35.23#ibcon#enter wrdev, iclass 35, count 0 2006.286.01:23:35.23#ibcon#first serial, iclass 35, count 0 2006.286.01:23:35.23#ibcon#enter sib2, iclass 35, count 0 2006.286.01:23:35.23#ibcon#flushed, iclass 35, count 0 2006.286.01:23:35.23#ibcon#about to write, iclass 35, count 0 2006.286.01:23:35.23#ibcon#wrote, iclass 35, count 0 2006.286.01:23:35.23#ibcon#about to read 3, iclass 35, count 0 2006.286.01:23:35.25#ibcon#read 3, iclass 35, count 0 2006.286.01:23:35.25#ibcon#about to read 4, iclass 35, count 0 2006.286.01:23:35.25#ibcon#read 4, iclass 35, count 0 2006.286.01:23:35.25#ibcon#about to read 5, iclass 35, count 0 2006.286.01:23:35.25#ibcon#read 5, iclass 35, count 0 2006.286.01:23:35.25#ibcon#about to read 6, iclass 35, count 0 2006.286.01:23:35.25#ibcon#read 6, iclass 35, count 0 2006.286.01:23:35.25#ibcon#end of sib2, iclass 35, count 0 2006.286.01:23:35.25#ibcon#*mode == 0, iclass 35, count 0 2006.286.01:23:35.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.01:23:35.25#ibcon#[27=USB\r\n] 2006.286.01:23:35.25#ibcon#*before write, iclass 35, count 0 2006.286.01:23:35.25#ibcon#enter sib2, iclass 35, count 0 2006.286.01:23:35.25#ibcon#flushed, iclass 35, count 0 2006.286.01:23:35.25#ibcon#about to write, iclass 35, count 0 2006.286.01:23:35.25#ibcon#wrote, iclass 35, count 0 2006.286.01:23:35.25#ibcon#about to read 3, iclass 35, count 0 2006.286.01:23:35.28#ibcon#read 3, iclass 35, count 0 2006.286.01:23:35.28#ibcon#about to read 4, iclass 35, count 0 2006.286.01:23:35.28#ibcon#read 4, iclass 35, count 0 2006.286.01:23:35.28#ibcon#about to read 5, iclass 35, count 0 2006.286.01:23:35.28#ibcon#read 5, iclass 35, count 0 2006.286.01:23:35.28#ibcon#about to read 6, iclass 35, count 0 2006.286.01:23:35.28#ibcon#read 6, iclass 35, count 0 2006.286.01:23:35.28#ibcon#end of sib2, iclass 35, count 0 2006.286.01:23:35.28#ibcon#*after write, iclass 35, count 0 2006.286.01:23:35.28#ibcon#*before return 0, iclass 35, count 0 2006.286.01:23:35.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:23:35.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:23:35.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.01:23:35.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.01:23:35.28$vck44/vblo=4,679.99 2006.286.01:23:35.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.01:23:35.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.01:23:35.28#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:35.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:23:35.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:23:35.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:23:35.28#ibcon#enter wrdev, iclass 37, count 0 2006.286.01:23:35.28#ibcon#first serial, iclass 37, count 0 2006.286.01:23:35.28#ibcon#enter sib2, iclass 37, count 0 2006.286.01:23:35.28#ibcon#flushed, iclass 37, count 0 2006.286.01:23:35.28#ibcon#about to write, iclass 37, count 0 2006.286.01:23:35.28#ibcon#wrote, iclass 37, count 0 2006.286.01:23:35.28#ibcon#about to read 3, iclass 37, count 0 2006.286.01:23:35.30#ibcon#read 3, iclass 37, count 0 2006.286.01:23:35.30#ibcon#about to read 4, iclass 37, count 0 2006.286.01:23:35.30#ibcon#read 4, iclass 37, count 0 2006.286.01:23:35.30#ibcon#about to read 5, iclass 37, count 0 2006.286.01:23:35.30#ibcon#read 5, iclass 37, count 0 2006.286.01:23:35.30#ibcon#about to read 6, iclass 37, count 0 2006.286.01:23:35.30#ibcon#read 6, iclass 37, count 0 2006.286.01:23:35.30#ibcon#end of sib2, iclass 37, count 0 2006.286.01:23:35.30#ibcon#*mode == 0, iclass 37, count 0 2006.286.01:23:35.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.01:23:35.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:23:35.30#ibcon#*before write, iclass 37, count 0 2006.286.01:23:35.30#ibcon#enter sib2, iclass 37, count 0 2006.286.01:23:35.30#ibcon#flushed, iclass 37, count 0 2006.286.01:23:35.30#ibcon#about to write, iclass 37, count 0 2006.286.01:23:35.30#ibcon#wrote, iclass 37, count 0 2006.286.01:23:35.30#ibcon#about to read 3, iclass 37, count 0 2006.286.01:23:35.34#ibcon#read 3, iclass 37, count 0 2006.286.01:23:35.34#ibcon#about to read 4, iclass 37, count 0 2006.286.01:23:35.34#ibcon#read 4, iclass 37, count 0 2006.286.01:23:35.34#ibcon#about to read 5, iclass 37, count 0 2006.286.01:23:35.34#ibcon#read 5, iclass 37, count 0 2006.286.01:23:35.34#ibcon#about to read 6, iclass 37, count 0 2006.286.01:23:35.34#ibcon#read 6, iclass 37, count 0 2006.286.01:23:35.34#ibcon#end of sib2, iclass 37, count 0 2006.286.01:23:35.34#ibcon#*after write, iclass 37, count 0 2006.286.01:23:35.34#ibcon#*before return 0, iclass 37, count 0 2006.286.01:23:35.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:23:35.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:23:35.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.01:23:35.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.01:23:35.34$vck44/vb=4,5 2006.286.01:23:35.34#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.01:23:35.34#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.01:23:35.34#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:35.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:23:35.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:23:35.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:23:35.40#ibcon#enter wrdev, iclass 39, count 2 2006.286.01:23:35.40#ibcon#first serial, iclass 39, count 2 2006.286.01:23:35.40#ibcon#enter sib2, iclass 39, count 2 2006.286.01:23:35.40#ibcon#flushed, iclass 39, count 2 2006.286.01:23:35.40#ibcon#about to write, iclass 39, count 2 2006.286.01:23:35.40#ibcon#wrote, iclass 39, count 2 2006.286.01:23:35.40#ibcon#about to read 3, iclass 39, count 2 2006.286.01:23:35.42#ibcon#read 3, iclass 39, count 2 2006.286.01:23:35.42#ibcon#about to read 4, iclass 39, count 2 2006.286.01:23:35.42#ibcon#read 4, iclass 39, count 2 2006.286.01:23:35.42#ibcon#about to read 5, iclass 39, count 2 2006.286.01:23:35.42#ibcon#read 5, iclass 39, count 2 2006.286.01:23:35.42#ibcon#about to read 6, iclass 39, count 2 2006.286.01:23:35.42#ibcon#read 6, iclass 39, count 2 2006.286.01:23:35.42#ibcon#end of sib2, iclass 39, count 2 2006.286.01:23:35.42#ibcon#*mode == 0, iclass 39, count 2 2006.286.01:23:35.42#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.01:23:35.42#ibcon#[27=AT04-05\r\n] 2006.286.01:23:35.42#ibcon#*before write, iclass 39, count 2 2006.286.01:23:35.42#ibcon#enter sib2, iclass 39, count 2 2006.286.01:23:35.42#ibcon#flushed, iclass 39, count 2 2006.286.01:23:35.42#ibcon#about to write, iclass 39, count 2 2006.286.01:23:35.42#ibcon#wrote, iclass 39, count 2 2006.286.01:23:35.42#ibcon#about to read 3, iclass 39, count 2 2006.286.01:23:35.45#ibcon#read 3, iclass 39, count 2 2006.286.01:23:35.45#ibcon#about to read 4, iclass 39, count 2 2006.286.01:23:35.45#ibcon#read 4, iclass 39, count 2 2006.286.01:23:35.45#ibcon#about to read 5, iclass 39, count 2 2006.286.01:23:35.45#ibcon#read 5, iclass 39, count 2 2006.286.01:23:35.45#ibcon#about to read 6, iclass 39, count 2 2006.286.01:23:35.45#ibcon#read 6, iclass 39, count 2 2006.286.01:23:35.45#ibcon#end of sib2, iclass 39, count 2 2006.286.01:23:35.45#ibcon#*after write, iclass 39, count 2 2006.286.01:23:35.45#ibcon#*before return 0, iclass 39, count 2 2006.286.01:23:35.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:23:35.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:23:35.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.01:23:35.45#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:35.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:23:35.57#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:23:35.57#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:23:35.57#ibcon#enter wrdev, iclass 39, count 0 2006.286.01:23:35.57#ibcon#first serial, iclass 39, count 0 2006.286.01:23:35.57#ibcon#enter sib2, iclass 39, count 0 2006.286.01:23:35.57#ibcon#flushed, iclass 39, count 0 2006.286.01:23:35.57#ibcon#about to write, iclass 39, count 0 2006.286.01:23:35.57#ibcon#wrote, iclass 39, count 0 2006.286.01:23:35.57#ibcon#about to read 3, iclass 39, count 0 2006.286.01:23:35.59#ibcon#read 3, iclass 39, count 0 2006.286.01:23:35.59#ibcon#about to read 4, iclass 39, count 0 2006.286.01:23:35.59#ibcon#read 4, iclass 39, count 0 2006.286.01:23:35.59#ibcon#about to read 5, iclass 39, count 0 2006.286.01:23:35.59#ibcon#read 5, iclass 39, count 0 2006.286.01:23:35.59#ibcon#about to read 6, iclass 39, count 0 2006.286.01:23:35.59#ibcon#read 6, iclass 39, count 0 2006.286.01:23:35.59#ibcon#end of sib2, iclass 39, count 0 2006.286.01:23:35.59#ibcon#*mode == 0, iclass 39, count 0 2006.286.01:23:35.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.01:23:35.59#ibcon#[27=USB\r\n] 2006.286.01:23:35.59#ibcon#*before write, iclass 39, count 0 2006.286.01:23:35.59#ibcon#enter sib2, iclass 39, count 0 2006.286.01:23:35.59#ibcon#flushed, iclass 39, count 0 2006.286.01:23:35.59#ibcon#about to write, iclass 39, count 0 2006.286.01:23:35.59#ibcon#wrote, iclass 39, count 0 2006.286.01:23:35.59#ibcon#about to read 3, iclass 39, count 0 2006.286.01:23:35.62#ibcon#read 3, iclass 39, count 0 2006.286.01:23:35.62#ibcon#about to read 4, iclass 39, count 0 2006.286.01:23:35.62#ibcon#read 4, iclass 39, count 0 2006.286.01:23:35.62#ibcon#about to read 5, iclass 39, count 0 2006.286.01:23:35.62#ibcon#read 5, iclass 39, count 0 2006.286.01:23:35.62#ibcon#about to read 6, iclass 39, count 0 2006.286.01:23:35.62#ibcon#read 6, iclass 39, count 0 2006.286.01:23:35.62#ibcon#end of sib2, iclass 39, count 0 2006.286.01:23:35.62#ibcon#*after write, iclass 39, count 0 2006.286.01:23:35.62#ibcon#*before return 0, iclass 39, count 0 2006.286.01:23:35.62#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:23:35.62#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:23:35.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.01:23:35.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.01:23:35.62$vck44/vblo=5,709.99 2006.286.01:23:35.62#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.01:23:35.62#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.01:23:35.62#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:35.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:23:35.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:23:35.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:23:35.62#ibcon#enter wrdev, iclass 3, count 0 2006.286.01:23:35.62#ibcon#first serial, iclass 3, count 0 2006.286.01:23:35.62#ibcon#enter sib2, iclass 3, count 0 2006.286.01:23:35.62#ibcon#flushed, iclass 3, count 0 2006.286.01:23:35.62#ibcon#about to write, iclass 3, count 0 2006.286.01:23:35.62#ibcon#wrote, iclass 3, count 0 2006.286.01:23:35.62#ibcon#about to read 3, iclass 3, count 0 2006.286.01:23:35.64#ibcon#read 3, iclass 3, count 0 2006.286.01:23:35.64#ibcon#about to read 4, iclass 3, count 0 2006.286.01:23:35.64#ibcon#read 4, iclass 3, count 0 2006.286.01:23:35.64#ibcon#about to read 5, iclass 3, count 0 2006.286.01:23:35.64#ibcon#read 5, iclass 3, count 0 2006.286.01:23:35.64#ibcon#about to read 6, iclass 3, count 0 2006.286.01:23:35.64#ibcon#read 6, iclass 3, count 0 2006.286.01:23:35.64#ibcon#end of sib2, iclass 3, count 0 2006.286.01:23:35.64#ibcon#*mode == 0, iclass 3, count 0 2006.286.01:23:35.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.01:23:35.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:23:35.64#ibcon#*before write, iclass 3, count 0 2006.286.01:23:35.64#ibcon#enter sib2, iclass 3, count 0 2006.286.01:23:35.64#ibcon#flushed, iclass 3, count 0 2006.286.01:23:35.64#ibcon#about to write, iclass 3, count 0 2006.286.01:23:35.64#ibcon#wrote, iclass 3, count 0 2006.286.01:23:35.64#ibcon#about to read 3, iclass 3, count 0 2006.286.01:23:35.68#ibcon#read 3, iclass 3, count 0 2006.286.01:23:35.68#ibcon#about to read 4, iclass 3, count 0 2006.286.01:23:35.68#ibcon#read 4, iclass 3, count 0 2006.286.01:23:35.68#ibcon#about to read 5, iclass 3, count 0 2006.286.01:23:35.68#ibcon#read 5, iclass 3, count 0 2006.286.01:23:35.68#ibcon#about to read 6, iclass 3, count 0 2006.286.01:23:35.68#ibcon#read 6, iclass 3, count 0 2006.286.01:23:35.68#ibcon#end of sib2, iclass 3, count 0 2006.286.01:23:35.68#ibcon#*after write, iclass 3, count 0 2006.286.01:23:35.68#ibcon#*before return 0, iclass 3, count 0 2006.286.01:23:35.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:23:35.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:23:35.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.01:23:35.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.01:23:35.68$vck44/vb=5,4 2006.286.01:23:35.68#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.01:23:35.68#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.01:23:35.68#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:35.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:23:35.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:23:35.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:23:35.74#ibcon#enter wrdev, iclass 5, count 2 2006.286.01:23:35.74#ibcon#first serial, iclass 5, count 2 2006.286.01:23:35.74#ibcon#enter sib2, iclass 5, count 2 2006.286.01:23:35.74#ibcon#flushed, iclass 5, count 2 2006.286.01:23:35.74#ibcon#about to write, iclass 5, count 2 2006.286.01:23:35.74#ibcon#wrote, iclass 5, count 2 2006.286.01:23:35.74#ibcon#about to read 3, iclass 5, count 2 2006.286.01:23:35.76#ibcon#read 3, iclass 5, count 2 2006.286.01:23:35.76#ibcon#about to read 4, iclass 5, count 2 2006.286.01:23:35.76#ibcon#read 4, iclass 5, count 2 2006.286.01:23:35.76#ibcon#about to read 5, iclass 5, count 2 2006.286.01:23:35.76#ibcon#read 5, iclass 5, count 2 2006.286.01:23:35.76#ibcon#about to read 6, iclass 5, count 2 2006.286.01:23:35.76#ibcon#read 6, iclass 5, count 2 2006.286.01:23:35.76#ibcon#end of sib2, iclass 5, count 2 2006.286.01:23:35.76#ibcon#*mode == 0, iclass 5, count 2 2006.286.01:23:35.76#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.01:23:35.76#ibcon#[27=AT05-04\r\n] 2006.286.01:23:35.76#ibcon#*before write, iclass 5, count 2 2006.286.01:23:35.76#ibcon#enter sib2, iclass 5, count 2 2006.286.01:23:35.76#ibcon#flushed, iclass 5, count 2 2006.286.01:23:35.76#ibcon#about to write, iclass 5, count 2 2006.286.01:23:35.76#ibcon#wrote, iclass 5, count 2 2006.286.01:23:35.76#ibcon#about to read 3, iclass 5, count 2 2006.286.01:23:35.79#ibcon#read 3, iclass 5, count 2 2006.286.01:23:35.79#ibcon#about to read 4, iclass 5, count 2 2006.286.01:23:35.79#ibcon#read 4, iclass 5, count 2 2006.286.01:23:35.79#ibcon#about to read 5, iclass 5, count 2 2006.286.01:23:35.79#ibcon#read 5, iclass 5, count 2 2006.286.01:23:35.79#ibcon#about to read 6, iclass 5, count 2 2006.286.01:23:35.79#ibcon#read 6, iclass 5, count 2 2006.286.01:23:35.79#ibcon#end of sib2, iclass 5, count 2 2006.286.01:23:35.79#ibcon#*after write, iclass 5, count 2 2006.286.01:23:35.79#ibcon#*before return 0, iclass 5, count 2 2006.286.01:23:35.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:23:35.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:23:35.79#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.01:23:35.79#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:35.79#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:23:35.91#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:23:35.91#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:23:35.91#ibcon#enter wrdev, iclass 5, count 0 2006.286.01:23:35.91#ibcon#first serial, iclass 5, count 0 2006.286.01:23:35.91#ibcon#enter sib2, iclass 5, count 0 2006.286.01:23:35.91#ibcon#flushed, iclass 5, count 0 2006.286.01:23:35.91#ibcon#about to write, iclass 5, count 0 2006.286.01:23:35.91#ibcon#wrote, iclass 5, count 0 2006.286.01:23:35.91#ibcon#about to read 3, iclass 5, count 0 2006.286.01:23:35.93#ibcon#read 3, iclass 5, count 0 2006.286.01:23:35.93#ibcon#about to read 4, iclass 5, count 0 2006.286.01:23:35.93#ibcon#read 4, iclass 5, count 0 2006.286.01:23:35.93#ibcon#about to read 5, iclass 5, count 0 2006.286.01:23:35.93#ibcon#read 5, iclass 5, count 0 2006.286.01:23:35.93#ibcon#about to read 6, iclass 5, count 0 2006.286.01:23:35.93#ibcon#read 6, iclass 5, count 0 2006.286.01:23:35.93#ibcon#end of sib2, iclass 5, count 0 2006.286.01:23:35.93#ibcon#*mode == 0, iclass 5, count 0 2006.286.01:23:35.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.01:23:35.93#ibcon#[27=USB\r\n] 2006.286.01:23:35.93#ibcon#*before write, iclass 5, count 0 2006.286.01:23:35.93#ibcon#enter sib2, iclass 5, count 0 2006.286.01:23:35.93#ibcon#flushed, iclass 5, count 0 2006.286.01:23:35.93#ibcon#about to write, iclass 5, count 0 2006.286.01:23:35.93#ibcon#wrote, iclass 5, count 0 2006.286.01:23:35.93#ibcon#about to read 3, iclass 5, count 0 2006.286.01:23:35.96#ibcon#read 3, iclass 5, count 0 2006.286.01:23:35.96#ibcon#about to read 4, iclass 5, count 0 2006.286.01:23:35.96#ibcon#read 4, iclass 5, count 0 2006.286.01:23:35.96#ibcon#about to read 5, iclass 5, count 0 2006.286.01:23:35.96#ibcon#read 5, iclass 5, count 0 2006.286.01:23:35.96#ibcon#about to read 6, iclass 5, count 0 2006.286.01:23:35.96#ibcon#read 6, iclass 5, count 0 2006.286.01:23:35.96#ibcon#end of sib2, iclass 5, count 0 2006.286.01:23:35.96#ibcon#*after write, iclass 5, count 0 2006.286.01:23:35.96#ibcon#*before return 0, iclass 5, count 0 2006.286.01:23:35.96#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:23:35.96#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:23:35.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.01:23:35.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.01:23:35.96$vck44/vblo=6,719.99 2006.286.01:23:35.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.01:23:35.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.01:23:35.96#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:35.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:23:35.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:23:35.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:23:35.96#ibcon#enter wrdev, iclass 7, count 0 2006.286.01:23:35.96#ibcon#first serial, iclass 7, count 0 2006.286.01:23:35.96#ibcon#enter sib2, iclass 7, count 0 2006.286.01:23:35.96#ibcon#flushed, iclass 7, count 0 2006.286.01:23:35.96#ibcon#about to write, iclass 7, count 0 2006.286.01:23:35.96#ibcon#wrote, iclass 7, count 0 2006.286.01:23:35.96#ibcon#about to read 3, iclass 7, count 0 2006.286.01:23:35.98#ibcon#read 3, iclass 7, count 0 2006.286.01:23:35.98#ibcon#about to read 4, iclass 7, count 0 2006.286.01:23:35.98#ibcon#read 4, iclass 7, count 0 2006.286.01:23:35.98#ibcon#about to read 5, iclass 7, count 0 2006.286.01:23:35.98#ibcon#read 5, iclass 7, count 0 2006.286.01:23:35.98#ibcon#about to read 6, iclass 7, count 0 2006.286.01:23:35.98#ibcon#read 6, iclass 7, count 0 2006.286.01:23:35.98#ibcon#end of sib2, iclass 7, count 0 2006.286.01:23:35.98#ibcon#*mode == 0, iclass 7, count 0 2006.286.01:23:35.98#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.01:23:35.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:23:35.98#ibcon#*before write, iclass 7, count 0 2006.286.01:23:35.98#ibcon#enter sib2, iclass 7, count 0 2006.286.01:23:35.98#ibcon#flushed, iclass 7, count 0 2006.286.01:23:35.98#ibcon#about to write, iclass 7, count 0 2006.286.01:23:35.98#ibcon#wrote, iclass 7, count 0 2006.286.01:23:35.98#ibcon#about to read 3, iclass 7, count 0 2006.286.01:23:36.02#ibcon#read 3, iclass 7, count 0 2006.286.01:23:36.02#ibcon#about to read 4, iclass 7, count 0 2006.286.01:23:36.02#ibcon#read 4, iclass 7, count 0 2006.286.01:23:36.02#ibcon#about to read 5, iclass 7, count 0 2006.286.01:23:36.02#ibcon#read 5, iclass 7, count 0 2006.286.01:23:36.02#ibcon#about to read 6, iclass 7, count 0 2006.286.01:23:36.02#ibcon#read 6, iclass 7, count 0 2006.286.01:23:36.02#ibcon#end of sib2, iclass 7, count 0 2006.286.01:23:36.02#ibcon#*after write, iclass 7, count 0 2006.286.01:23:36.02#ibcon#*before return 0, iclass 7, count 0 2006.286.01:23:36.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:23:36.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:23:36.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.01:23:36.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.01:23:36.02$vck44/vb=6,3 2006.286.01:23:36.02#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.01:23:36.02#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.01:23:36.02#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:36.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:23:36.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:23:36.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:23:36.08#ibcon#enter wrdev, iclass 11, count 2 2006.286.01:23:36.08#ibcon#first serial, iclass 11, count 2 2006.286.01:23:36.08#ibcon#enter sib2, iclass 11, count 2 2006.286.01:23:36.08#ibcon#flushed, iclass 11, count 2 2006.286.01:23:36.08#ibcon#about to write, iclass 11, count 2 2006.286.01:23:36.08#ibcon#wrote, iclass 11, count 2 2006.286.01:23:36.08#ibcon#about to read 3, iclass 11, count 2 2006.286.01:23:36.10#ibcon#read 3, iclass 11, count 2 2006.286.01:23:36.10#ibcon#about to read 4, iclass 11, count 2 2006.286.01:23:36.10#ibcon#read 4, iclass 11, count 2 2006.286.01:23:36.10#ibcon#about to read 5, iclass 11, count 2 2006.286.01:23:36.10#ibcon#read 5, iclass 11, count 2 2006.286.01:23:36.10#ibcon#about to read 6, iclass 11, count 2 2006.286.01:23:36.10#ibcon#read 6, iclass 11, count 2 2006.286.01:23:36.10#ibcon#end of sib2, iclass 11, count 2 2006.286.01:23:36.10#ibcon#*mode == 0, iclass 11, count 2 2006.286.01:23:36.10#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.01:23:36.10#ibcon#[27=AT06-03\r\n] 2006.286.01:23:36.10#ibcon#*before write, iclass 11, count 2 2006.286.01:23:36.10#ibcon#enter sib2, iclass 11, count 2 2006.286.01:23:36.10#ibcon#flushed, iclass 11, count 2 2006.286.01:23:36.10#ibcon#about to write, iclass 11, count 2 2006.286.01:23:36.10#ibcon#wrote, iclass 11, count 2 2006.286.01:23:36.10#ibcon#about to read 3, iclass 11, count 2 2006.286.01:23:36.13#ibcon#read 3, iclass 11, count 2 2006.286.01:23:36.13#ibcon#about to read 4, iclass 11, count 2 2006.286.01:23:36.13#ibcon#read 4, iclass 11, count 2 2006.286.01:23:36.13#ibcon#about to read 5, iclass 11, count 2 2006.286.01:23:36.13#ibcon#read 5, iclass 11, count 2 2006.286.01:23:36.13#ibcon#about to read 6, iclass 11, count 2 2006.286.01:23:36.13#ibcon#read 6, iclass 11, count 2 2006.286.01:23:36.13#ibcon#end of sib2, iclass 11, count 2 2006.286.01:23:36.13#ibcon#*after write, iclass 11, count 2 2006.286.01:23:36.13#ibcon#*before return 0, iclass 11, count 2 2006.286.01:23:36.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:23:36.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:23:36.13#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.01:23:36.13#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:36.13#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:23:36.25#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:23:36.25#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:23:36.25#ibcon#enter wrdev, iclass 11, count 0 2006.286.01:23:36.25#ibcon#first serial, iclass 11, count 0 2006.286.01:23:36.25#ibcon#enter sib2, iclass 11, count 0 2006.286.01:23:36.25#ibcon#flushed, iclass 11, count 0 2006.286.01:23:36.25#ibcon#about to write, iclass 11, count 0 2006.286.01:23:36.25#ibcon#wrote, iclass 11, count 0 2006.286.01:23:36.25#ibcon#about to read 3, iclass 11, count 0 2006.286.01:23:36.27#ibcon#read 3, iclass 11, count 0 2006.286.01:23:36.27#ibcon#about to read 4, iclass 11, count 0 2006.286.01:23:36.27#ibcon#read 4, iclass 11, count 0 2006.286.01:23:36.27#ibcon#about to read 5, iclass 11, count 0 2006.286.01:23:36.27#ibcon#read 5, iclass 11, count 0 2006.286.01:23:36.27#ibcon#about to read 6, iclass 11, count 0 2006.286.01:23:36.27#ibcon#read 6, iclass 11, count 0 2006.286.01:23:36.27#ibcon#end of sib2, iclass 11, count 0 2006.286.01:23:36.27#ibcon#*mode == 0, iclass 11, count 0 2006.286.01:23:36.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.01:23:36.27#ibcon#[27=USB\r\n] 2006.286.01:23:36.27#ibcon#*before write, iclass 11, count 0 2006.286.01:23:36.27#ibcon#enter sib2, iclass 11, count 0 2006.286.01:23:36.27#ibcon#flushed, iclass 11, count 0 2006.286.01:23:36.27#ibcon#about to write, iclass 11, count 0 2006.286.01:23:36.27#ibcon#wrote, iclass 11, count 0 2006.286.01:23:36.27#ibcon#about to read 3, iclass 11, count 0 2006.286.01:23:36.30#ibcon#read 3, iclass 11, count 0 2006.286.01:23:36.30#ibcon#about to read 4, iclass 11, count 0 2006.286.01:23:36.30#ibcon#read 4, iclass 11, count 0 2006.286.01:23:36.30#ibcon#about to read 5, iclass 11, count 0 2006.286.01:23:36.30#ibcon#read 5, iclass 11, count 0 2006.286.01:23:36.30#ibcon#about to read 6, iclass 11, count 0 2006.286.01:23:36.30#ibcon#read 6, iclass 11, count 0 2006.286.01:23:36.30#ibcon#end of sib2, iclass 11, count 0 2006.286.01:23:36.30#ibcon#*after write, iclass 11, count 0 2006.286.01:23:36.30#ibcon#*before return 0, iclass 11, count 0 2006.286.01:23:36.30#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:23:36.30#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:23:36.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.01:23:36.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.01:23:36.30$vck44/vblo=7,734.99 2006.286.01:23:36.30#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.01:23:36.30#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.01:23:36.30#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:36.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:23:36.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:23:36.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:23:36.30#ibcon#enter wrdev, iclass 13, count 0 2006.286.01:23:36.30#ibcon#first serial, iclass 13, count 0 2006.286.01:23:36.30#ibcon#enter sib2, iclass 13, count 0 2006.286.01:23:36.30#ibcon#flushed, iclass 13, count 0 2006.286.01:23:36.30#ibcon#about to write, iclass 13, count 0 2006.286.01:23:36.30#ibcon#wrote, iclass 13, count 0 2006.286.01:23:36.30#ibcon#about to read 3, iclass 13, count 0 2006.286.01:23:36.32#ibcon#read 3, iclass 13, count 0 2006.286.01:23:36.32#ibcon#about to read 4, iclass 13, count 0 2006.286.01:23:36.32#ibcon#read 4, iclass 13, count 0 2006.286.01:23:36.32#ibcon#about to read 5, iclass 13, count 0 2006.286.01:23:36.32#ibcon#read 5, iclass 13, count 0 2006.286.01:23:36.32#ibcon#about to read 6, iclass 13, count 0 2006.286.01:23:36.32#ibcon#read 6, iclass 13, count 0 2006.286.01:23:36.32#ibcon#end of sib2, iclass 13, count 0 2006.286.01:23:36.32#ibcon#*mode == 0, iclass 13, count 0 2006.286.01:23:36.32#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.01:23:36.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:23:36.32#ibcon#*before write, iclass 13, count 0 2006.286.01:23:36.32#ibcon#enter sib2, iclass 13, count 0 2006.286.01:23:36.32#ibcon#flushed, iclass 13, count 0 2006.286.01:23:36.32#ibcon#about to write, iclass 13, count 0 2006.286.01:23:36.32#ibcon#wrote, iclass 13, count 0 2006.286.01:23:36.32#ibcon#about to read 3, iclass 13, count 0 2006.286.01:23:36.36#ibcon#read 3, iclass 13, count 0 2006.286.01:23:36.36#ibcon#about to read 4, iclass 13, count 0 2006.286.01:23:36.36#ibcon#read 4, iclass 13, count 0 2006.286.01:23:36.36#ibcon#about to read 5, iclass 13, count 0 2006.286.01:23:36.36#ibcon#read 5, iclass 13, count 0 2006.286.01:23:36.36#ibcon#about to read 6, iclass 13, count 0 2006.286.01:23:36.36#ibcon#read 6, iclass 13, count 0 2006.286.01:23:36.36#ibcon#end of sib2, iclass 13, count 0 2006.286.01:23:36.36#ibcon#*after write, iclass 13, count 0 2006.286.01:23:36.36#ibcon#*before return 0, iclass 13, count 0 2006.286.01:23:36.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:23:36.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:23:36.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.01:23:36.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.01:23:36.36$vck44/vb=7,4 2006.286.01:23:36.36#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.01:23:36.36#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.01:23:36.36#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:36.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:23:36.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:23:36.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:23:36.42#ibcon#enter wrdev, iclass 15, count 2 2006.286.01:23:36.42#ibcon#first serial, iclass 15, count 2 2006.286.01:23:36.42#ibcon#enter sib2, iclass 15, count 2 2006.286.01:23:36.42#ibcon#flushed, iclass 15, count 2 2006.286.01:23:36.42#ibcon#about to write, iclass 15, count 2 2006.286.01:23:36.42#ibcon#wrote, iclass 15, count 2 2006.286.01:23:36.42#ibcon#about to read 3, iclass 15, count 2 2006.286.01:23:36.44#ibcon#read 3, iclass 15, count 2 2006.286.01:23:36.44#ibcon#about to read 4, iclass 15, count 2 2006.286.01:23:36.44#ibcon#read 4, iclass 15, count 2 2006.286.01:23:36.44#ibcon#about to read 5, iclass 15, count 2 2006.286.01:23:36.44#ibcon#read 5, iclass 15, count 2 2006.286.01:23:36.44#ibcon#about to read 6, iclass 15, count 2 2006.286.01:23:36.44#ibcon#read 6, iclass 15, count 2 2006.286.01:23:36.44#ibcon#end of sib2, iclass 15, count 2 2006.286.01:23:36.44#ibcon#*mode == 0, iclass 15, count 2 2006.286.01:23:36.44#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.01:23:36.44#ibcon#[27=AT07-04\r\n] 2006.286.01:23:36.44#ibcon#*before write, iclass 15, count 2 2006.286.01:23:36.44#ibcon#enter sib2, iclass 15, count 2 2006.286.01:23:36.44#ibcon#flushed, iclass 15, count 2 2006.286.01:23:36.44#ibcon#about to write, iclass 15, count 2 2006.286.01:23:36.44#ibcon#wrote, iclass 15, count 2 2006.286.01:23:36.44#ibcon#about to read 3, iclass 15, count 2 2006.286.01:23:36.47#ibcon#read 3, iclass 15, count 2 2006.286.01:23:36.47#ibcon#about to read 4, iclass 15, count 2 2006.286.01:23:36.47#ibcon#read 4, iclass 15, count 2 2006.286.01:23:36.47#ibcon#about to read 5, iclass 15, count 2 2006.286.01:23:36.47#ibcon#read 5, iclass 15, count 2 2006.286.01:23:36.47#ibcon#about to read 6, iclass 15, count 2 2006.286.01:23:36.47#ibcon#read 6, iclass 15, count 2 2006.286.01:23:36.47#ibcon#end of sib2, iclass 15, count 2 2006.286.01:23:36.47#ibcon#*after write, iclass 15, count 2 2006.286.01:23:36.47#ibcon#*before return 0, iclass 15, count 2 2006.286.01:23:36.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:23:36.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:23:36.47#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.01:23:36.47#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:36.47#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:23:36.59#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:23:36.59#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:23:36.59#ibcon#enter wrdev, iclass 15, count 0 2006.286.01:23:36.59#ibcon#first serial, iclass 15, count 0 2006.286.01:23:36.59#ibcon#enter sib2, iclass 15, count 0 2006.286.01:23:36.59#ibcon#flushed, iclass 15, count 0 2006.286.01:23:36.59#ibcon#about to write, iclass 15, count 0 2006.286.01:23:36.59#ibcon#wrote, iclass 15, count 0 2006.286.01:23:36.59#ibcon#about to read 3, iclass 15, count 0 2006.286.01:23:36.61#ibcon#read 3, iclass 15, count 0 2006.286.01:23:36.61#ibcon#about to read 4, iclass 15, count 0 2006.286.01:23:36.61#ibcon#read 4, iclass 15, count 0 2006.286.01:23:36.61#ibcon#about to read 5, iclass 15, count 0 2006.286.01:23:36.61#ibcon#read 5, iclass 15, count 0 2006.286.01:23:36.61#ibcon#about to read 6, iclass 15, count 0 2006.286.01:23:36.61#ibcon#read 6, iclass 15, count 0 2006.286.01:23:36.61#ibcon#end of sib2, iclass 15, count 0 2006.286.01:23:36.61#ibcon#*mode == 0, iclass 15, count 0 2006.286.01:23:36.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.01:23:36.61#ibcon#[27=USB\r\n] 2006.286.01:23:36.61#ibcon#*before write, iclass 15, count 0 2006.286.01:23:36.61#ibcon#enter sib2, iclass 15, count 0 2006.286.01:23:36.61#ibcon#flushed, iclass 15, count 0 2006.286.01:23:36.61#ibcon#about to write, iclass 15, count 0 2006.286.01:23:36.61#ibcon#wrote, iclass 15, count 0 2006.286.01:23:36.61#ibcon#about to read 3, iclass 15, count 0 2006.286.01:23:36.64#ibcon#read 3, iclass 15, count 0 2006.286.01:23:36.64#ibcon#about to read 4, iclass 15, count 0 2006.286.01:23:36.64#ibcon#read 4, iclass 15, count 0 2006.286.01:23:36.64#ibcon#about to read 5, iclass 15, count 0 2006.286.01:23:36.64#ibcon#read 5, iclass 15, count 0 2006.286.01:23:36.64#ibcon#about to read 6, iclass 15, count 0 2006.286.01:23:36.64#ibcon#read 6, iclass 15, count 0 2006.286.01:23:36.64#ibcon#end of sib2, iclass 15, count 0 2006.286.01:23:36.64#ibcon#*after write, iclass 15, count 0 2006.286.01:23:36.64#ibcon#*before return 0, iclass 15, count 0 2006.286.01:23:36.64#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:23:36.64#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:23:36.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.01:23:36.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.01:23:36.64$vck44/vblo=8,744.99 2006.286.01:23:36.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.01:23:36.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.01:23:36.64#ibcon#ireg 17 cls_cnt 0 2006.286.01:23:36.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:23:36.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:23:36.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:23:36.64#ibcon#enter wrdev, iclass 17, count 0 2006.286.01:23:36.64#ibcon#first serial, iclass 17, count 0 2006.286.01:23:36.64#ibcon#enter sib2, iclass 17, count 0 2006.286.01:23:36.64#ibcon#flushed, iclass 17, count 0 2006.286.01:23:36.64#ibcon#about to write, iclass 17, count 0 2006.286.01:23:36.64#ibcon#wrote, iclass 17, count 0 2006.286.01:23:36.64#ibcon#about to read 3, iclass 17, count 0 2006.286.01:23:36.66#ibcon#read 3, iclass 17, count 0 2006.286.01:23:36.66#ibcon#about to read 4, iclass 17, count 0 2006.286.01:23:36.66#ibcon#read 4, iclass 17, count 0 2006.286.01:23:36.66#ibcon#about to read 5, iclass 17, count 0 2006.286.01:23:36.66#ibcon#read 5, iclass 17, count 0 2006.286.01:23:36.66#ibcon#about to read 6, iclass 17, count 0 2006.286.01:23:36.66#ibcon#read 6, iclass 17, count 0 2006.286.01:23:36.66#ibcon#end of sib2, iclass 17, count 0 2006.286.01:23:36.66#ibcon#*mode == 0, iclass 17, count 0 2006.286.01:23:36.66#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.01:23:36.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:23:36.66#ibcon#*before write, iclass 17, count 0 2006.286.01:23:36.66#ibcon#enter sib2, iclass 17, count 0 2006.286.01:23:36.66#ibcon#flushed, iclass 17, count 0 2006.286.01:23:36.66#ibcon#about to write, iclass 17, count 0 2006.286.01:23:36.66#ibcon#wrote, iclass 17, count 0 2006.286.01:23:36.66#ibcon#about to read 3, iclass 17, count 0 2006.286.01:23:36.70#ibcon#read 3, iclass 17, count 0 2006.286.01:23:36.70#ibcon#about to read 4, iclass 17, count 0 2006.286.01:23:36.70#ibcon#read 4, iclass 17, count 0 2006.286.01:23:36.70#ibcon#about to read 5, iclass 17, count 0 2006.286.01:23:36.70#ibcon#read 5, iclass 17, count 0 2006.286.01:23:36.70#ibcon#about to read 6, iclass 17, count 0 2006.286.01:23:36.70#ibcon#read 6, iclass 17, count 0 2006.286.01:23:36.70#ibcon#end of sib2, iclass 17, count 0 2006.286.01:23:36.70#ibcon#*after write, iclass 17, count 0 2006.286.01:23:36.70#ibcon#*before return 0, iclass 17, count 0 2006.286.01:23:36.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:23:36.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:23:36.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.01:23:36.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.01:23:36.70$vck44/vb=8,4 2006.286.01:23:36.70#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.01:23:36.70#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.01:23:36.70#ibcon#ireg 11 cls_cnt 2 2006.286.01:23:36.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:23:36.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:23:36.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:23:36.76#ibcon#enter wrdev, iclass 19, count 2 2006.286.01:23:36.76#ibcon#first serial, iclass 19, count 2 2006.286.01:23:36.76#ibcon#enter sib2, iclass 19, count 2 2006.286.01:23:36.76#ibcon#flushed, iclass 19, count 2 2006.286.01:23:36.76#ibcon#about to write, iclass 19, count 2 2006.286.01:23:36.76#ibcon#wrote, iclass 19, count 2 2006.286.01:23:36.76#ibcon#about to read 3, iclass 19, count 2 2006.286.01:23:36.78#ibcon#read 3, iclass 19, count 2 2006.286.01:23:36.78#ibcon#about to read 4, iclass 19, count 2 2006.286.01:23:36.78#ibcon#read 4, iclass 19, count 2 2006.286.01:23:36.78#ibcon#about to read 5, iclass 19, count 2 2006.286.01:23:36.78#ibcon#read 5, iclass 19, count 2 2006.286.01:23:36.78#ibcon#about to read 6, iclass 19, count 2 2006.286.01:23:36.78#ibcon#read 6, iclass 19, count 2 2006.286.01:23:36.78#ibcon#end of sib2, iclass 19, count 2 2006.286.01:23:36.78#ibcon#*mode == 0, iclass 19, count 2 2006.286.01:23:36.78#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.01:23:36.78#ibcon#[27=AT08-04\r\n] 2006.286.01:23:36.78#ibcon#*before write, iclass 19, count 2 2006.286.01:23:36.78#ibcon#enter sib2, iclass 19, count 2 2006.286.01:23:36.78#ibcon#flushed, iclass 19, count 2 2006.286.01:23:36.78#ibcon#about to write, iclass 19, count 2 2006.286.01:23:36.78#ibcon#wrote, iclass 19, count 2 2006.286.01:23:36.78#ibcon#about to read 3, iclass 19, count 2 2006.286.01:23:36.81#ibcon#read 3, iclass 19, count 2 2006.286.01:23:36.81#ibcon#about to read 4, iclass 19, count 2 2006.286.01:23:36.81#ibcon#read 4, iclass 19, count 2 2006.286.01:23:36.81#ibcon#about to read 5, iclass 19, count 2 2006.286.01:23:36.81#ibcon#read 5, iclass 19, count 2 2006.286.01:23:36.81#ibcon#about to read 6, iclass 19, count 2 2006.286.01:23:36.81#ibcon#read 6, iclass 19, count 2 2006.286.01:23:36.81#ibcon#end of sib2, iclass 19, count 2 2006.286.01:23:36.81#ibcon#*after write, iclass 19, count 2 2006.286.01:23:36.81#ibcon#*before return 0, iclass 19, count 2 2006.286.01:23:36.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:23:36.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:23:36.81#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.01:23:36.81#ibcon#ireg 7 cls_cnt 0 2006.286.01:23:36.81#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:23:36.93#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:23:36.93#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:23:36.93#ibcon#enter wrdev, iclass 19, count 0 2006.286.01:23:36.93#ibcon#first serial, iclass 19, count 0 2006.286.01:23:36.93#ibcon#enter sib2, iclass 19, count 0 2006.286.01:23:36.93#ibcon#flushed, iclass 19, count 0 2006.286.01:23:36.93#ibcon#about to write, iclass 19, count 0 2006.286.01:23:36.93#ibcon#wrote, iclass 19, count 0 2006.286.01:23:36.93#ibcon#about to read 3, iclass 19, count 0 2006.286.01:23:36.95#ibcon#read 3, iclass 19, count 0 2006.286.01:23:36.95#ibcon#about to read 4, iclass 19, count 0 2006.286.01:23:36.95#ibcon#read 4, iclass 19, count 0 2006.286.01:23:36.95#ibcon#about to read 5, iclass 19, count 0 2006.286.01:23:36.95#ibcon#read 5, iclass 19, count 0 2006.286.01:23:36.95#ibcon#about to read 6, iclass 19, count 0 2006.286.01:23:36.95#ibcon#read 6, iclass 19, count 0 2006.286.01:23:36.95#ibcon#end of sib2, iclass 19, count 0 2006.286.01:23:36.95#ibcon#*mode == 0, iclass 19, count 0 2006.286.01:23:36.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.01:23:36.95#ibcon#[27=USB\r\n] 2006.286.01:23:36.95#ibcon#*before write, iclass 19, count 0 2006.286.01:23:36.95#ibcon#enter sib2, iclass 19, count 0 2006.286.01:23:36.95#ibcon#flushed, iclass 19, count 0 2006.286.01:23:36.95#ibcon#about to write, iclass 19, count 0 2006.286.01:23:36.95#ibcon#wrote, iclass 19, count 0 2006.286.01:23:36.95#ibcon#about to read 3, iclass 19, count 0 2006.286.01:23:36.98#ibcon#read 3, iclass 19, count 0 2006.286.01:23:36.98#ibcon#about to read 4, iclass 19, count 0 2006.286.01:23:36.98#ibcon#read 4, iclass 19, count 0 2006.286.01:23:36.98#ibcon#about to read 5, iclass 19, count 0 2006.286.01:23:36.98#ibcon#read 5, iclass 19, count 0 2006.286.01:23:36.98#ibcon#about to read 6, iclass 19, count 0 2006.286.01:23:36.98#ibcon#read 6, iclass 19, count 0 2006.286.01:23:36.98#ibcon#end of sib2, iclass 19, count 0 2006.286.01:23:36.98#ibcon#*after write, iclass 19, count 0 2006.286.01:23:36.98#ibcon#*before return 0, iclass 19, count 0 2006.286.01:23:36.98#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:23:36.98#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:23:36.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.01:23:36.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.01:23:36.98$vck44/vabw=wide 2006.286.01:23:36.98#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.01:23:36.98#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.01:23:36.98#ibcon#ireg 8 cls_cnt 0 2006.286.01:23:36.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:23:36.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:23:36.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:23:36.98#ibcon#enter wrdev, iclass 21, count 0 2006.286.01:23:36.98#ibcon#first serial, iclass 21, count 0 2006.286.01:23:36.98#ibcon#enter sib2, iclass 21, count 0 2006.286.01:23:36.98#ibcon#flushed, iclass 21, count 0 2006.286.01:23:36.98#ibcon#about to write, iclass 21, count 0 2006.286.01:23:36.98#ibcon#wrote, iclass 21, count 0 2006.286.01:23:36.98#ibcon#about to read 3, iclass 21, count 0 2006.286.01:23:37.00#ibcon#read 3, iclass 21, count 0 2006.286.01:23:37.00#ibcon#about to read 4, iclass 21, count 0 2006.286.01:23:37.00#ibcon#read 4, iclass 21, count 0 2006.286.01:23:37.00#ibcon#about to read 5, iclass 21, count 0 2006.286.01:23:37.00#ibcon#read 5, iclass 21, count 0 2006.286.01:23:37.00#ibcon#about to read 6, iclass 21, count 0 2006.286.01:23:37.00#ibcon#read 6, iclass 21, count 0 2006.286.01:23:37.00#ibcon#end of sib2, iclass 21, count 0 2006.286.01:23:37.00#ibcon#*mode == 0, iclass 21, count 0 2006.286.01:23:37.00#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.01:23:37.00#ibcon#[25=BW32\r\n] 2006.286.01:23:37.00#ibcon#*before write, iclass 21, count 0 2006.286.01:23:37.00#ibcon#enter sib2, iclass 21, count 0 2006.286.01:23:37.00#ibcon#flushed, iclass 21, count 0 2006.286.01:23:37.00#ibcon#about to write, iclass 21, count 0 2006.286.01:23:37.00#ibcon#wrote, iclass 21, count 0 2006.286.01:23:37.00#ibcon#about to read 3, iclass 21, count 0 2006.286.01:23:37.03#ibcon#read 3, iclass 21, count 0 2006.286.01:23:37.03#ibcon#about to read 4, iclass 21, count 0 2006.286.01:23:37.03#ibcon#read 4, iclass 21, count 0 2006.286.01:23:37.03#ibcon#about to read 5, iclass 21, count 0 2006.286.01:23:37.03#ibcon#read 5, iclass 21, count 0 2006.286.01:23:37.03#ibcon#about to read 6, iclass 21, count 0 2006.286.01:23:37.03#ibcon#read 6, iclass 21, count 0 2006.286.01:23:37.03#ibcon#end of sib2, iclass 21, count 0 2006.286.01:23:37.03#ibcon#*after write, iclass 21, count 0 2006.286.01:23:37.03#ibcon#*before return 0, iclass 21, count 0 2006.286.01:23:37.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:23:37.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:23:37.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.01:23:37.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.01:23:37.03$vck44/vbbw=wide 2006.286.01:23:37.03#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.01:23:37.03#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.01:23:37.03#ibcon#ireg 8 cls_cnt 0 2006.286.01:23:37.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:23:37.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:23:37.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:23:37.10#ibcon#enter wrdev, iclass 23, count 0 2006.286.01:23:37.10#ibcon#first serial, iclass 23, count 0 2006.286.01:23:37.10#ibcon#enter sib2, iclass 23, count 0 2006.286.01:23:37.10#ibcon#flushed, iclass 23, count 0 2006.286.01:23:37.10#ibcon#about to write, iclass 23, count 0 2006.286.01:23:37.10#ibcon#wrote, iclass 23, count 0 2006.286.01:23:37.10#ibcon#about to read 3, iclass 23, count 0 2006.286.01:23:37.12#ibcon#read 3, iclass 23, count 0 2006.286.01:23:37.12#ibcon#about to read 4, iclass 23, count 0 2006.286.01:23:37.12#ibcon#read 4, iclass 23, count 0 2006.286.01:23:37.12#ibcon#about to read 5, iclass 23, count 0 2006.286.01:23:37.12#ibcon#read 5, iclass 23, count 0 2006.286.01:23:37.12#ibcon#about to read 6, iclass 23, count 0 2006.286.01:23:37.12#ibcon#read 6, iclass 23, count 0 2006.286.01:23:37.12#ibcon#end of sib2, iclass 23, count 0 2006.286.01:23:37.12#ibcon#*mode == 0, iclass 23, count 0 2006.286.01:23:37.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.01:23:37.12#ibcon#[27=BW32\r\n] 2006.286.01:23:37.12#ibcon#*before write, iclass 23, count 0 2006.286.01:23:37.12#ibcon#enter sib2, iclass 23, count 0 2006.286.01:23:37.12#ibcon#flushed, iclass 23, count 0 2006.286.01:23:37.12#ibcon#about to write, iclass 23, count 0 2006.286.01:23:37.12#ibcon#wrote, iclass 23, count 0 2006.286.01:23:37.12#ibcon#about to read 3, iclass 23, count 0 2006.286.01:23:37.15#ibcon#read 3, iclass 23, count 0 2006.286.01:23:37.15#ibcon#about to read 4, iclass 23, count 0 2006.286.01:23:37.15#ibcon#read 4, iclass 23, count 0 2006.286.01:23:37.15#ibcon#about to read 5, iclass 23, count 0 2006.286.01:23:37.15#ibcon#read 5, iclass 23, count 0 2006.286.01:23:37.15#ibcon#about to read 6, iclass 23, count 0 2006.286.01:23:37.15#ibcon#read 6, iclass 23, count 0 2006.286.01:23:37.15#ibcon#end of sib2, iclass 23, count 0 2006.286.01:23:37.15#ibcon#*after write, iclass 23, count 0 2006.286.01:23:37.15#ibcon#*before return 0, iclass 23, count 0 2006.286.01:23:37.15#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:23:37.15#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:23:37.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.01:23:37.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.01:23:37.15$setupk4/ifdk4 2006.286.01:23:37.15$ifdk4/lo= 2006.286.01:23:37.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:23:37.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:23:37.15$ifdk4/patch= 2006.286.01:23:37.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:23:37.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:23:37.15$setupk4/!*+20s 2006.286.01:23:38.06#abcon#<5=/03 2.8 7.1 21.09 831016.2\r\n> 2006.286.01:23:38.08#abcon#{5=INTERFACE CLEAR} 2006.286.01:23:38.14#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:23:48.23#abcon#<5=/03 2.7 7.1 21.09 841016.2\r\n> 2006.286.01:23:48.25#abcon#{5=INTERFACE CLEAR} 2006.286.01:23:48.31#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:23:51.66$setupk4/"tpicd 2006.286.01:23:51.66$setupk4/echo=off 2006.286.01:23:51.66$setupk4/xlog=off 2006.286.01:23:51.66:!2006.286.01:26:47 2006.286.01:23:56.13#trakl#Source acquired 2006.286.01:23:57.13#flagr#flagr/antenna,acquired 2006.286.01:24:56.13#trakl#Off source 2006.286.01:24:56.13?ERROR st -7 Antenna off-source! 2006.286.01:24:56.13#trakl#az 155.169 el 5.840 azerr*cos(el) 0.0167 elerr -0.0019 2006.286.01:24:57.13#flagr#flagr/antenna,off-source 2006.286.01:25:02.13#trakl#Source re-acquired 2006.286.01:25:03.13#flagr#flagr/antenna,re-acquired 2006.286.01:26:47.02:preob 2006.286.01:26:48.15/onsource/TRACKING 2006.286.01:26:48.15:!2006.286.01:26:57 2006.286.01:26:57.02:"tape 2006.286.01:26:57.02:"st=record 2006.286.01:26:57.02:data_valid=on 2006.286.01:26:57.02:midob 2006.286.01:26:58.15/onsource/TRACKING 2006.286.01:26:58.15/wx/21.06,1016.2,83 2006.286.01:26:58.33/cable/+6.5037E-03 2006.286.01:26:59.42/va/01,07,usb,yes,43,46 2006.286.01:26:59.42/va/02,06,usb,yes,43,44 2006.286.01:26:59.43/va/03,07,usb,yes,42,45 2006.286.01:26:59.43/va/04,06,usb,yes,44,46 2006.286.01:26:59.43/va/05,03,usb,yes,44,44 2006.286.01:26:59.43/va/06,04,usb,yes,40,39 2006.286.01:26:59.43/va/07,04,usb,yes,41,41 2006.286.01:26:59.43/va/08,03,usb,yes,41,50 2006.286.01:26:59.66/valo/01,524.99,yes,locked 2006.286.01:26:59.66/valo/02,534.99,yes,locked 2006.286.01:26:59.66/valo/03,564.99,yes,locked 2006.286.01:26:59.66/valo/04,624.99,yes,locked 2006.286.01:26:59.66/valo/05,734.99,yes,locked 2006.286.01:26:59.66/valo/06,814.99,yes,locked 2006.286.01:26:59.66/valo/07,864.99,yes,locked 2006.286.01:26:59.66/valo/08,884.99,yes,locked 2006.286.01:27:00.74/vb/01,04,usb,yes,34,44 2006.286.01:27:00.75/vb/02,05,usb,yes,32,46 2006.286.01:27:00.75/vb/03,04,usb,yes,34,39 2006.286.01:27:00.75/vb/04,05,usb,yes,34,33 2006.286.01:27:00.75/vb/05,04,usb,yes,30,33 2006.286.01:27:00.75/vb/06,03,usb,yes,43,39 2006.286.01:27:00.75/vb/07,04,usb,yes,35,35 2006.286.01:27:00.75/vb/08,04,usb,yes,32,36 2006.286.01:27:00.97/vblo/01,629.99,yes,locked 2006.286.01:27:00.98/vblo/02,634.99,yes,locked 2006.286.01:27:00.98/vblo/03,649.99,yes,locked 2006.286.01:27:00.98/vblo/04,679.99,yes,locked 2006.286.01:27:00.98/vblo/05,709.99,yes,locked 2006.286.01:27:00.98/vblo/06,719.99,yes,locked 2006.286.01:27:00.98/vblo/07,734.99,yes,locked 2006.286.01:27:00.98/vblo/08,744.99,yes,locked 2006.286.01:27:01.12/vabw/8 2006.286.01:27:01.27/vbbw/8 2006.286.01:27:01.36/xfe/off,on,12.0 2006.286.01:27:01.75/ifatt/23,28,28,28 2006.286.01:27:02.07/fmout-gps/S +2.79E-07 2006.286.01:27:02.09:!2006.286.01:27:37 2006.286.01:27:37.02:data_valid=off 2006.286.01:27:37.02:"et 2006.286.01:27:37.02:!+3s 2006.286.01:27:40.04:"tape 2006.286.01:27:40.05:postob 2006.286.01:27:40.18/cable/+6.5033E-03 2006.286.01:27:40.19/wx/21.05,1016.2,83 2006.286.01:27:40.24/fmout-gps/S +2.78E-07 2006.286.01:27:40.25:scan_name=286-0135,jd0610,50 2006.286.01:27:40.25:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.286.01:27:41.15#flagr#flagr/antenna,new-source 2006.286.01:27:41.15:checkk5 2006.286.01:27:41.55/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:27:42.16/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:27:42.53/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:27:42.90/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:27:43.52/chk_obsdata//k5ts1/T2860126??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:27:43.94/chk_obsdata//k5ts2/T2860126??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:27:44.71/chk_obsdata//k5ts3/T2860126??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:27:45.15/chk_obsdata//k5ts4/T2860126??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:27:46.05/k5log//k5ts1_log_newline 2006.286.01:27:46.81/k5log//k5ts2_log_newline 2006.286.01:27:47.71/k5log//k5ts3_log_newline 2006.286.01:27:48.59/k5log//k5ts4_log_newline 2006.286.01:27:48.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:27:48.61:setupk4=1 2006.286.01:27:48.61$setupk4/echo=on 2006.286.01:27:48.61$setupk4/pcalon 2006.286.01:27:48.61$pcalon/"no phase cal control is implemented here 2006.286.01:27:48.61$setupk4/"tpicd=stop 2006.286.01:27:48.61$setupk4/"rec=synch_on 2006.286.01:27:48.61$setupk4/"rec_mode=128 2006.286.01:27:48.61$setupk4/!* 2006.286.01:27:48.61$setupk4/recpk4 2006.286.01:27:48.61$recpk4/recpatch= 2006.286.01:27:48.61$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:27:48.61$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:27:48.61$setupk4/vck44 2006.286.01:27:48.61$vck44/valo=1,524.99 2006.286.01:27:48.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.01:27:48.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.01:27:48.61#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:48.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:27:48.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:27:48.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:27:48.61#ibcon#enter wrdev, iclass 22, count 0 2006.286.01:27:48.61#ibcon#first serial, iclass 22, count 0 2006.286.01:27:48.61#ibcon#enter sib2, iclass 22, count 0 2006.286.01:27:48.61#ibcon#flushed, iclass 22, count 0 2006.286.01:27:48.61#ibcon#about to write, iclass 22, count 0 2006.286.01:27:48.61#ibcon#wrote, iclass 22, count 0 2006.286.01:27:48.61#ibcon#about to read 3, iclass 22, count 0 2006.286.01:27:48.63#ibcon#read 3, iclass 22, count 0 2006.286.01:27:48.63#ibcon#about to read 4, iclass 22, count 0 2006.286.01:27:48.63#ibcon#read 4, iclass 22, count 0 2006.286.01:27:48.63#ibcon#about to read 5, iclass 22, count 0 2006.286.01:27:48.63#ibcon#read 5, iclass 22, count 0 2006.286.01:27:48.63#ibcon#about to read 6, iclass 22, count 0 2006.286.01:27:48.63#ibcon#read 6, iclass 22, count 0 2006.286.01:27:48.63#ibcon#end of sib2, iclass 22, count 0 2006.286.01:27:48.63#ibcon#*mode == 0, iclass 22, count 0 2006.286.01:27:48.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.01:27:48.63#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:27:48.63#ibcon#*before write, iclass 22, count 0 2006.286.01:27:48.63#ibcon#enter sib2, iclass 22, count 0 2006.286.01:27:48.63#ibcon#flushed, iclass 22, count 0 2006.286.01:27:48.63#ibcon#about to write, iclass 22, count 0 2006.286.01:27:48.63#ibcon#wrote, iclass 22, count 0 2006.286.01:27:48.63#ibcon#about to read 3, iclass 22, count 0 2006.286.01:27:48.68#ibcon#read 3, iclass 22, count 0 2006.286.01:27:48.68#ibcon#about to read 4, iclass 22, count 0 2006.286.01:27:48.68#ibcon#read 4, iclass 22, count 0 2006.286.01:27:48.68#ibcon#about to read 5, iclass 22, count 0 2006.286.01:27:48.68#ibcon#read 5, iclass 22, count 0 2006.286.01:27:48.68#ibcon#about to read 6, iclass 22, count 0 2006.286.01:27:48.68#ibcon#read 6, iclass 22, count 0 2006.286.01:27:48.68#ibcon#end of sib2, iclass 22, count 0 2006.286.01:27:48.68#ibcon#*after write, iclass 22, count 0 2006.286.01:27:48.68#ibcon#*before return 0, iclass 22, count 0 2006.286.01:27:48.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:27:48.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:27:48.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.01:27:48.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.01:27:48.69$vck44/va=1,7 2006.286.01:27:48.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.01:27:48.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.01:27:48.69#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:48.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:27:48.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:27:48.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:27:48.69#ibcon#enter wrdev, iclass 24, count 2 2006.286.01:27:48.69#ibcon#first serial, iclass 24, count 2 2006.286.01:27:48.69#ibcon#enter sib2, iclass 24, count 2 2006.286.01:27:48.69#ibcon#flushed, iclass 24, count 2 2006.286.01:27:48.69#ibcon#about to write, iclass 24, count 2 2006.286.01:27:48.69#ibcon#wrote, iclass 24, count 2 2006.286.01:27:48.69#ibcon#about to read 3, iclass 24, count 2 2006.286.01:27:48.70#ibcon#read 3, iclass 24, count 2 2006.286.01:27:48.70#ibcon#about to read 4, iclass 24, count 2 2006.286.01:27:48.70#ibcon#read 4, iclass 24, count 2 2006.286.01:27:48.70#ibcon#about to read 5, iclass 24, count 2 2006.286.01:27:48.70#ibcon#read 5, iclass 24, count 2 2006.286.01:27:48.70#ibcon#about to read 6, iclass 24, count 2 2006.286.01:27:48.70#ibcon#read 6, iclass 24, count 2 2006.286.01:27:48.70#ibcon#end of sib2, iclass 24, count 2 2006.286.01:27:48.70#ibcon#*mode == 0, iclass 24, count 2 2006.286.01:27:48.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.01:27:48.70#ibcon#[25=AT01-07\r\n] 2006.286.01:27:48.70#ibcon#*before write, iclass 24, count 2 2006.286.01:27:48.70#ibcon#enter sib2, iclass 24, count 2 2006.286.01:27:48.70#ibcon#flushed, iclass 24, count 2 2006.286.01:27:48.70#ibcon#about to write, iclass 24, count 2 2006.286.01:27:48.70#ibcon#wrote, iclass 24, count 2 2006.286.01:27:48.70#ibcon#about to read 3, iclass 24, count 2 2006.286.01:27:48.73#ibcon#read 3, iclass 24, count 2 2006.286.01:27:48.73#ibcon#about to read 4, iclass 24, count 2 2006.286.01:27:48.73#ibcon#read 4, iclass 24, count 2 2006.286.01:27:48.73#ibcon#about to read 5, iclass 24, count 2 2006.286.01:27:48.73#ibcon#read 5, iclass 24, count 2 2006.286.01:27:48.73#ibcon#about to read 6, iclass 24, count 2 2006.286.01:27:48.73#ibcon#read 6, iclass 24, count 2 2006.286.01:27:48.73#ibcon#end of sib2, iclass 24, count 2 2006.286.01:27:48.73#ibcon#*after write, iclass 24, count 2 2006.286.01:27:48.73#ibcon#*before return 0, iclass 24, count 2 2006.286.01:27:48.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:27:48.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:27:48.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.01:27:48.73#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:48.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:27:48.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:27:48.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:27:48.85#ibcon#enter wrdev, iclass 24, count 0 2006.286.01:27:48.85#ibcon#first serial, iclass 24, count 0 2006.286.01:27:48.85#ibcon#enter sib2, iclass 24, count 0 2006.286.01:27:48.85#ibcon#flushed, iclass 24, count 0 2006.286.01:27:48.85#ibcon#about to write, iclass 24, count 0 2006.286.01:27:48.85#ibcon#wrote, iclass 24, count 0 2006.286.01:27:48.85#ibcon#about to read 3, iclass 24, count 0 2006.286.01:27:48.87#ibcon#read 3, iclass 24, count 0 2006.286.01:27:48.87#ibcon#about to read 4, iclass 24, count 0 2006.286.01:27:48.87#ibcon#read 4, iclass 24, count 0 2006.286.01:27:48.87#ibcon#about to read 5, iclass 24, count 0 2006.286.01:27:48.87#ibcon#read 5, iclass 24, count 0 2006.286.01:27:48.87#ibcon#about to read 6, iclass 24, count 0 2006.286.01:27:48.87#ibcon#read 6, iclass 24, count 0 2006.286.01:27:48.87#ibcon#end of sib2, iclass 24, count 0 2006.286.01:27:48.87#ibcon#*mode == 0, iclass 24, count 0 2006.286.01:27:48.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.01:27:48.87#ibcon#[25=USB\r\n] 2006.286.01:27:48.87#ibcon#*before write, iclass 24, count 0 2006.286.01:27:48.87#ibcon#enter sib2, iclass 24, count 0 2006.286.01:27:48.87#ibcon#flushed, iclass 24, count 0 2006.286.01:27:48.87#ibcon#about to write, iclass 24, count 0 2006.286.01:27:48.87#ibcon#wrote, iclass 24, count 0 2006.286.01:27:48.87#ibcon#about to read 3, iclass 24, count 0 2006.286.01:27:48.90#ibcon#read 3, iclass 24, count 0 2006.286.01:27:48.90#ibcon#about to read 4, iclass 24, count 0 2006.286.01:27:48.90#ibcon#read 4, iclass 24, count 0 2006.286.01:27:48.90#ibcon#about to read 5, iclass 24, count 0 2006.286.01:27:48.90#ibcon#read 5, iclass 24, count 0 2006.286.01:27:48.90#ibcon#about to read 6, iclass 24, count 0 2006.286.01:27:48.90#ibcon#read 6, iclass 24, count 0 2006.286.01:27:48.90#ibcon#end of sib2, iclass 24, count 0 2006.286.01:27:48.90#ibcon#*after write, iclass 24, count 0 2006.286.01:27:48.90#ibcon#*before return 0, iclass 24, count 0 2006.286.01:27:48.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:27:48.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:27:48.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.01:27:48.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.01:27:48.91$vck44/valo=2,534.99 2006.286.01:27:48.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.01:27:48.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.01:27:48.91#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:48.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:27:48.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:27:48.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:27:48.91#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:27:48.91#ibcon#first serial, iclass 26, count 0 2006.286.01:27:48.91#ibcon#enter sib2, iclass 26, count 0 2006.286.01:27:48.91#ibcon#flushed, iclass 26, count 0 2006.286.01:27:48.91#ibcon#about to write, iclass 26, count 0 2006.286.01:27:48.91#ibcon#wrote, iclass 26, count 0 2006.286.01:27:48.91#ibcon#about to read 3, iclass 26, count 0 2006.286.01:27:48.92#ibcon#read 3, iclass 26, count 0 2006.286.01:27:48.92#ibcon#about to read 4, iclass 26, count 0 2006.286.01:27:48.92#ibcon#read 4, iclass 26, count 0 2006.286.01:27:48.92#ibcon#about to read 5, iclass 26, count 0 2006.286.01:27:48.92#ibcon#read 5, iclass 26, count 0 2006.286.01:27:48.92#ibcon#about to read 6, iclass 26, count 0 2006.286.01:27:48.92#ibcon#read 6, iclass 26, count 0 2006.286.01:27:48.92#ibcon#end of sib2, iclass 26, count 0 2006.286.01:27:48.92#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:27:48.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:27:48.92#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:27:48.92#ibcon#*before write, iclass 26, count 0 2006.286.01:27:48.92#ibcon#enter sib2, iclass 26, count 0 2006.286.01:27:48.92#ibcon#flushed, iclass 26, count 0 2006.286.01:27:48.92#ibcon#about to write, iclass 26, count 0 2006.286.01:27:48.92#ibcon#wrote, iclass 26, count 0 2006.286.01:27:48.92#ibcon#about to read 3, iclass 26, count 0 2006.286.01:27:48.96#ibcon#read 3, iclass 26, count 0 2006.286.01:27:48.96#ibcon#about to read 4, iclass 26, count 0 2006.286.01:27:48.96#ibcon#read 4, iclass 26, count 0 2006.286.01:27:48.96#ibcon#about to read 5, iclass 26, count 0 2006.286.01:27:48.96#ibcon#read 5, iclass 26, count 0 2006.286.01:27:48.96#ibcon#about to read 6, iclass 26, count 0 2006.286.01:27:48.96#ibcon#read 6, iclass 26, count 0 2006.286.01:27:48.96#ibcon#end of sib2, iclass 26, count 0 2006.286.01:27:48.96#ibcon#*after write, iclass 26, count 0 2006.286.01:27:48.96#ibcon#*before return 0, iclass 26, count 0 2006.286.01:27:48.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:27:48.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:27:48.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:27:48.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:27:48.97$vck44/va=2,6 2006.286.01:27:48.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.01:27:48.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.01:27:48.97#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:48.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:27:49.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:27:49.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:27:49.01#ibcon#enter wrdev, iclass 28, count 2 2006.286.01:27:49.01#ibcon#first serial, iclass 28, count 2 2006.286.01:27:49.01#ibcon#enter sib2, iclass 28, count 2 2006.286.01:27:49.01#ibcon#flushed, iclass 28, count 2 2006.286.01:27:49.01#ibcon#about to write, iclass 28, count 2 2006.286.01:27:49.01#ibcon#wrote, iclass 28, count 2 2006.286.01:27:49.01#ibcon#about to read 3, iclass 28, count 2 2006.286.01:27:49.03#ibcon#read 3, iclass 28, count 2 2006.286.01:27:49.03#ibcon#about to read 4, iclass 28, count 2 2006.286.01:27:49.03#ibcon#read 4, iclass 28, count 2 2006.286.01:27:49.03#ibcon#about to read 5, iclass 28, count 2 2006.286.01:27:49.03#ibcon#read 5, iclass 28, count 2 2006.286.01:27:49.03#ibcon#about to read 6, iclass 28, count 2 2006.286.01:27:49.03#ibcon#read 6, iclass 28, count 2 2006.286.01:27:49.03#ibcon#end of sib2, iclass 28, count 2 2006.286.01:27:49.03#ibcon#*mode == 0, iclass 28, count 2 2006.286.01:27:49.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.01:27:49.03#ibcon#[25=AT02-06\r\n] 2006.286.01:27:49.03#ibcon#*before write, iclass 28, count 2 2006.286.01:27:49.03#ibcon#enter sib2, iclass 28, count 2 2006.286.01:27:49.03#ibcon#flushed, iclass 28, count 2 2006.286.01:27:49.03#ibcon#about to write, iclass 28, count 2 2006.286.01:27:49.03#ibcon#wrote, iclass 28, count 2 2006.286.01:27:49.03#ibcon#about to read 3, iclass 28, count 2 2006.286.01:27:49.06#ibcon#read 3, iclass 28, count 2 2006.286.01:27:49.06#ibcon#about to read 4, iclass 28, count 2 2006.286.01:27:49.06#ibcon#read 4, iclass 28, count 2 2006.286.01:27:49.06#ibcon#about to read 5, iclass 28, count 2 2006.286.01:27:49.06#ibcon#read 5, iclass 28, count 2 2006.286.01:27:49.06#ibcon#about to read 6, iclass 28, count 2 2006.286.01:27:49.06#ibcon#read 6, iclass 28, count 2 2006.286.01:27:49.06#ibcon#end of sib2, iclass 28, count 2 2006.286.01:27:49.06#ibcon#*after write, iclass 28, count 2 2006.286.01:27:49.06#ibcon#*before return 0, iclass 28, count 2 2006.286.01:27:49.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:27:49.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:27:49.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.01:27:49.06#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:49.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:27:49.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:27:49.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:27:49.18#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:27:49.18#ibcon#first serial, iclass 28, count 0 2006.286.01:27:49.18#ibcon#enter sib2, iclass 28, count 0 2006.286.01:27:49.18#ibcon#flushed, iclass 28, count 0 2006.286.01:27:49.18#ibcon#about to write, iclass 28, count 0 2006.286.01:27:49.18#ibcon#wrote, iclass 28, count 0 2006.286.01:27:49.18#ibcon#about to read 3, iclass 28, count 0 2006.286.01:27:49.20#ibcon#read 3, iclass 28, count 0 2006.286.01:27:49.20#ibcon#about to read 4, iclass 28, count 0 2006.286.01:27:49.20#ibcon#read 4, iclass 28, count 0 2006.286.01:27:49.20#ibcon#about to read 5, iclass 28, count 0 2006.286.01:27:49.20#ibcon#read 5, iclass 28, count 0 2006.286.01:27:49.20#ibcon#about to read 6, iclass 28, count 0 2006.286.01:27:49.20#ibcon#read 6, iclass 28, count 0 2006.286.01:27:49.20#ibcon#end of sib2, iclass 28, count 0 2006.286.01:27:49.20#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:27:49.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:27:49.20#ibcon#[25=USB\r\n] 2006.286.01:27:49.20#ibcon#*before write, iclass 28, count 0 2006.286.01:27:49.20#ibcon#enter sib2, iclass 28, count 0 2006.286.01:27:49.20#ibcon#flushed, iclass 28, count 0 2006.286.01:27:49.20#ibcon#about to write, iclass 28, count 0 2006.286.01:27:49.20#ibcon#wrote, iclass 28, count 0 2006.286.01:27:49.20#ibcon#about to read 3, iclass 28, count 0 2006.286.01:27:49.23#ibcon#read 3, iclass 28, count 0 2006.286.01:27:49.24#ibcon#about to read 4, iclass 28, count 0 2006.286.01:27:49.24#ibcon#read 4, iclass 28, count 0 2006.286.01:27:49.24#ibcon#about to read 5, iclass 28, count 0 2006.286.01:27:49.24#ibcon#read 5, iclass 28, count 0 2006.286.01:27:49.24#ibcon#about to read 6, iclass 28, count 0 2006.286.01:27:49.24#ibcon#read 6, iclass 28, count 0 2006.286.01:27:49.24#ibcon#end of sib2, iclass 28, count 0 2006.286.01:27:49.24#ibcon#*after write, iclass 28, count 0 2006.286.01:27:49.24#ibcon#*before return 0, iclass 28, count 0 2006.286.01:27:49.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:27:49.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:27:49.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:27:49.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:27:49.24$vck44/valo=3,564.99 2006.286.01:27:49.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.01:27:49.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.01:27:49.24#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:49.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:27:49.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:27:49.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:27:49.24#ibcon#enter wrdev, iclass 30, count 0 2006.286.01:27:49.24#ibcon#first serial, iclass 30, count 0 2006.286.01:27:49.24#ibcon#enter sib2, iclass 30, count 0 2006.286.01:27:49.24#ibcon#flushed, iclass 30, count 0 2006.286.01:27:49.24#ibcon#about to write, iclass 30, count 0 2006.286.01:27:49.24#ibcon#wrote, iclass 30, count 0 2006.286.01:27:49.24#ibcon#about to read 3, iclass 30, count 0 2006.286.01:27:49.25#ibcon#read 3, iclass 30, count 0 2006.286.01:27:49.25#ibcon#about to read 4, iclass 30, count 0 2006.286.01:27:49.25#ibcon#read 4, iclass 30, count 0 2006.286.01:27:49.25#ibcon#about to read 5, iclass 30, count 0 2006.286.01:27:49.25#ibcon#read 5, iclass 30, count 0 2006.286.01:27:49.25#ibcon#about to read 6, iclass 30, count 0 2006.286.01:27:49.25#ibcon#read 6, iclass 30, count 0 2006.286.01:27:49.25#ibcon#end of sib2, iclass 30, count 0 2006.286.01:27:49.25#ibcon#*mode == 0, iclass 30, count 0 2006.286.01:27:49.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.01:27:49.25#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:27:49.25#ibcon#*before write, iclass 30, count 0 2006.286.01:27:49.25#ibcon#enter sib2, iclass 30, count 0 2006.286.01:27:49.25#ibcon#flushed, iclass 30, count 0 2006.286.01:27:49.25#ibcon#about to write, iclass 30, count 0 2006.286.01:27:49.25#ibcon#wrote, iclass 30, count 0 2006.286.01:27:49.25#ibcon#about to read 3, iclass 30, count 0 2006.286.01:27:49.29#ibcon#read 3, iclass 30, count 0 2006.286.01:27:49.29#ibcon#about to read 4, iclass 30, count 0 2006.286.01:27:49.29#ibcon#read 4, iclass 30, count 0 2006.286.01:27:49.29#ibcon#about to read 5, iclass 30, count 0 2006.286.01:27:49.29#ibcon#read 5, iclass 30, count 0 2006.286.01:27:49.29#ibcon#about to read 6, iclass 30, count 0 2006.286.01:27:49.29#ibcon#read 6, iclass 30, count 0 2006.286.01:27:49.29#ibcon#end of sib2, iclass 30, count 0 2006.286.01:27:49.29#ibcon#*after write, iclass 30, count 0 2006.286.01:27:49.29#ibcon#*before return 0, iclass 30, count 0 2006.286.01:27:49.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:27:49.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:27:49.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.01:27:49.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.01:27:49.30$vck44/va=3,7 2006.286.01:27:49.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.01:27:49.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.01:27:49.30#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:49.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:27:49.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:27:49.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:27:49.35#ibcon#enter wrdev, iclass 32, count 2 2006.286.01:27:49.35#ibcon#first serial, iclass 32, count 2 2006.286.01:27:49.35#ibcon#enter sib2, iclass 32, count 2 2006.286.01:27:49.35#ibcon#flushed, iclass 32, count 2 2006.286.01:27:49.35#ibcon#about to write, iclass 32, count 2 2006.286.01:27:49.35#ibcon#wrote, iclass 32, count 2 2006.286.01:27:49.35#ibcon#about to read 3, iclass 32, count 2 2006.286.01:27:49.37#ibcon#read 3, iclass 32, count 2 2006.286.01:27:49.37#ibcon#about to read 4, iclass 32, count 2 2006.286.01:27:49.37#ibcon#read 4, iclass 32, count 2 2006.286.01:27:49.37#ibcon#about to read 5, iclass 32, count 2 2006.286.01:27:49.37#ibcon#read 5, iclass 32, count 2 2006.286.01:27:49.37#ibcon#about to read 6, iclass 32, count 2 2006.286.01:27:49.37#ibcon#read 6, iclass 32, count 2 2006.286.01:27:49.37#ibcon#end of sib2, iclass 32, count 2 2006.286.01:27:49.37#ibcon#*mode == 0, iclass 32, count 2 2006.286.01:27:49.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.01:27:49.37#ibcon#[25=AT03-07\r\n] 2006.286.01:27:49.37#ibcon#*before write, iclass 32, count 2 2006.286.01:27:49.37#ibcon#enter sib2, iclass 32, count 2 2006.286.01:27:49.37#ibcon#flushed, iclass 32, count 2 2006.286.01:27:49.37#ibcon#about to write, iclass 32, count 2 2006.286.01:27:49.37#ibcon#wrote, iclass 32, count 2 2006.286.01:27:49.37#ibcon#about to read 3, iclass 32, count 2 2006.286.01:27:49.40#ibcon#read 3, iclass 32, count 2 2006.286.01:27:49.40#ibcon#about to read 4, iclass 32, count 2 2006.286.01:27:49.40#ibcon#read 4, iclass 32, count 2 2006.286.01:27:49.40#ibcon#about to read 5, iclass 32, count 2 2006.286.01:27:49.40#ibcon#read 5, iclass 32, count 2 2006.286.01:27:49.40#ibcon#about to read 6, iclass 32, count 2 2006.286.01:27:49.40#ibcon#read 6, iclass 32, count 2 2006.286.01:27:49.40#ibcon#end of sib2, iclass 32, count 2 2006.286.01:27:49.40#ibcon#*after write, iclass 32, count 2 2006.286.01:27:49.40#ibcon#*before return 0, iclass 32, count 2 2006.286.01:27:49.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:27:49.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:27:49.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.01:27:49.40#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:49.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:27:49.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:27:49.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:27:49.52#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:27:49.52#ibcon#first serial, iclass 32, count 0 2006.286.01:27:49.52#ibcon#enter sib2, iclass 32, count 0 2006.286.01:27:49.52#ibcon#flushed, iclass 32, count 0 2006.286.01:27:49.52#ibcon#about to write, iclass 32, count 0 2006.286.01:27:49.52#ibcon#wrote, iclass 32, count 0 2006.286.01:27:49.52#ibcon#about to read 3, iclass 32, count 0 2006.286.01:27:49.54#ibcon#read 3, iclass 32, count 0 2006.286.01:27:49.54#ibcon#about to read 4, iclass 32, count 0 2006.286.01:27:49.54#ibcon#read 4, iclass 32, count 0 2006.286.01:27:49.54#ibcon#about to read 5, iclass 32, count 0 2006.286.01:27:49.54#ibcon#read 5, iclass 32, count 0 2006.286.01:27:49.54#ibcon#about to read 6, iclass 32, count 0 2006.286.01:27:49.54#ibcon#read 6, iclass 32, count 0 2006.286.01:27:49.54#ibcon#end of sib2, iclass 32, count 0 2006.286.01:27:49.54#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:27:49.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:27:49.54#ibcon#[25=USB\r\n] 2006.286.01:27:49.54#ibcon#*before write, iclass 32, count 0 2006.286.01:27:49.54#ibcon#enter sib2, iclass 32, count 0 2006.286.01:27:49.54#ibcon#flushed, iclass 32, count 0 2006.286.01:27:49.54#ibcon#about to write, iclass 32, count 0 2006.286.01:27:49.54#ibcon#wrote, iclass 32, count 0 2006.286.01:27:49.54#ibcon#about to read 3, iclass 32, count 0 2006.286.01:27:49.57#ibcon#read 3, iclass 32, count 0 2006.286.01:27:49.57#ibcon#about to read 4, iclass 32, count 0 2006.286.01:27:49.57#ibcon#read 4, iclass 32, count 0 2006.286.01:27:49.57#ibcon#about to read 5, iclass 32, count 0 2006.286.01:27:49.57#ibcon#read 5, iclass 32, count 0 2006.286.01:27:49.57#ibcon#about to read 6, iclass 32, count 0 2006.286.01:27:49.57#ibcon#read 6, iclass 32, count 0 2006.286.01:27:49.57#ibcon#end of sib2, iclass 32, count 0 2006.286.01:27:49.57#ibcon#*after write, iclass 32, count 0 2006.286.01:27:49.57#ibcon#*before return 0, iclass 32, count 0 2006.286.01:27:49.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:27:49.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:27:49.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:27:49.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:27:49.58$vck44/valo=4,624.99 2006.286.01:27:49.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.01:27:49.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.01:27:49.58#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:49.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:27:49.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:27:49.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:27:49.58#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:27:49.58#ibcon#first serial, iclass 34, count 0 2006.286.01:27:49.58#ibcon#enter sib2, iclass 34, count 0 2006.286.01:27:49.58#ibcon#flushed, iclass 34, count 0 2006.286.01:27:49.58#ibcon#about to write, iclass 34, count 0 2006.286.01:27:49.58#ibcon#wrote, iclass 34, count 0 2006.286.01:27:49.58#ibcon#about to read 3, iclass 34, count 0 2006.286.01:27:49.59#ibcon#read 3, iclass 34, count 0 2006.286.01:27:49.59#ibcon#about to read 4, iclass 34, count 0 2006.286.01:27:49.59#ibcon#read 4, iclass 34, count 0 2006.286.01:27:49.59#ibcon#about to read 5, iclass 34, count 0 2006.286.01:27:49.59#ibcon#read 5, iclass 34, count 0 2006.286.01:27:49.59#ibcon#about to read 6, iclass 34, count 0 2006.286.01:27:49.59#ibcon#read 6, iclass 34, count 0 2006.286.01:27:49.59#ibcon#end of sib2, iclass 34, count 0 2006.286.01:27:49.59#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:27:49.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:27:49.59#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:27:49.59#ibcon#*before write, iclass 34, count 0 2006.286.01:27:49.59#ibcon#enter sib2, iclass 34, count 0 2006.286.01:27:49.59#ibcon#flushed, iclass 34, count 0 2006.286.01:27:49.59#ibcon#about to write, iclass 34, count 0 2006.286.01:27:49.59#ibcon#wrote, iclass 34, count 0 2006.286.01:27:49.59#ibcon#about to read 3, iclass 34, count 0 2006.286.01:27:49.63#ibcon#read 3, iclass 34, count 0 2006.286.01:27:49.63#ibcon#about to read 4, iclass 34, count 0 2006.286.01:27:49.63#ibcon#read 4, iclass 34, count 0 2006.286.01:27:49.63#ibcon#about to read 5, iclass 34, count 0 2006.286.01:27:49.63#ibcon#read 5, iclass 34, count 0 2006.286.01:27:49.63#ibcon#about to read 6, iclass 34, count 0 2006.286.01:27:49.63#ibcon#read 6, iclass 34, count 0 2006.286.01:27:49.63#ibcon#end of sib2, iclass 34, count 0 2006.286.01:27:49.63#ibcon#*after write, iclass 34, count 0 2006.286.01:27:49.63#ibcon#*before return 0, iclass 34, count 0 2006.286.01:27:49.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:27:49.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:27:49.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:27:49.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:27:49.64$vck44/va=4,6 2006.286.01:27:49.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.01:27:49.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.01:27:49.64#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:49.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:27:49.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:27:49.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:27:49.68#ibcon#enter wrdev, iclass 36, count 2 2006.286.01:27:49.68#ibcon#first serial, iclass 36, count 2 2006.286.01:27:49.68#ibcon#enter sib2, iclass 36, count 2 2006.286.01:27:49.68#ibcon#flushed, iclass 36, count 2 2006.286.01:27:49.68#ibcon#about to write, iclass 36, count 2 2006.286.01:27:49.68#ibcon#wrote, iclass 36, count 2 2006.286.01:27:49.68#ibcon#about to read 3, iclass 36, count 2 2006.286.01:27:49.70#ibcon#read 3, iclass 36, count 2 2006.286.01:27:49.70#ibcon#about to read 4, iclass 36, count 2 2006.286.01:27:49.70#ibcon#read 4, iclass 36, count 2 2006.286.01:27:49.70#ibcon#about to read 5, iclass 36, count 2 2006.286.01:27:49.70#ibcon#read 5, iclass 36, count 2 2006.286.01:27:49.70#ibcon#about to read 6, iclass 36, count 2 2006.286.01:27:49.70#ibcon#read 6, iclass 36, count 2 2006.286.01:27:49.70#ibcon#end of sib2, iclass 36, count 2 2006.286.01:27:49.70#ibcon#*mode == 0, iclass 36, count 2 2006.286.01:27:49.70#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.01:27:49.70#ibcon#[25=AT04-06\r\n] 2006.286.01:27:49.70#ibcon#*before write, iclass 36, count 2 2006.286.01:27:49.70#ibcon#enter sib2, iclass 36, count 2 2006.286.01:27:49.70#ibcon#flushed, iclass 36, count 2 2006.286.01:27:49.70#ibcon#about to write, iclass 36, count 2 2006.286.01:27:49.70#ibcon#wrote, iclass 36, count 2 2006.286.01:27:49.70#ibcon#about to read 3, iclass 36, count 2 2006.286.01:27:49.73#ibcon#read 3, iclass 36, count 2 2006.286.01:27:49.73#ibcon#about to read 4, iclass 36, count 2 2006.286.01:27:49.73#ibcon#read 4, iclass 36, count 2 2006.286.01:27:49.73#ibcon#about to read 5, iclass 36, count 2 2006.286.01:27:49.73#ibcon#read 5, iclass 36, count 2 2006.286.01:27:49.73#ibcon#about to read 6, iclass 36, count 2 2006.286.01:27:49.73#ibcon#read 6, iclass 36, count 2 2006.286.01:27:49.73#ibcon#end of sib2, iclass 36, count 2 2006.286.01:27:49.73#ibcon#*after write, iclass 36, count 2 2006.286.01:27:49.73#ibcon#*before return 0, iclass 36, count 2 2006.286.01:27:49.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:27:49.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:27:49.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.01:27:49.73#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:49.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:27:49.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:27:49.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:27:49.85#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:27:49.85#ibcon#first serial, iclass 36, count 0 2006.286.01:27:49.85#ibcon#enter sib2, iclass 36, count 0 2006.286.01:27:49.85#ibcon#flushed, iclass 36, count 0 2006.286.01:27:49.85#ibcon#about to write, iclass 36, count 0 2006.286.01:27:49.85#ibcon#wrote, iclass 36, count 0 2006.286.01:27:49.85#ibcon#about to read 3, iclass 36, count 0 2006.286.01:27:49.87#ibcon#read 3, iclass 36, count 0 2006.286.01:27:49.87#ibcon#about to read 4, iclass 36, count 0 2006.286.01:27:49.87#ibcon#read 4, iclass 36, count 0 2006.286.01:27:49.87#ibcon#about to read 5, iclass 36, count 0 2006.286.01:27:49.87#ibcon#read 5, iclass 36, count 0 2006.286.01:27:49.87#ibcon#about to read 6, iclass 36, count 0 2006.286.01:27:49.87#ibcon#read 6, iclass 36, count 0 2006.286.01:27:49.87#ibcon#end of sib2, iclass 36, count 0 2006.286.01:27:49.87#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:27:49.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:27:49.87#ibcon#[25=USB\r\n] 2006.286.01:27:49.87#ibcon#*before write, iclass 36, count 0 2006.286.01:27:49.87#ibcon#enter sib2, iclass 36, count 0 2006.286.01:27:49.87#ibcon#flushed, iclass 36, count 0 2006.286.01:27:49.87#ibcon#about to write, iclass 36, count 0 2006.286.01:27:49.87#ibcon#wrote, iclass 36, count 0 2006.286.01:27:49.87#ibcon#about to read 3, iclass 36, count 0 2006.286.01:27:49.90#ibcon#read 3, iclass 36, count 0 2006.286.01:27:49.90#ibcon#about to read 4, iclass 36, count 0 2006.286.01:27:49.90#ibcon#read 4, iclass 36, count 0 2006.286.01:27:49.90#ibcon#about to read 5, iclass 36, count 0 2006.286.01:27:49.90#ibcon#read 5, iclass 36, count 0 2006.286.01:27:49.90#ibcon#about to read 6, iclass 36, count 0 2006.286.01:27:49.90#ibcon#read 6, iclass 36, count 0 2006.286.01:27:49.90#ibcon#end of sib2, iclass 36, count 0 2006.286.01:27:49.90#ibcon#*after write, iclass 36, count 0 2006.286.01:27:49.90#ibcon#*before return 0, iclass 36, count 0 2006.286.01:27:49.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:27:49.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:27:49.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:27:49.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:27:49.91$vck44/valo=5,734.99 2006.286.01:27:49.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.01:27:49.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.01:27:49.91#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:49.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:27:49.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:27:49.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:27:49.91#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:27:49.91#ibcon#first serial, iclass 38, count 0 2006.286.01:27:49.91#ibcon#enter sib2, iclass 38, count 0 2006.286.01:27:49.91#ibcon#flushed, iclass 38, count 0 2006.286.01:27:49.91#ibcon#about to write, iclass 38, count 0 2006.286.01:27:49.91#ibcon#wrote, iclass 38, count 0 2006.286.01:27:49.91#ibcon#about to read 3, iclass 38, count 0 2006.286.01:27:49.92#ibcon#read 3, iclass 38, count 0 2006.286.01:27:49.92#ibcon#about to read 4, iclass 38, count 0 2006.286.01:27:49.92#ibcon#read 4, iclass 38, count 0 2006.286.01:27:49.92#ibcon#about to read 5, iclass 38, count 0 2006.286.01:27:49.92#ibcon#read 5, iclass 38, count 0 2006.286.01:27:49.92#ibcon#about to read 6, iclass 38, count 0 2006.286.01:27:49.92#ibcon#read 6, iclass 38, count 0 2006.286.01:27:49.92#ibcon#end of sib2, iclass 38, count 0 2006.286.01:27:49.92#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:27:49.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:27:49.92#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:27:49.92#ibcon#*before write, iclass 38, count 0 2006.286.01:27:49.92#ibcon#enter sib2, iclass 38, count 0 2006.286.01:27:49.92#ibcon#flushed, iclass 38, count 0 2006.286.01:27:49.92#ibcon#about to write, iclass 38, count 0 2006.286.01:27:49.92#ibcon#wrote, iclass 38, count 0 2006.286.01:27:49.92#ibcon#about to read 3, iclass 38, count 0 2006.286.01:27:49.96#ibcon#read 3, iclass 38, count 0 2006.286.01:27:49.96#ibcon#about to read 4, iclass 38, count 0 2006.286.01:27:49.96#ibcon#read 4, iclass 38, count 0 2006.286.01:27:49.96#ibcon#about to read 5, iclass 38, count 0 2006.286.01:27:49.96#ibcon#read 5, iclass 38, count 0 2006.286.01:27:49.96#ibcon#about to read 6, iclass 38, count 0 2006.286.01:27:49.96#ibcon#read 6, iclass 38, count 0 2006.286.01:27:49.96#ibcon#end of sib2, iclass 38, count 0 2006.286.01:27:49.96#ibcon#*after write, iclass 38, count 0 2006.286.01:27:49.96#ibcon#*before return 0, iclass 38, count 0 2006.286.01:27:49.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:27:49.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:27:49.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:27:49.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:27:49.97$vck44/va=5,3 2006.286.01:27:49.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.01:27:49.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.01:27:49.97#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:49.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:27:50.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:27:50.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:27:50.02#ibcon#enter wrdev, iclass 40, count 2 2006.286.01:27:50.02#ibcon#first serial, iclass 40, count 2 2006.286.01:27:50.02#ibcon#enter sib2, iclass 40, count 2 2006.286.01:27:50.02#ibcon#flushed, iclass 40, count 2 2006.286.01:27:50.02#ibcon#about to write, iclass 40, count 2 2006.286.01:27:50.02#ibcon#wrote, iclass 40, count 2 2006.286.01:27:50.02#ibcon#about to read 3, iclass 40, count 2 2006.286.01:27:50.03#ibcon#read 3, iclass 40, count 2 2006.286.01:27:50.03#ibcon#about to read 4, iclass 40, count 2 2006.286.01:27:50.03#ibcon#read 4, iclass 40, count 2 2006.286.01:27:50.03#ibcon#about to read 5, iclass 40, count 2 2006.286.01:27:50.03#ibcon#read 5, iclass 40, count 2 2006.286.01:27:50.03#ibcon#about to read 6, iclass 40, count 2 2006.286.01:27:50.03#ibcon#read 6, iclass 40, count 2 2006.286.01:27:50.03#ibcon#end of sib2, iclass 40, count 2 2006.286.01:27:50.03#ibcon#*mode == 0, iclass 40, count 2 2006.286.01:27:50.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.01:27:50.03#ibcon#[25=AT05-03\r\n] 2006.286.01:27:50.03#ibcon#*before write, iclass 40, count 2 2006.286.01:27:50.03#ibcon#enter sib2, iclass 40, count 2 2006.286.01:27:50.03#ibcon#flushed, iclass 40, count 2 2006.286.01:27:50.03#ibcon#about to write, iclass 40, count 2 2006.286.01:27:50.03#ibcon#wrote, iclass 40, count 2 2006.286.01:27:50.03#ibcon#about to read 3, iclass 40, count 2 2006.286.01:27:50.06#ibcon#read 3, iclass 40, count 2 2006.286.01:27:50.06#ibcon#about to read 4, iclass 40, count 2 2006.286.01:27:50.06#ibcon#read 4, iclass 40, count 2 2006.286.01:27:50.06#ibcon#about to read 5, iclass 40, count 2 2006.286.01:27:50.06#ibcon#read 5, iclass 40, count 2 2006.286.01:27:50.06#ibcon#about to read 6, iclass 40, count 2 2006.286.01:27:50.06#ibcon#read 6, iclass 40, count 2 2006.286.01:27:50.06#ibcon#end of sib2, iclass 40, count 2 2006.286.01:27:50.06#ibcon#*after write, iclass 40, count 2 2006.286.01:27:50.06#ibcon#*before return 0, iclass 40, count 2 2006.286.01:27:50.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:27:50.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:27:50.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.01:27:50.06#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:50.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:27:50.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:27:50.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:27:50.18#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:27:50.18#ibcon#first serial, iclass 40, count 0 2006.286.01:27:50.18#ibcon#enter sib2, iclass 40, count 0 2006.286.01:27:50.18#ibcon#flushed, iclass 40, count 0 2006.286.01:27:50.18#ibcon#about to write, iclass 40, count 0 2006.286.01:27:50.18#ibcon#wrote, iclass 40, count 0 2006.286.01:27:50.18#ibcon#about to read 3, iclass 40, count 0 2006.286.01:27:50.20#ibcon#read 3, iclass 40, count 0 2006.286.01:27:50.20#ibcon#about to read 4, iclass 40, count 0 2006.286.01:27:50.20#ibcon#read 4, iclass 40, count 0 2006.286.01:27:50.20#ibcon#about to read 5, iclass 40, count 0 2006.286.01:27:50.20#ibcon#read 5, iclass 40, count 0 2006.286.01:27:50.20#ibcon#about to read 6, iclass 40, count 0 2006.286.01:27:50.20#ibcon#read 6, iclass 40, count 0 2006.286.01:27:50.20#ibcon#end of sib2, iclass 40, count 0 2006.286.01:27:50.20#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:27:50.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:27:50.20#ibcon#[25=USB\r\n] 2006.286.01:27:50.20#ibcon#*before write, iclass 40, count 0 2006.286.01:27:50.20#ibcon#enter sib2, iclass 40, count 0 2006.286.01:27:50.20#ibcon#flushed, iclass 40, count 0 2006.286.01:27:50.20#ibcon#about to write, iclass 40, count 0 2006.286.01:27:50.20#ibcon#wrote, iclass 40, count 0 2006.286.01:27:50.20#ibcon#about to read 3, iclass 40, count 0 2006.286.01:27:50.23#ibcon#read 3, iclass 40, count 0 2006.286.01:27:50.23#ibcon#about to read 4, iclass 40, count 0 2006.286.01:27:50.23#ibcon#read 4, iclass 40, count 0 2006.286.01:27:50.23#ibcon#about to read 5, iclass 40, count 0 2006.286.01:27:50.23#ibcon#read 5, iclass 40, count 0 2006.286.01:27:50.23#ibcon#about to read 6, iclass 40, count 0 2006.286.01:27:50.23#ibcon#read 6, iclass 40, count 0 2006.286.01:27:50.23#ibcon#end of sib2, iclass 40, count 0 2006.286.01:27:50.23#ibcon#*after write, iclass 40, count 0 2006.286.01:27:50.23#ibcon#*before return 0, iclass 40, count 0 2006.286.01:27:50.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:27:50.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:27:50.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:27:50.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:27:50.24$vck44/valo=6,814.99 2006.286.01:27:50.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.01:27:50.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.01:27:50.24#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:50.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:27:50.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:27:50.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:27:50.24#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:27:50.24#ibcon#first serial, iclass 4, count 0 2006.286.01:27:50.24#ibcon#enter sib2, iclass 4, count 0 2006.286.01:27:50.24#ibcon#flushed, iclass 4, count 0 2006.286.01:27:50.24#ibcon#about to write, iclass 4, count 0 2006.286.01:27:50.24#ibcon#wrote, iclass 4, count 0 2006.286.01:27:50.24#ibcon#about to read 3, iclass 4, count 0 2006.286.01:27:50.25#ibcon#read 3, iclass 4, count 0 2006.286.01:27:50.25#ibcon#about to read 4, iclass 4, count 0 2006.286.01:27:50.25#ibcon#read 4, iclass 4, count 0 2006.286.01:27:50.25#ibcon#about to read 5, iclass 4, count 0 2006.286.01:27:50.25#ibcon#read 5, iclass 4, count 0 2006.286.01:27:50.25#ibcon#about to read 6, iclass 4, count 0 2006.286.01:27:50.25#ibcon#read 6, iclass 4, count 0 2006.286.01:27:50.25#ibcon#end of sib2, iclass 4, count 0 2006.286.01:27:50.25#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:27:50.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:27:50.25#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:27:50.25#ibcon#*before write, iclass 4, count 0 2006.286.01:27:50.25#ibcon#enter sib2, iclass 4, count 0 2006.286.01:27:50.25#ibcon#flushed, iclass 4, count 0 2006.286.01:27:50.25#ibcon#about to write, iclass 4, count 0 2006.286.01:27:50.25#ibcon#wrote, iclass 4, count 0 2006.286.01:27:50.25#ibcon#about to read 3, iclass 4, count 0 2006.286.01:27:50.29#ibcon#read 3, iclass 4, count 0 2006.286.01:27:50.29#ibcon#about to read 4, iclass 4, count 0 2006.286.01:27:50.29#ibcon#read 4, iclass 4, count 0 2006.286.01:27:50.29#ibcon#about to read 5, iclass 4, count 0 2006.286.01:27:50.29#ibcon#read 5, iclass 4, count 0 2006.286.01:27:50.29#ibcon#about to read 6, iclass 4, count 0 2006.286.01:27:50.29#ibcon#read 6, iclass 4, count 0 2006.286.01:27:50.29#ibcon#end of sib2, iclass 4, count 0 2006.286.01:27:50.29#ibcon#*after write, iclass 4, count 0 2006.286.01:27:50.29#ibcon#*before return 0, iclass 4, count 0 2006.286.01:27:50.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:27:50.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:27:50.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:27:50.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:27:50.30$vck44/va=6,4 2006.286.01:27:50.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.01:27:50.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.01:27:50.30#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:50.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:27:50.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:27:50.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:27:50.34#ibcon#enter wrdev, iclass 6, count 2 2006.286.01:27:50.34#ibcon#first serial, iclass 6, count 2 2006.286.01:27:50.34#ibcon#enter sib2, iclass 6, count 2 2006.286.01:27:50.34#ibcon#flushed, iclass 6, count 2 2006.286.01:27:50.34#ibcon#about to write, iclass 6, count 2 2006.286.01:27:50.34#ibcon#wrote, iclass 6, count 2 2006.286.01:27:50.34#ibcon#about to read 3, iclass 6, count 2 2006.286.01:27:50.36#ibcon#read 3, iclass 6, count 2 2006.286.01:27:50.36#ibcon#about to read 4, iclass 6, count 2 2006.286.01:27:50.36#ibcon#read 4, iclass 6, count 2 2006.286.01:27:50.36#ibcon#about to read 5, iclass 6, count 2 2006.286.01:27:50.36#ibcon#read 5, iclass 6, count 2 2006.286.01:27:50.36#ibcon#about to read 6, iclass 6, count 2 2006.286.01:27:50.36#ibcon#read 6, iclass 6, count 2 2006.286.01:27:50.36#ibcon#end of sib2, iclass 6, count 2 2006.286.01:27:50.36#ibcon#*mode == 0, iclass 6, count 2 2006.286.01:27:50.36#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.01:27:50.36#ibcon#[25=AT06-04\r\n] 2006.286.01:27:50.36#ibcon#*before write, iclass 6, count 2 2006.286.01:27:50.36#ibcon#enter sib2, iclass 6, count 2 2006.286.01:27:50.36#ibcon#flushed, iclass 6, count 2 2006.286.01:27:50.36#ibcon#about to write, iclass 6, count 2 2006.286.01:27:50.36#ibcon#wrote, iclass 6, count 2 2006.286.01:27:50.36#ibcon#about to read 3, iclass 6, count 2 2006.286.01:27:50.39#ibcon#read 3, iclass 6, count 2 2006.286.01:27:50.39#ibcon#about to read 4, iclass 6, count 2 2006.286.01:27:50.39#ibcon#read 4, iclass 6, count 2 2006.286.01:27:50.39#ibcon#about to read 5, iclass 6, count 2 2006.286.01:27:50.39#ibcon#read 5, iclass 6, count 2 2006.286.01:27:50.39#ibcon#about to read 6, iclass 6, count 2 2006.286.01:27:50.39#ibcon#read 6, iclass 6, count 2 2006.286.01:27:50.39#ibcon#end of sib2, iclass 6, count 2 2006.286.01:27:50.39#ibcon#*after write, iclass 6, count 2 2006.286.01:27:50.39#ibcon#*before return 0, iclass 6, count 2 2006.286.01:27:50.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:27:50.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:27:50.39#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.01:27:50.39#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:50.39#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:27:50.51#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:27:50.51#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:27:50.51#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:27:50.51#ibcon#first serial, iclass 6, count 0 2006.286.01:27:50.51#ibcon#enter sib2, iclass 6, count 0 2006.286.01:27:50.51#ibcon#flushed, iclass 6, count 0 2006.286.01:27:50.51#ibcon#about to write, iclass 6, count 0 2006.286.01:27:50.51#ibcon#wrote, iclass 6, count 0 2006.286.01:27:50.51#ibcon#about to read 3, iclass 6, count 0 2006.286.01:27:50.53#ibcon#read 3, iclass 6, count 0 2006.286.01:27:50.53#ibcon#about to read 4, iclass 6, count 0 2006.286.01:27:50.53#ibcon#read 4, iclass 6, count 0 2006.286.01:27:50.53#ibcon#about to read 5, iclass 6, count 0 2006.286.01:27:50.53#ibcon#read 5, iclass 6, count 0 2006.286.01:27:50.53#ibcon#about to read 6, iclass 6, count 0 2006.286.01:27:50.53#ibcon#read 6, iclass 6, count 0 2006.286.01:27:50.53#ibcon#end of sib2, iclass 6, count 0 2006.286.01:27:50.53#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:27:50.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:27:50.53#ibcon#[25=USB\r\n] 2006.286.01:27:50.53#ibcon#*before write, iclass 6, count 0 2006.286.01:27:50.53#ibcon#enter sib2, iclass 6, count 0 2006.286.01:27:50.53#ibcon#flushed, iclass 6, count 0 2006.286.01:27:50.53#ibcon#about to write, iclass 6, count 0 2006.286.01:27:50.53#ibcon#wrote, iclass 6, count 0 2006.286.01:27:50.53#ibcon#about to read 3, iclass 6, count 0 2006.286.01:27:50.56#ibcon#read 3, iclass 6, count 0 2006.286.01:27:50.56#ibcon#about to read 4, iclass 6, count 0 2006.286.01:27:50.56#ibcon#read 4, iclass 6, count 0 2006.286.01:27:50.56#ibcon#about to read 5, iclass 6, count 0 2006.286.01:27:50.56#ibcon#read 5, iclass 6, count 0 2006.286.01:27:50.56#ibcon#about to read 6, iclass 6, count 0 2006.286.01:27:50.56#ibcon#read 6, iclass 6, count 0 2006.286.01:27:50.56#ibcon#end of sib2, iclass 6, count 0 2006.286.01:27:50.56#ibcon#*after write, iclass 6, count 0 2006.286.01:27:50.56#ibcon#*before return 0, iclass 6, count 0 2006.286.01:27:50.56#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:27:50.56#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:27:50.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:27:50.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:27:50.57$vck44/valo=7,864.99 2006.286.01:27:50.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.01:27:50.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.01:27:50.57#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:50.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:27:50.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:27:50.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:27:50.57#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:27:50.57#ibcon#first serial, iclass 10, count 0 2006.286.01:27:50.57#ibcon#enter sib2, iclass 10, count 0 2006.286.01:27:50.57#ibcon#flushed, iclass 10, count 0 2006.286.01:27:50.57#ibcon#about to write, iclass 10, count 0 2006.286.01:27:50.57#ibcon#wrote, iclass 10, count 0 2006.286.01:27:50.57#ibcon#about to read 3, iclass 10, count 0 2006.286.01:27:50.58#ibcon#read 3, iclass 10, count 0 2006.286.01:27:50.58#ibcon#about to read 4, iclass 10, count 0 2006.286.01:27:50.58#ibcon#read 4, iclass 10, count 0 2006.286.01:27:50.58#ibcon#about to read 5, iclass 10, count 0 2006.286.01:27:50.58#ibcon#read 5, iclass 10, count 0 2006.286.01:27:50.58#ibcon#about to read 6, iclass 10, count 0 2006.286.01:27:50.58#ibcon#read 6, iclass 10, count 0 2006.286.01:27:50.58#ibcon#end of sib2, iclass 10, count 0 2006.286.01:27:50.58#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:27:50.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:27:50.58#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:27:50.58#ibcon#*before write, iclass 10, count 0 2006.286.01:27:50.58#ibcon#enter sib2, iclass 10, count 0 2006.286.01:27:50.58#ibcon#flushed, iclass 10, count 0 2006.286.01:27:50.58#ibcon#about to write, iclass 10, count 0 2006.286.01:27:50.58#ibcon#wrote, iclass 10, count 0 2006.286.01:27:50.58#ibcon#about to read 3, iclass 10, count 0 2006.286.01:27:50.62#ibcon#read 3, iclass 10, count 0 2006.286.01:27:50.62#ibcon#about to read 4, iclass 10, count 0 2006.286.01:27:50.62#ibcon#read 4, iclass 10, count 0 2006.286.01:27:50.62#ibcon#about to read 5, iclass 10, count 0 2006.286.01:27:50.62#ibcon#read 5, iclass 10, count 0 2006.286.01:27:50.62#ibcon#about to read 6, iclass 10, count 0 2006.286.01:27:50.62#ibcon#read 6, iclass 10, count 0 2006.286.01:27:50.62#ibcon#end of sib2, iclass 10, count 0 2006.286.01:27:50.62#ibcon#*after write, iclass 10, count 0 2006.286.01:27:50.62#ibcon#*before return 0, iclass 10, count 0 2006.286.01:27:50.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:27:50.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:27:50.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:27:50.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:27:50.63$vck44/va=7,4 2006.286.01:27:50.63#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.01:27:50.63#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.01:27:50.63#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:50.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:27:50.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:27:50.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:27:50.67#ibcon#enter wrdev, iclass 12, count 2 2006.286.01:27:50.67#ibcon#first serial, iclass 12, count 2 2006.286.01:27:50.67#ibcon#enter sib2, iclass 12, count 2 2006.286.01:27:50.67#ibcon#flushed, iclass 12, count 2 2006.286.01:27:50.67#ibcon#about to write, iclass 12, count 2 2006.286.01:27:50.67#ibcon#wrote, iclass 12, count 2 2006.286.01:27:50.67#ibcon#about to read 3, iclass 12, count 2 2006.286.01:27:50.69#ibcon#read 3, iclass 12, count 2 2006.286.01:27:50.69#ibcon#about to read 4, iclass 12, count 2 2006.286.01:27:50.69#ibcon#read 4, iclass 12, count 2 2006.286.01:27:50.69#ibcon#about to read 5, iclass 12, count 2 2006.286.01:27:50.69#ibcon#read 5, iclass 12, count 2 2006.286.01:27:50.69#ibcon#about to read 6, iclass 12, count 2 2006.286.01:27:50.69#ibcon#read 6, iclass 12, count 2 2006.286.01:27:50.69#ibcon#end of sib2, iclass 12, count 2 2006.286.01:27:50.69#ibcon#*mode == 0, iclass 12, count 2 2006.286.01:27:50.69#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.01:27:50.69#ibcon#[25=AT07-04\r\n] 2006.286.01:27:50.69#ibcon#*before write, iclass 12, count 2 2006.286.01:27:50.69#ibcon#enter sib2, iclass 12, count 2 2006.286.01:27:50.69#ibcon#flushed, iclass 12, count 2 2006.286.01:27:50.69#ibcon#about to write, iclass 12, count 2 2006.286.01:27:50.69#ibcon#wrote, iclass 12, count 2 2006.286.01:27:50.69#ibcon#about to read 3, iclass 12, count 2 2006.286.01:27:50.72#ibcon#read 3, iclass 12, count 2 2006.286.01:27:50.72#ibcon#about to read 4, iclass 12, count 2 2006.286.01:27:50.72#ibcon#read 4, iclass 12, count 2 2006.286.01:27:50.72#ibcon#about to read 5, iclass 12, count 2 2006.286.01:27:50.72#ibcon#read 5, iclass 12, count 2 2006.286.01:27:50.72#ibcon#about to read 6, iclass 12, count 2 2006.286.01:27:50.72#ibcon#read 6, iclass 12, count 2 2006.286.01:27:50.72#ibcon#end of sib2, iclass 12, count 2 2006.286.01:27:50.72#ibcon#*after write, iclass 12, count 2 2006.286.01:27:50.72#ibcon#*before return 0, iclass 12, count 2 2006.286.01:27:50.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:27:50.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:27:50.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.01:27:50.72#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:50.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:27:50.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:27:50.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:27:50.84#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:27:50.84#ibcon#first serial, iclass 12, count 0 2006.286.01:27:50.84#ibcon#enter sib2, iclass 12, count 0 2006.286.01:27:50.84#ibcon#flushed, iclass 12, count 0 2006.286.01:27:50.84#ibcon#about to write, iclass 12, count 0 2006.286.01:27:50.84#ibcon#wrote, iclass 12, count 0 2006.286.01:27:50.84#ibcon#about to read 3, iclass 12, count 0 2006.286.01:27:50.86#ibcon#read 3, iclass 12, count 0 2006.286.01:27:50.86#ibcon#about to read 4, iclass 12, count 0 2006.286.01:27:50.86#ibcon#read 4, iclass 12, count 0 2006.286.01:27:50.86#ibcon#about to read 5, iclass 12, count 0 2006.286.01:27:50.86#ibcon#read 5, iclass 12, count 0 2006.286.01:27:50.86#ibcon#about to read 6, iclass 12, count 0 2006.286.01:27:50.86#ibcon#read 6, iclass 12, count 0 2006.286.01:27:50.86#ibcon#end of sib2, iclass 12, count 0 2006.286.01:27:50.86#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:27:50.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:27:50.86#ibcon#[25=USB\r\n] 2006.286.01:27:50.86#ibcon#*before write, iclass 12, count 0 2006.286.01:27:50.86#ibcon#enter sib2, iclass 12, count 0 2006.286.01:27:50.86#ibcon#flushed, iclass 12, count 0 2006.286.01:27:50.86#ibcon#about to write, iclass 12, count 0 2006.286.01:27:50.86#ibcon#wrote, iclass 12, count 0 2006.286.01:27:50.86#ibcon#about to read 3, iclass 12, count 0 2006.286.01:27:50.89#ibcon#read 3, iclass 12, count 0 2006.286.01:27:50.89#ibcon#about to read 4, iclass 12, count 0 2006.286.01:27:50.89#ibcon#read 4, iclass 12, count 0 2006.286.01:27:50.89#ibcon#about to read 5, iclass 12, count 0 2006.286.01:27:50.89#ibcon#read 5, iclass 12, count 0 2006.286.01:27:50.89#ibcon#about to read 6, iclass 12, count 0 2006.286.01:27:50.89#ibcon#read 6, iclass 12, count 0 2006.286.01:27:50.89#ibcon#end of sib2, iclass 12, count 0 2006.286.01:27:50.89#ibcon#*after write, iclass 12, count 0 2006.286.01:27:50.89#ibcon#*before return 0, iclass 12, count 0 2006.286.01:27:50.89#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:27:50.89#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:27:50.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:27:50.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:27:50.90$vck44/valo=8,884.99 2006.286.01:27:50.90#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.01:27:50.90#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.01:27:50.90#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:50.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:27:50.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:27:50.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:27:50.90#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:27:50.90#ibcon#first serial, iclass 14, count 0 2006.286.01:27:50.90#ibcon#enter sib2, iclass 14, count 0 2006.286.01:27:50.90#ibcon#flushed, iclass 14, count 0 2006.286.01:27:50.90#ibcon#about to write, iclass 14, count 0 2006.286.01:27:50.90#ibcon#wrote, iclass 14, count 0 2006.286.01:27:50.90#ibcon#about to read 3, iclass 14, count 0 2006.286.01:27:50.91#ibcon#read 3, iclass 14, count 0 2006.286.01:27:50.91#ibcon#about to read 4, iclass 14, count 0 2006.286.01:27:50.91#ibcon#read 4, iclass 14, count 0 2006.286.01:27:50.91#ibcon#about to read 5, iclass 14, count 0 2006.286.01:27:50.91#ibcon#read 5, iclass 14, count 0 2006.286.01:27:50.91#ibcon#about to read 6, iclass 14, count 0 2006.286.01:27:50.91#ibcon#read 6, iclass 14, count 0 2006.286.01:27:50.91#ibcon#end of sib2, iclass 14, count 0 2006.286.01:27:50.91#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:27:50.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:27:50.91#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:27:50.91#ibcon#*before write, iclass 14, count 0 2006.286.01:27:50.91#ibcon#enter sib2, iclass 14, count 0 2006.286.01:27:50.91#ibcon#flushed, iclass 14, count 0 2006.286.01:27:50.91#ibcon#about to write, iclass 14, count 0 2006.286.01:27:50.91#ibcon#wrote, iclass 14, count 0 2006.286.01:27:50.91#ibcon#about to read 3, iclass 14, count 0 2006.286.01:27:50.95#ibcon#read 3, iclass 14, count 0 2006.286.01:27:50.95#ibcon#about to read 4, iclass 14, count 0 2006.286.01:27:50.95#ibcon#read 4, iclass 14, count 0 2006.286.01:27:50.95#ibcon#about to read 5, iclass 14, count 0 2006.286.01:27:50.95#ibcon#read 5, iclass 14, count 0 2006.286.01:27:50.95#ibcon#about to read 6, iclass 14, count 0 2006.286.01:27:50.95#ibcon#read 6, iclass 14, count 0 2006.286.01:27:50.95#ibcon#end of sib2, iclass 14, count 0 2006.286.01:27:50.95#ibcon#*after write, iclass 14, count 0 2006.286.01:27:50.95#ibcon#*before return 0, iclass 14, count 0 2006.286.01:27:50.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:27:50.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:27:50.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:27:50.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:27:50.96$vck44/va=8,3 2006.286.01:27:50.96#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.01:27:50.96#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.01:27:50.96#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:50.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:27:51.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:27:51.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:27:51.00#ibcon#enter wrdev, iclass 16, count 2 2006.286.01:27:51.00#ibcon#first serial, iclass 16, count 2 2006.286.01:27:51.00#ibcon#enter sib2, iclass 16, count 2 2006.286.01:27:51.00#ibcon#flushed, iclass 16, count 2 2006.286.01:27:51.00#ibcon#about to write, iclass 16, count 2 2006.286.01:27:51.00#ibcon#wrote, iclass 16, count 2 2006.286.01:27:51.00#ibcon#about to read 3, iclass 16, count 2 2006.286.01:27:51.02#ibcon#read 3, iclass 16, count 2 2006.286.01:27:51.02#ibcon#about to read 4, iclass 16, count 2 2006.286.01:27:51.02#ibcon#read 4, iclass 16, count 2 2006.286.01:27:51.02#ibcon#about to read 5, iclass 16, count 2 2006.286.01:27:51.02#ibcon#read 5, iclass 16, count 2 2006.286.01:27:51.02#ibcon#about to read 6, iclass 16, count 2 2006.286.01:27:51.02#ibcon#read 6, iclass 16, count 2 2006.286.01:27:51.02#ibcon#end of sib2, iclass 16, count 2 2006.286.01:27:51.02#ibcon#*mode == 0, iclass 16, count 2 2006.286.01:27:51.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.01:27:51.02#ibcon#[25=AT08-03\r\n] 2006.286.01:27:51.02#ibcon#*before write, iclass 16, count 2 2006.286.01:27:51.02#ibcon#enter sib2, iclass 16, count 2 2006.286.01:27:51.02#ibcon#flushed, iclass 16, count 2 2006.286.01:27:51.02#ibcon#about to write, iclass 16, count 2 2006.286.01:27:51.02#ibcon#wrote, iclass 16, count 2 2006.286.01:27:51.02#ibcon#about to read 3, iclass 16, count 2 2006.286.01:27:51.05#ibcon#read 3, iclass 16, count 2 2006.286.01:27:51.05#ibcon#about to read 4, iclass 16, count 2 2006.286.01:27:51.05#ibcon#read 4, iclass 16, count 2 2006.286.01:27:51.05#ibcon#about to read 5, iclass 16, count 2 2006.286.01:27:51.05#ibcon#read 5, iclass 16, count 2 2006.286.01:27:51.05#ibcon#about to read 6, iclass 16, count 2 2006.286.01:27:51.05#ibcon#read 6, iclass 16, count 2 2006.286.01:27:51.05#ibcon#end of sib2, iclass 16, count 2 2006.286.01:27:51.05#ibcon#*after write, iclass 16, count 2 2006.286.01:27:51.05#ibcon#*before return 0, iclass 16, count 2 2006.286.01:27:51.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:27:51.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:27:51.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.01:27:51.05#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:51.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:27:51.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:27:51.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:27:51.17#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:27:51.17#ibcon#first serial, iclass 16, count 0 2006.286.01:27:51.17#ibcon#enter sib2, iclass 16, count 0 2006.286.01:27:51.17#ibcon#flushed, iclass 16, count 0 2006.286.01:27:51.17#ibcon#about to write, iclass 16, count 0 2006.286.01:27:51.17#ibcon#wrote, iclass 16, count 0 2006.286.01:27:51.17#ibcon#about to read 3, iclass 16, count 0 2006.286.01:27:51.19#ibcon#read 3, iclass 16, count 0 2006.286.01:27:51.19#ibcon#about to read 4, iclass 16, count 0 2006.286.01:27:51.19#ibcon#read 4, iclass 16, count 0 2006.286.01:27:51.19#ibcon#about to read 5, iclass 16, count 0 2006.286.01:27:51.19#ibcon#read 5, iclass 16, count 0 2006.286.01:27:51.19#ibcon#about to read 6, iclass 16, count 0 2006.286.01:27:51.19#ibcon#read 6, iclass 16, count 0 2006.286.01:27:51.19#ibcon#end of sib2, iclass 16, count 0 2006.286.01:27:51.19#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:27:51.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:27:51.19#ibcon#[25=USB\r\n] 2006.286.01:27:51.19#ibcon#*before write, iclass 16, count 0 2006.286.01:27:51.19#ibcon#enter sib2, iclass 16, count 0 2006.286.01:27:51.19#ibcon#flushed, iclass 16, count 0 2006.286.01:27:51.19#ibcon#about to write, iclass 16, count 0 2006.286.01:27:51.19#ibcon#wrote, iclass 16, count 0 2006.286.01:27:51.19#ibcon#about to read 3, iclass 16, count 0 2006.286.01:27:51.22#ibcon#read 3, iclass 16, count 0 2006.286.01:27:51.22#ibcon#about to read 4, iclass 16, count 0 2006.286.01:27:51.22#ibcon#read 4, iclass 16, count 0 2006.286.01:27:51.22#ibcon#about to read 5, iclass 16, count 0 2006.286.01:27:51.22#ibcon#read 5, iclass 16, count 0 2006.286.01:27:51.22#ibcon#about to read 6, iclass 16, count 0 2006.286.01:27:51.22#ibcon#read 6, iclass 16, count 0 2006.286.01:27:51.22#ibcon#end of sib2, iclass 16, count 0 2006.286.01:27:51.22#ibcon#*after write, iclass 16, count 0 2006.286.01:27:51.22#ibcon#*before return 0, iclass 16, count 0 2006.286.01:27:51.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:27:51.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:27:51.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:27:51.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:27:51.23$vck44/vblo=1,629.99 2006.286.01:27:51.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.01:27:51.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.01:27:51.23#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:51.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:27:51.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:27:51.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:27:51.23#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:27:51.23#ibcon#first serial, iclass 18, count 0 2006.286.01:27:51.23#ibcon#enter sib2, iclass 18, count 0 2006.286.01:27:51.23#ibcon#flushed, iclass 18, count 0 2006.286.01:27:51.23#ibcon#about to write, iclass 18, count 0 2006.286.01:27:51.23#ibcon#wrote, iclass 18, count 0 2006.286.01:27:51.23#ibcon#about to read 3, iclass 18, count 0 2006.286.01:27:51.24#ibcon#read 3, iclass 18, count 0 2006.286.01:27:51.24#ibcon#about to read 4, iclass 18, count 0 2006.286.01:27:51.24#ibcon#read 4, iclass 18, count 0 2006.286.01:27:51.24#ibcon#about to read 5, iclass 18, count 0 2006.286.01:27:51.24#ibcon#read 5, iclass 18, count 0 2006.286.01:27:51.24#ibcon#about to read 6, iclass 18, count 0 2006.286.01:27:51.24#ibcon#read 6, iclass 18, count 0 2006.286.01:27:51.24#ibcon#end of sib2, iclass 18, count 0 2006.286.01:27:51.24#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:27:51.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:27:51.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:27:51.24#ibcon#*before write, iclass 18, count 0 2006.286.01:27:51.24#ibcon#enter sib2, iclass 18, count 0 2006.286.01:27:51.24#ibcon#flushed, iclass 18, count 0 2006.286.01:27:51.24#ibcon#about to write, iclass 18, count 0 2006.286.01:27:51.24#ibcon#wrote, iclass 18, count 0 2006.286.01:27:51.24#ibcon#about to read 3, iclass 18, count 0 2006.286.01:27:51.28#ibcon#read 3, iclass 18, count 0 2006.286.01:27:51.28#ibcon#about to read 4, iclass 18, count 0 2006.286.01:27:51.28#ibcon#read 4, iclass 18, count 0 2006.286.01:27:51.28#ibcon#about to read 5, iclass 18, count 0 2006.286.01:27:51.28#ibcon#read 5, iclass 18, count 0 2006.286.01:27:51.28#ibcon#about to read 6, iclass 18, count 0 2006.286.01:27:51.28#ibcon#read 6, iclass 18, count 0 2006.286.01:27:51.28#ibcon#end of sib2, iclass 18, count 0 2006.286.01:27:51.28#ibcon#*after write, iclass 18, count 0 2006.286.01:27:51.28#ibcon#*before return 0, iclass 18, count 0 2006.286.01:27:51.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:27:51.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:27:51.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:27:51.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:27:51.29$vck44/vb=1,4 2006.286.01:27:51.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.01:27:51.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.01:27:51.29#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:51.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:27:51.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:27:51.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:27:51.29#ibcon#enter wrdev, iclass 20, count 2 2006.286.01:27:51.29#ibcon#first serial, iclass 20, count 2 2006.286.01:27:51.29#ibcon#enter sib2, iclass 20, count 2 2006.286.01:27:51.29#ibcon#flushed, iclass 20, count 2 2006.286.01:27:51.29#ibcon#about to write, iclass 20, count 2 2006.286.01:27:51.29#ibcon#wrote, iclass 20, count 2 2006.286.01:27:51.29#ibcon#about to read 3, iclass 20, count 2 2006.286.01:27:51.30#ibcon#read 3, iclass 20, count 2 2006.286.01:27:51.30#ibcon#about to read 4, iclass 20, count 2 2006.286.01:27:51.30#ibcon#read 4, iclass 20, count 2 2006.286.01:27:51.30#ibcon#about to read 5, iclass 20, count 2 2006.286.01:27:51.30#ibcon#read 5, iclass 20, count 2 2006.286.01:27:51.30#ibcon#about to read 6, iclass 20, count 2 2006.286.01:27:51.30#ibcon#read 6, iclass 20, count 2 2006.286.01:27:51.30#ibcon#end of sib2, iclass 20, count 2 2006.286.01:27:51.30#ibcon#*mode == 0, iclass 20, count 2 2006.286.01:27:51.30#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.01:27:51.30#ibcon#[27=AT01-04\r\n] 2006.286.01:27:51.30#ibcon#*before write, iclass 20, count 2 2006.286.01:27:51.30#ibcon#enter sib2, iclass 20, count 2 2006.286.01:27:51.30#ibcon#flushed, iclass 20, count 2 2006.286.01:27:51.30#ibcon#about to write, iclass 20, count 2 2006.286.01:27:51.30#ibcon#wrote, iclass 20, count 2 2006.286.01:27:51.30#ibcon#about to read 3, iclass 20, count 2 2006.286.01:27:51.33#ibcon#read 3, iclass 20, count 2 2006.286.01:27:51.33#ibcon#about to read 4, iclass 20, count 2 2006.286.01:27:51.33#ibcon#read 4, iclass 20, count 2 2006.286.01:27:51.33#ibcon#about to read 5, iclass 20, count 2 2006.286.01:27:51.33#ibcon#read 5, iclass 20, count 2 2006.286.01:27:51.33#ibcon#about to read 6, iclass 20, count 2 2006.286.01:27:51.33#ibcon#read 6, iclass 20, count 2 2006.286.01:27:51.33#ibcon#end of sib2, iclass 20, count 2 2006.286.01:27:51.33#ibcon#*after write, iclass 20, count 2 2006.286.01:27:51.33#ibcon#*before return 0, iclass 20, count 2 2006.286.01:27:51.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:27:51.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:27:51.33#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.01:27:51.33#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:51.33#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:27:51.45#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:27:51.45#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:27:51.45#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:27:51.45#ibcon#first serial, iclass 20, count 0 2006.286.01:27:51.45#ibcon#enter sib2, iclass 20, count 0 2006.286.01:27:51.45#ibcon#flushed, iclass 20, count 0 2006.286.01:27:51.45#ibcon#about to write, iclass 20, count 0 2006.286.01:27:51.45#ibcon#wrote, iclass 20, count 0 2006.286.01:27:51.45#ibcon#about to read 3, iclass 20, count 0 2006.286.01:27:51.47#ibcon#read 3, iclass 20, count 0 2006.286.01:27:51.47#ibcon#about to read 4, iclass 20, count 0 2006.286.01:27:51.47#ibcon#read 4, iclass 20, count 0 2006.286.01:27:51.47#ibcon#about to read 5, iclass 20, count 0 2006.286.01:27:51.47#ibcon#read 5, iclass 20, count 0 2006.286.01:27:51.47#ibcon#about to read 6, iclass 20, count 0 2006.286.01:27:51.47#ibcon#read 6, iclass 20, count 0 2006.286.01:27:51.47#ibcon#end of sib2, iclass 20, count 0 2006.286.01:27:51.47#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:27:51.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:27:51.47#ibcon#[27=USB\r\n] 2006.286.01:27:51.47#ibcon#*before write, iclass 20, count 0 2006.286.01:27:51.47#ibcon#enter sib2, iclass 20, count 0 2006.286.01:27:51.47#ibcon#flushed, iclass 20, count 0 2006.286.01:27:51.47#ibcon#about to write, iclass 20, count 0 2006.286.01:27:51.47#ibcon#wrote, iclass 20, count 0 2006.286.01:27:51.47#ibcon#about to read 3, iclass 20, count 0 2006.286.01:27:51.50#ibcon#read 3, iclass 20, count 0 2006.286.01:27:51.50#ibcon#about to read 4, iclass 20, count 0 2006.286.01:27:51.50#ibcon#read 4, iclass 20, count 0 2006.286.01:27:51.50#ibcon#about to read 5, iclass 20, count 0 2006.286.01:27:51.50#ibcon#read 5, iclass 20, count 0 2006.286.01:27:51.50#ibcon#about to read 6, iclass 20, count 0 2006.286.01:27:51.50#ibcon#read 6, iclass 20, count 0 2006.286.01:27:51.50#ibcon#end of sib2, iclass 20, count 0 2006.286.01:27:51.50#ibcon#*after write, iclass 20, count 0 2006.286.01:27:51.50#ibcon#*before return 0, iclass 20, count 0 2006.286.01:27:51.50#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:27:51.50#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:27:51.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:27:51.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:27:51.51$vck44/vblo=2,634.99 2006.286.01:27:51.51#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.01:27:51.51#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.01:27:51.51#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:51.51#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:27:51.51#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:27:51.51#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:27:51.51#ibcon#enter wrdev, iclass 22, count 0 2006.286.01:27:51.51#ibcon#first serial, iclass 22, count 0 2006.286.01:27:51.51#ibcon#enter sib2, iclass 22, count 0 2006.286.01:27:51.51#ibcon#flushed, iclass 22, count 0 2006.286.01:27:51.51#ibcon#about to write, iclass 22, count 0 2006.286.01:27:51.51#ibcon#wrote, iclass 22, count 0 2006.286.01:27:51.51#ibcon#about to read 3, iclass 22, count 0 2006.286.01:27:51.52#ibcon#read 3, iclass 22, count 0 2006.286.01:27:51.52#ibcon#about to read 4, iclass 22, count 0 2006.286.01:27:51.52#ibcon#read 4, iclass 22, count 0 2006.286.01:27:51.52#ibcon#about to read 5, iclass 22, count 0 2006.286.01:27:51.52#ibcon#read 5, iclass 22, count 0 2006.286.01:27:51.52#ibcon#about to read 6, iclass 22, count 0 2006.286.01:27:51.52#ibcon#read 6, iclass 22, count 0 2006.286.01:27:51.52#ibcon#end of sib2, iclass 22, count 0 2006.286.01:27:51.52#ibcon#*mode == 0, iclass 22, count 0 2006.286.01:27:51.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.01:27:51.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:27:51.52#ibcon#*before write, iclass 22, count 0 2006.286.01:27:51.52#ibcon#enter sib2, iclass 22, count 0 2006.286.01:27:51.52#ibcon#flushed, iclass 22, count 0 2006.286.01:27:51.52#ibcon#about to write, iclass 22, count 0 2006.286.01:27:51.52#ibcon#wrote, iclass 22, count 0 2006.286.01:27:51.52#ibcon#about to read 3, iclass 22, count 0 2006.286.01:27:51.56#ibcon#read 3, iclass 22, count 0 2006.286.01:27:51.56#ibcon#about to read 4, iclass 22, count 0 2006.286.01:27:51.56#ibcon#read 4, iclass 22, count 0 2006.286.01:27:51.56#ibcon#about to read 5, iclass 22, count 0 2006.286.01:27:51.56#ibcon#read 5, iclass 22, count 0 2006.286.01:27:51.56#ibcon#about to read 6, iclass 22, count 0 2006.286.01:27:51.56#ibcon#read 6, iclass 22, count 0 2006.286.01:27:51.56#ibcon#end of sib2, iclass 22, count 0 2006.286.01:27:51.56#ibcon#*after write, iclass 22, count 0 2006.286.01:27:51.56#ibcon#*before return 0, iclass 22, count 0 2006.286.01:27:51.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:27:51.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:27:51.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.01:27:51.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.01:27:51.57$vck44/vb=2,5 2006.286.01:27:51.57#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.01:27:51.57#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.01:27:51.57#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:51.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:27:51.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:27:51.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:27:51.61#ibcon#enter wrdev, iclass 24, count 2 2006.286.01:27:51.61#ibcon#first serial, iclass 24, count 2 2006.286.01:27:51.61#ibcon#enter sib2, iclass 24, count 2 2006.286.01:27:51.61#ibcon#flushed, iclass 24, count 2 2006.286.01:27:51.61#ibcon#about to write, iclass 24, count 2 2006.286.01:27:51.61#ibcon#wrote, iclass 24, count 2 2006.286.01:27:51.61#ibcon#about to read 3, iclass 24, count 2 2006.286.01:27:51.63#ibcon#read 3, iclass 24, count 2 2006.286.01:27:51.63#ibcon#about to read 4, iclass 24, count 2 2006.286.01:27:51.63#ibcon#read 4, iclass 24, count 2 2006.286.01:27:51.63#ibcon#about to read 5, iclass 24, count 2 2006.286.01:27:51.63#ibcon#read 5, iclass 24, count 2 2006.286.01:27:51.63#ibcon#about to read 6, iclass 24, count 2 2006.286.01:27:51.63#ibcon#read 6, iclass 24, count 2 2006.286.01:27:51.63#ibcon#end of sib2, iclass 24, count 2 2006.286.01:27:51.63#ibcon#*mode == 0, iclass 24, count 2 2006.286.01:27:51.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.01:27:51.63#ibcon#[27=AT02-05\r\n] 2006.286.01:27:51.63#ibcon#*before write, iclass 24, count 2 2006.286.01:27:51.63#ibcon#enter sib2, iclass 24, count 2 2006.286.01:27:51.63#ibcon#flushed, iclass 24, count 2 2006.286.01:27:51.63#ibcon#about to write, iclass 24, count 2 2006.286.01:27:51.63#ibcon#wrote, iclass 24, count 2 2006.286.01:27:51.63#ibcon#about to read 3, iclass 24, count 2 2006.286.01:27:51.66#ibcon#read 3, iclass 24, count 2 2006.286.01:27:51.66#ibcon#about to read 4, iclass 24, count 2 2006.286.01:27:51.66#ibcon#read 4, iclass 24, count 2 2006.286.01:27:51.66#ibcon#about to read 5, iclass 24, count 2 2006.286.01:27:51.66#ibcon#read 5, iclass 24, count 2 2006.286.01:27:51.66#ibcon#about to read 6, iclass 24, count 2 2006.286.01:27:51.66#ibcon#read 6, iclass 24, count 2 2006.286.01:27:51.66#ibcon#end of sib2, iclass 24, count 2 2006.286.01:27:51.66#ibcon#*after write, iclass 24, count 2 2006.286.01:27:51.66#ibcon#*before return 0, iclass 24, count 2 2006.286.01:27:51.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:27:51.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:27:51.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.01:27:51.66#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:51.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:27:51.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:27:51.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:27:51.78#ibcon#enter wrdev, iclass 24, count 0 2006.286.01:27:51.78#ibcon#first serial, iclass 24, count 0 2006.286.01:27:51.78#ibcon#enter sib2, iclass 24, count 0 2006.286.01:27:51.78#ibcon#flushed, iclass 24, count 0 2006.286.01:27:51.78#ibcon#about to write, iclass 24, count 0 2006.286.01:27:51.78#ibcon#wrote, iclass 24, count 0 2006.286.01:27:51.78#ibcon#about to read 3, iclass 24, count 0 2006.286.01:27:51.80#ibcon#read 3, iclass 24, count 0 2006.286.01:27:51.80#ibcon#about to read 4, iclass 24, count 0 2006.286.01:27:51.80#ibcon#read 4, iclass 24, count 0 2006.286.01:27:51.80#ibcon#about to read 5, iclass 24, count 0 2006.286.01:27:51.80#ibcon#read 5, iclass 24, count 0 2006.286.01:27:51.80#ibcon#about to read 6, iclass 24, count 0 2006.286.01:27:51.80#ibcon#read 6, iclass 24, count 0 2006.286.01:27:51.80#ibcon#end of sib2, iclass 24, count 0 2006.286.01:27:51.80#ibcon#*mode == 0, iclass 24, count 0 2006.286.01:27:51.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.01:27:51.80#ibcon#[27=USB\r\n] 2006.286.01:27:51.80#ibcon#*before write, iclass 24, count 0 2006.286.01:27:51.80#ibcon#enter sib2, iclass 24, count 0 2006.286.01:27:51.80#ibcon#flushed, iclass 24, count 0 2006.286.01:27:51.80#ibcon#about to write, iclass 24, count 0 2006.286.01:27:51.80#ibcon#wrote, iclass 24, count 0 2006.286.01:27:51.80#ibcon#about to read 3, iclass 24, count 0 2006.286.01:27:51.83#ibcon#read 3, iclass 24, count 0 2006.286.01:27:51.83#ibcon#about to read 4, iclass 24, count 0 2006.286.01:27:51.83#ibcon#read 4, iclass 24, count 0 2006.286.01:27:51.83#ibcon#about to read 5, iclass 24, count 0 2006.286.01:27:51.83#ibcon#read 5, iclass 24, count 0 2006.286.01:27:51.83#ibcon#about to read 6, iclass 24, count 0 2006.286.01:27:51.83#ibcon#read 6, iclass 24, count 0 2006.286.01:27:51.83#ibcon#end of sib2, iclass 24, count 0 2006.286.01:27:51.83#ibcon#*after write, iclass 24, count 0 2006.286.01:27:51.83#ibcon#*before return 0, iclass 24, count 0 2006.286.01:27:51.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:27:51.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:27:51.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.01:27:51.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.01:27:51.84$vck44/vblo=3,649.99 2006.286.01:27:51.84#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.01:27:51.84#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.01:27:51.84#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:51.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:27:51.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:27:51.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:27:51.84#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:27:51.84#ibcon#first serial, iclass 26, count 0 2006.286.01:27:51.84#ibcon#enter sib2, iclass 26, count 0 2006.286.01:27:51.84#ibcon#flushed, iclass 26, count 0 2006.286.01:27:51.84#ibcon#about to write, iclass 26, count 0 2006.286.01:27:51.84#ibcon#wrote, iclass 26, count 0 2006.286.01:27:51.84#ibcon#about to read 3, iclass 26, count 0 2006.286.01:27:51.85#ibcon#read 3, iclass 26, count 0 2006.286.01:27:51.85#ibcon#about to read 4, iclass 26, count 0 2006.286.01:27:51.85#ibcon#read 4, iclass 26, count 0 2006.286.01:27:51.85#ibcon#about to read 5, iclass 26, count 0 2006.286.01:27:51.85#ibcon#read 5, iclass 26, count 0 2006.286.01:27:51.85#ibcon#about to read 6, iclass 26, count 0 2006.286.01:27:51.85#ibcon#read 6, iclass 26, count 0 2006.286.01:27:51.85#ibcon#end of sib2, iclass 26, count 0 2006.286.01:27:51.85#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:27:51.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:27:51.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:27:51.85#ibcon#*before write, iclass 26, count 0 2006.286.01:27:51.85#ibcon#enter sib2, iclass 26, count 0 2006.286.01:27:51.85#ibcon#flushed, iclass 26, count 0 2006.286.01:27:51.85#ibcon#about to write, iclass 26, count 0 2006.286.01:27:51.85#ibcon#wrote, iclass 26, count 0 2006.286.01:27:51.85#ibcon#about to read 3, iclass 26, count 0 2006.286.01:27:51.89#ibcon#read 3, iclass 26, count 0 2006.286.01:27:51.89#ibcon#about to read 4, iclass 26, count 0 2006.286.01:27:51.89#ibcon#read 4, iclass 26, count 0 2006.286.01:27:51.89#ibcon#about to read 5, iclass 26, count 0 2006.286.01:27:51.89#ibcon#read 5, iclass 26, count 0 2006.286.01:27:51.89#ibcon#about to read 6, iclass 26, count 0 2006.286.01:27:51.89#ibcon#read 6, iclass 26, count 0 2006.286.01:27:51.89#ibcon#end of sib2, iclass 26, count 0 2006.286.01:27:51.89#ibcon#*after write, iclass 26, count 0 2006.286.01:27:51.89#ibcon#*before return 0, iclass 26, count 0 2006.286.01:27:51.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:27:51.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:27:51.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:27:51.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:27:51.90$vck44/vb=3,4 2006.286.01:27:51.90#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.01:27:51.90#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.01:27:51.90#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:51.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:27:51.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:27:51.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:27:51.94#ibcon#enter wrdev, iclass 28, count 2 2006.286.01:27:51.94#ibcon#first serial, iclass 28, count 2 2006.286.01:27:51.94#ibcon#enter sib2, iclass 28, count 2 2006.286.01:27:51.94#ibcon#flushed, iclass 28, count 2 2006.286.01:27:51.94#ibcon#about to write, iclass 28, count 2 2006.286.01:27:51.94#ibcon#wrote, iclass 28, count 2 2006.286.01:27:51.94#ibcon#about to read 3, iclass 28, count 2 2006.286.01:27:51.96#ibcon#read 3, iclass 28, count 2 2006.286.01:27:51.96#ibcon#about to read 4, iclass 28, count 2 2006.286.01:27:51.96#ibcon#read 4, iclass 28, count 2 2006.286.01:27:51.96#ibcon#about to read 5, iclass 28, count 2 2006.286.01:27:51.96#ibcon#read 5, iclass 28, count 2 2006.286.01:27:51.96#ibcon#about to read 6, iclass 28, count 2 2006.286.01:27:51.96#ibcon#read 6, iclass 28, count 2 2006.286.01:27:51.96#ibcon#end of sib2, iclass 28, count 2 2006.286.01:27:51.96#ibcon#*mode == 0, iclass 28, count 2 2006.286.01:27:51.96#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.01:27:51.96#ibcon#[27=AT03-04\r\n] 2006.286.01:27:51.96#ibcon#*before write, iclass 28, count 2 2006.286.01:27:51.96#ibcon#enter sib2, iclass 28, count 2 2006.286.01:27:51.96#ibcon#flushed, iclass 28, count 2 2006.286.01:27:51.96#ibcon#about to write, iclass 28, count 2 2006.286.01:27:51.96#ibcon#wrote, iclass 28, count 2 2006.286.01:27:51.96#ibcon#about to read 3, iclass 28, count 2 2006.286.01:27:51.99#ibcon#read 3, iclass 28, count 2 2006.286.01:27:51.99#ibcon#about to read 4, iclass 28, count 2 2006.286.01:27:51.99#ibcon#read 4, iclass 28, count 2 2006.286.01:27:51.99#ibcon#about to read 5, iclass 28, count 2 2006.286.01:27:51.99#ibcon#read 5, iclass 28, count 2 2006.286.01:27:51.99#ibcon#about to read 6, iclass 28, count 2 2006.286.01:27:51.99#ibcon#read 6, iclass 28, count 2 2006.286.01:27:51.99#ibcon#end of sib2, iclass 28, count 2 2006.286.01:27:51.99#ibcon#*after write, iclass 28, count 2 2006.286.01:27:51.99#ibcon#*before return 0, iclass 28, count 2 2006.286.01:27:51.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:27:51.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:27:51.99#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.01:27:51.99#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:51.99#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:27:52.11#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:27:52.11#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:27:52.11#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:27:52.11#ibcon#first serial, iclass 28, count 0 2006.286.01:27:52.11#ibcon#enter sib2, iclass 28, count 0 2006.286.01:27:52.11#ibcon#flushed, iclass 28, count 0 2006.286.01:27:52.11#ibcon#about to write, iclass 28, count 0 2006.286.01:27:52.11#ibcon#wrote, iclass 28, count 0 2006.286.01:27:52.11#ibcon#about to read 3, iclass 28, count 0 2006.286.01:27:52.13#ibcon#read 3, iclass 28, count 0 2006.286.01:27:52.13#ibcon#about to read 4, iclass 28, count 0 2006.286.01:27:52.13#ibcon#read 4, iclass 28, count 0 2006.286.01:27:52.13#ibcon#about to read 5, iclass 28, count 0 2006.286.01:27:52.13#ibcon#read 5, iclass 28, count 0 2006.286.01:27:52.13#ibcon#about to read 6, iclass 28, count 0 2006.286.01:27:52.13#ibcon#read 6, iclass 28, count 0 2006.286.01:27:52.13#ibcon#end of sib2, iclass 28, count 0 2006.286.01:27:52.13#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:27:52.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:27:52.13#ibcon#[27=USB\r\n] 2006.286.01:27:52.13#ibcon#*before write, iclass 28, count 0 2006.286.01:27:52.13#ibcon#enter sib2, iclass 28, count 0 2006.286.01:27:52.13#ibcon#flushed, iclass 28, count 0 2006.286.01:27:52.13#ibcon#about to write, iclass 28, count 0 2006.286.01:27:52.13#ibcon#wrote, iclass 28, count 0 2006.286.01:27:52.13#ibcon#about to read 3, iclass 28, count 0 2006.286.01:27:52.16#ibcon#read 3, iclass 28, count 0 2006.286.01:27:52.16#ibcon#about to read 4, iclass 28, count 0 2006.286.01:27:52.16#ibcon#read 4, iclass 28, count 0 2006.286.01:27:52.16#ibcon#about to read 5, iclass 28, count 0 2006.286.01:27:52.16#ibcon#read 5, iclass 28, count 0 2006.286.01:27:52.16#ibcon#about to read 6, iclass 28, count 0 2006.286.01:27:52.16#ibcon#read 6, iclass 28, count 0 2006.286.01:27:52.16#ibcon#end of sib2, iclass 28, count 0 2006.286.01:27:52.16#ibcon#*after write, iclass 28, count 0 2006.286.01:27:52.16#ibcon#*before return 0, iclass 28, count 0 2006.286.01:27:52.16#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:27:52.16#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:27:52.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:27:52.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:27:52.17$vck44/vblo=4,679.99 2006.286.01:27:52.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.01:27:52.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.01:27:52.17#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:52.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:27:52.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:27:52.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:27:52.17#ibcon#enter wrdev, iclass 30, count 0 2006.286.01:27:52.17#ibcon#first serial, iclass 30, count 0 2006.286.01:27:52.17#ibcon#enter sib2, iclass 30, count 0 2006.286.01:27:52.17#ibcon#flushed, iclass 30, count 0 2006.286.01:27:52.17#ibcon#about to write, iclass 30, count 0 2006.286.01:27:52.17#ibcon#wrote, iclass 30, count 0 2006.286.01:27:52.17#ibcon#about to read 3, iclass 30, count 0 2006.286.01:27:52.18#ibcon#read 3, iclass 30, count 0 2006.286.01:27:52.18#ibcon#about to read 4, iclass 30, count 0 2006.286.01:27:52.18#ibcon#read 4, iclass 30, count 0 2006.286.01:27:52.18#ibcon#about to read 5, iclass 30, count 0 2006.286.01:27:52.18#ibcon#read 5, iclass 30, count 0 2006.286.01:27:52.18#ibcon#about to read 6, iclass 30, count 0 2006.286.01:27:52.18#ibcon#read 6, iclass 30, count 0 2006.286.01:27:52.18#ibcon#end of sib2, iclass 30, count 0 2006.286.01:27:52.18#ibcon#*mode == 0, iclass 30, count 0 2006.286.01:27:52.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.01:27:52.18#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:27:52.18#ibcon#*before write, iclass 30, count 0 2006.286.01:27:52.18#ibcon#enter sib2, iclass 30, count 0 2006.286.01:27:52.18#ibcon#flushed, iclass 30, count 0 2006.286.01:27:52.18#ibcon#about to write, iclass 30, count 0 2006.286.01:27:52.18#ibcon#wrote, iclass 30, count 0 2006.286.01:27:52.18#ibcon#about to read 3, iclass 30, count 0 2006.286.01:27:52.22#ibcon#read 3, iclass 30, count 0 2006.286.01:27:52.22#ibcon#about to read 4, iclass 30, count 0 2006.286.01:27:52.22#ibcon#read 4, iclass 30, count 0 2006.286.01:27:52.22#ibcon#about to read 5, iclass 30, count 0 2006.286.01:27:52.22#ibcon#read 5, iclass 30, count 0 2006.286.01:27:52.22#ibcon#about to read 6, iclass 30, count 0 2006.286.01:27:52.22#ibcon#read 6, iclass 30, count 0 2006.286.01:27:52.22#ibcon#end of sib2, iclass 30, count 0 2006.286.01:27:52.22#ibcon#*after write, iclass 30, count 0 2006.286.01:27:52.22#ibcon#*before return 0, iclass 30, count 0 2006.286.01:27:52.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:27:52.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:27:52.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.01:27:52.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.01:27:52.23$vck44/vb=4,5 2006.286.01:27:52.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.01:27:52.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.01:27:52.23#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:52.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:27:52.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:27:52.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:27:52.27#ibcon#enter wrdev, iclass 32, count 2 2006.286.01:27:52.27#ibcon#first serial, iclass 32, count 2 2006.286.01:27:52.27#ibcon#enter sib2, iclass 32, count 2 2006.286.01:27:52.27#ibcon#flushed, iclass 32, count 2 2006.286.01:27:52.27#ibcon#about to write, iclass 32, count 2 2006.286.01:27:52.27#ibcon#wrote, iclass 32, count 2 2006.286.01:27:52.27#ibcon#about to read 3, iclass 32, count 2 2006.286.01:27:52.29#ibcon#read 3, iclass 32, count 2 2006.286.01:27:52.29#ibcon#about to read 4, iclass 32, count 2 2006.286.01:27:52.29#ibcon#read 4, iclass 32, count 2 2006.286.01:27:52.29#ibcon#about to read 5, iclass 32, count 2 2006.286.01:27:52.29#ibcon#read 5, iclass 32, count 2 2006.286.01:27:52.29#ibcon#about to read 6, iclass 32, count 2 2006.286.01:27:52.29#ibcon#read 6, iclass 32, count 2 2006.286.01:27:52.29#ibcon#end of sib2, iclass 32, count 2 2006.286.01:27:52.29#ibcon#*mode == 0, iclass 32, count 2 2006.286.01:27:52.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.01:27:52.29#ibcon#[27=AT04-05\r\n] 2006.286.01:27:52.29#ibcon#*before write, iclass 32, count 2 2006.286.01:27:52.29#ibcon#enter sib2, iclass 32, count 2 2006.286.01:27:52.29#ibcon#flushed, iclass 32, count 2 2006.286.01:27:52.29#ibcon#about to write, iclass 32, count 2 2006.286.01:27:52.29#ibcon#wrote, iclass 32, count 2 2006.286.01:27:52.29#ibcon#about to read 3, iclass 32, count 2 2006.286.01:27:52.32#ibcon#read 3, iclass 32, count 2 2006.286.01:27:52.32#ibcon#about to read 4, iclass 32, count 2 2006.286.01:27:52.32#ibcon#read 4, iclass 32, count 2 2006.286.01:27:52.32#ibcon#about to read 5, iclass 32, count 2 2006.286.01:27:52.32#ibcon#read 5, iclass 32, count 2 2006.286.01:27:52.32#ibcon#about to read 6, iclass 32, count 2 2006.286.01:27:52.32#ibcon#read 6, iclass 32, count 2 2006.286.01:27:52.32#ibcon#end of sib2, iclass 32, count 2 2006.286.01:27:52.32#ibcon#*after write, iclass 32, count 2 2006.286.01:27:52.32#ibcon#*before return 0, iclass 32, count 2 2006.286.01:27:52.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:27:52.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:27:52.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.01:27:52.32#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:52.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:27:52.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:27:52.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:27:52.44#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:27:52.44#ibcon#first serial, iclass 32, count 0 2006.286.01:27:52.44#ibcon#enter sib2, iclass 32, count 0 2006.286.01:27:52.44#ibcon#flushed, iclass 32, count 0 2006.286.01:27:52.44#ibcon#about to write, iclass 32, count 0 2006.286.01:27:52.44#ibcon#wrote, iclass 32, count 0 2006.286.01:27:52.44#ibcon#about to read 3, iclass 32, count 0 2006.286.01:27:52.46#ibcon#read 3, iclass 32, count 0 2006.286.01:27:52.46#ibcon#about to read 4, iclass 32, count 0 2006.286.01:27:52.46#ibcon#read 4, iclass 32, count 0 2006.286.01:27:52.46#ibcon#about to read 5, iclass 32, count 0 2006.286.01:27:52.46#ibcon#read 5, iclass 32, count 0 2006.286.01:27:52.46#ibcon#about to read 6, iclass 32, count 0 2006.286.01:27:52.46#ibcon#read 6, iclass 32, count 0 2006.286.01:27:52.46#ibcon#end of sib2, iclass 32, count 0 2006.286.01:27:52.46#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:27:52.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:27:52.46#ibcon#[27=USB\r\n] 2006.286.01:27:52.46#ibcon#*before write, iclass 32, count 0 2006.286.01:27:52.46#ibcon#enter sib2, iclass 32, count 0 2006.286.01:27:52.46#ibcon#flushed, iclass 32, count 0 2006.286.01:27:52.46#ibcon#about to write, iclass 32, count 0 2006.286.01:27:52.46#ibcon#wrote, iclass 32, count 0 2006.286.01:27:52.46#ibcon#about to read 3, iclass 32, count 0 2006.286.01:27:52.49#ibcon#read 3, iclass 32, count 0 2006.286.01:27:52.49#ibcon#about to read 4, iclass 32, count 0 2006.286.01:27:52.49#ibcon#read 4, iclass 32, count 0 2006.286.01:27:52.49#ibcon#about to read 5, iclass 32, count 0 2006.286.01:27:52.49#ibcon#read 5, iclass 32, count 0 2006.286.01:27:52.49#ibcon#about to read 6, iclass 32, count 0 2006.286.01:27:52.49#ibcon#read 6, iclass 32, count 0 2006.286.01:27:52.49#ibcon#end of sib2, iclass 32, count 0 2006.286.01:27:52.49#ibcon#*after write, iclass 32, count 0 2006.286.01:27:52.49#ibcon#*before return 0, iclass 32, count 0 2006.286.01:27:52.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:27:52.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:27:52.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:27:52.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:27:52.50$vck44/vblo=5,709.99 2006.286.01:27:52.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.01:27:52.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.01:27:52.50#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:52.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:27:52.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:27:52.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:27:52.50#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:27:52.50#ibcon#first serial, iclass 34, count 0 2006.286.01:27:52.50#ibcon#enter sib2, iclass 34, count 0 2006.286.01:27:52.50#ibcon#flushed, iclass 34, count 0 2006.286.01:27:52.50#ibcon#about to write, iclass 34, count 0 2006.286.01:27:52.50#ibcon#wrote, iclass 34, count 0 2006.286.01:27:52.50#ibcon#about to read 3, iclass 34, count 0 2006.286.01:27:52.51#ibcon#read 3, iclass 34, count 0 2006.286.01:27:52.51#ibcon#about to read 4, iclass 34, count 0 2006.286.01:27:52.51#ibcon#read 4, iclass 34, count 0 2006.286.01:27:52.51#ibcon#about to read 5, iclass 34, count 0 2006.286.01:27:52.51#ibcon#read 5, iclass 34, count 0 2006.286.01:27:52.51#ibcon#about to read 6, iclass 34, count 0 2006.286.01:27:52.51#ibcon#read 6, iclass 34, count 0 2006.286.01:27:52.51#ibcon#end of sib2, iclass 34, count 0 2006.286.01:27:52.51#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:27:52.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:27:52.51#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:27:52.51#ibcon#*before write, iclass 34, count 0 2006.286.01:27:52.51#ibcon#enter sib2, iclass 34, count 0 2006.286.01:27:52.51#ibcon#flushed, iclass 34, count 0 2006.286.01:27:52.51#ibcon#about to write, iclass 34, count 0 2006.286.01:27:52.51#ibcon#wrote, iclass 34, count 0 2006.286.01:27:52.51#ibcon#about to read 3, iclass 34, count 0 2006.286.01:27:52.55#ibcon#read 3, iclass 34, count 0 2006.286.01:27:52.55#ibcon#about to read 4, iclass 34, count 0 2006.286.01:27:52.55#ibcon#read 4, iclass 34, count 0 2006.286.01:27:52.55#ibcon#about to read 5, iclass 34, count 0 2006.286.01:27:52.55#ibcon#read 5, iclass 34, count 0 2006.286.01:27:52.55#ibcon#about to read 6, iclass 34, count 0 2006.286.01:27:52.55#ibcon#read 6, iclass 34, count 0 2006.286.01:27:52.55#ibcon#end of sib2, iclass 34, count 0 2006.286.01:27:52.55#ibcon#*after write, iclass 34, count 0 2006.286.01:27:52.55#ibcon#*before return 0, iclass 34, count 0 2006.286.01:27:52.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:27:52.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:27:52.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:27:52.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:27:52.56$vck44/vb=5,4 2006.286.01:27:52.56#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.01:27:52.56#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.01:27:52.56#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:52.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:27:52.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:27:52.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:27:52.60#ibcon#enter wrdev, iclass 36, count 2 2006.286.01:27:52.60#ibcon#first serial, iclass 36, count 2 2006.286.01:27:52.60#ibcon#enter sib2, iclass 36, count 2 2006.286.01:27:52.60#ibcon#flushed, iclass 36, count 2 2006.286.01:27:52.60#ibcon#about to write, iclass 36, count 2 2006.286.01:27:52.60#ibcon#wrote, iclass 36, count 2 2006.286.01:27:52.60#ibcon#about to read 3, iclass 36, count 2 2006.286.01:27:52.62#ibcon#read 3, iclass 36, count 2 2006.286.01:27:52.62#ibcon#about to read 4, iclass 36, count 2 2006.286.01:27:52.62#ibcon#read 4, iclass 36, count 2 2006.286.01:27:52.62#ibcon#about to read 5, iclass 36, count 2 2006.286.01:27:52.62#ibcon#read 5, iclass 36, count 2 2006.286.01:27:52.62#ibcon#about to read 6, iclass 36, count 2 2006.286.01:27:52.62#ibcon#read 6, iclass 36, count 2 2006.286.01:27:52.62#ibcon#end of sib2, iclass 36, count 2 2006.286.01:27:52.62#ibcon#*mode == 0, iclass 36, count 2 2006.286.01:27:52.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.01:27:52.62#ibcon#[27=AT05-04\r\n] 2006.286.01:27:52.62#ibcon#*before write, iclass 36, count 2 2006.286.01:27:52.62#ibcon#enter sib2, iclass 36, count 2 2006.286.01:27:52.62#ibcon#flushed, iclass 36, count 2 2006.286.01:27:52.62#ibcon#about to write, iclass 36, count 2 2006.286.01:27:52.62#ibcon#wrote, iclass 36, count 2 2006.286.01:27:52.62#ibcon#about to read 3, iclass 36, count 2 2006.286.01:27:52.65#ibcon#read 3, iclass 36, count 2 2006.286.01:27:52.65#ibcon#about to read 4, iclass 36, count 2 2006.286.01:27:52.65#ibcon#read 4, iclass 36, count 2 2006.286.01:27:52.65#ibcon#about to read 5, iclass 36, count 2 2006.286.01:27:52.65#ibcon#read 5, iclass 36, count 2 2006.286.01:27:52.65#ibcon#about to read 6, iclass 36, count 2 2006.286.01:27:52.65#ibcon#read 6, iclass 36, count 2 2006.286.01:27:52.65#ibcon#end of sib2, iclass 36, count 2 2006.286.01:27:52.65#ibcon#*after write, iclass 36, count 2 2006.286.01:27:52.65#ibcon#*before return 0, iclass 36, count 2 2006.286.01:27:52.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:27:52.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:27:52.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.01:27:52.65#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:52.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:27:52.66#abcon#<5=/03 3.1 7.1 21.06 811016.2\r\n> 2006.286.01:27:52.68#abcon#{5=INTERFACE CLEAR} 2006.286.01:27:52.74#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:27:52.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:27:52.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:27:52.77#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:27:52.77#ibcon#first serial, iclass 36, count 0 2006.286.01:27:52.77#ibcon#enter sib2, iclass 36, count 0 2006.286.01:27:52.77#ibcon#flushed, iclass 36, count 0 2006.286.01:27:52.77#ibcon#about to write, iclass 36, count 0 2006.286.01:27:52.77#ibcon#wrote, iclass 36, count 0 2006.286.01:27:52.77#ibcon#about to read 3, iclass 36, count 0 2006.286.01:27:52.79#ibcon#read 3, iclass 36, count 0 2006.286.01:27:52.79#ibcon#about to read 4, iclass 36, count 0 2006.286.01:27:52.79#ibcon#read 4, iclass 36, count 0 2006.286.01:27:52.79#ibcon#about to read 5, iclass 36, count 0 2006.286.01:27:52.79#ibcon#read 5, iclass 36, count 0 2006.286.01:27:52.79#ibcon#about to read 6, iclass 36, count 0 2006.286.01:27:52.79#ibcon#read 6, iclass 36, count 0 2006.286.01:27:52.79#ibcon#end of sib2, iclass 36, count 0 2006.286.01:27:52.79#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:27:52.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:27:52.79#ibcon#[27=USB\r\n] 2006.286.01:27:52.79#ibcon#*before write, iclass 36, count 0 2006.286.01:27:52.79#ibcon#enter sib2, iclass 36, count 0 2006.286.01:27:52.79#ibcon#flushed, iclass 36, count 0 2006.286.01:27:52.79#ibcon#about to write, iclass 36, count 0 2006.286.01:27:52.79#ibcon#wrote, iclass 36, count 0 2006.286.01:27:52.79#ibcon#about to read 3, iclass 36, count 0 2006.286.01:27:52.82#ibcon#read 3, iclass 36, count 0 2006.286.01:27:52.82#ibcon#about to read 4, iclass 36, count 0 2006.286.01:27:52.82#ibcon#read 4, iclass 36, count 0 2006.286.01:27:52.82#ibcon#about to read 5, iclass 36, count 0 2006.286.01:27:52.82#ibcon#read 5, iclass 36, count 0 2006.286.01:27:52.82#ibcon#about to read 6, iclass 36, count 0 2006.286.01:27:52.82#ibcon#read 6, iclass 36, count 0 2006.286.01:27:52.82#ibcon#end of sib2, iclass 36, count 0 2006.286.01:27:52.82#ibcon#*after write, iclass 36, count 0 2006.286.01:27:52.82#ibcon#*before return 0, iclass 36, count 0 2006.286.01:27:52.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:27:52.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:27:52.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:27:52.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:27:52.83$vck44/vblo=6,719.99 2006.286.01:27:52.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.01:27:52.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.01:27:52.83#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:52.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:27:52.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:27:52.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:27:52.83#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:27:52.83#ibcon#first serial, iclass 4, count 0 2006.286.01:27:52.83#ibcon#enter sib2, iclass 4, count 0 2006.286.01:27:52.83#ibcon#flushed, iclass 4, count 0 2006.286.01:27:52.83#ibcon#about to write, iclass 4, count 0 2006.286.01:27:52.83#ibcon#wrote, iclass 4, count 0 2006.286.01:27:52.83#ibcon#about to read 3, iclass 4, count 0 2006.286.01:27:52.84#ibcon#read 3, iclass 4, count 0 2006.286.01:27:52.84#ibcon#about to read 4, iclass 4, count 0 2006.286.01:27:52.84#ibcon#read 4, iclass 4, count 0 2006.286.01:27:52.84#ibcon#about to read 5, iclass 4, count 0 2006.286.01:27:52.84#ibcon#read 5, iclass 4, count 0 2006.286.01:27:52.84#ibcon#about to read 6, iclass 4, count 0 2006.286.01:27:52.84#ibcon#read 6, iclass 4, count 0 2006.286.01:27:52.84#ibcon#end of sib2, iclass 4, count 0 2006.286.01:27:52.84#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:27:52.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:27:52.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:27:52.84#ibcon#*before write, iclass 4, count 0 2006.286.01:27:52.84#ibcon#enter sib2, iclass 4, count 0 2006.286.01:27:52.84#ibcon#flushed, iclass 4, count 0 2006.286.01:27:52.84#ibcon#about to write, iclass 4, count 0 2006.286.01:27:52.84#ibcon#wrote, iclass 4, count 0 2006.286.01:27:52.84#ibcon#about to read 3, iclass 4, count 0 2006.286.01:27:52.88#ibcon#read 3, iclass 4, count 0 2006.286.01:27:52.88#ibcon#about to read 4, iclass 4, count 0 2006.286.01:27:52.88#ibcon#read 4, iclass 4, count 0 2006.286.01:27:52.88#ibcon#about to read 5, iclass 4, count 0 2006.286.01:27:52.88#ibcon#read 5, iclass 4, count 0 2006.286.01:27:52.88#ibcon#about to read 6, iclass 4, count 0 2006.286.01:27:52.88#ibcon#read 6, iclass 4, count 0 2006.286.01:27:52.88#ibcon#end of sib2, iclass 4, count 0 2006.286.01:27:52.88#ibcon#*after write, iclass 4, count 0 2006.286.01:27:52.88#ibcon#*before return 0, iclass 4, count 0 2006.286.01:27:52.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:27:52.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:27:52.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:27:52.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:27:52.89$vck44/vb=6,3 2006.286.01:27:52.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.01:27:52.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.01:27:52.89#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:52.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:27:52.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:27:52.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:27:52.93#ibcon#enter wrdev, iclass 6, count 2 2006.286.01:27:52.93#ibcon#first serial, iclass 6, count 2 2006.286.01:27:52.93#ibcon#enter sib2, iclass 6, count 2 2006.286.01:27:52.93#ibcon#flushed, iclass 6, count 2 2006.286.01:27:52.93#ibcon#about to write, iclass 6, count 2 2006.286.01:27:52.93#ibcon#wrote, iclass 6, count 2 2006.286.01:27:52.93#ibcon#about to read 3, iclass 6, count 2 2006.286.01:27:52.95#ibcon#read 3, iclass 6, count 2 2006.286.01:27:52.95#ibcon#about to read 4, iclass 6, count 2 2006.286.01:27:52.95#ibcon#read 4, iclass 6, count 2 2006.286.01:27:52.95#ibcon#about to read 5, iclass 6, count 2 2006.286.01:27:52.95#ibcon#read 5, iclass 6, count 2 2006.286.01:27:52.95#ibcon#about to read 6, iclass 6, count 2 2006.286.01:27:52.95#ibcon#read 6, iclass 6, count 2 2006.286.01:27:52.95#ibcon#end of sib2, iclass 6, count 2 2006.286.01:27:52.95#ibcon#*mode == 0, iclass 6, count 2 2006.286.01:27:52.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.01:27:52.95#ibcon#[27=AT06-03\r\n] 2006.286.01:27:52.95#ibcon#*before write, iclass 6, count 2 2006.286.01:27:52.95#ibcon#enter sib2, iclass 6, count 2 2006.286.01:27:52.95#ibcon#flushed, iclass 6, count 2 2006.286.01:27:52.95#ibcon#about to write, iclass 6, count 2 2006.286.01:27:52.95#ibcon#wrote, iclass 6, count 2 2006.286.01:27:52.95#ibcon#about to read 3, iclass 6, count 2 2006.286.01:27:52.98#ibcon#read 3, iclass 6, count 2 2006.286.01:27:52.98#ibcon#about to read 4, iclass 6, count 2 2006.286.01:27:52.98#ibcon#read 4, iclass 6, count 2 2006.286.01:27:52.98#ibcon#about to read 5, iclass 6, count 2 2006.286.01:27:52.98#ibcon#read 5, iclass 6, count 2 2006.286.01:27:52.98#ibcon#about to read 6, iclass 6, count 2 2006.286.01:27:52.98#ibcon#read 6, iclass 6, count 2 2006.286.01:27:52.98#ibcon#end of sib2, iclass 6, count 2 2006.286.01:27:52.98#ibcon#*after write, iclass 6, count 2 2006.286.01:27:52.98#ibcon#*before return 0, iclass 6, count 2 2006.286.01:27:52.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:27:52.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:27:52.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.01:27:52.98#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:52.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:27:53.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:27:53.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:27:53.10#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:27:53.10#ibcon#first serial, iclass 6, count 0 2006.286.01:27:53.10#ibcon#enter sib2, iclass 6, count 0 2006.286.01:27:53.10#ibcon#flushed, iclass 6, count 0 2006.286.01:27:53.10#ibcon#about to write, iclass 6, count 0 2006.286.01:27:53.10#ibcon#wrote, iclass 6, count 0 2006.286.01:27:53.10#ibcon#about to read 3, iclass 6, count 0 2006.286.01:27:53.12#ibcon#read 3, iclass 6, count 0 2006.286.01:27:53.12#ibcon#about to read 4, iclass 6, count 0 2006.286.01:27:53.12#ibcon#read 4, iclass 6, count 0 2006.286.01:27:53.12#ibcon#about to read 5, iclass 6, count 0 2006.286.01:27:53.12#ibcon#read 5, iclass 6, count 0 2006.286.01:27:53.12#ibcon#about to read 6, iclass 6, count 0 2006.286.01:27:53.12#ibcon#read 6, iclass 6, count 0 2006.286.01:27:53.12#ibcon#end of sib2, iclass 6, count 0 2006.286.01:27:53.12#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:27:53.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:27:53.12#ibcon#[27=USB\r\n] 2006.286.01:27:53.12#ibcon#*before write, iclass 6, count 0 2006.286.01:27:53.12#ibcon#enter sib2, iclass 6, count 0 2006.286.01:27:53.12#ibcon#flushed, iclass 6, count 0 2006.286.01:27:53.12#ibcon#about to write, iclass 6, count 0 2006.286.01:27:53.12#ibcon#wrote, iclass 6, count 0 2006.286.01:27:53.12#ibcon#about to read 3, iclass 6, count 0 2006.286.01:27:53.15#ibcon#read 3, iclass 6, count 0 2006.286.01:27:53.15#ibcon#about to read 4, iclass 6, count 0 2006.286.01:27:53.15#ibcon#read 4, iclass 6, count 0 2006.286.01:27:53.15#ibcon#about to read 5, iclass 6, count 0 2006.286.01:27:53.15#ibcon#read 5, iclass 6, count 0 2006.286.01:27:53.15#ibcon#about to read 6, iclass 6, count 0 2006.286.01:27:53.15#ibcon#read 6, iclass 6, count 0 2006.286.01:27:53.15#ibcon#end of sib2, iclass 6, count 0 2006.286.01:27:53.15#ibcon#*after write, iclass 6, count 0 2006.286.01:27:53.15#ibcon#*before return 0, iclass 6, count 0 2006.286.01:27:53.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:27:53.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:27:53.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:27:53.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:27:53.16$vck44/vblo=7,734.99 2006.286.01:27:53.16#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.01:27:53.16#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.01:27:53.16#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:53.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:27:53.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:27:53.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:27:53.16#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:27:53.16#ibcon#first serial, iclass 10, count 0 2006.286.01:27:53.16#ibcon#enter sib2, iclass 10, count 0 2006.286.01:27:53.16#ibcon#flushed, iclass 10, count 0 2006.286.01:27:53.16#ibcon#about to write, iclass 10, count 0 2006.286.01:27:53.16#ibcon#wrote, iclass 10, count 0 2006.286.01:27:53.16#ibcon#about to read 3, iclass 10, count 0 2006.286.01:27:53.17#ibcon#read 3, iclass 10, count 0 2006.286.01:27:53.17#ibcon#about to read 4, iclass 10, count 0 2006.286.01:27:53.17#ibcon#read 4, iclass 10, count 0 2006.286.01:27:53.17#ibcon#about to read 5, iclass 10, count 0 2006.286.01:27:53.17#ibcon#read 5, iclass 10, count 0 2006.286.01:27:53.17#ibcon#about to read 6, iclass 10, count 0 2006.286.01:27:53.17#ibcon#read 6, iclass 10, count 0 2006.286.01:27:53.17#ibcon#end of sib2, iclass 10, count 0 2006.286.01:27:53.17#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:27:53.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:27:53.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:27:53.17#ibcon#*before write, iclass 10, count 0 2006.286.01:27:53.17#ibcon#enter sib2, iclass 10, count 0 2006.286.01:27:53.17#ibcon#flushed, iclass 10, count 0 2006.286.01:27:53.17#ibcon#about to write, iclass 10, count 0 2006.286.01:27:53.17#ibcon#wrote, iclass 10, count 0 2006.286.01:27:53.17#ibcon#about to read 3, iclass 10, count 0 2006.286.01:27:53.21#ibcon#read 3, iclass 10, count 0 2006.286.01:27:53.21#ibcon#about to read 4, iclass 10, count 0 2006.286.01:27:53.21#ibcon#read 4, iclass 10, count 0 2006.286.01:27:53.21#ibcon#about to read 5, iclass 10, count 0 2006.286.01:27:53.21#ibcon#read 5, iclass 10, count 0 2006.286.01:27:53.21#ibcon#about to read 6, iclass 10, count 0 2006.286.01:27:53.21#ibcon#read 6, iclass 10, count 0 2006.286.01:27:53.21#ibcon#end of sib2, iclass 10, count 0 2006.286.01:27:53.21#ibcon#*after write, iclass 10, count 0 2006.286.01:27:53.21#ibcon#*before return 0, iclass 10, count 0 2006.286.01:27:53.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:27:53.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:27:53.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:27:53.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:27:53.22$vck44/vb=7,4 2006.286.01:27:53.22#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.01:27:53.22#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.01:27:53.22#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:53.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:27:53.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:27:53.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:27:53.26#ibcon#enter wrdev, iclass 12, count 2 2006.286.01:27:53.26#ibcon#first serial, iclass 12, count 2 2006.286.01:27:53.26#ibcon#enter sib2, iclass 12, count 2 2006.286.01:27:53.26#ibcon#flushed, iclass 12, count 2 2006.286.01:27:53.26#ibcon#about to write, iclass 12, count 2 2006.286.01:27:53.26#ibcon#wrote, iclass 12, count 2 2006.286.01:27:53.26#ibcon#about to read 3, iclass 12, count 2 2006.286.01:27:53.28#ibcon#read 3, iclass 12, count 2 2006.286.01:27:53.28#ibcon#about to read 4, iclass 12, count 2 2006.286.01:27:53.28#ibcon#read 4, iclass 12, count 2 2006.286.01:27:53.28#ibcon#about to read 5, iclass 12, count 2 2006.286.01:27:53.28#ibcon#read 5, iclass 12, count 2 2006.286.01:27:53.28#ibcon#about to read 6, iclass 12, count 2 2006.286.01:27:53.28#ibcon#read 6, iclass 12, count 2 2006.286.01:27:53.28#ibcon#end of sib2, iclass 12, count 2 2006.286.01:27:53.28#ibcon#*mode == 0, iclass 12, count 2 2006.286.01:27:53.28#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.01:27:53.28#ibcon#[27=AT07-04\r\n] 2006.286.01:27:53.28#ibcon#*before write, iclass 12, count 2 2006.286.01:27:53.28#ibcon#enter sib2, iclass 12, count 2 2006.286.01:27:53.28#ibcon#flushed, iclass 12, count 2 2006.286.01:27:53.28#ibcon#about to write, iclass 12, count 2 2006.286.01:27:53.28#ibcon#wrote, iclass 12, count 2 2006.286.01:27:53.28#ibcon#about to read 3, iclass 12, count 2 2006.286.01:27:53.31#ibcon#read 3, iclass 12, count 2 2006.286.01:27:53.31#ibcon#about to read 4, iclass 12, count 2 2006.286.01:27:53.31#ibcon#read 4, iclass 12, count 2 2006.286.01:27:53.31#ibcon#about to read 5, iclass 12, count 2 2006.286.01:27:53.31#ibcon#read 5, iclass 12, count 2 2006.286.01:27:53.31#ibcon#about to read 6, iclass 12, count 2 2006.286.01:27:53.31#ibcon#read 6, iclass 12, count 2 2006.286.01:27:53.31#ibcon#end of sib2, iclass 12, count 2 2006.286.01:27:53.31#ibcon#*after write, iclass 12, count 2 2006.286.01:27:53.31#ibcon#*before return 0, iclass 12, count 2 2006.286.01:27:53.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:27:53.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:27:53.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.01:27:53.31#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:53.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:27:53.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:27:53.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:27:53.43#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:27:53.43#ibcon#first serial, iclass 12, count 0 2006.286.01:27:53.43#ibcon#enter sib2, iclass 12, count 0 2006.286.01:27:53.43#ibcon#flushed, iclass 12, count 0 2006.286.01:27:53.43#ibcon#about to write, iclass 12, count 0 2006.286.01:27:53.43#ibcon#wrote, iclass 12, count 0 2006.286.01:27:53.43#ibcon#about to read 3, iclass 12, count 0 2006.286.01:27:53.45#ibcon#read 3, iclass 12, count 0 2006.286.01:27:53.45#ibcon#about to read 4, iclass 12, count 0 2006.286.01:27:53.45#ibcon#read 4, iclass 12, count 0 2006.286.01:27:53.45#ibcon#about to read 5, iclass 12, count 0 2006.286.01:27:53.45#ibcon#read 5, iclass 12, count 0 2006.286.01:27:53.45#ibcon#about to read 6, iclass 12, count 0 2006.286.01:27:53.45#ibcon#read 6, iclass 12, count 0 2006.286.01:27:53.45#ibcon#end of sib2, iclass 12, count 0 2006.286.01:27:53.45#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:27:53.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:27:53.45#ibcon#[27=USB\r\n] 2006.286.01:27:53.45#ibcon#*before write, iclass 12, count 0 2006.286.01:27:53.45#ibcon#enter sib2, iclass 12, count 0 2006.286.01:27:53.45#ibcon#flushed, iclass 12, count 0 2006.286.01:27:53.45#ibcon#about to write, iclass 12, count 0 2006.286.01:27:53.45#ibcon#wrote, iclass 12, count 0 2006.286.01:27:53.45#ibcon#about to read 3, iclass 12, count 0 2006.286.01:27:53.48#ibcon#read 3, iclass 12, count 0 2006.286.01:27:53.48#ibcon#about to read 4, iclass 12, count 0 2006.286.01:27:53.48#ibcon#read 4, iclass 12, count 0 2006.286.01:27:53.48#ibcon#about to read 5, iclass 12, count 0 2006.286.01:27:53.48#ibcon#read 5, iclass 12, count 0 2006.286.01:27:53.48#ibcon#about to read 6, iclass 12, count 0 2006.286.01:27:53.48#ibcon#read 6, iclass 12, count 0 2006.286.01:27:53.48#ibcon#end of sib2, iclass 12, count 0 2006.286.01:27:53.48#ibcon#*after write, iclass 12, count 0 2006.286.01:27:53.48#ibcon#*before return 0, iclass 12, count 0 2006.286.01:27:53.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:27:53.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:27:53.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:27:53.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:27:53.49$vck44/vblo=8,744.99 2006.286.01:27:53.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.01:27:53.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.01:27:53.49#ibcon#ireg 17 cls_cnt 0 2006.286.01:27:53.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:27:53.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:27:53.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:27:53.49#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:27:53.49#ibcon#first serial, iclass 14, count 0 2006.286.01:27:53.49#ibcon#enter sib2, iclass 14, count 0 2006.286.01:27:53.49#ibcon#flushed, iclass 14, count 0 2006.286.01:27:53.49#ibcon#about to write, iclass 14, count 0 2006.286.01:27:53.49#ibcon#wrote, iclass 14, count 0 2006.286.01:27:53.49#ibcon#about to read 3, iclass 14, count 0 2006.286.01:27:53.50#ibcon#read 3, iclass 14, count 0 2006.286.01:27:53.50#ibcon#about to read 4, iclass 14, count 0 2006.286.01:27:53.50#ibcon#read 4, iclass 14, count 0 2006.286.01:27:53.50#ibcon#about to read 5, iclass 14, count 0 2006.286.01:27:53.50#ibcon#read 5, iclass 14, count 0 2006.286.01:27:53.50#ibcon#about to read 6, iclass 14, count 0 2006.286.01:27:53.50#ibcon#read 6, iclass 14, count 0 2006.286.01:27:53.50#ibcon#end of sib2, iclass 14, count 0 2006.286.01:27:53.50#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:27:53.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:27:53.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:27:53.50#ibcon#*before write, iclass 14, count 0 2006.286.01:27:53.50#ibcon#enter sib2, iclass 14, count 0 2006.286.01:27:53.50#ibcon#flushed, iclass 14, count 0 2006.286.01:27:53.50#ibcon#about to write, iclass 14, count 0 2006.286.01:27:53.50#ibcon#wrote, iclass 14, count 0 2006.286.01:27:53.50#ibcon#about to read 3, iclass 14, count 0 2006.286.01:27:53.54#ibcon#read 3, iclass 14, count 0 2006.286.01:27:53.54#ibcon#about to read 4, iclass 14, count 0 2006.286.01:27:53.54#ibcon#read 4, iclass 14, count 0 2006.286.01:27:53.54#ibcon#about to read 5, iclass 14, count 0 2006.286.01:27:53.54#ibcon#read 5, iclass 14, count 0 2006.286.01:27:53.54#ibcon#about to read 6, iclass 14, count 0 2006.286.01:27:53.54#ibcon#read 6, iclass 14, count 0 2006.286.01:27:53.54#ibcon#end of sib2, iclass 14, count 0 2006.286.01:27:53.54#ibcon#*after write, iclass 14, count 0 2006.286.01:27:53.54#ibcon#*before return 0, iclass 14, count 0 2006.286.01:27:53.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:27:53.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:27:53.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:27:53.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:27:53.55$vck44/vb=8,4 2006.286.01:27:53.55#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.01:27:53.55#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.01:27:53.55#ibcon#ireg 11 cls_cnt 2 2006.286.01:27:53.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:27:53.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:27:53.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:27:53.59#ibcon#enter wrdev, iclass 16, count 2 2006.286.01:27:53.59#ibcon#first serial, iclass 16, count 2 2006.286.01:27:53.59#ibcon#enter sib2, iclass 16, count 2 2006.286.01:27:53.59#ibcon#flushed, iclass 16, count 2 2006.286.01:27:53.59#ibcon#about to write, iclass 16, count 2 2006.286.01:27:53.59#ibcon#wrote, iclass 16, count 2 2006.286.01:27:53.59#ibcon#about to read 3, iclass 16, count 2 2006.286.01:27:53.61#ibcon#read 3, iclass 16, count 2 2006.286.01:27:53.61#ibcon#about to read 4, iclass 16, count 2 2006.286.01:27:53.61#ibcon#read 4, iclass 16, count 2 2006.286.01:27:53.61#ibcon#about to read 5, iclass 16, count 2 2006.286.01:27:53.61#ibcon#read 5, iclass 16, count 2 2006.286.01:27:53.61#ibcon#about to read 6, iclass 16, count 2 2006.286.01:27:53.61#ibcon#read 6, iclass 16, count 2 2006.286.01:27:53.61#ibcon#end of sib2, iclass 16, count 2 2006.286.01:27:53.61#ibcon#*mode == 0, iclass 16, count 2 2006.286.01:27:53.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.01:27:53.61#ibcon#[27=AT08-04\r\n] 2006.286.01:27:53.61#ibcon#*before write, iclass 16, count 2 2006.286.01:27:53.61#ibcon#enter sib2, iclass 16, count 2 2006.286.01:27:53.61#ibcon#flushed, iclass 16, count 2 2006.286.01:27:53.61#ibcon#about to write, iclass 16, count 2 2006.286.01:27:53.61#ibcon#wrote, iclass 16, count 2 2006.286.01:27:53.61#ibcon#about to read 3, iclass 16, count 2 2006.286.01:27:53.64#ibcon#read 3, iclass 16, count 2 2006.286.01:27:53.64#ibcon#about to read 4, iclass 16, count 2 2006.286.01:27:53.64#ibcon#read 4, iclass 16, count 2 2006.286.01:27:53.64#ibcon#about to read 5, iclass 16, count 2 2006.286.01:27:53.64#ibcon#read 5, iclass 16, count 2 2006.286.01:27:53.64#ibcon#about to read 6, iclass 16, count 2 2006.286.01:27:53.64#ibcon#read 6, iclass 16, count 2 2006.286.01:27:53.64#ibcon#end of sib2, iclass 16, count 2 2006.286.01:27:53.64#ibcon#*after write, iclass 16, count 2 2006.286.01:27:53.64#ibcon#*before return 0, iclass 16, count 2 2006.286.01:27:53.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:27:53.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:27:53.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.01:27:53.64#ibcon#ireg 7 cls_cnt 0 2006.286.01:27:53.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:27:53.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:27:53.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:27:53.76#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:27:53.76#ibcon#first serial, iclass 16, count 0 2006.286.01:27:53.76#ibcon#enter sib2, iclass 16, count 0 2006.286.01:27:53.76#ibcon#flushed, iclass 16, count 0 2006.286.01:27:53.76#ibcon#about to write, iclass 16, count 0 2006.286.01:27:53.76#ibcon#wrote, iclass 16, count 0 2006.286.01:27:53.76#ibcon#about to read 3, iclass 16, count 0 2006.286.01:27:53.78#ibcon#read 3, iclass 16, count 0 2006.286.01:27:53.78#ibcon#about to read 4, iclass 16, count 0 2006.286.01:27:53.78#ibcon#read 4, iclass 16, count 0 2006.286.01:27:53.78#ibcon#about to read 5, iclass 16, count 0 2006.286.01:27:53.78#ibcon#read 5, iclass 16, count 0 2006.286.01:27:53.78#ibcon#about to read 6, iclass 16, count 0 2006.286.01:27:53.78#ibcon#read 6, iclass 16, count 0 2006.286.01:27:53.78#ibcon#end of sib2, iclass 16, count 0 2006.286.01:27:53.78#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:27:53.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:27:53.78#ibcon#[27=USB\r\n] 2006.286.01:27:53.78#ibcon#*before write, iclass 16, count 0 2006.286.01:27:53.78#ibcon#enter sib2, iclass 16, count 0 2006.286.01:27:53.78#ibcon#flushed, iclass 16, count 0 2006.286.01:27:53.78#ibcon#about to write, iclass 16, count 0 2006.286.01:27:53.78#ibcon#wrote, iclass 16, count 0 2006.286.01:27:53.78#ibcon#about to read 3, iclass 16, count 0 2006.286.01:27:53.81#ibcon#read 3, iclass 16, count 0 2006.286.01:27:53.81#ibcon#about to read 4, iclass 16, count 0 2006.286.01:27:53.81#ibcon#read 4, iclass 16, count 0 2006.286.01:27:53.81#ibcon#about to read 5, iclass 16, count 0 2006.286.01:27:53.81#ibcon#read 5, iclass 16, count 0 2006.286.01:27:53.81#ibcon#about to read 6, iclass 16, count 0 2006.286.01:27:53.81#ibcon#read 6, iclass 16, count 0 2006.286.01:27:53.81#ibcon#end of sib2, iclass 16, count 0 2006.286.01:27:53.81#ibcon#*after write, iclass 16, count 0 2006.286.01:27:53.81#ibcon#*before return 0, iclass 16, count 0 2006.286.01:27:53.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:27:53.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:27:53.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:27:53.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:27:53.82$vck44/vabw=wide 2006.286.01:27:53.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.01:27:53.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.01:27:53.82#ibcon#ireg 8 cls_cnt 0 2006.286.01:27:53.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:27:53.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:27:53.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:27:53.82#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:27:53.82#ibcon#first serial, iclass 18, count 0 2006.286.01:27:53.82#ibcon#enter sib2, iclass 18, count 0 2006.286.01:27:53.82#ibcon#flushed, iclass 18, count 0 2006.286.01:27:53.82#ibcon#about to write, iclass 18, count 0 2006.286.01:27:53.82#ibcon#wrote, iclass 18, count 0 2006.286.01:27:53.82#ibcon#about to read 3, iclass 18, count 0 2006.286.01:27:53.83#ibcon#read 3, iclass 18, count 0 2006.286.01:27:53.83#ibcon#about to read 4, iclass 18, count 0 2006.286.01:27:53.83#ibcon#read 4, iclass 18, count 0 2006.286.01:27:53.83#ibcon#about to read 5, iclass 18, count 0 2006.286.01:27:53.83#ibcon#read 5, iclass 18, count 0 2006.286.01:27:53.83#ibcon#about to read 6, iclass 18, count 0 2006.286.01:27:53.83#ibcon#read 6, iclass 18, count 0 2006.286.01:27:53.83#ibcon#end of sib2, iclass 18, count 0 2006.286.01:27:53.83#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:27:53.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:27:53.83#ibcon#[25=BW32\r\n] 2006.286.01:27:53.83#ibcon#*before write, iclass 18, count 0 2006.286.01:27:53.83#ibcon#enter sib2, iclass 18, count 0 2006.286.01:27:53.83#ibcon#flushed, iclass 18, count 0 2006.286.01:27:53.83#ibcon#about to write, iclass 18, count 0 2006.286.01:27:53.83#ibcon#wrote, iclass 18, count 0 2006.286.01:27:53.83#ibcon#about to read 3, iclass 18, count 0 2006.286.01:27:53.86#ibcon#read 3, iclass 18, count 0 2006.286.01:27:53.86#ibcon#about to read 4, iclass 18, count 0 2006.286.01:27:53.86#ibcon#read 4, iclass 18, count 0 2006.286.01:27:53.86#ibcon#about to read 5, iclass 18, count 0 2006.286.01:27:53.86#ibcon#read 5, iclass 18, count 0 2006.286.01:27:53.86#ibcon#about to read 6, iclass 18, count 0 2006.286.01:27:53.86#ibcon#read 6, iclass 18, count 0 2006.286.01:27:53.86#ibcon#end of sib2, iclass 18, count 0 2006.286.01:27:53.86#ibcon#*after write, iclass 18, count 0 2006.286.01:27:53.86#ibcon#*before return 0, iclass 18, count 0 2006.286.01:27:53.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:27:53.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:27:53.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:27:53.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:27:53.87$vck44/vbbw=wide 2006.286.01:27:53.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.01:27:53.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.01:27:53.87#ibcon#ireg 8 cls_cnt 0 2006.286.01:27:53.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:27:53.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:27:53.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:27:53.92#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:27:53.92#ibcon#first serial, iclass 20, count 0 2006.286.01:27:53.92#ibcon#enter sib2, iclass 20, count 0 2006.286.01:27:53.92#ibcon#flushed, iclass 20, count 0 2006.286.01:27:53.92#ibcon#about to write, iclass 20, count 0 2006.286.01:27:53.92#ibcon#wrote, iclass 20, count 0 2006.286.01:27:53.92#ibcon#about to read 3, iclass 20, count 0 2006.286.01:27:53.94#ibcon#read 3, iclass 20, count 0 2006.286.01:27:53.94#ibcon#about to read 4, iclass 20, count 0 2006.286.01:27:53.94#ibcon#read 4, iclass 20, count 0 2006.286.01:27:53.94#ibcon#about to read 5, iclass 20, count 0 2006.286.01:27:53.94#ibcon#read 5, iclass 20, count 0 2006.286.01:27:53.94#ibcon#about to read 6, iclass 20, count 0 2006.286.01:27:53.94#ibcon#read 6, iclass 20, count 0 2006.286.01:27:53.94#ibcon#end of sib2, iclass 20, count 0 2006.286.01:27:53.94#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:27:53.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:27:53.94#ibcon#[27=BW32\r\n] 2006.286.01:27:53.94#ibcon#*before write, iclass 20, count 0 2006.286.01:27:53.94#ibcon#enter sib2, iclass 20, count 0 2006.286.01:27:53.94#ibcon#flushed, iclass 20, count 0 2006.286.01:27:53.94#ibcon#about to write, iclass 20, count 0 2006.286.01:27:53.94#ibcon#wrote, iclass 20, count 0 2006.286.01:27:53.94#ibcon#about to read 3, iclass 20, count 0 2006.286.01:27:53.97#ibcon#read 3, iclass 20, count 0 2006.286.01:27:53.97#ibcon#about to read 4, iclass 20, count 0 2006.286.01:27:53.97#ibcon#read 4, iclass 20, count 0 2006.286.01:27:53.97#ibcon#about to read 5, iclass 20, count 0 2006.286.01:27:53.97#ibcon#read 5, iclass 20, count 0 2006.286.01:27:53.97#ibcon#about to read 6, iclass 20, count 0 2006.286.01:27:53.97#ibcon#read 6, iclass 20, count 0 2006.286.01:27:53.97#ibcon#end of sib2, iclass 20, count 0 2006.286.01:27:53.97#ibcon#*after write, iclass 20, count 0 2006.286.01:27:53.97#ibcon#*before return 0, iclass 20, count 0 2006.286.01:27:53.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:27:53.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:27:53.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:27:53.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:27:53.98$setupk4/ifdk4 2006.286.01:27:53.98$ifdk4/lo= 2006.286.01:27:53.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:27:53.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:27:53.98$ifdk4/patch= 2006.286.01:27:53.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:27:53.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:27:53.98$setupk4/!*+20s 2006.286.01:28:02.83#abcon#<5=/03 3.0 7.1 21.06 811016.2\r\n> 2006.286.01:28:02.85#abcon#{5=INTERFACE CLEAR} 2006.286.01:28:02.91#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:28:08.63$setupk4/"tpicd 2006.286.01:28:08.63$setupk4/echo=off 2006.286.01:28:08.63$setupk4/xlog=off 2006.286.01:28:08.63:!2006.286.01:34:54 2006.286.01:28:16.14#trakl#Source acquired 2006.286.01:28:16.15#flagr#flagr/antenna,acquired 2006.286.01:34:54.00:preob 2006.286.01:34:54.14/onsource/TRACKING 2006.286.01:34:54.14:!2006.286.01:35:04 2006.286.01:35:04.00:"tape 2006.286.01:35:04.00:"st=record 2006.286.01:35:04.00:data_valid=on 2006.286.01:35:04.00:midob 2006.286.01:35:04.14/onsource/TRACKING 2006.286.01:35:04.14/wx/21.09,1016.1,79 2006.286.01:35:04.26/cable/+6.5008E-03 2006.286.01:35:05.35/va/01,07,usb,yes,32,35 2006.286.01:35:05.35/va/02,06,usb,yes,32,33 2006.286.01:35:05.35/va/03,07,usb,yes,32,33 2006.286.01:35:05.35/va/04,06,usb,yes,33,35 2006.286.01:35:05.35/va/05,03,usb,yes,33,33 2006.286.01:35:05.35/va/06,04,usb,yes,29,29 2006.286.01:35:05.35/va/07,04,usb,yes,30,31 2006.286.01:35:05.35/va/08,03,usb,yes,31,37 2006.286.01:35:05.58/valo/01,524.99,yes,locked 2006.286.01:35:05.58/valo/02,534.99,yes,locked 2006.286.01:35:05.58/valo/03,564.99,yes,locked 2006.286.01:35:05.58/valo/04,624.99,yes,locked 2006.286.01:35:05.58/valo/05,734.99,yes,locked 2006.286.01:35:05.58/valo/06,814.99,yes,locked 2006.286.01:35:05.58/valo/07,864.99,yes,locked 2006.286.01:35:05.58/valo/08,884.99,yes,locked 2006.286.01:35:06.67/vb/01,04,usb,yes,31,28 2006.286.01:35:06.67/vb/02,05,usb,yes,29,29 2006.286.01:35:06.67/vb/03,04,usb,yes,30,33 2006.286.01:35:06.67/vb/04,05,usb,yes,30,29 2006.286.01:35:06.67/vb/05,04,usb,yes,27,29 2006.286.01:35:06.67/vb/06,03,usb,yes,38,34 2006.286.01:35:06.67/vb/07,04,usb,yes,31,31 2006.286.01:35:06.67/vb/08,04,usb,yes,28,32 2006.286.01:35:06.90/vblo/01,629.99,yes,locked 2006.286.01:35:06.90/vblo/02,634.99,yes,locked 2006.286.01:35:06.90/vblo/03,649.99,yes,locked 2006.286.01:35:06.90/vblo/04,679.99,yes,locked 2006.286.01:35:06.90/vblo/05,709.99,yes,locked 2006.286.01:35:06.90/vblo/06,719.99,yes,locked 2006.286.01:35:06.90/vblo/07,734.99,yes,locked 2006.286.01:35:06.90/vblo/08,744.99,yes,locked 2006.286.01:35:07.05/vabw/8 2006.286.01:35:07.20/vbbw/8 2006.286.01:35:07.29/xfe/off,on,12.0 2006.286.01:35:07.66/ifatt/23,28,28,28 2006.286.01:35:08.07/fmout-gps/S +2.75E-07 2006.286.01:35:08.09:!2006.286.01:35:54 2006.286.01:35:54.00:data_valid=off 2006.286.01:35:54.00:"et 2006.286.01:35:54.00:!+3s 2006.286.01:35:57.01:"tape 2006.286.01:35:57.01:postob 2006.286.01:35:57.14/cable/+6.5025E-03 2006.286.01:35:57.14/wx/21.10,1016.1,79 2006.286.01:35:58.07/fmout-gps/S +2.77E-07 2006.286.01:35:58.07:scan_name=286-0141,jd0610,40 2006.286.01:35:58.07:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.286.01:35:59.14#flagr#flagr/antenna,new-source 2006.286.01:35:59.14:checkk5 2006.286.01:35:59.53/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:35:59.90/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:36:00.48/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:36:00.82/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:36:01.36/chk_obsdata//k5ts1/T2860135??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.01:36:01.75/chk_obsdata//k5ts2/T2860135??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.01:36:02.18/chk_obsdata//k5ts3/T2860135??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.01:36:02.80/chk_obsdata//k5ts4/T2860135??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.01:36:03.85/k5log//k5ts1_log_newline 2006.286.01:36:05.32/k5log//k5ts2_log_newline 2006.286.01:36:06.03/k5log//k5ts3_log_newline 2006.286.01:36:06.79/k5log//k5ts4_log_newline 2006.286.01:36:06.81/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:36:06.81:setupk4=1 2006.286.01:36:06.81$setupk4/echo=on 2006.286.01:36:06.81$setupk4/pcalon 2006.286.01:36:06.81$pcalon/"no phase cal control is implemented here 2006.286.01:36:06.81$setupk4/"tpicd=stop 2006.286.01:36:06.81$setupk4/"rec=synch_on 2006.286.01:36:06.81$setupk4/"rec_mode=128 2006.286.01:36:06.81$setupk4/!* 2006.286.01:36:06.81$setupk4/recpk4 2006.286.01:36:06.81$recpk4/recpatch= 2006.286.01:36:06.82$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:36:06.82$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:36:06.82$setupk4/vck44 2006.286.01:36:06.82$vck44/valo=1,524.99 2006.286.01:36:06.82#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.01:36:06.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.01:36:06.82#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:06.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:36:06.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:36:06.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:36:06.82#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:36:06.82#ibcon#first serial, iclass 32, count 0 2006.286.01:36:06.82#ibcon#enter sib2, iclass 32, count 0 2006.286.01:36:06.82#ibcon#flushed, iclass 32, count 0 2006.286.01:36:06.82#ibcon#about to write, iclass 32, count 0 2006.286.01:36:06.82#ibcon#wrote, iclass 32, count 0 2006.286.01:36:06.82#ibcon#about to read 3, iclass 32, count 0 2006.286.01:36:06.83#ibcon#read 3, iclass 32, count 0 2006.286.01:36:06.83#ibcon#about to read 4, iclass 32, count 0 2006.286.01:36:06.83#ibcon#read 4, iclass 32, count 0 2006.286.01:36:06.83#ibcon#about to read 5, iclass 32, count 0 2006.286.01:36:06.83#ibcon#read 5, iclass 32, count 0 2006.286.01:36:06.83#ibcon#about to read 6, iclass 32, count 0 2006.286.01:36:06.83#ibcon#read 6, iclass 32, count 0 2006.286.01:36:06.83#ibcon#end of sib2, iclass 32, count 0 2006.286.01:36:06.83#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:36:06.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:36:06.83#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:36:06.83#ibcon#*before write, iclass 32, count 0 2006.286.01:36:06.83#ibcon#enter sib2, iclass 32, count 0 2006.286.01:36:06.83#ibcon#flushed, iclass 32, count 0 2006.286.01:36:06.83#ibcon#about to write, iclass 32, count 0 2006.286.01:36:06.83#ibcon#wrote, iclass 32, count 0 2006.286.01:36:06.83#ibcon#about to read 3, iclass 32, count 0 2006.286.01:36:06.88#ibcon#read 3, iclass 32, count 0 2006.286.01:36:06.88#ibcon#about to read 4, iclass 32, count 0 2006.286.01:36:06.88#ibcon#read 4, iclass 32, count 0 2006.286.01:36:06.88#ibcon#about to read 5, iclass 32, count 0 2006.286.01:36:06.88#ibcon#read 5, iclass 32, count 0 2006.286.01:36:06.88#ibcon#about to read 6, iclass 32, count 0 2006.286.01:36:06.88#ibcon#read 6, iclass 32, count 0 2006.286.01:36:06.88#ibcon#end of sib2, iclass 32, count 0 2006.286.01:36:06.88#ibcon#*after write, iclass 32, count 0 2006.286.01:36:06.88#ibcon#*before return 0, iclass 32, count 0 2006.286.01:36:06.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:36:06.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:36:06.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:36:06.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:36:06.88$vck44/va=1,7 2006.286.01:36:06.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.01:36:06.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.01:36:06.88#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:06.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:36:06.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:36:06.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:36:06.88#ibcon#enter wrdev, iclass 34, count 2 2006.286.01:36:06.88#ibcon#first serial, iclass 34, count 2 2006.286.01:36:06.88#ibcon#enter sib2, iclass 34, count 2 2006.286.01:36:06.88#ibcon#flushed, iclass 34, count 2 2006.286.01:36:06.88#ibcon#about to write, iclass 34, count 2 2006.286.01:36:06.88#ibcon#wrote, iclass 34, count 2 2006.286.01:36:06.88#ibcon#about to read 3, iclass 34, count 2 2006.286.01:36:06.90#ibcon#read 3, iclass 34, count 2 2006.286.01:36:06.90#ibcon#about to read 4, iclass 34, count 2 2006.286.01:36:06.90#ibcon#read 4, iclass 34, count 2 2006.286.01:36:06.90#ibcon#about to read 5, iclass 34, count 2 2006.286.01:36:06.90#ibcon#read 5, iclass 34, count 2 2006.286.01:36:06.90#ibcon#about to read 6, iclass 34, count 2 2006.286.01:36:06.90#ibcon#read 6, iclass 34, count 2 2006.286.01:36:06.90#ibcon#end of sib2, iclass 34, count 2 2006.286.01:36:06.90#ibcon#*mode == 0, iclass 34, count 2 2006.286.01:36:06.90#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.01:36:06.90#ibcon#[25=AT01-07\r\n] 2006.286.01:36:06.90#ibcon#*before write, iclass 34, count 2 2006.286.01:36:06.90#ibcon#enter sib2, iclass 34, count 2 2006.286.01:36:06.90#ibcon#flushed, iclass 34, count 2 2006.286.01:36:06.90#ibcon#about to write, iclass 34, count 2 2006.286.01:36:06.90#ibcon#wrote, iclass 34, count 2 2006.286.01:36:06.90#ibcon#about to read 3, iclass 34, count 2 2006.286.01:36:06.93#ibcon#read 3, iclass 34, count 2 2006.286.01:36:06.93#ibcon#about to read 4, iclass 34, count 2 2006.286.01:36:06.93#ibcon#read 4, iclass 34, count 2 2006.286.01:36:06.93#ibcon#about to read 5, iclass 34, count 2 2006.286.01:36:06.93#ibcon#read 5, iclass 34, count 2 2006.286.01:36:06.93#ibcon#about to read 6, iclass 34, count 2 2006.286.01:36:06.93#ibcon#read 6, iclass 34, count 2 2006.286.01:36:06.93#ibcon#end of sib2, iclass 34, count 2 2006.286.01:36:06.93#ibcon#*after write, iclass 34, count 2 2006.286.01:36:06.93#ibcon#*before return 0, iclass 34, count 2 2006.286.01:36:06.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:36:06.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:36:06.93#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.01:36:06.93#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:06.93#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:36:07.05#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:36:07.05#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:36:07.05#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:36:07.05#ibcon#first serial, iclass 34, count 0 2006.286.01:36:07.05#ibcon#enter sib2, iclass 34, count 0 2006.286.01:36:07.05#ibcon#flushed, iclass 34, count 0 2006.286.01:36:07.05#ibcon#about to write, iclass 34, count 0 2006.286.01:36:07.05#ibcon#wrote, iclass 34, count 0 2006.286.01:36:07.05#ibcon#about to read 3, iclass 34, count 0 2006.286.01:36:07.07#ibcon#read 3, iclass 34, count 0 2006.286.01:36:07.07#ibcon#about to read 4, iclass 34, count 0 2006.286.01:36:07.07#ibcon#read 4, iclass 34, count 0 2006.286.01:36:07.07#ibcon#about to read 5, iclass 34, count 0 2006.286.01:36:07.07#ibcon#read 5, iclass 34, count 0 2006.286.01:36:07.07#ibcon#about to read 6, iclass 34, count 0 2006.286.01:36:07.07#ibcon#read 6, iclass 34, count 0 2006.286.01:36:07.07#ibcon#end of sib2, iclass 34, count 0 2006.286.01:36:07.07#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:36:07.07#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:36:07.07#ibcon#[25=USB\r\n] 2006.286.01:36:07.07#ibcon#*before write, iclass 34, count 0 2006.286.01:36:07.07#ibcon#enter sib2, iclass 34, count 0 2006.286.01:36:07.07#ibcon#flushed, iclass 34, count 0 2006.286.01:36:07.07#ibcon#about to write, iclass 34, count 0 2006.286.01:36:07.07#ibcon#wrote, iclass 34, count 0 2006.286.01:36:07.07#ibcon#about to read 3, iclass 34, count 0 2006.286.01:36:07.10#ibcon#read 3, iclass 34, count 0 2006.286.01:36:07.10#ibcon#about to read 4, iclass 34, count 0 2006.286.01:36:07.10#ibcon#read 4, iclass 34, count 0 2006.286.01:36:07.10#ibcon#about to read 5, iclass 34, count 0 2006.286.01:36:07.10#ibcon#read 5, iclass 34, count 0 2006.286.01:36:07.10#ibcon#about to read 6, iclass 34, count 0 2006.286.01:36:07.10#ibcon#read 6, iclass 34, count 0 2006.286.01:36:07.10#ibcon#end of sib2, iclass 34, count 0 2006.286.01:36:07.10#ibcon#*after write, iclass 34, count 0 2006.286.01:36:07.10#ibcon#*before return 0, iclass 34, count 0 2006.286.01:36:07.10#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:36:07.10#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:36:07.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:36:07.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:36:07.10$vck44/valo=2,534.99 2006.286.01:36:07.10#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.01:36:07.10#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.01:36:07.10#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:07.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:36:07.10#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:36:07.10#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:36:07.10#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:36:07.10#ibcon#first serial, iclass 36, count 0 2006.286.01:36:07.10#ibcon#enter sib2, iclass 36, count 0 2006.286.01:36:07.10#ibcon#flushed, iclass 36, count 0 2006.286.01:36:07.10#ibcon#about to write, iclass 36, count 0 2006.286.01:36:07.10#ibcon#wrote, iclass 36, count 0 2006.286.01:36:07.10#ibcon#about to read 3, iclass 36, count 0 2006.286.01:36:07.12#ibcon#read 3, iclass 36, count 0 2006.286.01:36:07.12#ibcon#about to read 4, iclass 36, count 0 2006.286.01:36:07.12#ibcon#read 4, iclass 36, count 0 2006.286.01:36:07.12#ibcon#about to read 5, iclass 36, count 0 2006.286.01:36:07.12#ibcon#read 5, iclass 36, count 0 2006.286.01:36:07.12#ibcon#about to read 6, iclass 36, count 0 2006.286.01:36:07.12#ibcon#read 6, iclass 36, count 0 2006.286.01:36:07.12#ibcon#end of sib2, iclass 36, count 0 2006.286.01:36:07.12#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:36:07.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:36:07.12#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:36:07.12#ibcon#*before write, iclass 36, count 0 2006.286.01:36:07.12#ibcon#enter sib2, iclass 36, count 0 2006.286.01:36:07.12#ibcon#flushed, iclass 36, count 0 2006.286.01:36:07.12#ibcon#about to write, iclass 36, count 0 2006.286.01:36:07.12#ibcon#wrote, iclass 36, count 0 2006.286.01:36:07.12#ibcon#about to read 3, iclass 36, count 0 2006.286.01:36:07.16#ibcon#read 3, iclass 36, count 0 2006.286.01:36:07.16#ibcon#about to read 4, iclass 36, count 0 2006.286.01:36:07.16#ibcon#read 4, iclass 36, count 0 2006.286.01:36:07.16#ibcon#about to read 5, iclass 36, count 0 2006.286.01:36:07.16#ibcon#read 5, iclass 36, count 0 2006.286.01:36:07.16#ibcon#about to read 6, iclass 36, count 0 2006.286.01:36:07.16#ibcon#read 6, iclass 36, count 0 2006.286.01:36:07.16#ibcon#end of sib2, iclass 36, count 0 2006.286.01:36:07.16#ibcon#*after write, iclass 36, count 0 2006.286.01:36:07.16#ibcon#*before return 0, iclass 36, count 0 2006.286.01:36:07.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:36:07.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:36:07.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:36:07.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:36:07.16$vck44/va=2,6 2006.286.01:36:07.16#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.01:36:07.16#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.01:36:07.16#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:07.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:36:07.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:36:07.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:36:07.22#ibcon#enter wrdev, iclass 38, count 2 2006.286.01:36:07.22#ibcon#first serial, iclass 38, count 2 2006.286.01:36:07.22#ibcon#enter sib2, iclass 38, count 2 2006.286.01:36:07.22#ibcon#flushed, iclass 38, count 2 2006.286.01:36:07.22#ibcon#about to write, iclass 38, count 2 2006.286.01:36:07.22#ibcon#wrote, iclass 38, count 2 2006.286.01:36:07.22#ibcon#about to read 3, iclass 38, count 2 2006.286.01:36:07.24#ibcon#read 3, iclass 38, count 2 2006.286.01:36:07.24#ibcon#about to read 4, iclass 38, count 2 2006.286.01:36:07.24#ibcon#read 4, iclass 38, count 2 2006.286.01:36:07.24#ibcon#about to read 5, iclass 38, count 2 2006.286.01:36:07.24#ibcon#read 5, iclass 38, count 2 2006.286.01:36:07.24#ibcon#about to read 6, iclass 38, count 2 2006.286.01:36:07.24#ibcon#read 6, iclass 38, count 2 2006.286.01:36:07.24#ibcon#end of sib2, iclass 38, count 2 2006.286.01:36:07.24#ibcon#*mode == 0, iclass 38, count 2 2006.286.01:36:07.24#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.01:36:07.24#ibcon#[25=AT02-06\r\n] 2006.286.01:36:07.24#ibcon#*before write, iclass 38, count 2 2006.286.01:36:07.24#ibcon#enter sib2, iclass 38, count 2 2006.286.01:36:07.24#ibcon#flushed, iclass 38, count 2 2006.286.01:36:07.24#ibcon#about to write, iclass 38, count 2 2006.286.01:36:07.24#ibcon#wrote, iclass 38, count 2 2006.286.01:36:07.24#ibcon#about to read 3, iclass 38, count 2 2006.286.01:36:07.27#ibcon#read 3, iclass 38, count 2 2006.286.01:36:07.27#ibcon#about to read 4, iclass 38, count 2 2006.286.01:36:07.27#ibcon#read 4, iclass 38, count 2 2006.286.01:36:07.27#ibcon#about to read 5, iclass 38, count 2 2006.286.01:36:07.27#ibcon#read 5, iclass 38, count 2 2006.286.01:36:07.27#ibcon#about to read 6, iclass 38, count 2 2006.286.01:36:07.27#ibcon#read 6, iclass 38, count 2 2006.286.01:36:07.27#ibcon#end of sib2, iclass 38, count 2 2006.286.01:36:07.27#ibcon#*after write, iclass 38, count 2 2006.286.01:36:07.27#ibcon#*before return 0, iclass 38, count 2 2006.286.01:36:07.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:36:07.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:36:07.27#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.01:36:07.27#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:07.27#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:36:07.39#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:36:07.39#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:36:07.39#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:36:07.39#ibcon#first serial, iclass 38, count 0 2006.286.01:36:07.39#ibcon#enter sib2, iclass 38, count 0 2006.286.01:36:07.39#ibcon#flushed, iclass 38, count 0 2006.286.01:36:07.39#ibcon#about to write, iclass 38, count 0 2006.286.01:36:07.39#ibcon#wrote, iclass 38, count 0 2006.286.01:36:07.39#ibcon#about to read 3, iclass 38, count 0 2006.286.01:36:07.41#ibcon#read 3, iclass 38, count 0 2006.286.01:36:07.41#ibcon#about to read 4, iclass 38, count 0 2006.286.01:36:07.41#ibcon#read 4, iclass 38, count 0 2006.286.01:36:07.41#ibcon#about to read 5, iclass 38, count 0 2006.286.01:36:07.41#ibcon#read 5, iclass 38, count 0 2006.286.01:36:07.41#ibcon#about to read 6, iclass 38, count 0 2006.286.01:36:07.41#ibcon#read 6, iclass 38, count 0 2006.286.01:36:07.41#ibcon#end of sib2, iclass 38, count 0 2006.286.01:36:07.41#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:36:07.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:36:07.41#ibcon#[25=USB\r\n] 2006.286.01:36:07.41#ibcon#*before write, iclass 38, count 0 2006.286.01:36:07.41#ibcon#enter sib2, iclass 38, count 0 2006.286.01:36:07.41#ibcon#flushed, iclass 38, count 0 2006.286.01:36:07.41#ibcon#about to write, iclass 38, count 0 2006.286.01:36:07.41#ibcon#wrote, iclass 38, count 0 2006.286.01:36:07.41#ibcon#about to read 3, iclass 38, count 0 2006.286.01:36:07.44#ibcon#read 3, iclass 38, count 0 2006.286.01:36:07.44#ibcon#about to read 4, iclass 38, count 0 2006.286.01:36:07.44#ibcon#read 4, iclass 38, count 0 2006.286.01:36:07.44#ibcon#about to read 5, iclass 38, count 0 2006.286.01:36:07.44#ibcon#read 5, iclass 38, count 0 2006.286.01:36:07.44#ibcon#about to read 6, iclass 38, count 0 2006.286.01:36:07.44#ibcon#read 6, iclass 38, count 0 2006.286.01:36:07.44#ibcon#end of sib2, iclass 38, count 0 2006.286.01:36:07.44#ibcon#*after write, iclass 38, count 0 2006.286.01:36:07.44#ibcon#*before return 0, iclass 38, count 0 2006.286.01:36:07.44#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:36:07.44#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:36:07.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:36:07.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:36:07.44$vck44/valo=3,564.99 2006.286.01:36:07.44#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.01:36:07.44#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.01:36:07.44#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:07.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:36:07.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:36:07.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:36:07.44#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:36:07.44#ibcon#first serial, iclass 40, count 0 2006.286.01:36:07.44#ibcon#enter sib2, iclass 40, count 0 2006.286.01:36:07.44#ibcon#flushed, iclass 40, count 0 2006.286.01:36:07.44#ibcon#about to write, iclass 40, count 0 2006.286.01:36:07.44#ibcon#wrote, iclass 40, count 0 2006.286.01:36:07.44#ibcon#about to read 3, iclass 40, count 0 2006.286.01:36:07.46#ibcon#read 3, iclass 40, count 0 2006.286.01:36:07.46#ibcon#about to read 4, iclass 40, count 0 2006.286.01:36:07.46#ibcon#read 4, iclass 40, count 0 2006.286.01:36:07.46#ibcon#about to read 5, iclass 40, count 0 2006.286.01:36:07.46#ibcon#read 5, iclass 40, count 0 2006.286.01:36:07.46#ibcon#about to read 6, iclass 40, count 0 2006.286.01:36:07.46#ibcon#read 6, iclass 40, count 0 2006.286.01:36:07.46#ibcon#end of sib2, iclass 40, count 0 2006.286.01:36:07.46#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:36:07.46#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:36:07.46#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:36:07.46#ibcon#*before write, iclass 40, count 0 2006.286.01:36:07.46#ibcon#enter sib2, iclass 40, count 0 2006.286.01:36:07.46#ibcon#flushed, iclass 40, count 0 2006.286.01:36:07.46#ibcon#about to write, iclass 40, count 0 2006.286.01:36:07.46#ibcon#wrote, iclass 40, count 0 2006.286.01:36:07.46#ibcon#about to read 3, iclass 40, count 0 2006.286.01:36:07.50#ibcon#read 3, iclass 40, count 0 2006.286.01:36:07.50#ibcon#about to read 4, iclass 40, count 0 2006.286.01:36:07.50#ibcon#read 4, iclass 40, count 0 2006.286.01:36:07.50#ibcon#about to read 5, iclass 40, count 0 2006.286.01:36:07.50#ibcon#read 5, iclass 40, count 0 2006.286.01:36:07.50#ibcon#about to read 6, iclass 40, count 0 2006.286.01:36:07.50#ibcon#read 6, iclass 40, count 0 2006.286.01:36:07.50#ibcon#end of sib2, iclass 40, count 0 2006.286.01:36:07.50#ibcon#*after write, iclass 40, count 0 2006.286.01:36:07.50#ibcon#*before return 0, iclass 40, count 0 2006.286.01:36:07.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:36:07.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:36:07.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:36:07.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:36:07.50$vck44/va=3,7 2006.286.01:36:07.50#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.01:36:07.50#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.01:36:07.50#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:07.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:36:07.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:36:07.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:36:07.56#ibcon#enter wrdev, iclass 4, count 2 2006.286.01:36:07.56#ibcon#first serial, iclass 4, count 2 2006.286.01:36:07.56#ibcon#enter sib2, iclass 4, count 2 2006.286.01:36:07.56#ibcon#flushed, iclass 4, count 2 2006.286.01:36:07.56#ibcon#about to write, iclass 4, count 2 2006.286.01:36:07.56#ibcon#wrote, iclass 4, count 2 2006.286.01:36:07.56#ibcon#about to read 3, iclass 4, count 2 2006.286.01:36:07.58#ibcon#read 3, iclass 4, count 2 2006.286.01:36:07.58#ibcon#about to read 4, iclass 4, count 2 2006.286.01:36:07.58#ibcon#read 4, iclass 4, count 2 2006.286.01:36:07.58#ibcon#about to read 5, iclass 4, count 2 2006.286.01:36:07.58#ibcon#read 5, iclass 4, count 2 2006.286.01:36:07.58#ibcon#about to read 6, iclass 4, count 2 2006.286.01:36:07.58#ibcon#read 6, iclass 4, count 2 2006.286.01:36:07.58#ibcon#end of sib2, iclass 4, count 2 2006.286.01:36:07.58#ibcon#*mode == 0, iclass 4, count 2 2006.286.01:36:07.58#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.01:36:07.58#ibcon#[25=AT03-07\r\n] 2006.286.01:36:07.58#ibcon#*before write, iclass 4, count 2 2006.286.01:36:07.58#ibcon#enter sib2, iclass 4, count 2 2006.286.01:36:07.58#ibcon#flushed, iclass 4, count 2 2006.286.01:36:07.58#ibcon#about to write, iclass 4, count 2 2006.286.01:36:07.58#ibcon#wrote, iclass 4, count 2 2006.286.01:36:07.58#ibcon#about to read 3, iclass 4, count 2 2006.286.01:36:07.61#ibcon#read 3, iclass 4, count 2 2006.286.01:36:07.61#ibcon#about to read 4, iclass 4, count 2 2006.286.01:36:07.61#ibcon#read 4, iclass 4, count 2 2006.286.01:36:07.61#ibcon#about to read 5, iclass 4, count 2 2006.286.01:36:07.61#ibcon#read 5, iclass 4, count 2 2006.286.01:36:07.61#ibcon#about to read 6, iclass 4, count 2 2006.286.01:36:07.61#ibcon#read 6, iclass 4, count 2 2006.286.01:36:07.61#ibcon#end of sib2, iclass 4, count 2 2006.286.01:36:07.61#ibcon#*after write, iclass 4, count 2 2006.286.01:36:07.61#ibcon#*before return 0, iclass 4, count 2 2006.286.01:36:07.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:36:07.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:36:07.61#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.01:36:07.61#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:07.61#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:36:07.73#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:36:07.73#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:36:07.73#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:36:07.73#ibcon#first serial, iclass 4, count 0 2006.286.01:36:07.73#ibcon#enter sib2, iclass 4, count 0 2006.286.01:36:07.73#ibcon#flushed, iclass 4, count 0 2006.286.01:36:07.73#ibcon#about to write, iclass 4, count 0 2006.286.01:36:07.73#ibcon#wrote, iclass 4, count 0 2006.286.01:36:07.73#ibcon#about to read 3, iclass 4, count 0 2006.286.01:36:07.75#ibcon#read 3, iclass 4, count 0 2006.286.01:36:07.75#ibcon#about to read 4, iclass 4, count 0 2006.286.01:36:07.75#ibcon#read 4, iclass 4, count 0 2006.286.01:36:07.75#ibcon#about to read 5, iclass 4, count 0 2006.286.01:36:07.75#ibcon#read 5, iclass 4, count 0 2006.286.01:36:07.75#ibcon#about to read 6, iclass 4, count 0 2006.286.01:36:07.75#ibcon#read 6, iclass 4, count 0 2006.286.01:36:07.75#ibcon#end of sib2, iclass 4, count 0 2006.286.01:36:07.75#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:36:07.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:36:07.75#ibcon#[25=USB\r\n] 2006.286.01:36:07.75#ibcon#*before write, iclass 4, count 0 2006.286.01:36:07.75#ibcon#enter sib2, iclass 4, count 0 2006.286.01:36:07.75#ibcon#flushed, iclass 4, count 0 2006.286.01:36:07.75#ibcon#about to write, iclass 4, count 0 2006.286.01:36:07.75#ibcon#wrote, iclass 4, count 0 2006.286.01:36:07.75#ibcon#about to read 3, iclass 4, count 0 2006.286.01:36:07.78#ibcon#read 3, iclass 4, count 0 2006.286.01:36:07.78#ibcon#about to read 4, iclass 4, count 0 2006.286.01:36:07.78#ibcon#read 4, iclass 4, count 0 2006.286.01:36:07.78#ibcon#about to read 5, iclass 4, count 0 2006.286.01:36:07.78#ibcon#read 5, iclass 4, count 0 2006.286.01:36:07.78#ibcon#about to read 6, iclass 4, count 0 2006.286.01:36:07.78#ibcon#read 6, iclass 4, count 0 2006.286.01:36:07.78#ibcon#end of sib2, iclass 4, count 0 2006.286.01:36:07.78#ibcon#*after write, iclass 4, count 0 2006.286.01:36:07.78#ibcon#*before return 0, iclass 4, count 0 2006.286.01:36:07.78#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:36:07.78#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:36:07.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:36:07.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:36:07.78$vck44/valo=4,624.99 2006.286.01:36:07.78#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.01:36:07.78#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.01:36:07.78#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:07.78#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:36:07.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:36:07.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:36:07.78#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:36:07.78#ibcon#first serial, iclass 6, count 0 2006.286.01:36:07.78#ibcon#enter sib2, iclass 6, count 0 2006.286.01:36:07.78#ibcon#flushed, iclass 6, count 0 2006.286.01:36:07.78#ibcon#about to write, iclass 6, count 0 2006.286.01:36:07.78#ibcon#wrote, iclass 6, count 0 2006.286.01:36:07.78#ibcon#about to read 3, iclass 6, count 0 2006.286.01:36:07.80#ibcon#read 3, iclass 6, count 0 2006.286.01:36:07.80#ibcon#about to read 4, iclass 6, count 0 2006.286.01:36:07.80#ibcon#read 4, iclass 6, count 0 2006.286.01:36:07.80#ibcon#about to read 5, iclass 6, count 0 2006.286.01:36:07.80#ibcon#read 5, iclass 6, count 0 2006.286.01:36:07.80#ibcon#about to read 6, iclass 6, count 0 2006.286.01:36:07.80#ibcon#read 6, iclass 6, count 0 2006.286.01:36:07.80#ibcon#end of sib2, iclass 6, count 0 2006.286.01:36:07.80#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:36:07.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:36:07.80#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:36:07.80#ibcon#*before write, iclass 6, count 0 2006.286.01:36:07.80#ibcon#enter sib2, iclass 6, count 0 2006.286.01:36:07.80#ibcon#flushed, iclass 6, count 0 2006.286.01:36:07.80#ibcon#about to write, iclass 6, count 0 2006.286.01:36:07.80#ibcon#wrote, iclass 6, count 0 2006.286.01:36:07.80#ibcon#about to read 3, iclass 6, count 0 2006.286.01:36:07.84#ibcon#read 3, iclass 6, count 0 2006.286.01:36:07.84#ibcon#about to read 4, iclass 6, count 0 2006.286.01:36:07.84#ibcon#read 4, iclass 6, count 0 2006.286.01:36:07.84#ibcon#about to read 5, iclass 6, count 0 2006.286.01:36:07.84#ibcon#read 5, iclass 6, count 0 2006.286.01:36:07.84#ibcon#about to read 6, iclass 6, count 0 2006.286.01:36:07.84#ibcon#read 6, iclass 6, count 0 2006.286.01:36:07.84#ibcon#end of sib2, iclass 6, count 0 2006.286.01:36:07.84#ibcon#*after write, iclass 6, count 0 2006.286.01:36:07.84#ibcon#*before return 0, iclass 6, count 0 2006.286.01:36:07.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:36:07.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:36:07.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:36:07.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:36:07.84$vck44/va=4,6 2006.286.01:36:07.84#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.01:36:07.84#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.01:36:07.84#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:07.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:36:07.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:36:07.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:36:07.90#ibcon#enter wrdev, iclass 10, count 2 2006.286.01:36:07.90#ibcon#first serial, iclass 10, count 2 2006.286.01:36:07.90#ibcon#enter sib2, iclass 10, count 2 2006.286.01:36:07.90#ibcon#flushed, iclass 10, count 2 2006.286.01:36:07.90#ibcon#about to write, iclass 10, count 2 2006.286.01:36:07.90#ibcon#wrote, iclass 10, count 2 2006.286.01:36:07.90#ibcon#about to read 3, iclass 10, count 2 2006.286.01:36:07.92#ibcon#read 3, iclass 10, count 2 2006.286.01:36:07.92#ibcon#about to read 4, iclass 10, count 2 2006.286.01:36:07.92#ibcon#read 4, iclass 10, count 2 2006.286.01:36:07.92#ibcon#about to read 5, iclass 10, count 2 2006.286.01:36:07.92#ibcon#read 5, iclass 10, count 2 2006.286.01:36:07.92#ibcon#about to read 6, iclass 10, count 2 2006.286.01:36:07.92#ibcon#read 6, iclass 10, count 2 2006.286.01:36:07.92#ibcon#end of sib2, iclass 10, count 2 2006.286.01:36:07.92#ibcon#*mode == 0, iclass 10, count 2 2006.286.01:36:07.92#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.01:36:07.92#ibcon#[25=AT04-06\r\n] 2006.286.01:36:07.92#ibcon#*before write, iclass 10, count 2 2006.286.01:36:07.92#ibcon#enter sib2, iclass 10, count 2 2006.286.01:36:07.92#ibcon#flushed, iclass 10, count 2 2006.286.01:36:07.92#ibcon#about to write, iclass 10, count 2 2006.286.01:36:07.92#ibcon#wrote, iclass 10, count 2 2006.286.01:36:07.92#ibcon#about to read 3, iclass 10, count 2 2006.286.01:36:07.95#ibcon#read 3, iclass 10, count 2 2006.286.01:36:07.95#ibcon#about to read 4, iclass 10, count 2 2006.286.01:36:07.95#ibcon#read 4, iclass 10, count 2 2006.286.01:36:07.95#ibcon#about to read 5, iclass 10, count 2 2006.286.01:36:07.95#ibcon#read 5, iclass 10, count 2 2006.286.01:36:07.95#ibcon#about to read 6, iclass 10, count 2 2006.286.01:36:07.95#ibcon#read 6, iclass 10, count 2 2006.286.01:36:07.95#ibcon#end of sib2, iclass 10, count 2 2006.286.01:36:07.95#ibcon#*after write, iclass 10, count 2 2006.286.01:36:07.95#ibcon#*before return 0, iclass 10, count 2 2006.286.01:36:07.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:36:07.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:36:07.95#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.01:36:07.95#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:07.95#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:36:08.07#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:36:08.07#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:36:08.07#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:36:08.07#ibcon#first serial, iclass 10, count 0 2006.286.01:36:08.07#ibcon#enter sib2, iclass 10, count 0 2006.286.01:36:08.07#ibcon#flushed, iclass 10, count 0 2006.286.01:36:08.07#ibcon#about to write, iclass 10, count 0 2006.286.01:36:08.07#ibcon#wrote, iclass 10, count 0 2006.286.01:36:08.07#ibcon#about to read 3, iclass 10, count 0 2006.286.01:36:08.09#ibcon#read 3, iclass 10, count 0 2006.286.01:36:08.09#ibcon#about to read 4, iclass 10, count 0 2006.286.01:36:08.09#ibcon#read 4, iclass 10, count 0 2006.286.01:36:08.09#ibcon#about to read 5, iclass 10, count 0 2006.286.01:36:08.09#ibcon#read 5, iclass 10, count 0 2006.286.01:36:08.09#ibcon#about to read 6, iclass 10, count 0 2006.286.01:36:08.09#ibcon#read 6, iclass 10, count 0 2006.286.01:36:08.09#ibcon#end of sib2, iclass 10, count 0 2006.286.01:36:08.09#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:36:08.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:36:08.09#ibcon#[25=USB\r\n] 2006.286.01:36:08.09#ibcon#*before write, iclass 10, count 0 2006.286.01:36:08.09#ibcon#enter sib2, iclass 10, count 0 2006.286.01:36:08.09#ibcon#flushed, iclass 10, count 0 2006.286.01:36:08.09#ibcon#about to write, iclass 10, count 0 2006.286.01:36:08.09#ibcon#wrote, iclass 10, count 0 2006.286.01:36:08.09#ibcon#about to read 3, iclass 10, count 0 2006.286.01:36:08.12#ibcon#read 3, iclass 10, count 0 2006.286.01:36:08.12#ibcon#about to read 4, iclass 10, count 0 2006.286.01:36:08.12#ibcon#read 4, iclass 10, count 0 2006.286.01:36:08.12#ibcon#about to read 5, iclass 10, count 0 2006.286.01:36:08.12#ibcon#read 5, iclass 10, count 0 2006.286.01:36:08.12#ibcon#about to read 6, iclass 10, count 0 2006.286.01:36:08.12#ibcon#read 6, iclass 10, count 0 2006.286.01:36:08.12#ibcon#end of sib2, iclass 10, count 0 2006.286.01:36:08.12#ibcon#*after write, iclass 10, count 0 2006.286.01:36:08.12#ibcon#*before return 0, iclass 10, count 0 2006.286.01:36:08.12#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:36:08.12#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:36:08.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:36:08.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:36:08.12$vck44/valo=5,734.99 2006.286.01:36:08.12#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.01:36:08.12#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.01:36:08.12#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:08.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:36:08.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:36:08.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:36:08.12#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:36:08.12#ibcon#first serial, iclass 12, count 0 2006.286.01:36:08.12#ibcon#enter sib2, iclass 12, count 0 2006.286.01:36:08.12#ibcon#flushed, iclass 12, count 0 2006.286.01:36:08.12#ibcon#about to write, iclass 12, count 0 2006.286.01:36:08.12#ibcon#wrote, iclass 12, count 0 2006.286.01:36:08.12#ibcon#about to read 3, iclass 12, count 0 2006.286.01:36:08.14#ibcon#read 3, iclass 12, count 0 2006.286.01:36:08.14#ibcon#about to read 4, iclass 12, count 0 2006.286.01:36:08.14#ibcon#read 4, iclass 12, count 0 2006.286.01:36:08.14#ibcon#about to read 5, iclass 12, count 0 2006.286.01:36:08.14#ibcon#read 5, iclass 12, count 0 2006.286.01:36:08.14#ibcon#about to read 6, iclass 12, count 0 2006.286.01:36:08.14#ibcon#read 6, iclass 12, count 0 2006.286.01:36:08.14#ibcon#end of sib2, iclass 12, count 0 2006.286.01:36:08.14#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:36:08.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:36:08.14#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:36:08.14#ibcon#*before write, iclass 12, count 0 2006.286.01:36:08.14#ibcon#enter sib2, iclass 12, count 0 2006.286.01:36:08.14#ibcon#flushed, iclass 12, count 0 2006.286.01:36:08.14#ibcon#about to write, iclass 12, count 0 2006.286.01:36:08.14#ibcon#wrote, iclass 12, count 0 2006.286.01:36:08.14#ibcon#about to read 3, iclass 12, count 0 2006.286.01:36:08.18#ibcon#read 3, iclass 12, count 0 2006.286.01:36:08.18#ibcon#about to read 4, iclass 12, count 0 2006.286.01:36:08.18#ibcon#read 4, iclass 12, count 0 2006.286.01:36:08.18#ibcon#about to read 5, iclass 12, count 0 2006.286.01:36:08.18#ibcon#read 5, iclass 12, count 0 2006.286.01:36:08.18#ibcon#about to read 6, iclass 12, count 0 2006.286.01:36:08.18#ibcon#read 6, iclass 12, count 0 2006.286.01:36:08.18#ibcon#end of sib2, iclass 12, count 0 2006.286.01:36:08.18#ibcon#*after write, iclass 12, count 0 2006.286.01:36:08.18#ibcon#*before return 0, iclass 12, count 0 2006.286.01:36:08.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:36:08.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:36:08.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:36:08.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:36:08.18$vck44/va=5,3 2006.286.01:36:08.18#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.01:36:08.18#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.01:36:08.18#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:08.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:36:08.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:36:08.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:36:08.24#ibcon#enter wrdev, iclass 14, count 2 2006.286.01:36:08.24#ibcon#first serial, iclass 14, count 2 2006.286.01:36:08.24#ibcon#enter sib2, iclass 14, count 2 2006.286.01:36:08.24#ibcon#flushed, iclass 14, count 2 2006.286.01:36:08.24#ibcon#about to write, iclass 14, count 2 2006.286.01:36:08.24#ibcon#wrote, iclass 14, count 2 2006.286.01:36:08.24#ibcon#about to read 3, iclass 14, count 2 2006.286.01:36:08.26#ibcon#read 3, iclass 14, count 2 2006.286.01:36:08.26#ibcon#about to read 4, iclass 14, count 2 2006.286.01:36:08.26#ibcon#read 4, iclass 14, count 2 2006.286.01:36:08.26#ibcon#about to read 5, iclass 14, count 2 2006.286.01:36:08.26#ibcon#read 5, iclass 14, count 2 2006.286.01:36:08.26#ibcon#about to read 6, iclass 14, count 2 2006.286.01:36:08.26#ibcon#read 6, iclass 14, count 2 2006.286.01:36:08.26#ibcon#end of sib2, iclass 14, count 2 2006.286.01:36:08.26#ibcon#*mode == 0, iclass 14, count 2 2006.286.01:36:08.26#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.01:36:08.26#ibcon#[25=AT05-03\r\n] 2006.286.01:36:08.26#ibcon#*before write, iclass 14, count 2 2006.286.01:36:08.26#ibcon#enter sib2, iclass 14, count 2 2006.286.01:36:08.26#ibcon#flushed, iclass 14, count 2 2006.286.01:36:08.26#ibcon#about to write, iclass 14, count 2 2006.286.01:36:08.26#ibcon#wrote, iclass 14, count 2 2006.286.01:36:08.26#ibcon#about to read 3, iclass 14, count 2 2006.286.01:36:08.29#ibcon#read 3, iclass 14, count 2 2006.286.01:36:08.29#ibcon#about to read 4, iclass 14, count 2 2006.286.01:36:08.29#ibcon#read 4, iclass 14, count 2 2006.286.01:36:08.29#ibcon#about to read 5, iclass 14, count 2 2006.286.01:36:08.29#ibcon#read 5, iclass 14, count 2 2006.286.01:36:08.29#ibcon#about to read 6, iclass 14, count 2 2006.286.01:36:08.29#ibcon#read 6, iclass 14, count 2 2006.286.01:36:08.29#ibcon#end of sib2, iclass 14, count 2 2006.286.01:36:08.29#ibcon#*after write, iclass 14, count 2 2006.286.01:36:08.29#ibcon#*before return 0, iclass 14, count 2 2006.286.01:36:08.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:36:08.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:36:08.29#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.01:36:08.29#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:08.29#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:36:08.41#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:36:08.41#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:36:08.41#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:36:08.41#ibcon#first serial, iclass 14, count 0 2006.286.01:36:08.41#ibcon#enter sib2, iclass 14, count 0 2006.286.01:36:08.41#ibcon#flushed, iclass 14, count 0 2006.286.01:36:08.41#ibcon#about to write, iclass 14, count 0 2006.286.01:36:08.41#ibcon#wrote, iclass 14, count 0 2006.286.01:36:08.41#ibcon#about to read 3, iclass 14, count 0 2006.286.01:36:08.43#ibcon#read 3, iclass 14, count 0 2006.286.01:36:08.43#ibcon#about to read 4, iclass 14, count 0 2006.286.01:36:08.43#ibcon#read 4, iclass 14, count 0 2006.286.01:36:08.43#ibcon#about to read 5, iclass 14, count 0 2006.286.01:36:08.43#ibcon#read 5, iclass 14, count 0 2006.286.01:36:08.43#ibcon#about to read 6, iclass 14, count 0 2006.286.01:36:08.43#ibcon#read 6, iclass 14, count 0 2006.286.01:36:08.43#ibcon#end of sib2, iclass 14, count 0 2006.286.01:36:08.43#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:36:08.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:36:08.43#ibcon#[25=USB\r\n] 2006.286.01:36:08.43#ibcon#*before write, iclass 14, count 0 2006.286.01:36:08.43#ibcon#enter sib2, iclass 14, count 0 2006.286.01:36:08.43#ibcon#flushed, iclass 14, count 0 2006.286.01:36:08.43#ibcon#about to write, iclass 14, count 0 2006.286.01:36:08.43#ibcon#wrote, iclass 14, count 0 2006.286.01:36:08.43#ibcon#about to read 3, iclass 14, count 0 2006.286.01:36:08.46#ibcon#read 3, iclass 14, count 0 2006.286.01:36:08.46#ibcon#about to read 4, iclass 14, count 0 2006.286.01:36:08.46#ibcon#read 4, iclass 14, count 0 2006.286.01:36:08.46#ibcon#about to read 5, iclass 14, count 0 2006.286.01:36:08.46#ibcon#read 5, iclass 14, count 0 2006.286.01:36:08.46#ibcon#about to read 6, iclass 14, count 0 2006.286.01:36:08.46#ibcon#read 6, iclass 14, count 0 2006.286.01:36:08.46#ibcon#end of sib2, iclass 14, count 0 2006.286.01:36:08.46#ibcon#*after write, iclass 14, count 0 2006.286.01:36:08.46#ibcon#*before return 0, iclass 14, count 0 2006.286.01:36:08.46#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:36:08.46#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:36:08.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:36:08.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:36:08.46$vck44/valo=6,814.99 2006.286.01:36:08.46#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.01:36:08.46#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.01:36:08.46#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:08.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:36:08.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:36:08.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:36:08.46#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:36:08.46#ibcon#first serial, iclass 16, count 0 2006.286.01:36:08.46#ibcon#enter sib2, iclass 16, count 0 2006.286.01:36:08.46#ibcon#flushed, iclass 16, count 0 2006.286.01:36:08.46#ibcon#about to write, iclass 16, count 0 2006.286.01:36:08.46#ibcon#wrote, iclass 16, count 0 2006.286.01:36:08.46#ibcon#about to read 3, iclass 16, count 0 2006.286.01:36:08.48#ibcon#read 3, iclass 16, count 0 2006.286.01:36:08.48#ibcon#about to read 4, iclass 16, count 0 2006.286.01:36:08.48#ibcon#read 4, iclass 16, count 0 2006.286.01:36:08.48#ibcon#about to read 5, iclass 16, count 0 2006.286.01:36:08.48#ibcon#read 5, iclass 16, count 0 2006.286.01:36:08.48#ibcon#about to read 6, iclass 16, count 0 2006.286.01:36:08.48#ibcon#read 6, iclass 16, count 0 2006.286.01:36:08.48#ibcon#end of sib2, iclass 16, count 0 2006.286.01:36:08.48#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:36:08.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:36:08.48#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:36:08.48#ibcon#*before write, iclass 16, count 0 2006.286.01:36:08.48#ibcon#enter sib2, iclass 16, count 0 2006.286.01:36:08.48#ibcon#flushed, iclass 16, count 0 2006.286.01:36:08.48#ibcon#about to write, iclass 16, count 0 2006.286.01:36:08.48#ibcon#wrote, iclass 16, count 0 2006.286.01:36:08.48#ibcon#about to read 3, iclass 16, count 0 2006.286.01:36:08.52#ibcon#read 3, iclass 16, count 0 2006.286.01:36:08.52#ibcon#about to read 4, iclass 16, count 0 2006.286.01:36:08.52#ibcon#read 4, iclass 16, count 0 2006.286.01:36:08.52#ibcon#about to read 5, iclass 16, count 0 2006.286.01:36:08.52#ibcon#read 5, iclass 16, count 0 2006.286.01:36:08.52#ibcon#about to read 6, iclass 16, count 0 2006.286.01:36:08.52#ibcon#read 6, iclass 16, count 0 2006.286.01:36:08.52#ibcon#end of sib2, iclass 16, count 0 2006.286.01:36:08.52#ibcon#*after write, iclass 16, count 0 2006.286.01:36:08.52#ibcon#*before return 0, iclass 16, count 0 2006.286.01:36:08.52#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:36:08.52#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:36:08.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:36:08.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:36:08.52$vck44/va=6,4 2006.286.01:36:08.52#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.01:36:08.52#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.01:36:08.52#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:08.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:36:08.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:36:08.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:36:08.58#ibcon#enter wrdev, iclass 18, count 2 2006.286.01:36:08.58#ibcon#first serial, iclass 18, count 2 2006.286.01:36:08.58#ibcon#enter sib2, iclass 18, count 2 2006.286.01:36:08.58#ibcon#flushed, iclass 18, count 2 2006.286.01:36:08.58#ibcon#about to write, iclass 18, count 2 2006.286.01:36:08.58#ibcon#wrote, iclass 18, count 2 2006.286.01:36:08.58#ibcon#about to read 3, iclass 18, count 2 2006.286.01:36:08.60#ibcon#read 3, iclass 18, count 2 2006.286.01:36:08.60#ibcon#about to read 4, iclass 18, count 2 2006.286.01:36:08.60#ibcon#read 4, iclass 18, count 2 2006.286.01:36:08.60#ibcon#about to read 5, iclass 18, count 2 2006.286.01:36:08.60#ibcon#read 5, iclass 18, count 2 2006.286.01:36:08.60#ibcon#about to read 6, iclass 18, count 2 2006.286.01:36:08.60#ibcon#read 6, iclass 18, count 2 2006.286.01:36:08.60#ibcon#end of sib2, iclass 18, count 2 2006.286.01:36:08.60#ibcon#*mode == 0, iclass 18, count 2 2006.286.01:36:08.60#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.01:36:08.60#ibcon#[25=AT06-04\r\n] 2006.286.01:36:08.60#ibcon#*before write, iclass 18, count 2 2006.286.01:36:08.60#ibcon#enter sib2, iclass 18, count 2 2006.286.01:36:08.60#ibcon#flushed, iclass 18, count 2 2006.286.01:36:08.60#ibcon#about to write, iclass 18, count 2 2006.286.01:36:08.60#ibcon#wrote, iclass 18, count 2 2006.286.01:36:08.60#ibcon#about to read 3, iclass 18, count 2 2006.286.01:36:08.63#ibcon#read 3, iclass 18, count 2 2006.286.01:36:08.63#ibcon#about to read 4, iclass 18, count 2 2006.286.01:36:08.63#ibcon#read 4, iclass 18, count 2 2006.286.01:36:08.63#ibcon#about to read 5, iclass 18, count 2 2006.286.01:36:08.63#ibcon#read 5, iclass 18, count 2 2006.286.01:36:08.63#ibcon#about to read 6, iclass 18, count 2 2006.286.01:36:08.63#ibcon#read 6, iclass 18, count 2 2006.286.01:36:08.63#ibcon#end of sib2, iclass 18, count 2 2006.286.01:36:08.63#ibcon#*after write, iclass 18, count 2 2006.286.01:36:08.63#ibcon#*before return 0, iclass 18, count 2 2006.286.01:36:08.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:36:08.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:36:08.63#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.01:36:08.63#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:08.63#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:36:08.75#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:36:08.75#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:36:08.75#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:36:08.75#ibcon#first serial, iclass 18, count 0 2006.286.01:36:08.75#ibcon#enter sib2, iclass 18, count 0 2006.286.01:36:08.75#ibcon#flushed, iclass 18, count 0 2006.286.01:36:08.75#ibcon#about to write, iclass 18, count 0 2006.286.01:36:08.75#ibcon#wrote, iclass 18, count 0 2006.286.01:36:08.75#ibcon#about to read 3, iclass 18, count 0 2006.286.01:36:08.77#ibcon#read 3, iclass 18, count 0 2006.286.01:36:08.77#ibcon#about to read 4, iclass 18, count 0 2006.286.01:36:08.77#ibcon#read 4, iclass 18, count 0 2006.286.01:36:08.77#ibcon#about to read 5, iclass 18, count 0 2006.286.01:36:08.77#ibcon#read 5, iclass 18, count 0 2006.286.01:36:08.77#ibcon#about to read 6, iclass 18, count 0 2006.286.01:36:08.77#ibcon#read 6, iclass 18, count 0 2006.286.01:36:08.77#ibcon#end of sib2, iclass 18, count 0 2006.286.01:36:08.77#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:36:08.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:36:08.77#ibcon#[25=USB\r\n] 2006.286.01:36:08.77#ibcon#*before write, iclass 18, count 0 2006.286.01:36:08.77#ibcon#enter sib2, iclass 18, count 0 2006.286.01:36:08.77#ibcon#flushed, iclass 18, count 0 2006.286.01:36:08.77#ibcon#about to write, iclass 18, count 0 2006.286.01:36:08.77#ibcon#wrote, iclass 18, count 0 2006.286.01:36:08.77#ibcon#about to read 3, iclass 18, count 0 2006.286.01:36:08.80#ibcon#read 3, iclass 18, count 0 2006.286.01:36:08.80#ibcon#about to read 4, iclass 18, count 0 2006.286.01:36:08.80#ibcon#read 4, iclass 18, count 0 2006.286.01:36:08.80#ibcon#about to read 5, iclass 18, count 0 2006.286.01:36:08.80#ibcon#read 5, iclass 18, count 0 2006.286.01:36:08.80#ibcon#about to read 6, iclass 18, count 0 2006.286.01:36:08.80#ibcon#read 6, iclass 18, count 0 2006.286.01:36:08.80#ibcon#end of sib2, iclass 18, count 0 2006.286.01:36:08.80#ibcon#*after write, iclass 18, count 0 2006.286.01:36:08.80#ibcon#*before return 0, iclass 18, count 0 2006.286.01:36:08.80#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:36:08.80#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:36:08.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:36:08.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:36:08.80$vck44/valo=7,864.99 2006.286.01:36:08.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.01:36:08.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.01:36:08.80#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:08.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:36:08.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:36:08.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:36:08.80#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:36:08.80#ibcon#first serial, iclass 20, count 0 2006.286.01:36:08.80#ibcon#enter sib2, iclass 20, count 0 2006.286.01:36:08.80#ibcon#flushed, iclass 20, count 0 2006.286.01:36:08.80#ibcon#about to write, iclass 20, count 0 2006.286.01:36:08.80#ibcon#wrote, iclass 20, count 0 2006.286.01:36:08.80#ibcon#about to read 3, iclass 20, count 0 2006.286.01:36:08.82#ibcon#read 3, iclass 20, count 0 2006.286.01:36:08.82#ibcon#about to read 4, iclass 20, count 0 2006.286.01:36:08.82#ibcon#read 4, iclass 20, count 0 2006.286.01:36:08.82#ibcon#about to read 5, iclass 20, count 0 2006.286.01:36:08.82#ibcon#read 5, iclass 20, count 0 2006.286.01:36:08.82#ibcon#about to read 6, iclass 20, count 0 2006.286.01:36:08.82#ibcon#read 6, iclass 20, count 0 2006.286.01:36:08.82#ibcon#end of sib2, iclass 20, count 0 2006.286.01:36:08.82#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:36:08.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:36:08.82#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:36:08.82#ibcon#*before write, iclass 20, count 0 2006.286.01:36:08.82#ibcon#enter sib2, iclass 20, count 0 2006.286.01:36:08.82#ibcon#flushed, iclass 20, count 0 2006.286.01:36:08.82#ibcon#about to write, iclass 20, count 0 2006.286.01:36:08.82#ibcon#wrote, iclass 20, count 0 2006.286.01:36:08.82#ibcon#about to read 3, iclass 20, count 0 2006.286.01:36:08.86#ibcon#read 3, iclass 20, count 0 2006.286.01:36:08.86#ibcon#about to read 4, iclass 20, count 0 2006.286.01:36:08.86#ibcon#read 4, iclass 20, count 0 2006.286.01:36:08.86#ibcon#about to read 5, iclass 20, count 0 2006.286.01:36:08.86#ibcon#read 5, iclass 20, count 0 2006.286.01:36:08.86#ibcon#about to read 6, iclass 20, count 0 2006.286.01:36:08.86#ibcon#read 6, iclass 20, count 0 2006.286.01:36:08.86#ibcon#end of sib2, iclass 20, count 0 2006.286.01:36:08.86#ibcon#*after write, iclass 20, count 0 2006.286.01:36:08.86#ibcon#*before return 0, iclass 20, count 0 2006.286.01:36:08.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:36:08.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:36:08.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:36:08.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:36:08.86$vck44/va=7,4 2006.286.01:36:08.86#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.01:36:08.86#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.01:36:08.86#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:08.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:36:08.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:36:08.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:36:08.92#ibcon#enter wrdev, iclass 22, count 2 2006.286.01:36:08.92#ibcon#first serial, iclass 22, count 2 2006.286.01:36:08.92#ibcon#enter sib2, iclass 22, count 2 2006.286.01:36:08.92#ibcon#flushed, iclass 22, count 2 2006.286.01:36:08.92#ibcon#about to write, iclass 22, count 2 2006.286.01:36:08.92#ibcon#wrote, iclass 22, count 2 2006.286.01:36:08.92#ibcon#about to read 3, iclass 22, count 2 2006.286.01:36:08.94#ibcon#read 3, iclass 22, count 2 2006.286.01:36:08.94#ibcon#about to read 4, iclass 22, count 2 2006.286.01:36:08.94#ibcon#read 4, iclass 22, count 2 2006.286.01:36:08.94#ibcon#about to read 5, iclass 22, count 2 2006.286.01:36:08.94#ibcon#read 5, iclass 22, count 2 2006.286.01:36:08.94#ibcon#about to read 6, iclass 22, count 2 2006.286.01:36:08.94#ibcon#read 6, iclass 22, count 2 2006.286.01:36:08.94#ibcon#end of sib2, iclass 22, count 2 2006.286.01:36:08.94#ibcon#*mode == 0, iclass 22, count 2 2006.286.01:36:08.94#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.01:36:08.94#ibcon#[25=AT07-04\r\n] 2006.286.01:36:08.94#ibcon#*before write, iclass 22, count 2 2006.286.01:36:08.94#ibcon#enter sib2, iclass 22, count 2 2006.286.01:36:08.94#ibcon#flushed, iclass 22, count 2 2006.286.01:36:08.94#ibcon#about to write, iclass 22, count 2 2006.286.01:36:08.94#ibcon#wrote, iclass 22, count 2 2006.286.01:36:08.94#ibcon#about to read 3, iclass 22, count 2 2006.286.01:36:08.97#ibcon#read 3, iclass 22, count 2 2006.286.01:36:08.97#ibcon#about to read 4, iclass 22, count 2 2006.286.01:36:08.97#ibcon#read 4, iclass 22, count 2 2006.286.01:36:08.97#ibcon#about to read 5, iclass 22, count 2 2006.286.01:36:08.97#ibcon#read 5, iclass 22, count 2 2006.286.01:36:08.97#ibcon#about to read 6, iclass 22, count 2 2006.286.01:36:08.97#ibcon#read 6, iclass 22, count 2 2006.286.01:36:08.97#ibcon#end of sib2, iclass 22, count 2 2006.286.01:36:08.97#ibcon#*after write, iclass 22, count 2 2006.286.01:36:08.97#ibcon#*before return 0, iclass 22, count 2 2006.286.01:36:08.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:36:08.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:36:08.97#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.01:36:08.97#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:08.97#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:36:09.09#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:36:09.09#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:36:09.09#ibcon#enter wrdev, iclass 22, count 0 2006.286.01:36:09.09#ibcon#first serial, iclass 22, count 0 2006.286.01:36:09.09#ibcon#enter sib2, iclass 22, count 0 2006.286.01:36:09.09#ibcon#flushed, iclass 22, count 0 2006.286.01:36:09.09#ibcon#about to write, iclass 22, count 0 2006.286.01:36:09.09#ibcon#wrote, iclass 22, count 0 2006.286.01:36:09.09#ibcon#about to read 3, iclass 22, count 0 2006.286.01:36:09.11#ibcon#read 3, iclass 22, count 0 2006.286.01:36:09.11#ibcon#about to read 4, iclass 22, count 0 2006.286.01:36:09.11#ibcon#read 4, iclass 22, count 0 2006.286.01:36:09.11#ibcon#about to read 5, iclass 22, count 0 2006.286.01:36:09.11#ibcon#read 5, iclass 22, count 0 2006.286.01:36:09.11#ibcon#about to read 6, iclass 22, count 0 2006.286.01:36:09.11#ibcon#read 6, iclass 22, count 0 2006.286.01:36:09.11#ibcon#end of sib2, iclass 22, count 0 2006.286.01:36:09.11#ibcon#*mode == 0, iclass 22, count 0 2006.286.01:36:09.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.01:36:09.11#ibcon#[25=USB\r\n] 2006.286.01:36:09.11#ibcon#*before write, iclass 22, count 0 2006.286.01:36:09.11#ibcon#enter sib2, iclass 22, count 0 2006.286.01:36:09.11#ibcon#flushed, iclass 22, count 0 2006.286.01:36:09.11#ibcon#about to write, iclass 22, count 0 2006.286.01:36:09.11#ibcon#wrote, iclass 22, count 0 2006.286.01:36:09.11#ibcon#about to read 3, iclass 22, count 0 2006.286.01:36:09.14#ibcon#read 3, iclass 22, count 0 2006.286.01:36:09.14#ibcon#about to read 4, iclass 22, count 0 2006.286.01:36:09.14#ibcon#read 4, iclass 22, count 0 2006.286.01:36:09.14#ibcon#about to read 5, iclass 22, count 0 2006.286.01:36:09.14#ibcon#read 5, iclass 22, count 0 2006.286.01:36:09.14#ibcon#about to read 6, iclass 22, count 0 2006.286.01:36:09.14#ibcon#read 6, iclass 22, count 0 2006.286.01:36:09.14#ibcon#end of sib2, iclass 22, count 0 2006.286.01:36:09.14#ibcon#*after write, iclass 22, count 0 2006.286.01:36:09.14#ibcon#*before return 0, iclass 22, count 0 2006.286.01:36:09.14#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:36:09.14#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:36:09.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.01:36:09.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.01:36:09.14$vck44/valo=8,884.99 2006.286.01:36:09.14#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.01:36:09.14#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.01:36:09.14#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:09.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:36:09.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:36:09.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:36:09.14#ibcon#enter wrdev, iclass 24, count 0 2006.286.01:36:09.14#ibcon#first serial, iclass 24, count 0 2006.286.01:36:09.14#ibcon#enter sib2, iclass 24, count 0 2006.286.01:36:09.14#ibcon#flushed, iclass 24, count 0 2006.286.01:36:09.14#ibcon#about to write, iclass 24, count 0 2006.286.01:36:09.14#ibcon#wrote, iclass 24, count 0 2006.286.01:36:09.14#ibcon#about to read 3, iclass 24, count 0 2006.286.01:36:09.16#ibcon#read 3, iclass 24, count 0 2006.286.01:36:09.16#ibcon#about to read 4, iclass 24, count 0 2006.286.01:36:09.16#ibcon#read 4, iclass 24, count 0 2006.286.01:36:09.16#ibcon#about to read 5, iclass 24, count 0 2006.286.01:36:09.16#ibcon#read 5, iclass 24, count 0 2006.286.01:36:09.16#ibcon#about to read 6, iclass 24, count 0 2006.286.01:36:09.16#ibcon#read 6, iclass 24, count 0 2006.286.01:36:09.16#ibcon#end of sib2, iclass 24, count 0 2006.286.01:36:09.16#ibcon#*mode == 0, iclass 24, count 0 2006.286.01:36:09.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.01:36:09.16#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:36:09.16#ibcon#*before write, iclass 24, count 0 2006.286.01:36:09.16#ibcon#enter sib2, iclass 24, count 0 2006.286.01:36:09.16#ibcon#flushed, iclass 24, count 0 2006.286.01:36:09.16#ibcon#about to write, iclass 24, count 0 2006.286.01:36:09.16#ibcon#wrote, iclass 24, count 0 2006.286.01:36:09.16#ibcon#about to read 3, iclass 24, count 0 2006.286.01:36:09.20#ibcon#read 3, iclass 24, count 0 2006.286.01:36:09.20#ibcon#about to read 4, iclass 24, count 0 2006.286.01:36:09.20#ibcon#read 4, iclass 24, count 0 2006.286.01:36:09.20#ibcon#about to read 5, iclass 24, count 0 2006.286.01:36:09.20#ibcon#read 5, iclass 24, count 0 2006.286.01:36:09.20#ibcon#about to read 6, iclass 24, count 0 2006.286.01:36:09.20#ibcon#read 6, iclass 24, count 0 2006.286.01:36:09.20#ibcon#end of sib2, iclass 24, count 0 2006.286.01:36:09.20#ibcon#*after write, iclass 24, count 0 2006.286.01:36:09.20#ibcon#*before return 0, iclass 24, count 0 2006.286.01:36:09.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:36:09.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:36:09.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.01:36:09.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.01:36:09.20$vck44/va=8,3 2006.286.01:36:09.20#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.01:36:09.20#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.01:36:09.20#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:09.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:36:09.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:36:09.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:36:09.26#ibcon#enter wrdev, iclass 26, count 2 2006.286.01:36:09.26#ibcon#first serial, iclass 26, count 2 2006.286.01:36:09.26#ibcon#enter sib2, iclass 26, count 2 2006.286.01:36:09.26#ibcon#flushed, iclass 26, count 2 2006.286.01:36:09.26#ibcon#about to write, iclass 26, count 2 2006.286.01:36:09.26#ibcon#wrote, iclass 26, count 2 2006.286.01:36:09.26#ibcon#about to read 3, iclass 26, count 2 2006.286.01:36:09.28#ibcon#read 3, iclass 26, count 2 2006.286.01:36:09.28#ibcon#about to read 4, iclass 26, count 2 2006.286.01:36:09.28#ibcon#read 4, iclass 26, count 2 2006.286.01:36:09.28#ibcon#about to read 5, iclass 26, count 2 2006.286.01:36:09.28#ibcon#read 5, iclass 26, count 2 2006.286.01:36:09.28#ibcon#about to read 6, iclass 26, count 2 2006.286.01:36:09.28#ibcon#read 6, iclass 26, count 2 2006.286.01:36:09.28#ibcon#end of sib2, iclass 26, count 2 2006.286.01:36:09.28#ibcon#*mode == 0, iclass 26, count 2 2006.286.01:36:09.28#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.01:36:09.28#ibcon#[25=AT08-03\r\n] 2006.286.01:36:09.28#ibcon#*before write, iclass 26, count 2 2006.286.01:36:09.28#ibcon#enter sib2, iclass 26, count 2 2006.286.01:36:09.28#ibcon#flushed, iclass 26, count 2 2006.286.01:36:09.28#ibcon#about to write, iclass 26, count 2 2006.286.01:36:09.28#ibcon#wrote, iclass 26, count 2 2006.286.01:36:09.28#ibcon#about to read 3, iclass 26, count 2 2006.286.01:36:09.31#ibcon#read 3, iclass 26, count 2 2006.286.01:36:09.31#ibcon#about to read 4, iclass 26, count 2 2006.286.01:36:09.31#ibcon#read 4, iclass 26, count 2 2006.286.01:36:09.31#ibcon#about to read 5, iclass 26, count 2 2006.286.01:36:09.31#ibcon#read 5, iclass 26, count 2 2006.286.01:36:09.31#ibcon#about to read 6, iclass 26, count 2 2006.286.01:36:09.31#ibcon#read 6, iclass 26, count 2 2006.286.01:36:09.31#ibcon#end of sib2, iclass 26, count 2 2006.286.01:36:09.31#ibcon#*after write, iclass 26, count 2 2006.286.01:36:09.31#ibcon#*before return 0, iclass 26, count 2 2006.286.01:36:09.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:36:09.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.01:36:09.31#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.01:36:09.31#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:09.31#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:36:09.43#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:36:09.43#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:36:09.43#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:36:09.43#ibcon#first serial, iclass 26, count 0 2006.286.01:36:09.43#ibcon#enter sib2, iclass 26, count 0 2006.286.01:36:09.43#ibcon#flushed, iclass 26, count 0 2006.286.01:36:09.43#ibcon#about to write, iclass 26, count 0 2006.286.01:36:09.43#ibcon#wrote, iclass 26, count 0 2006.286.01:36:09.43#ibcon#about to read 3, iclass 26, count 0 2006.286.01:36:09.45#ibcon#read 3, iclass 26, count 0 2006.286.01:36:09.45#ibcon#about to read 4, iclass 26, count 0 2006.286.01:36:09.45#ibcon#read 4, iclass 26, count 0 2006.286.01:36:09.45#ibcon#about to read 5, iclass 26, count 0 2006.286.01:36:09.45#ibcon#read 5, iclass 26, count 0 2006.286.01:36:09.45#ibcon#about to read 6, iclass 26, count 0 2006.286.01:36:09.45#ibcon#read 6, iclass 26, count 0 2006.286.01:36:09.45#ibcon#end of sib2, iclass 26, count 0 2006.286.01:36:09.45#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:36:09.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:36:09.45#ibcon#[25=USB\r\n] 2006.286.01:36:09.45#ibcon#*before write, iclass 26, count 0 2006.286.01:36:09.45#ibcon#enter sib2, iclass 26, count 0 2006.286.01:36:09.45#ibcon#flushed, iclass 26, count 0 2006.286.01:36:09.45#ibcon#about to write, iclass 26, count 0 2006.286.01:36:09.45#ibcon#wrote, iclass 26, count 0 2006.286.01:36:09.45#ibcon#about to read 3, iclass 26, count 0 2006.286.01:36:09.48#ibcon#read 3, iclass 26, count 0 2006.286.01:36:09.48#ibcon#about to read 4, iclass 26, count 0 2006.286.01:36:09.48#ibcon#read 4, iclass 26, count 0 2006.286.01:36:09.48#ibcon#about to read 5, iclass 26, count 0 2006.286.01:36:09.48#ibcon#read 5, iclass 26, count 0 2006.286.01:36:09.48#ibcon#about to read 6, iclass 26, count 0 2006.286.01:36:09.48#ibcon#read 6, iclass 26, count 0 2006.286.01:36:09.48#ibcon#end of sib2, iclass 26, count 0 2006.286.01:36:09.48#ibcon#*after write, iclass 26, count 0 2006.286.01:36:09.48#ibcon#*before return 0, iclass 26, count 0 2006.286.01:36:09.48#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:36:09.48#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.01:36:09.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:36:09.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:36:09.48$vck44/vblo=1,629.99 2006.286.01:36:09.48#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.01:36:09.48#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.01:36:09.48#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:09.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:36:09.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:36:09.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:36:09.48#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:36:09.48#ibcon#first serial, iclass 28, count 0 2006.286.01:36:09.48#ibcon#enter sib2, iclass 28, count 0 2006.286.01:36:09.48#ibcon#flushed, iclass 28, count 0 2006.286.01:36:09.48#ibcon#about to write, iclass 28, count 0 2006.286.01:36:09.48#ibcon#wrote, iclass 28, count 0 2006.286.01:36:09.48#ibcon#about to read 3, iclass 28, count 0 2006.286.01:36:09.50#ibcon#read 3, iclass 28, count 0 2006.286.01:36:09.50#ibcon#about to read 4, iclass 28, count 0 2006.286.01:36:09.50#ibcon#read 4, iclass 28, count 0 2006.286.01:36:09.50#ibcon#about to read 5, iclass 28, count 0 2006.286.01:36:09.50#ibcon#read 5, iclass 28, count 0 2006.286.01:36:09.50#ibcon#about to read 6, iclass 28, count 0 2006.286.01:36:09.50#ibcon#read 6, iclass 28, count 0 2006.286.01:36:09.50#ibcon#end of sib2, iclass 28, count 0 2006.286.01:36:09.50#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:36:09.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:36:09.50#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:36:09.50#ibcon#*before write, iclass 28, count 0 2006.286.01:36:09.50#ibcon#enter sib2, iclass 28, count 0 2006.286.01:36:09.50#ibcon#flushed, iclass 28, count 0 2006.286.01:36:09.50#ibcon#about to write, iclass 28, count 0 2006.286.01:36:09.50#ibcon#wrote, iclass 28, count 0 2006.286.01:36:09.50#ibcon#about to read 3, iclass 28, count 0 2006.286.01:36:09.54#ibcon#read 3, iclass 28, count 0 2006.286.01:36:09.54#ibcon#about to read 4, iclass 28, count 0 2006.286.01:36:09.54#ibcon#read 4, iclass 28, count 0 2006.286.01:36:09.54#ibcon#about to read 5, iclass 28, count 0 2006.286.01:36:09.54#ibcon#read 5, iclass 28, count 0 2006.286.01:36:09.54#ibcon#about to read 6, iclass 28, count 0 2006.286.01:36:09.54#ibcon#read 6, iclass 28, count 0 2006.286.01:36:09.54#ibcon#end of sib2, iclass 28, count 0 2006.286.01:36:09.54#ibcon#*after write, iclass 28, count 0 2006.286.01:36:09.54#ibcon#*before return 0, iclass 28, count 0 2006.286.01:36:09.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:36:09.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:36:09.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:36:09.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:36:09.54$vck44/vb=1,4 2006.286.01:36:09.54#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.01:36:09.54#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.01:36:09.54#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:09.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:36:09.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:36:09.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:36:09.54#ibcon#enter wrdev, iclass 30, count 2 2006.286.01:36:09.54#ibcon#first serial, iclass 30, count 2 2006.286.01:36:09.54#ibcon#enter sib2, iclass 30, count 2 2006.286.01:36:09.54#ibcon#flushed, iclass 30, count 2 2006.286.01:36:09.54#ibcon#about to write, iclass 30, count 2 2006.286.01:36:09.54#ibcon#wrote, iclass 30, count 2 2006.286.01:36:09.54#ibcon#about to read 3, iclass 30, count 2 2006.286.01:36:09.56#ibcon#read 3, iclass 30, count 2 2006.286.01:36:09.56#ibcon#about to read 4, iclass 30, count 2 2006.286.01:36:09.56#ibcon#read 4, iclass 30, count 2 2006.286.01:36:09.56#ibcon#about to read 5, iclass 30, count 2 2006.286.01:36:09.56#ibcon#read 5, iclass 30, count 2 2006.286.01:36:09.56#ibcon#about to read 6, iclass 30, count 2 2006.286.01:36:09.56#ibcon#read 6, iclass 30, count 2 2006.286.01:36:09.56#ibcon#end of sib2, iclass 30, count 2 2006.286.01:36:09.56#ibcon#*mode == 0, iclass 30, count 2 2006.286.01:36:09.56#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.01:36:09.56#ibcon#[27=AT01-04\r\n] 2006.286.01:36:09.56#ibcon#*before write, iclass 30, count 2 2006.286.01:36:09.56#ibcon#enter sib2, iclass 30, count 2 2006.286.01:36:09.56#ibcon#flushed, iclass 30, count 2 2006.286.01:36:09.56#ibcon#about to write, iclass 30, count 2 2006.286.01:36:09.56#ibcon#wrote, iclass 30, count 2 2006.286.01:36:09.56#ibcon#about to read 3, iclass 30, count 2 2006.286.01:36:09.59#ibcon#read 3, iclass 30, count 2 2006.286.01:36:09.59#ibcon#about to read 4, iclass 30, count 2 2006.286.01:36:09.59#ibcon#read 4, iclass 30, count 2 2006.286.01:36:09.59#ibcon#about to read 5, iclass 30, count 2 2006.286.01:36:09.59#ibcon#read 5, iclass 30, count 2 2006.286.01:36:09.59#ibcon#about to read 6, iclass 30, count 2 2006.286.01:36:09.59#ibcon#read 6, iclass 30, count 2 2006.286.01:36:09.59#ibcon#end of sib2, iclass 30, count 2 2006.286.01:36:09.59#ibcon#*after write, iclass 30, count 2 2006.286.01:36:09.59#ibcon#*before return 0, iclass 30, count 2 2006.286.01:36:09.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:36:09.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.01:36:09.59#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.01:36:09.59#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:09.59#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:36:09.71#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:36:09.71#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:36:09.71#ibcon#enter wrdev, iclass 30, count 0 2006.286.01:36:09.71#ibcon#first serial, iclass 30, count 0 2006.286.01:36:09.71#ibcon#enter sib2, iclass 30, count 0 2006.286.01:36:09.71#ibcon#flushed, iclass 30, count 0 2006.286.01:36:09.71#ibcon#about to write, iclass 30, count 0 2006.286.01:36:09.71#ibcon#wrote, iclass 30, count 0 2006.286.01:36:09.71#ibcon#about to read 3, iclass 30, count 0 2006.286.01:36:09.73#ibcon#read 3, iclass 30, count 0 2006.286.01:36:09.73#ibcon#about to read 4, iclass 30, count 0 2006.286.01:36:09.73#ibcon#read 4, iclass 30, count 0 2006.286.01:36:09.73#ibcon#about to read 5, iclass 30, count 0 2006.286.01:36:09.73#ibcon#read 5, iclass 30, count 0 2006.286.01:36:09.73#ibcon#about to read 6, iclass 30, count 0 2006.286.01:36:09.73#ibcon#read 6, iclass 30, count 0 2006.286.01:36:09.73#ibcon#end of sib2, iclass 30, count 0 2006.286.01:36:09.73#ibcon#*mode == 0, iclass 30, count 0 2006.286.01:36:09.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.01:36:09.73#ibcon#[27=USB\r\n] 2006.286.01:36:09.73#ibcon#*before write, iclass 30, count 0 2006.286.01:36:09.73#ibcon#enter sib2, iclass 30, count 0 2006.286.01:36:09.73#ibcon#flushed, iclass 30, count 0 2006.286.01:36:09.73#ibcon#about to write, iclass 30, count 0 2006.286.01:36:09.73#ibcon#wrote, iclass 30, count 0 2006.286.01:36:09.73#ibcon#about to read 3, iclass 30, count 0 2006.286.01:36:09.76#ibcon#read 3, iclass 30, count 0 2006.286.01:36:09.76#ibcon#about to read 4, iclass 30, count 0 2006.286.01:36:09.76#ibcon#read 4, iclass 30, count 0 2006.286.01:36:09.76#ibcon#about to read 5, iclass 30, count 0 2006.286.01:36:09.76#ibcon#read 5, iclass 30, count 0 2006.286.01:36:09.76#ibcon#about to read 6, iclass 30, count 0 2006.286.01:36:09.76#ibcon#read 6, iclass 30, count 0 2006.286.01:36:09.76#ibcon#end of sib2, iclass 30, count 0 2006.286.01:36:09.76#ibcon#*after write, iclass 30, count 0 2006.286.01:36:09.76#ibcon#*before return 0, iclass 30, count 0 2006.286.01:36:09.76#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:36:09.76#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.01:36:09.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.01:36:09.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.01:36:09.76$vck44/vblo=2,634.99 2006.286.01:36:09.76#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.01:36:09.76#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.01:36:09.76#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:09.76#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:36:09.76#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:36:09.76#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:36:09.76#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:36:09.76#ibcon#first serial, iclass 32, count 0 2006.286.01:36:09.76#ibcon#enter sib2, iclass 32, count 0 2006.286.01:36:09.76#ibcon#flushed, iclass 32, count 0 2006.286.01:36:09.76#ibcon#about to write, iclass 32, count 0 2006.286.01:36:09.76#ibcon#wrote, iclass 32, count 0 2006.286.01:36:09.76#ibcon#about to read 3, iclass 32, count 0 2006.286.01:36:09.78#ibcon#read 3, iclass 32, count 0 2006.286.01:36:09.78#ibcon#about to read 4, iclass 32, count 0 2006.286.01:36:09.78#ibcon#read 4, iclass 32, count 0 2006.286.01:36:09.78#ibcon#about to read 5, iclass 32, count 0 2006.286.01:36:09.78#ibcon#read 5, iclass 32, count 0 2006.286.01:36:09.78#ibcon#about to read 6, iclass 32, count 0 2006.286.01:36:09.78#ibcon#read 6, iclass 32, count 0 2006.286.01:36:09.78#ibcon#end of sib2, iclass 32, count 0 2006.286.01:36:09.78#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:36:09.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:36:09.78#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:36:09.78#ibcon#*before write, iclass 32, count 0 2006.286.01:36:09.78#ibcon#enter sib2, iclass 32, count 0 2006.286.01:36:09.78#ibcon#flushed, iclass 32, count 0 2006.286.01:36:09.78#ibcon#about to write, iclass 32, count 0 2006.286.01:36:09.78#ibcon#wrote, iclass 32, count 0 2006.286.01:36:09.78#ibcon#about to read 3, iclass 32, count 0 2006.286.01:36:09.82#ibcon#read 3, iclass 32, count 0 2006.286.01:36:09.82#ibcon#about to read 4, iclass 32, count 0 2006.286.01:36:09.82#ibcon#read 4, iclass 32, count 0 2006.286.01:36:09.82#ibcon#about to read 5, iclass 32, count 0 2006.286.01:36:09.82#ibcon#read 5, iclass 32, count 0 2006.286.01:36:09.82#ibcon#about to read 6, iclass 32, count 0 2006.286.01:36:09.82#ibcon#read 6, iclass 32, count 0 2006.286.01:36:09.82#ibcon#end of sib2, iclass 32, count 0 2006.286.01:36:09.82#ibcon#*after write, iclass 32, count 0 2006.286.01:36:09.82#ibcon#*before return 0, iclass 32, count 0 2006.286.01:36:09.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:36:09.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.01:36:09.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:36:09.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:36:09.82$vck44/vb=2,5 2006.286.01:36:09.82#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.01:36:09.82#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.01:36:09.82#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:09.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:36:09.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:36:09.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:36:09.88#ibcon#enter wrdev, iclass 34, count 2 2006.286.01:36:09.88#ibcon#first serial, iclass 34, count 2 2006.286.01:36:09.88#ibcon#enter sib2, iclass 34, count 2 2006.286.01:36:09.88#ibcon#flushed, iclass 34, count 2 2006.286.01:36:09.88#ibcon#about to write, iclass 34, count 2 2006.286.01:36:09.88#ibcon#wrote, iclass 34, count 2 2006.286.01:36:09.88#ibcon#about to read 3, iclass 34, count 2 2006.286.01:36:09.90#ibcon#read 3, iclass 34, count 2 2006.286.01:36:09.90#ibcon#about to read 4, iclass 34, count 2 2006.286.01:36:09.90#ibcon#read 4, iclass 34, count 2 2006.286.01:36:09.90#ibcon#about to read 5, iclass 34, count 2 2006.286.01:36:09.90#ibcon#read 5, iclass 34, count 2 2006.286.01:36:09.90#ibcon#about to read 6, iclass 34, count 2 2006.286.01:36:09.90#ibcon#read 6, iclass 34, count 2 2006.286.01:36:09.90#ibcon#end of sib2, iclass 34, count 2 2006.286.01:36:09.90#ibcon#*mode == 0, iclass 34, count 2 2006.286.01:36:09.90#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.01:36:09.90#ibcon#[27=AT02-05\r\n] 2006.286.01:36:09.90#ibcon#*before write, iclass 34, count 2 2006.286.01:36:09.90#ibcon#enter sib2, iclass 34, count 2 2006.286.01:36:09.90#ibcon#flushed, iclass 34, count 2 2006.286.01:36:09.90#ibcon#about to write, iclass 34, count 2 2006.286.01:36:09.90#ibcon#wrote, iclass 34, count 2 2006.286.01:36:09.90#ibcon#about to read 3, iclass 34, count 2 2006.286.01:36:09.93#ibcon#read 3, iclass 34, count 2 2006.286.01:36:09.93#ibcon#about to read 4, iclass 34, count 2 2006.286.01:36:09.93#ibcon#read 4, iclass 34, count 2 2006.286.01:36:09.93#ibcon#about to read 5, iclass 34, count 2 2006.286.01:36:09.93#ibcon#read 5, iclass 34, count 2 2006.286.01:36:09.93#ibcon#about to read 6, iclass 34, count 2 2006.286.01:36:09.93#ibcon#read 6, iclass 34, count 2 2006.286.01:36:09.93#ibcon#end of sib2, iclass 34, count 2 2006.286.01:36:09.93#ibcon#*after write, iclass 34, count 2 2006.286.01:36:09.93#ibcon#*before return 0, iclass 34, count 2 2006.286.01:36:09.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:36:09.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.01:36:09.93#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.01:36:09.93#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:09.93#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:36:10.05#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:36:10.05#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:36:10.05#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:36:10.05#ibcon#first serial, iclass 34, count 0 2006.286.01:36:10.05#ibcon#enter sib2, iclass 34, count 0 2006.286.01:36:10.05#ibcon#flushed, iclass 34, count 0 2006.286.01:36:10.05#ibcon#about to write, iclass 34, count 0 2006.286.01:36:10.05#ibcon#wrote, iclass 34, count 0 2006.286.01:36:10.05#ibcon#about to read 3, iclass 34, count 0 2006.286.01:36:10.07#ibcon#read 3, iclass 34, count 0 2006.286.01:36:10.07#ibcon#about to read 4, iclass 34, count 0 2006.286.01:36:10.07#ibcon#read 4, iclass 34, count 0 2006.286.01:36:10.07#ibcon#about to read 5, iclass 34, count 0 2006.286.01:36:10.07#ibcon#read 5, iclass 34, count 0 2006.286.01:36:10.07#ibcon#about to read 6, iclass 34, count 0 2006.286.01:36:10.07#ibcon#read 6, iclass 34, count 0 2006.286.01:36:10.07#ibcon#end of sib2, iclass 34, count 0 2006.286.01:36:10.07#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:36:10.07#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:36:10.07#ibcon#[27=USB\r\n] 2006.286.01:36:10.07#ibcon#*before write, iclass 34, count 0 2006.286.01:36:10.07#ibcon#enter sib2, iclass 34, count 0 2006.286.01:36:10.07#ibcon#flushed, iclass 34, count 0 2006.286.01:36:10.07#ibcon#about to write, iclass 34, count 0 2006.286.01:36:10.07#ibcon#wrote, iclass 34, count 0 2006.286.01:36:10.07#ibcon#about to read 3, iclass 34, count 0 2006.286.01:36:10.10#ibcon#read 3, iclass 34, count 0 2006.286.01:36:10.10#ibcon#about to read 4, iclass 34, count 0 2006.286.01:36:10.10#ibcon#read 4, iclass 34, count 0 2006.286.01:36:10.10#ibcon#about to read 5, iclass 34, count 0 2006.286.01:36:10.10#ibcon#read 5, iclass 34, count 0 2006.286.01:36:10.10#ibcon#about to read 6, iclass 34, count 0 2006.286.01:36:10.10#ibcon#read 6, iclass 34, count 0 2006.286.01:36:10.10#ibcon#end of sib2, iclass 34, count 0 2006.286.01:36:10.10#ibcon#*after write, iclass 34, count 0 2006.286.01:36:10.10#ibcon#*before return 0, iclass 34, count 0 2006.286.01:36:10.10#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:36:10.10#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.01:36:10.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:36:10.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:36:10.10$vck44/vblo=3,649.99 2006.286.01:36:10.10#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.01:36:10.10#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.01:36:10.10#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:10.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:36:10.10#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:36:10.10#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:36:10.10#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:36:10.10#ibcon#first serial, iclass 36, count 0 2006.286.01:36:10.10#ibcon#enter sib2, iclass 36, count 0 2006.286.01:36:10.10#ibcon#flushed, iclass 36, count 0 2006.286.01:36:10.10#ibcon#about to write, iclass 36, count 0 2006.286.01:36:10.10#ibcon#wrote, iclass 36, count 0 2006.286.01:36:10.10#ibcon#about to read 3, iclass 36, count 0 2006.286.01:36:10.12#ibcon#read 3, iclass 36, count 0 2006.286.01:36:10.12#ibcon#about to read 4, iclass 36, count 0 2006.286.01:36:10.12#ibcon#read 4, iclass 36, count 0 2006.286.01:36:10.12#ibcon#about to read 5, iclass 36, count 0 2006.286.01:36:10.12#ibcon#read 5, iclass 36, count 0 2006.286.01:36:10.12#ibcon#about to read 6, iclass 36, count 0 2006.286.01:36:10.12#ibcon#read 6, iclass 36, count 0 2006.286.01:36:10.12#ibcon#end of sib2, iclass 36, count 0 2006.286.01:36:10.12#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:36:10.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:36:10.12#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:36:10.12#ibcon#*before write, iclass 36, count 0 2006.286.01:36:10.12#ibcon#enter sib2, iclass 36, count 0 2006.286.01:36:10.12#ibcon#flushed, iclass 36, count 0 2006.286.01:36:10.12#ibcon#about to write, iclass 36, count 0 2006.286.01:36:10.12#ibcon#wrote, iclass 36, count 0 2006.286.01:36:10.12#ibcon#about to read 3, iclass 36, count 0 2006.286.01:36:10.16#ibcon#read 3, iclass 36, count 0 2006.286.01:36:10.16#ibcon#about to read 4, iclass 36, count 0 2006.286.01:36:10.16#ibcon#read 4, iclass 36, count 0 2006.286.01:36:10.16#ibcon#about to read 5, iclass 36, count 0 2006.286.01:36:10.16#ibcon#read 5, iclass 36, count 0 2006.286.01:36:10.16#ibcon#about to read 6, iclass 36, count 0 2006.286.01:36:10.16#ibcon#read 6, iclass 36, count 0 2006.286.01:36:10.16#ibcon#end of sib2, iclass 36, count 0 2006.286.01:36:10.16#ibcon#*after write, iclass 36, count 0 2006.286.01:36:10.16#ibcon#*before return 0, iclass 36, count 0 2006.286.01:36:10.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:36:10.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.01:36:10.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:36:10.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:36:10.16$vck44/vb=3,4 2006.286.01:36:10.16#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.01:36:10.16#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.01:36:10.16#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:10.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:36:10.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:36:10.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:36:10.22#ibcon#enter wrdev, iclass 38, count 2 2006.286.01:36:10.22#ibcon#first serial, iclass 38, count 2 2006.286.01:36:10.22#ibcon#enter sib2, iclass 38, count 2 2006.286.01:36:10.22#ibcon#flushed, iclass 38, count 2 2006.286.01:36:10.22#ibcon#about to write, iclass 38, count 2 2006.286.01:36:10.22#ibcon#wrote, iclass 38, count 2 2006.286.01:36:10.22#ibcon#about to read 3, iclass 38, count 2 2006.286.01:36:10.24#ibcon#read 3, iclass 38, count 2 2006.286.01:36:10.24#ibcon#about to read 4, iclass 38, count 2 2006.286.01:36:10.24#ibcon#read 4, iclass 38, count 2 2006.286.01:36:10.24#ibcon#about to read 5, iclass 38, count 2 2006.286.01:36:10.24#ibcon#read 5, iclass 38, count 2 2006.286.01:36:10.24#ibcon#about to read 6, iclass 38, count 2 2006.286.01:36:10.24#ibcon#read 6, iclass 38, count 2 2006.286.01:36:10.24#ibcon#end of sib2, iclass 38, count 2 2006.286.01:36:10.24#ibcon#*mode == 0, iclass 38, count 2 2006.286.01:36:10.24#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.01:36:10.24#ibcon#[27=AT03-04\r\n] 2006.286.01:36:10.24#ibcon#*before write, iclass 38, count 2 2006.286.01:36:10.24#ibcon#enter sib2, iclass 38, count 2 2006.286.01:36:10.24#ibcon#flushed, iclass 38, count 2 2006.286.01:36:10.24#ibcon#about to write, iclass 38, count 2 2006.286.01:36:10.24#ibcon#wrote, iclass 38, count 2 2006.286.01:36:10.24#ibcon#about to read 3, iclass 38, count 2 2006.286.01:36:10.27#ibcon#read 3, iclass 38, count 2 2006.286.01:36:10.27#ibcon#about to read 4, iclass 38, count 2 2006.286.01:36:10.27#ibcon#read 4, iclass 38, count 2 2006.286.01:36:10.27#ibcon#about to read 5, iclass 38, count 2 2006.286.01:36:10.27#ibcon#read 5, iclass 38, count 2 2006.286.01:36:10.27#ibcon#about to read 6, iclass 38, count 2 2006.286.01:36:10.27#ibcon#read 6, iclass 38, count 2 2006.286.01:36:10.27#ibcon#end of sib2, iclass 38, count 2 2006.286.01:36:10.27#ibcon#*after write, iclass 38, count 2 2006.286.01:36:10.27#ibcon#*before return 0, iclass 38, count 2 2006.286.01:36:10.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:36:10.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.01:36:10.27#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.01:36:10.27#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:10.27#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:36:10.39#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:36:10.39#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:36:10.39#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:36:10.39#ibcon#first serial, iclass 38, count 0 2006.286.01:36:10.39#ibcon#enter sib2, iclass 38, count 0 2006.286.01:36:10.39#ibcon#flushed, iclass 38, count 0 2006.286.01:36:10.39#ibcon#about to write, iclass 38, count 0 2006.286.01:36:10.39#ibcon#wrote, iclass 38, count 0 2006.286.01:36:10.39#ibcon#about to read 3, iclass 38, count 0 2006.286.01:36:10.41#ibcon#read 3, iclass 38, count 0 2006.286.01:36:10.41#ibcon#about to read 4, iclass 38, count 0 2006.286.01:36:10.41#ibcon#read 4, iclass 38, count 0 2006.286.01:36:10.41#ibcon#about to read 5, iclass 38, count 0 2006.286.01:36:10.41#ibcon#read 5, iclass 38, count 0 2006.286.01:36:10.41#ibcon#about to read 6, iclass 38, count 0 2006.286.01:36:10.41#ibcon#read 6, iclass 38, count 0 2006.286.01:36:10.41#ibcon#end of sib2, iclass 38, count 0 2006.286.01:36:10.41#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:36:10.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:36:10.41#ibcon#[27=USB\r\n] 2006.286.01:36:10.41#ibcon#*before write, iclass 38, count 0 2006.286.01:36:10.41#ibcon#enter sib2, iclass 38, count 0 2006.286.01:36:10.41#ibcon#flushed, iclass 38, count 0 2006.286.01:36:10.41#ibcon#about to write, iclass 38, count 0 2006.286.01:36:10.41#ibcon#wrote, iclass 38, count 0 2006.286.01:36:10.41#ibcon#about to read 3, iclass 38, count 0 2006.286.01:36:10.44#ibcon#read 3, iclass 38, count 0 2006.286.01:36:10.44#ibcon#about to read 4, iclass 38, count 0 2006.286.01:36:10.44#ibcon#read 4, iclass 38, count 0 2006.286.01:36:10.44#ibcon#about to read 5, iclass 38, count 0 2006.286.01:36:10.44#ibcon#read 5, iclass 38, count 0 2006.286.01:36:10.44#ibcon#about to read 6, iclass 38, count 0 2006.286.01:36:10.44#ibcon#read 6, iclass 38, count 0 2006.286.01:36:10.44#ibcon#end of sib2, iclass 38, count 0 2006.286.01:36:10.44#ibcon#*after write, iclass 38, count 0 2006.286.01:36:10.44#ibcon#*before return 0, iclass 38, count 0 2006.286.01:36:10.44#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:36:10.44#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.01:36:10.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:36:10.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:36:10.44$vck44/vblo=4,679.99 2006.286.01:36:10.44#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.01:36:10.44#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.01:36:10.44#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:10.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:36:10.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:36:10.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:36:10.44#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:36:10.44#ibcon#first serial, iclass 40, count 0 2006.286.01:36:10.44#ibcon#enter sib2, iclass 40, count 0 2006.286.01:36:10.44#ibcon#flushed, iclass 40, count 0 2006.286.01:36:10.44#ibcon#about to write, iclass 40, count 0 2006.286.01:36:10.44#ibcon#wrote, iclass 40, count 0 2006.286.01:36:10.44#ibcon#about to read 3, iclass 40, count 0 2006.286.01:36:10.46#ibcon#read 3, iclass 40, count 0 2006.286.01:36:10.46#ibcon#about to read 4, iclass 40, count 0 2006.286.01:36:10.46#ibcon#read 4, iclass 40, count 0 2006.286.01:36:10.46#ibcon#about to read 5, iclass 40, count 0 2006.286.01:36:10.46#ibcon#read 5, iclass 40, count 0 2006.286.01:36:10.46#ibcon#about to read 6, iclass 40, count 0 2006.286.01:36:10.46#ibcon#read 6, iclass 40, count 0 2006.286.01:36:10.46#ibcon#end of sib2, iclass 40, count 0 2006.286.01:36:10.46#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:36:10.46#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:36:10.46#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:36:10.46#ibcon#*before write, iclass 40, count 0 2006.286.01:36:10.46#ibcon#enter sib2, iclass 40, count 0 2006.286.01:36:10.46#ibcon#flushed, iclass 40, count 0 2006.286.01:36:10.46#ibcon#about to write, iclass 40, count 0 2006.286.01:36:10.46#ibcon#wrote, iclass 40, count 0 2006.286.01:36:10.46#ibcon#about to read 3, iclass 40, count 0 2006.286.01:36:10.50#ibcon#read 3, iclass 40, count 0 2006.286.01:36:10.50#ibcon#about to read 4, iclass 40, count 0 2006.286.01:36:10.50#ibcon#read 4, iclass 40, count 0 2006.286.01:36:10.50#ibcon#about to read 5, iclass 40, count 0 2006.286.01:36:10.50#ibcon#read 5, iclass 40, count 0 2006.286.01:36:10.50#ibcon#about to read 6, iclass 40, count 0 2006.286.01:36:10.50#ibcon#read 6, iclass 40, count 0 2006.286.01:36:10.50#ibcon#end of sib2, iclass 40, count 0 2006.286.01:36:10.50#ibcon#*after write, iclass 40, count 0 2006.286.01:36:10.50#ibcon#*before return 0, iclass 40, count 0 2006.286.01:36:10.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:36:10.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.01:36:10.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:36:10.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:36:10.50$vck44/vb=4,5 2006.286.01:36:10.50#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.01:36:10.50#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.01:36:10.50#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:10.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:36:10.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:36:10.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:36:10.56#ibcon#enter wrdev, iclass 4, count 2 2006.286.01:36:10.56#ibcon#first serial, iclass 4, count 2 2006.286.01:36:10.56#ibcon#enter sib2, iclass 4, count 2 2006.286.01:36:10.56#ibcon#flushed, iclass 4, count 2 2006.286.01:36:10.56#ibcon#about to write, iclass 4, count 2 2006.286.01:36:10.56#ibcon#wrote, iclass 4, count 2 2006.286.01:36:10.56#ibcon#about to read 3, iclass 4, count 2 2006.286.01:36:10.58#ibcon#read 3, iclass 4, count 2 2006.286.01:36:10.58#ibcon#about to read 4, iclass 4, count 2 2006.286.01:36:10.58#ibcon#read 4, iclass 4, count 2 2006.286.01:36:10.58#ibcon#about to read 5, iclass 4, count 2 2006.286.01:36:10.58#ibcon#read 5, iclass 4, count 2 2006.286.01:36:10.58#ibcon#about to read 6, iclass 4, count 2 2006.286.01:36:10.58#ibcon#read 6, iclass 4, count 2 2006.286.01:36:10.58#ibcon#end of sib2, iclass 4, count 2 2006.286.01:36:10.58#ibcon#*mode == 0, iclass 4, count 2 2006.286.01:36:10.58#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.01:36:10.58#ibcon#[27=AT04-05\r\n] 2006.286.01:36:10.58#ibcon#*before write, iclass 4, count 2 2006.286.01:36:10.58#ibcon#enter sib2, iclass 4, count 2 2006.286.01:36:10.58#ibcon#flushed, iclass 4, count 2 2006.286.01:36:10.58#ibcon#about to write, iclass 4, count 2 2006.286.01:36:10.58#ibcon#wrote, iclass 4, count 2 2006.286.01:36:10.58#ibcon#about to read 3, iclass 4, count 2 2006.286.01:36:10.61#ibcon#read 3, iclass 4, count 2 2006.286.01:36:10.61#ibcon#about to read 4, iclass 4, count 2 2006.286.01:36:10.61#ibcon#read 4, iclass 4, count 2 2006.286.01:36:10.61#ibcon#about to read 5, iclass 4, count 2 2006.286.01:36:10.61#ibcon#read 5, iclass 4, count 2 2006.286.01:36:10.61#ibcon#about to read 6, iclass 4, count 2 2006.286.01:36:10.61#ibcon#read 6, iclass 4, count 2 2006.286.01:36:10.61#ibcon#end of sib2, iclass 4, count 2 2006.286.01:36:10.61#ibcon#*after write, iclass 4, count 2 2006.286.01:36:10.61#ibcon#*before return 0, iclass 4, count 2 2006.286.01:36:10.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:36:10.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.01:36:10.61#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.01:36:10.61#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:10.61#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:36:10.73#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:36:10.73#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:36:10.73#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:36:10.73#ibcon#first serial, iclass 4, count 0 2006.286.01:36:10.73#ibcon#enter sib2, iclass 4, count 0 2006.286.01:36:10.73#ibcon#flushed, iclass 4, count 0 2006.286.01:36:10.73#ibcon#about to write, iclass 4, count 0 2006.286.01:36:10.73#ibcon#wrote, iclass 4, count 0 2006.286.01:36:10.73#ibcon#about to read 3, iclass 4, count 0 2006.286.01:36:10.75#ibcon#read 3, iclass 4, count 0 2006.286.01:36:10.75#ibcon#about to read 4, iclass 4, count 0 2006.286.01:36:10.75#ibcon#read 4, iclass 4, count 0 2006.286.01:36:10.75#ibcon#about to read 5, iclass 4, count 0 2006.286.01:36:10.75#ibcon#read 5, iclass 4, count 0 2006.286.01:36:10.75#ibcon#about to read 6, iclass 4, count 0 2006.286.01:36:10.75#ibcon#read 6, iclass 4, count 0 2006.286.01:36:10.75#ibcon#end of sib2, iclass 4, count 0 2006.286.01:36:10.75#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:36:10.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:36:10.75#ibcon#[27=USB\r\n] 2006.286.01:36:10.75#ibcon#*before write, iclass 4, count 0 2006.286.01:36:10.75#ibcon#enter sib2, iclass 4, count 0 2006.286.01:36:10.75#ibcon#flushed, iclass 4, count 0 2006.286.01:36:10.75#ibcon#about to write, iclass 4, count 0 2006.286.01:36:10.75#ibcon#wrote, iclass 4, count 0 2006.286.01:36:10.75#ibcon#about to read 3, iclass 4, count 0 2006.286.01:36:10.78#ibcon#read 3, iclass 4, count 0 2006.286.01:36:10.78#ibcon#about to read 4, iclass 4, count 0 2006.286.01:36:10.78#ibcon#read 4, iclass 4, count 0 2006.286.01:36:10.78#ibcon#about to read 5, iclass 4, count 0 2006.286.01:36:10.78#ibcon#read 5, iclass 4, count 0 2006.286.01:36:10.78#ibcon#about to read 6, iclass 4, count 0 2006.286.01:36:10.78#ibcon#read 6, iclass 4, count 0 2006.286.01:36:10.78#ibcon#end of sib2, iclass 4, count 0 2006.286.01:36:10.78#ibcon#*after write, iclass 4, count 0 2006.286.01:36:10.78#ibcon#*before return 0, iclass 4, count 0 2006.286.01:36:10.78#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:36:10.78#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.01:36:10.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:36:10.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:36:10.78$vck44/vblo=5,709.99 2006.286.01:36:10.78#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.01:36:10.78#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.01:36:10.78#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:10.78#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:36:10.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:36:10.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:36:10.78#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:36:10.78#ibcon#first serial, iclass 6, count 0 2006.286.01:36:10.78#ibcon#enter sib2, iclass 6, count 0 2006.286.01:36:10.78#ibcon#flushed, iclass 6, count 0 2006.286.01:36:10.78#ibcon#about to write, iclass 6, count 0 2006.286.01:36:10.78#ibcon#wrote, iclass 6, count 0 2006.286.01:36:10.78#ibcon#about to read 3, iclass 6, count 0 2006.286.01:36:10.80#ibcon#read 3, iclass 6, count 0 2006.286.01:36:10.80#ibcon#about to read 4, iclass 6, count 0 2006.286.01:36:10.80#ibcon#read 4, iclass 6, count 0 2006.286.01:36:10.80#ibcon#about to read 5, iclass 6, count 0 2006.286.01:36:10.80#ibcon#read 5, iclass 6, count 0 2006.286.01:36:10.80#ibcon#about to read 6, iclass 6, count 0 2006.286.01:36:10.80#ibcon#read 6, iclass 6, count 0 2006.286.01:36:10.80#ibcon#end of sib2, iclass 6, count 0 2006.286.01:36:10.80#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:36:10.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:36:10.80#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:36:10.80#ibcon#*before write, iclass 6, count 0 2006.286.01:36:10.80#ibcon#enter sib2, iclass 6, count 0 2006.286.01:36:10.80#ibcon#flushed, iclass 6, count 0 2006.286.01:36:10.80#ibcon#about to write, iclass 6, count 0 2006.286.01:36:10.80#ibcon#wrote, iclass 6, count 0 2006.286.01:36:10.80#ibcon#about to read 3, iclass 6, count 0 2006.286.01:36:10.84#ibcon#read 3, iclass 6, count 0 2006.286.01:36:10.84#ibcon#about to read 4, iclass 6, count 0 2006.286.01:36:10.84#ibcon#read 4, iclass 6, count 0 2006.286.01:36:10.84#ibcon#about to read 5, iclass 6, count 0 2006.286.01:36:10.84#ibcon#read 5, iclass 6, count 0 2006.286.01:36:10.84#ibcon#about to read 6, iclass 6, count 0 2006.286.01:36:10.84#ibcon#read 6, iclass 6, count 0 2006.286.01:36:10.84#ibcon#end of sib2, iclass 6, count 0 2006.286.01:36:10.84#ibcon#*after write, iclass 6, count 0 2006.286.01:36:10.84#ibcon#*before return 0, iclass 6, count 0 2006.286.01:36:10.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:36:10.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.01:36:10.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:36:10.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:36:10.84$vck44/vb=5,4 2006.286.01:36:10.84#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.01:36:10.84#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.01:36:10.84#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:10.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:36:10.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:36:10.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:36:10.90#ibcon#enter wrdev, iclass 10, count 2 2006.286.01:36:10.90#ibcon#first serial, iclass 10, count 2 2006.286.01:36:10.90#ibcon#enter sib2, iclass 10, count 2 2006.286.01:36:10.90#ibcon#flushed, iclass 10, count 2 2006.286.01:36:10.90#ibcon#about to write, iclass 10, count 2 2006.286.01:36:10.90#ibcon#wrote, iclass 10, count 2 2006.286.01:36:10.90#ibcon#about to read 3, iclass 10, count 2 2006.286.01:36:10.92#ibcon#read 3, iclass 10, count 2 2006.286.01:36:10.92#ibcon#about to read 4, iclass 10, count 2 2006.286.01:36:10.92#ibcon#read 4, iclass 10, count 2 2006.286.01:36:10.92#ibcon#about to read 5, iclass 10, count 2 2006.286.01:36:10.92#ibcon#read 5, iclass 10, count 2 2006.286.01:36:10.92#ibcon#about to read 6, iclass 10, count 2 2006.286.01:36:10.92#ibcon#read 6, iclass 10, count 2 2006.286.01:36:10.92#ibcon#end of sib2, iclass 10, count 2 2006.286.01:36:10.92#ibcon#*mode == 0, iclass 10, count 2 2006.286.01:36:10.92#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.01:36:10.92#ibcon#[27=AT05-04\r\n] 2006.286.01:36:10.92#ibcon#*before write, iclass 10, count 2 2006.286.01:36:10.92#ibcon#enter sib2, iclass 10, count 2 2006.286.01:36:10.92#ibcon#flushed, iclass 10, count 2 2006.286.01:36:10.92#ibcon#about to write, iclass 10, count 2 2006.286.01:36:10.92#ibcon#wrote, iclass 10, count 2 2006.286.01:36:10.92#ibcon#about to read 3, iclass 10, count 2 2006.286.01:36:10.95#ibcon#read 3, iclass 10, count 2 2006.286.01:36:10.95#ibcon#about to read 4, iclass 10, count 2 2006.286.01:36:10.95#ibcon#read 4, iclass 10, count 2 2006.286.01:36:10.95#ibcon#about to read 5, iclass 10, count 2 2006.286.01:36:10.95#ibcon#read 5, iclass 10, count 2 2006.286.01:36:10.95#ibcon#about to read 6, iclass 10, count 2 2006.286.01:36:10.95#ibcon#read 6, iclass 10, count 2 2006.286.01:36:10.95#ibcon#end of sib2, iclass 10, count 2 2006.286.01:36:10.95#ibcon#*after write, iclass 10, count 2 2006.286.01:36:10.95#ibcon#*before return 0, iclass 10, count 2 2006.286.01:36:10.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:36:10.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.01:36:10.95#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.01:36:10.95#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:10.95#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:36:11.07#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:36:11.07#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:36:11.07#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:36:11.07#ibcon#first serial, iclass 10, count 0 2006.286.01:36:11.07#ibcon#enter sib2, iclass 10, count 0 2006.286.01:36:11.07#ibcon#flushed, iclass 10, count 0 2006.286.01:36:11.07#ibcon#about to write, iclass 10, count 0 2006.286.01:36:11.07#ibcon#wrote, iclass 10, count 0 2006.286.01:36:11.07#ibcon#about to read 3, iclass 10, count 0 2006.286.01:36:11.09#ibcon#read 3, iclass 10, count 0 2006.286.01:36:11.09#ibcon#about to read 4, iclass 10, count 0 2006.286.01:36:11.09#ibcon#read 4, iclass 10, count 0 2006.286.01:36:11.09#ibcon#about to read 5, iclass 10, count 0 2006.286.01:36:11.09#ibcon#read 5, iclass 10, count 0 2006.286.01:36:11.09#ibcon#about to read 6, iclass 10, count 0 2006.286.01:36:11.09#ibcon#read 6, iclass 10, count 0 2006.286.01:36:11.09#ibcon#end of sib2, iclass 10, count 0 2006.286.01:36:11.09#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:36:11.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:36:11.09#ibcon#[27=USB\r\n] 2006.286.01:36:11.09#ibcon#*before write, iclass 10, count 0 2006.286.01:36:11.09#ibcon#enter sib2, iclass 10, count 0 2006.286.01:36:11.09#ibcon#flushed, iclass 10, count 0 2006.286.01:36:11.09#ibcon#about to write, iclass 10, count 0 2006.286.01:36:11.09#ibcon#wrote, iclass 10, count 0 2006.286.01:36:11.09#ibcon#about to read 3, iclass 10, count 0 2006.286.01:36:11.12#ibcon#read 3, iclass 10, count 0 2006.286.01:36:11.12#ibcon#about to read 4, iclass 10, count 0 2006.286.01:36:11.12#ibcon#read 4, iclass 10, count 0 2006.286.01:36:11.12#ibcon#about to read 5, iclass 10, count 0 2006.286.01:36:11.12#ibcon#read 5, iclass 10, count 0 2006.286.01:36:11.12#ibcon#about to read 6, iclass 10, count 0 2006.286.01:36:11.12#ibcon#read 6, iclass 10, count 0 2006.286.01:36:11.12#ibcon#end of sib2, iclass 10, count 0 2006.286.01:36:11.12#ibcon#*after write, iclass 10, count 0 2006.286.01:36:11.12#ibcon#*before return 0, iclass 10, count 0 2006.286.01:36:11.12#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:36:11.12#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.01:36:11.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:36:11.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:36:11.12$vck44/vblo=6,719.99 2006.286.01:36:11.12#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.01:36:11.12#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.01:36:11.12#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:11.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:36:11.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:36:11.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:36:11.12#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:36:11.12#ibcon#first serial, iclass 12, count 0 2006.286.01:36:11.12#ibcon#enter sib2, iclass 12, count 0 2006.286.01:36:11.12#ibcon#flushed, iclass 12, count 0 2006.286.01:36:11.12#ibcon#about to write, iclass 12, count 0 2006.286.01:36:11.12#ibcon#wrote, iclass 12, count 0 2006.286.01:36:11.12#ibcon#about to read 3, iclass 12, count 0 2006.286.01:36:11.14#ibcon#read 3, iclass 12, count 0 2006.286.01:36:11.14#ibcon#about to read 4, iclass 12, count 0 2006.286.01:36:11.14#ibcon#read 4, iclass 12, count 0 2006.286.01:36:11.14#ibcon#about to read 5, iclass 12, count 0 2006.286.01:36:11.14#ibcon#read 5, iclass 12, count 0 2006.286.01:36:11.14#ibcon#about to read 6, iclass 12, count 0 2006.286.01:36:11.14#ibcon#read 6, iclass 12, count 0 2006.286.01:36:11.14#ibcon#end of sib2, iclass 12, count 0 2006.286.01:36:11.14#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:36:11.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:36:11.14#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:36:11.14#ibcon#*before write, iclass 12, count 0 2006.286.01:36:11.14#ibcon#enter sib2, iclass 12, count 0 2006.286.01:36:11.14#ibcon#flushed, iclass 12, count 0 2006.286.01:36:11.14#ibcon#about to write, iclass 12, count 0 2006.286.01:36:11.14#ibcon#wrote, iclass 12, count 0 2006.286.01:36:11.14#ibcon#about to read 3, iclass 12, count 0 2006.286.01:36:11.18#ibcon#read 3, iclass 12, count 0 2006.286.01:36:11.18#ibcon#about to read 4, iclass 12, count 0 2006.286.01:36:11.18#ibcon#read 4, iclass 12, count 0 2006.286.01:36:11.18#ibcon#about to read 5, iclass 12, count 0 2006.286.01:36:11.18#ibcon#read 5, iclass 12, count 0 2006.286.01:36:11.18#ibcon#about to read 6, iclass 12, count 0 2006.286.01:36:11.18#ibcon#read 6, iclass 12, count 0 2006.286.01:36:11.18#ibcon#end of sib2, iclass 12, count 0 2006.286.01:36:11.18#ibcon#*after write, iclass 12, count 0 2006.286.01:36:11.18#ibcon#*before return 0, iclass 12, count 0 2006.286.01:36:11.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:36:11.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.01:36:11.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:36:11.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:36:11.18$vck44/vb=6,3 2006.286.01:36:11.18#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.01:36:11.18#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.01:36:11.18#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:11.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:36:11.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:36:11.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:36:11.24#ibcon#enter wrdev, iclass 14, count 2 2006.286.01:36:11.24#ibcon#first serial, iclass 14, count 2 2006.286.01:36:11.24#ibcon#enter sib2, iclass 14, count 2 2006.286.01:36:11.24#ibcon#flushed, iclass 14, count 2 2006.286.01:36:11.24#ibcon#about to write, iclass 14, count 2 2006.286.01:36:11.24#ibcon#wrote, iclass 14, count 2 2006.286.01:36:11.24#ibcon#about to read 3, iclass 14, count 2 2006.286.01:36:11.26#ibcon#read 3, iclass 14, count 2 2006.286.01:36:11.26#ibcon#about to read 4, iclass 14, count 2 2006.286.01:36:11.26#ibcon#read 4, iclass 14, count 2 2006.286.01:36:11.26#ibcon#about to read 5, iclass 14, count 2 2006.286.01:36:11.26#ibcon#read 5, iclass 14, count 2 2006.286.01:36:11.26#ibcon#about to read 6, iclass 14, count 2 2006.286.01:36:11.26#ibcon#read 6, iclass 14, count 2 2006.286.01:36:11.26#ibcon#end of sib2, iclass 14, count 2 2006.286.01:36:11.26#ibcon#*mode == 0, iclass 14, count 2 2006.286.01:36:11.26#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.01:36:11.26#ibcon#[27=AT06-03\r\n] 2006.286.01:36:11.26#ibcon#*before write, iclass 14, count 2 2006.286.01:36:11.26#ibcon#enter sib2, iclass 14, count 2 2006.286.01:36:11.26#ibcon#flushed, iclass 14, count 2 2006.286.01:36:11.26#ibcon#about to write, iclass 14, count 2 2006.286.01:36:11.26#ibcon#wrote, iclass 14, count 2 2006.286.01:36:11.26#ibcon#about to read 3, iclass 14, count 2 2006.286.01:36:11.29#ibcon#read 3, iclass 14, count 2 2006.286.01:36:11.29#ibcon#about to read 4, iclass 14, count 2 2006.286.01:36:11.29#ibcon#read 4, iclass 14, count 2 2006.286.01:36:11.29#ibcon#about to read 5, iclass 14, count 2 2006.286.01:36:11.29#ibcon#read 5, iclass 14, count 2 2006.286.01:36:11.29#ibcon#about to read 6, iclass 14, count 2 2006.286.01:36:11.29#ibcon#read 6, iclass 14, count 2 2006.286.01:36:11.29#ibcon#end of sib2, iclass 14, count 2 2006.286.01:36:11.29#ibcon#*after write, iclass 14, count 2 2006.286.01:36:11.29#ibcon#*before return 0, iclass 14, count 2 2006.286.01:36:11.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:36:11.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.01:36:11.29#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.01:36:11.29#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:11.29#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:36:11.41#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:36:11.41#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:36:11.41#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:36:11.41#ibcon#first serial, iclass 14, count 0 2006.286.01:36:11.41#ibcon#enter sib2, iclass 14, count 0 2006.286.01:36:11.41#ibcon#flushed, iclass 14, count 0 2006.286.01:36:11.41#ibcon#about to write, iclass 14, count 0 2006.286.01:36:11.41#ibcon#wrote, iclass 14, count 0 2006.286.01:36:11.41#ibcon#about to read 3, iclass 14, count 0 2006.286.01:36:11.43#ibcon#read 3, iclass 14, count 0 2006.286.01:36:11.43#ibcon#about to read 4, iclass 14, count 0 2006.286.01:36:11.43#ibcon#read 4, iclass 14, count 0 2006.286.01:36:11.43#ibcon#about to read 5, iclass 14, count 0 2006.286.01:36:11.43#ibcon#read 5, iclass 14, count 0 2006.286.01:36:11.43#ibcon#about to read 6, iclass 14, count 0 2006.286.01:36:11.43#ibcon#read 6, iclass 14, count 0 2006.286.01:36:11.43#ibcon#end of sib2, iclass 14, count 0 2006.286.01:36:11.43#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:36:11.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:36:11.43#ibcon#[27=USB\r\n] 2006.286.01:36:11.43#ibcon#*before write, iclass 14, count 0 2006.286.01:36:11.43#ibcon#enter sib2, iclass 14, count 0 2006.286.01:36:11.43#ibcon#flushed, iclass 14, count 0 2006.286.01:36:11.43#ibcon#about to write, iclass 14, count 0 2006.286.01:36:11.43#ibcon#wrote, iclass 14, count 0 2006.286.01:36:11.43#ibcon#about to read 3, iclass 14, count 0 2006.286.01:36:11.46#ibcon#read 3, iclass 14, count 0 2006.286.01:36:11.46#ibcon#about to read 4, iclass 14, count 0 2006.286.01:36:11.46#ibcon#read 4, iclass 14, count 0 2006.286.01:36:11.46#ibcon#about to read 5, iclass 14, count 0 2006.286.01:36:11.46#ibcon#read 5, iclass 14, count 0 2006.286.01:36:11.46#ibcon#about to read 6, iclass 14, count 0 2006.286.01:36:11.46#ibcon#read 6, iclass 14, count 0 2006.286.01:36:11.46#ibcon#end of sib2, iclass 14, count 0 2006.286.01:36:11.46#ibcon#*after write, iclass 14, count 0 2006.286.01:36:11.46#ibcon#*before return 0, iclass 14, count 0 2006.286.01:36:11.46#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:36:11.46#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.01:36:11.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:36:11.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:36:11.46$vck44/vblo=7,734.99 2006.286.01:36:11.46#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.01:36:11.46#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.01:36:11.46#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:11.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:36:11.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:36:11.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:36:11.46#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:36:11.46#ibcon#first serial, iclass 16, count 0 2006.286.01:36:11.46#ibcon#enter sib2, iclass 16, count 0 2006.286.01:36:11.46#ibcon#flushed, iclass 16, count 0 2006.286.01:36:11.46#ibcon#about to write, iclass 16, count 0 2006.286.01:36:11.46#ibcon#wrote, iclass 16, count 0 2006.286.01:36:11.46#ibcon#about to read 3, iclass 16, count 0 2006.286.01:36:11.48#ibcon#read 3, iclass 16, count 0 2006.286.01:36:11.48#ibcon#about to read 4, iclass 16, count 0 2006.286.01:36:11.48#ibcon#read 4, iclass 16, count 0 2006.286.01:36:11.48#ibcon#about to read 5, iclass 16, count 0 2006.286.01:36:11.48#ibcon#read 5, iclass 16, count 0 2006.286.01:36:11.48#ibcon#about to read 6, iclass 16, count 0 2006.286.01:36:11.48#ibcon#read 6, iclass 16, count 0 2006.286.01:36:11.48#ibcon#end of sib2, iclass 16, count 0 2006.286.01:36:11.48#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:36:11.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:36:11.48#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:36:11.48#ibcon#*before write, iclass 16, count 0 2006.286.01:36:11.48#ibcon#enter sib2, iclass 16, count 0 2006.286.01:36:11.48#ibcon#flushed, iclass 16, count 0 2006.286.01:36:11.48#ibcon#about to write, iclass 16, count 0 2006.286.01:36:11.48#ibcon#wrote, iclass 16, count 0 2006.286.01:36:11.48#ibcon#about to read 3, iclass 16, count 0 2006.286.01:36:11.52#ibcon#read 3, iclass 16, count 0 2006.286.01:36:11.52#ibcon#about to read 4, iclass 16, count 0 2006.286.01:36:11.52#ibcon#read 4, iclass 16, count 0 2006.286.01:36:11.52#ibcon#about to read 5, iclass 16, count 0 2006.286.01:36:11.52#ibcon#read 5, iclass 16, count 0 2006.286.01:36:11.52#ibcon#about to read 6, iclass 16, count 0 2006.286.01:36:11.52#ibcon#read 6, iclass 16, count 0 2006.286.01:36:11.52#ibcon#end of sib2, iclass 16, count 0 2006.286.01:36:11.52#ibcon#*after write, iclass 16, count 0 2006.286.01:36:11.52#ibcon#*before return 0, iclass 16, count 0 2006.286.01:36:11.52#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:36:11.52#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.01:36:11.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:36:11.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:36:11.52$vck44/vb=7,4 2006.286.01:36:11.52#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.01:36:11.52#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.01:36:11.52#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:11.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:36:11.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:36:11.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:36:11.58#ibcon#enter wrdev, iclass 18, count 2 2006.286.01:36:11.58#ibcon#first serial, iclass 18, count 2 2006.286.01:36:11.58#ibcon#enter sib2, iclass 18, count 2 2006.286.01:36:11.58#ibcon#flushed, iclass 18, count 2 2006.286.01:36:11.58#ibcon#about to write, iclass 18, count 2 2006.286.01:36:11.58#ibcon#wrote, iclass 18, count 2 2006.286.01:36:11.58#ibcon#about to read 3, iclass 18, count 2 2006.286.01:36:11.60#ibcon#read 3, iclass 18, count 2 2006.286.01:36:11.60#ibcon#about to read 4, iclass 18, count 2 2006.286.01:36:11.60#ibcon#read 4, iclass 18, count 2 2006.286.01:36:11.60#ibcon#about to read 5, iclass 18, count 2 2006.286.01:36:11.60#ibcon#read 5, iclass 18, count 2 2006.286.01:36:11.60#ibcon#about to read 6, iclass 18, count 2 2006.286.01:36:11.60#ibcon#read 6, iclass 18, count 2 2006.286.01:36:11.60#ibcon#end of sib2, iclass 18, count 2 2006.286.01:36:11.60#ibcon#*mode == 0, iclass 18, count 2 2006.286.01:36:11.60#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.01:36:11.60#ibcon#[27=AT07-04\r\n] 2006.286.01:36:11.60#ibcon#*before write, iclass 18, count 2 2006.286.01:36:11.60#ibcon#enter sib2, iclass 18, count 2 2006.286.01:36:11.60#ibcon#flushed, iclass 18, count 2 2006.286.01:36:11.60#ibcon#about to write, iclass 18, count 2 2006.286.01:36:11.60#ibcon#wrote, iclass 18, count 2 2006.286.01:36:11.60#ibcon#about to read 3, iclass 18, count 2 2006.286.01:36:11.63#ibcon#read 3, iclass 18, count 2 2006.286.01:36:11.63#ibcon#about to read 4, iclass 18, count 2 2006.286.01:36:11.63#ibcon#read 4, iclass 18, count 2 2006.286.01:36:11.63#ibcon#about to read 5, iclass 18, count 2 2006.286.01:36:11.63#ibcon#read 5, iclass 18, count 2 2006.286.01:36:11.63#ibcon#about to read 6, iclass 18, count 2 2006.286.01:36:11.63#ibcon#read 6, iclass 18, count 2 2006.286.01:36:11.63#ibcon#end of sib2, iclass 18, count 2 2006.286.01:36:11.63#ibcon#*after write, iclass 18, count 2 2006.286.01:36:11.63#ibcon#*before return 0, iclass 18, count 2 2006.286.01:36:11.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:36:11.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.01:36:11.63#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.01:36:11.63#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:11.63#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:36:11.75#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:36:11.75#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:36:11.75#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:36:11.75#ibcon#first serial, iclass 18, count 0 2006.286.01:36:11.75#ibcon#enter sib2, iclass 18, count 0 2006.286.01:36:11.75#ibcon#flushed, iclass 18, count 0 2006.286.01:36:11.75#ibcon#about to write, iclass 18, count 0 2006.286.01:36:11.75#ibcon#wrote, iclass 18, count 0 2006.286.01:36:11.75#ibcon#about to read 3, iclass 18, count 0 2006.286.01:36:11.77#ibcon#read 3, iclass 18, count 0 2006.286.01:36:11.77#ibcon#about to read 4, iclass 18, count 0 2006.286.01:36:11.77#ibcon#read 4, iclass 18, count 0 2006.286.01:36:11.77#ibcon#about to read 5, iclass 18, count 0 2006.286.01:36:11.77#ibcon#read 5, iclass 18, count 0 2006.286.01:36:11.77#ibcon#about to read 6, iclass 18, count 0 2006.286.01:36:11.77#ibcon#read 6, iclass 18, count 0 2006.286.01:36:11.77#ibcon#end of sib2, iclass 18, count 0 2006.286.01:36:11.77#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:36:11.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:36:11.77#ibcon#[27=USB\r\n] 2006.286.01:36:11.77#ibcon#*before write, iclass 18, count 0 2006.286.01:36:11.77#ibcon#enter sib2, iclass 18, count 0 2006.286.01:36:11.77#ibcon#flushed, iclass 18, count 0 2006.286.01:36:11.77#ibcon#about to write, iclass 18, count 0 2006.286.01:36:11.77#ibcon#wrote, iclass 18, count 0 2006.286.01:36:11.77#ibcon#about to read 3, iclass 18, count 0 2006.286.01:36:11.80#ibcon#read 3, iclass 18, count 0 2006.286.01:36:11.80#ibcon#about to read 4, iclass 18, count 0 2006.286.01:36:11.80#ibcon#read 4, iclass 18, count 0 2006.286.01:36:11.80#ibcon#about to read 5, iclass 18, count 0 2006.286.01:36:11.80#ibcon#read 5, iclass 18, count 0 2006.286.01:36:11.80#ibcon#about to read 6, iclass 18, count 0 2006.286.01:36:11.80#ibcon#read 6, iclass 18, count 0 2006.286.01:36:11.80#ibcon#end of sib2, iclass 18, count 0 2006.286.01:36:11.80#ibcon#*after write, iclass 18, count 0 2006.286.01:36:11.80#ibcon#*before return 0, iclass 18, count 0 2006.286.01:36:11.80#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:36:11.80#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.01:36:11.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:36:11.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:36:11.80$vck44/vblo=8,744.99 2006.286.01:36:11.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.01:36:11.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.01:36:11.80#ibcon#ireg 17 cls_cnt 0 2006.286.01:36:11.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:36:11.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:36:11.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:36:11.80#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:36:11.80#ibcon#first serial, iclass 20, count 0 2006.286.01:36:11.80#ibcon#enter sib2, iclass 20, count 0 2006.286.01:36:11.80#ibcon#flushed, iclass 20, count 0 2006.286.01:36:11.80#ibcon#about to write, iclass 20, count 0 2006.286.01:36:11.80#ibcon#wrote, iclass 20, count 0 2006.286.01:36:11.80#ibcon#about to read 3, iclass 20, count 0 2006.286.01:36:11.82#ibcon#read 3, iclass 20, count 0 2006.286.01:36:11.82#ibcon#about to read 4, iclass 20, count 0 2006.286.01:36:11.82#ibcon#read 4, iclass 20, count 0 2006.286.01:36:11.82#ibcon#about to read 5, iclass 20, count 0 2006.286.01:36:11.82#ibcon#read 5, iclass 20, count 0 2006.286.01:36:11.82#ibcon#about to read 6, iclass 20, count 0 2006.286.01:36:11.82#ibcon#read 6, iclass 20, count 0 2006.286.01:36:11.82#ibcon#end of sib2, iclass 20, count 0 2006.286.01:36:11.82#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:36:11.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:36:11.82#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:36:11.82#ibcon#*before write, iclass 20, count 0 2006.286.01:36:11.82#ibcon#enter sib2, iclass 20, count 0 2006.286.01:36:11.82#ibcon#flushed, iclass 20, count 0 2006.286.01:36:11.82#ibcon#about to write, iclass 20, count 0 2006.286.01:36:11.82#ibcon#wrote, iclass 20, count 0 2006.286.01:36:11.82#ibcon#about to read 3, iclass 20, count 0 2006.286.01:36:11.86#ibcon#read 3, iclass 20, count 0 2006.286.01:36:11.86#ibcon#about to read 4, iclass 20, count 0 2006.286.01:36:11.86#ibcon#read 4, iclass 20, count 0 2006.286.01:36:11.86#ibcon#about to read 5, iclass 20, count 0 2006.286.01:36:11.86#ibcon#read 5, iclass 20, count 0 2006.286.01:36:11.86#ibcon#about to read 6, iclass 20, count 0 2006.286.01:36:11.86#ibcon#read 6, iclass 20, count 0 2006.286.01:36:11.86#ibcon#end of sib2, iclass 20, count 0 2006.286.01:36:11.86#ibcon#*after write, iclass 20, count 0 2006.286.01:36:11.86#ibcon#*before return 0, iclass 20, count 0 2006.286.01:36:11.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:36:11.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:36:11.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:36:11.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:36:11.86$vck44/vb=8,4 2006.286.01:36:11.86#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.01:36:11.86#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.01:36:11.86#ibcon#ireg 11 cls_cnt 2 2006.286.01:36:11.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:36:11.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:36:11.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:36:11.92#ibcon#enter wrdev, iclass 22, count 2 2006.286.01:36:11.92#ibcon#first serial, iclass 22, count 2 2006.286.01:36:11.92#ibcon#enter sib2, iclass 22, count 2 2006.286.01:36:11.92#ibcon#flushed, iclass 22, count 2 2006.286.01:36:11.92#ibcon#about to write, iclass 22, count 2 2006.286.01:36:11.92#ibcon#wrote, iclass 22, count 2 2006.286.01:36:11.92#ibcon#about to read 3, iclass 22, count 2 2006.286.01:36:11.94#ibcon#read 3, iclass 22, count 2 2006.286.01:36:11.94#ibcon#about to read 4, iclass 22, count 2 2006.286.01:36:11.94#ibcon#read 4, iclass 22, count 2 2006.286.01:36:11.94#ibcon#about to read 5, iclass 22, count 2 2006.286.01:36:11.94#ibcon#read 5, iclass 22, count 2 2006.286.01:36:11.94#ibcon#about to read 6, iclass 22, count 2 2006.286.01:36:11.94#ibcon#read 6, iclass 22, count 2 2006.286.01:36:11.94#ibcon#end of sib2, iclass 22, count 2 2006.286.01:36:11.94#ibcon#*mode == 0, iclass 22, count 2 2006.286.01:36:11.94#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.01:36:11.94#ibcon#[27=AT08-04\r\n] 2006.286.01:36:11.94#ibcon#*before write, iclass 22, count 2 2006.286.01:36:11.94#ibcon#enter sib2, iclass 22, count 2 2006.286.01:36:11.94#ibcon#flushed, iclass 22, count 2 2006.286.01:36:11.94#ibcon#about to write, iclass 22, count 2 2006.286.01:36:11.94#ibcon#wrote, iclass 22, count 2 2006.286.01:36:11.94#ibcon#about to read 3, iclass 22, count 2 2006.286.01:36:11.97#ibcon#read 3, iclass 22, count 2 2006.286.01:36:11.97#ibcon#about to read 4, iclass 22, count 2 2006.286.01:36:11.97#ibcon#read 4, iclass 22, count 2 2006.286.01:36:11.97#ibcon#about to read 5, iclass 22, count 2 2006.286.01:36:11.97#ibcon#read 5, iclass 22, count 2 2006.286.01:36:11.97#ibcon#about to read 6, iclass 22, count 2 2006.286.01:36:11.97#ibcon#read 6, iclass 22, count 2 2006.286.01:36:11.97#ibcon#end of sib2, iclass 22, count 2 2006.286.01:36:11.97#ibcon#*after write, iclass 22, count 2 2006.286.01:36:11.97#ibcon#*before return 0, iclass 22, count 2 2006.286.01:36:11.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:36:11.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.01:36:11.97#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.01:36:11.97#ibcon#ireg 7 cls_cnt 0 2006.286.01:36:11.97#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:36:12.09#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:36:12.09#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:36:12.09#ibcon#enter wrdev, iclass 22, count 0 2006.286.01:36:12.09#ibcon#first serial, iclass 22, count 0 2006.286.01:36:12.09#ibcon#enter sib2, iclass 22, count 0 2006.286.01:36:12.09#ibcon#flushed, iclass 22, count 0 2006.286.01:36:12.09#ibcon#about to write, iclass 22, count 0 2006.286.01:36:12.09#ibcon#wrote, iclass 22, count 0 2006.286.01:36:12.09#ibcon#about to read 3, iclass 22, count 0 2006.286.01:36:12.11#ibcon#read 3, iclass 22, count 0 2006.286.01:36:12.11#ibcon#about to read 4, iclass 22, count 0 2006.286.01:36:12.11#ibcon#read 4, iclass 22, count 0 2006.286.01:36:12.11#ibcon#about to read 5, iclass 22, count 0 2006.286.01:36:12.11#ibcon#read 5, iclass 22, count 0 2006.286.01:36:12.11#ibcon#about to read 6, iclass 22, count 0 2006.286.01:36:12.11#ibcon#read 6, iclass 22, count 0 2006.286.01:36:12.11#ibcon#end of sib2, iclass 22, count 0 2006.286.01:36:12.11#ibcon#*mode == 0, iclass 22, count 0 2006.286.01:36:12.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.01:36:12.11#ibcon#[27=USB\r\n] 2006.286.01:36:12.11#ibcon#*before write, iclass 22, count 0 2006.286.01:36:12.11#ibcon#enter sib2, iclass 22, count 0 2006.286.01:36:12.11#ibcon#flushed, iclass 22, count 0 2006.286.01:36:12.11#ibcon#about to write, iclass 22, count 0 2006.286.01:36:12.11#ibcon#wrote, iclass 22, count 0 2006.286.01:36:12.11#ibcon#about to read 3, iclass 22, count 0 2006.286.01:36:12.14#ibcon#read 3, iclass 22, count 0 2006.286.01:36:12.14#ibcon#about to read 4, iclass 22, count 0 2006.286.01:36:12.14#ibcon#read 4, iclass 22, count 0 2006.286.01:36:12.14#ibcon#about to read 5, iclass 22, count 0 2006.286.01:36:12.14#ibcon#read 5, iclass 22, count 0 2006.286.01:36:12.14#ibcon#about to read 6, iclass 22, count 0 2006.286.01:36:12.14#ibcon#read 6, iclass 22, count 0 2006.286.01:36:12.14#ibcon#end of sib2, iclass 22, count 0 2006.286.01:36:12.14#ibcon#*after write, iclass 22, count 0 2006.286.01:36:12.14#ibcon#*before return 0, iclass 22, count 0 2006.286.01:36:12.14#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:36:12.14#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.01:36:12.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.01:36:12.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.01:36:12.14$vck44/vabw=wide 2006.286.01:36:12.14#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.01:36:12.14#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.01:36:12.14#ibcon#ireg 8 cls_cnt 0 2006.286.01:36:12.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:36:12.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:36:12.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:36:12.14#ibcon#enter wrdev, iclass 24, count 0 2006.286.01:36:12.14#ibcon#first serial, iclass 24, count 0 2006.286.01:36:12.14#ibcon#enter sib2, iclass 24, count 0 2006.286.01:36:12.14#ibcon#flushed, iclass 24, count 0 2006.286.01:36:12.14#ibcon#about to write, iclass 24, count 0 2006.286.01:36:12.14#ibcon#wrote, iclass 24, count 0 2006.286.01:36:12.14#ibcon#about to read 3, iclass 24, count 0 2006.286.01:36:12.16#ibcon#read 3, iclass 24, count 0 2006.286.01:36:12.16#ibcon#about to read 4, iclass 24, count 0 2006.286.01:36:12.16#ibcon#read 4, iclass 24, count 0 2006.286.01:36:12.16#ibcon#about to read 5, iclass 24, count 0 2006.286.01:36:12.16#ibcon#read 5, iclass 24, count 0 2006.286.01:36:12.16#ibcon#about to read 6, iclass 24, count 0 2006.286.01:36:12.16#ibcon#read 6, iclass 24, count 0 2006.286.01:36:12.16#ibcon#end of sib2, iclass 24, count 0 2006.286.01:36:12.16#ibcon#*mode == 0, iclass 24, count 0 2006.286.01:36:12.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.01:36:12.16#ibcon#[25=BW32\r\n] 2006.286.01:36:12.16#ibcon#*before write, iclass 24, count 0 2006.286.01:36:12.16#ibcon#enter sib2, iclass 24, count 0 2006.286.01:36:12.16#ibcon#flushed, iclass 24, count 0 2006.286.01:36:12.16#ibcon#about to write, iclass 24, count 0 2006.286.01:36:12.16#ibcon#wrote, iclass 24, count 0 2006.286.01:36:12.16#ibcon#about to read 3, iclass 24, count 0 2006.286.01:36:12.19#ibcon#read 3, iclass 24, count 0 2006.286.01:36:12.19#ibcon#about to read 4, iclass 24, count 0 2006.286.01:36:12.19#ibcon#read 4, iclass 24, count 0 2006.286.01:36:12.19#ibcon#about to read 5, iclass 24, count 0 2006.286.01:36:12.19#ibcon#read 5, iclass 24, count 0 2006.286.01:36:12.19#ibcon#about to read 6, iclass 24, count 0 2006.286.01:36:12.19#ibcon#read 6, iclass 24, count 0 2006.286.01:36:12.19#ibcon#end of sib2, iclass 24, count 0 2006.286.01:36:12.19#ibcon#*after write, iclass 24, count 0 2006.286.01:36:12.19#ibcon#*before return 0, iclass 24, count 0 2006.286.01:36:12.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:36:12.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.01:36:12.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.01:36:12.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.01:36:12.19$vck44/vbbw=wide 2006.286.01:36:12.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.01:36:12.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.01:36:12.19#ibcon#ireg 8 cls_cnt 0 2006.286.01:36:12.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:36:12.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:36:12.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:36:12.26#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:36:12.26#ibcon#first serial, iclass 26, count 0 2006.286.01:36:12.26#ibcon#enter sib2, iclass 26, count 0 2006.286.01:36:12.26#ibcon#flushed, iclass 26, count 0 2006.286.01:36:12.26#ibcon#about to write, iclass 26, count 0 2006.286.01:36:12.26#ibcon#wrote, iclass 26, count 0 2006.286.01:36:12.26#ibcon#about to read 3, iclass 26, count 0 2006.286.01:36:12.28#ibcon#read 3, iclass 26, count 0 2006.286.01:36:12.28#ibcon#about to read 4, iclass 26, count 0 2006.286.01:36:12.28#ibcon#read 4, iclass 26, count 0 2006.286.01:36:12.28#ibcon#about to read 5, iclass 26, count 0 2006.286.01:36:12.28#ibcon#read 5, iclass 26, count 0 2006.286.01:36:12.28#ibcon#about to read 6, iclass 26, count 0 2006.286.01:36:12.28#ibcon#read 6, iclass 26, count 0 2006.286.01:36:12.28#ibcon#end of sib2, iclass 26, count 0 2006.286.01:36:12.28#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:36:12.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:36:12.28#ibcon#[27=BW32\r\n] 2006.286.01:36:12.28#ibcon#*before write, iclass 26, count 0 2006.286.01:36:12.28#ibcon#enter sib2, iclass 26, count 0 2006.286.01:36:12.28#ibcon#flushed, iclass 26, count 0 2006.286.01:36:12.28#ibcon#about to write, iclass 26, count 0 2006.286.01:36:12.28#ibcon#wrote, iclass 26, count 0 2006.286.01:36:12.28#ibcon#about to read 3, iclass 26, count 0 2006.286.01:36:12.31#ibcon#read 3, iclass 26, count 0 2006.286.01:36:12.31#ibcon#about to read 4, iclass 26, count 0 2006.286.01:36:12.31#ibcon#read 4, iclass 26, count 0 2006.286.01:36:12.31#ibcon#about to read 5, iclass 26, count 0 2006.286.01:36:12.31#ibcon#read 5, iclass 26, count 0 2006.286.01:36:12.31#ibcon#about to read 6, iclass 26, count 0 2006.286.01:36:12.31#ibcon#read 6, iclass 26, count 0 2006.286.01:36:12.31#ibcon#end of sib2, iclass 26, count 0 2006.286.01:36:12.31#ibcon#*after write, iclass 26, count 0 2006.286.01:36:12.31#ibcon#*before return 0, iclass 26, count 0 2006.286.01:36:12.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:36:12.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:36:12.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:36:12.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:36:12.31$setupk4/ifdk4 2006.286.01:36:12.31$ifdk4/lo= 2006.286.01:36:12.31$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:36:12.31$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:36:12.31$ifdk4/patch= 2006.286.01:36:12.31$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:36:12.31$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:36:12.32$setupk4/!*+20s 2006.286.01:36:13.82#abcon#<5=/04 3.3 6.8 21.10 791016.1\r\n> 2006.286.01:36:13.84#abcon#{5=INTERFACE CLEAR} 2006.286.01:36:13.90#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:36:23.14#trakl#Source acquired 2006.286.01:36:23.99#abcon#<5=/04 3.4 6.8 21.10 791016.1\r\n> 2006.286.01:36:24.01#abcon#{5=INTERFACE CLEAR} 2006.286.01:36:24.07#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:36:25.14#flagr#flagr/antenna,acquired 2006.286.01:36:26.83$setupk4/"tpicd 2006.286.01:36:26.83$setupk4/echo=off 2006.286.01:36:26.83$setupk4/xlog=off 2006.286.01:36:26.83:!2006.286.01:41:01 2006.286.01:41:01.00:preob 2006.286.01:41:02.13/onsource/TRACKING 2006.286.01:41:02.13:!2006.286.01:41:11 2006.286.01:41:11.00:"tape 2006.286.01:41:11.00:"st=record 2006.286.01:41:11.00:data_valid=on 2006.286.01:41:11.00:midob 2006.286.01:41:11.13/onsource/TRACKING 2006.286.01:41:11.13/wx/21.18,1016.1,78 2006.286.01:41:11.27/cable/+6.5026E-03 2006.286.01:41:12.36/va/01,07,usb,yes,41,45 2006.286.01:41:12.36/va/02,06,usb,yes,42,42 2006.286.01:41:12.36/va/03,07,usb,yes,41,43 2006.286.01:41:12.36/va/04,06,usb,yes,43,45 2006.286.01:41:12.36/va/05,03,usb,yes,42,43 2006.286.01:41:12.36/va/06,04,usb,yes,38,38 2006.286.01:41:12.36/va/07,04,usb,yes,39,40 2006.286.01:41:12.36/va/08,03,usb,yes,40,48 2006.286.01:41:12.59/valo/01,524.99,yes,locked 2006.286.01:41:12.59/valo/02,534.99,yes,locked 2006.286.01:41:12.59/valo/03,564.99,yes,locked 2006.286.01:41:12.59/valo/04,624.99,yes,locked 2006.286.01:41:12.59/valo/05,734.99,yes,locked 2006.286.01:41:12.59/valo/06,814.99,yes,locked 2006.286.01:41:12.59/valo/07,864.99,yes,locked 2006.286.01:41:12.59/valo/08,884.99,yes,locked 2006.286.01:41:13.68/vb/01,04,usb,yes,35,33 2006.286.01:41:13.68/vb/02,05,usb,yes,33,33 2006.286.01:41:13.68/vb/03,04,usb,yes,34,38 2006.286.01:41:13.68/vb/04,05,usb,yes,34,33 2006.286.01:41:13.68/vb/05,04,usb,yes,31,34 2006.286.01:41:13.68/vb/06,03,usb,yes,44,40 2006.286.01:41:13.68/vb/07,04,usb,yes,35,36 2006.286.01:41:13.68/vb/08,04,usb,yes,32,36 2006.286.01:41:13.91/vblo/01,629.99,yes,locked 2006.286.01:41:13.91/vblo/02,634.99,yes,locked 2006.286.01:41:13.91/vblo/03,649.99,yes,locked 2006.286.01:41:13.91/vblo/04,679.99,yes,locked 2006.286.01:41:13.91/vblo/05,709.99,yes,locked 2006.286.01:41:13.91/vblo/06,719.99,yes,locked 2006.286.01:41:13.91/vblo/07,734.99,yes,locked 2006.286.01:41:13.91/vblo/08,744.99,yes,locked 2006.286.01:41:14.06/vabw/8 2006.286.01:41:14.21/vbbw/8 2006.286.01:41:14.30/xfe/off,on,12.0 2006.286.01:41:14.67/ifatt/23,28,28,28 2006.286.01:41:15.07/fmout-gps/S +2.73E-07 2006.286.01:41:15.09:!2006.286.01:41:51 2006.286.01:41:51.00:data_valid=off 2006.286.01:41:51.00:"et 2006.286.01:41:51.00:!+3s 2006.286.01:41:54.01:"tape 2006.286.01:41:54.01:postob 2006.286.01:41:54.15/cable/+6.5030E-03 2006.286.01:41:54.15/wx/21.18,1016.1,78 2006.286.01:41:55.07/fmout-gps/S +2.73E-07 2006.286.01:41:55.07:scan_name=286-0142,jd0610,40 2006.286.01:41:55.07:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.286.01:41:56.13#flagr#flagr/antenna,new-source 2006.286.01:41:56.13:checkk5 2006.286.01:41:56.50/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:41:57.11/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:41:57.51/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:41:57.88/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:41:58.28/chk_obsdata//k5ts1/T2860141??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:41:58.73/chk_obsdata//k5ts2/T2860141??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:41:59.16/chk_obsdata//k5ts3/T2860141??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:41:59.51/chk_obsdata//k5ts4/T2860141??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.01:42:00.88/k5log//k5ts1_log_newline 2006.286.01:42:01.78/k5log//k5ts2_log_newline 2006.286.01:42:02.55/k5log//k5ts3_log_newline 2006.286.01:42:03.37/k5log//k5ts4_log_newline 2006.286.01:42:03.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:42:03.39:setupk4=1 2006.286.01:42:03.39$setupk4/echo=on 2006.286.01:42:03.39$setupk4/pcalon 2006.286.01:42:03.39$pcalon/"no phase cal control is implemented here 2006.286.01:42:03.39$setupk4/"tpicd=stop 2006.286.01:42:03.39$setupk4/"rec=synch_on 2006.286.01:42:03.39$setupk4/"rec_mode=128 2006.286.01:42:03.39$setupk4/!* 2006.286.01:42:03.39$setupk4/recpk4 2006.286.01:42:03.39$recpk4/recpatch= 2006.286.01:42:03.40$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:42:03.40$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:42:03.40$setupk4/vck44 2006.286.01:42:03.40$vck44/valo=1,524.99 2006.286.01:42:03.40#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.01:42:03.40#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.01:42:03.40#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:03.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:42:03.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:42:03.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:42:03.40#ibcon#enter wrdev, iclass 27, count 0 2006.286.01:42:03.40#ibcon#first serial, iclass 27, count 0 2006.286.01:42:03.40#ibcon#enter sib2, iclass 27, count 0 2006.286.01:42:03.40#ibcon#flushed, iclass 27, count 0 2006.286.01:42:03.40#ibcon#about to write, iclass 27, count 0 2006.286.01:42:03.40#ibcon#wrote, iclass 27, count 0 2006.286.01:42:03.40#ibcon#about to read 3, iclass 27, count 0 2006.286.01:42:03.41#ibcon#read 3, iclass 27, count 0 2006.286.01:42:03.41#ibcon#about to read 4, iclass 27, count 0 2006.286.01:42:03.41#ibcon#read 4, iclass 27, count 0 2006.286.01:42:03.41#ibcon#about to read 5, iclass 27, count 0 2006.286.01:42:03.41#ibcon#read 5, iclass 27, count 0 2006.286.01:42:03.41#ibcon#about to read 6, iclass 27, count 0 2006.286.01:42:03.41#ibcon#read 6, iclass 27, count 0 2006.286.01:42:03.41#ibcon#end of sib2, iclass 27, count 0 2006.286.01:42:03.41#ibcon#*mode == 0, iclass 27, count 0 2006.286.01:42:03.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.01:42:03.41#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:42:03.41#ibcon#*before write, iclass 27, count 0 2006.286.01:42:03.41#ibcon#enter sib2, iclass 27, count 0 2006.286.01:42:03.41#ibcon#flushed, iclass 27, count 0 2006.286.01:42:03.41#ibcon#about to write, iclass 27, count 0 2006.286.01:42:03.41#ibcon#wrote, iclass 27, count 0 2006.286.01:42:03.41#ibcon#about to read 3, iclass 27, count 0 2006.286.01:42:03.46#ibcon#read 3, iclass 27, count 0 2006.286.01:42:03.46#ibcon#about to read 4, iclass 27, count 0 2006.286.01:42:03.46#ibcon#read 4, iclass 27, count 0 2006.286.01:42:03.46#ibcon#about to read 5, iclass 27, count 0 2006.286.01:42:03.46#ibcon#read 5, iclass 27, count 0 2006.286.01:42:03.46#ibcon#about to read 6, iclass 27, count 0 2006.286.01:42:03.46#ibcon#read 6, iclass 27, count 0 2006.286.01:42:03.46#ibcon#end of sib2, iclass 27, count 0 2006.286.01:42:03.46#ibcon#*after write, iclass 27, count 0 2006.286.01:42:03.46#ibcon#*before return 0, iclass 27, count 0 2006.286.01:42:03.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:42:03.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:42:03.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.01:42:03.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.01:42:03.46$vck44/va=1,7 2006.286.01:42:03.46#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.01:42:03.46#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.01:42:03.46#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:03.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:42:03.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:42:03.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:42:03.46#ibcon#enter wrdev, iclass 29, count 2 2006.286.01:42:03.46#ibcon#first serial, iclass 29, count 2 2006.286.01:42:03.46#ibcon#enter sib2, iclass 29, count 2 2006.286.01:42:03.46#ibcon#flushed, iclass 29, count 2 2006.286.01:42:03.46#ibcon#about to write, iclass 29, count 2 2006.286.01:42:03.46#ibcon#wrote, iclass 29, count 2 2006.286.01:42:03.46#ibcon#about to read 3, iclass 29, count 2 2006.286.01:42:03.48#ibcon#read 3, iclass 29, count 2 2006.286.01:42:03.48#ibcon#about to read 4, iclass 29, count 2 2006.286.01:42:03.48#ibcon#read 4, iclass 29, count 2 2006.286.01:42:03.48#ibcon#about to read 5, iclass 29, count 2 2006.286.01:42:03.48#ibcon#read 5, iclass 29, count 2 2006.286.01:42:03.48#ibcon#about to read 6, iclass 29, count 2 2006.286.01:42:03.48#ibcon#read 6, iclass 29, count 2 2006.286.01:42:03.48#ibcon#end of sib2, iclass 29, count 2 2006.286.01:42:03.48#ibcon#*mode == 0, iclass 29, count 2 2006.286.01:42:03.48#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.01:42:03.48#ibcon#[25=AT01-07\r\n] 2006.286.01:42:03.48#ibcon#*before write, iclass 29, count 2 2006.286.01:42:03.48#ibcon#enter sib2, iclass 29, count 2 2006.286.01:42:03.48#ibcon#flushed, iclass 29, count 2 2006.286.01:42:03.48#ibcon#about to write, iclass 29, count 2 2006.286.01:42:03.48#ibcon#wrote, iclass 29, count 2 2006.286.01:42:03.48#ibcon#about to read 3, iclass 29, count 2 2006.286.01:42:03.51#ibcon#read 3, iclass 29, count 2 2006.286.01:42:03.51#ibcon#about to read 4, iclass 29, count 2 2006.286.01:42:03.51#ibcon#read 4, iclass 29, count 2 2006.286.01:42:03.51#ibcon#about to read 5, iclass 29, count 2 2006.286.01:42:03.51#ibcon#read 5, iclass 29, count 2 2006.286.01:42:03.51#ibcon#about to read 6, iclass 29, count 2 2006.286.01:42:03.51#ibcon#read 6, iclass 29, count 2 2006.286.01:42:03.51#ibcon#end of sib2, iclass 29, count 2 2006.286.01:42:03.51#ibcon#*after write, iclass 29, count 2 2006.286.01:42:03.51#ibcon#*before return 0, iclass 29, count 2 2006.286.01:42:03.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:42:03.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:42:03.51#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.01:42:03.51#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:03.51#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:42:03.63#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:42:03.63#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:42:03.63#ibcon#enter wrdev, iclass 29, count 0 2006.286.01:42:03.63#ibcon#first serial, iclass 29, count 0 2006.286.01:42:03.63#ibcon#enter sib2, iclass 29, count 0 2006.286.01:42:03.63#ibcon#flushed, iclass 29, count 0 2006.286.01:42:03.63#ibcon#about to write, iclass 29, count 0 2006.286.01:42:03.63#ibcon#wrote, iclass 29, count 0 2006.286.01:42:03.63#ibcon#about to read 3, iclass 29, count 0 2006.286.01:42:03.65#ibcon#read 3, iclass 29, count 0 2006.286.01:42:03.65#ibcon#about to read 4, iclass 29, count 0 2006.286.01:42:03.65#ibcon#read 4, iclass 29, count 0 2006.286.01:42:03.65#ibcon#about to read 5, iclass 29, count 0 2006.286.01:42:03.65#ibcon#read 5, iclass 29, count 0 2006.286.01:42:03.65#ibcon#about to read 6, iclass 29, count 0 2006.286.01:42:03.65#ibcon#read 6, iclass 29, count 0 2006.286.01:42:03.65#ibcon#end of sib2, iclass 29, count 0 2006.286.01:42:03.65#ibcon#*mode == 0, iclass 29, count 0 2006.286.01:42:03.65#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.01:42:03.65#ibcon#[25=USB\r\n] 2006.286.01:42:03.65#ibcon#*before write, iclass 29, count 0 2006.286.01:42:03.65#ibcon#enter sib2, iclass 29, count 0 2006.286.01:42:03.65#ibcon#flushed, iclass 29, count 0 2006.286.01:42:03.65#ibcon#about to write, iclass 29, count 0 2006.286.01:42:03.65#ibcon#wrote, iclass 29, count 0 2006.286.01:42:03.65#ibcon#about to read 3, iclass 29, count 0 2006.286.01:42:03.68#ibcon#read 3, iclass 29, count 0 2006.286.01:42:03.68#ibcon#about to read 4, iclass 29, count 0 2006.286.01:42:03.68#ibcon#read 4, iclass 29, count 0 2006.286.01:42:03.68#ibcon#about to read 5, iclass 29, count 0 2006.286.01:42:03.68#ibcon#read 5, iclass 29, count 0 2006.286.01:42:03.68#ibcon#about to read 6, iclass 29, count 0 2006.286.01:42:03.68#ibcon#read 6, iclass 29, count 0 2006.286.01:42:03.68#ibcon#end of sib2, iclass 29, count 0 2006.286.01:42:03.68#ibcon#*after write, iclass 29, count 0 2006.286.01:42:03.68#ibcon#*before return 0, iclass 29, count 0 2006.286.01:42:03.68#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:42:03.68#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:42:03.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.01:42:03.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.01:42:03.68$vck44/valo=2,534.99 2006.286.01:42:03.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.01:42:03.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.01:42:03.68#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:03.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:42:03.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:42:03.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:42:03.68#ibcon#enter wrdev, iclass 31, count 0 2006.286.01:42:03.68#ibcon#first serial, iclass 31, count 0 2006.286.01:42:03.68#ibcon#enter sib2, iclass 31, count 0 2006.286.01:42:03.68#ibcon#flushed, iclass 31, count 0 2006.286.01:42:03.68#ibcon#about to write, iclass 31, count 0 2006.286.01:42:03.68#ibcon#wrote, iclass 31, count 0 2006.286.01:42:03.68#ibcon#about to read 3, iclass 31, count 0 2006.286.01:42:03.70#ibcon#read 3, iclass 31, count 0 2006.286.01:42:03.70#ibcon#about to read 4, iclass 31, count 0 2006.286.01:42:03.70#ibcon#read 4, iclass 31, count 0 2006.286.01:42:03.70#ibcon#about to read 5, iclass 31, count 0 2006.286.01:42:03.70#ibcon#read 5, iclass 31, count 0 2006.286.01:42:03.70#ibcon#about to read 6, iclass 31, count 0 2006.286.01:42:03.70#ibcon#read 6, iclass 31, count 0 2006.286.01:42:03.70#ibcon#end of sib2, iclass 31, count 0 2006.286.01:42:03.70#ibcon#*mode == 0, iclass 31, count 0 2006.286.01:42:03.70#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.01:42:03.70#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:42:03.70#ibcon#*before write, iclass 31, count 0 2006.286.01:42:03.70#ibcon#enter sib2, iclass 31, count 0 2006.286.01:42:03.70#ibcon#flushed, iclass 31, count 0 2006.286.01:42:03.70#ibcon#about to write, iclass 31, count 0 2006.286.01:42:03.70#ibcon#wrote, iclass 31, count 0 2006.286.01:42:03.70#ibcon#about to read 3, iclass 31, count 0 2006.286.01:42:03.74#ibcon#read 3, iclass 31, count 0 2006.286.01:42:03.74#ibcon#about to read 4, iclass 31, count 0 2006.286.01:42:03.74#ibcon#read 4, iclass 31, count 0 2006.286.01:42:03.74#ibcon#about to read 5, iclass 31, count 0 2006.286.01:42:03.74#ibcon#read 5, iclass 31, count 0 2006.286.01:42:03.74#ibcon#about to read 6, iclass 31, count 0 2006.286.01:42:03.74#ibcon#read 6, iclass 31, count 0 2006.286.01:42:03.74#ibcon#end of sib2, iclass 31, count 0 2006.286.01:42:03.74#ibcon#*after write, iclass 31, count 0 2006.286.01:42:03.74#ibcon#*before return 0, iclass 31, count 0 2006.286.01:42:03.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:42:03.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:42:03.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.01:42:03.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.01:42:03.74$vck44/va=2,6 2006.286.01:42:03.74#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.01:42:03.74#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.01:42:03.74#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:03.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:42:03.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:42:03.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:42:03.80#ibcon#enter wrdev, iclass 33, count 2 2006.286.01:42:03.80#ibcon#first serial, iclass 33, count 2 2006.286.01:42:03.80#ibcon#enter sib2, iclass 33, count 2 2006.286.01:42:03.80#ibcon#flushed, iclass 33, count 2 2006.286.01:42:03.80#ibcon#about to write, iclass 33, count 2 2006.286.01:42:03.80#ibcon#wrote, iclass 33, count 2 2006.286.01:42:03.80#ibcon#about to read 3, iclass 33, count 2 2006.286.01:42:03.82#ibcon#read 3, iclass 33, count 2 2006.286.01:42:03.82#ibcon#about to read 4, iclass 33, count 2 2006.286.01:42:03.82#ibcon#read 4, iclass 33, count 2 2006.286.01:42:03.82#ibcon#about to read 5, iclass 33, count 2 2006.286.01:42:03.82#ibcon#read 5, iclass 33, count 2 2006.286.01:42:03.82#ibcon#about to read 6, iclass 33, count 2 2006.286.01:42:03.82#ibcon#read 6, iclass 33, count 2 2006.286.01:42:03.82#ibcon#end of sib2, iclass 33, count 2 2006.286.01:42:03.82#ibcon#*mode == 0, iclass 33, count 2 2006.286.01:42:03.82#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.01:42:03.82#ibcon#[25=AT02-06\r\n] 2006.286.01:42:03.82#ibcon#*before write, iclass 33, count 2 2006.286.01:42:03.82#ibcon#enter sib2, iclass 33, count 2 2006.286.01:42:03.82#ibcon#flushed, iclass 33, count 2 2006.286.01:42:03.82#ibcon#about to write, iclass 33, count 2 2006.286.01:42:03.82#ibcon#wrote, iclass 33, count 2 2006.286.01:42:03.82#ibcon#about to read 3, iclass 33, count 2 2006.286.01:42:03.85#ibcon#read 3, iclass 33, count 2 2006.286.01:42:03.85#ibcon#about to read 4, iclass 33, count 2 2006.286.01:42:03.85#ibcon#read 4, iclass 33, count 2 2006.286.01:42:03.85#ibcon#about to read 5, iclass 33, count 2 2006.286.01:42:03.85#ibcon#read 5, iclass 33, count 2 2006.286.01:42:03.85#ibcon#about to read 6, iclass 33, count 2 2006.286.01:42:03.85#ibcon#read 6, iclass 33, count 2 2006.286.01:42:03.85#ibcon#end of sib2, iclass 33, count 2 2006.286.01:42:03.85#ibcon#*after write, iclass 33, count 2 2006.286.01:42:03.85#ibcon#*before return 0, iclass 33, count 2 2006.286.01:42:03.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:42:03.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:42:03.85#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.01:42:03.85#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:03.85#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:42:03.97#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:42:03.97#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:42:03.97#ibcon#enter wrdev, iclass 33, count 0 2006.286.01:42:03.97#ibcon#first serial, iclass 33, count 0 2006.286.01:42:03.97#ibcon#enter sib2, iclass 33, count 0 2006.286.01:42:03.97#ibcon#flushed, iclass 33, count 0 2006.286.01:42:03.97#ibcon#about to write, iclass 33, count 0 2006.286.01:42:03.97#ibcon#wrote, iclass 33, count 0 2006.286.01:42:03.97#ibcon#about to read 3, iclass 33, count 0 2006.286.01:42:03.99#ibcon#read 3, iclass 33, count 0 2006.286.01:42:03.99#ibcon#about to read 4, iclass 33, count 0 2006.286.01:42:03.99#ibcon#read 4, iclass 33, count 0 2006.286.01:42:03.99#ibcon#about to read 5, iclass 33, count 0 2006.286.01:42:03.99#ibcon#read 5, iclass 33, count 0 2006.286.01:42:03.99#ibcon#about to read 6, iclass 33, count 0 2006.286.01:42:03.99#ibcon#read 6, iclass 33, count 0 2006.286.01:42:03.99#ibcon#end of sib2, iclass 33, count 0 2006.286.01:42:03.99#ibcon#*mode == 0, iclass 33, count 0 2006.286.01:42:03.99#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.01:42:03.99#ibcon#[25=USB\r\n] 2006.286.01:42:03.99#ibcon#*before write, iclass 33, count 0 2006.286.01:42:03.99#ibcon#enter sib2, iclass 33, count 0 2006.286.01:42:03.99#ibcon#flushed, iclass 33, count 0 2006.286.01:42:03.99#ibcon#about to write, iclass 33, count 0 2006.286.01:42:03.99#ibcon#wrote, iclass 33, count 0 2006.286.01:42:03.99#ibcon#about to read 3, iclass 33, count 0 2006.286.01:42:04.02#ibcon#read 3, iclass 33, count 0 2006.286.01:42:04.02#ibcon#about to read 4, iclass 33, count 0 2006.286.01:42:04.02#ibcon#read 4, iclass 33, count 0 2006.286.01:42:04.02#ibcon#about to read 5, iclass 33, count 0 2006.286.01:42:04.02#ibcon#read 5, iclass 33, count 0 2006.286.01:42:04.02#ibcon#about to read 6, iclass 33, count 0 2006.286.01:42:04.02#ibcon#read 6, iclass 33, count 0 2006.286.01:42:04.02#ibcon#end of sib2, iclass 33, count 0 2006.286.01:42:04.02#ibcon#*after write, iclass 33, count 0 2006.286.01:42:04.02#ibcon#*before return 0, iclass 33, count 0 2006.286.01:42:04.02#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:42:04.02#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:42:04.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.01:42:04.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.01:42:04.02$vck44/valo=3,564.99 2006.286.01:42:04.02#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.01:42:04.02#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.01:42:04.02#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:04.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:42:04.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:42:04.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:42:04.02#ibcon#enter wrdev, iclass 35, count 0 2006.286.01:42:04.02#ibcon#first serial, iclass 35, count 0 2006.286.01:42:04.02#ibcon#enter sib2, iclass 35, count 0 2006.286.01:42:04.02#ibcon#flushed, iclass 35, count 0 2006.286.01:42:04.02#ibcon#about to write, iclass 35, count 0 2006.286.01:42:04.02#ibcon#wrote, iclass 35, count 0 2006.286.01:42:04.02#ibcon#about to read 3, iclass 35, count 0 2006.286.01:42:04.04#ibcon#read 3, iclass 35, count 0 2006.286.01:42:04.04#ibcon#about to read 4, iclass 35, count 0 2006.286.01:42:04.04#ibcon#read 4, iclass 35, count 0 2006.286.01:42:04.04#ibcon#about to read 5, iclass 35, count 0 2006.286.01:42:04.04#ibcon#read 5, iclass 35, count 0 2006.286.01:42:04.04#ibcon#about to read 6, iclass 35, count 0 2006.286.01:42:04.04#ibcon#read 6, iclass 35, count 0 2006.286.01:42:04.04#ibcon#end of sib2, iclass 35, count 0 2006.286.01:42:04.04#ibcon#*mode == 0, iclass 35, count 0 2006.286.01:42:04.04#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.01:42:04.04#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:42:04.04#ibcon#*before write, iclass 35, count 0 2006.286.01:42:04.04#ibcon#enter sib2, iclass 35, count 0 2006.286.01:42:04.04#ibcon#flushed, iclass 35, count 0 2006.286.01:42:04.04#ibcon#about to write, iclass 35, count 0 2006.286.01:42:04.04#ibcon#wrote, iclass 35, count 0 2006.286.01:42:04.04#ibcon#about to read 3, iclass 35, count 0 2006.286.01:42:04.08#ibcon#read 3, iclass 35, count 0 2006.286.01:42:04.08#ibcon#about to read 4, iclass 35, count 0 2006.286.01:42:04.08#ibcon#read 4, iclass 35, count 0 2006.286.01:42:04.08#ibcon#about to read 5, iclass 35, count 0 2006.286.01:42:04.08#ibcon#read 5, iclass 35, count 0 2006.286.01:42:04.08#ibcon#about to read 6, iclass 35, count 0 2006.286.01:42:04.08#ibcon#read 6, iclass 35, count 0 2006.286.01:42:04.08#ibcon#end of sib2, iclass 35, count 0 2006.286.01:42:04.08#ibcon#*after write, iclass 35, count 0 2006.286.01:42:04.08#ibcon#*before return 0, iclass 35, count 0 2006.286.01:42:04.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:42:04.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:42:04.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.01:42:04.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.01:42:04.08$vck44/va=3,7 2006.286.01:42:04.08#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.01:42:04.08#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.01:42:04.08#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:04.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:42:04.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:42:04.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:42:04.14#ibcon#enter wrdev, iclass 37, count 2 2006.286.01:42:04.14#ibcon#first serial, iclass 37, count 2 2006.286.01:42:04.14#ibcon#enter sib2, iclass 37, count 2 2006.286.01:42:04.14#ibcon#flushed, iclass 37, count 2 2006.286.01:42:04.14#ibcon#about to write, iclass 37, count 2 2006.286.01:42:04.14#ibcon#wrote, iclass 37, count 2 2006.286.01:42:04.14#ibcon#about to read 3, iclass 37, count 2 2006.286.01:42:04.16#ibcon#read 3, iclass 37, count 2 2006.286.01:42:04.16#ibcon#about to read 4, iclass 37, count 2 2006.286.01:42:04.16#ibcon#read 4, iclass 37, count 2 2006.286.01:42:04.16#ibcon#about to read 5, iclass 37, count 2 2006.286.01:42:04.16#ibcon#read 5, iclass 37, count 2 2006.286.01:42:04.16#ibcon#about to read 6, iclass 37, count 2 2006.286.01:42:04.16#ibcon#read 6, iclass 37, count 2 2006.286.01:42:04.16#ibcon#end of sib2, iclass 37, count 2 2006.286.01:42:04.16#ibcon#*mode == 0, iclass 37, count 2 2006.286.01:42:04.16#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.01:42:04.16#ibcon#[25=AT03-07\r\n] 2006.286.01:42:04.16#ibcon#*before write, iclass 37, count 2 2006.286.01:42:04.16#ibcon#enter sib2, iclass 37, count 2 2006.286.01:42:04.16#ibcon#flushed, iclass 37, count 2 2006.286.01:42:04.16#ibcon#about to write, iclass 37, count 2 2006.286.01:42:04.16#ibcon#wrote, iclass 37, count 2 2006.286.01:42:04.16#ibcon#about to read 3, iclass 37, count 2 2006.286.01:42:04.19#ibcon#read 3, iclass 37, count 2 2006.286.01:42:04.19#ibcon#about to read 4, iclass 37, count 2 2006.286.01:42:04.19#ibcon#read 4, iclass 37, count 2 2006.286.01:42:04.19#ibcon#about to read 5, iclass 37, count 2 2006.286.01:42:04.19#ibcon#read 5, iclass 37, count 2 2006.286.01:42:04.19#ibcon#about to read 6, iclass 37, count 2 2006.286.01:42:04.19#ibcon#read 6, iclass 37, count 2 2006.286.01:42:04.19#ibcon#end of sib2, iclass 37, count 2 2006.286.01:42:04.19#ibcon#*after write, iclass 37, count 2 2006.286.01:42:04.19#ibcon#*before return 0, iclass 37, count 2 2006.286.01:42:04.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:42:04.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:42:04.19#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.01:42:04.19#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:04.19#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:42:04.31#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:42:04.31#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:42:04.31#ibcon#enter wrdev, iclass 37, count 0 2006.286.01:42:04.31#ibcon#first serial, iclass 37, count 0 2006.286.01:42:04.31#ibcon#enter sib2, iclass 37, count 0 2006.286.01:42:04.31#ibcon#flushed, iclass 37, count 0 2006.286.01:42:04.31#ibcon#about to write, iclass 37, count 0 2006.286.01:42:04.31#ibcon#wrote, iclass 37, count 0 2006.286.01:42:04.31#ibcon#about to read 3, iclass 37, count 0 2006.286.01:42:04.33#ibcon#read 3, iclass 37, count 0 2006.286.01:42:04.33#ibcon#about to read 4, iclass 37, count 0 2006.286.01:42:04.33#ibcon#read 4, iclass 37, count 0 2006.286.01:42:04.33#ibcon#about to read 5, iclass 37, count 0 2006.286.01:42:04.33#ibcon#read 5, iclass 37, count 0 2006.286.01:42:04.33#ibcon#about to read 6, iclass 37, count 0 2006.286.01:42:04.33#ibcon#read 6, iclass 37, count 0 2006.286.01:42:04.33#ibcon#end of sib2, iclass 37, count 0 2006.286.01:42:04.33#ibcon#*mode == 0, iclass 37, count 0 2006.286.01:42:04.33#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.01:42:04.33#ibcon#[25=USB\r\n] 2006.286.01:42:04.33#ibcon#*before write, iclass 37, count 0 2006.286.01:42:04.33#ibcon#enter sib2, iclass 37, count 0 2006.286.01:42:04.33#ibcon#flushed, iclass 37, count 0 2006.286.01:42:04.33#ibcon#about to write, iclass 37, count 0 2006.286.01:42:04.33#ibcon#wrote, iclass 37, count 0 2006.286.01:42:04.33#ibcon#about to read 3, iclass 37, count 0 2006.286.01:42:04.36#ibcon#read 3, iclass 37, count 0 2006.286.01:42:04.36#ibcon#about to read 4, iclass 37, count 0 2006.286.01:42:04.36#ibcon#read 4, iclass 37, count 0 2006.286.01:42:04.36#ibcon#about to read 5, iclass 37, count 0 2006.286.01:42:04.36#ibcon#read 5, iclass 37, count 0 2006.286.01:42:04.36#ibcon#about to read 6, iclass 37, count 0 2006.286.01:42:04.36#ibcon#read 6, iclass 37, count 0 2006.286.01:42:04.36#ibcon#end of sib2, iclass 37, count 0 2006.286.01:42:04.36#ibcon#*after write, iclass 37, count 0 2006.286.01:42:04.36#ibcon#*before return 0, iclass 37, count 0 2006.286.01:42:04.36#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:42:04.36#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:42:04.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.01:42:04.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.01:42:04.36$vck44/valo=4,624.99 2006.286.01:42:04.36#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.01:42:04.36#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.01:42:04.36#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:04.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:42:04.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:42:04.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:42:04.36#ibcon#enter wrdev, iclass 39, count 0 2006.286.01:42:04.36#ibcon#first serial, iclass 39, count 0 2006.286.01:42:04.36#ibcon#enter sib2, iclass 39, count 0 2006.286.01:42:04.36#ibcon#flushed, iclass 39, count 0 2006.286.01:42:04.36#ibcon#about to write, iclass 39, count 0 2006.286.01:42:04.36#ibcon#wrote, iclass 39, count 0 2006.286.01:42:04.36#ibcon#about to read 3, iclass 39, count 0 2006.286.01:42:04.38#ibcon#read 3, iclass 39, count 0 2006.286.01:42:04.38#ibcon#about to read 4, iclass 39, count 0 2006.286.01:42:04.38#ibcon#read 4, iclass 39, count 0 2006.286.01:42:04.38#ibcon#about to read 5, iclass 39, count 0 2006.286.01:42:04.38#ibcon#read 5, iclass 39, count 0 2006.286.01:42:04.38#ibcon#about to read 6, iclass 39, count 0 2006.286.01:42:04.38#ibcon#read 6, iclass 39, count 0 2006.286.01:42:04.38#ibcon#end of sib2, iclass 39, count 0 2006.286.01:42:04.38#ibcon#*mode == 0, iclass 39, count 0 2006.286.01:42:04.38#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.01:42:04.38#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:42:04.38#ibcon#*before write, iclass 39, count 0 2006.286.01:42:04.38#ibcon#enter sib2, iclass 39, count 0 2006.286.01:42:04.38#ibcon#flushed, iclass 39, count 0 2006.286.01:42:04.38#ibcon#about to write, iclass 39, count 0 2006.286.01:42:04.38#ibcon#wrote, iclass 39, count 0 2006.286.01:42:04.38#ibcon#about to read 3, iclass 39, count 0 2006.286.01:42:04.42#ibcon#read 3, iclass 39, count 0 2006.286.01:42:04.42#ibcon#about to read 4, iclass 39, count 0 2006.286.01:42:04.42#ibcon#read 4, iclass 39, count 0 2006.286.01:42:04.42#ibcon#about to read 5, iclass 39, count 0 2006.286.01:42:04.42#ibcon#read 5, iclass 39, count 0 2006.286.01:42:04.42#ibcon#about to read 6, iclass 39, count 0 2006.286.01:42:04.42#ibcon#read 6, iclass 39, count 0 2006.286.01:42:04.42#ibcon#end of sib2, iclass 39, count 0 2006.286.01:42:04.42#ibcon#*after write, iclass 39, count 0 2006.286.01:42:04.42#ibcon#*before return 0, iclass 39, count 0 2006.286.01:42:04.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:42:04.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:42:04.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.01:42:04.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.01:42:04.42$vck44/va=4,6 2006.286.01:42:04.42#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.01:42:04.42#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.01:42:04.42#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:04.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:42:04.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:42:04.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:42:04.48#ibcon#enter wrdev, iclass 3, count 2 2006.286.01:42:04.48#ibcon#first serial, iclass 3, count 2 2006.286.01:42:04.48#ibcon#enter sib2, iclass 3, count 2 2006.286.01:42:04.48#ibcon#flushed, iclass 3, count 2 2006.286.01:42:04.48#ibcon#about to write, iclass 3, count 2 2006.286.01:42:04.48#ibcon#wrote, iclass 3, count 2 2006.286.01:42:04.48#ibcon#about to read 3, iclass 3, count 2 2006.286.01:42:04.50#ibcon#read 3, iclass 3, count 2 2006.286.01:42:04.50#ibcon#about to read 4, iclass 3, count 2 2006.286.01:42:04.50#ibcon#read 4, iclass 3, count 2 2006.286.01:42:04.50#ibcon#about to read 5, iclass 3, count 2 2006.286.01:42:04.50#ibcon#read 5, iclass 3, count 2 2006.286.01:42:04.50#ibcon#about to read 6, iclass 3, count 2 2006.286.01:42:04.50#ibcon#read 6, iclass 3, count 2 2006.286.01:42:04.50#ibcon#end of sib2, iclass 3, count 2 2006.286.01:42:04.50#ibcon#*mode == 0, iclass 3, count 2 2006.286.01:42:04.50#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.01:42:04.50#ibcon#[25=AT04-06\r\n] 2006.286.01:42:04.50#ibcon#*before write, iclass 3, count 2 2006.286.01:42:04.50#ibcon#enter sib2, iclass 3, count 2 2006.286.01:42:04.50#ibcon#flushed, iclass 3, count 2 2006.286.01:42:04.50#ibcon#about to write, iclass 3, count 2 2006.286.01:42:04.50#ibcon#wrote, iclass 3, count 2 2006.286.01:42:04.50#ibcon#about to read 3, iclass 3, count 2 2006.286.01:42:04.53#ibcon#read 3, iclass 3, count 2 2006.286.01:42:04.53#ibcon#about to read 4, iclass 3, count 2 2006.286.01:42:04.53#ibcon#read 4, iclass 3, count 2 2006.286.01:42:04.53#ibcon#about to read 5, iclass 3, count 2 2006.286.01:42:04.53#ibcon#read 5, iclass 3, count 2 2006.286.01:42:04.53#ibcon#about to read 6, iclass 3, count 2 2006.286.01:42:04.53#ibcon#read 6, iclass 3, count 2 2006.286.01:42:04.53#ibcon#end of sib2, iclass 3, count 2 2006.286.01:42:04.53#ibcon#*after write, iclass 3, count 2 2006.286.01:42:04.53#ibcon#*before return 0, iclass 3, count 2 2006.286.01:42:04.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:42:04.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:42:04.53#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.01:42:04.53#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:04.53#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:42:04.65#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:42:04.65#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:42:04.65#ibcon#enter wrdev, iclass 3, count 0 2006.286.01:42:04.65#ibcon#first serial, iclass 3, count 0 2006.286.01:42:04.65#ibcon#enter sib2, iclass 3, count 0 2006.286.01:42:04.65#ibcon#flushed, iclass 3, count 0 2006.286.01:42:04.65#ibcon#about to write, iclass 3, count 0 2006.286.01:42:04.65#ibcon#wrote, iclass 3, count 0 2006.286.01:42:04.65#ibcon#about to read 3, iclass 3, count 0 2006.286.01:42:04.67#ibcon#read 3, iclass 3, count 0 2006.286.01:42:04.67#ibcon#about to read 4, iclass 3, count 0 2006.286.01:42:04.67#ibcon#read 4, iclass 3, count 0 2006.286.01:42:04.67#ibcon#about to read 5, iclass 3, count 0 2006.286.01:42:04.67#ibcon#read 5, iclass 3, count 0 2006.286.01:42:04.67#ibcon#about to read 6, iclass 3, count 0 2006.286.01:42:04.67#ibcon#read 6, iclass 3, count 0 2006.286.01:42:04.67#ibcon#end of sib2, iclass 3, count 0 2006.286.01:42:04.67#ibcon#*mode == 0, iclass 3, count 0 2006.286.01:42:04.67#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.01:42:04.67#ibcon#[25=USB\r\n] 2006.286.01:42:04.67#ibcon#*before write, iclass 3, count 0 2006.286.01:42:04.67#ibcon#enter sib2, iclass 3, count 0 2006.286.01:42:04.67#ibcon#flushed, iclass 3, count 0 2006.286.01:42:04.67#ibcon#about to write, iclass 3, count 0 2006.286.01:42:04.67#ibcon#wrote, iclass 3, count 0 2006.286.01:42:04.67#ibcon#about to read 3, iclass 3, count 0 2006.286.01:42:04.70#ibcon#read 3, iclass 3, count 0 2006.286.01:42:04.70#ibcon#about to read 4, iclass 3, count 0 2006.286.01:42:04.70#ibcon#read 4, iclass 3, count 0 2006.286.01:42:04.70#ibcon#about to read 5, iclass 3, count 0 2006.286.01:42:04.70#ibcon#read 5, iclass 3, count 0 2006.286.01:42:04.70#ibcon#about to read 6, iclass 3, count 0 2006.286.01:42:04.70#ibcon#read 6, iclass 3, count 0 2006.286.01:42:04.70#ibcon#end of sib2, iclass 3, count 0 2006.286.01:42:04.70#ibcon#*after write, iclass 3, count 0 2006.286.01:42:04.70#ibcon#*before return 0, iclass 3, count 0 2006.286.01:42:04.70#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:42:04.70#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:42:04.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.01:42:04.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.01:42:04.70$vck44/valo=5,734.99 2006.286.01:42:04.70#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.01:42:04.70#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.01:42:04.70#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:04.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:42:04.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:42:04.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:42:04.70#ibcon#enter wrdev, iclass 5, count 0 2006.286.01:42:04.70#ibcon#first serial, iclass 5, count 0 2006.286.01:42:04.70#ibcon#enter sib2, iclass 5, count 0 2006.286.01:42:04.70#ibcon#flushed, iclass 5, count 0 2006.286.01:42:04.70#ibcon#about to write, iclass 5, count 0 2006.286.01:42:04.70#ibcon#wrote, iclass 5, count 0 2006.286.01:42:04.70#ibcon#about to read 3, iclass 5, count 0 2006.286.01:42:04.72#ibcon#read 3, iclass 5, count 0 2006.286.01:42:04.72#ibcon#about to read 4, iclass 5, count 0 2006.286.01:42:04.72#ibcon#read 4, iclass 5, count 0 2006.286.01:42:04.72#ibcon#about to read 5, iclass 5, count 0 2006.286.01:42:04.72#ibcon#read 5, iclass 5, count 0 2006.286.01:42:04.72#ibcon#about to read 6, iclass 5, count 0 2006.286.01:42:04.72#ibcon#read 6, iclass 5, count 0 2006.286.01:42:04.72#ibcon#end of sib2, iclass 5, count 0 2006.286.01:42:04.72#ibcon#*mode == 0, iclass 5, count 0 2006.286.01:42:04.72#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.01:42:04.72#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:42:04.72#ibcon#*before write, iclass 5, count 0 2006.286.01:42:04.72#ibcon#enter sib2, iclass 5, count 0 2006.286.01:42:04.72#ibcon#flushed, iclass 5, count 0 2006.286.01:42:04.72#ibcon#about to write, iclass 5, count 0 2006.286.01:42:04.72#ibcon#wrote, iclass 5, count 0 2006.286.01:42:04.72#ibcon#about to read 3, iclass 5, count 0 2006.286.01:42:04.76#ibcon#read 3, iclass 5, count 0 2006.286.01:42:04.76#ibcon#about to read 4, iclass 5, count 0 2006.286.01:42:04.76#ibcon#read 4, iclass 5, count 0 2006.286.01:42:04.76#ibcon#about to read 5, iclass 5, count 0 2006.286.01:42:04.76#ibcon#read 5, iclass 5, count 0 2006.286.01:42:04.76#ibcon#about to read 6, iclass 5, count 0 2006.286.01:42:04.76#ibcon#read 6, iclass 5, count 0 2006.286.01:42:04.76#ibcon#end of sib2, iclass 5, count 0 2006.286.01:42:04.76#ibcon#*after write, iclass 5, count 0 2006.286.01:42:04.76#ibcon#*before return 0, iclass 5, count 0 2006.286.01:42:04.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:42:04.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:42:04.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.01:42:04.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.01:42:04.76$vck44/va=5,3 2006.286.01:42:04.76#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.01:42:04.76#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.01:42:04.76#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:04.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:42:04.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:42:04.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:42:04.82#ibcon#enter wrdev, iclass 7, count 2 2006.286.01:42:04.82#ibcon#first serial, iclass 7, count 2 2006.286.01:42:04.82#ibcon#enter sib2, iclass 7, count 2 2006.286.01:42:04.82#ibcon#flushed, iclass 7, count 2 2006.286.01:42:04.82#ibcon#about to write, iclass 7, count 2 2006.286.01:42:04.82#ibcon#wrote, iclass 7, count 2 2006.286.01:42:04.82#ibcon#about to read 3, iclass 7, count 2 2006.286.01:42:04.84#ibcon#read 3, iclass 7, count 2 2006.286.01:42:04.84#ibcon#about to read 4, iclass 7, count 2 2006.286.01:42:04.84#ibcon#read 4, iclass 7, count 2 2006.286.01:42:04.84#ibcon#about to read 5, iclass 7, count 2 2006.286.01:42:04.84#ibcon#read 5, iclass 7, count 2 2006.286.01:42:04.84#ibcon#about to read 6, iclass 7, count 2 2006.286.01:42:04.84#ibcon#read 6, iclass 7, count 2 2006.286.01:42:04.84#ibcon#end of sib2, iclass 7, count 2 2006.286.01:42:04.84#ibcon#*mode == 0, iclass 7, count 2 2006.286.01:42:04.84#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.01:42:04.84#ibcon#[25=AT05-03\r\n] 2006.286.01:42:04.84#ibcon#*before write, iclass 7, count 2 2006.286.01:42:04.84#ibcon#enter sib2, iclass 7, count 2 2006.286.01:42:04.84#ibcon#flushed, iclass 7, count 2 2006.286.01:42:04.84#ibcon#about to write, iclass 7, count 2 2006.286.01:42:04.84#ibcon#wrote, iclass 7, count 2 2006.286.01:42:04.84#ibcon#about to read 3, iclass 7, count 2 2006.286.01:42:04.87#ibcon#read 3, iclass 7, count 2 2006.286.01:42:04.87#ibcon#about to read 4, iclass 7, count 2 2006.286.01:42:04.87#ibcon#read 4, iclass 7, count 2 2006.286.01:42:04.87#ibcon#about to read 5, iclass 7, count 2 2006.286.01:42:04.87#ibcon#read 5, iclass 7, count 2 2006.286.01:42:04.87#ibcon#about to read 6, iclass 7, count 2 2006.286.01:42:04.87#ibcon#read 6, iclass 7, count 2 2006.286.01:42:04.87#ibcon#end of sib2, iclass 7, count 2 2006.286.01:42:04.87#ibcon#*after write, iclass 7, count 2 2006.286.01:42:04.87#ibcon#*before return 0, iclass 7, count 2 2006.286.01:42:04.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:42:04.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:42:04.87#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.01:42:04.87#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:04.87#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:42:04.99#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:42:04.99#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:42:04.99#ibcon#enter wrdev, iclass 7, count 0 2006.286.01:42:04.99#ibcon#first serial, iclass 7, count 0 2006.286.01:42:04.99#ibcon#enter sib2, iclass 7, count 0 2006.286.01:42:04.99#ibcon#flushed, iclass 7, count 0 2006.286.01:42:04.99#ibcon#about to write, iclass 7, count 0 2006.286.01:42:04.99#ibcon#wrote, iclass 7, count 0 2006.286.01:42:04.99#ibcon#about to read 3, iclass 7, count 0 2006.286.01:42:05.01#ibcon#read 3, iclass 7, count 0 2006.286.01:42:05.01#ibcon#about to read 4, iclass 7, count 0 2006.286.01:42:05.01#ibcon#read 4, iclass 7, count 0 2006.286.01:42:05.01#ibcon#about to read 5, iclass 7, count 0 2006.286.01:42:05.01#ibcon#read 5, iclass 7, count 0 2006.286.01:42:05.01#ibcon#about to read 6, iclass 7, count 0 2006.286.01:42:05.01#ibcon#read 6, iclass 7, count 0 2006.286.01:42:05.01#ibcon#end of sib2, iclass 7, count 0 2006.286.01:42:05.01#ibcon#*mode == 0, iclass 7, count 0 2006.286.01:42:05.01#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.01:42:05.01#ibcon#[25=USB\r\n] 2006.286.01:42:05.01#ibcon#*before write, iclass 7, count 0 2006.286.01:42:05.01#ibcon#enter sib2, iclass 7, count 0 2006.286.01:42:05.01#ibcon#flushed, iclass 7, count 0 2006.286.01:42:05.01#ibcon#about to write, iclass 7, count 0 2006.286.01:42:05.01#ibcon#wrote, iclass 7, count 0 2006.286.01:42:05.01#ibcon#about to read 3, iclass 7, count 0 2006.286.01:42:05.04#ibcon#read 3, iclass 7, count 0 2006.286.01:42:05.04#ibcon#about to read 4, iclass 7, count 0 2006.286.01:42:05.04#ibcon#read 4, iclass 7, count 0 2006.286.01:42:05.04#ibcon#about to read 5, iclass 7, count 0 2006.286.01:42:05.04#ibcon#read 5, iclass 7, count 0 2006.286.01:42:05.04#ibcon#about to read 6, iclass 7, count 0 2006.286.01:42:05.04#ibcon#read 6, iclass 7, count 0 2006.286.01:42:05.04#ibcon#end of sib2, iclass 7, count 0 2006.286.01:42:05.04#ibcon#*after write, iclass 7, count 0 2006.286.01:42:05.04#ibcon#*before return 0, iclass 7, count 0 2006.286.01:42:05.04#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:42:05.04#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:42:05.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.01:42:05.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.01:42:05.04$vck44/valo=6,814.99 2006.286.01:42:05.04#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.01:42:05.04#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.01:42:05.04#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:05.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:42:05.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:42:05.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:42:05.04#ibcon#enter wrdev, iclass 11, count 0 2006.286.01:42:05.04#ibcon#first serial, iclass 11, count 0 2006.286.01:42:05.04#ibcon#enter sib2, iclass 11, count 0 2006.286.01:42:05.04#ibcon#flushed, iclass 11, count 0 2006.286.01:42:05.04#ibcon#about to write, iclass 11, count 0 2006.286.01:42:05.04#ibcon#wrote, iclass 11, count 0 2006.286.01:42:05.04#ibcon#about to read 3, iclass 11, count 0 2006.286.01:42:05.06#ibcon#read 3, iclass 11, count 0 2006.286.01:42:05.06#ibcon#about to read 4, iclass 11, count 0 2006.286.01:42:05.06#ibcon#read 4, iclass 11, count 0 2006.286.01:42:05.06#ibcon#about to read 5, iclass 11, count 0 2006.286.01:42:05.06#ibcon#read 5, iclass 11, count 0 2006.286.01:42:05.06#ibcon#about to read 6, iclass 11, count 0 2006.286.01:42:05.06#ibcon#read 6, iclass 11, count 0 2006.286.01:42:05.06#ibcon#end of sib2, iclass 11, count 0 2006.286.01:42:05.06#ibcon#*mode == 0, iclass 11, count 0 2006.286.01:42:05.06#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.01:42:05.06#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:42:05.06#ibcon#*before write, iclass 11, count 0 2006.286.01:42:05.06#ibcon#enter sib2, iclass 11, count 0 2006.286.01:42:05.06#ibcon#flushed, iclass 11, count 0 2006.286.01:42:05.06#ibcon#about to write, iclass 11, count 0 2006.286.01:42:05.06#ibcon#wrote, iclass 11, count 0 2006.286.01:42:05.06#ibcon#about to read 3, iclass 11, count 0 2006.286.01:42:05.10#ibcon#read 3, iclass 11, count 0 2006.286.01:42:05.10#ibcon#about to read 4, iclass 11, count 0 2006.286.01:42:05.10#ibcon#read 4, iclass 11, count 0 2006.286.01:42:05.10#ibcon#about to read 5, iclass 11, count 0 2006.286.01:42:05.10#ibcon#read 5, iclass 11, count 0 2006.286.01:42:05.10#ibcon#about to read 6, iclass 11, count 0 2006.286.01:42:05.10#ibcon#read 6, iclass 11, count 0 2006.286.01:42:05.10#ibcon#end of sib2, iclass 11, count 0 2006.286.01:42:05.10#ibcon#*after write, iclass 11, count 0 2006.286.01:42:05.10#ibcon#*before return 0, iclass 11, count 0 2006.286.01:42:05.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:42:05.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:42:05.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.01:42:05.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.01:42:05.10$vck44/va=6,4 2006.286.01:42:05.10#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.01:42:05.10#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.01:42:05.10#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:05.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:42:05.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:42:05.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:42:05.16#ibcon#enter wrdev, iclass 13, count 2 2006.286.01:42:05.16#ibcon#first serial, iclass 13, count 2 2006.286.01:42:05.16#ibcon#enter sib2, iclass 13, count 2 2006.286.01:42:05.16#ibcon#flushed, iclass 13, count 2 2006.286.01:42:05.16#ibcon#about to write, iclass 13, count 2 2006.286.01:42:05.16#ibcon#wrote, iclass 13, count 2 2006.286.01:42:05.16#ibcon#about to read 3, iclass 13, count 2 2006.286.01:42:05.18#ibcon#read 3, iclass 13, count 2 2006.286.01:42:05.18#ibcon#about to read 4, iclass 13, count 2 2006.286.01:42:05.18#ibcon#read 4, iclass 13, count 2 2006.286.01:42:05.18#ibcon#about to read 5, iclass 13, count 2 2006.286.01:42:05.18#ibcon#read 5, iclass 13, count 2 2006.286.01:42:05.18#ibcon#about to read 6, iclass 13, count 2 2006.286.01:42:05.18#ibcon#read 6, iclass 13, count 2 2006.286.01:42:05.18#ibcon#end of sib2, iclass 13, count 2 2006.286.01:42:05.18#ibcon#*mode == 0, iclass 13, count 2 2006.286.01:42:05.18#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.01:42:05.18#ibcon#[25=AT06-04\r\n] 2006.286.01:42:05.18#ibcon#*before write, iclass 13, count 2 2006.286.01:42:05.18#ibcon#enter sib2, iclass 13, count 2 2006.286.01:42:05.18#ibcon#flushed, iclass 13, count 2 2006.286.01:42:05.18#ibcon#about to write, iclass 13, count 2 2006.286.01:42:05.18#ibcon#wrote, iclass 13, count 2 2006.286.01:42:05.18#ibcon#about to read 3, iclass 13, count 2 2006.286.01:42:05.21#ibcon#read 3, iclass 13, count 2 2006.286.01:42:05.21#ibcon#about to read 4, iclass 13, count 2 2006.286.01:42:05.21#ibcon#read 4, iclass 13, count 2 2006.286.01:42:05.21#ibcon#about to read 5, iclass 13, count 2 2006.286.01:42:05.21#ibcon#read 5, iclass 13, count 2 2006.286.01:42:05.21#ibcon#about to read 6, iclass 13, count 2 2006.286.01:42:05.21#ibcon#read 6, iclass 13, count 2 2006.286.01:42:05.21#ibcon#end of sib2, iclass 13, count 2 2006.286.01:42:05.21#ibcon#*after write, iclass 13, count 2 2006.286.01:42:05.21#ibcon#*before return 0, iclass 13, count 2 2006.286.01:42:05.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:42:05.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:42:05.21#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.01:42:05.21#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:05.21#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:42:05.33#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:42:05.33#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:42:05.33#ibcon#enter wrdev, iclass 13, count 0 2006.286.01:42:05.33#ibcon#first serial, iclass 13, count 0 2006.286.01:42:05.33#ibcon#enter sib2, iclass 13, count 0 2006.286.01:42:05.33#ibcon#flushed, iclass 13, count 0 2006.286.01:42:05.33#ibcon#about to write, iclass 13, count 0 2006.286.01:42:05.33#ibcon#wrote, iclass 13, count 0 2006.286.01:42:05.33#ibcon#about to read 3, iclass 13, count 0 2006.286.01:42:05.35#ibcon#read 3, iclass 13, count 0 2006.286.01:42:05.35#ibcon#about to read 4, iclass 13, count 0 2006.286.01:42:05.35#ibcon#read 4, iclass 13, count 0 2006.286.01:42:05.35#ibcon#about to read 5, iclass 13, count 0 2006.286.01:42:05.35#ibcon#read 5, iclass 13, count 0 2006.286.01:42:05.35#ibcon#about to read 6, iclass 13, count 0 2006.286.01:42:05.35#ibcon#read 6, iclass 13, count 0 2006.286.01:42:05.35#ibcon#end of sib2, iclass 13, count 0 2006.286.01:42:05.35#ibcon#*mode == 0, iclass 13, count 0 2006.286.01:42:05.35#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.01:42:05.35#ibcon#[25=USB\r\n] 2006.286.01:42:05.35#ibcon#*before write, iclass 13, count 0 2006.286.01:42:05.35#ibcon#enter sib2, iclass 13, count 0 2006.286.01:42:05.35#ibcon#flushed, iclass 13, count 0 2006.286.01:42:05.35#ibcon#about to write, iclass 13, count 0 2006.286.01:42:05.35#ibcon#wrote, iclass 13, count 0 2006.286.01:42:05.35#ibcon#about to read 3, iclass 13, count 0 2006.286.01:42:05.38#ibcon#read 3, iclass 13, count 0 2006.286.01:42:05.38#ibcon#about to read 4, iclass 13, count 0 2006.286.01:42:05.38#ibcon#read 4, iclass 13, count 0 2006.286.01:42:05.38#ibcon#about to read 5, iclass 13, count 0 2006.286.01:42:05.38#ibcon#read 5, iclass 13, count 0 2006.286.01:42:05.38#ibcon#about to read 6, iclass 13, count 0 2006.286.01:42:05.38#ibcon#read 6, iclass 13, count 0 2006.286.01:42:05.38#ibcon#end of sib2, iclass 13, count 0 2006.286.01:42:05.38#ibcon#*after write, iclass 13, count 0 2006.286.01:42:05.38#ibcon#*before return 0, iclass 13, count 0 2006.286.01:42:05.38#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:42:05.38#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:42:05.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.01:42:05.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.01:42:05.38$vck44/valo=7,864.99 2006.286.01:42:05.38#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.01:42:05.38#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.01:42:05.38#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:05.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:42:05.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:42:05.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:42:05.38#ibcon#enter wrdev, iclass 15, count 0 2006.286.01:42:05.38#ibcon#first serial, iclass 15, count 0 2006.286.01:42:05.38#ibcon#enter sib2, iclass 15, count 0 2006.286.01:42:05.38#ibcon#flushed, iclass 15, count 0 2006.286.01:42:05.38#ibcon#about to write, iclass 15, count 0 2006.286.01:42:05.38#ibcon#wrote, iclass 15, count 0 2006.286.01:42:05.38#ibcon#about to read 3, iclass 15, count 0 2006.286.01:42:05.40#ibcon#read 3, iclass 15, count 0 2006.286.01:42:05.40#ibcon#about to read 4, iclass 15, count 0 2006.286.01:42:05.40#ibcon#read 4, iclass 15, count 0 2006.286.01:42:05.40#ibcon#about to read 5, iclass 15, count 0 2006.286.01:42:05.40#ibcon#read 5, iclass 15, count 0 2006.286.01:42:05.40#ibcon#about to read 6, iclass 15, count 0 2006.286.01:42:05.40#ibcon#read 6, iclass 15, count 0 2006.286.01:42:05.40#ibcon#end of sib2, iclass 15, count 0 2006.286.01:42:05.40#ibcon#*mode == 0, iclass 15, count 0 2006.286.01:42:05.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.01:42:05.40#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:42:05.40#ibcon#*before write, iclass 15, count 0 2006.286.01:42:05.40#ibcon#enter sib2, iclass 15, count 0 2006.286.01:42:05.40#ibcon#flushed, iclass 15, count 0 2006.286.01:42:05.40#ibcon#about to write, iclass 15, count 0 2006.286.01:42:05.40#ibcon#wrote, iclass 15, count 0 2006.286.01:42:05.40#ibcon#about to read 3, iclass 15, count 0 2006.286.01:42:05.44#ibcon#read 3, iclass 15, count 0 2006.286.01:42:05.44#ibcon#about to read 4, iclass 15, count 0 2006.286.01:42:05.44#ibcon#read 4, iclass 15, count 0 2006.286.01:42:05.44#ibcon#about to read 5, iclass 15, count 0 2006.286.01:42:05.44#ibcon#read 5, iclass 15, count 0 2006.286.01:42:05.44#ibcon#about to read 6, iclass 15, count 0 2006.286.01:42:05.44#ibcon#read 6, iclass 15, count 0 2006.286.01:42:05.44#ibcon#end of sib2, iclass 15, count 0 2006.286.01:42:05.44#ibcon#*after write, iclass 15, count 0 2006.286.01:42:05.44#ibcon#*before return 0, iclass 15, count 0 2006.286.01:42:05.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:42:05.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:42:05.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.01:42:05.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.01:42:05.44$vck44/va=7,4 2006.286.01:42:05.44#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.01:42:05.44#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.01:42:05.44#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:05.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:42:05.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:42:05.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:42:05.50#ibcon#enter wrdev, iclass 17, count 2 2006.286.01:42:05.50#ibcon#first serial, iclass 17, count 2 2006.286.01:42:05.50#ibcon#enter sib2, iclass 17, count 2 2006.286.01:42:05.50#ibcon#flushed, iclass 17, count 2 2006.286.01:42:05.50#ibcon#about to write, iclass 17, count 2 2006.286.01:42:05.50#ibcon#wrote, iclass 17, count 2 2006.286.01:42:05.50#ibcon#about to read 3, iclass 17, count 2 2006.286.01:42:05.52#ibcon#read 3, iclass 17, count 2 2006.286.01:42:05.52#ibcon#about to read 4, iclass 17, count 2 2006.286.01:42:05.52#ibcon#read 4, iclass 17, count 2 2006.286.01:42:05.52#ibcon#about to read 5, iclass 17, count 2 2006.286.01:42:05.52#ibcon#read 5, iclass 17, count 2 2006.286.01:42:05.52#ibcon#about to read 6, iclass 17, count 2 2006.286.01:42:05.52#ibcon#read 6, iclass 17, count 2 2006.286.01:42:05.52#ibcon#end of sib2, iclass 17, count 2 2006.286.01:42:05.52#ibcon#*mode == 0, iclass 17, count 2 2006.286.01:42:05.52#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.01:42:05.52#ibcon#[25=AT07-04\r\n] 2006.286.01:42:05.52#ibcon#*before write, iclass 17, count 2 2006.286.01:42:05.52#ibcon#enter sib2, iclass 17, count 2 2006.286.01:42:05.52#ibcon#flushed, iclass 17, count 2 2006.286.01:42:05.52#ibcon#about to write, iclass 17, count 2 2006.286.01:42:05.52#ibcon#wrote, iclass 17, count 2 2006.286.01:42:05.52#ibcon#about to read 3, iclass 17, count 2 2006.286.01:42:05.55#ibcon#read 3, iclass 17, count 2 2006.286.01:42:05.55#ibcon#about to read 4, iclass 17, count 2 2006.286.01:42:05.55#ibcon#read 4, iclass 17, count 2 2006.286.01:42:05.55#ibcon#about to read 5, iclass 17, count 2 2006.286.01:42:05.55#ibcon#read 5, iclass 17, count 2 2006.286.01:42:05.55#ibcon#about to read 6, iclass 17, count 2 2006.286.01:42:05.55#ibcon#read 6, iclass 17, count 2 2006.286.01:42:05.55#ibcon#end of sib2, iclass 17, count 2 2006.286.01:42:05.55#ibcon#*after write, iclass 17, count 2 2006.286.01:42:05.55#ibcon#*before return 0, iclass 17, count 2 2006.286.01:42:05.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:42:05.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:42:05.55#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.01:42:05.55#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:05.55#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:42:05.67#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:42:05.67#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:42:05.67#ibcon#enter wrdev, iclass 17, count 0 2006.286.01:42:05.67#ibcon#first serial, iclass 17, count 0 2006.286.01:42:05.67#ibcon#enter sib2, iclass 17, count 0 2006.286.01:42:05.67#ibcon#flushed, iclass 17, count 0 2006.286.01:42:05.67#ibcon#about to write, iclass 17, count 0 2006.286.01:42:05.67#ibcon#wrote, iclass 17, count 0 2006.286.01:42:05.67#ibcon#about to read 3, iclass 17, count 0 2006.286.01:42:05.69#ibcon#read 3, iclass 17, count 0 2006.286.01:42:05.69#ibcon#about to read 4, iclass 17, count 0 2006.286.01:42:05.69#ibcon#read 4, iclass 17, count 0 2006.286.01:42:05.69#ibcon#about to read 5, iclass 17, count 0 2006.286.01:42:05.69#ibcon#read 5, iclass 17, count 0 2006.286.01:42:05.69#ibcon#about to read 6, iclass 17, count 0 2006.286.01:42:05.69#ibcon#read 6, iclass 17, count 0 2006.286.01:42:05.69#ibcon#end of sib2, iclass 17, count 0 2006.286.01:42:05.69#ibcon#*mode == 0, iclass 17, count 0 2006.286.01:42:05.69#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.01:42:05.69#ibcon#[25=USB\r\n] 2006.286.01:42:05.69#ibcon#*before write, iclass 17, count 0 2006.286.01:42:05.69#ibcon#enter sib2, iclass 17, count 0 2006.286.01:42:05.69#ibcon#flushed, iclass 17, count 0 2006.286.01:42:05.69#ibcon#about to write, iclass 17, count 0 2006.286.01:42:05.69#ibcon#wrote, iclass 17, count 0 2006.286.01:42:05.69#ibcon#about to read 3, iclass 17, count 0 2006.286.01:42:05.72#ibcon#read 3, iclass 17, count 0 2006.286.01:42:05.72#ibcon#about to read 4, iclass 17, count 0 2006.286.01:42:05.72#ibcon#read 4, iclass 17, count 0 2006.286.01:42:05.72#ibcon#about to read 5, iclass 17, count 0 2006.286.01:42:05.72#ibcon#read 5, iclass 17, count 0 2006.286.01:42:05.72#ibcon#about to read 6, iclass 17, count 0 2006.286.01:42:05.72#ibcon#read 6, iclass 17, count 0 2006.286.01:42:05.72#ibcon#end of sib2, iclass 17, count 0 2006.286.01:42:05.72#ibcon#*after write, iclass 17, count 0 2006.286.01:42:05.72#ibcon#*before return 0, iclass 17, count 0 2006.286.01:42:05.72#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:42:05.72#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:42:05.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.01:42:05.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.01:42:05.72$vck44/valo=8,884.99 2006.286.01:42:05.72#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.01:42:05.72#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.01:42:05.72#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:05.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:42:05.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:42:05.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:42:05.72#ibcon#enter wrdev, iclass 19, count 0 2006.286.01:42:05.72#ibcon#first serial, iclass 19, count 0 2006.286.01:42:05.72#ibcon#enter sib2, iclass 19, count 0 2006.286.01:42:05.72#ibcon#flushed, iclass 19, count 0 2006.286.01:42:05.72#ibcon#about to write, iclass 19, count 0 2006.286.01:42:05.72#ibcon#wrote, iclass 19, count 0 2006.286.01:42:05.72#ibcon#about to read 3, iclass 19, count 0 2006.286.01:42:05.74#ibcon#read 3, iclass 19, count 0 2006.286.01:42:05.74#ibcon#about to read 4, iclass 19, count 0 2006.286.01:42:05.74#ibcon#read 4, iclass 19, count 0 2006.286.01:42:05.74#ibcon#about to read 5, iclass 19, count 0 2006.286.01:42:05.74#ibcon#read 5, iclass 19, count 0 2006.286.01:42:05.74#ibcon#about to read 6, iclass 19, count 0 2006.286.01:42:05.74#ibcon#read 6, iclass 19, count 0 2006.286.01:42:05.74#ibcon#end of sib2, iclass 19, count 0 2006.286.01:42:05.74#ibcon#*mode == 0, iclass 19, count 0 2006.286.01:42:05.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.01:42:05.74#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:42:05.74#ibcon#*before write, iclass 19, count 0 2006.286.01:42:05.74#ibcon#enter sib2, iclass 19, count 0 2006.286.01:42:05.74#ibcon#flushed, iclass 19, count 0 2006.286.01:42:05.74#ibcon#about to write, iclass 19, count 0 2006.286.01:42:05.74#ibcon#wrote, iclass 19, count 0 2006.286.01:42:05.74#ibcon#about to read 3, iclass 19, count 0 2006.286.01:42:05.78#ibcon#read 3, iclass 19, count 0 2006.286.01:42:05.78#ibcon#about to read 4, iclass 19, count 0 2006.286.01:42:05.78#ibcon#read 4, iclass 19, count 0 2006.286.01:42:05.78#ibcon#about to read 5, iclass 19, count 0 2006.286.01:42:05.78#ibcon#read 5, iclass 19, count 0 2006.286.01:42:05.78#ibcon#about to read 6, iclass 19, count 0 2006.286.01:42:05.78#ibcon#read 6, iclass 19, count 0 2006.286.01:42:05.78#ibcon#end of sib2, iclass 19, count 0 2006.286.01:42:05.78#ibcon#*after write, iclass 19, count 0 2006.286.01:42:05.78#ibcon#*before return 0, iclass 19, count 0 2006.286.01:42:05.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:42:05.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:42:05.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.01:42:05.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.01:42:05.78$vck44/va=8,3 2006.286.01:42:05.78#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.01:42:05.78#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.01:42:05.78#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:05.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:42:05.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:42:05.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:42:05.84#ibcon#enter wrdev, iclass 21, count 2 2006.286.01:42:05.84#ibcon#first serial, iclass 21, count 2 2006.286.01:42:05.84#ibcon#enter sib2, iclass 21, count 2 2006.286.01:42:05.84#ibcon#flushed, iclass 21, count 2 2006.286.01:42:05.84#ibcon#about to write, iclass 21, count 2 2006.286.01:42:05.84#ibcon#wrote, iclass 21, count 2 2006.286.01:42:05.84#ibcon#about to read 3, iclass 21, count 2 2006.286.01:42:05.86#ibcon#read 3, iclass 21, count 2 2006.286.01:42:05.86#ibcon#about to read 4, iclass 21, count 2 2006.286.01:42:05.86#ibcon#read 4, iclass 21, count 2 2006.286.01:42:05.86#ibcon#about to read 5, iclass 21, count 2 2006.286.01:42:05.86#ibcon#read 5, iclass 21, count 2 2006.286.01:42:05.86#ibcon#about to read 6, iclass 21, count 2 2006.286.01:42:05.86#ibcon#read 6, iclass 21, count 2 2006.286.01:42:05.86#ibcon#end of sib2, iclass 21, count 2 2006.286.01:42:05.86#ibcon#*mode == 0, iclass 21, count 2 2006.286.01:42:05.86#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.01:42:05.86#ibcon#[25=AT08-03\r\n] 2006.286.01:42:05.86#ibcon#*before write, iclass 21, count 2 2006.286.01:42:05.86#ibcon#enter sib2, iclass 21, count 2 2006.286.01:42:05.86#ibcon#flushed, iclass 21, count 2 2006.286.01:42:05.86#ibcon#about to write, iclass 21, count 2 2006.286.01:42:05.86#ibcon#wrote, iclass 21, count 2 2006.286.01:42:05.86#ibcon#about to read 3, iclass 21, count 2 2006.286.01:42:05.89#ibcon#read 3, iclass 21, count 2 2006.286.01:42:05.89#ibcon#about to read 4, iclass 21, count 2 2006.286.01:42:05.89#ibcon#read 4, iclass 21, count 2 2006.286.01:42:05.89#ibcon#about to read 5, iclass 21, count 2 2006.286.01:42:05.89#ibcon#read 5, iclass 21, count 2 2006.286.01:42:05.89#ibcon#about to read 6, iclass 21, count 2 2006.286.01:42:05.89#ibcon#read 6, iclass 21, count 2 2006.286.01:42:05.89#ibcon#end of sib2, iclass 21, count 2 2006.286.01:42:05.89#ibcon#*after write, iclass 21, count 2 2006.286.01:42:05.89#ibcon#*before return 0, iclass 21, count 2 2006.286.01:42:05.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:42:05.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:42:05.89#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.01:42:05.89#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:05.89#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:42:06.01#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:42:06.01#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:42:06.01#ibcon#enter wrdev, iclass 21, count 0 2006.286.01:42:06.01#ibcon#first serial, iclass 21, count 0 2006.286.01:42:06.01#ibcon#enter sib2, iclass 21, count 0 2006.286.01:42:06.01#ibcon#flushed, iclass 21, count 0 2006.286.01:42:06.01#ibcon#about to write, iclass 21, count 0 2006.286.01:42:06.01#ibcon#wrote, iclass 21, count 0 2006.286.01:42:06.01#ibcon#about to read 3, iclass 21, count 0 2006.286.01:42:06.03#ibcon#read 3, iclass 21, count 0 2006.286.01:42:06.03#ibcon#about to read 4, iclass 21, count 0 2006.286.01:42:06.03#ibcon#read 4, iclass 21, count 0 2006.286.01:42:06.03#ibcon#about to read 5, iclass 21, count 0 2006.286.01:42:06.03#ibcon#read 5, iclass 21, count 0 2006.286.01:42:06.03#ibcon#about to read 6, iclass 21, count 0 2006.286.01:42:06.03#ibcon#read 6, iclass 21, count 0 2006.286.01:42:06.03#ibcon#end of sib2, iclass 21, count 0 2006.286.01:42:06.03#ibcon#*mode == 0, iclass 21, count 0 2006.286.01:42:06.03#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.01:42:06.03#ibcon#[25=USB\r\n] 2006.286.01:42:06.03#ibcon#*before write, iclass 21, count 0 2006.286.01:42:06.03#ibcon#enter sib2, iclass 21, count 0 2006.286.01:42:06.03#ibcon#flushed, iclass 21, count 0 2006.286.01:42:06.03#ibcon#about to write, iclass 21, count 0 2006.286.01:42:06.03#ibcon#wrote, iclass 21, count 0 2006.286.01:42:06.03#ibcon#about to read 3, iclass 21, count 0 2006.286.01:42:06.06#ibcon#read 3, iclass 21, count 0 2006.286.01:42:06.06#ibcon#about to read 4, iclass 21, count 0 2006.286.01:42:06.06#ibcon#read 4, iclass 21, count 0 2006.286.01:42:06.06#ibcon#about to read 5, iclass 21, count 0 2006.286.01:42:06.06#ibcon#read 5, iclass 21, count 0 2006.286.01:42:06.06#ibcon#about to read 6, iclass 21, count 0 2006.286.01:42:06.06#ibcon#read 6, iclass 21, count 0 2006.286.01:42:06.06#ibcon#end of sib2, iclass 21, count 0 2006.286.01:42:06.06#ibcon#*after write, iclass 21, count 0 2006.286.01:42:06.06#ibcon#*before return 0, iclass 21, count 0 2006.286.01:42:06.06#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:42:06.06#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:42:06.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.01:42:06.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.01:42:06.06$vck44/vblo=1,629.99 2006.286.01:42:06.06#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.01:42:06.06#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.01:42:06.06#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:06.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:42:06.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:42:06.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:42:06.06#ibcon#enter wrdev, iclass 23, count 0 2006.286.01:42:06.06#ibcon#first serial, iclass 23, count 0 2006.286.01:42:06.06#ibcon#enter sib2, iclass 23, count 0 2006.286.01:42:06.06#ibcon#flushed, iclass 23, count 0 2006.286.01:42:06.06#ibcon#about to write, iclass 23, count 0 2006.286.01:42:06.06#ibcon#wrote, iclass 23, count 0 2006.286.01:42:06.06#ibcon#about to read 3, iclass 23, count 0 2006.286.01:42:06.08#ibcon#read 3, iclass 23, count 0 2006.286.01:42:06.08#ibcon#about to read 4, iclass 23, count 0 2006.286.01:42:06.08#ibcon#read 4, iclass 23, count 0 2006.286.01:42:06.08#ibcon#about to read 5, iclass 23, count 0 2006.286.01:42:06.08#ibcon#read 5, iclass 23, count 0 2006.286.01:42:06.08#ibcon#about to read 6, iclass 23, count 0 2006.286.01:42:06.08#ibcon#read 6, iclass 23, count 0 2006.286.01:42:06.08#ibcon#end of sib2, iclass 23, count 0 2006.286.01:42:06.08#ibcon#*mode == 0, iclass 23, count 0 2006.286.01:42:06.08#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.01:42:06.08#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:42:06.08#ibcon#*before write, iclass 23, count 0 2006.286.01:42:06.08#ibcon#enter sib2, iclass 23, count 0 2006.286.01:42:06.08#ibcon#flushed, iclass 23, count 0 2006.286.01:42:06.08#ibcon#about to write, iclass 23, count 0 2006.286.01:42:06.08#ibcon#wrote, iclass 23, count 0 2006.286.01:42:06.08#ibcon#about to read 3, iclass 23, count 0 2006.286.01:42:06.12#ibcon#read 3, iclass 23, count 0 2006.286.01:42:06.12#ibcon#about to read 4, iclass 23, count 0 2006.286.01:42:06.12#ibcon#read 4, iclass 23, count 0 2006.286.01:42:06.12#ibcon#about to read 5, iclass 23, count 0 2006.286.01:42:06.12#ibcon#read 5, iclass 23, count 0 2006.286.01:42:06.12#ibcon#about to read 6, iclass 23, count 0 2006.286.01:42:06.12#ibcon#read 6, iclass 23, count 0 2006.286.01:42:06.12#ibcon#end of sib2, iclass 23, count 0 2006.286.01:42:06.12#ibcon#*after write, iclass 23, count 0 2006.286.01:42:06.12#ibcon#*before return 0, iclass 23, count 0 2006.286.01:42:06.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:42:06.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:42:06.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.01:42:06.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.01:42:06.12$vck44/vb=1,4 2006.286.01:42:06.12#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.01:42:06.12#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.01:42:06.12#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:06.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:42:06.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:42:06.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:42:06.12#ibcon#enter wrdev, iclass 25, count 2 2006.286.01:42:06.12#ibcon#first serial, iclass 25, count 2 2006.286.01:42:06.12#ibcon#enter sib2, iclass 25, count 2 2006.286.01:42:06.12#ibcon#flushed, iclass 25, count 2 2006.286.01:42:06.12#ibcon#about to write, iclass 25, count 2 2006.286.01:42:06.12#ibcon#wrote, iclass 25, count 2 2006.286.01:42:06.12#ibcon#about to read 3, iclass 25, count 2 2006.286.01:42:06.14#ibcon#read 3, iclass 25, count 2 2006.286.01:42:06.14#ibcon#about to read 4, iclass 25, count 2 2006.286.01:42:06.14#ibcon#read 4, iclass 25, count 2 2006.286.01:42:06.14#ibcon#about to read 5, iclass 25, count 2 2006.286.01:42:06.14#ibcon#read 5, iclass 25, count 2 2006.286.01:42:06.14#ibcon#about to read 6, iclass 25, count 2 2006.286.01:42:06.14#ibcon#read 6, iclass 25, count 2 2006.286.01:42:06.14#ibcon#end of sib2, iclass 25, count 2 2006.286.01:42:06.14#ibcon#*mode == 0, iclass 25, count 2 2006.286.01:42:06.14#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.01:42:06.14#ibcon#[27=AT01-04\r\n] 2006.286.01:42:06.14#ibcon#*before write, iclass 25, count 2 2006.286.01:42:06.14#ibcon#enter sib2, iclass 25, count 2 2006.286.01:42:06.14#ibcon#flushed, iclass 25, count 2 2006.286.01:42:06.14#ibcon#about to write, iclass 25, count 2 2006.286.01:42:06.14#ibcon#wrote, iclass 25, count 2 2006.286.01:42:06.14#ibcon#about to read 3, iclass 25, count 2 2006.286.01:42:06.17#ibcon#read 3, iclass 25, count 2 2006.286.01:42:06.17#ibcon#about to read 4, iclass 25, count 2 2006.286.01:42:06.17#ibcon#read 4, iclass 25, count 2 2006.286.01:42:06.17#ibcon#about to read 5, iclass 25, count 2 2006.286.01:42:06.17#ibcon#read 5, iclass 25, count 2 2006.286.01:42:06.17#ibcon#about to read 6, iclass 25, count 2 2006.286.01:42:06.17#ibcon#read 6, iclass 25, count 2 2006.286.01:42:06.17#ibcon#end of sib2, iclass 25, count 2 2006.286.01:42:06.17#ibcon#*after write, iclass 25, count 2 2006.286.01:42:06.17#ibcon#*before return 0, iclass 25, count 2 2006.286.01:42:06.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:42:06.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:42:06.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.01:42:06.17#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:06.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:42:06.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:42:06.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:42:06.29#ibcon#enter wrdev, iclass 25, count 0 2006.286.01:42:06.29#ibcon#first serial, iclass 25, count 0 2006.286.01:42:06.29#ibcon#enter sib2, iclass 25, count 0 2006.286.01:42:06.29#ibcon#flushed, iclass 25, count 0 2006.286.01:42:06.29#ibcon#about to write, iclass 25, count 0 2006.286.01:42:06.29#ibcon#wrote, iclass 25, count 0 2006.286.01:42:06.29#ibcon#about to read 3, iclass 25, count 0 2006.286.01:42:06.31#ibcon#read 3, iclass 25, count 0 2006.286.01:42:06.31#ibcon#about to read 4, iclass 25, count 0 2006.286.01:42:06.31#ibcon#read 4, iclass 25, count 0 2006.286.01:42:06.31#ibcon#about to read 5, iclass 25, count 0 2006.286.01:42:06.31#ibcon#read 5, iclass 25, count 0 2006.286.01:42:06.31#ibcon#about to read 6, iclass 25, count 0 2006.286.01:42:06.31#ibcon#read 6, iclass 25, count 0 2006.286.01:42:06.31#ibcon#end of sib2, iclass 25, count 0 2006.286.01:42:06.31#ibcon#*mode == 0, iclass 25, count 0 2006.286.01:42:06.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.01:42:06.31#ibcon#[27=USB\r\n] 2006.286.01:42:06.31#ibcon#*before write, iclass 25, count 0 2006.286.01:42:06.31#ibcon#enter sib2, iclass 25, count 0 2006.286.01:42:06.31#ibcon#flushed, iclass 25, count 0 2006.286.01:42:06.31#ibcon#about to write, iclass 25, count 0 2006.286.01:42:06.31#ibcon#wrote, iclass 25, count 0 2006.286.01:42:06.31#ibcon#about to read 3, iclass 25, count 0 2006.286.01:42:06.34#ibcon#read 3, iclass 25, count 0 2006.286.01:42:06.34#ibcon#about to read 4, iclass 25, count 0 2006.286.01:42:06.34#ibcon#read 4, iclass 25, count 0 2006.286.01:42:06.34#ibcon#about to read 5, iclass 25, count 0 2006.286.01:42:06.34#ibcon#read 5, iclass 25, count 0 2006.286.01:42:06.34#ibcon#about to read 6, iclass 25, count 0 2006.286.01:42:06.34#ibcon#read 6, iclass 25, count 0 2006.286.01:42:06.34#ibcon#end of sib2, iclass 25, count 0 2006.286.01:42:06.34#ibcon#*after write, iclass 25, count 0 2006.286.01:42:06.34#ibcon#*before return 0, iclass 25, count 0 2006.286.01:42:06.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:42:06.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:42:06.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.01:42:06.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.01:42:06.34$vck44/vblo=2,634.99 2006.286.01:42:06.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.01:42:06.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.01:42:06.34#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:06.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:42:06.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:42:06.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:42:06.34#ibcon#enter wrdev, iclass 27, count 0 2006.286.01:42:06.34#ibcon#first serial, iclass 27, count 0 2006.286.01:42:06.34#ibcon#enter sib2, iclass 27, count 0 2006.286.01:42:06.34#ibcon#flushed, iclass 27, count 0 2006.286.01:42:06.34#ibcon#about to write, iclass 27, count 0 2006.286.01:42:06.34#ibcon#wrote, iclass 27, count 0 2006.286.01:42:06.34#ibcon#about to read 3, iclass 27, count 0 2006.286.01:42:06.36#ibcon#read 3, iclass 27, count 0 2006.286.01:42:06.36#ibcon#about to read 4, iclass 27, count 0 2006.286.01:42:06.36#ibcon#read 4, iclass 27, count 0 2006.286.01:42:06.36#ibcon#about to read 5, iclass 27, count 0 2006.286.01:42:06.36#ibcon#read 5, iclass 27, count 0 2006.286.01:42:06.36#ibcon#about to read 6, iclass 27, count 0 2006.286.01:42:06.36#ibcon#read 6, iclass 27, count 0 2006.286.01:42:06.36#ibcon#end of sib2, iclass 27, count 0 2006.286.01:42:06.36#ibcon#*mode == 0, iclass 27, count 0 2006.286.01:42:06.36#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.01:42:06.36#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:42:06.36#ibcon#*before write, iclass 27, count 0 2006.286.01:42:06.36#ibcon#enter sib2, iclass 27, count 0 2006.286.01:42:06.36#ibcon#flushed, iclass 27, count 0 2006.286.01:42:06.36#ibcon#about to write, iclass 27, count 0 2006.286.01:42:06.36#ibcon#wrote, iclass 27, count 0 2006.286.01:42:06.36#ibcon#about to read 3, iclass 27, count 0 2006.286.01:42:06.40#ibcon#read 3, iclass 27, count 0 2006.286.01:42:06.40#ibcon#about to read 4, iclass 27, count 0 2006.286.01:42:06.40#ibcon#read 4, iclass 27, count 0 2006.286.01:42:06.40#ibcon#about to read 5, iclass 27, count 0 2006.286.01:42:06.40#ibcon#read 5, iclass 27, count 0 2006.286.01:42:06.40#ibcon#about to read 6, iclass 27, count 0 2006.286.01:42:06.40#ibcon#read 6, iclass 27, count 0 2006.286.01:42:06.40#ibcon#end of sib2, iclass 27, count 0 2006.286.01:42:06.40#ibcon#*after write, iclass 27, count 0 2006.286.01:42:06.40#ibcon#*before return 0, iclass 27, count 0 2006.286.01:42:06.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:42:06.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:42:06.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.01:42:06.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.01:42:06.40$vck44/vb=2,5 2006.286.01:42:06.40#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.01:42:06.40#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.01:42:06.40#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:06.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:42:06.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:42:06.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:42:06.46#ibcon#enter wrdev, iclass 29, count 2 2006.286.01:42:06.46#ibcon#first serial, iclass 29, count 2 2006.286.01:42:06.46#ibcon#enter sib2, iclass 29, count 2 2006.286.01:42:06.46#ibcon#flushed, iclass 29, count 2 2006.286.01:42:06.46#ibcon#about to write, iclass 29, count 2 2006.286.01:42:06.46#ibcon#wrote, iclass 29, count 2 2006.286.01:42:06.46#ibcon#about to read 3, iclass 29, count 2 2006.286.01:42:06.48#ibcon#read 3, iclass 29, count 2 2006.286.01:42:06.48#ibcon#about to read 4, iclass 29, count 2 2006.286.01:42:06.48#ibcon#read 4, iclass 29, count 2 2006.286.01:42:06.48#ibcon#about to read 5, iclass 29, count 2 2006.286.01:42:06.48#ibcon#read 5, iclass 29, count 2 2006.286.01:42:06.48#ibcon#about to read 6, iclass 29, count 2 2006.286.01:42:06.48#ibcon#read 6, iclass 29, count 2 2006.286.01:42:06.48#ibcon#end of sib2, iclass 29, count 2 2006.286.01:42:06.48#ibcon#*mode == 0, iclass 29, count 2 2006.286.01:42:06.48#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.01:42:06.48#ibcon#[27=AT02-05\r\n] 2006.286.01:42:06.48#ibcon#*before write, iclass 29, count 2 2006.286.01:42:06.48#ibcon#enter sib2, iclass 29, count 2 2006.286.01:42:06.48#ibcon#flushed, iclass 29, count 2 2006.286.01:42:06.48#ibcon#about to write, iclass 29, count 2 2006.286.01:42:06.48#ibcon#wrote, iclass 29, count 2 2006.286.01:42:06.48#ibcon#about to read 3, iclass 29, count 2 2006.286.01:42:06.51#ibcon#read 3, iclass 29, count 2 2006.286.01:42:06.51#ibcon#about to read 4, iclass 29, count 2 2006.286.01:42:06.51#ibcon#read 4, iclass 29, count 2 2006.286.01:42:06.51#ibcon#about to read 5, iclass 29, count 2 2006.286.01:42:06.51#ibcon#read 5, iclass 29, count 2 2006.286.01:42:06.51#ibcon#about to read 6, iclass 29, count 2 2006.286.01:42:06.51#ibcon#read 6, iclass 29, count 2 2006.286.01:42:06.51#ibcon#end of sib2, iclass 29, count 2 2006.286.01:42:06.51#ibcon#*after write, iclass 29, count 2 2006.286.01:42:06.51#ibcon#*before return 0, iclass 29, count 2 2006.286.01:42:06.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:42:06.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:42:06.51#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.01:42:06.51#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:06.51#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:42:06.63#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:42:06.63#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:42:06.63#ibcon#enter wrdev, iclass 29, count 0 2006.286.01:42:06.63#ibcon#first serial, iclass 29, count 0 2006.286.01:42:06.63#ibcon#enter sib2, iclass 29, count 0 2006.286.01:42:06.63#ibcon#flushed, iclass 29, count 0 2006.286.01:42:06.63#ibcon#about to write, iclass 29, count 0 2006.286.01:42:06.63#ibcon#wrote, iclass 29, count 0 2006.286.01:42:06.63#ibcon#about to read 3, iclass 29, count 0 2006.286.01:42:06.65#ibcon#read 3, iclass 29, count 0 2006.286.01:42:06.65#ibcon#about to read 4, iclass 29, count 0 2006.286.01:42:06.65#ibcon#read 4, iclass 29, count 0 2006.286.01:42:06.65#ibcon#about to read 5, iclass 29, count 0 2006.286.01:42:06.65#ibcon#read 5, iclass 29, count 0 2006.286.01:42:06.65#ibcon#about to read 6, iclass 29, count 0 2006.286.01:42:06.65#ibcon#read 6, iclass 29, count 0 2006.286.01:42:06.65#ibcon#end of sib2, iclass 29, count 0 2006.286.01:42:06.65#ibcon#*mode == 0, iclass 29, count 0 2006.286.01:42:06.65#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.01:42:06.65#ibcon#[27=USB\r\n] 2006.286.01:42:06.65#ibcon#*before write, iclass 29, count 0 2006.286.01:42:06.65#ibcon#enter sib2, iclass 29, count 0 2006.286.01:42:06.65#ibcon#flushed, iclass 29, count 0 2006.286.01:42:06.65#ibcon#about to write, iclass 29, count 0 2006.286.01:42:06.65#ibcon#wrote, iclass 29, count 0 2006.286.01:42:06.65#ibcon#about to read 3, iclass 29, count 0 2006.286.01:42:06.68#ibcon#read 3, iclass 29, count 0 2006.286.01:42:06.68#ibcon#about to read 4, iclass 29, count 0 2006.286.01:42:06.68#ibcon#read 4, iclass 29, count 0 2006.286.01:42:06.68#ibcon#about to read 5, iclass 29, count 0 2006.286.01:42:06.68#ibcon#read 5, iclass 29, count 0 2006.286.01:42:06.68#ibcon#about to read 6, iclass 29, count 0 2006.286.01:42:06.68#ibcon#read 6, iclass 29, count 0 2006.286.01:42:06.68#ibcon#end of sib2, iclass 29, count 0 2006.286.01:42:06.68#ibcon#*after write, iclass 29, count 0 2006.286.01:42:06.68#ibcon#*before return 0, iclass 29, count 0 2006.286.01:42:06.68#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:42:06.68#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:42:06.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.01:42:06.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.01:42:06.68$vck44/vblo=3,649.99 2006.286.01:42:06.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.01:42:06.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.01:42:06.68#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:06.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:42:06.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:42:06.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:42:06.68#ibcon#enter wrdev, iclass 31, count 0 2006.286.01:42:06.68#ibcon#first serial, iclass 31, count 0 2006.286.01:42:06.68#ibcon#enter sib2, iclass 31, count 0 2006.286.01:42:06.68#ibcon#flushed, iclass 31, count 0 2006.286.01:42:06.68#ibcon#about to write, iclass 31, count 0 2006.286.01:42:06.68#ibcon#wrote, iclass 31, count 0 2006.286.01:42:06.68#ibcon#about to read 3, iclass 31, count 0 2006.286.01:42:06.70#ibcon#read 3, iclass 31, count 0 2006.286.01:42:06.70#ibcon#about to read 4, iclass 31, count 0 2006.286.01:42:06.70#ibcon#read 4, iclass 31, count 0 2006.286.01:42:06.70#ibcon#about to read 5, iclass 31, count 0 2006.286.01:42:06.70#ibcon#read 5, iclass 31, count 0 2006.286.01:42:06.70#ibcon#about to read 6, iclass 31, count 0 2006.286.01:42:06.70#ibcon#read 6, iclass 31, count 0 2006.286.01:42:06.70#ibcon#end of sib2, iclass 31, count 0 2006.286.01:42:06.70#ibcon#*mode == 0, iclass 31, count 0 2006.286.01:42:06.70#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.01:42:06.70#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:42:06.70#ibcon#*before write, iclass 31, count 0 2006.286.01:42:06.70#ibcon#enter sib2, iclass 31, count 0 2006.286.01:42:06.70#ibcon#flushed, iclass 31, count 0 2006.286.01:42:06.70#ibcon#about to write, iclass 31, count 0 2006.286.01:42:06.70#ibcon#wrote, iclass 31, count 0 2006.286.01:42:06.70#ibcon#about to read 3, iclass 31, count 0 2006.286.01:42:06.74#ibcon#read 3, iclass 31, count 0 2006.286.01:42:06.74#ibcon#about to read 4, iclass 31, count 0 2006.286.01:42:06.74#ibcon#read 4, iclass 31, count 0 2006.286.01:42:06.74#ibcon#about to read 5, iclass 31, count 0 2006.286.01:42:06.74#ibcon#read 5, iclass 31, count 0 2006.286.01:42:06.74#ibcon#about to read 6, iclass 31, count 0 2006.286.01:42:06.74#ibcon#read 6, iclass 31, count 0 2006.286.01:42:06.74#ibcon#end of sib2, iclass 31, count 0 2006.286.01:42:06.74#ibcon#*after write, iclass 31, count 0 2006.286.01:42:06.74#ibcon#*before return 0, iclass 31, count 0 2006.286.01:42:06.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:42:06.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:42:06.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.01:42:06.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.01:42:06.74$vck44/vb=3,4 2006.286.01:42:06.74#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.01:42:06.74#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.01:42:06.74#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:06.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:42:06.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:42:06.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:42:06.80#ibcon#enter wrdev, iclass 33, count 2 2006.286.01:42:06.80#ibcon#first serial, iclass 33, count 2 2006.286.01:42:06.80#ibcon#enter sib2, iclass 33, count 2 2006.286.01:42:06.80#ibcon#flushed, iclass 33, count 2 2006.286.01:42:06.80#ibcon#about to write, iclass 33, count 2 2006.286.01:42:06.80#ibcon#wrote, iclass 33, count 2 2006.286.01:42:06.80#ibcon#about to read 3, iclass 33, count 2 2006.286.01:42:06.82#ibcon#read 3, iclass 33, count 2 2006.286.01:42:06.82#ibcon#about to read 4, iclass 33, count 2 2006.286.01:42:06.82#ibcon#read 4, iclass 33, count 2 2006.286.01:42:06.82#ibcon#about to read 5, iclass 33, count 2 2006.286.01:42:06.82#ibcon#read 5, iclass 33, count 2 2006.286.01:42:06.82#ibcon#about to read 6, iclass 33, count 2 2006.286.01:42:06.82#ibcon#read 6, iclass 33, count 2 2006.286.01:42:06.82#ibcon#end of sib2, iclass 33, count 2 2006.286.01:42:06.82#ibcon#*mode == 0, iclass 33, count 2 2006.286.01:42:06.82#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.01:42:06.82#ibcon#[27=AT03-04\r\n] 2006.286.01:42:06.82#ibcon#*before write, iclass 33, count 2 2006.286.01:42:06.82#ibcon#enter sib2, iclass 33, count 2 2006.286.01:42:06.82#ibcon#flushed, iclass 33, count 2 2006.286.01:42:06.82#ibcon#about to write, iclass 33, count 2 2006.286.01:42:06.82#ibcon#wrote, iclass 33, count 2 2006.286.01:42:06.82#ibcon#about to read 3, iclass 33, count 2 2006.286.01:42:06.85#ibcon#read 3, iclass 33, count 2 2006.286.01:42:06.85#ibcon#about to read 4, iclass 33, count 2 2006.286.01:42:06.85#ibcon#read 4, iclass 33, count 2 2006.286.01:42:06.85#ibcon#about to read 5, iclass 33, count 2 2006.286.01:42:06.85#ibcon#read 5, iclass 33, count 2 2006.286.01:42:06.85#ibcon#about to read 6, iclass 33, count 2 2006.286.01:42:06.85#ibcon#read 6, iclass 33, count 2 2006.286.01:42:06.85#ibcon#end of sib2, iclass 33, count 2 2006.286.01:42:06.85#ibcon#*after write, iclass 33, count 2 2006.286.01:42:06.85#ibcon#*before return 0, iclass 33, count 2 2006.286.01:42:06.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:42:06.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.01:42:06.85#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.01:42:06.85#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:06.85#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:42:06.97#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:42:06.97#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:42:06.97#ibcon#enter wrdev, iclass 33, count 0 2006.286.01:42:06.97#ibcon#first serial, iclass 33, count 0 2006.286.01:42:06.97#ibcon#enter sib2, iclass 33, count 0 2006.286.01:42:06.97#ibcon#flushed, iclass 33, count 0 2006.286.01:42:06.97#ibcon#about to write, iclass 33, count 0 2006.286.01:42:06.97#ibcon#wrote, iclass 33, count 0 2006.286.01:42:06.97#ibcon#about to read 3, iclass 33, count 0 2006.286.01:42:06.99#ibcon#read 3, iclass 33, count 0 2006.286.01:42:06.99#ibcon#about to read 4, iclass 33, count 0 2006.286.01:42:06.99#ibcon#read 4, iclass 33, count 0 2006.286.01:42:06.99#ibcon#about to read 5, iclass 33, count 0 2006.286.01:42:06.99#ibcon#read 5, iclass 33, count 0 2006.286.01:42:06.99#ibcon#about to read 6, iclass 33, count 0 2006.286.01:42:06.99#ibcon#read 6, iclass 33, count 0 2006.286.01:42:06.99#ibcon#end of sib2, iclass 33, count 0 2006.286.01:42:06.99#ibcon#*mode == 0, iclass 33, count 0 2006.286.01:42:06.99#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.01:42:06.99#ibcon#[27=USB\r\n] 2006.286.01:42:06.99#ibcon#*before write, iclass 33, count 0 2006.286.01:42:06.99#ibcon#enter sib2, iclass 33, count 0 2006.286.01:42:06.99#ibcon#flushed, iclass 33, count 0 2006.286.01:42:06.99#ibcon#about to write, iclass 33, count 0 2006.286.01:42:06.99#ibcon#wrote, iclass 33, count 0 2006.286.01:42:06.99#ibcon#about to read 3, iclass 33, count 0 2006.286.01:42:07.02#ibcon#read 3, iclass 33, count 0 2006.286.01:42:07.02#ibcon#about to read 4, iclass 33, count 0 2006.286.01:42:07.02#ibcon#read 4, iclass 33, count 0 2006.286.01:42:07.02#ibcon#about to read 5, iclass 33, count 0 2006.286.01:42:07.02#ibcon#read 5, iclass 33, count 0 2006.286.01:42:07.02#ibcon#about to read 6, iclass 33, count 0 2006.286.01:42:07.02#ibcon#read 6, iclass 33, count 0 2006.286.01:42:07.02#ibcon#end of sib2, iclass 33, count 0 2006.286.01:42:07.02#ibcon#*after write, iclass 33, count 0 2006.286.01:42:07.02#ibcon#*before return 0, iclass 33, count 0 2006.286.01:42:07.02#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:42:07.02#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.01:42:07.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.01:42:07.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.01:42:07.02$vck44/vblo=4,679.99 2006.286.01:42:07.02#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.01:42:07.02#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.01:42:07.02#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:07.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:42:07.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:42:07.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:42:07.02#ibcon#enter wrdev, iclass 35, count 0 2006.286.01:42:07.02#ibcon#first serial, iclass 35, count 0 2006.286.01:42:07.02#ibcon#enter sib2, iclass 35, count 0 2006.286.01:42:07.02#ibcon#flushed, iclass 35, count 0 2006.286.01:42:07.02#ibcon#about to write, iclass 35, count 0 2006.286.01:42:07.02#ibcon#wrote, iclass 35, count 0 2006.286.01:42:07.02#ibcon#about to read 3, iclass 35, count 0 2006.286.01:42:07.04#ibcon#read 3, iclass 35, count 0 2006.286.01:42:07.04#ibcon#about to read 4, iclass 35, count 0 2006.286.01:42:07.04#ibcon#read 4, iclass 35, count 0 2006.286.01:42:07.04#ibcon#about to read 5, iclass 35, count 0 2006.286.01:42:07.04#ibcon#read 5, iclass 35, count 0 2006.286.01:42:07.04#ibcon#about to read 6, iclass 35, count 0 2006.286.01:42:07.04#ibcon#read 6, iclass 35, count 0 2006.286.01:42:07.04#ibcon#end of sib2, iclass 35, count 0 2006.286.01:42:07.04#ibcon#*mode == 0, iclass 35, count 0 2006.286.01:42:07.04#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.01:42:07.04#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:42:07.04#ibcon#*before write, iclass 35, count 0 2006.286.01:42:07.04#ibcon#enter sib2, iclass 35, count 0 2006.286.01:42:07.04#ibcon#flushed, iclass 35, count 0 2006.286.01:42:07.04#ibcon#about to write, iclass 35, count 0 2006.286.01:42:07.04#ibcon#wrote, iclass 35, count 0 2006.286.01:42:07.04#ibcon#about to read 3, iclass 35, count 0 2006.286.01:42:07.08#ibcon#read 3, iclass 35, count 0 2006.286.01:42:07.08#ibcon#about to read 4, iclass 35, count 0 2006.286.01:42:07.08#ibcon#read 4, iclass 35, count 0 2006.286.01:42:07.08#ibcon#about to read 5, iclass 35, count 0 2006.286.01:42:07.08#ibcon#read 5, iclass 35, count 0 2006.286.01:42:07.08#ibcon#about to read 6, iclass 35, count 0 2006.286.01:42:07.08#ibcon#read 6, iclass 35, count 0 2006.286.01:42:07.08#ibcon#end of sib2, iclass 35, count 0 2006.286.01:42:07.08#ibcon#*after write, iclass 35, count 0 2006.286.01:42:07.08#ibcon#*before return 0, iclass 35, count 0 2006.286.01:42:07.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:42:07.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:42:07.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.01:42:07.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.01:42:07.08$vck44/vb=4,5 2006.286.01:42:07.08#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.01:42:07.08#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.01:42:07.08#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:07.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:42:07.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:42:07.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:42:07.14#ibcon#enter wrdev, iclass 37, count 2 2006.286.01:42:07.14#ibcon#first serial, iclass 37, count 2 2006.286.01:42:07.14#ibcon#enter sib2, iclass 37, count 2 2006.286.01:42:07.14#ibcon#flushed, iclass 37, count 2 2006.286.01:42:07.14#ibcon#about to write, iclass 37, count 2 2006.286.01:42:07.14#ibcon#wrote, iclass 37, count 2 2006.286.01:42:07.14#ibcon#about to read 3, iclass 37, count 2 2006.286.01:42:07.16#ibcon#read 3, iclass 37, count 2 2006.286.01:42:07.16#ibcon#about to read 4, iclass 37, count 2 2006.286.01:42:07.16#ibcon#read 4, iclass 37, count 2 2006.286.01:42:07.16#ibcon#about to read 5, iclass 37, count 2 2006.286.01:42:07.16#ibcon#read 5, iclass 37, count 2 2006.286.01:42:07.16#ibcon#about to read 6, iclass 37, count 2 2006.286.01:42:07.16#ibcon#read 6, iclass 37, count 2 2006.286.01:42:07.16#ibcon#end of sib2, iclass 37, count 2 2006.286.01:42:07.16#ibcon#*mode == 0, iclass 37, count 2 2006.286.01:42:07.16#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.01:42:07.16#ibcon#[27=AT04-05\r\n] 2006.286.01:42:07.16#ibcon#*before write, iclass 37, count 2 2006.286.01:42:07.16#ibcon#enter sib2, iclass 37, count 2 2006.286.01:42:07.16#ibcon#flushed, iclass 37, count 2 2006.286.01:42:07.16#ibcon#about to write, iclass 37, count 2 2006.286.01:42:07.16#ibcon#wrote, iclass 37, count 2 2006.286.01:42:07.16#ibcon#about to read 3, iclass 37, count 2 2006.286.01:42:07.19#ibcon#read 3, iclass 37, count 2 2006.286.01:42:07.19#ibcon#about to read 4, iclass 37, count 2 2006.286.01:42:07.19#ibcon#read 4, iclass 37, count 2 2006.286.01:42:07.19#ibcon#about to read 5, iclass 37, count 2 2006.286.01:42:07.19#ibcon#read 5, iclass 37, count 2 2006.286.01:42:07.19#ibcon#about to read 6, iclass 37, count 2 2006.286.01:42:07.19#ibcon#read 6, iclass 37, count 2 2006.286.01:42:07.19#ibcon#end of sib2, iclass 37, count 2 2006.286.01:42:07.19#ibcon#*after write, iclass 37, count 2 2006.286.01:42:07.19#ibcon#*before return 0, iclass 37, count 2 2006.286.01:42:07.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:42:07.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:42:07.19#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.01:42:07.19#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:07.19#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:42:07.31#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:42:07.31#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:42:07.31#ibcon#enter wrdev, iclass 37, count 0 2006.286.01:42:07.31#ibcon#first serial, iclass 37, count 0 2006.286.01:42:07.31#ibcon#enter sib2, iclass 37, count 0 2006.286.01:42:07.31#ibcon#flushed, iclass 37, count 0 2006.286.01:42:07.31#ibcon#about to write, iclass 37, count 0 2006.286.01:42:07.31#ibcon#wrote, iclass 37, count 0 2006.286.01:42:07.31#ibcon#about to read 3, iclass 37, count 0 2006.286.01:42:07.33#ibcon#read 3, iclass 37, count 0 2006.286.01:42:07.33#ibcon#about to read 4, iclass 37, count 0 2006.286.01:42:07.33#ibcon#read 4, iclass 37, count 0 2006.286.01:42:07.33#ibcon#about to read 5, iclass 37, count 0 2006.286.01:42:07.33#ibcon#read 5, iclass 37, count 0 2006.286.01:42:07.33#ibcon#about to read 6, iclass 37, count 0 2006.286.01:42:07.33#ibcon#read 6, iclass 37, count 0 2006.286.01:42:07.33#ibcon#end of sib2, iclass 37, count 0 2006.286.01:42:07.33#ibcon#*mode == 0, iclass 37, count 0 2006.286.01:42:07.33#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.01:42:07.33#ibcon#[27=USB\r\n] 2006.286.01:42:07.33#ibcon#*before write, iclass 37, count 0 2006.286.01:42:07.33#ibcon#enter sib2, iclass 37, count 0 2006.286.01:42:07.33#ibcon#flushed, iclass 37, count 0 2006.286.01:42:07.33#ibcon#about to write, iclass 37, count 0 2006.286.01:42:07.33#ibcon#wrote, iclass 37, count 0 2006.286.01:42:07.33#ibcon#about to read 3, iclass 37, count 0 2006.286.01:42:07.36#ibcon#read 3, iclass 37, count 0 2006.286.01:42:07.36#ibcon#about to read 4, iclass 37, count 0 2006.286.01:42:07.36#ibcon#read 4, iclass 37, count 0 2006.286.01:42:07.36#ibcon#about to read 5, iclass 37, count 0 2006.286.01:42:07.36#ibcon#read 5, iclass 37, count 0 2006.286.01:42:07.36#ibcon#about to read 6, iclass 37, count 0 2006.286.01:42:07.36#ibcon#read 6, iclass 37, count 0 2006.286.01:42:07.36#ibcon#end of sib2, iclass 37, count 0 2006.286.01:42:07.36#ibcon#*after write, iclass 37, count 0 2006.286.01:42:07.36#ibcon#*before return 0, iclass 37, count 0 2006.286.01:42:07.36#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:42:07.36#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:42:07.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.01:42:07.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.01:42:07.36$vck44/vblo=5,709.99 2006.286.01:42:07.36#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.01:42:07.36#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.01:42:07.36#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:07.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:42:07.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:42:07.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:42:07.36#ibcon#enter wrdev, iclass 39, count 0 2006.286.01:42:07.36#ibcon#first serial, iclass 39, count 0 2006.286.01:42:07.36#ibcon#enter sib2, iclass 39, count 0 2006.286.01:42:07.36#ibcon#flushed, iclass 39, count 0 2006.286.01:42:07.36#ibcon#about to write, iclass 39, count 0 2006.286.01:42:07.36#ibcon#wrote, iclass 39, count 0 2006.286.01:42:07.36#ibcon#about to read 3, iclass 39, count 0 2006.286.01:42:07.38#ibcon#read 3, iclass 39, count 0 2006.286.01:42:07.38#ibcon#about to read 4, iclass 39, count 0 2006.286.01:42:07.38#ibcon#read 4, iclass 39, count 0 2006.286.01:42:07.38#ibcon#about to read 5, iclass 39, count 0 2006.286.01:42:07.38#ibcon#read 5, iclass 39, count 0 2006.286.01:42:07.38#ibcon#about to read 6, iclass 39, count 0 2006.286.01:42:07.38#ibcon#read 6, iclass 39, count 0 2006.286.01:42:07.38#ibcon#end of sib2, iclass 39, count 0 2006.286.01:42:07.38#ibcon#*mode == 0, iclass 39, count 0 2006.286.01:42:07.38#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.01:42:07.38#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:42:07.38#ibcon#*before write, iclass 39, count 0 2006.286.01:42:07.38#ibcon#enter sib2, iclass 39, count 0 2006.286.01:42:07.38#ibcon#flushed, iclass 39, count 0 2006.286.01:42:07.38#ibcon#about to write, iclass 39, count 0 2006.286.01:42:07.38#ibcon#wrote, iclass 39, count 0 2006.286.01:42:07.38#ibcon#about to read 3, iclass 39, count 0 2006.286.01:42:07.42#ibcon#read 3, iclass 39, count 0 2006.286.01:42:07.42#ibcon#about to read 4, iclass 39, count 0 2006.286.01:42:07.42#ibcon#read 4, iclass 39, count 0 2006.286.01:42:07.42#ibcon#about to read 5, iclass 39, count 0 2006.286.01:42:07.42#ibcon#read 5, iclass 39, count 0 2006.286.01:42:07.42#ibcon#about to read 6, iclass 39, count 0 2006.286.01:42:07.42#ibcon#read 6, iclass 39, count 0 2006.286.01:42:07.42#ibcon#end of sib2, iclass 39, count 0 2006.286.01:42:07.42#ibcon#*after write, iclass 39, count 0 2006.286.01:42:07.42#ibcon#*before return 0, iclass 39, count 0 2006.286.01:42:07.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:42:07.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:42:07.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.01:42:07.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.01:42:07.42$vck44/vb=5,4 2006.286.01:42:07.42#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.01:42:07.42#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.01:42:07.42#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:07.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:42:07.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:42:07.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:42:07.48#ibcon#enter wrdev, iclass 3, count 2 2006.286.01:42:07.48#ibcon#first serial, iclass 3, count 2 2006.286.01:42:07.48#ibcon#enter sib2, iclass 3, count 2 2006.286.01:42:07.48#ibcon#flushed, iclass 3, count 2 2006.286.01:42:07.48#ibcon#about to write, iclass 3, count 2 2006.286.01:42:07.48#ibcon#wrote, iclass 3, count 2 2006.286.01:42:07.48#ibcon#about to read 3, iclass 3, count 2 2006.286.01:42:07.50#ibcon#read 3, iclass 3, count 2 2006.286.01:42:07.50#ibcon#about to read 4, iclass 3, count 2 2006.286.01:42:07.50#ibcon#read 4, iclass 3, count 2 2006.286.01:42:07.50#ibcon#about to read 5, iclass 3, count 2 2006.286.01:42:07.50#ibcon#read 5, iclass 3, count 2 2006.286.01:42:07.50#ibcon#about to read 6, iclass 3, count 2 2006.286.01:42:07.50#ibcon#read 6, iclass 3, count 2 2006.286.01:42:07.50#ibcon#end of sib2, iclass 3, count 2 2006.286.01:42:07.50#ibcon#*mode == 0, iclass 3, count 2 2006.286.01:42:07.50#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.01:42:07.50#ibcon#[27=AT05-04\r\n] 2006.286.01:42:07.50#ibcon#*before write, iclass 3, count 2 2006.286.01:42:07.50#ibcon#enter sib2, iclass 3, count 2 2006.286.01:42:07.50#ibcon#flushed, iclass 3, count 2 2006.286.01:42:07.50#ibcon#about to write, iclass 3, count 2 2006.286.01:42:07.50#ibcon#wrote, iclass 3, count 2 2006.286.01:42:07.50#ibcon#about to read 3, iclass 3, count 2 2006.286.01:42:07.53#ibcon#read 3, iclass 3, count 2 2006.286.01:42:07.53#ibcon#about to read 4, iclass 3, count 2 2006.286.01:42:07.53#ibcon#read 4, iclass 3, count 2 2006.286.01:42:07.53#ibcon#about to read 5, iclass 3, count 2 2006.286.01:42:07.53#ibcon#read 5, iclass 3, count 2 2006.286.01:42:07.53#ibcon#about to read 6, iclass 3, count 2 2006.286.01:42:07.53#ibcon#read 6, iclass 3, count 2 2006.286.01:42:07.53#ibcon#end of sib2, iclass 3, count 2 2006.286.01:42:07.53#ibcon#*after write, iclass 3, count 2 2006.286.01:42:07.53#ibcon#*before return 0, iclass 3, count 2 2006.286.01:42:07.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:42:07.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:42:07.53#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.01:42:07.53#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:07.53#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:42:07.65#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:42:07.65#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:42:07.65#ibcon#enter wrdev, iclass 3, count 0 2006.286.01:42:07.65#ibcon#first serial, iclass 3, count 0 2006.286.01:42:07.65#ibcon#enter sib2, iclass 3, count 0 2006.286.01:42:07.65#ibcon#flushed, iclass 3, count 0 2006.286.01:42:07.65#ibcon#about to write, iclass 3, count 0 2006.286.01:42:07.65#ibcon#wrote, iclass 3, count 0 2006.286.01:42:07.65#ibcon#about to read 3, iclass 3, count 0 2006.286.01:42:07.67#ibcon#read 3, iclass 3, count 0 2006.286.01:42:07.67#ibcon#about to read 4, iclass 3, count 0 2006.286.01:42:07.67#ibcon#read 4, iclass 3, count 0 2006.286.01:42:07.67#ibcon#about to read 5, iclass 3, count 0 2006.286.01:42:07.67#ibcon#read 5, iclass 3, count 0 2006.286.01:42:07.67#ibcon#about to read 6, iclass 3, count 0 2006.286.01:42:07.67#ibcon#read 6, iclass 3, count 0 2006.286.01:42:07.67#ibcon#end of sib2, iclass 3, count 0 2006.286.01:42:07.67#ibcon#*mode == 0, iclass 3, count 0 2006.286.01:42:07.67#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.01:42:07.67#ibcon#[27=USB\r\n] 2006.286.01:42:07.67#ibcon#*before write, iclass 3, count 0 2006.286.01:42:07.67#ibcon#enter sib2, iclass 3, count 0 2006.286.01:42:07.67#ibcon#flushed, iclass 3, count 0 2006.286.01:42:07.67#ibcon#about to write, iclass 3, count 0 2006.286.01:42:07.67#ibcon#wrote, iclass 3, count 0 2006.286.01:42:07.67#ibcon#about to read 3, iclass 3, count 0 2006.286.01:42:07.70#ibcon#read 3, iclass 3, count 0 2006.286.01:42:07.70#ibcon#about to read 4, iclass 3, count 0 2006.286.01:42:07.70#ibcon#read 4, iclass 3, count 0 2006.286.01:42:07.70#ibcon#about to read 5, iclass 3, count 0 2006.286.01:42:07.70#ibcon#read 5, iclass 3, count 0 2006.286.01:42:07.70#ibcon#about to read 6, iclass 3, count 0 2006.286.01:42:07.70#ibcon#read 6, iclass 3, count 0 2006.286.01:42:07.70#ibcon#end of sib2, iclass 3, count 0 2006.286.01:42:07.70#ibcon#*after write, iclass 3, count 0 2006.286.01:42:07.70#ibcon#*before return 0, iclass 3, count 0 2006.286.01:42:07.70#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:42:07.70#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:42:07.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.01:42:07.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.01:42:07.70$vck44/vblo=6,719.99 2006.286.01:42:07.70#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.01:42:07.70#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.01:42:07.70#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:07.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:42:07.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:42:07.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:42:07.70#ibcon#enter wrdev, iclass 5, count 0 2006.286.01:42:07.70#ibcon#first serial, iclass 5, count 0 2006.286.01:42:07.70#ibcon#enter sib2, iclass 5, count 0 2006.286.01:42:07.70#ibcon#flushed, iclass 5, count 0 2006.286.01:42:07.70#ibcon#about to write, iclass 5, count 0 2006.286.01:42:07.70#ibcon#wrote, iclass 5, count 0 2006.286.01:42:07.70#ibcon#about to read 3, iclass 5, count 0 2006.286.01:42:07.72#ibcon#read 3, iclass 5, count 0 2006.286.01:42:07.72#ibcon#about to read 4, iclass 5, count 0 2006.286.01:42:07.72#ibcon#read 4, iclass 5, count 0 2006.286.01:42:07.72#ibcon#about to read 5, iclass 5, count 0 2006.286.01:42:07.72#ibcon#read 5, iclass 5, count 0 2006.286.01:42:07.72#ibcon#about to read 6, iclass 5, count 0 2006.286.01:42:07.72#ibcon#read 6, iclass 5, count 0 2006.286.01:42:07.72#ibcon#end of sib2, iclass 5, count 0 2006.286.01:42:07.72#ibcon#*mode == 0, iclass 5, count 0 2006.286.01:42:07.72#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.01:42:07.72#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:42:07.72#ibcon#*before write, iclass 5, count 0 2006.286.01:42:07.72#ibcon#enter sib2, iclass 5, count 0 2006.286.01:42:07.72#ibcon#flushed, iclass 5, count 0 2006.286.01:42:07.72#ibcon#about to write, iclass 5, count 0 2006.286.01:42:07.72#ibcon#wrote, iclass 5, count 0 2006.286.01:42:07.72#ibcon#about to read 3, iclass 5, count 0 2006.286.01:42:07.76#ibcon#read 3, iclass 5, count 0 2006.286.01:42:07.76#ibcon#about to read 4, iclass 5, count 0 2006.286.01:42:07.76#ibcon#read 4, iclass 5, count 0 2006.286.01:42:07.76#ibcon#about to read 5, iclass 5, count 0 2006.286.01:42:07.76#ibcon#read 5, iclass 5, count 0 2006.286.01:42:07.76#ibcon#about to read 6, iclass 5, count 0 2006.286.01:42:07.76#ibcon#read 6, iclass 5, count 0 2006.286.01:42:07.76#ibcon#end of sib2, iclass 5, count 0 2006.286.01:42:07.76#ibcon#*after write, iclass 5, count 0 2006.286.01:42:07.76#ibcon#*before return 0, iclass 5, count 0 2006.286.01:42:07.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:42:07.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:42:07.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.01:42:07.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.01:42:07.76$vck44/vb=6,3 2006.286.01:42:07.76#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.01:42:07.76#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.01:42:07.76#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:07.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:42:07.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:42:07.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:42:07.82#ibcon#enter wrdev, iclass 7, count 2 2006.286.01:42:07.82#ibcon#first serial, iclass 7, count 2 2006.286.01:42:07.82#ibcon#enter sib2, iclass 7, count 2 2006.286.01:42:07.82#ibcon#flushed, iclass 7, count 2 2006.286.01:42:07.82#ibcon#about to write, iclass 7, count 2 2006.286.01:42:07.82#ibcon#wrote, iclass 7, count 2 2006.286.01:42:07.82#ibcon#about to read 3, iclass 7, count 2 2006.286.01:42:07.84#ibcon#read 3, iclass 7, count 2 2006.286.01:42:07.84#ibcon#about to read 4, iclass 7, count 2 2006.286.01:42:07.84#ibcon#read 4, iclass 7, count 2 2006.286.01:42:07.84#ibcon#about to read 5, iclass 7, count 2 2006.286.01:42:07.84#ibcon#read 5, iclass 7, count 2 2006.286.01:42:07.84#ibcon#about to read 6, iclass 7, count 2 2006.286.01:42:07.84#ibcon#read 6, iclass 7, count 2 2006.286.01:42:07.84#ibcon#end of sib2, iclass 7, count 2 2006.286.01:42:07.84#ibcon#*mode == 0, iclass 7, count 2 2006.286.01:42:07.84#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.01:42:07.84#ibcon#[27=AT06-03\r\n] 2006.286.01:42:07.84#ibcon#*before write, iclass 7, count 2 2006.286.01:42:07.84#ibcon#enter sib2, iclass 7, count 2 2006.286.01:42:07.84#ibcon#flushed, iclass 7, count 2 2006.286.01:42:07.84#ibcon#about to write, iclass 7, count 2 2006.286.01:42:07.84#ibcon#wrote, iclass 7, count 2 2006.286.01:42:07.84#ibcon#about to read 3, iclass 7, count 2 2006.286.01:42:07.87#ibcon#read 3, iclass 7, count 2 2006.286.01:42:07.87#ibcon#about to read 4, iclass 7, count 2 2006.286.01:42:07.87#ibcon#read 4, iclass 7, count 2 2006.286.01:42:07.87#ibcon#about to read 5, iclass 7, count 2 2006.286.01:42:07.87#ibcon#read 5, iclass 7, count 2 2006.286.01:42:07.87#ibcon#about to read 6, iclass 7, count 2 2006.286.01:42:07.87#ibcon#read 6, iclass 7, count 2 2006.286.01:42:07.87#ibcon#end of sib2, iclass 7, count 2 2006.286.01:42:07.87#ibcon#*after write, iclass 7, count 2 2006.286.01:42:07.87#ibcon#*before return 0, iclass 7, count 2 2006.286.01:42:07.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:42:07.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:42:07.87#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.01:42:07.87#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:07.87#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:42:07.99#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:42:07.99#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:42:07.99#ibcon#enter wrdev, iclass 7, count 0 2006.286.01:42:07.99#ibcon#first serial, iclass 7, count 0 2006.286.01:42:07.99#ibcon#enter sib2, iclass 7, count 0 2006.286.01:42:07.99#ibcon#flushed, iclass 7, count 0 2006.286.01:42:07.99#ibcon#about to write, iclass 7, count 0 2006.286.01:42:07.99#ibcon#wrote, iclass 7, count 0 2006.286.01:42:07.99#ibcon#about to read 3, iclass 7, count 0 2006.286.01:42:08.01#ibcon#read 3, iclass 7, count 0 2006.286.01:42:08.01#ibcon#about to read 4, iclass 7, count 0 2006.286.01:42:08.01#ibcon#read 4, iclass 7, count 0 2006.286.01:42:08.01#ibcon#about to read 5, iclass 7, count 0 2006.286.01:42:08.01#ibcon#read 5, iclass 7, count 0 2006.286.01:42:08.01#ibcon#about to read 6, iclass 7, count 0 2006.286.01:42:08.01#ibcon#read 6, iclass 7, count 0 2006.286.01:42:08.01#ibcon#end of sib2, iclass 7, count 0 2006.286.01:42:08.01#ibcon#*mode == 0, iclass 7, count 0 2006.286.01:42:08.01#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.01:42:08.01#ibcon#[27=USB\r\n] 2006.286.01:42:08.01#ibcon#*before write, iclass 7, count 0 2006.286.01:42:08.01#ibcon#enter sib2, iclass 7, count 0 2006.286.01:42:08.01#ibcon#flushed, iclass 7, count 0 2006.286.01:42:08.01#ibcon#about to write, iclass 7, count 0 2006.286.01:42:08.01#ibcon#wrote, iclass 7, count 0 2006.286.01:42:08.01#ibcon#about to read 3, iclass 7, count 0 2006.286.01:42:08.04#ibcon#read 3, iclass 7, count 0 2006.286.01:42:08.04#ibcon#about to read 4, iclass 7, count 0 2006.286.01:42:08.04#ibcon#read 4, iclass 7, count 0 2006.286.01:42:08.04#ibcon#about to read 5, iclass 7, count 0 2006.286.01:42:08.04#ibcon#read 5, iclass 7, count 0 2006.286.01:42:08.04#ibcon#about to read 6, iclass 7, count 0 2006.286.01:42:08.04#ibcon#read 6, iclass 7, count 0 2006.286.01:42:08.04#ibcon#end of sib2, iclass 7, count 0 2006.286.01:42:08.04#ibcon#*after write, iclass 7, count 0 2006.286.01:42:08.04#ibcon#*before return 0, iclass 7, count 0 2006.286.01:42:08.04#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:42:08.04#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:42:08.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.01:42:08.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.01:42:08.04$vck44/vblo=7,734.99 2006.286.01:42:08.04#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.01:42:08.04#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.01:42:08.04#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:08.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:42:08.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:42:08.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:42:08.04#ibcon#enter wrdev, iclass 11, count 0 2006.286.01:42:08.04#ibcon#first serial, iclass 11, count 0 2006.286.01:42:08.04#ibcon#enter sib2, iclass 11, count 0 2006.286.01:42:08.04#ibcon#flushed, iclass 11, count 0 2006.286.01:42:08.04#ibcon#about to write, iclass 11, count 0 2006.286.01:42:08.04#ibcon#wrote, iclass 11, count 0 2006.286.01:42:08.04#ibcon#about to read 3, iclass 11, count 0 2006.286.01:42:08.06#ibcon#read 3, iclass 11, count 0 2006.286.01:42:08.06#ibcon#about to read 4, iclass 11, count 0 2006.286.01:42:08.06#ibcon#read 4, iclass 11, count 0 2006.286.01:42:08.06#ibcon#about to read 5, iclass 11, count 0 2006.286.01:42:08.06#ibcon#read 5, iclass 11, count 0 2006.286.01:42:08.06#ibcon#about to read 6, iclass 11, count 0 2006.286.01:42:08.06#ibcon#read 6, iclass 11, count 0 2006.286.01:42:08.06#ibcon#end of sib2, iclass 11, count 0 2006.286.01:42:08.06#ibcon#*mode == 0, iclass 11, count 0 2006.286.01:42:08.06#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.01:42:08.06#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:42:08.06#ibcon#*before write, iclass 11, count 0 2006.286.01:42:08.06#ibcon#enter sib2, iclass 11, count 0 2006.286.01:42:08.06#ibcon#flushed, iclass 11, count 0 2006.286.01:42:08.06#ibcon#about to write, iclass 11, count 0 2006.286.01:42:08.06#ibcon#wrote, iclass 11, count 0 2006.286.01:42:08.06#ibcon#about to read 3, iclass 11, count 0 2006.286.01:42:08.10#ibcon#read 3, iclass 11, count 0 2006.286.01:42:08.10#ibcon#about to read 4, iclass 11, count 0 2006.286.01:42:08.10#ibcon#read 4, iclass 11, count 0 2006.286.01:42:08.10#ibcon#about to read 5, iclass 11, count 0 2006.286.01:42:08.10#ibcon#read 5, iclass 11, count 0 2006.286.01:42:08.10#ibcon#about to read 6, iclass 11, count 0 2006.286.01:42:08.10#ibcon#read 6, iclass 11, count 0 2006.286.01:42:08.10#ibcon#end of sib2, iclass 11, count 0 2006.286.01:42:08.10#ibcon#*after write, iclass 11, count 0 2006.286.01:42:08.10#ibcon#*before return 0, iclass 11, count 0 2006.286.01:42:08.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:42:08.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:42:08.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.01:42:08.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.01:42:08.10$vck44/vb=7,4 2006.286.01:42:08.10#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.01:42:08.10#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.01:42:08.10#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:08.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:42:08.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:42:08.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:42:08.16#ibcon#enter wrdev, iclass 13, count 2 2006.286.01:42:08.16#ibcon#first serial, iclass 13, count 2 2006.286.01:42:08.16#ibcon#enter sib2, iclass 13, count 2 2006.286.01:42:08.16#ibcon#flushed, iclass 13, count 2 2006.286.01:42:08.16#ibcon#about to write, iclass 13, count 2 2006.286.01:42:08.16#ibcon#wrote, iclass 13, count 2 2006.286.01:42:08.16#ibcon#about to read 3, iclass 13, count 2 2006.286.01:42:08.18#ibcon#read 3, iclass 13, count 2 2006.286.01:42:08.18#ibcon#about to read 4, iclass 13, count 2 2006.286.01:42:08.18#ibcon#read 4, iclass 13, count 2 2006.286.01:42:08.18#ibcon#about to read 5, iclass 13, count 2 2006.286.01:42:08.18#ibcon#read 5, iclass 13, count 2 2006.286.01:42:08.18#ibcon#about to read 6, iclass 13, count 2 2006.286.01:42:08.18#ibcon#read 6, iclass 13, count 2 2006.286.01:42:08.18#ibcon#end of sib2, iclass 13, count 2 2006.286.01:42:08.18#ibcon#*mode == 0, iclass 13, count 2 2006.286.01:42:08.18#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.01:42:08.18#ibcon#[27=AT07-04\r\n] 2006.286.01:42:08.18#ibcon#*before write, iclass 13, count 2 2006.286.01:42:08.18#ibcon#enter sib2, iclass 13, count 2 2006.286.01:42:08.18#ibcon#flushed, iclass 13, count 2 2006.286.01:42:08.18#ibcon#about to write, iclass 13, count 2 2006.286.01:42:08.18#ibcon#wrote, iclass 13, count 2 2006.286.01:42:08.18#ibcon#about to read 3, iclass 13, count 2 2006.286.01:42:08.21#ibcon#read 3, iclass 13, count 2 2006.286.01:42:08.21#ibcon#about to read 4, iclass 13, count 2 2006.286.01:42:08.21#ibcon#read 4, iclass 13, count 2 2006.286.01:42:08.21#ibcon#about to read 5, iclass 13, count 2 2006.286.01:42:08.21#ibcon#read 5, iclass 13, count 2 2006.286.01:42:08.21#ibcon#about to read 6, iclass 13, count 2 2006.286.01:42:08.21#ibcon#read 6, iclass 13, count 2 2006.286.01:42:08.21#ibcon#end of sib2, iclass 13, count 2 2006.286.01:42:08.21#ibcon#*after write, iclass 13, count 2 2006.286.01:42:08.21#ibcon#*before return 0, iclass 13, count 2 2006.286.01:42:08.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:42:08.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:42:08.21#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.01:42:08.21#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:08.21#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:42:08.33#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:42:08.33#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:42:08.33#ibcon#enter wrdev, iclass 13, count 0 2006.286.01:42:08.33#ibcon#first serial, iclass 13, count 0 2006.286.01:42:08.33#ibcon#enter sib2, iclass 13, count 0 2006.286.01:42:08.33#ibcon#flushed, iclass 13, count 0 2006.286.01:42:08.33#ibcon#about to write, iclass 13, count 0 2006.286.01:42:08.33#ibcon#wrote, iclass 13, count 0 2006.286.01:42:08.33#ibcon#about to read 3, iclass 13, count 0 2006.286.01:42:08.35#ibcon#read 3, iclass 13, count 0 2006.286.01:42:08.35#ibcon#about to read 4, iclass 13, count 0 2006.286.01:42:08.35#ibcon#read 4, iclass 13, count 0 2006.286.01:42:08.35#ibcon#about to read 5, iclass 13, count 0 2006.286.01:42:08.35#ibcon#read 5, iclass 13, count 0 2006.286.01:42:08.35#ibcon#about to read 6, iclass 13, count 0 2006.286.01:42:08.35#ibcon#read 6, iclass 13, count 0 2006.286.01:42:08.35#ibcon#end of sib2, iclass 13, count 0 2006.286.01:42:08.35#ibcon#*mode == 0, iclass 13, count 0 2006.286.01:42:08.35#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.01:42:08.35#ibcon#[27=USB\r\n] 2006.286.01:42:08.35#ibcon#*before write, iclass 13, count 0 2006.286.01:42:08.35#ibcon#enter sib2, iclass 13, count 0 2006.286.01:42:08.35#ibcon#flushed, iclass 13, count 0 2006.286.01:42:08.35#ibcon#about to write, iclass 13, count 0 2006.286.01:42:08.35#ibcon#wrote, iclass 13, count 0 2006.286.01:42:08.35#ibcon#about to read 3, iclass 13, count 0 2006.286.01:42:08.38#ibcon#read 3, iclass 13, count 0 2006.286.01:42:08.38#ibcon#about to read 4, iclass 13, count 0 2006.286.01:42:08.38#ibcon#read 4, iclass 13, count 0 2006.286.01:42:08.38#ibcon#about to read 5, iclass 13, count 0 2006.286.01:42:08.38#ibcon#read 5, iclass 13, count 0 2006.286.01:42:08.38#ibcon#about to read 6, iclass 13, count 0 2006.286.01:42:08.38#ibcon#read 6, iclass 13, count 0 2006.286.01:42:08.38#ibcon#end of sib2, iclass 13, count 0 2006.286.01:42:08.38#ibcon#*after write, iclass 13, count 0 2006.286.01:42:08.38#ibcon#*before return 0, iclass 13, count 0 2006.286.01:42:08.38#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:42:08.38#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:42:08.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.01:42:08.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.01:42:08.38$vck44/vblo=8,744.99 2006.286.01:42:08.38#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.01:42:08.38#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.01:42:08.38#ibcon#ireg 17 cls_cnt 0 2006.286.01:42:08.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:42:08.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:42:08.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:42:08.38#ibcon#enter wrdev, iclass 15, count 0 2006.286.01:42:08.38#ibcon#first serial, iclass 15, count 0 2006.286.01:42:08.38#ibcon#enter sib2, iclass 15, count 0 2006.286.01:42:08.38#ibcon#flushed, iclass 15, count 0 2006.286.01:42:08.38#ibcon#about to write, iclass 15, count 0 2006.286.01:42:08.38#ibcon#wrote, iclass 15, count 0 2006.286.01:42:08.38#ibcon#about to read 3, iclass 15, count 0 2006.286.01:42:08.40#ibcon#read 3, iclass 15, count 0 2006.286.01:42:08.40#ibcon#about to read 4, iclass 15, count 0 2006.286.01:42:08.40#ibcon#read 4, iclass 15, count 0 2006.286.01:42:08.40#ibcon#about to read 5, iclass 15, count 0 2006.286.01:42:08.40#ibcon#read 5, iclass 15, count 0 2006.286.01:42:08.40#ibcon#about to read 6, iclass 15, count 0 2006.286.01:42:08.40#ibcon#read 6, iclass 15, count 0 2006.286.01:42:08.40#ibcon#end of sib2, iclass 15, count 0 2006.286.01:42:08.40#ibcon#*mode == 0, iclass 15, count 0 2006.286.01:42:08.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.01:42:08.40#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:42:08.40#ibcon#*before write, iclass 15, count 0 2006.286.01:42:08.40#ibcon#enter sib2, iclass 15, count 0 2006.286.01:42:08.40#ibcon#flushed, iclass 15, count 0 2006.286.01:42:08.40#ibcon#about to write, iclass 15, count 0 2006.286.01:42:08.40#ibcon#wrote, iclass 15, count 0 2006.286.01:42:08.40#ibcon#about to read 3, iclass 15, count 0 2006.286.01:42:08.44#ibcon#read 3, iclass 15, count 0 2006.286.01:42:08.44#ibcon#about to read 4, iclass 15, count 0 2006.286.01:42:08.44#ibcon#read 4, iclass 15, count 0 2006.286.01:42:08.44#ibcon#about to read 5, iclass 15, count 0 2006.286.01:42:08.44#ibcon#read 5, iclass 15, count 0 2006.286.01:42:08.44#ibcon#about to read 6, iclass 15, count 0 2006.286.01:42:08.44#ibcon#read 6, iclass 15, count 0 2006.286.01:42:08.44#ibcon#end of sib2, iclass 15, count 0 2006.286.01:42:08.44#ibcon#*after write, iclass 15, count 0 2006.286.01:42:08.44#ibcon#*before return 0, iclass 15, count 0 2006.286.01:42:08.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:42:08.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:42:08.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.01:42:08.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.01:42:08.44$vck44/vb=8,4 2006.286.01:42:08.44#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.01:42:08.44#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.01:42:08.44#ibcon#ireg 11 cls_cnt 2 2006.286.01:42:08.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:42:08.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:42:08.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:42:08.50#ibcon#enter wrdev, iclass 17, count 2 2006.286.01:42:08.50#ibcon#first serial, iclass 17, count 2 2006.286.01:42:08.50#ibcon#enter sib2, iclass 17, count 2 2006.286.01:42:08.50#ibcon#flushed, iclass 17, count 2 2006.286.01:42:08.50#ibcon#about to write, iclass 17, count 2 2006.286.01:42:08.50#ibcon#wrote, iclass 17, count 2 2006.286.01:42:08.50#ibcon#about to read 3, iclass 17, count 2 2006.286.01:42:08.52#ibcon#read 3, iclass 17, count 2 2006.286.01:42:08.52#ibcon#about to read 4, iclass 17, count 2 2006.286.01:42:08.52#ibcon#read 4, iclass 17, count 2 2006.286.01:42:08.52#ibcon#about to read 5, iclass 17, count 2 2006.286.01:42:08.52#ibcon#read 5, iclass 17, count 2 2006.286.01:42:08.52#ibcon#about to read 6, iclass 17, count 2 2006.286.01:42:08.52#ibcon#read 6, iclass 17, count 2 2006.286.01:42:08.52#ibcon#end of sib2, iclass 17, count 2 2006.286.01:42:08.52#ibcon#*mode == 0, iclass 17, count 2 2006.286.01:42:08.52#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.01:42:08.52#ibcon#[27=AT08-04\r\n] 2006.286.01:42:08.52#ibcon#*before write, iclass 17, count 2 2006.286.01:42:08.52#ibcon#enter sib2, iclass 17, count 2 2006.286.01:42:08.52#ibcon#flushed, iclass 17, count 2 2006.286.01:42:08.52#ibcon#about to write, iclass 17, count 2 2006.286.01:42:08.52#ibcon#wrote, iclass 17, count 2 2006.286.01:42:08.52#ibcon#about to read 3, iclass 17, count 2 2006.286.01:42:08.55#ibcon#read 3, iclass 17, count 2 2006.286.01:42:08.55#ibcon#about to read 4, iclass 17, count 2 2006.286.01:42:08.55#ibcon#read 4, iclass 17, count 2 2006.286.01:42:08.55#ibcon#about to read 5, iclass 17, count 2 2006.286.01:42:08.55#ibcon#read 5, iclass 17, count 2 2006.286.01:42:08.55#ibcon#about to read 6, iclass 17, count 2 2006.286.01:42:08.55#ibcon#read 6, iclass 17, count 2 2006.286.01:42:08.55#ibcon#end of sib2, iclass 17, count 2 2006.286.01:42:08.55#ibcon#*after write, iclass 17, count 2 2006.286.01:42:08.55#ibcon#*before return 0, iclass 17, count 2 2006.286.01:42:08.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:42:08.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:42:08.55#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.01:42:08.55#ibcon#ireg 7 cls_cnt 0 2006.286.01:42:08.55#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:42:08.67#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:42:08.67#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:42:08.67#ibcon#enter wrdev, iclass 17, count 0 2006.286.01:42:08.67#ibcon#first serial, iclass 17, count 0 2006.286.01:42:08.67#ibcon#enter sib2, iclass 17, count 0 2006.286.01:42:08.67#ibcon#flushed, iclass 17, count 0 2006.286.01:42:08.67#ibcon#about to write, iclass 17, count 0 2006.286.01:42:08.67#ibcon#wrote, iclass 17, count 0 2006.286.01:42:08.67#ibcon#about to read 3, iclass 17, count 0 2006.286.01:42:08.69#ibcon#read 3, iclass 17, count 0 2006.286.01:42:08.69#ibcon#about to read 4, iclass 17, count 0 2006.286.01:42:08.69#ibcon#read 4, iclass 17, count 0 2006.286.01:42:08.69#ibcon#about to read 5, iclass 17, count 0 2006.286.01:42:08.69#ibcon#read 5, iclass 17, count 0 2006.286.01:42:08.69#ibcon#about to read 6, iclass 17, count 0 2006.286.01:42:08.69#ibcon#read 6, iclass 17, count 0 2006.286.01:42:08.69#ibcon#end of sib2, iclass 17, count 0 2006.286.01:42:08.69#ibcon#*mode == 0, iclass 17, count 0 2006.286.01:42:08.69#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.01:42:08.69#ibcon#[27=USB\r\n] 2006.286.01:42:08.69#ibcon#*before write, iclass 17, count 0 2006.286.01:42:08.69#ibcon#enter sib2, iclass 17, count 0 2006.286.01:42:08.69#ibcon#flushed, iclass 17, count 0 2006.286.01:42:08.69#ibcon#about to write, iclass 17, count 0 2006.286.01:42:08.69#ibcon#wrote, iclass 17, count 0 2006.286.01:42:08.69#ibcon#about to read 3, iclass 17, count 0 2006.286.01:42:08.72#ibcon#read 3, iclass 17, count 0 2006.286.01:42:08.72#ibcon#about to read 4, iclass 17, count 0 2006.286.01:42:08.72#ibcon#read 4, iclass 17, count 0 2006.286.01:42:08.72#ibcon#about to read 5, iclass 17, count 0 2006.286.01:42:08.72#ibcon#read 5, iclass 17, count 0 2006.286.01:42:08.72#ibcon#about to read 6, iclass 17, count 0 2006.286.01:42:08.72#ibcon#read 6, iclass 17, count 0 2006.286.01:42:08.72#ibcon#end of sib2, iclass 17, count 0 2006.286.01:42:08.72#ibcon#*after write, iclass 17, count 0 2006.286.01:42:08.72#ibcon#*before return 0, iclass 17, count 0 2006.286.01:42:08.72#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:42:08.72#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:42:08.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.01:42:08.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.01:42:08.72$vck44/vabw=wide 2006.286.01:42:08.72#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.01:42:08.72#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.01:42:08.72#ibcon#ireg 8 cls_cnt 0 2006.286.01:42:08.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:42:08.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:42:08.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:42:08.72#ibcon#enter wrdev, iclass 19, count 0 2006.286.01:42:08.72#ibcon#first serial, iclass 19, count 0 2006.286.01:42:08.72#ibcon#enter sib2, iclass 19, count 0 2006.286.01:42:08.72#ibcon#flushed, iclass 19, count 0 2006.286.01:42:08.72#ibcon#about to write, iclass 19, count 0 2006.286.01:42:08.72#ibcon#wrote, iclass 19, count 0 2006.286.01:42:08.72#ibcon#about to read 3, iclass 19, count 0 2006.286.01:42:08.74#ibcon#read 3, iclass 19, count 0 2006.286.01:42:08.74#ibcon#about to read 4, iclass 19, count 0 2006.286.01:42:08.74#ibcon#read 4, iclass 19, count 0 2006.286.01:42:08.74#ibcon#about to read 5, iclass 19, count 0 2006.286.01:42:08.74#ibcon#read 5, iclass 19, count 0 2006.286.01:42:08.74#ibcon#about to read 6, iclass 19, count 0 2006.286.01:42:08.74#ibcon#read 6, iclass 19, count 0 2006.286.01:42:08.74#ibcon#end of sib2, iclass 19, count 0 2006.286.01:42:08.74#ibcon#*mode == 0, iclass 19, count 0 2006.286.01:42:08.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.01:42:08.74#ibcon#[25=BW32\r\n] 2006.286.01:42:08.74#ibcon#*before write, iclass 19, count 0 2006.286.01:42:08.74#ibcon#enter sib2, iclass 19, count 0 2006.286.01:42:08.74#ibcon#flushed, iclass 19, count 0 2006.286.01:42:08.74#ibcon#about to write, iclass 19, count 0 2006.286.01:42:08.74#ibcon#wrote, iclass 19, count 0 2006.286.01:42:08.74#ibcon#about to read 3, iclass 19, count 0 2006.286.01:42:08.77#ibcon#read 3, iclass 19, count 0 2006.286.01:42:08.77#ibcon#about to read 4, iclass 19, count 0 2006.286.01:42:08.77#ibcon#read 4, iclass 19, count 0 2006.286.01:42:08.77#ibcon#about to read 5, iclass 19, count 0 2006.286.01:42:08.77#ibcon#read 5, iclass 19, count 0 2006.286.01:42:08.77#ibcon#about to read 6, iclass 19, count 0 2006.286.01:42:08.77#ibcon#read 6, iclass 19, count 0 2006.286.01:42:08.77#ibcon#end of sib2, iclass 19, count 0 2006.286.01:42:08.77#ibcon#*after write, iclass 19, count 0 2006.286.01:42:08.77#ibcon#*before return 0, iclass 19, count 0 2006.286.01:42:08.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:42:08.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:42:08.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.01:42:08.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.01:42:08.77$vck44/vbbw=wide 2006.286.01:42:08.77#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.01:42:08.77#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.01:42:08.77#ibcon#ireg 8 cls_cnt 0 2006.286.01:42:08.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:42:08.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:42:08.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:42:08.84#ibcon#enter wrdev, iclass 21, count 0 2006.286.01:42:08.84#ibcon#first serial, iclass 21, count 0 2006.286.01:42:08.84#ibcon#enter sib2, iclass 21, count 0 2006.286.01:42:08.84#ibcon#flushed, iclass 21, count 0 2006.286.01:42:08.84#ibcon#about to write, iclass 21, count 0 2006.286.01:42:08.84#ibcon#wrote, iclass 21, count 0 2006.286.01:42:08.84#ibcon#about to read 3, iclass 21, count 0 2006.286.01:42:08.86#ibcon#read 3, iclass 21, count 0 2006.286.01:42:08.86#ibcon#about to read 4, iclass 21, count 0 2006.286.01:42:08.86#ibcon#read 4, iclass 21, count 0 2006.286.01:42:08.86#ibcon#about to read 5, iclass 21, count 0 2006.286.01:42:08.86#ibcon#read 5, iclass 21, count 0 2006.286.01:42:08.86#ibcon#about to read 6, iclass 21, count 0 2006.286.01:42:08.86#ibcon#read 6, iclass 21, count 0 2006.286.01:42:08.86#ibcon#end of sib2, iclass 21, count 0 2006.286.01:42:08.86#ibcon#*mode == 0, iclass 21, count 0 2006.286.01:42:08.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.01:42:08.86#ibcon#[27=BW32\r\n] 2006.286.01:42:08.86#ibcon#*before write, iclass 21, count 0 2006.286.01:42:08.86#ibcon#enter sib2, iclass 21, count 0 2006.286.01:42:08.86#ibcon#flushed, iclass 21, count 0 2006.286.01:42:08.86#ibcon#about to write, iclass 21, count 0 2006.286.01:42:08.86#ibcon#wrote, iclass 21, count 0 2006.286.01:42:08.86#ibcon#about to read 3, iclass 21, count 0 2006.286.01:42:08.89#ibcon#read 3, iclass 21, count 0 2006.286.01:42:08.89#ibcon#about to read 4, iclass 21, count 0 2006.286.01:42:08.89#ibcon#read 4, iclass 21, count 0 2006.286.01:42:08.89#ibcon#about to read 5, iclass 21, count 0 2006.286.01:42:08.89#ibcon#read 5, iclass 21, count 0 2006.286.01:42:08.89#ibcon#about to read 6, iclass 21, count 0 2006.286.01:42:08.89#ibcon#read 6, iclass 21, count 0 2006.286.01:42:08.89#ibcon#end of sib2, iclass 21, count 0 2006.286.01:42:08.89#ibcon#*after write, iclass 21, count 0 2006.286.01:42:08.89#ibcon#*before return 0, iclass 21, count 0 2006.286.01:42:08.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:42:08.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:42:08.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.01:42:08.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.01:42:08.89$setupk4/ifdk4 2006.286.01:42:08.89$ifdk4/lo= 2006.286.01:42:08.89$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:42:08.89$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:42:08.89$ifdk4/patch= 2006.286.01:42:08.89$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:42:08.89$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:42:08.89$setupk4/!*+20s 2006.286.01:42:09.92#abcon#<5=/04 3.4 6.8 21.19 781016.1\r\n> 2006.286.01:42:09.94#abcon#{5=INTERFACE CLEAR} 2006.286.01:42:10.00#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:42:15.13#trakl#Source acquired 2006.286.01:42:15.13#flagr#flagr/antenna,acquired 2006.286.01:42:20.09#abcon#<5=/04 3.3 6.8 21.19 791016.1\r\n> 2006.286.01:42:20.11#abcon#{5=INTERFACE CLEAR} 2006.286.01:42:20.17#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:42:23.40$setupk4/"tpicd 2006.286.01:42:23.40$setupk4/echo=off 2006.286.01:42:23.40$setupk4/xlog=off 2006.286.01:42:23.40:!2006.286.01:42:31 2006.286.01:42:31.00:preob 2006.286.01:42:31.13/onsource/TRACKING 2006.286.01:42:31.13:!2006.286.01:42:41 2006.286.01:42:41.00:"tape 2006.286.01:42:41.00:"st=record 2006.286.01:42:41.00:data_valid=on 2006.286.01:42:41.00:midob 2006.286.01:42:42.13/onsource/TRACKING 2006.286.01:42:42.13/wx/21.19,1016.1,78 2006.286.01:42:42.19/cable/+6.5024E-03 2006.286.01:42:43.28/va/01,07,usb,yes,40,44 2006.286.01:42:43.28/va/02,06,usb,yes,41,41 2006.286.01:42:43.28/va/03,07,usb,yes,40,42 2006.286.01:42:43.28/va/04,06,usb,yes,42,44 2006.286.01:42:43.28/va/05,03,usb,yes,41,42 2006.286.01:42:43.28/va/06,04,usb,yes,37,37 2006.286.01:42:43.28/va/07,04,usb,yes,38,39 2006.286.01:42:43.28/va/08,03,usb,yes,39,47 2006.286.01:42:43.51/valo/01,524.99,yes,locked 2006.286.01:42:43.51/valo/02,534.99,yes,locked 2006.286.01:42:43.51/valo/03,564.99,yes,locked 2006.286.01:42:43.51/valo/04,624.99,yes,locked 2006.286.01:42:43.51/valo/05,734.99,yes,locked 2006.286.01:42:43.51/valo/06,814.99,yes,locked 2006.286.01:42:43.51/valo/07,864.99,yes,locked 2006.286.01:42:43.51/valo/08,884.99,yes,locked 2006.286.01:42:44.60/vb/01,04,usb,yes,31,40 2006.286.01:42:44.60/vb/02,05,usb,yes,30,41 2006.286.01:42:44.60/vb/03,04,usb,yes,31,36 2006.286.01:42:44.60/vb/04,05,usb,yes,31,30 2006.286.01:42:44.60/vb/05,04,usb,yes,28,30 2006.286.01:42:44.60/vb/06,03,usb,yes,40,36 2006.286.01:42:44.60/vb/07,04,usb,yes,32,32 2006.286.01:42:44.60/vb/08,04,usb,yes,29,33 2006.286.01:42:44.83/vblo/01,629.99,yes,locked 2006.286.01:42:44.83/vblo/02,634.99,yes,locked 2006.286.01:42:44.83/vblo/03,649.99,yes,locked 2006.286.01:42:44.83/vblo/04,679.99,yes,locked 2006.286.01:42:44.83/vblo/05,709.99,yes,locked 2006.286.01:42:44.83/vblo/06,719.99,yes,locked 2006.286.01:42:44.83/vblo/07,734.99,yes,locked 2006.286.01:42:44.83/vblo/08,744.99,yes,locked 2006.286.01:42:44.98/vabw/8 2006.286.01:42:45.13/vbbw/8 2006.286.01:42:45.22/xfe/off,on,12.0 2006.286.01:42:45.61/ifatt/23,28,28,28 2006.286.01:42:46.07/fmout-gps/S +2.73E-07 2006.286.01:42:46.09:!2006.286.01:43:21 2006.286.01:43:21.01:data_valid=off 2006.286.01:43:21.01:"et 2006.286.01:43:21.01:!+3s 2006.286.01:43:24.02:"tape 2006.286.01:43:24.02:postob 2006.286.01:43:24.22/cable/+6.5013E-03 2006.286.01:43:24.22/wx/21.20,1016.1,78 2006.286.01:43:24.28/fmout-gps/S +2.73E-07 2006.286.01:43:24.28:scan_name=286-0144,jd0610,40 2006.286.01:43:24.28:source=3c345,164258.81,394837.0,2000.0,ccw 2006.286.01:43:26.14#flagr#flagr/antenna,new-source 2006.286.01:43:26.14:checkk5 2006.286.01:43:26.57/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:43:26.99/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:43:27.61/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:43:28.01/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:43:28.37/chk_obsdata//k5ts1/T2860142??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.01:43:28.77/chk_obsdata//k5ts2/T2860142??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.01:43:29.37/chk_obsdata//k5ts3/T2860142??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.01:43:29.77/chk_obsdata//k5ts4/T2860142??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.01:43:31.19/k5log//k5ts1_log_newline 2006.286.01:43:31.94/k5log//k5ts2_log_newline 2006.286.01:43:32.66/k5log//k5ts3_log_newline 2006.286.01:43:33.41/k5log//k5ts4_log_newline 2006.286.01:43:33.43/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:43:33.43:setupk4=1 2006.286.01:43:33.43$setupk4/echo=on 2006.286.01:43:33.43$setupk4/pcalon 2006.286.01:43:33.43$pcalon/"no phase cal control is implemented here 2006.286.01:43:33.43$setupk4/"tpicd=stop 2006.286.01:43:33.43$setupk4/"rec=synch_on 2006.286.01:43:33.43$setupk4/"rec_mode=128 2006.286.01:43:33.43$setupk4/!* 2006.286.01:43:33.43$setupk4/recpk4 2006.286.01:43:33.43$recpk4/recpatch= 2006.286.01:43:33.43$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:43:33.43$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:43:33.43$setupk4/vck44 2006.286.01:43:33.43$vck44/valo=1,524.99 2006.286.01:43:33.43#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.01:43:33.43#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.01:43:33.43#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:33.43#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:43:33.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:43:33.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:43:33.43#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:43:33.43#ibcon#first serial, iclass 26, count 0 2006.286.01:43:33.43#ibcon#enter sib2, iclass 26, count 0 2006.286.01:43:33.43#ibcon#flushed, iclass 26, count 0 2006.286.01:43:33.43#ibcon#about to write, iclass 26, count 0 2006.286.01:43:33.43#ibcon#wrote, iclass 26, count 0 2006.286.01:43:33.43#ibcon#about to read 3, iclass 26, count 0 2006.286.01:43:33.45#ibcon#read 3, iclass 26, count 0 2006.286.01:43:33.45#ibcon#about to read 4, iclass 26, count 0 2006.286.01:43:33.45#ibcon#read 4, iclass 26, count 0 2006.286.01:43:33.45#ibcon#about to read 5, iclass 26, count 0 2006.286.01:43:33.45#ibcon#read 5, iclass 26, count 0 2006.286.01:43:33.45#ibcon#about to read 6, iclass 26, count 0 2006.286.01:43:33.45#ibcon#read 6, iclass 26, count 0 2006.286.01:43:33.45#ibcon#end of sib2, iclass 26, count 0 2006.286.01:43:33.45#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:43:33.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:43:33.45#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:43:33.45#ibcon#*before write, iclass 26, count 0 2006.286.01:43:33.45#ibcon#enter sib2, iclass 26, count 0 2006.286.01:43:33.45#ibcon#flushed, iclass 26, count 0 2006.286.01:43:33.45#ibcon#about to write, iclass 26, count 0 2006.286.01:43:33.45#ibcon#wrote, iclass 26, count 0 2006.286.01:43:33.45#ibcon#about to read 3, iclass 26, count 0 2006.286.01:43:33.50#ibcon#read 3, iclass 26, count 0 2006.286.01:43:33.50#ibcon#about to read 4, iclass 26, count 0 2006.286.01:43:33.50#ibcon#read 4, iclass 26, count 0 2006.286.01:43:33.50#ibcon#about to read 5, iclass 26, count 0 2006.286.01:43:33.50#ibcon#read 5, iclass 26, count 0 2006.286.01:43:33.50#ibcon#about to read 6, iclass 26, count 0 2006.286.01:43:33.50#ibcon#read 6, iclass 26, count 0 2006.286.01:43:33.50#ibcon#end of sib2, iclass 26, count 0 2006.286.01:43:33.50#ibcon#*after write, iclass 26, count 0 2006.286.01:43:33.50#ibcon#*before return 0, iclass 26, count 0 2006.286.01:43:33.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:43:33.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:43:33.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:43:33.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:43:33.50$vck44/va=1,7 2006.286.01:43:33.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.01:43:33.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.01:43:33.50#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:33.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:43:33.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:43:33.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:43:33.50#ibcon#enter wrdev, iclass 28, count 2 2006.286.01:43:33.50#ibcon#first serial, iclass 28, count 2 2006.286.01:43:33.50#ibcon#enter sib2, iclass 28, count 2 2006.286.01:43:33.50#ibcon#flushed, iclass 28, count 2 2006.286.01:43:33.50#ibcon#about to write, iclass 28, count 2 2006.286.01:43:33.50#ibcon#wrote, iclass 28, count 2 2006.286.01:43:33.50#ibcon#about to read 3, iclass 28, count 2 2006.286.01:43:33.52#ibcon#read 3, iclass 28, count 2 2006.286.01:43:33.52#ibcon#about to read 4, iclass 28, count 2 2006.286.01:43:33.52#ibcon#read 4, iclass 28, count 2 2006.286.01:43:33.52#ibcon#about to read 5, iclass 28, count 2 2006.286.01:43:33.52#ibcon#read 5, iclass 28, count 2 2006.286.01:43:33.52#ibcon#about to read 6, iclass 28, count 2 2006.286.01:43:33.52#ibcon#read 6, iclass 28, count 2 2006.286.01:43:33.52#ibcon#end of sib2, iclass 28, count 2 2006.286.01:43:33.52#ibcon#*mode == 0, iclass 28, count 2 2006.286.01:43:33.52#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.01:43:33.52#ibcon#[25=AT01-07\r\n] 2006.286.01:43:33.52#ibcon#*before write, iclass 28, count 2 2006.286.01:43:33.52#ibcon#enter sib2, iclass 28, count 2 2006.286.01:43:33.52#ibcon#flushed, iclass 28, count 2 2006.286.01:43:33.52#ibcon#about to write, iclass 28, count 2 2006.286.01:43:33.52#ibcon#wrote, iclass 28, count 2 2006.286.01:43:33.52#ibcon#about to read 3, iclass 28, count 2 2006.286.01:43:33.55#ibcon#read 3, iclass 28, count 2 2006.286.01:43:33.55#ibcon#about to read 4, iclass 28, count 2 2006.286.01:43:33.55#ibcon#read 4, iclass 28, count 2 2006.286.01:43:33.55#ibcon#about to read 5, iclass 28, count 2 2006.286.01:43:33.55#ibcon#read 5, iclass 28, count 2 2006.286.01:43:33.55#ibcon#about to read 6, iclass 28, count 2 2006.286.01:43:33.55#ibcon#read 6, iclass 28, count 2 2006.286.01:43:33.55#ibcon#end of sib2, iclass 28, count 2 2006.286.01:43:33.55#ibcon#*after write, iclass 28, count 2 2006.286.01:43:33.55#ibcon#*before return 0, iclass 28, count 2 2006.286.01:43:33.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:43:33.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:43:33.55#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.01:43:33.55#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:33.55#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:43:33.67#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:43:33.67#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:43:33.67#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:43:33.67#ibcon#first serial, iclass 28, count 0 2006.286.01:43:33.67#ibcon#enter sib2, iclass 28, count 0 2006.286.01:43:33.67#ibcon#flushed, iclass 28, count 0 2006.286.01:43:33.67#ibcon#about to write, iclass 28, count 0 2006.286.01:43:33.67#ibcon#wrote, iclass 28, count 0 2006.286.01:43:33.67#ibcon#about to read 3, iclass 28, count 0 2006.286.01:43:33.69#ibcon#read 3, iclass 28, count 0 2006.286.01:43:33.69#ibcon#about to read 4, iclass 28, count 0 2006.286.01:43:33.69#ibcon#read 4, iclass 28, count 0 2006.286.01:43:33.69#ibcon#about to read 5, iclass 28, count 0 2006.286.01:43:33.69#ibcon#read 5, iclass 28, count 0 2006.286.01:43:33.69#ibcon#about to read 6, iclass 28, count 0 2006.286.01:43:33.69#ibcon#read 6, iclass 28, count 0 2006.286.01:43:33.69#ibcon#end of sib2, iclass 28, count 0 2006.286.01:43:33.69#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:43:33.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:43:33.69#ibcon#[25=USB\r\n] 2006.286.01:43:33.69#ibcon#*before write, iclass 28, count 0 2006.286.01:43:33.69#ibcon#enter sib2, iclass 28, count 0 2006.286.01:43:33.69#ibcon#flushed, iclass 28, count 0 2006.286.01:43:33.69#ibcon#about to write, iclass 28, count 0 2006.286.01:43:33.69#ibcon#wrote, iclass 28, count 0 2006.286.01:43:33.69#ibcon#about to read 3, iclass 28, count 0 2006.286.01:43:33.72#ibcon#read 3, iclass 28, count 0 2006.286.01:43:33.72#ibcon#about to read 4, iclass 28, count 0 2006.286.01:43:33.72#ibcon#read 4, iclass 28, count 0 2006.286.01:43:33.72#ibcon#about to read 5, iclass 28, count 0 2006.286.01:43:33.72#ibcon#read 5, iclass 28, count 0 2006.286.01:43:33.72#ibcon#about to read 6, iclass 28, count 0 2006.286.01:43:33.72#ibcon#read 6, iclass 28, count 0 2006.286.01:43:33.72#ibcon#end of sib2, iclass 28, count 0 2006.286.01:43:33.72#ibcon#*after write, iclass 28, count 0 2006.286.01:43:33.72#ibcon#*before return 0, iclass 28, count 0 2006.286.01:43:33.72#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:43:33.72#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:43:33.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:43:33.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:43:33.72$vck44/valo=2,534.99 2006.286.01:43:33.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.01:43:33.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.01:43:33.72#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:33.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:43:33.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:43:33.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:43:33.72#ibcon#enter wrdev, iclass 30, count 0 2006.286.01:43:33.72#ibcon#first serial, iclass 30, count 0 2006.286.01:43:33.72#ibcon#enter sib2, iclass 30, count 0 2006.286.01:43:33.72#ibcon#flushed, iclass 30, count 0 2006.286.01:43:33.72#ibcon#about to write, iclass 30, count 0 2006.286.01:43:33.72#ibcon#wrote, iclass 30, count 0 2006.286.01:43:33.72#ibcon#about to read 3, iclass 30, count 0 2006.286.01:43:33.74#ibcon#read 3, iclass 30, count 0 2006.286.01:43:33.74#ibcon#about to read 4, iclass 30, count 0 2006.286.01:43:33.74#ibcon#read 4, iclass 30, count 0 2006.286.01:43:33.74#ibcon#about to read 5, iclass 30, count 0 2006.286.01:43:33.74#ibcon#read 5, iclass 30, count 0 2006.286.01:43:33.74#ibcon#about to read 6, iclass 30, count 0 2006.286.01:43:33.74#ibcon#read 6, iclass 30, count 0 2006.286.01:43:33.74#ibcon#end of sib2, iclass 30, count 0 2006.286.01:43:33.74#ibcon#*mode == 0, iclass 30, count 0 2006.286.01:43:33.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.01:43:33.74#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:43:33.74#ibcon#*before write, iclass 30, count 0 2006.286.01:43:33.74#ibcon#enter sib2, iclass 30, count 0 2006.286.01:43:33.74#ibcon#flushed, iclass 30, count 0 2006.286.01:43:33.74#ibcon#about to write, iclass 30, count 0 2006.286.01:43:33.74#ibcon#wrote, iclass 30, count 0 2006.286.01:43:33.74#ibcon#about to read 3, iclass 30, count 0 2006.286.01:43:33.78#ibcon#read 3, iclass 30, count 0 2006.286.01:43:33.78#ibcon#about to read 4, iclass 30, count 0 2006.286.01:43:33.78#ibcon#read 4, iclass 30, count 0 2006.286.01:43:33.78#ibcon#about to read 5, iclass 30, count 0 2006.286.01:43:33.78#ibcon#read 5, iclass 30, count 0 2006.286.01:43:33.78#ibcon#about to read 6, iclass 30, count 0 2006.286.01:43:33.78#ibcon#read 6, iclass 30, count 0 2006.286.01:43:33.78#ibcon#end of sib2, iclass 30, count 0 2006.286.01:43:33.78#ibcon#*after write, iclass 30, count 0 2006.286.01:43:33.78#ibcon#*before return 0, iclass 30, count 0 2006.286.01:43:33.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:43:33.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:43:33.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.01:43:33.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.01:43:33.78$vck44/va=2,6 2006.286.01:43:33.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.01:43:33.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.01:43:33.78#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:33.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:43:33.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:43:33.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:43:33.84#ibcon#enter wrdev, iclass 32, count 2 2006.286.01:43:33.84#ibcon#first serial, iclass 32, count 2 2006.286.01:43:33.84#ibcon#enter sib2, iclass 32, count 2 2006.286.01:43:33.84#ibcon#flushed, iclass 32, count 2 2006.286.01:43:33.84#ibcon#about to write, iclass 32, count 2 2006.286.01:43:33.84#ibcon#wrote, iclass 32, count 2 2006.286.01:43:33.84#ibcon#about to read 3, iclass 32, count 2 2006.286.01:43:33.86#ibcon#read 3, iclass 32, count 2 2006.286.01:43:33.86#ibcon#about to read 4, iclass 32, count 2 2006.286.01:43:33.86#ibcon#read 4, iclass 32, count 2 2006.286.01:43:33.86#ibcon#about to read 5, iclass 32, count 2 2006.286.01:43:33.86#ibcon#read 5, iclass 32, count 2 2006.286.01:43:33.86#ibcon#about to read 6, iclass 32, count 2 2006.286.01:43:33.86#ibcon#read 6, iclass 32, count 2 2006.286.01:43:33.86#ibcon#end of sib2, iclass 32, count 2 2006.286.01:43:33.86#ibcon#*mode == 0, iclass 32, count 2 2006.286.01:43:33.86#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.01:43:33.86#ibcon#[25=AT02-06\r\n] 2006.286.01:43:33.86#ibcon#*before write, iclass 32, count 2 2006.286.01:43:33.86#ibcon#enter sib2, iclass 32, count 2 2006.286.01:43:33.86#ibcon#flushed, iclass 32, count 2 2006.286.01:43:33.86#ibcon#about to write, iclass 32, count 2 2006.286.01:43:33.86#ibcon#wrote, iclass 32, count 2 2006.286.01:43:33.86#ibcon#about to read 3, iclass 32, count 2 2006.286.01:43:33.89#ibcon#read 3, iclass 32, count 2 2006.286.01:43:33.89#ibcon#about to read 4, iclass 32, count 2 2006.286.01:43:33.89#ibcon#read 4, iclass 32, count 2 2006.286.01:43:33.89#ibcon#about to read 5, iclass 32, count 2 2006.286.01:43:33.89#ibcon#read 5, iclass 32, count 2 2006.286.01:43:33.89#ibcon#about to read 6, iclass 32, count 2 2006.286.01:43:33.89#ibcon#read 6, iclass 32, count 2 2006.286.01:43:33.89#ibcon#end of sib2, iclass 32, count 2 2006.286.01:43:33.89#ibcon#*after write, iclass 32, count 2 2006.286.01:43:33.89#ibcon#*before return 0, iclass 32, count 2 2006.286.01:43:33.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:43:33.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:43:33.89#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.01:43:33.89#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:33.89#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:43:34.01#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:43:34.01#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:43:34.01#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:43:34.01#ibcon#first serial, iclass 32, count 0 2006.286.01:43:34.01#ibcon#enter sib2, iclass 32, count 0 2006.286.01:43:34.01#ibcon#flushed, iclass 32, count 0 2006.286.01:43:34.01#ibcon#about to write, iclass 32, count 0 2006.286.01:43:34.01#ibcon#wrote, iclass 32, count 0 2006.286.01:43:34.01#ibcon#about to read 3, iclass 32, count 0 2006.286.01:43:34.03#ibcon#read 3, iclass 32, count 0 2006.286.01:43:34.03#ibcon#about to read 4, iclass 32, count 0 2006.286.01:43:34.03#ibcon#read 4, iclass 32, count 0 2006.286.01:43:34.03#ibcon#about to read 5, iclass 32, count 0 2006.286.01:43:34.03#ibcon#read 5, iclass 32, count 0 2006.286.01:43:34.03#ibcon#about to read 6, iclass 32, count 0 2006.286.01:43:34.03#ibcon#read 6, iclass 32, count 0 2006.286.01:43:34.03#ibcon#end of sib2, iclass 32, count 0 2006.286.01:43:34.03#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:43:34.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:43:34.03#ibcon#[25=USB\r\n] 2006.286.01:43:34.03#ibcon#*before write, iclass 32, count 0 2006.286.01:43:34.03#ibcon#enter sib2, iclass 32, count 0 2006.286.01:43:34.03#ibcon#flushed, iclass 32, count 0 2006.286.01:43:34.03#ibcon#about to write, iclass 32, count 0 2006.286.01:43:34.03#ibcon#wrote, iclass 32, count 0 2006.286.01:43:34.03#ibcon#about to read 3, iclass 32, count 0 2006.286.01:43:34.06#ibcon#read 3, iclass 32, count 0 2006.286.01:43:34.06#ibcon#about to read 4, iclass 32, count 0 2006.286.01:43:34.06#ibcon#read 4, iclass 32, count 0 2006.286.01:43:34.06#ibcon#about to read 5, iclass 32, count 0 2006.286.01:43:34.06#ibcon#read 5, iclass 32, count 0 2006.286.01:43:34.06#ibcon#about to read 6, iclass 32, count 0 2006.286.01:43:34.06#ibcon#read 6, iclass 32, count 0 2006.286.01:43:34.06#ibcon#end of sib2, iclass 32, count 0 2006.286.01:43:34.06#ibcon#*after write, iclass 32, count 0 2006.286.01:43:34.06#ibcon#*before return 0, iclass 32, count 0 2006.286.01:43:34.06#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:43:34.06#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:43:34.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:43:34.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:43:34.06$vck44/valo=3,564.99 2006.286.01:43:34.06#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.01:43:34.06#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.01:43:34.06#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:34.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:43:34.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:43:34.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:43:34.06#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:43:34.06#ibcon#first serial, iclass 34, count 0 2006.286.01:43:34.06#ibcon#enter sib2, iclass 34, count 0 2006.286.01:43:34.06#ibcon#flushed, iclass 34, count 0 2006.286.01:43:34.06#ibcon#about to write, iclass 34, count 0 2006.286.01:43:34.06#ibcon#wrote, iclass 34, count 0 2006.286.01:43:34.06#ibcon#about to read 3, iclass 34, count 0 2006.286.01:43:34.08#ibcon#read 3, iclass 34, count 0 2006.286.01:43:34.08#ibcon#about to read 4, iclass 34, count 0 2006.286.01:43:34.08#ibcon#read 4, iclass 34, count 0 2006.286.01:43:34.08#ibcon#about to read 5, iclass 34, count 0 2006.286.01:43:34.08#ibcon#read 5, iclass 34, count 0 2006.286.01:43:34.08#ibcon#about to read 6, iclass 34, count 0 2006.286.01:43:34.08#ibcon#read 6, iclass 34, count 0 2006.286.01:43:34.08#ibcon#end of sib2, iclass 34, count 0 2006.286.01:43:34.08#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:43:34.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:43:34.08#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:43:34.08#ibcon#*before write, iclass 34, count 0 2006.286.01:43:34.08#ibcon#enter sib2, iclass 34, count 0 2006.286.01:43:34.08#ibcon#flushed, iclass 34, count 0 2006.286.01:43:34.08#ibcon#about to write, iclass 34, count 0 2006.286.01:43:34.08#ibcon#wrote, iclass 34, count 0 2006.286.01:43:34.08#ibcon#about to read 3, iclass 34, count 0 2006.286.01:43:34.12#ibcon#read 3, iclass 34, count 0 2006.286.01:43:34.12#ibcon#about to read 4, iclass 34, count 0 2006.286.01:43:34.12#ibcon#read 4, iclass 34, count 0 2006.286.01:43:34.12#ibcon#about to read 5, iclass 34, count 0 2006.286.01:43:34.12#ibcon#read 5, iclass 34, count 0 2006.286.01:43:34.12#ibcon#about to read 6, iclass 34, count 0 2006.286.01:43:34.12#ibcon#read 6, iclass 34, count 0 2006.286.01:43:34.12#ibcon#end of sib2, iclass 34, count 0 2006.286.01:43:34.12#ibcon#*after write, iclass 34, count 0 2006.286.01:43:34.12#ibcon#*before return 0, iclass 34, count 0 2006.286.01:43:34.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:43:34.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:43:34.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:43:34.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:43:34.12$vck44/va=3,7 2006.286.01:43:34.12#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.01:43:34.12#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.01:43:34.12#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:34.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:43:34.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:43:34.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:43:34.18#ibcon#enter wrdev, iclass 36, count 2 2006.286.01:43:34.18#ibcon#first serial, iclass 36, count 2 2006.286.01:43:34.18#ibcon#enter sib2, iclass 36, count 2 2006.286.01:43:34.18#ibcon#flushed, iclass 36, count 2 2006.286.01:43:34.18#ibcon#about to write, iclass 36, count 2 2006.286.01:43:34.18#ibcon#wrote, iclass 36, count 2 2006.286.01:43:34.18#ibcon#about to read 3, iclass 36, count 2 2006.286.01:43:34.20#ibcon#read 3, iclass 36, count 2 2006.286.01:43:34.20#ibcon#about to read 4, iclass 36, count 2 2006.286.01:43:34.20#ibcon#read 4, iclass 36, count 2 2006.286.01:43:34.20#ibcon#about to read 5, iclass 36, count 2 2006.286.01:43:34.20#ibcon#read 5, iclass 36, count 2 2006.286.01:43:34.20#ibcon#about to read 6, iclass 36, count 2 2006.286.01:43:34.20#ibcon#read 6, iclass 36, count 2 2006.286.01:43:34.20#ibcon#end of sib2, iclass 36, count 2 2006.286.01:43:34.20#ibcon#*mode == 0, iclass 36, count 2 2006.286.01:43:34.20#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.01:43:34.20#ibcon#[25=AT03-07\r\n] 2006.286.01:43:34.20#ibcon#*before write, iclass 36, count 2 2006.286.01:43:34.20#ibcon#enter sib2, iclass 36, count 2 2006.286.01:43:34.20#ibcon#flushed, iclass 36, count 2 2006.286.01:43:34.20#ibcon#about to write, iclass 36, count 2 2006.286.01:43:34.20#ibcon#wrote, iclass 36, count 2 2006.286.01:43:34.20#ibcon#about to read 3, iclass 36, count 2 2006.286.01:43:34.23#ibcon#read 3, iclass 36, count 2 2006.286.01:43:34.23#ibcon#about to read 4, iclass 36, count 2 2006.286.01:43:34.23#ibcon#read 4, iclass 36, count 2 2006.286.01:43:34.23#ibcon#about to read 5, iclass 36, count 2 2006.286.01:43:34.23#ibcon#read 5, iclass 36, count 2 2006.286.01:43:34.23#ibcon#about to read 6, iclass 36, count 2 2006.286.01:43:34.23#ibcon#read 6, iclass 36, count 2 2006.286.01:43:34.23#ibcon#end of sib2, iclass 36, count 2 2006.286.01:43:34.23#ibcon#*after write, iclass 36, count 2 2006.286.01:43:34.23#ibcon#*before return 0, iclass 36, count 2 2006.286.01:43:34.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:43:34.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:43:34.23#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.01:43:34.23#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:34.23#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:43:34.35#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:43:34.35#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:43:34.35#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:43:34.35#ibcon#first serial, iclass 36, count 0 2006.286.01:43:34.35#ibcon#enter sib2, iclass 36, count 0 2006.286.01:43:34.35#ibcon#flushed, iclass 36, count 0 2006.286.01:43:34.35#ibcon#about to write, iclass 36, count 0 2006.286.01:43:34.35#ibcon#wrote, iclass 36, count 0 2006.286.01:43:34.35#ibcon#about to read 3, iclass 36, count 0 2006.286.01:43:34.37#ibcon#read 3, iclass 36, count 0 2006.286.01:43:34.37#ibcon#about to read 4, iclass 36, count 0 2006.286.01:43:34.37#ibcon#read 4, iclass 36, count 0 2006.286.01:43:34.37#ibcon#about to read 5, iclass 36, count 0 2006.286.01:43:34.37#ibcon#read 5, iclass 36, count 0 2006.286.01:43:34.37#ibcon#about to read 6, iclass 36, count 0 2006.286.01:43:34.37#ibcon#read 6, iclass 36, count 0 2006.286.01:43:34.37#ibcon#end of sib2, iclass 36, count 0 2006.286.01:43:34.37#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:43:34.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:43:34.37#ibcon#[25=USB\r\n] 2006.286.01:43:34.37#ibcon#*before write, iclass 36, count 0 2006.286.01:43:34.37#ibcon#enter sib2, iclass 36, count 0 2006.286.01:43:34.37#ibcon#flushed, iclass 36, count 0 2006.286.01:43:34.37#ibcon#about to write, iclass 36, count 0 2006.286.01:43:34.37#ibcon#wrote, iclass 36, count 0 2006.286.01:43:34.37#ibcon#about to read 3, iclass 36, count 0 2006.286.01:43:34.40#ibcon#read 3, iclass 36, count 0 2006.286.01:43:34.40#ibcon#about to read 4, iclass 36, count 0 2006.286.01:43:34.40#ibcon#read 4, iclass 36, count 0 2006.286.01:43:34.40#ibcon#about to read 5, iclass 36, count 0 2006.286.01:43:34.40#ibcon#read 5, iclass 36, count 0 2006.286.01:43:34.40#ibcon#about to read 6, iclass 36, count 0 2006.286.01:43:34.40#ibcon#read 6, iclass 36, count 0 2006.286.01:43:34.40#ibcon#end of sib2, iclass 36, count 0 2006.286.01:43:34.40#ibcon#*after write, iclass 36, count 0 2006.286.01:43:34.40#ibcon#*before return 0, iclass 36, count 0 2006.286.01:43:34.40#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:43:34.40#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:43:34.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:43:34.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:43:34.40$vck44/valo=4,624.99 2006.286.01:43:34.40#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.01:43:34.40#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.01:43:34.40#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:34.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:43:34.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:43:34.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:43:34.40#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:43:34.40#ibcon#first serial, iclass 38, count 0 2006.286.01:43:34.40#ibcon#enter sib2, iclass 38, count 0 2006.286.01:43:34.40#ibcon#flushed, iclass 38, count 0 2006.286.01:43:34.40#ibcon#about to write, iclass 38, count 0 2006.286.01:43:34.40#ibcon#wrote, iclass 38, count 0 2006.286.01:43:34.40#ibcon#about to read 3, iclass 38, count 0 2006.286.01:43:34.42#ibcon#read 3, iclass 38, count 0 2006.286.01:43:34.42#ibcon#about to read 4, iclass 38, count 0 2006.286.01:43:34.42#ibcon#read 4, iclass 38, count 0 2006.286.01:43:34.42#ibcon#about to read 5, iclass 38, count 0 2006.286.01:43:34.42#ibcon#read 5, iclass 38, count 0 2006.286.01:43:34.42#ibcon#about to read 6, iclass 38, count 0 2006.286.01:43:34.42#ibcon#read 6, iclass 38, count 0 2006.286.01:43:34.42#ibcon#end of sib2, iclass 38, count 0 2006.286.01:43:34.42#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:43:34.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:43:34.42#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:43:34.42#ibcon#*before write, iclass 38, count 0 2006.286.01:43:34.42#ibcon#enter sib2, iclass 38, count 0 2006.286.01:43:34.42#ibcon#flushed, iclass 38, count 0 2006.286.01:43:34.42#ibcon#about to write, iclass 38, count 0 2006.286.01:43:34.42#ibcon#wrote, iclass 38, count 0 2006.286.01:43:34.42#ibcon#about to read 3, iclass 38, count 0 2006.286.01:43:34.46#ibcon#read 3, iclass 38, count 0 2006.286.01:43:34.46#ibcon#about to read 4, iclass 38, count 0 2006.286.01:43:34.46#ibcon#read 4, iclass 38, count 0 2006.286.01:43:34.46#ibcon#about to read 5, iclass 38, count 0 2006.286.01:43:34.46#ibcon#read 5, iclass 38, count 0 2006.286.01:43:34.46#ibcon#about to read 6, iclass 38, count 0 2006.286.01:43:34.46#ibcon#read 6, iclass 38, count 0 2006.286.01:43:34.46#ibcon#end of sib2, iclass 38, count 0 2006.286.01:43:34.46#ibcon#*after write, iclass 38, count 0 2006.286.01:43:34.46#ibcon#*before return 0, iclass 38, count 0 2006.286.01:43:34.46#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:43:34.46#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:43:34.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:43:34.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:43:34.46$vck44/va=4,6 2006.286.01:43:34.46#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.01:43:34.46#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.01:43:34.46#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:34.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:43:34.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:43:34.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:43:34.52#ibcon#enter wrdev, iclass 40, count 2 2006.286.01:43:34.52#ibcon#first serial, iclass 40, count 2 2006.286.01:43:34.52#ibcon#enter sib2, iclass 40, count 2 2006.286.01:43:34.52#ibcon#flushed, iclass 40, count 2 2006.286.01:43:34.52#ibcon#about to write, iclass 40, count 2 2006.286.01:43:34.52#ibcon#wrote, iclass 40, count 2 2006.286.01:43:34.52#ibcon#about to read 3, iclass 40, count 2 2006.286.01:43:34.54#ibcon#read 3, iclass 40, count 2 2006.286.01:43:34.54#ibcon#about to read 4, iclass 40, count 2 2006.286.01:43:34.54#ibcon#read 4, iclass 40, count 2 2006.286.01:43:34.54#ibcon#about to read 5, iclass 40, count 2 2006.286.01:43:34.54#ibcon#read 5, iclass 40, count 2 2006.286.01:43:34.54#ibcon#about to read 6, iclass 40, count 2 2006.286.01:43:34.54#ibcon#read 6, iclass 40, count 2 2006.286.01:43:34.54#ibcon#end of sib2, iclass 40, count 2 2006.286.01:43:34.54#ibcon#*mode == 0, iclass 40, count 2 2006.286.01:43:34.54#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.01:43:34.54#ibcon#[25=AT04-06\r\n] 2006.286.01:43:34.54#ibcon#*before write, iclass 40, count 2 2006.286.01:43:34.54#ibcon#enter sib2, iclass 40, count 2 2006.286.01:43:34.54#ibcon#flushed, iclass 40, count 2 2006.286.01:43:34.54#ibcon#about to write, iclass 40, count 2 2006.286.01:43:34.54#ibcon#wrote, iclass 40, count 2 2006.286.01:43:34.54#ibcon#about to read 3, iclass 40, count 2 2006.286.01:43:34.57#ibcon#read 3, iclass 40, count 2 2006.286.01:43:34.57#ibcon#about to read 4, iclass 40, count 2 2006.286.01:43:34.57#ibcon#read 4, iclass 40, count 2 2006.286.01:43:34.57#ibcon#about to read 5, iclass 40, count 2 2006.286.01:43:34.57#ibcon#read 5, iclass 40, count 2 2006.286.01:43:34.57#ibcon#about to read 6, iclass 40, count 2 2006.286.01:43:34.57#ibcon#read 6, iclass 40, count 2 2006.286.01:43:34.57#ibcon#end of sib2, iclass 40, count 2 2006.286.01:43:34.57#ibcon#*after write, iclass 40, count 2 2006.286.01:43:34.57#ibcon#*before return 0, iclass 40, count 2 2006.286.01:43:34.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:43:34.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:43:34.57#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.01:43:34.57#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:34.57#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:43:34.69#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:43:34.69#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:43:34.69#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:43:34.69#ibcon#first serial, iclass 40, count 0 2006.286.01:43:34.69#ibcon#enter sib2, iclass 40, count 0 2006.286.01:43:34.69#ibcon#flushed, iclass 40, count 0 2006.286.01:43:34.69#ibcon#about to write, iclass 40, count 0 2006.286.01:43:34.69#ibcon#wrote, iclass 40, count 0 2006.286.01:43:34.69#ibcon#about to read 3, iclass 40, count 0 2006.286.01:43:34.71#ibcon#read 3, iclass 40, count 0 2006.286.01:43:34.71#ibcon#about to read 4, iclass 40, count 0 2006.286.01:43:34.71#ibcon#read 4, iclass 40, count 0 2006.286.01:43:34.71#ibcon#about to read 5, iclass 40, count 0 2006.286.01:43:34.71#ibcon#read 5, iclass 40, count 0 2006.286.01:43:34.71#ibcon#about to read 6, iclass 40, count 0 2006.286.01:43:34.71#ibcon#read 6, iclass 40, count 0 2006.286.01:43:34.71#ibcon#end of sib2, iclass 40, count 0 2006.286.01:43:34.71#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:43:34.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:43:34.71#ibcon#[25=USB\r\n] 2006.286.01:43:34.71#ibcon#*before write, iclass 40, count 0 2006.286.01:43:34.71#ibcon#enter sib2, iclass 40, count 0 2006.286.01:43:34.71#ibcon#flushed, iclass 40, count 0 2006.286.01:43:34.71#ibcon#about to write, iclass 40, count 0 2006.286.01:43:34.71#ibcon#wrote, iclass 40, count 0 2006.286.01:43:34.71#ibcon#about to read 3, iclass 40, count 0 2006.286.01:43:34.74#ibcon#read 3, iclass 40, count 0 2006.286.01:43:34.74#ibcon#about to read 4, iclass 40, count 0 2006.286.01:43:34.74#ibcon#read 4, iclass 40, count 0 2006.286.01:43:34.74#ibcon#about to read 5, iclass 40, count 0 2006.286.01:43:34.74#ibcon#read 5, iclass 40, count 0 2006.286.01:43:34.74#ibcon#about to read 6, iclass 40, count 0 2006.286.01:43:34.74#ibcon#read 6, iclass 40, count 0 2006.286.01:43:34.74#ibcon#end of sib2, iclass 40, count 0 2006.286.01:43:34.74#ibcon#*after write, iclass 40, count 0 2006.286.01:43:34.74#ibcon#*before return 0, iclass 40, count 0 2006.286.01:43:34.74#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:43:34.74#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:43:34.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:43:34.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:43:34.74$vck44/valo=5,734.99 2006.286.01:43:34.74#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.01:43:34.74#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.01:43:34.74#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:34.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:43:34.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:43:34.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:43:34.74#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:43:34.74#ibcon#first serial, iclass 4, count 0 2006.286.01:43:34.74#ibcon#enter sib2, iclass 4, count 0 2006.286.01:43:34.74#ibcon#flushed, iclass 4, count 0 2006.286.01:43:34.74#ibcon#about to write, iclass 4, count 0 2006.286.01:43:34.74#ibcon#wrote, iclass 4, count 0 2006.286.01:43:34.74#ibcon#about to read 3, iclass 4, count 0 2006.286.01:43:34.76#ibcon#read 3, iclass 4, count 0 2006.286.01:43:34.76#ibcon#about to read 4, iclass 4, count 0 2006.286.01:43:34.76#ibcon#read 4, iclass 4, count 0 2006.286.01:43:34.76#ibcon#about to read 5, iclass 4, count 0 2006.286.01:43:34.76#ibcon#read 5, iclass 4, count 0 2006.286.01:43:34.76#ibcon#about to read 6, iclass 4, count 0 2006.286.01:43:34.76#ibcon#read 6, iclass 4, count 0 2006.286.01:43:34.76#ibcon#end of sib2, iclass 4, count 0 2006.286.01:43:34.76#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:43:34.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:43:34.76#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:43:34.76#ibcon#*before write, iclass 4, count 0 2006.286.01:43:34.76#ibcon#enter sib2, iclass 4, count 0 2006.286.01:43:34.76#ibcon#flushed, iclass 4, count 0 2006.286.01:43:34.76#ibcon#about to write, iclass 4, count 0 2006.286.01:43:34.76#ibcon#wrote, iclass 4, count 0 2006.286.01:43:34.76#ibcon#about to read 3, iclass 4, count 0 2006.286.01:43:34.80#ibcon#read 3, iclass 4, count 0 2006.286.01:43:34.80#ibcon#about to read 4, iclass 4, count 0 2006.286.01:43:34.80#ibcon#read 4, iclass 4, count 0 2006.286.01:43:34.80#ibcon#about to read 5, iclass 4, count 0 2006.286.01:43:34.80#ibcon#read 5, iclass 4, count 0 2006.286.01:43:34.80#ibcon#about to read 6, iclass 4, count 0 2006.286.01:43:34.80#ibcon#read 6, iclass 4, count 0 2006.286.01:43:34.80#ibcon#end of sib2, iclass 4, count 0 2006.286.01:43:34.80#ibcon#*after write, iclass 4, count 0 2006.286.01:43:34.80#ibcon#*before return 0, iclass 4, count 0 2006.286.01:43:34.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:43:34.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:43:34.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:43:34.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:43:34.80$vck44/va=5,3 2006.286.01:43:34.80#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.01:43:34.80#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.01:43:34.80#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:34.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:43:34.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:43:34.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:43:34.86#ibcon#enter wrdev, iclass 6, count 2 2006.286.01:43:34.86#ibcon#first serial, iclass 6, count 2 2006.286.01:43:34.86#ibcon#enter sib2, iclass 6, count 2 2006.286.01:43:34.86#ibcon#flushed, iclass 6, count 2 2006.286.01:43:34.86#ibcon#about to write, iclass 6, count 2 2006.286.01:43:34.86#ibcon#wrote, iclass 6, count 2 2006.286.01:43:34.86#ibcon#about to read 3, iclass 6, count 2 2006.286.01:43:34.88#ibcon#read 3, iclass 6, count 2 2006.286.01:43:34.88#ibcon#about to read 4, iclass 6, count 2 2006.286.01:43:34.88#ibcon#read 4, iclass 6, count 2 2006.286.01:43:34.88#ibcon#about to read 5, iclass 6, count 2 2006.286.01:43:34.88#ibcon#read 5, iclass 6, count 2 2006.286.01:43:34.88#ibcon#about to read 6, iclass 6, count 2 2006.286.01:43:34.88#ibcon#read 6, iclass 6, count 2 2006.286.01:43:34.88#ibcon#end of sib2, iclass 6, count 2 2006.286.01:43:34.88#ibcon#*mode == 0, iclass 6, count 2 2006.286.01:43:34.88#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.01:43:34.88#ibcon#[25=AT05-03\r\n] 2006.286.01:43:34.88#ibcon#*before write, iclass 6, count 2 2006.286.01:43:34.88#ibcon#enter sib2, iclass 6, count 2 2006.286.01:43:34.88#ibcon#flushed, iclass 6, count 2 2006.286.01:43:34.88#ibcon#about to write, iclass 6, count 2 2006.286.01:43:34.88#ibcon#wrote, iclass 6, count 2 2006.286.01:43:34.88#ibcon#about to read 3, iclass 6, count 2 2006.286.01:43:34.91#ibcon#read 3, iclass 6, count 2 2006.286.01:43:34.91#ibcon#about to read 4, iclass 6, count 2 2006.286.01:43:34.91#ibcon#read 4, iclass 6, count 2 2006.286.01:43:34.91#ibcon#about to read 5, iclass 6, count 2 2006.286.01:43:34.91#ibcon#read 5, iclass 6, count 2 2006.286.01:43:34.91#ibcon#about to read 6, iclass 6, count 2 2006.286.01:43:34.91#ibcon#read 6, iclass 6, count 2 2006.286.01:43:34.91#ibcon#end of sib2, iclass 6, count 2 2006.286.01:43:34.91#ibcon#*after write, iclass 6, count 2 2006.286.01:43:34.91#ibcon#*before return 0, iclass 6, count 2 2006.286.01:43:34.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:43:34.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:43:34.91#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.01:43:34.91#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:34.91#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:43:35.03#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:43:35.03#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:43:35.03#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:43:35.03#ibcon#first serial, iclass 6, count 0 2006.286.01:43:35.03#ibcon#enter sib2, iclass 6, count 0 2006.286.01:43:35.03#ibcon#flushed, iclass 6, count 0 2006.286.01:43:35.03#ibcon#about to write, iclass 6, count 0 2006.286.01:43:35.03#ibcon#wrote, iclass 6, count 0 2006.286.01:43:35.03#ibcon#about to read 3, iclass 6, count 0 2006.286.01:43:35.05#ibcon#read 3, iclass 6, count 0 2006.286.01:43:35.05#ibcon#about to read 4, iclass 6, count 0 2006.286.01:43:35.05#ibcon#read 4, iclass 6, count 0 2006.286.01:43:35.05#ibcon#about to read 5, iclass 6, count 0 2006.286.01:43:35.05#ibcon#read 5, iclass 6, count 0 2006.286.01:43:35.05#ibcon#about to read 6, iclass 6, count 0 2006.286.01:43:35.05#ibcon#read 6, iclass 6, count 0 2006.286.01:43:35.05#ibcon#end of sib2, iclass 6, count 0 2006.286.01:43:35.05#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:43:35.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:43:35.05#ibcon#[25=USB\r\n] 2006.286.01:43:35.05#ibcon#*before write, iclass 6, count 0 2006.286.01:43:35.05#ibcon#enter sib2, iclass 6, count 0 2006.286.01:43:35.05#ibcon#flushed, iclass 6, count 0 2006.286.01:43:35.05#ibcon#about to write, iclass 6, count 0 2006.286.01:43:35.05#ibcon#wrote, iclass 6, count 0 2006.286.01:43:35.05#ibcon#about to read 3, iclass 6, count 0 2006.286.01:43:35.08#ibcon#read 3, iclass 6, count 0 2006.286.01:43:35.08#ibcon#about to read 4, iclass 6, count 0 2006.286.01:43:35.08#ibcon#read 4, iclass 6, count 0 2006.286.01:43:35.08#ibcon#about to read 5, iclass 6, count 0 2006.286.01:43:35.08#ibcon#read 5, iclass 6, count 0 2006.286.01:43:35.08#ibcon#about to read 6, iclass 6, count 0 2006.286.01:43:35.08#ibcon#read 6, iclass 6, count 0 2006.286.01:43:35.08#ibcon#end of sib2, iclass 6, count 0 2006.286.01:43:35.08#ibcon#*after write, iclass 6, count 0 2006.286.01:43:35.08#ibcon#*before return 0, iclass 6, count 0 2006.286.01:43:35.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:43:35.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:43:35.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:43:35.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:43:35.08$vck44/valo=6,814.99 2006.286.01:43:35.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.01:43:35.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.01:43:35.08#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:35.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:43:35.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:43:35.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:43:35.08#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:43:35.08#ibcon#first serial, iclass 10, count 0 2006.286.01:43:35.08#ibcon#enter sib2, iclass 10, count 0 2006.286.01:43:35.08#ibcon#flushed, iclass 10, count 0 2006.286.01:43:35.08#ibcon#about to write, iclass 10, count 0 2006.286.01:43:35.08#ibcon#wrote, iclass 10, count 0 2006.286.01:43:35.08#ibcon#about to read 3, iclass 10, count 0 2006.286.01:43:35.10#ibcon#read 3, iclass 10, count 0 2006.286.01:43:35.10#ibcon#about to read 4, iclass 10, count 0 2006.286.01:43:35.10#ibcon#read 4, iclass 10, count 0 2006.286.01:43:35.10#ibcon#about to read 5, iclass 10, count 0 2006.286.01:43:35.10#ibcon#read 5, iclass 10, count 0 2006.286.01:43:35.10#ibcon#about to read 6, iclass 10, count 0 2006.286.01:43:35.10#ibcon#read 6, iclass 10, count 0 2006.286.01:43:35.10#ibcon#end of sib2, iclass 10, count 0 2006.286.01:43:35.10#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:43:35.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:43:35.10#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:43:35.10#ibcon#*before write, iclass 10, count 0 2006.286.01:43:35.10#ibcon#enter sib2, iclass 10, count 0 2006.286.01:43:35.10#ibcon#flushed, iclass 10, count 0 2006.286.01:43:35.10#ibcon#about to write, iclass 10, count 0 2006.286.01:43:35.10#ibcon#wrote, iclass 10, count 0 2006.286.01:43:35.10#ibcon#about to read 3, iclass 10, count 0 2006.286.01:43:35.14#ibcon#read 3, iclass 10, count 0 2006.286.01:43:35.14#ibcon#about to read 4, iclass 10, count 0 2006.286.01:43:35.14#ibcon#read 4, iclass 10, count 0 2006.286.01:43:35.14#ibcon#about to read 5, iclass 10, count 0 2006.286.01:43:35.14#ibcon#read 5, iclass 10, count 0 2006.286.01:43:35.14#ibcon#about to read 6, iclass 10, count 0 2006.286.01:43:35.14#ibcon#read 6, iclass 10, count 0 2006.286.01:43:35.14#ibcon#end of sib2, iclass 10, count 0 2006.286.01:43:35.14#ibcon#*after write, iclass 10, count 0 2006.286.01:43:35.14#ibcon#*before return 0, iclass 10, count 0 2006.286.01:43:35.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:43:35.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:43:35.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:43:35.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:43:35.14$vck44/va=6,4 2006.286.01:43:35.14#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.01:43:35.14#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.01:43:35.14#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:35.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:43:35.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:43:35.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:43:35.20#ibcon#enter wrdev, iclass 12, count 2 2006.286.01:43:35.20#ibcon#first serial, iclass 12, count 2 2006.286.01:43:35.20#ibcon#enter sib2, iclass 12, count 2 2006.286.01:43:35.20#ibcon#flushed, iclass 12, count 2 2006.286.01:43:35.20#ibcon#about to write, iclass 12, count 2 2006.286.01:43:35.20#ibcon#wrote, iclass 12, count 2 2006.286.01:43:35.20#ibcon#about to read 3, iclass 12, count 2 2006.286.01:43:35.22#ibcon#read 3, iclass 12, count 2 2006.286.01:43:35.22#ibcon#about to read 4, iclass 12, count 2 2006.286.01:43:35.22#ibcon#read 4, iclass 12, count 2 2006.286.01:43:35.22#ibcon#about to read 5, iclass 12, count 2 2006.286.01:43:35.22#ibcon#read 5, iclass 12, count 2 2006.286.01:43:35.22#ibcon#about to read 6, iclass 12, count 2 2006.286.01:43:35.22#ibcon#read 6, iclass 12, count 2 2006.286.01:43:35.22#ibcon#end of sib2, iclass 12, count 2 2006.286.01:43:35.22#ibcon#*mode == 0, iclass 12, count 2 2006.286.01:43:35.22#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.01:43:35.22#ibcon#[25=AT06-04\r\n] 2006.286.01:43:35.22#ibcon#*before write, iclass 12, count 2 2006.286.01:43:35.22#ibcon#enter sib2, iclass 12, count 2 2006.286.01:43:35.22#ibcon#flushed, iclass 12, count 2 2006.286.01:43:35.22#ibcon#about to write, iclass 12, count 2 2006.286.01:43:35.22#ibcon#wrote, iclass 12, count 2 2006.286.01:43:35.22#ibcon#about to read 3, iclass 12, count 2 2006.286.01:43:35.25#ibcon#read 3, iclass 12, count 2 2006.286.01:43:35.25#ibcon#about to read 4, iclass 12, count 2 2006.286.01:43:35.25#ibcon#read 4, iclass 12, count 2 2006.286.01:43:35.25#ibcon#about to read 5, iclass 12, count 2 2006.286.01:43:35.25#ibcon#read 5, iclass 12, count 2 2006.286.01:43:35.25#ibcon#about to read 6, iclass 12, count 2 2006.286.01:43:35.25#ibcon#read 6, iclass 12, count 2 2006.286.01:43:35.25#ibcon#end of sib2, iclass 12, count 2 2006.286.01:43:35.25#ibcon#*after write, iclass 12, count 2 2006.286.01:43:35.25#ibcon#*before return 0, iclass 12, count 2 2006.286.01:43:35.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:43:35.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:43:35.25#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.01:43:35.25#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:35.25#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:43:35.37#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:43:35.37#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:43:35.37#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:43:35.37#ibcon#first serial, iclass 12, count 0 2006.286.01:43:35.37#ibcon#enter sib2, iclass 12, count 0 2006.286.01:43:35.37#ibcon#flushed, iclass 12, count 0 2006.286.01:43:35.37#ibcon#about to write, iclass 12, count 0 2006.286.01:43:35.37#ibcon#wrote, iclass 12, count 0 2006.286.01:43:35.37#ibcon#about to read 3, iclass 12, count 0 2006.286.01:43:35.39#ibcon#read 3, iclass 12, count 0 2006.286.01:43:35.39#ibcon#about to read 4, iclass 12, count 0 2006.286.01:43:35.39#ibcon#read 4, iclass 12, count 0 2006.286.01:43:35.39#ibcon#about to read 5, iclass 12, count 0 2006.286.01:43:35.39#ibcon#read 5, iclass 12, count 0 2006.286.01:43:35.39#ibcon#about to read 6, iclass 12, count 0 2006.286.01:43:35.39#ibcon#read 6, iclass 12, count 0 2006.286.01:43:35.39#ibcon#end of sib2, iclass 12, count 0 2006.286.01:43:35.39#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:43:35.39#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:43:35.39#ibcon#[25=USB\r\n] 2006.286.01:43:35.39#ibcon#*before write, iclass 12, count 0 2006.286.01:43:35.39#ibcon#enter sib2, iclass 12, count 0 2006.286.01:43:35.39#ibcon#flushed, iclass 12, count 0 2006.286.01:43:35.39#ibcon#about to write, iclass 12, count 0 2006.286.01:43:35.39#ibcon#wrote, iclass 12, count 0 2006.286.01:43:35.39#ibcon#about to read 3, iclass 12, count 0 2006.286.01:43:35.42#ibcon#read 3, iclass 12, count 0 2006.286.01:43:35.42#ibcon#about to read 4, iclass 12, count 0 2006.286.01:43:35.42#ibcon#read 4, iclass 12, count 0 2006.286.01:43:35.42#ibcon#about to read 5, iclass 12, count 0 2006.286.01:43:35.42#ibcon#read 5, iclass 12, count 0 2006.286.01:43:35.42#ibcon#about to read 6, iclass 12, count 0 2006.286.01:43:35.42#ibcon#read 6, iclass 12, count 0 2006.286.01:43:35.42#ibcon#end of sib2, iclass 12, count 0 2006.286.01:43:35.42#ibcon#*after write, iclass 12, count 0 2006.286.01:43:35.42#ibcon#*before return 0, iclass 12, count 0 2006.286.01:43:35.42#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:43:35.42#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:43:35.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:43:35.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:43:35.42$vck44/valo=7,864.99 2006.286.01:43:35.42#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.01:43:35.42#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.01:43:35.42#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:35.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:43:35.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:43:35.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:43:35.42#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:43:35.42#ibcon#first serial, iclass 14, count 0 2006.286.01:43:35.42#ibcon#enter sib2, iclass 14, count 0 2006.286.01:43:35.42#ibcon#flushed, iclass 14, count 0 2006.286.01:43:35.42#ibcon#about to write, iclass 14, count 0 2006.286.01:43:35.42#ibcon#wrote, iclass 14, count 0 2006.286.01:43:35.42#ibcon#about to read 3, iclass 14, count 0 2006.286.01:43:35.44#ibcon#read 3, iclass 14, count 0 2006.286.01:43:35.44#ibcon#about to read 4, iclass 14, count 0 2006.286.01:43:35.44#ibcon#read 4, iclass 14, count 0 2006.286.01:43:35.44#ibcon#about to read 5, iclass 14, count 0 2006.286.01:43:35.44#ibcon#read 5, iclass 14, count 0 2006.286.01:43:35.44#ibcon#about to read 6, iclass 14, count 0 2006.286.01:43:35.44#ibcon#read 6, iclass 14, count 0 2006.286.01:43:35.44#ibcon#end of sib2, iclass 14, count 0 2006.286.01:43:35.44#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:43:35.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:43:35.44#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:43:35.44#ibcon#*before write, iclass 14, count 0 2006.286.01:43:35.44#ibcon#enter sib2, iclass 14, count 0 2006.286.01:43:35.44#ibcon#flushed, iclass 14, count 0 2006.286.01:43:35.44#ibcon#about to write, iclass 14, count 0 2006.286.01:43:35.44#ibcon#wrote, iclass 14, count 0 2006.286.01:43:35.44#ibcon#about to read 3, iclass 14, count 0 2006.286.01:43:35.48#ibcon#read 3, iclass 14, count 0 2006.286.01:43:35.48#ibcon#about to read 4, iclass 14, count 0 2006.286.01:43:35.48#ibcon#read 4, iclass 14, count 0 2006.286.01:43:35.48#ibcon#about to read 5, iclass 14, count 0 2006.286.01:43:35.48#ibcon#read 5, iclass 14, count 0 2006.286.01:43:35.48#ibcon#about to read 6, iclass 14, count 0 2006.286.01:43:35.48#ibcon#read 6, iclass 14, count 0 2006.286.01:43:35.48#ibcon#end of sib2, iclass 14, count 0 2006.286.01:43:35.48#ibcon#*after write, iclass 14, count 0 2006.286.01:43:35.48#ibcon#*before return 0, iclass 14, count 0 2006.286.01:43:35.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:43:35.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:43:35.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:43:35.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:43:35.48$vck44/va=7,4 2006.286.01:43:35.48#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.01:43:35.48#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.01:43:35.48#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:35.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:43:35.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:43:35.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:43:35.54#ibcon#enter wrdev, iclass 16, count 2 2006.286.01:43:35.54#ibcon#first serial, iclass 16, count 2 2006.286.01:43:35.54#ibcon#enter sib2, iclass 16, count 2 2006.286.01:43:35.54#ibcon#flushed, iclass 16, count 2 2006.286.01:43:35.54#ibcon#about to write, iclass 16, count 2 2006.286.01:43:35.54#ibcon#wrote, iclass 16, count 2 2006.286.01:43:35.54#ibcon#about to read 3, iclass 16, count 2 2006.286.01:43:35.56#ibcon#read 3, iclass 16, count 2 2006.286.01:43:35.56#ibcon#about to read 4, iclass 16, count 2 2006.286.01:43:35.56#ibcon#read 4, iclass 16, count 2 2006.286.01:43:35.56#ibcon#about to read 5, iclass 16, count 2 2006.286.01:43:35.56#ibcon#read 5, iclass 16, count 2 2006.286.01:43:35.56#ibcon#about to read 6, iclass 16, count 2 2006.286.01:43:35.56#ibcon#read 6, iclass 16, count 2 2006.286.01:43:35.56#ibcon#end of sib2, iclass 16, count 2 2006.286.01:43:35.56#ibcon#*mode == 0, iclass 16, count 2 2006.286.01:43:35.56#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.01:43:35.56#ibcon#[25=AT07-04\r\n] 2006.286.01:43:35.56#ibcon#*before write, iclass 16, count 2 2006.286.01:43:35.56#ibcon#enter sib2, iclass 16, count 2 2006.286.01:43:35.56#ibcon#flushed, iclass 16, count 2 2006.286.01:43:35.56#ibcon#about to write, iclass 16, count 2 2006.286.01:43:35.56#ibcon#wrote, iclass 16, count 2 2006.286.01:43:35.56#ibcon#about to read 3, iclass 16, count 2 2006.286.01:43:35.59#ibcon#read 3, iclass 16, count 2 2006.286.01:43:35.59#ibcon#about to read 4, iclass 16, count 2 2006.286.01:43:35.59#ibcon#read 4, iclass 16, count 2 2006.286.01:43:35.59#ibcon#about to read 5, iclass 16, count 2 2006.286.01:43:35.59#ibcon#read 5, iclass 16, count 2 2006.286.01:43:35.59#ibcon#about to read 6, iclass 16, count 2 2006.286.01:43:35.59#ibcon#read 6, iclass 16, count 2 2006.286.01:43:35.59#ibcon#end of sib2, iclass 16, count 2 2006.286.01:43:35.59#ibcon#*after write, iclass 16, count 2 2006.286.01:43:35.59#ibcon#*before return 0, iclass 16, count 2 2006.286.01:43:35.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:43:35.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:43:35.59#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.01:43:35.59#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:35.59#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:43:35.71#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:43:35.71#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:43:35.71#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:43:35.71#ibcon#first serial, iclass 16, count 0 2006.286.01:43:35.71#ibcon#enter sib2, iclass 16, count 0 2006.286.01:43:35.71#ibcon#flushed, iclass 16, count 0 2006.286.01:43:35.71#ibcon#about to write, iclass 16, count 0 2006.286.01:43:35.71#ibcon#wrote, iclass 16, count 0 2006.286.01:43:35.71#ibcon#about to read 3, iclass 16, count 0 2006.286.01:43:35.73#ibcon#read 3, iclass 16, count 0 2006.286.01:43:35.73#ibcon#about to read 4, iclass 16, count 0 2006.286.01:43:35.73#ibcon#read 4, iclass 16, count 0 2006.286.01:43:35.73#ibcon#about to read 5, iclass 16, count 0 2006.286.01:43:35.73#ibcon#read 5, iclass 16, count 0 2006.286.01:43:35.73#ibcon#about to read 6, iclass 16, count 0 2006.286.01:43:35.73#ibcon#read 6, iclass 16, count 0 2006.286.01:43:35.73#ibcon#end of sib2, iclass 16, count 0 2006.286.01:43:35.73#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:43:35.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:43:35.73#ibcon#[25=USB\r\n] 2006.286.01:43:35.73#ibcon#*before write, iclass 16, count 0 2006.286.01:43:35.73#ibcon#enter sib2, iclass 16, count 0 2006.286.01:43:35.73#ibcon#flushed, iclass 16, count 0 2006.286.01:43:35.73#ibcon#about to write, iclass 16, count 0 2006.286.01:43:35.73#ibcon#wrote, iclass 16, count 0 2006.286.01:43:35.73#ibcon#about to read 3, iclass 16, count 0 2006.286.01:43:35.76#ibcon#read 3, iclass 16, count 0 2006.286.01:43:35.76#ibcon#about to read 4, iclass 16, count 0 2006.286.01:43:35.76#ibcon#read 4, iclass 16, count 0 2006.286.01:43:35.76#ibcon#about to read 5, iclass 16, count 0 2006.286.01:43:35.76#ibcon#read 5, iclass 16, count 0 2006.286.01:43:35.76#ibcon#about to read 6, iclass 16, count 0 2006.286.01:43:35.76#ibcon#read 6, iclass 16, count 0 2006.286.01:43:35.76#ibcon#end of sib2, iclass 16, count 0 2006.286.01:43:35.76#ibcon#*after write, iclass 16, count 0 2006.286.01:43:35.76#ibcon#*before return 0, iclass 16, count 0 2006.286.01:43:35.76#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:43:35.76#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:43:35.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:43:35.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:43:35.76$vck44/valo=8,884.99 2006.286.01:43:35.76#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.01:43:35.76#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.01:43:35.76#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:35.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:43:35.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:43:35.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:43:35.76#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:43:35.76#ibcon#first serial, iclass 18, count 0 2006.286.01:43:35.76#ibcon#enter sib2, iclass 18, count 0 2006.286.01:43:35.76#ibcon#flushed, iclass 18, count 0 2006.286.01:43:35.76#ibcon#about to write, iclass 18, count 0 2006.286.01:43:35.76#ibcon#wrote, iclass 18, count 0 2006.286.01:43:35.76#ibcon#about to read 3, iclass 18, count 0 2006.286.01:43:35.78#ibcon#read 3, iclass 18, count 0 2006.286.01:43:35.78#ibcon#about to read 4, iclass 18, count 0 2006.286.01:43:35.78#ibcon#read 4, iclass 18, count 0 2006.286.01:43:35.78#ibcon#about to read 5, iclass 18, count 0 2006.286.01:43:35.78#ibcon#read 5, iclass 18, count 0 2006.286.01:43:35.78#ibcon#about to read 6, iclass 18, count 0 2006.286.01:43:35.78#ibcon#read 6, iclass 18, count 0 2006.286.01:43:35.78#ibcon#end of sib2, iclass 18, count 0 2006.286.01:43:35.78#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:43:35.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:43:35.78#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:43:35.78#ibcon#*before write, iclass 18, count 0 2006.286.01:43:35.78#ibcon#enter sib2, iclass 18, count 0 2006.286.01:43:35.78#ibcon#flushed, iclass 18, count 0 2006.286.01:43:35.78#ibcon#about to write, iclass 18, count 0 2006.286.01:43:35.78#ibcon#wrote, iclass 18, count 0 2006.286.01:43:35.78#ibcon#about to read 3, iclass 18, count 0 2006.286.01:43:35.82#ibcon#read 3, iclass 18, count 0 2006.286.01:43:35.82#ibcon#about to read 4, iclass 18, count 0 2006.286.01:43:35.82#ibcon#read 4, iclass 18, count 0 2006.286.01:43:35.82#ibcon#about to read 5, iclass 18, count 0 2006.286.01:43:35.82#ibcon#read 5, iclass 18, count 0 2006.286.01:43:35.82#ibcon#about to read 6, iclass 18, count 0 2006.286.01:43:35.82#ibcon#read 6, iclass 18, count 0 2006.286.01:43:35.82#ibcon#end of sib2, iclass 18, count 0 2006.286.01:43:35.82#ibcon#*after write, iclass 18, count 0 2006.286.01:43:35.82#ibcon#*before return 0, iclass 18, count 0 2006.286.01:43:35.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:43:35.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:43:35.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:43:35.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:43:35.82$vck44/va=8,3 2006.286.01:43:35.82#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.01:43:35.82#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.01:43:35.82#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:35.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:43:35.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:43:35.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:43:35.88#ibcon#enter wrdev, iclass 20, count 2 2006.286.01:43:35.88#ibcon#first serial, iclass 20, count 2 2006.286.01:43:35.88#ibcon#enter sib2, iclass 20, count 2 2006.286.01:43:35.88#ibcon#flushed, iclass 20, count 2 2006.286.01:43:35.88#ibcon#about to write, iclass 20, count 2 2006.286.01:43:35.88#ibcon#wrote, iclass 20, count 2 2006.286.01:43:35.88#ibcon#about to read 3, iclass 20, count 2 2006.286.01:43:35.90#ibcon#read 3, iclass 20, count 2 2006.286.01:43:35.90#ibcon#about to read 4, iclass 20, count 2 2006.286.01:43:35.90#ibcon#read 4, iclass 20, count 2 2006.286.01:43:35.90#ibcon#about to read 5, iclass 20, count 2 2006.286.01:43:35.90#ibcon#read 5, iclass 20, count 2 2006.286.01:43:35.90#ibcon#about to read 6, iclass 20, count 2 2006.286.01:43:35.90#ibcon#read 6, iclass 20, count 2 2006.286.01:43:35.90#ibcon#end of sib2, iclass 20, count 2 2006.286.01:43:35.90#ibcon#*mode == 0, iclass 20, count 2 2006.286.01:43:35.90#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.01:43:35.90#ibcon#[25=AT08-03\r\n] 2006.286.01:43:35.90#ibcon#*before write, iclass 20, count 2 2006.286.01:43:35.90#ibcon#enter sib2, iclass 20, count 2 2006.286.01:43:35.90#ibcon#flushed, iclass 20, count 2 2006.286.01:43:35.90#ibcon#about to write, iclass 20, count 2 2006.286.01:43:35.90#ibcon#wrote, iclass 20, count 2 2006.286.01:43:35.90#ibcon#about to read 3, iclass 20, count 2 2006.286.01:43:35.93#ibcon#read 3, iclass 20, count 2 2006.286.01:43:35.93#ibcon#about to read 4, iclass 20, count 2 2006.286.01:43:35.93#ibcon#read 4, iclass 20, count 2 2006.286.01:43:35.93#ibcon#about to read 5, iclass 20, count 2 2006.286.01:43:35.93#ibcon#read 5, iclass 20, count 2 2006.286.01:43:35.93#ibcon#about to read 6, iclass 20, count 2 2006.286.01:43:35.93#ibcon#read 6, iclass 20, count 2 2006.286.01:43:35.93#ibcon#end of sib2, iclass 20, count 2 2006.286.01:43:35.93#ibcon#*after write, iclass 20, count 2 2006.286.01:43:35.93#ibcon#*before return 0, iclass 20, count 2 2006.286.01:43:35.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:43:35.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:43:35.93#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.01:43:35.93#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:35.93#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:43:36.05#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:43:36.05#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:43:36.05#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:43:36.05#ibcon#first serial, iclass 20, count 0 2006.286.01:43:36.05#ibcon#enter sib2, iclass 20, count 0 2006.286.01:43:36.05#ibcon#flushed, iclass 20, count 0 2006.286.01:43:36.05#ibcon#about to write, iclass 20, count 0 2006.286.01:43:36.05#ibcon#wrote, iclass 20, count 0 2006.286.01:43:36.05#ibcon#about to read 3, iclass 20, count 0 2006.286.01:43:36.07#ibcon#read 3, iclass 20, count 0 2006.286.01:43:36.07#ibcon#about to read 4, iclass 20, count 0 2006.286.01:43:36.07#ibcon#read 4, iclass 20, count 0 2006.286.01:43:36.07#ibcon#about to read 5, iclass 20, count 0 2006.286.01:43:36.07#ibcon#read 5, iclass 20, count 0 2006.286.01:43:36.07#ibcon#about to read 6, iclass 20, count 0 2006.286.01:43:36.07#ibcon#read 6, iclass 20, count 0 2006.286.01:43:36.07#ibcon#end of sib2, iclass 20, count 0 2006.286.01:43:36.07#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:43:36.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:43:36.07#ibcon#[25=USB\r\n] 2006.286.01:43:36.07#ibcon#*before write, iclass 20, count 0 2006.286.01:43:36.07#ibcon#enter sib2, iclass 20, count 0 2006.286.01:43:36.07#ibcon#flushed, iclass 20, count 0 2006.286.01:43:36.07#ibcon#about to write, iclass 20, count 0 2006.286.01:43:36.07#ibcon#wrote, iclass 20, count 0 2006.286.01:43:36.07#ibcon#about to read 3, iclass 20, count 0 2006.286.01:43:36.10#ibcon#read 3, iclass 20, count 0 2006.286.01:43:36.10#ibcon#about to read 4, iclass 20, count 0 2006.286.01:43:36.10#ibcon#read 4, iclass 20, count 0 2006.286.01:43:36.10#ibcon#about to read 5, iclass 20, count 0 2006.286.01:43:36.10#ibcon#read 5, iclass 20, count 0 2006.286.01:43:36.10#ibcon#about to read 6, iclass 20, count 0 2006.286.01:43:36.10#ibcon#read 6, iclass 20, count 0 2006.286.01:43:36.10#ibcon#end of sib2, iclass 20, count 0 2006.286.01:43:36.10#ibcon#*after write, iclass 20, count 0 2006.286.01:43:36.10#ibcon#*before return 0, iclass 20, count 0 2006.286.01:43:36.10#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:43:36.10#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:43:36.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:43:36.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:43:36.10$vck44/vblo=1,629.99 2006.286.01:43:36.10#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.01:43:36.10#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.01:43:36.10#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:36.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:43:36.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:43:36.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:43:36.10#ibcon#enter wrdev, iclass 22, count 0 2006.286.01:43:36.10#ibcon#first serial, iclass 22, count 0 2006.286.01:43:36.10#ibcon#enter sib2, iclass 22, count 0 2006.286.01:43:36.10#ibcon#flushed, iclass 22, count 0 2006.286.01:43:36.10#ibcon#about to write, iclass 22, count 0 2006.286.01:43:36.10#ibcon#wrote, iclass 22, count 0 2006.286.01:43:36.10#ibcon#about to read 3, iclass 22, count 0 2006.286.01:43:36.12#ibcon#read 3, iclass 22, count 0 2006.286.01:43:36.12#ibcon#about to read 4, iclass 22, count 0 2006.286.01:43:36.12#ibcon#read 4, iclass 22, count 0 2006.286.01:43:36.12#ibcon#about to read 5, iclass 22, count 0 2006.286.01:43:36.12#ibcon#read 5, iclass 22, count 0 2006.286.01:43:36.12#ibcon#about to read 6, iclass 22, count 0 2006.286.01:43:36.12#ibcon#read 6, iclass 22, count 0 2006.286.01:43:36.12#ibcon#end of sib2, iclass 22, count 0 2006.286.01:43:36.12#ibcon#*mode == 0, iclass 22, count 0 2006.286.01:43:36.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.01:43:36.12#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:43:36.12#ibcon#*before write, iclass 22, count 0 2006.286.01:43:36.12#ibcon#enter sib2, iclass 22, count 0 2006.286.01:43:36.12#ibcon#flushed, iclass 22, count 0 2006.286.01:43:36.12#ibcon#about to write, iclass 22, count 0 2006.286.01:43:36.12#ibcon#wrote, iclass 22, count 0 2006.286.01:43:36.12#ibcon#about to read 3, iclass 22, count 0 2006.286.01:43:36.16#ibcon#read 3, iclass 22, count 0 2006.286.01:43:36.16#ibcon#about to read 4, iclass 22, count 0 2006.286.01:43:36.16#ibcon#read 4, iclass 22, count 0 2006.286.01:43:36.16#ibcon#about to read 5, iclass 22, count 0 2006.286.01:43:36.16#ibcon#read 5, iclass 22, count 0 2006.286.01:43:36.16#ibcon#about to read 6, iclass 22, count 0 2006.286.01:43:36.16#ibcon#read 6, iclass 22, count 0 2006.286.01:43:36.16#ibcon#end of sib2, iclass 22, count 0 2006.286.01:43:36.16#ibcon#*after write, iclass 22, count 0 2006.286.01:43:36.16#ibcon#*before return 0, iclass 22, count 0 2006.286.01:43:36.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:43:36.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:43:36.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.01:43:36.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.01:43:36.16$vck44/vb=1,4 2006.286.01:43:36.16#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.01:43:36.16#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.01:43:36.16#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:36.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:43:36.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:43:36.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:43:36.16#ibcon#enter wrdev, iclass 24, count 2 2006.286.01:43:36.16#ibcon#first serial, iclass 24, count 2 2006.286.01:43:36.16#ibcon#enter sib2, iclass 24, count 2 2006.286.01:43:36.16#ibcon#flushed, iclass 24, count 2 2006.286.01:43:36.16#ibcon#about to write, iclass 24, count 2 2006.286.01:43:36.16#ibcon#wrote, iclass 24, count 2 2006.286.01:43:36.16#ibcon#about to read 3, iclass 24, count 2 2006.286.01:43:36.18#ibcon#read 3, iclass 24, count 2 2006.286.01:43:36.18#ibcon#about to read 4, iclass 24, count 2 2006.286.01:43:36.18#ibcon#read 4, iclass 24, count 2 2006.286.01:43:36.18#ibcon#about to read 5, iclass 24, count 2 2006.286.01:43:36.18#ibcon#read 5, iclass 24, count 2 2006.286.01:43:36.18#ibcon#about to read 6, iclass 24, count 2 2006.286.01:43:36.18#ibcon#read 6, iclass 24, count 2 2006.286.01:43:36.18#ibcon#end of sib2, iclass 24, count 2 2006.286.01:43:36.18#ibcon#*mode == 0, iclass 24, count 2 2006.286.01:43:36.18#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.01:43:36.18#ibcon#[27=AT01-04\r\n] 2006.286.01:43:36.18#ibcon#*before write, iclass 24, count 2 2006.286.01:43:36.18#ibcon#enter sib2, iclass 24, count 2 2006.286.01:43:36.18#ibcon#flushed, iclass 24, count 2 2006.286.01:43:36.18#ibcon#about to write, iclass 24, count 2 2006.286.01:43:36.18#ibcon#wrote, iclass 24, count 2 2006.286.01:43:36.18#ibcon#about to read 3, iclass 24, count 2 2006.286.01:43:36.21#ibcon#read 3, iclass 24, count 2 2006.286.01:43:36.21#ibcon#about to read 4, iclass 24, count 2 2006.286.01:43:36.21#ibcon#read 4, iclass 24, count 2 2006.286.01:43:36.21#ibcon#about to read 5, iclass 24, count 2 2006.286.01:43:36.21#ibcon#read 5, iclass 24, count 2 2006.286.01:43:36.21#ibcon#about to read 6, iclass 24, count 2 2006.286.01:43:36.21#ibcon#read 6, iclass 24, count 2 2006.286.01:43:36.21#ibcon#end of sib2, iclass 24, count 2 2006.286.01:43:36.21#ibcon#*after write, iclass 24, count 2 2006.286.01:43:36.21#ibcon#*before return 0, iclass 24, count 2 2006.286.01:43:36.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:43:36.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:43:36.21#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.01:43:36.21#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:36.21#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:43:36.33#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:43:36.33#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:43:36.33#ibcon#enter wrdev, iclass 24, count 0 2006.286.01:43:36.33#ibcon#first serial, iclass 24, count 0 2006.286.01:43:36.33#ibcon#enter sib2, iclass 24, count 0 2006.286.01:43:36.33#ibcon#flushed, iclass 24, count 0 2006.286.01:43:36.33#ibcon#about to write, iclass 24, count 0 2006.286.01:43:36.33#ibcon#wrote, iclass 24, count 0 2006.286.01:43:36.33#ibcon#about to read 3, iclass 24, count 0 2006.286.01:43:36.35#ibcon#read 3, iclass 24, count 0 2006.286.01:43:36.35#ibcon#about to read 4, iclass 24, count 0 2006.286.01:43:36.35#ibcon#read 4, iclass 24, count 0 2006.286.01:43:36.35#ibcon#about to read 5, iclass 24, count 0 2006.286.01:43:36.35#ibcon#read 5, iclass 24, count 0 2006.286.01:43:36.35#ibcon#about to read 6, iclass 24, count 0 2006.286.01:43:36.35#ibcon#read 6, iclass 24, count 0 2006.286.01:43:36.35#ibcon#end of sib2, iclass 24, count 0 2006.286.01:43:36.35#ibcon#*mode == 0, iclass 24, count 0 2006.286.01:43:36.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.01:43:36.35#ibcon#[27=USB\r\n] 2006.286.01:43:36.35#ibcon#*before write, iclass 24, count 0 2006.286.01:43:36.35#ibcon#enter sib2, iclass 24, count 0 2006.286.01:43:36.35#ibcon#flushed, iclass 24, count 0 2006.286.01:43:36.35#ibcon#about to write, iclass 24, count 0 2006.286.01:43:36.35#ibcon#wrote, iclass 24, count 0 2006.286.01:43:36.35#ibcon#about to read 3, iclass 24, count 0 2006.286.01:43:36.38#ibcon#read 3, iclass 24, count 0 2006.286.01:43:36.38#ibcon#about to read 4, iclass 24, count 0 2006.286.01:43:36.38#ibcon#read 4, iclass 24, count 0 2006.286.01:43:36.38#ibcon#about to read 5, iclass 24, count 0 2006.286.01:43:36.38#ibcon#read 5, iclass 24, count 0 2006.286.01:43:36.38#ibcon#about to read 6, iclass 24, count 0 2006.286.01:43:36.38#ibcon#read 6, iclass 24, count 0 2006.286.01:43:36.38#ibcon#end of sib2, iclass 24, count 0 2006.286.01:43:36.38#ibcon#*after write, iclass 24, count 0 2006.286.01:43:36.38#ibcon#*before return 0, iclass 24, count 0 2006.286.01:43:36.38#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:43:36.38#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:43:36.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.01:43:36.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.01:43:36.38$vck44/vblo=2,634.99 2006.286.01:43:36.38#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.01:43:36.38#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.01:43:36.38#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:36.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:43:36.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:43:36.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:43:36.38#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:43:36.38#ibcon#first serial, iclass 26, count 0 2006.286.01:43:36.38#ibcon#enter sib2, iclass 26, count 0 2006.286.01:43:36.38#ibcon#flushed, iclass 26, count 0 2006.286.01:43:36.38#ibcon#about to write, iclass 26, count 0 2006.286.01:43:36.38#ibcon#wrote, iclass 26, count 0 2006.286.01:43:36.38#ibcon#about to read 3, iclass 26, count 0 2006.286.01:43:36.40#ibcon#read 3, iclass 26, count 0 2006.286.01:43:36.40#ibcon#about to read 4, iclass 26, count 0 2006.286.01:43:36.40#ibcon#read 4, iclass 26, count 0 2006.286.01:43:36.40#ibcon#about to read 5, iclass 26, count 0 2006.286.01:43:36.40#ibcon#read 5, iclass 26, count 0 2006.286.01:43:36.40#ibcon#about to read 6, iclass 26, count 0 2006.286.01:43:36.40#ibcon#read 6, iclass 26, count 0 2006.286.01:43:36.40#ibcon#end of sib2, iclass 26, count 0 2006.286.01:43:36.40#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:43:36.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:43:36.40#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:43:36.40#ibcon#*before write, iclass 26, count 0 2006.286.01:43:36.40#ibcon#enter sib2, iclass 26, count 0 2006.286.01:43:36.40#ibcon#flushed, iclass 26, count 0 2006.286.01:43:36.40#ibcon#about to write, iclass 26, count 0 2006.286.01:43:36.40#ibcon#wrote, iclass 26, count 0 2006.286.01:43:36.40#ibcon#about to read 3, iclass 26, count 0 2006.286.01:43:36.44#ibcon#read 3, iclass 26, count 0 2006.286.01:43:36.44#ibcon#about to read 4, iclass 26, count 0 2006.286.01:43:36.44#ibcon#read 4, iclass 26, count 0 2006.286.01:43:36.44#ibcon#about to read 5, iclass 26, count 0 2006.286.01:43:36.44#ibcon#read 5, iclass 26, count 0 2006.286.01:43:36.44#ibcon#about to read 6, iclass 26, count 0 2006.286.01:43:36.44#ibcon#read 6, iclass 26, count 0 2006.286.01:43:36.44#ibcon#end of sib2, iclass 26, count 0 2006.286.01:43:36.44#ibcon#*after write, iclass 26, count 0 2006.286.01:43:36.44#ibcon#*before return 0, iclass 26, count 0 2006.286.01:43:36.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:43:36.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:43:36.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:43:36.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:43:36.44$vck44/vb=2,5 2006.286.01:43:36.44#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.01:43:36.44#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.01:43:36.44#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:36.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:43:36.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:43:36.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:43:36.50#ibcon#enter wrdev, iclass 28, count 2 2006.286.01:43:36.50#ibcon#first serial, iclass 28, count 2 2006.286.01:43:36.50#ibcon#enter sib2, iclass 28, count 2 2006.286.01:43:36.50#ibcon#flushed, iclass 28, count 2 2006.286.01:43:36.50#ibcon#about to write, iclass 28, count 2 2006.286.01:43:36.50#ibcon#wrote, iclass 28, count 2 2006.286.01:43:36.50#ibcon#about to read 3, iclass 28, count 2 2006.286.01:43:36.52#ibcon#read 3, iclass 28, count 2 2006.286.01:43:36.52#ibcon#about to read 4, iclass 28, count 2 2006.286.01:43:36.52#ibcon#read 4, iclass 28, count 2 2006.286.01:43:36.52#ibcon#about to read 5, iclass 28, count 2 2006.286.01:43:36.52#ibcon#read 5, iclass 28, count 2 2006.286.01:43:36.52#ibcon#about to read 6, iclass 28, count 2 2006.286.01:43:36.52#ibcon#read 6, iclass 28, count 2 2006.286.01:43:36.52#ibcon#end of sib2, iclass 28, count 2 2006.286.01:43:36.52#ibcon#*mode == 0, iclass 28, count 2 2006.286.01:43:36.52#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.01:43:36.52#ibcon#[27=AT02-05\r\n] 2006.286.01:43:36.52#ibcon#*before write, iclass 28, count 2 2006.286.01:43:36.52#ibcon#enter sib2, iclass 28, count 2 2006.286.01:43:36.52#ibcon#flushed, iclass 28, count 2 2006.286.01:43:36.52#ibcon#about to write, iclass 28, count 2 2006.286.01:43:36.52#ibcon#wrote, iclass 28, count 2 2006.286.01:43:36.52#ibcon#about to read 3, iclass 28, count 2 2006.286.01:43:36.55#ibcon#read 3, iclass 28, count 2 2006.286.01:43:36.55#ibcon#about to read 4, iclass 28, count 2 2006.286.01:43:36.55#ibcon#read 4, iclass 28, count 2 2006.286.01:43:36.55#ibcon#about to read 5, iclass 28, count 2 2006.286.01:43:36.55#ibcon#read 5, iclass 28, count 2 2006.286.01:43:36.55#ibcon#about to read 6, iclass 28, count 2 2006.286.01:43:36.55#ibcon#read 6, iclass 28, count 2 2006.286.01:43:36.55#ibcon#end of sib2, iclass 28, count 2 2006.286.01:43:36.55#ibcon#*after write, iclass 28, count 2 2006.286.01:43:36.55#ibcon#*before return 0, iclass 28, count 2 2006.286.01:43:36.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:43:36.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:43:36.55#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.01:43:36.55#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:36.55#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:43:36.67#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:43:36.67#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:43:36.67#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:43:36.67#ibcon#first serial, iclass 28, count 0 2006.286.01:43:36.67#ibcon#enter sib2, iclass 28, count 0 2006.286.01:43:36.67#ibcon#flushed, iclass 28, count 0 2006.286.01:43:36.67#ibcon#about to write, iclass 28, count 0 2006.286.01:43:36.67#ibcon#wrote, iclass 28, count 0 2006.286.01:43:36.67#ibcon#about to read 3, iclass 28, count 0 2006.286.01:43:36.69#ibcon#read 3, iclass 28, count 0 2006.286.01:43:36.69#ibcon#about to read 4, iclass 28, count 0 2006.286.01:43:36.69#ibcon#read 4, iclass 28, count 0 2006.286.01:43:36.69#ibcon#about to read 5, iclass 28, count 0 2006.286.01:43:36.69#ibcon#read 5, iclass 28, count 0 2006.286.01:43:36.69#ibcon#about to read 6, iclass 28, count 0 2006.286.01:43:36.69#ibcon#read 6, iclass 28, count 0 2006.286.01:43:36.69#ibcon#end of sib2, iclass 28, count 0 2006.286.01:43:36.69#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:43:36.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:43:36.69#ibcon#[27=USB\r\n] 2006.286.01:43:36.69#ibcon#*before write, iclass 28, count 0 2006.286.01:43:36.69#ibcon#enter sib2, iclass 28, count 0 2006.286.01:43:36.69#ibcon#flushed, iclass 28, count 0 2006.286.01:43:36.69#ibcon#about to write, iclass 28, count 0 2006.286.01:43:36.69#ibcon#wrote, iclass 28, count 0 2006.286.01:43:36.69#ibcon#about to read 3, iclass 28, count 0 2006.286.01:43:36.72#ibcon#read 3, iclass 28, count 0 2006.286.01:43:36.72#ibcon#about to read 4, iclass 28, count 0 2006.286.01:43:36.72#ibcon#read 4, iclass 28, count 0 2006.286.01:43:36.72#ibcon#about to read 5, iclass 28, count 0 2006.286.01:43:36.72#ibcon#read 5, iclass 28, count 0 2006.286.01:43:36.72#ibcon#about to read 6, iclass 28, count 0 2006.286.01:43:36.72#ibcon#read 6, iclass 28, count 0 2006.286.01:43:36.72#ibcon#end of sib2, iclass 28, count 0 2006.286.01:43:36.72#ibcon#*after write, iclass 28, count 0 2006.286.01:43:36.72#ibcon#*before return 0, iclass 28, count 0 2006.286.01:43:36.72#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:43:36.72#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:43:36.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:43:36.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:43:36.72$vck44/vblo=3,649.99 2006.286.01:43:36.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.01:43:36.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.01:43:36.72#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:36.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:43:36.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:43:36.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:43:36.72#ibcon#enter wrdev, iclass 30, count 0 2006.286.01:43:36.72#ibcon#first serial, iclass 30, count 0 2006.286.01:43:36.72#ibcon#enter sib2, iclass 30, count 0 2006.286.01:43:36.72#ibcon#flushed, iclass 30, count 0 2006.286.01:43:36.72#ibcon#about to write, iclass 30, count 0 2006.286.01:43:36.72#ibcon#wrote, iclass 30, count 0 2006.286.01:43:36.72#ibcon#about to read 3, iclass 30, count 0 2006.286.01:43:36.74#ibcon#read 3, iclass 30, count 0 2006.286.01:43:36.74#ibcon#about to read 4, iclass 30, count 0 2006.286.01:43:36.74#ibcon#read 4, iclass 30, count 0 2006.286.01:43:36.74#ibcon#about to read 5, iclass 30, count 0 2006.286.01:43:36.74#ibcon#read 5, iclass 30, count 0 2006.286.01:43:36.74#ibcon#about to read 6, iclass 30, count 0 2006.286.01:43:36.74#ibcon#read 6, iclass 30, count 0 2006.286.01:43:36.74#ibcon#end of sib2, iclass 30, count 0 2006.286.01:43:36.74#ibcon#*mode == 0, iclass 30, count 0 2006.286.01:43:36.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.01:43:36.74#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:43:36.74#ibcon#*before write, iclass 30, count 0 2006.286.01:43:36.74#ibcon#enter sib2, iclass 30, count 0 2006.286.01:43:36.74#ibcon#flushed, iclass 30, count 0 2006.286.01:43:36.74#ibcon#about to write, iclass 30, count 0 2006.286.01:43:36.74#ibcon#wrote, iclass 30, count 0 2006.286.01:43:36.74#ibcon#about to read 3, iclass 30, count 0 2006.286.01:43:36.78#ibcon#read 3, iclass 30, count 0 2006.286.01:43:36.78#ibcon#about to read 4, iclass 30, count 0 2006.286.01:43:36.78#ibcon#read 4, iclass 30, count 0 2006.286.01:43:36.78#ibcon#about to read 5, iclass 30, count 0 2006.286.01:43:36.78#ibcon#read 5, iclass 30, count 0 2006.286.01:43:36.78#ibcon#about to read 6, iclass 30, count 0 2006.286.01:43:36.78#ibcon#read 6, iclass 30, count 0 2006.286.01:43:36.78#ibcon#end of sib2, iclass 30, count 0 2006.286.01:43:36.78#ibcon#*after write, iclass 30, count 0 2006.286.01:43:36.78#ibcon#*before return 0, iclass 30, count 0 2006.286.01:43:36.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:43:36.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:43:36.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.01:43:36.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.01:43:36.78$vck44/vb=3,4 2006.286.01:43:36.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.01:43:36.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.01:43:36.78#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:36.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:43:36.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:43:36.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:43:36.84#ibcon#enter wrdev, iclass 32, count 2 2006.286.01:43:36.84#ibcon#first serial, iclass 32, count 2 2006.286.01:43:36.84#ibcon#enter sib2, iclass 32, count 2 2006.286.01:43:36.84#ibcon#flushed, iclass 32, count 2 2006.286.01:43:36.84#ibcon#about to write, iclass 32, count 2 2006.286.01:43:36.84#ibcon#wrote, iclass 32, count 2 2006.286.01:43:36.84#ibcon#about to read 3, iclass 32, count 2 2006.286.01:43:36.86#ibcon#read 3, iclass 32, count 2 2006.286.01:43:36.86#ibcon#about to read 4, iclass 32, count 2 2006.286.01:43:36.86#ibcon#read 4, iclass 32, count 2 2006.286.01:43:36.86#ibcon#about to read 5, iclass 32, count 2 2006.286.01:43:36.86#ibcon#read 5, iclass 32, count 2 2006.286.01:43:36.86#ibcon#about to read 6, iclass 32, count 2 2006.286.01:43:36.86#ibcon#read 6, iclass 32, count 2 2006.286.01:43:36.86#ibcon#end of sib2, iclass 32, count 2 2006.286.01:43:36.86#ibcon#*mode == 0, iclass 32, count 2 2006.286.01:43:36.86#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.01:43:36.86#ibcon#[27=AT03-04\r\n] 2006.286.01:43:36.86#ibcon#*before write, iclass 32, count 2 2006.286.01:43:36.86#ibcon#enter sib2, iclass 32, count 2 2006.286.01:43:36.86#ibcon#flushed, iclass 32, count 2 2006.286.01:43:36.86#ibcon#about to write, iclass 32, count 2 2006.286.01:43:36.86#ibcon#wrote, iclass 32, count 2 2006.286.01:43:36.86#ibcon#about to read 3, iclass 32, count 2 2006.286.01:43:36.89#ibcon#read 3, iclass 32, count 2 2006.286.01:43:36.89#ibcon#about to read 4, iclass 32, count 2 2006.286.01:43:36.89#ibcon#read 4, iclass 32, count 2 2006.286.01:43:36.89#ibcon#about to read 5, iclass 32, count 2 2006.286.01:43:36.89#ibcon#read 5, iclass 32, count 2 2006.286.01:43:36.89#ibcon#about to read 6, iclass 32, count 2 2006.286.01:43:36.89#ibcon#read 6, iclass 32, count 2 2006.286.01:43:36.89#ibcon#end of sib2, iclass 32, count 2 2006.286.01:43:36.89#ibcon#*after write, iclass 32, count 2 2006.286.01:43:36.89#ibcon#*before return 0, iclass 32, count 2 2006.286.01:43:36.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:43:36.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:43:36.89#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.01:43:36.89#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:36.89#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:43:37.01#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:43:37.01#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:43:37.01#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:43:37.01#ibcon#first serial, iclass 32, count 0 2006.286.01:43:37.01#ibcon#enter sib2, iclass 32, count 0 2006.286.01:43:37.01#ibcon#flushed, iclass 32, count 0 2006.286.01:43:37.01#ibcon#about to write, iclass 32, count 0 2006.286.01:43:37.01#ibcon#wrote, iclass 32, count 0 2006.286.01:43:37.01#ibcon#about to read 3, iclass 32, count 0 2006.286.01:43:37.03#ibcon#read 3, iclass 32, count 0 2006.286.01:43:37.03#ibcon#about to read 4, iclass 32, count 0 2006.286.01:43:37.03#ibcon#read 4, iclass 32, count 0 2006.286.01:43:37.03#ibcon#about to read 5, iclass 32, count 0 2006.286.01:43:37.03#ibcon#read 5, iclass 32, count 0 2006.286.01:43:37.03#ibcon#about to read 6, iclass 32, count 0 2006.286.01:43:37.03#ibcon#read 6, iclass 32, count 0 2006.286.01:43:37.03#ibcon#end of sib2, iclass 32, count 0 2006.286.01:43:37.03#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:43:37.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:43:37.03#ibcon#[27=USB\r\n] 2006.286.01:43:37.03#ibcon#*before write, iclass 32, count 0 2006.286.01:43:37.03#ibcon#enter sib2, iclass 32, count 0 2006.286.01:43:37.03#ibcon#flushed, iclass 32, count 0 2006.286.01:43:37.03#ibcon#about to write, iclass 32, count 0 2006.286.01:43:37.03#ibcon#wrote, iclass 32, count 0 2006.286.01:43:37.03#ibcon#about to read 3, iclass 32, count 0 2006.286.01:43:37.06#ibcon#read 3, iclass 32, count 0 2006.286.01:43:37.06#ibcon#about to read 4, iclass 32, count 0 2006.286.01:43:37.06#ibcon#read 4, iclass 32, count 0 2006.286.01:43:37.06#ibcon#about to read 5, iclass 32, count 0 2006.286.01:43:37.06#ibcon#read 5, iclass 32, count 0 2006.286.01:43:37.06#ibcon#about to read 6, iclass 32, count 0 2006.286.01:43:37.06#ibcon#read 6, iclass 32, count 0 2006.286.01:43:37.06#ibcon#end of sib2, iclass 32, count 0 2006.286.01:43:37.06#ibcon#*after write, iclass 32, count 0 2006.286.01:43:37.06#ibcon#*before return 0, iclass 32, count 0 2006.286.01:43:37.06#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:43:37.06#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:43:37.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:43:37.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:43:37.06$vck44/vblo=4,679.99 2006.286.01:43:37.06#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.01:43:37.06#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.01:43:37.06#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:37.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:43:37.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:43:37.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:43:37.06#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:43:37.06#ibcon#first serial, iclass 34, count 0 2006.286.01:43:37.06#ibcon#enter sib2, iclass 34, count 0 2006.286.01:43:37.06#ibcon#flushed, iclass 34, count 0 2006.286.01:43:37.06#ibcon#about to write, iclass 34, count 0 2006.286.01:43:37.06#ibcon#wrote, iclass 34, count 0 2006.286.01:43:37.06#ibcon#about to read 3, iclass 34, count 0 2006.286.01:43:37.08#ibcon#read 3, iclass 34, count 0 2006.286.01:43:37.08#ibcon#about to read 4, iclass 34, count 0 2006.286.01:43:37.08#ibcon#read 4, iclass 34, count 0 2006.286.01:43:37.08#ibcon#about to read 5, iclass 34, count 0 2006.286.01:43:37.08#ibcon#read 5, iclass 34, count 0 2006.286.01:43:37.08#ibcon#about to read 6, iclass 34, count 0 2006.286.01:43:37.08#ibcon#read 6, iclass 34, count 0 2006.286.01:43:37.08#ibcon#end of sib2, iclass 34, count 0 2006.286.01:43:37.08#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:43:37.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:43:37.08#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:43:37.08#ibcon#*before write, iclass 34, count 0 2006.286.01:43:37.08#ibcon#enter sib2, iclass 34, count 0 2006.286.01:43:37.08#ibcon#flushed, iclass 34, count 0 2006.286.01:43:37.08#ibcon#about to write, iclass 34, count 0 2006.286.01:43:37.08#ibcon#wrote, iclass 34, count 0 2006.286.01:43:37.08#ibcon#about to read 3, iclass 34, count 0 2006.286.01:43:37.12#ibcon#read 3, iclass 34, count 0 2006.286.01:43:37.12#ibcon#about to read 4, iclass 34, count 0 2006.286.01:43:37.12#ibcon#read 4, iclass 34, count 0 2006.286.01:43:37.12#ibcon#about to read 5, iclass 34, count 0 2006.286.01:43:37.12#ibcon#read 5, iclass 34, count 0 2006.286.01:43:37.12#ibcon#about to read 6, iclass 34, count 0 2006.286.01:43:37.12#ibcon#read 6, iclass 34, count 0 2006.286.01:43:37.12#ibcon#end of sib2, iclass 34, count 0 2006.286.01:43:37.12#ibcon#*after write, iclass 34, count 0 2006.286.01:43:37.12#ibcon#*before return 0, iclass 34, count 0 2006.286.01:43:37.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:43:37.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:43:37.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:43:37.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:43:37.12$vck44/vb=4,5 2006.286.01:43:37.12#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.01:43:37.12#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.01:43:37.12#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:37.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:43:37.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:43:37.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:43:37.18#ibcon#enter wrdev, iclass 36, count 2 2006.286.01:43:37.18#ibcon#first serial, iclass 36, count 2 2006.286.01:43:37.18#ibcon#enter sib2, iclass 36, count 2 2006.286.01:43:37.18#ibcon#flushed, iclass 36, count 2 2006.286.01:43:37.18#ibcon#about to write, iclass 36, count 2 2006.286.01:43:37.18#ibcon#wrote, iclass 36, count 2 2006.286.01:43:37.18#ibcon#about to read 3, iclass 36, count 2 2006.286.01:43:37.20#ibcon#read 3, iclass 36, count 2 2006.286.01:43:37.20#ibcon#about to read 4, iclass 36, count 2 2006.286.01:43:37.20#ibcon#read 4, iclass 36, count 2 2006.286.01:43:37.20#ibcon#about to read 5, iclass 36, count 2 2006.286.01:43:37.20#ibcon#read 5, iclass 36, count 2 2006.286.01:43:37.20#ibcon#about to read 6, iclass 36, count 2 2006.286.01:43:37.20#ibcon#read 6, iclass 36, count 2 2006.286.01:43:37.20#ibcon#end of sib2, iclass 36, count 2 2006.286.01:43:37.20#ibcon#*mode == 0, iclass 36, count 2 2006.286.01:43:37.20#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.01:43:37.20#ibcon#[27=AT04-05\r\n] 2006.286.01:43:37.20#ibcon#*before write, iclass 36, count 2 2006.286.01:43:37.20#ibcon#enter sib2, iclass 36, count 2 2006.286.01:43:37.20#ibcon#flushed, iclass 36, count 2 2006.286.01:43:37.20#ibcon#about to write, iclass 36, count 2 2006.286.01:43:37.20#ibcon#wrote, iclass 36, count 2 2006.286.01:43:37.20#ibcon#about to read 3, iclass 36, count 2 2006.286.01:43:37.23#ibcon#read 3, iclass 36, count 2 2006.286.01:43:37.23#ibcon#about to read 4, iclass 36, count 2 2006.286.01:43:37.23#ibcon#read 4, iclass 36, count 2 2006.286.01:43:37.23#ibcon#about to read 5, iclass 36, count 2 2006.286.01:43:37.23#ibcon#read 5, iclass 36, count 2 2006.286.01:43:37.23#ibcon#about to read 6, iclass 36, count 2 2006.286.01:43:37.23#ibcon#read 6, iclass 36, count 2 2006.286.01:43:37.23#ibcon#end of sib2, iclass 36, count 2 2006.286.01:43:37.23#ibcon#*after write, iclass 36, count 2 2006.286.01:43:37.23#ibcon#*before return 0, iclass 36, count 2 2006.286.01:43:37.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:43:37.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:43:37.23#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.01:43:37.23#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:37.23#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:43:37.35#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:43:37.35#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:43:37.35#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:43:37.35#ibcon#first serial, iclass 36, count 0 2006.286.01:43:37.35#ibcon#enter sib2, iclass 36, count 0 2006.286.01:43:37.35#ibcon#flushed, iclass 36, count 0 2006.286.01:43:37.35#ibcon#about to write, iclass 36, count 0 2006.286.01:43:37.35#ibcon#wrote, iclass 36, count 0 2006.286.01:43:37.35#ibcon#about to read 3, iclass 36, count 0 2006.286.01:43:37.37#ibcon#read 3, iclass 36, count 0 2006.286.01:43:37.37#ibcon#about to read 4, iclass 36, count 0 2006.286.01:43:37.37#ibcon#read 4, iclass 36, count 0 2006.286.01:43:37.37#ibcon#about to read 5, iclass 36, count 0 2006.286.01:43:37.37#ibcon#read 5, iclass 36, count 0 2006.286.01:43:37.37#ibcon#about to read 6, iclass 36, count 0 2006.286.01:43:37.37#ibcon#read 6, iclass 36, count 0 2006.286.01:43:37.37#ibcon#end of sib2, iclass 36, count 0 2006.286.01:43:37.37#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:43:37.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:43:37.37#ibcon#[27=USB\r\n] 2006.286.01:43:37.37#ibcon#*before write, iclass 36, count 0 2006.286.01:43:37.37#ibcon#enter sib2, iclass 36, count 0 2006.286.01:43:37.37#ibcon#flushed, iclass 36, count 0 2006.286.01:43:37.37#ibcon#about to write, iclass 36, count 0 2006.286.01:43:37.37#ibcon#wrote, iclass 36, count 0 2006.286.01:43:37.37#ibcon#about to read 3, iclass 36, count 0 2006.286.01:43:37.40#ibcon#read 3, iclass 36, count 0 2006.286.01:43:37.40#ibcon#about to read 4, iclass 36, count 0 2006.286.01:43:37.40#ibcon#read 4, iclass 36, count 0 2006.286.01:43:37.40#ibcon#about to read 5, iclass 36, count 0 2006.286.01:43:37.40#ibcon#read 5, iclass 36, count 0 2006.286.01:43:37.40#ibcon#about to read 6, iclass 36, count 0 2006.286.01:43:37.40#ibcon#read 6, iclass 36, count 0 2006.286.01:43:37.40#ibcon#end of sib2, iclass 36, count 0 2006.286.01:43:37.40#ibcon#*after write, iclass 36, count 0 2006.286.01:43:37.40#ibcon#*before return 0, iclass 36, count 0 2006.286.01:43:37.40#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:43:37.40#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:43:37.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:43:37.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:43:37.40$vck44/vblo=5,709.99 2006.286.01:43:37.40#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.01:43:37.40#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.01:43:37.40#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:37.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:43:37.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:43:37.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:43:37.40#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:43:37.40#ibcon#first serial, iclass 38, count 0 2006.286.01:43:37.40#ibcon#enter sib2, iclass 38, count 0 2006.286.01:43:37.40#ibcon#flushed, iclass 38, count 0 2006.286.01:43:37.40#ibcon#about to write, iclass 38, count 0 2006.286.01:43:37.40#ibcon#wrote, iclass 38, count 0 2006.286.01:43:37.40#ibcon#about to read 3, iclass 38, count 0 2006.286.01:43:37.42#ibcon#read 3, iclass 38, count 0 2006.286.01:43:37.42#ibcon#about to read 4, iclass 38, count 0 2006.286.01:43:37.42#ibcon#read 4, iclass 38, count 0 2006.286.01:43:37.42#ibcon#about to read 5, iclass 38, count 0 2006.286.01:43:37.42#ibcon#read 5, iclass 38, count 0 2006.286.01:43:37.42#ibcon#about to read 6, iclass 38, count 0 2006.286.01:43:37.42#ibcon#read 6, iclass 38, count 0 2006.286.01:43:37.42#ibcon#end of sib2, iclass 38, count 0 2006.286.01:43:37.42#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:43:37.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:43:37.42#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:43:37.42#ibcon#*before write, iclass 38, count 0 2006.286.01:43:37.42#ibcon#enter sib2, iclass 38, count 0 2006.286.01:43:37.42#ibcon#flushed, iclass 38, count 0 2006.286.01:43:37.42#ibcon#about to write, iclass 38, count 0 2006.286.01:43:37.42#ibcon#wrote, iclass 38, count 0 2006.286.01:43:37.42#ibcon#about to read 3, iclass 38, count 0 2006.286.01:43:37.46#ibcon#read 3, iclass 38, count 0 2006.286.01:43:37.46#ibcon#about to read 4, iclass 38, count 0 2006.286.01:43:37.46#ibcon#read 4, iclass 38, count 0 2006.286.01:43:37.46#ibcon#about to read 5, iclass 38, count 0 2006.286.01:43:37.46#ibcon#read 5, iclass 38, count 0 2006.286.01:43:37.46#ibcon#about to read 6, iclass 38, count 0 2006.286.01:43:37.46#ibcon#read 6, iclass 38, count 0 2006.286.01:43:37.46#ibcon#end of sib2, iclass 38, count 0 2006.286.01:43:37.46#ibcon#*after write, iclass 38, count 0 2006.286.01:43:37.46#ibcon#*before return 0, iclass 38, count 0 2006.286.01:43:37.46#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:43:37.46#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:43:37.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:43:37.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:43:37.46$vck44/vb=5,4 2006.286.01:43:37.46#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.01:43:37.46#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.01:43:37.46#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:37.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:43:37.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:43:37.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:43:37.52#ibcon#enter wrdev, iclass 40, count 2 2006.286.01:43:37.52#ibcon#first serial, iclass 40, count 2 2006.286.01:43:37.52#ibcon#enter sib2, iclass 40, count 2 2006.286.01:43:37.52#ibcon#flushed, iclass 40, count 2 2006.286.01:43:37.52#ibcon#about to write, iclass 40, count 2 2006.286.01:43:37.52#ibcon#wrote, iclass 40, count 2 2006.286.01:43:37.52#ibcon#about to read 3, iclass 40, count 2 2006.286.01:43:37.54#ibcon#read 3, iclass 40, count 2 2006.286.01:43:37.54#ibcon#about to read 4, iclass 40, count 2 2006.286.01:43:37.54#ibcon#read 4, iclass 40, count 2 2006.286.01:43:37.54#ibcon#about to read 5, iclass 40, count 2 2006.286.01:43:37.54#ibcon#read 5, iclass 40, count 2 2006.286.01:43:37.54#ibcon#about to read 6, iclass 40, count 2 2006.286.01:43:37.54#ibcon#read 6, iclass 40, count 2 2006.286.01:43:37.54#ibcon#end of sib2, iclass 40, count 2 2006.286.01:43:37.54#ibcon#*mode == 0, iclass 40, count 2 2006.286.01:43:37.54#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.01:43:37.54#ibcon#[27=AT05-04\r\n] 2006.286.01:43:37.54#ibcon#*before write, iclass 40, count 2 2006.286.01:43:37.54#ibcon#enter sib2, iclass 40, count 2 2006.286.01:43:37.54#ibcon#flushed, iclass 40, count 2 2006.286.01:43:37.54#ibcon#about to write, iclass 40, count 2 2006.286.01:43:37.54#ibcon#wrote, iclass 40, count 2 2006.286.01:43:37.54#ibcon#about to read 3, iclass 40, count 2 2006.286.01:43:37.57#ibcon#read 3, iclass 40, count 2 2006.286.01:43:37.57#ibcon#about to read 4, iclass 40, count 2 2006.286.01:43:37.57#ibcon#read 4, iclass 40, count 2 2006.286.01:43:37.57#ibcon#about to read 5, iclass 40, count 2 2006.286.01:43:37.57#ibcon#read 5, iclass 40, count 2 2006.286.01:43:37.57#ibcon#about to read 6, iclass 40, count 2 2006.286.01:43:37.57#ibcon#read 6, iclass 40, count 2 2006.286.01:43:37.57#ibcon#end of sib2, iclass 40, count 2 2006.286.01:43:37.57#ibcon#*after write, iclass 40, count 2 2006.286.01:43:37.57#ibcon#*before return 0, iclass 40, count 2 2006.286.01:43:37.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:43:37.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:43:37.57#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.01:43:37.57#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:37.57#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:43:37.69#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:43:37.69#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:43:37.69#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:43:37.69#ibcon#first serial, iclass 40, count 0 2006.286.01:43:37.69#ibcon#enter sib2, iclass 40, count 0 2006.286.01:43:37.69#ibcon#flushed, iclass 40, count 0 2006.286.01:43:37.69#ibcon#about to write, iclass 40, count 0 2006.286.01:43:37.69#ibcon#wrote, iclass 40, count 0 2006.286.01:43:37.69#ibcon#about to read 3, iclass 40, count 0 2006.286.01:43:37.71#ibcon#read 3, iclass 40, count 0 2006.286.01:43:37.71#ibcon#about to read 4, iclass 40, count 0 2006.286.01:43:37.71#ibcon#read 4, iclass 40, count 0 2006.286.01:43:37.71#ibcon#about to read 5, iclass 40, count 0 2006.286.01:43:37.71#ibcon#read 5, iclass 40, count 0 2006.286.01:43:37.71#ibcon#about to read 6, iclass 40, count 0 2006.286.01:43:37.71#ibcon#read 6, iclass 40, count 0 2006.286.01:43:37.71#ibcon#end of sib2, iclass 40, count 0 2006.286.01:43:37.71#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:43:37.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:43:37.71#ibcon#[27=USB\r\n] 2006.286.01:43:37.71#ibcon#*before write, iclass 40, count 0 2006.286.01:43:37.71#ibcon#enter sib2, iclass 40, count 0 2006.286.01:43:37.71#ibcon#flushed, iclass 40, count 0 2006.286.01:43:37.71#ibcon#about to write, iclass 40, count 0 2006.286.01:43:37.71#ibcon#wrote, iclass 40, count 0 2006.286.01:43:37.71#ibcon#about to read 3, iclass 40, count 0 2006.286.01:43:37.74#ibcon#read 3, iclass 40, count 0 2006.286.01:43:37.74#ibcon#about to read 4, iclass 40, count 0 2006.286.01:43:37.74#ibcon#read 4, iclass 40, count 0 2006.286.01:43:37.74#ibcon#about to read 5, iclass 40, count 0 2006.286.01:43:37.74#ibcon#read 5, iclass 40, count 0 2006.286.01:43:37.74#ibcon#about to read 6, iclass 40, count 0 2006.286.01:43:37.74#ibcon#read 6, iclass 40, count 0 2006.286.01:43:37.74#ibcon#end of sib2, iclass 40, count 0 2006.286.01:43:37.74#ibcon#*after write, iclass 40, count 0 2006.286.01:43:37.74#ibcon#*before return 0, iclass 40, count 0 2006.286.01:43:37.74#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:43:37.74#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:43:37.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:43:37.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:43:37.74$vck44/vblo=6,719.99 2006.286.01:43:37.74#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.01:43:37.74#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.01:43:37.74#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:37.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:43:37.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:43:37.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:43:37.74#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:43:37.74#ibcon#first serial, iclass 4, count 0 2006.286.01:43:37.74#ibcon#enter sib2, iclass 4, count 0 2006.286.01:43:37.74#ibcon#flushed, iclass 4, count 0 2006.286.01:43:37.74#ibcon#about to write, iclass 4, count 0 2006.286.01:43:37.74#ibcon#wrote, iclass 4, count 0 2006.286.01:43:37.74#ibcon#about to read 3, iclass 4, count 0 2006.286.01:43:37.76#ibcon#read 3, iclass 4, count 0 2006.286.01:43:37.76#ibcon#about to read 4, iclass 4, count 0 2006.286.01:43:37.76#ibcon#read 4, iclass 4, count 0 2006.286.01:43:37.76#ibcon#about to read 5, iclass 4, count 0 2006.286.01:43:37.76#ibcon#read 5, iclass 4, count 0 2006.286.01:43:37.76#ibcon#about to read 6, iclass 4, count 0 2006.286.01:43:37.76#ibcon#read 6, iclass 4, count 0 2006.286.01:43:37.76#ibcon#end of sib2, iclass 4, count 0 2006.286.01:43:37.76#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:43:37.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:43:37.76#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:43:37.76#ibcon#*before write, iclass 4, count 0 2006.286.01:43:37.76#ibcon#enter sib2, iclass 4, count 0 2006.286.01:43:37.76#ibcon#flushed, iclass 4, count 0 2006.286.01:43:37.76#ibcon#about to write, iclass 4, count 0 2006.286.01:43:37.76#ibcon#wrote, iclass 4, count 0 2006.286.01:43:37.76#ibcon#about to read 3, iclass 4, count 0 2006.286.01:43:37.80#ibcon#read 3, iclass 4, count 0 2006.286.01:43:37.80#ibcon#about to read 4, iclass 4, count 0 2006.286.01:43:37.80#ibcon#read 4, iclass 4, count 0 2006.286.01:43:37.80#ibcon#about to read 5, iclass 4, count 0 2006.286.01:43:37.80#ibcon#read 5, iclass 4, count 0 2006.286.01:43:37.80#ibcon#about to read 6, iclass 4, count 0 2006.286.01:43:37.80#ibcon#read 6, iclass 4, count 0 2006.286.01:43:37.80#ibcon#end of sib2, iclass 4, count 0 2006.286.01:43:37.80#ibcon#*after write, iclass 4, count 0 2006.286.01:43:37.80#ibcon#*before return 0, iclass 4, count 0 2006.286.01:43:37.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:43:37.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:43:37.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:43:37.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:43:37.80$vck44/vb=6,3 2006.286.01:43:37.80#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.01:43:37.80#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.01:43:37.80#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:37.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:43:37.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:43:37.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:43:37.86#ibcon#enter wrdev, iclass 6, count 2 2006.286.01:43:37.86#ibcon#first serial, iclass 6, count 2 2006.286.01:43:37.86#ibcon#enter sib2, iclass 6, count 2 2006.286.01:43:37.86#ibcon#flushed, iclass 6, count 2 2006.286.01:43:37.86#ibcon#about to write, iclass 6, count 2 2006.286.01:43:37.86#ibcon#wrote, iclass 6, count 2 2006.286.01:43:37.86#ibcon#about to read 3, iclass 6, count 2 2006.286.01:43:37.88#ibcon#read 3, iclass 6, count 2 2006.286.01:43:37.88#ibcon#about to read 4, iclass 6, count 2 2006.286.01:43:37.88#ibcon#read 4, iclass 6, count 2 2006.286.01:43:37.88#ibcon#about to read 5, iclass 6, count 2 2006.286.01:43:37.88#ibcon#read 5, iclass 6, count 2 2006.286.01:43:37.88#ibcon#about to read 6, iclass 6, count 2 2006.286.01:43:37.88#ibcon#read 6, iclass 6, count 2 2006.286.01:43:37.88#ibcon#end of sib2, iclass 6, count 2 2006.286.01:43:37.88#ibcon#*mode == 0, iclass 6, count 2 2006.286.01:43:37.88#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.01:43:37.88#ibcon#[27=AT06-03\r\n] 2006.286.01:43:37.88#ibcon#*before write, iclass 6, count 2 2006.286.01:43:37.88#ibcon#enter sib2, iclass 6, count 2 2006.286.01:43:37.88#ibcon#flushed, iclass 6, count 2 2006.286.01:43:37.88#ibcon#about to write, iclass 6, count 2 2006.286.01:43:37.88#ibcon#wrote, iclass 6, count 2 2006.286.01:43:37.88#ibcon#about to read 3, iclass 6, count 2 2006.286.01:43:37.91#ibcon#read 3, iclass 6, count 2 2006.286.01:43:37.91#ibcon#about to read 4, iclass 6, count 2 2006.286.01:43:37.91#ibcon#read 4, iclass 6, count 2 2006.286.01:43:37.91#ibcon#about to read 5, iclass 6, count 2 2006.286.01:43:37.91#ibcon#read 5, iclass 6, count 2 2006.286.01:43:37.91#ibcon#about to read 6, iclass 6, count 2 2006.286.01:43:37.91#ibcon#read 6, iclass 6, count 2 2006.286.01:43:37.91#ibcon#end of sib2, iclass 6, count 2 2006.286.01:43:37.91#ibcon#*after write, iclass 6, count 2 2006.286.01:43:37.91#ibcon#*before return 0, iclass 6, count 2 2006.286.01:43:37.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:43:37.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:43:37.91#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.01:43:37.91#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:37.91#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:43:38.03#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:43:38.03#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:43:38.03#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:43:38.03#ibcon#first serial, iclass 6, count 0 2006.286.01:43:38.03#ibcon#enter sib2, iclass 6, count 0 2006.286.01:43:38.03#ibcon#flushed, iclass 6, count 0 2006.286.01:43:38.03#ibcon#about to write, iclass 6, count 0 2006.286.01:43:38.03#ibcon#wrote, iclass 6, count 0 2006.286.01:43:38.03#ibcon#about to read 3, iclass 6, count 0 2006.286.01:43:38.05#ibcon#read 3, iclass 6, count 0 2006.286.01:43:38.05#ibcon#about to read 4, iclass 6, count 0 2006.286.01:43:38.05#ibcon#read 4, iclass 6, count 0 2006.286.01:43:38.05#ibcon#about to read 5, iclass 6, count 0 2006.286.01:43:38.05#ibcon#read 5, iclass 6, count 0 2006.286.01:43:38.05#ibcon#about to read 6, iclass 6, count 0 2006.286.01:43:38.05#ibcon#read 6, iclass 6, count 0 2006.286.01:43:38.05#ibcon#end of sib2, iclass 6, count 0 2006.286.01:43:38.05#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:43:38.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:43:38.05#ibcon#[27=USB\r\n] 2006.286.01:43:38.05#ibcon#*before write, iclass 6, count 0 2006.286.01:43:38.05#ibcon#enter sib2, iclass 6, count 0 2006.286.01:43:38.05#ibcon#flushed, iclass 6, count 0 2006.286.01:43:38.05#ibcon#about to write, iclass 6, count 0 2006.286.01:43:38.05#ibcon#wrote, iclass 6, count 0 2006.286.01:43:38.05#ibcon#about to read 3, iclass 6, count 0 2006.286.01:43:38.08#ibcon#read 3, iclass 6, count 0 2006.286.01:43:38.08#ibcon#about to read 4, iclass 6, count 0 2006.286.01:43:38.08#ibcon#read 4, iclass 6, count 0 2006.286.01:43:38.08#ibcon#about to read 5, iclass 6, count 0 2006.286.01:43:38.08#ibcon#read 5, iclass 6, count 0 2006.286.01:43:38.08#ibcon#about to read 6, iclass 6, count 0 2006.286.01:43:38.08#ibcon#read 6, iclass 6, count 0 2006.286.01:43:38.08#ibcon#end of sib2, iclass 6, count 0 2006.286.01:43:38.08#ibcon#*after write, iclass 6, count 0 2006.286.01:43:38.08#ibcon#*before return 0, iclass 6, count 0 2006.286.01:43:38.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:43:38.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:43:38.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:43:38.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:43:38.08$vck44/vblo=7,734.99 2006.286.01:43:38.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.01:43:38.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.01:43:38.08#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:38.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:43:38.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:43:38.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:43:38.08#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:43:38.08#ibcon#first serial, iclass 10, count 0 2006.286.01:43:38.08#ibcon#enter sib2, iclass 10, count 0 2006.286.01:43:38.08#ibcon#flushed, iclass 10, count 0 2006.286.01:43:38.08#ibcon#about to write, iclass 10, count 0 2006.286.01:43:38.08#ibcon#wrote, iclass 10, count 0 2006.286.01:43:38.08#ibcon#about to read 3, iclass 10, count 0 2006.286.01:43:38.10#ibcon#read 3, iclass 10, count 0 2006.286.01:43:38.10#ibcon#about to read 4, iclass 10, count 0 2006.286.01:43:38.10#ibcon#read 4, iclass 10, count 0 2006.286.01:43:38.10#ibcon#about to read 5, iclass 10, count 0 2006.286.01:43:38.10#ibcon#read 5, iclass 10, count 0 2006.286.01:43:38.10#ibcon#about to read 6, iclass 10, count 0 2006.286.01:43:38.10#ibcon#read 6, iclass 10, count 0 2006.286.01:43:38.10#ibcon#end of sib2, iclass 10, count 0 2006.286.01:43:38.10#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:43:38.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:43:38.10#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:43:38.10#ibcon#*before write, iclass 10, count 0 2006.286.01:43:38.10#ibcon#enter sib2, iclass 10, count 0 2006.286.01:43:38.10#ibcon#flushed, iclass 10, count 0 2006.286.01:43:38.10#ibcon#about to write, iclass 10, count 0 2006.286.01:43:38.10#ibcon#wrote, iclass 10, count 0 2006.286.01:43:38.10#ibcon#about to read 3, iclass 10, count 0 2006.286.01:43:38.14#ibcon#read 3, iclass 10, count 0 2006.286.01:43:38.14#ibcon#about to read 4, iclass 10, count 0 2006.286.01:43:38.14#ibcon#read 4, iclass 10, count 0 2006.286.01:43:38.14#ibcon#about to read 5, iclass 10, count 0 2006.286.01:43:38.14#ibcon#read 5, iclass 10, count 0 2006.286.01:43:38.14#ibcon#about to read 6, iclass 10, count 0 2006.286.01:43:38.14#ibcon#read 6, iclass 10, count 0 2006.286.01:43:38.14#ibcon#end of sib2, iclass 10, count 0 2006.286.01:43:38.14#ibcon#*after write, iclass 10, count 0 2006.286.01:43:38.14#ibcon#*before return 0, iclass 10, count 0 2006.286.01:43:38.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:43:38.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:43:38.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:43:38.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:43:38.14$vck44/vb=7,4 2006.286.01:43:38.14#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.01:43:38.14#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.01:43:38.14#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:38.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:43:38.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:43:38.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:43:38.20#ibcon#enter wrdev, iclass 12, count 2 2006.286.01:43:38.20#ibcon#first serial, iclass 12, count 2 2006.286.01:43:38.20#ibcon#enter sib2, iclass 12, count 2 2006.286.01:43:38.20#ibcon#flushed, iclass 12, count 2 2006.286.01:43:38.20#ibcon#about to write, iclass 12, count 2 2006.286.01:43:38.20#ibcon#wrote, iclass 12, count 2 2006.286.01:43:38.20#ibcon#about to read 3, iclass 12, count 2 2006.286.01:43:38.22#ibcon#read 3, iclass 12, count 2 2006.286.01:43:38.22#ibcon#about to read 4, iclass 12, count 2 2006.286.01:43:38.22#ibcon#read 4, iclass 12, count 2 2006.286.01:43:38.22#ibcon#about to read 5, iclass 12, count 2 2006.286.01:43:38.22#ibcon#read 5, iclass 12, count 2 2006.286.01:43:38.22#ibcon#about to read 6, iclass 12, count 2 2006.286.01:43:38.22#ibcon#read 6, iclass 12, count 2 2006.286.01:43:38.22#ibcon#end of sib2, iclass 12, count 2 2006.286.01:43:38.22#ibcon#*mode == 0, iclass 12, count 2 2006.286.01:43:38.22#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.01:43:38.22#ibcon#[27=AT07-04\r\n] 2006.286.01:43:38.22#ibcon#*before write, iclass 12, count 2 2006.286.01:43:38.22#ibcon#enter sib2, iclass 12, count 2 2006.286.01:43:38.22#ibcon#flushed, iclass 12, count 2 2006.286.01:43:38.22#ibcon#about to write, iclass 12, count 2 2006.286.01:43:38.22#ibcon#wrote, iclass 12, count 2 2006.286.01:43:38.22#ibcon#about to read 3, iclass 12, count 2 2006.286.01:43:38.25#ibcon#read 3, iclass 12, count 2 2006.286.01:43:38.25#ibcon#about to read 4, iclass 12, count 2 2006.286.01:43:38.25#ibcon#read 4, iclass 12, count 2 2006.286.01:43:38.25#ibcon#about to read 5, iclass 12, count 2 2006.286.01:43:38.25#ibcon#read 5, iclass 12, count 2 2006.286.01:43:38.25#ibcon#about to read 6, iclass 12, count 2 2006.286.01:43:38.25#ibcon#read 6, iclass 12, count 2 2006.286.01:43:38.25#ibcon#end of sib2, iclass 12, count 2 2006.286.01:43:38.25#ibcon#*after write, iclass 12, count 2 2006.286.01:43:38.25#ibcon#*before return 0, iclass 12, count 2 2006.286.01:43:38.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:43:38.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:43:38.25#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.01:43:38.25#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:38.25#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:43:38.37#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:43:38.37#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:43:38.37#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:43:38.37#ibcon#first serial, iclass 12, count 0 2006.286.01:43:38.37#ibcon#enter sib2, iclass 12, count 0 2006.286.01:43:38.37#ibcon#flushed, iclass 12, count 0 2006.286.01:43:38.37#ibcon#about to write, iclass 12, count 0 2006.286.01:43:38.37#ibcon#wrote, iclass 12, count 0 2006.286.01:43:38.37#ibcon#about to read 3, iclass 12, count 0 2006.286.01:43:38.39#ibcon#read 3, iclass 12, count 0 2006.286.01:43:38.39#ibcon#about to read 4, iclass 12, count 0 2006.286.01:43:38.39#ibcon#read 4, iclass 12, count 0 2006.286.01:43:38.39#ibcon#about to read 5, iclass 12, count 0 2006.286.01:43:38.39#ibcon#read 5, iclass 12, count 0 2006.286.01:43:38.39#ibcon#about to read 6, iclass 12, count 0 2006.286.01:43:38.39#ibcon#read 6, iclass 12, count 0 2006.286.01:43:38.39#ibcon#end of sib2, iclass 12, count 0 2006.286.01:43:38.39#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:43:38.39#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:43:38.39#ibcon#[27=USB\r\n] 2006.286.01:43:38.39#ibcon#*before write, iclass 12, count 0 2006.286.01:43:38.39#ibcon#enter sib2, iclass 12, count 0 2006.286.01:43:38.39#ibcon#flushed, iclass 12, count 0 2006.286.01:43:38.39#ibcon#about to write, iclass 12, count 0 2006.286.01:43:38.39#ibcon#wrote, iclass 12, count 0 2006.286.01:43:38.39#ibcon#about to read 3, iclass 12, count 0 2006.286.01:43:38.42#ibcon#read 3, iclass 12, count 0 2006.286.01:43:38.42#ibcon#about to read 4, iclass 12, count 0 2006.286.01:43:38.42#ibcon#read 4, iclass 12, count 0 2006.286.01:43:38.42#ibcon#about to read 5, iclass 12, count 0 2006.286.01:43:38.42#ibcon#read 5, iclass 12, count 0 2006.286.01:43:38.42#ibcon#about to read 6, iclass 12, count 0 2006.286.01:43:38.42#ibcon#read 6, iclass 12, count 0 2006.286.01:43:38.42#ibcon#end of sib2, iclass 12, count 0 2006.286.01:43:38.42#ibcon#*after write, iclass 12, count 0 2006.286.01:43:38.42#ibcon#*before return 0, iclass 12, count 0 2006.286.01:43:38.42#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:43:38.42#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:43:38.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:43:38.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:43:38.42$vck44/vblo=8,744.99 2006.286.01:43:38.42#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.01:43:38.42#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.01:43:38.42#ibcon#ireg 17 cls_cnt 0 2006.286.01:43:38.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:43:38.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:43:38.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:43:38.42#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:43:38.42#ibcon#first serial, iclass 14, count 0 2006.286.01:43:38.42#ibcon#enter sib2, iclass 14, count 0 2006.286.01:43:38.42#ibcon#flushed, iclass 14, count 0 2006.286.01:43:38.42#ibcon#about to write, iclass 14, count 0 2006.286.01:43:38.42#ibcon#wrote, iclass 14, count 0 2006.286.01:43:38.42#ibcon#about to read 3, iclass 14, count 0 2006.286.01:43:38.44#ibcon#read 3, iclass 14, count 0 2006.286.01:43:38.44#ibcon#about to read 4, iclass 14, count 0 2006.286.01:43:38.44#ibcon#read 4, iclass 14, count 0 2006.286.01:43:38.44#ibcon#about to read 5, iclass 14, count 0 2006.286.01:43:38.44#ibcon#read 5, iclass 14, count 0 2006.286.01:43:38.44#ibcon#about to read 6, iclass 14, count 0 2006.286.01:43:38.44#ibcon#read 6, iclass 14, count 0 2006.286.01:43:38.44#ibcon#end of sib2, iclass 14, count 0 2006.286.01:43:38.44#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:43:38.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:43:38.44#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:43:38.44#ibcon#*before write, iclass 14, count 0 2006.286.01:43:38.44#ibcon#enter sib2, iclass 14, count 0 2006.286.01:43:38.44#ibcon#flushed, iclass 14, count 0 2006.286.01:43:38.44#ibcon#about to write, iclass 14, count 0 2006.286.01:43:38.44#ibcon#wrote, iclass 14, count 0 2006.286.01:43:38.44#ibcon#about to read 3, iclass 14, count 0 2006.286.01:43:38.48#ibcon#read 3, iclass 14, count 0 2006.286.01:43:38.48#ibcon#about to read 4, iclass 14, count 0 2006.286.01:43:38.48#ibcon#read 4, iclass 14, count 0 2006.286.01:43:38.48#ibcon#about to read 5, iclass 14, count 0 2006.286.01:43:38.48#ibcon#read 5, iclass 14, count 0 2006.286.01:43:38.48#ibcon#about to read 6, iclass 14, count 0 2006.286.01:43:38.48#ibcon#read 6, iclass 14, count 0 2006.286.01:43:38.48#ibcon#end of sib2, iclass 14, count 0 2006.286.01:43:38.48#ibcon#*after write, iclass 14, count 0 2006.286.01:43:38.48#ibcon#*before return 0, iclass 14, count 0 2006.286.01:43:38.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:43:38.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:43:38.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:43:38.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:43:38.48$vck44/vb=8,4 2006.286.01:43:38.48#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.01:43:38.48#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.01:43:38.48#ibcon#ireg 11 cls_cnt 2 2006.286.01:43:38.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:43:38.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:43:38.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:43:38.54#ibcon#enter wrdev, iclass 16, count 2 2006.286.01:43:38.54#ibcon#first serial, iclass 16, count 2 2006.286.01:43:38.54#ibcon#enter sib2, iclass 16, count 2 2006.286.01:43:38.54#ibcon#flushed, iclass 16, count 2 2006.286.01:43:38.54#ibcon#about to write, iclass 16, count 2 2006.286.01:43:38.54#ibcon#wrote, iclass 16, count 2 2006.286.01:43:38.54#ibcon#about to read 3, iclass 16, count 2 2006.286.01:43:38.56#ibcon#read 3, iclass 16, count 2 2006.286.01:43:38.56#ibcon#about to read 4, iclass 16, count 2 2006.286.01:43:38.56#ibcon#read 4, iclass 16, count 2 2006.286.01:43:38.56#ibcon#about to read 5, iclass 16, count 2 2006.286.01:43:38.56#ibcon#read 5, iclass 16, count 2 2006.286.01:43:38.56#ibcon#about to read 6, iclass 16, count 2 2006.286.01:43:38.56#ibcon#read 6, iclass 16, count 2 2006.286.01:43:38.56#ibcon#end of sib2, iclass 16, count 2 2006.286.01:43:38.56#ibcon#*mode == 0, iclass 16, count 2 2006.286.01:43:38.56#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.01:43:38.56#ibcon#[27=AT08-04\r\n] 2006.286.01:43:38.56#ibcon#*before write, iclass 16, count 2 2006.286.01:43:38.56#ibcon#enter sib2, iclass 16, count 2 2006.286.01:43:38.56#ibcon#flushed, iclass 16, count 2 2006.286.01:43:38.56#ibcon#about to write, iclass 16, count 2 2006.286.01:43:38.56#ibcon#wrote, iclass 16, count 2 2006.286.01:43:38.56#ibcon#about to read 3, iclass 16, count 2 2006.286.01:43:38.59#ibcon#read 3, iclass 16, count 2 2006.286.01:43:38.59#ibcon#about to read 4, iclass 16, count 2 2006.286.01:43:38.59#ibcon#read 4, iclass 16, count 2 2006.286.01:43:38.59#ibcon#about to read 5, iclass 16, count 2 2006.286.01:43:38.59#ibcon#read 5, iclass 16, count 2 2006.286.01:43:38.59#ibcon#about to read 6, iclass 16, count 2 2006.286.01:43:38.59#ibcon#read 6, iclass 16, count 2 2006.286.01:43:38.59#ibcon#end of sib2, iclass 16, count 2 2006.286.01:43:38.59#ibcon#*after write, iclass 16, count 2 2006.286.01:43:38.59#ibcon#*before return 0, iclass 16, count 2 2006.286.01:43:38.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:43:38.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:43:38.59#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.01:43:38.59#ibcon#ireg 7 cls_cnt 0 2006.286.01:43:38.59#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:43:38.71#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:43:38.71#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:43:38.71#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:43:38.71#ibcon#first serial, iclass 16, count 0 2006.286.01:43:38.71#ibcon#enter sib2, iclass 16, count 0 2006.286.01:43:38.71#ibcon#flushed, iclass 16, count 0 2006.286.01:43:38.71#ibcon#about to write, iclass 16, count 0 2006.286.01:43:38.71#ibcon#wrote, iclass 16, count 0 2006.286.01:43:38.71#ibcon#about to read 3, iclass 16, count 0 2006.286.01:43:38.73#ibcon#read 3, iclass 16, count 0 2006.286.01:43:38.73#ibcon#about to read 4, iclass 16, count 0 2006.286.01:43:38.73#ibcon#read 4, iclass 16, count 0 2006.286.01:43:38.73#ibcon#about to read 5, iclass 16, count 0 2006.286.01:43:38.73#ibcon#read 5, iclass 16, count 0 2006.286.01:43:38.73#ibcon#about to read 6, iclass 16, count 0 2006.286.01:43:38.73#ibcon#read 6, iclass 16, count 0 2006.286.01:43:38.73#ibcon#end of sib2, iclass 16, count 0 2006.286.01:43:38.73#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:43:38.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:43:38.73#ibcon#[27=USB\r\n] 2006.286.01:43:38.73#ibcon#*before write, iclass 16, count 0 2006.286.01:43:38.73#ibcon#enter sib2, iclass 16, count 0 2006.286.01:43:38.73#ibcon#flushed, iclass 16, count 0 2006.286.01:43:38.73#ibcon#about to write, iclass 16, count 0 2006.286.01:43:38.73#ibcon#wrote, iclass 16, count 0 2006.286.01:43:38.73#ibcon#about to read 3, iclass 16, count 0 2006.286.01:43:38.76#ibcon#read 3, iclass 16, count 0 2006.286.01:43:38.76#ibcon#about to read 4, iclass 16, count 0 2006.286.01:43:38.76#ibcon#read 4, iclass 16, count 0 2006.286.01:43:38.76#ibcon#about to read 5, iclass 16, count 0 2006.286.01:43:38.76#ibcon#read 5, iclass 16, count 0 2006.286.01:43:38.76#ibcon#about to read 6, iclass 16, count 0 2006.286.01:43:38.76#ibcon#read 6, iclass 16, count 0 2006.286.01:43:38.76#ibcon#end of sib2, iclass 16, count 0 2006.286.01:43:38.76#ibcon#*after write, iclass 16, count 0 2006.286.01:43:38.76#ibcon#*before return 0, iclass 16, count 0 2006.286.01:43:38.76#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:43:38.76#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:43:38.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:43:38.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:43:38.76$vck44/vabw=wide 2006.286.01:43:38.76#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.01:43:38.76#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.01:43:38.76#ibcon#ireg 8 cls_cnt 0 2006.286.01:43:38.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:43:38.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:43:38.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:43:38.76#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:43:38.76#ibcon#first serial, iclass 18, count 0 2006.286.01:43:38.76#ibcon#enter sib2, iclass 18, count 0 2006.286.01:43:38.76#ibcon#flushed, iclass 18, count 0 2006.286.01:43:38.76#ibcon#about to write, iclass 18, count 0 2006.286.01:43:38.76#ibcon#wrote, iclass 18, count 0 2006.286.01:43:38.76#ibcon#about to read 3, iclass 18, count 0 2006.286.01:43:38.78#ibcon#read 3, iclass 18, count 0 2006.286.01:43:38.78#ibcon#about to read 4, iclass 18, count 0 2006.286.01:43:38.78#ibcon#read 4, iclass 18, count 0 2006.286.01:43:38.78#ibcon#about to read 5, iclass 18, count 0 2006.286.01:43:38.78#ibcon#read 5, iclass 18, count 0 2006.286.01:43:38.78#ibcon#about to read 6, iclass 18, count 0 2006.286.01:43:38.78#ibcon#read 6, iclass 18, count 0 2006.286.01:43:38.78#ibcon#end of sib2, iclass 18, count 0 2006.286.01:43:38.78#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:43:38.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:43:38.78#ibcon#[25=BW32\r\n] 2006.286.01:43:38.78#ibcon#*before write, iclass 18, count 0 2006.286.01:43:38.78#ibcon#enter sib2, iclass 18, count 0 2006.286.01:43:38.78#ibcon#flushed, iclass 18, count 0 2006.286.01:43:38.78#ibcon#about to write, iclass 18, count 0 2006.286.01:43:38.78#ibcon#wrote, iclass 18, count 0 2006.286.01:43:38.78#ibcon#about to read 3, iclass 18, count 0 2006.286.01:43:38.81#ibcon#read 3, iclass 18, count 0 2006.286.01:43:38.81#ibcon#about to read 4, iclass 18, count 0 2006.286.01:43:38.81#ibcon#read 4, iclass 18, count 0 2006.286.01:43:38.81#ibcon#about to read 5, iclass 18, count 0 2006.286.01:43:38.81#ibcon#read 5, iclass 18, count 0 2006.286.01:43:38.81#ibcon#about to read 6, iclass 18, count 0 2006.286.01:43:38.81#ibcon#read 6, iclass 18, count 0 2006.286.01:43:38.81#ibcon#end of sib2, iclass 18, count 0 2006.286.01:43:38.81#ibcon#*after write, iclass 18, count 0 2006.286.01:43:38.81#ibcon#*before return 0, iclass 18, count 0 2006.286.01:43:38.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:43:38.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:43:38.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:43:38.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:43:38.81$vck44/vbbw=wide 2006.286.01:43:38.81#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.01:43:38.81#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.01:43:38.81#ibcon#ireg 8 cls_cnt 0 2006.286.01:43:38.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:43:38.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:43:38.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:43:38.88#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:43:38.88#ibcon#first serial, iclass 20, count 0 2006.286.01:43:38.88#ibcon#enter sib2, iclass 20, count 0 2006.286.01:43:38.88#ibcon#flushed, iclass 20, count 0 2006.286.01:43:38.88#ibcon#about to write, iclass 20, count 0 2006.286.01:43:38.88#ibcon#wrote, iclass 20, count 0 2006.286.01:43:38.88#ibcon#about to read 3, iclass 20, count 0 2006.286.01:43:38.90#ibcon#read 3, iclass 20, count 0 2006.286.01:43:38.90#ibcon#about to read 4, iclass 20, count 0 2006.286.01:43:38.90#ibcon#read 4, iclass 20, count 0 2006.286.01:43:38.90#ibcon#about to read 5, iclass 20, count 0 2006.286.01:43:38.90#ibcon#read 5, iclass 20, count 0 2006.286.01:43:38.90#ibcon#about to read 6, iclass 20, count 0 2006.286.01:43:38.90#ibcon#read 6, iclass 20, count 0 2006.286.01:43:38.90#ibcon#end of sib2, iclass 20, count 0 2006.286.01:43:38.90#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:43:38.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:43:38.90#ibcon#[27=BW32\r\n] 2006.286.01:43:38.90#ibcon#*before write, iclass 20, count 0 2006.286.01:43:38.90#ibcon#enter sib2, iclass 20, count 0 2006.286.01:43:38.90#ibcon#flushed, iclass 20, count 0 2006.286.01:43:38.90#ibcon#about to write, iclass 20, count 0 2006.286.01:43:38.90#ibcon#wrote, iclass 20, count 0 2006.286.01:43:38.90#ibcon#about to read 3, iclass 20, count 0 2006.286.01:43:38.93#ibcon#read 3, iclass 20, count 0 2006.286.01:43:38.93#ibcon#about to read 4, iclass 20, count 0 2006.286.01:43:38.93#ibcon#read 4, iclass 20, count 0 2006.286.01:43:38.93#ibcon#about to read 5, iclass 20, count 0 2006.286.01:43:38.93#ibcon#read 5, iclass 20, count 0 2006.286.01:43:38.93#ibcon#about to read 6, iclass 20, count 0 2006.286.01:43:38.93#ibcon#read 6, iclass 20, count 0 2006.286.01:43:38.93#ibcon#end of sib2, iclass 20, count 0 2006.286.01:43:38.93#ibcon#*after write, iclass 20, count 0 2006.286.01:43:38.93#ibcon#*before return 0, iclass 20, count 0 2006.286.01:43:38.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:43:38.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.01:43:38.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:43:38.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:43:38.93$setupk4/ifdk4 2006.286.01:43:38.93$ifdk4/lo= 2006.286.01:43:38.93$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:43:38.93$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:43:38.93$ifdk4/patch= 2006.286.01:43:38.93$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:43:38.93$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:43:38.93$setupk4/!*+20s 2006.286.01:43:41.45#abcon#<5=/03 3.6 6.8 21.20 781016.1\r\n> 2006.286.01:43:41.47#abcon#{5=INTERFACE CLEAR} 2006.286.01:43:41.53#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:43:51.62#abcon#<5=/03 3.6 7.1 21.20 781016.1\r\n> 2006.286.01:43:51.64#abcon#{5=INTERFACE CLEAR} 2006.286.01:43:51.70#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:43:53.44$setupk4/"tpicd 2006.286.01:43:53.44$setupk4/echo=off 2006.286.01:43:53.44$setupk4/xlog=off 2006.286.01:43:53.44:!2006.286.01:44:13 2006.286.01:43:55.14#trakl#Source acquired 2006.286.01:43:57.14#flagr#flagr/antenna,acquired 2006.286.01:44:13.00:preob 2006.286.01:44:13.14/onsource/TRACKING 2006.286.01:44:13.14:!2006.286.01:44:23 2006.286.01:44:23.00:"tape 2006.286.01:44:23.00:"st=record 2006.286.01:44:23.00:data_valid=on 2006.286.01:44:23.00:midob 2006.286.01:44:24.14/onsource/TRACKING 2006.286.01:44:24.14/wx/21.20,1016.1,78 2006.286.01:44:24.30/cable/+6.5009E-03 2006.286.01:44:25.39/va/01,07,usb,yes,32,35 2006.286.01:44:25.39/va/02,06,usb,yes,32,33 2006.286.01:44:25.39/va/03,07,usb,yes,32,34 2006.286.01:44:25.39/va/04,06,usb,yes,33,35 2006.286.01:44:25.39/va/05,03,usb,yes,33,33 2006.286.01:44:25.39/va/06,04,usb,yes,30,29 2006.286.01:44:25.39/va/07,04,usb,yes,30,31 2006.286.01:44:25.39/va/08,03,usb,yes,31,37 2006.286.01:44:25.62/valo/01,524.99,yes,locked 2006.286.01:44:25.62/valo/02,534.99,yes,locked 2006.286.01:44:25.62/valo/03,564.99,yes,locked 2006.286.01:44:25.62/valo/04,624.99,yes,locked 2006.286.01:44:25.62/valo/05,734.99,yes,locked 2006.286.01:44:25.62/valo/06,814.99,yes,locked 2006.286.01:44:25.62/valo/07,864.99,yes,locked 2006.286.01:44:25.62/valo/08,884.99,yes,locked 2006.286.01:44:26.71/vb/01,04,usb,yes,31,29 2006.286.01:44:26.71/vb/02,05,usb,yes,29,29 2006.286.01:44:26.71/vb/03,04,usb,yes,30,33 2006.286.01:44:26.71/vb/04,05,usb,yes,30,29 2006.286.01:44:26.71/vb/05,04,usb,yes,27,29 2006.286.01:44:26.71/vb/06,03,usb,yes,38,34 2006.286.01:44:26.71/vb/07,04,usb,yes,31,31 2006.286.01:44:26.71/vb/08,04,usb,yes,28,32 2006.286.01:44:26.95/vblo/01,629.99,yes,locked 2006.286.01:44:26.95/vblo/02,634.99,yes,locked 2006.286.01:44:26.95/vblo/03,649.99,yes,locked 2006.286.01:44:26.95/vblo/04,679.99,yes,locked 2006.286.01:44:26.95/vblo/05,709.99,yes,locked 2006.286.01:44:26.95/vblo/06,719.99,yes,locked 2006.286.01:44:26.95/vblo/07,734.99,yes,locked 2006.286.01:44:26.95/vblo/08,744.99,yes,locked 2006.286.01:44:27.10/vabw/8 2006.286.01:44:27.25/vbbw/8 2006.286.01:44:27.34/xfe/off,on,12.0 2006.286.01:44:27.71/ifatt/23,28,28,28 2006.286.01:44:28.07/fmout-gps/S +2.71E-07 2006.286.01:44:28.09:!2006.286.01:45:03 2006.286.01:45:03.00:data_valid=off 2006.286.01:45:03.00:"et 2006.286.01:45:03.00:!+3s 2006.286.01:45:06.01:"tape 2006.286.01:45:06.01:postob 2006.286.01:45:06.19/cable/+6.5015E-03 2006.286.01:45:06.19/wx/21.21,1016.1,79 2006.286.01:45:07.07/fmout-gps/S +2.72E-07 2006.286.01:45:07.07:scan_name=286-0150,jd0610,200 2006.286.01:45:07.07:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.286.01:45:08.14#flagr#flagr/antenna,new-source 2006.286.01:45:08.14:checkk5 2006.286.01:45:08.57/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:45:08.99/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:45:09.40/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:45:09.80/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:45:10.16/chk_obsdata//k5ts1/T2860144??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.01:45:10.64/chk_obsdata//k5ts2/T2860144??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.01:45:11.03/chk_obsdata//k5ts3/T2860144??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.01:45:11.40/chk_obsdata//k5ts4/T2860144??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.01:45:12.22/k5log//k5ts1_log_newline 2006.286.01:45:13.01/k5log//k5ts2_log_newline 2006.286.01:45:13.84/k5log//k5ts3_log_newline 2006.286.01:45:14.62/k5log//k5ts4_log_newline 2006.286.01:45:14.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:45:14.64:setupk4=1 2006.286.01:45:14.64$setupk4/echo=on 2006.286.01:45:14.64$setupk4/pcalon 2006.286.01:45:14.64$pcalon/"no phase cal control is implemented here 2006.286.01:45:14.64$setupk4/"tpicd=stop 2006.286.01:45:14.64$setupk4/"rec=synch_on 2006.286.01:45:14.64$setupk4/"rec_mode=128 2006.286.01:45:14.64$setupk4/!* 2006.286.01:45:14.64$setupk4/recpk4 2006.286.01:45:14.64$recpk4/recpatch= 2006.286.01:45:14.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:45:14.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:45:14.65$setupk4/vck44 2006.286.01:45:14.65$vck44/valo=1,524.99 2006.286.01:45:14.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.01:45:14.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.01:45:14.65#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:14.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:45:14.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:45:14.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:45:14.65#ibcon#enter wrdev, iclass 29, count 0 2006.286.01:45:14.65#ibcon#first serial, iclass 29, count 0 2006.286.01:45:14.65#ibcon#enter sib2, iclass 29, count 0 2006.286.01:45:14.65#ibcon#flushed, iclass 29, count 0 2006.286.01:45:14.65#ibcon#about to write, iclass 29, count 0 2006.286.01:45:14.65#ibcon#wrote, iclass 29, count 0 2006.286.01:45:14.65#ibcon#about to read 3, iclass 29, count 0 2006.286.01:45:14.66#ibcon#read 3, iclass 29, count 0 2006.286.01:45:14.66#ibcon#about to read 4, iclass 29, count 0 2006.286.01:45:14.66#ibcon#read 4, iclass 29, count 0 2006.286.01:45:14.66#ibcon#about to read 5, iclass 29, count 0 2006.286.01:45:14.66#ibcon#read 5, iclass 29, count 0 2006.286.01:45:14.66#ibcon#about to read 6, iclass 29, count 0 2006.286.01:45:14.66#ibcon#read 6, iclass 29, count 0 2006.286.01:45:14.66#ibcon#end of sib2, iclass 29, count 0 2006.286.01:45:14.66#ibcon#*mode == 0, iclass 29, count 0 2006.286.01:45:14.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.01:45:14.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:45:14.66#ibcon#*before write, iclass 29, count 0 2006.286.01:45:14.66#ibcon#enter sib2, iclass 29, count 0 2006.286.01:45:14.66#ibcon#flushed, iclass 29, count 0 2006.286.01:45:14.66#ibcon#about to write, iclass 29, count 0 2006.286.01:45:14.66#ibcon#wrote, iclass 29, count 0 2006.286.01:45:14.66#ibcon#about to read 3, iclass 29, count 0 2006.286.01:45:14.71#ibcon#read 3, iclass 29, count 0 2006.286.01:45:14.71#ibcon#about to read 4, iclass 29, count 0 2006.286.01:45:14.71#ibcon#read 4, iclass 29, count 0 2006.286.01:45:14.71#ibcon#about to read 5, iclass 29, count 0 2006.286.01:45:14.71#ibcon#read 5, iclass 29, count 0 2006.286.01:45:14.71#ibcon#about to read 6, iclass 29, count 0 2006.286.01:45:14.71#ibcon#read 6, iclass 29, count 0 2006.286.01:45:14.71#ibcon#end of sib2, iclass 29, count 0 2006.286.01:45:14.71#ibcon#*after write, iclass 29, count 0 2006.286.01:45:14.71#ibcon#*before return 0, iclass 29, count 0 2006.286.01:45:14.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:45:14.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:45:14.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.01:45:14.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.01:45:14.71$vck44/va=1,7 2006.286.01:45:14.71#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.01:45:14.71#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.01:45:14.71#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:14.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:45:14.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:45:14.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:45:14.71#ibcon#enter wrdev, iclass 31, count 2 2006.286.01:45:14.71#ibcon#first serial, iclass 31, count 2 2006.286.01:45:14.71#ibcon#enter sib2, iclass 31, count 2 2006.286.01:45:14.71#ibcon#flushed, iclass 31, count 2 2006.286.01:45:14.71#ibcon#about to write, iclass 31, count 2 2006.286.01:45:14.71#ibcon#wrote, iclass 31, count 2 2006.286.01:45:14.71#ibcon#about to read 3, iclass 31, count 2 2006.286.01:45:14.73#ibcon#read 3, iclass 31, count 2 2006.286.01:45:14.73#ibcon#about to read 4, iclass 31, count 2 2006.286.01:45:14.73#ibcon#read 4, iclass 31, count 2 2006.286.01:45:14.73#ibcon#about to read 5, iclass 31, count 2 2006.286.01:45:14.73#ibcon#read 5, iclass 31, count 2 2006.286.01:45:14.73#ibcon#about to read 6, iclass 31, count 2 2006.286.01:45:14.73#ibcon#read 6, iclass 31, count 2 2006.286.01:45:14.73#ibcon#end of sib2, iclass 31, count 2 2006.286.01:45:14.73#ibcon#*mode == 0, iclass 31, count 2 2006.286.01:45:14.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.01:45:14.73#ibcon#[25=AT01-07\r\n] 2006.286.01:45:14.73#ibcon#*before write, iclass 31, count 2 2006.286.01:45:14.73#ibcon#enter sib2, iclass 31, count 2 2006.286.01:45:14.73#ibcon#flushed, iclass 31, count 2 2006.286.01:45:14.73#ibcon#about to write, iclass 31, count 2 2006.286.01:45:14.73#ibcon#wrote, iclass 31, count 2 2006.286.01:45:14.73#ibcon#about to read 3, iclass 31, count 2 2006.286.01:45:14.76#ibcon#read 3, iclass 31, count 2 2006.286.01:45:14.76#ibcon#about to read 4, iclass 31, count 2 2006.286.01:45:14.76#ibcon#read 4, iclass 31, count 2 2006.286.01:45:14.76#ibcon#about to read 5, iclass 31, count 2 2006.286.01:45:14.76#ibcon#read 5, iclass 31, count 2 2006.286.01:45:14.76#ibcon#about to read 6, iclass 31, count 2 2006.286.01:45:14.76#ibcon#read 6, iclass 31, count 2 2006.286.01:45:14.76#ibcon#end of sib2, iclass 31, count 2 2006.286.01:45:14.76#ibcon#*after write, iclass 31, count 2 2006.286.01:45:14.76#ibcon#*before return 0, iclass 31, count 2 2006.286.01:45:14.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:45:14.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:45:14.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.01:45:14.76#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:14.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:45:14.88#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:45:14.88#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:45:14.88#ibcon#enter wrdev, iclass 31, count 0 2006.286.01:45:14.88#ibcon#first serial, iclass 31, count 0 2006.286.01:45:14.88#ibcon#enter sib2, iclass 31, count 0 2006.286.01:45:14.88#ibcon#flushed, iclass 31, count 0 2006.286.01:45:14.88#ibcon#about to write, iclass 31, count 0 2006.286.01:45:14.88#ibcon#wrote, iclass 31, count 0 2006.286.01:45:14.88#ibcon#about to read 3, iclass 31, count 0 2006.286.01:45:14.90#ibcon#read 3, iclass 31, count 0 2006.286.01:45:14.90#ibcon#about to read 4, iclass 31, count 0 2006.286.01:45:14.90#ibcon#read 4, iclass 31, count 0 2006.286.01:45:14.90#ibcon#about to read 5, iclass 31, count 0 2006.286.01:45:14.90#ibcon#read 5, iclass 31, count 0 2006.286.01:45:14.90#ibcon#about to read 6, iclass 31, count 0 2006.286.01:45:14.90#ibcon#read 6, iclass 31, count 0 2006.286.01:45:14.90#ibcon#end of sib2, iclass 31, count 0 2006.286.01:45:14.90#ibcon#*mode == 0, iclass 31, count 0 2006.286.01:45:14.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.01:45:14.90#ibcon#[25=USB\r\n] 2006.286.01:45:14.90#ibcon#*before write, iclass 31, count 0 2006.286.01:45:14.90#ibcon#enter sib2, iclass 31, count 0 2006.286.01:45:14.90#ibcon#flushed, iclass 31, count 0 2006.286.01:45:14.90#ibcon#about to write, iclass 31, count 0 2006.286.01:45:14.90#ibcon#wrote, iclass 31, count 0 2006.286.01:45:14.90#ibcon#about to read 3, iclass 31, count 0 2006.286.01:45:14.93#ibcon#read 3, iclass 31, count 0 2006.286.01:45:14.93#ibcon#about to read 4, iclass 31, count 0 2006.286.01:45:14.93#ibcon#read 4, iclass 31, count 0 2006.286.01:45:14.93#ibcon#about to read 5, iclass 31, count 0 2006.286.01:45:14.93#ibcon#read 5, iclass 31, count 0 2006.286.01:45:14.93#ibcon#about to read 6, iclass 31, count 0 2006.286.01:45:14.93#ibcon#read 6, iclass 31, count 0 2006.286.01:45:14.93#ibcon#end of sib2, iclass 31, count 0 2006.286.01:45:14.93#ibcon#*after write, iclass 31, count 0 2006.286.01:45:14.93#ibcon#*before return 0, iclass 31, count 0 2006.286.01:45:14.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:45:14.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:45:14.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.01:45:14.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.01:45:14.93$vck44/valo=2,534.99 2006.286.01:45:14.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.01:45:14.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.01:45:14.93#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:14.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:45:14.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:45:14.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:45:14.93#ibcon#enter wrdev, iclass 33, count 0 2006.286.01:45:14.93#ibcon#first serial, iclass 33, count 0 2006.286.01:45:14.93#ibcon#enter sib2, iclass 33, count 0 2006.286.01:45:14.93#ibcon#flushed, iclass 33, count 0 2006.286.01:45:14.93#ibcon#about to write, iclass 33, count 0 2006.286.01:45:14.93#ibcon#wrote, iclass 33, count 0 2006.286.01:45:14.93#ibcon#about to read 3, iclass 33, count 0 2006.286.01:45:14.95#ibcon#read 3, iclass 33, count 0 2006.286.01:45:14.95#ibcon#about to read 4, iclass 33, count 0 2006.286.01:45:14.95#ibcon#read 4, iclass 33, count 0 2006.286.01:45:14.95#ibcon#about to read 5, iclass 33, count 0 2006.286.01:45:14.95#ibcon#read 5, iclass 33, count 0 2006.286.01:45:14.95#ibcon#about to read 6, iclass 33, count 0 2006.286.01:45:14.95#ibcon#read 6, iclass 33, count 0 2006.286.01:45:14.95#ibcon#end of sib2, iclass 33, count 0 2006.286.01:45:14.95#ibcon#*mode == 0, iclass 33, count 0 2006.286.01:45:14.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.01:45:14.95#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:45:14.95#ibcon#*before write, iclass 33, count 0 2006.286.01:45:14.95#ibcon#enter sib2, iclass 33, count 0 2006.286.01:45:14.95#ibcon#flushed, iclass 33, count 0 2006.286.01:45:14.95#ibcon#about to write, iclass 33, count 0 2006.286.01:45:14.95#ibcon#wrote, iclass 33, count 0 2006.286.01:45:14.95#ibcon#about to read 3, iclass 33, count 0 2006.286.01:45:14.99#ibcon#read 3, iclass 33, count 0 2006.286.01:45:14.99#ibcon#about to read 4, iclass 33, count 0 2006.286.01:45:14.99#ibcon#read 4, iclass 33, count 0 2006.286.01:45:14.99#ibcon#about to read 5, iclass 33, count 0 2006.286.01:45:14.99#ibcon#read 5, iclass 33, count 0 2006.286.01:45:14.99#ibcon#about to read 6, iclass 33, count 0 2006.286.01:45:14.99#ibcon#read 6, iclass 33, count 0 2006.286.01:45:14.99#ibcon#end of sib2, iclass 33, count 0 2006.286.01:45:14.99#ibcon#*after write, iclass 33, count 0 2006.286.01:45:14.99#ibcon#*before return 0, iclass 33, count 0 2006.286.01:45:14.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:45:14.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:45:14.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.01:45:14.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.01:45:14.99$vck44/va=2,6 2006.286.01:45:14.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.01:45:14.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.01:45:14.99#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:14.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:45:15.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:45:15.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:45:15.05#ibcon#enter wrdev, iclass 35, count 2 2006.286.01:45:15.05#ibcon#first serial, iclass 35, count 2 2006.286.01:45:15.05#ibcon#enter sib2, iclass 35, count 2 2006.286.01:45:15.05#ibcon#flushed, iclass 35, count 2 2006.286.01:45:15.05#ibcon#about to write, iclass 35, count 2 2006.286.01:45:15.05#ibcon#wrote, iclass 35, count 2 2006.286.01:45:15.05#ibcon#about to read 3, iclass 35, count 2 2006.286.01:45:15.07#ibcon#read 3, iclass 35, count 2 2006.286.01:45:15.07#ibcon#about to read 4, iclass 35, count 2 2006.286.01:45:15.07#ibcon#read 4, iclass 35, count 2 2006.286.01:45:15.07#ibcon#about to read 5, iclass 35, count 2 2006.286.01:45:15.07#ibcon#read 5, iclass 35, count 2 2006.286.01:45:15.07#ibcon#about to read 6, iclass 35, count 2 2006.286.01:45:15.07#ibcon#read 6, iclass 35, count 2 2006.286.01:45:15.07#ibcon#end of sib2, iclass 35, count 2 2006.286.01:45:15.07#ibcon#*mode == 0, iclass 35, count 2 2006.286.01:45:15.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.01:45:15.07#ibcon#[25=AT02-06\r\n] 2006.286.01:45:15.07#ibcon#*before write, iclass 35, count 2 2006.286.01:45:15.07#ibcon#enter sib2, iclass 35, count 2 2006.286.01:45:15.07#ibcon#flushed, iclass 35, count 2 2006.286.01:45:15.07#ibcon#about to write, iclass 35, count 2 2006.286.01:45:15.07#ibcon#wrote, iclass 35, count 2 2006.286.01:45:15.07#ibcon#about to read 3, iclass 35, count 2 2006.286.01:45:15.10#ibcon#read 3, iclass 35, count 2 2006.286.01:45:15.10#ibcon#about to read 4, iclass 35, count 2 2006.286.01:45:15.10#ibcon#read 4, iclass 35, count 2 2006.286.01:45:15.10#ibcon#about to read 5, iclass 35, count 2 2006.286.01:45:15.10#ibcon#read 5, iclass 35, count 2 2006.286.01:45:15.10#ibcon#about to read 6, iclass 35, count 2 2006.286.01:45:15.10#ibcon#read 6, iclass 35, count 2 2006.286.01:45:15.10#ibcon#end of sib2, iclass 35, count 2 2006.286.01:45:15.10#ibcon#*after write, iclass 35, count 2 2006.286.01:45:15.10#ibcon#*before return 0, iclass 35, count 2 2006.286.01:45:15.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:45:15.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:45:15.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.01:45:15.10#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:15.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:45:15.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:45:15.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:45:15.22#ibcon#enter wrdev, iclass 35, count 0 2006.286.01:45:15.22#ibcon#first serial, iclass 35, count 0 2006.286.01:45:15.22#ibcon#enter sib2, iclass 35, count 0 2006.286.01:45:15.22#ibcon#flushed, iclass 35, count 0 2006.286.01:45:15.22#ibcon#about to write, iclass 35, count 0 2006.286.01:45:15.22#ibcon#wrote, iclass 35, count 0 2006.286.01:45:15.22#ibcon#about to read 3, iclass 35, count 0 2006.286.01:45:15.24#ibcon#read 3, iclass 35, count 0 2006.286.01:45:15.24#ibcon#about to read 4, iclass 35, count 0 2006.286.01:45:15.24#ibcon#read 4, iclass 35, count 0 2006.286.01:45:15.24#ibcon#about to read 5, iclass 35, count 0 2006.286.01:45:15.24#ibcon#read 5, iclass 35, count 0 2006.286.01:45:15.24#ibcon#about to read 6, iclass 35, count 0 2006.286.01:45:15.24#ibcon#read 6, iclass 35, count 0 2006.286.01:45:15.24#ibcon#end of sib2, iclass 35, count 0 2006.286.01:45:15.24#ibcon#*mode == 0, iclass 35, count 0 2006.286.01:45:15.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.01:45:15.24#ibcon#[25=USB\r\n] 2006.286.01:45:15.24#ibcon#*before write, iclass 35, count 0 2006.286.01:45:15.24#ibcon#enter sib2, iclass 35, count 0 2006.286.01:45:15.24#ibcon#flushed, iclass 35, count 0 2006.286.01:45:15.24#ibcon#about to write, iclass 35, count 0 2006.286.01:45:15.24#ibcon#wrote, iclass 35, count 0 2006.286.01:45:15.24#ibcon#about to read 3, iclass 35, count 0 2006.286.01:45:15.27#ibcon#read 3, iclass 35, count 0 2006.286.01:45:15.27#ibcon#about to read 4, iclass 35, count 0 2006.286.01:45:15.27#ibcon#read 4, iclass 35, count 0 2006.286.01:45:15.27#ibcon#about to read 5, iclass 35, count 0 2006.286.01:45:15.27#ibcon#read 5, iclass 35, count 0 2006.286.01:45:15.27#ibcon#about to read 6, iclass 35, count 0 2006.286.01:45:15.27#ibcon#read 6, iclass 35, count 0 2006.286.01:45:15.27#ibcon#end of sib2, iclass 35, count 0 2006.286.01:45:15.27#ibcon#*after write, iclass 35, count 0 2006.286.01:45:15.27#ibcon#*before return 0, iclass 35, count 0 2006.286.01:45:15.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:45:15.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:45:15.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.01:45:15.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.01:45:15.27$vck44/valo=3,564.99 2006.286.01:45:15.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.01:45:15.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.01:45:15.27#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:15.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:45:15.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:45:15.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:45:15.27#ibcon#enter wrdev, iclass 37, count 0 2006.286.01:45:15.27#ibcon#first serial, iclass 37, count 0 2006.286.01:45:15.27#ibcon#enter sib2, iclass 37, count 0 2006.286.01:45:15.27#ibcon#flushed, iclass 37, count 0 2006.286.01:45:15.27#ibcon#about to write, iclass 37, count 0 2006.286.01:45:15.27#ibcon#wrote, iclass 37, count 0 2006.286.01:45:15.27#ibcon#about to read 3, iclass 37, count 0 2006.286.01:45:15.29#ibcon#read 3, iclass 37, count 0 2006.286.01:45:15.29#ibcon#about to read 4, iclass 37, count 0 2006.286.01:45:15.29#ibcon#read 4, iclass 37, count 0 2006.286.01:45:15.29#ibcon#about to read 5, iclass 37, count 0 2006.286.01:45:15.29#ibcon#read 5, iclass 37, count 0 2006.286.01:45:15.29#ibcon#about to read 6, iclass 37, count 0 2006.286.01:45:15.29#ibcon#read 6, iclass 37, count 0 2006.286.01:45:15.29#ibcon#end of sib2, iclass 37, count 0 2006.286.01:45:15.29#ibcon#*mode == 0, iclass 37, count 0 2006.286.01:45:15.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.01:45:15.29#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:45:15.29#ibcon#*before write, iclass 37, count 0 2006.286.01:45:15.29#ibcon#enter sib2, iclass 37, count 0 2006.286.01:45:15.29#ibcon#flushed, iclass 37, count 0 2006.286.01:45:15.29#ibcon#about to write, iclass 37, count 0 2006.286.01:45:15.29#ibcon#wrote, iclass 37, count 0 2006.286.01:45:15.29#ibcon#about to read 3, iclass 37, count 0 2006.286.01:45:15.33#ibcon#read 3, iclass 37, count 0 2006.286.01:45:15.33#ibcon#about to read 4, iclass 37, count 0 2006.286.01:45:15.33#ibcon#read 4, iclass 37, count 0 2006.286.01:45:15.33#ibcon#about to read 5, iclass 37, count 0 2006.286.01:45:15.33#ibcon#read 5, iclass 37, count 0 2006.286.01:45:15.33#ibcon#about to read 6, iclass 37, count 0 2006.286.01:45:15.33#ibcon#read 6, iclass 37, count 0 2006.286.01:45:15.33#ibcon#end of sib2, iclass 37, count 0 2006.286.01:45:15.33#ibcon#*after write, iclass 37, count 0 2006.286.01:45:15.33#ibcon#*before return 0, iclass 37, count 0 2006.286.01:45:15.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:45:15.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:45:15.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.01:45:15.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.01:45:15.33$vck44/va=3,7 2006.286.01:45:15.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.01:45:15.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.01:45:15.33#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:15.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:45:15.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:45:15.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:45:15.39#ibcon#enter wrdev, iclass 39, count 2 2006.286.01:45:15.39#ibcon#first serial, iclass 39, count 2 2006.286.01:45:15.39#ibcon#enter sib2, iclass 39, count 2 2006.286.01:45:15.39#ibcon#flushed, iclass 39, count 2 2006.286.01:45:15.39#ibcon#about to write, iclass 39, count 2 2006.286.01:45:15.39#ibcon#wrote, iclass 39, count 2 2006.286.01:45:15.39#ibcon#about to read 3, iclass 39, count 2 2006.286.01:45:15.41#ibcon#read 3, iclass 39, count 2 2006.286.01:45:15.41#ibcon#about to read 4, iclass 39, count 2 2006.286.01:45:15.41#ibcon#read 4, iclass 39, count 2 2006.286.01:45:15.41#ibcon#about to read 5, iclass 39, count 2 2006.286.01:45:15.41#ibcon#read 5, iclass 39, count 2 2006.286.01:45:15.41#ibcon#about to read 6, iclass 39, count 2 2006.286.01:45:15.41#ibcon#read 6, iclass 39, count 2 2006.286.01:45:15.41#ibcon#end of sib2, iclass 39, count 2 2006.286.01:45:15.41#ibcon#*mode == 0, iclass 39, count 2 2006.286.01:45:15.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.01:45:15.41#ibcon#[25=AT03-07\r\n] 2006.286.01:45:15.41#ibcon#*before write, iclass 39, count 2 2006.286.01:45:15.41#ibcon#enter sib2, iclass 39, count 2 2006.286.01:45:15.41#ibcon#flushed, iclass 39, count 2 2006.286.01:45:15.41#ibcon#about to write, iclass 39, count 2 2006.286.01:45:15.41#ibcon#wrote, iclass 39, count 2 2006.286.01:45:15.41#ibcon#about to read 3, iclass 39, count 2 2006.286.01:45:15.44#ibcon#read 3, iclass 39, count 2 2006.286.01:45:15.44#ibcon#about to read 4, iclass 39, count 2 2006.286.01:45:15.44#ibcon#read 4, iclass 39, count 2 2006.286.01:45:15.44#ibcon#about to read 5, iclass 39, count 2 2006.286.01:45:15.44#ibcon#read 5, iclass 39, count 2 2006.286.01:45:15.44#ibcon#about to read 6, iclass 39, count 2 2006.286.01:45:15.44#ibcon#read 6, iclass 39, count 2 2006.286.01:45:15.44#ibcon#end of sib2, iclass 39, count 2 2006.286.01:45:15.44#ibcon#*after write, iclass 39, count 2 2006.286.01:45:15.44#ibcon#*before return 0, iclass 39, count 2 2006.286.01:45:15.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:45:15.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:45:15.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.01:45:15.44#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:15.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:45:15.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:45:15.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:45:15.56#ibcon#enter wrdev, iclass 39, count 0 2006.286.01:45:15.56#ibcon#first serial, iclass 39, count 0 2006.286.01:45:15.56#ibcon#enter sib2, iclass 39, count 0 2006.286.01:45:15.56#ibcon#flushed, iclass 39, count 0 2006.286.01:45:15.56#ibcon#about to write, iclass 39, count 0 2006.286.01:45:15.56#ibcon#wrote, iclass 39, count 0 2006.286.01:45:15.56#ibcon#about to read 3, iclass 39, count 0 2006.286.01:45:15.58#ibcon#read 3, iclass 39, count 0 2006.286.01:45:15.58#ibcon#about to read 4, iclass 39, count 0 2006.286.01:45:15.58#ibcon#read 4, iclass 39, count 0 2006.286.01:45:15.58#ibcon#about to read 5, iclass 39, count 0 2006.286.01:45:15.58#ibcon#read 5, iclass 39, count 0 2006.286.01:45:15.58#ibcon#about to read 6, iclass 39, count 0 2006.286.01:45:15.58#ibcon#read 6, iclass 39, count 0 2006.286.01:45:15.58#ibcon#end of sib2, iclass 39, count 0 2006.286.01:45:15.58#ibcon#*mode == 0, iclass 39, count 0 2006.286.01:45:15.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.01:45:15.58#ibcon#[25=USB\r\n] 2006.286.01:45:15.58#ibcon#*before write, iclass 39, count 0 2006.286.01:45:15.58#ibcon#enter sib2, iclass 39, count 0 2006.286.01:45:15.58#ibcon#flushed, iclass 39, count 0 2006.286.01:45:15.58#ibcon#about to write, iclass 39, count 0 2006.286.01:45:15.58#ibcon#wrote, iclass 39, count 0 2006.286.01:45:15.58#ibcon#about to read 3, iclass 39, count 0 2006.286.01:45:15.61#ibcon#read 3, iclass 39, count 0 2006.286.01:45:15.61#ibcon#about to read 4, iclass 39, count 0 2006.286.01:45:15.61#ibcon#read 4, iclass 39, count 0 2006.286.01:45:15.61#ibcon#about to read 5, iclass 39, count 0 2006.286.01:45:15.61#ibcon#read 5, iclass 39, count 0 2006.286.01:45:15.61#ibcon#about to read 6, iclass 39, count 0 2006.286.01:45:15.61#ibcon#read 6, iclass 39, count 0 2006.286.01:45:15.61#ibcon#end of sib2, iclass 39, count 0 2006.286.01:45:15.61#ibcon#*after write, iclass 39, count 0 2006.286.01:45:15.61#ibcon#*before return 0, iclass 39, count 0 2006.286.01:45:15.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:45:15.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:45:15.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.01:45:15.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.01:45:15.61$vck44/valo=4,624.99 2006.286.01:45:15.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.01:45:15.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.01:45:15.61#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:15.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:45:15.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:45:15.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:45:15.61#ibcon#enter wrdev, iclass 3, count 0 2006.286.01:45:15.61#ibcon#first serial, iclass 3, count 0 2006.286.01:45:15.61#ibcon#enter sib2, iclass 3, count 0 2006.286.01:45:15.61#ibcon#flushed, iclass 3, count 0 2006.286.01:45:15.61#ibcon#about to write, iclass 3, count 0 2006.286.01:45:15.61#ibcon#wrote, iclass 3, count 0 2006.286.01:45:15.61#ibcon#about to read 3, iclass 3, count 0 2006.286.01:45:15.63#ibcon#read 3, iclass 3, count 0 2006.286.01:45:15.63#ibcon#about to read 4, iclass 3, count 0 2006.286.01:45:15.63#ibcon#read 4, iclass 3, count 0 2006.286.01:45:15.63#ibcon#about to read 5, iclass 3, count 0 2006.286.01:45:15.63#ibcon#read 5, iclass 3, count 0 2006.286.01:45:15.63#ibcon#about to read 6, iclass 3, count 0 2006.286.01:45:15.63#ibcon#read 6, iclass 3, count 0 2006.286.01:45:15.63#ibcon#end of sib2, iclass 3, count 0 2006.286.01:45:15.63#ibcon#*mode == 0, iclass 3, count 0 2006.286.01:45:15.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.01:45:15.63#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:45:15.63#ibcon#*before write, iclass 3, count 0 2006.286.01:45:15.63#ibcon#enter sib2, iclass 3, count 0 2006.286.01:45:15.63#ibcon#flushed, iclass 3, count 0 2006.286.01:45:15.63#ibcon#about to write, iclass 3, count 0 2006.286.01:45:15.63#ibcon#wrote, iclass 3, count 0 2006.286.01:45:15.63#ibcon#about to read 3, iclass 3, count 0 2006.286.01:45:15.67#ibcon#read 3, iclass 3, count 0 2006.286.01:45:15.67#ibcon#about to read 4, iclass 3, count 0 2006.286.01:45:15.67#ibcon#read 4, iclass 3, count 0 2006.286.01:45:15.67#ibcon#about to read 5, iclass 3, count 0 2006.286.01:45:15.67#ibcon#read 5, iclass 3, count 0 2006.286.01:45:15.67#ibcon#about to read 6, iclass 3, count 0 2006.286.01:45:15.67#ibcon#read 6, iclass 3, count 0 2006.286.01:45:15.67#ibcon#end of sib2, iclass 3, count 0 2006.286.01:45:15.67#ibcon#*after write, iclass 3, count 0 2006.286.01:45:15.67#ibcon#*before return 0, iclass 3, count 0 2006.286.01:45:15.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:45:15.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:45:15.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.01:45:15.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.01:45:15.67$vck44/va=4,6 2006.286.01:45:15.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.01:45:15.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.01:45:15.67#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:15.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:45:15.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:45:15.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:45:15.73#ibcon#enter wrdev, iclass 5, count 2 2006.286.01:45:15.73#ibcon#first serial, iclass 5, count 2 2006.286.01:45:15.73#ibcon#enter sib2, iclass 5, count 2 2006.286.01:45:15.73#ibcon#flushed, iclass 5, count 2 2006.286.01:45:15.73#ibcon#about to write, iclass 5, count 2 2006.286.01:45:15.73#ibcon#wrote, iclass 5, count 2 2006.286.01:45:15.73#ibcon#about to read 3, iclass 5, count 2 2006.286.01:45:15.75#ibcon#read 3, iclass 5, count 2 2006.286.01:45:15.75#ibcon#about to read 4, iclass 5, count 2 2006.286.01:45:15.75#ibcon#read 4, iclass 5, count 2 2006.286.01:45:15.75#ibcon#about to read 5, iclass 5, count 2 2006.286.01:45:15.75#ibcon#read 5, iclass 5, count 2 2006.286.01:45:15.75#ibcon#about to read 6, iclass 5, count 2 2006.286.01:45:15.75#ibcon#read 6, iclass 5, count 2 2006.286.01:45:15.75#ibcon#end of sib2, iclass 5, count 2 2006.286.01:45:15.75#ibcon#*mode == 0, iclass 5, count 2 2006.286.01:45:15.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.01:45:15.75#ibcon#[25=AT04-06\r\n] 2006.286.01:45:15.75#ibcon#*before write, iclass 5, count 2 2006.286.01:45:15.75#ibcon#enter sib2, iclass 5, count 2 2006.286.01:45:15.75#ibcon#flushed, iclass 5, count 2 2006.286.01:45:15.75#ibcon#about to write, iclass 5, count 2 2006.286.01:45:15.75#ibcon#wrote, iclass 5, count 2 2006.286.01:45:15.75#ibcon#about to read 3, iclass 5, count 2 2006.286.01:45:15.78#ibcon#read 3, iclass 5, count 2 2006.286.01:45:15.78#ibcon#about to read 4, iclass 5, count 2 2006.286.01:45:15.78#ibcon#read 4, iclass 5, count 2 2006.286.01:45:15.78#ibcon#about to read 5, iclass 5, count 2 2006.286.01:45:15.78#ibcon#read 5, iclass 5, count 2 2006.286.01:45:15.78#ibcon#about to read 6, iclass 5, count 2 2006.286.01:45:15.78#ibcon#read 6, iclass 5, count 2 2006.286.01:45:15.78#ibcon#end of sib2, iclass 5, count 2 2006.286.01:45:15.78#ibcon#*after write, iclass 5, count 2 2006.286.01:45:15.78#ibcon#*before return 0, iclass 5, count 2 2006.286.01:45:15.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:45:15.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:45:15.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.01:45:15.78#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:15.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:45:15.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:45:15.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:45:15.90#ibcon#enter wrdev, iclass 5, count 0 2006.286.01:45:15.90#ibcon#first serial, iclass 5, count 0 2006.286.01:45:15.90#ibcon#enter sib2, iclass 5, count 0 2006.286.01:45:15.90#ibcon#flushed, iclass 5, count 0 2006.286.01:45:15.90#ibcon#about to write, iclass 5, count 0 2006.286.01:45:15.90#ibcon#wrote, iclass 5, count 0 2006.286.01:45:15.90#ibcon#about to read 3, iclass 5, count 0 2006.286.01:45:15.92#ibcon#read 3, iclass 5, count 0 2006.286.01:45:15.92#ibcon#about to read 4, iclass 5, count 0 2006.286.01:45:15.92#ibcon#read 4, iclass 5, count 0 2006.286.01:45:15.92#ibcon#about to read 5, iclass 5, count 0 2006.286.01:45:15.92#ibcon#read 5, iclass 5, count 0 2006.286.01:45:15.92#ibcon#about to read 6, iclass 5, count 0 2006.286.01:45:15.92#ibcon#read 6, iclass 5, count 0 2006.286.01:45:15.92#ibcon#end of sib2, iclass 5, count 0 2006.286.01:45:15.92#ibcon#*mode == 0, iclass 5, count 0 2006.286.01:45:15.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.01:45:15.92#ibcon#[25=USB\r\n] 2006.286.01:45:15.92#ibcon#*before write, iclass 5, count 0 2006.286.01:45:15.92#ibcon#enter sib2, iclass 5, count 0 2006.286.01:45:15.92#ibcon#flushed, iclass 5, count 0 2006.286.01:45:15.92#ibcon#about to write, iclass 5, count 0 2006.286.01:45:15.92#ibcon#wrote, iclass 5, count 0 2006.286.01:45:15.92#ibcon#about to read 3, iclass 5, count 0 2006.286.01:45:15.95#ibcon#read 3, iclass 5, count 0 2006.286.01:45:15.95#ibcon#about to read 4, iclass 5, count 0 2006.286.01:45:15.95#ibcon#read 4, iclass 5, count 0 2006.286.01:45:15.95#ibcon#about to read 5, iclass 5, count 0 2006.286.01:45:15.95#ibcon#read 5, iclass 5, count 0 2006.286.01:45:15.95#ibcon#about to read 6, iclass 5, count 0 2006.286.01:45:15.95#ibcon#read 6, iclass 5, count 0 2006.286.01:45:15.95#ibcon#end of sib2, iclass 5, count 0 2006.286.01:45:15.95#ibcon#*after write, iclass 5, count 0 2006.286.01:45:15.95#ibcon#*before return 0, iclass 5, count 0 2006.286.01:45:15.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:45:15.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:45:15.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.01:45:15.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.01:45:15.95$vck44/valo=5,734.99 2006.286.01:45:15.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.01:45:15.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.01:45:15.95#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:15.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:45:15.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:45:15.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:45:15.95#ibcon#enter wrdev, iclass 7, count 0 2006.286.01:45:15.95#ibcon#first serial, iclass 7, count 0 2006.286.01:45:15.95#ibcon#enter sib2, iclass 7, count 0 2006.286.01:45:15.95#ibcon#flushed, iclass 7, count 0 2006.286.01:45:15.95#ibcon#about to write, iclass 7, count 0 2006.286.01:45:15.95#ibcon#wrote, iclass 7, count 0 2006.286.01:45:15.95#ibcon#about to read 3, iclass 7, count 0 2006.286.01:45:15.97#ibcon#read 3, iclass 7, count 0 2006.286.01:45:15.97#ibcon#about to read 4, iclass 7, count 0 2006.286.01:45:15.97#ibcon#read 4, iclass 7, count 0 2006.286.01:45:15.97#ibcon#about to read 5, iclass 7, count 0 2006.286.01:45:15.97#ibcon#read 5, iclass 7, count 0 2006.286.01:45:15.97#ibcon#about to read 6, iclass 7, count 0 2006.286.01:45:15.97#ibcon#read 6, iclass 7, count 0 2006.286.01:45:15.97#ibcon#end of sib2, iclass 7, count 0 2006.286.01:45:15.97#ibcon#*mode == 0, iclass 7, count 0 2006.286.01:45:15.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.01:45:15.97#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:45:15.97#ibcon#*before write, iclass 7, count 0 2006.286.01:45:15.97#ibcon#enter sib2, iclass 7, count 0 2006.286.01:45:15.97#ibcon#flushed, iclass 7, count 0 2006.286.01:45:15.97#ibcon#about to write, iclass 7, count 0 2006.286.01:45:15.97#ibcon#wrote, iclass 7, count 0 2006.286.01:45:15.97#ibcon#about to read 3, iclass 7, count 0 2006.286.01:45:16.01#ibcon#read 3, iclass 7, count 0 2006.286.01:45:16.01#ibcon#about to read 4, iclass 7, count 0 2006.286.01:45:16.01#ibcon#read 4, iclass 7, count 0 2006.286.01:45:16.01#ibcon#about to read 5, iclass 7, count 0 2006.286.01:45:16.01#ibcon#read 5, iclass 7, count 0 2006.286.01:45:16.01#ibcon#about to read 6, iclass 7, count 0 2006.286.01:45:16.01#ibcon#read 6, iclass 7, count 0 2006.286.01:45:16.01#ibcon#end of sib2, iclass 7, count 0 2006.286.01:45:16.01#ibcon#*after write, iclass 7, count 0 2006.286.01:45:16.01#ibcon#*before return 0, iclass 7, count 0 2006.286.01:45:16.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:45:16.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:45:16.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.01:45:16.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.01:45:16.01$vck44/va=5,3 2006.286.01:45:16.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.01:45:16.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.01:45:16.01#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:16.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:45:16.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:45:16.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:45:16.07#ibcon#enter wrdev, iclass 11, count 2 2006.286.01:45:16.07#ibcon#first serial, iclass 11, count 2 2006.286.01:45:16.07#ibcon#enter sib2, iclass 11, count 2 2006.286.01:45:16.07#ibcon#flushed, iclass 11, count 2 2006.286.01:45:16.07#ibcon#about to write, iclass 11, count 2 2006.286.01:45:16.07#ibcon#wrote, iclass 11, count 2 2006.286.01:45:16.07#ibcon#about to read 3, iclass 11, count 2 2006.286.01:45:16.09#ibcon#read 3, iclass 11, count 2 2006.286.01:45:16.09#ibcon#about to read 4, iclass 11, count 2 2006.286.01:45:16.09#ibcon#read 4, iclass 11, count 2 2006.286.01:45:16.09#ibcon#about to read 5, iclass 11, count 2 2006.286.01:45:16.09#ibcon#read 5, iclass 11, count 2 2006.286.01:45:16.09#ibcon#about to read 6, iclass 11, count 2 2006.286.01:45:16.09#ibcon#read 6, iclass 11, count 2 2006.286.01:45:16.09#ibcon#end of sib2, iclass 11, count 2 2006.286.01:45:16.09#ibcon#*mode == 0, iclass 11, count 2 2006.286.01:45:16.09#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.01:45:16.09#ibcon#[25=AT05-03\r\n] 2006.286.01:45:16.09#ibcon#*before write, iclass 11, count 2 2006.286.01:45:16.09#ibcon#enter sib2, iclass 11, count 2 2006.286.01:45:16.09#ibcon#flushed, iclass 11, count 2 2006.286.01:45:16.09#ibcon#about to write, iclass 11, count 2 2006.286.01:45:16.09#ibcon#wrote, iclass 11, count 2 2006.286.01:45:16.09#ibcon#about to read 3, iclass 11, count 2 2006.286.01:45:16.12#ibcon#read 3, iclass 11, count 2 2006.286.01:45:16.12#ibcon#about to read 4, iclass 11, count 2 2006.286.01:45:16.12#ibcon#read 4, iclass 11, count 2 2006.286.01:45:16.12#ibcon#about to read 5, iclass 11, count 2 2006.286.01:45:16.12#ibcon#read 5, iclass 11, count 2 2006.286.01:45:16.12#ibcon#about to read 6, iclass 11, count 2 2006.286.01:45:16.12#ibcon#read 6, iclass 11, count 2 2006.286.01:45:16.12#ibcon#end of sib2, iclass 11, count 2 2006.286.01:45:16.12#ibcon#*after write, iclass 11, count 2 2006.286.01:45:16.12#ibcon#*before return 0, iclass 11, count 2 2006.286.01:45:16.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:45:16.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:45:16.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.01:45:16.12#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:16.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:45:16.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:45:16.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:45:16.24#ibcon#enter wrdev, iclass 11, count 0 2006.286.01:45:16.24#ibcon#first serial, iclass 11, count 0 2006.286.01:45:16.24#ibcon#enter sib2, iclass 11, count 0 2006.286.01:45:16.24#ibcon#flushed, iclass 11, count 0 2006.286.01:45:16.24#ibcon#about to write, iclass 11, count 0 2006.286.01:45:16.24#ibcon#wrote, iclass 11, count 0 2006.286.01:45:16.24#ibcon#about to read 3, iclass 11, count 0 2006.286.01:45:16.26#ibcon#read 3, iclass 11, count 0 2006.286.01:45:16.26#ibcon#about to read 4, iclass 11, count 0 2006.286.01:45:16.26#ibcon#read 4, iclass 11, count 0 2006.286.01:45:16.26#ibcon#about to read 5, iclass 11, count 0 2006.286.01:45:16.26#ibcon#read 5, iclass 11, count 0 2006.286.01:45:16.26#ibcon#about to read 6, iclass 11, count 0 2006.286.01:45:16.26#ibcon#read 6, iclass 11, count 0 2006.286.01:45:16.26#ibcon#end of sib2, iclass 11, count 0 2006.286.01:45:16.26#ibcon#*mode == 0, iclass 11, count 0 2006.286.01:45:16.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.01:45:16.26#ibcon#[25=USB\r\n] 2006.286.01:45:16.26#ibcon#*before write, iclass 11, count 0 2006.286.01:45:16.26#ibcon#enter sib2, iclass 11, count 0 2006.286.01:45:16.26#ibcon#flushed, iclass 11, count 0 2006.286.01:45:16.26#ibcon#about to write, iclass 11, count 0 2006.286.01:45:16.26#ibcon#wrote, iclass 11, count 0 2006.286.01:45:16.26#ibcon#about to read 3, iclass 11, count 0 2006.286.01:45:16.29#ibcon#read 3, iclass 11, count 0 2006.286.01:45:16.29#ibcon#about to read 4, iclass 11, count 0 2006.286.01:45:16.29#ibcon#read 4, iclass 11, count 0 2006.286.01:45:16.29#ibcon#about to read 5, iclass 11, count 0 2006.286.01:45:16.29#ibcon#read 5, iclass 11, count 0 2006.286.01:45:16.29#ibcon#about to read 6, iclass 11, count 0 2006.286.01:45:16.29#ibcon#read 6, iclass 11, count 0 2006.286.01:45:16.29#ibcon#end of sib2, iclass 11, count 0 2006.286.01:45:16.29#ibcon#*after write, iclass 11, count 0 2006.286.01:45:16.29#ibcon#*before return 0, iclass 11, count 0 2006.286.01:45:16.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:45:16.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:45:16.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.01:45:16.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.01:45:16.29$vck44/valo=6,814.99 2006.286.01:45:16.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.01:45:16.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.01:45:16.29#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:16.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:45:16.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:45:16.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:45:16.29#ibcon#enter wrdev, iclass 13, count 0 2006.286.01:45:16.29#ibcon#first serial, iclass 13, count 0 2006.286.01:45:16.29#ibcon#enter sib2, iclass 13, count 0 2006.286.01:45:16.29#ibcon#flushed, iclass 13, count 0 2006.286.01:45:16.29#ibcon#about to write, iclass 13, count 0 2006.286.01:45:16.29#ibcon#wrote, iclass 13, count 0 2006.286.01:45:16.29#ibcon#about to read 3, iclass 13, count 0 2006.286.01:45:16.31#ibcon#read 3, iclass 13, count 0 2006.286.01:45:16.31#ibcon#about to read 4, iclass 13, count 0 2006.286.01:45:16.31#ibcon#read 4, iclass 13, count 0 2006.286.01:45:16.31#ibcon#about to read 5, iclass 13, count 0 2006.286.01:45:16.31#ibcon#read 5, iclass 13, count 0 2006.286.01:45:16.31#ibcon#about to read 6, iclass 13, count 0 2006.286.01:45:16.31#ibcon#read 6, iclass 13, count 0 2006.286.01:45:16.31#ibcon#end of sib2, iclass 13, count 0 2006.286.01:45:16.31#ibcon#*mode == 0, iclass 13, count 0 2006.286.01:45:16.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.01:45:16.31#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:45:16.31#ibcon#*before write, iclass 13, count 0 2006.286.01:45:16.31#ibcon#enter sib2, iclass 13, count 0 2006.286.01:45:16.31#ibcon#flushed, iclass 13, count 0 2006.286.01:45:16.31#ibcon#about to write, iclass 13, count 0 2006.286.01:45:16.31#ibcon#wrote, iclass 13, count 0 2006.286.01:45:16.31#ibcon#about to read 3, iclass 13, count 0 2006.286.01:45:16.35#ibcon#read 3, iclass 13, count 0 2006.286.01:45:16.35#ibcon#about to read 4, iclass 13, count 0 2006.286.01:45:16.35#ibcon#read 4, iclass 13, count 0 2006.286.01:45:16.35#ibcon#about to read 5, iclass 13, count 0 2006.286.01:45:16.35#ibcon#read 5, iclass 13, count 0 2006.286.01:45:16.35#ibcon#about to read 6, iclass 13, count 0 2006.286.01:45:16.35#ibcon#read 6, iclass 13, count 0 2006.286.01:45:16.35#ibcon#end of sib2, iclass 13, count 0 2006.286.01:45:16.35#ibcon#*after write, iclass 13, count 0 2006.286.01:45:16.35#ibcon#*before return 0, iclass 13, count 0 2006.286.01:45:16.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:45:16.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:45:16.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.01:45:16.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.01:45:16.35$vck44/va=6,4 2006.286.01:45:16.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.01:45:16.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.01:45:16.35#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:16.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:45:16.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:45:16.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:45:16.41#ibcon#enter wrdev, iclass 15, count 2 2006.286.01:45:16.41#ibcon#first serial, iclass 15, count 2 2006.286.01:45:16.41#ibcon#enter sib2, iclass 15, count 2 2006.286.01:45:16.41#ibcon#flushed, iclass 15, count 2 2006.286.01:45:16.41#ibcon#about to write, iclass 15, count 2 2006.286.01:45:16.41#ibcon#wrote, iclass 15, count 2 2006.286.01:45:16.41#ibcon#about to read 3, iclass 15, count 2 2006.286.01:45:16.43#ibcon#read 3, iclass 15, count 2 2006.286.01:45:16.43#ibcon#about to read 4, iclass 15, count 2 2006.286.01:45:16.43#ibcon#read 4, iclass 15, count 2 2006.286.01:45:16.43#ibcon#about to read 5, iclass 15, count 2 2006.286.01:45:16.43#ibcon#read 5, iclass 15, count 2 2006.286.01:45:16.43#ibcon#about to read 6, iclass 15, count 2 2006.286.01:45:16.43#ibcon#read 6, iclass 15, count 2 2006.286.01:45:16.43#ibcon#end of sib2, iclass 15, count 2 2006.286.01:45:16.43#ibcon#*mode == 0, iclass 15, count 2 2006.286.01:45:16.43#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.01:45:16.43#ibcon#[25=AT06-04\r\n] 2006.286.01:45:16.43#ibcon#*before write, iclass 15, count 2 2006.286.01:45:16.43#ibcon#enter sib2, iclass 15, count 2 2006.286.01:45:16.43#ibcon#flushed, iclass 15, count 2 2006.286.01:45:16.43#ibcon#about to write, iclass 15, count 2 2006.286.01:45:16.43#ibcon#wrote, iclass 15, count 2 2006.286.01:45:16.43#ibcon#about to read 3, iclass 15, count 2 2006.286.01:45:16.46#ibcon#read 3, iclass 15, count 2 2006.286.01:45:16.46#ibcon#about to read 4, iclass 15, count 2 2006.286.01:45:16.46#ibcon#read 4, iclass 15, count 2 2006.286.01:45:16.46#ibcon#about to read 5, iclass 15, count 2 2006.286.01:45:16.46#ibcon#read 5, iclass 15, count 2 2006.286.01:45:16.46#ibcon#about to read 6, iclass 15, count 2 2006.286.01:45:16.46#ibcon#read 6, iclass 15, count 2 2006.286.01:45:16.46#ibcon#end of sib2, iclass 15, count 2 2006.286.01:45:16.46#ibcon#*after write, iclass 15, count 2 2006.286.01:45:16.46#ibcon#*before return 0, iclass 15, count 2 2006.286.01:45:16.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:45:16.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:45:16.46#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.01:45:16.46#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:16.46#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:45:16.58#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:45:16.58#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:45:16.58#ibcon#enter wrdev, iclass 15, count 0 2006.286.01:45:16.58#ibcon#first serial, iclass 15, count 0 2006.286.01:45:16.58#ibcon#enter sib2, iclass 15, count 0 2006.286.01:45:16.58#ibcon#flushed, iclass 15, count 0 2006.286.01:45:16.58#ibcon#about to write, iclass 15, count 0 2006.286.01:45:16.58#ibcon#wrote, iclass 15, count 0 2006.286.01:45:16.58#ibcon#about to read 3, iclass 15, count 0 2006.286.01:45:16.60#ibcon#read 3, iclass 15, count 0 2006.286.01:45:16.60#ibcon#about to read 4, iclass 15, count 0 2006.286.01:45:16.60#ibcon#read 4, iclass 15, count 0 2006.286.01:45:16.60#ibcon#about to read 5, iclass 15, count 0 2006.286.01:45:16.60#ibcon#read 5, iclass 15, count 0 2006.286.01:45:16.60#ibcon#about to read 6, iclass 15, count 0 2006.286.01:45:16.60#ibcon#read 6, iclass 15, count 0 2006.286.01:45:16.60#ibcon#end of sib2, iclass 15, count 0 2006.286.01:45:16.60#ibcon#*mode == 0, iclass 15, count 0 2006.286.01:45:16.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.01:45:16.60#ibcon#[25=USB\r\n] 2006.286.01:45:16.60#ibcon#*before write, iclass 15, count 0 2006.286.01:45:16.60#ibcon#enter sib2, iclass 15, count 0 2006.286.01:45:16.60#ibcon#flushed, iclass 15, count 0 2006.286.01:45:16.60#ibcon#about to write, iclass 15, count 0 2006.286.01:45:16.60#ibcon#wrote, iclass 15, count 0 2006.286.01:45:16.60#ibcon#about to read 3, iclass 15, count 0 2006.286.01:45:16.63#ibcon#read 3, iclass 15, count 0 2006.286.01:45:16.63#ibcon#about to read 4, iclass 15, count 0 2006.286.01:45:16.63#ibcon#read 4, iclass 15, count 0 2006.286.01:45:16.63#ibcon#about to read 5, iclass 15, count 0 2006.286.01:45:16.63#ibcon#read 5, iclass 15, count 0 2006.286.01:45:16.63#ibcon#about to read 6, iclass 15, count 0 2006.286.01:45:16.63#ibcon#read 6, iclass 15, count 0 2006.286.01:45:16.63#ibcon#end of sib2, iclass 15, count 0 2006.286.01:45:16.63#ibcon#*after write, iclass 15, count 0 2006.286.01:45:16.63#ibcon#*before return 0, iclass 15, count 0 2006.286.01:45:16.63#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:45:16.63#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:45:16.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.01:45:16.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.01:45:16.63$vck44/valo=7,864.99 2006.286.01:45:16.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.01:45:16.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.01:45:16.63#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:16.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:45:16.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:45:16.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:45:16.63#ibcon#enter wrdev, iclass 17, count 0 2006.286.01:45:16.63#ibcon#first serial, iclass 17, count 0 2006.286.01:45:16.63#ibcon#enter sib2, iclass 17, count 0 2006.286.01:45:16.63#ibcon#flushed, iclass 17, count 0 2006.286.01:45:16.63#ibcon#about to write, iclass 17, count 0 2006.286.01:45:16.63#ibcon#wrote, iclass 17, count 0 2006.286.01:45:16.63#ibcon#about to read 3, iclass 17, count 0 2006.286.01:45:16.65#ibcon#read 3, iclass 17, count 0 2006.286.01:45:16.65#ibcon#about to read 4, iclass 17, count 0 2006.286.01:45:16.65#ibcon#read 4, iclass 17, count 0 2006.286.01:45:16.65#ibcon#about to read 5, iclass 17, count 0 2006.286.01:45:16.65#ibcon#read 5, iclass 17, count 0 2006.286.01:45:16.65#ibcon#about to read 6, iclass 17, count 0 2006.286.01:45:16.65#ibcon#read 6, iclass 17, count 0 2006.286.01:45:16.65#ibcon#end of sib2, iclass 17, count 0 2006.286.01:45:16.65#ibcon#*mode == 0, iclass 17, count 0 2006.286.01:45:16.65#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.01:45:16.65#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:45:16.65#ibcon#*before write, iclass 17, count 0 2006.286.01:45:16.65#ibcon#enter sib2, iclass 17, count 0 2006.286.01:45:16.65#ibcon#flushed, iclass 17, count 0 2006.286.01:45:16.65#ibcon#about to write, iclass 17, count 0 2006.286.01:45:16.65#ibcon#wrote, iclass 17, count 0 2006.286.01:45:16.65#ibcon#about to read 3, iclass 17, count 0 2006.286.01:45:16.69#ibcon#read 3, iclass 17, count 0 2006.286.01:45:16.69#ibcon#about to read 4, iclass 17, count 0 2006.286.01:45:16.69#ibcon#read 4, iclass 17, count 0 2006.286.01:45:16.69#ibcon#about to read 5, iclass 17, count 0 2006.286.01:45:16.69#ibcon#read 5, iclass 17, count 0 2006.286.01:45:16.69#ibcon#about to read 6, iclass 17, count 0 2006.286.01:45:16.69#ibcon#read 6, iclass 17, count 0 2006.286.01:45:16.69#ibcon#end of sib2, iclass 17, count 0 2006.286.01:45:16.69#ibcon#*after write, iclass 17, count 0 2006.286.01:45:16.69#ibcon#*before return 0, iclass 17, count 0 2006.286.01:45:16.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:45:16.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:45:16.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.01:45:16.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.01:45:16.69$vck44/va=7,4 2006.286.01:45:16.69#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.01:45:16.69#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.01:45:16.69#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:16.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:45:16.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:45:16.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:45:16.75#ibcon#enter wrdev, iclass 19, count 2 2006.286.01:45:16.75#ibcon#first serial, iclass 19, count 2 2006.286.01:45:16.75#ibcon#enter sib2, iclass 19, count 2 2006.286.01:45:16.75#ibcon#flushed, iclass 19, count 2 2006.286.01:45:16.75#ibcon#about to write, iclass 19, count 2 2006.286.01:45:16.75#ibcon#wrote, iclass 19, count 2 2006.286.01:45:16.75#ibcon#about to read 3, iclass 19, count 2 2006.286.01:45:16.77#ibcon#read 3, iclass 19, count 2 2006.286.01:45:16.77#ibcon#about to read 4, iclass 19, count 2 2006.286.01:45:16.77#ibcon#read 4, iclass 19, count 2 2006.286.01:45:16.77#ibcon#about to read 5, iclass 19, count 2 2006.286.01:45:16.77#ibcon#read 5, iclass 19, count 2 2006.286.01:45:16.77#ibcon#about to read 6, iclass 19, count 2 2006.286.01:45:16.77#ibcon#read 6, iclass 19, count 2 2006.286.01:45:16.77#ibcon#end of sib2, iclass 19, count 2 2006.286.01:45:16.77#ibcon#*mode == 0, iclass 19, count 2 2006.286.01:45:16.77#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.01:45:16.77#ibcon#[25=AT07-04\r\n] 2006.286.01:45:16.77#ibcon#*before write, iclass 19, count 2 2006.286.01:45:16.77#ibcon#enter sib2, iclass 19, count 2 2006.286.01:45:16.77#ibcon#flushed, iclass 19, count 2 2006.286.01:45:16.77#ibcon#about to write, iclass 19, count 2 2006.286.01:45:16.77#ibcon#wrote, iclass 19, count 2 2006.286.01:45:16.77#ibcon#about to read 3, iclass 19, count 2 2006.286.01:45:16.80#ibcon#read 3, iclass 19, count 2 2006.286.01:45:16.80#ibcon#about to read 4, iclass 19, count 2 2006.286.01:45:16.80#ibcon#read 4, iclass 19, count 2 2006.286.01:45:16.80#ibcon#about to read 5, iclass 19, count 2 2006.286.01:45:16.80#ibcon#read 5, iclass 19, count 2 2006.286.01:45:16.80#ibcon#about to read 6, iclass 19, count 2 2006.286.01:45:16.80#ibcon#read 6, iclass 19, count 2 2006.286.01:45:16.80#ibcon#end of sib2, iclass 19, count 2 2006.286.01:45:16.80#ibcon#*after write, iclass 19, count 2 2006.286.01:45:16.80#ibcon#*before return 0, iclass 19, count 2 2006.286.01:45:16.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:45:16.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:45:16.80#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.01:45:16.80#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:16.80#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:45:16.92#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:45:16.92#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:45:16.92#ibcon#enter wrdev, iclass 19, count 0 2006.286.01:45:16.92#ibcon#first serial, iclass 19, count 0 2006.286.01:45:16.92#ibcon#enter sib2, iclass 19, count 0 2006.286.01:45:16.92#ibcon#flushed, iclass 19, count 0 2006.286.01:45:16.92#ibcon#about to write, iclass 19, count 0 2006.286.01:45:16.92#ibcon#wrote, iclass 19, count 0 2006.286.01:45:16.92#ibcon#about to read 3, iclass 19, count 0 2006.286.01:45:16.94#ibcon#read 3, iclass 19, count 0 2006.286.01:45:16.94#ibcon#about to read 4, iclass 19, count 0 2006.286.01:45:16.94#ibcon#read 4, iclass 19, count 0 2006.286.01:45:16.94#ibcon#about to read 5, iclass 19, count 0 2006.286.01:45:16.94#ibcon#read 5, iclass 19, count 0 2006.286.01:45:16.94#ibcon#about to read 6, iclass 19, count 0 2006.286.01:45:16.94#ibcon#read 6, iclass 19, count 0 2006.286.01:45:16.94#ibcon#end of sib2, iclass 19, count 0 2006.286.01:45:16.94#ibcon#*mode == 0, iclass 19, count 0 2006.286.01:45:16.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.01:45:16.94#ibcon#[25=USB\r\n] 2006.286.01:45:16.94#ibcon#*before write, iclass 19, count 0 2006.286.01:45:16.94#ibcon#enter sib2, iclass 19, count 0 2006.286.01:45:16.94#ibcon#flushed, iclass 19, count 0 2006.286.01:45:16.94#ibcon#about to write, iclass 19, count 0 2006.286.01:45:16.94#ibcon#wrote, iclass 19, count 0 2006.286.01:45:16.94#ibcon#about to read 3, iclass 19, count 0 2006.286.01:45:16.97#ibcon#read 3, iclass 19, count 0 2006.286.01:45:16.97#ibcon#about to read 4, iclass 19, count 0 2006.286.01:45:16.97#ibcon#read 4, iclass 19, count 0 2006.286.01:45:16.97#ibcon#about to read 5, iclass 19, count 0 2006.286.01:45:16.97#ibcon#read 5, iclass 19, count 0 2006.286.01:45:16.97#ibcon#about to read 6, iclass 19, count 0 2006.286.01:45:16.97#ibcon#read 6, iclass 19, count 0 2006.286.01:45:16.97#ibcon#end of sib2, iclass 19, count 0 2006.286.01:45:16.97#ibcon#*after write, iclass 19, count 0 2006.286.01:45:16.97#ibcon#*before return 0, iclass 19, count 0 2006.286.01:45:16.97#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:45:16.97#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:45:16.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.01:45:16.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.01:45:16.97$vck44/valo=8,884.99 2006.286.01:45:16.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.01:45:16.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.01:45:16.97#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:16.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:45:16.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:45:16.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:45:16.97#ibcon#enter wrdev, iclass 21, count 0 2006.286.01:45:16.97#ibcon#first serial, iclass 21, count 0 2006.286.01:45:16.97#ibcon#enter sib2, iclass 21, count 0 2006.286.01:45:16.97#ibcon#flushed, iclass 21, count 0 2006.286.01:45:16.97#ibcon#about to write, iclass 21, count 0 2006.286.01:45:16.97#ibcon#wrote, iclass 21, count 0 2006.286.01:45:16.97#ibcon#about to read 3, iclass 21, count 0 2006.286.01:45:16.99#ibcon#read 3, iclass 21, count 0 2006.286.01:45:16.99#ibcon#about to read 4, iclass 21, count 0 2006.286.01:45:16.99#ibcon#read 4, iclass 21, count 0 2006.286.01:45:16.99#ibcon#about to read 5, iclass 21, count 0 2006.286.01:45:16.99#ibcon#read 5, iclass 21, count 0 2006.286.01:45:16.99#ibcon#about to read 6, iclass 21, count 0 2006.286.01:45:16.99#ibcon#read 6, iclass 21, count 0 2006.286.01:45:16.99#ibcon#end of sib2, iclass 21, count 0 2006.286.01:45:16.99#ibcon#*mode == 0, iclass 21, count 0 2006.286.01:45:16.99#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.01:45:16.99#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:45:16.99#ibcon#*before write, iclass 21, count 0 2006.286.01:45:16.99#ibcon#enter sib2, iclass 21, count 0 2006.286.01:45:16.99#ibcon#flushed, iclass 21, count 0 2006.286.01:45:16.99#ibcon#about to write, iclass 21, count 0 2006.286.01:45:16.99#ibcon#wrote, iclass 21, count 0 2006.286.01:45:16.99#ibcon#about to read 3, iclass 21, count 0 2006.286.01:45:17.03#ibcon#read 3, iclass 21, count 0 2006.286.01:45:17.03#ibcon#about to read 4, iclass 21, count 0 2006.286.01:45:17.03#ibcon#read 4, iclass 21, count 0 2006.286.01:45:17.03#ibcon#about to read 5, iclass 21, count 0 2006.286.01:45:17.03#ibcon#read 5, iclass 21, count 0 2006.286.01:45:17.03#ibcon#about to read 6, iclass 21, count 0 2006.286.01:45:17.03#ibcon#read 6, iclass 21, count 0 2006.286.01:45:17.03#ibcon#end of sib2, iclass 21, count 0 2006.286.01:45:17.03#ibcon#*after write, iclass 21, count 0 2006.286.01:45:17.03#ibcon#*before return 0, iclass 21, count 0 2006.286.01:45:17.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:45:17.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:45:17.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.01:45:17.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.01:45:17.03$vck44/va=8,3 2006.286.01:45:17.03#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.01:45:17.03#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.01:45:17.03#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:17.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.01:45:17.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.01:45:17.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.01:45:17.09#ibcon#enter wrdev, iclass 23, count 2 2006.286.01:45:17.09#ibcon#first serial, iclass 23, count 2 2006.286.01:45:17.09#ibcon#enter sib2, iclass 23, count 2 2006.286.01:45:17.09#ibcon#flushed, iclass 23, count 2 2006.286.01:45:17.09#ibcon#about to write, iclass 23, count 2 2006.286.01:45:17.09#ibcon#wrote, iclass 23, count 2 2006.286.01:45:17.09#ibcon#about to read 3, iclass 23, count 2 2006.286.01:45:17.11#ibcon#read 3, iclass 23, count 2 2006.286.01:45:17.11#ibcon#about to read 4, iclass 23, count 2 2006.286.01:45:17.11#ibcon#read 4, iclass 23, count 2 2006.286.01:45:17.11#ibcon#about to read 5, iclass 23, count 2 2006.286.01:45:17.11#ibcon#read 5, iclass 23, count 2 2006.286.01:45:17.11#ibcon#about to read 6, iclass 23, count 2 2006.286.01:45:17.11#ibcon#read 6, iclass 23, count 2 2006.286.01:45:17.11#ibcon#end of sib2, iclass 23, count 2 2006.286.01:45:17.11#ibcon#*mode == 0, iclass 23, count 2 2006.286.01:45:17.11#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.01:45:17.11#ibcon#[25=AT08-03\r\n] 2006.286.01:45:17.11#ibcon#*before write, iclass 23, count 2 2006.286.01:45:17.11#ibcon#enter sib2, iclass 23, count 2 2006.286.01:45:17.11#ibcon#flushed, iclass 23, count 2 2006.286.01:45:17.11#ibcon#about to write, iclass 23, count 2 2006.286.01:45:17.11#ibcon#wrote, iclass 23, count 2 2006.286.01:45:17.11#ibcon#about to read 3, iclass 23, count 2 2006.286.01:45:17.14#ibcon#read 3, iclass 23, count 2 2006.286.01:45:17.14#ibcon#about to read 4, iclass 23, count 2 2006.286.01:45:17.14#ibcon#read 4, iclass 23, count 2 2006.286.01:45:17.14#ibcon#about to read 5, iclass 23, count 2 2006.286.01:45:17.14#ibcon#read 5, iclass 23, count 2 2006.286.01:45:17.14#ibcon#about to read 6, iclass 23, count 2 2006.286.01:45:17.14#ibcon#read 6, iclass 23, count 2 2006.286.01:45:17.14#ibcon#end of sib2, iclass 23, count 2 2006.286.01:45:17.14#ibcon#*after write, iclass 23, count 2 2006.286.01:45:17.14#ibcon#*before return 0, iclass 23, count 2 2006.286.01:45:17.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.01:45:17.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.01:45:17.14#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.01:45:17.14#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:17.14#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.01:45:17.26#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.01:45:17.26#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.01:45:17.26#ibcon#enter wrdev, iclass 23, count 0 2006.286.01:45:17.26#ibcon#first serial, iclass 23, count 0 2006.286.01:45:17.26#ibcon#enter sib2, iclass 23, count 0 2006.286.01:45:17.26#ibcon#flushed, iclass 23, count 0 2006.286.01:45:17.26#ibcon#about to write, iclass 23, count 0 2006.286.01:45:17.26#ibcon#wrote, iclass 23, count 0 2006.286.01:45:17.26#ibcon#about to read 3, iclass 23, count 0 2006.286.01:45:17.28#ibcon#read 3, iclass 23, count 0 2006.286.01:45:17.28#ibcon#about to read 4, iclass 23, count 0 2006.286.01:45:17.28#ibcon#read 4, iclass 23, count 0 2006.286.01:45:17.28#ibcon#about to read 5, iclass 23, count 0 2006.286.01:45:17.28#ibcon#read 5, iclass 23, count 0 2006.286.01:45:17.28#ibcon#about to read 6, iclass 23, count 0 2006.286.01:45:17.28#ibcon#read 6, iclass 23, count 0 2006.286.01:45:17.28#ibcon#end of sib2, iclass 23, count 0 2006.286.01:45:17.28#ibcon#*mode == 0, iclass 23, count 0 2006.286.01:45:17.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.01:45:17.28#ibcon#[25=USB\r\n] 2006.286.01:45:17.28#ibcon#*before write, iclass 23, count 0 2006.286.01:45:17.28#ibcon#enter sib2, iclass 23, count 0 2006.286.01:45:17.28#ibcon#flushed, iclass 23, count 0 2006.286.01:45:17.28#ibcon#about to write, iclass 23, count 0 2006.286.01:45:17.28#ibcon#wrote, iclass 23, count 0 2006.286.01:45:17.28#ibcon#about to read 3, iclass 23, count 0 2006.286.01:45:17.31#ibcon#read 3, iclass 23, count 0 2006.286.01:45:17.31#ibcon#about to read 4, iclass 23, count 0 2006.286.01:45:17.31#ibcon#read 4, iclass 23, count 0 2006.286.01:45:17.31#ibcon#about to read 5, iclass 23, count 0 2006.286.01:45:17.31#ibcon#read 5, iclass 23, count 0 2006.286.01:45:17.31#ibcon#about to read 6, iclass 23, count 0 2006.286.01:45:17.31#ibcon#read 6, iclass 23, count 0 2006.286.01:45:17.31#ibcon#end of sib2, iclass 23, count 0 2006.286.01:45:17.31#ibcon#*after write, iclass 23, count 0 2006.286.01:45:17.31#ibcon#*before return 0, iclass 23, count 0 2006.286.01:45:17.31#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.01:45:17.31#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.01:45:17.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.01:45:17.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.01:45:17.31$vck44/vblo=1,629.99 2006.286.01:45:17.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.01:45:17.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.01:45:17.31#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:17.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.01:45:17.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.01:45:17.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.01:45:17.31#ibcon#enter wrdev, iclass 25, count 0 2006.286.01:45:17.31#ibcon#first serial, iclass 25, count 0 2006.286.01:45:17.31#ibcon#enter sib2, iclass 25, count 0 2006.286.01:45:17.31#ibcon#flushed, iclass 25, count 0 2006.286.01:45:17.31#ibcon#about to write, iclass 25, count 0 2006.286.01:45:17.31#ibcon#wrote, iclass 25, count 0 2006.286.01:45:17.31#ibcon#about to read 3, iclass 25, count 0 2006.286.01:45:17.33#ibcon#read 3, iclass 25, count 0 2006.286.01:45:17.33#ibcon#about to read 4, iclass 25, count 0 2006.286.01:45:17.33#ibcon#read 4, iclass 25, count 0 2006.286.01:45:17.33#ibcon#about to read 5, iclass 25, count 0 2006.286.01:45:17.33#ibcon#read 5, iclass 25, count 0 2006.286.01:45:17.33#ibcon#about to read 6, iclass 25, count 0 2006.286.01:45:17.33#ibcon#read 6, iclass 25, count 0 2006.286.01:45:17.33#ibcon#end of sib2, iclass 25, count 0 2006.286.01:45:17.33#ibcon#*mode == 0, iclass 25, count 0 2006.286.01:45:17.33#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.01:45:17.33#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:45:17.33#ibcon#*before write, iclass 25, count 0 2006.286.01:45:17.33#ibcon#enter sib2, iclass 25, count 0 2006.286.01:45:17.33#ibcon#flushed, iclass 25, count 0 2006.286.01:45:17.33#ibcon#about to write, iclass 25, count 0 2006.286.01:45:17.33#ibcon#wrote, iclass 25, count 0 2006.286.01:45:17.33#ibcon#about to read 3, iclass 25, count 0 2006.286.01:45:17.37#ibcon#read 3, iclass 25, count 0 2006.286.01:45:17.37#ibcon#about to read 4, iclass 25, count 0 2006.286.01:45:17.37#ibcon#read 4, iclass 25, count 0 2006.286.01:45:17.37#ibcon#about to read 5, iclass 25, count 0 2006.286.01:45:17.37#ibcon#read 5, iclass 25, count 0 2006.286.01:45:17.37#ibcon#about to read 6, iclass 25, count 0 2006.286.01:45:17.37#ibcon#read 6, iclass 25, count 0 2006.286.01:45:17.37#ibcon#end of sib2, iclass 25, count 0 2006.286.01:45:17.37#ibcon#*after write, iclass 25, count 0 2006.286.01:45:17.37#ibcon#*before return 0, iclass 25, count 0 2006.286.01:45:17.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.01:45:17.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.01:45:17.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.01:45:17.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.01:45:17.37$vck44/vb=1,4 2006.286.01:45:17.37#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.01:45:17.37#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.01:45:17.37#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:17.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.01:45:17.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.01:45:17.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.01:45:17.37#ibcon#enter wrdev, iclass 27, count 2 2006.286.01:45:17.37#ibcon#first serial, iclass 27, count 2 2006.286.01:45:17.37#ibcon#enter sib2, iclass 27, count 2 2006.286.01:45:17.37#ibcon#flushed, iclass 27, count 2 2006.286.01:45:17.37#ibcon#about to write, iclass 27, count 2 2006.286.01:45:17.37#ibcon#wrote, iclass 27, count 2 2006.286.01:45:17.37#ibcon#about to read 3, iclass 27, count 2 2006.286.01:45:17.39#ibcon#read 3, iclass 27, count 2 2006.286.01:45:17.39#ibcon#about to read 4, iclass 27, count 2 2006.286.01:45:17.39#ibcon#read 4, iclass 27, count 2 2006.286.01:45:17.39#ibcon#about to read 5, iclass 27, count 2 2006.286.01:45:17.39#ibcon#read 5, iclass 27, count 2 2006.286.01:45:17.39#ibcon#about to read 6, iclass 27, count 2 2006.286.01:45:17.39#ibcon#read 6, iclass 27, count 2 2006.286.01:45:17.39#ibcon#end of sib2, iclass 27, count 2 2006.286.01:45:17.39#ibcon#*mode == 0, iclass 27, count 2 2006.286.01:45:17.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.01:45:17.39#ibcon#[27=AT01-04\r\n] 2006.286.01:45:17.39#ibcon#*before write, iclass 27, count 2 2006.286.01:45:17.39#ibcon#enter sib2, iclass 27, count 2 2006.286.01:45:17.39#ibcon#flushed, iclass 27, count 2 2006.286.01:45:17.39#ibcon#about to write, iclass 27, count 2 2006.286.01:45:17.39#ibcon#wrote, iclass 27, count 2 2006.286.01:45:17.39#ibcon#about to read 3, iclass 27, count 2 2006.286.01:45:17.42#ibcon#read 3, iclass 27, count 2 2006.286.01:45:17.42#ibcon#about to read 4, iclass 27, count 2 2006.286.01:45:17.42#ibcon#read 4, iclass 27, count 2 2006.286.01:45:17.42#ibcon#about to read 5, iclass 27, count 2 2006.286.01:45:17.42#ibcon#read 5, iclass 27, count 2 2006.286.01:45:17.42#ibcon#about to read 6, iclass 27, count 2 2006.286.01:45:17.42#ibcon#read 6, iclass 27, count 2 2006.286.01:45:17.42#ibcon#end of sib2, iclass 27, count 2 2006.286.01:45:17.42#ibcon#*after write, iclass 27, count 2 2006.286.01:45:17.42#ibcon#*before return 0, iclass 27, count 2 2006.286.01:45:17.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.01:45:17.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.01:45:17.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.01:45:17.42#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:17.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.01:45:17.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.01:45:17.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.01:45:17.54#ibcon#enter wrdev, iclass 27, count 0 2006.286.01:45:17.54#ibcon#first serial, iclass 27, count 0 2006.286.01:45:17.54#ibcon#enter sib2, iclass 27, count 0 2006.286.01:45:17.54#ibcon#flushed, iclass 27, count 0 2006.286.01:45:17.54#ibcon#about to write, iclass 27, count 0 2006.286.01:45:17.54#ibcon#wrote, iclass 27, count 0 2006.286.01:45:17.54#ibcon#about to read 3, iclass 27, count 0 2006.286.01:45:17.56#ibcon#read 3, iclass 27, count 0 2006.286.01:45:17.56#ibcon#about to read 4, iclass 27, count 0 2006.286.01:45:17.56#ibcon#read 4, iclass 27, count 0 2006.286.01:45:17.56#ibcon#about to read 5, iclass 27, count 0 2006.286.01:45:17.56#ibcon#read 5, iclass 27, count 0 2006.286.01:45:17.56#ibcon#about to read 6, iclass 27, count 0 2006.286.01:45:17.56#ibcon#read 6, iclass 27, count 0 2006.286.01:45:17.56#ibcon#end of sib2, iclass 27, count 0 2006.286.01:45:17.56#ibcon#*mode == 0, iclass 27, count 0 2006.286.01:45:17.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.01:45:17.56#ibcon#[27=USB\r\n] 2006.286.01:45:17.56#ibcon#*before write, iclass 27, count 0 2006.286.01:45:17.56#ibcon#enter sib2, iclass 27, count 0 2006.286.01:45:17.56#ibcon#flushed, iclass 27, count 0 2006.286.01:45:17.56#ibcon#about to write, iclass 27, count 0 2006.286.01:45:17.56#ibcon#wrote, iclass 27, count 0 2006.286.01:45:17.56#ibcon#about to read 3, iclass 27, count 0 2006.286.01:45:17.59#ibcon#read 3, iclass 27, count 0 2006.286.01:45:17.59#ibcon#about to read 4, iclass 27, count 0 2006.286.01:45:17.59#ibcon#read 4, iclass 27, count 0 2006.286.01:45:17.59#ibcon#about to read 5, iclass 27, count 0 2006.286.01:45:17.59#ibcon#read 5, iclass 27, count 0 2006.286.01:45:17.59#ibcon#about to read 6, iclass 27, count 0 2006.286.01:45:17.59#ibcon#read 6, iclass 27, count 0 2006.286.01:45:17.59#ibcon#end of sib2, iclass 27, count 0 2006.286.01:45:17.59#ibcon#*after write, iclass 27, count 0 2006.286.01:45:17.59#ibcon#*before return 0, iclass 27, count 0 2006.286.01:45:17.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.01:45:17.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.01:45:17.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.01:45:17.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.01:45:17.59$vck44/vblo=2,634.99 2006.286.01:45:17.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.01:45:17.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.01:45:17.59#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:17.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:45:17.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:45:17.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:45:17.59#ibcon#enter wrdev, iclass 29, count 0 2006.286.01:45:17.59#ibcon#first serial, iclass 29, count 0 2006.286.01:45:17.59#ibcon#enter sib2, iclass 29, count 0 2006.286.01:45:17.59#ibcon#flushed, iclass 29, count 0 2006.286.01:45:17.59#ibcon#about to write, iclass 29, count 0 2006.286.01:45:17.59#ibcon#wrote, iclass 29, count 0 2006.286.01:45:17.59#ibcon#about to read 3, iclass 29, count 0 2006.286.01:45:17.61#ibcon#read 3, iclass 29, count 0 2006.286.01:45:17.61#ibcon#about to read 4, iclass 29, count 0 2006.286.01:45:17.61#ibcon#read 4, iclass 29, count 0 2006.286.01:45:17.61#ibcon#about to read 5, iclass 29, count 0 2006.286.01:45:17.61#ibcon#read 5, iclass 29, count 0 2006.286.01:45:17.61#ibcon#about to read 6, iclass 29, count 0 2006.286.01:45:17.61#ibcon#read 6, iclass 29, count 0 2006.286.01:45:17.61#ibcon#end of sib2, iclass 29, count 0 2006.286.01:45:17.61#ibcon#*mode == 0, iclass 29, count 0 2006.286.01:45:17.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.01:45:17.61#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:45:17.61#ibcon#*before write, iclass 29, count 0 2006.286.01:45:17.61#ibcon#enter sib2, iclass 29, count 0 2006.286.01:45:17.61#ibcon#flushed, iclass 29, count 0 2006.286.01:45:17.61#ibcon#about to write, iclass 29, count 0 2006.286.01:45:17.61#ibcon#wrote, iclass 29, count 0 2006.286.01:45:17.61#ibcon#about to read 3, iclass 29, count 0 2006.286.01:45:17.65#ibcon#read 3, iclass 29, count 0 2006.286.01:45:17.65#ibcon#about to read 4, iclass 29, count 0 2006.286.01:45:17.65#ibcon#read 4, iclass 29, count 0 2006.286.01:45:17.65#ibcon#about to read 5, iclass 29, count 0 2006.286.01:45:17.65#ibcon#read 5, iclass 29, count 0 2006.286.01:45:17.65#ibcon#about to read 6, iclass 29, count 0 2006.286.01:45:17.65#ibcon#read 6, iclass 29, count 0 2006.286.01:45:17.65#ibcon#end of sib2, iclass 29, count 0 2006.286.01:45:17.65#ibcon#*after write, iclass 29, count 0 2006.286.01:45:17.65#ibcon#*before return 0, iclass 29, count 0 2006.286.01:45:17.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:45:17.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.01:45:17.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.01:45:17.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.01:45:17.65$vck44/vb=2,5 2006.286.01:45:17.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.01:45:17.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.01:45:17.65#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:17.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:45:17.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:45:17.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:45:17.71#ibcon#enter wrdev, iclass 31, count 2 2006.286.01:45:17.71#ibcon#first serial, iclass 31, count 2 2006.286.01:45:17.71#ibcon#enter sib2, iclass 31, count 2 2006.286.01:45:17.71#ibcon#flushed, iclass 31, count 2 2006.286.01:45:17.71#ibcon#about to write, iclass 31, count 2 2006.286.01:45:17.71#ibcon#wrote, iclass 31, count 2 2006.286.01:45:17.71#ibcon#about to read 3, iclass 31, count 2 2006.286.01:45:17.73#ibcon#read 3, iclass 31, count 2 2006.286.01:45:17.73#ibcon#about to read 4, iclass 31, count 2 2006.286.01:45:17.73#ibcon#read 4, iclass 31, count 2 2006.286.01:45:17.73#ibcon#about to read 5, iclass 31, count 2 2006.286.01:45:17.73#ibcon#read 5, iclass 31, count 2 2006.286.01:45:17.73#ibcon#about to read 6, iclass 31, count 2 2006.286.01:45:17.73#ibcon#read 6, iclass 31, count 2 2006.286.01:45:17.73#ibcon#end of sib2, iclass 31, count 2 2006.286.01:45:17.73#ibcon#*mode == 0, iclass 31, count 2 2006.286.01:45:17.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.01:45:17.73#ibcon#[27=AT02-05\r\n] 2006.286.01:45:17.73#ibcon#*before write, iclass 31, count 2 2006.286.01:45:17.73#ibcon#enter sib2, iclass 31, count 2 2006.286.01:45:17.73#ibcon#flushed, iclass 31, count 2 2006.286.01:45:17.73#ibcon#about to write, iclass 31, count 2 2006.286.01:45:17.73#ibcon#wrote, iclass 31, count 2 2006.286.01:45:17.73#ibcon#about to read 3, iclass 31, count 2 2006.286.01:45:17.76#ibcon#read 3, iclass 31, count 2 2006.286.01:45:17.76#ibcon#about to read 4, iclass 31, count 2 2006.286.01:45:17.76#ibcon#read 4, iclass 31, count 2 2006.286.01:45:17.76#ibcon#about to read 5, iclass 31, count 2 2006.286.01:45:17.76#ibcon#read 5, iclass 31, count 2 2006.286.01:45:17.76#ibcon#about to read 6, iclass 31, count 2 2006.286.01:45:17.76#ibcon#read 6, iclass 31, count 2 2006.286.01:45:17.76#ibcon#end of sib2, iclass 31, count 2 2006.286.01:45:17.76#ibcon#*after write, iclass 31, count 2 2006.286.01:45:17.76#ibcon#*before return 0, iclass 31, count 2 2006.286.01:45:17.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:45:17.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.01:45:17.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.01:45:17.76#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:17.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:45:17.88#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:45:17.88#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:45:17.88#ibcon#enter wrdev, iclass 31, count 0 2006.286.01:45:17.88#ibcon#first serial, iclass 31, count 0 2006.286.01:45:17.88#ibcon#enter sib2, iclass 31, count 0 2006.286.01:45:17.88#ibcon#flushed, iclass 31, count 0 2006.286.01:45:17.88#ibcon#about to write, iclass 31, count 0 2006.286.01:45:17.88#ibcon#wrote, iclass 31, count 0 2006.286.01:45:17.88#ibcon#about to read 3, iclass 31, count 0 2006.286.01:45:17.90#ibcon#read 3, iclass 31, count 0 2006.286.01:45:17.90#ibcon#about to read 4, iclass 31, count 0 2006.286.01:45:17.90#ibcon#read 4, iclass 31, count 0 2006.286.01:45:17.90#ibcon#about to read 5, iclass 31, count 0 2006.286.01:45:17.90#ibcon#read 5, iclass 31, count 0 2006.286.01:45:17.90#ibcon#about to read 6, iclass 31, count 0 2006.286.01:45:17.90#ibcon#read 6, iclass 31, count 0 2006.286.01:45:17.90#ibcon#end of sib2, iclass 31, count 0 2006.286.01:45:17.90#ibcon#*mode == 0, iclass 31, count 0 2006.286.01:45:17.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.01:45:17.90#ibcon#[27=USB\r\n] 2006.286.01:45:17.90#ibcon#*before write, iclass 31, count 0 2006.286.01:45:17.90#ibcon#enter sib2, iclass 31, count 0 2006.286.01:45:17.90#ibcon#flushed, iclass 31, count 0 2006.286.01:45:17.90#ibcon#about to write, iclass 31, count 0 2006.286.01:45:17.90#ibcon#wrote, iclass 31, count 0 2006.286.01:45:17.90#ibcon#about to read 3, iclass 31, count 0 2006.286.01:45:17.93#ibcon#read 3, iclass 31, count 0 2006.286.01:45:17.93#ibcon#about to read 4, iclass 31, count 0 2006.286.01:45:17.93#ibcon#read 4, iclass 31, count 0 2006.286.01:45:17.93#ibcon#about to read 5, iclass 31, count 0 2006.286.01:45:17.93#ibcon#read 5, iclass 31, count 0 2006.286.01:45:17.93#ibcon#about to read 6, iclass 31, count 0 2006.286.01:45:17.93#ibcon#read 6, iclass 31, count 0 2006.286.01:45:17.93#ibcon#end of sib2, iclass 31, count 0 2006.286.01:45:17.93#ibcon#*after write, iclass 31, count 0 2006.286.01:45:17.93#ibcon#*before return 0, iclass 31, count 0 2006.286.01:45:17.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:45:17.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.01:45:17.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.01:45:17.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.01:45:17.93$vck44/vblo=3,649.99 2006.286.01:45:17.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.01:45:17.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.01:45:17.93#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:17.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:45:17.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:45:17.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:45:17.93#ibcon#enter wrdev, iclass 33, count 0 2006.286.01:45:17.93#ibcon#first serial, iclass 33, count 0 2006.286.01:45:17.93#ibcon#enter sib2, iclass 33, count 0 2006.286.01:45:17.93#ibcon#flushed, iclass 33, count 0 2006.286.01:45:17.93#ibcon#about to write, iclass 33, count 0 2006.286.01:45:17.93#ibcon#wrote, iclass 33, count 0 2006.286.01:45:17.93#ibcon#about to read 3, iclass 33, count 0 2006.286.01:45:17.95#ibcon#read 3, iclass 33, count 0 2006.286.01:45:17.95#ibcon#about to read 4, iclass 33, count 0 2006.286.01:45:17.95#ibcon#read 4, iclass 33, count 0 2006.286.01:45:17.95#ibcon#about to read 5, iclass 33, count 0 2006.286.01:45:17.95#ibcon#read 5, iclass 33, count 0 2006.286.01:45:17.95#ibcon#about to read 6, iclass 33, count 0 2006.286.01:45:17.95#ibcon#read 6, iclass 33, count 0 2006.286.01:45:17.95#ibcon#end of sib2, iclass 33, count 0 2006.286.01:45:17.95#ibcon#*mode == 0, iclass 33, count 0 2006.286.01:45:17.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.01:45:17.95#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:45:17.95#ibcon#*before write, iclass 33, count 0 2006.286.01:45:17.95#ibcon#enter sib2, iclass 33, count 0 2006.286.01:45:17.95#ibcon#flushed, iclass 33, count 0 2006.286.01:45:17.95#ibcon#about to write, iclass 33, count 0 2006.286.01:45:17.95#ibcon#wrote, iclass 33, count 0 2006.286.01:45:17.95#ibcon#about to read 3, iclass 33, count 0 2006.286.01:45:17.99#ibcon#read 3, iclass 33, count 0 2006.286.01:45:17.99#ibcon#about to read 4, iclass 33, count 0 2006.286.01:45:17.99#ibcon#read 4, iclass 33, count 0 2006.286.01:45:17.99#ibcon#about to read 5, iclass 33, count 0 2006.286.01:45:17.99#ibcon#read 5, iclass 33, count 0 2006.286.01:45:17.99#ibcon#about to read 6, iclass 33, count 0 2006.286.01:45:17.99#ibcon#read 6, iclass 33, count 0 2006.286.01:45:17.99#ibcon#end of sib2, iclass 33, count 0 2006.286.01:45:17.99#ibcon#*after write, iclass 33, count 0 2006.286.01:45:17.99#ibcon#*before return 0, iclass 33, count 0 2006.286.01:45:17.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:45:17.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:45:17.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.01:45:17.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.01:45:17.99$vck44/vb=3,4 2006.286.01:45:17.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.01:45:17.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.01:45:17.99#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:17.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:45:18.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:45:18.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:45:18.05#ibcon#enter wrdev, iclass 35, count 2 2006.286.01:45:18.05#ibcon#first serial, iclass 35, count 2 2006.286.01:45:18.05#ibcon#enter sib2, iclass 35, count 2 2006.286.01:45:18.05#ibcon#flushed, iclass 35, count 2 2006.286.01:45:18.05#ibcon#about to write, iclass 35, count 2 2006.286.01:45:18.05#ibcon#wrote, iclass 35, count 2 2006.286.01:45:18.05#ibcon#about to read 3, iclass 35, count 2 2006.286.01:45:18.07#ibcon#read 3, iclass 35, count 2 2006.286.01:45:18.07#ibcon#about to read 4, iclass 35, count 2 2006.286.01:45:18.07#ibcon#read 4, iclass 35, count 2 2006.286.01:45:18.07#ibcon#about to read 5, iclass 35, count 2 2006.286.01:45:18.07#ibcon#read 5, iclass 35, count 2 2006.286.01:45:18.07#ibcon#about to read 6, iclass 35, count 2 2006.286.01:45:18.07#ibcon#read 6, iclass 35, count 2 2006.286.01:45:18.07#ibcon#end of sib2, iclass 35, count 2 2006.286.01:45:18.07#ibcon#*mode == 0, iclass 35, count 2 2006.286.01:45:18.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.01:45:18.07#ibcon#[27=AT03-04\r\n] 2006.286.01:45:18.07#ibcon#*before write, iclass 35, count 2 2006.286.01:45:18.07#ibcon#enter sib2, iclass 35, count 2 2006.286.01:45:18.07#ibcon#flushed, iclass 35, count 2 2006.286.01:45:18.07#ibcon#about to write, iclass 35, count 2 2006.286.01:45:18.07#ibcon#wrote, iclass 35, count 2 2006.286.01:45:18.07#ibcon#about to read 3, iclass 35, count 2 2006.286.01:45:18.10#ibcon#read 3, iclass 35, count 2 2006.286.01:45:18.10#ibcon#about to read 4, iclass 35, count 2 2006.286.01:45:18.10#ibcon#read 4, iclass 35, count 2 2006.286.01:45:18.10#ibcon#about to read 5, iclass 35, count 2 2006.286.01:45:18.10#ibcon#read 5, iclass 35, count 2 2006.286.01:45:18.10#ibcon#about to read 6, iclass 35, count 2 2006.286.01:45:18.10#ibcon#read 6, iclass 35, count 2 2006.286.01:45:18.10#ibcon#end of sib2, iclass 35, count 2 2006.286.01:45:18.10#ibcon#*after write, iclass 35, count 2 2006.286.01:45:18.10#ibcon#*before return 0, iclass 35, count 2 2006.286.01:45:18.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:45:18.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:45:18.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.01:45:18.10#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:18.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:45:18.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:45:18.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:45:18.22#ibcon#enter wrdev, iclass 35, count 0 2006.286.01:45:18.22#ibcon#first serial, iclass 35, count 0 2006.286.01:45:18.22#ibcon#enter sib2, iclass 35, count 0 2006.286.01:45:18.22#ibcon#flushed, iclass 35, count 0 2006.286.01:45:18.22#ibcon#about to write, iclass 35, count 0 2006.286.01:45:18.22#ibcon#wrote, iclass 35, count 0 2006.286.01:45:18.22#ibcon#about to read 3, iclass 35, count 0 2006.286.01:45:18.24#ibcon#read 3, iclass 35, count 0 2006.286.01:45:18.24#ibcon#about to read 4, iclass 35, count 0 2006.286.01:45:18.24#ibcon#read 4, iclass 35, count 0 2006.286.01:45:18.24#ibcon#about to read 5, iclass 35, count 0 2006.286.01:45:18.24#ibcon#read 5, iclass 35, count 0 2006.286.01:45:18.24#ibcon#about to read 6, iclass 35, count 0 2006.286.01:45:18.24#ibcon#read 6, iclass 35, count 0 2006.286.01:45:18.24#ibcon#end of sib2, iclass 35, count 0 2006.286.01:45:18.24#ibcon#*mode == 0, iclass 35, count 0 2006.286.01:45:18.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.01:45:18.24#ibcon#[27=USB\r\n] 2006.286.01:45:18.24#ibcon#*before write, iclass 35, count 0 2006.286.01:45:18.24#ibcon#enter sib2, iclass 35, count 0 2006.286.01:45:18.24#ibcon#flushed, iclass 35, count 0 2006.286.01:45:18.24#ibcon#about to write, iclass 35, count 0 2006.286.01:45:18.24#ibcon#wrote, iclass 35, count 0 2006.286.01:45:18.24#ibcon#about to read 3, iclass 35, count 0 2006.286.01:45:18.27#ibcon#read 3, iclass 35, count 0 2006.286.01:45:18.27#ibcon#about to read 4, iclass 35, count 0 2006.286.01:45:18.27#ibcon#read 4, iclass 35, count 0 2006.286.01:45:18.27#ibcon#about to read 5, iclass 35, count 0 2006.286.01:45:18.27#ibcon#read 5, iclass 35, count 0 2006.286.01:45:18.27#ibcon#about to read 6, iclass 35, count 0 2006.286.01:45:18.27#ibcon#read 6, iclass 35, count 0 2006.286.01:45:18.27#ibcon#end of sib2, iclass 35, count 0 2006.286.01:45:18.27#ibcon#*after write, iclass 35, count 0 2006.286.01:45:18.27#ibcon#*before return 0, iclass 35, count 0 2006.286.01:45:18.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:45:18.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:45:18.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.01:45:18.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.01:45:18.27$vck44/vblo=4,679.99 2006.286.01:45:18.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.01:45:18.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.01:45:18.27#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:18.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:45:18.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:45:18.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:45:18.27#ibcon#enter wrdev, iclass 37, count 0 2006.286.01:45:18.27#ibcon#first serial, iclass 37, count 0 2006.286.01:45:18.27#ibcon#enter sib2, iclass 37, count 0 2006.286.01:45:18.27#ibcon#flushed, iclass 37, count 0 2006.286.01:45:18.27#ibcon#about to write, iclass 37, count 0 2006.286.01:45:18.27#ibcon#wrote, iclass 37, count 0 2006.286.01:45:18.27#ibcon#about to read 3, iclass 37, count 0 2006.286.01:45:18.29#ibcon#read 3, iclass 37, count 0 2006.286.01:45:18.29#ibcon#about to read 4, iclass 37, count 0 2006.286.01:45:18.29#ibcon#read 4, iclass 37, count 0 2006.286.01:45:18.29#ibcon#about to read 5, iclass 37, count 0 2006.286.01:45:18.29#ibcon#read 5, iclass 37, count 0 2006.286.01:45:18.29#ibcon#about to read 6, iclass 37, count 0 2006.286.01:45:18.29#ibcon#read 6, iclass 37, count 0 2006.286.01:45:18.29#ibcon#end of sib2, iclass 37, count 0 2006.286.01:45:18.29#ibcon#*mode == 0, iclass 37, count 0 2006.286.01:45:18.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.01:45:18.29#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:45:18.29#ibcon#*before write, iclass 37, count 0 2006.286.01:45:18.29#ibcon#enter sib2, iclass 37, count 0 2006.286.01:45:18.29#ibcon#flushed, iclass 37, count 0 2006.286.01:45:18.29#ibcon#about to write, iclass 37, count 0 2006.286.01:45:18.29#ibcon#wrote, iclass 37, count 0 2006.286.01:45:18.29#ibcon#about to read 3, iclass 37, count 0 2006.286.01:45:18.33#ibcon#read 3, iclass 37, count 0 2006.286.01:45:18.33#ibcon#about to read 4, iclass 37, count 0 2006.286.01:45:18.33#ibcon#read 4, iclass 37, count 0 2006.286.01:45:18.33#ibcon#about to read 5, iclass 37, count 0 2006.286.01:45:18.33#ibcon#read 5, iclass 37, count 0 2006.286.01:45:18.33#ibcon#about to read 6, iclass 37, count 0 2006.286.01:45:18.33#ibcon#read 6, iclass 37, count 0 2006.286.01:45:18.33#ibcon#end of sib2, iclass 37, count 0 2006.286.01:45:18.33#ibcon#*after write, iclass 37, count 0 2006.286.01:45:18.33#ibcon#*before return 0, iclass 37, count 0 2006.286.01:45:18.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:45:18.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.01:45:18.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.01:45:18.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.01:45:18.33$vck44/vb=4,5 2006.286.01:45:18.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.01:45:18.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.01:45:18.33#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:18.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:45:18.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:45:18.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:45:18.39#ibcon#enter wrdev, iclass 39, count 2 2006.286.01:45:18.39#ibcon#first serial, iclass 39, count 2 2006.286.01:45:18.39#ibcon#enter sib2, iclass 39, count 2 2006.286.01:45:18.39#ibcon#flushed, iclass 39, count 2 2006.286.01:45:18.39#ibcon#about to write, iclass 39, count 2 2006.286.01:45:18.39#ibcon#wrote, iclass 39, count 2 2006.286.01:45:18.39#ibcon#about to read 3, iclass 39, count 2 2006.286.01:45:18.41#ibcon#read 3, iclass 39, count 2 2006.286.01:45:18.41#ibcon#about to read 4, iclass 39, count 2 2006.286.01:45:18.41#ibcon#read 4, iclass 39, count 2 2006.286.01:45:18.41#ibcon#about to read 5, iclass 39, count 2 2006.286.01:45:18.41#ibcon#read 5, iclass 39, count 2 2006.286.01:45:18.41#ibcon#about to read 6, iclass 39, count 2 2006.286.01:45:18.41#ibcon#read 6, iclass 39, count 2 2006.286.01:45:18.41#ibcon#end of sib2, iclass 39, count 2 2006.286.01:45:18.41#ibcon#*mode == 0, iclass 39, count 2 2006.286.01:45:18.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.01:45:18.41#ibcon#[27=AT04-05\r\n] 2006.286.01:45:18.41#ibcon#*before write, iclass 39, count 2 2006.286.01:45:18.41#ibcon#enter sib2, iclass 39, count 2 2006.286.01:45:18.41#ibcon#flushed, iclass 39, count 2 2006.286.01:45:18.41#ibcon#about to write, iclass 39, count 2 2006.286.01:45:18.41#ibcon#wrote, iclass 39, count 2 2006.286.01:45:18.41#ibcon#about to read 3, iclass 39, count 2 2006.286.01:45:18.44#ibcon#read 3, iclass 39, count 2 2006.286.01:45:18.44#ibcon#about to read 4, iclass 39, count 2 2006.286.01:45:18.44#ibcon#read 4, iclass 39, count 2 2006.286.01:45:18.44#ibcon#about to read 5, iclass 39, count 2 2006.286.01:45:18.44#ibcon#read 5, iclass 39, count 2 2006.286.01:45:18.44#ibcon#about to read 6, iclass 39, count 2 2006.286.01:45:18.44#ibcon#read 6, iclass 39, count 2 2006.286.01:45:18.44#ibcon#end of sib2, iclass 39, count 2 2006.286.01:45:18.44#ibcon#*after write, iclass 39, count 2 2006.286.01:45:18.44#ibcon#*before return 0, iclass 39, count 2 2006.286.01:45:18.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:45:18.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.01:45:18.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.01:45:18.44#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:18.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:45:18.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:45:18.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:45:18.56#ibcon#enter wrdev, iclass 39, count 0 2006.286.01:45:18.56#ibcon#first serial, iclass 39, count 0 2006.286.01:45:18.56#ibcon#enter sib2, iclass 39, count 0 2006.286.01:45:18.56#ibcon#flushed, iclass 39, count 0 2006.286.01:45:18.56#ibcon#about to write, iclass 39, count 0 2006.286.01:45:18.56#ibcon#wrote, iclass 39, count 0 2006.286.01:45:18.56#ibcon#about to read 3, iclass 39, count 0 2006.286.01:45:18.58#ibcon#read 3, iclass 39, count 0 2006.286.01:45:18.58#ibcon#about to read 4, iclass 39, count 0 2006.286.01:45:18.58#ibcon#read 4, iclass 39, count 0 2006.286.01:45:18.58#ibcon#about to read 5, iclass 39, count 0 2006.286.01:45:18.58#ibcon#read 5, iclass 39, count 0 2006.286.01:45:18.58#ibcon#about to read 6, iclass 39, count 0 2006.286.01:45:18.58#ibcon#read 6, iclass 39, count 0 2006.286.01:45:18.58#ibcon#end of sib2, iclass 39, count 0 2006.286.01:45:18.58#ibcon#*mode == 0, iclass 39, count 0 2006.286.01:45:18.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.01:45:18.58#ibcon#[27=USB\r\n] 2006.286.01:45:18.58#ibcon#*before write, iclass 39, count 0 2006.286.01:45:18.58#ibcon#enter sib2, iclass 39, count 0 2006.286.01:45:18.58#ibcon#flushed, iclass 39, count 0 2006.286.01:45:18.58#ibcon#about to write, iclass 39, count 0 2006.286.01:45:18.58#ibcon#wrote, iclass 39, count 0 2006.286.01:45:18.58#ibcon#about to read 3, iclass 39, count 0 2006.286.01:45:18.61#ibcon#read 3, iclass 39, count 0 2006.286.01:45:18.61#ibcon#about to read 4, iclass 39, count 0 2006.286.01:45:18.61#ibcon#read 4, iclass 39, count 0 2006.286.01:45:18.61#ibcon#about to read 5, iclass 39, count 0 2006.286.01:45:18.61#ibcon#read 5, iclass 39, count 0 2006.286.01:45:18.61#ibcon#about to read 6, iclass 39, count 0 2006.286.01:45:18.61#ibcon#read 6, iclass 39, count 0 2006.286.01:45:18.61#ibcon#end of sib2, iclass 39, count 0 2006.286.01:45:18.61#ibcon#*after write, iclass 39, count 0 2006.286.01:45:18.61#ibcon#*before return 0, iclass 39, count 0 2006.286.01:45:18.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:45:18.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.01:45:18.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.01:45:18.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.01:45:18.61$vck44/vblo=5,709.99 2006.286.01:45:18.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.01:45:18.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.01:45:18.61#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:18.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:45:18.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:45:18.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:45:18.61#ibcon#enter wrdev, iclass 3, count 0 2006.286.01:45:18.61#ibcon#first serial, iclass 3, count 0 2006.286.01:45:18.61#ibcon#enter sib2, iclass 3, count 0 2006.286.01:45:18.61#ibcon#flushed, iclass 3, count 0 2006.286.01:45:18.61#ibcon#about to write, iclass 3, count 0 2006.286.01:45:18.61#ibcon#wrote, iclass 3, count 0 2006.286.01:45:18.61#ibcon#about to read 3, iclass 3, count 0 2006.286.01:45:18.63#ibcon#read 3, iclass 3, count 0 2006.286.01:45:18.63#ibcon#about to read 4, iclass 3, count 0 2006.286.01:45:18.63#ibcon#read 4, iclass 3, count 0 2006.286.01:45:18.63#ibcon#about to read 5, iclass 3, count 0 2006.286.01:45:18.63#ibcon#read 5, iclass 3, count 0 2006.286.01:45:18.63#ibcon#about to read 6, iclass 3, count 0 2006.286.01:45:18.63#ibcon#read 6, iclass 3, count 0 2006.286.01:45:18.63#ibcon#end of sib2, iclass 3, count 0 2006.286.01:45:18.63#ibcon#*mode == 0, iclass 3, count 0 2006.286.01:45:18.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.01:45:18.63#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:45:18.63#ibcon#*before write, iclass 3, count 0 2006.286.01:45:18.63#ibcon#enter sib2, iclass 3, count 0 2006.286.01:45:18.63#ibcon#flushed, iclass 3, count 0 2006.286.01:45:18.63#ibcon#about to write, iclass 3, count 0 2006.286.01:45:18.63#ibcon#wrote, iclass 3, count 0 2006.286.01:45:18.63#ibcon#about to read 3, iclass 3, count 0 2006.286.01:45:18.67#ibcon#read 3, iclass 3, count 0 2006.286.01:45:18.67#ibcon#about to read 4, iclass 3, count 0 2006.286.01:45:18.67#ibcon#read 4, iclass 3, count 0 2006.286.01:45:18.67#ibcon#about to read 5, iclass 3, count 0 2006.286.01:45:18.67#ibcon#read 5, iclass 3, count 0 2006.286.01:45:18.67#ibcon#about to read 6, iclass 3, count 0 2006.286.01:45:18.67#ibcon#read 6, iclass 3, count 0 2006.286.01:45:18.67#ibcon#end of sib2, iclass 3, count 0 2006.286.01:45:18.67#ibcon#*after write, iclass 3, count 0 2006.286.01:45:18.67#ibcon#*before return 0, iclass 3, count 0 2006.286.01:45:18.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:45:18.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.01:45:18.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.01:45:18.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.01:45:18.67$vck44/vb=5,4 2006.286.01:45:18.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.01:45:18.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.01:45:18.67#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:18.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:45:18.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:45:18.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:45:18.73#ibcon#enter wrdev, iclass 5, count 2 2006.286.01:45:18.73#ibcon#first serial, iclass 5, count 2 2006.286.01:45:18.73#ibcon#enter sib2, iclass 5, count 2 2006.286.01:45:18.73#ibcon#flushed, iclass 5, count 2 2006.286.01:45:18.73#ibcon#about to write, iclass 5, count 2 2006.286.01:45:18.73#ibcon#wrote, iclass 5, count 2 2006.286.01:45:18.73#ibcon#about to read 3, iclass 5, count 2 2006.286.01:45:18.75#ibcon#read 3, iclass 5, count 2 2006.286.01:45:18.75#ibcon#about to read 4, iclass 5, count 2 2006.286.01:45:18.75#ibcon#read 4, iclass 5, count 2 2006.286.01:45:18.75#ibcon#about to read 5, iclass 5, count 2 2006.286.01:45:18.75#ibcon#read 5, iclass 5, count 2 2006.286.01:45:18.75#ibcon#about to read 6, iclass 5, count 2 2006.286.01:45:18.75#ibcon#read 6, iclass 5, count 2 2006.286.01:45:18.75#ibcon#end of sib2, iclass 5, count 2 2006.286.01:45:18.75#ibcon#*mode == 0, iclass 5, count 2 2006.286.01:45:18.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.01:45:18.75#ibcon#[27=AT05-04\r\n] 2006.286.01:45:18.75#ibcon#*before write, iclass 5, count 2 2006.286.01:45:18.75#ibcon#enter sib2, iclass 5, count 2 2006.286.01:45:18.75#ibcon#flushed, iclass 5, count 2 2006.286.01:45:18.75#ibcon#about to write, iclass 5, count 2 2006.286.01:45:18.75#ibcon#wrote, iclass 5, count 2 2006.286.01:45:18.75#ibcon#about to read 3, iclass 5, count 2 2006.286.01:45:18.78#ibcon#read 3, iclass 5, count 2 2006.286.01:45:18.78#ibcon#about to read 4, iclass 5, count 2 2006.286.01:45:18.78#ibcon#read 4, iclass 5, count 2 2006.286.01:45:18.78#ibcon#about to read 5, iclass 5, count 2 2006.286.01:45:18.78#ibcon#read 5, iclass 5, count 2 2006.286.01:45:18.78#ibcon#about to read 6, iclass 5, count 2 2006.286.01:45:18.78#ibcon#read 6, iclass 5, count 2 2006.286.01:45:18.78#ibcon#end of sib2, iclass 5, count 2 2006.286.01:45:18.78#ibcon#*after write, iclass 5, count 2 2006.286.01:45:18.78#ibcon#*before return 0, iclass 5, count 2 2006.286.01:45:18.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:45:18.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.01:45:18.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.01:45:18.78#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:18.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:45:18.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:45:18.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:45:18.90#ibcon#enter wrdev, iclass 5, count 0 2006.286.01:45:18.90#ibcon#first serial, iclass 5, count 0 2006.286.01:45:18.90#ibcon#enter sib2, iclass 5, count 0 2006.286.01:45:18.90#ibcon#flushed, iclass 5, count 0 2006.286.01:45:18.90#ibcon#about to write, iclass 5, count 0 2006.286.01:45:18.90#ibcon#wrote, iclass 5, count 0 2006.286.01:45:18.90#ibcon#about to read 3, iclass 5, count 0 2006.286.01:45:18.92#ibcon#read 3, iclass 5, count 0 2006.286.01:45:18.92#ibcon#about to read 4, iclass 5, count 0 2006.286.01:45:18.92#ibcon#read 4, iclass 5, count 0 2006.286.01:45:18.92#ibcon#about to read 5, iclass 5, count 0 2006.286.01:45:18.92#ibcon#read 5, iclass 5, count 0 2006.286.01:45:18.92#ibcon#about to read 6, iclass 5, count 0 2006.286.01:45:18.92#ibcon#read 6, iclass 5, count 0 2006.286.01:45:18.92#ibcon#end of sib2, iclass 5, count 0 2006.286.01:45:18.92#ibcon#*mode == 0, iclass 5, count 0 2006.286.01:45:18.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.01:45:18.92#ibcon#[27=USB\r\n] 2006.286.01:45:18.92#ibcon#*before write, iclass 5, count 0 2006.286.01:45:18.92#ibcon#enter sib2, iclass 5, count 0 2006.286.01:45:18.92#ibcon#flushed, iclass 5, count 0 2006.286.01:45:18.92#ibcon#about to write, iclass 5, count 0 2006.286.01:45:18.92#ibcon#wrote, iclass 5, count 0 2006.286.01:45:18.92#ibcon#about to read 3, iclass 5, count 0 2006.286.01:45:18.95#ibcon#read 3, iclass 5, count 0 2006.286.01:45:18.95#ibcon#about to read 4, iclass 5, count 0 2006.286.01:45:18.95#ibcon#read 4, iclass 5, count 0 2006.286.01:45:18.95#ibcon#about to read 5, iclass 5, count 0 2006.286.01:45:18.95#ibcon#read 5, iclass 5, count 0 2006.286.01:45:18.95#ibcon#about to read 6, iclass 5, count 0 2006.286.01:45:18.95#ibcon#read 6, iclass 5, count 0 2006.286.01:45:18.95#ibcon#end of sib2, iclass 5, count 0 2006.286.01:45:18.95#ibcon#*after write, iclass 5, count 0 2006.286.01:45:18.95#ibcon#*before return 0, iclass 5, count 0 2006.286.01:45:18.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:45:18.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.01:45:18.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.01:45:18.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.01:45:18.95$vck44/vblo=6,719.99 2006.286.01:45:18.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.01:45:18.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.01:45:18.95#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:18.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:45:18.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:45:18.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:45:18.95#ibcon#enter wrdev, iclass 7, count 0 2006.286.01:45:18.95#ibcon#first serial, iclass 7, count 0 2006.286.01:45:18.95#ibcon#enter sib2, iclass 7, count 0 2006.286.01:45:18.95#ibcon#flushed, iclass 7, count 0 2006.286.01:45:18.95#ibcon#about to write, iclass 7, count 0 2006.286.01:45:18.95#ibcon#wrote, iclass 7, count 0 2006.286.01:45:18.95#ibcon#about to read 3, iclass 7, count 0 2006.286.01:45:18.97#ibcon#read 3, iclass 7, count 0 2006.286.01:45:18.97#ibcon#about to read 4, iclass 7, count 0 2006.286.01:45:18.97#ibcon#read 4, iclass 7, count 0 2006.286.01:45:18.97#ibcon#about to read 5, iclass 7, count 0 2006.286.01:45:18.97#ibcon#read 5, iclass 7, count 0 2006.286.01:45:18.97#ibcon#about to read 6, iclass 7, count 0 2006.286.01:45:18.97#ibcon#read 6, iclass 7, count 0 2006.286.01:45:18.97#ibcon#end of sib2, iclass 7, count 0 2006.286.01:45:18.97#ibcon#*mode == 0, iclass 7, count 0 2006.286.01:45:18.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.01:45:18.97#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:45:18.97#ibcon#*before write, iclass 7, count 0 2006.286.01:45:18.97#ibcon#enter sib2, iclass 7, count 0 2006.286.01:45:18.97#ibcon#flushed, iclass 7, count 0 2006.286.01:45:18.97#ibcon#about to write, iclass 7, count 0 2006.286.01:45:18.97#ibcon#wrote, iclass 7, count 0 2006.286.01:45:18.97#ibcon#about to read 3, iclass 7, count 0 2006.286.01:45:19.01#ibcon#read 3, iclass 7, count 0 2006.286.01:45:19.01#ibcon#about to read 4, iclass 7, count 0 2006.286.01:45:19.01#ibcon#read 4, iclass 7, count 0 2006.286.01:45:19.01#ibcon#about to read 5, iclass 7, count 0 2006.286.01:45:19.01#ibcon#read 5, iclass 7, count 0 2006.286.01:45:19.01#ibcon#about to read 6, iclass 7, count 0 2006.286.01:45:19.01#ibcon#read 6, iclass 7, count 0 2006.286.01:45:19.01#ibcon#end of sib2, iclass 7, count 0 2006.286.01:45:19.01#ibcon#*after write, iclass 7, count 0 2006.286.01:45:19.01#ibcon#*before return 0, iclass 7, count 0 2006.286.01:45:19.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:45:19.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.01:45:19.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.01:45:19.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.01:45:19.01$vck44/vb=6,3 2006.286.01:45:19.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.01:45:19.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.01:45:19.01#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:19.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:45:19.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:45:19.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:45:19.07#ibcon#enter wrdev, iclass 11, count 2 2006.286.01:45:19.07#ibcon#first serial, iclass 11, count 2 2006.286.01:45:19.07#ibcon#enter sib2, iclass 11, count 2 2006.286.01:45:19.07#ibcon#flushed, iclass 11, count 2 2006.286.01:45:19.07#ibcon#about to write, iclass 11, count 2 2006.286.01:45:19.07#ibcon#wrote, iclass 11, count 2 2006.286.01:45:19.07#ibcon#about to read 3, iclass 11, count 2 2006.286.01:45:19.09#ibcon#read 3, iclass 11, count 2 2006.286.01:45:19.09#ibcon#about to read 4, iclass 11, count 2 2006.286.01:45:19.09#ibcon#read 4, iclass 11, count 2 2006.286.01:45:19.09#ibcon#about to read 5, iclass 11, count 2 2006.286.01:45:19.09#ibcon#read 5, iclass 11, count 2 2006.286.01:45:19.09#ibcon#about to read 6, iclass 11, count 2 2006.286.01:45:19.09#ibcon#read 6, iclass 11, count 2 2006.286.01:45:19.09#ibcon#end of sib2, iclass 11, count 2 2006.286.01:45:19.09#ibcon#*mode == 0, iclass 11, count 2 2006.286.01:45:19.09#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.01:45:19.09#ibcon#[27=AT06-03\r\n] 2006.286.01:45:19.09#ibcon#*before write, iclass 11, count 2 2006.286.01:45:19.09#ibcon#enter sib2, iclass 11, count 2 2006.286.01:45:19.09#ibcon#flushed, iclass 11, count 2 2006.286.01:45:19.09#ibcon#about to write, iclass 11, count 2 2006.286.01:45:19.09#ibcon#wrote, iclass 11, count 2 2006.286.01:45:19.09#ibcon#about to read 3, iclass 11, count 2 2006.286.01:45:19.12#ibcon#read 3, iclass 11, count 2 2006.286.01:45:19.12#ibcon#about to read 4, iclass 11, count 2 2006.286.01:45:19.12#ibcon#read 4, iclass 11, count 2 2006.286.01:45:19.12#ibcon#about to read 5, iclass 11, count 2 2006.286.01:45:19.12#ibcon#read 5, iclass 11, count 2 2006.286.01:45:19.12#ibcon#about to read 6, iclass 11, count 2 2006.286.01:45:19.12#ibcon#read 6, iclass 11, count 2 2006.286.01:45:19.12#ibcon#end of sib2, iclass 11, count 2 2006.286.01:45:19.12#ibcon#*after write, iclass 11, count 2 2006.286.01:45:19.12#ibcon#*before return 0, iclass 11, count 2 2006.286.01:45:19.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:45:19.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.01:45:19.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.01:45:19.12#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:19.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:45:19.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:45:19.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:45:19.24#ibcon#enter wrdev, iclass 11, count 0 2006.286.01:45:19.24#ibcon#first serial, iclass 11, count 0 2006.286.01:45:19.24#ibcon#enter sib2, iclass 11, count 0 2006.286.01:45:19.24#ibcon#flushed, iclass 11, count 0 2006.286.01:45:19.24#ibcon#about to write, iclass 11, count 0 2006.286.01:45:19.24#ibcon#wrote, iclass 11, count 0 2006.286.01:45:19.24#ibcon#about to read 3, iclass 11, count 0 2006.286.01:45:19.26#ibcon#read 3, iclass 11, count 0 2006.286.01:45:19.26#ibcon#about to read 4, iclass 11, count 0 2006.286.01:45:19.26#ibcon#read 4, iclass 11, count 0 2006.286.01:45:19.26#ibcon#about to read 5, iclass 11, count 0 2006.286.01:45:19.26#ibcon#read 5, iclass 11, count 0 2006.286.01:45:19.26#ibcon#about to read 6, iclass 11, count 0 2006.286.01:45:19.26#ibcon#read 6, iclass 11, count 0 2006.286.01:45:19.26#ibcon#end of sib2, iclass 11, count 0 2006.286.01:45:19.26#ibcon#*mode == 0, iclass 11, count 0 2006.286.01:45:19.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.01:45:19.26#ibcon#[27=USB\r\n] 2006.286.01:45:19.26#ibcon#*before write, iclass 11, count 0 2006.286.01:45:19.26#ibcon#enter sib2, iclass 11, count 0 2006.286.01:45:19.26#ibcon#flushed, iclass 11, count 0 2006.286.01:45:19.26#ibcon#about to write, iclass 11, count 0 2006.286.01:45:19.26#ibcon#wrote, iclass 11, count 0 2006.286.01:45:19.26#ibcon#about to read 3, iclass 11, count 0 2006.286.01:45:19.29#ibcon#read 3, iclass 11, count 0 2006.286.01:45:19.29#ibcon#about to read 4, iclass 11, count 0 2006.286.01:45:19.29#ibcon#read 4, iclass 11, count 0 2006.286.01:45:19.29#ibcon#about to read 5, iclass 11, count 0 2006.286.01:45:19.29#ibcon#read 5, iclass 11, count 0 2006.286.01:45:19.29#ibcon#about to read 6, iclass 11, count 0 2006.286.01:45:19.29#ibcon#read 6, iclass 11, count 0 2006.286.01:45:19.29#ibcon#end of sib2, iclass 11, count 0 2006.286.01:45:19.29#ibcon#*after write, iclass 11, count 0 2006.286.01:45:19.29#ibcon#*before return 0, iclass 11, count 0 2006.286.01:45:19.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:45:19.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.01:45:19.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.01:45:19.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.01:45:19.29$vck44/vblo=7,734.99 2006.286.01:45:19.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.01:45:19.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.01:45:19.29#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:19.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:45:19.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:45:19.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:45:19.29#ibcon#enter wrdev, iclass 13, count 0 2006.286.01:45:19.29#ibcon#first serial, iclass 13, count 0 2006.286.01:45:19.29#ibcon#enter sib2, iclass 13, count 0 2006.286.01:45:19.29#ibcon#flushed, iclass 13, count 0 2006.286.01:45:19.29#ibcon#about to write, iclass 13, count 0 2006.286.01:45:19.29#ibcon#wrote, iclass 13, count 0 2006.286.01:45:19.29#ibcon#about to read 3, iclass 13, count 0 2006.286.01:45:19.31#ibcon#read 3, iclass 13, count 0 2006.286.01:45:19.31#ibcon#about to read 4, iclass 13, count 0 2006.286.01:45:19.31#ibcon#read 4, iclass 13, count 0 2006.286.01:45:19.31#ibcon#about to read 5, iclass 13, count 0 2006.286.01:45:19.31#ibcon#read 5, iclass 13, count 0 2006.286.01:45:19.31#ibcon#about to read 6, iclass 13, count 0 2006.286.01:45:19.31#ibcon#read 6, iclass 13, count 0 2006.286.01:45:19.31#ibcon#end of sib2, iclass 13, count 0 2006.286.01:45:19.31#ibcon#*mode == 0, iclass 13, count 0 2006.286.01:45:19.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.01:45:19.31#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:45:19.31#ibcon#*before write, iclass 13, count 0 2006.286.01:45:19.31#ibcon#enter sib2, iclass 13, count 0 2006.286.01:45:19.31#ibcon#flushed, iclass 13, count 0 2006.286.01:45:19.31#ibcon#about to write, iclass 13, count 0 2006.286.01:45:19.31#ibcon#wrote, iclass 13, count 0 2006.286.01:45:19.31#ibcon#about to read 3, iclass 13, count 0 2006.286.01:45:19.35#ibcon#read 3, iclass 13, count 0 2006.286.01:45:19.35#ibcon#about to read 4, iclass 13, count 0 2006.286.01:45:19.35#ibcon#read 4, iclass 13, count 0 2006.286.01:45:19.35#ibcon#about to read 5, iclass 13, count 0 2006.286.01:45:19.35#ibcon#read 5, iclass 13, count 0 2006.286.01:45:19.35#ibcon#about to read 6, iclass 13, count 0 2006.286.01:45:19.35#ibcon#read 6, iclass 13, count 0 2006.286.01:45:19.35#ibcon#end of sib2, iclass 13, count 0 2006.286.01:45:19.35#ibcon#*after write, iclass 13, count 0 2006.286.01:45:19.35#ibcon#*before return 0, iclass 13, count 0 2006.286.01:45:19.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:45:19.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.01:45:19.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.01:45:19.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.01:45:19.35$vck44/vb=7,4 2006.286.01:45:19.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.01:45:19.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.01:45:19.35#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:19.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:45:19.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:45:19.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:45:19.41#ibcon#enter wrdev, iclass 15, count 2 2006.286.01:45:19.41#ibcon#first serial, iclass 15, count 2 2006.286.01:45:19.41#ibcon#enter sib2, iclass 15, count 2 2006.286.01:45:19.41#ibcon#flushed, iclass 15, count 2 2006.286.01:45:19.41#ibcon#about to write, iclass 15, count 2 2006.286.01:45:19.41#ibcon#wrote, iclass 15, count 2 2006.286.01:45:19.41#ibcon#about to read 3, iclass 15, count 2 2006.286.01:45:19.43#ibcon#read 3, iclass 15, count 2 2006.286.01:45:19.43#ibcon#about to read 4, iclass 15, count 2 2006.286.01:45:19.43#ibcon#read 4, iclass 15, count 2 2006.286.01:45:19.43#ibcon#about to read 5, iclass 15, count 2 2006.286.01:45:19.43#ibcon#read 5, iclass 15, count 2 2006.286.01:45:19.43#ibcon#about to read 6, iclass 15, count 2 2006.286.01:45:19.43#ibcon#read 6, iclass 15, count 2 2006.286.01:45:19.43#ibcon#end of sib2, iclass 15, count 2 2006.286.01:45:19.43#ibcon#*mode == 0, iclass 15, count 2 2006.286.01:45:19.43#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.01:45:19.43#ibcon#[27=AT07-04\r\n] 2006.286.01:45:19.43#ibcon#*before write, iclass 15, count 2 2006.286.01:45:19.43#ibcon#enter sib2, iclass 15, count 2 2006.286.01:45:19.43#ibcon#flushed, iclass 15, count 2 2006.286.01:45:19.43#ibcon#about to write, iclass 15, count 2 2006.286.01:45:19.43#ibcon#wrote, iclass 15, count 2 2006.286.01:45:19.43#ibcon#about to read 3, iclass 15, count 2 2006.286.01:45:19.46#ibcon#read 3, iclass 15, count 2 2006.286.01:45:19.46#ibcon#about to read 4, iclass 15, count 2 2006.286.01:45:19.46#ibcon#read 4, iclass 15, count 2 2006.286.01:45:19.46#ibcon#about to read 5, iclass 15, count 2 2006.286.01:45:19.46#ibcon#read 5, iclass 15, count 2 2006.286.01:45:19.46#ibcon#about to read 6, iclass 15, count 2 2006.286.01:45:19.46#ibcon#read 6, iclass 15, count 2 2006.286.01:45:19.46#ibcon#end of sib2, iclass 15, count 2 2006.286.01:45:19.46#ibcon#*after write, iclass 15, count 2 2006.286.01:45:19.46#ibcon#*before return 0, iclass 15, count 2 2006.286.01:45:19.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:45:19.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.01:45:19.46#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.01:45:19.46#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:19.46#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:45:19.58#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:45:19.58#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:45:19.58#ibcon#enter wrdev, iclass 15, count 0 2006.286.01:45:19.58#ibcon#first serial, iclass 15, count 0 2006.286.01:45:19.58#ibcon#enter sib2, iclass 15, count 0 2006.286.01:45:19.58#ibcon#flushed, iclass 15, count 0 2006.286.01:45:19.58#ibcon#about to write, iclass 15, count 0 2006.286.01:45:19.58#ibcon#wrote, iclass 15, count 0 2006.286.01:45:19.58#ibcon#about to read 3, iclass 15, count 0 2006.286.01:45:19.60#ibcon#read 3, iclass 15, count 0 2006.286.01:45:19.60#ibcon#about to read 4, iclass 15, count 0 2006.286.01:45:19.60#ibcon#read 4, iclass 15, count 0 2006.286.01:45:19.60#ibcon#about to read 5, iclass 15, count 0 2006.286.01:45:19.60#ibcon#read 5, iclass 15, count 0 2006.286.01:45:19.60#ibcon#about to read 6, iclass 15, count 0 2006.286.01:45:19.60#ibcon#read 6, iclass 15, count 0 2006.286.01:45:19.60#ibcon#end of sib2, iclass 15, count 0 2006.286.01:45:19.60#ibcon#*mode == 0, iclass 15, count 0 2006.286.01:45:19.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.01:45:19.60#ibcon#[27=USB\r\n] 2006.286.01:45:19.60#ibcon#*before write, iclass 15, count 0 2006.286.01:45:19.60#ibcon#enter sib2, iclass 15, count 0 2006.286.01:45:19.60#ibcon#flushed, iclass 15, count 0 2006.286.01:45:19.60#ibcon#about to write, iclass 15, count 0 2006.286.01:45:19.60#ibcon#wrote, iclass 15, count 0 2006.286.01:45:19.60#ibcon#about to read 3, iclass 15, count 0 2006.286.01:45:19.63#ibcon#read 3, iclass 15, count 0 2006.286.01:45:19.63#ibcon#about to read 4, iclass 15, count 0 2006.286.01:45:19.63#ibcon#read 4, iclass 15, count 0 2006.286.01:45:19.63#ibcon#about to read 5, iclass 15, count 0 2006.286.01:45:19.63#ibcon#read 5, iclass 15, count 0 2006.286.01:45:19.63#ibcon#about to read 6, iclass 15, count 0 2006.286.01:45:19.63#ibcon#read 6, iclass 15, count 0 2006.286.01:45:19.63#ibcon#end of sib2, iclass 15, count 0 2006.286.01:45:19.63#ibcon#*after write, iclass 15, count 0 2006.286.01:45:19.63#ibcon#*before return 0, iclass 15, count 0 2006.286.01:45:19.63#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:45:19.63#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.01:45:19.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.01:45:19.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.01:45:19.63$vck44/vblo=8,744.99 2006.286.01:45:19.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.01:45:19.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.01:45:19.63#ibcon#ireg 17 cls_cnt 0 2006.286.01:45:19.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:45:19.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:45:19.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:45:19.63#ibcon#enter wrdev, iclass 17, count 0 2006.286.01:45:19.63#ibcon#first serial, iclass 17, count 0 2006.286.01:45:19.63#ibcon#enter sib2, iclass 17, count 0 2006.286.01:45:19.63#ibcon#flushed, iclass 17, count 0 2006.286.01:45:19.63#ibcon#about to write, iclass 17, count 0 2006.286.01:45:19.63#ibcon#wrote, iclass 17, count 0 2006.286.01:45:19.63#ibcon#about to read 3, iclass 17, count 0 2006.286.01:45:19.65#ibcon#read 3, iclass 17, count 0 2006.286.01:45:19.65#ibcon#about to read 4, iclass 17, count 0 2006.286.01:45:19.65#ibcon#read 4, iclass 17, count 0 2006.286.01:45:19.65#ibcon#about to read 5, iclass 17, count 0 2006.286.01:45:19.65#ibcon#read 5, iclass 17, count 0 2006.286.01:45:19.65#ibcon#about to read 6, iclass 17, count 0 2006.286.01:45:19.65#ibcon#read 6, iclass 17, count 0 2006.286.01:45:19.65#ibcon#end of sib2, iclass 17, count 0 2006.286.01:45:19.65#ibcon#*mode == 0, iclass 17, count 0 2006.286.01:45:19.65#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.01:45:19.65#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:45:19.65#ibcon#*before write, iclass 17, count 0 2006.286.01:45:19.65#ibcon#enter sib2, iclass 17, count 0 2006.286.01:45:19.65#ibcon#flushed, iclass 17, count 0 2006.286.01:45:19.65#ibcon#about to write, iclass 17, count 0 2006.286.01:45:19.65#ibcon#wrote, iclass 17, count 0 2006.286.01:45:19.65#ibcon#about to read 3, iclass 17, count 0 2006.286.01:45:19.69#ibcon#read 3, iclass 17, count 0 2006.286.01:45:19.69#ibcon#about to read 4, iclass 17, count 0 2006.286.01:45:19.69#ibcon#read 4, iclass 17, count 0 2006.286.01:45:19.69#ibcon#about to read 5, iclass 17, count 0 2006.286.01:45:19.69#ibcon#read 5, iclass 17, count 0 2006.286.01:45:19.69#ibcon#about to read 6, iclass 17, count 0 2006.286.01:45:19.69#ibcon#read 6, iclass 17, count 0 2006.286.01:45:19.69#ibcon#end of sib2, iclass 17, count 0 2006.286.01:45:19.69#ibcon#*after write, iclass 17, count 0 2006.286.01:45:19.69#ibcon#*before return 0, iclass 17, count 0 2006.286.01:45:19.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:45:19.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.01:45:19.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.01:45:19.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.01:45:19.69$vck44/vb=8,4 2006.286.01:45:19.69#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.01:45:19.69#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.01:45:19.69#ibcon#ireg 11 cls_cnt 2 2006.286.01:45:19.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:45:19.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:45:19.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:45:19.75#ibcon#enter wrdev, iclass 19, count 2 2006.286.01:45:19.75#ibcon#first serial, iclass 19, count 2 2006.286.01:45:19.75#ibcon#enter sib2, iclass 19, count 2 2006.286.01:45:19.75#ibcon#flushed, iclass 19, count 2 2006.286.01:45:19.75#ibcon#about to write, iclass 19, count 2 2006.286.01:45:19.75#ibcon#wrote, iclass 19, count 2 2006.286.01:45:19.75#ibcon#about to read 3, iclass 19, count 2 2006.286.01:45:19.77#ibcon#read 3, iclass 19, count 2 2006.286.01:45:19.77#ibcon#about to read 4, iclass 19, count 2 2006.286.01:45:19.77#ibcon#read 4, iclass 19, count 2 2006.286.01:45:19.77#ibcon#about to read 5, iclass 19, count 2 2006.286.01:45:19.77#ibcon#read 5, iclass 19, count 2 2006.286.01:45:19.77#ibcon#about to read 6, iclass 19, count 2 2006.286.01:45:19.77#ibcon#read 6, iclass 19, count 2 2006.286.01:45:19.77#ibcon#end of sib2, iclass 19, count 2 2006.286.01:45:19.77#ibcon#*mode == 0, iclass 19, count 2 2006.286.01:45:19.77#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.01:45:19.77#ibcon#[27=AT08-04\r\n] 2006.286.01:45:19.77#ibcon#*before write, iclass 19, count 2 2006.286.01:45:19.77#ibcon#enter sib2, iclass 19, count 2 2006.286.01:45:19.77#ibcon#flushed, iclass 19, count 2 2006.286.01:45:19.77#ibcon#about to write, iclass 19, count 2 2006.286.01:45:19.77#ibcon#wrote, iclass 19, count 2 2006.286.01:45:19.77#ibcon#about to read 3, iclass 19, count 2 2006.286.01:45:19.80#ibcon#read 3, iclass 19, count 2 2006.286.01:45:19.80#ibcon#about to read 4, iclass 19, count 2 2006.286.01:45:19.80#ibcon#read 4, iclass 19, count 2 2006.286.01:45:19.80#ibcon#about to read 5, iclass 19, count 2 2006.286.01:45:19.80#ibcon#read 5, iclass 19, count 2 2006.286.01:45:19.80#ibcon#about to read 6, iclass 19, count 2 2006.286.01:45:19.80#ibcon#read 6, iclass 19, count 2 2006.286.01:45:19.80#ibcon#end of sib2, iclass 19, count 2 2006.286.01:45:19.80#ibcon#*after write, iclass 19, count 2 2006.286.01:45:19.80#ibcon#*before return 0, iclass 19, count 2 2006.286.01:45:19.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:45:19.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.01:45:19.80#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.01:45:19.80#ibcon#ireg 7 cls_cnt 0 2006.286.01:45:19.80#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:45:19.92#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:45:19.92#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:45:19.92#ibcon#enter wrdev, iclass 19, count 0 2006.286.01:45:19.92#ibcon#first serial, iclass 19, count 0 2006.286.01:45:19.92#ibcon#enter sib2, iclass 19, count 0 2006.286.01:45:19.92#ibcon#flushed, iclass 19, count 0 2006.286.01:45:19.92#ibcon#about to write, iclass 19, count 0 2006.286.01:45:19.92#ibcon#wrote, iclass 19, count 0 2006.286.01:45:19.92#ibcon#about to read 3, iclass 19, count 0 2006.286.01:45:19.94#ibcon#read 3, iclass 19, count 0 2006.286.01:45:19.94#ibcon#about to read 4, iclass 19, count 0 2006.286.01:45:19.94#ibcon#read 4, iclass 19, count 0 2006.286.01:45:19.94#ibcon#about to read 5, iclass 19, count 0 2006.286.01:45:19.94#ibcon#read 5, iclass 19, count 0 2006.286.01:45:19.94#ibcon#about to read 6, iclass 19, count 0 2006.286.01:45:19.94#ibcon#read 6, iclass 19, count 0 2006.286.01:45:19.94#ibcon#end of sib2, iclass 19, count 0 2006.286.01:45:19.94#ibcon#*mode == 0, iclass 19, count 0 2006.286.01:45:19.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.01:45:19.94#ibcon#[27=USB\r\n] 2006.286.01:45:19.94#ibcon#*before write, iclass 19, count 0 2006.286.01:45:19.94#ibcon#enter sib2, iclass 19, count 0 2006.286.01:45:19.94#ibcon#flushed, iclass 19, count 0 2006.286.01:45:19.94#ibcon#about to write, iclass 19, count 0 2006.286.01:45:19.94#ibcon#wrote, iclass 19, count 0 2006.286.01:45:19.94#ibcon#about to read 3, iclass 19, count 0 2006.286.01:45:19.97#ibcon#read 3, iclass 19, count 0 2006.286.01:45:19.97#ibcon#about to read 4, iclass 19, count 0 2006.286.01:45:19.97#ibcon#read 4, iclass 19, count 0 2006.286.01:45:19.97#ibcon#about to read 5, iclass 19, count 0 2006.286.01:45:19.97#ibcon#read 5, iclass 19, count 0 2006.286.01:45:19.97#ibcon#about to read 6, iclass 19, count 0 2006.286.01:45:19.97#ibcon#read 6, iclass 19, count 0 2006.286.01:45:19.97#ibcon#end of sib2, iclass 19, count 0 2006.286.01:45:19.97#ibcon#*after write, iclass 19, count 0 2006.286.01:45:19.97#ibcon#*before return 0, iclass 19, count 0 2006.286.01:45:19.97#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:45:19.97#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.01:45:19.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.01:45:19.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.01:45:19.97$vck44/vabw=wide 2006.286.01:45:19.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.01:45:19.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.01:45:19.97#ibcon#ireg 8 cls_cnt 0 2006.286.01:45:19.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:45:19.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:45:19.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:45:19.97#ibcon#enter wrdev, iclass 21, count 0 2006.286.01:45:19.97#ibcon#first serial, iclass 21, count 0 2006.286.01:45:19.97#ibcon#enter sib2, iclass 21, count 0 2006.286.01:45:19.97#ibcon#flushed, iclass 21, count 0 2006.286.01:45:19.97#ibcon#about to write, iclass 21, count 0 2006.286.01:45:19.97#ibcon#wrote, iclass 21, count 0 2006.286.01:45:19.97#ibcon#about to read 3, iclass 21, count 0 2006.286.01:45:19.99#ibcon#read 3, iclass 21, count 0 2006.286.01:45:19.99#ibcon#about to read 4, iclass 21, count 0 2006.286.01:45:19.99#ibcon#read 4, iclass 21, count 0 2006.286.01:45:19.99#ibcon#about to read 5, iclass 21, count 0 2006.286.01:45:19.99#ibcon#read 5, iclass 21, count 0 2006.286.01:45:19.99#ibcon#about to read 6, iclass 21, count 0 2006.286.01:45:19.99#ibcon#read 6, iclass 21, count 0 2006.286.01:45:19.99#ibcon#end of sib2, iclass 21, count 0 2006.286.01:45:19.99#ibcon#*mode == 0, iclass 21, count 0 2006.286.01:45:19.99#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.01:45:19.99#ibcon#[25=BW32\r\n] 2006.286.01:45:19.99#ibcon#*before write, iclass 21, count 0 2006.286.01:45:19.99#ibcon#enter sib2, iclass 21, count 0 2006.286.01:45:19.99#ibcon#flushed, iclass 21, count 0 2006.286.01:45:19.99#ibcon#about to write, iclass 21, count 0 2006.286.01:45:19.99#ibcon#wrote, iclass 21, count 0 2006.286.01:45:19.99#ibcon#about to read 3, iclass 21, count 0 2006.286.01:45:20.02#ibcon#read 3, iclass 21, count 0 2006.286.01:45:20.02#ibcon#about to read 4, iclass 21, count 0 2006.286.01:45:20.02#ibcon#read 4, iclass 21, count 0 2006.286.01:45:20.02#ibcon#about to read 5, iclass 21, count 0 2006.286.01:45:20.02#ibcon#read 5, iclass 21, count 0 2006.286.01:45:20.02#ibcon#about to read 6, iclass 21, count 0 2006.286.01:45:20.02#ibcon#read 6, iclass 21, count 0 2006.286.01:45:20.02#ibcon#end of sib2, iclass 21, count 0 2006.286.01:45:20.02#ibcon#*after write, iclass 21, count 0 2006.286.01:45:20.02#ibcon#*before return 0, iclass 21, count 0 2006.286.01:45:20.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:45:20.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.01:45:20.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.01:45:20.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.01:45:20.02$vck44/vbbw=wide 2006.286.01:45:20.02#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.01:45:20.02#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.01:45:20.02#ibcon#ireg 8 cls_cnt 0 2006.286.01:45:20.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:45:20.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:45:20.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:45:20.09#ibcon#enter wrdev, iclass 23, count 0 2006.286.01:45:20.09#ibcon#first serial, iclass 23, count 0 2006.286.01:45:20.09#ibcon#enter sib2, iclass 23, count 0 2006.286.01:45:20.09#ibcon#flushed, iclass 23, count 0 2006.286.01:45:20.09#ibcon#about to write, iclass 23, count 0 2006.286.01:45:20.09#ibcon#wrote, iclass 23, count 0 2006.286.01:45:20.09#ibcon#about to read 3, iclass 23, count 0 2006.286.01:45:20.11#ibcon#read 3, iclass 23, count 0 2006.286.01:45:20.11#ibcon#about to read 4, iclass 23, count 0 2006.286.01:45:20.11#ibcon#read 4, iclass 23, count 0 2006.286.01:45:20.11#ibcon#about to read 5, iclass 23, count 0 2006.286.01:45:20.11#ibcon#read 5, iclass 23, count 0 2006.286.01:45:20.11#ibcon#about to read 6, iclass 23, count 0 2006.286.01:45:20.11#ibcon#read 6, iclass 23, count 0 2006.286.01:45:20.11#ibcon#end of sib2, iclass 23, count 0 2006.286.01:45:20.11#ibcon#*mode == 0, iclass 23, count 0 2006.286.01:45:20.11#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.01:45:20.11#ibcon#[27=BW32\r\n] 2006.286.01:45:20.11#ibcon#*before write, iclass 23, count 0 2006.286.01:45:20.11#ibcon#enter sib2, iclass 23, count 0 2006.286.01:45:20.11#ibcon#flushed, iclass 23, count 0 2006.286.01:45:20.11#ibcon#about to write, iclass 23, count 0 2006.286.01:45:20.11#ibcon#wrote, iclass 23, count 0 2006.286.01:45:20.11#ibcon#about to read 3, iclass 23, count 0 2006.286.01:45:20.14#ibcon#read 3, iclass 23, count 0 2006.286.01:45:20.14#ibcon#about to read 4, iclass 23, count 0 2006.286.01:45:20.14#ibcon#read 4, iclass 23, count 0 2006.286.01:45:20.14#ibcon#about to read 5, iclass 23, count 0 2006.286.01:45:20.14#ibcon#read 5, iclass 23, count 0 2006.286.01:45:20.14#ibcon#about to read 6, iclass 23, count 0 2006.286.01:45:20.14#ibcon#read 6, iclass 23, count 0 2006.286.01:45:20.14#ibcon#end of sib2, iclass 23, count 0 2006.286.01:45:20.14#ibcon#*after write, iclass 23, count 0 2006.286.01:45:20.14#ibcon#*before return 0, iclass 23, count 0 2006.286.01:45:20.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:45:20.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:45:20.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.01:45:20.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.01:45:20.14$setupk4/ifdk4 2006.286.01:45:20.14$ifdk4/lo= 2006.286.01:45:20.14$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:45:20.14$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:45:20.14$ifdk4/patch= 2006.286.01:45:20.14$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:45:20.14$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:45:20.14$setupk4/!*+20s 2006.286.01:45:23.16#abcon#<5=/03 3.7 7.1 21.21 791016.0\r\n> 2006.286.01:45:23.18#abcon#{5=INTERFACE CLEAR} 2006.286.01:45:23.24#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:45:33.33#abcon#<5=/03 3.7 7.1 21.21 791016.0\r\n> 2006.286.01:45:33.35#abcon#{5=INTERFACE CLEAR} 2006.286.01:45:33.41#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:45:34.65$setupk4/"tpicd 2006.286.01:45:34.65$setupk4/echo=off 2006.286.01:45:34.65$setupk4/xlog=off 2006.286.01:45:34.65:!2006.286.01:49:50 2006.286.01:46:44.14#trakl#Source acquired 2006.286.01:46:45.14#flagr#flagr/antenna,acquired 2006.286.01:49:50.00:preob 2006.286.01:49:50.13/onsource/TRACKING 2006.286.01:49:50.13:!2006.286.01:50:00 2006.286.01:50:00.00:"tape 2006.286.01:50:00.00:"st=record 2006.286.01:50:00.00:data_valid=on 2006.286.01:50:00.00:midob 2006.286.01:50:00.13/onsource/TRACKING 2006.286.01:50:00.13/wx/21.22,1016.1,79 2006.286.01:50:00.24/cable/+6.5034E-03 2006.286.01:50:01.33/va/01,07,usb,yes,32,34 2006.286.01:50:01.33/va/02,06,usb,yes,32,32 2006.286.01:50:01.33/va/03,07,usb,yes,31,33 2006.286.01:50:01.33/va/04,06,usb,yes,32,34 2006.286.01:50:01.33/va/05,03,usb,yes,32,32 2006.286.01:50:01.33/va/06,04,usb,yes,29,28 2006.286.01:50:01.33/va/07,04,usb,yes,29,30 2006.286.01:50:01.33/va/08,03,usb,yes,30,37 2006.286.01:50:01.56/valo/01,524.99,yes,locked 2006.286.01:50:01.56/valo/02,534.99,yes,locked 2006.286.01:50:01.56/valo/03,564.99,yes,locked 2006.286.01:50:01.56/valo/04,624.99,yes,locked 2006.286.01:50:01.56/valo/05,734.99,yes,locked 2006.286.01:50:01.56/valo/06,814.99,yes,locked 2006.286.01:50:01.56/valo/07,864.99,yes,locked 2006.286.01:50:01.56/valo/08,884.99,yes,locked 2006.286.01:50:02.65/vb/01,04,usb,yes,29,27 2006.286.01:50:02.65/vb/02,05,usb,yes,28,27 2006.286.01:50:02.65/vb/03,04,usb,yes,28,31 2006.286.01:50:02.65/vb/04,05,usb,yes,29,28 2006.286.01:50:02.65/vb/05,04,usb,yes,25,27 2006.286.01:50:02.65/vb/06,03,usb,yes,36,32 2006.286.01:50:02.65/vb/07,04,usb,yes,29,29 2006.286.01:50:02.65/vb/08,04,usb,yes,26,30 2006.286.01:50:02.88/vblo/01,629.99,yes,locked 2006.286.01:50:02.88/vblo/02,634.99,yes,locked 2006.286.01:50:02.88/vblo/03,649.99,yes,locked 2006.286.01:50:02.88/vblo/04,679.99,yes,locked 2006.286.01:50:02.88/vblo/05,709.99,yes,locked 2006.286.01:50:02.88/vblo/06,719.99,yes,locked 2006.286.01:50:02.88/vblo/07,734.99,yes,locked 2006.286.01:50:02.88/vblo/08,744.99,yes,locked 2006.286.01:50:03.03/vabw/8 2006.286.01:50:03.18/vbbw/8 2006.286.01:50:03.27/xfe/off,on,12.0 2006.286.01:50:03.64/ifatt/23,28,28,28 2006.286.01:50:04.08/fmout-gps/S +2.74E-07 2006.286.01:50:04.10:!2006.286.01:53:20 2006.286.01:53:20.00:data_valid=off 2006.286.01:53:20.00:"et 2006.286.01:53:20.00:!+3s 2006.286.01:53:23.01:"tape 2006.286.01:53:23.01:postob 2006.286.01:53:23.18/cable/+6.5012E-03 2006.286.01:53:23.18/wx/21.21,1016.0,78 2006.286.01:53:24.07/fmout-gps/S +2.76E-07 2006.286.01:53:24.07:scan_name=286-0156,jd0610,70 2006.286.01:53:24.07:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.286.01:53:25.14#flagr#flagr/antenna,new-source 2006.286.01:53:25.14:checkk5 2006.286.01:53:25.50/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:53:26.20/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:53:26.56/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:53:26.97/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:53:27.32/chk_obsdata//k5ts1/T2860150??a.dat file size is correct (nominal:800MB, actual:796MB). 2006.286.01:53:27.70/chk_obsdata//k5ts2/T2860150??b.dat file size is correct (nominal:800MB, actual:796MB). 2006.286.01:53:28.06/chk_obsdata//k5ts3/T2860150??c.dat file size is correct (nominal:800MB, actual:796MB). 2006.286.01:53:28.51/chk_obsdata//k5ts4/T2860150??d.dat file size is correct (nominal:800MB, actual:796MB). 2006.286.01:53:29.29/k5log//k5ts1_log_newline 2006.286.01:53:29.99/k5log//k5ts2_log_newline 2006.286.01:53:30.95/k5log//k5ts3_log_newline 2006.286.01:53:31.71/k5log//k5ts4_log_newline 2006.286.01:53:31.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:53:31.73:setupk4=1 2006.286.01:53:31.73$setupk4/echo=on 2006.286.01:53:31.73$setupk4/pcalon 2006.286.01:53:31.73$pcalon/"no phase cal control is implemented here 2006.286.01:53:31.73$setupk4/"tpicd=stop 2006.286.01:53:31.73$setupk4/"rec=synch_on 2006.286.01:53:31.73$setupk4/"rec_mode=128 2006.286.01:53:31.73$setupk4/!* 2006.286.01:53:31.73$setupk4/recpk4 2006.286.01:53:31.73$recpk4/recpatch= 2006.286.01:53:31.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:53:31.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:53:31.73$setupk4/vck44 2006.286.01:53:31.73$vck44/valo=1,524.99 2006.286.01:53:31.74#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.01:53:31.74#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.01:53:31.74#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:31.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:53:31.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:53:31.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:53:31.74#ibcon#enter wrdev, iclass 35, count 0 2006.286.01:53:31.74#ibcon#first serial, iclass 35, count 0 2006.286.01:53:31.74#ibcon#enter sib2, iclass 35, count 0 2006.286.01:53:31.74#ibcon#flushed, iclass 35, count 0 2006.286.01:53:31.74#ibcon#about to write, iclass 35, count 0 2006.286.01:53:31.74#ibcon#wrote, iclass 35, count 0 2006.286.01:53:31.74#ibcon#about to read 3, iclass 35, count 0 2006.286.01:53:31.75#ibcon#read 3, iclass 35, count 0 2006.286.01:53:31.75#ibcon#about to read 4, iclass 35, count 0 2006.286.01:53:31.75#ibcon#read 4, iclass 35, count 0 2006.286.01:53:31.75#ibcon#about to read 5, iclass 35, count 0 2006.286.01:53:31.75#ibcon#read 5, iclass 35, count 0 2006.286.01:53:31.75#ibcon#about to read 6, iclass 35, count 0 2006.286.01:53:31.75#ibcon#read 6, iclass 35, count 0 2006.286.01:53:31.75#ibcon#end of sib2, iclass 35, count 0 2006.286.01:53:31.75#ibcon#*mode == 0, iclass 35, count 0 2006.286.01:53:31.75#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.01:53:31.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:53:31.75#ibcon#*before write, iclass 35, count 0 2006.286.01:53:31.75#ibcon#enter sib2, iclass 35, count 0 2006.286.01:53:31.75#ibcon#flushed, iclass 35, count 0 2006.286.01:53:31.75#ibcon#about to write, iclass 35, count 0 2006.286.01:53:31.75#ibcon#wrote, iclass 35, count 0 2006.286.01:53:31.75#ibcon#about to read 3, iclass 35, count 0 2006.286.01:53:31.80#ibcon#read 3, iclass 35, count 0 2006.286.01:53:31.80#ibcon#about to read 4, iclass 35, count 0 2006.286.01:53:31.80#ibcon#read 4, iclass 35, count 0 2006.286.01:53:31.80#ibcon#about to read 5, iclass 35, count 0 2006.286.01:53:31.80#ibcon#read 5, iclass 35, count 0 2006.286.01:53:31.80#ibcon#about to read 6, iclass 35, count 0 2006.286.01:53:31.80#ibcon#read 6, iclass 35, count 0 2006.286.01:53:31.80#ibcon#end of sib2, iclass 35, count 0 2006.286.01:53:31.80#ibcon#*after write, iclass 35, count 0 2006.286.01:53:31.80#ibcon#*before return 0, iclass 35, count 0 2006.286.01:53:31.80#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:53:31.80#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:53:31.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.01:53:31.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.01:53:31.80$vck44/va=1,7 2006.286.01:53:31.80#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.01:53:31.80#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.01:53:31.80#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:31.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:53:31.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:53:31.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:53:31.80#ibcon#enter wrdev, iclass 37, count 2 2006.286.01:53:31.80#ibcon#first serial, iclass 37, count 2 2006.286.01:53:31.80#ibcon#enter sib2, iclass 37, count 2 2006.286.01:53:31.80#ibcon#flushed, iclass 37, count 2 2006.286.01:53:31.80#ibcon#about to write, iclass 37, count 2 2006.286.01:53:31.80#ibcon#wrote, iclass 37, count 2 2006.286.01:53:31.80#ibcon#about to read 3, iclass 37, count 2 2006.286.01:53:31.82#ibcon#read 3, iclass 37, count 2 2006.286.01:53:31.82#ibcon#about to read 4, iclass 37, count 2 2006.286.01:53:31.82#ibcon#read 4, iclass 37, count 2 2006.286.01:53:31.82#ibcon#about to read 5, iclass 37, count 2 2006.286.01:53:31.82#ibcon#read 5, iclass 37, count 2 2006.286.01:53:31.82#ibcon#about to read 6, iclass 37, count 2 2006.286.01:53:31.82#ibcon#read 6, iclass 37, count 2 2006.286.01:53:31.82#ibcon#end of sib2, iclass 37, count 2 2006.286.01:53:31.82#ibcon#*mode == 0, iclass 37, count 2 2006.286.01:53:31.82#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.01:53:31.82#ibcon#[25=AT01-07\r\n] 2006.286.01:53:31.82#ibcon#*before write, iclass 37, count 2 2006.286.01:53:31.82#ibcon#enter sib2, iclass 37, count 2 2006.286.01:53:31.82#ibcon#flushed, iclass 37, count 2 2006.286.01:53:31.82#ibcon#about to write, iclass 37, count 2 2006.286.01:53:31.82#ibcon#wrote, iclass 37, count 2 2006.286.01:53:31.82#ibcon#about to read 3, iclass 37, count 2 2006.286.01:53:31.85#ibcon#read 3, iclass 37, count 2 2006.286.01:53:31.85#ibcon#about to read 4, iclass 37, count 2 2006.286.01:53:31.85#ibcon#read 4, iclass 37, count 2 2006.286.01:53:31.85#ibcon#about to read 5, iclass 37, count 2 2006.286.01:53:31.85#ibcon#read 5, iclass 37, count 2 2006.286.01:53:31.85#ibcon#about to read 6, iclass 37, count 2 2006.286.01:53:31.85#ibcon#read 6, iclass 37, count 2 2006.286.01:53:31.85#ibcon#end of sib2, iclass 37, count 2 2006.286.01:53:31.85#ibcon#*after write, iclass 37, count 2 2006.286.01:53:31.85#ibcon#*before return 0, iclass 37, count 2 2006.286.01:53:31.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:53:31.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:53:31.85#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.01:53:31.85#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:31.85#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:53:31.97#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:53:31.97#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:53:31.97#ibcon#enter wrdev, iclass 37, count 0 2006.286.01:53:31.97#ibcon#first serial, iclass 37, count 0 2006.286.01:53:31.97#ibcon#enter sib2, iclass 37, count 0 2006.286.01:53:31.97#ibcon#flushed, iclass 37, count 0 2006.286.01:53:31.97#ibcon#about to write, iclass 37, count 0 2006.286.01:53:31.97#ibcon#wrote, iclass 37, count 0 2006.286.01:53:31.97#ibcon#about to read 3, iclass 37, count 0 2006.286.01:53:31.99#ibcon#read 3, iclass 37, count 0 2006.286.01:53:31.99#ibcon#about to read 4, iclass 37, count 0 2006.286.01:53:31.99#ibcon#read 4, iclass 37, count 0 2006.286.01:53:31.99#ibcon#about to read 5, iclass 37, count 0 2006.286.01:53:31.99#ibcon#read 5, iclass 37, count 0 2006.286.01:53:31.99#ibcon#about to read 6, iclass 37, count 0 2006.286.01:53:31.99#ibcon#read 6, iclass 37, count 0 2006.286.01:53:31.99#ibcon#end of sib2, iclass 37, count 0 2006.286.01:53:31.99#ibcon#*mode == 0, iclass 37, count 0 2006.286.01:53:31.99#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.01:53:31.99#ibcon#[25=USB\r\n] 2006.286.01:53:31.99#ibcon#*before write, iclass 37, count 0 2006.286.01:53:31.99#ibcon#enter sib2, iclass 37, count 0 2006.286.01:53:31.99#ibcon#flushed, iclass 37, count 0 2006.286.01:53:31.99#ibcon#about to write, iclass 37, count 0 2006.286.01:53:31.99#ibcon#wrote, iclass 37, count 0 2006.286.01:53:31.99#ibcon#about to read 3, iclass 37, count 0 2006.286.01:53:32.02#ibcon#read 3, iclass 37, count 0 2006.286.01:53:32.02#ibcon#about to read 4, iclass 37, count 0 2006.286.01:53:32.02#ibcon#read 4, iclass 37, count 0 2006.286.01:53:32.02#ibcon#about to read 5, iclass 37, count 0 2006.286.01:53:32.02#ibcon#read 5, iclass 37, count 0 2006.286.01:53:32.02#ibcon#about to read 6, iclass 37, count 0 2006.286.01:53:32.02#ibcon#read 6, iclass 37, count 0 2006.286.01:53:32.02#ibcon#end of sib2, iclass 37, count 0 2006.286.01:53:32.02#ibcon#*after write, iclass 37, count 0 2006.286.01:53:32.02#ibcon#*before return 0, iclass 37, count 0 2006.286.01:53:32.02#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:53:32.02#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:53:32.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.01:53:32.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.01:53:32.02$vck44/valo=2,534.99 2006.286.01:53:32.02#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.01:53:32.02#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.01:53:32.02#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:32.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:53:32.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:53:32.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:53:32.02#ibcon#enter wrdev, iclass 39, count 0 2006.286.01:53:32.02#ibcon#first serial, iclass 39, count 0 2006.286.01:53:32.02#ibcon#enter sib2, iclass 39, count 0 2006.286.01:53:32.02#ibcon#flushed, iclass 39, count 0 2006.286.01:53:32.02#ibcon#about to write, iclass 39, count 0 2006.286.01:53:32.02#ibcon#wrote, iclass 39, count 0 2006.286.01:53:32.02#ibcon#about to read 3, iclass 39, count 0 2006.286.01:53:32.04#ibcon#read 3, iclass 39, count 0 2006.286.01:53:32.04#ibcon#about to read 4, iclass 39, count 0 2006.286.01:53:32.04#ibcon#read 4, iclass 39, count 0 2006.286.01:53:32.04#ibcon#about to read 5, iclass 39, count 0 2006.286.01:53:32.04#ibcon#read 5, iclass 39, count 0 2006.286.01:53:32.04#ibcon#about to read 6, iclass 39, count 0 2006.286.01:53:32.04#ibcon#read 6, iclass 39, count 0 2006.286.01:53:32.04#ibcon#end of sib2, iclass 39, count 0 2006.286.01:53:32.04#ibcon#*mode == 0, iclass 39, count 0 2006.286.01:53:32.04#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.01:53:32.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:53:32.04#ibcon#*before write, iclass 39, count 0 2006.286.01:53:32.04#ibcon#enter sib2, iclass 39, count 0 2006.286.01:53:32.04#ibcon#flushed, iclass 39, count 0 2006.286.01:53:32.04#ibcon#about to write, iclass 39, count 0 2006.286.01:53:32.04#ibcon#wrote, iclass 39, count 0 2006.286.01:53:32.04#ibcon#about to read 3, iclass 39, count 0 2006.286.01:53:32.08#ibcon#read 3, iclass 39, count 0 2006.286.01:53:32.08#ibcon#about to read 4, iclass 39, count 0 2006.286.01:53:32.08#ibcon#read 4, iclass 39, count 0 2006.286.01:53:32.08#ibcon#about to read 5, iclass 39, count 0 2006.286.01:53:32.08#ibcon#read 5, iclass 39, count 0 2006.286.01:53:32.08#ibcon#about to read 6, iclass 39, count 0 2006.286.01:53:32.08#ibcon#read 6, iclass 39, count 0 2006.286.01:53:32.08#ibcon#end of sib2, iclass 39, count 0 2006.286.01:53:32.08#ibcon#*after write, iclass 39, count 0 2006.286.01:53:32.08#ibcon#*before return 0, iclass 39, count 0 2006.286.01:53:32.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:53:32.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:53:32.08#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.01:53:32.08#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.01:53:32.08$vck44/va=2,6 2006.286.01:53:32.08#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.01:53:32.08#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.01:53:32.08#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:32.08#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:53:32.14#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:53:32.14#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:53:32.14#ibcon#enter wrdev, iclass 3, count 2 2006.286.01:53:32.14#ibcon#first serial, iclass 3, count 2 2006.286.01:53:32.14#ibcon#enter sib2, iclass 3, count 2 2006.286.01:53:32.14#ibcon#flushed, iclass 3, count 2 2006.286.01:53:32.14#ibcon#about to write, iclass 3, count 2 2006.286.01:53:32.14#ibcon#wrote, iclass 3, count 2 2006.286.01:53:32.14#ibcon#about to read 3, iclass 3, count 2 2006.286.01:53:32.16#ibcon#read 3, iclass 3, count 2 2006.286.01:53:32.16#ibcon#about to read 4, iclass 3, count 2 2006.286.01:53:32.16#ibcon#read 4, iclass 3, count 2 2006.286.01:53:32.16#ibcon#about to read 5, iclass 3, count 2 2006.286.01:53:32.16#ibcon#read 5, iclass 3, count 2 2006.286.01:53:32.16#ibcon#about to read 6, iclass 3, count 2 2006.286.01:53:32.16#ibcon#read 6, iclass 3, count 2 2006.286.01:53:32.16#ibcon#end of sib2, iclass 3, count 2 2006.286.01:53:32.16#ibcon#*mode == 0, iclass 3, count 2 2006.286.01:53:32.16#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.01:53:32.16#ibcon#[25=AT02-06\r\n] 2006.286.01:53:32.16#ibcon#*before write, iclass 3, count 2 2006.286.01:53:32.16#ibcon#enter sib2, iclass 3, count 2 2006.286.01:53:32.16#ibcon#flushed, iclass 3, count 2 2006.286.01:53:32.16#ibcon#about to write, iclass 3, count 2 2006.286.01:53:32.16#ibcon#wrote, iclass 3, count 2 2006.286.01:53:32.16#ibcon#about to read 3, iclass 3, count 2 2006.286.01:53:32.19#ibcon#read 3, iclass 3, count 2 2006.286.01:53:32.19#ibcon#about to read 4, iclass 3, count 2 2006.286.01:53:32.19#ibcon#read 4, iclass 3, count 2 2006.286.01:53:32.19#ibcon#about to read 5, iclass 3, count 2 2006.286.01:53:32.19#ibcon#read 5, iclass 3, count 2 2006.286.01:53:32.19#ibcon#about to read 6, iclass 3, count 2 2006.286.01:53:32.19#ibcon#read 6, iclass 3, count 2 2006.286.01:53:32.19#ibcon#end of sib2, iclass 3, count 2 2006.286.01:53:32.19#ibcon#*after write, iclass 3, count 2 2006.286.01:53:32.19#ibcon#*before return 0, iclass 3, count 2 2006.286.01:53:32.19#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:53:32.19#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:53:32.19#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.01:53:32.19#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:32.19#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:53:32.31#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:53:32.31#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:53:32.31#ibcon#enter wrdev, iclass 3, count 0 2006.286.01:53:32.31#ibcon#first serial, iclass 3, count 0 2006.286.01:53:32.31#ibcon#enter sib2, iclass 3, count 0 2006.286.01:53:32.31#ibcon#flushed, iclass 3, count 0 2006.286.01:53:32.31#ibcon#about to write, iclass 3, count 0 2006.286.01:53:32.31#ibcon#wrote, iclass 3, count 0 2006.286.01:53:32.31#ibcon#about to read 3, iclass 3, count 0 2006.286.01:53:32.33#ibcon#read 3, iclass 3, count 0 2006.286.01:53:32.33#ibcon#about to read 4, iclass 3, count 0 2006.286.01:53:32.33#ibcon#read 4, iclass 3, count 0 2006.286.01:53:32.33#ibcon#about to read 5, iclass 3, count 0 2006.286.01:53:32.33#ibcon#read 5, iclass 3, count 0 2006.286.01:53:32.33#ibcon#about to read 6, iclass 3, count 0 2006.286.01:53:32.33#ibcon#read 6, iclass 3, count 0 2006.286.01:53:32.33#ibcon#end of sib2, iclass 3, count 0 2006.286.01:53:32.33#ibcon#*mode == 0, iclass 3, count 0 2006.286.01:53:32.33#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.01:53:32.33#ibcon#[25=USB\r\n] 2006.286.01:53:32.33#ibcon#*before write, iclass 3, count 0 2006.286.01:53:32.33#ibcon#enter sib2, iclass 3, count 0 2006.286.01:53:32.33#ibcon#flushed, iclass 3, count 0 2006.286.01:53:32.33#ibcon#about to write, iclass 3, count 0 2006.286.01:53:32.33#ibcon#wrote, iclass 3, count 0 2006.286.01:53:32.33#ibcon#about to read 3, iclass 3, count 0 2006.286.01:53:32.36#ibcon#read 3, iclass 3, count 0 2006.286.01:53:32.36#ibcon#about to read 4, iclass 3, count 0 2006.286.01:53:32.36#ibcon#read 4, iclass 3, count 0 2006.286.01:53:32.36#ibcon#about to read 5, iclass 3, count 0 2006.286.01:53:32.36#ibcon#read 5, iclass 3, count 0 2006.286.01:53:32.36#ibcon#about to read 6, iclass 3, count 0 2006.286.01:53:32.36#ibcon#read 6, iclass 3, count 0 2006.286.01:53:32.36#ibcon#end of sib2, iclass 3, count 0 2006.286.01:53:32.36#ibcon#*after write, iclass 3, count 0 2006.286.01:53:32.36#ibcon#*before return 0, iclass 3, count 0 2006.286.01:53:32.36#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:53:32.36#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:53:32.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.01:53:32.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.01:53:32.36$vck44/valo=3,564.99 2006.286.01:53:32.36#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.01:53:32.36#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.01:53:32.36#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:32.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:53:32.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:53:32.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:53:32.36#ibcon#enter wrdev, iclass 5, count 0 2006.286.01:53:32.36#ibcon#first serial, iclass 5, count 0 2006.286.01:53:32.36#ibcon#enter sib2, iclass 5, count 0 2006.286.01:53:32.36#ibcon#flushed, iclass 5, count 0 2006.286.01:53:32.36#ibcon#about to write, iclass 5, count 0 2006.286.01:53:32.36#ibcon#wrote, iclass 5, count 0 2006.286.01:53:32.36#ibcon#about to read 3, iclass 5, count 0 2006.286.01:53:32.38#ibcon#read 3, iclass 5, count 0 2006.286.01:53:32.38#ibcon#about to read 4, iclass 5, count 0 2006.286.01:53:32.38#ibcon#read 4, iclass 5, count 0 2006.286.01:53:32.38#ibcon#about to read 5, iclass 5, count 0 2006.286.01:53:32.38#ibcon#read 5, iclass 5, count 0 2006.286.01:53:32.38#ibcon#about to read 6, iclass 5, count 0 2006.286.01:53:32.38#ibcon#read 6, iclass 5, count 0 2006.286.01:53:32.38#ibcon#end of sib2, iclass 5, count 0 2006.286.01:53:32.38#ibcon#*mode == 0, iclass 5, count 0 2006.286.01:53:32.38#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.01:53:32.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:53:32.38#ibcon#*before write, iclass 5, count 0 2006.286.01:53:32.38#ibcon#enter sib2, iclass 5, count 0 2006.286.01:53:32.38#ibcon#flushed, iclass 5, count 0 2006.286.01:53:32.38#ibcon#about to write, iclass 5, count 0 2006.286.01:53:32.38#ibcon#wrote, iclass 5, count 0 2006.286.01:53:32.38#ibcon#about to read 3, iclass 5, count 0 2006.286.01:53:32.42#ibcon#read 3, iclass 5, count 0 2006.286.01:53:32.42#ibcon#about to read 4, iclass 5, count 0 2006.286.01:53:32.42#ibcon#read 4, iclass 5, count 0 2006.286.01:53:32.42#ibcon#about to read 5, iclass 5, count 0 2006.286.01:53:32.42#ibcon#read 5, iclass 5, count 0 2006.286.01:53:32.42#ibcon#about to read 6, iclass 5, count 0 2006.286.01:53:32.42#ibcon#read 6, iclass 5, count 0 2006.286.01:53:32.42#ibcon#end of sib2, iclass 5, count 0 2006.286.01:53:32.42#ibcon#*after write, iclass 5, count 0 2006.286.01:53:32.42#ibcon#*before return 0, iclass 5, count 0 2006.286.01:53:32.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:53:32.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:53:32.42#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.01:53:32.42#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.01:53:32.42$vck44/va=3,7 2006.286.01:53:32.42#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.01:53:32.42#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.01:53:32.42#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:32.42#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:53:32.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:53:32.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:53:32.48#ibcon#enter wrdev, iclass 7, count 2 2006.286.01:53:32.48#ibcon#first serial, iclass 7, count 2 2006.286.01:53:32.48#ibcon#enter sib2, iclass 7, count 2 2006.286.01:53:32.48#ibcon#flushed, iclass 7, count 2 2006.286.01:53:32.48#ibcon#about to write, iclass 7, count 2 2006.286.01:53:32.48#ibcon#wrote, iclass 7, count 2 2006.286.01:53:32.48#ibcon#about to read 3, iclass 7, count 2 2006.286.01:53:32.50#ibcon#read 3, iclass 7, count 2 2006.286.01:53:32.50#ibcon#about to read 4, iclass 7, count 2 2006.286.01:53:32.50#ibcon#read 4, iclass 7, count 2 2006.286.01:53:32.50#ibcon#about to read 5, iclass 7, count 2 2006.286.01:53:32.50#ibcon#read 5, iclass 7, count 2 2006.286.01:53:32.50#ibcon#about to read 6, iclass 7, count 2 2006.286.01:53:32.50#ibcon#read 6, iclass 7, count 2 2006.286.01:53:32.50#ibcon#end of sib2, iclass 7, count 2 2006.286.01:53:32.50#ibcon#*mode == 0, iclass 7, count 2 2006.286.01:53:32.50#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.01:53:32.50#ibcon#[25=AT03-07\r\n] 2006.286.01:53:32.50#ibcon#*before write, iclass 7, count 2 2006.286.01:53:32.50#ibcon#enter sib2, iclass 7, count 2 2006.286.01:53:32.50#ibcon#flushed, iclass 7, count 2 2006.286.01:53:32.50#ibcon#about to write, iclass 7, count 2 2006.286.01:53:32.50#ibcon#wrote, iclass 7, count 2 2006.286.01:53:32.50#ibcon#about to read 3, iclass 7, count 2 2006.286.01:53:32.53#ibcon#read 3, iclass 7, count 2 2006.286.01:53:32.53#ibcon#about to read 4, iclass 7, count 2 2006.286.01:53:32.53#ibcon#read 4, iclass 7, count 2 2006.286.01:53:32.53#ibcon#about to read 5, iclass 7, count 2 2006.286.01:53:32.53#ibcon#read 5, iclass 7, count 2 2006.286.01:53:32.53#ibcon#about to read 6, iclass 7, count 2 2006.286.01:53:32.53#ibcon#read 6, iclass 7, count 2 2006.286.01:53:32.53#ibcon#end of sib2, iclass 7, count 2 2006.286.01:53:32.53#ibcon#*after write, iclass 7, count 2 2006.286.01:53:32.53#ibcon#*before return 0, iclass 7, count 2 2006.286.01:53:32.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:53:32.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:53:32.53#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.01:53:32.53#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:32.53#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:53:32.65#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:53:32.65#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:53:32.65#ibcon#enter wrdev, iclass 7, count 0 2006.286.01:53:32.65#ibcon#first serial, iclass 7, count 0 2006.286.01:53:32.65#ibcon#enter sib2, iclass 7, count 0 2006.286.01:53:32.65#ibcon#flushed, iclass 7, count 0 2006.286.01:53:32.65#ibcon#about to write, iclass 7, count 0 2006.286.01:53:32.65#ibcon#wrote, iclass 7, count 0 2006.286.01:53:32.65#ibcon#about to read 3, iclass 7, count 0 2006.286.01:53:32.67#ibcon#read 3, iclass 7, count 0 2006.286.01:53:32.67#ibcon#about to read 4, iclass 7, count 0 2006.286.01:53:32.67#ibcon#read 4, iclass 7, count 0 2006.286.01:53:32.67#ibcon#about to read 5, iclass 7, count 0 2006.286.01:53:32.67#ibcon#read 5, iclass 7, count 0 2006.286.01:53:32.67#ibcon#about to read 6, iclass 7, count 0 2006.286.01:53:32.67#ibcon#read 6, iclass 7, count 0 2006.286.01:53:32.67#ibcon#end of sib2, iclass 7, count 0 2006.286.01:53:32.67#ibcon#*mode == 0, iclass 7, count 0 2006.286.01:53:32.67#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.01:53:32.67#ibcon#[25=USB\r\n] 2006.286.01:53:32.67#ibcon#*before write, iclass 7, count 0 2006.286.01:53:32.67#ibcon#enter sib2, iclass 7, count 0 2006.286.01:53:32.67#ibcon#flushed, iclass 7, count 0 2006.286.01:53:32.67#ibcon#about to write, iclass 7, count 0 2006.286.01:53:32.67#ibcon#wrote, iclass 7, count 0 2006.286.01:53:32.67#ibcon#about to read 3, iclass 7, count 0 2006.286.01:53:32.70#ibcon#read 3, iclass 7, count 0 2006.286.01:53:32.70#ibcon#about to read 4, iclass 7, count 0 2006.286.01:53:32.70#ibcon#read 4, iclass 7, count 0 2006.286.01:53:32.70#ibcon#about to read 5, iclass 7, count 0 2006.286.01:53:32.70#ibcon#read 5, iclass 7, count 0 2006.286.01:53:32.70#ibcon#about to read 6, iclass 7, count 0 2006.286.01:53:32.70#ibcon#read 6, iclass 7, count 0 2006.286.01:53:32.70#ibcon#end of sib2, iclass 7, count 0 2006.286.01:53:32.70#ibcon#*after write, iclass 7, count 0 2006.286.01:53:32.70#ibcon#*before return 0, iclass 7, count 0 2006.286.01:53:32.70#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:53:32.70#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:53:32.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.01:53:32.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.01:53:32.70$vck44/valo=4,624.99 2006.286.01:53:32.70#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.01:53:32.70#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.01:53:32.70#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:32.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:53:32.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:53:32.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:53:32.70#ibcon#enter wrdev, iclass 11, count 0 2006.286.01:53:32.70#ibcon#first serial, iclass 11, count 0 2006.286.01:53:32.70#ibcon#enter sib2, iclass 11, count 0 2006.286.01:53:32.70#ibcon#flushed, iclass 11, count 0 2006.286.01:53:32.70#ibcon#about to write, iclass 11, count 0 2006.286.01:53:32.70#ibcon#wrote, iclass 11, count 0 2006.286.01:53:32.70#ibcon#about to read 3, iclass 11, count 0 2006.286.01:53:32.72#ibcon#read 3, iclass 11, count 0 2006.286.01:53:32.72#ibcon#about to read 4, iclass 11, count 0 2006.286.01:53:32.72#ibcon#read 4, iclass 11, count 0 2006.286.01:53:32.72#ibcon#about to read 5, iclass 11, count 0 2006.286.01:53:32.72#ibcon#read 5, iclass 11, count 0 2006.286.01:53:32.72#ibcon#about to read 6, iclass 11, count 0 2006.286.01:53:32.72#ibcon#read 6, iclass 11, count 0 2006.286.01:53:32.72#ibcon#end of sib2, iclass 11, count 0 2006.286.01:53:32.72#ibcon#*mode == 0, iclass 11, count 0 2006.286.01:53:32.72#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.01:53:32.72#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:53:32.72#ibcon#*before write, iclass 11, count 0 2006.286.01:53:32.72#ibcon#enter sib2, iclass 11, count 0 2006.286.01:53:32.72#ibcon#flushed, iclass 11, count 0 2006.286.01:53:32.72#ibcon#about to write, iclass 11, count 0 2006.286.01:53:32.72#ibcon#wrote, iclass 11, count 0 2006.286.01:53:32.72#ibcon#about to read 3, iclass 11, count 0 2006.286.01:53:32.76#ibcon#read 3, iclass 11, count 0 2006.286.01:53:32.76#ibcon#about to read 4, iclass 11, count 0 2006.286.01:53:32.76#ibcon#read 4, iclass 11, count 0 2006.286.01:53:32.76#ibcon#about to read 5, iclass 11, count 0 2006.286.01:53:32.76#ibcon#read 5, iclass 11, count 0 2006.286.01:53:32.76#ibcon#about to read 6, iclass 11, count 0 2006.286.01:53:32.76#ibcon#read 6, iclass 11, count 0 2006.286.01:53:32.76#ibcon#end of sib2, iclass 11, count 0 2006.286.01:53:32.76#ibcon#*after write, iclass 11, count 0 2006.286.01:53:32.76#ibcon#*before return 0, iclass 11, count 0 2006.286.01:53:32.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:53:32.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:53:32.76#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.01:53:32.76#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.01:53:32.76$vck44/va=4,6 2006.286.01:53:32.76#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.01:53:32.76#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.01:53:32.76#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:32.76#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:53:32.82#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:53:32.82#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:53:32.82#ibcon#enter wrdev, iclass 13, count 2 2006.286.01:53:32.82#ibcon#first serial, iclass 13, count 2 2006.286.01:53:32.82#ibcon#enter sib2, iclass 13, count 2 2006.286.01:53:32.82#ibcon#flushed, iclass 13, count 2 2006.286.01:53:32.82#ibcon#about to write, iclass 13, count 2 2006.286.01:53:32.82#ibcon#wrote, iclass 13, count 2 2006.286.01:53:32.82#ibcon#about to read 3, iclass 13, count 2 2006.286.01:53:32.84#ibcon#read 3, iclass 13, count 2 2006.286.01:53:32.84#ibcon#about to read 4, iclass 13, count 2 2006.286.01:53:32.84#ibcon#read 4, iclass 13, count 2 2006.286.01:53:32.84#ibcon#about to read 5, iclass 13, count 2 2006.286.01:53:32.84#ibcon#read 5, iclass 13, count 2 2006.286.01:53:32.84#ibcon#about to read 6, iclass 13, count 2 2006.286.01:53:32.84#ibcon#read 6, iclass 13, count 2 2006.286.01:53:32.84#ibcon#end of sib2, iclass 13, count 2 2006.286.01:53:32.84#ibcon#*mode == 0, iclass 13, count 2 2006.286.01:53:32.84#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.01:53:32.84#ibcon#[25=AT04-06\r\n] 2006.286.01:53:32.84#ibcon#*before write, iclass 13, count 2 2006.286.01:53:32.84#ibcon#enter sib2, iclass 13, count 2 2006.286.01:53:32.84#ibcon#flushed, iclass 13, count 2 2006.286.01:53:32.84#ibcon#about to write, iclass 13, count 2 2006.286.01:53:32.84#ibcon#wrote, iclass 13, count 2 2006.286.01:53:32.84#ibcon#about to read 3, iclass 13, count 2 2006.286.01:53:32.87#ibcon#read 3, iclass 13, count 2 2006.286.01:53:32.87#ibcon#about to read 4, iclass 13, count 2 2006.286.01:53:32.87#ibcon#read 4, iclass 13, count 2 2006.286.01:53:32.87#ibcon#about to read 5, iclass 13, count 2 2006.286.01:53:32.87#ibcon#read 5, iclass 13, count 2 2006.286.01:53:32.87#ibcon#about to read 6, iclass 13, count 2 2006.286.01:53:32.87#ibcon#read 6, iclass 13, count 2 2006.286.01:53:32.87#ibcon#end of sib2, iclass 13, count 2 2006.286.01:53:32.87#ibcon#*after write, iclass 13, count 2 2006.286.01:53:32.87#ibcon#*before return 0, iclass 13, count 2 2006.286.01:53:32.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:53:32.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:53:32.87#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.01:53:32.87#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:32.87#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:53:32.99#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:53:32.99#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:53:32.99#ibcon#enter wrdev, iclass 13, count 0 2006.286.01:53:32.99#ibcon#first serial, iclass 13, count 0 2006.286.01:53:32.99#ibcon#enter sib2, iclass 13, count 0 2006.286.01:53:32.99#ibcon#flushed, iclass 13, count 0 2006.286.01:53:32.99#ibcon#about to write, iclass 13, count 0 2006.286.01:53:32.99#ibcon#wrote, iclass 13, count 0 2006.286.01:53:32.99#ibcon#about to read 3, iclass 13, count 0 2006.286.01:53:33.01#ibcon#read 3, iclass 13, count 0 2006.286.01:53:33.01#ibcon#about to read 4, iclass 13, count 0 2006.286.01:53:33.01#ibcon#read 4, iclass 13, count 0 2006.286.01:53:33.01#ibcon#about to read 5, iclass 13, count 0 2006.286.01:53:33.01#ibcon#read 5, iclass 13, count 0 2006.286.01:53:33.01#ibcon#about to read 6, iclass 13, count 0 2006.286.01:53:33.01#ibcon#read 6, iclass 13, count 0 2006.286.01:53:33.01#ibcon#end of sib2, iclass 13, count 0 2006.286.01:53:33.01#ibcon#*mode == 0, iclass 13, count 0 2006.286.01:53:33.01#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.01:53:33.01#ibcon#[25=USB\r\n] 2006.286.01:53:33.01#ibcon#*before write, iclass 13, count 0 2006.286.01:53:33.01#ibcon#enter sib2, iclass 13, count 0 2006.286.01:53:33.01#ibcon#flushed, iclass 13, count 0 2006.286.01:53:33.01#ibcon#about to write, iclass 13, count 0 2006.286.01:53:33.01#ibcon#wrote, iclass 13, count 0 2006.286.01:53:33.01#ibcon#about to read 3, iclass 13, count 0 2006.286.01:53:33.04#ibcon#read 3, iclass 13, count 0 2006.286.01:53:33.04#ibcon#about to read 4, iclass 13, count 0 2006.286.01:53:33.04#ibcon#read 4, iclass 13, count 0 2006.286.01:53:33.04#ibcon#about to read 5, iclass 13, count 0 2006.286.01:53:33.04#ibcon#read 5, iclass 13, count 0 2006.286.01:53:33.04#ibcon#about to read 6, iclass 13, count 0 2006.286.01:53:33.04#ibcon#read 6, iclass 13, count 0 2006.286.01:53:33.04#ibcon#end of sib2, iclass 13, count 0 2006.286.01:53:33.04#ibcon#*after write, iclass 13, count 0 2006.286.01:53:33.04#ibcon#*before return 0, iclass 13, count 0 2006.286.01:53:33.04#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:53:33.04#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:53:33.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.01:53:33.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.01:53:33.04$vck44/valo=5,734.99 2006.286.01:53:33.04#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.01:53:33.04#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.01:53:33.04#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:33.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:53:33.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:53:33.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:53:33.04#ibcon#enter wrdev, iclass 15, count 0 2006.286.01:53:33.04#ibcon#first serial, iclass 15, count 0 2006.286.01:53:33.04#ibcon#enter sib2, iclass 15, count 0 2006.286.01:53:33.04#ibcon#flushed, iclass 15, count 0 2006.286.01:53:33.04#ibcon#about to write, iclass 15, count 0 2006.286.01:53:33.04#ibcon#wrote, iclass 15, count 0 2006.286.01:53:33.04#ibcon#about to read 3, iclass 15, count 0 2006.286.01:53:33.06#ibcon#read 3, iclass 15, count 0 2006.286.01:53:33.06#ibcon#about to read 4, iclass 15, count 0 2006.286.01:53:33.06#ibcon#read 4, iclass 15, count 0 2006.286.01:53:33.06#ibcon#about to read 5, iclass 15, count 0 2006.286.01:53:33.06#ibcon#read 5, iclass 15, count 0 2006.286.01:53:33.06#ibcon#about to read 6, iclass 15, count 0 2006.286.01:53:33.06#ibcon#read 6, iclass 15, count 0 2006.286.01:53:33.06#ibcon#end of sib2, iclass 15, count 0 2006.286.01:53:33.06#ibcon#*mode == 0, iclass 15, count 0 2006.286.01:53:33.06#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.01:53:33.06#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:53:33.06#ibcon#*before write, iclass 15, count 0 2006.286.01:53:33.06#ibcon#enter sib2, iclass 15, count 0 2006.286.01:53:33.06#ibcon#flushed, iclass 15, count 0 2006.286.01:53:33.06#ibcon#about to write, iclass 15, count 0 2006.286.01:53:33.06#ibcon#wrote, iclass 15, count 0 2006.286.01:53:33.06#ibcon#about to read 3, iclass 15, count 0 2006.286.01:53:33.10#ibcon#read 3, iclass 15, count 0 2006.286.01:53:33.10#ibcon#about to read 4, iclass 15, count 0 2006.286.01:53:33.10#ibcon#read 4, iclass 15, count 0 2006.286.01:53:33.10#ibcon#about to read 5, iclass 15, count 0 2006.286.01:53:33.10#ibcon#read 5, iclass 15, count 0 2006.286.01:53:33.10#ibcon#about to read 6, iclass 15, count 0 2006.286.01:53:33.10#ibcon#read 6, iclass 15, count 0 2006.286.01:53:33.10#ibcon#end of sib2, iclass 15, count 0 2006.286.01:53:33.10#ibcon#*after write, iclass 15, count 0 2006.286.01:53:33.10#ibcon#*before return 0, iclass 15, count 0 2006.286.01:53:33.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:53:33.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:53:33.10#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.01:53:33.10#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.01:53:33.10$vck44/va=5,3 2006.286.01:53:33.10#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.01:53:33.10#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.01:53:33.10#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:33.10#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:53:33.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:53:33.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:53:33.16#ibcon#enter wrdev, iclass 17, count 2 2006.286.01:53:33.16#ibcon#first serial, iclass 17, count 2 2006.286.01:53:33.16#ibcon#enter sib2, iclass 17, count 2 2006.286.01:53:33.16#ibcon#flushed, iclass 17, count 2 2006.286.01:53:33.16#ibcon#about to write, iclass 17, count 2 2006.286.01:53:33.16#ibcon#wrote, iclass 17, count 2 2006.286.01:53:33.16#ibcon#about to read 3, iclass 17, count 2 2006.286.01:53:33.18#ibcon#read 3, iclass 17, count 2 2006.286.01:53:33.18#ibcon#about to read 4, iclass 17, count 2 2006.286.01:53:33.18#ibcon#read 4, iclass 17, count 2 2006.286.01:53:33.18#ibcon#about to read 5, iclass 17, count 2 2006.286.01:53:33.18#ibcon#read 5, iclass 17, count 2 2006.286.01:53:33.18#ibcon#about to read 6, iclass 17, count 2 2006.286.01:53:33.18#ibcon#read 6, iclass 17, count 2 2006.286.01:53:33.18#ibcon#end of sib2, iclass 17, count 2 2006.286.01:53:33.18#ibcon#*mode == 0, iclass 17, count 2 2006.286.01:53:33.18#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.01:53:33.18#ibcon#[25=AT05-03\r\n] 2006.286.01:53:33.18#ibcon#*before write, iclass 17, count 2 2006.286.01:53:33.18#ibcon#enter sib2, iclass 17, count 2 2006.286.01:53:33.18#ibcon#flushed, iclass 17, count 2 2006.286.01:53:33.18#ibcon#about to write, iclass 17, count 2 2006.286.01:53:33.18#ibcon#wrote, iclass 17, count 2 2006.286.01:53:33.18#ibcon#about to read 3, iclass 17, count 2 2006.286.01:53:33.21#ibcon#read 3, iclass 17, count 2 2006.286.01:53:33.21#ibcon#about to read 4, iclass 17, count 2 2006.286.01:53:33.21#ibcon#read 4, iclass 17, count 2 2006.286.01:53:33.21#ibcon#about to read 5, iclass 17, count 2 2006.286.01:53:33.21#ibcon#read 5, iclass 17, count 2 2006.286.01:53:33.21#ibcon#about to read 6, iclass 17, count 2 2006.286.01:53:33.21#ibcon#read 6, iclass 17, count 2 2006.286.01:53:33.21#ibcon#end of sib2, iclass 17, count 2 2006.286.01:53:33.21#ibcon#*after write, iclass 17, count 2 2006.286.01:53:33.21#ibcon#*before return 0, iclass 17, count 2 2006.286.01:53:33.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:53:33.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:53:33.21#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.01:53:33.21#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:33.21#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:53:33.33#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:53:33.33#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:53:33.33#ibcon#enter wrdev, iclass 17, count 0 2006.286.01:53:33.33#ibcon#first serial, iclass 17, count 0 2006.286.01:53:33.33#ibcon#enter sib2, iclass 17, count 0 2006.286.01:53:33.33#ibcon#flushed, iclass 17, count 0 2006.286.01:53:33.33#ibcon#about to write, iclass 17, count 0 2006.286.01:53:33.33#ibcon#wrote, iclass 17, count 0 2006.286.01:53:33.33#ibcon#about to read 3, iclass 17, count 0 2006.286.01:53:33.35#ibcon#read 3, iclass 17, count 0 2006.286.01:53:33.35#ibcon#about to read 4, iclass 17, count 0 2006.286.01:53:33.35#ibcon#read 4, iclass 17, count 0 2006.286.01:53:33.35#ibcon#about to read 5, iclass 17, count 0 2006.286.01:53:33.35#ibcon#read 5, iclass 17, count 0 2006.286.01:53:33.35#ibcon#about to read 6, iclass 17, count 0 2006.286.01:53:33.35#ibcon#read 6, iclass 17, count 0 2006.286.01:53:33.35#ibcon#end of sib2, iclass 17, count 0 2006.286.01:53:33.35#ibcon#*mode == 0, iclass 17, count 0 2006.286.01:53:33.35#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.01:53:33.35#ibcon#[25=USB\r\n] 2006.286.01:53:33.35#ibcon#*before write, iclass 17, count 0 2006.286.01:53:33.35#ibcon#enter sib2, iclass 17, count 0 2006.286.01:53:33.35#ibcon#flushed, iclass 17, count 0 2006.286.01:53:33.35#ibcon#about to write, iclass 17, count 0 2006.286.01:53:33.35#ibcon#wrote, iclass 17, count 0 2006.286.01:53:33.35#ibcon#about to read 3, iclass 17, count 0 2006.286.01:53:33.38#ibcon#read 3, iclass 17, count 0 2006.286.01:53:33.38#ibcon#about to read 4, iclass 17, count 0 2006.286.01:53:33.38#ibcon#read 4, iclass 17, count 0 2006.286.01:53:33.38#ibcon#about to read 5, iclass 17, count 0 2006.286.01:53:33.38#ibcon#read 5, iclass 17, count 0 2006.286.01:53:33.38#ibcon#about to read 6, iclass 17, count 0 2006.286.01:53:33.38#ibcon#read 6, iclass 17, count 0 2006.286.01:53:33.38#ibcon#end of sib2, iclass 17, count 0 2006.286.01:53:33.38#ibcon#*after write, iclass 17, count 0 2006.286.01:53:33.38#ibcon#*before return 0, iclass 17, count 0 2006.286.01:53:33.38#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:53:33.38#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:53:33.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.01:53:33.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.01:53:33.38$vck44/valo=6,814.99 2006.286.01:53:33.38#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.01:53:33.38#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.01:53:33.38#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:33.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:53:33.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:53:33.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:53:33.38#ibcon#enter wrdev, iclass 19, count 0 2006.286.01:53:33.38#ibcon#first serial, iclass 19, count 0 2006.286.01:53:33.38#ibcon#enter sib2, iclass 19, count 0 2006.286.01:53:33.38#ibcon#flushed, iclass 19, count 0 2006.286.01:53:33.38#ibcon#about to write, iclass 19, count 0 2006.286.01:53:33.38#ibcon#wrote, iclass 19, count 0 2006.286.01:53:33.38#ibcon#about to read 3, iclass 19, count 0 2006.286.01:53:33.40#ibcon#read 3, iclass 19, count 0 2006.286.01:53:33.40#ibcon#about to read 4, iclass 19, count 0 2006.286.01:53:33.40#ibcon#read 4, iclass 19, count 0 2006.286.01:53:33.40#ibcon#about to read 5, iclass 19, count 0 2006.286.01:53:33.40#ibcon#read 5, iclass 19, count 0 2006.286.01:53:33.40#ibcon#about to read 6, iclass 19, count 0 2006.286.01:53:33.40#ibcon#read 6, iclass 19, count 0 2006.286.01:53:33.40#ibcon#end of sib2, iclass 19, count 0 2006.286.01:53:33.40#ibcon#*mode == 0, iclass 19, count 0 2006.286.01:53:33.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.01:53:33.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:53:33.40#ibcon#*before write, iclass 19, count 0 2006.286.01:53:33.40#ibcon#enter sib2, iclass 19, count 0 2006.286.01:53:33.40#ibcon#flushed, iclass 19, count 0 2006.286.01:53:33.40#ibcon#about to write, iclass 19, count 0 2006.286.01:53:33.40#ibcon#wrote, iclass 19, count 0 2006.286.01:53:33.40#ibcon#about to read 3, iclass 19, count 0 2006.286.01:53:33.44#ibcon#read 3, iclass 19, count 0 2006.286.01:53:33.44#ibcon#about to read 4, iclass 19, count 0 2006.286.01:53:33.44#ibcon#read 4, iclass 19, count 0 2006.286.01:53:33.44#ibcon#about to read 5, iclass 19, count 0 2006.286.01:53:33.44#ibcon#read 5, iclass 19, count 0 2006.286.01:53:33.44#ibcon#about to read 6, iclass 19, count 0 2006.286.01:53:33.44#ibcon#read 6, iclass 19, count 0 2006.286.01:53:33.44#ibcon#end of sib2, iclass 19, count 0 2006.286.01:53:33.44#ibcon#*after write, iclass 19, count 0 2006.286.01:53:33.44#ibcon#*before return 0, iclass 19, count 0 2006.286.01:53:33.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:53:33.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:53:33.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.01:53:33.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.01:53:33.44$vck44/va=6,4 2006.286.01:53:33.44#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.01:53:33.44#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.01:53:33.44#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:33.44#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:53:33.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:53:33.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:53:33.50#ibcon#enter wrdev, iclass 21, count 2 2006.286.01:53:33.50#ibcon#first serial, iclass 21, count 2 2006.286.01:53:33.50#ibcon#enter sib2, iclass 21, count 2 2006.286.01:53:33.50#ibcon#flushed, iclass 21, count 2 2006.286.01:53:33.50#ibcon#about to write, iclass 21, count 2 2006.286.01:53:33.50#ibcon#wrote, iclass 21, count 2 2006.286.01:53:33.50#ibcon#about to read 3, iclass 21, count 2 2006.286.01:53:33.52#ibcon#read 3, iclass 21, count 2 2006.286.01:53:33.52#ibcon#about to read 4, iclass 21, count 2 2006.286.01:53:33.52#ibcon#read 4, iclass 21, count 2 2006.286.01:53:33.52#ibcon#about to read 5, iclass 21, count 2 2006.286.01:53:33.52#ibcon#read 5, iclass 21, count 2 2006.286.01:53:33.52#ibcon#about to read 6, iclass 21, count 2 2006.286.01:53:33.52#ibcon#read 6, iclass 21, count 2 2006.286.01:53:33.52#ibcon#end of sib2, iclass 21, count 2 2006.286.01:53:33.52#ibcon#*mode == 0, iclass 21, count 2 2006.286.01:53:33.52#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.01:53:33.52#ibcon#[25=AT06-04\r\n] 2006.286.01:53:33.52#ibcon#*before write, iclass 21, count 2 2006.286.01:53:33.52#ibcon#enter sib2, iclass 21, count 2 2006.286.01:53:33.52#ibcon#flushed, iclass 21, count 2 2006.286.01:53:33.52#ibcon#about to write, iclass 21, count 2 2006.286.01:53:33.52#ibcon#wrote, iclass 21, count 2 2006.286.01:53:33.52#ibcon#about to read 3, iclass 21, count 2 2006.286.01:53:33.55#ibcon#read 3, iclass 21, count 2 2006.286.01:53:33.55#ibcon#about to read 4, iclass 21, count 2 2006.286.01:53:33.55#ibcon#read 4, iclass 21, count 2 2006.286.01:53:33.55#ibcon#about to read 5, iclass 21, count 2 2006.286.01:53:33.55#ibcon#read 5, iclass 21, count 2 2006.286.01:53:33.55#ibcon#about to read 6, iclass 21, count 2 2006.286.01:53:33.55#ibcon#read 6, iclass 21, count 2 2006.286.01:53:33.55#ibcon#end of sib2, iclass 21, count 2 2006.286.01:53:33.55#ibcon#*after write, iclass 21, count 2 2006.286.01:53:33.55#ibcon#*before return 0, iclass 21, count 2 2006.286.01:53:33.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:53:33.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:53:33.55#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.01:53:33.55#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:33.55#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:53:33.67#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:53:33.67#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:53:33.67#ibcon#enter wrdev, iclass 21, count 0 2006.286.01:53:33.67#ibcon#first serial, iclass 21, count 0 2006.286.01:53:33.67#ibcon#enter sib2, iclass 21, count 0 2006.286.01:53:33.67#ibcon#flushed, iclass 21, count 0 2006.286.01:53:33.67#ibcon#about to write, iclass 21, count 0 2006.286.01:53:33.67#ibcon#wrote, iclass 21, count 0 2006.286.01:53:33.67#ibcon#about to read 3, iclass 21, count 0 2006.286.01:53:33.69#ibcon#read 3, iclass 21, count 0 2006.286.01:53:33.69#ibcon#about to read 4, iclass 21, count 0 2006.286.01:53:33.69#ibcon#read 4, iclass 21, count 0 2006.286.01:53:33.69#ibcon#about to read 5, iclass 21, count 0 2006.286.01:53:33.69#ibcon#read 5, iclass 21, count 0 2006.286.01:53:33.69#ibcon#about to read 6, iclass 21, count 0 2006.286.01:53:33.69#ibcon#read 6, iclass 21, count 0 2006.286.01:53:33.69#ibcon#end of sib2, iclass 21, count 0 2006.286.01:53:33.69#ibcon#*mode == 0, iclass 21, count 0 2006.286.01:53:33.69#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.01:53:33.69#ibcon#[25=USB\r\n] 2006.286.01:53:33.69#ibcon#*before write, iclass 21, count 0 2006.286.01:53:33.69#ibcon#enter sib2, iclass 21, count 0 2006.286.01:53:33.69#ibcon#flushed, iclass 21, count 0 2006.286.01:53:33.69#ibcon#about to write, iclass 21, count 0 2006.286.01:53:33.69#ibcon#wrote, iclass 21, count 0 2006.286.01:53:33.69#ibcon#about to read 3, iclass 21, count 0 2006.286.01:53:33.72#ibcon#read 3, iclass 21, count 0 2006.286.01:53:33.72#ibcon#about to read 4, iclass 21, count 0 2006.286.01:53:33.72#ibcon#read 4, iclass 21, count 0 2006.286.01:53:33.72#ibcon#about to read 5, iclass 21, count 0 2006.286.01:53:33.72#ibcon#read 5, iclass 21, count 0 2006.286.01:53:33.72#ibcon#about to read 6, iclass 21, count 0 2006.286.01:53:33.72#ibcon#read 6, iclass 21, count 0 2006.286.01:53:33.72#ibcon#end of sib2, iclass 21, count 0 2006.286.01:53:33.72#ibcon#*after write, iclass 21, count 0 2006.286.01:53:33.72#ibcon#*before return 0, iclass 21, count 0 2006.286.01:53:33.72#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:53:33.72#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:53:33.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.01:53:33.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.01:53:33.72$vck44/valo=7,864.99 2006.286.01:53:33.72#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.01:53:33.72#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.01:53:33.72#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:33.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:53:33.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:53:33.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:53:33.72#ibcon#enter wrdev, iclass 23, count 0 2006.286.01:53:33.72#ibcon#first serial, iclass 23, count 0 2006.286.01:53:33.72#ibcon#enter sib2, iclass 23, count 0 2006.286.01:53:33.72#ibcon#flushed, iclass 23, count 0 2006.286.01:53:33.72#ibcon#about to write, iclass 23, count 0 2006.286.01:53:33.72#ibcon#wrote, iclass 23, count 0 2006.286.01:53:33.72#ibcon#about to read 3, iclass 23, count 0 2006.286.01:53:33.74#ibcon#read 3, iclass 23, count 0 2006.286.01:53:33.74#ibcon#about to read 4, iclass 23, count 0 2006.286.01:53:33.74#ibcon#read 4, iclass 23, count 0 2006.286.01:53:33.74#ibcon#about to read 5, iclass 23, count 0 2006.286.01:53:33.74#ibcon#read 5, iclass 23, count 0 2006.286.01:53:33.74#ibcon#about to read 6, iclass 23, count 0 2006.286.01:53:33.74#ibcon#read 6, iclass 23, count 0 2006.286.01:53:33.74#ibcon#end of sib2, iclass 23, count 0 2006.286.01:53:33.74#ibcon#*mode == 0, iclass 23, count 0 2006.286.01:53:33.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.01:53:33.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:53:33.74#ibcon#*before write, iclass 23, count 0 2006.286.01:53:33.74#ibcon#enter sib2, iclass 23, count 0 2006.286.01:53:33.74#ibcon#flushed, iclass 23, count 0 2006.286.01:53:33.74#ibcon#about to write, iclass 23, count 0 2006.286.01:53:33.74#ibcon#wrote, iclass 23, count 0 2006.286.01:53:33.74#ibcon#about to read 3, iclass 23, count 0 2006.286.01:53:33.78#ibcon#read 3, iclass 23, count 0 2006.286.01:53:33.78#ibcon#about to read 4, iclass 23, count 0 2006.286.01:53:33.78#ibcon#read 4, iclass 23, count 0 2006.286.01:53:33.78#ibcon#about to read 5, iclass 23, count 0 2006.286.01:53:33.78#ibcon#read 5, iclass 23, count 0 2006.286.01:53:33.78#ibcon#about to read 6, iclass 23, count 0 2006.286.01:53:33.78#ibcon#read 6, iclass 23, count 0 2006.286.01:53:33.78#ibcon#end of sib2, iclass 23, count 0 2006.286.01:53:33.78#ibcon#*after write, iclass 23, count 0 2006.286.01:53:33.78#ibcon#*before return 0, iclass 23, count 0 2006.286.01:53:33.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:53:33.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:53:33.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.01:53:33.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.01:53:33.78$vck44/va=7,4 2006.286.01:53:33.78#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.01:53:33.78#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.01:53:33.78#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:33.78#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:53:33.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:53:33.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:53:33.84#ibcon#enter wrdev, iclass 25, count 2 2006.286.01:53:33.84#ibcon#first serial, iclass 25, count 2 2006.286.01:53:33.84#ibcon#enter sib2, iclass 25, count 2 2006.286.01:53:33.84#ibcon#flushed, iclass 25, count 2 2006.286.01:53:33.84#ibcon#about to write, iclass 25, count 2 2006.286.01:53:33.84#ibcon#wrote, iclass 25, count 2 2006.286.01:53:33.84#ibcon#about to read 3, iclass 25, count 2 2006.286.01:53:33.86#ibcon#read 3, iclass 25, count 2 2006.286.01:53:33.86#ibcon#about to read 4, iclass 25, count 2 2006.286.01:53:33.86#ibcon#read 4, iclass 25, count 2 2006.286.01:53:33.86#ibcon#about to read 5, iclass 25, count 2 2006.286.01:53:33.86#ibcon#read 5, iclass 25, count 2 2006.286.01:53:33.86#ibcon#about to read 6, iclass 25, count 2 2006.286.01:53:33.86#ibcon#read 6, iclass 25, count 2 2006.286.01:53:33.86#ibcon#end of sib2, iclass 25, count 2 2006.286.01:53:33.86#ibcon#*mode == 0, iclass 25, count 2 2006.286.01:53:33.86#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.01:53:33.86#ibcon#[25=AT07-04\r\n] 2006.286.01:53:33.86#ibcon#*before write, iclass 25, count 2 2006.286.01:53:33.86#ibcon#enter sib2, iclass 25, count 2 2006.286.01:53:33.86#ibcon#flushed, iclass 25, count 2 2006.286.01:53:33.86#ibcon#about to write, iclass 25, count 2 2006.286.01:53:33.86#ibcon#wrote, iclass 25, count 2 2006.286.01:53:33.86#ibcon#about to read 3, iclass 25, count 2 2006.286.01:53:33.89#ibcon#read 3, iclass 25, count 2 2006.286.01:53:33.89#ibcon#about to read 4, iclass 25, count 2 2006.286.01:53:33.89#ibcon#read 4, iclass 25, count 2 2006.286.01:53:33.89#ibcon#about to read 5, iclass 25, count 2 2006.286.01:53:33.89#ibcon#read 5, iclass 25, count 2 2006.286.01:53:33.89#ibcon#about to read 6, iclass 25, count 2 2006.286.01:53:33.89#ibcon#read 6, iclass 25, count 2 2006.286.01:53:33.89#ibcon#end of sib2, iclass 25, count 2 2006.286.01:53:33.89#ibcon#*after write, iclass 25, count 2 2006.286.01:53:33.89#ibcon#*before return 0, iclass 25, count 2 2006.286.01:53:33.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:53:33.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:53:33.89#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.01:53:33.89#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:33.89#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:53:34.01#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:53:34.01#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:53:34.01#ibcon#enter wrdev, iclass 25, count 0 2006.286.01:53:34.01#ibcon#first serial, iclass 25, count 0 2006.286.01:53:34.01#ibcon#enter sib2, iclass 25, count 0 2006.286.01:53:34.01#ibcon#flushed, iclass 25, count 0 2006.286.01:53:34.01#ibcon#about to write, iclass 25, count 0 2006.286.01:53:34.01#ibcon#wrote, iclass 25, count 0 2006.286.01:53:34.01#ibcon#about to read 3, iclass 25, count 0 2006.286.01:53:34.03#ibcon#read 3, iclass 25, count 0 2006.286.01:53:34.03#ibcon#about to read 4, iclass 25, count 0 2006.286.01:53:34.03#ibcon#read 4, iclass 25, count 0 2006.286.01:53:34.03#ibcon#about to read 5, iclass 25, count 0 2006.286.01:53:34.03#ibcon#read 5, iclass 25, count 0 2006.286.01:53:34.03#ibcon#about to read 6, iclass 25, count 0 2006.286.01:53:34.03#ibcon#read 6, iclass 25, count 0 2006.286.01:53:34.03#ibcon#end of sib2, iclass 25, count 0 2006.286.01:53:34.03#ibcon#*mode == 0, iclass 25, count 0 2006.286.01:53:34.03#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.01:53:34.03#ibcon#[25=USB\r\n] 2006.286.01:53:34.03#ibcon#*before write, iclass 25, count 0 2006.286.01:53:34.03#ibcon#enter sib2, iclass 25, count 0 2006.286.01:53:34.03#ibcon#flushed, iclass 25, count 0 2006.286.01:53:34.03#ibcon#about to write, iclass 25, count 0 2006.286.01:53:34.03#ibcon#wrote, iclass 25, count 0 2006.286.01:53:34.03#ibcon#about to read 3, iclass 25, count 0 2006.286.01:53:34.06#ibcon#read 3, iclass 25, count 0 2006.286.01:53:34.06#ibcon#about to read 4, iclass 25, count 0 2006.286.01:53:34.06#ibcon#read 4, iclass 25, count 0 2006.286.01:53:34.06#ibcon#about to read 5, iclass 25, count 0 2006.286.01:53:34.06#ibcon#read 5, iclass 25, count 0 2006.286.01:53:34.06#ibcon#about to read 6, iclass 25, count 0 2006.286.01:53:34.06#ibcon#read 6, iclass 25, count 0 2006.286.01:53:34.06#ibcon#end of sib2, iclass 25, count 0 2006.286.01:53:34.06#ibcon#*after write, iclass 25, count 0 2006.286.01:53:34.06#ibcon#*before return 0, iclass 25, count 0 2006.286.01:53:34.06#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:53:34.06#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:53:34.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.01:53:34.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.01:53:34.06$vck44/valo=8,884.99 2006.286.01:53:34.06#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.01:53:34.06#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.01:53:34.06#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:34.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:53:34.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:53:34.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:53:34.06#ibcon#enter wrdev, iclass 27, count 0 2006.286.01:53:34.06#ibcon#first serial, iclass 27, count 0 2006.286.01:53:34.06#ibcon#enter sib2, iclass 27, count 0 2006.286.01:53:34.06#ibcon#flushed, iclass 27, count 0 2006.286.01:53:34.06#ibcon#about to write, iclass 27, count 0 2006.286.01:53:34.06#ibcon#wrote, iclass 27, count 0 2006.286.01:53:34.06#ibcon#about to read 3, iclass 27, count 0 2006.286.01:53:34.08#ibcon#read 3, iclass 27, count 0 2006.286.01:53:34.08#ibcon#about to read 4, iclass 27, count 0 2006.286.01:53:34.08#ibcon#read 4, iclass 27, count 0 2006.286.01:53:34.08#ibcon#about to read 5, iclass 27, count 0 2006.286.01:53:34.08#ibcon#read 5, iclass 27, count 0 2006.286.01:53:34.08#ibcon#about to read 6, iclass 27, count 0 2006.286.01:53:34.08#ibcon#read 6, iclass 27, count 0 2006.286.01:53:34.08#ibcon#end of sib2, iclass 27, count 0 2006.286.01:53:34.08#ibcon#*mode == 0, iclass 27, count 0 2006.286.01:53:34.08#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.01:53:34.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:53:34.08#ibcon#*before write, iclass 27, count 0 2006.286.01:53:34.08#ibcon#enter sib2, iclass 27, count 0 2006.286.01:53:34.08#ibcon#flushed, iclass 27, count 0 2006.286.01:53:34.08#ibcon#about to write, iclass 27, count 0 2006.286.01:53:34.08#ibcon#wrote, iclass 27, count 0 2006.286.01:53:34.08#ibcon#about to read 3, iclass 27, count 0 2006.286.01:53:34.12#ibcon#read 3, iclass 27, count 0 2006.286.01:53:34.12#ibcon#about to read 4, iclass 27, count 0 2006.286.01:53:34.12#ibcon#read 4, iclass 27, count 0 2006.286.01:53:34.12#ibcon#about to read 5, iclass 27, count 0 2006.286.01:53:34.12#ibcon#read 5, iclass 27, count 0 2006.286.01:53:34.12#ibcon#about to read 6, iclass 27, count 0 2006.286.01:53:34.12#ibcon#read 6, iclass 27, count 0 2006.286.01:53:34.12#ibcon#end of sib2, iclass 27, count 0 2006.286.01:53:34.12#ibcon#*after write, iclass 27, count 0 2006.286.01:53:34.12#ibcon#*before return 0, iclass 27, count 0 2006.286.01:53:34.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:53:34.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:53:34.12#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.01:53:34.12#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.01:53:34.12$vck44/va=8,3 2006.286.01:53:34.12#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.01:53:34.12#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.01:53:34.12#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:34.12#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:53:34.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:53:34.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:53:34.18#ibcon#enter wrdev, iclass 29, count 2 2006.286.01:53:34.18#ibcon#first serial, iclass 29, count 2 2006.286.01:53:34.18#ibcon#enter sib2, iclass 29, count 2 2006.286.01:53:34.18#ibcon#flushed, iclass 29, count 2 2006.286.01:53:34.18#ibcon#about to write, iclass 29, count 2 2006.286.01:53:34.18#ibcon#wrote, iclass 29, count 2 2006.286.01:53:34.18#ibcon#about to read 3, iclass 29, count 2 2006.286.01:53:34.20#ibcon#read 3, iclass 29, count 2 2006.286.01:53:34.20#ibcon#about to read 4, iclass 29, count 2 2006.286.01:53:34.20#ibcon#read 4, iclass 29, count 2 2006.286.01:53:34.20#ibcon#about to read 5, iclass 29, count 2 2006.286.01:53:34.20#ibcon#read 5, iclass 29, count 2 2006.286.01:53:34.20#ibcon#about to read 6, iclass 29, count 2 2006.286.01:53:34.20#ibcon#read 6, iclass 29, count 2 2006.286.01:53:34.20#ibcon#end of sib2, iclass 29, count 2 2006.286.01:53:34.20#ibcon#*mode == 0, iclass 29, count 2 2006.286.01:53:34.20#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.01:53:34.20#ibcon#[25=AT08-03\r\n] 2006.286.01:53:34.20#ibcon#*before write, iclass 29, count 2 2006.286.01:53:34.20#ibcon#enter sib2, iclass 29, count 2 2006.286.01:53:34.20#ibcon#flushed, iclass 29, count 2 2006.286.01:53:34.20#ibcon#about to write, iclass 29, count 2 2006.286.01:53:34.20#ibcon#wrote, iclass 29, count 2 2006.286.01:53:34.20#ibcon#about to read 3, iclass 29, count 2 2006.286.01:53:34.23#ibcon#read 3, iclass 29, count 2 2006.286.01:53:34.23#ibcon#about to read 4, iclass 29, count 2 2006.286.01:53:34.23#ibcon#read 4, iclass 29, count 2 2006.286.01:53:34.23#ibcon#about to read 5, iclass 29, count 2 2006.286.01:53:34.23#ibcon#read 5, iclass 29, count 2 2006.286.01:53:34.23#ibcon#about to read 6, iclass 29, count 2 2006.286.01:53:34.23#ibcon#read 6, iclass 29, count 2 2006.286.01:53:34.23#ibcon#end of sib2, iclass 29, count 2 2006.286.01:53:34.23#ibcon#*after write, iclass 29, count 2 2006.286.01:53:34.23#ibcon#*before return 0, iclass 29, count 2 2006.286.01:53:34.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:53:34.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:53:34.23#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.01:53:34.23#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:34.23#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:53:34.24#abcon#<5=/03 3.9 7.1 21.21 781016.0\r\n> 2006.286.01:53:34.26#abcon#{5=INTERFACE CLEAR} 2006.286.01:53:34.32#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:53:34.35#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:53:34.35#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:53:34.35#ibcon#enter wrdev, iclass 29, count 0 2006.286.01:53:34.35#ibcon#first serial, iclass 29, count 0 2006.286.01:53:34.35#ibcon#enter sib2, iclass 29, count 0 2006.286.01:53:34.35#ibcon#flushed, iclass 29, count 0 2006.286.01:53:34.35#ibcon#about to write, iclass 29, count 0 2006.286.01:53:34.35#ibcon#wrote, iclass 29, count 0 2006.286.01:53:34.35#ibcon#about to read 3, iclass 29, count 0 2006.286.01:53:34.37#ibcon#read 3, iclass 29, count 0 2006.286.01:53:34.37#ibcon#about to read 4, iclass 29, count 0 2006.286.01:53:34.37#ibcon#read 4, iclass 29, count 0 2006.286.01:53:34.37#ibcon#about to read 5, iclass 29, count 0 2006.286.01:53:34.37#ibcon#read 5, iclass 29, count 0 2006.286.01:53:34.37#ibcon#about to read 6, iclass 29, count 0 2006.286.01:53:34.37#ibcon#read 6, iclass 29, count 0 2006.286.01:53:34.37#ibcon#end of sib2, iclass 29, count 0 2006.286.01:53:34.37#ibcon#*mode == 0, iclass 29, count 0 2006.286.01:53:34.37#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.01:53:34.37#ibcon#[25=USB\r\n] 2006.286.01:53:34.37#ibcon#*before write, iclass 29, count 0 2006.286.01:53:34.37#ibcon#enter sib2, iclass 29, count 0 2006.286.01:53:34.37#ibcon#flushed, iclass 29, count 0 2006.286.01:53:34.37#ibcon#about to write, iclass 29, count 0 2006.286.01:53:34.37#ibcon#wrote, iclass 29, count 0 2006.286.01:53:34.37#ibcon#about to read 3, iclass 29, count 0 2006.286.01:53:34.40#ibcon#read 3, iclass 29, count 0 2006.286.01:53:34.40#ibcon#about to read 4, iclass 29, count 0 2006.286.01:53:34.40#ibcon#read 4, iclass 29, count 0 2006.286.01:53:34.40#ibcon#about to read 5, iclass 29, count 0 2006.286.01:53:34.40#ibcon#read 5, iclass 29, count 0 2006.286.01:53:34.40#ibcon#about to read 6, iclass 29, count 0 2006.286.01:53:34.40#ibcon#read 6, iclass 29, count 0 2006.286.01:53:34.40#ibcon#end of sib2, iclass 29, count 0 2006.286.01:53:34.40#ibcon#*after write, iclass 29, count 0 2006.286.01:53:34.40#ibcon#*before return 0, iclass 29, count 0 2006.286.01:53:34.40#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:53:34.40#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:53:34.40#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.01:53:34.40#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.01:53:34.40$vck44/vblo=1,629.99 2006.286.01:53:34.40#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.01:53:34.40#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.01:53:34.40#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:34.40#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:53:34.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:53:34.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:53:34.40#ibcon#enter wrdev, iclass 35, count 0 2006.286.01:53:34.40#ibcon#first serial, iclass 35, count 0 2006.286.01:53:34.40#ibcon#enter sib2, iclass 35, count 0 2006.286.01:53:34.40#ibcon#flushed, iclass 35, count 0 2006.286.01:53:34.40#ibcon#about to write, iclass 35, count 0 2006.286.01:53:34.40#ibcon#wrote, iclass 35, count 0 2006.286.01:53:34.40#ibcon#about to read 3, iclass 35, count 0 2006.286.01:53:34.42#ibcon#read 3, iclass 35, count 0 2006.286.01:53:34.42#ibcon#about to read 4, iclass 35, count 0 2006.286.01:53:34.42#ibcon#read 4, iclass 35, count 0 2006.286.01:53:34.42#ibcon#about to read 5, iclass 35, count 0 2006.286.01:53:34.42#ibcon#read 5, iclass 35, count 0 2006.286.01:53:34.42#ibcon#about to read 6, iclass 35, count 0 2006.286.01:53:34.42#ibcon#read 6, iclass 35, count 0 2006.286.01:53:34.42#ibcon#end of sib2, iclass 35, count 0 2006.286.01:53:34.42#ibcon#*mode == 0, iclass 35, count 0 2006.286.01:53:34.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.01:53:34.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:53:34.42#ibcon#*before write, iclass 35, count 0 2006.286.01:53:34.42#ibcon#enter sib2, iclass 35, count 0 2006.286.01:53:34.42#ibcon#flushed, iclass 35, count 0 2006.286.01:53:34.42#ibcon#about to write, iclass 35, count 0 2006.286.01:53:34.42#ibcon#wrote, iclass 35, count 0 2006.286.01:53:34.42#ibcon#about to read 3, iclass 35, count 0 2006.286.01:53:34.46#ibcon#read 3, iclass 35, count 0 2006.286.01:53:34.46#ibcon#about to read 4, iclass 35, count 0 2006.286.01:53:34.46#ibcon#read 4, iclass 35, count 0 2006.286.01:53:34.46#ibcon#about to read 5, iclass 35, count 0 2006.286.01:53:34.46#ibcon#read 5, iclass 35, count 0 2006.286.01:53:34.46#ibcon#about to read 6, iclass 35, count 0 2006.286.01:53:34.46#ibcon#read 6, iclass 35, count 0 2006.286.01:53:34.46#ibcon#end of sib2, iclass 35, count 0 2006.286.01:53:34.46#ibcon#*after write, iclass 35, count 0 2006.286.01:53:34.46#ibcon#*before return 0, iclass 35, count 0 2006.286.01:53:34.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:53:34.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.01:53:34.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.01:53:34.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.01:53:34.46$vck44/vb=1,4 2006.286.01:53:34.46#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.01:53:34.46#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.01:53:34.46#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:34.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:53:34.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:53:34.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:53:34.46#ibcon#enter wrdev, iclass 37, count 2 2006.286.01:53:34.46#ibcon#first serial, iclass 37, count 2 2006.286.01:53:34.46#ibcon#enter sib2, iclass 37, count 2 2006.286.01:53:34.46#ibcon#flushed, iclass 37, count 2 2006.286.01:53:34.46#ibcon#about to write, iclass 37, count 2 2006.286.01:53:34.46#ibcon#wrote, iclass 37, count 2 2006.286.01:53:34.46#ibcon#about to read 3, iclass 37, count 2 2006.286.01:53:34.48#ibcon#read 3, iclass 37, count 2 2006.286.01:53:34.48#ibcon#about to read 4, iclass 37, count 2 2006.286.01:53:34.48#ibcon#read 4, iclass 37, count 2 2006.286.01:53:34.48#ibcon#about to read 5, iclass 37, count 2 2006.286.01:53:34.48#ibcon#read 5, iclass 37, count 2 2006.286.01:53:34.48#ibcon#about to read 6, iclass 37, count 2 2006.286.01:53:34.48#ibcon#read 6, iclass 37, count 2 2006.286.01:53:34.48#ibcon#end of sib2, iclass 37, count 2 2006.286.01:53:34.48#ibcon#*mode == 0, iclass 37, count 2 2006.286.01:53:34.48#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.01:53:34.48#ibcon#[27=AT01-04\r\n] 2006.286.01:53:34.48#ibcon#*before write, iclass 37, count 2 2006.286.01:53:34.48#ibcon#enter sib2, iclass 37, count 2 2006.286.01:53:34.48#ibcon#flushed, iclass 37, count 2 2006.286.01:53:34.48#ibcon#about to write, iclass 37, count 2 2006.286.01:53:34.48#ibcon#wrote, iclass 37, count 2 2006.286.01:53:34.48#ibcon#about to read 3, iclass 37, count 2 2006.286.01:53:34.51#ibcon#read 3, iclass 37, count 2 2006.286.01:53:34.51#ibcon#about to read 4, iclass 37, count 2 2006.286.01:53:34.51#ibcon#read 4, iclass 37, count 2 2006.286.01:53:34.51#ibcon#about to read 5, iclass 37, count 2 2006.286.01:53:34.51#ibcon#read 5, iclass 37, count 2 2006.286.01:53:34.51#ibcon#about to read 6, iclass 37, count 2 2006.286.01:53:34.51#ibcon#read 6, iclass 37, count 2 2006.286.01:53:34.51#ibcon#end of sib2, iclass 37, count 2 2006.286.01:53:34.51#ibcon#*after write, iclass 37, count 2 2006.286.01:53:34.51#ibcon#*before return 0, iclass 37, count 2 2006.286.01:53:34.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:53:34.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.01:53:34.51#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.01:53:34.51#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:34.51#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:53:34.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:53:34.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:53:34.63#ibcon#enter wrdev, iclass 37, count 0 2006.286.01:53:34.63#ibcon#first serial, iclass 37, count 0 2006.286.01:53:34.63#ibcon#enter sib2, iclass 37, count 0 2006.286.01:53:34.63#ibcon#flushed, iclass 37, count 0 2006.286.01:53:34.63#ibcon#about to write, iclass 37, count 0 2006.286.01:53:34.63#ibcon#wrote, iclass 37, count 0 2006.286.01:53:34.63#ibcon#about to read 3, iclass 37, count 0 2006.286.01:53:34.65#ibcon#read 3, iclass 37, count 0 2006.286.01:53:34.65#ibcon#about to read 4, iclass 37, count 0 2006.286.01:53:34.65#ibcon#read 4, iclass 37, count 0 2006.286.01:53:34.65#ibcon#about to read 5, iclass 37, count 0 2006.286.01:53:34.65#ibcon#read 5, iclass 37, count 0 2006.286.01:53:34.65#ibcon#about to read 6, iclass 37, count 0 2006.286.01:53:34.65#ibcon#read 6, iclass 37, count 0 2006.286.01:53:34.65#ibcon#end of sib2, iclass 37, count 0 2006.286.01:53:34.65#ibcon#*mode == 0, iclass 37, count 0 2006.286.01:53:34.65#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.01:53:34.65#ibcon#[27=USB\r\n] 2006.286.01:53:34.65#ibcon#*before write, iclass 37, count 0 2006.286.01:53:34.65#ibcon#enter sib2, iclass 37, count 0 2006.286.01:53:34.65#ibcon#flushed, iclass 37, count 0 2006.286.01:53:34.65#ibcon#about to write, iclass 37, count 0 2006.286.01:53:34.65#ibcon#wrote, iclass 37, count 0 2006.286.01:53:34.65#ibcon#about to read 3, iclass 37, count 0 2006.286.01:53:34.68#ibcon#read 3, iclass 37, count 0 2006.286.01:53:34.68#ibcon#about to read 4, iclass 37, count 0 2006.286.01:53:34.68#ibcon#read 4, iclass 37, count 0 2006.286.01:53:34.68#ibcon#about to read 5, iclass 37, count 0 2006.286.01:53:34.68#ibcon#read 5, iclass 37, count 0 2006.286.01:53:34.68#ibcon#about to read 6, iclass 37, count 0 2006.286.01:53:34.68#ibcon#read 6, iclass 37, count 0 2006.286.01:53:34.68#ibcon#end of sib2, iclass 37, count 0 2006.286.01:53:34.68#ibcon#*after write, iclass 37, count 0 2006.286.01:53:34.68#ibcon#*before return 0, iclass 37, count 0 2006.286.01:53:34.68#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:53:34.68#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.01:53:34.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.01:53:34.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.01:53:34.68$vck44/vblo=2,634.99 2006.286.01:53:34.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.01:53:34.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.01:53:34.68#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:34.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:53:34.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:53:34.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:53:34.68#ibcon#enter wrdev, iclass 39, count 0 2006.286.01:53:34.68#ibcon#first serial, iclass 39, count 0 2006.286.01:53:34.68#ibcon#enter sib2, iclass 39, count 0 2006.286.01:53:34.68#ibcon#flushed, iclass 39, count 0 2006.286.01:53:34.68#ibcon#about to write, iclass 39, count 0 2006.286.01:53:34.68#ibcon#wrote, iclass 39, count 0 2006.286.01:53:34.68#ibcon#about to read 3, iclass 39, count 0 2006.286.01:53:34.70#ibcon#read 3, iclass 39, count 0 2006.286.01:53:34.70#ibcon#about to read 4, iclass 39, count 0 2006.286.01:53:34.70#ibcon#read 4, iclass 39, count 0 2006.286.01:53:34.70#ibcon#about to read 5, iclass 39, count 0 2006.286.01:53:34.70#ibcon#read 5, iclass 39, count 0 2006.286.01:53:34.70#ibcon#about to read 6, iclass 39, count 0 2006.286.01:53:34.70#ibcon#read 6, iclass 39, count 0 2006.286.01:53:34.70#ibcon#end of sib2, iclass 39, count 0 2006.286.01:53:34.70#ibcon#*mode == 0, iclass 39, count 0 2006.286.01:53:34.70#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.01:53:34.70#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:53:34.70#ibcon#*before write, iclass 39, count 0 2006.286.01:53:34.70#ibcon#enter sib2, iclass 39, count 0 2006.286.01:53:34.70#ibcon#flushed, iclass 39, count 0 2006.286.01:53:34.70#ibcon#about to write, iclass 39, count 0 2006.286.01:53:34.70#ibcon#wrote, iclass 39, count 0 2006.286.01:53:34.70#ibcon#about to read 3, iclass 39, count 0 2006.286.01:53:34.74#ibcon#read 3, iclass 39, count 0 2006.286.01:53:34.74#ibcon#about to read 4, iclass 39, count 0 2006.286.01:53:34.74#ibcon#read 4, iclass 39, count 0 2006.286.01:53:34.74#ibcon#about to read 5, iclass 39, count 0 2006.286.01:53:34.74#ibcon#read 5, iclass 39, count 0 2006.286.01:53:34.74#ibcon#about to read 6, iclass 39, count 0 2006.286.01:53:34.74#ibcon#read 6, iclass 39, count 0 2006.286.01:53:34.74#ibcon#end of sib2, iclass 39, count 0 2006.286.01:53:34.74#ibcon#*after write, iclass 39, count 0 2006.286.01:53:34.74#ibcon#*before return 0, iclass 39, count 0 2006.286.01:53:34.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:53:34.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.01:53:34.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.01:53:34.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.01:53:34.74$vck44/vb=2,5 2006.286.01:53:34.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.01:53:34.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.01:53:34.74#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:34.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:53:34.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:53:34.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:53:34.80#ibcon#enter wrdev, iclass 3, count 2 2006.286.01:53:34.80#ibcon#first serial, iclass 3, count 2 2006.286.01:53:34.80#ibcon#enter sib2, iclass 3, count 2 2006.286.01:53:34.80#ibcon#flushed, iclass 3, count 2 2006.286.01:53:34.80#ibcon#about to write, iclass 3, count 2 2006.286.01:53:34.80#ibcon#wrote, iclass 3, count 2 2006.286.01:53:34.80#ibcon#about to read 3, iclass 3, count 2 2006.286.01:53:34.82#ibcon#read 3, iclass 3, count 2 2006.286.01:53:34.82#ibcon#about to read 4, iclass 3, count 2 2006.286.01:53:34.82#ibcon#read 4, iclass 3, count 2 2006.286.01:53:34.82#ibcon#about to read 5, iclass 3, count 2 2006.286.01:53:34.82#ibcon#read 5, iclass 3, count 2 2006.286.01:53:34.82#ibcon#about to read 6, iclass 3, count 2 2006.286.01:53:34.82#ibcon#read 6, iclass 3, count 2 2006.286.01:53:34.82#ibcon#end of sib2, iclass 3, count 2 2006.286.01:53:34.82#ibcon#*mode == 0, iclass 3, count 2 2006.286.01:53:34.82#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.01:53:34.82#ibcon#[27=AT02-05\r\n] 2006.286.01:53:34.82#ibcon#*before write, iclass 3, count 2 2006.286.01:53:34.82#ibcon#enter sib2, iclass 3, count 2 2006.286.01:53:34.82#ibcon#flushed, iclass 3, count 2 2006.286.01:53:34.82#ibcon#about to write, iclass 3, count 2 2006.286.01:53:34.82#ibcon#wrote, iclass 3, count 2 2006.286.01:53:34.82#ibcon#about to read 3, iclass 3, count 2 2006.286.01:53:34.85#ibcon#read 3, iclass 3, count 2 2006.286.01:53:34.85#ibcon#about to read 4, iclass 3, count 2 2006.286.01:53:34.85#ibcon#read 4, iclass 3, count 2 2006.286.01:53:34.85#ibcon#about to read 5, iclass 3, count 2 2006.286.01:53:34.85#ibcon#read 5, iclass 3, count 2 2006.286.01:53:34.85#ibcon#about to read 6, iclass 3, count 2 2006.286.01:53:34.85#ibcon#read 6, iclass 3, count 2 2006.286.01:53:34.85#ibcon#end of sib2, iclass 3, count 2 2006.286.01:53:34.85#ibcon#*after write, iclass 3, count 2 2006.286.01:53:34.85#ibcon#*before return 0, iclass 3, count 2 2006.286.01:53:34.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:53:34.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.01:53:34.85#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.01:53:34.85#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:34.85#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:53:34.97#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:53:34.97#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:53:34.97#ibcon#enter wrdev, iclass 3, count 0 2006.286.01:53:34.97#ibcon#first serial, iclass 3, count 0 2006.286.01:53:34.97#ibcon#enter sib2, iclass 3, count 0 2006.286.01:53:34.97#ibcon#flushed, iclass 3, count 0 2006.286.01:53:34.97#ibcon#about to write, iclass 3, count 0 2006.286.01:53:34.97#ibcon#wrote, iclass 3, count 0 2006.286.01:53:34.97#ibcon#about to read 3, iclass 3, count 0 2006.286.01:53:34.99#ibcon#read 3, iclass 3, count 0 2006.286.01:53:34.99#ibcon#about to read 4, iclass 3, count 0 2006.286.01:53:34.99#ibcon#read 4, iclass 3, count 0 2006.286.01:53:34.99#ibcon#about to read 5, iclass 3, count 0 2006.286.01:53:34.99#ibcon#read 5, iclass 3, count 0 2006.286.01:53:34.99#ibcon#about to read 6, iclass 3, count 0 2006.286.01:53:34.99#ibcon#read 6, iclass 3, count 0 2006.286.01:53:34.99#ibcon#end of sib2, iclass 3, count 0 2006.286.01:53:34.99#ibcon#*mode == 0, iclass 3, count 0 2006.286.01:53:34.99#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.01:53:34.99#ibcon#[27=USB\r\n] 2006.286.01:53:34.99#ibcon#*before write, iclass 3, count 0 2006.286.01:53:34.99#ibcon#enter sib2, iclass 3, count 0 2006.286.01:53:34.99#ibcon#flushed, iclass 3, count 0 2006.286.01:53:34.99#ibcon#about to write, iclass 3, count 0 2006.286.01:53:34.99#ibcon#wrote, iclass 3, count 0 2006.286.01:53:34.99#ibcon#about to read 3, iclass 3, count 0 2006.286.01:53:35.02#ibcon#read 3, iclass 3, count 0 2006.286.01:53:35.02#ibcon#about to read 4, iclass 3, count 0 2006.286.01:53:35.02#ibcon#read 4, iclass 3, count 0 2006.286.01:53:35.02#ibcon#about to read 5, iclass 3, count 0 2006.286.01:53:35.02#ibcon#read 5, iclass 3, count 0 2006.286.01:53:35.02#ibcon#about to read 6, iclass 3, count 0 2006.286.01:53:35.02#ibcon#read 6, iclass 3, count 0 2006.286.01:53:35.02#ibcon#end of sib2, iclass 3, count 0 2006.286.01:53:35.02#ibcon#*after write, iclass 3, count 0 2006.286.01:53:35.02#ibcon#*before return 0, iclass 3, count 0 2006.286.01:53:35.02#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:53:35.02#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.01:53:35.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.01:53:35.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.01:53:35.02$vck44/vblo=3,649.99 2006.286.01:53:35.02#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.01:53:35.02#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.01:53:35.02#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:35.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:53:35.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:53:35.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:53:35.02#ibcon#enter wrdev, iclass 5, count 0 2006.286.01:53:35.02#ibcon#first serial, iclass 5, count 0 2006.286.01:53:35.02#ibcon#enter sib2, iclass 5, count 0 2006.286.01:53:35.02#ibcon#flushed, iclass 5, count 0 2006.286.01:53:35.02#ibcon#about to write, iclass 5, count 0 2006.286.01:53:35.02#ibcon#wrote, iclass 5, count 0 2006.286.01:53:35.02#ibcon#about to read 3, iclass 5, count 0 2006.286.01:53:35.04#ibcon#read 3, iclass 5, count 0 2006.286.01:53:35.04#ibcon#about to read 4, iclass 5, count 0 2006.286.01:53:35.04#ibcon#read 4, iclass 5, count 0 2006.286.01:53:35.04#ibcon#about to read 5, iclass 5, count 0 2006.286.01:53:35.04#ibcon#read 5, iclass 5, count 0 2006.286.01:53:35.04#ibcon#about to read 6, iclass 5, count 0 2006.286.01:53:35.04#ibcon#read 6, iclass 5, count 0 2006.286.01:53:35.04#ibcon#end of sib2, iclass 5, count 0 2006.286.01:53:35.04#ibcon#*mode == 0, iclass 5, count 0 2006.286.01:53:35.04#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.01:53:35.04#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:53:35.04#ibcon#*before write, iclass 5, count 0 2006.286.01:53:35.04#ibcon#enter sib2, iclass 5, count 0 2006.286.01:53:35.04#ibcon#flushed, iclass 5, count 0 2006.286.01:53:35.04#ibcon#about to write, iclass 5, count 0 2006.286.01:53:35.04#ibcon#wrote, iclass 5, count 0 2006.286.01:53:35.04#ibcon#about to read 3, iclass 5, count 0 2006.286.01:53:35.08#ibcon#read 3, iclass 5, count 0 2006.286.01:53:35.08#ibcon#about to read 4, iclass 5, count 0 2006.286.01:53:35.08#ibcon#read 4, iclass 5, count 0 2006.286.01:53:35.08#ibcon#about to read 5, iclass 5, count 0 2006.286.01:53:35.08#ibcon#read 5, iclass 5, count 0 2006.286.01:53:35.08#ibcon#about to read 6, iclass 5, count 0 2006.286.01:53:35.08#ibcon#read 6, iclass 5, count 0 2006.286.01:53:35.08#ibcon#end of sib2, iclass 5, count 0 2006.286.01:53:35.08#ibcon#*after write, iclass 5, count 0 2006.286.01:53:35.08#ibcon#*before return 0, iclass 5, count 0 2006.286.01:53:35.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:53:35.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.01:53:35.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.01:53:35.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.01:53:35.08$vck44/vb=3,4 2006.286.01:53:35.08#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.01:53:35.08#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.01:53:35.08#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:35.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:53:35.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:53:35.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:53:35.14#ibcon#enter wrdev, iclass 7, count 2 2006.286.01:53:35.14#ibcon#first serial, iclass 7, count 2 2006.286.01:53:35.14#ibcon#enter sib2, iclass 7, count 2 2006.286.01:53:35.14#ibcon#flushed, iclass 7, count 2 2006.286.01:53:35.14#ibcon#about to write, iclass 7, count 2 2006.286.01:53:35.14#ibcon#wrote, iclass 7, count 2 2006.286.01:53:35.14#ibcon#about to read 3, iclass 7, count 2 2006.286.01:53:35.16#ibcon#read 3, iclass 7, count 2 2006.286.01:53:35.16#ibcon#about to read 4, iclass 7, count 2 2006.286.01:53:35.16#ibcon#read 4, iclass 7, count 2 2006.286.01:53:35.16#ibcon#about to read 5, iclass 7, count 2 2006.286.01:53:35.16#ibcon#read 5, iclass 7, count 2 2006.286.01:53:35.16#ibcon#about to read 6, iclass 7, count 2 2006.286.01:53:35.16#ibcon#read 6, iclass 7, count 2 2006.286.01:53:35.16#ibcon#end of sib2, iclass 7, count 2 2006.286.01:53:35.16#ibcon#*mode == 0, iclass 7, count 2 2006.286.01:53:35.16#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.01:53:35.16#ibcon#[27=AT03-04\r\n] 2006.286.01:53:35.16#ibcon#*before write, iclass 7, count 2 2006.286.01:53:35.16#ibcon#enter sib2, iclass 7, count 2 2006.286.01:53:35.16#ibcon#flushed, iclass 7, count 2 2006.286.01:53:35.16#ibcon#about to write, iclass 7, count 2 2006.286.01:53:35.16#ibcon#wrote, iclass 7, count 2 2006.286.01:53:35.16#ibcon#about to read 3, iclass 7, count 2 2006.286.01:53:35.19#ibcon#read 3, iclass 7, count 2 2006.286.01:53:35.19#ibcon#about to read 4, iclass 7, count 2 2006.286.01:53:35.19#ibcon#read 4, iclass 7, count 2 2006.286.01:53:35.19#ibcon#about to read 5, iclass 7, count 2 2006.286.01:53:35.19#ibcon#read 5, iclass 7, count 2 2006.286.01:53:35.19#ibcon#about to read 6, iclass 7, count 2 2006.286.01:53:35.19#ibcon#read 6, iclass 7, count 2 2006.286.01:53:35.19#ibcon#end of sib2, iclass 7, count 2 2006.286.01:53:35.19#ibcon#*after write, iclass 7, count 2 2006.286.01:53:35.19#ibcon#*before return 0, iclass 7, count 2 2006.286.01:53:35.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:53:35.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.01:53:35.19#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.01:53:35.19#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:35.19#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:53:35.31#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:53:35.31#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:53:35.31#ibcon#enter wrdev, iclass 7, count 0 2006.286.01:53:35.31#ibcon#first serial, iclass 7, count 0 2006.286.01:53:35.31#ibcon#enter sib2, iclass 7, count 0 2006.286.01:53:35.31#ibcon#flushed, iclass 7, count 0 2006.286.01:53:35.31#ibcon#about to write, iclass 7, count 0 2006.286.01:53:35.31#ibcon#wrote, iclass 7, count 0 2006.286.01:53:35.31#ibcon#about to read 3, iclass 7, count 0 2006.286.01:53:35.33#ibcon#read 3, iclass 7, count 0 2006.286.01:53:35.33#ibcon#about to read 4, iclass 7, count 0 2006.286.01:53:35.33#ibcon#read 4, iclass 7, count 0 2006.286.01:53:35.33#ibcon#about to read 5, iclass 7, count 0 2006.286.01:53:35.33#ibcon#read 5, iclass 7, count 0 2006.286.01:53:35.33#ibcon#about to read 6, iclass 7, count 0 2006.286.01:53:35.33#ibcon#read 6, iclass 7, count 0 2006.286.01:53:35.33#ibcon#end of sib2, iclass 7, count 0 2006.286.01:53:35.33#ibcon#*mode == 0, iclass 7, count 0 2006.286.01:53:35.33#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.01:53:35.33#ibcon#[27=USB\r\n] 2006.286.01:53:35.33#ibcon#*before write, iclass 7, count 0 2006.286.01:53:35.33#ibcon#enter sib2, iclass 7, count 0 2006.286.01:53:35.33#ibcon#flushed, iclass 7, count 0 2006.286.01:53:35.33#ibcon#about to write, iclass 7, count 0 2006.286.01:53:35.33#ibcon#wrote, iclass 7, count 0 2006.286.01:53:35.33#ibcon#about to read 3, iclass 7, count 0 2006.286.01:53:35.36#ibcon#read 3, iclass 7, count 0 2006.286.01:53:35.36#ibcon#about to read 4, iclass 7, count 0 2006.286.01:53:35.36#ibcon#read 4, iclass 7, count 0 2006.286.01:53:35.36#ibcon#about to read 5, iclass 7, count 0 2006.286.01:53:35.36#ibcon#read 5, iclass 7, count 0 2006.286.01:53:35.36#ibcon#about to read 6, iclass 7, count 0 2006.286.01:53:35.36#ibcon#read 6, iclass 7, count 0 2006.286.01:53:35.36#ibcon#end of sib2, iclass 7, count 0 2006.286.01:53:35.36#ibcon#*after write, iclass 7, count 0 2006.286.01:53:35.36#ibcon#*before return 0, iclass 7, count 0 2006.286.01:53:35.36#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:53:35.36#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.01:53:35.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.01:53:35.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.01:53:35.36$vck44/vblo=4,679.99 2006.286.01:53:35.36#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.01:53:35.36#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.01:53:35.36#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:35.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:53:35.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:53:35.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:53:35.36#ibcon#enter wrdev, iclass 11, count 0 2006.286.01:53:35.36#ibcon#first serial, iclass 11, count 0 2006.286.01:53:35.36#ibcon#enter sib2, iclass 11, count 0 2006.286.01:53:35.36#ibcon#flushed, iclass 11, count 0 2006.286.01:53:35.36#ibcon#about to write, iclass 11, count 0 2006.286.01:53:35.36#ibcon#wrote, iclass 11, count 0 2006.286.01:53:35.36#ibcon#about to read 3, iclass 11, count 0 2006.286.01:53:35.38#ibcon#read 3, iclass 11, count 0 2006.286.01:53:35.38#ibcon#about to read 4, iclass 11, count 0 2006.286.01:53:35.38#ibcon#read 4, iclass 11, count 0 2006.286.01:53:35.38#ibcon#about to read 5, iclass 11, count 0 2006.286.01:53:35.38#ibcon#read 5, iclass 11, count 0 2006.286.01:53:35.38#ibcon#about to read 6, iclass 11, count 0 2006.286.01:53:35.38#ibcon#read 6, iclass 11, count 0 2006.286.01:53:35.38#ibcon#end of sib2, iclass 11, count 0 2006.286.01:53:35.38#ibcon#*mode == 0, iclass 11, count 0 2006.286.01:53:35.38#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.01:53:35.38#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:53:35.38#ibcon#*before write, iclass 11, count 0 2006.286.01:53:35.38#ibcon#enter sib2, iclass 11, count 0 2006.286.01:53:35.38#ibcon#flushed, iclass 11, count 0 2006.286.01:53:35.38#ibcon#about to write, iclass 11, count 0 2006.286.01:53:35.38#ibcon#wrote, iclass 11, count 0 2006.286.01:53:35.38#ibcon#about to read 3, iclass 11, count 0 2006.286.01:53:35.42#ibcon#read 3, iclass 11, count 0 2006.286.01:53:35.42#ibcon#about to read 4, iclass 11, count 0 2006.286.01:53:35.42#ibcon#read 4, iclass 11, count 0 2006.286.01:53:35.42#ibcon#about to read 5, iclass 11, count 0 2006.286.01:53:35.42#ibcon#read 5, iclass 11, count 0 2006.286.01:53:35.42#ibcon#about to read 6, iclass 11, count 0 2006.286.01:53:35.42#ibcon#read 6, iclass 11, count 0 2006.286.01:53:35.42#ibcon#end of sib2, iclass 11, count 0 2006.286.01:53:35.42#ibcon#*after write, iclass 11, count 0 2006.286.01:53:35.42#ibcon#*before return 0, iclass 11, count 0 2006.286.01:53:35.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:53:35.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.01:53:35.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.01:53:35.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.01:53:35.42$vck44/vb=4,5 2006.286.01:53:35.42#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.01:53:35.42#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.01:53:35.42#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:35.42#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:53:35.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:53:35.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:53:35.48#ibcon#enter wrdev, iclass 13, count 2 2006.286.01:53:35.48#ibcon#first serial, iclass 13, count 2 2006.286.01:53:35.48#ibcon#enter sib2, iclass 13, count 2 2006.286.01:53:35.48#ibcon#flushed, iclass 13, count 2 2006.286.01:53:35.48#ibcon#about to write, iclass 13, count 2 2006.286.01:53:35.48#ibcon#wrote, iclass 13, count 2 2006.286.01:53:35.48#ibcon#about to read 3, iclass 13, count 2 2006.286.01:53:35.50#ibcon#read 3, iclass 13, count 2 2006.286.01:53:35.50#ibcon#about to read 4, iclass 13, count 2 2006.286.01:53:35.50#ibcon#read 4, iclass 13, count 2 2006.286.01:53:35.50#ibcon#about to read 5, iclass 13, count 2 2006.286.01:53:35.50#ibcon#read 5, iclass 13, count 2 2006.286.01:53:35.50#ibcon#about to read 6, iclass 13, count 2 2006.286.01:53:35.50#ibcon#read 6, iclass 13, count 2 2006.286.01:53:35.50#ibcon#end of sib2, iclass 13, count 2 2006.286.01:53:35.50#ibcon#*mode == 0, iclass 13, count 2 2006.286.01:53:35.50#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.01:53:35.50#ibcon#[27=AT04-05\r\n] 2006.286.01:53:35.50#ibcon#*before write, iclass 13, count 2 2006.286.01:53:35.50#ibcon#enter sib2, iclass 13, count 2 2006.286.01:53:35.50#ibcon#flushed, iclass 13, count 2 2006.286.01:53:35.50#ibcon#about to write, iclass 13, count 2 2006.286.01:53:35.50#ibcon#wrote, iclass 13, count 2 2006.286.01:53:35.50#ibcon#about to read 3, iclass 13, count 2 2006.286.01:53:35.53#ibcon#read 3, iclass 13, count 2 2006.286.01:53:35.53#ibcon#about to read 4, iclass 13, count 2 2006.286.01:53:35.53#ibcon#read 4, iclass 13, count 2 2006.286.01:53:35.53#ibcon#about to read 5, iclass 13, count 2 2006.286.01:53:35.53#ibcon#read 5, iclass 13, count 2 2006.286.01:53:35.53#ibcon#about to read 6, iclass 13, count 2 2006.286.01:53:35.53#ibcon#read 6, iclass 13, count 2 2006.286.01:53:35.53#ibcon#end of sib2, iclass 13, count 2 2006.286.01:53:35.53#ibcon#*after write, iclass 13, count 2 2006.286.01:53:35.53#ibcon#*before return 0, iclass 13, count 2 2006.286.01:53:35.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:53:35.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.01:53:35.53#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.01:53:35.53#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:35.53#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:53:35.65#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:53:35.65#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:53:35.65#ibcon#enter wrdev, iclass 13, count 0 2006.286.01:53:35.65#ibcon#first serial, iclass 13, count 0 2006.286.01:53:35.65#ibcon#enter sib2, iclass 13, count 0 2006.286.01:53:35.65#ibcon#flushed, iclass 13, count 0 2006.286.01:53:35.65#ibcon#about to write, iclass 13, count 0 2006.286.01:53:35.65#ibcon#wrote, iclass 13, count 0 2006.286.01:53:35.65#ibcon#about to read 3, iclass 13, count 0 2006.286.01:53:35.67#ibcon#read 3, iclass 13, count 0 2006.286.01:53:35.67#ibcon#about to read 4, iclass 13, count 0 2006.286.01:53:35.67#ibcon#read 4, iclass 13, count 0 2006.286.01:53:35.67#ibcon#about to read 5, iclass 13, count 0 2006.286.01:53:35.67#ibcon#read 5, iclass 13, count 0 2006.286.01:53:35.67#ibcon#about to read 6, iclass 13, count 0 2006.286.01:53:35.67#ibcon#read 6, iclass 13, count 0 2006.286.01:53:35.67#ibcon#end of sib2, iclass 13, count 0 2006.286.01:53:35.67#ibcon#*mode == 0, iclass 13, count 0 2006.286.01:53:35.67#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.01:53:35.67#ibcon#[27=USB\r\n] 2006.286.01:53:35.67#ibcon#*before write, iclass 13, count 0 2006.286.01:53:35.67#ibcon#enter sib2, iclass 13, count 0 2006.286.01:53:35.67#ibcon#flushed, iclass 13, count 0 2006.286.01:53:35.67#ibcon#about to write, iclass 13, count 0 2006.286.01:53:35.67#ibcon#wrote, iclass 13, count 0 2006.286.01:53:35.67#ibcon#about to read 3, iclass 13, count 0 2006.286.01:53:35.70#ibcon#read 3, iclass 13, count 0 2006.286.01:53:35.70#ibcon#about to read 4, iclass 13, count 0 2006.286.01:53:35.70#ibcon#read 4, iclass 13, count 0 2006.286.01:53:35.70#ibcon#about to read 5, iclass 13, count 0 2006.286.01:53:35.70#ibcon#read 5, iclass 13, count 0 2006.286.01:53:35.70#ibcon#about to read 6, iclass 13, count 0 2006.286.01:53:35.70#ibcon#read 6, iclass 13, count 0 2006.286.01:53:35.70#ibcon#end of sib2, iclass 13, count 0 2006.286.01:53:35.70#ibcon#*after write, iclass 13, count 0 2006.286.01:53:35.70#ibcon#*before return 0, iclass 13, count 0 2006.286.01:53:35.70#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:53:35.70#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.01:53:35.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.01:53:35.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.01:53:35.70$vck44/vblo=5,709.99 2006.286.01:53:35.70#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.01:53:35.70#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.01:53:35.70#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:35.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:53:35.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:53:35.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:53:35.70#ibcon#enter wrdev, iclass 15, count 0 2006.286.01:53:35.70#ibcon#first serial, iclass 15, count 0 2006.286.01:53:35.70#ibcon#enter sib2, iclass 15, count 0 2006.286.01:53:35.70#ibcon#flushed, iclass 15, count 0 2006.286.01:53:35.70#ibcon#about to write, iclass 15, count 0 2006.286.01:53:35.70#ibcon#wrote, iclass 15, count 0 2006.286.01:53:35.70#ibcon#about to read 3, iclass 15, count 0 2006.286.01:53:35.72#ibcon#read 3, iclass 15, count 0 2006.286.01:53:35.72#ibcon#about to read 4, iclass 15, count 0 2006.286.01:53:35.72#ibcon#read 4, iclass 15, count 0 2006.286.01:53:35.72#ibcon#about to read 5, iclass 15, count 0 2006.286.01:53:35.72#ibcon#read 5, iclass 15, count 0 2006.286.01:53:35.72#ibcon#about to read 6, iclass 15, count 0 2006.286.01:53:35.72#ibcon#read 6, iclass 15, count 0 2006.286.01:53:35.72#ibcon#end of sib2, iclass 15, count 0 2006.286.01:53:35.72#ibcon#*mode == 0, iclass 15, count 0 2006.286.01:53:35.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.01:53:35.72#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:53:35.72#ibcon#*before write, iclass 15, count 0 2006.286.01:53:35.72#ibcon#enter sib2, iclass 15, count 0 2006.286.01:53:35.72#ibcon#flushed, iclass 15, count 0 2006.286.01:53:35.72#ibcon#about to write, iclass 15, count 0 2006.286.01:53:35.72#ibcon#wrote, iclass 15, count 0 2006.286.01:53:35.72#ibcon#about to read 3, iclass 15, count 0 2006.286.01:53:35.76#ibcon#read 3, iclass 15, count 0 2006.286.01:53:35.76#ibcon#about to read 4, iclass 15, count 0 2006.286.01:53:35.76#ibcon#read 4, iclass 15, count 0 2006.286.01:53:35.76#ibcon#about to read 5, iclass 15, count 0 2006.286.01:53:35.76#ibcon#read 5, iclass 15, count 0 2006.286.01:53:35.76#ibcon#about to read 6, iclass 15, count 0 2006.286.01:53:35.76#ibcon#read 6, iclass 15, count 0 2006.286.01:53:35.76#ibcon#end of sib2, iclass 15, count 0 2006.286.01:53:35.76#ibcon#*after write, iclass 15, count 0 2006.286.01:53:35.76#ibcon#*before return 0, iclass 15, count 0 2006.286.01:53:35.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:53:35.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.01:53:35.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.01:53:35.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.01:53:35.76$vck44/vb=5,4 2006.286.01:53:35.76#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.01:53:35.76#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.01:53:35.76#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:35.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:53:35.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:53:35.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:53:35.82#ibcon#enter wrdev, iclass 17, count 2 2006.286.01:53:35.82#ibcon#first serial, iclass 17, count 2 2006.286.01:53:35.82#ibcon#enter sib2, iclass 17, count 2 2006.286.01:53:35.82#ibcon#flushed, iclass 17, count 2 2006.286.01:53:35.82#ibcon#about to write, iclass 17, count 2 2006.286.01:53:35.82#ibcon#wrote, iclass 17, count 2 2006.286.01:53:35.82#ibcon#about to read 3, iclass 17, count 2 2006.286.01:53:35.84#ibcon#read 3, iclass 17, count 2 2006.286.01:53:35.84#ibcon#about to read 4, iclass 17, count 2 2006.286.01:53:35.84#ibcon#read 4, iclass 17, count 2 2006.286.01:53:35.84#ibcon#about to read 5, iclass 17, count 2 2006.286.01:53:35.84#ibcon#read 5, iclass 17, count 2 2006.286.01:53:35.84#ibcon#about to read 6, iclass 17, count 2 2006.286.01:53:35.84#ibcon#read 6, iclass 17, count 2 2006.286.01:53:35.84#ibcon#end of sib2, iclass 17, count 2 2006.286.01:53:35.84#ibcon#*mode == 0, iclass 17, count 2 2006.286.01:53:35.84#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.01:53:35.84#ibcon#[27=AT05-04\r\n] 2006.286.01:53:35.84#ibcon#*before write, iclass 17, count 2 2006.286.01:53:35.84#ibcon#enter sib2, iclass 17, count 2 2006.286.01:53:35.84#ibcon#flushed, iclass 17, count 2 2006.286.01:53:35.84#ibcon#about to write, iclass 17, count 2 2006.286.01:53:35.84#ibcon#wrote, iclass 17, count 2 2006.286.01:53:35.84#ibcon#about to read 3, iclass 17, count 2 2006.286.01:53:35.87#ibcon#read 3, iclass 17, count 2 2006.286.01:53:35.87#ibcon#about to read 4, iclass 17, count 2 2006.286.01:53:35.87#ibcon#read 4, iclass 17, count 2 2006.286.01:53:35.87#ibcon#about to read 5, iclass 17, count 2 2006.286.01:53:35.87#ibcon#read 5, iclass 17, count 2 2006.286.01:53:35.87#ibcon#about to read 6, iclass 17, count 2 2006.286.01:53:35.87#ibcon#read 6, iclass 17, count 2 2006.286.01:53:35.87#ibcon#end of sib2, iclass 17, count 2 2006.286.01:53:35.87#ibcon#*after write, iclass 17, count 2 2006.286.01:53:35.87#ibcon#*before return 0, iclass 17, count 2 2006.286.01:53:35.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:53:35.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.01:53:35.87#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.01:53:35.87#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:35.87#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:53:35.99#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:53:35.99#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:53:35.99#ibcon#enter wrdev, iclass 17, count 0 2006.286.01:53:35.99#ibcon#first serial, iclass 17, count 0 2006.286.01:53:35.99#ibcon#enter sib2, iclass 17, count 0 2006.286.01:53:35.99#ibcon#flushed, iclass 17, count 0 2006.286.01:53:35.99#ibcon#about to write, iclass 17, count 0 2006.286.01:53:35.99#ibcon#wrote, iclass 17, count 0 2006.286.01:53:35.99#ibcon#about to read 3, iclass 17, count 0 2006.286.01:53:36.01#ibcon#read 3, iclass 17, count 0 2006.286.01:53:36.01#ibcon#about to read 4, iclass 17, count 0 2006.286.01:53:36.01#ibcon#read 4, iclass 17, count 0 2006.286.01:53:36.01#ibcon#about to read 5, iclass 17, count 0 2006.286.01:53:36.01#ibcon#read 5, iclass 17, count 0 2006.286.01:53:36.01#ibcon#about to read 6, iclass 17, count 0 2006.286.01:53:36.01#ibcon#read 6, iclass 17, count 0 2006.286.01:53:36.01#ibcon#end of sib2, iclass 17, count 0 2006.286.01:53:36.01#ibcon#*mode == 0, iclass 17, count 0 2006.286.01:53:36.01#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.01:53:36.01#ibcon#[27=USB\r\n] 2006.286.01:53:36.01#ibcon#*before write, iclass 17, count 0 2006.286.01:53:36.01#ibcon#enter sib2, iclass 17, count 0 2006.286.01:53:36.01#ibcon#flushed, iclass 17, count 0 2006.286.01:53:36.01#ibcon#about to write, iclass 17, count 0 2006.286.01:53:36.01#ibcon#wrote, iclass 17, count 0 2006.286.01:53:36.01#ibcon#about to read 3, iclass 17, count 0 2006.286.01:53:36.04#ibcon#read 3, iclass 17, count 0 2006.286.01:53:36.04#ibcon#about to read 4, iclass 17, count 0 2006.286.01:53:36.04#ibcon#read 4, iclass 17, count 0 2006.286.01:53:36.04#ibcon#about to read 5, iclass 17, count 0 2006.286.01:53:36.04#ibcon#read 5, iclass 17, count 0 2006.286.01:53:36.04#ibcon#about to read 6, iclass 17, count 0 2006.286.01:53:36.04#ibcon#read 6, iclass 17, count 0 2006.286.01:53:36.04#ibcon#end of sib2, iclass 17, count 0 2006.286.01:53:36.04#ibcon#*after write, iclass 17, count 0 2006.286.01:53:36.04#ibcon#*before return 0, iclass 17, count 0 2006.286.01:53:36.04#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:53:36.04#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.01:53:36.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.01:53:36.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.01:53:36.04$vck44/vblo=6,719.99 2006.286.01:53:36.04#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.01:53:36.04#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.01:53:36.04#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:36.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:53:36.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:53:36.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:53:36.04#ibcon#enter wrdev, iclass 19, count 0 2006.286.01:53:36.04#ibcon#first serial, iclass 19, count 0 2006.286.01:53:36.04#ibcon#enter sib2, iclass 19, count 0 2006.286.01:53:36.04#ibcon#flushed, iclass 19, count 0 2006.286.01:53:36.04#ibcon#about to write, iclass 19, count 0 2006.286.01:53:36.04#ibcon#wrote, iclass 19, count 0 2006.286.01:53:36.04#ibcon#about to read 3, iclass 19, count 0 2006.286.01:53:36.06#ibcon#read 3, iclass 19, count 0 2006.286.01:53:36.06#ibcon#about to read 4, iclass 19, count 0 2006.286.01:53:36.06#ibcon#read 4, iclass 19, count 0 2006.286.01:53:36.06#ibcon#about to read 5, iclass 19, count 0 2006.286.01:53:36.06#ibcon#read 5, iclass 19, count 0 2006.286.01:53:36.06#ibcon#about to read 6, iclass 19, count 0 2006.286.01:53:36.06#ibcon#read 6, iclass 19, count 0 2006.286.01:53:36.06#ibcon#end of sib2, iclass 19, count 0 2006.286.01:53:36.06#ibcon#*mode == 0, iclass 19, count 0 2006.286.01:53:36.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.01:53:36.06#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:53:36.06#ibcon#*before write, iclass 19, count 0 2006.286.01:53:36.06#ibcon#enter sib2, iclass 19, count 0 2006.286.01:53:36.06#ibcon#flushed, iclass 19, count 0 2006.286.01:53:36.06#ibcon#about to write, iclass 19, count 0 2006.286.01:53:36.06#ibcon#wrote, iclass 19, count 0 2006.286.01:53:36.06#ibcon#about to read 3, iclass 19, count 0 2006.286.01:53:36.10#ibcon#read 3, iclass 19, count 0 2006.286.01:53:36.10#ibcon#about to read 4, iclass 19, count 0 2006.286.01:53:36.10#ibcon#read 4, iclass 19, count 0 2006.286.01:53:36.10#ibcon#about to read 5, iclass 19, count 0 2006.286.01:53:36.10#ibcon#read 5, iclass 19, count 0 2006.286.01:53:36.10#ibcon#about to read 6, iclass 19, count 0 2006.286.01:53:36.10#ibcon#read 6, iclass 19, count 0 2006.286.01:53:36.10#ibcon#end of sib2, iclass 19, count 0 2006.286.01:53:36.10#ibcon#*after write, iclass 19, count 0 2006.286.01:53:36.10#ibcon#*before return 0, iclass 19, count 0 2006.286.01:53:36.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:53:36.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.01:53:36.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.01:53:36.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.01:53:36.10$vck44/vb=6,3 2006.286.01:53:36.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.01:53:36.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.01:53:36.10#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:36.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:53:36.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:53:36.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:53:36.16#ibcon#enter wrdev, iclass 21, count 2 2006.286.01:53:36.16#ibcon#first serial, iclass 21, count 2 2006.286.01:53:36.16#ibcon#enter sib2, iclass 21, count 2 2006.286.01:53:36.16#ibcon#flushed, iclass 21, count 2 2006.286.01:53:36.16#ibcon#about to write, iclass 21, count 2 2006.286.01:53:36.16#ibcon#wrote, iclass 21, count 2 2006.286.01:53:36.16#ibcon#about to read 3, iclass 21, count 2 2006.286.01:53:36.18#ibcon#read 3, iclass 21, count 2 2006.286.01:53:36.18#ibcon#about to read 4, iclass 21, count 2 2006.286.01:53:36.18#ibcon#read 4, iclass 21, count 2 2006.286.01:53:36.18#ibcon#about to read 5, iclass 21, count 2 2006.286.01:53:36.18#ibcon#read 5, iclass 21, count 2 2006.286.01:53:36.18#ibcon#about to read 6, iclass 21, count 2 2006.286.01:53:36.18#ibcon#read 6, iclass 21, count 2 2006.286.01:53:36.18#ibcon#end of sib2, iclass 21, count 2 2006.286.01:53:36.18#ibcon#*mode == 0, iclass 21, count 2 2006.286.01:53:36.18#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.01:53:36.18#ibcon#[27=AT06-03\r\n] 2006.286.01:53:36.18#ibcon#*before write, iclass 21, count 2 2006.286.01:53:36.18#ibcon#enter sib2, iclass 21, count 2 2006.286.01:53:36.18#ibcon#flushed, iclass 21, count 2 2006.286.01:53:36.18#ibcon#about to write, iclass 21, count 2 2006.286.01:53:36.18#ibcon#wrote, iclass 21, count 2 2006.286.01:53:36.18#ibcon#about to read 3, iclass 21, count 2 2006.286.01:53:36.21#ibcon#read 3, iclass 21, count 2 2006.286.01:53:36.21#ibcon#about to read 4, iclass 21, count 2 2006.286.01:53:36.21#ibcon#read 4, iclass 21, count 2 2006.286.01:53:36.21#ibcon#about to read 5, iclass 21, count 2 2006.286.01:53:36.21#ibcon#read 5, iclass 21, count 2 2006.286.01:53:36.21#ibcon#about to read 6, iclass 21, count 2 2006.286.01:53:36.21#ibcon#read 6, iclass 21, count 2 2006.286.01:53:36.21#ibcon#end of sib2, iclass 21, count 2 2006.286.01:53:36.21#ibcon#*after write, iclass 21, count 2 2006.286.01:53:36.21#ibcon#*before return 0, iclass 21, count 2 2006.286.01:53:36.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:53:36.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.01:53:36.21#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.01:53:36.21#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:36.21#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:53:36.33#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:53:36.33#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:53:36.33#ibcon#enter wrdev, iclass 21, count 0 2006.286.01:53:36.33#ibcon#first serial, iclass 21, count 0 2006.286.01:53:36.33#ibcon#enter sib2, iclass 21, count 0 2006.286.01:53:36.33#ibcon#flushed, iclass 21, count 0 2006.286.01:53:36.33#ibcon#about to write, iclass 21, count 0 2006.286.01:53:36.33#ibcon#wrote, iclass 21, count 0 2006.286.01:53:36.33#ibcon#about to read 3, iclass 21, count 0 2006.286.01:53:36.35#ibcon#read 3, iclass 21, count 0 2006.286.01:53:36.35#ibcon#about to read 4, iclass 21, count 0 2006.286.01:53:36.35#ibcon#read 4, iclass 21, count 0 2006.286.01:53:36.35#ibcon#about to read 5, iclass 21, count 0 2006.286.01:53:36.35#ibcon#read 5, iclass 21, count 0 2006.286.01:53:36.35#ibcon#about to read 6, iclass 21, count 0 2006.286.01:53:36.35#ibcon#read 6, iclass 21, count 0 2006.286.01:53:36.35#ibcon#end of sib2, iclass 21, count 0 2006.286.01:53:36.35#ibcon#*mode == 0, iclass 21, count 0 2006.286.01:53:36.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.01:53:36.35#ibcon#[27=USB\r\n] 2006.286.01:53:36.35#ibcon#*before write, iclass 21, count 0 2006.286.01:53:36.35#ibcon#enter sib2, iclass 21, count 0 2006.286.01:53:36.35#ibcon#flushed, iclass 21, count 0 2006.286.01:53:36.35#ibcon#about to write, iclass 21, count 0 2006.286.01:53:36.35#ibcon#wrote, iclass 21, count 0 2006.286.01:53:36.35#ibcon#about to read 3, iclass 21, count 0 2006.286.01:53:36.38#ibcon#read 3, iclass 21, count 0 2006.286.01:53:36.38#ibcon#about to read 4, iclass 21, count 0 2006.286.01:53:36.38#ibcon#read 4, iclass 21, count 0 2006.286.01:53:36.38#ibcon#about to read 5, iclass 21, count 0 2006.286.01:53:36.38#ibcon#read 5, iclass 21, count 0 2006.286.01:53:36.38#ibcon#about to read 6, iclass 21, count 0 2006.286.01:53:36.38#ibcon#read 6, iclass 21, count 0 2006.286.01:53:36.38#ibcon#end of sib2, iclass 21, count 0 2006.286.01:53:36.38#ibcon#*after write, iclass 21, count 0 2006.286.01:53:36.38#ibcon#*before return 0, iclass 21, count 0 2006.286.01:53:36.38#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:53:36.38#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.01:53:36.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.01:53:36.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.01:53:36.38$vck44/vblo=7,734.99 2006.286.01:53:36.38#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.01:53:36.38#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.01:53:36.38#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:36.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:53:36.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:53:36.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:53:36.38#ibcon#enter wrdev, iclass 23, count 0 2006.286.01:53:36.38#ibcon#first serial, iclass 23, count 0 2006.286.01:53:36.38#ibcon#enter sib2, iclass 23, count 0 2006.286.01:53:36.38#ibcon#flushed, iclass 23, count 0 2006.286.01:53:36.38#ibcon#about to write, iclass 23, count 0 2006.286.01:53:36.38#ibcon#wrote, iclass 23, count 0 2006.286.01:53:36.38#ibcon#about to read 3, iclass 23, count 0 2006.286.01:53:36.40#ibcon#read 3, iclass 23, count 0 2006.286.01:53:36.40#ibcon#about to read 4, iclass 23, count 0 2006.286.01:53:36.40#ibcon#read 4, iclass 23, count 0 2006.286.01:53:36.40#ibcon#about to read 5, iclass 23, count 0 2006.286.01:53:36.40#ibcon#read 5, iclass 23, count 0 2006.286.01:53:36.40#ibcon#about to read 6, iclass 23, count 0 2006.286.01:53:36.40#ibcon#read 6, iclass 23, count 0 2006.286.01:53:36.40#ibcon#end of sib2, iclass 23, count 0 2006.286.01:53:36.40#ibcon#*mode == 0, iclass 23, count 0 2006.286.01:53:36.40#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.01:53:36.40#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:53:36.40#ibcon#*before write, iclass 23, count 0 2006.286.01:53:36.40#ibcon#enter sib2, iclass 23, count 0 2006.286.01:53:36.40#ibcon#flushed, iclass 23, count 0 2006.286.01:53:36.40#ibcon#about to write, iclass 23, count 0 2006.286.01:53:36.40#ibcon#wrote, iclass 23, count 0 2006.286.01:53:36.40#ibcon#about to read 3, iclass 23, count 0 2006.286.01:53:36.44#ibcon#read 3, iclass 23, count 0 2006.286.01:53:36.44#ibcon#about to read 4, iclass 23, count 0 2006.286.01:53:36.44#ibcon#read 4, iclass 23, count 0 2006.286.01:53:36.44#ibcon#about to read 5, iclass 23, count 0 2006.286.01:53:36.44#ibcon#read 5, iclass 23, count 0 2006.286.01:53:36.44#ibcon#about to read 6, iclass 23, count 0 2006.286.01:53:36.44#ibcon#read 6, iclass 23, count 0 2006.286.01:53:36.44#ibcon#end of sib2, iclass 23, count 0 2006.286.01:53:36.44#ibcon#*after write, iclass 23, count 0 2006.286.01:53:36.44#ibcon#*before return 0, iclass 23, count 0 2006.286.01:53:36.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:53:36.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.01:53:36.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.01:53:36.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.01:53:36.44$vck44/vb=7,4 2006.286.01:53:36.44#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.01:53:36.44#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.01:53:36.44#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:36.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:53:36.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:53:36.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:53:36.50#ibcon#enter wrdev, iclass 25, count 2 2006.286.01:53:36.50#ibcon#first serial, iclass 25, count 2 2006.286.01:53:36.50#ibcon#enter sib2, iclass 25, count 2 2006.286.01:53:36.50#ibcon#flushed, iclass 25, count 2 2006.286.01:53:36.50#ibcon#about to write, iclass 25, count 2 2006.286.01:53:36.50#ibcon#wrote, iclass 25, count 2 2006.286.01:53:36.50#ibcon#about to read 3, iclass 25, count 2 2006.286.01:53:36.52#ibcon#read 3, iclass 25, count 2 2006.286.01:53:36.52#ibcon#about to read 4, iclass 25, count 2 2006.286.01:53:36.52#ibcon#read 4, iclass 25, count 2 2006.286.01:53:36.52#ibcon#about to read 5, iclass 25, count 2 2006.286.01:53:36.52#ibcon#read 5, iclass 25, count 2 2006.286.01:53:36.52#ibcon#about to read 6, iclass 25, count 2 2006.286.01:53:36.52#ibcon#read 6, iclass 25, count 2 2006.286.01:53:36.52#ibcon#end of sib2, iclass 25, count 2 2006.286.01:53:36.52#ibcon#*mode == 0, iclass 25, count 2 2006.286.01:53:36.52#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.01:53:36.52#ibcon#[27=AT07-04\r\n] 2006.286.01:53:36.52#ibcon#*before write, iclass 25, count 2 2006.286.01:53:36.52#ibcon#enter sib2, iclass 25, count 2 2006.286.01:53:36.52#ibcon#flushed, iclass 25, count 2 2006.286.01:53:36.52#ibcon#about to write, iclass 25, count 2 2006.286.01:53:36.52#ibcon#wrote, iclass 25, count 2 2006.286.01:53:36.52#ibcon#about to read 3, iclass 25, count 2 2006.286.01:53:36.55#ibcon#read 3, iclass 25, count 2 2006.286.01:53:36.55#ibcon#about to read 4, iclass 25, count 2 2006.286.01:53:36.55#ibcon#read 4, iclass 25, count 2 2006.286.01:53:36.55#ibcon#about to read 5, iclass 25, count 2 2006.286.01:53:36.55#ibcon#read 5, iclass 25, count 2 2006.286.01:53:36.55#ibcon#about to read 6, iclass 25, count 2 2006.286.01:53:36.55#ibcon#read 6, iclass 25, count 2 2006.286.01:53:36.55#ibcon#end of sib2, iclass 25, count 2 2006.286.01:53:36.55#ibcon#*after write, iclass 25, count 2 2006.286.01:53:36.55#ibcon#*before return 0, iclass 25, count 2 2006.286.01:53:36.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:53:36.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.01:53:36.55#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.01:53:36.55#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:36.55#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:53:36.67#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:53:36.67#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:53:36.67#ibcon#enter wrdev, iclass 25, count 0 2006.286.01:53:36.67#ibcon#first serial, iclass 25, count 0 2006.286.01:53:36.67#ibcon#enter sib2, iclass 25, count 0 2006.286.01:53:36.67#ibcon#flushed, iclass 25, count 0 2006.286.01:53:36.67#ibcon#about to write, iclass 25, count 0 2006.286.01:53:36.67#ibcon#wrote, iclass 25, count 0 2006.286.01:53:36.67#ibcon#about to read 3, iclass 25, count 0 2006.286.01:53:36.69#ibcon#read 3, iclass 25, count 0 2006.286.01:53:36.69#ibcon#about to read 4, iclass 25, count 0 2006.286.01:53:36.69#ibcon#read 4, iclass 25, count 0 2006.286.01:53:36.69#ibcon#about to read 5, iclass 25, count 0 2006.286.01:53:36.69#ibcon#read 5, iclass 25, count 0 2006.286.01:53:36.69#ibcon#about to read 6, iclass 25, count 0 2006.286.01:53:36.69#ibcon#read 6, iclass 25, count 0 2006.286.01:53:36.69#ibcon#end of sib2, iclass 25, count 0 2006.286.01:53:36.69#ibcon#*mode == 0, iclass 25, count 0 2006.286.01:53:36.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.01:53:36.69#ibcon#[27=USB\r\n] 2006.286.01:53:36.69#ibcon#*before write, iclass 25, count 0 2006.286.01:53:36.69#ibcon#enter sib2, iclass 25, count 0 2006.286.01:53:36.69#ibcon#flushed, iclass 25, count 0 2006.286.01:53:36.69#ibcon#about to write, iclass 25, count 0 2006.286.01:53:36.69#ibcon#wrote, iclass 25, count 0 2006.286.01:53:36.69#ibcon#about to read 3, iclass 25, count 0 2006.286.01:53:36.72#ibcon#read 3, iclass 25, count 0 2006.286.01:53:36.72#ibcon#about to read 4, iclass 25, count 0 2006.286.01:53:36.72#ibcon#read 4, iclass 25, count 0 2006.286.01:53:36.72#ibcon#about to read 5, iclass 25, count 0 2006.286.01:53:36.72#ibcon#read 5, iclass 25, count 0 2006.286.01:53:36.72#ibcon#about to read 6, iclass 25, count 0 2006.286.01:53:36.72#ibcon#read 6, iclass 25, count 0 2006.286.01:53:36.72#ibcon#end of sib2, iclass 25, count 0 2006.286.01:53:36.72#ibcon#*after write, iclass 25, count 0 2006.286.01:53:36.72#ibcon#*before return 0, iclass 25, count 0 2006.286.01:53:36.72#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:53:36.72#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.01:53:36.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.01:53:36.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.01:53:36.72$vck44/vblo=8,744.99 2006.286.01:53:36.72#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.01:53:36.72#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.01:53:36.72#ibcon#ireg 17 cls_cnt 0 2006.286.01:53:36.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:53:36.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:53:36.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:53:36.72#ibcon#enter wrdev, iclass 27, count 0 2006.286.01:53:36.72#ibcon#first serial, iclass 27, count 0 2006.286.01:53:36.72#ibcon#enter sib2, iclass 27, count 0 2006.286.01:53:36.72#ibcon#flushed, iclass 27, count 0 2006.286.01:53:36.72#ibcon#about to write, iclass 27, count 0 2006.286.01:53:36.72#ibcon#wrote, iclass 27, count 0 2006.286.01:53:36.72#ibcon#about to read 3, iclass 27, count 0 2006.286.01:53:36.74#ibcon#read 3, iclass 27, count 0 2006.286.01:53:36.74#ibcon#about to read 4, iclass 27, count 0 2006.286.01:53:36.74#ibcon#read 4, iclass 27, count 0 2006.286.01:53:36.74#ibcon#about to read 5, iclass 27, count 0 2006.286.01:53:36.74#ibcon#read 5, iclass 27, count 0 2006.286.01:53:36.74#ibcon#about to read 6, iclass 27, count 0 2006.286.01:53:36.74#ibcon#read 6, iclass 27, count 0 2006.286.01:53:36.74#ibcon#end of sib2, iclass 27, count 0 2006.286.01:53:36.74#ibcon#*mode == 0, iclass 27, count 0 2006.286.01:53:36.74#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.01:53:36.74#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:53:36.74#ibcon#*before write, iclass 27, count 0 2006.286.01:53:36.74#ibcon#enter sib2, iclass 27, count 0 2006.286.01:53:36.74#ibcon#flushed, iclass 27, count 0 2006.286.01:53:36.74#ibcon#about to write, iclass 27, count 0 2006.286.01:53:36.74#ibcon#wrote, iclass 27, count 0 2006.286.01:53:36.74#ibcon#about to read 3, iclass 27, count 0 2006.286.01:53:36.78#ibcon#read 3, iclass 27, count 0 2006.286.01:53:36.78#ibcon#about to read 4, iclass 27, count 0 2006.286.01:53:36.78#ibcon#read 4, iclass 27, count 0 2006.286.01:53:36.78#ibcon#about to read 5, iclass 27, count 0 2006.286.01:53:36.78#ibcon#read 5, iclass 27, count 0 2006.286.01:53:36.78#ibcon#about to read 6, iclass 27, count 0 2006.286.01:53:36.78#ibcon#read 6, iclass 27, count 0 2006.286.01:53:36.78#ibcon#end of sib2, iclass 27, count 0 2006.286.01:53:36.78#ibcon#*after write, iclass 27, count 0 2006.286.01:53:36.78#ibcon#*before return 0, iclass 27, count 0 2006.286.01:53:36.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:53:36.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.01:53:36.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.01:53:36.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.01:53:36.78$vck44/vb=8,4 2006.286.01:53:36.78#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.01:53:36.78#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.01:53:36.78#ibcon#ireg 11 cls_cnt 2 2006.286.01:53:36.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:53:36.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:53:36.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:53:36.84#ibcon#enter wrdev, iclass 29, count 2 2006.286.01:53:36.84#ibcon#first serial, iclass 29, count 2 2006.286.01:53:36.84#ibcon#enter sib2, iclass 29, count 2 2006.286.01:53:36.84#ibcon#flushed, iclass 29, count 2 2006.286.01:53:36.84#ibcon#about to write, iclass 29, count 2 2006.286.01:53:36.84#ibcon#wrote, iclass 29, count 2 2006.286.01:53:36.84#ibcon#about to read 3, iclass 29, count 2 2006.286.01:53:36.86#ibcon#read 3, iclass 29, count 2 2006.286.01:53:36.86#ibcon#about to read 4, iclass 29, count 2 2006.286.01:53:36.86#ibcon#read 4, iclass 29, count 2 2006.286.01:53:36.86#ibcon#about to read 5, iclass 29, count 2 2006.286.01:53:36.86#ibcon#read 5, iclass 29, count 2 2006.286.01:53:36.86#ibcon#about to read 6, iclass 29, count 2 2006.286.01:53:36.86#ibcon#read 6, iclass 29, count 2 2006.286.01:53:36.86#ibcon#end of sib2, iclass 29, count 2 2006.286.01:53:36.86#ibcon#*mode == 0, iclass 29, count 2 2006.286.01:53:36.86#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.01:53:36.86#ibcon#[27=AT08-04\r\n] 2006.286.01:53:36.86#ibcon#*before write, iclass 29, count 2 2006.286.01:53:36.86#ibcon#enter sib2, iclass 29, count 2 2006.286.01:53:36.86#ibcon#flushed, iclass 29, count 2 2006.286.01:53:36.86#ibcon#about to write, iclass 29, count 2 2006.286.01:53:36.86#ibcon#wrote, iclass 29, count 2 2006.286.01:53:36.86#ibcon#about to read 3, iclass 29, count 2 2006.286.01:53:36.89#ibcon#read 3, iclass 29, count 2 2006.286.01:53:36.89#ibcon#about to read 4, iclass 29, count 2 2006.286.01:53:36.89#ibcon#read 4, iclass 29, count 2 2006.286.01:53:36.89#ibcon#about to read 5, iclass 29, count 2 2006.286.01:53:36.89#ibcon#read 5, iclass 29, count 2 2006.286.01:53:36.89#ibcon#about to read 6, iclass 29, count 2 2006.286.01:53:36.89#ibcon#read 6, iclass 29, count 2 2006.286.01:53:36.89#ibcon#end of sib2, iclass 29, count 2 2006.286.01:53:36.89#ibcon#*after write, iclass 29, count 2 2006.286.01:53:36.89#ibcon#*before return 0, iclass 29, count 2 2006.286.01:53:36.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:53:36.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.01:53:36.89#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.01:53:36.89#ibcon#ireg 7 cls_cnt 0 2006.286.01:53:36.89#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:53:37.01#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:53:37.01#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:53:37.01#ibcon#enter wrdev, iclass 29, count 0 2006.286.01:53:37.01#ibcon#first serial, iclass 29, count 0 2006.286.01:53:37.01#ibcon#enter sib2, iclass 29, count 0 2006.286.01:53:37.01#ibcon#flushed, iclass 29, count 0 2006.286.01:53:37.01#ibcon#about to write, iclass 29, count 0 2006.286.01:53:37.01#ibcon#wrote, iclass 29, count 0 2006.286.01:53:37.01#ibcon#about to read 3, iclass 29, count 0 2006.286.01:53:37.03#ibcon#read 3, iclass 29, count 0 2006.286.01:53:37.03#ibcon#about to read 4, iclass 29, count 0 2006.286.01:53:37.03#ibcon#read 4, iclass 29, count 0 2006.286.01:53:37.03#ibcon#about to read 5, iclass 29, count 0 2006.286.01:53:37.03#ibcon#read 5, iclass 29, count 0 2006.286.01:53:37.03#ibcon#about to read 6, iclass 29, count 0 2006.286.01:53:37.03#ibcon#read 6, iclass 29, count 0 2006.286.01:53:37.03#ibcon#end of sib2, iclass 29, count 0 2006.286.01:53:37.03#ibcon#*mode == 0, iclass 29, count 0 2006.286.01:53:37.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.01:53:37.03#ibcon#[27=USB\r\n] 2006.286.01:53:37.03#ibcon#*before write, iclass 29, count 0 2006.286.01:53:37.03#ibcon#enter sib2, iclass 29, count 0 2006.286.01:53:37.03#ibcon#flushed, iclass 29, count 0 2006.286.01:53:37.03#ibcon#about to write, iclass 29, count 0 2006.286.01:53:37.03#ibcon#wrote, iclass 29, count 0 2006.286.01:53:37.03#ibcon#about to read 3, iclass 29, count 0 2006.286.01:53:37.06#ibcon#read 3, iclass 29, count 0 2006.286.01:53:37.06#ibcon#about to read 4, iclass 29, count 0 2006.286.01:53:37.06#ibcon#read 4, iclass 29, count 0 2006.286.01:53:37.06#ibcon#about to read 5, iclass 29, count 0 2006.286.01:53:37.06#ibcon#read 5, iclass 29, count 0 2006.286.01:53:37.06#ibcon#about to read 6, iclass 29, count 0 2006.286.01:53:37.06#ibcon#read 6, iclass 29, count 0 2006.286.01:53:37.06#ibcon#end of sib2, iclass 29, count 0 2006.286.01:53:37.06#ibcon#*after write, iclass 29, count 0 2006.286.01:53:37.06#ibcon#*before return 0, iclass 29, count 0 2006.286.01:53:37.06#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:53:37.06#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.01:53:37.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.01:53:37.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.01:53:37.06$vck44/vabw=wide 2006.286.01:53:37.06#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.01:53:37.06#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.01:53:37.06#ibcon#ireg 8 cls_cnt 0 2006.286.01:53:37.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:53:37.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:53:37.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:53:37.06#ibcon#enter wrdev, iclass 31, count 0 2006.286.01:53:37.06#ibcon#first serial, iclass 31, count 0 2006.286.01:53:37.06#ibcon#enter sib2, iclass 31, count 0 2006.286.01:53:37.06#ibcon#flushed, iclass 31, count 0 2006.286.01:53:37.06#ibcon#about to write, iclass 31, count 0 2006.286.01:53:37.06#ibcon#wrote, iclass 31, count 0 2006.286.01:53:37.06#ibcon#about to read 3, iclass 31, count 0 2006.286.01:53:37.08#ibcon#read 3, iclass 31, count 0 2006.286.01:53:37.08#ibcon#about to read 4, iclass 31, count 0 2006.286.01:53:37.08#ibcon#read 4, iclass 31, count 0 2006.286.01:53:37.08#ibcon#about to read 5, iclass 31, count 0 2006.286.01:53:37.08#ibcon#read 5, iclass 31, count 0 2006.286.01:53:37.08#ibcon#about to read 6, iclass 31, count 0 2006.286.01:53:37.08#ibcon#read 6, iclass 31, count 0 2006.286.01:53:37.08#ibcon#end of sib2, iclass 31, count 0 2006.286.01:53:37.08#ibcon#*mode == 0, iclass 31, count 0 2006.286.01:53:37.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.01:53:37.08#ibcon#[25=BW32\r\n] 2006.286.01:53:37.08#ibcon#*before write, iclass 31, count 0 2006.286.01:53:37.08#ibcon#enter sib2, iclass 31, count 0 2006.286.01:53:37.08#ibcon#flushed, iclass 31, count 0 2006.286.01:53:37.08#ibcon#about to write, iclass 31, count 0 2006.286.01:53:37.08#ibcon#wrote, iclass 31, count 0 2006.286.01:53:37.08#ibcon#about to read 3, iclass 31, count 0 2006.286.01:53:37.11#ibcon#read 3, iclass 31, count 0 2006.286.01:53:37.11#ibcon#about to read 4, iclass 31, count 0 2006.286.01:53:37.11#ibcon#read 4, iclass 31, count 0 2006.286.01:53:37.11#ibcon#about to read 5, iclass 31, count 0 2006.286.01:53:37.11#ibcon#read 5, iclass 31, count 0 2006.286.01:53:37.11#ibcon#about to read 6, iclass 31, count 0 2006.286.01:53:37.11#ibcon#read 6, iclass 31, count 0 2006.286.01:53:37.11#ibcon#end of sib2, iclass 31, count 0 2006.286.01:53:37.11#ibcon#*after write, iclass 31, count 0 2006.286.01:53:37.11#ibcon#*before return 0, iclass 31, count 0 2006.286.01:53:37.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:53:37.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:53:37.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.01:53:37.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.01:53:37.11$vck44/vbbw=wide 2006.286.01:53:37.11#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.01:53:37.11#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.01:53:37.11#ibcon#ireg 8 cls_cnt 0 2006.286.01:53:37.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:53:37.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:53:37.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:53:37.18#ibcon#enter wrdev, iclass 33, count 0 2006.286.01:53:37.18#ibcon#first serial, iclass 33, count 0 2006.286.01:53:37.18#ibcon#enter sib2, iclass 33, count 0 2006.286.01:53:37.18#ibcon#flushed, iclass 33, count 0 2006.286.01:53:37.18#ibcon#about to write, iclass 33, count 0 2006.286.01:53:37.18#ibcon#wrote, iclass 33, count 0 2006.286.01:53:37.18#ibcon#about to read 3, iclass 33, count 0 2006.286.01:53:37.20#ibcon#read 3, iclass 33, count 0 2006.286.01:53:37.20#ibcon#about to read 4, iclass 33, count 0 2006.286.01:53:37.20#ibcon#read 4, iclass 33, count 0 2006.286.01:53:37.20#ibcon#about to read 5, iclass 33, count 0 2006.286.01:53:37.20#ibcon#read 5, iclass 33, count 0 2006.286.01:53:37.20#ibcon#about to read 6, iclass 33, count 0 2006.286.01:53:37.20#ibcon#read 6, iclass 33, count 0 2006.286.01:53:37.20#ibcon#end of sib2, iclass 33, count 0 2006.286.01:53:37.20#ibcon#*mode == 0, iclass 33, count 0 2006.286.01:53:37.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.01:53:37.20#ibcon#[27=BW32\r\n] 2006.286.01:53:37.20#ibcon#*before write, iclass 33, count 0 2006.286.01:53:37.20#ibcon#enter sib2, iclass 33, count 0 2006.286.01:53:37.20#ibcon#flushed, iclass 33, count 0 2006.286.01:53:37.20#ibcon#about to write, iclass 33, count 0 2006.286.01:53:37.20#ibcon#wrote, iclass 33, count 0 2006.286.01:53:37.20#ibcon#about to read 3, iclass 33, count 0 2006.286.01:53:37.23#ibcon#read 3, iclass 33, count 0 2006.286.01:53:37.23#ibcon#about to read 4, iclass 33, count 0 2006.286.01:53:37.23#ibcon#read 4, iclass 33, count 0 2006.286.01:53:37.23#ibcon#about to read 5, iclass 33, count 0 2006.286.01:53:37.23#ibcon#read 5, iclass 33, count 0 2006.286.01:53:37.23#ibcon#about to read 6, iclass 33, count 0 2006.286.01:53:37.23#ibcon#read 6, iclass 33, count 0 2006.286.01:53:37.23#ibcon#end of sib2, iclass 33, count 0 2006.286.01:53:37.23#ibcon#*after write, iclass 33, count 0 2006.286.01:53:37.23#ibcon#*before return 0, iclass 33, count 0 2006.286.01:53:37.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:53:37.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.01:53:37.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.01:53:37.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.01:53:37.23$setupk4/ifdk4 2006.286.01:53:37.23$ifdk4/lo= 2006.286.01:53:37.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:53:37.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:53:37.23$ifdk4/patch= 2006.286.01:53:37.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:53:37.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:53:37.23$setupk4/!*+20s 2006.286.01:53:44.41#abcon#<5=/03 3.9 7.1 21.21 781016.1\r\n> 2006.286.01:53:44.43#abcon#{5=INTERFACE CLEAR} 2006.286.01:53:44.49#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:53:49.14#trakl#Source acquired 2006.286.01:53:51.14#flagr#flagr/antenna,acquired 2006.286.01:53:51.74$setupk4/"tpicd 2006.286.01:53:51.74$setupk4/echo=off 2006.286.01:53:51.74$setupk4/xlog=off 2006.286.01:53:51.74:!2006.286.01:56:27 2006.286.01:56:27.00:preob 2006.286.01:56:28.14/onsource/TRACKING 2006.286.01:56:28.14:!2006.286.01:56:37 2006.286.01:56:37.00:"tape 2006.286.01:56:37.00:"st=record 2006.286.01:56:37.00:data_valid=on 2006.286.01:56:37.00:midob 2006.286.01:56:37.14/onsource/TRACKING 2006.286.01:56:37.14/wx/21.22,1016.0,80 2006.286.01:56:37.28/cable/+6.5009E-03 2006.286.01:56:38.37/va/01,07,usb,yes,44,47 2006.286.01:56:38.37/va/02,06,usb,yes,44,44 2006.286.01:56:38.37/va/03,07,usb,yes,43,45 2006.286.01:56:38.37/va/04,06,usb,yes,44,47 2006.286.01:56:38.37/va/05,03,usb,yes,44,44 2006.286.01:56:38.37/va/06,04,usb,yes,40,39 2006.286.01:56:38.37/va/07,04,usb,yes,41,41 2006.286.01:56:38.37/va/08,03,usb,yes,42,50 2006.286.01:56:38.60/valo/01,524.99,yes,locked 2006.286.01:56:38.60/valo/02,534.99,yes,locked 2006.286.01:56:38.60/valo/03,564.99,yes,locked 2006.286.01:56:38.60/valo/04,624.99,yes,locked 2006.286.01:56:38.60/valo/05,734.99,yes,locked 2006.286.01:56:38.60/valo/06,814.99,yes,locked 2006.286.01:56:38.60/valo/07,864.99,yes,locked 2006.286.01:56:38.60/valo/08,884.99,yes,locked 2006.286.01:56:39.69/vb/01,04,usb,yes,36,34 2006.286.01:56:39.69/vb/02,05,usb,yes,34,33 2006.286.01:56:39.69/vb/03,04,usb,yes,35,38 2006.286.01:56:39.69/vb/04,05,usb,yes,35,34 2006.286.01:56:39.69/vb/05,04,usb,yes,32,35 2006.286.01:56:39.69/vb/06,03,usb,yes,46,41 2006.286.01:56:39.69/vb/07,04,usb,yes,37,37 2006.286.01:56:39.69/vb/08,04,usb,yes,33,38 2006.286.01:56:39.92/vblo/01,629.99,yes,locked 2006.286.01:56:39.92/vblo/02,634.99,yes,locked 2006.286.01:56:39.92/vblo/03,649.99,yes,locked 2006.286.01:56:39.92/vblo/04,679.99,yes,locked 2006.286.01:56:39.92/vblo/05,709.99,yes,locked 2006.286.01:56:39.92/vblo/06,719.99,yes,locked 2006.286.01:56:39.92/vblo/07,734.99,yes,locked 2006.286.01:56:39.92/vblo/08,744.99,yes,locked 2006.286.01:56:40.07/vabw/8 2006.286.01:56:40.22/vbbw/8 2006.286.01:56:40.35/xfe/off,on,12.0 2006.286.01:56:40.73/ifatt/23,28,28,28 2006.286.01:56:41.08/fmout-gps/S +2.77E-07 2006.286.01:56:41.10:!2006.286.01:57:47 2006.286.01:57:47.01:data_valid=off 2006.286.01:57:47.01:"et 2006.286.01:57:47.01:!+3s 2006.286.01:57:50.02:"tape 2006.286.01:57:50.02:postob 2006.286.01:57:50.14/cable/+6.5022E-03 2006.286.01:57:50.14/wx/21.24,1016.0,80 2006.286.01:57:51.08/fmout-gps/S +2.76E-07 2006.286.01:57:51.08:scan_name=286-0202,jd0610,220 2006.286.01:57:51.08:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.286.01:57:52.13#flagr#flagr/antenna,new-source 2006.286.01:57:52.13:checkk5 2006.286.01:57:52.61/chk_autoobs//k5ts1/ autoobs is running! 2006.286.01:57:53.00/chk_autoobs//k5ts2/ autoobs is running! 2006.286.01:57:53.46/chk_autoobs//k5ts3/ autoobs is running! 2006.286.01:57:53.85/chk_autoobs//k5ts4/ autoobs is running! 2006.286.01:57:54.21/chk_obsdata//k5ts1/T2860156??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.286.01:57:54.63/chk_obsdata//k5ts2/T2860156??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.286.01:57:55.00/chk_obsdata//k5ts3/T2860156??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.286.01:57:55.45/chk_obsdata//k5ts4/T2860156??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.286.01:57:56.24/k5log//k5ts1_log_newline 2006.286.01:57:57.00/k5log//k5ts2_log_newline 2006.286.01:57:58.10/k5log//k5ts3_log_newline 2006.286.01:57:58.77/k5log//k5ts4_log_newline 2006.286.01:57:58.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.01:57:58.79:setupk4=1 2006.286.01:57:58.79$setupk4/echo=on 2006.286.01:57:58.79$setupk4/pcalon 2006.286.01:57:58.79$pcalon/"no phase cal control is implemented here 2006.286.01:57:58.79$setupk4/"tpicd=stop 2006.286.01:57:58.79$setupk4/"rec=synch_on 2006.286.01:57:58.79$setupk4/"rec_mode=128 2006.286.01:57:58.79$setupk4/!* 2006.286.01:57:58.79$setupk4/recpk4 2006.286.01:57:58.79$recpk4/recpatch= 2006.286.01:57:58.79$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.01:57:58.79$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.01:57:58.79$setupk4/vck44 2006.286.01:57:58.79$vck44/valo=1,524.99 2006.286.01:57:58.80#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.01:57:58.80#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.01:57:58.80#ibcon#ireg 17 cls_cnt 0 2006.286.01:57:58.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:57:58.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:57:58.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:57:58.80#ibcon#enter wrdev, iclass 31, count 0 2006.286.01:57:58.80#ibcon#first serial, iclass 31, count 0 2006.286.01:57:58.80#ibcon#enter sib2, iclass 31, count 0 2006.286.01:57:58.80#ibcon#flushed, iclass 31, count 0 2006.286.01:57:58.80#ibcon#about to write, iclass 31, count 0 2006.286.01:57:58.80#ibcon#wrote, iclass 31, count 0 2006.286.01:57:58.80#ibcon#about to read 3, iclass 31, count 0 2006.286.01:57:58.81#ibcon#read 3, iclass 31, count 0 2006.286.01:57:58.81#ibcon#about to read 4, iclass 31, count 0 2006.286.01:57:58.81#ibcon#read 4, iclass 31, count 0 2006.286.01:57:58.81#ibcon#about to read 5, iclass 31, count 0 2006.286.01:57:58.81#ibcon#read 5, iclass 31, count 0 2006.286.01:57:58.81#ibcon#about to read 6, iclass 31, count 0 2006.286.01:57:58.81#ibcon#read 6, iclass 31, count 0 2006.286.01:57:58.81#ibcon#end of sib2, iclass 31, count 0 2006.286.01:57:58.81#ibcon#*mode == 0, iclass 31, count 0 2006.286.01:57:58.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.01:57:58.81#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.01:57:58.81#ibcon#*before write, iclass 31, count 0 2006.286.01:57:58.81#ibcon#enter sib2, iclass 31, count 0 2006.286.01:57:58.81#ibcon#flushed, iclass 31, count 0 2006.286.01:57:58.81#ibcon#about to write, iclass 31, count 0 2006.286.01:57:58.81#ibcon#wrote, iclass 31, count 0 2006.286.01:57:58.81#ibcon#about to read 3, iclass 31, count 0 2006.286.01:57:58.84#abcon#{5=INTERFACE CLEAR} 2006.286.01:57:58.86#ibcon#read 3, iclass 31, count 0 2006.286.01:57:58.86#ibcon#about to read 4, iclass 31, count 0 2006.286.01:57:58.86#ibcon#read 4, iclass 31, count 0 2006.286.01:57:58.86#ibcon#about to read 5, iclass 31, count 0 2006.286.01:57:58.86#ibcon#read 5, iclass 31, count 0 2006.286.01:57:58.86#ibcon#about to read 6, iclass 31, count 0 2006.286.01:57:58.86#ibcon#read 6, iclass 31, count 0 2006.286.01:57:58.86#ibcon#end of sib2, iclass 31, count 0 2006.286.01:57:58.86#ibcon#*after write, iclass 31, count 0 2006.286.01:57:58.86#ibcon#*before return 0, iclass 31, count 0 2006.286.01:57:58.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:57:58.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.01:57:58.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.01:57:58.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.01:57:58.86$vck44/va=1,7 2006.286.01:57:58.86#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.01:57:58.86#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.01:57:58.86#ibcon#ireg 11 cls_cnt 2 2006.286.01:57:58.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:57:58.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:57:58.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:57:58.86#ibcon#enter wrdev, iclass 35, count 2 2006.286.01:57:58.86#ibcon#first serial, iclass 35, count 2 2006.286.01:57:58.86#ibcon#enter sib2, iclass 35, count 2 2006.286.01:57:58.86#ibcon#flushed, iclass 35, count 2 2006.286.01:57:58.86#ibcon#about to write, iclass 35, count 2 2006.286.01:57:58.86#ibcon#wrote, iclass 35, count 2 2006.286.01:57:58.86#ibcon#about to read 3, iclass 35, count 2 2006.286.01:57:58.88#ibcon#read 3, iclass 35, count 2 2006.286.01:57:58.88#ibcon#about to read 4, iclass 35, count 2 2006.286.01:57:58.88#ibcon#read 4, iclass 35, count 2 2006.286.01:57:58.88#ibcon#about to read 5, iclass 35, count 2 2006.286.01:57:58.88#ibcon#read 5, iclass 35, count 2 2006.286.01:57:58.88#ibcon#about to read 6, iclass 35, count 2 2006.286.01:57:58.88#ibcon#read 6, iclass 35, count 2 2006.286.01:57:58.88#ibcon#end of sib2, iclass 35, count 2 2006.286.01:57:58.88#ibcon#*mode == 0, iclass 35, count 2 2006.286.01:57:58.88#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.01:57:58.88#ibcon#[25=AT01-07\r\n] 2006.286.01:57:58.88#ibcon#*before write, iclass 35, count 2 2006.286.01:57:58.88#ibcon#enter sib2, iclass 35, count 2 2006.286.01:57:58.88#ibcon#flushed, iclass 35, count 2 2006.286.01:57:58.88#ibcon#about to write, iclass 35, count 2 2006.286.01:57:58.88#ibcon#wrote, iclass 35, count 2 2006.286.01:57:58.88#ibcon#about to read 3, iclass 35, count 2 2006.286.01:57:58.90#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:57:58.91#ibcon#read 3, iclass 35, count 2 2006.286.01:57:58.91#ibcon#about to read 4, iclass 35, count 2 2006.286.01:57:58.91#ibcon#read 4, iclass 35, count 2 2006.286.01:57:58.91#ibcon#about to read 5, iclass 35, count 2 2006.286.01:57:58.91#ibcon#read 5, iclass 35, count 2 2006.286.01:57:58.91#ibcon#about to read 6, iclass 35, count 2 2006.286.01:57:58.91#ibcon#read 6, iclass 35, count 2 2006.286.01:57:58.91#ibcon#end of sib2, iclass 35, count 2 2006.286.01:57:58.91#ibcon#*after write, iclass 35, count 2 2006.286.01:57:58.91#ibcon#*before return 0, iclass 35, count 2 2006.286.01:57:58.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:57:58.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.01:57:58.91#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.01:57:58.91#ibcon#ireg 7 cls_cnt 0 2006.286.01:57:58.91#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:57:59.03#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:57:59.03#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:57:59.03#ibcon#enter wrdev, iclass 35, count 0 2006.286.01:57:59.03#ibcon#first serial, iclass 35, count 0 2006.286.01:57:59.03#ibcon#enter sib2, iclass 35, count 0 2006.286.01:57:59.03#ibcon#flushed, iclass 35, count 0 2006.286.01:57:59.03#ibcon#about to write, iclass 35, count 0 2006.286.01:57:59.03#ibcon#wrote, iclass 35, count 0 2006.286.01:57:59.03#ibcon#about to read 3, iclass 35, count 0 2006.286.01:57:59.05#ibcon#read 3, iclass 35, count 0 2006.286.01:57:59.05#ibcon#about to read 4, iclass 35, count 0 2006.286.01:57:59.05#ibcon#read 4, iclass 35, count 0 2006.286.01:57:59.05#ibcon#about to read 5, iclass 35, count 0 2006.286.01:57:59.05#ibcon#read 5, iclass 35, count 0 2006.286.01:57:59.05#ibcon#about to read 6, iclass 35, count 0 2006.286.01:57:59.05#ibcon#read 6, iclass 35, count 0 2006.286.01:57:59.05#ibcon#end of sib2, iclass 35, count 0 2006.286.01:57:59.05#ibcon#*mode == 0, iclass 35, count 0 2006.286.01:57:59.05#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.01:57:59.05#ibcon#[25=USB\r\n] 2006.286.01:57:59.05#ibcon#*before write, iclass 35, count 0 2006.286.01:57:59.05#ibcon#enter sib2, iclass 35, count 0 2006.286.01:57:59.05#ibcon#flushed, iclass 35, count 0 2006.286.01:57:59.05#ibcon#about to write, iclass 35, count 0 2006.286.01:57:59.05#ibcon#wrote, iclass 35, count 0 2006.286.01:57:59.05#ibcon#about to read 3, iclass 35, count 0 2006.286.01:57:59.08#ibcon#read 3, iclass 35, count 0 2006.286.01:57:59.08#ibcon#about to read 4, iclass 35, count 0 2006.286.01:57:59.08#ibcon#read 4, iclass 35, count 0 2006.286.01:57:59.08#ibcon#about to read 5, iclass 35, count 0 2006.286.01:57:59.08#ibcon#read 5, iclass 35, count 0 2006.286.01:57:59.08#ibcon#about to read 6, iclass 35, count 0 2006.286.01:57:59.08#ibcon#read 6, iclass 35, count 0 2006.286.01:57:59.08#ibcon#end of sib2, iclass 35, count 0 2006.286.01:57:59.08#ibcon#*after write, iclass 35, count 0 2006.286.01:57:59.08#ibcon#*before return 0, iclass 35, count 0 2006.286.01:57:59.08#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:57:59.08#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.01:57:59.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.01:57:59.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.01:57:59.08$vck44/valo=2,534.99 2006.286.01:57:59.08#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.01:57:59.08#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.01:57:59.08#ibcon#ireg 17 cls_cnt 0 2006.286.01:57:59.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:57:59.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:57:59.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:57:59.08#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:57:59.08#ibcon#first serial, iclass 38, count 0 2006.286.01:57:59.08#ibcon#enter sib2, iclass 38, count 0 2006.286.01:57:59.08#ibcon#flushed, iclass 38, count 0 2006.286.01:57:59.08#ibcon#about to write, iclass 38, count 0 2006.286.01:57:59.08#ibcon#wrote, iclass 38, count 0 2006.286.01:57:59.08#ibcon#about to read 3, iclass 38, count 0 2006.286.01:57:59.10#ibcon#read 3, iclass 38, count 0 2006.286.01:57:59.10#ibcon#about to read 4, iclass 38, count 0 2006.286.01:57:59.10#ibcon#read 4, iclass 38, count 0 2006.286.01:57:59.10#ibcon#about to read 5, iclass 38, count 0 2006.286.01:57:59.10#ibcon#read 5, iclass 38, count 0 2006.286.01:57:59.10#ibcon#about to read 6, iclass 38, count 0 2006.286.01:57:59.10#ibcon#read 6, iclass 38, count 0 2006.286.01:57:59.10#ibcon#end of sib2, iclass 38, count 0 2006.286.01:57:59.10#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:57:59.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:57:59.10#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.01:57:59.10#ibcon#*before write, iclass 38, count 0 2006.286.01:57:59.10#ibcon#enter sib2, iclass 38, count 0 2006.286.01:57:59.10#ibcon#flushed, iclass 38, count 0 2006.286.01:57:59.10#ibcon#about to write, iclass 38, count 0 2006.286.01:57:59.10#ibcon#wrote, iclass 38, count 0 2006.286.01:57:59.10#ibcon#about to read 3, iclass 38, count 0 2006.286.01:57:59.14#ibcon#read 3, iclass 38, count 0 2006.286.01:57:59.14#ibcon#about to read 4, iclass 38, count 0 2006.286.01:57:59.14#ibcon#read 4, iclass 38, count 0 2006.286.01:57:59.14#ibcon#about to read 5, iclass 38, count 0 2006.286.01:57:59.14#ibcon#read 5, iclass 38, count 0 2006.286.01:57:59.14#ibcon#about to read 6, iclass 38, count 0 2006.286.01:57:59.14#ibcon#read 6, iclass 38, count 0 2006.286.01:57:59.14#ibcon#end of sib2, iclass 38, count 0 2006.286.01:57:59.14#ibcon#*after write, iclass 38, count 0 2006.286.01:57:59.14#ibcon#*before return 0, iclass 38, count 0 2006.286.01:57:59.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:57:59.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:57:59.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:57:59.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:57:59.14$vck44/va=2,6 2006.286.01:57:59.14#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.01:57:59.14#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.01:57:59.14#ibcon#ireg 11 cls_cnt 2 2006.286.01:57:59.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:57:59.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:57:59.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:57:59.20#ibcon#enter wrdev, iclass 40, count 2 2006.286.01:57:59.20#ibcon#first serial, iclass 40, count 2 2006.286.01:57:59.20#ibcon#enter sib2, iclass 40, count 2 2006.286.01:57:59.20#ibcon#flushed, iclass 40, count 2 2006.286.01:57:59.20#ibcon#about to write, iclass 40, count 2 2006.286.01:57:59.20#ibcon#wrote, iclass 40, count 2 2006.286.01:57:59.20#ibcon#about to read 3, iclass 40, count 2 2006.286.01:57:59.22#ibcon#read 3, iclass 40, count 2 2006.286.01:57:59.22#ibcon#about to read 4, iclass 40, count 2 2006.286.01:57:59.22#ibcon#read 4, iclass 40, count 2 2006.286.01:57:59.22#ibcon#about to read 5, iclass 40, count 2 2006.286.01:57:59.22#ibcon#read 5, iclass 40, count 2 2006.286.01:57:59.22#ibcon#about to read 6, iclass 40, count 2 2006.286.01:57:59.22#ibcon#read 6, iclass 40, count 2 2006.286.01:57:59.22#ibcon#end of sib2, iclass 40, count 2 2006.286.01:57:59.22#ibcon#*mode == 0, iclass 40, count 2 2006.286.01:57:59.22#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.01:57:59.22#ibcon#[25=AT02-06\r\n] 2006.286.01:57:59.22#ibcon#*before write, iclass 40, count 2 2006.286.01:57:59.22#ibcon#enter sib2, iclass 40, count 2 2006.286.01:57:59.22#ibcon#flushed, iclass 40, count 2 2006.286.01:57:59.22#ibcon#about to write, iclass 40, count 2 2006.286.01:57:59.22#ibcon#wrote, iclass 40, count 2 2006.286.01:57:59.22#ibcon#about to read 3, iclass 40, count 2 2006.286.01:57:59.25#ibcon#read 3, iclass 40, count 2 2006.286.01:57:59.25#ibcon#about to read 4, iclass 40, count 2 2006.286.01:57:59.25#ibcon#read 4, iclass 40, count 2 2006.286.01:57:59.25#ibcon#about to read 5, iclass 40, count 2 2006.286.01:57:59.25#ibcon#read 5, iclass 40, count 2 2006.286.01:57:59.25#ibcon#about to read 6, iclass 40, count 2 2006.286.01:57:59.25#ibcon#read 6, iclass 40, count 2 2006.286.01:57:59.25#ibcon#end of sib2, iclass 40, count 2 2006.286.01:57:59.25#ibcon#*after write, iclass 40, count 2 2006.286.01:57:59.25#ibcon#*before return 0, iclass 40, count 2 2006.286.01:57:59.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:57:59.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:57:59.25#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.01:57:59.25#ibcon#ireg 7 cls_cnt 0 2006.286.01:57:59.25#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:57:59.37#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:57:59.37#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:57:59.37#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:57:59.37#ibcon#first serial, iclass 40, count 0 2006.286.01:57:59.37#ibcon#enter sib2, iclass 40, count 0 2006.286.01:57:59.37#ibcon#flushed, iclass 40, count 0 2006.286.01:57:59.37#ibcon#about to write, iclass 40, count 0 2006.286.01:57:59.37#ibcon#wrote, iclass 40, count 0 2006.286.01:57:59.37#ibcon#about to read 3, iclass 40, count 0 2006.286.01:57:59.39#ibcon#read 3, iclass 40, count 0 2006.286.01:57:59.39#ibcon#about to read 4, iclass 40, count 0 2006.286.01:57:59.39#ibcon#read 4, iclass 40, count 0 2006.286.01:57:59.39#ibcon#about to read 5, iclass 40, count 0 2006.286.01:57:59.39#ibcon#read 5, iclass 40, count 0 2006.286.01:57:59.39#ibcon#about to read 6, iclass 40, count 0 2006.286.01:57:59.39#ibcon#read 6, iclass 40, count 0 2006.286.01:57:59.39#ibcon#end of sib2, iclass 40, count 0 2006.286.01:57:59.39#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:57:59.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:57:59.39#ibcon#[25=USB\r\n] 2006.286.01:57:59.39#ibcon#*before write, iclass 40, count 0 2006.286.01:57:59.39#ibcon#enter sib2, iclass 40, count 0 2006.286.01:57:59.39#ibcon#flushed, iclass 40, count 0 2006.286.01:57:59.39#ibcon#about to write, iclass 40, count 0 2006.286.01:57:59.39#ibcon#wrote, iclass 40, count 0 2006.286.01:57:59.39#ibcon#about to read 3, iclass 40, count 0 2006.286.01:57:59.42#ibcon#read 3, iclass 40, count 0 2006.286.01:57:59.42#ibcon#about to read 4, iclass 40, count 0 2006.286.01:57:59.42#ibcon#read 4, iclass 40, count 0 2006.286.01:57:59.42#ibcon#about to read 5, iclass 40, count 0 2006.286.01:57:59.42#ibcon#read 5, iclass 40, count 0 2006.286.01:57:59.42#ibcon#about to read 6, iclass 40, count 0 2006.286.01:57:59.42#ibcon#read 6, iclass 40, count 0 2006.286.01:57:59.42#ibcon#end of sib2, iclass 40, count 0 2006.286.01:57:59.42#ibcon#*after write, iclass 40, count 0 2006.286.01:57:59.42#ibcon#*before return 0, iclass 40, count 0 2006.286.01:57:59.42#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:57:59.42#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:57:59.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:57:59.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:57:59.42$vck44/valo=3,564.99 2006.286.01:57:59.42#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.01:57:59.42#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.01:57:59.42#ibcon#ireg 17 cls_cnt 0 2006.286.01:57:59.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:57:59.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:57:59.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:57:59.42#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:57:59.42#ibcon#first serial, iclass 4, count 0 2006.286.01:57:59.42#ibcon#enter sib2, iclass 4, count 0 2006.286.01:57:59.42#ibcon#flushed, iclass 4, count 0 2006.286.01:57:59.42#ibcon#about to write, iclass 4, count 0 2006.286.01:57:59.42#ibcon#wrote, iclass 4, count 0 2006.286.01:57:59.42#ibcon#about to read 3, iclass 4, count 0 2006.286.01:57:59.44#ibcon#read 3, iclass 4, count 0 2006.286.01:57:59.44#ibcon#about to read 4, iclass 4, count 0 2006.286.01:57:59.44#ibcon#read 4, iclass 4, count 0 2006.286.01:57:59.44#ibcon#about to read 5, iclass 4, count 0 2006.286.01:57:59.44#ibcon#read 5, iclass 4, count 0 2006.286.01:57:59.44#ibcon#about to read 6, iclass 4, count 0 2006.286.01:57:59.44#ibcon#read 6, iclass 4, count 0 2006.286.01:57:59.44#ibcon#end of sib2, iclass 4, count 0 2006.286.01:57:59.44#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:57:59.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:57:59.44#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.01:57:59.44#ibcon#*before write, iclass 4, count 0 2006.286.01:57:59.44#ibcon#enter sib2, iclass 4, count 0 2006.286.01:57:59.44#ibcon#flushed, iclass 4, count 0 2006.286.01:57:59.44#ibcon#about to write, iclass 4, count 0 2006.286.01:57:59.44#ibcon#wrote, iclass 4, count 0 2006.286.01:57:59.44#ibcon#about to read 3, iclass 4, count 0 2006.286.01:57:59.48#ibcon#read 3, iclass 4, count 0 2006.286.01:57:59.48#ibcon#about to read 4, iclass 4, count 0 2006.286.01:57:59.48#ibcon#read 4, iclass 4, count 0 2006.286.01:57:59.48#ibcon#about to read 5, iclass 4, count 0 2006.286.01:57:59.48#ibcon#read 5, iclass 4, count 0 2006.286.01:57:59.48#ibcon#about to read 6, iclass 4, count 0 2006.286.01:57:59.48#ibcon#read 6, iclass 4, count 0 2006.286.01:57:59.48#ibcon#end of sib2, iclass 4, count 0 2006.286.01:57:59.48#ibcon#*after write, iclass 4, count 0 2006.286.01:57:59.48#ibcon#*before return 0, iclass 4, count 0 2006.286.01:57:59.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:57:59.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:57:59.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:57:59.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:57:59.48$vck44/va=3,7 2006.286.01:57:59.48#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.01:57:59.48#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.01:57:59.48#ibcon#ireg 11 cls_cnt 2 2006.286.01:57:59.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:57:59.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:57:59.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:57:59.54#ibcon#enter wrdev, iclass 6, count 2 2006.286.01:57:59.54#ibcon#first serial, iclass 6, count 2 2006.286.01:57:59.54#ibcon#enter sib2, iclass 6, count 2 2006.286.01:57:59.54#ibcon#flushed, iclass 6, count 2 2006.286.01:57:59.54#ibcon#about to write, iclass 6, count 2 2006.286.01:57:59.54#ibcon#wrote, iclass 6, count 2 2006.286.01:57:59.54#ibcon#about to read 3, iclass 6, count 2 2006.286.01:57:59.56#ibcon#read 3, iclass 6, count 2 2006.286.01:57:59.56#ibcon#about to read 4, iclass 6, count 2 2006.286.01:57:59.56#ibcon#read 4, iclass 6, count 2 2006.286.01:57:59.56#ibcon#about to read 5, iclass 6, count 2 2006.286.01:57:59.56#ibcon#read 5, iclass 6, count 2 2006.286.01:57:59.56#ibcon#about to read 6, iclass 6, count 2 2006.286.01:57:59.56#ibcon#read 6, iclass 6, count 2 2006.286.01:57:59.56#ibcon#end of sib2, iclass 6, count 2 2006.286.01:57:59.56#ibcon#*mode == 0, iclass 6, count 2 2006.286.01:57:59.56#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.01:57:59.56#ibcon#[25=AT03-07\r\n] 2006.286.01:57:59.56#ibcon#*before write, iclass 6, count 2 2006.286.01:57:59.56#ibcon#enter sib2, iclass 6, count 2 2006.286.01:57:59.56#ibcon#flushed, iclass 6, count 2 2006.286.01:57:59.56#ibcon#about to write, iclass 6, count 2 2006.286.01:57:59.56#ibcon#wrote, iclass 6, count 2 2006.286.01:57:59.56#ibcon#about to read 3, iclass 6, count 2 2006.286.01:57:59.59#ibcon#read 3, iclass 6, count 2 2006.286.01:57:59.59#ibcon#about to read 4, iclass 6, count 2 2006.286.01:57:59.59#ibcon#read 4, iclass 6, count 2 2006.286.01:57:59.59#ibcon#about to read 5, iclass 6, count 2 2006.286.01:57:59.59#ibcon#read 5, iclass 6, count 2 2006.286.01:57:59.59#ibcon#about to read 6, iclass 6, count 2 2006.286.01:57:59.59#ibcon#read 6, iclass 6, count 2 2006.286.01:57:59.59#ibcon#end of sib2, iclass 6, count 2 2006.286.01:57:59.59#ibcon#*after write, iclass 6, count 2 2006.286.01:57:59.59#ibcon#*before return 0, iclass 6, count 2 2006.286.01:57:59.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:57:59.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:57:59.59#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.01:57:59.59#ibcon#ireg 7 cls_cnt 0 2006.286.01:57:59.59#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:57:59.71#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:57:59.71#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:57:59.71#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:57:59.71#ibcon#first serial, iclass 6, count 0 2006.286.01:57:59.71#ibcon#enter sib2, iclass 6, count 0 2006.286.01:57:59.71#ibcon#flushed, iclass 6, count 0 2006.286.01:57:59.71#ibcon#about to write, iclass 6, count 0 2006.286.01:57:59.71#ibcon#wrote, iclass 6, count 0 2006.286.01:57:59.71#ibcon#about to read 3, iclass 6, count 0 2006.286.01:57:59.73#ibcon#read 3, iclass 6, count 0 2006.286.01:57:59.73#ibcon#about to read 4, iclass 6, count 0 2006.286.01:57:59.73#ibcon#read 4, iclass 6, count 0 2006.286.01:57:59.73#ibcon#about to read 5, iclass 6, count 0 2006.286.01:57:59.73#ibcon#read 5, iclass 6, count 0 2006.286.01:57:59.73#ibcon#about to read 6, iclass 6, count 0 2006.286.01:57:59.73#ibcon#read 6, iclass 6, count 0 2006.286.01:57:59.73#ibcon#end of sib2, iclass 6, count 0 2006.286.01:57:59.73#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:57:59.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:57:59.73#ibcon#[25=USB\r\n] 2006.286.01:57:59.73#ibcon#*before write, iclass 6, count 0 2006.286.01:57:59.73#ibcon#enter sib2, iclass 6, count 0 2006.286.01:57:59.73#ibcon#flushed, iclass 6, count 0 2006.286.01:57:59.73#ibcon#about to write, iclass 6, count 0 2006.286.01:57:59.73#ibcon#wrote, iclass 6, count 0 2006.286.01:57:59.73#ibcon#about to read 3, iclass 6, count 0 2006.286.01:57:59.76#ibcon#read 3, iclass 6, count 0 2006.286.01:57:59.76#ibcon#about to read 4, iclass 6, count 0 2006.286.01:57:59.76#ibcon#read 4, iclass 6, count 0 2006.286.01:57:59.76#ibcon#about to read 5, iclass 6, count 0 2006.286.01:57:59.76#ibcon#read 5, iclass 6, count 0 2006.286.01:57:59.76#ibcon#about to read 6, iclass 6, count 0 2006.286.01:57:59.76#ibcon#read 6, iclass 6, count 0 2006.286.01:57:59.76#ibcon#end of sib2, iclass 6, count 0 2006.286.01:57:59.76#ibcon#*after write, iclass 6, count 0 2006.286.01:57:59.76#ibcon#*before return 0, iclass 6, count 0 2006.286.01:57:59.76#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:57:59.76#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:57:59.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:57:59.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:57:59.76$vck44/valo=4,624.99 2006.286.01:57:59.76#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.01:57:59.76#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.01:57:59.76#ibcon#ireg 17 cls_cnt 0 2006.286.01:57:59.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:57:59.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:57:59.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:57:59.76#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:57:59.76#ibcon#first serial, iclass 10, count 0 2006.286.01:57:59.76#ibcon#enter sib2, iclass 10, count 0 2006.286.01:57:59.76#ibcon#flushed, iclass 10, count 0 2006.286.01:57:59.76#ibcon#about to write, iclass 10, count 0 2006.286.01:57:59.76#ibcon#wrote, iclass 10, count 0 2006.286.01:57:59.76#ibcon#about to read 3, iclass 10, count 0 2006.286.01:57:59.78#ibcon#read 3, iclass 10, count 0 2006.286.01:57:59.78#ibcon#about to read 4, iclass 10, count 0 2006.286.01:57:59.78#ibcon#read 4, iclass 10, count 0 2006.286.01:57:59.78#ibcon#about to read 5, iclass 10, count 0 2006.286.01:57:59.78#ibcon#read 5, iclass 10, count 0 2006.286.01:57:59.78#ibcon#about to read 6, iclass 10, count 0 2006.286.01:57:59.78#ibcon#read 6, iclass 10, count 0 2006.286.01:57:59.78#ibcon#end of sib2, iclass 10, count 0 2006.286.01:57:59.78#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:57:59.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:57:59.78#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.01:57:59.78#ibcon#*before write, iclass 10, count 0 2006.286.01:57:59.78#ibcon#enter sib2, iclass 10, count 0 2006.286.01:57:59.78#ibcon#flushed, iclass 10, count 0 2006.286.01:57:59.78#ibcon#about to write, iclass 10, count 0 2006.286.01:57:59.78#ibcon#wrote, iclass 10, count 0 2006.286.01:57:59.78#ibcon#about to read 3, iclass 10, count 0 2006.286.01:57:59.82#ibcon#read 3, iclass 10, count 0 2006.286.01:57:59.82#ibcon#about to read 4, iclass 10, count 0 2006.286.01:57:59.82#ibcon#read 4, iclass 10, count 0 2006.286.01:57:59.82#ibcon#about to read 5, iclass 10, count 0 2006.286.01:57:59.82#ibcon#read 5, iclass 10, count 0 2006.286.01:57:59.82#ibcon#about to read 6, iclass 10, count 0 2006.286.01:57:59.82#ibcon#read 6, iclass 10, count 0 2006.286.01:57:59.82#ibcon#end of sib2, iclass 10, count 0 2006.286.01:57:59.82#ibcon#*after write, iclass 10, count 0 2006.286.01:57:59.82#ibcon#*before return 0, iclass 10, count 0 2006.286.01:57:59.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:57:59.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:57:59.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:57:59.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:57:59.82$vck44/va=4,6 2006.286.01:57:59.82#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.01:57:59.82#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.01:57:59.82#ibcon#ireg 11 cls_cnt 2 2006.286.01:57:59.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:57:59.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:57:59.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:57:59.88#ibcon#enter wrdev, iclass 12, count 2 2006.286.01:57:59.88#ibcon#first serial, iclass 12, count 2 2006.286.01:57:59.88#ibcon#enter sib2, iclass 12, count 2 2006.286.01:57:59.88#ibcon#flushed, iclass 12, count 2 2006.286.01:57:59.88#ibcon#about to write, iclass 12, count 2 2006.286.01:57:59.88#ibcon#wrote, iclass 12, count 2 2006.286.01:57:59.88#ibcon#about to read 3, iclass 12, count 2 2006.286.01:57:59.90#ibcon#read 3, iclass 12, count 2 2006.286.01:57:59.90#ibcon#about to read 4, iclass 12, count 2 2006.286.01:57:59.90#ibcon#read 4, iclass 12, count 2 2006.286.01:57:59.90#ibcon#about to read 5, iclass 12, count 2 2006.286.01:57:59.90#ibcon#read 5, iclass 12, count 2 2006.286.01:57:59.90#ibcon#about to read 6, iclass 12, count 2 2006.286.01:57:59.90#ibcon#read 6, iclass 12, count 2 2006.286.01:57:59.90#ibcon#end of sib2, iclass 12, count 2 2006.286.01:57:59.90#ibcon#*mode == 0, iclass 12, count 2 2006.286.01:57:59.90#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.01:57:59.90#ibcon#[25=AT04-06\r\n] 2006.286.01:57:59.90#ibcon#*before write, iclass 12, count 2 2006.286.01:57:59.90#ibcon#enter sib2, iclass 12, count 2 2006.286.01:57:59.90#ibcon#flushed, iclass 12, count 2 2006.286.01:57:59.90#ibcon#about to write, iclass 12, count 2 2006.286.01:57:59.90#ibcon#wrote, iclass 12, count 2 2006.286.01:57:59.90#ibcon#about to read 3, iclass 12, count 2 2006.286.01:57:59.93#ibcon#read 3, iclass 12, count 2 2006.286.01:57:59.93#ibcon#about to read 4, iclass 12, count 2 2006.286.01:57:59.93#ibcon#read 4, iclass 12, count 2 2006.286.01:57:59.93#ibcon#about to read 5, iclass 12, count 2 2006.286.01:57:59.93#ibcon#read 5, iclass 12, count 2 2006.286.01:57:59.93#ibcon#about to read 6, iclass 12, count 2 2006.286.01:57:59.93#ibcon#read 6, iclass 12, count 2 2006.286.01:57:59.93#ibcon#end of sib2, iclass 12, count 2 2006.286.01:57:59.93#ibcon#*after write, iclass 12, count 2 2006.286.01:57:59.93#ibcon#*before return 0, iclass 12, count 2 2006.286.01:57:59.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:57:59.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:57:59.93#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.01:57:59.93#ibcon#ireg 7 cls_cnt 0 2006.286.01:57:59.93#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:58:00.05#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:58:00.05#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:58:00.05#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:58:00.05#ibcon#first serial, iclass 12, count 0 2006.286.01:58:00.05#ibcon#enter sib2, iclass 12, count 0 2006.286.01:58:00.05#ibcon#flushed, iclass 12, count 0 2006.286.01:58:00.05#ibcon#about to write, iclass 12, count 0 2006.286.01:58:00.05#ibcon#wrote, iclass 12, count 0 2006.286.01:58:00.05#ibcon#about to read 3, iclass 12, count 0 2006.286.01:58:00.07#ibcon#read 3, iclass 12, count 0 2006.286.01:58:00.07#ibcon#about to read 4, iclass 12, count 0 2006.286.01:58:00.07#ibcon#read 4, iclass 12, count 0 2006.286.01:58:00.07#ibcon#about to read 5, iclass 12, count 0 2006.286.01:58:00.07#ibcon#read 5, iclass 12, count 0 2006.286.01:58:00.07#ibcon#about to read 6, iclass 12, count 0 2006.286.01:58:00.07#ibcon#read 6, iclass 12, count 0 2006.286.01:58:00.07#ibcon#end of sib2, iclass 12, count 0 2006.286.01:58:00.07#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:58:00.07#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:58:00.07#ibcon#[25=USB\r\n] 2006.286.01:58:00.07#ibcon#*before write, iclass 12, count 0 2006.286.01:58:00.07#ibcon#enter sib2, iclass 12, count 0 2006.286.01:58:00.07#ibcon#flushed, iclass 12, count 0 2006.286.01:58:00.07#ibcon#about to write, iclass 12, count 0 2006.286.01:58:00.07#ibcon#wrote, iclass 12, count 0 2006.286.01:58:00.07#ibcon#about to read 3, iclass 12, count 0 2006.286.01:58:00.10#ibcon#read 3, iclass 12, count 0 2006.286.01:58:00.10#ibcon#about to read 4, iclass 12, count 0 2006.286.01:58:00.10#ibcon#read 4, iclass 12, count 0 2006.286.01:58:00.10#ibcon#about to read 5, iclass 12, count 0 2006.286.01:58:00.10#ibcon#read 5, iclass 12, count 0 2006.286.01:58:00.10#ibcon#about to read 6, iclass 12, count 0 2006.286.01:58:00.10#ibcon#read 6, iclass 12, count 0 2006.286.01:58:00.10#ibcon#end of sib2, iclass 12, count 0 2006.286.01:58:00.10#ibcon#*after write, iclass 12, count 0 2006.286.01:58:00.10#ibcon#*before return 0, iclass 12, count 0 2006.286.01:58:00.10#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:58:00.10#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:58:00.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:58:00.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:58:00.10$vck44/valo=5,734.99 2006.286.01:58:00.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.01:58:00.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.01:58:00.10#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:00.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:58:00.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:58:00.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:58:00.10#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:58:00.10#ibcon#first serial, iclass 14, count 0 2006.286.01:58:00.10#ibcon#enter sib2, iclass 14, count 0 2006.286.01:58:00.10#ibcon#flushed, iclass 14, count 0 2006.286.01:58:00.10#ibcon#about to write, iclass 14, count 0 2006.286.01:58:00.10#ibcon#wrote, iclass 14, count 0 2006.286.01:58:00.10#ibcon#about to read 3, iclass 14, count 0 2006.286.01:58:00.12#ibcon#read 3, iclass 14, count 0 2006.286.01:58:00.12#ibcon#about to read 4, iclass 14, count 0 2006.286.01:58:00.12#ibcon#read 4, iclass 14, count 0 2006.286.01:58:00.12#ibcon#about to read 5, iclass 14, count 0 2006.286.01:58:00.12#ibcon#read 5, iclass 14, count 0 2006.286.01:58:00.12#ibcon#about to read 6, iclass 14, count 0 2006.286.01:58:00.12#ibcon#read 6, iclass 14, count 0 2006.286.01:58:00.12#ibcon#end of sib2, iclass 14, count 0 2006.286.01:58:00.12#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:58:00.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:58:00.12#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.01:58:00.12#ibcon#*before write, iclass 14, count 0 2006.286.01:58:00.12#ibcon#enter sib2, iclass 14, count 0 2006.286.01:58:00.12#ibcon#flushed, iclass 14, count 0 2006.286.01:58:00.12#ibcon#about to write, iclass 14, count 0 2006.286.01:58:00.12#ibcon#wrote, iclass 14, count 0 2006.286.01:58:00.12#ibcon#about to read 3, iclass 14, count 0 2006.286.01:58:00.16#ibcon#read 3, iclass 14, count 0 2006.286.01:58:00.16#ibcon#about to read 4, iclass 14, count 0 2006.286.01:58:00.16#ibcon#read 4, iclass 14, count 0 2006.286.01:58:00.16#ibcon#about to read 5, iclass 14, count 0 2006.286.01:58:00.16#ibcon#read 5, iclass 14, count 0 2006.286.01:58:00.16#ibcon#about to read 6, iclass 14, count 0 2006.286.01:58:00.16#ibcon#read 6, iclass 14, count 0 2006.286.01:58:00.16#ibcon#end of sib2, iclass 14, count 0 2006.286.01:58:00.16#ibcon#*after write, iclass 14, count 0 2006.286.01:58:00.16#ibcon#*before return 0, iclass 14, count 0 2006.286.01:58:00.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:58:00.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:58:00.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:58:00.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:58:00.16$vck44/va=5,3 2006.286.01:58:00.16#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.01:58:00.16#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.01:58:00.16#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:00.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:58:00.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:58:00.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:58:00.22#ibcon#enter wrdev, iclass 16, count 2 2006.286.01:58:00.22#ibcon#first serial, iclass 16, count 2 2006.286.01:58:00.22#ibcon#enter sib2, iclass 16, count 2 2006.286.01:58:00.22#ibcon#flushed, iclass 16, count 2 2006.286.01:58:00.22#ibcon#about to write, iclass 16, count 2 2006.286.01:58:00.22#ibcon#wrote, iclass 16, count 2 2006.286.01:58:00.22#ibcon#about to read 3, iclass 16, count 2 2006.286.01:58:00.24#ibcon#read 3, iclass 16, count 2 2006.286.01:58:00.24#ibcon#about to read 4, iclass 16, count 2 2006.286.01:58:00.24#ibcon#read 4, iclass 16, count 2 2006.286.01:58:00.24#ibcon#about to read 5, iclass 16, count 2 2006.286.01:58:00.24#ibcon#read 5, iclass 16, count 2 2006.286.01:58:00.24#ibcon#about to read 6, iclass 16, count 2 2006.286.01:58:00.24#ibcon#read 6, iclass 16, count 2 2006.286.01:58:00.24#ibcon#end of sib2, iclass 16, count 2 2006.286.01:58:00.24#ibcon#*mode == 0, iclass 16, count 2 2006.286.01:58:00.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.01:58:00.24#ibcon#[25=AT05-03\r\n] 2006.286.01:58:00.24#ibcon#*before write, iclass 16, count 2 2006.286.01:58:00.24#ibcon#enter sib2, iclass 16, count 2 2006.286.01:58:00.24#ibcon#flushed, iclass 16, count 2 2006.286.01:58:00.24#ibcon#about to write, iclass 16, count 2 2006.286.01:58:00.24#ibcon#wrote, iclass 16, count 2 2006.286.01:58:00.24#ibcon#about to read 3, iclass 16, count 2 2006.286.01:58:00.27#ibcon#read 3, iclass 16, count 2 2006.286.01:58:00.27#ibcon#about to read 4, iclass 16, count 2 2006.286.01:58:00.27#ibcon#read 4, iclass 16, count 2 2006.286.01:58:00.27#ibcon#about to read 5, iclass 16, count 2 2006.286.01:58:00.27#ibcon#read 5, iclass 16, count 2 2006.286.01:58:00.27#ibcon#about to read 6, iclass 16, count 2 2006.286.01:58:00.27#ibcon#read 6, iclass 16, count 2 2006.286.01:58:00.27#ibcon#end of sib2, iclass 16, count 2 2006.286.01:58:00.27#ibcon#*after write, iclass 16, count 2 2006.286.01:58:00.27#ibcon#*before return 0, iclass 16, count 2 2006.286.01:58:00.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:58:00.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:58:00.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.01:58:00.27#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:00.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:58:00.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:58:00.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:58:00.39#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:58:00.39#ibcon#first serial, iclass 16, count 0 2006.286.01:58:00.39#ibcon#enter sib2, iclass 16, count 0 2006.286.01:58:00.39#ibcon#flushed, iclass 16, count 0 2006.286.01:58:00.39#ibcon#about to write, iclass 16, count 0 2006.286.01:58:00.39#ibcon#wrote, iclass 16, count 0 2006.286.01:58:00.39#ibcon#about to read 3, iclass 16, count 0 2006.286.01:58:00.41#ibcon#read 3, iclass 16, count 0 2006.286.01:58:00.41#ibcon#about to read 4, iclass 16, count 0 2006.286.01:58:00.41#ibcon#read 4, iclass 16, count 0 2006.286.01:58:00.41#ibcon#about to read 5, iclass 16, count 0 2006.286.01:58:00.41#ibcon#read 5, iclass 16, count 0 2006.286.01:58:00.41#ibcon#about to read 6, iclass 16, count 0 2006.286.01:58:00.41#ibcon#read 6, iclass 16, count 0 2006.286.01:58:00.41#ibcon#end of sib2, iclass 16, count 0 2006.286.01:58:00.41#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:58:00.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:58:00.41#ibcon#[25=USB\r\n] 2006.286.01:58:00.41#ibcon#*before write, iclass 16, count 0 2006.286.01:58:00.41#ibcon#enter sib2, iclass 16, count 0 2006.286.01:58:00.41#ibcon#flushed, iclass 16, count 0 2006.286.01:58:00.41#ibcon#about to write, iclass 16, count 0 2006.286.01:58:00.41#ibcon#wrote, iclass 16, count 0 2006.286.01:58:00.41#ibcon#about to read 3, iclass 16, count 0 2006.286.01:58:00.44#ibcon#read 3, iclass 16, count 0 2006.286.01:58:00.44#ibcon#about to read 4, iclass 16, count 0 2006.286.01:58:00.44#ibcon#read 4, iclass 16, count 0 2006.286.01:58:00.44#ibcon#about to read 5, iclass 16, count 0 2006.286.01:58:00.44#ibcon#read 5, iclass 16, count 0 2006.286.01:58:00.44#ibcon#about to read 6, iclass 16, count 0 2006.286.01:58:00.44#ibcon#read 6, iclass 16, count 0 2006.286.01:58:00.44#ibcon#end of sib2, iclass 16, count 0 2006.286.01:58:00.44#ibcon#*after write, iclass 16, count 0 2006.286.01:58:00.44#ibcon#*before return 0, iclass 16, count 0 2006.286.01:58:00.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:58:00.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:58:00.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:58:00.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:58:00.44$vck44/valo=6,814.99 2006.286.01:58:00.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.01:58:00.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.01:58:00.44#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:00.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:58:00.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:58:00.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:58:00.44#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:58:00.44#ibcon#first serial, iclass 18, count 0 2006.286.01:58:00.44#ibcon#enter sib2, iclass 18, count 0 2006.286.01:58:00.44#ibcon#flushed, iclass 18, count 0 2006.286.01:58:00.44#ibcon#about to write, iclass 18, count 0 2006.286.01:58:00.44#ibcon#wrote, iclass 18, count 0 2006.286.01:58:00.44#ibcon#about to read 3, iclass 18, count 0 2006.286.01:58:00.46#ibcon#read 3, iclass 18, count 0 2006.286.01:58:00.46#ibcon#about to read 4, iclass 18, count 0 2006.286.01:58:00.46#ibcon#read 4, iclass 18, count 0 2006.286.01:58:00.46#ibcon#about to read 5, iclass 18, count 0 2006.286.01:58:00.46#ibcon#read 5, iclass 18, count 0 2006.286.01:58:00.46#ibcon#about to read 6, iclass 18, count 0 2006.286.01:58:00.46#ibcon#read 6, iclass 18, count 0 2006.286.01:58:00.46#ibcon#end of sib2, iclass 18, count 0 2006.286.01:58:00.46#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:58:00.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:58:00.46#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.01:58:00.46#ibcon#*before write, iclass 18, count 0 2006.286.01:58:00.46#ibcon#enter sib2, iclass 18, count 0 2006.286.01:58:00.46#ibcon#flushed, iclass 18, count 0 2006.286.01:58:00.46#ibcon#about to write, iclass 18, count 0 2006.286.01:58:00.46#ibcon#wrote, iclass 18, count 0 2006.286.01:58:00.46#ibcon#about to read 3, iclass 18, count 0 2006.286.01:58:00.50#ibcon#read 3, iclass 18, count 0 2006.286.01:58:00.50#ibcon#about to read 4, iclass 18, count 0 2006.286.01:58:00.50#ibcon#read 4, iclass 18, count 0 2006.286.01:58:00.50#ibcon#about to read 5, iclass 18, count 0 2006.286.01:58:00.50#ibcon#read 5, iclass 18, count 0 2006.286.01:58:00.50#ibcon#about to read 6, iclass 18, count 0 2006.286.01:58:00.50#ibcon#read 6, iclass 18, count 0 2006.286.01:58:00.50#ibcon#end of sib2, iclass 18, count 0 2006.286.01:58:00.50#ibcon#*after write, iclass 18, count 0 2006.286.01:58:00.50#ibcon#*before return 0, iclass 18, count 0 2006.286.01:58:00.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:58:00.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:58:00.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:58:00.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:58:00.50$vck44/va=6,4 2006.286.01:58:00.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.01:58:00.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.01:58:00.50#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:00.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:58:00.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:58:00.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:58:00.56#ibcon#enter wrdev, iclass 20, count 2 2006.286.01:58:00.56#ibcon#first serial, iclass 20, count 2 2006.286.01:58:00.56#ibcon#enter sib2, iclass 20, count 2 2006.286.01:58:00.56#ibcon#flushed, iclass 20, count 2 2006.286.01:58:00.56#ibcon#about to write, iclass 20, count 2 2006.286.01:58:00.56#ibcon#wrote, iclass 20, count 2 2006.286.01:58:00.56#ibcon#about to read 3, iclass 20, count 2 2006.286.01:58:00.58#ibcon#read 3, iclass 20, count 2 2006.286.01:58:00.58#ibcon#about to read 4, iclass 20, count 2 2006.286.01:58:00.58#ibcon#read 4, iclass 20, count 2 2006.286.01:58:00.58#ibcon#about to read 5, iclass 20, count 2 2006.286.01:58:00.58#ibcon#read 5, iclass 20, count 2 2006.286.01:58:00.58#ibcon#about to read 6, iclass 20, count 2 2006.286.01:58:00.58#ibcon#read 6, iclass 20, count 2 2006.286.01:58:00.58#ibcon#end of sib2, iclass 20, count 2 2006.286.01:58:00.58#ibcon#*mode == 0, iclass 20, count 2 2006.286.01:58:00.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.01:58:00.58#ibcon#[25=AT06-04\r\n] 2006.286.01:58:00.58#ibcon#*before write, iclass 20, count 2 2006.286.01:58:00.58#ibcon#enter sib2, iclass 20, count 2 2006.286.01:58:00.58#ibcon#flushed, iclass 20, count 2 2006.286.01:58:00.58#ibcon#about to write, iclass 20, count 2 2006.286.01:58:00.58#ibcon#wrote, iclass 20, count 2 2006.286.01:58:00.58#ibcon#about to read 3, iclass 20, count 2 2006.286.01:58:00.61#ibcon#read 3, iclass 20, count 2 2006.286.01:58:00.61#ibcon#about to read 4, iclass 20, count 2 2006.286.01:58:00.61#ibcon#read 4, iclass 20, count 2 2006.286.01:58:00.61#ibcon#about to read 5, iclass 20, count 2 2006.286.01:58:00.61#ibcon#read 5, iclass 20, count 2 2006.286.01:58:00.61#ibcon#about to read 6, iclass 20, count 2 2006.286.01:58:00.61#ibcon#read 6, iclass 20, count 2 2006.286.01:58:00.61#ibcon#end of sib2, iclass 20, count 2 2006.286.01:58:00.61#ibcon#*after write, iclass 20, count 2 2006.286.01:58:00.61#ibcon#*before return 0, iclass 20, count 2 2006.286.01:58:00.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:58:00.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:58:00.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.01:58:00.61#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:00.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:58:00.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:58:00.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:58:00.73#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:58:00.73#ibcon#first serial, iclass 20, count 0 2006.286.01:58:00.73#ibcon#enter sib2, iclass 20, count 0 2006.286.01:58:00.73#ibcon#flushed, iclass 20, count 0 2006.286.01:58:00.73#ibcon#about to write, iclass 20, count 0 2006.286.01:58:00.73#ibcon#wrote, iclass 20, count 0 2006.286.01:58:00.73#ibcon#about to read 3, iclass 20, count 0 2006.286.01:58:00.75#ibcon#read 3, iclass 20, count 0 2006.286.01:58:00.75#ibcon#about to read 4, iclass 20, count 0 2006.286.01:58:00.75#ibcon#read 4, iclass 20, count 0 2006.286.01:58:00.75#ibcon#about to read 5, iclass 20, count 0 2006.286.01:58:00.75#ibcon#read 5, iclass 20, count 0 2006.286.01:58:00.75#ibcon#about to read 6, iclass 20, count 0 2006.286.01:58:00.75#ibcon#read 6, iclass 20, count 0 2006.286.01:58:00.75#ibcon#end of sib2, iclass 20, count 0 2006.286.01:58:00.75#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:58:00.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:58:00.75#ibcon#[25=USB\r\n] 2006.286.01:58:00.75#ibcon#*before write, iclass 20, count 0 2006.286.01:58:00.75#ibcon#enter sib2, iclass 20, count 0 2006.286.01:58:00.75#ibcon#flushed, iclass 20, count 0 2006.286.01:58:00.75#ibcon#about to write, iclass 20, count 0 2006.286.01:58:00.75#ibcon#wrote, iclass 20, count 0 2006.286.01:58:00.75#ibcon#about to read 3, iclass 20, count 0 2006.286.01:58:00.78#ibcon#read 3, iclass 20, count 0 2006.286.01:58:00.78#ibcon#about to read 4, iclass 20, count 0 2006.286.01:58:00.78#ibcon#read 4, iclass 20, count 0 2006.286.01:58:00.78#ibcon#about to read 5, iclass 20, count 0 2006.286.01:58:00.78#ibcon#read 5, iclass 20, count 0 2006.286.01:58:00.78#ibcon#about to read 6, iclass 20, count 0 2006.286.01:58:00.78#ibcon#read 6, iclass 20, count 0 2006.286.01:58:00.78#ibcon#end of sib2, iclass 20, count 0 2006.286.01:58:00.78#ibcon#*after write, iclass 20, count 0 2006.286.01:58:00.78#ibcon#*before return 0, iclass 20, count 0 2006.286.01:58:00.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:58:00.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:58:00.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:58:00.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:58:00.78$vck44/valo=7,864.99 2006.286.01:58:00.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.01:58:00.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.01:58:00.78#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:00.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:58:00.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:58:00.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:58:00.78#ibcon#enter wrdev, iclass 22, count 0 2006.286.01:58:00.78#ibcon#first serial, iclass 22, count 0 2006.286.01:58:00.78#ibcon#enter sib2, iclass 22, count 0 2006.286.01:58:00.78#ibcon#flushed, iclass 22, count 0 2006.286.01:58:00.78#ibcon#about to write, iclass 22, count 0 2006.286.01:58:00.78#ibcon#wrote, iclass 22, count 0 2006.286.01:58:00.78#ibcon#about to read 3, iclass 22, count 0 2006.286.01:58:00.80#ibcon#read 3, iclass 22, count 0 2006.286.01:58:00.80#ibcon#about to read 4, iclass 22, count 0 2006.286.01:58:00.80#ibcon#read 4, iclass 22, count 0 2006.286.01:58:00.80#ibcon#about to read 5, iclass 22, count 0 2006.286.01:58:00.80#ibcon#read 5, iclass 22, count 0 2006.286.01:58:00.80#ibcon#about to read 6, iclass 22, count 0 2006.286.01:58:00.80#ibcon#read 6, iclass 22, count 0 2006.286.01:58:00.80#ibcon#end of sib2, iclass 22, count 0 2006.286.01:58:00.80#ibcon#*mode == 0, iclass 22, count 0 2006.286.01:58:00.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.01:58:00.80#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.01:58:00.80#ibcon#*before write, iclass 22, count 0 2006.286.01:58:00.80#ibcon#enter sib2, iclass 22, count 0 2006.286.01:58:00.80#ibcon#flushed, iclass 22, count 0 2006.286.01:58:00.80#ibcon#about to write, iclass 22, count 0 2006.286.01:58:00.80#ibcon#wrote, iclass 22, count 0 2006.286.01:58:00.80#ibcon#about to read 3, iclass 22, count 0 2006.286.01:58:00.84#ibcon#read 3, iclass 22, count 0 2006.286.01:58:00.84#ibcon#about to read 4, iclass 22, count 0 2006.286.01:58:00.84#ibcon#read 4, iclass 22, count 0 2006.286.01:58:00.84#ibcon#about to read 5, iclass 22, count 0 2006.286.01:58:00.84#ibcon#read 5, iclass 22, count 0 2006.286.01:58:00.84#ibcon#about to read 6, iclass 22, count 0 2006.286.01:58:00.84#ibcon#read 6, iclass 22, count 0 2006.286.01:58:00.84#ibcon#end of sib2, iclass 22, count 0 2006.286.01:58:00.84#ibcon#*after write, iclass 22, count 0 2006.286.01:58:00.84#ibcon#*before return 0, iclass 22, count 0 2006.286.01:58:00.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:58:00.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:58:00.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.01:58:00.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.01:58:00.84$vck44/va=7,4 2006.286.01:58:00.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.01:58:00.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.01:58:00.84#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:00.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:58:00.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:58:00.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:58:00.90#ibcon#enter wrdev, iclass 24, count 2 2006.286.01:58:00.90#ibcon#first serial, iclass 24, count 2 2006.286.01:58:00.90#ibcon#enter sib2, iclass 24, count 2 2006.286.01:58:00.90#ibcon#flushed, iclass 24, count 2 2006.286.01:58:00.90#ibcon#about to write, iclass 24, count 2 2006.286.01:58:00.90#ibcon#wrote, iclass 24, count 2 2006.286.01:58:00.90#ibcon#about to read 3, iclass 24, count 2 2006.286.01:58:00.92#ibcon#read 3, iclass 24, count 2 2006.286.01:58:00.92#ibcon#about to read 4, iclass 24, count 2 2006.286.01:58:00.92#ibcon#read 4, iclass 24, count 2 2006.286.01:58:00.92#ibcon#about to read 5, iclass 24, count 2 2006.286.01:58:00.92#ibcon#read 5, iclass 24, count 2 2006.286.01:58:00.92#ibcon#about to read 6, iclass 24, count 2 2006.286.01:58:00.92#ibcon#read 6, iclass 24, count 2 2006.286.01:58:00.92#ibcon#end of sib2, iclass 24, count 2 2006.286.01:58:00.92#ibcon#*mode == 0, iclass 24, count 2 2006.286.01:58:00.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.01:58:00.92#ibcon#[25=AT07-04\r\n] 2006.286.01:58:00.92#ibcon#*before write, iclass 24, count 2 2006.286.01:58:00.92#ibcon#enter sib2, iclass 24, count 2 2006.286.01:58:00.92#ibcon#flushed, iclass 24, count 2 2006.286.01:58:00.92#ibcon#about to write, iclass 24, count 2 2006.286.01:58:00.92#ibcon#wrote, iclass 24, count 2 2006.286.01:58:00.92#ibcon#about to read 3, iclass 24, count 2 2006.286.01:58:00.95#ibcon#read 3, iclass 24, count 2 2006.286.01:58:00.95#ibcon#about to read 4, iclass 24, count 2 2006.286.01:58:00.95#ibcon#read 4, iclass 24, count 2 2006.286.01:58:00.95#ibcon#about to read 5, iclass 24, count 2 2006.286.01:58:00.95#ibcon#read 5, iclass 24, count 2 2006.286.01:58:00.95#ibcon#about to read 6, iclass 24, count 2 2006.286.01:58:00.95#ibcon#read 6, iclass 24, count 2 2006.286.01:58:00.95#ibcon#end of sib2, iclass 24, count 2 2006.286.01:58:00.95#ibcon#*after write, iclass 24, count 2 2006.286.01:58:00.95#ibcon#*before return 0, iclass 24, count 2 2006.286.01:58:00.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:58:00.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:58:00.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.01:58:00.95#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:00.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:58:01.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:58:01.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:58:01.07#ibcon#enter wrdev, iclass 24, count 0 2006.286.01:58:01.07#ibcon#first serial, iclass 24, count 0 2006.286.01:58:01.07#ibcon#enter sib2, iclass 24, count 0 2006.286.01:58:01.07#ibcon#flushed, iclass 24, count 0 2006.286.01:58:01.07#ibcon#about to write, iclass 24, count 0 2006.286.01:58:01.07#ibcon#wrote, iclass 24, count 0 2006.286.01:58:01.07#ibcon#about to read 3, iclass 24, count 0 2006.286.01:58:01.09#ibcon#read 3, iclass 24, count 0 2006.286.01:58:01.09#ibcon#about to read 4, iclass 24, count 0 2006.286.01:58:01.09#ibcon#read 4, iclass 24, count 0 2006.286.01:58:01.09#ibcon#about to read 5, iclass 24, count 0 2006.286.01:58:01.09#ibcon#read 5, iclass 24, count 0 2006.286.01:58:01.09#ibcon#about to read 6, iclass 24, count 0 2006.286.01:58:01.09#ibcon#read 6, iclass 24, count 0 2006.286.01:58:01.09#ibcon#end of sib2, iclass 24, count 0 2006.286.01:58:01.09#ibcon#*mode == 0, iclass 24, count 0 2006.286.01:58:01.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.01:58:01.09#ibcon#[25=USB\r\n] 2006.286.01:58:01.09#ibcon#*before write, iclass 24, count 0 2006.286.01:58:01.09#ibcon#enter sib2, iclass 24, count 0 2006.286.01:58:01.09#ibcon#flushed, iclass 24, count 0 2006.286.01:58:01.09#ibcon#about to write, iclass 24, count 0 2006.286.01:58:01.09#ibcon#wrote, iclass 24, count 0 2006.286.01:58:01.09#ibcon#about to read 3, iclass 24, count 0 2006.286.01:58:01.12#ibcon#read 3, iclass 24, count 0 2006.286.01:58:01.12#ibcon#about to read 4, iclass 24, count 0 2006.286.01:58:01.12#ibcon#read 4, iclass 24, count 0 2006.286.01:58:01.12#ibcon#about to read 5, iclass 24, count 0 2006.286.01:58:01.12#ibcon#read 5, iclass 24, count 0 2006.286.01:58:01.12#ibcon#about to read 6, iclass 24, count 0 2006.286.01:58:01.12#ibcon#read 6, iclass 24, count 0 2006.286.01:58:01.12#ibcon#end of sib2, iclass 24, count 0 2006.286.01:58:01.12#ibcon#*after write, iclass 24, count 0 2006.286.01:58:01.12#ibcon#*before return 0, iclass 24, count 0 2006.286.01:58:01.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:58:01.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:58:01.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.01:58:01.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.01:58:01.12$vck44/valo=8,884.99 2006.286.01:58:01.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.01:58:01.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.01:58:01.12#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:01.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:58:01.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:58:01.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:58:01.12#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:58:01.12#ibcon#first serial, iclass 26, count 0 2006.286.01:58:01.12#ibcon#enter sib2, iclass 26, count 0 2006.286.01:58:01.12#ibcon#flushed, iclass 26, count 0 2006.286.01:58:01.12#ibcon#about to write, iclass 26, count 0 2006.286.01:58:01.12#ibcon#wrote, iclass 26, count 0 2006.286.01:58:01.12#ibcon#about to read 3, iclass 26, count 0 2006.286.01:58:01.14#ibcon#read 3, iclass 26, count 0 2006.286.01:58:01.14#ibcon#about to read 4, iclass 26, count 0 2006.286.01:58:01.14#ibcon#read 4, iclass 26, count 0 2006.286.01:58:01.14#ibcon#about to read 5, iclass 26, count 0 2006.286.01:58:01.14#ibcon#read 5, iclass 26, count 0 2006.286.01:58:01.14#ibcon#about to read 6, iclass 26, count 0 2006.286.01:58:01.14#ibcon#read 6, iclass 26, count 0 2006.286.01:58:01.14#ibcon#end of sib2, iclass 26, count 0 2006.286.01:58:01.14#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:58:01.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:58:01.14#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.01:58:01.14#ibcon#*before write, iclass 26, count 0 2006.286.01:58:01.14#ibcon#enter sib2, iclass 26, count 0 2006.286.01:58:01.14#ibcon#flushed, iclass 26, count 0 2006.286.01:58:01.14#ibcon#about to write, iclass 26, count 0 2006.286.01:58:01.14#ibcon#wrote, iclass 26, count 0 2006.286.01:58:01.14#ibcon#about to read 3, iclass 26, count 0 2006.286.01:58:01.18#ibcon#read 3, iclass 26, count 0 2006.286.01:58:01.18#ibcon#about to read 4, iclass 26, count 0 2006.286.01:58:01.18#ibcon#read 4, iclass 26, count 0 2006.286.01:58:01.18#ibcon#about to read 5, iclass 26, count 0 2006.286.01:58:01.18#ibcon#read 5, iclass 26, count 0 2006.286.01:58:01.18#ibcon#about to read 6, iclass 26, count 0 2006.286.01:58:01.18#ibcon#read 6, iclass 26, count 0 2006.286.01:58:01.18#ibcon#end of sib2, iclass 26, count 0 2006.286.01:58:01.18#ibcon#*after write, iclass 26, count 0 2006.286.01:58:01.18#ibcon#*before return 0, iclass 26, count 0 2006.286.01:58:01.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:58:01.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:58:01.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:58:01.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:58:01.18$vck44/va=8,3 2006.286.01:58:01.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.01:58:01.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.01:58:01.18#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:01.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:58:01.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:58:01.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:58:01.24#ibcon#enter wrdev, iclass 28, count 2 2006.286.01:58:01.24#ibcon#first serial, iclass 28, count 2 2006.286.01:58:01.24#ibcon#enter sib2, iclass 28, count 2 2006.286.01:58:01.24#ibcon#flushed, iclass 28, count 2 2006.286.01:58:01.24#ibcon#about to write, iclass 28, count 2 2006.286.01:58:01.24#ibcon#wrote, iclass 28, count 2 2006.286.01:58:01.24#ibcon#about to read 3, iclass 28, count 2 2006.286.01:58:01.26#ibcon#read 3, iclass 28, count 2 2006.286.01:58:01.26#ibcon#about to read 4, iclass 28, count 2 2006.286.01:58:01.26#ibcon#read 4, iclass 28, count 2 2006.286.01:58:01.26#ibcon#about to read 5, iclass 28, count 2 2006.286.01:58:01.26#ibcon#read 5, iclass 28, count 2 2006.286.01:58:01.26#ibcon#about to read 6, iclass 28, count 2 2006.286.01:58:01.26#ibcon#read 6, iclass 28, count 2 2006.286.01:58:01.26#ibcon#end of sib2, iclass 28, count 2 2006.286.01:58:01.26#ibcon#*mode == 0, iclass 28, count 2 2006.286.01:58:01.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.01:58:01.26#ibcon#[25=AT08-03\r\n] 2006.286.01:58:01.26#ibcon#*before write, iclass 28, count 2 2006.286.01:58:01.26#ibcon#enter sib2, iclass 28, count 2 2006.286.01:58:01.26#ibcon#flushed, iclass 28, count 2 2006.286.01:58:01.26#ibcon#about to write, iclass 28, count 2 2006.286.01:58:01.26#ibcon#wrote, iclass 28, count 2 2006.286.01:58:01.26#ibcon#about to read 3, iclass 28, count 2 2006.286.01:58:01.29#ibcon#read 3, iclass 28, count 2 2006.286.01:58:01.29#ibcon#about to read 4, iclass 28, count 2 2006.286.01:58:01.29#ibcon#read 4, iclass 28, count 2 2006.286.01:58:01.29#ibcon#about to read 5, iclass 28, count 2 2006.286.01:58:01.29#ibcon#read 5, iclass 28, count 2 2006.286.01:58:01.29#ibcon#about to read 6, iclass 28, count 2 2006.286.01:58:01.29#ibcon#read 6, iclass 28, count 2 2006.286.01:58:01.29#ibcon#end of sib2, iclass 28, count 2 2006.286.01:58:01.29#ibcon#*after write, iclass 28, count 2 2006.286.01:58:01.29#ibcon#*before return 0, iclass 28, count 2 2006.286.01:58:01.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:58:01.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.01:58:01.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.01:58:01.29#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:01.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:58:01.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:58:01.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:58:01.41#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:58:01.41#ibcon#first serial, iclass 28, count 0 2006.286.01:58:01.41#ibcon#enter sib2, iclass 28, count 0 2006.286.01:58:01.41#ibcon#flushed, iclass 28, count 0 2006.286.01:58:01.41#ibcon#about to write, iclass 28, count 0 2006.286.01:58:01.41#ibcon#wrote, iclass 28, count 0 2006.286.01:58:01.41#ibcon#about to read 3, iclass 28, count 0 2006.286.01:58:01.43#ibcon#read 3, iclass 28, count 0 2006.286.01:58:01.43#ibcon#about to read 4, iclass 28, count 0 2006.286.01:58:01.43#ibcon#read 4, iclass 28, count 0 2006.286.01:58:01.43#ibcon#about to read 5, iclass 28, count 0 2006.286.01:58:01.43#ibcon#read 5, iclass 28, count 0 2006.286.01:58:01.43#ibcon#about to read 6, iclass 28, count 0 2006.286.01:58:01.43#ibcon#read 6, iclass 28, count 0 2006.286.01:58:01.43#ibcon#end of sib2, iclass 28, count 0 2006.286.01:58:01.43#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:58:01.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:58:01.43#ibcon#[25=USB\r\n] 2006.286.01:58:01.43#ibcon#*before write, iclass 28, count 0 2006.286.01:58:01.43#ibcon#enter sib2, iclass 28, count 0 2006.286.01:58:01.43#ibcon#flushed, iclass 28, count 0 2006.286.01:58:01.43#ibcon#about to write, iclass 28, count 0 2006.286.01:58:01.43#ibcon#wrote, iclass 28, count 0 2006.286.01:58:01.43#ibcon#about to read 3, iclass 28, count 0 2006.286.01:58:01.46#ibcon#read 3, iclass 28, count 0 2006.286.01:58:01.46#ibcon#about to read 4, iclass 28, count 0 2006.286.01:58:01.46#ibcon#read 4, iclass 28, count 0 2006.286.01:58:01.46#ibcon#about to read 5, iclass 28, count 0 2006.286.01:58:01.46#ibcon#read 5, iclass 28, count 0 2006.286.01:58:01.46#ibcon#about to read 6, iclass 28, count 0 2006.286.01:58:01.46#ibcon#read 6, iclass 28, count 0 2006.286.01:58:01.46#ibcon#end of sib2, iclass 28, count 0 2006.286.01:58:01.46#ibcon#*after write, iclass 28, count 0 2006.286.01:58:01.46#ibcon#*before return 0, iclass 28, count 0 2006.286.01:58:01.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:58:01.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.01:58:01.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:58:01.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:58:01.46$vck44/vblo=1,629.99 2006.286.01:58:01.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.01:58:01.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.01:58:01.46#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:01.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:58:01.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:58:01.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:58:01.46#ibcon#enter wrdev, iclass 30, count 0 2006.286.01:58:01.46#ibcon#first serial, iclass 30, count 0 2006.286.01:58:01.46#ibcon#enter sib2, iclass 30, count 0 2006.286.01:58:01.46#ibcon#flushed, iclass 30, count 0 2006.286.01:58:01.46#ibcon#about to write, iclass 30, count 0 2006.286.01:58:01.46#ibcon#wrote, iclass 30, count 0 2006.286.01:58:01.46#ibcon#about to read 3, iclass 30, count 0 2006.286.01:58:01.48#ibcon#read 3, iclass 30, count 0 2006.286.01:58:01.48#ibcon#about to read 4, iclass 30, count 0 2006.286.01:58:01.48#ibcon#read 4, iclass 30, count 0 2006.286.01:58:01.48#ibcon#about to read 5, iclass 30, count 0 2006.286.01:58:01.48#ibcon#read 5, iclass 30, count 0 2006.286.01:58:01.48#ibcon#about to read 6, iclass 30, count 0 2006.286.01:58:01.48#ibcon#read 6, iclass 30, count 0 2006.286.01:58:01.48#ibcon#end of sib2, iclass 30, count 0 2006.286.01:58:01.48#ibcon#*mode == 0, iclass 30, count 0 2006.286.01:58:01.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.01:58:01.48#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.01:58:01.48#ibcon#*before write, iclass 30, count 0 2006.286.01:58:01.48#ibcon#enter sib2, iclass 30, count 0 2006.286.01:58:01.48#ibcon#flushed, iclass 30, count 0 2006.286.01:58:01.48#ibcon#about to write, iclass 30, count 0 2006.286.01:58:01.48#ibcon#wrote, iclass 30, count 0 2006.286.01:58:01.48#ibcon#about to read 3, iclass 30, count 0 2006.286.01:58:01.52#ibcon#read 3, iclass 30, count 0 2006.286.01:58:01.52#ibcon#about to read 4, iclass 30, count 0 2006.286.01:58:01.52#ibcon#read 4, iclass 30, count 0 2006.286.01:58:01.52#ibcon#about to read 5, iclass 30, count 0 2006.286.01:58:01.52#ibcon#read 5, iclass 30, count 0 2006.286.01:58:01.52#ibcon#about to read 6, iclass 30, count 0 2006.286.01:58:01.52#ibcon#read 6, iclass 30, count 0 2006.286.01:58:01.52#ibcon#end of sib2, iclass 30, count 0 2006.286.01:58:01.52#ibcon#*after write, iclass 30, count 0 2006.286.01:58:01.52#ibcon#*before return 0, iclass 30, count 0 2006.286.01:58:01.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:58:01.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.01:58:01.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.01:58:01.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.01:58:01.52$vck44/vb=1,4 2006.286.01:58:01.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.01:58:01.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.01:58:01.52#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:01.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:58:01.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:58:01.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:58:01.52#ibcon#enter wrdev, iclass 32, count 2 2006.286.01:58:01.52#ibcon#first serial, iclass 32, count 2 2006.286.01:58:01.52#ibcon#enter sib2, iclass 32, count 2 2006.286.01:58:01.52#ibcon#flushed, iclass 32, count 2 2006.286.01:58:01.52#ibcon#about to write, iclass 32, count 2 2006.286.01:58:01.52#ibcon#wrote, iclass 32, count 2 2006.286.01:58:01.52#ibcon#about to read 3, iclass 32, count 2 2006.286.01:58:01.54#ibcon#read 3, iclass 32, count 2 2006.286.01:58:01.54#ibcon#about to read 4, iclass 32, count 2 2006.286.01:58:01.54#ibcon#read 4, iclass 32, count 2 2006.286.01:58:01.54#ibcon#about to read 5, iclass 32, count 2 2006.286.01:58:01.54#ibcon#read 5, iclass 32, count 2 2006.286.01:58:01.54#ibcon#about to read 6, iclass 32, count 2 2006.286.01:58:01.54#ibcon#read 6, iclass 32, count 2 2006.286.01:58:01.54#ibcon#end of sib2, iclass 32, count 2 2006.286.01:58:01.54#ibcon#*mode == 0, iclass 32, count 2 2006.286.01:58:01.54#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.01:58:01.54#ibcon#[27=AT01-04\r\n] 2006.286.01:58:01.54#ibcon#*before write, iclass 32, count 2 2006.286.01:58:01.54#ibcon#enter sib2, iclass 32, count 2 2006.286.01:58:01.54#ibcon#flushed, iclass 32, count 2 2006.286.01:58:01.54#ibcon#about to write, iclass 32, count 2 2006.286.01:58:01.54#ibcon#wrote, iclass 32, count 2 2006.286.01:58:01.54#ibcon#about to read 3, iclass 32, count 2 2006.286.01:58:01.57#ibcon#read 3, iclass 32, count 2 2006.286.01:58:01.57#ibcon#about to read 4, iclass 32, count 2 2006.286.01:58:01.57#ibcon#read 4, iclass 32, count 2 2006.286.01:58:01.57#ibcon#about to read 5, iclass 32, count 2 2006.286.01:58:01.57#ibcon#read 5, iclass 32, count 2 2006.286.01:58:01.57#ibcon#about to read 6, iclass 32, count 2 2006.286.01:58:01.57#ibcon#read 6, iclass 32, count 2 2006.286.01:58:01.57#ibcon#end of sib2, iclass 32, count 2 2006.286.01:58:01.57#ibcon#*after write, iclass 32, count 2 2006.286.01:58:01.57#ibcon#*before return 0, iclass 32, count 2 2006.286.01:58:01.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:58:01.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.01:58:01.57#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.01:58:01.57#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:01.57#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:58:01.69#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:58:01.69#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:58:01.69#ibcon#enter wrdev, iclass 32, count 0 2006.286.01:58:01.69#ibcon#first serial, iclass 32, count 0 2006.286.01:58:01.69#ibcon#enter sib2, iclass 32, count 0 2006.286.01:58:01.69#ibcon#flushed, iclass 32, count 0 2006.286.01:58:01.69#ibcon#about to write, iclass 32, count 0 2006.286.01:58:01.69#ibcon#wrote, iclass 32, count 0 2006.286.01:58:01.69#ibcon#about to read 3, iclass 32, count 0 2006.286.01:58:01.71#ibcon#read 3, iclass 32, count 0 2006.286.01:58:01.71#ibcon#about to read 4, iclass 32, count 0 2006.286.01:58:01.71#ibcon#read 4, iclass 32, count 0 2006.286.01:58:01.71#ibcon#about to read 5, iclass 32, count 0 2006.286.01:58:01.71#ibcon#read 5, iclass 32, count 0 2006.286.01:58:01.71#ibcon#about to read 6, iclass 32, count 0 2006.286.01:58:01.71#ibcon#read 6, iclass 32, count 0 2006.286.01:58:01.71#ibcon#end of sib2, iclass 32, count 0 2006.286.01:58:01.71#ibcon#*mode == 0, iclass 32, count 0 2006.286.01:58:01.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.01:58:01.71#ibcon#[27=USB\r\n] 2006.286.01:58:01.71#ibcon#*before write, iclass 32, count 0 2006.286.01:58:01.71#ibcon#enter sib2, iclass 32, count 0 2006.286.01:58:01.71#ibcon#flushed, iclass 32, count 0 2006.286.01:58:01.71#ibcon#about to write, iclass 32, count 0 2006.286.01:58:01.71#ibcon#wrote, iclass 32, count 0 2006.286.01:58:01.71#ibcon#about to read 3, iclass 32, count 0 2006.286.01:58:01.74#ibcon#read 3, iclass 32, count 0 2006.286.01:58:01.74#ibcon#about to read 4, iclass 32, count 0 2006.286.01:58:01.74#ibcon#read 4, iclass 32, count 0 2006.286.01:58:01.74#ibcon#about to read 5, iclass 32, count 0 2006.286.01:58:01.74#ibcon#read 5, iclass 32, count 0 2006.286.01:58:01.74#ibcon#about to read 6, iclass 32, count 0 2006.286.01:58:01.74#ibcon#read 6, iclass 32, count 0 2006.286.01:58:01.74#ibcon#end of sib2, iclass 32, count 0 2006.286.01:58:01.74#ibcon#*after write, iclass 32, count 0 2006.286.01:58:01.74#ibcon#*before return 0, iclass 32, count 0 2006.286.01:58:01.74#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:58:01.74#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.01:58:01.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.01:58:01.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.01:58:01.74$vck44/vblo=2,634.99 2006.286.01:58:01.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.01:58:01.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.01:58:01.74#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:01.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:58:01.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:58:01.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:58:01.74#ibcon#enter wrdev, iclass 34, count 0 2006.286.01:58:01.74#ibcon#first serial, iclass 34, count 0 2006.286.01:58:01.74#ibcon#enter sib2, iclass 34, count 0 2006.286.01:58:01.74#ibcon#flushed, iclass 34, count 0 2006.286.01:58:01.74#ibcon#about to write, iclass 34, count 0 2006.286.01:58:01.74#ibcon#wrote, iclass 34, count 0 2006.286.01:58:01.74#ibcon#about to read 3, iclass 34, count 0 2006.286.01:58:01.76#ibcon#read 3, iclass 34, count 0 2006.286.01:58:01.76#ibcon#about to read 4, iclass 34, count 0 2006.286.01:58:01.76#ibcon#read 4, iclass 34, count 0 2006.286.01:58:01.76#ibcon#about to read 5, iclass 34, count 0 2006.286.01:58:01.76#ibcon#read 5, iclass 34, count 0 2006.286.01:58:01.76#ibcon#about to read 6, iclass 34, count 0 2006.286.01:58:01.76#ibcon#read 6, iclass 34, count 0 2006.286.01:58:01.76#ibcon#end of sib2, iclass 34, count 0 2006.286.01:58:01.76#ibcon#*mode == 0, iclass 34, count 0 2006.286.01:58:01.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.01:58:01.76#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.01:58:01.76#ibcon#*before write, iclass 34, count 0 2006.286.01:58:01.76#ibcon#enter sib2, iclass 34, count 0 2006.286.01:58:01.76#ibcon#flushed, iclass 34, count 0 2006.286.01:58:01.76#ibcon#about to write, iclass 34, count 0 2006.286.01:58:01.76#ibcon#wrote, iclass 34, count 0 2006.286.01:58:01.76#ibcon#about to read 3, iclass 34, count 0 2006.286.01:58:01.80#ibcon#read 3, iclass 34, count 0 2006.286.01:58:01.80#ibcon#about to read 4, iclass 34, count 0 2006.286.01:58:01.80#ibcon#read 4, iclass 34, count 0 2006.286.01:58:01.80#ibcon#about to read 5, iclass 34, count 0 2006.286.01:58:01.80#ibcon#read 5, iclass 34, count 0 2006.286.01:58:01.80#ibcon#about to read 6, iclass 34, count 0 2006.286.01:58:01.80#ibcon#read 6, iclass 34, count 0 2006.286.01:58:01.80#ibcon#end of sib2, iclass 34, count 0 2006.286.01:58:01.80#ibcon#*after write, iclass 34, count 0 2006.286.01:58:01.80#ibcon#*before return 0, iclass 34, count 0 2006.286.01:58:01.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:58:01.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.01:58:01.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.01:58:01.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.01:58:01.80$vck44/vb=2,5 2006.286.01:58:01.80#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.01:58:01.80#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.01:58:01.80#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:01.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:58:01.86#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:58:01.86#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:58:01.86#ibcon#enter wrdev, iclass 36, count 2 2006.286.01:58:01.86#ibcon#first serial, iclass 36, count 2 2006.286.01:58:01.86#ibcon#enter sib2, iclass 36, count 2 2006.286.01:58:01.86#ibcon#flushed, iclass 36, count 2 2006.286.01:58:01.86#ibcon#about to write, iclass 36, count 2 2006.286.01:58:01.86#ibcon#wrote, iclass 36, count 2 2006.286.01:58:01.86#ibcon#about to read 3, iclass 36, count 2 2006.286.01:58:01.88#ibcon#read 3, iclass 36, count 2 2006.286.01:58:01.88#ibcon#about to read 4, iclass 36, count 2 2006.286.01:58:01.88#ibcon#read 4, iclass 36, count 2 2006.286.01:58:01.88#ibcon#about to read 5, iclass 36, count 2 2006.286.01:58:01.88#ibcon#read 5, iclass 36, count 2 2006.286.01:58:01.88#ibcon#about to read 6, iclass 36, count 2 2006.286.01:58:01.88#ibcon#read 6, iclass 36, count 2 2006.286.01:58:01.88#ibcon#end of sib2, iclass 36, count 2 2006.286.01:58:01.88#ibcon#*mode == 0, iclass 36, count 2 2006.286.01:58:01.88#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.01:58:01.88#ibcon#[27=AT02-05\r\n] 2006.286.01:58:01.88#ibcon#*before write, iclass 36, count 2 2006.286.01:58:01.88#ibcon#enter sib2, iclass 36, count 2 2006.286.01:58:01.88#ibcon#flushed, iclass 36, count 2 2006.286.01:58:01.88#ibcon#about to write, iclass 36, count 2 2006.286.01:58:01.88#ibcon#wrote, iclass 36, count 2 2006.286.01:58:01.88#ibcon#about to read 3, iclass 36, count 2 2006.286.01:58:01.91#ibcon#read 3, iclass 36, count 2 2006.286.01:58:01.91#ibcon#about to read 4, iclass 36, count 2 2006.286.01:58:01.91#ibcon#read 4, iclass 36, count 2 2006.286.01:58:01.91#ibcon#about to read 5, iclass 36, count 2 2006.286.01:58:01.91#ibcon#read 5, iclass 36, count 2 2006.286.01:58:01.91#ibcon#about to read 6, iclass 36, count 2 2006.286.01:58:01.91#ibcon#read 6, iclass 36, count 2 2006.286.01:58:01.91#ibcon#end of sib2, iclass 36, count 2 2006.286.01:58:01.91#ibcon#*after write, iclass 36, count 2 2006.286.01:58:01.91#ibcon#*before return 0, iclass 36, count 2 2006.286.01:58:01.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:58:01.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.01:58:01.91#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.01:58:01.91#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:01.91#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:58:02.03#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:58:02.03#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:58:02.03#ibcon#enter wrdev, iclass 36, count 0 2006.286.01:58:02.03#ibcon#first serial, iclass 36, count 0 2006.286.01:58:02.03#ibcon#enter sib2, iclass 36, count 0 2006.286.01:58:02.03#ibcon#flushed, iclass 36, count 0 2006.286.01:58:02.03#ibcon#about to write, iclass 36, count 0 2006.286.01:58:02.03#ibcon#wrote, iclass 36, count 0 2006.286.01:58:02.03#ibcon#about to read 3, iclass 36, count 0 2006.286.01:58:02.05#ibcon#read 3, iclass 36, count 0 2006.286.01:58:02.05#ibcon#about to read 4, iclass 36, count 0 2006.286.01:58:02.05#ibcon#read 4, iclass 36, count 0 2006.286.01:58:02.05#ibcon#about to read 5, iclass 36, count 0 2006.286.01:58:02.05#ibcon#read 5, iclass 36, count 0 2006.286.01:58:02.05#ibcon#about to read 6, iclass 36, count 0 2006.286.01:58:02.05#ibcon#read 6, iclass 36, count 0 2006.286.01:58:02.05#ibcon#end of sib2, iclass 36, count 0 2006.286.01:58:02.05#ibcon#*mode == 0, iclass 36, count 0 2006.286.01:58:02.05#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.01:58:02.05#ibcon#[27=USB\r\n] 2006.286.01:58:02.05#ibcon#*before write, iclass 36, count 0 2006.286.01:58:02.05#ibcon#enter sib2, iclass 36, count 0 2006.286.01:58:02.05#ibcon#flushed, iclass 36, count 0 2006.286.01:58:02.05#ibcon#about to write, iclass 36, count 0 2006.286.01:58:02.05#ibcon#wrote, iclass 36, count 0 2006.286.01:58:02.05#ibcon#about to read 3, iclass 36, count 0 2006.286.01:58:02.08#ibcon#read 3, iclass 36, count 0 2006.286.01:58:02.08#ibcon#about to read 4, iclass 36, count 0 2006.286.01:58:02.08#ibcon#read 4, iclass 36, count 0 2006.286.01:58:02.08#ibcon#about to read 5, iclass 36, count 0 2006.286.01:58:02.08#ibcon#read 5, iclass 36, count 0 2006.286.01:58:02.08#ibcon#about to read 6, iclass 36, count 0 2006.286.01:58:02.08#ibcon#read 6, iclass 36, count 0 2006.286.01:58:02.08#ibcon#end of sib2, iclass 36, count 0 2006.286.01:58:02.08#ibcon#*after write, iclass 36, count 0 2006.286.01:58:02.08#ibcon#*before return 0, iclass 36, count 0 2006.286.01:58:02.08#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:58:02.08#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.01:58:02.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.01:58:02.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.01:58:02.08$vck44/vblo=3,649.99 2006.286.01:58:02.08#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.01:58:02.08#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.01:58:02.08#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:02.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:58:02.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:58:02.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:58:02.08#ibcon#enter wrdev, iclass 38, count 0 2006.286.01:58:02.08#ibcon#first serial, iclass 38, count 0 2006.286.01:58:02.08#ibcon#enter sib2, iclass 38, count 0 2006.286.01:58:02.08#ibcon#flushed, iclass 38, count 0 2006.286.01:58:02.08#ibcon#about to write, iclass 38, count 0 2006.286.01:58:02.08#ibcon#wrote, iclass 38, count 0 2006.286.01:58:02.08#ibcon#about to read 3, iclass 38, count 0 2006.286.01:58:02.10#ibcon#read 3, iclass 38, count 0 2006.286.01:58:02.10#ibcon#about to read 4, iclass 38, count 0 2006.286.01:58:02.10#ibcon#read 4, iclass 38, count 0 2006.286.01:58:02.10#ibcon#about to read 5, iclass 38, count 0 2006.286.01:58:02.10#ibcon#read 5, iclass 38, count 0 2006.286.01:58:02.10#ibcon#about to read 6, iclass 38, count 0 2006.286.01:58:02.10#ibcon#read 6, iclass 38, count 0 2006.286.01:58:02.10#ibcon#end of sib2, iclass 38, count 0 2006.286.01:58:02.10#ibcon#*mode == 0, iclass 38, count 0 2006.286.01:58:02.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.01:58:02.10#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.01:58:02.10#ibcon#*before write, iclass 38, count 0 2006.286.01:58:02.10#ibcon#enter sib2, iclass 38, count 0 2006.286.01:58:02.10#ibcon#flushed, iclass 38, count 0 2006.286.01:58:02.10#ibcon#about to write, iclass 38, count 0 2006.286.01:58:02.10#ibcon#wrote, iclass 38, count 0 2006.286.01:58:02.10#ibcon#about to read 3, iclass 38, count 0 2006.286.01:58:02.14#ibcon#read 3, iclass 38, count 0 2006.286.01:58:02.14#ibcon#about to read 4, iclass 38, count 0 2006.286.01:58:02.14#ibcon#read 4, iclass 38, count 0 2006.286.01:58:02.14#ibcon#about to read 5, iclass 38, count 0 2006.286.01:58:02.14#ibcon#read 5, iclass 38, count 0 2006.286.01:58:02.14#ibcon#about to read 6, iclass 38, count 0 2006.286.01:58:02.14#ibcon#read 6, iclass 38, count 0 2006.286.01:58:02.14#ibcon#end of sib2, iclass 38, count 0 2006.286.01:58:02.14#ibcon#*after write, iclass 38, count 0 2006.286.01:58:02.14#ibcon#*before return 0, iclass 38, count 0 2006.286.01:58:02.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:58:02.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.01:58:02.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.01:58:02.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.01:58:02.14$vck44/vb=3,4 2006.286.01:58:02.14#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.01:58:02.14#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.01:58:02.14#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:02.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:58:02.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:58:02.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:58:02.20#ibcon#enter wrdev, iclass 40, count 2 2006.286.01:58:02.20#ibcon#first serial, iclass 40, count 2 2006.286.01:58:02.20#ibcon#enter sib2, iclass 40, count 2 2006.286.01:58:02.20#ibcon#flushed, iclass 40, count 2 2006.286.01:58:02.20#ibcon#about to write, iclass 40, count 2 2006.286.01:58:02.20#ibcon#wrote, iclass 40, count 2 2006.286.01:58:02.20#ibcon#about to read 3, iclass 40, count 2 2006.286.01:58:02.22#ibcon#read 3, iclass 40, count 2 2006.286.01:58:02.22#ibcon#about to read 4, iclass 40, count 2 2006.286.01:58:02.22#ibcon#read 4, iclass 40, count 2 2006.286.01:58:02.22#ibcon#about to read 5, iclass 40, count 2 2006.286.01:58:02.22#ibcon#read 5, iclass 40, count 2 2006.286.01:58:02.22#ibcon#about to read 6, iclass 40, count 2 2006.286.01:58:02.22#ibcon#read 6, iclass 40, count 2 2006.286.01:58:02.22#ibcon#end of sib2, iclass 40, count 2 2006.286.01:58:02.22#ibcon#*mode == 0, iclass 40, count 2 2006.286.01:58:02.22#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.01:58:02.22#ibcon#[27=AT03-04\r\n] 2006.286.01:58:02.22#ibcon#*before write, iclass 40, count 2 2006.286.01:58:02.22#ibcon#enter sib2, iclass 40, count 2 2006.286.01:58:02.22#ibcon#flushed, iclass 40, count 2 2006.286.01:58:02.22#ibcon#about to write, iclass 40, count 2 2006.286.01:58:02.22#ibcon#wrote, iclass 40, count 2 2006.286.01:58:02.22#ibcon#about to read 3, iclass 40, count 2 2006.286.01:58:02.25#ibcon#read 3, iclass 40, count 2 2006.286.01:58:02.25#ibcon#about to read 4, iclass 40, count 2 2006.286.01:58:02.25#ibcon#read 4, iclass 40, count 2 2006.286.01:58:02.25#ibcon#about to read 5, iclass 40, count 2 2006.286.01:58:02.25#ibcon#read 5, iclass 40, count 2 2006.286.01:58:02.25#ibcon#about to read 6, iclass 40, count 2 2006.286.01:58:02.25#ibcon#read 6, iclass 40, count 2 2006.286.01:58:02.25#ibcon#end of sib2, iclass 40, count 2 2006.286.01:58:02.25#ibcon#*after write, iclass 40, count 2 2006.286.01:58:02.25#ibcon#*before return 0, iclass 40, count 2 2006.286.01:58:02.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:58:02.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.01:58:02.25#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.01:58:02.25#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:02.25#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:58:02.37#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:58:02.37#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:58:02.37#ibcon#enter wrdev, iclass 40, count 0 2006.286.01:58:02.37#ibcon#first serial, iclass 40, count 0 2006.286.01:58:02.37#ibcon#enter sib2, iclass 40, count 0 2006.286.01:58:02.37#ibcon#flushed, iclass 40, count 0 2006.286.01:58:02.37#ibcon#about to write, iclass 40, count 0 2006.286.01:58:02.37#ibcon#wrote, iclass 40, count 0 2006.286.01:58:02.37#ibcon#about to read 3, iclass 40, count 0 2006.286.01:58:02.39#ibcon#read 3, iclass 40, count 0 2006.286.01:58:02.39#ibcon#about to read 4, iclass 40, count 0 2006.286.01:58:02.39#ibcon#read 4, iclass 40, count 0 2006.286.01:58:02.39#ibcon#about to read 5, iclass 40, count 0 2006.286.01:58:02.39#ibcon#read 5, iclass 40, count 0 2006.286.01:58:02.39#ibcon#about to read 6, iclass 40, count 0 2006.286.01:58:02.39#ibcon#read 6, iclass 40, count 0 2006.286.01:58:02.39#ibcon#end of sib2, iclass 40, count 0 2006.286.01:58:02.39#ibcon#*mode == 0, iclass 40, count 0 2006.286.01:58:02.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.01:58:02.39#ibcon#[27=USB\r\n] 2006.286.01:58:02.39#ibcon#*before write, iclass 40, count 0 2006.286.01:58:02.39#ibcon#enter sib2, iclass 40, count 0 2006.286.01:58:02.39#ibcon#flushed, iclass 40, count 0 2006.286.01:58:02.39#ibcon#about to write, iclass 40, count 0 2006.286.01:58:02.39#ibcon#wrote, iclass 40, count 0 2006.286.01:58:02.39#ibcon#about to read 3, iclass 40, count 0 2006.286.01:58:02.42#ibcon#read 3, iclass 40, count 0 2006.286.01:58:02.42#ibcon#about to read 4, iclass 40, count 0 2006.286.01:58:02.42#ibcon#read 4, iclass 40, count 0 2006.286.01:58:02.42#ibcon#about to read 5, iclass 40, count 0 2006.286.01:58:02.42#ibcon#read 5, iclass 40, count 0 2006.286.01:58:02.42#ibcon#about to read 6, iclass 40, count 0 2006.286.01:58:02.42#ibcon#read 6, iclass 40, count 0 2006.286.01:58:02.42#ibcon#end of sib2, iclass 40, count 0 2006.286.01:58:02.42#ibcon#*after write, iclass 40, count 0 2006.286.01:58:02.42#ibcon#*before return 0, iclass 40, count 0 2006.286.01:58:02.42#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:58:02.42#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.01:58:02.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.01:58:02.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.01:58:02.42$vck44/vblo=4,679.99 2006.286.01:58:02.42#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.01:58:02.42#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.01:58:02.42#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:02.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:58:02.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:58:02.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:58:02.42#ibcon#enter wrdev, iclass 4, count 0 2006.286.01:58:02.42#ibcon#first serial, iclass 4, count 0 2006.286.01:58:02.42#ibcon#enter sib2, iclass 4, count 0 2006.286.01:58:02.42#ibcon#flushed, iclass 4, count 0 2006.286.01:58:02.42#ibcon#about to write, iclass 4, count 0 2006.286.01:58:02.42#ibcon#wrote, iclass 4, count 0 2006.286.01:58:02.42#ibcon#about to read 3, iclass 4, count 0 2006.286.01:58:02.44#ibcon#read 3, iclass 4, count 0 2006.286.01:58:02.44#ibcon#about to read 4, iclass 4, count 0 2006.286.01:58:02.44#ibcon#read 4, iclass 4, count 0 2006.286.01:58:02.44#ibcon#about to read 5, iclass 4, count 0 2006.286.01:58:02.44#ibcon#read 5, iclass 4, count 0 2006.286.01:58:02.44#ibcon#about to read 6, iclass 4, count 0 2006.286.01:58:02.44#ibcon#read 6, iclass 4, count 0 2006.286.01:58:02.44#ibcon#end of sib2, iclass 4, count 0 2006.286.01:58:02.44#ibcon#*mode == 0, iclass 4, count 0 2006.286.01:58:02.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.01:58:02.44#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.01:58:02.44#ibcon#*before write, iclass 4, count 0 2006.286.01:58:02.44#ibcon#enter sib2, iclass 4, count 0 2006.286.01:58:02.44#ibcon#flushed, iclass 4, count 0 2006.286.01:58:02.44#ibcon#about to write, iclass 4, count 0 2006.286.01:58:02.44#ibcon#wrote, iclass 4, count 0 2006.286.01:58:02.44#ibcon#about to read 3, iclass 4, count 0 2006.286.01:58:02.48#ibcon#read 3, iclass 4, count 0 2006.286.01:58:02.48#ibcon#about to read 4, iclass 4, count 0 2006.286.01:58:02.48#ibcon#read 4, iclass 4, count 0 2006.286.01:58:02.48#ibcon#about to read 5, iclass 4, count 0 2006.286.01:58:02.48#ibcon#read 5, iclass 4, count 0 2006.286.01:58:02.48#ibcon#about to read 6, iclass 4, count 0 2006.286.01:58:02.48#ibcon#read 6, iclass 4, count 0 2006.286.01:58:02.48#ibcon#end of sib2, iclass 4, count 0 2006.286.01:58:02.48#ibcon#*after write, iclass 4, count 0 2006.286.01:58:02.48#ibcon#*before return 0, iclass 4, count 0 2006.286.01:58:02.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:58:02.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.01:58:02.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.01:58:02.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.01:58:02.48$vck44/vb=4,5 2006.286.01:58:02.48#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.01:58:02.48#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.01:58:02.48#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:02.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:58:02.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:58:02.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:58:02.54#ibcon#enter wrdev, iclass 6, count 2 2006.286.01:58:02.54#ibcon#first serial, iclass 6, count 2 2006.286.01:58:02.54#ibcon#enter sib2, iclass 6, count 2 2006.286.01:58:02.54#ibcon#flushed, iclass 6, count 2 2006.286.01:58:02.54#ibcon#about to write, iclass 6, count 2 2006.286.01:58:02.54#ibcon#wrote, iclass 6, count 2 2006.286.01:58:02.54#ibcon#about to read 3, iclass 6, count 2 2006.286.01:58:02.56#ibcon#read 3, iclass 6, count 2 2006.286.01:58:02.56#ibcon#about to read 4, iclass 6, count 2 2006.286.01:58:02.56#ibcon#read 4, iclass 6, count 2 2006.286.01:58:02.56#ibcon#about to read 5, iclass 6, count 2 2006.286.01:58:02.56#ibcon#read 5, iclass 6, count 2 2006.286.01:58:02.56#ibcon#about to read 6, iclass 6, count 2 2006.286.01:58:02.56#ibcon#read 6, iclass 6, count 2 2006.286.01:58:02.56#ibcon#end of sib2, iclass 6, count 2 2006.286.01:58:02.56#ibcon#*mode == 0, iclass 6, count 2 2006.286.01:58:02.56#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.01:58:02.56#ibcon#[27=AT04-05\r\n] 2006.286.01:58:02.56#ibcon#*before write, iclass 6, count 2 2006.286.01:58:02.56#ibcon#enter sib2, iclass 6, count 2 2006.286.01:58:02.56#ibcon#flushed, iclass 6, count 2 2006.286.01:58:02.56#ibcon#about to write, iclass 6, count 2 2006.286.01:58:02.56#ibcon#wrote, iclass 6, count 2 2006.286.01:58:02.56#ibcon#about to read 3, iclass 6, count 2 2006.286.01:58:02.59#ibcon#read 3, iclass 6, count 2 2006.286.01:58:02.59#ibcon#about to read 4, iclass 6, count 2 2006.286.01:58:02.59#ibcon#read 4, iclass 6, count 2 2006.286.01:58:02.59#ibcon#about to read 5, iclass 6, count 2 2006.286.01:58:02.59#ibcon#read 5, iclass 6, count 2 2006.286.01:58:02.59#ibcon#about to read 6, iclass 6, count 2 2006.286.01:58:02.59#ibcon#read 6, iclass 6, count 2 2006.286.01:58:02.59#ibcon#end of sib2, iclass 6, count 2 2006.286.01:58:02.59#ibcon#*after write, iclass 6, count 2 2006.286.01:58:02.59#ibcon#*before return 0, iclass 6, count 2 2006.286.01:58:02.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:58:02.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.01:58:02.59#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.01:58:02.59#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:02.59#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:58:02.71#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:58:02.71#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:58:02.71#ibcon#enter wrdev, iclass 6, count 0 2006.286.01:58:02.71#ibcon#first serial, iclass 6, count 0 2006.286.01:58:02.71#ibcon#enter sib2, iclass 6, count 0 2006.286.01:58:02.71#ibcon#flushed, iclass 6, count 0 2006.286.01:58:02.71#ibcon#about to write, iclass 6, count 0 2006.286.01:58:02.71#ibcon#wrote, iclass 6, count 0 2006.286.01:58:02.71#ibcon#about to read 3, iclass 6, count 0 2006.286.01:58:02.73#ibcon#read 3, iclass 6, count 0 2006.286.01:58:02.73#ibcon#about to read 4, iclass 6, count 0 2006.286.01:58:02.73#ibcon#read 4, iclass 6, count 0 2006.286.01:58:02.73#ibcon#about to read 5, iclass 6, count 0 2006.286.01:58:02.73#ibcon#read 5, iclass 6, count 0 2006.286.01:58:02.73#ibcon#about to read 6, iclass 6, count 0 2006.286.01:58:02.73#ibcon#read 6, iclass 6, count 0 2006.286.01:58:02.73#ibcon#end of sib2, iclass 6, count 0 2006.286.01:58:02.73#ibcon#*mode == 0, iclass 6, count 0 2006.286.01:58:02.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.01:58:02.73#ibcon#[27=USB\r\n] 2006.286.01:58:02.73#ibcon#*before write, iclass 6, count 0 2006.286.01:58:02.73#ibcon#enter sib2, iclass 6, count 0 2006.286.01:58:02.73#ibcon#flushed, iclass 6, count 0 2006.286.01:58:02.73#ibcon#about to write, iclass 6, count 0 2006.286.01:58:02.73#ibcon#wrote, iclass 6, count 0 2006.286.01:58:02.73#ibcon#about to read 3, iclass 6, count 0 2006.286.01:58:02.76#ibcon#read 3, iclass 6, count 0 2006.286.01:58:02.76#ibcon#about to read 4, iclass 6, count 0 2006.286.01:58:02.76#ibcon#read 4, iclass 6, count 0 2006.286.01:58:02.76#ibcon#about to read 5, iclass 6, count 0 2006.286.01:58:02.76#ibcon#read 5, iclass 6, count 0 2006.286.01:58:02.76#ibcon#about to read 6, iclass 6, count 0 2006.286.01:58:02.76#ibcon#read 6, iclass 6, count 0 2006.286.01:58:02.76#ibcon#end of sib2, iclass 6, count 0 2006.286.01:58:02.76#ibcon#*after write, iclass 6, count 0 2006.286.01:58:02.76#ibcon#*before return 0, iclass 6, count 0 2006.286.01:58:02.76#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:58:02.76#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.01:58:02.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.01:58:02.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.01:58:02.76$vck44/vblo=5,709.99 2006.286.01:58:02.76#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.01:58:02.76#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.01:58:02.76#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:02.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:58:02.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:58:02.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:58:02.76#ibcon#enter wrdev, iclass 10, count 0 2006.286.01:58:02.76#ibcon#first serial, iclass 10, count 0 2006.286.01:58:02.76#ibcon#enter sib2, iclass 10, count 0 2006.286.01:58:02.76#ibcon#flushed, iclass 10, count 0 2006.286.01:58:02.76#ibcon#about to write, iclass 10, count 0 2006.286.01:58:02.76#ibcon#wrote, iclass 10, count 0 2006.286.01:58:02.76#ibcon#about to read 3, iclass 10, count 0 2006.286.01:58:02.78#ibcon#read 3, iclass 10, count 0 2006.286.01:58:02.78#ibcon#about to read 4, iclass 10, count 0 2006.286.01:58:02.78#ibcon#read 4, iclass 10, count 0 2006.286.01:58:02.78#ibcon#about to read 5, iclass 10, count 0 2006.286.01:58:02.78#ibcon#read 5, iclass 10, count 0 2006.286.01:58:02.78#ibcon#about to read 6, iclass 10, count 0 2006.286.01:58:02.78#ibcon#read 6, iclass 10, count 0 2006.286.01:58:02.78#ibcon#end of sib2, iclass 10, count 0 2006.286.01:58:02.78#ibcon#*mode == 0, iclass 10, count 0 2006.286.01:58:02.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.01:58:02.78#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.01:58:02.78#ibcon#*before write, iclass 10, count 0 2006.286.01:58:02.78#ibcon#enter sib2, iclass 10, count 0 2006.286.01:58:02.78#ibcon#flushed, iclass 10, count 0 2006.286.01:58:02.78#ibcon#about to write, iclass 10, count 0 2006.286.01:58:02.78#ibcon#wrote, iclass 10, count 0 2006.286.01:58:02.78#ibcon#about to read 3, iclass 10, count 0 2006.286.01:58:02.82#ibcon#read 3, iclass 10, count 0 2006.286.01:58:02.82#ibcon#about to read 4, iclass 10, count 0 2006.286.01:58:02.82#ibcon#read 4, iclass 10, count 0 2006.286.01:58:02.82#ibcon#about to read 5, iclass 10, count 0 2006.286.01:58:02.82#ibcon#read 5, iclass 10, count 0 2006.286.01:58:02.82#ibcon#about to read 6, iclass 10, count 0 2006.286.01:58:02.82#ibcon#read 6, iclass 10, count 0 2006.286.01:58:02.82#ibcon#end of sib2, iclass 10, count 0 2006.286.01:58:02.82#ibcon#*after write, iclass 10, count 0 2006.286.01:58:02.82#ibcon#*before return 0, iclass 10, count 0 2006.286.01:58:02.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:58:02.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.01:58:02.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.01:58:02.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.01:58:02.82$vck44/vb=5,4 2006.286.01:58:02.82#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.01:58:02.82#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.01:58:02.82#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:02.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:58:02.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:58:02.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:58:02.88#ibcon#enter wrdev, iclass 12, count 2 2006.286.01:58:02.88#ibcon#first serial, iclass 12, count 2 2006.286.01:58:02.88#ibcon#enter sib2, iclass 12, count 2 2006.286.01:58:02.88#ibcon#flushed, iclass 12, count 2 2006.286.01:58:02.88#ibcon#about to write, iclass 12, count 2 2006.286.01:58:02.88#ibcon#wrote, iclass 12, count 2 2006.286.01:58:02.88#ibcon#about to read 3, iclass 12, count 2 2006.286.01:58:02.90#ibcon#read 3, iclass 12, count 2 2006.286.01:58:02.90#ibcon#about to read 4, iclass 12, count 2 2006.286.01:58:02.90#ibcon#read 4, iclass 12, count 2 2006.286.01:58:02.90#ibcon#about to read 5, iclass 12, count 2 2006.286.01:58:02.90#ibcon#read 5, iclass 12, count 2 2006.286.01:58:02.90#ibcon#about to read 6, iclass 12, count 2 2006.286.01:58:02.90#ibcon#read 6, iclass 12, count 2 2006.286.01:58:02.90#ibcon#end of sib2, iclass 12, count 2 2006.286.01:58:02.90#ibcon#*mode == 0, iclass 12, count 2 2006.286.01:58:02.90#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.01:58:02.90#ibcon#[27=AT05-04\r\n] 2006.286.01:58:02.90#ibcon#*before write, iclass 12, count 2 2006.286.01:58:02.90#ibcon#enter sib2, iclass 12, count 2 2006.286.01:58:02.90#ibcon#flushed, iclass 12, count 2 2006.286.01:58:02.90#ibcon#about to write, iclass 12, count 2 2006.286.01:58:02.90#ibcon#wrote, iclass 12, count 2 2006.286.01:58:02.90#ibcon#about to read 3, iclass 12, count 2 2006.286.01:58:02.93#ibcon#read 3, iclass 12, count 2 2006.286.01:58:02.93#ibcon#about to read 4, iclass 12, count 2 2006.286.01:58:02.93#ibcon#read 4, iclass 12, count 2 2006.286.01:58:02.93#ibcon#about to read 5, iclass 12, count 2 2006.286.01:58:02.93#ibcon#read 5, iclass 12, count 2 2006.286.01:58:02.93#ibcon#about to read 6, iclass 12, count 2 2006.286.01:58:02.93#ibcon#read 6, iclass 12, count 2 2006.286.01:58:02.93#ibcon#end of sib2, iclass 12, count 2 2006.286.01:58:02.93#ibcon#*after write, iclass 12, count 2 2006.286.01:58:02.93#ibcon#*before return 0, iclass 12, count 2 2006.286.01:58:02.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:58:02.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.01:58:02.93#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.01:58:02.93#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:02.93#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:58:03.05#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:58:03.05#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:58:03.05#ibcon#enter wrdev, iclass 12, count 0 2006.286.01:58:03.05#ibcon#first serial, iclass 12, count 0 2006.286.01:58:03.05#ibcon#enter sib2, iclass 12, count 0 2006.286.01:58:03.05#ibcon#flushed, iclass 12, count 0 2006.286.01:58:03.05#ibcon#about to write, iclass 12, count 0 2006.286.01:58:03.05#ibcon#wrote, iclass 12, count 0 2006.286.01:58:03.05#ibcon#about to read 3, iclass 12, count 0 2006.286.01:58:03.07#ibcon#read 3, iclass 12, count 0 2006.286.01:58:03.07#ibcon#about to read 4, iclass 12, count 0 2006.286.01:58:03.07#ibcon#read 4, iclass 12, count 0 2006.286.01:58:03.07#ibcon#about to read 5, iclass 12, count 0 2006.286.01:58:03.07#ibcon#read 5, iclass 12, count 0 2006.286.01:58:03.07#ibcon#about to read 6, iclass 12, count 0 2006.286.01:58:03.07#ibcon#read 6, iclass 12, count 0 2006.286.01:58:03.07#ibcon#end of sib2, iclass 12, count 0 2006.286.01:58:03.07#ibcon#*mode == 0, iclass 12, count 0 2006.286.01:58:03.07#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.01:58:03.07#ibcon#[27=USB\r\n] 2006.286.01:58:03.07#ibcon#*before write, iclass 12, count 0 2006.286.01:58:03.07#ibcon#enter sib2, iclass 12, count 0 2006.286.01:58:03.07#ibcon#flushed, iclass 12, count 0 2006.286.01:58:03.07#ibcon#about to write, iclass 12, count 0 2006.286.01:58:03.07#ibcon#wrote, iclass 12, count 0 2006.286.01:58:03.07#ibcon#about to read 3, iclass 12, count 0 2006.286.01:58:03.10#ibcon#read 3, iclass 12, count 0 2006.286.01:58:03.10#ibcon#about to read 4, iclass 12, count 0 2006.286.01:58:03.10#ibcon#read 4, iclass 12, count 0 2006.286.01:58:03.10#ibcon#about to read 5, iclass 12, count 0 2006.286.01:58:03.10#ibcon#read 5, iclass 12, count 0 2006.286.01:58:03.10#ibcon#about to read 6, iclass 12, count 0 2006.286.01:58:03.10#ibcon#read 6, iclass 12, count 0 2006.286.01:58:03.10#ibcon#end of sib2, iclass 12, count 0 2006.286.01:58:03.10#ibcon#*after write, iclass 12, count 0 2006.286.01:58:03.10#ibcon#*before return 0, iclass 12, count 0 2006.286.01:58:03.10#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:58:03.10#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.01:58:03.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.01:58:03.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.01:58:03.10$vck44/vblo=6,719.99 2006.286.01:58:03.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.01:58:03.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.01:58:03.10#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:03.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:58:03.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:58:03.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:58:03.10#ibcon#enter wrdev, iclass 14, count 0 2006.286.01:58:03.10#ibcon#first serial, iclass 14, count 0 2006.286.01:58:03.10#ibcon#enter sib2, iclass 14, count 0 2006.286.01:58:03.10#ibcon#flushed, iclass 14, count 0 2006.286.01:58:03.10#ibcon#about to write, iclass 14, count 0 2006.286.01:58:03.10#ibcon#wrote, iclass 14, count 0 2006.286.01:58:03.10#ibcon#about to read 3, iclass 14, count 0 2006.286.01:58:03.12#ibcon#read 3, iclass 14, count 0 2006.286.01:58:03.12#ibcon#about to read 4, iclass 14, count 0 2006.286.01:58:03.12#ibcon#read 4, iclass 14, count 0 2006.286.01:58:03.12#ibcon#about to read 5, iclass 14, count 0 2006.286.01:58:03.12#ibcon#read 5, iclass 14, count 0 2006.286.01:58:03.12#ibcon#about to read 6, iclass 14, count 0 2006.286.01:58:03.12#ibcon#read 6, iclass 14, count 0 2006.286.01:58:03.12#ibcon#end of sib2, iclass 14, count 0 2006.286.01:58:03.12#ibcon#*mode == 0, iclass 14, count 0 2006.286.01:58:03.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.01:58:03.12#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.01:58:03.12#ibcon#*before write, iclass 14, count 0 2006.286.01:58:03.12#ibcon#enter sib2, iclass 14, count 0 2006.286.01:58:03.12#ibcon#flushed, iclass 14, count 0 2006.286.01:58:03.12#ibcon#about to write, iclass 14, count 0 2006.286.01:58:03.12#ibcon#wrote, iclass 14, count 0 2006.286.01:58:03.12#ibcon#about to read 3, iclass 14, count 0 2006.286.01:58:03.16#ibcon#read 3, iclass 14, count 0 2006.286.01:58:03.16#ibcon#about to read 4, iclass 14, count 0 2006.286.01:58:03.16#ibcon#read 4, iclass 14, count 0 2006.286.01:58:03.16#ibcon#about to read 5, iclass 14, count 0 2006.286.01:58:03.16#ibcon#read 5, iclass 14, count 0 2006.286.01:58:03.16#ibcon#about to read 6, iclass 14, count 0 2006.286.01:58:03.16#ibcon#read 6, iclass 14, count 0 2006.286.01:58:03.16#ibcon#end of sib2, iclass 14, count 0 2006.286.01:58:03.16#ibcon#*after write, iclass 14, count 0 2006.286.01:58:03.16#ibcon#*before return 0, iclass 14, count 0 2006.286.01:58:03.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:58:03.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.01:58:03.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.01:58:03.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.01:58:03.16$vck44/vb=6,3 2006.286.01:58:03.16#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.01:58:03.16#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.01:58:03.16#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:03.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:58:03.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:58:03.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:58:03.22#ibcon#enter wrdev, iclass 16, count 2 2006.286.01:58:03.22#ibcon#first serial, iclass 16, count 2 2006.286.01:58:03.22#ibcon#enter sib2, iclass 16, count 2 2006.286.01:58:03.22#ibcon#flushed, iclass 16, count 2 2006.286.01:58:03.22#ibcon#about to write, iclass 16, count 2 2006.286.01:58:03.22#ibcon#wrote, iclass 16, count 2 2006.286.01:58:03.22#ibcon#about to read 3, iclass 16, count 2 2006.286.01:58:03.24#ibcon#read 3, iclass 16, count 2 2006.286.01:58:03.24#ibcon#about to read 4, iclass 16, count 2 2006.286.01:58:03.24#ibcon#read 4, iclass 16, count 2 2006.286.01:58:03.24#ibcon#about to read 5, iclass 16, count 2 2006.286.01:58:03.24#ibcon#read 5, iclass 16, count 2 2006.286.01:58:03.24#ibcon#about to read 6, iclass 16, count 2 2006.286.01:58:03.24#ibcon#read 6, iclass 16, count 2 2006.286.01:58:03.24#ibcon#end of sib2, iclass 16, count 2 2006.286.01:58:03.24#ibcon#*mode == 0, iclass 16, count 2 2006.286.01:58:03.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.01:58:03.24#ibcon#[27=AT06-03\r\n] 2006.286.01:58:03.24#ibcon#*before write, iclass 16, count 2 2006.286.01:58:03.24#ibcon#enter sib2, iclass 16, count 2 2006.286.01:58:03.24#ibcon#flushed, iclass 16, count 2 2006.286.01:58:03.24#ibcon#about to write, iclass 16, count 2 2006.286.01:58:03.24#ibcon#wrote, iclass 16, count 2 2006.286.01:58:03.24#ibcon#about to read 3, iclass 16, count 2 2006.286.01:58:03.27#ibcon#read 3, iclass 16, count 2 2006.286.01:58:03.27#ibcon#about to read 4, iclass 16, count 2 2006.286.01:58:03.27#ibcon#read 4, iclass 16, count 2 2006.286.01:58:03.27#ibcon#about to read 5, iclass 16, count 2 2006.286.01:58:03.27#ibcon#read 5, iclass 16, count 2 2006.286.01:58:03.27#ibcon#about to read 6, iclass 16, count 2 2006.286.01:58:03.27#ibcon#read 6, iclass 16, count 2 2006.286.01:58:03.27#ibcon#end of sib2, iclass 16, count 2 2006.286.01:58:03.27#ibcon#*after write, iclass 16, count 2 2006.286.01:58:03.27#ibcon#*before return 0, iclass 16, count 2 2006.286.01:58:03.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:58:03.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.01:58:03.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.01:58:03.27#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:03.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:58:03.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:58:03.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:58:03.39#ibcon#enter wrdev, iclass 16, count 0 2006.286.01:58:03.39#ibcon#first serial, iclass 16, count 0 2006.286.01:58:03.39#ibcon#enter sib2, iclass 16, count 0 2006.286.01:58:03.39#ibcon#flushed, iclass 16, count 0 2006.286.01:58:03.39#ibcon#about to write, iclass 16, count 0 2006.286.01:58:03.39#ibcon#wrote, iclass 16, count 0 2006.286.01:58:03.39#ibcon#about to read 3, iclass 16, count 0 2006.286.01:58:03.41#ibcon#read 3, iclass 16, count 0 2006.286.01:58:03.41#ibcon#about to read 4, iclass 16, count 0 2006.286.01:58:03.41#ibcon#read 4, iclass 16, count 0 2006.286.01:58:03.41#ibcon#about to read 5, iclass 16, count 0 2006.286.01:58:03.41#ibcon#read 5, iclass 16, count 0 2006.286.01:58:03.41#ibcon#about to read 6, iclass 16, count 0 2006.286.01:58:03.41#ibcon#read 6, iclass 16, count 0 2006.286.01:58:03.41#ibcon#end of sib2, iclass 16, count 0 2006.286.01:58:03.41#ibcon#*mode == 0, iclass 16, count 0 2006.286.01:58:03.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.01:58:03.41#ibcon#[27=USB\r\n] 2006.286.01:58:03.41#ibcon#*before write, iclass 16, count 0 2006.286.01:58:03.41#ibcon#enter sib2, iclass 16, count 0 2006.286.01:58:03.41#ibcon#flushed, iclass 16, count 0 2006.286.01:58:03.41#ibcon#about to write, iclass 16, count 0 2006.286.01:58:03.41#ibcon#wrote, iclass 16, count 0 2006.286.01:58:03.41#ibcon#about to read 3, iclass 16, count 0 2006.286.01:58:03.44#ibcon#read 3, iclass 16, count 0 2006.286.01:58:03.44#ibcon#about to read 4, iclass 16, count 0 2006.286.01:58:03.44#ibcon#read 4, iclass 16, count 0 2006.286.01:58:03.44#ibcon#about to read 5, iclass 16, count 0 2006.286.01:58:03.44#ibcon#read 5, iclass 16, count 0 2006.286.01:58:03.44#ibcon#about to read 6, iclass 16, count 0 2006.286.01:58:03.44#ibcon#read 6, iclass 16, count 0 2006.286.01:58:03.44#ibcon#end of sib2, iclass 16, count 0 2006.286.01:58:03.44#ibcon#*after write, iclass 16, count 0 2006.286.01:58:03.44#ibcon#*before return 0, iclass 16, count 0 2006.286.01:58:03.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:58:03.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.01:58:03.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.01:58:03.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.01:58:03.44$vck44/vblo=7,734.99 2006.286.01:58:03.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.01:58:03.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.01:58:03.44#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:03.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:58:03.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:58:03.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:58:03.44#ibcon#enter wrdev, iclass 18, count 0 2006.286.01:58:03.44#ibcon#first serial, iclass 18, count 0 2006.286.01:58:03.44#ibcon#enter sib2, iclass 18, count 0 2006.286.01:58:03.44#ibcon#flushed, iclass 18, count 0 2006.286.01:58:03.44#ibcon#about to write, iclass 18, count 0 2006.286.01:58:03.44#ibcon#wrote, iclass 18, count 0 2006.286.01:58:03.44#ibcon#about to read 3, iclass 18, count 0 2006.286.01:58:03.46#ibcon#read 3, iclass 18, count 0 2006.286.01:58:03.46#ibcon#about to read 4, iclass 18, count 0 2006.286.01:58:03.46#ibcon#read 4, iclass 18, count 0 2006.286.01:58:03.46#ibcon#about to read 5, iclass 18, count 0 2006.286.01:58:03.46#ibcon#read 5, iclass 18, count 0 2006.286.01:58:03.46#ibcon#about to read 6, iclass 18, count 0 2006.286.01:58:03.46#ibcon#read 6, iclass 18, count 0 2006.286.01:58:03.46#ibcon#end of sib2, iclass 18, count 0 2006.286.01:58:03.46#ibcon#*mode == 0, iclass 18, count 0 2006.286.01:58:03.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.01:58:03.46#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.01:58:03.46#ibcon#*before write, iclass 18, count 0 2006.286.01:58:03.46#ibcon#enter sib2, iclass 18, count 0 2006.286.01:58:03.46#ibcon#flushed, iclass 18, count 0 2006.286.01:58:03.46#ibcon#about to write, iclass 18, count 0 2006.286.01:58:03.46#ibcon#wrote, iclass 18, count 0 2006.286.01:58:03.46#ibcon#about to read 3, iclass 18, count 0 2006.286.01:58:03.50#ibcon#read 3, iclass 18, count 0 2006.286.01:58:03.50#ibcon#about to read 4, iclass 18, count 0 2006.286.01:58:03.50#ibcon#read 4, iclass 18, count 0 2006.286.01:58:03.50#ibcon#about to read 5, iclass 18, count 0 2006.286.01:58:03.50#ibcon#read 5, iclass 18, count 0 2006.286.01:58:03.50#ibcon#about to read 6, iclass 18, count 0 2006.286.01:58:03.50#ibcon#read 6, iclass 18, count 0 2006.286.01:58:03.50#ibcon#end of sib2, iclass 18, count 0 2006.286.01:58:03.50#ibcon#*after write, iclass 18, count 0 2006.286.01:58:03.50#ibcon#*before return 0, iclass 18, count 0 2006.286.01:58:03.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:58:03.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.01:58:03.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.01:58:03.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.01:58:03.50$vck44/vb=7,4 2006.286.01:58:03.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.01:58:03.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.01:58:03.50#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:03.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:58:03.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:58:03.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:58:03.56#ibcon#enter wrdev, iclass 20, count 2 2006.286.01:58:03.56#ibcon#first serial, iclass 20, count 2 2006.286.01:58:03.56#ibcon#enter sib2, iclass 20, count 2 2006.286.01:58:03.56#ibcon#flushed, iclass 20, count 2 2006.286.01:58:03.56#ibcon#about to write, iclass 20, count 2 2006.286.01:58:03.56#ibcon#wrote, iclass 20, count 2 2006.286.01:58:03.56#ibcon#about to read 3, iclass 20, count 2 2006.286.01:58:03.58#ibcon#read 3, iclass 20, count 2 2006.286.01:58:03.58#ibcon#about to read 4, iclass 20, count 2 2006.286.01:58:03.58#ibcon#read 4, iclass 20, count 2 2006.286.01:58:03.58#ibcon#about to read 5, iclass 20, count 2 2006.286.01:58:03.58#ibcon#read 5, iclass 20, count 2 2006.286.01:58:03.58#ibcon#about to read 6, iclass 20, count 2 2006.286.01:58:03.58#ibcon#read 6, iclass 20, count 2 2006.286.01:58:03.58#ibcon#end of sib2, iclass 20, count 2 2006.286.01:58:03.58#ibcon#*mode == 0, iclass 20, count 2 2006.286.01:58:03.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.01:58:03.58#ibcon#[27=AT07-04\r\n] 2006.286.01:58:03.58#ibcon#*before write, iclass 20, count 2 2006.286.01:58:03.58#ibcon#enter sib2, iclass 20, count 2 2006.286.01:58:03.58#ibcon#flushed, iclass 20, count 2 2006.286.01:58:03.58#ibcon#about to write, iclass 20, count 2 2006.286.01:58:03.58#ibcon#wrote, iclass 20, count 2 2006.286.01:58:03.58#ibcon#about to read 3, iclass 20, count 2 2006.286.01:58:03.61#ibcon#read 3, iclass 20, count 2 2006.286.01:58:03.61#ibcon#about to read 4, iclass 20, count 2 2006.286.01:58:03.61#ibcon#read 4, iclass 20, count 2 2006.286.01:58:03.61#ibcon#about to read 5, iclass 20, count 2 2006.286.01:58:03.61#ibcon#read 5, iclass 20, count 2 2006.286.01:58:03.61#ibcon#about to read 6, iclass 20, count 2 2006.286.01:58:03.61#ibcon#read 6, iclass 20, count 2 2006.286.01:58:03.61#ibcon#end of sib2, iclass 20, count 2 2006.286.01:58:03.61#ibcon#*after write, iclass 20, count 2 2006.286.01:58:03.61#ibcon#*before return 0, iclass 20, count 2 2006.286.01:58:03.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:58:03.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.01:58:03.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.01:58:03.61#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:03.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:58:03.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:58:03.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:58:03.73#ibcon#enter wrdev, iclass 20, count 0 2006.286.01:58:03.73#ibcon#first serial, iclass 20, count 0 2006.286.01:58:03.73#ibcon#enter sib2, iclass 20, count 0 2006.286.01:58:03.73#ibcon#flushed, iclass 20, count 0 2006.286.01:58:03.73#ibcon#about to write, iclass 20, count 0 2006.286.01:58:03.73#ibcon#wrote, iclass 20, count 0 2006.286.01:58:03.73#ibcon#about to read 3, iclass 20, count 0 2006.286.01:58:03.75#ibcon#read 3, iclass 20, count 0 2006.286.01:58:03.75#ibcon#about to read 4, iclass 20, count 0 2006.286.01:58:03.75#ibcon#read 4, iclass 20, count 0 2006.286.01:58:03.75#ibcon#about to read 5, iclass 20, count 0 2006.286.01:58:03.75#ibcon#read 5, iclass 20, count 0 2006.286.01:58:03.75#ibcon#about to read 6, iclass 20, count 0 2006.286.01:58:03.75#ibcon#read 6, iclass 20, count 0 2006.286.01:58:03.75#ibcon#end of sib2, iclass 20, count 0 2006.286.01:58:03.75#ibcon#*mode == 0, iclass 20, count 0 2006.286.01:58:03.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.01:58:03.75#ibcon#[27=USB\r\n] 2006.286.01:58:03.75#ibcon#*before write, iclass 20, count 0 2006.286.01:58:03.75#ibcon#enter sib2, iclass 20, count 0 2006.286.01:58:03.75#ibcon#flushed, iclass 20, count 0 2006.286.01:58:03.75#ibcon#about to write, iclass 20, count 0 2006.286.01:58:03.75#ibcon#wrote, iclass 20, count 0 2006.286.01:58:03.75#ibcon#about to read 3, iclass 20, count 0 2006.286.01:58:03.78#ibcon#read 3, iclass 20, count 0 2006.286.01:58:03.78#ibcon#about to read 4, iclass 20, count 0 2006.286.01:58:03.78#ibcon#read 4, iclass 20, count 0 2006.286.01:58:03.78#ibcon#about to read 5, iclass 20, count 0 2006.286.01:58:03.78#ibcon#read 5, iclass 20, count 0 2006.286.01:58:03.78#ibcon#about to read 6, iclass 20, count 0 2006.286.01:58:03.78#ibcon#read 6, iclass 20, count 0 2006.286.01:58:03.78#ibcon#end of sib2, iclass 20, count 0 2006.286.01:58:03.78#ibcon#*after write, iclass 20, count 0 2006.286.01:58:03.78#ibcon#*before return 0, iclass 20, count 0 2006.286.01:58:03.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:58:03.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.01:58:03.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.01:58:03.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.01:58:03.78$vck44/vblo=8,744.99 2006.286.01:58:03.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.01:58:03.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.01:58:03.78#ibcon#ireg 17 cls_cnt 0 2006.286.01:58:03.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:58:03.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:58:03.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:58:03.78#ibcon#enter wrdev, iclass 22, count 0 2006.286.01:58:03.78#ibcon#first serial, iclass 22, count 0 2006.286.01:58:03.78#ibcon#enter sib2, iclass 22, count 0 2006.286.01:58:03.78#ibcon#flushed, iclass 22, count 0 2006.286.01:58:03.78#ibcon#about to write, iclass 22, count 0 2006.286.01:58:03.78#ibcon#wrote, iclass 22, count 0 2006.286.01:58:03.78#ibcon#about to read 3, iclass 22, count 0 2006.286.01:58:03.80#ibcon#read 3, iclass 22, count 0 2006.286.01:58:03.80#ibcon#about to read 4, iclass 22, count 0 2006.286.01:58:03.80#ibcon#read 4, iclass 22, count 0 2006.286.01:58:03.80#ibcon#about to read 5, iclass 22, count 0 2006.286.01:58:03.80#ibcon#read 5, iclass 22, count 0 2006.286.01:58:03.80#ibcon#about to read 6, iclass 22, count 0 2006.286.01:58:03.80#ibcon#read 6, iclass 22, count 0 2006.286.01:58:03.80#ibcon#end of sib2, iclass 22, count 0 2006.286.01:58:03.80#ibcon#*mode == 0, iclass 22, count 0 2006.286.01:58:03.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.01:58:03.80#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.01:58:03.80#ibcon#*before write, iclass 22, count 0 2006.286.01:58:03.80#ibcon#enter sib2, iclass 22, count 0 2006.286.01:58:03.80#ibcon#flushed, iclass 22, count 0 2006.286.01:58:03.80#ibcon#about to write, iclass 22, count 0 2006.286.01:58:03.80#ibcon#wrote, iclass 22, count 0 2006.286.01:58:03.80#ibcon#about to read 3, iclass 22, count 0 2006.286.01:58:03.84#ibcon#read 3, iclass 22, count 0 2006.286.01:58:03.84#ibcon#about to read 4, iclass 22, count 0 2006.286.01:58:03.84#ibcon#read 4, iclass 22, count 0 2006.286.01:58:03.84#ibcon#about to read 5, iclass 22, count 0 2006.286.01:58:03.84#ibcon#read 5, iclass 22, count 0 2006.286.01:58:03.84#ibcon#about to read 6, iclass 22, count 0 2006.286.01:58:03.84#ibcon#read 6, iclass 22, count 0 2006.286.01:58:03.84#ibcon#end of sib2, iclass 22, count 0 2006.286.01:58:03.84#ibcon#*after write, iclass 22, count 0 2006.286.01:58:03.84#ibcon#*before return 0, iclass 22, count 0 2006.286.01:58:03.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:58:03.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.01:58:03.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.01:58:03.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.01:58:03.84$vck44/vb=8,4 2006.286.01:58:03.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.01:58:03.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.01:58:03.84#ibcon#ireg 11 cls_cnt 2 2006.286.01:58:03.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:58:03.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:58:03.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:58:03.90#ibcon#enter wrdev, iclass 24, count 2 2006.286.01:58:03.90#ibcon#first serial, iclass 24, count 2 2006.286.01:58:03.90#ibcon#enter sib2, iclass 24, count 2 2006.286.01:58:03.90#ibcon#flushed, iclass 24, count 2 2006.286.01:58:03.90#ibcon#about to write, iclass 24, count 2 2006.286.01:58:03.90#ibcon#wrote, iclass 24, count 2 2006.286.01:58:03.90#ibcon#about to read 3, iclass 24, count 2 2006.286.01:58:03.92#ibcon#read 3, iclass 24, count 2 2006.286.01:58:03.92#ibcon#about to read 4, iclass 24, count 2 2006.286.01:58:03.92#ibcon#read 4, iclass 24, count 2 2006.286.01:58:03.92#ibcon#about to read 5, iclass 24, count 2 2006.286.01:58:03.92#ibcon#read 5, iclass 24, count 2 2006.286.01:58:03.92#ibcon#about to read 6, iclass 24, count 2 2006.286.01:58:03.92#ibcon#read 6, iclass 24, count 2 2006.286.01:58:03.92#ibcon#end of sib2, iclass 24, count 2 2006.286.01:58:03.92#ibcon#*mode == 0, iclass 24, count 2 2006.286.01:58:03.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.01:58:03.92#ibcon#[27=AT08-04\r\n] 2006.286.01:58:03.92#ibcon#*before write, iclass 24, count 2 2006.286.01:58:03.92#ibcon#enter sib2, iclass 24, count 2 2006.286.01:58:03.92#ibcon#flushed, iclass 24, count 2 2006.286.01:58:03.92#ibcon#about to write, iclass 24, count 2 2006.286.01:58:03.92#ibcon#wrote, iclass 24, count 2 2006.286.01:58:03.92#ibcon#about to read 3, iclass 24, count 2 2006.286.01:58:03.95#ibcon#read 3, iclass 24, count 2 2006.286.01:58:03.95#ibcon#about to read 4, iclass 24, count 2 2006.286.01:58:03.95#ibcon#read 4, iclass 24, count 2 2006.286.01:58:03.95#ibcon#about to read 5, iclass 24, count 2 2006.286.01:58:03.95#ibcon#read 5, iclass 24, count 2 2006.286.01:58:03.95#ibcon#about to read 6, iclass 24, count 2 2006.286.01:58:03.95#ibcon#read 6, iclass 24, count 2 2006.286.01:58:03.95#ibcon#end of sib2, iclass 24, count 2 2006.286.01:58:03.95#ibcon#*after write, iclass 24, count 2 2006.286.01:58:03.95#ibcon#*before return 0, iclass 24, count 2 2006.286.01:58:03.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:58:03.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.01:58:03.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.01:58:03.95#ibcon#ireg 7 cls_cnt 0 2006.286.01:58:03.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:58:04.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:58:04.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:58:04.07#ibcon#enter wrdev, iclass 24, count 0 2006.286.01:58:04.07#ibcon#first serial, iclass 24, count 0 2006.286.01:58:04.07#ibcon#enter sib2, iclass 24, count 0 2006.286.01:58:04.07#ibcon#flushed, iclass 24, count 0 2006.286.01:58:04.07#ibcon#about to write, iclass 24, count 0 2006.286.01:58:04.07#ibcon#wrote, iclass 24, count 0 2006.286.01:58:04.07#ibcon#about to read 3, iclass 24, count 0 2006.286.01:58:04.09#ibcon#read 3, iclass 24, count 0 2006.286.01:58:04.09#ibcon#about to read 4, iclass 24, count 0 2006.286.01:58:04.09#ibcon#read 4, iclass 24, count 0 2006.286.01:58:04.09#ibcon#about to read 5, iclass 24, count 0 2006.286.01:58:04.09#ibcon#read 5, iclass 24, count 0 2006.286.01:58:04.09#ibcon#about to read 6, iclass 24, count 0 2006.286.01:58:04.09#ibcon#read 6, iclass 24, count 0 2006.286.01:58:04.09#ibcon#end of sib2, iclass 24, count 0 2006.286.01:58:04.09#ibcon#*mode == 0, iclass 24, count 0 2006.286.01:58:04.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.01:58:04.09#ibcon#[27=USB\r\n] 2006.286.01:58:04.09#ibcon#*before write, iclass 24, count 0 2006.286.01:58:04.09#ibcon#enter sib2, iclass 24, count 0 2006.286.01:58:04.09#ibcon#flushed, iclass 24, count 0 2006.286.01:58:04.09#ibcon#about to write, iclass 24, count 0 2006.286.01:58:04.09#ibcon#wrote, iclass 24, count 0 2006.286.01:58:04.09#ibcon#about to read 3, iclass 24, count 0 2006.286.01:58:04.12#ibcon#read 3, iclass 24, count 0 2006.286.01:58:04.12#ibcon#about to read 4, iclass 24, count 0 2006.286.01:58:04.12#ibcon#read 4, iclass 24, count 0 2006.286.01:58:04.12#ibcon#about to read 5, iclass 24, count 0 2006.286.01:58:04.12#ibcon#read 5, iclass 24, count 0 2006.286.01:58:04.12#ibcon#about to read 6, iclass 24, count 0 2006.286.01:58:04.12#ibcon#read 6, iclass 24, count 0 2006.286.01:58:04.12#ibcon#end of sib2, iclass 24, count 0 2006.286.01:58:04.12#ibcon#*after write, iclass 24, count 0 2006.286.01:58:04.12#ibcon#*before return 0, iclass 24, count 0 2006.286.01:58:04.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:58:04.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.01:58:04.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.01:58:04.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.01:58:04.12$vck44/vabw=wide 2006.286.01:58:04.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.01:58:04.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.01:58:04.12#ibcon#ireg 8 cls_cnt 0 2006.286.01:58:04.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:58:04.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:58:04.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:58:04.12#ibcon#enter wrdev, iclass 26, count 0 2006.286.01:58:04.12#ibcon#first serial, iclass 26, count 0 2006.286.01:58:04.12#ibcon#enter sib2, iclass 26, count 0 2006.286.01:58:04.12#ibcon#flushed, iclass 26, count 0 2006.286.01:58:04.12#ibcon#about to write, iclass 26, count 0 2006.286.01:58:04.12#ibcon#wrote, iclass 26, count 0 2006.286.01:58:04.12#ibcon#about to read 3, iclass 26, count 0 2006.286.01:58:04.14#ibcon#read 3, iclass 26, count 0 2006.286.01:58:04.14#ibcon#about to read 4, iclass 26, count 0 2006.286.01:58:04.14#ibcon#read 4, iclass 26, count 0 2006.286.01:58:04.14#ibcon#about to read 5, iclass 26, count 0 2006.286.01:58:04.14#ibcon#read 5, iclass 26, count 0 2006.286.01:58:04.14#ibcon#about to read 6, iclass 26, count 0 2006.286.01:58:04.14#ibcon#read 6, iclass 26, count 0 2006.286.01:58:04.14#ibcon#end of sib2, iclass 26, count 0 2006.286.01:58:04.14#ibcon#*mode == 0, iclass 26, count 0 2006.286.01:58:04.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.01:58:04.14#ibcon#[25=BW32\r\n] 2006.286.01:58:04.14#ibcon#*before write, iclass 26, count 0 2006.286.01:58:04.14#ibcon#enter sib2, iclass 26, count 0 2006.286.01:58:04.14#ibcon#flushed, iclass 26, count 0 2006.286.01:58:04.14#ibcon#about to write, iclass 26, count 0 2006.286.01:58:04.14#ibcon#wrote, iclass 26, count 0 2006.286.01:58:04.14#ibcon#about to read 3, iclass 26, count 0 2006.286.01:58:04.17#ibcon#read 3, iclass 26, count 0 2006.286.01:58:04.17#ibcon#about to read 4, iclass 26, count 0 2006.286.01:58:04.17#ibcon#read 4, iclass 26, count 0 2006.286.01:58:04.17#ibcon#about to read 5, iclass 26, count 0 2006.286.01:58:04.17#ibcon#read 5, iclass 26, count 0 2006.286.01:58:04.17#ibcon#about to read 6, iclass 26, count 0 2006.286.01:58:04.17#ibcon#read 6, iclass 26, count 0 2006.286.01:58:04.17#ibcon#end of sib2, iclass 26, count 0 2006.286.01:58:04.17#ibcon#*after write, iclass 26, count 0 2006.286.01:58:04.17#ibcon#*before return 0, iclass 26, count 0 2006.286.01:58:04.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:58:04.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.01:58:04.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.01:58:04.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.01:58:04.17$vck44/vbbw=wide 2006.286.01:58:04.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.01:58:04.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.01:58:04.17#ibcon#ireg 8 cls_cnt 0 2006.286.01:58:04.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:58:04.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:58:04.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:58:04.24#ibcon#enter wrdev, iclass 28, count 0 2006.286.01:58:04.24#ibcon#first serial, iclass 28, count 0 2006.286.01:58:04.24#ibcon#enter sib2, iclass 28, count 0 2006.286.01:58:04.24#ibcon#flushed, iclass 28, count 0 2006.286.01:58:04.24#ibcon#about to write, iclass 28, count 0 2006.286.01:58:04.24#ibcon#wrote, iclass 28, count 0 2006.286.01:58:04.24#ibcon#about to read 3, iclass 28, count 0 2006.286.01:58:04.26#ibcon#read 3, iclass 28, count 0 2006.286.01:58:04.26#ibcon#about to read 4, iclass 28, count 0 2006.286.01:58:04.26#ibcon#read 4, iclass 28, count 0 2006.286.01:58:04.26#ibcon#about to read 5, iclass 28, count 0 2006.286.01:58:04.26#ibcon#read 5, iclass 28, count 0 2006.286.01:58:04.26#ibcon#about to read 6, iclass 28, count 0 2006.286.01:58:04.26#ibcon#read 6, iclass 28, count 0 2006.286.01:58:04.26#ibcon#end of sib2, iclass 28, count 0 2006.286.01:58:04.26#ibcon#*mode == 0, iclass 28, count 0 2006.286.01:58:04.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.01:58:04.26#ibcon#[27=BW32\r\n] 2006.286.01:58:04.26#ibcon#*before write, iclass 28, count 0 2006.286.01:58:04.26#ibcon#enter sib2, iclass 28, count 0 2006.286.01:58:04.26#ibcon#flushed, iclass 28, count 0 2006.286.01:58:04.26#ibcon#about to write, iclass 28, count 0 2006.286.01:58:04.26#ibcon#wrote, iclass 28, count 0 2006.286.01:58:04.26#ibcon#about to read 3, iclass 28, count 0 2006.286.01:58:04.29#ibcon#read 3, iclass 28, count 0 2006.286.01:58:04.29#ibcon#about to read 4, iclass 28, count 0 2006.286.01:58:04.29#ibcon#read 4, iclass 28, count 0 2006.286.01:58:04.29#ibcon#about to read 5, iclass 28, count 0 2006.286.01:58:04.29#ibcon#read 5, iclass 28, count 0 2006.286.01:58:04.29#ibcon#about to read 6, iclass 28, count 0 2006.286.01:58:04.29#ibcon#read 6, iclass 28, count 0 2006.286.01:58:04.29#ibcon#end of sib2, iclass 28, count 0 2006.286.01:58:04.29#ibcon#*after write, iclass 28, count 0 2006.286.01:58:04.29#ibcon#*before return 0, iclass 28, count 0 2006.286.01:58:04.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:58:04.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.01:58:04.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.01:58:04.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.01:58:04.29$setupk4/ifdk4 2006.286.01:58:04.29$ifdk4/lo= 2006.286.01:58:04.29$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.01:58:04.29$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.01:58:04.29$ifdk4/patch= 2006.286.01:58:04.29$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.01:58:04.29$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.01:58:04.29$setupk4/!*+20s 2006.286.01:58:08.99#abcon#<5=/03 3.1 6.8 21.25 801016.0\r\n> 2006.286.01:58:09.01#abcon#{5=INTERFACE CLEAR} 2006.286.01:58:09.07#abcon#[5=S1D000X0/0*\r\n] 2006.286.01:58:18.13#trakl#Source acquired 2006.286.01:58:18.80$setupk4/"tpicd 2006.286.01:58:18.80$setupk4/echo=off 2006.286.01:58:18.80$setupk4/xlog=off 2006.286.01:58:18.80:!2006.286.02:02:44 2006.286.01:58:20.13#flagr#flagr/antenna,acquired 2006.286.02:02:44.00:preob 2006.286.02:02:45.14/onsource/TRACKING 2006.286.02:02:45.14:!2006.286.02:02:54 2006.286.02:02:54.00:"tape 2006.286.02:02:54.00:"st=record 2006.286.02:02:54.00:data_valid=on 2006.286.02:02:54.00:midob 2006.286.02:02:54.14/onsource/TRACKING 2006.286.02:02:54.14/wx/21.30,1016.0,81 2006.286.02:02:54.31/cable/+6.5012E-03 2006.286.02:02:55.40/va/01,07,usb,yes,32,35 2006.286.02:02:55.40/va/02,06,usb,yes,33,33 2006.286.02:02:55.40/va/03,07,usb,yes,32,34 2006.286.02:02:55.40/va/04,06,usb,yes,34,35 2006.286.02:02:55.40/va/05,03,usb,yes,33,34 2006.286.02:02:55.40/va/06,04,usb,yes,30,29 2006.286.02:02:55.40/va/07,04,usb,yes,30,31 2006.286.02:02:55.40/va/08,03,usb,yes,31,38 2006.286.02:02:55.63/valo/01,524.99,yes,locked 2006.286.02:02:55.63/valo/02,534.99,yes,locked 2006.286.02:02:55.63/valo/03,564.99,yes,locked 2006.286.02:02:55.63/valo/04,624.99,yes,locked 2006.286.02:02:55.63/valo/05,734.99,yes,locked 2006.286.02:02:55.63/valo/06,814.99,yes,locked 2006.286.02:02:55.63/valo/07,864.99,yes,locked 2006.286.02:02:55.63/valo/08,884.99,yes,locked 2006.286.02:02:56.72/vb/01,04,usb,yes,30,28 2006.286.02:02:56.72/vb/02,05,usb,yes,28,28 2006.286.02:02:56.72/vb/03,04,usb,yes,29,32 2006.286.02:02:56.72/vb/04,05,usb,yes,29,28 2006.286.02:02:56.72/vb/05,04,usb,yes,26,28 2006.286.02:02:56.72/vb/06,03,usb,yes,38,33 2006.286.02:02:56.72/vb/07,04,usb,yes,30,30 2006.286.02:02:56.72/vb/08,04,usb,yes,27,31 2006.286.02:02:56.95/vblo/01,629.99,yes,locked 2006.286.02:02:56.95/vblo/02,634.99,yes,locked 2006.286.02:02:56.95/vblo/03,649.99,yes,locked 2006.286.02:02:56.95/vblo/04,679.99,yes,locked 2006.286.02:02:56.95/vblo/05,709.99,yes,locked 2006.286.02:02:56.95/vblo/06,719.99,yes,locked 2006.286.02:02:56.95/vblo/07,734.99,yes,locked 2006.286.02:02:56.95/vblo/08,744.99,yes,locked 2006.286.02:02:57.10/vabw/8 2006.286.02:02:57.25/vbbw/8 2006.286.02:02:57.34/xfe/off,on,12.0 2006.286.02:02:57.72/ifatt/23,28,28,28 2006.286.02:02:58.08/fmout-gps/S +2.77E-07 2006.286.02:02:58.09:!2006.286.02:06:34 2006.286.02:06:34.01:data_valid=off 2006.286.02:06:34.02:"et 2006.286.02:06:34.02:!+3s 2006.286.02:06:37.04:"tape 2006.286.02:06:37.04:postob 2006.286.02:06:37.11/cable/+6.5021E-03 2006.286.02:06:37.11/wx/21.28,1016.0,81 2006.286.02:06:37.17/fmout-gps/S +2.80E-07 2006.286.02:06:37.17:scan_name=286-0217,jd0610,80 2006.286.02:06:37.18:source=3c274,123049.42,122328.0,2000.0,ccw 2006.286.02:06:39.13#flagr#flagr/antenna,new-source 2006.286.02:06:39.14:checkk5 2006.286.02:06:39.56/chk_autoobs//k5ts1/ autoobs is running! 2006.286.02:06:39.98/chk_autoobs//k5ts2/ autoobs is running! 2006.286.02:06:40.39/chk_autoobs//k5ts3/ autoobs is running! 2006.286.02:06:40.79/chk_autoobs//k5ts4/ autoobs is running! 2006.286.02:06:41.17/chk_obsdata//k5ts1/T2860202??a.dat file size is correct (nominal:880MB, actual:880MB). 2006.286.02:06:41.57/chk_obsdata//k5ts2/T2860202??b.dat file size is correct (nominal:880MB, actual:880MB). 2006.286.02:06:41.99/chk_obsdata//k5ts3/T2860202??c.dat file size is correct (nominal:880MB, actual:880MB). 2006.286.02:06:42.36/chk_obsdata//k5ts4/T2860202??d.dat file size is correct (nominal:880MB, actual:880MB). 2006.286.02:06:43.38/k5log//k5ts1_log_newline 2006.286.02:06:44.17/k5log//k5ts2_log_newline 2006.286.02:06:44.95/k5log//k5ts3_log_newline 2006.286.02:06:45.71/k5log//k5ts4_log_newline 2006.286.02:06:45.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.02:06:45.73:setupk4=1 2006.286.02:06:45.73$setupk4/echo=on 2006.286.02:06:45.73$setupk4/pcalon 2006.286.02:06:45.73$pcalon/"no phase cal control is implemented here 2006.286.02:06:45.73$setupk4/"tpicd=stop 2006.286.02:06:45.73$setupk4/"rec=synch_on 2006.286.02:06:45.73$setupk4/"rec_mode=128 2006.286.02:06:45.73$setupk4/!* 2006.286.02:06:45.74$setupk4/recpk4 2006.286.02:06:45.74$recpk4/recpatch= 2006.286.02:06:45.74$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.02:06:45.74$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.02:06:45.74$setupk4/vck44 2006.286.02:06:45.74$vck44/valo=1,524.99 2006.286.02:06:45.74#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.02:06:45.74#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.02:06:45.74#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:45.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:06:45.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:06:45.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:06:45.74#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:06:45.74#ibcon#first serial, iclass 21, count 0 2006.286.02:06:45.74#ibcon#enter sib2, iclass 21, count 0 2006.286.02:06:45.74#ibcon#flushed, iclass 21, count 0 2006.286.02:06:45.74#ibcon#about to write, iclass 21, count 0 2006.286.02:06:45.74#ibcon#wrote, iclass 21, count 0 2006.286.02:06:45.74#ibcon#about to read 3, iclass 21, count 0 2006.286.02:06:45.75#ibcon#read 3, iclass 21, count 0 2006.286.02:06:45.75#ibcon#about to read 4, iclass 21, count 0 2006.286.02:06:45.75#ibcon#read 4, iclass 21, count 0 2006.286.02:06:45.75#ibcon#about to read 5, iclass 21, count 0 2006.286.02:06:45.75#ibcon#read 5, iclass 21, count 0 2006.286.02:06:45.75#ibcon#about to read 6, iclass 21, count 0 2006.286.02:06:45.75#ibcon#read 6, iclass 21, count 0 2006.286.02:06:45.75#ibcon#end of sib2, iclass 21, count 0 2006.286.02:06:45.75#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:06:45.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:06:45.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.02:06:45.75#ibcon#*before write, iclass 21, count 0 2006.286.02:06:45.75#ibcon#enter sib2, iclass 21, count 0 2006.286.02:06:45.75#ibcon#flushed, iclass 21, count 0 2006.286.02:06:45.75#ibcon#about to write, iclass 21, count 0 2006.286.02:06:45.75#ibcon#wrote, iclass 21, count 0 2006.286.02:06:45.75#ibcon#about to read 3, iclass 21, count 0 2006.286.02:06:45.80#ibcon#read 3, iclass 21, count 0 2006.286.02:06:45.80#ibcon#about to read 4, iclass 21, count 0 2006.286.02:06:45.80#ibcon#read 4, iclass 21, count 0 2006.286.02:06:45.80#ibcon#about to read 5, iclass 21, count 0 2006.286.02:06:45.80#ibcon#read 5, iclass 21, count 0 2006.286.02:06:45.80#ibcon#about to read 6, iclass 21, count 0 2006.286.02:06:45.80#ibcon#read 6, iclass 21, count 0 2006.286.02:06:45.80#ibcon#end of sib2, iclass 21, count 0 2006.286.02:06:45.80#ibcon#*after write, iclass 21, count 0 2006.286.02:06:45.80#ibcon#*before return 0, iclass 21, count 0 2006.286.02:06:45.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:06:45.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:06:45.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:06:45.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:06:45.81$vck44/va=1,7 2006.286.02:06:45.81#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.02:06:45.81#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.02:06:45.81#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:45.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:06:45.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:06:45.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:06:45.81#ibcon#enter wrdev, iclass 23, count 2 2006.286.02:06:45.81#ibcon#first serial, iclass 23, count 2 2006.286.02:06:45.81#ibcon#enter sib2, iclass 23, count 2 2006.286.02:06:45.81#ibcon#flushed, iclass 23, count 2 2006.286.02:06:45.81#ibcon#about to write, iclass 23, count 2 2006.286.02:06:45.81#ibcon#wrote, iclass 23, count 2 2006.286.02:06:45.81#ibcon#about to read 3, iclass 23, count 2 2006.286.02:06:45.82#ibcon#read 3, iclass 23, count 2 2006.286.02:06:45.82#ibcon#about to read 4, iclass 23, count 2 2006.286.02:06:45.82#ibcon#read 4, iclass 23, count 2 2006.286.02:06:45.82#ibcon#about to read 5, iclass 23, count 2 2006.286.02:06:45.82#ibcon#read 5, iclass 23, count 2 2006.286.02:06:45.82#ibcon#about to read 6, iclass 23, count 2 2006.286.02:06:45.82#ibcon#read 6, iclass 23, count 2 2006.286.02:06:45.82#ibcon#end of sib2, iclass 23, count 2 2006.286.02:06:45.82#ibcon#*mode == 0, iclass 23, count 2 2006.286.02:06:45.82#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.02:06:45.82#ibcon#[25=AT01-07\r\n] 2006.286.02:06:45.82#ibcon#*before write, iclass 23, count 2 2006.286.02:06:45.82#ibcon#enter sib2, iclass 23, count 2 2006.286.02:06:45.82#ibcon#flushed, iclass 23, count 2 2006.286.02:06:45.82#ibcon#about to write, iclass 23, count 2 2006.286.02:06:45.82#ibcon#wrote, iclass 23, count 2 2006.286.02:06:45.82#ibcon#about to read 3, iclass 23, count 2 2006.286.02:06:45.85#ibcon#read 3, iclass 23, count 2 2006.286.02:06:45.85#ibcon#about to read 4, iclass 23, count 2 2006.286.02:06:45.85#ibcon#read 4, iclass 23, count 2 2006.286.02:06:45.85#ibcon#about to read 5, iclass 23, count 2 2006.286.02:06:45.85#ibcon#read 5, iclass 23, count 2 2006.286.02:06:45.85#ibcon#about to read 6, iclass 23, count 2 2006.286.02:06:45.85#ibcon#read 6, iclass 23, count 2 2006.286.02:06:45.85#ibcon#end of sib2, iclass 23, count 2 2006.286.02:06:45.85#ibcon#*after write, iclass 23, count 2 2006.286.02:06:45.85#ibcon#*before return 0, iclass 23, count 2 2006.286.02:06:45.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:06:45.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:06:45.85#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.02:06:45.85#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:45.85#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:06:45.97#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:06:45.97#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:06:45.97#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:06:45.97#ibcon#first serial, iclass 23, count 0 2006.286.02:06:45.97#ibcon#enter sib2, iclass 23, count 0 2006.286.02:06:45.97#ibcon#flushed, iclass 23, count 0 2006.286.02:06:45.97#ibcon#about to write, iclass 23, count 0 2006.286.02:06:45.97#ibcon#wrote, iclass 23, count 0 2006.286.02:06:45.97#ibcon#about to read 3, iclass 23, count 0 2006.286.02:06:45.99#ibcon#read 3, iclass 23, count 0 2006.286.02:06:45.99#ibcon#about to read 4, iclass 23, count 0 2006.286.02:06:45.99#ibcon#read 4, iclass 23, count 0 2006.286.02:06:45.99#ibcon#about to read 5, iclass 23, count 0 2006.286.02:06:45.99#ibcon#read 5, iclass 23, count 0 2006.286.02:06:45.99#ibcon#about to read 6, iclass 23, count 0 2006.286.02:06:45.99#ibcon#read 6, iclass 23, count 0 2006.286.02:06:45.99#ibcon#end of sib2, iclass 23, count 0 2006.286.02:06:45.99#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:06:45.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:06:45.99#ibcon#[25=USB\r\n] 2006.286.02:06:45.99#ibcon#*before write, iclass 23, count 0 2006.286.02:06:45.99#ibcon#enter sib2, iclass 23, count 0 2006.286.02:06:45.99#ibcon#flushed, iclass 23, count 0 2006.286.02:06:45.99#ibcon#about to write, iclass 23, count 0 2006.286.02:06:45.99#ibcon#wrote, iclass 23, count 0 2006.286.02:06:45.99#ibcon#about to read 3, iclass 23, count 0 2006.286.02:06:46.02#ibcon#read 3, iclass 23, count 0 2006.286.02:06:46.02#ibcon#about to read 4, iclass 23, count 0 2006.286.02:06:46.02#ibcon#read 4, iclass 23, count 0 2006.286.02:06:46.02#ibcon#about to read 5, iclass 23, count 0 2006.286.02:06:46.02#ibcon#read 5, iclass 23, count 0 2006.286.02:06:46.02#ibcon#about to read 6, iclass 23, count 0 2006.286.02:06:46.02#ibcon#read 6, iclass 23, count 0 2006.286.02:06:46.02#ibcon#end of sib2, iclass 23, count 0 2006.286.02:06:46.02#ibcon#*after write, iclass 23, count 0 2006.286.02:06:46.02#ibcon#*before return 0, iclass 23, count 0 2006.286.02:06:46.02#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:06:46.02#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:06:46.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:06:46.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:06:46.03$vck44/valo=2,534.99 2006.286.02:06:46.03#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.02:06:46.03#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.02:06:46.03#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:46.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:06:46.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:06:46.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:06:46.03#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:06:46.03#ibcon#first serial, iclass 25, count 0 2006.286.02:06:46.03#ibcon#enter sib2, iclass 25, count 0 2006.286.02:06:46.03#ibcon#flushed, iclass 25, count 0 2006.286.02:06:46.03#ibcon#about to write, iclass 25, count 0 2006.286.02:06:46.03#ibcon#wrote, iclass 25, count 0 2006.286.02:06:46.03#ibcon#about to read 3, iclass 25, count 0 2006.286.02:06:46.04#ibcon#read 3, iclass 25, count 0 2006.286.02:06:46.04#ibcon#about to read 4, iclass 25, count 0 2006.286.02:06:46.04#ibcon#read 4, iclass 25, count 0 2006.286.02:06:46.04#ibcon#about to read 5, iclass 25, count 0 2006.286.02:06:46.04#ibcon#read 5, iclass 25, count 0 2006.286.02:06:46.04#ibcon#about to read 6, iclass 25, count 0 2006.286.02:06:46.04#ibcon#read 6, iclass 25, count 0 2006.286.02:06:46.04#ibcon#end of sib2, iclass 25, count 0 2006.286.02:06:46.04#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:06:46.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:06:46.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.02:06:46.04#ibcon#*before write, iclass 25, count 0 2006.286.02:06:46.04#ibcon#enter sib2, iclass 25, count 0 2006.286.02:06:46.04#ibcon#flushed, iclass 25, count 0 2006.286.02:06:46.04#ibcon#about to write, iclass 25, count 0 2006.286.02:06:46.04#ibcon#wrote, iclass 25, count 0 2006.286.02:06:46.04#ibcon#about to read 3, iclass 25, count 0 2006.286.02:06:46.08#ibcon#read 3, iclass 25, count 0 2006.286.02:06:46.08#ibcon#about to read 4, iclass 25, count 0 2006.286.02:06:46.08#ibcon#read 4, iclass 25, count 0 2006.286.02:06:46.08#ibcon#about to read 5, iclass 25, count 0 2006.286.02:06:46.08#ibcon#read 5, iclass 25, count 0 2006.286.02:06:46.08#ibcon#about to read 6, iclass 25, count 0 2006.286.02:06:46.08#ibcon#read 6, iclass 25, count 0 2006.286.02:06:46.08#ibcon#end of sib2, iclass 25, count 0 2006.286.02:06:46.08#ibcon#*after write, iclass 25, count 0 2006.286.02:06:46.08#ibcon#*before return 0, iclass 25, count 0 2006.286.02:06:46.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:06:46.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:06:46.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:06:46.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:06:46.09$vck44/va=2,6 2006.286.02:06:46.09#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.02:06:46.09#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.02:06:46.09#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:46.09#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:06:46.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:06:46.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:06:46.14#ibcon#enter wrdev, iclass 27, count 2 2006.286.02:06:46.14#ibcon#first serial, iclass 27, count 2 2006.286.02:06:46.14#ibcon#enter sib2, iclass 27, count 2 2006.286.02:06:46.14#ibcon#flushed, iclass 27, count 2 2006.286.02:06:46.14#ibcon#about to write, iclass 27, count 2 2006.286.02:06:46.14#ibcon#wrote, iclass 27, count 2 2006.286.02:06:46.14#ibcon#about to read 3, iclass 27, count 2 2006.286.02:06:46.15#ibcon#read 3, iclass 27, count 2 2006.286.02:06:46.15#ibcon#about to read 4, iclass 27, count 2 2006.286.02:06:46.15#ibcon#read 4, iclass 27, count 2 2006.286.02:06:46.15#ibcon#about to read 5, iclass 27, count 2 2006.286.02:06:46.15#ibcon#read 5, iclass 27, count 2 2006.286.02:06:46.15#ibcon#about to read 6, iclass 27, count 2 2006.286.02:06:46.15#ibcon#read 6, iclass 27, count 2 2006.286.02:06:46.15#ibcon#end of sib2, iclass 27, count 2 2006.286.02:06:46.15#ibcon#*mode == 0, iclass 27, count 2 2006.286.02:06:46.15#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.02:06:46.15#ibcon#[25=AT02-06\r\n] 2006.286.02:06:46.15#ibcon#*before write, iclass 27, count 2 2006.286.02:06:46.15#ibcon#enter sib2, iclass 27, count 2 2006.286.02:06:46.15#ibcon#flushed, iclass 27, count 2 2006.286.02:06:46.15#ibcon#about to write, iclass 27, count 2 2006.286.02:06:46.15#ibcon#wrote, iclass 27, count 2 2006.286.02:06:46.15#ibcon#about to read 3, iclass 27, count 2 2006.286.02:06:46.18#ibcon#read 3, iclass 27, count 2 2006.286.02:06:46.18#ibcon#about to read 4, iclass 27, count 2 2006.286.02:06:46.18#ibcon#read 4, iclass 27, count 2 2006.286.02:06:46.18#ibcon#about to read 5, iclass 27, count 2 2006.286.02:06:46.18#ibcon#read 5, iclass 27, count 2 2006.286.02:06:46.18#ibcon#about to read 6, iclass 27, count 2 2006.286.02:06:46.18#ibcon#read 6, iclass 27, count 2 2006.286.02:06:46.18#ibcon#end of sib2, iclass 27, count 2 2006.286.02:06:46.18#ibcon#*after write, iclass 27, count 2 2006.286.02:06:46.18#ibcon#*before return 0, iclass 27, count 2 2006.286.02:06:46.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:06:46.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:06:46.18#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.02:06:46.18#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:46.18#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:06:46.31#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:06:46.31#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:06:46.31#ibcon#enter wrdev, iclass 27, count 0 2006.286.02:06:46.31#ibcon#first serial, iclass 27, count 0 2006.286.02:06:46.31#ibcon#enter sib2, iclass 27, count 0 2006.286.02:06:46.31#ibcon#flushed, iclass 27, count 0 2006.286.02:06:46.31#ibcon#about to write, iclass 27, count 0 2006.286.02:06:46.31#ibcon#wrote, iclass 27, count 0 2006.286.02:06:46.31#ibcon#about to read 3, iclass 27, count 0 2006.286.02:06:46.33#ibcon#read 3, iclass 27, count 0 2006.286.02:06:46.33#ibcon#about to read 4, iclass 27, count 0 2006.286.02:06:46.33#ibcon#read 4, iclass 27, count 0 2006.286.02:06:46.33#ibcon#about to read 5, iclass 27, count 0 2006.286.02:06:46.33#ibcon#read 5, iclass 27, count 0 2006.286.02:06:46.33#ibcon#about to read 6, iclass 27, count 0 2006.286.02:06:46.33#ibcon#read 6, iclass 27, count 0 2006.286.02:06:46.33#ibcon#end of sib2, iclass 27, count 0 2006.286.02:06:46.33#ibcon#*mode == 0, iclass 27, count 0 2006.286.02:06:46.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.02:06:46.33#ibcon#[25=USB\r\n] 2006.286.02:06:46.33#ibcon#*before write, iclass 27, count 0 2006.286.02:06:46.33#ibcon#enter sib2, iclass 27, count 0 2006.286.02:06:46.33#ibcon#flushed, iclass 27, count 0 2006.286.02:06:46.33#ibcon#about to write, iclass 27, count 0 2006.286.02:06:46.33#ibcon#wrote, iclass 27, count 0 2006.286.02:06:46.33#ibcon#about to read 3, iclass 27, count 0 2006.286.02:06:46.36#ibcon#read 3, iclass 27, count 0 2006.286.02:06:46.36#ibcon#about to read 4, iclass 27, count 0 2006.286.02:06:46.36#ibcon#read 4, iclass 27, count 0 2006.286.02:06:46.36#ibcon#about to read 5, iclass 27, count 0 2006.286.02:06:46.36#ibcon#read 5, iclass 27, count 0 2006.286.02:06:46.36#ibcon#about to read 6, iclass 27, count 0 2006.286.02:06:46.36#ibcon#read 6, iclass 27, count 0 2006.286.02:06:46.36#ibcon#end of sib2, iclass 27, count 0 2006.286.02:06:46.36#ibcon#*after write, iclass 27, count 0 2006.286.02:06:46.36#ibcon#*before return 0, iclass 27, count 0 2006.286.02:06:46.36#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:06:46.36#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:06:46.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.02:06:46.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.02:06:46.37$vck44/valo=3,564.99 2006.286.02:06:46.37#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.02:06:46.37#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.02:06:46.37#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:46.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:06:46.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:06:46.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:06:46.37#ibcon#enter wrdev, iclass 29, count 0 2006.286.02:06:46.37#ibcon#first serial, iclass 29, count 0 2006.286.02:06:46.37#ibcon#enter sib2, iclass 29, count 0 2006.286.02:06:46.37#ibcon#flushed, iclass 29, count 0 2006.286.02:06:46.37#ibcon#about to write, iclass 29, count 0 2006.286.02:06:46.37#ibcon#wrote, iclass 29, count 0 2006.286.02:06:46.37#ibcon#about to read 3, iclass 29, count 0 2006.286.02:06:46.38#ibcon#read 3, iclass 29, count 0 2006.286.02:06:46.38#ibcon#about to read 4, iclass 29, count 0 2006.286.02:06:46.38#ibcon#read 4, iclass 29, count 0 2006.286.02:06:46.38#ibcon#about to read 5, iclass 29, count 0 2006.286.02:06:46.38#ibcon#read 5, iclass 29, count 0 2006.286.02:06:46.38#ibcon#about to read 6, iclass 29, count 0 2006.286.02:06:46.38#ibcon#read 6, iclass 29, count 0 2006.286.02:06:46.38#ibcon#end of sib2, iclass 29, count 0 2006.286.02:06:46.38#ibcon#*mode == 0, iclass 29, count 0 2006.286.02:06:46.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.02:06:46.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.02:06:46.38#ibcon#*before write, iclass 29, count 0 2006.286.02:06:46.38#ibcon#enter sib2, iclass 29, count 0 2006.286.02:06:46.38#ibcon#flushed, iclass 29, count 0 2006.286.02:06:46.38#ibcon#about to write, iclass 29, count 0 2006.286.02:06:46.38#ibcon#wrote, iclass 29, count 0 2006.286.02:06:46.38#ibcon#about to read 3, iclass 29, count 0 2006.286.02:06:46.42#ibcon#read 3, iclass 29, count 0 2006.286.02:06:46.42#ibcon#about to read 4, iclass 29, count 0 2006.286.02:06:46.42#ibcon#read 4, iclass 29, count 0 2006.286.02:06:46.42#ibcon#about to read 5, iclass 29, count 0 2006.286.02:06:46.42#ibcon#read 5, iclass 29, count 0 2006.286.02:06:46.42#ibcon#about to read 6, iclass 29, count 0 2006.286.02:06:46.42#ibcon#read 6, iclass 29, count 0 2006.286.02:06:46.42#ibcon#end of sib2, iclass 29, count 0 2006.286.02:06:46.42#ibcon#*after write, iclass 29, count 0 2006.286.02:06:46.42#ibcon#*before return 0, iclass 29, count 0 2006.286.02:06:46.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:06:46.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:06:46.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.02:06:46.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.02:06:46.43$vck44/va=3,7 2006.286.02:06:46.43#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.02:06:46.43#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.02:06:46.43#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:46.43#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:06:46.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:06:46.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:06:46.47#ibcon#enter wrdev, iclass 31, count 2 2006.286.02:06:46.47#ibcon#first serial, iclass 31, count 2 2006.286.02:06:46.47#ibcon#enter sib2, iclass 31, count 2 2006.286.02:06:46.47#ibcon#flushed, iclass 31, count 2 2006.286.02:06:46.47#ibcon#about to write, iclass 31, count 2 2006.286.02:06:46.47#ibcon#wrote, iclass 31, count 2 2006.286.02:06:46.47#ibcon#about to read 3, iclass 31, count 2 2006.286.02:06:46.49#ibcon#read 3, iclass 31, count 2 2006.286.02:06:46.49#ibcon#about to read 4, iclass 31, count 2 2006.286.02:06:46.49#ibcon#read 4, iclass 31, count 2 2006.286.02:06:46.49#ibcon#about to read 5, iclass 31, count 2 2006.286.02:06:46.49#ibcon#read 5, iclass 31, count 2 2006.286.02:06:46.49#ibcon#about to read 6, iclass 31, count 2 2006.286.02:06:46.49#ibcon#read 6, iclass 31, count 2 2006.286.02:06:46.49#ibcon#end of sib2, iclass 31, count 2 2006.286.02:06:46.49#ibcon#*mode == 0, iclass 31, count 2 2006.286.02:06:46.49#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.02:06:46.49#ibcon#[25=AT03-07\r\n] 2006.286.02:06:46.49#ibcon#*before write, iclass 31, count 2 2006.286.02:06:46.49#ibcon#enter sib2, iclass 31, count 2 2006.286.02:06:46.49#ibcon#flushed, iclass 31, count 2 2006.286.02:06:46.49#ibcon#about to write, iclass 31, count 2 2006.286.02:06:46.49#ibcon#wrote, iclass 31, count 2 2006.286.02:06:46.49#ibcon#about to read 3, iclass 31, count 2 2006.286.02:06:46.52#ibcon#read 3, iclass 31, count 2 2006.286.02:06:46.52#ibcon#about to read 4, iclass 31, count 2 2006.286.02:06:46.52#ibcon#read 4, iclass 31, count 2 2006.286.02:06:46.52#ibcon#about to read 5, iclass 31, count 2 2006.286.02:06:46.52#ibcon#read 5, iclass 31, count 2 2006.286.02:06:46.52#ibcon#about to read 6, iclass 31, count 2 2006.286.02:06:46.52#ibcon#read 6, iclass 31, count 2 2006.286.02:06:46.52#ibcon#end of sib2, iclass 31, count 2 2006.286.02:06:46.52#ibcon#*after write, iclass 31, count 2 2006.286.02:06:46.52#ibcon#*before return 0, iclass 31, count 2 2006.286.02:06:46.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:06:46.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:06:46.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.02:06:46.52#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:46.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:06:46.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:06:46.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:06:46.64#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:06:46.64#ibcon#first serial, iclass 31, count 0 2006.286.02:06:46.64#ibcon#enter sib2, iclass 31, count 0 2006.286.02:06:46.64#ibcon#flushed, iclass 31, count 0 2006.286.02:06:46.64#ibcon#about to write, iclass 31, count 0 2006.286.02:06:46.64#ibcon#wrote, iclass 31, count 0 2006.286.02:06:46.64#ibcon#about to read 3, iclass 31, count 0 2006.286.02:06:46.66#ibcon#read 3, iclass 31, count 0 2006.286.02:06:46.66#ibcon#about to read 4, iclass 31, count 0 2006.286.02:06:46.66#ibcon#read 4, iclass 31, count 0 2006.286.02:06:46.66#ibcon#about to read 5, iclass 31, count 0 2006.286.02:06:46.66#ibcon#read 5, iclass 31, count 0 2006.286.02:06:46.66#ibcon#about to read 6, iclass 31, count 0 2006.286.02:06:46.66#ibcon#read 6, iclass 31, count 0 2006.286.02:06:46.66#ibcon#end of sib2, iclass 31, count 0 2006.286.02:06:46.66#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:06:46.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:06:46.66#ibcon#[25=USB\r\n] 2006.286.02:06:46.66#ibcon#*before write, iclass 31, count 0 2006.286.02:06:46.66#ibcon#enter sib2, iclass 31, count 0 2006.286.02:06:46.66#ibcon#flushed, iclass 31, count 0 2006.286.02:06:46.66#ibcon#about to write, iclass 31, count 0 2006.286.02:06:46.66#ibcon#wrote, iclass 31, count 0 2006.286.02:06:46.66#ibcon#about to read 3, iclass 31, count 0 2006.286.02:06:46.69#ibcon#read 3, iclass 31, count 0 2006.286.02:06:46.69#ibcon#about to read 4, iclass 31, count 0 2006.286.02:06:46.69#ibcon#read 4, iclass 31, count 0 2006.286.02:06:46.69#ibcon#about to read 5, iclass 31, count 0 2006.286.02:06:46.69#ibcon#read 5, iclass 31, count 0 2006.286.02:06:46.69#ibcon#about to read 6, iclass 31, count 0 2006.286.02:06:46.69#ibcon#read 6, iclass 31, count 0 2006.286.02:06:46.69#ibcon#end of sib2, iclass 31, count 0 2006.286.02:06:46.69#ibcon#*after write, iclass 31, count 0 2006.286.02:06:46.69#ibcon#*before return 0, iclass 31, count 0 2006.286.02:06:46.69#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:06:46.69#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:06:46.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:06:46.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:06:46.70$vck44/valo=4,624.99 2006.286.02:06:46.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.02:06:46.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.02:06:46.70#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:46.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:06:46.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:06:46.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:06:46.70#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:06:46.70#ibcon#first serial, iclass 33, count 0 2006.286.02:06:46.70#ibcon#enter sib2, iclass 33, count 0 2006.286.02:06:46.70#ibcon#flushed, iclass 33, count 0 2006.286.02:06:46.70#ibcon#about to write, iclass 33, count 0 2006.286.02:06:46.70#ibcon#wrote, iclass 33, count 0 2006.286.02:06:46.70#ibcon#about to read 3, iclass 33, count 0 2006.286.02:06:46.71#ibcon#read 3, iclass 33, count 0 2006.286.02:06:46.71#ibcon#about to read 4, iclass 33, count 0 2006.286.02:06:46.71#ibcon#read 4, iclass 33, count 0 2006.286.02:06:46.71#ibcon#about to read 5, iclass 33, count 0 2006.286.02:06:46.71#ibcon#read 5, iclass 33, count 0 2006.286.02:06:46.71#ibcon#about to read 6, iclass 33, count 0 2006.286.02:06:46.71#ibcon#read 6, iclass 33, count 0 2006.286.02:06:46.71#ibcon#end of sib2, iclass 33, count 0 2006.286.02:06:46.71#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:06:46.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:06:46.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.02:06:46.71#ibcon#*before write, iclass 33, count 0 2006.286.02:06:46.71#ibcon#enter sib2, iclass 33, count 0 2006.286.02:06:46.71#ibcon#flushed, iclass 33, count 0 2006.286.02:06:46.71#ibcon#about to write, iclass 33, count 0 2006.286.02:06:46.71#ibcon#wrote, iclass 33, count 0 2006.286.02:06:46.71#ibcon#about to read 3, iclass 33, count 0 2006.286.02:06:46.75#ibcon#read 3, iclass 33, count 0 2006.286.02:06:46.75#ibcon#about to read 4, iclass 33, count 0 2006.286.02:06:46.75#ibcon#read 4, iclass 33, count 0 2006.286.02:06:46.75#ibcon#about to read 5, iclass 33, count 0 2006.286.02:06:46.75#ibcon#read 5, iclass 33, count 0 2006.286.02:06:46.75#ibcon#about to read 6, iclass 33, count 0 2006.286.02:06:46.75#ibcon#read 6, iclass 33, count 0 2006.286.02:06:46.75#ibcon#end of sib2, iclass 33, count 0 2006.286.02:06:46.75#ibcon#*after write, iclass 33, count 0 2006.286.02:06:46.75#ibcon#*before return 0, iclass 33, count 0 2006.286.02:06:46.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:06:46.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:06:46.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:06:46.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:06:46.76$vck44/va=4,6 2006.286.02:06:46.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.02:06:46.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.02:06:46.76#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:46.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:06:46.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:06:46.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:06:46.80#ibcon#enter wrdev, iclass 35, count 2 2006.286.02:06:46.80#ibcon#first serial, iclass 35, count 2 2006.286.02:06:46.80#ibcon#enter sib2, iclass 35, count 2 2006.286.02:06:46.80#ibcon#flushed, iclass 35, count 2 2006.286.02:06:46.80#ibcon#about to write, iclass 35, count 2 2006.286.02:06:46.80#ibcon#wrote, iclass 35, count 2 2006.286.02:06:46.80#ibcon#about to read 3, iclass 35, count 2 2006.286.02:06:46.82#ibcon#read 3, iclass 35, count 2 2006.286.02:06:46.82#ibcon#about to read 4, iclass 35, count 2 2006.286.02:06:46.82#ibcon#read 4, iclass 35, count 2 2006.286.02:06:46.82#ibcon#about to read 5, iclass 35, count 2 2006.286.02:06:46.82#ibcon#read 5, iclass 35, count 2 2006.286.02:06:46.82#ibcon#about to read 6, iclass 35, count 2 2006.286.02:06:46.82#ibcon#read 6, iclass 35, count 2 2006.286.02:06:46.82#ibcon#end of sib2, iclass 35, count 2 2006.286.02:06:46.82#ibcon#*mode == 0, iclass 35, count 2 2006.286.02:06:46.82#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.02:06:46.82#ibcon#[25=AT04-06\r\n] 2006.286.02:06:46.82#ibcon#*before write, iclass 35, count 2 2006.286.02:06:46.82#ibcon#enter sib2, iclass 35, count 2 2006.286.02:06:46.82#ibcon#flushed, iclass 35, count 2 2006.286.02:06:46.82#ibcon#about to write, iclass 35, count 2 2006.286.02:06:46.82#ibcon#wrote, iclass 35, count 2 2006.286.02:06:46.82#ibcon#about to read 3, iclass 35, count 2 2006.286.02:06:46.85#ibcon#read 3, iclass 35, count 2 2006.286.02:06:46.85#ibcon#about to read 4, iclass 35, count 2 2006.286.02:06:46.85#ibcon#read 4, iclass 35, count 2 2006.286.02:06:46.85#ibcon#about to read 5, iclass 35, count 2 2006.286.02:06:46.85#ibcon#read 5, iclass 35, count 2 2006.286.02:06:46.85#ibcon#about to read 6, iclass 35, count 2 2006.286.02:06:46.85#ibcon#read 6, iclass 35, count 2 2006.286.02:06:46.85#ibcon#end of sib2, iclass 35, count 2 2006.286.02:06:46.85#ibcon#*after write, iclass 35, count 2 2006.286.02:06:46.85#ibcon#*before return 0, iclass 35, count 2 2006.286.02:06:46.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:06:46.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:06:46.85#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.02:06:46.85#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:46.85#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:06:46.97#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:06:46.97#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:06:46.97#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:06:46.97#ibcon#first serial, iclass 35, count 0 2006.286.02:06:46.97#ibcon#enter sib2, iclass 35, count 0 2006.286.02:06:46.97#ibcon#flushed, iclass 35, count 0 2006.286.02:06:46.97#ibcon#about to write, iclass 35, count 0 2006.286.02:06:46.97#ibcon#wrote, iclass 35, count 0 2006.286.02:06:46.97#ibcon#about to read 3, iclass 35, count 0 2006.286.02:06:46.99#ibcon#read 3, iclass 35, count 0 2006.286.02:06:46.99#ibcon#about to read 4, iclass 35, count 0 2006.286.02:06:46.99#ibcon#read 4, iclass 35, count 0 2006.286.02:06:46.99#ibcon#about to read 5, iclass 35, count 0 2006.286.02:06:46.99#ibcon#read 5, iclass 35, count 0 2006.286.02:06:46.99#ibcon#about to read 6, iclass 35, count 0 2006.286.02:06:46.99#ibcon#read 6, iclass 35, count 0 2006.286.02:06:46.99#ibcon#end of sib2, iclass 35, count 0 2006.286.02:06:46.99#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:06:46.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:06:46.99#ibcon#[25=USB\r\n] 2006.286.02:06:46.99#ibcon#*before write, iclass 35, count 0 2006.286.02:06:46.99#ibcon#enter sib2, iclass 35, count 0 2006.286.02:06:46.99#ibcon#flushed, iclass 35, count 0 2006.286.02:06:46.99#ibcon#about to write, iclass 35, count 0 2006.286.02:06:46.99#ibcon#wrote, iclass 35, count 0 2006.286.02:06:46.99#ibcon#about to read 3, iclass 35, count 0 2006.286.02:06:47.02#ibcon#read 3, iclass 35, count 0 2006.286.02:06:47.02#ibcon#about to read 4, iclass 35, count 0 2006.286.02:06:47.02#ibcon#read 4, iclass 35, count 0 2006.286.02:06:47.02#ibcon#about to read 5, iclass 35, count 0 2006.286.02:06:47.02#ibcon#read 5, iclass 35, count 0 2006.286.02:06:47.02#ibcon#about to read 6, iclass 35, count 0 2006.286.02:06:47.02#ibcon#read 6, iclass 35, count 0 2006.286.02:06:47.02#ibcon#end of sib2, iclass 35, count 0 2006.286.02:06:47.02#ibcon#*after write, iclass 35, count 0 2006.286.02:06:47.02#ibcon#*before return 0, iclass 35, count 0 2006.286.02:06:47.02#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:06:47.02#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:06:47.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:06:47.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:06:47.03$vck44/valo=5,734.99 2006.286.02:06:47.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.02:06:47.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.02:06:47.03#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:47.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:06:47.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:06:47.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:06:47.03#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:06:47.03#ibcon#first serial, iclass 37, count 0 2006.286.02:06:47.03#ibcon#enter sib2, iclass 37, count 0 2006.286.02:06:47.03#ibcon#flushed, iclass 37, count 0 2006.286.02:06:47.03#ibcon#about to write, iclass 37, count 0 2006.286.02:06:47.03#ibcon#wrote, iclass 37, count 0 2006.286.02:06:47.03#ibcon#about to read 3, iclass 37, count 0 2006.286.02:06:47.04#ibcon#read 3, iclass 37, count 0 2006.286.02:06:47.04#ibcon#about to read 4, iclass 37, count 0 2006.286.02:06:47.04#ibcon#read 4, iclass 37, count 0 2006.286.02:06:47.04#ibcon#about to read 5, iclass 37, count 0 2006.286.02:06:47.04#ibcon#read 5, iclass 37, count 0 2006.286.02:06:47.04#ibcon#about to read 6, iclass 37, count 0 2006.286.02:06:47.04#ibcon#read 6, iclass 37, count 0 2006.286.02:06:47.04#ibcon#end of sib2, iclass 37, count 0 2006.286.02:06:47.04#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:06:47.04#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:06:47.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.02:06:47.04#ibcon#*before write, iclass 37, count 0 2006.286.02:06:47.04#ibcon#enter sib2, iclass 37, count 0 2006.286.02:06:47.04#ibcon#flushed, iclass 37, count 0 2006.286.02:06:47.04#ibcon#about to write, iclass 37, count 0 2006.286.02:06:47.04#ibcon#wrote, iclass 37, count 0 2006.286.02:06:47.04#ibcon#about to read 3, iclass 37, count 0 2006.286.02:06:47.08#ibcon#read 3, iclass 37, count 0 2006.286.02:06:47.08#ibcon#about to read 4, iclass 37, count 0 2006.286.02:06:47.08#ibcon#read 4, iclass 37, count 0 2006.286.02:06:47.08#ibcon#about to read 5, iclass 37, count 0 2006.286.02:06:47.08#ibcon#read 5, iclass 37, count 0 2006.286.02:06:47.08#ibcon#about to read 6, iclass 37, count 0 2006.286.02:06:47.08#ibcon#read 6, iclass 37, count 0 2006.286.02:06:47.08#ibcon#end of sib2, iclass 37, count 0 2006.286.02:06:47.08#ibcon#*after write, iclass 37, count 0 2006.286.02:06:47.08#ibcon#*before return 0, iclass 37, count 0 2006.286.02:06:47.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:06:47.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:06:47.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:06:47.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:06:47.09$vck44/va=5,3 2006.286.02:06:47.09#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.02:06:47.09#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.02:06:47.09#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:47.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:06:47.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:06:47.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:06:47.13#ibcon#enter wrdev, iclass 39, count 2 2006.286.02:06:47.13#ibcon#first serial, iclass 39, count 2 2006.286.02:06:47.13#ibcon#enter sib2, iclass 39, count 2 2006.286.02:06:47.13#ibcon#flushed, iclass 39, count 2 2006.286.02:06:47.13#ibcon#about to write, iclass 39, count 2 2006.286.02:06:47.13#ibcon#wrote, iclass 39, count 2 2006.286.02:06:47.13#ibcon#about to read 3, iclass 39, count 2 2006.286.02:06:47.15#ibcon#read 3, iclass 39, count 2 2006.286.02:06:47.15#ibcon#about to read 4, iclass 39, count 2 2006.286.02:06:47.15#ibcon#read 4, iclass 39, count 2 2006.286.02:06:47.15#ibcon#about to read 5, iclass 39, count 2 2006.286.02:06:47.15#ibcon#read 5, iclass 39, count 2 2006.286.02:06:47.15#ibcon#about to read 6, iclass 39, count 2 2006.286.02:06:47.15#ibcon#read 6, iclass 39, count 2 2006.286.02:06:47.15#ibcon#end of sib2, iclass 39, count 2 2006.286.02:06:47.15#ibcon#*mode == 0, iclass 39, count 2 2006.286.02:06:47.15#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.02:06:47.15#ibcon#[25=AT05-03\r\n] 2006.286.02:06:47.15#ibcon#*before write, iclass 39, count 2 2006.286.02:06:47.15#ibcon#enter sib2, iclass 39, count 2 2006.286.02:06:47.15#ibcon#flushed, iclass 39, count 2 2006.286.02:06:47.15#ibcon#about to write, iclass 39, count 2 2006.286.02:06:47.15#ibcon#wrote, iclass 39, count 2 2006.286.02:06:47.15#ibcon#about to read 3, iclass 39, count 2 2006.286.02:06:47.18#ibcon#read 3, iclass 39, count 2 2006.286.02:06:47.18#ibcon#about to read 4, iclass 39, count 2 2006.286.02:06:47.18#ibcon#read 4, iclass 39, count 2 2006.286.02:06:47.18#ibcon#about to read 5, iclass 39, count 2 2006.286.02:06:47.18#ibcon#read 5, iclass 39, count 2 2006.286.02:06:47.18#ibcon#about to read 6, iclass 39, count 2 2006.286.02:06:47.18#ibcon#read 6, iclass 39, count 2 2006.286.02:06:47.18#ibcon#end of sib2, iclass 39, count 2 2006.286.02:06:47.18#ibcon#*after write, iclass 39, count 2 2006.286.02:06:47.18#ibcon#*before return 0, iclass 39, count 2 2006.286.02:06:47.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:06:47.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:06:47.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.02:06:47.18#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:47.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:06:47.30#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:06:47.30#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:06:47.30#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:06:47.30#ibcon#first serial, iclass 39, count 0 2006.286.02:06:47.30#ibcon#enter sib2, iclass 39, count 0 2006.286.02:06:47.30#ibcon#flushed, iclass 39, count 0 2006.286.02:06:47.30#ibcon#about to write, iclass 39, count 0 2006.286.02:06:47.30#ibcon#wrote, iclass 39, count 0 2006.286.02:06:47.30#ibcon#about to read 3, iclass 39, count 0 2006.286.02:06:47.32#ibcon#read 3, iclass 39, count 0 2006.286.02:06:47.32#ibcon#about to read 4, iclass 39, count 0 2006.286.02:06:47.32#ibcon#read 4, iclass 39, count 0 2006.286.02:06:47.32#ibcon#about to read 5, iclass 39, count 0 2006.286.02:06:47.32#ibcon#read 5, iclass 39, count 0 2006.286.02:06:47.32#ibcon#about to read 6, iclass 39, count 0 2006.286.02:06:47.32#ibcon#read 6, iclass 39, count 0 2006.286.02:06:47.32#ibcon#end of sib2, iclass 39, count 0 2006.286.02:06:47.32#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:06:47.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:06:47.32#ibcon#[25=USB\r\n] 2006.286.02:06:47.32#ibcon#*before write, iclass 39, count 0 2006.286.02:06:47.32#ibcon#enter sib2, iclass 39, count 0 2006.286.02:06:47.32#ibcon#flushed, iclass 39, count 0 2006.286.02:06:47.32#ibcon#about to write, iclass 39, count 0 2006.286.02:06:47.32#ibcon#wrote, iclass 39, count 0 2006.286.02:06:47.32#ibcon#about to read 3, iclass 39, count 0 2006.286.02:06:47.35#ibcon#read 3, iclass 39, count 0 2006.286.02:06:47.35#ibcon#about to read 4, iclass 39, count 0 2006.286.02:06:47.35#ibcon#read 4, iclass 39, count 0 2006.286.02:06:47.35#ibcon#about to read 5, iclass 39, count 0 2006.286.02:06:47.35#ibcon#read 5, iclass 39, count 0 2006.286.02:06:47.35#ibcon#about to read 6, iclass 39, count 0 2006.286.02:06:47.35#ibcon#read 6, iclass 39, count 0 2006.286.02:06:47.35#ibcon#end of sib2, iclass 39, count 0 2006.286.02:06:47.35#ibcon#*after write, iclass 39, count 0 2006.286.02:06:47.35#ibcon#*before return 0, iclass 39, count 0 2006.286.02:06:47.35#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:06:47.35#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:06:47.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:06:47.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:06:47.36$vck44/valo=6,814.99 2006.286.02:06:47.36#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.02:06:47.36#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.02:06:47.36#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:47.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:06:47.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:06:47.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:06:47.36#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:06:47.36#ibcon#first serial, iclass 3, count 0 2006.286.02:06:47.36#ibcon#enter sib2, iclass 3, count 0 2006.286.02:06:47.36#ibcon#flushed, iclass 3, count 0 2006.286.02:06:47.36#ibcon#about to write, iclass 3, count 0 2006.286.02:06:47.36#ibcon#wrote, iclass 3, count 0 2006.286.02:06:47.36#ibcon#about to read 3, iclass 3, count 0 2006.286.02:06:47.37#ibcon#read 3, iclass 3, count 0 2006.286.02:06:47.37#ibcon#about to read 4, iclass 3, count 0 2006.286.02:06:47.37#ibcon#read 4, iclass 3, count 0 2006.286.02:06:47.37#ibcon#about to read 5, iclass 3, count 0 2006.286.02:06:47.37#ibcon#read 5, iclass 3, count 0 2006.286.02:06:47.37#ibcon#about to read 6, iclass 3, count 0 2006.286.02:06:47.37#ibcon#read 6, iclass 3, count 0 2006.286.02:06:47.37#ibcon#end of sib2, iclass 3, count 0 2006.286.02:06:47.37#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:06:47.37#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:06:47.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.02:06:47.37#ibcon#*before write, iclass 3, count 0 2006.286.02:06:47.37#ibcon#enter sib2, iclass 3, count 0 2006.286.02:06:47.37#ibcon#flushed, iclass 3, count 0 2006.286.02:06:47.37#ibcon#about to write, iclass 3, count 0 2006.286.02:06:47.37#ibcon#wrote, iclass 3, count 0 2006.286.02:06:47.37#ibcon#about to read 3, iclass 3, count 0 2006.286.02:06:47.41#ibcon#read 3, iclass 3, count 0 2006.286.02:06:47.41#ibcon#about to read 4, iclass 3, count 0 2006.286.02:06:47.41#ibcon#read 4, iclass 3, count 0 2006.286.02:06:47.41#ibcon#about to read 5, iclass 3, count 0 2006.286.02:06:47.41#ibcon#read 5, iclass 3, count 0 2006.286.02:06:47.41#ibcon#about to read 6, iclass 3, count 0 2006.286.02:06:47.41#ibcon#read 6, iclass 3, count 0 2006.286.02:06:47.41#ibcon#end of sib2, iclass 3, count 0 2006.286.02:06:47.41#ibcon#*after write, iclass 3, count 0 2006.286.02:06:47.41#ibcon#*before return 0, iclass 3, count 0 2006.286.02:06:47.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:06:47.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:06:47.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:06:47.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:06:47.42$vck44/va=6,4 2006.286.02:06:47.42#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.02:06:47.42#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.02:06:47.42#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:47.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:06:47.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:06:47.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:06:47.46#ibcon#enter wrdev, iclass 5, count 2 2006.286.02:06:47.46#ibcon#first serial, iclass 5, count 2 2006.286.02:06:47.46#ibcon#enter sib2, iclass 5, count 2 2006.286.02:06:47.46#ibcon#flushed, iclass 5, count 2 2006.286.02:06:47.46#ibcon#about to write, iclass 5, count 2 2006.286.02:06:47.46#ibcon#wrote, iclass 5, count 2 2006.286.02:06:47.46#ibcon#about to read 3, iclass 5, count 2 2006.286.02:06:47.48#ibcon#read 3, iclass 5, count 2 2006.286.02:06:47.48#ibcon#about to read 4, iclass 5, count 2 2006.286.02:06:47.48#ibcon#read 4, iclass 5, count 2 2006.286.02:06:47.48#ibcon#about to read 5, iclass 5, count 2 2006.286.02:06:47.48#ibcon#read 5, iclass 5, count 2 2006.286.02:06:47.48#ibcon#about to read 6, iclass 5, count 2 2006.286.02:06:47.48#ibcon#read 6, iclass 5, count 2 2006.286.02:06:47.48#ibcon#end of sib2, iclass 5, count 2 2006.286.02:06:47.48#ibcon#*mode == 0, iclass 5, count 2 2006.286.02:06:47.48#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.02:06:47.48#ibcon#[25=AT06-04\r\n] 2006.286.02:06:47.48#ibcon#*before write, iclass 5, count 2 2006.286.02:06:47.48#ibcon#enter sib2, iclass 5, count 2 2006.286.02:06:47.48#ibcon#flushed, iclass 5, count 2 2006.286.02:06:47.48#ibcon#about to write, iclass 5, count 2 2006.286.02:06:47.48#ibcon#wrote, iclass 5, count 2 2006.286.02:06:47.48#ibcon#about to read 3, iclass 5, count 2 2006.286.02:06:47.51#ibcon#read 3, iclass 5, count 2 2006.286.02:06:47.51#ibcon#about to read 4, iclass 5, count 2 2006.286.02:06:47.51#ibcon#read 4, iclass 5, count 2 2006.286.02:06:47.51#ibcon#about to read 5, iclass 5, count 2 2006.286.02:06:47.51#ibcon#read 5, iclass 5, count 2 2006.286.02:06:47.51#ibcon#about to read 6, iclass 5, count 2 2006.286.02:06:47.51#ibcon#read 6, iclass 5, count 2 2006.286.02:06:47.51#ibcon#end of sib2, iclass 5, count 2 2006.286.02:06:47.51#ibcon#*after write, iclass 5, count 2 2006.286.02:06:47.51#ibcon#*before return 0, iclass 5, count 2 2006.286.02:06:47.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:06:47.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:06:47.51#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.02:06:47.51#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:47.51#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:06:47.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:06:47.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:06:47.63#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:06:47.63#ibcon#first serial, iclass 5, count 0 2006.286.02:06:47.63#ibcon#enter sib2, iclass 5, count 0 2006.286.02:06:47.63#ibcon#flushed, iclass 5, count 0 2006.286.02:06:47.63#ibcon#about to write, iclass 5, count 0 2006.286.02:06:47.63#ibcon#wrote, iclass 5, count 0 2006.286.02:06:47.63#ibcon#about to read 3, iclass 5, count 0 2006.286.02:06:47.65#ibcon#read 3, iclass 5, count 0 2006.286.02:06:47.65#ibcon#about to read 4, iclass 5, count 0 2006.286.02:06:47.65#ibcon#read 4, iclass 5, count 0 2006.286.02:06:47.65#ibcon#about to read 5, iclass 5, count 0 2006.286.02:06:47.65#ibcon#read 5, iclass 5, count 0 2006.286.02:06:47.65#ibcon#about to read 6, iclass 5, count 0 2006.286.02:06:47.65#ibcon#read 6, iclass 5, count 0 2006.286.02:06:47.65#ibcon#end of sib2, iclass 5, count 0 2006.286.02:06:47.65#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:06:47.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:06:47.65#ibcon#[25=USB\r\n] 2006.286.02:06:47.65#ibcon#*before write, iclass 5, count 0 2006.286.02:06:47.65#ibcon#enter sib2, iclass 5, count 0 2006.286.02:06:47.65#ibcon#flushed, iclass 5, count 0 2006.286.02:06:47.65#ibcon#about to write, iclass 5, count 0 2006.286.02:06:47.65#ibcon#wrote, iclass 5, count 0 2006.286.02:06:47.65#ibcon#about to read 3, iclass 5, count 0 2006.286.02:06:47.68#ibcon#read 3, iclass 5, count 0 2006.286.02:06:47.68#ibcon#about to read 4, iclass 5, count 0 2006.286.02:06:47.68#ibcon#read 4, iclass 5, count 0 2006.286.02:06:47.68#ibcon#about to read 5, iclass 5, count 0 2006.286.02:06:47.68#ibcon#read 5, iclass 5, count 0 2006.286.02:06:47.68#ibcon#about to read 6, iclass 5, count 0 2006.286.02:06:47.68#ibcon#read 6, iclass 5, count 0 2006.286.02:06:47.68#ibcon#end of sib2, iclass 5, count 0 2006.286.02:06:47.68#ibcon#*after write, iclass 5, count 0 2006.286.02:06:47.68#ibcon#*before return 0, iclass 5, count 0 2006.286.02:06:47.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:06:47.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:06:47.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:06:47.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:06:47.69$vck44/valo=7,864.99 2006.286.02:06:47.69#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.02:06:47.69#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.02:06:47.69#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:47.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:06:47.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:06:47.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:06:47.69#ibcon#enter wrdev, iclass 10, count 0 2006.286.02:06:47.69#ibcon#first serial, iclass 10, count 0 2006.286.02:06:47.69#ibcon#enter sib2, iclass 10, count 0 2006.286.02:06:47.69#ibcon#flushed, iclass 10, count 0 2006.286.02:06:47.69#ibcon#about to write, iclass 10, count 0 2006.286.02:06:47.69#ibcon#wrote, iclass 10, count 0 2006.286.02:06:47.69#ibcon#about to read 3, iclass 10, count 0 2006.286.02:06:47.70#ibcon#read 3, iclass 10, count 0 2006.286.02:06:47.70#ibcon#about to read 4, iclass 10, count 0 2006.286.02:06:47.70#ibcon#read 4, iclass 10, count 0 2006.286.02:06:47.70#ibcon#about to read 5, iclass 10, count 0 2006.286.02:06:47.70#ibcon#read 5, iclass 10, count 0 2006.286.02:06:47.70#ibcon#about to read 6, iclass 10, count 0 2006.286.02:06:47.70#ibcon#read 6, iclass 10, count 0 2006.286.02:06:47.70#ibcon#end of sib2, iclass 10, count 0 2006.286.02:06:47.70#ibcon#*mode == 0, iclass 10, count 0 2006.286.02:06:47.70#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.02:06:47.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.02:06:47.70#ibcon#*before write, iclass 10, count 0 2006.286.02:06:47.70#ibcon#enter sib2, iclass 10, count 0 2006.286.02:06:47.70#ibcon#flushed, iclass 10, count 0 2006.286.02:06:47.70#ibcon#about to write, iclass 10, count 0 2006.286.02:06:47.70#ibcon#wrote, iclass 10, count 0 2006.286.02:06:47.70#ibcon#about to read 3, iclass 10, count 0 2006.286.02:06:47.71#abcon#<5=/03 3.3 5.9 21.28 811016.0\r\n> 2006.286.02:06:47.73#abcon#{5=INTERFACE CLEAR} 2006.286.02:06:47.74#ibcon#read 3, iclass 10, count 0 2006.286.02:06:47.74#ibcon#about to read 4, iclass 10, count 0 2006.286.02:06:47.74#ibcon#read 4, iclass 10, count 0 2006.286.02:06:47.74#ibcon#about to read 5, iclass 10, count 0 2006.286.02:06:47.74#ibcon#read 5, iclass 10, count 0 2006.286.02:06:47.74#ibcon#about to read 6, iclass 10, count 0 2006.286.02:06:47.74#ibcon#read 6, iclass 10, count 0 2006.286.02:06:47.74#ibcon#end of sib2, iclass 10, count 0 2006.286.02:06:47.74#ibcon#*after write, iclass 10, count 0 2006.286.02:06:47.74#ibcon#*before return 0, iclass 10, count 0 2006.286.02:06:47.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:06:47.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:06:47.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.02:06:47.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.02:06:47.75$vck44/va=7,4 2006.286.02:06:47.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.02:06:47.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.02:06:47.75#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:47.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.02:06:47.79#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:06:47.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.02:06:47.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.02:06:47.79#ibcon#enter wrdev, iclass 14, count 2 2006.286.02:06:47.79#ibcon#first serial, iclass 14, count 2 2006.286.02:06:47.79#ibcon#enter sib2, iclass 14, count 2 2006.286.02:06:47.79#ibcon#flushed, iclass 14, count 2 2006.286.02:06:47.79#ibcon#about to write, iclass 14, count 2 2006.286.02:06:47.79#ibcon#wrote, iclass 14, count 2 2006.286.02:06:47.79#ibcon#about to read 3, iclass 14, count 2 2006.286.02:06:47.81#ibcon#read 3, iclass 14, count 2 2006.286.02:06:47.81#ibcon#about to read 4, iclass 14, count 2 2006.286.02:06:47.81#ibcon#read 4, iclass 14, count 2 2006.286.02:06:47.81#ibcon#about to read 5, iclass 14, count 2 2006.286.02:06:47.81#ibcon#read 5, iclass 14, count 2 2006.286.02:06:47.81#ibcon#about to read 6, iclass 14, count 2 2006.286.02:06:47.81#ibcon#read 6, iclass 14, count 2 2006.286.02:06:47.81#ibcon#end of sib2, iclass 14, count 2 2006.286.02:06:47.81#ibcon#*mode == 0, iclass 14, count 2 2006.286.02:06:47.81#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.02:06:47.81#ibcon#[25=AT07-04\r\n] 2006.286.02:06:47.81#ibcon#*before write, iclass 14, count 2 2006.286.02:06:47.81#ibcon#enter sib2, iclass 14, count 2 2006.286.02:06:47.81#ibcon#flushed, iclass 14, count 2 2006.286.02:06:47.81#ibcon#about to write, iclass 14, count 2 2006.286.02:06:47.81#ibcon#wrote, iclass 14, count 2 2006.286.02:06:47.81#ibcon#about to read 3, iclass 14, count 2 2006.286.02:06:47.84#ibcon#read 3, iclass 14, count 2 2006.286.02:06:47.84#ibcon#about to read 4, iclass 14, count 2 2006.286.02:06:47.84#ibcon#read 4, iclass 14, count 2 2006.286.02:06:47.84#ibcon#about to read 5, iclass 14, count 2 2006.286.02:06:47.84#ibcon#read 5, iclass 14, count 2 2006.286.02:06:47.84#ibcon#about to read 6, iclass 14, count 2 2006.286.02:06:47.84#ibcon#read 6, iclass 14, count 2 2006.286.02:06:47.84#ibcon#end of sib2, iclass 14, count 2 2006.286.02:06:47.84#ibcon#*after write, iclass 14, count 2 2006.286.02:06:47.84#ibcon#*before return 0, iclass 14, count 2 2006.286.02:06:47.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.02:06:47.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.02:06:47.84#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.02:06:47.84#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:47.84#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.02:06:47.96#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.02:06:47.96#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.02:06:47.96#ibcon#enter wrdev, iclass 14, count 0 2006.286.02:06:47.96#ibcon#first serial, iclass 14, count 0 2006.286.02:06:47.96#ibcon#enter sib2, iclass 14, count 0 2006.286.02:06:47.96#ibcon#flushed, iclass 14, count 0 2006.286.02:06:47.96#ibcon#about to write, iclass 14, count 0 2006.286.02:06:47.96#ibcon#wrote, iclass 14, count 0 2006.286.02:06:47.96#ibcon#about to read 3, iclass 14, count 0 2006.286.02:06:47.98#ibcon#read 3, iclass 14, count 0 2006.286.02:06:47.98#ibcon#about to read 4, iclass 14, count 0 2006.286.02:06:47.98#ibcon#read 4, iclass 14, count 0 2006.286.02:06:47.98#ibcon#about to read 5, iclass 14, count 0 2006.286.02:06:47.98#ibcon#read 5, iclass 14, count 0 2006.286.02:06:47.98#ibcon#about to read 6, iclass 14, count 0 2006.286.02:06:47.98#ibcon#read 6, iclass 14, count 0 2006.286.02:06:47.98#ibcon#end of sib2, iclass 14, count 0 2006.286.02:06:47.98#ibcon#*mode == 0, iclass 14, count 0 2006.286.02:06:47.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.02:06:47.98#ibcon#[25=USB\r\n] 2006.286.02:06:47.98#ibcon#*before write, iclass 14, count 0 2006.286.02:06:47.98#ibcon#enter sib2, iclass 14, count 0 2006.286.02:06:47.98#ibcon#flushed, iclass 14, count 0 2006.286.02:06:47.98#ibcon#about to write, iclass 14, count 0 2006.286.02:06:47.98#ibcon#wrote, iclass 14, count 0 2006.286.02:06:47.98#ibcon#about to read 3, iclass 14, count 0 2006.286.02:06:48.01#ibcon#read 3, iclass 14, count 0 2006.286.02:06:48.01#ibcon#about to read 4, iclass 14, count 0 2006.286.02:06:48.01#ibcon#read 4, iclass 14, count 0 2006.286.02:06:48.01#ibcon#about to read 5, iclass 14, count 0 2006.286.02:06:48.01#ibcon#read 5, iclass 14, count 0 2006.286.02:06:48.01#ibcon#about to read 6, iclass 14, count 0 2006.286.02:06:48.01#ibcon#read 6, iclass 14, count 0 2006.286.02:06:48.01#ibcon#end of sib2, iclass 14, count 0 2006.286.02:06:48.01#ibcon#*after write, iclass 14, count 0 2006.286.02:06:48.01#ibcon#*before return 0, iclass 14, count 0 2006.286.02:06:48.01#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.02:06:48.01#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.02:06:48.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.02:06:48.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.02:06:48.02$vck44/valo=8,884.99 2006.286.02:06:48.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.02:06:48.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.02:06:48.02#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:48.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:06:48.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:06:48.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:06:48.02#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:06:48.02#ibcon#first serial, iclass 17, count 0 2006.286.02:06:48.02#ibcon#enter sib2, iclass 17, count 0 2006.286.02:06:48.02#ibcon#flushed, iclass 17, count 0 2006.286.02:06:48.02#ibcon#about to write, iclass 17, count 0 2006.286.02:06:48.02#ibcon#wrote, iclass 17, count 0 2006.286.02:06:48.02#ibcon#about to read 3, iclass 17, count 0 2006.286.02:06:48.03#ibcon#read 3, iclass 17, count 0 2006.286.02:06:48.03#ibcon#about to read 4, iclass 17, count 0 2006.286.02:06:48.03#ibcon#read 4, iclass 17, count 0 2006.286.02:06:48.03#ibcon#about to read 5, iclass 17, count 0 2006.286.02:06:48.03#ibcon#read 5, iclass 17, count 0 2006.286.02:06:48.03#ibcon#about to read 6, iclass 17, count 0 2006.286.02:06:48.03#ibcon#read 6, iclass 17, count 0 2006.286.02:06:48.03#ibcon#end of sib2, iclass 17, count 0 2006.286.02:06:48.03#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:06:48.03#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:06:48.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.02:06:48.03#ibcon#*before write, iclass 17, count 0 2006.286.02:06:48.03#ibcon#enter sib2, iclass 17, count 0 2006.286.02:06:48.03#ibcon#flushed, iclass 17, count 0 2006.286.02:06:48.03#ibcon#about to write, iclass 17, count 0 2006.286.02:06:48.03#ibcon#wrote, iclass 17, count 0 2006.286.02:06:48.03#ibcon#about to read 3, iclass 17, count 0 2006.286.02:06:48.07#ibcon#read 3, iclass 17, count 0 2006.286.02:06:48.07#ibcon#about to read 4, iclass 17, count 0 2006.286.02:06:48.07#ibcon#read 4, iclass 17, count 0 2006.286.02:06:48.07#ibcon#about to read 5, iclass 17, count 0 2006.286.02:06:48.07#ibcon#read 5, iclass 17, count 0 2006.286.02:06:48.07#ibcon#about to read 6, iclass 17, count 0 2006.286.02:06:48.07#ibcon#read 6, iclass 17, count 0 2006.286.02:06:48.07#ibcon#end of sib2, iclass 17, count 0 2006.286.02:06:48.07#ibcon#*after write, iclass 17, count 0 2006.286.02:06:48.07#ibcon#*before return 0, iclass 17, count 0 2006.286.02:06:48.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:06:48.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:06:48.07#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:06:48.07#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:06:48.08$vck44/va=8,3 2006.286.02:06:48.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.02:06:48.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.02:06:48.08#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:48.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:06:48.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:06:48.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:06:48.12#ibcon#enter wrdev, iclass 19, count 2 2006.286.02:06:48.12#ibcon#first serial, iclass 19, count 2 2006.286.02:06:48.12#ibcon#enter sib2, iclass 19, count 2 2006.286.02:06:48.12#ibcon#flushed, iclass 19, count 2 2006.286.02:06:48.12#ibcon#about to write, iclass 19, count 2 2006.286.02:06:48.12#ibcon#wrote, iclass 19, count 2 2006.286.02:06:48.12#ibcon#about to read 3, iclass 19, count 2 2006.286.02:06:48.14#ibcon#read 3, iclass 19, count 2 2006.286.02:06:48.14#ibcon#about to read 4, iclass 19, count 2 2006.286.02:06:48.14#ibcon#read 4, iclass 19, count 2 2006.286.02:06:48.14#ibcon#about to read 5, iclass 19, count 2 2006.286.02:06:48.14#ibcon#read 5, iclass 19, count 2 2006.286.02:06:48.14#ibcon#about to read 6, iclass 19, count 2 2006.286.02:06:48.14#ibcon#read 6, iclass 19, count 2 2006.286.02:06:48.14#ibcon#end of sib2, iclass 19, count 2 2006.286.02:06:48.14#ibcon#*mode == 0, iclass 19, count 2 2006.286.02:06:48.14#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.02:06:48.14#ibcon#[25=AT08-03\r\n] 2006.286.02:06:48.14#ibcon#*before write, iclass 19, count 2 2006.286.02:06:48.14#ibcon#enter sib2, iclass 19, count 2 2006.286.02:06:48.14#ibcon#flushed, iclass 19, count 2 2006.286.02:06:48.14#ibcon#about to write, iclass 19, count 2 2006.286.02:06:48.14#ibcon#wrote, iclass 19, count 2 2006.286.02:06:48.14#ibcon#about to read 3, iclass 19, count 2 2006.286.02:06:48.17#ibcon#read 3, iclass 19, count 2 2006.286.02:06:48.17#ibcon#about to read 4, iclass 19, count 2 2006.286.02:06:48.17#ibcon#read 4, iclass 19, count 2 2006.286.02:06:48.17#ibcon#about to read 5, iclass 19, count 2 2006.286.02:06:48.17#ibcon#read 5, iclass 19, count 2 2006.286.02:06:48.17#ibcon#about to read 6, iclass 19, count 2 2006.286.02:06:48.17#ibcon#read 6, iclass 19, count 2 2006.286.02:06:48.17#ibcon#end of sib2, iclass 19, count 2 2006.286.02:06:48.17#ibcon#*after write, iclass 19, count 2 2006.286.02:06:48.17#ibcon#*before return 0, iclass 19, count 2 2006.286.02:06:48.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:06:48.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:06:48.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.02:06:48.17#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:48.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:06:48.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:06:48.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:06:48.29#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:06:48.29#ibcon#first serial, iclass 19, count 0 2006.286.02:06:48.29#ibcon#enter sib2, iclass 19, count 0 2006.286.02:06:48.29#ibcon#flushed, iclass 19, count 0 2006.286.02:06:48.29#ibcon#about to write, iclass 19, count 0 2006.286.02:06:48.29#ibcon#wrote, iclass 19, count 0 2006.286.02:06:48.29#ibcon#about to read 3, iclass 19, count 0 2006.286.02:06:48.31#ibcon#read 3, iclass 19, count 0 2006.286.02:06:48.31#ibcon#about to read 4, iclass 19, count 0 2006.286.02:06:48.31#ibcon#read 4, iclass 19, count 0 2006.286.02:06:48.31#ibcon#about to read 5, iclass 19, count 0 2006.286.02:06:48.31#ibcon#read 5, iclass 19, count 0 2006.286.02:06:48.31#ibcon#about to read 6, iclass 19, count 0 2006.286.02:06:48.31#ibcon#read 6, iclass 19, count 0 2006.286.02:06:48.31#ibcon#end of sib2, iclass 19, count 0 2006.286.02:06:48.31#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:06:48.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:06:48.31#ibcon#[25=USB\r\n] 2006.286.02:06:48.31#ibcon#*before write, iclass 19, count 0 2006.286.02:06:48.31#ibcon#enter sib2, iclass 19, count 0 2006.286.02:06:48.31#ibcon#flushed, iclass 19, count 0 2006.286.02:06:48.31#ibcon#about to write, iclass 19, count 0 2006.286.02:06:48.31#ibcon#wrote, iclass 19, count 0 2006.286.02:06:48.31#ibcon#about to read 3, iclass 19, count 0 2006.286.02:06:48.34#ibcon#read 3, iclass 19, count 0 2006.286.02:06:48.34#ibcon#about to read 4, iclass 19, count 0 2006.286.02:06:48.34#ibcon#read 4, iclass 19, count 0 2006.286.02:06:48.34#ibcon#about to read 5, iclass 19, count 0 2006.286.02:06:48.34#ibcon#read 5, iclass 19, count 0 2006.286.02:06:48.34#ibcon#about to read 6, iclass 19, count 0 2006.286.02:06:48.34#ibcon#read 6, iclass 19, count 0 2006.286.02:06:48.34#ibcon#end of sib2, iclass 19, count 0 2006.286.02:06:48.34#ibcon#*after write, iclass 19, count 0 2006.286.02:06:48.34#ibcon#*before return 0, iclass 19, count 0 2006.286.02:06:48.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:06:48.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:06:48.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:06:48.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:06:48.35$vck44/vblo=1,629.99 2006.286.02:06:48.35#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.02:06:48.35#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.02:06:48.35#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:48.35#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:06:48.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:06:48.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:06:48.35#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:06:48.35#ibcon#first serial, iclass 21, count 0 2006.286.02:06:48.35#ibcon#enter sib2, iclass 21, count 0 2006.286.02:06:48.35#ibcon#flushed, iclass 21, count 0 2006.286.02:06:48.35#ibcon#about to write, iclass 21, count 0 2006.286.02:06:48.35#ibcon#wrote, iclass 21, count 0 2006.286.02:06:48.35#ibcon#about to read 3, iclass 21, count 0 2006.286.02:06:48.36#ibcon#read 3, iclass 21, count 0 2006.286.02:06:48.36#ibcon#about to read 4, iclass 21, count 0 2006.286.02:06:48.36#ibcon#read 4, iclass 21, count 0 2006.286.02:06:48.36#ibcon#about to read 5, iclass 21, count 0 2006.286.02:06:48.36#ibcon#read 5, iclass 21, count 0 2006.286.02:06:48.36#ibcon#about to read 6, iclass 21, count 0 2006.286.02:06:48.36#ibcon#read 6, iclass 21, count 0 2006.286.02:06:48.36#ibcon#end of sib2, iclass 21, count 0 2006.286.02:06:48.36#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:06:48.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:06:48.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.02:06:48.36#ibcon#*before write, iclass 21, count 0 2006.286.02:06:48.36#ibcon#enter sib2, iclass 21, count 0 2006.286.02:06:48.36#ibcon#flushed, iclass 21, count 0 2006.286.02:06:48.36#ibcon#about to write, iclass 21, count 0 2006.286.02:06:48.36#ibcon#wrote, iclass 21, count 0 2006.286.02:06:48.36#ibcon#about to read 3, iclass 21, count 0 2006.286.02:06:48.40#ibcon#read 3, iclass 21, count 0 2006.286.02:06:48.40#ibcon#about to read 4, iclass 21, count 0 2006.286.02:06:48.40#ibcon#read 4, iclass 21, count 0 2006.286.02:06:48.40#ibcon#about to read 5, iclass 21, count 0 2006.286.02:06:48.40#ibcon#read 5, iclass 21, count 0 2006.286.02:06:48.40#ibcon#about to read 6, iclass 21, count 0 2006.286.02:06:48.40#ibcon#read 6, iclass 21, count 0 2006.286.02:06:48.40#ibcon#end of sib2, iclass 21, count 0 2006.286.02:06:48.40#ibcon#*after write, iclass 21, count 0 2006.286.02:06:48.40#ibcon#*before return 0, iclass 21, count 0 2006.286.02:06:48.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:06:48.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:06:48.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:06:48.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:06:48.41$vck44/vb=1,4 2006.286.02:06:48.41#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.02:06:48.41#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.02:06:48.41#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:48.41#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:06:48.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:06:48.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:06:48.41#ibcon#enter wrdev, iclass 23, count 2 2006.286.02:06:48.41#ibcon#first serial, iclass 23, count 2 2006.286.02:06:48.41#ibcon#enter sib2, iclass 23, count 2 2006.286.02:06:48.41#ibcon#flushed, iclass 23, count 2 2006.286.02:06:48.41#ibcon#about to write, iclass 23, count 2 2006.286.02:06:48.41#ibcon#wrote, iclass 23, count 2 2006.286.02:06:48.41#ibcon#about to read 3, iclass 23, count 2 2006.286.02:06:48.42#ibcon#read 3, iclass 23, count 2 2006.286.02:06:48.42#ibcon#about to read 4, iclass 23, count 2 2006.286.02:06:48.42#ibcon#read 4, iclass 23, count 2 2006.286.02:06:48.42#ibcon#about to read 5, iclass 23, count 2 2006.286.02:06:48.42#ibcon#read 5, iclass 23, count 2 2006.286.02:06:48.42#ibcon#about to read 6, iclass 23, count 2 2006.286.02:06:48.42#ibcon#read 6, iclass 23, count 2 2006.286.02:06:48.42#ibcon#end of sib2, iclass 23, count 2 2006.286.02:06:48.42#ibcon#*mode == 0, iclass 23, count 2 2006.286.02:06:48.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.02:06:48.42#ibcon#[27=AT01-04\r\n] 2006.286.02:06:48.42#ibcon#*before write, iclass 23, count 2 2006.286.02:06:48.42#ibcon#enter sib2, iclass 23, count 2 2006.286.02:06:48.42#ibcon#flushed, iclass 23, count 2 2006.286.02:06:48.42#ibcon#about to write, iclass 23, count 2 2006.286.02:06:48.42#ibcon#wrote, iclass 23, count 2 2006.286.02:06:48.42#ibcon#about to read 3, iclass 23, count 2 2006.286.02:06:48.45#ibcon#read 3, iclass 23, count 2 2006.286.02:06:48.45#ibcon#about to read 4, iclass 23, count 2 2006.286.02:06:48.45#ibcon#read 4, iclass 23, count 2 2006.286.02:06:48.45#ibcon#about to read 5, iclass 23, count 2 2006.286.02:06:48.45#ibcon#read 5, iclass 23, count 2 2006.286.02:06:48.45#ibcon#about to read 6, iclass 23, count 2 2006.286.02:06:48.45#ibcon#read 6, iclass 23, count 2 2006.286.02:06:48.45#ibcon#end of sib2, iclass 23, count 2 2006.286.02:06:48.45#ibcon#*after write, iclass 23, count 2 2006.286.02:06:48.45#ibcon#*before return 0, iclass 23, count 2 2006.286.02:06:48.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:06:48.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:06:48.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.02:06:48.45#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:48.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:06:48.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:06:48.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:06:48.57#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:06:48.57#ibcon#first serial, iclass 23, count 0 2006.286.02:06:48.57#ibcon#enter sib2, iclass 23, count 0 2006.286.02:06:48.57#ibcon#flushed, iclass 23, count 0 2006.286.02:06:48.57#ibcon#about to write, iclass 23, count 0 2006.286.02:06:48.57#ibcon#wrote, iclass 23, count 0 2006.286.02:06:48.57#ibcon#about to read 3, iclass 23, count 0 2006.286.02:06:48.59#ibcon#read 3, iclass 23, count 0 2006.286.02:06:48.59#ibcon#about to read 4, iclass 23, count 0 2006.286.02:06:48.59#ibcon#read 4, iclass 23, count 0 2006.286.02:06:48.59#ibcon#about to read 5, iclass 23, count 0 2006.286.02:06:48.59#ibcon#read 5, iclass 23, count 0 2006.286.02:06:48.59#ibcon#about to read 6, iclass 23, count 0 2006.286.02:06:48.59#ibcon#read 6, iclass 23, count 0 2006.286.02:06:48.59#ibcon#end of sib2, iclass 23, count 0 2006.286.02:06:48.59#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:06:48.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:06:48.59#ibcon#[27=USB\r\n] 2006.286.02:06:48.59#ibcon#*before write, iclass 23, count 0 2006.286.02:06:48.59#ibcon#enter sib2, iclass 23, count 0 2006.286.02:06:48.59#ibcon#flushed, iclass 23, count 0 2006.286.02:06:48.59#ibcon#about to write, iclass 23, count 0 2006.286.02:06:48.59#ibcon#wrote, iclass 23, count 0 2006.286.02:06:48.59#ibcon#about to read 3, iclass 23, count 0 2006.286.02:06:48.62#ibcon#read 3, iclass 23, count 0 2006.286.02:06:48.62#ibcon#about to read 4, iclass 23, count 0 2006.286.02:06:48.62#ibcon#read 4, iclass 23, count 0 2006.286.02:06:48.62#ibcon#about to read 5, iclass 23, count 0 2006.286.02:06:48.62#ibcon#read 5, iclass 23, count 0 2006.286.02:06:48.62#ibcon#about to read 6, iclass 23, count 0 2006.286.02:06:48.62#ibcon#read 6, iclass 23, count 0 2006.286.02:06:48.62#ibcon#end of sib2, iclass 23, count 0 2006.286.02:06:48.62#ibcon#*after write, iclass 23, count 0 2006.286.02:06:48.62#ibcon#*before return 0, iclass 23, count 0 2006.286.02:06:48.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:06:48.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:06:48.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:06:48.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:06:48.63$vck44/vblo=2,634.99 2006.286.02:06:48.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.02:06:48.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.02:06:48.63#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:48.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:06:48.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:06:48.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:06:48.63#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:06:48.63#ibcon#first serial, iclass 25, count 0 2006.286.02:06:48.63#ibcon#enter sib2, iclass 25, count 0 2006.286.02:06:48.63#ibcon#flushed, iclass 25, count 0 2006.286.02:06:48.63#ibcon#about to write, iclass 25, count 0 2006.286.02:06:48.63#ibcon#wrote, iclass 25, count 0 2006.286.02:06:48.63#ibcon#about to read 3, iclass 25, count 0 2006.286.02:06:48.64#ibcon#read 3, iclass 25, count 0 2006.286.02:06:48.64#ibcon#about to read 4, iclass 25, count 0 2006.286.02:06:48.64#ibcon#read 4, iclass 25, count 0 2006.286.02:06:48.64#ibcon#about to read 5, iclass 25, count 0 2006.286.02:06:48.64#ibcon#read 5, iclass 25, count 0 2006.286.02:06:48.64#ibcon#about to read 6, iclass 25, count 0 2006.286.02:06:48.64#ibcon#read 6, iclass 25, count 0 2006.286.02:06:48.64#ibcon#end of sib2, iclass 25, count 0 2006.286.02:06:48.64#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:06:48.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:06:48.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.02:06:48.64#ibcon#*before write, iclass 25, count 0 2006.286.02:06:48.64#ibcon#enter sib2, iclass 25, count 0 2006.286.02:06:48.64#ibcon#flushed, iclass 25, count 0 2006.286.02:06:48.64#ibcon#about to write, iclass 25, count 0 2006.286.02:06:48.64#ibcon#wrote, iclass 25, count 0 2006.286.02:06:48.64#ibcon#about to read 3, iclass 25, count 0 2006.286.02:06:48.68#ibcon#read 3, iclass 25, count 0 2006.286.02:06:48.68#ibcon#about to read 4, iclass 25, count 0 2006.286.02:06:48.68#ibcon#read 4, iclass 25, count 0 2006.286.02:06:48.68#ibcon#about to read 5, iclass 25, count 0 2006.286.02:06:48.68#ibcon#read 5, iclass 25, count 0 2006.286.02:06:48.68#ibcon#about to read 6, iclass 25, count 0 2006.286.02:06:48.68#ibcon#read 6, iclass 25, count 0 2006.286.02:06:48.68#ibcon#end of sib2, iclass 25, count 0 2006.286.02:06:48.68#ibcon#*after write, iclass 25, count 0 2006.286.02:06:48.68#ibcon#*before return 0, iclass 25, count 0 2006.286.02:06:48.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:06:48.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:06:48.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:06:48.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:06:48.69$vck44/vb=2,5 2006.286.02:06:48.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.02:06:48.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.02:06:48.69#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:48.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:06:48.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:06:48.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:06:48.73#ibcon#enter wrdev, iclass 27, count 2 2006.286.02:06:48.73#ibcon#first serial, iclass 27, count 2 2006.286.02:06:48.73#ibcon#enter sib2, iclass 27, count 2 2006.286.02:06:48.73#ibcon#flushed, iclass 27, count 2 2006.286.02:06:48.73#ibcon#about to write, iclass 27, count 2 2006.286.02:06:48.73#ibcon#wrote, iclass 27, count 2 2006.286.02:06:48.73#ibcon#about to read 3, iclass 27, count 2 2006.286.02:06:48.75#ibcon#read 3, iclass 27, count 2 2006.286.02:06:48.75#ibcon#about to read 4, iclass 27, count 2 2006.286.02:06:48.75#ibcon#read 4, iclass 27, count 2 2006.286.02:06:48.75#ibcon#about to read 5, iclass 27, count 2 2006.286.02:06:48.75#ibcon#read 5, iclass 27, count 2 2006.286.02:06:48.75#ibcon#about to read 6, iclass 27, count 2 2006.286.02:06:48.75#ibcon#read 6, iclass 27, count 2 2006.286.02:06:48.75#ibcon#end of sib2, iclass 27, count 2 2006.286.02:06:48.75#ibcon#*mode == 0, iclass 27, count 2 2006.286.02:06:48.75#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.02:06:48.75#ibcon#[27=AT02-05\r\n] 2006.286.02:06:48.75#ibcon#*before write, iclass 27, count 2 2006.286.02:06:48.75#ibcon#enter sib2, iclass 27, count 2 2006.286.02:06:48.75#ibcon#flushed, iclass 27, count 2 2006.286.02:06:48.75#ibcon#about to write, iclass 27, count 2 2006.286.02:06:48.75#ibcon#wrote, iclass 27, count 2 2006.286.02:06:48.75#ibcon#about to read 3, iclass 27, count 2 2006.286.02:06:48.78#ibcon#read 3, iclass 27, count 2 2006.286.02:06:48.78#ibcon#about to read 4, iclass 27, count 2 2006.286.02:06:48.78#ibcon#read 4, iclass 27, count 2 2006.286.02:06:48.78#ibcon#about to read 5, iclass 27, count 2 2006.286.02:06:48.78#ibcon#read 5, iclass 27, count 2 2006.286.02:06:48.78#ibcon#about to read 6, iclass 27, count 2 2006.286.02:06:48.78#ibcon#read 6, iclass 27, count 2 2006.286.02:06:48.78#ibcon#end of sib2, iclass 27, count 2 2006.286.02:06:48.78#ibcon#*after write, iclass 27, count 2 2006.286.02:06:48.78#ibcon#*before return 0, iclass 27, count 2 2006.286.02:06:48.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:06:48.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:06:48.78#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.02:06:48.78#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:48.78#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:06:48.90#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:06:48.90#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:06:48.90#ibcon#enter wrdev, iclass 27, count 0 2006.286.02:06:48.90#ibcon#first serial, iclass 27, count 0 2006.286.02:06:48.90#ibcon#enter sib2, iclass 27, count 0 2006.286.02:06:48.90#ibcon#flushed, iclass 27, count 0 2006.286.02:06:48.90#ibcon#about to write, iclass 27, count 0 2006.286.02:06:48.90#ibcon#wrote, iclass 27, count 0 2006.286.02:06:48.90#ibcon#about to read 3, iclass 27, count 0 2006.286.02:06:48.92#ibcon#read 3, iclass 27, count 0 2006.286.02:06:48.92#ibcon#about to read 4, iclass 27, count 0 2006.286.02:06:48.92#ibcon#read 4, iclass 27, count 0 2006.286.02:06:48.92#ibcon#about to read 5, iclass 27, count 0 2006.286.02:06:48.92#ibcon#read 5, iclass 27, count 0 2006.286.02:06:48.92#ibcon#about to read 6, iclass 27, count 0 2006.286.02:06:48.92#ibcon#read 6, iclass 27, count 0 2006.286.02:06:48.92#ibcon#end of sib2, iclass 27, count 0 2006.286.02:06:48.92#ibcon#*mode == 0, iclass 27, count 0 2006.286.02:06:48.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.02:06:48.92#ibcon#[27=USB\r\n] 2006.286.02:06:48.92#ibcon#*before write, iclass 27, count 0 2006.286.02:06:48.92#ibcon#enter sib2, iclass 27, count 0 2006.286.02:06:48.92#ibcon#flushed, iclass 27, count 0 2006.286.02:06:48.92#ibcon#about to write, iclass 27, count 0 2006.286.02:06:48.92#ibcon#wrote, iclass 27, count 0 2006.286.02:06:48.92#ibcon#about to read 3, iclass 27, count 0 2006.286.02:06:48.95#ibcon#read 3, iclass 27, count 0 2006.286.02:06:48.95#ibcon#about to read 4, iclass 27, count 0 2006.286.02:06:48.95#ibcon#read 4, iclass 27, count 0 2006.286.02:06:48.95#ibcon#about to read 5, iclass 27, count 0 2006.286.02:06:48.95#ibcon#read 5, iclass 27, count 0 2006.286.02:06:48.95#ibcon#about to read 6, iclass 27, count 0 2006.286.02:06:48.95#ibcon#read 6, iclass 27, count 0 2006.286.02:06:48.95#ibcon#end of sib2, iclass 27, count 0 2006.286.02:06:48.95#ibcon#*after write, iclass 27, count 0 2006.286.02:06:48.95#ibcon#*before return 0, iclass 27, count 0 2006.286.02:06:48.95#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:06:48.95#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:06:48.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.02:06:48.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.02:06:48.96$vck44/vblo=3,649.99 2006.286.02:06:48.96#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.02:06:48.96#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.02:06:48.96#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:48.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:06:48.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:06:48.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:06:48.96#ibcon#enter wrdev, iclass 29, count 0 2006.286.02:06:48.96#ibcon#first serial, iclass 29, count 0 2006.286.02:06:48.96#ibcon#enter sib2, iclass 29, count 0 2006.286.02:06:48.96#ibcon#flushed, iclass 29, count 0 2006.286.02:06:48.96#ibcon#about to write, iclass 29, count 0 2006.286.02:06:48.96#ibcon#wrote, iclass 29, count 0 2006.286.02:06:48.96#ibcon#about to read 3, iclass 29, count 0 2006.286.02:06:48.97#ibcon#read 3, iclass 29, count 0 2006.286.02:06:48.97#ibcon#about to read 4, iclass 29, count 0 2006.286.02:06:48.97#ibcon#read 4, iclass 29, count 0 2006.286.02:06:48.97#ibcon#about to read 5, iclass 29, count 0 2006.286.02:06:48.97#ibcon#read 5, iclass 29, count 0 2006.286.02:06:48.97#ibcon#about to read 6, iclass 29, count 0 2006.286.02:06:48.97#ibcon#read 6, iclass 29, count 0 2006.286.02:06:48.97#ibcon#end of sib2, iclass 29, count 0 2006.286.02:06:48.97#ibcon#*mode == 0, iclass 29, count 0 2006.286.02:06:48.97#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.02:06:48.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.02:06:48.97#ibcon#*before write, iclass 29, count 0 2006.286.02:06:48.97#ibcon#enter sib2, iclass 29, count 0 2006.286.02:06:48.97#ibcon#flushed, iclass 29, count 0 2006.286.02:06:48.97#ibcon#about to write, iclass 29, count 0 2006.286.02:06:48.97#ibcon#wrote, iclass 29, count 0 2006.286.02:06:48.97#ibcon#about to read 3, iclass 29, count 0 2006.286.02:06:49.01#ibcon#read 3, iclass 29, count 0 2006.286.02:06:49.01#ibcon#about to read 4, iclass 29, count 0 2006.286.02:06:49.01#ibcon#read 4, iclass 29, count 0 2006.286.02:06:49.01#ibcon#about to read 5, iclass 29, count 0 2006.286.02:06:49.01#ibcon#read 5, iclass 29, count 0 2006.286.02:06:49.01#ibcon#about to read 6, iclass 29, count 0 2006.286.02:06:49.01#ibcon#read 6, iclass 29, count 0 2006.286.02:06:49.01#ibcon#end of sib2, iclass 29, count 0 2006.286.02:06:49.01#ibcon#*after write, iclass 29, count 0 2006.286.02:06:49.01#ibcon#*before return 0, iclass 29, count 0 2006.286.02:06:49.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:06:49.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:06:49.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.02:06:49.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.02:06:49.02$vck44/vb=3,4 2006.286.02:06:49.02#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.02:06:49.02#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.02:06:49.02#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:49.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:06:49.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:06:49.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:06:49.06#ibcon#enter wrdev, iclass 31, count 2 2006.286.02:06:49.06#ibcon#first serial, iclass 31, count 2 2006.286.02:06:49.06#ibcon#enter sib2, iclass 31, count 2 2006.286.02:06:49.06#ibcon#flushed, iclass 31, count 2 2006.286.02:06:49.06#ibcon#about to write, iclass 31, count 2 2006.286.02:06:49.06#ibcon#wrote, iclass 31, count 2 2006.286.02:06:49.06#ibcon#about to read 3, iclass 31, count 2 2006.286.02:06:49.08#ibcon#read 3, iclass 31, count 2 2006.286.02:06:49.08#ibcon#about to read 4, iclass 31, count 2 2006.286.02:06:49.08#ibcon#read 4, iclass 31, count 2 2006.286.02:06:49.08#ibcon#about to read 5, iclass 31, count 2 2006.286.02:06:49.08#ibcon#read 5, iclass 31, count 2 2006.286.02:06:49.08#ibcon#about to read 6, iclass 31, count 2 2006.286.02:06:49.08#ibcon#read 6, iclass 31, count 2 2006.286.02:06:49.08#ibcon#end of sib2, iclass 31, count 2 2006.286.02:06:49.08#ibcon#*mode == 0, iclass 31, count 2 2006.286.02:06:49.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.02:06:49.08#ibcon#[27=AT03-04\r\n] 2006.286.02:06:49.08#ibcon#*before write, iclass 31, count 2 2006.286.02:06:49.08#ibcon#enter sib2, iclass 31, count 2 2006.286.02:06:49.08#ibcon#flushed, iclass 31, count 2 2006.286.02:06:49.08#ibcon#about to write, iclass 31, count 2 2006.286.02:06:49.08#ibcon#wrote, iclass 31, count 2 2006.286.02:06:49.08#ibcon#about to read 3, iclass 31, count 2 2006.286.02:06:49.11#ibcon#read 3, iclass 31, count 2 2006.286.02:06:49.11#ibcon#about to read 4, iclass 31, count 2 2006.286.02:06:49.11#ibcon#read 4, iclass 31, count 2 2006.286.02:06:49.11#ibcon#about to read 5, iclass 31, count 2 2006.286.02:06:49.11#ibcon#read 5, iclass 31, count 2 2006.286.02:06:49.11#ibcon#about to read 6, iclass 31, count 2 2006.286.02:06:49.11#ibcon#read 6, iclass 31, count 2 2006.286.02:06:49.11#ibcon#end of sib2, iclass 31, count 2 2006.286.02:06:49.11#ibcon#*after write, iclass 31, count 2 2006.286.02:06:49.11#ibcon#*before return 0, iclass 31, count 2 2006.286.02:06:49.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:06:49.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:06:49.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.02:06:49.11#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:49.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:06:49.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:06:49.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:06:49.23#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:06:49.23#ibcon#first serial, iclass 31, count 0 2006.286.02:06:49.23#ibcon#enter sib2, iclass 31, count 0 2006.286.02:06:49.23#ibcon#flushed, iclass 31, count 0 2006.286.02:06:49.23#ibcon#about to write, iclass 31, count 0 2006.286.02:06:49.23#ibcon#wrote, iclass 31, count 0 2006.286.02:06:49.23#ibcon#about to read 3, iclass 31, count 0 2006.286.02:06:49.25#ibcon#read 3, iclass 31, count 0 2006.286.02:06:49.25#ibcon#about to read 4, iclass 31, count 0 2006.286.02:06:49.25#ibcon#read 4, iclass 31, count 0 2006.286.02:06:49.25#ibcon#about to read 5, iclass 31, count 0 2006.286.02:06:49.25#ibcon#read 5, iclass 31, count 0 2006.286.02:06:49.25#ibcon#about to read 6, iclass 31, count 0 2006.286.02:06:49.25#ibcon#read 6, iclass 31, count 0 2006.286.02:06:49.25#ibcon#end of sib2, iclass 31, count 0 2006.286.02:06:49.25#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:06:49.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:06:49.25#ibcon#[27=USB\r\n] 2006.286.02:06:49.25#ibcon#*before write, iclass 31, count 0 2006.286.02:06:49.25#ibcon#enter sib2, iclass 31, count 0 2006.286.02:06:49.25#ibcon#flushed, iclass 31, count 0 2006.286.02:06:49.25#ibcon#about to write, iclass 31, count 0 2006.286.02:06:49.25#ibcon#wrote, iclass 31, count 0 2006.286.02:06:49.25#ibcon#about to read 3, iclass 31, count 0 2006.286.02:06:49.28#ibcon#read 3, iclass 31, count 0 2006.286.02:06:49.28#ibcon#about to read 4, iclass 31, count 0 2006.286.02:06:49.28#ibcon#read 4, iclass 31, count 0 2006.286.02:06:49.28#ibcon#about to read 5, iclass 31, count 0 2006.286.02:06:49.28#ibcon#read 5, iclass 31, count 0 2006.286.02:06:49.28#ibcon#about to read 6, iclass 31, count 0 2006.286.02:06:49.28#ibcon#read 6, iclass 31, count 0 2006.286.02:06:49.28#ibcon#end of sib2, iclass 31, count 0 2006.286.02:06:49.28#ibcon#*after write, iclass 31, count 0 2006.286.02:06:49.28#ibcon#*before return 0, iclass 31, count 0 2006.286.02:06:49.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:06:49.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:06:49.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:06:49.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:06:49.29$vck44/vblo=4,679.99 2006.286.02:06:49.29#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.02:06:49.29#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.02:06:49.29#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:49.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:06:49.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:06:49.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:06:49.29#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:06:49.29#ibcon#first serial, iclass 33, count 0 2006.286.02:06:49.29#ibcon#enter sib2, iclass 33, count 0 2006.286.02:06:49.29#ibcon#flushed, iclass 33, count 0 2006.286.02:06:49.29#ibcon#about to write, iclass 33, count 0 2006.286.02:06:49.29#ibcon#wrote, iclass 33, count 0 2006.286.02:06:49.29#ibcon#about to read 3, iclass 33, count 0 2006.286.02:06:49.30#ibcon#read 3, iclass 33, count 0 2006.286.02:06:49.30#ibcon#about to read 4, iclass 33, count 0 2006.286.02:06:49.30#ibcon#read 4, iclass 33, count 0 2006.286.02:06:49.30#ibcon#about to read 5, iclass 33, count 0 2006.286.02:06:49.30#ibcon#read 5, iclass 33, count 0 2006.286.02:06:49.30#ibcon#about to read 6, iclass 33, count 0 2006.286.02:06:49.30#ibcon#read 6, iclass 33, count 0 2006.286.02:06:49.30#ibcon#end of sib2, iclass 33, count 0 2006.286.02:06:49.30#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:06:49.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:06:49.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.02:06:49.30#ibcon#*before write, iclass 33, count 0 2006.286.02:06:49.30#ibcon#enter sib2, iclass 33, count 0 2006.286.02:06:49.30#ibcon#flushed, iclass 33, count 0 2006.286.02:06:49.30#ibcon#about to write, iclass 33, count 0 2006.286.02:06:49.30#ibcon#wrote, iclass 33, count 0 2006.286.02:06:49.30#ibcon#about to read 3, iclass 33, count 0 2006.286.02:06:49.34#ibcon#read 3, iclass 33, count 0 2006.286.02:06:49.34#ibcon#about to read 4, iclass 33, count 0 2006.286.02:06:49.34#ibcon#read 4, iclass 33, count 0 2006.286.02:06:49.34#ibcon#about to read 5, iclass 33, count 0 2006.286.02:06:49.34#ibcon#read 5, iclass 33, count 0 2006.286.02:06:49.34#ibcon#about to read 6, iclass 33, count 0 2006.286.02:06:49.34#ibcon#read 6, iclass 33, count 0 2006.286.02:06:49.34#ibcon#end of sib2, iclass 33, count 0 2006.286.02:06:49.34#ibcon#*after write, iclass 33, count 0 2006.286.02:06:49.34#ibcon#*before return 0, iclass 33, count 0 2006.286.02:06:49.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:06:49.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:06:49.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:06:49.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:06:49.35$vck44/vb=4,5 2006.286.02:06:49.35#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.02:06:49.35#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.02:06:49.35#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:49.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:06:49.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:06:49.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:06:49.39#ibcon#enter wrdev, iclass 35, count 2 2006.286.02:06:49.39#ibcon#first serial, iclass 35, count 2 2006.286.02:06:49.39#ibcon#enter sib2, iclass 35, count 2 2006.286.02:06:49.39#ibcon#flushed, iclass 35, count 2 2006.286.02:06:49.39#ibcon#about to write, iclass 35, count 2 2006.286.02:06:49.39#ibcon#wrote, iclass 35, count 2 2006.286.02:06:49.39#ibcon#about to read 3, iclass 35, count 2 2006.286.02:06:49.41#ibcon#read 3, iclass 35, count 2 2006.286.02:06:49.41#ibcon#about to read 4, iclass 35, count 2 2006.286.02:06:49.41#ibcon#read 4, iclass 35, count 2 2006.286.02:06:49.41#ibcon#about to read 5, iclass 35, count 2 2006.286.02:06:49.41#ibcon#read 5, iclass 35, count 2 2006.286.02:06:49.41#ibcon#about to read 6, iclass 35, count 2 2006.286.02:06:49.41#ibcon#read 6, iclass 35, count 2 2006.286.02:06:49.41#ibcon#end of sib2, iclass 35, count 2 2006.286.02:06:49.41#ibcon#*mode == 0, iclass 35, count 2 2006.286.02:06:49.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.02:06:49.41#ibcon#[27=AT04-05\r\n] 2006.286.02:06:49.41#ibcon#*before write, iclass 35, count 2 2006.286.02:06:49.41#ibcon#enter sib2, iclass 35, count 2 2006.286.02:06:49.41#ibcon#flushed, iclass 35, count 2 2006.286.02:06:49.41#ibcon#about to write, iclass 35, count 2 2006.286.02:06:49.41#ibcon#wrote, iclass 35, count 2 2006.286.02:06:49.41#ibcon#about to read 3, iclass 35, count 2 2006.286.02:06:49.44#ibcon#read 3, iclass 35, count 2 2006.286.02:06:49.44#ibcon#about to read 4, iclass 35, count 2 2006.286.02:06:49.44#ibcon#read 4, iclass 35, count 2 2006.286.02:06:49.44#ibcon#about to read 5, iclass 35, count 2 2006.286.02:06:49.44#ibcon#read 5, iclass 35, count 2 2006.286.02:06:49.44#ibcon#about to read 6, iclass 35, count 2 2006.286.02:06:49.44#ibcon#read 6, iclass 35, count 2 2006.286.02:06:49.44#ibcon#end of sib2, iclass 35, count 2 2006.286.02:06:49.44#ibcon#*after write, iclass 35, count 2 2006.286.02:06:49.44#ibcon#*before return 0, iclass 35, count 2 2006.286.02:06:49.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:06:49.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:06:49.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.02:06:49.44#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:49.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:06:49.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:06:49.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:06:49.56#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:06:49.56#ibcon#first serial, iclass 35, count 0 2006.286.02:06:49.56#ibcon#enter sib2, iclass 35, count 0 2006.286.02:06:49.56#ibcon#flushed, iclass 35, count 0 2006.286.02:06:49.56#ibcon#about to write, iclass 35, count 0 2006.286.02:06:49.56#ibcon#wrote, iclass 35, count 0 2006.286.02:06:49.56#ibcon#about to read 3, iclass 35, count 0 2006.286.02:06:49.58#ibcon#read 3, iclass 35, count 0 2006.286.02:06:49.58#ibcon#about to read 4, iclass 35, count 0 2006.286.02:06:49.58#ibcon#read 4, iclass 35, count 0 2006.286.02:06:49.58#ibcon#about to read 5, iclass 35, count 0 2006.286.02:06:49.58#ibcon#read 5, iclass 35, count 0 2006.286.02:06:49.58#ibcon#about to read 6, iclass 35, count 0 2006.286.02:06:49.58#ibcon#read 6, iclass 35, count 0 2006.286.02:06:49.58#ibcon#end of sib2, iclass 35, count 0 2006.286.02:06:49.58#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:06:49.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:06:49.58#ibcon#[27=USB\r\n] 2006.286.02:06:49.58#ibcon#*before write, iclass 35, count 0 2006.286.02:06:49.58#ibcon#enter sib2, iclass 35, count 0 2006.286.02:06:49.58#ibcon#flushed, iclass 35, count 0 2006.286.02:06:49.58#ibcon#about to write, iclass 35, count 0 2006.286.02:06:49.58#ibcon#wrote, iclass 35, count 0 2006.286.02:06:49.58#ibcon#about to read 3, iclass 35, count 0 2006.286.02:06:49.61#ibcon#read 3, iclass 35, count 0 2006.286.02:06:49.61#ibcon#about to read 4, iclass 35, count 0 2006.286.02:06:49.61#ibcon#read 4, iclass 35, count 0 2006.286.02:06:49.61#ibcon#about to read 5, iclass 35, count 0 2006.286.02:06:49.61#ibcon#read 5, iclass 35, count 0 2006.286.02:06:49.61#ibcon#about to read 6, iclass 35, count 0 2006.286.02:06:49.61#ibcon#read 6, iclass 35, count 0 2006.286.02:06:49.61#ibcon#end of sib2, iclass 35, count 0 2006.286.02:06:49.61#ibcon#*after write, iclass 35, count 0 2006.286.02:06:49.61#ibcon#*before return 0, iclass 35, count 0 2006.286.02:06:49.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:06:49.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:06:49.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:06:49.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:06:49.62$vck44/vblo=5,709.99 2006.286.02:06:49.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.02:06:49.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.02:06:49.62#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:49.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:06:49.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:06:49.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:06:49.62#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:06:49.62#ibcon#first serial, iclass 37, count 0 2006.286.02:06:49.62#ibcon#enter sib2, iclass 37, count 0 2006.286.02:06:49.62#ibcon#flushed, iclass 37, count 0 2006.286.02:06:49.62#ibcon#about to write, iclass 37, count 0 2006.286.02:06:49.62#ibcon#wrote, iclass 37, count 0 2006.286.02:06:49.62#ibcon#about to read 3, iclass 37, count 0 2006.286.02:06:49.63#ibcon#read 3, iclass 37, count 0 2006.286.02:06:49.63#ibcon#about to read 4, iclass 37, count 0 2006.286.02:06:49.63#ibcon#read 4, iclass 37, count 0 2006.286.02:06:49.63#ibcon#about to read 5, iclass 37, count 0 2006.286.02:06:49.63#ibcon#read 5, iclass 37, count 0 2006.286.02:06:49.63#ibcon#about to read 6, iclass 37, count 0 2006.286.02:06:49.63#ibcon#read 6, iclass 37, count 0 2006.286.02:06:49.63#ibcon#end of sib2, iclass 37, count 0 2006.286.02:06:49.63#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:06:49.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:06:49.63#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.02:06:49.63#ibcon#*before write, iclass 37, count 0 2006.286.02:06:49.63#ibcon#enter sib2, iclass 37, count 0 2006.286.02:06:49.63#ibcon#flushed, iclass 37, count 0 2006.286.02:06:49.63#ibcon#about to write, iclass 37, count 0 2006.286.02:06:49.63#ibcon#wrote, iclass 37, count 0 2006.286.02:06:49.63#ibcon#about to read 3, iclass 37, count 0 2006.286.02:06:49.67#ibcon#read 3, iclass 37, count 0 2006.286.02:06:49.67#ibcon#about to read 4, iclass 37, count 0 2006.286.02:06:49.67#ibcon#read 4, iclass 37, count 0 2006.286.02:06:49.67#ibcon#about to read 5, iclass 37, count 0 2006.286.02:06:49.67#ibcon#read 5, iclass 37, count 0 2006.286.02:06:49.67#ibcon#about to read 6, iclass 37, count 0 2006.286.02:06:49.67#ibcon#read 6, iclass 37, count 0 2006.286.02:06:49.67#ibcon#end of sib2, iclass 37, count 0 2006.286.02:06:49.67#ibcon#*after write, iclass 37, count 0 2006.286.02:06:49.67#ibcon#*before return 0, iclass 37, count 0 2006.286.02:06:49.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:06:49.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:06:49.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:06:49.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:06:49.68$vck44/vb=5,4 2006.286.02:06:49.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.02:06:49.68#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.02:06:49.68#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:49.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:06:49.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:06:49.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:06:49.72#ibcon#enter wrdev, iclass 39, count 2 2006.286.02:06:49.72#ibcon#first serial, iclass 39, count 2 2006.286.02:06:49.72#ibcon#enter sib2, iclass 39, count 2 2006.286.02:06:49.72#ibcon#flushed, iclass 39, count 2 2006.286.02:06:49.72#ibcon#about to write, iclass 39, count 2 2006.286.02:06:49.72#ibcon#wrote, iclass 39, count 2 2006.286.02:06:49.72#ibcon#about to read 3, iclass 39, count 2 2006.286.02:06:49.74#ibcon#read 3, iclass 39, count 2 2006.286.02:06:49.74#ibcon#about to read 4, iclass 39, count 2 2006.286.02:06:49.74#ibcon#read 4, iclass 39, count 2 2006.286.02:06:49.74#ibcon#about to read 5, iclass 39, count 2 2006.286.02:06:49.74#ibcon#read 5, iclass 39, count 2 2006.286.02:06:49.74#ibcon#about to read 6, iclass 39, count 2 2006.286.02:06:49.74#ibcon#read 6, iclass 39, count 2 2006.286.02:06:49.74#ibcon#end of sib2, iclass 39, count 2 2006.286.02:06:49.74#ibcon#*mode == 0, iclass 39, count 2 2006.286.02:06:49.74#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.02:06:49.74#ibcon#[27=AT05-04\r\n] 2006.286.02:06:49.74#ibcon#*before write, iclass 39, count 2 2006.286.02:06:49.74#ibcon#enter sib2, iclass 39, count 2 2006.286.02:06:49.74#ibcon#flushed, iclass 39, count 2 2006.286.02:06:49.74#ibcon#about to write, iclass 39, count 2 2006.286.02:06:49.74#ibcon#wrote, iclass 39, count 2 2006.286.02:06:49.74#ibcon#about to read 3, iclass 39, count 2 2006.286.02:06:49.77#ibcon#read 3, iclass 39, count 2 2006.286.02:06:49.77#ibcon#about to read 4, iclass 39, count 2 2006.286.02:06:49.77#ibcon#read 4, iclass 39, count 2 2006.286.02:06:49.77#ibcon#about to read 5, iclass 39, count 2 2006.286.02:06:49.77#ibcon#read 5, iclass 39, count 2 2006.286.02:06:49.77#ibcon#about to read 6, iclass 39, count 2 2006.286.02:06:49.77#ibcon#read 6, iclass 39, count 2 2006.286.02:06:49.77#ibcon#end of sib2, iclass 39, count 2 2006.286.02:06:49.77#ibcon#*after write, iclass 39, count 2 2006.286.02:06:49.77#ibcon#*before return 0, iclass 39, count 2 2006.286.02:06:49.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:06:49.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:06:49.77#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.02:06:49.77#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:49.77#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:06:49.89#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:06:49.89#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:06:49.89#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:06:49.89#ibcon#first serial, iclass 39, count 0 2006.286.02:06:49.89#ibcon#enter sib2, iclass 39, count 0 2006.286.02:06:49.89#ibcon#flushed, iclass 39, count 0 2006.286.02:06:49.89#ibcon#about to write, iclass 39, count 0 2006.286.02:06:49.89#ibcon#wrote, iclass 39, count 0 2006.286.02:06:49.89#ibcon#about to read 3, iclass 39, count 0 2006.286.02:06:49.91#ibcon#read 3, iclass 39, count 0 2006.286.02:06:49.91#ibcon#about to read 4, iclass 39, count 0 2006.286.02:06:49.91#ibcon#read 4, iclass 39, count 0 2006.286.02:06:49.91#ibcon#about to read 5, iclass 39, count 0 2006.286.02:06:49.91#ibcon#read 5, iclass 39, count 0 2006.286.02:06:49.91#ibcon#about to read 6, iclass 39, count 0 2006.286.02:06:49.91#ibcon#read 6, iclass 39, count 0 2006.286.02:06:49.91#ibcon#end of sib2, iclass 39, count 0 2006.286.02:06:49.91#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:06:49.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:06:49.91#ibcon#[27=USB\r\n] 2006.286.02:06:49.91#ibcon#*before write, iclass 39, count 0 2006.286.02:06:49.91#ibcon#enter sib2, iclass 39, count 0 2006.286.02:06:49.91#ibcon#flushed, iclass 39, count 0 2006.286.02:06:49.91#ibcon#about to write, iclass 39, count 0 2006.286.02:06:49.91#ibcon#wrote, iclass 39, count 0 2006.286.02:06:49.91#ibcon#about to read 3, iclass 39, count 0 2006.286.02:06:49.94#ibcon#read 3, iclass 39, count 0 2006.286.02:06:49.94#ibcon#about to read 4, iclass 39, count 0 2006.286.02:06:49.94#ibcon#read 4, iclass 39, count 0 2006.286.02:06:49.94#ibcon#about to read 5, iclass 39, count 0 2006.286.02:06:49.94#ibcon#read 5, iclass 39, count 0 2006.286.02:06:49.94#ibcon#about to read 6, iclass 39, count 0 2006.286.02:06:49.94#ibcon#read 6, iclass 39, count 0 2006.286.02:06:49.94#ibcon#end of sib2, iclass 39, count 0 2006.286.02:06:49.94#ibcon#*after write, iclass 39, count 0 2006.286.02:06:49.94#ibcon#*before return 0, iclass 39, count 0 2006.286.02:06:49.94#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:06:49.94#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:06:49.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:06:49.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:06:49.95$vck44/vblo=6,719.99 2006.286.02:06:49.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.02:06:49.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.02:06:49.95#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:49.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:06:49.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:06:49.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:06:49.95#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:06:49.95#ibcon#first serial, iclass 3, count 0 2006.286.02:06:49.95#ibcon#enter sib2, iclass 3, count 0 2006.286.02:06:49.95#ibcon#flushed, iclass 3, count 0 2006.286.02:06:49.95#ibcon#about to write, iclass 3, count 0 2006.286.02:06:49.95#ibcon#wrote, iclass 3, count 0 2006.286.02:06:49.95#ibcon#about to read 3, iclass 3, count 0 2006.286.02:06:49.96#ibcon#read 3, iclass 3, count 0 2006.286.02:06:49.96#ibcon#about to read 4, iclass 3, count 0 2006.286.02:06:49.96#ibcon#read 4, iclass 3, count 0 2006.286.02:06:49.96#ibcon#about to read 5, iclass 3, count 0 2006.286.02:06:49.96#ibcon#read 5, iclass 3, count 0 2006.286.02:06:49.96#ibcon#about to read 6, iclass 3, count 0 2006.286.02:06:49.96#ibcon#read 6, iclass 3, count 0 2006.286.02:06:49.96#ibcon#end of sib2, iclass 3, count 0 2006.286.02:06:49.96#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:06:49.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:06:49.96#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.02:06:49.96#ibcon#*before write, iclass 3, count 0 2006.286.02:06:49.96#ibcon#enter sib2, iclass 3, count 0 2006.286.02:06:49.96#ibcon#flushed, iclass 3, count 0 2006.286.02:06:49.96#ibcon#about to write, iclass 3, count 0 2006.286.02:06:49.96#ibcon#wrote, iclass 3, count 0 2006.286.02:06:49.96#ibcon#about to read 3, iclass 3, count 0 2006.286.02:06:50.00#ibcon#read 3, iclass 3, count 0 2006.286.02:06:50.00#ibcon#about to read 4, iclass 3, count 0 2006.286.02:06:50.00#ibcon#read 4, iclass 3, count 0 2006.286.02:06:50.00#ibcon#about to read 5, iclass 3, count 0 2006.286.02:06:50.00#ibcon#read 5, iclass 3, count 0 2006.286.02:06:50.00#ibcon#about to read 6, iclass 3, count 0 2006.286.02:06:50.00#ibcon#read 6, iclass 3, count 0 2006.286.02:06:50.00#ibcon#end of sib2, iclass 3, count 0 2006.286.02:06:50.00#ibcon#*after write, iclass 3, count 0 2006.286.02:06:50.00#ibcon#*before return 0, iclass 3, count 0 2006.286.02:06:50.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:06:50.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:06:50.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:06:50.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:06:50.01$vck44/vb=6,3 2006.286.02:06:50.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.02:06:50.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.02:06:50.01#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:50.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:06:50.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:06:50.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:06:50.05#ibcon#enter wrdev, iclass 5, count 2 2006.286.02:06:50.05#ibcon#first serial, iclass 5, count 2 2006.286.02:06:50.05#ibcon#enter sib2, iclass 5, count 2 2006.286.02:06:50.05#ibcon#flushed, iclass 5, count 2 2006.286.02:06:50.05#ibcon#about to write, iclass 5, count 2 2006.286.02:06:50.05#ibcon#wrote, iclass 5, count 2 2006.286.02:06:50.05#ibcon#about to read 3, iclass 5, count 2 2006.286.02:06:50.07#ibcon#read 3, iclass 5, count 2 2006.286.02:06:50.07#ibcon#about to read 4, iclass 5, count 2 2006.286.02:06:50.07#ibcon#read 4, iclass 5, count 2 2006.286.02:06:50.07#ibcon#about to read 5, iclass 5, count 2 2006.286.02:06:50.07#ibcon#read 5, iclass 5, count 2 2006.286.02:06:50.07#ibcon#about to read 6, iclass 5, count 2 2006.286.02:06:50.07#ibcon#read 6, iclass 5, count 2 2006.286.02:06:50.07#ibcon#end of sib2, iclass 5, count 2 2006.286.02:06:50.07#ibcon#*mode == 0, iclass 5, count 2 2006.286.02:06:50.07#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.02:06:50.07#ibcon#[27=AT06-03\r\n] 2006.286.02:06:50.07#ibcon#*before write, iclass 5, count 2 2006.286.02:06:50.07#ibcon#enter sib2, iclass 5, count 2 2006.286.02:06:50.07#ibcon#flushed, iclass 5, count 2 2006.286.02:06:50.07#ibcon#about to write, iclass 5, count 2 2006.286.02:06:50.07#ibcon#wrote, iclass 5, count 2 2006.286.02:06:50.07#ibcon#about to read 3, iclass 5, count 2 2006.286.02:06:50.10#ibcon#read 3, iclass 5, count 2 2006.286.02:06:50.10#ibcon#about to read 4, iclass 5, count 2 2006.286.02:06:50.10#ibcon#read 4, iclass 5, count 2 2006.286.02:06:50.10#ibcon#about to read 5, iclass 5, count 2 2006.286.02:06:50.10#ibcon#read 5, iclass 5, count 2 2006.286.02:06:50.10#ibcon#about to read 6, iclass 5, count 2 2006.286.02:06:50.10#ibcon#read 6, iclass 5, count 2 2006.286.02:06:50.10#ibcon#end of sib2, iclass 5, count 2 2006.286.02:06:50.10#ibcon#*after write, iclass 5, count 2 2006.286.02:06:50.10#ibcon#*before return 0, iclass 5, count 2 2006.286.02:06:50.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:06:50.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:06:50.10#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.02:06:50.10#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:50.10#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:06:50.22#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:06:50.22#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:06:50.22#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:06:50.22#ibcon#first serial, iclass 5, count 0 2006.286.02:06:50.22#ibcon#enter sib2, iclass 5, count 0 2006.286.02:06:50.22#ibcon#flushed, iclass 5, count 0 2006.286.02:06:50.22#ibcon#about to write, iclass 5, count 0 2006.286.02:06:50.22#ibcon#wrote, iclass 5, count 0 2006.286.02:06:50.22#ibcon#about to read 3, iclass 5, count 0 2006.286.02:06:50.24#ibcon#read 3, iclass 5, count 0 2006.286.02:06:50.24#ibcon#about to read 4, iclass 5, count 0 2006.286.02:06:50.24#ibcon#read 4, iclass 5, count 0 2006.286.02:06:50.24#ibcon#about to read 5, iclass 5, count 0 2006.286.02:06:50.24#ibcon#read 5, iclass 5, count 0 2006.286.02:06:50.24#ibcon#about to read 6, iclass 5, count 0 2006.286.02:06:50.24#ibcon#read 6, iclass 5, count 0 2006.286.02:06:50.24#ibcon#end of sib2, iclass 5, count 0 2006.286.02:06:50.24#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:06:50.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:06:50.24#ibcon#[27=USB\r\n] 2006.286.02:06:50.24#ibcon#*before write, iclass 5, count 0 2006.286.02:06:50.24#ibcon#enter sib2, iclass 5, count 0 2006.286.02:06:50.24#ibcon#flushed, iclass 5, count 0 2006.286.02:06:50.24#ibcon#about to write, iclass 5, count 0 2006.286.02:06:50.24#ibcon#wrote, iclass 5, count 0 2006.286.02:06:50.24#ibcon#about to read 3, iclass 5, count 0 2006.286.02:06:50.27#ibcon#read 3, iclass 5, count 0 2006.286.02:06:50.27#ibcon#about to read 4, iclass 5, count 0 2006.286.02:06:50.27#ibcon#read 4, iclass 5, count 0 2006.286.02:06:50.27#ibcon#about to read 5, iclass 5, count 0 2006.286.02:06:50.27#ibcon#read 5, iclass 5, count 0 2006.286.02:06:50.27#ibcon#about to read 6, iclass 5, count 0 2006.286.02:06:50.27#ibcon#read 6, iclass 5, count 0 2006.286.02:06:50.27#ibcon#end of sib2, iclass 5, count 0 2006.286.02:06:50.27#ibcon#*after write, iclass 5, count 0 2006.286.02:06:50.27#ibcon#*before return 0, iclass 5, count 0 2006.286.02:06:50.27#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:06:50.27#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:06:50.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:06:50.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:06:50.28$vck44/vblo=7,734.99 2006.286.02:06:50.28#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.02:06:50.28#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.02:06:50.28#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:50.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:06:50.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:06:50.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:06:50.28#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:06:50.28#ibcon#first serial, iclass 7, count 0 2006.286.02:06:50.28#ibcon#enter sib2, iclass 7, count 0 2006.286.02:06:50.28#ibcon#flushed, iclass 7, count 0 2006.286.02:06:50.28#ibcon#about to write, iclass 7, count 0 2006.286.02:06:50.28#ibcon#wrote, iclass 7, count 0 2006.286.02:06:50.28#ibcon#about to read 3, iclass 7, count 0 2006.286.02:06:50.29#ibcon#read 3, iclass 7, count 0 2006.286.02:06:50.29#ibcon#about to read 4, iclass 7, count 0 2006.286.02:06:50.29#ibcon#read 4, iclass 7, count 0 2006.286.02:06:50.29#ibcon#about to read 5, iclass 7, count 0 2006.286.02:06:50.29#ibcon#read 5, iclass 7, count 0 2006.286.02:06:50.29#ibcon#about to read 6, iclass 7, count 0 2006.286.02:06:50.29#ibcon#read 6, iclass 7, count 0 2006.286.02:06:50.29#ibcon#end of sib2, iclass 7, count 0 2006.286.02:06:50.29#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:06:50.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:06:50.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.02:06:50.29#ibcon#*before write, iclass 7, count 0 2006.286.02:06:50.29#ibcon#enter sib2, iclass 7, count 0 2006.286.02:06:50.29#ibcon#flushed, iclass 7, count 0 2006.286.02:06:50.29#ibcon#about to write, iclass 7, count 0 2006.286.02:06:50.29#ibcon#wrote, iclass 7, count 0 2006.286.02:06:50.29#ibcon#about to read 3, iclass 7, count 0 2006.286.02:06:50.33#ibcon#read 3, iclass 7, count 0 2006.286.02:06:50.33#ibcon#about to read 4, iclass 7, count 0 2006.286.02:06:50.33#ibcon#read 4, iclass 7, count 0 2006.286.02:06:50.33#ibcon#about to read 5, iclass 7, count 0 2006.286.02:06:50.33#ibcon#read 5, iclass 7, count 0 2006.286.02:06:50.33#ibcon#about to read 6, iclass 7, count 0 2006.286.02:06:50.33#ibcon#read 6, iclass 7, count 0 2006.286.02:06:50.33#ibcon#end of sib2, iclass 7, count 0 2006.286.02:06:50.33#ibcon#*after write, iclass 7, count 0 2006.286.02:06:50.33#ibcon#*before return 0, iclass 7, count 0 2006.286.02:06:50.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:06:50.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:06:50.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:06:50.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:06:50.34$vck44/vb=7,4 2006.286.02:06:50.34#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.02:06:50.34#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.02:06:50.34#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:50.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:06:50.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:06:50.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:06:50.38#ibcon#enter wrdev, iclass 11, count 2 2006.286.02:06:50.38#ibcon#first serial, iclass 11, count 2 2006.286.02:06:50.38#ibcon#enter sib2, iclass 11, count 2 2006.286.02:06:50.38#ibcon#flushed, iclass 11, count 2 2006.286.02:06:50.38#ibcon#about to write, iclass 11, count 2 2006.286.02:06:50.38#ibcon#wrote, iclass 11, count 2 2006.286.02:06:50.38#ibcon#about to read 3, iclass 11, count 2 2006.286.02:06:50.40#ibcon#read 3, iclass 11, count 2 2006.286.02:06:50.40#ibcon#about to read 4, iclass 11, count 2 2006.286.02:06:50.40#ibcon#read 4, iclass 11, count 2 2006.286.02:06:50.40#ibcon#about to read 5, iclass 11, count 2 2006.286.02:06:50.40#ibcon#read 5, iclass 11, count 2 2006.286.02:06:50.40#ibcon#about to read 6, iclass 11, count 2 2006.286.02:06:50.40#ibcon#read 6, iclass 11, count 2 2006.286.02:06:50.40#ibcon#end of sib2, iclass 11, count 2 2006.286.02:06:50.40#ibcon#*mode == 0, iclass 11, count 2 2006.286.02:06:50.40#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.02:06:50.40#ibcon#[27=AT07-04\r\n] 2006.286.02:06:50.40#ibcon#*before write, iclass 11, count 2 2006.286.02:06:50.40#ibcon#enter sib2, iclass 11, count 2 2006.286.02:06:50.40#ibcon#flushed, iclass 11, count 2 2006.286.02:06:50.40#ibcon#about to write, iclass 11, count 2 2006.286.02:06:50.40#ibcon#wrote, iclass 11, count 2 2006.286.02:06:50.40#ibcon#about to read 3, iclass 11, count 2 2006.286.02:06:50.43#ibcon#read 3, iclass 11, count 2 2006.286.02:06:50.43#ibcon#about to read 4, iclass 11, count 2 2006.286.02:06:50.43#ibcon#read 4, iclass 11, count 2 2006.286.02:06:50.43#ibcon#about to read 5, iclass 11, count 2 2006.286.02:06:50.43#ibcon#read 5, iclass 11, count 2 2006.286.02:06:50.43#ibcon#about to read 6, iclass 11, count 2 2006.286.02:06:50.43#ibcon#read 6, iclass 11, count 2 2006.286.02:06:50.43#ibcon#end of sib2, iclass 11, count 2 2006.286.02:06:50.43#ibcon#*after write, iclass 11, count 2 2006.286.02:06:50.43#ibcon#*before return 0, iclass 11, count 2 2006.286.02:06:50.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:06:50.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:06:50.43#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.02:06:50.43#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:50.43#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:06:50.55#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:06:50.55#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:06:50.55#ibcon#enter wrdev, iclass 11, count 0 2006.286.02:06:50.55#ibcon#first serial, iclass 11, count 0 2006.286.02:06:50.55#ibcon#enter sib2, iclass 11, count 0 2006.286.02:06:50.55#ibcon#flushed, iclass 11, count 0 2006.286.02:06:50.55#ibcon#about to write, iclass 11, count 0 2006.286.02:06:50.55#ibcon#wrote, iclass 11, count 0 2006.286.02:06:50.55#ibcon#about to read 3, iclass 11, count 0 2006.286.02:06:50.57#ibcon#read 3, iclass 11, count 0 2006.286.02:06:50.57#ibcon#about to read 4, iclass 11, count 0 2006.286.02:06:50.57#ibcon#read 4, iclass 11, count 0 2006.286.02:06:50.57#ibcon#about to read 5, iclass 11, count 0 2006.286.02:06:50.57#ibcon#read 5, iclass 11, count 0 2006.286.02:06:50.57#ibcon#about to read 6, iclass 11, count 0 2006.286.02:06:50.57#ibcon#read 6, iclass 11, count 0 2006.286.02:06:50.57#ibcon#end of sib2, iclass 11, count 0 2006.286.02:06:50.57#ibcon#*mode == 0, iclass 11, count 0 2006.286.02:06:50.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.02:06:50.57#ibcon#[27=USB\r\n] 2006.286.02:06:50.57#ibcon#*before write, iclass 11, count 0 2006.286.02:06:50.57#ibcon#enter sib2, iclass 11, count 0 2006.286.02:06:50.57#ibcon#flushed, iclass 11, count 0 2006.286.02:06:50.57#ibcon#about to write, iclass 11, count 0 2006.286.02:06:50.57#ibcon#wrote, iclass 11, count 0 2006.286.02:06:50.57#ibcon#about to read 3, iclass 11, count 0 2006.286.02:06:50.60#ibcon#read 3, iclass 11, count 0 2006.286.02:06:50.60#ibcon#about to read 4, iclass 11, count 0 2006.286.02:06:50.60#ibcon#read 4, iclass 11, count 0 2006.286.02:06:50.60#ibcon#about to read 5, iclass 11, count 0 2006.286.02:06:50.60#ibcon#read 5, iclass 11, count 0 2006.286.02:06:50.60#ibcon#about to read 6, iclass 11, count 0 2006.286.02:06:50.60#ibcon#read 6, iclass 11, count 0 2006.286.02:06:50.60#ibcon#end of sib2, iclass 11, count 0 2006.286.02:06:50.60#ibcon#*after write, iclass 11, count 0 2006.286.02:06:50.60#ibcon#*before return 0, iclass 11, count 0 2006.286.02:06:50.60#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:06:50.60#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:06:50.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.02:06:50.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.02:06:50.61$vck44/vblo=8,744.99 2006.286.02:06:50.61#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.02:06:50.61#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.02:06:50.61#ibcon#ireg 17 cls_cnt 0 2006.286.02:06:50.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:06:50.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:06:50.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:06:50.61#ibcon#enter wrdev, iclass 13, count 0 2006.286.02:06:50.61#ibcon#first serial, iclass 13, count 0 2006.286.02:06:50.61#ibcon#enter sib2, iclass 13, count 0 2006.286.02:06:50.61#ibcon#flushed, iclass 13, count 0 2006.286.02:06:50.61#ibcon#about to write, iclass 13, count 0 2006.286.02:06:50.61#ibcon#wrote, iclass 13, count 0 2006.286.02:06:50.61#ibcon#about to read 3, iclass 13, count 0 2006.286.02:06:50.62#ibcon#read 3, iclass 13, count 0 2006.286.02:06:50.62#ibcon#about to read 4, iclass 13, count 0 2006.286.02:06:50.62#ibcon#read 4, iclass 13, count 0 2006.286.02:06:50.62#ibcon#about to read 5, iclass 13, count 0 2006.286.02:06:50.62#ibcon#read 5, iclass 13, count 0 2006.286.02:06:50.62#ibcon#about to read 6, iclass 13, count 0 2006.286.02:06:50.62#ibcon#read 6, iclass 13, count 0 2006.286.02:06:50.62#ibcon#end of sib2, iclass 13, count 0 2006.286.02:06:50.62#ibcon#*mode == 0, iclass 13, count 0 2006.286.02:06:50.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.02:06:50.62#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.02:06:50.62#ibcon#*before write, iclass 13, count 0 2006.286.02:06:50.62#ibcon#enter sib2, iclass 13, count 0 2006.286.02:06:50.62#ibcon#flushed, iclass 13, count 0 2006.286.02:06:50.62#ibcon#about to write, iclass 13, count 0 2006.286.02:06:50.62#ibcon#wrote, iclass 13, count 0 2006.286.02:06:50.62#ibcon#about to read 3, iclass 13, count 0 2006.286.02:06:50.66#ibcon#read 3, iclass 13, count 0 2006.286.02:06:50.66#ibcon#about to read 4, iclass 13, count 0 2006.286.02:06:50.66#ibcon#read 4, iclass 13, count 0 2006.286.02:06:50.66#ibcon#about to read 5, iclass 13, count 0 2006.286.02:06:50.66#ibcon#read 5, iclass 13, count 0 2006.286.02:06:50.66#ibcon#about to read 6, iclass 13, count 0 2006.286.02:06:50.66#ibcon#read 6, iclass 13, count 0 2006.286.02:06:50.66#ibcon#end of sib2, iclass 13, count 0 2006.286.02:06:50.66#ibcon#*after write, iclass 13, count 0 2006.286.02:06:50.66#ibcon#*before return 0, iclass 13, count 0 2006.286.02:06:50.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:06:50.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:06:50.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.02:06:50.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.02:06:50.67$vck44/vb=8,4 2006.286.02:06:50.67#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.02:06:50.67#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.02:06:50.67#ibcon#ireg 11 cls_cnt 2 2006.286.02:06:50.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:06:50.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:06:50.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:06:50.71#ibcon#enter wrdev, iclass 15, count 2 2006.286.02:06:50.71#ibcon#first serial, iclass 15, count 2 2006.286.02:06:50.71#ibcon#enter sib2, iclass 15, count 2 2006.286.02:06:50.71#ibcon#flushed, iclass 15, count 2 2006.286.02:06:50.71#ibcon#about to write, iclass 15, count 2 2006.286.02:06:50.71#ibcon#wrote, iclass 15, count 2 2006.286.02:06:50.71#ibcon#about to read 3, iclass 15, count 2 2006.286.02:06:50.73#ibcon#read 3, iclass 15, count 2 2006.286.02:06:50.73#ibcon#about to read 4, iclass 15, count 2 2006.286.02:06:50.73#ibcon#read 4, iclass 15, count 2 2006.286.02:06:50.73#ibcon#about to read 5, iclass 15, count 2 2006.286.02:06:50.73#ibcon#read 5, iclass 15, count 2 2006.286.02:06:50.73#ibcon#about to read 6, iclass 15, count 2 2006.286.02:06:50.73#ibcon#read 6, iclass 15, count 2 2006.286.02:06:50.73#ibcon#end of sib2, iclass 15, count 2 2006.286.02:06:50.73#ibcon#*mode == 0, iclass 15, count 2 2006.286.02:06:50.73#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.02:06:50.73#ibcon#[27=AT08-04\r\n] 2006.286.02:06:50.73#ibcon#*before write, iclass 15, count 2 2006.286.02:06:50.73#ibcon#enter sib2, iclass 15, count 2 2006.286.02:06:50.73#ibcon#flushed, iclass 15, count 2 2006.286.02:06:50.73#ibcon#about to write, iclass 15, count 2 2006.286.02:06:50.73#ibcon#wrote, iclass 15, count 2 2006.286.02:06:50.73#ibcon#about to read 3, iclass 15, count 2 2006.286.02:06:50.76#ibcon#read 3, iclass 15, count 2 2006.286.02:06:50.76#ibcon#about to read 4, iclass 15, count 2 2006.286.02:06:50.76#ibcon#read 4, iclass 15, count 2 2006.286.02:06:50.76#ibcon#about to read 5, iclass 15, count 2 2006.286.02:06:50.76#ibcon#read 5, iclass 15, count 2 2006.286.02:06:50.76#ibcon#about to read 6, iclass 15, count 2 2006.286.02:06:50.76#ibcon#read 6, iclass 15, count 2 2006.286.02:06:50.76#ibcon#end of sib2, iclass 15, count 2 2006.286.02:06:50.76#ibcon#*after write, iclass 15, count 2 2006.286.02:06:50.76#ibcon#*before return 0, iclass 15, count 2 2006.286.02:06:50.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:06:50.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:06:50.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.02:06:50.76#ibcon#ireg 7 cls_cnt 0 2006.286.02:06:50.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:06:50.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:06:50.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:06:50.88#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:06:50.88#ibcon#first serial, iclass 15, count 0 2006.286.02:06:50.88#ibcon#enter sib2, iclass 15, count 0 2006.286.02:06:50.88#ibcon#flushed, iclass 15, count 0 2006.286.02:06:50.88#ibcon#about to write, iclass 15, count 0 2006.286.02:06:50.88#ibcon#wrote, iclass 15, count 0 2006.286.02:06:50.88#ibcon#about to read 3, iclass 15, count 0 2006.286.02:06:50.90#ibcon#read 3, iclass 15, count 0 2006.286.02:06:50.90#ibcon#about to read 4, iclass 15, count 0 2006.286.02:06:50.90#ibcon#read 4, iclass 15, count 0 2006.286.02:06:50.90#ibcon#about to read 5, iclass 15, count 0 2006.286.02:06:50.90#ibcon#read 5, iclass 15, count 0 2006.286.02:06:50.90#ibcon#about to read 6, iclass 15, count 0 2006.286.02:06:50.90#ibcon#read 6, iclass 15, count 0 2006.286.02:06:50.90#ibcon#end of sib2, iclass 15, count 0 2006.286.02:06:50.90#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:06:50.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:06:50.90#ibcon#[27=USB\r\n] 2006.286.02:06:50.90#ibcon#*before write, iclass 15, count 0 2006.286.02:06:50.90#ibcon#enter sib2, iclass 15, count 0 2006.286.02:06:50.90#ibcon#flushed, iclass 15, count 0 2006.286.02:06:50.90#ibcon#about to write, iclass 15, count 0 2006.286.02:06:50.90#ibcon#wrote, iclass 15, count 0 2006.286.02:06:50.90#ibcon#about to read 3, iclass 15, count 0 2006.286.02:06:50.93#ibcon#read 3, iclass 15, count 0 2006.286.02:06:50.93#ibcon#about to read 4, iclass 15, count 0 2006.286.02:06:50.93#ibcon#read 4, iclass 15, count 0 2006.286.02:06:50.93#ibcon#about to read 5, iclass 15, count 0 2006.286.02:06:50.93#ibcon#read 5, iclass 15, count 0 2006.286.02:06:50.93#ibcon#about to read 6, iclass 15, count 0 2006.286.02:06:50.93#ibcon#read 6, iclass 15, count 0 2006.286.02:06:50.93#ibcon#end of sib2, iclass 15, count 0 2006.286.02:06:50.93#ibcon#*after write, iclass 15, count 0 2006.286.02:06:50.93#ibcon#*before return 0, iclass 15, count 0 2006.286.02:06:50.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:06:50.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:06:50.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:06:50.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:06:50.94$vck44/vabw=wide 2006.286.02:06:50.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.02:06:50.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.02:06:50.94#ibcon#ireg 8 cls_cnt 0 2006.286.02:06:50.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:06:50.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:06:50.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:06:50.94#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:06:50.94#ibcon#first serial, iclass 17, count 0 2006.286.02:06:50.94#ibcon#enter sib2, iclass 17, count 0 2006.286.02:06:50.94#ibcon#flushed, iclass 17, count 0 2006.286.02:06:50.94#ibcon#about to write, iclass 17, count 0 2006.286.02:06:50.94#ibcon#wrote, iclass 17, count 0 2006.286.02:06:50.94#ibcon#about to read 3, iclass 17, count 0 2006.286.02:06:50.95#ibcon#read 3, iclass 17, count 0 2006.286.02:06:50.95#ibcon#about to read 4, iclass 17, count 0 2006.286.02:06:50.95#ibcon#read 4, iclass 17, count 0 2006.286.02:06:50.95#ibcon#about to read 5, iclass 17, count 0 2006.286.02:06:50.95#ibcon#read 5, iclass 17, count 0 2006.286.02:06:50.95#ibcon#about to read 6, iclass 17, count 0 2006.286.02:06:50.95#ibcon#read 6, iclass 17, count 0 2006.286.02:06:50.95#ibcon#end of sib2, iclass 17, count 0 2006.286.02:06:50.95#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:06:50.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:06:50.95#ibcon#[25=BW32\r\n] 2006.286.02:06:50.95#ibcon#*before write, iclass 17, count 0 2006.286.02:06:50.95#ibcon#enter sib2, iclass 17, count 0 2006.286.02:06:50.95#ibcon#flushed, iclass 17, count 0 2006.286.02:06:50.95#ibcon#about to write, iclass 17, count 0 2006.286.02:06:50.95#ibcon#wrote, iclass 17, count 0 2006.286.02:06:50.95#ibcon#about to read 3, iclass 17, count 0 2006.286.02:06:50.98#ibcon#read 3, iclass 17, count 0 2006.286.02:06:50.98#ibcon#about to read 4, iclass 17, count 0 2006.286.02:06:50.98#ibcon#read 4, iclass 17, count 0 2006.286.02:06:50.98#ibcon#about to read 5, iclass 17, count 0 2006.286.02:06:50.98#ibcon#read 5, iclass 17, count 0 2006.286.02:06:50.98#ibcon#about to read 6, iclass 17, count 0 2006.286.02:06:50.98#ibcon#read 6, iclass 17, count 0 2006.286.02:06:50.98#ibcon#end of sib2, iclass 17, count 0 2006.286.02:06:50.98#ibcon#*after write, iclass 17, count 0 2006.286.02:06:50.98#ibcon#*before return 0, iclass 17, count 0 2006.286.02:06:50.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:06:50.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:06:50.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:06:50.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:06:50.99$vck44/vbbw=wide 2006.286.02:06:50.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.02:06:50.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.02:06:50.99#ibcon#ireg 8 cls_cnt 0 2006.286.02:06:50.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:06:51.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:06:51.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:06:51.04#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:06:51.04#ibcon#first serial, iclass 19, count 0 2006.286.02:06:51.04#ibcon#enter sib2, iclass 19, count 0 2006.286.02:06:51.04#ibcon#flushed, iclass 19, count 0 2006.286.02:06:51.04#ibcon#about to write, iclass 19, count 0 2006.286.02:06:51.04#ibcon#wrote, iclass 19, count 0 2006.286.02:06:51.04#ibcon#about to read 3, iclass 19, count 0 2006.286.02:06:51.06#ibcon#read 3, iclass 19, count 0 2006.286.02:06:51.06#ibcon#about to read 4, iclass 19, count 0 2006.286.02:06:51.06#ibcon#read 4, iclass 19, count 0 2006.286.02:06:51.06#ibcon#about to read 5, iclass 19, count 0 2006.286.02:06:51.06#ibcon#read 5, iclass 19, count 0 2006.286.02:06:51.06#ibcon#about to read 6, iclass 19, count 0 2006.286.02:06:51.06#ibcon#read 6, iclass 19, count 0 2006.286.02:06:51.06#ibcon#end of sib2, iclass 19, count 0 2006.286.02:06:51.06#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:06:51.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:06:51.06#ibcon#[27=BW32\r\n] 2006.286.02:06:51.06#ibcon#*before write, iclass 19, count 0 2006.286.02:06:51.06#ibcon#enter sib2, iclass 19, count 0 2006.286.02:06:51.06#ibcon#flushed, iclass 19, count 0 2006.286.02:06:51.06#ibcon#about to write, iclass 19, count 0 2006.286.02:06:51.06#ibcon#wrote, iclass 19, count 0 2006.286.02:06:51.06#ibcon#about to read 3, iclass 19, count 0 2006.286.02:06:51.09#ibcon#read 3, iclass 19, count 0 2006.286.02:06:51.09#ibcon#about to read 4, iclass 19, count 0 2006.286.02:06:51.09#ibcon#read 4, iclass 19, count 0 2006.286.02:06:51.09#ibcon#about to read 5, iclass 19, count 0 2006.286.02:06:51.09#ibcon#read 5, iclass 19, count 0 2006.286.02:06:51.09#ibcon#about to read 6, iclass 19, count 0 2006.286.02:06:51.09#ibcon#read 6, iclass 19, count 0 2006.286.02:06:51.09#ibcon#end of sib2, iclass 19, count 0 2006.286.02:06:51.09#ibcon#*after write, iclass 19, count 0 2006.286.02:06:51.09#ibcon#*before return 0, iclass 19, count 0 2006.286.02:06:51.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:06:51.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:06:51.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:06:51.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:06:51.10$setupk4/ifdk4 2006.286.02:06:51.10$ifdk4/lo= 2006.286.02:06:51.10$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.02:06:51.10$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.02:06:51.10$ifdk4/patch= 2006.286.02:06:51.10$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.02:06:51.10$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.02:06:51.10$setupk4/!*+20s 2006.286.02:06:57.88#abcon#<5=/03 3.3 5.9 21.28 811016.0\r\n> 2006.286.02:06:57.90#abcon#{5=INTERFACE CLEAR} 2006.286.02:06:57.96#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:07:05.75$setupk4/"tpicd 2006.286.02:07:05.75$setupk4/echo=off 2006.286.02:07:05.75$setupk4/xlog=off 2006.286.02:07:05.75:!2006.286.02:17:13 2006.286.02:07:40.13#trakl#Source acquired 2006.286.02:07:40.13#flagr#flagr/antenna,acquired 2006.286.02:17:13.00:preob 2006.286.02:17:14.14/onsource/TRACKING 2006.286.02:17:14.14:!2006.286.02:17:23 2006.286.02:17:23.00:"tape 2006.286.02:17:23.00:"st=record 2006.286.02:17:23.00:data_valid=on 2006.286.02:17:23.00:midob 2006.286.02:17:23.14/onsource/TRACKING 2006.286.02:17:23.14/wx/21.36,1015.9,81 2006.286.02:17:23.22/cable/+6.5007E-03 2006.286.02:17:24.31/va/01,07,usb,yes,34,37 2006.286.02:17:24.31/va/02,06,usb,yes,35,35 2006.286.02:17:24.31/va/03,07,usb,yes,34,36 2006.286.02:17:24.31/va/04,06,usb,yes,36,37 2006.286.02:17:24.31/va/05,03,usb,yes,35,35 2006.286.02:17:24.31/va/06,04,usb,yes,32,31 2006.286.02:17:24.31/va/07,04,usb,yes,32,33 2006.286.02:17:24.31/va/08,03,usb,yes,33,40 2006.286.02:17:24.54/valo/01,524.99,yes,locked 2006.286.02:17:24.54/valo/02,534.99,yes,locked 2006.286.02:17:24.54/valo/03,564.99,yes,locked 2006.286.02:17:24.54/valo/04,624.99,yes,locked 2006.286.02:17:24.54/valo/05,734.99,yes,locked 2006.286.02:17:24.54/valo/06,814.99,yes,locked 2006.286.02:17:24.54/valo/07,864.99,yes,locked 2006.286.02:17:24.54/valo/08,884.99,yes,locked 2006.286.02:17:25.63/vb/01,04,usb,yes,38,35 2006.286.02:17:25.63/vb/02,05,usb,yes,36,35 2006.286.02:17:25.63/vb/03,04,usb,yes,37,41 2006.286.02:17:25.63/vb/04,05,usb,yes,37,36 2006.286.02:17:25.63/vb/05,04,usb,yes,33,36 2006.286.02:17:25.63/vb/06,03,usb,yes,46,41 2006.286.02:17:25.63/vb/07,04,usb,yes,37,38 2006.286.02:17:25.63/vb/08,04,usb,yes,34,38 2006.286.02:17:25.87/vblo/01,629.99,yes,locked 2006.286.02:17:25.87/vblo/02,634.99,yes,locked 2006.286.02:17:25.87/vblo/03,649.99,yes,locked 2006.286.02:17:25.87/vblo/04,679.99,yes,locked 2006.286.02:17:25.87/vblo/05,709.99,yes,locked 2006.286.02:17:25.87/vblo/06,719.99,yes,locked 2006.286.02:17:25.87/vblo/07,734.99,yes,locked 2006.286.02:17:25.87/vblo/08,744.99,yes,locked 2006.286.02:17:26.02/vabw/8 2006.286.02:17:26.17/vbbw/8 2006.286.02:17:26.26/xfe/off,on,12.0 2006.286.02:17:26.63/ifatt/23,28,28,28 2006.286.02:17:27.07/fmout-gps/S +2.81E-07 2006.286.02:17:27.09:!2006.286.02:18:43 2006.286.02:18:43.00:data_valid=off 2006.286.02:18:43.00:"et 2006.286.02:18:43.00:!+3s 2006.286.02:18:46.01:"tape 2006.286.02:18:46.01:postob 2006.286.02:18:46.07/cable/+6.4988E-03 2006.286.02:18:46.07/wx/21.37,1015.9,80 2006.286.02:18:47.07/fmout-gps/S +2.78E-07 2006.286.02:18:47.07:scan_name=286-0222,jd0610,40 2006.286.02:18:47.07:source=1424-418,142756.30,-420619.4,2000.0,ccw 2006.286.02:18:48.14#flagr#flagr/antenna,new-source 2006.286.02:18:48.14:checkk5 2006.286.02:18:48.74/chk_autoobs//k5ts1/ autoobs is running! 2006.286.02:18:49.37/chk_autoobs//k5ts2/ autoobs is running! 2006.286.02:18:49.78/chk_autoobs//k5ts3/ autoobs is running! 2006.286.02:18:50.17/chk_autoobs//k5ts4/ autoobs is running! 2006.286.02:18:50.70/chk_obsdata//k5ts1/T2860217??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.02:18:51.09/chk_obsdata//k5ts2/T2860217??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.02:18:51.50/chk_obsdata//k5ts3/T2860217??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.02:18:51.92/chk_obsdata//k5ts4/T2860217??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.02:18:52.71/k5log//k5ts1_log_newline 2006.286.02:18:53.45/k5log//k5ts2_log_newline 2006.286.02:18:54.18/k5log//k5ts3_log_newline 2006.286.02:18:55.41/k5log//k5ts4_log_newline 2006.286.02:18:55.43/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.02:18:55.43:setupk4=1 2006.286.02:18:55.43$setupk4/echo=on 2006.286.02:18:55.43$setupk4/pcalon 2006.286.02:18:55.43$pcalon/"no phase cal control is implemented here 2006.286.02:18:55.43$setupk4/"tpicd=stop 2006.286.02:18:55.43$setupk4/"rec=synch_on 2006.286.02:18:55.43$setupk4/"rec_mode=128 2006.286.02:18:55.43$setupk4/!* 2006.286.02:18:55.43$setupk4/recpk4 2006.286.02:18:55.43$recpk4/recpatch= 2006.286.02:18:55.43$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.02:18:55.44$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.02:18:55.44$setupk4/vck44 2006.286.02:18:55.44$vck44/valo=1,524.99 2006.286.02:18:55.44#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.02:18:55.44#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.02:18:55.44#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:55.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:18:55.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:18:55.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:18:55.44#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:18:55.44#ibcon#first serial, iclass 15, count 0 2006.286.02:18:55.44#ibcon#enter sib2, iclass 15, count 0 2006.286.02:18:55.44#ibcon#flushed, iclass 15, count 0 2006.286.02:18:55.44#ibcon#about to write, iclass 15, count 0 2006.286.02:18:55.44#ibcon#wrote, iclass 15, count 0 2006.286.02:18:55.44#ibcon#about to read 3, iclass 15, count 0 2006.286.02:18:55.45#ibcon#read 3, iclass 15, count 0 2006.286.02:18:55.45#ibcon#about to read 4, iclass 15, count 0 2006.286.02:18:55.45#ibcon#read 4, iclass 15, count 0 2006.286.02:18:55.45#ibcon#about to read 5, iclass 15, count 0 2006.286.02:18:55.45#ibcon#read 5, iclass 15, count 0 2006.286.02:18:55.45#ibcon#about to read 6, iclass 15, count 0 2006.286.02:18:55.45#ibcon#read 6, iclass 15, count 0 2006.286.02:18:55.45#ibcon#end of sib2, iclass 15, count 0 2006.286.02:18:55.45#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:18:55.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:18:55.45#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.02:18:55.45#ibcon#*before write, iclass 15, count 0 2006.286.02:18:55.45#ibcon#enter sib2, iclass 15, count 0 2006.286.02:18:55.45#ibcon#flushed, iclass 15, count 0 2006.286.02:18:55.45#ibcon#about to write, iclass 15, count 0 2006.286.02:18:55.45#ibcon#wrote, iclass 15, count 0 2006.286.02:18:55.45#ibcon#about to read 3, iclass 15, count 0 2006.286.02:18:55.50#ibcon#read 3, iclass 15, count 0 2006.286.02:18:55.50#ibcon#about to read 4, iclass 15, count 0 2006.286.02:18:55.50#ibcon#read 4, iclass 15, count 0 2006.286.02:18:55.50#ibcon#about to read 5, iclass 15, count 0 2006.286.02:18:55.50#ibcon#read 5, iclass 15, count 0 2006.286.02:18:55.50#ibcon#about to read 6, iclass 15, count 0 2006.286.02:18:55.50#ibcon#read 6, iclass 15, count 0 2006.286.02:18:55.50#ibcon#end of sib2, iclass 15, count 0 2006.286.02:18:55.50#ibcon#*after write, iclass 15, count 0 2006.286.02:18:55.50#ibcon#*before return 0, iclass 15, count 0 2006.286.02:18:55.50#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:18:55.50#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:18:55.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:18:55.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:18:55.50$vck44/va=1,7 2006.286.02:18:55.50#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.02:18:55.50#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.02:18:55.50#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:55.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:18:55.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:18:55.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:18:55.50#ibcon#enter wrdev, iclass 17, count 2 2006.286.02:18:55.50#ibcon#first serial, iclass 17, count 2 2006.286.02:18:55.50#ibcon#enter sib2, iclass 17, count 2 2006.286.02:18:55.50#ibcon#flushed, iclass 17, count 2 2006.286.02:18:55.50#ibcon#about to write, iclass 17, count 2 2006.286.02:18:55.50#ibcon#wrote, iclass 17, count 2 2006.286.02:18:55.50#ibcon#about to read 3, iclass 17, count 2 2006.286.02:18:55.52#ibcon#read 3, iclass 17, count 2 2006.286.02:18:55.52#ibcon#about to read 4, iclass 17, count 2 2006.286.02:18:55.52#ibcon#read 4, iclass 17, count 2 2006.286.02:18:55.52#ibcon#about to read 5, iclass 17, count 2 2006.286.02:18:55.52#ibcon#read 5, iclass 17, count 2 2006.286.02:18:55.52#ibcon#about to read 6, iclass 17, count 2 2006.286.02:18:55.52#ibcon#read 6, iclass 17, count 2 2006.286.02:18:55.52#ibcon#end of sib2, iclass 17, count 2 2006.286.02:18:55.52#ibcon#*mode == 0, iclass 17, count 2 2006.286.02:18:55.52#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.02:18:55.52#ibcon#[25=AT01-07\r\n] 2006.286.02:18:55.52#ibcon#*before write, iclass 17, count 2 2006.286.02:18:55.52#ibcon#enter sib2, iclass 17, count 2 2006.286.02:18:55.52#ibcon#flushed, iclass 17, count 2 2006.286.02:18:55.52#ibcon#about to write, iclass 17, count 2 2006.286.02:18:55.52#ibcon#wrote, iclass 17, count 2 2006.286.02:18:55.52#ibcon#about to read 3, iclass 17, count 2 2006.286.02:18:55.55#ibcon#read 3, iclass 17, count 2 2006.286.02:18:55.55#ibcon#about to read 4, iclass 17, count 2 2006.286.02:18:55.55#ibcon#read 4, iclass 17, count 2 2006.286.02:18:55.55#ibcon#about to read 5, iclass 17, count 2 2006.286.02:18:55.55#ibcon#read 5, iclass 17, count 2 2006.286.02:18:55.55#ibcon#about to read 6, iclass 17, count 2 2006.286.02:18:55.55#ibcon#read 6, iclass 17, count 2 2006.286.02:18:55.55#ibcon#end of sib2, iclass 17, count 2 2006.286.02:18:55.55#ibcon#*after write, iclass 17, count 2 2006.286.02:18:55.55#ibcon#*before return 0, iclass 17, count 2 2006.286.02:18:55.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:18:55.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:18:55.55#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.02:18:55.55#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:55.55#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:18:55.67#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:18:55.67#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:18:55.67#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:18:55.67#ibcon#first serial, iclass 17, count 0 2006.286.02:18:55.67#ibcon#enter sib2, iclass 17, count 0 2006.286.02:18:55.67#ibcon#flushed, iclass 17, count 0 2006.286.02:18:55.67#ibcon#about to write, iclass 17, count 0 2006.286.02:18:55.67#ibcon#wrote, iclass 17, count 0 2006.286.02:18:55.67#ibcon#about to read 3, iclass 17, count 0 2006.286.02:18:55.69#ibcon#read 3, iclass 17, count 0 2006.286.02:18:55.69#ibcon#about to read 4, iclass 17, count 0 2006.286.02:18:55.69#ibcon#read 4, iclass 17, count 0 2006.286.02:18:55.69#ibcon#about to read 5, iclass 17, count 0 2006.286.02:18:55.69#ibcon#read 5, iclass 17, count 0 2006.286.02:18:55.69#ibcon#about to read 6, iclass 17, count 0 2006.286.02:18:55.69#ibcon#read 6, iclass 17, count 0 2006.286.02:18:55.69#ibcon#end of sib2, iclass 17, count 0 2006.286.02:18:55.69#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:18:55.69#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:18:55.69#ibcon#[25=USB\r\n] 2006.286.02:18:55.69#ibcon#*before write, iclass 17, count 0 2006.286.02:18:55.69#ibcon#enter sib2, iclass 17, count 0 2006.286.02:18:55.69#ibcon#flushed, iclass 17, count 0 2006.286.02:18:55.69#ibcon#about to write, iclass 17, count 0 2006.286.02:18:55.69#ibcon#wrote, iclass 17, count 0 2006.286.02:18:55.69#ibcon#about to read 3, iclass 17, count 0 2006.286.02:18:55.72#ibcon#read 3, iclass 17, count 0 2006.286.02:18:55.72#ibcon#about to read 4, iclass 17, count 0 2006.286.02:18:55.72#ibcon#read 4, iclass 17, count 0 2006.286.02:18:55.72#ibcon#about to read 5, iclass 17, count 0 2006.286.02:18:55.72#ibcon#read 5, iclass 17, count 0 2006.286.02:18:55.72#ibcon#about to read 6, iclass 17, count 0 2006.286.02:18:55.72#ibcon#read 6, iclass 17, count 0 2006.286.02:18:55.72#ibcon#end of sib2, iclass 17, count 0 2006.286.02:18:55.72#ibcon#*after write, iclass 17, count 0 2006.286.02:18:55.72#ibcon#*before return 0, iclass 17, count 0 2006.286.02:18:55.72#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:18:55.72#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:18:55.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:18:55.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:18:55.72$vck44/valo=2,534.99 2006.286.02:18:55.72#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.02:18:55.72#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.02:18:55.72#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:55.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:18:55.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:18:55.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:18:55.72#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:18:55.72#ibcon#first serial, iclass 19, count 0 2006.286.02:18:55.72#ibcon#enter sib2, iclass 19, count 0 2006.286.02:18:55.72#ibcon#flushed, iclass 19, count 0 2006.286.02:18:55.72#ibcon#about to write, iclass 19, count 0 2006.286.02:18:55.72#ibcon#wrote, iclass 19, count 0 2006.286.02:18:55.72#ibcon#about to read 3, iclass 19, count 0 2006.286.02:18:55.74#ibcon#read 3, iclass 19, count 0 2006.286.02:18:55.74#ibcon#about to read 4, iclass 19, count 0 2006.286.02:18:55.74#ibcon#read 4, iclass 19, count 0 2006.286.02:18:55.74#ibcon#about to read 5, iclass 19, count 0 2006.286.02:18:55.74#ibcon#read 5, iclass 19, count 0 2006.286.02:18:55.74#ibcon#about to read 6, iclass 19, count 0 2006.286.02:18:55.74#ibcon#read 6, iclass 19, count 0 2006.286.02:18:55.74#ibcon#end of sib2, iclass 19, count 0 2006.286.02:18:55.74#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:18:55.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:18:55.74#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.02:18:55.74#ibcon#*before write, iclass 19, count 0 2006.286.02:18:55.74#ibcon#enter sib2, iclass 19, count 0 2006.286.02:18:55.74#ibcon#flushed, iclass 19, count 0 2006.286.02:18:55.74#ibcon#about to write, iclass 19, count 0 2006.286.02:18:55.74#ibcon#wrote, iclass 19, count 0 2006.286.02:18:55.74#ibcon#about to read 3, iclass 19, count 0 2006.286.02:18:55.78#ibcon#read 3, iclass 19, count 0 2006.286.02:18:55.78#ibcon#about to read 4, iclass 19, count 0 2006.286.02:18:55.78#ibcon#read 4, iclass 19, count 0 2006.286.02:18:55.78#ibcon#about to read 5, iclass 19, count 0 2006.286.02:18:55.78#ibcon#read 5, iclass 19, count 0 2006.286.02:18:55.78#ibcon#about to read 6, iclass 19, count 0 2006.286.02:18:55.78#ibcon#read 6, iclass 19, count 0 2006.286.02:18:55.78#ibcon#end of sib2, iclass 19, count 0 2006.286.02:18:55.78#ibcon#*after write, iclass 19, count 0 2006.286.02:18:55.78#ibcon#*before return 0, iclass 19, count 0 2006.286.02:18:55.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:18:55.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:18:55.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:18:55.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:18:55.78$vck44/va=2,6 2006.286.02:18:55.78#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.02:18:55.78#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.02:18:55.78#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:55.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:18:55.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:18:55.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:18:55.84#ibcon#enter wrdev, iclass 21, count 2 2006.286.02:18:55.84#ibcon#first serial, iclass 21, count 2 2006.286.02:18:55.84#ibcon#enter sib2, iclass 21, count 2 2006.286.02:18:55.84#ibcon#flushed, iclass 21, count 2 2006.286.02:18:55.84#ibcon#about to write, iclass 21, count 2 2006.286.02:18:55.84#ibcon#wrote, iclass 21, count 2 2006.286.02:18:55.84#ibcon#about to read 3, iclass 21, count 2 2006.286.02:18:55.86#ibcon#read 3, iclass 21, count 2 2006.286.02:18:55.86#ibcon#about to read 4, iclass 21, count 2 2006.286.02:18:55.86#ibcon#read 4, iclass 21, count 2 2006.286.02:18:55.86#ibcon#about to read 5, iclass 21, count 2 2006.286.02:18:55.86#ibcon#read 5, iclass 21, count 2 2006.286.02:18:55.86#ibcon#about to read 6, iclass 21, count 2 2006.286.02:18:55.86#ibcon#read 6, iclass 21, count 2 2006.286.02:18:55.86#ibcon#end of sib2, iclass 21, count 2 2006.286.02:18:55.86#ibcon#*mode == 0, iclass 21, count 2 2006.286.02:18:55.86#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.02:18:55.86#ibcon#[25=AT02-06\r\n] 2006.286.02:18:55.86#ibcon#*before write, iclass 21, count 2 2006.286.02:18:55.86#ibcon#enter sib2, iclass 21, count 2 2006.286.02:18:55.86#ibcon#flushed, iclass 21, count 2 2006.286.02:18:55.86#ibcon#about to write, iclass 21, count 2 2006.286.02:18:55.86#ibcon#wrote, iclass 21, count 2 2006.286.02:18:55.86#ibcon#about to read 3, iclass 21, count 2 2006.286.02:18:55.89#ibcon#read 3, iclass 21, count 2 2006.286.02:18:55.89#ibcon#about to read 4, iclass 21, count 2 2006.286.02:18:55.89#ibcon#read 4, iclass 21, count 2 2006.286.02:18:55.89#ibcon#about to read 5, iclass 21, count 2 2006.286.02:18:55.89#ibcon#read 5, iclass 21, count 2 2006.286.02:18:55.89#ibcon#about to read 6, iclass 21, count 2 2006.286.02:18:55.89#ibcon#read 6, iclass 21, count 2 2006.286.02:18:55.89#ibcon#end of sib2, iclass 21, count 2 2006.286.02:18:55.89#ibcon#*after write, iclass 21, count 2 2006.286.02:18:55.89#ibcon#*before return 0, iclass 21, count 2 2006.286.02:18:55.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:18:55.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:18:55.89#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.02:18:55.89#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:55.89#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:18:56.01#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:18:56.01#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:18:56.01#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:18:56.01#ibcon#first serial, iclass 21, count 0 2006.286.02:18:56.01#ibcon#enter sib2, iclass 21, count 0 2006.286.02:18:56.01#ibcon#flushed, iclass 21, count 0 2006.286.02:18:56.01#ibcon#about to write, iclass 21, count 0 2006.286.02:18:56.01#ibcon#wrote, iclass 21, count 0 2006.286.02:18:56.01#ibcon#about to read 3, iclass 21, count 0 2006.286.02:18:56.03#ibcon#read 3, iclass 21, count 0 2006.286.02:18:56.03#ibcon#about to read 4, iclass 21, count 0 2006.286.02:18:56.03#ibcon#read 4, iclass 21, count 0 2006.286.02:18:56.03#ibcon#about to read 5, iclass 21, count 0 2006.286.02:18:56.03#ibcon#read 5, iclass 21, count 0 2006.286.02:18:56.03#ibcon#about to read 6, iclass 21, count 0 2006.286.02:18:56.03#ibcon#read 6, iclass 21, count 0 2006.286.02:18:56.03#ibcon#end of sib2, iclass 21, count 0 2006.286.02:18:56.03#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:18:56.03#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:18:56.03#ibcon#[25=USB\r\n] 2006.286.02:18:56.03#ibcon#*before write, iclass 21, count 0 2006.286.02:18:56.03#ibcon#enter sib2, iclass 21, count 0 2006.286.02:18:56.03#ibcon#flushed, iclass 21, count 0 2006.286.02:18:56.03#ibcon#about to write, iclass 21, count 0 2006.286.02:18:56.03#ibcon#wrote, iclass 21, count 0 2006.286.02:18:56.03#ibcon#about to read 3, iclass 21, count 0 2006.286.02:18:56.06#ibcon#read 3, iclass 21, count 0 2006.286.02:18:56.06#ibcon#about to read 4, iclass 21, count 0 2006.286.02:18:56.06#ibcon#read 4, iclass 21, count 0 2006.286.02:18:56.06#ibcon#about to read 5, iclass 21, count 0 2006.286.02:18:56.06#ibcon#read 5, iclass 21, count 0 2006.286.02:18:56.06#ibcon#about to read 6, iclass 21, count 0 2006.286.02:18:56.06#ibcon#read 6, iclass 21, count 0 2006.286.02:18:56.06#ibcon#end of sib2, iclass 21, count 0 2006.286.02:18:56.06#ibcon#*after write, iclass 21, count 0 2006.286.02:18:56.06#ibcon#*before return 0, iclass 21, count 0 2006.286.02:18:56.06#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:18:56.06#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:18:56.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:18:56.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:18:56.06$vck44/valo=3,564.99 2006.286.02:18:56.06#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.02:18:56.06#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.02:18:56.06#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:56.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:18:56.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:18:56.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:18:56.06#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:18:56.06#ibcon#first serial, iclass 23, count 0 2006.286.02:18:56.06#ibcon#enter sib2, iclass 23, count 0 2006.286.02:18:56.06#ibcon#flushed, iclass 23, count 0 2006.286.02:18:56.06#ibcon#about to write, iclass 23, count 0 2006.286.02:18:56.06#ibcon#wrote, iclass 23, count 0 2006.286.02:18:56.06#ibcon#about to read 3, iclass 23, count 0 2006.286.02:18:56.08#ibcon#read 3, iclass 23, count 0 2006.286.02:18:56.08#ibcon#about to read 4, iclass 23, count 0 2006.286.02:18:56.08#ibcon#read 4, iclass 23, count 0 2006.286.02:18:56.08#ibcon#about to read 5, iclass 23, count 0 2006.286.02:18:56.08#ibcon#read 5, iclass 23, count 0 2006.286.02:18:56.08#ibcon#about to read 6, iclass 23, count 0 2006.286.02:18:56.08#ibcon#read 6, iclass 23, count 0 2006.286.02:18:56.08#ibcon#end of sib2, iclass 23, count 0 2006.286.02:18:56.08#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:18:56.08#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:18:56.08#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.02:18:56.08#ibcon#*before write, iclass 23, count 0 2006.286.02:18:56.08#ibcon#enter sib2, iclass 23, count 0 2006.286.02:18:56.08#ibcon#flushed, iclass 23, count 0 2006.286.02:18:56.08#ibcon#about to write, iclass 23, count 0 2006.286.02:18:56.08#ibcon#wrote, iclass 23, count 0 2006.286.02:18:56.08#ibcon#about to read 3, iclass 23, count 0 2006.286.02:18:56.12#ibcon#read 3, iclass 23, count 0 2006.286.02:18:56.12#ibcon#about to read 4, iclass 23, count 0 2006.286.02:18:56.12#ibcon#read 4, iclass 23, count 0 2006.286.02:18:56.12#ibcon#about to read 5, iclass 23, count 0 2006.286.02:18:56.12#ibcon#read 5, iclass 23, count 0 2006.286.02:18:56.12#ibcon#about to read 6, iclass 23, count 0 2006.286.02:18:56.12#ibcon#read 6, iclass 23, count 0 2006.286.02:18:56.12#ibcon#end of sib2, iclass 23, count 0 2006.286.02:18:56.12#ibcon#*after write, iclass 23, count 0 2006.286.02:18:56.12#ibcon#*before return 0, iclass 23, count 0 2006.286.02:18:56.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:18:56.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:18:56.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:18:56.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:18:56.12$vck44/va=3,7 2006.286.02:18:56.12#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.02:18:56.12#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.02:18:56.12#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:56.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:18:56.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:18:56.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:18:56.18#ibcon#enter wrdev, iclass 25, count 2 2006.286.02:18:56.18#ibcon#first serial, iclass 25, count 2 2006.286.02:18:56.18#ibcon#enter sib2, iclass 25, count 2 2006.286.02:18:56.18#ibcon#flushed, iclass 25, count 2 2006.286.02:18:56.18#ibcon#about to write, iclass 25, count 2 2006.286.02:18:56.18#ibcon#wrote, iclass 25, count 2 2006.286.02:18:56.18#ibcon#about to read 3, iclass 25, count 2 2006.286.02:18:56.20#ibcon#read 3, iclass 25, count 2 2006.286.02:18:56.20#ibcon#about to read 4, iclass 25, count 2 2006.286.02:18:56.20#ibcon#read 4, iclass 25, count 2 2006.286.02:18:56.20#ibcon#about to read 5, iclass 25, count 2 2006.286.02:18:56.20#ibcon#read 5, iclass 25, count 2 2006.286.02:18:56.20#ibcon#about to read 6, iclass 25, count 2 2006.286.02:18:56.20#ibcon#read 6, iclass 25, count 2 2006.286.02:18:56.20#ibcon#end of sib2, iclass 25, count 2 2006.286.02:18:56.20#ibcon#*mode == 0, iclass 25, count 2 2006.286.02:18:56.20#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.02:18:56.20#ibcon#[25=AT03-07\r\n] 2006.286.02:18:56.20#ibcon#*before write, iclass 25, count 2 2006.286.02:18:56.20#ibcon#enter sib2, iclass 25, count 2 2006.286.02:18:56.20#ibcon#flushed, iclass 25, count 2 2006.286.02:18:56.20#ibcon#about to write, iclass 25, count 2 2006.286.02:18:56.20#ibcon#wrote, iclass 25, count 2 2006.286.02:18:56.20#ibcon#about to read 3, iclass 25, count 2 2006.286.02:18:56.23#ibcon#read 3, iclass 25, count 2 2006.286.02:18:56.23#ibcon#about to read 4, iclass 25, count 2 2006.286.02:18:56.23#ibcon#read 4, iclass 25, count 2 2006.286.02:18:56.23#ibcon#about to read 5, iclass 25, count 2 2006.286.02:18:56.23#ibcon#read 5, iclass 25, count 2 2006.286.02:18:56.23#ibcon#about to read 6, iclass 25, count 2 2006.286.02:18:56.23#ibcon#read 6, iclass 25, count 2 2006.286.02:18:56.23#ibcon#end of sib2, iclass 25, count 2 2006.286.02:18:56.23#ibcon#*after write, iclass 25, count 2 2006.286.02:18:56.23#ibcon#*before return 0, iclass 25, count 2 2006.286.02:18:56.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:18:56.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:18:56.23#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.02:18:56.23#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:56.23#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:18:56.35#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:18:56.35#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:18:56.35#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:18:56.35#ibcon#first serial, iclass 25, count 0 2006.286.02:18:56.35#ibcon#enter sib2, iclass 25, count 0 2006.286.02:18:56.35#ibcon#flushed, iclass 25, count 0 2006.286.02:18:56.35#ibcon#about to write, iclass 25, count 0 2006.286.02:18:56.35#ibcon#wrote, iclass 25, count 0 2006.286.02:18:56.35#ibcon#about to read 3, iclass 25, count 0 2006.286.02:18:56.37#ibcon#read 3, iclass 25, count 0 2006.286.02:18:56.37#ibcon#about to read 4, iclass 25, count 0 2006.286.02:18:56.37#ibcon#read 4, iclass 25, count 0 2006.286.02:18:56.37#ibcon#about to read 5, iclass 25, count 0 2006.286.02:18:56.37#ibcon#read 5, iclass 25, count 0 2006.286.02:18:56.37#ibcon#about to read 6, iclass 25, count 0 2006.286.02:18:56.37#ibcon#read 6, iclass 25, count 0 2006.286.02:18:56.37#ibcon#end of sib2, iclass 25, count 0 2006.286.02:18:56.37#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:18:56.37#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:18:56.37#ibcon#[25=USB\r\n] 2006.286.02:18:56.37#ibcon#*before write, iclass 25, count 0 2006.286.02:18:56.37#ibcon#enter sib2, iclass 25, count 0 2006.286.02:18:56.37#ibcon#flushed, iclass 25, count 0 2006.286.02:18:56.37#ibcon#about to write, iclass 25, count 0 2006.286.02:18:56.37#ibcon#wrote, iclass 25, count 0 2006.286.02:18:56.37#ibcon#about to read 3, iclass 25, count 0 2006.286.02:18:56.40#ibcon#read 3, iclass 25, count 0 2006.286.02:18:56.40#ibcon#about to read 4, iclass 25, count 0 2006.286.02:18:56.40#ibcon#read 4, iclass 25, count 0 2006.286.02:18:56.40#ibcon#about to read 5, iclass 25, count 0 2006.286.02:18:56.40#ibcon#read 5, iclass 25, count 0 2006.286.02:18:56.40#ibcon#about to read 6, iclass 25, count 0 2006.286.02:18:56.40#ibcon#read 6, iclass 25, count 0 2006.286.02:18:56.40#ibcon#end of sib2, iclass 25, count 0 2006.286.02:18:56.40#ibcon#*after write, iclass 25, count 0 2006.286.02:18:56.40#ibcon#*before return 0, iclass 25, count 0 2006.286.02:18:56.40#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:18:56.40#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:18:56.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:18:56.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:18:56.40$vck44/valo=4,624.99 2006.286.02:18:56.40#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.02:18:56.40#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.02:18:56.40#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:56.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:18:56.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:18:56.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:18:56.40#ibcon#enter wrdev, iclass 27, count 0 2006.286.02:18:56.40#ibcon#first serial, iclass 27, count 0 2006.286.02:18:56.40#ibcon#enter sib2, iclass 27, count 0 2006.286.02:18:56.40#ibcon#flushed, iclass 27, count 0 2006.286.02:18:56.40#ibcon#about to write, iclass 27, count 0 2006.286.02:18:56.40#ibcon#wrote, iclass 27, count 0 2006.286.02:18:56.40#ibcon#about to read 3, iclass 27, count 0 2006.286.02:18:56.42#ibcon#read 3, iclass 27, count 0 2006.286.02:18:56.42#ibcon#about to read 4, iclass 27, count 0 2006.286.02:18:56.42#ibcon#read 4, iclass 27, count 0 2006.286.02:18:56.42#ibcon#about to read 5, iclass 27, count 0 2006.286.02:18:56.42#ibcon#read 5, iclass 27, count 0 2006.286.02:18:56.42#ibcon#about to read 6, iclass 27, count 0 2006.286.02:18:56.42#ibcon#read 6, iclass 27, count 0 2006.286.02:18:56.42#ibcon#end of sib2, iclass 27, count 0 2006.286.02:18:56.42#ibcon#*mode == 0, iclass 27, count 0 2006.286.02:18:56.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.02:18:56.42#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.02:18:56.42#ibcon#*before write, iclass 27, count 0 2006.286.02:18:56.42#ibcon#enter sib2, iclass 27, count 0 2006.286.02:18:56.42#ibcon#flushed, iclass 27, count 0 2006.286.02:18:56.42#ibcon#about to write, iclass 27, count 0 2006.286.02:18:56.42#ibcon#wrote, iclass 27, count 0 2006.286.02:18:56.42#ibcon#about to read 3, iclass 27, count 0 2006.286.02:18:56.46#ibcon#read 3, iclass 27, count 0 2006.286.02:18:56.46#ibcon#about to read 4, iclass 27, count 0 2006.286.02:18:56.46#ibcon#read 4, iclass 27, count 0 2006.286.02:18:56.46#ibcon#about to read 5, iclass 27, count 0 2006.286.02:18:56.46#ibcon#read 5, iclass 27, count 0 2006.286.02:18:56.46#ibcon#about to read 6, iclass 27, count 0 2006.286.02:18:56.46#ibcon#read 6, iclass 27, count 0 2006.286.02:18:56.46#ibcon#end of sib2, iclass 27, count 0 2006.286.02:18:56.46#ibcon#*after write, iclass 27, count 0 2006.286.02:18:56.46#ibcon#*before return 0, iclass 27, count 0 2006.286.02:18:56.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:18:56.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:18:56.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.02:18:56.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.02:18:56.46$vck44/va=4,6 2006.286.02:18:56.46#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.02:18:56.46#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.02:18:56.46#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:56.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:18:56.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:18:56.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:18:56.52#ibcon#enter wrdev, iclass 29, count 2 2006.286.02:18:56.52#ibcon#first serial, iclass 29, count 2 2006.286.02:18:56.52#ibcon#enter sib2, iclass 29, count 2 2006.286.02:18:56.52#ibcon#flushed, iclass 29, count 2 2006.286.02:18:56.52#ibcon#about to write, iclass 29, count 2 2006.286.02:18:56.52#ibcon#wrote, iclass 29, count 2 2006.286.02:18:56.52#ibcon#about to read 3, iclass 29, count 2 2006.286.02:18:56.54#ibcon#read 3, iclass 29, count 2 2006.286.02:18:56.54#ibcon#about to read 4, iclass 29, count 2 2006.286.02:18:56.54#ibcon#read 4, iclass 29, count 2 2006.286.02:18:56.54#ibcon#about to read 5, iclass 29, count 2 2006.286.02:18:56.54#ibcon#read 5, iclass 29, count 2 2006.286.02:18:56.54#ibcon#about to read 6, iclass 29, count 2 2006.286.02:18:56.54#ibcon#read 6, iclass 29, count 2 2006.286.02:18:56.54#ibcon#end of sib2, iclass 29, count 2 2006.286.02:18:56.54#ibcon#*mode == 0, iclass 29, count 2 2006.286.02:18:56.54#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.02:18:56.54#ibcon#[25=AT04-06\r\n] 2006.286.02:18:56.54#ibcon#*before write, iclass 29, count 2 2006.286.02:18:56.54#ibcon#enter sib2, iclass 29, count 2 2006.286.02:18:56.54#ibcon#flushed, iclass 29, count 2 2006.286.02:18:56.54#ibcon#about to write, iclass 29, count 2 2006.286.02:18:56.54#ibcon#wrote, iclass 29, count 2 2006.286.02:18:56.54#ibcon#about to read 3, iclass 29, count 2 2006.286.02:18:56.57#ibcon#read 3, iclass 29, count 2 2006.286.02:18:56.57#ibcon#about to read 4, iclass 29, count 2 2006.286.02:18:56.57#ibcon#read 4, iclass 29, count 2 2006.286.02:18:56.57#ibcon#about to read 5, iclass 29, count 2 2006.286.02:18:56.57#ibcon#read 5, iclass 29, count 2 2006.286.02:18:56.57#ibcon#about to read 6, iclass 29, count 2 2006.286.02:18:56.57#ibcon#read 6, iclass 29, count 2 2006.286.02:18:56.57#ibcon#end of sib2, iclass 29, count 2 2006.286.02:18:56.57#ibcon#*after write, iclass 29, count 2 2006.286.02:18:56.57#ibcon#*before return 0, iclass 29, count 2 2006.286.02:18:56.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:18:56.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:18:56.57#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.02:18:56.57#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:56.57#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:18:56.69#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:18:56.69#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:18:56.69#ibcon#enter wrdev, iclass 29, count 0 2006.286.02:18:56.69#ibcon#first serial, iclass 29, count 0 2006.286.02:18:56.69#ibcon#enter sib2, iclass 29, count 0 2006.286.02:18:56.69#ibcon#flushed, iclass 29, count 0 2006.286.02:18:56.69#ibcon#about to write, iclass 29, count 0 2006.286.02:18:56.69#ibcon#wrote, iclass 29, count 0 2006.286.02:18:56.69#ibcon#about to read 3, iclass 29, count 0 2006.286.02:18:56.71#ibcon#read 3, iclass 29, count 0 2006.286.02:18:56.71#ibcon#about to read 4, iclass 29, count 0 2006.286.02:18:56.71#ibcon#read 4, iclass 29, count 0 2006.286.02:18:56.71#ibcon#about to read 5, iclass 29, count 0 2006.286.02:18:56.71#ibcon#read 5, iclass 29, count 0 2006.286.02:18:56.71#ibcon#about to read 6, iclass 29, count 0 2006.286.02:18:56.71#ibcon#read 6, iclass 29, count 0 2006.286.02:18:56.71#ibcon#end of sib2, iclass 29, count 0 2006.286.02:18:56.71#ibcon#*mode == 0, iclass 29, count 0 2006.286.02:18:56.71#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.02:18:56.71#ibcon#[25=USB\r\n] 2006.286.02:18:56.71#ibcon#*before write, iclass 29, count 0 2006.286.02:18:56.71#ibcon#enter sib2, iclass 29, count 0 2006.286.02:18:56.71#ibcon#flushed, iclass 29, count 0 2006.286.02:18:56.71#ibcon#about to write, iclass 29, count 0 2006.286.02:18:56.71#ibcon#wrote, iclass 29, count 0 2006.286.02:18:56.71#ibcon#about to read 3, iclass 29, count 0 2006.286.02:18:56.74#ibcon#read 3, iclass 29, count 0 2006.286.02:18:56.74#ibcon#about to read 4, iclass 29, count 0 2006.286.02:18:56.74#ibcon#read 4, iclass 29, count 0 2006.286.02:18:56.74#ibcon#about to read 5, iclass 29, count 0 2006.286.02:18:56.74#ibcon#read 5, iclass 29, count 0 2006.286.02:18:56.74#ibcon#about to read 6, iclass 29, count 0 2006.286.02:18:56.74#ibcon#read 6, iclass 29, count 0 2006.286.02:18:56.74#ibcon#end of sib2, iclass 29, count 0 2006.286.02:18:56.74#ibcon#*after write, iclass 29, count 0 2006.286.02:18:56.74#ibcon#*before return 0, iclass 29, count 0 2006.286.02:18:56.74#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:18:56.74#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:18:56.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.02:18:56.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.02:18:56.74$vck44/valo=5,734.99 2006.286.02:18:56.74#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.02:18:56.74#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.02:18:56.74#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:56.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:18:56.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:18:56.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:18:56.74#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:18:56.74#ibcon#first serial, iclass 31, count 0 2006.286.02:18:56.74#ibcon#enter sib2, iclass 31, count 0 2006.286.02:18:56.74#ibcon#flushed, iclass 31, count 0 2006.286.02:18:56.74#ibcon#about to write, iclass 31, count 0 2006.286.02:18:56.74#ibcon#wrote, iclass 31, count 0 2006.286.02:18:56.74#ibcon#about to read 3, iclass 31, count 0 2006.286.02:18:56.76#ibcon#read 3, iclass 31, count 0 2006.286.02:18:56.76#ibcon#about to read 4, iclass 31, count 0 2006.286.02:18:56.76#ibcon#read 4, iclass 31, count 0 2006.286.02:18:56.76#ibcon#about to read 5, iclass 31, count 0 2006.286.02:18:56.76#ibcon#read 5, iclass 31, count 0 2006.286.02:18:56.76#ibcon#about to read 6, iclass 31, count 0 2006.286.02:18:56.76#ibcon#read 6, iclass 31, count 0 2006.286.02:18:56.76#ibcon#end of sib2, iclass 31, count 0 2006.286.02:18:56.76#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:18:56.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:18:56.76#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.02:18:56.76#ibcon#*before write, iclass 31, count 0 2006.286.02:18:56.76#ibcon#enter sib2, iclass 31, count 0 2006.286.02:18:56.76#ibcon#flushed, iclass 31, count 0 2006.286.02:18:56.76#ibcon#about to write, iclass 31, count 0 2006.286.02:18:56.76#ibcon#wrote, iclass 31, count 0 2006.286.02:18:56.76#ibcon#about to read 3, iclass 31, count 0 2006.286.02:18:56.80#ibcon#read 3, iclass 31, count 0 2006.286.02:18:56.80#ibcon#about to read 4, iclass 31, count 0 2006.286.02:18:56.80#ibcon#read 4, iclass 31, count 0 2006.286.02:18:56.80#ibcon#about to read 5, iclass 31, count 0 2006.286.02:18:56.80#ibcon#read 5, iclass 31, count 0 2006.286.02:18:56.80#ibcon#about to read 6, iclass 31, count 0 2006.286.02:18:56.80#ibcon#read 6, iclass 31, count 0 2006.286.02:18:56.80#ibcon#end of sib2, iclass 31, count 0 2006.286.02:18:56.80#ibcon#*after write, iclass 31, count 0 2006.286.02:18:56.80#ibcon#*before return 0, iclass 31, count 0 2006.286.02:18:56.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:18:56.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:18:56.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:18:56.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:18:56.80$vck44/va=5,3 2006.286.02:18:56.80#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.02:18:56.80#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.02:18:56.80#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:56.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:18:56.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:18:56.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:18:56.86#ibcon#enter wrdev, iclass 33, count 2 2006.286.02:18:56.86#ibcon#first serial, iclass 33, count 2 2006.286.02:18:56.86#ibcon#enter sib2, iclass 33, count 2 2006.286.02:18:56.86#ibcon#flushed, iclass 33, count 2 2006.286.02:18:56.86#ibcon#about to write, iclass 33, count 2 2006.286.02:18:56.86#ibcon#wrote, iclass 33, count 2 2006.286.02:18:56.86#ibcon#about to read 3, iclass 33, count 2 2006.286.02:18:56.88#ibcon#read 3, iclass 33, count 2 2006.286.02:18:56.88#ibcon#about to read 4, iclass 33, count 2 2006.286.02:18:56.88#ibcon#read 4, iclass 33, count 2 2006.286.02:18:56.88#ibcon#about to read 5, iclass 33, count 2 2006.286.02:18:56.88#ibcon#read 5, iclass 33, count 2 2006.286.02:18:56.88#ibcon#about to read 6, iclass 33, count 2 2006.286.02:18:56.88#ibcon#read 6, iclass 33, count 2 2006.286.02:18:56.88#ibcon#end of sib2, iclass 33, count 2 2006.286.02:18:56.88#ibcon#*mode == 0, iclass 33, count 2 2006.286.02:18:56.88#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.02:18:56.88#ibcon#[25=AT05-03\r\n] 2006.286.02:18:56.88#ibcon#*before write, iclass 33, count 2 2006.286.02:18:56.88#ibcon#enter sib2, iclass 33, count 2 2006.286.02:18:56.88#ibcon#flushed, iclass 33, count 2 2006.286.02:18:56.88#ibcon#about to write, iclass 33, count 2 2006.286.02:18:56.88#ibcon#wrote, iclass 33, count 2 2006.286.02:18:56.88#ibcon#about to read 3, iclass 33, count 2 2006.286.02:18:56.91#ibcon#read 3, iclass 33, count 2 2006.286.02:18:56.91#ibcon#about to read 4, iclass 33, count 2 2006.286.02:18:56.91#ibcon#read 4, iclass 33, count 2 2006.286.02:18:56.91#ibcon#about to read 5, iclass 33, count 2 2006.286.02:18:56.91#ibcon#read 5, iclass 33, count 2 2006.286.02:18:56.91#ibcon#about to read 6, iclass 33, count 2 2006.286.02:18:56.91#ibcon#read 6, iclass 33, count 2 2006.286.02:18:56.91#ibcon#end of sib2, iclass 33, count 2 2006.286.02:18:56.91#ibcon#*after write, iclass 33, count 2 2006.286.02:18:56.91#ibcon#*before return 0, iclass 33, count 2 2006.286.02:18:56.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:18:56.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:18:56.91#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.02:18:56.91#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:56.91#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:18:57.03#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:18:57.03#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:18:57.03#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:18:57.03#ibcon#first serial, iclass 33, count 0 2006.286.02:18:57.03#ibcon#enter sib2, iclass 33, count 0 2006.286.02:18:57.03#ibcon#flushed, iclass 33, count 0 2006.286.02:18:57.03#ibcon#about to write, iclass 33, count 0 2006.286.02:18:57.03#ibcon#wrote, iclass 33, count 0 2006.286.02:18:57.03#ibcon#about to read 3, iclass 33, count 0 2006.286.02:18:57.05#ibcon#read 3, iclass 33, count 0 2006.286.02:18:57.05#ibcon#about to read 4, iclass 33, count 0 2006.286.02:18:57.05#ibcon#read 4, iclass 33, count 0 2006.286.02:18:57.05#ibcon#about to read 5, iclass 33, count 0 2006.286.02:18:57.05#ibcon#read 5, iclass 33, count 0 2006.286.02:18:57.05#ibcon#about to read 6, iclass 33, count 0 2006.286.02:18:57.05#ibcon#read 6, iclass 33, count 0 2006.286.02:18:57.05#ibcon#end of sib2, iclass 33, count 0 2006.286.02:18:57.05#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:18:57.05#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:18:57.05#ibcon#[25=USB\r\n] 2006.286.02:18:57.05#ibcon#*before write, iclass 33, count 0 2006.286.02:18:57.05#ibcon#enter sib2, iclass 33, count 0 2006.286.02:18:57.05#ibcon#flushed, iclass 33, count 0 2006.286.02:18:57.05#ibcon#about to write, iclass 33, count 0 2006.286.02:18:57.05#ibcon#wrote, iclass 33, count 0 2006.286.02:18:57.05#ibcon#about to read 3, iclass 33, count 0 2006.286.02:18:57.08#ibcon#read 3, iclass 33, count 0 2006.286.02:18:57.08#ibcon#about to read 4, iclass 33, count 0 2006.286.02:18:57.08#ibcon#read 4, iclass 33, count 0 2006.286.02:18:57.08#ibcon#about to read 5, iclass 33, count 0 2006.286.02:18:57.08#ibcon#read 5, iclass 33, count 0 2006.286.02:18:57.08#ibcon#about to read 6, iclass 33, count 0 2006.286.02:18:57.08#ibcon#read 6, iclass 33, count 0 2006.286.02:18:57.08#ibcon#end of sib2, iclass 33, count 0 2006.286.02:18:57.08#ibcon#*after write, iclass 33, count 0 2006.286.02:18:57.08#ibcon#*before return 0, iclass 33, count 0 2006.286.02:18:57.08#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:18:57.08#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:18:57.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:18:57.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:18:57.08$vck44/valo=6,814.99 2006.286.02:18:57.08#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.02:18:57.08#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.02:18:57.08#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:57.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:18:57.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:18:57.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:18:57.08#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:18:57.08#ibcon#first serial, iclass 35, count 0 2006.286.02:18:57.08#ibcon#enter sib2, iclass 35, count 0 2006.286.02:18:57.08#ibcon#flushed, iclass 35, count 0 2006.286.02:18:57.08#ibcon#about to write, iclass 35, count 0 2006.286.02:18:57.08#ibcon#wrote, iclass 35, count 0 2006.286.02:18:57.08#ibcon#about to read 3, iclass 35, count 0 2006.286.02:18:57.10#ibcon#read 3, iclass 35, count 0 2006.286.02:18:57.10#ibcon#about to read 4, iclass 35, count 0 2006.286.02:18:57.10#ibcon#read 4, iclass 35, count 0 2006.286.02:18:57.10#ibcon#about to read 5, iclass 35, count 0 2006.286.02:18:57.10#ibcon#read 5, iclass 35, count 0 2006.286.02:18:57.10#ibcon#about to read 6, iclass 35, count 0 2006.286.02:18:57.10#ibcon#read 6, iclass 35, count 0 2006.286.02:18:57.10#ibcon#end of sib2, iclass 35, count 0 2006.286.02:18:57.10#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:18:57.10#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:18:57.10#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.02:18:57.10#ibcon#*before write, iclass 35, count 0 2006.286.02:18:57.10#ibcon#enter sib2, iclass 35, count 0 2006.286.02:18:57.10#ibcon#flushed, iclass 35, count 0 2006.286.02:18:57.10#ibcon#about to write, iclass 35, count 0 2006.286.02:18:57.10#ibcon#wrote, iclass 35, count 0 2006.286.02:18:57.10#ibcon#about to read 3, iclass 35, count 0 2006.286.02:18:57.14#ibcon#read 3, iclass 35, count 0 2006.286.02:18:57.14#ibcon#about to read 4, iclass 35, count 0 2006.286.02:18:57.14#ibcon#read 4, iclass 35, count 0 2006.286.02:18:57.14#ibcon#about to read 5, iclass 35, count 0 2006.286.02:18:57.14#ibcon#read 5, iclass 35, count 0 2006.286.02:18:57.14#ibcon#about to read 6, iclass 35, count 0 2006.286.02:18:57.14#ibcon#read 6, iclass 35, count 0 2006.286.02:18:57.14#ibcon#end of sib2, iclass 35, count 0 2006.286.02:18:57.14#ibcon#*after write, iclass 35, count 0 2006.286.02:18:57.14#ibcon#*before return 0, iclass 35, count 0 2006.286.02:18:57.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:18:57.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:18:57.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:18:57.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:18:57.14$vck44/va=6,4 2006.286.02:18:57.14#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.02:18:57.14#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.02:18:57.14#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:57.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:18:57.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:18:57.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:18:57.20#ibcon#enter wrdev, iclass 37, count 2 2006.286.02:18:57.20#ibcon#first serial, iclass 37, count 2 2006.286.02:18:57.20#ibcon#enter sib2, iclass 37, count 2 2006.286.02:18:57.20#ibcon#flushed, iclass 37, count 2 2006.286.02:18:57.20#ibcon#about to write, iclass 37, count 2 2006.286.02:18:57.20#ibcon#wrote, iclass 37, count 2 2006.286.02:18:57.20#ibcon#about to read 3, iclass 37, count 2 2006.286.02:18:57.22#ibcon#read 3, iclass 37, count 2 2006.286.02:18:57.22#ibcon#about to read 4, iclass 37, count 2 2006.286.02:18:57.22#ibcon#read 4, iclass 37, count 2 2006.286.02:18:57.22#ibcon#about to read 5, iclass 37, count 2 2006.286.02:18:57.22#ibcon#read 5, iclass 37, count 2 2006.286.02:18:57.22#ibcon#about to read 6, iclass 37, count 2 2006.286.02:18:57.22#ibcon#read 6, iclass 37, count 2 2006.286.02:18:57.22#ibcon#end of sib2, iclass 37, count 2 2006.286.02:18:57.22#ibcon#*mode == 0, iclass 37, count 2 2006.286.02:18:57.22#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.02:18:57.22#ibcon#[25=AT06-04\r\n] 2006.286.02:18:57.22#ibcon#*before write, iclass 37, count 2 2006.286.02:18:57.22#ibcon#enter sib2, iclass 37, count 2 2006.286.02:18:57.22#ibcon#flushed, iclass 37, count 2 2006.286.02:18:57.22#ibcon#about to write, iclass 37, count 2 2006.286.02:18:57.22#ibcon#wrote, iclass 37, count 2 2006.286.02:18:57.22#ibcon#about to read 3, iclass 37, count 2 2006.286.02:18:57.25#ibcon#read 3, iclass 37, count 2 2006.286.02:18:57.25#ibcon#about to read 4, iclass 37, count 2 2006.286.02:18:57.25#ibcon#read 4, iclass 37, count 2 2006.286.02:18:57.25#ibcon#about to read 5, iclass 37, count 2 2006.286.02:18:57.25#ibcon#read 5, iclass 37, count 2 2006.286.02:18:57.25#ibcon#about to read 6, iclass 37, count 2 2006.286.02:18:57.25#ibcon#read 6, iclass 37, count 2 2006.286.02:18:57.25#ibcon#end of sib2, iclass 37, count 2 2006.286.02:18:57.25#ibcon#*after write, iclass 37, count 2 2006.286.02:18:57.25#ibcon#*before return 0, iclass 37, count 2 2006.286.02:18:57.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:18:57.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:18:57.25#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.02:18:57.25#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:57.25#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:18:57.37#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:18:57.37#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:18:57.37#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:18:57.37#ibcon#first serial, iclass 37, count 0 2006.286.02:18:57.37#ibcon#enter sib2, iclass 37, count 0 2006.286.02:18:57.37#ibcon#flushed, iclass 37, count 0 2006.286.02:18:57.37#ibcon#about to write, iclass 37, count 0 2006.286.02:18:57.37#ibcon#wrote, iclass 37, count 0 2006.286.02:18:57.37#ibcon#about to read 3, iclass 37, count 0 2006.286.02:18:57.39#ibcon#read 3, iclass 37, count 0 2006.286.02:18:57.39#ibcon#about to read 4, iclass 37, count 0 2006.286.02:18:57.39#ibcon#read 4, iclass 37, count 0 2006.286.02:18:57.39#ibcon#about to read 5, iclass 37, count 0 2006.286.02:18:57.39#ibcon#read 5, iclass 37, count 0 2006.286.02:18:57.39#ibcon#about to read 6, iclass 37, count 0 2006.286.02:18:57.39#ibcon#read 6, iclass 37, count 0 2006.286.02:18:57.39#ibcon#end of sib2, iclass 37, count 0 2006.286.02:18:57.39#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:18:57.39#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:18:57.39#ibcon#[25=USB\r\n] 2006.286.02:18:57.39#ibcon#*before write, iclass 37, count 0 2006.286.02:18:57.39#ibcon#enter sib2, iclass 37, count 0 2006.286.02:18:57.39#ibcon#flushed, iclass 37, count 0 2006.286.02:18:57.39#ibcon#about to write, iclass 37, count 0 2006.286.02:18:57.39#ibcon#wrote, iclass 37, count 0 2006.286.02:18:57.39#ibcon#about to read 3, iclass 37, count 0 2006.286.02:18:57.42#ibcon#read 3, iclass 37, count 0 2006.286.02:18:57.42#ibcon#about to read 4, iclass 37, count 0 2006.286.02:18:57.42#ibcon#read 4, iclass 37, count 0 2006.286.02:18:57.42#ibcon#about to read 5, iclass 37, count 0 2006.286.02:18:57.42#ibcon#read 5, iclass 37, count 0 2006.286.02:18:57.42#ibcon#about to read 6, iclass 37, count 0 2006.286.02:18:57.42#ibcon#read 6, iclass 37, count 0 2006.286.02:18:57.42#ibcon#end of sib2, iclass 37, count 0 2006.286.02:18:57.42#ibcon#*after write, iclass 37, count 0 2006.286.02:18:57.42#ibcon#*before return 0, iclass 37, count 0 2006.286.02:18:57.42#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:18:57.42#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:18:57.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:18:57.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:18:57.42$vck44/valo=7,864.99 2006.286.02:18:57.42#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.02:18:57.42#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.02:18:57.42#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:57.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:18:57.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:18:57.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:18:57.42#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:18:57.42#ibcon#first serial, iclass 39, count 0 2006.286.02:18:57.42#ibcon#enter sib2, iclass 39, count 0 2006.286.02:18:57.42#ibcon#flushed, iclass 39, count 0 2006.286.02:18:57.42#ibcon#about to write, iclass 39, count 0 2006.286.02:18:57.42#ibcon#wrote, iclass 39, count 0 2006.286.02:18:57.42#ibcon#about to read 3, iclass 39, count 0 2006.286.02:18:57.44#ibcon#read 3, iclass 39, count 0 2006.286.02:18:57.44#ibcon#about to read 4, iclass 39, count 0 2006.286.02:18:57.44#ibcon#read 4, iclass 39, count 0 2006.286.02:18:57.44#ibcon#about to read 5, iclass 39, count 0 2006.286.02:18:57.44#ibcon#read 5, iclass 39, count 0 2006.286.02:18:57.44#ibcon#about to read 6, iclass 39, count 0 2006.286.02:18:57.44#ibcon#read 6, iclass 39, count 0 2006.286.02:18:57.44#ibcon#end of sib2, iclass 39, count 0 2006.286.02:18:57.44#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:18:57.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:18:57.44#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.02:18:57.44#ibcon#*before write, iclass 39, count 0 2006.286.02:18:57.44#ibcon#enter sib2, iclass 39, count 0 2006.286.02:18:57.44#ibcon#flushed, iclass 39, count 0 2006.286.02:18:57.44#ibcon#about to write, iclass 39, count 0 2006.286.02:18:57.44#ibcon#wrote, iclass 39, count 0 2006.286.02:18:57.44#ibcon#about to read 3, iclass 39, count 0 2006.286.02:18:57.48#ibcon#read 3, iclass 39, count 0 2006.286.02:18:57.48#ibcon#about to read 4, iclass 39, count 0 2006.286.02:18:57.48#ibcon#read 4, iclass 39, count 0 2006.286.02:18:57.48#ibcon#about to read 5, iclass 39, count 0 2006.286.02:18:57.48#ibcon#read 5, iclass 39, count 0 2006.286.02:18:57.48#ibcon#about to read 6, iclass 39, count 0 2006.286.02:18:57.48#ibcon#read 6, iclass 39, count 0 2006.286.02:18:57.48#ibcon#end of sib2, iclass 39, count 0 2006.286.02:18:57.48#ibcon#*after write, iclass 39, count 0 2006.286.02:18:57.48#ibcon#*before return 0, iclass 39, count 0 2006.286.02:18:57.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:18:57.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:18:57.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:18:57.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:18:57.48$vck44/va=7,4 2006.286.02:18:57.48#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.02:18:57.48#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.02:18:57.48#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:57.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:18:57.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:18:57.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:18:57.54#ibcon#enter wrdev, iclass 3, count 2 2006.286.02:18:57.54#ibcon#first serial, iclass 3, count 2 2006.286.02:18:57.54#ibcon#enter sib2, iclass 3, count 2 2006.286.02:18:57.54#ibcon#flushed, iclass 3, count 2 2006.286.02:18:57.54#ibcon#about to write, iclass 3, count 2 2006.286.02:18:57.54#ibcon#wrote, iclass 3, count 2 2006.286.02:18:57.54#ibcon#about to read 3, iclass 3, count 2 2006.286.02:18:57.56#ibcon#read 3, iclass 3, count 2 2006.286.02:18:57.56#ibcon#about to read 4, iclass 3, count 2 2006.286.02:18:57.56#ibcon#read 4, iclass 3, count 2 2006.286.02:18:57.56#ibcon#about to read 5, iclass 3, count 2 2006.286.02:18:57.56#ibcon#read 5, iclass 3, count 2 2006.286.02:18:57.56#ibcon#about to read 6, iclass 3, count 2 2006.286.02:18:57.56#ibcon#read 6, iclass 3, count 2 2006.286.02:18:57.56#ibcon#end of sib2, iclass 3, count 2 2006.286.02:18:57.56#ibcon#*mode == 0, iclass 3, count 2 2006.286.02:18:57.56#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.02:18:57.56#ibcon#[25=AT07-04\r\n] 2006.286.02:18:57.56#ibcon#*before write, iclass 3, count 2 2006.286.02:18:57.56#ibcon#enter sib2, iclass 3, count 2 2006.286.02:18:57.56#ibcon#flushed, iclass 3, count 2 2006.286.02:18:57.56#ibcon#about to write, iclass 3, count 2 2006.286.02:18:57.56#ibcon#wrote, iclass 3, count 2 2006.286.02:18:57.56#ibcon#about to read 3, iclass 3, count 2 2006.286.02:18:57.59#ibcon#read 3, iclass 3, count 2 2006.286.02:18:57.59#ibcon#about to read 4, iclass 3, count 2 2006.286.02:18:57.59#ibcon#read 4, iclass 3, count 2 2006.286.02:18:57.59#ibcon#about to read 5, iclass 3, count 2 2006.286.02:18:57.59#ibcon#read 5, iclass 3, count 2 2006.286.02:18:57.59#ibcon#about to read 6, iclass 3, count 2 2006.286.02:18:57.59#ibcon#read 6, iclass 3, count 2 2006.286.02:18:57.59#ibcon#end of sib2, iclass 3, count 2 2006.286.02:18:57.59#ibcon#*after write, iclass 3, count 2 2006.286.02:18:57.59#ibcon#*before return 0, iclass 3, count 2 2006.286.02:18:57.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:18:57.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:18:57.59#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.02:18:57.59#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:57.59#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:18:57.71#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:18:57.71#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:18:57.71#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:18:57.71#ibcon#first serial, iclass 3, count 0 2006.286.02:18:57.71#ibcon#enter sib2, iclass 3, count 0 2006.286.02:18:57.71#ibcon#flushed, iclass 3, count 0 2006.286.02:18:57.71#ibcon#about to write, iclass 3, count 0 2006.286.02:18:57.71#ibcon#wrote, iclass 3, count 0 2006.286.02:18:57.71#ibcon#about to read 3, iclass 3, count 0 2006.286.02:18:57.73#ibcon#read 3, iclass 3, count 0 2006.286.02:18:57.73#ibcon#about to read 4, iclass 3, count 0 2006.286.02:18:57.73#ibcon#read 4, iclass 3, count 0 2006.286.02:18:57.73#ibcon#about to read 5, iclass 3, count 0 2006.286.02:18:57.73#ibcon#read 5, iclass 3, count 0 2006.286.02:18:57.73#ibcon#about to read 6, iclass 3, count 0 2006.286.02:18:57.73#ibcon#read 6, iclass 3, count 0 2006.286.02:18:57.73#ibcon#end of sib2, iclass 3, count 0 2006.286.02:18:57.73#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:18:57.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:18:57.73#ibcon#[25=USB\r\n] 2006.286.02:18:57.73#ibcon#*before write, iclass 3, count 0 2006.286.02:18:57.73#ibcon#enter sib2, iclass 3, count 0 2006.286.02:18:57.73#ibcon#flushed, iclass 3, count 0 2006.286.02:18:57.73#ibcon#about to write, iclass 3, count 0 2006.286.02:18:57.73#ibcon#wrote, iclass 3, count 0 2006.286.02:18:57.73#ibcon#about to read 3, iclass 3, count 0 2006.286.02:18:57.76#ibcon#read 3, iclass 3, count 0 2006.286.02:18:57.76#ibcon#about to read 4, iclass 3, count 0 2006.286.02:18:57.76#ibcon#read 4, iclass 3, count 0 2006.286.02:18:57.76#ibcon#about to read 5, iclass 3, count 0 2006.286.02:18:57.76#ibcon#read 5, iclass 3, count 0 2006.286.02:18:57.76#ibcon#about to read 6, iclass 3, count 0 2006.286.02:18:57.76#ibcon#read 6, iclass 3, count 0 2006.286.02:18:57.76#ibcon#end of sib2, iclass 3, count 0 2006.286.02:18:57.76#ibcon#*after write, iclass 3, count 0 2006.286.02:18:57.76#ibcon#*before return 0, iclass 3, count 0 2006.286.02:18:57.76#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:18:57.76#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:18:57.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:18:57.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:18:57.76$vck44/valo=8,884.99 2006.286.02:18:57.76#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.02:18:57.76#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.02:18:57.76#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:57.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:18:57.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:18:57.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:18:57.76#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:18:57.76#ibcon#first serial, iclass 5, count 0 2006.286.02:18:57.76#ibcon#enter sib2, iclass 5, count 0 2006.286.02:18:57.76#ibcon#flushed, iclass 5, count 0 2006.286.02:18:57.76#ibcon#about to write, iclass 5, count 0 2006.286.02:18:57.76#ibcon#wrote, iclass 5, count 0 2006.286.02:18:57.76#ibcon#about to read 3, iclass 5, count 0 2006.286.02:18:57.78#ibcon#read 3, iclass 5, count 0 2006.286.02:18:57.78#ibcon#about to read 4, iclass 5, count 0 2006.286.02:18:57.78#ibcon#read 4, iclass 5, count 0 2006.286.02:18:57.78#ibcon#about to read 5, iclass 5, count 0 2006.286.02:18:57.78#ibcon#read 5, iclass 5, count 0 2006.286.02:18:57.78#ibcon#about to read 6, iclass 5, count 0 2006.286.02:18:57.78#ibcon#read 6, iclass 5, count 0 2006.286.02:18:57.78#ibcon#end of sib2, iclass 5, count 0 2006.286.02:18:57.78#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:18:57.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:18:57.78#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.02:18:57.78#ibcon#*before write, iclass 5, count 0 2006.286.02:18:57.78#ibcon#enter sib2, iclass 5, count 0 2006.286.02:18:57.78#ibcon#flushed, iclass 5, count 0 2006.286.02:18:57.78#ibcon#about to write, iclass 5, count 0 2006.286.02:18:57.78#ibcon#wrote, iclass 5, count 0 2006.286.02:18:57.78#ibcon#about to read 3, iclass 5, count 0 2006.286.02:18:57.82#ibcon#read 3, iclass 5, count 0 2006.286.02:18:57.82#ibcon#about to read 4, iclass 5, count 0 2006.286.02:18:57.82#ibcon#read 4, iclass 5, count 0 2006.286.02:18:57.82#ibcon#about to read 5, iclass 5, count 0 2006.286.02:18:57.82#ibcon#read 5, iclass 5, count 0 2006.286.02:18:57.82#ibcon#about to read 6, iclass 5, count 0 2006.286.02:18:57.82#ibcon#read 6, iclass 5, count 0 2006.286.02:18:57.82#ibcon#end of sib2, iclass 5, count 0 2006.286.02:18:57.82#ibcon#*after write, iclass 5, count 0 2006.286.02:18:57.82#ibcon#*before return 0, iclass 5, count 0 2006.286.02:18:57.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:18:57.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:18:57.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:18:57.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:18:57.82$vck44/va=8,3 2006.286.02:18:57.82#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.02:18:57.82#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.02:18:57.82#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:57.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:18:57.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:18:57.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:18:57.88#ibcon#enter wrdev, iclass 7, count 2 2006.286.02:18:57.88#ibcon#first serial, iclass 7, count 2 2006.286.02:18:57.88#ibcon#enter sib2, iclass 7, count 2 2006.286.02:18:57.88#ibcon#flushed, iclass 7, count 2 2006.286.02:18:57.88#ibcon#about to write, iclass 7, count 2 2006.286.02:18:57.88#ibcon#wrote, iclass 7, count 2 2006.286.02:18:57.88#ibcon#about to read 3, iclass 7, count 2 2006.286.02:18:57.90#ibcon#read 3, iclass 7, count 2 2006.286.02:18:57.90#ibcon#about to read 4, iclass 7, count 2 2006.286.02:18:57.90#ibcon#read 4, iclass 7, count 2 2006.286.02:18:57.90#ibcon#about to read 5, iclass 7, count 2 2006.286.02:18:57.90#ibcon#read 5, iclass 7, count 2 2006.286.02:18:57.90#ibcon#about to read 6, iclass 7, count 2 2006.286.02:18:57.90#ibcon#read 6, iclass 7, count 2 2006.286.02:18:57.90#ibcon#end of sib2, iclass 7, count 2 2006.286.02:18:57.90#ibcon#*mode == 0, iclass 7, count 2 2006.286.02:18:57.90#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.02:18:57.90#ibcon#[25=AT08-03\r\n] 2006.286.02:18:57.90#ibcon#*before write, iclass 7, count 2 2006.286.02:18:57.90#ibcon#enter sib2, iclass 7, count 2 2006.286.02:18:57.90#ibcon#flushed, iclass 7, count 2 2006.286.02:18:57.90#ibcon#about to write, iclass 7, count 2 2006.286.02:18:57.90#ibcon#wrote, iclass 7, count 2 2006.286.02:18:57.90#ibcon#about to read 3, iclass 7, count 2 2006.286.02:18:57.93#ibcon#read 3, iclass 7, count 2 2006.286.02:18:57.93#ibcon#about to read 4, iclass 7, count 2 2006.286.02:18:57.93#ibcon#read 4, iclass 7, count 2 2006.286.02:18:57.93#ibcon#about to read 5, iclass 7, count 2 2006.286.02:18:57.93#ibcon#read 5, iclass 7, count 2 2006.286.02:18:57.93#ibcon#about to read 6, iclass 7, count 2 2006.286.02:18:57.93#ibcon#read 6, iclass 7, count 2 2006.286.02:18:57.93#ibcon#end of sib2, iclass 7, count 2 2006.286.02:18:57.93#ibcon#*after write, iclass 7, count 2 2006.286.02:18:57.93#ibcon#*before return 0, iclass 7, count 2 2006.286.02:18:57.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:18:57.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:18:57.93#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.02:18:57.93#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:57.93#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:18:58.05#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:18:58.05#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:18:58.05#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:18:58.05#ibcon#first serial, iclass 7, count 0 2006.286.02:18:58.05#ibcon#enter sib2, iclass 7, count 0 2006.286.02:18:58.05#ibcon#flushed, iclass 7, count 0 2006.286.02:18:58.05#ibcon#about to write, iclass 7, count 0 2006.286.02:18:58.05#ibcon#wrote, iclass 7, count 0 2006.286.02:18:58.05#ibcon#about to read 3, iclass 7, count 0 2006.286.02:18:58.07#ibcon#read 3, iclass 7, count 0 2006.286.02:18:58.07#ibcon#about to read 4, iclass 7, count 0 2006.286.02:18:58.07#ibcon#read 4, iclass 7, count 0 2006.286.02:18:58.07#ibcon#about to read 5, iclass 7, count 0 2006.286.02:18:58.07#ibcon#read 5, iclass 7, count 0 2006.286.02:18:58.07#ibcon#about to read 6, iclass 7, count 0 2006.286.02:18:58.07#ibcon#read 6, iclass 7, count 0 2006.286.02:18:58.07#ibcon#end of sib2, iclass 7, count 0 2006.286.02:18:58.07#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:18:58.07#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:18:58.07#ibcon#[25=USB\r\n] 2006.286.02:18:58.07#ibcon#*before write, iclass 7, count 0 2006.286.02:18:58.07#ibcon#enter sib2, iclass 7, count 0 2006.286.02:18:58.07#ibcon#flushed, iclass 7, count 0 2006.286.02:18:58.07#ibcon#about to write, iclass 7, count 0 2006.286.02:18:58.07#ibcon#wrote, iclass 7, count 0 2006.286.02:18:58.07#ibcon#about to read 3, iclass 7, count 0 2006.286.02:18:58.10#ibcon#read 3, iclass 7, count 0 2006.286.02:18:58.10#ibcon#about to read 4, iclass 7, count 0 2006.286.02:18:58.10#ibcon#read 4, iclass 7, count 0 2006.286.02:18:58.10#ibcon#about to read 5, iclass 7, count 0 2006.286.02:18:58.10#ibcon#read 5, iclass 7, count 0 2006.286.02:18:58.10#ibcon#about to read 6, iclass 7, count 0 2006.286.02:18:58.10#ibcon#read 6, iclass 7, count 0 2006.286.02:18:58.10#ibcon#end of sib2, iclass 7, count 0 2006.286.02:18:58.10#ibcon#*after write, iclass 7, count 0 2006.286.02:18:58.10#ibcon#*before return 0, iclass 7, count 0 2006.286.02:18:58.10#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:18:58.10#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:18:58.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:18:58.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:18:58.10$vck44/vblo=1,629.99 2006.286.02:18:58.10#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.02:18:58.10#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.02:18:58.10#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:58.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:18:58.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:18:58.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:18:58.10#ibcon#enter wrdev, iclass 11, count 0 2006.286.02:18:58.10#ibcon#first serial, iclass 11, count 0 2006.286.02:18:58.10#ibcon#enter sib2, iclass 11, count 0 2006.286.02:18:58.10#ibcon#flushed, iclass 11, count 0 2006.286.02:18:58.10#ibcon#about to write, iclass 11, count 0 2006.286.02:18:58.10#ibcon#wrote, iclass 11, count 0 2006.286.02:18:58.10#ibcon#about to read 3, iclass 11, count 0 2006.286.02:18:58.12#ibcon#read 3, iclass 11, count 0 2006.286.02:18:58.12#ibcon#about to read 4, iclass 11, count 0 2006.286.02:18:58.12#ibcon#read 4, iclass 11, count 0 2006.286.02:18:58.12#ibcon#about to read 5, iclass 11, count 0 2006.286.02:18:58.12#ibcon#read 5, iclass 11, count 0 2006.286.02:18:58.12#ibcon#about to read 6, iclass 11, count 0 2006.286.02:18:58.12#ibcon#read 6, iclass 11, count 0 2006.286.02:18:58.12#ibcon#end of sib2, iclass 11, count 0 2006.286.02:18:58.12#ibcon#*mode == 0, iclass 11, count 0 2006.286.02:18:58.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.02:18:58.12#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.02:18:58.12#ibcon#*before write, iclass 11, count 0 2006.286.02:18:58.12#ibcon#enter sib2, iclass 11, count 0 2006.286.02:18:58.12#ibcon#flushed, iclass 11, count 0 2006.286.02:18:58.12#ibcon#about to write, iclass 11, count 0 2006.286.02:18:58.12#ibcon#wrote, iclass 11, count 0 2006.286.02:18:58.12#ibcon#about to read 3, iclass 11, count 0 2006.286.02:18:58.16#ibcon#read 3, iclass 11, count 0 2006.286.02:18:58.16#ibcon#about to read 4, iclass 11, count 0 2006.286.02:18:58.16#ibcon#read 4, iclass 11, count 0 2006.286.02:18:58.16#ibcon#about to read 5, iclass 11, count 0 2006.286.02:18:58.16#ibcon#read 5, iclass 11, count 0 2006.286.02:18:58.16#ibcon#about to read 6, iclass 11, count 0 2006.286.02:18:58.16#ibcon#read 6, iclass 11, count 0 2006.286.02:18:58.16#ibcon#end of sib2, iclass 11, count 0 2006.286.02:18:58.16#ibcon#*after write, iclass 11, count 0 2006.286.02:18:58.16#ibcon#*before return 0, iclass 11, count 0 2006.286.02:18:58.16#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:18:58.16#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:18:58.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.02:18:58.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.02:18:58.16$vck44/vb=1,4 2006.286.02:18:58.16#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.02:18:58.16#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.02:18:58.16#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:58.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:18:58.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:18:58.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:18:58.16#ibcon#enter wrdev, iclass 13, count 2 2006.286.02:18:58.16#ibcon#first serial, iclass 13, count 2 2006.286.02:18:58.16#ibcon#enter sib2, iclass 13, count 2 2006.286.02:18:58.16#ibcon#flushed, iclass 13, count 2 2006.286.02:18:58.16#ibcon#about to write, iclass 13, count 2 2006.286.02:18:58.16#ibcon#wrote, iclass 13, count 2 2006.286.02:18:58.16#ibcon#about to read 3, iclass 13, count 2 2006.286.02:18:58.18#ibcon#read 3, iclass 13, count 2 2006.286.02:18:58.18#ibcon#about to read 4, iclass 13, count 2 2006.286.02:18:58.18#ibcon#read 4, iclass 13, count 2 2006.286.02:18:58.18#ibcon#about to read 5, iclass 13, count 2 2006.286.02:18:58.18#ibcon#read 5, iclass 13, count 2 2006.286.02:18:58.18#ibcon#about to read 6, iclass 13, count 2 2006.286.02:18:58.18#ibcon#read 6, iclass 13, count 2 2006.286.02:18:58.18#ibcon#end of sib2, iclass 13, count 2 2006.286.02:18:58.18#ibcon#*mode == 0, iclass 13, count 2 2006.286.02:18:58.18#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.02:18:58.18#ibcon#[27=AT01-04\r\n] 2006.286.02:18:58.18#ibcon#*before write, iclass 13, count 2 2006.286.02:18:58.18#ibcon#enter sib2, iclass 13, count 2 2006.286.02:18:58.18#ibcon#flushed, iclass 13, count 2 2006.286.02:18:58.18#ibcon#about to write, iclass 13, count 2 2006.286.02:18:58.18#ibcon#wrote, iclass 13, count 2 2006.286.02:18:58.18#ibcon#about to read 3, iclass 13, count 2 2006.286.02:18:58.21#ibcon#read 3, iclass 13, count 2 2006.286.02:18:58.21#ibcon#about to read 4, iclass 13, count 2 2006.286.02:18:58.21#ibcon#read 4, iclass 13, count 2 2006.286.02:18:58.21#ibcon#about to read 5, iclass 13, count 2 2006.286.02:18:58.21#ibcon#read 5, iclass 13, count 2 2006.286.02:18:58.21#ibcon#about to read 6, iclass 13, count 2 2006.286.02:18:58.21#ibcon#read 6, iclass 13, count 2 2006.286.02:18:58.21#ibcon#end of sib2, iclass 13, count 2 2006.286.02:18:58.21#ibcon#*after write, iclass 13, count 2 2006.286.02:18:58.21#ibcon#*before return 0, iclass 13, count 2 2006.286.02:18:58.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:18:58.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:18:58.21#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.02:18:58.21#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:58.21#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:18:58.33#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:18:58.33#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:18:58.33#ibcon#enter wrdev, iclass 13, count 0 2006.286.02:18:58.33#ibcon#first serial, iclass 13, count 0 2006.286.02:18:58.33#ibcon#enter sib2, iclass 13, count 0 2006.286.02:18:58.33#ibcon#flushed, iclass 13, count 0 2006.286.02:18:58.33#ibcon#about to write, iclass 13, count 0 2006.286.02:18:58.33#ibcon#wrote, iclass 13, count 0 2006.286.02:18:58.33#ibcon#about to read 3, iclass 13, count 0 2006.286.02:18:58.35#ibcon#read 3, iclass 13, count 0 2006.286.02:18:58.35#ibcon#about to read 4, iclass 13, count 0 2006.286.02:18:58.35#ibcon#read 4, iclass 13, count 0 2006.286.02:18:58.35#ibcon#about to read 5, iclass 13, count 0 2006.286.02:18:58.35#ibcon#read 5, iclass 13, count 0 2006.286.02:18:58.35#ibcon#about to read 6, iclass 13, count 0 2006.286.02:18:58.35#ibcon#read 6, iclass 13, count 0 2006.286.02:18:58.35#ibcon#end of sib2, iclass 13, count 0 2006.286.02:18:58.35#ibcon#*mode == 0, iclass 13, count 0 2006.286.02:18:58.35#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.02:18:58.35#ibcon#[27=USB\r\n] 2006.286.02:18:58.35#ibcon#*before write, iclass 13, count 0 2006.286.02:18:58.35#ibcon#enter sib2, iclass 13, count 0 2006.286.02:18:58.35#ibcon#flushed, iclass 13, count 0 2006.286.02:18:58.35#ibcon#about to write, iclass 13, count 0 2006.286.02:18:58.35#ibcon#wrote, iclass 13, count 0 2006.286.02:18:58.35#ibcon#about to read 3, iclass 13, count 0 2006.286.02:18:58.38#ibcon#read 3, iclass 13, count 0 2006.286.02:18:58.38#ibcon#about to read 4, iclass 13, count 0 2006.286.02:18:58.38#ibcon#read 4, iclass 13, count 0 2006.286.02:18:58.38#ibcon#about to read 5, iclass 13, count 0 2006.286.02:18:58.38#ibcon#read 5, iclass 13, count 0 2006.286.02:18:58.38#ibcon#about to read 6, iclass 13, count 0 2006.286.02:18:58.38#ibcon#read 6, iclass 13, count 0 2006.286.02:18:58.38#ibcon#end of sib2, iclass 13, count 0 2006.286.02:18:58.38#ibcon#*after write, iclass 13, count 0 2006.286.02:18:58.38#ibcon#*before return 0, iclass 13, count 0 2006.286.02:18:58.38#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:18:58.38#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:18:58.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.02:18:58.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.02:18:58.38$vck44/vblo=2,634.99 2006.286.02:18:58.38#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.02:18:58.38#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.02:18:58.38#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:58.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:18:58.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:18:58.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:18:58.38#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:18:58.38#ibcon#first serial, iclass 15, count 0 2006.286.02:18:58.38#ibcon#enter sib2, iclass 15, count 0 2006.286.02:18:58.38#ibcon#flushed, iclass 15, count 0 2006.286.02:18:58.38#ibcon#about to write, iclass 15, count 0 2006.286.02:18:58.38#ibcon#wrote, iclass 15, count 0 2006.286.02:18:58.38#ibcon#about to read 3, iclass 15, count 0 2006.286.02:18:58.40#ibcon#read 3, iclass 15, count 0 2006.286.02:18:58.40#ibcon#about to read 4, iclass 15, count 0 2006.286.02:18:58.40#ibcon#read 4, iclass 15, count 0 2006.286.02:18:58.40#ibcon#about to read 5, iclass 15, count 0 2006.286.02:18:58.40#ibcon#read 5, iclass 15, count 0 2006.286.02:18:58.40#ibcon#about to read 6, iclass 15, count 0 2006.286.02:18:58.40#ibcon#read 6, iclass 15, count 0 2006.286.02:18:58.40#ibcon#end of sib2, iclass 15, count 0 2006.286.02:18:58.40#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:18:58.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:18:58.40#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.02:18:58.40#ibcon#*before write, iclass 15, count 0 2006.286.02:18:58.40#ibcon#enter sib2, iclass 15, count 0 2006.286.02:18:58.40#ibcon#flushed, iclass 15, count 0 2006.286.02:18:58.40#ibcon#about to write, iclass 15, count 0 2006.286.02:18:58.40#ibcon#wrote, iclass 15, count 0 2006.286.02:18:58.40#ibcon#about to read 3, iclass 15, count 0 2006.286.02:18:58.44#ibcon#read 3, iclass 15, count 0 2006.286.02:18:58.44#ibcon#about to read 4, iclass 15, count 0 2006.286.02:18:58.44#ibcon#read 4, iclass 15, count 0 2006.286.02:18:58.44#ibcon#about to read 5, iclass 15, count 0 2006.286.02:18:58.44#ibcon#read 5, iclass 15, count 0 2006.286.02:18:58.44#ibcon#about to read 6, iclass 15, count 0 2006.286.02:18:58.44#ibcon#read 6, iclass 15, count 0 2006.286.02:18:58.44#ibcon#end of sib2, iclass 15, count 0 2006.286.02:18:58.44#ibcon#*after write, iclass 15, count 0 2006.286.02:18:58.44#ibcon#*before return 0, iclass 15, count 0 2006.286.02:18:58.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:18:58.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:18:58.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:18:58.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:18:58.44$vck44/vb=2,5 2006.286.02:18:58.44#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.02:18:58.44#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.02:18:58.44#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:58.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:18:58.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:18:58.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:18:58.50#ibcon#enter wrdev, iclass 17, count 2 2006.286.02:18:58.50#ibcon#first serial, iclass 17, count 2 2006.286.02:18:58.50#ibcon#enter sib2, iclass 17, count 2 2006.286.02:18:58.50#ibcon#flushed, iclass 17, count 2 2006.286.02:18:58.50#ibcon#about to write, iclass 17, count 2 2006.286.02:18:58.50#ibcon#wrote, iclass 17, count 2 2006.286.02:18:58.50#ibcon#about to read 3, iclass 17, count 2 2006.286.02:18:58.52#ibcon#read 3, iclass 17, count 2 2006.286.02:18:58.52#ibcon#about to read 4, iclass 17, count 2 2006.286.02:18:58.52#ibcon#read 4, iclass 17, count 2 2006.286.02:18:58.52#ibcon#about to read 5, iclass 17, count 2 2006.286.02:18:58.52#ibcon#read 5, iclass 17, count 2 2006.286.02:18:58.52#ibcon#about to read 6, iclass 17, count 2 2006.286.02:18:58.52#ibcon#read 6, iclass 17, count 2 2006.286.02:18:58.52#ibcon#end of sib2, iclass 17, count 2 2006.286.02:18:58.52#ibcon#*mode == 0, iclass 17, count 2 2006.286.02:18:58.52#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.02:18:58.52#ibcon#[27=AT02-05\r\n] 2006.286.02:18:58.52#ibcon#*before write, iclass 17, count 2 2006.286.02:18:58.52#ibcon#enter sib2, iclass 17, count 2 2006.286.02:18:58.52#ibcon#flushed, iclass 17, count 2 2006.286.02:18:58.52#ibcon#about to write, iclass 17, count 2 2006.286.02:18:58.52#ibcon#wrote, iclass 17, count 2 2006.286.02:18:58.52#ibcon#about to read 3, iclass 17, count 2 2006.286.02:18:58.55#ibcon#read 3, iclass 17, count 2 2006.286.02:18:58.55#ibcon#about to read 4, iclass 17, count 2 2006.286.02:18:58.55#ibcon#read 4, iclass 17, count 2 2006.286.02:18:58.55#ibcon#about to read 5, iclass 17, count 2 2006.286.02:18:58.55#ibcon#read 5, iclass 17, count 2 2006.286.02:18:58.55#ibcon#about to read 6, iclass 17, count 2 2006.286.02:18:58.55#ibcon#read 6, iclass 17, count 2 2006.286.02:18:58.55#ibcon#end of sib2, iclass 17, count 2 2006.286.02:18:58.55#ibcon#*after write, iclass 17, count 2 2006.286.02:18:58.55#ibcon#*before return 0, iclass 17, count 2 2006.286.02:18:58.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:18:58.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:18:58.55#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.02:18:58.55#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:58.55#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:18:58.67#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:18:58.67#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:18:58.67#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:18:58.67#ibcon#first serial, iclass 17, count 0 2006.286.02:18:58.67#ibcon#enter sib2, iclass 17, count 0 2006.286.02:18:58.67#ibcon#flushed, iclass 17, count 0 2006.286.02:18:58.67#ibcon#about to write, iclass 17, count 0 2006.286.02:18:58.67#ibcon#wrote, iclass 17, count 0 2006.286.02:18:58.67#ibcon#about to read 3, iclass 17, count 0 2006.286.02:18:58.69#ibcon#read 3, iclass 17, count 0 2006.286.02:18:58.69#ibcon#about to read 4, iclass 17, count 0 2006.286.02:18:58.69#ibcon#read 4, iclass 17, count 0 2006.286.02:18:58.69#ibcon#about to read 5, iclass 17, count 0 2006.286.02:18:58.69#ibcon#read 5, iclass 17, count 0 2006.286.02:18:58.69#ibcon#about to read 6, iclass 17, count 0 2006.286.02:18:58.69#ibcon#read 6, iclass 17, count 0 2006.286.02:18:58.69#ibcon#end of sib2, iclass 17, count 0 2006.286.02:18:58.69#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:18:58.69#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:18:58.69#ibcon#[27=USB\r\n] 2006.286.02:18:58.69#ibcon#*before write, iclass 17, count 0 2006.286.02:18:58.69#ibcon#enter sib2, iclass 17, count 0 2006.286.02:18:58.69#ibcon#flushed, iclass 17, count 0 2006.286.02:18:58.69#ibcon#about to write, iclass 17, count 0 2006.286.02:18:58.69#ibcon#wrote, iclass 17, count 0 2006.286.02:18:58.69#ibcon#about to read 3, iclass 17, count 0 2006.286.02:18:58.72#ibcon#read 3, iclass 17, count 0 2006.286.02:18:58.72#ibcon#about to read 4, iclass 17, count 0 2006.286.02:18:58.72#ibcon#read 4, iclass 17, count 0 2006.286.02:18:58.72#ibcon#about to read 5, iclass 17, count 0 2006.286.02:18:58.72#ibcon#read 5, iclass 17, count 0 2006.286.02:18:58.72#ibcon#about to read 6, iclass 17, count 0 2006.286.02:18:58.72#ibcon#read 6, iclass 17, count 0 2006.286.02:18:58.72#ibcon#end of sib2, iclass 17, count 0 2006.286.02:18:58.72#ibcon#*after write, iclass 17, count 0 2006.286.02:18:58.72#ibcon#*before return 0, iclass 17, count 0 2006.286.02:18:58.72#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:18:58.72#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:18:58.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:18:58.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:18:58.72$vck44/vblo=3,649.99 2006.286.02:18:58.72#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.02:18:58.72#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.02:18:58.72#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:58.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:18:58.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:18:58.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:18:58.72#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:18:58.72#ibcon#first serial, iclass 19, count 0 2006.286.02:18:58.72#ibcon#enter sib2, iclass 19, count 0 2006.286.02:18:58.72#ibcon#flushed, iclass 19, count 0 2006.286.02:18:58.72#ibcon#about to write, iclass 19, count 0 2006.286.02:18:58.72#ibcon#wrote, iclass 19, count 0 2006.286.02:18:58.72#ibcon#about to read 3, iclass 19, count 0 2006.286.02:18:58.74#ibcon#read 3, iclass 19, count 0 2006.286.02:18:58.74#ibcon#about to read 4, iclass 19, count 0 2006.286.02:18:58.74#ibcon#read 4, iclass 19, count 0 2006.286.02:18:58.74#ibcon#about to read 5, iclass 19, count 0 2006.286.02:18:58.74#ibcon#read 5, iclass 19, count 0 2006.286.02:18:58.74#ibcon#about to read 6, iclass 19, count 0 2006.286.02:18:58.74#ibcon#read 6, iclass 19, count 0 2006.286.02:18:58.74#ibcon#end of sib2, iclass 19, count 0 2006.286.02:18:58.74#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:18:58.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:18:58.74#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.02:18:58.74#ibcon#*before write, iclass 19, count 0 2006.286.02:18:58.74#ibcon#enter sib2, iclass 19, count 0 2006.286.02:18:58.74#ibcon#flushed, iclass 19, count 0 2006.286.02:18:58.74#ibcon#about to write, iclass 19, count 0 2006.286.02:18:58.74#ibcon#wrote, iclass 19, count 0 2006.286.02:18:58.74#ibcon#about to read 3, iclass 19, count 0 2006.286.02:18:58.78#ibcon#read 3, iclass 19, count 0 2006.286.02:18:58.78#ibcon#about to read 4, iclass 19, count 0 2006.286.02:18:58.78#ibcon#read 4, iclass 19, count 0 2006.286.02:18:58.78#ibcon#about to read 5, iclass 19, count 0 2006.286.02:18:58.78#ibcon#read 5, iclass 19, count 0 2006.286.02:18:58.78#ibcon#about to read 6, iclass 19, count 0 2006.286.02:18:58.78#ibcon#read 6, iclass 19, count 0 2006.286.02:18:58.78#ibcon#end of sib2, iclass 19, count 0 2006.286.02:18:58.78#ibcon#*after write, iclass 19, count 0 2006.286.02:18:58.78#ibcon#*before return 0, iclass 19, count 0 2006.286.02:18:58.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:18:58.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:18:58.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:18:58.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:18:58.78$vck44/vb=3,4 2006.286.02:18:58.78#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.02:18:58.78#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.02:18:58.78#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:58.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:18:58.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:18:58.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:18:58.84#ibcon#enter wrdev, iclass 21, count 2 2006.286.02:18:58.84#ibcon#first serial, iclass 21, count 2 2006.286.02:18:58.84#ibcon#enter sib2, iclass 21, count 2 2006.286.02:18:58.84#ibcon#flushed, iclass 21, count 2 2006.286.02:18:58.84#ibcon#about to write, iclass 21, count 2 2006.286.02:18:58.84#ibcon#wrote, iclass 21, count 2 2006.286.02:18:58.84#ibcon#about to read 3, iclass 21, count 2 2006.286.02:18:58.86#ibcon#read 3, iclass 21, count 2 2006.286.02:18:58.86#ibcon#about to read 4, iclass 21, count 2 2006.286.02:18:58.86#ibcon#read 4, iclass 21, count 2 2006.286.02:18:58.86#ibcon#about to read 5, iclass 21, count 2 2006.286.02:18:58.86#ibcon#read 5, iclass 21, count 2 2006.286.02:18:58.86#ibcon#about to read 6, iclass 21, count 2 2006.286.02:18:58.86#ibcon#read 6, iclass 21, count 2 2006.286.02:18:58.86#ibcon#end of sib2, iclass 21, count 2 2006.286.02:18:58.86#ibcon#*mode == 0, iclass 21, count 2 2006.286.02:18:58.86#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.02:18:58.86#ibcon#[27=AT03-04\r\n] 2006.286.02:18:58.86#ibcon#*before write, iclass 21, count 2 2006.286.02:18:58.86#ibcon#enter sib2, iclass 21, count 2 2006.286.02:18:58.86#ibcon#flushed, iclass 21, count 2 2006.286.02:18:58.86#ibcon#about to write, iclass 21, count 2 2006.286.02:18:58.86#ibcon#wrote, iclass 21, count 2 2006.286.02:18:58.86#ibcon#about to read 3, iclass 21, count 2 2006.286.02:18:58.89#ibcon#read 3, iclass 21, count 2 2006.286.02:18:58.89#ibcon#about to read 4, iclass 21, count 2 2006.286.02:18:58.89#ibcon#read 4, iclass 21, count 2 2006.286.02:18:58.89#ibcon#about to read 5, iclass 21, count 2 2006.286.02:18:58.89#ibcon#read 5, iclass 21, count 2 2006.286.02:18:58.89#ibcon#about to read 6, iclass 21, count 2 2006.286.02:18:58.89#ibcon#read 6, iclass 21, count 2 2006.286.02:18:58.89#ibcon#end of sib2, iclass 21, count 2 2006.286.02:18:58.89#ibcon#*after write, iclass 21, count 2 2006.286.02:18:58.89#ibcon#*before return 0, iclass 21, count 2 2006.286.02:18:58.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:18:58.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:18:58.89#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.02:18:58.89#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:58.89#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:18:59.01#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:18:59.01#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:18:59.01#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:18:59.01#ibcon#first serial, iclass 21, count 0 2006.286.02:18:59.01#ibcon#enter sib2, iclass 21, count 0 2006.286.02:18:59.01#ibcon#flushed, iclass 21, count 0 2006.286.02:18:59.01#ibcon#about to write, iclass 21, count 0 2006.286.02:18:59.01#ibcon#wrote, iclass 21, count 0 2006.286.02:18:59.01#ibcon#about to read 3, iclass 21, count 0 2006.286.02:18:59.03#ibcon#read 3, iclass 21, count 0 2006.286.02:18:59.03#ibcon#about to read 4, iclass 21, count 0 2006.286.02:18:59.03#ibcon#read 4, iclass 21, count 0 2006.286.02:18:59.03#ibcon#about to read 5, iclass 21, count 0 2006.286.02:18:59.03#ibcon#read 5, iclass 21, count 0 2006.286.02:18:59.03#ibcon#about to read 6, iclass 21, count 0 2006.286.02:18:59.03#ibcon#read 6, iclass 21, count 0 2006.286.02:18:59.03#ibcon#end of sib2, iclass 21, count 0 2006.286.02:18:59.03#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:18:59.03#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:18:59.03#ibcon#[27=USB\r\n] 2006.286.02:18:59.03#ibcon#*before write, iclass 21, count 0 2006.286.02:18:59.03#ibcon#enter sib2, iclass 21, count 0 2006.286.02:18:59.03#ibcon#flushed, iclass 21, count 0 2006.286.02:18:59.03#ibcon#about to write, iclass 21, count 0 2006.286.02:18:59.03#ibcon#wrote, iclass 21, count 0 2006.286.02:18:59.03#ibcon#about to read 3, iclass 21, count 0 2006.286.02:18:59.06#ibcon#read 3, iclass 21, count 0 2006.286.02:18:59.06#ibcon#about to read 4, iclass 21, count 0 2006.286.02:18:59.06#ibcon#read 4, iclass 21, count 0 2006.286.02:18:59.06#ibcon#about to read 5, iclass 21, count 0 2006.286.02:18:59.06#ibcon#read 5, iclass 21, count 0 2006.286.02:18:59.06#ibcon#about to read 6, iclass 21, count 0 2006.286.02:18:59.06#ibcon#read 6, iclass 21, count 0 2006.286.02:18:59.06#ibcon#end of sib2, iclass 21, count 0 2006.286.02:18:59.06#ibcon#*after write, iclass 21, count 0 2006.286.02:18:59.06#ibcon#*before return 0, iclass 21, count 0 2006.286.02:18:59.06#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:18:59.06#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:18:59.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:18:59.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:18:59.06$vck44/vblo=4,679.99 2006.286.02:18:59.06#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.02:18:59.06#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.02:18:59.06#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:59.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:18:59.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:18:59.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:18:59.06#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:18:59.06#ibcon#first serial, iclass 23, count 0 2006.286.02:18:59.06#ibcon#enter sib2, iclass 23, count 0 2006.286.02:18:59.06#ibcon#flushed, iclass 23, count 0 2006.286.02:18:59.06#ibcon#about to write, iclass 23, count 0 2006.286.02:18:59.06#ibcon#wrote, iclass 23, count 0 2006.286.02:18:59.06#ibcon#about to read 3, iclass 23, count 0 2006.286.02:18:59.08#ibcon#read 3, iclass 23, count 0 2006.286.02:18:59.08#ibcon#about to read 4, iclass 23, count 0 2006.286.02:18:59.08#ibcon#read 4, iclass 23, count 0 2006.286.02:18:59.08#ibcon#about to read 5, iclass 23, count 0 2006.286.02:18:59.08#ibcon#read 5, iclass 23, count 0 2006.286.02:18:59.08#ibcon#about to read 6, iclass 23, count 0 2006.286.02:18:59.08#ibcon#read 6, iclass 23, count 0 2006.286.02:18:59.08#ibcon#end of sib2, iclass 23, count 0 2006.286.02:18:59.08#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:18:59.08#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:18:59.08#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.02:18:59.08#ibcon#*before write, iclass 23, count 0 2006.286.02:18:59.08#ibcon#enter sib2, iclass 23, count 0 2006.286.02:18:59.08#ibcon#flushed, iclass 23, count 0 2006.286.02:18:59.08#ibcon#about to write, iclass 23, count 0 2006.286.02:18:59.08#ibcon#wrote, iclass 23, count 0 2006.286.02:18:59.08#ibcon#about to read 3, iclass 23, count 0 2006.286.02:18:59.12#ibcon#read 3, iclass 23, count 0 2006.286.02:18:59.12#ibcon#about to read 4, iclass 23, count 0 2006.286.02:18:59.12#ibcon#read 4, iclass 23, count 0 2006.286.02:18:59.12#ibcon#about to read 5, iclass 23, count 0 2006.286.02:18:59.12#ibcon#read 5, iclass 23, count 0 2006.286.02:18:59.12#ibcon#about to read 6, iclass 23, count 0 2006.286.02:18:59.12#ibcon#read 6, iclass 23, count 0 2006.286.02:18:59.12#ibcon#end of sib2, iclass 23, count 0 2006.286.02:18:59.12#ibcon#*after write, iclass 23, count 0 2006.286.02:18:59.12#ibcon#*before return 0, iclass 23, count 0 2006.286.02:18:59.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:18:59.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:18:59.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:18:59.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:18:59.12$vck44/vb=4,5 2006.286.02:18:59.12#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.02:18:59.12#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.02:18:59.12#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:59.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:18:59.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:18:59.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:18:59.18#ibcon#enter wrdev, iclass 25, count 2 2006.286.02:18:59.18#ibcon#first serial, iclass 25, count 2 2006.286.02:18:59.18#ibcon#enter sib2, iclass 25, count 2 2006.286.02:18:59.18#ibcon#flushed, iclass 25, count 2 2006.286.02:18:59.18#ibcon#about to write, iclass 25, count 2 2006.286.02:18:59.18#ibcon#wrote, iclass 25, count 2 2006.286.02:18:59.18#ibcon#about to read 3, iclass 25, count 2 2006.286.02:18:59.20#ibcon#read 3, iclass 25, count 2 2006.286.02:18:59.20#ibcon#about to read 4, iclass 25, count 2 2006.286.02:18:59.20#ibcon#read 4, iclass 25, count 2 2006.286.02:18:59.20#ibcon#about to read 5, iclass 25, count 2 2006.286.02:18:59.20#ibcon#read 5, iclass 25, count 2 2006.286.02:18:59.20#ibcon#about to read 6, iclass 25, count 2 2006.286.02:18:59.20#ibcon#read 6, iclass 25, count 2 2006.286.02:18:59.20#ibcon#end of sib2, iclass 25, count 2 2006.286.02:18:59.20#ibcon#*mode == 0, iclass 25, count 2 2006.286.02:18:59.20#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.02:18:59.20#ibcon#[27=AT04-05\r\n] 2006.286.02:18:59.20#ibcon#*before write, iclass 25, count 2 2006.286.02:18:59.20#ibcon#enter sib2, iclass 25, count 2 2006.286.02:18:59.20#ibcon#flushed, iclass 25, count 2 2006.286.02:18:59.20#ibcon#about to write, iclass 25, count 2 2006.286.02:18:59.20#ibcon#wrote, iclass 25, count 2 2006.286.02:18:59.20#ibcon#about to read 3, iclass 25, count 2 2006.286.02:18:59.23#ibcon#read 3, iclass 25, count 2 2006.286.02:18:59.23#ibcon#about to read 4, iclass 25, count 2 2006.286.02:18:59.23#ibcon#read 4, iclass 25, count 2 2006.286.02:18:59.23#ibcon#about to read 5, iclass 25, count 2 2006.286.02:18:59.23#ibcon#read 5, iclass 25, count 2 2006.286.02:18:59.23#ibcon#about to read 6, iclass 25, count 2 2006.286.02:18:59.23#ibcon#read 6, iclass 25, count 2 2006.286.02:18:59.23#ibcon#end of sib2, iclass 25, count 2 2006.286.02:18:59.23#ibcon#*after write, iclass 25, count 2 2006.286.02:18:59.23#ibcon#*before return 0, iclass 25, count 2 2006.286.02:18:59.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:18:59.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:18:59.23#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.02:18:59.23#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:59.23#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:18:59.35#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:18:59.35#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:18:59.35#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:18:59.35#ibcon#first serial, iclass 25, count 0 2006.286.02:18:59.35#ibcon#enter sib2, iclass 25, count 0 2006.286.02:18:59.35#ibcon#flushed, iclass 25, count 0 2006.286.02:18:59.35#ibcon#about to write, iclass 25, count 0 2006.286.02:18:59.35#ibcon#wrote, iclass 25, count 0 2006.286.02:18:59.35#ibcon#about to read 3, iclass 25, count 0 2006.286.02:18:59.37#ibcon#read 3, iclass 25, count 0 2006.286.02:18:59.37#ibcon#about to read 4, iclass 25, count 0 2006.286.02:18:59.37#ibcon#read 4, iclass 25, count 0 2006.286.02:18:59.37#ibcon#about to read 5, iclass 25, count 0 2006.286.02:18:59.37#ibcon#read 5, iclass 25, count 0 2006.286.02:18:59.37#ibcon#about to read 6, iclass 25, count 0 2006.286.02:18:59.37#ibcon#read 6, iclass 25, count 0 2006.286.02:18:59.37#ibcon#end of sib2, iclass 25, count 0 2006.286.02:18:59.37#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:18:59.37#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:18:59.37#ibcon#[27=USB\r\n] 2006.286.02:18:59.37#ibcon#*before write, iclass 25, count 0 2006.286.02:18:59.37#ibcon#enter sib2, iclass 25, count 0 2006.286.02:18:59.37#ibcon#flushed, iclass 25, count 0 2006.286.02:18:59.37#ibcon#about to write, iclass 25, count 0 2006.286.02:18:59.37#ibcon#wrote, iclass 25, count 0 2006.286.02:18:59.37#ibcon#about to read 3, iclass 25, count 0 2006.286.02:18:59.40#ibcon#read 3, iclass 25, count 0 2006.286.02:18:59.40#ibcon#about to read 4, iclass 25, count 0 2006.286.02:18:59.40#ibcon#read 4, iclass 25, count 0 2006.286.02:18:59.40#ibcon#about to read 5, iclass 25, count 0 2006.286.02:18:59.40#ibcon#read 5, iclass 25, count 0 2006.286.02:18:59.40#ibcon#about to read 6, iclass 25, count 0 2006.286.02:18:59.40#ibcon#read 6, iclass 25, count 0 2006.286.02:18:59.40#ibcon#end of sib2, iclass 25, count 0 2006.286.02:18:59.40#ibcon#*after write, iclass 25, count 0 2006.286.02:18:59.40#ibcon#*before return 0, iclass 25, count 0 2006.286.02:18:59.40#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:18:59.40#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:18:59.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:18:59.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:18:59.40$vck44/vblo=5,709.99 2006.286.02:18:59.40#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.02:18:59.40#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.02:18:59.40#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:59.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:18:59.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:18:59.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:18:59.40#ibcon#enter wrdev, iclass 27, count 0 2006.286.02:18:59.40#ibcon#first serial, iclass 27, count 0 2006.286.02:18:59.40#ibcon#enter sib2, iclass 27, count 0 2006.286.02:18:59.40#ibcon#flushed, iclass 27, count 0 2006.286.02:18:59.40#ibcon#about to write, iclass 27, count 0 2006.286.02:18:59.40#ibcon#wrote, iclass 27, count 0 2006.286.02:18:59.40#ibcon#about to read 3, iclass 27, count 0 2006.286.02:18:59.42#ibcon#read 3, iclass 27, count 0 2006.286.02:18:59.42#ibcon#about to read 4, iclass 27, count 0 2006.286.02:18:59.42#ibcon#read 4, iclass 27, count 0 2006.286.02:18:59.42#ibcon#about to read 5, iclass 27, count 0 2006.286.02:18:59.42#ibcon#read 5, iclass 27, count 0 2006.286.02:18:59.42#ibcon#about to read 6, iclass 27, count 0 2006.286.02:18:59.42#ibcon#read 6, iclass 27, count 0 2006.286.02:18:59.42#ibcon#end of sib2, iclass 27, count 0 2006.286.02:18:59.42#ibcon#*mode == 0, iclass 27, count 0 2006.286.02:18:59.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.02:18:59.42#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.02:18:59.42#ibcon#*before write, iclass 27, count 0 2006.286.02:18:59.42#ibcon#enter sib2, iclass 27, count 0 2006.286.02:18:59.42#ibcon#flushed, iclass 27, count 0 2006.286.02:18:59.42#ibcon#about to write, iclass 27, count 0 2006.286.02:18:59.42#ibcon#wrote, iclass 27, count 0 2006.286.02:18:59.42#ibcon#about to read 3, iclass 27, count 0 2006.286.02:18:59.46#ibcon#read 3, iclass 27, count 0 2006.286.02:18:59.46#ibcon#about to read 4, iclass 27, count 0 2006.286.02:18:59.46#ibcon#read 4, iclass 27, count 0 2006.286.02:18:59.46#ibcon#about to read 5, iclass 27, count 0 2006.286.02:18:59.46#ibcon#read 5, iclass 27, count 0 2006.286.02:18:59.46#ibcon#about to read 6, iclass 27, count 0 2006.286.02:18:59.46#ibcon#read 6, iclass 27, count 0 2006.286.02:18:59.46#ibcon#end of sib2, iclass 27, count 0 2006.286.02:18:59.46#ibcon#*after write, iclass 27, count 0 2006.286.02:18:59.46#ibcon#*before return 0, iclass 27, count 0 2006.286.02:18:59.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:18:59.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:18:59.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.02:18:59.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.02:18:59.46$vck44/vb=5,4 2006.286.02:18:59.46#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.02:18:59.46#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.02:18:59.46#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:59.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:18:59.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:18:59.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:18:59.52#ibcon#enter wrdev, iclass 29, count 2 2006.286.02:18:59.52#ibcon#first serial, iclass 29, count 2 2006.286.02:18:59.52#ibcon#enter sib2, iclass 29, count 2 2006.286.02:18:59.52#ibcon#flushed, iclass 29, count 2 2006.286.02:18:59.52#ibcon#about to write, iclass 29, count 2 2006.286.02:18:59.52#ibcon#wrote, iclass 29, count 2 2006.286.02:18:59.52#ibcon#about to read 3, iclass 29, count 2 2006.286.02:18:59.54#ibcon#read 3, iclass 29, count 2 2006.286.02:18:59.54#ibcon#about to read 4, iclass 29, count 2 2006.286.02:18:59.54#ibcon#read 4, iclass 29, count 2 2006.286.02:18:59.54#ibcon#about to read 5, iclass 29, count 2 2006.286.02:18:59.54#ibcon#read 5, iclass 29, count 2 2006.286.02:18:59.54#ibcon#about to read 6, iclass 29, count 2 2006.286.02:18:59.54#ibcon#read 6, iclass 29, count 2 2006.286.02:18:59.54#ibcon#end of sib2, iclass 29, count 2 2006.286.02:18:59.54#ibcon#*mode == 0, iclass 29, count 2 2006.286.02:18:59.54#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.02:18:59.54#ibcon#[27=AT05-04\r\n] 2006.286.02:18:59.54#ibcon#*before write, iclass 29, count 2 2006.286.02:18:59.54#ibcon#enter sib2, iclass 29, count 2 2006.286.02:18:59.54#ibcon#flushed, iclass 29, count 2 2006.286.02:18:59.54#ibcon#about to write, iclass 29, count 2 2006.286.02:18:59.54#ibcon#wrote, iclass 29, count 2 2006.286.02:18:59.54#ibcon#about to read 3, iclass 29, count 2 2006.286.02:18:59.57#ibcon#read 3, iclass 29, count 2 2006.286.02:18:59.57#ibcon#about to read 4, iclass 29, count 2 2006.286.02:18:59.57#ibcon#read 4, iclass 29, count 2 2006.286.02:18:59.57#ibcon#about to read 5, iclass 29, count 2 2006.286.02:18:59.57#ibcon#read 5, iclass 29, count 2 2006.286.02:18:59.57#ibcon#about to read 6, iclass 29, count 2 2006.286.02:18:59.57#ibcon#read 6, iclass 29, count 2 2006.286.02:18:59.57#ibcon#end of sib2, iclass 29, count 2 2006.286.02:18:59.57#ibcon#*after write, iclass 29, count 2 2006.286.02:18:59.57#ibcon#*before return 0, iclass 29, count 2 2006.286.02:18:59.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:18:59.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:18:59.57#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.02:18:59.57#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:59.57#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:18:59.69#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:18:59.69#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:18:59.69#ibcon#enter wrdev, iclass 29, count 0 2006.286.02:18:59.69#ibcon#first serial, iclass 29, count 0 2006.286.02:18:59.69#ibcon#enter sib2, iclass 29, count 0 2006.286.02:18:59.69#ibcon#flushed, iclass 29, count 0 2006.286.02:18:59.69#ibcon#about to write, iclass 29, count 0 2006.286.02:18:59.69#ibcon#wrote, iclass 29, count 0 2006.286.02:18:59.69#ibcon#about to read 3, iclass 29, count 0 2006.286.02:18:59.71#ibcon#read 3, iclass 29, count 0 2006.286.02:18:59.71#ibcon#about to read 4, iclass 29, count 0 2006.286.02:18:59.71#ibcon#read 4, iclass 29, count 0 2006.286.02:18:59.71#ibcon#about to read 5, iclass 29, count 0 2006.286.02:18:59.71#ibcon#read 5, iclass 29, count 0 2006.286.02:18:59.71#ibcon#about to read 6, iclass 29, count 0 2006.286.02:18:59.71#ibcon#read 6, iclass 29, count 0 2006.286.02:18:59.71#ibcon#end of sib2, iclass 29, count 0 2006.286.02:18:59.71#ibcon#*mode == 0, iclass 29, count 0 2006.286.02:18:59.71#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.02:18:59.71#ibcon#[27=USB\r\n] 2006.286.02:18:59.71#ibcon#*before write, iclass 29, count 0 2006.286.02:18:59.71#ibcon#enter sib2, iclass 29, count 0 2006.286.02:18:59.71#ibcon#flushed, iclass 29, count 0 2006.286.02:18:59.71#ibcon#about to write, iclass 29, count 0 2006.286.02:18:59.71#ibcon#wrote, iclass 29, count 0 2006.286.02:18:59.71#ibcon#about to read 3, iclass 29, count 0 2006.286.02:18:59.74#ibcon#read 3, iclass 29, count 0 2006.286.02:18:59.74#ibcon#about to read 4, iclass 29, count 0 2006.286.02:18:59.74#ibcon#read 4, iclass 29, count 0 2006.286.02:18:59.74#ibcon#about to read 5, iclass 29, count 0 2006.286.02:18:59.74#ibcon#read 5, iclass 29, count 0 2006.286.02:18:59.74#ibcon#about to read 6, iclass 29, count 0 2006.286.02:18:59.74#ibcon#read 6, iclass 29, count 0 2006.286.02:18:59.74#ibcon#end of sib2, iclass 29, count 0 2006.286.02:18:59.74#ibcon#*after write, iclass 29, count 0 2006.286.02:18:59.74#ibcon#*before return 0, iclass 29, count 0 2006.286.02:18:59.74#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:18:59.74#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:18:59.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.02:18:59.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.02:18:59.74$vck44/vblo=6,719.99 2006.286.02:18:59.74#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.02:18:59.74#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.02:18:59.74#ibcon#ireg 17 cls_cnt 0 2006.286.02:18:59.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:18:59.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:18:59.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:18:59.74#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:18:59.74#ibcon#first serial, iclass 31, count 0 2006.286.02:18:59.74#ibcon#enter sib2, iclass 31, count 0 2006.286.02:18:59.74#ibcon#flushed, iclass 31, count 0 2006.286.02:18:59.74#ibcon#about to write, iclass 31, count 0 2006.286.02:18:59.74#ibcon#wrote, iclass 31, count 0 2006.286.02:18:59.74#ibcon#about to read 3, iclass 31, count 0 2006.286.02:18:59.76#ibcon#read 3, iclass 31, count 0 2006.286.02:18:59.76#ibcon#about to read 4, iclass 31, count 0 2006.286.02:18:59.76#ibcon#read 4, iclass 31, count 0 2006.286.02:18:59.76#ibcon#about to read 5, iclass 31, count 0 2006.286.02:18:59.76#ibcon#read 5, iclass 31, count 0 2006.286.02:18:59.76#ibcon#about to read 6, iclass 31, count 0 2006.286.02:18:59.76#ibcon#read 6, iclass 31, count 0 2006.286.02:18:59.76#ibcon#end of sib2, iclass 31, count 0 2006.286.02:18:59.76#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:18:59.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:18:59.76#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.02:18:59.76#ibcon#*before write, iclass 31, count 0 2006.286.02:18:59.76#ibcon#enter sib2, iclass 31, count 0 2006.286.02:18:59.76#ibcon#flushed, iclass 31, count 0 2006.286.02:18:59.76#ibcon#about to write, iclass 31, count 0 2006.286.02:18:59.76#ibcon#wrote, iclass 31, count 0 2006.286.02:18:59.76#ibcon#about to read 3, iclass 31, count 0 2006.286.02:18:59.80#ibcon#read 3, iclass 31, count 0 2006.286.02:18:59.80#ibcon#about to read 4, iclass 31, count 0 2006.286.02:18:59.80#ibcon#read 4, iclass 31, count 0 2006.286.02:18:59.80#ibcon#about to read 5, iclass 31, count 0 2006.286.02:18:59.80#ibcon#read 5, iclass 31, count 0 2006.286.02:18:59.80#ibcon#about to read 6, iclass 31, count 0 2006.286.02:18:59.80#ibcon#read 6, iclass 31, count 0 2006.286.02:18:59.80#ibcon#end of sib2, iclass 31, count 0 2006.286.02:18:59.80#ibcon#*after write, iclass 31, count 0 2006.286.02:18:59.80#ibcon#*before return 0, iclass 31, count 0 2006.286.02:18:59.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:18:59.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:18:59.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:18:59.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:18:59.80$vck44/vb=6,3 2006.286.02:18:59.80#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.02:18:59.80#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.02:18:59.80#ibcon#ireg 11 cls_cnt 2 2006.286.02:18:59.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:18:59.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:18:59.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:18:59.86#ibcon#enter wrdev, iclass 33, count 2 2006.286.02:18:59.86#ibcon#first serial, iclass 33, count 2 2006.286.02:18:59.86#ibcon#enter sib2, iclass 33, count 2 2006.286.02:18:59.86#ibcon#flushed, iclass 33, count 2 2006.286.02:18:59.86#ibcon#about to write, iclass 33, count 2 2006.286.02:18:59.86#ibcon#wrote, iclass 33, count 2 2006.286.02:18:59.86#ibcon#about to read 3, iclass 33, count 2 2006.286.02:18:59.88#ibcon#read 3, iclass 33, count 2 2006.286.02:18:59.88#ibcon#about to read 4, iclass 33, count 2 2006.286.02:18:59.88#ibcon#read 4, iclass 33, count 2 2006.286.02:18:59.88#ibcon#about to read 5, iclass 33, count 2 2006.286.02:18:59.88#ibcon#read 5, iclass 33, count 2 2006.286.02:18:59.88#ibcon#about to read 6, iclass 33, count 2 2006.286.02:18:59.88#ibcon#read 6, iclass 33, count 2 2006.286.02:18:59.88#ibcon#end of sib2, iclass 33, count 2 2006.286.02:18:59.88#ibcon#*mode == 0, iclass 33, count 2 2006.286.02:18:59.88#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.02:18:59.88#ibcon#[27=AT06-03\r\n] 2006.286.02:18:59.88#ibcon#*before write, iclass 33, count 2 2006.286.02:18:59.88#ibcon#enter sib2, iclass 33, count 2 2006.286.02:18:59.88#ibcon#flushed, iclass 33, count 2 2006.286.02:18:59.88#ibcon#about to write, iclass 33, count 2 2006.286.02:18:59.88#ibcon#wrote, iclass 33, count 2 2006.286.02:18:59.88#ibcon#about to read 3, iclass 33, count 2 2006.286.02:18:59.91#ibcon#read 3, iclass 33, count 2 2006.286.02:18:59.91#ibcon#about to read 4, iclass 33, count 2 2006.286.02:18:59.91#ibcon#read 4, iclass 33, count 2 2006.286.02:18:59.91#ibcon#about to read 5, iclass 33, count 2 2006.286.02:18:59.91#ibcon#read 5, iclass 33, count 2 2006.286.02:18:59.91#ibcon#about to read 6, iclass 33, count 2 2006.286.02:18:59.91#ibcon#read 6, iclass 33, count 2 2006.286.02:18:59.91#ibcon#end of sib2, iclass 33, count 2 2006.286.02:18:59.91#ibcon#*after write, iclass 33, count 2 2006.286.02:18:59.91#ibcon#*before return 0, iclass 33, count 2 2006.286.02:18:59.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:18:59.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:18:59.91#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.02:18:59.91#ibcon#ireg 7 cls_cnt 0 2006.286.02:18:59.91#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:19:00.03#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:19:00.03#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:19:00.03#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:19:00.03#ibcon#first serial, iclass 33, count 0 2006.286.02:19:00.03#ibcon#enter sib2, iclass 33, count 0 2006.286.02:19:00.03#ibcon#flushed, iclass 33, count 0 2006.286.02:19:00.03#ibcon#about to write, iclass 33, count 0 2006.286.02:19:00.03#ibcon#wrote, iclass 33, count 0 2006.286.02:19:00.03#ibcon#about to read 3, iclass 33, count 0 2006.286.02:19:00.05#ibcon#read 3, iclass 33, count 0 2006.286.02:19:00.05#ibcon#about to read 4, iclass 33, count 0 2006.286.02:19:00.05#ibcon#read 4, iclass 33, count 0 2006.286.02:19:00.05#ibcon#about to read 5, iclass 33, count 0 2006.286.02:19:00.05#ibcon#read 5, iclass 33, count 0 2006.286.02:19:00.05#ibcon#about to read 6, iclass 33, count 0 2006.286.02:19:00.05#ibcon#read 6, iclass 33, count 0 2006.286.02:19:00.05#ibcon#end of sib2, iclass 33, count 0 2006.286.02:19:00.05#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:19:00.05#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:19:00.05#ibcon#[27=USB\r\n] 2006.286.02:19:00.05#ibcon#*before write, iclass 33, count 0 2006.286.02:19:00.05#ibcon#enter sib2, iclass 33, count 0 2006.286.02:19:00.05#ibcon#flushed, iclass 33, count 0 2006.286.02:19:00.05#ibcon#about to write, iclass 33, count 0 2006.286.02:19:00.05#ibcon#wrote, iclass 33, count 0 2006.286.02:19:00.05#ibcon#about to read 3, iclass 33, count 0 2006.286.02:19:00.08#ibcon#read 3, iclass 33, count 0 2006.286.02:19:00.08#ibcon#about to read 4, iclass 33, count 0 2006.286.02:19:00.08#ibcon#read 4, iclass 33, count 0 2006.286.02:19:00.08#ibcon#about to read 5, iclass 33, count 0 2006.286.02:19:00.08#ibcon#read 5, iclass 33, count 0 2006.286.02:19:00.08#ibcon#about to read 6, iclass 33, count 0 2006.286.02:19:00.08#ibcon#read 6, iclass 33, count 0 2006.286.02:19:00.08#ibcon#end of sib2, iclass 33, count 0 2006.286.02:19:00.08#ibcon#*after write, iclass 33, count 0 2006.286.02:19:00.08#ibcon#*before return 0, iclass 33, count 0 2006.286.02:19:00.08#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:19:00.08#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:19:00.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:19:00.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:19:00.08$vck44/vblo=7,734.99 2006.286.02:19:00.08#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.02:19:00.08#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.02:19:00.08#ibcon#ireg 17 cls_cnt 0 2006.286.02:19:00.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:19:00.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:19:00.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:19:00.08#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:19:00.08#ibcon#first serial, iclass 35, count 0 2006.286.02:19:00.08#ibcon#enter sib2, iclass 35, count 0 2006.286.02:19:00.08#ibcon#flushed, iclass 35, count 0 2006.286.02:19:00.08#ibcon#about to write, iclass 35, count 0 2006.286.02:19:00.08#ibcon#wrote, iclass 35, count 0 2006.286.02:19:00.08#ibcon#about to read 3, iclass 35, count 0 2006.286.02:19:00.10#ibcon#read 3, iclass 35, count 0 2006.286.02:19:00.10#ibcon#about to read 4, iclass 35, count 0 2006.286.02:19:00.10#ibcon#read 4, iclass 35, count 0 2006.286.02:19:00.10#ibcon#about to read 5, iclass 35, count 0 2006.286.02:19:00.10#ibcon#read 5, iclass 35, count 0 2006.286.02:19:00.10#ibcon#about to read 6, iclass 35, count 0 2006.286.02:19:00.10#ibcon#read 6, iclass 35, count 0 2006.286.02:19:00.10#ibcon#end of sib2, iclass 35, count 0 2006.286.02:19:00.10#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:19:00.10#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:19:00.10#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.02:19:00.10#ibcon#*before write, iclass 35, count 0 2006.286.02:19:00.10#ibcon#enter sib2, iclass 35, count 0 2006.286.02:19:00.10#ibcon#flushed, iclass 35, count 0 2006.286.02:19:00.10#ibcon#about to write, iclass 35, count 0 2006.286.02:19:00.10#ibcon#wrote, iclass 35, count 0 2006.286.02:19:00.10#ibcon#about to read 3, iclass 35, count 0 2006.286.02:19:00.14#ibcon#read 3, iclass 35, count 0 2006.286.02:19:00.14#ibcon#about to read 4, iclass 35, count 0 2006.286.02:19:00.14#ibcon#read 4, iclass 35, count 0 2006.286.02:19:00.14#ibcon#about to read 5, iclass 35, count 0 2006.286.02:19:00.14#ibcon#read 5, iclass 35, count 0 2006.286.02:19:00.14#ibcon#about to read 6, iclass 35, count 0 2006.286.02:19:00.14#ibcon#read 6, iclass 35, count 0 2006.286.02:19:00.14#ibcon#end of sib2, iclass 35, count 0 2006.286.02:19:00.14#ibcon#*after write, iclass 35, count 0 2006.286.02:19:00.14#ibcon#*before return 0, iclass 35, count 0 2006.286.02:19:00.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:19:00.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:19:00.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:19:00.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:19:00.14$vck44/vb=7,4 2006.286.02:19:00.14#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.02:19:00.14#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.02:19:00.14#ibcon#ireg 11 cls_cnt 2 2006.286.02:19:00.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:19:00.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:19:00.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:19:00.20#ibcon#enter wrdev, iclass 37, count 2 2006.286.02:19:00.20#ibcon#first serial, iclass 37, count 2 2006.286.02:19:00.20#ibcon#enter sib2, iclass 37, count 2 2006.286.02:19:00.20#ibcon#flushed, iclass 37, count 2 2006.286.02:19:00.20#ibcon#about to write, iclass 37, count 2 2006.286.02:19:00.20#ibcon#wrote, iclass 37, count 2 2006.286.02:19:00.20#ibcon#about to read 3, iclass 37, count 2 2006.286.02:19:00.22#ibcon#read 3, iclass 37, count 2 2006.286.02:19:00.22#ibcon#about to read 4, iclass 37, count 2 2006.286.02:19:00.22#ibcon#read 4, iclass 37, count 2 2006.286.02:19:00.22#ibcon#about to read 5, iclass 37, count 2 2006.286.02:19:00.22#ibcon#read 5, iclass 37, count 2 2006.286.02:19:00.22#ibcon#about to read 6, iclass 37, count 2 2006.286.02:19:00.22#ibcon#read 6, iclass 37, count 2 2006.286.02:19:00.22#ibcon#end of sib2, iclass 37, count 2 2006.286.02:19:00.22#ibcon#*mode == 0, iclass 37, count 2 2006.286.02:19:00.22#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.02:19:00.22#ibcon#[27=AT07-04\r\n] 2006.286.02:19:00.22#ibcon#*before write, iclass 37, count 2 2006.286.02:19:00.22#ibcon#enter sib2, iclass 37, count 2 2006.286.02:19:00.22#ibcon#flushed, iclass 37, count 2 2006.286.02:19:00.22#ibcon#about to write, iclass 37, count 2 2006.286.02:19:00.22#ibcon#wrote, iclass 37, count 2 2006.286.02:19:00.22#ibcon#about to read 3, iclass 37, count 2 2006.286.02:19:00.25#ibcon#read 3, iclass 37, count 2 2006.286.02:19:00.25#ibcon#about to read 4, iclass 37, count 2 2006.286.02:19:00.25#ibcon#read 4, iclass 37, count 2 2006.286.02:19:00.25#ibcon#about to read 5, iclass 37, count 2 2006.286.02:19:00.25#ibcon#read 5, iclass 37, count 2 2006.286.02:19:00.25#ibcon#about to read 6, iclass 37, count 2 2006.286.02:19:00.25#ibcon#read 6, iclass 37, count 2 2006.286.02:19:00.25#ibcon#end of sib2, iclass 37, count 2 2006.286.02:19:00.25#ibcon#*after write, iclass 37, count 2 2006.286.02:19:00.25#ibcon#*before return 0, iclass 37, count 2 2006.286.02:19:00.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:19:00.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:19:00.25#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.02:19:00.25#ibcon#ireg 7 cls_cnt 0 2006.286.02:19:00.25#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:19:00.37#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:19:00.37#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:19:00.37#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:19:00.37#ibcon#first serial, iclass 37, count 0 2006.286.02:19:00.37#ibcon#enter sib2, iclass 37, count 0 2006.286.02:19:00.37#ibcon#flushed, iclass 37, count 0 2006.286.02:19:00.37#ibcon#about to write, iclass 37, count 0 2006.286.02:19:00.37#ibcon#wrote, iclass 37, count 0 2006.286.02:19:00.37#ibcon#about to read 3, iclass 37, count 0 2006.286.02:19:00.39#ibcon#read 3, iclass 37, count 0 2006.286.02:19:00.39#ibcon#about to read 4, iclass 37, count 0 2006.286.02:19:00.39#ibcon#read 4, iclass 37, count 0 2006.286.02:19:00.39#ibcon#about to read 5, iclass 37, count 0 2006.286.02:19:00.39#ibcon#read 5, iclass 37, count 0 2006.286.02:19:00.39#ibcon#about to read 6, iclass 37, count 0 2006.286.02:19:00.39#ibcon#read 6, iclass 37, count 0 2006.286.02:19:00.39#ibcon#end of sib2, iclass 37, count 0 2006.286.02:19:00.39#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:19:00.39#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:19:00.39#ibcon#[27=USB\r\n] 2006.286.02:19:00.39#ibcon#*before write, iclass 37, count 0 2006.286.02:19:00.39#ibcon#enter sib2, iclass 37, count 0 2006.286.02:19:00.39#ibcon#flushed, iclass 37, count 0 2006.286.02:19:00.39#ibcon#about to write, iclass 37, count 0 2006.286.02:19:00.39#ibcon#wrote, iclass 37, count 0 2006.286.02:19:00.39#ibcon#about to read 3, iclass 37, count 0 2006.286.02:19:00.42#ibcon#read 3, iclass 37, count 0 2006.286.02:19:00.42#ibcon#about to read 4, iclass 37, count 0 2006.286.02:19:00.42#ibcon#read 4, iclass 37, count 0 2006.286.02:19:00.42#ibcon#about to read 5, iclass 37, count 0 2006.286.02:19:00.42#ibcon#read 5, iclass 37, count 0 2006.286.02:19:00.42#ibcon#about to read 6, iclass 37, count 0 2006.286.02:19:00.42#ibcon#read 6, iclass 37, count 0 2006.286.02:19:00.42#ibcon#end of sib2, iclass 37, count 0 2006.286.02:19:00.42#ibcon#*after write, iclass 37, count 0 2006.286.02:19:00.42#ibcon#*before return 0, iclass 37, count 0 2006.286.02:19:00.42#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:19:00.42#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:19:00.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:19:00.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:19:00.42$vck44/vblo=8,744.99 2006.286.02:19:00.42#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.02:19:00.42#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.02:19:00.42#ibcon#ireg 17 cls_cnt 0 2006.286.02:19:00.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:19:00.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:19:00.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:19:00.42#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:19:00.42#ibcon#first serial, iclass 39, count 0 2006.286.02:19:00.42#ibcon#enter sib2, iclass 39, count 0 2006.286.02:19:00.42#ibcon#flushed, iclass 39, count 0 2006.286.02:19:00.42#ibcon#about to write, iclass 39, count 0 2006.286.02:19:00.42#ibcon#wrote, iclass 39, count 0 2006.286.02:19:00.42#ibcon#about to read 3, iclass 39, count 0 2006.286.02:19:00.44#ibcon#read 3, iclass 39, count 0 2006.286.02:19:00.44#ibcon#about to read 4, iclass 39, count 0 2006.286.02:19:00.44#ibcon#read 4, iclass 39, count 0 2006.286.02:19:00.44#ibcon#about to read 5, iclass 39, count 0 2006.286.02:19:00.44#ibcon#read 5, iclass 39, count 0 2006.286.02:19:00.44#ibcon#about to read 6, iclass 39, count 0 2006.286.02:19:00.44#ibcon#read 6, iclass 39, count 0 2006.286.02:19:00.44#ibcon#end of sib2, iclass 39, count 0 2006.286.02:19:00.44#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:19:00.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:19:00.44#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.02:19:00.44#ibcon#*before write, iclass 39, count 0 2006.286.02:19:00.44#ibcon#enter sib2, iclass 39, count 0 2006.286.02:19:00.44#ibcon#flushed, iclass 39, count 0 2006.286.02:19:00.44#ibcon#about to write, iclass 39, count 0 2006.286.02:19:00.44#ibcon#wrote, iclass 39, count 0 2006.286.02:19:00.44#ibcon#about to read 3, iclass 39, count 0 2006.286.02:19:00.48#ibcon#read 3, iclass 39, count 0 2006.286.02:19:00.48#ibcon#about to read 4, iclass 39, count 0 2006.286.02:19:00.48#ibcon#read 4, iclass 39, count 0 2006.286.02:19:00.48#ibcon#about to read 5, iclass 39, count 0 2006.286.02:19:00.48#ibcon#read 5, iclass 39, count 0 2006.286.02:19:00.48#ibcon#about to read 6, iclass 39, count 0 2006.286.02:19:00.48#ibcon#read 6, iclass 39, count 0 2006.286.02:19:00.48#ibcon#end of sib2, iclass 39, count 0 2006.286.02:19:00.48#ibcon#*after write, iclass 39, count 0 2006.286.02:19:00.48#ibcon#*before return 0, iclass 39, count 0 2006.286.02:19:00.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:19:00.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:19:00.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:19:00.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:19:00.48$vck44/vb=8,4 2006.286.02:19:00.48#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.02:19:00.48#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.02:19:00.48#ibcon#ireg 11 cls_cnt 2 2006.286.02:19:00.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:19:00.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:19:00.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:19:00.54#ibcon#enter wrdev, iclass 3, count 2 2006.286.02:19:00.54#ibcon#first serial, iclass 3, count 2 2006.286.02:19:00.54#ibcon#enter sib2, iclass 3, count 2 2006.286.02:19:00.54#ibcon#flushed, iclass 3, count 2 2006.286.02:19:00.54#ibcon#about to write, iclass 3, count 2 2006.286.02:19:00.54#ibcon#wrote, iclass 3, count 2 2006.286.02:19:00.54#ibcon#about to read 3, iclass 3, count 2 2006.286.02:19:00.56#ibcon#read 3, iclass 3, count 2 2006.286.02:19:00.56#ibcon#about to read 4, iclass 3, count 2 2006.286.02:19:00.56#ibcon#read 4, iclass 3, count 2 2006.286.02:19:00.56#ibcon#about to read 5, iclass 3, count 2 2006.286.02:19:00.56#ibcon#read 5, iclass 3, count 2 2006.286.02:19:00.56#ibcon#about to read 6, iclass 3, count 2 2006.286.02:19:00.56#ibcon#read 6, iclass 3, count 2 2006.286.02:19:00.56#ibcon#end of sib2, iclass 3, count 2 2006.286.02:19:00.56#ibcon#*mode == 0, iclass 3, count 2 2006.286.02:19:00.56#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.02:19:00.56#ibcon#[27=AT08-04\r\n] 2006.286.02:19:00.56#ibcon#*before write, iclass 3, count 2 2006.286.02:19:00.56#ibcon#enter sib2, iclass 3, count 2 2006.286.02:19:00.56#ibcon#flushed, iclass 3, count 2 2006.286.02:19:00.56#ibcon#about to write, iclass 3, count 2 2006.286.02:19:00.56#ibcon#wrote, iclass 3, count 2 2006.286.02:19:00.56#ibcon#about to read 3, iclass 3, count 2 2006.286.02:19:00.59#ibcon#read 3, iclass 3, count 2 2006.286.02:19:00.59#ibcon#about to read 4, iclass 3, count 2 2006.286.02:19:00.59#ibcon#read 4, iclass 3, count 2 2006.286.02:19:00.59#ibcon#about to read 5, iclass 3, count 2 2006.286.02:19:00.59#ibcon#read 5, iclass 3, count 2 2006.286.02:19:00.59#ibcon#about to read 6, iclass 3, count 2 2006.286.02:19:00.59#ibcon#read 6, iclass 3, count 2 2006.286.02:19:00.59#ibcon#end of sib2, iclass 3, count 2 2006.286.02:19:00.59#ibcon#*after write, iclass 3, count 2 2006.286.02:19:00.59#ibcon#*before return 0, iclass 3, count 2 2006.286.02:19:00.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:19:00.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:19:00.59#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.02:19:00.59#ibcon#ireg 7 cls_cnt 0 2006.286.02:19:00.59#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:19:00.71#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:19:00.71#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:19:00.71#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:19:00.71#ibcon#first serial, iclass 3, count 0 2006.286.02:19:00.71#ibcon#enter sib2, iclass 3, count 0 2006.286.02:19:00.71#ibcon#flushed, iclass 3, count 0 2006.286.02:19:00.71#ibcon#about to write, iclass 3, count 0 2006.286.02:19:00.71#ibcon#wrote, iclass 3, count 0 2006.286.02:19:00.71#ibcon#about to read 3, iclass 3, count 0 2006.286.02:19:00.73#ibcon#read 3, iclass 3, count 0 2006.286.02:19:00.73#ibcon#about to read 4, iclass 3, count 0 2006.286.02:19:00.73#ibcon#read 4, iclass 3, count 0 2006.286.02:19:00.73#ibcon#about to read 5, iclass 3, count 0 2006.286.02:19:00.73#ibcon#read 5, iclass 3, count 0 2006.286.02:19:00.73#ibcon#about to read 6, iclass 3, count 0 2006.286.02:19:00.73#ibcon#read 6, iclass 3, count 0 2006.286.02:19:00.73#ibcon#end of sib2, iclass 3, count 0 2006.286.02:19:00.73#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:19:00.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:19:00.73#ibcon#[27=USB\r\n] 2006.286.02:19:00.73#ibcon#*before write, iclass 3, count 0 2006.286.02:19:00.73#ibcon#enter sib2, iclass 3, count 0 2006.286.02:19:00.73#ibcon#flushed, iclass 3, count 0 2006.286.02:19:00.73#ibcon#about to write, iclass 3, count 0 2006.286.02:19:00.73#ibcon#wrote, iclass 3, count 0 2006.286.02:19:00.73#ibcon#about to read 3, iclass 3, count 0 2006.286.02:19:00.76#ibcon#read 3, iclass 3, count 0 2006.286.02:19:00.76#ibcon#about to read 4, iclass 3, count 0 2006.286.02:19:00.76#ibcon#read 4, iclass 3, count 0 2006.286.02:19:00.76#ibcon#about to read 5, iclass 3, count 0 2006.286.02:19:00.76#ibcon#read 5, iclass 3, count 0 2006.286.02:19:00.76#ibcon#about to read 6, iclass 3, count 0 2006.286.02:19:00.76#ibcon#read 6, iclass 3, count 0 2006.286.02:19:00.76#ibcon#end of sib2, iclass 3, count 0 2006.286.02:19:00.76#ibcon#*after write, iclass 3, count 0 2006.286.02:19:00.76#ibcon#*before return 0, iclass 3, count 0 2006.286.02:19:00.76#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:19:00.76#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:19:00.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:19:00.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:19:00.76$vck44/vabw=wide 2006.286.02:19:00.76#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.02:19:00.76#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.02:19:00.76#ibcon#ireg 8 cls_cnt 0 2006.286.02:19:00.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:19:00.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:19:00.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:19:00.76#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:19:00.76#ibcon#first serial, iclass 5, count 0 2006.286.02:19:00.76#ibcon#enter sib2, iclass 5, count 0 2006.286.02:19:00.76#ibcon#flushed, iclass 5, count 0 2006.286.02:19:00.76#ibcon#about to write, iclass 5, count 0 2006.286.02:19:00.76#ibcon#wrote, iclass 5, count 0 2006.286.02:19:00.76#ibcon#about to read 3, iclass 5, count 0 2006.286.02:19:00.78#ibcon#read 3, iclass 5, count 0 2006.286.02:19:00.78#ibcon#about to read 4, iclass 5, count 0 2006.286.02:19:00.78#ibcon#read 4, iclass 5, count 0 2006.286.02:19:00.78#ibcon#about to read 5, iclass 5, count 0 2006.286.02:19:00.78#ibcon#read 5, iclass 5, count 0 2006.286.02:19:00.78#ibcon#about to read 6, iclass 5, count 0 2006.286.02:19:00.78#ibcon#read 6, iclass 5, count 0 2006.286.02:19:00.78#ibcon#end of sib2, iclass 5, count 0 2006.286.02:19:00.78#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:19:00.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:19:00.78#ibcon#[25=BW32\r\n] 2006.286.02:19:00.78#ibcon#*before write, iclass 5, count 0 2006.286.02:19:00.78#ibcon#enter sib2, iclass 5, count 0 2006.286.02:19:00.78#ibcon#flushed, iclass 5, count 0 2006.286.02:19:00.78#ibcon#about to write, iclass 5, count 0 2006.286.02:19:00.78#ibcon#wrote, iclass 5, count 0 2006.286.02:19:00.78#ibcon#about to read 3, iclass 5, count 0 2006.286.02:19:00.81#ibcon#read 3, iclass 5, count 0 2006.286.02:19:00.81#ibcon#about to read 4, iclass 5, count 0 2006.286.02:19:00.81#ibcon#read 4, iclass 5, count 0 2006.286.02:19:00.81#ibcon#about to read 5, iclass 5, count 0 2006.286.02:19:00.81#ibcon#read 5, iclass 5, count 0 2006.286.02:19:00.81#ibcon#about to read 6, iclass 5, count 0 2006.286.02:19:00.81#ibcon#read 6, iclass 5, count 0 2006.286.02:19:00.81#ibcon#end of sib2, iclass 5, count 0 2006.286.02:19:00.81#ibcon#*after write, iclass 5, count 0 2006.286.02:19:00.81#ibcon#*before return 0, iclass 5, count 0 2006.286.02:19:00.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:19:00.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:19:00.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:19:00.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:19:00.81$vck44/vbbw=wide 2006.286.02:19:00.81#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.02:19:00.81#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.02:19:00.81#ibcon#ireg 8 cls_cnt 0 2006.286.02:19:00.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:19:00.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:19:00.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:19:00.88#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:19:00.88#ibcon#first serial, iclass 7, count 0 2006.286.02:19:00.88#ibcon#enter sib2, iclass 7, count 0 2006.286.02:19:00.88#ibcon#flushed, iclass 7, count 0 2006.286.02:19:00.88#ibcon#about to write, iclass 7, count 0 2006.286.02:19:00.88#ibcon#wrote, iclass 7, count 0 2006.286.02:19:00.88#ibcon#about to read 3, iclass 7, count 0 2006.286.02:19:00.90#ibcon#read 3, iclass 7, count 0 2006.286.02:19:00.90#ibcon#about to read 4, iclass 7, count 0 2006.286.02:19:00.90#ibcon#read 4, iclass 7, count 0 2006.286.02:19:00.90#ibcon#about to read 5, iclass 7, count 0 2006.286.02:19:00.90#ibcon#read 5, iclass 7, count 0 2006.286.02:19:00.90#ibcon#about to read 6, iclass 7, count 0 2006.286.02:19:00.90#ibcon#read 6, iclass 7, count 0 2006.286.02:19:00.90#ibcon#end of sib2, iclass 7, count 0 2006.286.02:19:00.90#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:19:00.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:19:00.90#ibcon#[27=BW32\r\n] 2006.286.02:19:00.90#ibcon#*before write, iclass 7, count 0 2006.286.02:19:00.90#ibcon#enter sib2, iclass 7, count 0 2006.286.02:19:00.90#ibcon#flushed, iclass 7, count 0 2006.286.02:19:00.90#ibcon#about to write, iclass 7, count 0 2006.286.02:19:00.90#ibcon#wrote, iclass 7, count 0 2006.286.02:19:00.90#ibcon#about to read 3, iclass 7, count 0 2006.286.02:19:00.93#ibcon#read 3, iclass 7, count 0 2006.286.02:19:00.93#ibcon#about to read 4, iclass 7, count 0 2006.286.02:19:00.93#ibcon#read 4, iclass 7, count 0 2006.286.02:19:00.93#ibcon#about to read 5, iclass 7, count 0 2006.286.02:19:00.93#ibcon#read 5, iclass 7, count 0 2006.286.02:19:00.93#ibcon#about to read 6, iclass 7, count 0 2006.286.02:19:00.93#ibcon#read 6, iclass 7, count 0 2006.286.02:19:00.93#ibcon#end of sib2, iclass 7, count 0 2006.286.02:19:00.93#ibcon#*after write, iclass 7, count 0 2006.286.02:19:00.93#ibcon#*before return 0, iclass 7, count 0 2006.286.02:19:00.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:19:00.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:19:00.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:19:00.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:19:00.93$setupk4/ifdk4 2006.286.02:19:00.93$ifdk4/lo= 2006.286.02:19:00.93$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.02:19:00.93$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.02:19:00.93$ifdk4/patch= 2006.286.02:19:00.93$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.02:19:00.93$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.02:19:00.93$setupk4/!*+20s 2006.286.02:19:02.96#abcon#<5=/04 2.9 5.9 21.36 801015.9\r\n> 2006.286.02:19:02.98#abcon#{5=INTERFACE CLEAR} 2006.286.02:19:03.04#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:19:13.13#abcon#<5=/04 2.9 5.9 21.36 811015.9\r\n> 2006.286.02:19:13.15#abcon#{5=INTERFACE CLEAR} 2006.286.02:19:13.21#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:19:15.44$setupk4/"tpicd 2006.286.02:19:15.44$setupk4/echo=off 2006.286.02:19:15.44$setupk4/xlog=off 2006.286.02:19:15.44:!2006.286.02:22:10 2006.286.02:19:18.14#trakl#Source acquired 2006.286.02:19:20.14#flagr#flagr/antenna,acquired 2006.286.02:22:10.00:preob 2006.286.02:22:10.14/onsource/TRACKING 2006.286.02:22:10.14:!2006.286.02:22:20 2006.286.02:22:20.00:"tape 2006.286.02:22:20.00:"st=record 2006.286.02:22:20.00:data_valid=on 2006.286.02:22:20.00:midob 2006.286.02:22:20.14/onsource/TRACKING 2006.286.02:22:20.14/wx/21.38,1015.9,80 2006.286.02:22:20.31/cable/+6.5005E-03 2006.286.02:22:21.40/va/01,07,usb,yes,38,41 2006.286.02:22:21.40/va/02,06,usb,yes,38,38 2006.286.02:22:21.40/va/03,07,usb,yes,37,39 2006.286.02:22:21.40/va/04,06,usb,yes,39,41 2006.286.02:22:21.40/va/05,03,usb,yes,38,39 2006.286.02:22:21.40/va/06,04,usb,yes,35,34 2006.286.02:22:21.40/va/07,04,usb,yes,35,36 2006.286.02:22:21.40/va/08,03,usb,yes,36,44 2006.286.02:22:21.63/valo/01,524.99,yes,locked 2006.286.02:22:21.63/valo/02,534.99,yes,locked 2006.286.02:22:21.63/valo/03,564.99,yes,locked 2006.286.02:22:21.63/valo/04,624.99,yes,locked 2006.286.02:22:21.63/valo/05,734.99,yes,locked 2006.286.02:22:21.63/valo/06,814.99,yes,locked 2006.286.02:22:21.63/valo/07,864.99,yes,locked 2006.286.02:22:21.63/valo/08,884.99,yes,locked 2006.286.02:22:22.72/vb/01,04,usb,yes,33,30 2006.286.02:22:22.72/vb/02,05,usb,yes,31,31 2006.286.02:22:22.72/vb/03,04,usb,yes,32,35 2006.286.02:22:22.72/vb/04,05,usb,yes,32,31 2006.286.02:22:22.72/vb/05,04,usb,yes,29,31 2006.286.02:22:22.72/vb/06,03,usb,yes,41,36 2006.286.02:22:22.72/vb/07,04,usb,yes,33,33 2006.286.02:22:22.72/vb/08,04,usb,yes,30,34 2006.286.02:22:22.95/vblo/01,629.99,yes,locked 2006.286.02:22:22.95/vblo/02,634.99,yes,locked 2006.286.02:22:22.95/vblo/03,649.99,yes,locked 2006.286.02:22:22.95/vblo/04,679.99,yes,locked 2006.286.02:22:22.95/vblo/05,709.99,yes,locked 2006.286.02:22:22.95/vblo/06,719.99,yes,locked 2006.286.02:22:22.95/vblo/07,734.99,yes,locked 2006.286.02:22:22.95/vblo/08,744.99,yes,locked 2006.286.02:22:23.10/vabw/8 2006.286.02:22:23.25/vbbw/8 2006.286.02:22:23.34/xfe/off,on,12.0 2006.286.02:22:23.71/ifatt/23,28,28,28 2006.286.02:22:24.08/fmout-gps/S +2.79E-07 2006.286.02:22:24.10:!2006.286.02:23:00 2006.286.02:23:00.01:data_valid=off 2006.286.02:23:00.01:"et 2006.286.02:23:00.01:!+3s 2006.286.02:23:03.02:"tape 2006.286.02:23:03.02:postob 2006.286.02:23:03.22/cable/+6.5011E-03 2006.286.02:23:03.22/wx/21.39,1015.9,81 2006.286.02:23:04.07/fmout-gps/S +2.80E-07 2006.286.02:23:04.07:scan_name=286-0227,jd0610,40 2006.286.02:23:04.07:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.286.02:23:05.14#flagr#flagr/antenna,new-source 2006.286.02:23:05.14:checkk5 2006.286.02:23:05.51/chk_autoobs//k5ts1/ autoobs is running! 2006.286.02:23:05.91/chk_autoobs//k5ts2/ autoobs is running! 2006.286.02:23:06.43/chk_autoobs//k5ts3/ autoobs is running! 2006.286.02:23:06.85/chk_autoobs//k5ts4/ autoobs is running! 2006.286.02:23:07.25/chk_obsdata//k5ts1/T2860222??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:23:07.63/chk_obsdata//k5ts2/T2860222??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:23:07.99/chk_obsdata//k5ts3/T2860222??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:23:08.49/chk_obsdata//k5ts4/T2860222??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:23:09.27/k5log//k5ts1_log_newline 2006.286.02:23:10.02/k5log//k5ts2_log_newline 2006.286.02:23:10.83/k5log//k5ts3_log_newline 2006.286.02:23:11.63/k5log//k5ts4_log_newline 2006.286.02:23:11.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.02:23:11.65:setupk4=1 2006.286.02:23:11.65$setupk4/echo=on 2006.286.02:23:11.65$setupk4/pcalon 2006.286.02:23:11.65$pcalon/"no phase cal control is implemented here 2006.286.02:23:11.65$setupk4/"tpicd=stop 2006.286.02:23:11.65$setupk4/"rec=synch_on 2006.286.02:23:11.65$setupk4/"rec_mode=128 2006.286.02:23:11.65$setupk4/!* 2006.286.02:23:11.66$setupk4/recpk4 2006.286.02:23:11.66$recpk4/recpatch= 2006.286.02:23:11.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.02:23:11.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.02:23:11.66$setupk4/vck44 2006.286.02:23:11.66$vck44/valo=1,524.99 2006.286.02:23:11.66#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.02:23:11.66#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.02:23:11.66#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:11.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:23:11.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:23:11.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:23:11.66#ibcon#enter wrdev, iclass 4, count 0 2006.286.02:23:11.66#ibcon#first serial, iclass 4, count 0 2006.286.02:23:11.66#ibcon#enter sib2, iclass 4, count 0 2006.286.02:23:11.66#ibcon#flushed, iclass 4, count 0 2006.286.02:23:11.66#ibcon#about to write, iclass 4, count 0 2006.286.02:23:11.66#ibcon#wrote, iclass 4, count 0 2006.286.02:23:11.66#ibcon#about to read 3, iclass 4, count 0 2006.286.02:23:11.68#ibcon#read 3, iclass 4, count 0 2006.286.02:23:11.68#ibcon#about to read 4, iclass 4, count 0 2006.286.02:23:11.68#ibcon#read 4, iclass 4, count 0 2006.286.02:23:11.68#ibcon#about to read 5, iclass 4, count 0 2006.286.02:23:11.68#ibcon#read 5, iclass 4, count 0 2006.286.02:23:11.68#ibcon#about to read 6, iclass 4, count 0 2006.286.02:23:11.68#ibcon#read 6, iclass 4, count 0 2006.286.02:23:11.68#ibcon#end of sib2, iclass 4, count 0 2006.286.02:23:11.68#ibcon#*mode == 0, iclass 4, count 0 2006.286.02:23:11.68#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.02:23:11.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.02:23:11.68#ibcon#*before write, iclass 4, count 0 2006.286.02:23:11.68#ibcon#enter sib2, iclass 4, count 0 2006.286.02:23:11.68#ibcon#flushed, iclass 4, count 0 2006.286.02:23:11.68#ibcon#about to write, iclass 4, count 0 2006.286.02:23:11.68#ibcon#wrote, iclass 4, count 0 2006.286.02:23:11.68#ibcon#about to read 3, iclass 4, count 0 2006.286.02:23:11.73#ibcon#read 3, iclass 4, count 0 2006.286.02:23:11.73#ibcon#about to read 4, iclass 4, count 0 2006.286.02:23:11.73#ibcon#read 4, iclass 4, count 0 2006.286.02:23:11.73#ibcon#about to read 5, iclass 4, count 0 2006.286.02:23:11.73#ibcon#read 5, iclass 4, count 0 2006.286.02:23:11.73#ibcon#about to read 6, iclass 4, count 0 2006.286.02:23:11.73#ibcon#read 6, iclass 4, count 0 2006.286.02:23:11.73#ibcon#end of sib2, iclass 4, count 0 2006.286.02:23:11.73#ibcon#*after write, iclass 4, count 0 2006.286.02:23:11.73#ibcon#*before return 0, iclass 4, count 0 2006.286.02:23:11.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:23:11.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:23:11.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.02:23:11.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.02:23:11.73$vck44/va=1,7 2006.286.02:23:11.73#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.02:23:11.73#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.02:23:11.73#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:11.73#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:23:11.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:23:11.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:23:11.73#ibcon#enter wrdev, iclass 6, count 2 2006.286.02:23:11.73#ibcon#first serial, iclass 6, count 2 2006.286.02:23:11.73#ibcon#enter sib2, iclass 6, count 2 2006.286.02:23:11.73#ibcon#flushed, iclass 6, count 2 2006.286.02:23:11.73#ibcon#about to write, iclass 6, count 2 2006.286.02:23:11.73#ibcon#wrote, iclass 6, count 2 2006.286.02:23:11.73#ibcon#about to read 3, iclass 6, count 2 2006.286.02:23:11.75#ibcon#read 3, iclass 6, count 2 2006.286.02:23:11.75#ibcon#about to read 4, iclass 6, count 2 2006.286.02:23:11.75#ibcon#read 4, iclass 6, count 2 2006.286.02:23:11.75#ibcon#about to read 5, iclass 6, count 2 2006.286.02:23:11.75#ibcon#read 5, iclass 6, count 2 2006.286.02:23:11.75#ibcon#about to read 6, iclass 6, count 2 2006.286.02:23:11.75#ibcon#read 6, iclass 6, count 2 2006.286.02:23:11.75#ibcon#end of sib2, iclass 6, count 2 2006.286.02:23:11.75#ibcon#*mode == 0, iclass 6, count 2 2006.286.02:23:11.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.02:23:11.75#ibcon#[25=AT01-07\r\n] 2006.286.02:23:11.75#ibcon#*before write, iclass 6, count 2 2006.286.02:23:11.75#ibcon#enter sib2, iclass 6, count 2 2006.286.02:23:11.75#ibcon#flushed, iclass 6, count 2 2006.286.02:23:11.75#ibcon#about to write, iclass 6, count 2 2006.286.02:23:11.75#ibcon#wrote, iclass 6, count 2 2006.286.02:23:11.75#ibcon#about to read 3, iclass 6, count 2 2006.286.02:23:11.78#ibcon#read 3, iclass 6, count 2 2006.286.02:23:11.78#ibcon#about to read 4, iclass 6, count 2 2006.286.02:23:11.78#ibcon#read 4, iclass 6, count 2 2006.286.02:23:11.78#ibcon#about to read 5, iclass 6, count 2 2006.286.02:23:11.78#ibcon#read 5, iclass 6, count 2 2006.286.02:23:11.78#ibcon#about to read 6, iclass 6, count 2 2006.286.02:23:11.78#ibcon#read 6, iclass 6, count 2 2006.286.02:23:11.78#ibcon#end of sib2, iclass 6, count 2 2006.286.02:23:11.78#ibcon#*after write, iclass 6, count 2 2006.286.02:23:11.78#ibcon#*before return 0, iclass 6, count 2 2006.286.02:23:11.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:23:11.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:23:11.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.02:23:11.78#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:11.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:23:11.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:23:11.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:23:11.90#ibcon#enter wrdev, iclass 6, count 0 2006.286.02:23:11.90#ibcon#first serial, iclass 6, count 0 2006.286.02:23:11.90#ibcon#enter sib2, iclass 6, count 0 2006.286.02:23:11.90#ibcon#flushed, iclass 6, count 0 2006.286.02:23:11.90#ibcon#about to write, iclass 6, count 0 2006.286.02:23:11.90#ibcon#wrote, iclass 6, count 0 2006.286.02:23:11.90#ibcon#about to read 3, iclass 6, count 0 2006.286.02:23:11.92#ibcon#read 3, iclass 6, count 0 2006.286.02:23:11.92#ibcon#about to read 4, iclass 6, count 0 2006.286.02:23:11.92#ibcon#read 4, iclass 6, count 0 2006.286.02:23:11.92#ibcon#about to read 5, iclass 6, count 0 2006.286.02:23:11.92#ibcon#read 5, iclass 6, count 0 2006.286.02:23:11.92#ibcon#about to read 6, iclass 6, count 0 2006.286.02:23:11.92#ibcon#read 6, iclass 6, count 0 2006.286.02:23:11.92#ibcon#end of sib2, iclass 6, count 0 2006.286.02:23:11.92#ibcon#*mode == 0, iclass 6, count 0 2006.286.02:23:11.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.02:23:11.92#ibcon#[25=USB\r\n] 2006.286.02:23:11.92#ibcon#*before write, iclass 6, count 0 2006.286.02:23:11.92#ibcon#enter sib2, iclass 6, count 0 2006.286.02:23:11.92#ibcon#flushed, iclass 6, count 0 2006.286.02:23:11.92#ibcon#about to write, iclass 6, count 0 2006.286.02:23:11.92#ibcon#wrote, iclass 6, count 0 2006.286.02:23:11.92#ibcon#about to read 3, iclass 6, count 0 2006.286.02:23:11.95#ibcon#read 3, iclass 6, count 0 2006.286.02:23:11.95#ibcon#about to read 4, iclass 6, count 0 2006.286.02:23:11.95#ibcon#read 4, iclass 6, count 0 2006.286.02:23:11.95#ibcon#about to read 5, iclass 6, count 0 2006.286.02:23:11.95#ibcon#read 5, iclass 6, count 0 2006.286.02:23:11.95#ibcon#about to read 6, iclass 6, count 0 2006.286.02:23:11.95#ibcon#read 6, iclass 6, count 0 2006.286.02:23:11.95#ibcon#end of sib2, iclass 6, count 0 2006.286.02:23:11.95#ibcon#*after write, iclass 6, count 0 2006.286.02:23:11.95#ibcon#*before return 0, iclass 6, count 0 2006.286.02:23:11.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:23:11.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:23:11.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.02:23:11.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.02:23:11.95$vck44/valo=2,534.99 2006.286.02:23:11.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.02:23:11.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.02:23:11.95#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:11.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:23:11.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:23:11.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:23:11.95#ibcon#enter wrdev, iclass 10, count 0 2006.286.02:23:11.95#ibcon#first serial, iclass 10, count 0 2006.286.02:23:11.95#ibcon#enter sib2, iclass 10, count 0 2006.286.02:23:11.95#ibcon#flushed, iclass 10, count 0 2006.286.02:23:11.95#ibcon#about to write, iclass 10, count 0 2006.286.02:23:11.95#ibcon#wrote, iclass 10, count 0 2006.286.02:23:11.95#ibcon#about to read 3, iclass 10, count 0 2006.286.02:23:11.97#ibcon#read 3, iclass 10, count 0 2006.286.02:23:11.97#ibcon#about to read 4, iclass 10, count 0 2006.286.02:23:11.97#ibcon#read 4, iclass 10, count 0 2006.286.02:23:11.97#ibcon#about to read 5, iclass 10, count 0 2006.286.02:23:11.97#ibcon#read 5, iclass 10, count 0 2006.286.02:23:11.97#ibcon#about to read 6, iclass 10, count 0 2006.286.02:23:11.97#ibcon#read 6, iclass 10, count 0 2006.286.02:23:11.97#ibcon#end of sib2, iclass 10, count 0 2006.286.02:23:11.97#ibcon#*mode == 0, iclass 10, count 0 2006.286.02:23:11.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.02:23:11.97#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.02:23:11.97#ibcon#*before write, iclass 10, count 0 2006.286.02:23:11.97#ibcon#enter sib2, iclass 10, count 0 2006.286.02:23:11.97#ibcon#flushed, iclass 10, count 0 2006.286.02:23:11.97#ibcon#about to write, iclass 10, count 0 2006.286.02:23:11.97#ibcon#wrote, iclass 10, count 0 2006.286.02:23:11.97#ibcon#about to read 3, iclass 10, count 0 2006.286.02:23:12.01#ibcon#read 3, iclass 10, count 0 2006.286.02:23:12.01#ibcon#about to read 4, iclass 10, count 0 2006.286.02:23:12.01#ibcon#read 4, iclass 10, count 0 2006.286.02:23:12.01#ibcon#about to read 5, iclass 10, count 0 2006.286.02:23:12.01#ibcon#read 5, iclass 10, count 0 2006.286.02:23:12.01#ibcon#about to read 6, iclass 10, count 0 2006.286.02:23:12.01#ibcon#read 6, iclass 10, count 0 2006.286.02:23:12.01#ibcon#end of sib2, iclass 10, count 0 2006.286.02:23:12.01#ibcon#*after write, iclass 10, count 0 2006.286.02:23:12.01#ibcon#*before return 0, iclass 10, count 0 2006.286.02:23:12.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:23:12.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:23:12.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.02:23:12.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.02:23:12.01$vck44/va=2,6 2006.286.02:23:12.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.02:23:12.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.02:23:12.01#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:12.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:23:12.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:23:12.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:23:12.07#ibcon#enter wrdev, iclass 12, count 2 2006.286.02:23:12.07#ibcon#first serial, iclass 12, count 2 2006.286.02:23:12.07#ibcon#enter sib2, iclass 12, count 2 2006.286.02:23:12.07#ibcon#flushed, iclass 12, count 2 2006.286.02:23:12.07#ibcon#about to write, iclass 12, count 2 2006.286.02:23:12.07#ibcon#wrote, iclass 12, count 2 2006.286.02:23:12.07#ibcon#about to read 3, iclass 12, count 2 2006.286.02:23:12.09#ibcon#read 3, iclass 12, count 2 2006.286.02:23:12.09#ibcon#about to read 4, iclass 12, count 2 2006.286.02:23:12.09#ibcon#read 4, iclass 12, count 2 2006.286.02:23:12.09#ibcon#about to read 5, iclass 12, count 2 2006.286.02:23:12.09#ibcon#read 5, iclass 12, count 2 2006.286.02:23:12.09#ibcon#about to read 6, iclass 12, count 2 2006.286.02:23:12.09#ibcon#read 6, iclass 12, count 2 2006.286.02:23:12.09#ibcon#end of sib2, iclass 12, count 2 2006.286.02:23:12.09#ibcon#*mode == 0, iclass 12, count 2 2006.286.02:23:12.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.02:23:12.09#ibcon#[25=AT02-06\r\n] 2006.286.02:23:12.09#ibcon#*before write, iclass 12, count 2 2006.286.02:23:12.09#ibcon#enter sib2, iclass 12, count 2 2006.286.02:23:12.09#ibcon#flushed, iclass 12, count 2 2006.286.02:23:12.09#ibcon#about to write, iclass 12, count 2 2006.286.02:23:12.09#ibcon#wrote, iclass 12, count 2 2006.286.02:23:12.09#ibcon#about to read 3, iclass 12, count 2 2006.286.02:23:12.12#ibcon#read 3, iclass 12, count 2 2006.286.02:23:12.12#ibcon#about to read 4, iclass 12, count 2 2006.286.02:23:12.12#ibcon#read 4, iclass 12, count 2 2006.286.02:23:12.12#ibcon#about to read 5, iclass 12, count 2 2006.286.02:23:12.12#ibcon#read 5, iclass 12, count 2 2006.286.02:23:12.12#ibcon#about to read 6, iclass 12, count 2 2006.286.02:23:12.12#ibcon#read 6, iclass 12, count 2 2006.286.02:23:12.12#ibcon#end of sib2, iclass 12, count 2 2006.286.02:23:12.12#ibcon#*after write, iclass 12, count 2 2006.286.02:23:12.12#ibcon#*before return 0, iclass 12, count 2 2006.286.02:23:12.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:23:12.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:23:12.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.02:23:12.12#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:12.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:23:12.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:23:12.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:23:12.24#ibcon#enter wrdev, iclass 12, count 0 2006.286.02:23:12.24#ibcon#first serial, iclass 12, count 0 2006.286.02:23:12.24#ibcon#enter sib2, iclass 12, count 0 2006.286.02:23:12.24#ibcon#flushed, iclass 12, count 0 2006.286.02:23:12.24#ibcon#about to write, iclass 12, count 0 2006.286.02:23:12.24#ibcon#wrote, iclass 12, count 0 2006.286.02:23:12.24#ibcon#about to read 3, iclass 12, count 0 2006.286.02:23:12.26#ibcon#read 3, iclass 12, count 0 2006.286.02:23:12.26#ibcon#about to read 4, iclass 12, count 0 2006.286.02:23:12.26#ibcon#read 4, iclass 12, count 0 2006.286.02:23:12.26#ibcon#about to read 5, iclass 12, count 0 2006.286.02:23:12.26#ibcon#read 5, iclass 12, count 0 2006.286.02:23:12.26#ibcon#about to read 6, iclass 12, count 0 2006.286.02:23:12.26#ibcon#read 6, iclass 12, count 0 2006.286.02:23:12.26#ibcon#end of sib2, iclass 12, count 0 2006.286.02:23:12.26#ibcon#*mode == 0, iclass 12, count 0 2006.286.02:23:12.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.02:23:12.26#ibcon#[25=USB\r\n] 2006.286.02:23:12.26#ibcon#*before write, iclass 12, count 0 2006.286.02:23:12.26#ibcon#enter sib2, iclass 12, count 0 2006.286.02:23:12.26#ibcon#flushed, iclass 12, count 0 2006.286.02:23:12.26#ibcon#about to write, iclass 12, count 0 2006.286.02:23:12.26#ibcon#wrote, iclass 12, count 0 2006.286.02:23:12.26#ibcon#about to read 3, iclass 12, count 0 2006.286.02:23:12.29#ibcon#read 3, iclass 12, count 0 2006.286.02:23:12.29#ibcon#about to read 4, iclass 12, count 0 2006.286.02:23:12.29#ibcon#read 4, iclass 12, count 0 2006.286.02:23:12.29#ibcon#about to read 5, iclass 12, count 0 2006.286.02:23:12.29#ibcon#read 5, iclass 12, count 0 2006.286.02:23:12.29#ibcon#about to read 6, iclass 12, count 0 2006.286.02:23:12.29#ibcon#read 6, iclass 12, count 0 2006.286.02:23:12.29#ibcon#end of sib2, iclass 12, count 0 2006.286.02:23:12.29#ibcon#*after write, iclass 12, count 0 2006.286.02:23:12.29#ibcon#*before return 0, iclass 12, count 0 2006.286.02:23:12.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:23:12.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:23:12.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.02:23:12.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.02:23:12.29$vck44/valo=3,564.99 2006.286.02:23:12.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.02:23:12.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.02:23:12.29#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:12.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:23:12.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:23:12.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:23:12.29#ibcon#enter wrdev, iclass 14, count 0 2006.286.02:23:12.29#ibcon#first serial, iclass 14, count 0 2006.286.02:23:12.29#ibcon#enter sib2, iclass 14, count 0 2006.286.02:23:12.29#ibcon#flushed, iclass 14, count 0 2006.286.02:23:12.29#ibcon#about to write, iclass 14, count 0 2006.286.02:23:12.29#ibcon#wrote, iclass 14, count 0 2006.286.02:23:12.29#ibcon#about to read 3, iclass 14, count 0 2006.286.02:23:12.31#ibcon#read 3, iclass 14, count 0 2006.286.02:23:12.31#ibcon#about to read 4, iclass 14, count 0 2006.286.02:23:12.31#ibcon#read 4, iclass 14, count 0 2006.286.02:23:12.31#ibcon#about to read 5, iclass 14, count 0 2006.286.02:23:12.31#ibcon#read 5, iclass 14, count 0 2006.286.02:23:12.31#ibcon#about to read 6, iclass 14, count 0 2006.286.02:23:12.31#ibcon#read 6, iclass 14, count 0 2006.286.02:23:12.31#ibcon#end of sib2, iclass 14, count 0 2006.286.02:23:12.31#ibcon#*mode == 0, iclass 14, count 0 2006.286.02:23:12.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.02:23:12.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.02:23:12.31#ibcon#*before write, iclass 14, count 0 2006.286.02:23:12.31#ibcon#enter sib2, iclass 14, count 0 2006.286.02:23:12.31#ibcon#flushed, iclass 14, count 0 2006.286.02:23:12.31#ibcon#about to write, iclass 14, count 0 2006.286.02:23:12.31#ibcon#wrote, iclass 14, count 0 2006.286.02:23:12.31#ibcon#about to read 3, iclass 14, count 0 2006.286.02:23:12.35#ibcon#read 3, iclass 14, count 0 2006.286.02:23:12.35#ibcon#about to read 4, iclass 14, count 0 2006.286.02:23:12.35#ibcon#read 4, iclass 14, count 0 2006.286.02:23:12.35#ibcon#about to read 5, iclass 14, count 0 2006.286.02:23:12.35#ibcon#read 5, iclass 14, count 0 2006.286.02:23:12.35#ibcon#about to read 6, iclass 14, count 0 2006.286.02:23:12.35#ibcon#read 6, iclass 14, count 0 2006.286.02:23:12.35#ibcon#end of sib2, iclass 14, count 0 2006.286.02:23:12.35#ibcon#*after write, iclass 14, count 0 2006.286.02:23:12.35#ibcon#*before return 0, iclass 14, count 0 2006.286.02:23:12.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:23:12.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:23:12.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.02:23:12.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.02:23:12.35$vck44/va=3,7 2006.286.02:23:12.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.02:23:12.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.02:23:12.35#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:12.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:23:12.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:23:12.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:23:12.41#ibcon#enter wrdev, iclass 16, count 2 2006.286.02:23:12.41#ibcon#first serial, iclass 16, count 2 2006.286.02:23:12.41#ibcon#enter sib2, iclass 16, count 2 2006.286.02:23:12.41#ibcon#flushed, iclass 16, count 2 2006.286.02:23:12.41#ibcon#about to write, iclass 16, count 2 2006.286.02:23:12.41#ibcon#wrote, iclass 16, count 2 2006.286.02:23:12.41#ibcon#about to read 3, iclass 16, count 2 2006.286.02:23:12.43#ibcon#read 3, iclass 16, count 2 2006.286.02:23:12.43#ibcon#about to read 4, iclass 16, count 2 2006.286.02:23:12.43#ibcon#read 4, iclass 16, count 2 2006.286.02:23:12.43#ibcon#about to read 5, iclass 16, count 2 2006.286.02:23:12.43#ibcon#read 5, iclass 16, count 2 2006.286.02:23:12.43#ibcon#about to read 6, iclass 16, count 2 2006.286.02:23:12.43#ibcon#read 6, iclass 16, count 2 2006.286.02:23:12.43#ibcon#end of sib2, iclass 16, count 2 2006.286.02:23:12.43#ibcon#*mode == 0, iclass 16, count 2 2006.286.02:23:12.43#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.02:23:12.43#ibcon#[25=AT03-07\r\n] 2006.286.02:23:12.43#ibcon#*before write, iclass 16, count 2 2006.286.02:23:12.43#ibcon#enter sib2, iclass 16, count 2 2006.286.02:23:12.43#ibcon#flushed, iclass 16, count 2 2006.286.02:23:12.43#ibcon#about to write, iclass 16, count 2 2006.286.02:23:12.43#ibcon#wrote, iclass 16, count 2 2006.286.02:23:12.43#ibcon#about to read 3, iclass 16, count 2 2006.286.02:23:12.46#ibcon#read 3, iclass 16, count 2 2006.286.02:23:12.46#ibcon#about to read 4, iclass 16, count 2 2006.286.02:23:12.46#ibcon#read 4, iclass 16, count 2 2006.286.02:23:12.46#ibcon#about to read 5, iclass 16, count 2 2006.286.02:23:12.46#ibcon#read 5, iclass 16, count 2 2006.286.02:23:12.46#ibcon#about to read 6, iclass 16, count 2 2006.286.02:23:12.46#ibcon#read 6, iclass 16, count 2 2006.286.02:23:12.46#ibcon#end of sib2, iclass 16, count 2 2006.286.02:23:12.46#ibcon#*after write, iclass 16, count 2 2006.286.02:23:12.46#ibcon#*before return 0, iclass 16, count 2 2006.286.02:23:12.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:23:12.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:23:12.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.02:23:12.46#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:12.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:23:12.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:23:12.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:23:12.58#ibcon#enter wrdev, iclass 16, count 0 2006.286.02:23:12.58#ibcon#first serial, iclass 16, count 0 2006.286.02:23:12.58#ibcon#enter sib2, iclass 16, count 0 2006.286.02:23:12.58#ibcon#flushed, iclass 16, count 0 2006.286.02:23:12.58#ibcon#about to write, iclass 16, count 0 2006.286.02:23:12.58#ibcon#wrote, iclass 16, count 0 2006.286.02:23:12.58#ibcon#about to read 3, iclass 16, count 0 2006.286.02:23:12.60#ibcon#read 3, iclass 16, count 0 2006.286.02:23:12.60#ibcon#about to read 4, iclass 16, count 0 2006.286.02:23:12.60#ibcon#read 4, iclass 16, count 0 2006.286.02:23:12.60#ibcon#about to read 5, iclass 16, count 0 2006.286.02:23:12.60#ibcon#read 5, iclass 16, count 0 2006.286.02:23:12.60#ibcon#about to read 6, iclass 16, count 0 2006.286.02:23:12.60#ibcon#read 6, iclass 16, count 0 2006.286.02:23:12.60#ibcon#end of sib2, iclass 16, count 0 2006.286.02:23:12.60#ibcon#*mode == 0, iclass 16, count 0 2006.286.02:23:12.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.02:23:12.60#ibcon#[25=USB\r\n] 2006.286.02:23:12.60#ibcon#*before write, iclass 16, count 0 2006.286.02:23:12.60#ibcon#enter sib2, iclass 16, count 0 2006.286.02:23:12.60#ibcon#flushed, iclass 16, count 0 2006.286.02:23:12.60#ibcon#about to write, iclass 16, count 0 2006.286.02:23:12.60#ibcon#wrote, iclass 16, count 0 2006.286.02:23:12.60#ibcon#about to read 3, iclass 16, count 0 2006.286.02:23:12.63#ibcon#read 3, iclass 16, count 0 2006.286.02:23:12.63#ibcon#about to read 4, iclass 16, count 0 2006.286.02:23:12.63#ibcon#read 4, iclass 16, count 0 2006.286.02:23:12.63#ibcon#about to read 5, iclass 16, count 0 2006.286.02:23:12.63#ibcon#read 5, iclass 16, count 0 2006.286.02:23:12.63#ibcon#about to read 6, iclass 16, count 0 2006.286.02:23:12.63#ibcon#read 6, iclass 16, count 0 2006.286.02:23:12.63#ibcon#end of sib2, iclass 16, count 0 2006.286.02:23:12.63#ibcon#*after write, iclass 16, count 0 2006.286.02:23:12.63#ibcon#*before return 0, iclass 16, count 0 2006.286.02:23:12.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:23:12.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:23:12.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.02:23:12.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.02:23:12.63$vck44/valo=4,624.99 2006.286.02:23:12.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.02:23:12.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.02:23:12.63#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:12.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:23:12.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:23:12.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:23:12.63#ibcon#enter wrdev, iclass 18, count 0 2006.286.02:23:12.63#ibcon#first serial, iclass 18, count 0 2006.286.02:23:12.63#ibcon#enter sib2, iclass 18, count 0 2006.286.02:23:12.63#ibcon#flushed, iclass 18, count 0 2006.286.02:23:12.63#ibcon#about to write, iclass 18, count 0 2006.286.02:23:12.63#ibcon#wrote, iclass 18, count 0 2006.286.02:23:12.63#ibcon#about to read 3, iclass 18, count 0 2006.286.02:23:12.65#ibcon#read 3, iclass 18, count 0 2006.286.02:23:12.65#ibcon#about to read 4, iclass 18, count 0 2006.286.02:23:12.65#ibcon#read 4, iclass 18, count 0 2006.286.02:23:12.65#ibcon#about to read 5, iclass 18, count 0 2006.286.02:23:12.65#ibcon#read 5, iclass 18, count 0 2006.286.02:23:12.65#ibcon#about to read 6, iclass 18, count 0 2006.286.02:23:12.65#ibcon#read 6, iclass 18, count 0 2006.286.02:23:12.65#ibcon#end of sib2, iclass 18, count 0 2006.286.02:23:12.65#ibcon#*mode == 0, iclass 18, count 0 2006.286.02:23:12.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.02:23:12.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.02:23:12.65#ibcon#*before write, iclass 18, count 0 2006.286.02:23:12.65#ibcon#enter sib2, iclass 18, count 0 2006.286.02:23:12.65#ibcon#flushed, iclass 18, count 0 2006.286.02:23:12.65#ibcon#about to write, iclass 18, count 0 2006.286.02:23:12.65#ibcon#wrote, iclass 18, count 0 2006.286.02:23:12.65#ibcon#about to read 3, iclass 18, count 0 2006.286.02:23:12.69#ibcon#read 3, iclass 18, count 0 2006.286.02:23:12.69#ibcon#about to read 4, iclass 18, count 0 2006.286.02:23:12.69#ibcon#read 4, iclass 18, count 0 2006.286.02:23:12.69#ibcon#about to read 5, iclass 18, count 0 2006.286.02:23:12.69#ibcon#read 5, iclass 18, count 0 2006.286.02:23:12.69#ibcon#about to read 6, iclass 18, count 0 2006.286.02:23:12.69#ibcon#read 6, iclass 18, count 0 2006.286.02:23:12.69#ibcon#end of sib2, iclass 18, count 0 2006.286.02:23:12.69#ibcon#*after write, iclass 18, count 0 2006.286.02:23:12.69#ibcon#*before return 0, iclass 18, count 0 2006.286.02:23:12.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:23:12.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:23:12.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.02:23:12.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.02:23:12.69$vck44/va=4,6 2006.286.02:23:12.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.02:23:12.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.02:23:12.69#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:12.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:23:12.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:23:12.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:23:12.75#ibcon#enter wrdev, iclass 20, count 2 2006.286.02:23:12.75#ibcon#first serial, iclass 20, count 2 2006.286.02:23:12.75#ibcon#enter sib2, iclass 20, count 2 2006.286.02:23:12.75#ibcon#flushed, iclass 20, count 2 2006.286.02:23:12.75#ibcon#about to write, iclass 20, count 2 2006.286.02:23:12.75#ibcon#wrote, iclass 20, count 2 2006.286.02:23:12.75#ibcon#about to read 3, iclass 20, count 2 2006.286.02:23:12.77#ibcon#read 3, iclass 20, count 2 2006.286.02:23:12.77#ibcon#about to read 4, iclass 20, count 2 2006.286.02:23:12.77#ibcon#read 4, iclass 20, count 2 2006.286.02:23:12.77#ibcon#about to read 5, iclass 20, count 2 2006.286.02:23:12.77#ibcon#read 5, iclass 20, count 2 2006.286.02:23:12.77#ibcon#about to read 6, iclass 20, count 2 2006.286.02:23:12.77#ibcon#read 6, iclass 20, count 2 2006.286.02:23:12.77#ibcon#end of sib2, iclass 20, count 2 2006.286.02:23:12.77#ibcon#*mode == 0, iclass 20, count 2 2006.286.02:23:12.77#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.02:23:12.77#ibcon#[25=AT04-06\r\n] 2006.286.02:23:12.77#ibcon#*before write, iclass 20, count 2 2006.286.02:23:12.77#ibcon#enter sib2, iclass 20, count 2 2006.286.02:23:12.77#ibcon#flushed, iclass 20, count 2 2006.286.02:23:12.77#ibcon#about to write, iclass 20, count 2 2006.286.02:23:12.77#ibcon#wrote, iclass 20, count 2 2006.286.02:23:12.77#ibcon#about to read 3, iclass 20, count 2 2006.286.02:23:12.80#ibcon#read 3, iclass 20, count 2 2006.286.02:23:12.80#ibcon#about to read 4, iclass 20, count 2 2006.286.02:23:12.80#ibcon#read 4, iclass 20, count 2 2006.286.02:23:12.80#ibcon#about to read 5, iclass 20, count 2 2006.286.02:23:12.80#ibcon#read 5, iclass 20, count 2 2006.286.02:23:12.80#ibcon#about to read 6, iclass 20, count 2 2006.286.02:23:12.80#ibcon#read 6, iclass 20, count 2 2006.286.02:23:12.80#ibcon#end of sib2, iclass 20, count 2 2006.286.02:23:12.80#ibcon#*after write, iclass 20, count 2 2006.286.02:23:12.80#ibcon#*before return 0, iclass 20, count 2 2006.286.02:23:12.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:23:12.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:23:12.80#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.02:23:12.80#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:12.80#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:23:12.92#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:23:12.92#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:23:12.92#ibcon#enter wrdev, iclass 20, count 0 2006.286.02:23:12.92#ibcon#first serial, iclass 20, count 0 2006.286.02:23:12.92#ibcon#enter sib2, iclass 20, count 0 2006.286.02:23:12.92#ibcon#flushed, iclass 20, count 0 2006.286.02:23:12.92#ibcon#about to write, iclass 20, count 0 2006.286.02:23:12.92#ibcon#wrote, iclass 20, count 0 2006.286.02:23:12.92#ibcon#about to read 3, iclass 20, count 0 2006.286.02:23:12.94#ibcon#read 3, iclass 20, count 0 2006.286.02:23:12.94#ibcon#about to read 4, iclass 20, count 0 2006.286.02:23:12.94#ibcon#read 4, iclass 20, count 0 2006.286.02:23:12.94#ibcon#about to read 5, iclass 20, count 0 2006.286.02:23:12.94#ibcon#read 5, iclass 20, count 0 2006.286.02:23:12.94#ibcon#about to read 6, iclass 20, count 0 2006.286.02:23:12.94#ibcon#read 6, iclass 20, count 0 2006.286.02:23:12.94#ibcon#end of sib2, iclass 20, count 0 2006.286.02:23:12.94#ibcon#*mode == 0, iclass 20, count 0 2006.286.02:23:12.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.02:23:12.94#ibcon#[25=USB\r\n] 2006.286.02:23:12.94#ibcon#*before write, iclass 20, count 0 2006.286.02:23:12.94#ibcon#enter sib2, iclass 20, count 0 2006.286.02:23:12.94#ibcon#flushed, iclass 20, count 0 2006.286.02:23:12.94#ibcon#about to write, iclass 20, count 0 2006.286.02:23:12.94#ibcon#wrote, iclass 20, count 0 2006.286.02:23:12.94#ibcon#about to read 3, iclass 20, count 0 2006.286.02:23:12.97#ibcon#read 3, iclass 20, count 0 2006.286.02:23:12.97#ibcon#about to read 4, iclass 20, count 0 2006.286.02:23:12.97#ibcon#read 4, iclass 20, count 0 2006.286.02:23:12.97#ibcon#about to read 5, iclass 20, count 0 2006.286.02:23:12.97#ibcon#read 5, iclass 20, count 0 2006.286.02:23:12.97#ibcon#about to read 6, iclass 20, count 0 2006.286.02:23:12.97#ibcon#read 6, iclass 20, count 0 2006.286.02:23:12.97#ibcon#end of sib2, iclass 20, count 0 2006.286.02:23:12.97#ibcon#*after write, iclass 20, count 0 2006.286.02:23:12.97#ibcon#*before return 0, iclass 20, count 0 2006.286.02:23:12.97#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:23:12.97#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:23:12.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.02:23:12.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.02:23:12.97$vck44/valo=5,734.99 2006.286.02:23:12.97#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.02:23:12.97#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.02:23:12.97#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:12.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:23:12.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:23:12.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:23:12.97#ibcon#enter wrdev, iclass 22, count 0 2006.286.02:23:12.97#ibcon#first serial, iclass 22, count 0 2006.286.02:23:12.97#ibcon#enter sib2, iclass 22, count 0 2006.286.02:23:12.97#ibcon#flushed, iclass 22, count 0 2006.286.02:23:12.97#ibcon#about to write, iclass 22, count 0 2006.286.02:23:12.97#ibcon#wrote, iclass 22, count 0 2006.286.02:23:12.97#ibcon#about to read 3, iclass 22, count 0 2006.286.02:23:12.99#ibcon#read 3, iclass 22, count 0 2006.286.02:23:12.99#ibcon#about to read 4, iclass 22, count 0 2006.286.02:23:12.99#ibcon#read 4, iclass 22, count 0 2006.286.02:23:12.99#ibcon#about to read 5, iclass 22, count 0 2006.286.02:23:12.99#ibcon#read 5, iclass 22, count 0 2006.286.02:23:12.99#ibcon#about to read 6, iclass 22, count 0 2006.286.02:23:12.99#ibcon#read 6, iclass 22, count 0 2006.286.02:23:12.99#ibcon#end of sib2, iclass 22, count 0 2006.286.02:23:12.99#ibcon#*mode == 0, iclass 22, count 0 2006.286.02:23:12.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.02:23:12.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.02:23:12.99#ibcon#*before write, iclass 22, count 0 2006.286.02:23:12.99#ibcon#enter sib2, iclass 22, count 0 2006.286.02:23:12.99#ibcon#flushed, iclass 22, count 0 2006.286.02:23:12.99#ibcon#about to write, iclass 22, count 0 2006.286.02:23:12.99#ibcon#wrote, iclass 22, count 0 2006.286.02:23:12.99#ibcon#about to read 3, iclass 22, count 0 2006.286.02:23:13.03#ibcon#read 3, iclass 22, count 0 2006.286.02:23:13.03#ibcon#about to read 4, iclass 22, count 0 2006.286.02:23:13.03#ibcon#read 4, iclass 22, count 0 2006.286.02:23:13.03#ibcon#about to read 5, iclass 22, count 0 2006.286.02:23:13.03#ibcon#read 5, iclass 22, count 0 2006.286.02:23:13.03#ibcon#about to read 6, iclass 22, count 0 2006.286.02:23:13.03#ibcon#read 6, iclass 22, count 0 2006.286.02:23:13.03#ibcon#end of sib2, iclass 22, count 0 2006.286.02:23:13.03#ibcon#*after write, iclass 22, count 0 2006.286.02:23:13.03#ibcon#*before return 0, iclass 22, count 0 2006.286.02:23:13.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:23:13.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:23:13.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.02:23:13.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.02:23:13.03$vck44/va=5,3 2006.286.02:23:13.03#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.02:23:13.03#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.02:23:13.03#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:13.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:23:13.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:23:13.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:23:13.09#ibcon#enter wrdev, iclass 24, count 2 2006.286.02:23:13.09#ibcon#first serial, iclass 24, count 2 2006.286.02:23:13.09#ibcon#enter sib2, iclass 24, count 2 2006.286.02:23:13.09#ibcon#flushed, iclass 24, count 2 2006.286.02:23:13.09#ibcon#about to write, iclass 24, count 2 2006.286.02:23:13.09#ibcon#wrote, iclass 24, count 2 2006.286.02:23:13.09#ibcon#about to read 3, iclass 24, count 2 2006.286.02:23:13.11#ibcon#read 3, iclass 24, count 2 2006.286.02:23:13.11#ibcon#about to read 4, iclass 24, count 2 2006.286.02:23:13.11#ibcon#read 4, iclass 24, count 2 2006.286.02:23:13.11#ibcon#about to read 5, iclass 24, count 2 2006.286.02:23:13.11#ibcon#read 5, iclass 24, count 2 2006.286.02:23:13.11#ibcon#about to read 6, iclass 24, count 2 2006.286.02:23:13.11#ibcon#read 6, iclass 24, count 2 2006.286.02:23:13.11#ibcon#end of sib2, iclass 24, count 2 2006.286.02:23:13.11#ibcon#*mode == 0, iclass 24, count 2 2006.286.02:23:13.11#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.02:23:13.11#ibcon#[25=AT05-03\r\n] 2006.286.02:23:13.11#ibcon#*before write, iclass 24, count 2 2006.286.02:23:13.11#ibcon#enter sib2, iclass 24, count 2 2006.286.02:23:13.11#ibcon#flushed, iclass 24, count 2 2006.286.02:23:13.11#ibcon#about to write, iclass 24, count 2 2006.286.02:23:13.11#ibcon#wrote, iclass 24, count 2 2006.286.02:23:13.11#ibcon#about to read 3, iclass 24, count 2 2006.286.02:23:13.14#ibcon#read 3, iclass 24, count 2 2006.286.02:23:13.14#ibcon#about to read 4, iclass 24, count 2 2006.286.02:23:13.14#ibcon#read 4, iclass 24, count 2 2006.286.02:23:13.14#ibcon#about to read 5, iclass 24, count 2 2006.286.02:23:13.14#ibcon#read 5, iclass 24, count 2 2006.286.02:23:13.14#ibcon#about to read 6, iclass 24, count 2 2006.286.02:23:13.14#ibcon#read 6, iclass 24, count 2 2006.286.02:23:13.14#ibcon#end of sib2, iclass 24, count 2 2006.286.02:23:13.14#ibcon#*after write, iclass 24, count 2 2006.286.02:23:13.14#ibcon#*before return 0, iclass 24, count 2 2006.286.02:23:13.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:23:13.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:23:13.14#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.02:23:13.14#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:13.14#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:23:13.26#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:23:13.26#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:23:13.26#ibcon#enter wrdev, iclass 24, count 0 2006.286.02:23:13.26#ibcon#first serial, iclass 24, count 0 2006.286.02:23:13.26#ibcon#enter sib2, iclass 24, count 0 2006.286.02:23:13.26#ibcon#flushed, iclass 24, count 0 2006.286.02:23:13.26#ibcon#about to write, iclass 24, count 0 2006.286.02:23:13.26#ibcon#wrote, iclass 24, count 0 2006.286.02:23:13.26#ibcon#about to read 3, iclass 24, count 0 2006.286.02:23:13.28#ibcon#read 3, iclass 24, count 0 2006.286.02:23:13.28#ibcon#about to read 4, iclass 24, count 0 2006.286.02:23:13.28#ibcon#read 4, iclass 24, count 0 2006.286.02:23:13.28#ibcon#about to read 5, iclass 24, count 0 2006.286.02:23:13.28#ibcon#read 5, iclass 24, count 0 2006.286.02:23:13.28#ibcon#about to read 6, iclass 24, count 0 2006.286.02:23:13.28#ibcon#read 6, iclass 24, count 0 2006.286.02:23:13.28#ibcon#end of sib2, iclass 24, count 0 2006.286.02:23:13.28#ibcon#*mode == 0, iclass 24, count 0 2006.286.02:23:13.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.02:23:13.28#ibcon#[25=USB\r\n] 2006.286.02:23:13.28#ibcon#*before write, iclass 24, count 0 2006.286.02:23:13.28#ibcon#enter sib2, iclass 24, count 0 2006.286.02:23:13.28#ibcon#flushed, iclass 24, count 0 2006.286.02:23:13.28#ibcon#about to write, iclass 24, count 0 2006.286.02:23:13.28#ibcon#wrote, iclass 24, count 0 2006.286.02:23:13.28#ibcon#about to read 3, iclass 24, count 0 2006.286.02:23:13.31#ibcon#read 3, iclass 24, count 0 2006.286.02:23:13.31#ibcon#about to read 4, iclass 24, count 0 2006.286.02:23:13.31#ibcon#read 4, iclass 24, count 0 2006.286.02:23:13.31#ibcon#about to read 5, iclass 24, count 0 2006.286.02:23:13.31#ibcon#read 5, iclass 24, count 0 2006.286.02:23:13.31#ibcon#about to read 6, iclass 24, count 0 2006.286.02:23:13.31#ibcon#read 6, iclass 24, count 0 2006.286.02:23:13.31#ibcon#end of sib2, iclass 24, count 0 2006.286.02:23:13.31#ibcon#*after write, iclass 24, count 0 2006.286.02:23:13.31#ibcon#*before return 0, iclass 24, count 0 2006.286.02:23:13.31#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:23:13.31#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:23:13.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.02:23:13.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.02:23:13.31$vck44/valo=6,814.99 2006.286.02:23:13.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.02:23:13.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.02:23:13.31#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:13.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:23:13.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:23:13.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:23:13.31#ibcon#enter wrdev, iclass 26, count 0 2006.286.02:23:13.31#ibcon#first serial, iclass 26, count 0 2006.286.02:23:13.31#ibcon#enter sib2, iclass 26, count 0 2006.286.02:23:13.31#ibcon#flushed, iclass 26, count 0 2006.286.02:23:13.31#ibcon#about to write, iclass 26, count 0 2006.286.02:23:13.31#ibcon#wrote, iclass 26, count 0 2006.286.02:23:13.31#ibcon#about to read 3, iclass 26, count 0 2006.286.02:23:13.33#ibcon#read 3, iclass 26, count 0 2006.286.02:23:13.33#ibcon#about to read 4, iclass 26, count 0 2006.286.02:23:13.33#ibcon#read 4, iclass 26, count 0 2006.286.02:23:13.33#ibcon#about to read 5, iclass 26, count 0 2006.286.02:23:13.33#ibcon#read 5, iclass 26, count 0 2006.286.02:23:13.33#ibcon#about to read 6, iclass 26, count 0 2006.286.02:23:13.33#ibcon#read 6, iclass 26, count 0 2006.286.02:23:13.33#ibcon#end of sib2, iclass 26, count 0 2006.286.02:23:13.33#ibcon#*mode == 0, iclass 26, count 0 2006.286.02:23:13.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.02:23:13.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.02:23:13.33#ibcon#*before write, iclass 26, count 0 2006.286.02:23:13.33#ibcon#enter sib2, iclass 26, count 0 2006.286.02:23:13.33#ibcon#flushed, iclass 26, count 0 2006.286.02:23:13.33#ibcon#about to write, iclass 26, count 0 2006.286.02:23:13.33#ibcon#wrote, iclass 26, count 0 2006.286.02:23:13.33#ibcon#about to read 3, iclass 26, count 0 2006.286.02:23:13.37#ibcon#read 3, iclass 26, count 0 2006.286.02:23:13.37#ibcon#about to read 4, iclass 26, count 0 2006.286.02:23:13.37#ibcon#read 4, iclass 26, count 0 2006.286.02:23:13.37#ibcon#about to read 5, iclass 26, count 0 2006.286.02:23:13.37#ibcon#read 5, iclass 26, count 0 2006.286.02:23:13.37#ibcon#about to read 6, iclass 26, count 0 2006.286.02:23:13.37#ibcon#read 6, iclass 26, count 0 2006.286.02:23:13.37#ibcon#end of sib2, iclass 26, count 0 2006.286.02:23:13.37#ibcon#*after write, iclass 26, count 0 2006.286.02:23:13.37#ibcon#*before return 0, iclass 26, count 0 2006.286.02:23:13.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:23:13.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:23:13.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.02:23:13.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.02:23:13.37$vck44/va=6,4 2006.286.02:23:13.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.02:23:13.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.02:23:13.37#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:13.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:23:13.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:23:13.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:23:13.43#ibcon#enter wrdev, iclass 28, count 2 2006.286.02:23:13.43#ibcon#first serial, iclass 28, count 2 2006.286.02:23:13.43#ibcon#enter sib2, iclass 28, count 2 2006.286.02:23:13.43#ibcon#flushed, iclass 28, count 2 2006.286.02:23:13.43#ibcon#about to write, iclass 28, count 2 2006.286.02:23:13.43#ibcon#wrote, iclass 28, count 2 2006.286.02:23:13.43#ibcon#about to read 3, iclass 28, count 2 2006.286.02:23:13.45#ibcon#read 3, iclass 28, count 2 2006.286.02:23:13.45#ibcon#about to read 4, iclass 28, count 2 2006.286.02:23:13.45#ibcon#read 4, iclass 28, count 2 2006.286.02:23:13.45#ibcon#about to read 5, iclass 28, count 2 2006.286.02:23:13.45#ibcon#read 5, iclass 28, count 2 2006.286.02:23:13.45#ibcon#about to read 6, iclass 28, count 2 2006.286.02:23:13.45#ibcon#read 6, iclass 28, count 2 2006.286.02:23:13.45#ibcon#end of sib2, iclass 28, count 2 2006.286.02:23:13.45#ibcon#*mode == 0, iclass 28, count 2 2006.286.02:23:13.45#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.02:23:13.45#ibcon#[25=AT06-04\r\n] 2006.286.02:23:13.45#ibcon#*before write, iclass 28, count 2 2006.286.02:23:13.45#ibcon#enter sib2, iclass 28, count 2 2006.286.02:23:13.45#ibcon#flushed, iclass 28, count 2 2006.286.02:23:13.45#ibcon#about to write, iclass 28, count 2 2006.286.02:23:13.45#ibcon#wrote, iclass 28, count 2 2006.286.02:23:13.45#ibcon#about to read 3, iclass 28, count 2 2006.286.02:23:13.48#ibcon#read 3, iclass 28, count 2 2006.286.02:23:13.48#ibcon#about to read 4, iclass 28, count 2 2006.286.02:23:13.48#ibcon#read 4, iclass 28, count 2 2006.286.02:23:13.48#ibcon#about to read 5, iclass 28, count 2 2006.286.02:23:13.48#ibcon#read 5, iclass 28, count 2 2006.286.02:23:13.48#ibcon#about to read 6, iclass 28, count 2 2006.286.02:23:13.48#ibcon#read 6, iclass 28, count 2 2006.286.02:23:13.48#ibcon#end of sib2, iclass 28, count 2 2006.286.02:23:13.48#ibcon#*after write, iclass 28, count 2 2006.286.02:23:13.48#ibcon#*before return 0, iclass 28, count 2 2006.286.02:23:13.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:23:13.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:23:13.48#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.02:23:13.48#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:13.48#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:23:13.60#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:23:13.60#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:23:13.60#ibcon#enter wrdev, iclass 28, count 0 2006.286.02:23:13.60#ibcon#first serial, iclass 28, count 0 2006.286.02:23:13.60#ibcon#enter sib2, iclass 28, count 0 2006.286.02:23:13.60#ibcon#flushed, iclass 28, count 0 2006.286.02:23:13.60#ibcon#about to write, iclass 28, count 0 2006.286.02:23:13.60#ibcon#wrote, iclass 28, count 0 2006.286.02:23:13.60#ibcon#about to read 3, iclass 28, count 0 2006.286.02:23:13.62#ibcon#read 3, iclass 28, count 0 2006.286.02:23:13.62#ibcon#about to read 4, iclass 28, count 0 2006.286.02:23:13.62#ibcon#read 4, iclass 28, count 0 2006.286.02:23:13.62#ibcon#about to read 5, iclass 28, count 0 2006.286.02:23:13.62#ibcon#read 5, iclass 28, count 0 2006.286.02:23:13.62#ibcon#about to read 6, iclass 28, count 0 2006.286.02:23:13.62#ibcon#read 6, iclass 28, count 0 2006.286.02:23:13.62#ibcon#end of sib2, iclass 28, count 0 2006.286.02:23:13.62#ibcon#*mode == 0, iclass 28, count 0 2006.286.02:23:13.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.02:23:13.62#ibcon#[25=USB\r\n] 2006.286.02:23:13.62#ibcon#*before write, iclass 28, count 0 2006.286.02:23:13.62#ibcon#enter sib2, iclass 28, count 0 2006.286.02:23:13.62#ibcon#flushed, iclass 28, count 0 2006.286.02:23:13.62#ibcon#about to write, iclass 28, count 0 2006.286.02:23:13.62#ibcon#wrote, iclass 28, count 0 2006.286.02:23:13.62#ibcon#about to read 3, iclass 28, count 0 2006.286.02:23:13.65#ibcon#read 3, iclass 28, count 0 2006.286.02:23:13.65#ibcon#about to read 4, iclass 28, count 0 2006.286.02:23:13.65#ibcon#read 4, iclass 28, count 0 2006.286.02:23:13.65#ibcon#about to read 5, iclass 28, count 0 2006.286.02:23:13.65#ibcon#read 5, iclass 28, count 0 2006.286.02:23:13.65#ibcon#about to read 6, iclass 28, count 0 2006.286.02:23:13.65#ibcon#read 6, iclass 28, count 0 2006.286.02:23:13.65#ibcon#end of sib2, iclass 28, count 0 2006.286.02:23:13.65#ibcon#*after write, iclass 28, count 0 2006.286.02:23:13.65#ibcon#*before return 0, iclass 28, count 0 2006.286.02:23:13.65#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:23:13.65#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:23:13.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.02:23:13.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.02:23:13.65$vck44/valo=7,864.99 2006.286.02:23:13.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.02:23:13.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.02:23:13.65#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:13.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:23:13.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:23:13.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:23:13.65#ibcon#enter wrdev, iclass 30, count 0 2006.286.02:23:13.65#ibcon#first serial, iclass 30, count 0 2006.286.02:23:13.65#ibcon#enter sib2, iclass 30, count 0 2006.286.02:23:13.65#ibcon#flushed, iclass 30, count 0 2006.286.02:23:13.65#ibcon#about to write, iclass 30, count 0 2006.286.02:23:13.65#ibcon#wrote, iclass 30, count 0 2006.286.02:23:13.65#ibcon#about to read 3, iclass 30, count 0 2006.286.02:23:13.67#ibcon#read 3, iclass 30, count 0 2006.286.02:23:13.67#ibcon#about to read 4, iclass 30, count 0 2006.286.02:23:13.67#ibcon#read 4, iclass 30, count 0 2006.286.02:23:13.67#ibcon#about to read 5, iclass 30, count 0 2006.286.02:23:13.67#ibcon#read 5, iclass 30, count 0 2006.286.02:23:13.67#ibcon#about to read 6, iclass 30, count 0 2006.286.02:23:13.67#ibcon#read 6, iclass 30, count 0 2006.286.02:23:13.67#ibcon#end of sib2, iclass 30, count 0 2006.286.02:23:13.67#ibcon#*mode == 0, iclass 30, count 0 2006.286.02:23:13.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.02:23:13.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.02:23:13.67#ibcon#*before write, iclass 30, count 0 2006.286.02:23:13.67#ibcon#enter sib2, iclass 30, count 0 2006.286.02:23:13.67#ibcon#flushed, iclass 30, count 0 2006.286.02:23:13.67#ibcon#about to write, iclass 30, count 0 2006.286.02:23:13.67#ibcon#wrote, iclass 30, count 0 2006.286.02:23:13.67#ibcon#about to read 3, iclass 30, count 0 2006.286.02:23:13.71#ibcon#read 3, iclass 30, count 0 2006.286.02:23:13.71#ibcon#about to read 4, iclass 30, count 0 2006.286.02:23:13.71#ibcon#read 4, iclass 30, count 0 2006.286.02:23:13.71#ibcon#about to read 5, iclass 30, count 0 2006.286.02:23:13.71#ibcon#read 5, iclass 30, count 0 2006.286.02:23:13.71#ibcon#about to read 6, iclass 30, count 0 2006.286.02:23:13.71#ibcon#read 6, iclass 30, count 0 2006.286.02:23:13.71#ibcon#end of sib2, iclass 30, count 0 2006.286.02:23:13.71#ibcon#*after write, iclass 30, count 0 2006.286.02:23:13.71#ibcon#*before return 0, iclass 30, count 0 2006.286.02:23:13.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:23:13.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:23:13.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.02:23:13.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.02:23:13.71$vck44/va=7,4 2006.286.02:23:13.71#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.02:23:13.71#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.02:23:13.71#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:13.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:23:13.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:23:13.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:23:13.77#ibcon#enter wrdev, iclass 32, count 2 2006.286.02:23:13.77#ibcon#first serial, iclass 32, count 2 2006.286.02:23:13.77#ibcon#enter sib2, iclass 32, count 2 2006.286.02:23:13.77#ibcon#flushed, iclass 32, count 2 2006.286.02:23:13.77#ibcon#about to write, iclass 32, count 2 2006.286.02:23:13.77#ibcon#wrote, iclass 32, count 2 2006.286.02:23:13.77#ibcon#about to read 3, iclass 32, count 2 2006.286.02:23:13.79#ibcon#read 3, iclass 32, count 2 2006.286.02:23:13.79#ibcon#about to read 4, iclass 32, count 2 2006.286.02:23:13.79#ibcon#read 4, iclass 32, count 2 2006.286.02:23:13.79#ibcon#about to read 5, iclass 32, count 2 2006.286.02:23:13.79#ibcon#read 5, iclass 32, count 2 2006.286.02:23:13.79#ibcon#about to read 6, iclass 32, count 2 2006.286.02:23:13.79#ibcon#read 6, iclass 32, count 2 2006.286.02:23:13.79#ibcon#end of sib2, iclass 32, count 2 2006.286.02:23:13.79#ibcon#*mode == 0, iclass 32, count 2 2006.286.02:23:13.79#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.02:23:13.79#ibcon#[25=AT07-04\r\n] 2006.286.02:23:13.79#ibcon#*before write, iclass 32, count 2 2006.286.02:23:13.79#ibcon#enter sib2, iclass 32, count 2 2006.286.02:23:13.79#ibcon#flushed, iclass 32, count 2 2006.286.02:23:13.79#ibcon#about to write, iclass 32, count 2 2006.286.02:23:13.79#ibcon#wrote, iclass 32, count 2 2006.286.02:23:13.79#ibcon#about to read 3, iclass 32, count 2 2006.286.02:23:13.82#ibcon#read 3, iclass 32, count 2 2006.286.02:23:13.82#ibcon#about to read 4, iclass 32, count 2 2006.286.02:23:13.82#ibcon#read 4, iclass 32, count 2 2006.286.02:23:13.82#ibcon#about to read 5, iclass 32, count 2 2006.286.02:23:13.82#ibcon#read 5, iclass 32, count 2 2006.286.02:23:13.82#ibcon#about to read 6, iclass 32, count 2 2006.286.02:23:13.82#ibcon#read 6, iclass 32, count 2 2006.286.02:23:13.82#ibcon#end of sib2, iclass 32, count 2 2006.286.02:23:13.82#ibcon#*after write, iclass 32, count 2 2006.286.02:23:13.82#ibcon#*before return 0, iclass 32, count 2 2006.286.02:23:13.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:23:13.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:23:13.82#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.02:23:13.82#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:13.82#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:23:13.94#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:23:13.94#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:23:13.94#ibcon#enter wrdev, iclass 32, count 0 2006.286.02:23:13.94#ibcon#first serial, iclass 32, count 0 2006.286.02:23:13.94#ibcon#enter sib2, iclass 32, count 0 2006.286.02:23:13.94#ibcon#flushed, iclass 32, count 0 2006.286.02:23:13.94#ibcon#about to write, iclass 32, count 0 2006.286.02:23:13.94#ibcon#wrote, iclass 32, count 0 2006.286.02:23:13.94#ibcon#about to read 3, iclass 32, count 0 2006.286.02:23:13.96#ibcon#read 3, iclass 32, count 0 2006.286.02:23:13.96#ibcon#about to read 4, iclass 32, count 0 2006.286.02:23:13.96#ibcon#read 4, iclass 32, count 0 2006.286.02:23:13.96#ibcon#about to read 5, iclass 32, count 0 2006.286.02:23:13.96#ibcon#read 5, iclass 32, count 0 2006.286.02:23:13.96#ibcon#about to read 6, iclass 32, count 0 2006.286.02:23:13.96#ibcon#read 6, iclass 32, count 0 2006.286.02:23:13.96#ibcon#end of sib2, iclass 32, count 0 2006.286.02:23:13.96#ibcon#*mode == 0, iclass 32, count 0 2006.286.02:23:13.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.02:23:13.96#ibcon#[25=USB\r\n] 2006.286.02:23:13.96#ibcon#*before write, iclass 32, count 0 2006.286.02:23:13.96#ibcon#enter sib2, iclass 32, count 0 2006.286.02:23:13.96#ibcon#flushed, iclass 32, count 0 2006.286.02:23:13.96#ibcon#about to write, iclass 32, count 0 2006.286.02:23:13.96#ibcon#wrote, iclass 32, count 0 2006.286.02:23:13.96#ibcon#about to read 3, iclass 32, count 0 2006.286.02:23:13.99#ibcon#read 3, iclass 32, count 0 2006.286.02:23:13.99#ibcon#about to read 4, iclass 32, count 0 2006.286.02:23:13.99#ibcon#read 4, iclass 32, count 0 2006.286.02:23:13.99#ibcon#about to read 5, iclass 32, count 0 2006.286.02:23:13.99#ibcon#read 5, iclass 32, count 0 2006.286.02:23:13.99#ibcon#about to read 6, iclass 32, count 0 2006.286.02:23:13.99#ibcon#read 6, iclass 32, count 0 2006.286.02:23:13.99#ibcon#end of sib2, iclass 32, count 0 2006.286.02:23:13.99#ibcon#*after write, iclass 32, count 0 2006.286.02:23:13.99#ibcon#*before return 0, iclass 32, count 0 2006.286.02:23:13.99#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:23:13.99#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:23:13.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.02:23:13.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.02:23:13.99$vck44/valo=8,884.99 2006.286.02:23:13.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.02:23:13.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.02:23:13.99#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:13.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:23:13.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:23:13.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:23:13.99#ibcon#enter wrdev, iclass 34, count 0 2006.286.02:23:13.99#ibcon#first serial, iclass 34, count 0 2006.286.02:23:13.99#ibcon#enter sib2, iclass 34, count 0 2006.286.02:23:13.99#ibcon#flushed, iclass 34, count 0 2006.286.02:23:13.99#ibcon#about to write, iclass 34, count 0 2006.286.02:23:13.99#ibcon#wrote, iclass 34, count 0 2006.286.02:23:13.99#ibcon#about to read 3, iclass 34, count 0 2006.286.02:23:14.01#ibcon#read 3, iclass 34, count 0 2006.286.02:23:14.01#ibcon#about to read 4, iclass 34, count 0 2006.286.02:23:14.01#ibcon#read 4, iclass 34, count 0 2006.286.02:23:14.01#ibcon#about to read 5, iclass 34, count 0 2006.286.02:23:14.01#ibcon#read 5, iclass 34, count 0 2006.286.02:23:14.01#ibcon#about to read 6, iclass 34, count 0 2006.286.02:23:14.01#ibcon#read 6, iclass 34, count 0 2006.286.02:23:14.01#ibcon#end of sib2, iclass 34, count 0 2006.286.02:23:14.01#ibcon#*mode == 0, iclass 34, count 0 2006.286.02:23:14.01#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.02:23:14.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.02:23:14.01#ibcon#*before write, iclass 34, count 0 2006.286.02:23:14.01#ibcon#enter sib2, iclass 34, count 0 2006.286.02:23:14.01#ibcon#flushed, iclass 34, count 0 2006.286.02:23:14.01#ibcon#about to write, iclass 34, count 0 2006.286.02:23:14.01#ibcon#wrote, iclass 34, count 0 2006.286.02:23:14.01#ibcon#about to read 3, iclass 34, count 0 2006.286.02:23:14.05#ibcon#read 3, iclass 34, count 0 2006.286.02:23:14.05#ibcon#about to read 4, iclass 34, count 0 2006.286.02:23:14.05#ibcon#read 4, iclass 34, count 0 2006.286.02:23:14.05#ibcon#about to read 5, iclass 34, count 0 2006.286.02:23:14.05#ibcon#read 5, iclass 34, count 0 2006.286.02:23:14.05#ibcon#about to read 6, iclass 34, count 0 2006.286.02:23:14.05#ibcon#read 6, iclass 34, count 0 2006.286.02:23:14.05#ibcon#end of sib2, iclass 34, count 0 2006.286.02:23:14.05#ibcon#*after write, iclass 34, count 0 2006.286.02:23:14.05#ibcon#*before return 0, iclass 34, count 0 2006.286.02:23:14.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:23:14.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:23:14.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.02:23:14.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.02:23:14.05$vck44/va=8,3 2006.286.02:23:14.05#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.02:23:14.05#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.02:23:14.05#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:14.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.02:23:14.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.02:23:14.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.02:23:14.11#ibcon#enter wrdev, iclass 36, count 2 2006.286.02:23:14.11#ibcon#first serial, iclass 36, count 2 2006.286.02:23:14.11#ibcon#enter sib2, iclass 36, count 2 2006.286.02:23:14.11#ibcon#flushed, iclass 36, count 2 2006.286.02:23:14.11#ibcon#about to write, iclass 36, count 2 2006.286.02:23:14.11#ibcon#wrote, iclass 36, count 2 2006.286.02:23:14.11#ibcon#about to read 3, iclass 36, count 2 2006.286.02:23:14.13#ibcon#read 3, iclass 36, count 2 2006.286.02:23:14.13#ibcon#about to read 4, iclass 36, count 2 2006.286.02:23:14.13#ibcon#read 4, iclass 36, count 2 2006.286.02:23:14.13#ibcon#about to read 5, iclass 36, count 2 2006.286.02:23:14.13#ibcon#read 5, iclass 36, count 2 2006.286.02:23:14.13#ibcon#about to read 6, iclass 36, count 2 2006.286.02:23:14.13#ibcon#read 6, iclass 36, count 2 2006.286.02:23:14.13#ibcon#end of sib2, iclass 36, count 2 2006.286.02:23:14.13#ibcon#*mode == 0, iclass 36, count 2 2006.286.02:23:14.13#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.02:23:14.13#ibcon#[25=AT08-03\r\n] 2006.286.02:23:14.13#ibcon#*before write, iclass 36, count 2 2006.286.02:23:14.13#ibcon#enter sib2, iclass 36, count 2 2006.286.02:23:14.13#ibcon#flushed, iclass 36, count 2 2006.286.02:23:14.13#ibcon#about to write, iclass 36, count 2 2006.286.02:23:14.13#ibcon#wrote, iclass 36, count 2 2006.286.02:23:14.13#ibcon#about to read 3, iclass 36, count 2 2006.286.02:23:14.16#ibcon#read 3, iclass 36, count 2 2006.286.02:23:14.16#ibcon#about to read 4, iclass 36, count 2 2006.286.02:23:14.16#ibcon#read 4, iclass 36, count 2 2006.286.02:23:14.16#ibcon#about to read 5, iclass 36, count 2 2006.286.02:23:14.16#ibcon#read 5, iclass 36, count 2 2006.286.02:23:14.16#ibcon#about to read 6, iclass 36, count 2 2006.286.02:23:14.16#ibcon#read 6, iclass 36, count 2 2006.286.02:23:14.16#ibcon#end of sib2, iclass 36, count 2 2006.286.02:23:14.16#ibcon#*after write, iclass 36, count 2 2006.286.02:23:14.16#ibcon#*before return 0, iclass 36, count 2 2006.286.02:23:14.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.02:23:14.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.02:23:14.16#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.02:23:14.16#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:14.16#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.02:23:14.28#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.02:23:14.28#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.02:23:14.28#ibcon#enter wrdev, iclass 36, count 0 2006.286.02:23:14.28#ibcon#first serial, iclass 36, count 0 2006.286.02:23:14.28#ibcon#enter sib2, iclass 36, count 0 2006.286.02:23:14.28#ibcon#flushed, iclass 36, count 0 2006.286.02:23:14.28#ibcon#about to write, iclass 36, count 0 2006.286.02:23:14.28#ibcon#wrote, iclass 36, count 0 2006.286.02:23:14.28#ibcon#about to read 3, iclass 36, count 0 2006.286.02:23:14.30#ibcon#read 3, iclass 36, count 0 2006.286.02:23:14.30#ibcon#about to read 4, iclass 36, count 0 2006.286.02:23:14.30#ibcon#read 4, iclass 36, count 0 2006.286.02:23:14.30#ibcon#about to read 5, iclass 36, count 0 2006.286.02:23:14.30#ibcon#read 5, iclass 36, count 0 2006.286.02:23:14.30#ibcon#about to read 6, iclass 36, count 0 2006.286.02:23:14.30#ibcon#read 6, iclass 36, count 0 2006.286.02:23:14.30#ibcon#end of sib2, iclass 36, count 0 2006.286.02:23:14.30#ibcon#*mode == 0, iclass 36, count 0 2006.286.02:23:14.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.02:23:14.30#ibcon#[25=USB\r\n] 2006.286.02:23:14.30#ibcon#*before write, iclass 36, count 0 2006.286.02:23:14.30#ibcon#enter sib2, iclass 36, count 0 2006.286.02:23:14.30#ibcon#flushed, iclass 36, count 0 2006.286.02:23:14.30#ibcon#about to write, iclass 36, count 0 2006.286.02:23:14.30#ibcon#wrote, iclass 36, count 0 2006.286.02:23:14.30#ibcon#about to read 3, iclass 36, count 0 2006.286.02:23:14.33#ibcon#read 3, iclass 36, count 0 2006.286.02:23:14.33#ibcon#about to read 4, iclass 36, count 0 2006.286.02:23:14.33#ibcon#read 4, iclass 36, count 0 2006.286.02:23:14.33#ibcon#about to read 5, iclass 36, count 0 2006.286.02:23:14.33#ibcon#read 5, iclass 36, count 0 2006.286.02:23:14.33#ibcon#about to read 6, iclass 36, count 0 2006.286.02:23:14.33#ibcon#read 6, iclass 36, count 0 2006.286.02:23:14.33#ibcon#end of sib2, iclass 36, count 0 2006.286.02:23:14.33#ibcon#*after write, iclass 36, count 0 2006.286.02:23:14.33#ibcon#*before return 0, iclass 36, count 0 2006.286.02:23:14.33#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.02:23:14.33#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.02:23:14.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.02:23:14.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.02:23:14.33$vck44/vblo=1,629.99 2006.286.02:23:14.33#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.02:23:14.33#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.02:23:14.33#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:14.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.02:23:14.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.02:23:14.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.02:23:14.33#ibcon#enter wrdev, iclass 38, count 0 2006.286.02:23:14.33#ibcon#first serial, iclass 38, count 0 2006.286.02:23:14.33#ibcon#enter sib2, iclass 38, count 0 2006.286.02:23:14.33#ibcon#flushed, iclass 38, count 0 2006.286.02:23:14.33#ibcon#about to write, iclass 38, count 0 2006.286.02:23:14.33#ibcon#wrote, iclass 38, count 0 2006.286.02:23:14.33#ibcon#about to read 3, iclass 38, count 0 2006.286.02:23:14.35#ibcon#read 3, iclass 38, count 0 2006.286.02:23:14.35#ibcon#about to read 4, iclass 38, count 0 2006.286.02:23:14.35#ibcon#read 4, iclass 38, count 0 2006.286.02:23:14.35#ibcon#about to read 5, iclass 38, count 0 2006.286.02:23:14.35#ibcon#read 5, iclass 38, count 0 2006.286.02:23:14.35#ibcon#about to read 6, iclass 38, count 0 2006.286.02:23:14.35#ibcon#read 6, iclass 38, count 0 2006.286.02:23:14.35#ibcon#end of sib2, iclass 38, count 0 2006.286.02:23:14.35#ibcon#*mode == 0, iclass 38, count 0 2006.286.02:23:14.35#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.02:23:14.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.02:23:14.35#ibcon#*before write, iclass 38, count 0 2006.286.02:23:14.35#ibcon#enter sib2, iclass 38, count 0 2006.286.02:23:14.35#ibcon#flushed, iclass 38, count 0 2006.286.02:23:14.35#ibcon#about to write, iclass 38, count 0 2006.286.02:23:14.35#ibcon#wrote, iclass 38, count 0 2006.286.02:23:14.35#ibcon#about to read 3, iclass 38, count 0 2006.286.02:23:14.39#ibcon#read 3, iclass 38, count 0 2006.286.02:23:14.39#ibcon#about to read 4, iclass 38, count 0 2006.286.02:23:14.39#ibcon#read 4, iclass 38, count 0 2006.286.02:23:14.39#ibcon#about to read 5, iclass 38, count 0 2006.286.02:23:14.39#ibcon#read 5, iclass 38, count 0 2006.286.02:23:14.39#ibcon#about to read 6, iclass 38, count 0 2006.286.02:23:14.39#ibcon#read 6, iclass 38, count 0 2006.286.02:23:14.39#ibcon#end of sib2, iclass 38, count 0 2006.286.02:23:14.39#ibcon#*after write, iclass 38, count 0 2006.286.02:23:14.39#ibcon#*before return 0, iclass 38, count 0 2006.286.02:23:14.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.02:23:14.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.02:23:14.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.02:23:14.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.02:23:14.39$vck44/vb=1,4 2006.286.02:23:14.39#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.02:23:14.39#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.02:23:14.39#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:14.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.02:23:14.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.02:23:14.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.02:23:14.39#ibcon#enter wrdev, iclass 40, count 2 2006.286.02:23:14.39#ibcon#first serial, iclass 40, count 2 2006.286.02:23:14.39#ibcon#enter sib2, iclass 40, count 2 2006.286.02:23:14.39#ibcon#flushed, iclass 40, count 2 2006.286.02:23:14.39#ibcon#about to write, iclass 40, count 2 2006.286.02:23:14.39#ibcon#wrote, iclass 40, count 2 2006.286.02:23:14.39#ibcon#about to read 3, iclass 40, count 2 2006.286.02:23:14.41#ibcon#read 3, iclass 40, count 2 2006.286.02:23:14.41#ibcon#about to read 4, iclass 40, count 2 2006.286.02:23:14.41#ibcon#read 4, iclass 40, count 2 2006.286.02:23:14.41#ibcon#about to read 5, iclass 40, count 2 2006.286.02:23:14.41#ibcon#read 5, iclass 40, count 2 2006.286.02:23:14.41#ibcon#about to read 6, iclass 40, count 2 2006.286.02:23:14.41#ibcon#read 6, iclass 40, count 2 2006.286.02:23:14.41#ibcon#end of sib2, iclass 40, count 2 2006.286.02:23:14.41#ibcon#*mode == 0, iclass 40, count 2 2006.286.02:23:14.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.02:23:14.41#ibcon#[27=AT01-04\r\n] 2006.286.02:23:14.41#ibcon#*before write, iclass 40, count 2 2006.286.02:23:14.41#ibcon#enter sib2, iclass 40, count 2 2006.286.02:23:14.41#ibcon#flushed, iclass 40, count 2 2006.286.02:23:14.41#ibcon#about to write, iclass 40, count 2 2006.286.02:23:14.41#ibcon#wrote, iclass 40, count 2 2006.286.02:23:14.41#ibcon#about to read 3, iclass 40, count 2 2006.286.02:23:14.44#ibcon#read 3, iclass 40, count 2 2006.286.02:23:14.44#ibcon#about to read 4, iclass 40, count 2 2006.286.02:23:14.44#ibcon#read 4, iclass 40, count 2 2006.286.02:23:14.44#ibcon#about to read 5, iclass 40, count 2 2006.286.02:23:14.44#ibcon#read 5, iclass 40, count 2 2006.286.02:23:14.44#ibcon#about to read 6, iclass 40, count 2 2006.286.02:23:14.44#ibcon#read 6, iclass 40, count 2 2006.286.02:23:14.44#ibcon#end of sib2, iclass 40, count 2 2006.286.02:23:14.44#ibcon#*after write, iclass 40, count 2 2006.286.02:23:14.44#ibcon#*before return 0, iclass 40, count 2 2006.286.02:23:14.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.02:23:14.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.02:23:14.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.02:23:14.44#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:14.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.02:23:14.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.02:23:14.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.02:23:14.56#ibcon#enter wrdev, iclass 40, count 0 2006.286.02:23:14.56#ibcon#first serial, iclass 40, count 0 2006.286.02:23:14.56#ibcon#enter sib2, iclass 40, count 0 2006.286.02:23:14.56#ibcon#flushed, iclass 40, count 0 2006.286.02:23:14.56#ibcon#about to write, iclass 40, count 0 2006.286.02:23:14.56#ibcon#wrote, iclass 40, count 0 2006.286.02:23:14.56#ibcon#about to read 3, iclass 40, count 0 2006.286.02:23:14.58#ibcon#read 3, iclass 40, count 0 2006.286.02:23:14.58#ibcon#about to read 4, iclass 40, count 0 2006.286.02:23:14.58#ibcon#read 4, iclass 40, count 0 2006.286.02:23:14.58#ibcon#about to read 5, iclass 40, count 0 2006.286.02:23:14.58#ibcon#read 5, iclass 40, count 0 2006.286.02:23:14.58#ibcon#about to read 6, iclass 40, count 0 2006.286.02:23:14.58#ibcon#read 6, iclass 40, count 0 2006.286.02:23:14.58#ibcon#end of sib2, iclass 40, count 0 2006.286.02:23:14.58#ibcon#*mode == 0, iclass 40, count 0 2006.286.02:23:14.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.02:23:14.58#ibcon#[27=USB\r\n] 2006.286.02:23:14.58#ibcon#*before write, iclass 40, count 0 2006.286.02:23:14.58#ibcon#enter sib2, iclass 40, count 0 2006.286.02:23:14.58#ibcon#flushed, iclass 40, count 0 2006.286.02:23:14.58#ibcon#about to write, iclass 40, count 0 2006.286.02:23:14.58#ibcon#wrote, iclass 40, count 0 2006.286.02:23:14.58#ibcon#about to read 3, iclass 40, count 0 2006.286.02:23:14.61#ibcon#read 3, iclass 40, count 0 2006.286.02:23:14.61#ibcon#about to read 4, iclass 40, count 0 2006.286.02:23:14.61#ibcon#read 4, iclass 40, count 0 2006.286.02:23:14.61#ibcon#about to read 5, iclass 40, count 0 2006.286.02:23:14.61#ibcon#read 5, iclass 40, count 0 2006.286.02:23:14.61#ibcon#about to read 6, iclass 40, count 0 2006.286.02:23:14.61#ibcon#read 6, iclass 40, count 0 2006.286.02:23:14.61#ibcon#end of sib2, iclass 40, count 0 2006.286.02:23:14.61#ibcon#*after write, iclass 40, count 0 2006.286.02:23:14.61#ibcon#*before return 0, iclass 40, count 0 2006.286.02:23:14.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.02:23:14.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.02:23:14.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.02:23:14.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.02:23:14.61$vck44/vblo=2,634.99 2006.286.02:23:14.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.02:23:14.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.02:23:14.61#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:14.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:23:14.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:23:14.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:23:14.61#ibcon#enter wrdev, iclass 4, count 0 2006.286.02:23:14.61#ibcon#first serial, iclass 4, count 0 2006.286.02:23:14.61#ibcon#enter sib2, iclass 4, count 0 2006.286.02:23:14.61#ibcon#flushed, iclass 4, count 0 2006.286.02:23:14.61#ibcon#about to write, iclass 4, count 0 2006.286.02:23:14.61#ibcon#wrote, iclass 4, count 0 2006.286.02:23:14.61#ibcon#about to read 3, iclass 4, count 0 2006.286.02:23:14.63#ibcon#read 3, iclass 4, count 0 2006.286.02:23:14.63#ibcon#about to read 4, iclass 4, count 0 2006.286.02:23:14.63#ibcon#read 4, iclass 4, count 0 2006.286.02:23:14.63#ibcon#about to read 5, iclass 4, count 0 2006.286.02:23:14.63#ibcon#read 5, iclass 4, count 0 2006.286.02:23:14.63#ibcon#about to read 6, iclass 4, count 0 2006.286.02:23:14.63#ibcon#read 6, iclass 4, count 0 2006.286.02:23:14.63#ibcon#end of sib2, iclass 4, count 0 2006.286.02:23:14.63#ibcon#*mode == 0, iclass 4, count 0 2006.286.02:23:14.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.02:23:14.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.02:23:14.63#ibcon#*before write, iclass 4, count 0 2006.286.02:23:14.63#ibcon#enter sib2, iclass 4, count 0 2006.286.02:23:14.63#ibcon#flushed, iclass 4, count 0 2006.286.02:23:14.63#ibcon#about to write, iclass 4, count 0 2006.286.02:23:14.63#ibcon#wrote, iclass 4, count 0 2006.286.02:23:14.63#ibcon#about to read 3, iclass 4, count 0 2006.286.02:23:14.67#ibcon#read 3, iclass 4, count 0 2006.286.02:23:14.67#ibcon#about to read 4, iclass 4, count 0 2006.286.02:23:14.67#ibcon#read 4, iclass 4, count 0 2006.286.02:23:14.67#ibcon#about to read 5, iclass 4, count 0 2006.286.02:23:14.67#ibcon#read 5, iclass 4, count 0 2006.286.02:23:14.67#ibcon#about to read 6, iclass 4, count 0 2006.286.02:23:14.67#ibcon#read 6, iclass 4, count 0 2006.286.02:23:14.67#ibcon#end of sib2, iclass 4, count 0 2006.286.02:23:14.67#ibcon#*after write, iclass 4, count 0 2006.286.02:23:14.67#ibcon#*before return 0, iclass 4, count 0 2006.286.02:23:14.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:23:14.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:23:14.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.02:23:14.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.02:23:14.67$vck44/vb=2,5 2006.286.02:23:14.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.02:23:14.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.02:23:14.67#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:14.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:23:14.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:23:14.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:23:14.73#ibcon#enter wrdev, iclass 6, count 2 2006.286.02:23:14.73#ibcon#first serial, iclass 6, count 2 2006.286.02:23:14.73#ibcon#enter sib2, iclass 6, count 2 2006.286.02:23:14.73#ibcon#flushed, iclass 6, count 2 2006.286.02:23:14.73#ibcon#about to write, iclass 6, count 2 2006.286.02:23:14.73#ibcon#wrote, iclass 6, count 2 2006.286.02:23:14.73#ibcon#about to read 3, iclass 6, count 2 2006.286.02:23:14.75#ibcon#read 3, iclass 6, count 2 2006.286.02:23:14.75#ibcon#about to read 4, iclass 6, count 2 2006.286.02:23:14.75#ibcon#read 4, iclass 6, count 2 2006.286.02:23:14.75#ibcon#about to read 5, iclass 6, count 2 2006.286.02:23:14.75#ibcon#read 5, iclass 6, count 2 2006.286.02:23:14.75#ibcon#about to read 6, iclass 6, count 2 2006.286.02:23:14.75#ibcon#read 6, iclass 6, count 2 2006.286.02:23:14.75#ibcon#end of sib2, iclass 6, count 2 2006.286.02:23:14.75#ibcon#*mode == 0, iclass 6, count 2 2006.286.02:23:14.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.02:23:14.75#ibcon#[27=AT02-05\r\n] 2006.286.02:23:14.75#ibcon#*before write, iclass 6, count 2 2006.286.02:23:14.75#ibcon#enter sib2, iclass 6, count 2 2006.286.02:23:14.75#ibcon#flushed, iclass 6, count 2 2006.286.02:23:14.75#ibcon#about to write, iclass 6, count 2 2006.286.02:23:14.75#ibcon#wrote, iclass 6, count 2 2006.286.02:23:14.75#ibcon#about to read 3, iclass 6, count 2 2006.286.02:23:14.78#ibcon#read 3, iclass 6, count 2 2006.286.02:23:14.78#ibcon#about to read 4, iclass 6, count 2 2006.286.02:23:14.78#ibcon#read 4, iclass 6, count 2 2006.286.02:23:14.78#ibcon#about to read 5, iclass 6, count 2 2006.286.02:23:14.78#ibcon#read 5, iclass 6, count 2 2006.286.02:23:14.78#ibcon#about to read 6, iclass 6, count 2 2006.286.02:23:14.78#ibcon#read 6, iclass 6, count 2 2006.286.02:23:14.78#ibcon#end of sib2, iclass 6, count 2 2006.286.02:23:14.78#ibcon#*after write, iclass 6, count 2 2006.286.02:23:14.78#ibcon#*before return 0, iclass 6, count 2 2006.286.02:23:14.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:23:14.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:23:14.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.02:23:14.78#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:14.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:23:14.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:23:14.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:23:14.90#ibcon#enter wrdev, iclass 6, count 0 2006.286.02:23:14.90#ibcon#first serial, iclass 6, count 0 2006.286.02:23:14.90#ibcon#enter sib2, iclass 6, count 0 2006.286.02:23:14.90#ibcon#flushed, iclass 6, count 0 2006.286.02:23:14.90#ibcon#about to write, iclass 6, count 0 2006.286.02:23:14.90#ibcon#wrote, iclass 6, count 0 2006.286.02:23:14.90#ibcon#about to read 3, iclass 6, count 0 2006.286.02:23:14.92#ibcon#read 3, iclass 6, count 0 2006.286.02:23:14.92#ibcon#about to read 4, iclass 6, count 0 2006.286.02:23:14.92#ibcon#read 4, iclass 6, count 0 2006.286.02:23:14.92#ibcon#about to read 5, iclass 6, count 0 2006.286.02:23:14.92#ibcon#read 5, iclass 6, count 0 2006.286.02:23:14.92#ibcon#about to read 6, iclass 6, count 0 2006.286.02:23:14.92#ibcon#read 6, iclass 6, count 0 2006.286.02:23:14.92#ibcon#end of sib2, iclass 6, count 0 2006.286.02:23:14.92#ibcon#*mode == 0, iclass 6, count 0 2006.286.02:23:14.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.02:23:14.92#ibcon#[27=USB\r\n] 2006.286.02:23:14.92#ibcon#*before write, iclass 6, count 0 2006.286.02:23:14.92#ibcon#enter sib2, iclass 6, count 0 2006.286.02:23:14.92#ibcon#flushed, iclass 6, count 0 2006.286.02:23:14.92#ibcon#about to write, iclass 6, count 0 2006.286.02:23:14.92#ibcon#wrote, iclass 6, count 0 2006.286.02:23:14.92#ibcon#about to read 3, iclass 6, count 0 2006.286.02:23:14.95#ibcon#read 3, iclass 6, count 0 2006.286.02:23:14.95#ibcon#about to read 4, iclass 6, count 0 2006.286.02:23:14.95#ibcon#read 4, iclass 6, count 0 2006.286.02:23:14.95#ibcon#about to read 5, iclass 6, count 0 2006.286.02:23:14.95#ibcon#read 5, iclass 6, count 0 2006.286.02:23:14.95#ibcon#about to read 6, iclass 6, count 0 2006.286.02:23:14.95#ibcon#read 6, iclass 6, count 0 2006.286.02:23:14.95#ibcon#end of sib2, iclass 6, count 0 2006.286.02:23:14.95#ibcon#*after write, iclass 6, count 0 2006.286.02:23:14.95#ibcon#*before return 0, iclass 6, count 0 2006.286.02:23:14.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:23:14.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:23:14.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.02:23:14.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.02:23:14.95$vck44/vblo=3,649.99 2006.286.02:23:14.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.02:23:14.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.02:23:14.95#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:14.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:23:14.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:23:14.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:23:14.95#ibcon#enter wrdev, iclass 10, count 0 2006.286.02:23:14.95#ibcon#first serial, iclass 10, count 0 2006.286.02:23:14.95#ibcon#enter sib2, iclass 10, count 0 2006.286.02:23:14.95#ibcon#flushed, iclass 10, count 0 2006.286.02:23:14.95#ibcon#about to write, iclass 10, count 0 2006.286.02:23:14.95#ibcon#wrote, iclass 10, count 0 2006.286.02:23:14.95#ibcon#about to read 3, iclass 10, count 0 2006.286.02:23:14.97#ibcon#read 3, iclass 10, count 0 2006.286.02:23:14.97#ibcon#about to read 4, iclass 10, count 0 2006.286.02:23:14.97#ibcon#read 4, iclass 10, count 0 2006.286.02:23:14.97#ibcon#about to read 5, iclass 10, count 0 2006.286.02:23:14.97#ibcon#read 5, iclass 10, count 0 2006.286.02:23:14.97#ibcon#about to read 6, iclass 10, count 0 2006.286.02:23:14.97#ibcon#read 6, iclass 10, count 0 2006.286.02:23:14.97#ibcon#end of sib2, iclass 10, count 0 2006.286.02:23:14.97#ibcon#*mode == 0, iclass 10, count 0 2006.286.02:23:14.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.02:23:14.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.02:23:14.97#ibcon#*before write, iclass 10, count 0 2006.286.02:23:14.97#ibcon#enter sib2, iclass 10, count 0 2006.286.02:23:14.97#ibcon#flushed, iclass 10, count 0 2006.286.02:23:14.97#ibcon#about to write, iclass 10, count 0 2006.286.02:23:14.97#ibcon#wrote, iclass 10, count 0 2006.286.02:23:14.97#ibcon#about to read 3, iclass 10, count 0 2006.286.02:23:15.01#ibcon#read 3, iclass 10, count 0 2006.286.02:23:15.01#ibcon#about to read 4, iclass 10, count 0 2006.286.02:23:15.01#ibcon#read 4, iclass 10, count 0 2006.286.02:23:15.01#ibcon#about to read 5, iclass 10, count 0 2006.286.02:23:15.01#ibcon#read 5, iclass 10, count 0 2006.286.02:23:15.01#ibcon#about to read 6, iclass 10, count 0 2006.286.02:23:15.01#ibcon#read 6, iclass 10, count 0 2006.286.02:23:15.01#ibcon#end of sib2, iclass 10, count 0 2006.286.02:23:15.01#ibcon#*after write, iclass 10, count 0 2006.286.02:23:15.01#ibcon#*before return 0, iclass 10, count 0 2006.286.02:23:15.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:23:15.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:23:15.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.02:23:15.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.02:23:15.01$vck44/vb=3,4 2006.286.02:23:15.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.02:23:15.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.02:23:15.01#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:15.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:23:15.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:23:15.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:23:15.07#ibcon#enter wrdev, iclass 12, count 2 2006.286.02:23:15.07#ibcon#first serial, iclass 12, count 2 2006.286.02:23:15.07#ibcon#enter sib2, iclass 12, count 2 2006.286.02:23:15.07#ibcon#flushed, iclass 12, count 2 2006.286.02:23:15.07#ibcon#about to write, iclass 12, count 2 2006.286.02:23:15.07#ibcon#wrote, iclass 12, count 2 2006.286.02:23:15.07#ibcon#about to read 3, iclass 12, count 2 2006.286.02:23:15.09#ibcon#read 3, iclass 12, count 2 2006.286.02:23:15.09#ibcon#about to read 4, iclass 12, count 2 2006.286.02:23:15.09#ibcon#read 4, iclass 12, count 2 2006.286.02:23:15.09#ibcon#about to read 5, iclass 12, count 2 2006.286.02:23:15.09#ibcon#read 5, iclass 12, count 2 2006.286.02:23:15.09#ibcon#about to read 6, iclass 12, count 2 2006.286.02:23:15.09#ibcon#read 6, iclass 12, count 2 2006.286.02:23:15.09#ibcon#end of sib2, iclass 12, count 2 2006.286.02:23:15.09#ibcon#*mode == 0, iclass 12, count 2 2006.286.02:23:15.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.02:23:15.09#ibcon#[27=AT03-04\r\n] 2006.286.02:23:15.09#ibcon#*before write, iclass 12, count 2 2006.286.02:23:15.09#ibcon#enter sib2, iclass 12, count 2 2006.286.02:23:15.09#ibcon#flushed, iclass 12, count 2 2006.286.02:23:15.09#ibcon#about to write, iclass 12, count 2 2006.286.02:23:15.09#ibcon#wrote, iclass 12, count 2 2006.286.02:23:15.09#ibcon#about to read 3, iclass 12, count 2 2006.286.02:23:15.12#ibcon#read 3, iclass 12, count 2 2006.286.02:23:15.12#ibcon#about to read 4, iclass 12, count 2 2006.286.02:23:15.12#ibcon#read 4, iclass 12, count 2 2006.286.02:23:15.12#ibcon#about to read 5, iclass 12, count 2 2006.286.02:23:15.12#ibcon#read 5, iclass 12, count 2 2006.286.02:23:15.12#ibcon#about to read 6, iclass 12, count 2 2006.286.02:23:15.12#ibcon#read 6, iclass 12, count 2 2006.286.02:23:15.12#ibcon#end of sib2, iclass 12, count 2 2006.286.02:23:15.12#ibcon#*after write, iclass 12, count 2 2006.286.02:23:15.12#ibcon#*before return 0, iclass 12, count 2 2006.286.02:23:15.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:23:15.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:23:15.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.02:23:15.12#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:15.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:23:15.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:23:15.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:23:15.24#ibcon#enter wrdev, iclass 12, count 0 2006.286.02:23:15.24#ibcon#first serial, iclass 12, count 0 2006.286.02:23:15.24#ibcon#enter sib2, iclass 12, count 0 2006.286.02:23:15.24#ibcon#flushed, iclass 12, count 0 2006.286.02:23:15.24#ibcon#about to write, iclass 12, count 0 2006.286.02:23:15.24#ibcon#wrote, iclass 12, count 0 2006.286.02:23:15.24#ibcon#about to read 3, iclass 12, count 0 2006.286.02:23:15.26#ibcon#read 3, iclass 12, count 0 2006.286.02:23:15.26#ibcon#about to read 4, iclass 12, count 0 2006.286.02:23:15.26#ibcon#read 4, iclass 12, count 0 2006.286.02:23:15.26#ibcon#about to read 5, iclass 12, count 0 2006.286.02:23:15.26#ibcon#read 5, iclass 12, count 0 2006.286.02:23:15.26#ibcon#about to read 6, iclass 12, count 0 2006.286.02:23:15.26#ibcon#read 6, iclass 12, count 0 2006.286.02:23:15.26#ibcon#end of sib2, iclass 12, count 0 2006.286.02:23:15.26#ibcon#*mode == 0, iclass 12, count 0 2006.286.02:23:15.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.02:23:15.26#ibcon#[27=USB\r\n] 2006.286.02:23:15.26#ibcon#*before write, iclass 12, count 0 2006.286.02:23:15.26#ibcon#enter sib2, iclass 12, count 0 2006.286.02:23:15.26#ibcon#flushed, iclass 12, count 0 2006.286.02:23:15.26#ibcon#about to write, iclass 12, count 0 2006.286.02:23:15.26#ibcon#wrote, iclass 12, count 0 2006.286.02:23:15.26#ibcon#about to read 3, iclass 12, count 0 2006.286.02:23:15.29#ibcon#read 3, iclass 12, count 0 2006.286.02:23:15.29#ibcon#about to read 4, iclass 12, count 0 2006.286.02:23:15.29#ibcon#read 4, iclass 12, count 0 2006.286.02:23:15.29#ibcon#about to read 5, iclass 12, count 0 2006.286.02:23:15.29#ibcon#read 5, iclass 12, count 0 2006.286.02:23:15.29#ibcon#about to read 6, iclass 12, count 0 2006.286.02:23:15.29#ibcon#read 6, iclass 12, count 0 2006.286.02:23:15.29#ibcon#end of sib2, iclass 12, count 0 2006.286.02:23:15.29#ibcon#*after write, iclass 12, count 0 2006.286.02:23:15.29#ibcon#*before return 0, iclass 12, count 0 2006.286.02:23:15.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:23:15.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:23:15.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.02:23:15.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.02:23:15.29$vck44/vblo=4,679.99 2006.286.02:23:15.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.02:23:15.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.02:23:15.29#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:15.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:23:15.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:23:15.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:23:15.29#ibcon#enter wrdev, iclass 14, count 0 2006.286.02:23:15.29#ibcon#first serial, iclass 14, count 0 2006.286.02:23:15.29#ibcon#enter sib2, iclass 14, count 0 2006.286.02:23:15.29#ibcon#flushed, iclass 14, count 0 2006.286.02:23:15.29#ibcon#about to write, iclass 14, count 0 2006.286.02:23:15.29#ibcon#wrote, iclass 14, count 0 2006.286.02:23:15.29#ibcon#about to read 3, iclass 14, count 0 2006.286.02:23:15.31#ibcon#read 3, iclass 14, count 0 2006.286.02:23:15.31#ibcon#about to read 4, iclass 14, count 0 2006.286.02:23:15.31#ibcon#read 4, iclass 14, count 0 2006.286.02:23:15.31#ibcon#about to read 5, iclass 14, count 0 2006.286.02:23:15.31#ibcon#read 5, iclass 14, count 0 2006.286.02:23:15.31#ibcon#about to read 6, iclass 14, count 0 2006.286.02:23:15.31#ibcon#read 6, iclass 14, count 0 2006.286.02:23:15.31#ibcon#end of sib2, iclass 14, count 0 2006.286.02:23:15.31#ibcon#*mode == 0, iclass 14, count 0 2006.286.02:23:15.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.02:23:15.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.02:23:15.31#ibcon#*before write, iclass 14, count 0 2006.286.02:23:15.31#ibcon#enter sib2, iclass 14, count 0 2006.286.02:23:15.31#ibcon#flushed, iclass 14, count 0 2006.286.02:23:15.31#ibcon#about to write, iclass 14, count 0 2006.286.02:23:15.31#ibcon#wrote, iclass 14, count 0 2006.286.02:23:15.31#ibcon#about to read 3, iclass 14, count 0 2006.286.02:23:15.35#ibcon#read 3, iclass 14, count 0 2006.286.02:23:15.35#ibcon#about to read 4, iclass 14, count 0 2006.286.02:23:15.35#ibcon#read 4, iclass 14, count 0 2006.286.02:23:15.35#ibcon#about to read 5, iclass 14, count 0 2006.286.02:23:15.35#ibcon#read 5, iclass 14, count 0 2006.286.02:23:15.35#ibcon#about to read 6, iclass 14, count 0 2006.286.02:23:15.35#ibcon#read 6, iclass 14, count 0 2006.286.02:23:15.35#ibcon#end of sib2, iclass 14, count 0 2006.286.02:23:15.35#ibcon#*after write, iclass 14, count 0 2006.286.02:23:15.35#ibcon#*before return 0, iclass 14, count 0 2006.286.02:23:15.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:23:15.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:23:15.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.02:23:15.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.02:23:15.35$vck44/vb=4,5 2006.286.02:23:15.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.02:23:15.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.02:23:15.35#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:15.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:23:15.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:23:15.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:23:15.41#ibcon#enter wrdev, iclass 16, count 2 2006.286.02:23:15.41#ibcon#first serial, iclass 16, count 2 2006.286.02:23:15.41#ibcon#enter sib2, iclass 16, count 2 2006.286.02:23:15.41#ibcon#flushed, iclass 16, count 2 2006.286.02:23:15.41#ibcon#about to write, iclass 16, count 2 2006.286.02:23:15.41#ibcon#wrote, iclass 16, count 2 2006.286.02:23:15.41#ibcon#about to read 3, iclass 16, count 2 2006.286.02:23:15.43#ibcon#read 3, iclass 16, count 2 2006.286.02:23:15.43#ibcon#about to read 4, iclass 16, count 2 2006.286.02:23:15.43#ibcon#read 4, iclass 16, count 2 2006.286.02:23:15.43#ibcon#about to read 5, iclass 16, count 2 2006.286.02:23:15.43#ibcon#read 5, iclass 16, count 2 2006.286.02:23:15.43#ibcon#about to read 6, iclass 16, count 2 2006.286.02:23:15.43#ibcon#read 6, iclass 16, count 2 2006.286.02:23:15.43#ibcon#end of sib2, iclass 16, count 2 2006.286.02:23:15.43#ibcon#*mode == 0, iclass 16, count 2 2006.286.02:23:15.43#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.02:23:15.43#ibcon#[27=AT04-05\r\n] 2006.286.02:23:15.43#ibcon#*before write, iclass 16, count 2 2006.286.02:23:15.43#ibcon#enter sib2, iclass 16, count 2 2006.286.02:23:15.43#ibcon#flushed, iclass 16, count 2 2006.286.02:23:15.43#ibcon#about to write, iclass 16, count 2 2006.286.02:23:15.43#ibcon#wrote, iclass 16, count 2 2006.286.02:23:15.43#ibcon#about to read 3, iclass 16, count 2 2006.286.02:23:15.46#ibcon#read 3, iclass 16, count 2 2006.286.02:23:15.46#ibcon#about to read 4, iclass 16, count 2 2006.286.02:23:15.46#ibcon#read 4, iclass 16, count 2 2006.286.02:23:15.46#ibcon#about to read 5, iclass 16, count 2 2006.286.02:23:15.46#ibcon#read 5, iclass 16, count 2 2006.286.02:23:15.46#ibcon#about to read 6, iclass 16, count 2 2006.286.02:23:15.46#ibcon#read 6, iclass 16, count 2 2006.286.02:23:15.46#ibcon#end of sib2, iclass 16, count 2 2006.286.02:23:15.46#ibcon#*after write, iclass 16, count 2 2006.286.02:23:15.46#ibcon#*before return 0, iclass 16, count 2 2006.286.02:23:15.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:23:15.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:23:15.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.02:23:15.46#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:15.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:23:15.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:23:15.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:23:15.58#ibcon#enter wrdev, iclass 16, count 0 2006.286.02:23:15.58#ibcon#first serial, iclass 16, count 0 2006.286.02:23:15.58#ibcon#enter sib2, iclass 16, count 0 2006.286.02:23:15.58#ibcon#flushed, iclass 16, count 0 2006.286.02:23:15.58#ibcon#about to write, iclass 16, count 0 2006.286.02:23:15.58#ibcon#wrote, iclass 16, count 0 2006.286.02:23:15.58#ibcon#about to read 3, iclass 16, count 0 2006.286.02:23:15.60#ibcon#read 3, iclass 16, count 0 2006.286.02:23:15.60#ibcon#about to read 4, iclass 16, count 0 2006.286.02:23:15.60#ibcon#read 4, iclass 16, count 0 2006.286.02:23:15.60#ibcon#about to read 5, iclass 16, count 0 2006.286.02:23:15.60#ibcon#read 5, iclass 16, count 0 2006.286.02:23:15.60#ibcon#about to read 6, iclass 16, count 0 2006.286.02:23:15.60#ibcon#read 6, iclass 16, count 0 2006.286.02:23:15.60#ibcon#end of sib2, iclass 16, count 0 2006.286.02:23:15.60#ibcon#*mode == 0, iclass 16, count 0 2006.286.02:23:15.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.02:23:15.60#ibcon#[27=USB\r\n] 2006.286.02:23:15.60#ibcon#*before write, iclass 16, count 0 2006.286.02:23:15.60#ibcon#enter sib2, iclass 16, count 0 2006.286.02:23:15.60#ibcon#flushed, iclass 16, count 0 2006.286.02:23:15.60#ibcon#about to write, iclass 16, count 0 2006.286.02:23:15.60#ibcon#wrote, iclass 16, count 0 2006.286.02:23:15.60#ibcon#about to read 3, iclass 16, count 0 2006.286.02:23:15.63#ibcon#read 3, iclass 16, count 0 2006.286.02:23:15.63#ibcon#about to read 4, iclass 16, count 0 2006.286.02:23:15.63#ibcon#read 4, iclass 16, count 0 2006.286.02:23:15.63#ibcon#about to read 5, iclass 16, count 0 2006.286.02:23:15.63#ibcon#read 5, iclass 16, count 0 2006.286.02:23:15.63#ibcon#about to read 6, iclass 16, count 0 2006.286.02:23:15.63#ibcon#read 6, iclass 16, count 0 2006.286.02:23:15.63#ibcon#end of sib2, iclass 16, count 0 2006.286.02:23:15.63#ibcon#*after write, iclass 16, count 0 2006.286.02:23:15.63#ibcon#*before return 0, iclass 16, count 0 2006.286.02:23:15.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:23:15.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:23:15.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.02:23:15.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.02:23:15.63$vck44/vblo=5,709.99 2006.286.02:23:15.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.02:23:15.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.02:23:15.63#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:15.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:23:15.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:23:15.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:23:15.63#ibcon#enter wrdev, iclass 18, count 0 2006.286.02:23:15.63#ibcon#first serial, iclass 18, count 0 2006.286.02:23:15.63#ibcon#enter sib2, iclass 18, count 0 2006.286.02:23:15.63#ibcon#flushed, iclass 18, count 0 2006.286.02:23:15.63#ibcon#about to write, iclass 18, count 0 2006.286.02:23:15.63#ibcon#wrote, iclass 18, count 0 2006.286.02:23:15.63#ibcon#about to read 3, iclass 18, count 0 2006.286.02:23:15.65#ibcon#read 3, iclass 18, count 0 2006.286.02:23:15.65#ibcon#about to read 4, iclass 18, count 0 2006.286.02:23:15.65#ibcon#read 4, iclass 18, count 0 2006.286.02:23:15.65#ibcon#about to read 5, iclass 18, count 0 2006.286.02:23:15.65#ibcon#read 5, iclass 18, count 0 2006.286.02:23:15.65#ibcon#about to read 6, iclass 18, count 0 2006.286.02:23:15.65#ibcon#read 6, iclass 18, count 0 2006.286.02:23:15.65#ibcon#end of sib2, iclass 18, count 0 2006.286.02:23:15.65#ibcon#*mode == 0, iclass 18, count 0 2006.286.02:23:15.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.02:23:15.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.02:23:15.65#ibcon#*before write, iclass 18, count 0 2006.286.02:23:15.65#ibcon#enter sib2, iclass 18, count 0 2006.286.02:23:15.65#ibcon#flushed, iclass 18, count 0 2006.286.02:23:15.65#ibcon#about to write, iclass 18, count 0 2006.286.02:23:15.65#ibcon#wrote, iclass 18, count 0 2006.286.02:23:15.65#ibcon#about to read 3, iclass 18, count 0 2006.286.02:23:15.69#ibcon#read 3, iclass 18, count 0 2006.286.02:23:15.69#ibcon#about to read 4, iclass 18, count 0 2006.286.02:23:15.69#ibcon#read 4, iclass 18, count 0 2006.286.02:23:15.69#ibcon#about to read 5, iclass 18, count 0 2006.286.02:23:15.69#ibcon#read 5, iclass 18, count 0 2006.286.02:23:15.69#ibcon#about to read 6, iclass 18, count 0 2006.286.02:23:15.69#ibcon#read 6, iclass 18, count 0 2006.286.02:23:15.69#ibcon#end of sib2, iclass 18, count 0 2006.286.02:23:15.69#ibcon#*after write, iclass 18, count 0 2006.286.02:23:15.69#ibcon#*before return 0, iclass 18, count 0 2006.286.02:23:15.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:23:15.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:23:15.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.02:23:15.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.02:23:15.69$vck44/vb=5,4 2006.286.02:23:15.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.02:23:15.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.02:23:15.69#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:15.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:23:15.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:23:15.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:23:15.75#ibcon#enter wrdev, iclass 20, count 2 2006.286.02:23:15.75#ibcon#first serial, iclass 20, count 2 2006.286.02:23:15.75#ibcon#enter sib2, iclass 20, count 2 2006.286.02:23:15.75#ibcon#flushed, iclass 20, count 2 2006.286.02:23:15.75#ibcon#about to write, iclass 20, count 2 2006.286.02:23:15.75#ibcon#wrote, iclass 20, count 2 2006.286.02:23:15.75#ibcon#about to read 3, iclass 20, count 2 2006.286.02:23:15.77#ibcon#read 3, iclass 20, count 2 2006.286.02:23:15.77#ibcon#about to read 4, iclass 20, count 2 2006.286.02:23:15.77#ibcon#read 4, iclass 20, count 2 2006.286.02:23:15.77#ibcon#about to read 5, iclass 20, count 2 2006.286.02:23:15.77#ibcon#read 5, iclass 20, count 2 2006.286.02:23:15.77#ibcon#about to read 6, iclass 20, count 2 2006.286.02:23:15.77#ibcon#read 6, iclass 20, count 2 2006.286.02:23:15.77#ibcon#end of sib2, iclass 20, count 2 2006.286.02:23:15.77#ibcon#*mode == 0, iclass 20, count 2 2006.286.02:23:15.77#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.02:23:15.77#ibcon#[27=AT05-04\r\n] 2006.286.02:23:15.77#ibcon#*before write, iclass 20, count 2 2006.286.02:23:15.77#ibcon#enter sib2, iclass 20, count 2 2006.286.02:23:15.77#ibcon#flushed, iclass 20, count 2 2006.286.02:23:15.77#ibcon#about to write, iclass 20, count 2 2006.286.02:23:15.77#ibcon#wrote, iclass 20, count 2 2006.286.02:23:15.77#ibcon#about to read 3, iclass 20, count 2 2006.286.02:23:15.80#ibcon#read 3, iclass 20, count 2 2006.286.02:23:15.80#ibcon#about to read 4, iclass 20, count 2 2006.286.02:23:15.80#ibcon#read 4, iclass 20, count 2 2006.286.02:23:15.80#ibcon#about to read 5, iclass 20, count 2 2006.286.02:23:15.80#ibcon#read 5, iclass 20, count 2 2006.286.02:23:15.80#ibcon#about to read 6, iclass 20, count 2 2006.286.02:23:15.80#ibcon#read 6, iclass 20, count 2 2006.286.02:23:15.80#ibcon#end of sib2, iclass 20, count 2 2006.286.02:23:15.80#ibcon#*after write, iclass 20, count 2 2006.286.02:23:15.80#ibcon#*before return 0, iclass 20, count 2 2006.286.02:23:15.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:23:15.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:23:15.80#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.02:23:15.80#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:15.80#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:23:15.92#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:23:15.92#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:23:15.92#ibcon#enter wrdev, iclass 20, count 0 2006.286.02:23:15.92#ibcon#first serial, iclass 20, count 0 2006.286.02:23:15.92#ibcon#enter sib2, iclass 20, count 0 2006.286.02:23:15.92#ibcon#flushed, iclass 20, count 0 2006.286.02:23:15.92#ibcon#about to write, iclass 20, count 0 2006.286.02:23:15.92#ibcon#wrote, iclass 20, count 0 2006.286.02:23:15.92#ibcon#about to read 3, iclass 20, count 0 2006.286.02:23:15.94#ibcon#read 3, iclass 20, count 0 2006.286.02:23:15.94#ibcon#about to read 4, iclass 20, count 0 2006.286.02:23:15.94#ibcon#read 4, iclass 20, count 0 2006.286.02:23:15.94#ibcon#about to read 5, iclass 20, count 0 2006.286.02:23:15.94#ibcon#read 5, iclass 20, count 0 2006.286.02:23:15.94#ibcon#about to read 6, iclass 20, count 0 2006.286.02:23:15.94#ibcon#read 6, iclass 20, count 0 2006.286.02:23:15.94#ibcon#end of sib2, iclass 20, count 0 2006.286.02:23:15.94#ibcon#*mode == 0, iclass 20, count 0 2006.286.02:23:15.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.02:23:15.94#ibcon#[27=USB\r\n] 2006.286.02:23:15.94#ibcon#*before write, iclass 20, count 0 2006.286.02:23:15.94#ibcon#enter sib2, iclass 20, count 0 2006.286.02:23:15.94#ibcon#flushed, iclass 20, count 0 2006.286.02:23:15.94#ibcon#about to write, iclass 20, count 0 2006.286.02:23:15.94#ibcon#wrote, iclass 20, count 0 2006.286.02:23:15.94#ibcon#about to read 3, iclass 20, count 0 2006.286.02:23:15.97#ibcon#read 3, iclass 20, count 0 2006.286.02:23:15.97#ibcon#about to read 4, iclass 20, count 0 2006.286.02:23:15.97#ibcon#read 4, iclass 20, count 0 2006.286.02:23:15.97#ibcon#about to read 5, iclass 20, count 0 2006.286.02:23:15.97#ibcon#read 5, iclass 20, count 0 2006.286.02:23:15.97#ibcon#about to read 6, iclass 20, count 0 2006.286.02:23:15.97#ibcon#read 6, iclass 20, count 0 2006.286.02:23:15.97#ibcon#end of sib2, iclass 20, count 0 2006.286.02:23:15.97#ibcon#*after write, iclass 20, count 0 2006.286.02:23:15.97#ibcon#*before return 0, iclass 20, count 0 2006.286.02:23:15.97#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:23:15.97#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:23:15.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.02:23:15.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.02:23:15.97$vck44/vblo=6,719.99 2006.286.02:23:15.97#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.02:23:15.97#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.02:23:15.97#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:15.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:23:15.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:23:15.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:23:15.97#ibcon#enter wrdev, iclass 22, count 0 2006.286.02:23:15.97#ibcon#first serial, iclass 22, count 0 2006.286.02:23:15.97#ibcon#enter sib2, iclass 22, count 0 2006.286.02:23:15.97#ibcon#flushed, iclass 22, count 0 2006.286.02:23:15.97#ibcon#about to write, iclass 22, count 0 2006.286.02:23:15.97#ibcon#wrote, iclass 22, count 0 2006.286.02:23:15.97#ibcon#about to read 3, iclass 22, count 0 2006.286.02:23:15.99#ibcon#read 3, iclass 22, count 0 2006.286.02:23:15.99#ibcon#about to read 4, iclass 22, count 0 2006.286.02:23:15.99#ibcon#read 4, iclass 22, count 0 2006.286.02:23:15.99#ibcon#about to read 5, iclass 22, count 0 2006.286.02:23:15.99#ibcon#read 5, iclass 22, count 0 2006.286.02:23:15.99#ibcon#about to read 6, iclass 22, count 0 2006.286.02:23:15.99#ibcon#read 6, iclass 22, count 0 2006.286.02:23:15.99#ibcon#end of sib2, iclass 22, count 0 2006.286.02:23:15.99#ibcon#*mode == 0, iclass 22, count 0 2006.286.02:23:15.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.02:23:15.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.02:23:15.99#ibcon#*before write, iclass 22, count 0 2006.286.02:23:15.99#ibcon#enter sib2, iclass 22, count 0 2006.286.02:23:15.99#ibcon#flushed, iclass 22, count 0 2006.286.02:23:15.99#ibcon#about to write, iclass 22, count 0 2006.286.02:23:15.99#ibcon#wrote, iclass 22, count 0 2006.286.02:23:15.99#ibcon#about to read 3, iclass 22, count 0 2006.286.02:23:16.03#ibcon#read 3, iclass 22, count 0 2006.286.02:23:16.03#ibcon#about to read 4, iclass 22, count 0 2006.286.02:23:16.03#ibcon#read 4, iclass 22, count 0 2006.286.02:23:16.03#ibcon#about to read 5, iclass 22, count 0 2006.286.02:23:16.03#ibcon#read 5, iclass 22, count 0 2006.286.02:23:16.03#ibcon#about to read 6, iclass 22, count 0 2006.286.02:23:16.03#ibcon#read 6, iclass 22, count 0 2006.286.02:23:16.03#ibcon#end of sib2, iclass 22, count 0 2006.286.02:23:16.03#ibcon#*after write, iclass 22, count 0 2006.286.02:23:16.03#ibcon#*before return 0, iclass 22, count 0 2006.286.02:23:16.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:23:16.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:23:16.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.02:23:16.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.02:23:16.03$vck44/vb=6,3 2006.286.02:23:16.03#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.02:23:16.03#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.02:23:16.03#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:16.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:23:16.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:23:16.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:23:16.09#ibcon#enter wrdev, iclass 24, count 2 2006.286.02:23:16.09#ibcon#first serial, iclass 24, count 2 2006.286.02:23:16.09#ibcon#enter sib2, iclass 24, count 2 2006.286.02:23:16.09#ibcon#flushed, iclass 24, count 2 2006.286.02:23:16.09#ibcon#about to write, iclass 24, count 2 2006.286.02:23:16.09#ibcon#wrote, iclass 24, count 2 2006.286.02:23:16.09#ibcon#about to read 3, iclass 24, count 2 2006.286.02:23:16.11#ibcon#read 3, iclass 24, count 2 2006.286.02:23:16.11#ibcon#about to read 4, iclass 24, count 2 2006.286.02:23:16.11#ibcon#read 4, iclass 24, count 2 2006.286.02:23:16.11#ibcon#about to read 5, iclass 24, count 2 2006.286.02:23:16.11#ibcon#read 5, iclass 24, count 2 2006.286.02:23:16.11#ibcon#about to read 6, iclass 24, count 2 2006.286.02:23:16.11#ibcon#read 6, iclass 24, count 2 2006.286.02:23:16.11#ibcon#end of sib2, iclass 24, count 2 2006.286.02:23:16.11#ibcon#*mode == 0, iclass 24, count 2 2006.286.02:23:16.11#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.02:23:16.11#ibcon#[27=AT06-03\r\n] 2006.286.02:23:16.11#ibcon#*before write, iclass 24, count 2 2006.286.02:23:16.11#ibcon#enter sib2, iclass 24, count 2 2006.286.02:23:16.11#ibcon#flushed, iclass 24, count 2 2006.286.02:23:16.11#ibcon#about to write, iclass 24, count 2 2006.286.02:23:16.11#ibcon#wrote, iclass 24, count 2 2006.286.02:23:16.11#ibcon#about to read 3, iclass 24, count 2 2006.286.02:23:16.14#ibcon#read 3, iclass 24, count 2 2006.286.02:23:16.14#ibcon#about to read 4, iclass 24, count 2 2006.286.02:23:16.14#ibcon#read 4, iclass 24, count 2 2006.286.02:23:16.14#ibcon#about to read 5, iclass 24, count 2 2006.286.02:23:16.14#ibcon#read 5, iclass 24, count 2 2006.286.02:23:16.14#ibcon#about to read 6, iclass 24, count 2 2006.286.02:23:16.14#ibcon#read 6, iclass 24, count 2 2006.286.02:23:16.14#ibcon#end of sib2, iclass 24, count 2 2006.286.02:23:16.14#ibcon#*after write, iclass 24, count 2 2006.286.02:23:16.14#ibcon#*before return 0, iclass 24, count 2 2006.286.02:23:16.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:23:16.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:23:16.14#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.02:23:16.14#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:16.14#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:23:16.26#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:23:16.26#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:23:16.26#ibcon#enter wrdev, iclass 24, count 0 2006.286.02:23:16.26#ibcon#first serial, iclass 24, count 0 2006.286.02:23:16.26#ibcon#enter sib2, iclass 24, count 0 2006.286.02:23:16.26#ibcon#flushed, iclass 24, count 0 2006.286.02:23:16.26#ibcon#about to write, iclass 24, count 0 2006.286.02:23:16.26#ibcon#wrote, iclass 24, count 0 2006.286.02:23:16.26#ibcon#about to read 3, iclass 24, count 0 2006.286.02:23:16.28#ibcon#read 3, iclass 24, count 0 2006.286.02:23:16.28#ibcon#about to read 4, iclass 24, count 0 2006.286.02:23:16.28#ibcon#read 4, iclass 24, count 0 2006.286.02:23:16.28#ibcon#about to read 5, iclass 24, count 0 2006.286.02:23:16.28#ibcon#read 5, iclass 24, count 0 2006.286.02:23:16.28#ibcon#about to read 6, iclass 24, count 0 2006.286.02:23:16.28#ibcon#read 6, iclass 24, count 0 2006.286.02:23:16.28#ibcon#end of sib2, iclass 24, count 0 2006.286.02:23:16.28#ibcon#*mode == 0, iclass 24, count 0 2006.286.02:23:16.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.02:23:16.28#ibcon#[27=USB\r\n] 2006.286.02:23:16.28#ibcon#*before write, iclass 24, count 0 2006.286.02:23:16.28#ibcon#enter sib2, iclass 24, count 0 2006.286.02:23:16.28#ibcon#flushed, iclass 24, count 0 2006.286.02:23:16.28#ibcon#about to write, iclass 24, count 0 2006.286.02:23:16.28#ibcon#wrote, iclass 24, count 0 2006.286.02:23:16.28#ibcon#about to read 3, iclass 24, count 0 2006.286.02:23:16.31#ibcon#read 3, iclass 24, count 0 2006.286.02:23:16.31#ibcon#about to read 4, iclass 24, count 0 2006.286.02:23:16.31#ibcon#read 4, iclass 24, count 0 2006.286.02:23:16.31#ibcon#about to read 5, iclass 24, count 0 2006.286.02:23:16.31#ibcon#read 5, iclass 24, count 0 2006.286.02:23:16.31#ibcon#about to read 6, iclass 24, count 0 2006.286.02:23:16.31#ibcon#read 6, iclass 24, count 0 2006.286.02:23:16.31#ibcon#end of sib2, iclass 24, count 0 2006.286.02:23:16.31#ibcon#*after write, iclass 24, count 0 2006.286.02:23:16.31#ibcon#*before return 0, iclass 24, count 0 2006.286.02:23:16.31#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:23:16.31#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:23:16.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.02:23:16.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.02:23:16.31$vck44/vblo=7,734.99 2006.286.02:23:16.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.02:23:16.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.02:23:16.31#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:16.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:23:16.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:23:16.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:23:16.31#ibcon#enter wrdev, iclass 26, count 0 2006.286.02:23:16.31#ibcon#first serial, iclass 26, count 0 2006.286.02:23:16.31#ibcon#enter sib2, iclass 26, count 0 2006.286.02:23:16.31#ibcon#flushed, iclass 26, count 0 2006.286.02:23:16.31#ibcon#about to write, iclass 26, count 0 2006.286.02:23:16.31#ibcon#wrote, iclass 26, count 0 2006.286.02:23:16.31#ibcon#about to read 3, iclass 26, count 0 2006.286.02:23:16.33#ibcon#read 3, iclass 26, count 0 2006.286.02:23:16.33#ibcon#about to read 4, iclass 26, count 0 2006.286.02:23:16.33#ibcon#read 4, iclass 26, count 0 2006.286.02:23:16.33#ibcon#about to read 5, iclass 26, count 0 2006.286.02:23:16.33#ibcon#read 5, iclass 26, count 0 2006.286.02:23:16.33#ibcon#about to read 6, iclass 26, count 0 2006.286.02:23:16.33#ibcon#read 6, iclass 26, count 0 2006.286.02:23:16.33#ibcon#end of sib2, iclass 26, count 0 2006.286.02:23:16.33#ibcon#*mode == 0, iclass 26, count 0 2006.286.02:23:16.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.02:23:16.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.02:23:16.33#ibcon#*before write, iclass 26, count 0 2006.286.02:23:16.33#ibcon#enter sib2, iclass 26, count 0 2006.286.02:23:16.33#ibcon#flushed, iclass 26, count 0 2006.286.02:23:16.33#ibcon#about to write, iclass 26, count 0 2006.286.02:23:16.33#ibcon#wrote, iclass 26, count 0 2006.286.02:23:16.33#ibcon#about to read 3, iclass 26, count 0 2006.286.02:23:16.37#ibcon#read 3, iclass 26, count 0 2006.286.02:23:16.37#ibcon#about to read 4, iclass 26, count 0 2006.286.02:23:16.37#ibcon#read 4, iclass 26, count 0 2006.286.02:23:16.37#ibcon#about to read 5, iclass 26, count 0 2006.286.02:23:16.37#ibcon#read 5, iclass 26, count 0 2006.286.02:23:16.37#ibcon#about to read 6, iclass 26, count 0 2006.286.02:23:16.37#ibcon#read 6, iclass 26, count 0 2006.286.02:23:16.37#ibcon#end of sib2, iclass 26, count 0 2006.286.02:23:16.37#ibcon#*after write, iclass 26, count 0 2006.286.02:23:16.37#ibcon#*before return 0, iclass 26, count 0 2006.286.02:23:16.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:23:16.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:23:16.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.02:23:16.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.02:23:16.37$vck44/vb=7,4 2006.286.02:23:16.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.02:23:16.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.02:23:16.37#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:16.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:23:16.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:23:16.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:23:16.43#ibcon#enter wrdev, iclass 28, count 2 2006.286.02:23:16.43#ibcon#first serial, iclass 28, count 2 2006.286.02:23:16.43#ibcon#enter sib2, iclass 28, count 2 2006.286.02:23:16.43#ibcon#flushed, iclass 28, count 2 2006.286.02:23:16.43#ibcon#about to write, iclass 28, count 2 2006.286.02:23:16.43#ibcon#wrote, iclass 28, count 2 2006.286.02:23:16.43#ibcon#about to read 3, iclass 28, count 2 2006.286.02:23:16.45#ibcon#read 3, iclass 28, count 2 2006.286.02:23:16.45#ibcon#about to read 4, iclass 28, count 2 2006.286.02:23:16.45#ibcon#read 4, iclass 28, count 2 2006.286.02:23:16.45#ibcon#about to read 5, iclass 28, count 2 2006.286.02:23:16.45#ibcon#read 5, iclass 28, count 2 2006.286.02:23:16.45#ibcon#about to read 6, iclass 28, count 2 2006.286.02:23:16.45#ibcon#read 6, iclass 28, count 2 2006.286.02:23:16.45#ibcon#end of sib2, iclass 28, count 2 2006.286.02:23:16.45#ibcon#*mode == 0, iclass 28, count 2 2006.286.02:23:16.45#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.02:23:16.45#ibcon#[27=AT07-04\r\n] 2006.286.02:23:16.45#ibcon#*before write, iclass 28, count 2 2006.286.02:23:16.45#ibcon#enter sib2, iclass 28, count 2 2006.286.02:23:16.45#ibcon#flushed, iclass 28, count 2 2006.286.02:23:16.45#ibcon#about to write, iclass 28, count 2 2006.286.02:23:16.45#ibcon#wrote, iclass 28, count 2 2006.286.02:23:16.45#ibcon#about to read 3, iclass 28, count 2 2006.286.02:23:16.48#ibcon#read 3, iclass 28, count 2 2006.286.02:23:16.48#ibcon#about to read 4, iclass 28, count 2 2006.286.02:23:16.48#ibcon#read 4, iclass 28, count 2 2006.286.02:23:16.48#ibcon#about to read 5, iclass 28, count 2 2006.286.02:23:16.48#ibcon#read 5, iclass 28, count 2 2006.286.02:23:16.48#ibcon#about to read 6, iclass 28, count 2 2006.286.02:23:16.48#ibcon#read 6, iclass 28, count 2 2006.286.02:23:16.48#ibcon#end of sib2, iclass 28, count 2 2006.286.02:23:16.48#ibcon#*after write, iclass 28, count 2 2006.286.02:23:16.48#ibcon#*before return 0, iclass 28, count 2 2006.286.02:23:16.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:23:16.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:23:16.48#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.02:23:16.48#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:16.48#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:23:16.60#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:23:16.60#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:23:16.60#ibcon#enter wrdev, iclass 28, count 0 2006.286.02:23:16.60#ibcon#first serial, iclass 28, count 0 2006.286.02:23:16.60#ibcon#enter sib2, iclass 28, count 0 2006.286.02:23:16.60#ibcon#flushed, iclass 28, count 0 2006.286.02:23:16.60#ibcon#about to write, iclass 28, count 0 2006.286.02:23:16.60#ibcon#wrote, iclass 28, count 0 2006.286.02:23:16.60#ibcon#about to read 3, iclass 28, count 0 2006.286.02:23:16.62#ibcon#read 3, iclass 28, count 0 2006.286.02:23:16.62#ibcon#about to read 4, iclass 28, count 0 2006.286.02:23:16.62#ibcon#read 4, iclass 28, count 0 2006.286.02:23:16.62#ibcon#about to read 5, iclass 28, count 0 2006.286.02:23:16.62#ibcon#read 5, iclass 28, count 0 2006.286.02:23:16.62#ibcon#about to read 6, iclass 28, count 0 2006.286.02:23:16.62#ibcon#read 6, iclass 28, count 0 2006.286.02:23:16.62#ibcon#end of sib2, iclass 28, count 0 2006.286.02:23:16.62#ibcon#*mode == 0, iclass 28, count 0 2006.286.02:23:16.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.02:23:16.62#ibcon#[27=USB\r\n] 2006.286.02:23:16.62#ibcon#*before write, iclass 28, count 0 2006.286.02:23:16.62#ibcon#enter sib2, iclass 28, count 0 2006.286.02:23:16.62#ibcon#flushed, iclass 28, count 0 2006.286.02:23:16.62#ibcon#about to write, iclass 28, count 0 2006.286.02:23:16.62#ibcon#wrote, iclass 28, count 0 2006.286.02:23:16.62#ibcon#about to read 3, iclass 28, count 0 2006.286.02:23:16.65#ibcon#read 3, iclass 28, count 0 2006.286.02:23:16.65#ibcon#about to read 4, iclass 28, count 0 2006.286.02:23:16.65#ibcon#read 4, iclass 28, count 0 2006.286.02:23:16.65#ibcon#about to read 5, iclass 28, count 0 2006.286.02:23:16.65#ibcon#read 5, iclass 28, count 0 2006.286.02:23:16.65#ibcon#about to read 6, iclass 28, count 0 2006.286.02:23:16.65#ibcon#read 6, iclass 28, count 0 2006.286.02:23:16.65#ibcon#end of sib2, iclass 28, count 0 2006.286.02:23:16.65#ibcon#*after write, iclass 28, count 0 2006.286.02:23:16.65#ibcon#*before return 0, iclass 28, count 0 2006.286.02:23:16.65#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:23:16.65#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:23:16.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.02:23:16.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.02:23:16.65$vck44/vblo=8,744.99 2006.286.02:23:16.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.02:23:16.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.02:23:16.65#ibcon#ireg 17 cls_cnt 0 2006.286.02:23:16.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:23:16.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:23:16.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:23:16.65#ibcon#enter wrdev, iclass 30, count 0 2006.286.02:23:16.65#ibcon#first serial, iclass 30, count 0 2006.286.02:23:16.65#ibcon#enter sib2, iclass 30, count 0 2006.286.02:23:16.65#ibcon#flushed, iclass 30, count 0 2006.286.02:23:16.65#ibcon#about to write, iclass 30, count 0 2006.286.02:23:16.65#ibcon#wrote, iclass 30, count 0 2006.286.02:23:16.65#ibcon#about to read 3, iclass 30, count 0 2006.286.02:23:16.67#ibcon#read 3, iclass 30, count 0 2006.286.02:23:16.67#ibcon#about to read 4, iclass 30, count 0 2006.286.02:23:16.67#ibcon#read 4, iclass 30, count 0 2006.286.02:23:16.67#ibcon#about to read 5, iclass 30, count 0 2006.286.02:23:16.67#ibcon#read 5, iclass 30, count 0 2006.286.02:23:16.67#ibcon#about to read 6, iclass 30, count 0 2006.286.02:23:16.67#ibcon#read 6, iclass 30, count 0 2006.286.02:23:16.67#ibcon#end of sib2, iclass 30, count 0 2006.286.02:23:16.67#ibcon#*mode == 0, iclass 30, count 0 2006.286.02:23:16.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.02:23:16.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.02:23:16.67#ibcon#*before write, iclass 30, count 0 2006.286.02:23:16.67#ibcon#enter sib2, iclass 30, count 0 2006.286.02:23:16.67#ibcon#flushed, iclass 30, count 0 2006.286.02:23:16.67#ibcon#about to write, iclass 30, count 0 2006.286.02:23:16.67#ibcon#wrote, iclass 30, count 0 2006.286.02:23:16.67#ibcon#about to read 3, iclass 30, count 0 2006.286.02:23:16.71#ibcon#read 3, iclass 30, count 0 2006.286.02:23:16.71#ibcon#about to read 4, iclass 30, count 0 2006.286.02:23:16.71#ibcon#read 4, iclass 30, count 0 2006.286.02:23:16.71#ibcon#about to read 5, iclass 30, count 0 2006.286.02:23:16.71#ibcon#read 5, iclass 30, count 0 2006.286.02:23:16.71#ibcon#about to read 6, iclass 30, count 0 2006.286.02:23:16.71#ibcon#read 6, iclass 30, count 0 2006.286.02:23:16.71#ibcon#end of sib2, iclass 30, count 0 2006.286.02:23:16.71#ibcon#*after write, iclass 30, count 0 2006.286.02:23:16.71#ibcon#*before return 0, iclass 30, count 0 2006.286.02:23:16.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:23:16.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:23:16.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.02:23:16.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.02:23:16.71$vck44/vb=8,4 2006.286.02:23:16.71#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.02:23:16.71#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.02:23:16.71#ibcon#ireg 11 cls_cnt 2 2006.286.02:23:16.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:23:16.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:23:16.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:23:16.77#ibcon#enter wrdev, iclass 32, count 2 2006.286.02:23:16.77#ibcon#first serial, iclass 32, count 2 2006.286.02:23:16.77#ibcon#enter sib2, iclass 32, count 2 2006.286.02:23:16.77#ibcon#flushed, iclass 32, count 2 2006.286.02:23:16.77#ibcon#about to write, iclass 32, count 2 2006.286.02:23:16.77#ibcon#wrote, iclass 32, count 2 2006.286.02:23:16.77#ibcon#about to read 3, iclass 32, count 2 2006.286.02:23:16.79#ibcon#read 3, iclass 32, count 2 2006.286.02:23:16.79#ibcon#about to read 4, iclass 32, count 2 2006.286.02:23:16.79#ibcon#read 4, iclass 32, count 2 2006.286.02:23:16.79#ibcon#about to read 5, iclass 32, count 2 2006.286.02:23:16.79#ibcon#read 5, iclass 32, count 2 2006.286.02:23:16.79#ibcon#about to read 6, iclass 32, count 2 2006.286.02:23:16.79#ibcon#read 6, iclass 32, count 2 2006.286.02:23:16.79#ibcon#end of sib2, iclass 32, count 2 2006.286.02:23:16.79#ibcon#*mode == 0, iclass 32, count 2 2006.286.02:23:16.79#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.02:23:16.79#ibcon#[27=AT08-04\r\n] 2006.286.02:23:16.79#ibcon#*before write, iclass 32, count 2 2006.286.02:23:16.79#ibcon#enter sib2, iclass 32, count 2 2006.286.02:23:16.79#ibcon#flushed, iclass 32, count 2 2006.286.02:23:16.79#ibcon#about to write, iclass 32, count 2 2006.286.02:23:16.79#ibcon#wrote, iclass 32, count 2 2006.286.02:23:16.79#ibcon#about to read 3, iclass 32, count 2 2006.286.02:23:16.82#ibcon#read 3, iclass 32, count 2 2006.286.02:23:16.82#ibcon#about to read 4, iclass 32, count 2 2006.286.02:23:16.82#ibcon#read 4, iclass 32, count 2 2006.286.02:23:16.82#ibcon#about to read 5, iclass 32, count 2 2006.286.02:23:16.82#ibcon#read 5, iclass 32, count 2 2006.286.02:23:16.82#ibcon#about to read 6, iclass 32, count 2 2006.286.02:23:16.82#ibcon#read 6, iclass 32, count 2 2006.286.02:23:16.82#ibcon#end of sib2, iclass 32, count 2 2006.286.02:23:16.82#ibcon#*after write, iclass 32, count 2 2006.286.02:23:16.82#ibcon#*before return 0, iclass 32, count 2 2006.286.02:23:16.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:23:16.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:23:16.82#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.02:23:16.82#ibcon#ireg 7 cls_cnt 0 2006.286.02:23:16.82#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:23:16.94#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:23:16.94#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:23:16.94#ibcon#enter wrdev, iclass 32, count 0 2006.286.02:23:16.94#ibcon#first serial, iclass 32, count 0 2006.286.02:23:16.94#ibcon#enter sib2, iclass 32, count 0 2006.286.02:23:16.94#ibcon#flushed, iclass 32, count 0 2006.286.02:23:16.94#ibcon#about to write, iclass 32, count 0 2006.286.02:23:16.94#ibcon#wrote, iclass 32, count 0 2006.286.02:23:16.94#ibcon#about to read 3, iclass 32, count 0 2006.286.02:23:16.96#ibcon#read 3, iclass 32, count 0 2006.286.02:23:16.96#ibcon#about to read 4, iclass 32, count 0 2006.286.02:23:16.96#ibcon#read 4, iclass 32, count 0 2006.286.02:23:16.96#ibcon#about to read 5, iclass 32, count 0 2006.286.02:23:16.96#ibcon#read 5, iclass 32, count 0 2006.286.02:23:16.96#ibcon#about to read 6, iclass 32, count 0 2006.286.02:23:16.96#ibcon#read 6, iclass 32, count 0 2006.286.02:23:16.96#ibcon#end of sib2, iclass 32, count 0 2006.286.02:23:16.96#ibcon#*mode == 0, iclass 32, count 0 2006.286.02:23:16.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.02:23:16.96#ibcon#[27=USB\r\n] 2006.286.02:23:16.96#ibcon#*before write, iclass 32, count 0 2006.286.02:23:16.96#ibcon#enter sib2, iclass 32, count 0 2006.286.02:23:16.96#ibcon#flushed, iclass 32, count 0 2006.286.02:23:16.96#ibcon#about to write, iclass 32, count 0 2006.286.02:23:16.96#ibcon#wrote, iclass 32, count 0 2006.286.02:23:16.96#ibcon#about to read 3, iclass 32, count 0 2006.286.02:23:16.99#ibcon#read 3, iclass 32, count 0 2006.286.02:23:16.99#ibcon#about to read 4, iclass 32, count 0 2006.286.02:23:16.99#ibcon#read 4, iclass 32, count 0 2006.286.02:23:16.99#ibcon#about to read 5, iclass 32, count 0 2006.286.02:23:16.99#ibcon#read 5, iclass 32, count 0 2006.286.02:23:16.99#ibcon#about to read 6, iclass 32, count 0 2006.286.02:23:16.99#ibcon#read 6, iclass 32, count 0 2006.286.02:23:16.99#ibcon#end of sib2, iclass 32, count 0 2006.286.02:23:16.99#ibcon#*after write, iclass 32, count 0 2006.286.02:23:16.99#ibcon#*before return 0, iclass 32, count 0 2006.286.02:23:16.99#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:23:16.99#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:23:16.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.02:23:16.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.02:23:16.99$vck44/vabw=wide 2006.286.02:23:16.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.02:23:16.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.02:23:16.99#ibcon#ireg 8 cls_cnt 0 2006.286.02:23:16.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:23:16.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:23:16.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:23:16.99#ibcon#enter wrdev, iclass 34, count 0 2006.286.02:23:16.99#ibcon#first serial, iclass 34, count 0 2006.286.02:23:16.99#ibcon#enter sib2, iclass 34, count 0 2006.286.02:23:16.99#ibcon#flushed, iclass 34, count 0 2006.286.02:23:16.99#ibcon#about to write, iclass 34, count 0 2006.286.02:23:16.99#ibcon#wrote, iclass 34, count 0 2006.286.02:23:16.99#ibcon#about to read 3, iclass 34, count 0 2006.286.02:23:17.01#ibcon#read 3, iclass 34, count 0 2006.286.02:23:17.01#ibcon#about to read 4, iclass 34, count 0 2006.286.02:23:17.01#ibcon#read 4, iclass 34, count 0 2006.286.02:23:17.01#ibcon#about to read 5, iclass 34, count 0 2006.286.02:23:17.01#ibcon#read 5, iclass 34, count 0 2006.286.02:23:17.01#ibcon#about to read 6, iclass 34, count 0 2006.286.02:23:17.01#ibcon#read 6, iclass 34, count 0 2006.286.02:23:17.01#ibcon#end of sib2, iclass 34, count 0 2006.286.02:23:17.01#ibcon#*mode == 0, iclass 34, count 0 2006.286.02:23:17.01#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.02:23:17.01#ibcon#[25=BW32\r\n] 2006.286.02:23:17.01#ibcon#*before write, iclass 34, count 0 2006.286.02:23:17.01#ibcon#enter sib2, iclass 34, count 0 2006.286.02:23:17.01#ibcon#flushed, iclass 34, count 0 2006.286.02:23:17.01#ibcon#about to write, iclass 34, count 0 2006.286.02:23:17.01#ibcon#wrote, iclass 34, count 0 2006.286.02:23:17.01#ibcon#about to read 3, iclass 34, count 0 2006.286.02:23:17.04#ibcon#read 3, iclass 34, count 0 2006.286.02:23:17.04#ibcon#about to read 4, iclass 34, count 0 2006.286.02:23:17.04#ibcon#read 4, iclass 34, count 0 2006.286.02:23:17.04#ibcon#about to read 5, iclass 34, count 0 2006.286.02:23:17.04#ibcon#read 5, iclass 34, count 0 2006.286.02:23:17.04#ibcon#about to read 6, iclass 34, count 0 2006.286.02:23:17.04#ibcon#read 6, iclass 34, count 0 2006.286.02:23:17.04#ibcon#end of sib2, iclass 34, count 0 2006.286.02:23:17.04#ibcon#*after write, iclass 34, count 0 2006.286.02:23:17.04#ibcon#*before return 0, iclass 34, count 0 2006.286.02:23:17.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:23:17.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:23:17.04#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.02:23:17.04#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.02:23:17.04$vck44/vbbw=wide 2006.286.02:23:17.04#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.02:23:17.04#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.02:23:17.04#ibcon#ireg 8 cls_cnt 0 2006.286.02:23:17.04#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:23:17.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:23:17.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:23:17.11#ibcon#enter wrdev, iclass 36, count 0 2006.286.02:23:17.11#ibcon#first serial, iclass 36, count 0 2006.286.02:23:17.11#ibcon#enter sib2, iclass 36, count 0 2006.286.02:23:17.11#ibcon#flushed, iclass 36, count 0 2006.286.02:23:17.11#ibcon#about to write, iclass 36, count 0 2006.286.02:23:17.11#ibcon#wrote, iclass 36, count 0 2006.286.02:23:17.11#ibcon#about to read 3, iclass 36, count 0 2006.286.02:23:17.13#ibcon#read 3, iclass 36, count 0 2006.286.02:23:17.13#ibcon#about to read 4, iclass 36, count 0 2006.286.02:23:17.13#ibcon#read 4, iclass 36, count 0 2006.286.02:23:17.13#ibcon#about to read 5, iclass 36, count 0 2006.286.02:23:17.13#ibcon#read 5, iclass 36, count 0 2006.286.02:23:17.13#ibcon#about to read 6, iclass 36, count 0 2006.286.02:23:17.13#ibcon#read 6, iclass 36, count 0 2006.286.02:23:17.13#ibcon#end of sib2, iclass 36, count 0 2006.286.02:23:17.13#ibcon#*mode == 0, iclass 36, count 0 2006.286.02:23:17.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.02:23:17.13#ibcon#[27=BW32\r\n] 2006.286.02:23:17.13#ibcon#*before write, iclass 36, count 0 2006.286.02:23:17.13#ibcon#enter sib2, iclass 36, count 0 2006.286.02:23:17.13#ibcon#flushed, iclass 36, count 0 2006.286.02:23:17.13#ibcon#about to write, iclass 36, count 0 2006.286.02:23:17.13#ibcon#wrote, iclass 36, count 0 2006.286.02:23:17.13#ibcon#about to read 3, iclass 36, count 0 2006.286.02:23:17.16#ibcon#read 3, iclass 36, count 0 2006.286.02:23:17.16#ibcon#about to read 4, iclass 36, count 0 2006.286.02:23:17.16#ibcon#read 4, iclass 36, count 0 2006.286.02:23:17.16#ibcon#about to read 5, iclass 36, count 0 2006.286.02:23:17.16#ibcon#read 5, iclass 36, count 0 2006.286.02:23:17.16#ibcon#about to read 6, iclass 36, count 0 2006.286.02:23:17.16#ibcon#read 6, iclass 36, count 0 2006.286.02:23:17.16#ibcon#end of sib2, iclass 36, count 0 2006.286.02:23:17.16#ibcon#*after write, iclass 36, count 0 2006.286.02:23:17.16#ibcon#*before return 0, iclass 36, count 0 2006.286.02:23:17.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:23:17.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:23:17.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.02:23:17.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.02:23:17.16$setupk4/ifdk4 2006.286.02:23:17.16$ifdk4/lo= 2006.286.02:23:17.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.02:23:17.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.02:23:17.16$ifdk4/patch= 2006.286.02:23:17.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.02:23:17.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.02:23:17.16$setupk4/!*+20s 2006.286.02:23:17.39#abcon#<5=/04 2.8 5.9 21.39 811015.9\r\n> 2006.286.02:23:17.41#abcon#{5=INTERFACE CLEAR} 2006.286.02:23:17.47#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:23:27.56#abcon#<5=/04 2.8 5.9 21.39 811015.9\r\n> 2006.286.02:23:27.58#abcon#{5=INTERFACE CLEAR} 2006.286.02:23:27.64#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:23:31.66$setupk4/"tpicd 2006.286.02:23:31.66$setupk4/echo=off 2006.286.02:23:31.66$setupk4/xlog=off 2006.286.02:23:31.66:!2006.286.02:27:47 2006.286.02:23:35.13#trakl#Source acquired 2006.286.02:23:36.13#flagr#flagr/antenna,acquired 2006.286.02:27:47.00:preob 2006.286.02:27:47.14/onsource/TRACKING 2006.286.02:27:47.14:!2006.286.02:27:57 2006.286.02:27:57.00:"tape 2006.286.02:27:57.00:"st=record 2006.286.02:27:57.00:data_valid=on 2006.286.02:27:57.00:midob 2006.286.02:27:57.14/onsource/TRACKING 2006.286.02:27:57.14/wx/21.39,1015.9,81 2006.286.02:27:57.35/cable/+6.4988E-03 2006.286.02:27:58.44/va/01,07,usb,yes,36,39 2006.286.02:27:58.44/va/02,06,usb,yes,36,36 2006.286.02:27:58.44/va/03,07,usb,yes,35,37 2006.286.02:27:58.44/va/04,06,usb,yes,37,39 2006.286.02:27:58.44/va/05,03,usb,yes,36,37 2006.286.02:27:58.44/va/06,04,usb,yes,33,32 2006.286.02:27:58.44/va/07,04,usb,yes,33,34 2006.286.02:27:58.44/va/08,03,usb,yes,34,41 2006.286.02:27:58.67/valo/01,524.99,yes,locked 2006.286.02:27:58.67/valo/02,534.99,yes,locked 2006.286.02:27:58.67/valo/03,564.99,yes,locked 2006.286.02:27:58.67/valo/04,624.99,yes,locked 2006.286.02:27:58.67/valo/05,734.99,yes,locked 2006.286.02:27:58.67/valo/06,814.99,yes,locked 2006.286.02:27:58.67/valo/07,864.99,yes,locked 2006.286.02:27:58.67/valo/08,884.99,yes,locked 2006.286.02:27:59.76/vb/01,04,usb,yes,32,30 2006.286.02:27:59.76/vb/02,05,usb,yes,30,30 2006.286.02:27:59.76/vb/03,04,usb,yes,31,34 2006.286.02:27:59.76/vb/04,05,usb,yes,31,30 2006.286.02:27:59.76/vb/05,04,usb,yes,28,30 2006.286.02:27:59.76/vb/06,03,usb,yes,40,35 2006.286.02:27:59.76/vb/07,04,usb,yes,32,32 2006.286.02:27:59.76/vb/08,04,usb,yes,29,33 2006.286.02:27:59.99/vblo/01,629.99,yes,locked 2006.286.02:27:59.99/vblo/02,634.99,yes,locked 2006.286.02:27:59.99/vblo/03,649.99,yes,locked 2006.286.02:27:59.99/vblo/04,679.99,yes,locked 2006.286.02:27:59.99/vblo/05,709.99,yes,locked 2006.286.02:27:59.99/vblo/06,719.99,yes,locked 2006.286.02:27:59.99/vblo/07,734.99,yes,locked 2006.286.02:27:59.99/vblo/08,744.99,yes,locked 2006.286.02:28:00.14/vabw/8 2006.286.02:28:00.29/vbbw/8 2006.286.02:28:00.38/xfe/off,on,11.7 2006.286.02:28:00.75/ifatt/23,28,28,28 2006.286.02:28:01.08/fmout-gps/S +2.78E-07 2006.286.02:28:01.10:!2006.286.02:28:37 2006.286.02:28:37.00:data_valid=off 2006.286.02:28:37.00:"et 2006.286.02:28:37.00:!+3s 2006.286.02:28:40.01:"tape 2006.286.02:28:40.01:postob 2006.286.02:28:40.19/cable/+6.4986E-03 2006.286.02:28:40.19/wx/21.39,1015.9,81 2006.286.02:28:41.08/fmout-gps/S +2.79E-07 2006.286.02:28:41.08:scan_name=286-0231,jd0610,40 2006.286.02:28:41.08:source=3c345,164258.81,394837.0,2000.0,ccw 2006.286.02:28:42.14#flagr#flagr/antenna,new-source 2006.286.02:28:42.14:checkk5 2006.286.02:28:42.62/chk_autoobs//k5ts1/ autoobs is running! 2006.286.02:28:43.05/chk_autoobs//k5ts2/ autoobs is running! 2006.286.02:28:43.65/chk_autoobs//k5ts3/ autoobs is running! 2006.286.02:28:44.04/chk_autoobs//k5ts4/ autoobs is running! 2006.286.02:28:44.42/chk_obsdata//k5ts1/T2860227??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:28:44.82/chk_obsdata//k5ts2/T2860227??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:28:45.19/chk_obsdata//k5ts3/T2860227??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:28:45.87/chk_obsdata//k5ts4/T2860227??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:28:46.66/k5log//k5ts1_log_newline 2006.286.02:28:47.39/k5log//k5ts2_log_newline 2006.286.02:28:48.41/k5log//k5ts3_log_newline 2006.286.02:28:49.45/k5log//k5ts4_log_newline 2006.286.02:28:49.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.02:28:49.47:setupk4=1 2006.286.02:28:49.47$setupk4/echo=on 2006.286.02:28:49.47$setupk4/pcalon 2006.286.02:28:49.47$pcalon/"no phase cal control is implemented here 2006.286.02:28:49.47$setupk4/"tpicd=stop 2006.286.02:28:49.47$setupk4/"rec=synch_on 2006.286.02:28:49.47$setupk4/"rec_mode=128 2006.286.02:28:49.47$setupk4/!* 2006.286.02:28:49.47$setupk4/recpk4 2006.286.02:28:49.47$recpk4/recpatch= 2006.286.02:28:49.47$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.02:28:49.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.02:28:49.47$setupk4/vck44 2006.286.02:28:49.47$vck44/valo=1,524.99 2006.286.02:28:49.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.02:28:49.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.02:28:49.47#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:49.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:28:49.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:28:49.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:28:49.47#ibcon#enter wrdev, iclass 29, count 0 2006.286.02:28:49.47#ibcon#first serial, iclass 29, count 0 2006.286.02:28:49.47#ibcon#enter sib2, iclass 29, count 0 2006.286.02:28:49.47#ibcon#flushed, iclass 29, count 0 2006.286.02:28:49.47#ibcon#about to write, iclass 29, count 0 2006.286.02:28:49.48#ibcon#wrote, iclass 29, count 0 2006.286.02:28:49.48#ibcon#about to read 3, iclass 29, count 0 2006.286.02:28:49.49#ibcon#read 3, iclass 29, count 0 2006.286.02:28:49.49#ibcon#about to read 4, iclass 29, count 0 2006.286.02:28:49.49#ibcon#read 4, iclass 29, count 0 2006.286.02:28:49.49#ibcon#about to read 5, iclass 29, count 0 2006.286.02:28:49.49#ibcon#read 5, iclass 29, count 0 2006.286.02:28:49.49#ibcon#about to read 6, iclass 29, count 0 2006.286.02:28:49.49#ibcon#read 6, iclass 29, count 0 2006.286.02:28:49.49#ibcon#end of sib2, iclass 29, count 0 2006.286.02:28:49.49#ibcon#*mode == 0, iclass 29, count 0 2006.286.02:28:49.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.02:28:49.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.02:28:49.49#ibcon#*before write, iclass 29, count 0 2006.286.02:28:49.49#ibcon#enter sib2, iclass 29, count 0 2006.286.02:28:49.49#ibcon#flushed, iclass 29, count 0 2006.286.02:28:49.49#ibcon#about to write, iclass 29, count 0 2006.286.02:28:49.49#ibcon#wrote, iclass 29, count 0 2006.286.02:28:49.49#ibcon#about to read 3, iclass 29, count 0 2006.286.02:28:49.54#ibcon#read 3, iclass 29, count 0 2006.286.02:28:49.54#ibcon#about to read 4, iclass 29, count 0 2006.286.02:28:49.54#ibcon#read 4, iclass 29, count 0 2006.286.02:28:49.54#ibcon#about to read 5, iclass 29, count 0 2006.286.02:28:49.54#ibcon#read 5, iclass 29, count 0 2006.286.02:28:49.54#ibcon#about to read 6, iclass 29, count 0 2006.286.02:28:49.54#ibcon#read 6, iclass 29, count 0 2006.286.02:28:49.54#ibcon#end of sib2, iclass 29, count 0 2006.286.02:28:49.54#ibcon#*after write, iclass 29, count 0 2006.286.02:28:49.54#ibcon#*before return 0, iclass 29, count 0 2006.286.02:28:49.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:28:49.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:28:49.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.02:28:49.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.02:28:49.54$vck44/va=1,7 2006.286.02:28:49.54#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.02:28:49.54#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.02:28:49.54#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:49.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:28:49.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:28:49.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:28:49.54#ibcon#enter wrdev, iclass 31, count 2 2006.286.02:28:49.54#ibcon#first serial, iclass 31, count 2 2006.286.02:28:49.54#ibcon#enter sib2, iclass 31, count 2 2006.286.02:28:49.54#ibcon#flushed, iclass 31, count 2 2006.286.02:28:49.54#ibcon#about to write, iclass 31, count 2 2006.286.02:28:49.54#ibcon#wrote, iclass 31, count 2 2006.286.02:28:49.54#ibcon#about to read 3, iclass 31, count 2 2006.286.02:28:49.56#ibcon#read 3, iclass 31, count 2 2006.286.02:28:49.56#ibcon#about to read 4, iclass 31, count 2 2006.286.02:28:49.56#ibcon#read 4, iclass 31, count 2 2006.286.02:28:49.56#ibcon#about to read 5, iclass 31, count 2 2006.286.02:28:49.56#ibcon#read 5, iclass 31, count 2 2006.286.02:28:49.56#ibcon#about to read 6, iclass 31, count 2 2006.286.02:28:49.56#ibcon#read 6, iclass 31, count 2 2006.286.02:28:49.56#ibcon#end of sib2, iclass 31, count 2 2006.286.02:28:49.56#ibcon#*mode == 0, iclass 31, count 2 2006.286.02:28:49.56#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.02:28:49.56#ibcon#[25=AT01-07\r\n] 2006.286.02:28:49.56#ibcon#*before write, iclass 31, count 2 2006.286.02:28:49.56#ibcon#enter sib2, iclass 31, count 2 2006.286.02:28:49.56#ibcon#flushed, iclass 31, count 2 2006.286.02:28:49.56#ibcon#about to write, iclass 31, count 2 2006.286.02:28:49.56#ibcon#wrote, iclass 31, count 2 2006.286.02:28:49.56#ibcon#about to read 3, iclass 31, count 2 2006.286.02:28:49.59#ibcon#read 3, iclass 31, count 2 2006.286.02:28:49.59#ibcon#about to read 4, iclass 31, count 2 2006.286.02:28:49.59#ibcon#read 4, iclass 31, count 2 2006.286.02:28:49.59#ibcon#about to read 5, iclass 31, count 2 2006.286.02:28:49.59#ibcon#read 5, iclass 31, count 2 2006.286.02:28:49.59#ibcon#about to read 6, iclass 31, count 2 2006.286.02:28:49.59#ibcon#read 6, iclass 31, count 2 2006.286.02:28:49.59#ibcon#end of sib2, iclass 31, count 2 2006.286.02:28:49.59#ibcon#*after write, iclass 31, count 2 2006.286.02:28:49.59#ibcon#*before return 0, iclass 31, count 2 2006.286.02:28:49.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:28:49.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:28:49.59#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.02:28:49.59#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:49.59#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:28:49.71#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:28:49.71#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:28:49.71#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:28:49.71#ibcon#first serial, iclass 31, count 0 2006.286.02:28:49.71#ibcon#enter sib2, iclass 31, count 0 2006.286.02:28:49.71#ibcon#flushed, iclass 31, count 0 2006.286.02:28:49.71#ibcon#about to write, iclass 31, count 0 2006.286.02:28:49.71#ibcon#wrote, iclass 31, count 0 2006.286.02:28:49.71#ibcon#about to read 3, iclass 31, count 0 2006.286.02:28:49.73#ibcon#read 3, iclass 31, count 0 2006.286.02:28:49.73#ibcon#about to read 4, iclass 31, count 0 2006.286.02:28:49.73#ibcon#read 4, iclass 31, count 0 2006.286.02:28:49.73#ibcon#about to read 5, iclass 31, count 0 2006.286.02:28:49.73#ibcon#read 5, iclass 31, count 0 2006.286.02:28:49.73#ibcon#about to read 6, iclass 31, count 0 2006.286.02:28:49.73#ibcon#read 6, iclass 31, count 0 2006.286.02:28:49.73#ibcon#end of sib2, iclass 31, count 0 2006.286.02:28:49.73#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:28:49.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:28:49.73#ibcon#[25=USB\r\n] 2006.286.02:28:49.73#ibcon#*before write, iclass 31, count 0 2006.286.02:28:49.73#ibcon#enter sib2, iclass 31, count 0 2006.286.02:28:49.73#ibcon#flushed, iclass 31, count 0 2006.286.02:28:49.73#ibcon#about to write, iclass 31, count 0 2006.286.02:28:49.73#ibcon#wrote, iclass 31, count 0 2006.286.02:28:49.73#ibcon#about to read 3, iclass 31, count 0 2006.286.02:28:49.76#ibcon#read 3, iclass 31, count 0 2006.286.02:28:49.76#ibcon#about to read 4, iclass 31, count 0 2006.286.02:28:49.76#ibcon#read 4, iclass 31, count 0 2006.286.02:28:49.76#ibcon#about to read 5, iclass 31, count 0 2006.286.02:28:49.76#ibcon#read 5, iclass 31, count 0 2006.286.02:28:49.76#ibcon#about to read 6, iclass 31, count 0 2006.286.02:28:49.76#ibcon#read 6, iclass 31, count 0 2006.286.02:28:49.76#ibcon#end of sib2, iclass 31, count 0 2006.286.02:28:49.76#ibcon#*after write, iclass 31, count 0 2006.286.02:28:49.76#ibcon#*before return 0, iclass 31, count 0 2006.286.02:28:49.76#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:28:49.76#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:28:49.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:28:49.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:28:49.76$vck44/valo=2,534.99 2006.286.02:28:49.76#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.02:28:49.76#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.02:28:49.76#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:49.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:28:49.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:28:49.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:28:49.76#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:28:49.76#ibcon#first serial, iclass 33, count 0 2006.286.02:28:49.76#ibcon#enter sib2, iclass 33, count 0 2006.286.02:28:49.76#ibcon#flushed, iclass 33, count 0 2006.286.02:28:49.76#ibcon#about to write, iclass 33, count 0 2006.286.02:28:49.76#ibcon#wrote, iclass 33, count 0 2006.286.02:28:49.76#ibcon#about to read 3, iclass 33, count 0 2006.286.02:28:49.78#ibcon#read 3, iclass 33, count 0 2006.286.02:28:49.78#ibcon#about to read 4, iclass 33, count 0 2006.286.02:28:49.78#ibcon#read 4, iclass 33, count 0 2006.286.02:28:49.78#ibcon#about to read 5, iclass 33, count 0 2006.286.02:28:49.78#ibcon#read 5, iclass 33, count 0 2006.286.02:28:49.78#ibcon#about to read 6, iclass 33, count 0 2006.286.02:28:49.78#ibcon#read 6, iclass 33, count 0 2006.286.02:28:49.78#ibcon#end of sib2, iclass 33, count 0 2006.286.02:28:49.78#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:28:49.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:28:49.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.02:28:49.78#ibcon#*before write, iclass 33, count 0 2006.286.02:28:49.78#ibcon#enter sib2, iclass 33, count 0 2006.286.02:28:49.78#ibcon#flushed, iclass 33, count 0 2006.286.02:28:49.78#ibcon#about to write, iclass 33, count 0 2006.286.02:28:49.78#ibcon#wrote, iclass 33, count 0 2006.286.02:28:49.78#ibcon#about to read 3, iclass 33, count 0 2006.286.02:28:49.82#ibcon#read 3, iclass 33, count 0 2006.286.02:28:49.82#ibcon#about to read 4, iclass 33, count 0 2006.286.02:28:49.82#ibcon#read 4, iclass 33, count 0 2006.286.02:28:49.82#ibcon#about to read 5, iclass 33, count 0 2006.286.02:28:49.82#ibcon#read 5, iclass 33, count 0 2006.286.02:28:49.82#ibcon#about to read 6, iclass 33, count 0 2006.286.02:28:49.82#ibcon#read 6, iclass 33, count 0 2006.286.02:28:49.82#ibcon#end of sib2, iclass 33, count 0 2006.286.02:28:49.82#ibcon#*after write, iclass 33, count 0 2006.286.02:28:49.82#ibcon#*before return 0, iclass 33, count 0 2006.286.02:28:49.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:28:49.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:28:49.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:28:49.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:28:49.82$vck44/va=2,6 2006.286.02:28:49.82#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.02:28:49.82#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.02:28:49.82#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:49.82#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:28:49.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:28:49.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:28:49.88#ibcon#enter wrdev, iclass 35, count 2 2006.286.02:28:49.88#ibcon#first serial, iclass 35, count 2 2006.286.02:28:49.88#ibcon#enter sib2, iclass 35, count 2 2006.286.02:28:49.88#ibcon#flushed, iclass 35, count 2 2006.286.02:28:49.88#ibcon#about to write, iclass 35, count 2 2006.286.02:28:49.88#ibcon#wrote, iclass 35, count 2 2006.286.02:28:49.88#ibcon#about to read 3, iclass 35, count 2 2006.286.02:28:49.90#ibcon#read 3, iclass 35, count 2 2006.286.02:28:49.90#ibcon#about to read 4, iclass 35, count 2 2006.286.02:28:49.90#ibcon#read 4, iclass 35, count 2 2006.286.02:28:49.90#ibcon#about to read 5, iclass 35, count 2 2006.286.02:28:49.90#ibcon#read 5, iclass 35, count 2 2006.286.02:28:49.90#ibcon#about to read 6, iclass 35, count 2 2006.286.02:28:49.90#ibcon#read 6, iclass 35, count 2 2006.286.02:28:49.90#ibcon#end of sib2, iclass 35, count 2 2006.286.02:28:49.90#ibcon#*mode == 0, iclass 35, count 2 2006.286.02:28:49.90#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.02:28:49.90#ibcon#[25=AT02-06\r\n] 2006.286.02:28:49.90#ibcon#*before write, iclass 35, count 2 2006.286.02:28:49.90#ibcon#enter sib2, iclass 35, count 2 2006.286.02:28:49.90#ibcon#flushed, iclass 35, count 2 2006.286.02:28:49.90#ibcon#about to write, iclass 35, count 2 2006.286.02:28:49.90#ibcon#wrote, iclass 35, count 2 2006.286.02:28:49.90#ibcon#about to read 3, iclass 35, count 2 2006.286.02:28:49.93#ibcon#read 3, iclass 35, count 2 2006.286.02:28:49.93#ibcon#about to read 4, iclass 35, count 2 2006.286.02:28:49.93#ibcon#read 4, iclass 35, count 2 2006.286.02:28:49.93#ibcon#about to read 5, iclass 35, count 2 2006.286.02:28:49.93#ibcon#read 5, iclass 35, count 2 2006.286.02:28:49.93#ibcon#about to read 6, iclass 35, count 2 2006.286.02:28:49.93#ibcon#read 6, iclass 35, count 2 2006.286.02:28:49.93#ibcon#end of sib2, iclass 35, count 2 2006.286.02:28:49.93#ibcon#*after write, iclass 35, count 2 2006.286.02:28:49.93#ibcon#*before return 0, iclass 35, count 2 2006.286.02:28:49.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:28:49.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:28:49.93#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.02:28:49.93#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:49.93#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:28:50.05#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:28:50.05#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:28:50.05#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:28:50.05#ibcon#first serial, iclass 35, count 0 2006.286.02:28:50.05#ibcon#enter sib2, iclass 35, count 0 2006.286.02:28:50.05#ibcon#flushed, iclass 35, count 0 2006.286.02:28:50.05#ibcon#about to write, iclass 35, count 0 2006.286.02:28:50.05#ibcon#wrote, iclass 35, count 0 2006.286.02:28:50.05#ibcon#about to read 3, iclass 35, count 0 2006.286.02:28:50.07#ibcon#read 3, iclass 35, count 0 2006.286.02:28:50.07#ibcon#about to read 4, iclass 35, count 0 2006.286.02:28:50.07#ibcon#read 4, iclass 35, count 0 2006.286.02:28:50.07#ibcon#about to read 5, iclass 35, count 0 2006.286.02:28:50.07#ibcon#read 5, iclass 35, count 0 2006.286.02:28:50.07#ibcon#about to read 6, iclass 35, count 0 2006.286.02:28:50.07#ibcon#read 6, iclass 35, count 0 2006.286.02:28:50.07#ibcon#end of sib2, iclass 35, count 0 2006.286.02:28:50.07#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:28:50.07#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:28:50.07#ibcon#[25=USB\r\n] 2006.286.02:28:50.07#ibcon#*before write, iclass 35, count 0 2006.286.02:28:50.07#ibcon#enter sib2, iclass 35, count 0 2006.286.02:28:50.07#ibcon#flushed, iclass 35, count 0 2006.286.02:28:50.07#ibcon#about to write, iclass 35, count 0 2006.286.02:28:50.07#ibcon#wrote, iclass 35, count 0 2006.286.02:28:50.07#ibcon#about to read 3, iclass 35, count 0 2006.286.02:28:50.10#ibcon#read 3, iclass 35, count 0 2006.286.02:28:50.10#ibcon#about to read 4, iclass 35, count 0 2006.286.02:28:50.10#ibcon#read 4, iclass 35, count 0 2006.286.02:28:50.10#ibcon#about to read 5, iclass 35, count 0 2006.286.02:28:50.10#ibcon#read 5, iclass 35, count 0 2006.286.02:28:50.10#ibcon#about to read 6, iclass 35, count 0 2006.286.02:28:50.10#ibcon#read 6, iclass 35, count 0 2006.286.02:28:50.10#ibcon#end of sib2, iclass 35, count 0 2006.286.02:28:50.10#ibcon#*after write, iclass 35, count 0 2006.286.02:28:50.10#ibcon#*before return 0, iclass 35, count 0 2006.286.02:28:50.10#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:28:50.10#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:28:50.10#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:28:50.10#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:28:50.10$vck44/valo=3,564.99 2006.286.02:28:50.10#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.02:28:50.10#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.02:28:50.10#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:50.10#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:28:50.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:28:50.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:28:50.10#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:28:50.10#ibcon#first serial, iclass 37, count 0 2006.286.02:28:50.10#ibcon#enter sib2, iclass 37, count 0 2006.286.02:28:50.10#ibcon#flushed, iclass 37, count 0 2006.286.02:28:50.10#ibcon#about to write, iclass 37, count 0 2006.286.02:28:50.10#ibcon#wrote, iclass 37, count 0 2006.286.02:28:50.10#ibcon#about to read 3, iclass 37, count 0 2006.286.02:28:50.12#ibcon#read 3, iclass 37, count 0 2006.286.02:28:50.12#ibcon#about to read 4, iclass 37, count 0 2006.286.02:28:50.12#ibcon#read 4, iclass 37, count 0 2006.286.02:28:50.12#ibcon#about to read 5, iclass 37, count 0 2006.286.02:28:50.12#ibcon#read 5, iclass 37, count 0 2006.286.02:28:50.12#ibcon#about to read 6, iclass 37, count 0 2006.286.02:28:50.12#ibcon#read 6, iclass 37, count 0 2006.286.02:28:50.12#ibcon#end of sib2, iclass 37, count 0 2006.286.02:28:50.12#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:28:50.12#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:28:50.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.02:28:50.12#ibcon#*before write, iclass 37, count 0 2006.286.02:28:50.12#ibcon#enter sib2, iclass 37, count 0 2006.286.02:28:50.12#ibcon#flushed, iclass 37, count 0 2006.286.02:28:50.12#ibcon#about to write, iclass 37, count 0 2006.286.02:28:50.12#ibcon#wrote, iclass 37, count 0 2006.286.02:28:50.12#ibcon#about to read 3, iclass 37, count 0 2006.286.02:28:50.16#ibcon#read 3, iclass 37, count 0 2006.286.02:28:50.16#ibcon#about to read 4, iclass 37, count 0 2006.286.02:28:50.16#ibcon#read 4, iclass 37, count 0 2006.286.02:28:50.16#ibcon#about to read 5, iclass 37, count 0 2006.286.02:28:50.16#ibcon#read 5, iclass 37, count 0 2006.286.02:28:50.16#ibcon#about to read 6, iclass 37, count 0 2006.286.02:28:50.16#ibcon#read 6, iclass 37, count 0 2006.286.02:28:50.16#ibcon#end of sib2, iclass 37, count 0 2006.286.02:28:50.16#ibcon#*after write, iclass 37, count 0 2006.286.02:28:50.16#ibcon#*before return 0, iclass 37, count 0 2006.286.02:28:50.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:28:50.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:28:50.16#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:28:50.16#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:28:50.16$vck44/va=3,7 2006.286.02:28:50.16#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.02:28:50.16#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.02:28:50.16#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:50.16#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:28:50.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:28:50.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:28:50.22#ibcon#enter wrdev, iclass 39, count 2 2006.286.02:28:50.22#ibcon#first serial, iclass 39, count 2 2006.286.02:28:50.22#ibcon#enter sib2, iclass 39, count 2 2006.286.02:28:50.22#ibcon#flushed, iclass 39, count 2 2006.286.02:28:50.22#ibcon#about to write, iclass 39, count 2 2006.286.02:28:50.22#ibcon#wrote, iclass 39, count 2 2006.286.02:28:50.22#ibcon#about to read 3, iclass 39, count 2 2006.286.02:28:50.24#ibcon#read 3, iclass 39, count 2 2006.286.02:28:50.24#ibcon#about to read 4, iclass 39, count 2 2006.286.02:28:50.24#ibcon#read 4, iclass 39, count 2 2006.286.02:28:50.24#ibcon#about to read 5, iclass 39, count 2 2006.286.02:28:50.24#ibcon#read 5, iclass 39, count 2 2006.286.02:28:50.24#ibcon#about to read 6, iclass 39, count 2 2006.286.02:28:50.24#ibcon#read 6, iclass 39, count 2 2006.286.02:28:50.24#ibcon#end of sib2, iclass 39, count 2 2006.286.02:28:50.24#ibcon#*mode == 0, iclass 39, count 2 2006.286.02:28:50.24#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.02:28:50.24#ibcon#[25=AT03-07\r\n] 2006.286.02:28:50.24#ibcon#*before write, iclass 39, count 2 2006.286.02:28:50.24#ibcon#enter sib2, iclass 39, count 2 2006.286.02:28:50.24#ibcon#flushed, iclass 39, count 2 2006.286.02:28:50.24#ibcon#about to write, iclass 39, count 2 2006.286.02:28:50.24#ibcon#wrote, iclass 39, count 2 2006.286.02:28:50.24#ibcon#about to read 3, iclass 39, count 2 2006.286.02:28:50.27#ibcon#read 3, iclass 39, count 2 2006.286.02:28:50.27#ibcon#about to read 4, iclass 39, count 2 2006.286.02:28:50.27#ibcon#read 4, iclass 39, count 2 2006.286.02:28:50.27#ibcon#about to read 5, iclass 39, count 2 2006.286.02:28:50.27#ibcon#read 5, iclass 39, count 2 2006.286.02:28:50.27#ibcon#about to read 6, iclass 39, count 2 2006.286.02:28:50.27#ibcon#read 6, iclass 39, count 2 2006.286.02:28:50.27#ibcon#end of sib2, iclass 39, count 2 2006.286.02:28:50.27#ibcon#*after write, iclass 39, count 2 2006.286.02:28:50.27#ibcon#*before return 0, iclass 39, count 2 2006.286.02:28:50.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:28:50.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:28:50.27#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.02:28:50.27#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:50.27#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:28:50.39#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:28:50.39#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:28:50.39#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:28:50.39#ibcon#first serial, iclass 39, count 0 2006.286.02:28:50.39#ibcon#enter sib2, iclass 39, count 0 2006.286.02:28:50.39#ibcon#flushed, iclass 39, count 0 2006.286.02:28:50.39#ibcon#about to write, iclass 39, count 0 2006.286.02:28:50.39#ibcon#wrote, iclass 39, count 0 2006.286.02:28:50.39#ibcon#about to read 3, iclass 39, count 0 2006.286.02:28:50.41#ibcon#read 3, iclass 39, count 0 2006.286.02:28:50.41#ibcon#about to read 4, iclass 39, count 0 2006.286.02:28:50.41#ibcon#read 4, iclass 39, count 0 2006.286.02:28:50.41#ibcon#about to read 5, iclass 39, count 0 2006.286.02:28:50.41#ibcon#read 5, iclass 39, count 0 2006.286.02:28:50.41#ibcon#about to read 6, iclass 39, count 0 2006.286.02:28:50.41#ibcon#read 6, iclass 39, count 0 2006.286.02:28:50.41#ibcon#end of sib2, iclass 39, count 0 2006.286.02:28:50.41#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:28:50.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:28:50.41#ibcon#[25=USB\r\n] 2006.286.02:28:50.41#ibcon#*before write, iclass 39, count 0 2006.286.02:28:50.41#ibcon#enter sib2, iclass 39, count 0 2006.286.02:28:50.41#ibcon#flushed, iclass 39, count 0 2006.286.02:28:50.41#ibcon#about to write, iclass 39, count 0 2006.286.02:28:50.41#ibcon#wrote, iclass 39, count 0 2006.286.02:28:50.41#ibcon#about to read 3, iclass 39, count 0 2006.286.02:28:50.44#ibcon#read 3, iclass 39, count 0 2006.286.02:28:50.44#ibcon#about to read 4, iclass 39, count 0 2006.286.02:28:50.44#ibcon#read 4, iclass 39, count 0 2006.286.02:28:50.44#ibcon#about to read 5, iclass 39, count 0 2006.286.02:28:50.44#ibcon#read 5, iclass 39, count 0 2006.286.02:28:50.44#ibcon#about to read 6, iclass 39, count 0 2006.286.02:28:50.44#ibcon#read 6, iclass 39, count 0 2006.286.02:28:50.44#ibcon#end of sib2, iclass 39, count 0 2006.286.02:28:50.44#ibcon#*after write, iclass 39, count 0 2006.286.02:28:50.44#ibcon#*before return 0, iclass 39, count 0 2006.286.02:28:50.44#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:28:50.44#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:28:50.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:28:50.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:28:50.44$vck44/valo=4,624.99 2006.286.02:28:50.44#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.02:28:50.44#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.02:28:50.44#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:50.44#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:28:50.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:28:50.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:28:50.44#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:28:50.44#ibcon#first serial, iclass 3, count 0 2006.286.02:28:50.44#ibcon#enter sib2, iclass 3, count 0 2006.286.02:28:50.44#ibcon#flushed, iclass 3, count 0 2006.286.02:28:50.44#ibcon#about to write, iclass 3, count 0 2006.286.02:28:50.44#ibcon#wrote, iclass 3, count 0 2006.286.02:28:50.44#ibcon#about to read 3, iclass 3, count 0 2006.286.02:28:50.46#ibcon#read 3, iclass 3, count 0 2006.286.02:28:50.46#ibcon#about to read 4, iclass 3, count 0 2006.286.02:28:50.46#ibcon#read 4, iclass 3, count 0 2006.286.02:28:50.46#ibcon#about to read 5, iclass 3, count 0 2006.286.02:28:50.46#ibcon#read 5, iclass 3, count 0 2006.286.02:28:50.46#ibcon#about to read 6, iclass 3, count 0 2006.286.02:28:50.46#ibcon#read 6, iclass 3, count 0 2006.286.02:28:50.46#ibcon#end of sib2, iclass 3, count 0 2006.286.02:28:50.46#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:28:50.46#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:28:50.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.02:28:50.46#ibcon#*before write, iclass 3, count 0 2006.286.02:28:50.46#ibcon#enter sib2, iclass 3, count 0 2006.286.02:28:50.46#ibcon#flushed, iclass 3, count 0 2006.286.02:28:50.46#ibcon#about to write, iclass 3, count 0 2006.286.02:28:50.46#ibcon#wrote, iclass 3, count 0 2006.286.02:28:50.46#ibcon#about to read 3, iclass 3, count 0 2006.286.02:28:50.50#ibcon#read 3, iclass 3, count 0 2006.286.02:28:50.50#ibcon#about to read 4, iclass 3, count 0 2006.286.02:28:50.50#ibcon#read 4, iclass 3, count 0 2006.286.02:28:50.50#ibcon#about to read 5, iclass 3, count 0 2006.286.02:28:50.50#ibcon#read 5, iclass 3, count 0 2006.286.02:28:50.50#ibcon#about to read 6, iclass 3, count 0 2006.286.02:28:50.50#ibcon#read 6, iclass 3, count 0 2006.286.02:28:50.50#ibcon#end of sib2, iclass 3, count 0 2006.286.02:28:50.50#ibcon#*after write, iclass 3, count 0 2006.286.02:28:50.50#ibcon#*before return 0, iclass 3, count 0 2006.286.02:28:50.50#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:28:50.50#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:28:50.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:28:50.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:28:50.50$vck44/va=4,6 2006.286.02:28:50.50#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.02:28:50.50#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.02:28:50.50#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:50.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:28:50.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:28:50.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:28:50.56#ibcon#enter wrdev, iclass 5, count 2 2006.286.02:28:50.56#ibcon#first serial, iclass 5, count 2 2006.286.02:28:50.56#ibcon#enter sib2, iclass 5, count 2 2006.286.02:28:50.56#ibcon#flushed, iclass 5, count 2 2006.286.02:28:50.56#ibcon#about to write, iclass 5, count 2 2006.286.02:28:50.56#ibcon#wrote, iclass 5, count 2 2006.286.02:28:50.56#ibcon#about to read 3, iclass 5, count 2 2006.286.02:28:50.58#ibcon#read 3, iclass 5, count 2 2006.286.02:28:50.58#ibcon#about to read 4, iclass 5, count 2 2006.286.02:28:50.58#ibcon#read 4, iclass 5, count 2 2006.286.02:28:50.58#ibcon#about to read 5, iclass 5, count 2 2006.286.02:28:50.58#ibcon#read 5, iclass 5, count 2 2006.286.02:28:50.58#ibcon#about to read 6, iclass 5, count 2 2006.286.02:28:50.58#ibcon#read 6, iclass 5, count 2 2006.286.02:28:50.58#ibcon#end of sib2, iclass 5, count 2 2006.286.02:28:50.58#ibcon#*mode == 0, iclass 5, count 2 2006.286.02:28:50.58#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.02:28:50.58#ibcon#[25=AT04-06\r\n] 2006.286.02:28:50.58#ibcon#*before write, iclass 5, count 2 2006.286.02:28:50.58#ibcon#enter sib2, iclass 5, count 2 2006.286.02:28:50.58#ibcon#flushed, iclass 5, count 2 2006.286.02:28:50.58#ibcon#about to write, iclass 5, count 2 2006.286.02:28:50.58#ibcon#wrote, iclass 5, count 2 2006.286.02:28:50.58#ibcon#about to read 3, iclass 5, count 2 2006.286.02:28:50.61#ibcon#read 3, iclass 5, count 2 2006.286.02:28:50.61#ibcon#about to read 4, iclass 5, count 2 2006.286.02:28:50.61#ibcon#read 4, iclass 5, count 2 2006.286.02:28:50.61#ibcon#about to read 5, iclass 5, count 2 2006.286.02:28:50.61#ibcon#read 5, iclass 5, count 2 2006.286.02:28:50.61#ibcon#about to read 6, iclass 5, count 2 2006.286.02:28:50.61#ibcon#read 6, iclass 5, count 2 2006.286.02:28:50.61#ibcon#end of sib2, iclass 5, count 2 2006.286.02:28:50.61#ibcon#*after write, iclass 5, count 2 2006.286.02:28:50.61#ibcon#*before return 0, iclass 5, count 2 2006.286.02:28:50.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:28:50.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:28:50.61#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.02:28:50.61#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:50.61#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:28:50.73#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:28:50.73#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:28:50.73#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:28:50.73#ibcon#first serial, iclass 5, count 0 2006.286.02:28:50.73#ibcon#enter sib2, iclass 5, count 0 2006.286.02:28:50.73#ibcon#flushed, iclass 5, count 0 2006.286.02:28:50.73#ibcon#about to write, iclass 5, count 0 2006.286.02:28:50.73#ibcon#wrote, iclass 5, count 0 2006.286.02:28:50.73#ibcon#about to read 3, iclass 5, count 0 2006.286.02:28:50.75#ibcon#read 3, iclass 5, count 0 2006.286.02:28:50.75#ibcon#about to read 4, iclass 5, count 0 2006.286.02:28:50.75#ibcon#read 4, iclass 5, count 0 2006.286.02:28:50.75#ibcon#about to read 5, iclass 5, count 0 2006.286.02:28:50.75#ibcon#read 5, iclass 5, count 0 2006.286.02:28:50.75#ibcon#about to read 6, iclass 5, count 0 2006.286.02:28:50.75#ibcon#read 6, iclass 5, count 0 2006.286.02:28:50.75#ibcon#end of sib2, iclass 5, count 0 2006.286.02:28:50.75#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:28:50.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:28:50.75#ibcon#[25=USB\r\n] 2006.286.02:28:50.75#ibcon#*before write, iclass 5, count 0 2006.286.02:28:50.75#ibcon#enter sib2, iclass 5, count 0 2006.286.02:28:50.75#ibcon#flushed, iclass 5, count 0 2006.286.02:28:50.75#ibcon#about to write, iclass 5, count 0 2006.286.02:28:50.75#ibcon#wrote, iclass 5, count 0 2006.286.02:28:50.75#ibcon#about to read 3, iclass 5, count 0 2006.286.02:28:50.78#ibcon#read 3, iclass 5, count 0 2006.286.02:28:50.78#ibcon#about to read 4, iclass 5, count 0 2006.286.02:28:50.78#ibcon#read 4, iclass 5, count 0 2006.286.02:28:50.78#ibcon#about to read 5, iclass 5, count 0 2006.286.02:28:50.78#ibcon#read 5, iclass 5, count 0 2006.286.02:28:50.78#ibcon#about to read 6, iclass 5, count 0 2006.286.02:28:50.78#ibcon#read 6, iclass 5, count 0 2006.286.02:28:50.78#ibcon#end of sib2, iclass 5, count 0 2006.286.02:28:50.78#ibcon#*after write, iclass 5, count 0 2006.286.02:28:50.78#ibcon#*before return 0, iclass 5, count 0 2006.286.02:28:50.78#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:28:50.78#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:28:50.78#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:28:50.78#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:28:50.78$vck44/valo=5,734.99 2006.286.02:28:50.78#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.02:28:50.78#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.02:28:50.78#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:50.78#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:28:50.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:28:50.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:28:50.78#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:28:50.78#ibcon#first serial, iclass 7, count 0 2006.286.02:28:50.78#ibcon#enter sib2, iclass 7, count 0 2006.286.02:28:50.78#ibcon#flushed, iclass 7, count 0 2006.286.02:28:50.78#ibcon#about to write, iclass 7, count 0 2006.286.02:28:50.78#ibcon#wrote, iclass 7, count 0 2006.286.02:28:50.78#ibcon#about to read 3, iclass 7, count 0 2006.286.02:28:50.80#ibcon#read 3, iclass 7, count 0 2006.286.02:28:50.80#ibcon#about to read 4, iclass 7, count 0 2006.286.02:28:50.80#ibcon#read 4, iclass 7, count 0 2006.286.02:28:50.80#ibcon#about to read 5, iclass 7, count 0 2006.286.02:28:50.80#ibcon#read 5, iclass 7, count 0 2006.286.02:28:50.80#ibcon#about to read 6, iclass 7, count 0 2006.286.02:28:50.80#ibcon#read 6, iclass 7, count 0 2006.286.02:28:50.80#ibcon#end of sib2, iclass 7, count 0 2006.286.02:28:50.80#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:28:50.80#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:28:50.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.02:28:50.80#ibcon#*before write, iclass 7, count 0 2006.286.02:28:50.80#ibcon#enter sib2, iclass 7, count 0 2006.286.02:28:50.80#ibcon#flushed, iclass 7, count 0 2006.286.02:28:50.80#ibcon#about to write, iclass 7, count 0 2006.286.02:28:50.80#ibcon#wrote, iclass 7, count 0 2006.286.02:28:50.80#ibcon#about to read 3, iclass 7, count 0 2006.286.02:28:50.84#ibcon#read 3, iclass 7, count 0 2006.286.02:28:50.84#ibcon#about to read 4, iclass 7, count 0 2006.286.02:28:50.84#ibcon#read 4, iclass 7, count 0 2006.286.02:28:50.84#ibcon#about to read 5, iclass 7, count 0 2006.286.02:28:50.84#ibcon#read 5, iclass 7, count 0 2006.286.02:28:50.84#ibcon#about to read 6, iclass 7, count 0 2006.286.02:28:50.84#ibcon#read 6, iclass 7, count 0 2006.286.02:28:50.84#ibcon#end of sib2, iclass 7, count 0 2006.286.02:28:50.84#ibcon#*after write, iclass 7, count 0 2006.286.02:28:50.84#ibcon#*before return 0, iclass 7, count 0 2006.286.02:28:50.84#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:28:50.84#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:28:50.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:28:50.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:28:50.84$vck44/va=5,3 2006.286.02:28:50.84#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.02:28:50.84#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.02:28:50.84#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:50.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:28:50.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:28:50.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:28:50.90#ibcon#enter wrdev, iclass 11, count 2 2006.286.02:28:50.90#ibcon#first serial, iclass 11, count 2 2006.286.02:28:50.90#ibcon#enter sib2, iclass 11, count 2 2006.286.02:28:50.90#ibcon#flushed, iclass 11, count 2 2006.286.02:28:50.90#ibcon#about to write, iclass 11, count 2 2006.286.02:28:50.90#ibcon#wrote, iclass 11, count 2 2006.286.02:28:50.90#ibcon#about to read 3, iclass 11, count 2 2006.286.02:28:50.92#ibcon#read 3, iclass 11, count 2 2006.286.02:28:50.92#ibcon#about to read 4, iclass 11, count 2 2006.286.02:28:50.92#ibcon#read 4, iclass 11, count 2 2006.286.02:28:50.92#ibcon#about to read 5, iclass 11, count 2 2006.286.02:28:50.92#ibcon#read 5, iclass 11, count 2 2006.286.02:28:50.92#ibcon#about to read 6, iclass 11, count 2 2006.286.02:28:50.92#ibcon#read 6, iclass 11, count 2 2006.286.02:28:50.92#ibcon#end of sib2, iclass 11, count 2 2006.286.02:28:50.92#ibcon#*mode == 0, iclass 11, count 2 2006.286.02:28:50.92#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.02:28:50.92#ibcon#[25=AT05-03\r\n] 2006.286.02:28:50.92#ibcon#*before write, iclass 11, count 2 2006.286.02:28:50.92#ibcon#enter sib2, iclass 11, count 2 2006.286.02:28:50.92#ibcon#flushed, iclass 11, count 2 2006.286.02:28:50.92#ibcon#about to write, iclass 11, count 2 2006.286.02:28:50.92#ibcon#wrote, iclass 11, count 2 2006.286.02:28:50.92#ibcon#about to read 3, iclass 11, count 2 2006.286.02:28:50.95#ibcon#read 3, iclass 11, count 2 2006.286.02:28:50.95#ibcon#about to read 4, iclass 11, count 2 2006.286.02:28:50.95#ibcon#read 4, iclass 11, count 2 2006.286.02:28:50.95#ibcon#about to read 5, iclass 11, count 2 2006.286.02:28:50.95#ibcon#read 5, iclass 11, count 2 2006.286.02:28:50.95#ibcon#about to read 6, iclass 11, count 2 2006.286.02:28:50.95#ibcon#read 6, iclass 11, count 2 2006.286.02:28:50.95#ibcon#end of sib2, iclass 11, count 2 2006.286.02:28:50.95#ibcon#*after write, iclass 11, count 2 2006.286.02:28:50.95#ibcon#*before return 0, iclass 11, count 2 2006.286.02:28:50.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:28:50.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:28:50.95#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.02:28:50.95#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:50.95#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:28:51.07#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:28:51.07#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:28:51.07#ibcon#enter wrdev, iclass 11, count 0 2006.286.02:28:51.07#ibcon#first serial, iclass 11, count 0 2006.286.02:28:51.07#ibcon#enter sib2, iclass 11, count 0 2006.286.02:28:51.07#ibcon#flushed, iclass 11, count 0 2006.286.02:28:51.07#ibcon#about to write, iclass 11, count 0 2006.286.02:28:51.07#ibcon#wrote, iclass 11, count 0 2006.286.02:28:51.07#ibcon#about to read 3, iclass 11, count 0 2006.286.02:28:51.09#ibcon#read 3, iclass 11, count 0 2006.286.02:28:51.09#ibcon#about to read 4, iclass 11, count 0 2006.286.02:28:51.09#ibcon#read 4, iclass 11, count 0 2006.286.02:28:51.09#ibcon#about to read 5, iclass 11, count 0 2006.286.02:28:51.09#ibcon#read 5, iclass 11, count 0 2006.286.02:28:51.09#ibcon#about to read 6, iclass 11, count 0 2006.286.02:28:51.09#ibcon#read 6, iclass 11, count 0 2006.286.02:28:51.09#ibcon#end of sib2, iclass 11, count 0 2006.286.02:28:51.09#ibcon#*mode == 0, iclass 11, count 0 2006.286.02:28:51.09#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.02:28:51.09#ibcon#[25=USB\r\n] 2006.286.02:28:51.09#ibcon#*before write, iclass 11, count 0 2006.286.02:28:51.09#ibcon#enter sib2, iclass 11, count 0 2006.286.02:28:51.09#ibcon#flushed, iclass 11, count 0 2006.286.02:28:51.09#ibcon#about to write, iclass 11, count 0 2006.286.02:28:51.09#ibcon#wrote, iclass 11, count 0 2006.286.02:28:51.09#ibcon#about to read 3, iclass 11, count 0 2006.286.02:28:51.12#ibcon#read 3, iclass 11, count 0 2006.286.02:28:51.12#ibcon#about to read 4, iclass 11, count 0 2006.286.02:28:51.12#ibcon#read 4, iclass 11, count 0 2006.286.02:28:51.12#ibcon#about to read 5, iclass 11, count 0 2006.286.02:28:51.12#ibcon#read 5, iclass 11, count 0 2006.286.02:28:51.12#ibcon#about to read 6, iclass 11, count 0 2006.286.02:28:51.12#ibcon#read 6, iclass 11, count 0 2006.286.02:28:51.12#ibcon#end of sib2, iclass 11, count 0 2006.286.02:28:51.12#ibcon#*after write, iclass 11, count 0 2006.286.02:28:51.12#ibcon#*before return 0, iclass 11, count 0 2006.286.02:28:51.12#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:28:51.12#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:28:51.12#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.02:28:51.12#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.02:28:51.12$vck44/valo=6,814.99 2006.286.02:28:51.12#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.02:28:51.12#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.02:28:51.12#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:51.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:28:51.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:28:51.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:28:51.12#ibcon#enter wrdev, iclass 13, count 0 2006.286.02:28:51.12#ibcon#first serial, iclass 13, count 0 2006.286.02:28:51.12#ibcon#enter sib2, iclass 13, count 0 2006.286.02:28:51.12#ibcon#flushed, iclass 13, count 0 2006.286.02:28:51.12#ibcon#about to write, iclass 13, count 0 2006.286.02:28:51.12#ibcon#wrote, iclass 13, count 0 2006.286.02:28:51.12#ibcon#about to read 3, iclass 13, count 0 2006.286.02:28:51.14#ibcon#read 3, iclass 13, count 0 2006.286.02:28:51.14#ibcon#about to read 4, iclass 13, count 0 2006.286.02:28:51.14#ibcon#read 4, iclass 13, count 0 2006.286.02:28:51.14#ibcon#about to read 5, iclass 13, count 0 2006.286.02:28:51.14#ibcon#read 5, iclass 13, count 0 2006.286.02:28:51.14#ibcon#about to read 6, iclass 13, count 0 2006.286.02:28:51.14#ibcon#read 6, iclass 13, count 0 2006.286.02:28:51.14#ibcon#end of sib2, iclass 13, count 0 2006.286.02:28:51.14#ibcon#*mode == 0, iclass 13, count 0 2006.286.02:28:51.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.02:28:51.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.02:28:51.14#ibcon#*before write, iclass 13, count 0 2006.286.02:28:51.14#ibcon#enter sib2, iclass 13, count 0 2006.286.02:28:51.14#ibcon#flushed, iclass 13, count 0 2006.286.02:28:51.14#ibcon#about to write, iclass 13, count 0 2006.286.02:28:51.14#ibcon#wrote, iclass 13, count 0 2006.286.02:28:51.14#ibcon#about to read 3, iclass 13, count 0 2006.286.02:28:51.18#ibcon#read 3, iclass 13, count 0 2006.286.02:28:51.18#ibcon#about to read 4, iclass 13, count 0 2006.286.02:28:51.18#ibcon#read 4, iclass 13, count 0 2006.286.02:28:51.18#ibcon#about to read 5, iclass 13, count 0 2006.286.02:28:51.18#ibcon#read 5, iclass 13, count 0 2006.286.02:28:51.18#ibcon#about to read 6, iclass 13, count 0 2006.286.02:28:51.18#ibcon#read 6, iclass 13, count 0 2006.286.02:28:51.18#ibcon#end of sib2, iclass 13, count 0 2006.286.02:28:51.18#ibcon#*after write, iclass 13, count 0 2006.286.02:28:51.18#ibcon#*before return 0, iclass 13, count 0 2006.286.02:28:51.18#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:28:51.18#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:28:51.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.02:28:51.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.02:28:51.18$vck44/va=6,4 2006.286.02:28:51.18#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.02:28:51.18#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.02:28:51.18#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:51.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:28:51.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:28:51.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:28:51.24#ibcon#enter wrdev, iclass 15, count 2 2006.286.02:28:51.24#ibcon#first serial, iclass 15, count 2 2006.286.02:28:51.24#ibcon#enter sib2, iclass 15, count 2 2006.286.02:28:51.24#ibcon#flushed, iclass 15, count 2 2006.286.02:28:51.24#ibcon#about to write, iclass 15, count 2 2006.286.02:28:51.24#ibcon#wrote, iclass 15, count 2 2006.286.02:28:51.24#ibcon#about to read 3, iclass 15, count 2 2006.286.02:28:51.26#ibcon#read 3, iclass 15, count 2 2006.286.02:28:51.26#ibcon#about to read 4, iclass 15, count 2 2006.286.02:28:51.26#ibcon#read 4, iclass 15, count 2 2006.286.02:28:51.26#ibcon#about to read 5, iclass 15, count 2 2006.286.02:28:51.26#ibcon#read 5, iclass 15, count 2 2006.286.02:28:51.26#ibcon#about to read 6, iclass 15, count 2 2006.286.02:28:51.26#ibcon#read 6, iclass 15, count 2 2006.286.02:28:51.26#ibcon#end of sib2, iclass 15, count 2 2006.286.02:28:51.26#ibcon#*mode == 0, iclass 15, count 2 2006.286.02:28:51.26#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.02:28:51.26#ibcon#[25=AT06-04\r\n] 2006.286.02:28:51.26#ibcon#*before write, iclass 15, count 2 2006.286.02:28:51.26#ibcon#enter sib2, iclass 15, count 2 2006.286.02:28:51.26#ibcon#flushed, iclass 15, count 2 2006.286.02:28:51.26#ibcon#about to write, iclass 15, count 2 2006.286.02:28:51.26#ibcon#wrote, iclass 15, count 2 2006.286.02:28:51.26#ibcon#about to read 3, iclass 15, count 2 2006.286.02:28:51.29#ibcon#read 3, iclass 15, count 2 2006.286.02:28:51.29#ibcon#about to read 4, iclass 15, count 2 2006.286.02:28:51.29#ibcon#read 4, iclass 15, count 2 2006.286.02:28:51.29#ibcon#about to read 5, iclass 15, count 2 2006.286.02:28:51.29#ibcon#read 5, iclass 15, count 2 2006.286.02:28:51.29#ibcon#about to read 6, iclass 15, count 2 2006.286.02:28:51.29#ibcon#read 6, iclass 15, count 2 2006.286.02:28:51.29#ibcon#end of sib2, iclass 15, count 2 2006.286.02:28:51.29#ibcon#*after write, iclass 15, count 2 2006.286.02:28:51.29#ibcon#*before return 0, iclass 15, count 2 2006.286.02:28:51.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:28:51.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:28:51.29#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.02:28:51.29#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:51.29#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:28:51.41#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:28:51.41#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:28:51.41#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:28:51.41#ibcon#first serial, iclass 15, count 0 2006.286.02:28:51.41#ibcon#enter sib2, iclass 15, count 0 2006.286.02:28:51.41#ibcon#flushed, iclass 15, count 0 2006.286.02:28:51.41#ibcon#about to write, iclass 15, count 0 2006.286.02:28:51.41#ibcon#wrote, iclass 15, count 0 2006.286.02:28:51.41#ibcon#about to read 3, iclass 15, count 0 2006.286.02:28:51.43#ibcon#read 3, iclass 15, count 0 2006.286.02:28:51.43#ibcon#about to read 4, iclass 15, count 0 2006.286.02:28:51.43#ibcon#read 4, iclass 15, count 0 2006.286.02:28:51.43#ibcon#about to read 5, iclass 15, count 0 2006.286.02:28:51.43#ibcon#read 5, iclass 15, count 0 2006.286.02:28:51.43#ibcon#about to read 6, iclass 15, count 0 2006.286.02:28:51.43#ibcon#read 6, iclass 15, count 0 2006.286.02:28:51.43#ibcon#end of sib2, iclass 15, count 0 2006.286.02:28:51.43#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:28:51.43#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:28:51.43#ibcon#[25=USB\r\n] 2006.286.02:28:51.43#ibcon#*before write, iclass 15, count 0 2006.286.02:28:51.43#ibcon#enter sib2, iclass 15, count 0 2006.286.02:28:51.43#ibcon#flushed, iclass 15, count 0 2006.286.02:28:51.43#ibcon#about to write, iclass 15, count 0 2006.286.02:28:51.43#ibcon#wrote, iclass 15, count 0 2006.286.02:28:51.43#ibcon#about to read 3, iclass 15, count 0 2006.286.02:28:51.46#ibcon#read 3, iclass 15, count 0 2006.286.02:28:51.46#ibcon#about to read 4, iclass 15, count 0 2006.286.02:28:51.46#ibcon#read 4, iclass 15, count 0 2006.286.02:28:51.46#ibcon#about to read 5, iclass 15, count 0 2006.286.02:28:51.46#ibcon#read 5, iclass 15, count 0 2006.286.02:28:51.46#ibcon#about to read 6, iclass 15, count 0 2006.286.02:28:51.46#ibcon#read 6, iclass 15, count 0 2006.286.02:28:51.46#ibcon#end of sib2, iclass 15, count 0 2006.286.02:28:51.46#ibcon#*after write, iclass 15, count 0 2006.286.02:28:51.46#ibcon#*before return 0, iclass 15, count 0 2006.286.02:28:51.46#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:28:51.46#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:28:51.46#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:28:51.46#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:28:51.46$vck44/valo=7,864.99 2006.286.02:28:51.46#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.02:28:51.46#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.02:28:51.46#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:51.46#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:28:51.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:28:51.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:28:51.46#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:28:51.46#ibcon#first serial, iclass 17, count 0 2006.286.02:28:51.46#ibcon#enter sib2, iclass 17, count 0 2006.286.02:28:51.46#ibcon#flushed, iclass 17, count 0 2006.286.02:28:51.46#ibcon#about to write, iclass 17, count 0 2006.286.02:28:51.46#ibcon#wrote, iclass 17, count 0 2006.286.02:28:51.46#ibcon#about to read 3, iclass 17, count 0 2006.286.02:28:51.48#ibcon#read 3, iclass 17, count 0 2006.286.02:28:51.48#ibcon#about to read 4, iclass 17, count 0 2006.286.02:28:51.48#ibcon#read 4, iclass 17, count 0 2006.286.02:28:51.48#ibcon#about to read 5, iclass 17, count 0 2006.286.02:28:51.48#ibcon#read 5, iclass 17, count 0 2006.286.02:28:51.48#ibcon#about to read 6, iclass 17, count 0 2006.286.02:28:51.48#ibcon#read 6, iclass 17, count 0 2006.286.02:28:51.48#ibcon#end of sib2, iclass 17, count 0 2006.286.02:28:51.48#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:28:51.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:28:51.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.02:28:51.48#ibcon#*before write, iclass 17, count 0 2006.286.02:28:51.48#ibcon#enter sib2, iclass 17, count 0 2006.286.02:28:51.48#ibcon#flushed, iclass 17, count 0 2006.286.02:28:51.48#ibcon#about to write, iclass 17, count 0 2006.286.02:28:51.48#ibcon#wrote, iclass 17, count 0 2006.286.02:28:51.48#ibcon#about to read 3, iclass 17, count 0 2006.286.02:28:51.52#ibcon#read 3, iclass 17, count 0 2006.286.02:28:51.52#ibcon#about to read 4, iclass 17, count 0 2006.286.02:28:51.52#ibcon#read 4, iclass 17, count 0 2006.286.02:28:51.52#ibcon#about to read 5, iclass 17, count 0 2006.286.02:28:51.52#ibcon#read 5, iclass 17, count 0 2006.286.02:28:51.52#ibcon#about to read 6, iclass 17, count 0 2006.286.02:28:51.52#ibcon#read 6, iclass 17, count 0 2006.286.02:28:51.52#ibcon#end of sib2, iclass 17, count 0 2006.286.02:28:51.52#ibcon#*after write, iclass 17, count 0 2006.286.02:28:51.52#ibcon#*before return 0, iclass 17, count 0 2006.286.02:28:51.52#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:28:51.52#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:28:51.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:28:51.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:28:51.52$vck44/va=7,4 2006.286.02:28:51.52#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.02:28:51.52#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.02:28:51.52#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:51.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:28:51.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:28:51.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:28:51.58#ibcon#enter wrdev, iclass 19, count 2 2006.286.02:28:51.58#ibcon#first serial, iclass 19, count 2 2006.286.02:28:51.58#ibcon#enter sib2, iclass 19, count 2 2006.286.02:28:51.58#ibcon#flushed, iclass 19, count 2 2006.286.02:28:51.58#ibcon#about to write, iclass 19, count 2 2006.286.02:28:51.58#ibcon#wrote, iclass 19, count 2 2006.286.02:28:51.58#ibcon#about to read 3, iclass 19, count 2 2006.286.02:28:51.60#ibcon#read 3, iclass 19, count 2 2006.286.02:28:51.60#ibcon#about to read 4, iclass 19, count 2 2006.286.02:28:51.60#ibcon#read 4, iclass 19, count 2 2006.286.02:28:51.60#ibcon#about to read 5, iclass 19, count 2 2006.286.02:28:51.60#ibcon#read 5, iclass 19, count 2 2006.286.02:28:51.60#ibcon#about to read 6, iclass 19, count 2 2006.286.02:28:51.60#ibcon#read 6, iclass 19, count 2 2006.286.02:28:51.60#ibcon#end of sib2, iclass 19, count 2 2006.286.02:28:51.60#ibcon#*mode == 0, iclass 19, count 2 2006.286.02:28:51.60#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.02:28:51.60#ibcon#[25=AT07-04\r\n] 2006.286.02:28:51.60#ibcon#*before write, iclass 19, count 2 2006.286.02:28:51.60#ibcon#enter sib2, iclass 19, count 2 2006.286.02:28:51.60#ibcon#flushed, iclass 19, count 2 2006.286.02:28:51.60#ibcon#about to write, iclass 19, count 2 2006.286.02:28:51.60#ibcon#wrote, iclass 19, count 2 2006.286.02:28:51.60#ibcon#about to read 3, iclass 19, count 2 2006.286.02:28:51.63#ibcon#read 3, iclass 19, count 2 2006.286.02:28:51.63#ibcon#about to read 4, iclass 19, count 2 2006.286.02:28:51.63#ibcon#read 4, iclass 19, count 2 2006.286.02:28:51.63#ibcon#about to read 5, iclass 19, count 2 2006.286.02:28:51.63#ibcon#read 5, iclass 19, count 2 2006.286.02:28:51.63#ibcon#about to read 6, iclass 19, count 2 2006.286.02:28:51.63#ibcon#read 6, iclass 19, count 2 2006.286.02:28:51.63#ibcon#end of sib2, iclass 19, count 2 2006.286.02:28:51.63#ibcon#*after write, iclass 19, count 2 2006.286.02:28:51.63#ibcon#*before return 0, iclass 19, count 2 2006.286.02:28:51.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:28:51.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:28:51.63#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.02:28:51.63#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:51.63#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:28:51.75#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:28:51.75#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:28:51.75#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:28:51.75#ibcon#first serial, iclass 19, count 0 2006.286.02:28:51.75#ibcon#enter sib2, iclass 19, count 0 2006.286.02:28:51.75#ibcon#flushed, iclass 19, count 0 2006.286.02:28:51.75#ibcon#about to write, iclass 19, count 0 2006.286.02:28:51.75#ibcon#wrote, iclass 19, count 0 2006.286.02:28:51.75#ibcon#about to read 3, iclass 19, count 0 2006.286.02:28:51.77#ibcon#read 3, iclass 19, count 0 2006.286.02:28:51.77#ibcon#about to read 4, iclass 19, count 0 2006.286.02:28:51.77#ibcon#read 4, iclass 19, count 0 2006.286.02:28:51.77#ibcon#about to read 5, iclass 19, count 0 2006.286.02:28:51.77#ibcon#read 5, iclass 19, count 0 2006.286.02:28:51.77#ibcon#about to read 6, iclass 19, count 0 2006.286.02:28:51.77#ibcon#read 6, iclass 19, count 0 2006.286.02:28:51.77#ibcon#end of sib2, iclass 19, count 0 2006.286.02:28:51.77#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:28:51.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:28:51.77#ibcon#[25=USB\r\n] 2006.286.02:28:51.77#ibcon#*before write, iclass 19, count 0 2006.286.02:28:51.77#ibcon#enter sib2, iclass 19, count 0 2006.286.02:28:51.77#ibcon#flushed, iclass 19, count 0 2006.286.02:28:51.77#ibcon#about to write, iclass 19, count 0 2006.286.02:28:51.77#ibcon#wrote, iclass 19, count 0 2006.286.02:28:51.77#ibcon#about to read 3, iclass 19, count 0 2006.286.02:28:51.80#ibcon#read 3, iclass 19, count 0 2006.286.02:28:51.80#ibcon#about to read 4, iclass 19, count 0 2006.286.02:28:51.80#ibcon#read 4, iclass 19, count 0 2006.286.02:28:51.80#ibcon#about to read 5, iclass 19, count 0 2006.286.02:28:51.80#ibcon#read 5, iclass 19, count 0 2006.286.02:28:51.80#ibcon#about to read 6, iclass 19, count 0 2006.286.02:28:51.80#ibcon#read 6, iclass 19, count 0 2006.286.02:28:51.80#ibcon#end of sib2, iclass 19, count 0 2006.286.02:28:51.80#ibcon#*after write, iclass 19, count 0 2006.286.02:28:51.80#ibcon#*before return 0, iclass 19, count 0 2006.286.02:28:51.80#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:28:51.80#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:28:51.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:28:51.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:28:51.80$vck44/valo=8,884.99 2006.286.02:28:51.80#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.02:28:51.80#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.02:28:51.80#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:51.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:28:51.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:28:51.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:28:51.80#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:28:51.80#ibcon#first serial, iclass 21, count 0 2006.286.02:28:51.80#ibcon#enter sib2, iclass 21, count 0 2006.286.02:28:51.80#ibcon#flushed, iclass 21, count 0 2006.286.02:28:51.80#ibcon#about to write, iclass 21, count 0 2006.286.02:28:51.80#ibcon#wrote, iclass 21, count 0 2006.286.02:28:51.80#ibcon#about to read 3, iclass 21, count 0 2006.286.02:28:51.82#ibcon#read 3, iclass 21, count 0 2006.286.02:28:51.82#ibcon#about to read 4, iclass 21, count 0 2006.286.02:28:51.82#ibcon#read 4, iclass 21, count 0 2006.286.02:28:51.82#ibcon#about to read 5, iclass 21, count 0 2006.286.02:28:51.82#ibcon#read 5, iclass 21, count 0 2006.286.02:28:51.82#ibcon#about to read 6, iclass 21, count 0 2006.286.02:28:51.82#ibcon#read 6, iclass 21, count 0 2006.286.02:28:51.82#ibcon#end of sib2, iclass 21, count 0 2006.286.02:28:51.82#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:28:51.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:28:51.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.02:28:51.82#ibcon#*before write, iclass 21, count 0 2006.286.02:28:51.82#ibcon#enter sib2, iclass 21, count 0 2006.286.02:28:51.82#ibcon#flushed, iclass 21, count 0 2006.286.02:28:51.82#ibcon#about to write, iclass 21, count 0 2006.286.02:28:51.82#ibcon#wrote, iclass 21, count 0 2006.286.02:28:51.82#ibcon#about to read 3, iclass 21, count 0 2006.286.02:28:51.86#ibcon#read 3, iclass 21, count 0 2006.286.02:28:51.86#ibcon#about to read 4, iclass 21, count 0 2006.286.02:28:51.86#ibcon#read 4, iclass 21, count 0 2006.286.02:28:51.86#ibcon#about to read 5, iclass 21, count 0 2006.286.02:28:51.86#ibcon#read 5, iclass 21, count 0 2006.286.02:28:51.86#ibcon#about to read 6, iclass 21, count 0 2006.286.02:28:51.86#ibcon#read 6, iclass 21, count 0 2006.286.02:28:51.86#ibcon#end of sib2, iclass 21, count 0 2006.286.02:28:51.86#ibcon#*after write, iclass 21, count 0 2006.286.02:28:51.86#ibcon#*before return 0, iclass 21, count 0 2006.286.02:28:51.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:28:51.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:28:51.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:28:51.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:28:51.86$vck44/va=8,3 2006.286.02:28:51.86#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.02:28:51.86#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.02:28:51.86#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:51.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:28:51.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:28:51.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:28:51.92#ibcon#enter wrdev, iclass 23, count 2 2006.286.02:28:51.92#ibcon#first serial, iclass 23, count 2 2006.286.02:28:51.92#ibcon#enter sib2, iclass 23, count 2 2006.286.02:28:51.92#ibcon#flushed, iclass 23, count 2 2006.286.02:28:51.92#ibcon#about to write, iclass 23, count 2 2006.286.02:28:51.92#ibcon#wrote, iclass 23, count 2 2006.286.02:28:51.92#ibcon#about to read 3, iclass 23, count 2 2006.286.02:28:51.94#ibcon#read 3, iclass 23, count 2 2006.286.02:28:51.94#ibcon#about to read 4, iclass 23, count 2 2006.286.02:28:51.94#ibcon#read 4, iclass 23, count 2 2006.286.02:28:51.94#ibcon#about to read 5, iclass 23, count 2 2006.286.02:28:51.94#ibcon#read 5, iclass 23, count 2 2006.286.02:28:51.94#ibcon#about to read 6, iclass 23, count 2 2006.286.02:28:51.94#ibcon#read 6, iclass 23, count 2 2006.286.02:28:51.94#ibcon#end of sib2, iclass 23, count 2 2006.286.02:28:51.94#ibcon#*mode == 0, iclass 23, count 2 2006.286.02:28:51.94#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.02:28:51.94#ibcon#[25=AT08-03\r\n] 2006.286.02:28:51.94#ibcon#*before write, iclass 23, count 2 2006.286.02:28:51.94#ibcon#enter sib2, iclass 23, count 2 2006.286.02:28:51.94#ibcon#flushed, iclass 23, count 2 2006.286.02:28:51.94#ibcon#about to write, iclass 23, count 2 2006.286.02:28:51.94#ibcon#wrote, iclass 23, count 2 2006.286.02:28:51.94#ibcon#about to read 3, iclass 23, count 2 2006.286.02:28:51.97#ibcon#read 3, iclass 23, count 2 2006.286.02:28:51.97#ibcon#about to read 4, iclass 23, count 2 2006.286.02:28:51.97#ibcon#read 4, iclass 23, count 2 2006.286.02:28:51.97#ibcon#about to read 5, iclass 23, count 2 2006.286.02:28:51.97#ibcon#read 5, iclass 23, count 2 2006.286.02:28:51.97#ibcon#about to read 6, iclass 23, count 2 2006.286.02:28:51.97#ibcon#read 6, iclass 23, count 2 2006.286.02:28:51.97#ibcon#end of sib2, iclass 23, count 2 2006.286.02:28:51.97#ibcon#*after write, iclass 23, count 2 2006.286.02:28:51.97#ibcon#*before return 0, iclass 23, count 2 2006.286.02:28:51.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:28:51.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:28:51.97#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.02:28:51.97#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:51.97#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:28:52.09#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:28:52.09#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:28:52.09#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:28:52.09#ibcon#first serial, iclass 23, count 0 2006.286.02:28:52.09#ibcon#enter sib2, iclass 23, count 0 2006.286.02:28:52.09#ibcon#flushed, iclass 23, count 0 2006.286.02:28:52.09#ibcon#about to write, iclass 23, count 0 2006.286.02:28:52.09#ibcon#wrote, iclass 23, count 0 2006.286.02:28:52.09#ibcon#about to read 3, iclass 23, count 0 2006.286.02:28:52.11#ibcon#read 3, iclass 23, count 0 2006.286.02:28:52.11#ibcon#about to read 4, iclass 23, count 0 2006.286.02:28:52.11#ibcon#read 4, iclass 23, count 0 2006.286.02:28:52.11#ibcon#about to read 5, iclass 23, count 0 2006.286.02:28:52.11#ibcon#read 5, iclass 23, count 0 2006.286.02:28:52.11#ibcon#about to read 6, iclass 23, count 0 2006.286.02:28:52.11#ibcon#read 6, iclass 23, count 0 2006.286.02:28:52.11#ibcon#end of sib2, iclass 23, count 0 2006.286.02:28:52.11#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:28:52.11#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:28:52.11#ibcon#[25=USB\r\n] 2006.286.02:28:52.11#ibcon#*before write, iclass 23, count 0 2006.286.02:28:52.11#ibcon#enter sib2, iclass 23, count 0 2006.286.02:28:52.11#ibcon#flushed, iclass 23, count 0 2006.286.02:28:52.11#ibcon#about to write, iclass 23, count 0 2006.286.02:28:52.11#ibcon#wrote, iclass 23, count 0 2006.286.02:28:52.11#ibcon#about to read 3, iclass 23, count 0 2006.286.02:28:52.14#ibcon#read 3, iclass 23, count 0 2006.286.02:28:52.14#ibcon#about to read 4, iclass 23, count 0 2006.286.02:28:52.14#ibcon#read 4, iclass 23, count 0 2006.286.02:28:52.14#ibcon#about to read 5, iclass 23, count 0 2006.286.02:28:52.14#ibcon#read 5, iclass 23, count 0 2006.286.02:28:52.14#ibcon#about to read 6, iclass 23, count 0 2006.286.02:28:52.14#ibcon#read 6, iclass 23, count 0 2006.286.02:28:52.14#ibcon#end of sib2, iclass 23, count 0 2006.286.02:28:52.14#ibcon#*after write, iclass 23, count 0 2006.286.02:28:52.14#ibcon#*before return 0, iclass 23, count 0 2006.286.02:28:52.14#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:28:52.14#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:28:52.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:28:52.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:28:52.14$vck44/vblo=1,629.99 2006.286.02:28:52.14#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.02:28:52.14#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.02:28:52.14#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:52.14#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:28:52.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:28:52.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:28:52.14#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:28:52.14#ibcon#first serial, iclass 25, count 0 2006.286.02:28:52.14#ibcon#enter sib2, iclass 25, count 0 2006.286.02:28:52.14#ibcon#flushed, iclass 25, count 0 2006.286.02:28:52.14#ibcon#about to write, iclass 25, count 0 2006.286.02:28:52.14#ibcon#wrote, iclass 25, count 0 2006.286.02:28:52.14#ibcon#about to read 3, iclass 25, count 0 2006.286.02:28:52.16#ibcon#read 3, iclass 25, count 0 2006.286.02:28:52.16#ibcon#about to read 4, iclass 25, count 0 2006.286.02:28:52.16#ibcon#read 4, iclass 25, count 0 2006.286.02:28:52.16#ibcon#about to read 5, iclass 25, count 0 2006.286.02:28:52.16#ibcon#read 5, iclass 25, count 0 2006.286.02:28:52.16#ibcon#about to read 6, iclass 25, count 0 2006.286.02:28:52.16#ibcon#read 6, iclass 25, count 0 2006.286.02:28:52.16#ibcon#end of sib2, iclass 25, count 0 2006.286.02:28:52.16#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:28:52.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:28:52.16#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.02:28:52.16#ibcon#*before write, iclass 25, count 0 2006.286.02:28:52.16#ibcon#enter sib2, iclass 25, count 0 2006.286.02:28:52.16#ibcon#flushed, iclass 25, count 0 2006.286.02:28:52.16#ibcon#about to write, iclass 25, count 0 2006.286.02:28:52.16#ibcon#wrote, iclass 25, count 0 2006.286.02:28:52.16#ibcon#about to read 3, iclass 25, count 0 2006.286.02:28:52.20#ibcon#read 3, iclass 25, count 0 2006.286.02:28:52.20#ibcon#about to read 4, iclass 25, count 0 2006.286.02:28:52.20#ibcon#read 4, iclass 25, count 0 2006.286.02:28:52.20#ibcon#about to read 5, iclass 25, count 0 2006.286.02:28:52.20#ibcon#read 5, iclass 25, count 0 2006.286.02:28:52.20#ibcon#about to read 6, iclass 25, count 0 2006.286.02:28:52.20#ibcon#read 6, iclass 25, count 0 2006.286.02:28:52.20#ibcon#end of sib2, iclass 25, count 0 2006.286.02:28:52.20#ibcon#*after write, iclass 25, count 0 2006.286.02:28:52.20#ibcon#*before return 0, iclass 25, count 0 2006.286.02:28:52.20#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:28:52.20#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:28:52.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:28:52.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:28:52.20$vck44/vb=1,4 2006.286.02:28:52.20#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.02:28:52.20#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.02:28:52.20#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:52.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:28:52.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:28:52.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:28:52.20#ibcon#enter wrdev, iclass 27, count 2 2006.286.02:28:52.20#ibcon#first serial, iclass 27, count 2 2006.286.02:28:52.20#ibcon#enter sib2, iclass 27, count 2 2006.286.02:28:52.20#ibcon#flushed, iclass 27, count 2 2006.286.02:28:52.20#ibcon#about to write, iclass 27, count 2 2006.286.02:28:52.20#ibcon#wrote, iclass 27, count 2 2006.286.02:28:52.20#ibcon#about to read 3, iclass 27, count 2 2006.286.02:28:52.22#ibcon#read 3, iclass 27, count 2 2006.286.02:28:52.22#ibcon#about to read 4, iclass 27, count 2 2006.286.02:28:52.22#ibcon#read 4, iclass 27, count 2 2006.286.02:28:52.22#ibcon#about to read 5, iclass 27, count 2 2006.286.02:28:52.22#ibcon#read 5, iclass 27, count 2 2006.286.02:28:52.22#ibcon#about to read 6, iclass 27, count 2 2006.286.02:28:52.22#ibcon#read 6, iclass 27, count 2 2006.286.02:28:52.22#ibcon#end of sib2, iclass 27, count 2 2006.286.02:28:52.22#ibcon#*mode == 0, iclass 27, count 2 2006.286.02:28:52.22#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.02:28:52.22#ibcon#[27=AT01-04\r\n] 2006.286.02:28:52.22#ibcon#*before write, iclass 27, count 2 2006.286.02:28:52.22#ibcon#enter sib2, iclass 27, count 2 2006.286.02:28:52.22#ibcon#flushed, iclass 27, count 2 2006.286.02:28:52.22#ibcon#about to write, iclass 27, count 2 2006.286.02:28:52.22#ibcon#wrote, iclass 27, count 2 2006.286.02:28:52.22#ibcon#about to read 3, iclass 27, count 2 2006.286.02:28:52.25#ibcon#read 3, iclass 27, count 2 2006.286.02:28:52.25#ibcon#about to read 4, iclass 27, count 2 2006.286.02:28:52.25#ibcon#read 4, iclass 27, count 2 2006.286.02:28:52.25#ibcon#about to read 5, iclass 27, count 2 2006.286.02:28:52.25#ibcon#read 5, iclass 27, count 2 2006.286.02:28:52.25#ibcon#about to read 6, iclass 27, count 2 2006.286.02:28:52.25#ibcon#read 6, iclass 27, count 2 2006.286.02:28:52.25#ibcon#end of sib2, iclass 27, count 2 2006.286.02:28:52.25#ibcon#*after write, iclass 27, count 2 2006.286.02:28:52.25#ibcon#*before return 0, iclass 27, count 2 2006.286.02:28:52.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:28:52.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:28:52.25#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.02:28:52.25#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:52.25#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:28:52.37#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:28:52.37#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:28:52.37#ibcon#enter wrdev, iclass 27, count 0 2006.286.02:28:52.37#ibcon#first serial, iclass 27, count 0 2006.286.02:28:52.37#ibcon#enter sib2, iclass 27, count 0 2006.286.02:28:52.37#ibcon#flushed, iclass 27, count 0 2006.286.02:28:52.37#ibcon#about to write, iclass 27, count 0 2006.286.02:28:52.37#ibcon#wrote, iclass 27, count 0 2006.286.02:28:52.37#ibcon#about to read 3, iclass 27, count 0 2006.286.02:28:52.39#ibcon#read 3, iclass 27, count 0 2006.286.02:28:52.39#ibcon#about to read 4, iclass 27, count 0 2006.286.02:28:52.39#ibcon#read 4, iclass 27, count 0 2006.286.02:28:52.39#ibcon#about to read 5, iclass 27, count 0 2006.286.02:28:52.39#ibcon#read 5, iclass 27, count 0 2006.286.02:28:52.39#ibcon#about to read 6, iclass 27, count 0 2006.286.02:28:52.39#ibcon#read 6, iclass 27, count 0 2006.286.02:28:52.39#ibcon#end of sib2, iclass 27, count 0 2006.286.02:28:52.39#ibcon#*mode == 0, iclass 27, count 0 2006.286.02:28:52.39#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.02:28:52.39#ibcon#[27=USB\r\n] 2006.286.02:28:52.39#ibcon#*before write, iclass 27, count 0 2006.286.02:28:52.39#ibcon#enter sib2, iclass 27, count 0 2006.286.02:28:52.39#ibcon#flushed, iclass 27, count 0 2006.286.02:28:52.39#ibcon#about to write, iclass 27, count 0 2006.286.02:28:52.39#ibcon#wrote, iclass 27, count 0 2006.286.02:28:52.39#ibcon#about to read 3, iclass 27, count 0 2006.286.02:28:52.42#ibcon#read 3, iclass 27, count 0 2006.286.02:28:52.42#ibcon#about to read 4, iclass 27, count 0 2006.286.02:28:52.42#ibcon#read 4, iclass 27, count 0 2006.286.02:28:52.42#ibcon#about to read 5, iclass 27, count 0 2006.286.02:28:52.42#ibcon#read 5, iclass 27, count 0 2006.286.02:28:52.42#ibcon#about to read 6, iclass 27, count 0 2006.286.02:28:52.42#ibcon#read 6, iclass 27, count 0 2006.286.02:28:52.42#ibcon#end of sib2, iclass 27, count 0 2006.286.02:28:52.42#ibcon#*after write, iclass 27, count 0 2006.286.02:28:52.42#ibcon#*before return 0, iclass 27, count 0 2006.286.02:28:52.42#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:28:52.42#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:28:52.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.02:28:52.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.02:28:52.42$vck44/vblo=2,634.99 2006.286.02:28:52.42#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.02:28:52.42#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.02:28:52.42#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:52.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:28:52.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:28:52.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:28:52.42#ibcon#enter wrdev, iclass 29, count 0 2006.286.02:28:52.42#ibcon#first serial, iclass 29, count 0 2006.286.02:28:52.42#ibcon#enter sib2, iclass 29, count 0 2006.286.02:28:52.42#ibcon#flushed, iclass 29, count 0 2006.286.02:28:52.42#ibcon#about to write, iclass 29, count 0 2006.286.02:28:52.42#ibcon#wrote, iclass 29, count 0 2006.286.02:28:52.42#ibcon#about to read 3, iclass 29, count 0 2006.286.02:28:52.44#ibcon#read 3, iclass 29, count 0 2006.286.02:28:52.44#ibcon#about to read 4, iclass 29, count 0 2006.286.02:28:52.44#ibcon#read 4, iclass 29, count 0 2006.286.02:28:52.44#ibcon#about to read 5, iclass 29, count 0 2006.286.02:28:52.44#ibcon#read 5, iclass 29, count 0 2006.286.02:28:52.44#ibcon#about to read 6, iclass 29, count 0 2006.286.02:28:52.44#ibcon#read 6, iclass 29, count 0 2006.286.02:28:52.44#ibcon#end of sib2, iclass 29, count 0 2006.286.02:28:52.44#ibcon#*mode == 0, iclass 29, count 0 2006.286.02:28:52.44#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.02:28:52.44#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.02:28:52.44#ibcon#*before write, iclass 29, count 0 2006.286.02:28:52.44#ibcon#enter sib2, iclass 29, count 0 2006.286.02:28:52.44#ibcon#flushed, iclass 29, count 0 2006.286.02:28:52.44#ibcon#about to write, iclass 29, count 0 2006.286.02:28:52.44#ibcon#wrote, iclass 29, count 0 2006.286.02:28:52.44#ibcon#about to read 3, iclass 29, count 0 2006.286.02:28:52.48#ibcon#read 3, iclass 29, count 0 2006.286.02:28:52.48#ibcon#about to read 4, iclass 29, count 0 2006.286.02:28:52.48#ibcon#read 4, iclass 29, count 0 2006.286.02:28:52.48#ibcon#about to read 5, iclass 29, count 0 2006.286.02:28:52.48#ibcon#read 5, iclass 29, count 0 2006.286.02:28:52.48#ibcon#about to read 6, iclass 29, count 0 2006.286.02:28:52.48#ibcon#read 6, iclass 29, count 0 2006.286.02:28:52.48#ibcon#end of sib2, iclass 29, count 0 2006.286.02:28:52.48#ibcon#*after write, iclass 29, count 0 2006.286.02:28:52.48#ibcon#*before return 0, iclass 29, count 0 2006.286.02:28:52.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:28:52.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:28:52.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.02:28:52.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.02:28:52.48$vck44/vb=2,5 2006.286.02:28:52.48#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.02:28:52.48#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.02:28:52.48#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:52.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:28:52.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:28:52.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:28:52.54#ibcon#enter wrdev, iclass 31, count 2 2006.286.02:28:52.54#ibcon#first serial, iclass 31, count 2 2006.286.02:28:52.54#ibcon#enter sib2, iclass 31, count 2 2006.286.02:28:52.54#ibcon#flushed, iclass 31, count 2 2006.286.02:28:52.54#ibcon#about to write, iclass 31, count 2 2006.286.02:28:52.54#ibcon#wrote, iclass 31, count 2 2006.286.02:28:52.54#ibcon#about to read 3, iclass 31, count 2 2006.286.02:28:52.56#ibcon#read 3, iclass 31, count 2 2006.286.02:28:52.56#ibcon#about to read 4, iclass 31, count 2 2006.286.02:28:52.56#ibcon#read 4, iclass 31, count 2 2006.286.02:28:52.56#ibcon#about to read 5, iclass 31, count 2 2006.286.02:28:52.56#ibcon#read 5, iclass 31, count 2 2006.286.02:28:52.56#ibcon#about to read 6, iclass 31, count 2 2006.286.02:28:52.56#ibcon#read 6, iclass 31, count 2 2006.286.02:28:52.56#ibcon#end of sib2, iclass 31, count 2 2006.286.02:28:52.56#ibcon#*mode == 0, iclass 31, count 2 2006.286.02:28:52.56#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.02:28:52.56#ibcon#[27=AT02-05\r\n] 2006.286.02:28:52.56#ibcon#*before write, iclass 31, count 2 2006.286.02:28:52.56#ibcon#enter sib2, iclass 31, count 2 2006.286.02:28:52.56#ibcon#flushed, iclass 31, count 2 2006.286.02:28:52.56#ibcon#about to write, iclass 31, count 2 2006.286.02:28:52.56#ibcon#wrote, iclass 31, count 2 2006.286.02:28:52.56#ibcon#about to read 3, iclass 31, count 2 2006.286.02:28:52.59#ibcon#read 3, iclass 31, count 2 2006.286.02:28:52.59#ibcon#about to read 4, iclass 31, count 2 2006.286.02:28:52.59#ibcon#read 4, iclass 31, count 2 2006.286.02:28:52.59#ibcon#about to read 5, iclass 31, count 2 2006.286.02:28:52.59#ibcon#read 5, iclass 31, count 2 2006.286.02:28:52.59#ibcon#about to read 6, iclass 31, count 2 2006.286.02:28:52.59#ibcon#read 6, iclass 31, count 2 2006.286.02:28:52.59#ibcon#end of sib2, iclass 31, count 2 2006.286.02:28:52.59#ibcon#*after write, iclass 31, count 2 2006.286.02:28:52.59#ibcon#*before return 0, iclass 31, count 2 2006.286.02:28:52.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:28:52.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:28:52.59#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.02:28:52.59#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:52.59#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:28:52.71#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:28:52.71#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:28:52.71#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:28:52.71#ibcon#first serial, iclass 31, count 0 2006.286.02:28:52.71#ibcon#enter sib2, iclass 31, count 0 2006.286.02:28:52.71#ibcon#flushed, iclass 31, count 0 2006.286.02:28:52.71#ibcon#about to write, iclass 31, count 0 2006.286.02:28:52.71#ibcon#wrote, iclass 31, count 0 2006.286.02:28:52.71#ibcon#about to read 3, iclass 31, count 0 2006.286.02:28:52.73#ibcon#read 3, iclass 31, count 0 2006.286.02:28:52.73#ibcon#about to read 4, iclass 31, count 0 2006.286.02:28:52.73#ibcon#read 4, iclass 31, count 0 2006.286.02:28:52.73#ibcon#about to read 5, iclass 31, count 0 2006.286.02:28:52.73#ibcon#read 5, iclass 31, count 0 2006.286.02:28:52.73#ibcon#about to read 6, iclass 31, count 0 2006.286.02:28:52.73#ibcon#read 6, iclass 31, count 0 2006.286.02:28:52.73#ibcon#end of sib2, iclass 31, count 0 2006.286.02:28:52.73#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:28:52.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:28:52.73#ibcon#[27=USB\r\n] 2006.286.02:28:52.73#ibcon#*before write, iclass 31, count 0 2006.286.02:28:52.73#ibcon#enter sib2, iclass 31, count 0 2006.286.02:28:52.73#ibcon#flushed, iclass 31, count 0 2006.286.02:28:52.73#ibcon#about to write, iclass 31, count 0 2006.286.02:28:52.73#ibcon#wrote, iclass 31, count 0 2006.286.02:28:52.73#ibcon#about to read 3, iclass 31, count 0 2006.286.02:28:52.76#ibcon#read 3, iclass 31, count 0 2006.286.02:28:52.76#ibcon#about to read 4, iclass 31, count 0 2006.286.02:28:52.76#ibcon#read 4, iclass 31, count 0 2006.286.02:28:52.76#ibcon#about to read 5, iclass 31, count 0 2006.286.02:28:52.76#ibcon#read 5, iclass 31, count 0 2006.286.02:28:52.76#ibcon#about to read 6, iclass 31, count 0 2006.286.02:28:52.76#ibcon#read 6, iclass 31, count 0 2006.286.02:28:52.76#ibcon#end of sib2, iclass 31, count 0 2006.286.02:28:52.76#ibcon#*after write, iclass 31, count 0 2006.286.02:28:52.76#ibcon#*before return 0, iclass 31, count 0 2006.286.02:28:52.76#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:28:52.76#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:28:52.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:28:52.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:28:52.76$vck44/vblo=3,649.99 2006.286.02:28:52.76#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.02:28:52.76#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.02:28:52.76#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:52.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:28:52.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:28:52.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:28:52.76#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:28:52.76#ibcon#first serial, iclass 33, count 0 2006.286.02:28:52.76#ibcon#enter sib2, iclass 33, count 0 2006.286.02:28:52.76#ibcon#flushed, iclass 33, count 0 2006.286.02:28:52.76#ibcon#about to write, iclass 33, count 0 2006.286.02:28:52.76#ibcon#wrote, iclass 33, count 0 2006.286.02:28:52.76#ibcon#about to read 3, iclass 33, count 0 2006.286.02:28:52.78#ibcon#read 3, iclass 33, count 0 2006.286.02:28:52.78#ibcon#about to read 4, iclass 33, count 0 2006.286.02:28:52.78#ibcon#read 4, iclass 33, count 0 2006.286.02:28:52.78#ibcon#about to read 5, iclass 33, count 0 2006.286.02:28:52.78#ibcon#read 5, iclass 33, count 0 2006.286.02:28:52.78#ibcon#about to read 6, iclass 33, count 0 2006.286.02:28:52.78#ibcon#read 6, iclass 33, count 0 2006.286.02:28:52.78#ibcon#end of sib2, iclass 33, count 0 2006.286.02:28:52.78#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:28:52.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:28:52.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.02:28:52.78#ibcon#*before write, iclass 33, count 0 2006.286.02:28:52.78#ibcon#enter sib2, iclass 33, count 0 2006.286.02:28:52.78#ibcon#flushed, iclass 33, count 0 2006.286.02:28:52.78#ibcon#about to write, iclass 33, count 0 2006.286.02:28:52.78#ibcon#wrote, iclass 33, count 0 2006.286.02:28:52.78#ibcon#about to read 3, iclass 33, count 0 2006.286.02:28:52.82#ibcon#read 3, iclass 33, count 0 2006.286.02:28:52.82#ibcon#about to read 4, iclass 33, count 0 2006.286.02:28:52.82#ibcon#read 4, iclass 33, count 0 2006.286.02:28:52.82#ibcon#about to read 5, iclass 33, count 0 2006.286.02:28:52.82#ibcon#read 5, iclass 33, count 0 2006.286.02:28:52.82#ibcon#about to read 6, iclass 33, count 0 2006.286.02:28:52.82#ibcon#read 6, iclass 33, count 0 2006.286.02:28:52.82#ibcon#end of sib2, iclass 33, count 0 2006.286.02:28:52.82#ibcon#*after write, iclass 33, count 0 2006.286.02:28:52.82#ibcon#*before return 0, iclass 33, count 0 2006.286.02:28:52.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:28:52.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:28:52.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:28:52.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:28:52.82$vck44/vb=3,4 2006.286.02:28:52.82#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.02:28:52.82#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.02:28:52.82#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:52.82#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:28:52.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:28:52.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:28:52.88#ibcon#enter wrdev, iclass 35, count 2 2006.286.02:28:52.88#ibcon#first serial, iclass 35, count 2 2006.286.02:28:52.88#ibcon#enter sib2, iclass 35, count 2 2006.286.02:28:52.88#ibcon#flushed, iclass 35, count 2 2006.286.02:28:52.88#ibcon#about to write, iclass 35, count 2 2006.286.02:28:52.88#ibcon#wrote, iclass 35, count 2 2006.286.02:28:52.88#ibcon#about to read 3, iclass 35, count 2 2006.286.02:28:52.90#ibcon#read 3, iclass 35, count 2 2006.286.02:28:52.90#ibcon#about to read 4, iclass 35, count 2 2006.286.02:28:52.90#ibcon#read 4, iclass 35, count 2 2006.286.02:28:52.90#ibcon#about to read 5, iclass 35, count 2 2006.286.02:28:52.90#ibcon#read 5, iclass 35, count 2 2006.286.02:28:52.90#ibcon#about to read 6, iclass 35, count 2 2006.286.02:28:52.90#ibcon#read 6, iclass 35, count 2 2006.286.02:28:52.90#ibcon#end of sib2, iclass 35, count 2 2006.286.02:28:52.90#ibcon#*mode == 0, iclass 35, count 2 2006.286.02:28:52.90#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.02:28:52.90#ibcon#[27=AT03-04\r\n] 2006.286.02:28:52.90#ibcon#*before write, iclass 35, count 2 2006.286.02:28:52.90#ibcon#enter sib2, iclass 35, count 2 2006.286.02:28:52.90#ibcon#flushed, iclass 35, count 2 2006.286.02:28:52.90#ibcon#about to write, iclass 35, count 2 2006.286.02:28:52.90#ibcon#wrote, iclass 35, count 2 2006.286.02:28:52.90#ibcon#about to read 3, iclass 35, count 2 2006.286.02:28:52.93#ibcon#read 3, iclass 35, count 2 2006.286.02:28:52.93#ibcon#about to read 4, iclass 35, count 2 2006.286.02:28:52.93#ibcon#read 4, iclass 35, count 2 2006.286.02:28:52.93#ibcon#about to read 5, iclass 35, count 2 2006.286.02:28:52.93#ibcon#read 5, iclass 35, count 2 2006.286.02:28:52.93#ibcon#about to read 6, iclass 35, count 2 2006.286.02:28:52.93#ibcon#read 6, iclass 35, count 2 2006.286.02:28:52.93#ibcon#end of sib2, iclass 35, count 2 2006.286.02:28:52.93#ibcon#*after write, iclass 35, count 2 2006.286.02:28:52.93#ibcon#*before return 0, iclass 35, count 2 2006.286.02:28:52.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:28:52.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:28:52.93#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.02:28:52.93#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:52.93#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:28:53.01#abcon#<5=/04 2.6 5.5 21.39 811015.9\r\n> 2006.286.02:28:53.03#abcon#{5=INTERFACE CLEAR} 2006.286.02:28:53.05#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:28:53.05#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:28:53.05#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:28:53.05#ibcon#first serial, iclass 35, count 0 2006.286.02:28:53.05#ibcon#enter sib2, iclass 35, count 0 2006.286.02:28:53.05#ibcon#flushed, iclass 35, count 0 2006.286.02:28:53.05#ibcon#about to write, iclass 35, count 0 2006.286.02:28:53.05#ibcon#wrote, iclass 35, count 0 2006.286.02:28:53.05#ibcon#about to read 3, iclass 35, count 0 2006.286.02:28:53.07#ibcon#read 3, iclass 35, count 0 2006.286.02:28:53.07#ibcon#about to read 4, iclass 35, count 0 2006.286.02:28:53.07#ibcon#read 4, iclass 35, count 0 2006.286.02:28:53.07#ibcon#about to read 5, iclass 35, count 0 2006.286.02:28:53.07#ibcon#read 5, iclass 35, count 0 2006.286.02:28:53.07#ibcon#about to read 6, iclass 35, count 0 2006.286.02:28:53.07#ibcon#read 6, iclass 35, count 0 2006.286.02:28:53.07#ibcon#end of sib2, iclass 35, count 0 2006.286.02:28:53.07#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:28:53.07#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:28:53.07#ibcon#[27=USB\r\n] 2006.286.02:28:53.07#ibcon#*before write, iclass 35, count 0 2006.286.02:28:53.07#ibcon#enter sib2, iclass 35, count 0 2006.286.02:28:53.07#ibcon#flushed, iclass 35, count 0 2006.286.02:28:53.07#ibcon#about to write, iclass 35, count 0 2006.286.02:28:53.07#ibcon#wrote, iclass 35, count 0 2006.286.02:28:53.07#ibcon#about to read 3, iclass 35, count 0 2006.286.02:28:53.09#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:28:53.10#ibcon#read 3, iclass 35, count 0 2006.286.02:28:53.10#ibcon#about to read 4, iclass 35, count 0 2006.286.02:28:53.10#ibcon#read 4, iclass 35, count 0 2006.286.02:28:53.10#ibcon#about to read 5, iclass 35, count 0 2006.286.02:28:53.10#ibcon#read 5, iclass 35, count 0 2006.286.02:28:53.10#ibcon#about to read 6, iclass 35, count 0 2006.286.02:28:53.10#ibcon#read 6, iclass 35, count 0 2006.286.02:28:53.10#ibcon#end of sib2, iclass 35, count 0 2006.286.02:28:53.10#ibcon#*after write, iclass 35, count 0 2006.286.02:28:53.10#ibcon#*before return 0, iclass 35, count 0 2006.286.02:28:53.10#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:28:53.10#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:28:53.10#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:28:53.10#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:28:53.10$vck44/vblo=4,679.99 2006.286.02:28:53.10#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.02:28:53.10#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.02:28:53.10#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:53.10#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:28:53.10#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:28:53.10#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:28:53.10#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:28:53.10#ibcon#first serial, iclass 3, count 0 2006.286.02:28:53.10#ibcon#enter sib2, iclass 3, count 0 2006.286.02:28:53.10#ibcon#flushed, iclass 3, count 0 2006.286.02:28:53.10#ibcon#about to write, iclass 3, count 0 2006.286.02:28:53.10#ibcon#wrote, iclass 3, count 0 2006.286.02:28:53.10#ibcon#about to read 3, iclass 3, count 0 2006.286.02:28:53.12#ibcon#read 3, iclass 3, count 0 2006.286.02:28:53.12#ibcon#about to read 4, iclass 3, count 0 2006.286.02:28:53.12#ibcon#read 4, iclass 3, count 0 2006.286.02:28:53.12#ibcon#about to read 5, iclass 3, count 0 2006.286.02:28:53.12#ibcon#read 5, iclass 3, count 0 2006.286.02:28:53.12#ibcon#about to read 6, iclass 3, count 0 2006.286.02:28:53.12#ibcon#read 6, iclass 3, count 0 2006.286.02:28:53.12#ibcon#end of sib2, iclass 3, count 0 2006.286.02:28:53.12#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:28:53.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:28:53.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.02:28:53.12#ibcon#*before write, iclass 3, count 0 2006.286.02:28:53.12#ibcon#enter sib2, iclass 3, count 0 2006.286.02:28:53.12#ibcon#flushed, iclass 3, count 0 2006.286.02:28:53.12#ibcon#about to write, iclass 3, count 0 2006.286.02:28:53.12#ibcon#wrote, iclass 3, count 0 2006.286.02:28:53.12#ibcon#about to read 3, iclass 3, count 0 2006.286.02:28:53.16#ibcon#read 3, iclass 3, count 0 2006.286.02:28:53.16#ibcon#about to read 4, iclass 3, count 0 2006.286.02:28:53.16#ibcon#read 4, iclass 3, count 0 2006.286.02:28:53.16#ibcon#about to read 5, iclass 3, count 0 2006.286.02:28:53.16#ibcon#read 5, iclass 3, count 0 2006.286.02:28:53.16#ibcon#about to read 6, iclass 3, count 0 2006.286.02:28:53.16#ibcon#read 6, iclass 3, count 0 2006.286.02:28:53.16#ibcon#end of sib2, iclass 3, count 0 2006.286.02:28:53.16#ibcon#*after write, iclass 3, count 0 2006.286.02:28:53.16#ibcon#*before return 0, iclass 3, count 0 2006.286.02:28:53.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:28:53.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:28:53.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:28:53.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:28:53.16$vck44/vb=4,5 2006.286.02:28:53.16#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.02:28:53.16#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.02:28:53.16#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:53.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:28:53.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:28:53.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:28:53.22#ibcon#enter wrdev, iclass 5, count 2 2006.286.02:28:53.22#ibcon#first serial, iclass 5, count 2 2006.286.02:28:53.22#ibcon#enter sib2, iclass 5, count 2 2006.286.02:28:53.22#ibcon#flushed, iclass 5, count 2 2006.286.02:28:53.22#ibcon#about to write, iclass 5, count 2 2006.286.02:28:53.22#ibcon#wrote, iclass 5, count 2 2006.286.02:28:53.22#ibcon#about to read 3, iclass 5, count 2 2006.286.02:28:53.24#ibcon#read 3, iclass 5, count 2 2006.286.02:28:53.24#ibcon#about to read 4, iclass 5, count 2 2006.286.02:28:53.24#ibcon#read 4, iclass 5, count 2 2006.286.02:28:53.24#ibcon#about to read 5, iclass 5, count 2 2006.286.02:28:53.24#ibcon#read 5, iclass 5, count 2 2006.286.02:28:53.24#ibcon#about to read 6, iclass 5, count 2 2006.286.02:28:53.24#ibcon#read 6, iclass 5, count 2 2006.286.02:28:53.24#ibcon#end of sib2, iclass 5, count 2 2006.286.02:28:53.24#ibcon#*mode == 0, iclass 5, count 2 2006.286.02:28:53.24#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.02:28:53.24#ibcon#[27=AT04-05\r\n] 2006.286.02:28:53.24#ibcon#*before write, iclass 5, count 2 2006.286.02:28:53.24#ibcon#enter sib2, iclass 5, count 2 2006.286.02:28:53.24#ibcon#flushed, iclass 5, count 2 2006.286.02:28:53.24#ibcon#about to write, iclass 5, count 2 2006.286.02:28:53.24#ibcon#wrote, iclass 5, count 2 2006.286.02:28:53.24#ibcon#about to read 3, iclass 5, count 2 2006.286.02:28:53.27#ibcon#read 3, iclass 5, count 2 2006.286.02:28:53.27#ibcon#about to read 4, iclass 5, count 2 2006.286.02:28:53.27#ibcon#read 4, iclass 5, count 2 2006.286.02:28:53.27#ibcon#about to read 5, iclass 5, count 2 2006.286.02:28:53.27#ibcon#read 5, iclass 5, count 2 2006.286.02:28:53.27#ibcon#about to read 6, iclass 5, count 2 2006.286.02:28:53.27#ibcon#read 6, iclass 5, count 2 2006.286.02:28:53.27#ibcon#end of sib2, iclass 5, count 2 2006.286.02:28:53.27#ibcon#*after write, iclass 5, count 2 2006.286.02:28:53.27#ibcon#*before return 0, iclass 5, count 2 2006.286.02:28:53.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:28:53.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:28:53.27#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.02:28:53.27#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:53.27#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:28:53.39#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:28:53.39#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:28:53.39#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:28:53.39#ibcon#first serial, iclass 5, count 0 2006.286.02:28:53.39#ibcon#enter sib2, iclass 5, count 0 2006.286.02:28:53.39#ibcon#flushed, iclass 5, count 0 2006.286.02:28:53.39#ibcon#about to write, iclass 5, count 0 2006.286.02:28:53.39#ibcon#wrote, iclass 5, count 0 2006.286.02:28:53.39#ibcon#about to read 3, iclass 5, count 0 2006.286.02:28:53.41#ibcon#read 3, iclass 5, count 0 2006.286.02:28:53.41#ibcon#about to read 4, iclass 5, count 0 2006.286.02:28:53.41#ibcon#read 4, iclass 5, count 0 2006.286.02:28:53.41#ibcon#about to read 5, iclass 5, count 0 2006.286.02:28:53.41#ibcon#read 5, iclass 5, count 0 2006.286.02:28:53.41#ibcon#about to read 6, iclass 5, count 0 2006.286.02:28:53.41#ibcon#read 6, iclass 5, count 0 2006.286.02:28:53.41#ibcon#end of sib2, iclass 5, count 0 2006.286.02:28:53.41#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:28:53.41#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:28:53.41#ibcon#[27=USB\r\n] 2006.286.02:28:53.41#ibcon#*before write, iclass 5, count 0 2006.286.02:28:53.41#ibcon#enter sib2, iclass 5, count 0 2006.286.02:28:53.41#ibcon#flushed, iclass 5, count 0 2006.286.02:28:53.41#ibcon#about to write, iclass 5, count 0 2006.286.02:28:53.41#ibcon#wrote, iclass 5, count 0 2006.286.02:28:53.41#ibcon#about to read 3, iclass 5, count 0 2006.286.02:28:53.44#ibcon#read 3, iclass 5, count 0 2006.286.02:28:53.44#ibcon#about to read 4, iclass 5, count 0 2006.286.02:28:53.44#ibcon#read 4, iclass 5, count 0 2006.286.02:28:53.44#ibcon#about to read 5, iclass 5, count 0 2006.286.02:28:53.44#ibcon#read 5, iclass 5, count 0 2006.286.02:28:53.44#ibcon#about to read 6, iclass 5, count 0 2006.286.02:28:53.44#ibcon#read 6, iclass 5, count 0 2006.286.02:28:53.44#ibcon#end of sib2, iclass 5, count 0 2006.286.02:28:53.44#ibcon#*after write, iclass 5, count 0 2006.286.02:28:53.44#ibcon#*before return 0, iclass 5, count 0 2006.286.02:28:53.44#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:28:53.44#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:28:53.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:28:53.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:28:53.44$vck44/vblo=5,709.99 2006.286.02:28:53.44#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.02:28:53.44#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.02:28:53.44#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:53.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:28:53.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:28:53.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:28:53.44#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:28:53.44#ibcon#first serial, iclass 7, count 0 2006.286.02:28:53.44#ibcon#enter sib2, iclass 7, count 0 2006.286.02:28:53.44#ibcon#flushed, iclass 7, count 0 2006.286.02:28:53.44#ibcon#about to write, iclass 7, count 0 2006.286.02:28:53.44#ibcon#wrote, iclass 7, count 0 2006.286.02:28:53.44#ibcon#about to read 3, iclass 7, count 0 2006.286.02:28:53.46#ibcon#read 3, iclass 7, count 0 2006.286.02:28:53.46#ibcon#about to read 4, iclass 7, count 0 2006.286.02:28:53.46#ibcon#read 4, iclass 7, count 0 2006.286.02:28:53.46#ibcon#about to read 5, iclass 7, count 0 2006.286.02:28:53.46#ibcon#read 5, iclass 7, count 0 2006.286.02:28:53.46#ibcon#about to read 6, iclass 7, count 0 2006.286.02:28:53.46#ibcon#read 6, iclass 7, count 0 2006.286.02:28:53.46#ibcon#end of sib2, iclass 7, count 0 2006.286.02:28:53.46#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:28:53.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:28:53.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.02:28:53.46#ibcon#*before write, iclass 7, count 0 2006.286.02:28:53.46#ibcon#enter sib2, iclass 7, count 0 2006.286.02:28:53.46#ibcon#flushed, iclass 7, count 0 2006.286.02:28:53.46#ibcon#about to write, iclass 7, count 0 2006.286.02:28:53.46#ibcon#wrote, iclass 7, count 0 2006.286.02:28:53.46#ibcon#about to read 3, iclass 7, count 0 2006.286.02:28:53.50#ibcon#read 3, iclass 7, count 0 2006.286.02:28:53.50#ibcon#about to read 4, iclass 7, count 0 2006.286.02:28:53.50#ibcon#read 4, iclass 7, count 0 2006.286.02:28:53.50#ibcon#about to read 5, iclass 7, count 0 2006.286.02:28:53.50#ibcon#read 5, iclass 7, count 0 2006.286.02:28:53.50#ibcon#about to read 6, iclass 7, count 0 2006.286.02:28:53.50#ibcon#read 6, iclass 7, count 0 2006.286.02:28:53.50#ibcon#end of sib2, iclass 7, count 0 2006.286.02:28:53.50#ibcon#*after write, iclass 7, count 0 2006.286.02:28:53.50#ibcon#*before return 0, iclass 7, count 0 2006.286.02:28:53.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:28:53.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:28:53.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:28:53.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:28:53.50$vck44/vb=5,4 2006.286.02:28:53.50#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.02:28:53.50#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.02:28:53.50#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:53.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:28:53.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:28:53.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:28:53.56#ibcon#enter wrdev, iclass 11, count 2 2006.286.02:28:53.56#ibcon#first serial, iclass 11, count 2 2006.286.02:28:53.56#ibcon#enter sib2, iclass 11, count 2 2006.286.02:28:53.56#ibcon#flushed, iclass 11, count 2 2006.286.02:28:53.56#ibcon#about to write, iclass 11, count 2 2006.286.02:28:53.56#ibcon#wrote, iclass 11, count 2 2006.286.02:28:53.56#ibcon#about to read 3, iclass 11, count 2 2006.286.02:28:53.58#ibcon#read 3, iclass 11, count 2 2006.286.02:28:53.58#ibcon#about to read 4, iclass 11, count 2 2006.286.02:28:53.58#ibcon#read 4, iclass 11, count 2 2006.286.02:28:53.58#ibcon#about to read 5, iclass 11, count 2 2006.286.02:28:53.58#ibcon#read 5, iclass 11, count 2 2006.286.02:28:53.58#ibcon#about to read 6, iclass 11, count 2 2006.286.02:28:53.58#ibcon#read 6, iclass 11, count 2 2006.286.02:28:53.58#ibcon#end of sib2, iclass 11, count 2 2006.286.02:28:53.58#ibcon#*mode == 0, iclass 11, count 2 2006.286.02:28:53.58#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.02:28:53.58#ibcon#[27=AT05-04\r\n] 2006.286.02:28:53.58#ibcon#*before write, iclass 11, count 2 2006.286.02:28:53.58#ibcon#enter sib2, iclass 11, count 2 2006.286.02:28:53.58#ibcon#flushed, iclass 11, count 2 2006.286.02:28:53.58#ibcon#about to write, iclass 11, count 2 2006.286.02:28:53.58#ibcon#wrote, iclass 11, count 2 2006.286.02:28:53.58#ibcon#about to read 3, iclass 11, count 2 2006.286.02:28:53.61#ibcon#read 3, iclass 11, count 2 2006.286.02:28:53.61#ibcon#about to read 4, iclass 11, count 2 2006.286.02:28:53.61#ibcon#read 4, iclass 11, count 2 2006.286.02:28:53.61#ibcon#about to read 5, iclass 11, count 2 2006.286.02:28:53.61#ibcon#read 5, iclass 11, count 2 2006.286.02:28:53.61#ibcon#about to read 6, iclass 11, count 2 2006.286.02:28:53.61#ibcon#read 6, iclass 11, count 2 2006.286.02:28:53.61#ibcon#end of sib2, iclass 11, count 2 2006.286.02:28:53.61#ibcon#*after write, iclass 11, count 2 2006.286.02:28:53.61#ibcon#*before return 0, iclass 11, count 2 2006.286.02:28:53.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:28:53.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:28:53.61#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.02:28:53.61#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:53.61#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:28:53.73#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:28:53.73#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:28:53.73#ibcon#enter wrdev, iclass 11, count 0 2006.286.02:28:53.73#ibcon#first serial, iclass 11, count 0 2006.286.02:28:53.73#ibcon#enter sib2, iclass 11, count 0 2006.286.02:28:53.73#ibcon#flushed, iclass 11, count 0 2006.286.02:28:53.73#ibcon#about to write, iclass 11, count 0 2006.286.02:28:53.73#ibcon#wrote, iclass 11, count 0 2006.286.02:28:53.73#ibcon#about to read 3, iclass 11, count 0 2006.286.02:28:53.75#ibcon#read 3, iclass 11, count 0 2006.286.02:28:53.75#ibcon#about to read 4, iclass 11, count 0 2006.286.02:28:53.75#ibcon#read 4, iclass 11, count 0 2006.286.02:28:53.75#ibcon#about to read 5, iclass 11, count 0 2006.286.02:28:53.75#ibcon#read 5, iclass 11, count 0 2006.286.02:28:53.75#ibcon#about to read 6, iclass 11, count 0 2006.286.02:28:53.75#ibcon#read 6, iclass 11, count 0 2006.286.02:28:53.75#ibcon#end of sib2, iclass 11, count 0 2006.286.02:28:53.75#ibcon#*mode == 0, iclass 11, count 0 2006.286.02:28:53.75#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.02:28:53.75#ibcon#[27=USB\r\n] 2006.286.02:28:53.75#ibcon#*before write, iclass 11, count 0 2006.286.02:28:53.75#ibcon#enter sib2, iclass 11, count 0 2006.286.02:28:53.75#ibcon#flushed, iclass 11, count 0 2006.286.02:28:53.75#ibcon#about to write, iclass 11, count 0 2006.286.02:28:53.75#ibcon#wrote, iclass 11, count 0 2006.286.02:28:53.75#ibcon#about to read 3, iclass 11, count 0 2006.286.02:28:53.78#ibcon#read 3, iclass 11, count 0 2006.286.02:28:53.78#ibcon#about to read 4, iclass 11, count 0 2006.286.02:28:53.78#ibcon#read 4, iclass 11, count 0 2006.286.02:28:53.78#ibcon#about to read 5, iclass 11, count 0 2006.286.02:28:53.78#ibcon#read 5, iclass 11, count 0 2006.286.02:28:53.78#ibcon#about to read 6, iclass 11, count 0 2006.286.02:28:53.78#ibcon#read 6, iclass 11, count 0 2006.286.02:28:53.78#ibcon#end of sib2, iclass 11, count 0 2006.286.02:28:53.78#ibcon#*after write, iclass 11, count 0 2006.286.02:28:53.78#ibcon#*before return 0, iclass 11, count 0 2006.286.02:28:53.78#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:28:53.78#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:28:53.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.02:28:53.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.02:28:53.78$vck44/vblo=6,719.99 2006.286.02:28:53.78#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.02:28:53.78#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.02:28:53.78#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:53.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:28:53.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:28:53.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:28:53.78#ibcon#enter wrdev, iclass 13, count 0 2006.286.02:28:53.78#ibcon#first serial, iclass 13, count 0 2006.286.02:28:53.78#ibcon#enter sib2, iclass 13, count 0 2006.286.02:28:53.78#ibcon#flushed, iclass 13, count 0 2006.286.02:28:53.78#ibcon#about to write, iclass 13, count 0 2006.286.02:28:53.78#ibcon#wrote, iclass 13, count 0 2006.286.02:28:53.78#ibcon#about to read 3, iclass 13, count 0 2006.286.02:28:53.80#ibcon#read 3, iclass 13, count 0 2006.286.02:28:53.80#ibcon#about to read 4, iclass 13, count 0 2006.286.02:28:53.80#ibcon#read 4, iclass 13, count 0 2006.286.02:28:53.80#ibcon#about to read 5, iclass 13, count 0 2006.286.02:28:53.80#ibcon#read 5, iclass 13, count 0 2006.286.02:28:53.80#ibcon#about to read 6, iclass 13, count 0 2006.286.02:28:53.80#ibcon#read 6, iclass 13, count 0 2006.286.02:28:53.80#ibcon#end of sib2, iclass 13, count 0 2006.286.02:28:53.80#ibcon#*mode == 0, iclass 13, count 0 2006.286.02:28:53.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.02:28:53.80#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.02:28:53.80#ibcon#*before write, iclass 13, count 0 2006.286.02:28:53.80#ibcon#enter sib2, iclass 13, count 0 2006.286.02:28:53.80#ibcon#flushed, iclass 13, count 0 2006.286.02:28:53.80#ibcon#about to write, iclass 13, count 0 2006.286.02:28:53.80#ibcon#wrote, iclass 13, count 0 2006.286.02:28:53.80#ibcon#about to read 3, iclass 13, count 0 2006.286.02:28:53.84#ibcon#read 3, iclass 13, count 0 2006.286.02:28:53.84#ibcon#about to read 4, iclass 13, count 0 2006.286.02:28:53.84#ibcon#read 4, iclass 13, count 0 2006.286.02:28:53.84#ibcon#about to read 5, iclass 13, count 0 2006.286.02:28:53.84#ibcon#read 5, iclass 13, count 0 2006.286.02:28:53.84#ibcon#about to read 6, iclass 13, count 0 2006.286.02:28:53.84#ibcon#read 6, iclass 13, count 0 2006.286.02:28:53.84#ibcon#end of sib2, iclass 13, count 0 2006.286.02:28:53.84#ibcon#*after write, iclass 13, count 0 2006.286.02:28:53.84#ibcon#*before return 0, iclass 13, count 0 2006.286.02:28:53.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:28:53.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:28:53.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.02:28:53.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.02:28:53.84$vck44/vb=6,3 2006.286.02:28:53.84#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.02:28:53.84#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.02:28:53.84#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:53.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:28:53.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:28:53.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:28:53.90#ibcon#enter wrdev, iclass 15, count 2 2006.286.02:28:53.90#ibcon#first serial, iclass 15, count 2 2006.286.02:28:53.90#ibcon#enter sib2, iclass 15, count 2 2006.286.02:28:53.90#ibcon#flushed, iclass 15, count 2 2006.286.02:28:53.90#ibcon#about to write, iclass 15, count 2 2006.286.02:28:53.90#ibcon#wrote, iclass 15, count 2 2006.286.02:28:53.90#ibcon#about to read 3, iclass 15, count 2 2006.286.02:28:53.92#ibcon#read 3, iclass 15, count 2 2006.286.02:28:53.92#ibcon#about to read 4, iclass 15, count 2 2006.286.02:28:53.92#ibcon#read 4, iclass 15, count 2 2006.286.02:28:53.92#ibcon#about to read 5, iclass 15, count 2 2006.286.02:28:53.92#ibcon#read 5, iclass 15, count 2 2006.286.02:28:53.92#ibcon#about to read 6, iclass 15, count 2 2006.286.02:28:53.92#ibcon#read 6, iclass 15, count 2 2006.286.02:28:53.92#ibcon#end of sib2, iclass 15, count 2 2006.286.02:28:53.92#ibcon#*mode == 0, iclass 15, count 2 2006.286.02:28:53.92#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.02:28:53.92#ibcon#[27=AT06-03\r\n] 2006.286.02:28:53.92#ibcon#*before write, iclass 15, count 2 2006.286.02:28:53.92#ibcon#enter sib2, iclass 15, count 2 2006.286.02:28:53.92#ibcon#flushed, iclass 15, count 2 2006.286.02:28:53.92#ibcon#about to write, iclass 15, count 2 2006.286.02:28:53.92#ibcon#wrote, iclass 15, count 2 2006.286.02:28:53.92#ibcon#about to read 3, iclass 15, count 2 2006.286.02:28:53.95#ibcon#read 3, iclass 15, count 2 2006.286.02:28:53.95#ibcon#about to read 4, iclass 15, count 2 2006.286.02:28:53.95#ibcon#read 4, iclass 15, count 2 2006.286.02:28:53.95#ibcon#about to read 5, iclass 15, count 2 2006.286.02:28:53.95#ibcon#read 5, iclass 15, count 2 2006.286.02:28:53.95#ibcon#about to read 6, iclass 15, count 2 2006.286.02:28:53.95#ibcon#read 6, iclass 15, count 2 2006.286.02:28:53.95#ibcon#end of sib2, iclass 15, count 2 2006.286.02:28:53.95#ibcon#*after write, iclass 15, count 2 2006.286.02:28:53.95#ibcon#*before return 0, iclass 15, count 2 2006.286.02:28:53.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:28:53.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:28:53.95#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.02:28:53.95#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:53.95#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:28:54.07#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:28:54.07#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:28:54.07#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:28:54.07#ibcon#first serial, iclass 15, count 0 2006.286.02:28:54.07#ibcon#enter sib2, iclass 15, count 0 2006.286.02:28:54.07#ibcon#flushed, iclass 15, count 0 2006.286.02:28:54.07#ibcon#about to write, iclass 15, count 0 2006.286.02:28:54.07#ibcon#wrote, iclass 15, count 0 2006.286.02:28:54.07#ibcon#about to read 3, iclass 15, count 0 2006.286.02:28:54.09#ibcon#read 3, iclass 15, count 0 2006.286.02:28:54.09#ibcon#about to read 4, iclass 15, count 0 2006.286.02:28:54.09#ibcon#read 4, iclass 15, count 0 2006.286.02:28:54.09#ibcon#about to read 5, iclass 15, count 0 2006.286.02:28:54.09#ibcon#read 5, iclass 15, count 0 2006.286.02:28:54.09#ibcon#about to read 6, iclass 15, count 0 2006.286.02:28:54.09#ibcon#read 6, iclass 15, count 0 2006.286.02:28:54.09#ibcon#end of sib2, iclass 15, count 0 2006.286.02:28:54.09#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:28:54.09#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:28:54.09#ibcon#[27=USB\r\n] 2006.286.02:28:54.09#ibcon#*before write, iclass 15, count 0 2006.286.02:28:54.09#ibcon#enter sib2, iclass 15, count 0 2006.286.02:28:54.09#ibcon#flushed, iclass 15, count 0 2006.286.02:28:54.09#ibcon#about to write, iclass 15, count 0 2006.286.02:28:54.09#ibcon#wrote, iclass 15, count 0 2006.286.02:28:54.09#ibcon#about to read 3, iclass 15, count 0 2006.286.02:28:54.12#ibcon#read 3, iclass 15, count 0 2006.286.02:28:54.12#ibcon#about to read 4, iclass 15, count 0 2006.286.02:28:54.12#ibcon#read 4, iclass 15, count 0 2006.286.02:28:54.12#ibcon#about to read 5, iclass 15, count 0 2006.286.02:28:54.12#ibcon#read 5, iclass 15, count 0 2006.286.02:28:54.12#ibcon#about to read 6, iclass 15, count 0 2006.286.02:28:54.12#ibcon#read 6, iclass 15, count 0 2006.286.02:28:54.12#ibcon#end of sib2, iclass 15, count 0 2006.286.02:28:54.12#ibcon#*after write, iclass 15, count 0 2006.286.02:28:54.12#ibcon#*before return 0, iclass 15, count 0 2006.286.02:28:54.12#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:28:54.12#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:28:54.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:28:54.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:28:54.12$vck44/vblo=7,734.99 2006.286.02:28:54.12#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.02:28:54.12#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.02:28:54.12#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:54.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:28:54.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:28:54.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:28:54.12#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:28:54.12#ibcon#first serial, iclass 17, count 0 2006.286.02:28:54.12#ibcon#enter sib2, iclass 17, count 0 2006.286.02:28:54.12#ibcon#flushed, iclass 17, count 0 2006.286.02:28:54.12#ibcon#about to write, iclass 17, count 0 2006.286.02:28:54.12#ibcon#wrote, iclass 17, count 0 2006.286.02:28:54.12#ibcon#about to read 3, iclass 17, count 0 2006.286.02:28:54.14#ibcon#read 3, iclass 17, count 0 2006.286.02:28:54.14#ibcon#about to read 4, iclass 17, count 0 2006.286.02:28:54.14#ibcon#read 4, iclass 17, count 0 2006.286.02:28:54.14#ibcon#about to read 5, iclass 17, count 0 2006.286.02:28:54.14#ibcon#read 5, iclass 17, count 0 2006.286.02:28:54.14#ibcon#about to read 6, iclass 17, count 0 2006.286.02:28:54.14#ibcon#read 6, iclass 17, count 0 2006.286.02:28:54.14#ibcon#end of sib2, iclass 17, count 0 2006.286.02:28:54.14#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:28:54.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:28:54.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.02:28:54.14#ibcon#*before write, iclass 17, count 0 2006.286.02:28:54.14#ibcon#enter sib2, iclass 17, count 0 2006.286.02:28:54.14#ibcon#flushed, iclass 17, count 0 2006.286.02:28:54.14#ibcon#about to write, iclass 17, count 0 2006.286.02:28:54.14#ibcon#wrote, iclass 17, count 0 2006.286.02:28:54.14#ibcon#about to read 3, iclass 17, count 0 2006.286.02:28:54.18#ibcon#read 3, iclass 17, count 0 2006.286.02:28:54.18#ibcon#about to read 4, iclass 17, count 0 2006.286.02:28:54.18#ibcon#read 4, iclass 17, count 0 2006.286.02:28:54.18#ibcon#about to read 5, iclass 17, count 0 2006.286.02:28:54.18#ibcon#read 5, iclass 17, count 0 2006.286.02:28:54.18#ibcon#about to read 6, iclass 17, count 0 2006.286.02:28:54.18#ibcon#read 6, iclass 17, count 0 2006.286.02:28:54.18#ibcon#end of sib2, iclass 17, count 0 2006.286.02:28:54.18#ibcon#*after write, iclass 17, count 0 2006.286.02:28:54.18#ibcon#*before return 0, iclass 17, count 0 2006.286.02:28:54.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:28:54.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:28:54.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:28:54.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:28:54.18$vck44/vb=7,4 2006.286.02:28:54.18#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.02:28:54.18#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.02:28:54.18#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:54.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:28:54.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:28:54.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:28:54.24#ibcon#enter wrdev, iclass 19, count 2 2006.286.02:28:54.24#ibcon#first serial, iclass 19, count 2 2006.286.02:28:54.24#ibcon#enter sib2, iclass 19, count 2 2006.286.02:28:54.24#ibcon#flushed, iclass 19, count 2 2006.286.02:28:54.24#ibcon#about to write, iclass 19, count 2 2006.286.02:28:54.24#ibcon#wrote, iclass 19, count 2 2006.286.02:28:54.24#ibcon#about to read 3, iclass 19, count 2 2006.286.02:28:54.26#ibcon#read 3, iclass 19, count 2 2006.286.02:28:54.26#ibcon#about to read 4, iclass 19, count 2 2006.286.02:28:54.26#ibcon#read 4, iclass 19, count 2 2006.286.02:28:54.26#ibcon#about to read 5, iclass 19, count 2 2006.286.02:28:54.26#ibcon#read 5, iclass 19, count 2 2006.286.02:28:54.26#ibcon#about to read 6, iclass 19, count 2 2006.286.02:28:54.26#ibcon#read 6, iclass 19, count 2 2006.286.02:28:54.26#ibcon#end of sib2, iclass 19, count 2 2006.286.02:28:54.26#ibcon#*mode == 0, iclass 19, count 2 2006.286.02:28:54.26#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.02:28:54.26#ibcon#[27=AT07-04\r\n] 2006.286.02:28:54.26#ibcon#*before write, iclass 19, count 2 2006.286.02:28:54.26#ibcon#enter sib2, iclass 19, count 2 2006.286.02:28:54.26#ibcon#flushed, iclass 19, count 2 2006.286.02:28:54.26#ibcon#about to write, iclass 19, count 2 2006.286.02:28:54.26#ibcon#wrote, iclass 19, count 2 2006.286.02:28:54.26#ibcon#about to read 3, iclass 19, count 2 2006.286.02:28:54.29#ibcon#read 3, iclass 19, count 2 2006.286.02:28:54.29#ibcon#about to read 4, iclass 19, count 2 2006.286.02:28:54.29#ibcon#read 4, iclass 19, count 2 2006.286.02:28:54.29#ibcon#about to read 5, iclass 19, count 2 2006.286.02:28:54.29#ibcon#read 5, iclass 19, count 2 2006.286.02:28:54.29#ibcon#about to read 6, iclass 19, count 2 2006.286.02:28:54.29#ibcon#read 6, iclass 19, count 2 2006.286.02:28:54.29#ibcon#end of sib2, iclass 19, count 2 2006.286.02:28:54.29#ibcon#*after write, iclass 19, count 2 2006.286.02:28:54.29#ibcon#*before return 0, iclass 19, count 2 2006.286.02:28:54.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:28:54.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:28:54.29#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.02:28:54.29#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:54.29#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:28:54.41#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:28:54.41#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:28:54.41#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:28:54.41#ibcon#first serial, iclass 19, count 0 2006.286.02:28:54.41#ibcon#enter sib2, iclass 19, count 0 2006.286.02:28:54.41#ibcon#flushed, iclass 19, count 0 2006.286.02:28:54.41#ibcon#about to write, iclass 19, count 0 2006.286.02:28:54.41#ibcon#wrote, iclass 19, count 0 2006.286.02:28:54.41#ibcon#about to read 3, iclass 19, count 0 2006.286.02:28:54.43#ibcon#read 3, iclass 19, count 0 2006.286.02:28:54.43#ibcon#about to read 4, iclass 19, count 0 2006.286.02:28:54.43#ibcon#read 4, iclass 19, count 0 2006.286.02:28:54.43#ibcon#about to read 5, iclass 19, count 0 2006.286.02:28:54.43#ibcon#read 5, iclass 19, count 0 2006.286.02:28:54.43#ibcon#about to read 6, iclass 19, count 0 2006.286.02:28:54.43#ibcon#read 6, iclass 19, count 0 2006.286.02:28:54.43#ibcon#end of sib2, iclass 19, count 0 2006.286.02:28:54.43#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:28:54.43#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:28:54.43#ibcon#[27=USB\r\n] 2006.286.02:28:54.43#ibcon#*before write, iclass 19, count 0 2006.286.02:28:54.43#ibcon#enter sib2, iclass 19, count 0 2006.286.02:28:54.43#ibcon#flushed, iclass 19, count 0 2006.286.02:28:54.43#ibcon#about to write, iclass 19, count 0 2006.286.02:28:54.43#ibcon#wrote, iclass 19, count 0 2006.286.02:28:54.43#ibcon#about to read 3, iclass 19, count 0 2006.286.02:28:54.46#ibcon#read 3, iclass 19, count 0 2006.286.02:28:54.46#ibcon#about to read 4, iclass 19, count 0 2006.286.02:28:54.46#ibcon#read 4, iclass 19, count 0 2006.286.02:28:54.46#ibcon#about to read 5, iclass 19, count 0 2006.286.02:28:54.46#ibcon#read 5, iclass 19, count 0 2006.286.02:28:54.46#ibcon#about to read 6, iclass 19, count 0 2006.286.02:28:54.46#ibcon#read 6, iclass 19, count 0 2006.286.02:28:54.46#ibcon#end of sib2, iclass 19, count 0 2006.286.02:28:54.46#ibcon#*after write, iclass 19, count 0 2006.286.02:28:54.46#ibcon#*before return 0, iclass 19, count 0 2006.286.02:28:54.46#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:28:54.46#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:28:54.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:28:54.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:28:54.46$vck44/vblo=8,744.99 2006.286.02:28:54.46#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.02:28:54.46#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.02:28:54.46#ibcon#ireg 17 cls_cnt 0 2006.286.02:28:54.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:28:54.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:28:54.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:28:54.46#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:28:54.46#ibcon#first serial, iclass 21, count 0 2006.286.02:28:54.46#ibcon#enter sib2, iclass 21, count 0 2006.286.02:28:54.46#ibcon#flushed, iclass 21, count 0 2006.286.02:28:54.46#ibcon#about to write, iclass 21, count 0 2006.286.02:28:54.46#ibcon#wrote, iclass 21, count 0 2006.286.02:28:54.46#ibcon#about to read 3, iclass 21, count 0 2006.286.02:28:54.48#ibcon#read 3, iclass 21, count 0 2006.286.02:28:54.48#ibcon#about to read 4, iclass 21, count 0 2006.286.02:28:54.48#ibcon#read 4, iclass 21, count 0 2006.286.02:28:54.48#ibcon#about to read 5, iclass 21, count 0 2006.286.02:28:54.48#ibcon#read 5, iclass 21, count 0 2006.286.02:28:54.48#ibcon#about to read 6, iclass 21, count 0 2006.286.02:28:54.48#ibcon#read 6, iclass 21, count 0 2006.286.02:28:54.48#ibcon#end of sib2, iclass 21, count 0 2006.286.02:28:54.48#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:28:54.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:28:54.48#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.02:28:54.48#ibcon#*before write, iclass 21, count 0 2006.286.02:28:54.48#ibcon#enter sib2, iclass 21, count 0 2006.286.02:28:54.48#ibcon#flushed, iclass 21, count 0 2006.286.02:28:54.48#ibcon#about to write, iclass 21, count 0 2006.286.02:28:54.48#ibcon#wrote, iclass 21, count 0 2006.286.02:28:54.48#ibcon#about to read 3, iclass 21, count 0 2006.286.02:28:54.52#ibcon#read 3, iclass 21, count 0 2006.286.02:28:54.52#ibcon#about to read 4, iclass 21, count 0 2006.286.02:28:54.52#ibcon#read 4, iclass 21, count 0 2006.286.02:28:54.52#ibcon#about to read 5, iclass 21, count 0 2006.286.02:28:54.52#ibcon#read 5, iclass 21, count 0 2006.286.02:28:54.52#ibcon#about to read 6, iclass 21, count 0 2006.286.02:28:54.52#ibcon#read 6, iclass 21, count 0 2006.286.02:28:54.52#ibcon#end of sib2, iclass 21, count 0 2006.286.02:28:54.52#ibcon#*after write, iclass 21, count 0 2006.286.02:28:54.52#ibcon#*before return 0, iclass 21, count 0 2006.286.02:28:54.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:28:54.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:28:54.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:28:54.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:28:54.52$vck44/vb=8,4 2006.286.02:28:54.52#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.02:28:54.52#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.02:28:54.52#ibcon#ireg 11 cls_cnt 2 2006.286.02:28:54.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:28:54.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:28:54.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:28:54.58#ibcon#enter wrdev, iclass 23, count 2 2006.286.02:28:54.58#ibcon#first serial, iclass 23, count 2 2006.286.02:28:54.58#ibcon#enter sib2, iclass 23, count 2 2006.286.02:28:54.58#ibcon#flushed, iclass 23, count 2 2006.286.02:28:54.58#ibcon#about to write, iclass 23, count 2 2006.286.02:28:54.58#ibcon#wrote, iclass 23, count 2 2006.286.02:28:54.58#ibcon#about to read 3, iclass 23, count 2 2006.286.02:28:54.60#ibcon#read 3, iclass 23, count 2 2006.286.02:28:54.60#ibcon#about to read 4, iclass 23, count 2 2006.286.02:28:54.60#ibcon#read 4, iclass 23, count 2 2006.286.02:28:54.60#ibcon#about to read 5, iclass 23, count 2 2006.286.02:28:54.60#ibcon#read 5, iclass 23, count 2 2006.286.02:28:54.60#ibcon#about to read 6, iclass 23, count 2 2006.286.02:28:54.60#ibcon#read 6, iclass 23, count 2 2006.286.02:28:54.60#ibcon#end of sib2, iclass 23, count 2 2006.286.02:28:54.60#ibcon#*mode == 0, iclass 23, count 2 2006.286.02:28:54.60#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.02:28:54.60#ibcon#[27=AT08-04\r\n] 2006.286.02:28:54.60#ibcon#*before write, iclass 23, count 2 2006.286.02:28:54.60#ibcon#enter sib2, iclass 23, count 2 2006.286.02:28:54.60#ibcon#flushed, iclass 23, count 2 2006.286.02:28:54.60#ibcon#about to write, iclass 23, count 2 2006.286.02:28:54.60#ibcon#wrote, iclass 23, count 2 2006.286.02:28:54.60#ibcon#about to read 3, iclass 23, count 2 2006.286.02:28:54.63#ibcon#read 3, iclass 23, count 2 2006.286.02:28:54.63#ibcon#about to read 4, iclass 23, count 2 2006.286.02:28:54.63#ibcon#read 4, iclass 23, count 2 2006.286.02:28:54.63#ibcon#about to read 5, iclass 23, count 2 2006.286.02:28:54.63#ibcon#read 5, iclass 23, count 2 2006.286.02:28:54.63#ibcon#about to read 6, iclass 23, count 2 2006.286.02:28:54.63#ibcon#read 6, iclass 23, count 2 2006.286.02:28:54.63#ibcon#end of sib2, iclass 23, count 2 2006.286.02:28:54.63#ibcon#*after write, iclass 23, count 2 2006.286.02:28:54.63#ibcon#*before return 0, iclass 23, count 2 2006.286.02:28:54.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:28:54.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:28:54.63#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.02:28:54.63#ibcon#ireg 7 cls_cnt 0 2006.286.02:28:54.63#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:28:54.75#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:28:54.75#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:28:54.75#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:28:54.75#ibcon#first serial, iclass 23, count 0 2006.286.02:28:54.75#ibcon#enter sib2, iclass 23, count 0 2006.286.02:28:54.75#ibcon#flushed, iclass 23, count 0 2006.286.02:28:54.75#ibcon#about to write, iclass 23, count 0 2006.286.02:28:54.75#ibcon#wrote, iclass 23, count 0 2006.286.02:28:54.75#ibcon#about to read 3, iclass 23, count 0 2006.286.02:28:54.77#ibcon#read 3, iclass 23, count 0 2006.286.02:28:54.77#ibcon#about to read 4, iclass 23, count 0 2006.286.02:28:54.77#ibcon#read 4, iclass 23, count 0 2006.286.02:28:54.77#ibcon#about to read 5, iclass 23, count 0 2006.286.02:28:54.77#ibcon#read 5, iclass 23, count 0 2006.286.02:28:54.77#ibcon#about to read 6, iclass 23, count 0 2006.286.02:28:54.77#ibcon#read 6, iclass 23, count 0 2006.286.02:28:54.77#ibcon#end of sib2, iclass 23, count 0 2006.286.02:28:54.77#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:28:54.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:28:54.77#ibcon#[27=USB\r\n] 2006.286.02:28:54.77#ibcon#*before write, iclass 23, count 0 2006.286.02:28:54.77#ibcon#enter sib2, iclass 23, count 0 2006.286.02:28:54.77#ibcon#flushed, iclass 23, count 0 2006.286.02:28:54.77#ibcon#about to write, iclass 23, count 0 2006.286.02:28:54.77#ibcon#wrote, iclass 23, count 0 2006.286.02:28:54.77#ibcon#about to read 3, iclass 23, count 0 2006.286.02:28:54.80#ibcon#read 3, iclass 23, count 0 2006.286.02:28:54.80#ibcon#about to read 4, iclass 23, count 0 2006.286.02:28:54.80#ibcon#read 4, iclass 23, count 0 2006.286.02:28:54.80#ibcon#about to read 5, iclass 23, count 0 2006.286.02:28:54.80#ibcon#read 5, iclass 23, count 0 2006.286.02:28:54.80#ibcon#about to read 6, iclass 23, count 0 2006.286.02:28:54.80#ibcon#read 6, iclass 23, count 0 2006.286.02:28:54.80#ibcon#end of sib2, iclass 23, count 0 2006.286.02:28:54.80#ibcon#*after write, iclass 23, count 0 2006.286.02:28:54.80#ibcon#*before return 0, iclass 23, count 0 2006.286.02:28:54.80#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:28:54.80#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:28:54.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:28:54.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:28:54.80$vck44/vabw=wide 2006.286.02:28:54.80#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.02:28:54.80#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.02:28:54.80#ibcon#ireg 8 cls_cnt 0 2006.286.02:28:54.80#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:28:54.80#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:28:54.80#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:28:54.80#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:28:54.80#ibcon#first serial, iclass 25, count 0 2006.286.02:28:54.80#ibcon#enter sib2, iclass 25, count 0 2006.286.02:28:54.80#ibcon#flushed, iclass 25, count 0 2006.286.02:28:54.80#ibcon#about to write, iclass 25, count 0 2006.286.02:28:54.80#ibcon#wrote, iclass 25, count 0 2006.286.02:28:54.80#ibcon#about to read 3, iclass 25, count 0 2006.286.02:28:54.82#ibcon#read 3, iclass 25, count 0 2006.286.02:28:54.82#ibcon#about to read 4, iclass 25, count 0 2006.286.02:28:54.82#ibcon#read 4, iclass 25, count 0 2006.286.02:28:54.82#ibcon#about to read 5, iclass 25, count 0 2006.286.02:28:54.82#ibcon#read 5, iclass 25, count 0 2006.286.02:28:54.82#ibcon#about to read 6, iclass 25, count 0 2006.286.02:28:54.82#ibcon#read 6, iclass 25, count 0 2006.286.02:28:54.82#ibcon#end of sib2, iclass 25, count 0 2006.286.02:28:54.82#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:28:54.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:28:54.82#ibcon#[25=BW32\r\n] 2006.286.02:28:54.82#ibcon#*before write, iclass 25, count 0 2006.286.02:28:54.82#ibcon#enter sib2, iclass 25, count 0 2006.286.02:28:54.82#ibcon#flushed, iclass 25, count 0 2006.286.02:28:54.82#ibcon#about to write, iclass 25, count 0 2006.286.02:28:54.82#ibcon#wrote, iclass 25, count 0 2006.286.02:28:54.82#ibcon#about to read 3, iclass 25, count 0 2006.286.02:28:54.85#ibcon#read 3, iclass 25, count 0 2006.286.02:28:54.85#ibcon#about to read 4, iclass 25, count 0 2006.286.02:28:54.85#ibcon#read 4, iclass 25, count 0 2006.286.02:28:54.85#ibcon#about to read 5, iclass 25, count 0 2006.286.02:28:54.85#ibcon#read 5, iclass 25, count 0 2006.286.02:28:54.85#ibcon#about to read 6, iclass 25, count 0 2006.286.02:28:54.85#ibcon#read 6, iclass 25, count 0 2006.286.02:28:54.85#ibcon#end of sib2, iclass 25, count 0 2006.286.02:28:54.85#ibcon#*after write, iclass 25, count 0 2006.286.02:28:54.85#ibcon#*before return 0, iclass 25, count 0 2006.286.02:28:54.85#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:28:54.85#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:28:54.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:28:54.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:28:54.85$vck44/vbbw=wide 2006.286.02:28:54.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.02:28:54.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.02:28:54.85#ibcon#ireg 8 cls_cnt 0 2006.286.02:28:54.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:28:54.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:28:54.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:28:54.92#ibcon#enter wrdev, iclass 27, count 0 2006.286.02:28:54.92#ibcon#first serial, iclass 27, count 0 2006.286.02:28:54.92#ibcon#enter sib2, iclass 27, count 0 2006.286.02:28:54.92#ibcon#flushed, iclass 27, count 0 2006.286.02:28:54.92#ibcon#about to write, iclass 27, count 0 2006.286.02:28:54.92#ibcon#wrote, iclass 27, count 0 2006.286.02:28:54.92#ibcon#about to read 3, iclass 27, count 0 2006.286.02:28:54.94#ibcon#read 3, iclass 27, count 0 2006.286.02:28:54.94#ibcon#about to read 4, iclass 27, count 0 2006.286.02:28:54.94#ibcon#read 4, iclass 27, count 0 2006.286.02:28:54.94#ibcon#about to read 5, iclass 27, count 0 2006.286.02:28:54.94#ibcon#read 5, iclass 27, count 0 2006.286.02:28:54.94#ibcon#about to read 6, iclass 27, count 0 2006.286.02:28:54.94#ibcon#read 6, iclass 27, count 0 2006.286.02:28:54.94#ibcon#end of sib2, iclass 27, count 0 2006.286.02:28:54.94#ibcon#*mode == 0, iclass 27, count 0 2006.286.02:28:54.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.02:28:54.94#ibcon#[27=BW32\r\n] 2006.286.02:28:54.94#ibcon#*before write, iclass 27, count 0 2006.286.02:28:54.94#ibcon#enter sib2, iclass 27, count 0 2006.286.02:28:54.94#ibcon#flushed, iclass 27, count 0 2006.286.02:28:54.94#ibcon#about to write, iclass 27, count 0 2006.286.02:28:54.94#ibcon#wrote, iclass 27, count 0 2006.286.02:28:54.94#ibcon#about to read 3, iclass 27, count 0 2006.286.02:28:54.97#ibcon#read 3, iclass 27, count 0 2006.286.02:28:54.97#ibcon#about to read 4, iclass 27, count 0 2006.286.02:28:54.97#ibcon#read 4, iclass 27, count 0 2006.286.02:28:54.97#ibcon#about to read 5, iclass 27, count 0 2006.286.02:28:54.97#ibcon#read 5, iclass 27, count 0 2006.286.02:28:54.97#ibcon#about to read 6, iclass 27, count 0 2006.286.02:28:54.97#ibcon#read 6, iclass 27, count 0 2006.286.02:28:54.97#ibcon#end of sib2, iclass 27, count 0 2006.286.02:28:54.97#ibcon#*after write, iclass 27, count 0 2006.286.02:28:54.97#ibcon#*before return 0, iclass 27, count 0 2006.286.02:28:54.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:28:54.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:28:54.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.02:28:54.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.02:28:54.97$setupk4/ifdk4 2006.286.02:28:54.97$ifdk4/lo= 2006.286.02:28:54.97$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.02:28:54.97$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.02:28:54.97$ifdk4/patch= 2006.286.02:28:54.97$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.02:28:54.97$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.02:28:54.97$setupk4/!*+20s 2006.286.02:29:03.18#abcon#<5=/04 2.6 5.6 21.40 811015.9\r\n> 2006.286.02:29:03.20#abcon#{5=INTERFACE CLEAR} 2006.286.02:29:03.26#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:29:04.14#trakl#Source acquired 2006.286.02:29:04.14#flagr#flagr/antenna,acquired 2006.286.02:29:09.48$setupk4/"tpicd 2006.286.02:29:09.48$setupk4/echo=off 2006.286.02:29:09.48$setupk4/xlog=off 2006.286.02:29:09.48:!2006.286.02:31:04 2006.286.02:31:04.00:preob 2006.286.02:31:05.14/onsource/TRACKING 2006.286.02:31:05.14:!2006.286.02:31:14 2006.286.02:31:14.00:"tape 2006.286.02:31:14.00:"st=record 2006.286.02:31:14.00:data_valid=on 2006.286.02:31:14.00:midob 2006.286.02:31:14.14/onsource/TRACKING 2006.286.02:31:14.14/wx/21.41,1015.9,80 2006.286.02:31:14.23/cable/+6.4985E-03 2006.286.02:31:15.32/va/01,07,usb,yes,32,35 2006.286.02:31:15.32/va/02,06,usb,yes,32,32 2006.286.02:31:15.32/va/03,07,usb,yes,31,33 2006.286.02:31:15.32/va/04,06,usb,yes,33,34 2006.286.02:31:15.32/va/05,03,usb,yes,32,33 2006.286.02:31:15.32/va/06,04,usb,yes,29,29 2006.286.02:31:15.32/va/07,04,usb,yes,30,30 2006.286.02:31:15.32/va/08,03,usb,yes,30,37 2006.286.02:31:15.55/valo/01,524.99,yes,locked 2006.286.02:31:15.55/valo/02,534.99,yes,locked 2006.286.02:31:15.55/valo/03,564.99,yes,locked 2006.286.02:31:15.55/valo/04,624.99,yes,locked 2006.286.02:31:15.55/valo/05,734.99,yes,locked 2006.286.02:31:15.55/valo/06,814.99,yes,locked 2006.286.02:31:15.55/valo/07,864.99,yes,locked 2006.286.02:31:15.55/valo/08,884.99,yes,locked 2006.286.02:31:16.64/vb/01,04,usb,yes,31,29 2006.286.02:31:16.64/vb/02,05,usb,yes,29,29 2006.286.02:31:16.64/vb/03,04,usb,yes,30,33 2006.286.02:31:16.64/vb/04,05,usb,yes,30,29 2006.286.02:31:16.64/vb/05,04,usb,yes,27,29 2006.286.02:31:16.64/vb/06,03,usb,yes,38,34 2006.286.02:31:16.64/vb/07,04,usb,yes,31,31 2006.286.02:31:16.64/vb/08,04,usb,yes,28,32 2006.286.02:31:16.87/vblo/01,629.99,yes,locked 2006.286.02:31:16.87/vblo/02,634.99,yes,locked 2006.286.02:31:16.87/vblo/03,649.99,yes,locked 2006.286.02:31:16.87/vblo/04,679.99,yes,locked 2006.286.02:31:16.87/vblo/05,709.99,yes,locked 2006.286.02:31:16.87/vblo/06,719.99,yes,locked 2006.286.02:31:16.87/vblo/07,734.99,yes,locked 2006.286.02:31:16.87/vblo/08,744.99,yes,locked 2006.286.02:31:17.02/vabw/8 2006.286.02:31:17.17/vbbw/8 2006.286.02:31:17.26/xfe/off,on,12.0 2006.286.02:31:17.63/ifatt/23,28,28,28 2006.286.02:31:18.08/fmout-gps/S +2.79E-07 2006.286.02:31:18.10:!2006.286.02:31:54 2006.286.02:31:54.00:data_valid=off 2006.286.02:31:54.00:"et 2006.286.02:31:54.00:!+3s 2006.286.02:31:57.01:"tape 2006.286.02:31:57.01:postob 2006.286.02:31:57.23/cable/+6.4981E-03 2006.286.02:31:57.23/wx/21.41,1015.9,80 2006.286.02:31:58.07/fmout-gps/S +2.77E-07 2006.286.02:31:58.07:scan_name=286-0233,jd0610,50 2006.286.02:31:58.07:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.286.02:31:59.13#flagr#flagr/antenna,new-source 2006.286.02:31:59.13:checkk5 2006.286.02:31:59.73/chk_autoobs//k5ts1/ autoobs is running! 2006.286.02:32:00.11/chk_autoobs//k5ts2/ autoobs is running! 2006.286.02:32:00.51/chk_autoobs//k5ts3/ autoobs is running! 2006.286.02:32:00.96/chk_autoobs//k5ts4/ autoobs is running! 2006.286.02:32:01.34/chk_obsdata//k5ts1/T2860231??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:32:01.76/chk_obsdata//k5ts2/T2860231??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:32:02.15/chk_obsdata//k5ts3/T2860231??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:32:02.53/chk_obsdata//k5ts4/T2860231??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.02:32:03.67/k5log//k5ts1_log_newline 2006.286.02:32:04.43/k5log//k5ts2_log_newline 2006.286.02:32:05.14/k5log//k5ts3_log_newline 2006.286.02:32:06.13/k5log//k5ts4_log_newline 2006.286.02:32:06.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.02:32:06.15:setupk4=1 2006.286.02:32:06.15$setupk4/echo=on 2006.286.02:32:06.15$setupk4/pcalon 2006.286.02:32:06.15$pcalon/"no phase cal control is implemented here 2006.286.02:32:06.15$setupk4/"tpicd=stop 2006.286.02:32:06.15$setupk4/"rec=synch_on 2006.286.02:32:06.15$setupk4/"rec_mode=128 2006.286.02:32:06.15$setupk4/!* 2006.286.02:32:06.15$setupk4/recpk4 2006.286.02:32:06.15$recpk4/recpatch= 2006.286.02:32:06.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.02:32:06.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.02:32:06.15$setupk4/vck44 2006.286.02:32:06.15$vck44/valo=1,524.99 2006.286.02:32:06.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.02:32:06.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.02:32:06.16#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:06.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:32:06.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:32:06.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:32:06.16#ibcon#enter wrdev, iclass 27, count 0 2006.286.02:32:06.16#ibcon#first serial, iclass 27, count 0 2006.286.02:32:06.16#ibcon#enter sib2, iclass 27, count 0 2006.286.02:32:06.16#ibcon#flushed, iclass 27, count 0 2006.286.02:32:06.16#ibcon#about to write, iclass 27, count 0 2006.286.02:32:06.16#ibcon#wrote, iclass 27, count 0 2006.286.02:32:06.16#ibcon#about to read 3, iclass 27, count 0 2006.286.02:32:06.18#ibcon#read 3, iclass 27, count 0 2006.286.02:32:06.18#ibcon#about to read 4, iclass 27, count 0 2006.286.02:32:06.18#ibcon#read 4, iclass 27, count 0 2006.286.02:32:06.18#ibcon#about to read 5, iclass 27, count 0 2006.286.02:32:06.18#ibcon#read 5, iclass 27, count 0 2006.286.02:32:06.18#ibcon#about to read 6, iclass 27, count 0 2006.286.02:32:06.18#ibcon#read 6, iclass 27, count 0 2006.286.02:32:06.18#ibcon#end of sib2, iclass 27, count 0 2006.286.02:32:06.18#ibcon#*mode == 0, iclass 27, count 0 2006.286.02:32:06.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.02:32:06.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.02:32:06.18#ibcon#*before write, iclass 27, count 0 2006.286.02:32:06.18#ibcon#enter sib2, iclass 27, count 0 2006.286.02:32:06.18#ibcon#flushed, iclass 27, count 0 2006.286.02:32:06.18#ibcon#about to write, iclass 27, count 0 2006.286.02:32:06.18#ibcon#wrote, iclass 27, count 0 2006.286.02:32:06.18#ibcon#about to read 3, iclass 27, count 0 2006.286.02:32:06.23#ibcon#read 3, iclass 27, count 0 2006.286.02:32:06.23#ibcon#about to read 4, iclass 27, count 0 2006.286.02:32:06.23#ibcon#read 4, iclass 27, count 0 2006.286.02:32:06.23#ibcon#about to read 5, iclass 27, count 0 2006.286.02:32:06.23#ibcon#read 5, iclass 27, count 0 2006.286.02:32:06.23#ibcon#about to read 6, iclass 27, count 0 2006.286.02:32:06.23#ibcon#read 6, iclass 27, count 0 2006.286.02:32:06.23#ibcon#end of sib2, iclass 27, count 0 2006.286.02:32:06.23#ibcon#*after write, iclass 27, count 0 2006.286.02:32:06.23#ibcon#*before return 0, iclass 27, count 0 2006.286.02:32:06.23#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:32:06.23#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:32:06.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.02:32:06.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.02:32:06.23$vck44/va=1,7 2006.286.02:32:06.23#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.02:32:06.23#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.02:32:06.23#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:06.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:32:06.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:32:06.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:32:06.23#ibcon#enter wrdev, iclass 29, count 2 2006.286.02:32:06.23#ibcon#first serial, iclass 29, count 2 2006.286.02:32:06.23#ibcon#enter sib2, iclass 29, count 2 2006.286.02:32:06.23#ibcon#flushed, iclass 29, count 2 2006.286.02:32:06.23#ibcon#about to write, iclass 29, count 2 2006.286.02:32:06.23#ibcon#wrote, iclass 29, count 2 2006.286.02:32:06.23#ibcon#about to read 3, iclass 29, count 2 2006.286.02:32:06.25#ibcon#read 3, iclass 29, count 2 2006.286.02:32:06.25#ibcon#about to read 4, iclass 29, count 2 2006.286.02:32:06.25#ibcon#read 4, iclass 29, count 2 2006.286.02:32:06.25#ibcon#about to read 5, iclass 29, count 2 2006.286.02:32:06.25#ibcon#read 5, iclass 29, count 2 2006.286.02:32:06.25#ibcon#about to read 6, iclass 29, count 2 2006.286.02:32:06.25#ibcon#read 6, iclass 29, count 2 2006.286.02:32:06.25#ibcon#end of sib2, iclass 29, count 2 2006.286.02:32:06.25#ibcon#*mode == 0, iclass 29, count 2 2006.286.02:32:06.25#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.02:32:06.25#ibcon#[25=AT01-07\r\n] 2006.286.02:32:06.25#ibcon#*before write, iclass 29, count 2 2006.286.02:32:06.25#ibcon#enter sib2, iclass 29, count 2 2006.286.02:32:06.25#ibcon#flushed, iclass 29, count 2 2006.286.02:32:06.25#ibcon#about to write, iclass 29, count 2 2006.286.02:32:06.25#ibcon#wrote, iclass 29, count 2 2006.286.02:32:06.25#ibcon#about to read 3, iclass 29, count 2 2006.286.02:32:06.28#ibcon#read 3, iclass 29, count 2 2006.286.02:32:06.28#ibcon#about to read 4, iclass 29, count 2 2006.286.02:32:06.28#ibcon#read 4, iclass 29, count 2 2006.286.02:32:06.28#ibcon#about to read 5, iclass 29, count 2 2006.286.02:32:06.28#ibcon#read 5, iclass 29, count 2 2006.286.02:32:06.28#ibcon#about to read 6, iclass 29, count 2 2006.286.02:32:06.28#ibcon#read 6, iclass 29, count 2 2006.286.02:32:06.28#ibcon#end of sib2, iclass 29, count 2 2006.286.02:32:06.28#ibcon#*after write, iclass 29, count 2 2006.286.02:32:06.28#ibcon#*before return 0, iclass 29, count 2 2006.286.02:32:06.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:32:06.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:32:06.28#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.02:32:06.28#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:06.28#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:32:06.40#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:32:06.40#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:32:06.40#ibcon#enter wrdev, iclass 29, count 0 2006.286.02:32:06.40#ibcon#first serial, iclass 29, count 0 2006.286.02:32:06.40#ibcon#enter sib2, iclass 29, count 0 2006.286.02:32:06.40#ibcon#flushed, iclass 29, count 0 2006.286.02:32:06.40#ibcon#about to write, iclass 29, count 0 2006.286.02:32:06.40#ibcon#wrote, iclass 29, count 0 2006.286.02:32:06.40#ibcon#about to read 3, iclass 29, count 0 2006.286.02:32:06.42#ibcon#read 3, iclass 29, count 0 2006.286.02:32:06.42#ibcon#about to read 4, iclass 29, count 0 2006.286.02:32:06.42#ibcon#read 4, iclass 29, count 0 2006.286.02:32:06.42#ibcon#about to read 5, iclass 29, count 0 2006.286.02:32:06.42#ibcon#read 5, iclass 29, count 0 2006.286.02:32:06.42#ibcon#about to read 6, iclass 29, count 0 2006.286.02:32:06.42#ibcon#read 6, iclass 29, count 0 2006.286.02:32:06.42#ibcon#end of sib2, iclass 29, count 0 2006.286.02:32:06.42#ibcon#*mode == 0, iclass 29, count 0 2006.286.02:32:06.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.02:32:06.42#ibcon#[25=USB\r\n] 2006.286.02:32:06.42#ibcon#*before write, iclass 29, count 0 2006.286.02:32:06.42#ibcon#enter sib2, iclass 29, count 0 2006.286.02:32:06.42#ibcon#flushed, iclass 29, count 0 2006.286.02:32:06.42#ibcon#about to write, iclass 29, count 0 2006.286.02:32:06.42#ibcon#wrote, iclass 29, count 0 2006.286.02:32:06.42#ibcon#about to read 3, iclass 29, count 0 2006.286.02:32:06.45#ibcon#read 3, iclass 29, count 0 2006.286.02:32:06.45#ibcon#about to read 4, iclass 29, count 0 2006.286.02:32:06.45#ibcon#read 4, iclass 29, count 0 2006.286.02:32:06.45#ibcon#about to read 5, iclass 29, count 0 2006.286.02:32:06.45#ibcon#read 5, iclass 29, count 0 2006.286.02:32:06.45#ibcon#about to read 6, iclass 29, count 0 2006.286.02:32:06.45#ibcon#read 6, iclass 29, count 0 2006.286.02:32:06.45#ibcon#end of sib2, iclass 29, count 0 2006.286.02:32:06.45#ibcon#*after write, iclass 29, count 0 2006.286.02:32:06.45#ibcon#*before return 0, iclass 29, count 0 2006.286.02:32:06.45#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:32:06.45#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:32:06.45#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.02:32:06.45#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.02:32:06.45$vck44/valo=2,534.99 2006.286.02:32:06.45#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.02:32:06.45#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.02:32:06.45#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:06.45#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:32:06.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:32:06.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:32:06.45#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:32:06.45#ibcon#first serial, iclass 31, count 0 2006.286.02:32:06.45#ibcon#enter sib2, iclass 31, count 0 2006.286.02:32:06.45#ibcon#flushed, iclass 31, count 0 2006.286.02:32:06.45#ibcon#about to write, iclass 31, count 0 2006.286.02:32:06.45#ibcon#wrote, iclass 31, count 0 2006.286.02:32:06.45#ibcon#about to read 3, iclass 31, count 0 2006.286.02:32:06.47#ibcon#read 3, iclass 31, count 0 2006.286.02:32:06.47#ibcon#about to read 4, iclass 31, count 0 2006.286.02:32:06.47#ibcon#read 4, iclass 31, count 0 2006.286.02:32:06.47#ibcon#about to read 5, iclass 31, count 0 2006.286.02:32:06.47#ibcon#read 5, iclass 31, count 0 2006.286.02:32:06.47#ibcon#about to read 6, iclass 31, count 0 2006.286.02:32:06.47#ibcon#read 6, iclass 31, count 0 2006.286.02:32:06.47#ibcon#end of sib2, iclass 31, count 0 2006.286.02:32:06.47#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:32:06.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:32:06.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.02:32:06.47#ibcon#*before write, iclass 31, count 0 2006.286.02:32:06.47#ibcon#enter sib2, iclass 31, count 0 2006.286.02:32:06.47#ibcon#flushed, iclass 31, count 0 2006.286.02:32:06.47#ibcon#about to write, iclass 31, count 0 2006.286.02:32:06.47#ibcon#wrote, iclass 31, count 0 2006.286.02:32:06.47#ibcon#about to read 3, iclass 31, count 0 2006.286.02:32:06.51#ibcon#read 3, iclass 31, count 0 2006.286.02:32:06.51#ibcon#about to read 4, iclass 31, count 0 2006.286.02:32:06.51#ibcon#read 4, iclass 31, count 0 2006.286.02:32:06.51#ibcon#about to read 5, iclass 31, count 0 2006.286.02:32:06.51#ibcon#read 5, iclass 31, count 0 2006.286.02:32:06.51#ibcon#about to read 6, iclass 31, count 0 2006.286.02:32:06.51#ibcon#read 6, iclass 31, count 0 2006.286.02:32:06.51#ibcon#end of sib2, iclass 31, count 0 2006.286.02:32:06.51#ibcon#*after write, iclass 31, count 0 2006.286.02:32:06.51#ibcon#*before return 0, iclass 31, count 0 2006.286.02:32:06.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:32:06.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:32:06.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:32:06.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:32:06.51$vck44/va=2,6 2006.286.02:32:06.51#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.02:32:06.51#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.02:32:06.51#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:06.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:32:06.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:32:06.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:32:06.57#ibcon#enter wrdev, iclass 33, count 2 2006.286.02:32:06.57#ibcon#first serial, iclass 33, count 2 2006.286.02:32:06.57#ibcon#enter sib2, iclass 33, count 2 2006.286.02:32:06.57#ibcon#flushed, iclass 33, count 2 2006.286.02:32:06.57#ibcon#about to write, iclass 33, count 2 2006.286.02:32:06.57#ibcon#wrote, iclass 33, count 2 2006.286.02:32:06.57#ibcon#about to read 3, iclass 33, count 2 2006.286.02:32:06.59#ibcon#read 3, iclass 33, count 2 2006.286.02:32:06.59#ibcon#about to read 4, iclass 33, count 2 2006.286.02:32:06.59#ibcon#read 4, iclass 33, count 2 2006.286.02:32:06.59#ibcon#about to read 5, iclass 33, count 2 2006.286.02:32:06.59#ibcon#read 5, iclass 33, count 2 2006.286.02:32:06.59#ibcon#about to read 6, iclass 33, count 2 2006.286.02:32:06.59#ibcon#read 6, iclass 33, count 2 2006.286.02:32:06.59#ibcon#end of sib2, iclass 33, count 2 2006.286.02:32:06.59#ibcon#*mode == 0, iclass 33, count 2 2006.286.02:32:06.59#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.02:32:06.59#ibcon#[25=AT02-06\r\n] 2006.286.02:32:06.59#ibcon#*before write, iclass 33, count 2 2006.286.02:32:06.59#ibcon#enter sib2, iclass 33, count 2 2006.286.02:32:06.59#ibcon#flushed, iclass 33, count 2 2006.286.02:32:06.59#ibcon#about to write, iclass 33, count 2 2006.286.02:32:06.59#ibcon#wrote, iclass 33, count 2 2006.286.02:32:06.59#ibcon#about to read 3, iclass 33, count 2 2006.286.02:32:06.62#ibcon#read 3, iclass 33, count 2 2006.286.02:32:06.62#ibcon#about to read 4, iclass 33, count 2 2006.286.02:32:06.62#ibcon#read 4, iclass 33, count 2 2006.286.02:32:06.62#ibcon#about to read 5, iclass 33, count 2 2006.286.02:32:06.62#ibcon#read 5, iclass 33, count 2 2006.286.02:32:06.62#ibcon#about to read 6, iclass 33, count 2 2006.286.02:32:06.62#ibcon#read 6, iclass 33, count 2 2006.286.02:32:06.62#ibcon#end of sib2, iclass 33, count 2 2006.286.02:32:06.62#ibcon#*after write, iclass 33, count 2 2006.286.02:32:06.62#ibcon#*before return 0, iclass 33, count 2 2006.286.02:32:06.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:32:06.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:32:06.62#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.02:32:06.62#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:06.62#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:32:06.74#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:32:06.74#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:32:06.74#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:32:06.74#ibcon#first serial, iclass 33, count 0 2006.286.02:32:06.74#ibcon#enter sib2, iclass 33, count 0 2006.286.02:32:06.74#ibcon#flushed, iclass 33, count 0 2006.286.02:32:06.74#ibcon#about to write, iclass 33, count 0 2006.286.02:32:06.74#ibcon#wrote, iclass 33, count 0 2006.286.02:32:06.74#ibcon#about to read 3, iclass 33, count 0 2006.286.02:32:06.76#ibcon#read 3, iclass 33, count 0 2006.286.02:32:06.76#ibcon#about to read 4, iclass 33, count 0 2006.286.02:32:06.76#ibcon#read 4, iclass 33, count 0 2006.286.02:32:06.76#ibcon#about to read 5, iclass 33, count 0 2006.286.02:32:06.76#ibcon#read 5, iclass 33, count 0 2006.286.02:32:06.76#ibcon#about to read 6, iclass 33, count 0 2006.286.02:32:06.76#ibcon#read 6, iclass 33, count 0 2006.286.02:32:06.76#ibcon#end of sib2, iclass 33, count 0 2006.286.02:32:06.76#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:32:06.76#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:32:06.76#ibcon#[25=USB\r\n] 2006.286.02:32:06.76#ibcon#*before write, iclass 33, count 0 2006.286.02:32:06.76#ibcon#enter sib2, iclass 33, count 0 2006.286.02:32:06.76#ibcon#flushed, iclass 33, count 0 2006.286.02:32:06.76#ibcon#about to write, iclass 33, count 0 2006.286.02:32:06.76#ibcon#wrote, iclass 33, count 0 2006.286.02:32:06.76#ibcon#about to read 3, iclass 33, count 0 2006.286.02:32:06.79#ibcon#read 3, iclass 33, count 0 2006.286.02:32:06.79#ibcon#about to read 4, iclass 33, count 0 2006.286.02:32:06.79#ibcon#read 4, iclass 33, count 0 2006.286.02:32:06.79#ibcon#about to read 5, iclass 33, count 0 2006.286.02:32:06.79#ibcon#read 5, iclass 33, count 0 2006.286.02:32:06.79#ibcon#about to read 6, iclass 33, count 0 2006.286.02:32:06.79#ibcon#read 6, iclass 33, count 0 2006.286.02:32:06.79#ibcon#end of sib2, iclass 33, count 0 2006.286.02:32:06.79#ibcon#*after write, iclass 33, count 0 2006.286.02:32:06.79#ibcon#*before return 0, iclass 33, count 0 2006.286.02:32:06.79#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:32:06.79#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:32:06.79#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:32:06.79#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:32:06.79$vck44/valo=3,564.99 2006.286.02:32:06.79#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.02:32:06.79#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.02:32:06.79#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:06.79#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:32:06.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:32:06.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:32:06.79#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:32:06.79#ibcon#first serial, iclass 35, count 0 2006.286.02:32:06.79#ibcon#enter sib2, iclass 35, count 0 2006.286.02:32:06.79#ibcon#flushed, iclass 35, count 0 2006.286.02:32:06.79#ibcon#about to write, iclass 35, count 0 2006.286.02:32:06.79#ibcon#wrote, iclass 35, count 0 2006.286.02:32:06.79#ibcon#about to read 3, iclass 35, count 0 2006.286.02:32:06.81#ibcon#read 3, iclass 35, count 0 2006.286.02:32:06.81#ibcon#about to read 4, iclass 35, count 0 2006.286.02:32:06.81#ibcon#read 4, iclass 35, count 0 2006.286.02:32:06.81#ibcon#about to read 5, iclass 35, count 0 2006.286.02:32:06.81#ibcon#read 5, iclass 35, count 0 2006.286.02:32:06.81#ibcon#about to read 6, iclass 35, count 0 2006.286.02:32:06.81#ibcon#read 6, iclass 35, count 0 2006.286.02:32:06.81#ibcon#end of sib2, iclass 35, count 0 2006.286.02:32:06.81#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:32:06.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:32:06.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.02:32:06.81#ibcon#*before write, iclass 35, count 0 2006.286.02:32:06.81#ibcon#enter sib2, iclass 35, count 0 2006.286.02:32:06.81#ibcon#flushed, iclass 35, count 0 2006.286.02:32:06.81#ibcon#about to write, iclass 35, count 0 2006.286.02:32:06.81#ibcon#wrote, iclass 35, count 0 2006.286.02:32:06.81#ibcon#about to read 3, iclass 35, count 0 2006.286.02:32:06.85#ibcon#read 3, iclass 35, count 0 2006.286.02:32:06.85#ibcon#about to read 4, iclass 35, count 0 2006.286.02:32:06.85#ibcon#read 4, iclass 35, count 0 2006.286.02:32:06.85#ibcon#about to read 5, iclass 35, count 0 2006.286.02:32:06.85#ibcon#read 5, iclass 35, count 0 2006.286.02:32:06.85#ibcon#about to read 6, iclass 35, count 0 2006.286.02:32:06.85#ibcon#read 6, iclass 35, count 0 2006.286.02:32:06.85#ibcon#end of sib2, iclass 35, count 0 2006.286.02:32:06.85#ibcon#*after write, iclass 35, count 0 2006.286.02:32:06.85#ibcon#*before return 0, iclass 35, count 0 2006.286.02:32:06.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:32:06.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:32:06.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:32:06.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:32:06.85$vck44/va=3,7 2006.286.02:32:06.85#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.02:32:06.85#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.02:32:06.85#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:06.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:32:06.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:32:06.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:32:06.91#ibcon#enter wrdev, iclass 37, count 2 2006.286.02:32:06.91#ibcon#first serial, iclass 37, count 2 2006.286.02:32:06.91#ibcon#enter sib2, iclass 37, count 2 2006.286.02:32:06.91#ibcon#flushed, iclass 37, count 2 2006.286.02:32:06.91#ibcon#about to write, iclass 37, count 2 2006.286.02:32:06.91#ibcon#wrote, iclass 37, count 2 2006.286.02:32:06.91#ibcon#about to read 3, iclass 37, count 2 2006.286.02:32:06.93#ibcon#read 3, iclass 37, count 2 2006.286.02:32:06.93#ibcon#about to read 4, iclass 37, count 2 2006.286.02:32:06.93#ibcon#read 4, iclass 37, count 2 2006.286.02:32:06.93#ibcon#about to read 5, iclass 37, count 2 2006.286.02:32:06.93#ibcon#read 5, iclass 37, count 2 2006.286.02:32:06.93#ibcon#about to read 6, iclass 37, count 2 2006.286.02:32:06.93#ibcon#read 6, iclass 37, count 2 2006.286.02:32:06.93#ibcon#end of sib2, iclass 37, count 2 2006.286.02:32:06.93#ibcon#*mode == 0, iclass 37, count 2 2006.286.02:32:06.93#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.02:32:06.93#ibcon#[25=AT03-07\r\n] 2006.286.02:32:06.93#ibcon#*before write, iclass 37, count 2 2006.286.02:32:06.93#ibcon#enter sib2, iclass 37, count 2 2006.286.02:32:06.93#ibcon#flushed, iclass 37, count 2 2006.286.02:32:06.93#ibcon#about to write, iclass 37, count 2 2006.286.02:32:06.93#ibcon#wrote, iclass 37, count 2 2006.286.02:32:06.93#ibcon#about to read 3, iclass 37, count 2 2006.286.02:32:06.96#ibcon#read 3, iclass 37, count 2 2006.286.02:32:06.96#ibcon#about to read 4, iclass 37, count 2 2006.286.02:32:06.96#ibcon#read 4, iclass 37, count 2 2006.286.02:32:06.96#ibcon#about to read 5, iclass 37, count 2 2006.286.02:32:06.96#ibcon#read 5, iclass 37, count 2 2006.286.02:32:06.96#ibcon#about to read 6, iclass 37, count 2 2006.286.02:32:06.96#ibcon#read 6, iclass 37, count 2 2006.286.02:32:06.96#ibcon#end of sib2, iclass 37, count 2 2006.286.02:32:06.96#ibcon#*after write, iclass 37, count 2 2006.286.02:32:06.96#ibcon#*before return 0, iclass 37, count 2 2006.286.02:32:06.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:32:06.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:32:06.96#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.02:32:06.96#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:06.96#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:32:07.08#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:32:07.08#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:32:07.08#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:32:07.08#ibcon#first serial, iclass 37, count 0 2006.286.02:32:07.08#ibcon#enter sib2, iclass 37, count 0 2006.286.02:32:07.08#ibcon#flushed, iclass 37, count 0 2006.286.02:32:07.08#ibcon#about to write, iclass 37, count 0 2006.286.02:32:07.08#ibcon#wrote, iclass 37, count 0 2006.286.02:32:07.08#ibcon#about to read 3, iclass 37, count 0 2006.286.02:32:07.10#ibcon#read 3, iclass 37, count 0 2006.286.02:32:07.10#ibcon#about to read 4, iclass 37, count 0 2006.286.02:32:07.10#ibcon#read 4, iclass 37, count 0 2006.286.02:32:07.10#ibcon#about to read 5, iclass 37, count 0 2006.286.02:32:07.10#ibcon#read 5, iclass 37, count 0 2006.286.02:32:07.10#ibcon#about to read 6, iclass 37, count 0 2006.286.02:32:07.10#ibcon#read 6, iclass 37, count 0 2006.286.02:32:07.10#ibcon#end of sib2, iclass 37, count 0 2006.286.02:32:07.10#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:32:07.10#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:32:07.10#ibcon#[25=USB\r\n] 2006.286.02:32:07.10#ibcon#*before write, iclass 37, count 0 2006.286.02:32:07.10#ibcon#enter sib2, iclass 37, count 0 2006.286.02:32:07.10#ibcon#flushed, iclass 37, count 0 2006.286.02:32:07.10#ibcon#about to write, iclass 37, count 0 2006.286.02:32:07.10#ibcon#wrote, iclass 37, count 0 2006.286.02:32:07.10#ibcon#about to read 3, iclass 37, count 0 2006.286.02:32:07.13#ibcon#read 3, iclass 37, count 0 2006.286.02:32:07.13#ibcon#about to read 4, iclass 37, count 0 2006.286.02:32:07.13#ibcon#read 4, iclass 37, count 0 2006.286.02:32:07.13#ibcon#about to read 5, iclass 37, count 0 2006.286.02:32:07.13#ibcon#read 5, iclass 37, count 0 2006.286.02:32:07.13#ibcon#about to read 6, iclass 37, count 0 2006.286.02:32:07.13#ibcon#read 6, iclass 37, count 0 2006.286.02:32:07.13#ibcon#end of sib2, iclass 37, count 0 2006.286.02:32:07.13#ibcon#*after write, iclass 37, count 0 2006.286.02:32:07.13#ibcon#*before return 0, iclass 37, count 0 2006.286.02:32:07.13#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:32:07.13#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:32:07.13#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:32:07.13#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:32:07.13$vck44/valo=4,624.99 2006.286.02:32:07.13#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.02:32:07.13#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.02:32:07.13#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:07.13#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:32:07.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:32:07.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:32:07.13#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:32:07.13#ibcon#first serial, iclass 39, count 0 2006.286.02:32:07.13#ibcon#enter sib2, iclass 39, count 0 2006.286.02:32:07.13#ibcon#flushed, iclass 39, count 0 2006.286.02:32:07.13#ibcon#about to write, iclass 39, count 0 2006.286.02:32:07.13#ibcon#wrote, iclass 39, count 0 2006.286.02:32:07.13#ibcon#about to read 3, iclass 39, count 0 2006.286.02:32:07.15#ibcon#read 3, iclass 39, count 0 2006.286.02:32:07.15#ibcon#about to read 4, iclass 39, count 0 2006.286.02:32:07.15#ibcon#read 4, iclass 39, count 0 2006.286.02:32:07.15#ibcon#about to read 5, iclass 39, count 0 2006.286.02:32:07.15#ibcon#read 5, iclass 39, count 0 2006.286.02:32:07.15#ibcon#about to read 6, iclass 39, count 0 2006.286.02:32:07.15#ibcon#read 6, iclass 39, count 0 2006.286.02:32:07.15#ibcon#end of sib2, iclass 39, count 0 2006.286.02:32:07.15#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:32:07.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:32:07.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.02:32:07.15#ibcon#*before write, iclass 39, count 0 2006.286.02:32:07.15#ibcon#enter sib2, iclass 39, count 0 2006.286.02:32:07.15#ibcon#flushed, iclass 39, count 0 2006.286.02:32:07.15#ibcon#about to write, iclass 39, count 0 2006.286.02:32:07.15#ibcon#wrote, iclass 39, count 0 2006.286.02:32:07.15#ibcon#about to read 3, iclass 39, count 0 2006.286.02:32:07.19#ibcon#read 3, iclass 39, count 0 2006.286.02:32:07.19#ibcon#about to read 4, iclass 39, count 0 2006.286.02:32:07.19#ibcon#read 4, iclass 39, count 0 2006.286.02:32:07.19#ibcon#about to read 5, iclass 39, count 0 2006.286.02:32:07.19#ibcon#read 5, iclass 39, count 0 2006.286.02:32:07.19#ibcon#about to read 6, iclass 39, count 0 2006.286.02:32:07.19#ibcon#read 6, iclass 39, count 0 2006.286.02:32:07.19#ibcon#end of sib2, iclass 39, count 0 2006.286.02:32:07.19#ibcon#*after write, iclass 39, count 0 2006.286.02:32:07.19#ibcon#*before return 0, iclass 39, count 0 2006.286.02:32:07.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:32:07.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:32:07.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:32:07.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:32:07.19$vck44/va=4,6 2006.286.02:32:07.19#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.02:32:07.19#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.02:32:07.19#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:07.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:32:07.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:32:07.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:32:07.25#ibcon#enter wrdev, iclass 3, count 2 2006.286.02:32:07.25#ibcon#first serial, iclass 3, count 2 2006.286.02:32:07.25#ibcon#enter sib2, iclass 3, count 2 2006.286.02:32:07.25#ibcon#flushed, iclass 3, count 2 2006.286.02:32:07.25#ibcon#about to write, iclass 3, count 2 2006.286.02:32:07.25#ibcon#wrote, iclass 3, count 2 2006.286.02:32:07.25#ibcon#about to read 3, iclass 3, count 2 2006.286.02:32:07.27#ibcon#read 3, iclass 3, count 2 2006.286.02:32:07.27#ibcon#about to read 4, iclass 3, count 2 2006.286.02:32:07.27#ibcon#read 4, iclass 3, count 2 2006.286.02:32:07.27#ibcon#about to read 5, iclass 3, count 2 2006.286.02:32:07.27#ibcon#read 5, iclass 3, count 2 2006.286.02:32:07.27#ibcon#about to read 6, iclass 3, count 2 2006.286.02:32:07.27#ibcon#read 6, iclass 3, count 2 2006.286.02:32:07.27#ibcon#end of sib2, iclass 3, count 2 2006.286.02:32:07.27#ibcon#*mode == 0, iclass 3, count 2 2006.286.02:32:07.27#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.02:32:07.27#ibcon#[25=AT04-06\r\n] 2006.286.02:32:07.27#ibcon#*before write, iclass 3, count 2 2006.286.02:32:07.27#ibcon#enter sib2, iclass 3, count 2 2006.286.02:32:07.27#ibcon#flushed, iclass 3, count 2 2006.286.02:32:07.27#ibcon#about to write, iclass 3, count 2 2006.286.02:32:07.27#ibcon#wrote, iclass 3, count 2 2006.286.02:32:07.27#ibcon#about to read 3, iclass 3, count 2 2006.286.02:32:07.30#ibcon#read 3, iclass 3, count 2 2006.286.02:32:07.30#ibcon#about to read 4, iclass 3, count 2 2006.286.02:32:07.30#ibcon#read 4, iclass 3, count 2 2006.286.02:32:07.30#ibcon#about to read 5, iclass 3, count 2 2006.286.02:32:07.30#ibcon#read 5, iclass 3, count 2 2006.286.02:32:07.30#ibcon#about to read 6, iclass 3, count 2 2006.286.02:32:07.30#ibcon#read 6, iclass 3, count 2 2006.286.02:32:07.30#ibcon#end of sib2, iclass 3, count 2 2006.286.02:32:07.30#ibcon#*after write, iclass 3, count 2 2006.286.02:32:07.30#ibcon#*before return 0, iclass 3, count 2 2006.286.02:32:07.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:32:07.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:32:07.30#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.02:32:07.30#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:07.30#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:32:07.42#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:32:07.42#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:32:07.42#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:32:07.42#ibcon#first serial, iclass 3, count 0 2006.286.02:32:07.42#ibcon#enter sib2, iclass 3, count 0 2006.286.02:32:07.42#ibcon#flushed, iclass 3, count 0 2006.286.02:32:07.42#ibcon#about to write, iclass 3, count 0 2006.286.02:32:07.42#ibcon#wrote, iclass 3, count 0 2006.286.02:32:07.42#ibcon#about to read 3, iclass 3, count 0 2006.286.02:32:07.44#ibcon#read 3, iclass 3, count 0 2006.286.02:32:07.44#ibcon#about to read 4, iclass 3, count 0 2006.286.02:32:07.44#ibcon#read 4, iclass 3, count 0 2006.286.02:32:07.44#ibcon#about to read 5, iclass 3, count 0 2006.286.02:32:07.44#ibcon#read 5, iclass 3, count 0 2006.286.02:32:07.44#ibcon#about to read 6, iclass 3, count 0 2006.286.02:32:07.44#ibcon#read 6, iclass 3, count 0 2006.286.02:32:07.44#ibcon#end of sib2, iclass 3, count 0 2006.286.02:32:07.44#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:32:07.44#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:32:07.44#ibcon#[25=USB\r\n] 2006.286.02:32:07.44#ibcon#*before write, iclass 3, count 0 2006.286.02:32:07.44#ibcon#enter sib2, iclass 3, count 0 2006.286.02:32:07.44#ibcon#flushed, iclass 3, count 0 2006.286.02:32:07.44#ibcon#about to write, iclass 3, count 0 2006.286.02:32:07.44#ibcon#wrote, iclass 3, count 0 2006.286.02:32:07.44#ibcon#about to read 3, iclass 3, count 0 2006.286.02:32:07.47#ibcon#read 3, iclass 3, count 0 2006.286.02:32:07.47#ibcon#about to read 4, iclass 3, count 0 2006.286.02:32:07.47#ibcon#read 4, iclass 3, count 0 2006.286.02:32:07.47#ibcon#about to read 5, iclass 3, count 0 2006.286.02:32:07.47#ibcon#read 5, iclass 3, count 0 2006.286.02:32:07.47#ibcon#about to read 6, iclass 3, count 0 2006.286.02:32:07.47#ibcon#read 6, iclass 3, count 0 2006.286.02:32:07.47#ibcon#end of sib2, iclass 3, count 0 2006.286.02:32:07.47#ibcon#*after write, iclass 3, count 0 2006.286.02:32:07.47#ibcon#*before return 0, iclass 3, count 0 2006.286.02:32:07.47#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:32:07.47#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:32:07.47#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:32:07.47#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:32:07.47$vck44/valo=5,734.99 2006.286.02:32:07.47#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.02:32:07.47#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.02:32:07.47#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:07.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:32:07.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:32:07.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:32:07.47#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:32:07.47#ibcon#first serial, iclass 5, count 0 2006.286.02:32:07.47#ibcon#enter sib2, iclass 5, count 0 2006.286.02:32:07.47#ibcon#flushed, iclass 5, count 0 2006.286.02:32:07.47#ibcon#about to write, iclass 5, count 0 2006.286.02:32:07.47#ibcon#wrote, iclass 5, count 0 2006.286.02:32:07.47#ibcon#about to read 3, iclass 5, count 0 2006.286.02:32:07.49#ibcon#read 3, iclass 5, count 0 2006.286.02:32:07.49#ibcon#about to read 4, iclass 5, count 0 2006.286.02:32:07.49#ibcon#read 4, iclass 5, count 0 2006.286.02:32:07.49#ibcon#about to read 5, iclass 5, count 0 2006.286.02:32:07.49#ibcon#read 5, iclass 5, count 0 2006.286.02:32:07.49#ibcon#about to read 6, iclass 5, count 0 2006.286.02:32:07.49#ibcon#read 6, iclass 5, count 0 2006.286.02:32:07.49#ibcon#end of sib2, iclass 5, count 0 2006.286.02:32:07.49#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:32:07.49#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:32:07.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.02:32:07.49#ibcon#*before write, iclass 5, count 0 2006.286.02:32:07.49#ibcon#enter sib2, iclass 5, count 0 2006.286.02:32:07.49#ibcon#flushed, iclass 5, count 0 2006.286.02:32:07.49#ibcon#about to write, iclass 5, count 0 2006.286.02:32:07.49#ibcon#wrote, iclass 5, count 0 2006.286.02:32:07.49#ibcon#about to read 3, iclass 5, count 0 2006.286.02:32:07.53#ibcon#read 3, iclass 5, count 0 2006.286.02:32:07.53#ibcon#about to read 4, iclass 5, count 0 2006.286.02:32:07.53#ibcon#read 4, iclass 5, count 0 2006.286.02:32:07.53#ibcon#about to read 5, iclass 5, count 0 2006.286.02:32:07.53#ibcon#read 5, iclass 5, count 0 2006.286.02:32:07.53#ibcon#about to read 6, iclass 5, count 0 2006.286.02:32:07.53#ibcon#read 6, iclass 5, count 0 2006.286.02:32:07.53#ibcon#end of sib2, iclass 5, count 0 2006.286.02:32:07.53#ibcon#*after write, iclass 5, count 0 2006.286.02:32:07.53#ibcon#*before return 0, iclass 5, count 0 2006.286.02:32:07.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:32:07.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:32:07.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:32:07.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:32:07.53$vck44/va=5,3 2006.286.02:32:07.53#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.02:32:07.53#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.02:32:07.53#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:07.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:32:07.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:32:07.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:32:07.59#ibcon#enter wrdev, iclass 7, count 2 2006.286.02:32:07.59#ibcon#first serial, iclass 7, count 2 2006.286.02:32:07.59#ibcon#enter sib2, iclass 7, count 2 2006.286.02:32:07.59#ibcon#flushed, iclass 7, count 2 2006.286.02:32:07.59#ibcon#about to write, iclass 7, count 2 2006.286.02:32:07.59#ibcon#wrote, iclass 7, count 2 2006.286.02:32:07.59#ibcon#about to read 3, iclass 7, count 2 2006.286.02:32:07.61#ibcon#read 3, iclass 7, count 2 2006.286.02:32:07.61#ibcon#about to read 4, iclass 7, count 2 2006.286.02:32:07.61#ibcon#read 4, iclass 7, count 2 2006.286.02:32:07.61#ibcon#about to read 5, iclass 7, count 2 2006.286.02:32:07.61#ibcon#read 5, iclass 7, count 2 2006.286.02:32:07.61#ibcon#about to read 6, iclass 7, count 2 2006.286.02:32:07.61#ibcon#read 6, iclass 7, count 2 2006.286.02:32:07.61#ibcon#end of sib2, iclass 7, count 2 2006.286.02:32:07.61#ibcon#*mode == 0, iclass 7, count 2 2006.286.02:32:07.61#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.02:32:07.61#ibcon#[25=AT05-03\r\n] 2006.286.02:32:07.61#ibcon#*before write, iclass 7, count 2 2006.286.02:32:07.61#ibcon#enter sib2, iclass 7, count 2 2006.286.02:32:07.61#ibcon#flushed, iclass 7, count 2 2006.286.02:32:07.61#ibcon#about to write, iclass 7, count 2 2006.286.02:32:07.61#ibcon#wrote, iclass 7, count 2 2006.286.02:32:07.61#ibcon#about to read 3, iclass 7, count 2 2006.286.02:32:07.64#ibcon#read 3, iclass 7, count 2 2006.286.02:32:07.64#ibcon#about to read 4, iclass 7, count 2 2006.286.02:32:07.64#ibcon#read 4, iclass 7, count 2 2006.286.02:32:07.64#ibcon#about to read 5, iclass 7, count 2 2006.286.02:32:07.64#ibcon#read 5, iclass 7, count 2 2006.286.02:32:07.64#ibcon#about to read 6, iclass 7, count 2 2006.286.02:32:07.64#ibcon#read 6, iclass 7, count 2 2006.286.02:32:07.64#ibcon#end of sib2, iclass 7, count 2 2006.286.02:32:07.64#ibcon#*after write, iclass 7, count 2 2006.286.02:32:07.64#ibcon#*before return 0, iclass 7, count 2 2006.286.02:32:07.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:32:07.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:32:07.64#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.02:32:07.64#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:07.64#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:32:07.76#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:32:07.76#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:32:07.76#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:32:07.76#ibcon#first serial, iclass 7, count 0 2006.286.02:32:07.76#ibcon#enter sib2, iclass 7, count 0 2006.286.02:32:07.76#ibcon#flushed, iclass 7, count 0 2006.286.02:32:07.76#ibcon#about to write, iclass 7, count 0 2006.286.02:32:07.76#ibcon#wrote, iclass 7, count 0 2006.286.02:32:07.76#ibcon#about to read 3, iclass 7, count 0 2006.286.02:32:07.78#ibcon#read 3, iclass 7, count 0 2006.286.02:32:07.78#ibcon#about to read 4, iclass 7, count 0 2006.286.02:32:07.78#ibcon#read 4, iclass 7, count 0 2006.286.02:32:07.78#ibcon#about to read 5, iclass 7, count 0 2006.286.02:32:07.78#ibcon#read 5, iclass 7, count 0 2006.286.02:32:07.78#ibcon#about to read 6, iclass 7, count 0 2006.286.02:32:07.78#ibcon#read 6, iclass 7, count 0 2006.286.02:32:07.78#ibcon#end of sib2, iclass 7, count 0 2006.286.02:32:07.78#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:32:07.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:32:07.78#ibcon#[25=USB\r\n] 2006.286.02:32:07.78#ibcon#*before write, iclass 7, count 0 2006.286.02:32:07.78#ibcon#enter sib2, iclass 7, count 0 2006.286.02:32:07.78#ibcon#flushed, iclass 7, count 0 2006.286.02:32:07.78#ibcon#about to write, iclass 7, count 0 2006.286.02:32:07.78#ibcon#wrote, iclass 7, count 0 2006.286.02:32:07.78#ibcon#about to read 3, iclass 7, count 0 2006.286.02:32:07.81#ibcon#read 3, iclass 7, count 0 2006.286.02:32:07.81#ibcon#about to read 4, iclass 7, count 0 2006.286.02:32:07.81#ibcon#read 4, iclass 7, count 0 2006.286.02:32:07.81#ibcon#about to read 5, iclass 7, count 0 2006.286.02:32:07.81#ibcon#read 5, iclass 7, count 0 2006.286.02:32:07.81#ibcon#about to read 6, iclass 7, count 0 2006.286.02:32:07.81#ibcon#read 6, iclass 7, count 0 2006.286.02:32:07.81#ibcon#end of sib2, iclass 7, count 0 2006.286.02:32:07.81#ibcon#*after write, iclass 7, count 0 2006.286.02:32:07.81#ibcon#*before return 0, iclass 7, count 0 2006.286.02:32:07.81#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:32:07.81#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:32:07.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:32:07.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:32:07.81$vck44/valo=6,814.99 2006.286.02:32:07.81#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.02:32:07.81#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.02:32:07.81#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:07.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:32:07.81#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:32:07.81#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:32:07.81#ibcon#enter wrdev, iclass 11, count 0 2006.286.02:32:07.81#ibcon#first serial, iclass 11, count 0 2006.286.02:32:07.81#ibcon#enter sib2, iclass 11, count 0 2006.286.02:32:07.81#ibcon#flushed, iclass 11, count 0 2006.286.02:32:07.81#ibcon#about to write, iclass 11, count 0 2006.286.02:32:07.81#ibcon#wrote, iclass 11, count 0 2006.286.02:32:07.81#ibcon#about to read 3, iclass 11, count 0 2006.286.02:32:07.83#ibcon#read 3, iclass 11, count 0 2006.286.02:32:07.83#ibcon#about to read 4, iclass 11, count 0 2006.286.02:32:07.83#ibcon#read 4, iclass 11, count 0 2006.286.02:32:07.83#ibcon#about to read 5, iclass 11, count 0 2006.286.02:32:07.83#ibcon#read 5, iclass 11, count 0 2006.286.02:32:07.83#ibcon#about to read 6, iclass 11, count 0 2006.286.02:32:07.83#ibcon#read 6, iclass 11, count 0 2006.286.02:32:07.83#ibcon#end of sib2, iclass 11, count 0 2006.286.02:32:07.83#ibcon#*mode == 0, iclass 11, count 0 2006.286.02:32:07.83#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.02:32:07.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.02:32:07.83#ibcon#*before write, iclass 11, count 0 2006.286.02:32:07.83#ibcon#enter sib2, iclass 11, count 0 2006.286.02:32:07.83#ibcon#flushed, iclass 11, count 0 2006.286.02:32:07.83#ibcon#about to write, iclass 11, count 0 2006.286.02:32:07.83#ibcon#wrote, iclass 11, count 0 2006.286.02:32:07.83#ibcon#about to read 3, iclass 11, count 0 2006.286.02:32:07.87#ibcon#read 3, iclass 11, count 0 2006.286.02:32:07.87#ibcon#about to read 4, iclass 11, count 0 2006.286.02:32:07.87#ibcon#read 4, iclass 11, count 0 2006.286.02:32:07.87#ibcon#about to read 5, iclass 11, count 0 2006.286.02:32:07.87#ibcon#read 5, iclass 11, count 0 2006.286.02:32:07.87#ibcon#about to read 6, iclass 11, count 0 2006.286.02:32:07.87#ibcon#read 6, iclass 11, count 0 2006.286.02:32:07.87#ibcon#end of sib2, iclass 11, count 0 2006.286.02:32:07.87#ibcon#*after write, iclass 11, count 0 2006.286.02:32:07.87#ibcon#*before return 0, iclass 11, count 0 2006.286.02:32:07.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:32:07.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:32:07.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.02:32:07.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.02:32:07.87$vck44/va=6,4 2006.286.02:32:07.87#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.02:32:07.87#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.02:32:07.87#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:07.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:32:07.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:32:07.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:32:07.93#ibcon#enter wrdev, iclass 13, count 2 2006.286.02:32:07.93#ibcon#first serial, iclass 13, count 2 2006.286.02:32:07.93#ibcon#enter sib2, iclass 13, count 2 2006.286.02:32:07.93#ibcon#flushed, iclass 13, count 2 2006.286.02:32:07.93#ibcon#about to write, iclass 13, count 2 2006.286.02:32:07.93#ibcon#wrote, iclass 13, count 2 2006.286.02:32:07.93#ibcon#about to read 3, iclass 13, count 2 2006.286.02:32:07.95#ibcon#read 3, iclass 13, count 2 2006.286.02:32:07.95#ibcon#about to read 4, iclass 13, count 2 2006.286.02:32:07.95#ibcon#read 4, iclass 13, count 2 2006.286.02:32:07.95#ibcon#about to read 5, iclass 13, count 2 2006.286.02:32:07.95#ibcon#read 5, iclass 13, count 2 2006.286.02:32:07.95#ibcon#about to read 6, iclass 13, count 2 2006.286.02:32:07.95#ibcon#read 6, iclass 13, count 2 2006.286.02:32:07.95#ibcon#end of sib2, iclass 13, count 2 2006.286.02:32:07.95#ibcon#*mode == 0, iclass 13, count 2 2006.286.02:32:07.95#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.02:32:07.95#ibcon#[25=AT06-04\r\n] 2006.286.02:32:07.95#ibcon#*before write, iclass 13, count 2 2006.286.02:32:07.95#ibcon#enter sib2, iclass 13, count 2 2006.286.02:32:07.95#ibcon#flushed, iclass 13, count 2 2006.286.02:32:07.95#ibcon#about to write, iclass 13, count 2 2006.286.02:32:07.95#ibcon#wrote, iclass 13, count 2 2006.286.02:32:07.95#ibcon#about to read 3, iclass 13, count 2 2006.286.02:32:07.98#ibcon#read 3, iclass 13, count 2 2006.286.02:32:07.98#ibcon#about to read 4, iclass 13, count 2 2006.286.02:32:07.98#ibcon#read 4, iclass 13, count 2 2006.286.02:32:07.98#ibcon#about to read 5, iclass 13, count 2 2006.286.02:32:07.98#ibcon#read 5, iclass 13, count 2 2006.286.02:32:07.98#ibcon#about to read 6, iclass 13, count 2 2006.286.02:32:07.98#ibcon#read 6, iclass 13, count 2 2006.286.02:32:07.98#ibcon#end of sib2, iclass 13, count 2 2006.286.02:32:07.98#ibcon#*after write, iclass 13, count 2 2006.286.02:32:07.98#ibcon#*before return 0, iclass 13, count 2 2006.286.02:32:07.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:32:07.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:32:07.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.02:32:07.98#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:07.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:32:08.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:32:08.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:32:08.10#ibcon#enter wrdev, iclass 13, count 0 2006.286.02:32:08.10#ibcon#first serial, iclass 13, count 0 2006.286.02:32:08.10#ibcon#enter sib2, iclass 13, count 0 2006.286.02:32:08.10#ibcon#flushed, iclass 13, count 0 2006.286.02:32:08.10#ibcon#about to write, iclass 13, count 0 2006.286.02:32:08.10#ibcon#wrote, iclass 13, count 0 2006.286.02:32:08.10#ibcon#about to read 3, iclass 13, count 0 2006.286.02:32:08.12#ibcon#read 3, iclass 13, count 0 2006.286.02:32:08.12#ibcon#about to read 4, iclass 13, count 0 2006.286.02:32:08.12#ibcon#read 4, iclass 13, count 0 2006.286.02:32:08.12#ibcon#about to read 5, iclass 13, count 0 2006.286.02:32:08.12#ibcon#read 5, iclass 13, count 0 2006.286.02:32:08.12#ibcon#about to read 6, iclass 13, count 0 2006.286.02:32:08.12#ibcon#read 6, iclass 13, count 0 2006.286.02:32:08.12#ibcon#end of sib2, iclass 13, count 0 2006.286.02:32:08.12#ibcon#*mode == 0, iclass 13, count 0 2006.286.02:32:08.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.02:32:08.12#ibcon#[25=USB\r\n] 2006.286.02:32:08.12#ibcon#*before write, iclass 13, count 0 2006.286.02:32:08.12#ibcon#enter sib2, iclass 13, count 0 2006.286.02:32:08.12#ibcon#flushed, iclass 13, count 0 2006.286.02:32:08.12#ibcon#about to write, iclass 13, count 0 2006.286.02:32:08.12#ibcon#wrote, iclass 13, count 0 2006.286.02:32:08.12#ibcon#about to read 3, iclass 13, count 0 2006.286.02:32:08.15#ibcon#read 3, iclass 13, count 0 2006.286.02:32:08.15#ibcon#about to read 4, iclass 13, count 0 2006.286.02:32:08.15#ibcon#read 4, iclass 13, count 0 2006.286.02:32:08.15#ibcon#about to read 5, iclass 13, count 0 2006.286.02:32:08.15#ibcon#read 5, iclass 13, count 0 2006.286.02:32:08.15#ibcon#about to read 6, iclass 13, count 0 2006.286.02:32:08.15#ibcon#read 6, iclass 13, count 0 2006.286.02:32:08.15#ibcon#end of sib2, iclass 13, count 0 2006.286.02:32:08.15#ibcon#*after write, iclass 13, count 0 2006.286.02:32:08.15#ibcon#*before return 0, iclass 13, count 0 2006.286.02:32:08.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:32:08.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:32:08.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.02:32:08.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.02:32:08.15$vck44/valo=7,864.99 2006.286.02:32:08.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.02:32:08.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.02:32:08.15#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:08.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:32:08.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:32:08.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:32:08.15#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:32:08.15#ibcon#first serial, iclass 15, count 0 2006.286.02:32:08.15#ibcon#enter sib2, iclass 15, count 0 2006.286.02:32:08.15#ibcon#flushed, iclass 15, count 0 2006.286.02:32:08.15#ibcon#about to write, iclass 15, count 0 2006.286.02:32:08.15#ibcon#wrote, iclass 15, count 0 2006.286.02:32:08.15#ibcon#about to read 3, iclass 15, count 0 2006.286.02:32:08.17#ibcon#read 3, iclass 15, count 0 2006.286.02:32:08.17#ibcon#about to read 4, iclass 15, count 0 2006.286.02:32:08.17#ibcon#read 4, iclass 15, count 0 2006.286.02:32:08.17#ibcon#about to read 5, iclass 15, count 0 2006.286.02:32:08.17#ibcon#read 5, iclass 15, count 0 2006.286.02:32:08.17#ibcon#about to read 6, iclass 15, count 0 2006.286.02:32:08.17#ibcon#read 6, iclass 15, count 0 2006.286.02:32:08.17#ibcon#end of sib2, iclass 15, count 0 2006.286.02:32:08.17#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:32:08.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:32:08.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.02:32:08.17#ibcon#*before write, iclass 15, count 0 2006.286.02:32:08.17#ibcon#enter sib2, iclass 15, count 0 2006.286.02:32:08.17#ibcon#flushed, iclass 15, count 0 2006.286.02:32:08.17#ibcon#about to write, iclass 15, count 0 2006.286.02:32:08.17#ibcon#wrote, iclass 15, count 0 2006.286.02:32:08.17#ibcon#about to read 3, iclass 15, count 0 2006.286.02:32:08.21#ibcon#read 3, iclass 15, count 0 2006.286.02:32:08.21#ibcon#about to read 4, iclass 15, count 0 2006.286.02:32:08.21#ibcon#read 4, iclass 15, count 0 2006.286.02:32:08.21#ibcon#about to read 5, iclass 15, count 0 2006.286.02:32:08.21#ibcon#read 5, iclass 15, count 0 2006.286.02:32:08.21#ibcon#about to read 6, iclass 15, count 0 2006.286.02:32:08.21#ibcon#read 6, iclass 15, count 0 2006.286.02:32:08.21#ibcon#end of sib2, iclass 15, count 0 2006.286.02:32:08.21#ibcon#*after write, iclass 15, count 0 2006.286.02:32:08.21#ibcon#*before return 0, iclass 15, count 0 2006.286.02:32:08.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:32:08.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:32:08.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:32:08.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:32:08.21$vck44/va=7,4 2006.286.02:32:08.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.02:32:08.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.02:32:08.21#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:08.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:32:08.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:32:08.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:32:08.27#ibcon#enter wrdev, iclass 17, count 2 2006.286.02:32:08.27#ibcon#first serial, iclass 17, count 2 2006.286.02:32:08.27#ibcon#enter sib2, iclass 17, count 2 2006.286.02:32:08.27#ibcon#flushed, iclass 17, count 2 2006.286.02:32:08.27#ibcon#about to write, iclass 17, count 2 2006.286.02:32:08.27#ibcon#wrote, iclass 17, count 2 2006.286.02:32:08.27#ibcon#about to read 3, iclass 17, count 2 2006.286.02:32:08.29#ibcon#read 3, iclass 17, count 2 2006.286.02:32:08.29#ibcon#about to read 4, iclass 17, count 2 2006.286.02:32:08.29#ibcon#read 4, iclass 17, count 2 2006.286.02:32:08.29#ibcon#about to read 5, iclass 17, count 2 2006.286.02:32:08.29#ibcon#read 5, iclass 17, count 2 2006.286.02:32:08.29#ibcon#about to read 6, iclass 17, count 2 2006.286.02:32:08.29#ibcon#read 6, iclass 17, count 2 2006.286.02:32:08.29#ibcon#end of sib2, iclass 17, count 2 2006.286.02:32:08.29#ibcon#*mode == 0, iclass 17, count 2 2006.286.02:32:08.29#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.02:32:08.29#ibcon#[25=AT07-04\r\n] 2006.286.02:32:08.29#ibcon#*before write, iclass 17, count 2 2006.286.02:32:08.29#ibcon#enter sib2, iclass 17, count 2 2006.286.02:32:08.29#ibcon#flushed, iclass 17, count 2 2006.286.02:32:08.29#ibcon#about to write, iclass 17, count 2 2006.286.02:32:08.29#ibcon#wrote, iclass 17, count 2 2006.286.02:32:08.29#ibcon#about to read 3, iclass 17, count 2 2006.286.02:32:08.32#ibcon#read 3, iclass 17, count 2 2006.286.02:32:08.32#ibcon#about to read 4, iclass 17, count 2 2006.286.02:32:08.32#ibcon#read 4, iclass 17, count 2 2006.286.02:32:08.32#ibcon#about to read 5, iclass 17, count 2 2006.286.02:32:08.32#ibcon#read 5, iclass 17, count 2 2006.286.02:32:08.32#ibcon#about to read 6, iclass 17, count 2 2006.286.02:32:08.32#ibcon#read 6, iclass 17, count 2 2006.286.02:32:08.32#ibcon#end of sib2, iclass 17, count 2 2006.286.02:32:08.32#ibcon#*after write, iclass 17, count 2 2006.286.02:32:08.32#ibcon#*before return 0, iclass 17, count 2 2006.286.02:32:08.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:32:08.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:32:08.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.02:32:08.32#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:08.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:32:08.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:32:08.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:32:08.44#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:32:08.44#ibcon#first serial, iclass 17, count 0 2006.286.02:32:08.44#ibcon#enter sib2, iclass 17, count 0 2006.286.02:32:08.44#ibcon#flushed, iclass 17, count 0 2006.286.02:32:08.44#ibcon#about to write, iclass 17, count 0 2006.286.02:32:08.44#ibcon#wrote, iclass 17, count 0 2006.286.02:32:08.44#ibcon#about to read 3, iclass 17, count 0 2006.286.02:32:08.46#ibcon#read 3, iclass 17, count 0 2006.286.02:32:08.46#ibcon#about to read 4, iclass 17, count 0 2006.286.02:32:08.46#ibcon#read 4, iclass 17, count 0 2006.286.02:32:08.46#ibcon#about to read 5, iclass 17, count 0 2006.286.02:32:08.46#ibcon#read 5, iclass 17, count 0 2006.286.02:32:08.46#ibcon#about to read 6, iclass 17, count 0 2006.286.02:32:08.46#ibcon#read 6, iclass 17, count 0 2006.286.02:32:08.46#ibcon#end of sib2, iclass 17, count 0 2006.286.02:32:08.46#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:32:08.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:32:08.46#ibcon#[25=USB\r\n] 2006.286.02:32:08.46#ibcon#*before write, iclass 17, count 0 2006.286.02:32:08.46#ibcon#enter sib2, iclass 17, count 0 2006.286.02:32:08.46#ibcon#flushed, iclass 17, count 0 2006.286.02:32:08.46#ibcon#about to write, iclass 17, count 0 2006.286.02:32:08.46#ibcon#wrote, iclass 17, count 0 2006.286.02:32:08.46#ibcon#about to read 3, iclass 17, count 0 2006.286.02:32:08.49#ibcon#read 3, iclass 17, count 0 2006.286.02:32:08.49#ibcon#about to read 4, iclass 17, count 0 2006.286.02:32:08.49#ibcon#read 4, iclass 17, count 0 2006.286.02:32:08.49#ibcon#about to read 5, iclass 17, count 0 2006.286.02:32:08.49#ibcon#read 5, iclass 17, count 0 2006.286.02:32:08.49#ibcon#about to read 6, iclass 17, count 0 2006.286.02:32:08.49#ibcon#read 6, iclass 17, count 0 2006.286.02:32:08.49#ibcon#end of sib2, iclass 17, count 0 2006.286.02:32:08.49#ibcon#*after write, iclass 17, count 0 2006.286.02:32:08.49#ibcon#*before return 0, iclass 17, count 0 2006.286.02:32:08.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:32:08.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:32:08.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:32:08.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:32:08.49$vck44/valo=8,884.99 2006.286.02:32:08.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.02:32:08.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.02:32:08.49#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:08.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:32:08.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:32:08.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:32:08.49#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:32:08.49#ibcon#first serial, iclass 19, count 0 2006.286.02:32:08.49#ibcon#enter sib2, iclass 19, count 0 2006.286.02:32:08.49#ibcon#flushed, iclass 19, count 0 2006.286.02:32:08.49#ibcon#about to write, iclass 19, count 0 2006.286.02:32:08.49#ibcon#wrote, iclass 19, count 0 2006.286.02:32:08.49#ibcon#about to read 3, iclass 19, count 0 2006.286.02:32:08.51#ibcon#read 3, iclass 19, count 0 2006.286.02:32:08.51#ibcon#about to read 4, iclass 19, count 0 2006.286.02:32:08.51#ibcon#read 4, iclass 19, count 0 2006.286.02:32:08.51#ibcon#about to read 5, iclass 19, count 0 2006.286.02:32:08.51#ibcon#read 5, iclass 19, count 0 2006.286.02:32:08.51#ibcon#about to read 6, iclass 19, count 0 2006.286.02:32:08.51#ibcon#read 6, iclass 19, count 0 2006.286.02:32:08.51#ibcon#end of sib2, iclass 19, count 0 2006.286.02:32:08.51#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:32:08.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:32:08.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.02:32:08.51#ibcon#*before write, iclass 19, count 0 2006.286.02:32:08.51#ibcon#enter sib2, iclass 19, count 0 2006.286.02:32:08.51#ibcon#flushed, iclass 19, count 0 2006.286.02:32:08.51#ibcon#about to write, iclass 19, count 0 2006.286.02:32:08.51#ibcon#wrote, iclass 19, count 0 2006.286.02:32:08.51#ibcon#about to read 3, iclass 19, count 0 2006.286.02:32:08.55#ibcon#read 3, iclass 19, count 0 2006.286.02:32:08.55#ibcon#about to read 4, iclass 19, count 0 2006.286.02:32:08.55#ibcon#read 4, iclass 19, count 0 2006.286.02:32:08.55#ibcon#about to read 5, iclass 19, count 0 2006.286.02:32:08.55#ibcon#read 5, iclass 19, count 0 2006.286.02:32:08.55#ibcon#about to read 6, iclass 19, count 0 2006.286.02:32:08.55#ibcon#read 6, iclass 19, count 0 2006.286.02:32:08.55#ibcon#end of sib2, iclass 19, count 0 2006.286.02:32:08.55#ibcon#*after write, iclass 19, count 0 2006.286.02:32:08.55#ibcon#*before return 0, iclass 19, count 0 2006.286.02:32:08.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:32:08.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:32:08.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:32:08.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:32:08.55$vck44/va=8,3 2006.286.02:32:08.55#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.02:32:08.55#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.02:32:08.55#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:08.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:32:08.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:32:08.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:32:08.61#ibcon#enter wrdev, iclass 21, count 2 2006.286.02:32:08.61#ibcon#first serial, iclass 21, count 2 2006.286.02:32:08.61#ibcon#enter sib2, iclass 21, count 2 2006.286.02:32:08.61#ibcon#flushed, iclass 21, count 2 2006.286.02:32:08.61#ibcon#about to write, iclass 21, count 2 2006.286.02:32:08.61#ibcon#wrote, iclass 21, count 2 2006.286.02:32:08.61#ibcon#about to read 3, iclass 21, count 2 2006.286.02:32:08.63#ibcon#read 3, iclass 21, count 2 2006.286.02:32:08.63#ibcon#about to read 4, iclass 21, count 2 2006.286.02:32:08.63#ibcon#read 4, iclass 21, count 2 2006.286.02:32:08.63#ibcon#about to read 5, iclass 21, count 2 2006.286.02:32:08.63#ibcon#read 5, iclass 21, count 2 2006.286.02:32:08.63#ibcon#about to read 6, iclass 21, count 2 2006.286.02:32:08.63#ibcon#read 6, iclass 21, count 2 2006.286.02:32:08.63#ibcon#end of sib2, iclass 21, count 2 2006.286.02:32:08.63#ibcon#*mode == 0, iclass 21, count 2 2006.286.02:32:08.63#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.02:32:08.63#ibcon#[25=AT08-03\r\n] 2006.286.02:32:08.63#ibcon#*before write, iclass 21, count 2 2006.286.02:32:08.63#ibcon#enter sib2, iclass 21, count 2 2006.286.02:32:08.63#ibcon#flushed, iclass 21, count 2 2006.286.02:32:08.63#ibcon#about to write, iclass 21, count 2 2006.286.02:32:08.63#ibcon#wrote, iclass 21, count 2 2006.286.02:32:08.63#ibcon#about to read 3, iclass 21, count 2 2006.286.02:32:08.66#ibcon#read 3, iclass 21, count 2 2006.286.02:32:08.66#ibcon#about to read 4, iclass 21, count 2 2006.286.02:32:08.66#ibcon#read 4, iclass 21, count 2 2006.286.02:32:08.66#ibcon#about to read 5, iclass 21, count 2 2006.286.02:32:08.66#ibcon#read 5, iclass 21, count 2 2006.286.02:32:08.66#ibcon#about to read 6, iclass 21, count 2 2006.286.02:32:08.66#ibcon#read 6, iclass 21, count 2 2006.286.02:32:08.66#ibcon#end of sib2, iclass 21, count 2 2006.286.02:32:08.66#ibcon#*after write, iclass 21, count 2 2006.286.02:32:08.66#ibcon#*before return 0, iclass 21, count 2 2006.286.02:32:08.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:32:08.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:32:08.66#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.02:32:08.66#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:08.66#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:32:08.78#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:32:08.78#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:32:08.78#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:32:08.78#ibcon#first serial, iclass 21, count 0 2006.286.02:32:08.78#ibcon#enter sib2, iclass 21, count 0 2006.286.02:32:08.78#ibcon#flushed, iclass 21, count 0 2006.286.02:32:08.78#ibcon#about to write, iclass 21, count 0 2006.286.02:32:08.78#ibcon#wrote, iclass 21, count 0 2006.286.02:32:08.78#ibcon#about to read 3, iclass 21, count 0 2006.286.02:32:08.80#ibcon#read 3, iclass 21, count 0 2006.286.02:32:08.80#ibcon#about to read 4, iclass 21, count 0 2006.286.02:32:08.80#ibcon#read 4, iclass 21, count 0 2006.286.02:32:08.80#ibcon#about to read 5, iclass 21, count 0 2006.286.02:32:08.80#ibcon#read 5, iclass 21, count 0 2006.286.02:32:08.80#ibcon#about to read 6, iclass 21, count 0 2006.286.02:32:08.80#ibcon#read 6, iclass 21, count 0 2006.286.02:32:08.80#ibcon#end of sib2, iclass 21, count 0 2006.286.02:32:08.80#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:32:08.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:32:08.80#ibcon#[25=USB\r\n] 2006.286.02:32:08.80#ibcon#*before write, iclass 21, count 0 2006.286.02:32:08.80#ibcon#enter sib2, iclass 21, count 0 2006.286.02:32:08.80#ibcon#flushed, iclass 21, count 0 2006.286.02:32:08.80#ibcon#about to write, iclass 21, count 0 2006.286.02:32:08.80#ibcon#wrote, iclass 21, count 0 2006.286.02:32:08.80#ibcon#about to read 3, iclass 21, count 0 2006.286.02:32:08.83#ibcon#read 3, iclass 21, count 0 2006.286.02:32:08.83#ibcon#about to read 4, iclass 21, count 0 2006.286.02:32:08.83#ibcon#read 4, iclass 21, count 0 2006.286.02:32:08.83#ibcon#about to read 5, iclass 21, count 0 2006.286.02:32:08.83#ibcon#read 5, iclass 21, count 0 2006.286.02:32:08.83#ibcon#about to read 6, iclass 21, count 0 2006.286.02:32:08.83#ibcon#read 6, iclass 21, count 0 2006.286.02:32:08.83#ibcon#end of sib2, iclass 21, count 0 2006.286.02:32:08.83#ibcon#*after write, iclass 21, count 0 2006.286.02:32:08.83#ibcon#*before return 0, iclass 21, count 0 2006.286.02:32:08.83#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:32:08.83#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:32:08.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:32:08.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:32:08.83$vck44/vblo=1,629.99 2006.286.02:32:08.83#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.02:32:08.83#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.02:32:08.83#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:08.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:32:08.83#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:32:08.83#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:32:08.83#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:32:08.83#ibcon#first serial, iclass 23, count 0 2006.286.02:32:08.83#ibcon#enter sib2, iclass 23, count 0 2006.286.02:32:08.83#ibcon#flushed, iclass 23, count 0 2006.286.02:32:08.83#ibcon#about to write, iclass 23, count 0 2006.286.02:32:08.83#ibcon#wrote, iclass 23, count 0 2006.286.02:32:08.83#ibcon#about to read 3, iclass 23, count 0 2006.286.02:32:08.85#ibcon#read 3, iclass 23, count 0 2006.286.02:32:08.85#ibcon#about to read 4, iclass 23, count 0 2006.286.02:32:08.85#ibcon#read 4, iclass 23, count 0 2006.286.02:32:08.85#ibcon#about to read 5, iclass 23, count 0 2006.286.02:32:08.85#ibcon#read 5, iclass 23, count 0 2006.286.02:32:08.85#ibcon#about to read 6, iclass 23, count 0 2006.286.02:32:08.85#ibcon#read 6, iclass 23, count 0 2006.286.02:32:08.85#ibcon#end of sib2, iclass 23, count 0 2006.286.02:32:08.85#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:32:08.85#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:32:08.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.02:32:08.85#ibcon#*before write, iclass 23, count 0 2006.286.02:32:08.85#ibcon#enter sib2, iclass 23, count 0 2006.286.02:32:08.85#ibcon#flushed, iclass 23, count 0 2006.286.02:32:08.85#ibcon#about to write, iclass 23, count 0 2006.286.02:32:08.85#ibcon#wrote, iclass 23, count 0 2006.286.02:32:08.85#ibcon#about to read 3, iclass 23, count 0 2006.286.02:32:08.89#ibcon#read 3, iclass 23, count 0 2006.286.02:32:08.89#ibcon#about to read 4, iclass 23, count 0 2006.286.02:32:08.89#ibcon#read 4, iclass 23, count 0 2006.286.02:32:08.89#ibcon#about to read 5, iclass 23, count 0 2006.286.02:32:08.89#ibcon#read 5, iclass 23, count 0 2006.286.02:32:08.89#ibcon#about to read 6, iclass 23, count 0 2006.286.02:32:08.89#ibcon#read 6, iclass 23, count 0 2006.286.02:32:08.89#ibcon#end of sib2, iclass 23, count 0 2006.286.02:32:08.89#ibcon#*after write, iclass 23, count 0 2006.286.02:32:08.89#ibcon#*before return 0, iclass 23, count 0 2006.286.02:32:08.89#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:32:08.89#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:32:08.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:32:08.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:32:08.89$vck44/vb=1,4 2006.286.02:32:08.89#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.02:32:08.89#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.02:32:08.89#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:08.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:32:08.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:32:08.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:32:08.89#ibcon#enter wrdev, iclass 25, count 2 2006.286.02:32:08.89#ibcon#first serial, iclass 25, count 2 2006.286.02:32:08.89#ibcon#enter sib2, iclass 25, count 2 2006.286.02:32:08.89#ibcon#flushed, iclass 25, count 2 2006.286.02:32:08.89#ibcon#about to write, iclass 25, count 2 2006.286.02:32:08.89#ibcon#wrote, iclass 25, count 2 2006.286.02:32:08.89#ibcon#about to read 3, iclass 25, count 2 2006.286.02:32:08.91#ibcon#read 3, iclass 25, count 2 2006.286.02:32:08.91#ibcon#about to read 4, iclass 25, count 2 2006.286.02:32:08.91#ibcon#read 4, iclass 25, count 2 2006.286.02:32:08.91#ibcon#about to read 5, iclass 25, count 2 2006.286.02:32:08.91#ibcon#read 5, iclass 25, count 2 2006.286.02:32:08.91#ibcon#about to read 6, iclass 25, count 2 2006.286.02:32:08.91#ibcon#read 6, iclass 25, count 2 2006.286.02:32:08.91#ibcon#end of sib2, iclass 25, count 2 2006.286.02:32:08.91#ibcon#*mode == 0, iclass 25, count 2 2006.286.02:32:08.91#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.02:32:08.91#ibcon#[27=AT01-04\r\n] 2006.286.02:32:08.91#ibcon#*before write, iclass 25, count 2 2006.286.02:32:08.91#ibcon#enter sib2, iclass 25, count 2 2006.286.02:32:08.91#ibcon#flushed, iclass 25, count 2 2006.286.02:32:08.91#ibcon#about to write, iclass 25, count 2 2006.286.02:32:08.91#ibcon#wrote, iclass 25, count 2 2006.286.02:32:08.91#ibcon#about to read 3, iclass 25, count 2 2006.286.02:32:08.94#ibcon#read 3, iclass 25, count 2 2006.286.02:32:08.94#ibcon#about to read 4, iclass 25, count 2 2006.286.02:32:08.94#ibcon#read 4, iclass 25, count 2 2006.286.02:32:08.94#ibcon#about to read 5, iclass 25, count 2 2006.286.02:32:08.94#ibcon#read 5, iclass 25, count 2 2006.286.02:32:08.94#ibcon#about to read 6, iclass 25, count 2 2006.286.02:32:08.94#ibcon#read 6, iclass 25, count 2 2006.286.02:32:08.94#ibcon#end of sib2, iclass 25, count 2 2006.286.02:32:08.94#ibcon#*after write, iclass 25, count 2 2006.286.02:32:08.94#ibcon#*before return 0, iclass 25, count 2 2006.286.02:32:08.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:32:08.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:32:08.94#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.02:32:08.94#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:08.94#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:32:09.06#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:32:09.06#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:32:09.06#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:32:09.06#ibcon#first serial, iclass 25, count 0 2006.286.02:32:09.06#ibcon#enter sib2, iclass 25, count 0 2006.286.02:32:09.06#ibcon#flushed, iclass 25, count 0 2006.286.02:32:09.06#ibcon#about to write, iclass 25, count 0 2006.286.02:32:09.06#ibcon#wrote, iclass 25, count 0 2006.286.02:32:09.06#ibcon#about to read 3, iclass 25, count 0 2006.286.02:32:09.07#abcon#<5=/04 2.7 5.6 21.41 811015.9\r\n> 2006.286.02:32:09.08#ibcon#read 3, iclass 25, count 0 2006.286.02:32:09.08#ibcon#about to read 4, iclass 25, count 0 2006.286.02:32:09.08#ibcon#read 4, iclass 25, count 0 2006.286.02:32:09.08#ibcon#about to read 5, iclass 25, count 0 2006.286.02:32:09.08#ibcon#read 5, iclass 25, count 0 2006.286.02:32:09.08#ibcon#about to read 6, iclass 25, count 0 2006.286.02:32:09.08#ibcon#read 6, iclass 25, count 0 2006.286.02:32:09.08#ibcon#end of sib2, iclass 25, count 0 2006.286.02:32:09.08#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:32:09.08#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:32:09.08#ibcon#[27=USB\r\n] 2006.286.02:32:09.08#ibcon#*before write, iclass 25, count 0 2006.286.02:32:09.08#ibcon#enter sib2, iclass 25, count 0 2006.286.02:32:09.08#ibcon#flushed, iclass 25, count 0 2006.286.02:32:09.08#ibcon#about to write, iclass 25, count 0 2006.286.02:32:09.08#ibcon#wrote, iclass 25, count 0 2006.286.02:32:09.08#ibcon#about to read 3, iclass 25, count 0 2006.286.02:32:09.09#abcon#{5=INTERFACE CLEAR} 2006.286.02:32:09.11#ibcon#read 3, iclass 25, count 0 2006.286.02:32:09.11#ibcon#about to read 4, iclass 25, count 0 2006.286.02:32:09.11#ibcon#read 4, iclass 25, count 0 2006.286.02:32:09.11#ibcon#about to read 5, iclass 25, count 0 2006.286.02:32:09.11#ibcon#read 5, iclass 25, count 0 2006.286.02:32:09.11#ibcon#about to read 6, iclass 25, count 0 2006.286.02:32:09.11#ibcon#read 6, iclass 25, count 0 2006.286.02:32:09.11#ibcon#end of sib2, iclass 25, count 0 2006.286.02:32:09.11#ibcon#*after write, iclass 25, count 0 2006.286.02:32:09.11#ibcon#*before return 0, iclass 25, count 0 2006.286.02:32:09.11#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:32:09.11#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:32:09.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:32:09.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:32:09.11$vck44/vblo=2,634.99 2006.286.02:32:09.11#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.02:32:09.11#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.02:32:09.11#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:09.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:32:09.11#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:32:09.11#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:32:09.11#ibcon#enter wrdev, iclass 30, count 0 2006.286.02:32:09.11#ibcon#first serial, iclass 30, count 0 2006.286.02:32:09.11#ibcon#enter sib2, iclass 30, count 0 2006.286.02:32:09.11#ibcon#flushed, iclass 30, count 0 2006.286.02:32:09.11#ibcon#about to write, iclass 30, count 0 2006.286.02:32:09.11#ibcon#wrote, iclass 30, count 0 2006.286.02:32:09.11#ibcon#about to read 3, iclass 30, count 0 2006.286.02:32:09.13#ibcon#read 3, iclass 30, count 0 2006.286.02:32:09.13#ibcon#about to read 4, iclass 30, count 0 2006.286.02:32:09.13#ibcon#read 4, iclass 30, count 0 2006.286.02:32:09.13#ibcon#about to read 5, iclass 30, count 0 2006.286.02:32:09.13#ibcon#read 5, iclass 30, count 0 2006.286.02:32:09.13#ibcon#about to read 6, iclass 30, count 0 2006.286.02:32:09.13#ibcon#read 6, iclass 30, count 0 2006.286.02:32:09.13#ibcon#end of sib2, iclass 30, count 0 2006.286.02:32:09.13#ibcon#*mode == 0, iclass 30, count 0 2006.286.02:32:09.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.02:32:09.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.02:32:09.13#ibcon#*before write, iclass 30, count 0 2006.286.02:32:09.13#ibcon#enter sib2, iclass 30, count 0 2006.286.02:32:09.13#ibcon#flushed, iclass 30, count 0 2006.286.02:32:09.13#ibcon#about to write, iclass 30, count 0 2006.286.02:32:09.13#ibcon#wrote, iclass 30, count 0 2006.286.02:32:09.13#ibcon#about to read 3, iclass 30, count 0 2006.286.02:32:09.15#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:32:09.17#ibcon#read 3, iclass 30, count 0 2006.286.02:32:09.17#ibcon#about to read 4, iclass 30, count 0 2006.286.02:32:09.17#ibcon#read 4, iclass 30, count 0 2006.286.02:32:09.17#ibcon#about to read 5, iclass 30, count 0 2006.286.02:32:09.17#ibcon#read 5, iclass 30, count 0 2006.286.02:32:09.17#ibcon#about to read 6, iclass 30, count 0 2006.286.02:32:09.17#ibcon#read 6, iclass 30, count 0 2006.286.02:32:09.17#ibcon#end of sib2, iclass 30, count 0 2006.286.02:32:09.17#ibcon#*after write, iclass 30, count 0 2006.286.02:32:09.17#ibcon#*before return 0, iclass 30, count 0 2006.286.02:32:09.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:32:09.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:32:09.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.02:32:09.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.02:32:09.17$vck44/vb=2,5 2006.286.02:32:09.17#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.02:32:09.17#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.02:32:09.17#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:09.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:32:09.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:32:09.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:32:09.23#ibcon#enter wrdev, iclass 33, count 2 2006.286.02:32:09.23#ibcon#first serial, iclass 33, count 2 2006.286.02:32:09.23#ibcon#enter sib2, iclass 33, count 2 2006.286.02:32:09.23#ibcon#flushed, iclass 33, count 2 2006.286.02:32:09.23#ibcon#about to write, iclass 33, count 2 2006.286.02:32:09.23#ibcon#wrote, iclass 33, count 2 2006.286.02:32:09.23#ibcon#about to read 3, iclass 33, count 2 2006.286.02:32:09.25#ibcon#read 3, iclass 33, count 2 2006.286.02:32:09.25#ibcon#about to read 4, iclass 33, count 2 2006.286.02:32:09.25#ibcon#read 4, iclass 33, count 2 2006.286.02:32:09.25#ibcon#about to read 5, iclass 33, count 2 2006.286.02:32:09.25#ibcon#read 5, iclass 33, count 2 2006.286.02:32:09.25#ibcon#about to read 6, iclass 33, count 2 2006.286.02:32:09.25#ibcon#read 6, iclass 33, count 2 2006.286.02:32:09.25#ibcon#end of sib2, iclass 33, count 2 2006.286.02:32:09.25#ibcon#*mode == 0, iclass 33, count 2 2006.286.02:32:09.25#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.02:32:09.25#ibcon#[27=AT02-05\r\n] 2006.286.02:32:09.25#ibcon#*before write, iclass 33, count 2 2006.286.02:32:09.25#ibcon#enter sib2, iclass 33, count 2 2006.286.02:32:09.25#ibcon#flushed, iclass 33, count 2 2006.286.02:32:09.25#ibcon#about to write, iclass 33, count 2 2006.286.02:32:09.25#ibcon#wrote, iclass 33, count 2 2006.286.02:32:09.25#ibcon#about to read 3, iclass 33, count 2 2006.286.02:32:09.28#ibcon#read 3, iclass 33, count 2 2006.286.02:32:09.28#ibcon#about to read 4, iclass 33, count 2 2006.286.02:32:09.28#ibcon#read 4, iclass 33, count 2 2006.286.02:32:09.28#ibcon#about to read 5, iclass 33, count 2 2006.286.02:32:09.28#ibcon#read 5, iclass 33, count 2 2006.286.02:32:09.28#ibcon#about to read 6, iclass 33, count 2 2006.286.02:32:09.28#ibcon#read 6, iclass 33, count 2 2006.286.02:32:09.28#ibcon#end of sib2, iclass 33, count 2 2006.286.02:32:09.28#ibcon#*after write, iclass 33, count 2 2006.286.02:32:09.28#ibcon#*before return 0, iclass 33, count 2 2006.286.02:32:09.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:32:09.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:32:09.28#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.02:32:09.28#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:09.28#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:32:09.40#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:32:09.40#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:32:09.40#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:32:09.40#ibcon#first serial, iclass 33, count 0 2006.286.02:32:09.40#ibcon#enter sib2, iclass 33, count 0 2006.286.02:32:09.40#ibcon#flushed, iclass 33, count 0 2006.286.02:32:09.40#ibcon#about to write, iclass 33, count 0 2006.286.02:32:09.40#ibcon#wrote, iclass 33, count 0 2006.286.02:32:09.40#ibcon#about to read 3, iclass 33, count 0 2006.286.02:32:09.42#ibcon#read 3, iclass 33, count 0 2006.286.02:32:09.42#ibcon#about to read 4, iclass 33, count 0 2006.286.02:32:09.42#ibcon#read 4, iclass 33, count 0 2006.286.02:32:09.42#ibcon#about to read 5, iclass 33, count 0 2006.286.02:32:09.42#ibcon#read 5, iclass 33, count 0 2006.286.02:32:09.42#ibcon#about to read 6, iclass 33, count 0 2006.286.02:32:09.42#ibcon#read 6, iclass 33, count 0 2006.286.02:32:09.42#ibcon#end of sib2, iclass 33, count 0 2006.286.02:32:09.42#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:32:09.42#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:32:09.42#ibcon#[27=USB\r\n] 2006.286.02:32:09.42#ibcon#*before write, iclass 33, count 0 2006.286.02:32:09.42#ibcon#enter sib2, iclass 33, count 0 2006.286.02:32:09.42#ibcon#flushed, iclass 33, count 0 2006.286.02:32:09.42#ibcon#about to write, iclass 33, count 0 2006.286.02:32:09.42#ibcon#wrote, iclass 33, count 0 2006.286.02:32:09.42#ibcon#about to read 3, iclass 33, count 0 2006.286.02:32:09.45#ibcon#read 3, iclass 33, count 0 2006.286.02:32:09.45#ibcon#about to read 4, iclass 33, count 0 2006.286.02:32:09.45#ibcon#read 4, iclass 33, count 0 2006.286.02:32:09.45#ibcon#about to read 5, iclass 33, count 0 2006.286.02:32:09.45#ibcon#read 5, iclass 33, count 0 2006.286.02:32:09.45#ibcon#about to read 6, iclass 33, count 0 2006.286.02:32:09.45#ibcon#read 6, iclass 33, count 0 2006.286.02:32:09.45#ibcon#end of sib2, iclass 33, count 0 2006.286.02:32:09.45#ibcon#*after write, iclass 33, count 0 2006.286.02:32:09.45#ibcon#*before return 0, iclass 33, count 0 2006.286.02:32:09.45#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:32:09.45#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:32:09.45#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:32:09.45#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:32:09.45$vck44/vblo=3,649.99 2006.286.02:32:09.45#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.02:32:09.45#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.02:32:09.45#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:09.45#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:32:09.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:32:09.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:32:09.45#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:32:09.45#ibcon#first serial, iclass 35, count 0 2006.286.02:32:09.45#ibcon#enter sib2, iclass 35, count 0 2006.286.02:32:09.45#ibcon#flushed, iclass 35, count 0 2006.286.02:32:09.45#ibcon#about to write, iclass 35, count 0 2006.286.02:32:09.45#ibcon#wrote, iclass 35, count 0 2006.286.02:32:09.45#ibcon#about to read 3, iclass 35, count 0 2006.286.02:32:09.47#ibcon#read 3, iclass 35, count 0 2006.286.02:32:09.47#ibcon#about to read 4, iclass 35, count 0 2006.286.02:32:09.47#ibcon#read 4, iclass 35, count 0 2006.286.02:32:09.47#ibcon#about to read 5, iclass 35, count 0 2006.286.02:32:09.47#ibcon#read 5, iclass 35, count 0 2006.286.02:32:09.47#ibcon#about to read 6, iclass 35, count 0 2006.286.02:32:09.47#ibcon#read 6, iclass 35, count 0 2006.286.02:32:09.47#ibcon#end of sib2, iclass 35, count 0 2006.286.02:32:09.47#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:32:09.47#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:32:09.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.02:32:09.47#ibcon#*before write, iclass 35, count 0 2006.286.02:32:09.47#ibcon#enter sib2, iclass 35, count 0 2006.286.02:32:09.47#ibcon#flushed, iclass 35, count 0 2006.286.02:32:09.47#ibcon#about to write, iclass 35, count 0 2006.286.02:32:09.47#ibcon#wrote, iclass 35, count 0 2006.286.02:32:09.47#ibcon#about to read 3, iclass 35, count 0 2006.286.02:32:09.51#ibcon#read 3, iclass 35, count 0 2006.286.02:32:09.51#ibcon#about to read 4, iclass 35, count 0 2006.286.02:32:09.51#ibcon#read 4, iclass 35, count 0 2006.286.02:32:09.51#ibcon#about to read 5, iclass 35, count 0 2006.286.02:32:09.51#ibcon#read 5, iclass 35, count 0 2006.286.02:32:09.51#ibcon#about to read 6, iclass 35, count 0 2006.286.02:32:09.51#ibcon#read 6, iclass 35, count 0 2006.286.02:32:09.51#ibcon#end of sib2, iclass 35, count 0 2006.286.02:32:09.51#ibcon#*after write, iclass 35, count 0 2006.286.02:32:09.51#ibcon#*before return 0, iclass 35, count 0 2006.286.02:32:09.51#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:32:09.51#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:32:09.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:32:09.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:32:09.51$vck44/vb=3,4 2006.286.02:32:09.51#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.02:32:09.51#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.02:32:09.51#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:09.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:32:09.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:32:09.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:32:09.57#ibcon#enter wrdev, iclass 37, count 2 2006.286.02:32:09.57#ibcon#first serial, iclass 37, count 2 2006.286.02:32:09.57#ibcon#enter sib2, iclass 37, count 2 2006.286.02:32:09.57#ibcon#flushed, iclass 37, count 2 2006.286.02:32:09.57#ibcon#about to write, iclass 37, count 2 2006.286.02:32:09.57#ibcon#wrote, iclass 37, count 2 2006.286.02:32:09.57#ibcon#about to read 3, iclass 37, count 2 2006.286.02:32:09.59#ibcon#read 3, iclass 37, count 2 2006.286.02:32:09.59#ibcon#about to read 4, iclass 37, count 2 2006.286.02:32:09.59#ibcon#read 4, iclass 37, count 2 2006.286.02:32:09.59#ibcon#about to read 5, iclass 37, count 2 2006.286.02:32:09.59#ibcon#read 5, iclass 37, count 2 2006.286.02:32:09.59#ibcon#about to read 6, iclass 37, count 2 2006.286.02:32:09.59#ibcon#read 6, iclass 37, count 2 2006.286.02:32:09.59#ibcon#end of sib2, iclass 37, count 2 2006.286.02:32:09.59#ibcon#*mode == 0, iclass 37, count 2 2006.286.02:32:09.59#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.02:32:09.59#ibcon#[27=AT03-04\r\n] 2006.286.02:32:09.59#ibcon#*before write, iclass 37, count 2 2006.286.02:32:09.59#ibcon#enter sib2, iclass 37, count 2 2006.286.02:32:09.59#ibcon#flushed, iclass 37, count 2 2006.286.02:32:09.59#ibcon#about to write, iclass 37, count 2 2006.286.02:32:09.59#ibcon#wrote, iclass 37, count 2 2006.286.02:32:09.59#ibcon#about to read 3, iclass 37, count 2 2006.286.02:32:09.62#ibcon#read 3, iclass 37, count 2 2006.286.02:32:09.62#ibcon#about to read 4, iclass 37, count 2 2006.286.02:32:09.62#ibcon#read 4, iclass 37, count 2 2006.286.02:32:09.62#ibcon#about to read 5, iclass 37, count 2 2006.286.02:32:09.62#ibcon#read 5, iclass 37, count 2 2006.286.02:32:09.62#ibcon#about to read 6, iclass 37, count 2 2006.286.02:32:09.62#ibcon#read 6, iclass 37, count 2 2006.286.02:32:09.62#ibcon#end of sib2, iclass 37, count 2 2006.286.02:32:09.62#ibcon#*after write, iclass 37, count 2 2006.286.02:32:09.62#ibcon#*before return 0, iclass 37, count 2 2006.286.02:32:09.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:32:09.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:32:09.62#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.02:32:09.62#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:09.62#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:32:09.74#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:32:09.74#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:32:09.74#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:32:09.74#ibcon#first serial, iclass 37, count 0 2006.286.02:32:09.74#ibcon#enter sib2, iclass 37, count 0 2006.286.02:32:09.74#ibcon#flushed, iclass 37, count 0 2006.286.02:32:09.74#ibcon#about to write, iclass 37, count 0 2006.286.02:32:09.74#ibcon#wrote, iclass 37, count 0 2006.286.02:32:09.74#ibcon#about to read 3, iclass 37, count 0 2006.286.02:32:09.76#ibcon#read 3, iclass 37, count 0 2006.286.02:32:09.76#ibcon#about to read 4, iclass 37, count 0 2006.286.02:32:09.76#ibcon#read 4, iclass 37, count 0 2006.286.02:32:09.76#ibcon#about to read 5, iclass 37, count 0 2006.286.02:32:09.76#ibcon#read 5, iclass 37, count 0 2006.286.02:32:09.76#ibcon#about to read 6, iclass 37, count 0 2006.286.02:32:09.76#ibcon#read 6, iclass 37, count 0 2006.286.02:32:09.76#ibcon#end of sib2, iclass 37, count 0 2006.286.02:32:09.76#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:32:09.76#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:32:09.76#ibcon#[27=USB\r\n] 2006.286.02:32:09.76#ibcon#*before write, iclass 37, count 0 2006.286.02:32:09.76#ibcon#enter sib2, iclass 37, count 0 2006.286.02:32:09.76#ibcon#flushed, iclass 37, count 0 2006.286.02:32:09.76#ibcon#about to write, iclass 37, count 0 2006.286.02:32:09.76#ibcon#wrote, iclass 37, count 0 2006.286.02:32:09.76#ibcon#about to read 3, iclass 37, count 0 2006.286.02:32:09.79#ibcon#read 3, iclass 37, count 0 2006.286.02:32:09.79#ibcon#about to read 4, iclass 37, count 0 2006.286.02:32:09.79#ibcon#read 4, iclass 37, count 0 2006.286.02:32:09.79#ibcon#about to read 5, iclass 37, count 0 2006.286.02:32:09.79#ibcon#read 5, iclass 37, count 0 2006.286.02:32:09.79#ibcon#about to read 6, iclass 37, count 0 2006.286.02:32:09.79#ibcon#read 6, iclass 37, count 0 2006.286.02:32:09.79#ibcon#end of sib2, iclass 37, count 0 2006.286.02:32:09.79#ibcon#*after write, iclass 37, count 0 2006.286.02:32:09.79#ibcon#*before return 0, iclass 37, count 0 2006.286.02:32:09.79#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:32:09.79#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:32:09.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:32:09.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:32:09.79$vck44/vblo=4,679.99 2006.286.02:32:09.79#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.02:32:09.79#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.02:32:09.79#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:09.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:32:09.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:32:09.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:32:09.79#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:32:09.79#ibcon#first serial, iclass 39, count 0 2006.286.02:32:09.79#ibcon#enter sib2, iclass 39, count 0 2006.286.02:32:09.79#ibcon#flushed, iclass 39, count 0 2006.286.02:32:09.79#ibcon#about to write, iclass 39, count 0 2006.286.02:32:09.79#ibcon#wrote, iclass 39, count 0 2006.286.02:32:09.79#ibcon#about to read 3, iclass 39, count 0 2006.286.02:32:09.81#ibcon#read 3, iclass 39, count 0 2006.286.02:32:09.81#ibcon#about to read 4, iclass 39, count 0 2006.286.02:32:09.81#ibcon#read 4, iclass 39, count 0 2006.286.02:32:09.81#ibcon#about to read 5, iclass 39, count 0 2006.286.02:32:09.81#ibcon#read 5, iclass 39, count 0 2006.286.02:32:09.81#ibcon#about to read 6, iclass 39, count 0 2006.286.02:32:09.81#ibcon#read 6, iclass 39, count 0 2006.286.02:32:09.81#ibcon#end of sib2, iclass 39, count 0 2006.286.02:32:09.81#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:32:09.81#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:32:09.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.02:32:09.81#ibcon#*before write, iclass 39, count 0 2006.286.02:32:09.81#ibcon#enter sib2, iclass 39, count 0 2006.286.02:32:09.81#ibcon#flushed, iclass 39, count 0 2006.286.02:32:09.81#ibcon#about to write, iclass 39, count 0 2006.286.02:32:09.81#ibcon#wrote, iclass 39, count 0 2006.286.02:32:09.81#ibcon#about to read 3, iclass 39, count 0 2006.286.02:32:09.85#ibcon#read 3, iclass 39, count 0 2006.286.02:32:09.85#ibcon#about to read 4, iclass 39, count 0 2006.286.02:32:09.85#ibcon#read 4, iclass 39, count 0 2006.286.02:32:09.85#ibcon#about to read 5, iclass 39, count 0 2006.286.02:32:09.85#ibcon#read 5, iclass 39, count 0 2006.286.02:32:09.85#ibcon#about to read 6, iclass 39, count 0 2006.286.02:32:09.85#ibcon#read 6, iclass 39, count 0 2006.286.02:32:09.85#ibcon#end of sib2, iclass 39, count 0 2006.286.02:32:09.85#ibcon#*after write, iclass 39, count 0 2006.286.02:32:09.85#ibcon#*before return 0, iclass 39, count 0 2006.286.02:32:09.85#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:32:09.85#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:32:09.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:32:09.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:32:09.85$vck44/vb=4,5 2006.286.02:32:09.85#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.02:32:09.85#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.02:32:09.85#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:09.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:32:09.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:32:09.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:32:09.91#ibcon#enter wrdev, iclass 3, count 2 2006.286.02:32:09.91#ibcon#first serial, iclass 3, count 2 2006.286.02:32:09.91#ibcon#enter sib2, iclass 3, count 2 2006.286.02:32:09.91#ibcon#flushed, iclass 3, count 2 2006.286.02:32:09.91#ibcon#about to write, iclass 3, count 2 2006.286.02:32:09.91#ibcon#wrote, iclass 3, count 2 2006.286.02:32:09.91#ibcon#about to read 3, iclass 3, count 2 2006.286.02:32:09.93#ibcon#read 3, iclass 3, count 2 2006.286.02:32:09.93#ibcon#about to read 4, iclass 3, count 2 2006.286.02:32:09.93#ibcon#read 4, iclass 3, count 2 2006.286.02:32:09.93#ibcon#about to read 5, iclass 3, count 2 2006.286.02:32:09.93#ibcon#read 5, iclass 3, count 2 2006.286.02:32:09.93#ibcon#about to read 6, iclass 3, count 2 2006.286.02:32:09.93#ibcon#read 6, iclass 3, count 2 2006.286.02:32:09.93#ibcon#end of sib2, iclass 3, count 2 2006.286.02:32:09.93#ibcon#*mode == 0, iclass 3, count 2 2006.286.02:32:09.93#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.02:32:09.93#ibcon#[27=AT04-05\r\n] 2006.286.02:32:09.93#ibcon#*before write, iclass 3, count 2 2006.286.02:32:09.93#ibcon#enter sib2, iclass 3, count 2 2006.286.02:32:09.93#ibcon#flushed, iclass 3, count 2 2006.286.02:32:09.93#ibcon#about to write, iclass 3, count 2 2006.286.02:32:09.93#ibcon#wrote, iclass 3, count 2 2006.286.02:32:09.93#ibcon#about to read 3, iclass 3, count 2 2006.286.02:32:09.96#ibcon#read 3, iclass 3, count 2 2006.286.02:32:09.96#ibcon#about to read 4, iclass 3, count 2 2006.286.02:32:09.96#ibcon#read 4, iclass 3, count 2 2006.286.02:32:09.96#ibcon#about to read 5, iclass 3, count 2 2006.286.02:32:09.96#ibcon#read 5, iclass 3, count 2 2006.286.02:32:09.96#ibcon#about to read 6, iclass 3, count 2 2006.286.02:32:09.96#ibcon#read 6, iclass 3, count 2 2006.286.02:32:09.96#ibcon#end of sib2, iclass 3, count 2 2006.286.02:32:09.96#ibcon#*after write, iclass 3, count 2 2006.286.02:32:09.96#ibcon#*before return 0, iclass 3, count 2 2006.286.02:32:09.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:32:09.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:32:09.96#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.02:32:09.96#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:09.96#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:32:10.08#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:32:10.08#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:32:10.08#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:32:10.08#ibcon#first serial, iclass 3, count 0 2006.286.02:32:10.08#ibcon#enter sib2, iclass 3, count 0 2006.286.02:32:10.08#ibcon#flushed, iclass 3, count 0 2006.286.02:32:10.08#ibcon#about to write, iclass 3, count 0 2006.286.02:32:10.08#ibcon#wrote, iclass 3, count 0 2006.286.02:32:10.08#ibcon#about to read 3, iclass 3, count 0 2006.286.02:32:10.10#ibcon#read 3, iclass 3, count 0 2006.286.02:32:10.10#ibcon#about to read 4, iclass 3, count 0 2006.286.02:32:10.10#ibcon#read 4, iclass 3, count 0 2006.286.02:32:10.10#ibcon#about to read 5, iclass 3, count 0 2006.286.02:32:10.10#ibcon#read 5, iclass 3, count 0 2006.286.02:32:10.10#ibcon#about to read 6, iclass 3, count 0 2006.286.02:32:10.10#ibcon#read 6, iclass 3, count 0 2006.286.02:32:10.10#ibcon#end of sib2, iclass 3, count 0 2006.286.02:32:10.10#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:32:10.10#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:32:10.10#ibcon#[27=USB\r\n] 2006.286.02:32:10.10#ibcon#*before write, iclass 3, count 0 2006.286.02:32:10.10#ibcon#enter sib2, iclass 3, count 0 2006.286.02:32:10.10#ibcon#flushed, iclass 3, count 0 2006.286.02:32:10.10#ibcon#about to write, iclass 3, count 0 2006.286.02:32:10.10#ibcon#wrote, iclass 3, count 0 2006.286.02:32:10.10#ibcon#about to read 3, iclass 3, count 0 2006.286.02:32:10.13#ibcon#read 3, iclass 3, count 0 2006.286.02:32:10.13#ibcon#about to read 4, iclass 3, count 0 2006.286.02:32:10.13#ibcon#read 4, iclass 3, count 0 2006.286.02:32:10.13#ibcon#about to read 5, iclass 3, count 0 2006.286.02:32:10.13#ibcon#read 5, iclass 3, count 0 2006.286.02:32:10.13#ibcon#about to read 6, iclass 3, count 0 2006.286.02:32:10.13#ibcon#read 6, iclass 3, count 0 2006.286.02:32:10.13#ibcon#end of sib2, iclass 3, count 0 2006.286.02:32:10.13#ibcon#*after write, iclass 3, count 0 2006.286.02:32:10.13#ibcon#*before return 0, iclass 3, count 0 2006.286.02:32:10.13#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:32:10.13#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:32:10.13#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:32:10.13#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:32:10.13$vck44/vblo=5,709.99 2006.286.02:32:10.13#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.02:32:10.13#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.02:32:10.13#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:10.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:32:10.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:32:10.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:32:10.13#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:32:10.13#ibcon#first serial, iclass 5, count 0 2006.286.02:32:10.13#ibcon#enter sib2, iclass 5, count 0 2006.286.02:32:10.13#ibcon#flushed, iclass 5, count 0 2006.286.02:32:10.13#ibcon#about to write, iclass 5, count 0 2006.286.02:32:10.13#ibcon#wrote, iclass 5, count 0 2006.286.02:32:10.13#ibcon#about to read 3, iclass 5, count 0 2006.286.02:32:10.15#ibcon#read 3, iclass 5, count 0 2006.286.02:32:10.15#ibcon#about to read 4, iclass 5, count 0 2006.286.02:32:10.15#ibcon#read 4, iclass 5, count 0 2006.286.02:32:10.15#ibcon#about to read 5, iclass 5, count 0 2006.286.02:32:10.15#ibcon#read 5, iclass 5, count 0 2006.286.02:32:10.15#ibcon#about to read 6, iclass 5, count 0 2006.286.02:32:10.15#ibcon#read 6, iclass 5, count 0 2006.286.02:32:10.15#ibcon#end of sib2, iclass 5, count 0 2006.286.02:32:10.15#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:32:10.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:32:10.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.02:32:10.15#ibcon#*before write, iclass 5, count 0 2006.286.02:32:10.15#ibcon#enter sib2, iclass 5, count 0 2006.286.02:32:10.15#ibcon#flushed, iclass 5, count 0 2006.286.02:32:10.15#ibcon#about to write, iclass 5, count 0 2006.286.02:32:10.15#ibcon#wrote, iclass 5, count 0 2006.286.02:32:10.15#ibcon#about to read 3, iclass 5, count 0 2006.286.02:32:10.19#ibcon#read 3, iclass 5, count 0 2006.286.02:32:10.19#ibcon#about to read 4, iclass 5, count 0 2006.286.02:32:10.19#ibcon#read 4, iclass 5, count 0 2006.286.02:32:10.19#ibcon#about to read 5, iclass 5, count 0 2006.286.02:32:10.19#ibcon#read 5, iclass 5, count 0 2006.286.02:32:10.19#ibcon#about to read 6, iclass 5, count 0 2006.286.02:32:10.19#ibcon#read 6, iclass 5, count 0 2006.286.02:32:10.19#ibcon#end of sib2, iclass 5, count 0 2006.286.02:32:10.19#ibcon#*after write, iclass 5, count 0 2006.286.02:32:10.19#ibcon#*before return 0, iclass 5, count 0 2006.286.02:32:10.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:32:10.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:32:10.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:32:10.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:32:10.19$vck44/vb=5,4 2006.286.02:32:10.19#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.02:32:10.19#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.02:32:10.19#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:10.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:32:10.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:32:10.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:32:10.25#ibcon#enter wrdev, iclass 7, count 2 2006.286.02:32:10.25#ibcon#first serial, iclass 7, count 2 2006.286.02:32:10.25#ibcon#enter sib2, iclass 7, count 2 2006.286.02:32:10.25#ibcon#flushed, iclass 7, count 2 2006.286.02:32:10.25#ibcon#about to write, iclass 7, count 2 2006.286.02:32:10.25#ibcon#wrote, iclass 7, count 2 2006.286.02:32:10.25#ibcon#about to read 3, iclass 7, count 2 2006.286.02:32:10.27#ibcon#read 3, iclass 7, count 2 2006.286.02:32:10.27#ibcon#about to read 4, iclass 7, count 2 2006.286.02:32:10.27#ibcon#read 4, iclass 7, count 2 2006.286.02:32:10.27#ibcon#about to read 5, iclass 7, count 2 2006.286.02:32:10.27#ibcon#read 5, iclass 7, count 2 2006.286.02:32:10.27#ibcon#about to read 6, iclass 7, count 2 2006.286.02:32:10.27#ibcon#read 6, iclass 7, count 2 2006.286.02:32:10.27#ibcon#end of sib2, iclass 7, count 2 2006.286.02:32:10.27#ibcon#*mode == 0, iclass 7, count 2 2006.286.02:32:10.27#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.02:32:10.27#ibcon#[27=AT05-04\r\n] 2006.286.02:32:10.27#ibcon#*before write, iclass 7, count 2 2006.286.02:32:10.27#ibcon#enter sib2, iclass 7, count 2 2006.286.02:32:10.27#ibcon#flushed, iclass 7, count 2 2006.286.02:32:10.27#ibcon#about to write, iclass 7, count 2 2006.286.02:32:10.27#ibcon#wrote, iclass 7, count 2 2006.286.02:32:10.27#ibcon#about to read 3, iclass 7, count 2 2006.286.02:32:10.30#ibcon#read 3, iclass 7, count 2 2006.286.02:32:10.30#ibcon#about to read 4, iclass 7, count 2 2006.286.02:32:10.30#ibcon#read 4, iclass 7, count 2 2006.286.02:32:10.30#ibcon#about to read 5, iclass 7, count 2 2006.286.02:32:10.30#ibcon#read 5, iclass 7, count 2 2006.286.02:32:10.30#ibcon#about to read 6, iclass 7, count 2 2006.286.02:32:10.30#ibcon#read 6, iclass 7, count 2 2006.286.02:32:10.30#ibcon#end of sib2, iclass 7, count 2 2006.286.02:32:10.30#ibcon#*after write, iclass 7, count 2 2006.286.02:32:10.30#ibcon#*before return 0, iclass 7, count 2 2006.286.02:32:10.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:32:10.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:32:10.30#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.02:32:10.30#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:10.30#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:32:10.42#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:32:10.42#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:32:10.42#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:32:10.42#ibcon#first serial, iclass 7, count 0 2006.286.02:32:10.42#ibcon#enter sib2, iclass 7, count 0 2006.286.02:32:10.42#ibcon#flushed, iclass 7, count 0 2006.286.02:32:10.42#ibcon#about to write, iclass 7, count 0 2006.286.02:32:10.42#ibcon#wrote, iclass 7, count 0 2006.286.02:32:10.42#ibcon#about to read 3, iclass 7, count 0 2006.286.02:32:10.44#ibcon#read 3, iclass 7, count 0 2006.286.02:32:10.44#ibcon#about to read 4, iclass 7, count 0 2006.286.02:32:10.44#ibcon#read 4, iclass 7, count 0 2006.286.02:32:10.44#ibcon#about to read 5, iclass 7, count 0 2006.286.02:32:10.44#ibcon#read 5, iclass 7, count 0 2006.286.02:32:10.44#ibcon#about to read 6, iclass 7, count 0 2006.286.02:32:10.44#ibcon#read 6, iclass 7, count 0 2006.286.02:32:10.44#ibcon#end of sib2, iclass 7, count 0 2006.286.02:32:10.44#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:32:10.44#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:32:10.44#ibcon#[27=USB\r\n] 2006.286.02:32:10.44#ibcon#*before write, iclass 7, count 0 2006.286.02:32:10.44#ibcon#enter sib2, iclass 7, count 0 2006.286.02:32:10.44#ibcon#flushed, iclass 7, count 0 2006.286.02:32:10.44#ibcon#about to write, iclass 7, count 0 2006.286.02:32:10.44#ibcon#wrote, iclass 7, count 0 2006.286.02:32:10.44#ibcon#about to read 3, iclass 7, count 0 2006.286.02:32:10.47#ibcon#read 3, iclass 7, count 0 2006.286.02:32:10.47#ibcon#about to read 4, iclass 7, count 0 2006.286.02:32:10.47#ibcon#read 4, iclass 7, count 0 2006.286.02:32:10.47#ibcon#about to read 5, iclass 7, count 0 2006.286.02:32:10.47#ibcon#read 5, iclass 7, count 0 2006.286.02:32:10.47#ibcon#about to read 6, iclass 7, count 0 2006.286.02:32:10.47#ibcon#read 6, iclass 7, count 0 2006.286.02:32:10.47#ibcon#end of sib2, iclass 7, count 0 2006.286.02:32:10.47#ibcon#*after write, iclass 7, count 0 2006.286.02:32:10.47#ibcon#*before return 0, iclass 7, count 0 2006.286.02:32:10.47#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:32:10.47#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:32:10.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:32:10.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:32:10.47$vck44/vblo=6,719.99 2006.286.02:32:10.47#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.02:32:10.47#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.02:32:10.47#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:10.47#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:32:10.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:32:10.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:32:10.47#ibcon#enter wrdev, iclass 11, count 0 2006.286.02:32:10.47#ibcon#first serial, iclass 11, count 0 2006.286.02:32:10.47#ibcon#enter sib2, iclass 11, count 0 2006.286.02:32:10.47#ibcon#flushed, iclass 11, count 0 2006.286.02:32:10.47#ibcon#about to write, iclass 11, count 0 2006.286.02:32:10.47#ibcon#wrote, iclass 11, count 0 2006.286.02:32:10.47#ibcon#about to read 3, iclass 11, count 0 2006.286.02:32:10.49#ibcon#read 3, iclass 11, count 0 2006.286.02:32:10.49#ibcon#about to read 4, iclass 11, count 0 2006.286.02:32:10.49#ibcon#read 4, iclass 11, count 0 2006.286.02:32:10.49#ibcon#about to read 5, iclass 11, count 0 2006.286.02:32:10.49#ibcon#read 5, iclass 11, count 0 2006.286.02:32:10.49#ibcon#about to read 6, iclass 11, count 0 2006.286.02:32:10.49#ibcon#read 6, iclass 11, count 0 2006.286.02:32:10.49#ibcon#end of sib2, iclass 11, count 0 2006.286.02:32:10.49#ibcon#*mode == 0, iclass 11, count 0 2006.286.02:32:10.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.02:32:10.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.02:32:10.49#ibcon#*before write, iclass 11, count 0 2006.286.02:32:10.49#ibcon#enter sib2, iclass 11, count 0 2006.286.02:32:10.49#ibcon#flushed, iclass 11, count 0 2006.286.02:32:10.49#ibcon#about to write, iclass 11, count 0 2006.286.02:32:10.49#ibcon#wrote, iclass 11, count 0 2006.286.02:32:10.49#ibcon#about to read 3, iclass 11, count 0 2006.286.02:32:10.53#ibcon#read 3, iclass 11, count 0 2006.286.02:32:10.53#ibcon#about to read 4, iclass 11, count 0 2006.286.02:32:10.53#ibcon#read 4, iclass 11, count 0 2006.286.02:32:10.53#ibcon#about to read 5, iclass 11, count 0 2006.286.02:32:10.53#ibcon#read 5, iclass 11, count 0 2006.286.02:32:10.53#ibcon#about to read 6, iclass 11, count 0 2006.286.02:32:10.53#ibcon#read 6, iclass 11, count 0 2006.286.02:32:10.53#ibcon#end of sib2, iclass 11, count 0 2006.286.02:32:10.53#ibcon#*after write, iclass 11, count 0 2006.286.02:32:10.53#ibcon#*before return 0, iclass 11, count 0 2006.286.02:32:10.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:32:10.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:32:10.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.02:32:10.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.02:32:10.53$vck44/vb=6,3 2006.286.02:32:10.53#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.02:32:10.53#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.02:32:10.53#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:10.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:32:10.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:32:10.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:32:10.59#ibcon#enter wrdev, iclass 13, count 2 2006.286.02:32:10.59#ibcon#first serial, iclass 13, count 2 2006.286.02:32:10.59#ibcon#enter sib2, iclass 13, count 2 2006.286.02:32:10.59#ibcon#flushed, iclass 13, count 2 2006.286.02:32:10.59#ibcon#about to write, iclass 13, count 2 2006.286.02:32:10.59#ibcon#wrote, iclass 13, count 2 2006.286.02:32:10.59#ibcon#about to read 3, iclass 13, count 2 2006.286.02:32:10.61#ibcon#read 3, iclass 13, count 2 2006.286.02:32:10.61#ibcon#about to read 4, iclass 13, count 2 2006.286.02:32:10.61#ibcon#read 4, iclass 13, count 2 2006.286.02:32:10.61#ibcon#about to read 5, iclass 13, count 2 2006.286.02:32:10.61#ibcon#read 5, iclass 13, count 2 2006.286.02:32:10.61#ibcon#about to read 6, iclass 13, count 2 2006.286.02:32:10.61#ibcon#read 6, iclass 13, count 2 2006.286.02:32:10.61#ibcon#end of sib2, iclass 13, count 2 2006.286.02:32:10.61#ibcon#*mode == 0, iclass 13, count 2 2006.286.02:32:10.61#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.02:32:10.61#ibcon#[27=AT06-03\r\n] 2006.286.02:32:10.61#ibcon#*before write, iclass 13, count 2 2006.286.02:32:10.61#ibcon#enter sib2, iclass 13, count 2 2006.286.02:32:10.61#ibcon#flushed, iclass 13, count 2 2006.286.02:32:10.61#ibcon#about to write, iclass 13, count 2 2006.286.02:32:10.61#ibcon#wrote, iclass 13, count 2 2006.286.02:32:10.61#ibcon#about to read 3, iclass 13, count 2 2006.286.02:32:10.64#ibcon#read 3, iclass 13, count 2 2006.286.02:32:10.64#ibcon#about to read 4, iclass 13, count 2 2006.286.02:32:10.64#ibcon#read 4, iclass 13, count 2 2006.286.02:32:10.64#ibcon#about to read 5, iclass 13, count 2 2006.286.02:32:10.64#ibcon#read 5, iclass 13, count 2 2006.286.02:32:10.64#ibcon#about to read 6, iclass 13, count 2 2006.286.02:32:10.64#ibcon#read 6, iclass 13, count 2 2006.286.02:32:10.64#ibcon#end of sib2, iclass 13, count 2 2006.286.02:32:10.64#ibcon#*after write, iclass 13, count 2 2006.286.02:32:10.64#ibcon#*before return 0, iclass 13, count 2 2006.286.02:32:10.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:32:10.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:32:10.64#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.02:32:10.64#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:10.64#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:32:10.76#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:32:10.76#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:32:10.76#ibcon#enter wrdev, iclass 13, count 0 2006.286.02:32:10.76#ibcon#first serial, iclass 13, count 0 2006.286.02:32:10.76#ibcon#enter sib2, iclass 13, count 0 2006.286.02:32:10.76#ibcon#flushed, iclass 13, count 0 2006.286.02:32:10.76#ibcon#about to write, iclass 13, count 0 2006.286.02:32:10.76#ibcon#wrote, iclass 13, count 0 2006.286.02:32:10.76#ibcon#about to read 3, iclass 13, count 0 2006.286.02:32:10.78#ibcon#read 3, iclass 13, count 0 2006.286.02:32:10.78#ibcon#about to read 4, iclass 13, count 0 2006.286.02:32:10.78#ibcon#read 4, iclass 13, count 0 2006.286.02:32:10.78#ibcon#about to read 5, iclass 13, count 0 2006.286.02:32:10.78#ibcon#read 5, iclass 13, count 0 2006.286.02:32:10.78#ibcon#about to read 6, iclass 13, count 0 2006.286.02:32:10.78#ibcon#read 6, iclass 13, count 0 2006.286.02:32:10.78#ibcon#end of sib2, iclass 13, count 0 2006.286.02:32:10.78#ibcon#*mode == 0, iclass 13, count 0 2006.286.02:32:10.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.02:32:10.78#ibcon#[27=USB\r\n] 2006.286.02:32:10.78#ibcon#*before write, iclass 13, count 0 2006.286.02:32:10.78#ibcon#enter sib2, iclass 13, count 0 2006.286.02:32:10.78#ibcon#flushed, iclass 13, count 0 2006.286.02:32:10.78#ibcon#about to write, iclass 13, count 0 2006.286.02:32:10.78#ibcon#wrote, iclass 13, count 0 2006.286.02:32:10.78#ibcon#about to read 3, iclass 13, count 0 2006.286.02:32:10.81#ibcon#read 3, iclass 13, count 0 2006.286.02:32:10.81#ibcon#about to read 4, iclass 13, count 0 2006.286.02:32:10.81#ibcon#read 4, iclass 13, count 0 2006.286.02:32:10.81#ibcon#about to read 5, iclass 13, count 0 2006.286.02:32:10.81#ibcon#read 5, iclass 13, count 0 2006.286.02:32:10.81#ibcon#about to read 6, iclass 13, count 0 2006.286.02:32:10.81#ibcon#read 6, iclass 13, count 0 2006.286.02:32:10.81#ibcon#end of sib2, iclass 13, count 0 2006.286.02:32:10.81#ibcon#*after write, iclass 13, count 0 2006.286.02:32:10.81#ibcon#*before return 0, iclass 13, count 0 2006.286.02:32:10.81#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:32:10.81#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:32:10.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.02:32:10.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.02:32:10.81$vck44/vblo=7,734.99 2006.286.02:32:10.81#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.02:32:10.81#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.02:32:10.81#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:10.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:32:10.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:32:10.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:32:10.81#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:32:10.81#ibcon#first serial, iclass 15, count 0 2006.286.02:32:10.81#ibcon#enter sib2, iclass 15, count 0 2006.286.02:32:10.81#ibcon#flushed, iclass 15, count 0 2006.286.02:32:10.81#ibcon#about to write, iclass 15, count 0 2006.286.02:32:10.81#ibcon#wrote, iclass 15, count 0 2006.286.02:32:10.81#ibcon#about to read 3, iclass 15, count 0 2006.286.02:32:10.83#ibcon#read 3, iclass 15, count 0 2006.286.02:32:10.83#ibcon#about to read 4, iclass 15, count 0 2006.286.02:32:10.83#ibcon#read 4, iclass 15, count 0 2006.286.02:32:10.83#ibcon#about to read 5, iclass 15, count 0 2006.286.02:32:10.83#ibcon#read 5, iclass 15, count 0 2006.286.02:32:10.83#ibcon#about to read 6, iclass 15, count 0 2006.286.02:32:10.83#ibcon#read 6, iclass 15, count 0 2006.286.02:32:10.83#ibcon#end of sib2, iclass 15, count 0 2006.286.02:32:10.83#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:32:10.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:32:10.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.02:32:10.83#ibcon#*before write, iclass 15, count 0 2006.286.02:32:10.83#ibcon#enter sib2, iclass 15, count 0 2006.286.02:32:10.83#ibcon#flushed, iclass 15, count 0 2006.286.02:32:10.83#ibcon#about to write, iclass 15, count 0 2006.286.02:32:10.83#ibcon#wrote, iclass 15, count 0 2006.286.02:32:10.83#ibcon#about to read 3, iclass 15, count 0 2006.286.02:32:10.87#ibcon#read 3, iclass 15, count 0 2006.286.02:32:10.87#ibcon#about to read 4, iclass 15, count 0 2006.286.02:32:10.87#ibcon#read 4, iclass 15, count 0 2006.286.02:32:10.87#ibcon#about to read 5, iclass 15, count 0 2006.286.02:32:10.87#ibcon#read 5, iclass 15, count 0 2006.286.02:32:10.87#ibcon#about to read 6, iclass 15, count 0 2006.286.02:32:10.87#ibcon#read 6, iclass 15, count 0 2006.286.02:32:10.87#ibcon#end of sib2, iclass 15, count 0 2006.286.02:32:10.87#ibcon#*after write, iclass 15, count 0 2006.286.02:32:10.87#ibcon#*before return 0, iclass 15, count 0 2006.286.02:32:10.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:32:10.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:32:10.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:32:10.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:32:10.87$vck44/vb=7,4 2006.286.02:32:10.87#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.02:32:10.87#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.02:32:10.87#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:10.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:32:10.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:32:10.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:32:10.93#ibcon#enter wrdev, iclass 17, count 2 2006.286.02:32:10.93#ibcon#first serial, iclass 17, count 2 2006.286.02:32:10.93#ibcon#enter sib2, iclass 17, count 2 2006.286.02:32:10.93#ibcon#flushed, iclass 17, count 2 2006.286.02:32:10.93#ibcon#about to write, iclass 17, count 2 2006.286.02:32:10.93#ibcon#wrote, iclass 17, count 2 2006.286.02:32:10.93#ibcon#about to read 3, iclass 17, count 2 2006.286.02:32:10.95#ibcon#read 3, iclass 17, count 2 2006.286.02:32:10.95#ibcon#about to read 4, iclass 17, count 2 2006.286.02:32:10.95#ibcon#read 4, iclass 17, count 2 2006.286.02:32:10.95#ibcon#about to read 5, iclass 17, count 2 2006.286.02:32:10.95#ibcon#read 5, iclass 17, count 2 2006.286.02:32:10.95#ibcon#about to read 6, iclass 17, count 2 2006.286.02:32:10.95#ibcon#read 6, iclass 17, count 2 2006.286.02:32:10.95#ibcon#end of sib2, iclass 17, count 2 2006.286.02:32:10.95#ibcon#*mode == 0, iclass 17, count 2 2006.286.02:32:10.95#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.02:32:10.95#ibcon#[27=AT07-04\r\n] 2006.286.02:32:10.95#ibcon#*before write, iclass 17, count 2 2006.286.02:32:10.95#ibcon#enter sib2, iclass 17, count 2 2006.286.02:32:10.95#ibcon#flushed, iclass 17, count 2 2006.286.02:32:10.95#ibcon#about to write, iclass 17, count 2 2006.286.02:32:10.95#ibcon#wrote, iclass 17, count 2 2006.286.02:32:10.95#ibcon#about to read 3, iclass 17, count 2 2006.286.02:32:10.98#ibcon#read 3, iclass 17, count 2 2006.286.02:32:10.98#ibcon#about to read 4, iclass 17, count 2 2006.286.02:32:10.98#ibcon#read 4, iclass 17, count 2 2006.286.02:32:10.98#ibcon#about to read 5, iclass 17, count 2 2006.286.02:32:10.98#ibcon#read 5, iclass 17, count 2 2006.286.02:32:10.98#ibcon#about to read 6, iclass 17, count 2 2006.286.02:32:10.98#ibcon#read 6, iclass 17, count 2 2006.286.02:32:10.98#ibcon#end of sib2, iclass 17, count 2 2006.286.02:32:10.98#ibcon#*after write, iclass 17, count 2 2006.286.02:32:10.98#ibcon#*before return 0, iclass 17, count 2 2006.286.02:32:10.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:32:10.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:32:10.98#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.02:32:10.98#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:10.98#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:32:11.10#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:32:11.10#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:32:11.10#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:32:11.10#ibcon#first serial, iclass 17, count 0 2006.286.02:32:11.10#ibcon#enter sib2, iclass 17, count 0 2006.286.02:32:11.10#ibcon#flushed, iclass 17, count 0 2006.286.02:32:11.10#ibcon#about to write, iclass 17, count 0 2006.286.02:32:11.10#ibcon#wrote, iclass 17, count 0 2006.286.02:32:11.10#ibcon#about to read 3, iclass 17, count 0 2006.286.02:32:11.12#ibcon#read 3, iclass 17, count 0 2006.286.02:32:11.12#ibcon#about to read 4, iclass 17, count 0 2006.286.02:32:11.12#ibcon#read 4, iclass 17, count 0 2006.286.02:32:11.12#ibcon#about to read 5, iclass 17, count 0 2006.286.02:32:11.12#ibcon#read 5, iclass 17, count 0 2006.286.02:32:11.12#ibcon#about to read 6, iclass 17, count 0 2006.286.02:32:11.12#ibcon#read 6, iclass 17, count 0 2006.286.02:32:11.12#ibcon#end of sib2, iclass 17, count 0 2006.286.02:32:11.12#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:32:11.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:32:11.12#ibcon#[27=USB\r\n] 2006.286.02:32:11.12#ibcon#*before write, iclass 17, count 0 2006.286.02:32:11.12#ibcon#enter sib2, iclass 17, count 0 2006.286.02:32:11.12#ibcon#flushed, iclass 17, count 0 2006.286.02:32:11.12#ibcon#about to write, iclass 17, count 0 2006.286.02:32:11.12#ibcon#wrote, iclass 17, count 0 2006.286.02:32:11.12#ibcon#about to read 3, iclass 17, count 0 2006.286.02:32:11.15#ibcon#read 3, iclass 17, count 0 2006.286.02:32:11.15#ibcon#about to read 4, iclass 17, count 0 2006.286.02:32:11.15#ibcon#read 4, iclass 17, count 0 2006.286.02:32:11.15#ibcon#about to read 5, iclass 17, count 0 2006.286.02:32:11.15#ibcon#read 5, iclass 17, count 0 2006.286.02:32:11.15#ibcon#about to read 6, iclass 17, count 0 2006.286.02:32:11.15#ibcon#read 6, iclass 17, count 0 2006.286.02:32:11.15#ibcon#end of sib2, iclass 17, count 0 2006.286.02:32:11.15#ibcon#*after write, iclass 17, count 0 2006.286.02:32:11.15#ibcon#*before return 0, iclass 17, count 0 2006.286.02:32:11.15#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:32:11.15#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:32:11.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:32:11.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:32:11.15$vck44/vblo=8,744.99 2006.286.02:32:11.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.02:32:11.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.02:32:11.15#ibcon#ireg 17 cls_cnt 0 2006.286.02:32:11.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:32:11.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:32:11.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:32:11.15#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:32:11.15#ibcon#first serial, iclass 19, count 0 2006.286.02:32:11.15#ibcon#enter sib2, iclass 19, count 0 2006.286.02:32:11.15#ibcon#flushed, iclass 19, count 0 2006.286.02:32:11.15#ibcon#about to write, iclass 19, count 0 2006.286.02:32:11.15#ibcon#wrote, iclass 19, count 0 2006.286.02:32:11.15#ibcon#about to read 3, iclass 19, count 0 2006.286.02:32:11.17#ibcon#read 3, iclass 19, count 0 2006.286.02:32:11.17#ibcon#about to read 4, iclass 19, count 0 2006.286.02:32:11.17#ibcon#read 4, iclass 19, count 0 2006.286.02:32:11.17#ibcon#about to read 5, iclass 19, count 0 2006.286.02:32:11.17#ibcon#read 5, iclass 19, count 0 2006.286.02:32:11.17#ibcon#about to read 6, iclass 19, count 0 2006.286.02:32:11.17#ibcon#read 6, iclass 19, count 0 2006.286.02:32:11.17#ibcon#end of sib2, iclass 19, count 0 2006.286.02:32:11.17#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:32:11.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:32:11.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.02:32:11.17#ibcon#*before write, iclass 19, count 0 2006.286.02:32:11.17#ibcon#enter sib2, iclass 19, count 0 2006.286.02:32:11.17#ibcon#flushed, iclass 19, count 0 2006.286.02:32:11.17#ibcon#about to write, iclass 19, count 0 2006.286.02:32:11.17#ibcon#wrote, iclass 19, count 0 2006.286.02:32:11.17#ibcon#about to read 3, iclass 19, count 0 2006.286.02:32:11.21#ibcon#read 3, iclass 19, count 0 2006.286.02:32:11.21#ibcon#about to read 4, iclass 19, count 0 2006.286.02:32:11.21#ibcon#read 4, iclass 19, count 0 2006.286.02:32:11.21#ibcon#about to read 5, iclass 19, count 0 2006.286.02:32:11.21#ibcon#read 5, iclass 19, count 0 2006.286.02:32:11.21#ibcon#about to read 6, iclass 19, count 0 2006.286.02:32:11.21#ibcon#read 6, iclass 19, count 0 2006.286.02:32:11.21#ibcon#end of sib2, iclass 19, count 0 2006.286.02:32:11.21#ibcon#*after write, iclass 19, count 0 2006.286.02:32:11.21#ibcon#*before return 0, iclass 19, count 0 2006.286.02:32:11.21#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:32:11.21#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:32:11.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:32:11.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:32:11.21$vck44/vb=8,4 2006.286.02:32:11.21#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.02:32:11.21#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.02:32:11.21#ibcon#ireg 11 cls_cnt 2 2006.286.02:32:11.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:32:11.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:32:11.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:32:11.27#ibcon#enter wrdev, iclass 21, count 2 2006.286.02:32:11.27#ibcon#first serial, iclass 21, count 2 2006.286.02:32:11.27#ibcon#enter sib2, iclass 21, count 2 2006.286.02:32:11.27#ibcon#flushed, iclass 21, count 2 2006.286.02:32:11.27#ibcon#about to write, iclass 21, count 2 2006.286.02:32:11.27#ibcon#wrote, iclass 21, count 2 2006.286.02:32:11.27#ibcon#about to read 3, iclass 21, count 2 2006.286.02:32:11.29#ibcon#read 3, iclass 21, count 2 2006.286.02:32:11.29#ibcon#about to read 4, iclass 21, count 2 2006.286.02:32:11.29#ibcon#read 4, iclass 21, count 2 2006.286.02:32:11.29#ibcon#about to read 5, iclass 21, count 2 2006.286.02:32:11.29#ibcon#read 5, iclass 21, count 2 2006.286.02:32:11.29#ibcon#about to read 6, iclass 21, count 2 2006.286.02:32:11.29#ibcon#read 6, iclass 21, count 2 2006.286.02:32:11.29#ibcon#end of sib2, iclass 21, count 2 2006.286.02:32:11.29#ibcon#*mode == 0, iclass 21, count 2 2006.286.02:32:11.29#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.02:32:11.29#ibcon#[27=AT08-04\r\n] 2006.286.02:32:11.29#ibcon#*before write, iclass 21, count 2 2006.286.02:32:11.29#ibcon#enter sib2, iclass 21, count 2 2006.286.02:32:11.29#ibcon#flushed, iclass 21, count 2 2006.286.02:32:11.29#ibcon#about to write, iclass 21, count 2 2006.286.02:32:11.29#ibcon#wrote, iclass 21, count 2 2006.286.02:32:11.29#ibcon#about to read 3, iclass 21, count 2 2006.286.02:32:11.32#ibcon#read 3, iclass 21, count 2 2006.286.02:32:11.32#ibcon#about to read 4, iclass 21, count 2 2006.286.02:32:11.32#ibcon#read 4, iclass 21, count 2 2006.286.02:32:11.32#ibcon#about to read 5, iclass 21, count 2 2006.286.02:32:11.32#ibcon#read 5, iclass 21, count 2 2006.286.02:32:11.32#ibcon#about to read 6, iclass 21, count 2 2006.286.02:32:11.32#ibcon#read 6, iclass 21, count 2 2006.286.02:32:11.32#ibcon#end of sib2, iclass 21, count 2 2006.286.02:32:11.32#ibcon#*after write, iclass 21, count 2 2006.286.02:32:11.32#ibcon#*before return 0, iclass 21, count 2 2006.286.02:32:11.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:32:11.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:32:11.32#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.02:32:11.32#ibcon#ireg 7 cls_cnt 0 2006.286.02:32:11.32#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:32:11.44#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:32:11.44#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:32:11.44#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:32:11.44#ibcon#first serial, iclass 21, count 0 2006.286.02:32:11.44#ibcon#enter sib2, iclass 21, count 0 2006.286.02:32:11.44#ibcon#flushed, iclass 21, count 0 2006.286.02:32:11.44#ibcon#about to write, iclass 21, count 0 2006.286.02:32:11.44#ibcon#wrote, iclass 21, count 0 2006.286.02:32:11.44#ibcon#about to read 3, iclass 21, count 0 2006.286.02:32:11.46#ibcon#read 3, iclass 21, count 0 2006.286.02:32:11.46#ibcon#about to read 4, iclass 21, count 0 2006.286.02:32:11.46#ibcon#read 4, iclass 21, count 0 2006.286.02:32:11.46#ibcon#about to read 5, iclass 21, count 0 2006.286.02:32:11.46#ibcon#read 5, iclass 21, count 0 2006.286.02:32:11.46#ibcon#about to read 6, iclass 21, count 0 2006.286.02:32:11.46#ibcon#read 6, iclass 21, count 0 2006.286.02:32:11.46#ibcon#end of sib2, iclass 21, count 0 2006.286.02:32:11.46#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:32:11.46#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:32:11.46#ibcon#[27=USB\r\n] 2006.286.02:32:11.46#ibcon#*before write, iclass 21, count 0 2006.286.02:32:11.46#ibcon#enter sib2, iclass 21, count 0 2006.286.02:32:11.46#ibcon#flushed, iclass 21, count 0 2006.286.02:32:11.46#ibcon#about to write, iclass 21, count 0 2006.286.02:32:11.46#ibcon#wrote, iclass 21, count 0 2006.286.02:32:11.46#ibcon#about to read 3, iclass 21, count 0 2006.286.02:32:11.49#ibcon#read 3, iclass 21, count 0 2006.286.02:32:11.49#ibcon#about to read 4, iclass 21, count 0 2006.286.02:32:11.49#ibcon#read 4, iclass 21, count 0 2006.286.02:32:11.49#ibcon#about to read 5, iclass 21, count 0 2006.286.02:32:11.49#ibcon#read 5, iclass 21, count 0 2006.286.02:32:11.49#ibcon#about to read 6, iclass 21, count 0 2006.286.02:32:11.49#ibcon#read 6, iclass 21, count 0 2006.286.02:32:11.49#ibcon#end of sib2, iclass 21, count 0 2006.286.02:32:11.49#ibcon#*after write, iclass 21, count 0 2006.286.02:32:11.49#ibcon#*before return 0, iclass 21, count 0 2006.286.02:32:11.49#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:32:11.49#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:32:11.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:32:11.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:32:11.49$vck44/vabw=wide 2006.286.02:32:11.49#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.02:32:11.49#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.02:32:11.49#ibcon#ireg 8 cls_cnt 0 2006.286.02:32:11.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:32:11.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:32:11.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:32:11.49#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:32:11.49#ibcon#first serial, iclass 23, count 0 2006.286.02:32:11.49#ibcon#enter sib2, iclass 23, count 0 2006.286.02:32:11.49#ibcon#flushed, iclass 23, count 0 2006.286.02:32:11.49#ibcon#about to write, iclass 23, count 0 2006.286.02:32:11.49#ibcon#wrote, iclass 23, count 0 2006.286.02:32:11.49#ibcon#about to read 3, iclass 23, count 0 2006.286.02:32:11.51#ibcon#read 3, iclass 23, count 0 2006.286.02:32:11.51#ibcon#about to read 4, iclass 23, count 0 2006.286.02:32:11.51#ibcon#read 4, iclass 23, count 0 2006.286.02:32:11.51#ibcon#about to read 5, iclass 23, count 0 2006.286.02:32:11.51#ibcon#read 5, iclass 23, count 0 2006.286.02:32:11.51#ibcon#about to read 6, iclass 23, count 0 2006.286.02:32:11.51#ibcon#read 6, iclass 23, count 0 2006.286.02:32:11.51#ibcon#end of sib2, iclass 23, count 0 2006.286.02:32:11.51#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:32:11.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:32:11.51#ibcon#[25=BW32\r\n] 2006.286.02:32:11.51#ibcon#*before write, iclass 23, count 0 2006.286.02:32:11.51#ibcon#enter sib2, iclass 23, count 0 2006.286.02:32:11.51#ibcon#flushed, iclass 23, count 0 2006.286.02:32:11.51#ibcon#about to write, iclass 23, count 0 2006.286.02:32:11.51#ibcon#wrote, iclass 23, count 0 2006.286.02:32:11.51#ibcon#about to read 3, iclass 23, count 0 2006.286.02:32:11.54#ibcon#read 3, iclass 23, count 0 2006.286.02:32:11.54#ibcon#about to read 4, iclass 23, count 0 2006.286.02:32:11.54#ibcon#read 4, iclass 23, count 0 2006.286.02:32:11.54#ibcon#about to read 5, iclass 23, count 0 2006.286.02:32:11.54#ibcon#read 5, iclass 23, count 0 2006.286.02:32:11.54#ibcon#about to read 6, iclass 23, count 0 2006.286.02:32:11.54#ibcon#read 6, iclass 23, count 0 2006.286.02:32:11.54#ibcon#end of sib2, iclass 23, count 0 2006.286.02:32:11.54#ibcon#*after write, iclass 23, count 0 2006.286.02:32:11.54#ibcon#*before return 0, iclass 23, count 0 2006.286.02:32:11.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:32:11.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:32:11.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:32:11.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:32:11.54$vck44/vbbw=wide 2006.286.02:32:11.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.02:32:11.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.02:32:11.54#ibcon#ireg 8 cls_cnt 0 2006.286.02:32:11.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:32:11.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:32:11.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:32:11.61#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:32:11.61#ibcon#first serial, iclass 25, count 0 2006.286.02:32:11.61#ibcon#enter sib2, iclass 25, count 0 2006.286.02:32:11.61#ibcon#flushed, iclass 25, count 0 2006.286.02:32:11.61#ibcon#about to write, iclass 25, count 0 2006.286.02:32:11.61#ibcon#wrote, iclass 25, count 0 2006.286.02:32:11.61#ibcon#about to read 3, iclass 25, count 0 2006.286.02:32:11.63#ibcon#read 3, iclass 25, count 0 2006.286.02:32:11.63#ibcon#about to read 4, iclass 25, count 0 2006.286.02:32:11.63#ibcon#read 4, iclass 25, count 0 2006.286.02:32:11.63#ibcon#about to read 5, iclass 25, count 0 2006.286.02:32:11.63#ibcon#read 5, iclass 25, count 0 2006.286.02:32:11.63#ibcon#about to read 6, iclass 25, count 0 2006.286.02:32:11.63#ibcon#read 6, iclass 25, count 0 2006.286.02:32:11.63#ibcon#end of sib2, iclass 25, count 0 2006.286.02:32:11.63#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:32:11.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:32:11.63#ibcon#[27=BW32\r\n] 2006.286.02:32:11.63#ibcon#*before write, iclass 25, count 0 2006.286.02:32:11.63#ibcon#enter sib2, iclass 25, count 0 2006.286.02:32:11.63#ibcon#flushed, iclass 25, count 0 2006.286.02:32:11.63#ibcon#about to write, iclass 25, count 0 2006.286.02:32:11.63#ibcon#wrote, iclass 25, count 0 2006.286.02:32:11.63#ibcon#about to read 3, iclass 25, count 0 2006.286.02:32:11.66#ibcon#read 3, iclass 25, count 0 2006.286.02:32:11.66#ibcon#about to read 4, iclass 25, count 0 2006.286.02:32:11.66#ibcon#read 4, iclass 25, count 0 2006.286.02:32:11.66#ibcon#about to read 5, iclass 25, count 0 2006.286.02:32:11.66#ibcon#read 5, iclass 25, count 0 2006.286.02:32:11.66#ibcon#about to read 6, iclass 25, count 0 2006.286.02:32:11.66#ibcon#read 6, iclass 25, count 0 2006.286.02:32:11.66#ibcon#end of sib2, iclass 25, count 0 2006.286.02:32:11.66#ibcon#*after write, iclass 25, count 0 2006.286.02:32:11.66#ibcon#*before return 0, iclass 25, count 0 2006.286.02:32:11.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:32:11.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:32:11.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:32:11.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:32:11.66$setupk4/ifdk4 2006.286.02:32:11.66$ifdk4/lo= 2006.286.02:32:11.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.02:32:11.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.02:32:11.66$ifdk4/patch= 2006.286.02:32:11.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.02:32:11.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.02:32:11.66$setupk4/!*+20s 2006.286.02:32:13.13#trakl#Source acquired 2006.286.02:32:15.13#flagr#flagr/antenna,acquired 2006.286.02:32:19.24#abcon#<5=/04 2.7 5.6 21.41 801015.9\r\n> 2006.286.02:32:19.26#abcon#{5=INTERFACE CLEAR} 2006.286.02:32:19.32#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:32:26.16$setupk4/"tpicd 2006.286.02:32:26.16$setupk4/echo=off 2006.286.02:32:26.16$setupk4/xlog=off 2006.286.02:32:26.16:!2006.286.02:33:01 2006.286.02:33:01.00:preob 2006.286.02:33:01.13/onsource/TRACKING 2006.286.02:33:01.13:!2006.286.02:33:11 2006.286.02:33:11.00:"tape 2006.286.02:33:11.00:"st=record 2006.286.02:33:11.00:data_valid=on 2006.286.02:33:11.00:midob 2006.286.02:33:12.13/onsource/TRACKING 2006.286.02:33:12.13/wx/21.41,1015.8,81 2006.286.02:33:12.20/cable/+6.4988E-03 2006.286.02:33:13.29/va/01,07,usb,yes,32,34 2006.286.02:33:13.29/va/02,06,usb,yes,32,32 2006.286.02:33:13.29/va/03,07,usb,yes,31,33 2006.286.02:33:13.29/va/04,06,usb,yes,33,34 2006.286.02:33:13.29/va/05,03,usb,yes,32,33 2006.286.02:33:13.29/va/06,04,usb,yes,29,28 2006.286.02:33:13.29/va/07,04,usb,yes,30,30 2006.286.02:33:13.29/va/08,03,usb,yes,30,37 2006.286.02:33:13.52/valo/01,524.99,yes,locked 2006.286.02:33:13.52/valo/02,534.99,yes,locked 2006.286.02:33:13.52/valo/03,564.99,yes,locked 2006.286.02:33:13.52/valo/04,624.99,yes,locked 2006.286.02:33:13.52/valo/05,734.99,yes,locked 2006.286.02:33:13.52/valo/06,814.99,yes,locked 2006.286.02:33:13.52/valo/07,864.99,yes,locked 2006.286.02:33:13.52/valo/08,884.99,yes,locked 2006.286.02:33:14.61/vb/01,04,usb,yes,30,28 2006.286.02:33:14.61/vb/02,05,usb,yes,28,28 2006.286.02:33:14.61/vb/03,04,usb,yes,29,32 2006.286.02:33:14.61/vb/04,05,usb,yes,30,29 2006.286.02:33:14.61/vb/05,04,usb,yes,26,28 2006.286.02:33:14.61/vb/06,03,usb,yes,38,33 2006.286.02:33:14.61/vb/07,04,usb,yes,30,30 2006.286.02:33:14.61/vb/08,04,usb,yes,27,31 2006.286.02:33:14.84/vblo/01,629.99,yes,locked 2006.286.02:33:14.84/vblo/02,634.99,yes,locked 2006.286.02:33:14.84/vblo/03,649.99,yes,locked 2006.286.02:33:14.84/vblo/04,679.99,yes,locked 2006.286.02:33:14.84/vblo/05,709.99,yes,locked 2006.286.02:33:14.84/vblo/06,719.99,yes,locked 2006.286.02:33:14.84/vblo/07,734.99,yes,locked 2006.286.02:33:14.84/vblo/08,744.99,yes,locked 2006.286.02:33:14.99/vabw/8 2006.286.02:33:15.14/vbbw/8 2006.286.02:33:15.23/xfe/off,on,12.0 2006.286.02:33:15.61/ifatt/23,28,28,28 2006.286.02:33:16.07/fmout-gps/S +2.77E-07 2006.286.02:33:16.10:!2006.286.02:34:01 2006.286.02:34:01.00:data_valid=off 2006.286.02:34:01.00:"et 2006.286.02:34:01.00:!+3s 2006.286.02:34:04.01:"tape 2006.286.02:34:04.01:postob 2006.286.02:34:04.16/cable/+6.4979E-03 2006.286.02:34:04.16/wx/21.40,1015.8,79 2006.286.02:34:05.08/fmout-gps/S +2.76E-07 2006.286.02:34:05.08:scan_name=286-0239,jd0610,100 2006.286.02:34:05.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.286.02:34:06.14#flagr#flagr/antenna,new-source 2006.286.02:34:06.14:checkk5 2006.286.02:34:06.53/chk_autoobs//k5ts1/ autoobs is running! 2006.286.02:34:06.92/chk_autoobs//k5ts2/ autoobs is running! 2006.286.02:34:07.32/chk_autoobs//k5ts3/ autoobs is running! 2006.286.02:34:07.70/chk_autoobs//k5ts4/ autoobs is running! 2006.286.02:34:08.05/chk_obsdata//k5ts1/T2860233??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.02:34:08.47/chk_obsdata//k5ts2/T2860233??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.02:34:08.84/chk_obsdata//k5ts3/T2860233??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.02:34:09.20/chk_obsdata//k5ts4/T2860233??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.02:34:10.02/k5log//k5ts1_log_newline 2006.286.02:34:11.27/k5log//k5ts2_log_newline 2006.286.02:34:12.03/k5log//k5ts3_log_newline 2006.286.02:34:12.80/k5log//k5ts4_log_newline 2006.286.02:34:12.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.02:34:12.83:setupk4=1 2006.286.02:34:12.83$setupk4/echo=on 2006.286.02:34:12.83$setupk4/pcalon 2006.286.02:34:12.83$pcalon/"no phase cal control is implemented here 2006.286.02:34:12.83$setupk4/"tpicd=stop 2006.286.02:34:12.83$setupk4/"rec=synch_on 2006.286.02:34:12.83$setupk4/"rec_mode=128 2006.286.02:34:12.83$setupk4/!* 2006.286.02:34:12.83$setupk4/recpk4 2006.286.02:34:12.83$recpk4/recpatch= 2006.286.02:34:12.83$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.02:34:12.83$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.02:34:12.83$setupk4/vck44 2006.286.02:34:12.83$vck44/valo=1,524.99 2006.286.02:34:12.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.02:34:12.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.02:34:12.83#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:12.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:34:12.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:34:12.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:34:12.83#ibcon#enter wrdev, iclass 4, count 0 2006.286.02:34:12.83#ibcon#first serial, iclass 4, count 0 2006.286.02:34:12.83#ibcon#enter sib2, iclass 4, count 0 2006.286.02:34:12.83#ibcon#flushed, iclass 4, count 0 2006.286.02:34:12.83#ibcon#about to write, iclass 4, count 0 2006.286.02:34:12.83#ibcon#wrote, iclass 4, count 0 2006.286.02:34:12.83#ibcon#about to read 3, iclass 4, count 0 2006.286.02:34:12.85#ibcon#read 3, iclass 4, count 0 2006.286.02:34:12.85#ibcon#about to read 4, iclass 4, count 0 2006.286.02:34:12.85#ibcon#read 4, iclass 4, count 0 2006.286.02:34:12.85#ibcon#about to read 5, iclass 4, count 0 2006.286.02:34:12.85#ibcon#read 5, iclass 4, count 0 2006.286.02:34:12.85#ibcon#about to read 6, iclass 4, count 0 2006.286.02:34:12.85#ibcon#read 6, iclass 4, count 0 2006.286.02:34:12.85#ibcon#end of sib2, iclass 4, count 0 2006.286.02:34:12.85#ibcon#*mode == 0, iclass 4, count 0 2006.286.02:34:12.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.02:34:12.85#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.02:34:12.85#ibcon#*before write, iclass 4, count 0 2006.286.02:34:12.85#ibcon#enter sib2, iclass 4, count 0 2006.286.02:34:12.85#ibcon#flushed, iclass 4, count 0 2006.286.02:34:12.85#ibcon#about to write, iclass 4, count 0 2006.286.02:34:12.85#ibcon#wrote, iclass 4, count 0 2006.286.02:34:12.85#ibcon#about to read 3, iclass 4, count 0 2006.286.02:34:12.90#ibcon#read 3, iclass 4, count 0 2006.286.02:34:12.90#ibcon#about to read 4, iclass 4, count 0 2006.286.02:34:12.90#ibcon#read 4, iclass 4, count 0 2006.286.02:34:12.90#ibcon#about to read 5, iclass 4, count 0 2006.286.02:34:12.90#ibcon#read 5, iclass 4, count 0 2006.286.02:34:12.90#ibcon#about to read 6, iclass 4, count 0 2006.286.02:34:12.90#ibcon#read 6, iclass 4, count 0 2006.286.02:34:12.90#ibcon#end of sib2, iclass 4, count 0 2006.286.02:34:12.90#ibcon#*after write, iclass 4, count 0 2006.286.02:34:12.90#ibcon#*before return 0, iclass 4, count 0 2006.286.02:34:12.90#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:34:12.90#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:34:12.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.02:34:12.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.02:34:12.90$vck44/va=1,7 2006.286.02:34:12.90#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.02:34:12.90#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.02:34:12.90#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:12.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:34:12.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:34:12.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:34:12.90#ibcon#enter wrdev, iclass 6, count 2 2006.286.02:34:12.90#ibcon#first serial, iclass 6, count 2 2006.286.02:34:12.90#ibcon#enter sib2, iclass 6, count 2 2006.286.02:34:12.90#ibcon#flushed, iclass 6, count 2 2006.286.02:34:12.90#ibcon#about to write, iclass 6, count 2 2006.286.02:34:12.90#ibcon#wrote, iclass 6, count 2 2006.286.02:34:12.90#ibcon#about to read 3, iclass 6, count 2 2006.286.02:34:12.92#ibcon#read 3, iclass 6, count 2 2006.286.02:34:12.92#ibcon#about to read 4, iclass 6, count 2 2006.286.02:34:12.92#ibcon#read 4, iclass 6, count 2 2006.286.02:34:12.92#ibcon#about to read 5, iclass 6, count 2 2006.286.02:34:12.92#ibcon#read 5, iclass 6, count 2 2006.286.02:34:12.92#ibcon#about to read 6, iclass 6, count 2 2006.286.02:34:12.92#ibcon#read 6, iclass 6, count 2 2006.286.02:34:12.92#ibcon#end of sib2, iclass 6, count 2 2006.286.02:34:12.92#ibcon#*mode == 0, iclass 6, count 2 2006.286.02:34:12.92#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.02:34:12.92#ibcon#[25=AT01-07\r\n] 2006.286.02:34:12.92#ibcon#*before write, iclass 6, count 2 2006.286.02:34:12.92#ibcon#enter sib2, iclass 6, count 2 2006.286.02:34:12.92#ibcon#flushed, iclass 6, count 2 2006.286.02:34:12.92#ibcon#about to write, iclass 6, count 2 2006.286.02:34:12.92#ibcon#wrote, iclass 6, count 2 2006.286.02:34:12.92#ibcon#about to read 3, iclass 6, count 2 2006.286.02:34:12.95#ibcon#read 3, iclass 6, count 2 2006.286.02:34:12.95#ibcon#about to read 4, iclass 6, count 2 2006.286.02:34:12.95#ibcon#read 4, iclass 6, count 2 2006.286.02:34:12.95#ibcon#about to read 5, iclass 6, count 2 2006.286.02:34:12.95#ibcon#read 5, iclass 6, count 2 2006.286.02:34:12.95#ibcon#about to read 6, iclass 6, count 2 2006.286.02:34:12.95#ibcon#read 6, iclass 6, count 2 2006.286.02:34:12.95#ibcon#end of sib2, iclass 6, count 2 2006.286.02:34:12.95#ibcon#*after write, iclass 6, count 2 2006.286.02:34:12.95#ibcon#*before return 0, iclass 6, count 2 2006.286.02:34:12.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:34:12.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:34:12.95#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.02:34:12.95#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:12.95#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:34:13.07#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:34:13.07#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:34:13.07#ibcon#enter wrdev, iclass 6, count 0 2006.286.02:34:13.07#ibcon#first serial, iclass 6, count 0 2006.286.02:34:13.07#ibcon#enter sib2, iclass 6, count 0 2006.286.02:34:13.07#ibcon#flushed, iclass 6, count 0 2006.286.02:34:13.07#ibcon#about to write, iclass 6, count 0 2006.286.02:34:13.07#ibcon#wrote, iclass 6, count 0 2006.286.02:34:13.07#ibcon#about to read 3, iclass 6, count 0 2006.286.02:34:13.09#ibcon#read 3, iclass 6, count 0 2006.286.02:34:13.09#ibcon#about to read 4, iclass 6, count 0 2006.286.02:34:13.09#ibcon#read 4, iclass 6, count 0 2006.286.02:34:13.09#ibcon#about to read 5, iclass 6, count 0 2006.286.02:34:13.09#ibcon#read 5, iclass 6, count 0 2006.286.02:34:13.09#ibcon#about to read 6, iclass 6, count 0 2006.286.02:34:13.09#ibcon#read 6, iclass 6, count 0 2006.286.02:34:13.09#ibcon#end of sib2, iclass 6, count 0 2006.286.02:34:13.09#ibcon#*mode == 0, iclass 6, count 0 2006.286.02:34:13.09#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.02:34:13.09#ibcon#[25=USB\r\n] 2006.286.02:34:13.09#ibcon#*before write, iclass 6, count 0 2006.286.02:34:13.09#ibcon#enter sib2, iclass 6, count 0 2006.286.02:34:13.09#ibcon#flushed, iclass 6, count 0 2006.286.02:34:13.09#ibcon#about to write, iclass 6, count 0 2006.286.02:34:13.09#ibcon#wrote, iclass 6, count 0 2006.286.02:34:13.09#ibcon#about to read 3, iclass 6, count 0 2006.286.02:34:13.12#ibcon#read 3, iclass 6, count 0 2006.286.02:34:13.12#ibcon#about to read 4, iclass 6, count 0 2006.286.02:34:13.12#ibcon#read 4, iclass 6, count 0 2006.286.02:34:13.12#ibcon#about to read 5, iclass 6, count 0 2006.286.02:34:13.12#ibcon#read 5, iclass 6, count 0 2006.286.02:34:13.12#ibcon#about to read 6, iclass 6, count 0 2006.286.02:34:13.12#ibcon#read 6, iclass 6, count 0 2006.286.02:34:13.12#ibcon#end of sib2, iclass 6, count 0 2006.286.02:34:13.12#ibcon#*after write, iclass 6, count 0 2006.286.02:34:13.12#ibcon#*before return 0, iclass 6, count 0 2006.286.02:34:13.12#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:34:13.12#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:34:13.12#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.02:34:13.12#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.02:34:13.12$vck44/valo=2,534.99 2006.286.02:34:13.12#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.02:34:13.12#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.02:34:13.12#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:13.12#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:34:13.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:34:13.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:34:13.12#ibcon#enter wrdev, iclass 10, count 0 2006.286.02:34:13.12#ibcon#first serial, iclass 10, count 0 2006.286.02:34:13.12#ibcon#enter sib2, iclass 10, count 0 2006.286.02:34:13.12#ibcon#flushed, iclass 10, count 0 2006.286.02:34:13.12#ibcon#about to write, iclass 10, count 0 2006.286.02:34:13.12#ibcon#wrote, iclass 10, count 0 2006.286.02:34:13.12#ibcon#about to read 3, iclass 10, count 0 2006.286.02:34:13.14#ibcon#read 3, iclass 10, count 0 2006.286.02:34:13.14#ibcon#about to read 4, iclass 10, count 0 2006.286.02:34:13.14#ibcon#read 4, iclass 10, count 0 2006.286.02:34:13.14#ibcon#about to read 5, iclass 10, count 0 2006.286.02:34:13.14#ibcon#read 5, iclass 10, count 0 2006.286.02:34:13.14#ibcon#about to read 6, iclass 10, count 0 2006.286.02:34:13.14#ibcon#read 6, iclass 10, count 0 2006.286.02:34:13.14#ibcon#end of sib2, iclass 10, count 0 2006.286.02:34:13.14#ibcon#*mode == 0, iclass 10, count 0 2006.286.02:34:13.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.02:34:13.14#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.02:34:13.14#ibcon#*before write, iclass 10, count 0 2006.286.02:34:13.14#ibcon#enter sib2, iclass 10, count 0 2006.286.02:34:13.14#ibcon#flushed, iclass 10, count 0 2006.286.02:34:13.14#ibcon#about to write, iclass 10, count 0 2006.286.02:34:13.14#ibcon#wrote, iclass 10, count 0 2006.286.02:34:13.14#ibcon#about to read 3, iclass 10, count 0 2006.286.02:34:13.18#ibcon#read 3, iclass 10, count 0 2006.286.02:34:13.18#ibcon#about to read 4, iclass 10, count 0 2006.286.02:34:13.18#ibcon#read 4, iclass 10, count 0 2006.286.02:34:13.18#ibcon#about to read 5, iclass 10, count 0 2006.286.02:34:13.18#ibcon#read 5, iclass 10, count 0 2006.286.02:34:13.18#ibcon#about to read 6, iclass 10, count 0 2006.286.02:34:13.18#ibcon#read 6, iclass 10, count 0 2006.286.02:34:13.18#ibcon#end of sib2, iclass 10, count 0 2006.286.02:34:13.18#ibcon#*after write, iclass 10, count 0 2006.286.02:34:13.18#ibcon#*before return 0, iclass 10, count 0 2006.286.02:34:13.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:34:13.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:34:13.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.02:34:13.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.02:34:13.18$vck44/va=2,6 2006.286.02:34:13.18#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.02:34:13.18#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.02:34:13.18#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:13.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:34:13.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:34:13.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:34:13.24#ibcon#enter wrdev, iclass 12, count 2 2006.286.02:34:13.24#ibcon#first serial, iclass 12, count 2 2006.286.02:34:13.24#ibcon#enter sib2, iclass 12, count 2 2006.286.02:34:13.24#ibcon#flushed, iclass 12, count 2 2006.286.02:34:13.24#ibcon#about to write, iclass 12, count 2 2006.286.02:34:13.24#ibcon#wrote, iclass 12, count 2 2006.286.02:34:13.24#ibcon#about to read 3, iclass 12, count 2 2006.286.02:34:13.26#ibcon#read 3, iclass 12, count 2 2006.286.02:34:13.26#ibcon#about to read 4, iclass 12, count 2 2006.286.02:34:13.26#ibcon#read 4, iclass 12, count 2 2006.286.02:34:13.26#ibcon#about to read 5, iclass 12, count 2 2006.286.02:34:13.26#ibcon#read 5, iclass 12, count 2 2006.286.02:34:13.26#ibcon#about to read 6, iclass 12, count 2 2006.286.02:34:13.26#ibcon#read 6, iclass 12, count 2 2006.286.02:34:13.26#ibcon#end of sib2, iclass 12, count 2 2006.286.02:34:13.26#ibcon#*mode == 0, iclass 12, count 2 2006.286.02:34:13.26#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.02:34:13.26#ibcon#[25=AT02-06\r\n] 2006.286.02:34:13.26#ibcon#*before write, iclass 12, count 2 2006.286.02:34:13.26#ibcon#enter sib2, iclass 12, count 2 2006.286.02:34:13.26#ibcon#flushed, iclass 12, count 2 2006.286.02:34:13.26#ibcon#about to write, iclass 12, count 2 2006.286.02:34:13.26#ibcon#wrote, iclass 12, count 2 2006.286.02:34:13.26#ibcon#about to read 3, iclass 12, count 2 2006.286.02:34:13.29#ibcon#read 3, iclass 12, count 2 2006.286.02:34:13.29#ibcon#about to read 4, iclass 12, count 2 2006.286.02:34:13.29#ibcon#read 4, iclass 12, count 2 2006.286.02:34:13.29#ibcon#about to read 5, iclass 12, count 2 2006.286.02:34:13.29#ibcon#read 5, iclass 12, count 2 2006.286.02:34:13.29#ibcon#about to read 6, iclass 12, count 2 2006.286.02:34:13.29#ibcon#read 6, iclass 12, count 2 2006.286.02:34:13.29#ibcon#end of sib2, iclass 12, count 2 2006.286.02:34:13.29#ibcon#*after write, iclass 12, count 2 2006.286.02:34:13.29#ibcon#*before return 0, iclass 12, count 2 2006.286.02:34:13.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:34:13.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:34:13.29#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.02:34:13.29#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:13.29#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:34:13.41#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:34:13.41#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:34:13.41#ibcon#enter wrdev, iclass 12, count 0 2006.286.02:34:13.41#ibcon#first serial, iclass 12, count 0 2006.286.02:34:13.41#ibcon#enter sib2, iclass 12, count 0 2006.286.02:34:13.41#ibcon#flushed, iclass 12, count 0 2006.286.02:34:13.41#ibcon#about to write, iclass 12, count 0 2006.286.02:34:13.41#ibcon#wrote, iclass 12, count 0 2006.286.02:34:13.41#ibcon#about to read 3, iclass 12, count 0 2006.286.02:34:13.43#ibcon#read 3, iclass 12, count 0 2006.286.02:34:13.43#ibcon#about to read 4, iclass 12, count 0 2006.286.02:34:13.43#ibcon#read 4, iclass 12, count 0 2006.286.02:34:13.43#ibcon#about to read 5, iclass 12, count 0 2006.286.02:34:13.43#ibcon#read 5, iclass 12, count 0 2006.286.02:34:13.43#ibcon#about to read 6, iclass 12, count 0 2006.286.02:34:13.43#ibcon#read 6, iclass 12, count 0 2006.286.02:34:13.43#ibcon#end of sib2, iclass 12, count 0 2006.286.02:34:13.43#ibcon#*mode == 0, iclass 12, count 0 2006.286.02:34:13.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.02:34:13.43#ibcon#[25=USB\r\n] 2006.286.02:34:13.43#ibcon#*before write, iclass 12, count 0 2006.286.02:34:13.43#ibcon#enter sib2, iclass 12, count 0 2006.286.02:34:13.43#ibcon#flushed, iclass 12, count 0 2006.286.02:34:13.43#ibcon#about to write, iclass 12, count 0 2006.286.02:34:13.43#ibcon#wrote, iclass 12, count 0 2006.286.02:34:13.43#ibcon#about to read 3, iclass 12, count 0 2006.286.02:34:13.46#ibcon#read 3, iclass 12, count 0 2006.286.02:34:13.46#ibcon#about to read 4, iclass 12, count 0 2006.286.02:34:13.46#ibcon#read 4, iclass 12, count 0 2006.286.02:34:13.46#ibcon#about to read 5, iclass 12, count 0 2006.286.02:34:13.46#ibcon#read 5, iclass 12, count 0 2006.286.02:34:13.46#ibcon#about to read 6, iclass 12, count 0 2006.286.02:34:13.46#ibcon#read 6, iclass 12, count 0 2006.286.02:34:13.46#ibcon#end of sib2, iclass 12, count 0 2006.286.02:34:13.46#ibcon#*after write, iclass 12, count 0 2006.286.02:34:13.46#ibcon#*before return 0, iclass 12, count 0 2006.286.02:34:13.46#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:34:13.46#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:34:13.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.02:34:13.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.02:34:13.46$vck44/valo=3,564.99 2006.286.02:34:13.46#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.02:34:13.46#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.02:34:13.46#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:13.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:34:13.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:34:13.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:34:13.46#ibcon#enter wrdev, iclass 14, count 0 2006.286.02:34:13.46#ibcon#first serial, iclass 14, count 0 2006.286.02:34:13.46#ibcon#enter sib2, iclass 14, count 0 2006.286.02:34:13.46#ibcon#flushed, iclass 14, count 0 2006.286.02:34:13.46#ibcon#about to write, iclass 14, count 0 2006.286.02:34:13.46#ibcon#wrote, iclass 14, count 0 2006.286.02:34:13.46#ibcon#about to read 3, iclass 14, count 0 2006.286.02:34:13.48#ibcon#read 3, iclass 14, count 0 2006.286.02:34:13.48#ibcon#about to read 4, iclass 14, count 0 2006.286.02:34:13.48#ibcon#read 4, iclass 14, count 0 2006.286.02:34:13.48#ibcon#about to read 5, iclass 14, count 0 2006.286.02:34:13.48#ibcon#read 5, iclass 14, count 0 2006.286.02:34:13.48#ibcon#about to read 6, iclass 14, count 0 2006.286.02:34:13.48#ibcon#read 6, iclass 14, count 0 2006.286.02:34:13.48#ibcon#end of sib2, iclass 14, count 0 2006.286.02:34:13.48#ibcon#*mode == 0, iclass 14, count 0 2006.286.02:34:13.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.02:34:13.48#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.02:34:13.48#ibcon#*before write, iclass 14, count 0 2006.286.02:34:13.48#ibcon#enter sib2, iclass 14, count 0 2006.286.02:34:13.48#ibcon#flushed, iclass 14, count 0 2006.286.02:34:13.48#ibcon#about to write, iclass 14, count 0 2006.286.02:34:13.48#ibcon#wrote, iclass 14, count 0 2006.286.02:34:13.48#ibcon#about to read 3, iclass 14, count 0 2006.286.02:34:13.52#ibcon#read 3, iclass 14, count 0 2006.286.02:34:13.52#ibcon#about to read 4, iclass 14, count 0 2006.286.02:34:13.52#ibcon#read 4, iclass 14, count 0 2006.286.02:34:13.52#ibcon#about to read 5, iclass 14, count 0 2006.286.02:34:13.52#ibcon#read 5, iclass 14, count 0 2006.286.02:34:13.52#ibcon#about to read 6, iclass 14, count 0 2006.286.02:34:13.52#ibcon#read 6, iclass 14, count 0 2006.286.02:34:13.52#ibcon#end of sib2, iclass 14, count 0 2006.286.02:34:13.52#ibcon#*after write, iclass 14, count 0 2006.286.02:34:13.52#ibcon#*before return 0, iclass 14, count 0 2006.286.02:34:13.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:34:13.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:34:13.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.02:34:13.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.02:34:13.52$vck44/va=3,7 2006.286.02:34:13.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.02:34:13.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.02:34:13.52#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:13.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:34:13.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:34:13.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:34:13.58#ibcon#enter wrdev, iclass 16, count 2 2006.286.02:34:13.58#ibcon#first serial, iclass 16, count 2 2006.286.02:34:13.58#ibcon#enter sib2, iclass 16, count 2 2006.286.02:34:13.58#ibcon#flushed, iclass 16, count 2 2006.286.02:34:13.58#ibcon#about to write, iclass 16, count 2 2006.286.02:34:13.58#ibcon#wrote, iclass 16, count 2 2006.286.02:34:13.58#ibcon#about to read 3, iclass 16, count 2 2006.286.02:34:13.60#ibcon#read 3, iclass 16, count 2 2006.286.02:34:13.60#ibcon#about to read 4, iclass 16, count 2 2006.286.02:34:13.60#ibcon#read 4, iclass 16, count 2 2006.286.02:34:13.60#ibcon#about to read 5, iclass 16, count 2 2006.286.02:34:13.60#ibcon#read 5, iclass 16, count 2 2006.286.02:34:13.60#ibcon#about to read 6, iclass 16, count 2 2006.286.02:34:13.60#ibcon#read 6, iclass 16, count 2 2006.286.02:34:13.60#ibcon#end of sib2, iclass 16, count 2 2006.286.02:34:13.60#ibcon#*mode == 0, iclass 16, count 2 2006.286.02:34:13.60#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.02:34:13.60#ibcon#[25=AT03-07\r\n] 2006.286.02:34:13.60#ibcon#*before write, iclass 16, count 2 2006.286.02:34:13.60#ibcon#enter sib2, iclass 16, count 2 2006.286.02:34:13.60#ibcon#flushed, iclass 16, count 2 2006.286.02:34:13.60#ibcon#about to write, iclass 16, count 2 2006.286.02:34:13.60#ibcon#wrote, iclass 16, count 2 2006.286.02:34:13.60#ibcon#about to read 3, iclass 16, count 2 2006.286.02:34:13.63#ibcon#read 3, iclass 16, count 2 2006.286.02:34:13.63#ibcon#about to read 4, iclass 16, count 2 2006.286.02:34:13.63#ibcon#read 4, iclass 16, count 2 2006.286.02:34:13.63#ibcon#about to read 5, iclass 16, count 2 2006.286.02:34:13.63#ibcon#read 5, iclass 16, count 2 2006.286.02:34:13.63#ibcon#about to read 6, iclass 16, count 2 2006.286.02:34:13.63#ibcon#read 6, iclass 16, count 2 2006.286.02:34:13.63#ibcon#end of sib2, iclass 16, count 2 2006.286.02:34:13.63#ibcon#*after write, iclass 16, count 2 2006.286.02:34:13.63#ibcon#*before return 0, iclass 16, count 2 2006.286.02:34:13.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:34:13.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:34:13.63#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.02:34:13.63#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:13.63#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:34:13.75#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:34:13.75#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:34:13.75#ibcon#enter wrdev, iclass 16, count 0 2006.286.02:34:13.75#ibcon#first serial, iclass 16, count 0 2006.286.02:34:13.75#ibcon#enter sib2, iclass 16, count 0 2006.286.02:34:13.75#ibcon#flushed, iclass 16, count 0 2006.286.02:34:13.75#ibcon#about to write, iclass 16, count 0 2006.286.02:34:13.75#ibcon#wrote, iclass 16, count 0 2006.286.02:34:13.75#ibcon#about to read 3, iclass 16, count 0 2006.286.02:34:13.77#ibcon#read 3, iclass 16, count 0 2006.286.02:34:13.77#ibcon#about to read 4, iclass 16, count 0 2006.286.02:34:13.77#ibcon#read 4, iclass 16, count 0 2006.286.02:34:13.77#ibcon#about to read 5, iclass 16, count 0 2006.286.02:34:13.77#ibcon#read 5, iclass 16, count 0 2006.286.02:34:13.77#ibcon#about to read 6, iclass 16, count 0 2006.286.02:34:13.77#ibcon#read 6, iclass 16, count 0 2006.286.02:34:13.77#ibcon#end of sib2, iclass 16, count 0 2006.286.02:34:13.77#ibcon#*mode == 0, iclass 16, count 0 2006.286.02:34:13.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.02:34:13.77#ibcon#[25=USB\r\n] 2006.286.02:34:13.77#ibcon#*before write, iclass 16, count 0 2006.286.02:34:13.77#ibcon#enter sib2, iclass 16, count 0 2006.286.02:34:13.77#ibcon#flushed, iclass 16, count 0 2006.286.02:34:13.77#ibcon#about to write, iclass 16, count 0 2006.286.02:34:13.77#ibcon#wrote, iclass 16, count 0 2006.286.02:34:13.77#ibcon#about to read 3, iclass 16, count 0 2006.286.02:34:13.80#ibcon#read 3, iclass 16, count 0 2006.286.02:34:13.80#ibcon#about to read 4, iclass 16, count 0 2006.286.02:34:13.80#ibcon#read 4, iclass 16, count 0 2006.286.02:34:13.80#ibcon#about to read 5, iclass 16, count 0 2006.286.02:34:13.80#ibcon#read 5, iclass 16, count 0 2006.286.02:34:13.80#ibcon#about to read 6, iclass 16, count 0 2006.286.02:34:13.80#ibcon#read 6, iclass 16, count 0 2006.286.02:34:13.80#ibcon#end of sib2, iclass 16, count 0 2006.286.02:34:13.80#ibcon#*after write, iclass 16, count 0 2006.286.02:34:13.80#ibcon#*before return 0, iclass 16, count 0 2006.286.02:34:13.80#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:34:13.80#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:34:13.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.02:34:13.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.02:34:13.80$vck44/valo=4,624.99 2006.286.02:34:13.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.02:34:13.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.02:34:13.80#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:13.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:34:13.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:34:13.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:34:13.80#ibcon#enter wrdev, iclass 18, count 0 2006.286.02:34:13.80#ibcon#first serial, iclass 18, count 0 2006.286.02:34:13.80#ibcon#enter sib2, iclass 18, count 0 2006.286.02:34:13.80#ibcon#flushed, iclass 18, count 0 2006.286.02:34:13.80#ibcon#about to write, iclass 18, count 0 2006.286.02:34:13.80#ibcon#wrote, iclass 18, count 0 2006.286.02:34:13.80#ibcon#about to read 3, iclass 18, count 0 2006.286.02:34:13.82#ibcon#read 3, iclass 18, count 0 2006.286.02:34:13.82#ibcon#about to read 4, iclass 18, count 0 2006.286.02:34:13.82#ibcon#read 4, iclass 18, count 0 2006.286.02:34:13.82#ibcon#about to read 5, iclass 18, count 0 2006.286.02:34:13.82#ibcon#read 5, iclass 18, count 0 2006.286.02:34:13.82#ibcon#about to read 6, iclass 18, count 0 2006.286.02:34:13.82#ibcon#read 6, iclass 18, count 0 2006.286.02:34:13.82#ibcon#end of sib2, iclass 18, count 0 2006.286.02:34:13.82#ibcon#*mode == 0, iclass 18, count 0 2006.286.02:34:13.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.02:34:13.82#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.02:34:13.82#ibcon#*before write, iclass 18, count 0 2006.286.02:34:13.82#ibcon#enter sib2, iclass 18, count 0 2006.286.02:34:13.82#ibcon#flushed, iclass 18, count 0 2006.286.02:34:13.82#ibcon#about to write, iclass 18, count 0 2006.286.02:34:13.82#ibcon#wrote, iclass 18, count 0 2006.286.02:34:13.82#ibcon#about to read 3, iclass 18, count 0 2006.286.02:34:13.86#ibcon#read 3, iclass 18, count 0 2006.286.02:34:13.86#ibcon#about to read 4, iclass 18, count 0 2006.286.02:34:13.86#ibcon#read 4, iclass 18, count 0 2006.286.02:34:13.86#ibcon#about to read 5, iclass 18, count 0 2006.286.02:34:13.86#ibcon#read 5, iclass 18, count 0 2006.286.02:34:13.86#ibcon#about to read 6, iclass 18, count 0 2006.286.02:34:13.86#ibcon#read 6, iclass 18, count 0 2006.286.02:34:13.86#ibcon#end of sib2, iclass 18, count 0 2006.286.02:34:13.86#ibcon#*after write, iclass 18, count 0 2006.286.02:34:13.86#ibcon#*before return 0, iclass 18, count 0 2006.286.02:34:13.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:34:13.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:34:13.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.02:34:13.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.02:34:13.86$vck44/va=4,6 2006.286.02:34:13.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.02:34:13.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.02:34:13.86#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:13.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:34:13.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:34:13.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:34:13.92#ibcon#enter wrdev, iclass 20, count 2 2006.286.02:34:13.92#ibcon#first serial, iclass 20, count 2 2006.286.02:34:13.92#ibcon#enter sib2, iclass 20, count 2 2006.286.02:34:13.92#ibcon#flushed, iclass 20, count 2 2006.286.02:34:13.92#ibcon#about to write, iclass 20, count 2 2006.286.02:34:13.92#ibcon#wrote, iclass 20, count 2 2006.286.02:34:13.92#ibcon#about to read 3, iclass 20, count 2 2006.286.02:34:13.94#ibcon#read 3, iclass 20, count 2 2006.286.02:34:13.94#ibcon#about to read 4, iclass 20, count 2 2006.286.02:34:13.94#ibcon#read 4, iclass 20, count 2 2006.286.02:34:13.94#ibcon#about to read 5, iclass 20, count 2 2006.286.02:34:13.94#ibcon#read 5, iclass 20, count 2 2006.286.02:34:13.94#ibcon#about to read 6, iclass 20, count 2 2006.286.02:34:13.94#ibcon#read 6, iclass 20, count 2 2006.286.02:34:13.94#ibcon#end of sib2, iclass 20, count 2 2006.286.02:34:13.94#ibcon#*mode == 0, iclass 20, count 2 2006.286.02:34:13.94#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.02:34:13.94#ibcon#[25=AT04-06\r\n] 2006.286.02:34:13.94#ibcon#*before write, iclass 20, count 2 2006.286.02:34:13.94#ibcon#enter sib2, iclass 20, count 2 2006.286.02:34:13.94#ibcon#flushed, iclass 20, count 2 2006.286.02:34:13.94#ibcon#about to write, iclass 20, count 2 2006.286.02:34:13.94#ibcon#wrote, iclass 20, count 2 2006.286.02:34:13.94#ibcon#about to read 3, iclass 20, count 2 2006.286.02:34:13.97#ibcon#read 3, iclass 20, count 2 2006.286.02:34:13.97#ibcon#about to read 4, iclass 20, count 2 2006.286.02:34:13.97#ibcon#read 4, iclass 20, count 2 2006.286.02:34:13.97#ibcon#about to read 5, iclass 20, count 2 2006.286.02:34:13.97#ibcon#read 5, iclass 20, count 2 2006.286.02:34:13.97#ibcon#about to read 6, iclass 20, count 2 2006.286.02:34:13.97#ibcon#read 6, iclass 20, count 2 2006.286.02:34:13.97#ibcon#end of sib2, iclass 20, count 2 2006.286.02:34:13.97#ibcon#*after write, iclass 20, count 2 2006.286.02:34:13.97#ibcon#*before return 0, iclass 20, count 2 2006.286.02:34:13.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:34:13.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:34:13.97#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.02:34:13.97#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:13.97#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:34:14.09#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:34:14.09#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:34:14.09#ibcon#enter wrdev, iclass 20, count 0 2006.286.02:34:14.09#ibcon#first serial, iclass 20, count 0 2006.286.02:34:14.09#ibcon#enter sib2, iclass 20, count 0 2006.286.02:34:14.09#ibcon#flushed, iclass 20, count 0 2006.286.02:34:14.09#ibcon#about to write, iclass 20, count 0 2006.286.02:34:14.09#ibcon#wrote, iclass 20, count 0 2006.286.02:34:14.09#ibcon#about to read 3, iclass 20, count 0 2006.286.02:34:14.11#ibcon#read 3, iclass 20, count 0 2006.286.02:34:14.11#ibcon#about to read 4, iclass 20, count 0 2006.286.02:34:14.11#ibcon#read 4, iclass 20, count 0 2006.286.02:34:14.11#ibcon#about to read 5, iclass 20, count 0 2006.286.02:34:14.11#ibcon#read 5, iclass 20, count 0 2006.286.02:34:14.11#ibcon#about to read 6, iclass 20, count 0 2006.286.02:34:14.11#ibcon#read 6, iclass 20, count 0 2006.286.02:34:14.11#ibcon#end of sib2, iclass 20, count 0 2006.286.02:34:14.11#ibcon#*mode == 0, iclass 20, count 0 2006.286.02:34:14.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.02:34:14.11#ibcon#[25=USB\r\n] 2006.286.02:34:14.11#ibcon#*before write, iclass 20, count 0 2006.286.02:34:14.11#ibcon#enter sib2, iclass 20, count 0 2006.286.02:34:14.11#ibcon#flushed, iclass 20, count 0 2006.286.02:34:14.11#ibcon#about to write, iclass 20, count 0 2006.286.02:34:14.11#ibcon#wrote, iclass 20, count 0 2006.286.02:34:14.11#ibcon#about to read 3, iclass 20, count 0 2006.286.02:34:14.14#ibcon#read 3, iclass 20, count 0 2006.286.02:34:14.14#ibcon#about to read 4, iclass 20, count 0 2006.286.02:34:14.14#ibcon#read 4, iclass 20, count 0 2006.286.02:34:14.14#ibcon#about to read 5, iclass 20, count 0 2006.286.02:34:14.14#ibcon#read 5, iclass 20, count 0 2006.286.02:34:14.14#ibcon#about to read 6, iclass 20, count 0 2006.286.02:34:14.14#ibcon#read 6, iclass 20, count 0 2006.286.02:34:14.14#ibcon#end of sib2, iclass 20, count 0 2006.286.02:34:14.14#ibcon#*after write, iclass 20, count 0 2006.286.02:34:14.14#ibcon#*before return 0, iclass 20, count 0 2006.286.02:34:14.14#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:34:14.14#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:34:14.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.02:34:14.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.02:34:14.14$vck44/valo=5,734.99 2006.286.02:34:14.14#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.02:34:14.14#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.02:34:14.14#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:14.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:34:14.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:34:14.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:34:14.14#ibcon#enter wrdev, iclass 22, count 0 2006.286.02:34:14.14#ibcon#first serial, iclass 22, count 0 2006.286.02:34:14.14#ibcon#enter sib2, iclass 22, count 0 2006.286.02:34:14.14#ibcon#flushed, iclass 22, count 0 2006.286.02:34:14.14#ibcon#about to write, iclass 22, count 0 2006.286.02:34:14.14#ibcon#wrote, iclass 22, count 0 2006.286.02:34:14.14#ibcon#about to read 3, iclass 22, count 0 2006.286.02:34:14.16#ibcon#read 3, iclass 22, count 0 2006.286.02:34:14.16#ibcon#about to read 4, iclass 22, count 0 2006.286.02:34:14.16#ibcon#read 4, iclass 22, count 0 2006.286.02:34:14.16#ibcon#about to read 5, iclass 22, count 0 2006.286.02:34:14.16#ibcon#read 5, iclass 22, count 0 2006.286.02:34:14.16#ibcon#about to read 6, iclass 22, count 0 2006.286.02:34:14.16#ibcon#read 6, iclass 22, count 0 2006.286.02:34:14.16#ibcon#end of sib2, iclass 22, count 0 2006.286.02:34:14.16#ibcon#*mode == 0, iclass 22, count 0 2006.286.02:34:14.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.02:34:14.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.02:34:14.16#ibcon#*before write, iclass 22, count 0 2006.286.02:34:14.16#ibcon#enter sib2, iclass 22, count 0 2006.286.02:34:14.16#ibcon#flushed, iclass 22, count 0 2006.286.02:34:14.16#ibcon#about to write, iclass 22, count 0 2006.286.02:34:14.16#ibcon#wrote, iclass 22, count 0 2006.286.02:34:14.16#ibcon#about to read 3, iclass 22, count 0 2006.286.02:34:14.20#ibcon#read 3, iclass 22, count 0 2006.286.02:34:14.20#ibcon#about to read 4, iclass 22, count 0 2006.286.02:34:14.20#ibcon#read 4, iclass 22, count 0 2006.286.02:34:14.20#ibcon#about to read 5, iclass 22, count 0 2006.286.02:34:14.20#ibcon#read 5, iclass 22, count 0 2006.286.02:34:14.20#ibcon#about to read 6, iclass 22, count 0 2006.286.02:34:14.20#ibcon#read 6, iclass 22, count 0 2006.286.02:34:14.20#ibcon#end of sib2, iclass 22, count 0 2006.286.02:34:14.20#ibcon#*after write, iclass 22, count 0 2006.286.02:34:14.20#ibcon#*before return 0, iclass 22, count 0 2006.286.02:34:14.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:34:14.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:34:14.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.02:34:14.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.02:34:14.20$vck44/va=5,3 2006.286.02:34:14.20#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.02:34:14.20#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.02:34:14.20#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:14.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:34:14.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:34:14.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:34:14.26#ibcon#enter wrdev, iclass 24, count 2 2006.286.02:34:14.26#ibcon#first serial, iclass 24, count 2 2006.286.02:34:14.26#ibcon#enter sib2, iclass 24, count 2 2006.286.02:34:14.26#ibcon#flushed, iclass 24, count 2 2006.286.02:34:14.26#ibcon#about to write, iclass 24, count 2 2006.286.02:34:14.26#ibcon#wrote, iclass 24, count 2 2006.286.02:34:14.26#ibcon#about to read 3, iclass 24, count 2 2006.286.02:34:14.28#ibcon#read 3, iclass 24, count 2 2006.286.02:34:14.28#ibcon#about to read 4, iclass 24, count 2 2006.286.02:34:14.28#ibcon#read 4, iclass 24, count 2 2006.286.02:34:14.28#ibcon#about to read 5, iclass 24, count 2 2006.286.02:34:14.28#ibcon#read 5, iclass 24, count 2 2006.286.02:34:14.28#ibcon#about to read 6, iclass 24, count 2 2006.286.02:34:14.28#ibcon#read 6, iclass 24, count 2 2006.286.02:34:14.28#ibcon#end of sib2, iclass 24, count 2 2006.286.02:34:14.28#ibcon#*mode == 0, iclass 24, count 2 2006.286.02:34:14.28#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.02:34:14.28#ibcon#[25=AT05-03\r\n] 2006.286.02:34:14.28#ibcon#*before write, iclass 24, count 2 2006.286.02:34:14.28#ibcon#enter sib2, iclass 24, count 2 2006.286.02:34:14.28#ibcon#flushed, iclass 24, count 2 2006.286.02:34:14.28#ibcon#about to write, iclass 24, count 2 2006.286.02:34:14.28#ibcon#wrote, iclass 24, count 2 2006.286.02:34:14.28#ibcon#about to read 3, iclass 24, count 2 2006.286.02:34:14.31#ibcon#read 3, iclass 24, count 2 2006.286.02:34:14.31#ibcon#about to read 4, iclass 24, count 2 2006.286.02:34:14.31#ibcon#read 4, iclass 24, count 2 2006.286.02:34:14.31#ibcon#about to read 5, iclass 24, count 2 2006.286.02:34:14.31#ibcon#read 5, iclass 24, count 2 2006.286.02:34:14.31#ibcon#about to read 6, iclass 24, count 2 2006.286.02:34:14.31#ibcon#read 6, iclass 24, count 2 2006.286.02:34:14.31#ibcon#end of sib2, iclass 24, count 2 2006.286.02:34:14.31#ibcon#*after write, iclass 24, count 2 2006.286.02:34:14.31#ibcon#*before return 0, iclass 24, count 2 2006.286.02:34:14.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:34:14.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:34:14.31#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.02:34:14.31#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:14.31#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:34:14.43#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:34:14.43#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:34:14.43#ibcon#enter wrdev, iclass 24, count 0 2006.286.02:34:14.43#ibcon#first serial, iclass 24, count 0 2006.286.02:34:14.43#ibcon#enter sib2, iclass 24, count 0 2006.286.02:34:14.43#ibcon#flushed, iclass 24, count 0 2006.286.02:34:14.43#ibcon#about to write, iclass 24, count 0 2006.286.02:34:14.43#ibcon#wrote, iclass 24, count 0 2006.286.02:34:14.43#ibcon#about to read 3, iclass 24, count 0 2006.286.02:34:14.45#ibcon#read 3, iclass 24, count 0 2006.286.02:34:14.45#ibcon#about to read 4, iclass 24, count 0 2006.286.02:34:14.45#ibcon#read 4, iclass 24, count 0 2006.286.02:34:14.45#ibcon#about to read 5, iclass 24, count 0 2006.286.02:34:14.45#ibcon#read 5, iclass 24, count 0 2006.286.02:34:14.45#ibcon#about to read 6, iclass 24, count 0 2006.286.02:34:14.45#ibcon#read 6, iclass 24, count 0 2006.286.02:34:14.45#ibcon#end of sib2, iclass 24, count 0 2006.286.02:34:14.45#ibcon#*mode == 0, iclass 24, count 0 2006.286.02:34:14.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.02:34:14.45#ibcon#[25=USB\r\n] 2006.286.02:34:14.45#ibcon#*before write, iclass 24, count 0 2006.286.02:34:14.45#ibcon#enter sib2, iclass 24, count 0 2006.286.02:34:14.45#ibcon#flushed, iclass 24, count 0 2006.286.02:34:14.45#ibcon#about to write, iclass 24, count 0 2006.286.02:34:14.45#ibcon#wrote, iclass 24, count 0 2006.286.02:34:14.45#ibcon#about to read 3, iclass 24, count 0 2006.286.02:34:14.48#ibcon#read 3, iclass 24, count 0 2006.286.02:34:14.48#ibcon#about to read 4, iclass 24, count 0 2006.286.02:34:14.48#ibcon#read 4, iclass 24, count 0 2006.286.02:34:14.48#ibcon#about to read 5, iclass 24, count 0 2006.286.02:34:14.48#ibcon#read 5, iclass 24, count 0 2006.286.02:34:14.48#ibcon#about to read 6, iclass 24, count 0 2006.286.02:34:14.48#ibcon#read 6, iclass 24, count 0 2006.286.02:34:14.48#ibcon#end of sib2, iclass 24, count 0 2006.286.02:34:14.48#ibcon#*after write, iclass 24, count 0 2006.286.02:34:14.48#ibcon#*before return 0, iclass 24, count 0 2006.286.02:34:14.48#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:34:14.48#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:34:14.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.02:34:14.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.02:34:14.48$vck44/valo=6,814.99 2006.286.02:34:14.48#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.02:34:14.48#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.02:34:14.48#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:14.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:34:14.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:34:14.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:34:14.48#ibcon#enter wrdev, iclass 26, count 0 2006.286.02:34:14.48#ibcon#first serial, iclass 26, count 0 2006.286.02:34:14.48#ibcon#enter sib2, iclass 26, count 0 2006.286.02:34:14.48#ibcon#flushed, iclass 26, count 0 2006.286.02:34:14.48#ibcon#about to write, iclass 26, count 0 2006.286.02:34:14.48#ibcon#wrote, iclass 26, count 0 2006.286.02:34:14.48#ibcon#about to read 3, iclass 26, count 0 2006.286.02:34:14.50#ibcon#read 3, iclass 26, count 0 2006.286.02:34:14.50#ibcon#about to read 4, iclass 26, count 0 2006.286.02:34:14.50#ibcon#read 4, iclass 26, count 0 2006.286.02:34:14.50#ibcon#about to read 5, iclass 26, count 0 2006.286.02:34:14.50#ibcon#read 5, iclass 26, count 0 2006.286.02:34:14.50#ibcon#about to read 6, iclass 26, count 0 2006.286.02:34:14.50#ibcon#read 6, iclass 26, count 0 2006.286.02:34:14.50#ibcon#end of sib2, iclass 26, count 0 2006.286.02:34:14.50#ibcon#*mode == 0, iclass 26, count 0 2006.286.02:34:14.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.02:34:14.50#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.02:34:14.50#ibcon#*before write, iclass 26, count 0 2006.286.02:34:14.50#ibcon#enter sib2, iclass 26, count 0 2006.286.02:34:14.50#ibcon#flushed, iclass 26, count 0 2006.286.02:34:14.50#ibcon#about to write, iclass 26, count 0 2006.286.02:34:14.50#ibcon#wrote, iclass 26, count 0 2006.286.02:34:14.50#ibcon#about to read 3, iclass 26, count 0 2006.286.02:34:14.54#ibcon#read 3, iclass 26, count 0 2006.286.02:34:14.54#ibcon#about to read 4, iclass 26, count 0 2006.286.02:34:14.54#ibcon#read 4, iclass 26, count 0 2006.286.02:34:14.54#ibcon#about to read 5, iclass 26, count 0 2006.286.02:34:14.54#ibcon#read 5, iclass 26, count 0 2006.286.02:34:14.54#ibcon#about to read 6, iclass 26, count 0 2006.286.02:34:14.54#ibcon#read 6, iclass 26, count 0 2006.286.02:34:14.54#ibcon#end of sib2, iclass 26, count 0 2006.286.02:34:14.54#ibcon#*after write, iclass 26, count 0 2006.286.02:34:14.54#ibcon#*before return 0, iclass 26, count 0 2006.286.02:34:14.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:34:14.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:34:14.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.02:34:14.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.02:34:14.54$vck44/va=6,4 2006.286.02:34:14.54#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.02:34:14.54#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.02:34:14.54#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:14.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:34:14.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:34:14.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:34:14.60#ibcon#enter wrdev, iclass 28, count 2 2006.286.02:34:14.60#ibcon#first serial, iclass 28, count 2 2006.286.02:34:14.60#ibcon#enter sib2, iclass 28, count 2 2006.286.02:34:14.60#ibcon#flushed, iclass 28, count 2 2006.286.02:34:14.60#ibcon#about to write, iclass 28, count 2 2006.286.02:34:14.60#ibcon#wrote, iclass 28, count 2 2006.286.02:34:14.60#ibcon#about to read 3, iclass 28, count 2 2006.286.02:34:14.62#ibcon#read 3, iclass 28, count 2 2006.286.02:34:14.62#ibcon#about to read 4, iclass 28, count 2 2006.286.02:34:14.62#ibcon#read 4, iclass 28, count 2 2006.286.02:34:14.62#ibcon#about to read 5, iclass 28, count 2 2006.286.02:34:14.62#ibcon#read 5, iclass 28, count 2 2006.286.02:34:14.62#ibcon#about to read 6, iclass 28, count 2 2006.286.02:34:14.62#ibcon#read 6, iclass 28, count 2 2006.286.02:34:14.62#ibcon#end of sib2, iclass 28, count 2 2006.286.02:34:14.62#ibcon#*mode == 0, iclass 28, count 2 2006.286.02:34:14.62#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.02:34:14.62#ibcon#[25=AT06-04\r\n] 2006.286.02:34:14.62#ibcon#*before write, iclass 28, count 2 2006.286.02:34:14.62#ibcon#enter sib2, iclass 28, count 2 2006.286.02:34:14.62#ibcon#flushed, iclass 28, count 2 2006.286.02:34:14.62#ibcon#about to write, iclass 28, count 2 2006.286.02:34:14.62#ibcon#wrote, iclass 28, count 2 2006.286.02:34:14.62#ibcon#about to read 3, iclass 28, count 2 2006.286.02:34:14.65#ibcon#read 3, iclass 28, count 2 2006.286.02:34:14.65#ibcon#about to read 4, iclass 28, count 2 2006.286.02:34:14.65#ibcon#read 4, iclass 28, count 2 2006.286.02:34:14.65#ibcon#about to read 5, iclass 28, count 2 2006.286.02:34:14.65#ibcon#read 5, iclass 28, count 2 2006.286.02:34:14.65#ibcon#about to read 6, iclass 28, count 2 2006.286.02:34:14.65#ibcon#read 6, iclass 28, count 2 2006.286.02:34:14.65#ibcon#end of sib2, iclass 28, count 2 2006.286.02:34:14.65#ibcon#*after write, iclass 28, count 2 2006.286.02:34:14.65#ibcon#*before return 0, iclass 28, count 2 2006.286.02:34:14.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:34:14.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:34:14.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.02:34:14.65#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:14.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:34:14.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:34:14.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:34:14.77#ibcon#enter wrdev, iclass 28, count 0 2006.286.02:34:14.77#ibcon#first serial, iclass 28, count 0 2006.286.02:34:14.77#ibcon#enter sib2, iclass 28, count 0 2006.286.02:34:14.77#ibcon#flushed, iclass 28, count 0 2006.286.02:34:14.77#ibcon#about to write, iclass 28, count 0 2006.286.02:34:14.77#ibcon#wrote, iclass 28, count 0 2006.286.02:34:14.77#ibcon#about to read 3, iclass 28, count 0 2006.286.02:34:14.79#ibcon#read 3, iclass 28, count 0 2006.286.02:34:14.79#ibcon#about to read 4, iclass 28, count 0 2006.286.02:34:14.79#ibcon#read 4, iclass 28, count 0 2006.286.02:34:14.79#ibcon#about to read 5, iclass 28, count 0 2006.286.02:34:14.79#ibcon#read 5, iclass 28, count 0 2006.286.02:34:14.79#ibcon#about to read 6, iclass 28, count 0 2006.286.02:34:14.79#ibcon#read 6, iclass 28, count 0 2006.286.02:34:14.79#ibcon#end of sib2, iclass 28, count 0 2006.286.02:34:14.79#ibcon#*mode == 0, iclass 28, count 0 2006.286.02:34:14.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.02:34:14.79#ibcon#[25=USB\r\n] 2006.286.02:34:14.79#ibcon#*before write, iclass 28, count 0 2006.286.02:34:14.79#ibcon#enter sib2, iclass 28, count 0 2006.286.02:34:14.79#ibcon#flushed, iclass 28, count 0 2006.286.02:34:14.79#ibcon#about to write, iclass 28, count 0 2006.286.02:34:14.79#ibcon#wrote, iclass 28, count 0 2006.286.02:34:14.79#ibcon#about to read 3, iclass 28, count 0 2006.286.02:34:14.82#ibcon#read 3, iclass 28, count 0 2006.286.02:34:14.82#ibcon#about to read 4, iclass 28, count 0 2006.286.02:34:14.82#ibcon#read 4, iclass 28, count 0 2006.286.02:34:14.82#ibcon#about to read 5, iclass 28, count 0 2006.286.02:34:14.82#ibcon#read 5, iclass 28, count 0 2006.286.02:34:14.82#ibcon#about to read 6, iclass 28, count 0 2006.286.02:34:14.82#ibcon#read 6, iclass 28, count 0 2006.286.02:34:14.82#ibcon#end of sib2, iclass 28, count 0 2006.286.02:34:14.82#ibcon#*after write, iclass 28, count 0 2006.286.02:34:14.82#ibcon#*before return 0, iclass 28, count 0 2006.286.02:34:14.82#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:34:14.82#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:34:14.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.02:34:14.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.02:34:14.82$vck44/valo=7,864.99 2006.286.02:34:14.82#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.02:34:14.82#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.02:34:14.82#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:14.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:34:14.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:34:14.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:34:14.82#ibcon#enter wrdev, iclass 30, count 0 2006.286.02:34:14.82#ibcon#first serial, iclass 30, count 0 2006.286.02:34:14.82#ibcon#enter sib2, iclass 30, count 0 2006.286.02:34:14.82#ibcon#flushed, iclass 30, count 0 2006.286.02:34:14.82#ibcon#about to write, iclass 30, count 0 2006.286.02:34:14.82#ibcon#wrote, iclass 30, count 0 2006.286.02:34:14.82#ibcon#about to read 3, iclass 30, count 0 2006.286.02:34:14.84#ibcon#read 3, iclass 30, count 0 2006.286.02:34:14.84#ibcon#about to read 4, iclass 30, count 0 2006.286.02:34:14.84#ibcon#read 4, iclass 30, count 0 2006.286.02:34:14.84#ibcon#about to read 5, iclass 30, count 0 2006.286.02:34:14.84#ibcon#read 5, iclass 30, count 0 2006.286.02:34:14.84#ibcon#about to read 6, iclass 30, count 0 2006.286.02:34:14.84#ibcon#read 6, iclass 30, count 0 2006.286.02:34:14.84#ibcon#end of sib2, iclass 30, count 0 2006.286.02:34:14.84#ibcon#*mode == 0, iclass 30, count 0 2006.286.02:34:14.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.02:34:14.84#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.02:34:14.84#ibcon#*before write, iclass 30, count 0 2006.286.02:34:14.84#ibcon#enter sib2, iclass 30, count 0 2006.286.02:34:14.84#ibcon#flushed, iclass 30, count 0 2006.286.02:34:14.84#ibcon#about to write, iclass 30, count 0 2006.286.02:34:14.84#ibcon#wrote, iclass 30, count 0 2006.286.02:34:14.84#ibcon#about to read 3, iclass 30, count 0 2006.286.02:34:14.88#ibcon#read 3, iclass 30, count 0 2006.286.02:34:14.88#ibcon#about to read 4, iclass 30, count 0 2006.286.02:34:14.88#ibcon#read 4, iclass 30, count 0 2006.286.02:34:14.88#ibcon#about to read 5, iclass 30, count 0 2006.286.02:34:14.88#ibcon#read 5, iclass 30, count 0 2006.286.02:34:14.88#ibcon#about to read 6, iclass 30, count 0 2006.286.02:34:14.88#ibcon#read 6, iclass 30, count 0 2006.286.02:34:14.88#ibcon#end of sib2, iclass 30, count 0 2006.286.02:34:14.88#ibcon#*after write, iclass 30, count 0 2006.286.02:34:14.88#ibcon#*before return 0, iclass 30, count 0 2006.286.02:34:14.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:34:14.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:34:14.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.02:34:14.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.02:34:14.88$vck44/va=7,4 2006.286.02:34:14.88#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.02:34:14.88#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.02:34:14.88#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:14.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:34:14.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:34:14.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:34:14.94#ibcon#enter wrdev, iclass 32, count 2 2006.286.02:34:14.94#ibcon#first serial, iclass 32, count 2 2006.286.02:34:14.94#ibcon#enter sib2, iclass 32, count 2 2006.286.02:34:14.94#ibcon#flushed, iclass 32, count 2 2006.286.02:34:14.94#ibcon#about to write, iclass 32, count 2 2006.286.02:34:14.94#ibcon#wrote, iclass 32, count 2 2006.286.02:34:14.94#ibcon#about to read 3, iclass 32, count 2 2006.286.02:34:14.96#ibcon#read 3, iclass 32, count 2 2006.286.02:34:14.96#ibcon#about to read 4, iclass 32, count 2 2006.286.02:34:14.96#ibcon#read 4, iclass 32, count 2 2006.286.02:34:14.96#ibcon#about to read 5, iclass 32, count 2 2006.286.02:34:14.96#ibcon#read 5, iclass 32, count 2 2006.286.02:34:14.96#ibcon#about to read 6, iclass 32, count 2 2006.286.02:34:14.96#ibcon#read 6, iclass 32, count 2 2006.286.02:34:14.96#ibcon#end of sib2, iclass 32, count 2 2006.286.02:34:14.96#ibcon#*mode == 0, iclass 32, count 2 2006.286.02:34:14.96#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.02:34:14.96#ibcon#[25=AT07-04\r\n] 2006.286.02:34:14.96#ibcon#*before write, iclass 32, count 2 2006.286.02:34:14.96#ibcon#enter sib2, iclass 32, count 2 2006.286.02:34:14.96#ibcon#flushed, iclass 32, count 2 2006.286.02:34:14.96#ibcon#about to write, iclass 32, count 2 2006.286.02:34:14.96#ibcon#wrote, iclass 32, count 2 2006.286.02:34:14.96#ibcon#about to read 3, iclass 32, count 2 2006.286.02:34:14.99#ibcon#read 3, iclass 32, count 2 2006.286.02:34:14.99#ibcon#about to read 4, iclass 32, count 2 2006.286.02:34:14.99#ibcon#read 4, iclass 32, count 2 2006.286.02:34:14.99#ibcon#about to read 5, iclass 32, count 2 2006.286.02:34:14.99#ibcon#read 5, iclass 32, count 2 2006.286.02:34:14.99#ibcon#about to read 6, iclass 32, count 2 2006.286.02:34:14.99#ibcon#read 6, iclass 32, count 2 2006.286.02:34:14.99#ibcon#end of sib2, iclass 32, count 2 2006.286.02:34:14.99#ibcon#*after write, iclass 32, count 2 2006.286.02:34:14.99#ibcon#*before return 0, iclass 32, count 2 2006.286.02:34:14.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:34:14.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:34:14.99#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.02:34:14.99#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:14.99#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:34:15.11#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:34:15.11#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:34:15.11#ibcon#enter wrdev, iclass 32, count 0 2006.286.02:34:15.11#ibcon#first serial, iclass 32, count 0 2006.286.02:34:15.11#ibcon#enter sib2, iclass 32, count 0 2006.286.02:34:15.11#ibcon#flushed, iclass 32, count 0 2006.286.02:34:15.11#ibcon#about to write, iclass 32, count 0 2006.286.02:34:15.11#ibcon#wrote, iclass 32, count 0 2006.286.02:34:15.11#ibcon#about to read 3, iclass 32, count 0 2006.286.02:34:15.13#ibcon#read 3, iclass 32, count 0 2006.286.02:34:15.13#ibcon#about to read 4, iclass 32, count 0 2006.286.02:34:15.13#ibcon#read 4, iclass 32, count 0 2006.286.02:34:15.13#ibcon#about to read 5, iclass 32, count 0 2006.286.02:34:15.13#ibcon#read 5, iclass 32, count 0 2006.286.02:34:15.13#ibcon#about to read 6, iclass 32, count 0 2006.286.02:34:15.13#ibcon#read 6, iclass 32, count 0 2006.286.02:34:15.13#ibcon#end of sib2, iclass 32, count 0 2006.286.02:34:15.13#ibcon#*mode == 0, iclass 32, count 0 2006.286.02:34:15.13#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.02:34:15.13#ibcon#[25=USB\r\n] 2006.286.02:34:15.13#ibcon#*before write, iclass 32, count 0 2006.286.02:34:15.13#ibcon#enter sib2, iclass 32, count 0 2006.286.02:34:15.13#ibcon#flushed, iclass 32, count 0 2006.286.02:34:15.13#ibcon#about to write, iclass 32, count 0 2006.286.02:34:15.13#ibcon#wrote, iclass 32, count 0 2006.286.02:34:15.13#ibcon#about to read 3, iclass 32, count 0 2006.286.02:34:15.16#ibcon#read 3, iclass 32, count 0 2006.286.02:34:15.16#ibcon#about to read 4, iclass 32, count 0 2006.286.02:34:15.16#ibcon#read 4, iclass 32, count 0 2006.286.02:34:15.16#ibcon#about to read 5, iclass 32, count 0 2006.286.02:34:15.16#ibcon#read 5, iclass 32, count 0 2006.286.02:34:15.16#ibcon#about to read 6, iclass 32, count 0 2006.286.02:34:15.16#ibcon#read 6, iclass 32, count 0 2006.286.02:34:15.16#ibcon#end of sib2, iclass 32, count 0 2006.286.02:34:15.16#ibcon#*after write, iclass 32, count 0 2006.286.02:34:15.16#ibcon#*before return 0, iclass 32, count 0 2006.286.02:34:15.16#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:34:15.16#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:34:15.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.02:34:15.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.02:34:15.16$vck44/valo=8,884.99 2006.286.02:34:15.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.02:34:15.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.02:34:15.16#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:15.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:34:15.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:34:15.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:34:15.16#ibcon#enter wrdev, iclass 34, count 0 2006.286.02:34:15.16#ibcon#first serial, iclass 34, count 0 2006.286.02:34:15.16#ibcon#enter sib2, iclass 34, count 0 2006.286.02:34:15.16#ibcon#flushed, iclass 34, count 0 2006.286.02:34:15.16#ibcon#about to write, iclass 34, count 0 2006.286.02:34:15.16#ibcon#wrote, iclass 34, count 0 2006.286.02:34:15.16#ibcon#about to read 3, iclass 34, count 0 2006.286.02:34:15.18#ibcon#read 3, iclass 34, count 0 2006.286.02:34:15.18#ibcon#about to read 4, iclass 34, count 0 2006.286.02:34:15.18#ibcon#read 4, iclass 34, count 0 2006.286.02:34:15.18#ibcon#about to read 5, iclass 34, count 0 2006.286.02:34:15.18#ibcon#read 5, iclass 34, count 0 2006.286.02:34:15.18#ibcon#about to read 6, iclass 34, count 0 2006.286.02:34:15.18#ibcon#read 6, iclass 34, count 0 2006.286.02:34:15.18#ibcon#end of sib2, iclass 34, count 0 2006.286.02:34:15.18#ibcon#*mode == 0, iclass 34, count 0 2006.286.02:34:15.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.02:34:15.18#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.02:34:15.18#ibcon#*before write, iclass 34, count 0 2006.286.02:34:15.18#ibcon#enter sib2, iclass 34, count 0 2006.286.02:34:15.18#ibcon#flushed, iclass 34, count 0 2006.286.02:34:15.18#ibcon#about to write, iclass 34, count 0 2006.286.02:34:15.18#ibcon#wrote, iclass 34, count 0 2006.286.02:34:15.18#ibcon#about to read 3, iclass 34, count 0 2006.286.02:34:15.22#ibcon#read 3, iclass 34, count 0 2006.286.02:34:15.22#ibcon#about to read 4, iclass 34, count 0 2006.286.02:34:15.22#ibcon#read 4, iclass 34, count 0 2006.286.02:34:15.22#ibcon#about to read 5, iclass 34, count 0 2006.286.02:34:15.22#ibcon#read 5, iclass 34, count 0 2006.286.02:34:15.22#ibcon#about to read 6, iclass 34, count 0 2006.286.02:34:15.22#ibcon#read 6, iclass 34, count 0 2006.286.02:34:15.22#ibcon#end of sib2, iclass 34, count 0 2006.286.02:34:15.22#ibcon#*after write, iclass 34, count 0 2006.286.02:34:15.22#ibcon#*before return 0, iclass 34, count 0 2006.286.02:34:15.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:34:15.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:34:15.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.02:34:15.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.02:34:15.22$vck44/va=8,3 2006.286.02:34:15.22#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.02:34:15.22#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.02:34:15.22#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:15.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.02:34:15.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.02:34:15.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.02:34:15.28#ibcon#enter wrdev, iclass 36, count 2 2006.286.02:34:15.28#ibcon#first serial, iclass 36, count 2 2006.286.02:34:15.28#ibcon#enter sib2, iclass 36, count 2 2006.286.02:34:15.28#ibcon#flushed, iclass 36, count 2 2006.286.02:34:15.28#ibcon#about to write, iclass 36, count 2 2006.286.02:34:15.28#ibcon#wrote, iclass 36, count 2 2006.286.02:34:15.28#ibcon#about to read 3, iclass 36, count 2 2006.286.02:34:15.30#ibcon#read 3, iclass 36, count 2 2006.286.02:34:15.30#ibcon#about to read 4, iclass 36, count 2 2006.286.02:34:15.30#ibcon#read 4, iclass 36, count 2 2006.286.02:34:15.30#ibcon#about to read 5, iclass 36, count 2 2006.286.02:34:15.30#ibcon#read 5, iclass 36, count 2 2006.286.02:34:15.30#ibcon#about to read 6, iclass 36, count 2 2006.286.02:34:15.30#ibcon#read 6, iclass 36, count 2 2006.286.02:34:15.30#ibcon#end of sib2, iclass 36, count 2 2006.286.02:34:15.30#ibcon#*mode == 0, iclass 36, count 2 2006.286.02:34:15.30#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.02:34:15.30#ibcon#[25=AT08-03\r\n] 2006.286.02:34:15.30#ibcon#*before write, iclass 36, count 2 2006.286.02:34:15.30#ibcon#enter sib2, iclass 36, count 2 2006.286.02:34:15.30#ibcon#flushed, iclass 36, count 2 2006.286.02:34:15.30#ibcon#about to write, iclass 36, count 2 2006.286.02:34:15.30#ibcon#wrote, iclass 36, count 2 2006.286.02:34:15.30#ibcon#about to read 3, iclass 36, count 2 2006.286.02:34:15.33#ibcon#read 3, iclass 36, count 2 2006.286.02:34:15.33#ibcon#about to read 4, iclass 36, count 2 2006.286.02:34:15.33#ibcon#read 4, iclass 36, count 2 2006.286.02:34:15.33#ibcon#about to read 5, iclass 36, count 2 2006.286.02:34:15.33#ibcon#read 5, iclass 36, count 2 2006.286.02:34:15.33#ibcon#about to read 6, iclass 36, count 2 2006.286.02:34:15.33#ibcon#read 6, iclass 36, count 2 2006.286.02:34:15.33#ibcon#end of sib2, iclass 36, count 2 2006.286.02:34:15.33#ibcon#*after write, iclass 36, count 2 2006.286.02:34:15.33#ibcon#*before return 0, iclass 36, count 2 2006.286.02:34:15.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.02:34:15.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.02:34:15.33#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.02:34:15.33#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:15.33#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.02:34:15.45#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.02:34:15.45#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.02:34:15.45#ibcon#enter wrdev, iclass 36, count 0 2006.286.02:34:15.45#ibcon#first serial, iclass 36, count 0 2006.286.02:34:15.45#ibcon#enter sib2, iclass 36, count 0 2006.286.02:34:15.45#ibcon#flushed, iclass 36, count 0 2006.286.02:34:15.45#ibcon#about to write, iclass 36, count 0 2006.286.02:34:15.45#ibcon#wrote, iclass 36, count 0 2006.286.02:34:15.45#ibcon#about to read 3, iclass 36, count 0 2006.286.02:34:15.47#ibcon#read 3, iclass 36, count 0 2006.286.02:34:15.47#ibcon#about to read 4, iclass 36, count 0 2006.286.02:34:15.47#ibcon#read 4, iclass 36, count 0 2006.286.02:34:15.47#ibcon#about to read 5, iclass 36, count 0 2006.286.02:34:15.47#ibcon#read 5, iclass 36, count 0 2006.286.02:34:15.47#ibcon#about to read 6, iclass 36, count 0 2006.286.02:34:15.47#ibcon#read 6, iclass 36, count 0 2006.286.02:34:15.47#ibcon#end of sib2, iclass 36, count 0 2006.286.02:34:15.47#ibcon#*mode == 0, iclass 36, count 0 2006.286.02:34:15.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.02:34:15.47#ibcon#[25=USB\r\n] 2006.286.02:34:15.47#ibcon#*before write, iclass 36, count 0 2006.286.02:34:15.47#ibcon#enter sib2, iclass 36, count 0 2006.286.02:34:15.47#ibcon#flushed, iclass 36, count 0 2006.286.02:34:15.47#ibcon#about to write, iclass 36, count 0 2006.286.02:34:15.47#ibcon#wrote, iclass 36, count 0 2006.286.02:34:15.47#ibcon#about to read 3, iclass 36, count 0 2006.286.02:34:15.50#ibcon#read 3, iclass 36, count 0 2006.286.02:34:15.50#ibcon#about to read 4, iclass 36, count 0 2006.286.02:34:15.50#ibcon#read 4, iclass 36, count 0 2006.286.02:34:15.50#ibcon#about to read 5, iclass 36, count 0 2006.286.02:34:15.50#ibcon#read 5, iclass 36, count 0 2006.286.02:34:15.50#ibcon#about to read 6, iclass 36, count 0 2006.286.02:34:15.50#ibcon#read 6, iclass 36, count 0 2006.286.02:34:15.50#ibcon#end of sib2, iclass 36, count 0 2006.286.02:34:15.50#ibcon#*after write, iclass 36, count 0 2006.286.02:34:15.50#ibcon#*before return 0, iclass 36, count 0 2006.286.02:34:15.50#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.02:34:15.50#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.02:34:15.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.02:34:15.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.02:34:15.50$vck44/vblo=1,629.99 2006.286.02:34:15.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.02:34:15.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.02:34:15.50#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:15.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.02:34:15.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.02:34:15.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.02:34:15.50#ibcon#enter wrdev, iclass 38, count 0 2006.286.02:34:15.50#ibcon#first serial, iclass 38, count 0 2006.286.02:34:15.50#ibcon#enter sib2, iclass 38, count 0 2006.286.02:34:15.50#ibcon#flushed, iclass 38, count 0 2006.286.02:34:15.50#ibcon#about to write, iclass 38, count 0 2006.286.02:34:15.50#ibcon#wrote, iclass 38, count 0 2006.286.02:34:15.50#ibcon#about to read 3, iclass 38, count 0 2006.286.02:34:15.52#ibcon#read 3, iclass 38, count 0 2006.286.02:34:15.52#ibcon#about to read 4, iclass 38, count 0 2006.286.02:34:15.52#ibcon#read 4, iclass 38, count 0 2006.286.02:34:15.52#ibcon#about to read 5, iclass 38, count 0 2006.286.02:34:15.52#ibcon#read 5, iclass 38, count 0 2006.286.02:34:15.52#ibcon#about to read 6, iclass 38, count 0 2006.286.02:34:15.52#ibcon#read 6, iclass 38, count 0 2006.286.02:34:15.52#ibcon#end of sib2, iclass 38, count 0 2006.286.02:34:15.52#ibcon#*mode == 0, iclass 38, count 0 2006.286.02:34:15.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.02:34:15.52#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.02:34:15.52#ibcon#*before write, iclass 38, count 0 2006.286.02:34:15.52#ibcon#enter sib2, iclass 38, count 0 2006.286.02:34:15.52#ibcon#flushed, iclass 38, count 0 2006.286.02:34:15.52#ibcon#about to write, iclass 38, count 0 2006.286.02:34:15.52#ibcon#wrote, iclass 38, count 0 2006.286.02:34:15.52#ibcon#about to read 3, iclass 38, count 0 2006.286.02:34:15.56#ibcon#read 3, iclass 38, count 0 2006.286.02:34:15.56#ibcon#about to read 4, iclass 38, count 0 2006.286.02:34:15.56#ibcon#read 4, iclass 38, count 0 2006.286.02:34:15.56#ibcon#about to read 5, iclass 38, count 0 2006.286.02:34:15.56#ibcon#read 5, iclass 38, count 0 2006.286.02:34:15.56#ibcon#about to read 6, iclass 38, count 0 2006.286.02:34:15.56#ibcon#read 6, iclass 38, count 0 2006.286.02:34:15.56#ibcon#end of sib2, iclass 38, count 0 2006.286.02:34:15.56#ibcon#*after write, iclass 38, count 0 2006.286.02:34:15.56#ibcon#*before return 0, iclass 38, count 0 2006.286.02:34:15.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.02:34:15.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.02:34:15.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.02:34:15.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.02:34:15.56$vck44/vb=1,4 2006.286.02:34:15.56#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.02:34:15.56#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.02:34:15.56#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:15.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.02:34:15.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.02:34:15.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.02:34:15.56#ibcon#enter wrdev, iclass 40, count 2 2006.286.02:34:15.56#ibcon#first serial, iclass 40, count 2 2006.286.02:34:15.56#ibcon#enter sib2, iclass 40, count 2 2006.286.02:34:15.56#ibcon#flushed, iclass 40, count 2 2006.286.02:34:15.56#ibcon#about to write, iclass 40, count 2 2006.286.02:34:15.56#ibcon#wrote, iclass 40, count 2 2006.286.02:34:15.56#ibcon#about to read 3, iclass 40, count 2 2006.286.02:34:15.58#ibcon#read 3, iclass 40, count 2 2006.286.02:34:15.58#ibcon#about to read 4, iclass 40, count 2 2006.286.02:34:15.58#ibcon#read 4, iclass 40, count 2 2006.286.02:34:15.58#ibcon#about to read 5, iclass 40, count 2 2006.286.02:34:15.58#ibcon#read 5, iclass 40, count 2 2006.286.02:34:15.58#ibcon#about to read 6, iclass 40, count 2 2006.286.02:34:15.58#ibcon#read 6, iclass 40, count 2 2006.286.02:34:15.58#ibcon#end of sib2, iclass 40, count 2 2006.286.02:34:15.58#ibcon#*mode == 0, iclass 40, count 2 2006.286.02:34:15.58#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.02:34:15.58#ibcon#[27=AT01-04\r\n] 2006.286.02:34:15.58#ibcon#*before write, iclass 40, count 2 2006.286.02:34:15.58#ibcon#enter sib2, iclass 40, count 2 2006.286.02:34:15.58#ibcon#flushed, iclass 40, count 2 2006.286.02:34:15.58#ibcon#about to write, iclass 40, count 2 2006.286.02:34:15.58#ibcon#wrote, iclass 40, count 2 2006.286.02:34:15.58#ibcon#about to read 3, iclass 40, count 2 2006.286.02:34:15.61#ibcon#read 3, iclass 40, count 2 2006.286.02:34:15.61#ibcon#about to read 4, iclass 40, count 2 2006.286.02:34:15.61#ibcon#read 4, iclass 40, count 2 2006.286.02:34:15.61#ibcon#about to read 5, iclass 40, count 2 2006.286.02:34:15.61#ibcon#read 5, iclass 40, count 2 2006.286.02:34:15.61#ibcon#about to read 6, iclass 40, count 2 2006.286.02:34:15.61#ibcon#read 6, iclass 40, count 2 2006.286.02:34:15.61#ibcon#end of sib2, iclass 40, count 2 2006.286.02:34:15.61#ibcon#*after write, iclass 40, count 2 2006.286.02:34:15.61#ibcon#*before return 0, iclass 40, count 2 2006.286.02:34:15.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.02:34:15.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.02:34:15.61#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.02:34:15.61#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:15.61#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.02:34:15.73#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.02:34:15.73#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.02:34:15.73#ibcon#enter wrdev, iclass 40, count 0 2006.286.02:34:15.73#ibcon#first serial, iclass 40, count 0 2006.286.02:34:15.73#ibcon#enter sib2, iclass 40, count 0 2006.286.02:34:15.73#ibcon#flushed, iclass 40, count 0 2006.286.02:34:15.73#ibcon#about to write, iclass 40, count 0 2006.286.02:34:15.73#ibcon#wrote, iclass 40, count 0 2006.286.02:34:15.73#ibcon#about to read 3, iclass 40, count 0 2006.286.02:34:15.75#ibcon#read 3, iclass 40, count 0 2006.286.02:34:15.75#ibcon#about to read 4, iclass 40, count 0 2006.286.02:34:15.75#ibcon#read 4, iclass 40, count 0 2006.286.02:34:15.75#ibcon#about to read 5, iclass 40, count 0 2006.286.02:34:15.75#ibcon#read 5, iclass 40, count 0 2006.286.02:34:15.75#ibcon#about to read 6, iclass 40, count 0 2006.286.02:34:15.75#ibcon#read 6, iclass 40, count 0 2006.286.02:34:15.75#ibcon#end of sib2, iclass 40, count 0 2006.286.02:34:15.75#ibcon#*mode == 0, iclass 40, count 0 2006.286.02:34:15.75#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.02:34:15.75#ibcon#[27=USB\r\n] 2006.286.02:34:15.75#ibcon#*before write, iclass 40, count 0 2006.286.02:34:15.75#ibcon#enter sib2, iclass 40, count 0 2006.286.02:34:15.75#ibcon#flushed, iclass 40, count 0 2006.286.02:34:15.75#ibcon#about to write, iclass 40, count 0 2006.286.02:34:15.75#ibcon#wrote, iclass 40, count 0 2006.286.02:34:15.75#ibcon#about to read 3, iclass 40, count 0 2006.286.02:34:15.78#ibcon#read 3, iclass 40, count 0 2006.286.02:34:15.78#ibcon#about to read 4, iclass 40, count 0 2006.286.02:34:15.78#ibcon#read 4, iclass 40, count 0 2006.286.02:34:15.78#ibcon#about to read 5, iclass 40, count 0 2006.286.02:34:15.78#ibcon#read 5, iclass 40, count 0 2006.286.02:34:15.78#ibcon#about to read 6, iclass 40, count 0 2006.286.02:34:15.78#ibcon#read 6, iclass 40, count 0 2006.286.02:34:15.78#ibcon#end of sib2, iclass 40, count 0 2006.286.02:34:15.78#ibcon#*after write, iclass 40, count 0 2006.286.02:34:15.78#ibcon#*before return 0, iclass 40, count 0 2006.286.02:34:15.78#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.02:34:15.78#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.02:34:15.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.02:34:15.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.02:34:15.78$vck44/vblo=2,634.99 2006.286.02:34:15.78#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.02:34:15.78#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.02:34:15.78#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:15.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:34:15.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:34:15.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:34:15.78#ibcon#enter wrdev, iclass 4, count 0 2006.286.02:34:15.78#ibcon#first serial, iclass 4, count 0 2006.286.02:34:15.78#ibcon#enter sib2, iclass 4, count 0 2006.286.02:34:15.78#ibcon#flushed, iclass 4, count 0 2006.286.02:34:15.78#ibcon#about to write, iclass 4, count 0 2006.286.02:34:15.78#ibcon#wrote, iclass 4, count 0 2006.286.02:34:15.78#ibcon#about to read 3, iclass 4, count 0 2006.286.02:34:15.80#ibcon#read 3, iclass 4, count 0 2006.286.02:34:15.80#ibcon#about to read 4, iclass 4, count 0 2006.286.02:34:15.80#ibcon#read 4, iclass 4, count 0 2006.286.02:34:15.80#ibcon#about to read 5, iclass 4, count 0 2006.286.02:34:15.80#ibcon#read 5, iclass 4, count 0 2006.286.02:34:15.80#ibcon#about to read 6, iclass 4, count 0 2006.286.02:34:15.80#ibcon#read 6, iclass 4, count 0 2006.286.02:34:15.80#ibcon#end of sib2, iclass 4, count 0 2006.286.02:34:15.80#ibcon#*mode == 0, iclass 4, count 0 2006.286.02:34:15.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.02:34:15.80#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.02:34:15.80#ibcon#*before write, iclass 4, count 0 2006.286.02:34:15.80#ibcon#enter sib2, iclass 4, count 0 2006.286.02:34:15.80#ibcon#flushed, iclass 4, count 0 2006.286.02:34:15.80#ibcon#about to write, iclass 4, count 0 2006.286.02:34:15.80#ibcon#wrote, iclass 4, count 0 2006.286.02:34:15.80#ibcon#about to read 3, iclass 4, count 0 2006.286.02:34:15.84#ibcon#read 3, iclass 4, count 0 2006.286.02:34:15.84#ibcon#about to read 4, iclass 4, count 0 2006.286.02:34:15.84#ibcon#read 4, iclass 4, count 0 2006.286.02:34:15.84#ibcon#about to read 5, iclass 4, count 0 2006.286.02:34:15.84#ibcon#read 5, iclass 4, count 0 2006.286.02:34:15.84#ibcon#about to read 6, iclass 4, count 0 2006.286.02:34:15.84#ibcon#read 6, iclass 4, count 0 2006.286.02:34:15.84#ibcon#end of sib2, iclass 4, count 0 2006.286.02:34:15.84#ibcon#*after write, iclass 4, count 0 2006.286.02:34:15.84#ibcon#*before return 0, iclass 4, count 0 2006.286.02:34:15.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:34:15.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.02:34:15.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.02:34:15.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.02:34:15.84$vck44/vb=2,5 2006.286.02:34:15.84#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.02:34:15.84#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.02:34:15.84#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:15.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:34:15.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:34:15.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:34:15.90#ibcon#enter wrdev, iclass 6, count 2 2006.286.02:34:15.90#ibcon#first serial, iclass 6, count 2 2006.286.02:34:15.90#ibcon#enter sib2, iclass 6, count 2 2006.286.02:34:15.90#ibcon#flushed, iclass 6, count 2 2006.286.02:34:15.90#ibcon#about to write, iclass 6, count 2 2006.286.02:34:15.90#ibcon#wrote, iclass 6, count 2 2006.286.02:34:15.90#ibcon#about to read 3, iclass 6, count 2 2006.286.02:34:15.92#ibcon#read 3, iclass 6, count 2 2006.286.02:34:15.92#ibcon#about to read 4, iclass 6, count 2 2006.286.02:34:15.92#ibcon#read 4, iclass 6, count 2 2006.286.02:34:15.92#ibcon#about to read 5, iclass 6, count 2 2006.286.02:34:15.92#ibcon#read 5, iclass 6, count 2 2006.286.02:34:15.92#ibcon#about to read 6, iclass 6, count 2 2006.286.02:34:15.92#ibcon#read 6, iclass 6, count 2 2006.286.02:34:15.92#ibcon#end of sib2, iclass 6, count 2 2006.286.02:34:15.92#ibcon#*mode == 0, iclass 6, count 2 2006.286.02:34:15.92#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.02:34:15.92#ibcon#[27=AT02-05\r\n] 2006.286.02:34:15.92#ibcon#*before write, iclass 6, count 2 2006.286.02:34:15.92#ibcon#enter sib2, iclass 6, count 2 2006.286.02:34:15.92#ibcon#flushed, iclass 6, count 2 2006.286.02:34:15.92#ibcon#about to write, iclass 6, count 2 2006.286.02:34:15.92#ibcon#wrote, iclass 6, count 2 2006.286.02:34:15.92#ibcon#about to read 3, iclass 6, count 2 2006.286.02:34:15.95#ibcon#read 3, iclass 6, count 2 2006.286.02:34:15.95#ibcon#about to read 4, iclass 6, count 2 2006.286.02:34:15.95#ibcon#read 4, iclass 6, count 2 2006.286.02:34:15.95#ibcon#about to read 5, iclass 6, count 2 2006.286.02:34:15.95#ibcon#read 5, iclass 6, count 2 2006.286.02:34:15.95#ibcon#about to read 6, iclass 6, count 2 2006.286.02:34:15.95#ibcon#read 6, iclass 6, count 2 2006.286.02:34:15.95#ibcon#end of sib2, iclass 6, count 2 2006.286.02:34:15.95#ibcon#*after write, iclass 6, count 2 2006.286.02:34:15.95#ibcon#*before return 0, iclass 6, count 2 2006.286.02:34:15.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:34:15.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.02:34:15.95#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.02:34:15.95#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:15.95#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:34:16.07#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:34:16.07#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:34:16.07#ibcon#enter wrdev, iclass 6, count 0 2006.286.02:34:16.07#ibcon#first serial, iclass 6, count 0 2006.286.02:34:16.07#ibcon#enter sib2, iclass 6, count 0 2006.286.02:34:16.07#ibcon#flushed, iclass 6, count 0 2006.286.02:34:16.07#ibcon#about to write, iclass 6, count 0 2006.286.02:34:16.07#ibcon#wrote, iclass 6, count 0 2006.286.02:34:16.07#ibcon#about to read 3, iclass 6, count 0 2006.286.02:34:16.09#ibcon#read 3, iclass 6, count 0 2006.286.02:34:16.09#ibcon#about to read 4, iclass 6, count 0 2006.286.02:34:16.09#ibcon#read 4, iclass 6, count 0 2006.286.02:34:16.09#ibcon#about to read 5, iclass 6, count 0 2006.286.02:34:16.09#ibcon#read 5, iclass 6, count 0 2006.286.02:34:16.09#ibcon#about to read 6, iclass 6, count 0 2006.286.02:34:16.09#ibcon#read 6, iclass 6, count 0 2006.286.02:34:16.09#ibcon#end of sib2, iclass 6, count 0 2006.286.02:34:16.09#ibcon#*mode == 0, iclass 6, count 0 2006.286.02:34:16.09#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.02:34:16.09#ibcon#[27=USB\r\n] 2006.286.02:34:16.09#ibcon#*before write, iclass 6, count 0 2006.286.02:34:16.09#ibcon#enter sib2, iclass 6, count 0 2006.286.02:34:16.09#ibcon#flushed, iclass 6, count 0 2006.286.02:34:16.09#ibcon#about to write, iclass 6, count 0 2006.286.02:34:16.09#ibcon#wrote, iclass 6, count 0 2006.286.02:34:16.09#ibcon#about to read 3, iclass 6, count 0 2006.286.02:34:16.12#ibcon#read 3, iclass 6, count 0 2006.286.02:34:16.12#ibcon#about to read 4, iclass 6, count 0 2006.286.02:34:16.12#ibcon#read 4, iclass 6, count 0 2006.286.02:34:16.12#ibcon#about to read 5, iclass 6, count 0 2006.286.02:34:16.12#ibcon#read 5, iclass 6, count 0 2006.286.02:34:16.12#ibcon#about to read 6, iclass 6, count 0 2006.286.02:34:16.12#ibcon#read 6, iclass 6, count 0 2006.286.02:34:16.12#ibcon#end of sib2, iclass 6, count 0 2006.286.02:34:16.12#ibcon#*after write, iclass 6, count 0 2006.286.02:34:16.12#ibcon#*before return 0, iclass 6, count 0 2006.286.02:34:16.12#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:34:16.12#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.02:34:16.12#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.02:34:16.12#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.02:34:16.12$vck44/vblo=3,649.99 2006.286.02:34:16.12#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.02:34:16.12#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.02:34:16.12#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:16.12#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:34:16.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:34:16.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:34:16.12#ibcon#enter wrdev, iclass 10, count 0 2006.286.02:34:16.12#ibcon#first serial, iclass 10, count 0 2006.286.02:34:16.12#ibcon#enter sib2, iclass 10, count 0 2006.286.02:34:16.12#ibcon#flushed, iclass 10, count 0 2006.286.02:34:16.12#ibcon#about to write, iclass 10, count 0 2006.286.02:34:16.12#ibcon#wrote, iclass 10, count 0 2006.286.02:34:16.12#ibcon#about to read 3, iclass 10, count 0 2006.286.02:34:16.14#ibcon#read 3, iclass 10, count 0 2006.286.02:34:16.14#ibcon#about to read 4, iclass 10, count 0 2006.286.02:34:16.14#ibcon#read 4, iclass 10, count 0 2006.286.02:34:16.14#ibcon#about to read 5, iclass 10, count 0 2006.286.02:34:16.14#ibcon#read 5, iclass 10, count 0 2006.286.02:34:16.14#ibcon#about to read 6, iclass 10, count 0 2006.286.02:34:16.14#ibcon#read 6, iclass 10, count 0 2006.286.02:34:16.14#ibcon#end of sib2, iclass 10, count 0 2006.286.02:34:16.14#ibcon#*mode == 0, iclass 10, count 0 2006.286.02:34:16.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.02:34:16.14#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.02:34:16.14#ibcon#*before write, iclass 10, count 0 2006.286.02:34:16.14#ibcon#enter sib2, iclass 10, count 0 2006.286.02:34:16.14#ibcon#flushed, iclass 10, count 0 2006.286.02:34:16.14#ibcon#about to write, iclass 10, count 0 2006.286.02:34:16.14#ibcon#wrote, iclass 10, count 0 2006.286.02:34:16.14#ibcon#about to read 3, iclass 10, count 0 2006.286.02:34:16.18#ibcon#read 3, iclass 10, count 0 2006.286.02:34:16.18#ibcon#about to read 4, iclass 10, count 0 2006.286.02:34:16.18#ibcon#read 4, iclass 10, count 0 2006.286.02:34:16.18#ibcon#about to read 5, iclass 10, count 0 2006.286.02:34:16.18#ibcon#read 5, iclass 10, count 0 2006.286.02:34:16.18#ibcon#about to read 6, iclass 10, count 0 2006.286.02:34:16.18#ibcon#read 6, iclass 10, count 0 2006.286.02:34:16.18#ibcon#end of sib2, iclass 10, count 0 2006.286.02:34:16.18#ibcon#*after write, iclass 10, count 0 2006.286.02:34:16.18#ibcon#*before return 0, iclass 10, count 0 2006.286.02:34:16.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:34:16.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.02:34:16.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.02:34:16.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.02:34:16.18$vck44/vb=3,4 2006.286.02:34:16.18#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.02:34:16.18#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.02:34:16.18#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:16.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:34:16.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:34:16.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:34:16.24#ibcon#enter wrdev, iclass 12, count 2 2006.286.02:34:16.24#ibcon#first serial, iclass 12, count 2 2006.286.02:34:16.24#ibcon#enter sib2, iclass 12, count 2 2006.286.02:34:16.24#ibcon#flushed, iclass 12, count 2 2006.286.02:34:16.24#ibcon#about to write, iclass 12, count 2 2006.286.02:34:16.24#ibcon#wrote, iclass 12, count 2 2006.286.02:34:16.24#ibcon#about to read 3, iclass 12, count 2 2006.286.02:34:16.26#ibcon#read 3, iclass 12, count 2 2006.286.02:34:16.26#ibcon#about to read 4, iclass 12, count 2 2006.286.02:34:16.26#ibcon#read 4, iclass 12, count 2 2006.286.02:34:16.26#ibcon#about to read 5, iclass 12, count 2 2006.286.02:34:16.26#ibcon#read 5, iclass 12, count 2 2006.286.02:34:16.26#ibcon#about to read 6, iclass 12, count 2 2006.286.02:34:16.26#ibcon#read 6, iclass 12, count 2 2006.286.02:34:16.26#ibcon#end of sib2, iclass 12, count 2 2006.286.02:34:16.26#ibcon#*mode == 0, iclass 12, count 2 2006.286.02:34:16.26#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.02:34:16.26#ibcon#[27=AT03-04\r\n] 2006.286.02:34:16.26#ibcon#*before write, iclass 12, count 2 2006.286.02:34:16.26#ibcon#enter sib2, iclass 12, count 2 2006.286.02:34:16.26#ibcon#flushed, iclass 12, count 2 2006.286.02:34:16.26#ibcon#about to write, iclass 12, count 2 2006.286.02:34:16.26#ibcon#wrote, iclass 12, count 2 2006.286.02:34:16.26#ibcon#about to read 3, iclass 12, count 2 2006.286.02:34:16.29#ibcon#read 3, iclass 12, count 2 2006.286.02:34:16.29#ibcon#about to read 4, iclass 12, count 2 2006.286.02:34:16.29#ibcon#read 4, iclass 12, count 2 2006.286.02:34:16.29#ibcon#about to read 5, iclass 12, count 2 2006.286.02:34:16.29#ibcon#read 5, iclass 12, count 2 2006.286.02:34:16.29#ibcon#about to read 6, iclass 12, count 2 2006.286.02:34:16.29#ibcon#read 6, iclass 12, count 2 2006.286.02:34:16.29#ibcon#end of sib2, iclass 12, count 2 2006.286.02:34:16.29#ibcon#*after write, iclass 12, count 2 2006.286.02:34:16.29#ibcon#*before return 0, iclass 12, count 2 2006.286.02:34:16.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:34:16.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.02:34:16.29#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.02:34:16.29#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:16.29#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:34:16.41#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:34:16.41#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:34:16.41#ibcon#enter wrdev, iclass 12, count 0 2006.286.02:34:16.41#ibcon#first serial, iclass 12, count 0 2006.286.02:34:16.41#ibcon#enter sib2, iclass 12, count 0 2006.286.02:34:16.41#ibcon#flushed, iclass 12, count 0 2006.286.02:34:16.41#ibcon#about to write, iclass 12, count 0 2006.286.02:34:16.41#ibcon#wrote, iclass 12, count 0 2006.286.02:34:16.41#ibcon#about to read 3, iclass 12, count 0 2006.286.02:34:16.43#ibcon#read 3, iclass 12, count 0 2006.286.02:34:16.43#ibcon#about to read 4, iclass 12, count 0 2006.286.02:34:16.43#ibcon#read 4, iclass 12, count 0 2006.286.02:34:16.43#ibcon#about to read 5, iclass 12, count 0 2006.286.02:34:16.43#ibcon#read 5, iclass 12, count 0 2006.286.02:34:16.43#ibcon#about to read 6, iclass 12, count 0 2006.286.02:34:16.43#ibcon#read 6, iclass 12, count 0 2006.286.02:34:16.43#ibcon#end of sib2, iclass 12, count 0 2006.286.02:34:16.43#ibcon#*mode == 0, iclass 12, count 0 2006.286.02:34:16.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.02:34:16.43#ibcon#[27=USB\r\n] 2006.286.02:34:16.43#ibcon#*before write, iclass 12, count 0 2006.286.02:34:16.43#ibcon#enter sib2, iclass 12, count 0 2006.286.02:34:16.43#ibcon#flushed, iclass 12, count 0 2006.286.02:34:16.43#ibcon#about to write, iclass 12, count 0 2006.286.02:34:16.43#ibcon#wrote, iclass 12, count 0 2006.286.02:34:16.43#ibcon#about to read 3, iclass 12, count 0 2006.286.02:34:16.46#ibcon#read 3, iclass 12, count 0 2006.286.02:34:16.46#ibcon#about to read 4, iclass 12, count 0 2006.286.02:34:16.46#ibcon#read 4, iclass 12, count 0 2006.286.02:34:16.46#ibcon#about to read 5, iclass 12, count 0 2006.286.02:34:16.46#ibcon#read 5, iclass 12, count 0 2006.286.02:34:16.46#ibcon#about to read 6, iclass 12, count 0 2006.286.02:34:16.46#ibcon#read 6, iclass 12, count 0 2006.286.02:34:16.46#ibcon#end of sib2, iclass 12, count 0 2006.286.02:34:16.46#ibcon#*after write, iclass 12, count 0 2006.286.02:34:16.46#ibcon#*before return 0, iclass 12, count 0 2006.286.02:34:16.46#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:34:16.46#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.02:34:16.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.02:34:16.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.02:34:16.46$vck44/vblo=4,679.99 2006.286.02:34:16.46#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.02:34:16.46#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.02:34:16.46#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:16.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:34:16.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:34:16.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:34:16.46#ibcon#enter wrdev, iclass 14, count 0 2006.286.02:34:16.46#ibcon#first serial, iclass 14, count 0 2006.286.02:34:16.46#ibcon#enter sib2, iclass 14, count 0 2006.286.02:34:16.46#ibcon#flushed, iclass 14, count 0 2006.286.02:34:16.46#ibcon#about to write, iclass 14, count 0 2006.286.02:34:16.46#ibcon#wrote, iclass 14, count 0 2006.286.02:34:16.46#ibcon#about to read 3, iclass 14, count 0 2006.286.02:34:16.48#ibcon#read 3, iclass 14, count 0 2006.286.02:34:16.48#ibcon#about to read 4, iclass 14, count 0 2006.286.02:34:16.48#ibcon#read 4, iclass 14, count 0 2006.286.02:34:16.48#ibcon#about to read 5, iclass 14, count 0 2006.286.02:34:16.48#ibcon#read 5, iclass 14, count 0 2006.286.02:34:16.48#ibcon#about to read 6, iclass 14, count 0 2006.286.02:34:16.48#ibcon#read 6, iclass 14, count 0 2006.286.02:34:16.48#ibcon#end of sib2, iclass 14, count 0 2006.286.02:34:16.48#ibcon#*mode == 0, iclass 14, count 0 2006.286.02:34:16.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.02:34:16.48#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.02:34:16.48#ibcon#*before write, iclass 14, count 0 2006.286.02:34:16.48#ibcon#enter sib2, iclass 14, count 0 2006.286.02:34:16.48#ibcon#flushed, iclass 14, count 0 2006.286.02:34:16.48#ibcon#about to write, iclass 14, count 0 2006.286.02:34:16.48#ibcon#wrote, iclass 14, count 0 2006.286.02:34:16.48#ibcon#about to read 3, iclass 14, count 0 2006.286.02:34:16.52#ibcon#read 3, iclass 14, count 0 2006.286.02:34:16.52#ibcon#about to read 4, iclass 14, count 0 2006.286.02:34:16.52#ibcon#read 4, iclass 14, count 0 2006.286.02:34:16.52#ibcon#about to read 5, iclass 14, count 0 2006.286.02:34:16.52#ibcon#read 5, iclass 14, count 0 2006.286.02:34:16.52#ibcon#about to read 6, iclass 14, count 0 2006.286.02:34:16.52#ibcon#read 6, iclass 14, count 0 2006.286.02:34:16.52#ibcon#end of sib2, iclass 14, count 0 2006.286.02:34:16.52#ibcon#*after write, iclass 14, count 0 2006.286.02:34:16.52#ibcon#*before return 0, iclass 14, count 0 2006.286.02:34:16.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:34:16.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:34:16.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.02:34:16.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.02:34:16.52$vck44/vb=4,5 2006.286.02:34:16.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.02:34:16.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.02:34:16.52#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:16.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:34:16.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:34:16.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:34:16.58#ibcon#enter wrdev, iclass 16, count 2 2006.286.02:34:16.58#ibcon#first serial, iclass 16, count 2 2006.286.02:34:16.58#ibcon#enter sib2, iclass 16, count 2 2006.286.02:34:16.58#ibcon#flushed, iclass 16, count 2 2006.286.02:34:16.58#ibcon#about to write, iclass 16, count 2 2006.286.02:34:16.58#ibcon#wrote, iclass 16, count 2 2006.286.02:34:16.58#ibcon#about to read 3, iclass 16, count 2 2006.286.02:34:16.60#ibcon#read 3, iclass 16, count 2 2006.286.02:34:16.60#ibcon#about to read 4, iclass 16, count 2 2006.286.02:34:16.60#ibcon#read 4, iclass 16, count 2 2006.286.02:34:16.60#ibcon#about to read 5, iclass 16, count 2 2006.286.02:34:16.60#ibcon#read 5, iclass 16, count 2 2006.286.02:34:16.60#ibcon#about to read 6, iclass 16, count 2 2006.286.02:34:16.60#ibcon#read 6, iclass 16, count 2 2006.286.02:34:16.60#ibcon#end of sib2, iclass 16, count 2 2006.286.02:34:16.60#ibcon#*mode == 0, iclass 16, count 2 2006.286.02:34:16.60#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.02:34:16.60#ibcon#[27=AT04-05\r\n] 2006.286.02:34:16.60#ibcon#*before write, iclass 16, count 2 2006.286.02:34:16.60#ibcon#enter sib2, iclass 16, count 2 2006.286.02:34:16.60#ibcon#flushed, iclass 16, count 2 2006.286.02:34:16.60#ibcon#about to write, iclass 16, count 2 2006.286.02:34:16.60#ibcon#wrote, iclass 16, count 2 2006.286.02:34:16.60#ibcon#about to read 3, iclass 16, count 2 2006.286.02:34:16.63#ibcon#read 3, iclass 16, count 2 2006.286.02:34:16.63#ibcon#about to read 4, iclass 16, count 2 2006.286.02:34:16.63#ibcon#read 4, iclass 16, count 2 2006.286.02:34:16.63#ibcon#about to read 5, iclass 16, count 2 2006.286.02:34:16.63#ibcon#read 5, iclass 16, count 2 2006.286.02:34:16.63#ibcon#about to read 6, iclass 16, count 2 2006.286.02:34:16.63#ibcon#read 6, iclass 16, count 2 2006.286.02:34:16.63#ibcon#end of sib2, iclass 16, count 2 2006.286.02:34:16.63#ibcon#*after write, iclass 16, count 2 2006.286.02:34:16.63#ibcon#*before return 0, iclass 16, count 2 2006.286.02:34:16.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:34:16.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.02:34:16.63#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.02:34:16.63#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:16.63#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:34:16.75#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:34:16.75#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:34:16.75#ibcon#enter wrdev, iclass 16, count 0 2006.286.02:34:16.75#ibcon#first serial, iclass 16, count 0 2006.286.02:34:16.75#ibcon#enter sib2, iclass 16, count 0 2006.286.02:34:16.75#ibcon#flushed, iclass 16, count 0 2006.286.02:34:16.75#ibcon#about to write, iclass 16, count 0 2006.286.02:34:16.75#ibcon#wrote, iclass 16, count 0 2006.286.02:34:16.75#ibcon#about to read 3, iclass 16, count 0 2006.286.02:34:16.77#ibcon#read 3, iclass 16, count 0 2006.286.02:34:16.77#ibcon#about to read 4, iclass 16, count 0 2006.286.02:34:16.77#ibcon#read 4, iclass 16, count 0 2006.286.02:34:16.77#ibcon#about to read 5, iclass 16, count 0 2006.286.02:34:16.77#ibcon#read 5, iclass 16, count 0 2006.286.02:34:16.77#ibcon#about to read 6, iclass 16, count 0 2006.286.02:34:16.77#ibcon#read 6, iclass 16, count 0 2006.286.02:34:16.77#ibcon#end of sib2, iclass 16, count 0 2006.286.02:34:16.77#ibcon#*mode == 0, iclass 16, count 0 2006.286.02:34:16.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.02:34:16.77#ibcon#[27=USB\r\n] 2006.286.02:34:16.77#ibcon#*before write, iclass 16, count 0 2006.286.02:34:16.77#ibcon#enter sib2, iclass 16, count 0 2006.286.02:34:16.77#ibcon#flushed, iclass 16, count 0 2006.286.02:34:16.77#ibcon#about to write, iclass 16, count 0 2006.286.02:34:16.77#ibcon#wrote, iclass 16, count 0 2006.286.02:34:16.77#ibcon#about to read 3, iclass 16, count 0 2006.286.02:34:16.80#ibcon#read 3, iclass 16, count 0 2006.286.02:34:16.80#ibcon#about to read 4, iclass 16, count 0 2006.286.02:34:16.80#ibcon#read 4, iclass 16, count 0 2006.286.02:34:16.80#ibcon#about to read 5, iclass 16, count 0 2006.286.02:34:16.80#ibcon#read 5, iclass 16, count 0 2006.286.02:34:16.80#ibcon#about to read 6, iclass 16, count 0 2006.286.02:34:16.80#ibcon#read 6, iclass 16, count 0 2006.286.02:34:16.80#ibcon#end of sib2, iclass 16, count 0 2006.286.02:34:16.80#ibcon#*after write, iclass 16, count 0 2006.286.02:34:16.80#ibcon#*before return 0, iclass 16, count 0 2006.286.02:34:16.80#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:34:16.80#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.02:34:16.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.02:34:16.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.02:34:16.80$vck44/vblo=5,709.99 2006.286.02:34:16.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.02:34:16.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.02:34:16.80#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:16.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:34:16.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:34:16.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:34:16.80#ibcon#enter wrdev, iclass 18, count 0 2006.286.02:34:16.80#ibcon#first serial, iclass 18, count 0 2006.286.02:34:16.80#ibcon#enter sib2, iclass 18, count 0 2006.286.02:34:16.80#ibcon#flushed, iclass 18, count 0 2006.286.02:34:16.80#ibcon#about to write, iclass 18, count 0 2006.286.02:34:16.80#ibcon#wrote, iclass 18, count 0 2006.286.02:34:16.80#ibcon#about to read 3, iclass 18, count 0 2006.286.02:34:16.82#ibcon#read 3, iclass 18, count 0 2006.286.02:34:16.82#ibcon#about to read 4, iclass 18, count 0 2006.286.02:34:16.82#ibcon#read 4, iclass 18, count 0 2006.286.02:34:16.82#ibcon#about to read 5, iclass 18, count 0 2006.286.02:34:16.82#ibcon#read 5, iclass 18, count 0 2006.286.02:34:16.82#ibcon#about to read 6, iclass 18, count 0 2006.286.02:34:16.82#ibcon#read 6, iclass 18, count 0 2006.286.02:34:16.82#ibcon#end of sib2, iclass 18, count 0 2006.286.02:34:16.82#ibcon#*mode == 0, iclass 18, count 0 2006.286.02:34:16.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.02:34:16.82#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.02:34:16.82#ibcon#*before write, iclass 18, count 0 2006.286.02:34:16.82#ibcon#enter sib2, iclass 18, count 0 2006.286.02:34:16.82#ibcon#flushed, iclass 18, count 0 2006.286.02:34:16.82#ibcon#about to write, iclass 18, count 0 2006.286.02:34:16.82#ibcon#wrote, iclass 18, count 0 2006.286.02:34:16.82#ibcon#about to read 3, iclass 18, count 0 2006.286.02:34:16.86#ibcon#read 3, iclass 18, count 0 2006.286.02:34:16.86#ibcon#about to read 4, iclass 18, count 0 2006.286.02:34:16.86#ibcon#read 4, iclass 18, count 0 2006.286.02:34:16.86#ibcon#about to read 5, iclass 18, count 0 2006.286.02:34:16.86#ibcon#read 5, iclass 18, count 0 2006.286.02:34:16.86#ibcon#about to read 6, iclass 18, count 0 2006.286.02:34:16.86#ibcon#read 6, iclass 18, count 0 2006.286.02:34:16.86#ibcon#end of sib2, iclass 18, count 0 2006.286.02:34:16.86#ibcon#*after write, iclass 18, count 0 2006.286.02:34:16.86#ibcon#*before return 0, iclass 18, count 0 2006.286.02:34:16.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:34:16.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.02:34:16.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.02:34:16.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.02:34:16.86$vck44/vb=5,4 2006.286.02:34:16.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.02:34:16.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.02:34:16.86#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:16.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:34:16.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:34:16.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:34:16.92#ibcon#enter wrdev, iclass 20, count 2 2006.286.02:34:16.92#ibcon#first serial, iclass 20, count 2 2006.286.02:34:16.92#ibcon#enter sib2, iclass 20, count 2 2006.286.02:34:16.92#ibcon#flushed, iclass 20, count 2 2006.286.02:34:16.92#ibcon#about to write, iclass 20, count 2 2006.286.02:34:16.92#ibcon#wrote, iclass 20, count 2 2006.286.02:34:16.92#ibcon#about to read 3, iclass 20, count 2 2006.286.02:34:16.94#ibcon#read 3, iclass 20, count 2 2006.286.02:34:16.94#ibcon#about to read 4, iclass 20, count 2 2006.286.02:34:16.94#ibcon#read 4, iclass 20, count 2 2006.286.02:34:16.94#ibcon#about to read 5, iclass 20, count 2 2006.286.02:34:16.94#ibcon#read 5, iclass 20, count 2 2006.286.02:34:16.94#ibcon#about to read 6, iclass 20, count 2 2006.286.02:34:16.94#ibcon#read 6, iclass 20, count 2 2006.286.02:34:16.94#ibcon#end of sib2, iclass 20, count 2 2006.286.02:34:16.94#ibcon#*mode == 0, iclass 20, count 2 2006.286.02:34:16.94#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.02:34:16.94#ibcon#[27=AT05-04\r\n] 2006.286.02:34:16.94#ibcon#*before write, iclass 20, count 2 2006.286.02:34:16.94#ibcon#enter sib2, iclass 20, count 2 2006.286.02:34:16.94#ibcon#flushed, iclass 20, count 2 2006.286.02:34:16.94#ibcon#about to write, iclass 20, count 2 2006.286.02:34:16.94#ibcon#wrote, iclass 20, count 2 2006.286.02:34:16.94#ibcon#about to read 3, iclass 20, count 2 2006.286.02:34:16.97#ibcon#read 3, iclass 20, count 2 2006.286.02:34:16.97#ibcon#about to read 4, iclass 20, count 2 2006.286.02:34:16.97#ibcon#read 4, iclass 20, count 2 2006.286.02:34:16.97#ibcon#about to read 5, iclass 20, count 2 2006.286.02:34:16.97#ibcon#read 5, iclass 20, count 2 2006.286.02:34:16.97#ibcon#about to read 6, iclass 20, count 2 2006.286.02:34:16.97#ibcon#read 6, iclass 20, count 2 2006.286.02:34:16.97#ibcon#end of sib2, iclass 20, count 2 2006.286.02:34:16.97#ibcon#*after write, iclass 20, count 2 2006.286.02:34:16.97#ibcon#*before return 0, iclass 20, count 2 2006.286.02:34:16.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:34:16.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.02:34:16.97#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.02:34:16.97#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:16.97#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:34:17.09#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:34:17.09#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:34:17.09#ibcon#enter wrdev, iclass 20, count 0 2006.286.02:34:17.09#ibcon#first serial, iclass 20, count 0 2006.286.02:34:17.09#ibcon#enter sib2, iclass 20, count 0 2006.286.02:34:17.09#ibcon#flushed, iclass 20, count 0 2006.286.02:34:17.09#ibcon#about to write, iclass 20, count 0 2006.286.02:34:17.09#ibcon#wrote, iclass 20, count 0 2006.286.02:34:17.09#ibcon#about to read 3, iclass 20, count 0 2006.286.02:34:17.11#ibcon#read 3, iclass 20, count 0 2006.286.02:34:17.11#ibcon#about to read 4, iclass 20, count 0 2006.286.02:34:17.11#ibcon#read 4, iclass 20, count 0 2006.286.02:34:17.11#ibcon#about to read 5, iclass 20, count 0 2006.286.02:34:17.11#ibcon#read 5, iclass 20, count 0 2006.286.02:34:17.11#ibcon#about to read 6, iclass 20, count 0 2006.286.02:34:17.11#ibcon#read 6, iclass 20, count 0 2006.286.02:34:17.11#ibcon#end of sib2, iclass 20, count 0 2006.286.02:34:17.11#ibcon#*mode == 0, iclass 20, count 0 2006.286.02:34:17.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.02:34:17.11#ibcon#[27=USB\r\n] 2006.286.02:34:17.11#ibcon#*before write, iclass 20, count 0 2006.286.02:34:17.11#ibcon#enter sib2, iclass 20, count 0 2006.286.02:34:17.11#ibcon#flushed, iclass 20, count 0 2006.286.02:34:17.11#ibcon#about to write, iclass 20, count 0 2006.286.02:34:17.11#ibcon#wrote, iclass 20, count 0 2006.286.02:34:17.11#ibcon#about to read 3, iclass 20, count 0 2006.286.02:34:17.14#ibcon#read 3, iclass 20, count 0 2006.286.02:34:17.14#ibcon#about to read 4, iclass 20, count 0 2006.286.02:34:17.14#ibcon#read 4, iclass 20, count 0 2006.286.02:34:17.14#ibcon#about to read 5, iclass 20, count 0 2006.286.02:34:17.14#ibcon#read 5, iclass 20, count 0 2006.286.02:34:17.14#ibcon#about to read 6, iclass 20, count 0 2006.286.02:34:17.14#ibcon#read 6, iclass 20, count 0 2006.286.02:34:17.14#ibcon#end of sib2, iclass 20, count 0 2006.286.02:34:17.14#ibcon#*after write, iclass 20, count 0 2006.286.02:34:17.14#ibcon#*before return 0, iclass 20, count 0 2006.286.02:34:17.14#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:34:17.14#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.02:34:17.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.02:34:17.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.02:34:17.14$vck44/vblo=6,719.99 2006.286.02:34:17.14#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.02:34:17.14#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.02:34:17.14#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:17.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:34:17.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:34:17.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:34:17.14#ibcon#enter wrdev, iclass 22, count 0 2006.286.02:34:17.14#ibcon#first serial, iclass 22, count 0 2006.286.02:34:17.14#ibcon#enter sib2, iclass 22, count 0 2006.286.02:34:17.14#ibcon#flushed, iclass 22, count 0 2006.286.02:34:17.14#ibcon#about to write, iclass 22, count 0 2006.286.02:34:17.14#ibcon#wrote, iclass 22, count 0 2006.286.02:34:17.14#ibcon#about to read 3, iclass 22, count 0 2006.286.02:34:17.16#ibcon#read 3, iclass 22, count 0 2006.286.02:34:17.16#ibcon#about to read 4, iclass 22, count 0 2006.286.02:34:17.16#ibcon#read 4, iclass 22, count 0 2006.286.02:34:17.16#ibcon#about to read 5, iclass 22, count 0 2006.286.02:34:17.16#ibcon#read 5, iclass 22, count 0 2006.286.02:34:17.16#ibcon#about to read 6, iclass 22, count 0 2006.286.02:34:17.16#ibcon#read 6, iclass 22, count 0 2006.286.02:34:17.16#ibcon#end of sib2, iclass 22, count 0 2006.286.02:34:17.16#ibcon#*mode == 0, iclass 22, count 0 2006.286.02:34:17.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.02:34:17.16#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.02:34:17.16#ibcon#*before write, iclass 22, count 0 2006.286.02:34:17.16#ibcon#enter sib2, iclass 22, count 0 2006.286.02:34:17.16#ibcon#flushed, iclass 22, count 0 2006.286.02:34:17.16#ibcon#about to write, iclass 22, count 0 2006.286.02:34:17.16#ibcon#wrote, iclass 22, count 0 2006.286.02:34:17.16#ibcon#about to read 3, iclass 22, count 0 2006.286.02:34:17.20#ibcon#read 3, iclass 22, count 0 2006.286.02:34:17.20#ibcon#about to read 4, iclass 22, count 0 2006.286.02:34:17.20#ibcon#read 4, iclass 22, count 0 2006.286.02:34:17.20#ibcon#about to read 5, iclass 22, count 0 2006.286.02:34:17.20#ibcon#read 5, iclass 22, count 0 2006.286.02:34:17.20#ibcon#about to read 6, iclass 22, count 0 2006.286.02:34:17.20#ibcon#read 6, iclass 22, count 0 2006.286.02:34:17.20#ibcon#end of sib2, iclass 22, count 0 2006.286.02:34:17.20#ibcon#*after write, iclass 22, count 0 2006.286.02:34:17.20#ibcon#*before return 0, iclass 22, count 0 2006.286.02:34:17.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:34:17.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.02:34:17.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.02:34:17.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.02:34:17.20$vck44/vb=6,3 2006.286.02:34:17.20#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.02:34:17.20#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.02:34:17.20#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:17.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:34:17.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:34:17.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:34:17.26#ibcon#enter wrdev, iclass 24, count 2 2006.286.02:34:17.26#ibcon#first serial, iclass 24, count 2 2006.286.02:34:17.26#ibcon#enter sib2, iclass 24, count 2 2006.286.02:34:17.26#ibcon#flushed, iclass 24, count 2 2006.286.02:34:17.26#ibcon#about to write, iclass 24, count 2 2006.286.02:34:17.26#ibcon#wrote, iclass 24, count 2 2006.286.02:34:17.26#ibcon#about to read 3, iclass 24, count 2 2006.286.02:34:17.28#ibcon#read 3, iclass 24, count 2 2006.286.02:34:17.28#ibcon#about to read 4, iclass 24, count 2 2006.286.02:34:17.28#ibcon#read 4, iclass 24, count 2 2006.286.02:34:17.28#ibcon#about to read 5, iclass 24, count 2 2006.286.02:34:17.28#ibcon#read 5, iclass 24, count 2 2006.286.02:34:17.28#ibcon#about to read 6, iclass 24, count 2 2006.286.02:34:17.28#ibcon#read 6, iclass 24, count 2 2006.286.02:34:17.28#ibcon#end of sib2, iclass 24, count 2 2006.286.02:34:17.28#ibcon#*mode == 0, iclass 24, count 2 2006.286.02:34:17.28#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.02:34:17.28#ibcon#[27=AT06-03\r\n] 2006.286.02:34:17.28#ibcon#*before write, iclass 24, count 2 2006.286.02:34:17.28#ibcon#enter sib2, iclass 24, count 2 2006.286.02:34:17.28#ibcon#flushed, iclass 24, count 2 2006.286.02:34:17.28#ibcon#about to write, iclass 24, count 2 2006.286.02:34:17.28#ibcon#wrote, iclass 24, count 2 2006.286.02:34:17.28#ibcon#about to read 3, iclass 24, count 2 2006.286.02:34:17.31#ibcon#read 3, iclass 24, count 2 2006.286.02:34:17.31#ibcon#about to read 4, iclass 24, count 2 2006.286.02:34:17.31#ibcon#read 4, iclass 24, count 2 2006.286.02:34:17.31#ibcon#about to read 5, iclass 24, count 2 2006.286.02:34:17.31#ibcon#read 5, iclass 24, count 2 2006.286.02:34:17.31#ibcon#about to read 6, iclass 24, count 2 2006.286.02:34:17.31#ibcon#read 6, iclass 24, count 2 2006.286.02:34:17.31#ibcon#end of sib2, iclass 24, count 2 2006.286.02:34:17.31#ibcon#*after write, iclass 24, count 2 2006.286.02:34:17.31#ibcon#*before return 0, iclass 24, count 2 2006.286.02:34:17.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:34:17.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.02:34:17.31#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.02:34:17.31#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:17.31#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:34:17.43#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:34:17.43#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:34:17.43#ibcon#enter wrdev, iclass 24, count 0 2006.286.02:34:17.43#ibcon#first serial, iclass 24, count 0 2006.286.02:34:17.43#ibcon#enter sib2, iclass 24, count 0 2006.286.02:34:17.43#ibcon#flushed, iclass 24, count 0 2006.286.02:34:17.43#ibcon#about to write, iclass 24, count 0 2006.286.02:34:17.43#ibcon#wrote, iclass 24, count 0 2006.286.02:34:17.43#ibcon#about to read 3, iclass 24, count 0 2006.286.02:34:17.45#ibcon#read 3, iclass 24, count 0 2006.286.02:34:17.45#ibcon#about to read 4, iclass 24, count 0 2006.286.02:34:17.45#ibcon#read 4, iclass 24, count 0 2006.286.02:34:17.45#ibcon#about to read 5, iclass 24, count 0 2006.286.02:34:17.45#ibcon#read 5, iclass 24, count 0 2006.286.02:34:17.45#ibcon#about to read 6, iclass 24, count 0 2006.286.02:34:17.45#ibcon#read 6, iclass 24, count 0 2006.286.02:34:17.45#ibcon#end of sib2, iclass 24, count 0 2006.286.02:34:17.45#ibcon#*mode == 0, iclass 24, count 0 2006.286.02:34:17.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.02:34:17.45#ibcon#[27=USB\r\n] 2006.286.02:34:17.45#ibcon#*before write, iclass 24, count 0 2006.286.02:34:17.45#ibcon#enter sib2, iclass 24, count 0 2006.286.02:34:17.45#ibcon#flushed, iclass 24, count 0 2006.286.02:34:17.45#ibcon#about to write, iclass 24, count 0 2006.286.02:34:17.45#ibcon#wrote, iclass 24, count 0 2006.286.02:34:17.45#ibcon#about to read 3, iclass 24, count 0 2006.286.02:34:17.48#ibcon#read 3, iclass 24, count 0 2006.286.02:34:17.48#ibcon#about to read 4, iclass 24, count 0 2006.286.02:34:17.48#ibcon#read 4, iclass 24, count 0 2006.286.02:34:17.48#ibcon#about to read 5, iclass 24, count 0 2006.286.02:34:17.48#ibcon#read 5, iclass 24, count 0 2006.286.02:34:17.48#ibcon#about to read 6, iclass 24, count 0 2006.286.02:34:17.48#ibcon#read 6, iclass 24, count 0 2006.286.02:34:17.48#ibcon#end of sib2, iclass 24, count 0 2006.286.02:34:17.48#ibcon#*after write, iclass 24, count 0 2006.286.02:34:17.48#ibcon#*before return 0, iclass 24, count 0 2006.286.02:34:17.48#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:34:17.48#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.02:34:17.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.02:34:17.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.02:34:17.48$vck44/vblo=7,734.99 2006.286.02:34:17.48#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.02:34:17.48#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.02:34:17.48#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:17.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:34:17.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:34:17.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:34:17.48#ibcon#enter wrdev, iclass 26, count 0 2006.286.02:34:17.48#ibcon#first serial, iclass 26, count 0 2006.286.02:34:17.48#ibcon#enter sib2, iclass 26, count 0 2006.286.02:34:17.48#ibcon#flushed, iclass 26, count 0 2006.286.02:34:17.48#ibcon#about to write, iclass 26, count 0 2006.286.02:34:17.48#ibcon#wrote, iclass 26, count 0 2006.286.02:34:17.48#ibcon#about to read 3, iclass 26, count 0 2006.286.02:34:17.50#ibcon#read 3, iclass 26, count 0 2006.286.02:34:17.50#ibcon#about to read 4, iclass 26, count 0 2006.286.02:34:17.50#ibcon#read 4, iclass 26, count 0 2006.286.02:34:17.50#ibcon#about to read 5, iclass 26, count 0 2006.286.02:34:17.50#ibcon#read 5, iclass 26, count 0 2006.286.02:34:17.50#ibcon#about to read 6, iclass 26, count 0 2006.286.02:34:17.50#ibcon#read 6, iclass 26, count 0 2006.286.02:34:17.50#ibcon#end of sib2, iclass 26, count 0 2006.286.02:34:17.50#ibcon#*mode == 0, iclass 26, count 0 2006.286.02:34:17.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.02:34:17.50#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.02:34:17.50#ibcon#*before write, iclass 26, count 0 2006.286.02:34:17.50#ibcon#enter sib2, iclass 26, count 0 2006.286.02:34:17.50#ibcon#flushed, iclass 26, count 0 2006.286.02:34:17.50#ibcon#about to write, iclass 26, count 0 2006.286.02:34:17.50#ibcon#wrote, iclass 26, count 0 2006.286.02:34:17.50#ibcon#about to read 3, iclass 26, count 0 2006.286.02:34:17.54#ibcon#read 3, iclass 26, count 0 2006.286.02:34:17.54#ibcon#about to read 4, iclass 26, count 0 2006.286.02:34:17.54#ibcon#read 4, iclass 26, count 0 2006.286.02:34:17.54#ibcon#about to read 5, iclass 26, count 0 2006.286.02:34:17.54#ibcon#read 5, iclass 26, count 0 2006.286.02:34:17.54#ibcon#about to read 6, iclass 26, count 0 2006.286.02:34:17.54#ibcon#read 6, iclass 26, count 0 2006.286.02:34:17.54#ibcon#end of sib2, iclass 26, count 0 2006.286.02:34:17.54#ibcon#*after write, iclass 26, count 0 2006.286.02:34:17.54#ibcon#*before return 0, iclass 26, count 0 2006.286.02:34:17.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:34:17.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.02:34:17.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.02:34:17.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.02:34:17.54$vck44/vb=7,4 2006.286.02:34:17.54#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.02:34:17.54#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.02:34:17.54#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:17.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:34:17.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:34:17.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:34:17.60#ibcon#enter wrdev, iclass 28, count 2 2006.286.02:34:17.60#ibcon#first serial, iclass 28, count 2 2006.286.02:34:17.60#ibcon#enter sib2, iclass 28, count 2 2006.286.02:34:17.60#ibcon#flushed, iclass 28, count 2 2006.286.02:34:17.60#ibcon#about to write, iclass 28, count 2 2006.286.02:34:17.60#ibcon#wrote, iclass 28, count 2 2006.286.02:34:17.60#ibcon#about to read 3, iclass 28, count 2 2006.286.02:34:17.62#ibcon#read 3, iclass 28, count 2 2006.286.02:34:17.62#ibcon#about to read 4, iclass 28, count 2 2006.286.02:34:17.62#ibcon#read 4, iclass 28, count 2 2006.286.02:34:17.62#ibcon#about to read 5, iclass 28, count 2 2006.286.02:34:17.62#ibcon#read 5, iclass 28, count 2 2006.286.02:34:17.62#ibcon#about to read 6, iclass 28, count 2 2006.286.02:34:17.62#ibcon#read 6, iclass 28, count 2 2006.286.02:34:17.62#ibcon#end of sib2, iclass 28, count 2 2006.286.02:34:17.62#ibcon#*mode == 0, iclass 28, count 2 2006.286.02:34:17.62#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.02:34:17.62#ibcon#[27=AT07-04\r\n] 2006.286.02:34:17.62#ibcon#*before write, iclass 28, count 2 2006.286.02:34:17.62#ibcon#enter sib2, iclass 28, count 2 2006.286.02:34:17.62#ibcon#flushed, iclass 28, count 2 2006.286.02:34:17.62#ibcon#about to write, iclass 28, count 2 2006.286.02:34:17.62#ibcon#wrote, iclass 28, count 2 2006.286.02:34:17.62#ibcon#about to read 3, iclass 28, count 2 2006.286.02:34:17.65#ibcon#read 3, iclass 28, count 2 2006.286.02:34:17.65#ibcon#about to read 4, iclass 28, count 2 2006.286.02:34:17.65#ibcon#read 4, iclass 28, count 2 2006.286.02:34:17.65#ibcon#about to read 5, iclass 28, count 2 2006.286.02:34:17.65#ibcon#read 5, iclass 28, count 2 2006.286.02:34:17.65#ibcon#about to read 6, iclass 28, count 2 2006.286.02:34:17.65#ibcon#read 6, iclass 28, count 2 2006.286.02:34:17.65#ibcon#end of sib2, iclass 28, count 2 2006.286.02:34:17.65#ibcon#*after write, iclass 28, count 2 2006.286.02:34:17.65#ibcon#*before return 0, iclass 28, count 2 2006.286.02:34:17.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:34:17.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:34:17.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.02:34:17.65#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:17.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:34:17.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:34:17.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:34:17.77#ibcon#enter wrdev, iclass 28, count 0 2006.286.02:34:17.77#ibcon#first serial, iclass 28, count 0 2006.286.02:34:17.77#ibcon#enter sib2, iclass 28, count 0 2006.286.02:34:17.77#ibcon#flushed, iclass 28, count 0 2006.286.02:34:17.77#ibcon#about to write, iclass 28, count 0 2006.286.02:34:17.77#ibcon#wrote, iclass 28, count 0 2006.286.02:34:17.77#ibcon#about to read 3, iclass 28, count 0 2006.286.02:34:17.79#ibcon#read 3, iclass 28, count 0 2006.286.02:34:17.79#ibcon#about to read 4, iclass 28, count 0 2006.286.02:34:17.79#ibcon#read 4, iclass 28, count 0 2006.286.02:34:17.79#ibcon#about to read 5, iclass 28, count 0 2006.286.02:34:17.79#ibcon#read 5, iclass 28, count 0 2006.286.02:34:17.79#ibcon#about to read 6, iclass 28, count 0 2006.286.02:34:17.79#ibcon#read 6, iclass 28, count 0 2006.286.02:34:17.79#ibcon#end of sib2, iclass 28, count 0 2006.286.02:34:17.79#ibcon#*mode == 0, iclass 28, count 0 2006.286.02:34:17.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.02:34:17.79#ibcon#[27=USB\r\n] 2006.286.02:34:17.79#ibcon#*before write, iclass 28, count 0 2006.286.02:34:17.79#ibcon#enter sib2, iclass 28, count 0 2006.286.02:34:17.79#ibcon#flushed, iclass 28, count 0 2006.286.02:34:17.79#ibcon#about to write, iclass 28, count 0 2006.286.02:34:17.79#ibcon#wrote, iclass 28, count 0 2006.286.02:34:17.79#ibcon#about to read 3, iclass 28, count 0 2006.286.02:34:17.82#ibcon#read 3, iclass 28, count 0 2006.286.02:34:17.82#ibcon#about to read 4, iclass 28, count 0 2006.286.02:34:17.82#ibcon#read 4, iclass 28, count 0 2006.286.02:34:17.82#ibcon#about to read 5, iclass 28, count 0 2006.286.02:34:17.82#ibcon#read 5, iclass 28, count 0 2006.286.02:34:17.82#ibcon#about to read 6, iclass 28, count 0 2006.286.02:34:17.82#ibcon#read 6, iclass 28, count 0 2006.286.02:34:17.82#ibcon#end of sib2, iclass 28, count 0 2006.286.02:34:17.82#ibcon#*after write, iclass 28, count 0 2006.286.02:34:17.82#ibcon#*before return 0, iclass 28, count 0 2006.286.02:34:17.82#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:34:17.82#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:34:17.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.02:34:17.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.02:34:17.82$vck44/vblo=8,744.99 2006.286.02:34:17.82#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.02:34:17.82#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.02:34:17.82#ibcon#ireg 17 cls_cnt 0 2006.286.02:34:17.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:34:17.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:34:17.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:34:17.82#ibcon#enter wrdev, iclass 30, count 0 2006.286.02:34:17.82#ibcon#first serial, iclass 30, count 0 2006.286.02:34:17.82#ibcon#enter sib2, iclass 30, count 0 2006.286.02:34:17.82#ibcon#flushed, iclass 30, count 0 2006.286.02:34:17.82#ibcon#about to write, iclass 30, count 0 2006.286.02:34:17.82#ibcon#wrote, iclass 30, count 0 2006.286.02:34:17.82#ibcon#about to read 3, iclass 30, count 0 2006.286.02:34:17.84#ibcon#read 3, iclass 30, count 0 2006.286.02:34:17.84#ibcon#about to read 4, iclass 30, count 0 2006.286.02:34:17.84#ibcon#read 4, iclass 30, count 0 2006.286.02:34:17.84#ibcon#about to read 5, iclass 30, count 0 2006.286.02:34:17.84#ibcon#read 5, iclass 30, count 0 2006.286.02:34:17.84#ibcon#about to read 6, iclass 30, count 0 2006.286.02:34:17.84#ibcon#read 6, iclass 30, count 0 2006.286.02:34:17.84#ibcon#end of sib2, iclass 30, count 0 2006.286.02:34:17.84#ibcon#*mode == 0, iclass 30, count 0 2006.286.02:34:17.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.02:34:17.84#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.02:34:17.84#ibcon#*before write, iclass 30, count 0 2006.286.02:34:17.84#ibcon#enter sib2, iclass 30, count 0 2006.286.02:34:17.84#ibcon#flushed, iclass 30, count 0 2006.286.02:34:17.84#ibcon#about to write, iclass 30, count 0 2006.286.02:34:17.84#ibcon#wrote, iclass 30, count 0 2006.286.02:34:17.84#ibcon#about to read 3, iclass 30, count 0 2006.286.02:34:17.88#ibcon#read 3, iclass 30, count 0 2006.286.02:34:17.88#ibcon#about to read 4, iclass 30, count 0 2006.286.02:34:17.88#ibcon#read 4, iclass 30, count 0 2006.286.02:34:17.88#ibcon#about to read 5, iclass 30, count 0 2006.286.02:34:17.88#ibcon#read 5, iclass 30, count 0 2006.286.02:34:17.88#ibcon#about to read 6, iclass 30, count 0 2006.286.02:34:17.88#ibcon#read 6, iclass 30, count 0 2006.286.02:34:17.88#ibcon#end of sib2, iclass 30, count 0 2006.286.02:34:17.88#ibcon#*after write, iclass 30, count 0 2006.286.02:34:17.88#ibcon#*before return 0, iclass 30, count 0 2006.286.02:34:17.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:34:17.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.02:34:17.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.02:34:17.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.02:34:17.88$vck44/vb=8,4 2006.286.02:34:17.88#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.02:34:17.88#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.02:34:17.88#ibcon#ireg 11 cls_cnt 2 2006.286.02:34:17.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:34:17.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:34:17.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:34:17.94#ibcon#enter wrdev, iclass 32, count 2 2006.286.02:34:17.94#ibcon#first serial, iclass 32, count 2 2006.286.02:34:17.94#ibcon#enter sib2, iclass 32, count 2 2006.286.02:34:17.94#ibcon#flushed, iclass 32, count 2 2006.286.02:34:17.94#ibcon#about to write, iclass 32, count 2 2006.286.02:34:17.94#ibcon#wrote, iclass 32, count 2 2006.286.02:34:17.94#ibcon#about to read 3, iclass 32, count 2 2006.286.02:34:17.96#ibcon#read 3, iclass 32, count 2 2006.286.02:34:17.96#ibcon#about to read 4, iclass 32, count 2 2006.286.02:34:17.96#ibcon#read 4, iclass 32, count 2 2006.286.02:34:17.96#ibcon#about to read 5, iclass 32, count 2 2006.286.02:34:17.96#ibcon#read 5, iclass 32, count 2 2006.286.02:34:17.96#ibcon#about to read 6, iclass 32, count 2 2006.286.02:34:17.96#ibcon#read 6, iclass 32, count 2 2006.286.02:34:17.96#ibcon#end of sib2, iclass 32, count 2 2006.286.02:34:17.96#ibcon#*mode == 0, iclass 32, count 2 2006.286.02:34:17.96#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.02:34:17.96#ibcon#[27=AT08-04\r\n] 2006.286.02:34:17.96#ibcon#*before write, iclass 32, count 2 2006.286.02:34:17.96#ibcon#enter sib2, iclass 32, count 2 2006.286.02:34:17.96#ibcon#flushed, iclass 32, count 2 2006.286.02:34:17.96#ibcon#about to write, iclass 32, count 2 2006.286.02:34:17.96#ibcon#wrote, iclass 32, count 2 2006.286.02:34:17.96#ibcon#about to read 3, iclass 32, count 2 2006.286.02:34:17.99#ibcon#read 3, iclass 32, count 2 2006.286.02:34:17.99#ibcon#about to read 4, iclass 32, count 2 2006.286.02:34:17.99#ibcon#read 4, iclass 32, count 2 2006.286.02:34:17.99#ibcon#about to read 5, iclass 32, count 2 2006.286.02:34:17.99#ibcon#read 5, iclass 32, count 2 2006.286.02:34:17.99#ibcon#about to read 6, iclass 32, count 2 2006.286.02:34:17.99#ibcon#read 6, iclass 32, count 2 2006.286.02:34:17.99#ibcon#end of sib2, iclass 32, count 2 2006.286.02:34:17.99#ibcon#*after write, iclass 32, count 2 2006.286.02:34:17.99#ibcon#*before return 0, iclass 32, count 2 2006.286.02:34:17.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:34:17.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.02:34:17.99#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.02:34:17.99#ibcon#ireg 7 cls_cnt 0 2006.286.02:34:17.99#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:34:18.11#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:34:18.11#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:34:18.11#ibcon#enter wrdev, iclass 32, count 0 2006.286.02:34:18.11#ibcon#first serial, iclass 32, count 0 2006.286.02:34:18.11#ibcon#enter sib2, iclass 32, count 0 2006.286.02:34:18.11#ibcon#flushed, iclass 32, count 0 2006.286.02:34:18.11#ibcon#about to write, iclass 32, count 0 2006.286.02:34:18.11#ibcon#wrote, iclass 32, count 0 2006.286.02:34:18.11#ibcon#about to read 3, iclass 32, count 0 2006.286.02:34:18.13#ibcon#read 3, iclass 32, count 0 2006.286.02:34:18.13#ibcon#about to read 4, iclass 32, count 0 2006.286.02:34:18.13#ibcon#read 4, iclass 32, count 0 2006.286.02:34:18.13#ibcon#about to read 5, iclass 32, count 0 2006.286.02:34:18.13#ibcon#read 5, iclass 32, count 0 2006.286.02:34:18.13#ibcon#about to read 6, iclass 32, count 0 2006.286.02:34:18.13#ibcon#read 6, iclass 32, count 0 2006.286.02:34:18.13#ibcon#end of sib2, iclass 32, count 0 2006.286.02:34:18.13#ibcon#*mode == 0, iclass 32, count 0 2006.286.02:34:18.13#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.02:34:18.13#ibcon#[27=USB\r\n] 2006.286.02:34:18.13#ibcon#*before write, iclass 32, count 0 2006.286.02:34:18.13#ibcon#enter sib2, iclass 32, count 0 2006.286.02:34:18.13#ibcon#flushed, iclass 32, count 0 2006.286.02:34:18.13#ibcon#about to write, iclass 32, count 0 2006.286.02:34:18.13#ibcon#wrote, iclass 32, count 0 2006.286.02:34:18.13#ibcon#about to read 3, iclass 32, count 0 2006.286.02:34:18.16#ibcon#read 3, iclass 32, count 0 2006.286.02:34:18.16#ibcon#about to read 4, iclass 32, count 0 2006.286.02:34:18.16#ibcon#read 4, iclass 32, count 0 2006.286.02:34:18.16#ibcon#about to read 5, iclass 32, count 0 2006.286.02:34:18.16#ibcon#read 5, iclass 32, count 0 2006.286.02:34:18.16#ibcon#about to read 6, iclass 32, count 0 2006.286.02:34:18.16#ibcon#read 6, iclass 32, count 0 2006.286.02:34:18.16#ibcon#end of sib2, iclass 32, count 0 2006.286.02:34:18.16#ibcon#*after write, iclass 32, count 0 2006.286.02:34:18.16#ibcon#*before return 0, iclass 32, count 0 2006.286.02:34:18.16#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:34:18.16#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.02:34:18.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.02:34:18.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.02:34:18.16$vck44/vabw=wide 2006.286.02:34:18.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.02:34:18.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.02:34:18.16#ibcon#ireg 8 cls_cnt 0 2006.286.02:34:18.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:34:18.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:34:18.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:34:18.16#ibcon#enter wrdev, iclass 34, count 0 2006.286.02:34:18.16#ibcon#first serial, iclass 34, count 0 2006.286.02:34:18.16#ibcon#enter sib2, iclass 34, count 0 2006.286.02:34:18.16#ibcon#flushed, iclass 34, count 0 2006.286.02:34:18.16#ibcon#about to write, iclass 34, count 0 2006.286.02:34:18.16#ibcon#wrote, iclass 34, count 0 2006.286.02:34:18.16#ibcon#about to read 3, iclass 34, count 0 2006.286.02:34:18.18#ibcon#read 3, iclass 34, count 0 2006.286.02:34:18.18#ibcon#about to read 4, iclass 34, count 0 2006.286.02:34:18.18#ibcon#read 4, iclass 34, count 0 2006.286.02:34:18.18#ibcon#about to read 5, iclass 34, count 0 2006.286.02:34:18.18#ibcon#read 5, iclass 34, count 0 2006.286.02:34:18.18#ibcon#about to read 6, iclass 34, count 0 2006.286.02:34:18.18#ibcon#read 6, iclass 34, count 0 2006.286.02:34:18.18#ibcon#end of sib2, iclass 34, count 0 2006.286.02:34:18.18#ibcon#*mode == 0, iclass 34, count 0 2006.286.02:34:18.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.02:34:18.18#ibcon#[25=BW32\r\n] 2006.286.02:34:18.18#ibcon#*before write, iclass 34, count 0 2006.286.02:34:18.18#ibcon#enter sib2, iclass 34, count 0 2006.286.02:34:18.18#ibcon#flushed, iclass 34, count 0 2006.286.02:34:18.18#ibcon#about to write, iclass 34, count 0 2006.286.02:34:18.18#ibcon#wrote, iclass 34, count 0 2006.286.02:34:18.18#ibcon#about to read 3, iclass 34, count 0 2006.286.02:34:18.21#ibcon#read 3, iclass 34, count 0 2006.286.02:34:18.21#ibcon#about to read 4, iclass 34, count 0 2006.286.02:34:18.21#ibcon#read 4, iclass 34, count 0 2006.286.02:34:18.21#ibcon#about to read 5, iclass 34, count 0 2006.286.02:34:18.21#ibcon#read 5, iclass 34, count 0 2006.286.02:34:18.21#ibcon#about to read 6, iclass 34, count 0 2006.286.02:34:18.21#ibcon#read 6, iclass 34, count 0 2006.286.02:34:18.21#ibcon#end of sib2, iclass 34, count 0 2006.286.02:34:18.21#ibcon#*after write, iclass 34, count 0 2006.286.02:34:18.21#ibcon#*before return 0, iclass 34, count 0 2006.286.02:34:18.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:34:18.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.02:34:18.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.02:34:18.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.02:34:18.21$vck44/vbbw=wide 2006.286.02:34:18.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.02:34:18.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.02:34:18.21#ibcon#ireg 8 cls_cnt 0 2006.286.02:34:18.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:34:18.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:34:18.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:34:18.28#ibcon#enter wrdev, iclass 36, count 0 2006.286.02:34:18.28#ibcon#first serial, iclass 36, count 0 2006.286.02:34:18.28#ibcon#enter sib2, iclass 36, count 0 2006.286.02:34:18.28#ibcon#flushed, iclass 36, count 0 2006.286.02:34:18.28#ibcon#about to write, iclass 36, count 0 2006.286.02:34:18.28#ibcon#wrote, iclass 36, count 0 2006.286.02:34:18.28#ibcon#about to read 3, iclass 36, count 0 2006.286.02:34:18.30#ibcon#read 3, iclass 36, count 0 2006.286.02:34:18.30#ibcon#about to read 4, iclass 36, count 0 2006.286.02:34:18.30#ibcon#read 4, iclass 36, count 0 2006.286.02:34:18.30#ibcon#about to read 5, iclass 36, count 0 2006.286.02:34:18.30#ibcon#read 5, iclass 36, count 0 2006.286.02:34:18.30#ibcon#about to read 6, iclass 36, count 0 2006.286.02:34:18.30#ibcon#read 6, iclass 36, count 0 2006.286.02:34:18.30#ibcon#end of sib2, iclass 36, count 0 2006.286.02:34:18.30#ibcon#*mode == 0, iclass 36, count 0 2006.286.02:34:18.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.02:34:18.30#ibcon#[27=BW32\r\n] 2006.286.02:34:18.30#ibcon#*before write, iclass 36, count 0 2006.286.02:34:18.30#ibcon#enter sib2, iclass 36, count 0 2006.286.02:34:18.30#ibcon#flushed, iclass 36, count 0 2006.286.02:34:18.30#ibcon#about to write, iclass 36, count 0 2006.286.02:34:18.30#ibcon#wrote, iclass 36, count 0 2006.286.02:34:18.30#ibcon#about to read 3, iclass 36, count 0 2006.286.02:34:18.33#ibcon#read 3, iclass 36, count 0 2006.286.02:34:18.33#ibcon#about to read 4, iclass 36, count 0 2006.286.02:34:18.33#ibcon#read 4, iclass 36, count 0 2006.286.02:34:18.33#ibcon#about to read 5, iclass 36, count 0 2006.286.02:34:18.33#ibcon#read 5, iclass 36, count 0 2006.286.02:34:18.33#ibcon#about to read 6, iclass 36, count 0 2006.286.02:34:18.33#ibcon#read 6, iclass 36, count 0 2006.286.02:34:18.33#ibcon#end of sib2, iclass 36, count 0 2006.286.02:34:18.33#ibcon#*after write, iclass 36, count 0 2006.286.02:34:18.33#ibcon#*before return 0, iclass 36, count 0 2006.286.02:34:18.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:34:18.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:34:18.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.02:34:18.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.02:34:18.33$setupk4/ifdk4 2006.286.02:34:18.33$ifdk4/lo= 2006.286.02:34:18.33$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.02:34:18.33$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.02:34:18.33$ifdk4/patch= 2006.286.02:34:18.33$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.02:34:18.33$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.02:34:18.33$setupk4/!*+20s 2006.286.02:34:21.29#abcon#<5=/03 2.7 6.4 21.39 791015.8\r\n> 2006.286.02:34:21.31#abcon#{5=INTERFACE CLEAR} 2006.286.02:34:21.37#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:34:31.46#abcon#<5=/03 2.8 6.4 21.39 791015.9\r\n> 2006.286.02:34:31.48#abcon#{5=INTERFACE CLEAR} 2006.286.02:34:31.54#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:34:32.84$setupk4/"tpicd 2006.286.02:34:32.84$setupk4/echo=off 2006.286.02:34:32.84$setupk4/xlog=off 2006.286.02:34:32.84:!2006.286.02:39:08 2006.286.02:35:27.14#trakl#Source acquired 2006.286.02:35:29.14#flagr#flagr/antenna,acquired 2006.286.02:39:08.02:preob 2006.286.02:39:09.15/onsource/TRACKING 2006.286.02:39:09.15:!2006.286.02:39:18 2006.286.02:39:18.02:"tape 2006.286.02:39:18.02:"st=record 2006.286.02:39:18.02:data_valid=on 2006.286.02:39:18.02:midob 2006.286.02:39:19.15/onsource/TRACKING 2006.286.02:39:19.15/wx/21.30,1015.8,80 2006.286.02:39:19.34/cable/+6.5001E-03 2006.286.02:39:20.43/va/01,07,usb,yes,51,55 2006.286.02:39:20.43/va/02,06,usb,yes,51,52 2006.286.02:39:20.43/va/03,07,usb,yes,51,54 2006.286.02:39:20.43/va/04,06,usb,yes,53,56 2006.286.02:39:20.43/va/05,03,usb,yes,52,53 2006.286.02:39:20.43/va/06,04,usb,yes,48,47 2006.286.02:39:20.43/va/07,04,usb,yes,48,49 2006.286.02:39:20.43/va/08,03,usb,yes,49,58 2006.286.02:39:20.66/valo/01,524.99,yes,locked 2006.286.02:39:20.66/valo/02,534.99,yes,locked 2006.286.02:39:20.66/valo/03,564.99,yes,locked 2006.286.02:39:20.66/valo/04,624.99,yes,locked 2006.286.02:39:20.66/valo/05,734.99,yes,locked 2006.286.02:39:20.66/valo/06,814.99,yes,locked 2006.286.02:39:20.66/valo/07,864.99,yes,locked 2006.286.02:39:20.66/valo/08,884.99,yes,locked 2006.286.02:39:21.75/vb/01,04,usb,yes,45,42 2006.286.02:39:21.75/vb/02,05,usb,yes,42,41 2006.286.02:39:21.75/vb/03,04,usb,yes,43,48 2006.286.02:39:21.75/vb/04,05,usb,yes,44,43 2006.286.02:39:21.75/vb/05,04,usb,yes,40,43 2006.286.02:39:21.75/vb/06,03,usb,yes,56,51 2006.286.02:39:21.75/vb/07,04,usb,yes,45,46 2006.286.02:39:21.75/vb/08,04,usb,yes,41,46 2006.286.02:39:21.98/vblo/01,629.99,yes,locked 2006.286.02:39:21.98/vblo/02,634.99,yes,locked 2006.286.02:39:21.98/vblo/03,649.99,yes,locked 2006.286.02:39:21.98/vblo/04,679.99,yes,locked 2006.286.02:39:21.98/vblo/05,709.99,yes,locked 2006.286.02:39:21.98/vblo/06,719.99,yes,locked 2006.286.02:39:21.98/vblo/07,734.99,yes,locked 2006.286.02:39:21.98/vblo/08,744.99,yes,locked 2006.286.02:39:22.13/vabw/8 2006.286.02:39:22.28/vbbw/8 2006.286.02:39:22.37/xfe/off,on,12.0 2006.286.02:39:22.78/ifatt/23,28,28,28 2006.286.02:39:23.07/fmout-gps/S +2.68E-07 2006.286.02:39:23.09:!2006.286.02:40:58 2006.286.02:40:58.00:data_valid=off 2006.286.02:40:58.01:"et 2006.286.02:40:58.01:!+3s 2006.286.02:41:01.03:"tape 2006.286.02:41:01.03:postob 2006.286.02:41:01.10/cable/+6.4998E-03 2006.286.02:41:01.11/wx/21.28,1015.8,81 2006.286.02:41:01.16/fmout-gps/S +2.63E-07 2006.286.02:41:01.16:scan_name=286-0244,jd0610,350 2006.286.02:41:01.17:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.286.02:41:02.13#flagr#flagr/antenna,new-source 2006.286.02:41:02.14:checkk5 2006.286.02:41:02.55/chk_autoobs//k5ts1/ autoobs is running! 2006.286.02:41:02.96/chk_autoobs//k5ts2/ autoobs is running! 2006.286.02:41:03.35/chk_autoobs//k5ts3/ autoobs is running! 2006.286.02:41:03.76/chk_autoobs//k5ts4/ autoobs is running! 2006.286.02:41:04.15/chk_obsdata//k5ts1/T2860239??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.286.02:41:04.66/chk_obsdata//k5ts2/T2860239??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.286.02:41:05.11/chk_obsdata//k5ts3/T2860239??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.286.02:41:05.58/chk_obsdata//k5ts4/T2860239??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.286.02:41:06.29/k5log//k5ts1_log_newline 2006.286.02:41:07.23/k5log//k5ts2_log_newline 2006.286.02:41:08.28/k5log//k5ts3_log_newline 2006.286.02:41:09.29/k5log//k5ts4_log_newline 2006.286.02:41:09.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.02:41:09.31:setupk4=1 2006.286.02:41:09.31$setupk4/echo=on 2006.286.02:41:09.31$setupk4/pcalon 2006.286.02:41:09.31$pcalon/"no phase cal control is implemented here 2006.286.02:41:09.31$setupk4/"tpicd=stop 2006.286.02:41:09.31$setupk4/"rec=synch_on 2006.286.02:41:09.31$setupk4/"rec_mode=128 2006.286.02:41:09.31$setupk4/!* 2006.286.02:41:09.31$setupk4/recpk4 2006.286.02:41:09.31$recpk4/recpatch= 2006.286.02:41:09.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.02:41:09.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.02:41:09.31$setupk4/vck44 2006.286.02:41:09.32$vck44/valo=1,524.99 2006.286.02:41:09.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.02:41:09.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.02:41:09.32#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:09.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.02:41:09.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.02:41:09.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.02:41:09.32#ibcon#enter wrdev, iclass 16, count 0 2006.286.02:41:09.32#ibcon#first serial, iclass 16, count 0 2006.286.02:41:09.32#ibcon#enter sib2, iclass 16, count 0 2006.286.02:41:09.32#ibcon#flushed, iclass 16, count 0 2006.286.02:41:09.32#ibcon#about to write, iclass 16, count 0 2006.286.02:41:09.32#ibcon#wrote, iclass 16, count 0 2006.286.02:41:09.32#ibcon#about to read 3, iclass 16, count 0 2006.286.02:41:09.33#ibcon#read 3, iclass 16, count 0 2006.286.02:41:09.33#ibcon#about to read 4, iclass 16, count 0 2006.286.02:41:09.33#ibcon#read 4, iclass 16, count 0 2006.286.02:41:09.33#ibcon#about to read 5, iclass 16, count 0 2006.286.02:41:09.33#ibcon#read 5, iclass 16, count 0 2006.286.02:41:09.33#ibcon#about to read 6, iclass 16, count 0 2006.286.02:41:09.33#ibcon#read 6, iclass 16, count 0 2006.286.02:41:09.33#ibcon#end of sib2, iclass 16, count 0 2006.286.02:41:09.33#ibcon#*mode == 0, iclass 16, count 0 2006.286.02:41:09.33#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.02:41:09.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.02:41:09.33#ibcon#*before write, iclass 16, count 0 2006.286.02:41:09.33#ibcon#enter sib2, iclass 16, count 0 2006.286.02:41:09.33#ibcon#flushed, iclass 16, count 0 2006.286.02:41:09.33#ibcon#about to write, iclass 16, count 0 2006.286.02:41:09.33#ibcon#wrote, iclass 16, count 0 2006.286.02:41:09.33#ibcon#about to read 3, iclass 16, count 0 2006.286.02:41:09.38#ibcon#read 3, iclass 16, count 0 2006.286.02:41:09.38#ibcon#about to read 4, iclass 16, count 0 2006.286.02:41:09.38#ibcon#read 4, iclass 16, count 0 2006.286.02:41:09.38#ibcon#about to read 5, iclass 16, count 0 2006.286.02:41:09.38#ibcon#read 5, iclass 16, count 0 2006.286.02:41:09.38#ibcon#about to read 6, iclass 16, count 0 2006.286.02:41:09.38#ibcon#read 6, iclass 16, count 0 2006.286.02:41:09.38#ibcon#end of sib2, iclass 16, count 0 2006.286.02:41:09.38#ibcon#*after write, iclass 16, count 0 2006.286.02:41:09.38#ibcon#*before return 0, iclass 16, count 0 2006.286.02:41:09.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.02:41:09.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.02:41:09.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.02:41:09.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.02:41:09.38$vck44/va=1,7 2006.286.02:41:09.38#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.02:41:09.38#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.02:41:09.38#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:09.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.02:41:09.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.02:41:09.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.02:41:09.38#ibcon#enter wrdev, iclass 18, count 2 2006.286.02:41:09.38#ibcon#first serial, iclass 18, count 2 2006.286.02:41:09.38#ibcon#enter sib2, iclass 18, count 2 2006.286.02:41:09.38#ibcon#flushed, iclass 18, count 2 2006.286.02:41:09.38#ibcon#about to write, iclass 18, count 2 2006.286.02:41:09.39#ibcon#wrote, iclass 18, count 2 2006.286.02:41:09.39#ibcon#about to read 3, iclass 18, count 2 2006.286.02:41:09.40#ibcon#read 3, iclass 18, count 2 2006.286.02:41:09.40#ibcon#about to read 4, iclass 18, count 2 2006.286.02:41:09.40#ibcon#read 4, iclass 18, count 2 2006.286.02:41:09.40#ibcon#about to read 5, iclass 18, count 2 2006.286.02:41:09.40#ibcon#read 5, iclass 18, count 2 2006.286.02:41:09.40#ibcon#about to read 6, iclass 18, count 2 2006.286.02:41:09.40#ibcon#read 6, iclass 18, count 2 2006.286.02:41:09.40#ibcon#end of sib2, iclass 18, count 2 2006.286.02:41:09.40#ibcon#*mode == 0, iclass 18, count 2 2006.286.02:41:09.40#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.02:41:09.40#ibcon#[25=AT01-07\r\n] 2006.286.02:41:09.40#ibcon#*before write, iclass 18, count 2 2006.286.02:41:09.40#ibcon#enter sib2, iclass 18, count 2 2006.286.02:41:09.40#ibcon#flushed, iclass 18, count 2 2006.286.02:41:09.40#ibcon#about to write, iclass 18, count 2 2006.286.02:41:09.40#ibcon#wrote, iclass 18, count 2 2006.286.02:41:09.40#ibcon#about to read 3, iclass 18, count 2 2006.286.02:41:09.43#ibcon#read 3, iclass 18, count 2 2006.286.02:41:09.43#ibcon#about to read 4, iclass 18, count 2 2006.286.02:41:09.43#ibcon#read 4, iclass 18, count 2 2006.286.02:41:09.43#ibcon#about to read 5, iclass 18, count 2 2006.286.02:41:09.43#ibcon#read 5, iclass 18, count 2 2006.286.02:41:09.43#ibcon#about to read 6, iclass 18, count 2 2006.286.02:41:09.43#ibcon#read 6, iclass 18, count 2 2006.286.02:41:09.43#ibcon#end of sib2, iclass 18, count 2 2006.286.02:41:09.43#ibcon#*after write, iclass 18, count 2 2006.286.02:41:09.43#ibcon#*before return 0, iclass 18, count 2 2006.286.02:41:09.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.02:41:09.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.02:41:09.43#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.02:41:09.43#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:09.43#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.02:41:09.55#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.02:41:09.55#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.02:41:09.55#ibcon#enter wrdev, iclass 18, count 0 2006.286.02:41:09.55#ibcon#first serial, iclass 18, count 0 2006.286.02:41:09.55#ibcon#enter sib2, iclass 18, count 0 2006.286.02:41:09.55#ibcon#flushed, iclass 18, count 0 2006.286.02:41:09.55#ibcon#about to write, iclass 18, count 0 2006.286.02:41:09.55#ibcon#wrote, iclass 18, count 0 2006.286.02:41:09.55#ibcon#about to read 3, iclass 18, count 0 2006.286.02:41:09.57#ibcon#read 3, iclass 18, count 0 2006.286.02:41:09.57#ibcon#about to read 4, iclass 18, count 0 2006.286.02:41:09.57#ibcon#read 4, iclass 18, count 0 2006.286.02:41:09.57#ibcon#about to read 5, iclass 18, count 0 2006.286.02:41:09.57#ibcon#read 5, iclass 18, count 0 2006.286.02:41:09.57#ibcon#about to read 6, iclass 18, count 0 2006.286.02:41:09.57#ibcon#read 6, iclass 18, count 0 2006.286.02:41:09.57#ibcon#end of sib2, iclass 18, count 0 2006.286.02:41:09.57#ibcon#*mode == 0, iclass 18, count 0 2006.286.02:41:09.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.02:41:09.57#ibcon#[25=USB\r\n] 2006.286.02:41:09.57#ibcon#*before write, iclass 18, count 0 2006.286.02:41:09.57#ibcon#enter sib2, iclass 18, count 0 2006.286.02:41:09.57#ibcon#flushed, iclass 18, count 0 2006.286.02:41:09.57#ibcon#about to write, iclass 18, count 0 2006.286.02:41:09.57#ibcon#wrote, iclass 18, count 0 2006.286.02:41:09.57#ibcon#about to read 3, iclass 18, count 0 2006.286.02:41:09.60#ibcon#read 3, iclass 18, count 0 2006.286.02:41:09.60#ibcon#about to read 4, iclass 18, count 0 2006.286.02:41:09.60#ibcon#read 4, iclass 18, count 0 2006.286.02:41:09.60#ibcon#about to read 5, iclass 18, count 0 2006.286.02:41:09.60#ibcon#read 5, iclass 18, count 0 2006.286.02:41:09.60#ibcon#about to read 6, iclass 18, count 0 2006.286.02:41:09.60#ibcon#read 6, iclass 18, count 0 2006.286.02:41:09.60#ibcon#end of sib2, iclass 18, count 0 2006.286.02:41:09.60#ibcon#*after write, iclass 18, count 0 2006.286.02:41:09.60#ibcon#*before return 0, iclass 18, count 0 2006.286.02:41:09.60#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.02:41:09.60#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.02:41:09.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.02:41:09.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.02:41:09.60$vck44/valo=2,534.99 2006.286.02:41:09.60#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.02:41:09.60#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.02:41:09.60#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:09.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.02:41:09.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.02:41:09.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.02:41:09.60#ibcon#enter wrdev, iclass 20, count 0 2006.286.02:41:09.60#ibcon#first serial, iclass 20, count 0 2006.286.02:41:09.60#ibcon#enter sib2, iclass 20, count 0 2006.286.02:41:09.61#ibcon#flushed, iclass 20, count 0 2006.286.02:41:09.61#ibcon#about to write, iclass 20, count 0 2006.286.02:41:09.61#ibcon#wrote, iclass 20, count 0 2006.286.02:41:09.61#ibcon#about to read 3, iclass 20, count 0 2006.286.02:41:09.62#ibcon#read 3, iclass 20, count 0 2006.286.02:41:09.62#ibcon#about to read 4, iclass 20, count 0 2006.286.02:41:09.62#ibcon#read 4, iclass 20, count 0 2006.286.02:41:09.62#ibcon#about to read 5, iclass 20, count 0 2006.286.02:41:09.62#ibcon#read 5, iclass 20, count 0 2006.286.02:41:09.62#ibcon#about to read 6, iclass 20, count 0 2006.286.02:41:09.62#ibcon#read 6, iclass 20, count 0 2006.286.02:41:09.62#ibcon#end of sib2, iclass 20, count 0 2006.286.02:41:09.62#ibcon#*mode == 0, iclass 20, count 0 2006.286.02:41:09.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.02:41:09.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.02:41:09.62#ibcon#*before write, iclass 20, count 0 2006.286.02:41:09.62#ibcon#enter sib2, iclass 20, count 0 2006.286.02:41:09.62#ibcon#flushed, iclass 20, count 0 2006.286.02:41:09.62#ibcon#about to write, iclass 20, count 0 2006.286.02:41:09.62#ibcon#wrote, iclass 20, count 0 2006.286.02:41:09.62#ibcon#about to read 3, iclass 20, count 0 2006.286.02:41:09.66#ibcon#read 3, iclass 20, count 0 2006.286.02:41:09.66#ibcon#about to read 4, iclass 20, count 0 2006.286.02:41:09.66#ibcon#read 4, iclass 20, count 0 2006.286.02:41:09.66#ibcon#about to read 5, iclass 20, count 0 2006.286.02:41:09.66#ibcon#read 5, iclass 20, count 0 2006.286.02:41:09.66#ibcon#about to read 6, iclass 20, count 0 2006.286.02:41:09.66#ibcon#read 6, iclass 20, count 0 2006.286.02:41:09.66#ibcon#end of sib2, iclass 20, count 0 2006.286.02:41:09.66#ibcon#*after write, iclass 20, count 0 2006.286.02:41:09.66#ibcon#*before return 0, iclass 20, count 0 2006.286.02:41:09.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.02:41:09.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.02:41:09.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.02:41:09.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.02:41:09.66$vck44/va=2,6 2006.286.02:41:09.66#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.02:41:09.66#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.02:41:09.66#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:09.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.02:41:09.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.02:41:09.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.02:41:09.72#ibcon#enter wrdev, iclass 22, count 2 2006.286.02:41:09.72#ibcon#first serial, iclass 22, count 2 2006.286.02:41:09.72#ibcon#enter sib2, iclass 22, count 2 2006.286.02:41:09.72#ibcon#flushed, iclass 22, count 2 2006.286.02:41:09.72#ibcon#about to write, iclass 22, count 2 2006.286.02:41:09.72#ibcon#wrote, iclass 22, count 2 2006.286.02:41:09.72#ibcon#about to read 3, iclass 22, count 2 2006.286.02:41:09.74#ibcon#read 3, iclass 22, count 2 2006.286.02:41:09.74#ibcon#about to read 4, iclass 22, count 2 2006.286.02:41:09.74#ibcon#read 4, iclass 22, count 2 2006.286.02:41:09.74#ibcon#about to read 5, iclass 22, count 2 2006.286.02:41:09.74#ibcon#read 5, iclass 22, count 2 2006.286.02:41:09.74#ibcon#about to read 6, iclass 22, count 2 2006.286.02:41:09.74#ibcon#read 6, iclass 22, count 2 2006.286.02:41:09.74#ibcon#end of sib2, iclass 22, count 2 2006.286.02:41:09.74#ibcon#*mode == 0, iclass 22, count 2 2006.286.02:41:09.74#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.02:41:09.74#ibcon#[25=AT02-06\r\n] 2006.286.02:41:09.74#ibcon#*before write, iclass 22, count 2 2006.286.02:41:09.74#ibcon#enter sib2, iclass 22, count 2 2006.286.02:41:09.74#ibcon#flushed, iclass 22, count 2 2006.286.02:41:09.74#ibcon#about to write, iclass 22, count 2 2006.286.02:41:09.74#ibcon#wrote, iclass 22, count 2 2006.286.02:41:09.74#ibcon#about to read 3, iclass 22, count 2 2006.286.02:41:09.77#ibcon#read 3, iclass 22, count 2 2006.286.02:41:09.77#ibcon#about to read 4, iclass 22, count 2 2006.286.02:41:09.77#ibcon#read 4, iclass 22, count 2 2006.286.02:41:09.77#ibcon#about to read 5, iclass 22, count 2 2006.286.02:41:09.77#ibcon#read 5, iclass 22, count 2 2006.286.02:41:09.77#ibcon#about to read 6, iclass 22, count 2 2006.286.02:41:09.77#ibcon#read 6, iclass 22, count 2 2006.286.02:41:09.77#ibcon#end of sib2, iclass 22, count 2 2006.286.02:41:09.77#ibcon#*after write, iclass 22, count 2 2006.286.02:41:09.77#ibcon#*before return 0, iclass 22, count 2 2006.286.02:41:09.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.02:41:09.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.02:41:09.77#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.02:41:09.77#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:09.77#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.02:41:09.89#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.02:41:09.89#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.02:41:09.89#ibcon#enter wrdev, iclass 22, count 0 2006.286.02:41:09.89#ibcon#first serial, iclass 22, count 0 2006.286.02:41:09.89#ibcon#enter sib2, iclass 22, count 0 2006.286.02:41:09.89#ibcon#flushed, iclass 22, count 0 2006.286.02:41:09.89#ibcon#about to write, iclass 22, count 0 2006.286.02:41:09.89#ibcon#wrote, iclass 22, count 0 2006.286.02:41:09.89#ibcon#about to read 3, iclass 22, count 0 2006.286.02:41:09.91#ibcon#read 3, iclass 22, count 0 2006.286.02:41:09.91#ibcon#about to read 4, iclass 22, count 0 2006.286.02:41:09.91#ibcon#read 4, iclass 22, count 0 2006.286.02:41:09.91#ibcon#about to read 5, iclass 22, count 0 2006.286.02:41:09.91#ibcon#read 5, iclass 22, count 0 2006.286.02:41:09.91#ibcon#about to read 6, iclass 22, count 0 2006.286.02:41:09.91#ibcon#read 6, iclass 22, count 0 2006.286.02:41:09.91#ibcon#end of sib2, iclass 22, count 0 2006.286.02:41:09.91#ibcon#*mode == 0, iclass 22, count 0 2006.286.02:41:09.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.02:41:09.91#ibcon#[25=USB\r\n] 2006.286.02:41:09.91#ibcon#*before write, iclass 22, count 0 2006.286.02:41:09.91#ibcon#enter sib2, iclass 22, count 0 2006.286.02:41:09.91#ibcon#flushed, iclass 22, count 0 2006.286.02:41:09.91#ibcon#about to write, iclass 22, count 0 2006.286.02:41:09.91#ibcon#wrote, iclass 22, count 0 2006.286.02:41:09.91#ibcon#about to read 3, iclass 22, count 0 2006.286.02:41:09.94#ibcon#read 3, iclass 22, count 0 2006.286.02:41:09.94#ibcon#about to read 4, iclass 22, count 0 2006.286.02:41:09.94#ibcon#read 4, iclass 22, count 0 2006.286.02:41:09.94#ibcon#about to read 5, iclass 22, count 0 2006.286.02:41:09.94#ibcon#read 5, iclass 22, count 0 2006.286.02:41:09.94#ibcon#about to read 6, iclass 22, count 0 2006.286.02:41:09.94#ibcon#read 6, iclass 22, count 0 2006.286.02:41:09.94#ibcon#end of sib2, iclass 22, count 0 2006.286.02:41:09.94#ibcon#*after write, iclass 22, count 0 2006.286.02:41:09.94#ibcon#*before return 0, iclass 22, count 0 2006.286.02:41:09.94#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.02:41:09.94#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.02:41:09.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.02:41:09.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.02:41:09.94$vck44/valo=3,564.99 2006.286.02:41:09.94#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.02:41:09.94#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.02:41:09.94#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:09.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.02:41:09.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.02:41:09.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.02:41:09.94#ibcon#enter wrdev, iclass 24, count 0 2006.286.02:41:09.95#ibcon#first serial, iclass 24, count 0 2006.286.02:41:09.95#ibcon#enter sib2, iclass 24, count 0 2006.286.02:41:09.95#ibcon#flushed, iclass 24, count 0 2006.286.02:41:09.95#ibcon#about to write, iclass 24, count 0 2006.286.02:41:09.95#ibcon#wrote, iclass 24, count 0 2006.286.02:41:09.95#ibcon#about to read 3, iclass 24, count 0 2006.286.02:41:09.96#ibcon#read 3, iclass 24, count 0 2006.286.02:41:09.96#ibcon#about to read 4, iclass 24, count 0 2006.286.02:41:09.96#ibcon#read 4, iclass 24, count 0 2006.286.02:41:09.96#ibcon#about to read 5, iclass 24, count 0 2006.286.02:41:09.96#ibcon#read 5, iclass 24, count 0 2006.286.02:41:09.96#ibcon#about to read 6, iclass 24, count 0 2006.286.02:41:09.96#ibcon#read 6, iclass 24, count 0 2006.286.02:41:09.96#ibcon#end of sib2, iclass 24, count 0 2006.286.02:41:09.96#ibcon#*mode == 0, iclass 24, count 0 2006.286.02:41:09.96#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.02:41:09.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.02:41:09.96#ibcon#*before write, iclass 24, count 0 2006.286.02:41:09.96#ibcon#enter sib2, iclass 24, count 0 2006.286.02:41:09.96#ibcon#flushed, iclass 24, count 0 2006.286.02:41:09.96#ibcon#about to write, iclass 24, count 0 2006.286.02:41:09.96#ibcon#wrote, iclass 24, count 0 2006.286.02:41:09.96#ibcon#about to read 3, iclass 24, count 0 2006.286.02:41:10.00#ibcon#read 3, iclass 24, count 0 2006.286.02:41:10.00#ibcon#about to read 4, iclass 24, count 0 2006.286.02:41:10.00#ibcon#read 4, iclass 24, count 0 2006.286.02:41:10.00#ibcon#about to read 5, iclass 24, count 0 2006.286.02:41:10.00#ibcon#read 5, iclass 24, count 0 2006.286.02:41:10.00#ibcon#about to read 6, iclass 24, count 0 2006.286.02:41:10.00#ibcon#read 6, iclass 24, count 0 2006.286.02:41:10.00#ibcon#end of sib2, iclass 24, count 0 2006.286.02:41:10.00#ibcon#*after write, iclass 24, count 0 2006.286.02:41:10.00#ibcon#*before return 0, iclass 24, count 0 2006.286.02:41:10.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.02:41:10.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.02:41:10.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.02:41:10.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.02:41:10.00$vck44/va=3,7 2006.286.02:41:10.00#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.02:41:10.00#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.02:41:10.00#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:10.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.02:41:10.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.02:41:10.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.02:41:10.06#ibcon#enter wrdev, iclass 26, count 2 2006.286.02:41:10.06#ibcon#first serial, iclass 26, count 2 2006.286.02:41:10.06#ibcon#enter sib2, iclass 26, count 2 2006.286.02:41:10.06#ibcon#flushed, iclass 26, count 2 2006.286.02:41:10.06#ibcon#about to write, iclass 26, count 2 2006.286.02:41:10.06#ibcon#wrote, iclass 26, count 2 2006.286.02:41:10.06#ibcon#about to read 3, iclass 26, count 2 2006.286.02:41:10.08#ibcon#read 3, iclass 26, count 2 2006.286.02:41:10.08#ibcon#about to read 4, iclass 26, count 2 2006.286.02:41:10.08#ibcon#read 4, iclass 26, count 2 2006.286.02:41:10.08#ibcon#about to read 5, iclass 26, count 2 2006.286.02:41:10.08#ibcon#read 5, iclass 26, count 2 2006.286.02:41:10.08#ibcon#about to read 6, iclass 26, count 2 2006.286.02:41:10.08#ibcon#read 6, iclass 26, count 2 2006.286.02:41:10.08#ibcon#end of sib2, iclass 26, count 2 2006.286.02:41:10.08#ibcon#*mode == 0, iclass 26, count 2 2006.286.02:41:10.08#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.02:41:10.08#ibcon#[25=AT03-07\r\n] 2006.286.02:41:10.08#ibcon#*before write, iclass 26, count 2 2006.286.02:41:10.08#ibcon#enter sib2, iclass 26, count 2 2006.286.02:41:10.08#ibcon#flushed, iclass 26, count 2 2006.286.02:41:10.08#ibcon#about to write, iclass 26, count 2 2006.286.02:41:10.08#ibcon#wrote, iclass 26, count 2 2006.286.02:41:10.08#ibcon#about to read 3, iclass 26, count 2 2006.286.02:41:10.11#ibcon#read 3, iclass 26, count 2 2006.286.02:41:10.11#ibcon#about to read 4, iclass 26, count 2 2006.286.02:41:10.11#ibcon#read 4, iclass 26, count 2 2006.286.02:41:10.11#ibcon#about to read 5, iclass 26, count 2 2006.286.02:41:10.11#ibcon#read 5, iclass 26, count 2 2006.286.02:41:10.11#ibcon#about to read 6, iclass 26, count 2 2006.286.02:41:10.11#ibcon#read 6, iclass 26, count 2 2006.286.02:41:10.11#ibcon#end of sib2, iclass 26, count 2 2006.286.02:41:10.11#ibcon#*after write, iclass 26, count 2 2006.286.02:41:10.11#ibcon#*before return 0, iclass 26, count 2 2006.286.02:41:10.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.02:41:10.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.02:41:10.11#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.02:41:10.11#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:10.11#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.02:41:10.23#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.02:41:10.23#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.02:41:10.23#ibcon#enter wrdev, iclass 26, count 0 2006.286.02:41:10.23#ibcon#first serial, iclass 26, count 0 2006.286.02:41:10.23#ibcon#enter sib2, iclass 26, count 0 2006.286.02:41:10.23#ibcon#flushed, iclass 26, count 0 2006.286.02:41:10.23#ibcon#about to write, iclass 26, count 0 2006.286.02:41:10.23#ibcon#wrote, iclass 26, count 0 2006.286.02:41:10.23#ibcon#about to read 3, iclass 26, count 0 2006.286.02:41:10.25#ibcon#read 3, iclass 26, count 0 2006.286.02:41:10.25#ibcon#about to read 4, iclass 26, count 0 2006.286.02:41:10.25#ibcon#read 4, iclass 26, count 0 2006.286.02:41:10.25#ibcon#about to read 5, iclass 26, count 0 2006.286.02:41:10.25#ibcon#read 5, iclass 26, count 0 2006.286.02:41:10.25#ibcon#about to read 6, iclass 26, count 0 2006.286.02:41:10.25#ibcon#read 6, iclass 26, count 0 2006.286.02:41:10.25#ibcon#end of sib2, iclass 26, count 0 2006.286.02:41:10.25#ibcon#*mode == 0, iclass 26, count 0 2006.286.02:41:10.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.02:41:10.25#ibcon#[25=USB\r\n] 2006.286.02:41:10.25#ibcon#*before write, iclass 26, count 0 2006.286.02:41:10.25#ibcon#enter sib2, iclass 26, count 0 2006.286.02:41:10.25#ibcon#flushed, iclass 26, count 0 2006.286.02:41:10.25#ibcon#about to write, iclass 26, count 0 2006.286.02:41:10.25#ibcon#wrote, iclass 26, count 0 2006.286.02:41:10.25#ibcon#about to read 3, iclass 26, count 0 2006.286.02:41:10.28#ibcon#read 3, iclass 26, count 0 2006.286.02:41:10.28#ibcon#about to read 4, iclass 26, count 0 2006.286.02:41:10.28#ibcon#read 4, iclass 26, count 0 2006.286.02:41:10.28#ibcon#about to read 5, iclass 26, count 0 2006.286.02:41:10.28#ibcon#read 5, iclass 26, count 0 2006.286.02:41:10.28#ibcon#about to read 6, iclass 26, count 0 2006.286.02:41:10.28#ibcon#read 6, iclass 26, count 0 2006.286.02:41:10.28#ibcon#end of sib2, iclass 26, count 0 2006.286.02:41:10.28#ibcon#*after write, iclass 26, count 0 2006.286.02:41:10.28#ibcon#*before return 0, iclass 26, count 0 2006.286.02:41:10.28#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.02:41:10.28#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.02:41:10.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.02:41:10.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.02:41:10.28$vck44/valo=4,624.99 2006.286.02:41:10.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.02:41:10.28#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.02:41:10.28#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:10.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.02:41:10.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.02:41:10.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.02:41:10.28#ibcon#enter wrdev, iclass 28, count 0 2006.286.02:41:10.28#ibcon#first serial, iclass 28, count 0 2006.286.02:41:10.28#ibcon#enter sib2, iclass 28, count 0 2006.286.02:41:10.28#ibcon#flushed, iclass 28, count 0 2006.286.02:41:10.29#ibcon#about to write, iclass 28, count 0 2006.286.02:41:10.29#ibcon#wrote, iclass 28, count 0 2006.286.02:41:10.29#ibcon#about to read 3, iclass 28, count 0 2006.286.02:41:10.30#ibcon#read 3, iclass 28, count 0 2006.286.02:41:10.30#ibcon#about to read 4, iclass 28, count 0 2006.286.02:41:10.30#ibcon#read 4, iclass 28, count 0 2006.286.02:41:10.30#ibcon#about to read 5, iclass 28, count 0 2006.286.02:41:10.30#ibcon#read 5, iclass 28, count 0 2006.286.02:41:10.30#ibcon#about to read 6, iclass 28, count 0 2006.286.02:41:10.30#ibcon#read 6, iclass 28, count 0 2006.286.02:41:10.30#ibcon#end of sib2, iclass 28, count 0 2006.286.02:41:10.30#ibcon#*mode == 0, iclass 28, count 0 2006.286.02:41:10.30#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.02:41:10.30#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.02:41:10.30#ibcon#*before write, iclass 28, count 0 2006.286.02:41:10.30#ibcon#enter sib2, iclass 28, count 0 2006.286.02:41:10.30#ibcon#flushed, iclass 28, count 0 2006.286.02:41:10.30#ibcon#about to write, iclass 28, count 0 2006.286.02:41:10.30#ibcon#wrote, iclass 28, count 0 2006.286.02:41:10.30#ibcon#about to read 3, iclass 28, count 0 2006.286.02:41:10.34#ibcon#read 3, iclass 28, count 0 2006.286.02:41:10.34#ibcon#about to read 4, iclass 28, count 0 2006.286.02:41:10.34#ibcon#read 4, iclass 28, count 0 2006.286.02:41:10.34#ibcon#about to read 5, iclass 28, count 0 2006.286.02:41:10.34#ibcon#read 5, iclass 28, count 0 2006.286.02:41:10.34#ibcon#about to read 6, iclass 28, count 0 2006.286.02:41:10.34#ibcon#read 6, iclass 28, count 0 2006.286.02:41:10.34#ibcon#end of sib2, iclass 28, count 0 2006.286.02:41:10.34#ibcon#*after write, iclass 28, count 0 2006.286.02:41:10.34#ibcon#*before return 0, iclass 28, count 0 2006.286.02:41:10.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.02:41:10.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.02:41:10.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.02:41:10.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.02:41:10.34$vck44/va=4,6 2006.286.02:41:10.34#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.02:41:10.34#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.02:41:10.34#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:10.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.02:41:10.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.02:41:10.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.02:41:10.40#ibcon#enter wrdev, iclass 30, count 2 2006.286.02:41:10.40#ibcon#first serial, iclass 30, count 2 2006.286.02:41:10.40#ibcon#enter sib2, iclass 30, count 2 2006.286.02:41:10.40#ibcon#flushed, iclass 30, count 2 2006.286.02:41:10.40#ibcon#about to write, iclass 30, count 2 2006.286.02:41:10.40#ibcon#wrote, iclass 30, count 2 2006.286.02:41:10.40#ibcon#about to read 3, iclass 30, count 2 2006.286.02:41:10.42#ibcon#read 3, iclass 30, count 2 2006.286.02:41:10.42#ibcon#about to read 4, iclass 30, count 2 2006.286.02:41:10.42#ibcon#read 4, iclass 30, count 2 2006.286.02:41:10.42#ibcon#about to read 5, iclass 30, count 2 2006.286.02:41:10.42#ibcon#read 5, iclass 30, count 2 2006.286.02:41:10.42#ibcon#about to read 6, iclass 30, count 2 2006.286.02:41:10.42#ibcon#read 6, iclass 30, count 2 2006.286.02:41:10.42#ibcon#end of sib2, iclass 30, count 2 2006.286.02:41:10.42#ibcon#*mode == 0, iclass 30, count 2 2006.286.02:41:10.42#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.02:41:10.42#ibcon#[25=AT04-06\r\n] 2006.286.02:41:10.42#ibcon#*before write, iclass 30, count 2 2006.286.02:41:10.42#ibcon#enter sib2, iclass 30, count 2 2006.286.02:41:10.42#ibcon#flushed, iclass 30, count 2 2006.286.02:41:10.42#ibcon#about to write, iclass 30, count 2 2006.286.02:41:10.42#ibcon#wrote, iclass 30, count 2 2006.286.02:41:10.42#ibcon#about to read 3, iclass 30, count 2 2006.286.02:41:10.45#ibcon#read 3, iclass 30, count 2 2006.286.02:41:10.45#ibcon#about to read 4, iclass 30, count 2 2006.286.02:41:10.45#ibcon#read 4, iclass 30, count 2 2006.286.02:41:10.45#ibcon#about to read 5, iclass 30, count 2 2006.286.02:41:10.45#ibcon#read 5, iclass 30, count 2 2006.286.02:41:10.45#ibcon#about to read 6, iclass 30, count 2 2006.286.02:41:10.45#ibcon#read 6, iclass 30, count 2 2006.286.02:41:10.45#ibcon#end of sib2, iclass 30, count 2 2006.286.02:41:10.45#ibcon#*after write, iclass 30, count 2 2006.286.02:41:10.45#ibcon#*before return 0, iclass 30, count 2 2006.286.02:41:10.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.02:41:10.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.02:41:10.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.02:41:10.45#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:10.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.02:41:10.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.02:41:10.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.02:41:10.57#ibcon#enter wrdev, iclass 30, count 0 2006.286.02:41:10.57#ibcon#first serial, iclass 30, count 0 2006.286.02:41:10.57#ibcon#enter sib2, iclass 30, count 0 2006.286.02:41:10.57#ibcon#flushed, iclass 30, count 0 2006.286.02:41:10.57#ibcon#about to write, iclass 30, count 0 2006.286.02:41:10.57#ibcon#wrote, iclass 30, count 0 2006.286.02:41:10.57#ibcon#about to read 3, iclass 30, count 0 2006.286.02:41:10.59#ibcon#read 3, iclass 30, count 0 2006.286.02:41:10.59#ibcon#about to read 4, iclass 30, count 0 2006.286.02:41:10.59#ibcon#read 4, iclass 30, count 0 2006.286.02:41:10.59#ibcon#about to read 5, iclass 30, count 0 2006.286.02:41:10.59#ibcon#read 5, iclass 30, count 0 2006.286.02:41:10.59#ibcon#about to read 6, iclass 30, count 0 2006.286.02:41:10.59#ibcon#read 6, iclass 30, count 0 2006.286.02:41:10.59#ibcon#end of sib2, iclass 30, count 0 2006.286.02:41:10.59#ibcon#*mode == 0, iclass 30, count 0 2006.286.02:41:10.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.02:41:10.59#ibcon#[25=USB\r\n] 2006.286.02:41:10.59#ibcon#*before write, iclass 30, count 0 2006.286.02:41:10.59#ibcon#enter sib2, iclass 30, count 0 2006.286.02:41:10.59#ibcon#flushed, iclass 30, count 0 2006.286.02:41:10.59#ibcon#about to write, iclass 30, count 0 2006.286.02:41:10.59#ibcon#wrote, iclass 30, count 0 2006.286.02:41:10.59#ibcon#about to read 3, iclass 30, count 0 2006.286.02:41:10.62#ibcon#read 3, iclass 30, count 0 2006.286.02:41:10.62#ibcon#about to read 4, iclass 30, count 0 2006.286.02:41:10.62#ibcon#read 4, iclass 30, count 0 2006.286.02:41:10.62#ibcon#about to read 5, iclass 30, count 0 2006.286.02:41:10.62#ibcon#read 5, iclass 30, count 0 2006.286.02:41:10.62#ibcon#about to read 6, iclass 30, count 0 2006.286.02:41:10.62#ibcon#read 6, iclass 30, count 0 2006.286.02:41:10.62#ibcon#end of sib2, iclass 30, count 0 2006.286.02:41:10.62#ibcon#*after write, iclass 30, count 0 2006.286.02:41:10.62#ibcon#*before return 0, iclass 30, count 0 2006.286.02:41:10.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.02:41:10.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.02:41:10.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.02:41:10.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.02:41:10.62$vck44/valo=5,734.99 2006.286.02:41:10.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.02:41:10.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.02:41:10.62#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:10.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.02:41:10.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.02:41:10.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.02:41:10.62#ibcon#enter wrdev, iclass 32, count 0 2006.286.02:41:10.62#ibcon#first serial, iclass 32, count 0 2006.286.02:41:10.62#ibcon#enter sib2, iclass 32, count 0 2006.286.02:41:10.62#ibcon#flushed, iclass 32, count 0 2006.286.02:41:10.63#ibcon#about to write, iclass 32, count 0 2006.286.02:41:10.63#ibcon#wrote, iclass 32, count 0 2006.286.02:41:10.63#ibcon#about to read 3, iclass 32, count 0 2006.286.02:41:10.64#ibcon#read 3, iclass 32, count 0 2006.286.02:41:10.64#ibcon#about to read 4, iclass 32, count 0 2006.286.02:41:10.64#ibcon#read 4, iclass 32, count 0 2006.286.02:41:10.64#ibcon#about to read 5, iclass 32, count 0 2006.286.02:41:10.64#ibcon#read 5, iclass 32, count 0 2006.286.02:41:10.64#ibcon#about to read 6, iclass 32, count 0 2006.286.02:41:10.64#ibcon#read 6, iclass 32, count 0 2006.286.02:41:10.64#ibcon#end of sib2, iclass 32, count 0 2006.286.02:41:10.64#ibcon#*mode == 0, iclass 32, count 0 2006.286.02:41:10.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.02:41:10.64#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.02:41:10.64#ibcon#*before write, iclass 32, count 0 2006.286.02:41:10.64#ibcon#enter sib2, iclass 32, count 0 2006.286.02:41:10.64#ibcon#flushed, iclass 32, count 0 2006.286.02:41:10.64#ibcon#about to write, iclass 32, count 0 2006.286.02:41:10.64#ibcon#wrote, iclass 32, count 0 2006.286.02:41:10.64#ibcon#about to read 3, iclass 32, count 0 2006.286.02:41:10.68#ibcon#read 3, iclass 32, count 0 2006.286.02:41:10.68#ibcon#about to read 4, iclass 32, count 0 2006.286.02:41:10.68#ibcon#read 4, iclass 32, count 0 2006.286.02:41:10.68#ibcon#about to read 5, iclass 32, count 0 2006.286.02:41:10.68#ibcon#read 5, iclass 32, count 0 2006.286.02:41:10.68#ibcon#about to read 6, iclass 32, count 0 2006.286.02:41:10.68#ibcon#read 6, iclass 32, count 0 2006.286.02:41:10.68#ibcon#end of sib2, iclass 32, count 0 2006.286.02:41:10.68#ibcon#*after write, iclass 32, count 0 2006.286.02:41:10.68#ibcon#*before return 0, iclass 32, count 0 2006.286.02:41:10.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.02:41:10.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.02:41:10.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.02:41:10.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.02:41:10.68$vck44/va=5,3 2006.286.02:41:10.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.02:41:10.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.02:41:10.68#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:10.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.02:41:10.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.02:41:10.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.02:41:10.74#ibcon#enter wrdev, iclass 34, count 2 2006.286.02:41:10.74#ibcon#first serial, iclass 34, count 2 2006.286.02:41:10.74#ibcon#enter sib2, iclass 34, count 2 2006.286.02:41:10.74#ibcon#flushed, iclass 34, count 2 2006.286.02:41:10.74#ibcon#about to write, iclass 34, count 2 2006.286.02:41:10.74#ibcon#wrote, iclass 34, count 2 2006.286.02:41:10.74#ibcon#about to read 3, iclass 34, count 2 2006.286.02:41:10.76#ibcon#read 3, iclass 34, count 2 2006.286.02:41:10.76#ibcon#about to read 4, iclass 34, count 2 2006.286.02:41:10.76#ibcon#read 4, iclass 34, count 2 2006.286.02:41:10.76#ibcon#about to read 5, iclass 34, count 2 2006.286.02:41:10.76#ibcon#read 5, iclass 34, count 2 2006.286.02:41:10.76#ibcon#about to read 6, iclass 34, count 2 2006.286.02:41:10.76#ibcon#read 6, iclass 34, count 2 2006.286.02:41:10.76#ibcon#end of sib2, iclass 34, count 2 2006.286.02:41:10.76#ibcon#*mode == 0, iclass 34, count 2 2006.286.02:41:10.76#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.02:41:10.76#ibcon#[25=AT05-03\r\n] 2006.286.02:41:10.76#ibcon#*before write, iclass 34, count 2 2006.286.02:41:10.76#ibcon#enter sib2, iclass 34, count 2 2006.286.02:41:10.76#ibcon#flushed, iclass 34, count 2 2006.286.02:41:10.76#ibcon#about to write, iclass 34, count 2 2006.286.02:41:10.76#ibcon#wrote, iclass 34, count 2 2006.286.02:41:10.76#ibcon#about to read 3, iclass 34, count 2 2006.286.02:41:10.79#ibcon#read 3, iclass 34, count 2 2006.286.02:41:10.79#ibcon#about to read 4, iclass 34, count 2 2006.286.02:41:10.79#ibcon#read 4, iclass 34, count 2 2006.286.02:41:10.79#ibcon#about to read 5, iclass 34, count 2 2006.286.02:41:10.79#ibcon#read 5, iclass 34, count 2 2006.286.02:41:10.79#ibcon#about to read 6, iclass 34, count 2 2006.286.02:41:10.79#ibcon#read 6, iclass 34, count 2 2006.286.02:41:10.79#ibcon#end of sib2, iclass 34, count 2 2006.286.02:41:10.79#ibcon#*after write, iclass 34, count 2 2006.286.02:41:10.79#ibcon#*before return 0, iclass 34, count 2 2006.286.02:41:10.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.02:41:10.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.02:41:10.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.02:41:10.79#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:10.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.02:41:10.91#abcon#<5=/03 3.2 6.4 21.27 811015.8\r\n> 2006.286.02:41:10.91#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.02:41:10.91#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.02:41:10.91#ibcon#enter wrdev, iclass 34, count 0 2006.286.02:41:10.91#ibcon#first serial, iclass 34, count 0 2006.286.02:41:10.91#ibcon#enter sib2, iclass 34, count 0 2006.286.02:41:10.91#ibcon#flushed, iclass 34, count 0 2006.286.02:41:10.91#ibcon#about to write, iclass 34, count 0 2006.286.02:41:10.91#ibcon#wrote, iclass 34, count 0 2006.286.02:41:10.91#ibcon#about to read 3, iclass 34, count 0 2006.286.02:41:10.93#ibcon#read 3, iclass 34, count 0 2006.286.02:41:10.93#ibcon#about to read 4, iclass 34, count 0 2006.286.02:41:10.93#ibcon#read 4, iclass 34, count 0 2006.286.02:41:10.93#ibcon#about to read 5, iclass 34, count 0 2006.286.02:41:10.93#ibcon#read 5, iclass 34, count 0 2006.286.02:41:10.93#ibcon#about to read 6, iclass 34, count 0 2006.286.02:41:10.93#ibcon#read 6, iclass 34, count 0 2006.286.02:41:10.93#ibcon#end of sib2, iclass 34, count 0 2006.286.02:41:10.93#ibcon#*mode == 0, iclass 34, count 0 2006.286.02:41:10.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.02:41:10.93#ibcon#[25=USB\r\n] 2006.286.02:41:10.93#ibcon#*before write, iclass 34, count 0 2006.286.02:41:10.93#ibcon#enter sib2, iclass 34, count 0 2006.286.02:41:10.93#ibcon#flushed, iclass 34, count 0 2006.286.02:41:10.93#ibcon#about to write, iclass 34, count 0 2006.286.02:41:10.93#ibcon#wrote, iclass 34, count 0 2006.286.02:41:10.93#ibcon#about to read 3, iclass 34, count 0 2006.286.02:41:10.93#abcon#{5=INTERFACE CLEAR} 2006.286.02:41:10.96#ibcon#read 3, iclass 34, count 0 2006.286.02:41:10.96#ibcon#about to read 4, iclass 34, count 0 2006.286.02:41:10.96#ibcon#read 4, iclass 34, count 0 2006.286.02:41:10.96#ibcon#about to read 5, iclass 34, count 0 2006.286.02:41:10.96#ibcon#read 5, iclass 34, count 0 2006.286.02:41:10.96#ibcon#about to read 6, iclass 34, count 0 2006.286.02:41:10.96#ibcon#read 6, iclass 34, count 0 2006.286.02:41:10.96#ibcon#end of sib2, iclass 34, count 0 2006.286.02:41:10.96#ibcon#*after write, iclass 34, count 0 2006.286.02:41:10.96#ibcon#*before return 0, iclass 34, count 0 2006.286.02:41:10.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.02:41:10.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.02:41:10.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.02:41:10.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.02:41:10.96$vck44/valo=6,814.99 2006.286.02:41:10.96#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.02:41:10.96#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.02:41:10.96#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:10.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:41:10.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:41:10.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:41:10.96#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:41:10.96#ibcon#first serial, iclass 39, count 0 2006.286.02:41:10.96#ibcon#enter sib2, iclass 39, count 0 2006.286.02:41:10.97#ibcon#flushed, iclass 39, count 0 2006.286.02:41:10.97#ibcon#about to write, iclass 39, count 0 2006.286.02:41:10.97#ibcon#wrote, iclass 39, count 0 2006.286.02:41:10.97#ibcon#about to read 3, iclass 39, count 0 2006.286.02:41:10.98#ibcon#read 3, iclass 39, count 0 2006.286.02:41:10.98#ibcon#about to read 4, iclass 39, count 0 2006.286.02:41:10.98#ibcon#read 4, iclass 39, count 0 2006.286.02:41:10.98#ibcon#about to read 5, iclass 39, count 0 2006.286.02:41:10.98#ibcon#read 5, iclass 39, count 0 2006.286.02:41:10.98#ibcon#about to read 6, iclass 39, count 0 2006.286.02:41:10.98#ibcon#read 6, iclass 39, count 0 2006.286.02:41:10.98#ibcon#end of sib2, iclass 39, count 0 2006.286.02:41:10.98#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:41:10.98#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:41:10.98#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.02:41:10.98#ibcon#*before write, iclass 39, count 0 2006.286.02:41:10.98#ibcon#enter sib2, iclass 39, count 0 2006.286.02:41:10.98#ibcon#flushed, iclass 39, count 0 2006.286.02:41:10.98#ibcon#about to write, iclass 39, count 0 2006.286.02:41:10.98#ibcon#wrote, iclass 39, count 0 2006.286.02:41:10.98#ibcon#about to read 3, iclass 39, count 0 2006.286.02:41:10.99#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:41:11.02#ibcon#read 3, iclass 39, count 0 2006.286.02:41:11.02#ibcon#about to read 4, iclass 39, count 0 2006.286.02:41:11.02#ibcon#read 4, iclass 39, count 0 2006.286.02:41:11.02#ibcon#about to read 5, iclass 39, count 0 2006.286.02:41:11.02#ibcon#read 5, iclass 39, count 0 2006.286.02:41:11.02#ibcon#about to read 6, iclass 39, count 0 2006.286.02:41:11.02#ibcon#read 6, iclass 39, count 0 2006.286.02:41:11.02#ibcon#end of sib2, iclass 39, count 0 2006.286.02:41:11.02#ibcon#*after write, iclass 39, count 0 2006.286.02:41:11.02#ibcon#*before return 0, iclass 39, count 0 2006.286.02:41:11.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:41:11.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:41:11.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:41:11.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:41:11.02$vck44/va=6,4 2006.286.02:41:11.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.02:41:11.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.02:41:11.02#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:11.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.02:41:11.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.02:41:11.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.02:41:11.08#ibcon#enter wrdev, iclass 4, count 2 2006.286.02:41:11.08#ibcon#first serial, iclass 4, count 2 2006.286.02:41:11.08#ibcon#enter sib2, iclass 4, count 2 2006.286.02:41:11.08#ibcon#flushed, iclass 4, count 2 2006.286.02:41:11.08#ibcon#about to write, iclass 4, count 2 2006.286.02:41:11.08#ibcon#wrote, iclass 4, count 2 2006.286.02:41:11.08#ibcon#about to read 3, iclass 4, count 2 2006.286.02:41:11.10#ibcon#read 3, iclass 4, count 2 2006.286.02:41:11.10#ibcon#about to read 4, iclass 4, count 2 2006.286.02:41:11.10#ibcon#read 4, iclass 4, count 2 2006.286.02:41:11.10#ibcon#about to read 5, iclass 4, count 2 2006.286.02:41:11.10#ibcon#read 5, iclass 4, count 2 2006.286.02:41:11.10#ibcon#about to read 6, iclass 4, count 2 2006.286.02:41:11.10#ibcon#read 6, iclass 4, count 2 2006.286.02:41:11.10#ibcon#end of sib2, iclass 4, count 2 2006.286.02:41:11.10#ibcon#*mode == 0, iclass 4, count 2 2006.286.02:41:11.10#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.02:41:11.10#ibcon#[25=AT06-04\r\n] 2006.286.02:41:11.10#ibcon#*before write, iclass 4, count 2 2006.286.02:41:11.10#ibcon#enter sib2, iclass 4, count 2 2006.286.02:41:11.10#ibcon#flushed, iclass 4, count 2 2006.286.02:41:11.10#ibcon#about to write, iclass 4, count 2 2006.286.02:41:11.10#ibcon#wrote, iclass 4, count 2 2006.286.02:41:11.10#ibcon#about to read 3, iclass 4, count 2 2006.286.02:41:11.13#ibcon#read 3, iclass 4, count 2 2006.286.02:41:11.13#ibcon#about to read 4, iclass 4, count 2 2006.286.02:41:11.13#ibcon#read 4, iclass 4, count 2 2006.286.02:41:11.13#ibcon#about to read 5, iclass 4, count 2 2006.286.02:41:11.13#ibcon#read 5, iclass 4, count 2 2006.286.02:41:11.13#ibcon#about to read 6, iclass 4, count 2 2006.286.02:41:11.13#ibcon#read 6, iclass 4, count 2 2006.286.02:41:11.13#ibcon#end of sib2, iclass 4, count 2 2006.286.02:41:11.13#ibcon#*after write, iclass 4, count 2 2006.286.02:41:11.13#ibcon#*before return 0, iclass 4, count 2 2006.286.02:41:11.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.02:41:11.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.02:41:11.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.02:41:11.13#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:11.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.02:41:11.25#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.02:41:11.25#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.02:41:11.25#ibcon#enter wrdev, iclass 4, count 0 2006.286.02:41:11.25#ibcon#first serial, iclass 4, count 0 2006.286.02:41:11.25#ibcon#enter sib2, iclass 4, count 0 2006.286.02:41:11.25#ibcon#flushed, iclass 4, count 0 2006.286.02:41:11.25#ibcon#about to write, iclass 4, count 0 2006.286.02:41:11.25#ibcon#wrote, iclass 4, count 0 2006.286.02:41:11.25#ibcon#about to read 3, iclass 4, count 0 2006.286.02:41:11.27#ibcon#read 3, iclass 4, count 0 2006.286.02:41:11.27#ibcon#about to read 4, iclass 4, count 0 2006.286.02:41:11.27#ibcon#read 4, iclass 4, count 0 2006.286.02:41:11.27#ibcon#about to read 5, iclass 4, count 0 2006.286.02:41:11.27#ibcon#read 5, iclass 4, count 0 2006.286.02:41:11.27#ibcon#about to read 6, iclass 4, count 0 2006.286.02:41:11.27#ibcon#read 6, iclass 4, count 0 2006.286.02:41:11.27#ibcon#end of sib2, iclass 4, count 0 2006.286.02:41:11.27#ibcon#*mode == 0, iclass 4, count 0 2006.286.02:41:11.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.02:41:11.27#ibcon#[25=USB\r\n] 2006.286.02:41:11.27#ibcon#*before write, iclass 4, count 0 2006.286.02:41:11.27#ibcon#enter sib2, iclass 4, count 0 2006.286.02:41:11.27#ibcon#flushed, iclass 4, count 0 2006.286.02:41:11.27#ibcon#about to write, iclass 4, count 0 2006.286.02:41:11.27#ibcon#wrote, iclass 4, count 0 2006.286.02:41:11.27#ibcon#about to read 3, iclass 4, count 0 2006.286.02:41:11.30#ibcon#read 3, iclass 4, count 0 2006.286.02:41:11.30#ibcon#about to read 4, iclass 4, count 0 2006.286.02:41:11.30#ibcon#read 4, iclass 4, count 0 2006.286.02:41:11.30#ibcon#about to read 5, iclass 4, count 0 2006.286.02:41:11.30#ibcon#read 5, iclass 4, count 0 2006.286.02:41:11.30#ibcon#about to read 6, iclass 4, count 0 2006.286.02:41:11.30#ibcon#read 6, iclass 4, count 0 2006.286.02:41:11.30#ibcon#end of sib2, iclass 4, count 0 2006.286.02:41:11.30#ibcon#*after write, iclass 4, count 0 2006.286.02:41:11.30#ibcon#*before return 0, iclass 4, count 0 2006.286.02:41:11.30#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.02:41:11.30#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.02:41:11.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.02:41:11.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.02:41:11.30$vck44/valo=7,864.99 2006.286.02:41:11.30#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.02:41:11.30#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.02:41:11.30#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:11.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.02:41:11.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.02:41:11.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.02:41:11.30#ibcon#enter wrdev, iclass 6, count 0 2006.286.02:41:11.30#ibcon#first serial, iclass 6, count 0 2006.286.02:41:11.30#ibcon#enter sib2, iclass 6, count 0 2006.286.02:41:11.30#ibcon#flushed, iclass 6, count 0 2006.286.02:41:11.31#ibcon#about to write, iclass 6, count 0 2006.286.02:41:11.31#ibcon#wrote, iclass 6, count 0 2006.286.02:41:11.31#ibcon#about to read 3, iclass 6, count 0 2006.286.02:41:11.32#ibcon#read 3, iclass 6, count 0 2006.286.02:41:11.32#ibcon#about to read 4, iclass 6, count 0 2006.286.02:41:11.32#ibcon#read 4, iclass 6, count 0 2006.286.02:41:11.32#ibcon#about to read 5, iclass 6, count 0 2006.286.02:41:11.32#ibcon#read 5, iclass 6, count 0 2006.286.02:41:11.32#ibcon#about to read 6, iclass 6, count 0 2006.286.02:41:11.32#ibcon#read 6, iclass 6, count 0 2006.286.02:41:11.32#ibcon#end of sib2, iclass 6, count 0 2006.286.02:41:11.32#ibcon#*mode == 0, iclass 6, count 0 2006.286.02:41:11.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.02:41:11.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.02:41:11.32#ibcon#*before write, iclass 6, count 0 2006.286.02:41:11.32#ibcon#enter sib2, iclass 6, count 0 2006.286.02:41:11.32#ibcon#flushed, iclass 6, count 0 2006.286.02:41:11.32#ibcon#about to write, iclass 6, count 0 2006.286.02:41:11.32#ibcon#wrote, iclass 6, count 0 2006.286.02:41:11.32#ibcon#about to read 3, iclass 6, count 0 2006.286.02:41:11.36#ibcon#read 3, iclass 6, count 0 2006.286.02:41:11.36#ibcon#about to read 4, iclass 6, count 0 2006.286.02:41:11.36#ibcon#read 4, iclass 6, count 0 2006.286.02:41:11.36#ibcon#about to read 5, iclass 6, count 0 2006.286.02:41:11.36#ibcon#read 5, iclass 6, count 0 2006.286.02:41:11.36#ibcon#about to read 6, iclass 6, count 0 2006.286.02:41:11.36#ibcon#read 6, iclass 6, count 0 2006.286.02:41:11.36#ibcon#end of sib2, iclass 6, count 0 2006.286.02:41:11.36#ibcon#*after write, iclass 6, count 0 2006.286.02:41:11.36#ibcon#*before return 0, iclass 6, count 0 2006.286.02:41:11.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.02:41:11.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.02:41:11.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.02:41:11.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.02:41:11.36$vck44/va=7,4 2006.286.02:41:11.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.02:41:11.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.02:41:11.36#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:11.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.02:41:11.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.02:41:11.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.02:41:11.42#ibcon#enter wrdev, iclass 10, count 2 2006.286.02:41:11.42#ibcon#first serial, iclass 10, count 2 2006.286.02:41:11.42#ibcon#enter sib2, iclass 10, count 2 2006.286.02:41:11.42#ibcon#flushed, iclass 10, count 2 2006.286.02:41:11.42#ibcon#about to write, iclass 10, count 2 2006.286.02:41:11.42#ibcon#wrote, iclass 10, count 2 2006.286.02:41:11.42#ibcon#about to read 3, iclass 10, count 2 2006.286.02:41:11.44#ibcon#read 3, iclass 10, count 2 2006.286.02:41:11.44#ibcon#about to read 4, iclass 10, count 2 2006.286.02:41:11.44#ibcon#read 4, iclass 10, count 2 2006.286.02:41:11.44#ibcon#about to read 5, iclass 10, count 2 2006.286.02:41:11.44#ibcon#read 5, iclass 10, count 2 2006.286.02:41:11.44#ibcon#about to read 6, iclass 10, count 2 2006.286.02:41:11.44#ibcon#read 6, iclass 10, count 2 2006.286.02:41:11.44#ibcon#end of sib2, iclass 10, count 2 2006.286.02:41:11.44#ibcon#*mode == 0, iclass 10, count 2 2006.286.02:41:11.44#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.02:41:11.44#ibcon#[25=AT07-04\r\n] 2006.286.02:41:11.44#ibcon#*before write, iclass 10, count 2 2006.286.02:41:11.44#ibcon#enter sib2, iclass 10, count 2 2006.286.02:41:11.44#ibcon#flushed, iclass 10, count 2 2006.286.02:41:11.44#ibcon#about to write, iclass 10, count 2 2006.286.02:41:11.44#ibcon#wrote, iclass 10, count 2 2006.286.02:41:11.44#ibcon#about to read 3, iclass 10, count 2 2006.286.02:41:11.47#ibcon#read 3, iclass 10, count 2 2006.286.02:41:11.47#ibcon#about to read 4, iclass 10, count 2 2006.286.02:41:11.47#ibcon#read 4, iclass 10, count 2 2006.286.02:41:11.47#ibcon#about to read 5, iclass 10, count 2 2006.286.02:41:11.47#ibcon#read 5, iclass 10, count 2 2006.286.02:41:11.47#ibcon#about to read 6, iclass 10, count 2 2006.286.02:41:11.47#ibcon#read 6, iclass 10, count 2 2006.286.02:41:11.47#ibcon#end of sib2, iclass 10, count 2 2006.286.02:41:11.47#ibcon#*after write, iclass 10, count 2 2006.286.02:41:11.47#ibcon#*before return 0, iclass 10, count 2 2006.286.02:41:11.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.02:41:11.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.02:41:11.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.02:41:11.47#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:11.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.02:41:11.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.02:41:11.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.02:41:11.59#ibcon#enter wrdev, iclass 10, count 0 2006.286.02:41:11.59#ibcon#first serial, iclass 10, count 0 2006.286.02:41:11.59#ibcon#enter sib2, iclass 10, count 0 2006.286.02:41:11.59#ibcon#flushed, iclass 10, count 0 2006.286.02:41:11.59#ibcon#about to write, iclass 10, count 0 2006.286.02:41:11.59#ibcon#wrote, iclass 10, count 0 2006.286.02:41:11.59#ibcon#about to read 3, iclass 10, count 0 2006.286.02:41:11.61#ibcon#read 3, iclass 10, count 0 2006.286.02:41:11.61#ibcon#about to read 4, iclass 10, count 0 2006.286.02:41:11.61#ibcon#read 4, iclass 10, count 0 2006.286.02:41:11.61#ibcon#about to read 5, iclass 10, count 0 2006.286.02:41:11.61#ibcon#read 5, iclass 10, count 0 2006.286.02:41:11.61#ibcon#about to read 6, iclass 10, count 0 2006.286.02:41:11.61#ibcon#read 6, iclass 10, count 0 2006.286.02:41:11.61#ibcon#end of sib2, iclass 10, count 0 2006.286.02:41:11.61#ibcon#*mode == 0, iclass 10, count 0 2006.286.02:41:11.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.02:41:11.61#ibcon#[25=USB\r\n] 2006.286.02:41:11.61#ibcon#*before write, iclass 10, count 0 2006.286.02:41:11.61#ibcon#enter sib2, iclass 10, count 0 2006.286.02:41:11.61#ibcon#flushed, iclass 10, count 0 2006.286.02:41:11.61#ibcon#about to write, iclass 10, count 0 2006.286.02:41:11.61#ibcon#wrote, iclass 10, count 0 2006.286.02:41:11.61#ibcon#about to read 3, iclass 10, count 0 2006.286.02:41:11.64#ibcon#read 3, iclass 10, count 0 2006.286.02:41:11.64#ibcon#about to read 4, iclass 10, count 0 2006.286.02:41:11.64#ibcon#read 4, iclass 10, count 0 2006.286.02:41:11.64#ibcon#about to read 5, iclass 10, count 0 2006.286.02:41:11.64#ibcon#read 5, iclass 10, count 0 2006.286.02:41:11.64#ibcon#about to read 6, iclass 10, count 0 2006.286.02:41:11.64#ibcon#read 6, iclass 10, count 0 2006.286.02:41:11.64#ibcon#end of sib2, iclass 10, count 0 2006.286.02:41:11.64#ibcon#*after write, iclass 10, count 0 2006.286.02:41:11.64#ibcon#*before return 0, iclass 10, count 0 2006.286.02:41:11.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.02:41:11.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.02:41:11.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.02:41:11.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.02:41:11.64$vck44/valo=8,884.99 2006.286.02:41:11.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.02:41:11.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.02:41:11.64#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:11.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.02:41:11.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.02:41:11.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.02:41:11.64#ibcon#enter wrdev, iclass 12, count 0 2006.286.02:41:11.64#ibcon#first serial, iclass 12, count 0 2006.286.02:41:11.64#ibcon#enter sib2, iclass 12, count 0 2006.286.02:41:11.64#ibcon#flushed, iclass 12, count 0 2006.286.02:41:11.64#ibcon#about to write, iclass 12, count 0 2006.286.02:41:11.65#ibcon#wrote, iclass 12, count 0 2006.286.02:41:11.65#ibcon#about to read 3, iclass 12, count 0 2006.286.02:41:11.66#ibcon#read 3, iclass 12, count 0 2006.286.02:41:11.66#ibcon#about to read 4, iclass 12, count 0 2006.286.02:41:11.66#ibcon#read 4, iclass 12, count 0 2006.286.02:41:11.66#ibcon#about to read 5, iclass 12, count 0 2006.286.02:41:11.66#ibcon#read 5, iclass 12, count 0 2006.286.02:41:11.66#ibcon#about to read 6, iclass 12, count 0 2006.286.02:41:11.66#ibcon#read 6, iclass 12, count 0 2006.286.02:41:11.66#ibcon#end of sib2, iclass 12, count 0 2006.286.02:41:11.66#ibcon#*mode == 0, iclass 12, count 0 2006.286.02:41:11.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.02:41:11.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.02:41:11.66#ibcon#*before write, iclass 12, count 0 2006.286.02:41:11.66#ibcon#enter sib2, iclass 12, count 0 2006.286.02:41:11.66#ibcon#flushed, iclass 12, count 0 2006.286.02:41:11.66#ibcon#about to write, iclass 12, count 0 2006.286.02:41:11.66#ibcon#wrote, iclass 12, count 0 2006.286.02:41:11.66#ibcon#about to read 3, iclass 12, count 0 2006.286.02:41:11.70#ibcon#read 3, iclass 12, count 0 2006.286.02:41:11.70#ibcon#about to read 4, iclass 12, count 0 2006.286.02:41:11.70#ibcon#read 4, iclass 12, count 0 2006.286.02:41:11.70#ibcon#about to read 5, iclass 12, count 0 2006.286.02:41:11.70#ibcon#read 5, iclass 12, count 0 2006.286.02:41:11.70#ibcon#about to read 6, iclass 12, count 0 2006.286.02:41:11.70#ibcon#read 6, iclass 12, count 0 2006.286.02:41:11.70#ibcon#end of sib2, iclass 12, count 0 2006.286.02:41:11.70#ibcon#*after write, iclass 12, count 0 2006.286.02:41:11.70#ibcon#*before return 0, iclass 12, count 0 2006.286.02:41:11.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.02:41:11.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.02:41:11.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.02:41:11.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.02:41:11.70$vck44/va=8,3 2006.286.02:41:11.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.02:41:11.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.02:41:11.71#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:11.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.02:41:11.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.02:41:11.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.02:41:11.75#ibcon#enter wrdev, iclass 14, count 2 2006.286.02:41:11.75#ibcon#first serial, iclass 14, count 2 2006.286.02:41:11.75#ibcon#enter sib2, iclass 14, count 2 2006.286.02:41:11.75#ibcon#flushed, iclass 14, count 2 2006.286.02:41:11.75#ibcon#about to write, iclass 14, count 2 2006.286.02:41:11.75#ibcon#wrote, iclass 14, count 2 2006.286.02:41:11.75#ibcon#about to read 3, iclass 14, count 2 2006.286.02:41:11.77#ibcon#read 3, iclass 14, count 2 2006.286.02:41:11.77#ibcon#about to read 4, iclass 14, count 2 2006.286.02:41:11.77#ibcon#read 4, iclass 14, count 2 2006.286.02:41:11.77#ibcon#about to read 5, iclass 14, count 2 2006.286.02:41:11.77#ibcon#read 5, iclass 14, count 2 2006.286.02:41:11.77#ibcon#about to read 6, iclass 14, count 2 2006.286.02:41:11.77#ibcon#read 6, iclass 14, count 2 2006.286.02:41:11.77#ibcon#end of sib2, iclass 14, count 2 2006.286.02:41:11.77#ibcon#*mode == 0, iclass 14, count 2 2006.286.02:41:11.77#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.02:41:11.77#ibcon#[25=AT08-03\r\n] 2006.286.02:41:11.77#ibcon#*before write, iclass 14, count 2 2006.286.02:41:11.77#ibcon#enter sib2, iclass 14, count 2 2006.286.02:41:11.77#ibcon#flushed, iclass 14, count 2 2006.286.02:41:11.77#ibcon#about to write, iclass 14, count 2 2006.286.02:41:11.77#ibcon#wrote, iclass 14, count 2 2006.286.02:41:11.77#ibcon#about to read 3, iclass 14, count 2 2006.286.02:41:11.80#ibcon#read 3, iclass 14, count 2 2006.286.02:41:11.80#ibcon#about to read 4, iclass 14, count 2 2006.286.02:41:11.80#ibcon#read 4, iclass 14, count 2 2006.286.02:41:11.80#ibcon#about to read 5, iclass 14, count 2 2006.286.02:41:11.80#ibcon#read 5, iclass 14, count 2 2006.286.02:41:11.80#ibcon#about to read 6, iclass 14, count 2 2006.286.02:41:11.80#ibcon#read 6, iclass 14, count 2 2006.286.02:41:11.80#ibcon#end of sib2, iclass 14, count 2 2006.286.02:41:11.80#ibcon#*after write, iclass 14, count 2 2006.286.02:41:11.80#ibcon#*before return 0, iclass 14, count 2 2006.286.02:41:11.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.02:41:11.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.02:41:11.80#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.02:41:11.80#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:11.80#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.02:41:11.92#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.02:41:11.92#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.02:41:11.92#ibcon#enter wrdev, iclass 14, count 0 2006.286.02:41:11.92#ibcon#first serial, iclass 14, count 0 2006.286.02:41:11.92#ibcon#enter sib2, iclass 14, count 0 2006.286.02:41:11.92#ibcon#flushed, iclass 14, count 0 2006.286.02:41:11.92#ibcon#about to write, iclass 14, count 0 2006.286.02:41:11.92#ibcon#wrote, iclass 14, count 0 2006.286.02:41:11.92#ibcon#about to read 3, iclass 14, count 0 2006.286.02:41:11.94#ibcon#read 3, iclass 14, count 0 2006.286.02:41:11.94#ibcon#about to read 4, iclass 14, count 0 2006.286.02:41:11.94#ibcon#read 4, iclass 14, count 0 2006.286.02:41:11.94#ibcon#about to read 5, iclass 14, count 0 2006.286.02:41:11.94#ibcon#read 5, iclass 14, count 0 2006.286.02:41:11.94#ibcon#about to read 6, iclass 14, count 0 2006.286.02:41:11.94#ibcon#read 6, iclass 14, count 0 2006.286.02:41:11.94#ibcon#end of sib2, iclass 14, count 0 2006.286.02:41:11.94#ibcon#*mode == 0, iclass 14, count 0 2006.286.02:41:11.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.02:41:11.94#ibcon#[25=USB\r\n] 2006.286.02:41:11.94#ibcon#*before write, iclass 14, count 0 2006.286.02:41:11.94#ibcon#enter sib2, iclass 14, count 0 2006.286.02:41:11.94#ibcon#flushed, iclass 14, count 0 2006.286.02:41:11.94#ibcon#about to write, iclass 14, count 0 2006.286.02:41:11.94#ibcon#wrote, iclass 14, count 0 2006.286.02:41:11.94#ibcon#about to read 3, iclass 14, count 0 2006.286.02:41:11.97#ibcon#read 3, iclass 14, count 0 2006.286.02:41:11.97#ibcon#about to read 4, iclass 14, count 0 2006.286.02:41:11.97#ibcon#read 4, iclass 14, count 0 2006.286.02:41:11.97#ibcon#about to read 5, iclass 14, count 0 2006.286.02:41:11.97#ibcon#read 5, iclass 14, count 0 2006.286.02:41:11.97#ibcon#about to read 6, iclass 14, count 0 2006.286.02:41:11.97#ibcon#read 6, iclass 14, count 0 2006.286.02:41:11.97#ibcon#end of sib2, iclass 14, count 0 2006.286.02:41:11.97#ibcon#*after write, iclass 14, count 0 2006.286.02:41:11.97#ibcon#*before return 0, iclass 14, count 0 2006.286.02:41:11.97#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.02:41:11.97#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.02:41:11.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.02:41:11.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.02:41:11.97$vck44/vblo=1,629.99 2006.286.02:41:11.97#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.02:41:11.97#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.02:41:11.97#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:11.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.02:41:11.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.02:41:11.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.02:41:11.97#ibcon#enter wrdev, iclass 16, count 0 2006.286.02:41:11.97#ibcon#first serial, iclass 16, count 0 2006.286.02:41:11.97#ibcon#enter sib2, iclass 16, count 0 2006.286.02:41:11.97#ibcon#flushed, iclass 16, count 0 2006.286.02:41:11.97#ibcon#about to write, iclass 16, count 0 2006.286.02:41:11.98#ibcon#wrote, iclass 16, count 0 2006.286.02:41:11.98#ibcon#about to read 3, iclass 16, count 0 2006.286.02:41:11.99#ibcon#read 3, iclass 16, count 0 2006.286.02:41:11.99#ibcon#about to read 4, iclass 16, count 0 2006.286.02:41:11.99#ibcon#read 4, iclass 16, count 0 2006.286.02:41:11.99#ibcon#about to read 5, iclass 16, count 0 2006.286.02:41:11.99#ibcon#read 5, iclass 16, count 0 2006.286.02:41:11.99#ibcon#about to read 6, iclass 16, count 0 2006.286.02:41:11.99#ibcon#read 6, iclass 16, count 0 2006.286.02:41:11.99#ibcon#end of sib2, iclass 16, count 0 2006.286.02:41:11.99#ibcon#*mode == 0, iclass 16, count 0 2006.286.02:41:11.99#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.02:41:11.99#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.02:41:11.99#ibcon#*before write, iclass 16, count 0 2006.286.02:41:11.99#ibcon#enter sib2, iclass 16, count 0 2006.286.02:41:11.99#ibcon#flushed, iclass 16, count 0 2006.286.02:41:11.99#ibcon#about to write, iclass 16, count 0 2006.286.02:41:11.99#ibcon#wrote, iclass 16, count 0 2006.286.02:41:11.99#ibcon#about to read 3, iclass 16, count 0 2006.286.02:41:12.03#ibcon#read 3, iclass 16, count 0 2006.286.02:41:12.03#ibcon#about to read 4, iclass 16, count 0 2006.286.02:41:12.03#ibcon#read 4, iclass 16, count 0 2006.286.02:41:12.03#ibcon#about to read 5, iclass 16, count 0 2006.286.02:41:12.03#ibcon#read 5, iclass 16, count 0 2006.286.02:41:12.03#ibcon#about to read 6, iclass 16, count 0 2006.286.02:41:12.03#ibcon#read 6, iclass 16, count 0 2006.286.02:41:12.03#ibcon#end of sib2, iclass 16, count 0 2006.286.02:41:12.03#ibcon#*after write, iclass 16, count 0 2006.286.02:41:12.03#ibcon#*before return 0, iclass 16, count 0 2006.286.02:41:12.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.02:41:12.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.02:41:12.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.02:41:12.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.02:41:12.03$vck44/vb=1,4 2006.286.02:41:12.03#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.02:41:12.03#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.02:41:12.03#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:12.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.02:41:12.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.02:41:12.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.02:41:12.03#ibcon#enter wrdev, iclass 18, count 2 2006.286.02:41:12.03#ibcon#first serial, iclass 18, count 2 2006.286.02:41:12.03#ibcon#enter sib2, iclass 18, count 2 2006.286.02:41:12.03#ibcon#flushed, iclass 18, count 2 2006.286.02:41:12.03#ibcon#about to write, iclass 18, count 2 2006.286.02:41:12.04#ibcon#wrote, iclass 18, count 2 2006.286.02:41:12.04#ibcon#about to read 3, iclass 18, count 2 2006.286.02:41:12.05#ibcon#read 3, iclass 18, count 2 2006.286.02:41:12.05#ibcon#about to read 4, iclass 18, count 2 2006.286.02:41:12.05#ibcon#read 4, iclass 18, count 2 2006.286.02:41:12.05#ibcon#about to read 5, iclass 18, count 2 2006.286.02:41:12.05#ibcon#read 5, iclass 18, count 2 2006.286.02:41:12.05#ibcon#about to read 6, iclass 18, count 2 2006.286.02:41:12.05#ibcon#read 6, iclass 18, count 2 2006.286.02:41:12.05#ibcon#end of sib2, iclass 18, count 2 2006.286.02:41:12.05#ibcon#*mode == 0, iclass 18, count 2 2006.286.02:41:12.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.02:41:12.05#ibcon#[27=AT01-04\r\n] 2006.286.02:41:12.05#ibcon#*before write, iclass 18, count 2 2006.286.02:41:12.05#ibcon#enter sib2, iclass 18, count 2 2006.286.02:41:12.05#ibcon#flushed, iclass 18, count 2 2006.286.02:41:12.05#ibcon#about to write, iclass 18, count 2 2006.286.02:41:12.05#ibcon#wrote, iclass 18, count 2 2006.286.02:41:12.05#ibcon#about to read 3, iclass 18, count 2 2006.286.02:41:12.08#ibcon#read 3, iclass 18, count 2 2006.286.02:41:12.08#ibcon#about to read 4, iclass 18, count 2 2006.286.02:41:12.08#ibcon#read 4, iclass 18, count 2 2006.286.02:41:12.08#ibcon#about to read 5, iclass 18, count 2 2006.286.02:41:12.08#ibcon#read 5, iclass 18, count 2 2006.286.02:41:12.08#ibcon#about to read 6, iclass 18, count 2 2006.286.02:41:12.08#ibcon#read 6, iclass 18, count 2 2006.286.02:41:12.08#ibcon#end of sib2, iclass 18, count 2 2006.286.02:41:12.08#ibcon#*after write, iclass 18, count 2 2006.286.02:41:12.08#ibcon#*before return 0, iclass 18, count 2 2006.286.02:41:12.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.02:41:12.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.02:41:12.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.02:41:12.08#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:12.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.02:41:12.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.02:41:12.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.02:41:12.20#ibcon#enter wrdev, iclass 18, count 0 2006.286.02:41:12.20#ibcon#first serial, iclass 18, count 0 2006.286.02:41:12.20#ibcon#enter sib2, iclass 18, count 0 2006.286.02:41:12.20#ibcon#flushed, iclass 18, count 0 2006.286.02:41:12.20#ibcon#about to write, iclass 18, count 0 2006.286.02:41:12.20#ibcon#wrote, iclass 18, count 0 2006.286.02:41:12.20#ibcon#about to read 3, iclass 18, count 0 2006.286.02:41:12.22#ibcon#read 3, iclass 18, count 0 2006.286.02:41:12.22#ibcon#about to read 4, iclass 18, count 0 2006.286.02:41:12.22#ibcon#read 4, iclass 18, count 0 2006.286.02:41:12.22#ibcon#about to read 5, iclass 18, count 0 2006.286.02:41:12.22#ibcon#read 5, iclass 18, count 0 2006.286.02:41:12.22#ibcon#about to read 6, iclass 18, count 0 2006.286.02:41:12.22#ibcon#read 6, iclass 18, count 0 2006.286.02:41:12.22#ibcon#end of sib2, iclass 18, count 0 2006.286.02:41:12.22#ibcon#*mode == 0, iclass 18, count 0 2006.286.02:41:12.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.02:41:12.22#ibcon#[27=USB\r\n] 2006.286.02:41:12.22#ibcon#*before write, iclass 18, count 0 2006.286.02:41:12.22#ibcon#enter sib2, iclass 18, count 0 2006.286.02:41:12.22#ibcon#flushed, iclass 18, count 0 2006.286.02:41:12.22#ibcon#about to write, iclass 18, count 0 2006.286.02:41:12.22#ibcon#wrote, iclass 18, count 0 2006.286.02:41:12.22#ibcon#about to read 3, iclass 18, count 0 2006.286.02:41:12.25#ibcon#read 3, iclass 18, count 0 2006.286.02:41:12.25#ibcon#about to read 4, iclass 18, count 0 2006.286.02:41:12.25#ibcon#read 4, iclass 18, count 0 2006.286.02:41:12.25#ibcon#about to read 5, iclass 18, count 0 2006.286.02:41:12.25#ibcon#read 5, iclass 18, count 0 2006.286.02:41:12.25#ibcon#about to read 6, iclass 18, count 0 2006.286.02:41:12.25#ibcon#read 6, iclass 18, count 0 2006.286.02:41:12.25#ibcon#end of sib2, iclass 18, count 0 2006.286.02:41:12.25#ibcon#*after write, iclass 18, count 0 2006.286.02:41:12.25#ibcon#*before return 0, iclass 18, count 0 2006.286.02:41:12.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.02:41:12.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.02:41:12.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.02:41:12.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.02:41:12.25$vck44/vblo=2,634.99 2006.286.02:41:12.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.02:41:12.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.02:41:12.25#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:12.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.02:41:12.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.02:41:12.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.02:41:12.25#ibcon#enter wrdev, iclass 20, count 0 2006.286.02:41:12.25#ibcon#first serial, iclass 20, count 0 2006.286.02:41:12.25#ibcon#enter sib2, iclass 20, count 0 2006.286.02:41:12.25#ibcon#flushed, iclass 20, count 0 2006.286.02:41:12.26#ibcon#about to write, iclass 20, count 0 2006.286.02:41:12.26#ibcon#wrote, iclass 20, count 0 2006.286.02:41:12.26#ibcon#about to read 3, iclass 20, count 0 2006.286.02:41:12.27#ibcon#read 3, iclass 20, count 0 2006.286.02:41:12.27#ibcon#about to read 4, iclass 20, count 0 2006.286.02:41:12.27#ibcon#read 4, iclass 20, count 0 2006.286.02:41:12.27#ibcon#about to read 5, iclass 20, count 0 2006.286.02:41:12.27#ibcon#read 5, iclass 20, count 0 2006.286.02:41:12.27#ibcon#about to read 6, iclass 20, count 0 2006.286.02:41:12.27#ibcon#read 6, iclass 20, count 0 2006.286.02:41:12.27#ibcon#end of sib2, iclass 20, count 0 2006.286.02:41:12.27#ibcon#*mode == 0, iclass 20, count 0 2006.286.02:41:12.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.02:41:12.27#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.02:41:12.27#ibcon#*before write, iclass 20, count 0 2006.286.02:41:12.27#ibcon#enter sib2, iclass 20, count 0 2006.286.02:41:12.27#ibcon#flushed, iclass 20, count 0 2006.286.02:41:12.27#ibcon#about to write, iclass 20, count 0 2006.286.02:41:12.27#ibcon#wrote, iclass 20, count 0 2006.286.02:41:12.27#ibcon#about to read 3, iclass 20, count 0 2006.286.02:41:12.31#ibcon#read 3, iclass 20, count 0 2006.286.02:41:12.31#ibcon#about to read 4, iclass 20, count 0 2006.286.02:41:12.31#ibcon#read 4, iclass 20, count 0 2006.286.02:41:12.31#ibcon#about to read 5, iclass 20, count 0 2006.286.02:41:12.31#ibcon#read 5, iclass 20, count 0 2006.286.02:41:12.31#ibcon#about to read 6, iclass 20, count 0 2006.286.02:41:12.31#ibcon#read 6, iclass 20, count 0 2006.286.02:41:12.31#ibcon#end of sib2, iclass 20, count 0 2006.286.02:41:12.31#ibcon#*after write, iclass 20, count 0 2006.286.02:41:12.31#ibcon#*before return 0, iclass 20, count 0 2006.286.02:41:12.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.02:41:12.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.02:41:12.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.02:41:12.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.02:41:12.31$vck44/vb=2,5 2006.286.02:41:12.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.02:41:12.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.02:41:12.31#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:12.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.02:41:12.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.02:41:12.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.02:41:12.37#ibcon#enter wrdev, iclass 22, count 2 2006.286.02:41:12.37#ibcon#first serial, iclass 22, count 2 2006.286.02:41:12.37#ibcon#enter sib2, iclass 22, count 2 2006.286.02:41:12.37#ibcon#flushed, iclass 22, count 2 2006.286.02:41:12.37#ibcon#about to write, iclass 22, count 2 2006.286.02:41:12.37#ibcon#wrote, iclass 22, count 2 2006.286.02:41:12.37#ibcon#about to read 3, iclass 22, count 2 2006.286.02:41:12.39#ibcon#read 3, iclass 22, count 2 2006.286.02:41:12.39#ibcon#about to read 4, iclass 22, count 2 2006.286.02:41:12.39#ibcon#read 4, iclass 22, count 2 2006.286.02:41:12.39#ibcon#about to read 5, iclass 22, count 2 2006.286.02:41:12.39#ibcon#read 5, iclass 22, count 2 2006.286.02:41:12.39#ibcon#about to read 6, iclass 22, count 2 2006.286.02:41:12.39#ibcon#read 6, iclass 22, count 2 2006.286.02:41:12.39#ibcon#end of sib2, iclass 22, count 2 2006.286.02:41:12.39#ibcon#*mode == 0, iclass 22, count 2 2006.286.02:41:12.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.02:41:12.39#ibcon#[27=AT02-05\r\n] 2006.286.02:41:12.39#ibcon#*before write, iclass 22, count 2 2006.286.02:41:12.39#ibcon#enter sib2, iclass 22, count 2 2006.286.02:41:12.39#ibcon#flushed, iclass 22, count 2 2006.286.02:41:12.39#ibcon#about to write, iclass 22, count 2 2006.286.02:41:12.39#ibcon#wrote, iclass 22, count 2 2006.286.02:41:12.39#ibcon#about to read 3, iclass 22, count 2 2006.286.02:41:12.42#ibcon#read 3, iclass 22, count 2 2006.286.02:41:12.42#ibcon#about to read 4, iclass 22, count 2 2006.286.02:41:12.42#ibcon#read 4, iclass 22, count 2 2006.286.02:41:12.42#ibcon#about to read 5, iclass 22, count 2 2006.286.02:41:12.42#ibcon#read 5, iclass 22, count 2 2006.286.02:41:12.42#ibcon#about to read 6, iclass 22, count 2 2006.286.02:41:12.42#ibcon#read 6, iclass 22, count 2 2006.286.02:41:12.42#ibcon#end of sib2, iclass 22, count 2 2006.286.02:41:12.42#ibcon#*after write, iclass 22, count 2 2006.286.02:41:12.42#ibcon#*before return 0, iclass 22, count 2 2006.286.02:41:12.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.02:41:12.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.02:41:12.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.02:41:12.42#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:12.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.02:41:12.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.02:41:12.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.02:41:12.54#ibcon#enter wrdev, iclass 22, count 0 2006.286.02:41:12.54#ibcon#first serial, iclass 22, count 0 2006.286.02:41:12.54#ibcon#enter sib2, iclass 22, count 0 2006.286.02:41:12.54#ibcon#flushed, iclass 22, count 0 2006.286.02:41:12.54#ibcon#about to write, iclass 22, count 0 2006.286.02:41:12.54#ibcon#wrote, iclass 22, count 0 2006.286.02:41:12.54#ibcon#about to read 3, iclass 22, count 0 2006.286.02:41:12.56#ibcon#read 3, iclass 22, count 0 2006.286.02:41:12.56#ibcon#about to read 4, iclass 22, count 0 2006.286.02:41:12.56#ibcon#read 4, iclass 22, count 0 2006.286.02:41:12.56#ibcon#about to read 5, iclass 22, count 0 2006.286.02:41:12.56#ibcon#read 5, iclass 22, count 0 2006.286.02:41:12.56#ibcon#about to read 6, iclass 22, count 0 2006.286.02:41:12.56#ibcon#read 6, iclass 22, count 0 2006.286.02:41:12.56#ibcon#end of sib2, iclass 22, count 0 2006.286.02:41:12.56#ibcon#*mode == 0, iclass 22, count 0 2006.286.02:41:12.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.02:41:12.56#ibcon#[27=USB\r\n] 2006.286.02:41:12.56#ibcon#*before write, iclass 22, count 0 2006.286.02:41:12.56#ibcon#enter sib2, iclass 22, count 0 2006.286.02:41:12.56#ibcon#flushed, iclass 22, count 0 2006.286.02:41:12.56#ibcon#about to write, iclass 22, count 0 2006.286.02:41:12.56#ibcon#wrote, iclass 22, count 0 2006.286.02:41:12.56#ibcon#about to read 3, iclass 22, count 0 2006.286.02:41:12.59#ibcon#read 3, iclass 22, count 0 2006.286.02:41:12.59#ibcon#about to read 4, iclass 22, count 0 2006.286.02:41:12.59#ibcon#read 4, iclass 22, count 0 2006.286.02:41:12.59#ibcon#about to read 5, iclass 22, count 0 2006.286.02:41:12.59#ibcon#read 5, iclass 22, count 0 2006.286.02:41:12.59#ibcon#about to read 6, iclass 22, count 0 2006.286.02:41:12.59#ibcon#read 6, iclass 22, count 0 2006.286.02:41:12.59#ibcon#end of sib2, iclass 22, count 0 2006.286.02:41:12.59#ibcon#*after write, iclass 22, count 0 2006.286.02:41:12.59#ibcon#*before return 0, iclass 22, count 0 2006.286.02:41:12.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.02:41:12.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.02:41:12.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.02:41:12.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.02:41:12.59$vck44/vblo=3,649.99 2006.286.02:41:12.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.02:41:12.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.02:41:12.59#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:12.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.02:41:12.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.02:41:12.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.02:41:12.59#ibcon#enter wrdev, iclass 24, count 0 2006.286.02:41:12.59#ibcon#first serial, iclass 24, count 0 2006.286.02:41:12.59#ibcon#enter sib2, iclass 24, count 0 2006.286.02:41:12.59#ibcon#flushed, iclass 24, count 0 2006.286.02:41:12.59#ibcon#about to write, iclass 24, count 0 2006.286.02:41:12.60#ibcon#wrote, iclass 24, count 0 2006.286.02:41:12.60#ibcon#about to read 3, iclass 24, count 0 2006.286.02:41:12.61#ibcon#read 3, iclass 24, count 0 2006.286.02:41:12.61#ibcon#about to read 4, iclass 24, count 0 2006.286.02:41:12.61#ibcon#read 4, iclass 24, count 0 2006.286.02:41:12.61#ibcon#about to read 5, iclass 24, count 0 2006.286.02:41:12.61#ibcon#read 5, iclass 24, count 0 2006.286.02:41:12.61#ibcon#about to read 6, iclass 24, count 0 2006.286.02:41:12.61#ibcon#read 6, iclass 24, count 0 2006.286.02:41:12.61#ibcon#end of sib2, iclass 24, count 0 2006.286.02:41:12.61#ibcon#*mode == 0, iclass 24, count 0 2006.286.02:41:12.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.02:41:12.61#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.02:41:12.61#ibcon#*before write, iclass 24, count 0 2006.286.02:41:12.61#ibcon#enter sib2, iclass 24, count 0 2006.286.02:41:12.61#ibcon#flushed, iclass 24, count 0 2006.286.02:41:12.61#ibcon#about to write, iclass 24, count 0 2006.286.02:41:12.61#ibcon#wrote, iclass 24, count 0 2006.286.02:41:12.61#ibcon#about to read 3, iclass 24, count 0 2006.286.02:41:12.65#ibcon#read 3, iclass 24, count 0 2006.286.02:41:12.65#ibcon#about to read 4, iclass 24, count 0 2006.286.02:41:12.65#ibcon#read 4, iclass 24, count 0 2006.286.02:41:12.65#ibcon#about to read 5, iclass 24, count 0 2006.286.02:41:12.65#ibcon#read 5, iclass 24, count 0 2006.286.02:41:12.65#ibcon#about to read 6, iclass 24, count 0 2006.286.02:41:12.65#ibcon#read 6, iclass 24, count 0 2006.286.02:41:12.65#ibcon#end of sib2, iclass 24, count 0 2006.286.02:41:12.65#ibcon#*after write, iclass 24, count 0 2006.286.02:41:12.65#ibcon#*before return 0, iclass 24, count 0 2006.286.02:41:12.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.02:41:12.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.02:41:12.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.02:41:12.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.02:41:12.65$vck44/vb=3,4 2006.286.02:41:12.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.02:41:12.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.02:41:12.65#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:12.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.02:41:12.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.02:41:12.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.02:41:12.71#ibcon#enter wrdev, iclass 26, count 2 2006.286.02:41:12.71#ibcon#first serial, iclass 26, count 2 2006.286.02:41:12.71#ibcon#enter sib2, iclass 26, count 2 2006.286.02:41:12.71#ibcon#flushed, iclass 26, count 2 2006.286.02:41:12.71#ibcon#about to write, iclass 26, count 2 2006.286.02:41:12.71#ibcon#wrote, iclass 26, count 2 2006.286.02:41:12.71#ibcon#about to read 3, iclass 26, count 2 2006.286.02:41:12.73#ibcon#read 3, iclass 26, count 2 2006.286.02:41:12.73#ibcon#about to read 4, iclass 26, count 2 2006.286.02:41:12.73#ibcon#read 4, iclass 26, count 2 2006.286.02:41:12.73#ibcon#about to read 5, iclass 26, count 2 2006.286.02:41:12.73#ibcon#read 5, iclass 26, count 2 2006.286.02:41:12.73#ibcon#about to read 6, iclass 26, count 2 2006.286.02:41:12.73#ibcon#read 6, iclass 26, count 2 2006.286.02:41:12.73#ibcon#end of sib2, iclass 26, count 2 2006.286.02:41:12.73#ibcon#*mode == 0, iclass 26, count 2 2006.286.02:41:12.73#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.02:41:12.73#ibcon#[27=AT03-04\r\n] 2006.286.02:41:12.73#ibcon#*before write, iclass 26, count 2 2006.286.02:41:12.73#ibcon#enter sib2, iclass 26, count 2 2006.286.02:41:12.73#ibcon#flushed, iclass 26, count 2 2006.286.02:41:12.73#ibcon#about to write, iclass 26, count 2 2006.286.02:41:12.73#ibcon#wrote, iclass 26, count 2 2006.286.02:41:12.73#ibcon#about to read 3, iclass 26, count 2 2006.286.02:41:12.76#ibcon#read 3, iclass 26, count 2 2006.286.02:41:12.76#ibcon#about to read 4, iclass 26, count 2 2006.286.02:41:12.76#ibcon#read 4, iclass 26, count 2 2006.286.02:41:12.76#ibcon#about to read 5, iclass 26, count 2 2006.286.02:41:12.76#ibcon#read 5, iclass 26, count 2 2006.286.02:41:12.76#ibcon#about to read 6, iclass 26, count 2 2006.286.02:41:12.76#ibcon#read 6, iclass 26, count 2 2006.286.02:41:12.76#ibcon#end of sib2, iclass 26, count 2 2006.286.02:41:12.76#ibcon#*after write, iclass 26, count 2 2006.286.02:41:12.76#ibcon#*before return 0, iclass 26, count 2 2006.286.02:41:12.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.02:41:12.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.02:41:12.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.02:41:12.76#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:12.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.02:41:12.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.02:41:12.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.02:41:12.88#ibcon#enter wrdev, iclass 26, count 0 2006.286.02:41:12.88#ibcon#first serial, iclass 26, count 0 2006.286.02:41:12.88#ibcon#enter sib2, iclass 26, count 0 2006.286.02:41:12.88#ibcon#flushed, iclass 26, count 0 2006.286.02:41:12.88#ibcon#about to write, iclass 26, count 0 2006.286.02:41:12.88#ibcon#wrote, iclass 26, count 0 2006.286.02:41:12.88#ibcon#about to read 3, iclass 26, count 0 2006.286.02:41:12.90#ibcon#read 3, iclass 26, count 0 2006.286.02:41:12.90#ibcon#about to read 4, iclass 26, count 0 2006.286.02:41:12.90#ibcon#read 4, iclass 26, count 0 2006.286.02:41:12.90#ibcon#about to read 5, iclass 26, count 0 2006.286.02:41:12.90#ibcon#read 5, iclass 26, count 0 2006.286.02:41:12.90#ibcon#about to read 6, iclass 26, count 0 2006.286.02:41:12.90#ibcon#read 6, iclass 26, count 0 2006.286.02:41:12.90#ibcon#end of sib2, iclass 26, count 0 2006.286.02:41:12.90#ibcon#*mode == 0, iclass 26, count 0 2006.286.02:41:12.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.02:41:12.90#ibcon#[27=USB\r\n] 2006.286.02:41:12.90#ibcon#*before write, iclass 26, count 0 2006.286.02:41:12.90#ibcon#enter sib2, iclass 26, count 0 2006.286.02:41:12.90#ibcon#flushed, iclass 26, count 0 2006.286.02:41:12.90#ibcon#about to write, iclass 26, count 0 2006.286.02:41:12.90#ibcon#wrote, iclass 26, count 0 2006.286.02:41:12.90#ibcon#about to read 3, iclass 26, count 0 2006.286.02:41:12.93#ibcon#read 3, iclass 26, count 0 2006.286.02:41:12.93#ibcon#about to read 4, iclass 26, count 0 2006.286.02:41:12.93#ibcon#read 4, iclass 26, count 0 2006.286.02:41:12.93#ibcon#about to read 5, iclass 26, count 0 2006.286.02:41:12.93#ibcon#read 5, iclass 26, count 0 2006.286.02:41:12.93#ibcon#about to read 6, iclass 26, count 0 2006.286.02:41:12.93#ibcon#read 6, iclass 26, count 0 2006.286.02:41:12.93#ibcon#end of sib2, iclass 26, count 0 2006.286.02:41:12.93#ibcon#*after write, iclass 26, count 0 2006.286.02:41:12.93#ibcon#*before return 0, iclass 26, count 0 2006.286.02:41:12.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.02:41:12.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.02:41:12.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.02:41:12.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.02:41:12.93$vck44/vblo=4,679.99 2006.286.02:41:12.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.02:41:12.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.02:41:12.93#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:12.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.02:41:12.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.02:41:12.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.02:41:12.93#ibcon#enter wrdev, iclass 28, count 0 2006.286.02:41:12.93#ibcon#first serial, iclass 28, count 0 2006.286.02:41:12.93#ibcon#enter sib2, iclass 28, count 0 2006.286.02:41:12.93#ibcon#flushed, iclass 28, count 0 2006.286.02:41:12.94#ibcon#about to write, iclass 28, count 0 2006.286.02:41:12.94#ibcon#wrote, iclass 28, count 0 2006.286.02:41:12.94#ibcon#about to read 3, iclass 28, count 0 2006.286.02:41:12.95#ibcon#read 3, iclass 28, count 0 2006.286.02:41:12.95#ibcon#about to read 4, iclass 28, count 0 2006.286.02:41:12.95#ibcon#read 4, iclass 28, count 0 2006.286.02:41:12.95#ibcon#about to read 5, iclass 28, count 0 2006.286.02:41:12.95#ibcon#read 5, iclass 28, count 0 2006.286.02:41:12.95#ibcon#about to read 6, iclass 28, count 0 2006.286.02:41:12.95#ibcon#read 6, iclass 28, count 0 2006.286.02:41:12.95#ibcon#end of sib2, iclass 28, count 0 2006.286.02:41:12.95#ibcon#*mode == 0, iclass 28, count 0 2006.286.02:41:12.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.02:41:12.95#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.02:41:12.95#ibcon#*before write, iclass 28, count 0 2006.286.02:41:12.95#ibcon#enter sib2, iclass 28, count 0 2006.286.02:41:12.95#ibcon#flushed, iclass 28, count 0 2006.286.02:41:12.95#ibcon#about to write, iclass 28, count 0 2006.286.02:41:12.95#ibcon#wrote, iclass 28, count 0 2006.286.02:41:12.95#ibcon#about to read 3, iclass 28, count 0 2006.286.02:41:12.99#ibcon#read 3, iclass 28, count 0 2006.286.02:41:12.99#ibcon#about to read 4, iclass 28, count 0 2006.286.02:41:12.99#ibcon#read 4, iclass 28, count 0 2006.286.02:41:12.99#ibcon#about to read 5, iclass 28, count 0 2006.286.02:41:12.99#ibcon#read 5, iclass 28, count 0 2006.286.02:41:12.99#ibcon#about to read 6, iclass 28, count 0 2006.286.02:41:12.99#ibcon#read 6, iclass 28, count 0 2006.286.02:41:12.99#ibcon#end of sib2, iclass 28, count 0 2006.286.02:41:12.99#ibcon#*after write, iclass 28, count 0 2006.286.02:41:12.99#ibcon#*before return 0, iclass 28, count 0 2006.286.02:41:12.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.02:41:12.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.02:41:12.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.02:41:12.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.02:41:12.99$vck44/vb=4,5 2006.286.02:41:12.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.02:41:12.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.02:41:12.99#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:12.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.02:41:13.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.02:41:13.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.02:41:13.05#ibcon#enter wrdev, iclass 30, count 2 2006.286.02:41:13.05#ibcon#first serial, iclass 30, count 2 2006.286.02:41:13.05#ibcon#enter sib2, iclass 30, count 2 2006.286.02:41:13.05#ibcon#flushed, iclass 30, count 2 2006.286.02:41:13.05#ibcon#about to write, iclass 30, count 2 2006.286.02:41:13.05#ibcon#wrote, iclass 30, count 2 2006.286.02:41:13.05#ibcon#about to read 3, iclass 30, count 2 2006.286.02:41:13.07#ibcon#read 3, iclass 30, count 2 2006.286.02:41:13.07#ibcon#about to read 4, iclass 30, count 2 2006.286.02:41:13.07#ibcon#read 4, iclass 30, count 2 2006.286.02:41:13.07#ibcon#about to read 5, iclass 30, count 2 2006.286.02:41:13.07#ibcon#read 5, iclass 30, count 2 2006.286.02:41:13.07#ibcon#about to read 6, iclass 30, count 2 2006.286.02:41:13.07#ibcon#read 6, iclass 30, count 2 2006.286.02:41:13.07#ibcon#end of sib2, iclass 30, count 2 2006.286.02:41:13.07#ibcon#*mode == 0, iclass 30, count 2 2006.286.02:41:13.07#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.02:41:13.07#ibcon#[27=AT04-05\r\n] 2006.286.02:41:13.07#ibcon#*before write, iclass 30, count 2 2006.286.02:41:13.07#ibcon#enter sib2, iclass 30, count 2 2006.286.02:41:13.07#ibcon#flushed, iclass 30, count 2 2006.286.02:41:13.07#ibcon#about to write, iclass 30, count 2 2006.286.02:41:13.07#ibcon#wrote, iclass 30, count 2 2006.286.02:41:13.07#ibcon#about to read 3, iclass 30, count 2 2006.286.02:41:13.10#ibcon#read 3, iclass 30, count 2 2006.286.02:41:13.10#ibcon#about to read 4, iclass 30, count 2 2006.286.02:41:13.10#ibcon#read 4, iclass 30, count 2 2006.286.02:41:13.10#ibcon#about to read 5, iclass 30, count 2 2006.286.02:41:13.10#ibcon#read 5, iclass 30, count 2 2006.286.02:41:13.10#ibcon#about to read 6, iclass 30, count 2 2006.286.02:41:13.10#ibcon#read 6, iclass 30, count 2 2006.286.02:41:13.10#ibcon#end of sib2, iclass 30, count 2 2006.286.02:41:13.10#ibcon#*after write, iclass 30, count 2 2006.286.02:41:13.10#ibcon#*before return 0, iclass 30, count 2 2006.286.02:41:13.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.02:41:13.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.02:41:13.10#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.02:41:13.10#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:13.10#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.02:41:13.22#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.02:41:13.22#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.02:41:13.22#ibcon#enter wrdev, iclass 30, count 0 2006.286.02:41:13.22#ibcon#first serial, iclass 30, count 0 2006.286.02:41:13.22#ibcon#enter sib2, iclass 30, count 0 2006.286.02:41:13.22#ibcon#flushed, iclass 30, count 0 2006.286.02:41:13.22#ibcon#about to write, iclass 30, count 0 2006.286.02:41:13.22#ibcon#wrote, iclass 30, count 0 2006.286.02:41:13.22#ibcon#about to read 3, iclass 30, count 0 2006.286.02:41:13.24#ibcon#read 3, iclass 30, count 0 2006.286.02:41:13.24#ibcon#about to read 4, iclass 30, count 0 2006.286.02:41:13.24#ibcon#read 4, iclass 30, count 0 2006.286.02:41:13.24#ibcon#about to read 5, iclass 30, count 0 2006.286.02:41:13.24#ibcon#read 5, iclass 30, count 0 2006.286.02:41:13.24#ibcon#about to read 6, iclass 30, count 0 2006.286.02:41:13.24#ibcon#read 6, iclass 30, count 0 2006.286.02:41:13.24#ibcon#end of sib2, iclass 30, count 0 2006.286.02:41:13.24#ibcon#*mode == 0, iclass 30, count 0 2006.286.02:41:13.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.02:41:13.24#ibcon#[27=USB\r\n] 2006.286.02:41:13.24#ibcon#*before write, iclass 30, count 0 2006.286.02:41:13.24#ibcon#enter sib2, iclass 30, count 0 2006.286.02:41:13.24#ibcon#flushed, iclass 30, count 0 2006.286.02:41:13.24#ibcon#about to write, iclass 30, count 0 2006.286.02:41:13.24#ibcon#wrote, iclass 30, count 0 2006.286.02:41:13.24#ibcon#about to read 3, iclass 30, count 0 2006.286.02:41:13.27#ibcon#read 3, iclass 30, count 0 2006.286.02:41:13.27#ibcon#about to read 4, iclass 30, count 0 2006.286.02:41:13.27#ibcon#read 4, iclass 30, count 0 2006.286.02:41:13.27#ibcon#about to read 5, iclass 30, count 0 2006.286.02:41:13.27#ibcon#read 5, iclass 30, count 0 2006.286.02:41:13.27#ibcon#about to read 6, iclass 30, count 0 2006.286.02:41:13.27#ibcon#read 6, iclass 30, count 0 2006.286.02:41:13.27#ibcon#end of sib2, iclass 30, count 0 2006.286.02:41:13.27#ibcon#*after write, iclass 30, count 0 2006.286.02:41:13.27#ibcon#*before return 0, iclass 30, count 0 2006.286.02:41:13.27#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.02:41:13.27#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.02:41:13.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.02:41:13.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.02:41:13.27$vck44/vblo=5,709.99 2006.286.02:41:13.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.02:41:13.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.02:41:13.27#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:13.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.02:41:13.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.02:41:13.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.02:41:13.27#ibcon#enter wrdev, iclass 32, count 0 2006.286.02:41:13.27#ibcon#first serial, iclass 32, count 0 2006.286.02:41:13.27#ibcon#enter sib2, iclass 32, count 0 2006.286.02:41:13.27#ibcon#flushed, iclass 32, count 0 2006.286.02:41:13.28#ibcon#about to write, iclass 32, count 0 2006.286.02:41:13.28#ibcon#wrote, iclass 32, count 0 2006.286.02:41:13.28#ibcon#about to read 3, iclass 32, count 0 2006.286.02:41:13.29#ibcon#read 3, iclass 32, count 0 2006.286.02:41:13.29#ibcon#about to read 4, iclass 32, count 0 2006.286.02:41:13.29#ibcon#read 4, iclass 32, count 0 2006.286.02:41:13.29#ibcon#about to read 5, iclass 32, count 0 2006.286.02:41:13.29#ibcon#read 5, iclass 32, count 0 2006.286.02:41:13.29#ibcon#about to read 6, iclass 32, count 0 2006.286.02:41:13.29#ibcon#read 6, iclass 32, count 0 2006.286.02:41:13.29#ibcon#end of sib2, iclass 32, count 0 2006.286.02:41:13.29#ibcon#*mode == 0, iclass 32, count 0 2006.286.02:41:13.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.02:41:13.29#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.02:41:13.29#ibcon#*before write, iclass 32, count 0 2006.286.02:41:13.29#ibcon#enter sib2, iclass 32, count 0 2006.286.02:41:13.29#ibcon#flushed, iclass 32, count 0 2006.286.02:41:13.29#ibcon#about to write, iclass 32, count 0 2006.286.02:41:13.29#ibcon#wrote, iclass 32, count 0 2006.286.02:41:13.29#ibcon#about to read 3, iclass 32, count 0 2006.286.02:41:13.33#ibcon#read 3, iclass 32, count 0 2006.286.02:41:13.33#ibcon#about to read 4, iclass 32, count 0 2006.286.02:41:13.33#ibcon#read 4, iclass 32, count 0 2006.286.02:41:13.33#ibcon#about to read 5, iclass 32, count 0 2006.286.02:41:13.33#ibcon#read 5, iclass 32, count 0 2006.286.02:41:13.33#ibcon#about to read 6, iclass 32, count 0 2006.286.02:41:13.33#ibcon#read 6, iclass 32, count 0 2006.286.02:41:13.33#ibcon#end of sib2, iclass 32, count 0 2006.286.02:41:13.33#ibcon#*after write, iclass 32, count 0 2006.286.02:41:13.33#ibcon#*before return 0, iclass 32, count 0 2006.286.02:41:13.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.02:41:13.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.02:41:13.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.02:41:13.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.02:41:13.33$vck44/vb=5,4 2006.286.02:41:13.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.02:41:13.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.02:41:13.33#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:13.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.02:41:13.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.02:41:13.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.02:41:13.39#ibcon#enter wrdev, iclass 34, count 2 2006.286.02:41:13.39#ibcon#first serial, iclass 34, count 2 2006.286.02:41:13.39#ibcon#enter sib2, iclass 34, count 2 2006.286.02:41:13.39#ibcon#flushed, iclass 34, count 2 2006.286.02:41:13.39#ibcon#about to write, iclass 34, count 2 2006.286.02:41:13.39#ibcon#wrote, iclass 34, count 2 2006.286.02:41:13.39#ibcon#about to read 3, iclass 34, count 2 2006.286.02:41:13.41#ibcon#read 3, iclass 34, count 2 2006.286.02:41:13.41#ibcon#about to read 4, iclass 34, count 2 2006.286.02:41:13.41#ibcon#read 4, iclass 34, count 2 2006.286.02:41:13.41#ibcon#about to read 5, iclass 34, count 2 2006.286.02:41:13.41#ibcon#read 5, iclass 34, count 2 2006.286.02:41:13.41#ibcon#about to read 6, iclass 34, count 2 2006.286.02:41:13.41#ibcon#read 6, iclass 34, count 2 2006.286.02:41:13.41#ibcon#end of sib2, iclass 34, count 2 2006.286.02:41:13.41#ibcon#*mode == 0, iclass 34, count 2 2006.286.02:41:13.41#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.02:41:13.41#ibcon#[27=AT05-04\r\n] 2006.286.02:41:13.41#ibcon#*before write, iclass 34, count 2 2006.286.02:41:13.41#ibcon#enter sib2, iclass 34, count 2 2006.286.02:41:13.41#ibcon#flushed, iclass 34, count 2 2006.286.02:41:13.41#ibcon#about to write, iclass 34, count 2 2006.286.02:41:13.41#ibcon#wrote, iclass 34, count 2 2006.286.02:41:13.41#ibcon#about to read 3, iclass 34, count 2 2006.286.02:41:13.44#ibcon#read 3, iclass 34, count 2 2006.286.02:41:13.44#ibcon#about to read 4, iclass 34, count 2 2006.286.02:41:13.44#ibcon#read 4, iclass 34, count 2 2006.286.02:41:13.44#ibcon#about to read 5, iclass 34, count 2 2006.286.02:41:13.44#ibcon#read 5, iclass 34, count 2 2006.286.02:41:13.44#ibcon#about to read 6, iclass 34, count 2 2006.286.02:41:13.44#ibcon#read 6, iclass 34, count 2 2006.286.02:41:13.44#ibcon#end of sib2, iclass 34, count 2 2006.286.02:41:13.44#ibcon#*after write, iclass 34, count 2 2006.286.02:41:13.44#ibcon#*before return 0, iclass 34, count 2 2006.286.02:41:13.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.02:41:13.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.02:41:13.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.02:41:13.44#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:13.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.02:41:13.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.02:41:13.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.02:41:13.56#ibcon#enter wrdev, iclass 34, count 0 2006.286.02:41:13.56#ibcon#first serial, iclass 34, count 0 2006.286.02:41:13.56#ibcon#enter sib2, iclass 34, count 0 2006.286.02:41:13.56#ibcon#flushed, iclass 34, count 0 2006.286.02:41:13.56#ibcon#about to write, iclass 34, count 0 2006.286.02:41:13.56#ibcon#wrote, iclass 34, count 0 2006.286.02:41:13.56#ibcon#about to read 3, iclass 34, count 0 2006.286.02:41:13.58#ibcon#read 3, iclass 34, count 0 2006.286.02:41:13.58#ibcon#about to read 4, iclass 34, count 0 2006.286.02:41:13.58#ibcon#read 4, iclass 34, count 0 2006.286.02:41:13.58#ibcon#about to read 5, iclass 34, count 0 2006.286.02:41:13.58#ibcon#read 5, iclass 34, count 0 2006.286.02:41:13.58#ibcon#about to read 6, iclass 34, count 0 2006.286.02:41:13.58#ibcon#read 6, iclass 34, count 0 2006.286.02:41:13.58#ibcon#end of sib2, iclass 34, count 0 2006.286.02:41:13.58#ibcon#*mode == 0, iclass 34, count 0 2006.286.02:41:13.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.02:41:13.58#ibcon#[27=USB\r\n] 2006.286.02:41:13.58#ibcon#*before write, iclass 34, count 0 2006.286.02:41:13.58#ibcon#enter sib2, iclass 34, count 0 2006.286.02:41:13.58#ibcon#flushed, iclass 34, count 0 2006.286.02:41:13.58#ibcon#about to write, iclass 34, count 0 2006.286.02:41:13.58#ibcon#wrote, iclass 34, count 0 2006.286.02:41:13.58#ibcon#about to read 3, iclass 34, count 0 2006.286.02:41:13.61#ibcon#read 3, iclass 34, count 0 2006.286.02:41:13.61#ibcon#about to read 4, iclass 34, count 0 2006.286.02:41:13.61#ibcon#read 4, iclass 34, count 0 2006.286.02:41:13.61#ibcon#about to read 5, iclass 34, count 0 2006.286.02:41:13.61#ibcon#read 5, iclass 34, count 0 2006.286.02:41:13.61#ibcon#about to read 6, iclass 34, count 0 2006.286.02:41:13.61#ibcon#read 6, iclass 34, count 0 2006.286.02:41:13.61#ibcon#end of sib2, iclass 34, count 0 2006.286.02:41:13.61#ibcon#*after write, iclass 34, count 0 2006.286.02:41:13.61#ibcon#*before return 0, iclass 34, count 0 2006.286.02:41:13.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.02:41:13.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.02:41:13.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.02:41:13.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.02:41:13.61$vck44/vblo=6,719.99 2006.286.02:41:13.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.02:41:13.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.02:41:13.61#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:13.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:41:13.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:41:13.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:41:13.61#ibcon#enter wrdev, iclass 36, count 0 2006.286.02:41:13.61#ibcon#first serial, iclass 36, count 0 2006.286.02:41:13.61#ibcon#enter sib2, iclass 36, count 0 2006.286.02:41:13.61#ibcon#flushed, iclass 36, count 0 2006.286.02:41:13.61#ibcon#about to write, iclass 36, count 0 2006.286.02:41:13.62#ibcon#wrote, iclass 36, count 0 2006.286.02:41:13.62#ibcon#about to read 3, iclass 36, count 0 2006.286.02:41:13.63#ibcon#read 3, iclass 36, count 0 2006.286.02:41:13.63#ibcon#about to read 4, iclass 36, count 0 2006.286.02:41:13.63#ibcon#read 4, iclass 36, count 0 2006.286.02:41:13.63#ibcon#about to read 5, iclass 36, count 0 2006.286.02:41:13.63#ibcon#read 5, iclass 36, count 0 2006.286.02:41:13.63#ibcon#about to read 6, iclass 36, count 0 2006.286.02:41:13.63#ibcon#read 6, iclass 36, count 0 2006.286.02:41:13.63#ibcon#end of sib2, iclass 36, count 0 2006.286.02:41:13.63#ibcon#*mode == 0, iclass 36, count 0 2006.286.02:41:13.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.02:41:13.63#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.02:41:13.63#ibcon#*before write, iclass 36, count 0 2006.286.02:41:13.63#ibcon#enter sib2, iclass 36, count 0 2006.286.02:41:13.63#ibcon#flushed, iclass 36, count 0 2006.286.02:41:13.63#ibcon#about to write, iclass 36, count 0 2006.286.02:41:13.63#ibcon#wrote, iclass 36, count 0 2006.286.02:41:13.63#ibcon#about to read 3, iclass 36, count 0 2006.286.02:41:13.67#ibcon#read 3, iclass 36, count 0 2006.286.02:41:13.67#ibcon#about to read 4, iclass 36, count 0 2006.286.02:41:13.67#ibcon#read 4, iclass 36, count 0 2006.286.02:41:13.67#ibcon#about to read 5, iclass 36, count 0 2006.286.02:41:13.67#ibcon#read 5, iclass 36, count 0 2006.286.02:41:13.67#ibcon#about to read 6, iclass 36, count 0 2006.286.02:41:13.67#ibcon#read 6, iclass 36, count 0 2006.286.02:41:13.67#ibcon#end of sib2, iclass 36, count 0 2006.286.02:41:13.67#ibcon#*after write, iclass 36, count 0 2006.286.02:41:13.67#ibcon#*before return 0, iclass 36, count 0 2006.286.02:41:13.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:41:13.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.02:41:13.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.02:41:13.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.02:41:13.67$vck44/vb=6,3 2006.286.02:41:13.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.02:41:13.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.02:41:13.67#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:13.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.02:41:13.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.02:41:13.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.02:41:13.73#ibcon#enter wrdev, iclass 38, count 2 2006.286.02:41:13.73#ibcon#first serial, iclass 38, count 2 2006.286.02:41:13.73#ibcon#enter sib2, iclass 38, count 2 2006.286.02:41:13.73#ibcon#flushed, iclass 38, count 2 2006.286.02:41:13.73#ibcon#about to write, iclass 38, count 2 2006.286.02:41:13.73#ibcon#wrote, iclass 38, count 2 2006.286.02:41:13.73#ibcon#about to read 3, iclass 38, count 2 2006.286.02:41:13.75#ibcon#read 3, iclass 38, count 2 2006.286.02:41:13.75#ibcon#about to read 4, iclass 38, count 2 2006.286.02:41:13.75#ibcon#read 4, iclass 38, count 2 2006.286.02:41:13.75#ibcon#about to read 5, iclass 38, count 2 2006.286.02:41:13.75#ibcon#read 5, iclass 38, count 2 2006.286.02:41:13.75#ibcon#about to read 6, iclass 38, count 2 2006.286.02:41:13.75#ibcon#read 6, iclass 38, count 2 2006.286.02:41:13.75#ibcon#end of sib2, iclass 38, count 2 2006.286.02:41:13.75#ibcon#*mode == 0, iclass 38, count 2 2006.286.02:41:13.75#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.02:41:13.75#ibcon#[27=AT06-03\r\n] 2006.286.02:41:13.75#ibcon#*before write, iclass 38, count 2 2006.286.02:41:13.75#ibcon#enter sib2, iclass 38, count 2 2006.286.02:41:13.75#ibcon#flushed, iclass 38, count 2 2006.286.02:41:13.75#ibcon#about to write, iclass 38, count 2 2006.286.02:41:13.75#ibcon#wrote, iclass 38, count 2 2006.286.02:41:13.75#ibcon#about to read 3, iclass 38, count 2 2006.286.02:41:13.78#ibcon#read 3, iclass 38, count 2 2006.286.02:41:13.78#ibcon#about to read 4, iclass 38, count 2 2006.286.02:41:13.78#ibcon#read 4, iclass 38, count 2 2006.286.02:41:13.78#ibcon#about to read 5, iclass 38, count 2 2006.286.02:41:13.78#ibcon#read 5, iclass 38, count 2 2006.286.02:41:13.78#ibcon#about to read 6, iclass 38, count 2 2006.286.02:41:13.78#ibcon#read 6, iclass 38, count 2 2006.286.02:41:13.78#ibcon#end of sib2, iclass 38, count 2 2006.286.02:41:13.78#ibcon#*after write, iclass 38, count 2 2006.286.02:41:13.78#ibcon#*before return 0, iclass 38, count 2 2006.286.02:41:13.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.02:41:13.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.02:41:13.78#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.02:41:13.78#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:13.78#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.02:41:13.90#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.02:41:13.90#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.02:41:13.90#ibcon#enter wrdev, iclass 38, count 0 2006.286.02:41:13.90#ibcon#first serial, iclass 38, count 0 2006.286.02:41:13.90#ibcon#enter sib2, iclass 38, count 0 2006.286.02:41:13.90#ibcon#flushed, iclass 38, count 0 2006.286.02:41:13.90#ibcon#about to write, iclass 38, count 0 2006.286.02:41:13.90#ibcon#wrote, iclass 38, count 0 2006.286.02:41:13.90#ibcon#about to read 3, iclass 38, count 0 2006.286.02:41:13.92#ibcon#read 3, iclass 38, count 0 2006.286.02:41:13.92#ibcon#about to read 4, iclass 38, count 0 2006.286.02:41:13.92#ibcon#read 4, iclass 38, count 0 2006.286.02:41:13.92#ibcon#about to read 5, iclass 38, count 0 2006.286.02:41:13.92#ibcon#read 5, iclass 38, count 0 2006.286.02:41:13.92#ibcon#about to read 6, iclass 38, count 0 2006.286.02:41:13.92#ibcon#read 6, iclass 38, count 0 2006.286.02:41:13.92#ibcon#end of sib2, iclass 38, count 0 2006.286.02:41:13.92#ibcon#*mode == 0, iclass 38, count 0 2006.286.02:41:13.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.02:41:13.92#ibcon#[27=USB\r\n] 2006.286.02:41:13.92#ibcon#*before write, iclass 38, count 0 2006.286.02:41:13.92#ibcon#enter sib2, iclass 38, count 0 2006.286.02:41:13.92#ibcon#flushed, iclass 38, count 0 2006.286.02:41:13.92#ibcon#about to write, iclass 38, count 0 2006.286.02:41:13.92#ibcon#wrote, iclass 38, count 0 2006.286.02:41:13.92#ibcon#about to read 3, iclass 38, count 0 2006.286.02:41:13.95#ibcon#read 3, iclass 38, count 0 2006.286.02:41:13.95#ibcon#about to read 4, iclass 38, count 0 2006.286.02:41:13.95#ibcon#read 4, iclass 38, count 0 2006.286.02:41:13.95#ibcon#about to read 5, iclass 38, count 0 2006.286.02:41:13.95#ibcon#read 5, iclass 38, count 0 2006.286.02:41:13.95#ibcon#about to read 6, iclass 38, count 0 2006.286.02:41:13.95#ibcon#read 6, iclass 38, count 0 2006.286.02:41:13.95#ibcon#end of sib2, iclass 38, count 0 2006.286.02:41:13.95#ibcon#*after write, iclass 38, count 0 2006.286.02:41:13.95#ibcon#*before return 0, iclass 38, count 0 2006.286.02:41:13.95#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.02:41:13.95#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.02:41:13.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.02:41:13.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.02:41:13.95$vck44/vblo=7,734.99 2006.286.02:41:13.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.02:41:13.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.02:41:13.95#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:13.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.02:41:13.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.02:41:13.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.02:41:13.95#ibcon#enter wrdev, iclass 40, count 0 2006.286.02:41:13.95#ibcon#first serial, iclass 40, count 0 2006.286.02:41:13.95#ibcon#enter sib2, iclass 40, count 0 2006.286.02:41:13.95#ibcon#flushed, iclass 40, count 0 2006.286.02:41:13.96#ibcon#about to write, iclass 40, count 0 2006.286.02:41:13.96#ibcon#wrote, iclass 40, count 0 2006.286.02:41:13.96#ibcon#about to read 3, iclass 40, count 0 2006.286.02:41:13.97#ibcon#read 3, iclass 40, count 0 2006.286.02:41:13.97#ibcon#about to read 4, iclass 40, count 0 2006.286.02:41:13.97#ibcon#read 4, iclass 40, count 0 2006.286.02:41:13.97#ibcon#about to read 5, iclass 40, count 0 2006.286.02:41:13.97#ibcon#read 5, iclass 40, count 0 2006.286.02:41:13.97#ibcon#about to read 6, iclass 40, count 0 2006.286.02:41:13.97#ibcon#read 6, iclass 40, count 0 2006.286.02:41:13.97#ibcon#end of sib2, iclass 40, count 0 2006.286.02:41:13.97#ibcon#*mode == 0, iclass 40, count 0 2006.286.02:41:13.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.02:41:13.97#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.02:41:13.97#ibcon#*before write, iclass 40, count 0 2006.286.02:41:13.97#ibcon#enter sib2, iclass 40, count 0 2006.286.02:41:13.97#ibcon#flushed, iclass 40, count 0 2006.286.02:41:13.97#ibcon#about to write, iclass 40, count 0 2006.286.02:41:13.97#ibcon#wrote, iclass 40, count 0 2006.286.02:41:13.97#ibcon#about to read 3, iclass 40, count 0 2006.286.02:41:14.01#ibcon#read 3, iclass 40, count 0 2006.286.02:41:14.01#ibcon#about to read 4, iclass 40, count 0 2006.286.02:41:14.01#ibcon#read 4, iclass 40, count 0 2006.286.02:41:14.01#ibcon#about to read 5, iclass 40, count 0 2006.286.02:41:14.01#ibcon#read 5, iclass 40, count 0 2006.286.02:41:14.01#ibcon#about to read 6, iclass 40, count 0 2006.286.02:41:14.01#ibcon#read 6, iclass 40, count 0 2006.286.02:41:14.01#ibcon#end of sib2, iclass 40, count 0 2006.286.02:41:14.01#ibcon#*after write, iclass 40, count 0 2006.286.02:41:14.01#ibcon#*before return 0, iclass 40, count 0 2006.286.02:41:14.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.02:41:14.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.02:41:14.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.02:41:14.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.02:41:14.01$vck44/vb=7,4 2006.286.02:41:14.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.02:41:14.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.02:41:14.01#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:14.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.02:41:14.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.02:41:14.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.02:41:14.07#ibcon#enter wrdev, iclass 4, count 2 2006.286.02:41:14.07#ibcon#first serial, iclass 4, count 2 2006.286.02:41:14.07#ibcon#enter sib2, iclass 4, count 2 2006.286.02:41:14.07#ibcon#flushed, iclass 4, count 2 2006.286.02:41:14.07#ibcon#about to write, iclass 4, count 2 2006.286.02:41:14.07#ibcon#wrote, iclass 4, count 2 2006.286.02:41:14.07#ibcon#about to read 3, iclass 4, count 2 2006.286.02:41:14.09#ibcon#read 3, iclass 4, count 2 2006.286.02:41:14.09#ibcon#about to read 4, iclass 4, count 2 2006.286.02:41:14.09#ibcon#read 4, iclass 4, count 2 2006.286.02:41:14.09#ibcon#about to read 5, iclass 4, count 2 2006.286.02:41:14.09#ibcon#read 5, iclass 4, count 2 2006.286.02:41:14.09#ibcon#about to read 6, iclass 4, count 2 2006.286.02:41:14.09#ibcon#read 6, iclass 4, count 2 2006.286.02:41:14.09#ibcon#end of sib2, iclass 4, count 2 2006.286.02:41:14.09#ibcon#*mode == 0, iclass 4, count 2 2006.286.02:41:14.09#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.02:41:14.09#ibcon#[27=AT07-04\r\n] 2006.286.02:41:14.09#ibcon#*before write, iclass 4, count 2 2006.286.02:41:14.09#ibcon#enter sib2, iclass 4, count 2 2006.286.02:41:14.09#ibcon#flushed, iclass 4, count 2 2006.286.02:41:14.09#ibcon#about to write, iclass 4, count 2 2006.286.02:41:14.09#ibcon#wrote, iclass 4, count 2 2006.286.02:41:14.09#ibcon#about to read 3, iclass 4, count 2 2006.286.02:41:14.12#ibcon#read 3, iclass 4, count 2 2006.286.02:41:14.12#ibcon#about to read 4, iclass 4, count 2 2006.286.02:41:14.12#ibcon#read 4, iclass 4, count 2 2006.286.02:41:14.12#ibcon#about to read 5, iclass 4, count 2 2006.286.02:41:14.12#ibcon#read 5, iclass 4, count 2 2006.286.02:41:14.12#ibcon#about to read 6, iclass 4, count 2 2006.286.02:41:14.12#ibcon#read 6, iclass 4, count 2 2006.286.02:41:14.12#ibcon#end of sib2, iclass 4, count 2 2006.286.02:41:14.12#ibcon#*after write, iclass 4, count 2 2006.286.02:41:14.12#ibcon#*before return 0, iclass 4, count 2 2006.286.02:41:14.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.02:41:14.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.02:41:14.12#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.02:41:14.12#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:14.12#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.02:41:14.24#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.02:41:14.24#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.02:41:14.24#ibcon#enter wrdev, iclass 4, count 0 2006.286.02:41:14.24#ibcon#first serial, iclass 4, count 0 2006.286.02:41:14.24#ibcon#enter sib2, iclass 4, count 0 2006.286.02:41:14.24#ibcon#flushed, iclass 4, count 0 2006.286.02:41:14.24#ibcon#about to write, iclass 4, count 0 2006.286.02:41:14.24#ibcon#wrote, iclass 4, count 0 2006.286.02:41:14.24#ibcon#about to read 3, iclass 4, count 0 2006.286.02:41:14.26#ibcon#read 3, iclass 4, count 0 2006.286.02:41:14.26#ibcon#about to read 4, iclass 4, count 0 2006.286.02:41:14.26#ibcon#read 4, iclass 4, count 0 2006.286.02:41:14.26#ibcon#about to read 5, iclass 4, count 0 2006.286.02:41:14.26#ibcon#read 5, iclass 4, count 0 2006.286.02:41:14.26#ibcon#about to read 6, iclass 4, count 0 2006.286.02:41:14.26#ibcon#read 6, iclass 4, count 0 2006.286.02:41:14.26#ibcon#end of sib2, iclass 4, count 0 2006.286.02:41:14.26#ibcon#*mode == 0, iclass 4, count 0 2006.286.02:41:14.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.02:41:14.26#ibcon#[27=USB\r\n] 2006.286.02:41:14.26#ibcon#*before write, iclass 4, count 0 2006.286.02:41:14.26#ibcon#enter sib2, iclass 4, count 0 2006.286.02:41:14.26#ibcon#flushed, iclass 4, count 0 2006.286.02:41:14.26#ibcon#about to write, iclass 4, count 0 2006.286.02:41:14.26#ibcon#wrote, iclass 4, count 0 2006.286.02:41:14.26#ibcon#about to read 3, iclass 4, count 0 2006.286.02:41:14.29#ibcon#read 3, iclass 4, count 0 2006.286.02:41:14.29#ibcon#about to read 4, iclass 4, count 0 2006.286.02:41:14.29#ibcon#read 4, iclass 4, count 0 2006.286.02:41:14.29#ibcon#about to read 5, iclass 4, count 0 2006.286.02:41:14.29#ibcon#read 5, iclass 4, count 0 2006.286.02:41:14.29#ibcon#about to read 6, iclass 4, count 0 2006.286.02:41:14.29#ibcon#read 6, iclass 4, count 0 2006.286.02:41:14.29#ibcon#end of sib2, iclass 4, count 0 2006.286.02:41:14.29#ibcon#*after write, iclass 4, count 0 2006.286.02:41:14.29#ibcon#*before return 0, iclass 4, count 0 2006.286.02:41:14.29#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.02:41:14.29#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.02:41:14.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.02:41:14.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.02:41:14.29$vck44/vblo=8,744.99 2006.286.02:41:14.29#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.02:41:14.29#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.02:41:14.29#ibcon#ireg 17 cls_cnt 0 2006.286.02:41:14.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.02:41:14.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.02:41:14.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.02:41:14.29#ibcon#enter wrdev, iclass 6, count 0 2006.286.02:41:14.29#ibcon#first serial, iclass 6, count 0 2006.286.02:41:14.29#ibcon#enter sib2, iclass 6, count 0 2006.286.02:41:14.29#ibcon#flushed, iclass 6, count 0 2006.286.02:41:14.29#ibcon#about to write, iclass 6, count 0 2006.286.02:41:14.30#ibcon#wrote, iclass 6, count 0 2006.286.02:41:14.30#ibcon#about to read 3, iclass 6, count 0 2006.286.02:41:14.31#ibcon#read 3, iclass 6, count 0 2006.286.02:41:14.31#ibcon#about to read 4, iclass 6, count 0 2006.286.02:41:14.31#ibcon#read 4, iclass 6, count 0 2006.286.02:41:14.31#ibcon#about to read 5, iclass 6, count 0 2006.286.02:41:14.31#ibcon#read 5, iclass 6, count 0 2006.286.02:41:14.31#ibcon#about to read 6, iclass 6, count 0 2006.286.02:41:14.31#ibcon#read 6, iclass 6, count 0 2006.286.02:41:14.31#ibcon#end of sib2, iclass 6, count 0 2006.286.02:41:14.31#ibcon#*mode == 0, iclass 6, count 0 2006.286.02:41:14.31#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.02:41:14.31#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.02:41:14.31#ibcon#*before write, iclass 6, count 0 2006.286.02:41:14.31#ibcon#enter sib2, iclass 6, count 0 2006.286.02:41:14.31#ibcon#flushed, iclass 6, count 0 2006.286.02:41:14.31#ibcon#about to write, iclass 6, count 0 2006.286.02:41:14.31#ibcon#wrote, iclass 6, count 0 2006.286.02:41:14.31#ibcon#about to read 3, iclass 6, count 0 2006.286.02:41:14.35#ibcon#read 3, iclass 6, count 0 2006.286.02:41:14.35#ibcon#about to read 4, iclass 6, count 0 2006.286.02:41:14.35#ibcon#read 4, iclass 6, count 0 2006.286.02:41:14.35#ibcon#about to read 5, iclass 6, count 0 2006.286.02:41:14.35#ibcon#read 5, iclass 6, count 0 2006.286.02:41:14.35#ibcon#about to read 6, iclass 6, count 0 2006.286.02:41:14.35#ibcon#read 6, iclass 6, count 0 2006.286.02:41:14.35#ibcon#end of sib2, iclass 6, count 0 2006.286.02:41:14.35#ibcon#*after write, iclass 6, count 0 2006.286.02:41:14.35#ibcon#*before return 0, iclass 6, count 0 2006.286.02:41:14.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.02:41:14.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.02:41:14.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.02:41:14.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.02:41:14.35$vck44/vb=8,4 2006.286.02:41:14.35#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.02:41:14.35#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.02:41:14.35#ibcon#ireg 11 cls_cnt 2 2006.286.02:41:14.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.02:41:14.41#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.02:41:14.41#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.02:41:14.41#ibcon#enter wrdev, iclass 10, count 2 2006.286.02:41:14.41#ibcon#first serial, iclass 10, count 2 2006.286.02:41:14.41#ibcon#enter sib2, iclass 10, count 2 2006.286.02:41:14.41#ibcon#flushed, iclass 10, count 2 2006.286.02:41:14.41#ibcon#about to write, iclass 10, count 2 2006.286.02:41:14.41#ibcon#wrote, iclass 10, count 2 2006.286.02:41:14.41#ibcon#about to read 3, iclass 10, count 2 2006.286.02:41:14.43#ibcon#read 3, iclass 10, count 2 2006.286.02:41:14.43#ibcon#about to read 4, iclass 10, count 2 2006.286.02:41:14.43#ibcon#read 4, iclass 10, count 2 2006.286.02:41:14.43#ibcon#about to read 5, iclass 10, count 2 2006.286.02:41:14.43#ibcon#read 5, iclass 10, count 2 2006.286.02:41:14.43#ibcon#about to read 6, iclass 10, count 2 2006.286.02:41:14.43#ibcon#read 6, iclass 10, count 2 2006.286.02:41:14.43#ibcon#end of sib2, iclass 10, count 2 2006.286.02:41:14.43#ibcon#*mode == 0, iclass 10, count 2 2006.286.02:41:14.43#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.02:41:14.43#ibcon#[27=AT08-04\r\n] 2006.286.02:41:14.43#ibcon#*before write, iclass 10, count 2 2006.286.02:41:14.43#ibcon#enter sib2, iclass 10, count 2 2006.286.02:41:14.43#ibcon#flushed, iclass 10, count 2 2006.286.02:41:14.43#ibcon#about to write, iclass 10, count 2 2006.286.02:41:14.43#ibcon#wrote, iclass 10, count 2 2006.286.02:41:14.43#ibcon#about to read 3, iclass 10, count 2 2006.286.02:41:14.46#ibcon#read 3, iclass 10, count 2 2006.286.02:41:14.46#ibcon#about to read 4, iclass 10, count 2 2006.286.02:41:14.46#ibcon#read 4, iclass 10, count 2 2006.286.02:41:14.46#ibcon#about to read 5, iclass 10, count 2 2006.286.02:41:14.46#ibcon#read 5, iclass 10, count 2 2006.286.02:41:14.46#ibcon#about to read 6, iclass 10, count 2 2006.286.02:41:14.46#ibcon#read 6, iclass 10, count 2 2006.286.02:41:14.46#ibcon#end of sib2, iclass 10, count 2 2006.286.02:41:14.46#ibcon#*after write, iclass 10, count 2 2006.286.02:41:14.46#ibcon#*before return 0, iclass 10, count 2 2006.286.02:41:14.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.02:41:14.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.02:41:14.46#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.02:41:14.46#ibcon#ireg 7 cls_cnt 0 2006.286.02:41:14.46#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.02:41:14.58#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.02:41:14.58#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.02:41:14.58#ibcon#enter wrdev, iclass 10, count 0 2006.286.02:41:14.58#ibcon#first serial, iclass 10, count 0 2006.286.02:41:14.58#ibcon#enter sib2, iclass 10, count 0 2006.286.02:41:14.58#ibcon#flushed, iclass 10, count 0 2006.286.02:41:14.58#ibcon#about to write, iclass 10, count 0 2006.286.02:41:14.58#ibcon#wrote, iclass 10, count 0 2006.286.02:41:14.58#ibcon#about to read 3, iclass 10, count 0 2006.286.02:41:14.60#ibcon#read 3, iclass 10, count 0 2006.286.02:41:14.60#ibcon#about to read 4, iclass 10, count 0 2006.286.02:41:14.60#ibcon#read 4, iclass 10, count 0 2006.286.02:41:14.60#ibcon#about to read 5, iclass 10, count 0 2006.286.02:41:14.60#ibcon#read 5, iclass 10, count 0 2006.286.02:41:14.60#ibcon#about to read 6, iclass 10, count 0 2006.286.02:41:14.60#ibcon#read 6, iclass 10, count 0 2006.286.02:41:14.60#ibcon#end of sib2, iclass 10, count 0 2006.286.02:41:14.60#ibcon#*mode == 0, iclass 10, count 0 2006.286.02:41:14.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.02:41:14.60#ibcon#[27=USB\r\n] 2006.286.02:41:14.60#ibcon#*before write, iclass 10, count 0 2006.286.02:41:14.60#ibcon#enter sib2, iclass 10, count 0 2006.286.02:41:14.60#ibcon#flushed, iclass 10, count 0 2006.286.02:41:14.60#ibcon#about to write, iclass 10, count 0 2006.286.02:41:14.60#ibcon#wrote, iclass 10, count 0 2006.286.02:41:14.60#ibcon#about to read 3, iclass 10, count 0 2006.286.02:41:14.63#ibcon#read 3, iclass 10, count 0 2006.286.02:41:14.63#ibcon#about to read 4, iclass 10, count 0 2006.286.02:41:14.63#ibcon#read 4, iclass 10, count 0 2006.286.02:41:14.63#ibcon#about to read 5, iclass 10, count 0 2006.286.02:41:14.63#ibcon#read 5, iclass 10, count 0 2006.286.02:41:14.63#ibcon#about to read 6, iclass 10, count 0 2006.286.02:41:14.63#ibcon#read 6, iclass 10, count 0 2006.286.02:41:14.63#ibcon#end of sib2, iclass 10, count 0 2006.286.02:41:14.63#ibcon#*after write, iclass 10, count 0 2006.286.02:41:14.63#ibcon#*before return 0, iclass 10, count 0 2006.286.02:41:14.63#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.02:41:14.63#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.02:41:14.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.02:41:14.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.02:41:14.63$vck44/vabw=wide 2006.286.02:41:14.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.02:41:14.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.02:41:14.63#ibcon#ireg 8 cls_cnt 0 2006.286.02:41:14.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.02:41:14.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.02:41:14.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.02:41:14.63#ibcon#enter wrdev, iclass 12, count 0 2006.286.02:41:14.63#ibcon#first serial, iclass 12, count 0 2006.286.02:41:14.63#ibcon#enter sib2, iclass 12, count 0 2006.286.02:41:14.63#ibcon#flushed, iclass 12, count 0 2006.286.02:41:14.63#ibcon#about to write, iclass 12, count 0 2006.286.02:41:14.63#ibcon#wrote, iclass 12, count 0 2006.286.02:41:14.64#ibcon#about to read 3, iclass 12, count 0 2006.286.02:41:14.65#ibcon#read 3, iclass 12, count 0 2006.286.02:41:14.65#ibcon#about to read 4, iclass 12, count 0 2006.286.02:41:14.65#ibcon#read 4, iclass 12, count 0 2006.286.02:41:14.65#ibcon#about to read 5, iclass 12, count 0 2006.286.02:41:14.65#ibcon#read 5, iclass 12, count 0 2006.286.02:41:14.65#ibcon#about to read 6, iclass 12, count 0 2006.286.02:41:14.65#ibcon#read 6, iclass 12, count 0 2006.286.02:41:14.65#ibcon#end of sib2, iclass 12, count 0 2006.286.02:41:14.65#ibcon#*mode == 0, iclass 12, count 0 2006.286.02:41:14.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.02:41:14.65#ibcon#[25=BW32\r\n] 2006.286.02:41:14.65#ibcon#*before write, iclass 12, count 0 2006.286.02:41:14.65#ibcon#enter sib2, iclass 12, count 0 2006.286.02:41:14.65#ibcon#flushed, iclass 12, count 0 2006.286.02:41:14.65#ibcon#about to write, iclass 12, count 0 2006.286.02:41:14.65#ibcon#wrote, iclass 12, count 0 2006.286.02:41:14.65#ibcon#about to read 3, iclass 12, count 0 2006.286.02:41:14.68#ibcon#read 3, iclass 12, count 0 2006.286.02:41:14.68#ibcon#about to read 4, iclass 12, count 0 2006.286.02:41:14.68#ibcon#read 4, iclass 12, count 0 2006.286.02:41:14.68#ibcon#about to read 5, iclass 12, count 0 2006.286.02:41:14.68#ibcon#read 5, iclass 12, count 0 2006.286.02:41:14.68#ibcon#about to read 6, iclass 12, count 0 2006.286.02:41:14.68#ibcon#read 6, iclass 12, count 0 2006.286.02:41:14.68#ibcon#end of sib2, iclass 12, count 0 2006.286.02:41:14.68#ibcon#*after write, iclass 12, count 0 2006.286.02:41:14.68#ibcon#*before return 0, iclass 12, count 0 2006.286.02:41:14.68#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.02:41:14.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.02:41:14.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.02:41:14.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.02:41:14.68$vck44/vbbw=wide 2006.286.02:41:14.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.02:41:14.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.02:41:14.68#ibcon#ireg 8 cls_cnt 0 2006.286.02:41:14.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:41:14.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:41:14.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:41:14.75#ibcon#enter wrdev, iclass 14, count 0 2006.286.02:41:14.75#ibcon#first serial, iclass 14, count 0 2006.286.02:41:14.75#ibcon#enter sib2, iclass 14, count 0 2006.286.02:41:14.75#ibcon#flushed, iclass 14, count 0 2006.286.02:41:14.75#ibcon#about to write, iclass 14, count 0 2006.286.02:41:14.75#ibcon#wrote, iclass 14, count 0 2006.286.02:41:14.75#ibcon#about to read 3, iclass 14, count 0 2006.286.02:41:14.77#ibcon#read 3, iclass 14, count 0 2006.286.02:41:14.77#ibcon#about to read 4, iclass 14, count 0 2006.286.02:41:14.77#ibcon#read 4, iclass 14, count 0 2006.286.02:41:14.77#ibcon#about to read 5, iclass 14, count 0 2006.286.02:41:14.77#ibcon#read 5, iclass 14, count 0 2006.286.02:41:14.77#ibcon#about to read 6, iclass 14, count 0 2006.286.02:41:14.77#ibcon#read 6, iclass 14, count 0 2006.286.02:41:14.77#ibcon#end of sib2, iclass 14, count 0 2006.286.02:41:14.77#ibcon#*mode == 0, iclass 14, count 0 2006.286.02:41:14.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.02:41:14.77#ibcon#[27=BW32\r\n] 2006.286.02:41:14.77#ibcon#*before write, iclass 14, count 0 2006.286.02:41:14.77#ibcon#enter sib2, iclass 14, count 0 2006.286.02:41:14.77#ibcon#flushed, iclass 14, count 0 2006.286.02:41:14.77#ibcon#about to write, iclass 14, count 0 2006.286.02:41:14.77#ibcon#wrote, iclass 14, count 0 2006.286.02:41:14.77#ibcon#about to read 3, iclass 14, count 0 2006.286.02:41:14.80#ibcon#read 3, iclass 14, count 0 2006.286.02:41:14.80#ibcon#about to read 4, iclass 14, count 0 2006.286.02:41:14.80#ibcon#read 4, iclass 14, count 0 2006.286.02:41:14.80#ibcon#about to read 5, iclass 14, count 0 2006.286.02:41:14.80#ibcon#read 5, iclass 14, count 0 2006.286.02:41:14.80#ibcon#about to read 6, iclass 14, count 0 2006.286.02:41:14.80#ibcon#read 6, iclass 14, count 0 2006.286.02:41:14.80#ibcon#end of sib2, iclass 14, count 0 2006.286.02:41:14.80#ibcon#*after write, iclass 14, count 0 2006.286.02:41:14.80#ibcon#*before return 0, iclass 14, count 0 2006.286.02:41:14.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:41:14.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.02:41:14.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.02:41:14.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.02:41:14.80$setupk4/ifdk4 2006.286.02:41:14.80$ifdk4/lo= 2006.286.02:41:14.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.02:41:14.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.02:41:14.81$ifdk4/patch= 2006.286.02:41:14.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.02:41:14.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.02:41:14.81$setupk4/!*+20s 2006.286.02:41:21.08#abcon#<5=/03 3.2 6.4 21.27 801015.8\r\n> 2006.286.02:41:21.10#abcon#{5=INTERFACE CLEAR} 2006.286.02:41:21.16#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:41:29.33$setupk4/"tpicd 2006.286.02:41:29.33$setupk4/echo=off 2006.286.02:41:29.33$setupk4/xlog=off 2006.286.02:41:29.33:!2006.286.02:44:07 2006.286.02:42:06.13#trakl#Source acquired 2006.286.02:42:07.13#flagr#flagr/antenna,acquired 2006.286.02:44:07.00:preob 2006.286.02:44:08.14/onsource/TRACKING 2006.286.02:44:08.14:!2006.286.02:44:17 2006.286.02:44:17.00:"tape 2006.286.02:44:17.00:"st=record 2006.286.02:44:17.00:data_valid=on 2006.286.02:44:17.00:midob 2006.286.02:44:17.14/onsource/TRACKING 2006.286.02:44:17.14/wx/21.26,1015.8,79 2006.286.02:44:17.27/cable/+6.4997E-03 2006.286.02:44:18.36/va/01,07,usb,yes,35,38 2006.286.02:44:18.36/va/02,06,usb,yes,35,35 2006.286.02:44:18.36/va/03,07,usb,yes,34,36 2006.286.02:44:18.36/va/04,06,usb,yes,36,38 2006.286.02:44:18.36/va/05,03,usb,yes,35,36 2006.286.02:44:18.36/va/06,04,usb,yes,32,31 2006.286.02:44:18.36/va/07,04,usb,yes,33,33 2006.286.02:44:18.36/va/08,03,usb,yes,33,40 2006.286.02:44:18.59/valo/01,524.99,yes,locked 2006.286.02:44:18.59/valo/02,534.99,yes,locked 2006.286.02:44:18.59/valo/03,564.99,yes,locked 2006.286.02:44:18.59/valo/04,624.99,yes,locked 2006.286.02:44:18.59/valo/05,734.99,yes,locked 2006.286.02:44:18.59/valo/06,814.99,yes,locked 2006.286.02:44:18.59/valo/07,864.99,yes,locked 2006.286.02:44:18.59/valo/08,884.99,yes,locked 2006.286.02:44:19.68/vb/01,04,usb,yes,30,29 2006.286.02:44:19.68/vb/02,05,usb,yes,29,29 2006.286.02:44:19.68/vb/03,04,usb,yes,30,33 2006.286.02:44:19.68/vb/04,05,usb,yes,30,29 2006.286.02:44:19.68/vb/05,04,usb,yes,26,29 2006.286.02:44:19.68/vb/06,03,usb,yes,38,34 2006.286.02:44:19.68/vb/07,04,usb,yes,31,31 2006.286.02:44:19.68/vb/08,04,usb,yes,28,32 2006.286.02:44:19.91/vblo/01,629.99,yes,locked 2006.286.02:44:19.91/vblo/02,634.99,yes,locked 2006.286.02:44:19.91/vblo/03,649.99,yes,locked 2006.286.02:44:19.91/vblo/04,679.99,yes,locked 2006.286.02:44:19.91/vblo/05,709.99,yes,locked 2006.286.02:44:19.91/vblo/06,719.99,yes,locked 2006.286.02:44:19.91/vblo/07,734.99,yes,locked 2006.286.02:44:19.91/vblo/08,744.99,yes,locked 2006.286.02:44:20.06/vabw/8 2006.286.02:44:20.21/vbbw/8 2006.286.02:44:20.42/xfe/off,on,12.2 2006.286.02:44:20.79/ifatt/23,28,28,28 2006.286.02:44:21.07/fmout-gps/S +2.57E-07 2006.286.02:44:21.09:!2006.286.02:50:07 2006.286.02:50:07.00:data_valid=off 2006.286.02:50:07.00:"et 2006.286.02:50:07.00:!+3s 2006.286.02:50:10.01:"tape 2006.286.02:50:10.01:postob 2006.286.02:50:10.08/cable/+6.4991E-03 2006.286.02:50:10.08/wx/21.31,1015.6,79 2006.286.02:50:11.08/fmout-gps/S +2.60E-07 2006.286.02:50:11.08:scan_name=286-0253,jd0610,330 2006.286.02:50:11.08:source=oj287,085448.87,200630.6,2000.0,ccw 2006.286.02:50:12.13#flagr#flagr/antenna,new-source 2006.286.02:50:12.13:checkk5 2006.286.02:50:12.62/chk_autoobs//k5ts1/ autoobs is running! 2006.286.02:50:13.08/chk_autoobs//k5ts2/ autoobs is running! 2006.286.02:50:13.55/chk_autoobs//k5ts3/ autoobs is running! 2006.286.02:50:14.03/chk_autoobs//k5ts4/ autoobs is running! 2006.286.02:50:14.43/chk_obsdata//k5ts1/T2860244??a.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.286.02:50:14.80/chk_obsdata//k5ts2/T2860244??b.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.286.02:50:15.49/chk_obsdata//k5ts3/T2860244??c.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.286.02:50:15.88/chk_obsdata//k5ts4/T2860244??d.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.286.02:50:17.07/k5log//k5ts1_log_newline 2006.286.02:50:17.85/k5log//k5ts2_log_newline 2006.286.02:50:18.62/k5log//k5ts3_log_newline 2006.286.02:50:19.55/k5log//k5ts4_log_newline 2006.286.02:50:19.57/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.02:50:19.57:setupk4=1 2006.286.02:50:19.57$setupk4/echo=on 2006.286.02:50:19.57$setupk4/pcalon 2006.286.02:50:19.57$pcalon/"no phase cal control is implemented here 2006.286.02:50:19.57$setupk4/"tpicd=stop 2006.286.02:50:19.57$setupk4/"rec=synch_on 2006.286.02:50:19.57$setupk4/"rec_mode=128 2006.286.02:50:19.57$setupk4/!* 2006.286.02:50:19.57$setupk4/recpk4 2006.286.02:50:19.57$recpk4/recpatch= 2006.286.02:50:19.57$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.02:50:19.57$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.02:50:19.57$setupk4/vck44 2006.286.02:50:19.57$vck44/valo=1,524.99 2006.286.02:50:19.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.02:50:19.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.02:50:19.57#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:19.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:50:19.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:50:19.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:50:19.57#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:50:19.57#ibcon#first serial, iclass 15, count 0 2006.286.02:50:19.57#ibcon#enter sib2, iclass 15, count 0 2006.286.02:50:19.57#ibcon#flushed, iclass 15, count 0 2006.286.02:50:19.57#ibcon#about to write, iclass 15, count 0 2006.286.02:50:19.57#ibcon#wrote, iclass 15, count 0 2006.286.02:50:19.57#ibcon#about to read 3, iclass 15, count 0 2006.286.02:50:19.59#ibcon#read 3, iclass 15, count 0 2006.286.02:50:19.59#ibcon#about to read 4, iclass 15, count 0 2006.286.02:50:19.59#ibcon#read 4, iclass 15, count 0 2006.286.02:50:19.59#ibcon#about to read 5, iclass 15, count 0 2006.286.02:50:19.59#ibcon#read 5, iclass 15, count 0 2006.286.02:50:19.59#ibcon#about to read 6, iclass 15, count 0 2006.286.02:50:19.59#ibcon#read 6, iclass 15, count 0 2006.286.02:50:19.59#ibcon#end of sib2, iclass 15, count 0 2006.286.02:50:19.59#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:50:19.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:50:19.59#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.02:50:19.59#ibcon#*before write, iclass 15, count 0 2006.286.02:50:19.59#ibcon#enter sib2, iclass 15, count 0 2006.286.02:50:19.59#ibcon#flushed, iclass 15, count 0 2006.286.02:50:19.59#ibcon#about to write, iclass 15, count 0 2006.286.02:50:19.59#ibcon#wrote, iclass 15, count 0 2006.286.02:50:19.59#ibcon#about to read 3, iclass 15, count 0 2006.286.02:50:19.64#ibcon#read 3, iclass 15, count 0 2006.286.02:50:19.64#ibcon#about to read 4, iclass 15, count 0 2006.286.02:50:19.64#ibcon#read 4, iclass 15, count 0 2006.286.02:50:19.64#ibcon#about to read 5, iclass 15, count 0 2006.286.02:50:19.64#ibcon#read 5, iclass 15, count 0 2006.286.02:50:19.64#ibcon#about to read 6, iclass 15, count 0 2006.286.02:50:19.64#ibcon#read 6, iclass 15, count 0 2006.286.02:50:19.64#ibcon#end of sib2, iclass 15, count 0 2006.286.02:50:19.64#ibcon#*after write, iclass 15, count 0 2006.286.02:50:19.64#ibcon#*before return 0, iclass 15, count 0 2006.286.02:50:19.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:50:19.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:50:19.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:50:19.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:50:19.64$vck44/va=1,7 2006.286.02:50:19.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.02:50:19.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.02:50:19.64#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:19.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:50:19.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:50:19.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:50:19.64#ibcon#enter wrdev, iclass 17, count 2 2006.286.02:50:19.64#ibcon#first serial, iclass 17, count 2 2006.286.02:50:19.64#ibcon#enter sib2, iclass 17, count 2 2006.286.02:50:19.64#ibcon#flushed, iclass 17, count 2 2006.286.02:50:19.64#ibcon#about to write, iclass 17, count 2 2006.286.02:50:19.64#ibcon#wrote, iclass 17, count 2 2006.286.02:50:19.64#ibcon#about to read 3, iclass 17, count 2 2006.286.02:50:19.66#ibcon#read 3, iclass 17, count 2 2006.286.02:50:19.66#ibcon#about to read 4, iclass 17, count 2 2006.286.02:50:19.66#ibcon#read 4, iclass 17, count 2 2006.286.02:50:19.66#ibcon#about to read 5, iclass 17, count 2 2006.286.02:50:19.66#ibcon#read 5, iclass 17, count 2 2006.286.02:50:19.66#ibcon#about to read 6, iclass 17, count 2 2006.286.02:50:19.66#ibcon#read 6, iclass 17, count 2 2006.286.02:50:19.66#ibcon#end of sib2, iclass 17, count 2 2006.286.02:50:19.66#ibcon#*mode == 0, iclass 17, count 2 2006.286.02:50:19.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.02:50:19.66#ibcon#[25=AT01-07\r\n] 2006.286.02:50:19.66#ibcon#*before write, iclass 17, count 2 2006.286.02:50:19.66#ibcon#enter sib2, iclass 17, count 2 2006.286.02:50:19.66#ibcon#flushed, iclass 17, count 2 2006.286.02:50:19.66#ibcon#about to write, iclass 17, count 2 2006.286.02:50:19.66#ibcon#wrote, iclass 17, count 2 2006.286.02:50:19.66#ibcon#about to read 3, iclass 17, count 2 2006.286.02:50:19.69#ibcon#read 3, iclass 17, count 2 2006.286.02:50:19.69#ibcon#about to read 4, iclass 17, count 2 2006.286.02:50:19.69#ibcon#read 4, iclass 17, count 2 2006.286.02:50:19.69#ibcon#about to read 5, iclass 17, count 2 2006.286.02:50:19.69#ibcon#read 5, iclass 17, count 2 2006.286.02:50:19.69#ibcon#about to read 6, iclass 17, count 2 2006.286.02:50:19.69#ibcon#read 6, iclass 17, count 2 2006.286.02:50:19.69#ibcon#end of sib2, iclass 17, count 2 2006.286.02:50:19.69#ibcon#*after write, iclass 17, count 2 2006.286.02:50:19.69#ibcon#*before return 0, iclass 17, count 2 2006.286.02:50:19.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:50:19.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:50:19.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.02:50:19.69#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:19.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:50:19.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:50:19.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:50:19.81#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:50:19.81#ibcon#first serial, iclass 17, count 0 2006.286.02:50:19.81#ibcon#enter sib2, iclass 17, count 0 2006.286.02:50:19.81#ibcon#flushed, iclass 17, count 0 2006.286.02:50:19.81#ibcon#about to write, iclass 17, count 0 2006.286.02:50:19.81#ibcon#wrote, iclass 17, count 0 2006.286.02:50:19.81#ibcon#about to read 3, iclass 17, count 0 2006.286.02:50:19.83#ibcon#read 3, iclass 17, count 0 2006.286.02:50:19.83#ibcon#about to read 4, iclass 17, count 0 2006.286.02:50:19.83#ibcon#read 4, iclass 17, count 0 2006.286.02:50:19.83#ibcon#about to read 5, iclass 17, count 0 2006.286.02:50:19.83#ibcon#read 5, iclass 17, count 0 2006.286.02:50:19.83#ibcon#about to read 6, iclass 17, count 0 2006.286.02:50:19.83#ibcon#read 6, iclass 17, count 0 2006.286.02:50:19.83#ibcon#end of sib2, iclass 17, count 0 2006.286.02:50:19.83#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:50:19.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:50:19.83#ibcon#[25=USB\r\n] 2006.286.02:50:19.83#ibcon#*before write, iclass 17, count 0 2006.286.02:50:19.83#ibcon#enter sib2, iclass 17, count 0 2006.286.02:50:19.83#ibcon#flushed, iclass 17, count 0 2006.286.02:50:19.83#ibcon#about to write, iclass 17, count 0 2006.286.02:50:19.83#ibcon#wrote, iclass 17, count 0 2006.286.02:50:19.83#ibcon#about to read 3, iclass 17, count 0 2006.286.02:50:19.86#ibcon#read 3, iclass 17, count 0 2006.286.02:50:19.86#ibcon#about to read 4, iclass 17, count 0 2006.286.02:50:19.86#ibcon#read 4, iclass 17, count 0 2006.286.02:50:19.86#ibcon#about to read 5, iclass 17, count 0 2006.286.02:50:19.86#ibcon#read 5, iclass 17, count 0 2006.286.02:50:19.86#ibcon#about to read 6, iclass 17, count 0 2006.286.02:50:19.86#ibcon#read 6, iclass 17, count 0 2006.286.02:50:19.86#ibcon#end of sib2, iclass 17, count 0 2006.286.02:50:19.86#ibcon#*after write, iclass 17, count 0 2006.286.02:50:19.86#ibcon#*before return 0, iclass 17, count 0 2006.286.02:50:19.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:50:19.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:50:19.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:50:19.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:50:19.86$vck44/valo=2,534.99 2006.286.02:50:19.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.02:50:19.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.02:50:19.86#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:19.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:50:19.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:50:19.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:50:19.86#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:50:19.86#ibcon#first serial, iclass 19, count 0 2006.286.02:50:19.86#ibcon#enter sib2, iclass 19, count 0 2006.286.02:50:19.86#ibcon#flushed, iclass 19, count 0 2006.286.02:50:19.86#ibcon#about to write, iclass 19, count 0 2006.286.02:50:19.86#ibcon#wrote, iclass 19, count 0 2006.286.02:50:19.86#ibcon#about to read 3, iclass 19, count 0 2006.286.02:50:19.88#ibcon#read 3, iclass 19, count 0 2006.286.02:50:19.88#ibcon#about to read 4, iclass 19, count 0 2006.286.02:50:19.88#ibcon#read 4, iclass 19, count 0 2006.286.02:50:19.88#ibcon#about to read 5, iclass 19, count 0 2006.286.02:50:19.88#ibcon#read 5, iclass 19, count 0 2006.286.02:50:19.88#ibcon#about to read 6, iclass 19, count 0 2006.286.02:50:19.88#ibcon#read 6, iclass 19, count 0 2006.286.02:50:19.88#ibcon#end of sib2, iclass 19, count 0 2006.286.02:50:19.88#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:50:19.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:50:19.88#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.02:50:19.88#ibcon#*before write, iclass 19, count 0 2006.286.02:50:19.88#ibcon#enter sib2, iclass 19, count 0 2006.286.02:50:19.88#ibcon#flushed, iclass 19, count 0 2006.286.02:50:19.88#ibcon#about to write, iclass 19, count 0 2006.286.02:50:19.88#ibcon#wrote, iclass 19, count 0 2006.286.02:50:19.88#ibcon#about to read 3, iclass 19, count 0 2006.286.02:50:19.92#ibcon#read 3, iclass 19, count 0 2006.286.02:50:19.92#ibcon#about to read 4, iclass 19, count 0 2006.286.02:50:19.92#ibcon#read 4, iclass 19, count 0 2006.286.02:50:19.92#ibcon#about to read 5, iclass 19, count 0 2006.286.02:50:19.92#ibcon#read 5, iclass 19, count 0 2006.286.02:50:19.92#ibcon#about to read 6, iclass 19, count 0 2006.286.02:50:19.92#ibcon#read 6, iclass 19, count 0 2006.286.02:50:19.92#ibcon#end of sib2, iclass 19, count 0 2006.286.02:50:19.92#ibcon#*after write, iclass 19, count 0 2006.286.02:50:19.92#ibcon#*before return 0, iclass 19, count 0 2006.286.02:50:19.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:50:19.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:50:19.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:50:19.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:50:19.92$vck44/va=2,6 2006.286.02:50:19.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.02:50:19.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.02:50:19.92#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:19.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:50:19.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:50:19.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:50:19.98#ibcon#enter wrdev, iclass 21, count 2 2006.286.02:50:19.98#ibcon#first serial, iclass 21, count 2 2006.286.02:50:19.98#ibcon#enter sib2, iclass 21, count 2 2006.286.02:50:19.98#ibcon#flushed, iclass 21, count 2 2006.286.02:50:19.98#ibcon#about to write, iclass 21, count 2 2006.286.02:50:19.98#ibcon#wrote, iclass 21, count 2 2006.286.02:50:19.98#ibcon#about to read 3, iclass 21, count 2 2006.286.02:50:20.00#ibcon#read 3, iclass 21, count 2 2006.286.02:50:20.00#ibcon#about to read 4, iclass 21, count 2 2006.286.02:50:20.00#ibcon#read 4, iclass 21, count 2 2006.286.02:50:20.00#ibcon#about to read 5, iclass 21, count 2 2006.286.02:50:20.00#ibcon#read 5, iclass 21, count 2 2006.286.02:50:20.00#ibcon#about to read 6, iclass 21, count 2 2006.286.02:50:20.00#ibcon#read 6, iclass 21, count 2 2006.286.02:50:20.00#ibcon#end of sib2, iclass 21, count 2 2006.286.02:50:20.00#ibcon#*mode == 0, iclass 21, count 2 2006.286.02:50:20.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.02:50:20.00#ibcon#[25=AT02-06\r\n] 2006.286.02:50:20.00#ibcon#*before write, iclass 21, count 2 2006.286.02:50:20.00#ibcon#enter sib2, iclass 21, count 2 2006.286.02:50:20.00#ibcon#flushed, iclass 21, count 2 2006.286.02:50:20.00#ibcon#about to write, iclass 21, count 2 2006.286.02:50:20.00#ibcon#wrote, iclass 21, count 2 2006.286.02:50:20.00#ibcon#about to read 3, iclass 21, count 2 2006.286.02:50:20.03#ibcon#read 3, iclass 21, count 2 2006.286.02:50:20.03#ibcon#about to read 4, iclass 21, count 2 2006.286.02:50:20.03#ibcon#read 4, iclass 21, count 2 2006.286.02:50:20.03#ibcon#about to read 5, iclass 21, count 2 2006.286.02:50:20.03#ibcon#read 5, iclass 21, count 2 2006.286.02:50:20.03#ibcon#about to read 6, iclass 21, count 2 2006.286.02:50:20.03#ibcon#read 6, iclass 21, count 2 2006.286.02:50:20.03#ibcon#end of sib2, iclass 21, count 2 2006.286.02:50:20.03#ibcon#*after write, iclass 21, count 2 2006.286.02:50:20.03#ibcon#*before return 0, iclass 21, count 2 2006.286.02:50:20.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:50:20.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:50:20.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.02:50:20.03#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:20.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:50:20.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:50:20.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:50:20.15#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:50:20.15#ibcon#first serial, iclass 21, count 0 2006.286.02:50:20.15#ibcon#enter sib2, iclass 21, count 0 2006.286.02:50:20.15#ibcon#flushed, iclass 21, count 0 2006.286.02:50:20.15#ibcon#about to write, iclass 21, count 0 2006.286.02:50:20.15#ibcon#wrote, iclass 21, count 0 2006.286.02:50:20.15#ibcon#about to read 3, iclass 21, count 0 2006.286.02:50:20.17#ibcon#read 3, iclass 21, count 0 2006.286.02:50:20.17#ibcon#about to read 4, iclass 21, count 0 2006.286.02:50:20.17#ibcon#read 4, iclass 21, count 0 2006.286.02:50:20.17#ibcon#about to read 5, iclass 21, count 0 2006.286.02:50:20.17#ibcon#read 5, iclass 21, count 0 2006.286.02:50:20.17#ibcon#about to read 6, iclass 21, count 0 2006.286.02:50:20.17#ibcon#read 6, iclass 21, count 0 2006.286.02:50:20.17#ibcon#end of sib2, iclass 21, count 0 2006.286.02:50:20.17#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:50:20.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:50:20.17#ibcon#[25=USB\r\n] 2006.286.02:50:20.17#ibcon#*before write, iclass 21, count 0 2006.286.02:50:20.17#ibcon#enter sib2, iclass 21, count 0 2006.286.02:50:20.17#ibcon#flushed, iclass 21, count 0 2006.286.02:50:20.17#ibcon#about to write, iclass 21, count 0 2006.286.02:50:20.17#ibcon#wrote, iclass 21, count 0 2006.286.02:50:20.17#ibcon#about to read 3, iclass 21, count 0 2006.286.02:50:20.20#ibcon#read 3, iclass 21, count 0 2006.286.02:50:20.20#ibcon#about to read 4, iclass 21, count 0 2006.286.02:50:20.20#ibcon#read 4, iclass 21, count 0 2006.286.02:50:20.20#ibcon#about to read 5, iclass 21, count 0 2006.286.02:50:20.20#ibcon#read 5, iclass 21, count 0 2006.286.02:50:20.20#ibcon#about to read 6, iclass 21, count 0 2006.286.02:50:20.20#ibcon#read 6, iclass 21, count 0 2006.286.02:50:20.20#ibcon#end of sib2, iclass 21, count 0 2006.286.02:50:20.20#ibcon#*after write, iclass 21, count 0 2006.286.02:50:20.20#ibcon#*before return 0, iclass 21, count 0 2006.286.02:50:20.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:50:20.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:50:20.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:50:20.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:50:20.20$vck44/valo=3,564.99 2006.286.02:50:20.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.02:50:20.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.02:50:20.20#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:20.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:50:20.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:50:20.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:50:20.20#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:50:20.20#ibcon#first serial, iclass 23, count 0 2006.286.02:50:20.20#ibcon#enter sib2, iclass 23, count 0 2006.286.02:50:20.20#ibcon#flushed, iclass 23, count 0 2006.286.02:50:20.20#ibcon#about to write, iclass 23, count 0 2006.286.02:50:20.20#ibcon#wrote, iclass 23, count 0 2006.286.02:50:20.20#ibcon#about to read 3, iclass 23, count 0 2006.286.02:50:20.22#ibcon#read 3, iclass 23, count 0 2006.286.02:50:20.22#ibcon#about to read 4, iclass 23, count 0 2006.286.02:50:20.22#ibcon#read 4, iclass 23, count 0 2006.286.02:50:20.22#ibcon#about to read 5, iclass 23, count 0 2006.286.02:50:20.22#ibcon#read 5, iclass 23, count 0 2006.286.02:50:20.22#ibcon#about to read 6, iclass 23, count 0 2006.286.02:50:20.22#ibcon#read 6, iclass 23, count 0 2006.286.02:50:20.22#ibcon#end of sib2, iclass 23, count 0 2006.286.02:50:20.22#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:50:20.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:50:20.22#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.02:50:20.22#ibcon#*before write, iclass 23, count 0 2006.286.02:50:20.22#ibcon#enter sib2, iclass 23, count 0 2006.286.02:50:20.22#ibcon#flushed, iclass 23, count 0 2006.286.02:50:20.22#ibcon#about to write, iclass 23, count 0 2006.286.02:50:20.22#ibcon#wrote, iclass 23, count 0 2006.286.02:50:20.22#ibcon#about to read 3, iclass 23, count 0 2006.286.02:50:20.25#abcon#<5=/04 3.0 5.9 21.31 791015.6\r\n> 2006.286.02:50:20.26#ibcon#read 3, iclass 23, count 0 2006.286.02:50:20.26#ibcon#about to read 4, iclass 23, count 0 2006.286.02:50:20.26#ibcon#read 4, iclass 23, count 0 2006.286.02:50:20.26#ibcon#about to read 5, iclass 23, count 0 2006.286.02:50:20.26#ibcon#read 5, iclass 23, count 0 2006.286.02:50:20.26#ibcon#about to read 6, iclass 23, count 0 2006.286.02:50:20.26#ibcon#read 6, iclass 23, count 0 2006.286.02:50:20.26#ibcon#end of sib2, iclass 23, count 0 2006.286.02:50:20.26#ibcon#*after write, iclass 23, count 0 2006.286.02:50:20.26#ibcon#*before return 0, iclass 23, count 0 2006.286.02:50:20.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:50:20.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:50:20.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:50:20.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:50:20.26$vck44/va=3,7 2006.286.02:50:20.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.02:50:20.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.02:50:20.26#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:20.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:50:20.27#abcon#{5=INTERFACE CLEAR} 2006.286.02:50:20.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:50:20.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:50:20.32#ibcon#enter wrdev, iclass 28, count 2 2006.286.02:50:20.32#ibcon#first serial, iclass 28, count 2 2006.286.02:50:20.32#ibcon#enter sib2, iclass 28, count 2 2006.286.02:50:20.32#ibcon#flushed, iclass 28, count 2 2006.286.02:50:20.32#ibcon#about to write, iclass 28, count 2 2006.286.02:50:20.32#ibcon#wrote, iclass 28, count 2 2006.286.02:50:20.32#ibcon#about to read 3, iclass 28, count 2 2006.286.02:50:20.33#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:50:20.34#ibcon#read 3, iclass 28, count 2 2006.286.02:50:20.34#ibcon#about to read 4, iclass 28, count 2 2006.286.02:50:20.34#ibcon#read 4, iclass 28, count 2 2006.286.02:50:20.34#ibcon#about to read 5, iclass 28, count 2 2006.286.02:50:20.34#ibcon#read 5, iclass 28, count 2 2006.286.02:50:20.34#ibcon#about to read 6, iclass 28, count 2 2006.286.02:50:20.34#ibcon#read 6, iclass 28, count 2 2006.286.02:50:20.34#ibcon#end of sib2, iclass 28, count 2 2006.286.02:50:20.34#ibcon#*mode == 0, iclass 28, count 2 2006.286.02:50:20.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.02:50:20.34#ibcon#[25=AT03-07\r\n] 2006.286.02:50:20.34#ibcon#*before write, iclass 28, count 2 2006.286.02:50:20.34#ibcon#enter sib2, iclass 28, count 2 2006.286.02:50:20.34#ibcon#flushed, iclass 28, count 2 2006.286.02:50:20.34#ibcon#about to write, iclass 28, count 2 2006.286.02:50:20.34#ibcon#wrote, iclass 28, count 2 2006.286.02:50:20.34#ibcon#about to read 3, iclass 28, count 2 2006.286.02:50:20.37#ibcon#read 3, iclass 28, count 2 2006.286.02:50:20.93#ibcon#about to read 4, iclass 28, count 2 2006.286.02:50:20.93#ibcon#read 4, iclass 28, count 2 2006.286.02:50:20.93#ibcon#about to read 5, iclass 28, count 2 2006.286.02:50:20.93#ibcon#read 5, iclass 28, count 2 2006.286.02:50:20.93#ibcon#about to read 6, iclass 28, count 2 2006.286.02:50:20.93#ibcon#read 6, iclass 28, count 2 2006.286.02:50:20.93#ibcon#end of sib2, iclass 28, count 2 2006.286.02:50:20.93#ibcon#*after write, iclass 28, count 2 2006.286.02:50:20.93#ibcon#*before return 0, iclass 28, count 2 2006.286.02:50:20.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:50:20.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.02:50:20.93#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.02:50:20.93#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:20.93#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:50:21.04#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:50:21.04#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:50:21.04#ibcon#enter wrdev, iclass 28, count 0 2006.286.02:50:21.04#ibcon#first serial, iclass 28, count 0 2006.286.02:50:21.04#ibcon#enter sib2, iclass 28, count 0 2006.286.02:50:21.04#ibcon#flushed, iclass 28, count 0 2006.286.02:50:21.04#ibcon#about to write, iclass 28, count 0 2006.286.02:50:21.04#ibcon#wrote, iclass 28, count 0 2006.286.02:50:21.04#ibcon#about to read 3, iclass 28, count 0 2006.286.02:50:21.06#ibcon#read 3, iclass 28, count 0 2006.286.02:50:21.06#ibcon#about to read 4, iclass 28, count 0 2006.286.02:50:21.06#ibcon#read 4, iclass 28, count 0 2006.286.02:50:21.06#ibcon#about to read 5, iclass 28, count 0 2006.286.02:50:21.06#ibcon#read 5, iclass 28, count 0 2006.286.02:50:21.06#ibcon#about to read 6, iclass 28, count 0 2006.286.02:50:21.06#ibcon#read 6, iclass 28, count 0 2006.286.02:50:21.06#ibcon#end of sib2, iclass 28, count 0 2006.286.02:50:21.06#ibcon#*mode == 0, iclass 28, count 0 2006.286.02:50:21.06#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.02:50:21.06#ibcon#[25=USB\r\n] 2006.286.02:50:21.06#ibcon#*before write, iclass 28, count 0 2006.286.02:50:21.06#ibcon#enter sib2, iclass 28, count 0 2006.286.02:50:21.06#ibcon#flushed, iclass 28, count 0 2006.286.02:50:21.06#ibcon#about to write, iclass 28, count 0 2006.286.02:50:21.06#ibcon#wrote, iclass 28, count 0 2006.286.02:50:21.06#ibcon#about to read 3, iclass 28, count 0 2006.286.02:50:21.09#ibcon#read 3, iclass 28, count 0 2006.286.02:50:21.09#ibcon#about to read 4, iclass 28, count 0 2006.286.02:50:21.09#ibcon#read 4, iclass 28, count 0 2006.286.02:50:21.09#ibcon#about to read 5, iclass 28, count 0 2006.286.02:50:21.09#ibcon#read 5, iclass 28, count 0 2006.286.02:50:21.09#ibcon#about to read 6, iclass 28, count 0 2006.286.02:50:21.09#ibcon#read 6, iclass 28, count 0 2006.286.02:50:21.09#ibcon#end of sib2, iclass 28, count 0 2006.286.02:50:21.09#ibcon#*after write, iclass 28, count 0 2006.286.02:50:21.09#ibcon#*before return 0, iclass 28, count 0 2006.286.02:50:21.09#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:50:21.09#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.02:50:21.09#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.02:50:21.09#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.02:50:21.09$vck44/valo=4,624.99 2006.286.02:50:21.09#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.02:50:21.09#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.02:50:21.09#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:21.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:50:21.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:50:21.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:50:21.09#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:50:21.09#ibcon#first serial, iclass 31, count 0 2006.286.02:50:21.09#ibcon#enter sib2, iclass 31, count 0 2006.286.02:50:21.09#ibcon#flushed, iclass 31, count 0 2006.286.02:50:21.09#ibcon#about to write, iclass 31, count 0 2006.286.02:50:21.09#ibcon#wrote, iclass 31, count 0 2006.286.02:50:21.09#ibcon#about to read 3, iclass 31, count 0 2006.286.02:50:21.11#ibcon#read 3, iclass 31, count 0 2006.286.02:50:21.11#ibcon#about to read 4, iclass 31, count 0 2006.286.02:50:21.11#ibcon#read 4, iclass 31, count 0 2006.286.02:50:21.11#ibcon#about to read 5, iclass 31, count 0 2006.286.02:50:21.11#ibcon#read 5, iclass 31, count 0 2006.286.02:50:21.11#ibcon#about to read 6, iclass 31, count 0 2006.286.02:50:21.11#ibcon#read 6, iclass 31, count 0 2006.286.02:50:21.11#ibcon#end of sib2, iclass 31, count 0 2006.286.02:50:21.11#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:50:21.11#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:50:21.11#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.02:50:21.11#ibcon#*before write, iclass 31, count 0 2006.286.02:50:21.11#ibcon#enter sib2, iclass 31, count 0 2006.286.02:50:21.11#ibcon#flushed, iclass 31, count 0 2006.286.02:50:21.11#ibcon#about to write, iclass 31, count 0 2006.286.02:50:21.11#ibcon#wrote, iclass 31, count 0 2006.286.02:50:21.11#ibcon#about to read 3, iclass 31, count 0 2006.286.02:50:21.15#ibcon#read 3, iclass 31, count 0 2006.286.02:50:21.15#ibcon#about to read 4, iclass 31, count 0 2006.286.02:50:21.15#ibcon#read 4, iclass 31, count 0 2006.286.02:50:21.15#ibcon#about to read 5, iclass 31, count 0 2006.286.02:50:21.15#ibcon#read 5, iclass 31, count 0 2006.286.02:50:21.15#ibcon#about to read 6, iclass 31, count 0 2006.286.02:50:21.15#ibcon#read 6, iclass 31, count 0 2006.286.02:50:21.15#ibcon#end of sib2, iclass 31, count 0 2006.286.02:50:21.15#ibcon#*after write, iclass 31, count 0 2006.286.02:50:21.15#ibcon#*before return 0, iclass 31, count 0 2006.286.02:50:21.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:50:21.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:50:21.15#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:50:21.15#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:50:21.15$vck44/va=4,6 2006.286.02:50:21.15#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.02:50:21.15#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.02:50:21.15#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:21.15#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:50:21.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:50:21.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:50:21.21#ibcon#enter wrdev, iclass 33, count 2 2006.286.02:50:21.21#ibcon#first serial, iclass 33, count 2 2006.286.02:50:21.21#ibcon#enter sib2, iclass 33, count 2 2006.286.02:50:21.21#ibcon#flushed, iclass 33, count 2 2006.286.02:50:21.21#ibcon#about to write, iclass 33, count 2 2006.286.02:50:21.21#ibcon#wrote, iclass 33, count 2 2006.286.02:50:21.21#ibcon#about to read 3, iclass 33, count 2 2006.286.02:50:21.23#ibcon#read 3, iclass 33, count 2 2006.286.02:50:21.54#ibcon#about to read 4, iclass 33, count 2 2006.286.02:50:21.54#ibcon#read 4, iclass 33, count 2 2006.286.02:50:21.54#ibcon#about to read 5, iclass 33, count 2 2006.286.02:50:21.54#ibcon#read 5, iclass 33, count 2 2006.286.02:50:21.54#ibcon#about to read 6, iclass 33, count 2 2006.286.02:50:21.54#ibcon#read 6, iclass 33, count 2 2006.286.02:50:21.54#ibcon#end of sib2, iclass 33, count 2 2006.286.02:50:21.54#ibcon#*mode == 0, iclass 33, count 2 2006.286.02:50:21.54#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.02:50:21.54#ibcon#[25=AT04-06\r\n] 2006.286.02:50:21.54#ibcon#*before write, iclass 33, count 2 2006.286.02:50:21.54#ibcon#enter sib2, iclass 33, count 2 2006.286.02:50:21.54#ibcon#flushed, iclass 33, count 2 2006.286.02:50:21.54#ibcon#about to write, iclass 33, count 2 2006.286.02:50:21.54#ibcon#wrote, iclass 33, count 2 2006.286.02:50:21.54#ibcon#about to read 3, iclass 33, count 2 2006.286.02:50:21.57#ibcon#read 3, iclass 33, count 2 2006.286.02:50:21.57#ibcon#about to read 4, iclass 33, count 2 2006.286.02:50:21.57#ibcon#read 4, iclass 33, count 2 2006.286.02:50:21.57#ibcon#about to read 5, iclass 33, count 2 2006.286.02:50:21.57#ibcon#read 5, iclass 33, count 2 2006.286.02:50:21.57#ibcon#about to read 6, iclass 33, count 2 2006.286.02:50:21.57#ibcon#read 6, iclass 33, count 2 2006.286.02:50:21.57#ibcon#end of sib2, iclass 33, count 2 2006.286.02:50:21.57#ibcon#*after write, iclass 33, count 2 2006.286.02:50:21.57#ibcon#*before return 0, iclass 33, count 2 2006.286.02:50:21.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:50:21.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:50:21.57#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.02:50:21.57#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:21.57#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:50:21.69#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:50:21.69#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:50:21.69#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:50:21.69#ibcon#first serial, iclass 33, count 0 2006.286.02:50:21.69#ibcon#enter sib2, iclass 33, count 0 2006.286.02:50:21.69#ibcon#flushed, iclass 33, count 0 2006.286.02:50:21.69#ibcon#about to write, iclass 33, count 0 2006.286.02:50:21.69#ibcon#wrote, iclass 33, count 0 2006.286.02:50:21.69#ibcon#about to read 3, iclass 33, count 0 2006.286.02:50:21.71#ibcon#read 3, iclass 33, count 0 2006.286.02:50:21.71#ibcon#about to read 4, iclass 33, count 0 2006.286.02:50:21.71#ibcon#read 4, iclass 33, count 0 2006.286.02:50:21.71#ibcon#about to read 5, iclass 33, count 0 2006.286.02:50:21.71#ibcon#read 5, iclass 33, count 0 2006.286.02:50:21.71#ibcon#about to read 6, iclass 33, count 0 2006.286.02:50:21.71#ibcon#read 6, iclass 33, count 0 2006.286.02:50:21.71#ibcon#end of sib2, iclass 33, count 0 2006.286.02:50:21.71#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:50:21.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:50:21.71#ibcon#[25=USB\r\n] 2006.286.02:50:21.71#ibcon#*before write, iclass 33, count 0 2006.286.02:50:21.71#ibcon#enter sib2, iclass 33, count 0 2006.286.02:50:21.71#ibcon#flushed, iclass 33, count 0 2006.286.02:50:21.71#ibcon#about to write, iclass 33, count 0 2006.286.02:50:21.71#ibcon#wrote, iclass 33, count 0 2006.286.02:50:21.71#ibcon#about to read 3, iclass 33, count 0 2006.286.02:50:21.74#ibcon#read 3, iclass 33, count 0 2006.286.02:50:21.74#ibcon#about to read 4, iclass 33, count 0 2006.286.02:50:21.74#ibcon#read 4, iclass 33, count 0 2006.286.02:50:21.74#ibcon#about to read 5, iclass 33, count 0 2006.286.02:50:21.74#ibcon#read 5, iclass 33, count 0 2006.286.02:50:21.74#ibcon#about to read 6, iclass 33, count 0 2006.286.02:50:21.74#ibcon#read 6, iclass 33, count 0 2006.286.02:50:21.74#ibcon#end of sib2, iclass 33, count 0 2006.286.02:50:21.74#ibcon#*after write, iclass 33, count 0 2006.286.02:50:21.74#ibcon#*before return 0, iclass 33, count 0 2006.286.02:50:21.74#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:50:21.74#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:50:21.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:50:21.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:50:21.74$vck44/valo=5,734.99 2006.286.02:50:21.74#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.02:50:21.74#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.02:50:21.74#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:21.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:50:21.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:50:21.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:50:21.74#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:50:21.74#ibcon#first serial, iclass 35, count 0 2006.286.02:50:21.74#ibcon#enter sib2, iclass 35, count 0 2006.286.02:50:21.74#ibcon#flushed, iclass 35, count 0 2006.286.02:50:21.74#ibcon#about to write, iclass 35, count 0 2006.286.02:50:21.74#ibcon#wrote, iclass 35, count 0 2006.286.02:50:21.74#ibcon#about to read 3, iclass 35, count 0 2006.286.02:50:21.76#ibcon#read 3, iclass 35, count 0 2006.286.02:50:21.94#ibcon#about to read 4, iclass 35, count 0 2006.286.02:50:21.94#ibcon#read 4, iclass 35, count 0 2006.286.02:50:21.94#ibcon#about to read 5, iclass 35, count 0 2006.286.02:50:21.94#ibcon#read 5, iclass 35, count 0 2006.286.02:50:21.94#ibcon#about to read 6, iclass 35, count 0 2006.286.02:50:21.94#ibcon#read 6, iclass 35, count 0 2006.286.02:50:21.94#ibcon#end of sib2, iclass 35, count 0 2006.286.02:50:21.94#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:50:21.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:50:21.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.02:50:21.94#ibcon#*before write, iclass 35, count 0 2006.286.02:50:21.94#ibcon#enter sib2, iclass 35, count 0 2006.286.02:50:21.94#ibcon#flushed, iclass 35, count 0 2006.286.02:50:21.94#ibcon#about to write, iclass 35, count 0 2006.286.02:50:21.94#ibcon#wrote, iclass 35, count 0 2006.286.02:50:21.94#ibcon#about to read 3, iclass 35, count 0 2006.286.02:50:21.98#ibcon#read 3, iclass 35, count 0 2006.286.02:50:21.98#ibcon#about to read 4, iclass 35, count 0 2006.286.02:50:21.98#ibcon#read 4, iclass 35, count 0 2006.286.02:50:21.98#ibcon#about to read 5, iclass 35, count 0 2006.286.02:50:21.98#ibcon#read 5, iclass 35, count 0 2006.286.02:50:21.98#ibcon#about to read 6, iclass 35, count 0 2006.286.02:50:21.98#ibcon#read 6, iclass 35, count 0 2006.286.02:50:21.98#ibcon#end of sib2, iclass 35, count 0 2006.286.02:50:21.98#ibcon#*after write, iclass 35, count 0 2006.286.02:50:21.98#ibcon#*before return 0, iclass 35, count 0 2006.286.02:50:21.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:50:21.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:50:21.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:50:21.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:50:21.98$vck44/va=5,3 2006.286.02:50:21.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.02:50:21.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.02:50:21.98#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:21.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:50:21.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:50:21.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:50:21.98#ibcon#enter wrdev, iclass 37, count 2 2006.286.02:50:21.98#ibcon#first serial, iclass 37, count 2 2006.286.02:50:21.98#ibcon#enter sib2, iclass 37, count 2 2006.286.02:50:21.98#ibcon#flushed, iclass 37, count 2 2006.286.02:50:21.98#ibcon#about to write, iclass 37, count 2 2006.286.02:50:21.98#ibcon#wrote, iclass 37, count 2 2006.286.02:50:21.98#ibcon#about to read 3, iclass 37, count 2 2006.286.02:50:22.00#ibcon#read 3, iclass 37, count 2 2006.286.02:50:22.00#ibcon#about to read 4, iclass 37, count 2 2006.286.02:50:22.00#ibcon#read 4, iclass 37, count 2 2006.286.02:50:22.00#ibcon#about to read 5, iclass 37, count 2 2006.286.02:50:22.00#ibcon#read 5, iclass 37, count 2 2006.286.02:50:22.00#ibcon#about to read 6, iclass 37, count 2 2006.286.02:50:22.00#ibcon#read 6, iclass 37, count 2 2006.286.02:50:22.00#ibcon#end of sib2, iclass 37, count 2 2006.286.02:50:22.00#ibcon#*mode == 0, iclass 37, count 2 2006.286.02:50:22.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.02:50:22.00#ibcon#[25=AT05-03\r\n] 2006.286.02:50:22.00#ibcon#*before write, iclass 37, count 2 2006.286.02:50:22.00#ibcon#enter sib2, iclass 37, count 2 2006.286.02:50:22.00#ibcon#flushed, iclass 37, count 2 2006.286.02:50:22.00#ibcon#about to write, iclass 37, count 2 2006.286.02:50:22.00#ibcon#wrote, iclass 37, count 2 2006.286.02:50:22.00#ibcon#about to read 3, iclass 37, count 2 2006.286.02:50:22.03#ibcon#read 3, iclass 37, count 2 2006.286.02:50:22.03#ibcon#about to read 4, iclass 37, count 2 2006.286.02:50:22.03#ibcon#read 4, iclass 37, count 2 2006.286.02:50:22.03#ibcon#about to read 5, iclass 37, count 2 2006.286.02:50:22.03#ibcon#read 5, iclass 37, count 2 2006.286.02:50:22.03#ibcon#about to read 6, iclass 37, count 2 2006.286.02:50:22.03#ibcon#read 6, iclass 37, count 2 2006.286.02:50:22.03#ibcon#end of sib2, iclass 37, count 2 2006.286.02:50:22.03#ibcon#*after write, iclass 37, count 2 2006.286.02:50:22.03#ibcon#*before return 0, iclass 37, count 2 2006.286.02:50:22.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:50:22.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:50:22.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.02:50:22.03#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:22.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:50:22.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:50:22.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:50:22.15#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:50:22.15#ibcon#first serial, iclass 37, count 0 2006.286.02:50:22.15#ibcon#enter sib2, iclass 37, count 0 2006.286.02:50:22.15#ibcon#flushed, iclass 37, count 0 2006.286.02:50:22.15#ibcon#about to write, iclass 37, count 0 2006.286.02:50:22.15#ibcon#wrote, iclass 37, count 0 2006.286.02:50:22.15#ibcon#about to read 3, iclass 37, count 0 2006.286.02:50:22.17#ibcon#read 3, iclass 37, count 0 2006.286.02:50:22.17#ibcon#about to read 4, iclass 37, count 0 2006.286.02:50:22.17#ibcon#read 4, iclass 37, count 0 2006.286.02:50:22.17#ibcon#about to read 5, iclass 37, count 0 2006.286.02:50:22.17#ibcon#read 5, iclass 37, count 0 2006.286.02:50:22.17#ibcon#about to read 6, iclass 37, count 0 2006.286.02:50:22.17#ibcon#read 6, iclass 37, count 0 2006.286.02:50:22.17#ibcon#end of sib2, iclass 37, count 0 2006.286.02:50:22.17#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:50:22.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:50:22.17#ibcon#[25=USB\r\n] 2006.286.02:50:22.17#ibcon#*before write, iclass 37, count 0 2006.286.02:50:22.17#ibcon#enter sib2, iclass 37, count 0 2006.286.02:50:22.17#ibcon#flushed, iclass 37, count 0 2006.286.02:50:22.17#ibcon#about to write, iclass 37, count 0 2006.286.02:50:22.17#ibcon#wrote, iclass 37, count 0 2006.286.02:50:22.17#ibcon#about to read 3, iclass 37, count 0 2006.286.02:50:22.20#ibcon#read 3, iclass 37, count 0 2006.286.02:50:22.20#ibcon#about to read 4, iclass 37, count 0 2006.286.02:50:22.20#ibcon#read 4, iclass 37, count 0 2006.286.02:50:22.20#ibcon#about to read 5, iclass 37, count 0 2006.286.02:50:22.20#ibcon#read 5, iclass 37, count 0 2006.286.02:50:22.20#ibcon#about to read 6, iclass 37, count 0 2006.286.02:50:22.20#ibcon#read 6, iclass 37, count 0 2006.286.02:50:22.20#ibcon#end of sib2, iclass 37, count 0 2006.286.02:50:22.20#ibcon#*after write, iclass 37, count 0 2006.286.02:50:22.20#ibcon#*before return 0, iclass 37, count 0 2006.286.02:50:22.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:50:22.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:50:22.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:50:22.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:50:22.20$vck44/valo=6,814.99 2006.286.02:50:22.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.02:50:22.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.02:50:22.20#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:22.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:50:22.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:50:22.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:50:22.20#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:50:22.20#ibcon#first serial, iclass 39, count 0 2006.286.02:50:22.20#ibcon#enter sib2, iclass 39, count 0 2006.286.02:50:22.20#ibcon#flushed, iclass 39, count 0 2006.286.02:50:22.20#ibcon#about to write, iclass 39, count 0 2006.286.02:50:22.20#ibcon#wrote, iclass 39, count 0 2006.286.02:50:22.20#ibcon#about to read 3, iclass 39, count 0 2006.286.02:50:22.22#ibcon#read 3, iclass 39, count 0 2006.286.02:50:22.22#ibcon#about to read 4, iclass 39, count 0 2006.286.02:50:22.22#ibcon#read 4, iclass 39, count 0 2006.286.02:50:22.22#ibcon#about to read 5, iclass 39, count 0 2006.286.02:50:22.22#ibcon#read 5, iclass 39, count 0 2006.286.02:50:22.22#ibcon#about to read 6, iclass 39, count 0 2006.286.02:50:22.22#ibcon#read 6, iclass 39, count 0 2006.286.02:50:22.22#ibcon#end of sib2, iclass 39, count 0 2006.286.02:50:22.22#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:50:22.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:50:22.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.02:50:22.22#ibcon#*before write, iclass 39, count 0 2006.286.02:50:22.22#ibcon#enter sib2, iclass 39, count 0 2006.286.02:50:22.22#ibcon#flushed, iclass 39, count 0 2006.286.02:50:22.22#ibcon#about to write, iclass 39, count 0 2006.286.02:50:22.22#ibcon#wrote, iclass 39, count 0 2006.286.02:50:22.22#ibcon#about to read 3, iclass 39, count 0 2006.286.02:50:22.26#ibcon#read 3, iclass 39, count 0 2006.286.02:50:22.26#ibcon#about to read 4, iclass 39, count 0 2006.286.02:50:22.26#ibcon#read 4, iclass 39, count 0 2006.286.02:50:22.26#ibcon#about to read 5, iclass 39, count 0 2006.286.02:50:22.26#ibcon#read 5, iclass 39, count 0 2006.286.02:50:22.26#ibcon#about to read 6, iclass 39, count 0 2006.286.02:50:22.26#ibcon#read 6, iclass 39, count 0 2006.286.02:50:22.26#ibcon#end of sib2, iclass 39, count 0 2006.286.02:50:22.26#ibcon#*after write, iclass 39, count 0 2006.286.02:50:22.26#ibcon#*before return 0, iclass 39, count 0 2006.286.02:50:22.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:50:22.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:50:22.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:50:22.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:50:22.26$vck44/va=6,4 2006.286.02:50:22.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.02:50:22.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.02:50:22.26#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:22.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:50:22.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:50:22.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:50:22.32#ibcon#enter wrdev, iclass 3, count 2 2006.286.02:50:22.32#ibcon#first serial, iclass 3, count 2 2006.286.02:50:22.32#ibcon#enter sib2, iclass 3, count 2 2006.286.02:50:22.32#ibcon#flushed, iclass 3, count 2 2006.286.02:50:22.32#ibcon#about to write, iclass 3, count 2 2006.286.02:50:22.32#ibcon#wrote, iclass 3, count 2 2006.286.02:50:22.32#ibcon#about to read 3, iclass 3, count 2 2006.286.02:50:22.34#ibcon#read 3, iclass 3, count 2 2006.286.02:50:22.34#ibcon#about to read 4, iclass 3, count 2 2006.286.02:50:22.34#ibcon#read 4, iclass 3, count 2 2006.286.02:50:22.34#ibcon#about to read 5, iclass 3, count 2 2006.286.02:50:22.34#ibcon#read 5, iclass 3, count 2 2006.286.02:50:22.34#ibcon#about to read 6, iclass 3, count 2 2006.286.02:50:22.34#ibcon#read 6, iclass 3, count 2 2006.286.02:50:22.34#ibcon#end of sib2, iclass 3, count 2 2006.286.02:50:22.34#ibcon#*mode == 0, iclass 3, count 2 2006.286.02:50:22.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.02:50:22.34#ibcon#[25=AT06-04\r\n] 2006.286.02:50:22.34#ibcon#*before write, iclass 3, count 2 2006.286.02:50:22.34#ibcon#enter sib2, iclass 3, count 2 2006.286.02:50:22.34#ibcon#flushed, iclass 3, count 2 2006.286.02:50:22.34#ibcon#about to write, iclass 3, count 2 2006.286.02:50:22.34#ibcon#wrote, iclass 3, count 2 2006.286.02:50:22.34#ibcon#about to read 3, iclass 3, count 2 2006.286.02:50:22.37#ibcon#read 3, iclass 3, count 2 2006.286.02:50:22.37#ibcon#about to read 4, iclass 3, count 2 2006.286.02:50:22.37#ibcon#read 4, iclass 3, count 2 2006.286.02:50:22.37#ibcon#about to read 5, iclass 3, count 2 2006.286.02:50:22.37#ibcon#read 5, iclass 3, count 2 2006.286.02:50:22.37#ibcon#about to read 6, iclass 3, count 2 2006.286.02:50:22.37#ibcon#read 6, iclass 3, count 2 2006.286.02:50:22.37#ibcon#end of sib2, iclass 3, count 2 2006.286.02:50:22.37#ibcon#*after write, iclass 3, count 2 2006.286.02:50:22.37#ibcon#*before return 0, iclass 3, count 2 2006.286.02:50:22.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:50:22.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:50:22.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.02:50:22.37#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:22.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:50:22.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:50:22.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:50:22.49#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:50:22.49#ibcon#first serial, iclass 3, count 0 2006.286.02:50:22.49#ibcon#enter sib2, iclass 3, count 0 2006.286.02:50:22.49#ibcon#flushed, iclass 3, count 0 2006.286.02:50:22.49#ibcon#about to write, iclass 3, count 0 2006.286.02:50:22.49#ibcon#wrote, iclass 3, count 0 2006.286.02:50:22.49#ibcon#about to read 3, iclass 3, count 0 2006.286.02:50:22.51#ibcon#read 3, iclass 3, count 0 2006.286.02:50:22.51#ibcon#about to read 4, iclass 3, count 0 2006.286.02:50:22.51#ibcon#read 4, iclass 3, count 0 2006.286.02:50:22.51#ibcon#about to read 5, iclass 3, count 0 2006.286.02:50:22.51#ibcon#read 5, iclass 3, count 0 2006.286.02:50:22.51#ibcon#about to read 6, iclass 3, count 0 2006.286.02:50:22.51#ibcon#read 6, iclass 3, count 0 2006.286.02:50:22.51#ibcon#end of sib2, iclass 3, count 0 2006.286.02:50:22.51#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:50:22.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:50:22.51#ibcon#[25=USB\r\n] 2006.286.02:50:22.51#ibcon#*before write, iclass 3, count 0 2006.286.02:50:22.51#ibcon#enter sib2, iclass 3, count 0 2006.286.02:50:22.51#ibcon#flushed, iclass 3, count 0 2006.286.02:50:22.51#ibcon#about to write, iclass 3, count 0 2006.286.02:50:22.51#ibcon#wrote, iclass 3, count 0 2006.286.02:50:22.51#ibcon#about to read 3, iclass 3, count 0 2006.286.02:50:22.54#ibcon#read 3, iclass 3, count 0 2006.286.02:50:22.54#ibcon#about to read 4, iclass 3, count 0 2006.286.02:50:22.54#ibcon#read 4, iclass 3, count 0 2006.286.02:50:22.54#ibcon#about to read 5, iclass 3, count 0 2006.286.02:50:22.54#ibcon#read 5, iclass 3, count 0 2006.286.02:50:22.54#ibcon#about to read 6, iclass 3, count 0 2006.286.02:50:22.54#ibcon#read 6, iclass 3, count 0 2006.286.02:50:22.54#ibcon#end of sib2, iclass 3, count 0 2006.286.02:50:22.54#ibcon#*after write, iclass 3, count 0 2006.286.02:50:22.54#ibcon#*before return 0, iclass 3, count 0 2006.286.02:50:22.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:50:22.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:50:22.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:50:22.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:50:22.54$vck44/valo=7,864.99 2006.286.02:50:22.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.02:50:22.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.02:50:22.54#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:22.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:50:22.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:50:22.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:50:22.54#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:50:22.54#ibcon#first serial, iclass 5, count 0 2006.286.02:50:22.54#ibcon#enter sib2, iclass 5, count 0 2006.286.02:50:22.54#ibcon#flushed, iclass 5, count 0 2006.286.02:50:22.54#ibcon#about to write, iclass 5, count 0 2006.286.02:50:22.54#ibcon#wrote, iclass 5, count 0 2006.286.02:50:22.54#ibcon#about to read 3, iclass 5, count 0 2006.286.02:50:22.56#ibcon#read 3, iclass 5, count 0 2006.286.02:50:22.56#ibcon#about to read 4, iclass 5, count 0 2006.286.02:50:22.56#ibcon#read 4, iclass 5, count 0 2006.286.02:50:22.56#ibcon#about to read 5, iclass 5, count 0 2006.286.02:50:22.56#ibcon#read 5, iclass 5, count 0 2006.286.02:50:22.56#ibcon#about to read 6, iclass 5, count 0 2006.286.02:50:22.56#ibcon#read 6, iclass 5, count 0 2006.286.02:50:22.56#ibcon#end of sib2, iclass 5, count 0 2006.286.02:50:22.56#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:50:22.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:50:22.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.02:50:22.56#ibcon#*before write, iclass 5, count 0 2006.286.02:50:22.56#ibcon#enter sib2, iclass 5, count 0 2006.286.02:50:22.56#ibcon#flushed, iclass 5, count 0 2006.286.02:50:22.56#ibcon#about to write, iclass 5, count 0 2006.286.02:50:22.56#ibcon#wrote, iclass 5, count 0 2006.286.02:50:22.56#ibcon#about to read 3, iclass 5, count 0 2006.286.02:50:22.60#ibcon#read 3, iclass 5, count 0 2006.286.02:50:22.60#ibcon#about to read 4, iclass 5, count 0 2006.286.02:50:22.60#ibcon#read 4, iclass 5, count 0 2006.286.02:50:22.60#ibcon#about to read 5, iclass 5, count 0 2006.286.02:50:22.60#ibcon#read 5, iclass 5, count 0 2006.286.02:50:22.60#ibcon#about to read 6, iclass 5, count 0 2006.286.02:50:22.60#ibcon#read 6, iclass 5, count 0 2006.286.02:50:22.60#ibcon#end of sib2, iclass 5, count 0 2006.286.02:50:22.60#ibcon#*after write, iclass 5, count 0 2006.286.02:50:22.60#ibcon#*before return 0, iclass 5, count 0 2006.286.02:50:22.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:50:22.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:50:22.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:50:22.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:50:22.60$vck44/va=7,4 2006.286.02:50:22.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.02:50:22.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.02:50:22.60#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:22.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:50:22.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:50:22.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:50:22.66#ibcon#enter wrdev, iclass 7, count 2 2006.286.02:50:22.66#ibcon#first serial, iclass 7, count 2 2006.286.02:50:22.66#ibcon#enter sib2, iclass 7, count 2 2006.286.02:50:22.66#ibcon#flushed, iclass 7, count 2 2006.286.02:50:22.66#ibcon#about to write, iclass 7, count 2 2006.286.02:50:22.66#ibcon#wrote, iclass 7, count 2 2006.286.02:50:22.66#ibcon#about to read 3, iclass 7, count 2 2006.286.02:50:22.68#ibcon#read 3, iclass 7, count 2 2006.286.02:50:22.68#ibcon#about to read 4, iclass 7, count 2 2006.286.02:50:22.68#ibcon#read 4, iclass 7, count 2 2006.286.02:50:22.68#ibcon#about to read 5, iclass 7, count 2 2006.286.02:50:22.68#ibcon#read 5, iclass 7, count 2 2006.286.02:50:22.68#ibcon#about to read 6, iclass 7, count 2 2006.286.02:50:22.68#ibcon#read 6, iclass 7, count 2 2006.286.02:50:22.68#ibcon#end of sib2, iclass 7, count 2 2006.286.02:50:22.68#ibcon#*mode == 0, iclass 7, count 2 2006.286.02:50:22.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.02:50:22.68#ibcon#[25=AT07-04\r\n] 2006.286.02:50:22.68#ibcon#*before write, iclass 7, count 2 2006.286.02:50:22.68#ibcon#enter sib2, iclass 7, count 2 2006.286.02:50:22.68#ibcon#flushed, iclass 7, count 2 2006.286.02:50:22.68#ibcon#about to write, iclass 7, count 2 2006.286.02:50:22.68#ibcon#wrote, iclass 7, count 2 2006.286.02:50:22.68#ibcon#about to read 3, iclass 7, count 2 2006.286.02:50:22.71#ibcon#read 3, iclass 7, count 2 2006.286.02:50:22.71#ibcon#about to read 4, iclass 7, count 2 2006.286.02:50:22.71#ibcon#read 4, iclass 7, count 2 2006.286.02:50:22.71#ibcon#about to read 5, iclass 7, count 2 2006.286.02:50:22.71#ibcon#read 5, iclass 7, count 2 2006.286.02:50:22.71#ibcon#about to read 6, iclass 7, count 2 2006.286.02:50:22.71#ibcon#read 6, iclass 7, count 2 2006.286.02:50:22.71#ibcon#end of sib2, iclass 7, count 2 2006.286.02:50:22.71#ibcon#*after write, iclass 7, count 2 2006.286.02:50:22.71#ibcon#*before return 0, iclass 7, count 2 2006.286.02:50:22.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:50:22.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:50:22.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.02:50:22.71#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:22.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:50:22.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:50:22.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:50:22.83#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:50:22.83#ibcon#first serial, iclass 7, count 0 2006.286.02:50:22.83#ibcon#enter sib2, iclass 7, count 0 2006.286.02:50:22.83#ibcon#flushed, iclass 7, count 0 2006.286.02:50:22.83#ibcon#about to write, iclass 7, count 0 2006.286.02:50:22.83#ibcon#wrote, iclass 7, count 0 2006.286.02:50:22.83#ibcon#about to read 3, iclass 7, count 0 2006.286.02:50:22.85#ibcon#read 3, iclass 7, count 0 2006.286.02:50:22.85#ibcon#about to read 4, iclass 7, count 0 2006.286.02:50:22.85#ibcon#read 4, iclass 7, count 0 2006.286.02:50:22.85#ibcon#about to read 5, iclass 7, count 0 2006.286.02:50:22.85#ibcon#read 5, iclass 7, count 0 2006.286.02:50:22.85#ibcon#about to read 6, iclass 7, count 0 2006.286.02:50:22.85#ibcon#read 6, iclass 7, count 0 2006.286.02:50:22.85#ibcon#end of sib2, iclass 7, count 0 2006.286.02:50:22.85#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:50:22.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:50:22.85#ibcon#[25=USB\r\n] 2006.286.02:50:22.85#ibcon#*before write, iclass 7, count 0 2006.286.02:50:22.85#ibcon#enter sib2, iclass 7, count 0 2006.286.02:50:22.85#ibcon#flushed, iclass 7, count 0 2006.286.02:50:22.85#ibcon#about to write, iclass 7, count 0 2006.286.02:50:22.85#ibcon#wrote, iclass 7, count 0 2006.286.02:50:22.85#ibcon#about to read 3, iclass 7, count 0 2006.286.02:50:22.88#ibcon#read 3, iclass 7, count 0 2006.286.02:50:22.88#ibcon#about to read 4, iclass 7, count 0 2006.286.02:50:22.88#ibcon#read 4, iclass 7, count 0 2006.286.02:50:22.88#ibcon#about to read 5, iclass 7, count 0 2006.286.02:50:22.88#ibcon#read 5, iclass 7, count 0 2006.286.02:50:22.88#ibcon#about to read 6, iclass 7, count 0 2006.286.02:50:22.88#ibcon#read 6, iclass 7, count 0 2006.286.02:50:22.88#ibcon#end of sib2, iclass 7, count 0 2006.286.02:50:22.88#ibcon#*after write, iclass 7, count 0 2006.286.02:50:22.88#ibcon#*before return 0, iclass 7, count 0 2006.286.02:50:22.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:50:22.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:50:22.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:50:22.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:50:22.88$vck44/valo=8,884.99 2006.286.02:50:22.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.02:50:22.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.02:50:22.88#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:22.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:50:22.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:50:22.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:50:22.88#ibcon#enter wrdev, iclass 11, count 0 2006.286.02:50:22.88#ibcon#first serial, iclass 11, count 0 2006.286.02:50:22.88#ibcon#enter sib2, iclass 11, count 0 2006.286.02:50:22.88#ibcon#flushed, iclass 11, count 0 2006.286.02:50:22.88#ibcon#about to write, iclass 11, count 0 2006.286.02:50:22.88#ibcon#wrote, iclass 11, count 0 2006.286.02:50:22.88#ibcon#about to read 3, iclass 11, count 0 2006.286.02:50:22.90#ibcon#read 3, iclass 11, count 0 2006.286.02:50:22.90#ibcon#about to read 4, iclass 11, count 0 2006.286.02:50:22.90#ibcon#read 4, iclass 11, count 0 2006.286.02:50:22.90#ibcon#about to read 5, iclass 11, count 0 2006.286.02:50:22.90#ibcon#read 5, iclass 11, count 0 2006.286.02:50:22.90#ibcon#about to read 6, iclass 11, count 0 2006.286.02:50:22.90#ibcon#read 6, iclass 11, count 0 2006.286.02:50:22.90#ibcon#end of sib2, iclass 11, count 0 2006.286.02:50:22.90#ibcon#*mode == 0, iclass 11, count 0 2006.286.02:50:22.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.02:50:22.90#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.02:50:22.90#ibcon#*before write, iclass 11, count 0 2006.286.02:50:22.90#ibcon#enter sib2, iclass 11, count 0 2006.286.02:50:22.90#ibcon#flushed, iclass 11, count 0 2006.286.02:50:22.90#ibcon#about to write, iclass 11, count 0 2006.286.02:50:22.90#ibcon#wrote, iclass 11, count 0 2006.286.02:50:22.90#ibcon#about to read 3, iclass 11, count 0 2006.286.02:50:22.94#ibcon#read 3, iclass 11, count 0 2006.286.02:50:22.94#ibcon#about to read 4, iclass 11, count 0 2006.286.02:50:22.94#ibcon#read 4, iclass 11, count 0 2006.286.02:50:22.94#ibcon#about to read 5, iclass 11, count 0 2006.286.02:50:22.94#ibcon#read 5, iclass 11, count 0 2006.286.02:50:22.94#ibcon#about to read 6, iclass 11, count 0 2006.286.02:50:22.94#ibcon#read 6, iclass 11, count 0 2006.286.02:50:22.94#ibcon#end of sib2, iclass 11, count 0 2006.286.02:50:22.94#ibcon#*after write, iclass 11, count 0 2006.286.02:50:22.94#ibcon#*before return 0, iclass 11, count 0 2006.286.02:50:22.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:50:22.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:50:22.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.02:50:22.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.02:50:22.94$vck44/va=8,3 2006.286.02:50:22.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.02:50:22.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.02:50:22.94#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:22.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:50:23.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:50:23.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:50:23.00#ibcon#enter wrdev, iclass 13, count 2 2006.286.02:50:23.00#ibcon#first serial, iclass 13, count 2 2006.286.02:50:23.00#ibcon#enter sib2, iclass 13, count 2 2006.286.02:50:23.00#ibcon#flushed, iclass 13, count 2 2006.286.02:50:23.00#ibcon#about to write, iclass 13, count 2 2006.286.02:50:23.00#ibcon#wrote, iclass 13, count 2 2006.286.02:50:23.00#ibcon#about to read 3, iclass 13, count 2 2006.286.02:50:23.02#ibcon#read 3, iclass 13, count 2 2006.286.02:50:23.02#ibcon#about to read 4, iclass 13, count 2 2006.286.02:50:23.02#ibcon#read 4, iclass 13, count 2 2006.286.02:50:23.02#ibcon#about to read 5, iclass 13, count 2 2006.286.02:50:23.02#ibcon#read 5, iclass 13, count 2 2006.286.02:50:23.02#ibcon#about to read 6, iclass 13, count 2 2006.286.02:50:23.02#ibcon#read 6, iclass 13, count 2 2006.286.02:50:23.02#ibcon#end of sib2, iclass 13, count 2 2006.286.02:50:23.02#ibcon#*mode == 0, iclass 13, count 2 2006.286.02:50:23.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.02:50:23.02#ibcon#[25=AT08-03\r\n] 2006.286.02:50:23.02#ibcon#*before write, iclass 13, count 2 2006.286.02:50:23.02#ibcon#enter sib2, iclass 13, count 2 2006.286.02:50:23.02#ibcon#flushed, iclass 13, count 2 2006.286.02:50:23.02#ibcon#about to write, iclass 13, count 2 2006.286.02:50:23.02#ibcon#wrote, iclass 13, count 2 2006.286.02:50:23.02#ibcon#about to read 3, iclass 13, count 2 2006.286.02:50:23.05#ibcon#read 3, iclass 13, count 2 2006.286.02:50:23.05#ibcon#about to read 4, iclass 13, count 2 2006.286.02:50:23.05#ibcon#read 4, iclass 13, count 2 2006.286.02:50:23.05#ibcon#about to read 5, iclass 13, count 2 2006.286.02:50:23.05#ibcon#read 5, iclass 13, count 2 2006.286.02:50:23.05#ibcon#about to read 6, iclass 13, count 2 2006.286.02:50:23.05#ibcon#read 6, iclass 13, count 2 2006.286.02:50:23.05#ibcon#end of sib2, iclass 13, count 2 2006.286.02:50:23.05#ibcon#*after write, iclass 13, count 2 2006.286.02:50:23.05#ibcon#*before return 0, iclass 13, count 2 2006.286.02:50:23.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:50:23.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.02:50:23.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.02:50:23.05#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:23.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:50:23.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:50:23.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:50:23.17#ibcon#enter wrdev, iclass 13, count 0 2006.286.02:50:23.17#ibcon#first serial, iclass 13, count 0 2006.286.02:50:23.17#ibcon#enter sib2, iclass 13, count 0 2006.286.02:50:23.17#ibcon#flushed, iclass 13, count 0 2006.286.02:50:23.17#ibcon#about to write, iclass 13, count 0 2006.286.02:50:23.17#ibcon#wrote, iclass 13, count 0 2006.286.02:50:23.17#ibcon#about to read 3, iclass 13, count 0 2006.286.02:50:23.19#ibcon#read 3, iclass 13, count 0 2006.286.02:50:23.19#ibcon#about to read 4, iclass 13, count 0 2006.286.02:50:23.19#ibcon#read 4, iclass 13, count 0 2006.286.02:50:23.19#ibcon#about to read 5, iclass 13, count 0 2006.286.02:50:23.19#ibcon#read 5, iclass 13, count 0 2006.286.02:50:23.19#ibcon#about to read 6, iclass 13, count 0 2006.286.02:50:23.19#ibcon#read 6, iclass 13, count 0 2006.286.02:50:23.19#ibcon#end of sib2, iclass 13, count 0 2006.286.02:50:23.19#ibcon#*mode == 0, iclass 13, count 0 2006.286.02:50:23.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.02:50:23.19#ibcon#[25=USB\r\n] 2006.286.02:50:23.19#ibcon#*before write, iclass 13, count 0 2006.286.02:50:23.19#ibcon#enter sib2, iclass 13, count 0 2006.286.02:50:23.19#ibcon#flushed, iclass 13, count 0 2006.286.02:50:23.19#ibcon#about to write, iclass 13, count 0 2006.286.02:50:23.19#ibcon#wrote, iclass 13, count 0 2006.286.02:50:23.19#ibcon#about to read 3, iclass 13, count 0 2006.286.02:50:23.22#ibcon#read 3, iclass 13, count 0 2006.286.02:50:23.22#ibcon#about to read 4, iclass 13, count 0 2006.286.02:50:23.22#ibcon#read 4, iclass 13, count 0 2006.286.02:50:23.22#ibcon#about to read 5, iclass 13, count 0 2006.286.02:50:23.22#ibcon#read 5, iclass 13, count 0 2006.286.02:50:23.22#ibcon#about to read 6, iclass 13, count 0 2006.286.02:50:23.22#ibcon#read 6, iclass 13, count 0 2006.286.02:50:23.22#ibcon#end of sib2, iclass 13, count 0 2006.286.02:50:23.22#ibcon#*after write, iclass 13, count 0 2006.286.02:50:23.22#ibcon#*before return 0, iclass 13, count 0 2006.286.02:50:23.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:50:23.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.02:50:23.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.02:50:23.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.02:50:23.22$vck44/vblo=1,629.99 2006.286.02:50:23.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.02:50:23.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.02:50:23.22#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:23.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:50:23.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:50:23.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:50:23.22#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:50:23.22#ibcon#first serial, iclass 15, count 0 2006.286.02:50:23.22#ibcon#enter sib2, iclass 15, count 0 2006.286.02:50:23.22#ibcon#flushed, iclass 15, count 0 2006.286.02:50:23.22#ibcon#about to write, iclass 15, count 0 2006.286.02:50:23.22#ibcon#wrote, iclass 15, count 0 2006.286.02:50:23.22#ibcon#about to read 3, iclass 15, count 0 2006.286.02:50:23.24#ibcon#read 3, iclass 15, count 0 2006.286.02:50:23.24#ibcon#about to read 4, iclass 15, count 0 2006.286.02:50:23.24#ibcon#read 4, iclass 15, count 0 2006.286.02:50:23.24#ibcon#about to read 5, iclass 15, count 0 2006.286.02:50:23.24#ibcon#read 5, iclass 15, count 0 2006.286.02:50:23.24#ibcon#about to read 6, iclass 15, count 0 2006.286.02:50:23.24#ibcon#read 6, iclass 15, count 0 2006.286.02:50:23.24#ibcon#end of sib2, iclass 15, count 0 2006.286.02:50:23.24#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:50:23.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:50:23.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.02:50:23.24#ibcon#*before write, iclass 15, count 0 2006.286.02:50:23.24#ibcon#enter sib2, iclass 15, count 0 2006.286.02:50:23.24#ibcon#flushed, iclass 15, count 0 2006.286.02:50:23.24#ibcon#about to write, iclass 15, count 0 2006.286.02:50:23.24#ibcon#wrote, iclass 15, count 0 2006.286.02:50:23.24#ibcon#about to read 3, iclass 15, count 0 2006.286.02:50:23.28#ibcon#read 3, iclass 15, count 0 2006.286.02:50:23.28#ibcon#about to read 4, iclass 15, count 0 2006.286.02:50:23.28#ibcon#read 4, iclass 15, count 0 2006.286.02:50:23.28#ibcon#about to read 5, iclass 15, count 0 2006.286.02:50:23.28#ibcon#read 5, iclass 15, count 0 2006.286.02:50:23.28#ibcon#about to read 6, iclass 15, count 0 2006.286.02:50:23.28#ibcon#read 6, iclass 15, count 0 2006.286.02:50:23.28#ibcon#end of sib2, iclass 15, count 0 2006.286.02:50:23.28#ibcon#*after write, iclass 15, count 0 2006.286.02:50:23.28#ibcon#*before return 0, iclass 15, count 0 2006.286.02:50:23.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:50:23.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.02:50:23.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:50:23.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:50:23.28$vck44/vb=1,4 2006.286.02:50:23.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.02:50:23.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.02:50:23.28#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:23.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:50:23.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:50:23.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:50:23.28#ibcon#enter wrdev, iclass 17, count 2 2006.286.02:50:23.28#ibcon#first serial, iclass 17, count 2 2006.286.02:50:23.28#ibcon#enter sib2, iclass 17, count 2 2006.286.02:50:23.28#ibcon#flushed, iclass 17, count 2 2006.286.02:50:23.28#ibcon#about to write, iclass 17, count 2 2006.286.02:50:23.28#ibcon#wrote, iclass 17, count 2 2006.286.02:50:23.28#ibcon#about to read 3, iclass 17, count 2 2006.286.02:50:23.30#ibcon#read 3, iclass 17, count 2 2006.286.02:50:23.30#ibcon#about to read 4, iclass 17, count 2 2006.286.02:50:23.30#ibcon#read 4, iclass 17, count 2 2006.286.02:50:23.30#ibcon#about to read 5, iclass 17, count 2 2006.286.02:50:23.30#ibcon#read 5, iclass 17, count 2 2006.286.02:50:23.30#ibcon#about to read 6, iclass 17, count 2 2006.286.02:50:23.30#ibcon#read 6, iclass 17, count 2 2006.286.02:50:23.30#ibcon#end of sib2, iclass 17, count 2 2006.286.02:50:23.30#ibcon#*mode == 0, iclass 17, count 2 2006.286.02:50:23.30#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.02:50:23.30#ibcon#[27=AT01-04\r\n] 2006.286.02:50:23.30#ibcon#*before write, iclass 17, count 2 2006.286.02:50:23.30#ibcon#enter sib2, iclass 17, count 2 2006.286.02:50:23.30#ibcon#flushed, iclass 17, count 2 2006.286.02:50:23.30#ibcon#about to write, iclass 17, count 2 2006.286.02:50:23.30#ibcon#wrote, iclass 17, count 2 2006.286.02:50:23.30#ibcon#about to read 3, iclass 17, count 2 2006.286.02:50:23.33#ibcon#read 3, iclass 17, count 2 2006.286.02:50:23.33#ibcon#about to read 4, iclass 17, count 2 2006.286.02:50:23.33#ibcon#read 4, iclass 17, count 2 2006.286.02:50:23.33#ibcon#about to read 5, iclass 17, count 2 2006.286.02:50:23.33#ibcon#read 5, iclass 17, count 2 2006.286.02:50:23.33#ibcon#about to read 6, iclass 17, count 2 2006.286.02:50:23.33#ibcon#read 6, iclass 17, count 2 2006.286.02:50:23.33#ibcon#end of sib2, iclass 17, count 2 2006.286.02:50:23.33#ibcon#*after write, iclass 17, count 2 2006.286.02:50:23.33#ibcon#*before return 0, iclass 17, count 2 2006.286.02:50:23.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:50:23.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.02:50:23.33#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.02:50:23.33#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:23.33#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:50:23.45#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:50:23.45#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:50:23.45#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:50:23.45#ibcon#first serial, iclass 17, count 0 2006.286.02:50:23.45#ibcon#enter sib2, iclass 17, count 0 2006.286.02:50:23.45#ibcon#flushed, iclass 17, count 0 2006.286.02:50:23.45#ibcon#about to write, iclass 17, count 0 2006.286.02:50:23.45#ibcon#wrote, iclass 17, count 0 2006.286.02:50:23.45#ibcon#about to read 3, iclass 17, count 0 2006.286.02:50:23.47#ibcon#read 3, iclass 17, count 0 2006.286.02:50:23.47#ibcon#about to read 4, iclass 17, count 0 2006.286.02:50:23.47#ibcon#read 4, iclass 17, count 0 2006.286.02:50:23.47#ibcon#about to read 5, iclass 17, count 0 2006.286.02:50:23.47#ibcon#read 5, iclass 17, count 0 2006.286.02:50:23.47#ibcon#about to read 6, iclass 17, count 0 2006.286.02:50:23.47#ibcon#read 6, iclass 17, count 0 2006.286.02:50:23.51#ibcon#end of sib2, iclass 17, count 0 2006.286.02:50:23.51#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:50:23.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:50:23.51#ibcon#[27=USB\r\n] 2006.286.02:50:23.51#ibcon#*before write, iclass 17, count 0 2006.286.02:50:23.51#ibcon#enter sib2, iclass 17, count 0 2006.286.02:50:23.51#ibcon#flushed, iclass 17, count 0 2006.286.02:50:23.51#ibcon#about to write, iclass 17, count 0 2006.286.02:50:23.51#ibcon#wrote, iclass 17, count 0 2006.286.02:50:23.51#ibcon#about to read 3, iclass 17, count 0 2006.286.02:50:23.54#ibcon#read 3, iclass 17, count 0 2006.286.02:50:23.54#ibcon#about to read 4, iclass 17, count 0 2006.286.02:50:23.54#ibcon#read 4, iclass 17, count 0 2006.286.02:50:23.54#ibcon#about to read 5, iclass 17, count 0 2006.286.02:50:23.54#ibcon#read 5, iclass 17, count 0 2006.286.02:50:23.54#ibcon#about to read 6, iclass 17, count 0 2006.286.02:50:23.54#ibcon#read 6, iclass 17, count 0 2006.286.02:50:23.54#ibcon#end of sib2, iclass 17, count 0 2006.286.02:50:23.54#ibcon#*after write, iclass 17, count 0 2006.286.02:50:23.54#ibcon#*before return 0, iclass 17, count 0 2006.286.02:50:23.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:50:23.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.02:50:23.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:50:23.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:50:23.54$vck44/vblo=2,634.99 2006.286.02:50:23.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.02:50:23.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.02:50:23.54#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:23.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:50:23.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:50:23.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:50:23.54#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:50:23.54#ibcon#first serial, iclass 19, count 0 2006.286.02:50:23.54#ibcon#enter sib2, iclass 19, count 0 2006.286.02:50:23.54#ibcon#flushed, iclass 19, count 0 2006.286.02:50:23.54#ibcon#about to write, iclass 19, count 0 2006.286.02:50:23.54#ibcon#wrote, iclass 19, count 0 2006.286.02:50:23.54#ibcon#about to read 3, iclass 19, count 0 2006.286.02:50:23.56#ibcon#read 3, iclass 19, count 0 2006.286.02:50:23.56#ibcon#about to read 4, iclass 19, count 0 2006.286.02:50:23.56#ibcon#read 4, iclass 19, count 0 2006.286.02:50:23.56#ibcon#about to read 5, iclass 19, count 0 2006.286.02:50:23.56#ibcon#read 5, iclass 19, count 0 2006.286.02:50:23.56#ibcon#about to read 6, iclass 19, count 0 2006.286.02:50:23.56#ibcon#read 6, iclass 19, count 0 2006.286.02:50:23.56#ibcon#end of sib2, iclass 19, count 0 2006.286.02:50:23.56#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:50:23.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:50:23.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.02:50:23.56#ibcon#*before write, iclass 19, count 0 2006.286.02:50:23.56#ibcon#enter sib2, iclass 19, count 0 2006.286.02:50:23.56#ibcon#flushed, iclass 19, count 0 2006.286.02:50:23.56#ibcon#about to write, iclass 19, count 0 2006.286.02:50:23.56#ibcon#wrote, iclass 19, count 0 2006.286.02:50:23.56#ibcon#about to read 3, iclass 19, count 0 2006.286.02:50:23.60#ibcon#read 3, iclass 19, count 0 2006.286.02:50:23.60#ibcon#about to read 4, iclass 19, count 0 2006.286.02:50:23.60#ibcon#read 4, iclass 19, count 0 2006.286.02:50:23.60#ibcon#about to read 5, iclass 19, count 0 2006.286.02:50:23.60#ibcon#read 5, iclass 19, count 0 2006.286.02:50:23.60#ibcon#about to read 6, iclass 19, count 0 2006.286.02:50:23.60#ibcon#read 6, iclass 19, count 0 2006.286.02:50:23.60#ibcon#end of sib2, iclass 19, count 0 2006.286.02:50:23.60#ibcon#*after write, iclass 19, count 0 2006.286.02:50:23.60#ibcon#*before return 0, iclass 19, count 0 2006.286.02:50:23.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:50:23.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.02:50:23.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:50:23.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:50:23.60$vck44/vb=2,5 2006.286.02:50:23.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.02:50:23.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.02:50:23.60#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:23.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:50:23.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:50:23.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:50:23.66#ibcon#enter wrdev, iclass 21, count 2 2006.286.02:50:23.66#ibcon#first serial, iclass 21, count 2 2006.286.02:50:23.66#ibcon#enter sib2, iclass 21, count 2 2006.286.02:50:23.66#ibcon#flushed, iclass 21, count 2 2006.286.02:50:23.66#ibcon#about to write, iclass 21, count 2 2006.286.02:50:23.66#ibcon#wrote, iclass 21, count 2 2006.286.02:50:23.66#ibcon#about to read 3, iclass 21, count 2 2006.286.02:50:23.68#ibcon#read 3, iclass 21, count 2 2006.286.02:50:23.68#ibcon#about to read 4, iclass 21, count 2 2006.286.02:50:23.68#ibcon#read 4, iclass 21, count 2 2006.286.02:50:23.68#ibcon#about to read 5, iclass 21, count 2 2006.286.02:50:23.68#ibcon#read 5, iclass 21, count 2 2006.286.02:50:23.68#ibcon#about to read 6, iclass 21, count 2 2006.286.02:50:23.68#ibcon#read 6, iclass 21, count 2 2006.286.02:50:23.68#ibcon#end of sib2, iclass 21, count 2 2006.286.02:50:23.68#ibcon#*mode == 0, iclass 21, count 2 2006.286.02:50:23.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.02:50:23.68#ibcon#[27=AT02-05\r\n] 2006.286.02:50:23.68#ibcon#*before write, iclass 21, count 2 2006.286.02:50:23.68#ibcon#enter sib2, iclass 21, count 2 2006.286.02:50:23.68#ibcon#flushed, iclass 21, count 2 2006.286.02:50:23.68#ibcon#about to write, iclass 21, count 2 2006.286.02:50:23.68#ibcon#wrote, iclass 21, count 2 2006.286.02:50:23.68#ibcon#about to read 3, iclass 21, count 2 2006.286.02:50:23.71#ibcon#read 3, iclass 21, count 2 2006.286.02:50:23.71#ibcon#about to read 4, iclass 21, count 2 2006.286.02:50:23.71#ibcon#read 4, iclass 21, count 2 2006.286.02:50:23.71#ibcon#about to read 5, iclass 21, count 2 2006.286.02:50:23.71#ibcon#read 5, iclass 21, count 2 2006.286.02:50:23.71#ibcon#about to read 6, iclass 21, count 2 2006.286.02:50:23.71#ibcon#read 6, iclass 21, count 2 2006.286.02:50:23.71#ibcon#end of sib2, iclass 21, count 2 2006.286.02:50:23.71#ibcon#*after write, iclass 21, count 2 2006.286.02:50:23.71#ibcon#*before return 0, iclass 21, count 2 2006.286.02:50:23.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:50:23.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.02:50:23.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.02:50:23.71#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:23.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:50:23.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:50:23.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:50:23.83#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:50:23.83#ibcon#first serial, iclass 21, count 0 2006.286.02:50:23.83#ibcon#enter sib2, iclass 21, count 0 2006.286.02:50:23.83#ibcon#flushed, iclass 21, count 0 2006.286.02:50:23.83#ibcon#about to write, iclass 21, count 0 2006.286.02:50:23.83#ibcon#wrote, iclass 21, count 0 2006.286.02:50:23.83#ibcon#about to read 3, iclass 21, count 0 2006.286.02:50:23.85#ibcon#read 3, iclass 21, count 0 2006.286.02:50:23.85#ibcon#about to read 4, iclass 21, count 0 2006.286.02:50:23.85#ibcon#read 4, iclass 21, count 0 2006.286.02:50:23.85#ibcon#about to read 5, iclass 21, count 0 2006.286.02:50:23.85#ibcon#read 5, iclass 21, count 0 2006.286.02:50:23.85#ibcon#about to read 6, iclass 21, count 0 2006.286.02:50:23.85#ibcon#read 6, iclass 21, count 0 2006.286.02:50:23.85#ibcon#end of sib2, iclass 21, count 0 2006.286.02:50:23.85#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:50:23.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:50:23.85#ibcon#[27=USB\r\n] 2006.286.02:50:23.85#ibcon#*before write, iclass 21, count 0 2006.286.02:50:23.85#ibcon#enter sib2, iclass 21, count 0 2006.286.02:50:23.85#ibcon#flushed, iclass 21, count 0 2006.286.02:50:23.85#ibcon#about to write, iclass 21, count 0 2006.286.02:50:23.85#ibcon#wrote, iclass 21, count 0 2006.286.02:50:23.85#ibcon#about to read 3, iclass 21, count 0 2006.286.02:50:23.88#ibcon#read 3, iclass 21, count 0 2006.286.02:50:23.88#ibcon#about to read 4, iclass 21, count 0 2006.286.02:50:23.88#ibcon#read 4, iclass 21, count 0 2006.286.02:50:23.88#ibcon#about to read 5, iclass 21, count 0 2006.286.02:50:23.88#ibcon#read 5, iclass 21, count 0 2006.286.02:50:23.88#ibcon#about to read 6, iclass 21, count 0 2006.286.02:50:23.88#ibcon#read 6, iclass 21, count 0 2006.286.02:50:23.88#ibcon#end of sib2, iclass 21, count 0 2006.286.02:50:23.88#ibcon#*after write, iclass 21, count 0 2006.286.02:50:23.88#ibcon#*before return 0, iclass 21, count 0 2006.286.02:50:23.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:50:23.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.02:50:23.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:50:23.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:50:23.88$vck44/vblo=3,649.99 2006.286.02:50:23.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.02:50:23.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.02:50:23.88#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:23.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:50:23.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:50:23.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:50:23.88#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:50:23.88#ibcon#first serial, iclass 23, count 0 2006.286.02:50:23.88#ibcon#enter sib2, iclass 23, count 0 2006.286.02:50:23.88#ibcon#flushed, iclass 23, count 0 2006.286.02:50:23.88#ibcon#about to write, iclass 23, count 0 2006.286.02:50:23.88#ibcon#wrote, iclass 23, count 0 2006.286.02:50:23.88#ibcon#about to read 3, iclass 23, count 0 2006.286.02:50:23.90#ibcon#read 3, iclass 23, count 0 2006.286.02:50:23.90#ibcon#about to read 4, iclass 23, count 0 2006.286.02:50:23.90#ibcon#read 4, iclass 23, count 0 2006.286.02:50:23.90#ibcon#about to read 5, iclass 23, count 0 2006.286.02:50:23.90#ibcon#read 5, iclass 23, count 0 2006.286.02:50:23.90#ibcon#about to read 6, iclass 23, count 0 2006.286.02:50:23.90#ibcon#read 6, iclass 23, count 0 2006.286.02:50:23.90#ibcon#end of sib2, iclass 23, count 0 2006.286.02:50:23.90#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:50:23.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:50:23.90#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.02:50:23.90#ibcon#*before write, iclass 23, count 0 2006.286.02:50:23.90#ibcon#enter sib2, iclass 23, count 0 2006.286.02:50:23.90#ibcon#flushed, iclass 23, count 0 2006.286.02:50:23.90#ibcon#about to write, iclass 23, count 0 2006.286.02:50:23.90#ibcon#wrote, iclass 23, count 0 2006.286.02:50:23.90#ibcon#about to read 3, iclass 23, count 0 2006.286.02:50:23.94#ibcon#read 3, iclass 23, count 0 2006.286.02:50:23.94#ibcon#about to read 4, iclass 23, count 0 2006.286.02:50:23.94#ibcon#read 4, iclass 23, count 0 2006.286.02:50:23.94#ibcon#about to read 5, iclass 23, count 0 2006.286.02:50:23.94#ibcon#read 5, iclass 23, count 0 2006.286.02:50:23.94#ibcon#about to read 6, iclass 23, count 0 2006.286.02:50:23.94#ibcon#read 6, iclass 23, count 0 2006.286.02:50:23.94#ibcon#end of sib2, iclass 23, count 0 2006.286.02:50:23.94#ibcon#*after write, iclass 23, count 0 2006.286.02:50:23.94#ibcon#*before return 0, iclass 23, count 0 2006.286.02:50:23.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:50:23.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.02:50:23.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:50:23.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:50:23.94$vck44/vb=3,4 2006.286.02:50:23.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.02:50:23.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.02:50:23.94#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:23.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:50:24.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:50:24.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:50:24.00#ibcon#enter wrdev, iclass 25, count 2 2006.286.02:50:24.00#ibcon#first serial, iclass 25, count 2 2006.286.02:50:24.00#ibcon#enter sib2, iclass 25, count 2 2006.286.02:50:24.00#ibcon#flushed, iclass 25, count 2 2006.286.02:50:24.00#ibcon#about to write, iclass 25, count 2 2006.286.02:50:24.00#ibcon#wrote, iclass 25, count 2 2006.286.02:50:24.00#ibcon#about to read 3, iclass 25, count 2 2006.286.02:50:24.02#ibcon#read 3, iclass 25, count 2 2006.286.02:50:24.02#ibcon#about to read 4, iclass 25, count 2 2006.286.02:50:24.02#ibcon#read 4, iclass 25, count 2 2006.286.02:50:24.02#ibcon#about to read 5, iclass 25, count 2 2006.286.02:50:24.02#ibcon#read 5, iclass 25, count 2 2006.286.02:50:24.02#ibcon#about to read 6, iclass 25, count 2 2006.286.02:50:24.02#ibcon#read 6, iclass 25, count 2 2006.286.02:50:24.02#ibcon#end of sib2, iclass 25, count 2 2006.286.02:50:24.02#ibcon#*mode == 0, iclass 25, count 2 2006.286.02:50:24.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.02:50:24.02#ibcon#[27=AT03-04\r\n] 2006.286.02:50:24.02#ibcon#*before write, iclass 25, count 2 2006.286.02:50:24.02#ibcon#enter sib2, iclass 25, count 2 2006.286.02:50:24.02#ibcon#flushed, iclass 25, count 2 2006.286.02:50:24.02#ibcon#about to write, iclass 25, count 2 2006.286.02:50:24.02#ibcon#wrote, iclass 25, count 2 2006.286.02:50:24.02#ibcon#about to read 3, iclass 25, count 2 2006.286.02:50:24.05#ibcon#read 3, iclass 25, count 2 2006.286.02:50:24.05#ibcon#about to read 4, iclass 25, count 2 2006.286.02:50:24.05#ibcon#read 4, iclass 25, count 2 2006.286.02:50:24.05#ibcon#about to read 5, iclass 25, count 2 2006.286.02:50:24.05#ibcon#read 5, iclass 25, count 2 2006.286.02:50:24.05#ibcon#about to read 6, iclass 25, count 2 2006.286.02:50:24.05#ibcon#read 6, iclass 25, count 2 2006.286.02:50:24.05#ibcon#end of sib2, iclass 25, count 2 2006.286.02:50:24.05#ibcon#*after write, iclass 25, count 2 2006.286.02:50:24.05#ibcon#*before return 0, iclass 25, count 2 2006.286.02:50:24.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:50:24.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.02:50:24.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.02:50:24.05#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:24.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:50:24.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:50:24.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:50:24.17#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:50:24.17#ibcon#first serial, iclass 25, count 0 2006.286.02:50:24.17#ibcon#enter sib2, iclass 25, count 0 2006.286.02:50:24.17#ibcon#flushed, iclass 25, count 0 2006.286.02:50:24.17#ibcon#about to write, iclass 25, count 0 2006.286.02:50:24.17#ibcon#wrote, iclass 25, count 0 2006.286.02:50:24.17#ibcon#about to read 3, iclass 25, count 0 2006.286.02:50:24.19#ibcon#read 3, iclass 25, count 0 2006.286.02:50:24.19#ibcon#about to read 4, iclass 25, count 0 2006.286.02:50:24.19#ibcon#read 4, iclass 25, count 0 2006.286.02:50:24.19#ibcon#about to read 5, iclass 25, count 0 2006.286.02:50:24.19#ibcon#read 5, iclass 25, count 0 2006.286.02:50:24.19#ibcon#about to read 6, iclass 25, count 0 2006.286.02:50:24.19#ibcon#read 6, iclass 25, count 0 2006.286.02:50:24.19#ibcon#end of sib2, iclass 25, count 0 2006.286.02:50:24.19#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:50:24.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:50:24.19#ibcon#[27=USB\r\n] 2006.286.02:50:24.19#ibcon#*before write, iclass 25, count 0 2006.286.02:50:24.19#ibcon#enter sib2, iclass 25, count 0 2006.286.02:50:24.19#ibcon#flushed, iclass 25, count 0 2006.286.02:50:24.19#ibcon#about to write, iclass 25, count 0 2006.286.02:50:24.19#ibcon#wrote, iclass 25, count 0 2006.286.02:50:24.19#ibcon#about to read 3, iclass 25, count 0 2006.286.02:50:24.22#ibcon#read 3, iclass 25, count 0 2006.286.02:50:24.22#ibcon#about to read 4, iclass 25, count 0 2006.286.02:50:24.22#ibcon#read 4, iclass 25, count 0 2006.286.02:50:24.22#ibcon#about to read 5, iclass 25, count 0 2006.286.02:50:24.22#ibcon#read 5, iclass 25, count 0 2006.286.02:50:24.22#ibcon#about to read 6, iclass 25, count 0 2006.286.02:50:24.22#ibcon#read 6, iclass 25, count 0 2006.286.02:50:24.22#ibcon#end of sib2, iclass 25, count 0 2006.286.02:50:24.22#ibcon#*after write, iclass 25, count 0 2006.286.02:50:24.22#ibcon#*before return 0, iclass 25, count 0 2006.286.02:50:24.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:50:24.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.02:50:24.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:50:24.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:50:24.22$vck44/vblo=4,679.99 2006.286.02:50:24.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.02:50:24.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.02:50:24.22#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:24.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:50:24.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:50:24.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:50:24.22#ibcon#enter wrdev, iclass 27, count 0 2006.286.02:50:24.22#ibcon#first serial, iclass 27, count 0 2006.286.02:50:24.22#ibcon#enter sib2, iclass 27, count 0 2006.286.02:50:24.22#ibcon#flushed, iclass 27, count 0 2006.286.02:50:24.22#ibcon#about to write, iclass 27, count 0 2006.286.02:50:24.22#ibcon#wrote, iclass 27, count 0 2006.286.02:50:24.22#ibcon#about to read 3, iclass 27, count 0 2006.286.02:50:24.24#ibcon#read 3, iclass 27, count 0 2006.286.02:50:24.24#ibcon#about to read 4, iclass 27, count 0 2006.286.02:50:24.24#ibcon#read 4, iclass 27, count 0 2006.286.02:50:24.24#ibcon#about to read 5, iclass 27, count 0 2006.286.02:50:24.24#ibcon#read 5, iclass 27, count 0 2006.286.02:50:24.24#ibcon#about to read 6, iclass 27, count 0 2006.286.02:50:24.24#ibcon#read 6, iclass 27, count 0 2006.286.02:50:24.24#ibcon#end of sib2, iclass 27, count 0 2006.286.02:50:24.24#ibcon#*mode == 0, iclass 27, count 0 2006.286.02:50:24.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.02:50:24.24#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.02:50:24.24#ibcon#*before write, iclass 27, count 0 2006.286.02:50:24.24#ibcon#enter sib2, iclass 27, count 0 2006.286.02:50:24.24#ibcon#flushed, iclass 27, count 0 2006.286.02:50:24.24#ibcon#about to write, iclass 27, count 0 2006.286.02:50:24.24#ibcon#wrote, iclass 27, count 0 2006.286.02:50:24.24#ibcon#about to read 3, iclass 27, count 0 2006.286.02:50:24.28#ibcon#read 3, iclass 27, count 0 2006.286.02:50:24.28#ibcon#about to read 4, iclass 27, count 0 2006.286.02:50:24.28#ibcon#read 4, iclass 27, count 0 2006.286.02:50:24.28#ibcon#about to read 5, iclass 27, count 0 2006.286.02:50:24.28#ibcon#read 5, iclass 27, count 0 2006.286.02:50:24.28#ibcon#about to read 6, iclass 27, count 0 2006.286.02:50:24.28#ibcon#read 6, iclass 27, count 0 2006.286.02:50:24.28#ibcon#end of sib2, iclass 27, count 0 2006.286.02:50:24.28#ibcon#*after write, iclass 27, count 0 2006.286.02:50:24.28#ibcon#*before return 0, iclass 27, count 0 2006.286.02:50:24.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:50:24.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.02:50:24.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.02:50:24.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.02:50:24.28$vck44/vb=4,5 2006.286.02:50:24.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.02:50:24.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.02:50:24.28#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:24.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:50:24.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:50:24.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:50:24.34#ibcon#enter wrdev, iclass 29, count 2 2006.286.02:50:24.34#ibcon#first serial, iclass 29, count 2 2006.286.02:50:24.34#ibcon#enter sib2, iclass 29, count 2 2006.286.02:50:24.34#ibcon#flushed, iclass 29, count 2 2006.286.02:50:24.34#ibcon#about to write, iclass 29, count 2 2006.286.02:50:24.34#ibcon#wrote, iclass 29, count 2 2006.286.02:50:24.34#ibcon#about to read 3, iclass 29, count 2 2006.286.02:50:24.36#ibcon#read 3, iclass 29, count 2 2006.286.02:50:24.36#ibcon#about to read 4, iclass 29, count 2 2006.286.02:50:24.36#ibcon#read 4, iclass 29, count 2 2006.286.02:50:24.36#ibcon#about to read 5, iclass 29, count 2 2006.286.02:50:24.36#ibcon#read 5, iclass 29, count 2 2006.286.02:50:24.36#ibcon#about to read 6, iclass 29, count 2 2006.286.02:50:24.36#ibcon#read 6, iclass 29, count 2 2006.286.02:50:24.36#ibcon#end of sib2, iclass 29, count 2 2006.286.02:50:24.36#ibcon#*mode == 0, iclass 29, count 2 2006.286.02:50:24.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.02:50:24.36#ibcon#[27=AT04-05\r\n] 2006.286.02:50:24.36#ibcon#*before write, iclass 29, count 2 2006.286.02:50:24.36#ibcon#enter sib2, iclass 29, count 2 2006.286.02:50:24.36#ibcon#flushed, iclass 29, count 2 2006.286.02:50:24.36#ibcon#about to write, iclass 29, count 2 2006.286.02:50:24.36#ibcon#wrote, iclass 29, count 2 2006.286.02:50:24.36#ibcon#about to read 3, iclass 29, count 2 2006.286.02:50:24.39#ibcon#read 3, iclass 29, count 2 2006.286.02:50:24.39#ibcon#about to read 4, iclass 29, count 2 2006.286.02:50:24.39#ibcon#read 4, iclass 29, count 2 2006.286.02:50:24.39#ibcon#about to read 5, iclass 29, count 2 2006.286.02:50:24.39#ibcon#read 5, iclass 29, count 2 2006.286.02:50:24.39#ibcon#about to read 6, iclass 29, count 2 2006.286.02:50:24.39#ibcon#read 6, iclass 29, count 2 2006.286.02:50:24.39#ibcon#end of sib2, iclass 29, count 2 2006.286.02:50:24.39#ibcon#*after write, iclass 29, count 2 2006.286.02:50:24.39#ibcon#*before return 0, iclass 29, count 2 2006.286.02:50:24.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:50:24.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.02:50:24.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.02:50:24.39#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:24.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:50:24.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:50:24.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:50:24.53#ibcon#enter wrdev, iclass 29, count 0 2006.286.02:50:24.53#ibcon#first serial, iclass 29, count 0 2006.286.02:50:24.53#ibcon#enter sib2, iclass 29, count 0 2006.286.02:50:24.53#ibcon#flushed, iclass 29, count 0 2006.286.02:50:24.53#ibcon#about to write, iclass 29, count 0 2006.286.02:50:24.53#ibcon#wrote, iclass 29, count 0 2006.286.02:50:24.53#ibcon#about to read 3, iclass 29, count 0 2006.286.02:50:24.54#ibcon#read 3, iclass 29, count 0 2006.286.02:50:24.54#ibcon#about to read 4, iclass 29, count 0 2006.286.02:50:24.54#ibcon#read 4, iclass 29, count 0 2006.286.02:50:24.54#ibcon#about to read 5, iclass 29, count 0 2006.286.02:50:24.54#ibcon#read 5, iclass 29, count 0 2006.286.02:50:24.54#ibcon#about to read 6, iclass 29, count 0 2006.286.02:50:24.54#ibcon#read 6, iclass 29, count 0 2006.286.02:50:24.54#ibcon#end of sib2, iclass 29, count 0 2006.286.02:50:24.54#ibcon#*mode == 0, iclass 29, count 0 2006.286.02:50:24.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.02:50:24.54#ibcon#[27=USB\r\n] 2006.286.02:50:24.54#ibcon#*before write, iclass 29, count 0 2006.286.02:50:24.54#ibcon#enter sib2, iclass 29, count 0 2006.286.02:50:24.54#ibcon#flushed, iclass 29, count 0 2006.286.02:50:24.54#ibcon#about to write, iclass 29, count 0 2006.286.02:50:24.54#ibcon#wrote, iclass 29, count 0 2006.286.02:50:24.54#ibcon#about to read 3, iclass 29, count 0 2006.286.02:50:24.57#ibcon#read 3, iclass 29, count 0 2006.286.02:50:24.57#ibcon#about to read 4, iclass 29, count 0 2006.286.02:50:24.57#ibcon#read 4, iclass 29, count 0 2006.286.02:50:24.57#ibcon#about to read 5, iclass 29, count 0 2006.286.02:50:24.57#ibcon#read 5, iclass 29, count 0 2006.286.02:50:24.57#ibcon#about to read 6, iclass 29, count 0 2006.286.02:50:24.57#ibcon#read 6, iclass 29, count 0 2006.286.02:50:24.57#ibcon#end of sib2, iclass 29, count 0 2006.286.02:50:24.57#ibcon#*after write, iclass 29, count 0 2006.286.02:50:24.57#ibcon#*before return 0, iclass 29, count 0 2006.286.02:50:24.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:50:24.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.02:50:24.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.02:50:24.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.02:50:24.57$vck44/vblo=5,709.99 2006.286.02:50:24.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.02:50:24.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.02:50:24.57#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:24.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:50:24.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:50:24.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:50:24.57#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:50:24.57#ibcon#first serial, iclass 31, count 0 2006.286.02:50:24.57#ibcon#enter sib2, iclass 31, count 0 2006.286.02:50:24.57#ibcon#flushed, iclass 31, count 0 2006.286.02:50:24.57#ibcon#about to write, iclass 31, count 0 2006.286.02:50:24.57#ibcon#wrote, iclass 31, count 0 2006.286.02:50:24.57#ibcon#about to read 3, iclass 31, count 0 2006.286.02:50:24.59#ibcon#read 3, iclass 31, count 0 2006.286.02:50:24.59#ibcon#about to read 4, iclass 31, count 0 2006.286.02:50:24.59#ibcon#read 4, iclass 31, count 0 2006.286.02:50:24.59#ibcon#about to read 5, iclass 31, count 0 2006.286.02:50:24.59#ibcon#read 5, iclass 31, count 0 2006.286.02:50:24.59#ibcon#about to read 6, iclass 31, count 0 2006.286.02:50:24.59#ibcon#read 6, iclass 31, count 0 2006.286.02:50:24.59#ibcon#end of sib2, iclass 31, count 0 2006.286.02:50:24.59#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:50:24.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:50:24.59#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.02:50:24.59#ibcon#*before write, iclass 31, count 0 2006.286.02:50:24.59#ibcon#enter sib2, iclass 31, count 0 2006.286.02:50:24.59#ibcon#flushed, iclass 31, count 0 2006.286.02:50:24.59#ibcon#about to write, iclass 31, count 0 2006.286.02:50:24.59#ibcon#wrote, iclass 31, count 0 2006.286.02:50:24.59#ibcon#about to read 3, iclass 31, count 0 2006.286.02:50:24.63#ibcon#read 3, iclass 31, count 0 2006.286.02:50:24.63#ibcon#about to read 4, iclass 31, count 0 2006.286.02:50:24.63#ibcon#read 4, iclass 31, count 0 2006.286.02:50:24.63#ibcon#about to read 5, iclass 31, count 0 2006.286.02:50:24.63#ibcon#read 5, iclass 31, count 0 2006.286.02:50:24.63#ibcon#about to read 6, iclass 31, count 0 2006.286.02:50:24.63#ibcon#read 6, iclass 31, count 0 2006.286.02:50:24.63#ibcon#end of sib2, iclass 31, count 0 2006.286.02:50:24.63#ibcon#*after write, iclass 31, count 0 2006.286.02:50:24.63#ibcon#*before return 0, iclass 31, count 0 2006.286.02:50:24.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:50:24.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:50:24.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:50:24.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:50:24.63$vck44/vb=5,4 2006.286.02:50:24.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.02:50:24.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.02:50:24.63#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:24.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:50:24.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:50:24.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:50:24.69#ibcon#enter wrdev, iclass 33, count 2 2006.286.02:50:24.69#ibcon#first serial, iclass 33, count 2 2006.286.02:50:24.69#ibcon#enter sib2, iclass 33, count 2 2006.286.02:50:24.69#ibcon#flushed, iclass 33, count 2 2006.286.02:50:24.69#ibcon#about to write, iclass 33, count 2 2006.286.02:50:24.69#ibcon#wrote, iclass 33, count 2 2006.286.02:50:24.69#ibcon#about to read 3, iclass 33, count 2 2006.286.02:50:24.71#ibcon#read 3, iclass 33, count 2 2006.286.02:50:24.71#ibcon#about to read 4, iclass 33, count 2 2006.286.02:50:24.71#ibcon#read 4, iclass 33, count 2 2006.286.02:50:24.71#ibcon#about to read 5, iclass 33, count 2 2006.286.02:50:24.71#ibcon#read 5, iclass 33, count 2 2006.286.02:50:24.71#ibcon#about to read 6, iclass 33, count 2 2006.286.02:50:24.71#ibcon#read 6, iclass 33, count 2 2006.286.02:50:24.71#ibcon#end of sib2, iclass 33, count 2 2006.286.02:50:24.71#ibcon#*mode == 0, iclass 33, count 2 2006.286.02:50:24.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.02:50:24.71#ibcon#[27=AT05-04\r\n] 2006.286.02:50:24.71#ibcon#*before write, iclass 33, count 2 2006.286.02:50:24.71#ibcon#enter sib2, iclass 33, count 2 2006.286.02:50:24.71#ibcon#flushed, iclass 33, count 2 2006.286.02:50:24.71#ibcon#about to write, iclass 33, count 2 2006.286.02:50:24.71#ibcon#wrote, iclass 33, count 2 2006.286.02:50:24.71#ibcon#about to read 3, iclass 33, count 2 2006.286.02:50:24.74#ibcon#read 3, iclass 33, count 2 2006.286.02:50:24.74#ibcon#about to read 4, iclass 33, count 2 2006.286.02:50:24.74#ibcon#read 4, iclass 33, count 2 2006.286.02:50:24.74#ibcon#about to read 5, iclass 33, count 2 2006.286.02:50:24.74#ibcon#read 5, iclass 33, count 2 2006.286.02:50:24.74#ibcon#about to read 6, iclass 33, count 2 2006.286.02:50:24.74#ibcon#read 6, iclass 33, count 2 2006.286.02:50:24.74#ibcon#end of sib2, iclass 33, count 2 2006.286.02:50:24.74#ibcon#*after write, iclass 33, count 2 2006.286.02:50:24.74#ibcon#*before return 0, iclass 33, count 2 2006.286.02:50:24.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:50:24.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.02:50:24.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.02:50:24.74#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:24.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:50:24.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:50:24.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:50:24.86#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:50:24.86#ibcon#first serial, iclass 33, count 0 2006.286.02:50:24.86#ibcon#enter sib2, iclass 33, count 0 2006.286.02:50:24.86#ibcon#flushed, iclass 33, count 0 2006.286.02:50:24.86#ibcon#about to write, iclass 33, count 0 2006.286.02:50:24.86#ibcon#wrote, iclass 33, count 0 2006.286.02:50:24.86#ibcon#about to read 3, iclass 33, count 0 2006.286.02:50:24.88#ibcon#read 3, iclass 33, count 0 2006.286.02:50:24.88#ibcon#about to read 4, iclass 33, count 0 2006.286.02:50:24.88#ibcon#read 4, iclass 33, count 0 2006.286.02:50:24.88#ibcon#about to read 5, iclass 33, count 0 2006.286.02:50:24.88#ibcon#read 5, iclass 33, count 0 2006.286.02:50:24.88#ibcon#about to read 6, iclass 33, count 0 2006.286.02:50:24.88#ibcon#read 6, iclass 33, count 0 2006.286.02:50:24.88#ibcon#end of sib2, iclass 33, count 0 2006.286.02:50:24.88#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:50:24.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:50:24.88#ibcon#[27=USB\r\n] 2006.286.02:50:24.88#ibcon#*before write, iclass 33, count 0 2006.286.02:50:24.88#ibcon#enter sib2, iclass 33, count 0 2006.286.02:50:24.88#ibcon#flushed, iclass 33, count 0 2006.286.02:50:24.88#ibcon#about to write, iclass 33, count 0 2006.286.02:50:24.88#ibcon#wrote, iclass 33, count 0 2006.286.02:50:24.88#ibcon#about to read 3, iclass 33, count 0 2006.286.02:50:24.91#ibcon#read 3, iclass 33, count 0 2006.286.02:50:24.91#ibcon#about to read 4, iclass 33, count 0 2006.286.02:50:24.91#ibcon#read 4, iclass 33, count 0 2006.286.02:50:24.91#ibcon#about to read 5, iclass 33, count 0 2006.286.02:50:24.91#ibcon#read 5, iclass 33, count 0 2006.286.02:50:24.91#ibcon#about to read 6, iclass 33, count 0 2006.286.02:50:24.91#ibcon#read 6, iclass 33, count 0 2006.286.02:50:24.91#ibcon#end of sib2, iclass 33, count 0 2006.286.02:50:24.91#ibcon#*after write, iclass 33, count 0 2006.286.02:50:24.91#ibcon#*before return 0, iclass 33, count 0 2006.286.02:50:24.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:50:24.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.02:50:24.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:50:24.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:50:24.91$vck44/vblo=6,719.99 2006.286.02:50:24.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.02:50:24.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.02:50:24.91#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:24.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:50:24.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:50:24.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:50:24.91#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:50:24.91#ibcon#first serial, iclass 35, count 0 2006.286.02:50:24.91#ibcon#enter sib2, iclass 35, count 0 2006.286.02:50:24.91#ibcon#flushed, iclass 35, count 0 2006.286.02:50:24.91#ibcon#about to write, iclass 35, count 0 2006.286.02:50:24.91#ibcon#wrote, iclass 35, count 0 2006.286.02:50:24.91#ibcon#about to read 3, iclass 35, count 0 2006.286.02:50:24.93#ibcon#read 3, iclass 35, count 0 2006.286.02:50:24.93#ibcon#about to read 4, iclass 35, count 0 2006.286.02:50:24.93#ibcon#read 4, iclass 35, count 0 2006.286.02:50:24.93#ibcon#about to read 5, iclass 35, count 0 2006.286.02:50:24.93#ibcon#read 5, iclass 35, count 0 2006.286.02:50:24.93#ibcon#about to read 6, iclass 35, count 0 2006.286.02:50:24.93#ibcon#read 6, iclass 35, count 0 2006.286.02:50:24.93#ibcon#end of sib2, iclass 35, count 0 2006.286.02:50:24.93#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:50:24.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:50:24.93#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.02:50:24.93#ibcon#*before write, iclass 35, count 0 2006.286.02:50:24.93#ibcon#enter sib2, iclass 35, count 0 2006.286.02:50:24.93#ibcon#flushed, iclass 35, count 0 2006.286.02:50:24.93#ibcon#about to write, iclass 35, count 0 2006.286.02:50:24.93#ibcon#wrote, iclass 35, count 0 2006.286.02:50:24.93#ibcon#about to read 3, iclass 35, count 0 2006.286.02:50:24.97#ibcon#read 3, iclass 35, count 0 2006.286.02:50:24.97#ibcon#about to read 4, iclass 35, count 0 2006.286.02:50:24.97#ibcon#read 4, iclass 35, count 0 2006.286.02:50:24.97#ibcon#about to read 5, iclass 35, count 0 2006.286.02:50:24.97#ibcon#read 5, iclass 35, count 0 2006.286.02:50:24.97#ibcon#about to read 6, iclass 35, count 0 2006.286.02:50:24.97#ibcon#read 6, iclass 35, count 0 2006.286.02:50:24.97#ibcon#end of sib2, iclass 35, count 0 2006.286.02:50:24.97#ibcon#*after write, iclass 35, count 0 2006.286.02:50:24.97#ibcon#*before return 0, iclass 35, count 0 2006.286.02:50:24.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:50:24.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.02:50:24.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:50:24.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:50:24.97$vck44/vb=6,3 2006.286.02:50:24.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.02:50:24.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.02:50:24.97#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:24.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:50:25.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:50:25.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:50:25.03#ibcon#enter wrdev, iclass 37, count 2 2006.286.02:50:25.03#ibcon#first serial, iclass 37, count 2 2006.286.02:50:25.03#ibcon#enter sib2, iclass 37, count 2 2006.286.02:50:25.03#ibcon#flushed, iclass 37, count 2 2006.286.02:50:25.03#ibcon#about to write, iclass 37, count 2 2006.286.02:50:25.03#ibcon#wrote, iclass 37, count 2 2006.286.02:50:25.03#ibcon#about to read 3, iclass 37, count 2 2006.286.02:50:25.05#ibcon#read 3, iclass 37, count 2 2006.286.02:50:25.05#ibcon#about to read 4, iclass 37, count 2 2006.286.02:50:25.05#ibcon#read 4, iclass 37, count 2 2006.286.02:50:25.05#ibcon#about to read 5, iclass 37, count 2 2006.286.02:50:25.05#ibcon#read 5, iclass 37, count 2 2006.286.02:50:25.05#ibcon#about to read 6, iclass 37, count 2 2006.286.02:50:25.05#ibcon#read 6, iclass 37, count 2 2006.286.02:50:25.05#ibcon#end of sib2, iclass 37, count 2 2006.286.02:50:25.05#ibcon#*mode == 0, iclass 37, count 2 2006.286.02:50:25.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.02:50:25.05#ibcon#[27=AT06-03\r\n] 2006.286.02:50:25.05#ibcon#*before write, iclass 37, count 2 2006.286.02:50:25.05#ibcon#enter sib2, iclass 37, count 2 2006.286.02:50:25.05#ibcon#flushed, iclass 37, count 2 2006.286.02:50:25.05#ibcon#about to write, iclass 37, count 2 2006.286.02:50:25.05#ibcon#wrote, iclass 37, count 2 2006.286.02:50:25.05#ibcon#about to read 3, iclass 37, count 2 2006.286.02:50:25.08#ibcon#read 3, iclass 37, count 2 2006.286.02:50:25.08#ibcon#about to read 4, iclass 37, count 2 2006.286.02:50:25.08#ibcon#read 4, iclass 37, count 2 2006.286.02:50:25.08#ibcon#about to read 5, iclass 37, count 2 2006.286.02:50:25.08#ibcon#read 5, iclass 37, count 2 2006.286.02:50:25.08#ibcon#about to read 6, iclass 37, count 2 2006.286.02:50:25.08#ibcon#read 6, iclass 37, count 2 2006.286.02:50:25.08#ibcon#end of sib2, iclass 37, count 2 2006.286.02:50:25.08#ibcon#*after write, iclass 37, count 2 2006.286.02:50:25.08#ibcon#*before return 0, iclass 37, count 2 2006.286.02:50:25.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:50:25.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.02:50:25.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.02:50:25.08#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:25.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:50:25.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:50:25.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:50:25.20#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:50:25.20#ibcon#first serial, iclass 37, count 0 2006.286.02:50:25.20#ibcon#enter sib2, iclass 37, count 0 2006.286.02:50:25.20#ibcon#flushed, iclass 37, count 0 2006.286.02:50:25.20#ibcon#about to write, iclass 37, count 0 2006.286.02:50:25.20#ibcon#wrote, iclass 37, count 0 2006.286.02:50:25.20#ibcon#about to read 3, iclass 37, count 0 2006.286.02:50:25.22#ibcon#read 3, iclass 37, count 0 2006.286.02:50:25.22#ibcon#about to read 4, iclass 37, count 0 2006.286.02:50:25.22#ibcon#read 4, iclass 37, count 0 2006.286.02:50:25.22#ibcon#about to read 5, iclass 37, count 0 2006.286.02:50:25.22#ibcon#read 5, iclass 37, count 0 2006.286.02:50:25.22#ibcon#about to read 6, iclass 37, count 0 2006.286.02:50:25.22#ibcon#read 6, iclass 37, count 0 2006.286.02:50:25.22#ibcon#end of sib2, iclass 37, count 0 2006.286.02:50:25.22#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:50:25.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:50:25.22#ibcon#[27=USB\r\n] 2006.286.02:50:25.22#ibcon#*before write, iclass 37, count 0 2006.286.02:50:25.22#ibcon#enter sib2, iclass 37, count 0 2006.286.02:50:25.22#ibcon#flushed, iclass 37, count 0 2006.286.02:50:25.22#ibcon#about to write, iclass 37, count 0 2006.286.02:50:25.22#ibcon#wrote, iclass 37, count 0 2006.286.02:50:25.22#ibcon#about to read 3, iclass 37, count 0 2006.286.02:50:25.25#ibcon#read 3, iclass 37, count 0 2006.286.02:50:25.25#ibcon#about to read 4, iclass 37, count 0 2006.286.02:50:25.25#ibcon#read 4, iclass 37, count 0 2006.286.02:50:25.25#ibcon#about to read 5, iclass 37, count 0 2006.286.02:50:25.25#ibcon#read 5, iclass 37, count 0 2006.286.02:50:25.25#ibcon#about to read 6, iclass 37, count 0 2006.286.02:50:25.25#ibcon#read 6, iclass 37, count 0 2006.286.02:50:25.25#ibcon#end of sib2, iclass 37, count 0 2006.286.02:50:25.25#ibcon#*after write, iclass 37, count 0 2006.286.02:50:25.25#ibcon#*before return 0, iclass 37, count 0 2006.286.02:50:25.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:50:25.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.02:50:25.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:50:25.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:50:25.25$vck44/vblo=7,734.99 2006.286.02:50:25.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.02:50:25.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.02:50:25.25#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:25.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:50:25.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:50:25.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:50:25.25#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:50:25.25#ibcon#first serial, iclass 39, count 0 2006.286.02:50:25.25#ibcon#enter sib2, iclass 39, count 0 2006.286.02:50:25.25#ibcon#flushed, iclass 39, count 0 2006.286.02:50:25.25#ibcon#about to write, iclass 39, count 0 2006.286.02:50:25.25#ibcon#wrote, iclass 39, count 0 2006.286.02:50:25.25#ibcon#about to read 3, iclass 39, count 0 2006.286.02:50:25.27#ibcon#read 3, iclass 39, count 0 2006.286.02:50:25.27#ibcon#about to read 4, iclass 39, count 0 2006.286.02:50:25.27#ibcon#read 4, iclass 39, count 0 2006.286.02:50:25.27#ibcon#about to read 5, iclass 39, count 0 2006.286.02:50:25.27#ibcon#read 5, iclass 39, count 0 2006.286.02:50:25.27#ibcon#about to read 6, iclass 39, count 0 2006.286.02:50:25.27#ibcon#read 6, iclass 39, count 0 2006.286.02:50:25.27#ibcon#end of sib2, iclass 39, count 0 2006.286.02:50:25.27#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:50:25.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:50:25.27#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.02:50:25.27#ibcon#*before write, iclass 39, count 0 2006.286.02:50:25.27#ibcon#enter sib2, iclass 39, count 0 2006.286.02:50:25.27#ibcon#flushed, iclass 39, count 0 2006.286.02:50:25.27#ibcon#about to write, iclass 39, count 0 2006.286.02:50:25.27#ibcon#wrote, iclass 39, count 0 2006.286.02:50:25.27#ibcon#about to read 3, iclass 39, count 0 2006.286.02:50:25.31#ibcon#read 3, iclass 39, count 0 2006.286.02:50:25.31#ibcon#about to read 4, iclass 39, count 0 2006.286.02:50:25.31#ibcon#read 4, iclass 39, count 0 2006.286.02:50:25.31#ibcon#about to read 5, iclass 39, count 0 2006.286.02:50:25.31#ibcon#read 5, iclass 39, count 0 2006.286.02:50:25.31#ibcon#about to read 6, iclass 39, count 0 2006.286.02:50:25.31#ibcon#read 6, iclass 39, count 0 2006.286.02:50:25.31#ibcon#end of sib2, iclass 39, count 0 2006.286.02:50:25.31#ibcon#*after write, iclass 39, count 0 2006.286.02:50:25.31#ibcon#*before return 0, iclass 39, count 0 2006.286.02:50:25.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:50:25.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.02:50:25.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:50:25.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:50:25.31$vck44/vb=7,4 2006.286.02:50:25.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.02:50:25.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.02:50:25.31#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:25.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:50:25.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:50:25.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:50:25.37#ibcon#enter wrdev, iclass 3, count 2 2006.286.02:50:25.37#ibcon#first serial, iclass 3, count 2 2006.286.02:50:25.37#ibcon#enter sib2, iclass 3, count 2 2006.286.02:50:25.37#ibcon#flushed, iclass 3, count 2 2006.286.02:50:25.37#ibcon#about to write, iclass 3, count 2 2006.286.02:50:25.37#ibcon#wrote, iclass 3, count 2 2006.286.02:50:25.37#ibcon#about to read 3, iclass 3, count 2 2006.286.02:50:25.39#ibcon#read 3, iclass 3, count 2 2006.286.02:50:25.39#ibcon#about to read 4, iclass 3, count 2 2006.286.02:50:25.39#ibcon#read 4, iclass 3, count 2 2006.286.02:50:25.39#ibcon#about to read 5, iclass 3, count 2 2006.286.02:50:25.39#ibcon#read 5, iclass 3, count 2 2006.286.02:50:25.39#ibcon#about to read 6, iclass 3, count 2 2006.286.02:50:25.39#ibcon#read 6, iclass 3, count 2 2006.286.02:50:25.39#ibcon#end of sib2, iclass 3, count 2 2006.286.02:50:25.39#ibcon#*mode == 0, iclass 3, count 2 2006.286.02:50:25.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.02:50:25.39#ibcon#[27=AT07-04\r\n] 2006.286.02:50:25.39#ibcon#*before write, iclass 3, count 2 2006.286.02:50:25.39#ibcon#enter sib2, iclass 3, count 2 2006.286.02:50:25.39#ibcon#flushed, iclass 3, count 2 2006.286.02:50:25.39#ibcon#about to write, iclass 3, count 2 2006.286.02:50:25.39#ibcon#wrote, iclass 3, count 2 2006.286.02:50:25.39#ibcon#about to read 3, iclass 3, count 2 2006.286.02:50:25.42#ibcon#read 3, iclass 3, count 2 2006.286.02:50:25.42#ibcon#about to read 4, iclass 3, count 2 2006.286.02:50:25.42#ibcon#read 4, iclass 3, count 2 2006.286.02:50:25.42#ibcon#about to read 5, iclass 3, count 2 2006.286.02:50:25.42#ibcon#read 5, iclass 3, count 2 2006.286.02:50:25.42#ibcon#about to read 6, iclass 3, count 2 2006.286.02:50:25.42#ibcon#read 6, iclass 3, count 2 2006.286.02:50:25.42#ibcon#end of sib2, iclass 3, count 2 2006.286.02:50:25.42#ibcon#*after write, iclass 3, count 2 2006.286.02:50:25.42#ibcon#*before return 0, iclass 3, count 2 2006.286.02:50:25.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:50:25.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.02:50:25.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.02:50:25.42#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:25.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:50:25.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:50:25.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:50:25.54#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:50:25.54#ibcon#first serial, iclass 3, count 0 2006.286.02:50:25.54#ibcon#enter sib2, iclass 3, count 0 2006.286.02:50:25.54#ibcon#flushed, iclass 3, count 0 2006.286.02:50:25.54#ibcon#about to write, iclass 3, count 0 2006.286.02:50:25.54#ibcon#wrote, iclass 3, count 0 2006.286.02:50:25.54#ibcon#about to read 3, iclass 3, count 0 2006.286.02:50:25.56#ibcon#read 3, iclass 3, count 0 2006.286.02:50:25.56#ibcon#about to read 4, iclass 3, count 0 2006.286.02:50:25.56#ibcon#read 4, iclass 3, count 0 2006.286.02:50:25.56#ibcon#about to read 5, iclass 3, count 0 2006.286.02:50:25.56#ibcon#read 5, iclass 3, count 0 2006.286.02:50:25.56#ibcon#about to read 6, iclass 3, count 0 2006.286.02:50:25.56#ibcon#read 6, iclass 3, count 0 2006.286.02:50:25.56#ibcon#end of sib2, iclass 3, count 0 2006.286.02:50:25.56#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:50:25.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:50:25.56#ibcon#[27=USB\r\n] 2006.286.02:50:25.56#ibcon#*before write, iclass 3, count 0 2006.286.02:50:25.56#ibcon#enter sib2, iclass 3, count 0 2006.286.02:50:25.56#ibcon#flushed, iclass 3, count 0 2006.286.02:50:25.56#ibcon#about to write, iclass 3, count 0 2006.286.02:50:25.56#ibcon#wrote, iclass 3, count 0 2006.286.02:50:25.56#ibcon#about to read 3, iclass 3, count 0 2006.286.02:50:25.59#ibcon#read 3, iclass 3, count 0 2006.286.02:50:25.59#ibcon#about to read 4, iclass 3, count 0 2006.286.02:50:25.59#ibcon#read 4, iclass 3, count 0 2006.286.02:50:25.59#ibcon#about to read 5, iclass 3, count 0 2006.286.02:50:25.59#ibcon#read 5, iclass 3, count 0 2006.286.02:50:25.59#ibcon#about to read 6, iclass 3, count 0 2006.286.02:50:25.59#ibcon#read 6, iclass 3, count 0 2006.286.02:50:25.59#ibcon#end of sib2, iclass 3, count 0 2006.286.02:50:25.59#ibcon#*after write, iclass 3, count 0 2006.286.02:50:25.59#ibcon#*before return 0, iclass 3, count 0 2006.286.02:50:25.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:50:25.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.02:50:25.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:50:25.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:50:25.59$vck44/vblo=8,744.99 2006.286.02:50:25.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.02:50:25.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.02:50:25.59#ibcon#ireg 17 cls_cnt 0 2006.286.02:50:25.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:50:25.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:50:25.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:50:25.59#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:50:25.59#ibcon#first serial, iclass 5, count 0 2006.286.02:50:25.59#ibcon#enter sib2, iclass 5, count 0 2006.286.02:50:25.59#ibcon#flushed, iclass 5, count 0 2006.286.02:50:25.59#ibcon#about to write, iclass 5, count 0 2006.286.02:50:25.59#ibcon#wrote, iclass 5, count 0 2006.286.02:50:25.59#ibcon#about to read 3, iclass 5, count 0 2006.286.02:50:25.61#ibcon#read 3, iclass 5, count 0 2006.286.02:50:25.61#ibcon#about to read 4, iclass 5, count 0 2006.286.02:50:25.61#ibcon#read 4, iclass 5, count 0 2006.286.02:50:25.61#ibcon#about to read 5, iclass 5, count 0 2006.286.02:50:25.61#ibcon#read 5, iclass 5, count 0 2006.286.02:50:25.61#ibcon#about to read 6, iclass 5, count 0 2006.286.02:50:25.61#ibcon#read 6, iclass 5, count 0 2006.286.02:50:25.61#ibcon#end of sib2, iclass 5, count 0 2006.286.02:50:25.61#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:50:25.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:50:25.61#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.02:50:25.61#ibcon#*before write, iclass 5, count 0 2006.286.02:50:25.61#ibcon#enter sib2, iclass 5, count 0 2006.286.02:50:25.61#ibcon#flushed, iclass 5, count 0 2006.286.02:50:25.61#ibcon#about to write, iclass 5, count 0 2006.286.02:50:25.61#ibcon#wrote, iclass 5, count 0 2006.286.02:50:25.61#ibcon#about to read 3, iclass 5, count 0 2006.286.02:50:25.65#ibcon#read 3, iclass 5, count 0 2006.286.02:50:25.65#ibcon#about to read 4, iclass 5, count 0 2006.286.02:50:25.65#ibcon#read 4, iclass 5, count 0 2006.286.02:50:25.65#ibcon#about to read 5, iclass 5, count 0 2006.286.02:50:25.65#ibcon#read 5, iclass 5, count 0 2006.286.02:50:25.65#ibcon#about to read 6, iclass 5, count 0 2006.286.02:50:25.65#ibcon#read 6, iclass 5, count 0 2006.286.02:50:25.65#ibcon#end of sib2, iclass 5, count 0 2006.286.02:50:25.65#ibcon#*after write, iclass 5, count 0 2006.286.02:50:25.65#ibcon#*before return 0, iclass 5, count 0 2006.286.02:50:25.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:50:25.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.02:50:25.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:50:25.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:50:25.65$vck44/vb=8,4 2006.286.02:50:25.65#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.02:50:25.65#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.02:50:25.65#ibcon#ireg 11 cls_cnt 2 2006.286.02:50:25.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:50:25.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:50:25.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:50:25.71#ibcon#enter wrdev, iclass 7, count 2 2006.286.02:50:25.71#ibcon#first serial, iclass 7, count 2 2006.286.02:50:25.71#ibcon#enter sib2, iclass 7, count 2 2006.286.02:50:25.71#ibcon#flushed, iclass 7, count 2 2006.286.02:50:25.71#ibcon#about to write, iclass 7, count 2 2006.286.02:50:25.71#ibcon#wrote, iclass 7, count 2 2006.286.02:50:25.71#ibcon#about to read 3, iclass 7, count 2 2006.286.02:50:25.73#ibcon#read 3, iclass 7, count 2 2006.286.02:50:25.73#ibcon#about to read 4, iclass 7, count 2 2006.286.02:50:25.73#ibcon#read 4, iclass 7, count 2 2006.286.02:50:25.73#ibcon#about to read 5, iclass 7, count 2 2006.286.02:50:25.73#ibcon#read 5, iclass 7, count 2 2006.286.02:50:25.73#ibcon#about to read 6, iclass 7, count 2 2006.286.02:50:25.73#ibcon#read 6, iclass 7, count 2 2006.286.02:50:25.73#ibcon#end of sib2, iclass 7, count 2 2006.286.02:50:25.73#ibcon#*mode == 0, iclass 7, count 2 2006.286.02:50:25.73#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.02:50:25.73#ibcon#[27=AT08-04\r\n] 2006.286.02:50:25.73#ibcon#*before write, iclass 7, count 2 2006.286.02:50:25.73#ibcon#enter sib2, iclass 7, count 2 2006.286.02:50:25.73#ibcon#flushed, iclass 7, count 2 2006.286.02:50:25.73#ibcon#about to write, iclass 7, count 2 2006.286.02:50:25.73#ibcon#wrote, iclass 7, count 2 2006.286.02:50:25.73#ibcon#about to read 3, iclass 7, count 2 2006.286.02:50:25.76#ibcon#read 3, iclass 7, count 2 2006.286.02:50:25.76#ibcon#about to read 4, iclass 7, count 2 2006.286.02:50:25.76#ibcon#read 4, iclass 7, count 2 2006.286.02:50:25.76#ibcon#about to read 5, iclass 7, count 2 2006.286.02:50:25.76#ibcon#read 5, iclass 7, count 2 2006.286.02:50:25.76#ibcon#about to read 6, iclass 7, count 2 2006.286.02:50:25.76#ibcon#read 6, iclass 7, count 2 2006.286.02:50:25.76#ibcon#end of sib2, iclass 7, count 2 2006.286.02:50:25.76#ibcon#*after write, iclass 7, count 2 2006.286.02:50:25.76#ibcon#*before return 0, iclass 7, count 2 2006.286.02:50:25.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:50:25.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.02:50:25.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.02:50:25.76#ibcon#ireg 7 cls_cnt 0 2006.286.02:50:25.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:50:25.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:50:25.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:50:25.88#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:50:25.88#ibcon#first serial, iclass 7, count 0 2006.286.02:50:25.88#ibcon#enter sib2, iclass 7, count 0 2006.286.02:50:25.88#ibcon#flushed, iclass 7, count 0 2006.286.02:50:25.88#ibcon#about to write, iclass 7, count 0 2006.286.02:50:25.88#ibcon#wrote, iclass 7, count 0 2006.286.02:50:25.88#ibcon#about to read 3, iclass 7, count 0 2006.286.02:50:25.90#ibcon#read 3, iclass 7, count 0 2006.286.02:50:25.90#ibcon#about to read 4, iclass 7, count 0 2006.286.02:50:25.90#ibcon#read 4, iclass 7, count 0 2006.286.02:50:25.90#ibcon#about to read 5, iclass 7, count 0 2006.286.02:50:25.90#ibcon#read 5, iclass 7, count 0 2006.286.02:50:25.90#ibcon#about to read 6, iclass 7, count 0 2006.286.02:50:25.90#ibcon#read 6, iclass 7, count 0 2006.286.02:50:25.90#ibcon#end of sib2, iclass 7, count 0 2006.286.02:50:25.90#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:50:25.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:50:25.90#ibcon#[27=USB\r\n] 2006.286.02:50:25.90#ibcon#*before write, iclass 7, count 0 2006.286.02:50:25.90#ibcon#enter sib2, iclass 7, count 0 2006.286.02:50:25.90#ibcon#flushed, iclass 7, count 0 2006.286.02:50:25.90#ibcon#about to write, iclass 7, count 0 2006.286.02:50:25.90#ibcon#wrote, iclass 7, count 0 2006.286.02:50:25.90#ibcon#about to read 3, iclass 7, count 0 2006.286.02:50:25.93#ibcon#read 3, iclass 7, count 0 2006.286.02:50:25.93#ibcon#about to read 4, iclass 7, count 0 2006.286.02:50:25.93#ibcon#read 4, iclass 7, count 0 2006.286.02:50:25.93#ibcon#about to read 5, iclass 7, count 0 2006.286.02:50:25.93#ibcon#read 5, iclass 7, count 0 2006.286.02:50:25.93#ibcon#about to read 6, iclass 7, count 0 2006.286.02:50:25.93#ibcon#read 6, iclass 7, count 0 2006.286.02:50:25.93#ibcon#end of sib2, iclass 7, count 0 2006.286.02:50:25.93#ibcon#*after write, iclass 7, count 0 2006.286.02:50:25.93#ibcon#*before return 0, iclass 7, count 0 2006.286.02:50:25.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:50:25.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.02:50:25.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:50:25.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:50:25.93$vck44/vabw=wide 2006.286.02:50:25.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.02:50:25.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.02:50:25.93#ibcon#ireg 8 cls_cnt 0 2006.286.02:50:25.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:50:25.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:50:25.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:50:25.93#ibcon#enter wrdev, iclass 11, count 0 2006.286.02:50:25.93#ibcon#first serial, iclass 11, count 0 2006.286.02:50:25.93#ibcon#enter sib2, iclass 11, count 0 2006.286.02:50:25.93#ibcon#flushed, iclass 11, count 0 2006.286.02:50:25.93#ibcon#about to write, iclass 11, count 0 2006.286.02:50:25.93#ibcon#wrote, iclass 11, count 0 2006.286.02:50:25.93#ibcon#about to read 3, iclass 11, count 0 2006.286.02:50:25.95#ibcon#read 3, iclass 11, count 0 2006.286.02:50:25.95#ibcon#about to read 4, iclass 11, count 0 2006.286.02:50:25.95#ibcon#read 4, iclass 11, count 0 2006.286.02:50:25.95#ibcon#about to read 5, iclass 11, count 0 2006.286.02:50:25.95#ibcon#read 5, iclass 11, count 0 2006.286.02:50:25.95#ibcon#about to read 6, iclass 11, count 0 2006.286.02:50:25.95#ibcon#read 6, iclass 11, count 0 2006.286.02:50:25.95#ibcon#end of sib2, iclass 11, count 0 2006.286.02:50:25.95#ibcon#*mode == 0, iclass 11, count 0 2006.286.02:50:25.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.02:50:25.95#ibcon#[25=BW32\r\n] 2006.286.02:50:25.95#ibcon#*before write, iclass 11, count 0 2006.286.02:50:25.95#ibcon#enter sib2, iclass 11, count 0 2006.286.02:50:25.95#ibcon#flushed, iclass 11, count 0 2006.286.02:50:25.95#ibcon#about to write, iclass 11, count 0 2006.286.02:50:25.95#ibcon#wrote, iclass 11, count 0 2006.286.02:50:25.95#ibcon#about to read 3, iclass 11, count 0 2006.286.02:50:25.98#ibcon#read 3, iclass 11, count 0 2006.286.02:50:25.98#ibcon#about to read 4, iclass 11, count 0 2006.286.02:50:25.98#ibcon#read 4, iclass 11, count 0 2006.286.02:50:25.98#ibcon#about to read 5, iclass 11, count 0 2006.286.02:50:25.98#ibcon#read 5, iclass 11, count 0 2006.286.02:50:25.98#ibcon#about to read 6, iclass 11, count 0 2006.286.02:50:25.98#ibcon#read 6, iclass 11, count 0 2006.286.02:50:25.98#ibcon#end of sib2, iclass 11, count 0 2006.286.02:50:25.98#ibcon#*after write, iclass 11, count 0 2006.286.02:50:25.98#ibcon#*before return 0, iclass 11, count 0 2006.286.02:50:25.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:50:25.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.02:50:25.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.02:50:25.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.02:50:25.98$vck44/vbbw=wide 2006.286.02:50:25.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.02:50:25.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.02:50:25.98#ibcon#ireg 8 cls_cnt 0 2006.286.02:50:25.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:50:26.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:50:26.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:50:26.05#ibcon#enter wrdev, iclass 13, count 0 2006.286.02:50:26.05#ibcon#first serial, iclass 13, count 0 2006.286.02:50:26.05#ibcon#enter sib2, iclass 13, count 0 2006.286.02:50:26.05#ibcon#flushed, iclass 13, count 0 2006.286.02:50:26.05#ibcon#about to write, iclass 13, count 0 2006.286.02:50:26.05#ibcon#wrote, iclass 13, count 0 2006.286.02:50:26.05#ibcon#about to read 3, iclass 13, count 0 2006.286.02:50:26.07#ibcon#read 3, iclass 13, count 0 2006.286.02:50:26.07#ibcon#about to read 4, iclass 13, count 0 2006.286.02:50:26.07#ibcon#read 4, iclass 13, count 0 2006.286.02:50:26.07#ibcon#about to read 5, iclass 13, count 0 2006.286.02:50:26.07#ibcon#read 5, iclass 13, count 0 2006.286.02:50:26.07#ibcon#about to read 6, iclass 13, count 0 2006.286.02:50:26.07#ibcon#read 6, iclass 13, count 0 2006.286.02:50:26.07#ibcon#end of sib2, iclass 13, count 0 2006.286.02:50:26.07#ibcon#*mode == 0, iclass 13, count 0 2006.286.02:50:26.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.02:50:26.07#ibcon#[27=BW32\r\n] 2006.286.02:50:26.07#ibcon#*before write, iclass 13, count 0 2006.286.02:50:26.07#ibcon#enter sib2, iclass 13, count 0 2006.286.02:50:26.07#ibcon#flushed, iclass 13, count 0 2006.286.02:50:26.07#ibcon#about to write, iclass 13, count 0 2006.286.02:50:26.07#ibcon#wrote, iclass 13, count 0 2006.286.02:50:26.07#ibcon#about to read 3, iclass 13, count 0 2006.286.02:50:26.10#ibcon#read 3, iclass 13, count 0 2006.286.02:50:26.10#ibcon#about to read 4, iclass 13, count 0 2006.286.02:50:26.10#ibcon#read 4, iclass 13, count 0 2006.286.02:50:26.10#ibcon#about to read 5, iclass 13, count 0 2006.286.02:50:26.10#ibcon#read 5, iclass 13, count 0 2006.286.02:50:26.10#ibcon#about to read 6, iclass 13, count 0 2006.286.02:50:26.10#ibcon#read 6, iclass 13, count 0 2006.286.02:50:26.10#ibcon#end of sib2, iclass 13, count 0 2006.286.02:50:26.10#ibcon#*after write, iclass 13, count 0 2006.286.02:50:26.10#ibcon#*before return 0, iclass 13, count 0 2006.286.02:50:26.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:50:26.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:50:26.10#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.02:50:26.10#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.02:50:26.10$setupk4/ifdk4 2006.286.02:50:26.10$ifdk4/lo= 2006.286.02:50:26.10$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.02:50:26.10$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.02:50:26.10$ifdk4/patch= 2006.286.02:50:26.10$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.02:50:26.10$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.02:50:26.10$setupk4/!*+20s 2006.286.02:50:30.99#abcon#<5=/04 3.0 5.9 21.31 791015.6\r\n> 2006.286.02:50:31.01#abcon#{5=INTERFACE CLEAR} 2006.286.02:50:31.07#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:50:39.58$setupk4/"tpicd 2006.286.02:50:39.58$setupk4/echo=off 2006.286.02:50:39.58$setupk4/xlog=off 2006.286.02:50:39.58:!2006.286.02:53:11 2006.286.02:51:03.14#trakl#Source acquired 2006.286.02:51:05.14#flagr#flagr/antenna,acquired 2006.286.02:53:11.00:preob 2006.286.02:53:12.14/onsource/TRACKING 2006.286.02:53:12.14:!2006.286.02:53:21 2006.286.02:53:21.00:"tape 2006.286.02:53:21.00:"st=record 2006.286.02:53:21.00:data_valid=on 2006.286.02:53:21.00:midob 2006.286.02:53:21.14/onsource/TRACKING 2006.286.02:53:21.14/wx/21.36,1015.6,79 2006.286.02:53:21.35/cable/+6.5014E-03 2006.286.02:53:22.44/va/01,07,usb,yes,33,36 2006.286.02:53:22.44/va/02,06,usb,yes,33,33 2006.286.02:53:22.44/va/03,07,usb,yes,32,34 2006.286.02:53:22.44/va/04,06,usb,yes,34,35 2006.286.02:53:22.44/va/05,03,usb,yes,33,34 2006.286.02:53:22.44/va/06,04,usb,yes,30,30 2006.286.02:53:22.44/va/07,04,usb,yes,31,31 2006.286.02:53:22.44/va/08,03,usb,yes,31,38 2006.286.02:53:22.67/valo/01,524.99,yes,locked 2006.286.02:53:22.67/valo/02,534.99,yes,locked 2006.286.02:53:22.67/valo/03,564.99,yes,locked 2006.286.02:53:22.67/valo/04,624.99,yes,locked 2006.286.02:53:22.67/valo/05,734.99,yes,locked 2006.286.02:53:22.67/valo/06,814.99,yes,locked 2006.286.02:53:22.67/valo/07,864.99,yes,locked 2006.286.02:53:22.67/valo/08,884.99,yes,locked 2006.286.02:53:23.76/vb/01,04,usb,yes,31,29 2006.286.02:53:23.76/vb/02,05,usb,yes,29,29 2006.286.02:53:23.76/vb/03,04,usb,yes,30,33 2006.286.02:53:23.76/vb/04,05,usb,yes,30,29 2006.286.02:53:23.76/vb/05,04,usb,yes,27,29 2006.286.02:53:23.76/vb/06,03,usb,yes,38,34 2006.286.02:53:23.76/vb/07,04,usb,yes,31,31 2006.286.02:53:23.76/vb/08,04,usb,yes,28,32 2006.286.02:53:23.99/vblo/01,629.99,yes,locked 2006.286.02:53:23.99/vblo/02,634.99,yes,locked 2006.286.02:53:23.99/vblo/03,649.99,yes,locked 2006.286.02:53:23.99/vblo/04,679.99,yes,locked 2006.286.02:53:23.99/vblo/05,709.99,yes,locked 2006.286.02:53:23.99/vblo/06,719.99,yes,locked 2006.286.02:53:23.99/vblo/07,734.99,yes,locked 2006.286.02:53:23.99/vblo/08,744.99,yes,locked 2006.286.02:53:24.14/vabw/8 2006.286.02:53:24.29/vbbw/8 2006.286.02:53:24.50/xfe/off,on,12.2 2006.286.02:53:24.87/ifatt/23,28,28,28 2006.286.02:53:25.07/fmout-gps/S +2.62E-07 2006.286.02:53:25.09:!2006.286.02:58:51 2006.286.02:58:51.00:data_valid=off 2006.286.02:58:51.00:"et 2006.286.02:58:51.00:!+3s 2006.286.02:58:54.01:"tape 2006.286.02:58:54.01:postob 2006.286.02:58:54.15/cable/+6.4996E-03 2006.286.02:58:54.15/wx/21.46,1015.5,79 2006.286.02:58:55.07/fmout-gps/S +2.66E-07 2006.286.02:58:55.07:scan_name=286-0303,jd0610,80 2006.286.02:58:55.07:source=3c274,123049.42,122328.0,2000.0,ccw 2006.286.02:58:55.13#flagr#flagr/antenna,new-source 2006.286.02:58:56.13:checkk5 2006.286.02:58:56.58/chk_autoobs//k5ts1/ autoobs is running! 2006.286.02:58:56.99/chk_autoobs//k5ts2/ autoobs is running! 2006.286.02:58:57.54/chk_autoobs//k5ts3/ autoobs is running! 2006.286.02:58:57.97/chk_autoobs//k5ts4/ autoobs is running! 2006.286.02:58:58.36/chk_obsdata//k5ts1/T2860253??a.dat file size is correct (nominal:1320MB, actual:1320MB). 2006.286.02:58:58.80/chk_obsdata//k5ts2/T2860253??b.dat file size is correct (nominal:1320MB, actual:1320MB). 2006.286.02:58:59.38/chk_obsdata//k5ts3/T2860253??c.dat file size is correct (nominal:1320MB, actual:1320MB). 2006.286.02:58:59.92/chk_obsdata//k5ts4/T2860253??d.dat file size is correct (nominal:1320MB, actual:1320MB). 2006.286.02:59:00.77/k5log//k5ts1_log_newline 2006.286.02:59:01.50/k5log//k5ts2_log_newline 2006.286.02:59:02.27/k5log//k5ts3_log_newline 2006.286.02:59:03.11/k5log//k5ts4_log_newline 2006.286.02:59:03.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.02:59:03.13:setupk4=1 2006.286.02:59:03.13$setupk4/echo=on 2006.286.02:59:03.13$setupk4/pcalon 2006.286.02:59:03.13$pcalon/"no phase cal control is implemented here 2006.286.02:59:03.13$setupk4/"tpicd=stop 2006.286.02:59:03.13$setupk4/"rec=synch_on 2006.286.02:59:03.13$setupk4/"rec_mode=128 2006.286.02:59:03.13$setupk4/!* 2006.286.02:59:03.13$setupk4/recpk4 2006.286.02:59:03.13$recpk4/recpatch= 2006.286.02:59:03.14$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.02:59:03.14$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.02:59:03.14$setupk4/vck44 2006.286.02:59:03.14$vck44/valo=1,524.99 2006.286.02:59:03.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.02:59:03.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.02:59:03.14#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:03.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:59:03.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:59:03.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:59:03.14#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:59:03.14#ibcon#first serial, iclass 37, count 0 2006.286.02:59:03.14#ibcon#enter sib2, iclass 37, count 0 2006.286.02:59:03.14#ibcon#flushed, iclass 37, count 0 2006.286.02:59:03.14#ibcon#about to write, iclass 37, count 0 2006.286.02:59:03.14#ibcon#wrote, iclass 37, count 0 2006.286.02:59:03.14#ibcon#about to read 3, iclass 37, count 0 2006.286.02:59:03.16#ibcon#read 3, iclass 37, count 0 2006.286.02:59:03.16#ibcon#about to read 4, iclass 37, count 0 2006.286.02:59:03.16#ibcon#read 4, iclass 37, count 0 2006.286.02:59:03.16#ibcon#about to read 5, iclass 37, count 0 2006.286.02:59:03.16#ibcon#read 5, iclass 37, count 0 2006.286.02:59:03.16#ibcon#about to read 6, iclass 37, count 0 2006.286.02:59:03.16#ibcon#read 6, iclass 37, count 0 2006.286.02:59:03.16#ibcon#end of sib2, iclass 37, count 0 2006.286.02:59:03.16#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:59:03.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:59:03.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.02:59:03.16#ibcon#*before write, iclass 37, count 0 2006.286.02:59:03.16#ibcon#enter sib2, iclass 37, count 0 2006.286.02:59:03.16#ibcon#flushed, iclass 37, count 0 2006.286.02:59:03.16#ibcon#about to write, iclass 37, count 0 2006.286.02:59:03.16#ibcon#wrote, iclass 37, count 0 2006.286.02:59:03.16#ibcon#about to read 3, iclass 37, count 0 2006.286.02:59:03.21#ibcon#read 3, iclass 37, count 0 2006.286.02:59:03.21#ibcon#about to read 4, iclass 37, count 0 2006.286.02:59:03.21#ibcon#read 4, iclass 37, count 0 2006.286.02:59:03.21#ibcon#about to read 5, iclass 37, count 0 2006.286.02:59:03.21#ibcon#read 5, iclass 37, count 0 2006.286.02:59:03.21#ibcon#about to read 6, iclass 37, count 0 2006.286.02:59:03.21#ibcon#read 6, iclass 37, count 0 2006.286.02:59:03.21#ibcon#end of sib2, iclass 37, count 0 2006.286.02:59:03.21#ibcon#*after write, iclass 37, count 0 2006.286.02:59:03.21#ibcon#*before return 0, iclass 37, count 0 2006.286.02:59:03.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:59:03.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:59:03.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:59:03.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:59:03.21$vck44/va=1,7 2006.286.02:59:03.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.02:59:03.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.02:59:03.21#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:03.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:59:03.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:59:03.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:59:03.21#ibcon#enter wrdev, iclass 39, count 2 2006.286.02:59:03.21#ibcon#first serial, iclass 39, count 2 2006.286.02:59:03.21#ibcon#enter sib2, iclass 39, count 2 2006.286.02:59:03.21#ibcon#flushed, iclass 39, count 2 2006.286.02:59:03.21#ibcon#about to write, iclass 39, count 2 2006.286.02:59:03.21#ibcon#wrote, iclass 39, count 2 2006.286.02:59:03.21#ibcon#about to read 3, iclass 39, count 2 2006.286.02:59:03.23#ibcon#read 3, iclass 39, count 2 2006.286.02:59:03.23#ibcon#about to read 4, iclass 39, count 2 2006.286.02:59:03.23#ibcon#read 4, iclass 39, count 2 2006.286.02:59:03.23#ibcon#about to read 5, iclass 39, count 2 2006.286.02:59:03.23#ibcon#read 5, iclass 39, count 2 2006.286.02:59:03.23#ibcon#about to read 6, iclass 39, count 2 2006.286.02:59:03.23#ibcon#read 6, iclass 39, count 2 2006.286.02:59:03.23#ibcon#end of sib2, iclass 39, count 2 2006.286.02:59:03.23#ibcon#*mode == 0, iclass 39, count 2 2006.286.02:59:03.23#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.02:59:03.23#ibcon#[25=AT01-07\r\n] 2006.286.02:59:03.23#ibcon#*before write, iclass 39, count 2 2006.286.02:59:03.23#ibcon#enter sib2, iclass 39, count 2 2006.286.02:59:03.23#ibcon#flushed, iclass 39, count 2 2006.286.02:59:03.23#ibcon#about to write, iclass 39, count 2 2006.286.02:59:03.23#ibcon#wrote, iclass 39, count 2 2006.286.02:59:03.23#ibcon#about to read 3, iclass 39, count 2 2006.286.02:59:03.26#ibcon#read 3, iclass 39, count 2 2006.286.02:59:03.26#ibcon#about to read 4, iclass 39, count 2 2006.286.02:59:03.26#ibcon#read 4, iclass 39, count 2 2006.286.02:59:03.26#ibcon#about to read 5, iclass 39, count 2 2006.286.02:59:03.26#ibcon#read 5, iclass 39, count 2 2006.286.02:59:03.26#ibcon#about to read 6, iclass 39, count 2 2006.286.02:59:03.26#ibcon#read 6, iclass 39, count 2 2006.286.02:59:03.26#ibcon#end of sib2, iclass 39, count 2 2006.286.02:59:03.26#ibcon#*after write, iclass 39, count 2 2006.286.02:59:03.26#ibcon#*before return 0, iclass 39, count 2 2006.286.02:59:03.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:59:03.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:59:03.26#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.02:59:03.26#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:03.26#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:59:03.38#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:59:03.38#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:59:03.38#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:59:03.38#ibcon#first serial, iclass 39, count 0 2006.286.02:59:03.38#ibcon#enter sib2, iclass 39, count 0 2006.286.02:59:03.38#ibcon#flushed, iclass 39, count 0 2006.286.02:59:03.38#ibcon#about to write, iclass 39, count 0 2006.286.02:59:03.38#ibcon#wrote, iclass 39, count 0 2006.286.02:59:03.38#ibcon#about to read 3, iclass 39, count 0 2006.286.02:59:03.40#ibcon#read 3, iclass 39, count 0 2006.286.02:59:03.40#ibcon#about to read 4, iclass 39, count 0 2006.286.02:59:03.40#ibcon#read 4, iclass 39, count 0 2006.286.02:59:03.40#ibcon#about to read 5, iclass 39, count 0 2006.286.02:59:03.40#ibcon#read 5, iclass 39, count 0 2006.286.02:59:03.40#ibcon#about to read 6, iclass 39, count 0 2006.286.02:59:03.40#ibcon#read 6, iclass 39, count 0 2006.286.02:59:03.40#ibcon#end of sib2, iclass 39, count 0 2006.286.02:59:03.40#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:59:03.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:59:03.40#ibcon#[25=USB\r\n] 2006.286.02:59:03.40#ibcon#*before write, iclass 39, count 0 2006.286.02:59:03.40#ibcon#enter sib2, iclass 39, count 0 2006.286.02:59:03.40#ibcon#flushed, iclass 39, count 0 2006.286.02:59:03.40#ibcon#about to write, iclass 39, count 0 2006.286.02:59:03.40#ibcon#wrote, iclass 39, count 0 2006.286.02:59:03.40#ibcon#about to read 3, iclass 39, count 0 2006.286.02:59:03.43#ibcon#read 3, iclass 39, count 0 2006.286.02:59:03.43#ibcon#about to read 4, iclass 39, count 0 2006.286.02:59:03.43#ibcon#read 4, iclass 39, count 0 2006.286.02:59:03.43#ibcon#about to read 5, iclass 39, count 0 2006.286.02:59:03.43#ibcon#read 5, iclass 39, count 0 2006.286.02:59:03.43#ibcon#about to read 6, iclass 39, count 0 2006.286.02:59:03.43#ibcon#read 6, iclass 39, count 0 2006.286.02:59:03.43#ibcon#end of sib2, iclass 39, count 0 2006.286.02:59:03.43#ibcon#*after write, iclass 39, count 0 2006.286.02:59:03.43#ibcon#*before return 0, iclass 39, count 0 2006.286.02:59:03.43#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:59:03.43#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:59:03.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:59:03.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:59:03.43$vck44/valo=2,534.99 2006.286.02:59:03.43#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.02:59:03.43#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.02:59:03.43#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:03.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:59:03.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:59:03.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:59:03.43#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:59:03.43#ibcon#first serial, iclass 3, count 0 2006.286.02:59:03.43#ibcon#enter sib2, iclass 3, count 0 2006.286.02:59:03.43#ibcon#flushed, iclass 3, count 0 2006.286.02:59:03.43#ibcon#about to write, iclass 3, count 0 2006.286.02:59:03.43#ibcon#wrote, iclass 3, count 0 2006.286.02:59:03.43#ibcon#about to read 3, iclass 3, count 0 2006.286.02:59:03.45#ibcon#read 3, iclass 3, count 0 2006.286.02:59:03.45#ibcon#about to read 4, iclass 3, count 0 2006.286.02:59:03.45#ibcon#read 4, iclass 3, count 0 2006.286.02:59:03.45#ibcon#about to read 5, iclass 3, count 0 2006.286.02:59:03.45#ibcon#read 5, iclass 3, count 0 2006.286.02:59:03.45#ibcon#about to read 6, iclass 3, count 0 2006.286.02:59:03.45#ibcon#read 6, iclass 3, count 0 2006.286.02:59:03.45#ibcon#end of sib2, iclass 3, count 0 2006.286.02:59:03.45#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:59:03.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:59:03.45#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.02:59:03.45#ibcon#*before write, iclass 3, count 0 2006.286.02:59:03.45#ibcon#enter sib2, iclass 3, count 0 2006.286.02:59:03.45#ibcon#flushed, iclass 3, count 0 2006.286.02:59:03.45#ibcon#about to write, iclass 3, count 0 2006.286.02:59:03.45#ibcon#wrote, iclass 3, count 0 2006.286.02:59:03.45#ibcon#about to read 3, iclass 3, count 0 2006.286.02:59:03.49#ibcon#read 3, iclass 3, count 0 2006.286.02:59:03.49#ibcon#about to read 4, iclass 3, count 0 2006.286.02:59:03.49#ibcon#read 4, iclass 3, count 0 2006.286.02:59:03.49#ibcon#about to read 5, iclass 3, count 0 2006.286.02:59:03.49#ibcon#read 5, iclass 3, count 0 2006.286.02:59:03.49#ibcon#about to read 6, iclass 3, count 0 2006.286.02:59:03.49#ibcon#read 6, iclass 3, count 0 2006.286.02:59:03.49#ibcon#end of sib2, iclass 3, count 0 2006.286.02:59:03.49#ibcon#*after write, iclass 3, count 0 2006.286.02:59:03.49#ibcon#*before return 0, iclass 3, count 0 2006.286.02:59:03.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:59:03.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:59:03.49#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:59:03.49#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:59:03.49$vck44/va=2,6 2006.286.02:59:03.49#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.02:59:03.49#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.02:59:03.49#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:03.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:59:03.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:59:03.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:59:03.55#ibcon#enter wrdev, iclass 5, count 2 2006.286.02:59:03.55#ibcon#first serial, iclass 5, count 2 2006.286.02:59:03.55#ibcon#enter sib2, iclass 5, count 2 2006.286.02:59:03.55#ibcon#flushed, iclass 5, count 2 2006.286.02:59:03.55#ibcon#about to write, iclass 5, count 2 2006.286.02:59:03.55#ibcon#wrote, iclass 5, count 2 2006.286.02:59:03.55#ibcon#about to read 3, iclass 5, count 2 2006.286.02:59:03.57#ibcon#read 3, iclass 5, count 2 2006.286.02:59:04.22#ibcon#about to read 4, iclass 5, count 2 2006.286.02:59:04.22#ibcon#read 4, iclass 5, count 2 2006.286.02:59:04.22#ibcon#about to read 5, iclass 5, count 2 2006.286.02:59:04.22#ibcon#read 5, iclass 5, count 2 2006.286.02:59:04.22#ibcon#about to read 6, iclass 5, count 2 2006.286.02:59:04.22#ibcon#read 6, iclass 5, count 2 2006.286.02:59:04.22#ibcon#end of sib2, iclass 5, count 2 2006.286.02:59:04.22#ibcon#*mode == 0, iclass 5, count 2 2006.286.02:59:04.22#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.02:59:04.22#ibcon#[25=AT02-06\r\n] 2006.286.02:59:04.22#ibcon#*before write, iclass 5, count 2 2006.286.02:59:04.22#ibcon#enter sib2, iclass 5, count 2 2006.286.02:59:04.22#ibcon#flushed, iclass 5, count 2 2006.286.02:59:04.22#ibcon#about to write, iclass 5, count 2 2006.286.02:59:04.22#ibcon#wrote, iclass 5, count 2 2006.286.02:59:04.22#ibcon#about to read 3, iclass 5, count 2 2006.286.02:59:04.25#ibcon#read 3, iclass 5, count 2 2006.286.02:59:04.25#ibcon#about to read 4, iclass 5, count 2 2006.286.02:59:04.25#ibcon#read 4, iclass 5, count 2 2006.286.02:59:04.25#ibcon#about to read 5, iclass 5, count 2 2006.286.02:59:04.25#ibcon#read 5, iclass 5, count 2 2006.286.02:59:04.25#ibcon#about to read 6, iclass 5, count 2 2006.286.02:59:04.25#ibcon#read 6, iclass 5, count 2 2006.286.02:59:04.25#ibcon#end of sib2, iclass 5, count 2 2006.286.02:59:04.25#ibcon#*after write, iclass 5, count 2 2006.286.02:59:04.25#ibcon#*before return 0, iclass 5, count 2 2006.286.02:59:04.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:59:04.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:59:04.25#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.02:59:04.25#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:04.25#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:59:04.37#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:59:04.37#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:59:04.37#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:59:04.37#ibcon#first serial, iclass 5, count 0 2006.286.02:59:04.37#ibcon#enter sib2, iclass 5, count 0 2006.286.02:59:04.37#ibcon#flushed, iclass 5, count 0 2006.286.02:59:04.37#ibcon#about to write, iclass 5, count 0 2006.286.02:59:04.37#ibcon#wrote, iclass 5, count 0 2006.286.02:59:04.37#ibcon#about to read 3, iclass 5, count 0 2006.286.02:59:04.39#ibcon#read 3, iclass 5, count 0 2006.286.02:59:04.39#ibcon#about to read 4, iclass 5, count 0 2006.286.02:59:04.39#ibcon#read 4, iclass 5, count 0 2006.286.02:59:04.39#ibcon#about to read 5, iclass 5, count 0 2006.286.02:59:04.39#ibcon#read 5, iclass 5, count 0 2006.286.02:59:04.39#ibcon#about to read 6, iclass 5, count 0 2006.286.02:59:04.39#ibcon#read 6, iclass 5, count 0 2006.286.02:59:04.39#ibcon#end of sib2, iclass 5, count 0 2006.286.02:59:04.39#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:59:04.39#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:59:04.39#ibcon#[25=USB\r\n] 2006.286.02:59:04.39#ibcon#*before write, iclass 5, count 0 2006.286.02:59:04.39#ibcon#enter sib2, iclass 5, count 0 2006.286.02:59:04.39#ibcon#flushed, iclass 5, count 0 2006.286.02:59:04.39#ibcon#about to write, iclass 5, count 0 2006.286.02:59:04.39#ibcon#wrote, iclass 5, count 0 2006.286.02:59:04.39#ibcon#about to read 3, iclass 5, count 0 2006.286.02:59:04.42#ibcon#read 3, iclass 5, count 0 2006.286.02:59:04.42#ibcon#about to read 4, iclass 5, count 0 2006.286.02:59:04.42#ibcon#read 4, iclass 5, count 0 2006.286.02:59:04.42#ibcon#about to read 5, iclass 5, count 0 2006.286.02:59:04.42#ibcon#read 5, iclass 5, count 0 2006.286.02:59:04.42#ibcon#about to read 6, iclass 5, count 0 2006.286.02:59:04.42#ibcon#read 6, iclass 5, count 0 2006.286.02:59:04.42#ibcon#end of sib2, iclass 5, count 0 2006.286.02:59:04.42#ibcon#*after write, iclass 5, count 0 2006.286.02:59:04.42#ibcon#*before return 0, iclass 5, count 0 2006.286.02:59:04.42#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:59:04.42#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:59:04.42#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:59:04.42#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:59:04.42$vck44/valo=3,564.99 2006.286.02:59:04.42#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.02:59:04.42#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.02:59:04.42#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:04.42#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:59:04.42#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:59:04.42#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:59:04.42#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:59:04.42#ibcon#first serial, iclass 7, count 0 2006.286.02:59:04.42#ibcon#enter sib2, iclass 7, count 0 2006.286.02:59:04.42#ibcon#flushed, iclass 7, count 0 2006.286.02:59:04.42#ibcon#about to write, iclass 7, count 0 2006.286.02:59:04.42#ibcon#wrote, iclass 7, count 0 2006.286.02:59:04.42#ibcon#about to read 3, iclass 7, count 0 2006.286.02:59:04.44#ibcon#read 3, iclass 7, count 0 2006.286.02:59:04.44#ibcon#about to read 4, iclass 7, count 0 2006.286.02:59:04.44#ibcon#read 4, iclass 7, count 0 2006.286.02:59:04.44#ibcon#about to read 5, iclass 7, count 0 2006.286.02:59:04.44#ibcon#read 5, iclass 7, count 0 2006.286.02:59:04.44#ibcon#about to read 6, iclass 7, count 0 2006.286.02:59:04.44#ibcon#read 6, iclass 7, count 0 2006.286.02:59:04.44#ibcon#end of sib2, iclass 7, count 0 2006.286.02:59:04.44#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:59:04.44#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:59:04.44#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.02:59:04.44#ibcon#*before write, iclass 7, count 0 2006.286.02:59:04.44#ibcon#enter sib2, iclass 7, count 0 2006.286.02:59:04.44#ibcon#flushed, iclass 7, count 0 2006.286.02:59:04.44#ibcon#about to write, iclass 7, count 0 2006.286.02:59:04.44#ibcon#wrote, iclass 7, count 0 2006.286.02:59:04.44#ibcon#about to read 3, iclass 7, count 0 2006.286.02:59:04.48#ibcon#read 3, iclass 7, count 0 2006.286.02:59:04.48#ibcon#about to read 4, iclass 7, count 0 2006.286.02:59:04.48#ibcon#read 4, iclass 7, count 0 2006.286.02:59:04.48#ibcon#about to read 5, iclass 7, count 0 2006.286.02:59:04.48#ibcon#read 5, iclass 7, count 0 2006.286.02:59:04.48#ibcon#about to read 6, iclass 7, count 0 2006.286.02:59:04.48#ibcon#read 6, iclass 7, count 0 2006.286.02:59:04.48#ibcon#end of sib2, iclass 7, count 0 2006.286.02:59:04.48#ibcon#*after write, iclass 7, count 0 2006.286.02:59:04.48#ibcon#*before return 0, iclass 7, count 0 2006.286.02:59:04.48#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:59:04.48#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:59:04.48#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:59:04.48#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:59:04.48$vck44/va=3,7 2006.286.02:59:04.48#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.02:59:04.48#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.02:59:04.48#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:04.48#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:59:04.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:59:04.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:59:04.54#ibcon#enter wrdev, iclass 11, count 2 2006.286.02:59:04.54#ibcon#first serial, iclass 11, count 2 2006.286.02:59:04.54#ibcon#enter sib2, iclass 11, count 2 2006.286.02:59:04.54#ibcon#flushed, iclass 11, count 2 2006.286.02:59:04.54#ibcon#about to write, iclass 11, count 2 2006.286.02:59:04.54#ibcon#wrote, iclass 11, count 2 2006.286.02:59:04.54#ibcon#about to read 3, iclass 11, count 2 2006.286.02:59:04.56#ibcon#read 3, iclass 11, count 2 2006.286.02:59:04.56#ibcon#about to read 4, iclass 11, count 2 2006.286.02:59:04.56#ibcon#read 4, iclass 11, count 2 2006.286.02:59:04.56#ibcon#about to read 5, iclass 11, count 2 2006.286.02:59:04.56#ibcon#read 5, iclass 11, count 2 2006.286.02:59:04.56#ibcon#about to read 6, iclass 11, count 2 2006.286.02:59:04.56#ibcon#read 6, iclass 11, count 2 2006.286.02:59:04.56#ibcon#end of sib2, iclass 11, count 2 2006.286.02:59:04.56#ibcon#*mode == 0, iclass 11, count 2 2006.286.02:59:04.56#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.02:59:04.56#ibcon#[25=AT03-07\r\n] 2006.286.02:59:04.56#ibcon#*before write, iclass 11, count 2 2006.286.02:59:04.56#ibcon#enter sib2, iclass 11, count 2 2006.286.02:59:04.56#ibcon#flushed, iclass 11, count 2 2006.286.02:59:04.56#ibcon#about to write, iclass 11, count 2 2006.286.02:59:04.56#ibcon#wrote, iclass 11, count 2 2006.286.02:59:04.56#ibcon#about to read 3, iclass 11, count 2 2006.286.02:59:04.59#ibcon#read 3, iclass 11, count 2 2006.286.02:59:04.59#ibcon#about to read 4, iclass 11, count 2 2006.286.02:59:04.59#ibcon#read 4, iclass 11, count 2 2006.286.02:59:04.59#ibcon#about to read 5, iclass 11, count 2 2006.286.02:59:04.59#ibcon#read 5, iclass 11, count 2 2006.286.02:59:04.59#ibcon#about to read 6, iclass 11, count 2 2006.286.02:59:04.59#ibcon#read 6, iclass 11, count 2 2006.286.02:59:04.59#ibcon#end of sib2, iclass 11, count 2 2006.286.02:59:04.59#ibcon#*after write, iclass 11, count 2 2006.286.02:59:04.59#ibcon#*before return 0, iclass 11, count 2 2006.286.02:59:04.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:59:04.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:59:04.59#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.02:59:04.59#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:04.59#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:59:04.71#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:59:04.71#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:59:04.71#ibcon#enter wrdev, iclass 11, count 0 2006.286.02:59:04.71#ibcon#first serial, iclass 11, count 0 2006.286.02:59:04.71#ibcon#enter sib2, iclass 11, count 0 2006.286.02:59:04.71#ibcon#flushed, iclass 11, count 0 2006.286.02:59:04.71#ibcon#about to write, iclass 11, count 0 2006.286.02:59:04.71#ibcon#wrote, iclass 11, count 0 2006.286.02:59:04.71#ibcon#about to read 3, iclass 11, count 0 2006.286.02:59:04.73#ibcon#read 3, iclass 11, count 0 2006.286.02:59:04.73#ibcon#about to read 4, iclass 11, count 0 2006.286.02:59:04.73#ibcon#read 4, iclass 11, count 0 2006.286.02:59:04.73#ibcon#about to read 5, iclass 11, count 0 2006.286.02:59:04.73#ibcon#read 5, iclass 11, count 0 2006.286.02:59:04.73#ibcon#about to read 6, iclass 11, count 0 2006.286.02:59:04.73#ibcon#read 6, iclass 11, count 0 2006.286.02:59:04.90#ibcon#end of sib2, iclass 11, count 0 2006.286.02:59:04.90#ibcon#*mode == 0, iclass 11, count 0 2006.286.02:59:04.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.02:59:04.90#ibcon#[25=USB\r\n] 2006.286.02:59:04.90#ibcon#*before write, iclass 11, count 0 2006.286.02:59:04.90#ibcon#enter sib2, iclass 11, count 0 2006.286.02:59:04.90#ibcon#flushed, iclass 11, count 0 2006.286.02:59:04.90#ibcon#about to write, iclass 11, count 0 2006.286.02:59:04.90#ibcon#wrote, iclass 11, count 0 2006.286.02:59:04.90#ibcon#about to read 3, iclass 11, count 0 2006.286.02:59:04.93#ibcon#read 3, iclass 11, count 0 2006.286.02:59:04.93#ibcon#about to read 4, iclass 11, count 0 2006.286.02:59:04.93#ibcon#read 4, iclass 11, count 0 2006.286.02:59:04.93#ibcon#about to read 5, iclass 11, count 0 2006.286.02:59:04.93#ibcon#read 5, iclass 11, count 0 2006.286.02:59:04.93#ibcon#about to read 6, iclass 11, count 0 2006.286.02:59:04.93#ibcon#read 6, iclass 11, count 0 2006.286.02:59:04.93#ibcon#end of sib2, iclass 11, count 0 2006.286.02:59:04.93#ibcon#*after write, iclass 11, count 0 2006.286.02:59:04.93#ibcon#*before return 0, iclass 11, count 0 2006.286.02:59:04.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:59:04.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:59:04.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.02:59:04.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.02:59:04.93$vck44/valo=4,624.99 2006.286.02:59:04.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.02:59:04.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.02:59:04.93#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:04.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:59:04.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:59:04.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:59:04.93#ibcon#enter wrdev, iclass 13, count 0 2006.286.02:59:04.93#ibcon#first serial, iclass 13, count 0 2006.286.02:59:04.93#ibcon#enter sib2, iclass 13, count 0 2006.286.02:59:04.93#ibcon#flushed, iclass 13, count 0 2006.286.02:59:04.93#ibcon#about to write, iclass 13, count 0 2006.286.02:59:04.93#ibcon#wrote, iclass 13, count 0 2006.286.02:59:04.93#ibcon#about to read 3, iclass 13, count 0 2006.286.02:59:04.95#ibcon#read 3, iclass 13, count 0 2006.286.02:59:04.95#ibcon#about to read 4, iclass 13, count 0 2006.286.02:59:04.95#ibcon#read 4, iclass 13, count 0 2006.286.02:59:04.95#ibcon#about to read 5, iclass 13, count 0 2006.286.02:59:04.95#ibcon#read 5, iclass 13, count 0 2006.286.02:59:04.95#ibcon#about to read 6, iclass 13, count 0 2006.286.02:59:04.95#ibcon#read 6, iclass 13, count 0 2006.286.02:59:04.95#ibcon#end of sib2, iclass 13, count 0 2006.286.02:59:04.95#ibcon#*mode == 0, iclass 13, count 0 2006.286.02:59:04.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.02:59:04.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.02:59:04.95#ibcon#*before write, iclass 13, count 0 2006.286.02:59:04.95#ibcon#enter sib2, iclass 13, count 0 2006.286.02:59:04.95#ibcon#flushed, iclass 13, count 0 2006.286.02:59:04.95#ibcon#about to write, iclass 13, count 0 2006.286.02:59:04.95#ibcon#wrote, iclass 13, count 0 2006.286.02:59:04.95#ibcon#about to read 3, iclass 13, count 0 2006.286.02:59:04.99#ibcon#read 3, iclass 13, count 0 2006.286.02:59:04.99#ibcon#about to read 4, iclass 13, count 0 2006.286.02:59:04.99#ibcon#read 4, iclass 13, count 0 2006.286.02:59:04.99#ibcon#about to read 5, iclass 13, count 0 2006.286.02:59:04.99#ibcon#read 5, iclass 13, count 0 2006.286.02:59:04.99#ibcon#about to read 6, iclass 13, count 0 2006.286.02:59:04.99#ibcon#read 6, iclass 13, count 0 2006.286.02:59:04.99#ibcon#end of sib2, iclass 13, count 0 2006.286.02:59:04.99#ibcon#*after write, iclass 13, count 0 2006.286.02:59:04.99#ibcon#*before return 0, iclass 13, count 0 2006.286.02:59:04.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:59:04.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:59:04.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.02:59:04.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.02:59:04.99$vck44/va=4,6 2006.286.02:59:04.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.02:59:04.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.02:59:04.99#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:04.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:59:05.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:59:05.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:59:05.05#ibcon#enter wrdev, iclass 15, count 2 2006.286.02:59:05.05#ibcon#first serial, iclass 15, count 2 2006.286.02:59:05.05#ibcon#enter sib2, iclass 15, count 2 2006.286.02:59:05.05#ibcon#flushed, iclass 15, count 2 2006.286.02:59:05.05#ibcon#about to write, iclass 15, count 2 2006.286.02:59:05.05#ibcon#wrote, iclass 15, count 2 2006.286.02:59:05.05#ibcon#about to read 3, iclass 15, count 2 2006.286.02:59:05.07#ibcon#read 3, iclass 15, count 2 2006.286.02:59:05.07#ibcon#about to read 4, iclass 15, count 2 2006.286.02:59:05.07#ibcon#read 4, iclass 15, count 2 2006.286.02:59:05.07#ibcon#about to read 5, iclass 15, count 2 2006.286.02:59:05.07#ibcon#read 5, iclass 15, count 2 2006.286.02:59:05.07#ibcon#about to read 6, iclass 15, count 2 2006.286.02:59:05.07#ibcon#read 6, iclass 15, count 2 2006.286.02:59:05.07#ibcon#end of sib2, iclass 15, count 2 2006.286.02:59:05.07#ibcon#*mode == 0, iclass 15, count 2 2006.286.02:59:05.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.02:59:05.07#ibcon#[25=AT04-06\r\n] 2006.286.02:59:05.07#ibcon#*before write, iclass 15, count 2 2006.286.02:59:05.07#ibcon#enter sib2, iclass 15, count 2 2006.286.02:59:05.07#ibcon#flushed, iclass 15, count 2 2006.286.02:59:05.07#ibcon#about to write, iclass 15, count 2 2006.286.02:59:05.07#ibcon#wrote, iclass 15, count 2 2006.286.02:59:05.07#ibcon#about to read 3, iclass 15, count 2 2006.286.02:59:05.10#ibcon#read 3, iclass 15, count 2 2006.286.02:59:05.10#ibcon#about to read 4, iclass 15, count 2 2006.286.02:59:05.10#ibcon#read 4, iclass 15, count 2 2006.286.02:59:05.10#ibcon#about to read 5, iclass 15, count 2 2006.286.02:59:05.10#ibcon#read 5, iclass 15, count 2 2006.286.02:59:05.10#ibcon#about to read 6, iclass 15, count 2 2006.286.02:59:05.10#ibcon#read 6, iclass 15, count 2 2006.286.02:59:05.10#ibcon#end of sib2, iclass 15, count 2 2006.286.02:59:05.10#ibcon#*after write, iclass 15, count 2 2006.286.02:59:05.10#ibcon#*before return 0, iclass 15, count 2 2006.286.02:59:05.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:59:05.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:59:05.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.02:59:05.10#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:05.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:59:05.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:59:05.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:59:05.22#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:59:05.22#ibcon#first serial, iclass 15, count 0 2006.286.02:59:05.22#ibcon#enter sib2, iclass 15, count 0 2006.286.02:59:05.22#ibcon#flushed, iclass 15, count 0 2006.286.02:59:05.22#ibcon#about to write, iclass 15, count 0 2006.286.02:59:05.22#ibcon#wrote, iclass 15, count 0 2006.286.02:59:05.22#ibcon#about to read 3, iclass 15, count 0 2006.286.02:59:05.24#ibcon#read 3, iclass 15, count 0 2006.286.02:59:05.24#ibcon#about to read 4, iclass 15, count 0 2006.286.02:59:05.24#ibcon#read 4, iclass 15, count 0 2006.286.02:59:05.24#ibcon#about to read 5, iclass 15, count 0 2006.286.02:59:05.24#ibcon#read 5, iclass 15, count 0 2006.286.02:59:05.24#ibcon#about to read 6, iclass 15, count 0 2006.286.02:59:05.24#ibcon#read 6, iclass 15, count 0 2006.286.02:59:05.24#ibcon#end of sib2, iclass 15, count 0 2006.286.02:59:05.24#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:59:05.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:59:05.24#ibcon#[25=USB\r\n] 2006.286.02:59:05.24#ibcon#*before write, iclass 15, count 0 2006.286.02:59:05.24#ibcon#enter sib2, iclass 15, count 0 2006.286.02:59:05.24#ibcon#flushed, iclass 15, count 0 2006.286.02:59:05.24#ibcon#about to write, iclass 15, count 0 2006.286.02:59:05.24#ibcon#wrote, iclass 15, count 0 2006.286.02:59:05.24#ibcon#about to read 3, iclass 15, count 0 2006.286.02:59:05.27#ibcon#read 3, iclass 15, count 0 2006.286.02:59:05.27#ibcon#about to read 4, iclass 15, count 0 2006.286.02:59:05.27#ibcon#read 4, iclass 15, count 0 2006.286.02:59:05.27#ibcon#about to read 5, iclass 15, count 0 2006.286.02:59:05.27#ibcon#read 5, iclass 15, count 0 2006.286.02:59:05.27#ibcon#about to read 6, iclass 15, count 0 2006.286.02:59:05.27#ibcon#read 6, iclass 15, count 0 2006.286.02:59:05.27#ibcon#end of sib2, iclass 15, count 0 2006.286.02:59:05.27#ibcon#*after write, iclass 15, count 0 2006.286.02:59:05.27#ibcon#*before return 0, iclass 15, count 0 2006.286.02:59:05.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:59:05.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:59:05.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:59:05.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:59:05.27$vck44/valo=5,734.99 2006.286.02:59:05.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.02:59:05.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.02:59:05.27#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:05.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:59:05.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:59:05.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:59:05.27#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:59:05.27#ibcon#first serial, iclass 17, count 0 2006.286.02:59:05.27#ibcon#enter sib2, iclass 17, count 0 2006.286.02:59:05.27#ibcon#flushed, iclass 17, count 0 2006.286.02:59:05.27#ibcon#about to write, iclass 17, count 0 2006.286.02:59:05.27#ibcon#wrote, iclass 17, count 0 2006.286.02:59:05.27#ibcon#about to read 3, iclass 17, count 0 2006.286.02:59:05.29#ibcon#read 3, iclass 17, count 0 2006.286.02:59:05.29#ibcon#about to read 4, iclass 17, count 0 2006.286.02:59:05.29#ibcon#read 4, iclass 17, count 0 2006.286.02:59:05.29#ibcon#about to read 5, iclass 17, count 0 2006.286.02:59:05.29#ibcon#read 5, iclass 17, count 0 2006.286.02:59:05.29#ibcon#about to read 6, iclass 17, count 0 2006.286.02:59:05.29#ibcon#read 6, iclass 17, count 0 2006.286.02:59:05.29#ibcon#end of sib2, iclass 17, count 0 2006.286.02:59:05.29#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:59:05.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:59:05.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.02:59:05.29#ibcon#*before write, iclass 17, count 0 2006.286.02:59:05.29#ibcon#enter sib2, iclass 17, count 0 2006.286.02:59:05.29#ibcon#flushed, iclass 17, count 0 2006.286.02:59:05.29#ibcon#about to write, iclass 17, count 0 2006.286.02:59:05.29#ibcon#wrote, iclass 17, count 0 2006.286.02:59:05.29#ibcon#about to read 3, iclass 17, count 0 2006.286.02:59:05.33#ibcon#read 3, iclass 17, count 0 2006.286.02:59:05.33#ibcon#about to read 4, iclass 17, count 0 2006.286.02:59:05.33#ibcon#read 4, iclass 17, count 0 2006.286.02:59:05.33#ibcon#about to read 5, iclass 17, count 0 2006.286.02:59:05.33#ibcon#read 5, iclass 17, count 0 2006.286.02:59:05.33#ibcon#about to read 6, iclass 17, count 0 2006.286.02:59:05.33#ibcon#read 6, iclass 17, count 0 2006.286.02:59:05.33#ibcon#end of sib2, iclass 17, count 0 2006.286.02:59:05.33#ibcon#*after write, iclass 17, count 0 2006.286.02:59:05.33#ibcon#*before return 0, iclass 17, count 0 2006.286.02:59:05.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:59:05.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:59:05.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:59:05.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:59:05.33$vck44/va=5,3 2006.286.02:59:05.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.02:59:05.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.02:59:05.33#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:05.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:59:05.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:59:05.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:59:05.39#ibcon#enter wrdev, iclass 19, count 2 2006.286.02:59:05.39#ibcon#first serial, iclass 19, count 2 2006.286.02:59:05.39#ibcon#enter sib2, iclass 19, count 2 2006.286.02:59:05.39#ibcon#flushed, iclass 19, count 2 2006.286.02:59:05.39#ibcon#about to write, iclass 19, count 2 2006.286.02:59:05.39#ibcon#wrote, iclass 19, count 2 2006.286.02:59:05.39#ibcon#about to read 3, iclass 19, count 2 2006.286.02:59:05.41#ibcon#read 3, iclass 19, count 2 2006.286.02:59:05.41#ibcon#about to read 4, iclass 19, count 2 2006.286.02:59:05.41#ibcon#read 4, iclass 19, count 2 2006.286.02:59:05.41#ibcon#about to read 5, iclass 19, count 2 2006.286.02:59:05.41#ibcon#read 5, iclass 19, count 2 2006.286.02:59:05.41#ibcon#about to read 6, iclass 19, count 2 2006.286.02:59:05.41#ibcon#read 6, iclass 19, count 2 2006.286.02:59:05.41#ibcon#end of sib2, iclass 19, count 2 2006.286.02:59:05.41#ibcon#*mode == 0, iclass 19, count 2 2006.286.02:59:05.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.02:59:05.41#ibcon#[25=AT05-03\r\n] 2006.286.02:59:05.41#ibcon#*before write, iclass 19, count 2 2006.286.02:59:05.41#ibcon#enter sib2, iclass 19, count 2 2006.286.02:59:05.41#ibcon#flushed, iclass 19, count 2 2006.286.02:59:05.41#ibcon#about to write, iclass 19, count 2 2006.286.02:59:05.41#ibcon#wrote, iclass 19, count 2 2006.286.02:59:05.41#ibcon#about to read 3, iclass 19, count 2 2006.286.02:59:05.44#ibcon#read 3, iclass 19, count 2 2006.286.02:59:05.44#ibcon#about to read 4, iclass 19, count 2 2006.286.02:59:05.44#ibcon#read 4, iclass 19, count 2 2006.286.02:59:05.44#ibcon#about to read 5, iclass 19, count 2 2006.286.02:59:05.44#ibcon#read 5, iclass 19, count 2 2006.286.02:59:05.44#ibcon#about to read 6, iclass 19, count 2 2006.286.02:59:05.44#ibcon#read 6, iclass 19, count 2 2006.286.02:59:05.44#ibcon#end of sib2, iclass 19, count 2 2006.286.02:59:05.44#ibcon#*after write, iclass 19, count 2 2006.286.02:59:05.44#ibcon#*before return 0, iclass 19, count 2 2006.286.02:59:05.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:59:05.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:59:05.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.02:59:05.44#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:05.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:59:05.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:59:05.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:59:05.56#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:59:05.56#ibcon#first serial, iclass 19, count 0 2006.286.02:59:05.56#ibcon#enter sib2, iclass 19, count 0 2006.286.02:59:05.56#ibcon#flushed, iclass 19, count 0 2006.286.02:59:05.56#ibcon#about to write, iclass 19, count 0 2006.286.02:59:05.56#ibcon#wrote, iclass 19, count 0 2006.286.02:59:05.56#ibcon#about to read 3, iclass 19, count 0 2006.286.02:59:05.58#ibcon#read 3, iclass 19, count 0 2006.286.02:59:05.58#ibcon#about to read 4, iclass 19, count 0 2006.286.02:59:05.58#ibcon#read 4, iclass 19, count 0 2006.286.02:59:05.58#ibcon#about to read 5, iclass 19, count 0 2006.286.02:59:05.58#ibcon#read 5, iclass 19, count 0 2006.286.02:59:05.58#ibcon#about to read 6, iclass 19, count 0 2006.286.02:59:05.58#ibcon#read 6, iclass 19, count 0 2006.286.02:59:05.58#ibcon#end of sib2, iclass 19, count 0 2006.286.02:59:05.58#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:59:05.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:59:05.58#ibcon#[25=USB\r\n] 2006.286.02:59:05.58#ibcon#*before write, iclass 19, count 0 2006.286.02:59:05.58#ibcon#enter sib2, iclass 19, count 0 2006.286.02:59:05.58#ibcon#flushed, iclass 19, count 0 2006.286.02:59:05.58#ibcon#about to write, iclass 19, count 0 2006.286.02:59:05.58#ibcon#wrote, iclass 19, count 0 2006.286.02:59:05.58#ibcon#about to read 3, iclass 19, count 0 2006.286.02:59:05.61#ibcon#read 3, iclass 19, count 0 2006.286.02:59:05.61#ibcon#about to read 4, iclass 19, count 0 2006.286.02:59:05.61#ibcon#read 4, iclass 19, count 0 2006.286.02:59:05.61#ibcon#about to read 5, iclass 19, count 0 2006.286.02:59:05.61#ibcon#read 5, iclass 19, count 0 2006.286.02:59:05.61#ibcon#about to read 6, iclass 19, count 0 2006.286.02:59:05.61#ibcon#read 6, iclass 19, count 0 2006.286.02:59:05.61#ibcon#end of sib2, iclass 19, count 0 2006.286.02:59:05.61#ibcon#*after write, iclass 19, count 0 2006.286.02:59:05.61#ibcon#*before return 0, iclass 19, count 0 2006.286.02:59:05.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:59:05.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:59:05.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:59:05.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:59:05.61$vck44/valo=6,814.99 2006.286.02:59:05.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.02:59:05.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.02:59:05.61#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:05.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:59:05.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:59:05.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:59:05.61#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:59:05.61#ibcon#first serial, iclass 21, count 0 2006.286.02:59:05.61#ibcon#enter sib2, iclass 21, count 0 2006.286.02:59:05.61#ibcon#flushed, iclass 21, count 0 2006.286.02:59:05.61#ibcon#about to write, iclass 21, count 0 2006.286.02:59:05.61#ibcon#wrote, iclass 21, count 0 2006.286.02:59:05.61#ibcon#about to read 3, iclass 21, count 0 2006.286.02:59:05.63#ibcon#read 3, iclass 21, count 0 2006.286.02:59:05.76#ibcon#about to read 4, iclass 21, count 0 2006.286.02:59:05.76#ibcon#read 4, iclass 21, count 0 2006.286.02:59:05.76#ibcon#about to read 5, iclass 21, count 0 2006.286.02:59:05.76#ibcon#read 5, iclass 21, count 0 2006.286.02:59:05.76#ibcon#about to read 6, iclass 21, count 0 2006.286.02:59:05.76#ibcon#read 6, iclass 21, count 0 2006.286.02:59:05.76#ibcon#end of sib2, iclass 21, count 0 2006.286.02:59:05.76#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:59:05.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:59:05.76#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.02:59:05.76#ibcon#*before write, iclass 21, count 0 2006.286.02:59:05.76#ibcon#enter sib2, iclass 21, count 0 2006.286.02:59:05.76#ibcon#flushed, iclass 21, count 0 2006.286.02:59:05.76#ibcon#about to write, iclass 21, count 0 2006.286.02:59:05.76#ibcon#wrote, iclass 21, count 0 2006.286.02:59:05.76#ibcon#about to read 3, iclass 21, count 0 2006.286.02:59:05.80#ibcon#read 3, iclass 21, count 0 2006.286.02:59:05.80#ibcon#about to read 4, iclass 21, count 0 2006.286.02:59:05.80#ibcon#read 4, iclass 21, count 0 2006.286.02:59:05.80#ibcon#about to read 5, iclass 21, count 0 2006.286.02:59:05.80#ibcon#read 5, iclass 21, count 0 2006.286.02:59:05.80#ibcon#about to read 6, iclass 21, count 0 2006.286.02:59:05.80#ibcon#read 6, iclass 21, count 0 2006.286.02:59:05.80#ibcon#end of sib2, iclass 21, count 0 2006.286.02:59:05.80#ibcon#*after write, iclass 21, count 0 2006.286.02:59:05.80#ibcon#*before return 0, iclass 21, count 0 2006.286.02:59:05.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:59:05.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:59:05.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:59:05.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:59:05.80$vck44/va=6,4 2006.286.02:59:05.80#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.02:59:05.80#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.02:59:05.80#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:05.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:59:05.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:59:05.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:59:05.80#ibcon#enter wrdev, iclass 23, count 2 2006.286.02:59:05.80#ibcon#first serial, iclass 23, count 2 2006.286.02:59:05.80#ibcon#enter sib2, iclass 23, count 2 2006.286.02:59:05.80#ibcon#flushed, iclass 23, count 2 2006.286.02:59:05.80#ibcon#about to write, iclass 23, count 2 2006.286.02:59:05.80#ibcon#wrote, iclass 23, count 2 2006.286.02:59:05.80#ibcon#about to read 3, iclass 23, count 2 2006.286.02:59:05.82#ibcon#read 3, iclass 23, count 2 2006.286.02:59:05.82#ibcon#about to read 4, iclass 23, count 2 2006.286.02:59:05.82#ibcon#read 4, iclass 23, count 2 2006.286.02:59:05.82#ibcon#about to read 5, iclass 23, count 2 2006.286.02:59:05.82#ibcon#read 5, iclass 23, count 2 2006.286.02:59:05.82#ibcon#about to read 6, iclass 23, count 2 2006.286.02:59:05.82#ibcon#read 6, iclass 23, count 2 2006.286.02:59:05.82#ibcon#end of sib2, iclass 23, count 2 2006.286.02:59:05.82#ibcon#*mode == 0, iclass 23, count 2 2006.286.02:59:05.82#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.02:59:05.82#ibcon#[25=AT06-04\r\n] 2006.286.02:59:05.82#ibcon#*before write, iclass 23, count 2 2006.286.02:59:05.82#ibcon#enter sib2, iclass 23, count 2 2006.286.02:59:05.82#ibcon#flushed, iclass 23, count 2 2006.286.02:59:05.82#ibcon#about to write, iclass 23, count 2 2006.286.02:59:05.82#ibcon#wrote, iclass 23, count 2 2006.286.02:59:05.82#ibcon#about to read 3, iclass 23, count 2 2006.286.02:59:05.85#ibcon#read 3, iclass 23, count 2 2006.286.02:59:05.85#ibcon#about to read 4, iclass 23, count 2 2006.286.02:59:05.85#ibcon#read 4, iclass 23, count 2 2006.286.02:59:05.85#ibcon#about to read 5, iclass 23, count 2 2006.286.02:59:05.85#ibcon#read 5, iclass 23, count 2 2006.286.02:59:05.85#ibcon#about to read 6, iclass 23, count 2 2006.286.02:59:05.85#ibcon#read 6, iclass 23, count 2 2006.286.02:59:05.85#ibcon#end of sib2, iclass 23, count 2 2006.286.02:59:05.85#ibcon#*after write, iclass 23, count 2 2006.286.02:59:05.85#ibcon#*before return 0, iclass 23, count 2 2006.286.02:59:05.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:59:05.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:59:05.85#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.02:59:05.85#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:05.85#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:59:05.97#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:59:05.97#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:59:05.97#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:59:05.97#ibcon#first serial, iclass 23, count 0 2006.286.02:59:05.97#ibcon#enter sib2, iclass 23, count 0 2006.286.02:59:05.97#ibcon#flushed, iclass 23, count 0 2006.286.02:59:05.97#ibcon#about to write, iclass 23, count 0 2006.286.02:59:05.97#ibcon#wrote, iclass 23, count 0 2006.286.02:59:05.97#ibcon#about to read 3, iclass 23, count 0 2006.286.02:59:05.99#ibcon#read 3, iclass 23, count 0 2006.286.02:59:05.99#ibcon#about to read 4, iclass 23, count 0 2006.286.02:59:05.99#ibcon#read 4, iclass 23, count 0 2006.286.02:59:05.99#ibcon#about to read 5, iclass 23, count 0 2006.286.02:59:05.99#ibcon#read 5, iclass 23, count 0 2006.286.02:59:05.99#ibcon#about to read 6, iclass 23, count 0 2006.286.02:59:05.99#ibcon#read 6, iclass 23, count 0 2006.286.02:59:05.99#ibcon#end of sib2, iclass 23, count 0 2006.286.02:59:05.99#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:59:05.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:59:05.99#ibcon#[25=USB\r\n] 2006.286.02:59:05.99#ibcon#*before write, iclass 23, count 0 2006.286.02:59:05.99#ibcon#enter sib2, iclass 23, count 0 2006.286.02:59:05.99#ibcon#flushed, iclass 23, count 0 2006.286.02:59:05.99#ibcon#about to write, iclass 23, count 0 2006.286.02:59:05.99#ibcon#wrote, iclass 23, count 0 2006.286.02:59:05.99#ibcon#about to read 3, iclass 23, count 0 2006.286.02:59:06.02#ibcon#read 3, iclass 23, count 0 2006.286.02:59:06.02#ibcon#about to read 4, iclass 23, count 0 2006.286.02:59:06.02#ibcon#read 4, iclass 23, count 0 2006.286.02:59:06.02#ibcon#about to read 5, iclass 23, count 0 2006.286.02:59:06.02#ibcon#read 5, iclass 23, count 0 2006.286.02:59:06.02#ibcon#about to read 6, iclass 23, count 0 2006.286.02:59:06.02#ibcon#read 6, iclass 23, count 0 2006.286.02:59:06.02#ibcon#end of sib2, iclass 23, count 0 2006.286.02:59:06.02#ibcon#*after write, iclass 23, count 0 2006.286.02:59:06.02#ibcon#*before return 0, iclass 23, count 0 2006.286.02:59:06.02#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:59:06.02#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:59:06.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:59:06.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:59:06.02$vck44/valo=7,864.99 2006.286.02:59:06.02#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.02:59:06.02#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.02:59:06.02#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:06.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:59:06.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:59:06.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:59:06.02#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:59:06.02#ibcon#first serial, iclass 25, count 0 2006.286.02:59:06.02#ibcon#enter sib2, iclass 25, count 0 2006.286.02:59:06.02#ibcon#flushed, iclass 25, count 0 2006.286.02:59:06.02#ibcon#about to write, iclass 25, count 0 2006.286.02:59:06.02#ibcon#wrote, iclass 25, count 0 2006.286.02:59:06.02#ibcon#about to read 3, iclass 25, count 0 2006.286.02:59:06.04#ibcon#read 3, iclass 25, count 0 2006.286.02:59:06.04#ibcon#about to read 4, iclass 25, count 0 2006.286.02:59:06.04#ibcon#read 4, iclass 25, count 0 2006.286.02:59:06.04#ibcon#about to read 5, iclass 25, count 0 2006.286.02:59:06.04#ibcon#read 5, iclass 25, count 0 2006.286.02:59:06.04#ibcon#about to read 6, iclass 25, count 0 2006.286.02:59:06.04#ibcon#read 6, iclass 25, count 0 2006.286.02:59:06.04#ibcon#end of sib2, iclass 25, count 0 2006.286.02:59:06.04#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:59:06.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:59:06.04#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.02:59:06.04#ibcon#*before write, iclass 25, count 0 2006.286.02:59:06.04#ibcon#enter sib2, iclass 25, count 0 2006.286.02:59:06.04#ibcon#flushed, iclass 25, count 0 2006.286.02:59:06.04#ibcon#about to write, iclass 25, count 0 2006.286.02:59:06.04#ibcon#wrote, iclass 25, count 0 2006.286.02:59:06.04#ibcon#about to read 3, iclass 25, count 0 2006.286.02:59:06.08#ibcon#read 3, iclass 25, count 0 2006.286.02:59:06.08#ibcon#about to read 4, iclass 25, count 0 2006.286.02:59:06.08#ibcon#read 4, iclass 25, count 0 2006.286.02:59:06.08#ibcon#about to read 5, iclass 25, count 0 2006.286.02:59:06.08#ibcon#read 5, iclass 25, count 0 2006.286.02:59:06.08#ibcon#about to read 6, iclass 25, count 0 2006.286.02:59:06.08#ibcon#read 6, iclass 25, count 0 2006.286.02:59:06.08#ibcon#end of sib2, iclass 25, count 0 2006.286.02:59:06.08#ibcon#*after write, iclass 25, count 0 2006.286.02:59:06.08#ibcon#*before return 0, iclass 25, count 0 2006.286.02:59:06.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:59:06.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:59:06.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:59:06.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:59:06.08$vck44/va=7,4 2006.286.02:59:06.08#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.02:59:06.08#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.02:59:06.08#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:06.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:59:06.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:59:06.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:59:06.14#ibcon#enter wrdev, iclass 27, count 2 2006.286.02:59:06.14#ibcon#first serial, iclass 27, count 2 2006.286.02:59:06.14#ibcon#enter sib2, iclass 27, count 2 2006.286.02:59:06.14#ibcon#flushed, iclass 27, count 2 2006.286.02:59:06.14#ibcon#about to write, iclass 27, count 2 2006.286.02:59:06.14#ibcon#wrote, iclass 27, count 2 2006.286.02:59:06.14#ibcon#about to read 3, iclass 27, count 2 2006.286.02:59:06.16#ibcon#read 3, iclass 27, count 2 2006.286.02:59:06.16#ibcon#about to read 4, iclass 27, count 2 2006.286.02:59:06.16#ibcon#read 4, iclass 27, count 2 2006.286.02:59:06.16#ibcon#about to read 5, iclass 27, count 2 2006.286.02:59:06.16#ibcon#read 5, iclass 27, count 2 2006.286.02:59:06.16#ibcon#about to read 6, iclass 27, count 2 2006.286.02:59:06.16#ibcon#read 6, iclass 27, count 2 2006.286.02:59:06.16#ibcon#end of sib2, iclass 27, count 2 2006.286.02:59:06.16#ibcon#*mode == 0, iclass 27, count 2 2006.286.02:59:06.16#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.02:59:06.16#ibcon#[25=AT07-04\r\n] 2006.286.02:59:06.16#ibcon#*before write, iclass 27, count 2 2006.286.02:59:06.16#ibcon#enter sib2, iclass 27, count 2 2006.286.02:59:06.16#ibcon#flushed, iclass 27, count 2 2006.286.02:59:06.16#ibcon#about to write, iclass 27, count 2 2006.286.02:59:06.16#ibcon#wrote, iclass 27, count 2 2006.286.02:59:06.16#ibcon#about to read 3, iclass 27, count 2 2006.286.02:59:06.19#ibcon#read 3, iclass 27, count 2 2006.286.02:59:06.19#ibcon#about to read 4, iclass 27, count 2 2006.286.02:59:06.19#ibcon#read 4, iclass 27, count 2 2006.286.02:59:06.19#ibcon#about to read 5, iclass 27, count 2 2006.286.02:59:06.19#ibcon#read 5, iclass 27, count 2 2006.286.02:59:06.19#ibcon#about to read 6, iclass 27, count 2 2006.286.02:59:06.19#ibcon#read 6, iclass 27, count 2 2006.286.02:59:06.19#ibcon#end of sib2, iclass 27, count 2 2006.286.02:59:06.19#ibcon#*after write, iclass 27, count 2 2006.286.02:59:06.19#ibcon#*before return 0, iclass 27, count 2 2006.286.02:59:06.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:59:06.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:59:06.19#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.02:59:06.19#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:06.19#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:59:06.31#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:59:06.31#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:59:06.31#ibcon#enter wrdev, iclass 27, count 0 2006.286.02:59:06.31#ibcon#first serial, iclass 27, count 0 2006.286.02:59:06.31#ibcon#enter sib2, iclass 27, count 0 2006.286.02:59:06.31#ibcon#flushed, iclass 27, count 0 2006.286.02:59:06.31#ibcon#about to write, iclass 27, count 0 2006.286.02:59:06.31#ibcon#wrote, iclass 27, count 0 2006.286.02:59:06.31#ibcon#about to read 3, iclass 27, count 0 2006.286.02:59:06.33#ibcon#read 3, iclass 27, count 0 2006.286.02:59:06.33#ibcon#about to read 4, iclass 27, count 0 2006.286.02:59:06.33#ibcon#read 4, iclass 27, count 0 2006.286.02:59:06.33#ibcon#about to read 5, iclass 27, count 0 2006.286.02:59:06.33#ibcon#read 5, iclass 27, count 0 2006.286.02:59:06.33#ibcon#about to read 6, iclass 27, count 0 2006.286.02:59:06.33#ibcon#read 6, iclass 27, count 0 2006.286.02:59:06.33#ibcon#end of sib2, iclass 27, count 0 2006.286.02:59:06.33#ibcon#*mode == 0, iclass 27, count 0 2006.286.02:59:06.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.02:59:06.33#ibcon#[25=USB\r\n] 2006.286.02:59:06.33#ibcon#*before write, iclass 27, count 0 2006.286.02:59:06.33#ibcon#enter sib2, iclass 27, count 0 2006.286.02:59:06.33#ibcon#flushed, iclass 27, count 0 2006.286.02:59:06.33#ibcon#about to write, iclass 27, count 0 2006.286.02:59:06.33#ibcon#wrote, iclass 27, count 0 2006.286.02:59:06.33#ibcon#about to read 3, iclass 27, count 0 2006.286.02:59:06.36#ibcon#read 3, iclass 27, count 0 2006.286.02:59:06.36#ibcon#about to read 4, iclass 27, count 0 2006.286.02:59:06.36#ibcon#read 4, iclass 27, count 0 2006.286.02:59:06.36#ibcon#about to read 5, iclass 27, count 0 2006.286.02:59:06.36#ibcon#read 5, iclass 27, count 0 2006.286.02:59:06.36#ibcon#about to read 6, iclass 27, count 0 2006.286.02:59:06.36#ibcon#read 6, iclass 27, count 0 2006.286.02:59:06.36#ibcon#end of sib2, iclass 27, count 0 2006.286.02:59:06.36#ibcon#*after write, iclass 27, count 0 2006.286.02:59:06.36#ibcon#*before return 0, iclass 27, count 0 2006.286.02:59:06.36#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:59:06.36#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:59:06.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.02:59:06.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.02:59:06.36$vck44/valo=8,884.99 2006.286.02:59:06.36#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.02:59:06.36#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.02:59:06.36#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:06.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:59:06.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:59:06.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:59:06.36#ibcon#enter wrdev, iclass 29, count 0 2006.286.02:59:06.36#ibcon#first serial, iclass 29, count 0 2006.286.02:59:06.36#ibcon#enter sib2, iclass 29, count 0 2006.286.02:59:06.36#ibcon#flushed, iclass 29, count 0 2006.286.02:59:06.36#ibcon#about to write, iclass 29, count 0 2006.286.02:59:06.36#ibcon#wrote, iclass 29, count 0 2006.286.02:59:06.36#ibcon#about to read 3, iclass 29, count 0 2006.286.02:59:06.38#ibcon#read 3, iclass 29, count 0 2006.286.02:59:06.38#ibcon#about to read 4, iclass 29, count 0 2006.286.02:59:06.38#ibcon#read 4, iclass 29, count 0 2006.286.02:59:06.38#ibcon#about to read 5, iclass 29, count 0 2006.286.02:59:06.38#ibcon#read 5, iclass 29, count 0 2006.286.02:59:06.38#ibcon#about to read 6, iclass 29, count 0 2006.286.02:59:06.38#ibcon#read 6, iclass 29, count 0 2006.286.02:59:06.38#ibcon#end of sib2, iclass 29, count 0 2006.286.02:59:06.38#ibcon#*mode == 0, iclass 29, count 0 2006.286.02:59:06.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.02:59:06.38#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.02:59:06.38#ibcon#*before write, iclass 29, count 0 2006.286.02:59:06.38#ibcon#enter sib2, iclass 29, count 0 2006.286.02:59:06.38#ibcon#flushed, iclass 29, count 0 2006.286.02:59:06.38#ibcon#about to write, iclass 29, count 0 2006.286.02:59:06.38#ibcon#wrote, iclass 29, count 0 2006.286.02:59:06.38#ibcon#about to read 3, iclass 29, count 0 2006.286.02:59:06.42#ibcon#read 3, iclass 29, count 0 2006.286.02:59:06.42#ibcon#about to read 4, iclass 29, count 0 2006.286.02:59:06.42#ibcon#read 4, iclass 29, count 0 2006.286.02:59:06.42#ibcon#about to read 5, iclass 29, count 0 2006.286.02:59:06.42#ibcon#read 5, iclass 29, count 0 2006.286.02:59:06.42#ibcon#about to read 6, iclass 29, count 0 2006.286.02:59:06.42#ibcon#read 6, iclass 29, count 0 2006.286.02:59:06.42#ibcon#end of sib2, iclass 29, count 0 2006.286.02:59:06.42#ibcon#*after write, iclass 29, count 0 2006.286.02:59:06.42#ibcon#*before return 0, iclass 29, count 0 2006.286.02:59:06.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:59:06.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:59:06.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.02:59:06.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.02:59:06.42$vck44/va=8,3 2006.286.02:59:06.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.02:59:06.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.02:59:06.42#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:06.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:59:06.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:59:06.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:59:06.48#ibcon#enter wrdev, iclass 31, count 2 2006.286.02:59:06.48#ibcon#first serial, iclass 31, count 2 2006.286.02:59:06.48#ibcon#enter sib2, iclass 31, count 2 2006.286.02:59:06.48#ibcon#flushed, iclass 31, count 2 2006.286.02:59:06.48#ibcon#about to write, iclass 31, count 2 2006.286.02:59:06.48#ibcon#wrote, iclass 31, count 2 2006.286.02:59:06.48#ibcon#about to read 3, iclass 31, count 2 2006.286.02:59:06.50#ibcon#read 3, iclass 31, count 2 2006.286.02:59:06.50#ibcon#about to read 4, iclass 31, count 2 2006.286.02:59:06.50#ibcon#read 4, iclass 31, count 2 2006.286.02:59:06.50#ibcon#about to read 5, iclass 31, count 2 2006.286.02:59:06.50#ibcon#read 5, iclass 31, count 2 2006.286.02:59:06.50#ibcon#about to read 6, iclass 31, count 2 2006.286.02:59:06.50#ibcon#read 6, iclass 31, count 2 2006.286.02:59:06.50#ibcon#end of sib2, iclass 31, count 2 2006.286.02:59:06.50#ibcon#*mode == 0, iclass 31, count 2 2006.286.02:59:06.50#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.02:59:06.50#ibcon#[25=AT08-03\r\n] 2006.286.02:59:06.50#ibcon#*before write, iclass 31, count 2 2006.286.02:59:06.50#ibcon#enter sib2, iclass 31, count 2 2006.286.02:59:06.50#ibcon#flushed, iclass 31, count 2 2006.286.02:59:06.50#ibcon#about to write, iclass 31, count 2 2006.286.02:59:06.50#ibcon#wrote, iclass 31, count 2 2006.286.02:59:06.50#ibcon#about to read 3, iclass 31, count 2 2006.286.02:59:06.53#ibcon#read 3, iclass 31, count 2 2006.286.02:59:06.53#ibcon#about to read 4, iclass 31, count 2 2006.286.02:59:06.53#ibcon#read 4, iclass 31, count 2 2006.286.02:59:06.53#ibcon#about to read 5, iclass 31, count 2 2006.286.02:59:06.53#ibcon#read 5, iclass 31, count 2 2006.286.02:59:06.53#ibcon#about to read 6, iclass 31, count 2 2006.286.02:59:06.53#ibcon#read 6, iclass 31, count 2 2006.286.02:59:06.53#ibcon#end of sib2, iclass 31, count 2 2006.286.02:59:06.53#ibcon#*after write, iclass 31, count 2 2006.286.02:59:06.53#ibcon#*before return 0, iclass 31, count 2 2006.286.02:59:06.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:59:06.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.02:59:06.53#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.02:59:06.53#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:06.53#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:59:06.65#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:59:06.65#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:59:06.65#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:59:06.65#ibcon#first serial, iclass 31, count 0 2006.286.02:59:06.65#ibcon#enter sib2, iclass 31, count 0 2006.286.02:59:06.65#ibcon#flushed, iclass 31, count 0 2006.286.02:59:06.65#ibcon#about to write, iclass 31, count 0 2006.286.02:59:06.65#ibcon#wrote, iclass 31, count 0 2006.286.02:59:06.65#ibcon#about to read 3, iclass 31, count 0 2006.286.02:59:06.67#ibcon#read 3, iclass 31, count 0 2006.286.02:59:06.67#ibcon#about to read 4, iclass 31, count 0 2006.286.02:59:06.67#ibcon#read 4, iclass 31, count 0 2006.286.02:59:06.67#ibcon#about to read 5, iclass 31, count 0 2006.286.02:59:06.67#ibcon#read 5, iclass 31, count 0 2006.286.02:59:06.67#ibcon#about to read 6, iclass 31, count 0 2006.286.02:59:06.67#ibcon#read 6, iclass 31, count 0 2006.286.02:59:06.67#ibcon#end of sib2, iclass 31, count 0 2006.286.02:59:06.67#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:59:06.67#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:59:06.67#ibcon#[25=USB\r\n] 2006.286.02:59:06.67#ibcon#*before write, iclass 31, count 0 2006.286.02:59:06.67#ibcon#enter sib2, iclass 31, count 0 2006.286.02:59:06.67#ibcon#flushed, iclass 31, count 0 2006.286.02:59:06.67#ibcon#about to write, iclass 31, count 0 2006.286.02:59:06.67#ibcon#wrote, iclass 31, count 0 2006.286.02:59:06.67#ibcon#about to read 3, iclass 31, count 0 2006.286.02:59:06.70#ibcon#read 3, iclass 31, count 0 2006.286.02:59:06.70#ibcon#about to read 4, iclass 31, count 0 2006.286.02:59:06.70#ibcon#read 4, iclass 31, count 0 2006.286.02:59:06.70#ibcon#about to read 5, iclass 31, count 0 2006.286.02:59:06.70#ibcon#read 5, iclass 31, count 0 2006.286.02:59:06.70#ibcon#about to read 6, iclass 31, count 0 2006.286.02:59:06.70#ibcon#read 6, iclass 31, count 0 2006.286.02:59:06.70#ibcon#end of sib2, iclass 31, count 0 2006.286.02:59:06.70#ibcon#*after write, iclass 31, count 0 2006.286.02:59:06.70#ibcon#*before return 0, iclass 31, count 0 2006.286.02:59:06.70#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:59:06.70#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.02:59:06.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:59:06.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:59:06.70$vck44/vblo=1,629.99 2006.286.02:59:06.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.02:59:06.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.02:59:06.70#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:06.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:59:06.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:59:06.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:59:06.70#ibcon#enter wrdev, iclass 33, count 0 2006.286.02:59:06.70#ibcon#first serial, iclass 33, count 0 2006.286.02:59:06.70#ibcon#enter sib2, iclass 33, count 0 2006.286.02:59:06.70#ibcon#flushed, iclass 33, count 0 2006.286.02:59:06.70#ibcon#about to write, iclass 33, count 0 2006.286.02:59:06.70#ibcon#wrote, iclass 33, count 0 2006.286.02:59:06.70#ibcon#about to read 3, iclass 33, count 0 2006.286.02:59:06.72#ibcon#read 3, iclass 33, count 0 2006.286.02:59:06.72#ibcon#about to read 4, iclass 33, count 0 2006.286.02:59:06.72#ibcon#read 4, iclass 33, count 0 2006.286.02:59:06.72#ibcon#about to read 5, iclass 33, count 0 2006.286.02:59:06.72#ibcon#read 5, iclass 33, count 0 2006.286.02:59:06.72#ibcon#about to read 6, iclass 33, count 0 2006.286.02:59:06.72#ibcon#read 6, iclass 33, count 0 2006.286.02:59:06.72#ibcon#end of sib2, iclass 33, count 0 2006.286.02:59:06.72#ibcon#*mode == 0, iclass 33, count 0 2006.286.02:59:06.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.02:59:06.72#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.02:59:06.72#ibcon#*before write, iclass 33, count 0 2006.286.02:59:06.72#ibcon#enter sib2, iclass 33, count 0 2006.286.02:59:06.72#ibcon#flushed, iclass 33, count 0 2006.286.02:59:06.72#ibcon#about to write, iclass 33, count 0 2006.286.02:59:06.72#ibcon#wrote, iclass 33, count 0 2006.286.02:59:06.72#ibcon#about to read 3, iclass 33, count 0 2006.286.02:59:06.76#ibcon#read 3, iclass 33, count 0 2006.286.02:59:06.76#ibcon#about to read 4, iclass 33, count 0 2006.286.02:59:06.76#ibcon#read 4, iclass 33, count 0 2006.286.02:59:06.76#ibcon#about to read 5, iclass 33, count 0 2006.286.02:59:06.76#ibcon#read 5, iclass 33, count 0 2006.286.02:59:06.76#ibcon#about to read 6, iclass 33, count 0 2006.286.02:59:06.76#ibcon#read 6, iclass 33, count 0 2006.286.02:59:06.76#ibcon#end of sib2, iclass 33, count 0 2006.286.02:59:06.76#ibcon#*after write, iclass 33, count 0 2006.286.02:59:06.76#ibcon#*before return 0, iclass 33, count 0 2006.286.02:59:06.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:59:06.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.02:59:06.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.02:59:06.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.02:59:06.76$vck44/vb=1,4 2006.286.02:59:06.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.02:59:06.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.02:59:06.76#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:06.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:59:06.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:59:06.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:59:06.76#ibcon#enter wrdev, iclass 35, count 2 2006.286.02:59:06.76#ibcon#first serial, iclass 35, count 2 2006.286.02:59:06.76#ibcon#enter sib2, iclass 35, count 2 2006.286.02:59:06.76#ibcon#flushed, iclass 35, count 2 2006.286.02:59:06.76#ibcon#about to write, iclass 35, count 2 2006.286.02:59:06.76#ibcon#wrote, iclass 35, count 2 2006.286.02:59:06.76#ibcon#about to read 3, iclass 35, count 2 2006.286.02:59:06.78#ibcon#read 3, iclass 35, count 2 2006.286.02:59:06.78#ibcon#about to read 4, iclass 35, count 2 2006.286.02:59:06.78#ibcon#read 4, iclass 35, count 2 2006.286.02:59:06.78#ibcon#about to read 5, iclass 35, count 2 2006.286.02:59:06.78#ibcon#read 5, iclass 35, count 2 2006.286.02:59:06.78#ibcon#about to read 6, iclass 35, count 2 2006.286.02:59:06.78#ibcon#read 6, iclass 35, count 2 2006.286.02:59:06.78#ibcon#end of sib2, iclass 35, count 2 2006.286.02:59:06.78#ibcon#*mode == 0, iclass 35, count 2 2006.286.02:59:06.78#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.02:59:06.78#ibcon#[27=AT01-04\r\n] 2006.286.02:59:06.78#ibcon#*before write, iclass 35, count 2 2006.286.02:59:06.78#ibcon#enter sib2, iclass 35, count 2 2006.286.02:59:06.78#ibcon#flushed, iclass 35, count 2 2006.286.02:59:06.78#ibcon#about to write, iclass 35, count 2 2006.286.02:59:06.78#ibcon#wrote, iclass 35, count 2 2006.286.02:59:06.78#ibcon#about to read 3, iclass 35, count 2 2006.286.02:59:06.81#ibcon#read 3, iclass 35, count 2 2006.286.02:59:06.81#ibcon#about to read 4, iclass 35, count 2 2006.286.02:59:06.81#ibcon#read 4, iclass 35, count 2 2006.286.02:59:06.81#ibcon#about to read 5, iclass 35, count 2 2006.286.02:59:06.81#ibcon#read 5, iclass 35, count 2 2006.286.02:59:06.81#ibcon#about to read 6, iclass 35, count 2 2006.286.02:59:06.81#ibcon#read 6, iclass 35, count 2 2006.286.02:59:06.81#ibcon#end of sib2, iclass 35, count 2 2006.286.02:59:06.81#ibcon#*after write, iclass 35, count 2 2006.286.02:59:06.81#ibcon#*before return 0, iclass 35, count 2 2006.286.02:59:06.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:59:06.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.02:59:06.81#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.02:59:06.81#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:06.81#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:59:06.93#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:59:06.93#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:59:06.93#ibcon#enter wrdev, iclass 35, count 0 2006.286.02:59:06.93#ibcon#first serial, iclass 35, count 0 2006.286.02:59:06.93#ibcon#enter sib2, iclass 35, count 0 2006.286.02:59:06.93#ibcon#flushed, iclass 35, count 0 2006.286.02:59:06.93#ibcon#about to write, iclass 35, count 0 2006.286.02:59:06.93#ibcon#wrote, iclass 35, count 0 2006.286.02:59:06.93#ibcon#about to read 3, iclass 35, count 0 2006.286.02:59:06.95#ibcon#read 3, iclass 35, count 0 2006.286.02:59:06.95#ibcon#about to read 4, iclass 35, count 0 2006.286.02:59:06.95#ibcon#read 4, iclass 35, count 0 2006.286.02:59:06.95#ibcon#about to read 5, iclass 35, count 0 2006.286.02:59:06.95#ibcon#read 5, iclass 35, count 0 2006.286.02:59:06.95#ibcon#about to read 6, iclass 35, count 0 2006.286.02:59:06.95#ibcon#read 6, iclass 35, count 0 2006.286.02:59:06.95#ibcon#end of sib2, iclass 35, count 0 2006.286.02:59:06.95#ibcon#*mode == 0, iclass 35, count 0 2006.286.02:59:06.95#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.02:59:06.95#ibcon#[27=USB\r\n] 2006.286.02:59:06.95#ibcon#*before write, iclass 35, count 0 2006.286.02:59:06.95#ibcon#enter sib2, iclass 35, count 0 2006.286.02:59:06.95#ibcon#flushed, iclass 35, count 0 2006.286.02:59:06.95#ibcon#about to write, iclass 35, count 0 2006.286.02:59:06.95#ibcon#wrote, iclass 35, count 0 2006.286.02:59:06.95#ibcon#about to read 3, iclass 35, count 0 2006.286.02:59:06.98#ibcon#read 3, iclass 35, count 0 2006.286.02:59:06.98#ibcon#about to read 4, iclass 35, count 0 2006.286.02:59:06.98#ibcon#read 4, iclass 35, count 0 2006.286.02:59:06.98#ibcon#about to read 5, iclass 35, count 0 2006.286.02:59:06.98#ibcon#read 5, iclass 35, count 0 2006.286.02:59:06.98#ibcon#about to read 6, iclass 35, count 0 2006.286.02:59:06.98#ibcon#read 6, iclass 35, count 0 2006.286.02:59:06.98#ibcon#end of sib2, iclass 35, count 0 2006.286.02:59:06.98#ibcon#*after write, iclass 35, count 0 2006.286.02:59:06.98#ibcon#*before return 0, iclass 35, count 0 2006.286.02:59:06.98#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:59:06.98#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.02:59:06.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.02:59:06.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.02:59:06.98$vck44/vblo=2,634.99 2006.286.02:59:06.98#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.02:59:06.98#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.02:59:06.98#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:06.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:59:06.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:59:06.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:59:06.98#ibcon#enter wrdev, iclass 37, count 0 2006.286.02:59:06.98#ibcon#first serial, iclass 37, count 0 2006.286.02:59:06.98#ibcon#enter sib2, iclass 37, count 0 2006.286.02:59:06.98#ibcon#flushed, iclass 37, count 0 2006.286.02:59:06.98#ibcon#about to write, iclass 37, count 0 2006.286.02:59:06.98#ibcon#wrote, iclass 37, count 0 2006.286.02:59:06.98#ibcon#about to read 3, iclass 37, count 0 2006.286.02:59:07.00#ibcon#read 3, iclass 37, count 0 2006.286.02:59:07.00#ibcon#about to read 4, iclass 37, count 0 2006.286.02:59:07.00#ibcon#read 4, iclass 37, count 0 2006.286.02:59:07.00#ibcon#about to read 5, iclass 37, count 0 2006.286.02:59:07.00#ibcon#read 5, iclass 37, count 0 2006.286.02:59:07.00#ibcon#about to read 6, iclass 37, count 0 2006.286.02:59:07.00#ibcon#read 6, iclass 37, count 0 2006.286.02:59:07.00#ibcon#end of sib2, iclass 37, count 0 2006.286.02:59:07.00#ibcon#*mode == 0, iclass 37, count 0 2006.286.02:59:07.00#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.02:59:07.00#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.02:59:07.00#ibcon#*before write, iclass 37, count 0 2006.286.02:59:07.00#ibcon#enter sib2, iclass 37, count 0 2006.286.02:59:07.00#ibcon#flushed, iclass 37, count 0 2006.286.02:59:07.00#ibcon#about to write, iclass 37, count 0 2006.286.02:59:07.00#ibcon#wrote, iclass 37, count 0 2006.286.02:59:07.00#ibcon#about to read 3, iclass 37, count 0 2006.286.02:59:07.04#ibcon#read 3, iclass 37, count 0 2006.286.02:59:07.04#ibcon#about to read 4, iclass 37, count 0 2006.286.02:59:07.04#ibcon#read 4, iclass 37, count 0 2006.286.02:59:07.04#ibcon#about to read 5, iclass 37, count 0 2006.286.02:59:07.04#ibcon#read 5, iclass 37, count 0 2006.286.02:59:07.04#ibcon#about to read 6, iclass 37, count 0 2006.286.02:59:07.04#ibcon#read 6, iclass 37, count 0 2006.286.02:59:07.04#ibcon#end of sib2, iclass 37, count 0 2006.286.02:59:07.04#ibcon#*after write, iclass 37, count 0 2006.286.02:59:07.04#ibcon#*before return 0, iclass 37, count 0 2006.286.02:59:07.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:59:07.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.02:59:07.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.02:59:07.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.02:59:07.04$vck44/vb=2,5 2006.286.02:59:07.04#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.02:59:07.04#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.02:59:07.04#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:07.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:59:07.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:59:07.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:59:07.10#ibcon#enter wrdev, iclass 39, count 2 2006.286.02:59:07.10#ibcon#first serial, iclass 39, count 2 2006.286.02:59:07.10#ibcon#enter sib2, iclass 39, count 2 2006.286.02:59:07.10#ibcon#flushed, iclass 39, count 2 2006.286.02:59:07.10#ibcon#about to write, iclass 39, count 2 2006.286.02:59:07.10#ibcon#wrote, iclass 39, count 2 2006.286.02:59:07.10#ibcon#about to read 3, iclass 39, count 2 2006.286.02:59:07.12#ibcon#read 3, iclass 39, count 2 2006.286.02:59:07.12#ibcon#about to read 4, iclass 39, count 2 2006.286.02:59:07.12#ibcon#read 4, iclass 39, count 2 2006.286.02:59:07.12#ibcon#about to read 5, iclass 39, count 2 2006.286.02:59:07.12#ibcon#read 5, iclass 39, count 2 2006.286.02:59:07.12#ibcon#about to read 6, iclass 39, count 2 2006.286.02:59:07.12#ibcon#read 6, iclass 39, count 2 2006.286.02:59:07.12#ibcon#end of sib2, iclass 39, count 2 2006.286.02:59:07.12#ibcon#*mode == 0, iclass 39, count 2 2006.286.02:59:07.12#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.02:59:07.12#ibcon#[27=AT02-05\r\n] 2006.286.02:59:07.12#ibcon#*before write, iclass 39, count 2 2006.286.02:59:07.12#ibcon#enter sib2, iclass 39, count 2 2006.286.02:59:07.12#ibcon#flushed, iclass 39, count 2 2006.286.02:59:07.12#ibcon#about to write, iclass 39, count 2 2006.286.02:59:07.12#ibcon#wrote, iclass 39, count 2 2006.286.02:59:07.12#ibcon#about to read 3, iclass 39, count 2 2006.286.02:59:07.15#ibcon#read 3, iclass 39, count 2 2006.286.02:59:07.15#ibcon#about to read 4, iclass 39, count 2 2006.286.02:59:07.15#ibcon#read 4, iclass 39, count 2 2006.286.02:59:07.15#ibcon#about to read 5, iclass 39, count 2 2006.286.02:59:07.15#ibcon#read 5, iclass 39, count 2 2006.286.02:59:07.15#ibcon#about to read 6, iclass 39, count 2 2006.286.02:59:07.15#ibcon#read 6, iclass 39, count 2 2006.286.02:59:07.15#ibcon#end of sib2, iclass 39, count 2 2006.286.02:59:07.15#ibcon#*after write, iclass 39, count 2 2006.286.02:59:07.15#ibcon#*before return 0, iclass 39, count 2 2006.286.02:59:07.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:59:07.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.02:59:07.15#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.02:59:07.15#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:07.15#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:59:07.27#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:59:07.27#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:59:07.27#ibcon#enter wrdev, iclass 39, count 0 2006.286.02:59:07.27#ibcon#first serial, iclass 39, count 0 2006.286.02:59:07.27#ibcon#enter sib2, iclass 39, count 0 2006.286.02:59:07.27#ibcon#flushed, iclass 39, count 0 2006.286.02:59:07.27#ibcon#about to write, iclass 39, count 0 2006.286.02:59:07.27#ibcon#wrote, iclass 39, count 0 2006.286.02:59:07.27#ibcon#about to read 3, iclass 39, count 0 2006.286.02:59:07.29#ibcon#read 3, iclass 39, count 0 2006.286.02:59:07.29#ibcon#about to read 4, iclass 39, count 0 2006.286.02:59:07.29#ibcon#read 4, iclass 39, count 0 2006.286.02:59:07.29#ibcon#about to read 5, iclass 39, count 0 2006.286.02:59:07.29#ibcon#read 5, iclass 39, count 0 2006.286.02:59:07.29#ibcon#about to read 6, iclass 39, count 0 2006.286.02:59:07.29#ibcon#read 6, iclass 39, count 0 2006.286.02:59:07.29#ibcon#end of sib2, iclass 39, count 0 2006.286.02:59:07.29#ibcon#*mode == 0, iclass 39, count 0 2006.286.02:59:07.29#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.02:59:07.29#ibcon#[27=USB\r\n] 2006.286.02:59:07.29#ibcon#*before write, iclass 39, count 0 2006.286.02:59:07.29#ibcon#enter sib2, iclass 39, count 0 2006.286.02:59:07.29#ibcon#flushed, iclass 39, count 0 2006.286.02:59:07.29#ibcon#about to write, iclass 39, count 0 2006.286.02:59:07.29#ibcon#wrote, iclass 39, count 0 2006.286.02:59:07.29#ibcon#about to read 3, iclass 39, count 0 2006.286.02:59:07.32#ibcon#read 3, iclass 39, count 0 2006.286.02:59:07.32#ibcon#about to read 4, iclass 39, count 0 2006.286.02:59:07.32#ibcon#read 4, iclass 39, count 0 2006.286.02:59:07.32#ibcon#about to read 5, iclass 39, count 0 2006.286.02:59:07.32#ibcon#read 5, iclass 39, count 0 2006.286.02:59:07.32#ibcon#about to read 6, iclass 39, count 0 2006.286.02:59:07.32#ibcon#read 6, iclass 39, count 0 2006.286.02:59:07.32#ibcon#end of sib2, iclass 39, count 0 2006.286.02:59:07.32#ibcon#*after write, iclass 39, count 0 2006.286.02:59:07.32#ibcon#*before return 0, iclass 39, count 0 2006.286.02:59:07.32#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:59:07.32#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.02:59:07.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.02:59:07.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.02:59:07.32$vck44/vblo=3,649.99 2006.286.02:59:07.32#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.02:59:07.32#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.02:59:07.32#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:07.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:59:07.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:59:07.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:59:07.32#ibcon#enter wrdev, iclass 3, count 0 2006.286.02:59:07.32#ibcon#first serial, iclass 3, count 0 2006.286.02:59:07.32#ibcon#enter sib2, iclass 3, count 0 2006.286.02:59:07.32#ibcon#flushed, iclass 3, count 0 2006.286.02:59:07.32#ibcon#about to write, iclass 3, count 0 2006.286.02:59:07.32#ibcon#wrote, iclass 3, count 0 2006.286.02:59:07.32#ibcon#about to read 3, iclass 3, count 0 2006.286.02:59:07.34#ibcon#read 3, iclass 3, count 0 2006.286.02:59:07.34#ibcon#about to read 4, iclass 3, count 0 2006.286.02:59:07.34#ibcon#read 4, iclass 3, count 0 2006.286.02:59:07.34#ibcon#about to read 5, iclass 3, count 0 2006.286.02:59:07.34#ibcon#read 5, iclass 3, count 0 2006.286.02:59:07.34#ibcon#about to read 6, iclass 3, count 0 2006.286.02:59:07.34#ibcon#read 6, iclass 3, count 0 2006.286.02:59:07.34#ibcon#end of sib2, iclass 3, count 0 2006.286.02:59:07.34#ibcon#*mode == 0, iclass 3, count 0 2006.286.02:59:07.34#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.02:59:07.34#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.02:59:07.34#ibcon#*before write, iclass 3, count 0 2006.286.02:59:07.34#ibcon#enter sib2, iclass 3, count 0 2006.286.02:59:07.34#ibcon#flushed, iclass 3, count 0 2006.286.02:59:07.34#ibcon#about to write, iclass 3, count 0 2006.286.02:59:07.34#ibcon#wrote, iclass 3, count 0 2006.286.02:59:07.34#ibcon#about to read 3, iclass 3, count 0 2006.286.02:59:07.38#ibcon#read 3, iclass 3, count 0 2006.286.02:59:07.38#ibcon#about to read 4, iclass 3, count 0 2006.286.02:59:07.38#ibcon#read 4, iclass 3, count 0 2006.286.02:59:07.38#ibcon#about to read 5, iclass 3, count 0 2006.286.02:59:07.38#ibcon#read 5, iclass 3, count 0 2006.286.02:59:07.38#ibcon#about to read 6, iclass 3, count 0 2006.286.02:59:07.38#ibcon#read 6, iclass 3, count 0 2006.286.02:59:07.38#ibcon#end of sib2, iclass 3, count 0 2006.286.02:59:07.38#ibcon#*after write, iclass 3, count 0 2006.286.02:59:07.38#ibcon#*before return 0, iclass 3, count 0 2006.286.02:59:07.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:59:07.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.02:59:07.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.02:59:07.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.02:59:07.38$vck44/vb=3,4 2006.286.02:59:07.38#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.02:59:07.38#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.02:59:07.38#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:07.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:59:07.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:59:07.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:59:07.44#ibcon#enter wrdev, iclass 5, count 2 2006.286.02:59:07.44#ibcon#first serial, iclass 5, count 2 2006.286.02:59:07.44#ibcon#enter sib2, iclass 5, count 2 2006.286.02:59:07.44#ibcon#flushed, iclass 5, count 2 2006.286.02:59:07.44#ibcon#about to write, iclass 5, count 2 2006.286.02:59:07.44#ibcon#wrote, iclass 5, count 2 2006.286.02:59:07.44#ibcon#about to read 3, iclass 5, count 2 2006.286.02:59:07.46#ibcon#read 3, iclass 5, count 2 2006.286.02:59:07.46#ibcon#about to read 4, iclass 5, count 2 2006.286.02:59:07.46#ibcon#read 4, iclass 5, count 2 2006.286.02:59:07.46#ibcon#about to read 5, iclass 5, count 2 2006.286.02:59:07.46#ibcon#read 5, iclass 5, count 2 2006.286.02:59:07.46#ibcon#about to read 6, iclass 5, count 2 2006.286.02:59:07.46#ibcon#read 6, iclass 5, count 2 2006.286.02:59:07.46#ibcon#end of sib2, iclass 5, count 2 2006.286.02:59:07.46#ibcon#*mode == 0, iclass 5, count 2 2006.286.02:59:07.46#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.02:59:07.46#ibcon#[27=AT03-04\r\n] 2006.286.02:59:07.46#ibcon#*before write, iclass 5, count 2 2006.286.02:59:07.46#ibcon#enter sib2, iclass 5, count 2 2006.286.02:59:07.46#ibcon#flushed, iclass 5, count 2 2006.286.02:59:07.46#ibcon#about to write, iclass 5, count 2 2006.286.02:59:07.46#ibcon#wrote, iclass 5, count 2 2006.286.02:59:07.46#ibcon#about to read 3, iclass 5, count 2 2006.286.02:59:07.49#ibcon#read 3, iclass 5, count 2 2006.286.02:59:07.49#ibcon#about to read 4, iclass 5, count 2 2006.286.02:59:07.49#ibcon#read 4, iclass 5, count 2 2006.286.02:59:07.49#ibcon#about to read 5, iclass 5, count 2 2006.286.02:59:07.49#ibcon#read 5, iclass 5, count 2 2006.286.02:59:07.49#ibcon#about to read 6, iclass 5, count 2 2006.286.02:59:07.49#ibcon#read 6, iclass 5, count 2 2006.286.02:59:07.49#ibcon#end of sib2, iclass 5, count 2 2006.286.02:59:07.49#ibcon#*after write, iclass 5, count 2 2006.286.02:59:07.49#ibcon#*before return 0, iclass 5, count 2 2006.286.02:59:07.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:59:07.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.02:59:07.49#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.02:59:07.49#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:07.49#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:59:07.61#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:59:07.61#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:59:07.61#ibcon#enter wrdev, iclass 5, count 0 2006.286.02:59:07.61#ibcon#first serial, iclass 5, count 0 2006.286.02:59:07.61#ibcon#enter sib2, iclass 5, count 0 2006.286.02:59:07.61#ibcon#flushed, iclass 5, count 0 2006.286.02:59:07.61#ibcon#about to write, iclass 5, count 0 2006.286.02:59:07.61#ibcon#wrote, iclass 5, count 0 2006.286.02:59:07.61#ibcon#about to read 3, iclass 5, count 0 2006.286.02:59:07.63#ibcon#read 3, iclass 5, count 0 2006.286.02:59:07.63#ibcon#about to read 4, iclass 5, count 0 2006.286.02:59:07.63#ibcon#read 4, iclass 5, count 0 2006.286.02:59:07.63#ibcon#about to read 5, iclass 5, count 0 2006.286.02:59:07.63#ibcon#read 5, iclass 5, count 0 2006.286.02:59:07.63#ibcon#about to read 6, iclass 5, count 0 2006.286.02:59:07.63#ibcon#read 6, iclass 5, count 0 2006.286.02:59:07.63#ibcon#end of sib2, iclass 5, count 0 2006.286.02:59:07.63#ibcon#*mode == 0, iclass 5, count 0 2006.286.02:59:07.63#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.02:59:07.63#ibcon#[27=USB\r\n] 2006.286.02:59:07.63#ibcon#*before write, iclass 5, count 0 2006.286.02:59:07.63#ibcon#enter sib2, iclass 5, count 0 2006.286.02:59:07.63#ibcon#flushed, iclass 5, count 0 2006.286.02:59:07.63#ibcon#about to write, iclass 5, count 0 2006.286.02:59:07.63#ibcon#wrote, iclass 5, count 0 2006.286.02:59:07.63#ibcon#about to read 3, iclass 5, count 0 2006.286.02:59:07.66#ibcon#read 3, iclass 5, count 0 2006.286.02:59:07.66#ibcon#about to read 4, iclass 5, count 0 2006.286.02:59:07.66#ibcon#read 4, iclass 5, count 0 2006.286.02:59:07.66#ibcon#about to read 5, iclass 5, count 0 2006.286.02:59:07.66#ibcon#read 5, iclass 5, count 0 2006.286.02:59:07.66#ibcon#about to read 6, iclass 5, count 0 2006.286.02:59:07.66#ibcon#read 6, iclass 5, count 0 2006.286.02:59:07.66#ibcon#end of sib2, iclass 5, count 0 2006.286.02:59:07.66#ibcon#*after write, iclass 5, count 0 2006.286.02:59:07.66#ibcon#*before return 0, iclass 5, count 0 2006.286.02:59:07.66#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:59:07.66#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.02:59:07.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.02:59:07.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.02:59:07.66$vck44/vblo=4,679.99 2006.286.02:59:07.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.02:59:07.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.02:59:07.68#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:07.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:59:07.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:59:07.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:59:07.68#ibcon#enter wrdev, iclass 7, count 0 2006.286.02:59:07.68#ibcon#first serial, iclass 7, count 0 2006.286.02:59:07.68#ibcon#enter sib2, iclass 7, count 0 2006.286.02:59:07.68#ibcon#flushed, iclass 7, count 0 2006.286.02:59:07.68#ibcon#about to write, iclass 7, count 0 2006.286.02:59:07.68#ibcon#wrote, iclass 7, count 0 2006.286.02:59:07.68#ibcon#about to read 3, iclass 7, count 0 2006.286.02:59:07.70#ibcon#read 3, iclass 7, count 0 2006.286.02:59:07.70#ibcon#about to read 4, iclass 7, count 0 2006.286.02:59:07.70#ibcon#read 4, iclass 7, count 0 2006.286.02:59:07.70#ibcon#about to read 5, iclass 7, count 0 2006.286.02:59:07.70#ibcon#read 5, iclass 7, count 0 2006.286.02:59:07.70#ibcon#about to read 6, iclass 7, count 0 2006.286.02:59:07.70#ibcon#read 6, iclass 7, count 0 2006.286.02:59:07.70#ibcon#end of sib2, iclass 7, count 0 2006.286.02:59:07.70#ibcon#*mode == 0, iclass 7, count 0 2006.286.02:59:07.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.02:59:07.70#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.02:59:07.70#ibcon#*before write, iclass 7, count 0 2006.286.02:59:07.70#ibcon#enter sib2, iclass 7, count 0 2006.286.02:59:07.70#ibcon#flushed, iclass 7, count 0 2006.286.02:59:07.70#ibcon#about to write, iclass 7, count 0 2006.286.02:59:07.70#ibcon#wrote, iclass 7, count 0 2006.286.02:59:07.70#ibcon#about to read 3, iclass 7, count 0 2006.286.02:59:07.74#ibcon#read 3, iclass 7, count 0 2006.286.02:59:07.74#ibcon#about to read 4, iclass 7, count 0 2006.286.02:59:07.74#ibcon#read 4, iclass 7, count 0 2006.286.02:59:07.74#ibcon#about to read 5, iclass 7, count 0 2006.286.02:59:07.74#ibcon#read 5, iclass 7, count 0 2006.286.02:59:07.74#ibcon#about to read 6, iclass 7, count 0 2006.286.02:59:07.74#ibcon#read 6, iclass 7, count 0 2006.286.02:59:07.74#ibcon#end of sib2, iclass 7, count 0 2006.286.02:59:07.74#ibcon#*after write, iclass 7, count 0 2006.286.02:59:07.74#ibcon#*before return 0, iclass 7, count 0 2006.286.02:59:07.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:59:07.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.02:59:07.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.02:59:07.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.02:59:07.74$vck44/vb=4,5 2006.286.02:59:07.74#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.02:59:07.74#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.02:59:07.74#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:07.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:59:07.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:59:07.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:59:07.78#ibcon#enter wrdev, iclass 11, count 2 2006.286.02:59:07.78#ibcon#first serial, iclass 11, count 2 2006.286.02:59:07.78#ibcon#enter sib2, iclass 11, count 2 2006.286.02:59:07.78#ibcon#flushed, iclass 11, count 2 2006.286.02:59:07.78#ibcon#about to write, iclass 11, count 2 2006.286.02:59:07.78#ibcon#wrote, iclass 11, count 2 2006.286.02:59:07.78#ibcon#about to read 3, iclass 11, count 2 2006.286.02:59:07.80#ibcon#read 3, iclass 11, count 2 2006.286.02:59:07.80#ibcon#about to read 4, iclass 11, count 2 2006.286.02:59:07.80#ibcon#read 4, iclass 11, count 2 2006.286.02:59:07.80#ibcon#about to read 5, iclass 11, count 2 2006.286.02:59:07.80#ibcon#read 5, iclass 11, count 2 2006.286.02:59:07.80#ibcon#about to read 6, iclass 11, count 2 2006.286.02:59:07.80#ibcon#read 6, iclass 11, count 2 2006.286.02:59:07.80#ibcon#end of sib2, iclass 11, count 2 2006.286.02:59:07.80#ibcon#*mode == 0, iclass 11, count 2 2006.286.02:59:07.80#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.02:59:07.80#ibcon#[27=AT04-05\r\n] 2006.286.02:59:07.80#ibcon#*before write, iclass 11, count 2 2006.286.02:59:07.80#ibcon#enter sib2, iclass 11, count 2 2006.286.02:59:07.80#ibcon#flushed, iclass 11, count 2 2006.286.02:59:07.80#ibcon#about to write, iclass 11, count 2 2006.286.02:59:07.80#ibcon#wrote, iclass 11, count 2 2006.286.02:59:07.80#ibcon#about to read 3, iclass 11, count 2 2006.286.02:59:07.83#ibcon#read 3, iclass 11, count 2 2006.286.02:59:07.83#ibcon#about to read 4, iclass 11, count 2 2006.286.02:59:07.83#ibcon#read 4, iclass 11, count 2 2006.286.02:59:07.83#ibcon#about to read 5, iclass 11, count 2 2006.286.02:59:07.83#ibcon#read 5, iclass 11, count 2 2006.286.02:59:07.83#ibcon#about to read 6, iclass 11, count 2 2006.286.02:59:07.83#ibcon#read 6, iclass 11, count 2 2006.286.02:59:07.83#ibcon#end of sib2, iclass 11, count 2 2006.286.02:59:07.83#ibcon#*after write, iclass 11, count 2 2006.286.02:59:07.83#ibcon#*before return 0, iclass 11, count 2 2006.286.02:59:07.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:59:07.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.02:59:07.83#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.02:59:07.83#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:07.83#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:59:07.95#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:59:07.95#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:59:07.95#ibcon#enter wrdev, iclass 11, count 0 2006.286.02:59:07.95#ibcon#first serial, iclass 11, count 0 2006.286.02:59:07.95#ibcon#enter sib2, iclass 11, count 0 2006.286.02:59:07.95#ibcon#flushed, iclass 11, count 0 2006.286.02:59:07.95#ibcon#about to write, iclass 11, count 0 2006.286.02:59:07.95#ibcon#wrote, iclass 11, count 0 2006.286.02:59:07.95#ibcon#about to read 3, iclass 11, count 0 2006.286.02:59:07.97#ibcon#read 3, iclass 11, count 0 2006.286.02:59:07.97#ibcon#about to read 4, iclass 11, count 0 2006.286.02:59:07.97#ibcon#read 4, iclass 11, count 0 2006.286.02:59:07.97#ibcon#about to read 5, iclass 11, count 0 2006.286.02:59:07.97#ibcon#read 5, iclass 11, count 0 2006.286.02:59:07.97#ibcon#about to read 6, iclass 11, count 0 2006.286.02:59:07.97#ibcon#read 6, iclass 11, count 0 2006.286.02:59:07.97#ibcon#end of sib2, iclass 11, count 0 2006.286.02:59:07.97#ibcon#*mode == 0, iclass 11, count 0 2006.286.02:59:07.97#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.02:59:07.97#ibcon#[27=USB\r\n] 2006.286.02:59:07.97#ibcon#*before write, iclass 11, count 0 2006.286.02:59:07.97#ibcon#enter sib2, iclass 11, count 0 2006.286.02:59:07.97#ibcon#flushed, iclass 11, count 0 2006.286.02:59:07.97#ibcon#about to write, iclass 11, count 0 2006.286.02:59:07.97#ibcon#wrote, iclass 11, count 0 2006.286.02:59:07.97#ibcon#about to read 3, iclass 11, count 0 2006.286.02:59:08.00#ibcon#read 3, iclass 11, count 0 2006.286.02:59:08.00#ibcon#about to read 4, iclass 11, count 0 2006.286.02:59:08.00#ibcon#read 4, iclass 11, count 0 2006.286.02:59:08.00#ibcon#about to read 5, iclass 11, count 0 2006.286.02:59:08.00#ibcon#read 5, iclass 11, count 0 2006.286.02:59:08.00#ibcon#about to read 6, iclass 11, count 0 2006.286.02:59:08.00#ibcon#read 6, iclass 11, count 0 2006.286.02:59:08.00#ibcon#end of sib2, iclass 11, count 0 2006.286.02:59:08.00#ibcon#*after write, iclass 11, count 0 2006.286.02:59:08.00#ibcon#*before return 0, iclass 11, count 0 2006.286.02:59:08.00#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:59:08.00#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.02:59:08.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.02:59:08.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.02:59:08.00$vck44/vblo=5,709.99 2006.286.02:59:08.00#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.02:59:08.00#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.02:59:08.00#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:08.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:59:08.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:59:08.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:59:08.00#ibcon#enter wrdev, iclass 13, count 0 2006.286.02:59:08.00#ibcon#first serial, iclass 13, count 0 2006.286.02:59:08.00#ibcon#enter sib2, iclass 13, count 0 2006.286.02:59:08.00#ibcon#flushed, iclass 13, count 0 2006.286.02:59:08.00#ibcon#about to write, iclass 13, count 0 2006.286.02:59:08.00#ibcon#wrote, iclass 13, count 0 2006.286.02:59:08.00#ibcon#about to read 3, iclass 13, count 0 2006.286.02:59:08.02#ibcon#read 3, iclass 13, count 0 2006.286.02:59:08.02#ibcon#about to read 4, iclass 13, count 0 2006.286.02:59:08.02#ibcon#read 4, iclass 13, count 0 2006.286.02:59:08.02#ibcon#about to read 5, iclass 13, count 0 2006.286.02:59:08.02#ibcon#read 5, iclass 13, count 0 2006.286.02:59:08.02#ibcon#about to read 6, iclass 13, count 0 2006.286.02:59:08.02#ibcon#read 6, iclass 13, count 0 2006.286.02:59:08.02#ibcon#end of sib2, iclass 13, count 0 2006.286.02:59:08.02#ibcon#*mode == 0, iclass 13, count 0 2006.286.02:59:08.02#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.02:59:08.02#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.02:59:08.02#ibcon#*before write, iclass 13, count 0 2006.286.02:59:08.02#ibcon#enter sib2, iclass 13, count 0 2006.286.02:59:08.02#ibcon#flushed, iclass 13, count 0 2006.286.02:59:08.02#ibcon#about to write, iclass 13, count 0 2006.286.02:59:08.02#ibcon#wrote, iclass 13, count 0 2006.286.02:59:08.02#ibcon#about to read 3, iclass 13, count 0 2006.286.02:59:08.06#ibcon#read 3, iclass 13, count 0 2006.286.02:59:08.06#ibcon#about to read 4, iclass 13, count 0 2006.286.02:59:08.06#ibcon#read 4, iclass 13, count 0 2006.286.02:59:08.06#ibcon#about to read 5, iclass 13, count 0 2006.286.02:59:08.06#ibcon#read 5, iclass 13, count 0 2006.286.02:59:08.06#ibcon#about to read 6, iclass 13, count 0 2006.286.02:59:08.06#ibcon#read 6, iclass 13, count 0 2006.286.02:59:08.06#ibcon#end of sib2, iclass 13, count 0 2006.286.02:59:08.06#ibcon#*after write, iclass 13, count 0 2006.286.02:59:08.06#ibcon#*before return 0, iclass 13, count 0 2006.286.02:59:08.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:59:08.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.02:59:08.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.02:59:08.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.02:59:08.06$vck44/vb=5,4 2006.286.02:59:08.06#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.02:59:08.06#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.02:59:08.06#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:08.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:59:08.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:59:08.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:59:08.12#ibcon#enter wrdev, iclass 15, count 2 2006.286.02:59:08.12#ibcon#first serial, iclass 15, count 2 2006.286.02:59:08.12#ibcon#enter sib2, iclass 15, count 2 2006.286.02:59:08.12#ibcon#flushed, iclass 15, count 2 2006.286.02:59:08.12#ibcon#about to write, iclass 15, count 2 2006.286.02:59:08.12#ibcon#wrote, iclass 15, count 2 2006.286.02:59:08.12#ibcon#about to read 3, iclass 15, count 2 2006.286.02:59:08.14#ibcon#read 3, iclass 15, count 2 2006.286.02:59:08.14#ibcon#about to read 4, iclass 15, count 2 2006.286.02:59:08.14#ibcon#read 4, iclass 15, count 2 2006.286.02:59:08.14#ibcon#about to read 5, iclass 15, count 2 2006.286.02:59:08.14#ibcon#read 5, iclass 15, count 2 2006.286.02:59:08.14#ibcon#about to read 6, iclass 15, count 2 2006.286.02:59:08.14#ibcon#read 6, iclass 15, count 2 2006.286.02:59:08.14#ibcon#end of sib2, iclass 15, count 2 2006.286.02:59:08.14#ibcon#*mode == 0, iclass 15, count 2 2006.286.02:59:08.14#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.02:59:08.14#ibcon#[27=AT05-04\r\n] 2006.286.02:59:08.14#ibcon#*before write, iclass 15, count 2 2006.286.02:59:08.14#ibcon#enter sib2, iclass 15, count 2 2006.286.02:59:08.14#ibcon#flushed, iclass 15, count 2 2006.286.02:59:08.14#ibcon#about to write, iclass 15, count 2 2006.286.02:59:08.14#ibcon#wrote, iclass 15, count 2 2006.286.02:59:08.14#ibcon#about to read 3, iclass 15, count 2 2006.286.02:59:08.17#ibcon#read 3, iclass 15, count 2 2006.286.02:59:08.17#ibcon#about to read 4, iclass 15, count 2 2006.286.02:59:08.17#ibcon#read 4, iclass 15, count 2 2006.286.02:59:08.17#ibcon#about to read 5, iclass 15, count 2 2006.286.02:59:08.17#ibcon#read 5, iclass 15, count 2 2006.286.02:59:08.17#ibcon#about to read 6, iclass 15, count 2 2006.286.02:59:08.17#ibcon#read 6, iclass 15, count 2 2006.286.02:59:08.17#ibcon#end of sib2, iclass 15, count 2 2006.286.02:59:08.17#ibcon#*after write, iclass 15, count 2 2006.286.02:59:08.17#ibcon#*before return 0, iclass 15, count 2 2006.286.02:59:08.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:59:08.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.02:59:08.17#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.02:59:08.17#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:08.17#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:59:08.29#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:59:08.29#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:59:08.29#ibcon#enter wrdev, iclass 15, count 0 2006.286.02:59:08.29#ibcon#first serial, iclass 15, count 0 2006.286.02:59:08.29#ibcon#enter sib2, iclass 15, count 0 2006.286.02:59:08.29#ibcon#flushed, iclass 15, count 0 2006.286.02:59:08.29#ibcon#about to write, iclass 15, count 0 2006.286.02:59:08.29#ibcon#wrote, iclass 15, count 0 2006.286.02:59:08.29#ibcon#about to read 3, iclass 15, count 0 2006.286.02:59:08.31#ibcon#read 3, iclass 15, count 0 2006.286.02:59:08.31#ibcon#about to read 4, iclass 15, count 0 2006.286.02:59:08.31#ibcon#read 4, iclass 15, count 0 2006.286.02:59:08.31#ibcon#about to read 5, iclass 15, count 0 2006.286.02:59:08.31#ibcon#read 5, iclass 15, count 0 2006.286.02:59:08.31#ibcon#about to read 6, iclass 15, count 0 2006.286.02:59:08.31#ibcon#read 6, iclass 15, count 0 2006.286.02:59:08.31#ibcon#end of sib2, iclass 15, count 0 2006.286.02:59:08.31#ibcon#*mode == 0, iclass 15, count 0 2006.286.02:59:08.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.02:59:08.31#ibcon#[27=USB\r\n] 2006.286.02:59:08.31#ibcon#*before write, iclass 15, count 0 2006.286.02:59:08.31#ibcon#enter sib2, iclass 15, count 0 2006.286.02:59:08.31#ibcon#flushed, iclass 15, count 0 2006.286.02:59:08.31#ibcon#about to write, iclass 15, count 0 2006.286.02:59:08.31#ibcon#wrote, iclass 15, count 0 2006.286.02:59:08.31#ibcon#about to read 3, iclass 15, count 0 2006.286.02:59:08.34#ibcon#read 3, iclass 15, count 0 2006.286.02:59:08.34#ibcon#about to read 4, iclass 15, count 0 2006.286.02:59:08.34#ibcon#read 4, iclass 15, count 0 2006.286.02:59:08.34#ibcon#about to read 5, iclass 15, count 0 2006.286.02:59:08.34#ibcon#read 5, iclass 15, count 0 2006.286.02:59:08.34#ibcon#about to read 6, iclass 15, count 0 2006.286.02:59:08.34#ibcon#read 6, iclass 15, count 0 2006.286.02:59:08.34#ibcon#end of sib2, iclass 15, count 0 2006.286.02:59:08.34#ibcon#*after write, iclass 15, count 0 2006.286.02:59:08.34#ibcon#*before return 0, iclass 15, count 0 2006.286.02:59:08.34#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:59:08.34#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.02:59:08.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.02:59:08.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.02:59:08.34$vck44/vblo=6,719.99 2006.286.02:59:08.34#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.02:59:08.34#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.02:59:08.34#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:08.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:59:08.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:59:08.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:59:08.34#ibcon#enter wrdev, iclass 17, count 0 2006.286.02:59:08.34#ibcon#first serial, iclass 17, count 0 2006.286.02:59:08.34#ibcon#enter sib2, iclass 17, count 0 2006.286.02:59:08.34#ibcon#flushed, iclass 17, count 0 2006.286.02:59:08.34#ibcon#about to write, iclass 17, count 0 2006.286.02:59:08.34#ibcon#wrote, iclass 17, count 0 2006.286.02:59:08.34#ibcon#about to read 3, iclass 17, count 0 2006.286.02:59:08.36#ibcon#read 3, iclass 17, count 0 2006.286.02:59:08.36#ibcon#about to read 4, iclass 17, count 0 2006.286.02:59:08.36#ibcon#read 4, iclass 17, count 0 2006.286.02:59:08.36#ibcon#about to read 5, iclass 17, count 0 2006.286.02:59:08.36#ibcon#read 5, iclass 17, count 0 2006.286.02:59:08.36#ibcon#about to read 6, iclass 17, count 0 2006.286.02:59:08.36#ibcon#read 6, iclass 17, count 0 2006.286.02:59:08.36#ibcon#end of sib2, iclass 17, count 0 2006.286.02:59:08.36#ibcon#*mode == 0, iclass 17, count 0 2006.286.02:59:08.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.02:59:08.36#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.02:59:08.36#ibcon#*before write, iclass 17, count 0 2006.286.02:59:08.36#ibcon#enter sib2, iclass 17, count 0 2006.286.02:59:08.36#ibcon#flushed, iclass 17, count 0 2006.286.02:59:08.36#ibcon#about to write, iclass 17, count 0 2006.286.02:59:08.36#ibcon#wrote, iclass 17, count 0 2006.286.02:59:08.36#ibcon#about to read 3, iclass 17, count 0 2006.286.02:59:08.40#ibcon#read 3, iclass 17, count 0 2006.286.02:59:08.40#ibcon#about to read 4, iclass 17, count 0 2006.286.02:59:08.40#ibcon#read 4, iclass 17, count 0 2006.286.02:59:08.40#ibcon#about to read 5, iclass 17, count 0 2006.286.02:59:08.40#ibcon#read 5, iclass 17, count 0 2006.286.02:59:08.40#ibcon#about to read 6, iclass 17, count 0 2006.286.02:59:08.40#ibcon#read 6, iclass 17, count 0 2006.286.02:59:08.40#ibcon#end of sib2, iclass 17, count 0 2006.286.02:59:08.40#ibcon#*after write, iclass 17, count 0 2006.286.02:59:08.40#ibcon#*before return 0, iclass 17, count 0 2006.286.02:59:08.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:59:08.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.02:59:08.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.02:59:08.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.02:59:08.40$vck44/vb=6,3 2006.286.02:59:08.40#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.02:59:08.40#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.02:59:08.40#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:08.40#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:59:08.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:59:08.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:59:08.46#ibcon#enter wrdev, iclass 19, count 2 2006.286.02:59:08.46#ibcon#first serial, iclass 19, count 2 2006.286.02:59:08.46#ibcon#enter sib2, iclass 19, count 2 2006.286.02:59:08.46#ibcon#flushed, iclass 19, count 2 2006.286.02:59:08.46#ibcon#about to write, iclass 19, count 2 2006.286.02:59:08.46#ibcon#wrote, iclass 19, count 2 2006.286.02:59:08.46#ibcon#about to read 3, iclass 19, count 2 2006.286.02:59:08.48#ibcon#read 3, iclass 19, count 2 2006.286.02:59:08.48#ibcon#about to read 4, iclass 19, count 2 2006.286.02:59:08.48#ibcon#read 4, iclass 19, count 2 2006.286.02:59:08.48#ibcon#about to read 5, iclass 19, count 2 2006.286.02:59:08.48#ibcon#read 5, iclass 19, count 2 2006.286.02:59:08.48#ibcon#about to read 6, iclass 19, count 2 2006.286.02:59:08.48#ibcon#read 6, iclass 19, count 2 2006.286.02:59:08.48#ibcon#end of sib2, iclass 19, count 2 2006.286.02:59:08.48#ibcon#*mode == 0, iclass 19, count 2 2006.286.02:59:08.48#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.02:59:08.48#ibcon#[27=AT06-03\r\n] 2006.286.02:59:08.48#ibcon#*before write, iclass 19, count 2 2006.286.02:59:08.48#ibcon#enter sib2, iclass 19, count 2 2006.286.02:59:08.48#ibcon#flushed, iclass 19, count 2 2006.286.02:59:08.48#ibcon#about to write, iclass 19, count 2 2006.286.02:59:08.48#ibcon#wrote, iclass 19, count 2 2006.286.02:59:08.48#ibcon#about to read 3, iclass 19, count 2 2006.286.02:59:08.51#ibcon#read 3, iclass 19, count 2 2006.286.02:59:08.51#ibcon#about to read 4, iclass 19, count 2 2006.286.02:59:08.51#ibcon#read 4, iclass 19, count 2 2006.286.02:59:08.51#ibcon#about to read 5, iclass 19, count 2 2006.286.02:59:08.51#ibcon#read 5, iclass 19, count 2 2006.286.02:59:08.51#ibcon#about to read 6, iclass 19, count 2 2006.286.02:59:08.51#ibcon#read 6, iclass 19, count 2 2006.286.02:59:08.51#ibcon#end of sib2, iclass 19, count 2 2006.286.02:59:08.51#ibcon#*after write, iclass 19, count 2 2006.286.02:59:08.51#ibcon#*before return 0, iclass 19, count 2 2006.286.02:59:08.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:59:08.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.02:59:08.51#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.02:59:08.51#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:08.51#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:59:08.63#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:59:08.63#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:59:08.63#ibcon#enter wrdev, iclass 19, count 0 2006.286.02:59:08.63#ibcon#first serial, iclass 19, count 0 2006.286.02:59:08.63#ibcon#enter sib2, iclass 19, count 0 2006.286.02:59:08.63#ibcon#flushed, iclass 19, count 0 2006.286.02:59:08.63#ibcon#about to write, iclass 19, count 0 2006.286.02:59:08.63#ibcon#wrote, iclass 19, count 0 2006.286.02:59:08.63#ibcon#about to read 3, iclass 19, count 0 2006.286.02:59:08.65#ibcon#read 3, iclass 19, count 0 2006.286.02:59:08.65#ibcon#about to read 4, iclass 19, count 0 2006.286.02:59:08.65#ibcon#read 4, iclass 19, count 0 2006.286.02:59:08.65#ibcon#about to read 5, iclass 19, count 0 2006.286.02:59:08.65#ibcon#read 5, iclass 19, count 0 2006.286.02:59:08.65#ibcon#about to read 6, iclass 19, count 0 2006.286.02:59:08.65#ibcon#read 6, iclass 19, count 0 2006.286.02:59:08.65#ibcon#end of sib2, iclass 19, count 0 2006.286.02:59:08.65#ibcon#*mode == 0, iclass 19, count 0 2006.286.02:59:08.65#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.02:59:08.65#ibcon#[27=USB\r\n] 2006.286.02:59:08.65#ibcon#*before write, iclass 19, count 0 2006.286.02:59:08.65#ibcon#enter sib2, iclass 19, count 0 2006.286.02:59:08.65#ibcon#flushed, iclass 19, count 0 2006.286.02:59:08.65#ibcon#about to write, iclass 19, count 0 2006.286.02:59:08.65#ibcon#wrote, iclass 19, count 0 2006.286.02:59:08.65#ibcon#about to read 3, iclass 19, count 0 2006.286.02:59:08.68#ibcon#read 3, iclass 19, count 0 2006.286.02:59:08.68#ibcon#about to read 4, iclass 19, count 0 2006.286.02:59:08.68#ibcon#read 4, iclass 19, count 0 2006.286.02:59:08.68#ibcon#about to read 5, iclass 19, count 0 2006.286.02:59:08.68#ibcon#read 5, iclass 19, count 0 2006.286.02:59:08.68#ibcon#about to read 6, iclass 19, count 0 2006.286.02:59:08.68#ibcon#read 6, iclass 19, count 0 2006.286.02:59:08.68#ibcon#end of sib2, iclass 19, count 0 2006.286.02:59:08.68#ibcon#*after write, iclass 19, count 0 2006.286.02:59:08.68#ibcon#*before return 0, iclass 19, count 0 2006.286.02:59:08.68#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:59:08.68#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.02:59:08.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.02:59:08.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.02:59:08.68$vck44/vblo=7,734.99 2006.286.02:59:08.78#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.02:59:08.78#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.02:59:08.78#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:08.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:59:08.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:59:08.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:59:08.78#ibcon#enter wrdev, iclass 21, count 0 2006.286.02:59:08.78#ibcon#first serial, iclass 21, count 0 2006.286.02:59:08.78#ibcon#enter sib2, iclass 21, count 0 2006.286.02:59:08.78#ibcon#flushed, iclass 21, count 0 2006.286.02:59:08.78#ibcon#about to write, iclass 21, count 0 2006.286.02:59:08.78#ibcon#wrote, iclass 21, count 0 2006.286.02:59:08.78#ibcon#about to read 3, iclass 21, count 0 2006.286.02:59:08.79#ibcon#read 3, iclass 21, count 0 2006.286.02:59:08.79#ibcon#about to read 4, iclass 21, count 0 2006.286.02:59:08.79#ibcon#read 4, iclass 21, count 0 2006.286.02:59:08.79#ibcon#about to read 5, iclass 21, count 0 2006.286.02:59:08.79#ibcon#read 5, iclass 21, count 0 2006.286.02:59:08.79#ibcon#about to read 6, iclass 21, count 0 2006.286.02:59:08.79#ibcon#read 6, iclass 21, count 0 2006.286.02:59:08.79#ibcon#end of sib2, iclass 21, count 0 2006.286.02:59:08.79#ibcon#*mode == 0, iclass 21, count 0 2006.286.02:59:08.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.02:59:08.79#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.02:59:08.79#ibcon#*before write, iclass 21, count 0 2006.286.02:59:08.79#ibcon#enter sib2, iclass 21, count 0 2006.286.02:59:08.79#ibcon#flushed, iclass 21, count 0 2006.286.02:59:08.79#ibcon#about to write, iclass 21, count 0 2006.286.02:59:08.79#ibcon#wrote, iclass 21, count 0 2006.286.02:59:08.79#ibcon#about to read 3, iclass 21, count 0 2006.286.02:59:08.83#ibcon#read 3, iclass 21, count 0 2006.286.02:59:08.83#ibcon#about to read 4, iclass 21, count 0 2006.286.02:59:08.83#ibcon#read 4, iclass 21, count 0 2006.286.02:59:08.83#ibcon#about to read 5, iclass 21, count 0 2006.286.02:59:08.83#ibcon#read 5, iclass 21, count 0 2006.286.02:59:08.83#ibcon#about to read 6, iclass 21, count 0 2006.286.02:59:08.83#ibcon#read 6, iclass 21, count 0 2006.286.02:59:08.83#ibcon#end of sib2, iclass 21, count 0 2006.286.02:59:08.83#ibcon#*after write, iclass 21, count 0 2006.286.02:59:08.83#ibcon#*before return 0, iclass 21, count 0 2006.286.02:59:08.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:59:08.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.02:59:08.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.02:59:08.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.02:59:08.83$vck44/vb=7,4 2006.286.02:59:08.83#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.02:59:08.83#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.02:59:08.83#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:08.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:59:08.83#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:59:08.83#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:59:08.83#ibcon#enter wrdev, iclass 23, count 2 2006.286.02:59:08.83#ibcon#first serial, iclass 23, count 2 2006.286.02:59:08.83#ibcon#enter sib2, iclass 23, count 2 2006.286.02:59:08.83#ibcon#flushed, iclass 23, count 2 2006.286.02:59:08.83#ibcon#about to write, iclass 23, count 2 2006.286.02:59:08.83#ibcon#wrote, iclass 23, count 2 2006.286.02:59:08.83#ibcon#about to read 3, iclass 23, count 2 2006.286.02:59:08.85#ibcon#read 3, iclass 23, count 2 2006.286.02:59:08.85#ibcon#about to read 4, iclass 23, count 2 2006.286.02:59:08.85#ibcon#read 4, iclass 23, count 2 2006.286.02:59:08.85#ibcon#about to read 5, iclass 23, count 2 2006.286.02:59:08.85#ibcon#read 5, iclass 23, count 2 2006.286.02:59:08.85#ibcon#about to read 6, iclass 23, count 2 2006.286.02:59:08.85#ibcon#read 6, iclass 23, count 2 2006.286.02:59:08.85#ibcon#end of sib2, iclass 23, count 2 2006.286.02:59:08.85#ibcon#*mode == 0, iclass 23, count 2 2006.286.02:59:08.85#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.02:59:08.85#ibcon#[27=AT07-04\r\n] 2006.286.02:59:08.85#ibcon#*before write, iclass 23, count 2 2006.286.02:59:08.85#ibcon#enter sib2, iclass 23, count 2 2006.286.02:59:08.85#ibcon#flushed, iclass 23, count 2 2006.286.02:59:08.85#ibcon#about to write, iclass 23, count 2 2006.286.02:59:08.85#ibcon#wrote, iclass 23, count 2 2006.286.02:59:08.85#ibcon#about to read 3, iclass 23, count 2 2006.286.02:59:08.88#ibcon#read 3, iclass 23, count 2 2006.286.02:59:08.88#ibcon#about to read 4, iclass 23, count 2 2006.286.02:59:08.88#ibcon#read 4, iclass 23, count 2 2006.286.02:59:08.88#ibcon#about to read 5, iclass 23, count 2 2006.286.02:59:08.88#ibcon#read 5, iclass 23, count 2 2006.286.02:59:08.88#ibcon#about to read 6, iclass 23, count 2 2006.286.02:59:08.88#ibcon#read 6, iclass 23, count 2 2006.286.02:59:08.88#ibcon#end of sib2, iclass 23, count 2 2006.286.02:59:08.88#ibcon#*after write, iclass 23, count 2 2006.286.02:59:08.88#ibcon#*before return 0, iclass 23, count 2 2006.286.02:59:08.88#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:59:08.88#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.02:59:08.88#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.02:59:08.88#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:08.88#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:59:09.00#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:59:09.00#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:59:09.00#ibcon#enter wrdev, iclass 23, count 0 2006.286.02:59:09.00#ibcon#first serial, iclass 23, count 0 2006.286.02:59:09.00#ibcon#enter sib2, iclass 23, count 0 2006.286.02:59:09.00#ibcon#flushed, iclass 23, count 0 2006.286.02:59:09.00#ibcon#about to write, iclass 23, count 0 2006.286.02:59:09.00#ibcon#wrote, iclass 23, count 0 2006.286.02:59:09.00#ibcon#about to read 3, iclass 23, count 0 2006.286.02:59:09.02#ibcon#read 3, iclass 23, count 0 2006.286.02:59:09.02#ibcon#about to read 4, iclass 23, count 0 2006.286.02:59:09.02#ibcon#read 4, iclass 23, count 0 2006.286.02:59:09.02#ibcon#about to read 5, iclass 23, count 0 2006.286.02:59:09.02#ibcon#read 5, iclass 23, count 0 2006.286.02:59:09.02#ibcon#about to read 6, iclass 23, count 0 2006.286.02:59:09.02#ibcon#read 6, iclass 23, count 0 2006.286.02:59:09.02#ibcon#end of sib2, iclass 23, count 0 2006.286.02:59:09.02#ibcon#*mode == 0, iclass 23, count 0 2006.286.02:59:09.02#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.02:59:09.02#ibcon#[27=USB\r\n] 2006.286.02:59:09.02#ibcon#*before write, iclass 23, count 0 2006.286.02:59:09.02#ibcon#enter sib2, iclass 23, count 0 2006.286.02:59:09.02#ibcon#flushed, iclass 23, count 0 2006.286.02:59:09.02#ibcon#about to write, iclass 23, count 0 2006.286.02:59:09.02#ibcon#wrote, iclass 23, count 0 2006.286.02:59:09.02#ibcon#about to read 3, iclass 23, count 0 2006.286.02:59:09.05#ibcon#read 3, iclass 23, count 0 2006.286.02:59:09.05#ibcon#about to read 4, iclass 23, count 0 2006.286.02:59:09.05#ibcon#read 4, iclass 23, count 0 2006.286.02:59:09.05#ibcon#about to read 5, iclass 23, count 0 2006.286.02:59:09.05#ibcon#read 5, iclass 23, count 0 2006.286.02:59:09.05#ibcon#about to read 6, iclass 23, count 0 2006.286.02:59:09.05#ibcon#read 6, iclass 23, count 0 2006.286.02:59:09.05#ibcon#end of sib2, iclass 23, count 0 2006.286.02:59:09.05#ibcon#*after write, iclass 23, count 0 2006.286.02:59:09.05#ibcon#*before return 0, iclass 23, count 0 2006.286.02:59:09.05#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:59:09.05#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.02:59:09.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.02:59:09.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.02:59:09.05$vck44/vblo=8,744.99 2006.286.02:59:09.05#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.02:59:09.05#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.02:59:09.05#ibcon#ireg 17 cls_cnt 0 2006.286.02:59:09.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:59:09.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:59:09.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:59:09.05#ibcon#enter wrdev, iclass 25, count 0 2006.286.02:59:09.05#ibcon#first serial, iclass 25, count 0 2006.286.02:59:09.05#ibcon#enter sib2, iclass 25, count 0 2006.286.02:59:09.05#ibcon#flushed, iclass 25, count 0 2006.286.02:59:09.05#ibcon#about to write, iclass 25, count 0 2006.286.02:59:09.05#ibcon#wrote, iclass 25, count 0 2006.286.02:59:09.05#ibcon#about to read 3, iclass 25, count 0 2006.286.02:59:09.07#ibcon#read 3, iclass 25, count 0 2006.286.02:59:09.07#ibcon#about to read 4, iclass 25, count 0 2006.286.02:59:09.07#ibcon#read 4, iclass 25, count 0 2006.286.02:59:09.07#ibcon#about to read 5, iclass 25, count 0 2006.286.02:59:09.07#ibcon#read 5, iclass 25, count 0 2006.286.02:59:09.07#ibcon#about to read 6, iclass 25, count 0 2006.286.02:59:09.07#ibcon#read 6, iclass 25, count 0 2006.286.02:59:09.07#ibcon#end of sib2, iclass 25, count 0 2006.286.02:59:09.07#ibcon#*mode == 0, iclass 25, count 0 2006.286.02:59:09.07#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.02:59:09.07#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.02:59:09.07#ibcon#*before write, iclass 25, count 0 2006.286.02:59:09.07#ibcon#enter sib2, iclass 25, count 0 2006.286.02:59:09.07#ibcon#flushed, iclass 25, count 0 2006.286.02:59:09.07#ibcon#about to write, iclass 25, count 0 2006.286.02:59:09.07#ibcon#wrote, iclass 25, count 0 2006.286.02:59:09.07#ibcon#about to read 3, iclass 25, count 0 2006.286.02:59:09.11#ibcon#read 3, iclass 25, count 0 2006.286.02:59:09.11#ibcon#about to read 4, iclass 25, count 0 2006.286.02:59:09.11#ibcon#read 4, iclass 25, count 0 2006.286.02:59:09.11#ibcon#about to read 5, iclass 25, count 0 2006.286.02:59:09.11#ibcon#read 5, iclass 25, count 0 2006.286.02:59:09.11#ibcon#about to read 6, iclass 25, count 0 2006.286.02:59:09.11#ibcon#read 6, iclass 25, count 0 2006.286.02:59:09.11#ibcon#end of sib2, iclass 25, count 0 2006.286.02:59:09.11#ibcon#*after write, iclass 25, count 0 2006.286.02:59:09.11#ibcon#*before return 0, iclass 25, count 0 2006.286.02:59:09.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:59:09.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.02:59:09.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.02:59:09.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.02:59:09.11$vck44/vb=8,4 2006.286.02:59:09.11#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.02:59:09.11#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.02:59:09.11#ibcon#ireg 11 cls_cnt 2 2006.286.02:59:09.11#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:59:09.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:59:09.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:59:09.17#ibcon#enter wrdev, iclass 27, count 2 2006.286.02:59:09.17#ibcon#first serial, iclass 27, count 2 2006.286.02:59:09.17#ibcon#enter sib2, iclass 27, count 2 2006.286.02:59:09.17#ibcon#flushed, iclass 27, count 2 2006.286.02:59:09.17#ibcon#about to write, iclass 27, count 2 2006.286.02:59:09.17#ibcon#wrote, iclass 27, count 2 2006.286.02:59:09.17#ibcon#about to read 3, iclass 27, count 2 2006.286.02:59:09.19#ibcon#read 3, iclass 27, count 2 2006.286.02:59:09.19#ibcon#about to read 4, iclass 27, count 2 2006.286.02:59:09.19#ibcon#read 4, iclass 27, count 2 2006.286.02:59:09.19#ibcon#about to read 5, iclass 27, count 2 2006.286.02:59:09.19#ibcon#read 5, iclass 27, count 2 2006.286.02:59:09.19#ibcon#about to read 6, iclass 27, count 2 2006.286.02:59:09.19#ibcon#read 6, iclass 27, count 2 2006.286.02:59:09.19#ibcon#end of sib2, iclass 27, count 2 2006.286.02:59:09.19#ibcon#*mode == 0, iclass 27, count 2 2006.286.02:59:09.19#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.02:59:09.19#ibcon#[27=AT08-04\r\n] 2006.286.02:59:09.19#ibcon#*before write, iclass 27, count 2 2006.286.02:59:09.19#ibcon#enter sib2, iclass 27, count 2 2006.286.02:59:09.19#ibcon#flushed, iclass 27, count 2 2006.286.02:59:09.19#ibcon#about to write, iclass 27, count 2 2006.286.02:59:09.19#ibcon#wrote, iclass 27, count 2 2006.286.02:59:09.19#ibcon#about to read 3, iclass 27, count 2 2006.286.02:59:09.22#ibcon#read 3, iclass 27, count 2 2006.286.02:59:09.22#ibcon#about to read 4, iclass 27, count 2 2006.286.02:59:09.22#ibcon#read 4, iclass 27, count 2 2006.286.02:59:09.22#ibcon#about to read 5, iclass 27, count 2 2006.286.02:59:09.22#ibcon#read 5, iclass 27, count 2 2006.286.02:59:09.22#ibcon#about to read 6, iclass 27, count 2 2006.286.02:59:09.22#ibcon#read 6, iclass 27, count 2 2006.286.02:59:09.22#ibcon#end of sib2, iclass 27, count 2 2006.286.02:59:09.22#ibcon#*after write, iclass 27, count 2 2006.286.02:59:09.22#ibcon#*before return 0, iclass 27, count 2 2006.286.02:59:09.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:59:09.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.02:59:09.22#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.02:59:09.22#ibcon#ireg 7 cls_cnt 0 2006.286.02:59:09.22#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:59:09.34#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:59:09.34#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:59:09.34#ibcon#enter wrdev, iclass 27, count 0 2006.286.02:59:09.34#ibcon#first serial, iclass 27, count 0 2006.286.02:59:09.34#ibcon#enter sib2, iclass 27, count 0 2006.286.02:59:09.34#ibcon#flushed, iclass 27, count 0 2006.286.02:59:09.34#ibcon#about to write, iclass 27, count 0 2006.286.02:59:09.34#ibcon#wrote, iclass 27, count 0 2006.286.02:59:09.34#ibcon#about to read 3, iclass 27, count 0 2006.286.02:59:09.36#ibcon#read 3, iclass 27, count 0 2006.286.02:59:09.36#ibcon#about to read 4, iclass 27, count 0 2006.286.02:59:09.36#ibcon#read 4, iclass 27, count 0 2006.286.02:59:09.36#ibcon#about to read 5, iclass 27, count 0 2006.286.02:59:09.36#ibcon#read 5, iclass 27, count 0 2006.286.02:59:09.36#ibcon#about to read 6, iclass 27, count 0 2006.286.02:59:09.36#ibcon#read 6, iclass 27, count 0 2006.286.02:59:09.36#ibcon#end of sib2, iclass 27, count 0 2006.286.02:59:09.36#ibcon#*mode == 0, iclass 27, count 0 2006.286.02:59:09.36#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.02:59:09.36#ibcon#[27=USB\r\n] 2006.286.02:59:09.36#ibcon#*before write, iclass 27, count 0 2006.286.02:59:09.36#ibcon#enter sib2, iclass 27, count 0 2006.286.02:59:09.36#ibcon#flushed, iclass 27, count 0 2006.286.02:59:09.36#ibcon#about to write, iclass 27, count 0 2006.286.02:59:09.36#ibcon#wrote, iclass 27, count 0 2006.286.02:59:09.36#ibcon#about to read 3, iclass 27, count 0 2006.286.02:59:09.39#ibcon#read 3, iclass 27, count 0 2006.286.02:59:09.39#ibcon#about to read 4, iclass 27, count 0 2006.286.02:59:09.39#ibcon#read 4, iclass 27, count 0 2006.286.02:59:09.39#ibcon#about to read 5, iclass 27, count 0 2006.286.02:59:09.39#ibcon#read 5, iclass 27, count 0 2006.286.02:59:09.39#ibcon#about to read 6, iclass 27, count 0 2006.286.02:59:09.39#ibcon#read 6, iclass 27, count 0 2006.286.02:59:09.39#ibcon#end of sib2, iclass 27, count 0 2006.286.02:59:09.39#ibcon#*after write, iclass 27, count 0 2006.286.02:59:09.39#ibcon#*before return 0, iclass 27, count 0 2006.286.02:59:09.39#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:59:09.39#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.02:59:09.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.02:59:09.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.02:59:09.39$vck44/vabw=wide 2006.286.02:59:09.39#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.02:59:09.39#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.02:59:09.39#ibcon#ireg 8 cls_cnt 0 2006.286.02:59:09.39#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:59:09.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:59:09.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:59:09.39#ibcon#enter wrdev, iclass 29, count 0 2006.286.02:59:09.39#ibcon#first serial, iclass 29, count 0 2006.286.02:59:09.39#ibcon#enter sib2, iclass 29, count 0 2006.286.02:59:09.39#ibcon#flushed, iclass 29, count 0 2006.286.02:59:09.39#ibcon#about to write, iclass 29, count 0 2006.286.02:59:09.39#ibcon#wrote, iclass 29, count 0 2006.286.02:59:09.39#ibcon#about to read 3, iclass 29, count 0 2006.286.02:59:09.41#ibcon#read 3, iclass 29, count 0 2006.286.02:59:09.41#ibcon#about to read 4, iclass 29, count 0 2006.286.02:59:09.41#ibcon#read 4, iclass 29, count 0 2006.286.02:59:09.41#ibcon#about to read 5, iclass 29, count 0 2006.286.02:59:09.41#ibcon#read 5, iclass 29, count 0 2006.286.02:59:09.41#ibcon#about to read 6, iclass 29, count 0 2006.286.02:59:09.41#ibcon#read 6, iclass 29, count 0 2006.286.02:59:09.41#ibcon#end of sib2, iclass 29, count 0 2006.286.02:59:09.41#ibcon#*mode == 0, iclass 29, count 0 2006.286.02:59:09.41#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.02:59:09.41#ibcon#[25=BW32\r\n] 2006.286.02:59:09.41#ibcon#*before write, iclass 29, count 0 2006.286.02:59:09.41#ibcon#enter sib2, iclass 29, count 0 2006.286.02:59:09.41#ibcon#flushed, iclass 29, count 0 2006.286.02:59:09.41#ibcon#about to write, iclass 29, count 0 2006.286.02:59:09.41#ibcon#wrote, iclass 29, count 0 2006.286.02:59:09.41#ibcon#about to read 3, iclass 29, count 0 2006.286.02:59:09.44#ibcon#read 3, iclass 29, count 0 2006.286.02:59:09.44#ibcon#about to read 4, iclass 29, count 0 2006.286.02:59:09.44#ibcon#read 4, iclass 29, count 0 2006.286.02:59:09.44#ibcon#about to read 5, iclass 29, count 0 2006.286.02:59:09.44#ibcon#read 5, iclass 29, count 0 2006.286.02:59:09.44#ibcon#about to read 6, iclass 29, count 0 2006.286.02:59:09.44#ibcon#read 6, iclass 29, count 0 2006.286.02:59:09.44#ibcon#end of sib2, iclass 29, count 0 2006.286.02:59:09.44#ibcon#*after write, iclass 29, count 0 2006.286.02:59:09.44#ibcon#*before return 0, iclass 29, count 0 2006.286.02:59:09.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:59:09.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.02:59:09.44#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.02:59:09.44#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.02:59:09.44$vck44/vbbw=wide 2006.286.02:59:09.44#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.02:59:09.44#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.02:59:09.44#ibcon#ireg 8 cls_cnt 0 2006.286.02:59:09.44#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:59:09.51#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:59:09.51#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:59:09.51#ibcon#enter wrdev, iclass 31, count 0 2006.286.02:59:09.51#ibcon#first serial, iclass 31, count 0 2006.286.02:59:09.51#ibcon#enter sib2, iclass 31, count 0 2006.286.02:59:09.51#ibcon#flushed, iclass 31, count 0 2006.286.02:59:09.51#ibcon#about to write, iclass 31, count 0 2006.286.02:59:09.51#ibcon#wrote, iclass 31, count 0 2006.286.02:59:09.51#ibcon#about to read 3, iclass 31, count 0 2006.286.02:59:09.53#ibcon#read 3, iclass 31, count 0 2006.286.02:59:09.53#ibcon#about to read 4, iclass 31, count 0 2006.286.02:59:09.53#ibcon#read 4, iclass 31, count 0 2006.286.02:59:09.53#ibcon#about to read 5, iclass 31, count 0 2006.286.02:59:09.53#ibcon#read 5, iclass 31, count 0 2006.286.02:59:09.53#ibcon#about to read 6, iclass 31, count 0 2006.286.02:59:09.53#ibcon#read 6, iclass 31, count 0 2006.286.02:59:09.53#ibcon#end of sib2, iclass 31, count 0 2006.286.02:59:09.53#ibcon#*mode == 0, iclass 31, count 0 2006.286.02:59:09.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.02:59:09.53#ibcon#[27=BW32\r\n] 2006.286.02:59:09.53#ibcon#*before write, iclass 31, count 0 2006.286.02:59:09.53#ibcon#enter sib2, iclass 31, count 0 2006.286.02:59:09.53#ibcon#flushed, iclass 31, count 0 2006.286.02:59:09.53#ibcon#about to write, iclass 31, count 0 2006.286.02:59:09.53#ibcon#wrote, iclass 31, count 0 2006.286.02:59:09.53#ibcon#about to read 3, iclass 31, count 0 2006.286.02:59:09.56#ibcon#read 3, iclass 31, count 0 2006.286.02:59:09.56#ibcon#about to read 4, iclass 31, count 0 2006.286.02:59:09.56#ibcon#read 4, iclass 31, count 0 2006.286.02:59:09.56#ibcon#about to read 5, iclass 31, count 0 2006.286.02:59:09.56#ibcon#read 5, iclass 31, count 0 2006.286.02:59:09.56#ibcon#about to read 6, iclass 31, count 0 2006.286.02:59:09.56#ibcon#read 6, iclass 31, count 0 2006.286.02:59:09.56#ibcon#end of sib2, iclass 31, count 0 2006.286.02:59:09.56#ibcon#*after write, iclass 31, count 0 2006.286.02:59:09.56#ibcon#*before return 0, iclass 31, count 0 2006.286.02:59:09.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:59:09.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.02:59:09.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.02:59:09.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.02:59:09.56$setupk4/ifdk4 2006.286.02:59:09.56$ifdk4/lo= 2006.286.02:59:09.56$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.02:59:09.56$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.02:59:09.56$ifdk4/patch= 2006.286.02:59:09.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.02:59:09.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.02:59:09.68$setupk4/!*+20s 2006.286.02:59:12.50#abcon#<5=/04 2.7 5.0 21.47 791015.5\r\n> 2006.286.02:59:12.52#abcon#{5=INTERFACE CLEAR} 2006.286.02:59:12.58#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:59:22.67#abcon#<5=/04 2.7 5.0 21.48 781015.5\r\n> 2006.286.02:59:22.69#abcon#{5=INTERFACE CLEAR} 2006.286.02:59:22.75#abcon#[5=S1D000X0/0*\r\n] 2006.286.02:59:23.13#trakl#Source acquired 2006.286.02:59:23.15$setupk4/"tpicd 2006.286.02:59:23.15$setupk4/echo=off 2006.286.02:59:23.15$setupk4/xlog=off 2006.286.02:59:23.15:!2006.286.03:03:10 2006.286.02:59:25.13#flagr#flagr/antenna,acquired 2006.286.03:03:10.00:preob 2006.286.03:03:11.14/onsource/TRACKING 2006.286.03:03:11.14:!2006.286.03:03:20 2006.286.03:03:20.00:"tape 2006.286.03:03:20.00:"st=record 2006.286.03:03:20.00:data_valid=on 2006.286.03:03:20.00:midob 2006.286.03:03:20.14/onsource/TRACKING 2006.286.03:03:20.14/wx/21.57,1015.5,78 2006.286.03:03:20.27/cable/+6.4975E-03 2006.286.03:03:21.36/va/01,07,usb,yes,35,37 2006.286.03:03:21.36/va/02,06,usb,yes,35,35 2006.286.03:03:21.36/va/03,07,usb,yes,34,36 2006.286.03:03:21.36/va/04,06,usb,yes,36,37 2006.286.03:03:21.36/va/05,03,usb,yes,35,36 2006.286.03:03:21.36/va/06,04,usb,yes,32,31 2006.286.03:03:21.36/va/07,04,usb,yes,32,33 2006.286.03:03:21.36/va/08,03,usb,yes,33,40 2006.286.03:03:21.59/valo/01,524.99,yes,locked 2006.286.03:03:21.59/valo/02,534.99,yes,locked 2006.286.03:03:21.59/valo/03,564.99,yes,locked 2006.286.03:03:21.59/valo/04,624.99,yes,locked 2006.286.03:03:21.59/valo/05,734.99,yes,locked 2006.286.03:03:21.59/valo/06,814.99,yes,locked 2006.286.03:03:21.59/valo/07,864.99,yes,locked 2006.286.03:03:21.59/valo/08,884.99,yes,locked 2006.286.03:03:22.68/vb/01,04,usb,yes,38,35 2006.286.03:03:22.68/vb/02,05,usb,yes,36,35 2006.286.03:03:22.68/vb/03,04,usb,yes,37,41 2006.286.03:03:22.68/vb/04,05,usb,yes,37,36 2006.286.03:03:22.68/vb/05,04,usb,yes,33,36 2006.286.03:03:22.68/vb/06,03,usb,yes,46,41 2006.286.03:03:22.68/vb/07,04,usb,yes,38,38 2006.286.03:03:22.68/vb/08,04,usb,yes,34,38 2006.286.03:03:22.92/vblo/01,629.99,yes,locked 2006.286.03:03:22.92/vblo/02,634.99,yes,locked 2006.286.03:03:22.92/vblo/03,649.99,yes,locked 2006.286.03:03:22.92/vblo/04,679.99,yes,locked 2006.286.03:03:22.92/vblo/05,709.99,yes,locked 2006.286.03:03:22.92/vblo/06,719.99,yes,locked 2006.286.03:03:22.92/vblo/07,734.99,yes,locked 2006.286.03:03:22.92/vblo/08,744.99,yes,locked 2006.286.03:03:23.07/vabw/8 2006.286.03:03:23.22/vbbw/8 2006.286.03:03:23.31/xfe/off,on,12.2 2006.286.03:03:23.69/ifatt/23,28,28,28 2006.286.03:03:24.08/fmout-gps/S +2.69E-07 2006.286.03:03:24.10:!2006.286.03:04:40 2006.286.03:04:40.01:data_valid=off 2006.286.03:04:40.01:"et 2006.286.03:04:40.01:!+3s 2006.286.03:04:43.02:"tape 2006.286.03:04:43.02:postob 2006.286.03:04:43.11/cable/+6.4997E-03 2006.286.03:04:43.11/wx/21.59,1015.4,80 2006.286.03:04:43.17/fmout-gps/S +2.70E-07 2006.286.03:04:43.17:scan_name=286-0308,jd0610,40 2006.286.03:04:43.17:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.286.03:04:44.14#flagr#flagr/antenna,new-source 2006.286.03:04:44.14:checkk5 2006.286.03:04:44.58/chk_autoobs//k5ts1/ autoobs is running! 2006.286.03:04:45.05/chk_autoobs//k5ts2/ autoobs is running! 2006.286.03:04:45.48/chk_autoobs//k5ts3/ autoobs is running! 2006.286.03:04:45.84/chk_autoobs//k5ts4/ autoobs is running! 2006.286.03:04:46.34/chk_obsdata//k5ts1/T2860303??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.03:04:46.71/chk_obsdata//k5ts2/T2860303??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.03:04:47.20/chk_obsdata//k5ts3/T2860303??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.03:04:47.61/chk_obsdata//k5ts4/T2860303??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.286.03:04:48.58/k5log//k5ts1_log_newline 2006.286.03:04:49.37/k5log//k5ts2_log_newline 2006.286.03:04:50.13/k5log//k5ts3_log_newline 2006.286.03:04:51.30/k5log//k5ts4_log_newline 2006.286.03:04:51.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.03:04:51.32:setupk4=1 2006.286.03:04:51.32$setupk4/echo=on 2006.286.03:04:51.32$setupk4/pcalon 2006.286.03:04:51.32$pcalon/"no phase cal control is implemented here 2006.286.03:04:51.32$setupk4/"tpicd=stop 2006.286.03:04:51.32$setupk4/"rec=synch_on 2006.286.03:04:51.32$setupk4/"rec_mode=128 2006.286.03:04:51.32$setupk4/!* 2006.286.03:04:51.32$setupk4/recpk4 2006.286.03:04:51.32$recpk4/recpatch= 2006.286.03:04:51.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.03:04:51.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.03:04:51.32$setupk4/vck44 2006.286.03:04:51.32$vck44/valo=1,524.99 2006.286.03:04:51.33#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.03:04:51.33#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.03:04:51.33#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:51.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:04:51.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:04:51.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:04:51.33#ibcon#enter wrdev, iclass 28, count 0 2006.286.03:04:51.33#ibcon#first serial, iclass 28, count 0 2006.286.03:04:51.33#ibcon#enter sib2, iclass 28, count 0 2006.286.03:04:51.33#ibcon#flushed, iclass 28, count 0 2006.286.03:04:51.33#ibcon#about to write, iclass 28, count 0 2006.286.03:04:51.33#ibcon#wrote, iclass 28, count 0 2006.286.03:04:51.33#ibcon#about to read 3, iclass 28, count 0 2006.286.03:04:51.35#ibcon#read 3, iclass 28, count 0 2006.286.03:04:51.35#ibcon#about to read 4, iclass 28, count 0 2006.286.03:04:51.35#ibcon#read 4, iclass 28, count 0 2006.286.03:04:51.35#ibcon#about to read 5, iclass 28, count 0 2006.286.03:04:51.35#ibcon#read 5, iclass 28, count 0 2006.286.03:04:51.35#ibcon#about to read 6, iclass 28, count 0 2006.286.03:04:51.35#ibcon#read 6, iclass 28, count 0 2006.286.03:04:51.35#ibcon#end of sib2, iclass 28, count 0 2006.286.03:04:51.35#ibcon#*mode == 0, iclass 28, count 0 2006.286.03:04:51.35#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.03:04:51.35#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.03:04:51.35#ibcon#*before write, iclass 28, count 0 2006.286.03:04:51.35#ibcon#enter sib2, iclass 28, count 0 2006.286.03:04:51.35#ibcon#flushed, iclass 28, count 0 2006.286.03:04:51.35#ibcon#about to write, iclass 28, count 0 2006.286.03:04:51.35#ibcon#wrote, iclass 28, count 0 2006.286.03:04:51.35#ibcon#about to read 3, iclass 28, count 0 2006.286.03:04:51.40#ibcon#read 3, iclass 28, count 0 2006.286.03:04:51.40#ibcon#about to read 4, iclass 28, count 0 2006.286.03:04:51.40#ibcon#read 4, iclass 28, count 0 2006.286.03:04:51.40#ibcon#about to read 5, iclass 28, count 0 2006.286.03:04:51.40#ibcon#read 5, iclass 28, count 0 2006.286.03:04:51.40#ibcon#about to read 6, iclass 28, count 0 2006.286.03:04:51.40#ibcon#read 6, iclass 28, count 0 2006.286.03:04:51.40#ibcon#end of sib2, iclass 28, count 0 2006.286.03:04:51.40#ibcon#*after write, iclass 28, count 0 2006.286.03:04:51.40#ibcon#*before return 0, iclass 28, count 0 2006.286.03:04:51.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:04:51.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:04:51.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.03:04:51.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.03:04:51.40$vck44/va=1,7 2006.286.03:04:51.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.03:04:51.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.03:04:51.40#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:51.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:04:51.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:04:51.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:04:51.40#ibcon#enter wrdev, iclass 30, count 2 2006.286.03:04:51.40#ibcon#first serial, iclass 30, count 2 2006.286.03:04:51.40#ibcon#enter sib2, iclass 30, count 2 2006.286.03:04:51.40#ibcon#flushed, iclass 30, count 2 2006.286.03:04:51.40#ibcon#about to write, iclass 30, count 2 2006.286.03:04:51.40#ibcon#wrote, iclass 30, count 2 2006.286.03:04:51.40#ibcon#about to read 3, iclass 30, count 2 2006.286.03:04:51.42#ibcon#read 3, iclass 30, count 2 2006.286.03:04:51.42#ibcon#about to read 4, iclass 30, count 2 2006.286.03:04:51.42#ibcon#read 4, iclass 30, count 2 2006.286.03:04:51.42#ibcon#about to read 5, iclass 30, count 2 2006.286.03:04:51.42#ibcon#read 5, iclass 30, count 2 2006.286.03:04:51.42#ibcon#about to read 6, iclass 30, count 2 2006.286.03:04:51.42#ibcon#read 6, iclass 30, count 2 2006.286.03:04:51.42#ibcon#end of sib2, iclass 30, count 2 2006.286.03:04:51.42#ibcon#*mode == 0, iclass 30, count 2 2006.286.03:04:51.42#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.03:04:51.42#ibcon#[25=AT01-07\r\n] 2006.286.03:04:51.42#ibcon#*before write, iclass 30, count 2 2006.286.03:04:51.42#ibcon#enter sib2, iclass 30, count 2 2006.286.03:04:51.42#ibcon#flushed, iclass 30, count 2 2006.286.03:04:51.42#ibcon#about to write, iclass 30, count 2 2006.286.03:04:51.42#ibcon#wrote, iclass 30, count 2 2006.286.03:04:51.42#ibcon#about to read 3, iclass 30, count 2 2006.286.03:04:51.45#ibcon#read 3, iclass 30, count 2 2006.286.03:04:51.45#ibcon#about to read 4, iclass 30, count 2 2006.286.03:04:51.45#ibcon#read 4, iclass 30, count 2 2006.286.03:04:51.45#ibcon#about to read 5, iclass 30, count 2 2006.286.03:04:51.45#ibcon#read 5, iclass 30, count 2 2006.286.03:04:51.45#ibcon#about to read 6, iclass 30, count 2 2006.286.03:04:51.45#ibcon#read 6, iclass 30, count 2 2006.286.03:04:51.45#ibcon#end of sib2, iclass 30, count 2 2006.286.03:04:51.45#ibcon#*after write, iclass 30, count 2 2006.286.03:04:51.45#ibcon#*before return 0, iclass 30, count 2 2006.286.03:04:51.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:04:51.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:04:51.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.03:04:51.45#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:51.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:04:51.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:04:51.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:04:51.57#ibcon#enter wrdev, iclass 30, count 0 2006.286.03:04:51.57#ibcon#first serial, iclass 30, count 0 2006.286.03:04:51.57#ibcon#enter sib2, iclass 30, count 0 2006.286.03:04:51.57#ibcon#flushed, iclass 30, count 0 2006.286.03:04:51.57#ibcon#about to write, iclass 30, count 0 2006.286.03:04:51.57#ibcon#wrote, iclass 30, count 0 2006.286.03:04:51.57#ibcon#about to read 3, iclass 30, count 0 2006.286.03:04:51.59#ibcon#read 3, iclass 30, count 0 2006.286.03:04:51.59#ibcon#about to read 4, iclass 30, count 0 2006.286.03:04:51.59#ibcon#read 4, iclass 30, count 0 2006.286.03:04:51.59#ibcon#about to read 5, iclass 30, count 0 2006.286.03:04:51.59#ibcon#read 5, iclass 30, count 0 2006.286.03:04:51.59#ibcon#about to read 6, iclass 30, count 0 2006.286.03:04:51.59#ibcon#read 6, iclass 30, count 0 2006.286.03:04:51.59#ibcon#end of sib2, iclass 30, count 0 2006.286.03:04:51.59#ibcon#*mode == 0, iclass 30, count 0 2006.286.03:04:51.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.03:04:51.59#ibcon#[25=USB\r\n] 2006.286.03:04:51.59#ibcon#*before write, iclass 30, count 0 2006.286.03:04:51.59#ibcon#enter sib2, iclass 30, count 0 2006.286.03:04:51.59#ibcon#flushed, iclass 30, count 0 2006.286.03:04:51.59#ibcon#about to write, iclass 30, count 0 2006.286.03:04:51.59#ibcon#wrote, iclass 30, count 0 2006.286.03:04:51.59#ibcon#about to read 3, iclass 30, count 0 2006.286.03:04:51.62#ibcon#read 3, iclass 30, count 0 2006.286.03:04:51.62#ibcon#about to read 4, iclass 30, count 0 2006.286.03:04:51.62#ibcon#read 4, iclass 30, count 0 2006.286.03:04:51.62#ibcon#about to read 5, iclass 30, count 0 2006.286.03:04:51.62#ibcon#read 5, iclass 30, count 0 2006.286.03:04:51.62#ibcon#about to read 6, iclass 30, count 0 2006.286.03:04:51.62#ibcon#read 6, iclass 30, count 0 2006.286.03:04:51.62#ibcon#end of sib2, iclass 30, count 0 2006.286.03:04:51.62#ibcon#*after write, iclass 30, count 0 2006.286.03:04:51.62#ibcon#*before return 0, iclass 30, count 0 2006.286.03:04:51.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:04:51.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:04:51.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.03:04:51.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.03:04:51.62$vck44/valo=2,534.99 2006.286.03:04:51.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.03:04:51.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.03:04:51.62#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:51.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:04:51.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:04:51.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:04:51.62#ibcon#enter wrdev, iclass 32, count 0 2006.286.03:04:51.62#ibcon#first serial, iclass 32, count 0 2006.286.03:04:51.62#ibcon#enter sib2, iclass 32, count 0 2006.286.03:04:51.62#ibcon#flushed, iclass 32, count 0 2006.286.03:04:51.62#ibcon#about to write, iclass 32, count 0 2006.286.03:04:51.62#ibcon#wrote, iclass 32, count 0 2006.286.03:04:51.62#ibcon#about to read 3, iclass 32, count 0 2006.286.03:04:51.64#ibcon#read 3, iclass 32, count 0 2006.286.03:04:51.64#ibcon#about to read 4, iclass 32, count 0 2006.286.03:04:51.64#ibcon#read 4, iclass 32, count 0 2006.286.03:04:51.64#ibcon#about to read 5, iclass 32, count 0 2006.286.03:04:51.64#ibcon#read 5, iclass 32, count 0 2006.286.03:04:51.64#ibcon#about to read 6, iclass 32, count 0 2006.286.03:04:51.64#ibcon#read 6, iclass 32, count 0 2006.286.03:04:51.64#ibcon#end of sib2, iclass 32, count 0 2006.286.03:04:51.64#ibcon#*mode == 0, iclass 32, count 0 2006.286.03:04:51.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.03:04:51.64#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.03:04:51.64#ibcon#*before write, iclass 32, count 0 2006.286.03:04:51.64#ibcon#enter sib2, iclass 32, count 0 2006.286.03:04:51.64#ibcon#flushed, iclass 32, count 0 2006.286.03:04:51.64#ibcon#about to write, iclass 32, count 0 2006.286.03:04:51.64#ibcon#wrote, iclass 32, count 0 2006.286.03:04:51.64#ibcon#about to read 3, iclass 32, count 0 2006.286.03:04:51.68#ibcon#read 3, iclass 32, count 0 2006.286.03:04:51.68#ibcon#about to read 4, iclass 32, count 0 2006.286.03:04:51.68#ibcon#read 4, iclass 32, count 0 2006.286.03:04:51.68#ibcon#about to read 5, iclass 32, count 0 2006.286.03:04:51.68#ibcon#read 5, iclass 32, count 0 2006.286.03:04:51.68#ibcon#about to read 6, iclass 32, count 0 2006.286.03:04:51.68#ibcon#read 6, iclass 32, count 0 2006.286.03:04:51.68#ibcon#end of sib2, iclass 32, count 0 2006.286.03:04:51.68#ibcon#*after write, iclass 32, count 0 2006.286.03:04:51.68#ibcon#*before return 0, iclass 32, count 0 2006.286.03:04:51.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:04:51.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:04:51.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.03:04:51.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.03:04:51.68$vck44/va=2,6 2006.286.03:04:51.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.03:04:51.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.03:04:51.68#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:51.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:04:51.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:04:51.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:04:51.74#ibcon#enter wrdev, iclass 34, count 2 2006.286.03:04:51.74#ibcon#first serial, iclass 34, count 2 2006.286.03:04:51.74#ibcon#enter sib2, iclass 34, count 2 2006.286.03:04:51.74#ibcon#flushed, iclass 34, count 2 2006.286.03:04:51.74#ibcon#about to write, iclass 34, count 2 2006.286.03:04:51.74#ibcon#wrote, iclass 34, count 2 2006.286.03:04:51.74#ibcon#about to read 3, iclass 34, count 2 2006.286.03:04:51.76#ibcon#read 3, iclass 34, count 2 2006.286.03:04:51.76#ibcon#about to read 4, iclass 34, count 2 2006.286.03:04:51.76#ibcon#read 4, iclass 34, count 2 2006.286.03:04:51.76#ibcon#about to read 5, iclass 34, count 2 2006.286.03:04:51.76#ibcon#read 5, iclass 34, count 2 2006.286.03:04:51.76#ibcon#about to read 6, iclass 34, count 2 2006.286.03:04:51.76#ibcon#read 6, iclass 34, count 2 2006.286.03:04:51.76#ibcon#end of sib2, iclass 34, count 2 2006.286.03:04:51.76#ibcon#*mode == 0, iclass 34, count 2 2006.286.03:04:51.76#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.03:04:51.76#ibcon#[25=AT02-06\r\n] 2006.286.03:04:51.76#ibcon#*before write, iclass 34, count 2 2006.286.03:04:51.76#ibcon#enter sib2, iclass 34, count 2 2006.286.03:04:51.76#ibcon#flushed, iclass 34, count 2 2006.286.03:04:51.76#ibcon#about to write, iclass 34, count 2 2006.286.03:04:51.76#ibcon#wrote, iclass 34, count 2 2006.286.03:04:51.76#ibcon#about to read 3, iclass 34, count 2 2006.286.03:04:51.79#ibcon#read 3, iclass 34, count 2 2006.286.03:04:51.79#ibcon#about to read 4, iclass 34, count 2 2006.286.03:04:51.79#ibcon#read 4, iclass 34, count 2 2006.286.03:04:51.79#ibcon#about to read 5, iclass 34, count 2 2006.286.03:04:51.79#ibcon#read 5, iclass 34, count 2 2006.286.03:04:51.79#ibcon#about to read 6, iclass 34, count 2 2006.286.03:04:51.79#ibcon#read 6, iclass 34, count 2 2006.286.03:04:51.79#ibcon#end of sib2, iclass 34, count 2 2006.286.03:04:51.79#ibcon#*after write, iclass 34, count 2 2006.286.03:04:51.79#ibcon#*before return 0, iclass 34, count 2 2006.286.03:04:51.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:04:51.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:04:51.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.03:04:51.79#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:51.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:04:51.91#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:04:51.91#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:04:51.91#ibcon#enter wrdev, iclass 34, count 0 2006.286.03:04:51.91#ibcon#first serial, iclass 34, count 0 2006.286.03:04:51.91#ibcon#enter sib2, iclass 34, count 0 2006.286.03:04:51.91#ibcon#flushed, iclass 34, count 0 2006.286.03:04:51.91#ibcon#about to write, iclass 34, count 0 2006.286.03:04:51.91#ibcon#wrote, iclass 34, count 0 2006.286.03:04:51.91#ibcon#about to read 3, iclass 34, count 0 2006.286.03:04:51.93#ibcon#read 3, iclass 34, count 0 2006.286.03:04:51.93#ibcon#about to read 4, iclass 34, count 0 2006.286.03:04:51.93#ibcon#read 4, iclass 34, count 0 2006.286.03:04:51.93#ibcon#about to read 5, iclass 34, count 0 2006.286.03:04:51.93#ibcon#read 5, iclass 34, count 0 2006.286.03:04:51.93#ibcon#about to read 6, iclass 34, count 0 2006.286.03:04:51.93#ibcon#read 6, iclass 34, count 0 2006.286.03:04:51.93#ibcon#end of sib2, iclass 34, count 0 2006.286.03:04:51.93#ibcon#*mode == 0, iclass 34, count 0 2006.286.03:04:51.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.03:04:51.93#ibcon#[25=USB\r\n] 2006.286.03:04:51.93#ibcon#*before write, iclass 34, count 0 2006.286.03:04:51.93#ibcon#enter sib2, iclass 34, count 0 2006.286.03:04:51.93#ibcon#flushed, iclass 34, count 0 2006.286.03:04:51.93#ibcon#about to write, iclass 34, count 0 2006.286.03:04:51.93#ibcon#wrote, iclass 34, count 0 2006.286.03:04:51.93#ibcon#about to read 3, iclass 34, count 0 2006.286.03:04:51.96#ibcon#read 3, iclass 34, count 0 2006.286.03:04:51.96#ibcon#about to read 4, iclass 34, count 0 2006.286.03:04:51.96#ibcon#read 4, iclass 34, count 0 2006.286.03:04:51.96#ibcon#about to read 5, iclass 34, count 0 2006.286.03:04:51.96#ibcon#read 5, iclass 34, count 0 2006.286.03:04:51.96#ibcon#about to read 6, iclass 34, count 0 2006.286.03:04:51.96#ibcon#read 6, iclass 34, count 0 2006.286.03:04:51.96#ibcon#end of sib2, iclass 34, count 0 2006.286.03:04:51.96#ibcon#*after write, iclass 34, count 0 2006.286.03:04:51.96#ibcon#*before return 0, iclass 34, count 0 2006.286.03:04:51.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:04:51.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:04:51.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.03:04:51.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.03:04:51.96$vck44/valo=3,564.99 2006.286.03:04:51.96#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.03:04:51.96#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.03:04:51.96#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:51.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:04:51.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:04:51.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:04:51.96#ibcon#enter wrdev, iclass 36, count 0 2006.286.03:04:51.96#ibcon#first serial, iclass 36, count 0 2006.286.03:04:51.96#ibcon#enter sib2, iclass 36, count 0 2006.286.03:04:51.96#ibcon#flushed, iclass 36, count 0 2006.286.03:04:51.96#ibcon#about to write, iclass 36, count 0 2006.286.03:04:51.96#ibcon#wrote, iclass 36, count 0 2006.286.03:04:51.96#ibcon#about to read 3, iclass 36, count 0 2006.286.03:04:51.98#ibcon#read 3, iclass 36, count 0 2006.286.03:04:52.34#ibcon#about to read 4, iclass 36, count 0 2006.286.03:04:52.34#ibcon#read 4, iclass 36, count 0 2006.286.03:04:52.34#ibcon#about to read 5, iclass 36, count 0 2006.286.03:04:52.34#ibcon#read 5, iclass 36, count 0 2006.286.03:04:52.34#ibcon#about to read 6, iclass 36, count 0 2006.286.03:04:52.34#ibcon#read 6, iclass 36, count 0 2006.286.03:04:52.34#ibcon#end of sib2, iclass 36, count 0 2006.286.03:04:52.34#ibcon#*mode == 0, iclass 36, count 0 2006.286.03:04:52.34#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.03:04:52.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.03:04:52.34#ibcon#*before write, iclass 36, count 0 2006.286.03:04:52.34#ibcon#enter sib2, iclass 36, count 0 2006.286.03:04:52.34#ibcon#flushed, iclass 36, count 0 2006.286.03:04:52.34#ibcon#about to write, iclass 36, count 0 2006.286.03:04:52.34#ibcon#wrote, iclass 36, count 0 2006.286.03:04:52.34#ibcon#about to read 3, iclass 36, count 0 2006.286.03:04:52.39#ibcon#read 3, iclass 36, count 0 2006.286.03:04:52.39#ibcon#about to read 4, iclass 36, count 0 2006.286.03:04:52.39#ibcon#read 4, iclass 36, count 0 2006.286.03:04:52.39#ibcon#about to read 5, iclass 36, count 0 2006.286.03:04:52.39#ibcon#read 5, iclass 36, count 0 2006.286.03:04:52.39#ibcon#about to read 6, iclass 36, count 0 2006.286.03:04:52.39#ibcon#read 6, iclass 36, count 0 2006.286.03:04:52.39#ibcon#end of sib2, iclass 36, count 0 2006.286.03:04:52.39#ibcon#*after write, iclass 36, count 0 2006.286.03:04:52.39#ibcon#*before return 0, iclass 36, count 0 2006.286.03:04:52.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:04:52.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:04:52.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.03:04:52.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.03:04:52.39$vck44/va=3,7 2006.286.03:04:52.39#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.03:04:52.39#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.03:04:52.39#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:52.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:04:52.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:04:52.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:04:52.39#ibcon#enter wrdev, iclass 38, count 2 2006.286.03:04:52.39#ibcon#first serial, iclass 38, count 2 2006.286.03:04:52.39#ibcon#enter sib2, iclass 38, count 2 2006.286.03:04:52.39#ibcon#flushed, iclass 38, count 2 2006.286.03:04:52.39#ibcon#about to write, iclass 38, count 2 2006.286.03:04:52.39#ibcon#wrote, iclass 38, count 2 2006.286.03:04:52.39#ibcon#about to read 3, iclass 38, count 2 2006.286.03:04:52.41#ibcon#read 3, iclass 38, count 2 2006.286.03:04:52.41#ibcon#about to read 4, iclass 38, count 2 2006.286.03:04:52.41#ibcon#read 4, iclass 38, count 2 2006.286.03:04:52.41#ibcon#about to read 5, iclass 38, count 2 2006.286.03:04:52.41#ibcon#read 5, iclass 38, count 2 2006.286.03:04:52.41#ibcon#about to read 6, iclass 38, count 2 2006.286.03:04:52.41#ibcon#read 6, iclass 38, count 2 2006.286.03:04:52.41#ibcon#end of sib2, iclass 38, count 2 2006.286.03:04:52.41#ibcon#*mode == 0, iclass 38, count 2 2006.286.03:04:52.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.03:04:52.41#ibcon#[25=AT03-07\r\n] 2006.286.03:04:52.41#ibcon#*before write, iclass 38, count 2 2006.286.03:04:52.41#ibcon#enter sib2, iclass 38, count 2 2006.286.03:04:52.41#ibcon#flushed, iclass 38, count 2 2006.286.03:04:52.41#ibcon#about to write, iclass 38, count 2 2006.286.03:04:52.41#ibcon#wrote, iclass 38, count 2 2006.286.03:04:52.41#ibcon#about to read 3, iclass 38, count 2 2006.286.03:04:52.44#ibcon#read 3, iclass 38, count 2 2006.286.03:04:52.44#ibcon#about to read 4, iclass 38, count 2 2006.286.03:04:52.44#ibcon#read 4, iclass 38, count 2 2006.286.03:04:52.44#ibcon#about to read 5, iclass 38, count 2 2006.286.03:04:52.44#ibcon#read 5, iclass 38, count 2 2006.286.03:04:52.44#ibcon#about to read 6, iclass 38, count 2 2006.286.03:04:52.44#ibcon#read 6, iclass 38, count 2 2006.286.03:04:52.44#ibcon#end of sib2, iclass 38, count 2 2006.286.03:04:52.44#ibcon#*after write, iclass 38, count 2 2006.286.03:04:52.44#ibcon#*before return 0, iclass 38, count 2 2006.286.03:04:52.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:04:52.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:04:52.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.03:04:52.44#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:52.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:04:52.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:04:52.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:04:52.56#ibcon#enter wrdev, iclass 38, count 0 2006.286.03:04:52.56#ibcon#first serial, iclass 38, count 0 2006.286.03:04:52.56#ibcon#enter sib2, iclass 38, count 0 2006.286.03:04:52.56#ibcon#flushed, iclass 38, count 0 2006.286.03:04:52.56#ibcon#about to write, iclass 38, count 0 2006.286.03:04:52.56#ibcon#wrote, iclass 38, count 0 2006.286.03:04:52.56#ibcon#about to read 3, iclass 38, count 0 2006.286.03:04:52.58#ibcon#read 3, iclass 38, count 0 2006.286.03:04:52.58#ibcon#about to read 4, iclass 38, count 0 2006.286.03:04:52.58#ibcon#read 4, iclass 38, count 0 2006.286.03:04:52.58#ibcon#about to read 5, iclass 38, count 0 2006.286.03:04:52.58#ibcon#read 5, iclass 38, count 0 2006.286.03:04:52.58#ibcon#about to read 6, iclass 38, count 0 2006.286.03:04:52.58#ibcon#read 6, iclass 38, count 0 2006.286.03:04:52.58#ibcon#end of sib2, iclass 38, count 0 2006.286.03:04:52.58#ibcon#*mode == 0, iclass 38, count 0 2006.286.03:04:52.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.03:04:52.58#ibcon#[25=USB\r\n] 2006.286.03:04:52.58#ibcon#*before write, iclass 38, count 0 2006.286.03:04:52.58#ibcon#enter sib2, iclass 38, count 0 2006.286.03:04:52.58#ibcon#flushed, iclass 38, count 0 2006.286.03:04:52.58#ibcon#about to write, iclass 38, count 0 2006.286.03:04:52.58#ibcon#wrote, iclass 38, count 0 2006.286.03:04:52.58#ibcon#about to read 3, iclass 38, count 0 2006.286.03:04:52.61#ibcon#read 3, iclass 38, count 0 2006.286.03:04:52.61#ibcon#about to read 4, iclass 38, count 0 2006.286.03:04:52.61#ibcon#read 4, iclass 38, count 0 2006.286.03:04:52.61#ibcon#about to read 5, iclass 38, count 0 2006.286.03:04:52.61#ibcon#read 5, iclass 38, count 0 2006.286.03:04:52.61#ibcon#about to read 6, iclass 38, count 0 2006.286.03:04:52.61#ibcon#read 6, iclass 38, count 0 2006.286.03:04:52.61#ibcon#end of sib2, iclass 38, count 0 2006.286.03:04:52.61#ibcon#*after write, iclass 38, count 0 2006.286.03:04:52.61#ibcon#*before return 0, iclass 38, count 0 2006.286.03:04:52.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:04:52.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:04:52.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.03:04:52.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.03:04:52.61$vck44/valo=4,624.99 2006.286.03:04:52.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.03:04:52.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.03:04:52.61#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:52.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:04:52.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:04:52.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:04:52.61#ibcon#enter wrdev, iclass 40, count 0 2006.286.03:04:52.61#ibcon#first serial, iclass 40, count 0 2006.286.03:04:52.61#ibcon#enter sib2, iclass 40, count 0 2006.286.03:04:52.61#ibcon#flushed, iclass 40, count 0 2006.286.03:04:52.61#ibcon#about to write, iclass 40, count 0 2006.286.03:04:52.61#ibcon#wrote, iclass 40, count 0 2006.286.03:04:52.61#ibcon#about to read 3, iclass 40, count 0 2006.286.03:04:52.63#ibcon#read 3, iclass 40, count 0 2006.286.03:04:52.63#ibcon#about to read 4, iclass 40, count 0 2006.286.03:04:52.63#ibcon#read 4, iclass 40, count 0 2006.286.03:04:52.63#ibcon#about to read 5, iclass 40, count 0 2006.286.03:04:52.63#ibcon#read 5, iclass 40, count 0 2006.286.03:04:52.63#ibcon#about to read 6, iclass 40, count 0 2006.286.03:04:52.63#ibcon#read 6, iclass 40, count 0 2006.286.03:04:52.63#ibcon#end of sib2, iclass 40, count 0 2006.286.03:04:52.63#ibcon#*mode == 0, iclass 40, count 0 2006.286.03:04:52.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.03:04:52.63#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.03:04:52.63#ibcon#*before write, iclass 40, count 0 2006.286.03:04:52.63#ibcon#enter sib2, iclass 40, count 0 2006.286.03:04:52.63#ibcon#flushed, iclass 40, count 0 2006.286.03:04:52.63#ibcon#about to write, iclass 40, count 0 2006.286.03:04:52.63#ibcon#wrote, iclass 40, count 0 2006.286.03:04:52.63#ibcon#about to read 3, iclass 40, count 0 2006.286.03:04:52.67#ibcon#read 3, iclass 40, count 0 2006.286.03:04:52.67#ibcon#about to read 4, iclass 40, count 0 2006.286.03:04:52.67#ibcon#read 4, iclass 40, count 0 2006.286.03:04:52.67#ibcon#about to read 5, iclass 40, count 0 2006.286.03:04:52.67#ibcon#read 5, iclass 40, count 0 2006.286.03:04:52.67#ibcon#about to read 6, iclass 40, count 0 2006.286.03:04:52.67#ibcon#read 6, iclass 40, count 0 2006.286.03:04:52.67#ibcon#end of sib2, iclass 40, count 0 2006.286.03:04:52.67#ibcon#*after write, iclass 40, count 0 2006.286.03:04:52.67#ibcon#*before return 0, iclass 40, count 0 2006.286.03:04:52.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:04:52.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:04:52.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.03:04:52.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.03:04:52.67$vck44/va=4,6 2006.286.03:04:52.67#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.03:04:52.67#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.03:04:52.67#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:52.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:04:52.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:04:52.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:04:52.73#ibcon#enter wrdev, iclass 4, count 2 2006.286.03:04:52.73#ibcon#first serial, iclass 4, count 2 2006.286.03:04:52.73#ibcon#enter sib2, iclass 4, count 2 2006.286.03:04:52.73#ibcon#flushed, iclass 4, count 2 2006.286.03:04:52.73#ibcon#about to write, iclass 4, count 2 2006.286.03:04:52.73#ibcon#wrote, iclass 4, count 2 2006.286.03:04:52.73#ibcon#about to read 3, iclass 4, count 2 2006.286.03:04:52.75#ibcon#read 3, iclass 4, count 2 2006.286.03:04:52.75#ibcon#about to read 4, iclass 4, count 2 2006.286.03:04:52.75#ibcon#read 4, iclass 4, count 2 2006.286.03:04:52.75#ibcon#about to read 5, iclass 4, count 2 2006.286.03:04:52.75#ibcon#read 5, iclass 4, count 2 2006.286.03:04:52.75#ibcon#about to read 6, iclass 4, count 2 2006.286.03:04:52.75#ibcon#read 6, iclass 4, count 2 2006.286.03:04:52.75#ibcon#end of sib2, iclass 4, count 2 2006.286.03:04:52.75#ibcon#*mode == 0, iclass 4, count 2 2006.286.03:04:52.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.03:04:52.75#ibcon#[25=AT04-06\r\n] 2006.286.03:04:52.75#ibcon#*before write, iclass 4, count 2 2006.286.03:04:52.75#ibcon#enter sib2, iclass 4, count 2 2006.286.03:04:52.75#ibcon#flushed, iclass 4, count 2 2006.286.03:04:52.75#ibcon#about to write, iclass 4, count 2 2006.286.03:04:52.75#ibcon#wrote, iclass 4, count 2 2006.286.03:04:52.75#ibcon#about to read 3, iclass 4, count 2 2006.286.03:04:52.78#ibcon#read 3, iclass 4, count 2 2006.286.03:04:53.06#ibcon#about to read 4, iclass 4, count 2 2006.286.03:04:53.06#ibcon#read 4, iclass 4, count 2 2006.286.03:04:53.06#ibcon#about to read 5, iclass 4, count 2 2006.286.03:04:53.06#ibcon#read 5, iclass 4, count 2 2006.286.03:04:53.06#ibcon#about to read 6, iclass 4, count 2 2006.286.03:04:53.06#ibcon#read 6, iclass 4, count 2 2006.286.03:04:53.06#ibcon#end of sib2, iclass 4, count 2 2006.286.03:04:53.06#ibcon#*after write, iclass 4, count 2 2006.286.03:04:53.06#ibcon#*before return 0, iclass 4, count 2 2006.286.03:04:53.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:04:53.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:04:53.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.03:04:53.06#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:53.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:04:53.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:04:53.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:04:53.18#ibcon#enter wrdev, iclass 4, count 0 2006.286.03:04:53.18#ibcon#first serial, iclass 4, count 0 2006.286.03:04:53.18#ibcon#enter sib2, iclass 4, count 0 2006.286.03:04:53.18#ibcon#flushed, iclass 4, count 0 2006.286.03:04:53.18#ibcon#about to write, iclass 4, count 0 2006.286.03:04:53.18#ibcon#wrote, iclass 4, count 0 2006.286.03:04:53.18#ibcon#about to read 3, iclass 4, count 0 2006.286.03:04:53.20#ibcon#read 3, iclass 4, count 0 2006.286.03:04:53.20#ibcon#about to read 4, iclass 4, count 0 2006.286.03:04:53.20#ibcon#read 4, iclass 4, count 0 2006.286.03:04:53.20#ibcon#about to read 5, iclass 4, count 0 2006.286.03:04:53.20#ibcon#read 5, iclass 4, count 0 2006.286.03:04:53.20#ibcon#about to read 6, iclass 4, count 0 2006.286.03:04:53.20#ibcon#read 6, iclass 4, count 0 2006.286.03:04:53.20#ibcon#end of sib2, iclass 4, count 0 2006.286.03:04:53.20#ibcon#*mode == 0, iclass 4, count 0 2006.286.03:04:53.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.03:04:53.20#ibcon#[25=USB\r\n] 2006.286.03:04:53.20#ibcon#*before write, iclass 4, count 0 2006.286.03:04:53.20#ibcon#enter sib2, iclass 4, count 0 2006.286.03:04:53.20#ibcon#flushed, iclass 4, count 0 2006.286.03:04:53.20#ibcon#about to write, iclass 4, count 0 2006.286.03:04:53.20#ibcon#wrote, iclass 4, count 0 2006.286.03:04:53.20#ibcon#about to read 3, iclass 4, count 0 2006.286.03:04:53.23#ibcon#read 3, iclass 4, count 0 2006.286.03:04:53.23#ibcon#about to read 4, iclass 4, count 0 2006.286.03:04:53.23#ibcon#read 4, iclass 4, count 0 2006.286.03:04:53.23#ibcon#about to read 5, iclass 4, count 0 2006.286.03:04:53.23#ibcon#read 5, iclass 4, count 0 2006.286.03:04:53.23#ibcon#about to read 6, iclass 4, count 0 2006.286.03:04:53.23#ibcon#read 6, iclass 4, count 0 2006.286.03:04:53.23#ibcon#end of sib2, iclass 4, count 0 2006.286.03:04:53.23#ibcon#*after write, iclass 4, count 0 2006.286.03:04:53.23#ibcon#*before return 0, iclass 4, count 0 2006.286.03:04:53.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:04:53.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:04:53.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.03:04:53.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.03:04:53.23$vck44/valo=5,734.99 2006.286.03:04:53.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.03:04:53.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.03:04:53.23#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:53.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:04:53.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:04:53.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:04:53.23#ibcon#enter wrdev, iclass 6, count 0 2006.286.03:04:53.23#ibcon#first serial, iclass 6, count 0 2006.286.03:04:53.23#ibcon#enter sib2, iclass 6, count 0 2006.286.03:04:53.23#ibcon#flushed, iclass 6, count 0 2006.286.03:04:53.23#ibcon#about to write, iclass 6, count 0 2006.286.03:04:53.23#ibcon#wrote, iclass 6, count 0 2006.286.03:04:53.23#ibcon#about to read 3, iclass 6, count 0 2006.286.03:04:53.25#ibcon#read 3, iclass 6, count 0 2006.286.03:04:53.25#ibcon#about to read 4, iclass 6, count 0 2006.286.03:04:53.36#ibcon#read 4, iclass 6, count 0 2006.286.03:04:53.36#ibcon#about to read 5, iclass 6, count 0 2006.286.03:04:53.36#ibcon#read 5, iclass 6, count 0 2006.286.03:04:53.36#ibcon#about to read 6, iclass 6, count 0 2006.286.03:04:53.36#ibcon#read 6, iclass 6, count 0 2006.286.03:04:53.36#ibcon#end of sib2, iclass 6, count 0 2006.286.03:04:53.36#ibcon#*mode == 0, iclass 6, count 0 2006.286.03:04:53.36#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.03:04:53.36#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.03:04:53.36#ibcon#*before write, iclass 6, count 0 2006.286.03:04:53.36#ibcon#enter sib2, iclass 6, count 0 2006.286.03:04:53.36#ibcon#flushed, iclass 6, count 0 2006.286.03:04:53.36#ibcon#about to write, iclass 6, count 0 2006.286.03:04:53.36#ibcon#wrote, iclass 6, count 0 2006.286.03:04:53.36#ibcon#about to read 3, iclass 6, count 0 2006.286.03:04:53.40#ibcon#read 3, iclass 6, count 0 2006.286.03:04:53.40#ibcon#about to read 4, iclass 6, count 0 2006.286.03:04:53.40#ibcon#read 4, iclass 6, count 0 2006.286.03:04:53.40#ibcon#about to read 5, iclass 6, count 0 2006.286.03:04:53.40#ibcon#read 5, iclass 6, count 0 2006.286.03:04:53.40#ibcon#about to read 6, iclass 6, count 0 2006.286.03:04:53.40#ibcon#read 6, iclass 6, count 0 2006.286.03:04:53.40#ibcon#end of sib2, iclass 6, count 0 2006.286.03:04:53.40#ibcon#*after write, iclass 6, count 0 2006.286.03:04:53.40#ibcon#*before return 0, iclass 6, count 0 2006.286.03:04:53.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:04:53.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:04:53.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.03:04:53.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.03:04:53.40$vck44/va=5,3 2006.286.03:04:53.40#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.03:04:53.40#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.03:04:53.40#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:53.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:04:53.40#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:04:53.40#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:04:53.40#ibcon#enter wrdev, iclass 10, count 2 2006.286.03:04:53.40#ibcon#first serial, iclass 10, count 2 2006.286.03:04:53.40#ibcon#enter sib2, iclass 10, count 2 2006.286.03:04:53.40#ibcon#flushed, iclass 10, count 2 2006.286.03:04:53.40#ibcon#about to write, iclass 10, count 2 2006.286.03:04:53.40#ibcon#wrote, iclass 10, count 2 2006.286.03:04:53.40#ibcon#about to read 3, iclass 10, count 2 2006.286.03:04:53.42#ibcon#read 3, iclass 10, count 2 2006.286.03:04:53.42#ibcon#about to read 4, iclass 10, count 2 2006.286.03:04:53.42#ibcon#read 4, iclass 10, count 2 2006.286.03:04:53.42#ibcon#about to read 5, iclass 10, count 2 2006.286.03:04:53.42#ibcon#read 5, iclass 10, count 2 2006.286.03:04:53.42#ibcon#about to read 6, iclass 10, count 2 2006.286.03:04:53.42#ibcon#read 6, iclass 10, count 2 2006.286.03:04:53.42#ibcon#end of sib2, iclass 10, count 2 2006.286.03:04:53.42#ibcon#*mode == 0, iclass 10, count 2 2006.286.03:04:53.42#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.03:04:53.42#ibcon#[25=AT05-03\r\n] 2006.286.03:04:53.42#ibcon#*before write, iclass 10, count 2 2006.286.03:04:53.42#ibcon#enter sib2, iclass 10, count 2 2006.286.03:04:53.42#ibcon#flushed, iclass 10, count 2 2006.286.03:04:53.42#ibcon#about to write, iclass 10, count 2 2006.286.03:04:53.42#ibcon#wrote, iclass 10, count 2 2006.286.03:04:53.42#ibcon#about to read 3, iclass 10, count 2 2006.286.03:04:53.45#ibcon#read 3, iclass 10, count 2 2006.286.03:04:53.45#ibcon#about to read 4, iclass 10, count 2 2006.286.03:04:53.45#ibcon#read 4, iclass 10, count 2 2006.286.03:04:53.45#ibcon#about to read 5, iclass 10, count 2 2006.286.03:04:53.45#ibcon#read 5, iclass 10, count 2 2006.286.03:04:53.45#ibcon#about to read 6, iclass 10, count 2 2006.286.03:04:53.45#ibcon#read 6, iclass 10, count 2 2006.286.03:04:53.45#ibcon#end of sib2, iclass 10, count 2 2006.286.03:04:53.45#ibcon#*after write, iclass 10, count 2 2006.286.03:04:53.45#ibcon#*before return 0, iclass 10, count 2 2006.286.03:04:53.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:04:53.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:04:53.45#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.03:04:53.45#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:53.45#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:04:53.57#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:04:53.57#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:04:53.57#ibcon#enter wrdev, iclass 10, count 0 2006.286.03:04:53.57#ibcon#first serial, iclass 10, count 0 2006.286.03:04:53.57#ibcon#enter sib2, iclass 10, count 0 2006.286.03:04:53.57#ibcon#flushed, iclass 10, count 0 2006.286.03:04:53.57#ibcon#about to write, iclass 10, count 0 2006.286.03:04:53.57#ibcon#wrote, iclass 10, count 0 2006.286.03:04:53.57#ibcon#about to read 3, iclass 10, count 0 2006.286.03:04:53.59#ibcon#read 3, iclass 10, count 0 2006.286.03:04:53.59#ibcon#about to read 4, iclass 10, count 0 2006.286.03:04:53.59#ibcon#read 4, iclass 10, count 0 2006.286.03:04:53.59#ibcon#about to read 5, iclass 10, count 0 2006.286.03:04:53.59#ibcon#read 5, iclass 10, count 0 2006.286.03:04:53.59#ibcon#about to read 6, iclass 10, count 0 2006.286.03:04:53.59#ibcon#read 6, iclass 10, count 0 2006.286.03:04:53.59#ibcon#end of sib2, iclass 10, count 0 2006.286.03:04:53.59#ibcon#*mode == 0, iclass 10, count 0 2006.286.03:04:53.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.03:04:53.59#ibcon#[25=USB\r\n] 2006.286.03:04:53.59#ibcon#*before write, iclass 10, count 0 2006.286.03:04:53.59#ibcon#enter sib2, iclass 10, count 0 2006.286.03:04:53.59#ibcon#flushed, iclass 10, count 0 2006.286.03:04:53.59#ibcon#about to write, iclass 10, count 0 2006.286.03:04:53.59#ibcon#wrote, iclass 10, count 0 2006.286.03:04:53.59#ibcon#about to read 3, iclass 10, count 0 2006.286.03:04:53.62#ibcon#read 3, iclass 10, count 0 2006.286.03:04:53.62#ibcon#about to read 4, iclass 10, count 0 2006.286.03:04:53.62#ibcon#read 4, iclass 10, count 0 2006.286.03:04:53.62#ibcon#about to read 5, iclass 10, count 0 2006.286.03:04:53.62#ibcon#read 5, iclass 10, count 0 2006.286.03:04:53.62#ibcon#about to read 6, iclass 10, count 0 2006.286.03:04:53.62#ibcon#read 6, iclass 10, count 0 2006.286.03:04:53.62#ibcon#end of sib2, iclass 10, count 0 2006.286.03:04:53.62#ibcon#*after write, iclass 10, count 0 2006.286.03:04:53.62#ibcon#*before return 0, iclass 10, count 0 2006.286.03:04:53.62#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:04:53.62#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:04:53.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.03:04:53.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.03:04:53.62$vck44/valo=6,814.99 2006.286.03:04:53.62#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.03:04:53.62#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.03:04:53.62#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:53.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:04:53.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:04:53.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:04:53.62#ibcon#enter wrdev, iclass 12, count 0 2006.286.03:04:53.62#ibcon#first serial, iclass 12, count 0 2006.286.03:04:53.62#ibcon#enter sib2, iclass 12, count 0 2006.286.03:04:53.62#ibcon#flushed, iclass 12, count 0 2006.286.03:04:53.62#ibcon#about to write, iclass 12, count 0 2006.286.03:04:53.62#ibcon#wrote, iclass 12, count 0 2006.286.03:04:53.62#ibcon#about to read 3, iclass 12, count 0 2006.286.03:04:53.64#ibcon#read 3, iclass 12, count 0 2006.286.03:04:53.64#ibcon#about to read 4, iclass 12, count 0 2006.286.03:04:53.64#ibcon#read 4, iclass 12, count 0 2006.286.03:04:53.64#ibcon#about to read 5, iclass 12, count 0 2006.286.03:04:53.64#ibcon#read 5, iclass 12, count 0 2006.286.03:04:53.64#ibcon#about to read 6, iclass 12, count 0 2006.286.03:04:53.64#ibcon#read 6, iclass 12, count 0 2006.286.03:04:53.64#ibcon#end of sib2, iclass 12, count 0 2006.286.03:04:53.64#ibcon#*mode == 0, iclass 12, count 0 2006.286.03:04:53.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.03:04:53.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.03:04:53.64#ibcon#*before write, iclass 12, count 0 2006.286.03:04:53.64#ibcon#enter sib2, iclass 12, count 0 2006.286.03:04:53.64#ibcon#flushed, iclass 12, count 0 2006.286.03:04:53.64#ibcon#about to write, iclass 12, count 0 2006.286.03:04:53.64#ibcon#wrote, iclass 12, count 0 2006.286.03:04:53.64#ibcon#about to read 3, iclass 12, count 0 2006.286.03:04:53.68#ibcon#read 3, iclass 12, count 0 2006.286.03:04:53.68#ibcon#about to read 4, iclass 12, count 0 2006.286.03:04:53.68#ibcon#read 4, iclass 12, count 0 2006.286.03:04:53.68#ibcon#about to read 5, iclass 12, count 0 2006.286.03:04:53.68#ibcon#read 5, iclass 12, count 0 2006.286.03:04:53.68#ibcon#about to read 6, iclass 12, count 0 2006.286.03:04:53.68#ibcon#read 6, iclass 12, count 0 2006.286.03:04:53.68#ibcon#end of sib2, iclass 12, count 0 2006.286.03:04:53.68#ibcon#*after write, iclass 12, count 0 2006.286.03:04:53.68#ibcon#*before return 0, iclass 12, count 0 2006.286.03:04:53.68#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:04:53.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:04:53.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.03:04:53.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.03:04:53.68$vck44/va=6,4 2006.286.03:04:53.68#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.03:04:53.68#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.03:04:53.68#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:53.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:04:53.74#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:04:53.74#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:04:53.74#ibcon#enter wrdev, iclass 14, count 2 2006.286.03:04:53.74#ibcon#first serial, iclass 14, count 2 2006.286.03:04:53.74#ibcon#enter sib2, iclass 14, count 2 2006.286.03:04:53.74#ibcon#flushed, iclass 14, count 2 2006.286.03:04:53.74#ibcon#about to write, iclass 14, count 2 2006.286.03:04:53.74#ibcon#wrote, iclass 14, count 2 2006.286.03:04:53.74#ibcon#about to read 3, iclass 14, count 2 2006.286.03:04:53.76#ibcon#read 3, iclass 14, count 2 2006.286.03:04:53.76#ibcon#about to read 4, iclass 14, count 2 2006.286.03:04:53.76#ibcon#read 4, iclass 14, count 2 2006.286.03:04:53.76#ibcon#about to read 5, iclass 14, count 2 2006.286.03:04:53.76#ibcon#read 5, iclass 14, count 2 2006.286.03:04:53.76#ibcon#about to read 6, iclass 14, count 2 2006.286.03:04:53.76#ibcon#read 6, iclass 14, count 2 2006.286.03:04:53.76#ibcon#end of sib2, iclass 14, count 2 2006.286.03:04:53.76#ibcon#*mode == 0, iclass 14, count 2 2006.286.03:04:53.76#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.03:04:53.76#ibcon#[25=AT06-04\r\n] 2006.286.03:04:53.76#ibcon#*before write, iclass 14, count 2 2006.286.03:04:53.76#ibcon#enter sib2, iclass 14, count 2 2006.286.03:04:53.76#ibcon#flushed, iclass 14, count 2 2006.286.03:04:53.76#ibcon#about to write, iclass 14, count 2 2006.286.03:04:53.76#ibcon#wrote, iclass 14, count 2 2006.286.03:04:53.76#ibcon#about to read 3, iclass 14, count 2 2006.286.03:04:53.79#ibcon#read 3, iclass 14, count 2 2006.286.03:04:53.79#ibcon#about to read 4, iclass 14, count 2 2006.286.03:04:53.79#ibcon#read 4, iclass 14, count 2 2006.286.03:04:53.79#ibcon#about to read 5, iclass 14, count 2 2006.286.03:04:53.79#ibcon#read 5, iclass 14, count 2 2006.286.03:04:53.79#ibcon#about to read 6, iclass 14, count 2 2006.286.03:04:53.79#ibcon#read 6, iclass 14, count 2 2006.286.03:04:53.79#ibcon#end of sib2, iclass 14, count 2 2006.286.03:04:53.79#ibcon#*after write, iclass 14, count 2 2006.286.03:04:53.79#ibcon#*before return 0, iclass 14, count 2 2006.286.03:04:53.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:04:53.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:04:53.79#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.03:04:53.79#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:53.79#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:04:53.91#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:04:53.91#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:04:53.91#ibcon#enter wrdev, iclass 14, count 0 2006.286.03:04:53.91#ibcon#first serial, iclass 14, count 0 2006.286.03:04:53.91#ibcon#enter sib2, iclass 14, count 0 2006.286.03:04:53.91#ibcon#flushed, iclass 14, count 0 2006.286.03:04:53.91#ibcon#about to write, iclass 14, count 0 2006.286.03:04:53.91#ibcon#wrote, iclass 14, count 0 2006.286.03:04:53.91#ibcon#about to read 3, iclass 14, count 0 2006.286.03:04:53.93#ibcon#read 3, iclass 14, count 0 2006.286.03:04:53.93#ibcon#about to read 4, iclass 14, count 0 2006.286.03:04:53.93#ibcon#read 4, iclass 14, count 0 2006.286.03:04:53.93#ibcon#about to read 5, iclass 14, count 0 2006.286.03:04:53.93#ibcon#read 5, iclass 14, count 0 2006.286.03:04:53.93#ibcon#about to read 6, iclass 14, count 0 2006.286.03:04:53.93#ibcon#read 6, iclass 14, count 0 2006.286.03:04:53.93#ibcon#end of sib2, iclass 14, count 0 2006.286.03:04:53.93#ibcon#*mode == 0, iclass 14, count 0 2006.286.03:04:53.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.03:04:53.93#ibcon#[25=USB\r\n] 2006.286.03:04:53.93#ibcon#*before write, iclass 14, count 0 2006.286.03:04:53.93#ibcon#enter sib2, iclass 14, count 0 2006.286.03:04:53.93#ibcon#flushed, iclass 14, count 0 2006.286.03:04:53.93#ibcon#about to write, iclass 14, count 0 2006.286.03:04:53.93#ibcon#wrote, iclass 14, count 0 2006.286.03:04:53.93#ibcon#about to read 3, iclass 14, count 0 2006.286.03:04:53.96#ibcon#read 3, iclass 14, count 0 2006.286.03:04:53.96#ibcon#about to read 4, iclass 14, count 0 2006.286.03:04:53.96#ibcon#read 4, iclass 14, count 0 2006.286.03:04:53.96#ibcon#about to read 5, iclass 14, count 0 2006.286.03:04:53.96#ibcon#read 5, iclass 14, count 0 2006.286.03:04:53.96#ibcon#about to read 6, iclass 14, count 0 2006.286.03:04:53.96#ibcon#read 6, iclass 14, count 0 2006.286.03:04:53.96#ibcon#end of sib2, iclass 14, count 0 2006.286.03:04:53.96#ibcon#*after write, iclass 14, count 0 2006.286.03:04:53.96#ibcon#*before return 0, iclass 14, count 0 2006.286.03:04:53.96#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:04:53.96#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:04:53.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.03:04:53.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.03:04:53.96$vck44/valo=7,864.99 2006.286.03:04:53.96#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.03:04:53.96#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.03:04:53.96#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:53.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:04:53.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:04:53.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:04:53.96#ibcon#enter wrdev, iclass 16, count 0 2006.286.03:04:53.96#ibcon#first serial, iclass 16, count 0 2006.286.03:04:53.96#ibcon#enter sib2, iclass 16, count 0 2006.286.03:04:53.96#ibcon#flushed, iclass 16, count 0 2006.286.03:04:53.96#ibcon#about to write, iclass 16, count 0 2006.286.03:04:53.96#ibcon#wrote, iclass 16, count 0 2006.286.03:04:53.96#ibcon#about to read 3, iclass 16, count 0 2006.286.03:04:53.98#ibcon#read 3, iclass 16, count 0 2006.286.03:04:54.06#ibcon#about to read 4, iclass 16, count 0 2006.286.03:04:54.06#ibcon#read 4, iclass 16, count 0 2006.286.03:04:54.06#ibcon#about to read 5, iclass 16, count 0 2006.286.03:04:54.06#ibcon#read 5, iclass 16, count 0 2006.286.03:04:54.06#ibcon#about to read 6, iclass 16, count 0 2006.286.03:04:54.06#ibcon#read 6, iclass 16, count 0 2006.286.03:04:54.06#ibcon#end of sib2, iclass 16, count 0 2006.286.03:04:54.06#ibcon#*mode == 0, iclass 16, count 0 2006.286.03:04:54.06#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.03:04:54.06#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.03:04:54.06#ibcon#*before write, iclass 16, count 0 2006.286.03:04:54.06#ibcon#enter sib2, iclass 16, count 0 2006.286.03:04:54.06#ibcon#flushed, iclass 16, count 0 2006.286.03:04:54.06#ibcon#about to write, iclass 16, count 0 2006.286.03:04:54.06#ibcon#wrote, iclass 16, count 0 2006.286.03:04:54.06#ibcon#about to read 3, iclass 16, count 0 2006.286.03:04:54.11#ibcon#read 3, iclass 16, count 0 2006.286.03:04:54.11#ibcon#about to read 4, iclass 16, count 0 2006.286.03:04:54.11#ibcon#read 4, iclass 16, count 0 2006.286.03:04:54.11#ibcon#about to read 5, iclass 16, count 0 2006.286.03:04:54.11#ibcon#read 5, iclass 16, count 0 2006.286.03:04:54.11#ibcon#about to read 6, iclass 16, count 0 2006.286.03:04:54.11#ibcon#read 6, iclass 16, count 0 2006.286.03:04:54.11#ibcon#end of sib2, iclass 16, count 0 2006.286.03:04:54.11#ibcon#*after write, iclass 16, count 0 2006.286.03:04:54.11#ibcon#*before return 0, iclass 16, count 0 2006.286.03:04:54.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:04:54.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:04:54.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.03:04:54.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.03:04:54.11$vck44/va=7,4 2006.286.03:04:54.11#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.03:04:54.11#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.03:04:54.11#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:54.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:04:54.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:04:54.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:04:54.11#ibcon#enter wrdev, iclass 18, count 2 2006.286.03:04:54.11#ibcon#first serial, iclass 18, count 2 2006.286.03:04:54.11#ibcon#enter sib2, iclass 18, count 2 2006.286.03:04:54.11#ibcon#flushed, iclass 18, count 2 2006.286.03:04:54.11#ibcon#about to write, iclass 18, count 2 2006.286.03:04:54.11#ibcon#wrote, iclass 18, count 2 2006.286.03:04:54.11#ibcon#about to read 3, iclass 18, count 2 2006.286.03:04:54.13#ibcon#read 3, iclass 18, count 2 2006.286.03:04:54.13#ibcon#about to read 4, iclass 18, count 2 2006.286.03:04:54.13#ibcon#read 4, iclass 18, count 2 2006.286.03:04:54.13#ibcon#about to read 5, iclass 18, count 2 2006.286.03:04:54.13#ibcon#read 5, iclass 18, count 2 2006.286.03:04:54.13#ibcon#about to read 6, iclass 18, count 2 2006.286.03:04:54.13#ibcon#read 6, iclass 18, count 2 2006.286.03:04:54.13#ibcon#end of sib2, iclass 18, count 2 2006.286.03:04:54.13#ibcon#*mode == 0, iclass 18, count 2 2006.286.03:04:54.13#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.03:04:54.13#ibcon#[25=AT07-04\r\n] 2006.286.03:04:54.13#ibcon#*before write, iclass 18, count 2 2006.286.03:04:54.13#ibcon#enter sib2, iclass 18, count 2 2006.286.03:04:54.13#ibcon#flushed, iclass 18, count 2 2006.286.03:04:54.13#ibcon#about to write, iclass 18, count 2 2006.286.03:04:54.13#ibcon#wrote, iclass 18, count 2 2006.286.03:04:54.13#ibcon#about to read 3, iclass 18, count 2 2006.286.03:04:54.16#ibcon#read 3, iclass 18, count 2 2006.286.03:04:54.16#ibcon#about to read 4, iclass 18, count 2 2006.286.03:04:54.16#ibcon#read 4, iclass 18, count 2 2006.286.03:04:54.16#ibcon#about to read 5, iclass 18, count 2 2006.286.03:04:54.16#ibcon#read 5, iclass 18, count 2 2006.286.03:04:54.16#ibcon#about to read 6, iclass 18, count 2 2006.286.03:04:54.16#ibcon#read 6, iclass 18, count 2 2006.286.03:04:54.16#ibcon#end of sib2, iclass 18, count 2 2006.286.03:04:54.16#ibcon#*after write, iclass 18, count 2 2006.286.03:04:54.16#ibcon#*before return 0, iclass 18, count 2 2006.286.03:04:54.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:04:54.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:04:54.16#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.03:04:54.16#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:54.16#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:04:54.28#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:04:54.28#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:04:54.28#ibcon#enter wrdev, iclass 18, count 0 2006.286.03:04:54.28#ibcon#first serial, iclass 18, count 0 2006.286.03:04:54.28#ibcon#enter sib2, iclass 18, count 0 2006.286.03:04:54.28#ibcon#flushed, iclass 18, count 0 2006.286.03:04:54.28#ibcon#about to write, iclass 18, count 0 2006.286.03:04:54.28#ibcon#wrote, iclass 18, count 0 2006.286.03:04:54.28#ibcon#about to read 3, iclass 18, count 0 2006.286.03:04:54.30#ibcon#read 3, iclass 18, count 0 2006.286.03:04:54.30#ibcon#about to read 4, iclass 18, count 0 2006.286.03:04:54.30#ibcon#read 4, iclass 18, count 0 2006.286.03:04:54.30#ibcon#about to read 5, iclass 18, count 0 2006.286.03:04:54.30#ibcon#read 5, iclass 18, count 0 2006.286.03:04:54.30#ibcon#about to read 6, iclass 18, count 0 2006.286.03:04:54.30#ibcon#read 6, iclass 18, count 0 2006.286.03:04:54.30#ibcon#end of sib2, iclass 18, count 0 2006.286.03:04:54.30#ibcon#*mode == 0, iclass 18, count 0 2006.286.03:04:54.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.03:04:54.30#ibcon#[25=USB\r\n] 2006.286.03:04:54.30#ibcon#*before write, iclass 18, count 0 2006.286.03:04:54.30#ibcon#enter sib2, iclass 18, count 0 2006.286.03:04:54.30#ibcon#flushed, iclass 18, count 0 2006.286.03:04:54.30#ibcon#about to write, iclass 18, count 0 2006.286.03:04:54.30#ibcon#wrote, iclass 18, count 0 2006.286.03:04:54.30#ibcon#about to read 3, iclass 18, count 0 2006.286.03:04:54.33#ibcon#read 3, iclass 18, count 0 2006.286.03:04:54.33#ibcon#about to read 4, iclass 18, count 0 2006.286.03:04:54.33#ibcon#read 4, iclass 18, count 0 2006.286.03:04:54.33#ibcon#about to read 5, iclass 18, count 0 2006.286.03:04:54.33#ibcon#read 5, iclass 18, count 0 2006.286.03:04:54.33#ibcon#about to read 6, iclass 18, count 0 2006.286.03:04:54.33#ibcon#read 6, iclass 18, count 0 2006.286.03:04:54.33#ibcon#end of sib2, iclass 18, count 0 2006.286.03:04:54.33#ibcon#*after write, iclass 18, count 0 2006.286.03:04:54.33#ibcon#*before return 0, iclass 18, count 0 2006.286.03:04:54.33#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:04:54.33#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:04:54.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.03:04:54.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.03:04:54.33$vck44/valo=8,884.99 2006.286.03:04:54.33#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.03:04:54.33#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.03:04:54.33#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:54.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:04:54.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:04:54.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:04:54.33#ibcon#enter wrdev, iclass 20, count 0 2006.286.03:04:54.33#ibcon#first serial, iclass 20, count 0 2006.286.03:04:54.33#ibcon#enter sib2, iclass 20, count 0 2006.286.03:04:54.33#ibcon#flushed, iclass 20, count 0 2006.286.03:04:54.33#ibcon#about to write, iclass 20, count 0 2006.286.03:04:54.33#ibcon#wrote, iclass 20, count 0 2006.286.03:04:54.33#ibcon#about to read 3, iclass 20, count 0 2006.286.03:04:54.35#ibcon#read 3, iclass 20, count 0 2006.286.03:04:54.35#ibcon#about to read 4, iclass 20, count 0 2006.286.03:04:54.35#ibcon#read 4, iclass 20, count 0 2006.286.03:04:54.35#ibcon#about to read 5, iclass 20, count 0 2006.286.03:04:54.35#ibcon#read 5, iclass 20, count 0 2006.286.03:04:54.35#ibcon#about to read 6, iclass 20, count 0 2006.286.03:04:54.35#ibcon#read 6, iclass 20, count 0 2006.286.03:04:54.35#ibcon#end of sib2, iclass 20, count 0 2006.286.03:04:54.35#ibcon#*mode == 0, iclass 20, count 0 2006.286.03:04:54.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.03:04:54.35#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.03:04:54.35#ibcon#*before write, iclass 20, count 0 2006.286.03:04:54.35#ibcon#enter sib2, iclass 20, count 0 2006.286.03:04:54.35#ibcon#flushed, iclass 20, count 0 2006.286.03:04:54.35#ibcon#about to write, iclass 20, count 0 2006.286.03:04:54.35#ibcon#wrote, iclass 20, count 0 2006.286.03:04:54.35#ibcon#about to read 3, iclass 20, count 0 2006.286.03:04:54.39#ibcon#read 3, iclass 20, count 0 2006.286.03:04:54.39#ibcon#about to read 4, iclass 20, count 0 2006.286.03:04:54.39#ibcon#read 4, iclass 20, count 0 2006.286.03:04:54.39#ibcon#about to read 5, iclass 20, count 0 2006.286.03:04:54.39#ibcon#read 5, iclass 20, count 0 2006.286.03:04:54.39#ibcon#about to read 6, iclass 20, count 0 2006.286.03:04:54.39#ibcon#read 6, iclass 20, count 0 2006.286.03:04:54.39#ibcon#end of sib2, iclass 20, count 0 2006.286.03:04:54.39#ibcon#*after write, iclass 20, count 0 2006.286.03:04:54.39#ibcon#*before return 0, iclass 20, count 0 2006.286.03:04:54.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:04:54.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:04:54.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.03:04:54.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.03:04:54.39$vck44/va=8,3 2006.286.03:04:54.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.03:04:54.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.03:04:54.39#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:54.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:04:54.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:04:54.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:04:54.45#ibcon#enter wrdev, iclass 22, count 2 2006.286.03:04:54.45#ibcon#first serial, iclass 22, count 2 2006.286.03:04:54.45#ibcon#enter sib2, iclass 22, count 2 2006.286.03:04:54.45#ibcon#flushed, iclass 22, count 2 2006.286.03:04:54.45#ibcon#about to write, iclass 22, count 2 2006.286.03:04:54.45#ibcon#wrote, iclass 22, count 2 2006.286.03:04:54.45#ibcon#about to read 3, iclass 22, count 2 2006.286.03:04:54.47#ibcon#read 3, iclass 22, count 2 2006.286.03:04:54.47#ibcon#about to read 4, iclass 22, count 2 2006.286.03:04:54.47#ibcon#read 4, iclass 22, count 2 2006.286.03:04:54.47#ibcon#about to read 5, iclass 22, count 2 2006.286.03:04:54.47#ibcon#read 5, iclass 22, count 2 2006.286.03:04:54.47#ibcon#about to read 6, iclass 22, count 2 2006.286.03:04:54.47#ibcon#read 6, iclass 22, count 2 2006.286.03:04:54.47#ibcon#end of sib2, iclass 22, count 2 2006.286.03:04:54.47#ibcon#*mode == 0, iclass 22, count 2 2006.286.03:04:54.47#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.03:04:54.47#ibcon#[25=AT08-03\r\n] 2006.286.03:04:54.47#ibcon#*before write, iclass 22, count 2 2006.286.03:04:54.47#ibcon#enter sib2, iclass 22, count 2 2006.286.03:04:54.47#ibcon#flushed, iclass 22, count 2 2006.286.03:04:54.47#ibcon#about to write, iclass 22, count 2 2006.286.03:04:54.47#ibcon#wrote, iclass 22, count 2 2006.286.03:04:54.47#ibcon#about to read 3, iclass 22, count 2 2006.286.03:04:54.50#ibcon#read 3, iclass 22, count 2 2006.286.03:04:54.50#ibcon#about to read 4, iclass 22, count 2 2006.286.03:04:54.50#ibcon#read 4, iclass 22, count 2 2006.286.03:04:54.50#ibcon#about to read 5, iclass 22, count 2 2006.286.03:04:54.50#ibcon#read 5, iclass 22, count 2 2006.286.03:04:54.50#ibcon#about to read 6, iclass 22, count 2 2006.286.03:04:54.50#ibcon#read 6, iclass 22, count 2 2006.286.03:04:54.50#ibcon#end of sib2, iclass 22, count 2 2006.286.03:04:54.50#ibcon#*after write, iclass 22, count 2 2006.286.03:04:54.50#ibcon#*before return 0, iclass 22, count 2 2006.286.03:04:54.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:04:54.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:04:54.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.03:04:54.50#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:54.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:04:54.62#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:04:54.62#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:04:54.62#ibcon#enter wrdev, iclass 22, count 0 2006.286.03:04:54.62#ibcon#first serial, iclass 22, count 0 2006.286.03:04:54.62#ibcon#enter sib2, iclass 22, count 0 2006.286.03:04:54.62#ibcon#flushed, iclass 22, count 0 2006.286.03:04:54.62#ibcon#about to write, iclass 22, count 0 2006.286.03:04:54.62#ibcon#wrote, iclass 22, count 0 2006.286.03:04:54.62#ibcon#about to read 3, iclass 22, count 0 2006.286.03:04:54.64#ibcon#read 3, iclass 22, count 0 2006.286.03:04:54.64#ibcon#about to read 4, iclass 22, count 0 2006.286.03:04:54.64#ibcon#read 4, iclass 22, count 0 2006.286.03:04:54.64#ibcon#about to read 5, iclass 22, count 0 2006.286.03:04:54.64#ibcon#read 5, iclass 22, count 0 2006.286.03:04:54.64#ibcon#about to read 6, iclass 22, count 0 2006.286.03:04:54.64#ibcon#read 6, iclass 22, count 0 2006.286.03:04:54.64#ibcon#end of sib2, iclass 22, count 0 2006.286.03:04:54.64#ibcon#*mode == 0, iclass 22, count 0 2006.286.03:04:54.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.03:04:54.64#ibcon#[25=USB\r\n] 2006.286.03:04:54.64#ibcon#*before write, iclass 22, count 0 2006.286.03:04:54.64#ibcon#enter sib2, iclass 22, count 0 2006.286.03:04:54.64#ibcon#flushed, iclass 22, count 0 2006.286.03:04:54.64#ibcon#about to write, iclass 22, count 0 2006.286.03:04:54.64#ibcon#wrote, iclass 22, count 0 2006.286.03:04:54.64#ibcon#about to read 3, iclass 22, count 0 2006.286.03:04:54.67#ibcon#read 3, iclass 22, count 0 2006.286.03:04:54.67#ibcon#about to read 4, iclass 22, count 0 2006.286.03:04:54.67#ibcon#read 4, iclass 22, count 0 2006.286.03:04:54.67#ibcon#about to read 5, iclass 22, count 0 2006.286.03:04:54.67#ibcon#read 5, iclass 22, count 0 2006.286.03:04:54.67#ibcon#about to read 6, iclass 22, count 0 2006.286.03:04:54.67#ibcon#read 6, iclass 22, count 0 2006.286.03:04:54.67#ibcon#end of sib2, iclass 22, count 0 2006.286.03:04:54.67#ibcon#*after write, iclass 22, count 0 2006.286.03:04:54.67#ibcon#*before return 0, iclass 22, count 0 2006.286.03:04:54.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:04:54.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:04:54.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.03:04:54.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.03:04:54.67$vck44/vblo=1,629.99 2006.286.03:04:54.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.03:04:54.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.03:04:54.67#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:54.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:04:54.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:04:54.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:04:54.67#ibcon#enter wrdev, iclass 24, count 0 2006.286.03:04:54.67#ibcon#first serial, iclass 24, count 0 2006.286.03:04:54.67#ibcon#enter sib2, iclass 24, count 0 2006.286.03:04:54.67#ibcon#flushed, iclass 24, count 0 2006.286.03:04:54.67#ibcon#about to write, iclass 24, count 0 2006.286.03:04:54.67#ibcon#wrote, iclass 24, count 0 2006.286.03:04:54.67#ibcon#about to read 3, iclass 24, count 0 2006.286.03:04:54.69#ibcon#read 3, iclass 24, count 0 2006.286.03:04:54.69#ibcon#about to read 4, iclass 24, count 0 2006.286.03:04:54.69#ibcon#read 4, iclass 24, count 0 2006.286.03:04:54.69#ibcon#about to read 5, iclass 24, count 0 2006.286.03:04:54.69#ibcon#read 5, iclass 24, count 0 2006.286.03:04:54.69#ibcon#about to read 6, iclass 24, count 0 2006.286.03:04:54.69#ibcon#read 6, iclass 24, count 0 2006.286.03:04:54.69#ibcon#end of sib2, iclass 24, count 0 2006.286.03:04:54.69#ibcon#*mode == 0, iclass 24, count 0 2006.286.03:04:54.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.03:04:54.69#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.03:04:54.69#ibcon#*before write, iclass 24, count 0 2006.286.03:04:54.69#ibcon#enter sib2, iclass 24, count 0 2006.286.03:04:54.69#ibcon#flushed, iclass 24, count 0 2006.286.03:04:54.69#ibcon#about to write, iclass 24, count 0 2006.286.03:04:54.69#ibcon#wrote, iclass 24, count 0 2006.286.03:04:54.69#ibcon#about to read 3, iclass 24, count 0 2006.286.03:04:54.73#ibcon#read 3, iclass 24, count 0 2006.286.03:04:54.73#ibcon#about to read 4, iclass 24, count 0 2006.286.03:04:54.73#ibcon#read 4, iclass 24, count 0 2006.286.03:04:54.73#ibcon#about to read 5, iclass 24, count 0 2006.286.03:04:54.73#ibcon#read 5, iclass 24, count 0 2006.286.03:04:54.73#ibcon#about to read 6, iclass 24, count 0 2006.286.03:04:54.73#ibcon#read 6, iclass 24, count 0 2006.286.03:04:54.73#ibcon#end of sib2, iclass 24, count 0 2006.286.03:04:54.73#ibcon#*after write, iclass 24, count 0 2006.286.03:04:54.73#ibcon#*before return 0, iclass 24, count 0 2006.286.03:04:54.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:04:54.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:04:54.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.03:04:54.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.03:04:54.73$vck44/vb=1,4 2006.286.03:04:54.73#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.03:04:54.73#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.03:04:54.73#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:54.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:04:54.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:04:54.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:04:54.73#ibcon#enter wrdev, iclass 26, count 2 2006.286.03:04:54.73#ibcon#first serial, iclass 26, count 2 2006.286.03:04:54.73#ibcon#enter sib2, iclass 26, count 2 2006.286.03:04:54.73#ibcon#flushed, iclass 26, count 2 2006.286.03:04:54.73#ibcon#about to write, iclass 26, count 2 2006.286.03:04:54.73#ibcon#wrote, iclass 26, count 2 2006.286.03:04:54.73#ibcon#about to read 3, iclass 26, count 2 2006.286.03:04:54.75#ibcon#read 3, iclass 26, count 2 2006.286.03:04:54.75#ibcon#about to read 4, iclass 26, count 2 2006.286.03:04:54.75#ibcon#read 4, iclass 26, count 2 2006.286.03:04:54.75#ibcon#about to read 5, iclass 26, count 2 2006.286.03:04:54.75#ibcon#read 5, iclass 26, count 2 2006.286.03:04:54.75#ibcon#about to read 6, iclass 26, count 2 2006.286.03:04:54.75#ibcon#read 6, iclass 26, count 2 2006.286.03:04:54.75#ibcon#end of sib2, iclass 26, count 2 2006.286.03:04:54.75#ibcon#*mode == 0, iclass 26, count 2 2006.286.03:04:54.75#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.03:04:54.75#ibcon#[27=AT01-04\r\n] 2006.286.03:04:54.75#ibcon#*before write, iclass 26, count 2 2006.286.03:04:54.75#ibcon#enter sib2, iclass 26, count 2 2006.286.03:04:54.75#ibcon#flushed, iclass 26, count 2 2006.286.03:04:54.75#ibcon#about to write, iclass 26, count 2 2006.286.03:04:54.75#ibcon#wrote, iclass 26, count 2 2006.286.03:04:54.75#ibcon#about to read 3, iclass 26, count 2 2006.286.03:04:54.78#ibcon#read 3, iclass 26, count 2 2006.286.03:04:54.78#ibcon#about to read 4, iclass 26, count 2 2006.286.03:04:54.78#ibcon#read 4, iclass 26, count 2 2006.286.03:04:54.78#ibcon#about to read 5, iclass 26, count 2 2006.286.03:04:54.78#ibcon#read 5, iclass 26, count 2 2006.286.03:04:54.78#ibcon#about to read 6, iclass 26, count 2 2006.286.03:04:54.78#ibcon#read 6, iclass 26, count 2 2006.286.03:04:54.78#ibcon#end of sib2, iclass 26, count 2 2006.286.03:04:54.78#ibcon#*after write, iclass 26, count 2 2006.286.03:04:54.78#ibcon#*before return 0, iclass 26, count 2 2006.286.03:04:54.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:04:54.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:04:54.78#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.03:04:54.78#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:54.78#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:04:54.90#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:04:54.90#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:04:54.90#ibcon#enter wrdev, iclass 26, count 0 2006.286.03:04:54.90#ibcon#first serial, iclass 26, count 0 2006.286.03:04:54.90#ibcon#enter sib2, iclass 26, count 0 2006.286.03:04:54.90#ibcon#flushed, iclass 26, count 0 2006.286.03:04:54.90#ibcon#about to write, iclass 26, count 0 2006.286.03:04:54.90#ibcon#wrote, iclass 26, count 0 2006.286.03:04:54.90#ibcon#about to read 3, iclass 26, count 0 2006.286.03:04:54.92#ibcon#read 3, iclass 26, count 0 2006.286.03:04:54.92#ibcon#about to read 4, iclass 26, count 0 2006.286.03:04:54.92#ibcon#read 4, iclass 26, count 0 2006.286.03:04:54.92#ibcon#about to read 5, iclass 26, count 0 2006.286.03:04:54.92#ibcon#read 5, iclass 26, count 0 2006.286.03:04:54.92#ibcon#about to read 6, iclass 26, count 0 2006.286.03:04:54.92#ibcon#read 6, iclass 26, count 0 2006.286.03:04:54.92#ibcon#end of sib2, iclass 26, count 0 2006.286.03:04:54.92#ibcon#*mode == 0, iclass 26, count 0 2006.286.03:04:54.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.03:04:54.92#ibcon#[27=USB\r\n] 2006.286.03:04:54.92#ibcon#*before write, iclass 26, count 0 2006.286.03:04:54.92#ibcon#enter sib2, iclass 26, count 0 2006.286.03:04:54.92#ibcon#flushed, iclass 26, count 0 2006.286.03:04:54.92#ibcon#about to write, iclass 26, count 0 2006.286.03:04:54.92#ibcon#wrote, iclass 26, count 0 2006.286.03:04:54.92#ibcon#about to read 3, iclass 26, count 0 2006.286.03:04:54.95#ibcon#read 3, iclass 26, count 0 2006.286.03:04:54.95#ibcon#about to read 4, iclass 26, count 0 2006.286.03:04:54.95#ibcon#read 4, iclass 26, count 0 2006.286.03:04:54.95#ibcon#about to read 5, iclass 26, count 0 2006.286.03:04:54.95#ibcon#read 5, iclass 26, count 0 2006.286.03:04:54.95#ibcon#about to read 6, iclass 26, count 0 2006.286.03:04:54.95#ibcon#read 6, iclass 26, count 0 2006.286.03:04:54.95#ibcon#end of sib2, iclass 26, count 0 2006.286.03:04:54.95#ibcon#*after write, iclass 26, count 0 2006.286.03:04:54.95#ibcon#*before return 0, iclass 26, count 0 2006.286.03:04:54.95#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:04:54.95#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:04:54.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.03:04:54.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.03:04:54.95$vck44/vblo=2,634.99 2006.286.03:04:54.95#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.03:04:54.95#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.03:04:54.95#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:54.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:04:54.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:04:54.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:04:54.95#ibcon#enter wrdev, iclass 28, count 0 2006.286.03:04:54.95#ibcon#first serial, iclass 28, count 0 2006.286.03:04:54.95#ibcon#enter sib2, iclass 28, count 0 2006.286.03:04:54.95#ibcon#flushed, iclass 28, count 0 2006.286.03:04:54.95#ibcon#about to write, iclass 28, count 0 2006.286.03:04:54.95#ibcon#wrote, iclass 28, count 0 2006.286.03:04:54.95#ibcon#about to read 3, iclass 28, count 0 2006.286.03:04:54.97#ibcon#read 3, iclass 28, count 0 2006.286.03:04:54.97#ibcon#about to read 4, iclass 28, count 0 2006.286.03:04:54.97#ibcon#read 4, iclass 28, count 0 2006.286.03:04:54.97#ibcon#about to read 5, iclass 28, count 0 2006.286.03:04:54.97#ibcon#read 5, iclass 28, count 0 2006.286.03:04:54.97#ibcon#about to read 6, iclass 28, count 0 2006.286.03:04:54.97#ibcon#read 6, iclass 28, count 0 2006.286.03:04:54.97#ibcon#end of sib2, iclass 28, count 0 2006.286.03:04:54.97#ibcon#*mode == 0, iclass 28, count 0 2006.286.03:04:54.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.03:04:54.97#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.03:04:54.97#ibcon#*before write, iclass 28, count 0 2006.286.03:04:54.97#ibcon#enter sib2, iclass 28, count 0 2006.286.03:04:54.97#ibcon#flushed, iclass 28, count 0 2006.286.03:04:54.97#ibcon#about to write, iclass 28, count 0 2006.286.03:04:54.97#ibcon#wrote, iclass 28, count 0 2006.286.03:04:54.97#ibcon#about to read 3, iclass 28, count 0 2006.286.03:04:55.01#ibcon#read 3, iclass 28, count 0 2006.286.03:04:55.01#ibcon#about to read 4, iclass 28, count 0 2006.286.03:04:55.01#ibcon#read 4, iclass 28, count 0 2006.286.03:04:55.01#ibcon#about to read 5, iclass 28, count 0 2006.286.03:04:55.01#ibcon#read 5, iclass 28, count 0 2006.286.03:04:55.01#ibcon#about to read 6, iclass 28, count 0 2006.286.03:04:55.01#ibcon#read 6, iclass 28, count 0 2006.286.03:04:55.01#ibcon#end of sib2, iclass 28, count 0 2006.286.03:04:55.01#ibcon#*after write, iclass 28, count 0 2006.286.03:04:55.01#ibcon#*before return 0, iclass 28, count 0 2006.286.03:04:55.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:04:55.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:04:55.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.03:04:55.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.03:04:55.01$vck44/vb=2,5 2006.286.03:04:55.21#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.03:04:55.21#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.03:04:55.21#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:55.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:04:55.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:04:55.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:04:55.21#ibcon#enter wrdev, iclass 30, count 2 2006.286.03:04:55.21#ibcon#first serial, iclass 30, count 2 2006.286.03:04:55.21#ibcon#enter sib2, iclass 30, count 2 2006.286.03:04:55.21#ibcon#flushed, iclass 30, count 2 2006.286.03:04:55.21#ibcon#about to write, iclass 30, count 2 2006.286.03:04:55.21#ibcon#wrote, iclass 30, count 2 2006.286.03:04:55.21#ibcon#about to read 3, iclass 30, count 2 2006.286.03:04:55.23#ibcon#read 3, iclass 30, count 2 2006.286.03:04:55.23#ibcon#about to read 4, iclass 30, count 2 2006.286.03:04:55.23#ibcon#read 4, iclass 30, count 2 2006.286.03:04:55.23#ibcon#about to read 5, iclass 30, count 2 2006.286.03:04:55.23#ibcon#read 5, iclass 30, count 2 2006.286.03:04:55.23#ibcon#about to read 6, iclass 30, count 2 2006.286.03:04:55.23#ibcon#read 6, iclass 30, count 2 2006.286.03:04:55.23#ibcon#end of sib2, iclass 30, count 2 2006.286.03:04:55.23#ibcon#*mode == 0, iclass 30, count 2 2006.286.03:04:55.23#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.03:04:55.23#ibcon#[27=AT02-05\r\n] 2006.286.03:04:55.23#ibcon#*before write, iclass 30, count 2 2006.286.03:04:55.23#ibcon#enter sib2, iclass 30, count 2 2006.286.03:04:55.23#ibcon#flushed, iclass 30, count 2 2006.286.03:04:55.23#ibcon#about to write, iclass 30, count 2 2006.286.03:04:55.23#ibcon#wrote, iclass 30, count 2 2006.286.03:04:55.23#ibcon#about to read 3, iclass 30, count 2 2006.286.03:04:55.26#ibcon#read 3, iclass 30, count 2 2006.286.03:04:55.26#ibcon#about to read 4, iclass 30, count 2 2006.286.03:04:55.26#ibcon#read 4, iclass 30, count 2 2006.286.03:04:55.26#ibcon#about to read 5, iclass 30, count 2 2006.286.03:04:55.26#ibcon#read 5, iclass 30, count 2 2006.286.03:04:55.26#ibcon#about to read 6, iclass 30, count 2 2006.286.03:04:55.26#ibcon#read 6, iclass 30, count 2 2006.286.03:04:55.26#ibcon#end of sib2, iclass 30, count 2 2006.286.03:04:55.26#ibcon#*after write, iclass 30, count 2 2006.286.03:04:55.26#ibcon#*before return 0, iclass 30, count 2 2006.286.03:04:55.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:04:55.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:04:55.26#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.03:04:55.26#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:55.26#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:04:55.38#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:04:55.38#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:04:55.38#ibcon#enter wrdev, iclass 30, count 0 2006.286.03:04:55.38#ibcon#first serial, iclass 30, count 0 2006.286.03:04:55.38#ibcon#enter sib2, iclass 30, count 0 2006.286.03:04:55.38#ibcon#flushed, iclass 30, count 0 2006.286.03:04:55.38#ibcon#about to write, iclass 30, count 0 2006.286.03:04:55.38#ibcon#wrote, iclass 30, count 0 2006.286.03:04:55.38#ibcon#about to read 3, iclass 30, count 0 2006.286.03:04:55.40#ibcon#read 3, iclass 30, count 0 2006.286.03:04:55.40#ibcon#about to read 4, iclass 30, count 0 2006.286.03:04:55.40#ibcon#read 4, iclass 30, count 0 2006.286.03:04:55.40#ibcon#about to read 5, iclass 30, count 0 2006.286.03:04:55.40#ibcon#read 5, iclass 30, count 0 2006.286.03:04:55.40#ibcon#about to read 6, iclass 30, count 0 2006.286.03:04:55.40#ibcon#read 6, iclass 30, count 0 2006.286.03:04:55.40#ibcon#end of sib2, iclass 30, count 0 2006.286.03:04:55.40#ibcon#*mode == 0, iclass 30, count 0 2006.286.03:04:55.40#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.03:04:55.40#ibcon#[27=USB\r\n] 2006.286.03:04:55.40#ibcon#*before write, iclass 30, count 0 2006.286.03:04:55.40#ibcon#enter sib2, iclass 30, count 0 2006.286.03:04:55.40#ibcon#flushed, iclass 30, count 0 2006.286.03:04:55.40#ibcon#about to write, iclass 30, count 0 2006.286.03:04:55.40#ibcon#wrote, iclass 30, count 0 2006.286.03:04:55.40#ibcon#about to read 3, iclass 30, count 0 2006.286.03:04:55.43#ibcon#read 3, iclass 30, count 0 2006.286.03:04:55.43#ibcon#about to read 4, iclass 30, count 0 2006.286.03:04:55.43#ibcon#read 4, iclass 30, count 0 2006.286.03:04:55.43#ibcon#about to read 5, iclass 30, count 0 2006.286.03:04:55.43#ibcon#read 5, iclass 30, count 0 2006.286.03:04:55.43#ibcon#about to read 6, iclass 30, count 0 2006.286.03:04:55.43#ibcon#read 6, iclass 30, count 0 2006.286.03:04:55.43#ibcon#end of sib2, iclass 30, count 0 2006.286.03:04:55.43#ibcon#*after write, iclass 30, count 0 2006.286.03:04:55.43#ibcon#*before return 0, iclass 30, count 0 2006.286.03:04:55.43#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:04:55.43#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:04:55.43#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.03:04:55.43#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.03:04:55.43$vck44/vblo=3,649.99 2006.286.03:04:55.43#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.03:04:55.43#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.03:04:55.43#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:55.43#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:04:55.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:04:55.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:04:55.43#ibcon#enter wrdev, iclass 32, count 0 2006.286.03:04:55.43#ibcon#first serial, iclass 32, count 0 2006.286.03:04:55.43#ibcon#enter sib2, iclass 32, count 0 2006.286.03:04:55.43#ibcon#flushed, iclass 32, count 0 2006.286.03:04:55.43#ibcon#about to write, iclass 32, count 0 2006.286.03:04:55.43#ibcon#wrote, iclass 32, count 0 2006.286.03:04:55.43#ibcon#about to read 3, iclass 32, count 0 2006.286.03:04:55.45#ibcon#read 3, iclass 32, count 0 2006.286.03:04:55.45#ibcon#about to read 4, iclass 32, count 0 2006.286.03:04:55.45#ibcon#read 4, iclass 32, count 0 2006.286.03:04:55.45#ibcon#about to read 5, iclass 32, count 0 2006.286.03:04:55.45#ibcon#read 5, iclass 32, count 0 2006.286.03:04:55.45#ibcon#about to read 6, iclass 32, count 0 2006.286.03:04:55.45#ibcon#read 6, iclass 32, count 0 2006.286.03:04:55.45#ibcon#end of sib2, iclass 32, count 0 2006.286.03:04:55.45#ibcon#*mode == 0, iclass 32, count 0 2006.286.03:04:55.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.03:04:55.45#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.03:04:55.45#ibcon#*before write, iclass 32, count 0 2006.286.03:04:55.45#ibcon#enter sib2, iclass 32, count 0 2006.286.03:04:55.45#ibcon#flushed, iclass 32, count 0 2006.286.03:04:55.45#ibcon#about to write, iclass 32, count 0 2006.286.03:04:55.45#ibcon#wrote, iclass 32, count 0 2006.286.03:04:55.45#ibcon#about to read 3, iclass 32, count 0 2006.286.03:04:55.49#ibcon#read 3, iclass 32, count 0 2006.286.03:04:55.49#ibcon#about to read 4, iclass 32, count 0 2006.286.03:04:55.49#ibcon#read 4, iclass 32, count 0 2006.286.03:04:55.49#ibcon#about to read 5, iclass 32, count 0 2006.286.03:04:55.49#ibcon#read 5, iclass 32, count 0 2006.286.03:04:55.49#ibcon#about to read 6, iclass 32, count 0 2006.286.03:04:55.49#ibcon#read 6, iclass 32, count 0 2006.286.03:04:55.49#ibcon#end of sib2, iclass 32, count 0 2006.286.03:04:55.49#ibcon#*after write, iclass 32, count 0 2006.286.03:04:55.49#ibcon#*before return 0, iclass 32, count 0 2006.286.03:04:55.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:04:55.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:04:55.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.03:04:55.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.03:04:55.49$vck44/vb=3,4 2006.286.03:04:55.49#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.03:04:55.49#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.03:04:55.49#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:55.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:04:55.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:04:55.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:04:55.55#ibcon#enter wrdev, iclass 34, count 2 2006.286.03:04:55.55#ibcon#first serial, iclass 34, count 2 2006.286.03:04:55.55#ibcon#enter sib2, iclass 34, count 2 2006.286.03:04:55.55#ibcon#flushed, iclass 34, count 2 2006.286.03:04:55.55#ibcon#about to write, iclass 34, count 2 2006.286.03:04:55.55#ibcon#wrote, iclass 34, count 2 2006.286.03:04:55.55#ibcon#about to read 3, iclass 34, count 2 2006.286.03:04:55.57#ibcon#read 3, iclass 34, count 2 2006.286.03:04:55.57#ibcon#about to read 4, iclass 34, count 2 2006.286.03:04:55.57#ibcon#read 4, iclass 34, count 2 2006.286.03:04:55.57#ibcon#about to read 5, iclass 34, count 2 2006.286.03:04:55.57#ibcon#read 5, iclass 34, count 2 2006.286.03:04:55.57#ibcon#about to read 6, iclass 34, count 2 2006.286.03:04:55.57#ibcon#read 6, iclass 34, count 2 2006.286.03:04:55.57#ibcon#end of sib2, iclass 34, count 2 2006.286.03:04:55.57#ibcon#*mode == 0, iclass 34, count 2 2006.286.03:04:55.57#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.03:04:55.57#ibcon#[27=AT03-04\r\n] 2006.286.03:04:55.57#ibcon#*before write, iclass 34, count 2 2006.286.03:04:55.57#ibcon#enter sib2, iclass 34, count 2 2006.286.03:04:55.57#ibcon#flushed, iclass 34, count 2 2006.286.03:04:55.57#ibcon#about to write, iclass 34, count 2 2006.286.03:04:55.57#ibcon#wrote, iclass 34, count 2 2006.286.03:04:55.57#ibcon#about to read 3, iclass 34, count 2 2006.286.03:04:55.60#ibcon#read 3, iclass 34, count 2 2006.286.03:04:55.60#ibcon#about to read 4, iclass 34, count 2 2006.286.03:04:55.60#ibcon#read 4, iclass 34, count 2 2006.286.03:04:55.60#ibcon#about to read 5, iclass 34, count 2 2006.286.03:04:55.60#ibcon#read 5, iclass 34, count 2 2006.286.03:04:55.60#ibcon#about to read 6, iclass 34, count 2 2006.286.03:04:55.60#ibcon#read 6, iclass 34, count 2 2006.286.03:04:55.60#ibcon#end of sib2, iclass 34, count 2 2006.286.03:04:55.60#ibcon#*after write, iclass 34, count 2 2006.286.03:04:55.60#ibcon#*before return 0, iclass 34, count 2 2006.286.03:04:55.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:04:55.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:04:55.60#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.03:04:55.60#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:55.60#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:04:55.72#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:04:55.72#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:04:55.72#ibcon#enter wrdev, iclass 34, count 0 2006.286.03:04:55.72#ibcon#first serial, iclass 34, count 0 2006.286.03:04:55.72#ibcon#enter sib2, iclass 34, count 0 2006.286.03:04:55.72#ibcon#flushed, iclass 34, count 0 2006.286.03:04:55.72#ibcon#about to write, iclass 34, count 0 2006.286.03:04:55.72#ibcon#wrote, iclass 34, count 0 2006.286.03:04:55.72#ibcon#about to read 3, iclass 34, count 0 2006.286.03:04:55.74#ibcon#read 3, iclass 34, count 0 2006.286.03:04:55.74#ibcon#about to read 4, iclass 34, count 0 2006.286.03:04:55.74#ibcon#read 4, iclass 34, count 0 2006.286.03:04:55.74#ibcon#about to read 5, iclass 34, count 0 2006.286.03:04:55.74#ibcon#read 5, iclass 34, count 0 2006.286.03:04:55.74#ibcon#about to read 6, iclass 34, count 0 2006.286.03:04:55.74#ibcon#read 6, iclass 34, count 0 2006.286.03:04:55.74#ibcon#end of sib2, iclass 34, count 0 2006.286.03:04:55.74#ibcon#*mode == 0, iclass 34, count 0 2006.286.03:04:55.74#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.03:04:55.74#ibcon#[27=USB\r\n] 2006.286.03:04:55.74#ibcon#*before write, iclass 34, count 0 2006.286.03:04:55.74#ibcon#enter sib2, iclass 34, count 0 2006.286.03:04:55.74#ibcon#flushed, iclass 34, count 0 2006.286.03:04:55.74#ibcon#about to write, iclass 34, count 0 2006.286.03:04:55.74#ibcon#wrote, iclass 34, count 0 2006.286.03:04:55.74#ibcon#about to read 3, iclass 34, count 0 2006.286.03:04:55.77#ibcon#read 3, iclass 34, count 0 2006.286.03:04:55.77#ibcon#about to read 4, iclass 34, count 0 2006.286.03:04:55.77#ibcon#read 4, iclass 34, count 0 2006.286.03:04:55.77#ibcon#about to read 5, iclass 34, count 0 2006.286.03:04:55.77#ibcon#read 5, iclass 34, count 0 2006.286.03:04:55.77#ibcon#about to read 6, iclass 34, count 0 2006.286.03:04:55.77#ibcon#read 6, iclass 34, count 0 2006.286.03:04:55.77#ibcon#end of sib2, iclass 34, count 0 2006.286.03:04:55.77#ibcon#*after write, iclass 34, count 0 2006.286.03:04:55.77#ibcon#*before return 0, iclass 34, count 0 2006.286.03:04:55.77#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:04:55.77#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:04:55.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.03:04:55.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.03:04:55.77$vck44/vblo=4,679.99 2006.286.03:04:55.77#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.03:04:55.77#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.03:04:55.77#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:55.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:04:55.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:04:55.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:04:55.77#ibcon#enter wrdev, iclass 36, count 0 2006.286.03:04:55.77#ibcon#first serial, iclass 36, count 0 2006.286.03:04:55.77#ibcon#enter sib2, iclass 36, count 0 2006.286.03:04:55.77#ibcon#flushed, iclass 36, count 0 2006.286.03:04:55.77#ibcon#about to write, iclass 36, count 0 2006.286.03:04:55.77#ibcon#wrote, iclass 36, count 0 2006.286.03:04:55.77#ibcon#about to read 3, iclass 36, count 0 2006.286.03:04:55.79#ibcon#read 3, iclass 36, count 0 2006.286.03:04:55.79#ibcon#about to read 4, iclass 36, count 0 2006.286.03:04:55.79#ibcon#read 4, iclass 36, count 0 2006.286.03:04:55.79#ibcon#about to read 5, iclass 36, count 0 2006.286.03:04:55.79#ibcon#read 5, iclass 36, count 0 2006.286.03:04:55.79#ibcon#about to read 6, iclass 36, count 0 2006.286.03:04:55.79#ibcon#read 6, iclass 36, count 0 2006.286.03:04:55.79#ibcon#end of sib2, iclass 36, count 0 2006.286.03:04:55.79#ibcon#*mode == 0, iclass 36, count 0 2006.286.03:04:55.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.03:04:55.79#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.03:04:55.79#ibcon#*before write, iclass 36, count 0 2006.286.03:04:55.79#ibcon#enter sib2, iclass 36, count 0 2006.286.03:04:55.79#ibcon#flushed, iclass 36, count 0 2006.286.03:04:55.79#ibcon#about to write, iclass 36, count 0 2006.286.03:04:55.79#ibcon#wrote, iclass 36, count 0 2006.286.03:04:55.79#ibcon#about to read 3, iclass 36, count 0 2006.286.03:04:55.83#ibcon#read 3, iclass 36, count 0 2006.286.03:04:55.83#ibcon#about to read 4, iclass 36, count 0 2006.286.03:04:55.83#ibcon#read 4, iclass 36, count 0 2006.286.03:04:55.83#ibcon#about to read 5, iclass 36, count 0 2006.286.03:04:55.83#ibcon#read 5, iclass 36, count 0 2006.286.03:04:55.83#ibcon#about to read 6, iclass 36, count 0 2006.286.03:04:55.83#ibcon#read 6, iclass 36, count 0 2006.286.03:04:55.83#ibcon#end of sib2, iclass 36, count 0 2006.286.03:04:55.83#ibcon#*after write, iclass 36, count 0 2006.286.03:04:55.83#ibcon#*before return 0, iclass 36, count 0 2006.286.03:04:55.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:04:55.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:04:55.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.03:04:55.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.03:04:55.83$vck44/vb=4,5 2006.286.03:04:55.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.03:04:55.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.03:04:55.83#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:55.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:04:55.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:04:55.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:04:55.89#ibcon#enter wrdev, iclass 38, count 2 2006.286.03:04:55.89#ibcon#first serial, iclass 38, count 2 2006.286.03:04:55.89#ibcon#enter sib2, iclass 38, count 2 2006.286.03:04:55.89#ibcon#flushed, iclass 38, count 2 2006.286.03:04:55.89#ibcon#about to write, iclass 38, count 2 2006.286.03:04:55.89#ibcon#wrote, iclass 38, count 2 2006.286.03:04:55.89#ibcon#about to read 3, iclass 38, count 2 2006.286.03:04:55.91#ibcon#read 3, iclass 38, count 2 2006.286.03:04:55.91#ibcon#about to read 4, iclass 38, count 2 2006.286.03:04:55.91#ibcon#read 4, iclass 38, count 2 2006.286.03:04:55.91#ibcon#about to read 5, iclass 38, count 2 2006.286.03:04:55.91#ibcon#read 5, iclass 38, count 2 2006.286.03:04:55.91#ibcon#about to read 6, iclass 38, count 2 2006.286.03:04:55.91#ibcon#read 6, iclass 38, count 2 2006.286.03:04:55.91#ibcon#end of sib2, iclass 38, count 2 2006.286.03:04:55.91#ibcon#*mode == 0, iclass 38, count 2 2006.286.03:04:55.91#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.03:04:55.91#ibcon#[27=AT04-05\r\n] 2006.286.03:04:55.91#ibcon#*before write, iclass 38, count 2 2006.286.03:04:55.91#ibcon#enter sib2, iclass 38, count 2 2006.286.03:04:55.91#ibcon#flushed, iclass 38, count 2 2006.286.03:04:55.91#ibcon#about to write, iclass 38, count 2 2006.286.03:04:55.91#ibcon#wrote, iclass 38, count 2 2006.286.03:04:55.91#ibcon#about to read 3, iclass 38, count 2 2006.286.03:04:55.94#ibcon#read 3, iclass 38, count 2 2006.286.03:04:55.94#ibcon#about to read 4, iclass 38, count 2 2006.286.03:04:55.94#ibcon#read 4, iclass 38, count 2 2006.286.03:04:55.94#ibcon#about to read 5, iclass 38, count 2 2006.286.03:04:55.94#ibcon#read 5, iclass 38, count 2 2006.286.03:04:55.94#ibcon#about to read 6, iclass 38, count 2 2006.286.03:04:55.94#ibcon#read 6, iclass 38, count 2 2006.286.03:04:55.94#ibcon#end of sib2, iclass 38, count 2 2006.286.03:04:55.94#ibcon#*after write, iclass 38, count 2 2006.286.03:04:55.94#ibcon#*before return 0, iclass 38, count 2 2006.286.03:04:55.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:04:55.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:04:55.94#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.03:04:55.94#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:55.94#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:04:56.06#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:04:56.06#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:04:56.06#ibcon#enter wrdev, iclass 38, count 0 2006.286.03:04:56.06#ibcon#first serial, iclass 38, count 0 2006.286.03:04:56.06#ibcon#enter sib2, iclass 38, count 0 2006.286.03:04:56.06#ibcon#flushed, iclass 38, count 0 2006.286.03:04:56.06#ibcon#about to write, iclass 38, count 0 2006.286.03:04:56.06#ibcon#wrote, iclass 38, count 0 2006.286.03:04:56.06#ibcon#about to read 3, iclass 38, count 0 2006.286.03:04:56.08#ibcon#read 3, iclass 38, count 0 2006.286.03:04:56.08#ibcon#about to read 4, iclass 38, count 0 2006.286.03:04:56.08#ibcon#read 4, iclass 38, count 0 2006.286.03:04:56.08#ibcon#about to read 5, iclass 38, count 0 2006.286.03:04:56.08#ibcon#read 5, iclass 38, count 0 2006.286.03:04:56.08#ibcon#about to read 6, iclass 38, count 0 2006.286.03:04:56.08#ibcon#read 6, iclass 38, count 0 2006.286.03:04:56.08#ibcon#end of sib2, iclass 38, count 0 2006.286.03:04:56.08#ibcon#*mode == 0, iclass 38, count 0 2006.286.03:04:56.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.03:04:56.08#ibcon#[27=USB\r\n] 2006.286.03:04:56.08#ibcon#*before write, iclass 38, count 0 2006.286.03:04:56.08#ibcon#enter sib2, iclass 38, count 0 2006.286.03:04:56.08#ibcon#flushed, iclass 38, count 0 2006.286.03:04:56.08#ibcon#about to write, iclass 38, count 0 2006.286.03:04:56.08#ibcon#wrote, iclass 38, count 0 2006.286.03:04:56.08#ibcon#about to read 3, iclass 38, count 0 2006.286.03:04:56.11#ibcon#read 3, iclass 38, count 0 2006.286.03:04:56.11#ibcon#about to read 4, iclass 38, count 0 2006.286.03:04:56.11#ibcon#read 4, iclass 38, count 0 2006.286.03:04:56.11#ibcon#about to read 5, iclass 38, count 0 2006.286.03:04:56.11#ibcon#read 5, iclass 38, count 0 2006.286.03:04:56.11#ibcon#about to read 6, iclass 38, count 0 2006.286.03:04:56.11#ibcon#read 6, iclass 38, count 0 2006.286.03:04:56.11#ibcon#end of sib2, iclass 38, count 0 2006.286.03:04:56.11#ibcon#*after write, iclass 38, count 0 2006.286.03:04:56.11#ibcon#*before return 0, iclass 38, count 0 2006.286.03:04:56.11#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:04:56.11#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:04:56.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.03:04:56.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.03:04:56.11$vck44/vblo=5,709.99 2006.286.03:04:56.11#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.03:04:56.11#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.03:04:56.11#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:56.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:04:56.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:04:56.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:04:56.11#ibcon#enter wrdev, iclass 40, count 0 2006.286.03:04:56.11#ibcon#first serial, iclass 40, count 0 2006.286.03:04:56.11#ibcon#enter sib2, iclass 40, count 0 2006.286.03:04:56.11#ibcon#flushed, iclass 40, count 0 2006.286.03:04:56.11#ibcon#about to write, iclass 40, count 0 2006.286.03:04:56.11#ibcon#wrote, iclass 40, count 0 2006.286.03:04:56.11#ibcon#about to read 3, iclass 40, count 0 2006.286.03:04:56.13#ibcon#read 3, iclass 40, count 0 2006.286.03:04:56.13#ibcon#about to read 4, iclass 40, count 0 2006.286.03:04:56.13#ibcon#read 4, iclass 40, count 0 2006.286.03:04:56.13#ibcon#about to read 5, iclass 40, count 0 2006.286.03:04:56.13#ibcon#read 5, iclass 40, count 0 2006.286.03:04:56.13#ibcon#about to read 6, iclass 40, count 0 2006.286.03:04:56.13#ibcon#read 6, iclass 40, count 0 2006.286.03:04:56.13#ibcon#end of sib2, iclass 40, count 0 2006.286.03:04:56.13#ibcon#*mode == 0, iclass 40, count 0 2006.286.03:04:56.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.03:04:56.13#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.03:04:56.13#ibcon#*before write, iclass 40, count 0 2006.286.03:04:56.13#ibcon#enter sib2, iclass 40, count 0 2006.286.03:04:56.13#ibcon#flushed, iclass 40, count 0 2006.286.03:04:56.13#ibcon#about to write, iclass 40, count 0 2006.286.03:04:56.13#ibcon#wrote, iclass 40, count 0 2006.286.03:04:56.13#ibcon#about to read 3, iclass 40, count 0 2006.286.03:04:56.18#ibcon#read 3, iclass 40, count 0 2006.286.03:04:56.18#ibcon#about to read 4, iclass 40, count 0 2006.286.03:04:56.18#ibcon#read 4, iclass 40, count 0 2006.286.03:04:56.18#ibcon#about to read 5, iclass 40, count 0 2006.286.03:04:56.18#ibcon#read 5, iclass 40, count 0 2006.286.03:04:56.18#ibcon#about to read 6, iclass 40, count 0 2006.286.03:04:56.18#ibcon#read 6, iclass 40, count 0 2006.286.03:04:56.18#ibcon#end of sib2, iclass 40, count 0 2006.286.03:04:56.18#ibcon#*after write, iclass 40, count 0 2006.286.03:04:56.18#ibcon#*before return 0, iclass 40, count 0 2006.286.03:04:56.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:04:56.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:04:56.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.03:04:56.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.03:04:56.18$vck44/vb=5,4 2006.286.03:04:56.18#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.03:04:56.18#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.03:04:56.18#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:56.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:04:56.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:04:56.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:04:56.23#ibcon#enter wrdev, iclass 4, count 2 2006.286.03:04:56.23#ibcon#first serial, iclass 4, count 2 2006.286.03:04:56.23#ibcon#enter sib2, iclass 4, count 2 2006.286.03:04:56.23#ibcon#flushed, iclass 4, count 2 2006.286.03:04:56.23#ibcon#about to write, iclass 4, count 2 2006.286.03:04:56.23#ibcon#wrote, iclass 4, count 2 2006.286.03:04:56.23#ibcon#about to read 3, iclass 4, count 2 2006.286.03:04:56.25#ibcon#read 3, iclass 4, count 2 2006.286.03:04:56.25#ibcon#about to read 4, iclass 4, count 2 2006.286.03:04:56.25#ibcon#read 4, iclass 4, count 2 2006.286.03:04:56.25#ibcon#about to read 5, iclass 4, count 2 2006.286.03:04:56.25#ibcon#read 5, iclass 4, count 2 2006.286.03:04:56.25#ibcon#about to read 6, iclass 4, count 2 2006.286.03:04:56.25#ibcon#read 6, iclass 4, count 2 2006.286.03:04:56.25#ibcon#end of sib2, iclass 4, count 2 2006.286.03:04:56.25#ibcon#*mode == 0, iclass 4, count 2 2006.286.03:04:56.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.03:04:56.25#ibcon#[27=AT05-04\r\n] 2006.286.03:04:56.25#ibcon#*before write, iclass 4, count 2 2006.286.03:04:56.25#ibcon#enter sib2, iclass 4, count 2 2006.286.03:04:56.25#ibcon#flushed, iclass 4, count 2 2006.286.03:04:56.25#ibcon#about to write, iclass 4, count 2 2006.286.03:04:56.25#ibcon#wrote, iclass 4, count 2 2006.286.03:04:56.25#ibcon#about to read 3, iclass 4, count 2 2006.286.03:04:56.28#ibcon#read 3, iclass 4, count 2 2006.286.03:04:56.28#ibcon#about to read 4, iclass 4, count 2 2006.286.03:04:56.28#ibcon#read 4, iclass 4, count 2 2006.286.03:04:56.28#ibcon#about to read 5, iclass 4, count 2 2006.286.03:04:56.28#ibcon#read 5, iclass 4, count 2 2006.286.03:04:56.28#ibcon#about to read 6, iclass 4, count 2 2006.286.03:04:56.28#ibcon#read 6, iclass 4, count 2 2006.286.03:04:56.28#ibcon#end of sib2, iclass 4, count 2 2006.286.03:04:56.28#ibcon#*after write, iclass 4, count 2 2006.286.03:04:56.28#ibcon#*before return 0, iclass 4, count 2 2006.286.03:04:56.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:04:56.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:04:56.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.03:04:56.28#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:56.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:04:56.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:04:56.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:04:56.40#ibcon#enter wrdev, iclass 4, count 0 2006.286.03:04:56.40#ibcon#first serial, iclass 4, count 0 2006.286.03:04:56.40#ibcon#enter sib2, iclass 4, count 0 2006.286.03:04:56.40#ibcon#flushed, iclass 4, count 0 2006.286.03:04:56.40#ibcon#about to write, iclass 4, count 0 2006.286.03:04:56.40#ibcon#wrote, iclass 4, count 0 2006.286.03:04:56.40#ibcon#about to read 3, iclass 4, count 0 2006.286.03:04:56.42#ibcon#read 3, iclass 4, count 0 2006.286.03:04:56.42#ibcon#about to read 4, iclass 4, count 0 2006.286.03:04:56.42#ibcon#read 4, iclass 4, count 0 2006.286.03:04:56.42#ibcon#about to read 5, iclass 4, count 0 2006.286.03:04:56.42#ibcon#read 5, iclass 4, count 0 2006.286.03:04:56.42#ibcon#about to read 6, iclass 4, count 0 2006.286.03:04:56.42#ibcon#read 6, iclass 4, count 0 2006.286.03:04:56.42#ibcon#end of sib2, iclass 4, count 0 2006.286.03:04:56.42#ibcon#*mode == 0, iclass 4, count 0 2006.286.03:04:56.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.03:04:56.42#ibcon#[27=USB\r\n] 2006.286.03:04:56.42#ibcon#*before write, iclass 4, count 0 2006.286.03:04:56.42#ibcon#enter sib2, iclass 4, count 0 2006.286.03:04:56.42#ibcon#flushed, iclass 4, count 0 2006.286.03:04:56.42#ibcon#about to write, iclass 4, count 0 2006.286.03:04:56.42#ibcon#wrote, iclass 4, count 0 2006.286.03:04:56.42#ibcon#about to read 3, iclass 4, count 0 2006.286.03:04:56.45#ibcon#read 3, iclass 4, count 0 2006.286.03:04:56.45#ibcon#about to read 4, iclass 4, count 0 2006.286.03:04:56.45#ibcon#read 4, iclass 4, count 0 2006.286.03:04:56.45#ibcon#about to read 5, iclass 4, count 0 2006.286.03:04:56.45#ibcon#read 5, iclass 4, count 0 2006.286.03:04:56.45#ibcon#about to read 6, iclass 4, count 0 2006.286.03:04:56.45#ibcon#read 6, iclass 4, count 0 2006.286.03:04:56.45#ibcon#end of sib2, iclass 4, count 0 2006.286.03:04:56.45#ibcon#*after write, iclass 4, count 0 2006.286.03:04:56.45#ibcon#*before return 0, iclass 4, count 0 2006.286.03:04:56.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:04:56.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:04:56.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.03:04:56.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.03:04:56.45$vck44/vblo=6,719.99 2006.286.03:04:56.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.03:04:56.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.03:04:56.45#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:56.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:04:56.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:04:56.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:04:56.45#ibcon#enter wrdev, iclass 6, count 0 2006.286.03:04:56.45#ibcon#first serial, iclass 6, count 0 2006.286.03:04:56.45#ibcon#enter sib2, iclass 6, count 0 2006.286.03:04:56.45#ibcon#flushed, iclass 6, count 0 2006.286.03:04:56.45#ibcon#about to write, iclass 6, count 0 2006.286.03:04:56.45#ibcon#wrote, iclass 6, count 0 2006.286.03:04:56.45#ibcon#about to read 3, iclass 6, count 0 2006.286.03:04:56.47#ibcon#read 3, iclass 6, count 0 2006.286.03:04:56.47#ibcon#about to read 4, iclass 6, count 0 2006.286.03:04:56.47#ibcon#read 4, iclass 6, count 0 2006.286.03:04:56.47#ibcon#about to read 5, iclass 6, count 0 2006.286.03:04:56.47#ibcon#read 5, iclass 6, count 0 2006.286.03:04:56.47#ibcon#about to read 6, iclass 6, count 0 2006.286.03:04:56.47#ibcon#read 6, iclass 6, count 0 2006.286.03:04:56.47#ibcon#end of sib2, iclass 6, count 0 2006.286.03:04:56.47#ibcon#*mode == 0, iclass 6, count 0 2006.286.03:04:56.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.03:04:56.47#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.03:04:56.47#ibcon#*before write, iclass 6, count 0 2006.286.03:04:56.47#ibcon#enter sib2, iclass 6, count 0 2006.286.03:04:56.47#ibcon#flushed, iclass 6, count 0 2006.286.03:04:56.47#ibcon#about to write, iclass 6, count 0 2006.286.03:04:56.47#ibcon#wrote, iclass 6, count 0 2006.286.03:04:56.47#ibcon#about to read 3, iclass 6, count 0 2006.286.03:04:56.51#ibcon#read 3, iclass 6, count 0 2006.286.03:04:56.51#ibcon#about to read 4, iclass 6, count 0 2006.286.03:04:56.51#ibcon#read 4, iclass 6, count 0 2006.286.03:04:56.51#ibcon#about to read 5, iclass 6, count 0 2006.286.03:04:56.51#ibcon#read 5, iclass 6, count 0 2006.286.03:04:56.51#ibcon#about to read 6, iclass 6, count 0 2006.286.03:04:56.51#ibcon#read 6, iclass 6, count 0 2006.286.03:04:56.51#ibcon#end of sib2, iclass 6, count 0 2006.286.03:04:56.51#ibcon#*after write, iclass 6, count 0 2006.286.03:04:56.51#ibcon#*before return 0, iclass 6, count 0 2006.286.03:04:56.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:04:56.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:04:56.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.03:04:56.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.03:04:56.51$vck44/vb=6,3 2006.286.03:04:56.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.03:04:56.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.03:04:56.51#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:56.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:04:56.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:04:56.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:04:56.57#ibcon#enter wrdev, iclass 10, count 2 2006.286.03:04:56.57#ibcon#first serial, iclass 10, count 2 2006.286.03:04:56.57#ibcon#enter sib2, iclass 10, count 2 2006.286.03:04:56.57#ibcon#flushed, iclass 10, count 2 2006.286.03:04:56.57#ibcon#about to write, iclass 10, count 2 2006.286.03:04:56.57#ibcon#wrote, iclass 10, count 2 2006.286.03:04:56.57#ibcon#about to read 3, iclass 10, count 2 2006.286.03:04:56.59#ibcon#read 3, iclass 10, count 2 2006.286.03:04:56.59#ibcon#about to read 4, iclass 10, count 2 2006.286.03:04:56.59#ibcon#read 4, iclass 10, count 2 2006.286.03:04:56.59#ibcon#about to read 5, iclass 10, count 2 2006.286.03:04:56.59#ibcon#read 5, iclass 10, count 2 2006.286.03:04:56.59#ibcon#about to read 6, iclass 10, count 2 2006.286.03:04:56.59#ibcon#read 6, iclass 10, count 2 2006.286.03:04:56.59#ibcon#end of sib2, iclass 10, count 2 2006.286.03:04:56.59#ibcon#*mode == 0, iclass 10, count 2 2006.286.03:04:56.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.03:04:56.59#ibcon#[27=AT06-03\r\n] 2006.286.03:04:56.59#ibcon#*before write, iclass 10, count 2 2006.286.03:04:56.59#ibcon#enter sib2, iclass 10, count 2 2006.286.03:04:56.59#ibcon#flushed, iclass 10, count 2 2006.286.03:04:56.59#ibcon#about to write, iclass 10, count 2 2006.286.03:04:56.59#ibcon#wrote, iclass 10, count 2 2006.286.03:04:56.59#ibcon#about to read 3, iclass 10, count 2 2006.286.03:04:56.62#ibcon#read 3, iclass 10, count 2 2006.286.03:04:56.62#ibcon#about to read 4, iclass 10, count 2 2006.286.03:04:56.62#ibcon#read 4, iclass 10, count 2 2006.286.03:04:56.62#ibcon#about to read 5, iclass 10, count 2 2006.286.03:04:56.62#ibcon#read 5, iclass 10, count 2 2006.286.03:04:56.62#ibcon#about to read 6, iclass 10, count 2 2006.286.03:04:56.62#ibcon#read 6, iclass 10, count 2 2006.286.03:04:56.62#ibcon#end of sib2, iclass 10, count 2 2006.286.03:04:56.62#ibcon#*after write, iclass 10, count 2 2006.286.03:04:56.62#ibcon#*before return 0, iclass 10, count 2 2006.286.03:04:56.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:04:56.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:04:56.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.03:04:56.62#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:56.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:04:56.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:04:56.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:04:56.74#ibcon#enter wrdev, iclass 10, count 0 2006.286.03:04:56.74#ibcon#first serial, iclass 10, count 0 2006.286.03:04:56.74#ibcon#enter sib2, iclass 10, count 0 2006.286.03:04:56.74#ibcon#flushed, iclass 10, count 0 2006.286.03:04:56.74#ibcon#about to write, iclass 10, count 0 2006.286.03:04:56.74#ibcon#wrote, iclass 10, count 0 2006.286.03:04:56.74#ibcon#about to read 3, iclass 10, count 0 2006.286.03:04:56.76#ibcon#read 3, iclass 10, count 0 2006.286.03:04:56.76#ibcon#about to read 4, iclass 10, count 0 2006.286.03:04:56.76#ibcon#read 4, iclass 10, count 0 2006.286.03:04:56.76#ibcon#about to read 5, iclass 10, count 0 2006.286.03:04:56.76#ibcon#read 5, iclass 10, count 0 2006.286.03:04:56.76#ibcon#about to read 6, iclass 10, count 0 2006.286.03:04:56.76#ibcon#read 6, iclass 10, count 0 2006.286.03:04:56.76#ibcon#end of sib2, iclass 10, count 0 2006.286.03:04:56.76#ibcon#*mode == 0, iclass 10, count 0 2006.286.03:04:56.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.03:04:56.76#ibcon#[27=USB\r\n] 2006.286.03:04:56.76#ibcon#*before write, iclass 10, count 0 2006.286.03:04:56.76#ibcon#enter sib2, iclass 10, count 0 2006.286.03:04:56.76#ibcon#flushed, iclass 10, count 0 2006.286.03:04:56.76#ibcon#about to write, iclass 10, count 0 2006.286.03:04:56.76#ibcon#wrote, iclass 10, count 0 2006.286.03:04:56.76#ibcon#about to read 3, iclass 10, count 0 2006.286.03:04:56.79#ibcon#read 3, iclass 10, count 0 2006.286.03:04:56.79#ibcon#about to read 4, iclass 10, count 0 2006.286.03:04:56.79#ibcon#read 4, iclass 10, count 0 2006.286.03:04:56.79#ibcon#about to read 5, iclass 10, count 0 2006.286.03:04:56.79#ibcon#read 5, iclass 10, count 0 2006.286.03:04:56.79#ibcon#about to read 6, iclass 10, count 0 2006.286.03:04:56.79#ibcon#read 6, iclass 10, count 0 2006.286.03:04:56.79#ibcon#end of sib2, iclass 10, count 0 2006.286.03:04:56.79#ibcon#*after write, iclass 10, count 0 2006.286.03:04:56.79#ibcon#*before return 0, iclass 10, count 0 2006.286.03:04:56.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:04:56.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:04:56.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.03:04:56.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.03:04:56.79$vck44/vblo=7,734.99 2006.286.03:04:56.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.03:04:56.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.03:04:56.79#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:56.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:04:56.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:04:56.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:04:56.79#ibcon#enter wrdev, iclass 12, count 0 2006.286.03:04:56.79#ibcon#first serial, iclass 12, count 0 2006.286.03:04:56.79#ibcon#enter sib2, iclass 12, count 0 2006.286.03:04:56.79#ibcon#flushed, iclass 12, count 0 2006.286.03:04:56.79#ibcon#about to write, iclass 12, count 0 2006.286.03:04:56.79#ibcon#wrote, iclass 12, count 0 2006.286.03:04:56.79#ibcon#about to read 3, iclass 12, count 0 2006.286.03:04:56.81#ibcon#read 3, iclass 12, count 0 2006.286.03:04:56.81#ibcon#about to read 4, iclass 12, count 0 2006.286.03:04:56.81#ibcon#read 4, iclass 12, count 0 2006.286.03:04:56.81#ibcon#about to read 5, iclass 12, count 0 2006.286.03:04:56.81#ibcon#read 5, iclass 12, count 0 2006.286.03:04:56.81#ibcon#about to read 6, iclass 12, count 0 2006.286.03:04:56.81#ibcon#read 6, iclass 12, count 0 2006.286.03:04:56.81#ibcon#end of sib2, iclass 12, count 0 2006.286.03:04:56.81#ibcon#*mode == 0, iclass 12, count 0 2006.286.03:04:56.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.03:04:56.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.03:04:56.81#ibcon#*before write, iclass 12, count 0 2006.286.03:04:56.81#ibcon#enter sib2, iclass 12, count 0 2006.286.03:04:56.81#ibcon#flushed, iclass 12, count 0 2006.286.03:04:56.81#ibcon#about to write, iclass 12, count 0 2006.286.03:04:56.81#ibcon#wrote, iclass 12, count 0 2006.286.03:04:56.81#ibcon#about to read 3, iclass 12, count 0 2006.286.03:04:56.85#ibcon#read 3, iclass 12, count 0 2006.286.03:04:56.85#ibcon#about to read 4, iclass 12, count 0 2006.286.03:04:56.85#ibcon#read 4, iclass 12, count 0 2006.286.03:04:56.85#ibcon#about to read 5, iclass 12, count 0 2006.286.03:04:56.85#ibcon#read 5, iclass 12, count 0 2006.286.03:04:56.85#ibcon#about to read 6, iclass 12, count 0 2006.286.03:04:56.85#ibcon#read 6, iclass 12, count 0 2006.286.03:04:56.85#ibcon#end of sib2, iclass 12, count 0 2006.286.03:04:56.85#ibcon#*after write, iclass 12, count 0 2006.286.03:04:56.85#ibcon#*before return 0, iclass 12, count 0 2006.286.03:04:56.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:04:56.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:04:56.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.03:04:56.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.03:04:56.85$vck44/vb=7,4 2006.286.03:04:56.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.03:04:56.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.03:04:56.85#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:56.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:04:56.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:04:56.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:04:56.91#ibcon#enter wrdev, iclass 14, count 2 2006.286.03:04:56.91#ibcon#first serial, iclass 14, count 2 2006.286.03:04:56.91#ibcon#enter sib2, iclass 14, count 2 2006.286.03:04:56.91#ibcon#flushed, iclass 14, count 2 2006.286.03:04:56.91#ibcon#about to write, iclass 14, count 2 2006.286.03:04:56.91#ibcon#wrote, iclass 14, count 2 2006.286.03:04:56.91#ibcon#about to read 3, iclass 14, count 2 2006.286.03:04:56.93#ibcon#read 3, iclass 14, count 2 2006.286.03:04:56.93#ibcon#about to read 4, iclass 14, count 2 2006.286.03:04:56.93#ibcon#read 4, iclass 14, count 2 2006.286.03:04:56.93#ibcon#about to read 5, iclass 14, count 2 2006.286.03:04:56.93#ibcon#read 5, iclass 14, count 2 2006.286.03:04:56.93#ibcon#about to read 6, iclass 14, count 2 2006.286.03:04:56.93#ibcon#read 6, iclass 14, count 2 2006.286.03:04:56.93#ibcon#end of sib2, iclass 14, count 2 2006.286.03:04:56.93#ibcon#*mode == 0, iclass 14, count 2 2006.286.03:04:56.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.03:04:56.93#ibcon#[27=AT07-04\r\n] 2006.286.03:04:56.93#ibcon#*before write, iclass 14, count 2 2006.286.03:04:56.93#ibcon#enter sib2, iclass 14, count 2 2006.286.03:04:56.93#ibcon#flushed, iclass 14, count 2 2006.286.03:04:56.93#ibcon#about to write, iclass 14, count 2 2006.286.03:04:56.93#ibcon#wrote, iclass 14, count 2 2006.286.03:04:56.93#ibcon#about to read 3, iclass 14, count 2 2006.286.03:04:56.96#ibcon#read 3, iclass 14, count 2 2006.286.03:04:56.96#ibcon#about to read 4, iclass 14, count 2 2006.286.03:04:56.96#ibcon#read 4, iclass 14, count 2 2006.286.03:04:56.96#ibcon#about to read 5, iclass 14, count 2 2006.286.03:04:56.96#ibcon#read 5, iclass 14, count 2 2006.286.03:04:56.96#ibcon#about to read 6, iclass 14, count 2 2006.286.03:04:56.96#ibcon#read 6, iclass 14, count 2 2006.286.03:04:56.96#ibcon#end of sib2, iclass 14, count 2 2006.286.03:04:56.96#ibcon#*after write, iclass 14, count 2 2006.286.03:04:56.96#ibcon#*before return 0, iclass 14, count 2 2006.286.03:04:56.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:04:56.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:04:56.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.03:04:56.96#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:56.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:04:57.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:04:57.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:04:57.08#ibcon#enter wrdev, iclass 14, count 0 2006.286.03:04:57.08#ibcon#first serial, iclass 14, count 0 2006.286.03:04:57.08#ibcon#enter sib2, iclass 14, count 0 2006.286.03:04:57.08#ibcon#flushed, iclass 14, count 0 2006.286.03:04:57.08#ibcon#about to write, iclass 14, count 0 2006.286.03:04:57.08#ibcon#wrote, iclass 14, count 0 2006.286.03:04:57.08#ibcon#about to read 3, iclass 14, count 0 2006.286.03:04:57.10#ibcon#read 3, iclass 14, count 0 2006.286.03:04:57.10#ibcon#about to read 4, iclass 14, count 0 2006.286.03:04:57.10#ibcon#read 4, iclass 14, count 0 2006.286.03:04:57.10#ibcon#about to read 5, iclass 14, count 0 2006.286.03:04:57.10#ibcon#read 5, iclass 14, count 0 2006.286.03:04:57.10#ibcon#about to read 6, iclass 14, count 0 2006.286.03:04:57.10#ibcon#read 6, iclass 14, count 0 2006.286.03:04:57.10#ibcon#end of sib2, iclass 14, count 0 2006.286.03:04:57.10#ibcon#*mode == 0, iclass 14, count 0 2006.286.03:04:57.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.03:04:57.10#ibcon#[27=USB\r\n] 2006.286.03:04:57.10#ibcon#*before write, iclass 14, count 0 2006.286.03:04:57.10#ibcon#enter sib2, iclass 14, count 0 2006.286.03:04:57.10#ibcon#flushed, iclass 14, count 0 2006.286.03:04:57.10#ibcon#about to write, iclass 14, count 0 2006.286.03:04:57.10#ibcon#wrote, iclass 14, count 0 2006.286.03:04:57.10#ibcon#about to read 3, iclass 14, count 0 2006.286.03:04:57.13#ibcon#read 3, iclass 14, count 0 2006.286.03:04:57.13#ibcon#about to read 4, iclass 14, count 0 2006.286.03:04:57.13#ibcon#read 4, iclass 14, count 0 2006.286.03:04:57.13#ibcon#about to read 5, iclass 14, count 0 2006.286.03:04:57.13#ibcon#read 5, iclass 14, count 0 2006.286.03:04:57.13#ibcon#about to read 6, iclass 14, count 0 2006.286.03:04:57.13#ibcon#read 6, iclass 14, count 0 2006.286.03:04:57.13#ibcon#end of sib2, iclass 14, count 0 2006.286.03:04:57.13#ibcon#*after write, iclass 14, count 0 2006.286.03:04:57.13#ibcon#*before return 0, iclass 14, count 0 2006.286.03:04:57.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:04:57.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:04:57.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.03:04:57.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.03:04:57.13$vck44/vblo=8,744.99 2006.286.03:04:57.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.03:04:57.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.03:04:57.21#ibcon#ireg 17 cls_cnt 0 2006.286.03:04:57.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:04:57.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:04:57.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:04:57.21#ibcon#enter wrdev, iclass 16, count 0 2006.286.03:04:57.21#ibcon#first serial, iclass 16, count 0 2006.286.03:04:57.21#ibcon#enter sib2, iclass 16, count 0 2006.286.03:04:57.21#ibcon#flushed, iclass 16, count 0 2006.286.03:04:57.21#ibcon#about to write, iclass 16, count 0 2006.286.03:04:57.21#ibcon#wrote, iclass 16, count 0 2006.286.03:04:57.21#ibcon#about to read 3, iclass 16, count 0 2006.286.03:04:57.23#ibcon#read 3, iclass 16, count 0 2006.286.03:04:57.23#ibcon#about to read 4, iclass 16, count 0 2006.286.03:04:57.23#ibcon#read 4, iclass 16, count 0 2006.286.03:04:57.23#ibcon#about to read 5, iclass 16, count 0 2006.286.03:04:57.23#ibcon#read 5, iclass 16, count 0 2006.286.03:04:57.23#ibcon#about to read 6, iclass 16, count 0 2006.286.03:04:57.23#ibcon#read 6, iclass 16, count 0 2006.286.03:04:57.23#ibcon#end of sib2, iclass 16, count 0 2006.286.03:04:57.23#ibcon#*mode == 0, iclass 16, count 0 2006.286.03:04:57.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.03:04:57.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.03:04:57.23#ibcon#*before write, iclass 16, count 0 2006.286.03:04:57.23#ibcon#enter sib2, iclass 16, count 0 2006.286.03:04:57.23#ibcon#flushed, iclass 16, count 0 2006.286.03:04:57.23#ibcon#about to write, iclass 16, count 0 2006.286.03:04:57.23#ibcon#wrote, iclass 16, count 0 2006.286.03:04:57.23#ibcon#about to read 3, iclass 16, count 0 2006.286.03:04:57.27#ibcon#read 3, iclass 16, count 0 2006.286.03:04:57.27#ibcon#about to read 4, iclass 16, count 0 2006.286.03:04:57.27#ibcon#read 4, iclass 16, count 0 2006.286.03:04:57.27#ibcon#about to read 5, iclass 16, count 0 2006.286.03:04:57.27#ibcon#read 5, iclass 16, count 0 2006.286.03:04:57.27#ibcon#about to read 6, iclass 16, count 0 2006.286.03:04:57.27#ibcon#read 6, iclass 16, count 0 2006.286.03:04:57.27#ibcon#end of sib2, iclass 16, count 0 2006.286.03:04:57.27#ibcon#*after write, iclass 16, count 0 2006.286.03:04:57.27#ibcon#*before return 0, iclass 16, count 0 2006.286.03:04:57.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:04:57.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:04:57.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.03:04:57.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.03:04:57.27$vck44/vb=8,4 2006.286.03:04:57.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.03:04:57.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.03:04:57.27#ibcon#ireg 11 cls_cnt 2 2006.286.03:04:57.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:04:57.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:04:57.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:04:57.27#ibcon#enter wrdev, iclass 18, count 2 2006.286.03:04:57.27#ibcon#first serial, iclass 18, count 2 2006.286.03:04:57.27#ibcon#enter sib2, iclass 18, count 2 2006.286.03:04:57.27#ibcon#flushed, iclass 18, count 2 2006.286.03:04:57.27#ibcon#about to write, iclass 18, count 2 2006.286.03:04:57.27#ibcon#wrote, iclass 18, count 2 2006.286.03:04:57.27#ibcon#about to read 3, iclass 18, count 2 2006.286.03:04:57.29#ibcon#read 3, iclass 18, count 2 2006.286.03:04:57.29#ibcon#about to read 4, iclass 18, count 2 2006.286.03:04:57.29#ibcon#read 4, iclass 18, count 2 2006.286.03:04:57.29#ibcon#about to read 5, iclass 18, count 2 2006.286.03:04:57.29#ibcon#read 5, iclass 18, count 2 2006.286.03:04:57.29#ibcon#about to read 6, iclass 18, count 2 2006.286.03:04:57.29#ibcon#read 6, iclass 18, count 2 2006.286.03:04:57.29#ibcon#end of sib2, iclass 18, count 2 2006.286.03:04:57.29#ibcon#*mode == 0, iclass 18, count 2 2006.286.03:04:57.29#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.03:04:57.29#ibcon#[27=AT08-04\r\n] 2006.286.03:04:57.29#ibcon#*before write, iclass 18, count 2 2006.286.03:04:57.29#ibcon#enter sib2, iclass 18, count 2 2006.286.03:04:57.29#ibcon#flushed, iclass 18, count 2 2006.286.03:04:57.29#ibcon#about to write, iclass 18, count 2 2006.286.03:04:57.29#ibcon#wrote, iclass 18, count 2 2006.286.03:04:57.29#ibcon#about to read 3, iclass 18, count 2 2006.286.03:04:57.32#ibcon#read 3, iclass 18, count 2 2006.286.03:04:57.32#ibcon#about to read 4, iclass 18, count 2 2006.286.03:04:57.32#ibcon#read 4, iclass 18, count 2 2006.286.03:04:57.32#ibcon#about to read 5, iclass 18, count 2 2006.286.03:04:57.32#ibcon#read 5, iclass 18, count 2 2006.286.03:04:57.32#ibcon#about to read 6, iclass 18, count 2 2006.286.03:04:57.32#ibcon#read 6, iclass 18, count 2 2006.286.03:04:57.32#ibcon#end of sib2, iclass 18, count 2 2006.286.03:04:57.32#ibcon#*after write, iclass 18, count 2 2006.286.03:04:57.32#ibcon#*before return 0, iclass 18, count 2 2006.286.03:04:57.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:04:57.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:04:57.32#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.03:04:57.32#ibcon#ireg 7 cls_cnt 0 2006.286.03:04:57.32#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:04:57.44#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:04:57.44#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:04:57.44#ibcon#enter wrdev, iclass 18, count 0 2006.286.03:04:57.44#ibcon#first serial, iclass 18, count 0 2006.286.03:04:57.44#ibcon#enter sib2, iclass 18, count 0 2006.286.03:04:57.44#ibcon#flushed, iclass 18, count 0 2006.286.03:04:57.44#ibcon#about to write, iclass 18, count 0 2006.286.03:04:57.44#ibcon#wrote, iclass 18, count 0 2006.286.03:04:57.44#ibcon#about to read 3, iclass 18, count 0 2006.286.03:04:57.46#ibcon#read 3, iclass 18, count 0 2006.286.03:04:57.46#ibcon#about to read 4, iclass 18, count 0 2006.286.03:04:57.46#ibcon#read 4, iclass 18, count 0 2006.286.03:04:57.46#ibcon#about to read 5, iclass 18, count 0 2006.286.03:04:57.46#ibcon#read 5, iclass 18, count 0 2006.286.03:04:57.46#ibcon#about to read 6, iclass 18, count 0 2006.286.03:04:57.46#ibcon#read 6, iclass 18, count 0 2006.286.03:04:57.46#ibcon#end of sib2, iclass 18, count 0 2006.286.03:04:57.46#ibcon#*mode == 0, iclass 18, count 0 2006.286.03:04:57.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.03:04:57.46#ibcon#[27=USB\r\n] 2006.286.03:04:57.46#ibcon#*before write, iclass 18, count 0 2006.286.03:04:57.46#ibcon#enter sib2, iclass 18, count 0 2006.286.03:04:57.46#ibcon#flushed, iclass 18, count 0 2006.286.03:04:57.46#ibcon#about to write, iclass 18, count 0 2006.286.03:04:57.46#ibcon#wrote, iclass 18, count 0 2006.286.03:04:57.46#ibcon#about to read 3, iclass 18, count 0 2006.286.03:04:57.49#ibcon#read 3, iclass 18, count 0 2006.286.03:04:57.49#ibcon#about to read 4, iclass 18, count 0 2006.286.03:04:57.49#ibcon#read 4, iclass 18, count 0 2006.286.03:04:57.49#ibcon#about to read 5, iclass 18, count 0 2006.286.03:04:57.49#ibcon#read 5, iclass 18, count 0 2006.286.03:04:57.49#ibcon#about to read 6, iclass 18, count 0 2006.286.03:04:57.49#ibcon#read 6, iclass 18, count 0 2006.286.03:04:57.49#ibcon#end of sib2, iclass 18, count 0 2006.286.03:04:57.49#ibcon#*after write, iclass 18, count 0 2006.286.03:04:57.49#ibcon#*before return 0, iclass 18, count 0 2006.286.03:04:57.49#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:04:57.49#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:04:57.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.03:04:57.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.03:04:57.49$vck44/vabw=wide 2006.286.03:04:57.49#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.03:04:57.49#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.03:04:57.49#ibcon#ireg 8 cls_cnt 0 2006.286.03:04:57.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:04:57.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:04:57.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:04:57.49#ibcon#enter wrdev, iclass 20, count 0 2006.286.03:04:57.49#ibcon#first serial, iclass 20, count 0 2006.286.03:04:57.49#ibcon#enter sib2, iclass 20, count 0 2006.286.03:04:57.49#ibcon#flushed, iclass 20, count 0 2006.286.03:04:57.49#ibcon#about to write, iclass 20, count 0 2006.286.03:04:57.49#ibcon#wrote, iclass 20, count 0 2006.286.03:04:57.49#ibcon#about to read 3, iclass 20, count 0 2006.286.03:04:57.51#ibcon#read 3, iclass 20, count 0 2006.286.03:04:57.51#ibcon#about to read 4, iclass 20, count 0 2006.286.03:04:57.51#ibcon#read 4, iclass 20, count 0 2006.286.03:04:57.51#ibcon#about to read 5, iclass 20, count 0 2006.286.03:04:57.51#ibcon#read 5, iclass 20, count 0 2006.286.03:04:57.51#ibcon#about to read 6, iclass 20, count 0 2006.286.03:04:57.51#ibcon#read 6, iclass 20, count 0 2006.286.03:04:57.51#ibcon#end of sib2, iclass 20, count 0 2006.286.03:04:57.51#ibcon#*mode == 0, iclass 20, count 0 2006.286.03:04:57.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.03:04:57.51#ibcon#[25=BW32\r\n] 2006.286.03:04:57.51#ibcon#*before write, iclass 20, count 0 2006.286.03:04:57.51#ibcon#enter sib2, iclass 20, count 0 2006.286.03:04:57.51#ibcon#flushed, iclass 20, count 0 2006.286.03:04:57.51#ibcon#about to write, iclass 20, count 0 2006.286.03:04:57.51#ibcon#wrote, iclass 20, count 0 2006.286.03:04:57.51#ibcon#about to read 3, iclass 20, count 0 2006.286.03:04:57.54#ibcon#read 3, iclass 20, count 0 2006.286.03:04:57.54#ibcon#about to read 4, iclass 20, count 0 2006.286.03:04:57.54#ibcon#read 4, iclass 20, count 0 2006.286.03:04:57.54#ibcon#about to read 5, iclass 20, count 0 2006.286.03:04:57.54#ibcon#read 5, iclass 20, count 0 2006.286.03:04:57.54#ibcon#about to read 6, iclass 20, count 0 2006.286.03:04:57.54#ibcon#read 6, iclass 20, count 0 2006.286.03:04:57.54#ibcon#end of sib2, iclass 20, count 0 2006.286.03:04:57.54#ibcon#*after write, iclass 20, count 0 2006.286.03:04:57.54#ibcon#*before return 0, iclass 20, count 0 2006.286.03:04:57.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:04:57.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:04:57.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.03:04:57.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.03:04:57.54$vck44/vbbw=wide 2006.286.03:04:57.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.03:04:57.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.03:04:57.54#ibcon#ireg 8 cls_cnt 0 2006.286.03:04:57.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:04:57.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:04:57.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:04:57.61#ibcon#enter wrdev, iclass 22, count 0 2006.286.03:04:57.61#ibcon#first serial, iclass 22, count 0 2006.286.03:04:57.61#ibcon#enter sib2, iclass 22, count 0 2006.286.03:04:57.61#ibcon#flushed, iclass 22, count 0 2006.286.03:04:57.61#ibcon#about to write, iclass 22, count 0 2006.286.03:04:57.61#ibcon#wrote, iclass 22, count 0 2006.286.03:04:57.61#ibcon#about to read 3, iclass 22, count 0 2006.286.03:04:57.63#ibcon#read 3, iclass 22, count 0 2006.286.03:04:57.63#ibcon#about to read 4, iclass 22, count 0 2006.286.03:04:57.63#ibcon#read 4, iclass 22, count 0 2006.286.03:04:57.63#ibcon#about to read 5, iclass 22, count 0 2006.286.03:04:57.63#ibcon#read 5, iclass 22, count 0 2006.286.03:04:57.63#ibcon#about to read 6, iclass 22, count 0 2006.286.03:04:57.63#ibcon#read 6, iclass 22, count 0 2006.286.03:04:57.63#ibcon#end of sib2, iclass 22, count 0 2006.286.03:04:57.63#ibcon#*mode == 0, iclass 22, count 0 2006.286.03:04:57.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.03:04:57.63#ibcon#[27=BW32\r\n] 2006.286.03:04:57.63#ibcon#*before write, iclass 22, count 0 2006.286.03:04:57.63#ibcon#enter sib2, iclass 22, count 0 2006.286.03:04:57.63#ibcon#flushed, iclass 22, count 0 2006.286.03:04:57.63#ibcon#about to write, iclass 22, count 0 2006.286.03:04:57.63#ibcon#wrote, iclass 22, count 0 2006.286.03:04:57.63#ibcon#about to read 3, iclass 22, count 0 2006.286.03:04:57.66#ibcon#read 3, iclass 22, count 0 2006.286.03:04:57.66#ibcon#about to read 4, iclass 22, count 0 2006.286.03:04:57.66#ibcon#read 4, iclass 22, count 0 2006.286.03:04:57.66#ibcon#about to read 5, iclass 22, count 0 2006.286.03:04:57.66#ibcon#read 5, iclass 22, count 0 2006.286.03:04:57.66#ibcon#about to read 6, iclass 22, count 0 2006.286.03:04:57.66#ibcon#read 6, iclass 22, count 0 2006.286.03:04:57.66#ibcon#end of sib2, iclass 22, count 0 2006.286.03:04:57.66#ibcon#*after write, iclass 22, count 0 2006.286.03:04:57.66#ibcon#*before return 0, iclass 22, count 0 2006.286.03:04:57.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:04:57.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:04:57.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.03:04:57.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.03:04:57.66$setupk4/ifdk4 2006.286.03:04:57.66$ifdk4/lo= 2006.286.03:04:57.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.03:04:57.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.03:04:57.66$ifdk4/patch= 2006.286.03:04:57.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.03:04:57.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.03:04:57.66$setupk4/!*+20s 2006.286.03:04:58.38#abcon#<5=/04 2.6 5.9 21.60 801015.4\r\n> 2006.286.03:04:58.40#abcon#{5=INTERFACE CLEAR} 2006.286.03:04:58.46#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:05:08.55#abcon#<5=/04 2.5 5.9 21.61 791015.4\r\n> 2006.286.03:05:08.57#abcon#{5=INTERFACE CLEAR} 2006.286.03:05:08.63#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:05:11.33$setupk4/"tpicd 2006.286.03:05:11.33$setupk4/echo=off 2006.286.03:05:11.33$setupk4/xlog=off 2006.286.03:05:11.33:!2006.286.03:08:29 2006.286.03:05:27.14#trakl#Source acquired 2006.286.03:05:27.14#flagr#flagr/antenna,acquired 2006.286.03:08:29.00:preob 2006.286.03:08:29.14/onsource/TRACKING 2006.286.03:08:29.14:!2006.286.03:08:39 2006.286.03:08:39.00:"tape 2006.286.03:08:39.00:"st=record 2006.286.03:08:39.00:data_valid=on 2006.286.03:08:39.00:midob 2006.286.03:08:39.14/onsource/TRACKING 2006.286.03:08:39.14/wx/21.68,1015.4,78 2006.286.03:08:39.19/cable/+6.4972E-03 2006.286.03:08:40.28/va/01,07,usb,yes,33,36 2006.286.03:08:40.28/va/02,06,usb,yes,34,34 2006.286.03:08:40.28/va/03,07,usb,yes,33,35 2006.286.03:08:40.28/va/04,06,usb,yes,35,36 2006.286.03:08:40.28/va/05,03,usb,yes,34,35 2006.286.03:08:40.28/va/06,04,usb,yes,31,30 2006.286.03:08:40.28/va/07,04,usb,yes,31,32 2006.286.03:08:40.28/va/08,03,usb,yes,32,39 2006.286.03:08:40.51/valo/01,524.99,yes,locked 2006.286.03:08:40.51/valo/02,534.99,yes,locked 2006.286.03:08:40.51/valo/03,564.99,yes,locked 2006.286.03:08:40.51/valo/04,624.99,yes,locked 2006.286.03:08:40.51/valo/05,734.99,yes,locked 2006.286.03:08:40.51/valo/06,814.99,yes,locked 2006.286.03:08:40.51/valo/07,864.99,yes,locked 2006.286.03:08:40.51/valo/08,884.99,yes,locked 2006.286.03:08:41.60/vb/01,04,usb,yes,31,29 2006.286.03:08:41.60/vb/02,05,usb,yes,30,29 2006.286.03:08:41.60/vb/03,04,usb,yes,30,34 2006.286.03:08:41.60/vb/04,05,usb,yes,31,30 2006.286.03:08:41.60/vb/05,04,usb,yes,27,30 2006.286.03:08:41.60/vb/06,03,usb,yes,39,35 2006.286.03:08:41.60/vb/07,04,usb,yes,31,31 2006.286.03:08:41.60/vb/08,04,usb,yes,29,32 2006.286.03:08:41.84/vblo/01,629.99,yes,locked 2006.286.03:08:41.84/vblo/02,634.99,yes,locked 2006.286.03:08:41.84/vblo/03,649.99,yes,locked 2006.286.03:08:41.84/vblo/04,679.99,yes,locked 2006.286.03:08:41.84/vblo/05,709.99,yes,locked 2006.286.03:08:41.84/vblo/06,719.99,yes,locked 2006.286.03:08:41.84/vblo/07,734.99,yes,locked 2006.286.03:08:41.84/vblo/08,744.99,yes,locked 2006.286.03:08:41.99/vabw/8 2006.286.03:08:42.14/vbbw/8 2006.286.03:08:42.23/xfe/off,on,12.0 2006.286.03:08:42.65/ifatt/23,28,28,28 2006.286.03:08:43.08/fmout-gps/S +2.71E-07 2006.286.03:08:43.10:!2006.286.03:09:19 2006.286.03:09:19.00:data_valid=off 2006.286.03:09:19.00:"et 2006.286.03:09:19.00:!+3s 2006.286.03:09:22.01:"tape 2006.286.03:09:22.01:postob 2006.286.03:09:22.15/cable/+6.4981E-03 2006.286.03:09:22.15/wx/21.69,1015.4,79 2006.286.03:09:23.08/fmout-gps/S +2.71E-07 2006.286.03:09:23.08:scan_name=286-0311,jd0610,50 2006.286.03:09:23.08:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.286.03:09:24.14#flagr#flagr/antenna,new-source 2006.286.03:09:24.14:checkk5 2006.286.03:09:24.54/chk_autoobs//k5ts1/ autoobs is running! 2006.286.03:09:25.28/chk_autoobs//k5ts2/ autoobs is running! 2006.286.03:09:25.64/chk_autoobs//k5ts3/ autoobs is running! 2006.286.03:09:26.02/chk_autoobs//k5ts4/ autoobs is running! 2006.286.03:09:26.39/chk_obsdata//k5ts1/T2860308??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:09:26.83/chk_obsdata//k5ts2/T2860308??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:09:27.29/chk_obsdata//k5ts3/T2860308??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:09:27.75/chk_obsdata//k5ts4/T2860308??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:09:28.57/k5log//k5ts1_log_newline 2006.286.03:09:29.60/k5log//k5ts2_log_newline 2006.286.03:09:30.47/k5log//k5ts3_log_newline 2006.286.03:09:31.30/k5log//k5ts4_log_newline 2006.286.03:09:31.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.03:09:31.32:setupk4=1 2006.286.03:09:31.32$setupk4/echo=on 2006.286.03:09:31.32$setupk4/pcalon 2006.286.03:09:31.32$pcalon/"no phase cal control is implemented here 2006.286.03:09:31.32$setupk4/"tpicd=stop 2006.286.03:09:31.32$setupk4/"rec=synch_on 2006.286.03:09:31.32$setupk4/"rec_mode=128 2006.286.03:09:31.32$setupk4/!* 2006.286.03:09:31.32$setupk4/recpk4 2006.286.03:09:31.32$recpk4/recpatch= 2006.286.03:09:31.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.03:09:31.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.03:09:31.32$setupk4/vck44 2006.286.03:09:31.32$vck44/valo=1,524.99 2006.286.03:09:31.32#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.03:09:31.32#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.03:09:31.32#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:31.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:09:31.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:09:31.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:09:31.32#ibcon#enter wrdev, iclass 27, count 0 2006.286.03:09:31.32#ibcon#first serial, iclass 27, count 0 2006.286.03:09:31.32#ibcon#enter sib2, iclass 27, count 0 2006.286.03:09:31.32#ibcon#flushed, iclass 27, count 0 2006.286.03:09:31.32#ibcon#about to write, iclass 27, count 0 2006.286.03:09:31.32#ibcon#wrote, iclass 27, count 0 2006.286.03:09:31.32#ibcon#about to read 3, iclass 27, count 0 2006.286.03:09:31.34#ibcon#read 3, iclass 27, count 0 2006.286.03:09:31.34#ibcon#about to read 4, iclass 27, count 0 2006.286.03:09:31.34#ibcon#read 4, iclass 27, count 0 2006.286.03:09:31.34#ibcon#about to read 5, iclass 27, count 0 2006.286.03:09:31.34#ibcon#read 5, iclass 27, count 0 2006.286.03:09:31.34#ibcon#about to read 6, iclass 27, count 0 2006.286.03:09:31.34#ibcon#read 6, iclass 27, count 0 2006.286.03:09:31.34#ibcon#end of sib2, iclass 27, count 0 2006.286.03:09:31.34#ibcon#*mode == 0, iclass 27, count 0 2006.286.03:09:31.34#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.03:09:31.34#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.03:09:31.34#ibcon#*before write, iclass 27, count 0 2006.286.03:09:31.34#ibcon#enter sib2, iclass 27, count 0 2006.286.03:09:31.34#ibcon#flushed, iclass 27, count 0 2006.286.03:09:31.34#ibcon#about to write, iclass 27, count 0 2006.286.03:09:31.34#ibcon#wrote, iclass 27, count 0 2006.286.03:09:31.34#ibcon#about to read 3, iclass 27, count 0 2006.286.03:09:31.39#ibcon#read 3, iclass 27, count 0 2006.286.03:09:31.39#ibcon#about to read 4, iclass 27, count 0 2006.286.03:09:31.39#ibcon#read 4, iclass 27, count 0 2006.286.03:09:31.39#ibcon#about to read 5, iclass 27, count 0 2006.286.03:09:31.39#ibcon#read 5, iclass 27, count 0 2006.286.03:09:31.39#ibcon#about to read 6, iclass 27, count 0 2006.286.03:09:31.39#ibcon#read 6, iclass 27, count 0 2006.286.03:09:31.39#ibcon#end of sib2, iclass 27, count 0 2006.286.03:09:31.39#ibcon#*after write, iclass 27, count 0 2006.286.03:09:31.39#ibcon#*before return 0, iclass 27, count 0 2006.286.03:09:31.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:09:31.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:09:31.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.03:09:31.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.03:09:31.39$vck44/va=1,7 2006.286.03:09:31.39#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.03:09:31.39#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.03:09:31.39#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:31.39#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:09:31.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:09:31.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:09:31.39#ibcon#enter wrdev, iclass 29, count 2 2006.286.03:09:31.39#ibcon#first serial, iclass 29, count 2 2006.286.03:09:31.39#ibcon#enter sib2, iclass 29, count 2 2006.286.03:09:31.39#ibcon#flushed, iclass 29, count 2 2006.286.03:09:31.39#ibcon#about to write, iclass 29, count 2 2006.286.03:09:31.39#ibcon#wrote, iclass 29, count 2 2006.286.03:09:31.39#ibcon#about to read 3, iclass 29, count 2 2006.286.03:09:31.41#ibcon#read 3, iclass 29, count 2 2006.286.03:09:31.41#ibcon#about to read 4, iclass 29, count 2 2006.286.03:09:31.41#ibcon#read 4, iclass 29, count 2 2006.286.03:09:31.41#ibcon#about to read 5, iclass 29, count 2 2006.286.03:09:31.41#ibcon#read 5, iclass 29, count 2 2006.286.03:09:31.41#ibcon#about to read 6, iclass 29, count 2 2006.286.03:09:31.41#ibcon#read 6, iclass 29, count 2 2006.286.03:09:31.41#ibcon#end of sib2, iclass 29, count 2 2006.286.03:09:31.41#ibcon#*mode == 0, iclass 29, count 2 2006.286.03:09:31.41#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.03:09:31.41#ibcon#[25=AT01-07\r\n] 2006.286.03:09:31.41#ibcon#*before write, iclass 29, count 2 2006.286.03:09:31.41#ibcon#enter sib2, iclass 29, count 2 2006.286.03:09:31.41#ibcon#flushed, iclass 29, count 2 2006.286.03:09:31.41#ibcon#about to write, iclass 29, count 2 2006.286.03:09:31.41#ibcon#wrote, iclass 29, count 2 2006.286.03:09:31.41#ibcon#about to read 3, iclass 29, count 2 2006.286.03:09:31.44#ibcon#read 3, iclass 29, count 2 2006.286.03:09:31.44#ibcon#about to read 4, iclass 29, count 2 2006.286.03:09:31.44#ibcon#read 4, iclass 29, count 2 2006.286.03:09:31.44#ibcon#about to read 5, iclass 29, count 2 2006.286.03:09:31.44#ibcon#read 5, iclass 29, count 2 2006.286.03:09:31.44#ibcon#about to read 6, iclass 29, count 2 2006.286.03:09:31.44#ibcon#read 6, iclass 29, count 2 2006.286.03:09:31.44#ibcon#end of sib2, iclass 29, count 2 2006.286.03:09:31.44#ibcon#*after write, iclass 29, count 2 2006.286.03:09:31.44#ibcon#*before return 0, iclass 29, count 2 2006.286.03:09:31.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:09:31.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:09:31.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.03:09:31.44#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:31.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:09:31.56#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:09:31.56#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:09:31.56#ibcon#enter wrdev, iclass 29, count 0 2006.286.03:09:31.56#ibcon#first serial, iclass 29, count 0 2006.286.03:09:31.56#ibcon#enter sib2, iclass 29, count 0 2006.286.03:09:31.56#ibcon#flushed, iclass 29, count 0 2006.286.03:09:31.56#ibcon#about to write, iclass 29, count 0 2006.286.03:09:31.56#ibcon#wrote, iclass 29, count 0 2006.286.03:09:31.56#ibcon#about to read 3, iclass 29, count 0 2006.286.03:09:31.58#ibcon#read 3, iclass 29, count 0 2006.286.03:09:31.58#ibcon#about to read 4, iclass 29, count 0 2006.286.03:09:31.58#ibcon#read 4, iclass 29, count 0 2006.286.03:09:31.58#ibcon#about to read 5, iclass 29, count 0 2006.286.03:09:31.58#ibcon#read 5, iclass 29, count 0 2006.286.03:09:31.58#ibcon#about to read 6, iclass 29, count 0 2006.286.03:09:31.58#ibcon#read 6, iclass 29, count 0 2006.286.03:09:31.58#ibcon#end of sib2, iclass 29, count 0 2006.286.03:09:31.58#ibcon#*mode == 0, iclass 29, count 0 2006.286.03:09:31.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.03:09:31.58#ibcon#[25=USB\r\n] 2006.286.03:09:31.58#ibcon#*before write, iclass 29, count 0 2006.286.03:09:31.58#ibcon#enter sib2, iclass 29, count 0 2006.286.03:09:31.58#ibcon#flushed, iclass 29, count 0 2006.286.03:09:31.58#ibcon#about to write, iclass 29, count 0 2006.286.03:09:31.58#ibcon#wrote, iclass 29, count 0 2006.286.03:09:31.58#ibcon#about to read 3, iclass 29, count 0 2006.286.03:09:31.61#ibcon#read 3, iclass 29, count 0 2006.286.03:09:31.61#ibcon#about to read 4, iclass 29, count 0 2006.286.03:09:31.61#ibcon#read 4, iclass 29, count 0 2006.286.03:09:31.61#ibcon#about to read 5, iclass 29, count 0 2006.286.03:09:31.61#ibcon#read 5, iclass 29, count 0 2006.286.03:09:31.61#ibcon#about to read 6, iclass 29, count 0 2006.286.03:09:31.61#ibcon#read 6, iclass 29, count 0 2006.286.03:09:31.61#ibcon#end of sib2, iclass 29, count 0 2006.286.03:09:31.61#ibcon#*after write, iclass 29, count 0 2006.286.03:09:31.61#ibcon#*before return 0, iclass 29, count 0 2006.286.03:09:31.61#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:09:31.61#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:09:31.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.03:09:31.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.03:09:31.61$vck44/valo=2,534.99 2006.286.03:09:31.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.03:09:31.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.03:09:31.61#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:31.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:09:31.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:09:31.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:09:31.61#ibcon#enter wrdev, iclass 31, count 0 2006.286.03:09:31.61#ibcon#first serial, iclass 31, count 0 2006.286.03:09:31.61#ibcon#enter sib2, iclass 31, count 0 2006.286.03:09:31.61#ibcon#flushed, iclass 31, count 0 2006.286.03:09:31.61#ibcon#about to write, iclass 31, count 0 2006.286.03:09:31.61#ibcon#wrote, iclass 31, count 0 2006.286.03:09:31.61#ibcon#about to read 3, iclass 31, count 0 2006.286.03:09:31.63#ibcon#read 3, iclass 31, count 0 2006.286.03:09:31.63#ibcon#about to read 4, iclass 31, count 0 2006.286.03:09:31.63#ibcon#read 4, iclass 31, count 0 2006.286.03:09:31.63#ibcon#about to read 5, iclass 31, count 0 2006.286.03:09:31.63#ibcon#read 5, iclass 31, count 0 2006.286.03:09:31.63#ibcon#about to read 6, iclass 31, count 0 2006.286.03:09:31.63#ibcon#read 6, iclass 31, count 0 2006.286.03:09:31.63#ibcon#end of sib2, iclass 31, count 0 2006.286.03:09:31.63#ibcon#*mode == 0, iclass 31, count 0 2006.286.03:09:31.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.03:09:31.63#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.03:09:31.63#ibcon#*before write, iclass 31, count 0 2006.286.03:09:31.63#ibcon#enter sib2, iclass 31, count 0 2006.286.03:09:31.63#ibcon#flushed, iclass 31, count 0 2006.286.03:09:31.63#ibcon#about to write, iclass 31, count 0 2006.286.03:09:31.63#ibcon#wrote, iclass 31, count 0 2006.286.03:09:31.63#ibcon#about to read 3, iclass 31, count 0 2006.286.03:09:31.67#ibcon#read 3, iclass 31, count 0 2006.286.03:09:31.67#ibcon#about to read 4, iclass 31, count 0 2006.286.03:09:31.67#ibcon#read 4, iclass 31, count 0 2006.286.03:09:31.67#ibcon#about to read 5, iclass 31, count 0 2006.286.03:09:31.67#ibcon#read 5, iclass 31, count 0 2006.286.03:09:31.67#ibcon#about to read 6, iclass 31, count 0 2006.286.03:09:31.67#ibcon#read 6, iclass 31, count 0 2006.286.03:09:31.67#ibcon#end of sib2, iclass 31, count 0 2006.286.03:09:31.67#ibcon#*after write, iclass 31, count 0 2006.286.03:09:31.67#ibcon#*before return 0, iclass 31, count 0 2006.286.03:09:31.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:09:31.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:09:31.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.03:09:31.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.03:09:31.67$vck44/va=2,6 2006.286.03:09:31.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.03:09:31.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.03:09:31.67#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:31.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:09:31.73#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:09:31.73#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:09:31.73#ibcon#enter wrdev, iclass 33, count 2 2006.286.03:09:31.73#ibcon#first serial, iclass 33, count 2 2006.286.03:09:31.73#ibcon#enter sib2, iclass 33, count 2 2006.286.03:09:31.73#ibcon#flushed, iclass 33, count 2 2006.286.03:09:31.73#ibcon#about to write, iclass 33, count 2 2006.286.03:09:31.73#ibcon#wrote, iclass 33, count 2 2006.286.03:09:31.73#ibcon#about to read 3, iclass 33, count 2 2006.286.03:09:31.75#ibcon#read 3, iclass 33, count 2 2006.286.03:09:31.75#ibcon#about to read 4, iclass 33, count 2 2006.286.03:09:31.75#ibcon#read 4, iclass 33, count 2 2006.286.03:09:31.75#ibcon#about to read 5, iclass 33, count 2 2006.286.03:09:31.75#ibcon#read 5, iclass 33, count 2 2006.286.03:09:31.75#ibcon#about to read 6, iclass 33, count 2 2006.286.03:09:31.75#ibcon#read 6, iclass 33, count 2 2006.286.03:09:31.75#ibcon#end of sib2, iclass 33, count 2 2006.286.03:09:31.75#ibcon#*mode == 0, iclass 33, count 2 2006.286.03:09:31.75#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.03:09:31.75#ibcon#[25=AT02-06\r\n] 2006.286.03:09:31.75#ibcon#*before write, iclass 33, count 2 2006.286.03:09:31.75#ibcon#enter sib2, iclass 33, count 2 2006.286.03:09:31.75#ibcon#flushed, iclass 33, count 2 2006.286.03:09:31.75#ibcon#about to write, iclass 33, count 2 2006.286.03:09:31.75#ibcon#wrote, iclass 33, count 2 2006.286.03:09:31.75#ibcon#about to read 3, iclass 33, count 2 2006.286.03:09:31.78#ibcon#read 3, iclass 33, count 2 2006.286.03:09:31.78#ibcon#about to read 4, iclass 33, count 2 2006.286.03:09:31.78#ibcon#read 4, iclass 33, count 2 2006.286.03:09:31.78#ibcon#about to read 5, iclass 33, count 2 2006.286.03:09:31.78#ibcon#read 5, iclass 33, count 2 2006.286.03:09:31.78#ibcon#about to read 6, iclass 33, count 2 2006.286.03:09:31.78#ibcon#read 6, iclass 33, count 2 2006.286.03:09:31.78#ibcon#end of sib2, iclass 33, count 2 2006.286.03:09:31.78#ibcon#*after write, iclass 33, count 2 2006.286.03:09:31.78#ibcon#*before return 0, iclass 33, count 2 2006.286.03:09:31.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:09:31.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:09:31.78#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.03:09:31.78#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:31.78#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:09:31.90#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:09:32.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:09:32.44#ibcon#enter wrdev, iclass 33, count 0 2006.286.03:09:32.44#ibcon#first serial, iclass 33, count 0 2006.286.03:09:32.44#ibcon#enter sib2, iclass 33, count 0 2006.286.03:09:32.44#ibcon#flushed, iclass 33, count 0 2006.286.03:09:32.44#ibcon#about to write, iclass 33, count 0 2006.286.03:09:32.44#ibcon#wrote, iclass 33, count 0 2006.286.03:09:32.44#ibcon#about to read 3, iclass 33, count 0 2006.286.03:09:32.46#ibcon#read 3, iclass 33, count 0 2006.286.03:09:32.46#ibcon#about to read 4, iclass 33, count 0 2006.286.03:09:32.46#ibcon#read 4, iclass 33, count 0 2006.286.03:09:32.46#ibcon#about to read 5, iclass 33, count 0 2006.286.03:09:32.46#ibcon#read 5, iclass 33, count 0 2006.286.03:09:32.46#ibcon#about to read 6, iclass 33, count 0 2006.286.03:09:32.46#ibcon#read 6, iclass 33, count 0 2006.286.03:09:32.46#ibcon#end of sib2, iclass 33, count 0 2006.286.03:09:32.46#ibcon#*mode == 0, iclass 33, count 0 2006.286.03:09:32.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.03:09:32.46#ibcon#[25=USB\r\n] 2006.286.03:09:32.46#ibcon#*before write, iclass 33, count 0 2006.286.03:09:32.46#ibcon#enter sib2, iclass 33, count 0 2006.286.03:09:32.46#ibcon#flushed, iclass 33, count 0 2006.286.03:09:32.46#ibcon#about to write, iclass 33, count 0 2006.286.03:09:32.46#ibcon#wrote, iclass 33, count 0 2006.286.03:09:32.46#ibcon#about to read 3, iclass 33, count 0 2006.286.03:09:32.49#ibcon#read 3, iclass 33, count 0 2006.286.03:09:32.49#ibcon#about to read 4, iclass 33, count 0 2006.286.03:09:32.49#ibcon#read 4, iclass 33, count 0 2006.286.03:09:32.49#ibcon#about to read 5, iclass 33, count 0 2006.286.03:09:32.49#ibcon#read 5, iclass 33, count 0 2006.286.03:09:32.49#ibcon#about to read 6, iclass 33, count 0 2006.286.03:09:32.49#ibcon#read 6, iclass 33, count 0 2006.286.03:09:32.49#ibcon#end of sib2, iclass 33, count 0 2006.286.03:09:32.49#ibcon#*after write, iclass 33, count 0 2006.286.03:09:32.49#ibcon#*before return 0, iclass 33, count 0 2006.286.03:09:32.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:09:32.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:09:32.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.03:09:32.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.03:09:32.49$vck44/valo=3,564.99 2006.286.03:09:32.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.03:09:32.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.03:09:32.49#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:32.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:09:32.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:09:32.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:09:32.49#ibcon#enter wrdev, iclass 35, count 0 2006.286.03:09:32.49#ibcon#first serial, iclass 35, count 0 2006.286.03:09:32.49#ibcon#enter sib2, iclass 35, count 0 2006.286.03:09:32.49#ibcon#flushed, iclass 35, count 0 2006.286.03:09:32.49#ibcon#about to write, iclass 35, count 0 2006.286.03:09:32.49#ibcon#wrote, iclass 35, count 0 2006.286.03:09:32.49#ibcon#about to read 3, iclass 35, count 0 2006.286.03:09:32.51#ibcon#read 3, iclass 35, count 0 2006.286.03:09:32.51#ibcon#about to read 4, iclass 35, count 0 2006.286.03:09:32.51#ibcon#read 4, iclass 35, count 0 2006.286.03:09:32.51#ibcon#about to read 5, iclass 35, count 0 2006.286.03:09:32.51#ibcon#read 5, iclass 35, count 0 2006.286.03:09:32.51#ibcon#about to read 6, iclass 35, count 0 2006.286.03:09:32.51#ibcon#read 6, iclass 35, count 0 2006.286.03:09:32.51#ibcon#end of sib2, iclass 35, count 0 2006.286.03:09:32.51#ibcon#*mode == 0, iclass 35, count 0 2006.286.03:09:32.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.03:09:32.51#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.03:09:32.51#ibcon#*before write, iclass 35, count 0 2006.286.03:09:32.51#ibcon#enter sib2, iclass 35, count 0 2006.286.03:09:32.51#ibcon#flushed, iclass 35, count 0 2006.286.03:09:32.51#ibcon#about to write, iclass 35, count 0 2006.286.03:09:32.51#ibcon#wrote, iclass 35, count 0 2006.286.03:09:32.51#ibcon#about to read 3, iclass 35, count 0 2006.286.03:09:32.55#ibcon#read 3, iclass 35, count 0 2006.286.03:09:32.55#ibcon#about to read 4, iclass 35, count 0 2006.286.03:09:32.55#ibcon#read 4, iclass 35, count 0 2006.286.03:09:32.55#ibcon#about to read 5, iclass 35, count 0 2006.286.03:09:32.55#ibcon#read 5, iclass 35, count 0 2006.286.03:09:32.55#ibcon#about to read 6, iclass 35, count 0 2006.286.03:09:32.55#ibcon#read 6, iclass 35, count 0 2006.286.03:09:32.55#ibcon#end of sib2, iclass 35, count 0 2006.286.03:09:32.55#ibcon#*after write, iclass 35, count 0 2006.286.03:09:32.55#ibcon#*before return 0, iclass 35, count 0 2006.286.03:09:32.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:09:32.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:09:32.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.03:09:32.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.03:09:32.55$vck44/va=3,7 2006.286.03:09:32.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.03:09:32.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.03:09:32.55#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:32.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:09:32.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:09:32.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:09:32.61#ibcon#enter wrdev, iclass 37, count 2 2006.286.03:09:32.61#ibcon#first serial, iclass 37, count 2 2006.286.03:09:32.61#ibcon#enter sib2, iclass 37, count 2 2006.286.03:09:32.61#ibcon#flushed, iclass 37, count 2 2006.286.03:09:32.61#ibcon#about to write, iclass 37, count 2 2006.286.03:09:32.61#ibcon#wrote, iclass 37, count 2 2006.286.03:09:32.61#ibcon#about to read 3, iclass 37, count 2 2006.286.03:09:32.63#ibcon#read 3, iclass 37, count 2 2006.286.03:09:32.63#ibcon#about to read 4, iclass 37, count 2 2006.286.03:09:32.63#ibcon#read 4, iclass 37, count 2 2006.286.03:09:32.63#ibcon#about to read 5, iclass 37, count 2 2006.286.03:09:32.63#ibcon#read 5, iclass 37, count 2 2006.286.03:09:32.63#ibcon#about to read 6, iclass 37, count 2 2006.286.03:09:32.63#ibcon#read 6, iclass 37, count 2 2006.286.03:09:32.63#ibcon#end of sib2, iclass 37, count 2 2006.286.03:09:32.63#ibcon#*mode == 0, iclass 37, count 2 2006.286.03:09:32.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.03:09:32.63#ibcon#[25=AT03-07\r\n] 2006.286.03:09:32.63#ibcon#*before write, iclass 37, count 2 2006.286.03:09:32.63#ibcon#enter sib2, iclass 37, count 2 2006.286.03:09:32.63#ibcon#flushed, iclass 37, count 2 2006.286.03:09:32.63#ibcon#about to write, iclass 37, count 2 2006.286.03:09:32.63#ibcon#wrote, iclass 37, count 2 2006.286.03:09:32.63#ibcon#about to read 3, iclass 37, count 2 2006.286.03:09:32.66#ibcon#read 3, iclass 37, count 2 2006.286.03:09:32.66#ibcon#about to read 4, iclass 37, count 2 2006.286.03:09:32.66#ibcon#read 4, iclass 37, count 2 2006.286.03:09:32.66#ibcon#about to read 5, iclass 37, count 2 2006.286.03:09:32.66#ibcon#read 5, iclass 37, count 2 2006.286.03:09:32.66#ibcon#about to read 6, iclass 37, count 2 2006.286.03:09:32.66#ibcon#read 6, iclass 37, count 2 2006.286.03:09:32.66#ibcon#end of sib2, iclass 37, count 2 2006.286.03:09:32.66#ibcon#*after write, iclass 37, count 2 2006.286.03:09:32.66#ibcon#*before return 0, iclass 37, count 2 2006.286.03:09:32.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:09:32.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:09:32.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.03:09:32.66#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:32.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:09:32.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:09:32.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:09:32.78#ibcon#enter wrdev, iclass 37, count 0 2006.286.03:09:32.78#ibcon#first serial, iclass 37, count 0 2006.286.03:09:32.78#ibcon#enter sib2, iclass 37, count 0 2006.286.03:09:32.78#ibcon#flushed, iclass 37, count 0 2006.286.03:09:32.78#ibcon#about to write, iclass 37, count 0 2006.286.03:09:32.78#ibcon#wrote, iclass 37, count 0 2006.286.03:09:32.78#ibcon#about to read 3, iclass 37, count 0 2006.286.03:09:32.80#ibcon#read 3, iclass 37, count 0 2006.286.03:09:32.80#ibcon#about to read 4, iclass 37, count 0 2006.286.03:09:32.80#ibcon#read 4, iclass 37, count 0 2006.286.03:09:32.80#ibcon#about to read 5, iclass 37, count 0 2006.286.03:09:32.80#ibcon#read 5, iclass 37, count 0 2006.286.03:09:32.80#ibcon#about to read 6, iclass 37, count 0 2006.286.03:09:32.80#ibcon#read 6, iclass 37, count 0 2006.286.03:09:32.80#ibcon#end of sib2, iclass 37, count 0 2006.286.03:09:32.80#ibcon#*mode == 0, iclass 37, count 0 2006.286.03:09:32.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.03:09:32.80#ibcon#[25=USB\r\n] 2006.286.03:09:32.80#ibcon#*before write, iclass 37, count 0 2006.286.03:09:32.80#ibcon#enter sib2, iclass 37, count 0 2006.286.03:09:32.80#ibcon#flushed, iclass 37, count 0 2006.286.03:09:32.80#ibcon#about to write, iclass 37, count 0 2006.286.03:09:32.80#ibcon#wrote, iclass 37, count 0 2006.286.03:09:32.80#ibcon#about to read 3, iclass 37, count 0 2006.286.03:09:32.83#ibcon#read 3, iclass 37, count 0 2006.286.03:09:32.83#ibcon#about to read 4, iclass 37, count 0 2006.286.03:09:32.83#ibcon#read 4, iclass 37, count 0 2006.286.03:09:32.83#ibcon#about to read 5, iclass 37, count 0 2006.286.03:09:32.83#ibcon#read 5, iclass 37, count 0 2006.286.03:09:32.83#ibcon#about to read 6, iclass 37, count 0 2006.286.03:09:32.83#ibcon#read 6, iclass 37, count 0 2006.286.03:09:32.83#ibcon#end of sib2, iclass 37, count 0 2006.286.03:09:32.83#ibcon#*after write, iclass 37, count 0 2006.286.03:09:32.83#ibcon#*before return 0, iclass 37, count 0 2006.286.03:09:32.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:09:32.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:09:32.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.03:09:32.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.03:09:32.83$vck44/valo=4,624.99 2006.286.03:09:32.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.03:09:32.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.03:09:32.83#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:32.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:09:32.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:09:32.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:09:32.83#ibcon#enter wrdev, iclass 39, count 0 2006.286.03:09:32.83#ibcon#first serial, iclass 39, count 0 2006.286.03:09:32.83#ibcon#enter sib2, iclass 39, count 0 2006.286.03:09:32.83#ibcon#flushed, iclass 39, count 0 2006.286.03:09:32.83#ibcon#about to write, iclass 39, count 0 2006.286.03:09:32.83#ibcon#wrote, iclass 39, count 0 2006.286.03:09:32.83#ibcon#about to read 3, iclass 39, count 0 2006.286.03:09:32.85#ibcon#read 3, iclass 39, count 0 2006.286.03:09:33.12#ibcon#about to read 4, iclass 39, count 0 2006.286.03:09:33.12#ibcon#read 4, iclass 39, count 0 2006.286.03:09:33.12#ibcon#about to read 5, iclass 39, count 0 2006.286.03:09:33.12#ibcon#read 5, iclass 39, count 0 2006.286.03:09:33.12#ibcon#about to read 6, iclass 39, count 0 2006.286.03:09:33.12#ibcon#read 6, iclass 39, count 0 2006.286.03:09:33.12#ibcon#end of sib2, iclass 39, count 0 2006.286.03:09:33.12#ibcon#*mode == 0, iclass 39, count 0 2006.286.03:09:33.12#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.03:09:33.12#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.03:09:33.12#ibcon#*before write, iclass 39, count 0 2006.286.03:09:33.12#ibcon#enter sib2, iclass 39, count 0 2006.286.03:09:33.12#ibcon#flushed, iclass 39, count 0 2006.286.03:09:33.12#ibcon#about to write, iclass 39, count 0 2006.286.03:09:33.12#ibcon#wrote, iclass 39, count 0 2006.286.03:09:33.12#ibcon#about to read 3, iclass 39, count 0 2006.286.03:09:33.17#ibcon#read 3, iclass 39, count 0 2006.286.03:09:33.17#ibcon#about to read 4, iclass 39, count 0 2006.286.03:09:33.17#ibcon#read 4, iclass 39, count 0 2006.286.03:09:33.17#ibcon#about to read 5, iclass 39, count 0 2006.286.03:09:33.17#ibcon#read 5, iclass 39, count 0 2006.286.03:09:33.17#ibcon#about to read 6, iclass 39, count 0 2006.286.03:09:33.17#ibcon#read 6, iclass 39, count 0 2006.286.03:09:33.17#ibcon#end of sib2, iclass 39, count 0 2006.286.03:09:33.17#ibcon#*after write, iclass 39, count 0 2006.286.03:09:33.17#ibcon#*before return 0, iclass 39, count 0 2006.286.03:09:33.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:09:33.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:09:33.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.03:09:33.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.03:09:33.17$vck44/va=4,6 2006.286.03:09:33.17#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.03:09:33.17#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.03:09:33.17#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:33.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:09:33.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:09:33.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:09:33.17#ibcon#enter wrdev, iclass 4, count 2 2006.286.03:09:33.17#ibcon#first serial, iclass 4, count 2 2006.286.03:09:33.17#ibcon#enter sib2, iclass 4, count 2 2006.286.03:09:33.17#ibcon#flushed, iclass 4, count 2 2006.286.03:09:33.17#ibcon#about to write, iclass 4, count 2 2006.286.03:09:33.17#ibcon#wrote, iclass 4, count 2 2006.286.03:09:33.17#ibcon#about to read 3, iclass 4, count 2 2006.286.03:09:33.17#abcon#<5=/04 3.0 5.9 21.69 781015.4\r\n> 2006.286.03:09:33.19#ibcon#read 3, iclass 4, count 2 2006.286.03:09:33.19#ibcon#about to read 4, iclass 4, count 2 2006.286.03:09:33.19#ibcon#read 4, iclass 4, count 2 2006.286.03:09:33.19#ibcon#about to read 5, iclass 4, count 2 2006.286.03:09:33.19#ibcon#read 5, iclass 4, count 2 2006.286.03:09:33.19#ibcon#about to read 6, iclass 4, count 2 2006.286.03:09:33.19#ibcon#read 6, iclass 4, count 2 2006.286.03:09:33.19#ibcon#end of sib2, iclass 4, count 2 2006.286.03:09:33.19#ibcon#*mode == 0, iclass 4, count 2 2006.286.03:09:33.19#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.03:09:33.19#ibcon#[25=AT04-06\r\n] 2006.286.03:09:33.19#ibcon#*before write, iclass 4, count 2 2006.286.03:09:33.19#ibcon#enter sib2, iclass 4, count 2 2006.286.03:09:33.19#ibcon#flushed, iclass 4, count 2 2006.286.03:09:33.19#ibcon#about to write, iclass 4, count 2 2006.286.03:09:33.19#ibcon#wrote, iclass 4, count 2 2006.286.03:09:33.19#ibcon#about to read 3, iclass 4, count 2 2006.286.03:09:33.19#abcon#{5=INTERFACE CLEAR} 2006.286.03:09:33.22#ibcon#read 3, iclass 4, count 2 2006.286.03:09:33.22#ibcon#about to read 4, iclass 4, count 2 2006.286.03:09:33.22#ibcon#read 4, iclass 4, count 2 2006.286.03:09:33.22#ibcon#about to read 5, iclass 4, count 2 2006.286.03:09:33.22#ibcon#read 5, iclass 4, count 2 2006.286.03:09:33.22#ibcon#about to read 6, iclass 4, count 2 2006.286.03:09:33.22#ibcon#read 6, iclass 4, count 2 2006.286.03:09:33.22#ibcon#end of sib2, iclass 4, count 2 2006.286.03:09:33.22#ibcon#*after write, iclass 4, count 2 2006.286.03:09:33.22#ibcon#*before return 0, iclass 4, count 2 2006.286.03:09:33.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:09:33.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:09:33.22#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.03:09:33.22#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:33.22#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:09:33.25#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:09:33.34#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:09:33.34#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:09:33.34#ibcon#enter wrdev, iclass 4, count 0 2006.286.03:09:33.34#ibcon#first serial, iclass 4, count 0 2006.286.03:09:33.34#ibcon#enter sib2, iclass 4, count 0 2006.286.03:09:33.34#ibcon#flushed, iclass 4, count 0 2006.286.03:09:33.34#ibcon#about to write, iclass 4, count 0 2006.286.03:09:33.34#ibcon#wrote, iclass 4, count 0 2006.286.03:09:33.34#ibcon#about to read 3, iclass 4, count 0 2006.286.03:09:33.36#ibcon#read 3, iclass 4, count 0 2006.286.03:09:33.36#ibcon#about to read 4, iclass 4, count 0 2006.286.03:09:33.36#ibcon#read 4, iclass 4, count 0 2006.286.03:09:33.36#ibcon#about to read 5, iclass 4, count 0 2006.286.03:09:33.36#ibcon#read 5, iclass 4, count 0 2006.286.03:09:33.36#ibcon#about to read 6, iclass 4, count 0 2006.286.03:09:33.36#ibcon#read 6, iclass 4, count 0 2006.286.03:09:33.36#ibcon#end of sib2, iclass 4, count 0 2006.286.03:09:33.36#ibcon#*mode == 0, iclass 4, count 0 2006.286.03:09:33.36#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.03:09:33.36#ibcon#[25=USB\r\n] 2006.286.03:09:33.36#ibcon#*before write, iclass 4, count 0 2006.286.03:09:33.36#ibcon#enter sib2, iclass 4, count 0 2006.286.03:09:33.36#ibcon#flushed, iclass 4, count 0 2006.286.03:09:33.36#ibcon#about to write, iclass 4, count 0 2006.286.03:09:33.36#ibcon#wrote, iclass 4, count 0 2006.286.03:09:33.36#ibcon#about to read 3, iclass 4, count 0 2006.286.03:09:33.39#ibcon#read 3, iclass 4, count 0 2006.286.03:09:33.39#ibcon#about to read 4, iclass 4, count 0 2006.286.03:09:33.39#ibcon#read 4, iclass 4, count 0 2006.286.03:09:33.39#ibcon#about to read 5, iclass 4, count 0 2006.286.03:09:33.39#ibcon#read 5, iclass 4, count 0 2006.286.03:09:33.39#ibcon#about to read 6, iclass 4, count 0 2006.286.03:09:33.39#ibcon#read 6, iclass 4, count 0 2006.286.03:09:33.39#ibcon#end of sib2, iclass 4, count 0 2006.286.03:09:33.39#ibcon#*after write, iclass 4, count 0 2006.286.03:09:33.39#ibcon#*before return 0, iclass 4, count 0 2006.286.03:09:33.39#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:09:33.39#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:09:33.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.03:09:33.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.03:09:33.39$vck44/valo=5,734.99 2006.286.03:09:33.39#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.03:09:33.39#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.03:09:33.39#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:33.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:09:33.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:09:33.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:09:33.39#ibcon#enter wrdev, iclass 11, count 0 2006.286.03:09:33.39#ibcon#first serial, iclass 11, count 0 2006.286.03:09:33.39#ibcon#enter sib2, iclass 11, count 0 2006.286.03:09:33.39#ibcon#flushed, iclass 11, count 0 2006.286.03:09:33.39#ibcon#about to write, iclass 11, count 0 2006.286.03:09:33.39#ibcon#wrote, iclass 11, count 0 2006.286.03:09:33.39#ibcon#about to read 3, iclass 11, count 0 2006.286.03:09:33.41#ibcon#read 3, iclass 11, count 0 2006.286.03:09:33.41#ibcon#about to read 4, iclass 11, count 0 2006.286.03:09:33.41#ibcon#read 4, iclass 11, count 0 2006.286.03:09:33.41#ibcon#about to read 5, iclass 11, count 0 2006.286.03:09:33.41#ibcon#read 5, iclass 11, count 0 2006.286.03:09:33.41#ibcon#about to read 6, iclass 11, count 0 2006.286.03:09:33.41#ibcon#read 6, iclass 11, count 0 2006.286.03:09:33.41#ibcon#end of sib2, iclass 11, count 0 2006.286.03:09:33.41#ibcon#*mode == 0, iclass 11, count 0 2006.286.03:09:33.41#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.03:09:33.41#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.03:09:33.41#ibcon#*before write, iclass 11, count 0 2006.286.03:09:33.41#ibcon#enter sib2, iclass 11, count 0 2006.286.03:09:33.41#ibcon#flushed, iclass 11, count 0 2006.286.03:09:33.41#ibcon#about to write, iclass 11, count 0 2006.286.03:09:33.41#ibcon#wrote, iclass 11, count 0 2006.286.03:09:33.41#ibcon#about to read 3, iclass 11, count 0 2006.286.03:09:33.45#ibcon#read 3, iclass 11, count 0 2006.286.03:09:33.45#ibcon#about to read 4, iclass 11, count 0 2006.286.03:09:33.45#ibcon#read 4, iclass 11, count 0 2006.286.03:09:33.45#ibcon#about to read 5, iclass 11, count 0 2006.286.03:09:33.45#ibcon#read 5, iclass 11, count 0 2006.286.03:09:33.45#ibcon#about to read 6, iclass 11, count 0 2006.286.03:09:33.45#ibcon#read 6, iclass 11, count 0 2006.286.03:09:33.45#ibcon#end of sib2, iclass 11, count 0 2006.286.03:09:33.45#ibcon#*after write, iclass 11, count 0 2006.286.03:09:33.45#ibcon#*before return 0, iclass 11, count 0 2006.286.03:09:33.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:09:33.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:09:33.45#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.03:09:33.45#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.03:09:33.45$vck44/va=5,3 2006.286.03:09:33.45#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.03:09:33.45#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.03:09:33.45#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:33.45#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:09:33.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:09:33.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:09:33.51#ibcon#enter wrdev, iclass 13, count 2 2006.286.03:09:33.51#ibcon#first serial, iclass 13, count 2 2006.286.03:09:33.51#ibcon#enter sib2, iclass 13, count 2 2006.286.03:09:33.51#ibcon#flushed, iclass 13, count 2 2006.286.03:09:33.51#ibcon#about to write, iclass 13, count 2 2006.286.03:09:33.51#ibcon#wrote, iclass 13, count 2 2006.286.03:09:33.51#ibcon#about to read 3, iclass 13, count 2 2006.286.03:09:33.53#ibcon#read 3, iclass 13, count 2 2006.286.03:09:33.53#ibcon#about to read 4, iclass 13, count 2 2006.286.03:09:33.53#ibcon#read 4, iclass 13, count 2 2006.286.03:09:33.53#ibcon#about to read 5, iclass 13, count 2 2006.286.03:09:33.53#ibcon#read 5, iclass 13, count 2 2006.286.03:09:33.53#ibcon#about to read 6, iclass 13, count 2 2006.286.03:09:33.53#ibcon#read 6, iclass 13, count 2 2006.286.03:09:33.53#ibcon#end of sib2, iclass 13, count 2 2006.286.03:09:33.53#ibcon#*mode == 0, iclass 13, count 2 2006.286.03:09:33.53#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.03:09:33.53#ibcon#[25=AT05-03\r\n] 2006.286.03:09:33.53#ibcon#*before write, iclass 13, count 2 2006.286.03:09:33.53#ibcon#enter sib2, iclass 13, count 2 2006.286.03:09:33.53#ibcon#flushed, iclass 13, count 2 2006.286.03:09:33.53#ibcon#about to write, iclass 13, count 2 2006.286.03:09:33.53#ibcon#wrote, iclass 13, count 2 2006.286.03:09:33.53#ibcon#about to read 3, iclass 13, count 2 2006.286.03:09:33.56#ibcon#read 3, iclass 13, count 2 2006.286.03:09:33.56#ibcon#about to read 4, iclass 13, count 2 2006.286.03:09:33.56#ibcon#read 4, iclass 13, count 2 2006.286.03:09:33.56#ibcon#about to read 5, iclass 13, count 2 2006.286.03:09:33.56#ibcon#read 5, iclass 13, count 2 2006.286.03:09:33.56#ibcon#about to read 6, iclass 13, count 2 2006.286.03:09:33.56#ibcon#read 6, iclass 13, count 2 2006.286.03:09:33.56#ibcon#end of sib2, iclass 13, count 2 2006.286.03:09:33.56#ibcon#*after write, iclass 13, count 2 2006.286.03:09:33.56#ibcon#*before return 0, iclass 13, count 2 2006.286.03:09:33.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:09:33.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:09:33.56#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.03:09:33.56#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:33.56#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:09:33.68#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:09:33.68#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:09:33.68#ibcon#enter wrdev, iclass 13, count 0 2006.286.03:09:33.68#ibcon#first serial, iclass 13, count 0 2006.286.03:09:33.68#ibcon#enter sib2, iclass 13, count 0 2006.286.03:09:33.68#ibcon#flushed, iclass 13, count 0 2006.286.03:09:33.68#ibcon#about to write, iclass 13, count 0 2006.286.03:09:33.68#ibcon#wrote, iclass 13, count 0 2006.286.03:09:33.68#ibcon#about to read 3, iclass 13, count 0 2006.286.03:09:33.70#ibcon#read 3, iclass 13, count 0 2006.286.03:09:33.70#ibcon#about to read 4, iclass 13, count 0 2006.286.03:09:33.70#ibcon#read 4, iclass 13, count 0 2006.286.03:09:33.70#ibcon#about to read 5, iclass 13, count 0 2006.286.03:09:33.70#ibcon#read 5, iclass 13, count 0 2006.286.03:09:33.70#ibcon#about to read 6, iclass 13, count 0 2006.286.03:09:33.70#ibcon#read 6, iclass 13, count 0 2006.286.03:09:33.70#ibcon#end of sib2, iclass 13, count 0 2006.286.03:09:33.70#ibcon#*mode == 0, iclass 13, count 0 2006.286.03:09:33.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.03:09:33.70#ibcon#[25=USB\r\n] 2006.286.03:09:33.70#ibcon#*before write, iclass 13, count 0 2006.286.03:09:33.70#ibcon#enter sib2, iclass 13, count 0 2006.286.03:09:33.70#ibcon#flushed, iclass 13, count 0 2006.286.03:09:33.70#ibcon#about to write, iclass 13, count 0 2006.286.03:09:33.70#ibcon#wrote, iclass 13, count 0 2006.286.03:09:33.70#ibcon#about to read 3, iclass 13, count 0 2006.286.03:09:33.73#ibcon#read 3, iclass 13, count 0 2006.286.03:09:33.73#ibcon#about to read 4, iclass 13, count 0 2006.286.03:09:33.73#ibcon#read 4, iclass 13, count 0 2006.286.03:09:33.73#ibcon#about to read 5, iclass 13, count 0 2006.286.03:09:33.73#ibcon#read 5, iclass 13, count 0 2006.286.03:09:33.73#ibcon#about to read 6, iclass 13, count 0 2006.286.03:09:33.73#ibcon#read 6, iclass 13, count 0 2006.286.03:09:33.73#ibcon#end of sib2, iclass 13, count 0 2006.286.03:09:33.73#ibcon#*after write, iclass 13, count 0 2006.286.03:09:33.73#ibcon#*before return 0, iclass 13, count 0 2006.286.03:09:33.73#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:09:33.73#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:09:33.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.03:09:33.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.03:09:33.73$vck44/valo=6,814.99 2006.286.03:09:33.73#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.03:09:33.73#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.03:09:33.73#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:33.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:09:33.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:09:33.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:09:33.73#ibcon#enter wrdev, iclass 15, count 0 2006.286.03:09:33.73#ibcon#first serial, iclass 15, count 0 2006.286.03:09:33.73#ibcon#enter sib2, iclass 15, count 0 2006.286.03:09:33.73#ibcon#flushed, iclass 15, count 0 2006.286.03:09:33.73#ibcon#about to write, iclass 15, count 0 2006.286.03:09:33.73#ibcon#wrote, iclass 15, count 0 2006.286.03:09:33.73#ibcon#about to read 3, iclass 15, count 0 2006.286.03:09:33.75#ibcon#read 3, iclass 15, count 0 2006.286.03:09:33.75#ibcon#about to read 4, iclass 15, count 0 2006.286.03:09:33.75#ibcon#read 4, iclass 15, count 0 2006.286.03:09:33.75#ibcon#about to read 5, iclass 15, count 0 2006.286.03:09:33.75#ibcon#read 5, iclass 15, count 0 2006.286.03:09:33.75#ibcon#about to read 6, iclass 15, count 0 2006.286.03:09:33.75#ibcon#read 6, iclass 15, count 0 2006.286.03:09:33.75#ibcon#end of sib2, iclass 15, count 0 2006.286.03:09:33.75#ibcon#*mode == 0, iclass 15, count 0 2006.286.03:09:33.75#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.03:09:33.75#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.03:09:33.75#ibcon#*before write, iclass 15, count 0 2006.286.03:09:33.75#ibcon#enter sib2, iclass 15, count 0 2006.286.03:09:33.75#ibcon#flushed, iclass 15, count 0 2006.286.03:09:33.75#ibcon#about to write, iclass 15, count 0 2006.286.03:09:33.75#ibcon#wrote, iclass 15, count 0 2006.286.03:09:33.75#ibcon#about to read 3, iclass 15, count 0 2006.286.03:09:33.79#ibcon#read 3, iclass 15, count 0 2006.286.03:09:33.79#ibcon#about to read 4, iclass 15, count 0 2006.286.03:09:33.79#ibcon#read 4, iclass 15, count 0 2006.286.03:09:33.79#ibcon#about to read 5, iclass 15, count 0 2006.286.03:09:33.79#ibcon#read 5, iclass 15, count 0 2006.286.03:09:33.79#ibcon#about to read 6, iclass 15, count 0 2006.286.03:09:33.79#ibcon#read 6, iclass 15, count 0 2006.286.03:09:33.79#ibcon#end of sib2, iclass 15, count 0 2006.286.03:09:33.79#ibcon#*after write, iclass 15, count 0 2006.286.03:09:33.79#ibcon#*before return 0, iclass 15, count 0 2006.286.03:09:33.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:09:33.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:09:33.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.03:09:33.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.03:09:33.79$vck44/va=6,4 2006.286.03:09:33.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.03:09:33.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.03:09:33.92#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:33.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:09:33.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:09:33.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:09:33.92#ibcon#enter wrdev, iclass 17, count 2 2006.286.03:09:33.92#ibcon#first serial, iclass 17, count 2 2006.286.03:09:33.92#ibcon#enter sib2, iclass 17, count 2 2006.286.03:09:33.92#ibcon#flushed, iclass 17, count 2 2006.286.03:09:33.92#ibcon#about to write, iclass 17, count 2 2006.286.03:09:33.92#ibcon#wrote, iclass 17, count 2 2006.286.03:09:33.92#ibcon#about to read 3, iclass 17, count 2 2006.286.03:09:33.94#ibcon#read 3, iclass 17, count 2 2006.286.03:09:33.94#ibcon#about to read 4, iclass 17, count 2 2006.286.03:09:33.94#ibcon#read 4, iclass 17, count 2 2006.286.03:09:33.94#ibcon#about to read 5, iclass 17, count 2 2006.286.03:09:33.94#ibcon#read 5, iclass 17, count 2 2006.286.03:09:33.94#ibcon#about to read 6, iclass 17, count 2 2006.286.03:09:33.94#ibcon#read 6, iclass 17, count 2 2006.286.03:09:33.94#ibcon#end of sib2, iclass 17, count 2 2006.286.03:09:33.94#ibcon#*mode == 0, iclass 17, count 2 2006.286.03:09:33.94#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.03:09:33.94#ibcon#[25=AT06-04\r\n] 2006.286.03:09:33.94#ibcon#*before write, iclass 17, count 2 2006.286.03:09:33.94#ibcon#enter sib2, iclass 17, count 2 2006.286.03:09:33.94#ibcon#flushed, iclass 17, count 2 2006.286.03:09:33.94#ibcon#about to write, iclass 17, count 2 2006.286.03:09:33.94#ibcon#wrote, iclass 17, count 2 2006.286.03:09:33.94#ibcon#about to read 3, iclass 17, count 2 2006.286.03:09:33.97#ibcon#read 3, iclass 17, count 2 2006.286.03:09:33.97#ibcon#about to read 4, iclass 17, count 2 2006.286.03:09:33.97#ibcon#read 4, iclass 17, count 2 2006.286.03:09:33.97#ibcon#about to read 5, iclass 17, count 2 2006.286.03:09:33.97#ibcon#read 5, iclass 17, count 2 2006.286.03:09:33.97#ibcon#about to read 6, iclass 17, count 2 2006.286.03:09:33.97#ibcon#read 6, iclass 17, count 2 2006.286.03:09:33.97#ibcon#end of sib2, iclass 17, count 2 2006.286.03:09:33.97#ibcon#*after write, iclass 17, count 2 2006.286.03:09:33.97#ibcon#*before return 0, iclass 17, count 2 2006.286.03:09:33.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:09:33.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:09:33.97#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.03:09:33.97#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:33.97#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:09:34.09#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:09:34.09#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:09:34.09#ibcon#enter wrdev, iclass 17, count 0 2006.286.03:09:34.09#ibcon#first serial, iclass 17, count 0 2006.286.03:09:34.09#ibcon#enter sib2, iclass 17, count 0 2006.286.03:09:34.09#ibcon#flushed, iclass 17, count 0 2006.286.03:09:34.09#ibcon#about to write, iclass 17, count 0 2006.286.03:09:34.09#ibcon#wrote, iclass 17, count 0 2006.286.03:09:34.09#ibcon#about to read 3, iclass 17, count 0 2006.286.03:09:34.11#ibcon#read 3, iclass 17, count 0 2006.286.03:09:34.11#ibcon#about to read 4, iclass 17, count 0 2006.286.03:09:34.11#ibcon#read 4, iclass 17, count 0 2006.286.03:09:34.11#ibcon#about to read 5, iclass 17, count 0 2006.286.03:09:34.11#ibcon#read 5, iclass 17, count 0 2006.286.03:09:34.11#ibcon#about to read 6, iclass 17, count 0 2006.286.03:09:34.11#ibcon#read 6, iclass 17, count 0 2006.286.03:09:34.11#ibcon#end of sib2, iclass 17, count 0 2006.286.03:09:34.11#ibcon#*mode == 0, iclass 17, count 0 2006.286.03:09:34.11#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.03:09:34.11#ibcon#[25=USB\r\n] 2006.286.03:09:34.11#ibcon#*before write, iclass 17, count 0 2006.286.03:09:34.11#ibcon#enter sib2, iclass 17, count 0 2006.286.03:09:34.11#ibcon#flushed, iclass 17, count 0 2006.286.03:09:34.11#ibcon#about to write, iclass 17, count 0 2006.286.03:09:34.11#ibcon#wrote, iclass 17, count 0 2006.286.03:09:34.11#ibcon#about to read 3, iclass 17, count 0 2006.286.03:09:34.14#ibcon#read 3, iclass 17, count 0 2006.286.03:09:34.14#ibcon#about to read 4, iclass 17, count 0 2006.286.03:09:34.14#ibcon#read 4, iclass 17, count 0 2006.286.03:09:34.14#ibcon#about to read 5, iclass 17, count 0 2006.286.03:09:34.14#ibcon#read 5, iclass 17, count 0 2006.286.03:09:34.14#ibcon#about to read 6, iclass 17, count 0 2006.286.03:09:34.14#ibcon#read 6, iclass 17, count 0 2006.286.03:09:34.14#ibcon#end of sib2, iclass 17, count 0 2006.286.03:09:34.14#ibcon#*after write, iclass 17, count 0 2006.286.03:09:34.14#ibcon#*before return 0, iclass 17, count 0 2006.286.03:09:34.14#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:09:34.14#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:09:34.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.03:09:34.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.03:09:34.14$vck44/valo=7,864.99 2006.286.03:09:34.14#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.03:09:34.14#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.03:09:34.14#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:34.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:09:34.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:09:34.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:09:34.14#ibcon#enter wrdev, iclass 19, count 0 2006.286.03:09:34.14#ibcon#first serial, iclass 19, count 0 2006.286.03:09:34.14#ibcon#enter sib2, iclass 19, count 0 2006.286.03:09:34.14#ibcon#flushed, iclass 19, count 0 2006.286.03:09:34.14#ibcon#about to write, iclass 19, count 0 2006.286.03:09:34.14#ibcon#wrote, iclass 19, count 0 2006.286.03:09:34.14#ibcon#about to read 3, iclass 19, count 0 2006.286.03:09:34.16#ibcon#read 3, iclass 19, count 0 2006.286.03:09:34.16#ibcon#about to read 4, iclass 19, count 0 2006.286.03:09:34.16#ibcon#read 4, iclass 19, count 0 2006.286.03:09:34.16#ibcon#about to read 5, iclass 19, count 0 2006.286.03:09:34.16#ibcon#read 5, iclass 19, count 0 2006.286.03:09:34.16#ibcon#about to read 6, iclass 19, count 0 2006.286.03:09:34.16#ibcon#read 6, iclass 19, count 0 2006.286.03:09:34.16#ibcon#end of sib2, iclass 19, count 0 2006.286.03:09:34.16#ibcon#*mode == 0, iclass 19, count 0 2006.286.03:09:34.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.03:09:34.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.03:09:34.16#ibcon#*before write, iclass 19, count 0 2006.286.03:09:34.16#ibcon#enter sib2, iclass 19, count 0 2006.286.03:09:34.16#ibcon#flushed, iclass 19, count 0 2006.286.03:09:34.16#ibcon#about to write, iclass 19, count 0 2006.286.03:09:34.16#ibcon#wrote, iclass 19, count 0 2006.286.03:09:34.16#ibcon#about to read 3, iclass 19, count 0 2006.286.03:09:34.20#ibcon#read 3, iclass 19, count 0 2006.286.03:09:34.20#ibcon#about to read 4, iclass 19, count 0 2006.286.03:09:34.20#ibcon#read 4, iclass 19, count 0 2006.286.03:09:34.20#ibcon#about to read 5, iclass 19, count 0 2006.286.03:09:34.20#ibcon#read 5, iclass 19, count 0 2006.286.03:09:34.20#ibcon#about to read 6, iclass 19, count 0 2006.286.03:09:34.20#ibcon#read 6, iclass 19, count 0 2006.286.03:09:34.20#ibcon#end of sib2, iclass 19, count 0 2006.286.03:09:34.20#ibcon#*after write, iclass 19, count 0 2006.286.03:09:34.20#ibcon#*before return 0, iclass 19, count 0 2006.286.03:09:34.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:09:34.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:09:34.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.03:09:34.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.03:09:34.20$vck44/va=7,4 2006.286.03:09:34.20#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.03:09:34.20#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.03:09:34.20#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:34.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:09:34.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:09:34.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:09:34.26#ibcon#enter wrdev, iclass 21, count 2 2006.286.03:09:34.26#ibcon#first serial, iclass 21, count 2 2006.286.03:09:34.26#ibcon#enter sib2, iclass 21, count 2 2006.286.03:09:34.26#ibcon#flushed, iclass 21, count 2 2006.286.03:09:34.26#ibcon#about to write, iclass 21, count 2 2006.286.03:09:34.26#ibcon#wrote, iclass 21, count 2 2006.286.03:09:34.26#ibcon#about to read 3, iclass 21, count 2 2006.286.03:09:34.28#ibcon#read 3, iclass 21, count 2 2006.286.03:09:34.28#ibcon#about to read 4, iclass 21, count 2 2006.286.03:09:34.28#ibcon#read 4, iclass 21, count 2 2006.286.03:09:34.28#ibcon#about to read 5, iclass 21, count 2 2006.286.03:09:34.28#ibcon#read 5, iclass 21, count 2 2006.286.03:09:34.28#ibcon#about to read 6, iclass 21, count 2 2006.286.03:09:34.28#ibcon#read 6, iclass 21, count 2 2006.286.03:09:34.28#ibcon#end of sib2, iclass 21, count 2 2006.286.03:09:34.28#ibcon#*mode == 0, iclass 21, count 2 2006.286.03:09:34.28#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.03:09:34.28#ibcon#[25=AT07-04\r\n] 2006.286.03:09:34.28#ibcon#*before write, iclass 21, count 2 2006.286.03:09:34.28#ibcon#enter sib2, iclass 21, count 2 2006.286.03:09:34.28#ibcon#flushed, iclass 21, count 2 2006.286.03:09:34.28#ibcon#about to write, iclass 21, count 2 2006.286.03:09:34.28#ibcon#wrote, iclass 21, count 2 2006.286.03:09:34.28#ibcon#about to read 3, iclass 21, count 2 2006.286.03:09:34.31#ibcon#read 3, iclass 21, count 2 2006.286.03:09:34.31#ibcon#about to read 4, iclass 21, count 2 2006.286.03:09:34.31#ibcon#read 4, iclass 21, count 2 2006.286.03:09:34.31#ibcon#about to read 5, iclass 21, count 2 2006.286.03:09:34.31#ibcon#read 5, iclass 21, count 2 2006.286.03:09:34.31#ibcon#about to read 6, iclass 21, count 2 2006.286.03:09:34.31#ibcon#read 6, iclass 21, count 2 2006.286.03:09:34.31#ibcon#end of sib2, iclass 21, count 2 2006.286.03:09:34.31#ibcon#*after write, iclass 21, count 2 2006.286.03:09:34.31#ibcon#*before return 0, iclass 21, count 2 2006.286.03:09:34.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:09:34.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:09:34.31#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.03:09:34.31#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:34.31#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:09:34.43#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:09:34.43#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:09:34.43#ibcon#enter wrdev, iclass 21, count 0 2006.286.03:09:34.43#ibcon#first serial, iclass 21, count 0 2006.286.03:09:34.43#ibcon#enter sib2, iclass 21, count 0 2006.286.03:09:34.43#ibcon#flushed, iclass 21, count 0 2006.286.03:09:34.43#ibcon#about to write, iclass 21, count 0 2006.286.03:09:34.43#ibcon#wrote, iclass 21, count 0 2006.286.03:09:34.43#ibcon#about to read 3, iclass 21, count 0 2006.286.03:09:34.45#ibcon#read 3, iclass 21, count 0 2006.286.03:09:34.45#ibcon#about to read 4, iclass 21, count 0 2006.286.03:09:34.45#ibcon#read 4, iclass 21, count 0 2006.286.03:09:34.45#ibcon#about to read 5, iclass 21, count 0 2006.286.03:09:34.45#ibcon#read 5, iclass 21, count 0 2006.286.03:09:34.45#ibcon#about to read 6, iclass 21, count 0 2006.286.03:09:34.45#ibcon#read 6, iclass 21, count 0 2006.286.03:09:34.45#ibcon#end of sib2, iclass 21, count 0 2006.286.03:09:34.45#ibcon#*mode == 0, iclass 21, count 0 2006.286.03:09:34.45#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.03:09:34.45#ibcon#[25=USB\r\n] 2006.286.03:09:34.45#ibcon#*before write, iclass 21, count 0 2006.286.03:09:34.45#ibcon#enter sib2, iclass 21, count 0 2006.286.03:09:34.45#ibcon#flushed, iclass 21, count 0 2006.286.03:09:34.45#ibcon#about to write, iclass 21, count 0 2006.286.03:09:34.45#ibcon#wrote, iclass 21, count 0 2006.286.03:09:34.45#ibcon#about to read 3, iclass 21, count 0 2006.286.03:09:34.48#ibcon#read 3, iclass 21, count 0 2006.286.03:09:34.48#ibcon#about to read 4, iclass 21, count 0 2006.286.03:09:34.48#ibcon#read 4, iclass 21, count 0 2006.286.03:09:34.48#ibcon#about to read 5, iclass 21, count 0 2006.286.03:09:34.48#ibcon#read 5, iclass 21, count 0 2006.286.03:09:34.48#ibcon#about to read 6, iclass 21, count 0 2006.286.03:09:34.48#ibcon#read 6, iclass 21, count 0 2006.286.03:09:34.48#ibcon#end of sib2, iclass 21, count 0 2006.286.03:09:34.48#ibcon#*after write, iclass 21, count 0 2006.286.03:09:34.48#ibcon#*before return 0, iclass 21, count 0 2006.286.03:09:34.48#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:09:34.48#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:09:34.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.03:09:34.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.03:09:34.48$vck44/valo=8,884.99 2006.286.03:09:34.48#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.03:09:34.48#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.03:09:34.48#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:34.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:09:34.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:09:34.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:09:34.48#ibcon#enter wrdev, iclass 23, count 0 2006.286.03:09:34.48#ibcon#first serial, iclass 23, count 0 2006.286.03:09:34.48#ibcon#enter sib2, iclass 23, count 0 2006.286.03:09:34.48#ibcon#flushed, iclass 23, count 0 2006.286.03:09:34.48#ibcon#about to write, iclass 23, count 0 2006.286.03:09:34.48#ibcon#wrote, iclass 23, count 0 2006.286.03:09:34.48#ibcon#about to read 3, iclass 23, count 0 2006.286.03:09:34.50#ibcon#read 3, iclass 23, count 0 2006.286.03:09:34.50#ibcon#about to read 4, iclass 23, count 0 2006.286.03:09:34.50#ibcon#read 4, iclass 23, count 0 2006.286.03:09:34.50#ibcon#about to read 5, iclass 23, count 0 2006.286.03:09:34.50#ibcon#read 5, iclass 23, count 0 2006.286.03:09:34.50#ibcon#about to read 6, iclass 23, count 0 2006.286.03:09:34.50#ibcon#read 6, iclass 23, count 0 2006.286.03:09:34.50#ibcon#end of sib2, iclass 23, count 0 2006.286.03:09:34.50#ibcon#*mode == 0, iclass 23, count 0 2006.286.03:09:34.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.03:09:34.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.03:09:34.50#ibcon#*before write, iclass 23, count 0 2006.286.03:09:34.50#ibcon#enter sib2, iclass 23, count 0 2006.286.03:09:34.50#ibcon#flushed, iclass 23, count 0 2006.286.03:09:34.50#ibcon#about to write, iclass 23, count 0 2006.286.03:09:34.50#ibcon#wrote, iclass 23, count 0 2006.286.03:09:34.50#ibcon#about to read 3, iclass 23, count 0 2006.286.03:09:34.54#ibcon#read 3, iclass 23, count 0 2006.286.03:09:34.54#ibcon#about to read 4, iclass 23, count 0 2006.286.03:09:34.54#ibcon#read 4, iclass 23, count 0 2006.286.03:09:34.54#ibcon#about to read 5, iclass 23, count 0 2006.286.03:09:34.54#ibcon#read 5, iclass 23, count 0 2006.286.03:09:34.54#ibcon#about to read 6, iclass 23, count 0 2006.286.03:09:34.54#ibcon#read 6, iclass 23, count 0 2006.286.03:09:34.54#ibcon#end of sib2, iclass 23, count 0 2006.286.03:09:34.54#ibcon#*after write, iclass 23, count 0 2006.286.03:09:34.54#ibcon#*before return 0, iclass 23, count 0 2006.286.03:09:34.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:09:34.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:09:34.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.03:09:34.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.03:09:34.54$vck44/va=8,3 2006.286.03:09:34.54#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.03:09:34.54#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.03:09:34.54#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:34.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.03:09:34.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.03:09:34.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.03:09:34.60#ibcon#enter wrdev, iclass 25, count 2 2006.286.03:09:34.60#ibcon#first serial, iclass 25, count 2 2006.286.03:09:34.60#ibcon#enter sib2, iclass 25, count 2 2006.286.03:09:34.60#ibcon#flushed, iclass 25, count 2 2006.286.03:09:34.60#ibcon#about to write, iclass 25, count 2 2006.286.03:09:34.60#ibcon#wrote, iclass 25, count 2 2006.286.03:09:34.60#ibcon#about to read 3, iclass 25, count 2 2006.286.03:09:34.62#ibcon#read 3, iclass 25, count 2 2006.286.03:09:34.62#ibcon#about to read 4, iclass 25, count 2 2006.286.03:09:34.62#ibcon#read 4, iclass 25, count 2 2006.286.03:09:34.62#ibcon#about to read 5, iclass 25, count 2 2006.286.03:09:34.62#ibcon#read 5, iclass 25, count 2 2006.286.03:09:34.62#ibcon#about to read 6, iclass 25, count 2 2006.286.03:09:34.62#ibcon#read 6, iclass 25, count 2 2006.286.03:09:34.62#ibcon#end of sib2, iclass 25, count 2 2006.286.03:09:34.62#ibcon#*mode == 0, iclass 25, count 2 2006.286.03:09:34.62#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.03:09:34.62#ibcon#[25=AT08-03\r\n] 2006.286.03:09:34.62#ibcon#*before write, iclass 25, count 2 2006.286.03:09:34.62#ibcon#enter sib2, iclass 25, count 2 2006.286.03:09:34.62#ibcon#flushed, iclass 25, count 2 2006.286.03:09:34.62#ibcon#about to write, iclass 25, count 2 2006.286.03:09:34.62#ibcon#wrote, iclass 25, count 2 2006.286.03:09:34.62#ibcon#about to read 3, iclass 25, count 2 2006.286.03:09:34.65#ibcon#read 3, iclass 25, count 2 2006.286.03:09:34.65#ibcon#about to read 4, iclass 25, count 2 2006.286.03:09:34.65#ibcon#read 4, iclass 25, count 2 2006.286.03:09:34.65#ibcon#about to read 5, iclass 25, count 2 2006.286.03:09:34.65#ibcon#read 5, iclass 25, count 2 2006.286.03:09:34.65#ibcon#about to read 6, iclass 25, count 2 2006.286.03:09:34.65#ibcon#read 6, iclass 25, count 2 2006.286.03:09:34.65#ibcon#end of sib2, iclass 25, count 2 2006.286.03:09:34.65#ibcon#*after write, iclass 25, count 2 2006.286.03:09:34.65#ibcon#*before return 0, iclass 25, count 2 2006.286.03:09:34.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.03:09:34.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.03:09:34.65#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.03:09:34.65#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:34.65#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.03:09:34.77#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.03:09:34.77#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.03:09:34.77#ibcon#enter wrdev, iclass 25, count 0 2006.286.03:09:34.77#ibcon#first serial, iclass 25, count 0 2006.286.03:09:34.77#ibcon#enter sib2, iclass 25, count 0 2006.286.03:09:34.77#ibcon#flushed, iclass 25, count 0 2006.286.03:09:34.77#ibcon#about to write, iclass 25, count 0 2006.286.03:09:34.77#ibcon#wrote, iclass 25, count 0 2006.286.03:09:34.77#ibcon#about to read 3, iclass 25, count 0 2006.286.03:09:34.79#ibcon#read 3, iclass 25, count 0 2006.286.03:09:34.79#ibcon#about to read 4, iclass 25, count 0 2006.286.03:09:34.79#ibcon#read 4, iclass 25, count 0 2006.286.03:09:34.79#ibcon#about to read 5, iclass 25, count 0 2006.286.03:09:34.79#ibcon#read 5, iclass 25, count 0 2006.286.03:09:34.79#ibcon#about to read 6, iclass 25, count 0 2006.286.03:09:34.79#ibcon#read 6, iclass 25, count 0 2006.286.03:09:34.79#ibcon#end of sib2, iclass 25, count 0 2006.286.03:09:34.79#ibcon#*mode == 0, iclass 25, count 0 2006.286.03:09:34.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.03:09:34.79#ibcon#[25=USB\r\n] 2006.286.03:09:34.79#ibcon#*before write, iclass 25, count 0 2006.286.03:09:34.79#ibcon#enter sib2, iclass 25, count 0 2006.286.03:09:34.79#ibcon#flushed, iclass 25, count 0 2006.286.03:09:34.79#ibcon#about to write, iclass 25, count 0 2006.286.03:09:34.79#ibcon#wrote, iclass 25, count 0 2006.286.03:09:34.79#ibcon#about to read 3, iclass 25, count 0 2006.286.03:09:34.82#ibcon#read 3, iclass 25, count 0 2006.286.03:09:34.82#ibcon#about to read 4, iclass 25, count 0 2006.286.03:09:34.82#ibcon#read 4, iclass 25, count 0 2006.286.03:09:34.82#ibcon#about to read 5, iclass 25, count 0 2006.286.03:09:34.82#ibcon#read 5, iclass 25, count 0 2006.286.03:09:34.82#ibcon#about to read 6, iclass 25, count 0 2006.286.03:09:34.82#ibcon#read 6, iclass 25, count 0 2006.286.03:09:34.82#ibcon#end of sib2, iclass 25, count 0 2006.286.03:09:34.82#ibcon#*after write, iclass 25, count 0 2006.286.03:09:34.82#ibcon#*before return 0, iclass 25, count 0 2006.286.03:09:34.82#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.03:09:34.82#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.03:09:34.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.03:09:34.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.03:09:34.82$vck44/vblo=1,629.99 2006.286.03:09:34.82#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.03:09:34.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.03:09:34.82#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:34.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:09:34.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:09:34.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:09:34.82#ibcon#enter wrdev, iclass 27, count 0 2006.286.03:09:34.82#ibcon#first serial, iclass 27, count 0 2006.286.03:09:34.82#ibcon#enter sib2, iclass 27, count 0 2006.286.03:09:34.82#ibcon#flushed, iclass 27, count 0 2006.286.03:09:34.82#ibcon#about to write, iclass 27, count 0 2006.286.03:09:34.82#ibcon#wrote, iclass 27, count 0 2006.286.03:09:34.82#ibcon#about to read 3, iclass 27, count 0 2006.286.03:09:34.84#ibcon#read 3, iclass 27, count 0 2006.286.03:09:34.91#ibcon#about to read 4, iclass 27, count 0 2006.286.03:09:34.91#ibcon#read 4, iclass 27, count 0 2006.286.03:09:34.91#ibcon#about to read 5, iclass 27, count 0 2006.286.03:09:34.91#ibcon#read 5, iclass 27, count 0 2006.286.03:09:34.91#ibcon#about to read 6, iclass 27, count 0 2006.286.03:09:34.91#ibcon#read 6, iclass 27, count 0 2006.286.03:09:34.91#ibcon#end of sib2, iclass 27, count 0 2006.286.03:09:34.91#ibcon#*mode == 0, iclass 27, count 0 2006.286.03:09:34.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.03:09:34.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.03:09:34.91#ibcon#*before write, iclass 27, count 0 2006.286.03:09:34.91#ibcon#enter sib2, iclass 27, count 0 2006.286.03:09:34.91#ibcon#flushed, iclass 27, count 0 2006.286.03:09:34.91#ibcon#about to write, iclass 27, count 0 2006.286.03:09:34.91#ibcon#wrote, iclass 27, count 0 2006.286.03:09:34.91#ibcon#about to read 3, iclass 27, count 0 2006.286.03:09:34.96#ibcon#read 3, iclass 27, count 0 2006.286.03:09:34.96#ibcon#about to read 4, iclass 27, count 0 2006.286.03:09:34.96#ibcon#read 4, iclass 27, count 0 2006.286.03:09:34.96#ibcon#about to read 5, iclass 27, count 0 2006.286.03:09:34.96#ibcon#read 5, iclass 27, count 0 2006.286.03:09:34.96#ibcon#about to read 6, iclass 27, count 0 2006.286.03:09:34.96#ibcon#read 6, iclass 27, count 0 2006.286.03:09:34.96#ibcon#end of sib2, iclass 27, count 0 2006.286.03:09:34.96#ibcon#*after write, iclass 27, count 0 2006.286.03:09:34.96#ibcon#*before return 0, iclass 27, count 0 2006.286.03:09:34.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:09:34.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:09:34.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.03:09:34.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.03:09:34.96$vck44/vb=1,4 2006.286.03:09:34.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.03:09:34.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.03:09:34.96#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:34.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:09:34.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:09:34.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:09:34.96#ibcon#enter wrdev, iclass 29, count 2 2006.286.03:09:34.96#ibcon#first serial, iclass 29, count 2 2006.286.03:09:34.96#ibcon#enter sib2, iclass 29, count 2 2006.286.03:09:34.96#ibcon#flushed, iclass 29, count 2 2006.286.03:09:34.96#ibcon#about to write, iclass 29, count 2 2006.286.03:09:34.96#ibcon#wrote, iclass 29, count 2 2006.286.03:09:34.96#ibcon#about to read 3, iclass 29, count 2 2006.286.03:09:34.98#ibcon#read 3, iclass 29, count 2 2006.286.03:09:34.98#ibcon#about to read 4, iclass 29, count 2 2006.286.03:09:34.98#ibcon#read 4, iclass 29, count 2 2006.286.03:09:34.98#ibcon#about to read 5, iclass 29, count 2 2006.286.03:09:34.98#ibcon#read 5, iclass 29, count 2 2006.286.03:09:34.98#ibcon#about to read 6, iclass 29, count 2 2006.286.03:09:34.98#ibcon#read 6, iclass 29, count 2 2006.286.03:09:34.98#ibcon#end of sib2, iclass 29, count 2 2006.286.03:09:34.98#ibcon#*mode == 0, iclass 29, count 2 2006.286.03:09:34.98#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.03:09:34.98#ibcon#[27=AT01-04\r\n] 2006.286.03:09:34.98#ibcon#*before write, iclass 29, count 2 2006.286.03:09:34.98#ibcon#enter sib2, iclass 29, count 2 2006.286.03:09:34.98#ibcon#flushed, iclass 29, count 2 2006.286.03:09:34.98#ibcon#about to write, iclass 29, count 2 2006.286.03:09:34.98#ibcon#wrote, iclass 29, count 2 2006.286.03:09:34.98#ibcon#about to read 3, iclass 29, count 2 2006.286.03:09:35.01#ibcon#read 3, iclass 29, count 2 2006.286.03:09:35.01#ibcon#about to read 4, iclass 29, count 2 2006.286.03:09:35.01#ibcon#read 4, iclass 29, count 2 2006.286.03:09:35.01#ibcon#about to read 5, iclass 29, count 2 2006.286.03:09:35.01#ibcon#read 5, iclass 29, count 2 2006.286.03:09:35.01#ibcon#about to read 6, iclass 29, count 2 2006.286.03:09:35.01#ibcon#read 6, iclass 29, count 2 2006.286.03:09:35.01#ibcon#end of sib2, iclass 29, count 2 2006.286.03:09:35.01#ibcon#*after write, iclass 29, count 2 2006.286.03:09:35.01#ibcon#*before return 0, iclass 29, count 2 2006.286.03:09:35.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:09:35.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:09:35.01#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.03:09:35.01#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:35.01#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:09:35.13#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:09:35.13#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:09:35.13#ibcon#enter wrdev, iclass 29, count 0 2006.286.03:09:35.13#ibcon#first serial, iclass 29, count 0 2006.286.03:09:35.13#ibcon#enter sib2, iclass 29, count 0 2006.286.03:09:35.13#ibcon#flushed, iclass 29, count 0 2006.286.03:09:35.13#ibcon#about to write, iclass 29, count 0 2006.286.03:09:35.13#ibcon#wrote, iclass 29, count 0 2006.286.03:09:35.13#ibcon#about to read 3, iclass 29, count 0 2006.286.03:09:35.15#ibcon#read 3, iclass 29, count 0 2006.286.03:09:35.15#ibcon#about to read 4, iclass 29, count 0 2006.286.03:09:35.15#ibcon#read 4, iclass 29, count 0 2006.286.03:09:35.15#ibcon#about to read 5, iclass 29, count 0 2006.286.03:09:35.15#ibcon#read 5, iclass 29, count 0 2006.286.03:09:35.15#ibcon#about to read 6, iclass 29, count 0 2006.286.03:09:35.15#ibcon#read 6, iclass 29, count 0 2006.286.03:09:35.15#ibcon#end of sib2, iclass 29, count 0 2006.286.03:09:35.15#ibcon#*mode == 0, iclass 29, count 0 2006.286.03:09:35.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.03:09:35.15#ibcon#[27=USB\r\n] 2006.286.03:09:35.15#ibcon#*before write, iclass 29, count 0 2006.286.03:09:35.15#ibcon#enter sib2, iclass 29, count 0 2006.286.03:09:35.15#ibcon#flushed, iclass 29, count 0 2006.286.03:09:35.15#ibcon#about to write, iclass 29, count 0 2006.286.03:09:35.15#ibcon#wrote, iclass 29, count 0 2006.286.03:09:35.15#ibcon#about to read 3, iclass 29, count 0 2006.286.03:09:35.18#ibcon#read 3, iclass 29, count 0 2006.286.03:09:35.18#ibcon#about to read 4, iclass 29, count 0 2006.286.03:09:35.18#ibcon#read 4, iclass 29, count 0 2006.286.03:09:35.18#ibcon#about to read 5, iclass 29, count 0 2006.286.03:09:35.18#ibcon#read 5, iclass 29, count 0 2006.286.03:09:35.18#ibcon#about to read 6, iclass 29, count 0 2006.286.03:09:35.18#ibcon#read 6, iclass 29, count 0 2006.286.03:09:35.18#ibcon#end of sib2, iclass 29, count 0 2006.286.03:09:35.18#ibcon#*after write, iclass 29, count 0 2006.286.03:09:35.18#ibcon#*before return 0, iclass 29, count 0 2006.286.03:09:35.18#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:09:35.18#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:09:35.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.03:09:35.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.03:09:35.18$vck44/vblo=2,634.99 2006.286.03:09:35.18#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.03:09:35.18#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.03:09:35.18#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:35.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:09:35.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:09:35.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:09:35.18#ibcon#enter wrdev, iclass 31, count 0 2006.286.03:09:35.18#ibcon#first serial, iclass 31, count 0 2006.286.03:09:35.18#ibcon#enter sib2, iclass 31, count 0 2006.286.03:09:35.18#ibcon#flushed, iclass 31, count 0 2006.286.03:09:35.18#ibcon#about to write, iclass 31, count 0 2006.286.03:09:35.18#ibcon#wrote, iclass 31, count 0 2006.286.03:09:35.18#ibcon#about to read 3, iclass 31, count 0 2006.286.03:09:35.20#ibcon#read 3, iclass 31, count 0 2006.286.03:09:35.20#ibcon#about to read 4, iclass 31, count 0 2006.286.03:09:35.20#ibcon#read 4, iclass 31, count 0 2006.286.03:09:35.20#ibcon#about to read 5, iclass 31, count 0 2006.286.03:09:35.20#ibcon#read 5, iclass 31, count 0 2006.286.03:09:35.20#ibcon#about to read 6, iclass 31, count 0 2006.286.03:09:35.20#ibcon#read 6, iclass 31, count 0 2006.286.03:09:35.20#ibcon#end of sib2, iclass 31, count 0 2006.286.03:09:35.20#ibcon#*mode == 0, iclass 31, count 0 2006.286.03:09:35.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.03:09:35.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.03:09:35.20#ibcon#*before write, iclass 31, count 0 2006.286.03:09:35.20#ibcon#enter sib2, iclass 31, count 0 2006.286.03:09:35.20#ibcon#flushed, iclass 31, count 0 2006.286.03:09:35.20#ibcon#about to write, iclass 31, count 0 2006.286.03:09:35.20#ibcon#wrote, iclass 31, count 0 2006.286.03:09:35.20#ibcon#about to read 3, iclass 31, count 0 2006.286.03:09:35.24#ibcon#read 3, iclass 31, count 0 2006.286.03:09:35.24#ibcon#about to read 4, iclass 31, count 0 2006.286.03:09:35.24#ibcon#read 4, iclass 31, count 0 2006.286.03:09:35.24#ibcon#about to read 5, iclass 31, count 0 2006.286.03:09:35.24#ibcon#read 5, iclass 31, count 0 2006.286.03:09:35.24#ibcon#about to read 6, iclass 31, count 0 2006.286.03:09:35.24#ibcon#read 6, iclass 31, count 0 2006.286.03:09:35.24#ibcon#end of sib2, iclass 31, count 0 2006.286.03:09:35.24#ibcon#*after write, iclass 31, count 0 2006.286.03:09:35.24#ibcon#*before return 0, iclass 31, count 0 2006.286.03:09:35.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:09:35.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:09:35.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.03:09:35.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.03:09:35.24$vck44/vb=2,5 2006.286.03:09:35.24#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.03:09:35.24#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.03:09:35.24#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:35.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:09:35.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:09:35.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:09:35.30#ibcon#enter wrdev, iclass 33, count 2 2006.286.03:09:35.30#ibcon#first serial, iclass 33, count 2 2006.286.03:09:35.30#ibcon#enter sib2, iclass 33, count 2 2006.286.03:09:35.30#ibcon#flushed, iclass 33, count 2 2006.286.03:09:35.30#ibcon#about to write, iclass 33, count 2 2006.286.03:09:35.30#ibcon#wrote, iclass 33, count 2 2006.286.03:09:35.30#ibcon#about to read 3, iclass 33, count 2 2006.286.03:09:35.32#ibcon#read 3, iclass 33, count 2 2006.286.03:09:35.32#ibcon#about to read 4, iclass 33, count 2 2006.286.03:09:35.32#ibcon#read 4, iclass 33, count 2 2006.286.03:09:35.32#ibcon#about to read 5, iclass 33, count 2 2006.286.03:09:35.32#ibcon#read 5, iclass 33, count 2 2006.286.03:09:35.32#ibcon#about to read 6, iclass 33, count 2 2006.286.03:09:35.32#ibcon#read 6, iclass 33, count 2 2006.286.03:09:35.32#ibcon#end of sib2, iclass 33, count 2 2006.286.03:09:35.32#ibcon#*mode == 0, iclass 33, count 2 2006.286.03:09:35.32#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.03:09:35.32#ibcon#[27=AT02-05\r\n] 2006.286.03:09:35.32#ibcon#*before write, iclass 33, count 2 2006.286.03:09:35.32#ibcon#enter sib2, iclass 33, count 2 2006.286.03:09:35.32#ibcon#flushed, iclass 33, count 2 2006.286.03:09:35.32#ibcon#about to write, iclass 33, count 2 2006.286.03:09:35.32#ibcon#wrote, iclass 33, count 2 2006.286.03:09:35.32#ibcon#about to read 3, iclass 33, count 2 2006.286.03:09:35.35#ibcon#read 3, iclass 33, count 2 2006.286.03:09:35.35#ibcon#about to read 4, iclass 33, count 2 2006.286.03:09:35.35#ibcon#read 4, iclass 33, count 2 2006.286.03:09:35.35#ibcon#about to read 5, iclass 33, count 2 2006.286.03:09:35.35#ibcon#read 5, iclass 33, count 2 2006.286.03:09:35.35#ibcon#about to read 6, iclass 33, count 2 2006.286.03:09:35.35#ibcon#read 6, iclass 33, count 2 2006.286.03:09:35.35#ibcon#end of sib2, iclass 33, count 2 2006.286.03:09:35.35#ibcon#*after write, iclass 33, count 2 2006.286.03:09:35.35#ibcon#*before return 0, iclass 33, count 2 2006.286.03:09:35.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:09:35.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:09:35.35#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.03:09:35.35#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:35.35#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:09:35.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:09:35.47#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:09:35.47#ibcon#enter wrdev, iclass 33, count 0 2006.286.03:09:35.47#ibcon#first serial, iclass 33, count 0 2006.286.03:09:35.47#ibcon#enter sib2, iclass 33, count 0 2006.286.03:09:35.47#ibcon#flushed, iclass 33, count 0 2006.286.03:09:35.47#ibcon#about to write, iclass 33, count 0 2006.286.03:09:35.47#ibcon#wrote, iclass 33, count 0 2006.286.03:09:35.47#ibcon#about to read 3, iclass 33, count 0 2006.286.03:09:35.49#ibcon#read 3, iclass 33, count 0 2006.286.03:09:35.49#ibcon#about to read 4, iclass 33, count 0 2006.286.03:09:35.49#ibcon#read 4, iclass 33, count 0 2006.286.03:09:35.49#ibcon#about to read 5, iclass 33, count 0 2006.286.03:09:35.49#ibcon#read 5, iclass 33, count 0 2006.286.03:09:35.49#ibcon#about to read 6, iclass 33, count 0 2006.286.03:09:35.49#ibcon#read 6, iclass 33, count 0 2006.286.03:09:35.49#ibcon#end of sib2, iclass 33, count 0 2006.286.03:09:35.49#ibcon#*mode == 0, iclass 33, count 0 2006.286.03:09:35.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.03:09:35.49#ibcon#[27=USB\r\n] 2006.286.03:09:35.49#ibcon#*before write, iclass 33, count 0 2006.286.03:09:35.49#ibcon#enter sib2, iclass 33, count 0 2006.286.03:09:35.49#ibcon#flushed, iclass 33, count 0 2006.286.03:09:35.49#ibcon#about to write, iclass 33, count 0 2006.286.03:09:35.49#ibcon#wrote, iclass 33, count 0 2006.286.03:09:35.49#ibcon#about to read 3, iclass 33, count 0 2006.286.03:09:35.52#ibcon#read 3, iclass 33, count 0 2006.286.03:09:35.52#ibcon#about to read 4, iclass 33, count 0 2006.286.03:09:35.52#ibcon#read 4, iclass 33, count 0 2006.286.03:09:35.52#ibcon#about to read 5, iclass 33, count 0 2006.286.03:09:35.52#ibcon#read 5, iclass 33, count 0 2006.286.03:09:35.52#ibcon#about to read 6, iclass 33, count 0 2006.286.03:09:35.52#ibcon#read 6, iclass 33, count 0 2006.286.03:09:35.52#ibcon#end of sib2, iclass 33, count 0 2006.286.03:09:35.52#ibcon#*after write, iclass 33, count 0 2006.286.03:09:35.52#ibcon#*before return 0, iclass 33, count 0 2006.286.03:09:35.52#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:09:35.52#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:09:35.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.03:09:35.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.03:09:35.52$vck44/vblo=3,649.99 2006.286.03:09:35.52#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.03:09:35.52#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.03:09:35.52#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:35.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:09:35.52#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:09:35.52#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:09:35.52#ibcon#enter wrdev, iclass 35, count 0 2006.286.03:09:35.52#ibcon#first serial, iclass 35, count 0 2006.286.03:09:35.52#ibcon#enter sib2, iclass 35, count 0 2006.286.03:09:35.52#ibcon#flushed, iclass 35, count 0 2006.286.03:09:35.52#ibcon#about to write, iclass 35, count 0 2006.286.03:09:35.52#ibcon#wrote, iclass 35, count 0 2006.286.03:09:35.52#ibcon#about to read 3, iclass 35, count 0 2006.286.03:09:35.54#ibcon#read 3, iclass 35, count 0 2006.286.03:09:35.54#ibcon#about to read 4, iclass 35, count 0 2006.286.03:09:35.54#ibcon#read 4, iclass 35, count 0 2006.286.03:09:35.54#ibcon#about to read 5, iclass 35, count 0 2006.286.03:09:35.54#ibcon#read 5, iclass 35, count 0 2006.286.03:09:35.54#ibcon#about to read 6, iclass 35, count 0 2006.286.03:09:35.54#ibcon#read 6, iclass 35, count 0 2006.286.03:09:35.54#ibcon#end of sib2, iclass 35, count 0 2006.286.03:09:35.54#ibcon#*mode == 0, iclass 35, count 0 2006.286.03:09:35.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.03:09:35.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.03:09:35.54#ibcon#*before write, iclass 35, count 0 2006.286.03:09:35.54#ibcon#enter sib2, iclass 35, count 0 2006.286.03:09:35.54#ibcon#flushed, iclass 35, count 0 2006.286.03:09:35.54#ibcon#about to write, iclass 35, count 0 2006.286.03:09:35.54#ibcon#wrote, iclass 35, count 0 2006.286.03:09:35.54#ibcon#about to read 3, iclass 35, count 0 2006.286.03:09:35.58#ibcon#read 3, iclass 35, count 0 2006.286.03:09:35.58#ibcon#about to read 4, iclass 35, count 0 2006.286.03:09:35.58#ibcon#read 4, iclass 35, count 0 2006.286.03:09:35.58#ibcon#about to read 5, iclass 35, count 0 2006.286.03:09:35.58#ibcon#read 5, iclass 35, count 0 2006.286.03:09:35.58#ibcon#about to read 6, iclass 35, count 0 2006.286.03:09:35.58#ibcon#read 6, iclass 35, count 0 2006.286.03:09:35.58#ibcon#end of sib2, iclass 35, count 0 2006.286.03:09:35.58#ibcon#*after write, iclass 35, count 0 2006.286.03:09:35.58#ibcon#*before return 0, iclass 35, count 0 2006.286.03:09:35.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:09:35.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:09:35.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.03:09:35.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.03:09:35.58$vck44/vb=3,4 2006.286.03:09:35.58#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.03:09:35.58#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.03:09:35.58#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:35.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:09:35.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:09:35.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:09:35.64#ibcon#enter wrdev, iclass 37, count 2 2006.286.03:09:35.64#ibcon#first serial, iclass 37, count 2 2006.286.03:09:35.64#ibcon#enter sib2, iclass 37, count 2 2006.286.03:09:35.64#ibcon#flushed, iclass 37, count 2 2006.286.03:09:35.64#ibcon#about to write, iclass 37, count 2 2006.286.03:09:35.64#ibcon#wrote, iclass 37, count 2 2006.286.03:09:35.64#ibcon#about to read 3, iclass 37, count 2 2006.286.03:09:35.66#ibcon#read 3, iclass 37, count 2 2006.286.03:09:35.66#ibcon#about to read 4, iclass 37, count 2 2006.286.03:09:35.66#ibcon#read 4, iclass 37, count 2 2006.286.03:09:35.66#ibcon#about to read 5, iclass 37, count 2 2006.286.03:09:35.66#ibcon#read 5, iclass 37, count 2 2006.286.03:09:35.66#ibcon#about to read 6, iclass 37, count 2 2006.286.03:09:35.66#ibcon#read 6, iclass 37, count 2 2006.286.03:09:35.66#ibcon#end of sib2, iclass 37, count 2 2006.286.03:09:35.66#ibcon#*mode == 0, iclass 37, count 2 2006.286.03:09:35.66#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.03:09:35.66#ibcon#[27=AT03-04\r\n] 2006.286.03:09:35.66#ibcon#*before write, iclass 37, count 2 2006.286.03:09:35.66#ibcon#enter sib2, iclass 37, count 2 2006.286.03:09:35.66#ibcon#flushed, iclass 37, count 2 2006.286.03:09:35.66#ibcon#about to write, iclass 37, count 2 2006.286.03:09:35.66#ibcon#wrote, iclass 37, count 2 2006.286.03:09:35.66#ibcon#about to read 3, iclass 37, count 2 2006.286.03:09:35.69#ibcon#read 3, iclass 37, count 2 2006.286.03:09:35.69#ibcon#about to read 4, iclass 37, count 2 2006.286.03:09:35.69#ibcon#read 4, iclass 37, count 2 2006.286.03:09:35.69#ibcon#about to read 5, iclass 37, count 2 2006.286.03:09:35.69#ibcon#read 5, iclass 37, count 2 2006.286.03:09:35.69#ibcon#about to read 6, iclass 37, count 2 2006.286.03:09:35.69#ibcon#read 6, iclass 37, count 2 2006.286.03:09:35.69#ibcon#end of sib2, iclass 37, count 2 2006.286.03:09:35.69#ibcon#*after write, iclass 37, count 2 2006.286.03:09:35.69#ibcon#*before return 0, iclass 37, count 2 2006.286.03:09:35.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:09:35.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:09:35.69#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.03:09:35.69#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:35.69#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:09:35.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:09:35.81#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:09:35.81#ibcon#enter wrdev, iclass 37, count 0 2006.286.03:09:35.81#ibcon#first serial, iclass 37, count 0 2006.286.03:09:35.81#ibcon#enter sib2, iclass 37, count 0 2006.286.03:09:35.81#ibcon#flushed, iclass 37, count 0 2006.286.03:09:35.81#ibcon#about to write, iclass 37, count 0 2006.286.03:09:35.81#ibcon#wrote, iclass 37, count 0 2006.286.03:09:35.81#ibcon#about to read 3, iclass 37, count 0 2006.286.03:09:35.83#ibcon#read 3, iclass 37, count 0 2006.286.03:09:35.83#ibcon#about to read 4, iclass 37, count 0 2006.286.03:09:35.83#ibcon#read 4, iclass 37, count 0 2006.286.03:09:35.83#ibcon#about to read 5, iclass 37, count 0 2006.286.03:09:35.83#ibcon#read 5, iclass 37, count 0 2006.286.03:09:35.83#ibcon#about to read 6, iclass 37, count 0 2006.286.03:09:35.83#ibcon#read 6, iclass 37, count 0 2006.286.03:09:35.83#ibcon#end of sib2, iclass 37, count 0 2006.286.03:09:35.83#ibcon#*mode == 0, iclass 37, count 0 2006.286.03:09:35.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.03:09:35.83#ibcon#[27=USB\r\n] 2006.286.03:09:35.83#ibcon#*before write, iclass 37, count 0 2006.286.03:09:35.83#ibcon#enter sib2, iclass 37, count 0 2006.286.03:09:35.83#ibcon#flushed, iclass 37, count 0 2006.286.03:09:35.83#ibcon#about to write, iclass 37, count 0 2006.286.03:09:35.83#ibcon#wrote, iclass 37, count 0 2006.286.03:09:35.83#ibcon#about to read 3, iclass 37, count 0 2006.286.03:09:35.86#ibcon#read 3, iclass 37, count 0 2006.286.03:09:35.86#ibcon#about to read 4, iclass 37, count 0 2006.286.03:09:35.86#ibcon#read 4, iclass 37, count 0 2006.286.03:09:35.86#ibcon#about to read 5, iclass 37, count 0 2006.286.03:09:35.86#ibcon#read 5, iclass 37, count 0 2006.286.03:09:35.86#ibcon#about to read 6, iclass 37, count 0 2006.286.03:09:35.86#ibcon#read 6, iclass 37, count 0 2006.286.03:09:35.86#ibcon#end of sib2, iclass 37, count 0 2006.286.03:09:35.86#ibcon#*after write, iclass 37, count 0 2006.286.03:09:35.86#ibcon#*before return 0, iclass 37, count 0 2006.286.03:09:35.86#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:09:35.86#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:09:35.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.03:09:35.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.03:09:35.86$vck44/vblo=4,679.99 2006.286.03:09:35.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.03:09:35.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.03:09:35.86#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:35.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:09:35.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:09:35.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:09:35.86#ibcon#enter wrdev, iclass 39, count 0 2006.286.03:09:35.86#ibcon#first serial, iclass 39, count 0 2006.286.03:09:35.86#ibcon#enter sib2, iclass 39, count 0 2006.286.03:09:35.86#ibcon#flushed, iclass 39, count 0 2006.286.03:09:35.86#ibcon#about to write, iclass 39, count 0 2006.286.03:09:35.86#ibcon#wrote, iclass 39, count 0 2006.286.03:09:35.86#ibcon#about to read 3, iclass 39, count 0 2006.286.03:09:35.88#ibcon#read 3, iclass 39, count 0 2006.286.03:09:35.93#ibcon#about to read 4, iclass 39, count 0 2006.286.03:09:35.93#ibcon#read 4, iclass 39, count 0 2006.286.03:09:35.93#ibcon#about to read 5, iclass 39, count 0 2006.286.03:09:35.93#ibcon#read 5, iclass 39, count 0 2006.286.03:09:35.93#ibcon#about to read 6, iclass 39, count 0 2006.286.03:09:35.93#ibcon#read 6, iclass 39, count 0 2006.286.03:09:35.93#ibcon#end of sib2, iclass 39, count 0 2006.286.03:09:35.93#ibcon#*mode == 0, iclass 39, count 0 2006.286.03:09:35.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.03:09:35.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.03:09:35.93#ibcon#*before write, iclass 39, count 0 2006.286.03:09:35.93#ibcon#enter sib2, iclass 39, count 0 2006.286.03:09:35.93#ibcon#flushed, iclass 39, count 0 2006.286.03:09:35.93#ibcon#about to write, iclass 39, count 0 2006.286.03:09:35.93#ibcon#wrote, iclass 39, count 0 2006.286.03:09:35.93#ibcon#about to read 3, iclass 39, count 0 2006.286.03:09:35.98#ibcon#read 3, iclass 39, count 0 2006.286.03:09:35.98#ibcon#about to read 4, iclass 39, count 0 2006.286.03:09:35.98#ibcon#read 4, iclass 39, count 0 2006.286.03:09:35.98#ibcon#about to read 5, iclass 39, count 0 2006.286.03:09:35.98#ibcon#read 5, iclass 39, count 0 2006.286.03:09:35.98#ibcon#about to read 6, iclass 39, count 0 2006.286.03:09:35.98#ibcon#read 6, iclass 39, count 0 2006.286.03:09:35.98#ibcon#end of sib2, iclass 39, count 0 2006.286.03:09:35.98#ibcon#*after write, iclass 39, count 0 2006.286.03:09:35.98#ibcon#*before return 0, iclass 39, count 0 2006.286.03:09:35.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:09:35.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:09:35.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.03:09:35.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.03:09:35.98$vck44/vb=4,5 2006.286.03:09:35.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.03:09:35.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.03:09:35.98#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:35.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:09:35.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:09:35.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:09:35.98#ibcon#enter wrdev, iclass 3, count 2 2006.286.03:09:35.98#ibcon#first serial, iclass 3, count 2 2006.286.03:09:35.98#ibcon#enter sib2, iclass 3, count 2 2006.286.03:09:35.98#ibcon#flushed, iclass 3, count 2 2006.286.03:09:35.98#ibcon#about to write, iclass 3, count 2 2006.286.03:09:35.98#ibcon#wrote, iclass 3, count 2 2006.286.03:09:35.98#ibcon#about to read 3, iclass 3, count 2 2006.286.03:09:36.00#ibcon#read 3, iclass 3, count 2 2006.286.03:09:36.00#ibcon#about to read 4, iclass 3, count 2 2006.286.03:09:36.00#ibcon#read 4, iclass 3, count 2 2006.286.03:09:36.00#ibcon#about to read 5, iclass 3, count 2 2006.286.03:09:36.00#ibcon#read 5, iclass 3, count 2 2006.286.03:09:36.00#ibcon#about to read 6, iclass 3, count 2 2006.286.03:09:36.00#ibcon#read 6, iclass 3, count 2 2006.286.03:09:36.00#ibcon#end of sib2, iclass 3, count 2 2006.286.03:09:36.00#ibcon#*mode == 0, iclass 3, count 2 2006.286.03:09:36.00#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.03:09:36.00#ibcon#[27=AT04-05\r\n] 2006.286.03:09:36.00#ibcon#*before write, iclass 3, count 2 2006.286.03:09:36.00#ibcon#enter sib2, iclass 3, count 2 2006.286.03:09:36.00#ibcon#flushed, iclass 3, count 2 2006.286.03:09:36.00#ibcon#about to write, iclass 3, count 2 2006.286.03:09:36.00#ibcon#wrote, iclass 3, count 2 2006.286.03:09:36.00#ibcon#about to read 3, iclass 3, count 2 2006.286.03:09:36.03#ibcon#read 3, iclass 3, count 2 2006.286.03:09:36.03#ibcon#about to read 4, iclass 3, count 2 2006.286.03:09:36.03#ibcon#read 4, iclass 3, count 2 2006.286.03:09:36.03#ibcon#about to read 5, iclass 3, count 2 2006.286.03:09:36.03#ibcon#read 5, iclass 3, count 2 2006.286.03:09:36.03#ibcon#about to read 6, iclass 3, count 2 2006.286.03:09:36.03#ibcon#read 6, iclass 3, count 2 2006.286.03:09:36.03#ibcon#end of sib2, iclass 3, count 2 2006.286.03:09:36.03#ibcon#*after write, iclass 3, count 2 2006.286.03:09:36.03#ibcon#*before return 0, iclass 3, count 2 2006.286.03:09:36.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:09:36.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:09:36.03#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.03:09:36.03#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:36.03#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:09:36.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:09:36.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:09:36.15#ibcon#enter wrdev, iclass 3, count 0 2006.286.03:09:36.15#ibcon#first serial, iclass 3, count 0 2006.286.03:09:36.15#ibcon#enter sib2, iclass 3, count 0 2006.286.03:09:36.15#ibcon#flushed, iclass 3, count 0 2006.286.03:09:36.15#ibcon#about to write, iclass 3, count 0 2006.286.03:09:36.15#ibcon#wrote, iclass 3, count 0 2006.286.03:09:36.15#ibcon#about to read 3, iclass 3, count 0 2006.286.03:09:36.17#ibcon#read 3, iclass 3, count 0 2006.286.03:09:36.17#ibcon#about to read 4, iclass 3, count 0 2006.286.03:09:36.17#ibcon#read 4, iclass 3, count 0 2006.286.03:09:36.17#ibcon#about to read 5, iclass 3, count 0 2006.286.03:09:36.17#ibcon#read 5, iclass 3, count 0 2006.286.03:09:36.17#ibcon#about to read 6, iclass 3, count 0 2006.286.03:09:36.17#ibcon#read 6, iclass 3, count 0 2006.286.03:09:36.17#ibcon#end of sib2, iclass 3, count 0 2006.286.03:09:36.17#ibcon#*mode == 0, iclass 3, count 0 2006.286.03:09:36.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.03:09:36.17#ibcon#[27=USB\r\n] 2006.286.03:09:36.17#ibcon#*before write, iclass 3, count 0 2006.286.03:09:36.17#ibcon#enter sib2, iclass 3, count 0 2006.286.03:09:36.17#ibcon#flushed, iclass 3, count 0 2006.286.03:09:36.17#ibcon#about to write, iclass 3, count 0 2006.286.03:09:36.17#ibcon#wrote, iclass 3, count 0 2006.286.03:09:36.17#ibcon#about to read 3, iclass 3, count 0 2006.286.03:09:36.20#ibcon#read 3, iclass 3, count 0 2006.286.03:09:36.20#ibcon#about to read 4, iclass 3, count 0 2006.286.03:09:36.20#ibcon#read 4, iclass 3, count 0 2006.286.03:09:36.20#ibcon#about to read 5, iclass 3, count 0 2006.286.03:09:36.20#ibcon#read 5, iclass 3, count 0 2006.286.03:09:36.20#ibcon#about to read 6, iclass 3, count 0 2006.286.03:09:36.20#ibcon#read 6, iclass 3, count 0 2006.286.03:09:36.20#ibcon#end of sib2, iclass 3, count 0 2006.286.03:09:36.20#ibcon#*after write, iclass 3, count 0 2006.286.03:09:36.20#ibcon#*before return 0, iclass 3, count 0 2006.286.03:09:36.20#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:09:36.20#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:09:36.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.03:09:36.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.03:09:36.20$vck44/vblo=5,709.99 2006.286.03:09:36.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.03:09:36.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.03:09:36.20#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:36.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:09:36.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:09:36.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:09:36.20#ibcon#enter wrdev, iclass 5, count 0 2006.286.03:09:36.20#ibcon#first serial, iclass 5, count 0 2006.286.03:09:36.20#ibcon#enter sib2, iclass 5, count 0 2006.286.03:09:36.20#ibcon#flushed, iclass 5, count 0 2006.286.03:09:36.20#ibcon#about to write, iclass 5, count 0 2006.286.03:09:36.20#ibcon#wrote, iclass 5, count 0 2006.286.03:09:36.20#ibcon#about to read 3, iclass 5, count 0 2006.286.03:09:36.22#ibcon#read 3, iclass 5, count 0 2006.286.03:09:36.22#ibcon#about to read 4, iclass 5, count 0 2006.286.03:09:36.22#ibcon#read 4, iclass 5, count 0 2006.286.03:09:36.22#ibcon#about to read 5, iclass 5, count 0 2006.286.03:09:36.22#ibcon#read 5, iclass 5, count 0 2006.286.03:09:36.22#ibcon#about to read 6, iclass 5, count 0 2006.286.03:09:36.22#ibcon#read 6, iclass 5, count 0 2006.286.03:09:36.22#ibcon#end of sib2, iclass 5, count 0 2006.286.03:09:36.22#ibcon#*mode == 0, iclass 5, count 0 2006.286.03:09:36.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.03:09:36.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.03:09:36.22#ibcon#*before write, iclass 5, count 0 2006.286.03:09:36.22#ibcon#enter sib2, iclass 5, count 0 2006.286.03:09:36.22#ibcon#flushed, iclass 5, count 0 2006.286.03:09:36.22#ibcon#about to write, iclass 5, count 0 2006.286.03:09:36.22#ibcon#wrote, iclass 5, count 0 2006.286.03:09:36.22#ibcon#about to read 3, iclass 5, count 0 2006.286.03:09:36.26#ibcon#read 3, iclass 5, count 0 2006.286.03:09:36.26#ibcon#about to read 4, iclass 5, count 0 2006.286.03:09:36.26#ibcon#read 4, iclass 5, count 0 2006.286.03:09:36.26#ibcon#about to read 5, iclass 5, count 0 2006.286.03:09:36.26#ibcon#read 5, iclass 5, count 0 2006.286.03:09:36.26#ibcon#about to read 6, iclass 5, count 0 2006.286.03:09:36.26#ibcon#read 6, iclass 5, count 0 2006.286.03:09:36.26#ibcon#end of sib2, iclass 5, count 0 2006.286.03:09:36.26#ibcon#*after write, iclass 5, count 0 2006.286.03:09:36.26#ibcon#*before return 0, iclass 5, count 0 2006.286.03:09:36.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:09:36.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:09:36.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.03:09:36.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.03:09:36.26$vck44/vb=5,4 2006.286.03:09:36.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.03:09:36.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.03:09:36.26#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:36.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:09:36.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:09:36.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:09:36.32#ibcon#enter wrdev, iclass 7, count 2 2006.286.03:09:36.32#ibcon#first serial, iclass 7, count 2 2006.286.03:09:36.32#ibcon#enter sib2, iclass 7, count 2 2006.286.03:09:36.32#ibcon#flushed, iclass 7, count 2 2006.286.03:09:36.32#ibcon#about to write, iclass 7, count 2 2006.286.03:09:36.32#ibcon#wrote, iclass 7, count 2 2006.286.03:09:36.32#ibcon#about to read 3, iclass 7, count 2 2006.286.03:09:36.34#ibcon#read 3, iclass 7, count 2 2006.286.03:09:36.34#ibcon#about to read 4, iclass 7, count 2 2006.286.03:09:36.34#ibcon#read 4, iclass 7, count 2 2006.286.03:09:36.34#ibcon#about to read 5, iclass 7, count 2 2006.286.03:09:36.34#ibcon#read 5, iclass 7, count 2 2006.286.03:09:36.34#ibcon#about to read 6, iclass 7, count 2 2006.286.03:09:36.34#ibcon#read 6, iclass 7, count 2 2006.286.03:09:36.34#ibcon#end of sib2, iclass 7, count 2 2006.286.03:09:36.34#ibcon#*mode == 0, iclass 7, count 2 2006.286.03:09:36.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.03:09:36.34#ibcon#[27=AT05-04\r\n] 2006.286.03:09:36.34#ibcon#*before write, iclass 7, count 2 2006.286.03:09:36.34#ibcon#enter sib2, iclass 7, count 2 2006.286.03:09:36.34#ibcon#flushed, iclass 7, count 2 2006.286.03:09:36.34#ibcon#about to write, iclass 7, count 2 2006.286.03:09:36.34#ibcon#wrote, iclass 7, count 2 2006.286.03:09:36.34#ibcon#about to read 3, iclass 7, count 2 2006.286.03:09:36.37#ibcon#read 3, iclass 7, count 2 2006.286.03:09:36.37#ibcon#about to read 4, iclass 7, count 2 2006.286.03:09:36.37#ibcon#read 4, iclass 7, count 2 2006.286.03:09:36.37#ibcon#about to read 5, iclass 7, count 2 2006.286.03:09:36.37#ibcon#read 5, iclass 7, count 2 2006.286.03:09:36.37#ibcon#about to read 6, iclass 7, count 2 2006.286.03:09:36.37#ibcon#read 6, iclass 7, count 2 2006.286.03:09:36.37#ibcon#end of sib2, iclass 7, count 2 2006.286.03:09:36.37#ibcon#*after write, iclass 7, count 2 2006.286.03:09:36.37#ibcon#*before return 0, iclass 7, count 2 2006.286.03:09:36.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:09:36.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:09:36.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.03:09:36.37#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:36.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:09:36.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:09:36.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:09:36.49#ibcon#enter wrdev, iclass 7, count 0 2006.286.03:09:36.49#ibcon#first serial, iclass 7, count 0 2006.286.03:09:36.49#ibcon#enter sib2, iclass 7, count 0 2006.286.03:09:36.49#ibcon#flushed, iclass 7, count 0 2006.286.03:09:36.49#ibcon#about to write, iclass 7, count 0 2006.286.03:09:36.49#ibcon#wrote, iclass 7, count 0 2006.286.03:09:36.49#ibcon#about to read 3, iclass 7, count 0 2006.286.03:09:36.51#ibcon#read 3, iclass 7, count 0 2006.286.03:09:36.51#ibcon#about to read 4, iclass 7, count 0 2006.286.03:09:36.51#ibcon#read 4, iclass 7, count 0 2006.286.03:09:36.51#ibcon#about to read 5, iclass 7, count 0 2006.286.03:09:36.51#ibcon#read 5, iclass 7, count 0 2006.286.03:09:36.51#ibcon#about to read 6, iclass 7, count 0 2006.286.03:09:36.51#ibcon#read 6, iclass 7, count 0 2006.286.03:09:36.51#ibcon#end of sib2, iclass 7, count 0 2006.286.03:09:36.51#ibcon#*mode == 0, iclass 7, count 0 2006.286.03:09:36.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.03:09:36.51#ibcon#[27=USB\r\n] 2006.286.03:09:36.51#ibcon#*before write, iclass 7, count 0 2006.286.03:09:36.51#ibcon#enter sib2, iclass 7, count 0 2006.286.03:09:36.51#ibcon#flushed, iclass 7, count 0 2006.286.03:09:36.51#ibcon#about to write, iclass 7, count 0 2006.286.03:09:36.51#ibcon#wrote, iclass 7, count 0 2006.286.03:09:36.51#ibcon#about to read 3, iclass 7, count 0 2006.286.03:09:36.54#ibcon#read 3, iclass 7, count 0 2006.286.03:09:36.54#ibcon#about to read 4, iclass 7, count 0 2006.286.03:09:36.54#ibcon#read 4, iclass 7, count 0 2006.286.03:09:36.54#ibcon#about to read 5, iclass 7, count 0 2006.286.03:09:36.54#ibcon#read 5, iclass 7, count 0 2006.286.03:09:36.54#ibcon#about to read 6, iclass 7, count 0 2006.286.03:09:36.54#ibcon#read 6, iclass 7, count 0 2006.286.03:09:36.54#ibcon#end of sib2, iclass 7, count 0 2006.286.03:09:36.54#ibcon#*after write, iclass 7, count 0 2006.286.03:09:36.54#ibcon#*before return 0, iclass 7, count 0 2006.286.03:09:36.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:09:36.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:09:36.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.03:09:36.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.03:09:36.54$vck44/vblo=6,719.99 2006.286.03:09:36.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.03:09:36.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.03:09:36.54#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:36.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:09:36.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:09:36.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:09:36.54#ibcon#enter wrdev, iclass 11, count 0 2006.286.03:09:36.54#ibcon#first serial, iclass 11, count 0 2006.286.03:09:36.54#ibcon#enter sib2, iclass 11, count 0 2006.286.03:09:36.54#ibcon#flushed, iclass 11, count 0 2006.286.03:09:36.54#ibcon#about to write, iclass 11, count 0 2006.286.03:09:36.54#ibcon#wrote, iclass 11, count 0 2006.286.03:09:36.54#ibcon#about to read 3, iclass 11, count 0 2006.286.03:09:36.56#ibcon#read 3, iclass 11, count 0 2006.286.03:09:36.56#ibcon#about to read 4, iclass 11, count 0 2006.286.03:09:36.56#ibcon#read 4, iclass 11, count 0 2006.286.03:09:36.56#ibcon#about to read 5, iclass 11, count 0 2006.286.03:09:36.56#ibcon#read 5, iclass 11, count 0 2006.286.03:09:36.56#ibcon#about to read 6, iclass 11, count 0 2006.286.03:09:36.56#ibcon#read 6, iclass 11, count 0 2006.286.03:09:36.56#ibcon#end of sib2, iclass 11, count 0 2006.286.03:09:36.56#ibcon#*mode == 0, iclass 11, count 0 2006.286.03:09:36.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.03:09:36.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.03:09:36.56#ibcon#*before write, iclass 11, count 0 2006.286.03:09:36.56#ibcon#enter sib2, iclass 11, count 0 2006.286.03:09:36.56#ibcon#flushed, iclass 11, count 0 2006.286.03:09:36.56#ibcon#about to write, iclass 11, count 0 2006.286.03:09:36.56#ibcon#wrote, iclass 11, count 0 2006.286.03:09:36.56#ibcon#about to read 3, iclass 11, count 0 2006.286.03:09:36.60#ibcon#read 3, iclass 11, count 0 2006.286.03:09:36.60#ibcon#about to read 4, iclass 11, count 0 2006.286.03:09:36.60#ibcon#read 4, iclass 11, count 0 2006.286.03:09:36.60#ibcon#about to read 5, iclass 11, count 0 2006.286.03:09:36.60#ibcon#read 5, iclass 11, count 0 2006.286.03:09:36.60#ibcon#about to read 6, iclass 11, count 0 2006.286.03:09:36.60#ibcon#read 6, iclass 11, count 0 2006.286.03:09:36.60#ibcon#end of sib2, iclass 11, count 0 2006.286.03:09:36.60#ibcon#*after write, iclass 11, count 0 2006.286.03:09:36.60#ibcon#*before return 0, iclass 11, count 0 2006.286.03:09:36.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:09:36.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:09:36.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.03:09:36.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.03:09:36.60$vck44/vb=6,3 2006.286.03:09:36.60#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.03:09:36.60#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.03:09:36.60#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:36.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:09:36.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:09:36.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:09:36.66#ibcon#enter wrdev, iclass 13, count 2 2006.286.03:09:36.66#ibcon#first serial, iclass 13, count 2 2006.286.03:09:36.66#ibcon#enter sib2, iclass 13, count 2 2006.286.03:09:36.66#ibcon#flushed, iclass 13, count 2 2006.286.03:09:36.66#ibcon#about to write, iclass 13, count 2 2006.286.03:09:36.66#ibcon#wrote, iclass 13, count 2 2006.286.03:09:36.66#ibcon#about to read 3, iclass 13, count 2 2006.286.03:09:36.68#ibcon#read 3, iclass 13, count 2 2006.286.03:09:36.68#ibcon#about to read 4, iclass 13, count 2 2006.286.03:09:36.68#ibcon#read 4, iclass 13, count 2 2006.286.03:09:36.68#ibcon#about to read 5, iclass 13, count 2 2006.286.03:09:36.68#ibcon#read 5, iclass 13, count 2 2006.286.03:09:36.68#ibcon#about to read 6, iclass 13, count 2 2006.286.03:09:36.68#ibcon#read 6, iclass 13, count 2 2006.286.03:09:36.68#ibcon#end of sib2, iclass 13, count 2 2006.286.03:09:36.68#ibcon#*mode == 0, iclass 13, count 2 2006.286.03:09:36.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.03:09:36.68#ibcon#[27=AT06-03\r\n] 2006.286.03:09:36.68#ibcon#*before write, iclass 13, count 2 2006.286.03:09:36.68#ibcon#enter sib2, iclass 13, count 2 2006.286.03:09:36.68#ibcon#flushed, iclass 13, count 2 2006.286.03:09:36.68#ibcon#about to write, iclass 13, count 2 2006.286.03:09:36.68#ibcon#wrote, iclass 13, count 2 2006.286.03:09:36.68#ibcon#about to read 3, iclass 13, count 2 2006.286.03:09:36.71#ibcon#read 3, iclass 13, count 2 2006.286.03:09:36.71#ibcon#about to read 4, iclass 13, count 2 2006.286.03:09:36.71#ibcon#read 4, iclass 13, count 2 2006.286.03:09:36.71#ibcon#about to read 5, iclass 13, count 2 2006.286.03:09:36.71#ibcon#read 5, iclass 13, count 2 2006.286.03:09:36.71#ibcon#about to read 6, iclass 13, count 2 2006.286.03:09:36.71#ibcon#read 6, iclass 13, count 2 2006.286.03:09:36.71#ibcon#end of sib2, iclass 13, count 2 2006.286.03:09:36.71#ibcon#*after write, iclass 13, count 2 2006.286.03:09:36.71#ibcon#*before return 0, iclass 13, count 2 2006.286.03:09:36.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:09:36.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:09:36.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.03:09:36.71#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:36.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:09:36.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:09:36.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:09:36.83#ibcon#enter wrdev, iclass 13, count 0 2006.286.03:09:36.83#ibcon#first serial, iclass 13, count 0 2006.286.03:09:36.83#ibcon#enter sib2, iclass 13, count 0 2006.286.03:09:36.83#ibcon#flushed, iclass 13, count 0 2006.286.03:09:36.83#ibcon#about to write, iclass 13, count 0 2006.286.03:09:36.83#ibcon#wrote, iclass 13, count 0 2006.286.03:09:36.83#ibcon#about to read 3, iclass 13, count 0 2006.286.03:09:36.85#ibcon#read 3, iclass 13, count 0 2006.286.03:09:36.85#ibcon#about to read 4, iclass 13, count 0 2006.286.03:09:36.85#ibcon#read 4, iclass 13, count 0 2006.286.03:09:36.85#ibcon#about to read 5, iclass 13, count 0 2006.286.03:09:36.85#ibcon#read 5, iclass 13, count 0 2006.286.03:09:36.85#ibcon#about to read 6, iclass 13, count 0 2006.286.03:09:36.85#ibcon#read 6, iclass 13, count 0 2006.286.03:09:36.85#ibcon#end of sib2, iclass 13, count 0 2006.286.03:09:36.85#ibcon#*mode == 0, iclass 13, count 0 2006.286.03:09:36.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.03:09:36.85#ibcon#[27=USB\r\n] 2006.286.03:09:36.85#ibcon#*before write, iclass 13, count 0 2006.286.03:09:36.85#ibcon#enter sib2, iclass 13, count 0 2006.286.03:09:36.85#ibcon#flushed, iclass 13, count 0 2006.286.03:09:36.85#ibcon#about to write, iclass 13, count 0 2006.286.03:09:36.85#ibcon#wrote, iclass 13, count 0 2006.286.03:09:36.85#ibcon#about to read 3, iclass 13, count 0 2006.286.03:09:36.88#ibcon#read 3, iclass 13, count 0 2006.286.03:09:36.88#ibcon#about to read 4, iclass 13, count 0 2006.286.03:09:36.88#ibcon#read 4, iclass 13, count 0 2006.286.03:09:36.88#ibcon#about to read 5, iclass 13, count 0 2006.286.03:09:36.88#ibcon#read 5, iclass 13, count 0 2006.286.03:09:36.88#ibcon#about to read 6, iclass 13, count 0 2006.286.03:09:36.88#ibcon#read 6, iclass 13, count 0 2006.286.03:09:36.88#ibcon#end of sib2, iclass 13, count 0 2006.286.03:09:36.88#ibcon#*after write, iclass 13, count 0 2006.286.03:09:36.88#ibcon#*before return 0, iclass 13, count 0 2006.286.03:09:36.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:09:36.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:09:36.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.03:09:36.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.03:09:36.88$vck44/vblo=7,734.99 2006.286.03:09:36.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.03:09:36.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.03:09:36.88#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:36.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:09:36.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:09:36.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:09:36.88#ibcon#enter wrdev, iclass 15, count 0 2006.286.03:09:36.88#ibcon#first serial, iclass 15, count 0 2006.286.03:09:36.88#ibcon#enter sib2, iclass 15, count 0 2006.286.03:09:36.88#ibcon#flushed, iclass 15, count 0 2006.286.03:09:36.88#ibcon#about to write, iclass 15, count 0 2006.286.03:09:36.88#ibcon#wrote, iclass 15, count 0 2006.286.03:09:36.88#ibcon#about to read 3, iclass 15, count 0 2006.286.03:09:36.90#ibcon#read 3, iclass 15, count 0 2006.286.03:09:36.95#ibcon#about to read 4, iclass 15, count 0 2006.286.03:09:36.95#ibcon#read 4, iclass 15, count 0 2006.286.03:09:36.95#ibcon#about to read 5, iclass 15, count 0 2006.286.03:09:36.95#ibcon#read 5, iclass 15, count 0 2006.286.03:09:36.95#ibcon#about to read 6, iclass 15, count 0 2006.286.03:09:36.95#ibcon#read 6, iclass 15, count 0 2006.286.03:09:36.95#ibcon#end of sib2, iclass 15, count 0 2006.286.03:09:36.95#ibcon#*mode == 0, iclass 15, count 0 2006.286.03:09:36.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.03:09:36.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.03:09:36.95#ibcon#*before write, iclass 15, count 0 2006.286.03:09:36.95#ibcon#enter sib2, iclass 15, count 0 2006.286.03:09:36.95#ibcon#flushed, iclass 15, count 0 2006.286.03:09:36.95#ibcon#about to write, iclass 15, count 0 2006.286.03:09:36.95#ibcon#wrote, iclass 15, count 0 2006.286.03:09:36.95#ibcon#about to read 3, iclass 15, count 0 2006.286.03:09:37.00#ibcon#read 3, iclass 15, count 0 2006.286.03:09:37.00#ibcon#about to read 4, iclass 15, count 0 2006.286.03:09:37.00#ibcon#read 4, iclass 15, count 0 2006.286.03:09:37.00#ibcon#about to read 5, iclass 15, count 0 2006.286.03:09:37.00#ibcon#read 5, iclass 15, count 0 2006.286.03:09:37.00#ibcon#about to read 6, iclass 15, count 0 2006.286.03:09:37.00#ibcon#read 6, iclass 15, count 0 2006.286.03:09:37.00#ibcon#end of sib2, iclass 15, count 0 2006.286.03:09:37.00#ibcon#*after write, iclass 15, count 0 2006.286.03:09:37.00#ibcon#*before return 0, iclass 15, count 0 2006.286.03:09:37.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:09:37.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:09:37.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.03:09:37.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.03:09:37.00$vck44/vb=7,4 2006.286.03:09:37.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.03:09:37.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.03:09:37.00#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:37.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:09:37.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:09:37.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:09:37.00#ibcon#enter wrdev, iclass 17, count 2 2006.286.03:09:37.00#ibcon#first serial, iclass 17, count 2 2006.286.03:09:37.00#ibcon#enter sib2, iclass 17, count 2 2006.286.03:09:37.00#ibcon#flushed, iclass 17, count 2 2006.286.03:09:37.00#ibcon#about to write, iclass 17, count 2 2006.286.03:09:37.00#ibcon#wrote, iclass 17, count 2 2006.286.03:09:37.00#ibcon#about to read 3, iclass 17, count 2 2006.286.03:09:37.02#ibcon#read 3, iclass 17, count 2 2006.286.03:09:37.02#ibcon#about to read 4, iclass 17, count 2 2006.286.03:09:37.02#ibcon#read 4, iclass 17, count 2 2006.286.03:09:37.02#ibcon#about to read 5, iclass 17, count 2 2006.286.03:09:37.02#ibcon#read 5, iclass 17, count 2 2006.286.03:09:37.02#ibcon#about to read 6, iclass 17, count 2 2006.286.03:09:37.02#ibcon#read 6, iclass 17, count 2 2006.286.03:09:37.02#ibcon#end of sib2, iclass 17, count 2 2006.286.03:09:37.02#ibcon#*mode == 0, iclass 17, count 2 2006.286.03:09:37.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.03:09:37.02#ibcon#[27=AT07-04\r\n] 2006.286.03:09:37.02#ibcon#*before write, iclass 17, count 2 2006.286.03:09:37.02#ibcon#enter sib2, iclass 17, count 2 2006.286.03:09:37.02#ibcon#flushed, iclass 17, count 2 2006.286.03:09:37.02#ibcon#about to write, iclass 17, count 2 2006.286.03:09:37.02#ibcon#wrote, iclass 17, count 2 2006.286.03:09:37.02#ibcon#about to read 3, iclass 17, count 2 2006.286.03:09:37.05#ibcon#read 3, iclass 17, count 2 2006.286.03:09:37.05#ibcon#about to read 4, iclass 17, count 2 2006.286.03:09:37.05#ibcon#read 4, iclass 17, count 2 2006.286.03:09:37.05#ibcon#about to read 5, iclass 17, count 2 2006.286.03:09:37.05#ibcon#read 5, iclass 17, count 2 2006.286.03:09:37.05#ibcon#about to read 6, iclass 17, count 2 2006.286.03:09:37.05#ibcon#read 6, iclass 17, count 2 2006.286.03:09:37.05#ibcon#end of sib2, iclass 17, count 2 2006.286.03:09:37.05#ibcon#*after write, iclass 17, count 2 2006.286.03:09:37.05#ibcon#*before return 0, iclass 17, count 2 2006.286.03:09:37.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:09:37.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:09:37.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.03:09:37.05#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:37.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:09:37.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:09:37.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:09:37.17#ibcon#enter wrdev, iclass 17, count 0 2006.286.03:09:37.17#ibcon#first serial, iclass 17, count 0 2006.286.03:09:37.17#ibcon#enter sib2, iclass 17, count 0 2006.286.03:09:37.17#ibcon#flushed, iclass 17, count 0 2006.286.03:09:37.17#ibcon#about to write, iclass 17, count 0 2006.286.03:09:37.17#ibcon#wrote, iclass 17, count 0 2006.286.03:09:37.17#ibcon#about to read 3, iclass 17, count 0 2006.286.03:09:37.19#ibcon#read 3, iclass 17, count 0 2006.286.03:09:37.19#ibcon#about to read 4, iclass 17, count 0 2006.286.03:09:37.19#ibcon#read 4, iclass 17, count 0 2006.286.03:09:37.19#ibcon#about to read 5, iclass 17, count 0 2006.286.03:09:37.19#ibcon#read 5, iclass 17, count 0 2006.286.03:09:37.19#ibcon#about to read 6, iclass 17, count 0 2006.286.03:09:37.19#ibcon#read 6, iclass 17, count 0 2006.286.03:09:37.19#ibcon#end of sib2, iclass 17, count 0 2006.286.03:09:37.19#ibcon#*mode == 0, iclass 17, count 0 2006.286.03:09:37.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.03:09:37.19#ibcon#[27=USB\r\n] 2006.286.03:09:37.19#ibcon#*before write, iclass 17, count 0 2006.286.03:09:37.19#ibcon#enter sib2, iclass 17, count 0 2006.286.03:09:37.19#ibcon#flushed, iclass 17, count 0 2006.286.03:09:37.19#ibcon#about to write, iclass 17, count 0 2006.286.03:09:37.19#ibcon#wrote, iclass 17, count 0 2006.286.03:09:37.19#ibcon#about to read 3, iclass 17, count 0 2006.286.03:09:37.22#ibcon#read 3, iclass 17, count 0 2006.286.03:09:37.22#ibcon#about to read 4, iclass 17, count 0 2006.286.03:09:37.22#ibcon#read 4, iclass 17, count 0 2006.286.03:09:37.22#ibcon#about to read 5, iclass 17, count 0 2006.286.03:09:37.22#ibcon#read 5, iclass 17, count 0 2006.286.03:09:37.22#ibcon#about to read 6, iclass 17, count 0 2006.286.03:09:37.22#ibcon#read 6, iclass 17, count 0 2006.286.03:09:37.22#ibcon#end of sib2, iclass 17, count 0 2006.286.03:09:37.22#ibcon#*after write, iclass 17, count 0 2006.286.03:09:37.22#ibcon#*before return 0, iclass 17, count 0 2006.286.03:09:37.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:09:37.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:09:37.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.03:09:37.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.03:09:37.22$vck44/vblo=8,744.99 2006.286.03:09:37.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.03:09:37.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.03:09:37.22#ibcon#ireg 17 cls_cnt 0 2006.286.03:09:37.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:09:37.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:09:37.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:09:37.22#ibcon#enter wrdev, iclass 19, count 0 2006.286.03:09:37.22#ibcon#first serial, iclass 19, count 0 2006.286.03:09:37.22#ibcon#enter sib2, iclass 19, count 0 2006.286.03:09:37.22#ibcon#flushed, iclass 19, count 0 2006.286.03:09:37.22#ibcon#about to write, iclass 19, count 0 2006.286.03:09:37.22#ibcon#wrote, iclass 19, count 0 2006.286.03:09:37.22#ibcon#about to read 3, iclass 19, count 0 2006.286.03:09:37.24#ibcon#read 3, iclass 19, count 0 2006.286.03:09:37.24#ibcon#about to read 4, iclass 19, count 0 2006.286.03:09:37.24#ibcon#read 4, iclass 19, count 0 2006.286.03:09:37.24#ibcon#about to read 5, iclass 19, count 0 2006.286.03:09:37.24#ibcon#read 5, iclass 19, count 0 2006.286.03:09:37.24#ibcon#about to read 6, iclass 19, count 0 2006.286.03:09:37.24#ibcon#read 6, iclass 19, count 0 2006.286.03:09:37.24#ibcon#end of sib2, iclass 19, count 0 2006.286.03:09:37.24#ibcon#*mode == 0, iclass 19, count 0 2006.286.03:09:37.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.03:09:37.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.03:09:37.24#ibcon#*before write, iclass 19, count 0 2006.286.03:09:37.24#ibcon#enter sib2, iclass 19, count 0 2006.286.03:09:37.24#ibcon#flushed, iclass 19, count 0 2006.286.03:09:37.24#ibcon#about to write, iclass 19, count 0 2006.286.03:09:37.24#ibcon#wrote, iclass 19, count 0 2006.286.03:09:37.24#ibcon#about to read 3, iclass 19, count 0 2006.286.03:09:37.28#ibcon#read 3, iclass 19, count 0 2006.286.03:09:37.28#ibcon#about to read 4, iclass 19, count 0 2006.286.03:09:37.28#ibcon#read 4, iclass 19, count 0 2006.286.03:09:37.28#ibcon#about to read 5, iclass 19, count 0 2006.286.03:09:37.28#ibcon#read 5, iclass 19, count 0 2006.286.03:09:37.28#ibcon#about to read 6, iclass 19, count 0 2006.286.03:09:37.28#ibcon#read 6, iclass 19, count 0 2006.286.03:09:37.28#ibcon#end of sib2, iclass 19, count 0 2006.286.03:09:37.28#ibcon#*after write, iclass 19, count 0 2006.286.03:09:37.28#ibcon#*before return 0, iclass 19, count 0 2006.286.03:09:37.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:09:37.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:09:37.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.03:09:37.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.03:09:37.28$vck44/vb=8,4 2006.286.03:09:37.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.03:09:37.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.03:09:37.28#ibcon#ireg 11 cls_cnt 2 2006.286.03:09:37.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:09:37.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:09:37.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:09:37.34#ibcon#enter wrdev, iclass 21, count 2 2006.286.03:09:37.34#ibcon#first serial, iclass 21, count 2 2006.286.03:09:37.34#ibcon#enter sib2, iclass 21, count 2 2006.286.03:09:37.34#ibcon#flushed, iclass 21, count 2 2006.286.03:09:37.34#ibcon#about to write, iclass 21, count 2 2006.286.03:09:37.34#ibcon#wrote, iclass 21, count 2 2006.286.03:09:37.34#ibcon#about to read 3, iclass 21, count 2 2006.286.03:09:37.36#ibcon#read 3, iclass 21, count 2 2006.286.03:09:37.36#ibcon#about to read 4, iclass 21, count 2 2006.286.03:09:37.36#ibcon#read 4, iclass 21, count 2 2006.286.03:09:37.36#ibcon#about to read 5, iclass 21, count 2 2006.286.03:09:37.36#ibcon#read 5, iclass 21, count 2 2006.286.03:09:37.36#ibcon#about to read 6, iclass 21, count 2 2006.286.03:09:37.36#ibcon#read 6, iclass 21, count 2 2006.286.03:09:37.36#ibcon#end of sib2, iclass 21, count 2 2006.286.03:09:37.36#ibcon#*mode == 0, iclass 21, count 2 2006.286.03:09:37.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.03:09:37.36#ibcon#[27=AT08-04\r\n] 2006.286.03:09:37.36#ibcon#*before write, iclass 21, count 2 2006.286.03:09:37.36#ibcon#enter sib2, iclass 21, count 2 2006.286.03:09:37.36#ibcon#flushed, iclass 21, count 2 2006.286.03:09:37.36#ibcon#about to write, iclass 21, count 2 2006.286.03:09:37.36#ibcon#wrote, iclass 21, count 2 2006.286.03:09:37.36#ibcon#about to read 3, iclass 21, count 2 2006.286.03:09:37.39#ibcon#read 3, iclass 21, count 2 2006.286.03:09:37.39#ibcon#about to read 4, iclass 21, count 2 2006.286.03:09:37.39#ibcon#read 4, iclass 21, count 2 2006.286.03:09:37.39#ibcon#about to read 5, iclass 21, count 2 2006.286.03:09:37.39#ibcon#read 5, iclass 21, count 2 2006.286.03:09:37.39#ibcon#about to read 6, iclass 21, count 2 2006.286.03:09:37.39#ibcon#read 6, iclass 21, count 2 2006.286.03:09:37.39#ibcon#end of sib2, iclass 21, count 2 2006.286.03:09:37.39#ibcon#*after write, iclass 21, count 2 2006.286.03:09:37.39#ibcon#*before return 0, iclass 21, count 2 2006.286.03:09:37.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:09:37.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:09:37.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.03:09:37.39#ibcon#ireg 7 cls_cnt 0 2006.286.03:09:37.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:09:37.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:09:37.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:09:37.51#ibcon#enter wrdev, iclass 21, count 0 2006.286.03:09:37.51#ibcon#first serial, iclass 21, count 0 2006.286.03:09:37.51#ibcon#enter sib2, iclass 21, count 0 2006.286.03:09:37.51#ibcon#flushed, iclass 21, count 0 2006.286.03:09:37.51#ibcon#about to write, iclass 21, count 0 2006.286.03:09:37.51#ibcon#wrote, iclass 21, count 0 2006.286.03:09:37.51#ibcon#about to read 3, iclass 21, count 0 2006.286.03:09:37.53#ibcon#read 3, iclass 21, count 0 2006.286.03:09:37.53#ibcon#about to read 4, iclass 21, count 0 2006.286.03:09:37.53#ibcon#read 4, iclass 21, count 0 2006.286.03:09:37.53#ibcon#about to read 5, iclass 21, count 0 2006.286.03:09:37.53#ibcon#read 5, iclass 21, count 0 2006.286.03:09:37.53#ibcon#about to read 6, iclass 21, count 0 2006.286.03:09:37.53#ibcon#read 6, iclass 21, count 0 2006.286.03:09:37.53#ibcon#end of sib2, iclass 21, count 0 2006.286.03:09:37.53#ibcon#*mode == 0, iclass 21, count 0 2006.286.03:09:37.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.03:09:37.53#ibcon#[27=USB\r\n] 2006.286.03:09:37.53#ibcon#*before write, iclass 21, count 0 2006.286.03:09:37.53#ibcon#enter sib2, iclass 21, count 0 2006.286.03:09:37.53#ibcon#flushed, iclass 21, count 0 2006.286.03:09:37.53#ibcon#about to write, iclass 21, count 0 2006.286.03:09:37.53#ibcon#wrote, iclass 21, count 0 2006.286.03:09:37.53#ibcon#about to read 3, iclass 21, count 0 2006.286.03:09:37.56#ibcon#read 3, iclass 21, count 0 2006.286.03:09:37.56#ibcon#about to read 4, iclass 21, count 0 2006.286.03:09:37.56#ibcon#read 4, iclass 21, count 0 2006.286.03:09:37.56#ibcon#about to read 5, iclass 21, count 0 2006.286.03:09:37.56#ibcon#read 5, iclass 21, count 0 2006.286.03:09:37.56#ibcon#about to read 6, iclass 21, count 0 2006.286.03:09:37.56#ibcon#read 6, iclass 21, count 0 2006.286.03:09:37.56#ibcon#end of sib2, iclass 21, count 0 2006.286.03:09:37.56#ibcon#*after write, iclass 21, count 0 2006.286.03:09:37.56#ibcon#*before return 0, iclass 21, count 0 2006.286.03:09:37.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:09:37.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:09:37.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.03:09:37.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.03:09:37.56$vck44/vabw=wide 2006.286.03:09:37.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.03:09:37.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.03:09:37.56#ibcon#ireg 8 cls_cnt 0 2006.286.03:09:37.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:09:37.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:09:37.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:09:37.56#ibcon#enter wrdev, iclass 23, count 0 2006.286.03:09:37.56#ibcon#first serial, iclass 23, count 0 2006.286.03:09:37.56#ibcon#enter sib2, iclass 23, count 0 2006.286.03:09:37.56#ibcon#flushed, iclass 23, count 0 2006.286.03:09:37.56#ibcon#about to write, iclass 23, count 0 2006.286.03:09:37.56#ibcon#wrote, iclass 23, count 0 2006.286.03:09:37.56#ibcon#about to read 3, iclass 23, count 0 2006.286.03:09:37.58#ibcon#read 3, iclass 23, count 0 2006.286.03:09:37.58#ibcon#about to read 4, iclass 23, count 0 2006.286.03:09:37.58#ibcon#read 4, iclass 23, count 0 2006.286.03:09:37.58#ibcon#about to read 5, iclass 23, count 0 2006.286.03:09:37.58#ibcon#read 5, iclass 23, count 0 2006.286.03:09:37.58#ibcon#about to read 6, iclass 23, count 0 2006.286.03:09:37.58#ibcon#read 6, iclass 23, count 0 2006.286.03:09:37.58#ibcon#end of sib2, iclass 23, count 0 2006.286.03:09:37.58#ibcon#*mode == 0, iclass 23, count 0 2006.286.03:09:37.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.03:09:37.58#ibcon#[25=BW32\r\n] 2006.286.03:09:37.58#ibcon#*before write, iclass 23, count 0 2006.286.03:09:37.58#ibcon#enter sib2, iclass 23, count 0 2006.286.03:09:37.58#ibcon#flushed, iclass 23, count 0 2006.286.03:09:37.58#ibcon#about to write, iclass 23, count 0 2006.286.03:09:37.58#ibcon#wrote, iclass 23, count 0 2006.286.03:09:37.58#ibcon#about to read 3, iclass 23, count 0 2006.286.03:09:37.61#ibcon#read 3, iclass 23, count 0 2006.286.03:09:37.61#ibcon#about to read 4, iclass 23, count 0 2006.286.03:09:37.61#ibcon#read 4, iclass 23, count 0 2006.286.03:09:37.61#ibcon#about to read 5, iclass 23, count 0 2006.286.03:09:37.61#ibcon#read 5, iclass 23, count 0 2006.286.03:09:37.61#ibcon#about to read 6, iclass 23, count 0 2006.286.03:09:37.61#ibcon#read 6, iclass 23, count 0 2006.286.03:09:37.61#ibcon#end of sib2, iclass 23, count 0 2006.286.03:09:37.61#ibcon#*after write, iclass 23, count 0 2006.286.03:09:37.61#ibcon#*before return 0, iclass 23, count 0 2006.286.03:09:37.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:09:37.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:09:37.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.03:09:37.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.03:09:37.61$vck44/vbbw=wide 2006.286.03:09:37.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.03:09:37.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.03:09:37.61#ibcon#ireg 8 cls_cnt 0 2006.286.03:09:37.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:09:37.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:09:37.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:09:37.68#ibcon#enter wrdev, iclass 25, count 0 2006.286.03:09:37.68#ibcon#first serial, iclass 25, count 0 2006.286.03:09:37.68#ibcon#enter sib2, iclass 25, count 0 2006.286.03:09:37.68#ibcon#flushed, iclass 25, count 0 2006.286.03:09:37.68#ibcon#about to write, iclass 25, count 0 2006.286.03:09:37.68#ibcon#wrote, iclass 25, count 0 2006.286.03:09:37.68#ibcon#about to read 3, iclass 25, count 0 2006.286.03:09:37.70#ibcon#read 3, iclass 25, count 0 2006.286.03:09:37.70#ibcon#about to read 4, iclass 25, count 0 2006.286.03:09:37.70#ibcon#read 4, iclass 25, count 0 2006.286.03:09:37.70#ibcon#about to read 5, iclass 25, count 0 2006.286.03:09:37.70#ibcon#read 5, iclass 25, count 0 2006.286.03:09:37.70#ibcon#about to read 6, iclass 25, count 0 2006.286.03:09:37.70#ibcon#read 6, iclass 25, count 0 2006.286.03:09:37.70#ibcon#end of sib2, iclass 25, count 0 2006.286.03:09:37.70#ibcon#*mode == 0, iclass 25, count 0 2006.286.03:09:37.70#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.03:09:37.70#ibcon#[27=BW32\r\n] 2006.286.03:09:37.70#ibcon#*before write, iclass 25, count 0 2006.286.03:09:37.70#ibcon#enter sib2, iclass 25, count 0 2006.286.03:09:37.70#ibcon#flushed, iclass 25, count 0 2006.286.03:09:37.70#ibcon#about to write, iclass 25, count 0 2006.286.03:09:37.70#ibcon#wrote, iclass 25, count 0 2006.286.03:09:37.70#ibcon#about to read 3, iclass 25, count 0 2006.286.03:09:37.73#ibcon#read 3, iclass 25, count 0 2006.286.03:09:37.73#ibcon#about to read 4, iclass 25, count 0 2006.286.03:09:37.73#ibcon#read 4, iclass 25, count 0 2006.286.03:09:37.73#ibcon#about to read 5, iclass 25, count 0 2006.286.03:09:37.73#ibcon#read 5, iclass 25, count 0 2006.286.03:09:37.73#ibcon#about to read 6, iclass 25, count 0 2006.286.03:09:37.73#ibcon#read 6, iclass 25, count 0 2006.286.03:09:37.73#ibcon#end of sib2, iclass 25, count 0 2006.286.03:09:37.73#ibcon#*after write, iclass 25, count 0 2006.286.03:09:37.73#ibcon#*before return 0, iclass 25, count 0 2006.286.03:09:37.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:09:37.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:09:37.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.03:09:37.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.03:09:37.73$setupk4/ifdk4 2006.286.03:09:37.73$ifdk4/lo= 2006.286.03:09:37.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.03:09:37.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.03:09:37.73$ifdk4/patch= 2006.286.03:09:37.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.03:09:37.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.03:09:37.73$setupk4/!*+20s 2006.286.03:09:43.34#abcon#<5=/04 2.9 5.9 21.69 781015.3\r\n> 2006.286.03:09:43.36#abcon#{5=INTERFACE CLEAR} 2006.286.03:09:43.42#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:09:51.33$setupk4/"tpicd 2006.286.03:09:51.33$setupk4/echo=off 2006.286.03:09:51.33$setupk4/xlog=off 2006.286.03:09:51.33:!2006.286.03:10:56 2006.286.03:09:52.14#trakl#Source acquired 2006.286.03:09:52.14#flagr#flagr/antenna,acquired 2006.286.03:10:56.00:preob 2006.286.03:10:56.14/onsource/TRACKING 2006.286.03:10:56.14:!2006.286.03:11:06 2006.286.03:11:06.00:"tape 2006.286.03:11:06.00:"st=record 2006.286.03:11:06.00:data_valid=on 2006.286.03:11:06.00:midob 2006.286.03:11:07.14/onsource/TRACKING 2006.286.03:11:07.14/wx/21.69,1015.3,79 2006.286.03:11:07.19/cable/+6.4971E-03 2006.286.03:11:08.28/va/01,07,usb,yes,32,34 2006.286.03:11:08.28/va/02,06,usb,yes,32,32 2006.286.03:11:08.28/va/03,07,usb,yes,31,33 2006.286.03:11:08.28/va/04,06,usb,yes,33,34 2006.286.03:11:08.28/va/05,03,usb,yes,32,32 2006.286.03:11:08.28/va/06,04,usb,yes,29,28 2006.286.03:11:08.28/va/07,04,usb,yes,29,30 2006.286.03:11:08.28/va/08,03,usb,yes,30,37 2006.286.03:11:08.51/valo/01,524.99,yes,locked 2006.286.03:11:08.51/valo/02,534.99,yes,locked 2006.286.03:11:08.51/valo/03,564.99,yes,locked 2006.286.03:11:08.51/valo/04,624.99,yes,locked 2006.286.03:11:08.51/valo/05,734.99,yes,locked 2006.286.03:11:08.51/valo/06,814.99,yes,locked 2006.286.03:11:08.51/valo/07,864.99,yes,locked 2006.286.03:11:08.51/valo/08,884.99,yes,locked 2006.286.03:11:09.60/vb/01,04,usb,yes,30,28 2006.286.03:11:09.60/vb/02,05,usb,yes,29,29 2006.286.03:11:09.60/vb/03,04,usb,yes,30,33 2006.286.03:11:09.60/vb/04,05,usb,yes,30,29 2006.286.03:11:09.60/vb/05,04,usb,yes,26,29 2006.286.03:11:09.60/vb/06,03,usb,yes,38,33 2006.286.03:11:09.60/vb/07,04,usb,yes,30,30 2006.286.03:11:09.60/vb/08,04,usb,yes,28,31 2006.286.03:11:09.83/vblo/01,629.99,yes,locked 2006.286.03:11:09.83/vblo/02,634.99,yes,locked 2006.286.03:11:09.83/vblo/03,649.99,yes,locked 2006.286.03:11:09.83/vblo/04,679.99,yes,locked 2006.286.03:11:09.83/vblo/05,709.99,yes,locked 2006.286.03:11:09.83/vblo/06,719.99,yes,locked 2006.286.03:11:09.83/vblo/07,734.99,yes,locked 2006.286.03:11:09.83/vblo/08,744.99,yes,locked 2006.286.03:11:09.98/vabw/8 2006.286.03:11:10.13/vbbw/8 2006.286.03:11:10.22/xfe/off,on,12.2 2006.286.03:11:10.59/ifatt/23,28,28,28 2006.286.03:11:11.08/fmout-gps/S +2.71E-07 2006.286.03:11:11.10:!2006.286.03:11:56 2006.286.03:11:56.00:data_valid=off 2006.286.03:11:56.00:"et 2006.286.03:11:56.00:!+3s 2006.286.03:11:59.01:"tape 2006.286.03:11:59.01:postob 2006.286.03:11:59.07/cable/+6.4973E-03 2006.286.03:11:59.07/wx/21.69,1015.3,78 2006.286.03:12:00.08/fmout-gps/S +2.72E-07 2006.286.03:12:00.08:scan_name=286-0316,jd0610,210 2006.286.03:12:00.08:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.286.03:12:01.14#flagr#flagr/antenna,new-source 2006.286.03:12:01.14:checkk5 2006.286.03:12:01.51/chk_autoobs//k5ts1/ autoobs is running! 2006.286.03:12:01.97/chk_autoobs//k5ts2/ autoobs is running! 2006.286.03:12:02.44/chk_autoobs//k5ts3/ autoobs is running! 2006.286.03:12:02.86/chk_autoobs//k5ts4/ autoobs is running! 2006.286.03:12:03.26/chk_obsdata//k5ts1/T2860311??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.03:12:03.82/chk_obsdata//k5ts2/T2860311??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.03:12:04.25/chk_obsdata//k5ts3/T2860311??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.03:12:04.73/chk_obsdata//k5ts4/T2860311??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.03:12:05.83/k5log//k5ts1_log_newline 2006.286.03:12:06.66/k5log//k5ts2_log_newline 2006.286.03:12:07.82/k5log//k5ts3_log_newline 2006.286.03:12:08.83/k5log//k5ts4_log_newline 2006.286.03:12:08.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.03:12:08.85:setupk4=1 2006.286.03:12:08.85$setupk4/echo=on 2006.286.03:12:08.85$setupk4/pcalon 2006.286.03:12:08.85$pcalon/"no phase cal control is implemented here 2006.286.03:12:08.85$setupk4/"tpicd=stop 2006.286.03:12:08.85$setupk4/"rec=synch_on 2006.286.03:12:08.85$setupk4/"rec_mode=128 2006.286.03:12:08.85$setupk4/!* 2006.286.03:12:08.85$setupk4/recpk4 2006.286.03:12:08.85$recpk4/recpatch= 2006.286.03:12:08.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.03:12:08.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.03:12:08.86$setupk4/vck44 2006.286.03:12:08.86$vck44/valo=1,524.99 2006.286.03:12:08.86#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.03:12:08.86#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.03:12:08.86#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:08.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:12:08.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:12:08.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:12:08.86#ibcon#enter wrdev, iclass 18, count 0 2006.286.03:12:08.86#ibcon#first serial, iclass 18, count 0 2006.286.03:12:08.86#ibcon#enter sib2, iclass 18, count 0 2006.286.03:12:08.86#ibcon#flushed, iclass 18, count 0 2006.286.03:12:08.86#ibcon#about to write, iclass 18, count 0 2006.286.03:12:08.86#ibcon#wrote, iclass 18, count 0 2006.286.03:12:08.86#ibcon#about to read 3, iclass 18, count 0 2006.286.03:12:08.88#ibcon#read 3, iclass 18, count 0 2006.286.03:12:08.88#ibcon#about to read 4, iclass 18, count 0 2006.286.03:12:08.88#ibcon#read 4, iclass 18, count 0 2006.286.03:12:08.88#ibcon#about to read 5, iclass 18, count 0 2006.286.03:12:08.88#ibcon#read 5, iclass 18, count 0 2006.286.03:12:08.88#ibcon#about to read 6, iclass 18, count 0 2006.286.03:12:08.88#ibcon#read 6, iclass 18, count 0 2006.286.03:12:08.88#ibcon#end of sib2, iclass 18, count 0 2006.286.03:12:08.88#ibcon#*mode == 0, iclass 18, count 0 2006.286.03:12:08.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.03:12:08.88#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.03:12:08.88#ibcon#*before write, iclass 18, count 0 2006.286.03:12:08.88#ibcon#enter sib2, iclass 18, count 0 2006.286.03:12:08.88#ibcon#flushed, iclass 18, count 0 2006.286.03:12:08.88#ibcon#about to write, iclass 18, count 0 2006.286.03:12:08.88#ibcon#wrote, iclass 18, count 0 2006.286.03:12:08.88#ibcon#about to read 3, iclass 18, count 0 2006.286.03:12:08.93#ibcon#read 3, iclass 18, count 0 2006.286.03:12:08.93#ibcon#about to read 4, iclass 18, count 0 2006.286.03:12:08.93#ibcon#read 4, iclass 18, count 0 2006.286.03:12:08.93#ibcon#about to read 5, iclass 18, count 0 2006.286.03:12:08.93#ibcon#read 5, iclass 18, count 0 2006.286.03:12:08.93#ibcon#about to read 6, iclass 18, count 0 2006.286.03:12:08.93#ibcon#read 6, iclass 18, count 0 2006.286.03:12:08.93#ibcon#end of sib2, iclass 18, count 0 2006.286.03:12:08.93#ibcon#*after write, iclass 18, count 0 2006.286.03:12:08.93#ibcon#*before return 0, iclass 18, count 0 2006.286.03:12:08.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:12:08.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:12:08.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.03:12:08.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.03:12:08.93$vck44/va=1,7 2006.286.03:12:08.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.03:12:08.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.03:12:08.93#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:08.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:12:08.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:12:08.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:12:08.93#ibcon#enter wrdev, iclass 20, count 2 2006.286.03:12:08.93#ibcon#first serial, iclass 20, count 2 2006.286.03:12:08.93#ibcon#enter sib2, iclass 20, count 2 2006.286.03:12:08.93#ibcon#flushed, iclass 20, count 2 2006.286.03:12:08.93#ibcon#about to write, iclass 20, count 2 2006.286.03:12:08.93#ibcon#wrote, iclass 20, count 2 2006.286.03:12:08.93#ibcon#about to read 3, iclass 20, count 2 2006.286.03:12:08.95#ibcon#read 3, iclass 20, count 2 2006.286.03:12:08.95#ibcon#about to read 4, iclass 20, count 2 2006.286.03:12:08.95#ibcon#read 4, iclass 20, count 2 2006.286.03:12:08.95#ibcon#about to read 5, iclass 20, count 2 2006.286.03:12:08.95#ibcon#read 5, iclass 20, count 2 2006.286.03:12:08.95#ibcon#about to read 6, iclass 20, count 2 2006.286.03:12:08.95#ibcon#read 6, iclass 20, count 2 2006.286.03:12:08.95#ibcon#end of sib2, iclass 20, count 2 2006.286.03:12:08.95#ibcon#*mode == 0, iclass 20, count 2 2006.286.03:12:08.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.03:12:08.95#ibcon#[25=AT01-07\r\n] 2006.286.03:12:08.95#ibcon#*before write, iclass 20, count 2 2006.286.03:12:08.95#ibcon#enter sib2, iclass 20, count 2 2006.286.03:12:08.95#ibcon#flushed, iclass 20, count 2 2006.286.03:12:08.95#ibcon#about to write, iclass 20, count 2 2006.286.03:12:08.95#ibcon#wrote, iclass 20, count 2 2006.286.03:12:08.95#ibcon#about to read 3, iclass 20, count 2 2006.286.03:12:08.98#ibcon#read 3, iclass 20, count 2 2006.286.03:12:08.98#ibcon#about to read 4, iclass 20, count 2 2006.286.03:12:08.98#ibcon#read 4, iclass 20, count 2 2006.286.03:12:08.98#ibcon#about to read 5, iclass 20, count 2 2006.286.03:12:08.98#ibcon#read 5, iclass 20, count 2 2006.286.03:12:08.98#ibcon#about to read 6, iclass 20, count 2 2006.286.03:12:08.98#ibcon#read 6, iclass 20, count 2 2006.286.03:12:08.98#ibcon#end of sib2, iclass 20, count 2 2006.286.03:12:08.98#ibcon#*after write, iclass 20, count 2 2006.286.03:12:08.98#ibcon#*before return 0, iclass 20, count 2 2006.286.03:12:08.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:12:08.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:12:08.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.03:12:08.98#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:08.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:12:09.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:12:09.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:12:09.10#ibcon#enter wrdev, iclass 20, count 0 2006.286.03:12:09.10#ibcon#first serial, iclass 20, count 0 2006.286.03:12:09.10#ibcon#enter sib2, iclass 20, count 0 2006.286.03:12:09.10#ibcon#flushed, iclass 20, count 0 2006.286.03:12:09.10#ibcon#about to write, iclass 20, count 0 2006.286.03:12:09.10#ibcon#wrote, iclass 20, count 0 2006.286.03:12:09.10#ibcon#about to read 3, iclass 20, count 0 2006.286.03:12:09.12#ibcon#read 3, iclass 20, count 0 2006.286.03:12:09.12#ibcon#about to read 4, iclass 20, count 0 2006.286.03:12:09.12#ibcon#read 4, iclass 20, count 0 2006.286.03:12:09.12#ibcon#about to read 5, iclass 20, count 0 2006.286.03:12:09.12#ibcon#read 5, iclass 20, count 0 2006.286.03:12:09.12#ibcon#about to read 6, iclass 20, count 0 2006.286.03:12:09.12#ibcon#read 6, iclass 20, count 0 2006.286.03:12:09.12#ibcon#end of sib2, iclass 20, count 0 2006.286.03:12:09.12#ibcon#*mode == 0, iclass 20, count 0 2006.286.03:12:09.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.03:12:09.12#ibcon#[25=USB\r\n] 2006.286.03:12:09.12#ibcon#*before write, iclass 20, count 0 2006.286.03:12:09.12#ibcon#enter sib2, iclass 20, count 0 2006.286.03:12:09.12#ibcon#flushed, iclass 20, count 0 2006.286.03:12:09.12#ibcon#about to write, iclass 20, count 0 2006.286.03:12:09.12#ibcon#wrote, iclass 20, count 0 2006.286.03:12:09.12#ibcon#about to read 3, iclass 20, count 0 2006.286.03:12:09.15#ibcon#read 3, iclass 20, count 0 2006.286.03:12:09.15#ibcon#about to read 4, iclass 20, count 0 2006.286.03:12:09.15#ibcon#read 4, iclass 20, count 0 2006.286.03:12:09.15#ibcon#about to read 5, iclass 20, count 0 2006.286.03:12:09.15#ibcon#read 5, iclass 20, count 0 2006.286.03:12:09.15#ibcon#about to read 6, iclass 20, count 0 2006.286.03:12:09.15#ibcon#read 6, iclass 20, count 0 2006.286.03:12:09.15#ibcon#end of sib2, iclass 20, count 0 2006.286.03:12:09.15#ibcon#*after write, iclass 20, count 0 2006.286.03:12:09.15#ibcon#*before return 0, iclass 20, count 0 2006.286.03:12:09.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:12:09.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:12:09.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.03:12:09.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.03:12:09.15$vck44/valo=2,534.99 2006.286.03:12:09.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.03:12:09.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.03:12:09.15#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:09.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:12:09.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:12:09.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:12:09.15#ibcon#enter wrdev, iclass 22, count 0 2006.286.03:12:09.15#ibcon#first serial, iclass 22, count 0 2006.286.03:12:09.15#ibcon#enter sib2, iclass 22, count 0 2006.286.03:12:09.15#ibcon#flushed, iclass 22, count 0 2006.286.03:12:09.15#ibcon#about to write, iclass 22, count 0 2006.286.03:12:09.15#ibcon#wrote, iclass 22, count 0 2006.286.03:12:09.15#ibcon#about to read 3, iclass 22, count 0 2006.286.03:12:09.17#ibcon#read 3, iclass 22, count 0 2006.286.03:12:09.17#ibcon#about to read 4, iclass 22, count 0 2006.286.03:12:09.17#ibcon#read 4, iclass 22, count 0 2006.286.03:12:09.17#ibcon#about to read 5, iclass 22, count 0 2006.286.03:12:09.17#ibcon#read 5, iclass 22, count 0 2006.286.03:12:09.17#ibcon#about to read 6, iclass 22, count 0 2006.286.03:12:09.17#ibcon#read 6, iclass 22, count 0 2006.286.03:12:09.17#ibcon#end of sib2, iclass 22, count 0 2006.286.03:12:09.17#ibcon#*mode == 0, iclass 22, count 0 2006.286.03:12:09.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.03:12:09.17#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.03:12:09.17#ibcon#*before write, iclass 22, count 0 2006.286.03:12:09.17#ibcon#enter sib2, iclass 22, count 0 2006.286.03:12:09.17#ibcon#flushed, iclass 22, count 0 2006.286.03:12:09.17#ibcon#about to write, iclass 22, count 0 2006.286.03:12:09.17#ibcon#wrote, iclass 22, count 0 2006.286.03:12:09.17#ibcon#about to read 3, iclass 22, count 0 2006.286.03:12:09.21#ibcon#read 3, iclass 22, count 0 2006.286.03:12:09.21#ibcon#about to read 4, iclass 22, count 0 2006.286.03:12:09.21#ibcon#read 4, iclass 22, count 0 2006.286.03:12:09.21#ibcon#about to read 5, iclass 22, count 0 2006.286.03:12:09.21#ibcon#read 5, iclass 22, count 0 2006.286.03:12:09.21#ibcon#about to read 6, iclass 22, count 0 2006.286.03:12:09.21#ibcon#read 6, iclass 22, count 0 2006.286.03:12:09.21#ibcon#end of sib2, iclass 22, count 0 2006.286.03:12:09.21#ibcon#*after write, iclass 22, count 0 2006.286.03:12:09.21#ibcon#*before return 0, iclass 22, count 0 2006.286.03:12:09.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:12:09.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:12:09.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.03:12:09.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.03:12:09.21$vck44/va=2,6 2006.286.03:12:09.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.03:12:09.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.03:12:09.21#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:09.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:12:09.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:12:09.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:12:09.27#ibcon#enter wrdev, iclass 24, count 2 2006.286.03:12:09.27#ibcon#first serial, iclass 24, count 2 2006.286.03:12:09.27#ibcon#enter sib2, iclass 24, count 2 2006.286.03:12:09.27#ibcon#flushed, iclass 24, count 2 2006.286.03:12:09.27#ibcon#about to write, iclass 24, count 2 2006.286.03:12:09.27#ibcon#wrote, iclass 24, count 2 2006.286.03:12:09.27#ibcon#about to read 3, iclass 24, count 2 2006.286.03:12:09.29#ibcon#read 3, iclass 24, count 2 2006.286.03:12:09.29#ibcon#about to read 4, iclass 24, count 2 2006.286.03:12:09.29#ibcon#read 4, iclass 24, count 2 2006.286.03:12:09.29#ibcon#about to read 5, iclass 24, count 2 2006.286.03:12:09.29#ibcon#read 5, iclass 24, count 2 2006.286.03:12:09.29#ibcon#about to read 6, iclass 24, count 2 2006.286.03:12:09.29#ibcon#read 6, iclass 24, count 2 2006.286.03:12:09.29#ibcon#end of sib2, iclass 24, count 2 2006.286.03:12:09.29#ibcon#*mode == 0, iclass 24, count 2 2006.286.03:12:09.29#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.03:12:09.29#ibcon#[25=AT02-06\r\n] 2006.286.03:12:09.29#ibcon#*before write, iclass 24, count 2 2006.286.03:12:09.29#ibcon#enter sib2, iclass 24, count 2 2006.286.03:12:09.29#ibcon#flushed, iclass 24, count 2 2006.286.03:12:09.29#ibcon#about to write, iclass 24, count 2 2006.286.03:12:09.29#ibcon#wrote, iclass 24, count 2 2006.286.03:12:09.29#ibcon#about to read 3, iclass 24, count 2 2006.286.03:12:09.32#ibcon#read 3, iclass 24, count 2 2006.286.03:12:09.32#ibcon#about to read 4, iclass 24, count 2 2006.286.03:12:09.32#ibcon#read 4, iclass 24, count 2 2006.286.03:12:09.32#ibcon#about to read 5, iclass 24, count 2 2006.286.03:12:09.32#ibcon#read 5, iclass 24, count 2 2006.286.03:12:09.32#ibcon#about to read 6, iclass 24, count 2 2006.286.03:12:09.32#ibcon#read 6, iclass 24, count 2 2006.286.03:12:09.32#ibcon#end of sib2, iclass 24, count 2 2006.286.03:12:09.32#ibcon#*after write, iclass 24, count 2 2006.286.03:12:09.32#ibcon#*before return 0, iclass 24, count 2 2006.286.03:12:09.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:12:09.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:12:09.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.03:12:09.32#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:09.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:12:09.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:12:09.97#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:12:09.97#ibcon#enter wrdev, iclass 24, count 0 2006.286.03:12:09.97#ibcon#first serial, iclass 24, count 0 2006.286.03:12:09.97#ibcon#enter sib2, iclass 24, count 0 2006.286.03:12:09.97#ibcon#flushed, iclass 24, count 0 2006.286.03:12:09.97#ibcon#about to write, iclass 24, count 0 2006.286.03:12:09.97#ibcon#wrote, iclass 24, count 0 2006.286.03:12:09.97#ibcon#about to read 3, iclass 24, count 0 2006.286.03:12:09.99#ibcon#read 3, iclass 24, count 0 2006.286.03:12:09.99#ibcon#about to read 4, iclass 24, count 0 2006.286.03:12:09.99#ibcon#read 4, iclass 24, count 0 2006.286.03:12:09.99#ibcon#about to read 5, iclass 24, count 0 2006.286.03:12:09.99#ibcon#read 5, iclass 24, count 0 2006.286.03:12:09.99#ibcon#about to read 6, iclass 24, count 0 2006.286.03:12:09.99#ibcon#read 6, iclass 24, count 0 2006.286.03:12:09.99#ibcon#end of sib2, iclass 24, count 0 2006.286.03:12:09.99#ibcon#*mode == 0, iclass 24, count 0 2006.286.03:12:09.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.03:12:09.99#ibcon#[25=USB\r\n] 2006.286.03:12:09.99#ibcon#*before write, iclass 24, count 0 2006.286.03:12:09.99#ibcon#enter sib2, iclass 24, count 0 2006.286.03:12:09.99#ibcon#flushed, iclass 24, count 0 2006.286.03:12:09.99#ibcon#about to write, iclass 24, count 0 2006.286.03:12:09.99#ibcon#wrote, iclass 24, count 0 2006.286.03:12:09.99#ibcon#about to read 3, iclass 24, count 0 2006.286.03:12:10.02#ibcon#read 3, iclass 24, count 0 2006.286.03:12:10.02#ibcon#about to read 4, iclass 24, count 0 2006.286.03:12:10.02#ibcon#read 4, iclass 24, count 0 2006.286.03:12:10.02#ibcon#about to read 5, iclass 24, count 0 2006.286.03:12:10.02#ibcon#read 5, iclass 24, count 0 2006.286.03:12:10.02#ibcon#about to read 6, iclass 24, count 0 2006.286.03:12:10.02#ibcon#read 6, iclass 24, count 0 2006.286.03:12:10.02#ibcon#end of sib2, iclass 24, count 0 2006.286.03:12:10.02#ibcon#*after write, iclass 24, count 0 2006.286.03:12:10.02#ibcon#*before return 0, iclass 24, count 0 2006.286.03:12:10.02#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:12:10.02#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:12:10.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.03:12:10.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.03:12:10.02$vck44/valo=3,564.99 2006.286.03:12:10.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.03:12:10.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.03:12:10.02#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:10.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:12:10.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:12:10.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:12:10.02#ibcon#enter wrdev, iclass 26, count 0 2006.286.03:12:10.02#ibcon#first serial, iclass 26, count 0 2006.286.03:12:10.02#ibcon#enter sib2, iclass 26, count 0 2006.286.03:12:10.02#ibcon#flushed, iclass 26, count 0 2006.286.03:12:10.02#ibcon#about to write, iclass 26, count 0 2006.286.03:12:10.02#ibcon#wrote, iclass 26, count 0 2006.286.03:12:10.02#ibcon#about to read 3, iclass 26, count 0 2006.286.03:12:10.04#ibcon#read 3, iclass 26, count 0 2006.286.03:12:10.04#ibcon#about to read 4, iclass 26, count 0 2006.286.03:12:10.04#ibcon#read 4, iclass 26, count 0 2006.286.03:12:10.04#ibcon#about to read 5, iclass 26, count 0 2006.286.03:12:10.04#ibcon#read 5, iclass 26, count 0 2006.286.03:12:10.04#ibcon#about to read 6, iclass 26, count 0 2006.286.03:12:10.04#ibcon#read 6, iclass 26, count 0 2006.286.03:12:10.04#ibcon#end of sib2, iclass 26, count 0 2006.286.03:12:10.04#ibcon#*mode == 0, iclass 26, count 0 2006.286.03:12:10.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.03:12:10.04#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.03:12:10.04#ibcon#*before write, iclass 26, count 0 2006.286.03:12:10.04#ibcon#enter sib2, iclass 26, count 0 2006.286.03:12:10.04#ibcon#flushed, iclass 26, count 0 2006.286.03:12:10.04#ibcon#about to write, iclass 26, count 0 2006.286.03:12:10.04#ibcon#wrote, iclass 26, count 0 2006.286.03:12:10.04#ibcon#about to read 3, iclass 26, count 0 2006.286.03:12:10.08#ibcon#read 3, iclass 26, count 0 2006.286.03:12:10.08#ibcon#about to read 4, iclass 26, count 0 2006.286.03:12:10.08#ibcon#read 4, iclass 26, count 0 2006.286.03:12:10.08#ibcon#about to read 5, iclass 26, count 0 2006.286.03:12:10.08#ibcon#read 5, iclass 26, count 0 2006.286.03:12:10.08#ibcon#about to read 6, iclass 26, count 0 2006.286.03:12:10.08#ibcon#read 6, iclass 26, count 0 2006.286.03:12:10.08#ibcon#end of sib2, iclass 26, count 0 2006.286.03:12:10.08#ibcon#*after write, iclass 26, count 0 2006.286.03:12:10.08#ibcon#*before return 0, iclass 26, count 0 2006.286.03:12:10.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:12:10.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:12:10.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.03:12:10.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.03:12:10.08$vck44/va=3,7 2006.286.03:12:10.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.03:12:10.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.03:12:10.08#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:10.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:12:10.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:12:10.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:12:10.14#ibcon#enter wrdev, iclass 28, count 2 2006.286.03:12:10.14#ibcon#first serial, iclass 28, count 2 2006.286.03:12:10.14#ibcon#enter sib2, iclass 28, count 2 2006.286.03:12:10.14#ibcon#flushed, iclass 28, count 2 2006.286.03:12:10.14#ibcon#about to write, iclass 28, count 2 2006.286.03:12:10.14#ibcon#wrote, iclass 28, count 2 2006.286.03:12:10.14#ibcon#about to read 3, iclass 28, count 2 2006.286.03:12:10.16#ibcon#read 3, iclass 28, count 2 2006.286.03:12:10.16#ibcon#about to read 4, iclass 28, count 2 2006.286.03:12:10.16#ibcon#read 4, iclass 28, count 2 2006.286.03:12:10.16#ibcon#about to read 5, iclass 28, count 2 2006.286.03:12:10.16#ibcon#read 5, iclass 28, count 2 2006.286.03:12:10.16#ibcon#about to read 6, iclass 28, count 2 2006.286.03:12:10.16#ibcon#read 6, iclass 28, count 2 2006.286.03:12:10.16#ibcon#end of sib2, iclass 28, count 2 2006.286.03:12:10.16#ibcon#*mode == 0, iclass 28, count 2 2006.286.03:12:10.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.03:12:10.16#ibcon#[25=AT03-07\r\n] 2006.286.03:12:10.16#ibcon#*before write, iclass 28, count 2 2006.286.03:12:10.16#ibcon#enter sib2, iclass 28, count 2 2006.286.03:12:10.16#ibcon#flushed, iclass 28, count 2 2006.286.03:12:10.16#ibcon#about to write, iclass 28, count 2 2006.286.03:12:10.16#ibcon#wrote, iclass 28, count 2 2006.286.03:12:10.16#ibcon#about to read 3, iclass 28, count 2 2006.286.03:12:10.19#ibcon#read 3, iclass 28, count 2 2006.286.03:12:10.19#ibcon#about to read 4, iclass 28, count 2 2006.286.03:12:10.19#ibcon#read 4, iclass 28, count 2 2006.286.03:12:10.19#ibcon#about to read 5, iclass 28, count 2 2006.286.03:12:10.19#ibcon#read 5, iclass 28, count 2 2006.286.03:12:10.19#ibcon#about to read 6, iclass 28, count 2 2006.286.03:12:10.19#ibcon#read 6, iclass 28, count 2 2006.286.03:12:10.19#ibcon#end of sib2, iclass 28, count 2 2006.286.03:12:10.19#ibcon#*after write, iclass 28, count 2 2006.286.03:12:10.19#ibcon#*before return 0, iclass 28, count 2 2006.286.03:12:10.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:12:10.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:12:10.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.03:12:10.19#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:10.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:12:10.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:12:10.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:12:10.31#ibcon#enter wrdev, iclass 28, count 0 2006.286.03:12:10.31#ibcon#first serial, iclass 28, count 0 2006.286.03:12:10.31#ibcon#enter sib2, iclass 28, count 0 2006.286.03:12:10.31#ibcon#flushed, iclass 28, count 0 2006.286.03:12:10.31#ibcon#about to write, iclass 28, count 0 2006.286.03:12:10.31#ibcon#wrote, iclass 28, count 0 2006.286.03:12:10.31#ibcon#about to read 3, iclass 28, count 0 2006.286.03:12:10.33#ibcon#read 3, iclass 28, count 0 2006.286.03:12:10.33#ibcon#about to read 4, iclass 28, count 0 2006.286.03:12:10.33#ibcon#read 4, iclass 28, count 0 2006.286.03:12:10.40#ibcon#about to read 5, iclass 28, count 0 2006.286.03:12:10.40#ibcon#read 5, iclass 28, count 0 2006.286.03:12:10.40#ibcon#about to read 6, iclass 28, count 0 2006.286.03:12:10.40#ibcon#read 6, iclass 28, count 0 2006.286.03:12:10.40#ibcon#end of sib2, iclass 28, count 0 2006.286.03:12:10.40#ibcon#*mode == 0, iclass 28, count 0 2006.286.03:12:10.40#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.03:12:10.40#ibcon#[25=USB\r\n] 2006.286.03:12:10.40#ibcon#*before write, iclass 28, count 0 2006.286.03:12:10.40#ibcon#enter sib2, iclass 28, count 0 2006.286.03:12:10.40#ibcon#flushed, iclass 28, count 0 2006.286.03:12:10.40#ibcon#about to write, iclass 28, count 0 2006.286.03:12:10.40#ibcon#wrote, iclass 28, count 0 2006.286.03:12:10.40#ibcon#about to read 3, iclass 28, count 0 2006.286.03:12:10.44#ibcon#read 3, iclass 28, count 0 2006.286.03:12:10.44#ibcon#about to read 4, iclass 28, count 0 2006.286.03:12:10.44#ibcon#read 4, iclass 28, count 0 2006.286.03:12:10.44#ibcon#about to read 5, iclass 28, count 0 2006.286.03:12:10.44#ibcon#read 5, iclass 28, count 0 2006.286.03:12:10.44#ibcon#about to read 6, iclass 28, count 0 2006.286.03:12:10.44#ibcon#read 6, iclass 28, count 0 2006.286.03:12:10.44#ibcon#end of sib2, iclass 28, count 0 2006.286.03:12:10.44#ibcon#*after write, iclass 28, count 0 2006.286.03:12:10.44#ibcon#*before return 0, iclass 28, count 0 2006.286.03:12:10.44#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:12:10.44#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:12:10.44#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.03:12:10.44#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.03:12:10.44$vck44/valo=4,624.99 2006.286.03:12:10.44#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.03:12:10.44#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.03:12:10.44#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:10.44#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:12:10.44#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:12:10.44#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:12:10.44#ibcon#enter wrdev, iclass 30, count 0 2006.286.03:12:10.44#ibcon#first serial, iclass 30, count 0 2006.286.03:12:10.44#ibcon#enter sib2, iclass 30, count 0 2006.286.03:12:10.44#ibcon#flushed, iclass 30, count 0 2006.286.03:12:10.44#ibcon#about to write, iclass 30, count 0 2006.286.03:12:10.44#ibcon#wrote, iclass 30, count 0 2006.286.03:12:10.44#ibcon#about to read 3, iclass 30, count 0 2006.286.03:12:10.46#ibcon#read 3, iclass 30, count 0 2006.286.03:12:10.46#ibcon#about to read 4, iclass 30, count 0 2006.286.03:12:10.46#ibcon#read 4, iclass 30, count 0 2006.286.03:12:10.46#ibcon#about to read 5, iclass 30, count 0 2006.286.03:12:10.46#ibcon#read 5, iclass 30, count 0 2006.286.03:12:10.46#ibcon#about to read 6, iclass 30, count 0 2006.286.03:12:10.46#ibcon#read 6, iclass 30, count 0 2006.286.03:12:10.46#ibcon#end of sib2, iclass 30, count 0 2006.286.03:12:10.46#ibcon#*mode == 0, iclass 30, count 0 2006.286.03:12:10.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.03:12:10.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.03:12:10.46#ibcon#*before write, iclass 30, count 0 2006.286.03:12:10.46#ibcon#enter sib2, iclass 30, count 0 2006.286.03:12:10.46#ibcon#flushed, iclass 30, count 0 2006.286.03:12:10.46#ibcon#about to write, iclass 30, count 0 2006.286.03:12:10.46#ibcon#wrote, iclass 30, count 0 2006.286.03:12:10.46#ibcon#about to read 3, iclass 30, count 0 2006.286.03:12:10.50#ibcon#read 3, iclass 30, count 0 2006.286.03:12:10.50#ibcon#about to read 4, iclass 30, count 0 2006.286.03:12:10.50#ibcon#read 4, iclass 30, count 0 2006.286.03:12:10.50#ibcon#about to read 5, iclass 30, count 0 2006.286.03:12:10.50#ibcon#read 5, iclass 30, count 0 2006.286.03:12:10.50#ibcon#about to read 6, iclass 30, count 0 2006.286.03:12:10.50#ibcon#read 6, iclass 30, count 0 2006.286.03:12:10.50#ibcon#end of sib2, iclass 30, count 0 2006.286.03:12:10.50#ibcon#*after write, iclass 30, count 0 2006.286.03:12:10.50#ibcon#*before return 0, iclass 30, count 0 2006.286.03:12:10.50#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:12:10.50#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:12:10.50#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.03:12:10.50#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.03:12:10.50$vck44/va=4,6 2006.286.03:12:10.50#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.03:12:10.50#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.03:12:10.50#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:10.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:12:10.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:12:10.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:12:10.56#ibcon#enter wrdev, iclass 32, count 2 2006.286.03:12:10.56#ibcon#first serial, iclass 32, count 2 2006.286.03:12:10.56#ibcon#enter sib2, iclass 32, count 2 2006.286.03:12:10.56#ibcon#flushed, iclass 32, count 2 2006.286.03:12:10.56#ibcon#about to write, iclass 32, count 2 2006.286.03:12:10.56#ibcon#wrote, iclass 32, count 2 2006.286.03:12:10.56#ibcon#about to read 3, iclass 32, count 2 2006.286.03:12:10.58#ibcon#read 3, iclass 32, count 2 2006.286.03:12:10.58#ibcon#about to read 4, iclass 32, count 2 2006.286.03:12:10.58#ibcon#read 4, iclass 32, count 2 2006.286.03:12:10.58#ibcon#about to read 5, iclass 32, count 2 2006.286.03:12:10.58#ibcon#read 5, iclass 32, count 2 2006.286.03:12:10.58#ibcon#about to read 6, iclass 32, count 2 2006.286.03:12:10.58#ibcon#read 6, iclass 32, count 2 2006.286.03:12:10.58#ibcon#end of sib2, iclass 32, count 2 2006.286.03:12:10.58#ibcon#*mode == 0, iclass 32, count 2 2006.286.03:12:10.58#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.03:12:10.58#ibcon#[25=AT04-06\r\n] 2006.286.03:12:10.58#ibcon#*before write, iclass 32, count 2 2006.286.03:12:10.58#ibcon#enter sib2, iclass 32, count 2 2006.286.03:12:10.58#ibcon#flushed, iclass 32, count 2 2006.286.03:12:10.58#ibcon#about to write, iclass 32, count 2 2006.286.03:12:10.58#ibcon#wrote, iclass 32, count 2 2006.286.03:12:10.58#ibcon#about to read 3, iclass 32, count 2 2006.286.03:12:10.61#ibcon#read 3, iclass 32, count 2 2006.286.03:12:10.61#ibcon#about to read 4, iclass 32, count 2 2006.286.03:12:10.61#ibcon#read 4, iclass 32, count 2 2006.286.03:12:10.61#ibcon#about to read 5, iclass 32, count 2 2006.286.03:12:10.61#ibcon#read 5, iclass 32, count 2 2006.286.03:12:10.61#ibcon#about to read 6, iclass 32, count 2 2006.286.03:12:10.61#ibcon#read 6, iclass 32, count 2 2006.286.03:12:10.61#ibcon#end of sib2, iclass 32, count 2 2006.286.03:12:10.61#ibcon#*after write, iclass 32, count 2 2006.286.03:12:10.61#ibcon#*before return 0, iclass 32, count 2 2006.286.03:12:10.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:12:10.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:12:10.61#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.03:12:10.61#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:10.61#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:12:10.73#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:12:10.73#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:12:10.73#ibcon#enter wrdev, iclass 32, count 0 2006.286.03:12:10.73#ibcon#first serial, iclass 32, count 0 2006.286.03:12:10.73#ibcon#enter sib2, iclass 32, count 0 2006.286.03:12:10.73#ibcon#flushed, iclass 32, count 0 2006.286.03:12:10.73#ibcon#about to write, iclass 32, count 0 2006.286.03:12:10.73#ibcon#wrote, iclass 32, count 0 2006.286.03:12:10.73#ibcon#about to read 3, iclass 32, count 0 2006.286.03:12:10.75#ibcon#read 3, iclass 32, count 0 2006.286.03:12:10.75#ibcon#about to read 4, iclass 32, count 0 2006.286.03:12:10.75#ibcon#read 4, iclass 32, count 0 2006.286.03:12:10.75#ibcon#about to read 5, iclass 32, count 0 2006.286.03:12:10.75#ibcon#read 5, iclass 32, count 0 2006.286.03:12:10.75#ibcon#about to read 6, iclass 32, count 0 2006.286.03:12:10.75#ibcon#read 6, iclass 32, count 0 2006.286.03:12:10.75#ibcon#end of sib2, iclass 32, count 0 2006.286.03:12:10.75#ibcon#*mode == 0, iclass 32, count 0 2006.286.03:12:10.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.03:12:10.75#ibcon#[25=USB\r\n] 2006.286.03:12:10.75#ibcon#*before write, iclass 32, count 0 2006.286.03:12:10.75#ibcon#enter sib2, iclass 32, count 0 2006.286.03:12:10.75#ibcon#flushed, iclass 32, count 0 2006.286.03:12:10.75#ibcon#about to write, iclass 32, count 0 2006.286.03:12:10.75#ibcon#wrote, iclass 32, count 0 2006.286.03:12:10.75#ibcon#about to read 3, iclass 32, count 0 2006.286.03:12:10.78#ibcon#read 3, iclass 32, count 0 2006.286.03:12:10.78#ibcon#about to read 4, iclass 32, count 0 2006.286.03:12:10.78#ibcon#read 4, iclass 32, count 0 2006.286.03:12:10.78#ibcon#about to read 5, iclass 32, count 0 2006.286.03:12:10.78#ibcon#read 5, iclass 32, count 0 2006.286.03:12:10.78#ibcon#about to read 6, iclass 32, count 0 2006.286.03:12:10.78#ibcon#read 6, iclass 32, count 0 2006.286.03:12:10.78#ibcon#end of sib2, iclass 32, count 0 2006.286.03:12:10.78#ibcon#*after write, iclass 32, count 0 2006.286.03:12:10.78#ibcon#*before return 0, iclass 32, count 0 2006.286.03:12:10.78#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:12:10.78#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:12:10.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.03:12:10.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.03:12:10.78$vck44/valo=5,734.99 2006.286.03:12:10.78#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.03:12:10.78#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.03:12:10.78#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:10.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:12:10.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:12:10.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:12:10.78#ibcon#enter wrdev, iclass 34, count 0 2006.286.03:12:10.78#ibcon#first serial, iclass 34, count 0 2006.286.03:12:10.78#ibcon#enter sib2, iclass 34, count 0 2006.286.03:12:10.78#ibcon#flushed, iclass 34, count 0 2006.286.03:12:10.78#ibcon#about to write, iclass 34, count 0 2006.286.03:12:10.78#ibcon#wrote, iclass 34, count 0 2006.286.03:12:10.78#ibcon#about to read 3, iclass 34, count 0 2006.286.03:12:10.80#ibcon#read 3, iclass 34, count 0 2006.286.03:12:10.80#ibcon#about to read 4, iclass 34, count 0 2006.286.03:12:10.80#ibcon#read 4, iclass 34, count 0 2006.286.03:12:10.80#ibcon#about to read 5, iclass 34, count 0 2006.286.03:12:10.80#ibcon#read 5, iclass 34, count 0 2006.286.03:12:10.80#ibcon#about to read 6, iclass 34, count 0 2006.286.03:12:10.80#ibcon#read 6, iclass 34, count 0 2006.286.03:12:10.80#ibcon#end of sib2, iclass 34, count 0 2006.286.03:12:10.80#ibcon#*mode == 0, iclass 34, count 0 2006.286.03:12:10.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.03:12:10.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.03:12:10.80#ibcon#*before write, iclass 34, count 0 2006.286.03:12:10.80#ibcon#enter sib2, iclass 34, count 0 2006.286.03:12:10.80#ibcon#flushed, iclass 34, count 0 2006.286.03:12:10.80#ibcon#about to write, iclass 34, count 0 2006.286.03:12:10.80#ibcon#wrote, iclass 34, count 0 2006.286.03:12:10.80#ibcon#about to read 3, iclass 34, count 0 2006.286.03:12:10.84#ibcon#read 3, iclass 34, count 0 2006.286.03:12:10.84#ibcon#about to read 4, iclass 34, count 0 2006.286.03:12:10.84#ibcon#read 4, iclass 34, count 0 2006.286.03:12:10.84#ibcon#about to read 5, iclass 34, count 0 2006.286.03:12:10.84#ibcon#read 5, iclass 34, count 0 2006.286.03:12:10.84#ibcon#about to read 6, iclass 34, count 0 2006.286.03:12:10.84#ibcon#read 6, iclass 34, count 0 2006.286.03:12:10.84#ibcon#end of sib2, iclass 34, count 0 2006.286.03:12:10.84#ibcon#*after write, iclass 34, count 0 2006.286.03:12:10.84#ibcon#*before return 0, iclass 34, count 0 2006.286.03:12:10.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:12:10.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:12:10.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.03:12:10.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.03:12:10.84$vck44/va=5,3 2006.286.03:12:10.84#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.03:12:10.84#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.03:12:10.84#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:10.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:12:10.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:12:10.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:12:10.90#ibcon#enter wrdev, iclass 36, count 2 2006.286.03:12:10.90#ibcon#first serial, iclass 36, count 2 2006.286.03:12:10.90#ibcon#enter sib2, iclass 36, count 2 2006.286.03:12:10.90#ibcon#flushed, iclass 36, count 2 2006.286.03:12:10.90#ibcon#about to write, iclass 36, count 2 2006.286.03:12:10.90#ibcon#wrote, iclass 36, count 2 2006.286.03:12:10.90#ibcon#about to read 3, iclass 36, count 2 2006.286.03:12:10.92#ibcon#read 3, iclass 36, count 2 2006.286.03:12:10.92#ibcon#about to read 4, iclass 36, count 2 2006.286.03:12:10.92#ibcon#read 4, iclass 36, count 2 2006.286.03:12:10.92#ibcon#about to read 5, iclass 36, count 2 2006.286.03:12:10.92#ibcon#read 5, iclass 36, count 2 2006.286.03:12:10.92#ibcon#about to read 6, iclass 36, count 2 2006.286.03:12:10.92#ibcon#read 6, iclass 36, count 2 2006.286.03:12:10.92#ibcon#end of sib2, iclass 36, count 2 2006.286.03:12:10.92#ibcon#*mode == 0, iclass 36, count 2 2006.286.03:12:10.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.03:12:10.92#ibcon#[25=AT05-03\r\n] 2006.286.03:12:10.92#ibcon#*before write, iclass 36, count 2 2006.286.03:12:10.92#ibcon#enter sib2, iclass 36, count 2 2006.286.03:12:10.92#ibcon#flushed, iclass 36, count 2 2006.286.03:12:10.92#ibcon#about to write, iclass 36, count 2 2006.286.03:12:10.92#ibcon#wrote, iclass 36, count 2 2006.286.03:12:10.92#ibcon#about to read 3, iclass 36, count 2 2006.286.03:12:10.95#ibcon#read 3, iclass 36, count 2 2006.286.03:12:10.95#ibcon#about to read 4, iclass 36, count 2 2006.286.03:12:10.95#ibcon#read 4, iclass 36, count 2 2006.286.03:12:10.95#ibcon#about to read 5, iclass 36, count 2 2006.286.03:12:10.95#ibcon#read 5, iclass 36, count 2 2006.286.03:12:10.95#ibcon#about to read 6, iclass 36, count 2 2006.286.03:12:10.95#ibcon#read 6, iclass 36, count 2 2006.286.03:12:10.95#ibcon#end of sib2, iclass 36, count 2 2006.286.03:12:10.95#ibcon#*after write, iclass 36, count 2 2006.286.03:12:10.95#ibcon#*before return 0, iclass 36, count 2 2006.286.03:12:10.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:12:10.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:12:10.95#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.03:12:10.95#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:10.95#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:12:11.07#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:12:11.07#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:12:11.07#ibcon#enter wrdev, iclass 36, count 0 2006.286.03:12:11.07#ibcon#first serial, iclass 36, count 0 2006.286.03:12:11.07#ibcon#enter sib2, iclass 36, count 0 2006.286.03:12:11.07#ibcon#flushed, iclass 36, count 0 2006.286.03:12:11.07#ibcon#about to write, iclass 36, count 0 2006.286.03:12:11.07#ibcon#wrote, iclass 36, count 0 2006.286.03:12:11.07#ibcon#about to read 3, iclass 36, count 0 2006.286.03:12:11.09#ibcon#read 3, iclass 36, count 0 2006.286.03:12:11.09#ibcon#about to read 4, iclass 36, count 0 2006.286.03:12:11.09#ibcon#read 4, iclass 36, count 0 2006.286.03:12:11.09#ibcon#about to read 5, iclass 36, count 0 2006.286.03:12:11.09#ibcon#read 5, iclass 36, count 0 2006.286.03:12:11.09#ibcon#about to read 6, iclass 36, count 0 2006.286.03:12:11.09#ibcon#read 6, iclass 36, count 0 2006.286.03:12:11.09#ibcon#end of sib2, iclass 36, count 0 2006.286.03:12:11.09#ibcon#*mode == 0, iclass 36, count 0 2006.286.03:12:11.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.03:12:11.09#ibcon#[25=USB\r\n] 2006.286.03:12:11.09#ibcon#*before write, iclass 36, count 0 2006.286.03:12:11.09#ibcon#enter sib2, iclass 36, count 0 2006.286.03:12:11.09#ibcon#flushed, iclass 36, count 0 2006.286.03:12:11.09#ibcon#about to write, iclass 36, count 0 2006.286.03:12:11.09#ibcon#wrote, iclass 36, count 0 2006.286.03:12:11.09#ibcon#about to read 3, iclass 36, count 0 2006.286.03:12:11.12#ibcon#read 3, iclass 36, count 0 2006.286.03:12:11.12#ibcon#about to read 4, iclass 36, count 0 2006.286.03:12:11.12#ibcon#read 4, iclass 36, count 0 2006.286.03:12:11.12#ibcon#about to read 5, iclass 36, count 0 2006.286.03:12:11.12#ibcon#read 5, iclass 36, count 0 2006.286.03:12:11.12#ibcon#about to read 6, iclass 36, count 0 2006.286.03:12:11.12#ibcon#read 6, iclass 36, count 0 2006.286.03:12:11.12#ibcon#end of sib2, iclass 36, count 0 2006.286.03:12:11.12#ibcon#*after write, iclass 36, count 0 2006.286.03:12:11.12#ibcon#*before return 0, iclass 36, count 0 2006.286.03:12:11.12#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:12:11.12#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:12:11.12#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.03:12:11.12#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.03:12:11.12$vck44/valo=6,814.99 2006.286.03:12:11.12#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.03:12:11.12#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.03:12:11.12#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:11.12#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:12:11.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:12:11.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:12:11.12#ibcon#enter wrdev, iclass 38, count 0 2006.286.03:12:11.12#ibcon#first serial, iclass 38, count 0 2006.286.03:12:11.12#ibcon#enter sib2, iclass 38, count 0 2006.286.03:12:11.12#ibcon#flushed, iclass 38, count 0 2006.286.03:12:11.12#ibcon#about to write, iclass 38, count 0 2006.286.03:12:11.12#ibcon#wrote, iclass 38, count 0 2006.286.03:12:11.12#ibcon#about to read 3, iclass 38, count 0 2006.286.03:12:11.14#ibcon#read 3, iclass 38, count 0 2006.286.03:12:11.14#ibcon#about to read 4, iclass 38, count 0 2006.286.03:12:11.14#ibcon#read 4, iclass 38, count 0 2006.286.03:12:11.14#ibcon#about to read 5, iclass 38, count 0 2006.286.03:12:11.14#ibcon#read 5, iclass 38, count 0 2006.286.03:12:11.14#ibcon#about to read 6, iclass 38, count 0 2006.286.03:12:11.14#ibcon#read 6, iclass 38, count 0 2006.286.03:12:11.14#ibcon#end of sib2, iclass 38, count 0 2006.286.03:12:11.14#ibcon#*mode == 0, iclass 38, count 0 2006.286.03:12:11.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.03:12:11.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.03:12:11.14#ibcon#*before write, iclass 38, count 0 2006.286.03:12:11.14#ibcon#enter sib2, iclass 38, count 0 2006.286.03:12:11.14#ibcon#flushed, iclass 38, count 0 2006.286.03:12:11.14#ibcon#about to write, iclass 38, count 0 2006.286.03:12:11.14#ibcon#wrote, iclass 38, count 0 2006.286.03:12:11.14#ibcon#about to read 3, iclass 38, count 0 2006.286.03:12:11.18#ibcon#read 3, iclass 38, count 0 2006.286.03:12:11.18#ibcon#about to read 4, iclass 38, count 0 2006.286.03:12:11.18#ibcon#read 4, iclass 38, count 0 2006.286.03:12:11.18#ibcon#about to read 5, iclass 38, count 0 2006.286.03:12:11.18#ibcon#read 5, iclass 38, count 0 2006.286.03:12:11.18#ibcon#about to read 6, iclass 38, count 0 2006.286.03:12:11.18#ibcon#read 6, iclass 38, count 0 2006.286.03:12:11.18#ibcon#end of sib2, iclass 38, count 0 2006.286.03:12:11.18#ibcon#*after write, iclass 38, count 0 2006.286.03:12:11.18#ibcon#*before return 0, iclass 38, count 0 2006.286.03:12:11.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:12:11.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:12:11.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.03:12:11.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.03:12:11.18$vck44/va=6,4 2006.286.03:12:11.18#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.03:12:11.18#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.03:12:11.18#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:11.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:12:11.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:12:11.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:12:11.24#ibcon#enter wrdev, iclass 40, count 2 2006.286.03:12:11.24#ibcon#first serial, iclass 40, count 2 2006.286.03:12:11.24#ibcon#enter sib2, iclass 40, count 2 2006.286.03:12:11.24#ibcon#flushed, iclass 40, count 2 2006.286.03:12:11.24#ibcon#about to write, iclass 40, count 2 2006.286.03:12:11.24#ibcon#wrote, iclass 40, count 2 2006.286.03:12:11.24#ibcon#about to read 3, iclass 40, count 2 2006.286.03:12:11.26#ibcon#read 3, iclass 40, count 2 2006.286.03:12:11.26#ibcon#about to read 4, iclass 40, count 2 2006.286.03:12:11.26#ibcon#read 4, iclass 40, count 2 2006.286.03:12:11.26#ibcon#about to read 5, iclass 40, count 2 2006.286.03:12:11.26#ibcon#read 5, iclass 40, count 2 2006.286.03:12:11.26#ibcon#about to read 6, iclass 40, count 2 2006.286.03:12:11.26#ibcon#read 6, iclass 40, count 2 2006.286.03:12:11.26#ibcon#end of sib2, iclass 40, count 2 2006.286.03:12:11.26#ibcon#*mode == 0, iclass 40, count 2 2006.286.03:12:11.26#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.03:12:11.26#ibcon#[25=AT06-04\r\n] 2006.286.03:12:11.26#ibcon#*before write, iclass 40, count 2 2006.286.03:12:11.26#ibcon#enter sib2, iclass 40, count 2 2006.286.03:12:11.26#ibcon#flushed, iclass 40, count 2 2006.286.03:12:11.26#ibcon#about to write, iclass 40, count 2 2006.286.03:12:11.26#ibcon#wrote, iclass 40, count 2 2006.286.03:12:11.26#ibcon#about to read 3, iclass 40, count 2 2006.286.03:12:11.29#ibcon#read 3, iclass 40, count 2 2006.286.03:12:11.29#ibcon#about to read 4, iclass 40, count 2 2006.286.03:12:11.29#ibcon#read 4, iclass 40, count 2 2006.286.03:12:11.29#ibcon#about to read 5, iclass 40, count 2 2006.286.03:12:11.29#ibcon#read 5, iclass 40, count 2 2006.286.03:12:11.29#ibcon#about to read 6, iclass 40, count 2 2006.286.03:12:11.29#ibcon#read 6, iclass 40, count 2 2006.286.03:12:11.29#ibcon#end of sib2, iclass 40, count 2 2006.286.03:12:11.29#ibcon#*after write, iclass 40, count 2 2006.286.03:12:11.29#ibcon#*before return 0, iclass 40, count 2 2006.286.03:12:11.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:12:11.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:12:11.29#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.03:12:11.29#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:11.29#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:12:11.41#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:12:11.41#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:12:11.41#ibcon#enter wrdev, iclass 40, count 0 2006.286.03:12:11.41#ibcon#first serial, iclass 40, count 0 2006.286.03:12:11.41#ibcon#enter sib2, iclass 40, count 0 2006.286.03:12:11.41#ibcon#flushed, iclass 40, count 0 2006.286.03:12:11.41#ibcon#about to write, iclass 40, count 0 2006.286.03:12:11.41#ibcon#wrote, iclass 40, count 0 2006.286.03:12:11.41#ibcon#about to read 3, iclass 40, count 0 2006.286.03:12:11.43#ibcon#read 3, iclass 40, count 0 2006.286.03:12:11.43#ibcon#about to read 4, iclass 40, count 0 2006.286.03:12:11.43#ibcon#read 4, iclass 40, count 0 2006.286.03:12:11.43#ibcon#about to read 5, iclass 40, count 0 2006.286.03:12:11.43#ibcon#read 5, iclass 40, count 0 2006.286.03:12:11.43#ibcon#about to read 6, iclass 40, count 0 2006.286.03:12:11.43#ibcon#read 6, iclass 40, count 0 2006.286.03:12:11.43#ibcon#end of sib2, iclass 40, count 0 2006.286.03:12:11.43#ibcon#*mode == 0, iclass 40, count 0 2006.286.03:12:11.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.03:12:11.43#ibcon#[25=USB\r\n] 2006.286.03:12:11.43#ibcon#*before write, iclass 40, count 0 2006.286.03:12:11.43#ibcon#enter sib2, iclass 40, count 0 2006.286.03:12:11.43#ibcon#flushed, iclass 40, count 0 2006.286.03:12:11.43#ibcon#about to write, iclass 40, count 0 2006.286.03:12:11.43#ibcon#wrote, iclass 40, count 0 2006.286.03:12:11.43#ibcon#about to read 3, iclass 40, count 0 2006.286.03:12:11.46#ibcon#read 3, iclass 40, count 0 2006.286.03:12:11.46#ibcon#about to read 4, iclass 40, count 0 2006.286.03:12:11.67#ibcon#read 4, iclass 40, count 0 2006.286.03:12:11.67#ibcon#about to read 5, iclass 40, count 0 2006.286.03:12:11.67#ibcon#read 5, iclass 40, count 0 2006.286.03:12:11.67#ibcon#about to read 6, iclass 40, count 0 2006.286.03:12:11.67#ibcon#read 6, iclass 40, count 0 2006.286.03:12:11.67#ibcon#end of sib2, iclass 40, count 0 2006.286.03:12:11.67#ibcon#*after write, iclass 40, count 0 2006.286.03:12:11.67#ibcon#*before return 0, iclass 40, count 0 2006.286.03:12:11.67#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:12:11.67#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:12:11.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.03:12:11.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.03:12:11.67$vck44/valo=7,864.99 2006.286.03:12:11.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.03:12:11.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.03:12:11.67#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:11.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:12:11.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:12:11.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:12:11.67#ibcon#enter wrdev, iclass 4, count 0 2006.286.03:12:11.67#ibcon#first serial, iclass 4, count 0 2006.286.03:12:11.67#ibcon#enter sib2, iclass 4, count 0 2006.286.03:12:11.67#ibcon#flushed, iclass 4, count 0 2006.286.03:12:11.67#ibcon#about to write, iclass 4, count 0 2006.286.03:12:11.67#ibcon#wrote, iclass 4, count 0 2006.286.03:12:11.67#ibcon#about to read 3, iclass 4, count 0 2006.286.03:12:11.69#ibcon#read 3, iclass 4, count 0 2006.286.03:12:11.69#ibcon#about to read 4, iclass 4, count 0 2006.286.03:12:11.69#ibcon#read 4, iclass 4, count 0 2006.286.03:12:11.69#ibcon#about to read 5, iclass 4, count 0 2006.286.03:12:11.69#ibcon#read 5, iclass 4, count 0 2006.286.03:12:11.69#ibcon#about to read 6, iclass 4, count 0 2006.286.03:12:11.69#ibcon#read 6, iclass 4, count 0 2006.286.03:12:11.69#ibcon#end of sib2, iclass 4, count 0 2006.286.03:12:11.69#ibcon#*mode == 0, iclass 4, count 0 2006.286.03:12:11.69#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.03:12:11.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.03:12:11.69#ibcon#*before write, iclass 4, count 0 2006.286.03:12:11.69#ibcon#enter sib2, iclass 4, count 0 2006.286.03:12:11.69#ibcon#flushed, iclass 4, count 0 2006.286.03:12:11.69#ibcon#about to write, iclass 4, count 0 2006.286.03:12:11.69#ibcon#wrote, iclass 4, count 0 2006.286.03:12:11.69#ibcon#about to read 3, iclass 4, count 0 2006.286.03:12:11.73#ibcon#read 3, iclass 4, count 0 2006.286.03:12:11.73#ibcon#about to read 4, iclass 4, count 0 2006.286.03:12:11.73#ibcon#read 4, iclass 4, count 0 2006.286.03:12:11.73#ibcon#about to read 5, iclass 4, count 0 2006.286.03:12:11.73#ibcon#read 5, iclass 4, count 0 2006.286.03:12:11.73#ibcon#about to read 6, iclass 4, count 0 2006.286.03:12:11.73#ibcon#read 6, iclass 4, count 0 2006.286.03:12:11.73#ibcon#end of sib2, iclass 4, count 0 2006.286.03:12:11.73#ibcon#*after write, iclass 4, count 0 2006.286.03:12:11.73#ibcon#*before return 0, iclass 4, count 0 2006.286.03:12:11.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:12:11.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:12:11.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.03:12:11.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.03:12:11.73$vck44/va=7,4 2006.286.03:12:11.73#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.03:12:11.73#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.03:12:11.73#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:11.73#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.03:12:11.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.03:12:11.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.03:12:11.79#ibcon#enter wrdev, iclass 6, count 2 2006.286.03:12:11.79#ibcon#first serial, iclass 6, count 2 2006.286.03:12:11.79#ibcon#enter sib2, iclass 6, count 2 2006.286.03:12:11.79#ibcon#flushed, iclass 6, count 2 2006.286.03:12:11.79#ibcon#about to write, iclass 6, count 2 2006.286.03:12:11.79#ibcon#wrote, iclass 6, count 2 2006.286.03:12:11.79#ibcon#about to read 3, iclass 6, count 2 2006.286.03:12:11.81#ibcon#read 3, iclass 6, count 2 2006.286.03:12:11.81#ibcon#about to read 4, iclass 6, count 2 2006.286.03:12:11.81#ibcon#read 4, iclass 6, count 2 2006.286.03:12:11.81#ibcon#about to read 5, iclass 6, count 2 2006.286.03:12:11.81#ibcon#read 5, iclass 6, count 2 2006.286.03:12:11.81#ibcon#about to read 6, iclass 6, count 2 2006.286.03:12:11.81#ibcon#read 6, iclass 6, count 2 2006.286.03:12:11.81#ibcon#end of sib2, iclass 6, count 2 2006.286.03:12:11.81#ibcon#*mode == 0, iclass 6, count 2 2006.286.03:12:11.81#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.03:12:11.81#ibcon#[25=AT07-04\r\n] 2006.286.03:12:11.81#ibcon#*before write, iclass 6, count 2 2006.286.03:12:11.81#ibcon#enter sib2, iclass 6, count 2 2006.286.03:12:11.81#ibcon#flushed, iclass 6, count 2 2006.286.03:12:11.81#ibcon#about to write, iclass 6, count 2 2006.286.03:12:11.81#ibcon#wrote, iclass 6, count 2 2006.286.03:12:11.81#ibcon#about to read 3, iclass 6, count 2 2006.286.03:12:11.84#ibcon#read 3, iclass 6, count 2 2006.286.03:12:11.84#ibcon#about to read 4, iclass 6, count 2 2006.286.03:12:11.84#ibcon#read 4, iclass 6, count 2 2006.286.03:12:11.84#ibcon#about to read 5, iclass 6, count 2 2006.286.03:12:11.84#ibcon#read 5, iclass 6, count 2 2006.286.03:12:11.84#ibcon#about to read 6, iclass 6, count 2 2006.286.03:12:11.84#ibcon#read 6, iclass 6, count 2 2006.286.03:12:11.84#ibcon#end of sib2, iclass 6, count 2 2006.286.03:12:11.84#ibcon#*after write, iclass 6, count 2 2006.286.03:12:11.84#ibcon#*before return 0, iclass 6, count 2 2006.286.03:12:11.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.03:12:11.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.03:12:11.84#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.03:12:11.84#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:11.84#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.03:12:11.96#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.03:12:11.96#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.03:12:11.96#ibcon#enter wrdev, iclass 6, count 0 2006.286.03:12:11.96#ibcon#first serial, iclass 6, count 0 2006.286.03:12:11.96#ibcon#enter sib2, iclass 6, count 0 2006.286.03:12:11.96#ibcon#flushed, iclass 6, count 0 2006.286.03:12:11.96#ibcon#about to write, iclass 6, count 0 2006.286.03:12:11.96#ibcon#wrote, iclass 6, count 0 2006.286.03:12:11.96#ibcon#about to read 3, iclass 6, count 0 2006.286.03:12:11.98#ibcon#read 3, iclass 6, count 0 2006.286.03:12:11.98#ibcon#about to read 4, iclass 6, count 0 2006.286.03:12:11.98#ibcon#read 4, iclass 6, count 0 2006.286.03:12:11.98#ibcon#about to read 5, iclass 6, count 0 2006.286.03:12:11.98#ibcon#read 5, iclass 6, count 0 2006.286.03:12:11.98#ibcon#about to read 6, iclass 6, count 0 2006.286.03:12:11.98#ibcon#read 6, iclass 6, count 0 2006.286.03:12:11.98#ibcon#end of sib2, iclass 6, count 0 2006.286.03:12:11.98#ibcon#*mode == 0, iclass 6, count 0 2006.286.03:12:11.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.03:12:11.98#ibcon#[25=USB\r\n] 2006.286.03:12:11.98#ibcon#*before write, iclass 6, count 0 2006.286.03:12:11.98#ibcon#enter sib2, iclass 6, count 0 2006.286.03:12:11.98#ibcon#flushed, iclass 6, count 0 2006.286.03:12:11.98#ibcon#about to write, iclass 6, count 0 2006.286.03:12:11.98#ibcon#wrote, iclass 6, count 0 2006.286.03:12:11.98#ibcon#about to read 3, iclass 6, count 0 2006.286.03:12:12.01#ibcon#read 3, iclass 6, count 0 2006.286.03:12:12.01#ibcon#about to read 4, iclass 6, count 0 2006.286.03:12:12.01#ibcon#read 4, iclass 6, count 0 2006.286.03:12:12.01#ibcon#about to read 5, iclass 6, count 0 2006.286.03:12:12.01#ibcon#read 5, iclass 6, count 0 2006.286.03:12:12.01#ibcon#about to read 6, iclass 6, count 0 2006.286.03:12:12.01#ibcon#read 6, iclass 6, count 0 2006.286.03:12:12.01#ibcon#end of sib2, iclass 6, count 0 2006.286.03:12:12.01#ibcon#*after write, iclass 6, count 0 2006.286.03:12:12.01#ibcon#*before return 0, iclass 6, count 0 2006.286.03:12:12.01#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.03:12:12.01#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.03:12:12.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.03:12:12.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.03:12:12.01$vck44/valo=8,884.99 2006.286.03:12:12.01#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.03:12:12.01#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.03:12:12.01#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:12.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:12:12.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:12:12.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:12:12.01#ibcon#enter wrdev, iclass 10, count 0 2006.286.03:12:12.01#ibcon#first serial, iclass 10, count 0 2006.286.03:12:12.01#ibcon#enter sib2, iclass 10, count 0 2006.286.03:12:12.01#ibcon#flushed, iclass 10, count 0 2006.286.03:12:12.01#ibcon#about to write, iclass 10, count 0 2006.286.03:12:12.01#ibcon#wrote, iclass 10, count 0 2006.286.03:12:12.01#ibcon#about to read 3, iclass 10, count 0 2006.286.03:12:12.03#ibcon#read 3, iclass 10, count 0 2006.286.03:12:12.03#ibcon#about to read 4, iclass 10, count 0 2006.286.03:12:12.03#ibcon#read 4, iclass 10, count 0 2006.286.03:12:12.03#ibcon#about to read 5, iclass 10, count 0 2006.286.03:12:12.03#ibcon#read 5, iclass 10, count 0 2006.286.03:12:12.03#ibcon#about to read 6, iclass 10, count 0 2006.286.03:12:12.03#ibcon#read 6, iclass 10, count 0 2006.286.03:12:12.03#ibcon#end of sib2, iclass 10, count 0 2006.286.03:12:12.03#ibcon#*mode == 0, iclass 10, count 0 2006.286.03:12:12.03#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.03:12:12.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.03:12:12.03#ibcon#*before write, iclass 10, count 0 2006.286.03:12:12.03#ibcon#enter sib2, iclass 10, count 0 2006.286.03:12:12.03#ibcon#flushed, iclass 10, count 0 2006.286.03:12:12.03#ibcon#about to write, iclass 10, count 0 2006.286.03:12:12.03#ibcon#wrote, iclass 10, count 0 2006.286.03:12:12.03#ibcon#about to read 3, iclass 10, count 0 2006.286.03:12:12.07#ibcon#read 3, iclass 10, count 0 2006.286.03:12:12.07#ibcon#about to read 4, iclass 10, count 0 2006.286.03:12:12.07#ibcon#read 4, iclass 10, count 0 2006.286.03:12:12.07#ibcon#about to read 5, iclass 10, count 0 2006.286.03:12:12.07#ibcon#read 5, iclass 10, count 0 2006.286.03:12:12.07#ibcon#about to read 6, iclass 10, count 0 2006.286.03:12:12.07#ibcon#read 6, iclass 10, count 0 2006.286.03:12:12.07#ibcon#end of sib2, iclass 10, count 0 2006.286.03:12:12.07#ibcon#*after write, iclass 10, count 0 2006.286.03:12:12.07#ibcon#*before return 0, iclass 10, count 0 2006.286.03:12:12.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:12:12.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:12:12.07#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.03:12:12.07#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.03:12:12.07$vck44/va=8,3 2006.286.03:12:12.07#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.03:12:12.07#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.03:12:12.07#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:12.07#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:12:12.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:12:12.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:12:12.13#ibcon#enter wrdev, iclass 12, count 2 2006.286.03:12:12.13#ibcon#first serial, iclass 12, count 2 2006.286.03:12:12.13#ibcon#enter sib2, iclass 12, count 2 2006.286.03:12:12.13#ibcon#flushed, iclass 12, count 2 2006.286.03:12:12.13#ibcon#about to write, iclass 12, count 2 2006.286.03:12:12.13#ibcon#wrote, iclass 12, count 2 2006.286.03:12:12.13#ibcon#about to read 3, iclass 12, count 2 2006.286.03:12:12.15#ibcon#read 3, iclass 12, count 2 2006.286.03:12:12.15#ibcon#about to read 4, iclass 12, count 2 2006.286.03:12:12.15#ibcon#read 4, iclass 12, count 2 2006.286.03:12:12.15#ibcon#about to read 5, iclass 12, count 2 2006.286.03:12:12.15#ibcon#read 5, iclass 12, count 2 2006.286.03:12:12.15#ibcon#about to read 6, iclass 12, count 2 2006.286.03:12:12.15#ibcon#read 6, iclass 12, count 2 2006.286.03:12:12.15#ibcon#end of sib2, iclass 12, count 2 2006.286.03:12:12.15#ibcon#*mode == 0, iclass 12, count 2 2006.286.03:12:12.15#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.03:12:12.15#ibcon#[25=AT08-03\r\n] 2006.286.03:12:12.15#ibcon#*before write, iclass 12, count 2 2006.286.03:12:12.15#ibcon#enter sib2, iclass 12, count 2 2006.286.03:12:12.15#ibcon#flushed, iclass 12, count 2 2006.286.03:12:12.15#ibcon#about to write, iclass 12, count 2 2006.286.03:12:12.15#ibcon#wrote, iclass 12, count 2 2006.286.03:12:12.15#ibcon#about to read 3, iclass 12, count 2 2006.286.03:12:12.18#ibcon#read 3, iclass 12, count 2 2006.286.03:12:12.18#ibcon#about to read 4, iclass 12, count 2 2006.286.03:12:12.18#ibcon#read 4, iclass 12, count 2 2006.286.03:12:12.18#ibcon#about to read 5, iclass 12, count 2 2006.286.03:12:12.18#ibcon#read 5, iclass 12, count 2 2006.286.03:12:12.18#ibcon#about to read 6, iclass 12, count 2 2006.286.03:12:12.18#ibcon#read 6, iclass 12, count 2 2006.286.03:12:12.18#ibcon#end of sib2, iclass 12, count 2 2006.286.03:12:12.18#ibcon#*after write, iclass 12, count 2 2006.286.03:12:12.18#ibcon#*before return 0, iclass 12, count 2 2006.286.03:12:12.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:12:12.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:12:12.18#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.03:12:12.18#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:12.18#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:12:12.30#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:12:12.30#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:12:12.30#ibcon#enter wrdev, iclass 12, count 0 2006.286.03:12:12.30#ibcon#first serial, iclass 12, count 0 2006.286.03:12:12.30#ibcon#enter sib2, iclass 12, count 0 2006.286.03:12:12.30#ibcon#flushed, iclass 12, count 0 2006.286.03:12:12.30#ibcon#about to write, iclass 12, count 0 2006.286.03:12:12.30#ibcon#wrote, iclass 12, count 0 2006.286.03:12:12.30#ibcon#about to read 3, iclass 12, count 0 2006.286.03:12:12.32#ibcon#read 3, iclass 12, count 0 2006.286.03:12:12.32#ibcon#about to read 4, iclass 12, count 0 2006.286.03:12:12.32#ibcon#read 4, iclass 12, count 0 2006.286.03:12:12.32#ibcon#about to read 5, iclass 12, count 0 2006.286.03:12:12.32#ibcon#read 5, iclass 12, count 0 2006.286.03:12:12.32#ibcon#about to read 6, iclass 12, count 0 2006.286.03:12:12.32#ibcon#read 6, iclass 12, count 0 2006.286.03:12:12.32#ibcon#end of sib2, iclass 12, count 0 2006.286.03:12:12.32#ibcon#*mode == 0, iclass 12, count 0 2006.286.03:12:12.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.03:12:12.32#ibcon#[25=USB\r\n] 2006.286.03:12:12.32#ibcon#*before write, iclass 12, count 0 2006.286.03:12:12.32#ibcon#enter sib2, iclass 12, count 0 2006.286.03:12:12.32#ibcon#flushed, iclass 12, count 0 2006.286.03:12:12.32#ibcon#about to write, iclass 12, count 0 2006.286.03:12:12.32#ibcon#wrote, iclass 12, count 0 2006.286.03:12:12.32#ibcon#about to read 3, iclass 12, count 0 2006.286.03:12:12.35#ibcon#read 3, iclass 12, count 0 2006.286.03:12:12.35#ibcon#about to read 4, iclass 12, count 0 2006.286.03:12:12.35#ibcon#read 4, iclass 12, count 0 2006.286.03:12:12.35#ibcon#about to read 5, iclass 12, count 0 2006.286.03:12:12.35#ibcon#read 5, iclass 12, count 0 2006.286.03:12:12.35#ibcon#about to read 6, iclass 12, count 0 2006.286.03:12:12.35#ibcon#read 6, iclass 12, count 0 2006.286.03:12:12.35#ibcon#end of sib2, iclass 12, count 0 2006.286.03:12:12.35#ibcon#*after write, iclass 12, count 0 2006.286.03:12:12.35#ibcon#*before return 0, iclass 12, count 0 2006.286.03:12:12.35#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:12:12.35#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:12:12.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.03:12:12.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.03:12:12.35$vck44/vblo=1,629.99 2006.286.03:12:12.35#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.03:12:12.35#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.03:12:12.35#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:12.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:12:12.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:12:12.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:12:12.35#ibcon#enter wrdev, iclass 14, count 0 2006.286.03:12:12.35#ibcon#first serial, iclass 14, count 0 2006.286.03:12:12.35#ibcon#enter sib2, iclass 14, count 0 2006.286.03:12:12.35#ibcon#flushed, iclass 14, count 0 2006.286.03:12:12.35#ibcon#about to write, iclass 14, count 0 2006.286.03:12:12.35#ibcon#wrote, iclass 14, count 0 2006.286.03:12:12.35#ibcon#about to read 3, iclass 14, count 0 2006.286.03:12:12.44#ibcon#read 3, iclass 14, count 0 2006.286.03:12:12.44#ibcon#about to read 4, iclass 14, count 0 2006.286.03:12:12.44#ibcon#read 4, iclass 14, count 0 2006.286.03:12:12.44#ibcon#about to read 5, iclass 14, count 0 2006.286.03:12:12.44#ibcon#read 5, iclass 14, count 0 2006.286.03:12:12.44#ibcon#about to read 6, iclass 14, count 0 2006.286.03:12:12.44#ibcon#read 6, iclass 14, count 0 2006.286.03:12:12.44#ibcon#end of sib2, iclass 14, count 0 2006.286.03:12:12.44#ibcon#*mode == 0, iclass 14, count 0 2006.286.03:12:12.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.03:12:12.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.03:12:12.44#ibcon#*before write, iclass 14, count 0 2006.286.03:12:12.44#ibcon#enter sib2, iclass 14, count 0 2006.286.03:12:12.44#ibcon#flushed, iclass 14, count 0 2006.286.03:12:12.44#ibcon#about to write, iclass 14, count 0 2006.286.03:12:12.44#ibcon#wrote, iclass 14, count 0 2006.286.03:12:12.44#ibcon#about to read 3, iclass 14, count 0 2006.286.03:12:12.48#ibcon#read 3, iclass 14, count 0 2006.286.03:12:12.48#ibcon#about to read 4, iclass 14, count 0 2006.286.03:12:12.48#ibcon#read 4, iclass 14, count 0 2006.286.03:12:12.48#ibcon#about to read 5, iclass 14, count 0 2006.286.03:12:12.48#ibcon#read 5, iclass 14, count 0 2006.286.03:12:12.48#ibcon#about to read 6, iclass 14, count 0 2006.286.03:12:12.48#ibcon#read 6, iclass 14, count 0 2006.286.03:12:12.48#ibcon#end of sib2, iclass 14, count 0 2006.286.03:12:12.48#ibcon#*after write, iclass 14, count 0 2006.286.03:12:12.48#ibcon#*before return 0, iclass 14, count 0 2006.286.03:12:12.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:12:12.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:12:12.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.03:12:12.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.03:12:12.48$vck44/vb=1,4 2006.286.03:12:12.48#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.03:12:12.48#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.03:12:12.48#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:12.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:12:12.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:12:12.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:12:12.48#ibcon#enter wrdev, iclass 16, count 2 2006.286.03:12:12.48#ibcon#first serial, iclass 16, count 2 2006.286.03:12:12.48#ibcon#enter sib2, iclass 16, count 2 2006.286.03:12:12.48#ibcon#flushed, iclass 16, count 2 2006.286.03:12:12.48#ibcon#about to write, iclass 16, count 2 2006.286.03:12:12.48#ibcon#wrote, iclass 16, count 2 2006.286.03:12:12.48#ibcon#about to read 3, iclass 16, count 2 2006.286.03:12:12.50#ibcon#read 3, iclass 16, count 2 2006.286.03:12:12.50#ibcon#about to read 4, iclass 16, count 2 2006.286.03:12:12.50#ibcon#read 4, iclass 16, count 2 2006.286.03:12:12.50#ibcon#about to read 5, iclass 16, count 2 2006.286.03:12:12.50#ibcon#read 5, iclass 16, count 2 2006.286.03:12:12.50#ibcon#about to read 6, iclass 16, count 2 2006.286.03:12:12.50#ibcon#read 6, iclass 16, count 2 2006.286.03:12:12.50#ibcon#end of sib2, iclass 16, count 2 2006.286.03:12:12.50#ibcon#*mode == 0, iclass 16, count 2 2006.286.03:12:12.50#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.03:12:12.50#ibcon#[27=AT01-04\r\n] 2006.286.03:12:12.50#ibcon#*before write, iclass 16, count 2 2006.286.03:12:12.50#ibcon#enter sib2, iclass 16, count 2 2006.286.03:12:12.50#ibcon#flushed, iclass 16, count 2 2006.286.03:12:12.50#ibcon#about to write, iclass 16, count 2 2006.286.03:12:12.50#ibcon#wrote, iclass 16, count 2 2006.286.03:12:12.50#ibcon#about to read 3, iclass 16, count 2 2006.286.03:12:12.53#ibcon#read 3, iclass 16, count 2 2006.286.03:12:12.53#ibcon#about to read 4, iclass 16, count 2 2006.286.03:12:12.53#ibcon#read 4, iclass 16, count 2 2006.286.03:12:12.53#ibcon#about to read 5, iclass 16, count 2 2006.286.03:12:12.53#ibcon#read 5, iclass 16, count 2 2006.286.03:12:12.53#ibcon#about to read 6, iclass 16, count 2 2006.286.03:12:12.53#ibcon#read 6, iclass 16, count 2 2006.286.03:12:12.53#ibcon#end of sib2, iclass 16, count 2 2006.286.03:12:12.53#ibcon#*after write, iclass 16, count 2 2006.286.03:12:12.53#ibcon#*before return 0, iclass 16, count 2 2006.286.03:12:12.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:12:12.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:12:12.53#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.03:12:12.53#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:12.53#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:12:12.65#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:12:12.65#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:12:12.65#ibcon#enter wrdev, iclass 16, count 0 2006.286.03:12:12.65#ibcon#first serial, iclass 16, count 0 2006.286.03:12:12.65#ibcon#enter sib2, iclass 16, count 0 2006.286.03:12:12.65#ibcon#flushed, iclass 16, count 0 2006.286.03:12:12.65#ibcon#about to write, iclass 16, count 0 2006.286.03:12:12.65#ibcon#wrote, iclass 16, count 0 2006.286.03:12:12.65#ibcon#about to read 3, iclass 16, count 0 2006.286.03:12:12.67#ibcon#read 3, iclass 16, count 0 2006.286.03:12:12.67#ibcon#about to read 4, iclass 16, count 0 2006.286.03:12:12.67#ibcon#read 4, iclass 16, count 0 2006.286.03:12:12.67#ibcon#about to read 5, iclass 16, count 0 2006.286.03:12:12.67#ibcon#read 5, iclass 16, count 0 2006.286.03:12:12.67#ibcon#about to read 6, iclass 16, count 0 2006.286.03:12:12.67#ibcon#read 6, iclass 16, count 0 2006.286.03:12:12.67#ibcon#end of sib2, iclass 16, count 0 2006.286.03:12:12.67#ibcon#*mode == 0, iclass 16, count 0 2006.286.03:12:12.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.03:12:12.67#ibcon#[27=USB\r\n] 2006.286.03:12:12.67#ibcon#*before write, iclass 16, count 0 2006.286.03:12:12.67#ibcon#enter sib2, iclass 16, count 0 2006.286.03:12:12.67#ibcon#flushed, iclass 16, count 0 2006.286.03:12:12.67#ibcon#about to write, iclass 16, count 0 2006.286.03:12:12.67#ibcon#wrote, iclass 16, count 0 2006.286.03:12:12.67#ibcon#about to read 3, iclass 16, count 0 2006.286.03:12:12.70#ibcon#read 3, iclass 16, count 0 2006.286.03:12:12.70#ibcon#about to read 4, iclass 16, count 0 2006.286.03:12:12.70#ibcon#read 4, iclass 16, count 0 2006.286.03:12:12.70#ibcon#about to read 5, iclass 16, count 0 2006.286.03:12:12.70#ibcon#read 5, iclass 16, count 0 2006.286.03:12:12.70#ibcon#about to read 6, iclass 16, count 0 2006.286.03:12:12.70#ibcon#read 6, iclass 16, count 0 2006.286.03:12:12.70#ibcon#end of sib2, iclass 16, count 0 2006.286.03:12:12.70#ibcon#*after write, iclass 16, count 0 2006.286.03:12:12.70#ibcon#*before return 0, iclass 16, count 0 2006.286.03:12:12.70#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:12:12.70#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:12:12.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.03:12:12.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.03:12:12.70$vck44/vblo=2,634.99 2006.286.03:12:12.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.03:12:12.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.03:12:12.70#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:12.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:12:12.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:12:12.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:12:12.70#ibcon#enter wrdev, iclass 18, count 0 2006.286.03:12:12.70#ibcon#first serial, iclass 18, count 0 2006.286.03:12:12.70#ibcon#enter sib2, iclass 18, count 0 2006.286.03:12:12.70#ibcon#flushed, iclass 18, count 0 2006.286.03:12:12.70#ibcon#about to write, iclass 18, count 0 2006.286.03:12:12.70#ibcon#wrote, iclass 18, count 0 2006.286.03:12:12.70#ibcon#about to read 3, iclass 18, count 0 2006.286.03:12:12.72#ibcon#read 3, iclass 18, count 0 2006.286.03:12:12.72#ibcon#about to read 4, iclass 18, count 0 2006.286.03:12:12.72#ibcon#read 4, iclass 18, count 0 2006.286.03:12:12.72#ibcon#about to read 5, iclass 18, count 0 2006.286.03:12:12.72#ibcon#read 5, iclass 18, count 0 2006.286.03:12:12.72#ibcon#about to read 6, iclass 18, count 0 2006.286.03:12:12.72#ibcon#read 6, iclass 18, count 0 2006.286.03:12:12.72#ibcon#end of sib2, iclass 18, count 0 2006.286.03:12:12.72#ibcon#*mode == 0, iclass 18, count 0 2006.286.03:12:12.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.03:12:12.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.03:12:12.72#ibcon#*before write, iclass 18, count 0 2006.286.03:12:12.72#ibcon#enter sib2, iclass 18, count 0 2006.286.03:12:12.72#ibcon#flushed, iclass 18, count 0 2006.286.03:12:12.72#ibcon#about to write, iclass 18, count 0 2006.286.03:12:12.72#ibcon#wrote, iclass 18, count 0 2006.286.03:12:12.72#ibcon#about to read 3, iclass 18, count 0 2006.286.03:12:12.76#ibcon#read 3, iclass 18, count 0 2006.286.03:12:12.76#ibcon#about to read 4, iclass 18, count 0 2006.286.03:12:12.76#ibcon#read 4, iclass 18, count 0 2006.286.03:12:12.76#ibcon#about to read 5, iclass 18, count 0 2006.286.03:12:12.76#ibcon#read 5, iclass 18, count 0 2006.286.03:12:12.76#ibcon#about to read 6, iclass 18, count 0 2006.286.03:12:12.76#ibcon#read 6, iclass 18, count 0 2006.286.03:12:12.76#ibcon#end of sib2, iclass 18, count 0 2006.286.03:12:12.76#ibcon#*after write, iclass 18, count 0 2006.286.03:12:12.76#ibcon#*before return 0, iclass 18, count 0 2006.286.03:12:12.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:12:12.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:12:12.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.03:12:12.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.03:12:12.76$vck44/vb=2,5 2006.286.03:12:12.76#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.03:12:12.76#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.03:12:12.76#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:12.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:12:12.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:12:12.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:12:12.82#ibcon#enter wrdev, iclass 20, count 2 2006.286.03:12:12.82#ibcon#first serial, iclass 20, count 2 2006.286.03:12:12.82#ibcon#enter sib2, iclass 20, count 2 2006.286.03:12:12.82#ibcon#flushed, iclass 20, count 2 2006.286.03:12:12.82#ibcon#about to write, iclass 20, count 2 2006.286.03:12:12.82#ibcon#wrote, iclass 20, count 2 2006.286.03:12:12.82#ibcon#about to read 3, iclass 20, count 2 2006.286.03:12:12.84#ibcon#read 3, iclass 20, count 2 2006.286.03:12:12.84#ibcon#about to read 4, iclass 20, count 2 2006.286.03:12:12.84#ibcon#read 4, iclass 20, count 2 2006.286.03:12:12.84#ibcon#about to read 5, iclass 20, count 2 2006.286.03:12:12.84#ibcon#read 5, iclass 20, count 2 2006.286.03:12:12.84#ibcon#about to read 6, iclass 20, count 2 2006.286.03:12:12.84#ibcon#read 6, iclass 20, count 2 2006.286.03:12:12.84#ibcon#end of sib2, iclass 20, count 2 2006.286.03:12:12.84#ibcon#*mode == 0, iclass 20, count 2 2006.286.03:12:12.84#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.03:12:12.84#ibcon#[27=AT02-05\r\n] 2006.286.03:12:12.84#ibcon#*before write, iclass 20, count 2 2006.286.03:12:12.84#ibcon#enter sib2, iclass 20, count 2 2006.286.03:12:12.84#ibcon#flushed, iclass 20, count 2 2006.286.03:12:12.84#ibcon#about to write, iclass 20, count 2 2006.286.03:12:12.84#ibcon#wrote, iclass 20, count 2 2006.286.03:12:12.84#ibcon#about to read 3, iclass 20, count 2 2006.286.03:12:12.87#ibcon#read 3, iclass 20, count 2 2006.286.03:12:12.87#ibcon#about to read 4, iclass 20, count 2 2006.286.03:12:12.87#ibcon#read 4, iclass 20, count 2 2006.286.03:12:12.87#ibcon#about to read 5, iclass 20, count 2 2006.286.03:12:12.87#ibcon#read 5, iclass 20, count 2 2006.286.03:12:12.87#ibcon#about to read 6, iclass 20, count 2 2006.286.03:12:12.87#ibcon#read 6, iclass 20, count 2 2006.286.03:12:12.87#ibcon#end of sib2, iclass 20, count 2 2006.286.03:12:12.87#ibcon#*after write, iclass 20, count 2 2006.286.03:12:12.87#ibcon#*before return 0, iclass 20, count 2 2006.286.03:12:12.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:12:12.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:12:12.87#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.03:12:12.87#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:12.87#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:12:12.99#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:12:12.99#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:12:12.99#ibcon#enter wrdev, iclass 20, count 0 2006.286.03:12:12.99#ibcon#first serial, iclass 20, count 0 2006.286.03:12:12.99#ibcon#enter sib2, iclass 20, count 0 2006.286.03:12:12.99#ibcon#flushed, iclass 20, count 0 2006.286.03:12:12.99#ibcon#about to write, iclass 20, count 0 2006.286.03:12:12.99#ibcon#wrote, iclass 20, count 0 2006.286.03:12:12.99#ibcon#about to read 3, iclass 20, count 0 2006.286.03:12:13.01#ibcon#read 3, iclass 20, count 0 2006.286.03:12:13.01#ibcon#about to read 4, iclass 20, count 0 2006.286.03:12:13.01#ibcon#read 4, iclass 20, count 0 2006.286.03:12:13.01#ibcon#about to read 5, iclass 20, count 0 2006.286.03:12:13.01#ibcon#read 5, iclass 20, count 0 2006.286.03:12:13.01#ibcon#about to read 6, iclass 20, count 0 2006.286.03:12:13.01#ibcon#read 6, iclass 20, count 0 2006.286.03:12:13.01#ibcon#end of sib2, iclass 20, count 0 2006.286.03:12:13.01#ibcon#*mode == 0, iclass 20, count 0 2006.286.03:12:13.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.03:12:13.01#ibcon#[27=USB\r\n] 2006.286.03:12:13.01#ibcon#*before write, iclass 20, count 0 2006.286.03:12:13.01#ibcon#enter sib2, iclass 20, count 0 2006.286.03:12:13.01#ibcon#flushed, iclass 20, count 0 2006.286.03:12:13.01#ibcon#about to write, iclass 20, count 0 2006.286.03:12:13.01#ibcon#wrote, iclass 20, count 0 2006.286.03:12:13.01#ibcon#about to read 3, iclass 20, count 0 2006.286.03:12:13.04#ibcon#read 3, iclass 20, count 0 2006.286.03:12:13.04#ibcon#about to read 4, iclass 20, count 0 2006.286.03:12:13.04#ibcon#read 4, iclass 20, count 0 2006.286.03:12:13.04#ibcon#about to read 5, iclass 20, count 0 2006.286.03:12:13.04#ibcon#read 5, iclass 20, count 0 2006.286.03:12:13.04#ibcon#about to read 6, iclass 20, count 0 2006.286.03:12:13.04#ibcon#read 6, iclass 20, count 0 2006.286.03:12:13.04#ibcon#end of sib2, iclass 20, count 0 2006.286.03:12:13.04#ibcon#*after write, iclass 20, count 0 2006.286.03:12:13.04#ibcon#*before return 0, iclass 20, count 0 2006.286.03:12:13.04#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:12:13.04#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:12:13.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.03:12:13.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.03:12:13.04$vck44/vblo=3,649.99 2006.286.03:12:13.04#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.03:12:13.04#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.03:12:13.04#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:13.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:12:13.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:12:13.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:12:13.04#ibcon#enter wrdev, iclass 22, count 0 2006.286.03:12:13.04#ibcon#first serial, iclass 22, count 0 2006.286.03:12:13.04#ibcon#enter sib2, iclass 22, count 0 2006.286.03:12:13.04#ibcon#flushed, iclass 22, count 0 2006.286.03:12:13.04#ibcon#about to write, iclass 22, count 0 2006.286.03:12:13.04#ibcon#wrote, iclass 22, count 0 2006.286.03:12:13.04#ibcon#about to read 3, iclass 22, count 0 2006.286.03:12:13.06#ibcon#read 3, iclass 22, count 0 2006.286.03:12:13.06#ibcon#about to read 4, iclass 22, count 0 2006.286.03:12:13.06#ibcon#read 4, iclass 22, count 0 2006.286.03:12:13.06#ibcon#about to read 5, iclass 22, count 0 2006.286.03:12:13.06#ibcon#read 5, iclass 22, count 0 2006.286.03:12:13.06#ibcon#about to read 6, iclass 22, count 0 2006.286.03:12:13.06#ibcon#read 6, iclass 22, count 0 2006.286.03:12:13.06#ibcon#end of sib2, iclass 22, count 0 2006.286.03:12:13.06#ibcon#*mode == 0, iclass 22, count 0 2006.286.03:12:13.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.03:12:13.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.03:12:13.06#ibcon#*before write, iclass 22, count 0 2006.286.03:12:13.06#ibcon#enter sib2, iclass 22, count 0 2006.286.03:12:13.06#ibcon#flushed, iclass 22, count 0 2006.286.03:12:13.06#ibcon#about to write, iclass 22, count 0 2006.286.03:12:13.06#ibcon#wrote, iclass 22, count 0 2006.286.03:12:13.06#ibcon#about to read 3, iclass 22, count 0 2006.286.03:12:13.10#ibcon#read 3, iclass 22, count 0 2006.286.03:12:13.10#ibcon#about to read 4, iclass 22, count 0 2006.286.03:12:13.10#ibcon#read 4, iclass 22, count 0 2006.286.03:12:13.10#ibcon#about to read 5, iclass 22, count 0 2006.286.03:12:13.10#ibcon#read 5, iclass 22, count 0 2006.286.03:12:13.10#ibcon#about to read 6, iclass 22, count 0 2006.286.03:12:13.10#ibcon#read 6, iclass 22, count 0 2006.286.03:12:13.10#ibcon#end of sib2, iclass 22, count 0 2006.286.03:12:13.10#ibcon#*after write, iclass 22, count 0 2006.286.03:12:13.10#ibcon#*before return 0, iclass 22, count 0 2006.286.03:12:13.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:12:13.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:12:13.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.03:12:13.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.03:12:13.10$vck44/vb=3,4 2006.286.03:12:13.10#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.03:12:13.10#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.03:12:13.10#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:13.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:12:13.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:12:13.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:12:13.16#ibcon#enter wrdev, iclass 24, count 2 2006.286.03:12:13.16#ibcon#first serial, iclass 24, count 2 2006.286.03:12:13.16#ibcon#enter sib2, iclass 24, count 2 2006.286.03:12:13.16#ibcon#flushed, iclass 24, count 2 2006.286.03:12:13.16#ibcon#about to write, iclass 24, count 2 2006.286.03:12:13.16#ibcon#wrote, iclass 24, count 2 2006.286.03:12:13.16#ibcon#about to read 3, iclass 24, count 2 2006.286.03:12:13.18#ibcon#read 3, iclass 24, count 2 2006.286.03:12:13.18#ibcon#about to read 4, iclass 24, count 2 2006.286.03:12:13.18#ibcon#read 4, iclass 24, count 2 2006.286.03:12:13.18#ibcon#about to read 5, iclass 24, count 2 2006.286.03:12:13.18#ibcon#read 5, iclass 24, count 2 2006.286.03:12:13.18#ibcon#about to read 6, iclass 24, count 2 2006.286.03:12:13.18#ibcon#read 6, iclass 24, count 2 2006.286.03:12:13.18#ibcon#end of sib2, iclass 24, count 2 2006.286.03:12:13.18#ibcon#*mode == 0, iclass 24, count 2 2006.286.03:12:13.18#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.03:12:13.18#ibcon#[27=AT03-04\r\n] 2006.286.03:12:13.18#ibcon#*before write, iclass 24, count 2 2006.286.03:12:13.18#ibcon#enter sib2, iclass 24, count 2 2006.286.03:12:13.18#ibcon#flushed, iclass 24, count 2 2006.286.03:12:13.18#ibcon#about to write, iclass 24, count 2 2006.286.03:12:13.18#ibcon#wrote, iclass 24, count 2 2006.286.03:12:13.18#ibcon#about to read 3, iclass 24, count 2 2006.286.03:12:13.21#ibcon#read 3, iclass 24, count 2 2006.286.03:12:13.21#ibcon#about to read 4, iclass 24, count 2 2006.286.03:12:13.21#ibcon#read 4, iclass 24, count 2 2006.286.03:12:13.21#ibcon#about to read 5, iclass 24, count 2 2006.286.03:12:13.21#ibcon#read 5, iclass 24, count 2 2006.286.03:12:13.21#ibcon#about to read 6, iclass 24, count 2 2006.286.03:12:13.21#ibcon#read 6, iclass 24, count 2 2006.286.03:12:13.21#ibcon#end of sib2, iclass 24, count 2 2006.286.03:12:13.21#ibcon#*after write, iclass 24, count 2 2006.286.03:12:13.21#ibcon#*before return 0, iclass 24, count 2 2006.286.03:12:13.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:12:13.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:12:13.21#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.03:12:13.21#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:13.21#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:12:13.33#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:12:13.33#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:12:13.33#ibcon#enter wrdev, iclass 24, count 0 2006.286.03:12:13.33#ibcon#first serial, iclass 24, count 0 2006.286.03:12:13.33#ibcon#enter sib2, iclass 24, count 0 2006.286.03:12:13.33#ibcon#flushed, iclass 24, count 0 2006.286.03:12:13.33#ibcon#about to write, iclass 24, count 0 2006.286.03:12:13.33#ibcon#wrote, iclass 24, count 0 2006.286.03:12:13.33#ibcon#about to read 3, iclass 24, count 0 2006.286.03:12:13.35#ibcon#read 3, iclass 24, count 0 2006.286.03:12:13.35#ibcon#about to read 4, iclass 24, count 0 2006.286.03:12:13.35#ibcon#read 4, iclass 24, count 0 2006.286.03:12:13.35#ibcon#about to read 5, iclass 24, count 0 2006.286.03:12:13.35#ibcon#read 5, iclass 24, count 0 2006.286.03:12:13.35#ibcon#about to read 6, iclass 24, count 0 2006.286.03:12:13.35#ibcon#read 6, iclass 24, count 0 2006.286.03:12:13.35#ibcon#end of sib2, iclass 24, count 0 2006.286.03:12:13.35#ibcon#*mode == 0, iclass 24, count 0 2006.286.03:12:13.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.03:12:13.35#ibcon#[27=USB\r\n] 2006.286.03:12:13.35#ibcon#*before write, iclass 24, count 0 2006.286.03:12:13.35#ibcon#enter sib2, iclass 24, count 0 2006.286.03:12:13.35#ibcon#flushed, iclass 24, count 0 2006.286.03:12:13.35#ibcon#about to write, iclass 24, count 0 2006.286.03:12:13.35#ibcon#wrote, iclass 24, count 0 2006.286.03:12:13.35#ibcon#about to read 3, iclass 24, count 0 2006.286.03:12:13.38#ibcon#read 3, iclass 24, count 0 2006.286.03:12:13.38#ibcon#about to read 4, iclass 24, count 0 2006.286.03:12:13.38#ibcon#read 4, iclass 24, count 0 2006.286.03:12:13.38#ibcon#about to read 5, iclass 24, count 0 2006.286.03:12:13.38#ibcon#read 5, iclass 24, count 0 2006.286.03:12:13.38#ibcon#about to read 6, iclass 24, count 0 2006.286.03:12:13.38#ibcon#read 6, iclass 24, count 0 2006.286.03:12:13.38#ibcon#end of sib2, iclass 24, count 0 2006.286.03:12:13.38#ibcon#*after write, iclass 24, count 0 2006.286.03:12:13.38#ibcon#*before return 0, iclass 24, count 0 2006.286.03:12:13.38#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:12:13.38#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:12:13.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.03:12:13.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.03:12:13.38$vck44/vblo=4,679.99 2006.286.03:12:13.38#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.03:12:13.38#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.03:12:13.38#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:13.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:12:13.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:12:13.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:12:13.38#ibcon#enter wrdev, iclass 26, count 0 2006.286.03:12:13.38#ibcon#first serial, iclass 26, count 0 2006.286.03:12:13.38#ibcon#enter sib2, iclass 26, count 0 2006.286.03:12:13.38#ibcon#flushed, iclass 26, count 0 2006.286.03:12:13.38#ibcon#about to write, iclass 26, count 0 2006.286.03:12:13.55#ibcon#wrote, iclass 26, count 0 2006.286.03:12:13.55#ibcon#about to read 3, iclass 26, count 0 2006.286.03:12:13.57#ibcon#read 3, iclass 26, count 0 2006.286.03:12:13.57#ibcon#about to read 4, iclass 26, count 0 2006.286.03:12:13.57#ibcon#read 4, iclass 26, count 0 2006.286.03:12:13.57#ibcon#about to read 5, iclass 26, count 0 2006.286.03:12:13.57#ibcon#read 5, iclass 26, count 0 2006.286.03:12:13.57#ibcon#about to read 6, iclass 26, count 0 2006.286.03:12:13.57#ibcon#read 6, iclass 26, count 0 2006.286.03:12:13.57#ibcon#end of sib2, iclass 26, count 0 2006.286.03:12:13.57#ibcon#*mode == 0, iclass 26, count 0 2006.286.03:12:13.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.03:12:13.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.03:12:13.57#ibcon#*before write, iclass 26, count 0 2006.286.03:12:13.57#ibcon#enter sib2, iclass 26, count 0 2006.286.03:12:13.57#ibcon#flushed, iclass 26, count 0 2006.286.03:12:13.57#ibcon#about to write, iclass 26, count 0 2006.286.03:12:13.57#ibcon#wrote, iclass 26, count 0 2006.286.03:12:13.57#ibcon#about to read 3, iclass 26, count 0 2006.286.03:12:13.61#ibcon#read 3, iclass 26, count 0 2006.286.03:12:13.61#ibcon#about to read 4, iclass 26, count 0 2006.286.03:12:13.61#ibcon#read 4, iclass 26, count 0 2006.286.03:12:13.61#ibcon#about to read 5, iclass 26, count 0 2006.286.03:12:13.61#ibcon#read 5, iclass 26, count 0 2006.286.03:12:13.61#ibcon#about to read 6, iclass 26, count 0 2006.286.03:12:13.61#ibcon#read 6, iclass 26, count 0 2006.286.03:12:13.61#ibcon#end of sib2, iclass 26, count 0 2006.286.03:12:13.61#ibcon#*after write, iclass 26, count 0 2006.286.03:12:13.61#ibcon#*before return 0, iclass 26, count 0 2006.286.03:12:13.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:12:13.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:12:13.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.03:12:13.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.03:12:13.61$vck44/vb=4,5 2006.286.03:12:13.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.03:12:13.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.03:12:13.61#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:13.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:12:13.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:12:13.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:12:13.61#ibcon#enter wrdev, iclass 28, count 2 2006.286.03:12:13.61#ibcon#first serial, iclass 28, count 2 2006.286.03:12:13.61#ibcon#enter sib2, iclass 28, count 2 2006.286.03:12:13.61#ibcon#flushed, iclass 28, count 2 2006.286.03:12:13.61#ibcon#about to write, iclass 28, count 2 2006.286.03:12:13.61#ibcon#wrote, iclass 28, count 2 2006.286.03:12:13.61#ibcon#about to read 3, iclass 28, count 2 2006.286.03:12:13.63#ibcon#read 3, iclass 28, count 2 2006.286.03:12:13.63#ibcon#about to read 4, iclass 28, count 2 2006.286.03:12:13.63#ibcon#read 4, iclass 28, count 2 2006.286.03:12:13.63#ibcon#about to read 5, iclass 28, count 2 2006.286.03:12:13.63#ibcon#read 5, iclass 28, count 2 2006.286.03:12:13.63#ibcon#about to read 6, iclass 28, count 2 2006.286.03:12:13.63#ibcon#read 6, iclass 28, count 2 2006.286.03:12:13.63#ibcon#end of sib2, iclass 28, count 2 2006.286.03:12:13.63#ibcon#*mode == 0, iclass 28, count 2 2006.286.03:12:13.63#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.03:12:13.63#ibcon#[27=AT04-05\r\n] 2006.286.03:12:13.63#ibcon#*before write, iclass 28, count 2 2006.286.03:12:13.63#ibcon#enter sib2, iclass 28, count 2 2006.286.03:12:13.63#ibcon#flushed, iclass 28, count 2 2006.286.03:12:13.63#ibcon#about to write, iclass 28, count 2 2006.286.03:12:13.63#ibcon#wrote, iclass 28, count 2 2006.286.03:12:13.63#ibcon#about to read 3, iclass 28, count 2 2006.286.03:12:13.66#ibcon#read 3, iclass 28, count 2 2006.286.03:12:13.66#ibcon#about to read 4, iclass 28, count 2 2006.286.03:12:13.66#ibcon#read 4, iclass 28, count 2 2006.286.03:12:13.66#ibcon#about to read 5, iclass 28, count 2 2006.286.03:12:13.66#ibcon#read 5, iclass 28, count 2 2006.286.03:12:13.66#ibcon#about to read 6, iclass 28, count 2 2006.286.03:12:13.66#ibcon#read 6, iclass 28, count 2 2006.286.03:12:13.66#ibcon#end of sib2, iclass 28, count 2 2006.286.03:12:13.66#ibcon#*after write, iclass 28, count 2 2006.286.03:12:13.66#ibcon#*before return 0, iclass 28, count 2 2006.286.03:12:13.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:12:13.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:12:13.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.03:12:13.66#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:13.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:12:13.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:12:13.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:12:13.78#ibcon#enter wrdev, iclass 28, count 0 2006.286.03:12:13.78#ibcon#first serial, iclass 28, count 0 2006.286.03:12:13.78#ibcon#enter sib2, iclass 28, count 0 2006.286.03:12:13.78#ibcon#flushed, iclass 28, count 0 2006.286.03:12:13.78#ibcon#about to write, iclass 28, count 0 2006.286.03:12:13.78#ibcon#wrote, iclass 28, count 0 2006.286.03:12:13.78#ibcon#about to read 3, iclass 28, count 0 2006.286.03:12:13.80#ibcon#read 3, iclass 28, count 0 2006.286.03:12:13.80#ibcon#about to read 4, iclass 28, count 0 2006.286.03:12:13.80#ibcon#read 4, iclass 28, count 0 2006.286.03:12:13.80#ibcon#about to read 5, iclass 28, count 0 2006.286.03:12:13.80#ibcon#read 5, iclass 28, count 0 2006.286.03:12:13.80#ibcon#about to read 6, iclass 28, count 0 2006.286.03:12:13.80#ibcon#read 6, iclass 28, count 0 2006.286.03:12:13.80#ibcon#end of sib2, iclass 28, count 0 2006.286.03:12:13.80#ibcon#*mode == 0, iclass 28, count 0 2006.286.03:12:13.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.03:12:13.80#ibcon#[27=USB\r\n] 2006.286.03:12:13.80#ibcon#*before write, iclass 28, count 0 2006.286.03:12:13.80#ibcon#enter sib2, iclass 28, count 0 2006.286.03:12:13.80#ibcon#flushed, iclass 28, count 0 2006.286.03:12:13.80#ibcon#about to write, iclass 28, count 0 2006.286.03:12:13.80#ibcon#wrote, iclass 28, count 0 2006.286.03:12:13.80#ibcon#about to read 3, iclass 28, count 0 2006.286.03:12:13.83#ibcon#read 3, iclass 28, count 0 2006.286.03:12:13.83#ibcon#about to read 4, iclass 28, count 0 2006.286.03:12:13.83#ibcon#read 4, iclass 28, count 0 2006.286.03:12:13.83#ibcon#about to read 5, iclass 28, count 0 2006.286.03:12:13.83#ibcon#read 5, iclass 28, count 0 2006.286.03:12:13.83#ibcon#about to read 6, iclass 28, count 0 2006.286.03:12:13.83#ibcon#read 6, iclass 28, count 0 2006.286.03:12:13.83#ibcon#end of sib2, iclass 28, count 0 2006.286.03:12:13.83#ibcon#*after write, iclass 28, count 0 2006.286.03:12:13.83#ibcon#*before return 0, iclass 28, count 0 2006.286.03:12:13.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:12:13.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:12:13.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.03:12:13.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.03:12:13.83$vck44/vblo=5,709.99 2006.286.03:12:13.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.03:12:13.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.03:12:13.83#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:13.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:12:13.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:12:13.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:12:13.83#ibcon#enter wrdev, iclass 30, count 0 2006.286.03:12:13.83#ibcon#first serial, iclass 30, count 0 2006.286.03:12:13.83#ibcon#enter sib2, iclass 30, count 0 2006.286.03:12:13.83#ibcon#flushed, iclass 30, count 0 2006.286.03:12:13.83#ibcon#about to write, iclass 30, count 0 2006.286.03:12:13.83#ibcon#wrote, iclass 30, count 0 2006.286.03:12:13.83#ibcon#about to read 3, iclass 30, count 0 2006.286.03:12:13.85#ibcon#read 3, iclass 30, count 0 2006.286.03:12:13.85#ibcon#about to read 4, iclass 30, count 0 2006.286.03:12:13.85#ibcon#read 4, iclass 30, count 0 2006.286.03:12:13.85#ibcon#about to read 5, iclass 30, count 0 2006.286.03:12:13.85#ibcon#read 5, iclass 30, count 0 2006.286.03:12:13.85#ibcon#about to read 6, iclass 30, count 0 2006.286.03:12:13.85#ibcon#read 6, iclass 30, count 0 2006.286.03:12:13.85#ibcon#end of sib2, iclass 30, count 0 2006.286.03:12:13.85#ibcon#*mode == 0, iclass 30, count 0 2006.286.03:12:13.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.03:12:13.85#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.03:12:13.85#ibcon#*before write, iclass 30, count 0 2006.286.03:12:13.85#ibcon#enter sib2, iclass 30, count 0 2006.286.03:12:13.85#ibcon#flushed, iclass 30, count 0 2006.286.03:12:13.85#ibcon#about to write, iclass 30, count 0 2006.286.03:12:13.85#ibcon#wrote, iclass 30, count 0 2006.286.03:12:13.85#ibcon#about to read 3, iclass 30, count 0 2006.286.03:12:13.89#ibcon#read 3, iclass 30, count 0 2006.286.03:12:13.89#ibcon#about to read 4, iclass 30, count 0 2006.286.03:12:13.89#ibcon#read 4, iclass 30, count 0 2006.286.03:12:13.89#ibcon#about to read 5, iclass 30, count 0 2006.286.03:12:13.89#ibcon#read 5, iclass 30, count 0 2006.286.03:12:13.89#ibcon#about to read 6, iclass 30, count 0 2006.286.03:12:13.89#ibcon#read 6, iclass 30, count 0 2006.286.03:12:13.89#ibcon#end of sib2, iclass 30, count 0 2006.286.03:12:13.89#ibcon#*after write, iclass 30, count 0 2006.286.03:12:13.89#ibcon#*before return 0, iclass 30, count 0 2006.286.03:12:13.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:12:13.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:12:13.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.03:12:13.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.03:12:13.89$vck44/vb=5,4 2006.286.03:12:13.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.03:12:13.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.03:12:13.89#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:13.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:12:13.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:12:13.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:12:13.95#ibcon#enter wrdev, iclass 32, count 2 2006.286.03:12:13.95#ibcon#first serial, iclass 32, count 2 2006.286.03:12:13.95#ibcon#enter sib2, iclass 32, count 2 2006.286.03:12:13.95#ibcon#flushed, iclass 32, count 2 2006.286.03:12:13.95#ibcon#about to write, iclass 32, count 2 2006.286.03:12:13.95#ibcon#wrote, iclass 32, count 2 2006.286.03:12:13.95#ibcon#about to read 3, iclass 32, count 2 2006.286.03:12:13.97#ibcon#read 3, iclass 32, count 2 2006.286.03:12:13.97#ibcon#about to read 4, iclass 32, count 2 2006.286.03:12:13.97#ibcon#read 4, iclass 32, count 2 2006.286.03:12:13.97#ibcon#about to read 5, iclass 32, count 2 2006.286.03:12:13.97#ibcon#read 5, iclass 32, count 2 2006.286.03:12:13.97#ibcon#about to read 6, iclass 32, count 2 2006.286.03:12:13.97#ibcon#read 6, iclass 32, count 2 2006.286.03:12:13.97#ibcon#end of sib2, iclass 32, count 2 2006.286.03:12:13.97#ibcon#*mode == 0, iclass 32, count 2 2006.286.03:12:13.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.03:12:13.97#ibcon#[27=AT05-04\r\n] 2006.286.03:12:13.97#ibcon#*before write, iclass 32, count 2 2006.286.03:12:13.97#ibcon#enter sib2, iclass 32, count 2 2006.286.03:12:13.97#ibcon#flushed, iclass 32, count 2 2006.286.03:12:13.97#ibcon#about to write, iclass 32, count 2 2006.286.03:12:13.97#ibcon#wrote, iclass 32, count 2 2006.286.03:12:13.97#ibcon#about to read 3, iclass 32, count 2 2006.286.03:12:14.00#ibcon#read 3, iclass 32, count 2 2006.286.03:12:14.00#ibcon#about to read 4, iclass 32, count 2 2006.286.03:12:14.00#ibcon#read 4, iclass 32, count 2 2006.286.03:12:14.00#ibcon#about to read 5, iclass 32, count 2 2006.286.03:12:14.00#ibcon#read 5, iclass 32, count 2 2006.286.03:12:14.00#ibcon#about to read 6, iclass 32, count 2 2006.286.03:12:14.00#ibcon#read 6, iclass 32, count 2 2006.286.03:12:14.00#ibcon#end of sib2, iclass 32, count 2 2006.286.03:12:14.00#ibcon#*after write, iclass 32, count 2 2006.286.03:12:14.00#ibcon#*before return 0, iclass 32, count 2 2006.286.03:12:14.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:12:14.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:12:14.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.03:12:14.00#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:14.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:12:14.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:12:14.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:12:14.12#ibcon#enter wrdev, iclass 32, count 0 2006.286.03:12:14.12#ibcon#first serial, iclass 32, count 0 2006.286.03:12:14.12#ibcon#enter sib2, iclass 32, count 0 2006.286.03:12:14.12#ibcon#flushed, iclass 32, count 0 2006.286.03:12:14.12#ibcon#about to write, iclass 32, count 0 2006.286.03:12:14.12#ibcon#wrote, iclass 32, count 0 2006.286.03:12:14.12#ibcon#about to read 3, iclass 32, count 0 2006.286.03:12:14.14#ibcon#read 3, iclass 32, count 0 2006.286.03:12:14.14#ibcon#about to read 4, iclass 32, count 0 2006.286.03:12:14.14#ibcon#read 4, iclass 32, count 0 2006.286.03:12:14.14#ibcon#about to read 5, iclass 32, count 0 2006.286.03:12:14.14#ibcon#read 5, iclass 32, count 0 2006.286.03:12:14.14#ibcon#about to read 6, iclass 32, count 0 2006.286.03:12:14.14#ibcon#read 6, iclass 32, count 0 2006.286.03:12:14.14#ibcon#end of sib2, iclass 32, count 0 2006.286.03:12:14.14#ibcon#*mode == 0, iclass 32, count 0 2006.286.03:12:14.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.03:12:14.14#ibcon#[27=USB\r\n] 2006.286.03:12:14.14#ibcon#*before write, iclass 32, count 0 2006.286.03:12:14.14#ibcon#enter sib2, iclass 32, count 0 2006.286.03:12:14.14#ibcon#flushed, iclass 32, count 0 2006.286.03:12:14.14#ibcon#about to write, iclass 32, count 0 2006.286.03:12:14.14#ibcon#wrote, iclass 32, count 0 2006.286.03:12:14.14#ibcon#about to read 3, iclass 32, count 0 2006.286.03:12:14.17#ibcon#read 3, iclass 32, count 0 2006.286.03:12:14.17#ibcon#about to read 4, iclass 32, count 0 2006.286.03:12:14.17#ibcon#read 4, iclass 32, count 0 2006.286.03:12:14.17#ibcon#about to read 5, iclass 32, count 0 2006.286.03:12:14.17#ibcon#read 5, iclass 32, count 0 2006.286.03:12:14.17#ibcon#about to read 6, iclass 32, count 0 2006.286.03:12:14.17#ibcon#read 6, iclass 32, count 0 2006.286.03:12:14.17#ibcon#end of sib2, iclass 32, count 0 2006.286.03:12:14.17#ibcon#*after write, iclass 32, count 0 2006.286.03:12:14.17#ibcon#*before return 0, iclass 32, count 0 2006.286.03:12:14.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:12:14.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:12:14.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.03:12:14.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.03:12:14.17$vck44/vblo=6,719.99 2006.286.03:12:14.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.03:12:14.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.03:12:14.17#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:14.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:12:14.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:12:14.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:12:14.17#ibcon#enter wrdev, iclass 34, count 0 2006.286.03:12:14.17#ibcon#first serial, iclass 34, count 0 2006.286.03:12:14.17#ibcon#enter sib2, iclass 34, count 0 2006.286.03:12:14.17#ibcon#flushed, iclass 34, count 0 2006.286.03:12:14.17#ibcon#about to write, iclass 34, count 0 2006.286.03:12:14.17#ibcon#wrote, iclass 34, count 0 2006.286.03:12:14.17#ibcon#about to read 3, iclass 34, count 0 2006.286.03:12:14.19#ibcon#read 3, iclass 34, count 0 2006.286.03:12:14.19#ibcon#about to read 4, iclass 34, count 0 2006.286.03:12:14.19#ibcon#read 4, iclass 34, count 0 2006.286.03:12:14.19#ibcon#about to read 5, iclass 34, count 0 2006.286.03:12:14.19#ibcon#read 5, iclass 34, count 0 2006.286.03:12:14.19#ibcon#about to read 6, iclass 34, count 0 2006.286.03:12:14.19#ibcon#read 6, iclass 34, count 0 2006.286.03:12:14.19#ibcon#end of sib2, iclass 34, count 0 2006.286.03:12:14.19#ibcon#*mode == 0, iclass 34, count 0 2006.286.03:12:14.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.03:12:14.19#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.03:12:14.19#ibcon#*before write, iclass 34, count 0 2006.286.03:12:14.19#ibcon#enter sib2, iclass 34, count 0 2006.286.03:12:14.19#ibcon#flushed, iclass 34, count 0 2006.286.03:12:14.19#ibcon#about to write, iclass 34, count 0 2006.286.03:12:14.19#ibcon#wrote, iclass 34, count 0 2006.286.03:12:14.19#ibcon#about to read 3, iclass 34, count 0 2006.286.03:12:14.23#ibcon#read 3, iclass 34, count 0 2006.286.03:12:14.23#ibcon#about to read 4, iclass 34, count 0 2006.286.03:12:14.23#ibcon#read 4, iclass 34, count 0 2006.286.03:12:14.23#ibcon#about to read 5, iclass 34, count 0 2006.286.03:12:14.23#ibcon#read 5, iclass 34, count 0 2006.286.03:12:14.23#ibcon#about to read 6, iclass 34, count 0 2006.286.03:12:14.23#ibcon#read 6, iclass 34, count 0 2006.286.03:12:14.23#ibcon#end of sib2, iclass 34, count 0 2006.286.03:12:14.23#ibcon#*after write, iclass 34, count 0 2006.286.03:12:14.23#ibcon#*before return 0, iclass 34, count 0 2006.286.03:12:14.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:12:14.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:12:14.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.03:12:14.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.03:12:14.23$vck44/vb=6,3 2006.286.03:12:14.23#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.03:12:14.23#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.03:12:14.23#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:14.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:12:14.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:12:14.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:12:14.29#ibcon#enter wrdev, iclass 36, count 2 2006.286.03:12:14.29#ibcon#first serial, iclass 36, count 2 2006.286.03:12:14.29#ibcon#enter sib2, iclass 36, count 2 2006.286.03:12:14.29#ibcon#flushed, iclass 36, count 2 2006.286.03:12:14.29#ibcon#about to write, iclass 36, count 2 2006.286.03:12:14.29#ibcon#wrote, iclass 36, count 2 2006.286.03:12:14.29#ibcon#about to read 3, iclass 36, count 2 2006.286.03:12:14.31#ibcon#read 3, iclass 36, count 2 2006.286.03:12:14.31#ibcon#about to read 4, iclass 36, count 2 2006.286.03:12:14.31#ibcon#read 4, iclass 36, count 2 2006.286.03:12:14.31#ibcon#about to read 5, iclass 36, count 2 2006.286.03:12:14.31#ibcon#read 5, iclass 36, count 2 2006.286.03:12:14.31#ibcon#about to read 6, iclass 36, count 2 2006.286.03:12:14.31#ibcon#read 6, iclass 36, count 2 2006.286.03:12:14.31#ibcon#end of sib2, iclass 36, count 2 2006.286.03:12:14.31#ibcon#*mode == 0, iclass 36, count 2 2006.286.03:12:14.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.03:12:14.31#ibcon#[27=AT06-03\r\n] 2006.286.03:12:14.31#ibcon#*before write, iclass 36, count 2 2006.286.03:12:14.31#ibcon#enter sib2, iclass 36, count 2 2006.286.03:12:14.31#ibcon#flushed, iclass 36, count 2 2006.286.03:12:14.31#ibcon#about to write, iclass 36, count 2 2006.286.03:12:14.31#ibcon#wrote, iclass 36, count 2 2006.286.03:12:14.31#ibcon#about to read 3, iclass 36, count 2 2006.286.03:12:14.34#ibcon#read 3, iclass 36, count 2 2006.286.03:12:14.34#ibcon#about to read 4, iclass 36, count 2 2006.286.03:12:14.34#ibcon#read 4, iclass 36, count 2 2006.286.03:12:14.34#ibcon#about to read 5, iclass 36, count 2 2006.286.03:12:14.34#ibcon#read 5, iclass 36, count 2 2006.286.03:12:14.34#ibcon#about to read 6, iclass 36, count 2 2006.286.03:12:14.34#ibcon#read 6, iclass 36, count 2 2006.286.03:12:14.34#ibcon#end of sib2, iclass 36, count 2 2006.286.03:12:14.34#ibcon#*after write, iclass 36, count 2 2006.286.03:12:14.34#ibcon#*before return 0, iclass 36, count 2 2006.286.03:12:14.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:12:14.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:12:14.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.03:12:14.34#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:14.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:12:14.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:12:14.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:12:14.46#ibcon#enter wrdev, iclass 36, count 0 2006.286.03:12:14.46#ibcon#first serial, iclass 36, count 0 2006.286.03:12:14.46#ibcon#enter sib2, iclass 36, count 0 2006.286.03:12:14.46#ibcon#flushed, iclass 36, count 0 2006.286.03:12:14.46#ibcon#about to write, iclass 36, count 0 2006.286.03:12:14.46#ibcon#wrote, iclass 36, count 0 2006.286.03:12:14.46#ibcon#about to read 3, iclass 36, count 0 2006.286.03:12:14.48#ibcon#read 3, iclass 36, count 0 2006.286.03:12:14.48#ibcon#about to read 4, iclass 36, count 0 2006.286.03:12:14.48#ibcon#read 4, iclass 36, count 0 2006.286.03:12:14.48#ibcon#about to read 5, iclass 36, count 0 2006.286.03:12:14.48#ibcon#read 5, iclass 36, count 0 2006.286.03:12:14.48#ibcon#about to read 6, iclass 36, count 0 2006.286.03:12:14.48#ibcon#read 6, iclass 36, count 0 2006.286.03:12:14.48#ibcon#end of sib2, iclass 36, count 0 2006.286.03:12:14.48#ibcon#*mode == 0, iclass 36, count 0 2006.286.03:12:14.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.03:12:14.48#ibcon#[27=USB\r\n] 2006.286.03:12:14.48#ibcon#*before write, iclass 36, count 0 2006.286.03:12:14.48#ibcon#enter sib2, iclass 36, count 0 2006.286.03:12:14.48#ibcon#flushed, iclass 36, count 0 2006.286.03:12:14.48#ibcon#about to write, iclass 36, count 0 2006.286.03:12:14.48#ibcon#wrote, iclass 36, count 0 2006.286.03:12:14.48#ibcon#about to read 3, iclass 36, count 0 2006.286.03:12:14.51#ibcon#read 3, iclass 36, count 0 2006.286.03:12:14.51#ibcon#about to read 4, iclass 36, count 0 2006.286.03:12:14.51#ibcon#read 4, iclass 36, count 0 2006.286.03:12:14.51#ibcon#about to read 5, iclass 36, count 0 2006.286.03:12:14.51#ibcon#read 5, iclass 36, count 0 2006.286.03:12:14.51#ibcon#about to read 6, iclass 36, count 0 2006.286.03:12:14.51#ibcon#read 6, iclass 36, count 0 2006.286.03:12:14.51#ibcon#end of sib2, iclass 36, count 0 2006.286.03:12:14.51#ibcon#*after write, iclass 36, count 0 2006.286.03:12:14.51#ibcon#*before return 0, iclass 36, count 0 2006.286.03:12:14.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:12:14.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:12:14.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.03:12:14.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.03:12:14.51$vck44/vblo=7,734.99 2006.286.03:12:14.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.03:12:14.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.03:12:14.53#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:14.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:12:14.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:12:14.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:12:14.53#ibcon#enter wrdev, iclass 38, count 0 2006.286.03:12:14.53#ibcon#first serial, iclass 38, count 0 2006.286.03:12:14.53#ibcon#enter sib2, iclass 38, count 0 2006.286.03:12:14.53#ibcon#flushed, iclass 38, count 0 2006.286.03:12:14.53#ibcon#about to write, iclass 38, count 0 2006.286.03:12:14.53#ibcon#wrote, iclass 38, count 0 2006.286.03:12:14.53#ibcon#about to read 3, iclass 38, count 0 2006.286.03:12:14.55#ibcon#read 3, iclass 38, count 0 2006.286.03:12:14.55#ibcon#about to read 4, iclass 38, count 0 2006.286.03:12:14.55#ibcon#read 4, iclass 38, count 0 2006.286.03:12:14.55#ibcon#about to read 5, iclass 38, count 0 2006.286.03:12:14.55#ibcon#read 5, iclass 38, count 0 2006.286.03:12:14.55#ibcon#about to read 6, iclass 38, count 0 2006.286.03:12:14.55#ibcon#read 6, iclass 38, count 0 2006.286.03:12:14.55#ibcon#end of sib2, iclass 38, count 0 2006.286.03:12:14.55#ibcon#*mode == 0, iclass 38, count 0 2006.286.03:12:14.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.03:12:14.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.03:12:14.55#ibcon#*before write, iclass 38, count 0 2006.286.03:12:14.55#ibcon#enter sib2, iclass 38, count 0 2006.286.03:12:14.55#ibcon#flushed, iclass 38, count 0 2006.286.03:12:14.55#ibcon#about to write, iclass 38, count 0 2006.286.03:12:14.55#ibcon#wrote, iclass 38, count 0 2006.286.03:12:14.55#ibcon#about to read 3, iclass 38, count 0 2006.286.03:12:14.59#ibcon#read 3, iclass 38, count 0 2006.286.03:12:14.59#ibcon#about to read 4, iclass 38, count 0 2006.286.03:12:14.59#ibcon#read 4, iclass 38, count 0 2006.286.03:12:14.59#ibcon#about to read 5, iclass 38, count 0 2006.286.03:12:14.59#ibcon#read 5, iclass 38, count 0 2006.286.03:12:14.59#ibcon#about to read 6, iclass 38, count 0 2006.286.03:12:14.59#ibcon#read 6, iclass 38, count 0 2006.286.03:12:14.59#ibcon#end of sib2, iclass 38, count 0 2006.286.03:12:14.59#ibcon#*after write, iclass 38, count 0 2006.286.03:12:14.59#ibcon#*before return 0, iclass 38, count 0 2006.286.03:12:14.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:12:14.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:12:14.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.03:12:14.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.03:12:14.59$vck44/vb=7,4 2006.286.03:12:14.59#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.03:12:14.59#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.03:12:14.59#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:14.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:12:14.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:12:14.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:12:14.63#ibcon#enter wrdev, iclass 40, count 2 2006.286.03:12:14.63#ibcon#first serial, iclass 40, count 2 2006.286.03:12:14.63#ibcon#enter sib2, iclass 40, count 2 2006.286.03:12:14.63#ibcon#flushed, iclass 40, count 2 2006.286.03:12:14.63#ibcon#about to write, iclass 40, count 2 2006.286.03:12:14.63#ibcon#wrote, iclass 40, count 2 2006.286.03:12:14.63#ibcon#about to read 3, iclass 40, count 2 2006.286.03:12:14.65#ibcon#read 3, iclass 40, count 2 2006.286.03:12:14.65#ibcon#about to read 4, iclass 40, count 2 2006.286.03:12:14.65#ibcon#read 4, iclass 40, count 2 2006.286.03:12:14.65#ibcon#about to read 5, iclass 40, count 2 2006.286.03:12:14.65#ibcon#read 5, iclass 40, count 2 2006.286.03:12:14.65#ibcon#about to read 6, iclass 40, count 2 2006.286.03:12:14.65#ibcon#read 6, iclass 40, count 2 2006.286.03:12:14.65#ibcon#end of sib2, iclass 40, count 2 2006.286.03:12:14.65#ibcon#*mode == 0, iclass 40, count 2 2006.286.03:12:14.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.03:12:14.65#ibcon#[27=AT07-04\r\n] 2006.286.03:12:14.65#ibcon#*before write, iclass 40, count 2 2006.286.03:12:14.65#ibcon#enter sib2, iclass 40, count 2 2006.286.03:12:14.65#ibcon#flushed, iclass 40, count 2 2006.286.03:12:14.65#ibcon#about to write, iclass 40, count 2 2006.286.03:12:14.65#ibcon#wrote, iclass 40, count 2 2006.286.03:12:14.65#ibcon#about to read 3, iclass 40, count 2 2006.286.03:12:14.68#ibcon#read 3, iclass 40, count 2 2006.286.03:12:14.68#ibcon#about to read 4, iclass 40, count 2 2006.286.03:12:14.68#ibcon#read 4, iclass 40, count 2 2006.286.03:12:14.68#ibcon#about to read 5, iclass 40, count 2 2006.286.03:12:14.68#ibcon#read 5, iclass 40, count 2 2006.286.03:12:14.68#ibcon#about to read 6, iclass 40, count 2 2006.286.03:12:14.68#ibcon#read 6, iclass 40, count 2 2006.286.03:12:14.68#ibcon#end of sib2, iclass 40, count 2 2006.286.03:12:14.68#ibcon#*after write, iclass 40, count 2 2006.286.03:12:14.68#ibcon#*before return 0, iclass 40, count 2 2006.286.03:12:14.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:12:14.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:12:14.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.03:12:14.68#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:14.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:12:14.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:12:14.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:12:14.80#ibcon#enter wrdev, iclass 40, count 0 2006.286.03:12:14.80#ibcon#first serial, iclass 40, count 0 2006.286.03:12:14.80#ibcon#enter sib2, iclass 40, count 0 2006.286.03:12:14.80#ibcon#flushed, iclass 40, count 0 2006.286.03:12:14.80#ibcon#about to write, iclass 40, count 0 2006.286.03:12:14.80#ibcon#wrote, iclass 40, count 0 2006.286.03:12:14.80#ibcon#about to read 3, iclass 40, count 0 2006.286.03:12:14.82#ibcon#read 3, iclass 40, count 0 2006.286.03:12:14.82#ibcon#about to read 4, iclass 40, count 0 2006.286.03:12:14.82#ibcon#read 4, iclass 40, count 0 2006.286.03:12:14.82#ibcon#about to read 5, iclass 40, count 0 2006.286.03:12:14.82#ibcon#read 5, iclass 40, count 0 2006.286.03:12:14.82#ibcon#about to read 6, iclass 40, count 0 2006.286.03:12:14.82#ibcon#read 6, iclass 40, count 0 2006.286.03:12:14.82#ibcon#end of sib2, iclass 40, count 0 2006.286.03:12:14.82#ibcon#*mode == 0, iclass 40, count 0 2006.286.03:12:14.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.03:12:14.82#ibcon#[27=USB\r\n] 2006.286.03:12:14.82#ibcon#*before write, iclass 40, count 0 2006.286.03:12:14.82#ibcon#enter sib2, iclass 40, count 0 2006.286.03:12:14.82#ibcon#flushed, iclass 40, count 0 2006.286.03:12:14.82#ibcon#about to write, iclass 40, count 0 2006.286.03:12:14.82#ibcon#wrote, iclass 40, count 0 2006.286.03:12:14.82#ibcon#about to read 3, iclass 40, count 0 2006.286.03:12:14.85#ibcon#read 3, iclass 40, count 0 2006.286.03:12:14.85#ibcon#about to read 4, iclass 40, count 0 2006.286.03:12:14.85#ibcon#read 4, iclass 40, count 0 2006.286.03:12:14.85#ibcon#about to read 5, iclass 40, count 0 2006.286.03:12:14.85#ibcon#read 5, iclass 40, count 0 2006.286.03:12:14.85#ibcon#about to read 6, iclass 40, count 0 2006.286.03:12:14.85#ibcon#read 6, iclass 40, count 0 2006.286.03:12:14.85#ibcon#end of sib2, iclass 40, count 0 2006.286.03:12:14.85#ibcon#*after write, iclass 40, count 0 2006.286.03:12:14.85#ibcon#*before return 0, iclass 40, count 0 2006.286.03:12:14.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:12:14.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:12:14.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.03:12:14.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.03:12:14.85$vck44/vblo=8,744.99 2006.286.03:12:14.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.03:12:14.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.03:12:14.85#ibcon#ireg 17 cls_cnt 0 2006.286.03:12:14.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:12:14.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:12:14.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:12:14.85#ibcon#enter wrdev, iclass 4, count 0 2006.286.03:12:14.85#ibcon#first serial, iclass 4, count 0 2006.286.03:12:14.85#ibcon#enter sib2, iclass 4, count 0 2006.286.03:12:14.85#ibcon#flushed, iclass 4, count 0 2006.286.03:12:14.85#ibcon#about to write, iclass 4, count 0 2006.286.03:12:14.85#ibcon#wrote, iclass 4, count 0 2006.286.03:12:14.85#ibcon#about to read 3, iclass 4, count 0 2006.286.03:12:14.87#ibcon#read 3, iclass 4, count 0 2006.286.03:12:14.87#ibcon#about to read 4, iclass 4, count 0 2006.286.03:12:14.87#ibcon#read 4, iclass 4, count 0 2006.286.03:12:14.87#ibcon#about to read 5, iclass 4, count 0 2006.286.03:12:14.87#ibcon#read 5, iclass 4, count 0 2006.286.03:12:14.87#ibcon#about to read 6, iclass 4, count 0 2006.286.03:12:14.87#ibcon#read 6, iclass 4, count 0 2006.286.03:12:14.87#ibcon#end of sib2, iclass 4, count 0 2006.286.03:12:14.87#ibcon#*mode == 0, iclass 4, count 0 2006.286.03:12:14.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.03:12:14.87#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.03:12:14.87#ibcon#*before write, iclass 4, count 0 2006.286.03:12:14.87#ibcon#enter sib2, iclass 4, count 0 2006.286.03:12:14.87#ibcon#flushed, iclass 4, count 0 2006.286.03:12:14.87#ibcon#about to write, iclass 4, count 0 2006.286.03:12:14.87#ibcon#wrote, iclass 4, count 0 2006.286.03:12:14.87#ibcon#about to read 3, iclass 4, count 0 2006.286.03:12:14.91#ibcon#read 3, iclass 4, count 0 2006.286.03:12:14.91#ibcon#about to read 4, iclass 4, count 0 2006.286.03:12:14.91#ibcon#read 4, iclass 4, count 0 2006.286.03:12:14.91#ibcon#about to read 5, iclass 4, count 0 2006.286.03:12:14.91#ibcon#read 5, iclass 4, count 0 2006.286.03:12:14.91#ibcon#about to read 6, iclass 4, count 0 2006.286.03:12:14.91#ibcon#read 6, iclass 4, count 0 2006.286.03:12:14.91#ibcon#end of sib2, iclass 4, count 0 2006.286.03:12:14.91#ibcon#*after write, iclass 4, count 0 2006.286.03:12:14.91#ibcon#*before return 0, iclass 4, count 0 2006.286.03:12:14.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:12:14.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:12:14.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.03:12:14.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.03:12:14.91$vck44/vb=8,4 2006.286.03:12:14.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.03:12:14.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.03:12:14.91#ibcon#ireg 11 cls_cnt 2 2006.286.03:12:14.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.03:12:14.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.03:12:14.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.03:12:14.97#ibcon#enter wrdev, iclass 6, count 2 2006.286.03:12:14.97#ibcon#first serial, iclass 6, count 2 2006.286.03:12:14.97#ibcon#enter sib2, iclass 6, count 2 2006.286.03:12:14.97#ibcon#flushed, iclass 6, count 2 2006.286.03:12:14.97#ibcon#about to write, iclass 6, count 2 2006.286.03:12:14.97#ibcon#wrote, iclass 6, count 2 2006.286.03:12:14.97#ibcon#about to read 3, iclass 6, count 2 2006.286.03:12:14.99#ibcon#read 3, iclass 6, count 2 2006.286.03:12:14.99#ibcon#about to read 4, iclass 6, count 2 2006.286.03:12:14.99#ibcon#read 4, iclass 6, count 2 2006.286.03:12:14.99#ibcon#about to read 5, iclass 6, count 2 2006.286.03:12:14.99#ibcon#read 5, iclass 6, count 2 2006.286.03:12:14.99#ibcon#about to read 6, iclass 6, count 2 2006.286.03:12:14.99#ibcon#read 6, iclass 6, count 2 2006.286.03:12:14.99#ibcon#end of sib2, iclass 6, count 2 2006.286.03:12:14.99#ibcon#*mode == 0, iclass 6, count 2 2006.286.03:12:14.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.03:12:14.99#ibcon#[27=AT08-04\r\n] 2006.286.03:12:14.99#ibcon#*before write, iclass 6, count 2 2006.286.03:12:14.99#ibcon#enter sib2, iclass 6, count 2 2006.286.03:12:14.99#ibcon#flushed, iclass 6, count 2 2006.286.03:12:14.99#ibcon#about to write, iclass 6, count 2 2006.286.03:12:14.99#ibcon#wrote, iclass 6, count 2 2006.286.03:12:14.99#ibcon#about to read 3, iclass 6, count 2 2006.286.03:12:15.02#ibcon#read 3, iclass 6, count 2 2006.286.03:12:15.02#ibcon#about to read 4, iclass 6, count 2 2006.286.03:12:15.02#ibcon#read 4, iclass 6, count 2 2006.286.03:12:15.02#ibcon#about to read 5, iclass 6, count 2 2006.286.03:12:15.02#ibcon#read 5, iclass 6, count 2 2006.286.03:12:15.02#ibcon#about to read 6, iclass 6, count 2 2006.286.03:12:15.02#ibcon#read 6, iclass 6, count 2 2006.286.03:12:15.02#ibcon#end of sib2, iclass 6, count 2 2006.286.03:12:15.02#ibcon#*after write, iclass 6, count 2 2006.286.03:12:15.02#ibcon#*before return 0, iclass 6, count 2 2006.286.03:12:15.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.03:12:15.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.03:12:15.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.03:12:15.02#ibcon#ireg 7 cls_cnt 0 2006.286.03:12:15.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.03:12:15.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.03:12:15.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.03:12:15.14#ibcon#enter wrdev, iclass 6, count 0 2006.286.03:12:15.14#ibcon#first serial, iclass 6, count 0 2006.286.03:12:15.14#ibcon#enter sib2, iclass 6, count 0 2006.286.03:12:15.14#ibcon#flushed, iclass 6, count 0 2006.286.03:12:15.14#ibcon#about to write, iclass 6, count 0 2006.286.03:12:15.14#ibcon#wrote, iclass 6, count 0 2006.286.03:12:15.14#ibcon#about to read 3, iclass 6, count 0 2006.286.03:12:15.16#ibcon#read 3, iclass 6, count 0 2006.286.03:12:15.16#ibcon#about to read 4, iclass 6, count 0 2006.286.03:12:15.16#ibcon#read 4, iclass 6, count 0 2006.286.03:12:15.16#ibcon#about to read 5, iclass 6, count 0 2006.286.03:12:15.16#ibcon#read 5, iclass 6, count 0 2006.286.03:12:15.16#ibcon#about to read 6, iclass 6, count 0 2006.286.03:12:15.16#ibcon#read 6, iclass 6, count 0 2006.286.03:12:15.16#ibcon#end of sib2, iclass 6, count 0 2006.286.03:12:15.16#ibcon#*mode == 0, iclass 6, count 0 2006.286.03:12:15.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.03:12:15.16#ibcon#[27=USB\r\n] 2006.286.03:12:15.16#ibcon#*before write, iclass 6, count 0 2006.286.03:12:15.16#ibcon#enter sib2, iclass 6, count 0 2006.286.03:12:15.16#ibcon#flushed, iclass 6, count 0 2006.286.03:12:15.16#ibcon#about to write, iclass 6, count 0 2006.286.03:12:15.16#ibcon#wrote, iclass 6, count 0 2006.286.03:12:15.16#ibcon#about to read 3, iclass 6, count 0 2006.286.03:12:15.19#ibcon#read 3, iclass 6, count 0 2006.286.03:12:15.19#ibcon#about to read 4, iclass 6, count 0 2006.286.03:12:15.19#ibcon#read 4, iclass 6, count 0 2006.286.03:12:15.19#ibcon#about to read 5, iclass 6, count 0 2006.286.03:12:15.19#ibcon#read 5, iclass 6, count 0 2006.286.03:12:15.19#ibcon#about to read 6, iclass 6, count 0 2006.286.03:12:15.19#ibcon#read 6, iclass 6, count 0 2006.286.03:12:15.19#ibcon#end of sib2, iclass 6, count 0 2006.286.03:12:15.19#ibcon#*after write, iclass 6, count 0 2006.286.03:12:15.19#ibcon#*before return 0, iclass 6, count 0 2006.286.03:12:15.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.03:12:15.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.03:12:15.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.03:12:15.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.03:12:15.19$vck44/vabw=wide 2006.286.03:12:15.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.03:12:15.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.03:12:15.19#ibcon#ireg 8 cls_cnt 0 2006.286.03:12:15.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:12:15.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:12:15.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:12:15.19#ibcon#enter wrdev, iclass 10, count 0 2006.286.03:12:15.19#ibcon#first serial, iclass 10, count 0 2006.286.03:12:15.19#ibcon#enter sib2, iclass 10, count 0 2006.286.03:12:15.19#ibcon#flushed, iclass 10, count 0 2006.286.03:12:15.19#ibcon#about to write, iclass 10, count 0 2006.286.03:12:15.19#ibcon#wrote, iclass 10, count 0 2006.286.03:12:15.19#ibcon#about to read 3, iclass 10, count 0 2006.286.03:12:15.21#ibcon#read 3, iclass 10, count 0 2006.286.03:12:15.21#ibcon#about to read 4, iclass 10, count 0 2006.286.03:12:15.21#ibcon#read 4, iclass 10, count 0 2006.286.03:12:15.21#ibcon#about to read 5, iclass 10, count 0 2006.286.03:12:15.21#ibcon#read 5, iclass 10, count 0 2006.286.03:12:15.21#ibcon#about to read 6, iclass 10, count 0 2006.286.03:12:15.21#ibcon#read 6, iclass 10, count 0 2006.286.03:12:15.21#ibcon#end of sib2, iclass 10, count 0 2006.286.03:12:15.21#ibcon#*mode == 0, iclass 10, count 0 2006.286.03:12:15.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.03:12:15.21#ibcon#[25=BW32\r\n] 2006.286.03:12:15.21#ibcon#*before write, iclass 10, count 0 2006.286.03:12:15.21#ibcon#enter sib2, iclass 10, count 0 2006.286.03:12:15.21#ibcon#flushed, iclass 10, count 0 2006.286.03:12:15.21#ibcon#about to write, iclass 10, count 0 2006.286.03:12:15.21#ibcon#wrote, iclass 10, count 0 2006.286.03:12:15.21#ibcon#about to read 3, iclass 10, count 0 2006.286.03:12:15.24#ibcon#read 3, iclass 10, count 0 2006.286.03:12:15.24#ibcon#about to read 4, iclass 10, count 0 2006.286.03:12:15.24#ibcon#read 4, iclass 10, count 0 2006.286.03:12:15.24#ibcon#about to read 5, iclass 10, count 0 2006.286.03:12:15.24#ibcon#read 5, iclass 10, count 0 2006.286.03:12:15.24#ibcon#about to read 6, iclass 10, count 0 2006.286.03:12:15.24#ibcon#read 6, iclass 10, count 0 2006.286.03:12:15.24#ibcon#end of sib2, iclass 10, count 0 2006.286.03:12:15.24#ibcon#*after write, iclass 10, count 0 2006.286.03:12:15.24#ibcon#*before return 0, iclass 10, count 0 2006.286.03:12:15.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:12:15.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:12:15.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.03:12:15.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.03:12:15.24$vck44/vbbw=wide 2006.286.03:12:15.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.03:12:15.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.03:12:15.24#ibcon#ireg 8 cls_cnt 0 2006.286.03:12:15.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:12:15.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:12:15.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:12:15.31#ibcon#enter wrdev, iclass 12, count 0 2006.286.03:12:15.31#ibcon#first serial, iclass 12, count 0 2006.286.03:12:15.31#ibcon#enter sib2, iclass 12, count 0 2006.286.03:12:15.31#ibcon#flushed, iclass 12, count 0 2006.286.03:12:15.31#ibcon#about to write, iclass 12, count 0 2006.286.03:12:15.31#ibcon#wrote, iclass 12, count 0 2006.286.03:12:15.31#ibcon#about to read 3, iclass 12, count 0 2006.286.03:12:15.33#ibcon#read 3, iclass 12, count 0 2006.286.03:12:15.33#ibcon#about to read 4, iclass 12, count 0 2006.286.03:12:15.33#ibcon#read 4, iclass 12, count 0 2006.286.03:12:15.33#ibcon#about to read 5, iclass 12, count 0 2006.286.03:12:15.33#ibcon#read 5, iclass 12, count 0 2006.286.03:12:15.33#ibcon#about to read 6, iclass 12, count 0 2006.286.03:12:15.33#ibcon#read 6, iclass 12, count 0 2006.286.03:12:15.33#ibcon#end of sib2, iclass 12, count 0 2006.286.03:12:15.33#ibcon#*mode == 0, iclass 12, count 0 2006.286.03:12:15.33#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.03:12:15.33#ibcon#[27=BW32\r\n] 2006.286.03:12:15.33#ibcon#*before write, iclass 12, count 0 2006.286.03:12:15.33#ibcon#enter sib2, iclass 12, count 0 2006.286.03:12:15.33#ibcon#flushed, iclass 12, count 0 2006.286.03:12:15.33#ibcon#about to write, iclass 12, count 0 2006.286.03:12:15.33#ibcon#wrote, iclass 12, count 0 2006.286.03:12:15.33#ibcon#about to read 3, iclass 12, count 0 2006.286.03:12:15.36#ibcon#read 3, iclass 12, count 0 2006.286.03:12:15.36#ibcon#about to read 4, iclass 12, count 0 2006.286.03:12:15.36#ibcon#read 4, iclass 12, count 0 2006.286.03:12:15.36#ibcon#about to read 5, iclass 12, count 0 2006.286.03:12:15.36#ibcon#read 5, iclass 12, count 0 2006.286.03:12:15.36#ibcon#about to read 6, iclass 12, count 0 2006.286.03:12:15.36#ibcon#read 6, iclass 12, count 0 2006.286.03:12:15.36#ibcon#end of sib2, iclass 12, count 0 2006.286.03:12:15.36#ibcon#*after write, iclass 12, count 0 2006.286.03:12:15.36#ibcon#*before return 0, iclass 12, count 0 2006.286.03:12:15.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:12:15.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:12:15.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.03:12:15.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.03:12:15.36$setupk4/ifdk4 2006.286.03:12:15.36$ifdk4/lo= 2006.286.03:12:15.36$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.03:12:15.36$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.03:12:15.36$ifdk4/patch= 2006.286.03:12:15.36$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.03:12:15.36$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.03:12:15.36$setupk4/!*+20s 2006.286.03:12:16.02#abcon#<5=/04 2.8 6.2 21.69 771015.3\r\n> 2006.286.03:12:16.04#abcon#{5=INTERFACE CLEAR} 2006.286.03:12:16.10#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:12:26.19#abcon#<5=/04 2.8 6.2 21.69 771015.3\r\n> 2006.286.03:12:26.21#abcon#{5=INTERFACE CLEAR} 2006.286.03:12:26.27#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:12:28.86$setupk4/"tpicd 2006.286.03:12:28.86$setupk4/echo=off 2006.286.03:12:28.86$setupk4/xlog=off 2006.286.03:12:28.86:!2006.286.03:16:42 2006.286.03:13:38.14#trakl#Source acquired 2006.286.03:13:39.15#flagr#flagr/antenna,acquired 2006.286.03:16:42.01:preob 2006.286.03:16:43.14/onsource/TRACKING 2006.286.03:16:43.14:!2006.286.03:16:52 2006.286.03:16:52.00:"tape 2006.286.03:16:52.00:"st=record 2006.286.03:16:52.00:data_valid=on 2006.286.03:16:52.00:midob 2006.286.03:16:52.14/onsource/TRACKING 2006.286.03:16:52.15/wx/21.75,1015.2,78 2006.286.03:16:52.26/cable/+6.4985E-03 2006.286.03:16:53.35/va/01,07,usb,yes,46,50 2006.286.03:16:53.35/va/02,06,usb,yes,47,47 2006.286.03:16:53.35/va/03,07,usb,yes,46,48 2006.286.03:16:53.35/va/04,06,usb,yes,48,50 2006.286.03:16:53.35/va/05,03,usb,yes,47,48 2006.286.03:16:53.35/va/06,04,usb,yes,43,42 2006.286.03:16:53.35/va/07,04,usb,yes,44,45 2006.286.03:16:53.35/va/08,03,usb,yes,45,54 2006.286.03:16:53.58/valo/01,524.99,yes,locked 2006.286.03:16:53.58/valo/02,534.99,yes,locked 2006.286.03:16:53.58/valo/03,564.99,yes,locked 2006.286.03:16:53.58/valo/04,624.99,yes,locked 2006.286.03:16:53.58/valo/05,734.99,yes,locked 2006.286.03:16:53.58/valo/06,814.99,yes,locked 2006.286.03:16:53.58/valo/07,864.99,yes,locked 2006.286.03:16:53.58/valo/08,884.99,yes,locked 2006.286.03:16:54.67/vb/01,04,usb,yes,57,99 2006.286.03:16:54.67/vb/02,05,usb,yes,34,96 2006.286.03:16:54.67/vb/03,04,usb,yes,29,81 2006.286.03:16:54.67/vb/04,05,usb,yes,28,27 2006.286.03:16:54.67/vb/05,04,usb,yes,27,30 2006.286.03:16:54.67/vb/06,03,usb,yes,37,32 2006.286.03:16:54.67/vb/07,04,usb,yes,30,30 2006.286.03:16:54.67/vb/08,04,usb,yes,27,31 2006.286.03:16:54.90/vblo/01,629.99,yes,locked 2006.286.03:16:54.90/vblo/02,634.99,yes,locked 2006.286.03:16:54.90/vblo/03,649.99,yes,locked 2006.286.03:16:54.90/vblo/04,679.99,yes,locked 2006.286.03:16:54.90/vblo/05,709.99,yes,locked 2006.286.03:16:54.90/vblo/06,719.99,yes,locked 2006.286.03:16:54.90/vblo/07,734.99,yes,locked 2006.286.03:16:54.90/vblo/08,744.99,yes,locked 2006.286.03:16:55.05/vabw/8 2006.286.03:16:55.20/vbbw/8 2006.286.03:16:55.29/xfe/off,on,12.0 2006.286.03:16:55.66/ifatt/23,28,28,28 2006.286.03:16:56.06/fmout-gps/S +2.57E-07 2006.286.03:16:56.10:!2006.286.03:20:22 2006.286.03:20:22.01:data_valid=off 2006.286.03:20:22.01:"et 2006.286.03:20:22.01:!+3s 2006.286.03:20:25.04:"tape 2006.286.03:20:25.04:postob 2006.286.03:20:25.23/cable/+6.4980E-03 2006.286.03:20:25.23/wx/21.82,1015.2,77 2006.286.03:20:25.29/fmout-gps/S +2.56E-07 2006.286.03:20:25.29:scan_name=286-0321,jd0610,200 2006.286.03:20:25.29:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.286.03:20:26.14#flagr#flagr/antenna,new-source 2006.286.03:20:26.16:checkk5 2006.286.03:20:26.81/chk_autoobs//k5ts1/ autoobs is running! 2006.286.03:20:27.20/chk_autoobs//k5ts2/ autoobs is running! 2006.286.03:20:27.63/chk_autoobs//k5ts3/ autoobs is running! 2006.286.03:20:28.00/chk_autoobs//k5ts4/ autoobs is running! 2006.286.03:20:28.46/chk_obsdata//k5ts1/T2860316??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.286.03:20:28.87/chk_obsdata//k5ts2/T2860316??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.286.03:20:29.30/chk_obsdata//k5ts3/T2860316??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.286.03:20:29.88/chk_obsdata//k5ts4/T2860316??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.286.03:20:30.80/k5log//k5ts1_log_newline 2006.286.03:20:31.66/k5log//k5ts2_log_newline 2006.286.03:20:32.67/k5log//k5ts3_log_newline 2006.286.03:20:33.52/k5log//k5ts4_log_newline 2006.286.03:20:33.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.03:20:33.55:setupk4=1 2006.286.03:20:33.55$setupk4/echo=on 2006.286.03:20:33.55$setupk4/pcalon 2006.286.03:20:33.55$pcalon/"no phase cal control is implemented here 2006.286.03:20:33.55$setupk4/"tpicd=stop 2006.286.03:20:33.55$setupk4/"rec=synch_on 2006.286.03:20:33.55$setupk4/"rec_mode=128 2006.286.03:20:33.55$setupk4/!* 2006.286.03:20:33.55$setupk4/recpk4 2006.286.03:20:33.55$recpk4/recpatch= 2006.286.03:20:33.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.03:20:33.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.03:20:33.55$setupk4/vck44 2006.286.03:20:33.55$vck44/valo=1,524.99 2006.286.03:20:33.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.03:20:33.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.03:20:33.55#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:33.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:20:33.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:20:33.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:20:33.55#ibcon#enter wrdev, iclass 33, count 0 2006.286.03:20:33.55#ibcon#first serial, iclass 33, count 0 2006.286.03:20:33.55#ibcon#enter sib2, iclass 33, count 0 2006.286.03:20:33.55#ibcon#flushed, iclass 33, count 0 2006.286.03:20:33.55#ibcon#about to write, iclass 33, count 0 2006.286.03:20:33.55#ibcon#wrote, iclass 33, count 0 2006.286.03:20:33.55#ibcon#about to read 3, iclass 33, count 0 2006.286.03:20:33.56#ibcon#read 3, iclass 33, count 0 2006.286.03:20:33.56#ibcon#about to read 4, iclass 33, count 0 2006.286.03:20:33.56#ibcon#read 4, iclass 33, count 0 2006.286.03:20:33.56#ibcon#about to read 5, iclass 33, count 0 2006.286.03:20:33.56#ibcon#read 5, iclass 33, count 0 2006.286.03:20:33.56#ibcon#about to read 6, iclass 33, count 0 2006.286.03:20:33.56#ibcon#read 6, iclass 33, count 0 2006.286.03:20:33.56#ibcon#end of sib2, iclass 33, count 0 2006.286.03:20:33.56#ibcon#*mode == 0, iclass 33, count 0 2006.286.03:20:33.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.03:20:33.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.03:20:33.56#ibcon#*before write, iclass 33, count 0 2006.286.03:20:33.56#ibcon#enter sib2, iclass 33, count 0 2006.286.03:20:33.56#ibcon#flushed, iclass 33, count 0 2006.286.03:20:33.56#ibcon#about to write, iclass 33, count 0 2006.286.03:20:33.56#ibcon#wrote, iclass 33, count 0 2006.286.03:20:33.56#ibcon#about to read 3, iclass 33, count 0 2006.286.03:20:33.61#ibcon#read 3, iclass 33, count 0 2006.286.03:20:33.61#ibcon#about to read 4, iclass 33, count 0 2006.286.03:20:33.61#ibcon#read 4, iclass 33, count 0 2006.286.03:20:33.61#ibcon#about to read 5, iclass 33, count 0 2006.286.03:20:33.61#ibcon#read 5, iclass 33, count 0 2006.286.03:20:33.61#ibcon#about to read 6, iclass 33, count 0 2006.286.03:20:33.61#ibcon#read 6, iclass 33, count 0 2006.286.03:20:33.61#ibcon#end of sib2, iclass 33, count 0 2006.286.03:20:33.61#ibcon#*after write, iclass 33, count 0 2006.286.03:20:33.61#ibcon#*before return 0, iclass 33, count 0 2006.286.03:20:33.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:20:33.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:20:33.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.03:20:33.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.03:20:33.61$vck44/va=1,7 2006.286.03:20:33.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.03:20:33.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.03:20:33.61#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:33.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:20:33.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:20:33.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:20:33.61#ibcon#enter wrdev, iclass 35, count 2 2006.286.03:20:33.61#ibcon#first serial, iclass 35, count 2 2006.286.03:20:33.61#ibcon#enter sib2, iclass 35, count 2 2006.286.03:20:33.61#ibcon#flushed, iclass 35, count 2 2006.286.03:20:33.61#ibcon#about to write, iclass 35, count 2 2006.286.03:20:33.61#ibcon#wrote, iclass 35, count 2 2006.286.03:20:33.61#ibcon#about to read 3, iclass 35, count 2 2006.286.03:20:33.63#ibcon#read 3, iclass 35, count 2 2006.286.03:20:33.63#ibcon#about to read 4, iclass 35, count 2 2006.286.03:20:33.63#ibcon#read 4, iclass 35, count 2 2006.286.03:20:33.63#ibcon#about to read 5, iclass 35, count 2 2006.286.03:20:33.63#ibcon#read 5, iclass 35, count 2 2006.286.03:20:33.63#ibcon#about to read 6, iclass 35, count 2 2006.286.03:20:33.63#ibcon#read 6, iclass 35, count 2 2006.286.03:20:33.63#ibcon#end of sib2, iclass 35, count 2 2006.286.03:20:33.63#ibcon#*mode == 0, iclass 35, count 2 2006.286.03:20:33.63#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.03:20:33.63#ibcon#[25=AT01-07\r\n] 2006.286.03:20:33.63#ibcon#*before write, iclass 35, count 2 2006.286.03:20:33.63#ibcon#enter sib2, iclass 35, count 2 2006.286.03:20:33.63#ibcon#flushed, iclass 35, count 2 2006.286.03:20:33.63#ibcon#about to write, iclass 35, count 2 2006.286.03:20:33.63#ibcon#wrote, iclass 35, count 2 2006.286.03:20:33.63#ibcon#about to read 3, iclass 35, count 2 2006.286.03:20:33.66#ibcon#read 3, iclass 35, count 2 2006.286.03:20:33.66#ibcon#about to read 4, iclass 35, count 2 2006.286.03:20:33.66#ibcon#read 4, iclass 35, count 2 2006.286.03:20:33.66#ibcon#about to read 5, iclass 35, count 2 2006.286.03:20:33.66#ibcon#read 5, iclass 35, count 2 2006.286.03:20:33.66#ibcon#about to read 6, iclass 35, count 2 2006.286.03:20:33.66#ibcon#read 6, iclass 35, count 2 2006.286.03:20:33.66#ibcon#end of sib2, iclass 35, count 2 2006.286.03:20:33.66#ibcon#*after write, iclass 35, count 2 2006.286.03:20:33.66#ibcon#*before return 0, iclass 35, count 2 2006.286.03:20:33.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:20:33.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:20:33.66#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.03:20:33.66#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:33.66#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:20:33.78#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:20:33.78#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:20:33.78#ibcon#enter wrdev, iclass 35, count 0 2006.286.03:20:33.78#ibcon#first serial, iclass 35, count 0 2006.286.03:20:33.78#ibcon#enter sib2, iclass 35, count 0 2006.286.03:20:33.78#ibcon#flushed, iclass 35, count 0 2006.286.03:20:33.78#ibcon#about to write, iclass 35, count 0 2006.286.03:20:33.78#ibcon#wrote, iclass 35, count 0 2006.286.03:20:33.78#ibcon#about to read 3, iclass 35, count 0 2006.286.03:20:33.80#ibcon#read 3, iclass 35, count 0 2006.286.03:20:33.80#ibcon#about to read 4, iclass 35, count 0 2006.286.03:20:33.80#ibcon#read 4, iclass 35, count 0 2006.286.03:20:33.80#ibcon#about to read 5, iclass 35, count 0 2006.286.03:20:33.80#ibcon#read 5, iclass 35, count 0 2006.286.03:20:33.80#ibcon#about to read 6, iclass 35, count 0 2006.286.03:20:33.80#ibcon#read 6, iclass 35, count 0 2006.286.03:20:33.80#ibcon#end of sib2, iclass 35, count 0 2006.286.03:20:33.80#ibcon#*mode == 0, iclass 35, count 0 2006.286.03:20:33.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.03:20:33.80#ibcon#[25=USB\r\n] 2006.286.03:20:33.80#ibcon#*before write, iclass 35, count 0 2006.286.03:20:33.80#ibcon#enter sib2, iclass 35, count 0 2006.286.03:20:33.80#ibcon#flushed, iclass 35, count 0 2006.286.03:20:33.80#ibcon#about to write, iclass 35, count 0 2006.286.03:20:33.80#ibcon#wrote, iclass 35, count 0 2006.286.03:20:33.80#ibcon#about to read 3, iclass 35, count 0 2006.286.03:20:33.83#ibcon#read 3, iclass 35, count 0 2006.286.03:20:33.83#ibcon#about to read 4, iclass 35, count 0 2006.286.03:20:33.83#ibcon#read 4, iclass 35, count 0 2006.286.03:20:33.83#ibcon#about to read 5, iclass 35, count 0 2006.286.03:20:33.83#ibcon#read 5, iclass 35, count 0 2006.286.03:20:33.83#ibcon#about to read 6, iclass 35, count 0 2006.286.03:20:33.83#ibcon#read 6, iclass 35, count 0 2006.286.03:20:33.83#ibcon#end of sib2, iclass 35, count 0 2006.286.03:20:33.83#ibcon#*after write, iclass 35, count 0 2006.286.03:20:33.83#ibcon#*before return 0, iclass 35, count 0 2006.286.03:20:33.83#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:20:33.83#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:20:33.83#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.03:20:33.83#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.03:20:33.83$vck44/valo=2,534.99 2006.286.03:20:33.83#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.03:20:33.83#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.03:20:33.83#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:33.83#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:20:33.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:20:33.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:20:33.83#ibcon#enter wrdev, iclass 37, count 0 2006.286.03:20:33.83#ibcon#first serial, iclass 37, count 0 2006.286.03:20:33.83#ibcon#enter sib2, iclass 37, count 0 2006.286.03:20:33.83#ibcon#flushed, iclass 37, count 0 2006.286.03:20:33.83#ibcon#about to write, iclass 37, count 0 2006.286.03:20:33.83#ibcon#wrote, iclass 37, count 0 2006.286.03:20:33.83#ibcon#about to read 3, iclass 37, count 0 2006.286.03:20:33.85#ibcon#read 3, iclass 37, count 0 2006.286.03:20:33.85#ibcon#about to read 4, iclass 37, count 0 2006.286.03:20:33.85#ibcon#read 4, iclass 37, count 0 2006.286.03:20:33.85#ibcon#about to read 5, iclass 37, count 0 2006.286.03:20:33.85#ibcon#read 5, iclass 37, count 0 2006.286.03:20:33.85#ibcon#about to read 6, iclass 37, count 0 2006.286.03:20:33.85#ibcon#read 6, iclass 37, count 0 2006.286.03:20:33.85#ibcon#end of sib2, iclass 37, count 0 2006.286.03:20:33.85#ibcon#*mode == 0, iclass 37, count 0 2006.286.03:20:33.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.03:20:33.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.03:20:33.85#ibcon#*before write, iclass 37, count 0 2006.286.03:20:33.85#ibcon#enter sib2, iclass 37, count 0 2006.286.03:20:33.85#ibcon#flushed, iclass 37, count 0 2006.286.03:20:33.85#ibcon#about to write, iclass 37, count 0 2006.286.03:20:33.85#ibcon#wrote, iclass 37, count 0 2006.286.03:20:33.85#ibcon#about to read 3, iclass 37, count 0 2006.286.03:20:33.89#ibcon#read 3, iclass 37, count 0 2006.286.03:20:33.89#ibcon#about to read 4, iclass 37, count 0 2006.286.03:20:33.89#ibcon#read 4, iclass 37, count 0 2006.286.03:20:33.89#ibcon#about to read 5, iclass 37, count 0 2006.286.03:20:33.89#ibcon#read 5, iclass 37, count 0 2006.286.03:20:33.89#ibcon#about to read 6, iclass 37, count 0 2006.286.03:20:33.89#ibcon#read 6, iclass 37, count 0 2006.286.03:20:33.89#ibcon#end of sib2, iclass 37, count 0 2006.286.03:20:33.89#ibcon#*after write, iclass 37, count 0 2006.286.03:20:33.89#ibcon#*before return 0, iclass 37, count 0 2006.286.03:20:33.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:20:33.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:20:33.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.03:20:33.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.03:20:33.89$vck44/va=2,6 2006.286.03:20:33.89#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.03:20:33.89#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.03:20:33.89#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:33.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:20:33.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:20:33.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:20:33.95#ibcon#enter wrdev, iclass 39, count 2 2006.286.03:20:33.95#ibcon#first serial, iclass 39, count 2 2006.286.03:20:33.95#ibcon#enter sib2, iclass 39, count 2 2006.286.03:20:33.95#ibcon#flushed, iclass 39, count 2 2006.286.03:20:33.95#ibcon#about to write, iclass 39, count 2 2006.286.03:20:33.95#ibcon#wrote, iclass 39, count 2 2006.286.03:20:33.95#ibcon#about to read 3, iclass 39, count 2 2006.286.03:20:33.97#ibcon#read 3, iclass 39, count 2 2006.286.03:20:33.97#ibcon#about to read 4, iclass 39, count 2 2006.286.03:20:33.97#ibcon#read 4, iclass 39, count 2 2006.286.03:20:33.97#ibcon#about to read 5, iclass 39, count 2 2006.286.03:20:33.97#ibcon#read 5, iclass 39, count 2 2006.286.03:20:33.97#ibcon#about to read 6, iclass 39, count 2 2006.286.03:20:33.97#ibcon#read 6, iclass 39, count 2 2006.286.03:20:33.97#ibcon#end of sib2, iclass 39, count 2 2006.286.03:20:33.97#ibcon#*mode == 0, iclass 39, count 2 2006.286.03:20:33.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.03:20:33.97#ibcon#[25=AT02-06\r\n] 2006.286.03:20:33.97#ibcon#*before write, iclass 39, count 2 2006.286.03:20:33.97#ibcon#enter sib2, iclass 39, count 2 2006.286.03:20:33.97#ibcon#flushed, iclass 39, count 2 2006.286.03:20:33.97#ibcon#about to write, iclass 39, count 2 2006.286.03:20:33.97#ibcon#wrote, iclass 39, count 2 2006.286.03:20:33.97#ibcon#about to read 3, iclass 39, count 2 2006.286.03:20:34.00#ibcon#read 3, iclass 39, count 2 2006.286.03:20:34.00#ibcon#about to read 4, iclass 39, count 2 2006.286.03:20:34.00#ibcon#read 4, iclass 39, count 2 2006.286.03:20:34.00#ibcon#about to read 5, iclass 39, count 2 2006.286.03:20:34.00#ibcon#read 5, iclass 39, count 2 2006.286.03:20:34.00#ibcon#about to read 6, iclass 39, count 2 2006.286.03:20:34.00#ibcon#read 6, iclass 39, count 2 2006.286.03:20:34.00#ibcon#end of sib2, iclass 39, count 2 2006.286.03:20:34.00#ibcon#*after write, iclass 39, count 2 2006.286.03:20:34.00#ibcon#*before return 0, iclass 39, count 2 2006.286.03:20:34.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:20:34.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:20:34.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.03:20:34.00#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:34.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:20:34.12#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:20:34.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:20:34.12#ibcon#enter wrdev, iclass 39, count 0 2006.286.03:20:34.12#ibcon#first serial, iclass 39, count 0 2006.286.03:20:34.12#ibcon#enter sib2, iclass 39, count 0 2006.286.03:20:34.12#ibcon#flushed, iclass 39, count 0 2006.286.03:20:34.12#ibcon#about to write, iclass 39, count 0 2006.286.03:20:34.12#ibcon#wrote, iclass 39, count 0 2006.286.03:20:34.12#ibcon#about to read 3, iclass 39, count 0 2006.286.03:20:34.14#ibcon#read 3, iclass 39, count 0 2006.286.03:20:34.14#ibcon#about to read 4, iclass 39, count 0 2006.286.03:20:34.14#ibcon#read 4, iclass 39, count 0 2006.286.03:20:34.14#ibcon#about to read 5, iclass 39, count 0 2006.286.03:20:34.14#ibcon#read 5, iclass 39, count 0 2006.286.03:20:34.14#ibcon#about to read 6, iclass 39, count 0 2006.286.03:20:34.14#ibcon#read 6, iclass 39, count 0 2006.286.03:20:34.14#ibcon#end of sib2, iclass 39, count 0 2006.286.03:20:34.14#ibcon#*mode == 0, iclass 39, count 0 2006.286.03:20:34.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.03:20:34.14#ibcon#[25=USB\r\n] 2006.286.03:20:34.14#ibcon#*before write, iclass 39, count 0 2006.286.03:20:34.14#ibcon#enter sib2, iclass 39, count 0 2006.286.03:20:34.14#ibcon#flushed, iclass 39, count 0 2006.286.03:20:34.14#ibcon#about to write, iclass 39, count 0 2006.286.03:20:34.14#ibcon#wrote, iclass 39, count 0 2006.286.03:20:34.14#ibcon#about to read 3, iclass 39, count 0 2006.286.03:20:34.17#ibcon#read 3, iclass 39, count 0 2006.286.03:20:34.17#ibcon#about to read 4, iclass 39, count 0 2006.286.03:20:34.17#ibcon#read 4, iclass 39, count 0 2006.286.03:20:34.17#ibcon#about to read 5, iclass 39, count 0 2006.286.03:20:34.17#ibcon#read 5, iclass 39, count 0 2006.286.03:20:34.17#ibcon#about to read 6, iclass 39, count 0 2006.286.03:20:34.17#ibcon#read 6, iclass 39, count 0 2006.286.03:20:34.17#ibcon#end of sib2, iclass 39, count 0 2006.286.03:20:34.17#ibcon#*after write, iclass 39, count 0 2006.286.03:20:34.17#ibcon#*before return 0, iclass 39, count 0 2006.286.03:20:34.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:20:34.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:20:34.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.03:20:34.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.03:20:34.17$vck44/valo=3,564.99 2006.286.03:20:34.17#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.03:20:34.17#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.03:20:34.17#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:34.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:20:34.17#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:20:34.17#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:20:34.17#ibcon#enter wrdev, iclass 3, count 0 2006.286.03:20:34.17#ibcon#first serial, iclass 3, count 0 2006.286.03:20:34.17#ibcon#enter sib2, iclass 3, count 0 2006.286.03:20:34.17#ibcon#flushed, iclass 3, count 0 2006.286.03:20:34.17#ibcon#about to write, iclass 3, count 0 2006.286.03:20:34.17#ibcon#wrote, iclass 3, count 0 2006.286.03:20:34.17#ibcon#about to read 3, iclass 3, count 0 2006.286.03:20:34.19#ibcon#read 3, iclass 3, count 0 2006.286.03:20:34.19#ibcon#about to read 4, iclass 3, count 0 2006.286.03:20:34.19#ibcon#read 4, iclass 3, count 0 2006.286.03:20:34.19#ibcon#about to read 5, iclass 3, count 0 2006.286.03:20:34.19#ibcon#read 5, iclass 3, count 0 2006.286.03:20:34.19#ibcon#about to read 6, iclass 3, count 0 2006.286.03:20:34.19#ibcon#read 6, iclass 3, count 0 2006.286.03:20:34.19#ibcon#end of sib2, iclass 3, count 0 2006.286.03:20:34.19#ibcon#*mode == 0, iclass 3, count 0 2006.286.03:20:34.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.03:20:34.19#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.03:20:34.19#ibcon#*before write, iclass 3, count 0 2006.286.03:20:34.19#ibcon#enter sib2, iclass 3, count 0 2006.286.03:20:34.19#ibcon#flushed, iclass 3, count 0 2006.286.03:20:34.19#ibcon#about to write, iclass 3, count 0 2006.286.03:20:34.19#ibcon#wrote, iclass 3, count 0 2006.286.03:20:34.19#ibcon#about to read 3, iclass 3, count 0 2006.286.03:20:34.23#ibcon#read 3, iclass 3, count 0 2006.286.03:20:34.23#ibcon#about to read 4, iclass 3, count 0 2006.286.03:20:34.23#ibcon#read 4, iclass 3, count 0 2006.286.03:20:34.23#ibcon#about to read 5, iclass 3, count 0 2006.286.03:20:34.23#ibcon#read 5, iclass 3, count 0 2006.286.03:20:34.23#ibcon#about to read 6, iclass 3, count 0 2006.286.03:20:34.23#ibcon#read 6, iclass 3, count 0 2006.286.03:20:34.23#ibcon#end of sib2, iclass 3, count 0 2006.286.03:20:34.23#ibcon#*after write, iclass 3, count 0 2006.286.03:20:34.23#ibcon#*before return 0, iclass 3, count 0 2006.286.03:20:34.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:20:34.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:20:34.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.03:20:34.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.03:20:34.23$vck44/va=3,7 2006.286.03:20:34.23#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.03:20:34.23#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.03:20:34.23#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:34.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:20:34.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:20:34.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:20:34.29#ibcon#enter wrdev, iclass 5, count 2 2006.286.03:20:34.29#ibcon#first serial, iclass 5, count 2 2006.286.03:20:34.29#ibcon#enter sib2, iclass 5, count 2 2006.286.03:20:34.29#ibcon#flushed, iclass 5, count 2 2006.286.03:20:34.29#ibcon#about to write, iclass 5, count 2 2006.286.03:20:34.29#ibcon#wrote, iclass 5, count 2 2006.286.03:20:34.29#ibcon#about to read 3, iclass 5, count 2 2006.286.03:20:34.31#ibcon#read 3, iclass 5, count 2 2006.286.03:20:34.31#ibcon#about to read 4, iclass 5, count 2 2006.286.03:20:34.31#ibcon#read 4, iclass 5, count 2 2006.286.03:20:34.31#ibcon#about to read 5, iclass 5, count 2 2006.286.03:20:34.31#ibcon#read 5, iclass 5, count 2 2006.286.03:20:34.31#ibcon#about to read 6, iclass 5, count 2 2006.286.03:20:34.31#ibcon#read 6, iclass 5, count 2 2006.286.03:20:34.31#ibcon#end of sib2, iclass 5, count 2 2006.286.03:20:34.31#ibcon#*mode == 0, iclass 5, count 2 2006.286.03:20:34.31#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.03:20:34.31#ibcon#[25=AT03-07\r\n] 2006.286.03:20:34.31#ibcon#*before write, iclass 5, count 2 2006.286.03:20:34.31#ibcon#enter sib2, iclass 5, count 2 2006.286.03:20:34.31#ibcon#flushed, iclass 5, count 2 2006.286.03:20:34.31#ibcon#about to write, iclass 5, count 2 2006.286.03:20:34.31#ibcon#wrote, iclass 5, count 2 2006.286.03:20:34.31#ibcon#about to read 3, iclass 5, count 2 2006.286.03:20:34.34#abcon#<5=/04 3.2 6.5 21.83 771015.2\r\n> 2006.286.03:20:34.34#ibcon#read 3, iclass 5, count 2 2006.286.03:20:34.34#ibcon#about to read 4, iclass 5, count 2 2006.286.03:20:34.34#ibcon#read 4, iclass 5, count 2 2006.286.03:20:34.34#ibcon#about to read 5, iclass 5, count 2 2006.286.03:20:34.34#ibcon#read 5, iclass 5, count 2 2006.286.03:20:34.34#ibcon#about to read 6, iclass 5, count 2 2006.286.03:20:34.34#ibcon#read 6, iclass 5, count 2 2006.286.03:20:34.34#ibcon#end of sib2, iclass 5, count 2 2006.286.03:20:34.34#ibcon#*after write, iclass 5, count 2 2006.286.03:20:34.34#ibcon#*before return 0, iclass 5, count 2 2006.286.03:20:34.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:20:34.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:20:34.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.03:20:34.34#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:34.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:20:34.36#abcon#{5=INTERFACE CLEAR} 2006.286.03:20:34.46#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:20:35.07#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:20:35.07#ibcon#enter wrdev, iclass 5, count 0 2006.286.03:20:35.07#ibcon#first serial, iclass 5, count 0 2006.286.03:20:35.07#ibcon#enter sib2, iclass 5, count 0 2006.286.03:20:35.07#ibcon#flushed, iclass 5, count 0 2006.286.03:20:35.07#ibcon#about to write, iclass 5, count 0 2006.286.03:20:35.07#ibcon#wrote, iclass 5, count 0 2006.286.03:20:35.07#ibcon#about to read 3, iclass 5, count 0 2006.286.03:20:35.08#ibcon#read 3, iclass 5, count 0 2006.286.03:20:35.08#ibcon#about to read 4, iclass 5, count 0 2006.286.03:20:35.08#ibcon#read 4, iclass 5, count 0 2006.286.03:20:35.08#ibcon#about to read 5, iclass 5, count 0 2006.286.03:20:35.08#ibcon#read 5, iclass 5, count 0 2006.286.03:20:35.08#ibcon#about to read 6, iclass 5, count 0 2006.286.03:20:35.08#ibcon#read 6, iclass 5, count 0 2006.286.03:20:35.08#ibcon#end of sib2, iclass 5, count 0 2006.286.03:20:35.08#ibcon#*mode == 0, iclass 5, count 0 2006.286.03:20:35.08#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.03:20:35.08#ibcon#[25=USB\r\n] 2006.286.03:20:35.08#ibcon#*before write, iclass 5, count 0 2006.286.03:20:35.08#ibcon#enter sib2, iclass 5, count 0 2006.286.03:20:35.08#ibcon#flushed, iclass 5, count 0 2006.286.03:20:35.08#ibcon#about to write, iclass 5, count 0 2006.286.03:20:35.08#ibcon#wrote, iclass 5, count 0 2006.286.03:20:35.08#ibcon#about to read 3, iclass 5, count 0 2006.286.03:20:35.11#ibcon#read 3, iclass 5, count 0 2006.286.03:20:35.11#ibcon#about to read 4, iclass 5, count 0 2006.286.03:20:35.11#ibcon#read 4, iclass 5, count 0 2006.286.03:20:35.11#ibcon#about to read 5, iclass 5, count 0 2006.286.03:20:35.11#ibcon#read 5, iclass 5, count 0 2006.286.03:20:35.11#ibcon#about to read 6, iclass 5, count 0 2006.286.03:20:35.11#ibcon#read 6, iclass 5, count 0 2006.286.03:20:35.11#ibcon#end of sib2, iclass 5, count 0 2006.286.03:20:35.11#ibcon#*after write, iclass 5, count 0 2006.286.03:20:35.11#ibcon#*before return 0, iclass 5, count 0 2006.286.03:20:35.11#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:20:35.11#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:20:35.11#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.03:20:35.11#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.03:20:35.11$vck44/valo=4,624.99 2006.286.03:20:35.11#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.03:20:35.11#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.03:20:35.11#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:35.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:20:35.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:20:35.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:20:35.11#ibcon#enter wrdev, iclass 13, count 0 2006.286.03:20:35.11#ibcon#first serial, iclass 13, count 0 2006.286.03:20:35.11#ibcon#enter sib2, iclass 13, count 0 2006.286.03:20:35.11#ibcon#flushed, iclass 13, count 0 2006.286.03:20:35.11#ibcon#about to write, iclass 13, count 0 2006.286.03:20:35.11#ibcon#wrote, iclass 13, count 0 2006.286.03:20:35.11#ibcon#about to read 3, iclass 13, count 0 2006.286.03:20:35.12#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:20:35.13#ibcon#read 3, iclass 13, count 0 2006.286.03:20:35.13#ibcon#about to read 4, iclass 13, count 0 2006.286.03:20:35.13#ibcon#read 4, iclass 13, count 0 2006.286.03:20:35.13#ibcon#about to read 5, iclass 13, count 0 2006.286.03:20:35.13#ibcon#read 5, iclass 13, count 0 2006.286.03:20:35.13#ibcon#about to read 6, iclass 13, count 0 2006.286.03:20:35.13#ibcon#read 6, iclass 13, count 0 2006.286.03:20:35.13#ibcon#end of sib2, iclass 13, count 0 2006.286.03:20:35.13#ibcon#*mode == 0, iclass 13, count 0 2006.286.03:20:35.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.03:20:35.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.03:20:35.13#ibcon#*before write, iclass 13, count 0 2006.286.03:20:35.13#ibcon#enter sib2, iclass 13, count 0 2006.286.03:20:35.13#ibcon#flushed, iclass 13, count 0 2006.286.03:20:35.13#ibcon#about to write, iclass 13, count 0 2006.286.03:20:35.13#ibcon#wrote, iclass 13, count 0 2006.286.03:20:35.13#ibcon#about to read 3, iclass 13, count 0 2006.286.03:20:35.17#ibcon#read 3, iclass 13, count 0 2006.286.03:20:35.17#ibcon#about to read 4, iclass 13, count 0 2006.286.03:20:35.17#ibcon#read 4, iclass 13, count 0 2006.286.03:20:35.17#ibcon#about to read 5, iclass 13, count 0 2006.286.03:20:35.17#ibcon#read 5, iclass 13, count 0 2006.286.03:20:35.17#ibcon#about to read 6, iclass 13, count 0 2006.286.03:20:35.17#ibcon#read 6, iclass 13, count 0 2006.286.03:20:35.17#ibcon#end of sib2, iclass 13, count 0 2006.286.03:20:35.17#ibcon#*after write, iclass 13, count 0 2006.286.03:20:35.17#ibcon#*before return 0, iclass 13, count 0 2006.286.03:20:35.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:20:35.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:20:35.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.03:20:35.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.03:20:35.17$vck44/va=4,6 2006.286.03:20:35.17#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.03:20:35.17#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.03:20:35.17#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:35.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:20:35.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:20:35.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:20:35.23#ibcon#enter wrdev, iclass 15, count 2 2006.286.03:20:35.23#ibcon#first serial, iclass 15, count 2 2006.286.03:20:35.23#ibcon#enter sib2, iclass 15, count 2 2006.286.03:20:35.23#ibcon#flushed, iclass 15, count 2 2006.286.03:20:35.23#ibcon#about to write, iclass 15, count 2 2006.286.03:20:35.23#ibcon#wrote, iclass 15, count 2 2006.286.03:20:35.23#ibcon#about to read 3, iclass 15, count 2 2006.286.03:20:35.25#ibcon#read 3, iclass 15, count 2 2006.286.03:20:35.25#ibcon#about to read 4, iclass 15, count 2 2006.286.03:20:35.25#ibcon#read 4, iclass 15, count 2 2006.286.03:20:35.25#ibcon#about to read 5, iclass 15, count 2 2006.286.03:20:35.25#ibcon#read 5, iclass 15, count 2 2006.286.03:20:35.25#ibcon#about to read 6, iclass 15, count 2 2006.286.03:20:35.25#ibcon#read 6, iclass 15, count 2 2006.286.03:20:35.25#ibcon#end of sib2, iclass 15, count 2 2006.286.03:20:35.25#ibcon#*mode == 0, iclass 15, count 2 2006.286.03:20:35.25#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.03:20:35.25#ibcon#[25=AT04-06\r\n] 2006.286.03:20:35.25#ibcon#*before write, iclass 15, count 2 2006.286.03:20:35.25#ibcon#enter sib2, iclass 15, count 2 2006.286.03:20:35.25#ibcon#flushed, iclass 15, count 2 2006.286.03:20:35.25#ibcon#about to write, iclass 15, count 2 2006.286.03:20:35.25#ibcon#wrote, iclass 15, count 2 2006.286.03:20:35.25#ibcon#about to read 3, iclass 15, count 2 2006.286.03:20:35.28#ibcon#read 3, iclass 15, count 2 2006.286.03:20:35.28#ibcon#about to read 4, iclass 15, count 2 2006.286.03:20:35.28#ibcon#read 4, iclass 15, count 2 2006.286.03:20:35.28#ibcon#about to read 5, iclass 15, count 2 2006.286.03:20:35.28#ibcon#read 5, iclass 15, count 2 2006.286.03:20:35.28#ibcon#about to read 6, iclass 15, count 2 2006.286.03:20:35.28#ibcon#read 6, iclass 15, count 2 2006.286.03:20:35.28#ibcon#end of sib2, iclass 15, count 2 2006.286.03:20:35.28#ibcon#*after write, iclass 15, count 2 2006.286.03:20:35.28#ibcon#*before return 0, iclass 15, count 2 2006.286.03:20:35.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:20:35.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:20:35.28#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.03:20:35.28#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:35.28#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:20:35.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:20:35.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:20:35.40#ibcon#enter wrdev, iclass 15, count 0 2006.286.03:20:35.40#ibcon#first serial, iclass 15, count 0 2006.286.03:20:35.40#ibcon#enter sib2, iclass 15, count 0 2006.286.03:20:35.40#ibcon#flushed, iclass 15, count 0 2006.286.03:20:35.40#ibcon#about to write, iclass 15, count 0 2006.286.03:20:35.40#ibcon#wrote, iclass 15, count 0 2006.286.03:20:35.40#ibcon#about to read 3, iclass 15, count 0 2006.286.03:20:35.42#ibcon#read 3, iclass 15, count 0 2006.286.03:20:35.42#ibcon#about to read 4, iclass 15, count 0 2006.286.03:20:35.42#ibcon#read 4, iclass 15, count 0 2006.286.03:20:35.42#ibcon#about to read 5, iclass 15, count 0 2006.286.03:20:35.42#ibcon#read 5, iclass 15, count 0 2006.286.03:20:35.42#ibcon#about to read 6, iclass 15, count 0 2006.286.03:20:35.42#ibcon#read 6, iclass 15, count 0 2006.286.03:20:35.42#ibcon#end of sib2, iclass 15, count 0 2006.286.03:20:35.42#ibcon#*mode == 0, iclass 15, count 0 2006.286.03:20:35.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.03:20:35.42#ibcon#[25=USB\r\n] 2006.286.03:20:35.42#ibcon#*before write, iclass 15, count 0 2006.286.03:20:35.42#ibcon#enter sib2, iclass 15, count 0 2006.286.03:20:35.42#ibcon#flushed, iclass 15, count 0 2006.286.03:20:35.42#ibcon#about to write, iclass 15, count 0 2006.286.03:20:35.42#ibcon#wrote, iclass 15, count 0 2006.286.03:20:35.42#ibcon#about to read 3, iclass 15, count 0 2006.286.03:20:35.45#ibcon#read 3, iclass 15, count 0 2006.286.03:20:35.56#ibcon#about to read 4, iclass 15, count 0 2006.286.03:20:35.56#ibcon#read 4, iclass 15, count 0 2006.286.03:20:35.56#ibcon#about to read 5, iclass 15, count 0 2006.286.03:20:35.56#ibcon#read 5, iclass 15, count 0 2006.286.03:20:35.56#ibcon#about to read 6, iclass 15, count 0 2006.286.03:20:35.56#ibcon#read 6, iclass 15, count 0 2006.286.03:20:35.56#ibcon#end of sib2, iclass 15, count 0 2006.286.03:20:35.56#ibcon#*after write, iclass 15, count 0 2006.286.03:20:35.56#ibcon#*before return 0, iclass 15, count 0 2006.286.03:20:35.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:20:35.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:20:35.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.03:20:35.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.03:20:35.56$vck44/valo=5,734.99 2006.286.03:20:35.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.03:20:35.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.03:20:35.56#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:35.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:20:35.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:20:35.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:20:35.56#ibcon#enter wrdev, iclass 17, count 0 2006.286.03:20:35.56#ibcon#first serial, iclass 17, count 0 2006.286.03:20:35.56#ibcon#enter sib2, iclass 17, count 0 2006.286.03:20:35.56#ibcon#flushed, iclass 17, count 0 2006.286.03:20:35.56#ibcon#about to write, iclass 17, count 0 2006.286.03:20:35.56#ibcon#wrote, iclass 17, count 0 2006.286.03:20:35.56#ibcon#about to read 3, iclass 17, count 0 2006.286.03:20:35.57#ibcon#read 3, iclass 17, count 0 2006.286.03:20:35.57#ibcon#about to read 4, iclass 17, count 0 2006.286.03:20:35.57#ibcon#read 4, iclass 17, count 0 2006.286.03:20:35.57#ibcon#about to read 5, iclass 17, count 0 2006.286.03:20:35.57#ibcon#read 5, iclass 17, count 0 2006.286.03:20:35.57#ibcon#about to read 6, iclass 17, count 0 2006.286.03:20:35.57#ibcon#read 6, iclass 17, count 0 2006.286.03:20:35.57#ibcon#end of sib2, iclass 17, count 0 2006.286.03:20:35.57#ibcon#*mode == 0, iclass 17, count 0 2006.286.03:20:35.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.03:20:35.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.03:20:35.57#ibcon#*before write, iclass 17, count 0 2006.286.03:20:35.57#ibcon#enter sib2, iclass 17, count 0 2006.286.03:20:35.57#ibcon#flushed, iclass 17, count 0 2006.286.03:20:35.57#ibcon#about to write, iclass 17, count 0 2006.286.03:20:35.57#ibcon#wrote, iclass 17, count 0 2006.286.03:20:35.57#ibcon#about to read 3, iclass 17, count 0 2006.286.03:20:35.61#ibcon#read 3, iclass 17, count 0 2006.286.03:20:35.61#ibcon#about to read 4, iclass 17, count 0 2006.286.03:20:35.61#ibcon#read 4, iclass 17, count 0 2006.286.03:20:35.61#ibcon#about to read 5, iclass 17, count 0 2006.286.03:20:35.61#ibcon#read 5, iclass 17, count 0 2006.286.03:20:35.61#ibcon#about to read 6, iclass 17, count 0 2006.286.03:20:35.61#ibcon#read 6, iclass 17, count 0 2006.286.03:20:35.61#ibcon#end of sib2, iclass 17, count 0 2006.286.03:20:35.61#ibcon#*after write, iclass 17, count 0 2006.286.03:20:35.61#ibcon#*before return 0, iclass 17, count 0 2006.286.03:20:35.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:20:35.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:20:35.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.03:20:35.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.03:20:35.61$vck44/va=5,3 2006.286.03:20:35.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.03:20:35.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.03:20:35.61#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:35.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:20:35.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:20:35.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:20:35.68#ibcon#enter wrdev, iclass 19, count 2 2006.286.03:20:35.68#ibcon#first serial, iclass 19, count 2 2006.286.03:20:35.68#ibcon#enter sib2, iclass 19, count 2 2006.286.03:20:35.68#ibcon#flushed, iclass 19, count 2 2006.286.03:20:35.68#ibcon#about to write, iclass 19, count 2 2006.286.03:20:35.68#ibcon#wrote, iclass 19, count 2 2006.286.03:20:35.68#ibcon#about to read 3, iclass 19, count 2 2006.286.03:20:35.70#ibcon#read 3, iclass 19, count 2 2006.286.03:20:35.70#ibcon#about to read 4, iclass 19, count 2 2006.286.03:20:35.70#ibcon#read 4, iclass 19, count 2 2006.286.03:20:35.70#ibcon#about to read 5, iclass 19, count 2 2006.286.03:20:35.70#ibcon#read 5, iclass 19, count 2 2006.286.03:20:35.70#ibcon#about to read 6, iclass 19, count 2 2006.286.03:20:35.70#ibcon#read 6, iclass 19, count 2 2006.286.03:20:35.70#ibcon#end of sib2, iclass 19, count 2 2006.286.03:20:35.70#ibcon#*mode == 0, iclass 19, count 2 2006.286.03:20:35.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.03:20:35.70#ibcon#[25=AT05-03\r\n] 2006.286.03:20:35.70#ibcon#*before write, iclass 19, count 2 2006.286.03:20:35.70#ibcon#enter sib2, iclass 19, count 2 2006.286.03:20:35.70#ibcon#flushed, iclass 19, count 2 2006.286.03:20:35.70#ibcon#about to write, iclass 19, count 2 2006.286.03:20:35.70#ibcon#wrote, iclass 19, count 2 2006.286.03:20:35.70#ibcon#about to read 3, iclass 19, count 2 2006.286.03:20:35.73#ibcon#read 3, iclass 19, count 2 2006.286.03:20:35.73#ibcon#about to read 4, iclass 19, count 2 2006.286.03:20:35.73#ibcon#read 4, iclass 19, count 2 2006.286.03:20:35.73#ibcon#about to read 5, iclass 19, count 2 2006.286.03:20:35.73#ibcon#read 5, iclass 19, count 2 2006.286.03:20:35.73#ibcon#about to read 6, iclass 19, count 2 2006.286.03:20:35.73#ibcon#read 6, iclass 19, count 2 2006.286.03:20:35.73#ibcon#end of sib2, iclass 19, count 2 2006.286.03:20:35.73#ibcon#*after write, iclass 19, count 2 2006.286.03:20:35.73#ibcon#*before return 0, iclass 19, count 2 2006.286.03:20:35.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:20:35.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:20:35.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.03:20:35.73#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:35.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:20:35.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:20:35.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:20:35.85#ibcon#enter wrdev, iclass 19, count 0 2006.286.03:20:35.85#ibcon#first serial, iclass 19, count 0 2006.286.03:20:35.85#ibcon#enter sib2, iclass 19, count 0 2006.286.03:20:35.85#ibcon#flushed, iclass 19, count 0 2006.286.03:20:35.85#ibcon#about to write, iclass 19, count 0 2006.286.03:20:35.85#ibcon#wrote, iclass 19, count 0 2006.286.03:20:35.85#ibcon#about to read 3, iclass 19, count 0 2006.286.03:20:35.87#ibcon#read 3, iclass 19, count 0 2006.286.03:20:35.87#ibcon#about to read 4, iclass 19, count 0 2006.286.03:20:35.87#ibcon#read 4, iclass 19, count 0 2006.286.03:20:35.87#ibcon#about to read 5, iclass 19, count 0 2006.286.03:20:35.87#ibcon#read 5, iclass 19, count 0 2006.286.03:20:35.87#ibcon#about to read 6, iclass 19, count 0 2006.286.03:20:35.87#ibcon#read 6, iclass 19, count 0 2006.286.03:20:35.87#ibcon#end of sib2, iclass 19, count 0 2006.286.03:20:35.87#ibcon#*mode == 0, iclass 19, count 0 2006.286.03:20:35.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.03:20:35.87#ibcon#[25=USB\r\n] 2006.286.03:20:35.87#ibcon#*before write, iclass 19, count 0 2006.286.03:20:35.87#ibcon#enter sib2, iclass 19, count 0 2006.286.03:20:35.87#ibcon#flushed, iclass 19, count 0 2006.286.03:20:35.87#ibcon#about to write, iclass 19, count 0 2006.286.03:20:35.87#ibcon#wrote, iclass 19, count 0 2006.286.03:20:35.87#ibcon#about to read 3, iclass 19, count 0 2006.286.03:20:35.90#ibcon#read 3, iclass 19, count 0 2006.286.03:20:35.90#ibcon#about to read 4, iclass 19, count 0 2006.286.03:20:35.90#ibcon#read 4, iclass 19, count 0 2006.286.03:20:35.90#ibcon#about to read 5, iclass 19, count 0 2006.286.03:20:35.90#ibcon#read 5, iclass 19, count 0 2006.286.03:20:35.90#ibcon#about to read 6, iclass 19, count 0 2006.286.03:20:35.90#ibcon#read 6, iclass 19, count 0 2006.286.03:20:35.90#ibcon#end of sib2, iclass 19, count 0 2006.286.03:20:35.90#ibcon#*after write, iclass 19, count 0 2006.286.03:20:35.90#ibcon#*before return 0, iclass 19, count 0 2006.286.03:20:35.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:20:35.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:20:35.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.03:20:35.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.03:20:35.90$vck44/valo=6,814.99 2006.286.03:20:35.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.03:20:35.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.03:20:35.90#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:35.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:20:35.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:20:35.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:20:35.90#ibcon#enter wrdev, iclass 21, count 0 2006.286.03:20:35.90#ibcon#first serial, iclass 21, count 0 2006.286.03:20:35.90#ibcon#enter sib2, iclass 21, count 0 2006.286.03:20:35.90#ibcon#flushed, iclass 21, count 0 2006.286.03:20:35.90#ibcon#about to write, iclass 21, count 0 2006.286.03:20:35.90#ibcon#wrote, iclass 21, count 0 2006.286.03:20:35.90#ibcon#about to read 3, iclass 21, count 0 2006.286.03:20:35.92#ibcon#read 3, iclass 21, count 0 2006.286.03:20:36.14#ibcon#about to read 4, iclass 21, count 0 2006.286.03:20:36.14#ibcon#read 4, iclass 21, count 0 2006.286.03:20:36.14#ibcon#about to read 5, iclass 21, count 0 2006.286.03:20:36.14#ibcon#read 5, iclass 21, count 0 2006.286.03:20:36.14#ibcon#about to read 6, iclass 21, count 0 2006.286.03:20:36.14#ibcon#read 6, iclass 21, count 0 2006.286.03:20:36.14#ibcon#end of sib2, iclass 21, count 0 2006.286.03:20:36.14#ibcon#*mode == 0, iclass 21, count 0 2006.286.03:20:36.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.03:20:36.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.03:20:36.14#ibcon#*before write, iclass 21, count 0 2006.286.03:20:36.14#ibcon#enter sib2, iclass 21, count 0 2006.286.03:20:36.14#ibcon#flushed, iclass 21, count 0 2006.286.03:20:36.14#ibcon#about to write, iclass 21, count 0 2006.286.03:20:36.14#ibcon#wrote, iclass 21, count 0 2006.286.03:20:36.14#ibcon#about to read 3, iclass 21, count 0 2006.286.03:20:36.17#ibcon#read 3, iclass 21, count 0 2006.286.03:20:36.17#ibcon#about to read 4, iclass 21, count 0 2006.286.03:20:36.17#ibcon#read 4, iclass 21, count 0 2006.286.03:20:36.17#ibcon#about to read 5, iclass 21, count 0 2006.286.03:20:36.17#ibcon#read 5, iclass 21, count 0 2006.286.03:20:36.17#ibcon#about to read 6, iclass 21, count 0 2006.286.03:20:36.17#ibcon#read 6, iclass 21, count 0 2006.286.03:20:36.17#ibcon#end of sib2, iclass 21, count 0 2006.286.03:20:36.17#ibcon#*after write, iclass 21, count 0 2006.286.03:20:36.17#ibcon#*before return 0, iclass 21, count 0 2006.286.03:20:36.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:20:36.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:20:36.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.03:20:36.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.03:20:36.17$vck44/va=6,4 2006.286.03:20:36.17#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.03:20:36.17#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.03:20:36.17#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:36.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:20:36.17#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:20:36.17#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:20:36.17#ibcon#enter wrdev, iclass 23, count 2 2006.286.03:20:36.17#ibcon#first serial, iclass 23, count 2 2006.286.03:20:36.17#ibcon#enter sib2, iclass 23, count 2 2006.286.03:20:36.17#ibcon#flushed, iclass 23, count 2 2006.286.03:20:36.17#ibcon#about to write, iclass 23, count 2 2006.286.03:20:36.17#ibcon#wrote, iclass 23, count 2 2006.286.03:20:36.17#ibcon#about to read 3, iclass 23, count 2 2006.286.03:20:36.19#ibcon#read 3, iclass 23, count 2 2006.286.03:20:36.19#ibcon#about to read 4, iclass 23, count 2 2006.286.03:20:36.19#ibcon#read 4, iclass 23, count 2 2006.286.03:20:36.19#ibcon#about to read 5, iclass 23, count 2 2006.286.03:20:36.19#ibcon#read 5, iclass 23, count 2 2006.286.03:20:36.19#ibcon#about to read 6, iclass 23, count 2 2006.286.03:20:36.19#ibcon#read 6, iclass 23, count 2 2006.286.03:20:36.19#ibcon#end of sib2, iclass 23, count 2 2006.286.03:20:36.19#ibcon#*mode == 0, iclass 23, count 2 2006.286.03:20:36.19#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.03:20:36.19#ibcon#[25=AT06-04\r\n] 2006.286.03:20:36.19#ibcon#*before write, iclass 23, count 2 2006.286.03:20:36.19#ibcon#enter sib2, iclass 23, count 2 2006.286.03:20:36.19#ibcon#flushed, iclass 23, count 2 2006.286.03:20:36.19#ibcon#about to write, iclass 23, count 2 2006.286.03:20:36.19#ibcon#wrote, iclass 23, count 2 2006.286.03:20:36.19#ibcon#about to read 3, iclass 23, count 2 2006.286.03:20:36.22#ibcon#read 3, iclass 23, count 2 2006.286.03:20:36.22#ibcon#about to read 4, iclass 23, count 2 2006.286.03:20:36.22#ibcon#read 4, iclass 23, count 2 2006.286.03:20:36.22#ibcon#about to read 5, iclass 23, count 2 2006.286.03:20:36.22#ibcon#read 5, iclass 23, count 2 2006.286.03:20:36.22#ibcon#about to read 6, iclass 23, count 2 2006.286.03:20:36.22#ibcon#read 6, iclass 23, count 2 2006.286.03:20:36.22#ibcon#end of sib2, iclass 23, count 2 2006.286.03:20:36.22#ibcon#*after write, iclass 23, count 2 2006.286.03:20:36.22#ibcon#*before return 0, iclass 23, count 2 2006.286.03:20:36.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:20:36.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:20:36.22#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.03:20:36.22#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:36.22#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:20:36.34#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:20:36.34#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:20:36.34#ibcon#enter wrdev, iclass 23, count 0 2006.286.03:20:36.34#ibcon#first serial, iclass 23, count 0 2006.286.03:20:36.34#ibcon#enter sib2, iclass 23, count 0 2006.286.03:20:36.34#ibcon#flushed, iclass 23, count 0 2006.286.03:20:36.34#ibcon#about to write, iclass 23, count 0 2006.286.03:20:36.34#ibcon#wrote, iclass 23, count 0 2006.286.03:20:36.34#ibcon#about to read 3, iclass 23, count 0 2006.286.03:20:36.36#ibcon#read 3, iclass 23, count 0 2006.286.03:20:36.36#ibcon#about to read 4, iclass 23, count 0 2006.286.03:20:36.36#ibcon#read 4, iclass 23, count 0 2006.286.03:20:36.36#ibcon#about to read 5, iclass 23, count 0 2006.286.03:20:36.36#ibcon#read 5, iclass 23, count 0 2006.286.03:20:36.36#ibcon#about to read 6, iclass 23, count 0 2006.286.03:20:36.36#ibcon#read 6, iclass 23, count 0 2006.286.03:20:36.36#ibcon#end of sib2, iclass 23, count 0 2006.286.03:20:36.36#ibcon#*mode == 0, iclass 23, count 0 2006.286.03:20:36.36#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.03:20:36.36#ibcon#[25=USB\r\n] 2006.286.03:20:36.36#ibcon#*before write, iclass 23, count 0 2006.286.03:20:36.36#ibcon#enter sib2, iclass 23, count 0 2006.286.03:20:36.36#ibcon#flushed, iclass 23, count 0 2006.286.03:20:36.36#ibcon#about to write, iclass 23, count 0 2006.286.03:20:36.36#ibcon#wrote, iclass 23, count 0 2006.286.03:20:36.36#ibcon#about to read 3, iclass 23, count 0 2006.286.03:20:36.39#ibcon#read 3, iclass 23, count 0 2006.286.03:20:36.39#ibcon#about to read 4, iclass 23, count 0 2006.286.03:20:36.39#ibcon#read 4, iclass 23, count 0 2006.286.03:20:36.39#ibcon#about to read 5, iclass 23, count 0 2006.286.03:20:36.39#ibcon#read 5, iclass 23, count 0 2006.286.03:20:36.39#ibcon#about to read 6, iclass 23, count 0 2006.286.03:20:36.39#ibcon#read 6, iclass 23, count 0 2006.286.03:20:36.39#ibcon#end of sib2, iclass 23, count 0 2006.286.03:20:36.39#ibcon#*after write, iclass 23, count 0 2006.286.03:20:36.39#ibcon#*before return 0, iclass 23, count 0 2006.286.03:20:36.39#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:20:36.39#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:20:36.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.03:20:36.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.03:20:36.39$vck44/valo=7,864.99 2006.286.03:20:36.39#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.03:20:36.39#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.03:20:36.39#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:36.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:20:36.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:20:36.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:20:36.39#ibcon#enter wrdev, iclass 25, count 0 2006.286.03:20:36.39#ibcon#first serial, iclass 25, count 0 2006.286.03:20:36.39#ibcon#enter sib2, iclass 25, count 0 2006.286.03:20:36.39#ibcon#flushed, iclass 25, count 0 2006.286.03:20:36.39#ibcon#about to write, iclass 25, count 0 2006.286.03:20:36.39#ibcon#wrote, iclass 25, count 0 2006.286.03:20:36.39#ibcon#about to read 3, iclass 25, count 0 2006.286.03:20:36.41#ibcon#read 3, iclass 25, count 0 2006.286.03:20:36.56#ibcon#about to read 4, iclass 25, count 0 2006.286.03:20:36.56#ibcon#read 4, iclass 25, count 0 2006.286.03:20:36.56#ibcon#about to read 5, iclass 25, count 0 2006.286.03:20:36.56#ibcon#read 5, iclass 25, count 0 2006.286.03:20:36.56#ibcon#about to read 6, iclass 25, count 0 2006.286.03:20:36.56#ibcon#read 6, iclass 25, count 0 2006.286.03:20:36.56#ibcon#end of sib2, iclass 25, count 0 2006.286.03:20:36.56#ibcon#*mode == 0, iclass 25, count 0 2006.286.03:20:36.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.03:20:36.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.03:20:36.56#ibcon#*before write, iclass 25, count 0 2006.286.03:20:36.56#ibcon#enter sib2, iclass 25, count 0 2006.286.03:20:36.56#ibcon#flushed, iclass 25, count 0 2006.286.03:20:36.56#ibcon#about to write, iclass 25, count 0 2006.286.03:20:36.56#ibcon#wrote, iclass 25, count 0 2006.286.03:20:36.56#ibcon#about to read 3, iclass 25, count 0 2006.286.03:20:36.59#ibcon#read 3, iclass 25, count 0 2006.286.03:20:36.59#ibcon#about to read 4, iclass 25, count 0 2006.286.03:20:36.59#ibcon#read 4, iclass 25, count 0 2006.286.03:20:36.59#ibcon#about to read 5, iclass 25, count 0 2006.286.03:20:36.59#ibcon#read 5, iclass 25, count 0 2006.286.03:20:36.59#ibcon#about to read 6, iclass 25, count 0 2006.286.03:20:36.59#ibcon#read 6, iclass 25, count 0 2006.286.03:20:36.59#ibcon#end of sib2, iclass 25, count 0 2006.286.03:20:36.59#ibcon#*after write, iclass 25, count 0 2006.286.03:20:36.59#ibcon#*before return 0, iclass 25, count 0 2006.286.03:20:36.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:20:36.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:20:36.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.03:20:36.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.03:20:36.59$vck44/va=7,4 2006.286.03:20:36.59#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.03:20:36.59#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.03:20:36.59#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:36.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:20:36.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:20:36.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:20:36.59#ibcon#enter wrdev, iclass 27, count 2 2006.286.03:20:36.59#ibcon#first serial, iclass 27, count 2 2006.286.03:20:36.59#ibcon#enter sib2, iclass 27, count 2 2006.286.03:20:36.59#ibcon#flushed, iclass 27, count 2 2006.286.03:20:36.59#ibcon#about to write, iclass 27, count 2 2006.286.03:20:36.59#ibcon#wrote, iclass 27, count 2 2006.286.03:20:36.59#ibcon#about to read 3, iclass 27, count 2 2006.286.03:20:36.61#ibcon#read 3, iclass 27, count 2 2006.286.03:20:36.61#ibcon#about to read 4, iclass 27, count 2 2006.286.03:20:36.61#ibcon#read 4, iclass 27, count 2 2006.286.03:20:36.61#ibcon#about to read 5, iclass 27, count 2 2006.286.03:20:36.61#ibcon#read 5, iclass 27, count 2 2006.286.03:20:36.61#ibcon#about to read 6, iclass 27, count 2 2006.286.03:20:36.61#ibcon#read 6, iclass 27, count 2 2006.286.03:20:36.61#ibcon#end of sib2, iclass 27, count 2 2006.286.03:20:36.61#ibcon#*mode == 0, iclass 27, count 2 2006.286.03:20:36.61#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.03:20:36.61#ibcon#[25=AT07-04\r\n] 2006.286.03:20:36.61#ibcon#*before write, iclass 27, count 2 2006.286.03:20:36.61#ibcon#enter sib2, iclass 27, count 2 2006.286.03:20:36.61#ibcon#flushed, iclass 27, count 2 2006.286.03:20:36.61#ibcon#about to write, iclass 27, count 2 2006.286.03:20:36.61#ibcon#wrote, iclass 27, count 2 2006.286.03:20:36.61#ibcon#about to read 3, iclass 27, count 2 2006.286.03:20:36.64#ibcon#read 3, iclass 27, count 2 2006.286.03:20:36.64#ibcon#about to read 4, iclass 27, count 2 2006.286.03:20:36.64#ibcon#read 4, iclass 27, count 2 2006.286.03:20:36.64#ibcon#about to read 5, iclass 27, count 2 2006.286.03:20:36.64#ibcon#read 5, iclass 27, count 2 2006.286.03:20:36.64#ibcon#about to read 6, iclass 27, count 2 2006.286.03:20:36.64#ibcon#read 6, iclass 27, count 2 2006.286.03:20:36.64#ibcon#end of sib2, iclass 27, count 2 2006.286.03:20:36.64#ibcon#*after write, iclass 27, count 2 2006.286.03:20:36.64#ibcon#*before return 0, iclass 27, count 2 2006.286.03:20:36.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:20:36.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:20:36.64#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.03:20:36.64#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:36.64#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:20:36.76#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:20:36.76#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:20:36.76#ibcon#enter wrdev, iclass 27, count 0 2006.286.03:20:36.76#ibcon#first serial, iclass 27, count 0 2006.286.03:20:36.76#ibcon#enter sib2, iclass 27, count 0 2006.286.03:20:36.76#ibcon#flushed, iclass 27, count 0 2006.286.03:20:36.76#ibcon#about to write, iclass 27, count 0 2006.286.03:20:36.76#ibcon#wrote, iclass 27, count 0 2006.286.03:20:36.76#ibcon#about to read 3, iclass 27, count 0 2006.286.03:20:36.78#ibcon#read 3, iclass 27, count 0 2006.286.03:20:36.78#ibcon#about to read 4, iclass 27, count 0 2006.286.03:20:36.78#ibcon#read 4, iclass 27, count 0 2006.286.03:20:36.78#ibcon#about to read 5, iclass 27, count 0 2006.286.03:20:36.78#ibcon#read 5, iclass 27, count 0 2006.286.03:20:36.78#ibcon#about to read 6, iclass 27, count 0 2006.286.03:20:36.78#ibcon#read 6, iclass 27, count 0 2006.286.03:20:36.78#ibcon#end of sib2, iclass 27, count 0 2006.286.03:20:36.78#ibcon#*mode == 0, iclass 27, count 0 2006.286.03:20:36.78#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.03:20:36.78#ibcon#[25=USB\r\n] 2006.286.03:20:36.78#ibcon#*before write, iclass 27, count 0 2006.286.03:20:36.78#ibcon#enter sib2, iclass 27, count 0 2006.286.03:20:36.78#ibcon#flushed, iclass 27, count 0 2006.286.03:20:36.78#ibcon#about to write, iclass 27, count 0 2006.286.03:20:36.78#ibcon#wrote, iclass 27, count 0 2006.286.03:20:36.78#ibcon#about to read 3, iclass 27, count 0 2006.286.03:20:36.81#ibcon#read 3, iclass 27, count 0 2006.286.03:20:36.81#ibcon#about to read 4, iclass 27, count 0 2006.286.03:20:36.81#ibcon#read 4, iclass 27, count 0 2006.286.03:20:36.81#ibcon#about to read 5, iclass 27, count 0 2006.286.03:20:36.81#ibcon#read 5, iclass 27, count 0 2006.286.03:20:36.81#ibcon#about to read 6, iclass 27, count 0 2006.286.03:20:36.81#ibcon#read 6, iclass 27, count 0 2006.286.03:20:36.81#ibcon#end of sib2, iclass 27, count 0 2006.286.03:20:36.81#ibcon#*after write, iclass 27, count 0 2006.286.03:20:36.81#ibcon#*before return 0, iclass 27, count 0 2006.286.03:20:36.81#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:20:36.81#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:20:36.81#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.03:20:36.81#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.03:20:36.81$vck44/valo=8,884.99 2006.286.03:20:36.81#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.03:20:36.81#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.03:20:36.81#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:36.81#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:20:36.81#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:20:36.81#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:20:36.81#ibcon#enter wrdev, iclass 29, count 0 2006.286.03:20:36.81#ibcon#first serial, iclass 29, count 0 2006.286.03:20:36.81#ibcon#enter sib2, iclass 29, count 0 2006.286.03:20:36.81#ibcon#flushed, iclass 29, count 0 2006.286.03:20:36.81#ibcon#about to write, iclass 29, count 0 2006.286.03:20:36.81#ibcon#wrote, iclass 29, count 0 2006.286.03:20:36.81#ibcon#about to read 3, iclass 29, count 0 2006.286.03:20:36.83#ibcon#read 3, iclass 29, count 0 2006.286.03:20:36.83#ibcon#about to read 4, iclass 29, count 0 2006.286.03:20:36.83#ibcon#read 4, iclass 29, count 0 2006.286.03:20:36.83#ibcon#about to read 5, iclass 29, count 0 2006.286.03:20:36.83#ibcon#read 5, iclass 29, count 0 2006.286.03:20:36.83#ibcon#about to read 6, iclass 29, count 0 2006.286.03:20:36.83#ibcon#read 6, iclass 29, count 0 2006.286.03:20:36.83#ibcon#end of sib2, iclass 29, count 0 2006.286.03:20:36.83#ibcon#*mode == 0, iclass 29, count 0 2006.286.03:20:36.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.03:20:36.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.03:20:36.83#ibcon#*before write, iclass 29, count 0 2006.286.03:20:36.83#ibcon#enter sib2, iclass 29, count 0 2006.286.03:20:36.83#ibcon#flushed, iclass 29, count 0 2006.286.03:20:36.83#ibcon#about to write, iclass 29, count 0 2006.286.03:20:36.83#ibcon#wrote, iclass 29, count 0 2006.286.03:20:36.83#ibcon#about to read 3, iclass 29, count 0 2006.286.03:20:36.87#ibcon#read 3, iclass 29, count 0 2006.286.03:20:36.87#ibcon#about to read 4, iclass 29, count 0 2006.286.03:20:36.87#ibcon#read 4, iclass 29, count 0 2006.286.03:20:36.87#ibcon#about to read 5, iclass 29, count 0 2006.286.03:20:36.87#ibcon#read 5, iclass 29, count 0 2006.286.03:20:36.87#ibcon#about to read 6, iclass 29, count 0 2006.286.03:20:36.87#ibcon#read 6, iclass 29, count 0 2006.286.03:20:36.87#ibcon#end of sib2, iclass 29, count 0 2006.286.03:20:36.87#ibcon#*after write, iclass 29, count 0 2006.286.03:20:36.87#ibcon#*before return 0, iclass 29, count 0 2006.286.03:20:36.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:20:36.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:20:36.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.03:20:36.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.03:20:36.87$vck44/va=8,3 2006.286.03:20:36.87#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.03:20:36.87#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.03:20:36.87#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:36.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:20:36.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:20:36.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:20:36.93#ibcon#enter wrdev, iclass 31, count 2 2006.286.03:20:36.93#ibcon#first serial, iclass 31, count 2 2006.286.03:20:36.93#ibcon#enter sib2, iclass 31, count 2 2006.286.03:20:36.93#ibcon#flushed, iclass 31, count 2 2006.286.03:20:36.93#ibcon#about to write, iclass 31, count 2 2006.286.03:20:36.93#ibcon#wrote, iclass 31, count 2 2006.286.03:20:36.93#ibcon#about to read 3, iclass 31, count 2 2006.286.03:20:36.95#ibcon#read 3, iclass 31, count 2 2006.286.03:20:36.95#ibcon#about to read 4, iclass 31, count 2 2006.286.03:20:36.95#ibcon#read 4, iclass 31, count 2 2006.286.03:20:36.95#ibcon#about to read 5, iclass 31, count 2 2006.286.03:20:36.95#ibcon#read 5, iclass 31, count 2 2006.286.03:20:36.95#ibcon#about to read 6, iclass 31, count 2 2006.286.03:20:36.95#ibcon#read 6, iclass 31, count 2 2006.286.03:20:36.95#ibcon#end of sib2, iclass 31, count 2 2006.286.03:20:36.95#ibcon#*mode == 0, iclass 31, count 2 2006.286.03:20:36.95#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.03:20:36.95#ibcon#[25=AT08-03\r\n] 2006.286.03:20:36.95#ibcon#*before write, iclass 31, count 2 2006.286.03:20:36.95#ibcon#enter sib2, iclass 31, count 2 2006.286.03:20:36.95#ibcon#flushed, iclass 31, count 2 2006.286.03:20:36.95#ibcon#about to write, iclass 31, count 2 2006.286.03:20:36.95#ibcon#wrote, iclass 31, count 2 2006.286.03:20:36.95#ibcon#about to read 3, iclass 31, count 2 2006.286.03:20:36.98#ibcon#read 3, iclass 31, count 2 2006.286.03:20:36.98#ibcon#about to read 4, iclass 31, count 2 2006.286.03:20:36.98#ibcon#read 4, iclass 31, count 2 2006.286.03:20:36.98#ibcon#about to read 5, iclass 31, count 2 2006.286.03:20:36.98#ibcon#read 5, iclass 31, count 2 2006.286.03:20:36.98#ibcon#about to read 6, iclass 31, count 2 2006.286.03:20:36.98#ibcon#read 6, iclass 31, count 2 2006.286.03:20:36.98#ibcon#end of sib2, iclass 31, count 2 2006.286.03:20:36.98#ibcon#*after write, iclass 31, count 2 2006.286.03:20:36.98#ibcon#*before return 0, iclass 31, count 2 2006.286.03:20:36.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:20:36.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:20:36.98#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.03:20:36.98#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:36.98#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:20:37.10#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:20:37.10#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:20:37.10#ibcon#enter wrdev, iclass 31, count 0 2006.286.03:20:37.10#ibcon#first serial, iclass 31, count 0 2006.286.03:20:37.10#ibcon#enter sib2, iclass 31, count 0 2006.286.03:20:37.10#ibcon#flushed, iclass 31, count 0 2006.286.03:20:37.10#ibcon#about to write, iclass 31, count 0 2006.286.03:20:37.10#ibcon#wrote, iclass 31, count 0 2006.286.03:20:37.10#ibcon#about to read 3, iclass 31, count 0 2006.286.03:20:37.12#ibcon#read 3, iclass 31, count 0 2006.286.03:20:37.12#ibcon#about to read 4, iclass 31, count 0 2006.286.03:20:37.12#ibcon#read 4, iclass 31, count 0 2006.286.03:20:37.12#ibcon#about to read 5, iclass 31, count 0 2006.286.03:20:37.12#ibcon#read 5, iclass 31, count 0 2006.286.03:20:37.12#ibcon#about to read 6, iclass 31, count 0 2006.286.03:20:37.12#ibcon#read 6, iclass 31, count 0 2006.286.03:20:37.12#ibcon#end of sib2, iclass 31, count 0 2006.286.03:20:37.12#ibcon#*mode == 0, iclass 31, count 0 2006.286.03:20:37.12#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.03:20:37.12#ibcon#[25=USB\r\n] 2006.286.03:20:37.12#ibcon#*before write, iclass 31, count 0 2006.286.03:20:37.12#ibcon#enter sib2, iclass 31, count 0 2006.286.03:20:37.12#ibcon#flushed, iclass 31, count 0 2006.286.03:20:37.12#ibcon#about to write, iclass 31, count 0 2006.286.03:20:37.12#ibcon#wrote, iclass 31, count 0 2006.286.03:20:37.12#ibcon#about to read 3, iclass 31, count 0 2006.286.03:20:37.15#ibcon#read 3, iclass 31, count 0 2006.286.03:20:37.15#ibcon#about to read 4, iclass 31, count 0 2006.286.03:20:37.15#ibcon#read 4, iclass 31, count 0 2006.286.03:20:37.15#ibcon#about to read 5, iclass 31, count 0 2006.286.03:20:37.15#ibcon#read 5, iclass 31, count 0 2006.286.03:20:37.15#ibcon#about to read 6, iclass 31, count 0 2006.286.03:20:37.15#ibcon#read 6, iclass 31, count 0 2006.286.03:20:37.15#ibcon#end of sib2, iclass 31, count 0 2006.286.03:20:37.15#ibcon#*after write, iclass 31, count 0 2006.286.03:20:37.15#ibcon#*before return 0, iclass 31, count 0 2006.286.03:20:37.15#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:20:37.15#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:20:37.15#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.03:20:37.15#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.03:20:37.15$vck44/vblo=1,629.99 2006.286.03:20:37.15#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.03:20:37.15#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.03:20:37.15#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:37.15#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:20:37.15#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:20:37.15#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:20:37.15#ibcon#enter wrdev, iclass 33, count 0 2006.286.03:20:37.15#ibcon#first serial, iclass 33, count 0 2006.286.03:20:37.15#ibcon#enter sib2, iclass 33, count 0 2006.286.03:20:37.15#ibcon#flushed, iclass 33, count 0 2006.286.03:20:37.15#ibcon#about to write, iclass 33, count 0 2006.286.03:20:37.15#ibcon#wrote, iclass 33, count 0 2006.286.03:20:37.15#ibcon#about to read 3, iclass 33, count 0 2006.286.03:20:37.17#ibcon#read 3, iclass 33, count 0 2006.286.03:20:37.17#ibcon#about to read 4, iclass 33, count 0 2006.286.03:20:37.17#ibcon#read 4, iclass 33, count 0 2006.286.03:20:37.17#ibcon#about to read 5, iclass 33, count 0 2006.286.03:20:37.17#ibcon#read 5, iclass 33, count 0 2006.286.03:20:37.17#ibcon#about to read 6, iclass 33, count 0 2006.286.03:20:37.17#ibcon#read 6, iclass 33, count 0 2006.286.03:20:37.17#ibcon#end of sib2, iclass 33, count 0 2006.286.03:20:37.17#ibcon#*mode == 0, iclass 33, count 0 2006.286.03:20:37.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.03:20:37.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.03:20:37.17#ibcon#*before write, iclass 33, count 0 2006.286.03:20:37.17#ibcon#enter sib2, iclass 33, count 0 2006.286.03:20:37.17#ibcon#flushed, iclass 33, count 0 2006.286.03:20:37.17#ibcon#about to write, iclass 33, count 0 2006.286.03:20:37.17#ibcon#wrote, iclass 33, count 0 2006.286.03:20:37.17#ibcon#about to read 3, iclass 33, count 0 2006.286.03:20:37.21#ibcon#read 3, iclass 33, count 0 2006.286.03:20:37.21#ibcon#about to read 4, iclass 33, count 0 2006.286.03:20:37.21#ibcon#read 4, iclass 33, count 0 2006.286.03:20:37.21#ibcon#about to read 5, iclass 33, count 0 2006.286.03:20:37.21#ibcon#read 5, iclass 33, count 0 2006.286.03:20:37.21#ibcon#about to read 6, iclass 33, count 0 2006.286.03:20:37.21#ibcon#read 6, iclass 33, count 0 2006.286.03:20:37.21#ibcon#end of sib2, iclass 33, count 0 2006.286.03:20:37.21#ibcon#*after write, iclass 33, count 0 2006.286.03:20:37.21#ibcon#*before return 0, iclass 33, count 0 2006.286.03:20:37.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:20:37.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:20:37.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.03:20:37.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.03:20:37.21$vck44/vb=1,4 2006.286.03:20:37.21#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.03:20:37.21#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.03:20:37.21#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:37.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:20:37.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:20:37.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:20:37.21#ibcon#enter wrdev, iclass 35, count 2 2006.286.03:20:37.21#ibcon#first serial, iclass 35, count 2 2006.286.03:20:37.21#ibcon#enter sib2, iclass 35, count 2 2006.286.03:20:37.21#ibcon#flushed, iclass 35, count 2 2006.286.03:20:37.21#ibcon#about to write, iclass 35, count 2 2006.286.03:20:37.21#ibcon#wrote, iclass 35, count 2 2006.286.03:20:37.21#ibcon#about to read 3, iclass 35, count 2 2006.286.03:20:37.23#ibcon#read 3, iclass 35, count 2 2006.286.03:20:37.23#ibcon#about to read 4, iclass 35, count 2 2006.286.03:20:37.23#ibcon#read 4, iclass 35, count 2 2006.286.03:20:37.23#ibcon#about to read 5, iclass 35, count 2 2006.286.03:20:37.23#ibcon#read 5, iclass 35, count 2 2006.286.03:20:37.23#ibcon#about to read 6, iclass 35, count 2 2006.286.03:20:37.23#ibcon#read 6, iclass 35, count 2 2006.286.03:20:37.23#ibcon#end of sib2, iclass 35, count 2 2006.286.03:20:37.23#ibcon#*mode == 0, iclass 35, count 2 2006.286.03:20:37.23#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.03:20:37.23#ibcon#[27=AT01-04\r\n] 2006.286.03:20:37.23#ibcon#*before write, iclass 35, count 2 2006.286.03:20:37.23#ibcon#enter sib2, iclass 35, count 2 2006.286.03:20:37.23#ibcon#flushed, iclass 35, count 2 2006.286.03:20:37.23#ibcon#about to write, iclass 35, count 2 2006.286.03:20:37.23#ibcon#wrote, iclass 35, count 2 2006.286.03:20:37.23#ibcon#about to read 3, iclass 35, count 2 2006.286.03:20:37.26#ibcon#read 3, iclass 35, count 2 2006.286.03:20:37.26#ibcon#about to read 4, iclass 35, count 2 2006.286.03:20:37.26#ibcon#read 4, iclass 35, count 2 2006.286.03:20:37.26#ibcon#about to read 5, iclass 35, count 2 2006.286.03:20:37.26#ibcon#read 5, iclass 35, count 2 2006.286.03:20:37.26#ibcon#about to read 6, iclass 35, count 2 2006.286.03:20:37.26#ibcon#read 6, iclass 35, count 2 2006.286.03:20:37.26#ibcon#end of sib2, iclass 35, count 2 2006.286.03:20:37.26#ibcon#*after write, iclass 35, count 2 2006.286.03:20:37.26#ibcon#*before return 0, iclass 35, count 2 2006.286.03:20:37.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:20:37.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:20:37.26#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.03:20:37.26#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:37.26#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:20:37.38#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:20:37.38#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:20:37.38#ibcon#enter wrdev, iclass 35, count 0 2006.286.03:20:37.38#ibcon#first serial, iclass 35, count 0 2006.286.03:20:37.38#ibcon#enter sib2, iclass 35, count 0 2006.286.03:20:37.38#ibcon#flushed, iclass 35, count 0 2006.286.03:20:37.38#ibcon#about to write, iclass 35, count 0 2006.286.03:20:37.38#ibcon#wrote, iclass 35, count 0 2006.286.03:20:37.38#ibcon#about to read 3, iclass 35, count 0 2006.286.03:20:37.40#ibcon#read 3, iclass 35, count 0 2006.286.03:20:37.40#ibcon#about to read 4, iclass 35, count 0 2006.286.03:20:37.40#ibcon#read 4, iclass 35, count 0 2006.286.03:20:37.40#ibcon#about to read 5, iclass 35, count 0 2006.286.03:20:37.40#ibcon#read 5, iclass 35, count 0 2006.286.03:20:37.40#ibcon#about to read 6, iclass 35, count 0 2006.286.03:20:37.40#ibcon#read 6, iclass 35, count 0 2006.286.03:20:37.40#ibcon#end of sib2, iclass 35, count 0 2006.286.03:20:37.40#ibcon#*mode == 0, iclass 35, count 0 2006.286.03:20:37.40#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.03:20:37.40#ibcon#[27=USB\r\n] 2006.286.03:20:37.40#ibcon#*before write, iclass 35, count 0 2006.286.03:20:37.40#ibcon#enter sib2, iclass 35, count 0 2006.286.03:20:37.40#ibcon#flushed, iclass 35, count 0 2006.286.03:20:37.40#ibcon#about to write, iclass 35, count 0 2006.286.03:20:37.40#ibcon#wrote, iclass 35, count 0 2006.286.03:20:37.40#ibcon#about to read 3, iclass 35, count 0 2006.286.03:20:37.43#ibcon#read 3, iclass 35, count 0 2006.286.03:20:37.43#ibcon#about to read 4, iclass 35, count 0 2006.286.03:20:37.43#ibcon#read 4, iclass 35, count 0 2006.286.03:20:37.43#ibcon#about to read 5, iclass 35, count 0 2006.286.03:20:37.43#ibcon#read 5, iclass 35, count 0 2006.286.03:20:37.43#ibcon#about to read 6, iclass 35, count 0 2006.286.03:20:37.43#ibcon#read 6, iclass 35, count 0 2006.286.03:20:37.43#ibcon#end of sib2, iclass 35, count 0 2006.286.03:20:37.43#ibcon#*after write, iclass 35, count 0 2006.286.03:20:37.43#ibcon#*before return 0, iclass 35, count 0 2006.286.03:20:37.43#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:20:37.43#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:20:37.43#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.03:20:37.43#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.03:20:37.43$vck44/vblo=2,634.99 2006.286.03:20:37.43#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.03:20:37.43#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.03:20:37.43#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:37.43#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:20:37.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:20:37.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:20:37.43#ibcon#enter wrdev, iclass 37, count 0 2006.286.03:20:37.43#ibcon#first serial, iclass 37, count 0 2006.286.03:20:37.43#ibcon#enter sib2, iclass 37, count 0 2006.286.03:20:37.43#ibcon#flushed, iclass 37, count 0 2006.286.03:20:37.43#ibcon#about to write, iclass 37, count 0 2006.286.03:20:37.43#ibcon#wrote, iclass 37, count 0 2006.286.03:20:37.43#ibcon#about to read 3, iclass 37, count 0 2006.286.03:20:37.45#ibcon#read 3, iclass 37, count 0 2006.286.03:20:37.52#ibcon#about to read 4, iclass 37, count 0 2006.286.03:20:37.52#ibcon#read 4, iclass 37, count 0 2006.286.03:20:37.52#ibcon#about to read 5, iclass 37, count 0 2006.286.03:20:37.52#ibcon#read 5, iclass 37, count 0 2006.286.03:20:37.52#ibcon#about to read 6, iclass 37, count 0 2006.286.03:20:37.52#ibcon#read 6, iclass 37, count 0 2006.286.03:20:37.52#ibcon#end of sib2, iclass 37, count 0 2006.286.03:20:37.52#ibcon#*mode == 0, iclass 37, count 0 2006.286.03:20:37.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.03:20:37.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.03:20:37.52#ibcon#*before write, iclass 37, count 0 2006.286.03:20:37.52#ibcon#enter sib2, iclass 37, count 0 2006.286.03:20:37.52#ibcon#flushed, iclass 37, count 0 2006.286.03:20:37.52#ibcon#about to write, iclass 37, count 0 2006.286.03:20:37.52#ibcon#wrote, iclass 37, count 0 2006.286.03:20:37.52#ibcon#about to read 3, iclass 37, count 0 2006.286.03:20:37.55#ibcon#read 3, iclass 37, count 0 2006.286.03:20:37.55#ibcon#about to read 4, iclass 37, count 0 2006.286.03:20:37.55#ibcon#read 4, iclass 37, count 0 2006.286.03:20:37.55#ibcon#about to read 5, iclass 37, count 0 2006.286.03:20:37.55#ibcon#read 5, iclass 37, count 0 2006.286.03:20:37.55#ibcon#about to read 6, iclass 37, count 0 2006.286.03:20:37.55#ibcon#read 6, iclass 37, count 0 2006.286.03:20:37.55#ibcon#end of sib2, iclass 37, count 0 2006.286.03:20:37.55#ibcon#*after write, iclass 37, count 0 2006.286.03:20:37.55#ibcon#*before return 0, iclass 37, count 0 2006.286.03:20:37.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:20:37.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:20:37.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.03:20:37.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.03:20:37.55$vck44/vb=2,5 2006.286.03:20:37.55#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.03:20:37.55#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.03:20:37.55#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:37.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:20:37.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:20:37.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:20:37.55#ibcon#enter wrdev, iclass 39, count 2 2006.286.03:20:37.55#ibcon#first serial, iclass 39, count 2 2006.286.03:20:37.55#ibcon#enter sib2, iclass 39, count 2 2006.286.03:20:37.55#ibcon#flushed, iclass 39, count 2 2006.286.03:20:37.55#ibcon#about to write, iclass 39, count 2 2006.286.03:20:37.55#ibcon#wrote, iclass 39, count 2 2006.286.03:20:37.55#ibcon#about to read 3, iclass 39, count 2 2006.286.03:20:37.57#ibcon#read 3, iclass 39, count 2 2006.286.03:20:37.57#ibcon#about to read 4, iclass 39, count 2 2006.286.03:20:37.57#ibcon#read 4, iclass 39, count 2 2006.286.03:20:37.57#ibcon#about to read 5, iclass 39, count 2 2006.286.03:20:37.57#ibcon#read 5, iclass 39, count 2 2006.286.03:20:37.57#ibcon#about to read 6, iclass 39, count 2 2006.286.03:20:37.57#ibcon#read 6, iclass 39, count 2 2006.286.03:20:37.57#ibcon#end of sib2, iclass 39, count 2 2006.286.03:20:37.57#ibcon#*mode == 0, iclass 39, count 2 2006.286.03:20:37.57#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.03:20:37.57#ibcon#[27=AT02-05\r\n] 2006.286.03:20:37.57#ibcon#*before write, iclass 39, count 2 2006.286.03:20:37.57#ibcon#enter sib2, iclass 39, count 2 2006.286.03:20:37.57#ibcon#flushed, iclass 39, count 2 2006.286.03:20:37.57#ibcon#about to write, iclass 39, count 2 2006.286.03:20:37.57#ibcon#wrote, iclass 39, count 2 2006.286.03:20:37.57#ibcon#about to read 3, iclass 39, count 2 2006.286.03:20:37.60#ibcon#read 3, iclass 39, count 2 2006.286.03:20:37.60#ibcon#about to read 4, iclass 39, count 2 2006.286.03:20:37.60#ibcon#read 4, iclass 39, count 2 2006.286.03:20:37.60#ibcon#about to read 5, iclass 39, count 2 2006.286.03:20:37.60#ibcon#read 5, iclass 39, count 2 2006.286.03:20:37.60#ibcon#about to read 6, iclass 39, count 2 2006.286.03:20:37.60#ibcon#read 6, iclass 39, count 2 2006.286.03:20:37.60#ibcon#end of sib2, iclass 39, count 2 2006.286.03:20:37.60#ibcon#*after write, iclass 39, count 2 2006.286.03:20:37.60#ibcon#*before return 0, iclass 39, count 2 2006.286.03:20:37.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:20:37.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:20:37.60#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.03:20:37.60#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:37.60#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:20:37.72#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:20:37.72#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:20:37.72#ibcon#enter wrdev, iclass 39, count 0 2006.286.03:20:37.72#ibcon#first serial, iclass 39, count 0 2006.286.03:20:37.72#ibcon#enter sib2, iclass 39, count 0 2006.286.03:20:37.72#ibcon#flushed, iclass 39, count 0 2006.286.03:20:37.72#ibcon#about to write, iclass 39, count 0 2006.286.03:20:37.72#ibcon#wrote, iclass 39, count 0 2006.286.03:20:37.72#ibcon#about to read 3, iclass 39, count 0 2006.286.03:20:37.74#ibcon#read 3, iclass 39, count 0 2006.286.03:20:37.74#ibcon#about to read 4, iclass 39, count 0 2006.286.03:20:37.74#ibcon#read 4, iclass 39, count 0 2006.286.03:20:37.74#ibcon#about to read 5, iclass 39, count 0 2006.286.03:20:37.74#ibcon#read 5, iclass 39, count 0 2006.286.03:20:37.74#ibcon#about to read 6, iclass 39, count 0 2006.286.03:20:37.74#ibcon#read 6, iclass 39, count 0 2006.286.03:20:37.74#ibcon#end of sib2, iclass 39, count 0 2006.286.03:20:37.74#ibcon#*mode == 0, iclass 39, count 0 2006.286.03:20:37.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.03:20:37.74#ibcon#[27=USB\r\n] 2006.286.03:20:37.74#ibcon#*before write, iclass 39, count 0 2006.286.03:20:37.74#ibcon#enter sib2, iclass 39, count 0 2006.286.03:20:37.74#ibcon#flushed, iclass 39, count 0 2006.286.03:20:37.74#ibcon#about to write, iclass 39, count 0 2006.286.03:20:37.74#ibcon#wrote, iclass 39, count 0 2006.286.03:20:37.74#ibcon#about to read 3, iclass 39, count 0 2006.286.03:20:37.77#ibcon#read 3, iclass 39, count 0 2006.286.03:20:37.77#ibcon#about to read 4, iclass 39, count 0 2006.286.03:20:37.77#ibcon#read 4, iclass 39, count 0 2006.286.03:20:37.77#ibcon#about to read 5, iclass 39, count 0 2006.286.03:20:37.77#ibcon#read 5, iclass 39, count 0 2006.286.03:20:37.77#ibcon#about to read 6, iclass 39, count 0 2006.286.03:20:37.77#ibcon#read 6, iclass 39, count 0 2006.286.03:20:37.77#ibcon#end of sib2, iclass 39, count 0 2006.286.03:20:37.77#ibcon#*after write, iclass 39, count 0 2006.286.03:20:37.77#ibcon#*before return 0, iclass 39, count 0 2006.286.03:20:37.77#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:20:37.77#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:20:37.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.03:20:37.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.03:20:37.77$vck44/vblo=3,649.99 2006.286.03:20:37.77#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.03:20:37.77#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.03:20:37.77#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:37.77#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:20:37.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:20:37.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:20:37.77#ibcon#enter wrdev, iclass 3, count 0 2006.286.03:20:37.77#ibcon#first serial, iclass 3, count 0 2006.286.03:20:37.77#ibcon#enter sib2, iclass 3, count 0 2006.286.03:20:37.77#ibcon#flushed, iclass 3, count 0 2006.286.03:20:37.77#ibcon#about to write, iclass 3, count 0 2006.286.03:20:37.77#ibcon#wrote, iclass 3, count 0 2006.286.03:20:37.77#ibcon#about to read 3, iclass 3, count 0 2006.286.03:20:37.79#ibcon#read 3, iclass 3, count 0 2006.286.03:20:37.79#ibcon#about to read 4, iclass 3, count 0 2006.286.03:20:37.79#ibcon#read 4, iclass 3, count 0 2006.286.03:20:37.79#ibcon#about to read 5, iclass 3, count 0 2006.286.03:20:37.79#ibcon#read 5, iclass 3, count 0 2006.286.03:20:37.79#ibcon#about to read 6, iclass 3, count 0 2006.286.03:20:37.79#ibcon#read 6, iclass 3, count 0 2006.286.03:20:37.79#ibcon#end of sib2, iclass 3, count 0 2006.286.03:20:37.79#ibcon#*mode == 0, iclass 3, count 0 2006.286.03:20:37.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.03:20:37.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.03:20:37.79#ibcon#*before write, iclass 3, count 0 2006.286.03:20:37.79#ibcon#enter sib2, iclass 3, count 0 2006.286.03:20:37.79#ibcon#flushed, iclass 3, count 0 2006.286.03:20:37.79#ibcon#about to write, iclass 3, count 0 2006.286.03:20:37.79#ibcon#wrote, iclass 3, count 0 2006.286.03:20:37.79#ibcon#about to read 3, iclass 3, count 0 2006.286.03:20:37.83#ibcon#read 3, iclass 3, count 0 2006.286.03:20:37.83#ibcon#about to read 4, iclass 3, count 0 2006.286.03:20:37.83#ibcon#read 4, iclass 3, count 0 2006.286.03:20:37.83#ibcon#about to read 5, iclass 3, count 0 2006.286.03:20:37.83#ibcon#read 5, iclass 3, count 0 2006.286.03:20:37.83#ibcon#about to read 6, iclass 3, count 0 2006.286.03:20:37.83#ibcon#read 6, iclass 3, count 0 2006.286.03:20:37.83#ibcon#end of sib2, iclass 3, count 0 2006.286.03:20:37.83#ibcon#*after write, iclass 3, count 0 2006.286.03:20:37.83#ibcon#*before return 0, iclass 3, count 0 2006.286.03:20:37.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:20:37.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:20:37.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.03:20:37.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.03:20:37.83$vck44/vb=3,4 2006.286.03:20:37.83#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.03:20:37.83#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.03:20:37.83#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:37.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:20:37.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:20:37.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:20:37.89#ibcon#enter wrdev, iclass 5, count 2 2006.286.03:20:37.89#ibcon#first serial, iclass 5, count 2 2006.286.03:20:37.89#ibcon#enter sib2, iclass 5, count 2 2006.286.03:20:37.89#ibcon#flushed, iclass 5, count 2 2006.286.03:20:37.89#ibcon#about to write, iclass 5, count 2 2006.286.03:20:37.89#ibcon#wrote, iclass 5, count 2 2006.286.03:20:37.89#ibcon#about to read 3, iclass 5, count 2 2006.286.03:20:37.91#ibcon#read 3, iclass 5, count 2 2006.286.03:20:37.91#ibcon#about to read 4, iclass 5, count 2 2006.286.03:20:37.91#ibcon#read 4, iclass 5, count 2 2006.286.03:20:37.91#ibcon#about to read 5, iclass 5, count 2 2006.286.03:20:37.91#ibcon#read 5, iclass 5, count 2 2006.286.03:20:37.91#ibcon#about to read 6, iclass 5, count 2 2006.286.03:20:37.91#ibcon#read 6, iclass 5, count 2 2006.286.03:20:37.91#ibcon#end of sib2, iclass 5, count 2 2006.286.03:20:37.91#ibcon#*mode == 0, iclass 5, count 2 2006.286.03:20:37.91#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.03:20:37.91#ibcon#[27=AT03-04\r\n] 2006.286.03:20:37.91#ibcon#*before write, iclass 5, count 2 2006.286.03:20:37.91#ibcon#enter sib2, iclass 5, count 2 2006.286.03:20:37.91#ibcon#flushed, iclass 5, count 2 2006.286.03:20:37.91#ibcon#about to write, iclass 5, count 2 2006.286.03:20:37.91#ibcon#wrote, iclass 5, count 2 2006.286.03:20:37.91#ibcon#about to read 3, iclass 5, count 2 2006.286.03:20:37.94#ibcon#read 3, iclass 5, count 2 2006.286.03:20:37.94#ibcon#about to read 4, iclass 5, count 2 2006.286.03:20:37.94#ibcon#read 4, iclass 5, count 2 2006.286.03:20:37.94#ibcon#about to read 5, iclass 5, count 2 2006.286.03:20:37.94#ibcon#read 5, iclass 5, count 2 2006.286.03:20:37.94#ibcon#about to read 6, iclass 5, count 2 2006.286.03:20:37.94#ibcon#read 6, iclass 5, count 2 2006.286.03:20:37.94#ibcon#end of sib2, iclass 5, count 2 2006.286.03:20:37.94#ibcon#*after write, iclass 5, count 2 2006.286.03:20:37.94#ibcon#*before return 0, iclass 5, count 2 2006.286.03:20:37.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:20:37.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:20:37.94#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.03:20:37.94#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:37.94#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:20:38.06#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:20:38.06#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:20:38.06#ibcon#enter wrdev, iclass 5, count 0 2006.286.03:20:38.06#ibcon#first serial, iclass 5, count 0 2006.286.03:20:38.06#ibcon#enter sib2, iclass 5, count 0 2006.286.03:20:38.06#ibcon#flushed, iclass 5, count 0 2006.286.03:20:38.06#ibcon#about to write, iclass 5, count 0 2006.286.03:20:38.06#ibcon#wrote, iclass 5, count 0 2006.286.03:20:38.06#ibcon#about to read 3, iclass 5, count 0 2006.286.03:20:38.08#ibcon#read 3, iclass 5, count 0 2006.286.03:20:38.08#ibcon#about to read 4, iclass 5, count 0 2006.286.03:20:38.08#ibcon#read 4, iclass 5, count 0 2006.286.03:20:38.08#ibcon#about to read 5, iclass 5, count 0 2006.286.03:20:38.08#ibcon#read 5, iclass 5, count 0 2006.286.03:20:38.08#ibcon#about to read 6, iclass 5, count 0 2006.286.03:20:38.08#ibcon#read 6, iclass 5, count 0 2006.286.03:20:38.08#ibcon#end of sib2, iclass 5, count 0 2006.286.03:20:38.08#ibcon#*mode == 0, iclass 5, count 0 2006.286.03:20:38.08#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.03:20:38.08#ibcon#[27=USB\r\n] 2006.286.03:20:38.08#ibcon#*before write, iclass 5, count 0 2006.286.03:20:38.08#ibcon#enter sib2, iclass 5, count 0 2006.286.03:20:38.08#ibcon#flushed, iclass 5, count 0 2006.286.03:20:38.08#ibcon#about to write, iclass 5, count 0 2006.286.03:20:38.08#ibcon#wrote, iclass 5, count 0 2006.286.03:20:38.08#ibcon#about to read 3, iclass 5, count 0 2006.286.03:20:38.11#ibcon#read 3, iclass 5, count 0 2006.286.03:20:38.11#ibcon#about to read 4, iclass 5, count 0 2006.286.03:20:38.11#ibcon#read 4, iclass 5, count 0 2006.286.03:20:38.11#ibcon#about to read 5, iclass 5, count 0 2006.286.03:20:38.11#ibcon#read 5, iclass 5, count 0 2006.286.03:20:38.11#ibcon#about to read 6, iclass 5, count 0 2006.286.03:20:38.11#ibcon#read 6, iclass 5, count 0 2006.286.03:20:38.11#ibcon#end of sib2, iclass 5, count 0 2006.286.03:20:38.11#ibcon#*after write, iclass 5, count 0 2006.286.03:20:38.11#ibcon#*before return 0, iclass 5, count 0 2006.286.03:20:38.11#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:20:38.11#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:20:38.11#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.03:20:38.11#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.03:20:38.11$vck44/vblo=4,679.99 2006.286.03:20:38.11#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.03:20:38.11#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.03:20:38.11#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:38.11#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:20:38.11#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:20:38.11#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:20:38.11#ibcon#enter wrdev, iclass 7, count 0 2006.286.03:20:38.11#ibcon#first serial, iclass 7, count 0 2006.286.03:20:38.11#ibcon#enter sib2, iclass 7, count 0 2006.286.03:20:38.11#ibcon#flushed, iclass 7, count 0 2006.286.03:20:38.11#ibcon#about to write, iclass 7, count 0 2006.286.03:20:38.11#ibcon#wrote, iclass 7, count 0 2006.286.03:20:38.11#ibcon#about to read 3, iclass 7, count 0 2006.286.03:20:38.13#ibcon#read 3, iclass 7, count 0 2006.286.03:20:38.13#ibcon#about to read 4, iclass 7, count 0 2006.286.03:20:38.13#ibcon#read 4, iclass 7, count 0 2006.286.03:20:38.13#ibcon#about to read 5, iclass 7, count 0 2006.286.03:20:38.13#ibcon#read 5, iclass 7, count 0 2006.286.03:20:38.13#ibcon#about to read 6, iclass 7, count 0 2006.286.03:20:38.13#ibcon#read 6, iclass 7, count 0 2006.286.03:20:38.13#ibcon#end of sib2, iclass 7, count 0 2006.286.03:20:38.13#ibcon#*mode == 0, iclass 7, count 0 2006.286.03:20:38.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.03:20:38.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.03:20:38.13#ibcon#*before write, iclass 7, count 0 2006.286.03:20:38.13#ibcon#enter sib2, iclass 7, count 0 2006.286.03:20:38.13#ibcon#flushed, iclass 7, count 0 2006.286.03:20:38.13#ibcon#about to write, iclass 7, count 0 2006.286.03:20:38.13#ibcon#wrote, iclass 7, count 0 2006.286.03:20:38.13#ibcon#about to read 3, iclass 7, count 0 2006.286.03:20:38.17#ibcon#read 3, iclass 7, count 0 2006.286.03:20:38.17#ibcon#about to read 4, iclass 7, count 0 2006.286.03:20:38.17#ibcon#read 4, iclass 7, count 0 2006.286.03:20:38.17#ibcon#about to read 5, iclass 7, count 0 2006.286.03:20:38.17#ibcon#read 5, iclass 7, count 0 2006.286.03:20:38.17#ibcon#about to read 6, iclass 7, count 0 2006.286.03:20:38.17#ibcon#read 6, iclass 7, count 0 2006.286.03:20:38.17#ibcon#end of sib2, iclass 7, count 0 2006.286.03:20:38.17#ibcon#*after write, iclass 7, count 0 2006.286.03:20:38.17#ibcon#*before return 0, iclass 7, count 0 2006.286.03:20:38.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:20:38.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:20:38.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.03:20:38.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.03:20:38.17$vck44/vb=4,5 2006.286.03:20:38.17#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.03:20:38.17#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.03:20:38.17#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:38.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.03:20:38.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.03:20:38.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.03:20:38.23#ibcon#enter wrdev, iclass 11, count 2 2006.286.03:20:38.23#ibcon#first serial, iclass 11, count 2 2006.286.03:20:38.23#ibcon#enter sib2, iclass 11, count 2 2006.286.03:20:38.23#ibcon#flushed, iclass 11, count 2 2006.286.03:20:38.23#ibcon#about to write, iclass 11, count 2 2006.286.03:20:38.23#ibcon#wrote, iclass 11, count 2 2006.286.03:20:38.23#ibcon#about to read 3, iclass 11, count 2 2006.286.03:20:38.25#ibcon#read 3, iclass 11, count 2 2006.286.03:20:38.25#ibcon#about to read 4, iclass 11, count 2 2006.286.03:20:38.25#ibcon#read 4, iclass 11, count 2 2006.286.03:20:38.25#ibcon#about to read 5, iclass 11, count 2 2006.286.03:20:38.25#ibcon#read 5, iclass 11, count 2 2006.286.03:20:38.25#ibcon#about to read 6, iclass 11, count 2 2006.286.03:20:38.25#ibcon#read 6, iclass 11, count 2 2006.286.03:20:38.25#ibcon#end of sib2, iclass 11, count 2 2006.286.03:20:38.25#ibcon#*mode == 0, iclass 11, count 2 2006.286.03:20:38.25#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.03:20:38.25#ibcon#[27=AT04-05\r\n] 2006.286.03:20:38.25#ibcon#*before write, iclass 11, count 2 2006.286.03:20:38.25#ibcon#enter sib2, iclass 11, count 2 2006.286.03:20:38.25#ibcon#flushed, iclass 11, count 2 2006.286.03:20:38.25#ibcon#about to write, iclass 11, count 2 2006.286.03:20:38.25#ibcon#wrote, iclass 11, count 2 2006.286.03:20:38.25#ibcon#about to read 3, iclass 11, count 2 2006.286.03:20:38.28#ibcon#read 3, iclass 11, count 2 2006.286.03:20:38.28#ibcon#about to read 4, iclass 11, count 2 2006.286.03:20:38.28#ibcon#read 4, iclass 11, count 2 2006.286.03:20:38.28#ibcon#about to read 5, iclass 11, count 2 2006.286.03:20:38.28#ibcon#read 5, iclass 11, count 2 2006.286.03:20:38.28#ibcon#about to read 6, iclass 11, count 2 2006.286.03:20:38.28#ibcon#read 6, iclass 11, count 2 2006.286.03:20:38.28#ibcon#end of sib2, iclass 11, count 2 2006.286.03:20:38.28#ibcon#*after write, iclass 11, count 2 2006.286.03:20:38.28#ibcon#*before return 0, iclass 11, count 2 2006.286.03:20:38.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.03:20:38.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.03:20:38.28#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.03:20:38.28#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:38.28#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.03:20:38.40#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.03:20:38.40#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.03:20:38.40#ibcon#enter wrdev, iclass 11, count 0 2006.286.03:20:38.40#ibcon#first serial, iclass 11, count 0 2006.286.03:20:38.40#ibcon#enter sib2, iclass 11, count 0 2006.286.03:20:38.40#ibcon#flushed, iclass 11, count 0 2006.286.03:20:38.40#ibcon#about to write, iclass 11, count 0 2006.286.03:20:38.40#ibcon#wrote, iclass 11, count 0 2006.286.03:20:38.40#ibcon#about to read 3, iclass 11, count 0 2006.286.03:20:38.42#ibcon#read 3, iclass 11, count 0 2006.286.03:20:38.42#ibcon#about to read 4, iclass 11, count 0 2006.286.03:20:38.42#ibcon#read 4, iclass 11, count 0 2006.286.03:20:38.42#ibcon#about to read 5, iclass 11, count 0 2006.286.03:20:38.42#ibcon#read 5, iclass 11, count 0 2006.286.03:20:38.42#ibcon#about to read 6, iclass 11, count 0 2006.286.03:20:38.42#ibcon#read 6, iclass 11, count 0 2006.286.03:20:38.42#ibcon#end of sib2, iclass 11, count 0 2006.286.03:20:38.42#ibcon#*mode == 0, iclass 11, count 0 2006.286.03:20:38.42#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.03:20:38.42#ibcon#[27=USB\r\n] 2006.286.03:20:38.42#ibcon#*before write, iclass 11, count 0 2006.286.03:20:38.42#ibcon#enter sib2, iclass 11, count 0 2006.286.03:20:38.42#ibcon#flushed, iclass 11, count 0 2006.286.03:20:38.42#ibcon#about to write, iclass 11, count 0 2006.286.03:20:38.42#ibcon#wrote, iclass 11, count 0 2006.286.03:20:38.42#ibcon#about to read 3, iclass 11, count 0 2006.286.03:20:38.45#ibcon#read 3, iclass 11, count 0 2006.286.03:20:38.45#ibcon#about to read 4, iclass 11, count 0 2006.286.03:20:38.45#ibcon#read 4, iclass 11, count 0 2006.286.03:20:38.45#ibcon#about to read 5, iclass 11, count 0 2006.286.03:20:38.45#ibcon#read 5, iclass 11, count 0 2006.286.03:20:38.45#ibcon#about to read 6, iclass 11, count 0 2006.286.03:20:38.45#ibcon#read 6, iclass 11, count 0 2006.286.03:20:38.45#ibcon#end of sib2, iclass 11, count 0 2006.286.03:20:38.45#ibcon#*after write, iclass 11, count 0 2006.286.03:20:38.45#ibcon#*before return 0, iclass 11, count 0 2006.286.03:20:38.45#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.03:20:38.45#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.03:20:38.45#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.03:20:38.45#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.03:20:38.45$vck44/vblo=5,709.99 2006.286.03:20:38.45#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.03:20:38.45#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.03:20:38.45#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:38.45#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:20:38.45#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:20:38.45#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:20:38.45#ibcon#enter wrdev, iclass 13, count 0 2006.286.03:20:38.45#ibcon#first serial, iclass 13, count 0 2006.286.03:20:38.45#ibcon#enter sib2, iclass 13, count 0 2006.286.03:20:38.45#ibcon#flushed, iclass 13, count 0 2006.286.03:20:38.45#ibcon#about to write, iclass 13, count 0 2006.286.03:20:38.45#ibcon#wrote, iclass 13, count 0 2006.286.03:20:38.45#ibcon#about to read 3, iclass 13, count 0 2006.286.03:20:38.47#ibcon#read 3, iclass 13, count 0 2006.286.03:20:38.68#ibcon#about to read 4, iclass 13, count 0 2006.286.03:20:38.68#ibcon#read 4, iclass 13, count 0 2006.286.03:20:38.68#ibcon#about to read 5, iclass 13, count 0 2006.286.03:20:38.68#ibcon#read 5, iclass 13, count 0 2006.286.03:20:38.68#ibcon#about to read 6, iclass 13, count 0 2006.286.03:20:38.68#ibcon#read 6, iclass 13, count 0 2006.286.03:20:38.68#ibcon#end of sib2, iclass 13, count 0 2006.286.03:20:38.68#ibcon#*mode == 0, iclass 13, count 0 2006.286.03:20:38.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.03:20:38.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.03:20:38.68#ibcon#*before write, iclass 13, count 0 2006.286.03:20:38.68#ibcon#enter sib2, iclass 13, count 0 2006.286.03:20:38.68#ibcon#flushed, iclass 13, count 0 2006.286.03:20:38.68#ibcon#about to write, iclass 13, count 0 2006.286.03:20:38.68#ibcon#wrote, iclass 13, count 0 2006.286.03:20:38.68#ibcon#about to read 3, iclass 13, count 0 2006.286.03:20:38.72#ibcon#read 3, iclass 13, count 0 2006.286.03:20:38.72#ibcon#about to read 4, iclass 13, count 0 2006.286.03:20:38.72#ibcon#read 4, iclass 13, count 0 2006.286.03:20:38.72#ibcon#about to read 5, iclass 13, count 0 2006.286.03:20:38.72#ibcon#read 5, iclass 13, count 0 2006.286.03:20:38.72#ibcon#about to read 6, iclass 13, count 0 2006.286.03:20:38.72#ibcon#read 6, iclass 13, count 0 2006.286.03:20:38.72#ibcon#end of sib2, iclass 13, count 0 2006.286.03:20:38.72#ibcon#*after write, iclass 13, count 0 2006.286.03:20:38.72#ibcon#*before return 0, iclass 13, count 0 2006.286.03:20:38.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:20:38.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:20:38.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.03:20:38.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.03:20:38.72$vck44/vb=5,4 2006.286.03:20:38.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.03:20:38.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.03:20:38.72#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:38.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:20:38.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:20:38.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:20:38.72#ibcon#enter wrdev, iclass 15, count 2 2006.286.03:20:38.72#ibcon#first serial, iclass 15, count 2 2006.286.03:20:38.72#ibcon#enter sib2, iclass 15, count 2 2006.286.03:20:38.72#ibcon#flushed, iclass 15, count 2 2006.286.03:20:38.72#ibcon#about to write, iclass 15, count 2 2006.286.03:20:38.72#ibcon#wrote, iclass 15, count 2 2006.286.03:20:38.72#ibcon#about to read 3, iclass 15, count 2 2006.286.03:20:38.74#ibcon#read 3, iclass 15, count 2 2006.286.03:20:38.74#ibcon#about to read 4, iclass 15, count 2 2006.286.03:20:38.74#ibcon#read 4, iclass 15, count 2 2006.286.03:20:38.74#ibcon#about to read 5, iclass 15, count 2 2006.286.03:20:38.74#ibcon#read 5, iclass 15, count 2 2006.286.03:20:38.74#ibcon#about to read 6, iclass 15, count 2 2006.286.03:20:38.74#ibcon#read 6, iclass 15, count 2 2006.286.03:20:38.74#ibcon#end of sib2, iclass 15, count 2 2006.286.03:20:38.74#ibcon#*mode == 0, iclass 15, count 2 2006.286.03:20:38.74#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.03:20:38.74#ibcon#[27=AT05-04\r\n] 2006.286.03:20:38.74#ibcon#*before write, iclass 15, count 2 2006.286.03:20:38.74#ibcon#enter sib2, iclass 15, count 2 2006.286.03:20:38.74#ibcon#flushed, iclass 15, count 2 2006.286.03:20:38.74#ibcon#about to write, iclass 15, count 2 2006.286.03:20:38.74#ibcon#wrote, iclass 15, count 2 2006.286.03:20:38.74#ibcon#about to read 3, iclass 15, count 2 2006.286.03:20:38.77#ibcon#read 3, iclass 15, count 2 2006.286.03:20:38.77#ibcon#about to read 4, iclass 15, count 2 2006.286.03:20:38.77#ibcon#read 4, iclass 15, count 2 2006.286.03:20:38.77#ibcon#about to read 5, iclass 15, count 2 2006.286.03:20:38.77#ibcon#read 5, iclass 15, count 2 2006.286.03:20:38.77#ibcon#about to read 6, iclass 15, count 2 2006.286.03:20:38.77#ibcon#read 6, iclass 15, count 2 2006.286.03:20:38.77#ibcon#end of sib2, iclass 15, count 2 2006.286.03:20:38.77#ibcon#*after write, iclass 15, count 2 2006.286.03:20:38.77#ibcon#*before return 0, iclass 15, count 2 2006.286.03:20:38.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:20:38.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:20:38.77#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.03:20:38.77#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:38.77#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:20:38.89#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:20:38.89#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:20:38.89#ibcon#enter wrdev, iclass 15, count 0 2006.286.03:20:38.89#ibcon#first serial, iclass 15, count 0 2006.286.03:20:38.89#ibcon#enter sib2, iclass 15, count 0 2006.286.03:20:38.89#ibcon#flushed, iclass 15, count 0 2006.286.03:20:38.89#ibcon#about to write, iclass 15, count 0 2006.286.03:20:38.89#ibcon#wrote, iclass 15, count 0 2006.286.03:20:38.89#ibcon#about to read 3, iclass 15, count 0 2006.286.03:20:38.91#ibcon#read 3, iclass 15, count 0 2006.286.03:20:38.91#ibcon#about to read 4, iclass 15, count 0 2006.286.03:20:38.91#ibcon#read 4, iclass 15, count 0 2006.286.03:20:38.91#ibcon#about to read 5, iclass 15, count 0 2006.286.03:20:38.91#ibcon#read 5, iclass 15, count 0 2006.286.03:20:38.91#ibcon#about to read 6, iclass 15, count 0 2006.286.03:20:38.91#ibcon#read 6, iclass 15, count 0 2006.286.03:20:38.91#ibcon#end of sib2, iclass 15, count 0 2006.286.03:20:38.91#ibcon#*mode == 0, iclass 15, count 0 2006.286.03:20:38.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.03:20:38.91#ibcon#[27=USB\r\n] 2006.286.03:20:38.91#ibcon#*before write, iclass 15, count 0 2006.286.03:20:38.91#ibcon#enter sib2, iclass 15, count 0 2006.286.03:20:38.91#ibcon#flushed, iclass 15, count 0 2006.286.03:20:38.91#ibcon#about to write, iclass 15, count 0 2006.286.03:20:38.91#ibcon#wrote, iclass 15, count 0 2006.286.03:20:38.91#ibcon#about to read 3, iclass 15, count 0 2006.286.03:20:38.94#ibcon#read 3, iclass 15, count 0 2006.286.03:20:38.94#ibcon#about to read 4, iclass 15, count 0 2006.286.03:20:38.94#ibcon#read 4, iclass 15, count 0 2006.286.03:20:38.94#ibcon#about to read 5, iclass 15, count 0 2006.286.03:20:38.94#ibcon#read 5, iclass 15, count 0 2006.286.03:20:38.94#ibcon#about to read 6, iclass 15, count 0 2006.286.03:20:38.94#ibcon#read 6, iclass 15, count 0 2006.286.03:20:38.94#ibcon#end of sib2, iclass 15, count 0 2006.286.03:20:38.94#ibcon#*after write, iclass 15, count 0 2006.286.03:20:38.94#ibcon#*before return 0, iclass 15, count 0 2006.286.03:20:38.94#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:20:38.94#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:20:38.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.03:20:38.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.03:20:38.94$vck44/vblo=6,719.99 2006.286.03:20:38.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.03:20:38.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.03:20:38.94#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:38.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:20:38.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:20:38.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:20:38.94#ibcon#enter wrdev, iclass 17, count 0 2006.286.03:20:38.94#ibcon#first serial, iclass 17, count 0 2006.286.03:20:38.94#ibcon#enter sib2, iclass 17, count 0 2006.286.03:20:38.94#ibcon#flushed, iclass 17, count 0 2006.286.03:20:38.94#ibcon#about to write, iclass 17, count 0 2006.286.03:20:38.94#ibcon#wrote, iclass 17, count 0 2006.286.03:20:38.94#ibcon#about to read 3, iclass 17, count 0 2006.286.03:20:38.96#ibcon#read 3, iclass 17, count 0 2006.286.03:20:38.96#ibcon#about to read 4, iclass 17, count 0 2006.286.03:20:38.96#ibcon#read 4, iclass 17, count 0 2006.286.03:20:38.96#ibcon#about to read 5, iclass 17, count 0 2006.286.03:20:38.96#ibcon#read 5, iclass 17, count 0 2006.286.03:20:38.96#ibcon#about to read 6, iclass 17, count 0 2006.286.03:20:38.96#ibcon#read 6, iclass 17, count 0 2006.286.03:20:38.96#ibcon#end of sib2, iclass 17, count 0 2006.286.03:20:38.96#ibcon#*mode == 0, iclass 17, count 0 2006.286.03:20:38.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.03:20:38.96#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.03:20:38.96#ibcon#*before write, iclass 17, count 0 2006.286.03:20:38.96#ibcon#enter sib2, iclass 17, count 0 2006.286.03:20:38.96#ibcon#flushed, iclass 17, count 0 2006.286.03:20:38.96#ibcon#about to write, iclass 17, count 0 2006.286.03:20:38.96#ibcon#wrote, iclass 17, count 0 2006.286.03:20:38.96#ibcon#about to read 3, iclass 17, count 0 2006.286.03:20:39.00#ibcon#read 3, iclass 17, count 0 2006.286.03:20:39.00#ibcon#about to read 4, iclass 17, count 0 2006.286.03:20:39.00#ibcon#read 4, iclass 17, count 0 2006.286.03:20:39.00#ibcon#about to read 5, iclass 17, count 0 2006.286.03:20:39.00#ibcon#read 5, iclass 17, count 0 2006.286.03:20:39.00#ibcon#about to read 6, iclass 17, count 0 2006.286.03:20:39.00#ibcon#read 6, iclass 17, count 0 2006.286.03:20:39.00#ibcon#end of sib2, iclass 17, count 0 2006.286.03:20:39.00#ibcon#*after write, iclass 17, count 0 2006.286.03:20:39.00#ibcon#*before return 0, iclass 17, count 0 2006.286.03:20:39.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:20:39.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:20:39.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.03:20:39.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.03:20:39.00$vck44/vb=6,3 2006.286.03:20:39.00#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.03:20:39.00#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.03:20:39.00#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:39.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:20:39.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:20:39.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:20:39.06#ibcon#enter wrdev, iclass 19, count 2 2006.286.03:20:39.06#ibcon#first serial, iclass 19, count 2 2006.286.03:20:39.06#ibcon#enter sib2, iclass 19, count 2 2006.286.03:20:39.06#ibcon#flushed, iclass 19, count 2 2006.286.03:20:39.06#ibcon#about to write, iclass 19, count 2 2006.286.03:20:39.06#ibcon#wrote, iclass 19, count 2 2006.286.03:20:39.06#ibcon#about to read 3, iclass 19, count 2 2006.286.03:20:39.08#ibcon#read 3, iclass 19, count 2 2006.286.03:20:39.08#ibcon#about to read 4, iclass 19, count 2 2006.286.03:20:39.08#ibcon#read 4, iclass 19, count 2 2006.286.03:20:39.08#ibcon#about to read 5, iclass 19, count 2 2006.286.03:20:39.08#ibcon#read 5, iclass 19, count 2 2006.286.03:20:39.08#ibcon#about to read 6, iclass 19, count 2 2006.286.03:20:39.08#ibcon#read 6, iclass 19, count 2 2006.286.03:20:39.08#ibcon#end of sib2, iclass 19, count 2 2006.286.03:20:39.08#ibcon#*mode == 0, iclass 19, count 2 2006.286.03:20:39.08#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.03:20:39.08#ibcon#[27=AT06-03\r\n] 2006.286.03:20:39.08#ibcon#*before write, iclass 19, count 2 2006.286.03:20:39.08#ibcon#enter sib2, iclass 19, count 2 2006.286.03:20:39.08#ibcon#flushed, iclass 19, count 2 2006.286.03:20:39.08#ibcon#about to write, iclass 19, count 2 2006.286.03:20:39.08#ibcon#wrote, iclass 19, count 2 2006.286.03:20:39.08#ibcon#about to read 3, iclass 19, count 2 2006.286.03:20:39.11#ibcon#read 3, iclass 19, count 2 2006.286.03:20:39.11#ibcon#about to read 4, iclass 19, count 2 2006.286.03:20:39.11#ibcon#read 4, iclass 19, count 2 2006.286.03:20:39.11#ibcon#about to read 5, iclass 19, count 2 2006.286.03:20:39.11#ibcon#read 5, iclass 19, count 2 2006.286.03:20:39.11#ibcon#about to read 6, iclass 19, count 2 2006.286.03:20:39.11#ibcon#read 6, iclass 19, count 2 2006.286.03:20:39.11#ibcon#end of sib2, iclass 19, count 2 2006.286.03:20:39.11#ibcon#*after write, iclass 19, count 2 2006.286.03:20:39.11#ibcon#*before return 0, iclass 19, count 2 2006.286.03:20:39.11#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:20:39.11#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:20:39.11#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.03:20:39.11#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:39.11#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:20:39.23#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:20:39.23#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:20:39.23#ibcon#enter wrdev, iclass 19, count 0 2006.286.03:20:39.23#ibcon#first serial, iclass 19, count 0 2006.286.03:20:39.23#ibcon#enter sib2, iclass 19, count 0 2006.286.03:20:39.23#ibcon#flushed, iclass 19, count 0 2006.286.03:20:39.23#ibcon#about to write, iclass 19, count 0 2006.286.03:20:39.23#ibcon#wrote, iclass 19, count 0 2006.286.03:20:39.23#ibcon#about to read 3, iclass 19, count 0 2006.286.03:20:39.25#ibcon#read 3, iclass 19, count 0 2006.286.03:20:39.25#ibcon#about to read 4, iclass 19, count 0 2006.286.03:20:39.25#ibcon#read 4, iclass 19, count 0 2006.286.03:20:39.25#ibcon#about to read 5, iclass 19, count 0 2006.286.03:20:39.25#ibcon#read 5, iclass 19, count 0 2006.286.03:20:39.25#ibcon#about to read 6, iclass 19, count 0 2006.286.03:20:39.25#ibcon#read 6, iclass 19, count 0 2006.286.03:20:39.25#ibcon#end of sib2, iclass 19, count 0 2006.286.03:20:39.25#ibcon#*mode == 0, iclass 19, count 0 2006.286.03:20:39.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.03:20:39.25#ibcon#[27=USB\r\n] 2006.286.03:20:39.25#ibcon#*before write, iclass 19, count 0 2006.286.03:20:39.25#ibcon#enter sib2, iclass 19, count 0 2006.286.03:20:39.25#ibcon#flushed, iclass 19, count 0 2006.286.03:20:39.25#ibcon#about to write, iclass 19, count 0 2006.286.03:20:39.25#ibcon#wrote, iclass 19, count 0 2006.286.03:20:39.25#ibcon#about to read 3, iclass 19, count 0 2006.286.03:20:39.28#ibcon#read 3, iclass 19, count 0 2006.286.03:20:39.28#ibcon#about to read 4, iclass 19, count 0 2006.286.03:20:39.28#ibcon#read 4, iclass 19, count 0 2006.286.03:20:39.28#ibcon#about to read 5, iclass 19, count 0 2006.286.03:20:39.28#ibcon#read 5, iclass 19, count 0 2006.286.03:20:39.28#ibcon#about to read 6, iclass 19, count 0 2006.286.03:20:39.28#ibcon#read 6, iclass 19, count 0 2006.286.03:20:39.28#ibcon#end of sib2, iclass 19, count 0 2006.286.03:20:39.28#ibcon#*after write, iclass 19, count 0 2006.286.03:20:39.28#ibcon#*before return 0, iclass 19, count 0 2006.286.03:20:39.28#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:20:39.28#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:20:39.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.03:20:39.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.03:20:39.28$vck44/vblo=7,734.99 2006.286.03:20:39.28#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.03:20:39.28#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.03:20:39.28#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:39.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:20:39.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:20:39.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:20:39.28#ibcon#enter wrdev, iclass 21, count 0 2006.286.03:20:39.28#ibcon#first serial, iclass 21, count 0 2006.286.03:20:39.28#ibcon#enter sib2, iclass 21, count 0 2006.286.03:20:39.28#ibcon#flushed, iclass 21, count 0 2006.286.03:20:39.28#ibcon#about to write, iclass 21, count 0 2006.286.03:20:39.28#ibcon#wrote, iclass 21, count 0 2006.286.03:20:39.28#ibcon#about to read 3, iclass 21, count 0 2006.286.03:20:39.30#ibcon#read 3, iclass 21, count 0 2006.286.03:20:39.30#ibcon#about to read 4, iclass 21, count 0 2006.286.03:20:39.30#ibcon#read 4, iclass 21, count 0 2006.286.03:20:39.30#ibcon#about to read 5, iclass 21, count 0 2006.286.03:20:39.30#ibcon#read 5, iclass 21, count 0 2006.286.03:20:39.30#ibcon#about to read 6, iclass 21, count 0 2006.286.03:20:39.30#ibcon#read 6, iclass 21, count 0 2006.286.03:20:39.30#ibcon#end of sib2, iclass 21, count 0 2006.286.03:20:39.30#ibcon#*mode == 0, iclass 21, count 0 2006.286.03:20:39.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.03:20:39.30#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.03:20:39.30#ibcon#*before write, iclass 21, count 0 2006.286.03:20:39.30#ibcon#enter sib2, iclass 21, count 0 2006.286.03:20:39.30#ibcon#flushed, iclass 21, count 0 2006.286.03:20:39.30#ibcon#about to write, iclass 21, count 0 2006.286.03:20:39.30#ibcon#wrote, iclass 21, count 0 2006.286.03:20:39.30#ibcon#about to read 3, iclass 21, count 0 2006.286.03:20:39.34#ibcon#read 3, iclass 21, count 0 2006.286.03:20:39.34#ibcon#about to read 4, iclass 21, count 0 2006.286.03:20:39.34#ibcon#read 4, iclass 21, count 0 2006.286.03:20:39.34#ibcon#about to read 5, iclass 21, count 0 2006.286.03:20:39.34#ibcon#read 5, iclass 21, count 0 2006.286.03:20:39.34#ibcon#about to read 6, iclass 21, count 0 2006.286.03:20:39.34#ibcon#read 6, iclass 21, count 0 2006.286.03:20:39.34#ibcon#end of sib2, iclass 21, count 0 2006.286.03:20:39.34#ibcon#*after write, iclass 21, count 0 2006.286.03:20:39.34#ibcon#*before return 0, iclass 21, count 0 2006.286.03:20:39.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:20:39.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:20:39.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.03:20:39.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.03:20:39.34$vck44/vb=7,4 2006.286.03:20:39.34#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.03:20:39.34#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.03:20:39.34#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:39.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:20:39.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:20:39.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:20:39.40#ibcon#enter wrdev, iclass 23, count 2 2006.286.03:20:39.40#ibcon#first serial, iclass 23, count 2 2006.286.03:20:39.40#ibcon#enter sib2, iclass 23, count 2 2006.286.03:20:39.40#ibcon#flushed, iclass 23, count 2 2006.286.03:20:39.40#ibcon#about to write, iclass 23, count 2 2006.286.03:20:39.40#ibcon#wrote, iclass 23, count 2 2006.286.03:20:39.40#ibcon#about to read 3, iclass 23, count 2 2006.286.03:20:39.42#ibcon#read 3, iclass 23, count 2 2006.286.03:20:39.42#ibcon#about to read 4, iclass 23, count 2 2006.286.03:20:39.42#ibcon#read 4, iclass 23, count 2 2006.286.03:20:39.42#ibcon#about to read 5, iclass 23, count 2 2006.286.03:20:39.42#ibcon#read 5, iclass 23, count 2 2006.286.03:20:39.42#ibcon#about to read 6, iclass 23, count 2 2006.286.03:20:39.42#ibcon#read 6, iclass 23, count 2 2006.286.03:20:39.42#ibcon#end of sib2, iclass 23, count 2 2006.286.03:20:39.42#ibcon#*mode == 0, iclass 23, count 2 2006.286.03:20:39.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.03:20:39.42#ibcon#[27=AT07-04\r\n] 2006.286.03:20:39.42#ibcon#*before write, iclass 23, count 2 2006.286.03:20:39.42#ibcon#enter sib2, iclass 23, count 2 2006.286.03:20:39.42#ibcon#flushed, iclass 23, count 2 2006.286.03:20:39.42#ibcon#about to write, iclass 23, count 2 2006.286.03:20:39.42#ibcon#wrote, iclass 23, count 2 2006.286.03:20:39.42#ibcon#about to read 3, iclass 23, count 2 2006.286.03:20:39.45#ibcon#read 3, iclass 23, count 2 2006.286.03:20:39.45#ibcon#about to read 4, iclass 23, count 2 2006.286.03:20:39.45#ibcon#read 4, iclass 23, count 2 2006.286.03:20:39.45#ibcon#about to read 5, iclass 23, count 2 2006.286.03:20:39.45#ibcon#read 5, iclass 23, count 2 2006.286.03:20:39.45#ibcon#about to read 6, iclass 23, count 2 2006.286.03:20:39.45#ibcon#read 6, iclass 23, count 2 2006.286.03:20:39.45#ibcon#end of sib2, iclass 23, count 2 2006.286.03:20:39.45#ibcon#*after write, iclass 23, count 2 2006.286.03:20:39.45#ibcon#*before return 0, iclass 23, count 2 2006.286.03:20:39.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:20:39.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:20:39.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.03:20:39.45#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:39.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:20:39.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:20:39.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:20:39.57#ibcon#enter wrdev, iclass 23, count 0 2006.286.03:20:39.57#ibcon#first serial, iclass 23, count 0 2006.286.03:20:39.57#ibcon#enter sib2, iclass 23, count 0 2006.286.03:20:39.57#ibcon#flushed, iclass 23, count 0 2006.286.03:20:39.57#ibcon#about to write, iclass 23, count 0 2006.286.03:20:39.57#ibcon#wrote, iclass 23, count 0 2006.286.03:20:39.57#ibcon#about to read 3, iclass 23, count 0 2006.286.03:20:39.59#ibcon#read 3, iclass 23, count 0 2006.286.03:20:39.59#ibcon#about to read 4, iclass 23, count 0 2006.286.03:20:39.59#ibcon#read 4, iclass 23, count 0 2006.286.03:20:39.59#ibcon#about to read 5, iclass 23, count 0 2006.286.03:20:39.59#ibcon#read 5, iclass 23, count 0 2006.286.03:20:39.59#ibcon#about to read 6, iclass 23, count 0 2006.286.03:20:39.59#ibcon#read 6, iclass 23, count 0 2006.286.03:20:39.59#ibcon#end of sib2, iclass 23, count 0 2006.286.03:20:39.59#ibcon#*mode == 0, iclass 23, count 0 2006.286.03:20:39.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.03:20:39.59#ibcon#[27=USB\r\n] 2006.286.03:20:39.59#ibcon#*before write, iclass 23, count 0 2006.286.03:20:39.59#ibcon#enter sib2, iclass 23, count 0 2006.286.03:20:39.59#ibcon#flushed, iclass 23, count 0 2006.286.03:20:39.59#ibcon#about to write, iclass 23, count 0 2006.286.03:20:39.59#ibcon#wrote, iclass 23, count 0 2006.286.03:20:39.59#ibcon#about to read 3, iclass 23, count 0 2006.286.03:20:39.62#ibcon#read 3, iclass 23, count 0 2006.286.03:20:39.62#ibcon#about to read 4, iclass 23, count 0 2006.286.03:20:39.62#ibcon#read 4, iclass 23, count 0 2006.286.03:20:39.62#ibcon#about to read 5, iclass 23, count 0 2006.286.03:20:39.62#ibcon#read 5, iclass 23, count 0 2006.286.03:20:39.62#ibcon#about to read 6, iclass 23, count 0 2006.286.03:20:39.62#ibcon#read 6, iclass 23, count 0 2006.286.03:20:39.62#ibcon#end of sib2, iclass 23, count 0 2006.286.03:20:39.62#ibcon#*after write, iclass 23, count 0 2006.286.03:20:39.62#ibcon#*before return 0, iclass 23, count 0 2006.286.03:20:39.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:20:39.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:20:39.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.03:20:39.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.03:20:39.62$vck44/vblo=8,744.99 2006.286.03:20:39.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.03:20:39.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.03:20:39.62#ibcon#ireg 17 cls_cnt 0 2006.286.03:20:39.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:20:39.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:20:39.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:20:39.62#ibcon#enter wrdev, iclass 25, count 0 2006.286.03:20:39.62#ibcon#first serial, iclass 25, count 0 2006.286.03:20:39.62#ibcon#enter sib2, iclass 25, count 0 2006.286.03:20:39.62#ibcon#flushed, iclass 25, count 0 2006.286.03:20:39.62#ibcon#about to write, iclass 25, count 0 2006.286.03:20:39.62#ibcon#wrote, iclass 25, count 0 2006.286.03:20:39.62#ibcon#about to read 3, iclass 25, count 0 2006.286.03:20:39.64#ibcon#read 3, iclass 25, count 0 2006.286.03:20:39.64#ibcon#about to read 4, iclass 25, count 0 2006.286.03:20:39.64#ibcon#read 4, iclass 25, count 0 2006.286.03:20:39.64#ibcon#about to read 5, iclass 25, count 0 2006.286.03:20:39.64#ibcon#read 5, iclass 25, count 0 2006.286.03:20:39.64#ibcon#about to read 6, iclass 25, count 0 2006.286.03:20:39.64#ibcon#read 6, iclass 25, count 0 2006.286.03:20:39.64#ibcon#end of sib2, iclass 25, count 0 2006.286.03:20:39.64#ibcon#*mode == 0, iclass 25, count 0 2006.286.03:20:39.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.03:20:39.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.03:20:39.64#ibcon#*before write, iclass 25, count 0 2006.286.03:20:39.64#ibcon#enter sib2, iclass 25, count 0 2006.286.03:20:39.64#ibcon#flushed, iclass 25, count 0 2006.286.03:20:39.64#ibcon#about to write, iclass 25, count 0 2006.286.03:20:39.64#ibcon#wrote, iclass 25, count 0 2006.286.03:20:39.64#ibcon#about to read 3, iclass 25, count 0 2006.286.03:20:39.68#ibcon#read 3, iclass 25, count 0 2006.286.03:20:39.68#ibcon#about to read 4, iclass 25, count 0 2006.286.03:20:39.68#ibcon#read 4, iclass 25, count 0 2006.286.03:20:39.68#ibcon#about to read 5, iclass 25, count 0 2006.286.03:20:39.68#ibcon#read 5, iclass 25, count 0 2006.286.03:20:39.68#ibcon#about to read 6, iclass 25, count 0 2006.286.03:20:39.68#ibcon#read 6, iclass 25, count 0 2006.286.03:20:39.68#ibcon#end of sib2, iclass 25, count 0 2006.286.03:20:39.68#ibcon#*after write, iclass 25, count 0 2006.286.03:20:39.68#ibcon#*before return 0, iclass 25, count 0 2006.286.03:20:39.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:20:39.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:20:39.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.03:20:39.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.03:20:39.68$vck44/vb=8,4 2006.286.03:20:39.68#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.03:20:39.68#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.03:20:39.68#ibcon#ireg 11 cls_cnt 2 2006.286.03:20:39.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:20:39.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:20:39.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:20:39.74#ibcon#enter wrdev, iclass 27, count 2 2006.286.03:20:39.74#ibcon#first serial, iclass 27, count 2 2006.286.03:20:39.74#ibcon#enter sib2, iclass 27, count 2 2006.286.03:20:39.74#ibcon#flushed, iclass 27, count 2 2006.286.03:20:39.74#ibcon#about to write, iclass 27, count 2 2006.286.03:20:39.74#ibcon#wrote, iclass 27, count 2 2006.286.03:20:39.74#ibcon#about to read 3, iclass 27, count 2 2006.286.03:20:39.76#ibcon#read 3, iclass 27, count 2 2006.286.03:20:39.76#ibcon#about to read 4, iclass 27, count 2 2006.286.03:20:39.76#ibcon#read 4, iclass 27, count 2 2006.286.03:20:39.76#ibcon#about to read 5, iclass 27, count 2 2006.286.03:20:39.76#ibcon#read 5, iclass 27, count 2 2006.286.03:20:39.76#ibcon#about to read 6, iclass 27, count 2 2006.286.03:20:39.76#ibcon#read 6, iclass 27, count 2 2006.286.03:20:39.76#ibcon#end of sib2, iclass 27, count 2 2006.286.03:20:39.76#ibcon#*mode == 0, iclass 27, count 2 2006.286.03:20:39.76#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.03:20:39.76#ibcon#[27=AT08-04\r\n] 2006.286.03:20:39.76#ibcon#*before write, iclass 27, count 2 2006.286.03:20:39.76#ibcon#enter sib2, iclass 27, count 2 2006.286.03:20:39.76#ibcon#flushed, iclass 27, count 2 2006.286.03:20:39.76#ibcon#about to write, iclass 27, count 2 2006.286.03:20:39.76#ibcon#wrote, iclass 27, count 2 2006.286.03:20:39.76#ibcon#about to read 3, iclass 27, count 2 2006.286.03:20:39.79#ibcon#read 3, iclass 27, count 2 2006.286.03:20:39.79#ibcon#about to read 4, iclass 27, count 2 2006.286.03:20:39.79#ibcon#read 4, iclass 27, count 2 2006.286.03:20:39.79#ibcon#about to read 5, iclass 27, count 2 2006.286.03:20:39.79#ibcon#read 5, iclass 27, count 2 2006.286.03:20:39.79#ibcon#about to read 6, iclass 27, count 2 2006.286.03:20:39.79#ibcon#read 6, iclass 27, count 2 2006.286.03:20:39.79#ibcon#end of sib2, iclass 27, count 2 2006.286.03:20:39.79#ibcon#*after write, iclass 27, count 2 2006.286.03:20:39.79#ibcon#*before return 0, iclass 27, count 2 2006.286.03:20:39.79#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:20:39.79#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:20:39.79#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.03:20:39.79#ibcon#ireg 7 cls_cnt 0 2006.286.03:20:39.79#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:20:39.91#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:20:39.91#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:20:39.91#ibcon#enter wrdev, iclass 27, count 0 2006.286.03:20:39.91#ibcon#first serial, iclass 27, count 0 2006.286.03:20:39.91#ibcon#enter sib2, iclass 27, count 0 2006.286.03:20:39.91#ibcon#flushed, iclass 27, count 0 2006.286.03:20:39.91#ibcon#about to write, iclass 27, count 0 2006.286.03:20:39.91#ibcon#wrote, iclass 27, count 0 2006.286.03:20:39.91#ibcon#about to read 3, iclass 27, count 0 2006.286.03:20:39.93#ibcon#read 3, iclass 27, count 0 2006.286.03:20:39.93#ibcon#about to read 4, iclass 27, count 0 2006.286.03:20:39.93#ibcon#read 4, iclass 27, count 0 2006.286.03:20:39.93#ibcon#about to read 5, iclass 27, count 0 2006.286.03:20:39.93#ibcon#read 5, iclass 27, count 0 2006.286.03:20:39.93#ibcon#about to read 6, iclass 27, count 0 2006.286.03:20:39.93#ibcon#read 6, iclass 27, count 0 2006.286.03:20:39.93#ibcon#end of sib2, iclass 27, count 0 2006.286.03:20:39.93#ibcon#*mode == 0, iclass 27, count 0 2006.286.03:20:39.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.03:20:39.93#ibcon#[27=USB\r\n] 2006.286.03:20:39.93#ibcon#*before write, iclass 27, count 0 2006.286.03:20:39.93#ibcon#enter sib2, iclass 27, count 0 2006.286.03:20:39.93#ibcon#flushed, iclass 27, count 0 2006.286.03:20:39.93#ibcon#about to write, iclass 27, count 0 2006.286.03:20:39.93#ibcon#wrote, iclass 27, count 0 2006.286.03:20:39.93#ibcon#about to read 3, iclass 27, count 0 2006.286.03:20:39.96#ibcon#read 3, iclass 27, count 0 2006.286.03:20:39.96#ibcon#about to read 4, iclass 27, count 0 2006.286.03:20:39.96#ibcon#read 4, iclass 27, count 0 2006.286.03:20:39.96#ibcon#about to read 5, iclass 27, count 0 2006.286.03:20:39.96#ibcon#read 5, iclass 27, count 0 2006.286.03:20:39.96#ibcon#about to read 6, iclass 27, count 0 2006.286.03:20:39.96#ibcon#read 6, iclass 27, count 0 2006.286.03:20:39.96#ibcon#end of sib2, iclass 27, count 0 2006.286.03:20:39.96#ibcon#*after write, iclass 27, count 0 2006.286.03:20:39.96#ibcon#*before return 0, iclass 27, count 0 2006.286.03:20:39.96#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:20:39.96#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:20:39.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.03:20:39.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.03:20:39.96$vck44/vabw=wide 2006.286.03:20:39.96#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.03:20:39.96#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.03:20:39.96#ibcon#ireg 8 cls_cnt 0 2006.286.03:20:39.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:20:39.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:20:39.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:20:39.96#ibcon#enter wrdev, iclass 29, count 0 2006.286.03:20:39.96#ibcon#first serial, iclass 29, count 0 2006.286.03:20:39.96#ibcon#enter sib2, iclass 29, count 0 2006.286.03:20:39.96#ibcon#flushed, iclass 29, count 0 2006.286.03:20:39.96#ibcon#about to write, iclass 29, count 0 2006.286.03:20:39.96#ibcon#wrote, iclass 29, count 0 2006.286.03:20:39.96#ibcon#about to read 3, iclass 29, count 0 2006.286.03:20:39.98#ibcon#read 3, iclass 29, count 0 2006.286.03:20:39.98#ibcon#about to read 4, iclass 29, count 0 2006.286.03:20:39.98#ibcon#read 4, iclass 29, count 0 2006.286.03:20:39.98#ibcon#about to read 5, iclass 29, count 0 2006.286.03:20:39.98#ibcon#read 5, iclass 29, count 0 2006.286.03:20:39.98#ibcon#about to read 6, iclass 29, count 0 2006.286.03:20:39.98#ibcon#read 6, iclass 29, count 0 2006.286.03:20:39.98#ibcon#end of sib2, iclass 29, count 0 2006.286.03:20:39.98#ibcon#*mode == 0, iclass 29, count 0 2006.286.03:20:39.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.03:20:39.98#ibcon#[25=BW32\r\n] 2006.286.03:20:39.98#ibcon#*before write, iclass 29, count 0 2006.286.03:20:39.98#ibcon#enter sib2, iclass 29, count 0 2006.286.03:20:39.98#ibcon#flushed, iclass 29, count 0 2006.286.03:20:39.98#ibcon#about to write, iclass 29, count 0 2006.286.03:20:39.98#ibcon#wrote, iclass 29, count 0 2006.286.03:20:39.98#ibcon#about to read 3, iclass 29, count 0 2006.286.03:20:40.01#ibcon#read 3, iclass 29, count 0 2006.286.03:20:40.01#ibcon#about to read 4, iclass 29, count 0 2006.286.03:20:40.01#ibcon#read 4, iclass 29, count 0 2006.286.03:20:40.01#ibcon#about to read 5, iclass 29, count 0 2006.286.03:20:40.01#ibcon#read 5, iclass 29, count 0 2006.286.03:20:40.01#ibcon#about to read 6, iclass 29, count 0 2006.286.03:20:40.01#ibcon#read 6, iclass 29, count 0 2006.286.03:20:40.01#ibcon#end of sib2, iclass 29, count 0 2006.286.03:20:40.01#ibcon#*after write, iclass 29, count 0 2006.286.03:20:40.01#ibcon#*before return 0, iclass 29, count 0 2006.286.03:20:40.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:20:40.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:20:40.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.03:20:40.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.03:20:40.01$vck44/vbbw=wide 2006.286.03:20:40.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.03:20:40.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.03:20:40.01#ibcon#ireg 8 cls_cnt 0 2006.286.03:20:40.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:20:40.08#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:20:40.08#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:20:40.08#ibcon#enter wrdev, iclass 31, count 0 2006.286.03:20:40.08#ibcon#first serial, iclass 31, count 0 2006.286.03:20:40.08#ibcon#enter sib2, iclass 31, count 0 2006.286.03:20:40.08#ibcon#flushed, iclass 31, count 0 2006.286.03:20:40.08#ibcon#about to write, iclass 31, count 0 2006.286.03:20:40.08#ibcon#wrote, iclass 31, count 0 2006.286.03:20:40.08#ibcon#about to read 3, iclass 31, count 0 2006.286.03:20:40.10#ibcon#read 3, iclass 31, count 0 2006.286.03:20:40.10#ibcon#about to read 4, iclass 31, count 0 2006.286.03:20:40.10#ibcon#read 4, iclass 31, count 0 2006.286.03:20:40.10#ibcon#about to read 5, iclass 31, count 0 2006.286.03:20:40.10#ibcon#read 5, iclass 31, count 0 2006.286.03:20:40.10#ibcon#about to read 6, iclass 31, count 0 2006.286.03:20:40.10#ibcon#read 6, iclass 31, count 0 2006.286.03:20:40.10#ibcon#end of sib2, iclass 31, count 0 2006.286.03:20:40.10#ibcon#*mode == 0, iclass 31, count 0 2006.286.03:20:40.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.03:20:40.10#ibcon#[27=BW32\r\n] 2006.286.03:20:40.10#ibcon#*before write, iclass 31, count 0 2006.286.03:20:40.10#ibcon#enter sib2, iclass 31, count 0 2006.286.03:20:40.10#ibcon#flushed, iclass 31, count 0 2006.286.03:20:40.10#ibcon#about to write, iclass 31, count 0 2006.286.03:20:40.10#ibcon#wrote, iclass 31, count 0 2006.286.03:20:40.10#ibcon#about to read 3, iclass 31, count 0 2006.286.03:20:40.13#ibcon#read 3, iclass 31, count 0 2006.286.03:20:40.13#ibcon#about to read 4, iclass 31, count 0 2006.286.03:20:40.13#ibcon#read 4, iclass 31, count 0 2006.286.03:20:40.13#ibcon#about to read 5, iclass 31, count 0 2006.286.03:20:40.13#ibcon#read 5, iclass 31, count 0 2006.286.03:20:40.13#ibcon#about to read 6, iclass 31, count 0 2006.286.03:20:40.13#ibcon#read 6, iclass 31, count 0 2006.286.03:20:40.13#ibcon#end of sib2, iclass 31, count 0 2006.286.03:20:40.13#ibcon#*after write, iclass 31, count 0 2006.286.03:20:40.13#ibcon#*before return 0, iclass 31, count 0 2006.286.03:20:40.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:20:40.13#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:20:40.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.03:20:40.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.03:20:40.13$setupk4/ifdk4 2006.286.03:20:40.13$ifdk4/lo= 2006.286.03:20:40.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.03:20:40.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.03:20:40.13$ifdk4/patch= 2006.286.03:20:40.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.03:20:40.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.03:20:40.14$setupk4/!*+20s 2006.286.03:20:45.31#abcon#<5=/04 3.2 6.5 21.83 771015.2\r\n> 2006.286.03:20:45.33#abcon#{5=INTERFACE CLEAR} 2006.286.03:20:45.39#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:20:50.14#trakl#Source acquired 2006.286.03:20:52.14#flagr#flagr/antenna,acquired 2006.286.03:20:53.57$setupk4/"tpicd 2006.286.03:20:53.57$setupk4/echo=off 2006.286.03:20:53.57$setupk4/xlog=off 2006.286.03:20:53.57:!2006.286.03:21:18 2006.286.03:21:18.00:preob 2006.286.03:21:18.14/onsource/TRACKING 2006.286.03:21:18.14:!2006.286.03:21:28 2006.286.03:21:28.00:"tape 2006.286.03:21:28.00:"st=record 2006.286.03:21:28.00:data_valid=on 2006.286.03:21:28.00:midob 2006.286.03:21:28.14/onsource/TRACKING 2006.286.03:21:28.14/wx/21.83,1015.2,78 2006.286.03:21:28.36/cable/+6.4988E-03 2006.286.03:21:29.45/va/01,07,usb,yes,32,34 2006.286.03:21:29.45/va/02,06,usb,yes,32,32 2006.286.03:21:29.45/va/03,07,usb,yes,31,33 2006.286.03:21:29.45/va/04,06,usb,yes,33,34 2006.286.03:21:29.45/va/05,03,usb,yes,32,33 2006.286.03:21:29.45/va/06,04,usb,yes,29,28 2006.286.03:21:29.45/va/07,04,usb,yes,30,30 2006.286.03:21:29.45/va/08,03,usb,yes,30,37 2006.286.03:21:29.68/valo/01,524.99,yes,locked 2006.286.03:21:29.68/valo/02,534.99,yes,locked 2006.286.03:21:29.68/valo/03,564.99,yes,locked 2006.286.03:21:29.68/valo/04,624.99,yes,locked 2006.286.03:21:29.68/valo/05,734.99,yes,locked 2006.286.03:21:29.68/valo/06,814.99,yes,locked 2006.286.03:21:29.68/valo/07,864.99,yes,locked 2006.286.03:21:29.68/valo/08,884.99,yes,locked 2006.286.03:21:30.77/vb/01,04,usb,yes,30,28 2006.286.03:21:30.77/vb/02,05,usb,yes,29,28 2006.286.03:21:30.77/vb/03,04,usb,yes,29,32 2006.286.03:21:30.77/vb/04,05,usb,yes,30,29 2006.286.03:21:30.77/vb/05,04,usb,yes,26,29 2006.286.03:21:30.77/vb/06,03,usb,yes,38,34 2006.286.03:21:30.77/vb/07,04,usb,yes,30,30 2006.286.03:21:30.77/vb/08,04,usb,yes,28,31 2006.286.03:21:31.00/vblo/01,629.99,yes,locked 2006.286.03:21:31.00/vblo/02,634.99,yes,locked 2006.286.03:21:31.00/vblo/03,649.99,yes,locked 2006.286.03:21:31.00/vblo/04,679.99,yes,locked 2006.286.03:21:31.00/vblo/05,709.99,yes,locked 2006.286.03:21:31.00/vblo/06,719.99,yes,locked 2006.286.03:21:31.00/vblo/07,734.99,yes,locked 2006.286.03:21:31.00/vblo/08,744.99,yes,locked 2006.286.03:21:31.15/vabw/8 2006.286.03:21:31.30/vbbw/8 2006.286.03:21:31.39/xfe/off,on,12.0 2006.286.03:21:31.77/ifatt/23,28,28,28 2006.286.03:21:32.07/fmout-gps/S +2.58E-07 2006.286.03:21:32.09:!2006.286.03:24:48 2006.286.03:24:48.00:data_valid=off 2006.286.03:24:48.00:"et 2006.286.03:24:48.00:!+3s 2006.286.03:24:51.01:"tape 2006.286.03:24:51.01:postob 2006.286.03:24:51.07/cable/+6.4981E-03 2006.286.03:24:51.07/wx/21.82,1015.1,79 2006.286.03:24:52.07/fmout-gps/S +2.53E-07 2006.286.03:24:52.07:scan_name=286-0328,jd0610,310 2006.286.03:24:52.07:source=1622-253,162546.89,-252738.3,2000.0,cw 2006.286.03:24:53.13#flagr#flagr/antenna,new-source 2006.286.03:24:53.13:checkk5 2006.286.03:24:53.55/chk_autoobs//k5ts1/ autoobs is running! 2006.286.03:24:54.29/chk_autoobs//k5ts2/ autoobs is running! 2006.286.03:24:54.70/chk_autoobs//k5ts3/ autoobs is running! 2006.286.03:24:55.26/chk_autoobs//k5ts4/ autoobs is running! 2006.286.03:24:55.78/chk_obsdata//k5ts1/T2860321??a.dat file size is correct (nominal:800MB, actual:800MB). 2006.286.03:24:56.14/chk_obsdata//k5ts2/T2860321??b.dat file size is correct (nominal:800MB, actual:800MB). 2006.286.03:24:56.52/chk_obsdata//k5ts3/T2860321??c.dat file size is correct (nominal:800MB, actual:800MB). 2006.286.03:24:56.88/chk_obsdata//k5ts4/T2860321??d.dat file size is correct (nominal:800MB, actual:800MB). 2006.286.03:24:57.83/k5log//k5ts1_log_newline 2006.286.03:24:58.82/k5log//k5ts2_log_newline 2006.286.03:24:59.98/k5log//k5ts3_log_newline 2006.286.03:25:00.77/k5log//k5ts4_log_newline 2006.286.03:25:00.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.03:25:00.79:setupk4=1 2006.286.03:25:00.79$setupk4/echo=on 2006.286.03:25:00.79$setupk4/pcalon 2006.286.03:25:00.79$pcalon/"no phase cal control is implemented here 2006.286.03:25:00.79$setupk4/"tpicd=stop 2006.286.03:25:00.79$setupk4/"rec=synch_on 2006.286.03:25:00.79$setupk4/"rec_mode=128 2006.286.03:25:00.79$setupk4/!* 2006.286.03:25:00.79$setupk4/recpk4 2006.286.03:25:00.79$recpk4/recpatch= 2006.286.03:25:00.79$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.03:25:00.79$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.03:25:00.79$setupk4/vck44 2006.286.03:25:00.79$vck44/valo=1,524.99 2006.286.03:25:00.79#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.03:25:00.79#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.03:25:00.79#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:00.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:25:00.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:25:00.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:25:00.79#ibcon#enter wrdev, iclass 32, count 0 2006.286.03:25:00.79#ibcon#first serial, iclass 32, count 0 2006.286.03:25:00.79#ibcon#enter sib2, iclass 32, count 0 2006.286.03:25:00.79#ibcon#flushed, iclass 32, count 0 2006.286.03:25:00.79#ibcon#about to write, iclass 32, count 0 2006.286.03:25:00.79#ibcon#wrote, iclass 32, count 0 2006.286.03:25:00.79#ibcon#about to read 3, iclass 32, count 0 2006.286.03:25:00.81#ibcon#read 3, iclass 32, count 0 2006.286.03:25:00.81#ibcon#about to read 4, iclass 32, count 0 2006.286.03:25:00.81#ibcon#read 4, iclass 32, count 0 2006.286.03:25:00.81#ibcon#about to read 5, iclass 32, count 0 2006.286.03:25:00.81#ibcon#read 5, iclass 32, count 0 2006.286.03:25:00.81#ibcon#about to read 6, iclass 32, count 0 2006.286.03:25:00.81#ibcon#read 6, iclass 32, count 0 2006.286.03:25:00.81#ibcon#end of sib2, iclass 32, count 0 2006.286.03:25:00.81#ibcon#*mode == 0, iclass 32, count 0 2006.286.03:25:00.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.03:25:00.81#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.03:25:00.81#ibcon#*before write, iclass 32, count 0 2006.286.03:25:00.81#ibcon#enter sib2, iclass 32, count 0 2006.286.03:25:00.81#ibcon#flushed, iclass 32, count 0 2006.286.03:25:00.81#ibcon#about to write, iclass 32, count 0 2006.286.03:25:00.81#ibcon#wrote, iclass 32, count 0 2006.286.03:25:00.81#ibcon#about to read 3, iclass 32, count 0 2006.286.03:25:00.86#ibcon#read 3, iclass 32, count 0 2006.286.03:25:00.86#ibcon#about to read 4, iclass 32, count 0 2006.286.03:25:00.86#ibcon#read 4, iclass 32, count 0 2006.286.03:25:00.86#ibcon#about to read 5, iclass 32, count 0 2006.286.03:25:00.86#ibcon#read 5, iclass 32, count 0 2006.286.03:25:00.86#ibcon#about to read 6, iclass 32, count 0 2006.286.03:25:00.86#ibcon#read 6, iclass 32, count 0 2006.286.03:25:00.86#ibcon#end of sib2, iclass 32, count 0 2006.286.03:25:00.86#ibcon#*after write, iclass 32, count 0 2006.286.03:25:00.86#ibcon#*before return 0, iclass 32, count 0 2006.286.03:25:00.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:25:00.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:25:00.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.03:25:00.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.03:25:00.86$vck44/va=1,7 2006.286.03:25:00.86#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.03:25:00.86#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.03:25:00.86#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:00.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:25:00.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:25:00.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:25:00.86#ibcon#enter wrdev, iclass 34, count 2 2006.286.03:25:00.86#ibcon#first serial, iclass 34, count 2 2006.286.03:25:00.86#ibcon#enter sib2, iclass 34, count 2 2006.286.03:25:00.86#ibcon#flushed, iclass 34, count 2 2006.286.03:25:00.86#ibcon#about to write, iclass 34, count 2 2006.286.03:25:00.86#ibcon#wrote, iclass 34, count 2 2006.286.03:25:00.86#ibcon#about to read 3, iclass 34, count 2 2006.286.03:25:00.88#ibcon#read 3, iclass 34, count 2 2006.286.03:25:00.88#ibcon#about to read 4, iclass 34, count 2 2006.286.03:25:00.88#ibcon#read 4, iclass 34, count 2 2006.286.03:25:00.88#ibcon#about to read 5, iclass 34, count 2 2006.286.03:25:00.88#ibcon#read 5, iclass 34, count 2 2006.286.03:25:00.88#ibcon#about to read 6, iclass 34, count 2 2006.286.03:25:00.88#ibcon#read 6, iclass 34, count 2 2006.286.03:25:00.88#ibcon#end of sib2, iclass 34, count 2 2006.286.03:25:00.88#ibcon#*mode == 0, iclass 34, count 2 2006.286.03:25:00.88#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.03:25:00.88#ibcon#[25=AT01-07\r\n] 2006.286.03:25:00.88#ibcon#*before write, iclass 34, count 2 2006.286.03:25:00.88#ibcon#enter sib2, iclass 34, count 2 2006.286.03:25:00.88#ibcon#flushed, iclass 34, count 2 2006.286.03:25:00.88#ibcon#about to write, iclass 34, count 2 2006.286.03:25:00.88#ibcon#wrote, iclass 34, count 2 2006.286.03:25:00.88#ibcon#about to read 3, iclass 34, count 2 2006.286.03:25:00.91#ibcon#read 3, iclass 34, count 2 2006.286.03:25:00.91#ibcon#about to read 4, iclass 34, count 2 2006.286.03:25:00.91#ibcon#read 4, iclass 34, count 2 2006.286.03:25:00.91#ibcon#about to read 5, iclass 34, count 2 2006.286.03:25:00.91#ibcon#read 5, iclass 34, count 2 2006.286.03:25:00.91#ibcon#about to read 6, iclass 34, count 2 2006.286.03:25:00.91#ibcon#read 6, iclass 34, count 2 2006.286.03:25:00.91#ibcon#end of sib2, iclass 34, count 2 2006.286.03:25:00.91#ibcon#*after write, iclass 34, count 2 2006.286.03:25:00.91#ibcon#*before return 0, iclass 34, count 2 2006.286.03:25:00.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:25:00.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:25:00.91#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.03:25:00.91#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:00.91#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:25:01.03#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:25:01.03#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:25:01.03#ibcon#enter wrdev, iclass 34, count 0 2006.286.03:25:01.03#ibcon#first serial, iclass 34, count 0 2006.286.03:25:01.03#ibcon#enter sib2, iclass 34, count 0 2006.286.03:25:01.03#ibcon#flushed, iclass 34, count 0 2006.286.03:25:01.03#ibcon#about to write, iclass 34, count 0 2006.286.03:25:01.03#ibcon#wrote, iclass 34, count 0 2006.286.03:25:01.03#ibcon#about to read 3, iclass 34, count 0 2006.286.03:25:01.05#ibcon#read 3, iclass 34, count 0 2006.286.03:25:01.05#ibcon#about to read 4, iclass 34, count 0 2006.286.03:25:01.05#ibcon#read 4, iclass 34, count 0 2006.286.03:25:01.05#ibcon#about to read 5, iclass 34, count 0 2006.286.03:25:01.05#ibcon#read 5, iclass 34, count 0 2006.286.03:25:01.05#ibcon#about to read 6, iclass 34, count 0 2006.286.03:25:01.05#ibcon#read 6, iclass 34, count 0 2006.286.03:25:01.05#ibcon#end of sib2, iclass 34, count 0 2006.286.03:25:01.05#ibcon#*mode == 0, iclass 34, count 0 2006.286.03:25:01.05#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.03:25:01.05#ibcon#[25=USB\r\n] 2006.286.03:25:01.05#ibcon#*before write, iclass 34, count 0 2006.286.03:25:01.05#ibcon#enter sib2, iclass 34, count 0 2006.286.03:25:01.05#ibcon#flushed, iclass 34, count 0 2006.286.03:25:01.05#ibcon#about to write, iclass 34, count 0 2006.286.03:25:01.05#ibcon#wrote, iclass 34, count 0 2006.286.03:25:01.05#ibcon#about to read 3, iclass 34, count 0 2006.286.03:25:01.08#ibcon#read 3, iclass 34, count 0 2006.286.03:25:01.08#ibcon#about to read 4, iclass 34, count 0 2006.286.03:25:01.08#ibcon#read 4, iclass 34, count 0 2006.286.03:25:01.08#ibcon#about to read 5, iclass 34, count 0 2006.286.03:25:01.08#ibcon#read 5, iclass 34, count 0 2006.286.03:25:01.08#ibcon#about to read 6, iclass 34, count 0 2006.286.03:25:01.08#ibcon#read 6, iclass 34, count 0 2006.286.03:25:01.08#ibcon#end of sib2, iclass 34, count 0 2006.286.03:25:01.08#ibcon#*after write, iclass 34, count 0 2006.286.03:25:01.08#ibcon#*before return 0, iclass 34, count 0 2006.286.03:25:01.08#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:25:01.08#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:25:01.08#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.03:25:01.08#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.03:25:01.08$vck44/valo=2,534.99 2006.286.03:25:01.08#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.03:25:01.08#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.03:25:01.08#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:01.08#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:25:01.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:25:01.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:25:01.08#ibcon#enter wrdev, iclass 36, count 0 2006.286.03:25:01.08#ibcon#first serial, iclass 36, count 0 2006.286.03:25:01.08#ibcon#enter sib2, iclass 36, count 0 2006.286.03:25:01.08#ibcon#flushed, iclass 36, count 0 2006.286.03:25:01.08#ibcon#about to write, iclass 36, count 0 2006.286.03:25:01.08#ibcon#wrote, iclass 36, count 0 2006.286.03:25:01.08#ibcon#about to read 3, iclass 36, count 0 2006.286.03:25:01.10#ibcon#read 3, iclass 36, count 0 2006.286.03:25:01.41#ibcon#about to read 4, iclass 36, count 0 2006.286.03:25:01.41#ibcon#read 4, iclass 36, count 0 2006.286.03:25:01.41#ibcon#about to read 5, iclass 36, count 0 2006.286.03:25:01.41#ibcon#read 5, iclass 36, count 0 2006.286.03:25:01.41#ibcon#about to read 6, iclass 36, count 0 2006.286.03:25:01.41#ibcon#read 6, iclass 36, count 0 2006.286.03:25:01.41#ibcon#end of sib2, iclass 36, count 0 2006.286.03:25:01.41#ibcon#*mode == 0, iclass 36, count 0 2006.286.03:25:01.41#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.03:25:01.41#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.03:25:01.41#ibcon#*before write, iclass 36, count 0 2006.286.03:25:01.41#ibcon#enter sib2, iclass 36, count 0 2006.286.03:25:01.41#ibcon#flushed, iclass 36, count 0 2006.286.03:25:01.41#ibcon#about to write, iclass 36, count 0 2006.286.03:25:01.41#ibcon#wrote, iclass 36, count 0 2006.286.03:25:01.41#ibcon#about to read 3, iclass 36, count 0 2006.286.03:25:01.45#ibcon#read 3, iclass 36, count 0 2006.286.03:25:01.45#ibcon#about to read 4, iclass 36, count 0 2006.286.03:25:01.45#ibcon#read 4, iclass 36, count 0 2006.286.03:25:01.45#ibcon#about to read 5, iclass 36, count 0 2006.286.03:25:01.45#ibcon#read 5, iclass 36, count 0 2006.286.03:25:01.45#ibcon#about to read 6, iclass 36, count 0 2006.286.03:25:01.45#ibcon#read 6, iclass 36, count 0 2006.286.03:25:01.45#ibcon#end of sib2, iclass 36, count 0 2006.286.03:25:01.45#ibcon#*after write, iclass 36, count 0 2006.286.03:25:01.45#ibcon#*before return 0, iclass 36, count 0 2006.286.03:25:01.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:25:01.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:25:01.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.03:25:01.45#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.03:25:01.45$vck44/va=2,6 2006.286.03:25:01.45#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.03:25:01.45#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.03:25:01.45#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:01.45#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:25:01.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:25:01.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:25:01.45#ibcon#enter wrdev, iclass 38, count 2 2006.286.03:25:01.45#ibcon#first serial, iclass 38, count 2 2006.286.03:25:01.45#ibcon#enter sib2, iclass 38, count 2 2006.286.03:25:01.45#ibcon#flushed, iclass 38, count 2 2006.286.03:25:01.45#ibcon#about to write, iclass 38, count 2 2006.286.03:25:01.45#ibcon#wrote, iclass 38, count 2 2006.286.03:25:01.45#ibcon#about to read 3, iclass 38, count 2 2006.286.03:25:01.47#ibcon#read 3, iclass 38, count 2 2006.286.03:25:01.47#ibcon#about to read 4, iclass 38, count 2 2006.286.03:25:01.47#ibcon#read 4, iclass 38, count 2 2006.286.03:25:01.47#ibcon#about to read 5, iclass 38, count 2 2006.286.03:25:01.47#ibcon#read 5, iclass 38, count 2 2006.286.03:25:01.47#ibcon#about to read 6, iclass 38, count 2 2006.286.03:25:01.47#ibcon#read 6, iclass 38, count 2 2006.286.03:25:01.47#ibcon#end of sib2, iclass 38, count 2 2006.286.03:25:01.47#ibcon#*mode == 0, iclass 38, count 2 2006.286.03:25:01.47#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.03:25:01.47#ibcon#[25=AT02-06\r\n] 2006.286.03:25:01.47#ibcon#*before write, iclass 38, count 2 2006.286.03:25:01.47#ibcon#enter sib2, iclass 38, count 2 2006.286.03:25:01.47#ibcon#flushed, iclass 38, count 2 2006.286.03:25:01.47#ibcon#about to write, iclass 38, count 2 2006.286.03:25:01.47#ibcon#wrote, iclass 38, count 2 2006.286.03:25:01.47#ibcon#about to read 3, iclass 38, count 2 2006.286.03:25:01.50#ibcon#read 3, iclass 38, count 2 2006.286.03:25:01.50#ibcon#about to read 4, iclass 38, count 2 2006.286.03:25:01.50#ibcon#read 4, iclass 38, count 2 2006.286.03:25:01.50#ibcon#about to read 5, iclass 38, count 2 2006.286.03:25:01.50#ibcon#read 5, iclass 38, count 2 2006.286.03:25:01.50#ibcon#about to read 6, iclass 38, count 2 2006.286.03:25:01.50#ibcon#read 6, iclass 38, count 2 2006.286.03:25:01.50#ibcon#end of sib2, iclass 38, count 2 2006.286.03:25:01.50#ibcon#*after write, iclass 38, count 2 2006.286.03:25:01.50#ibcon#*before return 0, iclass 38, count 2 2006.286.03:25:01.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:25:01.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:25:01.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.03:25:01.50#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:01.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:25:01.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:25:01.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:25:01.62#ibcon#enter wrdev, iclass 38, count 0 2006.286.03:25:01.62#ibcon#first serial, iclass 38, count 0 2006.286.03:25:01.62#ibcon#enter sib2, iclass 38, count 0 2006.286.03:25:01.62#ibcon#flushed, iclass 38, count 0 2006.286.03:25:01.62#ibcon#about to write, iclass 38, count 0 2006.286.03:25:01.62#ibcon#wrote, iclass 38, count 0 2006.286.03:25:01.62#ibcon#about to read 3, iclass 38, count 0 2006.286.03:25:01.64#ibcon#read 3, iclass 38, count 0 2006.286.03:25:01.64#ibcon#about to read 4, iclass 38, count 0 2006.286.03:25:01.64#ibcon#read 4, iclass 38, count 0 2006.286.03:25:01.64#ibcon#about to read 5, iclass 38, count 0 2006.286.03:25:01.64#ibcon#read 5, iclass 38, count 0 2006.286.03:25:01.64#ibcon#about to read 6, iclass 38, count 0 2006.286.03:25:01.64#ibcon#read 6, iclass 38, count 0 2006.286.03:25:01.64#ibcon#end of sib2, iclass 38, count 0 2006.286.03:25:01.64#ibcon#*mode == 0, iclass 38, count 0 2006.286.03:25:01.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.03:25:01.64#ibcon#[25=USB\r\n] 2006.286.03:25:01.64#ibcon#*before write, iclass 38, count 0 2006.286.03:25:01.64#ibcon#enter sib2, iclass 38, count 0 2006.286.03:25:01.64#ibcon#flushed, iclass 38, count 0 2006.286.03:25:01.64#ibcon#about to write, iclass 38, count 0 2006.286.03:25:01.64#ibcon#wrote, iclass 38, count 0 2006.286.03:25:01.64#ibcon#about to read 3, iclass 38, count 0 2006.286.03:25:01.67#ibcon#read 3, iclass 38, count 0 2006.286.03:25:01.67#ibcon#about to read 4, iclass 38, count 0 2006.286.03:25:01.67#ibcon#read 4, iclass 38, count 0 2006.286.03:25:01.67#ibcon#about to read 5, iclass 38, count 0 2006.286.03:25:01.67#ibcon#read 5, iclass 38, count 0 2006.286.03:25:01.67#ibcon#about to read 6, iclass 38, count 0 2006.286.03:25:01.67#ibcon#read 6, iclass 38, count 0 2006.286.03:25:01.67#ibcon#end of sib2, iclass 38, count 0 2006.286.03:25:01.67#ibcon#*after write, iclass 38, count 0 2006.286.03:25:01.67#ibcon#*before return 0, iclass 38, count 0 2006.286.03:25:01.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:25:01.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:25:01.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.03:25:01.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.03:25:01.67$vck44/valo=3,564.99 2006.286.03:25:01.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.03:25:01.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.03:25:01.67#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:01.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:25:01.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:25:01.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:25:01.67#ibcon#enter wrdev, iclass 40, count 0 2006.286.03:25:01.67#ibcon#first serial, iclass 40, count 0 2006.286.03:25:01.67#ibcon#enter sib2, iclass 40, count 0 2006.286.03:25:01.67#ibcon#flushed, iclass 40, count 0 2006.286.03:25:01.67#ibcon#about to write, iclass 40, count 0 2006.286.03:25:01.67#ibcon#wrote, iclass 40, count 0 2006.286.03:25:01.67#ibcon#about to read 3, iclass 40, count 0 2006.286.03:25:01.69#ibcon#read 3, iclass 40, count 0 2006.286.03:25:01.69#ibcon#about to read 4, iclass 40, count 0 2006.286.03:25:01.69#ibcon#read 4, iclass 40, count 0 2006.286.03:25:01.69#ibcon#about to read 5, iclass 40, count 0 2006.286.03:25:01.69#ibcon#read 5, iclass 40, count 0 2006.286.03:25:01.69#ibcon#about to read 6, iclass 40, count 0 2006.286.03:25:01.69#ibcon#read 6, iclass 40, count 0 2006.286.03:25:01.69#ibcon#end of sib2, iclass 40, count 0 2006.286.03:25:01.69#ibcon#*mode == 0, iclass 40, count 0 2006.286.03:25:01.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.03:25:01.69#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.03:25:01.69#ibcon#*before write, iclass 40, count 0 2006.286.03:25:01.69#ibcon#enter sib2, iclass 40, count 0 2006.286.03:25:01.69#ibcon#flushed, iclass 40, count 0 2006.286.03:25:01.69#ibcon#about to write, iclass 40, count 0 2006.286.03:25:01.69#ibcon#wrote, iclass 40, count 0 2006.286.03:25:01.69#ibcon#about to read 3, iclass 40, count 0 2006.286.03:25:01.73#ibcon#read 3, iclass 40, count 0 2006.286.03:25:01.73#ibcon#about to read 4, iclass 40, count 0 2006.286.03:25:01.73#ibcon#read 4, iclass 40, count 0 2006.286.03:25:01.73#ibcon#about to read 5, iclass 40, count 0 2006.286.03:25:01.73#ibcon#read 5, iclass 40, count 0 2006.286.03:25:01.73#ibcon#about to read 6, iclass 40, count 0 2006.286.03:25:01.73#ibcon#read 6, iclass 40, count 0 2006.286.03:25:01.73#ibcon#end of sib2, iclass 40, count 0 2006.286.03:25:01.73#ibcon#*after write, iclass 40, count 0 2006.286.03:25:01.73#ibcon#*before return 0, iclass 40, count 0 2006.286.03:25:01.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:25:01.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:25:01.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.03:25:01.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.03:25:01.73$vck44/va=3,7 2006.286.03:25:01.73#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.03:25:01.73#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.03:25:01.73#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:01.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:25:01.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:25:01.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:25:01.79#ibcon#enter wrdev, iclass 4, count 2 2006.286.03:25:01.79#ibcon#first serial, iclass 4, count 2 2006.286.03:25:01.79#ibcon#enter sib2, iclass 4, count 2 2006.286.03:25:01.79#ibcon#flushed, iclass 4, count 2 2006.286.03:25:01.79#ibcon#about to write, iclass 4, count 2 2006.286.03:25:01.79#ibcon#wrote, iclass 4, count 2 2006.286.03:25:01.79#ibcon#about to read 3, iclass 4, count 2 2006.286.03:25:01.81#ibcon#read 3, iclass 4, count 2 2006.286.03:25:01.81#ibcon#about to read 4, iclass 4, count 2 2006.286.03:25:01.81#ibcon#read 4, iclass 4, count 2 2006.286.03:25:01.81#ibcon#about to read 5, iclass 4, count 2 2006.286.03:25:01.81#ibcon#read 5, iclass 4, count 2 2006.286.03:25:01.81#ibcon#about to read 6, iclass 4, count 2 2006.286.03:25:01.81#ibcon#read 6, iclass 4, count 2 2006.286.03:25:01.81#ibcon#end of sib2, iclass 4, count 2 2006.286.03:25:01.81#ibcon#*mode == 0, iclass 4, count 2 2006.286.03:25:01.81#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.03:25:01.81#ibcon#[25=AT03-07\r\n] 2006.286.03:25:01.81#ibcon#*before write, iclass 4, count 2 2006.286.03:25:01.81#ibcon#enter sib2, iclass 4, count 2 2006.286.03:25:01.81#ibcon#flushed, iclass 4, count 2 2006.286.03:25:01.81#ibcon#about to write, iclass 4, count 2 2006.286.03:25:01.81#ibcon#wrote, iclass 4, count 2 2006.286.03:25:01.81#ibcon#about to read 3, iclass 4, count 2 2006.286.03:25:01.84#ibcon#read 3, iclass 4, count 2 2006.286.03:25:01.97#ibcon#about to read 4, iclass 4, count 2 2006.286.03:25:01.97#ibcon#read 4, iclass 4, count 2 2006.286.03:25:01.97#ibcon#about to read 5, iclass 4, count 2 2006.286.03:25:01.97#ibcon#read 5, iclass 4, count 2 2006.286.03:25:01.97#ibcon#about to read 6, iclass 4, count 2 2006.286.03:25:01.97#ibcon#read 6, iclass 4, count 2 2006.286.03:25:01.97#ibcon#end of sib2, iclass 4, count 2 2006.286.03:25:01.97#ibcon#*after write, iclass 4, count 2 2006.286.03:25:01.97#ibcon#*before return 0, iclass 4, count 2 2006.286.03:25:01.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:25:01.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:25:01.97#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.03:25:01.97#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:01.97#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:25:02.09#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:25:02.09#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:25:02.09#ibcon#enter wrdev, iclass 4, count 0 2006.286.03:25:02.09#ibcon#first serial, iclass 4, count 0 2006.286.03:25:02.09#ibcon#enter sib2, iclass 4, count 0 2006.286.03:25:02.09#ibcon#flushed, iclass 4, count 0 2006.286.03:25:02.09#ibcon#about to write, iclass 4, count 0 2006.286.03:25:02.09#ibcon#wrote, iclass 4, count 0 2006.286.03:25:02.09#ibcon#about to read 3, iclass 4, count 0 2006.286.03:25:02.11#ibcon#read 3, iclass 4, count 0 2006.286.03:25:02.11#ibcon#about to read 4, iclass 4, count 0 2006.286.03:25:02.11#ibcon#read 4, iclass 4, count 0 2006.286.03:25:02.11#ibcon#about to read 5, iclass 4, count 0 2006.286.03:25:02.11#ibcon#read 5, iclass 4, count 0 2006.286.03:25:02.11#ibcon#about to read 6, iclass 4, count 0 2006.286.03:25:02.11#ibcon#read 6, iclass 4, count 0 2006.286.03:25:02.11#ibcon#end of sib2, iclass 4, count 0 2006.286.03:25:02.11#ibcon#*mode == 0, iclass 4, count 0 2006.286.03:25:02.11#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.03:25:02.11#ibcon#[25=USB\r\n] 2006.286.03:25:02.11#ibcon#*before write, iclass 4, count 0 2006.286.03:25:02.11#ibcon#enter sib2, iclass 4, count 0 2006.286.03:25:02.11#ibcon#flushed, iclass 4, count 0 2006.286.03:25:02.11#ibcon#about to write, iclass 4, count 0 2006.286.03:25:02.11#ibcon#wrote, iclass 4, count 0 2006.286.03:25:02.11#ibcon#about to read 3, iclass 4, count 0 2006.286.03:25:02.14#ibcon#read 3, iclass 4, count 0 2006.286.03:25:02.14#ibcon#about to read 4, iclass 4, count 0 2006.286.03:25:02.14#ibcon#read 4, iclass 4, count 0 2006.286.03:25:02.14#ibcon#about to read 5, iclass 4, count 0 2006.286.03:25:02.14#ibcon#read 5, iclass 4, count 0 2006.286.03:25:02.14#ibcon#about to read 6, iclass 4, count 0 2006.286.03:25:02.14#ibcon#read 6, iclass 4, count 0 2006.286.03:25:02.14#ibcon#end of sib2, iclass 4, count 0 2006.286.03:25:02.14#ibcon#*after write, iclass 4, count 0 2006.286.03:25:02.14#ibcon#*before return 0, iclass 4, count 0 2006.286.03:25:02.14#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:25:02.14#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:25:02.14#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.03:25:02.14#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.03:25:02.14$vck44/valo=4,624.99 2006.286.03:25:02.14#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.03:25:02.14#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.03:25:02.14#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:02.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:25:02.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:25:02.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:25:02.14#ibcon#enter wrdev, iclass 6, count 0 2006.286.03:25:02.14#ibcon#first serial, iclass 6, count 0 2006.286.03:25:02.14#ibcon#enter sib2, iclass 6, count 0 2006.286.03:25:02.14#ibcon#flushed, iclass 6, count 0 2006.286.03:25:02.14#ibcon#about to write, iclass 6, count 0 2006.286.03:25:02.14#ibcon#wrote, iclass 6, count 0 2006.286.03:25:02.14#ibcon#about to read 3, iclass 6, count 0 2006.286.03:25:02.16#ibcon#read 3, iclass 6, count 0 2006.286.03:25:02.29#ibcon#about to read 4, iclass 6, count 0 2006.286.03:25:02.29#ibcon#read 4, iclass 6, count 0 2006.286.03:25:02.29#ibcon#about to read 5, iclass 6, count 0 2006.286.03:25:02.29#ibcon#read 5, iclass 6, count 0 2006.286.03:25:02.29#ibcon#about to read 6, iclass 6, count 0 2006.286.03:25:02.29#ibcon#read 6, iclass 6, count 0 2006.286.03:25:02.29#ibcon#end of sib2, iclass 6, count 0 2006.286.03:25:02.29#ibcon#*mode == 0, iclass 6, count 0 2006.286.03:25:02.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.03:25:02.29#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.03:25:02.29#ibcon#*before write, iclass 6, count 0 2006.286.03:25:02.29#ibcon#enter sib2, iclass 6, count 0 2006.286.03:25:02.29#ibcon#flushed, iclass 6, count 0 2006.286.03:25:02.29#ibcon#about to write, iclass 6, count 0 2006.286.03:25:02.29#ibcon#wrote, iclass 6, count 0 2006.286.03:25:02.29#ibcon#about to read 3, iclass 6, count 0 2006.286.03:25:02.33#ibcon#read 3, iclass 6, count 0 2006.286.03:25:02.33#ibcon#about to read 4, iclass 6, count 0 2006.286.03:25:02.33#ibcon#read 4, iclass 6, count 0 2006.286.03:25:02.33#ibcon#about to read 5, iclass 6, count 0 2006.286.03:25:02.33#ibcon#read 5, iclass 6, count 0 2006.286.03:25:02.33#ibcon#about to read 6, iclass 6, count 0 2006.286.03:25:02.33#ibcon#read 6, iclass 6, count 0 2006.286.03:25:02.33#ibcon#end of sib2, iclass 6, count 0 2006.286.03:25:02.33#ibcon#*after write, iclass 6, count 0 2006.286.03:25:02.33#ibcon#*before return 0, iclass 6, count 0 2006.286.03:25:02.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:25:02.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:25:02.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.03:25:02.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.03:25:02.33$vck44/va=4,6 2006.286.03:25:02.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.03:25:02.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.03:25:02.33#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:02.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:25:02.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:25:02.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:25:02.33#ibcon#enter wrdev, iclass 10, count 2 2006.286.03:25:02.33#ibcon#first serial, iclass 10, count 2 2006.286.03:25:02.33#ibcon#enter sib2, iclass 10, count 2 2006.286.03:25:02.33#ibcon#flushed, iclass 10, count 2 2006.286.03:25:02.33#ibcon#about to write, iclass 10, count 2 2006.286.03:25:02.33#ibcon#wrote, iclass 10, count 2 2006.286.03:25:02.33#ibcon#about to read 3, iclass 10, count 2 2006.286.03:25:02.35#ibcon#read 3, iclass 10, count 2 2006.286.03:25:02.35#ibcon#about to read 4, iclass 10, count 2 2006.286.03:25:02.35#ibcon#read 4, iclass 10, count 2 2006.286.03:25:02.35#ibcon#about to read 5, iclass 10, count 2 2006.286.03:25:02.35#ibcon#read 5, iclass 10, count 2 2006.286.03:25:02.35#ibcon#about to read 6, iclass 10, count 2 2006.286.03:25:02.35#ibcon#read 6, iclass 10, count 2 2006.286.03:25:02.35#ibcon#end of sib2, iclass 10, count 2 2006.286.03:25:02.35#ibcon#*mode == 0, iclass 10, count 2 2006.286.03:25:02.35#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.03:25:02.35#ibcon#[25=AT04-06\r\n] 2006.286.03:25:02.35#ibcon#*before write, iclass 10, count 2 2006.286.03:25:02.35#ibcon#enter sib2, iclass 10, count 2 2006.286.03:25:02.35#ibcon#flushed, iclass 10, count 2 2006.286.03:25:02.35#ibcon#about to write, iclass 10, count 2 2006.286.03:25:02.35#ibcon#wrote, iclass 10, count 2 2006.286.03:25:02.35#ibcon#about to read 3, iclass 10, count 2 2006.286.03:25:02.38#ibcon#read 3, iclass 10, count 2 2006.286.03:25:02.38#ibcon#about to read 4, iclass 10, count 2 2006.286.03:25:02.38#ibcon#read 4, iclass 10, count 2 2006.286.03:25:02.38#ibcon#about to read 5, iclass 10, count 2 2006.286.03:25:02.38#ibcon#read 5, iclass 10, count 2 2006.286.03:25:02.38#ibcon#about to read 6, iclass 10, count 2 2006.286.03:25:02.38#ibcon#read 6, iclass 10, count 2 2006.286.03:25:02.38#ibcon#end of sib2, iclass 10, count 2 2006.286.03:25:02.38#ibcon#*after write, iclass 10, count 2 2006.286.03:25:02.38#ibcon#*before return 0, iclass 10, count 2 2006.286.03:25:02.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:25:02.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:25:02.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.03:25:02.38#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:02.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:25:02.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:25:02.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:25:02.50#ibcon#enter wrdev, iclass 10, count 0 2006.286.03:25:02.50#ibcon#first serial, iclass 10, count 0 2006.286.03:25:02.50#ibcon#enter sib2, iclass 10, count 0 2006.286.03:25:02.50#ibcon#flushed, iclass 10, count 0 2006.286.03:25:02.50#ibcon#about to write, iclass 10, count 0 2006.286.03:25:02.50#ibcon#wrote, iclass 10, count 0 2006.286.03:25:02.50#ibcon#about to read 3, iclass 10, count 0 2006.286.03:25:02.52#ibcon#read 3, iclass 10, count 0 2006.286.03:25:02.52#ibcon#about to read 4, iclass 10, count 0 2006.286.03:25:02.52#ibcon#read 4, iclass 10, count 0 2006.286.03:25:02.52#ibcon#about to read 5, iclass 10, count 0 2006.286.03:25:02.52#ibcon#read 5, iclass 10, count 0 2006.286.03:25:02.52#ibcon#about to read 6, iclass 10, count 0 2006.286.03:25:02.52#ibcon#read 6, iclass 10, count 0 2006.286.03:25:02.52#ibcon#end of sib2, iclass 10, count 0 2006.286.03:25:02.52#ibcon#*mode == 0, iclass 10, count 0 2006.286.03:25:02.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.03:25:02.52#ibcon#[25=USB\r\n] 2006.286.03:25:02.52#ibcon#*before write, iclass 10, count 0 2006.286.03:25:02.52#ibcon#enter sib2, iclass 10, count 0 2006.286.03:25:02.52#ibcon#flushed, iclass 10, count 0 2006.286.03:25:02.52#ibcon#about to write, iclass 10, count 0 2006.286.03:25:02.52#ibcon#wrote, iclass 10, count 0 2006.286.03:25:02.52#ibcon#about to read 3, iclass 10, count 0 2006.286.03:25:02.55#ibcon#read 3, iclass 10, count 0 2006.286.03:25:02.55#ibcon#about to read 4, iclass 10, count 0 2006.286.03:25:02.55#ibcon#read 4, iclass 10, count 0 2006.286.03:25:02.55#ibcon#about to read 5, iclass 10, count 0 2006.286.03:25:02.55#ibcon#read 5, iclass 10, count 0 2006.286.03:25:02.55#ibcon#about to read 6, iclass 10, count 0 2006.286.03:25:02.55#ibcon#read 6, iclass 10, count 0 2006.286.03:25:02.55#ibcon#end of sib2, iclass 10, count 0 2006.286.03:25:02.55#ibcon#*after write, iclass 10, count 0 2006.286.03:25:02.55#ibcon#*before return 0, iclass 10, count 0 2006.286.03:25:02.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:25:02.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:25:02.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.03:25:02.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.03:25:02.55$vck44/valo=5,734.99 2006.286.03:25:02.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.03:25:02.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.03:25:02.55#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:02.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:25:02.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:25:02.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:25:02.55#ibcon#enter wrdev, iclass 12, count 0 2006.286.03:25:02.55#ibcon#first serial, iclass 12, count 0 2006.286.03:25:02.55#ibcon#enter sib2, iclass 12, count 0 2006.286.03:25:02.55#ibcon#flushed, iclass 12, count 0 2006.286.03:25:02.55#ibcon#about to write, iclass 12, count 0 2006.286.03:25:02.55#ibcon#wrote, iclass 12, count 0 2006.286.03:25:02.55#ibcon#about to read 3, iclass 12, count 0 2006.286.03:25:02.57#ibcon#read 3, iclass 12, count 0 2006.286.03:25:02.57#ibcon#about to read 4, iclass 12, count 0 2006.286.03:25:02.57#ibcon#read 4, iclass 12, count 0 2006.286.03:25:02.57#ibcon#about to read 5, iclass 12, count 0 2006.286.03:25:02.57#ibcon#read 5, iclass 12, count 0 2006.286.03:25:02.57#ibcon#about to read 6, iclass 12, count 0 2006.286.03:25:02.57#ibcon#read 6, iclass 12, count 0 2006.286.03:25:02.57#ibcon#end of sib2, iclass 12, count 0 2006.286.03:25:02.57#ibcon#*mode == 0, iclass 12, count 0 2006.286.03:25:02.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.03:25:02.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.03:25:02.57#ibcon#*before write, iclass 12, count 0 2006.286.03:25:02.57#ibcon#enter sib2, iclass 12, count 0 2006.286.03:25:02.57#ibcon#flushed, iclass 12, count 0 2006.286.03:25:02.57#ibcon#about to write, iclass 12, count 0 2006.286.03:25:02.57#ibcon#wrote, iclass 12, count 0 2006.286.03:25:02.57#ibcon#about to read 3, iclass 12, count 0 2006.286.03:25:02.61#ibcon#read 3, iclass 12, count 0 2006.286.03:25:02.61#ibcon#about to read 4, iclass 12, count 0 2006.286.03:25:02.61#ibcon#read 4, iclass 12, count 0 2006.286.03:25:02.61#ibcon#about to read 5, iclass 12, count 0 2006.286.03:25:02.61#ibcon#read 5, iclass 12, count 0 2006.286.03:25:02.61#ibcon#about to read 6, iclass 12, count 0 2006.286.03:25:02.61#ibcon#read 6, iclass 12, count 0 2006.286.03:25:02.61#ibcon#end of sib2, iclass 12, count 0 2006.286.03:25:02.61#ibcon#*after write, iclass 12, count 0 2006.286.03:25:02.61#ibcon#*before return 0, iclass 12, count 0 2006.286.03:25:02.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:25:02.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:25:02.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.03:25:02.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.03:25:02.61$vck44/va=5,3 2006.286.03:25:02.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.03:25:02.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.03:25:02.61#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:02.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:25:02.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:25:02.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:25:02.67#ibcon#enter wrdev, iclass 14, count 2 2006.286.03:25:02.67#ibcon#first serial, iclass 14, count 2 2006.286.03:25:02.67#ibcon#enter sib2, iclass 14, count 2 2006.286.03:25:02.67#ibcon#flushed, iclass 14, count 2 2006.286.03:25:02.67#ibcon#about to write, iclass 14, count 2 2006.286.03:25:02.67#ibcon#wrote, iclass 14, count 2 2006.286.03:25:02.67#ibcon#about to read 3, iclass 14, count 2 2006.286.03:25:02.69#ibcon#read 3, iclass 14, count 2 2006.286.03:25:02.69#ibcon#about to read 4, iclass 14, count 2 2006.286.03:25:02.69#ibcon#read 4, iclass 14, count 2 2006.286.03:25:02.69#ibcon#about to read 5, iclass 14, count 2 2006.286.03:25:02.69#ibcon#read 5, iclass 14, count 2 2006.286.03:25:02.69#ibcon#about to read 6, iclass 14, count 2 2006.286.03:25:02.69#ibcon#read 6, iclass 14, count 2 2006.286.03:25:02.69#ibcon#end of sib2, iclass 14, count 2 2006.286.03:25:02.69#ibcon#*mode == 0, iclass 14, count 2 2006.286.03:25:02.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.03:25:02.69#ibcon#[25=AT05-03\r\n] 2006.286.03:25:02.69#ibcon#*before write, iclass 14, count 2 2006.286.03:25:02.69#ibcon#enter sib2, iclass 14, count 2 2006.286.03:25:02.69#ibcon#flushed, iclass 14, count 2 2006.286.03:25:02.69#ibcon#about to write, iclass 14, count 2 2006.286.03:25:02.69#ibcon#wrote, iclass 14, count 2 2006.286.03:25:02.69#ibcon#about to read 3, iclass 14, count 2 2006.286.03:25:02.72#ibcon#read 3, iclass 14, count 2 2006.286.03:25:02.72#ibcon#about to read 4, iclass 14, count 2 2006.286.03:25:02.72#ibcon#read 4, iclass 14, count 2 2006.286.03:25:02.72#ibcon#about to read 5, iclass 14, count 2 2006.286.03:25:02.72#ibcon#read 5, iclass 14, count 2 2006.286.03:25:02.72#ibcon#about to read 6, iclass 14, count 2 2006.286.03:25:02.72#ibcon#read 6, iclass 14, count 2 2006.286.03:25:02.72#ibcon#end of sib2, iclass 14, count 2 2006.286.03:25:02.72#ibcon#*after write, iclass 14, count 2 2006.286.03:25:02.72#ibcon#*before return 0, iclass 14, count 2 2006.286.03:25:02.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:25:02.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:25:02.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.03:25:02.72#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:02.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:25:02.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:25:02.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:25:02.84#ibcon#enter wrdev, iclass 14, count 0 2006.286.03:25:02.84#ibcon#first serial, iclass 14, count 0 2006.286.03:25:02.84#ibcon#enter sib2, iclass 14, count 0 2006.286.03:25:02.84#ibcon#flushed, iclass 14, count 0 2006.286.03:25:02.84#ibcon#about to write, iclass 14, count 0 2006.286.03:25:02.84#ibcon#wrote, iclass 14, count 0 2006.286.03:25:02.84#ibcon#about to read 3, iclass 14, count 0 2006.286.03:25:02.86#ibcon#read 3, iclass 14, count 0 2006.286.03:25:02.86#ibcon#about to read 4, iclass 14, count 0 2006.286.03:25:02.86#ibcon#read 4, iclass 14, count 0 2006.286.03:25:02.86#ibcon#about to read 5, iclass 14, count 0 2006.286.03:25:02.86#ibcon#read 5, iclass 14, count 0 2006.286.03:25:02.86#ibcon#about to read 6, iclass 14, count 0 2006.286.03:25:02.86#ibcon#read 6, iclass 14, count 0 2006.286.03:25:02.86#ibcon#end of sib2, iclass 14, count 0 2006.286.03:25:02.86#ibcon#*mode == 0, iclass 14, count 0 2006.286.03:25:02.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.03:25:02.86#ibcon#[25=USB\r\n] 2006.286.03:25:02.86#ibcon#*before write, iclass 14, count 0 2006.286.03:25:02.86#ibcon#enter sib2, iclass 14, count 0 2006.286.03:25:02.86#ibcon#flushed, iclass 14, count 0 2006.286.03:25:02.86#ibcon#about to write, iclass 14, count 0 2006.286.03:25:02.86#ibcon#wrote, iclass 14, count 0 2006.286.03:25:02.86#ibcon#about to read 3, iclass 14, count 0 2006.286.03:25:02.89#ibcon#read 3, iclass 14, count 0 2006.286.03:25:02.89#ibcon#about to read 4, iclass 14, count 0 2006.286.03:25:02.89#ibcon#read 4, iclass 14, count 0 2006.286.03:25:02.89#ibcon#about to read 5, iclass 14, count 0 2006.286.03:25:02.89#ibcon#read 5, iclass 14, count 0 2006.286.03:25:02.89#ibcon#about to read 6, iclass 14, count 0 2006.286.03:25:02.89#ibcon#read 6, iclass 14, count 0 2006.286.03:25:02.89#ibcon#end of sib2, iclass 14, count 0 2006.286.03:25:02.89#ibcon#*after write, iclass 14, count 0 2006.286.03:25:02.89#ibcon#*before return 0, iclass 14, count 0 2006.286.03:25:02.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:25:02.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:25:02.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.03:25:02.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.03:25:02.89$vck44/valo=6,814.99 2006.286.03:25:02.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.03:25:02.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.03:25:02.89#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:02.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:25:02.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:25:02.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:25:02.89#ibcon#enter wrdev, iclass 16, count 0 2006.286.03:25:02.89#ibcon#first serial, iclass 16, count 0 2006.286.03:25:02.89#ibcon#enter sib2, iclass 16, count 0 2006.286.03:25:02.89#ibcon#flushed, iclass 16, count 0 2006.286.03:25:02.89#ibcon#about to write, iclass 16, count 0 2006.286.03:25:02.89#ibcon#wrote, iclass 16, count 0 2006.286.03:25:02.89#ibcon#about to read 3, iclass 16, count 0 2006.286.03:25:02.91#ibcon#read 3, iclass 16, count 0 2006.286.03:25:02.91#ibcon#about to read 4, iclass 16, count 0 2006.286.03:25:02.91#ibcon#read 4, iclass 16, count 0 2006.286.03:25:02.91#ibcon#about to read 5, iclass 16, count 0 2006.286.03:25:02.91#ibcon#read 5, iclass 16, count 0 2006.286.03:25:02.91#ibcon#about to read 6, iclass 16, count 0 2006.286.03:25:02.91#ibcon#read 6, iclass 16, count 0 2006.286.03:25:02.91#ibcon#end of sib2, iclass 16, count 0 2006.286.03:25:02.91#ibcon#*mode == 0, iclass 16, count 0 2006.286.03:25:02.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.03:25:02.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.03:25:02.91#ibcon#*before write, iclass 16, count 0 2006.286.03:25:02.91#ibcon#enter sib2, iclass 16, count 0 2006.286.03:25:02.91#ibcon#flushed, iclass 16, count 0 2006.286.03:25:02.91#ibcon#about to write, iclass 16, count 0 2006.286.03:25:02.91#ibcon#wrote, iclass 16, count 0 2006.286.03:25:02.91#ibcon#about to read 3, iclass 16, count 0 2006.286.03:25:02.95#ibcon#read 3, iclass 16, count 0 2006.286.03:25:02.95#ibcon#about to read 4, iclass 16, count 0 2006.286.03:25:02.95#ibcon#read 4, iclass 16, count 0 2006.286.03:25:02.95#ibcon#about to read 5, iclass 16, count 0 2006.286.03:25:02.95#ibcon#read 5, iclass 16, count 0 2006.286.03:25:02.95#ibcon#about to read 6, iclass 16, count 0 2006.286.03:25:02.95#ibcon#read 6, iclass 16, count 0 2006.286.03:25:02.95#ibcon#end of sib2, iclass 16, count 0 2006.286.03:25:02.95#ibcon#*after write, iclass 16, count 0 2006.286.03:25:02.95#ibcon#*before return 0, iclass 16, count 0 2006.286.03:25:02.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:25:02.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:25:02.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.03:25:02.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.03:25:02.95$vck44/va=6,4 2006.286.03:25:02.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.03:25:02.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.03:25:02.95#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:02.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:25:03.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:25:03.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:25:03.01#ibcon#enter wrdev, iclass 18, count 2 2006.286.03:25:03.01#ibcon#first serial, iclass 18, count 2 2006.286.03:25:03.01#ibcon#enter sib2, iclass 18, count 2 2006.286.03:25:03.01#ibcon#flushed, iclass 18, count 2 2006.286.03:25:03.01#ibcon#about to write, iclass 18, count 2 2006.286.03:25:03.01#ibcon#wrote, iclass 18, count 2 2006.286.03:25:03.01#ibcon#about to read 3, iclass 18, count 2 2006.286.03:25:03.03#ibcon#read 3, iclass 18, count 2 2006.286.03:25:03.03#ibcon#about to read 4, iclass 18, count 2 2006.286.03:25:03.03#ibcon#read 4, iclass 18, count 2 2006.286.03:25:03.03#ibcon#about to read 5, iclass 18, count 2 2006.286.03:25:03.03#ibcon#read 5, iclass 18, count 2 2006.286.03:25:03.03#ibcon#about to read 6, iclass 18, count 2 2006.286.03:25:03.03#ibcon#read 6, iclass 18, count 2 2006.286.03:25:03.03#ibcon#end of sib2, iclass 18, count 2 2006.286.03:25:03.03#ibcon#*mode == 0, iclass 18, count 2 2006.286.03:25:03.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.03:25:03.03#ibcon#[25=AT06-04\r\n] 2006.286.03:25:03.03#ibcon#*before write, iclass 18, count 2 2006.286.03:25:03.03#ibcon#enter sib2, iclass 18, count 2 2006.286.03:25:03.03#ibcon#flushed, iclass 18, count 2 2006.286.03:25:03.03#ibcon#about to write, iclass 18, count 2 2006.286.03:25:03.03#ibcon#wrote, iclass 18, count 2 2006.286.03:25:03.03#ibcon#about to read 3, iclass 18, count 2 2006.286.03:25:03.06#ibcon#read 3, iclass 18, count 2 2006.286.03:25:03.06#ibcon#about to read 4, iclass 18, count 2 2006.286.03:25:03.06#ibcon#read 4, iclass 18, count 2 2006.286.03:25:03.06#ibcon#about to read 5, iclass 18, count 2 2006.286.03:25:03.06#ibcon#read 5, iclass 18, count 2 2006.286.03:25:03.06#ibcon#about to read 6, iclass 18, count 2 2006.286.03:25:03.06#ibcon#read 6, iclass 18, count 2 2006.286.03:25:03.06#ibcon#end of sib2, iclass 18, count 2 2006.286.03:25:03.06#ibcon#*after write, iclass 18, count 2 2006.286.03:25:03.06#ibcon#*before return 0, iclass 18, count 2 2006.286.03:25:03.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:25:03.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:25:03.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.03:25:03.06#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:03.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:25:03.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:25:03.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:25:03.18#ibcon#enter wrdev, iclass 18, count 0 2006.286.03:25:03.18#ibcon#first serial, iclass 18, count 0 2006.286.03:25:03.18#ibcon#enter sib2, iclass 18, count 0 2006.286.03:25:03.18#ibcon#flushed, iclass 18, count 0 2006.286.03:25:03.18#ibcon#about to write, iclass 18, count 0 2006.286.03:25:03.18#ibcon#wrote, iclass 18, count 0 2006.286.03:25:03.18#ibcon#about to read 3, iclass 18, count 0 2006.286.03:25:03.20#ibcon#read 3, iclass 18, count 0 2006.286.03:25:03.20#ibcon#about to read 4, iclass 18, count 0 2006.286.03:25:03.20#ibcon#read 4, iclass 18, count 0 2006.286.03:25:03.20#ibcon#about to read 5, iclass 18, count 0 2006.286.03:25:03.20#ibcon#read 5, iclass 18, count 0 2006.286.03:25:03.20#ibcon#about to read 6, iclass 18, count 0 2006.286.03:25:03.20#ibcon#read 6, iclass 18, count 0 2006.286.03:25:03.20#ibcon#end of sib2, iclass 18, count 0 2006.286.03:25:03.20#ibcon#*mode == 0, iclass 18, count 0 2006.286.03:25:03.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.03:25:03.20#ibcon#[25=USB\r\n] 2006.286.03:25:03.20#ibcon#*before write, iclass 18, count 0 2006.286.03:25:03.20#ibcon#enter sib2, iclass 18, count 0 2006.286.03:25:03.20#ibcon#flushed, iclass 18, count 0 2006.286.03:25:03.20#ibcon#about to write, iclass 18, count 0 2006.286.03:25:03.20#ibcon#wrote, iclass 18, count 0 2006.286.03:25:03.20#ibcon#about to read 3, iclass 18, count 0 2006.286.03:25:03.23#ibcon#read 3, iclass 18, count 0 2006.286.03:25:03.23#ibcon#about to read 4, iclass 18, count 0 2006.286.03:25:03.23#ibcon#read 4, iclass 18, count 0 2006.286.03:25:03.23#ibcon#about to read 5, iclass 18, count 0 2006.286.03:25:03.23#ibcon#read 5, iclass 18, count 0 2006.286.03:25:03.23#ibcon#about to read 6, iclass 18, count 0 2006.286.03:25:03.23#ibcon#read 6, iclass 18, count 0 2006.286.03:25:03.23#ibcon#end of sib2, iclass 18, count 0 2006.286.03:25:03.23#ibcon#*after write, iclass 18, count 0 2006.286.03:25:03.23#ibcon#*before return 0, iclass 18, count 0 2006.286.03:25:03.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:25:03.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:25:03.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.03:25:03.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.03:25:03.23$vck44/valo=7,864.99 2006.286.03:25:03.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.03:25:03.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.03:25:03.23#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:03.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:25:03.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:25:03.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:25:03.23#ibcon#enter wrdev, iclass 20, count 0 2006.286.03:25:03.23#ibcon#first serial, iclass 20, count 0 2006.286.03:25:03.23#ibcon#enter sib2, iclass 20, count 0 2006.286.03:25:03.23#ibcon#flushed, iclass 20, count 0 2006.286.03:25:03.23#ibcon#about to write, iclass 20, count 0 2006.286.03:25:03.23#ibcon#wrote, iclass 20, count 0 2006.286.03:25:03.23#ibcon#about to read 3, iclass 20, count 0 2006.286.03:25:03.25#ibcon#read 3, iclass 20, count 0 2006.286.03:25:03.25#ibcon#about to read 4, iclass 20, count 0 2006.286.03:25:03.25#ibcon#read 4, iclass 20, count 0 2006.286.03:25:03.25#ibcon#about to read 5, iclass 20, count 0 2006.286.03:25:03.25#ibcon#read 5, iclass 20, count 0 2006.286.03:25:03.25#ibcon#about to read 6, iclass 20, count 0 2006.286.03:25:03.25#ibcon#read 6, iclass 20, count 0 2006.286.03:25:03.25#ibcon#end of sib2, iclass 20, count 0 2006.286.03:25:03.25#ibcon#*mode == 0, iclass 20, count 0 2006.286.03:25:03.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.03:25:03.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.03:25:03.25#ibcon#*before write, iclass 20, count 0 2006.286.03:25:03.25#ibcon#enter sib2, iclass 20, count 0 2006.286.03:25:03.25#ibcon#flushed, iclass 20, count 0 2006.286.03:25:03.25#ibcon#about to write, iclass 20, count 0 2006.286.03:25:03.25#ibcon#wrote, iclass 20, count 0 2006.286.03:25:03.25#ibcon#about to read 3, iclass 20, count 0 2006.286.03:25:03.29#ibcon#read 3, iclass 20, count 0 2006.286.03:25:03.29#ibcon#about to read 4, iclass 20, count 0 2006.286.03:25:03.29#ibcon#read 4, iclass 20, count 0 2006.286.03:25:03.29#ibcon#about to read 5, iclass 20, count 0 2006.286.03:25:03.29#ibcon#read 5, iclass 20, count 0 2006.286.03:25:03.29#ibcon#about to read 6, iclass 20, count 0 2006.286.03:25:03.29#ibcon#read 6, iclass 20, count 0 2006.286.03:25:03.29#ibcon#end of sib2, iclass 20, count 0 2006.286.03:25:03.29#ibcon#*after write, iclass 20, count 0 2006.286.03:25:03.29#ibcon#*before return 0, iclass 20, count 0 2006.286.03:25:03.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:25:03.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:25:03.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.03:25:03.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.03:25:03.29$vck44/va=7,4 2006.286.03:25:03.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.03:25:03.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.03:25:03.29#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:03.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:25:03.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:25:03.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:25:03.35#ibcon#enter wrdev, iclass 22, count 2 2006.286.03:25:03.35#ibcon#first serial, iclass 22, count 2 2006.286.03:25:03.35#ibcon#enter sib2, iclass 22, count 2 2006.286.03:25:03.35#ibcon#flushed, iclass 22, count 2 2006.286.03:25:03.35#ibcon#about to write, iclass 22, count 2 2006.286.03:25:03.35#ibcon#wrote, iclass 22, count 2 2006.286.03:25:03.35#ibcon#about to read 3, iclass 22, count 2 2006.286.03:25:03.37#ibcon#read 3, iclass 22, count 2 2006.286.03:25:03.37#ibcon#about to read 4, iclass 22, count 2 2006.286.03:25:03.37#ibcon#read 4, iclass 22, count 2 2006.286.03:25:03.37#ibcon#about to read 5, iclass 22, count 2 2006.286.03:25:03.37#ibcon#read 5, iclass 22, count 2 2006.286.03:25:03.37#ibcon#about to read 6, iclass 22, count 2 2006.286.03:25:03.37#ibcon#read 6, iclass 22, count 2 2006.286.03:25:03.37#ibcon#end of sib2, iclass 22, count 2 2006.286.03:25:03.37#ibcon#*mode == 0, iclass 22, count 2 2006.286.03:25:03.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.03:25:03.37#ibcon#[25=AT07-04\r\n] 2006.286.03:25:03.37#ibcon#*before write, iclass 22, count 2 2006.286.03:25:03.37#ibcon#enter sib2, iclass 22, count 2 2006.286.03:25:03.37#ibcon#flushed, iclass 22, count 2 2006.286.03:25:03.37#ibcon#about to write, iclass 22, count 2 2006.286.03:25:03.37#ibcon#wrote, iclass 22, count 2 2006.286.03:25:03.37#ibcon#about to read 3, iclass 22, count 2 2006.286.03:25:03.40#ibcon#read 3, iclass 22, count 2 2006.286.03:25:03.40#ibcon#about to read 4, iclass 22, count 2 2006.286.03:25:03.40#ibcon#read 4, iclass 22, count 2 2006.286.03:25:03.40#ibcon#about to read 5, iclass 22, count 2 2006.286.03:25:03.40#ibcon#read 5, iclass 22, count 2 2006.286.03:25:03.40#ibcon#about to read 6, iclass 22, count 2 2006.286.03:25:03.40#ibcon#read 6, iclass 22, count 2 2006.286.03:25:03.40#ibcon#end of sib2, iclass 22, count 2 2006.286.03:25:03.40#ibcon#*after write, iclass 22, count 2 2006.286.03:25:03.40#ibcon#*before return 0, iclass 22, count 2 2006.286.03:25:03.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:25:03.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:25:03.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.03:25:03.40#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:03.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:25:03.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:25:03.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:25:03.52#ibcon#enter wrdev, iclass 22, count 0 2006.286.03:25:03.52#ibcon#first serial, iclass 22, count 0 2006.286.03:25:03.52#ibcon#enter sib2, iclass 22, count 0 2006.286.03:25:03.52#ibcon#flushed, iclass 22, count 0 2006.286.03:25:03.52#ibcon#about to write, iclass 22, count 0 2006.286.03:25:03.52#ibcon#wrote, iclass 22, count 0 2006.286.03:25:03.52#ibcon#about to read 3, iclass 22, count 0 2006.286.03:25:03.54#ibcon#read 3, iclass 22, count 0 2006.286.03:25:03.54#ibcon#about to read 4, iclass 22, count 0 2006.286.03:25:03.54#ibcon#read 4, iclass 22, count 0 2006.286.03:25:03.54#ibcon#about to read 5, iclass 22, count 0 2006.286.03:25:03.54#ibcon#read 5, iclass 22, count 0 2006.286.03:25:03.54#ibcon#about to read 6, iclass 22, count 0 2006.286.03:25:03.54#ibcon#read 6, iclass 22, count 0 2006.286.03:25:03.54#ibcon#end of sib2, iclass 22, count 0 2006.286.03:25:03.54#ibcon#*mode == 0, iclass 22, count 0 2006.286.03:25:03.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.03:25:03.54#ibcon#[25=USB\r\n] 2006.286.03:25:03.54#ibcon#*before write, iclass 22, count 0 2006.286.03:25:03.54#ibcon#enter sib2, iclass 22, count 0 2006.286.03:25:03.54#ibcon#flushed, iclass 22, count 0 2006.286.03:25:03.54#ibcon#about to write, iclass 22, count 0 2006.286.03:25:03.54#ibcon#wrote, iclass 22, count 0 2006.286.03:25:03.54#ibcon#about to read 3, iclass 22, count 0 2006.286.03:25:03.57#ibcon#read 3, iclass 22, count 0 2006.286.03:25:03.57#ibcon#about to read 4, iclass 22, count 0 2006.286.03:25:03.57#ibcon#read 4, iclass 22, count 0 2006.286.03:25:03.57#ibcon#about to read 5, iclass 22, count 0 2006.286.03:25:03.57#ibcon#read 5, iclass 22, count 0 2006.286.03:25:03.57#ibcon#about to read 6, iclass 22, count 0 2006.286.03:25:03.57#ibcon#read 6, iclass 22, count 0 2006.286.03:25:03.57#ibcon#end of sib2, iclass 22, count 0 2006.286.03:25:03.57#ibcon#*after write, iclass 22, count 0 2006.286.03:25:03.57#ibcon#*before return 0, iclass 22, count 0 2006.286.03:25:03.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:25:03.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:25:03.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.03:25:03.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.03:25:03.57$vck44/valo=8,884.99 2006.286.03:25:03.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.03:25:03.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.03:25:03.57#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:03.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:25:03.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:25:03.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:25:03.57#ibcon#enter wrdev, iclass 24, count 0 2006.286.03:25:03.57#ibcon#first serial, iclass 24, count 0 2006.286.03:25:03.57#ibcon#enter sib2, iclass 24, count 0 2006.286.03:25:03.57#ibcon#flushed, iclass 24, count 0 2006.286.03:25:03.57#ibcon#about to write, iclass 24, count 0 2006.286.03:25:03.57#ibcon#wrote, iclass 24, count 0 2006.286.03:25:03.57#ibcon#about to read 3, iclass 24, count 0 2006.286.03:25:03.59#ibcon#read 3, iclass 24, count 0 2006.286.03:25:03.59#ibcon#about to read 4, iclass 24, count 0 2006.286.03:25:03.59#ibcon#read 4, iclass 24, count 0 2006.286.03:25:03.59#ibcon#about to read 5, iclass 24, count 0 2006.286.03:25:03.59#ibcon#read 5, iclass 24, count 0 2006.286.03:25:03.59#ibcon#about to read 6, iclass 24, count 0 2006.286.03:25:03.59#ibcon#read 6, iclass 24, count 0 2006.286.03:25:03.59#ibcon#end of sib2, iclass 24, count 0 2006.286.03:25:03.59#ibcon#*mode == 0, iclass 24, count 0 2006.286.03:25:03.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.03:25:03.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.03:25:03.59#ibcon#*before write, iclass 24, count 0 2006.286.03:25:03.59#ibcon#enter sib2, iclass 24, count 0 2006.286.03:25:03.59#ibcon#flushed, iclass 24, count 0 2006.286.03:25:03.59#ibcon#about to write, iclass 24, count 0 2006.286.03:25:03.59#ibcon#wrote, iclass 24, count 0 2006.286.03:25:03.59#ibcon#about to read 3, iclass 24, count 0 2006.286.03:25:03.63#ibcon#read 3, iclass 24, count 0 2006.286.03:25:03.63#ibcon#about to read 4, iclass 24, count 0 2006.286.03:25:03.63#ibcon#read 4, iclass 24, count 0 2006.286.03:25:03.63#ibcon#about to read 5, iclass 24, count 0 2006.286.03:25:03.63#ibcon#read 5, iclass 24, count 0 2006.286.03:25:03.63#ibcon#about to read 6, iclass 24, count 0 2006.286.03:25:03.63#ibcon#read 6, iclass 24, count 0 2006.286.03:25:03.63#ibcon#end of sib2, iclass 24, count 0 2006.286.03:25:03.63#ibcon#*after write, iclass 24, count 0 2006.286.03:25:03.63#ibcon#*before return 0, iclass 24, count 0 2006.286.03:25:03.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:25:03.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:25:03.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.03:25:03.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.03:25:03.63$vck44/va=8,3 2006.286.03:25:03.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.03:25:03.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.03:25:03.63#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:03.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:25:03.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:25:03.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:25:03.69#ibcon#enter wrdev, iclass 26, count 2 2006.286.03:25:03.69#ibcon#first serial, iclass 26, count 2 2006.286.03:25:03.69#ibcon#enter sib2, iclass 26, count 2 2006.286.03:25:03.69#ibcon#flushed, iclass 26, count 2 2006.286.03:25:03.69#ibcon#about to write, iclass 26, count 2 2006.286.03:25:03.69#ibcon#wrote, iclass 26, count 2 2006.286.03:25:03.69#ibcon#about to read 3, iclass 26, count 2 2006.286.03:25:03.71#ibcon#read 3, iclass 26, count 2 2006.286.03:25:03.71#ibcon#about to read 4, iclass 26, count 2 2006.286.03:25:03.71#ibcon#read 4, iclass 26, count 2 2006.286.03:25:03.71#ibcon#about to read 5, iclass 26, count 2 2006.286.03:25:03.71#ibcon#read 5, iclass 26, count 2 2006.286.03:25:03.71#ibcon#about to read 6, iclass 26, count 2 2006.286.03:25:03.71#ibcon#read 6, iclass 26, count 2 2006.286.03:25:03.71#ibcon#end of sib2, iclass 26, count 2 2006.286.03:25:03.71#ibcon#*mode == 0, iclass 26, count 2 2006.286.03:25:03.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.03:25:03.71#ibcon#[25=AT08-03\r\n] 2006.286.03:25:03.71#ibcon#*before write, iclass 26, count 2 2006.286.03:25:03.71#ibcon#enter sib2, iclass 26, count 2 2006.286.03:25:03.71#ibcon#flushed, iclass 26, count 2 2006.286.03:25:03.71#ibcon#about to write, iclass 26, count 2 2006.286.03:25:03.71#ibcon#wrote, iclass 26, count 2 2006.286.03:25:03.71#ibcon#about to read 3, iclass 26, count 2 2006.286.03:25:03.74#ibcon#read 3, iclass 26, count 2 2006.286.03:25:03.74#ibcon#about to read 4, iclass 26, count 2 2006.286.03:25:03.74#ibcon#read 4, iclass 26, count 2 2006.286.03:25:03.74#ibcon#about to read 5, iclass 26, count 2 2006.286.03:25:03.74#ibcon#read 5, iclass 26, count 2 2006.286.03:25:03.74#ibcon#about to read 6, iclass 26, count 2 2006.286.03:25:03.74#ibcon#read 6, iclass 26, count 2 2006.286.03:25:03.74#ibcon#end of sib2, iclass 26, count 2 2006.286.03:25:03.74#ibcon#*after write, iclass 26, count 2 2006.286.03:25:03.74#ibcon#*before return 0, iclass 26, count 2 2006.286.03:25:03.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:25:03.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:25:03.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.03:25:03.74#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:03.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:25:03.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:25:03.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:25:03.86#ibcon#enter wrdev, iclass 26, count 0 2006.286.03:25:03.86#ibcon#first serial, iclass 26, count 0 2006.286.03:25:03.86#ibcon#enter sib2, iclass 26, count 0 2006.286.03:25:03.86#ibcon#flushed, iclass 26, count 0 2006.286.03:25:03.86#ibcon#about to write, iclass 26, count 0 2006.286.03:25:03.86#ibcon#wrote, iclass 26, count 0 2006.286.03:25:03.86#ibcon#about to read 3, iclass 26, count 0 2006.286.03:25:03.88#ibcon#read 3, iclass 26, count 0 2006.286.03:25:03.88#ibcon#about to read 4, iclass 26, count 0 2006.286.03:25:03.88#ibcon#read 4, iclass 26, count 0 2006.286.03:25:03.88#ibcon#about to read 5, iclass 26, count 0 2006.286.03:25:03.88#ibcon#read 5, iclass 26, count 0 2006.286.03:25:03.88#ibcon#about to read 6, iclass 26, count 0 2006.286.03:25:03.88#ibcon#read 6, iclass 26, count 0 2006.286.03:25:03.88#ibcon#end of sib2, iclass 26, count 0 2006.286.03:25:03.88#ibcon#*mode == 0, iclass 26, count 0 2006.286.03:25:03.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.03:25:03.88#ibcon#[25=USB\r\n] 2006.286.03:25:03.88#ibcon#*before write, iclass 26, count 0 2006.286.03:25:03.88#ibcon#enter sib2, iclass 26, count 0 2006.286.03:25:03.88#ibcon#flushed, iclass 26, count 0 2006.286.03:25:03.88#ibcon#about to write, iclass 26, count 0 2006.286.03:25:03.88#ibcon#wrote, iclass 26, count 0 2006.286.03:25:03.88#ibcon#about to read 3, iclass 26, count 0 2006.286.03:25:03.91#ibcon#read 3, iclass 26, count 0 2006.286.03:25:03.91#ibcon#about to read 4, iclass 26, count 0 2006.286.03:25:03.91#ibcon#read 4, iclass 26, count 0 2006.286.03:25:03.91#ibcon#about to read 5, iclass 26, count 0 2006.286.03:25:03.91#ibcon#read 5, iclass 26, count 0 2006.286.03:25:03.91#ibcon#about to read 6, iclass 26, count 0 2006.286.03:25:03.91#ibcon#read 6, iclass 26, count 0 2006.286.03:25:03.91#ibcon#end of sib2, iclass 26, count 0 2006.286.03:25:03.91#ibcon#*after write, iclass 26, count 0 2006.286.03:25:03.91#ibcon#*before return 0, iclass 26, count 0 2006.286.03:25:03.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:25:03.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:25:03.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.03:25:03.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.03:25:03.91$vck44/vblo=1,629.99 2006.286.03:25:03.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.03:25:03.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.03:25:03.91#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:03.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:25:03.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:25:03.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:25:03.91#ibcon#enter wrdev, iclass 28, count 0 2006.286.03:25:03.91#ibcon#first serial, iclass 28, count 0 2006.286.03:25:03.91#ibcon#enter sib2, iclass 28, count 0 2006.286.03:25:03.91#ibcon#flushed, iclass 28, count 0 2006.286.03:25:03.91#ibcon#about to write, iclass 28, count 0 2006.286.03:25:03.91#ibcon#wrote, iclass 28, count 0 2006.286.03:25:03.91#ibcon#about to read 3, iclass 28, count 0 2006.286.03:25:03.93#ibcon#read 3, iclass 28, count 0 2006.286.03:25:03.93#ibcon#about to read 4, iclass 28, count 0 2006.286.03:25:03.93#ibcon#read 4, iclass 28, count 0 2006.286.03:25:03.93#ibcon#about to read 5, iclass 28, count 0 2006.286.03:25:03.93#ibcon#read 5, iclass 28, count 0 2006.286.03:25:03.93#ibcon#about to read 6, iclass 28, count 0 2006.286.03:25:03.93#ibcon#read 6, iclass 28, count 0 2006.286.03:25:03.93#ibcon#end of sib2, iclass 28, count 0 2006.286.03:25:03.93#ibcon#*mode == 0, iclass 28, count 0 2006.286.03:25:03.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.03:25:03.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.03:25:03.93#ibcon#*before write, iclass 28, count 0 2006.286.03:25:03.93#ibcon#enter sib2, iclass 28, count 0 2006.286.03:25:03.93#ibcon#flushed, iclass 28, count 0 2006.286.03:25:03.93#ibcon#about to write, iclass 28, count 0 2006.286.03:25:03.93#ibcon#wrote, iclass 28, count 0 2006.286.03:25:03.93#ibcon#about to read 3, iclass 28, count 0 2006.286.03:25:03.97#ibcon#read 3, iclass 28, count 0 2006.286.03:25:03.97#ibcon#about to read 4, iclass 28, count 0 2006.286.03:25:03.97#ibcon#read 4, iclass 28, count 0 2006.286.03:25:03.97#ibcon#about to read 5, iclass 28, count 0 2006.286.03:25:03.97#ibcon#read 5, iclass 28, count 0 2006.286.03:25:03.97#ibcon#about to read 6, iclass 28, count 0 2006.286.03:25:03.97#ibcon#read 6, iclass 28, count 0 2006.286.03:25:03.97#ibcon#end of sib2, iclass 28, count 0 2006.286.03:25:03.97#ibcon#*after write, iclass 28, count 0 2006.286.03:25:03.97#ibcon#*before return 0, iclass 28, count 0 2006.286.03:25:03.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:25:03.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:25:03.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.03:25:03.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.03:25:03.97$vck44/vb=1,4 2006.286.03:25:03.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.03:25:03.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.03:25:03.97#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:03.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:25:03.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:25:03.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:25:03.97#ibcon#enter wrdev, iclass 30, count 2 2006.286.03:25:03.97#ibcon#first serial, iclass 30, count 2 2006.286.03:25:03.97#ibcon#enter sib2, iclass 30, count 2 2006.286.03:25:03.97#ibcon#flushed, iclass 30, count 2 2006.286.03:25:03.97#ibcon#about to write, iclass 30, count 2 2006.286.03:25:03.97#ibcon#wrote, iclass 30, count 2 2006.286.03:25:03.97#ibcon#about to read 3, iclass 30, count 2 2006.286.03:25:03.99#ibcon#read 3, iclass 30, count 2 2006.286.03:25:03.99#ibcon#about to read 4, iclass 30, count 2 2006.286.03:25:03.99#ibcon#read 4, iclass 30, count 2 2006.286.03:25:03.99#ibcon#about to read 5, iclass 30, count 2 2006.286.03:25:03.99#ibcon#read 5, iclass 30, count 2 2006.286.03:25:03.99#ibcon#about to read 6, iclass 30, count 2 2006.286.03:25:03.99#ibcon#read 6, iclass 30, count 2 2006.286.03:25:03.99#ibcon#end of sib2, iclass 30, count 2 2006.286.03:25:03.99#ibcon#*mode == 0, iclass 30, count 2 2006.286.03:25:03.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.03:25:03.99#ibcon#[27=AT01-04\r\n] 2006.286.03:25:03.99#ibcon#*before write, iclass 30, count 2 2006.286.03:25:03.99#ibcon#enter sib2, iclass 30, count 2 2006.286.03:25:03.99#ibcon#flushed, iclass 30, count 2 2006.286.03:25:03.99#ibcon#about to write, iclass 30, count 2 2006.286.03:25:03.99#ibcon#wrote, iclass 30, count 2 2006.286.03:25:03.99#ibcon#about to read 3, iclass 30, count 2 2006.286.03:25:04.02#ibcon#read 3, iclass 30, count 2 2006.286.03:25:04.02#ibcon#about to read 4, iclass 30, count 2 2006.286.03:25:04.02#ibcon#read 4, iclass 30, count 2 2006.286.03:25:04.02#ibcon#about to read 5, iclass 30, count 2 2006.286.03:25:04.02#ibcon#read 5, iclass 30, count 2 2006.286.03:25:04.02#ibcon#about to read 6, iclass 30, count 2 2006.286.03:25:04.02#ibcon#read 6, iclass 30, count 2 2006.286.03:25:04.02#ibcon#end of sib2, iclass 30, count 2 2006.286.03:25:04.02#ibcon#*after write, iclass 30, count 2 2006.286.03:25:04.02#ibcon#*before return 0, iclass 30, count 2 2006.286.03:25:04.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:25:04.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:25:04.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.03:25:04.02#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:04.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:25:04.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:25:04.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:25:04.18#ibcon#enter wrdev, iclass 30, count 0 2006.286.03:25:04.18#ibcon#first serial, iclass 30, count 0 2006.286.03:25:04.18#ibcon#enter sib2, iclass 30, count 0 2006.286.03:25:04.18#ibcon#flushed, iclass 30, count 0 2006.286.03:25:04.18#ibcon#about to write, iclass 30, count 0 2006.286.03:25:04.18#ibcon#wrote, iclass 30, count 0 2006.286.03:25:04.18#ibcon#about to read 3, iclass 30, count 0 2006.286.03:25:04.19#ibcon#read 3, iclass 30, count 0 2006.286.03:25:04.19#ibcon#about to read 4, iclass 30, count 0 2006.286.03:25:04.19#ibcon#read 4, iclass 30, count 0 2006.286.03:25:04.19#ibcon#about to read 5, iclass 30, count 0 2006.286.03:25:04.19#ibcon#read 5, iclass 30, count 0 2006.286.03:25:04.19#ibcon#about to read 6, iclass 30, count 0 2006.286.03:25:04.19#ibcon#read 6, iclass 30, count 0 2006.286.03:25:04.19#ibcon#end of sib2, iclass 30, count 0 2006.286.03:25:04.19#ibcon#*mode == 0, iclass 30, count 0 2006.286.03:25:04.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.03:25:04.19#ibcon#[27=USB\r\n] 2006.286.03:25:04.19#ibcon#*before write, iclass 30, count 0 2006.286.03:25:04.19#ibcon#enter sib2, iclass 30, count 0 2006.286.03:25:04.19#ibcon#flushed, iclass 30, count 0 2006.286.03:25:04.19#ibcon#about to write, iclass 30, count 0 2006.286.03:25:04.19#ibcon#wrote, iclass 30, count 0 2006.286.03:25:04.19#ibcon#about to read 3, iclass 30, count 0 2006.286.03:25:04.22#ibcon#read 3, iclass 30, count 0 2006.286.03:25:04.22#ibcon#about to read 4, iclass 30, count 0 2006.286.03:25:04.22#ibcon#read 4, iclass 30, count 0 2006.286.03:25:04.22#ibcon#about to read 5, iclass 30, count 0 2006.286.03:25:04.22#ibcon#read 5, iclass 30, count 0 2006.286.03:25:04.22#ibcon#about to read 6, iclass 30, count 0 2006.286.03:25:04.22#ibcon#read 6, iclass 30, count 0 2006.286.03:25:04.22#ibcon#end of sib2, iclass 30, count 0 2006.286.03:25:04.22#ibcon#*after write, iclass 30, count 0 2006.286.03:25:04.22#ibcon#*before return 0, iclass 30, count 0 2006.286.03:25:04.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:25:04.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:25:04.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.03:25:04.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.03:25:04.22$vck44/vblo=2,634.99 2006.286.03:25:04.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.03:25:04.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.03:25:04.22#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:04.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:25:04.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:25:04.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:25:04.22#ibcon#enter wrdev, iclass 32, count 0 2006.286.03:25:04.22#ibcon#first serial, iclass 32, count 0 2006.286.03:25:04.22#ibcon#enter sib2, iclass 32, count 0 2006.286.03:25:04.22#ibcon#flushed, iclass 32, count 0 2006.286.03:25:04.22#ibcon#about to write, iclass 32, count 0 2006.286.03:25:04.22#ibcon#wrote, iclass 32, count 0 2006.286.03:25:04.22#ibcon#about to read 3, iclass 32, count 0 2006.286.03:25:04.24#ibcon#read 3, iclass 32, count 0 2006.286.03:25:04.24#ibcon#about to read 4, iclass 32, count 0 2006.286.03:25:04.24#ibcon#read 4, iclass 32, count 0 2006.286.03:25:04.24#ibcon#about to read 5, iclass 32, count 0 2006.286.03:25:04.24#ibcon#read 5, iclass 32, count 0 2006.286.03:25:04.24#ibcon#about to read 6, iclass 32, count 0 2006.286.03:25:04.24#ibcon#read 6, iclass 32, count 0 2006.286.03:25:04.24#ibcon#end of sib2, iclass 32, count 0 2006.286.03:25:04.24#ibcon#*mode == 0, iclass 32, count 0 2006.286.03:25:04.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.03:25:04.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.03:25:04.24#ibcon#*before write, iclass 32, count 0 2006.286.03:25:04.24#ibcon#enter sib2, iclass 32, count 0 2006.286.03:25:04.24#ibcon#flushed, iclass 32, count 0 2006.286.03:25:04.24#ibcon#about to write, iclass 32, count 0 2006.286.03:25:04.24#ibcon#wrote, iclass 32, count 0 2006.286.03:25:04.24#ibcon#about to read 3, iclass 32, count 0 2006.286.03:25:04.28#ibcon#read 3, iclass 32, count 0 2006.286.03:25:04.28#ibcon#about to read 4, iclass 32, count 0 2006.286.03:25:04.28#ibcon#read 4, iclass 32, count 0 2006.286.03:25:04.28#ibcon#about to read 5, iclass 32, count 0 2006.286.03:25:04.28#ibcon#read 5, iclass 32, count 0 2006.286.03:25:04.28#ibcon#about to read 6, iclass 32, count 0 2006.286.03:25:04.28#ibcon#read 6, iclass 32, count 0 2006.286.03:25:04.28#ibcon#end of sib2, iclass 32, count 0 2006.286.03:25:04.28#ibcon#*after write, iclass 32, count 0 2006.286.03:25:04.28#ibcon#*before return 0, iclass 32, count 0 2006.286.03:25:04.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:25:04.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:25:04.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.03:25:04.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.03:25:04.28$vck44/vb=2,5 2006.286.03:25:04.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.03:25:04.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.03:25:04.28#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:04.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:25:04.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:25:04.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:25:04.34#ibcon#enter wrdev, iclass 34, count 2 2006.286.03:25:04.34#ibcon#first serial, iclass 34, count 2 2006.286.03:25:04.34#ibcon#enter sib2, iclass 34, count 2 2006.286.03:25:04.34#ibcon#flushed, iclass 34, count 2 2006.286.03:25:04.34#ibcon#about to write, iclass 34, count 2 2006.286.03:25:04.34#ibcon#wrote, iclass 34, count 2 2006.286.03:25:04.34#ibcon#about to read 3, iclass 34, count 2 2006.286.03:25:04.36#ibcon#read 3, iclass 34, count 2 2006.286.03:25:04.36#ibcon#about to read 4, iclass 34, count 2 2006.286.03:25:04.36#ibcon#read 4, iclass 34, count 2 2006.286.03:25:04.36#ibcon#about to read 5, iclass 34, count 2 2006.286.03:25:04.36#ibcon#read 5, iclass 34, count 2 2006.286.03:25:04.36#ibcon#about to read 6, iclass 34, count 2 2006.286.03:25:04.36#ibcon#read 6, iclass 34, count 2 2006.286.03:25:04.36#ibcon#end of sib2, iclass 34, count 2 2006.286.03:25:04.36#ibcon#*mode == 0, iclass 34, count 2 2006.286.03:25:04.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.03:25:04.36#ibcon#[27=AT02-05\r\n] 2006.286.03:25:04.36#ibcon#*before write, iclass 34, count 2 2006.286.03:25:04.36#ibcon#enter sib2, iclass 34, count 2 2006.286.03:25:04.36#ibcon#flushed, iclass 34, count 2 2006.286.03:25:04.36#ibcon#about to write, iclass 34, count 2 2006.286.03:25:04.36#ibcon#wrote, iclass 34, count 2 2006.286.03:25:04.36#ibcon#about to read 3, iclass 34, count 2 2006.286.03:25:04.39#ibcon#read 3, iclass 34, count 2 2006.286.03:25:04.39#ibcon#about to read 4, iclass 34, count 2 2006.286.03:25:04.39#ibcon#read 4, iclass 34, count 2 2006.286.03:25:04.39#ibcon#about to read 5, iclass 34, count 2 2006.286.03:25:04.39#ibcon#read 5, iclass 34, count 2 2006.286.03:25:04.39#ibcon#about to read 6, iclass 34, count 2 2006.286.03:25:04.39#ibcon#read 6, iclass 34, count 2 2006.286.03:25:04.39#ibcon#end of sib2, iclass 34, count 2 2006.286.03:25:04.39#ibcon#*after write, iclass 34, count 2 2006.286.03:25:04.39#ibcon#*before return 0, iclass 34, count 2 2006.286.03:25:04.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:25:04.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:25:04.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.03:25:04.39#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:04.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:25:04.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:25:04.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:25:04.51#ibcon#enter wrdev, iclass 34, count 0 2006.286.03:25:04.51#ibcon#first serial, iclass 34, count 0 2006.286.03:25:04.51#ibcon#enter sib2, iclass 34, count 0 2006.286.03:25:04.51#ibcon#flushed, iclass 34, count 0 2006.286.03:25:04.51#ibcon#about to write, iclass 34, count 0 2006.286.03:25:04.51#ibcon#wrote, iclass 34, count 0 2006.286.03:25:04.51#ibcon#about to read 3, iclass 34, count 0 2006.286.03:25:04.53#ibcon#read 3, iclass 34, count 0 2006.286.03:25:04.53#ibcon#about to read 4, iclass 34, count 0 2006.286.03:25:04.53#ibcon#read 4, iclass 34, count 0 2006.286.03:25:04.53#ibcon#about to read 5, iclass 34, count 0 2006.286.03:25:04.53#ibcon#read 5, iclass 34, count 0 2006.286.03:25:04.53#ibcon#about to read 6, iclass 34, count 0 2006.286.03:25:04.53#ibcon#read 6, iclass 34, count 0 2006.286.03:25:04.53#ibcon#end of sib2, iclass 34, count 0 2006.286.03:25:04.53#ibcon#*mode == 0, iclass 34, count 0 2006.286.03:25:04.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.03:25:04.53#ibcon#[27=USB\r\n] 2006.286.03:25:04.53#ibcon#*before write, iclass 34, count 0 2006.286.03:25:04.53#ibcon#enter sib2, iclass 34, count 0 2006.286.03:25:04.53#ibcon#flushed, iclass 34, count 0 2006.286.03:25:04.53#ibcon#about to write, iclass 34, count 0 2006.286.03:25:04.53#ibcon#wrote, iclass 34, count 0 2006.286.03:25:04.53#ibcon#about to read 3, iclass 34, count 0 2006.286.03:25:04.56#ibcon#read 3, iclass 34, count 0 2006.286.03:25:04.56#ibcon#about to read 4, iclass 34, count 0 2006.286.03:25:04.56#ibcon#read 4, iclass 34, count 0 2006.286.03:25:04.56#ibcon#about to read 5, iclass 34, count 0 2006.286.03:25:04.56#ibcon#read 5, iclass 34, count 0 2006.286.03:25:04.56#ibcon#about to read 6, iclass 34, count 0 2006.286.03:25:04.56#ibcon#read 6, iclass 34, count 0 2006.286.03:25:04.56#ibcon#end of sib2, iclass 34, count 0 2006.286.03:25:04.56#ibcon#*after write, iclass 34, count 0 2006.286.03:25:04.56#ibcon#*before return 0, iclass 34, count 0 2006.286.03:25:04.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:25:04.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:25:04.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.03:25:04.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.03:25:04.56$vck44/vblo=3,649.99 2006.286.03:25:04.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.03:25:04.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.03:25:04.56#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:04.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:25:04.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:25:04.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:25:04.56#ibcon#enter wrdev, iclass 36, count 0 2006.286.03:25:04.56#ibcon#first serial, iclass 36, count 0 2006.286.03:25:04.56#ibcon#enter sib2, iclass 36, count 0 2006.286.03:25:04.56#ibcon#flushed, iclass 36, count 0 2006.286.03:25:04.56#ibcon#about to write, iclass 36, count 0 2006.286.03:25:04.56#ibcon#wrote, iclass 36, count 0 2006.286.03:25:04.56#ibcon#about to read 3, iclass 36, count 0 2006.286.03:25:04.58#ibcon#read 3, iclass 36, count 0 2006.286.03:25:04.58#ibcon#about to read 4, iclass 36, count 0 2006.286.03:25:04.58#ibcon#read 4, iclass 36, count 0 2006.286.03:25:04.58#ibcon#about to read 5, iclass 36, count 0 2006.286.03:25:04.58#ibcon#read 5, iclass 36, count 0 2006.286.03:25:04.58#ibcon#about to read 6, iclass 36, count 0 2006.286.03:25:04.58#ibcon#read 6, iclass 36, count 0 2006.286.03:25:04.58#ibcon#end of sib2, iclass 36, count 0 2006.286.03:25:04.58#ibcon#*mode == 0, iclass 36, count 0 2006.286.03:25:04.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.03:25:04.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.03:25:04.58#ibcon#*before write, iclass 36, count 0 2006.286.03:25:04.58#ibcon#enter sib2, iclass 36, count 0 2006.286.03:25:04.58#ibcon#flushed, iclass 36, count 0 2006.286.03:25:04.58#ibcon#about to write, iclass 36, count 0 2006.286.03:25:04.58#ibcon#wrote, iclass 36, count 0 2006.286.03:25:04.58#ibcon#about to read 3, iclass 36, count 0 2006.286.03:25:04.62#ibcon#read 3, iclass 36, count 0 2006.286.03:25:04.62#ibcon#about to read 4, iclass 36, count 0 2006.286.03:25:04.62#ibcon#read 4, iclass 36, count 0 2006.286.03:25:04.62#ibcon#about to read 5, iclass 36, count 0 2006.286.03:25:04.62#ibcon#read 5, iclass 36, count 0 2006.286.03:25:04.62#ibcon#about to read 6, iclass 36, count 0 2006.286.03:25:04.62#ibcon#read 6, iclass 36, count 0 2006.286.03:25:04.62#ibcon#end of sib2, iclass 36, count 0 2006.286.03:25:04.62#ibcon#*after write, iclass 36, count 0 2006.286.03:25:04.62#ibcon#*before return 0, iclass 36, count 0 2006.286.03:25:04.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:25:04.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:25:04.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.03:25:04.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.03:25:04.62$vck44/vb=3,4 2006.286.03:25:04.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.03:25:04.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.03:25:04.62#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:04.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:25:04.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:25:04.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:25:04.68#ibcon#enter wrdev, iclass 38, count 2 2006.286.03:25:04.68#ibcon#first serial, iclass 38, count 2 2006.286.03:25:04.68#ibcon#enter sib2, iclass 38, count 2 2006.286.03:25:04.68#ibcon#flushed, iclass 38, count 2 2006.286.03:25:04.68#ibcon#about to write, iclass 38, count 2 2006.286.03:25:04.68#ibcon#wrote, iclass 38, count 2 2006.286.03:25:04.68#ibcon#about to read 3, iclass 38, count 2 2006.286.03:25:04.70#ibcon#read 3, iclass 38, count 2 2006.286.03:25:04.70#ibcon#about to read 4, iclass 38, count 2 2006.286.03:25:04.70#ibcon#read 4, iclass 38, count 2 2006.286.03:25:04.70#ibcon#about to read 5, iclass 38, count 2 2006.286.03:25:04.70#ibcon#read 5, iclass 38, count 2 2006.286.03:25:04.70#ibcon#about to read 6, iclass 38, count 2 2006.286.03:25:04.70#ibcon#read 6, iclass 38, count 2 2006.286.03:25:04.70#ibcon#end of sib2, iclass 38, count 2 2006.286.03:25:04.70#ibcon#*mode == 0, iclass 38, count 2 2006.286.03:25:04.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.03:25:04.70#ibcon#[27=AT03-04\r\n] 2006.286.03:25:04.70#ibcon#*before write, iclass 38, count 2 2006.286.03:25:04.70#ibcon#enter sib2, iclass 38, count 2 2006.286.03:25:04.70#ibcon#flushed, iclass 38, count 2 2006.286.03:25:04.70#ibcon#about to write, iclass 38, count 2 2006.286.03:25:04.70#ibcon#wrote, iclass 38, count 2 2006.286.03:25:04.70#ibcon#about to read 3, iclass 38, count 2 2006.286.03:25:04.73#ibcon#read 3, iclass 38, count 2 2006.286.03:25:04.73#ibcon#about to read 4, iclass 38, count 2 2006.286.03:25:04.73#ibcon#read 4, iclass 38, count 2 2006.286.03:25:04.73#ibcon#about to read 5, iclass 38, count 2 2006.286.03:25:04.73#ibcon#read 5, iclass 38, count 2 2006.286.03:25:04.73#ibcon#about to read 6, iclass 38, count 2 2006.286.03:25:04.73#ibcon#read 6, iclass 38, count 2 2006.286.03:25:04.73#ibcon#end of sib2, iclass 38, count 2 2006.286.03:25:04.73#ibcon#*after write, iclass 38, count 2 2006.286.03:25:04.73#ibcon#*before return 0, iclass 38, count 2 2006.286.03:25:04.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:25:04.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:25:04.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.03:25:04.73#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:04.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:25:04.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:25:04.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:25:04.85#ibcon#enter wrdev, iclass 38, count 0 2006.286.03:25:04.85#ibcon#first serial, iclass 38, count 0 2006.286.03:25:04.85#ibcon#enter sib2, iclass 38, count 0 2006.286.03:25:04.85#ibcon#flushed, iclass 38, count 0 2006.286.03:25:04.85#ibcon#about to write, iclass 38, count 0 2006.286.03:25:04.85#ibcon#wrote, iclass 38, count 0 2006.286.03:25:04.85#ibcon#about to read 3, iclass 38, count 0 2006.286.03:25:04.87#ibcon#read 3, iclass 38, count 0 2006.286.03:25:04.87#ibcon#about to read 4, iclass 38, count 0 2006.286.03:25:04.87#ibcon#read 4, iclass 38, count 0 2006.286.03:25:04.87#ibcon#about to read 5, iclass 38, count 0 2006.286.03:25:04.87#ibcon#read 5, iclass 38, count 0 2006.286.03:25:04.87#ibcon#about to read 6, iclass 38, count 0 2006.286.03:25:04.87#ibcon#read 6, iclass 38, count 0 2006.286.03:25:04.87#ibcon#end of sib2, iclass 38, count 0 2006.286.03:25:04.87#ibcon#*mode == 0, iclass 38, count 0 2006.286.03:25:04.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.03:25:04.87#ibcon#[27=USB\r\n] 2006.286.03:25:04.87#ibcon#*before write, iclass 38, count 0 2006.286.03:25:04.87#ibcon#enter sib2, iclass 38, count 0 2006.286.03:25:04.87#ibcon#flushed, iclass 38, count 0 2006.286.03:25:04.87#ibcon#about to write, iclass 38, count 0 2006.286.03:25:04.87#ibcon#wrote, iclass 38, count 0 2006.286.03:25:04.87#ibcon#about to read 3, iclass 38, count 0 2006.286.03:25:04.90#ibcon#read 3, iclass 38, count 0 2006.286.03:25:04.90#ibcon#about to read 4, iclass 38, count 0 2006.286.03:25:04.90#ibcon#read 4, iclass 38, count 0 2006.286.03:25:04.90#ibcon#about to read 5, iclass 38, count 0 2006.286.03:25:04.90#ibcon#read 5, iclass 38, count 0 2006.286.03:25:04.90#ibcon#about to read 6, iclass 38, count 0 2006.286.03:25:04.90#ibcon#read 6, iclass 38, count 0 2006.286.03:25:04.90#ibcon#end of sib2, iclass 38, count 0 2006.286.03:25:04.90#ibcon#*after write, iclass 38, count 0 2006.286.03:25:04.90#ibcon#*before return 0, iclass 38, count 0 2006.286.03:25:04.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:25:04.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:25:04.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.03:25:04.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.03:25:04.90$vck44/vblo=4,679.99 2006.286.03:25:04.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.03:25:04.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.03:25:04.90#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:04.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:25:04.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:25:04.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:25:04.90#ibcon#enter wrdev, iclass 40, count 0 2006.286.03:25:04.90#ibcon#first serial, iclass 40, count 0 2006.286.03:25:04.90#ibcon#enter sib2, iclass 40, count 0 2006.286.03:25:04.90#ibcon#flushed, iclass 40, count 0 2006.286.03:25:04.90#ibcon#about to write, iclass 40, count 0 2006.286.03:25:04.90#ibcon#wrote, iclass 40, count 0 2006.286.03:25:04.90#ibcon#about to read 3, iclass 40, count 0 2006.286.03:25:04.92#ibcon#read 3, iclass 40, count 0 2006.286.03:25:04.92#ibcon#about to read 4, iclass 40, count 0 2006.286.03:25:04.92#ibcon#read 4, iclass 40, count 0 2006.286.03:25:04.92#ibcon#about to read 5, iclass 40, count 0 2006.286.03:25:04.92#ibcon#read 5, iclass 40, count 0 2006.286.03:25:04.92#ibcon#about to read 6, iclass 40, count 0 2006.286.03:25:04.92#ibcon#read 6, iclass 40, count 0 2006.286.03:25:04.92#ibcon#end of sib2, iclass 40, count 0 2006.286.03:25:04.92#ibcon#*mode == 0, iclass 40, count 0 2006.286.03:25:04.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.03:25:04.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.03:25:04.92#ibcon#*before write, iclass 40, count 0 2006.286.03:25:04.92#ibcon#enter sib2, iclass 40, count 0 2006.286.03:25:04.92#ibcon#flushed, iclass 40, count 0 2006.286.03:25:04.92#ibcon#about to write, iclass 40, count 0 2006.286.03:25:04.92#ibcon#wrote, iclass 40, count 0 2006.286.03:25:04.92#ibcon#about to read 3, iclass 40, count 0 2006.286.03:25:04.96#ibcon#read 3, iclass 40, count 0 2006.286.03:25:04.96#ibcon#about to read 4, iclass 40, count 0 2006.286.03:25:04.96#ibcon#read 4, iclass 40, count 0 2006.286.03:25:04.96#ibcon#about to read 5, iclass 40, count 0 2006.286.03:25:04.96#ibcon#read 5, iclass 40, count 0 2006.286.03:25:04.96#ibcon#about to read 6, iclass 40, count 0 2006.286.03:25:04.96#ibcon#read 6, iclass 40, count 0 2006.286.03:25:04.96#ibcon#end of sib2, iclass 40, count 0 2006.286.03:25:04.96#ibcon#*after write, iclass 40, count 0 2006.286.03:25:04.96#ibcon#*before return 0, iclass 40, count 0 2006.286.03:25:04.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:25:04.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:25:04.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.03:25:04.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.03:25:04.96$vck44/vb=4,5 2006.286.03:25:04.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.03:25:04.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.03:25:04.96#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:04.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:25:05.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:25:05.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:25:05.02#ibcon#enter wrdev, iclass 4, count 2 2006.286.03:25:05.02#ibcon#first serial, iclass 4, count 2 2006.286.03:25:05.02#ibcon#enter sib2, iclass 4, count 2 2006.286.03:25:05.02#ibcon#flushed, iclass 4, count 2 2006.286.03:25:05.02#ibcon#about to write, iclass 4, count 2 2006.286.03:25:05.02#ibcon#wrote, iclass 4, count 2 2006.286.03:25:05.02#ibcon#about to read 3, iclass 4, count 2 2006.286.03:25:05.04#ibcon#read 3, iclass 4, count 2 2006.286.03:25:05.04#ibcon#about to read 4, iclass 4, count 2 2006.286.03:25:05.04#ibcon#read 4, iclass 4, count 2 2006.286.03:25:05.04#ibcon#about to read 5, iclass 4, count 2 2006.286.03:25:05.04#ibcon#read 5, iclass 4, count 2 2006.286.03:25:05.04#ibcon#about to read 6, iclass 4, count 2 2006.286.03:25:05.04#ibcon#read 6, iclass 4, count 2 2006.286.03:25:05.04#ibcon#end of sib2, iclass 4, count 2 2006.286.03:25:05.04#ibcon#*mode == 0, iclass 4, count 2 2006.286.03:25:05.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.03:25:05.04#ibcon#[27=AT04-05\r\n] 2006.286.03:25:05.04#ibcon#*before write, iclass 4, count 2 2006.286.03:25:05.04#ibcon#enter sib2, iclass 4, count 2 2006.286.03:25:05.04#ibcon#flushed, iclass 4, count 2 2006.286.03:25:05.04#ibcon#about to write, iclass 4, count 2 2006.286.03:25:05.04#ibcon#wrote, iclass 4, count 2 2006.286.03:25:05.04#ibcon#about to read 3, iclass 4, count 2 2006.286.03:25:05.07#ibcon#read 3, iclass 4, count 2 2006.286.03:25:05.07#ibcon#about to read 4, iclass 4, count 2 2006.286.03:25:05.07#ibcon#read 4, iclass 4, count 2 2006.286.03:25:05.07#ibcon#about to read 5, iclass 4, count 2 2006.286.03:25:05.07#ibcon#read 5, iclass 4, count 2 2006.286.03:25:05.07#ibcon#about to read 6, iclass 4, count 2 2006.286.03:25:05.07#ibcon#read 6, iclass 4, count 2 2006.286.03:25:05.07#ibcon#end of sib2, iclass 4, count 2 2006.286.03:25:05.07#ibcon#*after write, iclass 4, count 2 2006.286.03:25:05.07#ibcon#*before return 0, iclass 4, count 2 2006.286.03:25:05.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:25:05.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:25:05.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.03:25:05.07#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:05.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:25:05.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:25:05.32#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:25:05.32#ibcon#enter wrdev, iclass 4, count 0 2006.286.03:25:05.32#ibcon#first serial, iclass 4, count 0 2006.286.03:25:05.32#ibcon#enter sib2, iclass 4, count 0 2006.286.03:25:05.32#ibcon#flushed, iclass 4, count 0 2006.286.03:25:05.32#ibcon#about to write, iclass 4, count 0 2006.286.03:25:05.32#ibcon#wrote, iclass 4, count 0 2006.286.03:25:05.32#ibcon#about to read 3, iclass 4, count 0 2006.286.03:25:05.33#ibcon#read 3, iclass 4, count 0 2006.286.03:25:05.33#ibcon#about to read 4, iclass 4, count 0 2006.286.03:25:05.33#ibcon#read 4, iclass 4, count 0 2006.286.03:25:05.33#ibcon#about to read 5, iclass 4, count 0 2006.286.03:25:05.33#ibcon#read 5, iclass 4, count 0 2006.286.03:25:05.33#ibcon#about to read 6, iclass 4, count 0 2006.286.03:25:05.33#ibcon#read 6, iclass 4, count 0 2006.286.03:25:05.33#ibcon#end of sib2, iclass 4, count 0 2006.286.03:25:05.33#ibcon#*mode == 0, iclass 4, count 0 2006.286.03:25:05.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.03:25:05.33#ibcon#[27=USB\r\n] 2006.286.03:25:05.33#ibcon#*before write, iclass 4, count 0 2006.286.03:25:05.33#ibcon#enter sib2, iclass 4, count 0 2006.286.03:25:05.33#ibcon#flushed, iclass 4, count 0 2006.286.03:25:05.33#ibcon#about to write, iclass 4, count 0 2006.286.03:25:05.33#ibcon#wrote, iclass 4, count 0 2006.286.03:25:05.33#ibcon#about to read 3, iclass 4, count 0 2006.286.03:25:05.36#ibcon#read 3, iclass 4, count 0 2006.286.03:25:05.36#ibcon#about to read 4, iclass 4, count 0 2006.286.03:25:05.36#ibcon#read 4, iclass 4, count 0 2006.286.03:25:05.36#ibcon#about to read 5, iclass 4, count 0 2006.286.03:25:05.36#ibcon#read 5, iclass 4, count 0 2006.286.03:25:05.36#ibcon#about to read 6, iclass 4, count 0 2006.286.03:25:05.36#ibcon#read 6, iclass 4, count 0 2006.286.03:25:05.36#ibcon#end of sib2, iclass 4, count 0 2006.286.03:25:05.36#ibcon#*after write, iclass 4, count 0 2006.286.03:25:05.36#ibcon#*before return 0, iclass 4, count 0 2006.286.03:25:05.36#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:25:05.36#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:25:05.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.03:25:05.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.03:25:05.36$vck44/vblo=5,709.99 2006.286.03:25:05.36#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.03:25:05.36#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.03:25:05.36#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:05.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:25:05.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:25:05.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:25:05.36#ibcon#enter wrdev, iclass 6, count 0 2006.286.03:25:05.36#ibcon#first serial, iclass 6, count 0 2006.286.03:25:05.36#ibcon#enter sib2, iclass 6, count 0 2006.286.03:25:05.36#ibcon#flushed, iclass 6, count 0 2006.286.03:25:05.36#ibcon#about to write, iclass 6, count 0 2006.286.03:25:05.36#ibcon#wrote, iclass 6, count 0 2006.286.03:25:05.36#ibcon#about to read 3, iclass 6, count 0 2006.286.03:25:05.38#ibcon#read 3, iclass 6, count 0 2006.286.03:25:05.38#ibcon#about to read 4, iclass 6, count 0 2006.286.03:25:05.38#ibcon#read 4, iclass 6, count 0 2006.286.03:25:05.38#ibcon#about to read 5, iclass 6, count 0 2006.286.03:25:05.38#ibcon#read 5, iclass 6, count 0 2006.286.03:25:05.38#ibcon#about to read 6, iclass 6, count 0 2006.286.03:25:05.38#ibcon#read 6, iclass 6, count 0 2006.286.03:25:05.38#ibcon#end of sib2, iclass 6, count 0 2006.286.03:25:05.38#ibcon#*mode == 0, iclass 6, count 0 2006.286.03:25:05.38#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.03:25:05.38#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.03:25:05.38#ibcon#*before write, iclass 6, count 0 2006.286.03:25:05.38#ibcon#enter sib2, iclass 6, count 0 2006.286.03:25:05.38#ibcon#flushed, iclass 6, count 0 2006.286.03:25:05.38#ibcon#about to write, iclass 6, count 0 2006.286.03:25:05.38#ibcon#wrote, iclass 6, count 0 2006.286.03:25:05.38#ibcon#about to read 3, iclass 6, count 0 2006.286.03:25:05.42#ibcon#read 3, iclass 6, count 0 2006.286.03:25:05.42#ibcon#about to read 4, iclass 6, count 0 2006.286.03:25:05.42#ibcon#read 4, iclass 6, count 0 2006.286.03:25:05.42#ibcon#about to read 5, iclass 6, count 0 2006.286.03:25:05.42#ibcon#read 5, iclass 6, count 0 2006.286.03:25:05.42#ibcon#about to read 6, iclass 6, count 0 2006.286.03:25:05.42#ibcon#read 6, iclass 6, count 0 2006.286.03:25:05.42#ibcon#end of sib2, iclass 6, count 0 2006.286.03:25:05.42#ibcon#*after write, iclass 6, count 0 2006.286.03:25:05.42#ibcon#*before return 0, iclass 6, count 0 2006.286.03:25:05.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:25:05.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:25:05.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.03:25:05.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.03:25:05.42$vck44/vb=5,4 2006.286.03:25:05.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.03:25:05.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.03:25:05.42#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:05.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:25:05.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:25:05.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:25:05.48#ibcon#enter wrdev, iclass 10, count 2 2006.286.03:25:05.48#ibcon#first serial, iclass 10, count 2 2006.286.03:25:05.48#ibcon#enter sib2, iclass 10, count 2 2006.286.03:25:05.48#ibcon#flushed, iclass 10, count 2 2006.286.03:25:05.48#ibcon#about to write, iclass 10, count 2 2006.286.03:25:05.48#ibcon#wrote, iclass 10, count 2 2006.286.03:25:05.48#ibcon#about to read 3, iclass 10, count 2 2006.286.03:25:05.50#ibcon#read 3, iclass 10, count 2 2006.286.03:25:05.50#ibcon#about to read 4, iclass 10, count 2 2006.286.03:25:05.50#ibcon#read 4, iclass 10, count 2 2006.286.03:25:05.50#ibcon#about to read 5, iclass 10, count 2 2006.286.03:25:05.50#ibcon#read 5, iclass 10, count 2 2006.286.03:25:05.50#ibcon#about to read 6, iclass 10, count 2 2006.286.03:25:05.50#ibcon#read 6, iclass 10, count 2 2006.286.03:25:05.50#ibcon#end of sib2, iclass 10, count 2 2006.286.03:25:05.50#ibcon#*mode == 0, iclass 10, count 2 2006.286.03:25:05.50#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.03:25:05.50#ibcon#[27=AT05-04\r\n] 2006.286.03:25:05.50#ibcon#*before write, iclass 10, count 2 2006.286.03:25:05.50#ibcon#enter sib2, iclass 10, count 2 2006.286.03:25:05.50#ibcon#flushed, iclass 10, count 2 2006.286.03:25:05.50#ibcon#about to write, iclass 10, count 2 2006.286.03:25:05.50#ibcon#wrote, iclass 10, count 2 2006.286.03:25:05.50#ibcon#about to read 3, iclass 10, count 2 2006.286.03:25:05.53#ibcon#read 3, iclass 10, count 2 2006.286.03:25:05.53#ibcon#about to read 4, iclass 10, count 2 2006.286.03:25:05.53#ibcon#read 4, iclass 10, count 2 2006.286.03:25:05.53#ibcon#about to read 5, iclass 10, count 2 2006.286.03:25:05.53#ibcon#read 5, iclass 10, count 2 2006.286.03:25:05.53#ibcon#about to read 6, iclass 10, count 2 2006.286.03:25:05.53#ibcon#read 6, iclass 10, count 2 2006.286.03:25:05.53#ibcon#end of sib2, iclass 10, count 2 2006.286.03:25:05.53#ibcon#*after write, iclass 10, count 2 2006.286.03:25:05.53#ibcon#*before return 0, iclass 10, count 2 2006.286.03:25:05.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:25:05.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:25:05.53#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.03:25:05.53#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:05.53#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:25:05.65#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:25:05.65#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:25:05.65#ibcon#enter wrdev, iclass 10, count 0 2006.286.03:25:05.65#ibcon#first serial, iclass 10, count 0 2006.286.03:25:05.65#ibcon#enter sib2, iclass 10, count 0 2006.286.03:25:05.65#ibcon#flushed, iclass 10, count 0 2006.286.03:25:05.65#ibcon#about to write, iclass 10, count 0 2006.286.03:25:05.65#ibcon#wrote, iclass 10, count 0 2006.286.03:25:05.65#ibcon#about to read 3, iclass 10, count 0 2006.286.03:25:05.67#ibcon#read 3, iclass 10, count 0 2006.286.03:25:05.67#ibcon#about to read 4, iclass 10, count 0 2006.286.03:25:05.67#ibcon#read 4, iclass 10, count 0 2006.286.03:25:05.67#ibcon#about to read 5, iclass 10, count 0 2006.286.03:25:05.67#ibcon#read 5, iclass 10, count 0 2006.286.03:25:05.67#ibcon#about to read 6, iclass 10, count 0 2006.286.03:25:05.67#ibcon#read 6, iclass 10, count 0 2006.286.03:25:05.67#ibcon#end of sib2, iclass 10, count 0 2006.286.03:25:05.67#ibcon#*mode == 0, iclass 10, count 0 2006.286.03:25:05.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.03:25:05.67#ibcon#[27=USB\r\n] 2006.286.03:25:05.67#ibcon#*before write, iclass 10, count 0 2006.286.03:25:05.67#ibcon#enter sib2, iclass 10, count 0 2006.286.03:25:05.67#ibcon#flushed, iclass 10, count 0 2006.286.03:25:05.67#ibcon#about to write, iclass 10, count 0 2006.286.03:25:05.67#ibcon#wrote, iclass 10, count 0 2006.286.03:25:05.67#ibcon#about to read 3, iclass 10, count 0 2006.286.03:25:05.70#ibcon#read 3, iclass 10, count 0 2006.286.03:25:05.70#ibcon#about to read 4, iclass 10, count 0 2006.286.03:25:05.70#ibcon#read 4, iclass 10, count 0 2006.286.03:25:05.70#ibcon#about to read 5, iclass 10, count 0 2006.286.03:25:05.70#ibcon#read 5, iclass 10, count 0 2006.286.03:25:05.70#ibcon#about to read 6, iclass 10, count 0 2006.286.03:25:05.70#ibcon#read 6, iclass 10, count 0 2006.286.03:25:05.70#ibcon#end of sib2, iclass 10, count 0 2006.286.03:25:05.70#ibcon#*after write, iclass 10, count 0 2006.286.03:25:05.70#ibcon#*before return 0, iclass 10, count 0 2006.286.03:25:05.70#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:25:05.70#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:25:05.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.03:25:05.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.03:25:05.70$vck44/vblo=6,719.99 2006.286.03:25:05.70#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.03:25:05.70#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.03:25:05.70#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:05.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:25:05.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:25:05.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:25:05.70#ibcon#enter wrdev, iclass 12, count 0 2006.286.03:25:05.70#ibcon#first serial, iclass 12, count 0 2006.286.03:25:05.70#ibcon#enter sib2, iclass 12, count 0 2006.286.03:25:05.70#ibcon#flushed, iclass 12, count 0 2006.286.03:25:05.70#ibcon#about to write, iclass 12, count 0 2006.286.03:25:05.70#ibcon#wrote, iclass 12, count 0 2006.286.03:25:05.70#ibcon#about to read 3, iclass 12, count 0 2006.286.03:25:05.72#ibcon#read 3, iclass 12, count 0 2006.286.03:25:05.72#ibcon#about to read 4, iclass 12, count 0 2006.286.03:25:05.72#ibcon#read 4, iclass 12, count 0 2006.286.03:25:05.72#ibcon#about to read 5, iclass 12, count 0 2006.286.03:25:05.72#ibcon#read 5, iclass 12, count 0 2006.286.03:25:05.72#ibcon#about to read 6, iclass 12, count 0 2006.286.03:25:05.72#ibcon#read 6, iclass 12, count 0 2006.286.03:25:05.72#ibcon#end of sib2, iclass 12, count 0 2006.286.03:25:05.72#ibcon#*mode == 0, iclass 12, count 0 2006.286.03:25:05.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.03:25:05.72#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.03:25:05.72#ibcon#*before write, iclass 12, count 0 2006.286.03:25:05.72#ibcon#enter sib2, iclass 12, count 0 2006.286.03:25:05.72#ibcon#flushed, iclass 12, count 0 2006.286.03:25:05.72#ibcon#about to write, iclass 12, count 0 2006.286.03:25:05.72#ibcon#wrote, iclass 12, count 0 2006.286.03:25:05.72#ibcon#about to read 3, iclass 12, count 0 2006.286.03:25:05.76#ibcon#read 3, iclass 12, count 0 2006.286.03:25:05.76#ibcon#about to read 4, iclass 12, count 0 2006.286.03:25:05.76#ibcon#read 4, iclass 12, count 0 2006.286.03:25:05.76#ibcon#about to read 5, iclass 12, count 0 2006.286.03:25:05.76#ibcon#read 5, iclass 12, count 0 2006.286.03:25:05.76#ibcon#about to read 6, iclass 12, count 0 2006.286.03:25:05.76#ibcon#read 6, iclass 12, count 0 2006.286.03:25:05.76#ibcon#end of sib2, iclass 12, count 0 2006.286.03:25:05.76#ibcon#*after write, iclass 12, count 0 2006.286.03:25:05.76#ibcon#*before return 0, iclass 12, count 0 2006.286.03:25:05.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:25:05.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:25:05.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.03:25:05.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.03:25:05.76$vck44/vb=6,3 2006.286.03:25:05.76#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.03:25:05.76#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.03:25:05.76#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:05.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:25:05.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:25:05.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:25:05.82#ibcon#enter wrdev, iclass 14, count 2 2006.286.03:25:05.82#ibcon#first serial, iclass 14, count 2 2006.286.03:25:05.82#ibcon#enter sib2, iclass 14, count 2 2006.286.03:25:05.82#ibcon#flushed, iclass 14, count 2 2006.286.03:25:05.82#ibcon#about to write, iclass 14, count 2 2006.286.03:25:05.82#ibcon#wrote, iclass 14, count 2 2006.286.03:25:05.82#ibcon#about to read 3, iclass 14, count 2 2006.286.03:25:05.84#ibcon#read 3, iclass 14, count 2 2006.286.03:25:05.84#ibcon#about to read 4, iclass 14, count 2 2006.286.03:25:05.84#ibcon#read 4, iclass 14, count 2 2006.286.03:25:05.84#ibcon#about to read 5, iclass 14, count 2 2006.286.03:25:05.84#ibcon#read 5, iclass 14, count 2 2006.286.03:25:05.84#ibcon#about to read 6, iclass 14, count 2 2006.286.03:25:05.84#ibcon#read 6, iclass 14, count 2 2006.286.03:25:05.84#ibcon#end of sib2, iclass 14, count 2 2006.286.03:25:05.84#ibcon#*mode == 0, iclass 14, count 2 2006.286.03:25:05.84#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.03:25:05.84#ibcon#[27=AT06-03\r\n] 2006.286.03:25:05.84#ibcon#*before write, iclass 14, count 2 2006.286.03:25:05.84#ibcon#enter sib2, iclass 14, count 2 2006.286.03:25:05.84#ibcon#flushed, iclass 14, count 2 2006.286.03:25:05.84#ibcon#about to write, iclass 14, count 2 2006.286.03:25:05.84#ibcon#wrote, iclass 14, count 2 2006.286.03:25:05.84#ibcon#about to read 3, iclass 14, count 2 2006.286.03:25:05.87#ibcon#read 3, iclass 14, count 2 2006.286.03:25:05.87#ibcon#about to read 4, iclass 14, count 2 2006.286.03:25:05.87#ibcon#read 4, iclass 14, count 2 2006.286.03:25:05.87#ibcon#about to read 5, iclass 14, count 2 2006.286.03:25:05.87#ibcon#read 5, iclass 14, count 2 2006.286.03:25:05.87#ibcon#about to read 6, iclass 14, count 2 2006.286.03:25:05.87#ibcon#read 6, iclass 14, count 2 2006.286.03:25:05.87#ibcon#end of sib2, iclass 14, count 2 2006.286.03:25:05.87#ibcon#*after write, iclass 14, count 2 2006.286.03:25:05.87#ibcon#*before return 0, iclass 14, count 2 2006.286.03:25:05.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:25:05.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:25:05.87#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.03:25:05.87#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:05.87#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:25:05.99#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:25:05.99#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:25:05.99#ibcon#enter wrdev, iclass 14, count 0 2006.286.03:25:05.99#ibcon#first serial, iclass 14, count 0 2006.286.03:25:05.99#ibcon#enter sib2, iclass 14, count 0 2006.286.03:25:05.99#ibcon#flushed, iclass 14, count 0 2006.286.03:25:05.99#ibcon#about to write, iclass 14, count 0 2006.286.03:25:05.99#ibcon#wrote, iclass 14, count 0 2006.286.03:25:05.99#ibcon#about to read 3, iclass 14, count 0 2006.286.03:25:06.01#ibcon#read 3, iclass 14, count 0 2006.286.03:25:06.01#ibcon#about to read 4, iclass 14, count 0 2006.286.03:25:06.01#ibcon#read 4, iclass 14, count 0 2006.286.03:25:06.01#ibcon#about to read 5, iclass 14, count 0 2006.286.03:25:06.01#ibcon#read 5, iclass 14, count 0 2006.286.03:25:06.01#ibcon#about to read 6, iclass 14, count 0 2006.286.03:25:06.01#ibcon#read 6, iclass 14, count 0 2006.286.03:25:06.01#ibcon#end of sib2, iclass 14, count 0 2006.286.03:25:06.01#ibcon#*mode == 0, iclass 14, count 0 2006.286.03:25:06.01#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.03:25:06.01#ibcon#[27=USB\r\n] 2006.286.03:25:06.01#ibcon#*before write, iclass 14, count 0 2006.286.03:25:06.01#ibcon#enter sib2, iclass 14, count 0 2006.286.03:25:06.01#ibcon#flushed, iclass 14, count 0 2006.286.03:25:06.01#ibcon#about to write, iclass 14, count 0 2006.286.03:25:06.01#ibcon#wrote, iclass 14, count 0 2006.286.03:25:06.01#ibcon#about to read 3, iclass 14, count 0 2006.286.03:25:06.04#ibcon#read 3, iclass 14, count 0 2006.286.03:25:06.04#ibcon#about to read 4, iclass 14, count 0 2006.286.03:25:06.04#ibcon#read 4, iclass 14, count 0 2006.286.03:25:06.04#ibcon#about to read 5, iclass 14, count 0 2006.286.03:25:06.04#ibcon#read 5, iclass 14, count 0 2006.286.03:25:06.04#ibcon#about to read 6, iclass 14, count 0 2006.286.03:25:06.04#ibcon#read 6, iclass 14, count 0 2006.286.03:25:06.04#ibcon#end of sib2, iclass 14, count 0 2006.286.03:25:06.04#ibcon#*after write, iclass 14, count 0 2006.286.03:25:06.04#ibcon#*before return 0, iclass 14, count 0 2006.286.03:25:06.04#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:25:06.04#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:25:06.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.03:25:06.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.03:25:06.04$vck44/vblo=7,734.99 2006.286.03:25:06.04#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.03:25:06.04#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.03:25:06.04#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:06.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:25:06.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:25:06.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:25:06.04#ibcon#enter wrdev, iclass 16, count 0 2006.286.03:25:06.04#ibcon#first serial, iclass 16, count 0 2006.286.03:25:06.04#ibcon#enter sib2, iclass 16, count 0 2006.286.03:25:06.04#ibcon#flushed, iclass 16, count 0 2006.286.03:25:06.04#ibcon#about to write, iclass 16, count 0 2006.286.03:25:06.04#ibcon#wrote, iclass 16, count 0 2006.286.03:25:06.04#ibcon#about to read 3, iclass 16, count 0 2006.286.03:25:06.06#ibcon#read 3, iclass 16, count 0 2006.286.03:25:06.15#ibcon#about to read 4, iclass 16, count 0 2006.286.03:25:06.15#ibcon#read 4, iclass 16, count 0 2006.286.03:25:06.15#ibcon#about to read 5, iclass 16, count 0 2006.286.03:25:06.15#ibcon#read 5, iclass 16, count 0 2006.286.03:25:06.15#ibcon#about to read 6, iclass 16, count 0 2006.286.03:25:06.15#ibcon#read 6, iclass 16, count 0 2006.286.03:25:06.15#ibcon#end of sib2, iclass 16, count 0 2006.286.03:25:06.15#ibcon#*mode == 0, iclass 16, count 0 2006.286.03:25:06.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.03:25:06.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.03:25:06.15#ibcon#*before write, iclass 16, count 0 2006.286.03:25:06.15#ibcon#enter sib2, iclass 16, count 0 2006.286.03:25:06.15#ibcon#flushed, iclass 16, count 0 2006.286.03:25:06.15#ibcon#about to write, iclass 16, count 0 2006.286.03:25:06.15#ibcon#wrote, iclass 16, count 0 2006.286.03:25:06.15#ibcon#about to read 3, iclass 16, count 0 2006.286.03:25:06.19#ibcon#read 3, iclass 16, count 0 2006.286.03:25:06.19#ibcon#about to read 4, iclass 16, count 0 2006.286.03:25:06.19#ibcon#read 4, iclass 16, count 0 2006.286.03:25:06.19#ibcon#about to read 5, iclass 16, count 0 2006.286.03:25:06.19#ibcon#read 5, iclass 16, count 0 2006.286.03:25:06.19#ibcon#about to read 6, iclass 16, count 0 2006.286.03:25:06.19#ibcon#read 6, iclass 16, count 0 2006.286.03:25:06.19#ibcon#end of sib2, iclass 16, count 0 2006.286.03:25:06.19#ibcon#*after write, iclass 16, count 0 2006.286.03:25:06.19#ibcon#*before return 0, iclass 16, count 0 2006.286.03:25:06.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:25:06.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:25:06.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.03:25:06.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.03:25:06.19$vck44/vb=7,4 2006.286.03:25:06.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.03:25:06.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.03:25:06.19#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:06.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:25:06.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:25:06.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:25:06.19#ibcon#enter wrdev, iclass 18, count 2 2006.286.03:25:06.19#ibcon#first serial, iclass 18, count 2 2006.286.03:25:06.19#ibcon#enter sib2, iclass 18, count 2 2006.286.03:25:06.19#ibcon#flushed, iclass 18, count 2 2006.286.03:25:06.19#ibcon#about to write, iclass 18, count 2 2006.286.03:25:06.19#ibcon#wrote, iclass 18, count 2 2006.286.03:25:06.19#ibcon#about to read 3, iclass 18, count 2 2006.286.03:25:06.21#ibcon#read 3, iclass 18, count 2 2006.286.03:25:06.21#ibcon#about to read 4, iclass 18, count 2 2006.286.03:25:06.21#ibcon#read 4, iclass 18, count 2 2006.286.03:25:06.21#ibcon#about to read 5, iclass 18, count 2 2006.286.03:25:06.21#ibcon#read 5, iclass 18, count 2 2006.286.03:25:06.21#ibcon#about to read 6, iclass 18, count 2 2006.286.03:25:06.21#ibcon#read 6, iclass 18, count 2 2006.286.03:25:06.21#ibcon#end of sib2, iclass 18, count 2 2006.286.03:25:06.21#ibcon#*mode == 0, iclass 18, count 2 2006.286.03:25:06.21#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.03:25:06.21#ibcon#[27=AT07-04\r\n] 2006.286.03:25:06.21#ibcon#*before write, iclass 18, count 2 2006.286.03:25:06.21#ibcon#enter sib2, iclass 18, count 2 2006.286.03:25:06.21#ibcon#flushed, iclass 18, count 2 2006.286.03:25:06.21#ibcon#about to write, iclass 18, count 2 2006.286.03:25:06.21#ibcon#wrote, iclass 18, count 2 2006.286.03:25:06.21#ibcon#about to read 3, iclass 18, count 2 2006.286.03:25:06.24#ibcon#read 3, iclass 18, count 2 2006.286.03:25:06.24#ibcon#about to read 4, iclass 18, count 2 2006.286.03:25:06.24#ibcon#read 4, iclass 18, count 2 2006.286.03:25:06.24#ibcon#about to read 5, iclass 18, count 2 2006.286.03:25:06.24#ibcon#read 5, iclass 18, count 2 2006.286.03:25:06.24#ibcon#about to read 6, iclass 18, count 2 2006.286.03:25:06.24#ibcon#read 6, iclass 18, count 2 2006.286.03:25:06.24#ibcon#end of sib2, iclass 18, count 2 2006.286.03:25:06.24#ibcon#*after write, iclass 18, count 2 2006.286.03:25:06.24#ibcon#*before return 0, iclass 18, count 2 2006.286.03:25:06.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:25:06.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:25:06.24#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.03:25:06.24#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:06.24#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:25:06.36#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:25:06.36#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:25:06.36#ibcon#enter wrdev, iclass 18, count 0 2006.286.03:25:06.36#ibcon#first serial, iclass 18, count 0 2006.286.03:25:06.36#ibcon#enter sib2, iclass 18, count 0 2006.286.03:25:06.36#ibcon#flushed, iclass 18, count 0 2006.286.03:25:06.36#ibcon#about to write, iclass 18, count 0 2006.286.03:25:06.36#ibcon#wrote, iclass 18, count 0 2006.286.03:25:06.36#ibcon#about to read 3, iclass 18, count 0 2006.286.03:25:06.38#ibcon#read 3, iclass 18, count 0 2006.286.03:25:06.38#ibcon#about to read 4, iclass 18, count 0 2006.286.03:25:06.38#ibcon#read 4, iclass 18, count 0 2006.286.03:25:06.38#ibcon#about to read 5, iclass 18, count 0 2006.286.03:25:06.38#ibcon#read 5, iclass 18, count 0 2006.286.03:25:06.38#ibcon#about to read 6, iclass 18, count 0 2006.286.03:25:06.38#ibcon#read 6, iclass 18, count 0 2006.286.03:25:06.38#ibcon#end of sib2, iclass 18, count 0 2006.286.03:25:06.38#ibcon#*mode == 0, iclass 18, count 0 2006.286.03:25:06.38#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.03:25:06.38#ibcon#[27=USB\r\n] 2006.286.03:25:06.38#ibcon#*before write, iclass 18, count 0 2006.286.03:25:06.38#ibcon#enter sib2, iclass 18, count 0 2006.286.03:25:06.38#ibcon#flushed, iclass 18, count 0 2006.286.03:25:06.38#ibcon#about to write, iclass 18, count 0 2006.286.03:25:06.38#ibcon#wrote, iclass 18, count 0 2006.286.03:25:06.38#ibcon#about to read 3, iclass 18, count 0 2006.286.03:25:06.41#ibcon#read 3, iclass 18, count 0 2006.286.03:25:06.41#ibcon#about to read 4, iclass 18, count 0 2006.286.03:25:06.41#ibcon#read 4, iclass 18, count 0 2006.286.03:25:06.41#ibcon#about to read 5, iclass 18, count 0 2006.286.03:25:06.41#ibcon#read 5, iclass 18, count 0 2006.286.03:25:06.41#ibcon#about to read 6, iclass 18, count 0 2006.286.03:25:06.41#ibcon#read 6, iclass 18, count 0 2006.286.03:25:06.41#ibcon#end of sib2, iclass 18, count 0 2006.286.03:25:06.41#ibcon#*after write, iclass 18, count 0 2006.286.03:25:06.41#ibcon#*before return 0, iclass 18, count 0 2006.286.03:25:06.41#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:25:06.41#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:25:06.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.03:25:06.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.03:25:06.41$vck44/vblo=8,744.99 2006.286.03:25:06.41#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.03:25:06.41#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.03:25:06.41#ibcon#ireg 17 cls_cnt 0 2006.286.03:25:06.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:25:06.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:25:06.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:25:06.41#ibcon#enter wrdev, iclass 20, count 0 2006.286.03:25:06.41#ibcon#first serial, iclass 20, count 0 2006.286.03:25:06.41#ibcon#enter sib2, iclass 20, count 0 2006.286.03:25:06.41#ibcon#flushed, iclass 20, count 0 2006.286.03:25:06.41#ibcon#about to write, iclass 20, count 0 2006.286.03:25:06.41#ibcon#wrote, iclass 20, count 0 2006.286.03:25:06.41#ibcon#about to read 3, iclass 20, count 0 2006.286.03:25:06.43#ibcon#read 3, iclass 20, count 0 2006.286.03:25:06.43#ibcon#about to read 4, iclass 20, count 0 2006.286.03:25:06.43#ibcon#read 4, iclass 20, count 0 2006.286.03:25:06.43#ibcon#about to read 5, iclass 20, count 0 2006.286.03:25:06.43#ibcon#read 5, iclass 20, count 0 2006.286.03:25:06.43#ibcon#about to read 6, iclass 20, count 0 2006.286.03:25:06.43#ibcon#read 6, iclass 20, count 0 2006.286.03:25:06.43#ibcon#end of sib2, iclass 20, count 0 2006.286.03:25:06.43#ibcon#*mode == 0, iclass 20, count 0 2006.286.03:25:06.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.03:25:06.43#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.03:25:06.43#ibcon#*before write, iclass 20, count 0 2006.286.03:25:06.43#ibcon#enter sib2, iclass 20, count 0 2006.286.03:25:06.43#ibcon#flushed, iclass 20, count 0 2006.286.03:25:06.43#ibcon#about to write, iclass 20, count 0 2006.286.03:25:06.43#ibcon#wrote, iclass 20, count 0 2006.286.03:25:06.43#ibcon#about to read 3, iclass 20, count 0 2006.286.03:25:06.47#ibcon#read 3, iclass 20, count 0 2006.286.03:25:06.47#ibcon#about to read 4, iclass 20, count 0 2006.286.03:25:06.47#ibcon#read 4, iclass 20, count 0 2006.286.03:25:06.47#ibcon#about to read 5, iclass 20, count 0 2006.286.03:25:06.47#ibcon#read 5, iclass 20, count 0 2006.286.03:25:06.47#ibcon#about to read 6, iclass 20, count 0 2006.286.03:25:06.47#ibcon#read 6, iclass 20, count 0 2006.286.03:25:06.47#ibcon#end of sib2, iclass 20, count 0 2006.286.03:25:06.47#ibcon#*after write, iclass 20, count 0 2006.286.03:25:06.47#ibcon#*before return 0, iclass 20, count 0 2006.286.03:25:06.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:25:06.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:25:06.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.03:25:06.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.03:25:06.47$vck44/vb=8,4 2006.286.03:25:06.47#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.03:25:06.47#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.03:25:06.47#ibcon#ireg 11 cls_cnt 2 2006.286.03:25:06.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:25:06.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:25:06.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:25:06.53#ibcon#enter wrdev, iclass 22, count 2 2006.286.03:25:06.53#ibcon#first serial, iclass 22, count 2 2006.286.03:25:06.53#ibcon#enter sib2, iclass 22, count 2 2006.286.03:25:06.53#ibcon#flushed, iclass 22, count 2 2006.286.03:25:06.53#ibcon#about to write, iclass 22, count 2 2006.286.03:25:06.53#ibcon#wrote, iclass 22, count 2 2006.286.03:25:06.53#ibcon#about to read 3, iclass 22, count 2 2006.286.03:25:06.55#ibcon#read 3, iclass 22, count 2 2006.286.03:25:06.55#ibcon#about to read 4, iclass 22, count 2 2006.286.03:25:06.55#ibcon#read 4, iclass 22, count 2 2006.286.03:25:06.55#ibcon#about to read 5, iclass 22, count 2 2006.286.03:25:06.55#ibcon#read 5, iclass 22, count 2 2006.286.03:25:06.55#ibcon#about to read 6, iclass 22, count 2 2006.286.03:25:06.55#ibcon#read 6, iclass 22, count 2 2006.286.03:25:06.55#ibcon#end of sib2, iclass 22, count 2 2006.286.03:25:06.55#ibcon#*mode == 0, iclass 22, count 2 2006.286.03:25:06.55#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.03:25:06.55#ibcon#[27=AT08-04\r\n] 2006.286.03:25:06.55#ibcon#*before write, iclass 22, count 2 2006.286.03:25:06.55#ibcon#enter sib2, iclass 22, count 2 2006.286.03:25:06.55#ibcon#flushed, iclass 22, count 2 2006.286.03:25:06.55#ibcon#about to write, iclass 22, count 2 2006.286.03:25:06.55#ibcon#wrote, iclass 22, count 2 2006.286.03:25:06.55#ibcon#about to read 3, iclass 22, count 2 2006.286.03:25:06.58#ibcon#read 3, iclass 22, count 2 2006.286.03:25:06.58#ibcon#about to read 4, iclass 22, count 2 2006.286.03:25:06.58#ibcon#read 4, iclass 22, count 2 2006.286.03:25:06.58#ibcon#about to read 5, iclass 22, count 2 2006.286.03:25:06.58#ibcon#read 5, iclass 22, count 2 2006.286.03:25:06.58#ibcon#about to read 6, iclass 22, count 2 2006.286.03:25:06.58#ibcon#read 6, iclass 22, count 2 2006.286.03:25:06.58#ibcon#end of sib2, iclass 22, count 2 2006.286.03:25:06.58#ibcon#*after write, iclass 22, count 2 2006.286.03:25:06.58#ibcon#*before return 0, iclass 22, count 2 2006.286.03:25:06.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:25:06.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:25:06.58#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.03:25:06.58#ibcon#ireg 7 cls_cnt 0 2006.286.03:25:06.58#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:25:06.70#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:25:06.70#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:25:06.70#ibcon#enter wrdev, iclass 22, count 0 2006.286.03:25:06.70#ibcon#first serial, iclass 22, count 0 2006.286.03:25:06.70#ibcon#enter sib2, iclass 22, count 0 2006.286.03:25:06.70#ibcon#flushed, iclass 22, count 0 2006.286.03:25:06.70#ibcon#about to write, iclass 22, count 0 2006.286.03:25:06.70#ibcon#wrote, iclass 22, count 0 2006.286.03:25:06.70#ibcon#about to read 3, iclass 22, count 0 2006.286.03:25:06.72#ibcon#read 3, iclass 22, count 0 2006.286.03:25:06.72#ibcon#about to read 4, iclass 22, count 0 2006.286.03:25:06.72#ibcon#read 4, iclass 22, count 0 2006.286.03:25:06.72#ibcon#about to read 5, iclass 22, count 0 2006.286.03:25:06.72#ibcon#read 5, iclass 22, count 0 2006.286.03:25:06.72#ibcon#about to read 6, iclass 22, count 0 2006.286.03:25:06.72#ibcon#read 6, iclass 22, count 0 2006.286.03:25:06.72#ibcon#end of sib2, iclass 22, count 0 2006.286.03:25:06.72#ibcon#*mode == 0, iclass 22, count 0 2006.286.03:25:06.72#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.03:25:06.72#ibcon#[27=USB\r\n] 2006.286.03:25:06.72#ibcon#*before write, iclass 22, count 0 2006.286.03:25:06.72#ibcon#enter sib2, iclass 22, count 0 2006.286.03:25:06.72#ibcon#flushed, iclass 22, count 0 2006.286.03:25:06.72#ibcon#about to write, iclass 22, count 0 2006.286.03:25:06.72#ibcon#wrote, iclass 22, count 0 2006.286.03:25:06.72#ibcon#about to read 3, iclass 22, count 0 2006.286.03:25:06.75#ibcon#read 3, iclass 22, count 0 2006.286.03:25:06.75#ibcon#about to read 4, iclass 22, count 0 2006.286.03:25:06.75#ibcon#read 4, iclass 22, count 0 2006.286.03:25:06.75#ibcon#about to read 5, iclass 22, count 0 2006.286.03:25:06.75#ibcon#read 5, iclass 22, count 0 2006.286.03:25:06.75#ibcon#about to read 6, iclass 22, count 0 2006.286.03:25:06.75#ibcon#read 6, iclass 22, count 0 2006.286.03:25:06.75#ibcon#end of sib2, iclass 22, count 0 2006.286.03:25:06.75#ibcon#*after write, iclass 22, count 0 2006.286.03:25:06.75#ibcon#*before return 0, iclass 22, count 0 2006.286.03:25:06.75#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:25:06.75#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:25:06.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.03:25:06.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.03:25:06.75$vck44/vabw=wide 2006.286.03:25:06.75#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.03:25:06.75#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.03:25:06.75#ibcon#ireg 8 cls_cnt 0 2006.286.03:25:06.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:25:06.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:25:06.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:25:06.75#ibcon#enter wrdev, iclass 24, count 0 2006.286.03:25:06.75#ibcon#first serial, iclass 24, count 0 2006.286.03:25:06.75#ibcon#enter sib2, iclass 24, count 0 2006.286.03:25:06.75#ibcon#flushed, iclass 24, count 0 2006.286.03:25:06.75#ibcon#about to write, iclass 24, count 0 2006.286.03:25:06.75#ibcon#wrote, iclass 24, count 0 2006.286.03:25:06.75#ibcon#about to read 3, iclass 24, count 0 2006.286.03:25:06.77#ibcon#read 3, iclass 24, count 0 2006.286.03:25:06.77#ibcon#about to read 4, iclass 24, count 0 2006.286.03:25:06.77#ibcon#read 4, iclass 24, count 0 2006.286.03:25:06.77#ibcon#about to read 5, iclass 24, count 0 2006.286.03:25:06.77#ibcon#read 5, iclass 24, count 0 2006.286.03:25:06.77#ibcon#about to read 6, iclass 24, count 0 2006.286.03:25:06.77#ibcon#read 6, iclass 24, count 0 2006.286.03:25:06.77#ibcon#end of sib2, iclass 24, count 0 2006.286.03:25:06.77#ibcon#*mode == 0, iclass 24, count 0 2006.286.03:25:06.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.03:25:06.77#ibcon#[25=BW32\r\n] 2006.286.03:25:06.77#ibcon#*before write, iclass 24, count 0 2006.286.03:25:06.77#ibcon#enter sib2, iclass 24, count 0 2006.286.03:25:06.77#ibcon#flushed, iclass 24, count 0 2006.286.03:25:06.77#ibcon#about to write, iclass 24, count 0 2006.286.03:25:06.77#ibcon#wrote, iclass 24, count 0 2006.286.03:25:06.77#ibcon#about to read 3, iclass 24, count 0 2006.286.03:25:06.80#ibcon#read 3, iclass 24, count 0 2006.286.03:25:06.80#ibcon#about to read 4, iclass 24, count 0 2006.286.03:25:06.80#ibcon#read 4, iclass 24, count 0 2006.286.03:25:06.80#ibcon#about to read 5, iclass 24, count 0 2006.286.03:25:06.80#ibcon#read 5, iclass 24, count 0 2006.286.03:25:06.80#ibcon#about to read 6, iclass 24, count 0 2006.286.03:25:06.80#ibcon#read 6, iclass 24, count 0 2006.286.03:25:06.80#ibcon#end of sib2, iclass 24, count 0 2006.286.03:25:06.80#ibcon#*after write, iclass 24, count 0 2006.286.03:25:06.80#ibcon#*before return 0, iclass 24, count 0 2006.286.03:25:06.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:25:06.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:25:06.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.03:25:06.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.03:25:06.80$vck44/vbbw=wide 2006.286.03:25:06.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.03:25:06.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.03:25:06.80#ibcon#ireg 8 cls_cnt 0 2006.286.03:25:06.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:25:06.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:25:06.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:25:06.87#ibcon#enter wrdev, iclass 26, count 0 2006.286.03:25:06.87#ibcon#first serial, iclass 26, count 0 2006.286.03:25:06.87#ibcon#enter sib2, iclass 26, count 0 2006.286.03:25:06.87#ibcon#flushed, iclass 26, count 0 2006.286.03:25:06.87#ibcon#about to write, iclass 26, count 0 2006.286.03:25:06.87#ibcon#wrote, iclass 26, count 0 2006.286.03:25:06.87#ibcon#about to read 3, iclass 26, count 0 2006.286.03:25:06.89#ibcon#read 3, iclass 26, count 0 2006.286.03:25:06.89#ibcon#about to read 4, iclass 26, count 0 2006.286.03:25:06.89#ibcon#read 4, iclass 26, count 0 2006.286.03:25:06.89#ibcon#about to read 5, iclass 26, count 0 2006.286.03:25:06.89#ibcon#read 5, iclass 26, count 0 2006.286.03:25:06.89#ibcon#about to read 6, iclass 26, count 0 2006.286.03:25:06.89#ibcon#read 6, iclass 26, count 0 2006.286.03:25:06.89#ibcon#end of sib2, iclass 26, count 0 2006.286.03:25:06.89#ibcon#*mode == 0, iclass 26, count 0 2006.286.03:25:06.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.03:25:06.89#ibcon#[27=BW32\r\n] 2006.286.03:25:06.89#ibcon#*before write, iclass 26, count 0 2006.286.03:25:06.89#ibcon#enter sib2, iclass 26, count 0 2006.286.03:25:06.89#ibcon#flushed, iclass 26, count 0 2006.286.03:25:06.89#ibcon#about to write, iclass 26, count 0 2006.286.03:25:06.89#ibcon#wrote, iclass 26, count 0 2006.286.03:25:06.89#ibcon#about to read 3, iclass 26, count 0 2006.286.03:25:06.92#ibcon#read 3, iclass 26, count 0 2006.286.03:25:06.92#ibcon#about to read 4, iclass 26, count 0 2006.286.03:25:06.92#ibcon#read 4, iclass 26, count 0 2006.286.03:25:06.92#ibcon#about to read 5, iclass 26, count 0 2006.286.03:25:06.92#ibcon#read 5, iclass 26, count 0 2006.286.03:25:06.92#ibcon#about to read 6, iclass 26, count 0 2006.286.03:25:06.92#ibcon#read 6, iclass 26, count 0 2006.286.03:25:06.92#ibcon#end of sib2, iclass 26, count 0 2006.286.03:25:06.92#ibcon#*after write, iclass 26, count 0 2006.286.03:25:06.92#ibcon#*before return 0, iclass 26, count 0 2006.286.03:25:06.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:25:06.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:25:06.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.03:25:06.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.03:25:06.92$setupk4/ifdk4 2006.286.03:25:06.92$ifdk4/lo= 2006.286.03:25:06.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.03:25:06.92$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.03:25:06.92$ifdk4/patch= 2006.286.03:25:06.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.03:25:06.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.03:25:06.92$setupk4/!*+20s 2006.286.03:25:09.73#abcon#<5=/04 3.2 6.3 21.82 771015.1\r\n> 2006.286.03:25:09.75#abcon#{5=INTERFACE CLEAR} 2006.286.03:25:09.81#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:25:19.90#abcon#<5=/04 3.2 6.3 21.83 771015.1\r\n> 2006.286.03:25:19.92#abcon#{5=INTERFACE CLEAR} 2006.286.03:25:19.98#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:25:20.80$setupk4/"tpicd 2006.286.03:25:20.80$setupk4/echo=off 2006.286.03:25:20.80$setupk4/xlog=off 2006.286.03:25:20.80:!2006.286.03:28:40 2006.286.03:25:55.14#trakl#Source acquired 2006.286.03:25:55.14#flagr#flagr/antenna,acquired 2006.286.03:28:40.00:preob 2006.286.03:28:41.14/onsource/TRACKING 2006.286.03:28:41.14:!2006.286.03:28:50 2006.286.03:28:50.00:"tape 2006.286.03:28:50.00:"st=record 2006.286.03:28:50.00:data_valid=on 2006.286.03:28:50.00:midob 2006.286.03:28:50.14/onsource/TRACKING 2006.286.03:28:50.14/wx/21.85,1015.1,76 2006.286.03:28:50.31/cable/+6.4984E-03 2006.286.03:28:51.40/va/01,07,usb,yes,33,36 2006.286.03:28:51.40/va/02,06,usb,yes,34,34 2006.286.03:28:51.40/va/03,07,usb,yes,33,35 2006.286.03:28:51.40/va/04,06,usb,yes,35,36 2006.286.03:28:51.40/va/05,03,usb,yes,34,35 2006.286.03:28:51.40/va/06,04,usb,yes,31,30 2006.286.03:28:51.40/va/07,04,usb,yes,31,32 2006.286.03:28:51.40/va/08,03,usb,yes,32,39 2006.286.03:28:51.63/valo/01,524.99,yes,locked 2006.286.03:28:51.63/valo/02,534.99,yes,locked 2006.286.03:28:51.63/valo/03,564.99,yes,locked 2006.286.03:28:51.63/valo/04,624.99,yes,locked 2006.286.03:28:51.63/valo/05,734.99,yes,locked 2006.286.03:28:51.63/valo/06,814.99,yes,locked 2006.286.03:28:51.63/valo/07,864.99,yes,locked 2006.286.03:28:51.63/valo/08,884.99,yes,locked 2006.286.03:28:52.72/vb/01,04,usb,yes,31,29 2006.286.03:28:52.72/vb/02,05,usb,yes,30,29 2006.286.03:28:52.72/vb/03,04,usb,yes,31,34 2006.286.03:28:52.72/vb/04,05,usb,yes,31,30 2006.286.03:28:52.72/vb/05,04,usb,yes,27,30 2006.286.03:28:52.72/vb/06,03,usb,yes,39,35 2006.286.03:28:52.72/vb/07,04,usb,yes,32,31 2006.286.03:28:52.72/vb/08,04,usb,yes,29,32 2006.286.03:28:52.95/vblo/01,629.99,yes,locked 2006.286.03:28:52.95/vblo/02,634.99,yes,locked 2006.286.03:28:52.95/vblo/03,649.99,yes,locked 2006.286.03:28:52.95/vblo/04,679.99,yes,locked 2006.286.03:28:52.95/vblo/05,709.99,yes,locked 2006.286.03:28:52.95/vblo/06,719.99,yes,locked 2006.286.03:28:52.95/vblo/07,734.99,yes,locked 2006.286.03:28:52.95/vblo/08,744.99,yes,locked 2006.286.03:28:53.10/vabw/8 2006.286.03:28:53.25/vbbw/8 2006.286.03:28:53.34/xfe/off,on,12.2 2006.286.03:28:53.72/ifatt/23,28,28,28 2006.286.03:28:54.07/fmout-gps/S +2.51E-07 2006.286.03:28:54.09:!2006.286.03:34:00 2006.286.03:34:00.00:data_valid=off 2006.286.03:34:00.00:"et 2006.286.03:34:00.00:!+3s 2006.286.03:34:03.01:"tape 2006.286.03:34:03.01:postob 2006.286.03:34:03.08/cable/+6.4981E-03 2006.286.03:34:03.08/wx/21.73,1015.1,79 2006.286.03:34:04.07/fmout-gps/S +2.53E-07 2006.286.03:34:04.07:scan_name=286-0337,jd0610,40 2006.286.03:34:04.07:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.286.03:34:05.14#flagr#flagr/antenna,new-source 2006.286.03:34:05.14:checkk5 2006.286.03:34:05.71/chk_autoobs//k5ts1/ autoobs is running! 2006.286.03:34:06.15/chk_autoobs//k5ts2/ autoobs is running! 2006.286.03:34:06.64/chk_autoobs//k5ts3/ autoobs is running! 2006.286.03:34:07.05/chk_autoobs//k5ts4/ autoobs is running! 2006.286.03:34:07.52/chk_obsdata//k5ts1/T2860328??a.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.286.03:34:07.90/chk_obsdata//k5ts2/T2860328??b.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.286.03:34:08.56/chk_obsdata//k5ts3/T2860328??c.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.286.03:34:09.23/chk_obsdata//k5ts4/T2860328??d.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.286.03:34:09.99/k5log//k5ts1_log_newline 2006.286.03:34:10.81/k5log//k5ts2_log_newline 2006.286.03:34:11.82/k5log//k5ts3_log_newline 2006.286.03:34:12.65/k5log//k5ts4_log_newline 2006.286.03:34:12.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.03:34:12.67:setupk4=1 2006.286.03:34:12.67$setupk4/echo=on 2006.286.03:34:12.67$setupk4/pcalon 2006.286.03:34:12.67$pcalon/"no phase cal control is implemented here 2006.286.03:34:12.67$setupk4/"tpicd=stop 2006.286.03:34:12.67$setupk4/"rec=synch_on 2006.286.03:34:12.67$setupk4/"rec_mode=128 2006.286.03:34:12.67$setupk4/!* 2006.286.03:34:12.67$setupk4/recpk4 2006.286.03:34:12.67$recpk4/recpatch= 2006.286.03:34:12.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.03:34:12.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.03:34:12.68$setupk4/vck44 2006.286.03:34:12.68$vck44/valo=1,524.99 2006.286.03:34:12.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.03:34:12.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.03:34:12.68#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:12.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:34:12.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:34:12.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:34:12.68#ibcon#enter wrdev, iclass 31, count 0 2006.286.03:34:12.68#ibcon#first serial, iclass 31, count 0 2006.286.03:34:12.68#ibcon#enter sib2, iclass 31, count 0 2006.286.03:34:12.68#ibcon#flushed, iclass 31, count 0 2006.286.03:34:12.68#ibcon#about to write, iclass 31, count 0 2006.286.03:34:12.68#ibcon#wrote, iclass 31, count 0 2006.286.03:34:12.68#ibcon#about to read 3, iclass 31, count 0 2006.286.03:34:12.70#ibcon#read 3, iclass 31, count 0 2006.286.03:34:12.70#ibcon#about to read 4, iclass 31, count 0 2006.286.03:34:12.70#ibcon#read 4, iclass 31, count 0 2006.286.03:34:12.70#ibcon#about to read 5, iclass 31, count 0 2006.286.03:34:12.70#ibcon#read 5, iclass 31, count 0 2006.286.03:34:12.70#ibcon#about to read 6, iclass 31, count 0 2006.286.03:34:12.70#ibcon#read 6, iclass 31, count 0 2006.286.03:34:12.70#ibcon#end of sib2, iclass 31, count 0 2006.286.03:34:12.70#ibcon#*mode == 0, iclass 31, count 0 2006.286.03:34:12.70#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.03:34:12.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.03:34:12.70#ibcon#*before write, iclass 31, count 0 2006.286.03:34:12.70#ibcon#enter sib2, iclass 31, count 0 2006.286.03:34:12.70#ibcon#flushed, iclass 31, count 0 2006.286.03:34:12.70#ibcon#about to write, iclass 31, count 0 2006.286.03:34:12.70#ibcon#wrote, iclass 31, count 0 2006.286.03:34:12.70#ibcon#about to read 3, iclass 31, count 0 2006.286.03:34:12.75#ibcon#read 3, iclass 31, count 0 2006.286.03:34:12.75#ibcon#about to read 4, iclass 31, count 0 2006.286.03:34:12.75#ibcon#read 4, iclass 31, count 0 2006.286.03:34:12.75#ibcon#about to read 5, iclass 31, count 0 2006.286.03:34:12.75#ibcon#read 5, iclass 31, count 0 2006.286.03:34:12.75#ibcon#about to read 6, iclass 31, count 0 2006.286.03:34:12.75#ibcon#read 6, iclass 31, count 0 2006.286.03:34:12.75#ibcon#end of sib2, iclass 31, count 0 2006.286.03:34:12.75#ibcon#*after write, iclass 31, count 0 2006.286.03:34:12.75#ibcon#*before return 0, iclass 31, count 0 2006.286.03:34:12.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:34:12.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:34:12.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.03:34:12.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.03:34:12.75$vck44/va=1,7 2006.286.03:34:12.75#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.03:34:12.75#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.03:34:12.75#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:12.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:34:12.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:34:12.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:34:12.75#ibcon#enter wrdev, iclass 33, count 2 2006.286.03:34:12.75#ibcon#first serial, iclass 33, count 2 2006.286.03:34:12.75#ibcon#enter sib2, iclass 33, count 2 2006.286.03:34:12.75#ibcon#flushed, iclass 33, count 2 2006.286.03:34:12.75#ibcon#about to write, iclass 33, count 2 2006.286.03:34:12.75#ibcon#wrote, iclass 33, count 2 2006.286.03:34:12.75#ibcon#about to read 3, iclass 33, count 2 2006.286.03:34:12.77#ibcon#read 3, iclass 33, count 2 2006.286.03:34:12.77#ibcon#about to read 4, iclass 33, count 2 2006.286.03:34:12.77#ibcon#read 4, iclass 33, count 2 2006.286.03:34:12.77#ibcon#about to read 5, iclass 33, count 2 2006.286.03:34:12.77#ibcon#read 5, iclass 33, count 2 2006.286.03:34:12.77#ibcon#about to read 6, iclass 33, count 2 2006.286.03:34:12.77#ibcon#read 6, iclass 33, count 2 2006.286.03:34:12.77#ibcon#end of sib2, iclass 33, count 2 2006.286.03:34:12.77#ibcon#*mode == 0, iclass 33, count 2 2006.286.03:34:12.77#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.03:34:12.77#ibcon#[25=AT01-07\r\n] 2006.286.03:34:12.77#ibcon#*before write, iclass 33, count 2 2006.286.03:34:12.77#ibcon#enter sib2, iclass 33, count 2 2006.286.03:34:12.77#ibcon#flushed, iclass 33, count 2 2006.286.03:34:12.77#ibcon#about to write, iclass 33, count 2 2006.286.03:34:12.77#ibcon#wrote, iclass 33, count 2 2006.286.03:34:12.77#ibcon#about to read 3, iclass 33, count 2 2006.286.03:34:12.80#ibcon#read 3, iclass 33, count 2 2006.286.03:34:12.80#ibcon#about to read 4, iclass 33, count 2 2006.286.03:34:12.80#ibcon#read 4, iclass 33, count 2 2006.286.03:34:12.80#ibcon#about to read 5, iclass 33, count 2 2006.286.03:34:12.80#ibcon#read 5, iclass 33, count 2 2006.286.03:34:12.80#ibcon#about to read 6, iclass 33, count 2 2006.286.03:34:12.80#ibcon#read 6, iclass 33, count 2 2006.286.03:34:12.80#ibcon#end of sib2, iclass 33, count 2 2006.286.03:34:12.80#ibcon#*after write, iclass 33, count 2 2006.286.03:34:12.80#ibcon#*before return 0, iclass 33, count 2 2006.286.03:34:12.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:34:12.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:34:12.80#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.03:34:12.80#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:12.80#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:34:12.92#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:34:12.92#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:34:12.92#ibcon#enter wrdev, iclass 33, count 0 2006.286.03:34:12.92#ibcon#first serial, iclass 33, count 0 2006.286.03:34:12.92#ibcon#enter sib2, iclass 33, count 0 2006.286.03:34:12.92#ibcon#flushed, iclass 33, count 0 2006.286.03:34:12.92#ibcon#about to write, iclass 33, count 0 2006.286.03:34:12.92#ibcon#wrote, iclass 33, count 0 2006.286.03:34:12.92#ibcon#about to read 3, iclass 33, count 0 2006.286.03:34:12.94#ibcon#read 3, iclass 33, count 0 2006.286.03:34:12.94#ibcon#about to read 4, iclass 33, count 0 2006.286.03:34:12.94#ibcon#read 4, iclass 33, count 0 2006.286.03:34:12.94#ibcon#about to read 5, iclass 33, count 0 2006.286.03:34:12.94#ibcon#read 5, iclass 33, count 0 2006.286.03:34:12.94#ibcon#about to read 6, iclass 33, count 0 2006.286.03:34:12.94#ibcon#read 6, iclass 33, count 0 2006.286.03:34:12.94#ibcon#end of sib2, iclass 33, count 0 2006.286.03:34:12.94#ibcon#*mode == 0, iclass 33, count 0 2006.286.03:34:12.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.03:34:12.94#ibcon#[25=USB\r\n] 2006.286.03:34:12.94#ibcon#*before write, iclass 33, count 0 2006.286.03:34:12.94#ibcon#enter sib2, iclass 33, count 0 2006.286.03:34:12.94#ibcon#flushed, iclass 33, count 0 2006.286.03:34:12.94#ibcon#about to write, iclass 33, count 0 2006.286.03:34:12.94#ibcon#wrote, iclass 33, count 0 2006.286.03:34:12.94#ibcon#about to read 3, iclass 33, count 0 2006.286.03:34:12.97#ibcon#read 3, iclass 33, count 0 2006.286.03:34:12.97#ibcon#about to read 4, iclass 33, count 0 2006.286.03:34:12.97#ibcon#read 4, iclass 33, count 0 2006.286.03:34:12.97#ibcon#about to read 5, iclass 33, count 0 2006.286.03:34:12.97#ibcon#read 5, iclass 33, count 0 2006.286.03:34:12.97#ibcon#about to read 6, iclass 33, count 0 2006.286.03:34:12.97#ibcon#read 6, iclass 33, count 0 2006.286.03:34:12.97#ibcon#end of sib2, iclass 33, count 0 2006.286.03:34:12.97#ibcon#*after write, iclass 33, count 0 2006.286.03:34:12.97#ibcon#*before return 0, iclass 33, count 0 2006.286.03:34:12.97#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:34:12.97#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:34:12.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.03:34:12.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.03:34:12.97$vck44/valo=2,534.99 2006.286.03:34:12.97#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.03:34:12.97#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.03:34:12.97#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:12.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:34:12.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:34:12.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:34:12.97#ibcon#enter wrdev, iclass 35, count 0 2006.286.03:34:12.97#ibcon#first serial, iclass 35, count 0 2006.286.03:34:12.97#ibcon#enter sib2, iclass 35, count 0 2006.286.03:34:12.97#ibcon#flushed, iclass 35, count 0 2006.286.03:34:12.97#ibcon#about to write, iclass 35, count 0 2006.286.03:34:12.97#ibcon#wrote, iclass 35, count 0 2006.286.03:34:12.97#ibcon#about to read 3, iclass 35, count 0 2006.286.03:34:12.99#ibcon#read 3, iclass 35, count 0 2006.286.03:34:12.99#ibcon#about to read 4, iclass 35, count 0 2006.286.03:34:12.99#ibcon#read 4, iclass 35, count 0 2006.286.03:34:12.99#ibcon#about to read 5, iclass 35, count 0 2006.286.03:34:12.99#ibcon#read 5, iclass 35, count 0 2006.286.03:34:12.99#ibcon#about to read 6, iclass 35, count 0 2006.286.03:34:12.99#ibcon#read 6, iclass 35, count 0 2006.286.03:34:12.99#ibcon#end of sib2, iclass 35, count 0 2006.286.03:34:12.99#ibcon#*mode == 0, iclass 35, count 0 2006.286.03:34:12.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.03:34:12.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.03:34:12.99#ibcon#*before write, iclass 35, count 0 2006.286.03:34:12.99#ibcon#enter sib2, iclass 35, count 0 2006.286.03:34:12.99#ibcon#flushed, iclass 35, count 0 2006.286.03:34:12.99#ibcon#about to write, iclass 35, count 0 2006.286.03:34:12.99#ibcon#wrote, iclass 35, count 0 2006.286.03:34:12.99#ibcon#about to read 3, iclass 35, count 0 2006.286.03:34:13.03#ibcon#read 3, iclass 35, count 0 2006.286.03:34:13.03#ibcon#about to read 4, iclass 35, count 0 2006.286.03:34:13.03#ibcon#read 4, iclass 35, count 0 2006.286.03:34:13.03#ibcon#about to read 5, iclass 35, count 0 2006.286.03:34:13.03#ibcon#read 5, iclass 35, count 0 2006.286.03:34:13.03#ibcon#about to read 6, iclass 35, count 0 2006.286.03:34:13.03#ibcon#read 6, iclass 35, count 0 2006.286.03:34:13.03#ibcon#end of sib2, iclass 35, count 0 2006.286.03:34:13.03#ibcon#*after write, iclass 35, count 0 2006.286.03:34:13.03#ibcon#*before return 0, iclass 35, count 0 2006.286.03:34:13.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:34:13.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:34:13.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.03:34:13.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.03:34:13.03$vck44/va=2,6 2006.286.03:34:13.03#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.03:34:13.03#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.03:34:13.03#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:13.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:34:13.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:34:13.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:34:13.09#ibcon#enter wrdev, iclass 37, count 2 2006.286.03:34:13.09#ibcon#first serial, iclass 37, count 2 2006.286.03:34:13.09#ibcon#enter sib2, iclass 37, count 2 2006.286.03:34:13.09#ibcon#flushed, iclass 37, count 2 2006.286.03:34:13.09#ibcon#about to write, iclass 37, count 2 2006.286.03:34:13.09#ibcon#wrote, iclass 37, count 2 2006.286.03:34:13.09#ibcon#about to read 3, iclass 37, count 2 2006.286.03:34:13.11#ibcon#read 3, iclass 37, count 2 2006.286.03:34:13.11#ibcon#about to read 4, iclass 37, count 2 2006.286.03:34:13.11#ibcon#read 4, iclass 37, count 2 2006.286.03:34:13.11#ibcon#about to read 5, iclass 37, count 2 2006.286.03:34:13.11#ibcon#read 5, iclass 37, count 2 2006.286.03:34:13.11#ibcon#about to read 6, iclass 37, count 2 2006.286.03:34:13.11#ibcon#read 6, iclass 37, count 2 2006.286.03:34:13.11#ibcon#end of sib2, iclass 37, count 2 2006.286.03:34:13.11#ibcon#*mode == 0, iclass 37, count 2 2006.286.03:34:13.11#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.03:34:13.11#ibcon#[25=AT02-06\r\n] 2006.286.03:34:13.11#ibcon#*before write, iclass 37, count 2 2006.286.03:34:13.11#ibcon#enter sib2, iclass 37, count 2 2006.286.03:34:13.11#ibcon#flushed, iclass 37, count 2 2006.286.03:34:13.11#ibcon#about to write, iclass 37, count 2 2006.286.03:34:13.11#ibcon#wrote, iclass 37, count 2 2006.286.03:34:13.11#ibcon#about to read 3, iclass 37, count 2 2006.286.03:34:13.14#ibcon#read 3, iclass 37, count 2 2006.286.03:34:13.14#ibcon#about to read 4, iclass 37, count 2 2006.286.03:34:13.14#ibcon#read 4, iclass 37, count 2 2006.286.03:34:13.14#ibcon#about to read 5, iclass 37, count 2 2006.286.03:34:13.14#ibcon#read 5, iclass 37, count 2 2006.286.03:34:13.14#ibcon#about to read 6, iclass 37, count 2 2006.286.03:34:13.14#ibcon#read 6, iclass 37, count 2 2006.286.03:34:13.14#ibcon#end of sib2, iclass 37, count 2 2006.286.03:34:13.14#ibcon#*after write, iclass 37, count 2 2006.286.03:34:13.14#ibcon#*before return 0, iclass 37, count 2 2006.286.03:34:13.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:34:13.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:34:13.14#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.03:34:13.14#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:13.14#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:34:13.26#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:34:13.26#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:34:13.26#ibcon#enter wrdev, iclass 37, count 0 2006.286.03:34:13.26#ibcon#first serial, iclass 37, count 0 2006.286.03:34:13.26#ibcon#enter sib2, iclass 37, count 0 2006.286.03:34:13.26#ibcon#flushed, iclass 37, count 0 2006.286.03:34:13.26#ibcon#about to write, iclass 37, count 0 2006.286.03:34:13.26#ibcon#wrote, iclass 37, count 0 2006.286.03:34:13.26#ibcon#about to read 3, iclass 37, count 0 2006.286.03:34:13.28#ibcon#read 3, iclass 37, count 0 2006.286.03:34:13.28#ibcon#about to read 4, iclass 37, count 0 2006.286.03:34:13.28#ibcon#read 4, iclass 37, count 0 2006.286.03:34:13.28#ibcon#about to read 5, iclass 37, count 0 2006.286.03:34:13.28#ibcon#read 5, iclass 37, count 0 2006.286.03:34:13.28#ibcon#about to read 6, iclass 37, count 0 2006.286.03:34:13.28#ibcon#read 6, iclass 37, count 0 2006.286.03:34:13.28#ibcon#end of sib2, iclass 37, count 0 2006.286.03:34:13.28#ibcon#*mode == 0, iclass 37, count 0 2006.286.03:34:13.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.03:34:13.28#ibcon#[25=USB\r\n] 2006.286.03:34:13.28#ibcon#*before write, iclass 37, count 0 2006.286.03:34:13.28#ibcon#enter sib2, iclass 37, count 0 2006.286.03:34:13.28#ibcon#flushed, iclass 37, count 0 2006.286.03:34:13.28#ibcon#about to write, iclass 37, count 0 2006.286.03:34:13.28#ibcon#wrote, iclass 37, count 0 2006.286.03:34:13.28#ibcon#about to read 3, iclass 37, count 0 2006.286.03:34:13.31#ibcon#read 3, iclass 37, count 0 2006.286.03:34:13.31#ibcon#about to read 4, iclass 37, count 0 2006.286.03:34:13.31#ibcon#read 4, iclass 37, count 0 2006.286.03:34:13.31#ibcon#about to read 5, iclass 37, count 0 2006.286.03:34:13.31#ibcon#read 5, iclass 37, count 0 2006.286.03:34:13.31#ibcon#about to read 6, iclass 37, count 0 2006.286.03:34:13.31#ibcon#read 6, iclass 37, count 0 2006.286.03:34:13.31#ibcon#end of sib2, iclass 37, count 0 2006.286.03:34:13.31#ibcon#*after write, iclass 37, count 0 2006.286.03:34:13.31#ibcon#*before return 0, iclass 37, count 0 2006.286.03:34:13.31#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:34:13.31#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:34:13.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.03:34:13.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.03:34:13.31$vck44/valo=3,564.99 2006.286.03:34:13.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.03:34:13.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.03:34:13.31#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:13.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:34:13.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:34:13.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:34:13.31#ibcon#enter wrdev, iclass 39, count 0 2006.286.03:34:13.31#ibcon#first serial, iclass 39, count 0 2006.286.03:34:13.31#ibcon#enter sib2, iclass 39, count 0 2006.286.03:34:13.31#ibcon#flushed, iclass 39, count 0 2006.286.03:34:13.31#ibcon#about to write, iclass 39, count 0 2006.286.03:34:13.31#ibcon#wrote, iclass 39, count 0 2006.286.03:34:13.31#ibcon#about to read 3, iclass 39, count 0 2006.286.03:34:13.33#ibcon#read 3, iclass 39, count 0 2006.286.03:34:13.33#ibcon#about to read 4, iclass 39, count 0 2006.286.03:34:13.33#ibcon#read 4, iclass 39, count 0 2006.286.03:34:13.33#ibcon#about to read 5, iclass 39, count 0 2006.286.03:34:13.33#ibcon#read 5, iclass 39, count 0 2006.286.03:34:13.33#ibcon#about to read 6, iclass 39, count 0 2006.286.03:34:13.33#ibcon#read 6, iclass 39, count 0 2006.286.03:34:13.33#ibcon#end of sib2, iclass 39, count 0 2006.286.03:34:13.33#ibcon#*mode == 0, iclass 39, count 0 2006.286.03:34:13.33#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.03:34:13.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.03:34:13.33#ibcon#*before write, iclass 39, count 0 2006.286.03:34:13.33#ibcon#enter sib2, iclass 39, count 0 2006.286.03:34:13.33#ibcon#flushed, iclass 39, count 0 2006.286.03:34:13.33#ibcon#about to write, iclass 39, count 0 2006.286.03:34:13.33#ibcon#wrote, iclass 39, count 0 2006.286.03:34:13.33#ibcon#about to read 3, iclass 39, count 0 2006.286.03:34:13.37#ibcon#read 3, iclass 39, count 0 2006.286.03:34:13.37#ibcon#about to read 4, iclass 39, count 0 2006.286.03:34:13.37#ibcon#read 4, iclass 39, count 0 2006.286.03:34:13.37#ibcon#about to read 5, iclass 39, count 0 2006.286.03:34:13.37#ibcon#read 5, iclass 39, count 0 2006.286.03:34:13.37#ibcon#about to read 6, iclass 39, count 0 2006.286.03:34:13.37#ibcon#read 6, iclass 39, count 0 2006.286.03:34:13.37#ibcon#end of sib2, iclass 39, count 0 2006.286.03:34:13.37#ibcon#*after write, iclass 39, count 0 2006.286.03:34:13.37#ibcon#*before return 0, iclass 39, count 0 2006.286.03:34:13.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:34:13.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:34:13.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.03:34:13.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.03:34:13.37$vck44/va=3,7 2006.286.03:34:13.37#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.03:34:13.37#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.03:34:13.37#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:13.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:34:13.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:34:13.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:34:13.43#ibcon#enter wrdev, iclass 3, count 2 2006.286.03:34:13.43#ibcon#first serial, iclass 3, count 2 2006.286.03:34:13.43#ibcon#enter sib2, iclass 3, count 2 2006.286.03:34:13.43#ibcon#flushed, iclass 3, count 2 2006.286.03:34:13.43#ibcon#about to write, iclass 3, count 2 2006.286.03:34:13.43#ibcon#wrote, iclass 3, count 2 2006.286.03:34:13.43#ibcon#about to read 3, iclass 3, count 2 2006.286.03:34:13.45#ibcon#read 3, iclass 3, count 2 2006.286.03:34:13.45#ibcon#about to read 4, iclass 3, count 2 2006.286.03:34:13.45#ibcon#read 4, iclass 3, count 2 2006.286.03:34:13.45#ibcon#about to read 5, iclass 3, count 2 2006.286.03:34:13.45#ibcon#read 5, iclass 3, count 2 2006.286.03:34:13.45#ibcon#about to read 6, iclass 3, count 2 2006.286.03:34:13.45#ibcon#read 6, iclass 3, count 2 2006.286.03:34:13.45#ibcon#end of sib2, iclass 3, count 2 2006.286.03:34:13.45#ibcon#*mode == 0, iclass 3, count 2 2006.286.03:34:13.45#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.03:34:13.45#ibcon#[25=AT03-07\r\n] 2006.286.03:34:13.45#ibcon#*before write, iclass 3, count 2 2006.286.03:34:13.45#ibcon#enter sib2, iclass 3, count 2 2006.286.03:34:13.45#ibcon#flushed, iclass 3, count 2 2006.286.03:34:13.45#ibcon#about to write, iclass 3, count 2 2006.286.03:34:13.45#ibcon#wrote, iclass 3, count 2 2006.286.03:34:13.45#ibcon#about to read 3, iclass 3, count 2 2006.286.03:34:13.48#ibcon#read 3, iclass 3, count 2 2006.286.03:34:13.48#ibcon#about to read 4, iclass 3, count 2 2006.286.03:34:13.48#ibcon#read 4, iclass 3, count 2 2006.286.03:34:13.48#ibcon#about to read 5, iclass 3, count 2 2006.286.03:34:13.48#ibcon#read 5, iclass 3, count 2 2006.286.03:34:13.48#ibcon#about to read 6, iclass 3, count 2 2006.286.03:34:13.48#ibcon#read 6, iclass 3, count 2 2006.286.03:34:13.48#ibcon#end of sib2, iclass 3, count 2 2006.286.03:34:13.48#ibcon#*after write, iclass 3, count 2 2006.286.03:34:13.48#ibcon#*before return 0, iclass 3, count 2 2006.286.03:34:13.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:34:13.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:34:13.48#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.03:34:13.48#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:13.48#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:34:13.60#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:34:13.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:34:13.96#ibcon#enter wrdev, iclass 3, count 0 2006.286.03:34:13.96#ibcon#first serial, iclass 3, count 0 2006.286.03:34:13.96#ibcon#enter sib2, iclass 3, count 0 2006.286.03:34:13.96#ibcon#flushed, iclass 3, count 0 2006.286.03:34:13.96#ibcon#about to write, iclass 3, count 0 2006.286.03:34:13.96#ibcon#wrote, iclass 3, count 0 2006.286.03:34:13.96#ibcon#about to read 3, iclass 3, count 0 2006.286.03:34:13.97#ibcon#read 3, iclass 3, count 0 2006.286.03:34:13.97#ibcon#about to read 4, iclass 3, count 0 2006.286.03:34:13.97#ibcon#read 4, iclass 3, count 0 2006.286.03:34:13.97#ibcon#about to read 5, iclass 3, count 0 2006.286.03:34:13.97#ibcon#read 5, iclass 3, count 0 2006.286.03:34:13.97#ibcon#about to read 6, iclass 3, count 0 2006.286.03:34:13.97#ibcon#read 6, iclass 3, count 0 2006.286.03:34:13.97#ibcon#end of sib2, iclass 3, count 0 2006.286.03:34:13.97#ibcon#*mode == 0, iclass 3, count 0 2006.286.03:34:13.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.03:34:13.97#ibcon#[25=USB\r\n] 2006.286.03:34:13.97#ibcon#*before write, iclass 3, count 0 2006.286.03:34:13.97#ibcon#enter sib2, iclass 3, count 0 2006.286.03:34:13.97#ibcon#flushed, iclass 3, count 0 2006.286.03:34:13.97#ibcon#about to write, iclass 3, count 0 2006.286.03:34:13.97#ibcon#wrote, iclass 3, count 0 2006.286.03:34:13.97#ibcon#about to read 3, iclass 3, count 0 2006.286.03:34:14.00#ibcon#read 3, iclass 3, count 0 2006.286.03:34:14.00#ibcon#about to read 4, iclass 3, count 0 2006.286.03:34:14.00#ibcon#read 4, iclass 3, count 0 2006.286.03:34:14.00#ibcon#about to read 5, iclass 3, count 0 2006.286.03:34:14.00#ibcon#read 5, iclass 3, count 0 2006.286.03:34:14.00#ibcon#about to read 6, iclass 3, count 0 2006.286.03:34:14.00#ibcon#read 6, iclass 3, count 0 2006.286.03:34:14.00#ibcon#end of sib2, iclass 3, count 0 2006.286.03:34:14.00#ibcon#*after write, iclass 3, count 0 2006.286.03:34:14.00#ibcon#*before return 0, iclass 3, count 0 2006.286.03:34:14.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:34:14.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:34:14.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.03:34:14.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.03:34:14.00$vck44/valo=4,624.99 2006.286.03:34:14.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.03:34:14.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.03:34:14.00#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:14.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:34:14.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:34:14.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:34:14.00#ibcon#enter wrdev, iclass 5, count 0 2006.286.03:34:14.00#ibcon#first serial, iclass 5, count 0 2006.286.03:34:14.00#ibcon#enter sib2, iclass 5, count 0 2006.286.03:34:14.00#ibcon#flushed, iclass 5, count 0 2006.286.03:34:14.00#ibcon#about to write, iclass 5, count 0 2006.286.03:34:14.00#ibcon#wrote, iclass 5, count 0 2006.286.03:34:14.00#ibcon#about to read 3, iclass 5, count 0 2006.286.03:34:14.02#ibcon#read 3, iclass 5, count 0 2006.286.03:34:14.02#ibcon#about to read 4, iclass 5, count 0 2006.286.03:34:14.02#ibcon#read 4, iclass 5, count 0 2006.286.03:34:14.02#ibcon#about to read 5, iclass 5, count 0 2006.286.03:34:14.02#ibcon#read 5, iclass 5, count 0 2006.286.03:34:14.02#ibcon#about to read 6, iclass 5, count 0 2006.286.03:34:14.02#ibcon#read 6, iclass 5, count 0 2006.286.03:34:14.02#ibcon#end of sib2, iclass 5, count 0 2006.286.03:34:14.02#ibcon#*mode == 0, iclass 5, count 0 2006.286.03:34:14.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.03:34:14.02#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.03:34:14.02#ibcon#*before write, iclass 5, count 0 2006.286.03:34:14.02#ibcon#enter sib2, iclass 5, count 0 2006.286.03:34:14.02#ibcon#flushed, iclass 5, count 0 2006.286.03:34:14.02#ibcon#about to write, iclass 5, count 0 2006.286.03:34:14.02#ibcon#wrote, iclass 5, count 0 2006.286.03:34:14.02#ibcon#about to read 3, iclass 5, count 0 2006.286.03:34:14.06#ibcon#read 3, iclass 5, count 0 2006.286.03:34:14.06#ibcon#about to read 4, iclass 5, count 0 2006.286.03:34:14.06#ibcon#read 4, iclass 5, count 0 2006.286.03:34:14.06#ibcon#about to read 5, iclass 5, count 0 2006.286.03:34:14.06#ibcon#read 5, iclass 5, count 0 2006.286.03:34:14.06#ibcon#about to read 6, iclass 5, count 0 2006.286.03:34:14.06#ibcon#read 6, iclass 5, count 0 2006.286.03:34:14.06#ibcon#end of sib2, iclass 5, count 0 2006.286.03:34:14.06#ibcon#*after write, iclass 5, count 0 2006.286.03:34:14.06#ibcon#*before return 0, iclass 5, count 0 2006.286.03:34:14.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:34:14.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:34:14.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.03:34:14.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.03:34:14.06$vck44/va=4,6 2006.286.03:34:14.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.03:34:14.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.03:34:14.06#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:14.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:34:14.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:34:14.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:34:14.12#ibcon#enter wrdev, iclass 7, count 2 2006.286.03:34:14.12#ibcon#first serial, iclass 7, count 2 2006.286.03:34:14.12#ibcon#enter sib2, iclass 7, count 2 2006.286.03:34:14.12#ibcon#flushed, iclass 7, count 2 2006.286.03:34:14.12#ibcon#about to write, iclass 7, count 2 2006.286.03:34:14.12#ibcon#wrote, iclass 7, count 2 2006.286.03:34:14.12#ibcon#about to read 3, iclass 7, count 2 2006.286.03:34:14.14#ibcon#read 3, iclass 7, count 2 2006.286.03:34:14.14#ibcon#about to read 4, iclass 7, count 2 2006.286.03:34:14.14#ibcon#read 4, iclass 7, count 2 2006.286.03:34:14.14#ibcon#about to read 5, iclass 7, count 2 2006.286.03:34:14.14#ibcon#read 5, iclass 7, count 2 2006.286.03:34:14.14#ibcon#about to read 6, iclass 7, count 2 2006.286.03:34:14.14#ibcon#read 6, iclass 7, count 2 2006.286.03:34:14.14#ibcon#end of sib2, iclass 7, count 2 2006.286.03:34:14.14#ibcon#*mode == 0, iclass 7, count 2 2006.286.03:34:14.14#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.03:34:14.14#ibcon#[25=AT04-06\r\n] 2006.286.03:34:14.14#ibcon#*before write, iclass 7, count 2 2006.286.03:34:14.14#ibcon#enter sib2, iclass 7, count 2 2006.286.03:34:14.14#ibcon#flushed, iclass 7, count 2 2006.286.03:34:14.14#ibcon#about to write, iclass 7, count 2 2006.286.03:34:14.14#ibcon#wrote, iclass 7, count 2 2006.286.03:34:14.14#ibcon#about to read 3, iclass 7, count 2 2006.286.03:34:14.17#ibcon#read 3, iclass 7, count 2 2006.286.03:34:14.17#ibcon#about to read 4, iclass 7, count 2 2006.286.03:34:14.17#ibcon#read 4, iclass 7, count 2 2006.286.03:34:14.17#ibcon#about to read 5, iclass 7, count 2 2006.286.03:34:14.17#ibcon#read 5, iclass 7, count 2 2006.286.03:34:14.17#ibcon#about to read 6, iclass 7, count 2 2006.286.03:34:14.17#ibcon#read 6, iclass 7, count 2 2006.286.03:34:14.17#ibcon#end of sib2, iclass 7, count 2 2006.286.03:34:14.17#ibcon#*after write, iclass 7, count 2 2006.286.03:34:14.17#ibcon#*before return 0, iclass 7, count 2 2006.286.03:34:14.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:34:14.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:34:14.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.03:34:14.17#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:14.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:34:14.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:34:14.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:34:14.29#ibcon#enter wrdev, iclass 7, count 0 2006.286.03:34:14.29#ibcon#first serial, iclass 7, count 0 2006.286.03:34:14.29#ibcon#enter sib2, iclass 7, count 0 2006.286.03:34:14.29#ibcon#flushed, iclass 7, count 0 2006.286.03:34:14.29#ibcon#about to write, iclass 7, count 0 2006.286.03:34:14.29#ibcon#wrote, iclass 7, count 0 2006.286.03:34:14.29#ibcon#about to read 3, iclass 7, count 0 2006.286.03:34:14.31#ibcon#read 3, iclass 7, count 0 2006.286.03:34:14.31#ibcon#about to read 4, iclass 7, count 0 2006.286.03:34:14.31#ibcon#read 4, iclass 7, count 0 2006.286.03:34:14.31#ibcon#about to read 5, iclass 7, count 0 2006.286.03:34:14.31#ibcon#read 5, iclass 7, count 0 2006.286.03:34:14.31#ibcon#about to read 6, iclass 7, count 0 2006.286.03:34:14.31#ibcon#read 6, iclass 7, count 0 2006.286.03:34:14.31#ibcon#end of sib2, iclass 7, count 0 2006.286.03:34:14.31#ibcon#*mode == 0, iclass 7, count 0 2006.286.03:34:14.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.03:34:14.31#ibcon#[25=USB\r\n] 2006.286.03:34:14.31#ibcon#*before write, iclass 7, count 0 2006.286.03:34:14.31#ibcon#enter sib2, iclass 7, count 0 2006.286.03:34:14.31#ibcon#flushed, iclass 7, count 0 2006.286.03:34:14.31#ibcon#about to write, iclass 7, count 0 2006.286.03:34:14.31#ibcon#wrote, iclass 7, count 0 2006.286.03:34:14.31#ibcon#about to read 3, iclass 7, count 0 2006.286.03:34:14.34#ibcon#read 3, iclass 7, count 0 2006.286.03:34:14.42#ibcon#about to read 4, iclass 7, count 0 2006.286.03:34:14.42#ibcon#read 4, iclass 7, count 0 2006.286.03:34:14.42#ibcon#about to read 5, iclass 7, count 0 2006.286.03:34:14.42#ibcon#read 5, iclass 7, count 0 2006.286.03:34:14.42#ibcon#about to read 6, iclass 7, count 0 2006.286.03:34:14.42#ibcon#read 6, iclass 7, count 0 2006.286.03:34:14.42#ibcon#end of sib2, iclass 7, count 0 2006.286.03:34:14.42#ibcon#*after write, iclass 7, count 0 2006.286.03:34:14.42#ibcon#*before return 0, iclass 7, count 0 2006.286.03:34:14.42#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:34:14.42#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:34:14.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.03:34:14.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.03:34:14.42$vck44/valo=5,734.99 2006.286.03:34:14.42#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.03:34:14.42#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.03:34:14.42#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:14.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:34:14.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:34:14.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:34:14.42#ibcon#enter wrdev, iclass 11, count 0 2006.286.03:34:14.42#ibcon#first serial, iclass 11, count 0 2006.286.03:34:14.42#ibcon#enter sib2, iclass 11, count 0 2006.286.03:34:14.42#ibcon#flushed, iclass 11, count 0 2006.286.03:34:14.42#ibcon#about to write, iclass 11, count 0 2006.286.03:34:14.42#ibcon#wrote, iclass 11, count 0 2006.286.03:34:14.42#ibcon#about to read 3, iclass 11, count 0 2006.286.03:34:14.43#ibcon#read 3, iclass 11, count 0 2006.286.03:34:14.43#ibcon#about to read 4, iclass 11, count 0 2006.286.03:34:14.43#ibcon#read 4, iclass 11, count 0 2006.286.03:34:14.43#ibcon#about to read 5, iclass 11, count 0 2006.286.03:34:14.43#ibcon#read 5, iclass 11, count 0 2006.286.03:34:14.43#ibcon#about to read 6, iclass 11, count 0 2006.286.03:34:14.43#ibcon#read 6, iclass 11, count 0 2006.286.03:34:14.43#ibcon#end of sib2, iclass 11, count 0 2006.286.03:34:14.43#ibcon#*mode == 0, iclass 11, count 0 2006.286.03:34:14.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.03:34:14.43#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.03:34:14.43#ibcon#*before write, iclass 11, count 0 2006.286.03:34:14.43#ibcon#enter sib2, iclass 11, count 0 2006.286.03:34:14.43#ibcon#flushed, iclass 11, count 0 2006.286.03:34:14.43#ibcon#about to write, iclass 11, count 0 2006.286.03:34:14.43#ibcon#wrote, iclass 11, count 0 2006.286.03:34:14.43#ibcon#about to read 3, iclass 11, count 0 2006.286.03:34:14.47#ibcon#read 3, iclass 11, count 0 2006.286.03:34:14.47#ibcon#about to read 4, iclass 11, count 0 2006.286.03:34:14.47#ibcon#read 4, iclass 11, count 0 2006.286.03:34:14.47#ibcon#about to read 5, iclass 11, count 0 2006.286.03:34:14.47#ibcon#read 5, iclass 11, count 0 2006.286.03:34:14.47#ibcon#about to read 6, iclass 11, count 0 2006.286.03:34:14.47#ibcon#read 6, iclass 11, count 0 2006.286.03:34:14.47#ibcon#end of sib2, iclass 11, count 0 2006.286.03:34:14.47#ibcon#*after write, iclass 11, count 0 2006.286.03:34:14.47#ibcon#*before return 0, iclass 11, count 0 2006.286.03:34:14.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:34:14.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:34:14.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.03:34:14.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.03:34:14.47$vck44/va=5,3 2006.286.03:34:14.47#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.03:34:14.47#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.03:34:14.47#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:14.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:34:14.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:34:14.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:34:14.54#ibcon#enter wrdev, iclass 13, count 2 2006.286.03:34:14.54#ibcon#first serial, iclass 13, count 2 2006.286.03:34:14.54#ibcon#enter sib2, iclass 13, count 2 2006.286.03:34:14.54#ibcon#flushed, iclass 13, count 2 2006.286.03:34:14.54#ibcon#about to write, iclass 13, count 2 2006.286.03:34:14.54#ibcon#wrote, iclass 13, count 2 2006.286.03:34:14.54#ibcon#about to read 3, iclass 13, count 2 2006.286.03:34:14.56#ibcon#read 3, iclass 13, count 2 2006.286.03:34:14.56#ibcon#about to read 4, iclass 13, count 2 2006.286.03:34:14.56#ibcon#read 4, iclass 13, count 2 2006.286.03:34:14.56#ibcon#about to read 5, iclass 13, count 2 2006.286.03:34:14.56#ibcon#read 5, iclass 13, count 2 2006.286.03:34:14.56#ibcon#about to read 6, iclass 13, count 2 2006.286.03:34:14.56#ibcon#read 6, iclass 13, count 2 2006.286.03:34:14.56#ibcon#end of sib2, iclass 13, count 2 2006.286.03:34:14.56#ibcon#*mode == 0, iclass 13, count 2 2006.286.03:34:14.56#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.03:34:14.56#ibcon#[25=AT05-03\r\n] 2006.286.03:34:14.56#ibcon#*before write, iclass 13, count 2 2006.286.03:34:14.56#ibcon#enter sib2, iclass 13, count 2 2006.286.03:34:14.56#ibcon#flushed, iclass 13, count 2 2006.286.03:34:14.56#ibcon#about to write, iclass 13, count 2 2006.286.03:34:14.56#ibcon#wrote, iclass 13, count 2 2006.286.03:34:14.56#ibcon#about to read 3, iclass 13, count 2 2006.286.03:34:14.59#ibcon#read 3, iclass 13, count 2 2006.286.03:34:14.59#ibcon#about to read 4, iclass 13, count 2 2006.286.03:34:14.59#ibcon#read 4, iclass 13, count 2 2006.286.03:34:14.59#ibcon#about to read 5, iclass 13, count 2 2006.286.03:34:14.59#ibcon#read 5, iclass 13, count 2 2006.286.03:34:14.59#ibcon#about to read 6, iclass 13, count 2 2006.286.03:34:14.59#ibcon#read 6, iclass 13, count 2 2006.286.03:34:14.59#ibcon#end of sib2, iclass 13, count 2 2006.286.03:34:14.59#ibcon#*after write, iclass 13, count 2 2006.286.03:34:14.59#ibcon#*before return 0, iclass 13, count 2 2006.286.03:34:14.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:34:14.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:34:14.59#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.03:34:14.59#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:14.59#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:34:14.71#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:34:14.71#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:34:14.71#ibcon#enter wrdev, iclass 13, count 0 2006.286.03:34:14.71#ibcon#first serial, iclass 13, count 0 2006.286.03:34:14.71#ibcon#enter sib2, iclass 13, count 0 2006.286.03:34:14.71#ibcon#flushed, iclass 13, count 0 2006.286.03:34:14.71#ibcon#about to write, iclass 13, count 0 2006.286.03:34:14.71#ibcon#wrote, iclass 13, count 0 2006.286.03:34:14.71#ibcon#about to read 3, iclass 13, count 0 2006.286.03:34:14.73#ibcon#read 3, iclass 13, count 0 2006.286.03:34:14.73#ibcon#about to read 4, iclass 13, count 0 2006.286.03:34:14.73#ibcon#read 4, iclass 13, count 0 2006.286.03:34:14.73#ibcon#about to read 5, iclass 13, count 0 2006.286.03:34:14.73#ibcon#read 5, iclass 13, count 0 2006.286.03:34:14.73#ibcon#about to read 6, iclass 13, count 0 2006.286.03:34:14.73#ibcon#read 6, iclass 13, count 0 2006.286.03:34:14.73#ibcon#end of sib2, iclass 13, count 0 2006.286.03:34:14.73#ibcon#*mode == 0, iclass 13, count 0 2006.286.03:34:14.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.03:34:14.73#ibcon#[25=USB\r\n] 2006.286.03:34:14.73#ibcon#*before write, iclass 13, count 0 2006.286.03:34:14.73#ibcon#enter sib2, iclass 13, count 0 2006.286.03:34:14.73#ibcon#flushed, iclass 13, count 0 2006.286.03:34:14.73#ibcon#about to write, iclass 13, count 0 2006.286.03:34:14.73#ibcon#wrote, iclass 13, count 0 2006.286.03:34:14.73#ibcon#about to read 3, iclass 13, count 0 2006.286.03:34:14.76#ibcon#read 3, iclass 13, count 0 2006.286.03:34:14.76#ibcon#about to read 4, iclass 13, count 0 2006.286.03:34:14.76#ibcon#read 4, iclass 13, count 0 2006.286.03:34:14.76#ibcon#about to read 5, iclass 13, count 0 2006.286.03:34:14.76#ibcon#read 5, iclass 13, count 0 2006.286.03:34:14.76#ibcon#about to read 6, iclass 13, count 0 2006.286.03:34:14.76#ibcon#read 6, iclass 13, count 0 2006.286.03:34:14.76#ibcon#end of sib2, iclass 13, count 0 2006.286.03:34:14.76#ibcon#*after write, iclass 13, count 0 2006.286.03:34:14.76#ibcon#*before return 0, iclass 13, count 0 2006.286.03:34:14.76#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:34:14.76#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:34:14.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.03:34:14.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.03:34:14.76$vck44/valo=6,814.99 2006.286.03:34:14.76#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.03:34:14.76#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.03:34:14.76#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:14.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:34:14.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:34:14.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:34:14.76#ibcon#enter wrdev, iclass 15, count 0 2006.286.03:34:14.76#ibcon#first serial, iclass 15, count 0 2006.286.03:34:14.76#ibcon#enter sib2, iclass 15, count 0 2006.286.03:34:14.76#ibcon#flushed, iclass 15, count 0 2006.286.03:34:14.76#ibcon#about to write, iclass 15, count 0 2006.286.03:34:14.76#ibcon#wrote, iclass 15, count 0 2006.286.03:34:14.76#ibcon#about to read 3, iclass 15, count 0 2006.286.03:34:14.78#ibcon#read 3, iclass 15, count 0 2006.286.03:34:14.78#ibcon#about to read 4, iclass 15, count 0 2006.286.03:34:14.78#ibcon#read 4, iclass 15, count 0 2006.286.03:34:14.78#ibcon#about to read 5, iclass 15, count 0 2006.286.03:34:14.78#ibcon#read 5, iclass 15, count 0 2006.286.03:34:14.78#ibcon#about to read 6, iclass 15, count 0 2006.286.03:34:14.78#ibcon#read 6, iclass 15, count 0 2006.286.03:34:14.78#ibcon#end of sib2, iclass 15, count 0 2006.286.03:34:14.78#ibcon#*mode == 0, iclass 15, count 0 2006.286.03:34:14.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.03:34:14.78#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.03:34:14.78#ibcon#*before write, iclass 15, count 0 2006.286.03:34:14.78#ibcon#enter sib2, iclass 15, count 0 2006.286.03:34:14.78#ibcon#flushed, iclass 15, count 0 2006.286.03:34:14.78#ibcon#about to write, iclass 15, count 0 2006.286.03:34:14.78#ibcon#wrote, iclass 15, count 0 2006.286.03:34:14.78#ibcon#about to read 3, iclass 15, count 0 2006.286.03:34:14.82#ibcon#read 3, iclass 15, count 0 2006.286.03:34:14.82#ibcon#about to read 4, iclass 15, count 0 2006.286.03:34:14.82#ibcon#read 4, iclass 15, count 0 2006.286.03:34:14.82#ibcon#about to read 5, iclass 15, count 0 2006.286.03:34:14.82#ibcon#read 5, iclass 15, count 0 2006.286.03:34:14.82#ibcon#about to read 6, iclass 15, count 0 2006.286.03:34:14.82#ibcon#read 6, iclass 15, count 0 2006.286.03:34:14.82#ibcon#end of sib2, iclass 15, count 0 2006.286.03:34:14.82#ibcon#*after write, iclass 15, count 0 2006.286.03:34:14.82#ibcon#*before return 0, iclass 15, count 0 2006.286.03:34:14.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:34:14.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:34:14.82#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.03:34:14.82#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.03:34:14.82$vck44/va=6,4 2006.286.03:34:14.82#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.03:34:14.82#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.03:34:14.82#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:14.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:34:14.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:34:14.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:34:14.88#ibcon#enter wrdev, iclass 17, count 2 2006.286.03:34:14.88#ibcon#first serial, iclass 17, count 2 2006.286.03:34:14.88#ibcon#enter sib2, iclass 17, count 2 2006.286.03:34:14.88#ibcon#flushed, iclass 17, count 2 2006.286.03:34:14.88#ibcon#about to write, iclass 17, count 2 2006.286.03:34:14.88#ibcon#wrote, iclass 17, count 2 2006.286.03:34:14.88#ibcon#about to read 3, iclass 17, count 2 2006.286.03:34:14.90#ibcon#read 3, iclass 17, count 2 2006.286.03:34:14.90#ibcon#about to read 4, iclass 17, count 2 2006.286.03:34:14.90#ibcon#read 4, iclass 17, count 2 2006.286.03:34:14.90#ibcon#about to read 5, iclass 17, count 2 2006.286.03:34:14.90#ibcon#read 5, iclass 17, count 2 2006.286.03:34:14.90#ibcon#about to read 6, iclass 17, count 2 2006.286.03:34:14.90#ibcon#read 6, iclass 17, count 2 2006.286.03:34:14.90#ibcon#end of sib2, iclass 17, count 2 2006.286.03:34:14.90#ibcon#*mode == 0, iclass 17, count 2 2006.286.03:34:14.90#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.03:34:14.90#ibcon#[25=AT06-04\r\n] 2006.286.03:34:14.90#ibcon#*before write, iclass 17, count 2 2006.286.03:34:14.90#ibcon#enter sib2, iclass 17, count 2 2006.286.03:34:14.90#ibcon#flushed, iclass 17, count 2 2006.286.03:34:14.90#ibcon#about to write, iclass 17, count 2 2006.286.03:34:14.90#ibcon#wrote, iclass 17, count 2 2006.286.03:34:14.90#ibcon#about to read 3, iclass 17, count 2 2006.286.03:34:14.93#ibcon#read 3, iclass 17, count 2 2006.286.03:34:14.93#ibcon#about to read 4, iclass 17, count 2 2006.286.03:34:14.93#ibcon#read 4, iclass 17, count 2 2006.286.03:34:14.93#ibcon#about to read 5, iclass 17, count 2 2006.286.03:34:14.93#ibcon#read 5, iclass 17, count 2 2006.286.03:34:14.93#ibcon#about to read 6, iclass 17, count 2 2006.286.03:34:14.93#ibcon#read 6, iclass 17, count 2 2006.286.03:34:14.93#ibcon#end of sib2, iclass 17, count 2 2006.286.03:34:14.93#ibcon#*after write, iclass 17, count 2 2006.286.03:34:14.93#ibcon#*before return 0, iclass 17, count 2 2006.286.03:34:14.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:34:14.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:34:14.93#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.03:34:14.93#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:14.93#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:34:15.05#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:34:15.05#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:34:15.05#ibcon#enter wrdev, iclass 17, count 0 2006.286.03:34:15.05#ibcon#first serial, iclass 17, count 0 2006.286.03:34:15.05#ibcon#enter sib2, iclass 17, count 0 2006.286.03:34:15.05#ibcon#flushed, iclass 17, count 0 2006.286.03:34:15.05#ibcon#about to write, iclass 17, count 0 2006.286.03:34:15.05#ibcon#wrote, iclass 17, count 0 2006.286.03:34:15.05#ibcon#about to read 3, iclass 17, count 0 2006.286.03:34:15.07#ibcon#read 3, iclass 17, count 0 2006.286.03:34:15.07#ibcon#about to read 4, iclass 17, count 0 2006.286.03:34:15.07#ibcon#read 4, iclass 17, count 0 2006.286.03:34:15.07#ibcon#about to read 5, iclass 17, count 0 2006.286.03:34:15.07#ibcon#read 5, iclass 17, count 0 2006.286.03:34:15.07#ibcon#about to read 6, iclass 17, count 0 2006.286.03:34:15.07#ibcon#read 6, iclass 17, count 0 2006.286.03:34:15.07#ibcon#end of sib2, iclass 17, count 0 2006.286.03:34:15.07#ibcon#*mode == 0, iclass 17, count 0 2006.286.03:34:15.07#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.03:34:15.07#ibcon#[25=USB\r\n] 2006.286.03:34:15.07#ibcon#*before write, iclass 17, count 0 2006.286.03:34:15.07#ibcon#enter sib2, iclass 17, count 0 2006.286.03:34:15.07#ibcon#flushed, iclass 17, count 0 2006.286.03:34:15.07#ibcon#about to write, iclass 17, count 0 2006.286.03:34:15.07#ibcon#wrote, iclass 17, count 0 2006.286.03:34:15.07#ibcon#about to read 3, iclass 17, count 0 2006.286.03:34:15.10#ibcon#read 3, iclass 17, count 0 2006.286.03:34:15.10#ibcon#about to read 4, iclass 17, count 0 2006.286.03:34:15.10#ibcon#read 4, iclass 17, count 0 2006.286.03:34:15.10#ibcon#about to read 5, iclass 17, count 0 2006.286.03:34:15.10#ibcon#read 5, iclass 17, count 0 2006.286.03:34:15.10#ibcon#about to read 6, iclass 17, count 0 2006.286.03:34:15.10#ibcon#read 6, iclass 17, count 0 2006.286.03:34:15.10#ibcon#end of sib2, iclass 17, count 0 2006.286.03:34:15.10#ibcon#*after write, iclass 17, count 0 2006.286.03:34:15.10#ibcon#*before return 0, iclass 17, count 0 2006.286.03:34:15.10#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:34:15.10#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:34:15.10#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.03:34:15.10#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.03:34:15.10$vck44/valo=7,864.99 2006.286.03:34:15.10#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.03:34:15.10#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.03:34:15.10#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:15.10#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:34:15.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:34:15.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:34:15.10#ibcon#enter wrdev, iclass 19, count 0 2006.286.03:34:15.10#ibcon#first serial, iclass 19, count 0 2006.286.03:34:15.10#ibcon#enter sib2, iclass 19, count 0 2006.286.03:34:15.10#ibcon#flushed, iclass 19, count 0 2006.286.03:34:15.10#ibcon#about to write, iclass 19, count 0 2006.286.03:34:15.10#ibcon#wrote, iclass 19, count 0 2006.286.03:34:15.10#ibcon#about to read 3, iclass 19, count 0 2006.286.03:34:15.12#ibcon#read 3, iclass 19, count 0 2006.286.03:34:15.12#ibcon#about to read 4, iclass 19, count 0 2006.286.03:34:15.12#ibcon#read 4, iclass 19, count 0 2006.286.03:34:15.12#ibcon#about to read 5, iclass 19, count 0 2006.286.03:34:15.12#ibcon#read 5, iclass 19, count 0 2006.286.03:34:15.12#ibcon#about to read 6, iclass 19, count 0 2006.286.03:34:15.12#ibcon#read 6, iclass 19, count 0 2006.286.03:34:15.12#ibcon#end of sib2, iclass 19, count 0 2006.286.03:34:15.12#ibcon#*mode == 0, iclass 19, count 0 2006.286.03:34:15.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.03:34:15.12#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.03:34:15.12#ibcon#*before write, iclass 19, count 0 2006.286.03:34:15.12#ibcon#enter sib2, iclass 19, count 0 2006.286.03:34:15.12#ibcon#flushed, iclass 19, count 0 2006.286.03:34:15.12#ibcon#about to write, iclass 19, count 0 2006.286.03:34:15.12#ibcon#wrote, iclass 19, count 0 2006.286.03:34:15.12#ibcon#about to read 3, iclass 19, count 0 2006.286.03:34:15.16#ibcon#read 3, iclass 19, count 0 2006.286.03:34:15.16#ibcon#about to read 4, iclass 19, count 0 2006.286.03:34:15.16#ibcon#read 4, iclass 19, count 0 2006.286.03:34:15.16#ibcon#about to read 5, iclass 19, count 0 2006.286.03:34:15.16#ibcon#read 5, iclass 19, count 0 2006.286.03:34:15.16#ibcon#about to read 6, iclass 19, count 0 2006.286.03:34:15.16#ibcon#read 6, iclass 19, count 0 2006.286.03:34:15.16#ibcon#end of sib2, iclass 19, count 0 2006.286.03:34:15.16#ibcon#*after write, iclass 19, count 0 2006.286.03:34:15.16#ibcon#*before return 0, iclass 19, count 0 2006.286.03:34:15.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:34:15.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:34:15.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.03:34:15.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.03:34:15.16$vck44/va=7,4 2006.286.03:34:15.16#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.03:34:15.16#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.03:34:15.16#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:15.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:34:15.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:34:15.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:34:15.22#ibcon#enter wrdev, iclass 21, count 2 2006.286.03:34:15.22#ibcon#first serial, iclass 21, count 2 2006.286.03:34:15.22#ibcon#enter sib2, iclass 21, count 2 2006.286.03:34:15.22#ibcon#flushed, iclass 21, count 2 2006.286.03:34:15.22#ibcon#about to write, iclass 21, count 2 2006.286.03:34:15.22#ibcon#wrote, iclass 21, count 2 2006.286.03:34:15.22#ibcon#about to read 3, iclass 21, count 2 2006.286.03:34:15.24#ibcon#read 3, iclass 21, count 2 2006.286.03:34:15.24#ibcon#about to read 4, iclass 21, count 2 2006.286.03:34:15.24#ibcon#read 4, iclass 21, count 2 2006.286.03:34:15.24#ibcon#about to read 5, iclass 21, count 2 2006.286.03:34:15.24#ibcon#read 5, iclass 21, count 2 2006.286.03:34:15.24#ibcon#about to read 6, iclass 21, count 2 2006.286.03:34:15.24#ibcon#read 6, iclass 21, count 2 2006.286.03:34:15.24#ibcon#end of sib2, iclass 21, count 2 2006.286.03:34:15.24#ibcon#*mode == 0, iclass 21, count 2 2006.286.03:34:15.24#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.03:34:15.24#ibcon#[25=AT07-04\r\n] 2006.286.03:34:15.24#ibcon#*before write, iclass 21, count 2 2006.286.03:34:15.24#ibcon#enter sib2, iclass 21, count 2 2006.286.03:34:15.24#ibcon#flushed, iclass 21, count 2 2006.286.03:34:15.24#ibcon#about to write, iclass 21, count 2 2006.286.03:34:15.24#ibcon#wrote, iclass 21, count 2 2006.286.03:34:15.24#ibcon#about to read 3, iclass 21, count 2 2006.286.03:34:15.27#ibcon#read 3, iclass 21, count 2 2006.286.03:34:15.27#ibcon#about to read 4, iclass 21, count 2 2006.286.03:34:15.27#ibcon#read 4, iclass 21, count 2 2006.286.03:34:15.27#ibcon#about to read 5, iclass 21, count 2 2006.286.03:34:15.27#ibcon#read 5, iclass 21, count 2 2006.286.03:34:15.27#ibcon#about to read 6, iclass 21, count 2 2006.286.03:34:15.27#ibcon#read 6, iclass 21, count 2 2006.286.03:34:15.27#ibcon#end of sib2, iclass 21, count 2 2006.286.03:34:15.27#ibcon#*after write, iclass 21, count 2 2006.286.03:34:15.27#ibcon#*before return 0, iclass 21, count 2 2006.286.03:34:15.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:34:15.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:34:15.27#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.03:34:15.27#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:15.27#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:34:15.39#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:34:15.39#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:34:15.39#ibcon#enter wrdev, iclass 21, count 0 2006.286.03:34:15.39#ibcon#first serial, iclass 21, count 0 2006.286.03:34:15.39#ibcon#enter sib2, iclass 21, count 0 2006.286.03:34:15.39#ibcon#flushed, iclass 21, count 0 2006.286.03:34:15.39#ibcon#about to write, iclass 21, count 0 2006.286.03:34:15.39#ibcon#wrote, iclass 21, count 0 2006.286.03:34:15.39#ibcon#about to read 3, iclass 21, count 0 2006.286.03:34:15.41#ibcon#read 3, iclass 21, count 0 2006.286.03:34:15.41#ibcon#about to read 4, iclass 21, count 0 2006.286.03:34:15.41#ibcon#read 4, iclass 21, count 0 2006.286.03:34:15.41#ibcon#about to read 5, iclass 21, count 0 2006.286.03:34:15.41#ibcon#read 5, iclass 21, count 0 2006.286.03:34:15.41#ibcon#about to read 6, iclass 21, count 0 2006.286.03:34:15.41#ibcon#read 6, iclass 21, count 0 2006.286.03:34:15.41#ibcon#end of sib2, iclass 21, count 0 2006.286.03:34:15.41#ibcon#*mode == 0, iclass 21, count 0 2006.286.03:34:15.41#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.03:34:15.41#ibcon#[25=USB\r\n] 2006.286.03:34:15.41#ibcon#*before write, iclass 21, count 0 2006.286.03:34:15.41#ibcon#enter sib2, iclass 21, count 0 2006.286.03:34:15.41#ibcon#flushed, iclass 21, count 0 2006.286.03:34:15.41#ibcon#about to write, iclass 21, count 0 2006.286.03:34:15.41#ibcon#wrote, iclass 21, count 0 2006.286.03:34:15.41#ibcon#about to read 3, iclass 21, count 0 2006.286.03:34:15.44#ibcon#read 3, iclass 21, count 0 2006.286.03:34:15.44#ibcon#about to read 4, iclass 21, count 0 2006.286.03:34:15.44#ibcon#read 4, iclass 21, count 0 2006.286.03:34:15.44#ibcon#about to read 5, iclass 21, count 0 2006.286.03:34:15.44#ibcon#read 5, iclass 21, count 0 2006.286.03:34:15.44#ibcon#about to read 6, iclass 21, count 0 2006.286.03:34:15.44#ibcon#read 6, iclass 21, count 0 2006.286.03:34:15.44#ibcon#end of sib2, iclass 21, count 0 2006.286.03:34:15.44#ibcon#*after write, iclass 21, count 0 2006.286.03:34:15.44#ibcon#*before return 0, iclass 21, count 0 2006.286.03:34:15.44#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:34:15.44#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:34:15.44#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.03:34:15.44#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.03:34:15.44$vck44/valo=8,884.99 2006.286.03:34:15.44#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.03:34:15.44#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.03:34:15.44#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:15.44#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:34:15.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:34:15.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:34:15.44#ibcon#enter wrdev, iclass 23, count 0 2006.286.03:34:15.44#ibcon#first serial, iclass 23, count 0 2006.286.03:34:15.44#ibcon#enter sib2, iclass 23, count 0 2006.286.03:34:15.44#ibcon#flushed, iclass 23, count 0 2006.286.03:34:15.44#ibcon#about to write, iclass 23, count 0 2006.286.03:34:15.44#ibcon#wrote, iclass 23, count 0 2006.286.03:34:15.44#ibcon#about to read 3, iclass 23, count 0 2006.286.03:34:15.46#ibcon#read 3, iclass 23, count 0 2006.286.03:34:15.46#ibcon#about to read 4, iclass 23, count 0 2006.286.03:34:15.46#ibcon#read 4, iclass 23, count 0 2006.286.03:34:15.46#ibcon#about to read 5, iclass 23, count 0 2006.286.03:34:15.46#ibcon#read 5, iclass 23, count 0 2006.286.03:34:15.46#ibcon#about to read 6, iclass 23, count 0 2006.286.03:34:15.46#ibcon#read 6, iclass 23, count 0 2006.286.03:34:15.46#ibcon#end of sib2, iclass 23, count 0 2006.286.03:34:15.46#ibcon#*mode == 0, iclass 23, count 0 2006.286.03:34:15.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.03:34:15.46#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.03:34:15.46#ibcon#*before write, iclass 23, count 0 2006.286.03:34:15.46#ibcon#enter sib2, iclass 23, count 0 2006.286.03:34:15.46#ibcon#flushed, iclass 23, count 0 2006.286.03:34:15.46#ibcon#about to write, iclass 23, count 0 2006.286.03:34:15.46#ibcon#wrote, iclass 23, count 0 2006.286.03:34:15.46#ibcon#about to read 3, iclass 23, count 0 2006.286.03:34:15.50#ibcon#read 3, iclass 23, count 0 2006.286.03:34:15.50#ibcon#about to read 4, iclass 23, count 0 2006.286.03:34:15.50#ibcon#read 4, iclass 23, count 0 2006.286.03:34:15.50#ibcon#about to read 5, iclass 23, count 0 2006.286.03:34:15.50#ibcon#read 5, iclass 23, count 0 2006.286.03:34:15.50#ibcon#about to read 6, iclass 23, count 0 2006.286.03:34:15.50#ibcon#read 6, iclass 23, count 0 2006.286.03:34:15.50#ibcon#end of sib2, iclass 23, count 0 2006.286.03:34:15.50#ibcon#*after write, iclass 23, count 0 2006.286.03:34:15.50#ibcon#*before return 0, iclass 23, count 0 2006.286.03:34:15.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:34:15.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:34:15.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.03:34:15.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.03:34:15.50$vck44/va=8,3 2006.286.03:34:15.66#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.03:34:15.66#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.03:34:15.66#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:15.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.03:34:15.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.03:34:15.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.03:34:15.66#ibcon#enter wrdev, iclass 25, count 2 2006.286.03:34:15.66#ibcon#first serial, iclass 25, count 2 2006.286.03:34:15.66#ibcon#enter sib2, iclass 25, count 2 2006.286.03:34:15.66#ibcon#flushed, iclass 25, count 2 2006.286.03:34:15.66#ibcon#about to write, iclass 25, count 2 2006.286.03:34:15.66#ibcon#wrote, iclass 25, count 2 2006.286.03:34:15.66#ibcon#about to read 3, iclass 25, count 2 2006.286.03:34:15.68#ibcon#read 3, iclass 25, count 2 2006.286.03:34:15.68#ibcon#about to read 4, iclass 25, count 2 2006.286.03:34:15.68#ibcon#read 4, iclass 25, count 2 2006.286.03:34:15.68#ibcon#about to read 5, iclass 25, count 2 2006.286.03:34:15.68#ibcon#read 5, iclass 25, count 2 2006.286.03:34:15.68#ibcon#about to read 6, iclass 25, count 2 2006.286.03:34:15.68#ibcon#read 6, iclass 25, count 2 2006.286.03:34:15.68#ibcon#end of sib2, iclass 25, count 2 2006.286.03:34:15.68#ibcon#*mode == 0, iclass 25, count 2 2006.286.03:34:15.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.03:34:15.68#ibcon#[25=AT08-03\r\n] 2006.286.03:34:15.68#ibcon#*before write, iclass 25, count 2 2006.286.03:34:15.68#ibcon#enter sib2, iclass 25, count 2 2006.286.03:34:15.68#ibcon#flushed, iclass 25, count 2 2006.286.03:34:15.68#ibcon#about to write, iclass 25, count 2 2006.286.03:34:15.68#ibcon#wrote, iclass 25, count 2 2006.286.03:34:15.68#ibcon#about to read 3, iclass 25, count 2 2006.286.03:34:15.71#ibcon#read 3, iclass 25, count 2 2006.286.03:34:15.71#ibcon#about to read 4, iclass 25, count 2 2006.286.03:34:15.71#ibcon#read 4, iclass 25, count 2 2006.286.03:34:15.71#ibcon#about to read 5, iclass 25, count 2 2006.286.03:34:15.71#ibcon#read 5, iclass 25, count 2 2006.286.03:34:15.71#ibcon#about to read 6, iclass 25, count 2 2006.286.03:34:15.71#ibcon#read 6, iclass 25, count 2 2006.286.03:34:15.71#ibcon#end of sib2, iclass 25, count 2 2006.286.03:34:15.71#ibcon#*after write, iclass 25, count 2 2006.286.03:34:15.71#ibcon#*before return 0, iclass 25, count 2 2006.286.03:34:15.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.03:34:15.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.03:34:15.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.03:34:15.71#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:15.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.03:34:15.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.03:34:15.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.03:34:15.83#ibcon#enter wrdev, iclass 25, count 0 2006.286.03:34:15.83#ibcon#first serial, iclass 25, count 0 2006.286.03:34:15.83#ibcon#enter sib2, iclass 25, count 0 2006.286.03:34:15.83#ibcon#flushed, iclass 25, count 0 2006.286.03:34:15.83#ibcon#about to write, iclass 25, count 0 2006.286.03:34:15.83#ibcon#wrote, iclass 25, count 0 2006.286.03:34:15.83#ibcon#about to read 3, iclass 25, count 0 2006.286.03:34:15.85#ibcon#read 3, iclass 25, count 0 2006.286.03:34:15.85#ibcon#about to read 4, iclass 25, count 0 2006.286.03:34:15.85#ibcon#read 4, iclass 25, count 0 2006.286.03:34:15.85#ibcon#about to read 5, iclass 25, count 0 2006.286.03:34:15.85#ibcon#read 5, iclass 25, count 0 2006.286.03:34:15.85#ibcon#about to read 6, iclass 25, count 0 2006.286.03:34:15.85#ibcon#read 6, iclass 25, count 0 2006.286.03:34:15.85#ibcon#end of sib2, iclass 25, count 0 2006.286.03:34:15.85#ibcon#*mode == 0, iclass 25, count 0 2006.286.03:34:15.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.03:34:15.85#ibcon#[25=USB\r\n] 2006.286.03:34:15.85#ibcon#*before write, iclass 25, count 0 2006.286.03:34:15.85#ibcon#enter sib2, iclass 25, count 0 2006.286.03:34:15.85#ibcon#flushed, iclass 25, count 0 2006.286.03:34:15.85#ibcon#about to write, iclass 25, count 0 2006.286.03:34:15.85#ibcon#wrote, iclass 25, count 0 2006.286.03:34:15.85#ibcon#about to read 3, iclass 25, count 0 2006.286.03:34:15.88#ibcon#read 3, iclass 25, count 0 2006.286.03:34:15.88#ibcon#about to read 4, iclass 25, count 0 2006.286.03:34:15.88#ibcon#read 4, iclass 25, count 0 2006.286.03:34:15.88#ibcon#about to read 5, iclass 25, count 0 2006.286.03:34:15.88#ibcon#read 5, iclass 25, count 0 2006.286.03:34:15.88#ibcon#about to read 6, iclass 25, count 0 2006.286.03:34:15.88#ibcon#read 6, iclass 25, count 0 2006.286.03:34:15.88#ibcon#end of sib2, iclass 25, count 0 2006.286.03:34:15.88#ibcon#*after write, iclass 25, count 0 2006.286.03:34:15.88#ibcon#*before return 0, iclass 25, count 0 2006.286.03:34:15.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.03:34:15.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.03:34:15.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.03:34:15.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.03:34:15.88$vck44/vblo=1,629.99 2006.286.03:34:15.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.03:34:15.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.03:34:15.88#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:15.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:34:15.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:34:15.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:34:15.88#ibcon#enter wrdev, iclass 27, count 0 2006.286.03:34:15.88#ibcon#first serial, iclass 27, count 0 2006.286.03:34:15.88#ibcon#enter sib2, iclass 27, count 0 2006.286.03:34:15.88#ibcon#flushed, iclass 27, count 0 2006.286.03:34:15.88#ibcon#about to write, iclass 27, count 0 2006.286.03:34:15.88#ibcon#wrote, iclass 27, count 0 2006.286.03:34:15.88#ibcon#about to read 3, iclass 27, count 0 2006.286.03:34:15.90#ibcon#read 3, iclass 27, count 0 2006.286.03:34:15.90#ibcon#about to read 4, iclass 27, count 0 2006.286.03:34:15.90#ibcon#read 4, iclass 27, count 0 2006.286.03:34:15.90#ibcon#about to read 5, iclass 27, count 0 2006.286.03:34:15.90#ibcon#read 5, iclass 27, count 0 2006.286.03:34:15.90#ibcon#about to read 6, iclass 27, count 0 2006.286.03:34:15.90#ibcon#read 6, iclass 27, count 0 2006.286.03:34:15.90#ibcon#end of sib2, iclass 27, count 0 2006.286.03:34:15.90#ibcon#*mode == 0, iclass 27, count 0 2006.286.03:34:15.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.03:34:15.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.03:34:15.90#ibcon#*before write, iclass 27, count 0 2006.286.03:34:15.90#ibcon#enter sib2, iclass 27, count 0 2006.286.03:34:15.90#ibcon#flushed, iclass 27, count 0 2006.286.03:34:15.90#ibcon#about to write, iclass 27, count 0 2006.286.03:34:15.90#ibcon#wrote, iclass 27, count 0 2006.286.03:34:15.90#ibcon#about to read 3, iclass 27, count 0 2006.286.03:34:15.94#ibcon#read 3, iclass 27, count 0 2006.286.03:34:15.94#ibcon#about to read 4, iclass 27, count 0 2006.286.03:34:15.94#ibcon#read 4, iclass 27, count 0 2006.286.03:34:15.94#ibcon#about to read 5, iclass 27, count 0 2006.286.03:34:15.94#ibcon#read 5, iclass 27, count 0 2006.286.03:34:15.94#ibcon#about to read 6, iclass 27, count 0 2006.286.03:34:15.94#ibcon#read 6, iclass 27, count 0 2006.286.03:34:15.94#ibcon#end of sib2, iclass 27, count 0 2006.286.03:34:15.94#ibcon#*after write, iclass 27, count 0 2006.286.03:34:15.94#ibcon#*before return 0, iclass 27, count 0 2006.286.03:34:15.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:34:15.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.03:34:15.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.03:34:15.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.03:34:15.94$vck44/vb=1,4 2006.286.03:34:15.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.03:34:15.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.03:34:15.94#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:15.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:34:15.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:34:15.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:34:15.94#ibcon#enter wrdev, iclass 29, count 2 2006.286.03:34:15.94#ibcon#first serial, iclass 29, count 2 2006.286.03:34:15.94#ibcon#enter sib2, iclass 29, count 2 2006.286.03:34:15.94#ibcon#flushed, iclass 29, count 2 2006.286.03:34:15.94#ibcon#about to write, iclass 29, count 2 2006.286.03:34:15.94#ibcon#wrote, iclass 29, count 2 2006.286.03:34:15.94#ibcon#about to read 3, iclass 29, count 2 2006.286.03:34:15.96#ibcon#read 3, iclass 29, count 2 2006.286.03:34:15.96#ibcon#about to read 4, iclass 29, count 2 2006.286.03:34:15.96#ibcon#read 4, iclass 29, count 2 2006.286.03:34:15.96#ibcon#about to read 5, iclass 29, count 2 2006.286.03:34:15.96#ibcon#read 5, iclass 29, count 2 2006.286.03:34:15.96#ibcon#about to read 6, iclass 29, count 2 2006.286.03:34:15.96#ibcon#read 6, iclass 29, count 2 2006.286.03:34:15.96#ibcon#end of sib2, iclass 29, count 2 2006.286.03:34:15.96#ibcon#*mode == 0, iclass 29, count 2 2006.286.03:34:15.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.03:34:15.96#ibcon#[27=AT01-04\r\n] 2006.286.03:34:15.96#ibcon#*before write, iclass 29, count 2 2006.286.03:34:15.96#ibcon#enter sib2, iclass 29, count 2 2006.286.03:34:15.96#ibcon#flushed, iclass 29, count 2 2006.286.03:34:15.96#ibcon#about to write, iclass 29, count 2 2006.286.03:34:15.96#ibcon#wrote, iclass 29, count 2 2006.286.03:34:15.96#ibcon#about to read 3, iclass 29, count 2 2006.286.03:34:15.99#ibcon#read 3, iclass 29, count 2 2006.286.03:34:15.99#ibcon#about to read 4, iclass 29, count 2 2006.286.03:34:15.99#ibcon#read 4, iclass 29, count 2 2006.286.03:34:15.99#ibcon#about to read 5, iclass 29, count 2 2006.286.03:34:15.99#ibcon#read 5, iclass 29, count 2 2006.286.03:34:15.99#ibcon#about to read 6, iclass 29, count 2 2006.286.03:34:15.99#ibcon#read 6, iclass 29, count 2 2006.286.03:34:15.99#ibcon#end of sib2, iclass 29, count 2 2006.286.03:34:15.99#ibcon#*after write, iclass 29, count 2 2006.286.03:34:15.99#ibcon#*before return 0, iclass 29, count 2 2006.286.03:34:15.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:34:15.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.03:34:15.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.03:34:15.99#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:15.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:34:16.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:34:16.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:34:16.11#ibcon#enter wrdev, iclass 29, count 0 2006.286.03:34:16.11#ibcon#first serial, iclass 29, count 0 2006.286.03:34:16.11#ibcon#enter sib2, iclass 29, count 0 2006.286.03:34:16.11#ibcon#flushed, iclass 29, count 0 2006.286.03:34:16.11#ibcon#about to write, iclass 29, count 0 2006.286.03:34:16.11#ibcon#wrote, iclass 29, count 0 2006.286.03:34:16.11#ibcon#about to read 3, iclass 29, count 0 2006.286.03:34:16.13#ibcon#read 3, iclass 29, count 0 2006.286.03:34:16.13#ibcon#about to read 4, iclass 29, count 0 2006.286.03:34:16.13#ibcon#read 4, iclass 29, count 0 2006.286.03:34:16.13#ibcon#about to read 5, iclass 29, count 0 2006.286.03:34:16.13#ibcon#read 5, iclass 29, count 0 2006.286.03:34:16.13#ibcon#about to read 6, iclass 29, count 0 2006.286.03:34:16.13#ibcon#read 6, iclass 29, count 0 2006.286.03:34:16.13#ibcon#end of sib2, iclass 29, count 0 2006.286.03:34:16.13#ibcon#*mode == 0, iclass 29, count 0 2006.286.03:34:16.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.03:34:16.13#ibcon#[27=USB\r\n] 2006.286.03:34:16.13#ibcon#*before write, iclass 29, count 0 2006.286.03:34:16.13#ibcon#enter sib2, iclass 29, count 0 2006.286.03:34:16.13#ibcon#flushed, iclass 29, count 0 2006.286.03:34:16.13#ibcon#about to write, iclass 29, count 0 2006.286.03:34:16.13#ibcon#wrote, iclass 29, count 0 2006.286.03:34:16.13#ibcon#about to read 3, iclass 29, count 0 2006.286.03:34:16.16#ibcon#read 3, iclass 29, count 0 2006.286.03:34:16.16#ibcon#about to read 4, iclass 29, count 0 2006.286.03:34:16.16#ibcon#read 4, iclass 29, count 0 2006.286.03:34:16.16#ibcon#about to read 5, iclass 29, count 0 2006.286.03:34:16.16#ibcon#read 5, iclass 29, count 0 2006.286.03:34:16.16#ibcon#about to read 6, iclass 29, count 0 2006.286.03:34:16.16#ibcon#read 6, iclass 29, count 0 2006.286.03:34:16.16#ibcon#end of sib2, iclass 29, count 0 2006.286.03:34:16.16#ibcon#*after write, iclass 29, count 0 2006.286.03:34:16.16#ibcon#*before return 0, iclass 29, count 0 2006.286.03:34:16.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:34:16.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.03:34:16.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.03:34:16.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.03:34:16.16$vck44/vblo=2,634.99 2006.286.03:34:16.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.03:34:16.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.03:34:16.16#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:16.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:34:16.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:34:16.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:34:16.16#ibcon#enter wrdev, iclass 31, count 0 2006.286.03:34:16.16#ibcon#first serial, iclass 31, count 0 2006.286.03:34:16.16#ibcon#enter sib2, iclass 31, count 0 2006.286.03:34:16.16#ibcon#flushed, iclass 31, count 0 2006.286.03:34:16.16#ibcon#about to write, iclass 31, count 0 2006.286.03:34:16.16#ibcon#wrote, iclass 31, count 0 2006.286.03:34:16.16#ibcon#about to read 3, iclass 31, count 0 2006.286.03:34:16.18#ibcon#read 3, iclass 31, count 0 2006.286.03:34:16.18#ibcon#about to read 4, iclass 31, count 0 2006.286.03:34:16.18#ibcon#read 4, iclass 31, count 0 2006.286.03:34:16.18#ibcon#about to read 5, iclass 31, count 0 2006.286.03:34:16.18#ibcon#read 5, iclass 31, count 0 2006.286.03:34:16.18#ibcon#about to read 6, iclass 31, count 0 2006.286.03:34:16.18#ibcon#read 6, iclass 31, count 0 2006.286.03:34:16.18#ibcon#end of sib2, iclass 31, count 0 2006.286.03:34:16.18#ibcon#*mode == 0, iclass 31, count 0 2006.286.03:34:16.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.03:34:16.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.03:34:16.18#ibcon#*before write, iclass 31, count 0 2006.286.03:34:16.18#ibcon#enter sib2, iclass 31, count 0 2006.286.03:34:16.18#ibcon#flushed, iclass 31, count 0 2006.286.03:34:16.18#ibcon#about to write, iclass 31, count 0 2006.286.03:34:16.18#ibcon#wrote, iclass 31, count 0 2006.286.03:34:16.18#ibcon#about to read 3, iclass 31, count 0 2006.286.03:34:16.22#ibcon#read 3, iclass 31, count 0 2006.286.03:34:16.22#ibcon#about to read 4, iclass 31, count 0 2006.286.03:34:16.22#ibcon#read 4, iclass 31, count 0 2006.286.03:34:16.22#ibcon#about to read 5, iclass 31, count 0 2006.286.03:34:16.22#ibcon#read 5, iclass 31, count 0 2006.286.03:34:16.22#ibcon#about to read 6, iclass 31, count 0 2006.286.03:34:16.22#ibcon#read 6, iclass 31, count 0 2006.286.03:34:16.22#ibcon#end of sib2, iclass 31, count 0 2006.286.03:34:16.22#ibcon#*after write, iclass 31, count 0 2006.286.03:34:16.22#ibcon#*before return 0, iclass 31, count 0 2006.286.03:34:16.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:34:16.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.03:34:16.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.03:34:16.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.03:34:16.22$vck44/vb=2,5 2006.286.03:34:16.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.03:34:16.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.03:34:16.22#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:16.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:34:16.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:34:16.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:34:16.28#ibcon#enter wrdev, iclass 33, count 2 2006.286.03:34:16.28#ibcon#first serial, iclass 33, count 2 2006.286.03:34:16.28#ibcon#enter sib2, iclass 33, count 2 2006.286.03:34:16.28#ibcon#flushed, iclass 33, count 2 2006.286.03:34:16.28#ibcon#about to write, iclass 33, count 2 2006.286.03:34:16.28#ibcon#wrote, iclass 33, count 2 2006.286.03:34:16.28#ibcon#about to read 3, iclass 33, count 2 2006.286.03:34:16.30#ibcon#read 3, iclass 33, count 2 2006.286.03:34:16.30#ibcon#about to read 4, iclass 33, count 2 2006.286.03:34:16.30#ibcon#read 4, iclass 33, count 2 2006.286.03:34:16.30#ibcon#about to read 5, iclass 33, count 2 2006.286.03:34:16.30#ibcon#read 5, iclass 33, count 2 2006.286.03:34:16.30#ibcon#about to read 6, iclass 33, count 2 2006.286.03:34:16.30#ibcon#read 6, iclass 33, count 2 2006.286.03:34:16.30#ibcon#end of sib2, iclass 33, count 2 2006.286.03:34:16.30#ibcon#*mode == 0, iclass 33, count 2 2006.286.03:34:16.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.03:34:16.30#ibcon#[27=AT02-05\r\n] 2006.286.03:34:16.30#ibcon#*before write, iclass 33, count 2 2006.286.03:34:16.30#ibcon#enter sib2, iclass 33, count 2 2006.286.03:34:16.30#ibcon#flushed, iclass 33, count 2 2006.286.03:34:16.30#ibcon#about to write, iclass 33, count 2 2006.286.03:34:16.30#ibcon#wrote, iclass 33, count 2 2006.286.03:34:16.30#ibcon#about to read 3, iclass 33, count 2 2006.286.03:34:16.33#ibcon#read 3, iclass 33, count 2 2006.286.03:34:16.33#ibcon#about to read 4, iclass 33, count 2 2006.286.03:34:16.33#ibcon#read 4, iclass 33, count 2 2006.286.03:34:16.33#ibcon#about to read 5, iclass 33, count 2 2006.286.03:34:16.33#ibcon#read 5, iclass 33, count 2 2006.286.03:34:16.33#ibcon#about to read 6, iclass 33, count 2 2006.286.03:34:16.33#ibcon#read 6, iclass 33, count 2 2006.286.03:34:16.33#ibcon#end of sib2, iclass 33, count 2 2006.286.03:34:16.33#ibcon#*after write, iclass 33, count 2 2006.286.03:34:16.33#ibcon#*before return 0, iclass 33, count 2 2006.286.03:34:16.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:34:16.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.03:34:16.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.03:34:16.33#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:16.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:34:16.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:34:16.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:34:16.45#ibcon#enter wrdev, iclass 33, count 0 2006.286.03:34:16.45#ibcon#first serial, iclass 33, count 0 2006.286.03:34:16.45#ibcon#enter sib2, iclass 33, count 0 2006.286.03:34:16.45#ibcon#flushed, iclass 33, count 0 2006.286.03:34:16.45#ibcon#about to write, iclass 33, count 0 2006.286.03:34:16.45#ibcon#wrote, iclass 33, count 0 2006.286.03:34:16.45#ibcon#about to read 3, iclass 33, count 0 2006.286.03:34:16.47#ibcon#read 3, iclass 33, count 0 2006.286.03:34:16.47#ibcon#about to read 4, iclass 33, count 0 2006.286.03:34:16.47#ibcon#read 4, iclass 33, count 0 2006.286.03:34:16.47#ibcon#about to read 5, iclass 33, count 0 2006.286.03:34:16.47#ibcon#read 5, iclass 33, count 0 2006.286.03:34:16.47#ibcon#about to read 6, iclass 33, count 0 2006.286.03:34:16.47#ibcon#read 6, iclass 33, count 0 2006.286.03:34:16.47#ibcon#end of sib2, iclass 33, count 0 2006.286.03:34:16.47#ibcon#*mode == 0, iclass 33, count 0 2006.286.03:34:16.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.03:34:16.47#ibcon#[27=USB\r\n] 2006.286.03:34:16.47#ibcon#*before write, iclass 33, count 0 2006.286.03:34:16.47#ibcon#enter sib2, iclass 33, count 0 2006.286.03:34:16.47#ibcon#flushed, iclass 33, count 0 2006.286.03:34:16.47#ibcon#about to write, iclass 33, count 0 2006.286.03:34:16.47#ibcon#wrote, iclass 33, count 0 2006.286.03:34:16.47#ibcon#about to read 3, iclass 33, count 0 2006.286.03:34:16.50#ibcon#read 3, iclass 33, count 0 2006.286.03:34:16.50#ibcon#about to read 4, iclass 33, count 0 2006.286.03:34:16.50#ibcon#read 4, iclass 33, count 0 2006.286.03:34:16.50#ibcon#about to read 5, iclass 33, count 0 2006.286.03:34:16.50#ibcon#read 5, iclass 33, count 0 2006.286.03:34:16.50#ibcon#about to read 6, iclass 33, count 0 2006.286.03:34:16.50#ibcon#read 6, iclass 33, count 0 2006.286.03:34:16.50#ibcon#end of sib2, iclass 33, count 0 2006.286.03:34:16.50#ibcon#*after write, iclass 33, count 0 2006.286.03:34:16.50#ibcon#*before return 0, iclass 33, count 0 2006.286.03:34:16.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:34:16.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.03:34:16.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.03:34:16.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.03:34:16.50$vck44/vblo=3,649.99 2006.286.03:34:16.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.03:34:16.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.03:34:16.50#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:16.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:34:16.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:34:16.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:34:16.50#ibcon#enter wrdev, iclass 35, count 0 2006.286.03:34:16.50#ibcon#first serial, iclass 35, count 0 2006.286.03:34:16.50#ibcon#enter sib2, iclass 35, count 0 2006.286.03:34:16.50#ibcon#flushed, iclass 35, count 0 2006.286.03:34:16.50#ibcon#about to write, iclass 35, count 0 2006.286.03:34:16.50#ibcon#wrote, iclass 35, count 0 2006.286.03:34:16.50#ibcon#about to read 3, iclass 35, count 0 2006.286.03:34:16.52#ibcon#read 3, iclass 35, count 0 2006.286.03:34:16.78#ibcon#about to read 4, iclass 35, count 0 2006.286.03:34:16.78#ibcon#read 4, iclass 35, count 0 2006.286.03:34:16.78#ibcon#about to read 5, iclass 35, count 0 2006.286.03:34:16.78#ibcon#read 5, iclass 35, count 0 2006.286.03:34:16.78#ibcon#about to read 6, iclass 35, count 0 2006.286.03:34:16.78#ibcon#read 6, iclass 35, count 0 2006.286.03:34:16.78#ibcon#end of sib2, iclass 35, count 0 2006.286.03:34:16.78#ibcon#*mode == 0, iclass 35, count 0 2006.286.03:34:16.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.03:34:16.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.03:34:16.78#ibcon#*before write, iclass 35, count 0 2006.286.03:34:16.78#ibcon#enter sib2, iclass 35, count 0 2006.286.03:34:16.78#ibcon#flushed, iclass 35, count 0 2006.286.03:34:16.78#ibcon#about to write, iclass 35, count 0 2006.286.03:34:16.78#ibcon#wrote, iclass 35, count 0 2006.286.03:34:16.78#ibcon#about to read 3, iclass 35, count 0 2006.286.03:34:16.82#ibcon#read 3, iclass 35, count 0 2006.286.03:34:16.82#ibcon#about to read 4, iclass 35, count 0 2006.286.03:34:16.82#ibcon#read 4, iclass 35, count 0 2006.286.03:34:16.82#ibcon#about to read 5, iclass 35, count 0 2006.286.03:34:16.82#ibcon#read 5, iclass 35, count 0 2006.286.03:34:16.82#ibcon#about to read 6, iclass 35, count 0 2006.286.03:34:16.82#ibcon#read 6, iclass 35, count 0 2006.286.03:34:16.82#ibcon#end of sib2, iclass 35, count 0 2006.286.03:34:16.82#ibcon#*after write, iclass 35, count 0 2006.286.03:34:16.82#ibcon#*before return 0, iclass 35, count 0 2006.286.03:34:16.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:34:16.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.03:34:16.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.03:34:16.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.03:34:16.82$vck44/vb=3,4 2006.286.03:34:16.82#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.03:34:16.82#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.03:34:16.82#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:16.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:34:16.82#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:34:16.82#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:34:16.82#ibcon#enter wrdev, iclass 37, count 2 2006.286.03:34:16.82#ibcon#first serial, iclass 37, count 2 2006.286.03:34:16.82#ibcon#enter sib2, iclass 37, count 2 2006.286.03:34:16.82#ibcon#flushed, iclass 37, count 2 2006.286.03:34:16.82#ibcon#about to write, iclass 37, count 2 2006.286.03:34:16.82#ibcon#wrote, iclass 37, count 2 2006.286.03:34:16.82#ibcon#about to read 3, iclass 37, count 2 2006.286.03:34:16.84#ibcon#read 3, iclass 37, count 2 2006.286.03:34:16.84#ibcon#about to read 4, iclass 37, count 2 2006.286.03:34:16.84#ibcon#read 4, iclass 37, count 2 2006.286.03:34:16.84#ibcon#about to read 5, iclass 37, count 2 2006.286.03:34:16.84#ibcon#read 5, iclass 37, count 2 2006.286.03:34:16.84#ibcon#about to read 6, iclass 37, count 2 2006.286.03:34:16.84#ibcon#read 6, iclass 37, count 2 2006.286.03:34:16.84#ibcon#end of sib2, iclass 37, count 2 2006.286.03:34:16.84#ibcon#*mode == 0, iclass 37, count 2 2006.286.03:34:16.84#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.03:34:16.84#ibcon#[27=AT03-04\r\n] 2006.286.03:34:16.84#ibcon#*before write, iclass 37, count 2 2006.286.03:34:16.84#ibcon#enter sib2, iclass 37, count 2 2006.286.03:34:16.84#ibcon#flushed, iclass 37, count 2 2006.286.03:34:16.84#ibcon#about to write, iclass 37, count 2 2006.286.03:34:16.84#ibcon#wrote, iclass 37, count 2 2006.286.03:34:16.84#ibcon#about to read 3, iclass 37, count 2 2006.286.03:34:16.87#ibcon#read 3, iclass 37, count 2 2006.286.03:34:16.87#ibcon#about to read 4, iclass 37, count 2 2006.286.03:34:16.87#ibcon#read 4, iclass 37, count 2 2006.286.03:34:16.87#ibcon#about to read 5, iclass 37, count 2 2006.286.03:34:16.87#ibcon#read 5, iclass 37, count 2 2006.286.03:34:16.87#ibcon#about to read 6, iclass 37, count 2 2006.286.03:34:16.87#ibcon#read 6, iclass 37, count 2 2006.286.03:34:16.87#ibcon#end of sib2, iclass 37, count 2 2006.286.03:34:16.87#ibcon#*after write, iclass 37, count 2 2006.286.03:34:16.87#ibcon#*before return 0, iclass 37, count 2 2006.286.03:34:16.87#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:34:16.87#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.03:34:16.87#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.03:34:16.87#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:16.87#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:34:16.99#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:34:16.99#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:34:16.99#ibcon#enter wrdev, iclass 37, count 0 2006.286.03:34:16.99#ibcon#first serial, iclass 37, count 0 2006.286.03:34:16.99#ibcon#enter sib2, iclass 37, count 0 2006.286.03:34:16.99#ibcon#flushed, iclass 37, count 0 2006.286.03:34:16.99#ibcon#about to write, iclass 37, count 0 2006.286.03:34:16.99#ibcon#wrote, iclass 37, count 0 2006.286.03:34:16.99#ibcon#about to read 3, iclass 37, count 0 2006.286.03:34:17.01#ibcon#read 3, iclass 37, count 0 2006.286.03:34:17.01#ibcon#about to read 4, iclass 37, count 0 2006.286.03:34:17.01#ibcon#read 4, iclass 37, count 0 2006.286.03:34:17.01#ibcon#about to read 5, iclass 37, count 0 2006.286.03:34:17.01#ibcon#read 5, iclass 37, count 0 2006.286.03:34:17.01#ibcon#about to read 6, iclass 37, count 0 2006.286.03:34:17.01#ibcon#read 6, iclass 37, count 0 2006.286.03:34:17.01#ibcon#end of sib2, iclass 37, count 0 2006.286.03:34:17.01#ibcon#*mode == 0, iclass 37, count 0 2006.286.03:34:17.01#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.03:34:17.01#ibcon#[27=USB\r\n] 2006.286.03:34:17.01#ibcon#*before write, iclass 37, count 0 2006.286.03:34:17.01#ibcon#enter sib2, iclass 37, count 0 2006.286.03:34:17.01#ibcon#flushed, iclass 37, count 0 2006.286.03:34:17.01#ibcon#about to write, iclass 37, count 0 2006.286.03:34:17.01#ibcon#wrote, iclass 37, count 0 2006.286.03:34:17.01#ibcon#about to read 3, iclass 37, count 0 2006.286.03:34:17.04#ibcon#read 3, iclass 37, count 0 2006.286.03:34:17.04#ibcon#about to read 4, iclass 37, count 0 2006.286.03:34:17.04#ibcon#read 4, iclass 37, count 0 2006.286.03:34:17.04#ibcon#about to read 5, iclass 37, count 0 2006.286.03:34:17.04#ibcon#read 5, iclass 37, count 0 2006.286.03:34:17.04#ibcon#about to read 6, iclass 37, count 0 2006.286.03:34:17.04#ibcon#read 6, iclass 37, count 0 2006.286.03:34:17.04#ibcon#end of sib2, iclass 37, count 0 2006.286.03:34:17.04#ibcon#*after write, iclass 37, count 0 2006.286.03:34:17.04#ibcon#*before return 0, iclass 37, count 0 2006.286.03:34:17.04#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:34:17.04#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.03:34:17.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.03:34:17.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.03:34:17.04$vck44/vblo=4,679.99 2006.286.03:34:17.04#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.03:34:17.04#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.03:34:17.04#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:17.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:34:17.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:34:17.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:34:17.04#ibcon#enter wrdev, iclass 39, count 0 2006.286.03:34:17.04#ibcon#first serial, iclass 39, count 0 2006.286.03:34:17.04#ibcon#enter sib2, iclass 39, count 0 2006.286.03:34:17.04#ibcon#flushed, iclass 39, count 0 2006.286.03:34:17.04#ibcon#about to write, iclass 39, count 0 2006.286.03:34:17.04#ibcon#wrote, iclass 39, count 0 2006.286.03:34:17.04#ibcon#about to read 3, iclass 39, count 0 2006.286.03:34:17.06#ibcon#read 3, iclass 39, count 0 2006.286.03:34:17.06#ibcon#about to read 4, iclass 39, count 0 2006.286.03:34:17.06#ibcon#read 4, iclass 39, count 0 2006.286.03:34:17.06#ibcon#about to read 5, iclass 39, count 0 2006.286.03:34:17.06#ibcon#read 5, iclass 39, count 0 2006.286.03:34:17.06#ibcon#about to read 6, iclass 39, count 0 2006.286.03:34:17.06#ibcon#read 6, iclass 39, count 0 2006.286.03:34:17.06#ibcon#end of sib2, iclass 39, count 0 2006.286.03:34:17.06#ibcon#*mode == 0, iclass 39, count 0 2006.286.03:34:17.06#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.03:34:17.06#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.03:34:17.06#ibcon#*before write, iclass 39, count 0 2006.286.03:34:17.06#ibcon#enter sib2, iclass 39, count 0 2006.286.03:34:17.06#ibcon#flushed, iclass 39, count 0 2006.286.03:34:17.06#ibcon#about to write, iclass 39, count 0 2006.286.03:34:17.06#ibcon#wrote, iclass 39, count 0 2006.286.03:34:17.06#ibcon#about to read 3, iclass 39, count 0 2006.286.03:34:17.10#ibcon#read 3, iclass 39, count 0 2006.286.03:34:17.10#ibcon#about to read 4, iclass 39, count 0 2006.286.03:34:17.10#ibcon#read 4, iclass 39, count 0 2006.286.03:34:17.10#ibcon#about to read 5, iclass 39, count 0 2006.286.03:34:17.10#ibcon#read 5, iclass 39, count 0 2006.286.03:34:17.10#ibcon#about to read 6, iclass 39, count 0 2006.286.03:34:17.10#ibcon#read 6, iclass 39, count 0 2006.286.03:34:17.10#ibcon#end of sib2, iclass 39, count 0 2006.286.03:34:17.10#ibcon#*after write, iclass 39, count 0 2006.286.03:34:17.10#ibcon#*before return 0, iclass 39, count 0 2006.286.03:34:17.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:34:17.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.03:34:17.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.03:34:17.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.03:34:17.10$vck44/vb=4,5 2006.286.03:34:17.10#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.03:34:17.10#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.03:34:17.10#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:17.10#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:34:17.16#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:34:17.16#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:34:17.16#ibcon#enter wrdev, iclass 3, count 2 2006.286.03:34:17.16#ibcon#first serial, iclass 3, count 2 2006.286.03:34:17.16#ibcon#enter sib2, iclass 3, count 2 2006.286.03:34:17.16#ibcon#flushed, iclass 3, count 2 2006.286.03:34:17.16#ibcon#about to write, iclass 3, count 2 2006.286.03:34:17.16#ibcon#wrote, iclass 3, count 2 2006.286.03:34:17.16#ibcon#about to read 3, iclass 3, count 2 2006.286.03:34:17.18#ibcon#read 3, iclass 3, count 2 2006.286.03:34:17.18#ibcon#about to read 4, iclass 3, count 2 2006.286.03:34:17.18#ibcon#read 4, iclass 3, count 2 2006.286.03:34:17.18#ibcon#about to read 5, iclass 3, count 2 2006.286.03:34:17.18#ibcon#read 5, iclass 3, count 2 2006.286.03:34:17.18#ibcon#about to read 6, iclass 3, count 2 2006.286.03:34:17.18#ibcon#read 6, iclass 3, count 2 2006.286.03:34:17.18#ibcon#end of sib2, iclass 3, count 2 2006.286.03:34:17.18#ibcon#*mode == 0, iclass 3, count 2 2006.286.03:34:17.18#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.03:34:17.18#ibcon#[27=AT04-05\r\n] 2006.286.03:34:17.18#ibcon#*before write, iclass 3, count 2 2006.286.03:34:17.18#ibcon#enter sib2, iclass 3, count 2 2006.286.03:34:17.18#ibcon#flushed, iclass 3, count 2 2006.286.03:34:17.18#ibcon#about to write, iclass 3, count 2 2006.286.03:34:17.18#ibcon#wrote, iclass 3, count 2 2006.286.03:34:17.18#ibcon#about to read 3, iclass 3, count 2 2006.286.03:34:17.21#ibcon#read 3, iclass 3, count 2 2006.286.03:34:17.21#ibcon#about to read 4, iclass 3, count 2 2006.286.03:34:17.21#ibcon#read 4, iclass 3, count 2 2006.286.03:34:17.21#ibcon#about to read 5, iclass 3, count 2 2006.286.03:34:17.21#ibcon#read 5, iclass 3, count 2 2006.286.03:34:17.21#ibcon#about to read 6, iclass 3, count 2 2006.286.03:34:17.21#ibcon#read 6, iclass 3, count 2 2006.286.03:34:17.21#ibcon#end of sib2, iclass 3, count 2 2006.286.03:34:17.21#ibcon#*after write, iclass 3, count 2 2006.286.03:34:17.21#ibcon#*before return 0, iclass 3, count 2 2006.286.03:34:17.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:34:17.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.03:34:17.21#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.03:34:17.21#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:17.21#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:34:17.33#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:34:17.33#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:34:17.33#ibcon#enter wrdev, iclass 3, count 0 2006.286.03:34:17.33#ibcon#first serial, iclass 3, count 0 2006.286.03:34:17.33#ibcon#enter sib2, iclass 3, count 0 2006.286.03:34:17.33#ibcon#flushed, iclass 3, count 0 2006.286.03:34:17.33#ibcon#about to write, iclass 3, count 0 2006.286.03:34:17.33#ibcon#wrote, iclass 3, count 0 2006.286.03:34:17.33#ibcon#about to read 3, iclass 3, count 0 2006.286.03:34:17.35#ibcon#read 3, iclass 3, count 0 2006.286.03:34:17.35#ibcon#about to read 4, iclass 3, count 0 2006.286.03:34:17.35#ibcon#read 4, iclass 3, count 0 2006.286.03:34:17.35#ibcon#about to read 5, iclass 3, count 0 2006.286.03:34:17.35#ibcon#read 5, iclass 3, count 0 2006.286.03:34:17.35#ibcon#about to read 6, iclass 3, count 0 2006.286.03:34:17.35#ibcon#read 6, iclass 3, count 0 2006.286.03:34:17.35#ibcon#end of sib2, iclass 3, count 0 2006.286.03:34:17.35#ibcon#*mode == 0, iclass 3, count 0 2006.286.03:34:17.35#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.03:34:17.35#ibcon#[27=USB\r\n] 2006.286.03:34:17.35#ibcon#*before write, iclass 3, count 0 2006.286.03:34:17.35#ibcon#enter sib2, iclass 3, count 0 2006.286.03:34:17.35#ibcon#flushed, iclass 3, count 0 2006.286.03:34:17.35#ibcon#about to write, iclass 3, count 0 2006.286.03:34:17.35#ibcon#wrote, iclass 3, count 0 2006.286.03:34:17.35#ibcon#about to read 3, iclass 3, count 0 2006.286.03:34:17.38#ibcon#read 3, iclass 3, count 0 2006.286.03:34:17.38#ibcon#about to read 4, iclass 3, count 0 2006.286.03:34:17.38#ibcon#read 4, iclass 3, count 0 2006.286.03:34:17.38#ibcon#about to read 5, iclass 3, count 0 2006.286.03:34:17.38#ibcon#read 5, iclass 3, count 0 2006.286.03:34:17.38#ibcon#about to read 6, iclass 3, count 0 2006.286.03:34:17.38#ibcon#read 6, iclass 3, count 0 2006.286.03:34:17.38#ibcon#end of sib2, iclass 3, count 0 2006.286.03:34:17.38#ibcon#*after write, iclass 3, count 0 2006.286.03:34:17.38#ibcon#*before return 0, iclass 3, count 0 2006.286.03:34:17.38#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:34:17.38#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.03:34:17.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.03:34:17.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.03:34:17.38$vck44/vblo=5,709.99 2006.286.03:34:17.38#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.03:34:17.38#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.03:34:17.38#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:17.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:34:17.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:34:17.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:34:17.38#ibcon#enter wrdev, iclass 5, count 0 2006.286.03:34:17.38#ibcon#first serial, iclass 5, count 0 2006.286.03:34:17.38#ibcon#enter sib2, iclass 5, count 0 2006.286.03:34:17.38#ibcon#flushed, iclass 5, count 0 2006.286.03:34:17.38#ibcon#about to write, iclass 5, count 0 2006.286.03:34:17.38#ibcon#wrote, iclass 5, count 0 2006.286.03:34:17.38#ibcon#about to read 3, iclass 5, count 0 2006.286.03:34:17.40#ibcon#read 3, iclass 5, count 0 2006.286.03:34:17.40#ibcon#about to read 4, iclass 5, count 0 2006.286.03:34:17.40#ibcon#read 4, iclass 5, count 0 2006.286.03:34:17.40#ibcon#about to read 5, iclass 5, count 0 2006.286.03:34:17.40#ibcon#read 5, iclass 5, count 0 2006.286.03:34:17.40#ibcon#about to read 6, iclass 5, count 0 2006.286.03:34:17.40#ibcon#read 6, iclass 5, count 0 2006.286.03:34:17.40#ibcon#end of sib2, iclass 5, count 0 2006.286.03:34:17.40#ibcon#*mode == 0, iclass 5, count 0 2006.286.03:34:17.40#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.03:34:17.40#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.03:34:17.40#ibcon#*before write, iclass 5, count 0 2006.286.03:34:17.40#ibcon#enter sib2, iclass 5, count 0 2006.286.03:34:17.40#ibcon#flushed, iclass 5, count 0 2006.286.03:34:17.40#ibcon#about to write, iclass 5, count 0 2006.286.03:34:17.40#ibcon#wrote, iclass 5, count 0 2006.286.03:34:17.40#ibcon#about to read 3, iclass 5, count 0 2006.286.03:34:17.44#ibcon#read 3, iclass 5, count 0 2006.286.03:34:17.44#ibcon#about to read 4, iclass 5, count 0 2006.286.03:34:17.44#ibcon#read 4, iclass 5, count 0 2006.286.03:34:17.44#ibcon#about to read 5, iclass 5, count 0 2006.286.03:34:17.44#ibcon#read 5, iclass 5, count 0 2006.286.03:34:17.44#ibcon#about to read 6, iclass 5, count 0 2006.286.03:34:17.44#ibcon#read 6, iclass 5, count 0 2006.286.03:34:17.44#ibcon#end of sib2, iclass 5, count 0 2006.286.03:34:17.44#ibcon#*after write, iclass 5, count 0 2006.286.03:34:17.44#ibcon#*before return 0, iclass 5, count 0 2006.286.03:34:17.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:34:17.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.03:34:17.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.03:34:17.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.03:34:17.44$vck44/vb=5,4 2006.286.03:34:17.44#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.03:34:17.44#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.03:34:17.44#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:17.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:34:17.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:34:17.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:34:17.50#ibcon#enter wrdev, iclass 7, count 2 2006.286.03:34:17.50#ibcon#first serial, iclass 7, count 2 2006.286.03:34:17.50#ibcon#enter sib2, iclass 7, count 2 2006.286.03:34:17.50#ibcon#flushed, iclass 7, count 2 2006.286.03:34:17.50#ibcon#about to write, iclass 7, count 2 2006.286.03:34:17.50#ibcon#wrote, iclass 7, count 2 2006.286.03:34:17.50#ibcon#about to read 3, iclass 7, count 2 2006.286.03:34:17.52#ibcon#read 3, iclass 7, count 2 2006.286.03:34:17.52#ibcon#about to read 4, iclass 7, count 2 2006.286.03:34:17.52#ibcon#read 4, iclass 7, count 2 2006.286.03:34:17.52#ibcon#about to read 5, iclass 7, count 2 2006.286.03:34:17.52#ibcon#read 5, iclass 7, count 2 2006.286.03:34:17.52#ibcon#about to read 6, iclass 7, count 2 2006.286.03:34:17.52#ibcon#read 6, iclass 7, count 2 2006.286.03:34:17.52#ibcon#end of sib2, iclass 7, count 2 2006.286.03:34:17.52#ibcon#*mode == 0, iclass 7, count 2 2006.286.03:34:17.52#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.03:34:17.52#ibcon#[27=AT05-04\r\n] 2006.286.03:34:17.52#ibcon#*before write, iclass 7, count 2 2006.286.03:34:17.52#ibcon#enter sib2, iclass 7, count 2 2006.286.03:34:17.52#ibcon#flushed, iclass 7, count 2 2006.286.03:34:17.52#ibcon#about to write, iclass 7, count 2 2006.286.03:34:17.52#ibcon#wrote, iclass 7, count 2 2006.286.03:34:17.52#ibcon#about to read 3, iclass 7, count 2 2006.286.03:34:17.55#ibcon#read 3, iclass 7, count 2 2006.286.03:34:17.55#ibcon#about to read 4, iclass 7, count 2 2006.286.03:34:17.55#ibcon#read 4, iclass 7, count 2 2006.286.03:34:17.55#ibcon#about to read 5, iclass 7, count 2 2006.286.03:34:17.55#ibcon#read 5, iclass 7, count 2 2006.286.03:34:17.55#ibcon#about to read 6, iclass 7, count 2 2006.286.03:34:17.55#ibcon#read 6, iclass 7, count 2 2006.286.03:34:17.55#ibcon#end of sib2, iclass 7, count 2 2006.286.03:34:17.55#ibcon#*after write, iclass 7, count 2 2006.286.03:34:17.55#ibcon#*before return 0, iclass 7, count 2 2006.286.03:34:17.55#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:34:17.55#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.03:34:17.55#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.03:34:17.55#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:17.55#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:34:17.67#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:34:17.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:34:17.81#ibcon#enter wrdev, iclass 7, count 0 2006.286.03:34:17.81#ibcon#first serial, iclass 7, count 0 2006.286.03:34:17.81#ibcon#enter sib2, iclass 7, count 0 2006.286.03:34:17.81#ibcon#flushed, iclass 7, count 0 2006.286.03:34:17.81#ibcon#about to write, iclass 7, count 0 2006.286.03:34:17.81#ibcon#wrote, iclass 7, count 0 2006.286.03:34:17.81#ibcon#about to read 3, iclass 7, count 0 2006.286.03:34:17.83#ibcon#read 3, iclass 7, count 0 2006.286.03:34:17.83#ibcon#about to read 4, iclass 7, count 0 2006.286.03:34:17.83#ibcon#read 4, iclass 7, count 0 2006.286.03:34:17.83#ibcon#about to read 5, iclass 7, count 0 2006.286.03:34:17.83#ibcon#read 5, iclass 7, count 0 2006.286.03:34:17.83#ibcon#about to read 6, iclass 7, count 0 2006.286.03:34:17.83#ibcon#read 6, iclass 7, count 0 2006.286.03:34:17.83#ibcon#end of sib2, iclass 7, count 0 2006.286.03:34:17.83#ibcon#*mode == 0, iclass 7, count 0 2006.286.03:34:17.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.03:34:17.83#ibcon#[27=USB\r\n] 2006.286.03:34:17.83#ibcon#*before write, iclass 7, count 0 2006.286.03:34:17.83#ibcon#enter sib2, iclass 7, count 0 2006.286.03:34:17.83#ibcon#flushed, iclass 7, count 0 2006.286.03:34:17.83#ibcon#about to write, iclass 7, count 0 2006.286.03:34:17.83#ibcon#wrote, iclass 7, count 0 2006.286.03:34:17.83#ibcon#about to read 3, iclass 7, count 0 2006.286.03:34:17.86#ibcon#read 3, iclass 7, count 0 2006.286.03:34:17.86#ibcon#about to read 4, iclass 7, count 0 2006.286.03:34:17.86#ibcon#read 4, iclass 7, count 0 2006.286.03:34:17.86#ibcon#about to read 5, iclass 7, count 0 2006.286.03:34:17.86#ibcon#read 5, iclass 7, count 0 2006.286.03:34:17.86#ibcon#about to read 6, iclass 7, count 0 2006.286.03:34:17.86#ibcon#read 6, iclass 7, count 0 2006.286.03:34:17.86#ibcon#end of sib2, iclass 7, count 0 2006.286.03:34:17.86#ibcon#*after write, iclass 7, count 0 2006.286.03:34:17.86#ibcon#*before return 0, iclass 7, count 0 2006.286.03:34:17.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:34:17.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.03:34:17.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.03:34:17.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.03:34:17.86$vck44/vblo=6,719.99 2006.286.03:34:17.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.03:34:17.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.03:34:17.86#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:17.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:34:17.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:34:17.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:34:17.86#ibcon#enter wrdev, iclass 11, count 0 2006.286.03:34:17.86#ibcon#first serial, iclass 11, count 0 2006.286.03:34:17.86#ibcon#enter sib2, iclass 11, count 0 2006.286.03:34:17.86#ibcon#flushed, iclass 11, count 0 2006.286.03:34:17.86#ibcon#about to write, iclass 11, count 0 2006.286.03:34:17.86#ibcon#wrote, iclass 11, count 0 2006.286.03:34:17.86#ibcon#about to read 3, iclass 11, count 0 2006.286.03:34:17.88#ibcon#read 3, iclass 11, count 0 2006.286.03:34:17.88#ibcon#about to read 4, iclass 11, count 0 2006.286.03:34:17.88#ibcon#read 4, iclass 11, count 0 2006.286.03:34:17.88#ibcon#about to read 5, iclass 11, count 0 2006.286.03:34:17.88#ibcon#read 5, iclass 11, count 0 2006.286.03:34:17.88#ibcon#about to read 6, iclass 11, count 0 2006.286.03:34:17.88#ibcon#read 6, iclass 11, count 0 2006.286.03:34:17.88#ibcon#end of sib2, iclass 11, count 0 2006.286.03:34:17.88#ibcon#*mode == 0, iclass 11, count 0 2006.286.03:34:17.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.03:34:17.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.03:34:17.88#ibcon#*before write, iclass 11, count 0 2006.286.03:34:17.88#ibcon#enter sib2, iclass 11, count 0 2006.286.03:34:17.88#ibcon#flushed, iclass 11, count 0 2006.286.03:34:17.88#ibcon#about to write, iclass 11, count 0 2006.286.03:34:17.88#ibcon#wrote, iclass 11, count 0 2006.286.03:34:17.88#ibcon#about to read 3, iclass 11, count 0 2006.286.03:34:17.92#ibcon#read 3, iclass 11, count 0 2006.286.03:34:17.92#ibcon#about to read 4, iclass 11, count 0 2006.286.03:34:17.92#ibcon#read 4, iclass 11, count 0 2006.286.03:34:17.92#ibcon#about to read 5, iclass 11, count 0 2006.286.03:34:17.92#ibcon#read 5, iclass 11, count 0 2006.286.03:34:17.92#ibcon#about to read 6, iclass 11, count 0 2006.286.03:34:17.92#ibcon#read 6, iclass 11, count 0 2006.286.03:34:17.92#ibcon#end of sib2, iclass 11, count 0 2006.286.03:34:17.92#ibcon#*after write, iclass 11, count 0 2006.286.03:34:17.92#ibcon#*before return 0, iclass 11, count 0 2006.286.03:34:17.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:34:17.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.03:34:17.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.03:34:17.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.03:34:17.92$vck44/vb=6,3 2006.286.03:34:17.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.03:34:17.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.03:34:17.92#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:17.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:34:17.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:34:17.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:34:17.98#ibcon#enter wrdev, iclass 13, count 2 2006.286.03:34:17.98#ibcon#first serial, iclass 13, count 2 2006.286.03:34:17.98#ibcon#enter sib2, iclass 13, count 2 2006.286.03:34:17.98#ibcon#flushed, iclass 13, count 2 2006.286.03:34:17.98#ibcon#about to write, iclass 13, count 2 2006.286.03:34:17.98#ibcon#wrote, iclass 13, count 2 2006.286.03:34:17.98#ibcon#about to read 3, iclass 13, count 2 2006.286.03:34:18.00#ibcon#read 3, iclass 13, count 2 2006.286.03:34:18.00#ibcon#about to read 4, iclass 13, count 2 2006.286.03:34:18.00#ibcon#read 4, iclass 13, count 2 2006.286.03:34:18.00#ibcon#about to read 5, iclass 13, count 2 2006.286.03:34:18.00#ibcon#read 5, iclass 13, count 2 2006.286.03:34:18.00#ibcon#about to read 6, iclass 13, count 2 2006.286.03:34:18.00#ibcon#read 6, iclass 13, count 2 2006.286.03:34:18.00#ibcon#end of sib2, iclass 13, count 2 2006.286.03:34:18.00#ibcon#*mode == 0, iclass 13, count 2 2006.286.03:34:18.00#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.03:34:18.00#ibcon#[27=AT06-03\r\n] 2006.286.03:34:18.00#ibcon#*before write, iclass 13, count 2 2006.286.03:34:18.00#ibcon#enter sib2, iclass 13, count 2 2006.286.03:34:18.00#ibcon#flushed, iclass 13, count 2 2006.286.03:34:18.00#ibcon#about to write, iclass 13, count 2 2006.286.03:34:18.00#ibcon#wrote, iclass 13, count 2 2006.286.03:34:18.00#ibcon#about to read 3, iclass 13, count 2 2006.286.03:34:18.03#ibcon#read 3, iclass 13, count 2 2006.286.03:34:18.03#ibcon#about to read 4, iclass 13, count 2 2006.286.03:34:18.03#ibcon#read 4, iclass 13, count 2 2006.286.03:34:18.03#ibcon#about to read 5, iclass 13, count 2 2006.286.03:34:18.03#ibcon#read 5, iclass 13, count 2 2006.286.03:34:18.03#ibcon#about to read 6, iclass 13, count 2 2006.286.03:34:18.03#ibcon#read 6, iclass 13, count 2 2006.286.03:34:18.03#ibcon#end of sib2, iclass 13, count 2 2006.286.03:34:18.03#ibcon#*after write, iclass 13, count 2 2006.286.03:34:18.03#ibcon#*before return 0, iclass 13, count 2 2006.286.03:34:18.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:34:18.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.03:34:18.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.03:34:18.03#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:18.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:34:18.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:34:18.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:34:18.15#ibcon#enter wrdev, iclass 13, count 0 2006.286.03:34:18.15#ibcon#first serial, iclass 13, count 0 2006.286.03:34:18.15#ibcon#enter sib2, iclass 13, count 0 2006.286.03:34:18.15#ibcon#flushed, iclass 13, count 0 2006.286.03:34:18.15#ibcon#about to write, iclass 13, count 0 2006.286.03:34:18.15#ibcon#wrote, iclass 13, count 0 2006.286.03:34:18.15#ibcon#about to read 3, iclass 13, count 0 2006.286.03:34:18.17#ibcon#read 3, iclass 13, count 0 2006.286.03:34:18.17#ibcon#about to read 4, iclass 13, count 0 2006.286.03:34:18.17#ibcon#read 4, iclass 13, count 0 2006.286.03:34:18.17#ibcon#about to read 5, iclass 13, count 0 2006.286.03:34:18.17#ibcon#read 5, iclass 13, count 0 2006.286.03:34:18.17#ibcon#about to read 6, iclass 13, count 0 2006.286.03:34:18.17#ibcon#read 6, iclass 13, count 0 2006.286.03:34:18.17#ibcon#end of sib2, iclass 13, count 0 2006.286.03:34:18.17#ibcon#*mode == 0, iclass 13, count 0 2006.286.03:34:18.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.03:34:18.17#ibcon#[27=USB\r\n] 2006.286.03:34:18.17#ibcon#*before write, iclass 13, count 0 2006.286.03:34:18.17#ibcon#enter sib2, iclass 13, count 0 2006.286.03:34:18.17#ibcon#flushed, iclass 13, count 0 2006.286.03:34:18.17#ibcon#about to write, iclass 13, count 0 2006.286.03:34:18.17#ibcon#wrote, iclass 13, count 0 2006.286.03:34:18.17#ibcon#about to read 3, iclass 13, count 0 2006.286.03:34:18.20#ibcon#read 3, iclass 13, count 0 2006.286.03:34:18.20#ibcon#about to read 4, iclass 13, count 0 2006.286.03:34:18.20#ibcon#read 4, iclass 13, count 0 2006.286.03:34:18.20#ibcon#about to read 5, iclass 13, count 0 2006.286.03:34:18.20#ibcon#read 5, iclass 13, count 0 2006.286.03:34:18.20#ibcon#about to read 6, iclass 13, count 0 2006.286.03:34:18.20#ibcon#read 6, iclass 13, count 0 2006.286.03:34:18.20#ibcon#end of sib2, iclass 13, count 0 2006.286.03:34:18.20#ibcon#*after write, iclass 13, count 0 2006.286.03:34:18.20#ibcon#*before return 0, iclass 13, count 0 2006.286.03:34:18.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:34:18.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.03:34:18.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.03:34:18.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.03:34:18.20$vck44/vblo=7,734.99 2006.286.03:34:18.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.03:34:18.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.03:34:18.20#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:18.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:34:18.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:34:18.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:34:18.20#ibcon#enter wrdev, iclass 15, count 0 2006.286.03:34:18.20#ibcon#first serial, iclass 15, count 0 2006.286.03:34:18.20#ibcon#enter sib2, iclass 15, count 0 2006.286.03:34:18.20#ibcon#flushed, iclass 15, count 0 2006.286.03:34:18.20#ibcon#about to write, iclass 15, count 0 2006.286.03:34:18.20#ibcon#wrote, iclass 15, count 0 2006.286.03:34:18.20#ibcon#about to read 3, iclass 15, count 0 2006.286.03:34:18.22#ibcon#read 3, iclass 15, count 0 2006.286.03:34:18.22#ibcon#about to read 4, iclass 15, count 0 2006.286.03:34:18.22#ibcon#read 4, iclass 15, count 0 2006.286.03:34:18.22#ibcon#about to read 5, iclass 15, count 0 2006.286.03:34:18.22#ibcon#read 5, iclass 15, count 0 2006.286.03:34:18.22#ibcon#about to read 6, iclass 15, count 0 2006.286.03:34:18.22#ibcon#read 6, iclass 15, count 0 2006.286.03:34:18.22#ibcon#end of sib2, iclass 15, count 0 2006.286.03:34:18.22#ibcon#*mode == 0, iclass 15, count 0 2006.286.03:34:18.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.03:34:18.22#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.03:34:18.22#ibcon#*before write, iclass 15, count 0 2006.286.03:34:18.22#ibcon#enter sib2, iclass 15, count 0 2006.286.03:34:18.22#ibcon#flushed, iclass 15, count 0 2006.286.03:34:18.22#ibcon#about to write, iclass 15, count 0 2006.286.03:34:18.22#ibcon#wrote, iclass 15, count 0 2006.286.03:34:18.22#ibcon#about to read 3, iclass 15, count 0 2006.286.03:34:18.26#ibcon#read 3, iclass 15, count 0 2006.286.03:34:18.26#ibcon#about to read 4, iclass 15, count 0 2006.286.03:34:18.26#ibcon#read 4, iclass 15, count 0 2006.286.03:34:18.26#ibcon#about to read 5, iclass 15, count 0 2006.286.03:34:18.26#ibcon#read 5, iclass 15, count 0 2006.286.03:34:18.26#ibcon#about to read 6, iclass 15, count 0 2006.286.03:34:18.26#ibcon#read 6, iclass 15, count 0 2006.286.03:34:18.26#ibcon#end of sib2, iclass 15, count 0 2006.286.03:34:18.26#ibcon#*after write, iclass 15, count 0 2006.286.03:34:18.26#ibcon#*before return 0, iclass 15, count 0 2006.286.03:34:18.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:34:18.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.03:34:18.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.03:34:18.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.03:34:18.26$vck44/vb=7,4 2006.286.03:34:18.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.03:34:18.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.03:34:18.26#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:18.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:34:18.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:34:18.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:34:18.32#ibcon#enter wrdev, iclass 17, count 2 2006.286.03:34:18.32#ibcon#first serial, iclass 17, count 2 2006.286.03:34:18.32#ibcon#enter sib2, iclass 17, count 2 2006.286.03:34:18.32#ibcon#flushed, iclass 17, count 2 2006.286.03:34:18.32#ibcon#about to write, iclass 17, count 2 2006.286.03:34:18.32#ibcon#wrote, iclass 17, count 2 2006.286.03:34:18.32#ibcon#about to read 3, iclass 17, count 2 2006.286.03:34:18.34#ibcon#read 3, iclass 17, count 2 2006.286.03:34:18.34#ibcon#about to read 4, iclass 17, count 2 2006.286.03:34:18.34#ibcon#read 4, iclass 17, count 2 2006.286.03:34:18.34#ibcon#about to read 5, iclass 17, count 2 2006.286.03:34:18.34#ibcon#read 5, iclass 17, count 2 2006.286.03:34:18.34#ibcon#about to read 6, iclass 17, count 2 2006.286.03:34:18.34#ibcon#read 6, iclass 17, count 2 2006.286.03:34:18.34#ibcon#end of sib2, iclass 17, count 2 2006.286.03:34:18.34#ibcon#*mode == 0, iclass 17, count 2 2006.286.03:34:18.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.03:34:18.34#ibcon#[27=AT07-04\r\n] 2006.286.03:34:18.34#ibcon#*before write, iclass 17, count 2 2006.286.03:34:18.34#ibcon#enter sib2, iclass 17, count 2 2006.286.03:34:18.34#ibcon#flushed, iclass 17, count 2 2006.286.03:34:18.34#ibcon#about to write, iclass 17, count 2 2006.286.03:34:18.34#ibcon#wrote, iclass 17, count 2 2006.286.03:34:18.34#ibcon#about to read 3, iclass 17, count 2 2006.286.03:34:18.37#ibcon#read 3, iclass 17, count 2 2006.286.03:34:18.37#ibcon#about to read 4, iclass 17, count 2 2006.286.03:34:18.37#ibcon#read 4, iclass 17, count 2 2006.286.03:34:18.37#ibcon#about to read 5, iclass 17, count 2 2006.286.03:34:18.37#ibcon#read 5, iclass 17, count 2 2006.286.03:34:18.37#ibcon#about to read 6, iclass 17, count 2 2006.286.03:34:18.37#ibcon#read 6, iclass 17, count 2 2006.286.03:34:18.37#ibcon#end of sib2, iclass 17, count 2 2006.286.03:34:18.37#ibcon#*after write, iclass 17, count 2 2006.286.03:34:18.37#ibcon#*before return 0, iclass 17, count 2 2006.286.03:34:18.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:34:18.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.03:34:18.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.03:34:18.37#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:18.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:34:18.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:34:18.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:34:18.49#ibcon#enter wrdev, iclass 17, count 0 2006.286.03:34:18.49#ibcon#first serial, iclass 17, count 0 2006.286.03:34:18.49#ibcon#enter sib2, iclass 17, count 0 2006.286.03:34:18.49#ibcon#flushed, iclass 17, count 0 2006.286.03:34:18.49#ibcon#about to write, iclass 17, count 0 2006.286.03:34:18.49#ibcon#wrote, iclass 17, count 0 2006.286.03:34:18.49#ibcon#about to read 3, iclass 17, count 0 2006.286.03:34:18.51#ibcon#read 3, iclass 17, count 0 2006.286.03:34:18.51#ibcon#about to read 4, iclass 17, count 0 2006.286.03:34:18.51#ibcon#read 4, iclass 17, count 0 2006.286.03:34:18.51#ibcon#about to read 5, iclass 17, count 0 2006.286.03:34:18.51#ibcon#read 5, iclass 17, count 0 2006.286.03:34:18.51#ibcon#about to read 6, iclass 17, count 0 2006.286.03:34:18.51#ibcon#read 6, iclass 17, count 0 2006.286.03:34:18.51#ibcon#end of sib2, iclass 17, count 0 2006.286.03:34:18.51#ibcon#*mode == 0, iclass 17, count 0 2006.286.03:34:18.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.03:34:18.51#ibcon#[27=USB\r\n] 2006.286.03:34:18.51#ibcon#*before write, iclass 17, count 0 2006.286.03:34:18.51#ibcon#enter sib2, iclass 17, count 0 2006.286.03:34:18.51#ibcon#flushed, iclass 17, count 0 2006.286.03:34:18.51#ibcon#about to write, iclass 17, count 0 2006.286.03:34:18.51#ibcon#wrote, iclass 17, count 0 2006.286.03:34:18.51#ibcon#about to read 3, iclass 17, count 0 2006.286.03:34:18.54#ibcon#read 3, iclass 17, count 0 2006.286.03:34:18.54#ibcon#about to read 4, iclass 17, count 0 2006.286.03:34:18.54#ibcon#read 4, iclass 17, count 0 2006.286.03:34:18.54#ibcon#about to read 5, iclass 17, count 0 2006.286.03:34:18.54#ibcon#read 5, iclass 17, count 0 2006.286.03:34:18.54#ibcon#about to read 6, iclass 17, count 0 2006.286.03:34:18.54#ibcon#read 6, iclass 17, count 0 2006.286.03:34:18.54#ibcon#end of sib2, iclass 17, count 0 2006.286.03:34:18.54#ibcon#*after write, iclass 17, count 0 2006.286.03:34:18.54#ibcon#*before return 0, iclass 17, count 0 2006.286.03:34:18.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:34:18.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.03:34:18.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.03:34:18.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.03:34:18.54$vck44/vblo=8,744.99 2006.286.03:34:18.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.03:34:18.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.03:34:18.54#ibcon#ireg 17 cls_cnt 0 2006.286.03:34:18.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:34:18.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:34:18.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:34:18.54#ibcon#enter wrdev, iclass 19, count 0 2006.286.03:34:18.54#ibcon#first serial, iclass 19, count 0 2006.286.03:34:18.54#ibcon#enter sib2, iclass 19, count 0 2006.286.03:34:18.54#ibcon#flushed, iclass 19, count 0 2006.286.03:34:18.54#ibcon#about to write, iclass 19, count 0 2006.286.03:34:18.54#ibcon#wrote, iclass 19, count 0 2006.286.03:34:18.54#ibcon#about to read 3, iclass 19, count 0 2006.286.03:34:18.56#ibcon#read 3, iclass 19, count 0 2006.286.03:34:18.62#ibcon#about to read 4, iclass 19, count 0 2006.286.03:34:18.62#ibcon#read 4, iclass 19, count 0 2006.286.03:34:18.62#ibcon#about to read 5, iclass 19, count 0 2006.286.03:34:18.62#ibcon#read 5, iclass 19, count 0 2006.286.03:34:18.62#ibcon#about to read 6, iclass 19, count 0 2006.286.03:34:18.62#ibcon#read 6, iclass 19, count 0 2006.286.03:34:18.62#ibcon#end of sib2, iclass 19, count 0 2006.286.03:34:18.62#ibcon#*mode == 0, iclass 19, count 0 2006.286.03:34:18.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.03:34:18.62#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.03:34:18.62#ibcon#*before write, iclass 19, count 0 2006.286.03:34:18.62#ibcon#enter sib2, iclass 19, count 0 2006.286.03:34:18.62#ibcon#flushed, iclass 19, count 0 2006.286.03:34:18.62#ibcon#about to write, iclass 19, count 0 2006.286.03:34:18.62#ibcon#wrote, iclass 19, count 0 2006.286.03:34:18.62#ibcon#about to read 3, iclass 19, count 0 2006.286.03:34:18.66#ibcon#read 3, iclass 19, count 0 2006.286.03:34:18.66#ibcon#about to read 4, iclass 19, count 0 2006.286.03:34:18.66#ibcon#read 4, iclass 19, count 0 2006.286.03:34:18.66#ibcon#about to read 5, iclass 19, count 0 2006.286.03:34:18.66#ibcon#read 5, iclass 19, count 0 2006.286.03:34:18.66#ibcon#about to read 6, iclass 19, count 0 2006.286.03:34:18.66#ibcon#read 6, iclass 19, count 0 2006.286.03:34:18.66#ibcon#end of sib2, iclass 19, count 0 2006.286.03:34:18.66#ibcon#*after write, iclass 19, count 0 2006.286.03:34:18.66#ibcon#*before return 0, iclass 19, count 0 2006.286.03:34:18.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:34:18.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:34:18.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.03:34:18.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.03:34:18.66$vck44/vb=8,4 2006.286.03:34:18.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.03:34:18.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.03:34:18.66#ibcon#ireg 11 cls_cnt 2 2006.286.03:34:18.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:34:18.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:34:18.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:34:18.66#ibcon#enter wrdev, iclass 21, count 2 2006.286.03:34:18.66#ibcon#first serial, iclass 21, count 2 2006.286.03:34:18.66#ibcon#enter sib2, iclass 21, count 2 2006.286.03:34:18.66#ibcon#flushed, iclass 21, count 2 2006.286.03:34:18.66#ibcon#about to write, iclass 21, count 2 2006.286.03:34:18.66#ibcon#wrote, iclass 21, count 2 2006.286.03:34:18.66#ibcon#about to read 3, iclass 21, count 2 2006.286.03:34:18.68#ibcon#read 3, iclass 21, count 2 2006.286.03:34:18.68#ibcon#about to read 4, iclass 21, count 2 2006.286.03:34:18.68#ibcon#read 4, iclass 21, count 2 2006.286.03:34:18.68#ibcon#about to read 5, iclass 21, count 2 2006.286.03:34:18.68#ibcon#read 5, iclass 21, count 2 2006.286.03:34:18.68#ibcon#about to read 6, iclass 21, count 2 2006.286.03:34:18.68#ibcon#read 6, iclass 21, count 2 2006.286.03:34:18.68#ibcon#end of sib2, iclass 21, count 2 2006.286.03:34:18.68#ibcon#*mode == 0, iclass 21, count 2 2006.286.03:34:18.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.03:34:18.68#ibcon#[27=AT08-04\r\n] 2006.286.03:34:18.68#ibcon#*before write, iclass 21, count 2 2006.286.03:34:18.68#ibcon#enter sib2, iclass 21, count 2 2006.286.03:34:18.68#ibcon#flushed, iclass 21, count 2 2006.286.03:34:18.68#ibcon#about to write, iclass 21, count 2 2006.286.03:34:18.68#ibcon#wrote, iclass 21, count 2 2006.286.03:34:18.68#ibcon#about to read 3, iclass 21, count 2 2006.286.03:34:18.71#ibcon#read 3, iclass 21, count 2 2006.286.03:34:18.71#ibcon#about to read 4, iclass 21, count 2 2006.286.03:34:18.71#ibcon#read 4, iclass 21, count 2 2006.286.03:34:18.71#ibcon#about to read 5, iclass 21, count 2 2006.286.03:34:18.71#ibcon#read 5, iclass 21, count 2 2006.286.03:34:18.71#ibcon#about to read 6, iclass 21, count 2 2006.286.03:34:18.71#ibcon#read 6, iclass 21, count 2 2006.286.03:34:18.71#ibcon#end of sib2, iclass 21, count 2 2006.286.03:34:18.71#ibcon#*after write, iclass 21, count 2 2006.286.03:34:18.71#ibcon#*before return 0, iclass 21, count 2 2006.286.03:34:18.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:34:18.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.03:34:18.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.03:34:18.71#ibcon#ireg 7 cls_cnt 0 2006.286.03:34:18.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:34:18.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:34:18.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:34:18.83#ibcon#enter wrdev, iclass 21, count 0 2006.286.03:34:18.83#ibcon#first serial, iclass 21, count 0 2006.286.03:34:18.83#ibcon#enter sib2, iclass 21, count 0 2006.286.03:34:18.83#ibcon#flushed, iclass 21, count 0 2006.286.03:34:18.83#ibcon#about to write, iclass 21, count 0 2006.286.03:34:18.83#ibcon#wrote, iclass 21, count 0 2006.286.03:34:18.83#ibcon#about to read 3, iclass 21, count 0 2006.286.03:34:18.85#ibcon#read 3, iclass 21, count 0 2006.286.03:34:18.85#ibcon#about to read 4, iclass 21, count 0 2006.286.03:34:18.85#ibcon#read 4, iclass 21, count 0 2006.286.03:34:18.85#ibcon#about to read 5, iclass 21, count 0 2006.286.03:34:18.85#ibcon#read 5, iclass 21, count 0 2006.286.03:34:18.85#ibcon#about to read 6, iclass 21, count 0 2006.286.03:34:18.85#ibcon#read 6, iclass 21, count 0 2006.286.03:34:18.85#ibcon#end of sib2, iclass 21, count 0 2006.286.03:34:18.85#ibcon#*mode == 0, iclass 21, count 0 2006.286.03:34:18.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.03:34:18.85#ibcon#[27=USB\r\n] 2006.286.03:34:18.85#ibcon#*before write, iclass 21, count 0 2006.286.03:34:18.85#ibcon#enter sib2, iclass 21, count 0 2006.286.03:34:18.85#ibcon#flushed, iclass 21, count 0 2006.286.03:34:18.85#ibcon#about to write, iclass 21, count 0 2006.286.03:34:18.85#ibcon#wrote, iclass 21, count 0 2006.286.03:34:18.85#ibcon#about to read 3, iclass 21, count 0 2006.286.03:34:18.88#ibcon#read 3, iclass 21, count 0 2006.286.03:34:18.88#ibcon#about to read 4, iclass 21, count 0 2006.286.03:34:18.88#ibcon#read 4, iclass 21, count 0 2006.286.03:34:18.88#ibcon#about to read 5, iclass 21, count 0 2006.286.03:34:18.88#ibcon#read 5, iclass 21, count 0 2006.286.03:34:18.88#ibcon#about to read 6, iclass 21, count 0 2006.286.03:34:18.88#ibcon#read 6, iclass 21, count 0 2006.286.03:34:18.88#ibcon#end of sib2, iclass 21, count 0 2006.286.03:34:18.88#ibcon#*after write, iclass 21, count 0 2006.286.03:34:18.88#ibcon#*before return 0, iclass 21, count 0 2006.286.03:34:18.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:34:18.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.03:34:18.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.03:34:18.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.03:34:18.88$vck44/vabw=wide 2006.286.03:34:18.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.03:34:18.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.03:34:18.88#ibcon#ireg 8 cls_cnt 0 2006.286.03:34:18.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:34:18.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:34:18.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:34:18.88#ibcon#enter wrdev, iclass 23, count 0 2006.286.03:34:18.88#ibcon#first serial, iclass 23, count 0 2006.286.03:34:18.88#ibcon#enter sib2, iclass 23, count 0 2006.286.03:34:18.88#ibcon#flushed, iclass 23, count 0 2006.286.03:34:18.88#ibcon#about to write, iclass 23, count 0 2006.286.03:34:18.88#ibcon#wrote, iclass 23, count 0 2006.286.03:34:18.88#ibcon#about to read 3, iclass 23, count 0 2006.286.03:34:18.90#ibcon#read 3, iclass 23, count 0 2006.286.03:34:18.90#ibcon#about to read 4, iclass 23, count 0 2006.286.03:34:18.90#ibcon#read 4, iclass 23, count 0 2006.286.03:34:18.90#ibcon#about to read 5, iclass 23, count 0 2006.286.03:34:18.90#ibcon#read 5, iclass 23, count 0 2006.286.03:34:18.90#ibcon#about to read 6, iclass 23, count 0 2006.286.03:34:18.90#ibcon#read 6, iclass 23, count 0 2006.286.03:34:18.90#ibcon#end of sib2, iclass 23, count 0 2006.286.03:34:18.90#ibcon#*mode == 0, iclass 23, count 0 2006.286.03:34:18.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.03:34:18.90#ibcon#[25=BW32\r\n] 2006.286.03:34:18.90#ibcon#*before write, iclass 23, count 0 2006.286.03:34:18.90#ibcon#enter sib2, iclass 23, count 0 2006.286.03:34:18.90#ibcon#flushed, iclass 23, count 0 2006.286.03:34:18.90#ibcon#about to write, iclass 23, count 0 2006.286.03:34:18.90#ibcon#wrote, iclass 23, count 0 2006.286.03:34:18.90#ibcon#about to read 3, iclass 23, count 0 2006.286.03:34:18.93#ibcon#read 3, iclass 23, count 0 2006.286.03:34:18.93#ibcon#about to read 4, iclass 23, count 0 2006.286.03:34:18.93#ibcon#read 4, iclass 23, count 0 2006.286.03:34:18.93#ibcon#about to read 5, iclass 23, count 0 2006.286.03:34:18.93#ibcon#read 5, iclass 23, count 0 2006.286.03:34:18.93#ibcon#about to read 6, iclass 23, count 0 2006.286.03:34:18.93#ibcon#read 6, iclass 23, count 0 2006.286.03:34:18.93#ibcon#end of sib2, iclass 23, count 0 2006.286.03:34:18.93#ibcon#*after write, iclass 23, count 0 2006.286.03:34:18.93#ibcon#*before return 0, iclass 23, count 0 2006.286.03:34:18.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:34:18.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.03:34:18.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.03:34:18.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.03:34:18.93$vck44/vbbw=wide 2006.286.03:34:18.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.03:34:18.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.03:34:18.93#ibcon#ireg 8 cls_cnt 0 2006.286.03:34:18.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:34:19.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:34:19.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:34:19.00#ibcon#enter wrdev, iclass 25, count 0 2006.286.03:34:19.00#ibcon#first serial, iclass 25, count 0 2006.286.03:34:19.00#ibcon#enter sib2, iclass 25, count 0 2006.286.03:34:19.00#ibcon#flushed, iclass 25, count 0 2006.286.03:34:19.00#ibcon#about to write, iclass 25, count 0 2006.286.03:34:19.00#ibcon#wrote, iclass 25, count 0 2006.286.03:34:19.00#ibcon#about to read 3, iclass 25, count 0 2006.286.03:34:19.02#ibcon#read 3, iclass 25, count 0 2006.286.03:34:19.02#ibcon#about to read 4, iclass 25, count 0 2006.286.03:34:19.02#ibcon#read 4, iclass 25, count 0 2006.286.03:34:19.02#ibcon#about to read 5, iclass 25, count 0 2006.286.03:34:19.02#ibcon#read 5, iclass 25, count 0 2006.286.03:34:19.02#ibcon#about to read 6, iclass 25, count 0 2006.286.03:34:19.02#ibcon#read 6, iclass 25, count 0 2006.286.03:34:19.02#ibcon#end of sib2, iclass 25, count 0 2006.286.03:34:19.02#ibcon#*mode == 0, iclass 25, count 0 2006.286.03:34:19.02#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.03:34:19.02#ibcon#[27=BW32\r\n] 2006.286.03:34:19.02#ibcon#*before write, iclass 25, count 0 2006.286.03:34:19.02#ibcon#enter sib2, iclass 25, count 0 2006.286.03:34:19.02#ibcon#flushed, iclass 25, count 0 2006.286.03:34:19.02#ibcon#about to write, iclass 25, count 0 2006.286.03:34:19.02#ibcon#wrote, iclass 25, count 0 2006.286.03:34:19.02#ibcon#about to read 3, iclass 25, count 0 2006.286.03:34:19.05#ibcon#read 3, iclass 25, count 0 2006.286.03:34:19.05#ibcon#about to read 4, iclass 25, count 0 2006.286.03:34:19.05#ibcon#read 4, iclass 25, count 0 2006.286.03:34:19.05#ibcon#about to read 5, iclass 25, count 0 2006.286.03:34:19.05#ibcon#read 5, iclass 25, count 0 2006.286.03:34:19.05#ibcon#about to read 6, iclass 25, count 0 2006.286.03:34:19.05#ibcon#read 6, iclass 25, count 0 2006.286.03:34:19.05#ibcon#end of sib2, iclass 25, count 0 2006.286.03:34:19.05#ibcon#*after write, iclass 25, count 0 2006.286.03:34:19.05#ibcon#*before return 0, iclass 25, count 0 2006.286.03:34:19.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:34:19.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:34:19.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.03:34:19.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.03:34:19.05$setupk4/ifdk4 2006.286.03:34:19.05$ifdk4/lo= 2006.286.03:34:19.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.03:34:19.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.03:34:19.05$ifdk4/patch= 2006.286.03:34:19.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.03:34:19.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.03:34:19.05$setupk4/!*+20s 2006.286.03:34:19.40#abcon#<5=/04 3.2 6.8 21.73 791015.1\r\n> 2006.286.03:34:19.42#abcon#{5=INTERFACE CLEAR} 2006.286.03:34:19.48#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:34:24.14#trakl#Source acquired 2006.286.03:34:24.14#flagr#flagr/antenna,acquired 2006.286.03:34:29.57#abcon#<5=/04 3.2 6.8 21.72 791015.1\r\n> 2006.286.03:34:29.59#abcon#{5=INTERFACE CLEAR} 2006.286.03:34:29.65#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:34:32.68$setupk4/"tpicd 2006.286.03:34:32.68$setupk4/echo=off 2006.286.03:34:32.68$setupk4/xlog=off 2006.286.03:34:32.68:!2006.286.03:36:57 2006.286.03:36:57.00:preob 2006.286.03:36:58.14/onsource/TRACKING 2006.286.03:36:58.14:!2006.286.03:37:07 2006.286.03:37:07.00:"tape 2006.286.03:37:07.00:"st=record 2006.286.03:37:07.00:data_valid=on 2006.286.03:37:07.00:midob 2006.286.03:37:07.14/onsource/TRACKING 2006.286.03:37:07.14/wx/21.68,1015.0,78 2006.286.03:37:07.36/cable/+6.4970E-03 2006.286.03:37:08.45/va/01,07,usb,yes,36,40 2006.286.03:37:08.45/va/02,06,usb,yes,37,37 2006.286.03:37:08.45/va/03,07,usb,yes,36,38 2006.286.03:37:08.45/va/04,06,usb,yes,38,40 2006.286.03:37:08.45/va/05,03,usb,yes,37,38 2006.286.03:37:08.45/va/06,04,usb,yes,34,33 2006.286.03:37:08.45/va/07,04,usb,yes,34,35 2006.286.03:37:08.45/va/08,03,usb,yes,35,43 2006.286.03:37:08.68/valo/01,524.99,yes,locked 2006.286.03:37:08.68/valo/02,534.99,yes,locked 2006.286.03:37:08.68/valo/03,564.99,yes,locked 2006.286.03:37:08.68/valo/04,624.99,yes,locked 2006.286.03:37:08.68/valo/05,734.99,yes,locked 2006.286.03:37:08.68/valo/06,814.99,yes,locked 2006.286.03:37:08.68/valo/07,864.99,yes,locked 2006.286.03:37:08.68/valo/08,884.99,yes,locked 2006.286.03:37:09.77/vb/01,04,usb,yes,33,30 2006.286.03:37:09.77/vb/02,05,usb,yes,31,31 2006.286.03:37:09.77/vb/03,04,usb,yes,32,35 2006.286.03:37:09.77/vb/04,05,usb,yes,32,31 2006.286.03:37:09.77/vb/05,04,usb,yes,29,31 2006.286.03:37:09.77/vb/06,03,usb,yes,41,36 2006.286.03:37:09.77/vb/07,04,usb,yes,33,33 2006.286.03:37:09.77/vb/08,04,usb,yes,30,34 2006.286.03:37:10.00/vblo/01,629.99,yes,locked 2006.286.03:37:10.00/vblo/02,634.99,yes,locked 2006.286.03:37:10.00/vblo/03,649.99,yes,locked 2006.286.03:37:10.00/vblo/04,679.99,yes,locked 2006.286.03:37:10.00/vblo/05,709.99,yes,locked 2006.286.03:37:10.00/vblo/06,719.99,yes,locked 2006.286.03:37:10.00/vblo/07,734.99,yes,locked 2006.286.03:37:10.00/vblo/08,744.99,yes,locked 2006.286.03:37:10.15/vabw/8 2006.286.03:37:10.30/vbbw/8 2006.286.03:37:10.39/xfe/off,on,12.0 2006.286.03:37:10.76/ifatt/23,28,28,28 2006.286.03:37:11.08/fmout-gps/S +2.56E-07 2006.286.03:37:11.10:!2006.286.03:37:47 2006.286.03:37:47.01:data_valid=off 2006.286.03:37:47.01:"et 2006.286.03:37:47.01:!+3s 2006.286.03:37:50.02:"tape 2006.286.03:37:50.02:postob 2006.286.03:37:50.20/cable/+6.4977E-03 2006.286.03:37:50.20/wx/21.67,1015.0,78 2006.286.03:37:50.26/fmout-gps/S +2.57E-07 2006.286.03:37:50.26:scan_name=286-0342,jd0610,570 2006.286.03:37:50.26:source=0804+499,080839.67,495036.5,2000.0,cw 2006.286.03:37:52.14#flagr#flagr/antenna,new-source 2006.286.03:37:52.14:checkk5 2006.286.03:37:52.49/chk_autoobs//k5ts1/ autoobs is running! 2006.286.03:37:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.286.03:37:53.48/chk_autoobs//k5ts3/ autoobs is running! 2006.286.03:37:53.89/chk_autoobs//k5ts4/ autoobs is running! 2006.286.03:37:54.30/chk_obsdata//k5ts1/T2860337??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:37:54.96/chk_obsdata//k5ts2/T2860337??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:37:55.31/chk_obsdata//k5ts3/T2860337??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:37:55.74/chk_obsdata//k5ts4/T2860337??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:37:56.91/k5log//k5ts1_log_newline 2006.286.03:37:57.76/k5log//k5ts2_log_newline 2006.286.03:37:58.72/k5log//k5ts3_log_newline 2006.286.03:37:59.66/k5log//k5ts4_log_newline 2006.286.03:37:59.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.03:37:59.68:setupk4=1 2006.286.03:37:59.68$setupk4/echo=on 2006.286.03:37:59.68$setupk4/pcalon 2006.286.03:37:59.68$pcalon/"no phase cal control is implemented here 2006.286.03:37:59.68$setupk4/"tpicd=stop 2006.286.03:37:59.68$setupk4/"rec=synch_on 2006.286.03:37:59.68$setupk4/"rec_mode=128 2006.286.03:37:59.68$setupk4/!* 2006.286.03:37:59.68$setupk4/recpk4 2006.286.03:37:59.68$recpk4/recpatch= 2006.286.03:37:59.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.03:37:59.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.03:37:59.69$setupk4/vck44 2006.286.03:37:59.69$vck44/valo=1,524.99 2006.286.03:37:59.69#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.03:37:59.69#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.03:37:59.69#ibcon#ireg 17 cls_cnt 0 2006.286.03:37:59.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:37:59.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:37:59.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:37:59.69#ibcon#enter wrdev, iclass 10, count 0 2006.286.03:37:59.69#ibcon#first serial, iclass 10, count 0 2006.286.03:37:59.69#ibcon#enter sib2, iclass 10, count 0 2006.286.03:37:59.69#ibcon#flushed, iclass 10, count 0 2006.286.03:37:59.69#ibcon#about to write, iclass 10, count 0 2006.286.03:37:59.69#ibcon#wrote, iclass 10, count 0 2006.286.03:37:59.69#ibcon#about to read 3, iclass 10, count 0 2006.286.03:37:59.70#ibcon#read 3, iclass 10, count 0 2006.286.03:37:59.70#ibcon#about to read 4, iclass 10, count 0 2006.286.03:37:59.70#ibcon#read 4, iclass 10, count 0 2006.286.03:37:59.70#ibcon#about to read 5, iclass 10, count 0 2006.286.03:37:59.70#ibcon#read 5, iclass 10, count 0 2006.286.03:37:59.70#ibcon#about to read 6, iclass 10, count 0 2006.286.03:37:59.70#ibcon#read 6, iclass 10, count 0 2006.286.03:37:59.70#ibcon#end of sib2, iclass 10, count 0 2006.286.03:37:59.70#ibcon#*mode == 0, iclass 10, count 0 2006.286.03:37:59.70#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.03:37:59.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.03:37:59.70#ibcon#*before write, iclass 10, count 0 2006.286.03:37:59.70#ibcon#enter sib2, iclass 10, count 0 2006.286.03:37:59.70#ibcon#flushed, iclass 10, count 0 2006.286.03:37:59.70#ibcon#about to write, iclass 10, count 0 2006.286.03:37:59.70#ibcon#wrote, iclass 10, count 0 2006.286.03:37:59.70#ibcon#about to read 3, iclass 10, count 0 2006.286.03:37:59.75#ibcon#read 3, iclass 10, count 0 2006.286.03:37:59.75#ibcon#about to read 4, iclass 10, count 0 2006.286.03:37:59.75#ibcon#read 4, iclass 10, count 0 2006.286.03:37:59.75#ibcon#about to read 5, iclass 10, count 0 2006.286.03:37:59.75#ibcon#read 5, iclass 10, count 0 2006.286.03:37:59.75#ibcon#about to read 6, iclass 10, count 0 2006.286.03:37:59.75#ibcon#read 6, iclass 10, count 0 2006.286.03:37:59.75#ibcon#end of sib2, iclass 10, count 0 2006.286.03:37:59.75#ibcon#*after write, iclass 10, count 0 2006.286.03:37:59.75#ibcon#*before return 0, iclass 10, count 0 2006.286.03:37:59.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:37:59.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:37:59.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.03:37:59.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.03:37:59.75$vck44/va=1,7 2006.286.03:37:59.75#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.03:37:59.75#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.03:37:59.75#ibcon#ireg 11 cls_cnt 2 2006.286.03:37:59.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:37:59.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:37:59.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:37:59.75#ibcon#enter wrdev, iclass 12, count 2 2006.286.03:37:59.75#ibcon#first serial, iclass 12, count 2 2006.286.03:37:59.75#ibcon#enter sib2, iclass 12, count 2 2006.286.03:37:59.75#ibcon#flushed, iclass 12, count 2 2006.286.03:37:59.75#ibcon#about to write, iclass 12, count 2 2006.286.03:37:59.75#ibcon#wrote, iclass 12, count 2 2006.286.03:37:59.75#ibcon#about to read 3, iclass 12, count 2 2006.286.03:37:59.77#ibcon#read 3, iclass 12, count 2 2006.286.03:37:59.77#ibcon#about to read 4, iclass 12, count 2 2006.286.03:37:59.77#ibcon#read 4, iclass 12, count 2 2006.286.03:37:59.77#ibcon#about to read 5, iclass 12, count 2 2006.286.03:37:59.77#ibcon#read 5, iclass 12, count 2 2006.286.03:37:59.77#ibcon#about to read 6, iclass 12, count 2 2006.286.03:37:59.77#ibcon#read 6, iclass 12, count 2 2006.286.03:37:59.77#ibcon#end of sib2, iclass 12, count 2 2006.286.03:37:59.77#ibcon#*mode == 0, iclass 12, count 2 2006.286.03:37:59.77#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.03:37:59.77#ibcon#[25=AT01-07\r\n] 2006.286.03:37:59.77#ibcon#*before write, iclass 12, count 2 2006.286.03:37:59.77#ibcon#enter sib2, iclass 12, count 2 2006.286.03:37:59.77#ibcon#flushed, iclass 12, count 2 2006.286.03:37:59.77#ibcon#about to write, iclass 12, count 2 2006.286.03:37:59.77#ibcon#wrote, iclass 12, count 2 2006.286.03:37:59.77#ibcon#about to read 3, iclass 12, count 2 2006.286.03:37:59.80#ibcon#read 3, iclass 12, count 2 2006.286.03:37:59.80#ibcon#about to read 4, iclass 12, count 2 2006.286.03:37:59.80#ibcon#read 4, iclass 12, count 2 2006.286.03:37:59.80#ibcon#about to read 5, iclass 12, count 2 2006.286.03:37:59.80#ibcon#read 5, iclass 12, count 2 2006.286.03:37:59.80#ibcon#about to read 6, iclass 12, count 2 2006.286.03:37:59.80#ibcon#read 6, iclass 12, count 2 2006.286.03:37:59.80#ibcon#end of sib2, iclass 12, count 2 2006.286.03:37:59.80#ibcon#*after write, iclass 12, count 2 2006.286.03:37:59.80#ibcon#*before return 0, iclass 12, count 2 2006.286.03:37:59.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:37:59.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:37:59.80#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.03:37:59.80#ibcon#ireg 7 cls_cnt 0 2006.286.03:37:59.80#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:37:59.92#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:37:59.92#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:37:59.92#ibcon#enter wrdev, iclass 12, count 0 2006.286.03:37:59.92#ibcon#first serial, iclass 12, count 0 2006.286.03:37:59.92#ibcon#enter sib2, iclass 12, count 0 2006.286.03:37:59.92#ibcon#flushed, iclass 12, count 0 2006.286.03:37:59.92#ibcon#about to write, iclass 12, count 0 2006.286.03:37:59.92#ibcon#wrote, iclass 12, count 0 2006.286.03:37:59.92#ibcon#about to read 3, iclass 12, count 0 2006.286.03:37:59.94#ibcon#read 3, iclass 12, count 0 2006.286.03:37:59.94#ibcon#about to read 4, iclass 12, count 0 2006.286.03:37:59.94#ibcon#read 4, iclass 12, count 0 2006.286.03:37:59.94#ibcon#about to read 5, iclass 12, count 0 2006.286.03:37:59.94#ibcon#read 5, iclass 12, count 0 2006.286.03:37:59.94#ibcon#about to read 6, iclass 12, count 0 2006.286.03:37:59.94#ibcon#read 6, iclass 12, count 0 2006.286.03:37:59.94#ibcon#end of sib2, iclass 12, count 0 2006.286.03:37:59.94#ibcon#*mode == 0, iclass 12, count 0 2006.286.03:37:59.94#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.03:37:59.94#ibcon#[25=USB\r\n] 2006.286.03:37:59.94#ibcon#*before write, iclass 12, count 0 2006.286.03:37:59.94#ibcon#enter sib2, iclass 12, count 0 2006.286.03:37:59.94#ibcon#flushed, iclass 12, count 0 2006.286.03:37:59.94#ibcon#about to write, iclass 12, count 0 2006.286.03:37:59.94#ibcon#wrote, iclass 12, count 0 2006.286.03:37:59.94#ibcon#about to read 3, iclass 12, count 0 2006.286.03:37:59.97#ibcon#read 3, iclass 12, count 0 2006.286.03:37:59.97#ibcon#about to read 4, iclass 12, count 0 2006.286.03:37:59.97#ibcon#read 4, iclass 12, count 0 2006.286.03:37:59.97#ibcon#about to read 5, iclass 12, count 0 2006.286.03:37:59.97#ibcon#read 5, iclass 12, count 0 2006.286.03:37:59.97#ibcon#about to read 6, iclass 12, count 0 2006.286.03:37:59.97#ibcon#read 6, iclass 12, count 0 2006.286.03:37:59.97#ibcon#end of sib2, iclass 12, count 0 2006.286.03:37:59.97#ibcon#*after write, iclass 12, count 0 2006.286.03:37:59.97#ibcon#*before return 0, iclass 12, count 0 2006.286.03:37:59.97#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:37:59.97#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:37:59.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.03:37:59.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.03:37:59.97$vck44/valo=2,534.99 2006.286.03:37:59.97#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.03:37:59.97#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.03:37:59.97#ibcon#ireg 17 cls_cnt 0 2006.286.03:37:59.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:37:59.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:37:59.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:37:59.97#ibcon#enter wrdev, iclass 14, count 0 2006.286.03:37:59.97#ibcon#first serial, iclass 14, count 0 2006.286.03:37:59.97#ibcon#enter sib2, iclass 14, count 0 2006.286.03:37:59.97#ibcon#flushed, iclass 14, count 0 2006.286.03:37:59.97#ibcon#about to write, iclass 14, count 0 2006.286.03:37:59.97#ibcon#wrote, iclass 14, count 0 2006.286.03:37:59.97#ibcon#about to read 3, iclass 14, count 0 2006.286.03:37:59.99#ibcon#read 3, iclass 14, count 0 2006.286.03:37:59.99#ibcon#about to read 4, iclass 14, count 0 2006.286.03:37:59.99#ibcon#read 4, iclass 14, count 0 2006.286.03:37:59.99#ibcon#about to read 5, iclass 14, count 0 2006.286.03:37:59.99#ibcon#read 5, iclass 14, count 0 2006.286.03:37:59.99#ibcon#about to read 6, iclass 14, count 0 2006.286.03:37:59.99#ibcon#read 6, iclass 14, count 0 2006.286.03:37:59.99#ibcon#end of sib2, iclass 14, count 0 2006.286.03:37:59.99#ibcon#*mode == 0, iclass 14, count 0 2006.286.03:37:59.99#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.03:37:59.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.03:37:59.99#ibcon#*before write, iclass 14, count 0 2006.286.03:37:59.99#ibcon#enter sib2, iclass 14, count 0 2006.286.03:37:59.99#ibcon#flushed, iclass 14, count 0 2006.286.03:37:59.99#ibcon#about to write, iclass 14, count 0 2006.286.03:37:59.99#ibcon#wrote, iclass 14, count 0 2006.286.03:37:59.99#ibcon#about to read 3, iclass 14, count 0 2006.286.03:38:00.03#ibcon#read 3, iclass 14, count 0 2006.286.03:38:00.03#ibcon#about to read 4, iclass 14, count 0 2006.286.03:38:00.03#ibcon#read 4, iclass 14, count 0 2006.286.03:38:00.03#ibcon#about to read 5, iclass 14, count 0 2006.286.03:38:00.03#ibcon#read 5, iclass 14, count 0 2006.286.03:38:00.03#ibcon#about to read 6, iclass 14, count 0 2006.286.03:38:00.03#ibcon#read 6, iclass 14, count 0 2006.286.03:38:00.03#ibcon#end of sib2, iclass 14, count 0 2006.286.03:38:00.03#ibcon#*after write, iclass 14, count 0 2006.286.03:38:00.03#ibcon#*before return 0, iclass 14, count 0 2006.286.03:38:00.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:38:00.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:38:00.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.03:38:00.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.03:38:00.03$vck44/va=2,6 2006.286.03:38:00.03#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.03:38:00.03#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.03:38:00.03#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:00.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:38:00.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:38:00.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:38:00.09#ibcon#enter wrdev, iclass 16, count 2 2006.286.03:38:00.09#ibcon#first serial, iclass 16, count 2 2006.286.03:38:00.09#ibcon#enter sib2, iclass 16, count 2 2006.286.03:38:00.09#ibcon#flushed, iclass 16, count 2 2006.286.03:38:00.09#ibcon#about to write, iclass 16, count 2 2006.286.03:38:00.09#ibcon#wrote, iclass 16, count 2 2006.286.03:38:00.09#ibcon#about to read 3, iclass 16, count 2 2006.286.03:38:00.11#ibcon#read 3, iclass 16, count 2 2006.286.03:38:00.11#ibcon#about to read 4, iclass 16, count 2 2006.286.03:38:00.11#ibcon#read 4, iclass 16, count 2 2006.286.03:38:00.11#ibcon#about to read 5, iclass 16, count 2 2006.286.03:38:00.11#ibcon#read 5, iclass 16, count 2 2006.286.03:38:00.11#ibcon#about to read 6, iclass 16, count 2 2006.286.03:38:00.11#ibcon#read 6, iclass 16, count 2 2006.286.03:38:00.11#ibcon#end of sib2, iclass 16, count 2 2006.286.03:38:00.11#ibcon#*mode == 0, iclass 16, count 2 2006.286.03:38:00.11#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.03:38:00.11#ibcon#[25=AT02-06\r\n] 2006.286.03:38:00.11#ibcon#*before write, iclass 16, count 2 2006.286.03:38:00.11#ibcon#enter sib2, iclass 16, count 2 2006.286.03:38:00.11#ibcon#flushed, iclass 16, count 2 2006.286.03:38:00.11#ibcon#about to write, iclass 16, count 2 2006.286.03:38:00.11#ibcon#wrote, iclass 16, count 2 2006.286.03:38:00.11#ibcon#about to read 3, iclass 16, count 2 2006.286.03:38:00.14#ibcon#read 3, iclass 16, count 2 2006.286.03:38:00.14#ibcon#about to read 4, iclass 16, count 2 2006.286.03:38:00.14#ibcon#read 4, iclass 16, count 2 2006.286.03:38:00.14#ibcon#about to read 5, iclass 16, count 2 2006.286.03:38:00.14#ibcon#read 5, iclass 16, count 2 2006.286.03:38:00.14#ibcon#about to read 6, iclass 16, count 2 2006.286.03:38:00.14#ibcon#read 6, iclass 16, count 2 2006.286.03:38:00.14#ibcon#end of sib2, iclass 16, count 2 2006.286.03:38:00.14#ibcon#*after write, iclass 16, count 2 2006.286.03:38:00.14#ibcon#*before return 0, iclass 16, count 2 2006.286.03:38:00.14#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:38:00.14#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:38:00.14#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.03:38:00.14#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:00.14#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:38:00.26#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:38:00.26#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:38:00.26#ibcon#enter wrdev, iclass 16, count 0 2006.286.03:38:00.26#ibcon#first serial, iclass 16, count 0 2006.286.03:38:00.26#ibcon#enter sib2, iclass 16, count 0 2006.286.03:38:00.26#ibcon#flushed, iclass 16, count 0 2006.286.03:38:00.26#ibcon#about to write, iclass 16, count 0 2006.286.03:38:00.26#ibcon#wrote, iclass 16, count 0 2006.286.03:38:00.26#ibcon#about to read 3, iclass 16, count 0 2006.286.03:38:00.28#ibcon#read 3, iclass 16, count 0 2006.286.03:38:00.28#ibcon#about to read 4, iclass 16, count 0 2006.286.03:38:00.28#ibcon#read 4, iclass 16, count 0 2006.286.03:38:00.28#ibcon#about to read 5, iclass 16, count 0 2006.286.03:38:00.28#ibcon#read 5, iclass 16, count 0 2006.286.03:38:00.28#ibcon#about to read 6, iclass 16, count 0 2006.286.03:38:00.28#ibcon#read 6, iclass 16, count 0 2006.286.03:38:00.28#ibcon#end of sib2, iclass 16, count 0 2006.286.03:38:00.28#ibcon#*mode == 0, iclass 16, count 0 2006.286.03:38:00.28#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.03:38:00.28#ibcon#[25=USB\r\n] 2006.286.03:38:00.28#ibcon#*before write, iclass 16, count 0 2006.286.03:38:00.28#ibcon#enter sib2, iclass 16, count 0 2006.286.03:38:00.28#ibcon#flushed, iclass 16, count 0 2006.286.03:38:00.28#ibcon#about to write, iclass 16, count 0 2006.286.03:38:00.28#ibcon#wrote, iclass 16, count 0 2006.286.03:38:00.28#ibcon#about to read 3, iclass 16, count 0 2006.286.03:38:00.31#ibcon#read 3, iclass 16, count 0 2006.286.03:38:00.31#ibcon#about to read 4, iclass 16, count 0 2006.286.03:38:00.31#ibcon#read 4, iclass 16, count 0 2006.286.03:38:00.31#ibcon#about to read 5, iclass 16, count 0 2006.286.03:38:00.31#ibcon#read 5, iclass 16, count 0 2006.286.03:38:00.31#ibcon#about to read 6, iclass 16, count 0 2006.286.03:38:00.31#ibcon#read 6, iclass 16, count 0 2006.286.03:38:00.31#ibcon#end of sib2, iclass 16, count 0 2006.286.03:38:00.31#ibcon#*after write, iclass 16, count 0 2006.286.03:38:00.31#ibcon#*before return 0, iclass 16, count 0 2006.286.03:38:00.31#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:38:00.31#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:38:00.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.03:38:00.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.03:38:00.31$vck44/valo=3,564.99 2006.286.03:38:00.31#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.03:38:00.31#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.03:38:00.31#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:00.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:38:00.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:38:00.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:38:00.31#ibcon#enter wrdev, iclass 18, count 0 2006.286.03:38:00.31#ibcon#first serial, iclass 18, count 0 2006.286.03:38:00.31#ibcon#enter sib2, iclass 18, count 0 2006.286.03:38:00.31#ibcon#flushed, iclass 18, count 0 2006.286.03:38:00.31#ibcon#about to write, iclass 18, count 0 2006.286.03:38:00.31#ibcon#wrote, iclass 18, count 0 2006.286.03:38:00.31#ibcon#about to read 3, iclass 18, count 0 2006.286.03:38:00.33#ibcon#read 3, iclass 18, count 0 2006.286.03:38:00.33#ibcon#about to read 4, iclass 18, count 0 2006.286.03:38:00.33#ibcon#read 4, iclass 18, count 0 2006.286.03:38:00.33#ibcon#about to read 5, iclass 18, count 0 2006.286.03:38:00.33#ibcon#read 5, iclass 18, count 0 2006.286.03:38:00.33#ibcon#about to read 6, iclass 18, count 0 2006.286.03:38:00.33#ibcon#read 6, iclass 18, count 0 2006.286.03:38:00.33#ibcon#end of sib2, iclass 18, count 0 2006.286.03:38:00.33#ibcon#*mode == 0, iclass 18, count 0 2006.286.03:38:00.33#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.03:38:00.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.03:38:00.33#ibcon#*before write, iclass 18, count 0 2006.286.03:38:00.33#ibcon#enter sib2, iclass 18, count 0 2006.286.03:38:00.33#ibcon#flushed, iclass 18, count 0 2006.286.03:38:00.33#ibcon#about to write, iclass 18, count 0 2006.286.03:38:00.33#ibcon#wrote, iclass 18, count 0 2006.286.03:38:00.33#ibcon#about to read 3, iclass 18, count 0 2006.286.03:38:00.37#ibcon#read 3, iclass 18, count 0 2006.286.03:38:00.37#ibcon#about to read 4, iclass 18, count 0 2006.286.03:38:00.37#ibcon#read 4, iclass 18, count 0 2006.286.03:38:00.37#ibcon#about to read 5, iclass 18, count 0 2006.286.03:38:00.37#ibcon#read 5, iclass 18, count 0 2006.286.03:38:00.37#ibcon#about to read 6, iclass 18, count 0 2006.286.03:38:00.37#ibcon#read 6, iclass 18, count 0 2006.286.03:38:00.37#ibcon#end of sib2, iclass 18, count 0 2006.286.03:38:00.37#ibcon#*after write, iclass 18, count 0 2006.286.03:38:00.37#ibcon#*before return 0, iclass 18, count 0 2006.286.03:38:00.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:38:00.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:38:00.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.03:38:00.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.03:38:00.37$vck44/va=3,7 2006.286.03:38:00.37#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.03:38:00.37#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.03:38:00.37#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:00.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:38:00.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:38:00.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:38:00.43#ibcon#enter wrdev, iclass 20, count 2 2006.286.03:38:00.43#ibcon#first serial, iclass 20, count 2 2006.286.03:38:00.43#ibcon#enter sib2, iclass 20, count 2 2006.286.03:38:00.43#ibcon#flushed, iclass 20, count 2 2006.286.03:38:00.43#ibcon#about to write, iclass 20, count 2 2006.286.03:38:00.43#ibcon#wrote, iclass 20, count 2 2006.286.03:38:00.43#ibcon#about to read 3, iclass 20, count 2 2006.286.03:38:00.45#ibcon#read 3, iclass 20, count 2 2006.286.03:38:00.45#ibcon#about to read 4, iclass 20, count 2 2006.286.03:38:00.45#ibcon#read 4, iclass 20, count 2 2006.286.03:38:00.45#ibcon#about to read 5, iclass 20, count 2 2006.286.03:38:00.45#ibcon#read 5, iclass 20, count 2 2006.286.03:38:00.45#ibcon#about to read 6, iclass 20, count 2 2006.286.03:38:00.45#ibcon#read 6, iclass 20, count 2 2006.286.03:38:00.45#ibcon#end of sib2, iclass 20, count 2 2006.286.03:38:00.45#ibcon#*mode == 0, iclass 20, count 2 2006.286.03:38:00.45#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.03:38:00.45#ibcon#[25=AT03-07\r\n] 2006.286.03:38:00.45#ibcon#*before write, iclass 20, count 2 2006.286.03:38:00.45#ibcon#enter sib2, iclass 20, count 2 2006.286.03:38:00.45#ibcon#flushed, iclass 20, count 2 2006.286.03:38:00.45#ibcon#about to write, iclass 20, count 2 2006.286.03:38:00.45#ibcon#wrote, iclass 20, count 2 2006.286.03:38:00.45#ibcon#about to read 3, iclass 20, count 2 2006.286.03:38:00.48#ibcon#read 3, iclass 20, count 2 2006.286.03:38:00.48#ibcon#about to read 4, iclass 20, count 2 2006.286.03:38:00.48#ibcon#read 4, iclass 20, count 2 2006.286.03:38:00.48#ibcon#about to read 5, iclass 20, count 2 2006.286.03:38:00.48#ibcon#read 5, iclass 20, count 2 2006.286.03:38:00.48#ibcon#about to read 6, iclass 20, count 2 2006.286.03:38:00.48#ibcon#read 6, iclass 20, count 2 2006.286.03:38:00.48#ibcon#end of sib2, iclass 20, count 2 2006.286.03:38:00.48#ibcon#*after write, iclass 20, count 2 2006.286.03:38:00.48#ibcon#*before return 0, iclass 20, count 2 2006.286.03:38:00.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:38:00.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:38:00.48#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.03:38:00.48#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:00.48#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:38:00.60#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:38:00.60#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:38:00.60#ibcon#enter wrdev, iclass 20, count 0 2006.286.03:38:00.60#ibcon#first serial, iclass 20, count 0 2006.286.03:38:00.60#ibcon#enter sib2, iclass 20, count 0 2006.286.03:38:00.60#ibcon#flushed, iclass 20, count 0 2006.286.03:38:00.60#ibcon#about to write, iclass 20, count 0 2006.286.03:38:00.60#ibcon#wrote, iclass 20, count 0 2006.286.03:38:00.60#ibcon#about to read 3, iclass 20, count 0 2006.286.03:38:00.62#ibcon#read 3, iclass 20, count 0 2006.286.03:38:00.62#ibcon#about to read 4, iclass 20, count 0 2006.286.03:38:00.62#ibcon#read 4, iclass 20, count 0 2006.286.03:38:00.62#ibcon#about to read 5, iclass 20, count 0 2006.286.03:38:00.62#ibcon#read 5, iclass 20, count 0 2006.286.03:38:00.62#ibcon#about to read 6, iclass 20, count 0 2006.286.03:38:00.62#ibcon#read 6, iclass 20, count 0 2006.286.03:38:00.62#ibcon#end of sib2, iclass 20, count 0 2006.286.03:38:00.62#ibcon#*mode == 0, iclass 20, count 0 2006.286.03:38:00.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.03:38:00.62#ibcon#[25=USB\r\n] 2006.286.03:38:00.62#ibcon#*before write, iclass 20, count 0 2006.286.03:38:00.62#ibcon#enter sib2, iclass 20, count 0 2006.286.03:38:00.62#ibcon#flushed, iclass 20, count 0 2006.286.03:38:00.62#ibcon#about to write, iclass 20, count 0 2006.286.03:38:00.62#ibcon#wrote, iclass 20, count 0 2006.286.03:38:00.62#ibcon#about to read 3, iclass 20, count 0 2006.286.03:38:00.65#ibcon#read 3, iclass 20, count 0 2006.286.03:38:00.65#ibcon#about to read 4, iclass 20, count 0 2006.286.03:38:00.65#ibcon#read 4, iclass 20, count 0 2006.286.03:38:00.65#ibcon#about to read 5, iclass 20, count 0 2006.286.03:38:00.65#ibcon#read 5, iclass 20, count 0 2006.286.03:38:00.65#ibcon#about to read 6, iclass 20, count 0 2006.286.03:38:00.65#ibcon#read 6, iclass 20, count 0 2006.286.03:38:00.65#ibcon#end of sib2, iclass 20, count 0 2006.286.03:38:00.65#ibcon#*after write, iclass 20, count 0 2006.286.03:38:00.65#ibcon#*before return 0, iclass 20, count 0 2006.286.03:38:00.65#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:38:00.65#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:38:00.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.03:38:00.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.03:38:00.65$vck44/valo=4,624.99 2006.286.03:38:00.65#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.03:38:00.65#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.03:38:00.65#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:00.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:38:00.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:38:00.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:38:00.65#ibcon#enter wrdev, iclass 22, count 0 2006.286.03:38:00.65#ibcon#first serial, iclass 22, count 0 2006.286.03:38:00.65#ibcon#enter sib2, iclass 22, count 0 2006.286.03:38:00.65#ibcon#flushed, iclass 22, count 0 2006.286.03:38:00.65#ibcon#about to write, iclass 22, count 0 2006.286.03:38:00.65#ibcon#wrote, iclass 22, count 0 2006.286.03:38:00.65#ibcon#about to read 3, iclass 22, count 0 2006.286.03:38:00.67#ibcon#read 3, iclass 22, count 0 2006.286.03:38:00.67#ibcon#about to read 4, iclass 22, count 0 2006.286.03:38:00.67#ibcon#read 4, iclass 22, count 0 2006.286.03:38:00.67#ibcon#about to read 5, iclass 22, count 0 2006.286.03:38:00.67#ibcon#read 5, iclass 22, count 0 2006.286.03:38:00.67#ibcon#about to read 6, iclass 22, count 0 2006.286.03:38:00.67#ibcon#read 6, iclass 22, count 0 2006.286.03:38:00.67#ibcon#end of sib2, iclass 22, count 0 2006.286.03:38:00.67#ibcon#*mode == 0, iclass 22, count 0 2006.286.03:38:00.67#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.03:38:00.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.03:38:00.67#ibcon#*before write, iclass 22, count 0 2006.286.03:38:00.67#ibcon#enter sib2, iclass 22, count 0 2006.286.03:38:00.67#ibcon#flushed, iclass 22, count 0 2006.286.03:38:00.67#ibcon#about to write, iclass 22, count 0 2006.286.03:38:00.67#ibcon#wrote, iclass 22, count 0 2006.286.03:38:00.67#ibcon#about to read 3, iclass 22, count 0 2006.286.03:38:00.71#ibcon#read 3, iclass 22, count 0 2006.286.03:38:00.71#ibcon#about to read 4, iclass 22, count 0 2006.286.03:38:00.71#ibcon#read 4, iclass 22, count 0 2006.286.03:38:00.71#ibcon#about to read 5, iclass 22, count 0 2006.286.03:38:00.71#ibcon#read 5, iclass 22, count 0 2006.286.03:38:00.71#ibcon#about to read 6, iclass 22, count 0 2006.286.03:38:00.71#ibcon#read 6, iclass 22, count 0 2006.286.03:38:00.71#ibcon#end of sib2, iclass 22, count 0 2006.286.03:38:00.71#ibcon#*after write, iclass 22, count 0 2006.286.03:38:00.71#ibcon#*before return 0, iclass 22, count 0 2006.286.03:38:00.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:38:00.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:38:00.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.03:38:00.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.03:38:00.71$vck44/va=4,6 2006.286.03:38:00.71#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.03:38:00.71#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.03:38:00.71#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:00.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:38:00.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:38:00.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:38:00.77#ibcon#enter wrdev, iclass 24, count 2 2006.286.03:38:00.77#ibcon#first serial, iclass 24, count 2 2006.286.03:38:00.77#ibcon#enter sib2, iclass 24, count 2 2006.286.03:38:00.77#ibcon#flushed, iclass 24, count 2 2006.286.03:38:00.77#ibcon#about to write, iclass 24, count 2 2006.286.03:38:00.77#ibcon#wrote, iclass 24, count 2 2006.286.03:38:00.77#ibcon#about to read 3, iclass 24, count 2 2006.286.03:38:00.79#ibcon#read 3, iclass 24, count 2 2006.286.03:38:00.79#ibcon#about to read 4, iclass 24, count 2 2006.286.03:38:00.79#ibcon#read 4, iclass 24, count 2 2006.286.03:38:00.79#ibcon#about to read 5, iclass 24, count 2 2006.286.03:38:00.79#ibcon#read 5, iclass 24, count 2 2006.286.03:38:00.79#ibcon#about to read 6, iclass 24, count 2 2006.286.03:38:00.79#ibcon#read 6, iclass 24, count 2 2006.286.03:38:00.79#ibcon#end of sib2, iclass 24, count 2 2006.286.03:38:00.79#ibcon#*mode == 0, iclass 24, count 2 2006.286.03:38:00.79#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.03:38:00.79#ibcon#[25=AT04-06\r\n] 2006.286.03:38:00.79#ibcon#*before write, iclass 24, count 2 2006.286.03:38:00.79#ibcon#enter sib2, iclass 24, count 2 2006.286.03:38:00.79#ibcon#flushed, iclass 24, count 2 2006.286.03:38:00.79#ibcon#about to write, iclass 24, count 2 2006.286.03:38:00.79#ibcon#wrote, iclass 24, count 2 2006.286.03:38:00.79#ibcon#about to read 3, iclass 24, count 2 2006.286.03:38:00.82#ibcon#read 3, iclass 24, count 2 2006.286.03:38:01.23#ibcon#about to read 4, iclass 24, count 2 2006.286.03:38:01.23#ibcon#read 4, iclass 24, count 2 2006.286.03:38:01.23#ibcon#about to read 5, iclass 24, count 2 2006.286.03:38:01.23#ibcon#read 5, iclass 24, count 2 2006.286.03:38:01.23#ibcon#about to read 6, iclass 24, count 2 2006.286.03:38:01.23#ibcon#read 6, iclass 24, count 2 2006.286.03:38:01.23#ibcon#end of sib2, iclass 24, count 2 2006.286.03:38:01.23#ibcon#*after write, iclass 24, count 2 2006.286.03:38:01.23#ibcon#*before return 0, iclass 24, count 2 2006.286.03:38:01.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:38:01.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:38:01.23#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.03:38:01.23#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:01.23#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:38:01.35#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:38:01.35#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:38:01.35#ibcon#enter wrdev, iclass 24, count 0 2006.286.03:38:01.35#ibcon#first serial, iclass 24, count 0 2006.286.03:38:01.35#ibcon#enter sib2, iclass 24, count 0 2006.286.03:38:01.35#ibcon#flushed, iclass 24, count 0 2006.286.03:38:01.35#ibcon#about to write, iclass 24, count 0 2006.286.03:38:01.35#ibcon#wrote, iclass 24, count 0 2006.286.03:38:01.35#ibcon#about to read 3, iclass 24, count 0 2006.286.03:38:01.37#ibcon#read 3, iclass 24, count 0 2006.286.03:38:01.37#ibcon#about to read 4, iclass 24, count 0 2006.286.03:38:01.37#ibcon#read 4, iclass 24, count 0 2006.286.03:38:01.37#ibcon#about to read 5, iclass 24, count 0 2006.286.03:38:01.37#ibcon#read 5, iclass 24, count 0 2006.286.03:38:01.37#ibcon#about to read 6, iclass 24, count 0 2006.286.03:38:01.37#ibcon#read 6, iclass 24, count 0 2006.286.03:38:01.37#ibcon#end of sib2, iclass 24, count 0 2006.286.03:38:01.37#ibcon#*mode == 0, iclass 24, count 0 2006.286.03:38:01.37#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.03:38:01.37#ibcon#[25=USB\r\n] 2006.286.03:38:01.37#ibcon#*before write, iclass 24, count 0 2006.286.03:38:01.37#ibcon#enter sib2, iclass 24, count 0 2006.286.03:38:01.37#ibcon#flushed, iclass 24, count 0 2006.286.03:38:01.37#ibcon#about to write, iclass 24, count 0 2006.286.03:38:01.37#ibcon#wrote, iclass 24, count 0 2006.286.03:38:01.37#ibcon#about to read 3, iclass 24, count 0 2006.286.03:38:01.40#ibcon#read 3, iclass 24, count 0 2006.286.03:38:01.40#ibcon#about to read 4, iclass 24, count 0 2006.286.03:38:01.40#ibcon#read 4, iclass 24, count 0 2006.286.03:38:01.40#ibcon#about to read 5, iclass 24, count 0 2006.286.03:38:01.40#ibcon#read 5, iclass 24, count 0 2006.286.03:38:01.40#ibcon#about to read 6, iclass 24, count 0 2006.286.03:38:01.40#ibcon#read 6, iclass 24, count 0 2006.286.03:38:01.40#ibcon#end of sib2, iclass 24, count 0 2006.286.03:38:01.40#ibcon#*after write, iclass 24, count 0 2006.286.03:38:01.40#ibcon#*before return 0, iclass 24, count 0 2006.286.03:38:01.40#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:38:01.40#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:38:01.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.03:38:01.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.03:38:01.40$vck44/valo=5,734.99 2006.286.03:38:01.40#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.03:38:01.40#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.03:38:01.40#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:01.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:38:01.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:38:01.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:38:01.40#ibcon#enter wrdev, iclass 26, count 0 2006.286.03:38:01.40#ibcon#first serial, iclass 26, count 0 2006.286.03:38:01.40#ibcon#enter sib2, iclass 26, count 0 2006.286.03:38:01.40#ibcon#flushed, iclass 26, count 0 2006.286.03:38:01.40#ibcon#about to write, iclass 26, count 0 2006.286.03:38:01.40#ibcon#wrote, iclass 26, count 0 2006.286.03:38:01.40#ibcon#about to read 3, iclass 26, count 0 2006.286.03:38:01.42#ibcon#read 3, iclass 26, count 0 2006.286.03:38:01.42#ibcon#about to read 4, iclass 26, count 0 2006.286.03:38:01.42#ibcon#read 4, iclass 26, count 0 2006.286.03:38:01.42#ibcon#about to read 5, iclass 26, count 0 2006.286.03:38:01.42#ibcon#read 5, iclass 26, count 0 2006.286.03:38:01.42#ibcon#about to read 6, iclass 26, count 0 2006.286.03:38:01.42#ibcon#read 6, iclass 26, count 0 2006.286.03:38:01.42#ibcon#end of sib2, iclass 26, count 0 2006.286.03:38:01.42#ibcon#*mode == 0, iclass 26, count 0 2006.286.03:38:01.42#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.03:38:01.42#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.03:38:01.42#ibcon#*before write, iclass 26, count 0 2006.286.03:38:01.42#ibcon#enter sib2, iclass 26, count 0 2006.286.03:38:01.42#ibcon#flushed, iclass 26, count 0 2006.286.03:38:01.42#ibcon#about to write, iclass 26, count 0 2006.286.03:38:01.42#ibcon#wrote, iclass 26, count 0 2006.286.03:38:01.42#ibcon#about to read 3, iclass 26, count 0 2006.286.03:38:01.46#ibcon#read 3, iclass 26, count 0 2006.286.03:38:01.46#ibcon#about to read 4, iclass 26, count 0 2006.286.03:38:01.46#ibcon#read 4, iclass 26, count 0 2006.286.03:38:01.46#ibcon#about to read 5, iclass 26, count 0 2006.286.03:38:01.46#ibcon#read 5, iclass 26, count 0 2006.286.03:38:01.46#ibcon#about to read 6, iclass 26, count 0 2006.286.03:38:01.46#ibcon#read 6, iclass 26, count 0 2006.286.03:38:01.46#ibcon#end of sib2, iclass 26, count 0 2006.286.03:38:01.46#ibcon#*after write, iclass 26, count 0 2006.286.03:38:01.46#ibcon#*before return 0, iclass 26, count 0 2006.286.03:38:01.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:38:01.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:38:01.46#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.03:38:01.46#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.03:38:01.46$vck44/va=5,3 2006.286.03:38:01.46#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.03:38:01.46#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.03:38:01.46#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:01.46#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:38:01.52#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:38:01.52#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:38:01.52#ibcon#enter wrdev, iclass 28, count 2 2006.286.03:38:01.52#ibcon#first serial, iclass 28, count 2 2006.286.03:38:01.52#ibcon#enter sib2, iclass 28, count 2 2006.286.03:38:01.52#ibcon#flushed, iclass 28, count 2 2006.286.03:38:01.52#ibcon#about to write, iclass 28, count 2 2006.286.03:38:01.52#ibcon#wrote, iclass 28, count 2 2006.286.03:38:01.52#ibcon#about to read 3, iclass 28, count 2 2006.286.03:38:01.54#ibcon#read 3, iclass 28, count 2 2006.286.03:38:01.95#ibcon#about to read 4, iclass 28, count 2 2006.286.03:38:01.95#ibcon#read 4, iclass 28, count 2 2006.286.03:38:01.95#ibcon#about to read 5, iclass 28, count 2 2006.286.03:38:01.95#ibcon#read 5, iclass 28, count 2 2006.286.03:38:01.95#ibcon#about to read 6, iclass 28, count 2 2006.286.03:38:01.95#ibcon#read 6, iclass 28, count 2 2006.286.03:38:01.95#ibcon#end of sib2, iclass 28, count 2 2006.286.03:38:01.95#ibcon#*mode == 0, iclass 28, count 2 2006.286.03:38:01.95#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.03:38:01.95#ibcon#[25=AT05-03\r\n] 2006.286.03:38:01.95#ibcon#*before write, iclass 28, count 2 2006.286.03:38:01.95#ibcon#enter sib2, iclass 28, count 2 2006.286.03:38:01.95#ibcon#flushed, iclass 28, count 2 2006.286.03:38:01.95#ibcon#about to write, iclass 28, count 2 2006.286.03:38:01.95#ibcon#wrote, iclass 28, count 2 2006.286.03:38:01.95#ibcon#about to read 3, iclass 28, count 2 2006.286.03:38:01.98#ibcon#read 3, iclass 28, count 2 2006.286.03:38:01.98#ibcon#about to read 4, iclass 28, count 2 2006.286.03:38:01.98#ibcon#read 4, iclass 28, count 2 2006.286.03:38:01.98#ibcon#about to read 5, iclass 28, count 2 2006.286.03:38:01.98#ibcon#read 5, iclass 28, count 2 2006.286.03:38:01.98#ibcon#about to read 6, iclass 28, count 2 2006.286.03:38:01.98#ibcon#read 6, iclass 28, count 2 2006.286.03:38:01.98#ibcon#end of sib2, iclass 28, count 2 2006.286.03:38:01.98#ibcon#*after write, iclass 28, count 2 2006.286.03:38:01.98#ibcon#*before return 0, iclass 28, count 2 2006.286.03:38:01.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:38:01.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:38:01.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.03:38:01.98#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:01.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:38:02.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:38:02.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:38:02.10#ibcon#enter wrdev, iclass 28, count 0 2006.286.03:38:02.10#ibcon#first serial, iclass 28, count 0 2006.286.03:38:02.10#ibcon#enter sib2, iclass 28, count 0 2006.286.03:38:02.10#ibcon#flushed, iclass 28, count 0 2006.286.03:38:02.10#ibcon#about to write, iclass 28, count 0 2006.286.03:38:02.10#ibcon#wrote, iclass 28, count 0 2006.286.03:38:02.10#ibcon#about to read 3, iclass 28, count 0 2006.286.03:38:02.12#ibcon#read 3, iclass 28, count 0 2006.286.03:38:02.12#ibcon#about to read 4, iclass 28, count 0 2006.286.03:38:02.12#ibcon#read 4, iclass 28, count 0 2006.286.03:38:02.12#ibcon#about to read 5, iclass 28, count 0 2006.286.03:38:02.12#ibcon#read 5, iclass 28, count 0 2006.286.03:38:02.12#ibcon#about to read 6, iclass 28, count 0 2006.286.03:38:02.12#ibcon#read 6, iclass 28, count 0 2006.286.03:38:02.12#ibcon#end of sib2, iclass 28, count 0 2006.286.03:38:02.12#ibcon#*mode == 0, iclass 28, count 0 2006.286.03:38:02.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.03:38:02.12#ibcon#[25=USB\r\n] 2006.286.03:38:02.12#ibcon#*before write, iclass 28, count 0 2006.286.03:38:02.12#ibcon#enter sib2, iclass 28, count 0 2006.286.03:38:02.12#ibcon#flushed, iclass 28, count 0 2006.286.03:38:02.12#ibcon#about to write, iclass 28, count 0 2006.286.03:38:02.12#ibcon#wrote, iclass 28, count 0 2006.286.03:38:02.12#ibcon#about to read 3, iclass 28, count 0 2006.286.03:38:02.15#ibcon#read 3, iclass 28, count 0 2006.286.03:38:02.15#ibcon#about to read 4, iclass 28, count 0 2006.286.03:38:02.15#ibcon#read 4, iclass 28, count 0 2006.286.03:38:02.15#ibcon#about to read 5, iclass 28, count 0 2006.286.03:38:02.15#ibcon#read 5, iclass 28, count 0 2006.286.03:38:02.15#ibcon#about to read 6, iclass 28, count 0 2006.286.03:38:02.15#ibcon#read 6, iclass 28, count 0 2006.286.03:38:02.15#ibcon#end of sib2, iclass 28, count 0 2006.286.03:38:02.15#ibcon#*after write, iclass 28, count 0 2006.286.03:38:02.15#ibcon#*before return 0, iclass 28, count 0 2006.286.03:38:02.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:38:02.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:38:02.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.03:38:02.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.03:38:02.15$vck44/valo=6,814.99 2006.286.03:38:02.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.03:38:02.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.03:38:02.15#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:02.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:38:02.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:38:02.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:38:02.15#ibcon#enter wrdev, iclass 30, count 0 2006.286.03:38:02.15#ibcon#first serial, iclass 30, count 0 2006.286.03:38:02.15#ibcon#enter sib2, iclass 30, count 0 2006.286.03:38:02.15#ibcon#flushed, iclass 30, count 0 2006.286.03:38:02.15#ibcon#about to write, iclass 30, count 0 2006.286.03:38:02.15#ibcon#wrote, iclass 30, count 0 2006.286.03:38:02.15#ibcon#about to read 3, iclass 30, count 0 2006.286.03:38:02.17#ibcon#read 3, iclass 30, count 0 2006.286.03:38:02.17#ibcon#about to read 4, iclass 30, count 0 2006.286.03:38:02.17#ibcon#read 4, iclass 30, count 0 2006.286.03:38:02.17#ibcon#about to read 5, iclass 30, count 0 2006.286.03:38:02.17#ibcon#read 5, iclass 30, count 0 2006.286.03:38:02.17#ibcon#about to read 6, iclass 30, count 0 2006.286.03:38:02.17#ibcon#read 6, iclass 30, count 0 2006.286.03:38:02.17#ibcon#end of sib2, iclass 30, count 0 2006.286.03:38:02.17#ibcon#*mode == 0, iclass 30, count 0 2006.286.03:38:02.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.03:38:02.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.03:38:02.17#ibcon#*before write, iclass 30, count 0 2006.286.03:38:02.17#ibcon#enter sib2, iclass 30, count 0 2006.286.03:38:02.17#ibcon#flushed, iclass 30, count 0 2006.286.03:38:02.17#ibcon#about to write, iclass 30, count 0 2006.286.03:38:02.17#ibcon#wrote, iclass 30, count 0 2006.286.03:38:02.17#ibcon#about to read 3, iclass 30, count 0 2006.286.03:38:02.21#ibcon#read 3, iclass 30, count 0 2006.286.03:38:02.21#ibcon#about to read 4, iclass 30, count 0 2006.286.03:38:02.21#ibcon#read 4, iclass 30, count 0 2006.286.03:38:02.21#ibcon#about to read 5, iclass 30, count 0 2006.286.03:38:02.21#ibcon#read 5, iclass 30, count 0 2006.286.03:38:02.21#ibcon#about to read 6, iclass 30, count 0 2006.286.03:38:02.21#ibcon#read 6, iclass 30, count 0 2006.286.03:38:02.21#ibcon#end of sib2, iclass 30, count 0 2006.286.03:38:02.21#ibcon#*after write, iclass 30, count 0 2006.286.03:38:02.21#ibcon#*before return 0, iclass 30, count 0 2006.286.03:38:02.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:38:02.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:38:02.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.03:38:02.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.03:38:02.21$vck44/va=6,4 2006.286.03:38:02.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.03:38:02.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.03:38:02.21#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:02.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:38:02.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:38:02.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:38:02.27#ibcon#enter wrdev, iclass 32, count 2 2006.286.03:38:02.27#ibcon#first serial, iclass 32, count 2 2006.286.03:38:02.27#ibcon#enter sib2, iclass 32, count 2 2006.286.03:38:02.27#ibcon#flushed, iclass 32, count 2 2006.286.03:38:02.27#ibcon#about to write, iclass 32, count 2 2006.286.03:38:02.27#ibcon#wrote, iclass 32, count 2 2006.286.03:38:02.27#ibcon#about to read 3, iclass 32, count 2 2006.286.03:38:02.29#ibcon#read 3, iclass 32, count 2 2006.286.03:38:02.29#ibcon#about to read 4, iclass 32, count 2 2006.286.03:38:02.29#ibcon#read 4, iclass 32, count 2 2006.286.03:38:02.29#ibcon#about to read 5, iclass 32, count 2 2006.286.03:38:02.29#ibcon#read 5, iclass 32, count 2 2006.286.03:38:02.29#ibcon#about to read 6, iclass 32, count 2 2006.286.03:38:02.29#ibcon#read 6, iclass 32, count 2 2006.286.03:38:02.29#ibcon#end of sib2, iclass 32, count 2 2006.286.03:38:02.29#ibcon#*mode == 0, iclass 32, count 2 2006.286.03:38:02.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.03:38:02.29#ibcon#[25=AT06-04\r\n] 2006.286.03:38:02.29#ibcon#*before write, iclass 32, count 2 2006.286.03:38:02.29#ibcon#enter sib2, iclass 32, count 2 2006.286.03:38:02.29#ibcon#flushed, iclass 32, count 2 2006.286.03:38:02.29#ibcon#about to write, iclass 32, count 2 2006.286.03:38:02.29#ibcon#wrote, iclass 32, count 2 2006.286.03:38:02.29#ibcon#about to read 3, iclass 32, count 2 2006.286.03:38:02.32#ibcon#read 3, iclass 32, count 2 2006.286.03:38:02.32#ibcon#about to read 4, iclass 32, count 2 2006.286.03:38:02.32#ibcon#read 4, iclass 32, count 2 2006.286.03:38:02.32#ibcon#about to read 5, iclass 32, count 2 2006.286.03:38:02.32#ibcon#read 5, iclass 32, count 2 2006.286.03:38:02.32#ibcon#about to read 6, iclass 32, count 2 2006.286.03:38:02.32#ibcon#read 6, iclass 32, count 2 2006.286.03:38:02.32#ibcon#end of sib2, iclass 32, count 2 2006.286.03:38:02.32#ibcon#*after write, iclass 32, count 2 2006.286.03:38:02.32#ibcon#*before return 0, iclass 32, count 2 2006.286.03:38:02.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:38:02.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:38:02.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.03:38:02.32#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:02.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:38:02.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:38:02.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:38:02.46#ibcon#enter wrdev, iclass 32, count 0 2006.286.03:38:02.46#ibcon#first serial, iclass 32, count 0 2006.286.03:38:02.46#ibcon#enter sib2, iclass 32, count 0 2006.286.03:38:02.46#ibcon#flushed, iclass 32, count 0 2006.286.03:38:02.46#ibcon#about to write, iclass 32, count 0 2006.286.03:38:02.46#ibcon#wrote, iclass 32, count 0 2006.286.03:38:02.46#ibcon#about to read 3, iclass 32, count 0 2006.286.03:38:02.48#ibcon#read 3, iclass 32, count 0 2006.286.03:38:02.48#ibcon#about to read 4, iclass 32, count 0 2006.286.03:38:02.48#ibcon#read 4, iclass 32, count 0 2006.286.03:38:02.48#ibcon#about to read 5, iclass 32, count 0 2006.286.03:38:02.48#ibcon#read 5, iclass 32, count 0 2006.286.03:38:02.48#ibcon#about to read 6, iclass 32, count 0 2006.286.03:38:02.48#ibcon#read 6, iclass 32, count 0 2006.286.03:38:02.48#ibcon#end of sib2, iclass 32, count 0 2006.286.03:38:02.48#ibcon#*mode == 0, iclass 32, count 0 2006.286.03:38:02.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.03:38:02.48#ibcon#[25=USB\r\n] 2006.286.03:38:02.48#ibcon#*before write, iclass 32, count 0 2006.286.03:38:02.48#ibcon#enter sib2, iclass 32, count 0 2006.286.03:38:02.48#ibcon#flushed, iclass 32, count 0 2006.286.03:38:02.48#ibcon#about to write, iclass 32, count 0 2006.286.03:38:02.48#ibcon#wrote, iclass 32, count 0 2006.286.03:38:02.48#ibcon#about to read 3, iclass 32, count 0 2006.286.03:38:02.51#ibcon#read 3, iclass 32, count 0 2006.286.03:38:02.51#ibcon#about to read 4, iclass 32, count 0 2006.286.03:38:02.51#ibcon#read 4, iclass 32, count 0 2006.286.03:38:02.51#ibcon#about to read 5, iclass 32, count 0 2006.286.03:38:02.51#ibcon#read 5, iclass 32, count 0 2006.286.03:38:02.51#ibcon#about to read 6, iclass 32, count 0 2006.286.03:38:02.51#ibcon#read 6, iclass 32, count 0 2006.286.03:38:02.51#ibcon#end of sib2, iclass 32, count 0 2006.286.03:38:02.51#ibcon#*after write, iclass 32, count 0 2006.286.03:38:02.51#ibcon#*before return 0, iclass 32, count 0 2006.286.03:38:02.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:38:02.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:38:02.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.03:38:02.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.03:38:02.51$vck44/valo=7,864.99 2006.286.03:38:02.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.03:38:02.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.03:38:02.51#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:02.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:38:02.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:38:02.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:38:02.51#ibcon#enter wrdev, iclass 34, count 0 2006.286.03:38:02.51#ibcon#first serial, iclass 34, count 0 2006.286.03:38:02.51#ibcon#enter sib2, iclass 34, count 0 2006.286.03:38:02.51#ibcon#flushed, iclass 34, count 0 2006.286.03:38:02.51#ibcon#about to write, iclass 34, count 0 2006.286.03:38:02.51#ibcon#wrote, iclass 34, count 0 2006.286.03:38:02.51#ibcon#about to read 3, iclass 34, count 0 2006.286.03:38:02.53#ibcon#read 3, iclass 34, count 0 2006.286.03:38:02.53#ibcon#about to read 4, iclass 34, count 0 2006.286.03:38:02.53#ibcon#read 4, iclass 34, count 0 2006.286.03:38:02.53#ibcon#about to read 5, iclass 34, count 0 2006.286.03:38:02.53#ibcon#read 5, iclass 34, count 0 2006.286.03:38:02.53#ibcon#about to read 6, iclass 34, count 0 2006.286.03:38:02.53#ibcon#read 6, iclass 34, count 0 2006.286.03:38:02.53#ibcon#end of sib2, iclass 34, count 0 2006.286.03:38:02.53#ibcon#*mode == 0, iclass 34, count 0 2006.286.03:38:02.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.03:38:02.53#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.03:38:02.53#ibcon#*before write, iclass 34, count 0 2006.286.03:38:02.53#ibcon#enter sib2, iclass 34, count 0 2006.286.03:38:02.53#ibcon#flushed, iclass 34, count 0 2006.286.03:38:02.53#ibcon#about to write, iclass 34, count 0 2006.286.03:38:02.53#ibcon#wrote, iclass 34, count 0 2006.286.03:38:02.53#ibcon#about to read 3, iclass 34, count 0 2006.286.03:38:02.57#ibcon#read 3, iclass 34, count 0 2006.286.03:38:02.57#ibcon#about to read 4, iclass 34, count 0 2006.286.03:38:02.57#ibcon#read 4, iclass 34, count 0 2006.286.03:38:02.57#ibcon#about to read 5, iclass 34, count 0 2006.286.03:38:02.57#ibcon#read 5, iclass 34, count 0 2006.286.03:38:02.57#ibcon#about to read 6, iclass 34, count 0 2006.286.03:38:02.57#ibcon#read 6, iclass 34, count 0 2006.286.03:38:02.57#ibcon#end of sib2, iclass 34, count 0 2006.286.03:38:02.57#ibcon#*after write, iclass 34, count 0 2006.286.03:38:02.57#ibcon#*before return 0, iclass 34, count 0 2006.286.03:38:02.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:38:02.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:38:02.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.03:38:02.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.03:38:02.57$vck44/va=7,4 2006.286.03:38:02.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.03:38:02.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.03:38:02.57#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:02.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:38:02.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:38:02.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:38:02.63#ibcon#enter wrdev, iclass 36, count 2 2006.286.03:38:02.63#ibcon#first serial, iclass 36, count 2 2006.286.03:38:02.63#ibcon#enter sib2, iclass 36, count 2 2006.286.03:38:02.63#ibcon#flushed, iclass 36, count 2 2006.286.03:38:02.63#ibcon#about to write, iclass 36, count 2 2006.286.03:38:02.63#ibcon#wrote, iclass 36, count 2 2006.286.03:38:02.63#ibcon#about to read 3, iclass 36, count 2 2006.286.03:38:02.65#ibcon#read 3, iclass 36, count 2 2006.286.03:38:02.65#ibcon#about to read 4, iclass 36, count 2 2006.286.03:38:02.65#ibcon#read 4, iclass 36, count 2 2006.286.03:38:02.65#ibcon#about to read 5, iclass 36, count 2 2006.286.03:38:02.65#ibcon#read 5, iclass 36, count 2 2006.286.03:38:02.65#ibcon#about to read 6, iclass 36, count 2 2006.286.03:38:02.65#ibcon#read 6, iclass 36, count 2 2006.286.03:38:02.65#ibcon#end of sib2, iclass 36, count 2 2006.286.03:38:02.65#ibcon#*mode == 0, iclass 36, count 2 2006.286.03:38:02.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.03:38:02.65#ibcon#[25=AT07-04\r\n] 2006.286.03:38:02.65#ibcon#*before write, iclass 36, count 2 2006.286.03:38:02.65#ibcon#enter sib2, iclass 36, count 2 2006.286.03:38:02.65#ibcon#flushed, iclass 36, count 2 2006.286.03:38:02.65#ibcon#about to write, iclass 36, count 2 2006.286.03:38:02.65#ibcon#wrote, iclass 36, count 2 2006.286.03:38:02.65#ibcon#about to read 3, iclass 36, count 2 2006.286.03:38:02.68#ibcon#read 3, iclass 36, count 2 2006.286.03:38:02.68#ibcon#about to read 4, iclass 36, count 2 2006.286.03:38:02.68#ibcon#read 4, iclass 36, count 2 2006.286.03:38:02.68#ibcon#about to read 5, iclass 36, count 2 2006.286.03:38:02.68#ibcon#read 5, iclass 36, count 2 2006.286.03:38:02.68#ibcon#about to read 6, iclass 36, count 2 2006.286.03:38:02.68#ibcon#read 6, iclass 36, count 2 2006.286.03:38:02.68#ibcon#end of sib2, iclass 36, count 2 2006.286.03:38:02.68#ibcon#*after write, iclass 36, count 2 2006.286.03:38:02.68#ibcon#*before return 0, iclass 36, count 2 2006.286.03:38:02.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:38:02.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:38:02.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.03:38:02.68#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:02.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:38:02.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:38:02.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:38:02.80#ibcon#enter wrdev, iclass 36, count 0 2006.286.03:38:02.80#ibcon#first serial, iclass 36, count 0 2006.286.03:38:02.80#ibcon#enter sib2, iclass 36, count 0 2006.286.03:38:02.80#ibcon#flushed, iclass 36, count 0 2006.286.03:38:02.80#ibcon#about to write, iclass 36, count 0 2006.286.03:38:02.80#ibcon#wrote, iclass 36, count 0 2006.286.03:38:02.80#ibcon#about to read 3, iclass 36, count 0 2006.286.03:38:02.82#ibcon#read 3, iclass 36, count 0 2006.286.03:38:02.82#ibcon#about to read 4, iclass 36, count 0 2006.286.03:38:02.82#ibcon#read 4, iclass 36, count 0 2006.286.03:38:02.82#ibcon#about to read 5, iclass 36, count 0 2006.286.03:38:02.82#ibcon#read 5, iclass 36, count 0 2006.286.03:38:02.82#ibcon#about to read 6, iclass 36, count 0 2006.286.03:38:02.82#ibcon#read 6, iclass 36, count 0 2006.286.03:38:02.82#ibcon#end of sib2, iclass 36, count 0 2006.286.03:38:02.82#ibcon#*mode == 0, iclass 36, count 0 2006.286.03:38:02.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.03:38:02.82#ibcon#[25=USB\r\n] 2006.286.03:38:02.82#ibcon#*before write, iclass 36, count 0 2006.286.03:38:02.82#ibcon#enter sib2, iclass 36, count 0 2006.286.03:38:02.82#ibcon#flushed, iclass 36, count 0 2006.286.03:38:02.82#ibcon#about to write, iclass 36, count 0 2006.286.03:38:02.82#ibcon#wrote, iclass 36, count 0 2006.286.03:38:02.82#ibcon#about to read 3, iclass 36, count 0 2006.286.03:38:02.85#ibcon#read 3, iclass 36, count 0 2006.286.03:38:02.85#ibcon#about to read 4, iclass 36, count 0 2006.286.03:38:02.85#ibcon#read 4, iclass 36, count 0 2006.286.03:38:02.85#ibcon#about to read 5, iclass 36, count 0 2006.286.03:38:02.85#ibcon#read 5, iclass 36, count 0 2006.286.03:38:02.85#ibcon#about to read 6, iclass 36, count 0 2006.286.03:38:02.85#ibcon#read 6, iclass 36, count 0 2006.286.03:38:02.85#ibcon#end of sib2, iclass 36, count 0 2006.286.03:38:02.85#ibcon#*after write, iclass 36, count 0 2006.286.03:38:02.85#ibcon#*before return 0, iclass 36, count 0 2006.286.03:38:02.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:38:02.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:38:02.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.03:38:02.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.03:38:02.85$vck44/valo=8,884.99 2006.286.03:38:02.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.03:38:02.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.03:38:02.85#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:02.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:38:02.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:38:02.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:38:02.85#ibcon#enter wrdev, iclass 38, count 0 2006.286.03:38:02.85#ibcon#first serial, iclass 38, count 0 2006.286.03:38:02.85#ibcon#enter sib2, iclass 38, count 0 2006.286.03:38:02.85#ibcon#flushed, iclass 38, count 0 2006.286.03:38:02.85#ibcon#about to write, iclass 38, count 0 2006.286.03:38:02.85#ibcon#wrote, iclass 38, count 0 2006.286.03:38:02.85#ibcon#about to read 3, iclass 38, count 0 2006.286.03:38:02.87#ibcon#read 3, iclass 38, count 0 2006.286.03:38:02.87#ibcon#about to read 4, iclass 38, count 0 2006.286.03:38:02.87#ibcon#read 4, iclass 38, count 0 2006.286.03:38:02.87#ibcon#about to read 5, iclass 38, count 0 2006.286.03:38:02.87#ibcon#read 5, iclass 38, count 0 2006.286.03:38:02.87#ibcon#about to read 6, iclass 38, count 0 2006.286.03:38:02.87#ibcon#read 6, iclass 38, count 0 2006.286.03:38:02.87#ibcon#end of sib2, iclass 38, count 0 2006.286.03:38:02.87#ibcon#*mode == 0, iclass 38, count 0 2006.286.03:38:02.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.03:38:02.87#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.03:38:02.87#ibcon#*before write, iclass 38, count 0 2006.286.03:38:02.87#ibcon#enter sib2, iclass 38, count 0 2006.286.03:38:02.87#ibcon#flushed, iclass 38, count 0 2006.286.03:38:02.87#ibcon#about to write, iclass 38, count 0 2006.286.03:38:02.87#ibcon#wrote, iclass 38, count 0 2006.286.03:38:02.87#ibcon#about to read 3, iclass 38, count 0 2006.286.03:38:02.91#ibcon#read 3, iclass 38, count 0 2006.286.03:38:02.91#ibcon#about to read 4, iclass 38, count 0 2006.286.03:38:02.91#ibcon#read 4, iclass 38, count 0 2006.286.03:38:02.91#ibcon#about to read 5, iclass 38, count 0 2006.286.03:38:02.91#ibcon#read 5, iclass 38, count 0 2006.286.03:38:02.91#ibcon#about to read 6, iclass 38, count 0 2006.286.03:38:02.91#ibcon#read 6, iclass 38, count 0 2006.286.03:38:02.91#ibcon#end of sib2, iclass 38, count 0 2006.286.03:38:02.91#ibcon#*after write, iclass 38, count 0 2006.286.03:38:02.91#ibcon#*before return 0, iclass 38, count 0 2006.286.03:38:02.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:38:02.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:38:02.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.03:38:02.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.03:38:02.91$vck44/va=8,3 2006.286.03:38:02.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.03:38:02.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.03:38:02.91#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:02.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:38:02.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:38:02.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:38:02.97#ibcon#enter wrdev, iclass 40, count 2 2006.286.03:38:02.97#ibcon#first serial, iclass 40, count 2 2006.286.03:38:02.97#ibcon#enter sib2, iclass 40, count 2 2006.286.03:38:02.97#ibcon#flushed, iclass 40, count 2 2006.286.03:38:02.97#ibcon#about to write, iclass 40, count 2 2006.286.03:38:02.97#ibcon#wrote, iclass 40, count 2 2006.286.03:38:02.97#ibcon#about to read 3, iclass 40, count 2 2006.286.03:38:02.99#ibcon#read 3, iclass 40, count 2 2006.286.03:38:02.99#ibcon#about to read 4, iclass 40, count 2 2006.286.03:38:02.99#ibcon#read 4, iclass 40, count 2 2006.286.03:38:02.99#ibcon#about to read 5, iclass 40, count 2 2006.286.03:38:02.99#ibcon#read 5, iclass 40, count 2 2006.286.03:38:02.99#ibcon#about to read 6, iclass 40, count 2 2006.286.03:38:02.99#ibcon#read 6, iclass 40, count 2 2006.286.03:38:02.99#ibcon#end of sib2, iclass 40, count 2 2006.286.03:38:02.99#ibcon#*mode == 0, iclass 40, count 2 2006.286.03:38:02.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.03:38:02.99#ibcon#[25=AT08-03\r\n] 2006.286.03:38:02.99#ibcon#*before write, iclass 40, count 2 2006.286.03:38:02.99#ibcon#enter sib2, iclass 40, count 2 2006.286.03:38:02.99#ibcon#flushed, iclass 40, count 2 2006.286.03:38:02.99#ibcon#about to write, iclass 40, count 2 2006.286.03:38:02.99#ibcon#wrote, iclass 40, count 2 2006.286.03:38:02.99#ibcon#about to read 3, iclass 40, count 2 2006.286.03:38:03.02#ibcon#read 3, iclass 40, count 2 2006.286.03:38:03.02#ibcon#about to read 4, iclass 40, count 2 2006.286.03:38:03.02#ibcon#read 4, iclass 40, count 2 2006.286.03:38:03.02#ibcon#about to read 5, iclass 40, count 2 2006.286.03:38:03.02#ibcon#read 5, iclass 40, count 2 2006.286.03:38:03.02#ibcon#about to read 6, iclass 40, count 2 2006.286.03:38:03.02#ibcon#read 6, iclass 40, count 2 2006.286.03:38:03.02#ibcon#end of sib2, iclass 40, count 2 2006.286.03:38:03.02#ibcon#*after write, iclass 40, count 2 2006.286.03:38:03.02#ibcon#*before return 0, iclass 40, count 2 2006.286.03:38:03.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:38:03.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:38:03.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.03:38:03.02#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:03.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:38:03.14#abcon#<5=/04 3.3 6.8 21.67 771015.0\r\n> 2006.286.03:38:03.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:38:03.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:38:03.14#ibcon#enter wrdev, iclass 40, count 0 2006.286.03:38:03.14#ibcon#first serial, iclass 40, count 0 2006.286.03:38:03.14#ibcon#enter sib2, iclass 40, count 0 2006.286.03:38:03.14#ibcon#flushed, iclass 40, count 0 2006.286.03:38:03.14#ibcon#about to write, iclass 40, count 0 2006.286.03:38:03.14#ibcon#wrote, iclass 40, count 0 2006.286.03:38:03.14#ibcon#about to read 3, iclass 40, count 0 2006.286.03:38:03.16#abcon#{5=INTERFACE CLEAR} 2006.286.03:38:03.16#ibcon#read 3, iclass 40, count 0 2006.286.03:38:03.16#ibcon#about to read 4, iclass 40, count 0 2006.286.03:38:03.16#ibcon#read 4, iclass 40, count 0 2006.286.03:38:03.16#ibcon#about to read 5, iclass 40, count 0 2006.286.03:38:03.16#ibcon#read 5, iclass 40, count 0 2006.286.03:38:03.16#ibcon#about to read 6, iclass 40, count 0 2006.286.03:38:03.16#ibcon#read 6, iclass 40, count 0 2006.286.03:38:03.16#ibcon#end of sib2, iclass 40, count 0 2006.286.03:38:03.16#ibcon#*mode == 0, iclass 40, count 0 2006.286.03:38:03.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.03:38:03.16#ibcon#[25=USB\r\n] 2006.286.03:38:03.16#ibcon#*before write, iclass 40, count 0 2006.286.03:38:03.16#ibcon#enter sib2, iclass 40, count 0 2006.286.03:38:03.16#ibcon#flushed, iclass 40, count 0 2006.286.03:38:03.16#ibcon#about to write, iclass 40, count 0 2006.286.03:38:03.16#ibcon#wrote, iclass 40, count 0 2006.286.03:38:03.16#ibcon#about to read 3, iclass 40, count 0 2006.286.03:38:03.19#ibcon#read 3, iclass 40, count 0 2006.286.03:38:03.19#ibcon#about to read 4, iclass 40, count 0 2006.286.03:38:03.19#ibcon#read 4, iclass 40, count 0 2006.286.03:38:03.19#ibcon#about to read 5, iclass 40, count 0 2006.286.03:38:03.19#ibcon#read 5, iclass 40, count 0 2006.286.03:38:03.19#ibcon#about to read 6, iclass 40, count 0 2006.286.03:38:03.19#ibcon#read 6, iclass 40, count 0 2006.286.03:38:03.19#ibcon#end of sib2, iclass 40, count 0 2006.286.03:38:03.19#ibcon#*after write, iclass 40, count 0 2006.286.03:38:03.19#ibcon#*before return 0, iclass 40, count 0 2006.286.03:38:03.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:38:03.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:38:03.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.03:38:03.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.03:38:03.19$vck44/vblo=1,629.99 2006.286.03:38:03.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.03:38:03.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.03:38:03.19#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:03.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:38:03.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:38:03.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:38:03.19#ibcon#enter wrdev, iclass 7, count 0 2006.286.03:38:03.19#ibcon#first serial, iclass 7, count 0 2006.286.03:38:03.19#ibcon#enter sib2, iclass 7, count 0 2006.286.03:38:03.19#ibcon#flushed, iclass 7, count 0 2006.286.03:38:03.19#ibcon#about to write, iclass 7, count 0 2006.286.03:38:03.19#ibcon#wrote, iclass 7, count 0 2006.286.03:38:03.19#ibcon#about to read 3, iclass 7, count 0 2006.286.03:38:03.21#ibcon#read 3, iclass 7, count 0 2006.286.03:38:03.21#ibcon#about to read 4, iclass 7, count 0 2006.286.03:38:03.21#ibcon#read 4, iclass 7, count 0 2006.286.03:38:03.21#ibcon#about to read 5, iclass 7, count 0 2006.286.03:38:03.21#ibcon#read 5, iclass 7, count 0 2006.286.03:38:03.21#ibcon#about to read 6, iclass 7, count 0 2006.286.03:38:03.21#ibcon#read 6, iclass 7, count 0 2006.286.03:38:03.21#ibcon#end of sib2, iclass 7, count 0 2006.286.03:38:03.21#ibcon#*mode == 0, iclass 7, count 0 2006.286.03:38:03.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.03:38:03.21#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.03:38:03.21#ibcon#*before write, iclass 7, count 0 2006.286.03:38:03.21#ibcon#enter sib2, iclass 7, count 0 2006.286.03:38:03.21#ibcon#flushed, iclass 7, count 0 2006.286.03:38:03.21#ibcon#about to write, iclass 7, count 0 2006.286.03:38:03.21#ibcon#wrote, iclass 7, count 0 2006.286.03:38:03.21#ibcon#about to read 3, iclass 7, count 0 2006.286.03:38:03.22#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:38:03.25#ibcon#read 3, iclass 7, count 0 2006.286.03:38:03.25#ibcon#about to read 4, iclass 7, count 0 2006.286.03:38:03.25#ibcon#read 4, iclass 7, count 0 2006.286.03:38:03.25#ibcon#about to read 5, iclass 7, count 0 2006.286.03:38:03.25#ibcon#read 5, iclass 7, count 0 2006.286.03:38:03.25#ibcon#about to read 6, iclass 7, count 0 2006.286.03:38:03.25#ibcon#read 6, iclass 7, count 0 2006.286.03:38:03.25#ibcon#end of sib2, iclass 7, count 0 2006.286.03:38:03.25#ibcon#*after write, iclass 7, count 0 2006.286.03:38:03.25#ibcon#*before return 0, iclass 7, count 0 2006.286.03:38:03.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:38:03.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:38:03.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.03:38:03.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.03:38:03.25$vck44/vb=1,4 2006.286.03:38:03.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.03:38:03.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.03:38:03.25#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:03.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:38:03.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:38:03.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:38:03.25#ibcon#enter wrdev, iclass 12, count 2 2006.286.03:38:03.25#ibcon#first serial, iclass 12, count 2 2006.286.03:38:03.25#ibcon#enter sib2, iclass 12, count 2 2006.286.03:38:03.25#ibcon#flushed, iclass 12, count 2 2006.286.03:38:03.25#ibcon#about to write, iclass 12, count 2 2006.286.03:38:03.25#ibcon#wrote, iclass 12, count 2 2006.286.03:38:03.25#ibcon#about to read 3, iclass 12, count 2 2006.286.03:38:03.27#ibcon#read 3, iclass 12, count 2 2006.286.03:38:03.27#ibcon#about to read 4, iclass 12, count 2 2006.286.03:38:03.27#ibcon#read 4, iclass 12, count 2 2006.286.03:38:03.27#ibcon#about to read 5, iclass 12, count 2 2006.286.03:38:03.27#ibcon#read 5, iclass 12, count 2 2006.286.03:38:03.27#ibcon#about to read 6, iclass 12, count 2 2006.286.03:38:03.27#ibcon#read 6, iclass 12, count 2 2006.286.03:38:03.27#ibcon#end of sib2, iclass 12, count 2 2006.286.03:38:03.27#ibcon#*mode == 0, iclass 12, count 2 2006.286.03:38:03.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.03:38:03.27#ibcon#[27=AT01-04\r\n] 2006.286.03:38:03.27#ibcon#*before write, iclass 12, count 2 2006.286.03:38:03.27#ibcon#enter sib2, iclass 12, count 2 2006.286.03:38:03.27#ibcon#flushed, iclass 12, count 2 2006.286.03:38:03.27#ibcon#about to write, iclass 12, count 2 2006.286.03:38:03.27#ibcon#wrote, iclass 12, count 2 2006.286.03:38:03.27#ibcon#about to read 3, iclass 12, count 2 2006.286.03:38:03.30#ibcon#read 3, iclass 12, count 2 2006.286.03:38:03.30#ibcon#about to read 4, iclass 12, count 2 2006.286.03:38:03.30#ibcon#read 4, iclass 12, count 2 2006.286.03:38:03.30#ibcon#about to read 5, iclass 12, count 2 2006.286.03:38:03.30#ibcon#read 5, iclass 12, count 2 2006.286.03:38:03.30#ibcon#about to read 6, iclass 12, count 2 2006.286.03:38:03.30#ibcon#read 6, iclass 12, count 2 2006.286.03:38:03.30#ibcon#end of sib2, iclass 12, count 2 2006.286.03:38:03.30#ibcon#*after write, iclass 12, count 2 2006.286.03:38:03.30#ibcon#*before return 0, iclass 12, count 2 2006.286.03:38:03.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:38:03.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.03:38:03.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.03:38:03.30#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:03.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:38:03.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:38:03.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:38:03.42#ibcon#enter wrdev, iclass 12, count 0 2006.286.03:38:03.42#ibcon#first serial, iclass 12, count 0 2006.286.03:38:03.42#ibcon#enter sib2, iclass 12, count 0 2006.286.03:38:03.42#ibcon#flushed, iclass 12, count 0 2006.286.03:38:03.42#ibcon#about to write, iclass 12, count 0 2006.286.03:38:03.42#ibcon#wrote, iclass 12, count 0 2006.286.03:38:03.42#ibcon#about to read 3, iclass 12, count 0 2006.286.03:38:03.44#ibcon#read 3, iclass 12, count 0 2006.286.03:38:03.44#ibcon#about to read 4, iclass 12, count 0 2006.286.03:38:03.44#ibcon#read 4, iclass 12, count 0 2006.286.03:38:03.44#ibcon#about to read 5, iclass 12, count 0 2006.286.03:38:03.44#ibcon#read 5, iclass 12, count 0 2006.286.03:38:03.44#ibcon#about to read 6, iclass 12, count 0 2006.286.03:38:03.44#ibcon#read 6, iclass 12, count 0 2006.286.03:38:03.44#ibcon#end of sib2, iclass 12, count 0 2006.286.03:38:03.44#ibcon#*mode == 0, iclass 12, count 0 2006.286.03:38:03.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.03:38:03.44#ibcon#[27=USB\r\n] 2006.286.03:38:03.44#ibcon#*before write, iclass 12, count 0 2006.286.03:38:03.44#ibcon#enter sib2, iclass 12, count 0 2006.286.03:38:03.44#ibcon#flushed, iclass 12, count 0 2006.286.03:38:03.44#ibcon#about to write, iclass 12, count 0 2006.286.03:38:03.44#ibcon#wrote, iclass 12, count 0 2006.286.03:38:03.44#ibcon#about to read 3, iclass 12, count 0 2006.286.03:38:03.47#ibcon#read 3, iclass 12, count 0 2006.286.03:38:03.47#ibcon#about to read 4, iclass 12, count 0 2006.286.03:38:03.47#ibcon#read 4, iclass 12, count 0 2006.286.03:38:03.47#ibcon#about to read 5, iclass 12, count 0 2006.286.03:38:03.47#ibcon#read 5, iclass 12, count 0 2006.286.03:38:03.47#ibcon#about to read 6, iclass 12, count 0 2006.286.03:38:03.47#ibcon#read 6, iclass 12, count 0 2006.286.03:38:03.47#ibcon#end of sib2, iclass 12, count 0 2006.286.03:38:03.47#ibcon#*after write, iclass 12, count 0 2006.286.03:38:03.47#ibcon#*before return 0, iclass 12, count 0 2006.286.03:38:03.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:38:03.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.03:38:03.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.03:38:03.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.03:38:03.47$vck44/vblo=2,634.99 2006.286.03:38:03.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.03:38:03.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.03:38:03.47#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:03.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:38:03.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:38:03.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:38:03.47#ibcon#enter wrdev, iclass 14, count 0 2006.286.03:38:03.47#ibcon#first serial, iclass 14, count 0 2006.286.03:38:03.47#ibcon#enter sib2, iclass 14, count 0 2006.286.03:38:03.47#ibcon#flushed, iclass 14, count 0 2006.286.03:38:03.47#ibcon#about to write, iclass 14, count 0 2006.286.03:38:03.47#ibcon#wrote, iclass 14, count 0 2006.286.03:38:03.47#ibcon#about to read 3, iclass 14, count 0 2006.286.03:38:03.49#ibcon#read 3, iclass 14, count 0 2006.286.03:38:03.49#ibcon#about to read 4, iclass 14, count 0 2006.286.03:38:03.49#ibcon#read 4, iclass 14, count 0 2006.286.03:38:03.49#ibcon#about to read 5, iclass 14, count 0 2006.286.03:38:03.49#ibcon#read 5, iclass 14, count 0 2006.286.03:38:03.49#ibcon#about to read 6, iclass 14, count 0 2006.286.03:38:03.49#ibcon#read 6, iclass 14, count 0 2006.286.03:38:03.49#ibcon#end of sib2, iclass 14, count 0 2006.286.03:38:03.49#ibcon#*mode == 0, iclass 14, count 0 2006.286.03:38:03.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.03:38:03.49#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.03:38:03.49#ibcon#*before write, iclass 14, count 0 2006.286.03:38:03.49#ibcon#enter sib2, iclass 14, count 0 2006.286.03:38:03.49#ibcon#flushed, iclass 14, count 0 2006.286.03:38:03.49#ibcon#about to write, iclass 14, count 0 2006.286.03:38:03.49#ibcon#wrote, iclass 14, count 0 2006.286.03:38:03.49#ibcon#about to read 3, iclass 14, count 0 2006.286.03:38:03.53#ibcon#read 3, iclass 14, count 0 2006.286.03:38:03.53#ibcon#about to read 4, iclass 14, count 0 2006.286.03:38:03.53#ibcon#read 4, iclass 14, count 0 2006.286.03:38:03.53#ibcon#about to read 5, iclass 14, count 0 2006.286.03:38:03.53#ibcon#read 5, iclass 14, count 0 2006.286.03:38:03.53#ibcon#about to read 6, iclass 14, count 0 2006.286.03:38:03.53#ibcon#read 6, iclass 14, count 0 2006.286.03:38:03.53#ibcon#end of sib2, iclass 14, count 0 2006.286.03:38:03.53#ibcon#*after write, iclass 14, count 0 2006.286.03:38:03.53#ibcon#*before return 0, iclass 14, count 0 2006.286.03:38:03.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:38:03.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.03:38:03.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.03:38:03.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.03:38:03.53$vck44/vb=2,5 2006.286.03:38:03.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.03:38:03.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.03:38:03.53#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:03.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:38:03.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:38:03.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:38:03.59#ibcon#enter wrdev, iclass 16, count 2 2006.286.03:38:03.59#ibcon#first serial, iclass 16, count 2 2006.286.03:38:03.59#ibcon#enter sib2, iclass 16, count 2 2006.286.03:38:03.59#ibcon#flushed, iclass 16, count 2 2006.286.03:38:03.59#ibcon#about to write, iclass 16, count 2 2006.286.03:38:03.59#ibcon#wrote, iclass 16, count 2 2006.286.03:38:03.59#ibcon#about to read 3, iclass 16, count 2 2006.286.03:38:03.61#ibcon#read 3, iclass 16, count 2 2006.286.03:38:03.61#ibcon#about to read 4, iclass 16, count 2 2006.286.03:38:03.61#ibcon#read 4, iclass 16, count 2 2006.286.03:38:03.61#ibcon#about to read 5, iclass 16, count 2 2006.286.03:38:03.61#ibcon#read 5, iclass 16, count 2 2006.286.03:38:03.61#ibcon#about to read 6, iclass 16, count 2 2006.286.03:38:03.61#ibcon#read 6, iclass 16, count 2 2006.286.03:38:03.61#ibcon#end of sib2, iclass 16, count 2 2006.286.03:38:03.61#ibcon#*mode == 0, iclass 16, count 2 2006.286.03:38:03.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.03:38:03.61#ibcon#[27=AT02-05\r\n] 2006.286.03:38:03.61#ibcon#*before write, iclass 16, count 2 2006.286.03:38:03.61#ibcon#enter sib2, iclass 16, count 2 2006.286.03:38:03.61#ibcon#flushed, iclass 16, count 2 2006.286.03:38:03.61#ibcon#about to write, iclass 16, count 2 2006.286.03:38:03.61#ibcon#wrote, iclass 16, count 2 2006.286.03:38:03.61#ibcon#about to read 3, iclass 16, count 2 2006.286.03:38:03.64#ibcon#read 3, iclass 16, count 2 2006.286.03:38:03.64#ibcon#about to read 4, iclass 16, count 2 2006.286.03:38:03.64#ibcon#read 4, iclass 16, count 2 2006.286.03:38:03.64#ibcon#about to read 5, iclass 16, count 2 2006.286.03:38:03.64#ibcon#read 5, iclass 16, count 2 2006.286.03:38:03.64#ibcon#about to read 6, iclass 16, count 2 2006.286.03:38:03.64#ibcon#read 6, iclass 16, count 2 2006.286.03:38:03.64#ibcon#end of sib2, iclass 16, count 2 2006.286.03:38:03.64#ibcon#*after write, iclass 16, count 2 2006.286.03:38:03.64#ibcon#*before return 0, iclass 16, count 2 2006.286.03:38:03.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:38:03.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.03:38:03.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.03:38:03.64#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:03.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:38:03.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:38:03.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:38:03.76#ibcon#enter wrdev, iclass 16, count 0 2006.286.03:38:03.76#ibcon#first serial, iclass 16, count 0 2006.286.03:38:03.76#ibcon#enter sib2, iclass 16, count 0 2006.286.03:38:03.76#ibcon#flushed, iclass 16, count 0 2006.286.03:38:03.76#ibcon#about to write, iclass 16, count 0 2006.286.03:38:03.76#ibcon#wrote, iclass 16, count 0 2006.286.03:38:03.76#ibcon#about to read 3, iclass 16, count 0 2006.286.03:38:03.78#ibcon#read 3, iclass 16, count 0 2006.286.03:38:03.78#ibcon#about to read 4, iclass 16, count 0 2006.286.03:38:03.78#ibcon#read 4, iclass 16, count 0 2006.286.03:38:03.78#ibcon#about to read 5, iclass 16, count 0 2006.286.03:38:03.78#ibcon#read 5, iclass 16, count 0 2006.286.03:38:03.78#ibcon#about to read 6, iclass 16, count 0 2006.286.03:38:03.78#ibcon#read 6, iclass 16, count 0 2006.286.03:38:03.78#ibcon#end of sib2, iclass 16, count 0 2006.286.03:38:03.78#ibcon#*mode == 0, iclass 16, count 0 2006.286.03:38:03.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.03:38:03.78#ibcon#[27=USB\r\n] 2006.286.03:38:03.78#ibcon#*before write, iclass 16, count 0 2006.286.03:38:03.78#ibcon#enter sib2, iclass 16, count 0 2006.286.03:38:03.78#ibcon#flushed, iclass 16, count 0 2006.286.03:38:03.78#ibcon#about to write, iclass 16, count 0 2006.286.03:38:03.78#ibcon#wrote, iclass 16, count 0 2006.286.03:38:03.78#ibcon#about to read 3, iclass 16, count 0 2006.286.03:38:03.81#ibcon#read 3, iclass 16, count 0 2006.286.03:38:03.81#ibcon#about to read 4, iclass 16, count 0 2006.286.03:38:03.81#ibcon#read 4, iclass 16, count 0 2006.286.03:38:03.81#ibcon#about to read 5, iclass 16, count 0 2006.286.03:38:03.81#ibcon#read 5, iclass 16, count 0 2006.286.03:38:03.81#ibcon#about to read 6, iclass 16, count 0 2006.286.03:38:03.81#ibcon#read 6, iclass 16, count 0 2006.286.03:38:03.81#ibcon#end of sib2, iclass 16, count 0 2006.286.03:38:03.81#ibcon#*after write, iclass 16, count 0 2006.286.03:38:03.81#ibcon#*before return 0, iclass 16, count 0 2006.286.03:38:03.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:38:03.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.03:38:03.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.03:38:03.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.03:38:03.81$vck44/vblo=3,649.99 2006.286.03:38:03.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.03:38:03.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.03:38:03.81#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:03.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:38:03.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:38:03.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:38:03.81#ibcon#enter wrdev, iclass 18, count 0 2006.286.03:38:03.81#ibcon#first serial, iclass 18, count 0 2006.286.03:38:03.81#ibcon#enter sib2, iclass 18, count 0 2006.286.03:38:03.81#ibcon#flushed, iclass 18, count 0 2006.286.03:38:03.81#ibcon#about to write, iclass 18, count 0 2006.286.03:38:03.81#ibcon#wrote, iclass 18, count 0 2006.286.03:38:03.81#ibcon#about to read 3, iclass 18, count 0 2006.286.03:38:03.83#ibcon#read 3, iclass 18, count 0 2006.286.03:38:04.04#ibcon#about to read 4, iclass 18, count 0 2006.286.03:38:04.04#ibcon#read 4, iclass 18, count 0 2006.286.03:38:04.04#ibcon#about to read 5, iclass 18, count 0 2006.286.03:38:04.04#ibcon#read 5, iclass 18, count 0 2006.286.03:38:04.04#ibcon#about to read 6, iclass 18, count 0 2006.286.03:38:04.04#ibcon#read 6, iclass 18, count 0 2006.286.03:38:04.04#ibcon#end of sib2, iclass 18, count 0 2006.286.03:38:04.04#ibcon#*mode == 0, iclass 18, count 0 2006.286.03:38:04.04#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.03:38:04.04#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.03:38:04.04#ibcon#*before write, iclass 18, count 0 2006.286.03:38:04.04#ibcon#enter sib2, iclass 18, count 0 2006.286.03:38:04.04#ibcon#flushed, iclass 18, count 0 2006.286.03:38:04.04#ibcon#about to write, iclass 18, count 0 2006.286.03:38:04.04#ibcon#wrote, iclass 18, count 0 2006.286.03:38:04.04#ibcon#about to read 3, iclass 18, count 0 2006.286.03:38:04.08#ibcon#read 3, iclass 18, count 0 2006.286.03:38:04.08#ibcon#about to read 4, iclass 18, count 0 2006.286.03:38:04.08#ibcon#read 4, iclass 18, count 0 2006.286.03:38:04.08#ibcon#about to read 5, iclass 18, count 0 2006.286.03:38:04.08#ibcon#read 5, iclass 18, count 0 2006.286.03:38:04.08#ibcon#about to read 6, iclass 18, count 0 2006.286.03:38:04.08#ibcon#read 6, iclass 18, count 0 2006.286.03:38:04.08#ibcon#end of sib2, iclass 18, count 0 2006.286.03:38:04.08#ibcon#*after write, iclass 18, count 0 2006.286.03:38:04.08#ibcon#*before return 0, iclass 18, count 0 2006.286.03:38:04.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:38:04.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.03:38:04.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.03:38:04.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.03:38:04.08$vck44/vb=3,4 2006.286.03:38:04.08#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.03:38:04.08#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.03:38:04.08#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:04.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:38:04.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:38:04.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:38:04.08#ibcon#enter wrdev, iclass 20, count 2 2006.286.03:38:04.08#ibcon#first serial, iclass 20, count 2 2006.286.03:38:04.08#ibcon#enter sib2, iclass 20, count 2 2006.286.03:38:04.08#ibcon#flushed, iclass 20, count 2 2006.286.03:38:04.08#ibcon#about to write, iclass 20, count 2 2006.286.03:38:04.08#ibcon#wrote, iclass 20, count 2 2006.286.03:38:04.08#ibcon#about to read 3, iclass 20, count 2 2006.286.03:38:04.10#ibcon#read 3, iclass 20, count 2 2006.286.03:38:04.10#ibcon#about to read 4, iclass 20, count 2 2006.286.03:38:04.10#ibcon#read 4, iclass 20, count 2 2006.286.03:38:04.10#ibcon#about to read 5, iclass 20, count 2 2006.286.03:38:04.10#ibcon#read 5, iclass 20, count 2 2006.286.03:38:04.10#ibcon#about to read 6, iclass 20, count 2 2006.286.03:38:04.10#ibcon#read 6, iclass 20, count 2 2006.286.03:38:04.10#ibcon#end of sib2, iclass 20, count 2 2006.286.03:38:04.10#ibcon#*mode == 0, iclass 20, count 2 2006.286.03:38:04.10#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.03:38:04.10#ibcon#[27=AT03-04\r\n] 2006.286.03:38:04.10#ibcon#*before write, iclass 20, count 2 2006.286.03:38:04.10#ibcon#enter sib2, iclass 20, count 2 2006.286.03:38:04.10#ibcon#flushed, iclass 20, count 2 2006.286.03:38:04.10#ibcon#about to write, iclass 20, count 2 2006.286.03:38:04.10#ibcon#wrote, iclass 20, count 2 2006.286.03:38:04.10#ibcon#about to read 3, iclass 20, count 2 2006.286.03:38:04.13#ibcon#read 3, iclass 20, count 2 2006.286.03:38:04.13#ibcon#about to read 4, iclass 20, count 2 2006.286.03:38:04.13#ibcon#read 4, iclass 20, count 2 2006.286.03:38:04.13#ibcon#about to read 5, iclass 20, count 2 2006.286.03:38:04.13#ibcon#read 5, iclass 20, count 2 2006.286.03:38:04.13#ibcon#about to read 6, iclass 20, count 2 2006.286.03:38:04.13#ibcon#read 6, iclass 20, count 2 2006.286.03:38:04.13#ibcon#end of sib2, iclass 20, count 2 2006.286.03:38:04.13#ibcon#*after write, iclass 20, count 2 2006.286.03:38:04.13#ibcon#*before return 0, iclass 20, count 2 2006.286.03:38:04.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:38:04.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.03:38:04.13#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.03:38:04.13#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:04.13#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:38:04.25#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:38:04.25#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:38:04.25#ibcon#enter wrdev, iclass 20, count 0 2006.286.03:38:04.25#ibcon#first serial, iclass 20, count 0 2006.286.03:38:04.25#ibcon#enter sib2, iclass 20, count 0 2006.286.03:38:04.25#ibcon#flushed, iclass 20, count 0 2006.286.03:38:04.25#ibcon#about to write, iclass 20, count 0 2006.286.03:38:04.25#ibcon#wrote, iclass 20, count 0 2006.286.03:38:04.25#ibcon#about to read 3, iclass 20, count 0 2006.286.03:38:04.27#ibcon#read 3, iclass 20, count 0 2006.286.03:38:04.27#ibcon#about to read 4, iclass 20, count 0 2006.286.03:38:04.27#ibcon#read 4, iclass 20, count 0 2006.286.03:38:04.27#ibcon#about to read 5, iclass 20, count 0 2006.286.03:38:04.27#ibcon#read 5, iclass 20, count 0 2006.286.03:38:04.27#ibcon#about to read 6, iclass 20, count 0 2006.286.03:38:04.27#ibcon#read 6, iclass 20, count 0 2006.286.03:38:04.27#ibcon#end of sib2, iclass 20, count 0 2006.286.03:38:04.27#ibcon#*mode == 0, iclass 20, count 0 2006.286.03:38:04.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.03:38:04.27#ibcon#[27=USB\r\n] 2006.286.03:38:04.27#ibcon#*before write, iclass 20, count 0 2006.286.03:38:04.27#ibcon#enter sib2, iclass 20, count 0 2006.286.03:38:04.27#ibcon#flushed, iclass 20, count 0 2006.286.03:38:04.27#ibcon#about to write, iclass 20, count 0 2006.286.03:38:04.27#ibcon#wrote, iclass 20, count 0 2006.286.03:38:04.27#ibcon#about to read 3, iclass 20, count 0 2006.286.03:38:04.30#ibcon#read 3, iclass 20, count 0 2006.286.03:38:04.30#ibcon#about to read 4, iclass 20, count 0 2006.286.03:38:04.30#ibcon#read 4, iclass 20, count 0 2006.286.03:38:04.30#ibcon#about to read 5, iclass 20, count 0 2006.286.03:38:04.30#ibcon#read 5, iclass 20, count 0 2006.286.03:38:04.30#ibcon#about to read 6, iclass 20, count 0 2006.286.03:38:04.30#ibcon#read 6, iclass 20, count 0 2006.286.03:38:04.30#ibcon#end of sib2, iclass 20, count 0 2006.286.03:38:04.30#ibcon#*after write, iclass 20, count 0 2006.286.03:38:04.30#ibcon#*before return 0, iclass 20, count 0 2006.286.03:38:04.30#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:38:04.30#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.03:38:04.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.03:38:04.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.03:38:04.30$vck44/vblo=4,679.99 2006.286.03:38:04.30#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.03:38:04.30#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.03:38:04.30#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:04.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:38:04.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:38:04.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:38:04.30#ibcon#enter wrdev, iclass 22, count 0 2006.286.03:38:04.30#ibcon#first serial, iclass 22, count 0 2006.286.03:38:04.30#ibcon#enter sib2, iclass 22, count 0 2006.286.03:38:04.30#ibcon#flushed, iclass 22, count 0 2006.286.03:38:04.30#ibcon#about to write, iclass 22, count 0 2006.286.03:38:04.30#ibcon#wrote, iclass 22, count 0 2006.286.03:38:04.30#ibcon#about to read 3, iclass 22, count 0 2006.286.03:38:04.32#ibcon#read 3, iclass 22, count 0 2006.286.03:38:04.32#ibcon#about to read 4, iclass 22, count 0 2006.286.03:38:04.32#ibcon#read 4, iclass 22, count 0 2006.286.03:38:04.32#ibcon#about to read 5, iclass 22, count 0 2006.286.03:38:04.32#ibcon#read 5, iclass 22, count 0 2006.286.03:38:04.32#ibcon#about to read 6, iclass 22, count 0 2006.286.03:38:04.32#ibcon#read 6, iclass 22, count 0 2006.286.03:38:04.32#ibcon#end of sib2, iclass 22, count 0 2006.286.03:38:04.32#ibcon#*mode == 0, iclass 22, count 0 2006.286.03:38:04.32#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.03:38:04.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.03:38:04.32#ibcon#*before write, iclass 22, count 0 2006.286.03:38:04.32#ibcon#enter sib2, iclass 22, count 0 2006.286.03:38:04.32#ibcon#flushed, iclass 22, count 0 2006.286.03:38:04.32#ibcon#about to write, iclass 22, count 0 2006.286.03:38:04.32#ibcon#wrote, iclass 22, count 0 2006.286.03:38:04.32#ibcon#about to read 3, iclass 22, count 0 2006.286.03:38:04.36#ibcon#read 3, iclass 22, count 0 2006.286.03:38:04.36#ibcon#about to read 4, iclass 22, count 0 2006.286.03:38:04.36#ibcon#read 4, iclass 22, count 0 2006.286.03:38:04.36#ibcon#about to read 5, iclass 22, count 0 2006.286.03:38:04.36#ibcon#read 5, iclass 22, count 0 2006.286.03:38:04.36#ibcon#about to read 6, iclass 22, count 0 2006.286.03:38:04.36#ibcon#read 6, iclass 22, count 0 2006.286.03:38:04.36#ibcon#end of sib2, iclass 22, count 0 2006.286.03:38:04.36#ibcon#*after write, iclass 22, count 0 2006.286.03:38:04.36#ibcon#*before return 0, iclass 22, count 0 2006.286.03:38:04.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:38:04.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.03:38:04.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.03:38:04.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.03:38:04.36$vck44/vb=4,5 2006.286.03:38:04.36#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.03:38:04.36#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.03:38:04.36#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:04.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:38:04.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:38:04.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:38:04.42#ibcon#enter wrdev, iclass 24, count 2 2006.286.03:38:04.42#ibcon#first serial, iclass 24, count 2 2006.286.03:38:04.42#ibcon#enter sib2, iclass 24, count 2 2006.286.03:38:04.42#ibcon#flushed, iclass 24, count 2 2006.286.03:38:04.42#ibcon#about to write, iclass 24, count 2 2006.286.03:38:04.42#ibcon#wrote, iclass 24, count 2 2006.286.03:38:04.42#ibcon#about to read 3, iclass 24, count 2 2006.286.03:38:04.44#ibcon#read 3, iclass 24, count 2 2006.286.03:38:04.44#ibcon#about to read 4, iclass 24, count 2 2006.286.03:38:04.44#ibcon#read 4, iclass 24, count 2 2006.286.03:38:04.44#ibcon#about to read 5, iclass 24, count 2 2006.286.03:38:04.44#ibcon#read 5, iclass 24, count 2 2006.286.03:38:04.44#ibcon#about to read 6, iclass 24, count 2 2006.286.03:38:04.44#ibcon#read 6, iclass 24, count 2 2006.286.03:38:04.44#ibcon#end of sib2, iclass 24, count 2 2006.286.03:38:04.44#ibcon#*mode == 0, iclass 24, count 2 2006.286.03:38:04.44#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.03:38:04.44#ibcon#[27=AT04-05\r\n] 2006.286.03:38:04.44#ibcon#*before write, iclass 24, count 2 2006.286.03:38:04.44#ibcon#enter sib2, iclass 24, count 2 2006.286.03:38:04.44#ibcon#flushed, iclass 24, count 2 2006.286.03:38:04.44#ibcon#about to write, iclass 24, count 2 2006.286.03:38:04.44#ibcon#wrote, iclass 24, count 2 2006.286.03:38:04.44#ibcon#about to read 3, iclass 24, count 2 2006.286.03:38:04.47#ibcon#read 3, iclass 24, count 2 2006.286.03:38:04.47#ibcon#about to read 4, iclass 24, count 2 2006.286.03:38:04.47#ibcon#read 4, iclass 24, count 2 2006.286.03:38:04.47#ibcon#about to read 5, iclass 24, count 2 2006.286.03:38:04.47#ibcon#read 5, iclass 24, count 2 2006.286.03:38:04.47#ibcon#about to read 6, iclass 24, count 2 2006.286.03:38:04.47#ibcon#read 6, iclass 24, count 2 2006.286.03:38:04.47#ibcon#end of sib2, iclass 24, count 2 2006.286.03:38:04.47#ibcon#*after write, iclass 24, count 2 2006.286.03:38:04.47#ibcon#*before return 0, iclass 24, count 2 2006.286.03:38:04.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:38:04.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.03:38:04.47#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.03:38:04.47#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:04.47#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:38:04.59#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:38:04.59#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:38:04.59#ibcon#enter wrdev, iclass 24, count 0 2006.286.03:38:04.59#ibcon#first serial, iclass 24, count 0 2006.286.03:38:04.59#ibcon#enter sib2, iclass 24, count 0 2006.286.03:38:04.59#ibcon#flushed, iclass 24, count 0 2006.286.03:38:04.59#ibcon#about to write, iclass 24, count 0 2006.286.03:38:04.59#ibcon#wrote, iclass 24, count 0 2006.286.03:38:04.59#ibcon#about to read 3, iclass 24, count 0 2006.286.03:38:04.61#ibcon#read 3, iclass 24, count 0 2006.286.03:38:04.61#ibcon#about to read 4, iclass 24, count 0 2006.286.03:38:04.61#ibcon#read 4, iclass 24, count 0 2006.286.03:38:04.61#ibcon#about to read 5, iclass 24, count 0 2006.286.03:38:04.61#ibcon#read 5, iclass 24, count 0 2006.286.03:38:04.61#ibcon#about to read 6, iclass 24, count 0 2006.286.03:38:04.61#ibcon#read 6, iclass 24, count 0 2006.286.03:38:04.61#ibcon#end of sib2, iclass 24, count 0 2006.286.03:38:04.61#ibcon#*mode == 0, iclass 24, count 0 2006.286.03:38:04.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.03:38:04.61#ibcon#[27=USB\r\n] 2006.286.03:38:04.61#ibcon#*before write, iclass 24, count 0 2006.286.03:38:04.61#ibcon#enter sib2, iclass 24, count 0 2006.286.03:38:04.61#ibcon#flushed, iclass 24, count 0 2006.286.03:38:04.61#ibcon#about to write, iclass 24, count 0 2006.286.03:38:04.61#ibcon#wrote, iclass 24, count 0 2006.286.03:38:04.61#ibcon#about to read 3, iclass 24, count 0 2006.286.03:38:04.64#ibcon#read 3, iclass 24, count 0 2006.286.03:38:04.64#ibcon#about to read 4, iclass 24, count 0 2006.286.03:38:04.64#ibcon#read 4, iclass 24, count 0 2006.286.03:38:04.64#ibcon#about to read 5, iclass 24, count 0 2006.286.03:38:04.64#ibcon#read 5, iclass 24, count 0 2006.286.03:38:04.64#ibcon#about to read 6, iclass 24, count 0 2006.286.03:38:04.64#ibcon#read 6, iclass 24, count 0 2006.286.03:38:04.64#ibcon#end of sib2, iclass 24, count 0 2006.286.03:38:04.64#ibcon#*after write, iclass 24, count 0 2006.286.03:38:04.64#ibcon#*before return 0, iclass 24, count 0 2006.286.03:38:04.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:38:04.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.03:38:04.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.03:38:04.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.03:38:04.64$vck44/vblo=5,709.99 2006.286.03:38:04.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.03:38:04.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.03:38:04.64#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:04.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:38:04.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:38:04.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:38:04.64#ibcon#enter wrdev, iclass 26, count 0 2006.286.03:38:04.64#ibcon#first serial, iclass 26, count 0 2006.286.03:38:04.64#ibcon#enter sib2, iclass 26, count 0 2006.286.03:38:04.64#ibcon#flushed, iclass 26, count 0 2006.286.03:38:04.64#ibcon#about to write, iclass 26, count 0 2006.286.03:38:04.64#ibcon#wrote, iclass 26, count 0 2006.286.03:38:04.64#ibcon#about to read 3, iclass 26, count 0 2006.286.03:38:04.66#ibcon#read 3, iclass 26, count 0 2006.286.03:38:04.66#ibcon#about to read 4, iclass 26, count 0 2006.286.03:38:04.66#ibcon#read 4, iclass 26, count 0 2006.286.03:38:04.66#ibcon#about to read 5, iclass 26, count 0 2006.286.03:38:04.66#ibcon#read 5, iclass 26, count 0 2006.286.03:38:04.66#ibcon#about to read 6, iclass 26, count 0 2006.286.03:38:04.66#ibcon#read 6, iclass 26, count 0 2006.286.03:38:04.66#ibcon#end of sib2, iclass 26, count 0 2006.286.03:38:04.66#ibcon#*mode == 0, iclass 26, count 0 2006.286.03:38:04.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.03:38:04.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.03:38:04.66#ibcon#*before write, iclass 26, count 0 2006.286.03:38:04.66#ibcon#enter sib2, iclass 26, count 0 2006.286.03:38:04.66#ibcon#flushed, iclass 26, count 0 2006.286.03:38:04.66#ibcon#about to write, iclass 26, count 0 2006.286.03:38:04.66#ibcon#wrote, iclass 26, count 0 2006.286.03:38:04.66#ibcon#about to read 3, iclass 26, count 0 2006.286.03:38:04.70#ibcon#read 3, iclass 26, count 0 2006.286.03:38:04.70#ibcon#about to read 4, iclass 26, count 0 2006.286.03:38:04.70#ibcon#read 4, iclass 26, count 0 2006.286.03:38:04.70#ibcon#about to read 5, iclass 26, count 0 2006.286.03:38:04.70#ibcon#read 5, iclass 26, count 0 2006.286.03:38:04.70#ibcon#about to read 6, iclass 26, count 0 2006.286.03:38:04.70#ibcon#read 6, iclass 26, count 0 2006.286.03:38:04.70#ibcon#end of sib2, iclass 26, count 0 2006.286.03:38:04.70#ibcon#*after write, iclass 26, count 0 2006.286.03:38:04.70#ibcon#*before return 0, iclass 26, count 0 2006.286.03:38:04.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:38:04.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.03:38:04.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.03:38:04.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.03:38:04.70$vck44/vb=5,4 2006.286.03:38:04.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.03:38:04.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.03:38:04.70#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:04.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:38:04.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:38:04.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:38:04.76#ibcon#enter wrdev, iclass 28, count 2 2006.286.03:38:04.76#ibcon#first serial, iclass 28, count 2 2006.286.03:38:04.76#ibcon#enter sib2, iclass 28, count 2 2006.286.03:38:04.76#ibcon#flushed, iclass 28, count 2 2006.286.03:38:04.76#ibcon#about to write, iclass 28, count 2 2006.286.03:38:04.76#ibcon#wrote, iclass 28, count 2 2006.286.03:38:04.76#ibcon#about to read 3, iclass 28, count 2 2006.286.03:38:04.78#ibcon#read 3, iclass 28, count 2 2006.286.03:38:04.78#ibcon#about to read 4, iclass 28, count 2 2006.286.03:38:04.78#ibcon#read 4, iclass 28, count 2 2006.286.03:38:04.78#ibcon#about to read 5, iclass 28, count 2 2006.286.03:38:04.78#ibcon#read 5, iclass 28, count 2 2006.286.03:38:04.78#ibcon#about to read 6, iclass 28, count 2 2006.286.03:38:04.78#ibcon#read 6, iclass 28, count 2 2006.286.03:38:04.78#ibcon#end of sib2, iclass 28, count 2 2006.286.03:38:04.78#ibcon#*mode == 0, iclass 28, count 2 2006.286.03:38:04.78#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.03:38:04.78#ibcon#[27=AT05-04\r\n] 2006.286.03:38:04.78#ibcon#*before write, iclass 28, count 2 2006.286.03:38:04.78#ibcon#enter sib2, iclass 28, count 2 2006.286.03:38:04.78#ibcon#flushed, iclass 28, count 2 2006.286.03:38:04.78#ibcon#about to write, iclass 28, count 2 2006.286.03:38:04.78#ibcon#wrote, iclass 28, count 2 2006.286.03:38:04.78#ibcon#about to read 3, iclass 28, count 2 2006.286.03:38:04.81#ibcon#read 3, iclass 28, count 2 2006.286.03:38:04.81#ibcon#about to read 4, iclass 28, count 2 2006.286.03:38:04.81#ibcon#read 4, iclass 28, count 2 2006.286.03:38:04.81#ibcon#about to read 5, iclass 28, count 2 2006.286.03:38:04.81#ibcon#read 5, iclass 28, count 2 2006.286.03:38:04.81#ibcon#about to read 6, iclass 28, count 2 2006.286.03:38:04.81#ibcon#read 6, iclass 28, count 2 2006.286.03:38:04.81#ibcon#end of sib2, iclass 28, count 2 2006.286.03:38:04.81#ibcon#*after write, iclass 28, count 2 2006.286.03:38:04.81#ibcon#*before return 0, iclass 28, count 2 2006.286.03:38:04.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:38:04.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.03:38:04.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.03:38:04.81#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:04.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:38:04.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:38:05.15#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:38:05.15#ibcon#enter wrdev, iclass 28, count 0 2006.286.03:38:05.15#ibcon#first serial, iclass 28, count 0 2006.286.03:38:05.15#ibcon#enter sib2, iclass 28, count 0 2006.286.03:38:05.15#ibcon#flushed, iclass 28, count 0 2006.286.03:38:05.15#ibcon#about to write, iclass 28, count 0 2006.286.03:38:05.15#ibcon#wrote, iclass 28, count 0 2006.286.03:38:05.15#ibcon#about to read 3, iclass 28, count 0 2006.286.03:38:05.16#ibcon#read 3, iclass 28, count 0 2006.286.03:38:05.16#ibcon#about to read 4, iclass 28, count 0 2006.286.03:38:05.16#ibcon#read 4, iclass 28, count 0 2006.286.03:38:05.16#ibcon#about to read 5, iclass 28, count 0 2006.286.03:38:05.16#ibcon#read 5, iclass 28, count 0 2006.286.03:38:05.16#ibcon#about to read 6, iclass 28, count 0 2006.286.03:38:05.16#ibcon#read 6, iclass 28, count 0 2006.286.03:38:05.16#ibcon#end of sib2, iclass 28, count 0 2006.286.03:38:05.16#ibcon#*mode == 0, iclass 28, count 0 2006.286.03:38:05.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.03:38:05.16#ibcon#[27=USB\r\n] 2006.286.03:38:05.16#ibcon#*before write, iclass 28, count 0 2006.286.03:38:05.16#ibcon#enter sib2, iclass 28, count 0 2006.286.03:38:05.16#ibcon#flushed, iclass 28, count 0 2006.286.03:38:05.16#ibcon#about to write, iclass 28, count 0 2006.286.03:38:05.16#ibcon#wrote, iclass 28, count 0 2006.286.03:38:05.16#ibcon#about to read 3, iclass 28, count 0 2006.286.03:38:05.19#ibcon#read 3, iclass 28, count 0 2006.286.03:38:05.19#ibcon#about to read 4, iclass 28, count 0 2006.286.03:38:05.19#ibcon#read 4, iclass 28, count 0 2006.286.03:38:05.19#ibcon#about to read 5, iclass 28, count 0 2006.286.03:38:05.19#ibcon#read 5, iclass 28, count 0 2006.286.03:38:05.19#ibcon#about to read 6, iclass 28, count 0 2006.286.03:38:05.19#ibcon#read 6, iclass 28, count 0 2006.286.03:38:05.19#ibcon#end of sib2, iclass 28, count 0 2006.286.03:38:05.19#ibcon#*after write, iclass 28, count 0 2006.286.03:38:05.19#ibcon#*before return 0, iclass 28, count 0 2006.286.03:38:05.19#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:38:05.19#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.03:38:05.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.03:38:05.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.03:38:05.19$vck44/vblo=6,719.99 2006.286.03:38:05.19#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.03:38:05.19#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.03:38:05.19#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:05.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:38:05.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:38:05.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:38:05.19#ibcon#enter wrdev, iclass 30, count 0 2006.286.03:38:05.19#ibcon#first serial, iclass 30, count 0 2006.286.03:38:05.19#ibcon#enter sib2, iclass 30, count 0 2006.286.03:38:05.19#ibcon#flushed, iclass 30, count 0 2006.286.03:38:05.19#ibcon#about to write, iclass 30, count 0 2006.286.03:38:05.19#ibcon#wrote, iclass 30, count 0 2006.286.03:38:05.19#ibcon#about to read 3, iclass 30, count 0 2006.286.03:38:05.21#ibcon#read 3, iclass 30, count 0 2006.286.03:38:05.21#ibcon#about to read 4, iclass 30, count 0 2006.286.03:38:05.21#ibcon#read 4, iclass 30, count 0 2006.286.03:38:05.21#ibcon#about to read 5, iclass 30, count 0 2006.286.03:38:05.21#ibcon#read 5, iclass 30, count 0 2006.286.03:38:05.21#ibcon#about to read 6, iclass 30, count 0 2006.286.03:38:05.21#ibcon#read 6, iclass 30, count 0 2006.286.03:38:05.21#ibcon#end of sib2, iclass 30, count 0 2006.286.03:38:05.21#ibcon#*mode == 0, iclass 30, count 0 2006.286.03:38:05.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.03:38:05.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.03:38:05.21#ibcon#*before write, iclass 30, count 0 2006.286.03:38:05.21#ibcon#enter sib2, iclass 30, count 0 2006.286.03:38:05.21#ibcon#flushed, iclass 30, count 0 2006.286.03:38:05.21#ibcon#about to write, iclass 30, count 0 2006.286.03:38:05.21#ibcon#wrote, iclass 30, count 0 2006.286.03:38:05.21#ibcon#about to read 3, iclass 30, count 0 2006.286.03:38:05.25#ibcon#read 3, iclass 30, count 0 2006.286.03:38:05.25#ibcon#about to read 4, iclass 30, count 0 2006.286.03:38:05.25#ibcon#read 4, iclass 30, count 0 2006.286.03:38:05.25#ibcon#about to read 5, iclass 30, count 0 2006.286.03:38:05.25#ibcon#read 5, iclass 30, count 0 2006.286.03:38:05.25#ibcon#about to read 6, iclass 30, count 0 2006.286.03:38:05.25#ibcon#read 6, iclass 30, count 0 2006.286.03:38:05.25#ibcon#end of sib2, iclass 30, count 0 2006.286.03:38:05.25#ibcon#*after write, iclass 30, count 0 2006.286.03:38:05.25#ibcon#*before return 0, iclass 30, count 0 2006.286.03:38:05.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:38:05.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.03:38:05.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.03:38:05.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.03:38:05.25$vck44/vb=6,3 2006.286.03:38:05.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.03:38:05.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.03:38:05.25#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:05.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:38:05.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:38:05.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:38:05.31#ibcon#enter wrdev, iclass 32, count 2 2006.286.03:38:05.31#ibcon#first serial, iclass 32, count 2 2006.286.03:38:05.31#ibcon#enter sib2, iclass 32, count 2 2006.286.03:38:05.31#ibcon#flushed, iclass 32, count 2 2006.286.03:38:05.31#ibcon#about to write, iclass 32, count 2 2006.286.03:38:05.31#ibcon#wrote, iclass 32, count 2 2006.286.03:38:05.31#ibcon#about to read 3, iclass 32, count 2 2006.286.03:38:05.33#ibcon#read 3, iclass 32, count 2 2006.286.03:38:05.33#ibcon#about to read 4, iclass 32, count 2 2006.286.03:38:05.33#ibcon#read 4, iclass 32, count 2 2006.286.03:38:05.33#ibcon#about to read 5, iclass 32, count 2 2006.286.03:38:05.33#ibcon#read 5, iclass 32, count 2 2006.286.03:38:05.33#ibcon#about to read 6, iclass 32, count 2 2006.286.03:38:05.33#ibcon#read 6, iclass 32, count 2 2006.286.03:38:05.33#ibcon#end of sib2, iclass 32, count 2 2006.286.03:38:05.33#ibcon#*mode == 0, iclass 32, count 2 2006.286.03:38:05.33#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.03:38:05.33#ibcon#[27=AT06-03\r\n] 2006.286.03:38:05.33#ibcon#*before write, iclass 32, count 2 2006.286.03:38:05.33#ibcon#enter sib2, iclass 32, count 2 2006.286.03:38:05.33#ibcon#flushed, iclass 32, count 2 2006.286.03:38:05.33#ibcon#about to write, iclass 32, count 2 2006.286.03:38:05.33#ibcon#wrote, iclass 32, count 2 2006.286.03:38:05.33#ibcon#about to read 3, iclass 32, count 2 2006.286.03:38:05.36#ibcon#read 3, iclass 32, count 2 2006.286.03:38:05.36#ibcon#about to read 4, iclass 32, count 2 2006.286.03:38:05.36#ibcon#read 4, iclass 32, count 2 2006.286.03:38:05.36#ibcon#about to read 5, iclass 32, count 2 2006.286.03:38:05.36#ibcon#read 5, iclass 32, count 2 2006.286.03:38:05.36#ibcon#about to read 6, iclass 32, count 2 2006.286.03:38:05.36#ibcon#read 6, iclass 32, count 2 2006.286.03:38:05.36#ibcon#end of sib2, iclass 32, count 2 2006.286.03:38:05.36#ibcon#*after write, iclass 32, count 2 2006.286.03:38:05.36#ibcon#*before return 0, iclass 32, count 2 2006.286.03:38:05.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:38:05.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.03:38:05.36#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.03:38:05.36#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:05.36#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:38:05.48#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:38:05.48#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:38:05.48#ibcon#enter wrdev, iclass 32, count 0 2006.286.03:38:05.48#ibcon#first serial, iclass 32, count 0 2006.286.03:38:05.48#ibcon#enter sib2, iclass 32, count 0 2006.286.03:38:05.48#ibcon#flushed, iclass 32, count 0 2006.286.03:38:05.48#ibcon#about to write, iclass 32, count 0 2006.286.03:38:05.48#ibcon#wrote, iclass 32, count 0 2006.286.03:38:05.48#ibcon#about to read 3, iclass 32, count 0 2006.286.03:38:05.50#ibcon#read 3, iclass 32, count 0 2006.286.03:38:05.50#ibcon#about to read 4, iclass 32, count 0 2006.286.03:38:05.50#ibcon#read 4, iclass 32, count 0 2006.286.03:38:05.50#ibcon#about to read 5, iclass 32, count 0 2006.286.03:38:05.50#ibcon#read 5, iclass 32, count 0 2006.286.03:38:05.50#ibcon#about to read 6, iclass 32, count 0 2006.286.03:38:05.50#ibcon#read 6, iclass 32, count 0 2006.286.03:38:05.50#ibcon#end of sib2, iclass 32, count 0 2006.286.03:38:05.50#ibcon#*mode == 0, iclass 32, count 0 2006.286.03:38:05.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.03:38:05.50#ibcon#[27=USB\r\n] 2006.286.03:38:05.50#ibcon#*before write, iclass 32, count 0 2006.286.03:38:05.50#ibcon#enter sib2, iclass 32, count 0 2006.286.03:38:05.50#ibcon#flushed, iclass 32, count 0 2006.286.03:38:05.50#ibcon#about to write, iclass 32, count 0 2006.286.03:38:05.50#ibcon#wrote, iclass 32, count 0 2006.286.03:38:05.50#ibcon#about to read 3, iclass 32, count 0 2006.286.03:38:05.53#ibcon#read 3, iclass 32, count 0 2006.286.03:38:05.53#ibcon#about to read 4, iclass 32, count 0 2006.286.03:38:05.53#ibcon#read 4, iclass 32, count 0 2006.286.03:38:05.53#ibcon#about to read 5, iclass 32, count 0 2006.286.03:38:05.53#ibcon#read 5, iclass 32, count 0 2006.286.03:38:05.53#ibcon#about to read 6, iclass 32, count 0 2006.286.03:38:05.53#ibcon#read 6, iclass 32, count 0 2006.286.03:38:05.53#ibcon#end of sib2, iclass 32, count 0 2006.286.03:38:05.53#ibcon#*after write, iclass 32, count 0 2006.286.03:38:05.53#ibcon#*before return 0, iclass 32, count 0 2006.286.03:38:05.53#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:38:05.53#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.03:38:05.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.03:38:05.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.03:38:05.53$vck44/vblo=7,734.99 2006.286.03:38:05.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.03:38:05.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.03:38:05.53#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:05.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:38:05.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:38:05.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:38:05.53#ibcon#enter wrdev, iclass 34, count 0 2006.286.03:38:05.53#ibcon#first serial, iclass 34, count 0 2006.286.03:38:05.53#ibcon#enter sib2, iclass 34, count 0 2006.286.03:38:05.53#ibcon#flushed, iclass 34, count 0 2006.286.03:38:05.53#ibcon#about to write, iclass 34, count 0 2006.286.03:38:05.53#ibcon#wrote, iclass 34, count 0 2006.286.03:38:05.53#ibcon#about to read 3, iclass 34, count 0 2006.286.03:38:05.55#ibcon#read 3, iclass 34, count 0 2006.286.03:38:05.55#ibcon#about to read 4, iclass 34, count 0 2006.286.03:38:05.55#ibcon#read 4, iclass 34, count 0 2006.286.03:38:05.55#ibcon#about to read 5, iclass 34, count 0 2006.286.03:38:05.55#ibcon#read 5, iclass 34, count 0 2006.286.03:38:05.55#ibcon#about to read 6, iclass 34, count 0 2006.286.03:38:05.55#ibcon#read 6, iclass 34, count 0 2006.286.03:38:05.55#ibcon#end of sib2, iclass 34, count 0 2006.286.03:38:05.55#ibcon#*mode == 0, iclass 34, count 0 2006.286.03:38:05.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.03:38:05.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.03:38:05.55#ibcon#*before write, iclass 34, count 0 2006.286.03:38:05.55#ibcon#enter sib2, iclass 34, count 0 2006.286.03:38:05.55#ibcon#flushed, iclass 34, count 0 2006.286.03:38:05.55#ibcon#about to write, iclass 34, count 0 2006.286.03:38:05.55#ibcon#wrote, iclass 34, count 0 2006.286.03:38:05.55#ibcon#about to read 3, iclass 34, count 0 2006.286.03:38:05.59#ibcon#read 3, iclass 34, count 0 2006.286.03:38:05.59#ibcon#about to read 4, iclass 34, count 0 2006.286.03:38:05.59#ibcon#read 4, iclass 34, count 0 2006.286.03:38:05.59#ibcon#about to read 5, iclass 34, count 0 2006.286.03:38:05.59#ibcon#read 5, iclass 34, count 0 2006.286.03:38:05.59#ibcon#about to read 6, iclass 34, count 0 2006.286.03:38:05.59#ibcon#read 6, iclass 34, count 0 2006.286.03:38:05.59#ibcon#end of sib2, iclass 34, count 0 2006.286.03:38:05.59#ibcon#*after write, iclass 34, count 0 2006.286.03:38:05.59#ibcon#*before return 0, iclass 34, count 0 2006.286.03:38:05.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:38:05.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.03:38:05.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.03:38:05.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.03:38:05.59$vck44/vb=7,4 2006.286.03:38:05.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.03:38:05.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.03:38:05.59#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:05.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:38:05.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:38:05.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:38:05.65#ibcon#enter wrdev, iclass 36, count 2 2006.286.03:38:05.65#ibcon#first serial, iclass 36, count 2 2006.286.03:38:05.65#ibcon#enter sib2, iclass 36, count 2 2006.286.03:38:05.65#ibcon#flushed, iclass 36, count 2 2006.286.03:38:05.65#ibcon#about to write, iclass 36, count 2 2006.286.03:38:05.65#ibcon#wrote, iclass 36, count 2 2006.286.03:38:05.65#ibcon#about to read 3, iclass 36, count 2 2006.286.03:38:05.67#ibcon#read 3, iclass 36, count 2 2006.286.03:38:05.67#ibcon#about to read 4, iclass 36, count 2 2006.286.03:38:05.67#ibcon#read 4, iclass 36, count 2 2006.286.03:38:05.67#ibcon#about to read 5, iclass 36, count 2 2006.286.03:38:05.67#ibcon#read 5, iclass 36, count 2 2006.286.03:38:05.67#ibcon#about to read 6, iclass 36, count 2 2006.286.03:38:05.67#ibcon#read 6, iclass 36, count 2 2006.286.03:38:05.67#ibcon#end of sib2, iclass 36, count 2 2006.286.03:38:05.67#ibcon#*mode == 0, iclass 36, count 2 2006.286.03:38:05.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.03:38:05.67#ibcon#[27=AT07-04\r\n] 2006.286.03:38:05.67#ibcon#*before write, iclass 36, count 2 2006.286.03:38:05.67#ibcon#enter sib2, iclass 36, count 2 2006.286.03:38:05.67#ibcon#flushed, iclass 36, count 2 2006.286.03:38:05.67#ibcon#about to write, iclass 36, count 2 2006.286.03:38:05.67#ibcon#wrote, iclass 36, count 2 2006.286.03:38:05.67#ibcon#about to read 3, iclass 36, count 2 2006.286.03:38:05.70#ibcon#read 3, iclass 36, count 2 2006.286.03:38:05.70#ibcon#about to read 4, iclass 36, count 2 2006.286.03:38:05.70#ibcon#read 4, iclass 36, count 2 2006.286.03:38:05.70#ibcon#about to read 5, iclass 36, count 2 2006.286.03:38:05.70#ibcon#read 5, iclass 36, count 2 2006.286.03:38:05.70#ibcon#about to read 6, iclass 36, count 2 2006.286.03:38:05.70#ibcon#read 6, iclass 36, count 2 2006.286.03:38:05.70#ibcon#end of sib2, iclass 36, count 2 2006.286.03:38:05.70#ibcon#*after write, iclass 36, count 2 2006.286.03:38:05.70#ibcon#*before return 0, iclass 36, count 2 2006.286.03:38:05.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:38:05.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.03:38:05.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.03:38:05.70#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:05.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:38:05.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:38:05.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:38:05.82#ibcon#enter wrdev, iclass 36, count 0 2006.286.03:38:05.82#ibcon#first serial, iclass 36, count 0 2006.286.03:38:05.82#ibcon#enter sib2, iclass 36, count 0 2006.286.03:38:05.82#ibcon#flushed, iclass 36, count 0 2006.286.03:38:05.82#ibcon#about to write, iclass 36, count 0 2006.286.03:38:05.82#ibcon#wrote, iclass 36, count 0 2006.286.03:38:05.82#ibcon#about to read 3, iclass 36, count 0 2006.286.03:38:05.84#ibcon#read 3, iclass 36, count 0 2006.286.03:38:05.84#ibcon#about to read 4, iclass 36, count 0 2006.286.03:38:05.84#ibcon#read 4, iclass 36, count 0 2006.286.03:38:05.84#ibcon#about to read 5, iclass 36, count 0 2006.286.03:38:05.84#ibcon#read 5, iclass 36, count 0 2006.286.03:38:05.84#ibcon#about to read 6, iclass 36, count 0 2006.286.03:38:05.84#ibcon#read 6, iclass 36, count 0 2006.286.03:38:05.84#ibcon#end of sib2, iclass 36, count 0 2006.286.03:38:05.84#ibcon#*mode == 0, iclass 36, count 0 2006.286.03:38:05.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.03:38:05.84#ibcon#[27=USB\r\n] 2006.286.03:38:05.84#ibcon#*before write, iclass 36, count 0 2006.286.03:38:05.84#ibcon#enter sib2, iclass 36, count 0 2006.286.03:38:05.84#ibcon#flushed, iclass 36, count 0 2006.286.03:38:05.84#ibcon#about to write, iclass 36, count 0 2006.286.03:38:05.84#ibcon#wrote, iclass 36, count 0 2006.286.03:38:05.84#ibcon#about to read 3, iclass 36, count 0 2006.286.03:38:05.87#ibcon#read 3, iclass 36, count 0 2006.286.03:38:05.87#ibcon#about to read 4, iclass 36, count 0 2006.286.03:38:05.87#ibcon#read 4, iclass 36, count 0 2006.286.03:38:05.87#ibcon#about to read 5, iclass 36, count 0 2006.286.03:38:05.87#ibcon#read 5, iclass 36, count 0 2006.286.03:38:05.87#ibcon#about to read 6, iclass 36, count 0 2006.286.03:38:05.87#ibcon#read 6, iclass 36, count 0 2006.286.03:38:05.87#ibcon#end of sib2, iclass 36, count 0 2006.286.03:38:05.87#ibcon#*after write, iclass 36, count 0 2006.286.03:38:05.87#ibcon#*before return 0, iclass 36, count 0 2006.286.03:38:05.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:38:05.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.03:38:05.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.03:38:05.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.03:38:05.87$vck44/vblo=8,744.99 2006.286.03:38:05.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.03:38:05.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.03:38:05.87#ibcon#ireg 17 cls_cnt 0 2006.286.03:38:05.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:38:05.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:38:05.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:38:05.87#ibcon#enter wrdev, iclass 38, count 0 2006.286.03:38:05.87#ibcon#first serial, iclass 38, count 0 2006.286.03:38:05.87#ibcon#enter sib2, iclass 38, count 0 2006.286.03:38:05.87#ibcon#flushed, iclass 38, count 0 2006.286.03:38:05.87#ibcon#about to write, iclass 38, count 0 2006.286.03:38:05.87#ibcon#wrote, iclass 38, count 0 2006.286.03:38:05.87#ibcon#about to read 3, iclass 38, count 0 2006.286.03:38:05.89#ibcon#read 3, iclass 38, count 0 2006.286.03:38:05.96#ibcon#about to read 4, iclass 38, count 0 2006.286.03:38:05.96#ibcon#read 4, iclass 38, count 0 2006.286.03:38:05.96#ibcon#about to read 5, iclass 38, count 0 2006.286.03:38:05.96#ibcon#read 5, iclass 38, count 0 2006.286.03:38:05.96#ibcon#about to read 6, iclass 38, count 0 2006.286.03:38:05.96#ibcon#read 6, iclass 38, count 0 2006.286.03:38:05.96#ibcon#end of sib2, iclass 38, count 0 2006.286.03:38:05.96#ibcon#*mode == 0, iclass 38, count 0 2006.286.03:38:05.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.03:38:05.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.03:38:05.96#ibcon#*before write, iclass 38, count 0 2006.286.03:38:05.96#ibcon#enter sib2, iclass 38, count 0 2006.286.03:38:05.96#ibcon#flushed, iclass 38, count 0 2006.286.03:38:05.96#ibcon#about to write, iclass 38, count 0 2006.286.03:38:05.96#ibcon#wrote, iclass 38, count 0 2006.286.03:38:05.96#ibcon#about to read 3, iclass 38, count 0 2006.286.03:38:06.00#ibcon#read 3, iclass 38, count 0 2006.286.03:38:06.00#ibcon#about to read 4, iclass 38, count 0 2006.286.03:38:06.00#ibcon#read 4, iclass 38, count 0 2006.286.03:38:06.00#ibcon#about to read 5, iclass 38, count 0 2006.286.03:38:06.00#ibcon#read 5, iclass 38, count 0 2006.286.03:38:06.00#ibcon#about to read 6, iclass 38, count 0 2006.286.03:38:06.00#ibcon#read 6, iclass 38, count 0 2006.286.03:38:06.00#ibcon#end of sib2, iclass 38, count 0 2006.286.03:38:06.00#ibcon#*after write, iclass 38, count 0 2006.286.03:38:06.00#ibcon#*before return 0, iclass 38, count 0 2006.286.03:38:06.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:38:06.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.03:38:06.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.03:38:06.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.03:38:06.00$vck44/vb=8,4 2006.286.03:38:06.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.03:38:06.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.03:38:06.00#ibcon#ireg 11 cls_cnt 2 2006.286.03:38:06.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:38:06.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:38:06.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:38:06.00#ibcon#enter wrdev, iclass 40, count 2 2006.286.03:38:06.00#ibcon#first serial, iclass 40, count 2 2006.286.03:38:06.00#ibcon#enter sib2, iclass 40, count 2 2006.286.03:38:06.00#ibcon#flushed, iclass 40, count 2 2006.286.03:38:06.00#ibcon#about to write, iclass 40, count 2 2006.286.03:38:06.00#ibcon#wrote, iclass 40, count 2 2006.286.03:38:06.00#ibcon#about to read 3, iclass 40, count 2 2006.286.03:38:06.02#ibcon#read 3, iclass 40, count 2 2006.286.03:38:06.02#ibcon#about to read 4, iclass 40, count 2 2006.286.03:38:06.02#ibcon#read 4, iclass 40, count 2 2006.286.03:38:06.02#ibcon#about to read 5, iclass 40, count 2 2006.286.03:38:06.02#ibcon#read 5, iclass 40, count 2 2006.286.03:38:06.02#ibcon#about to read 6, iclass 40, count 2 2006.286.03:38:06.02#ibcon#read 6, iclass 40, count 2 2006.286.03:38:06.02#ibcon#end of sib2, iclass 40, count 2 2006.286.03:38:06.02#ibcon#*mode == 0, iclass 40, count 2 2006.286.03:38:06.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.03:38:06.02#ibcon#[27=AT08-04\r\n] 2006.286.03:38:06.02#ibcon#*before write, iclass 40, count 2 2006.286.03:38:06.02#ibcon#enter sib2, iclass 40, count 2 2006.286.03:38:06.02#ibcon#flushed, iclass 40, count 2 2006.286.03:38:06.02#ibcon#about to write, iclass 40, count 2 2006.286.03:38:06.02#ibcon#wrote, iclass 40, count 2 2006.286.03:38:06.02#ibcon#about to read 3, iclass 40, count 2 2006.286.03:38:06.05#ibcon#read 3, iclass 40, count 2 2006.286.03:38:06.05#ibcon#about to read 4, iclass 40, count 2 2006.286.03:38:06.05#ibcon#read 4, iclass 40, count 2 2006.286.03:38:06.05#ibcon#about to read 5, iclass 40, count 2 2006.286.03:38:06.05#ibcon#read 5, iclass 40, count 2 2006.286.03:38:06.05#ibcon#about to read 6, iclass 40, count 2 2006.286.03:38:06.05#ibcon#read 6, iclass 40, count 2 2006.286.03:38:06.05#ibcon#end of sib2, iclass 40, count 2 2006.286.03:38:06.05#ibcon#*after write, iclass 40, count 2 2006.286.03:38:06.05#ibcon#*before return 0, iclass 40, count 2 2006.286.03:38:06.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:38:06.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.03:38:06.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.03:38:06.05#ibcon#ireg 7 cls_cnt 0 2006.286.03:38:06.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:38:06.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:38:06.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:38:06.17#ibcon#enter wrdev, iclass 40, count 0 2006.286.03:38:06.17#ibcon#first serial, iclass 40, count 0 2006.286.03:38:06.17#ibcon#enter sib2, iclass 40, count 0 2006.286.03:38:06.17#ibcon#flushed, iclass 40, count 0 2006.286.03:38:06.17#ibcon#about to write, iclass 40, count 0 2006.286.03:38:06.17#ibcon#wrote, iclass 40, count 0 2006.286.03:38:06.17#ibcon#about to read 3, iclass 40, count 0 2006.286.03:38:06.19#ibcon#read 3, iclass 40, count 0 2006.286.03:38:06.19#ibcon#about to read 4, iclass 40, count 0 2006.286.03:38:06.19#ibcon#read 4, iclass 40, count 0 2006.286.03:38:06.19#ibcon#about to read 5, iclass 40, count 0 2006.286.03:38:06.19#ibcon#read 5, iclass 40, count 0 2006.286.03:38:06.19#ibcon#about to read 6, iclass 40, count 0 2006.286.03:38:06.19#ibcon#read 6, iclass 40, count 0 2006.286.03:38:06.19#ibcon#end of sib2, iclass 40, count 0 2006.286.03:38:06.19#ibcon#*mode == 0, iclass 40, count 0 2006.286.03:38:06.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.03:38:06.19#ibcon#[27=USB\r\n] 2006.286.03:38:06.19#ibcon#*before write, iclass 40, count 0 2006.286.03:38:06.19#ibcon#enter sib2, iclass 40, count 0 2006.286.03:38:06.19#ibcon#flushed, iclass 40, count 0 2006.286.03:38:06.19#ibcon#about to write, iclass 40, count 0 2006.286.03:38:06.19#ibcon#wrote, iclass 40, count 0 2006.286.03:38:06.19#ibcon#about to read 3, iclass 40, count 0 2006.286.03:38:06.22#ibcon#read 3, iclass 40, count 0 2006.286.03:38:06.22#ibcon#about to read 4, iclass 40, count 0 2006.286.03:38:06.22#ibcon#read 4, iclass 40, count 0 2006.286.03:38:06.22#ibcon#about to read 5, iclass 40, count 0 2006.286.03:38:06.22#ibcon#read 5, iclass 40, count 0 2006.286.03:38:06.22#ibcon#about to read 6, iclass 40, count 0 2006.286.03:38:06.22#ibcon#read 6, iclass 40, count 0 2006.286.03:38:06.22#ibcon#end of sib2, iclass 40, count 0 2006.286.03:38:06.22#ibcon#*after write, iclass 40, count 0 2006.286.03:38:06.22#ibcon#*before return 0, iclass 40, count 0 2006.286.03:38:06.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:38:06.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.03:38:06.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.03:38:06.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.03:38:06.22$vck44/vabw=wide 2006.286.03:38:06.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.03:38:06.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.03:38:06.22#ibcon#ireg 8 cls_cnt 0 2006.286.03:38:06.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:38:06.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:38:06.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:38:06.22#ibcon#enter wrdev, iclass 4, count 0 2006.286.03:38:06.22#ibcon#first serial, iclass 4, count 0 2006.286.03:38:06.22#ibcon#enter sib2, iclass 4, count 0 2006.286.03:38:06.22#ibcon#flushed, iclass 4, count 0 2006.286.03:38:06.22#ibcon#about to write, iclass 4, count 0 2006.286.03:38:06.22#ibcon#wrote, iclass 4, count 0 2006.286.03:38:06.22#ibcon#about to read 3, iclass 4, count 0 2006.286.03:38:06.24#ibcon#read 3, iclass 4, count 0 2006.286.03:38:06.24#ibcon#about to read 4, iclass 4, count 0 2006.286.03:38:06.24#ibcon#read 4, iclass 4, count 0 2006.286.03:38:06.24#ibcon#about to read 5, iclass 4, count 0 2006.286.03:38:06.24#ibcon#read 5, iclass 4, count 0 2006.286.03:38:06.24#ibcon#about to read 6, iclass 4, count 0 2006.286.03:38:06.24#ibcon#read 6, iclass 4, count 0 2006.286.03:38:06.24#ibcon#end of sib2, iclass 4, count 0 2006.286.03:38:06.24#ibcon#*mode == 0, iclass 4, count 0 2006.286.03:38:06.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.03:38:06.24#ibcon#[25=BW32\r\n] 2006.286.03:38:06.24#ibcon#*before write, iclass 4, count 0 2006.286.03:38:06.24#ibcon#enter sib2, iclass 4, count 0 2006.286.03:38:06.24#ibcon#flushed, iclass 4, count 0 2006.286.03:38:06.24#ibcon#about to write, iclass 4, count 0 2006.286.03:38:06.24#ibcon#wrote, iclass 4, count 0 2006.286.03:38:06.24#ibcon#about to read 3, iclass 4, count 0 2006.286.03:38:06.27#ibcon#read 3, iclass 4, count 0 2006.286.03:38:06.27#ibcon#about to read 4, iclass 4, count 0 2006.286.03:38:06.27#ibcon#read 4, iclass 4, count 0 2006.286.03:38:06.27#ibcon#about to read 5, iclass 4, count 0 2006.286.03:38:06.27#ibcon#read 5, iclass 4, count 0 2006.286.03:38:06.27#ibcon#about to read 6, iclass 4, count 0 2006.286.03:38:06.27#ibcon#read 6, iclass 4, count 0 2006.286.03:38:06.27#ibcon#end of sib2, iclass 4, count 0 2006.286.03:38:06.27#ibcon#*after write, iclass 4, count 0 2006.286.03:38:06.27#ibcon#*before return 0, iclass 4, count 0 2006.286.03:38:06.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:38:06.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.03:38:06.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.03:38:06.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.03:38:06.27$vck44/vbbw=wide 2006.286.03:38:06.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.03:38:06.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.03:38:06.27#ibcon#ireg 8 cls_cnt 0 2006.286.03:38:06.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:38:06.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:38:06.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:38:06.34#ibcon#enter wrdev, iclass 6, count 0 2006.286.03:38:06.34#ibcon#first serial, iclass 6, count 0 2006.286.03:38:06.34#ibcon#enter sib2, iclass 6, count 0 2006.286.03:38:06.34#ibcon#flushed, iclass 6, count 0 2006.286.03:38:06.34#ibcon#about to write, iclass 6, count 0 2006.286.03:38:06.34#ibcon#wrote, iclass 6, count 0 2006.286.03:38:06.34#ibcon#about to read 3, iclass 6, count 0 2006.286.03:38:06.36#ibcon#read 3, iclass 6, count 0 2006.286.03:38:06.36#ibcon#about to read 4, iclass 6, count 0 2006.286.03:38:06.36#ibcon#read 4, iclass 6, count 0 2006.286.03:38:06.36#ibcon#about to read 5, iclass 6, count 0 2006.286.03:38:06.36#ibcon#read 5, iclass 6, count 0 2006.286.03:38:06.36#ibcon#about to read 6, iclass 6, count 0 2006.286.03:38:06.36#ibcon#read 6, iclass 6, count 0 2006.286.03:38:06.36#ibcon#end of sib2, iclass 6, count 0 2006.286.03:38:06.36#ibcon#*mode == 0, iclass 6, count 0 2006.286.03:38:06.36#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.03:38:06.36#ibcon#[27=BW32\r\n] 2006.286.03:38:06.36#ibcon#*before write, iclass 6, count 0 2006.286.03:38:06.36#ibcon#enter sib2, iclass 6, count 0 2006.286.03:38:06.36#ibcon#flushed, iclass 6, count 0 2006.286.03:38:06.36#ibcon#about to write, iclass 6, count 0 2006.286.03:38:06.36#ibcon#wrote, iclass 6, count 0 2006.286.03:38:06.36#ibcon#about to read 3, iclass 6, count 0 2006.286.03:38:06.39#ibcon#read 3, iclass 6, count 0 2006.286.03:38:06.39#ibcon#about to read 4, iclass 6, count 0 2006.286.03:38:06.39#ibcon#read 4, iclass 6, count 0 2006.286.03:38:06.39#ibcon#about to read 5, iclass 6, count 0 2006.286.03:38:06.39#ibcon#read 5, iclass 6, count 0 2006.286.03:38:06.39#ibcon#about to read 6, iclass 6, count 0 2006.286.03:38:06.39#ibcon#read 6, iclass 6, count 0 2006.286.03:38:06.39#ibcon#end of sib2, iclass 6, count 0 2006.286.03:38:06.39#ibcon#*after write, iclass 6, count 0 2006.286.03:38:06.39#ibcon#*before return 0, iclass 6, count 0 2006.286.03:38:06.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:38:06.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:38:06.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.03:38:06.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.03:38:06.39$setupk4/ifdk4 2006.286.03:38:06.39$ifdk4/lo= 2006.286.03:38:06.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.03:38:06.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.03:38:06.39$ifdk4/patch= 2006.286.03:38:06.39$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.03:38:06.39$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.03:38:06.39$setupk4/!*+20s 2006.286.03:38:13.31#abcon#<5=/04 3.3 6.8 21.67 781015.0\r\n> 2006.286.03:38:13.33#abcon#{5=INTERFACE CLEAR} 2006.286.03:38:13.39#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:38:19.69$setupk4/"tpicd 2006.286.03:38:19.69$setupk4/echo=off 2006.286.03:38:19.69$setupk4/xlog=off 2006.286.03:38:19.69:!2006.286.03:42:21 2006.286.03:38:44.14#trakl#Source acquired 2006.286.03:38:44.14#flagr#flagr/antenna,acquired 2006.286.03:42:21.00:preob 2006.286.03:42:21.14/onsource/TRACKING 2006.286.03:42:21.14:!2006.286.03:42:31 2006.286.03:42:31.00:"tape 2006.286.03:42:31.00:"st=record 2006.286.03:42:31.00:data_valid=on 2006.286.03:42:31.00:midob 2006.286.03:42:32.14/onsource/TRACKING 2006.286.03:42:32.14/wx/21.71,1015.0,78 2006.286.03:42:32.30/cable/+6.4958E-03 2006.286.03:42:33.39/va/01,07,usb,yes,33,36 2006.286.03:42:33.39/va/02,06,usb,yes,33,33 2006.286.03:42:33.39/va/03,07,usb,yes,33,34 2006.286.03:42:33.39/va/04,06,usb,yes,34,36 2006.286.03:42:33.39/va/05,03,usb,yes,34,34 2006.286.03:42:33.39/va/06,04,usb,yes,30,30 2006.286.03:42:33.39/va/07,04,usb,yes,31,32 2006.286.03:42:33.39/va/08,03,usb,yes,32,39 2006.286.03:42:33.62/valo/01,524.99,yes,locked 2006.286.03:42:33.62/valo/02,534.99,yes,locked 2006.286.03:42:33.62/valo/03,564.99,yes,locked 2006.286.03:42:33.62/valo/04,624.99,yes,locked 2006.286.03:42:33.62/valo/05,734.99,yes,locked 2006.286.03:42:33.62/valo/06,814.99,yes,locked 2006.286.03:42:33.62/valo/07,864.99,yes,locked 2006.286.03:42:33.62/valo/08,884.99,yes,locked 2006.286.03:42:34.71/vb/01,04,usb,yes,30,29 2006.286.03:42:34.71/vb/02,05,usb,yes,29,29 2006.286.03:42:34.71/vb/03,04,usb,yes,30,33 2006.286.03:42:34.71/vb/04,05,usb,yes,30,29 2006.286.03:42:34.71/vb/05,04,usb,yes,27,29 2006.286.03:42:34.71/vb/06,03,usb,yes,39,35 2006.286.03:42:34.71/vb/07,04,usb,yes,31,31 2006.286.03:42:34.71/vb/08,04,usb,yes,28,32 2006.286.03:42:34.94/vblo/01,629.99,yes,locked 2006.286.03:42:34.94/vblo/02,634.99,yes,locked 2006.286.03:42:34.94/vblo/03,649.99,yes,locked 2006.286.03:42:34.94/vblo/04,679.99,yes,locked 2006.286.03:42:34.94/vblo/05,709.99,yes,locked 2006.286.03:42:34.94/vblo/06,719.99,yes,locked 2006.286.03:42:34.94/vblo/07,734.99,yes,locked 2006.286.03:42:34.94/vblo/08,744.99,yes,locked 2006.286.03:42:35.09/vabw/8 2006.286.03:42:35.24/vbbw/8 2006.286.03:42:35.33/xfe/off,on,12.0 2006.286.03:42:35.70/ifatt/23,28,28,28 2006.286.03:42:36.08/fmout-gps/S +2.54E-07 2006.286.03:42:36.10:!2006.286.03:52:01 2006.286.03:52:01.01:data_valid=off 2006.286.03:52:01.02:"et 2006.286.03:52:01.02:!+3s 2006.286.03:52:04.04:"tape 2006.286.03:52:04.04:postob 2006.286.03:52:04.19/cable/+6.4956E-03 2006.286.03:52:04.19/wx/21.80,1015.0,77 2006.286.03:52:04.25/fmout-gps/S +2.38E-07 2006.286.03:52:04.25:scan_name=286-0357,jd0610,40 2006.286.03:52:04.26:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.286.03:52:05.14#flagr#flagr/antenna,new-source 2006.286.03:52:05.15:checkk5 2006.286.03:52:05.65/chk_autoobs//k5ts1/ autoobs is running! 2006.286.03:52:06.02/chk_autoobs//k5ts2/ autoobs is running! 2006.286.03:52:06.60/chk_autoobs//k5ts3/ autoobs is running! 2006.286.03:52:07.52/chk_autoobs//k5ts4/ autoobs is running! 2006.286.03:52:08.30/chk_obsdata//k5ts1/T2860342??a.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.286.03:52:09.05/chk_obsdata//k5ts2/T2860342??b.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.286.03:52:09.86/chk_obsdata//k5ts3/T2860342??c.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.286.03:52:11.09/chk_obsdata//k5ts4/T2860342??d.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.286.03:52:11.83/k5log//k5ts1_log_newline 2006.286.03:52:12.66/k5log//k5ts2_log_newline 2006.286.03:52:13.93/k5log//k5ts3_log_newline 2006.286.03:52:14.89/k5log//k5ts4_log_newline 2006.286.03:52:14.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.03:52:14.92:setupk4=1 2006.286.03:52:14.92$setupk4/echo=on 2006.286.03:52:14.92$setupk4/pcalon 2006.286.03:52:14.92$pcalon/"no phase cal control is implemented here 2006.286.03:52:14.92$setupk4/"tpicd=stop 2006.286.03:52:14.92$setupk4/"rec=synch_on 2006.286.03:52:14.92$setupk4/"rec_mode=128 2006.286.03:52:14.92$setupk4/!* 2006.286.03:52:14.92$setupk4/recpk4 2006.286.03:52:14.92$recpk4/recpatch= 2006.286.03:52:14.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.03:52:14.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.03:52:14.92$setupk4/vck44 2006.286.03:52:14.92$vck44/valo=1,524.99 2006.286.03:52:14.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.03:52:14.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.03:52:14.92#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:14.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:52:14.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:52:14.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:52:14.92#ibcon#enter wrdev, iclass 21, count 0 2006.286.03:52:14.92#ibcon#first serial, iclass 21, count 0 2006.286.03:52:14.92#ibcon#enter sib2, iclass 21, count 0 2006.286.03:52:14.92#ibcon#flushed, iclass 21, count 0 2006.286.03:52:14.92#ibcon#about to write, iclass 21, count 0 2006.286.03:52:14.92#ibcon#wrote, iclass 21, count 0 2006.286.03:52:14.92#ibcon#about to read 3, iclass 21, count 0 2006.286.03:52:14.93#ibcon#read 3, iclass 21, count 0 2006.286.03:52:14.93#ibcon#about to read 4, iclass 21, count 0 2006.286.03:52:14.93#ibcon#read 4, iclass 21, count 0 2006.286.03:52:14.93#ibcon#about to read 5, iclass 21, count 0 2006.286.03:52:14.93#ibcon#read 5, iclass 21, count 0 2006.286.03:52:14.93#ibcon#about to read 6, iclass 21, count 0 2006.286.03:52:14.93#ibcon#read 6, iclass 21, count 0 2006.286.03:52:14.93#ibcon#end of sib2, iclass 21, count 0 2006.286.03:52:14.93#ibcon#*mode == 0, iclass 21, count 0 2006.286.03:52:14.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.03:52:14.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.03:52:14.93#ibcon#*before write, iclass 21, count 0 2006.286.03:52:14.93#ibcon#enter sib2, iclass 21, count 0 2006.286.03:52:14.93#ibcon#flushed, iclass 21, count 0 2006.286.03:52:14.93#ibcon#about to write, iclass 21, count 0 2006.286.03:52:14.93#ibcon#wrote, iclass 21, count 0 2006.286.03:52:14.93#ibcon#about to read 3, iclass 21, count 0 2006.286.03:52:14.98#ibcon#read 3, iclass 21, count 0 2006.286.03:52:14.98#ibcon#about to read 4, iclass 21, count 0 2006.286.03:52:14.98#ibcon#read 4, iclass 21, count 0 2006.286.03:52:14.98#ibcon#about to read 5, iclass 21, count 0 2006.286.03:52:14.98#ibcon#read 5, iclass 21, count 0 2006.286.03:52:14.98#ibcon#about to read 6, iclass 21, count 0 2006.286.03:52:14.98#ibcon#read 6, iclass 21, count 0 2006.286.03:52:14.98#ibcon#end of sib2, iclass 21, count 0 2006.286.03:52:14.98#ibcon#*after write, iclass 21, count 0 2006.286.03:52:14.98#ibcon#*before return 0, iclass 21, count 0 2006.286.03:52:14.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:52:14.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:52:14.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.03:52:14.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.03:52:14.98$vck44/va=1,7 2006.286.03:52:14.98#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.03:52:14.98#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.03:52:14.98#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:14.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:52:14.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:52:14.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:52:14.98#ibcon#enter wrdev, iclass 23, count 2 2006.286.03:52:14.98#ibcon#first serial, iclass 23, count 2 2006.286.03:52:14.98#ibcon#enter sib2, iclass 23, count 2 2006.286.03:52:14.98#ibcon#flushed, iclass 23, count 2 2006.286.03:52:14.98#ibcon#about to write, iclass 23, count 2 2006.286.03:52:14.98#ibcon#wrote, iclass 23, count 2 2006.286.03:52:14.98#ibcon#about to read 3, iclass 23, count 2 2006.286.03:52:15.00#ibcon#read 3, iclass 23, count 2 2006.286.03:52:15.00#ibcon#about to read 4, iclass 23, count 2 2006.286.03:52:15.00#ibcon#read 4, iclass 23, count 2 2006.286.03:52:15.00#ibcon#about to read 5, iclass 23, count 2 2006.286.03:52:15.00#ibcon#read 5, iclass 23, count 2 2006.286.03:52:15.00#ibcon#about to read 6, iclass 23, count 2 2006.286.03:52:15.00#ibcon#read 6, iclass 23, count 2 2006.286.03:52:15.00#ibcon#end of sib2, iclass 23, count 2 2006.286.03:52:15.00#ibcon#*mode == 0, iclass 23, count 2 2006.286.03:52:15.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.03:52:15.00#ibcon#[25=AT01-07\r\n] 2006.286.03:52:15.00#ibcon#*before write, iclass 23, count 2 2006.286.03:52:15.00#ibcon#enter sib2, iclass 23, count 2 2006.286.03:52:15.00#ibcon#flushed, iclass 23, count 2 2006.286.03:52:15.00#ibcon#about to write, iclass 23, count 2 2006.286.03:52:15.00#ibcon#wrote, iclass 23, count 2 2006.286.03:52:15.00#ibcon#about to read 3, iclass 23, count 2 2006.286.03:52:15.03#ibcon#read 3, iclass 23, count 2 2006.286.03:52:15.03#ibcon#about to read 4, iclass 23, count 2 2006.286.03:52:15.03#ibcon#read 4, iclass 23, count 2 2006.286.03:52:15.03#ibcon#about to read 5, iclass 23, count 2 2006.286.03:52:15.03#ibcon#read 5, iclass 23, count 2 2006.286.03:52:15.03#ibcon#about to read 6, iclass 23, count 2 2006.286.03:52:15.03#ibcon#read 6, iclass 23, count 2 2006.286.03:52:15.03#ibcon#end of sib2, iclass 23, count 2 2006.286.03:52:15.03#ibcon#*after write, iclass 23, count 2 2006.286.03:52:15.03#ibcon#*before return 0, iclass 23, count 2 2006.286.03:52:15.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:52:15.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:52:15.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.03:52:15.03#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:15.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:52:15.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:52:15.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:52:15.15#ibcon#enter wrdev, iclass 23, count 0 2006.286.03:52:15.15#ibcon#first serial, iclass 23, count 0 2006.286.03:52:15.15#ibcon#enter sib2, iclass 23, count 0 2006.286.03:52:15.15#ibcon#flushed, iclass 23, count 0 2006.286.03:52:15.15#ibcon#about to write, iclass 23, count 0 2006.286.03:52:15.15#ibcon#wrote, iclass 23, count 0 2006.286.03:52:15.15#ibcon#about to read 3, iclass 23, count 0 2006.286.03:52:15.17#ibcon#read 3, iclass 23, count 0 2006.286.03:52:15.17#ibcon#about to read 4, iclass 23, count 0 2006.286.03:52:15.17#ibcon#read 4, iclass 23, count 0 2006.286.03:52:15.17#ibcon#about to read 5, iclass 23, count 0 2006.286.03:52:15.17#ibcon#read 5, iclass 23, count 0 2006.286.03:52:15.17#ibcon#about to read 6, iclass 23, count 0 2006.286.03:52:15.17#ibcon#read 6, iclass 23, count 0 2006.286.03:52:15.17#ibcon#end of sib2, iclass 23, count 0 2006.286.03:52:15.17#ibcon#*mode == 0, iclass 23, count 0 2006.286.03:52:15.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.03:52:15.17#ibcon#[25=USB\r\n] 2006.286.03:52:15.17#ibcon#*before write, iclass 23, count 0 2006.286.03:52:15.17#ibcon#enter sib2, iclass 23, count 0 2006.286.03:52:15.17#ibcon#flushed, iclass 23, count 0 2006.286.03:52:15.17#ibcon#about to write, iclass 23, count 0 2006.286.03:52:15.17#ibcon#wrote, iclass 23, count 0 2006.286.03:52:15.17#ibcon#about to read 3, iclass 23, count 0 2006.286.03:52:15.20#ibcon#read 3, iclass 23, count 0 2006.286.03:52:15.20#ibcon#about to read 4, iclass 23, count 0 2006.286.03:52:15.20#ibcon#read 4, iclass 23, count 0 2006.286.03:52:15.20#ibcon#about to read 5, iclass 23, count 0 2006.286.03:52:15.20#ibcon#read 5, iclass 23, count 0 2006.286.03:52:15.20#ibcon#about to read 6, iclass 23, count 0 2006.286.03:52:15.20#ibcon#read 6, iclass 23, count 0 2006.286.03:52:15.20#ibcon#end of sib2, iclass 23, count 0 2006.286.03:52:15.20#ibcon#*after write, iclass 23, count 0 2006.286.03:52:15.20#ibcon#*before return 0, iclass 23, count 0 2006.286.03:52:15.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:52:15.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:52:15.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.03:52:15.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.03:52:15.20$vck44/valo=2,534.99 2006.286.03:52:15.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.03:52:15.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.03:52:15.20#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:15.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:52:15.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:52:15.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:52:15.20#ibcon#enter wrdev, iclass 25, count 0 2006.286.03:52:15.20#ibcon#first serial, iclass 25, count 0 2006.286.03:52:15.20#ibcon#enter sib2, iclass 25, count 0 2006.286.03:52:15.20#ibcon#flushed, iclass 25, count 0 2006.286.03:52:15.20#ibcon#about to write, iclass 25, count 0 2006.286.03:52:16.03#ibcon#wrote, iclass 25, count 0 2006.286.03:52:16.03#ibcon#about to read 3, iclass 25, count 0 2006.286.03:52:16.04#ibcon#read 3, iclass 25, count 0 2006.286.03:52:16.04#ibcon#about to read 4, iclass 25, count 0 2006.286.03:52:16.04#ibcon#read 4, iclass 25, count 0 2006.286.03:52:16.04#ibcon#about to read 5, iclass 25, count 0 2006.286.03:52:16.04#ibcon#read 5, iclass 25, count 0 2006.286.03:52:16.04#ibcon#about to read 6, iclass 25, count 0 2006.286.03:52:16.04#ibcon#read 6, iclass 25, count 0 2006.286.03:52:16.04#ibcon#end of sib2, iclass 25, count 0 2006.286.03:52:16.04#ibcon#*mode == 0, iclass 25, count 0 2006.286.03:52:16.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.03:52:16.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.03:52:16.04#ibcon#*before write, iclass 25, count 0 2006.286.03:52:16.04#ibcon#enter sib2, iclass 25, count 0 2006.286.03:52:16.04#ibcon#flushed, iclass 25, count 0 2006.286.03:52:16.04#ibcon#about to write, iclass 25, count 0 2006.286.03:52:16.04#ibcon#wrote, iclass 25, count 0 2006.286.03:52:16.04#ibcon#about to read 3, iclass 25, count 0 2006.286.03:52:16.08#ibcon#read 3, iclass 25, count 0 2006.286.03:52:16.08#ibcon#about to read 4, iclass 25, count 0 2006.286.03:52:16.08#ibcon#read 4, iclass 25, count 0 2006.286.03:52:16.08#ibcon#about to read 5, iclass 25, count 0 2006.286.03:52:16.08#ibcon#read 5, iclass 25, count 0 2006.286.03:52:16.08#ibcon#about to read 6, iclass 25, count 0 2006.286.03:52:16.08#ibcon#read 6, iclass 25, count 0 2006.286.03:52:16.08#ibcon#end of sib2, iclass 25, count 0 2006.286.03:52:16.08#ibcon#*after write, iclass 25, count 0 2006.286.03:52:16.08#ibcon#*before return 0, iclass 25, count 0 2006.286.03:52:16.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:52:16.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:52:16.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.03:52:16.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.03:52:16.08$vck44/va=2,6 2006.286.03:52:16.08#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.03:52:16.08#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.03:52:16.08#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:16.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:52:16.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:52:16.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:52:16.08#ibcon#enter wrdev, iclass 27, count 2 2006.286.03:52:16.08#ibcon#first serial, iclass 27, count 2 2006.286.03:52:16.08#ibcon#enter sib2, iclass 27, count 2 2006.286.03:52:16.08#ibcon#flushed, iclass 27, count 2 2006.286.03:52:16.08#ibcon#about to write, iclass 27, count 2 2006.286.03:52:16.08#ibcon#wrote, iclass 27, count 2 2006.286.03:52:16.08#ibcon#about to read 3, iclass 27, count 2 2006.286.03:52:16.10#ibcon#read 3, iclass 27, count 2 2006.286.03:52:16.10#ibcon#about to read 4, iclass 27, count 2 2006.286.03:52:16.10#ibcon#read 4, iclass 27, count 2 2006.286.03:52:16.10#ibcon#about to read 5, iclass 27, count 2 2006.286.03:52:16.10#ibcon#read 5, iclass 27, count 2 2006.286.03:52:16.10#ibcon#about to read 6, iclass 27, count 2 2006.286.03:52:16.10#ibcon#read 6, iclass 27, count 2 2006.286.03:52:16.10#ibcon#end of sib2, iclass 27, count 2 2006.286.03:52:16.10#ibcon#*mode == 0, iclass 27, count 2 2006.286.03:52:16.10#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.03:52:16.10#ibcon#[25=AT02-06\r\n] 2006.286.03:52:16.10#ibcon#*before write, iclass 27, count 2 2006.286.03:52:16.10#ibcon#enter sib2, iclass 27, count 2 2006.286.03:52:16.10#ibcon#flushed, iclass 27, count 2 2006.286.03:52:16.10#ibcon#about to write, iclass 27, count 2 2006.286.03:52:16.10#ibcon#wrote, iclass 27, count 2 2006.286.03:52:16.10#ibcon#about to read 3, iclass 27, count 2 2006.286.03:52:16.13#ibcon#read 3, iclass 27, count 2 2006.286.03:52:16.13#ibcon#about to read 4, iclass 27, count 2 2006.286.03:52:16.13#ibcon#read 4, iclass 27, count 2 2006.286.03:52:16.13#ibcon#about to read 5, iclass 27, count 2 2006.286.03:52:16.13#ibcon#read 5, iclass 27, count 2 2006.286.03:52:16.13#ibcon#about to read 6, iclass 27, count 2 2006.286.03:52:16.13#ibcon#read 6, iclass 27, count 2 2006.286.03:52:16.13#ibcon#end of sib2, iclass 27, count 2 2006.286.03:52:16.13#ibcon#*after write, iclass 27, count 2 2006.286.03:52:16.13#ibcon#*before return 0, iclass 27, count 2 2006.286.03:52:16.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:52:16.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:52:16.13#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.03:52:16.13#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:16.13#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:52:16.25#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:52:16.25#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:52:16.25#ibcon#enter wrdev, iclass 27, count 0 2006.286.03:52:16.25#ibcon#first serial, iclass 27, count 0 2006.286.03:52:16.25#ibcon#enter sib2, iclass 27, count 0 2006.286.03:52:16.25#ibcon#flushed, iclass 27, count 0 2006.286.03:52:16.25#ibcon#about to write, iclass 27, count 0 2006.286.03:52:16.25#ibcon#wrote, iclass 27, count 0 2006.286.03:52:16.25#ibcon#about to read 3, iclass 27, count 0 2006.286.03:52:16.27#ibcon#read 3, iclass 27, count 0 2006.286.03:52:16.27#ibcon#about to read 4, iclass 27, count 0 2006.286.03:52:16.27#ibcon#read 4, iclass 27, count 0 2006.286.03:52:16.27#ibcon#about to read 5, iclass 27, count 0 2006.286.03:52:16.27#ibcon#read 5, iclass 27, count 0 2006.286.03:52:16.27#ibcon#about to read 6, iclass 27, count 0 2006.286.03:52:16.27#ibcon#read 6, iclass 27, count 0 2006.286.03:52:16.27#ibcon#end of sib2, iclass 27, count 0 2006.286.03:52:16.27#ibcon#*mode == 0, iclass 27, count 0 2006.286.03:52:16.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.03:52:16.27#ibcon#[25=USB\r\n] 2006.286.03:52:16.27#ibcon#*before write, iclass 27, count 0 2006.286.03:52:16.27#ibcon#enter sib2, iclass 27, count 0 2006.286.03:52:16.27#ibcon#flushed, iclass 27, count 0 2006.286.03:52:16.27#ibcon#about to write, iclass 27, count 0 2006.286.03:52:16.27#ibcon#wrote, iclass 27, count 0 2006.286.03:52:16.27#ibcon#about to read 3, iclass 27, count 0 2006.286.03:52:16.30#ibcon#read 3, iclass 27, count 0 2006.286.03:52:16.30#ibcon#about to read 4, iclass 27, count 0 2006.286.03:52:16.30#ibcon#read 4, iclass 27, count 0 2006.286.03:52:16.30#ibcon#about to read 5, iclass 27, count 0 2006.286.03:52:16.30#ibcon#read 5, iclass 27, count 0 2006.286.03:52:16.30#ibcon#about to read 6, iclass 27, count 0 2006.286.03:52:16.30#ibcon#read 6, iclass 27, count 0 2006.286.03:52:16.30#ibcon#end of sib2, iclass 27, count 0 2006.286.03:52:16.30#ibcon#*after write, iclass 27, count 0 2006.286.03:52:16.30#ibcon#*before return 0, iclass 27, count 0 2006.286.03:52:16.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:52:16.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:52:16.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.03:52:16.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.03:52:16.30$vck44/valo=3,564.99 2006.286.03:52:16.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.03:52:16.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.03:52:16.30#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:16.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:52:16.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:52:16.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:52:16.30#ibcon#enter wrdev, iclass 29, count 0 2006.286.03:52:16.30#ibcon#first serial, iclass 29, count 0 2006.286.03:52:16.30#ibcon#enter sib2, iclass 29, count 0 2006.286.03:52:16.30#ibcon#flushed, iclass 29, count 0 2006.286.03:52:16.30#ibcon#about to write, iclass 29, count 0 2006.286.03:52:16.30#ibcon#wrote, iclass 29, count 0 2006.286.03:52:16.30#ibcon#about to read 3, iclass 29, count 0 2006.286.03:52:16.32#ibcon#read 3, iclass 29, count 0 2006.286.03:52:16.39#ibcon#about to read 4, iclass 29, count 0 2006.286.03:52:16.39#ibcon#read 4, iclass 29, count 0 2006.286.03:52:16.39#ibcon#about to read 5, iclass 29, count 0 2006.286.03:52:16.39#ibcon#read 5, iclass 29, count 0 2006.286.03:52:16.39#ibcon#about to read 6, iclass 29, count 0 2006.286.03:52:16.39#ibcon#read 6, iclass 29, count 0 2006.286.03:52:16.39#ibcon#end of sib2, iclass 29, count 0 2006.286.03:52:16.39#ibcon#*mode == 0, iclass 29, count 0 2006.286.03:52:16.39#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.03:52:16.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.03:52:16.39#ibcon#*before write, iclass 29, count 0 2006.286.03:52:16.39#ibcon#enter sib2, iclass 29, count 0 2006.286.03:52:16.39#ibcon#flushed, iclass 29, count 0 2006.286.03:52:16.39#ibcon#about to write, iclass 29, count 0 2006.286.03:52:16.39#ibcon#wrote, iclass 29, count 0 2006.286.03:52:16.39#ibcon#about to read 3, iclass 29, count 0 2006.286.03:52:16.43#ibcon#read 3, iclass 29, count 0 2006.286.03:52:16.43#ibcon#about to read 4, iclass 29, count 0 2006.286.03:52:16.43#ibcon#read 4, iclass 29, count 0 2006.286.03:52:16.43#ibcon#about to read 5, iclass 29, count 0 2006.286.03:52:16.43#ibcon#read 5, iclass 29, count 0 2006.286.03:52:16.43#ibcon#about to read 6, iclass 29, count 0 2006.286.03:52:16.43#ibcon#read 6, iclass 29, count 0 2006.286.03:52:16.43#ibcon#end of sib2, iclass 29, count 0 2006.286.03:52:16.43#ibcon#*after write, iclass 29, count 0 2006.286.03:52:16.43#ibcon#*before return 0, iclass 29, count 0 2006.286.03:52:16.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:52:16.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:52:16.43#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.03:52:16.43#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.03:52:16.43$vck44/va=3,7 2006.286.03:52:16.43#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.03:52:16.43#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.03:52:16.43#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:16.43#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:52:16.43#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:52:16.43#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:52:16.43#ibcon#enter wrdev, iclass 31, count 2 2006.286.03:52:16.43#ibcon#first serial, iclass 31, count 2 2006.286.03:52:16.43#ibcon#enter sib2, iclass 31, count 2 2006.286.03:52:16.43#ibcon#flushed, iclass 31, count 2 2006.286.03:52:16.43#ibcon#about to write, iclass 31, count 2 2006.286.03:52:16.43#ibcon#wrote, iclass 31, count 2 2006.286.03:52:16.43#ibcon#about to read 3, iclass 31, count 2 2006.286.03:52:16.45#ibcon#read 3, iclass 31, count 2 2006.286.03:52:16.45#ibcon#about to read 4, iclass 31, count 2 2006.286.03:52:16.45#ibcon#read 4, iclass 31, count 2 2006.286.03:52:16.45#ibcon#about to read 5, iclass 31, count 2 2006.286.03:52:16.45#ibcon#read 5, iclass 31, count 2 2006.286.03:52:16.45#ibcon#about to read 6, iclass 31, count 2 2006.286.03:52:16.45#ibcon#read 6, iclass 31, count 2 2006.286.03:52:16.45#ibcon#end of sib2, iclass 31, count 2 2006.286.03:52:16.45#ibcon#*mode == 0, iclass 31, count 2 2006.286.03:52:16.45#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.03:52:16.45#ibcon#[25=AT03-07\r\n] 2006.286.03:52:16.45#ibcon#*before write, iclass 31, count 2 2006.286.03:52:16.45#ibcon#enter sib2, iclass 31, count 2 2006.286.03:52:16.45#ibcon#flushed, iclass 31, count 2 2006.286.03:52:16.45#ibcon#about to write, iclass 31, count 2 2006.286.03:52:16.45#ibcon#wrote, iclass 31, count 2 2006.286.03:52:16.45#ibcon#about to read 3, iclass 31, count 2 2006.286.03:52:16.48#ibcon#read 3, iclass 31, count 2 2006.286.03:52:16.48#ibcon#about to read 4, iclass 31, count 2 2006.286.03:52:16.48#ibcon#read 4, iclass 31, count 2 2006.286.03:52:16.48#ibcon#about to read 5, iclass 31, count 2 2006.286.03:52:16.48#ibcon#read 5, iclass 31, count 2 2006.286.03:52:16.48#ibcon#about to read 6, iclass 31, count 2 2006.286.03:52:16.48#ibcon#read 6, iclass 31, count 2 2006.286.03:52:16.48#ibcon#end of sib2, iclass 31, count 2 2006.286.03:52:16.48#ibcon#*after write, iclass 31, count 2 2006.286.03:52:16.48#ibcon#*before return 0, iclass 31, count 2 2006.286.03:52:16.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:52:16.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:52:16.48#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.03:52:16.48#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:16.48#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:52:16.60#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:52:16.60#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:52:16.60#ibcon#enter wrdev, iclass 31, count 0 2006.286.03:52:16.60#ibcon#first serial, iclass 31, count 0 2006.286.03:52:16.60#ibcon#enter sib2, iclass 31, count 0 2006.286.03:52:16.60#ibcon#flushed, iclass 31, count 0 2006.286.03:52:16.60#ibcon#about to write, iclass 31, count 0 2006.286.03:52:16.60#ibcon#wrote, iclass 31, count 0 2006.286.03:52:16.60#ibcon#about to read 3, iclass 31, count 0 2006.286.03:52:16.62#ibcon#read 3, iclass 31, count 0 2006.286.03:52:16.62#ibcon#about to read 4, iclass 31, count 0 2006.286.03:52:16.62#ibcon#read 4, iclass 31, count 0 2006.286.03:52:16.62#ibcon#about to read 5, iclass 31, count 0 2006.286.03:52:16.62#ibcon#read 5, iclass 31, count 0 2006.286.03:52:16.62#ibcon#about to read 6, iclass 31, count 0 2006.286.03:52:16.62#ibcon#read 6, iclass 31, count 0 2006.286.03:52:16.62#ibcon#end of sib2, iclass 31, count 0 2006.286.03:52:16.62#ibcon#*mode == 0, iclass 31, count 0 2006.286.03:52:16.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.03:52:16.62#ibcon#[25=USB\r\n] 2006.286.03:52:16.62#ibcon#*before write, iclass 31, count 0 2006.286.03:52:16.62#ibcon#enter sib2, iclass 31, count 0 2006.286.03:52:16.62#ibcon#flushed, iclass 31, count 0 2006.286.03:52:16.62#ibcon#about to write, iclass 31, count 0 2006.286.03:52:16.62#ibcon#wrote, iclass 31, count 0 2006.286.03:52:16.62#ibcon#about to read 3, iclass 31, count 0 2006.286.03:52:16.65#ibcon#read 3, iclass 31, count 0 2006.286.03:52:16.65#ibcon#about to read 4, iclass 31, count 0 2006.286.03:52:16.65#ibcon#read 4, iclass 31, count 0 2006.286.03:52:16.65#ibcon#about to read 5, iclass 31, count 0 2006.286.03:52:16.65#ibcon#read 5, iclass 31, count 0 2006.286.03:52:16.65#ibcon#about to read 6, iclass 31, count 0 2006.286.03:52:16.65#ibcon#read 6, iclass 31, count 0 2006.286.03:52:16.65#ibcon#end of sib2, iclass 31, count 0 2006.286.03:52:16.65#ibcon#*after write, iclass 31, count 0 2006.286.03:52:16.65#ibcon#*before return 0, iclass 31, count 0 2006.286.03:52:16.65#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:52:16.65#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:52:16.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.03:52:16.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.03:52:16.65$vck44/valo=4,624.99 2006.286.03:52:16.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.03:52:16.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.03:52:16.65#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:16.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:52:16.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:52:16.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:52:16.65#ibcon#enter wrdev, iclass 33, count 0 2006.286.03:52:16.65#ibcon#first serial, iclass 33, count 0 2006.286.03:52:16.65#ibcon#enter sib2, iclass 33, count 0 2006.286.03:52:16.65#ibcon#flushed, iclass 33, count 0 2006.286.03:52:16.65#ibcon#about to write, iclass 33, count 0 2006.286.03:52:16.65#ibcon#wrote, iclass 33, count 0 2006.286.03:52:16.65#ibcon#about to read 3, iclass 33, count 0 2006.286.03:52:16.67#ibcon#read 3, iclass 33, count 0 2006.286.03:52:16.67#ibcon#about to read 4, iclass 33, count 0 2006.286.03:52:16.67#ibcon#read 4, iclass 33, count 0 2006.286.03:52:16.67#ibcon#about to read 5, iclass 33, count 0 2006.286.03:52:16.67#ibcon#read 5, iclass 33, count 0 2006.286.03:52:16.67#ibcon#about to read 6, iclass 33, count 0 2006.286.03:52:16.67#ibcon#read 6, iclass 33, count 0 2006.286.03:52:16.67#ibcon#end of sib2, iclass 33, count 0 2006.286.03:52:16.67#ibcon#*mode == 0, iclass 33, count 0 2006.286.03:52:16.67#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.03:52:16.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.03:52:16.67#ibcon#*before write, iclass 33, count 0 2006.286.03:52:16.67#ibcon#enter sib2, iclass 33, count 0 2006.286.03:52:16.67#ibcon#flushed, iclass 33, count 0 2006.286.03:52:16.67#ibcon#about to write, iclass 33, count 0 2006.286.03:52:16.67#ibcon#wrote, iclass 33, count 0 2006.286.03:52:16.67#ibcon#about to read 3, iclass 33, count 0 2006.286.03:52:16.71#ibcon#read 3, iclass 33, count 0 2006.286.03:52:16.71#ibcon#about to read 4, iclass 33, count 0 2006.286.03:52:16.71#ibcon#read 4, iclass 33, count 0 2006.286.03:52:16.71#ibcon#about to read 5, iclass 33, count 0 2006.286.03:52:16.71#ibcon#read 5, iclass 33, count 0 2006.286.03:52:16.71#ibcon#about to read 6, iclass 33, count 0 2006.286.03:52:16.71#ibcon#read 6, iclass 33, count 0 2006.286.03:52:16.71#ibcon#end of sib2, iclass 33, count 0 2006.286.03:52:16.71#ibcon#*after write, iclass 33, count 0 2006.286.03:52:16.71#ibcon#*before return 0, iclass 33, count 0 2006.286.03:52:16.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:52:16.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:52:16.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.03:52:16.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.03:52:16.71$vck44/va=4,6 2006.286.03:52:16.71#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.03:52:16.71#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.03:52:16.71#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:16.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:52:16.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:52:16.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:52:16.77#ibcon#enter wrdev, iclass 35, count 2 2006.286.03:52:16.77#ibcon#first serial, iclass 35, count 2 2006.286.03:52:16.77#ibcon#enter sib2, iclass 35, count 2 2006.286.03:52:16.77#ibcon#flushed, iclass 35, count 2 2006.286.03:52:16.77#ibcon#about to write, iclass 35, count 2 2006.286.03:52:16.77#ibcon#wrote, iclass 35, count 2 2006.286.03:52:16.77#ibcon#about to read 3, iclass 35, count 2 2006.286.03:52:16.79#ibcon#read 3, iclass 35, count 2 2006.286.03:52:16.79#ibcon#about to read 4, iclass 35, count 2 2006.286.03:52:16.79#ibcon#read 4, iclass 35, count 2 2006.286.03:52:16.79#ibcon#about to read 5, iclass 35, count 2 2006.286.03:52:16.79#ibcon#read 5, iclass 35, count 2 2006.286.03:52:16.79#ibcon#about to read 6, iclass 35, count 2 2006.286.03:52:16.79#ibcon#read 6, iclass 35, count 2 2006.286.03:52:16.79#ibcon#end of sib2, iclass 35, count 2 2006.286.03:52:16.79#ibcon#*mode == 0, iclass 35, count 2 2006.286.03:52:16.79#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.03:52:16.79#ibcon#[25=AT04-06\r\n] 2006.286.03:52:16.79#ibcon#*before write, iclass 35, count 2 2006.286.03:52:16.79#ibcon#enter sib2, iclass 35, count 2 2006.286.03:52:16.79#ibcon#flushed, iclass 35, count 2 2006.286.03:52:16.79#ibcon#about to write, iclass 35, count 2 2006.286.03:52:16.79#ibcon#wrote, iclass 35, count 2 2006.286.03:52:16.79#ibcon#about to read 3, iclass 35, count 2 2006.286.03:52:16.82#ibcon#read 3, iclass 35, count 2 2006.286.03:52:16.82#ibcon#about to read 4, iclass 35, count 2 2006.286.03:52:16.82#ibcon#read 4, iclass 35, count 2 2006.286.03:52:16.82#ibcon#about to read 5, iclass 35, count 2 2006.286.03:52:16.82#ibcon#read 5, iclass 35, count 2 2006.286.03:52:16.82#ibcon#about to read 6, iclass 35, count 2 2006.286.03:52:16.82#ibcon#read 6, iclass 35, count 2 2006.286.03:52:16.82#ibcon#end of sib2, iclass 35, count 2 2006.286.03:52:16.82#ibcon#*after write, iclass 35, count 2 2006.286.03:52:16.82#ibcon#*before return 0, iclass 35, count 2 2006.286.03:52:16.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:52:16.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:52:16.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.03:52:16.82#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:16.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:52:16.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:52:16.94#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:52:16.94#ibcon#enter wrdev, iclass 35, count 0 2006.286.03:52:16.94#ibcon#first serial, iclass 35, count 0 2006.286.03:52:16.94#ibcon#enter sib2, iclass 35, count 0 2006.286.03:52:16.94#ibcon#flushed, iclass 35, count 0 2006.286.03:52:16.94#ibcon#about to write, iclass 35, count 0 2006.286.03:52:16.94#ibcon#wrote, iclass 35, count 0 2006.286.03:52:16.94#ibcon#about to read 3, iclass 35, count 0 2006.286.03:52:16.96#ibcon#read 3, iclass 35, count 0 2006.286.03:52:16.96#ibcon#about to read 4, iclass 35, count 0 2006.286.03:52:16.96#ibcon#read 4, iclass 35, count 0 2006.286.03:52:16.96#ibcon#about to read 5, iclass 35, count 0 2006.286.03:52:16.96#ibcon#read 5, iclass 35, count 0 2006.286.03:52:16.96#ibcon#about to read 6, iclass 35, count 0 2006.286.03:52:16.96#ibcon#read 6, iclass 35, count 0 2006.286.03:52:16.96#ibcon#end of sib2, iclass 35, count 0 2006.286.03:52:16.96#ibcon#*mode == 0, iclass 35, count 0 2006.286.03:52:16.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.03:52:16.96#ibcon#[25=USB\r\n] 2006.286.03:52:16.96#ibcon#*before write, iclass 35, count 0 2006.286.03:52:16.96#ibcon#enter sib2, iclass 35, count 0 2006.286.03:52:16.96#ibcon#flushed, iclass 35, count 0 2006.286.03:52:16.96#ibcon#about to write, iclass 35, count 0 2006.286.03:52:16.96#ibcon#wrote, iclass 35, count 0 2006.286.03:52:16.96#ibcon#about to read 3, iclass 35, count 0 2006.286.03:52:16.99#ibcon#read 3, iclass 35, count 0 2006.286.03:52:16.99#ibcon#about to read 4, iclass 35, count 0 2006.286.03:52:16.99#ibcon#read 4, iclass 35, count 0 2006.286.03:52:16.99#ibcon#about to read 5, iclass 35, count 0 2006.286.03:52:16.99#ibcon#read 5, iclass 35, count 0 2006.286.03:52:16.99#ibcon#about to read 6, iclass 35, count 0 2006.286.03:52:16.99#ibcon#read 6, iclass 35, count 0 2006.286.03:52:16.99#ibcon#end of sib2, iclass 35, count 0 2006.286.03:52:16.99#ibcon#*after write, iclass 35, count 0 2006.286.03:52:16.99#ibcon#*before return 0, iclass 35, count 0 2006.286.03:52:16.99#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:52:16.99#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:52:16.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.03:52:16.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.03:52:16.99$vck44/valo=5,734.99 2006.286.03:52:16.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.03:52:16.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.03:52:16.99#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:16.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:52:16.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:52:16.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:52:16.99#ibcon#enter wrdev, iclass 37, count 0 2006.286.03:52:16.99#ibcon#first serial, iclass 37, count 0 2006.286.03:52:16.99#ibcon#enter sib2, iclass 37, count 0 2006.286.03:52:16.99#ibcon#flushed, iclass 37, count 0 2006.286.03:52:16.99#ibcon#about to write, iclass 37, count 0 2006.286.03:52:16.99#ibcon#wrote, iclass 37, count 0 2006.286.03:52:16.99#ibcon#about to read 3, iclass 37, count 0 2006.286.03:52:17.01#ibcon#read 3, iclass 37, count 0 2006.286.03:52:17.01#ibcon#about to read 4, iclass 37, count 0 2006.286.03:52:17.01#ibcon#read 4, iclass 37, count 0 2006.286.03:52:17.01#ibcon#about to read 5, iclass 37, count 0 2006.286.03:52:17.01#ibcon#read 5, iclass 37, count 0 2006.286.03:52:17.01#ibcon#about to read 6, iclass 37, count 0 2006.286.03:52:17.01#ibcon#read 6, iclass 37, count 0 2006.286.03:52:17.01#ibcon#end of sib2, iclass 37, count 0 2006.286.03:52:17.01#ibcon#*mode == 0, iclass 37, count 0 2006.286.03:52:17.01#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.03:52:17.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.03:52:17.01#ibcon#*before write, iclass 37, count 0 2006.286.03:52:17.01#ibcon#enter sib2, iclass 37, count 0 2006.286.03:52:17.01#ibcon#flushed, iclass 37, count 0 2006.286.03:52:17.01#ibcon#about to write, iclass 37, count 0 2006.286.03:52:17.01#ibcon#wrote, iclass 37, count 0 2006.286.03:52:17.01#ibcon#about to read 3, iclass 37, count 0 2006.286.03:52:17.05#ibcon#read 3, iclass 37, count 0 2006.286.03:52:17.05#ibcon#about to read 4, iclass 37, count 0 2006.286.03:52:17.05#ibcon#read 4, iclass 37, count 0 2006.286.03:52:17.05#ibcon#about to read 5, iclass 37, count 0 2006.286.03:52:17.05#ibcon#read 5, iclass 37, count 0 2006.286.03:52:17.05#ibcon#about to read 6, iclass 37, count 0 2006.286.03:52:17.05#ibcon#read 6, iclass 37, count 0 2006.286.03:52:17.05#ibcon#end of sib2, iclass 37, count 0 2006.286.03:52:17.05#ibcon#*after write, iclass 37, count 0 2006.286.03:52:17.05#ibcon#*before return 0, iclass 37, count 0 2006.286.03:52:17.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:52:17.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:52:17.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.03:52:17.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.03:52:17.05$vck44/va=5,3 2006.286.03:52:17.05#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.03:52:17.05#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.03:52:17.05#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:17.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:52:17.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:52:17.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:52:17.11#ibcon#enter wrdev, iclass 39, count 2 2006.286.03:52:17.11#ibcon#first serial, iclass 39, count 2 2006.286.03:52:17.11#ibcon#enter sib2, iclass 39, count 2 2006.286.03:52:17.11#ibcon#flushed, iclass 39, count 2 2006.286.03:52:17.11#ibcon#about to write, iclass 39, count 2 2006.286.03:52:17.11#ibcon#wrote, iclass 39, count 2 2006.286.03:52:17.11#ibcon#about to read 3, iclass 39, count 2 2006.286.03:52:17.13#ibcon#read 3, iclass 39, count 2 2006.286.03:52:17.13#ibcon#about to read 4, iclass 39, count 2 2006.286.03:52:17.13#ibcon#read 4, iclass 39, count 2 2006.286.03:52:17.13#ibcon#about to read 5, iclass 39, count 2 2006.286.03:52:17.13#ibcon#read 5, iclass 39, count 2 2006.286.03:52:17.13#ibcon#about to read 6, iclass 39, count 2 2006.286.03:52:17.13#ibcon#read 6, iclass 39, count 2 2006.286.03:52:17.13#ibcon#end of sib2, iclass 39, count 2 2006.286.03:52:17.13#ibcon#*mode == 0, iclass 39, count 2 2006.286.03:52:17.13#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.03:52:17.13#ibcon#[25=AT05-03\r\n] 2006.286.03:52:17.13#ibcon#*before write, iclass 39, count 2 2006.286.03:52:17.13#ibcon#enter sib2, iclass 39, count 2 2006.286.03:52:17.13#ibcon#flushed, iclass 39, count 2 2006.286.03:52:17.13#ibcon#about to write, iclass 39, count 2 2006.286.03:52:17.13#ibcon#wrote, iclass 39, count 2 2006.286.03:52:17.13#ibcon#about to read 3, iclass 39, count 2 2006.286.03:52:17.16#ibcon#read 3, iclass 39, count 2 2006.286.03:52:17.16#ibcon#about to read 4, iclass 39, count 2 2006.286.03:52:17.16#ibcon#read 4, iclass 39, count 2 2006.286.03:52:17.16#ibcon#about to read 5, iclass 39, count 2 2006.286.03:52:17.16#ibcon#read 5, iclass 39, count 2 2006.286.03:52:17.16#ibcon#about to read 6, iclass 39, count 2 2006.286.03:52:17.16#ibcon#read 6, iclass 39, count 2 2006.286.03:52:17.16#ibcon#end of sib2, iclass 39, count 2 2006.286.03:52:17.16#ibcon#*after write, iclass 39, count 2 2006.286.03:52:17.16#ibcon#*before return 0, iclass 39, count 2 2006.286.03:52:17.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:52:17.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:52:17.16#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.03:52:17.16#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:17.16#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:52:17.28#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:52:17.28#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:52:17.28#ibcon#enter wrdev, iclass 39, count 0 2006.286.03:52:17.28#ibcon#first serial, iclass 39, count 0 2006.286.03:52:17.28#ibcon#enter sib2, iclass 39, count 0 2006.286.03:52:17.28#ibcon#flushed, iclass 39, count 0 2006.286.03:52:17.28#ibcon#about to write, iclass 39, count 0 2006.286.03:52:17.28#ibcon#wrote, iclass 39, count 0 2006.286.03:52:17.28#ibcon#about to read 3, iclass 39, count 0 2006.286.03:52:17.30#ibcon#read 3, iclass 39, count 0 2006.286.03:52:17.30#ibcon#about to read 4, iclass 39, count 0 2006.286.03:52:17.30#ibcon#read 4, iclass 39, count 0 2006.286.03:52:17.30#ibcon#about to read 5, iclass 39, count 0 2006.286.03:52:17.30#ibcon#read 5, iclass 39, count 0 2006.286.03:52:17.30#ibcon#about to read 6, iclass 39, count 0 2006.286.03:52:17.30#ibcon#read 6, iclass 39, count 0 2006.286.03:52:17.30#ibcon#end of sib2, iclass 39, count 0 2006.286.03:52:17.30#ibcon#*mode == 0, iclass 39, count 0 2006.286.03:52:17.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.03:52:17.30#ibcon#[25=USB\r\n] 2006.286.03:52:17.30#ibcon#*before write, iclass 39, count 0 2006.286.03:52:17.30#ibcon#enter sib2, iclass 39, count 0 2006.286.03:52:17.30#ibcon#flushed, iclass 39, count 0 2006.286.03:52:17.30#ibcon#about to write, iclass 39, count 0 2006.286.03:52:17.30#ibcon#wrote, iclass 39, count 0 2006.286.03:52:17.30#ibcon#about to read 3, iclass 39, count 0 2006.286.03:52:17.33#ibcon#read 3, iclass 39, count 0 2006.286.03:52:17.33#ibcon#about to read 4, iclass 39, count 0 2006.286.03:52:17.33#ibcon#read 4, iclass 39, count 0 2006.286.03:52:17.33#ibcon#about to read 5, iclass 39, count 0 2006.286.03:52:17.33#ibcon#read 5, iclass 39, count 0 2006.286.03:52:17.33#ibcon#about to read 6, iclass 39, count 0 2006.286.03:52:17.33#ibcon#read 6, iclass 39, count 0 2006.286.03:52:17.33#ibcon#end of sib2, iclass 39, count 0 2006.286.03:52:17.33#ibcon#*after write, iclass 39, count 0 2006.286.03:52:17.33#ibcon#*before return 0, iclass 39, count 0 2006.286.03:52:17.33#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:52:17.33#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:52:17.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.03:52:17.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.03:52:17.33$vck44/valo=6,814.99 2006.286.03:52:17.35#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.03:52:17.35#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.03:52:17.35#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:17.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:52:17.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:52:17.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:52:17.35#ibcon#enter wrdev, iclass 3, count 0 2006.286.03:52:17.35#ibcon#first serial, iclass 3, count 0 2006.286.03:52:17.35#ibcon#enter sib2, iclass 3, count 0 2006.286.03:52:17.35#ibcon#flushed, iclass 3, count 0 2006.286.03:52:17.35#ibcon#about to write, iclass 3, count 0 2006.286.03:52:17.35#ibcon#wrote, iclass 3, count 0 2006.286.03:52:17.35#ibcon#about to read 3, iclass 3, count 0 2006.286.03:52:17.36#ibcon#read 3, iclass 3, count 0 2006.286.03:52:17.36#ibcon#about to read 4, iclass 3, count 0 2006.286.03:52:17.36#ibcon#read 4, iclass 3, count 0 2006.286.03:52:17.36#ibcon#about to read 5, iclass 3, count 0 2006.286.03:52:17.36#ibcon#read 5, iclass 3, count 0 2006.286.03:52:17.36#ibcon#about to read 6, iclass 3, count 0 2006.286.03:52:17.36#ibcon#read 6, iclass 3, count 0 2006.286.03:52:17.36#ibcon#end of sib2, iclass 3, count 0 2006.286.03:52:17.36#ibcon#*mode == 0, iclass 3, count 0 2006.286.03:52:17.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.03:52:17.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.03:52:17.36#ibcon#*before write, iclass 3, count 0 2006.286.03:52:17.36#ibcon#enter sib2, iclass 3, count 0 2006.286.03:52:17.36#ibcon#flushed, iclass 3, count 0 2006.286.03:52:17.36#ibcon#about to write, iclass 3, count 0 2006.286.03:52:17.36#ibcon#wrote, iclass 3, count 0 2006.286.03:52:17.36#ibcon#about to read 3, iclass 3, count 0 2006.286.03:52:17.40#ibcon#read 3, iclass 3, count 0 2006.286.03:52:17.40#ibcon#about to read 4, iclass 3, count 0 2006.286.03:52:17.40#ibcon#read 4, iclass 3, count 0 2006.286.03:52:17.40#ibcon#about to read 5, iclass 3, count 0 2006.286.03:52:17.40#ibcon#read 5, iclass 3, count 0 2006.286.03:52:17.40#ibcon#about to read 6, iclass 3, count 0 2006.286.03:52:17.40#ibcon#read 6, iclass 3, count 0 2006.286.03:52:17.40#ibcon#end of sib2, iclass 3, count 0 2006.286.03:52:17.40#ibcon#*after write, iclass 3, count 0 2006.286.03:52:17.40#ibcon#*before return 0, iclass 3, count 0 2006.286.03:52:17.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:52:17.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:52:17.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.03:52:17.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.03:52:17.40$vck44/va=6,4 2006.286.03:52:17.40#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.03:52:17.40#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.03:52:17.40#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:17.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:52:17.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:52:17.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:52:17.45#ibcon#enter wrdev, iclass 5, count 2 2006.286.03:52:17.45#ibcon#first serial, iclass 5, count 2 2006.286.03:52:17.45#ibcon#enter sib2, iclass 5, count 2 2006.286.03:52:17.45#ibcon#flushed, iclass 5, count 2 2006.286.03:52:17.45#ibcon#about to write, iclass 5, count 2 2006.286.03:52:17.45#ibcon#wrote, iclass 5, count 2 2006.286.03:52:17.45#ibcon#about to read 3, iclass 5, count 2 2006.286.03:52:17.47#ibcon#read 3, iclass 5, count 2 2006.286.03:52:17.47#ibcon#about to read 4, iclass 5, count 2 2006.286.03:52:17.47#ibcon#read 4, iclass 5, count 2 2006.286.03:52:17.47#ibcon#about to read 5, iclass 5, count 2 2006.286.03:52:17.47#ibcon#read 5, iclass 5, count 2 2006.286.03:52:17.47#ibcon#about to read 6, iclass 5, count 2 2006.286.03:52:17.47#ibcon#read 6, iclass 5, count 2 2006.286.03:52:17.47#ibcon#end of sib2, iclass 5, count 2 2006.286.03:52:17.47#ibcon#*mode == 0, iclass 5, count 2 2006.286.03:52:17.47#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.03:52:17.47#ibcon#[25=AT06-04\r\n] 2006.286.03:52:17.47#ibcon#*before write, iclass 5, count 2 2006.286.03:52:17.47#ibcon#enter sib2, iclass 5, count 2 2006.286.03:52:17.47#ibcon#flushed, iclass 5, count 2 2006.286.03:52:17.47#ibcon#about to write, iclass 5, count 2 2006.286.03:52:17.47#ibcon#wrote, iclass 5, count 2 2006.286.03:52:17.47#ibcon#about to read 3, iclass 5, count 2 2006.286.03:52:17.50#ibcon#read 3, iclass 5, count 2 2006.286.03:52:17.50#ibcon#about to read 4, iclass 5, count 2 2006.286.03:52:17.50#ibcon#read 4, iclass 5, count 2 2006.286.03:52:17.50#ibcon#about to read 5, iclass 5, count 2 2006.286.03:52:17.50#ibcon#read 5, iclass 5, count 2 2006.286.03:52:17.50#ibcon#about to read 6, iclass 5, count 2 2006.286.03:52:17.50#ibcon#read 6, iclass 5, count 2 2006.286.03:52:17.50#ibcon#end of sib2, iclass 5, count 2 2006.286.03:52:17.50#ibcon#*after write, iclass 5, count 2 2006.286.03:52:17.50#ibcon#*before return 0, iclass 5, count 2 2006.286.03:52:17.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:52:17.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:52:17.50#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.03:52:17.50#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:17.50#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:52:17.62#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:52:17.62#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:52:17.62#ibcon#enter wrdev, iclass 5, count 0 2006.286.03:52:17.62#ibcon#first serial, iclass 5, count 0 2006.286.03:52:17.62#ibcon#enter sib2, iclass 5, count 0 2006.286.03:52:17.62#ibcon#flushed, iclass 5, count 0 2006.286.03:52:17.62#ibcon#about to write, iclass 5, count 0 2006.286.03:52:17.62#ibcon#wrote, iclass 5, count 0 2006.286.03:52:17.62#ibcon#about to read 3, iclass 5, count 0 2006.286.03:52:17.64#ibcon#read 3, iclass 5, count 0 2006.286.03:52:17.64#ibcon#about to read 4, iclass 5, count 0 2006.286.03:52:17.64#ibcon#read 4, iclass 5, count 0 2006.286.03:52:17.64#ibcon#about to read 5, iclass 5, count 0 2006.286.03:52:17.64#ibcon#read 5, iclass 5, count 0 2006.286.03:52:17.64#ibcon#about to read 6, iclass 5, count 0 2006.286.03:52:17.64#ibcon#read 6, iclass 5, count 0 2006.286.03:52:17.64#ibcon#end of sib2, iclass 5, count 0 2006.286.03:52:17.64#ibcon#*mode == 0, iclass 5, count 0 2006.286.03:52:17.64#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.03:52:17.64#ibcon#[25=USB\r\n] 2006.286.03:52:17.64#ibcon#*before write, iclass 5, count 0 2006.286.03:52:17.64#ibcon#enter sib2, iclass 5, count 0 2006.286.03:52:17.64#ibcon#flushed, iclass 5, count 0 2006.286.03:52:17.64#ibcon#about to write, iclass 5, count 0 2006.286.03:52:17.64#ibcon#wrote, iclass 5, count 0 2006.286.03:52:17.64#ibcon#about to read 3, iclass 5, count 0 2006.286.03:52:17.67#ibcon#read 3, iclass 5, count 0 2006.286.03:52:17.67#ibcon#about to read 4, iclass 5, count 0 2006.286.03:52:17.67#ibcon#read 4, iclass 5, count 0 2006.286.03:52:17.67#ibcon#about to read 5, iclass 5, count 0 2006.286.03:52:17.67#ibcon#read 5, iclass 5, count 0 2006.286.03:52:17.67#ibcon#about to read 6, iclass 5, count 0 2006.286.03:52:17.67#ibcon#read 6, iclass 5, count 0 2006.286.03:52:17.67#ibcon#end of sib2, iclass 5, count 0 2006.286.03:52:17.67#ibcon#*after write, iclass 5, count 0 2006.286.03:52:17.67#ibcon#*before return 0, iclass 5, count 0 2006.286.03:52:17.67#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:52:17.67#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:52:17.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.03:52:17.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.03:52:17.67$vck44/valo=7,864.99 2006.286.03:52:17.67#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.03:52:17.67#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.03:52:17.67#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:17.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:52:17.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:52:17.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:52:17.67#ibcon#enter wrdev, iclass 10, count 0 2006.286.03:52:17.67#ibcon#first serial, iclass 10, count 0 2006.286.03:52:17.67#ibcon#enter sib2, iclass 10, count 0 2006.286.03:52:17.67#ibcon#flushed, iclass 10, count 0 2006.286.03:52:17.67#ibcon#about to write, iclass 10, count 0 2006.286.03:52:17.67#ibcon#wrote, iclass 10, count 0 2006.286.03:52:17.67#ibcon#about to read 3, iclass 10, count 0 2006.286.03:52:17.69#ibcon#read 3, iclass 10, count 0 2006.286.03:52:17.69#ibcon#about to read 4, iclass 10, count 0 2006.286.03:52:17.69#ibcon#read 4, iclass 10, count 0 2006.286.03:52:17.69#ibcon#about to read 5, iclass 10, count 0 2006.286.03:52:17.69#ibcon#read 5, iclass 10, count 0 2006.286.03:52:17.69#ibcon#about to read 6, iclass 10, count 0 2006.286.03:52:17.69#ibcon#read 6, iclass 10, count 0 2006.286.03:52:17.69#ibcon#end of sib2, iclass 10, count 0 2006.286.03:52:17.69#ibcon#*mode == 0, iclass 10, count 0 2006.286.03:52:17.69#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.03:52:17.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.03:52:17.69#ibcon#*before write, iclass 10, count 0 2006.286.03:52:17.69#ibcon#enter sib2, iclass 10, count 0 2006.286.03:52:17.69#ibcon#flushed, iclass 10, count 0 2006.286.03:52:17.69#ibcon#about to write, iclass 10, count 0 2006.286.03:52:17.69#ibcon#wrote, iclass 10, count 0 2006.286.03:52:17.69#ibcon#about to read 3, iclass 10, count 0 2006.286.03:52:17.69#abcon#<5=/04 3.4 6.9 21.79 781015.0\r\n> 2006.286.03:52:17.71#abcon#{5=INTERFACE CLEAR} 2006.286.03:52:17.73#ibcon#read 3, iclass 10, count 0 2006.286.03:52:17.73#ibcon#about to read 4, iclass 10, count 0 2006.286.03:52:17.73#ibcon#read 4, iclass 10, count 0 2006.286.03:52:17.73#ibcon#about to read 5, iclass 10, count 0 2006.286.03:52:17.73#ibcon#read 5, iclass 10, count 0 2006.286.03:52:17.73#ibcon#about to read 6, iclass 10, count 0 2006.286.03:52:17.73#ibcon#read 6, iclass 10, count 0 2006.286.03:52:17.73#ibcon#end of sib2, iclass 10, count 0 2006.286.03:52:17.73#ibcon#*after write, iclass 10, count 0 2006.286.03:52:17.73#ibcon#*before return 0, iclass 10, count 0 2006.286.03:52:17.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:52:17.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:52:17.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.03:52:17.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.03:52:17.73$vck44/va=7,4 2006.286.03:52:17.73#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.03:52:17.73#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.03:52:17.73#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:17.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:52:17.77#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:52:17.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:52:17.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:52:17.79#ibcon#enter wrdev, iclass 14, count 2 2006.286.03:52:17.79#ibcon#first serial, iclass 14, count 2 2006.286.03:52:17.79#ibcon#enter sib2, iclass 14, count 2 2006.286.03:52:17.79#ibcon#flushed, iclass 14, count 2 2006.286.03:52:17.79#ibcon#about to write, iclass 14, count 2 2006.286.03:52:17.79#ibcon#wrote, iclass 14, count 2 2006.286.03:52:17.79#ibcon#about to read 3, iclass 14, count 2 2006.286.03:52:17.81#ibcon#read 3, iclass 14, count 2 2006.286.03:52:17.81#ibcon#about to read 4, iclass 14, count 2 2006.286.03:52:17.81#ibcon#read 4, iclass 14, count 2 2006.286.03:52:17.81#ibcon#about to read 5, iclass 14, count 2 2006.286.03:52:17.81#ibcon#read 5, iclass 14, count 2 2006.286.03:52:17.81#ibcon#about to read 6, iclass 14, count 2 2006.286.03:52:17.81#ibcon#read 6, iclass 14, count 2 2006.286.03:52:17.81#ibcon#end of sib2, iclass 14, count 2 2006.286.03:52:17.81#ibcon#*mode == 0, iclass 14, count 2 2006.286.03:52:17.81#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.03:52:17.81#ibcon#[25=AT07-04\r\n] 2006.286.03:52:17.81#ibcon#*before write, iclass 14, count 2 2006.286.03:52:17.81#ibcon#enter sib2, iclass 14, count 2 2006.286.03:52:17.81#ibcon#flushed, iclass 14, count 2 2006.286.03:52:17.81#ibcon#about to write, iclass 14, count 2 2006.286.03:52:17.81#ibcon#wrote, iclass 14, count 2 2006.286.03:52:17.81#ibcon#about to read 3, iclass 14, count 2 2006.286.03:52:17.84#ibcon#read 3, iclass 14, count 2 2006.286.03:52:17.84#ibcon#about to read 4, iclass 14, count 2 2006.286.03:52:17.84#ibcon#read 4, iclass 14, count 2 2006.286.03:52:17.84#ibcon#about to read 5, iclass 14, count 2 2006.286.03:52:17.84#ibcon#read 5, iclass 14, count 2 2006.286.03:52:17.84#ibcon#about to read 6, iclass 14, count 2 2006.286.03:52:17.84#ibcon#read 6, iclass 14, count 2 2006.286.03:52:17.84#ibcon#end of sib2, iclass 14, count 2 2006.286.03:52:17.84#ibcon#*after write, iclass 14, count 2 2006.286.03:52:17.84#ibcon#*before return 0, iclass 14, count 2 2006.286.03:52:17.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:52:17.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:52:17.84#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.03:52:17.84#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:17.84#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:52:17.96#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:52:17.96#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:52:17.96#ibcon#enter wrdev, iclass 14, count 0 2006.286.03:52:17.96#ibcon#first serial, iclass 14, count 0 2006.286.03:52:17.96#ibcon#enter sib2, iclass 14, count 0 2006.286.03:52:17.96#ibcon#flushed, iclass 14, count 0 2006.286.03:52:17.96#ibcon#about to write, iclass 14, count 0 2006.286.03:52:17.96#ibcon#wrote, iclass 14, count 0 2006.286.03:52:17.96#ibcon#about to read 3, iclass 14, count 0 2006.286.03:52:17.98#ibcon#read 3, iclass 14, count 0 2006.286.03:52:17.98#ibcon#about to read 4, iclass 14, count 0 2006.286.03:52:17.98#ibcon#read 4, iclass 14, count 0 2006.286.03:52:17.98#ibcon#about to read 5, iclass 14, count 0 2006.286.03:52:17.98#ibcon#read 5, iclass 14, count 0 2006.286.03:52:17.98#ibcon#about to read 6, iclass 14, count 0 2006.286.03:52:17.98#ibcon#read 6, iclass 14, count 0 2006.286.03:52:17.98#ibcon#end of sib2, iclass 14, count 0 2006.286.03:52:17.98#ibcon#*mode == 0, iclass 14, count 0 2006.286.03:52:17.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.03:52:17.98#ibcon#[25=USB\r\n] 2006.286.03:52:17.98#ibcon#*before write, iclass 14, count 0 2006.286.03:52:17.98#ibcon#enter sib2, iclass 14, count 0 2006.286.03:52:17.98#ibcon#flushed, iclass 14, count 0 2006.286.03:52:17.98#ibcon#about to write, iclass 14, count 0 2006.286.03:52:17.98#ibcon#wrote, iclass 14, count 0 2006.286.03:52:17.98#ibcon#about to read 3, iclass 14, count 0 2006.286.03:52:18.01#ibcon#read 3, iclass 14, count 0 2006.286.03:52:18.01#ibcon#about to read 4, iclass 14, count 0 2006.286.03:52:18.01#ibcon#read 4, iclass 14, count 0 2006.286.03:52:18.01#ibcon#about to read 5, iclass 14, count 0 2006.286.03:52:18.01#ibcon#read 5, iclass 14, count 0 2006.286.03:52:18.01#ibcon#about to read 6, iclass 14, count 0 2006.286.03:52:18.01#ibcon#read 6, iclass 14, count 0 2006.286.03:52:18.01#ibcon#end of sib2, iclass 14, count 0 2006.286.03:52:18.01#ibcon#*after write, iclass 14, count 0 2006.286.03:52:18.01#ibcon#*before return 0, iclass 14, count 0 2006.286.03:52:18.01#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:52:18.01#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:52:18.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.03:52:18.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.03:52:18.01$vck44/valo=8,884.99 2006.286.03:52:18.01#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.03:52:18.01#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.03:52:18.01#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:18.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:52:18.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:52:18.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:52:18.01#ibcon#enter wrdev, iclass 17, count 0 2006.286.03:52:18.01#ibcon#first serial, iclass 17, count 0 2006.286.03:52:18.01#ibcon#enter sib2, iclass 17, count 0 2006.286.03:52:18.01#ibcon#flushed, iclass 17, count 0 2006.286.03:52:18.01#ibcon#about to write, iclass 17, count 0 2006.286.03:52:18.01#ibcon#wrote, iclass 17, count 0 2006.286.03:52:18.01#ibcon#about to read 3, iclass 17, count 0 2006.286.03:52:18.03#ibcon#read 3, iclass 17, count 0 2006.286.03:52:18.03#ibcon#about to read 4, iclass 17, count 0 2006.286.03:52:18.03#ibcon#read 4, iclass 17, count 0 2006.286.03:52:18.03#ibcon#about to read 5, iclass 17, count 0 2006.286.03:52:18.03#ibcon#read 5, iclass 17, count 0 2006.286.03:52:18.03#ibcon#about to read 6, iclass 17, count 0 2006.286.03:52:18.03#ibcon#read 6, iclass 17, count 0 2006.286.03:52:18.03#ibcon#end of sib2, iclass 17, count 0 2006.286.03:52:18.03#ibcon#*mode == 0, iclass 17, count 0 2006.286.03:52:18.03#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.03:52:18.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.03:52:18.03#ibcon#*before write, iclass 17, count 0 2006.286.03:52:18.03#ibcon#enter sib2, iclass 17, count 0 2006.286.03:52:18.03#ibcon#flushed, iclass 17, count 0 2006.286.03:52:18.03#ibcon#about to write, iclass 17, count 0 2006.286.03:52:18.03#ibcon#wrote, iclass 17, count 0 2006.286.03:52:18.03#ibcon#about to read 3, iclass 17, count 0 2006.286.03:52:18.07#ibcon#read 3, iclass 17, count 0 2006.286.03:52:18.07#ibcon#about to read 4, iclass 17, count 0 2006.286.03:52:18.07#ibcon#read 4, iclass 17, count 0 2006.286.03:52:18.07#ibcon#about to read 5, iclass 17, count 0 2006.286.03:52:18.07#ibcon#read 5, iclass 17, count 0 2006.286.03:52:18.07#ibcon#about to read 6, iclass 17, count 0 2006.286.03:52:18.07#ibcon#read 6, iclass 17, count 0 2006.286.03:52:18.07#ibcon#end of sib2, iclass 17, count 0 2006.286.03:52:18.07#ibcon#*after write, iclass 17, count 0 2006.286.03:52:18.07#ibcon#*before return 0, iclass 17, count 0 2006.286.03:52:18.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:52:18.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:52:18.07#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.03:52:18.07#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.03:52:18.07$vck44/va=8,3 2006.286.03:52:18.07#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.03:52:18.07#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.03:52:18.07#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:18.07#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:52:18.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:52:18.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:52:18.13#ibcon#enter wrdev, iclass 19, count 2 2006.286.03:52:18.13#ibcon#first serial, iclass 19, count 2 2006.286.03:52:18.13#ibcon#enter sib2, iclass 19, count 2 2006.286.03:52:18.13#ibcon#flushed, iclass 19, count 2 2006.286.03:52:18.13#ibcon#about to write, iclass 19, count 2 2006.286.03:52:18.13#ibcon#wrote, iclass 19, count 2 2006.286.03:52:18.13#ibcon#about to read 3, iclass 19, count 2 2006.286.03:52:18.15#ibcon#read 3, iclass 19, count 2 2006.286.03:52:18.15#ibcon#about to read 4, iclass 19, count 2 2006.286.03:52:18.15#ibcon#read 4, iclass 19, count 2 2006.286.03:52:18.15#ibcon#about to read 5, iclass 19, count 2 2006.286.03:52:18.15#ibcon#read 5, iclass 19, count 2 2006.286.03:52:18.15#ibcon#about to read 6, iclass 19, count 2 2006.286.03:52:18.15#ibcon#read 6, iclass 19, count 2 2006.286.03:52:18.15#ibcon#end of sib2, iclass 19, count 2 2006.286.03:52:18.15#ibcon#*mode == 0, iclass 19, count 2 2006.286.03:52:18.15#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.03:52:18.15#ibcon#[25=AT08-03\r\n] 2006.286.03:52:18.15#ibcon#*before write, iclass 19, count 2 2006.286.03:52:18.15#ibcon#enter sib2, iclass 19, count 2 2006.286.03:52:18.15#ibcon#flushed, iclass 19, count 2 2006.286.03:52:18.15#ibcon#about to write, iclass 19, count 2 2006.286.03:52:18.15#ibcon#wrote, iclass 19, count 2 2006.286.03:52:18.15#ibcon#about to read 3, iclass 19, count 2 2006.286.03:52:18.18#ibcon#read 3, iclass 19, count 2 2006.286.03:52:18.18#ibcon#about to read 4, iclass 19, count 2 2006.286.03:52:18.18#ibcon#read 4, iclass 19, count 2 2006.286.03:52:18.18#ibcon#about to read 5, iclass 19, count 2 2006.286.03:52:18.18#ibcon#read 5, iclass 19, count 2 2006.286.03:52:18.18#ibcon#about to read 6, iclass 19, count 2 2006.286.03:52:18.18#ibcon#read 6, iclass 19, count 2 2006.286.03:52:18.18#ibcon#end of sib2, iclass 19, count 2 2006.286.03:52:18.18#ibcon#*after write, iclass 19, count 2 2006.286.03:52:18.18#ibcon#*before return 0, iclass 19, count 2 2006.286.03:52:18.18#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:52:18.18#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.03:52:18.18#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.03:52:18.18#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:18.18#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:52:18.30#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:52:18.30#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:52:18.30#ibcon#enter wrdev, iclass 19, count 0 2006.286.03:52:18.30#ibcon#first serial, iclass 19, count 0 2006.286.03:52:18.30#ibcon#enter sib2, iclass 19, count 0 2006.286.03:52:18.30#ibcon#flushed, iclass 19, count 0 2006.286.03:52:18.30#ibcon#about to write, iclass 19, count 0 2006.286.03:52:18.30#ibcon#wrote, iclass 19, count 0 2006.286.03:52:18.30#ibcon#about to read 3, iclass 19, count 0 2006.286.03:52:18.32#ibcon#read 3, iclass 19, count 0 2006.286.03:52:18.32#ibcon#about to read 4, iclass 19, count 0 2006.286.03:52:18.32#ibcon#read 4, iclass 19, count 0 2006.286.03:52:18.32#ibcon#about to read 5, iclass 19, count 0 2006.286.03:52:18.32#ibcon#read 5, iclass 19, count 0 2006.286.03:52:18.32#ibcon#about to read 6, iclass 19, count 0 2006.286.03:52:18.32#ibcon#read 6, iclass 19, count 0 2006.286.03:52:18.32#ibcon#end of sib2, iclass 19, count 0 2006.286.03:52:18.32#ibcon#*mode == 0, iclass 19, count 0 2006.286.03:52:18.32#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.03:52:18.32#ibcon#[25=USB\r\n] 2006.286.03:52:18.32#ibcon#*before write, iclass 19, count 0 2006.286.03:52:18.32#ibcon#enter sib2, iclass 19, count 0 2006.286.03:52:18.32#ibcon#flushed, iclass 19, count 0 2006.286.03:52:18.32#ibcon#about to write, iclass 19, count 0 2006.286.03:52:18.32#ibcon#wrote, iclass 19, count 0 2006.286.03:52:18.32#ibcon#about to read 3, iclass 19, count 0 2006.286.03:52:18.35#ibcon#read 3, iclass 19, count 0 2006.286.03:52:18.35#ibcon#about to read 4, iclass 19, count 0 2006.286.03:52:18.35#ibcon#read 4, iclass 19, count 0 2006.286.03:52:18.35#ibcon#about to read 5, iclass 19, count 0 2006.286.03:52:18.35#ibcon#read 5, iclass 19, count 0 2006.286.03:52:18.35#ibcon#about to read 6, iclass 19, count 0 2006.286.03:52:18.35#ibcon#read 6, iclass 19, count 0 2006.286.03:52:18.35#ibcon#end of sib2, iclass 19, count 0 2006.286.03:52:18.35#ibcon#*after write, iclass 19, count 0 2006.286.03:52:18.35#ibcon#*before return 0, iclass 19, count 0 2006.286.03:52:18.35#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:52:18.35#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.03:52:18.35#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.03:52:18.35#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.03:52:18.35$vck44/vblo=1,629.99 2006.286.03:52:18.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.03:52:18.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.03:52:18.49#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:18.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:52:18.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:52:18.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:52:18.49#ibcon#enter wrdev, iclass 21, count 0 2006.286.03:52:18.49#ibcon#first serial, iclass 21, count 0 2006.286.03:52:18.49#ibcon#enter sib2, iclass 21, count 0 2006.286.03:52:18.49#ibcon#flushed, iclass 21, count 0 2006.286.03:52:18.49#ibcon#about to write, iclass 21, count 0 2006.286.03:52:18.49#ibcon#wrote, iclass 21, count 0 2006.286.03:52:18.49#ibcon#about to read 3, iclass 21, count 0 2006.286.03:52:18.50#ibcon#read 3, iclass 21, count 0 2006.286.03:52:18.50#ibcon#about to read 4, iclass 21, count 0 2006.286.03:52:18.50#ibcon#read 4, iclass 21, count 0 2006.286.03:52:18.50#ibcon#about to read 5, iclass 21, count 0 2006.286.03:52:18.50#ibcon#read 5, iclass 21, count 0 2006.286.03:52:18.50#ibcon#about to read 6, iclass 21, count 0 2006.286.03:52:18.50#ibcon#read 6, iclass 21, count 0 2006.286.03:52:18.50#ibcon#end of sib2, iclass 21, count 0 2006.286.03:52:18.50#ibcon#*mode == 0, iclass 21, count 0 2006.286.03:52:18.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.03:52:18.50#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.03:52:18.50#ibcon#*before write, iclass 21, count 0 2006.286.03:52:18.50#ibcon#enter sib2, iclass 21, count 0 2006.286.03:52:18.50#ibcon#flushed, iclass 21, count 0 2006.286.03:52:18.50#ibcon#about to write, iclass 21, count 0 2006.286.03:52:18.50#ibcon#wrote, iclass 21, count 0 2006.286.03:52:18.50#ibcon#about to read 3, iclass 21, count 0 2006.286.03:52:18.54#ibcon#read 3, iclass 21, count 0 2006.286.03:52:18.54#ibcon#about to read 4, iclass 21, count 0 2006.286.03:52:18.54#ibcon#read 4, iclass 21, count 0 2006.286.03:52:18.54#ibcon#about to read 5, iclass 21, count 0 2006.286.03:52:18.54#ibcon#read 5, iclass 21, count 0 2006.286.03:52:18.54#ibcon#about to read 6, iclass 21, count 0 2006.286.03:52:18.54#ibcon#read 6, iclass 21, count 0 2006.286.03:52:18.54#ibcon#end of sib2, iclass 21, count 0 2006.286.03:52:18.54#ibcon#*after write, iclass 21, count 0 2006.286.03:52:18.54#ibcon#*before return 0, iclass 21, count 0 2006.286.03:52:18.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:52:18.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.03:52:18.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.03:52:18.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.03:52:18.54$vck44/vb=1,4 2006.286.03:52:18.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.03:52:18.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.03:52:18.54#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:18.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:52:18.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:52:18.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:52:18.54#ibcon#enter wrdev, iclass 23, count 2 2006.286.03:52:18.54#ibcon#first serial, iclass 23, count 2 2006.286.03:52:18.54#ibcon#enter sib2, iclass 23, count 2 2006.286.03:52:18.54#ibcon#flushed, iclass 23, count 2 2006.286.03:52:18.54#ibcon#about to write, iclass 23, count 2 2006.286.03:52:18.54#ibcon#wrote, iclass 23, count 2 2006.286.03:52:18.54#ibcon#about to read 3, iclass 23, count 2 2006.286.03:52:18.56#ibcon#read 3, iclass 23, count 2 2006.286.03:52:18.56#ibcon#about to read 4, iclass 23, count 2 2006.286.03:52:18.56#ibcon#read 4, iclass 23, count 2 2006.286.03:52:18.56#ibcon#about to read 5, iclass 23, count 2 2006.286.03:52:18.56#ibcon#read 5, iclass 23, count 2 2006.286.03:52:18.56#ibcon#about to read 6, iclass 23, count 2 2006.286.03:52:18.56#ibcon#read 6, iclass 23, count 2 2006.286.03:52:18.56#ibcon#end of sib2, iclass 23, count 2 2006.286.03:52:18.56#ibcon#*mode == 0, iclass 23, count 2 2006.286.03:52:18.56#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.03:52:18.56#ibcon#[27=AT01-04\r\n] 2006.286.03:52:18.56#ibcon#*before write, iclass 23, count 2 2006.286.03:52:18.56#ibcon#enter sib2, iclass 23, count 2 2006.286.03:52:18.56#ibcon#flushed, iclass 23, count 2 2006.286.03:52:18.56#ibcon#about to write, iclass 23, count 2 2006.286.03:52:18.56#ibcon#wrote, iclass 23, count 2 2006.286.03:52:18.56#ibcon#about to read 3, iclass 23, count 2 2006.286.03:52:18.59#ibcon#read 3, iclass 23, count 2 2006.286.03:52:18.59#ibcon#about to read 4, iclass 23, count 2 2006.286.03:52:18.59#ibcon#read 4, iclass 23, count 2 2006.286.03:52:18.59#ibcon#about to read 5, iclass 23, count 2 2006.286.03:52:18.59#ibcon#read 5, iclass 23, count 2 2006.286.03:52:18.59#ibcon#about to read 6, iclass 23, count 2 2006.286.03:52:18.59#ibcon#read 6, iclass 23, count 2 2006.286.03:52:18.59#ibcon#end of sib2, iclass 23, count 2 2006.286.03:52:18.59#ibcon#*after write, iclass 23, count 2 2006.286.03:52:18.59#ibcon#*before return 0, iclass 23, count 2 2006.286.03:52:18.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:52:18.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.03:52:18.59#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.03:52:18.59#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:18.59#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:52:18.71#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:52:18.71#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:52:18.71#ibcon#enter wrdev, iclass 23, count 0 2006.286.03:52:18.71#ibcon#first serial, iclass 23, count 0 2006.286.03:52:18.71#ibcon#enter sib2, iclass 23, count 0 2006.286.03:52:18.71#ibcon#flushed, iclass 23, count 0 2006.286.03:52:18.71#ibcon#about to write, iclass 23, count 0 2006.286.03:52:18.71#ibcon#wrote, iclass 23, count 0 2006.286.03:52:18.71#ibcon#about to read 3, iclass 23, count 0 2006.286.03:52:18.73#ibcon#read 3, iclass 23, count 0 2006.286.03:52:18.73#ibcon#about to read 4, iclass 23, count 0 2006.286.03:52:18.73#ibcon#read 4, iclass 23, count 0 2006.286.03:52:18.73#ibcon#about to read 5, iclass 23, count 0 2006.286.03:52:18.73#ibcon#read 5, iclass 23, count 0 2006.286.03:52:18.73#ibcon#about to read 6, iclass 23, count 0 2006.286.03:52:18.73#ibcon#read 6, iclass 23, count 0 2006.286.03:52:18.73#ibcon#end of sib2, iclass 23, count 0 2006.286.03:52:18.73#ibcon#*mode == 0, iclass 23, count 0 2006.286.03:52:18.73#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.03:52:18.73#ibcon#[27=USB\r\n] 2006.286.03:52:18.73#ibcon#*before write, iclass 23, count 0 2006.286.03:52:18.73#ibcon#enter sib2, iclass 23, count 0 2006.286.03:52:18.73#ibcon#flushed, iclass 23, count 0 2006.286.03:52:18.73#ibcon#about to write, iclass 23, count 0 2006.286.03:52:18.73#ibcon#wrote, iclass 23, count 0 2006.286.03:52:18.73#ibcon#about to read 3, iclass 23, count 0 2006.286.03:52:18.76#ibcon#read 3, iclass 23, count 0 2006.286.03:52:18.76#ibcon#about to read 4, iclass 23, count 0 2006.286.03:52:18.76#ibcon#read 4, iclass 23, count 0 2006.286.03:52:18.76#ibcon#about to read 5, iclass 23, count 0 2006.286.03:52:18.76#ibcon#read 5, iclass 23, count 0 2006.286.03:52:18.76#ibcon#about to read 6, iclass 23, count 0 2006.286.03:52:18.76#ibcon#read 6, iclass 23, count 0 2006.286.03:52:18.76#ibcon#end of sib2, iclass 23, count 0 2006.286.03:52:18.76#ibcon#*after write, iclass 23, count 0 2006.286.03:52:18.76#ibcon#*before return 0, iclass 23, count 0 2006.286.03:52:18.76#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:52:18.76#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.03:52:18.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.03:52:18.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.03:52:18.76$vck44/vblo=2,634.99 2006.286.03:52:18.76#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.03:52:18.76#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.03:52:18.76#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:18.76#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:52:18.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:52:18.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:52:18.76#ibcon#enter wrdev, iclass 25, count 0 2006.286.03:52:18.76#ibcon#first serial, iclass 25, count 0 2006.286.03:52:18.76#ibcon#enter sib2, iclass 25, count 0 2006.286.03:52:18.76#ibcon#flushed, iclass 25, count 0 2006.286.03:52:18.76#ibcon#about to write, iclass 25, count 0 2006.286.03:52:18.76#ibcon#wrote, iclass 25, count 0 2006.286.03:52:18.76#ibcon#about to read 3, iclass 25, count 0 2006.286.03:52:18.78#ibcon#read 3, iclass 25, count 0 2006.286.03:52:18.78#ibcon#about to read 4, iclass 25, count 0 2006.286.03:52:18.78#ibcon#read 4, iclass 25, count 0 2006.286.03:52:18.78#ibcon#about to read 5, iclass 25, count 0 2006.286.03:52:18.78#ibcon#read 5, iclass 25, count 0 2006.286.03:52:18.78#ibcon#about to read 6, iclass 25, count 0 2006.286.03:52:18.78#ibcon#read 6, iclass 25, count 0 2006.286.03:52:18.78#ibcon#end of sib2, iclass 25, count 0 2006.286.03:52:18.78#ibcon#*mode == 0, iclass 25, count 0 2006.286.03:52:18.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.03:52:18.78#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.03:52:18.78#ibcon#*before write, iclass 25, count 0 2006.286.03:52:18.78#ibcon#enter sib2, iclass 25, count 0 2006.286.03:52:18.78#ibcon#flushed, iclass 25, count 0 2006.286.03:52:18.78#ibcon#about to write, iclass 25, count 0 2006.286.03:52:18.78#ibcon#wrote, iclass 25, count 0 2006.286.03:52:18.78#ibcon#about to read 3, iclass 25, count 0 2006.286.03:52:18.82#ibcon#read 3, iclass 25, count 0 2006.286.03:52:18.82#ibcon#about to read 4, iclass 25, count 0 2006.286.03:52:18.82#ibcon#read 4, iclass 25, count 0 2006.286.03:52:18.82#ibcon#about to read 5, iclass 25, count 0 2006.286.03:52:18.82#ibcon#read 5, iclass 25, count 0 2006.286.03:52:18.82#ibcon#about to read 6, iclass 25, count 0 2006.286.03:52:18.82#ibcon#read 6, iclass 25, count 0 2006.286.03:52:18.82#ibcon#end of sib2, iclass 25, count 0 2006.286.03:52:18.82#ibcon#*after write, iclass 25, count 0 2006.286.03:52:18.82#ibcon#*before return 0, iclass 25, count 0 2006.286.03:52:18.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:52:18.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.03:52:18.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.03:52:18.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.03:52:18.82$vck44/vb=2,5 2006.286.03:52:18.82#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.03:52:18.82#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.03:52:18.82#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:18.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:52:18.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:52:18.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:52:18.88#ibcon#enter wrdev, iclass 27, count 2 2006.286.03:52:18.88#ibcon#first serial, iclass 27, count 2 2006.286.03:52:18.88#ibcon#enter sib2, iclass 27, count 2 2006.286.03:52:18.88#ibcon#flushed, iclass 27, count 2 2006.286.03:52:18.88#ibcon#about to write, iclass 27, count 2 2006.286.03:52:18.88#ibcon#wrote, iclass 27, count 2 2006.286.03:52:18.88#ibcon#about to read 3, iclass 27, count 2 2006.286.03:52:18.90#ibcon#read 3, iclass 27, count 2 2006.286.03:52:18.90#ibcon#about to read 4, iclass 27, count 2 2006.286.03:52:18.90#ibcon#read 4, iclass 27, count 2 2006.286.03:52:18.90#ibcon#about to read 5, iclass 27, count 2 2006.286.03:52:18.90#ibcon#read 5, iclass 27, count 2 2006.286.03:52:18.90#ibcon#about to read 6, iclass 27, count 2 2006.286.03:52:18.90#ibcon#read 6, iclass 27, count 2 2006.286.03:52:18.90#ibcon#end of sib2, iclass 27, count 2 2006.286.03:52:18.90#ibcon#*mode == 0, iclass 27, count 2 2006.286.03:52:18.90#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.03:52:18.90#ibcon#[27=AT02-05\r\n] 2006.286.03:52:18.90#ibcon#*before write, iclass 27, count 2 2006.286.03:52:18.90#ibcon#enter sib2, iclass 27, count 2 2006.286.03:52:18.90#ibcon#flushed, iclass 27, count 2 2006.286.03:52:18.90#ibcon#about to write, iclass 27, count 2 2006.286.03:52:18.90#ibcon#wrote, iclass 27, count 2 2006.286.03:52:18.90#ibcon#about to read 3, iclass 27, count 2 2006.286.03:52:18.93#ibcon#read 3, iclass 27, count 2 2006.286.03:52:18.93#ibcon#about to read 4, iclass 27, count 2 2006.286.03:52:18.93#ibcon#read 4, iclass 27, count 2 2006.286.03:52:18.93#ibcon#about to read 5, iclass 27, count 2 2006.286.03:52:18.93#ibcon#read 5, iclass 27, count 2 2006.286.03:52:18.93#ibcon#about to read 6, iclass 27, count 2 2006.286.03:52:18.93#ibcon#read 6, iclass 27, count 2 2006.286.03:52:18.93#ibcon#end of sib2, iclass 27, count 2 2006.286.03:52:18.93#ibcon#*after write, iclass 27, count 2 2006.286.03:52:18.93#ibcon#*before return 0, iclass 27, count 2 2006.286.03:52:18.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:52:18.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.03:52:18.93#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.03:52:18.93#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:18.93#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:52:19.05#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:52:19.05#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:52:19.05#ibcon#enter wrdev, iclass 27, count 0 2006.286.03:52:19.05#ibcon#first serial, iclass 27, count 0 2006.286.03:52:19.05#ibcon#enter sib2, iclass 27, count 0 2006.286.03:52:19.05#ibcon#flushed, iclass 27, count 0 2006.286.03:52:19.05#ibcon#about to write, iclass 27, count 0 2006.286.03:52:19.05#ibcon#wrote, iclass 27, count 0 2006.286.03:52:19.05#ibcon#about to read 3, iclass 27, count 0 2006.286.03:52:19.07#ibcon#read 3, iclass 27, count 0 2006.286.03:52:19.07#ibcon#about to read 4, iclass 27, count 0 2006.286.03:52:19.07#ibcon#read 4, iclass 27, count 0 2006.286.03:52:19.07#ibcon#about to read 5, iclass 27, count 0 2006.286.03:52:19.07#ibcon#read 5, iclass 27, count 0 2006.286.03:52:19.07#ibcon#about to read 6, iclass 27, count 0 2006.286.03:52:19.07#ibcon#read 6, iclass 27, count 0 2006.286.03:52:19.07#ibcon#end of sib2, iclass 27, count 0 2006.286.03:52:19.07#ibcon#*mode == 0, iclass 27, count 0 2006.286.03:52:19.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.03:52:19.07#ibcon#[27=USB\r\n] 2006.286.03:52:19.07#ibcon#*before write, iclass 27, count 0 2006.286.03:52:19.07#ibcon#enter sib2, iclass 27, count 0 2006.286.03:52:19.07#ibcon#flushed, iclass 27, count 0 2006.286.03:52:19.07#ibcon#about to write, iclass 27, count 0 2006.286.03:52:19.07#ibcon#wrote, iclass 27, count 0 2006.286.03:52:19.07#ibcon#about to read 3, iclass 27, count 0 2006.286.03:52:19.10#ibcon#read 3, iclass 27, count 0 2006.286.03:52:19.10#ibcon#about to read 4, iclass 27, count 0 2006.286.03:52:19.10#ibcon#read 4, iclass 27, count 0 2006.286.03:52:19.10#ibcon#about to read 5, iclass 27, count 0 2006.286.03:52:19.10#ibcon#read 5, iclass 27, count 0 2006.286.03:52:19.10#ibcon#about to read 6, iclass 27, count 0 2006.286.03:52:19.10#ibcon#read 6, iclass 27, count 0 2006.286.03:52:19.10#ibcon#end of sib2, iclass 27, count 0 2006.286.03:52:19.10#ibcon#*after write, iclass 27, count 0 2006.286.03:52:19.10#ibcon#*before return 0, iclass 27, count 0 2006.286.03:52:19.10#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:52:19.10#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.03:52:19.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.03:52:19.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.03:52:19.10$vck44/vblo=3,649.99 2006.286.03:52:19.10#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.03:52:19.10#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.03:52:19.10#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:19.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:52:19.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:52:19.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:52:19.10#ibcon#enter wrdev, iclass 29, count 0 2006.286.03:52:19.10#ibcon#first serial, iclass 29, count 0 2006.286.03:52:19.10#ibcon#enter sib2, iclass 29, count 0 2006.286.03:52:19.10#ibcon#flushed, iclass 29, count 0 2006.286.03:52:19.10#ibcon#about to write, iclass 29, count 0 2006.286.03:52:19.10#ibcon#wrote, iclass 29, count 0 2006.286.03:52:19.10#ibcon#about to read 3, iclass 29, count 0 2006.286.03:52:19.12#ibcon#read 3, iclass 29, count 0 2006.286.03:52:19.12#ibcon#about to read 4, iclass 29, count 0 2006.286.03:52:19.12#ibcon#read 4, iclass 29, count 0 2006.286.03:52:19.12#ibcon#about to read 5, iclass 29, count 0 2006.286.03:52:19.12#ibcon#read 5, iclass 29, count 0 2006.286.03:52:19.12#ibcon#about to read 6, iclass 29, count 0 2006.286.03:52:19.12#ibcon#read 6, iclass 29, count 0 2006.286.03:52:19.12#ibcon#end of sib2, iclass 29, count 0 2006.286.03:52:19.12#ibcon#*mode == 0, iclass 29, count 0 2006.286.03:52:19.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.03:52:19.12#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.03:52:19.12#ibcon#*before write, iclass 29, count 0 2006.286.03:52:19.12#ibcon#enter sib2, iclass 29, count 0 2006.286.03:52:19.12#ibcon#flushed, iclass 29, count 0 2006.286.03:52:19.12#ibcon#about to write, iclass 29, count 0 2006.286.03:52:19.12#ibcon#wrote, iclass 29, count 0 2006.286.03:52:19.12#ibcon#about to read 3, iclass 29, count 0 2006.286.03:52:19.16#ibcon#read 3, iclass 29, count 0 2006.286.03:52:19.16#ibcon#about to read 4, iclass 29, count 0 2006.286.03:52:19.16#ibcon#read 4, iclass 29, count 0 2006.286.03:52:19.16#ibcon#about to read 5, iclass 29, count 0 2006.286.03:52:19.16#ibcon#read 5, iclass 29, count 0 2006.286.03:52:19.16#ibcon#about to read 6, iclass 29, count 0 2006.286.03:52:19.16#ibcon#read 6, iclass 29, count 0 2006.286.03:52:19.16#ibcon#end of sib2, iclass 29, count 0 2006.286.03:52:19.16#ibcon#*after write, iclass 29, count 0 2006.286.03:52:19.16#ibcon#*before return 0, iclass 29, count 0 2006.286.03:52:19.16#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:52:19.16#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.03:52:19.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.03:52:19.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.03:52:19.16$vck44/vb=3,4 2006.286.03:52:19.16#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.03:52:19.16#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.03:52:19.16#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:19.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:52:19.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:52:19.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:52:19.22#ibcon#enter wrdev, iclass 31, count 2 2006.286.03:52:19.22#ibcon#first serial, iclass 31, count 2 2006.286.03:52:19.22#ibcon#enter sib2, iclass 31, count 2 2006.286.03:52:19.22#ibcon#flushed, iclass 31, count 2 2006.286.03:52:19.22#ibcon#about to write, iclass 31, count 2 2006.286.03:52:19.22#ibcon#wrote, iclass 31, count 2 2006.286.03:52:19.22#ibcon#about to read 3, iclass 31, count 2 2006.286.03:52:19.24#ibcon#read 3, iclass 31, count 2 2006.286.03:52:19.24#ibcon#about to read 4, iclass 31, count 2 2006.286.03:52:19.24#ibcon#read 4, iclass 31, count 2 2006.286.03:52:19.24#ibcon#about to read 5, iclass 31, count 2 2006.286.03:52:19.24#ibcon#read 5, iclass 31, count 2 2006.286.03:52:19.24#ibcon#about to read 6, iclass 31, count 2 2006.286.03:52:19.24#ibcon#read 6, iclass 31, count 2 2006.286.03:52:19.24#ibcon#end of sib2, iclass 31, count 2 2006.286.03:52:19.24#ibcon#*mode == 0, iclass 31, count 2 2006.286.03:52:19.24#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.03:52:19.24#ibcon#[27=AT03-04\r\n] 2006.286.03:52:19.24#ibcon#*before write, iclass 31, count 2 2006.286.03:52:19.24#ibcon#enter sib2, iclass 31, count 2 2006.286.03:52:19.24#ibcon#flushed, iclass 31, count 2 2006.286.03:52:19.24#ibcon#about to write, iclass 31, count 2 2006.286.03:52:19.24#ibcon#wrote, iclass 31, count 2 2006.286.03:52:19.24#ibcon#about to read 3, iclass 31, count 2 2006.286.03:52:19.27#ibcon#read 3, iclass 31, count 2 2006.286.03:52:19.27#ibcon#about to read 4, iclass 31, count 2 2006.286.03:52:19.27#ibcon#read 4, iclass 31, count 2 2006.286.03:52:19.27#ibcon#about to read 5, iclass 31, count 2 2006.286.03:52:19.27#ibcon#read 5, iclass 31, count 2 2006.286.03:52:19.27#ibcon#about to read 6, iclass 31, count 2 2006.286.03:52:19.27#ibcon#read 6, iclass 31, count 2 2006.286.03:52:19.27#ibcon#end of sib2, iclass 31, count 2 2006.286.03:52:19.27#ibcon#*after write, iclass 31, count 2 2006.286.03:52:19.27#ibcon#*before return 0, iclass 31, count 2 2006.286.03:52:19.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:52:19.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.03:52:19.27#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.03:52:19.27#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:19.27#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:52:19.39#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:52:19.43#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:52:19.43#ibcon#enter wrdev, iclass 31, count 0 2006.286.03:52:19.43#ibcon#first serial, iclass 31, count 0 2006.286.03:52:19.43#ibcon#enter sib2, iclass 31, count 0 2006.286.03:52:19.43#ibcon#flushed, iclass 31, count 0 2006.286.03:52:19.43#ibcon#about to write, iclass 31, count 0 2006.286.03:52:19.43#ibcon#wrote, iclass 31, count 0 2006.286.03:52:19.43#ibcon#about to read 3, iclass 31, count 0 2006.286.03:52:19.44#ibcon#read 3, iclass 31, count 0 2006.286.03:52:19.44#ibcon#about to read 4, iclass 31, count 0 2006.286.03:52:19.44#ibcon#read 4, iclass 31, count 0 2006.286.03:52:19.44#ibcon#about to read 5, iclass 31, count 0 2006.286.03:52:19.44#ibcon#read 5, iclass 31, count 0 2006.286.03:52:19.44#ibcon#about to read 6, iclass 31, count 0 2006.286.03:52:19.44#ibcon#read 6, iclass 31, count 0 2006.286.03:52:19.44#ibcon#end of sib2, iclass 31, count 0 2006.286.03:52:19.44#ibcon#*mode == 0, iclass 31, count 0 2006.286.03:52:19.44#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.03:52:19.44#ibcon#[27=USB\r\n] 2006.286.03:52:19.44#ibcon#*before write, iclass 31, count 0 2006.286.03:52:19.44#ibcon#enter sib2, iclass 31, count 0 2006.286.03:52:19.44#ibcon#flushed, iclass 31, count 0 2006.286.03:52:19.44#ibcon#about to write, iclass 31, count 0 2006.286.03:52:19.44#ibcon#wrote, iclass 31, count 0 2006.286.03:52:19.44#ibcon#about to read 3, iclass 31, count 0 2006.286.03:52:19.47#ibcon#read 3, iclass 31, count 0 2006.286.03:52:19.47#ibcon#about to read 4, iclass 31, count 0 2006.286.03:52:19.47#ibcon#read 4, iclass 31, count 0 2006.286.03:52:19.47#ibcon#about to read 5, iclass 31, count 0 2006.286.03:52:19.47#ibcon#read 5, iclass 31, count 0 2006.286.03:52:19.47#ibcon#about to read 6, iclass 31, count 0 2006.286.03:52:19.47#ibcon#read 6, iclass 31, count 0 2006.286.03:52:19.47#ibcon#end of sib2, iclass 31, count 0 2006.286.03:52:19.47#ibcon#*after write, iclass 31, count 0 2006.286.03:52:19.47#ibcon#*before return 0, iclass 31, count 0 2006.286.03:52:19.47#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:52:19.47#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.03:52:19.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.03:52:19.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.03:52:19.47$vck44/vblo=4,679.99 2006.286.03:52:19.47#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.03:52:19.47#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.03:52:19.47#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:19.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:52:19.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:52:19.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:52:19.47#ibcon#enter wrdev, iclass 33, count 0 2006.286.03:52:19.47#ibcon#first serial, iclass 33, count 0 2006.286.03:52:19.47#ibcon#enter sib2, iclass 33, count 0 2006.286.03:52:19.47#ibcon#flushed, iclass 33, count 0 2006.286.03:52:19.47#ibcon#about to write, iclass 33, count 0 2006.286.03:52:19.47#ibcon#wrote, iclass 33, count 0 2006.286.03:52:19.47#ibcon#about to read 3, iclass 33, count 0 2006.286.03:52:19.49#ibcon#read 3, iclass 33, count 0 2006.286.03:52:19.49#ibcon#about to read 4, iclass 33, count 0 2006.286.03:52:19.49#ibcon#read 4, iclass 33, count 0 2006.286.03:52:19.49#ibcon#about to read 5, iclass 33, count 0 2006.286.03:52:19.49#ibcon#read 5, iclass 33, count 0 2006.286.03:52:19.49#ibcon#about to read 6, iclass 33, count 0 2006.286.03:52:19.49#ibcon#read 6, iclass 33, count 0 2006.286.03:52:19.49#ibcon#end of sib2, iclass 33, count 0 2006.286.03:52:19.49#ibcon#*mode == 0, iclass 33, count 0 2006.286.03:52:19.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.03:52:19.49#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.03:52:19.49#ibcon#*before write, iclass 33, count 0 2006.286.03:52:19.49#ibcon#enter sib2, iclass 33, count 0 2006.286.03:52:19.49#ibcon#flushed, iclass 33, count 0 2006.286.03:52:19.49#ibcon#about to write, iclass 33, count 0 2006.286.03:52:19.49#ibcon#wrote, iclass 33, count 0 2006.286.03:52:19.49#ibcon#about to read 3, iclass 33, count 0 2006.286.03:52:19.53#ibcon#read 3, iclass 33, count 0 2006.286.03:52:19.53#ibcon#about to read 4, iclass 33, count 0 2006.286.03:52:19.53#ibcon#read 4, iclass 33, count 0 2006.286.03:52:19.53#ibcon#about to read 5, iclass 33, count 0 2006.286.03:52:19.53#ibcon#read 5, iclass 33, count 0 2006.286.03:52:19.53#ibcon#about to read 6, iclass 33, count 0 2006.286.03:52:19.53#ibcon#read 6, iclass 33, count 0 2006.286.03:52:19.53#ibcon#end of sib2, iclass 33, count 0 2006.286.03:52:19.53#ibcon#*after write, iclass 33, count 0 2006.286.03:52:19.53#ibcon#*before return 0, iclass 33, count 0 2006.286.03:52:19.53#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:52:19.53#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.03:52:19.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.03:52:19.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.03:52:19.53$vck44/vb=4,5 2006.286.03:52:19.53#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.03:52:19.53#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.03:52:19.53#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:19.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:52:19.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:52:19.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:52:19.59#ibcon#enter wrdev, iclass 35, count 2 2006.286.03:52:19.59#ibcon#first serial, iclass 35, count 2 2006.286.03:52:19.59#ibcon#enter sib2, iclass 35, count 2 2006.286.03:52:19.59#ibcon#flushed, iclass 35, count 2 2006.286.03:52:19.59#ibcon#about to write, iclass 35, count 2 2006.286.03:52:19.59#ibcon#wrote, iclass 35, count 2 2006.286.03:52:19.59#ibcon#about to read 3, iclass 35, count 2 2006.286.03:52:19.61#ibcon#read 3, iclass 35, count 2 2006.286.03:52:19.61#ibcon#about to read 4, iclass 35, count 2 2006.286.03:52:19.61#ibcon#read 4, iclass 35, count 2 2006.286.03:52:19.61#ibcon#about to read 5, iclass 35, count 2 2006.286.03:52:19.61#ibcon#read 5, iclass 35, count 2 2006.286.03:52:19.61#ibcon#about to read 6, iclass 35, count 2 2006.286.03:52:19.61#ibcon#read 6, iclass 35, count 2 2006.286.03:52:19.61#ibcon#end of sib2, iclass 35, count 2 2006.286.03:52:19.61#ibcon#*mode == 0, iclass 35, count 2 2006.286.03:52:19.61#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.03:52:19.61#ibcon#[27=AT04-05\r\n] 2006.286.03:52:19.61#ibcon#*before write, iclass 35, count 2 2006.286.03:52:19.61#ibcon#enter sib2, iclass 35, count 2 2006.286.03:52:19.61#ibcon#flushed, iclass 35, count 2 2006.286.03:52:19.61#ibcon#about to write, iclass 35, count 2 2006.286.03:52:19.61#ibcon#wrote, iclass 35, count 2 2006.286.03:52:19.61#ibcon#about to read 3, iclass 35, count 2 2006.286.03:52:19.64#ibcon#read 3, iclass 35, count 2 2006.286.03:52:19.64#ibcon#about to read 4, iclass 35, count 2 2006.286.03:52:19.64#ibcon#read 4, iclass 35, count 2 2006.286.03:52:19.64#ibcon#about to read 5, iclass 35, count 2 2006.286.03:52:19.64#ibcon#read 5, iclass 35, count 2 2006.286.03:52:19.64#ibcon#about to read 6, iclass 35, count 2 2006.286.03:52:19.64#ibcon#read 6, iclass 35, count 2 2006.286.03:52:19.64#ibcon#end of sib2, iclass 35, count 2 2006.286.03:52:19.64#ibcon#*after write, iclass 35, count 2 2006.286.03:52:19.64#ibcon#*before return 0, iclass 35, count 2 2006.286.03:52:19.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:52:19.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.03:52:19.64#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.03:52:19.64#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:19.64#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:52:19.76#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:52:19.76#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:52:19.76#ibcon#enter wrdev, iclass 35, count 0 2006.286.03:52:19.76#ibcon#first serial, iclass 35, count 0 2006.286.03:52:19.76#ibcon#enter sib2, iclass 35, count 0 2006.286.03:52:19.76#ibcon#flushed, iclass 35, count 0 2006.286.03:52:19.76#ibcon#about to write, iclass 35, count 0 2006.286.03:52:19.76#ibcon#wrote, iclass 35, count 0 2006.286.03:52:19.76#ibcon#about to read 3, iclass 35, count 0 2006.286.03:52:19.78#ibcon#read 3, iclass 35, count 0 2006.286.03:52:19.78#ibcon#about to read 4, iclass 35, count 0 2006.286.03:52:19.78#ibcon#read 4, iclass 35, count 0 2006.286.03:52:19.78#ibcon#about to read 5, iclass 35, count 0 2006.286.03:52:19.78#ibcon#read 5, iclass 35, count 0 2006.286.03:52:19.78#ibcon#about to read 6, iclass 35, count 0 2006.286.03:52:19.78#ibcon#read 6, iclass 35, count 0 2006.286.03:52:19.78#ibcon#end of sib2, iclass 35, count 0 2006.286.03:52:19.78#ibcon#*mode == 0, iclass 35, count 0 2006.286.03:52:19.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.03:52:19.78#ibcon#[27=USB\r\n] 2006.286.03:52:19.78#ibcon#*before write, iclass 35, count 0 2006.286.03:52:19.78#ibcon#enter sib2, iclass 35, count 0 2006.286.03:52:19.78#ibcon#flushed, iclass 35, count 0 2006.286.03:52:19.78#ibcon#about to write, iclass 35, count 0 2006.286.03:52:19.78#ibcon#wrote, iclass 35, count 0 2006.286.03:52:19.78#ibcon#about to read 3, iclass 35, count 0 2006.286.03:52:19.81#ibcon#read 3, iclass 35, count 0 2006.286.03:52:19.81#ibcon#about to read 4, iclass 35, count 0 2006.286.03:52:19.81#ibcon#read 4, iclass 35, count 0 2006.286.03:52:19.81#ibcon#about to read 5, iclass 35, count 0 2006.286.03:52:19.81#ibcon#read 5, iclass 35, count 0 2006.286.03:52:19.81#ibcon#about to read 6, iclass 35, count 0 2006.286.03:52:19.81#ibcon#read 6, iclass 35, count 0 2006.286.03:52:19.81#ibcon#end of sib2, iclass 35, count 0 2006.286.03:52:19.81#ibcon#*after write, iclass 35, count 0 2006.286.03:52:19.81#ibcon#*before return 0, iclass 35, count 0 2006.286.03:52:19.81#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:52:19.81#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.03:52:19.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.03:52:19.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.03:52:19.81$vck44/vblo=5,709.99 2006.286.03:52:19.81#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.03:52:19.81#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.03:52:19.81#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:19.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:52:19.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:52:19.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:52:19.81#ibcon#enter wrdev, iclass 37, count 0 2006.286.03:52:19.81#ibcon#first serial, iclass 37, count 0 2006.286.03:52:19.81#ibcon#enter sib2, iclass 37, count 0 2006.286.03:52:19.81#ibcon#flushed, iclass 37, count 0 2006.286.03:52:19.81#ibcon#about to write, iclass 37, count 0 2006.286.03:52:19.81#ibcon#wrote, iclass 37, count 0 2006.286.03:52:19.81#ibcon#about to read 3, iclass 37, count 0 2006.286.03:52:19.83#ibcon#read 3, iclass 37, count 0 2006.286.03:52:19.83#ibcon#about to read 4, iclass 37, count 0 2006.286.03:52:19.83#ibcon#read 4, iclass 37, count 0 2006.286.03:52:19.83#ibcon#about to read 5, iclass 37, count 0 2006.286.03:52:19.83#ibcon#read 5, iclass 37, count 0 2006.286.03:52:19.83#ibcon#about to read 6, iclass 37, count 0 2006.286.03:52:19.83#ibcon#read 6, iclass 37, count 0 2006.286.03:52:19.83#ibcon#end of sib2, iclass 37, count 0 2006.286.03:52:19.83#ibcon#*mode == 0, iclass 37, count 0 2006.286.03:52:19.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.03:52:19.83#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.03:52:19.83#ibcon#*before write, iclass 37, count 0 2006.286.03:52:19.83#ibcon#enter sib2, iclass 37, count 0 2006.286.03:52:19.83#ibcon#flushed, iclass 37, count 0 2006.286.03:52:19.83#ibcon#about to write, iclass 37, count 0 2006.286.03:52:19.83#ibcon#wrote, iclass 37, count 0 2006.286.03:52:19.83#ibcon#about to read 3, iclass 37, count 0 2006.286.03:52:19.87#ibcon#read 3, iclass 37, count 0 2006.286.03:52:19.87#ibcon#about to read 4, iclass 37, count 0 2006.286.03:52:19.87#ibcon#read 4, iclass 37, count 0 2006.286.03:52:19.87#ibcon#about to read 5, iclass 37, count 0 2006.286.03:52:19.87#ibcon#read 5, iclass 37, count 0 2006.286.03:52:19.87#ibcon#about to read 6, iclass 37, count 0 2006.286.03:52:19.87#ibcon#read 6, iclass 37, count 0 2006.286.03:52:19.87#ibcon#end of sib2, iclass 37, count 0 2006.286.03:52:19.87#ibcon#*after write, iclass 37, count 0 2006.286.03:52:19.87#ibcon#*before return 0, iclass 37, count 0 2006.286.03:52:19.87#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:52:19.87#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.03:52:19.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.03:52:19.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.03:52:19.87$vck44/vb=5,4 2006.286.03:52:19.87#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.03:52:19.87#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.03:52:19.87#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:19.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:52:19.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:52:19.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:52:19.93#ibcon#enter wrdev, iclass 39, count 2 2006.286.03:52:19.93#ibcon#first serial, iclass 39, count 2 2006.286.03:52:19.93#ibcon#enter sib2, iclass 39, count 2 2006.286.03:52:19.93#ibcon#flushed, iclass 39, count 2 2006.286.03:52:19.93#ibcon#about to write, iclass 39, count 2 2006.286.03:52:19.93#ibcon#wrote, iclass 39, count 2 2006.286.03:52:19.93#ibcon#about to read 3, iclass 39, count 2 2006.286.03:52:19.95#ibcon#read 3, iclass 39, count 2 2006.286.03:52:19.95#ibcon#about to read 4, iclass 39, count 2 2006.286.03:52:19.95#ibcon#read 4, iclass 39, count 2 2006.286.03:52:19.95#ibcon#about to read 5, iclass 39, count 2 2006.286.03:52:19.95#ibcon#read 5, iclass 39, count 2 2006.286.03:52:19.95#ibcon#about to read 6, iclass 39, count 2 2006.286.03:52:19.95#ibcon#read 6, iclass 39, count 2 2006.286.03:52:19.95#ibcon#end of sib2, iclass 39, count 2 2006.286.03:52:19.95#ibcon#*mode == 0, iclass 39, count 2 2006.286.03:52:19.95#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.03:52:19.95#ibcon#[27=AT05-04\r\n] 2006.286.03:52:19.95#ibcon#*before write, iclass 39, count 2 2006.286.03:52:19.95#ibcon#enter sib2, iclass 39, count 2 2006.286.03:52:19.95#ibcon#flushed, iclass 39, count 2 2006.286.03:52:19.95#ibcon#about to write, iclass 39, count 2 2006.286.03:52:19.95#ibcon#wrote, iclass 39, count 2 2006.286.03:52:19.95#ibcon#about to read 3, iclass 39, count 2 2006.286.03:52:19.98#ibcon#read 3, iclass 39, count 2 2006.286.03:52:19.98#ibcon#about to read 4, iclass 39, count 2 2006.286.03:52:19.98#ibcon#read 4, iclass 39, count 2 2006.286.03:52:19.98#ibcon#about to read 5, iclass 39, count 2 2006.286.03:52:19.98#ibcon#read 5, iclass 39, count 2 2006.286.03:52:19.98#ibcon#about to read 6, iclass 39, count 2 2006.286.03:52:19.98#ibcon#read 6, iclass 39, count 2 2006.286.03:52:19.98#ibcon#end of sib2, iclass 39, count 2 2006.286.03:52:19.98#ibcon#*after write, iclass 39, count 2 2006.286.03:52:19.98#ibcon#*before return 0, iclass 39, count 2 2006.286.03:52:19.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:52:19.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.03:52:19.98#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.03:52:19.98#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:19.98#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:52:20.10#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:52:20.10#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:52:20.10#ibcon#enter wrdev, iclass 39, count 0 2006.286.03:52:20.10#ibcon#first serial, iclass 39, count 0 2006.286.03:52:20.10#ibcon#enter sib2, iclass 39, count 0 2006.286.03:52:20.10#ibcon#flushed, iclass 39, count 0 2006.286.03:52:20.10#ibcon#about to write, iclass 39, count 0 2006.286.03:52:20.10#ibcon#wrote, iclass 39, count 0 2006.286.03:52:20.10#ibcon#about to read 3, iclass 39, count 0 2006.286.03:52:20.12#ibcon#read 3, iclass 39, count 0 2006.286.03:52:20.12#ibcon#about to read 4, iclass 39, count 0 2006.286.03:52:20.12#ibcon#read 4, iclass 39, count 0 2006.286.03:52:20.12#ibcon#about to read 5, iclass 39, count 0 2006.286.03:52:20.12#ibcon#read 5, iclass 39, count 0 2006.286.03:52:20.12#ibcon#about to read 6, iclass 39, count 0 2006.286.03:52:20.12#ibcon#read 6, iclass 39, count 0 2006.286.03:52:20.12#ibcon#end of sib2, iclass 39, count 0 2006.286.03:52:20.12#ibcon#*mode == 0, iclass 39, count 0 2006.286.03:52:20.12#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.03:52:20.12#ibcon#[27=USB\r\n] 2006.286.03:52:20.12#ibcon#*before write, iclass 39, count 0 2006.286.03:52:20.12#ibcon#enter sib2, iclass 39, count 0 2006.286.03:52:20.12#ibcon#flushed, iclass 39, count 0 2006.286.03:52:20.12#ibcon#about to write, iclass 39, count 0 2006.286.03:52:20.12#ibcon#wrote, iclass 39, count 0 2006.286.03:52:20.12#ibcon#about to read 3, iclass 39, count 0 2006.286.03:52:20.15#ibcon#read 3, iclass 39, count 0 2006.286.03:52:20.15#ibcon#about to read 4, iclass 39, count 0 2006.286.03:52:20.15#ibcon#read 4, iclass 39, count 0 2006.286.03:52:20.15#ibcon#about to read 5, iclass 39, count 0 2006.286.03:52:20.15#ibcon#read 5, iclass 39, count 0 2006.286.03:52:20.15#ibcon#about to read 6, iclass 39, count 0 2006.286.03:52:20.15#ibcon#read 6, iclass 39, count 0 2006.286.03:52:20.15#ibcon#end of sib2, iclass 39, count 0 2006.286.03:52:20.15#ibcon#*after write, iclass 39, count 0 2006.286.03:52:20.15#ibcon#*before return 0, iclass 39, count 0 2006.286.03:52:20.15#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:52:20.15#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.03:52:20.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.03:52:20.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.03:52:20.15$vck44/vblo=6,719.99 2006.286.03:52:20.15#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.03:52:20.15#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.03:52:20.15#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:20.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:52:20.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:52:20.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:52:20.15#ibcon#enter wrdev, iclass 3, count 0 2006.286.03:52:20.15#ibcon#first serial, iclass 3, count 0 2006.286.03:52:20.15#ibcon#enter sib2, iclass 3, count 0 2006.286.03:52:20.15#ibcon#flushed, iclass 3, count 0 2006.286.03:52:20.15#ibcon#about to write, iclass 3, count 0 2006.286.03:52:20.15#ibcon#wrote, iclass 3, count 0 2006.286.03:52:20.15#ibcon#about to read 3, iclass 3, count 0 2006.286.03:52:20.17#ibcon#read 3, iclass 3, count 0 2006.286.03:52:20.17#ibcon#about to read 4, iclass 3, count 0 2006.286.03:52:20.17#ibcon#read 4, iclass 3, count 0 2006.286.03:52:20.17#ibcon#about to read 5, iclass 3, count 0 2006.286.03:52:20.17#ibcon#read 5, iclass 3, count 0 2006.286.03:52:20.17#ibcon#about to read 6, iclass 3, count 0 2006.286.03:52:20.17#ibcon#read 6, iclass 3, count 0 2006.286.03:52:20.17#ibcon#end of sib2, iclass 3, count 0 2006.286.03:52:20.17#ibcon#*mode == 0, iclass 3, count 0 2006.286.03:52:20.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.03:52:20.17#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.03:52:20.17#ibcon#*before write, iclass 3, count 0 2006.286.03:52:20.17#ibcon#enter sib2, iclass 3, count 0 2006.286.03:52:20.17#ibcon#flushed, iclass 3, count 0 2006.286.03:52:20.17#ibcon#about to write, iclass 3, count 0 2006.286.03:52:20.17#ibcon#wrote, iclass 3, count 0 2006.286.03:52:20.17#ibcon#about to read 3, iclass 3, count 0 2006.286.03:52:20.21#ibcon#read 3, iclass 3, count 0 2006.286.03:52:20.21#ibcon#about to read 4, iclass 3, count 0 2006.286.03:52:20.21#ibcon#read 4, iclass 3, count 0 2006.286.03:52:20.21#ibcon#about to read 5, iclass 3, count 0 2006.286.03:52:20.21#ibcon#read 5, iclass 3, count 0 2006.286.03:52:20.21#ibcon#about to read 6, iclass 3, count 0 2006.286.03:52:20.21#ibcon#read 6, iclass 3, count 0 2006.286.03:52:20.21#ibcon#end of sib2, iclass 3, count 0 2006.286.03:52:20.21#ibcon#*after write, iclass 3, count 0 2006.286.03:52:20.21#ibcon#*before return 0, iclass 3, count 0 2006.286.03:52:20.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:52:20.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.03:52:20.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.03:52:20.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.03:52:20.21$vck44/vb=6,3 2006.286.03:52:20.21#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.03:52:20.21#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.03:52:20.21#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:20.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:52:20.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:52:20.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:52:20.27#ibcon#enter wrdev, iclass 5, count 2 2006.286.03:52:20.27#ibcon#first serial, iclass 5, count 2 2006.286.03:52:20.27#ibcon#enter sib2, iclass 5, count 2 2006.286.03:52:20.27#ibcon#flushed, iclass 5, count 2 2006.286.03:52:20.27#ibcon#about to write, iclass 5, count 2 2006.286.03:52:20.27#ibcon#wrote, iclass 5, count 2 2006.286.03:52:20.27#ibcon#about to read 3, iclass 5, count 2 2006.286.03:52:20.29#ibcon#read 3, iclass 5, count 2 2006.286.03:52:20.29#ibcon#about to read 4, iclass 5, count 2 2006.286.03:52:20.29#ibcon#read 4, iclass 5, count 2 2006.286.03:52:20.29#ibcon#about to read 5, iclass 5, count 2 2006.286.03:52:20.29#ibcon#read 5, iclass 5, count 2 2006.286.03:52:20.29#ibcon#about to read 6, iclass 5, count 2 2006.286.03:52:20.29#ibcon#read 6, iclass 5, count 2 2006.286.03:52:20.29#ibcon#end of sib2, iclass 5, count 2 2006.286.03:52:20.29#ibcon#*mode == 0, iclass 5, count 2 2006.286.03:52:20.29#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.03:52:20.29#ibcon#[27=AT06-03\r\n] 2006.286.03:52:20.29#ibcon#*before write, iclass 5, count 2 2006.286.03:52:20.29#ibcon#enter sib2, iclass 5, count 2 2006.286.03:52:20.29#ibcon#flushed, iclass 5, count 2 2006.286.03:52:20.29#ibcon#about to write, iclass 5, count 2 2006.286.03:52:20.29#ibcon#wrote, iclass 5, count 2 2006.286.03:52:20.29#ibcon#about to read 3, iclass 5, count 2 2006.286.03:52:20.32#ibcon#read 3, iclass 5, count 2 2006.286.03:52:20.32#ibcon#about to read 4, iclass 5, count 2 2006.286.03:52:20.32#ibcon#read 4, iclass 5, count 2 2006.286.03:52:20.32#ibcon#about to read 5, iclass 5, count 2 2006.286.03:52:20.32#ibcon#read 5, iclass 5, count 2 2006.286.03:52:20.32#ibcon#about to read 6, iclass 5, count 2 2006.286.03:52:20.32#ibcon#read 6, iclass 5, count 2 2006.286.03:52:20.32#ibcon#end of sib2, iclass 5, count 2 2006.286.03:52:20.32#ibcon#*after write, iclass 5, count 2 2006.286.03:52:20.32#ibcon#*before return 0, iclass 5, count 2 2006.286.03:52:20.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:52:20.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.03:52:20.32#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.03:52:20.32#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:20.32#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:52:20.44#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:52:20.44#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:52:20.44#ibcon#enter wrdev, iclass 5, count 0 2006.286.03:52:20.44#ibcon#first serial, iclass 5, count 0 2006.286.03:52:20.44#ibcon#enter sib2, iclass 5, count 0 2006.286.03:52:20.44#ibcon#flushed, iclass 5, count 0 2006.286.03:52:20.44#ibcon#about to write, iclass 5, count 0 2006.286.03:52:20.44#ibcon#wrote, iclass 5, count 0 2006.286.03:52:20.44#ibcon#about to read 3, iclass 5, count 0 2006.286.03:52:20.46#ibcon#read 3, iclass 5, count 0 2006.286.03:52:20.46#ibcon#about to read 4, iclass 5, count 0 2006.286.03:52:20.46#ibcon#read 4, iclass 5, count 0 2006.286.03:52:20.46#ibcon#about to read 5, iclass 5, count 0 2006.286.03:52:20.46#ibcon#read 5, iclass 5, count 0 2006.286.03:52:20.46#ibcon#about to read 6, iclass 5, count 0 2006.286.03:52:20.46#ibcon#read 6, iclass 5, count 0 2006.286.03:52:20.46#ibcon#end of sib2, iclass 5, count 0 2006.286.03:52:20.46#ibcon#*mode == 0, iclass 5, count 0 2006.286.03:52:20.46#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.03:52:20.46#ibcon#[27=USB\r\n] 2006.286.03:52:20.46#ibcon#*before write, iclass 5, count 0 2006.286.03:52:20.46#ibcon#enter sib2, iclass 5, count 0 2006.286.03:52:20.46#ibcon#flushed, iclass 5, count 0 2006.286.03:52:20.46#ibcon#about to write, iclass 5, count 0 2006.286.03:52:20.46#ibcon#wrote, iclass 5, count 0 2006.286.03:52:20.46#ibcon#about to read 3, iclass 5, count 0 2006.286.03:52:20.49#ibcon#read 3, iclass 5, count 0 2006.286.03:52:20.49#ibcon#about to read 4, iclass 5, count 0 2006.286.03:52:20.49#ibcon#read 4, iclass 5, count 0 2006.286.03:52:20.49#ibcon#about to read 5, iclass 5, count 0 2006.286.03:52:20.49#ibcon#read 5, iclass 5, count 0 2006.286.03:52:20.49#ibcon#about to read 6, iclass 5, count 0 2006.286.03:52:20.49#ibcon#read 6, iclass 5, count 0 2006.286.03:52:20.49#ibcon#end of sib2, iclass 5, count 0 2006.286.03:52:20.49#ibcon#*after write, iclass 5, count 0 2006.286.03:52:20.49#ibcon#*before return 0, iclass 5, count 0 2006.286.03:52:20.49#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:52:20.49#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.03:52:20.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.03:52:20.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.03:52:20.49$vck44/vblo=7,734.99 2006.286.03:52:20.49#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.03:52:20.49#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.03:52:20.49#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:20.49#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:52:20.49#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:52:20.49#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:52:20.49#ibcon#enter wrdev, iclass 7, count 0 2006.286.03:52:20.49#ibcon#first serial, iclass 7, count 0 2006.286.03:52:20.49#ibcon#enter sib2, iclass 7, count 0 2006.286.03:52:20.49#ibcon#flushed, iclass 7, count 0 2006.286.03:52:20.49#ibcon#about to write, iclass 7, count 0 2006.286.03:52:20.49#ibcon#wrote, iclass 7, count 0 2006.286.03:52:20.49#ibcon#about to read 3, iclass 7, count 0 2006.286.03:52:20.51#ibcon#read 3, iclass 7, count 0 2006.286.03:52:20.51#ibcon#about to read 4, iclass 7, count 0 2006.286.03:52:20.51#ibcon#read 4, iclass 7, count 0 2006.286.03:52:20.51#ibcon#about to read 5, iclass 7, count 0 2006.286.03:52:20.51#ibcon#read 5, iclass 7, count 0 2006.286.03:52:20.51#ibcon#about to read 6, iclass 7, count 0 2006.286.03:52:20.51#ibcon#read 6, iclass 7, count 0 2006.286.03:52:20.51#ibcon#end of sib2, iclass 7, count 0 2006.286.03:52:20.51#ibcon#*mode == 0, iclass 7, count 0 2006.286.03:52:20.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.03:52:20.51#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.03:52:20.51#ibcon#*before write, iclass 7, count 0 2006.286.03:52:20.51#ibcon#enter sib2, iclass 7, count 0 2006.286.03:52:20.51#ibcon#flushed, iclass 7, count 0 2006.286.03:52:20.51#ibcon#about to write, iclass 7, count 0 2006.286.03:52:20.51#ibcon#wrote, iclass 7, count 0 2006.286.03:52:20.51#ibcon#about to read 3, iclass 7, count 0 2006.286.03:52:20.55#ibcon#read 3, iclass 7, count 0 2006.286.03:52:20.55#ibcon#about to read 4, iclass 7, count 0 2006.286.03:52:20.55#ibcon#read 4, iclass 7, count 0 2006.286.03:52:20.55#ibcon#about to read 5, iclass 7, count 0 2006.286.03:52:20.55#ibcon#read 5, iclass 7, count 0 2006.286.03:52:20.55#ibcon#about to read 6, iclass 7, count 0 2006.286.03:52:20.55#ibcon#read 6, iclass 7, count 0 2006.286.03:52:20.55#ibcon#end of sib2, iclass 7, count 0 2006.286.03:52:20.55#ibcon#*after write, iclass 7, count 0 2006.286.03:52:20.55#ibcon#*before return 0, iclass 7, count 0 2006.286.03:52:20.55#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:52:20.55#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.03:52:20.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.03:52:20.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.03:52:20.55$vck44/vb=7,4 2006.286.03:52:20.55#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.03:52:20.55#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.03:52:20.55#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:20.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.03:52:20.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.03:52:20.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.03:52:20.61#ibcon#enter wrdev, iclass 11, count 2 2006.286.03:52:20.61#ibcon#first serial, iclass 11, count 2 2006.286.03:52:20.61#ibcon#enter sib2, iclass 11, count 2 2006.286.03:52:20.61#ibcon#flushed, iclass 11, count 2 2006.286.03:52:20.61#ibcon#about to write, iclass 11, count 2 2006.286.03:52:20.61#ibcon#wrote, iclass 11, count 2 2006.286.03:52:20.61#ibcon#about to read 3, iclass 11, count 2 2006.286.03:52:20.63#ibcon#read 3, iclass 11, count 2 2006.286.03:52:20.63#ibcon#about to read 4, iclass 11, count 2 2006.286.03:52:20.63#ibcon#read 4, iclass 11, count 2 2006.286.03:52:20.63#ibcon#about to read 5, iclass 11, count 2 2006.286.03:52:20.63#ibcon#read 5, iclass 11, count 2 2006.286.03:52:20.63#ibcon#about to read 6, iclass 11, count 2 2006.286.03:52:20.63#ibcon#read 6, iclass 11, count 2 2006.286.03:52:20.63#ibcon#end of sib2, iclass 11, count 2 2006.286.03:52:20.63#ibcon#*mode == 0, iclass 11, count 2 2006.286.03:52:20.63#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.03:52:20.63#ibcon#[27=AT07-04\r\n] 2006.286.03:52:20.63#ibcon#*before write, iclass 11, count 2 2006.286.03:52:20.63#ibcon#enter sib2, iclass 11, count 2 2006.286.03:52:20.63#ibcon#flushed, iclass 11, count 2 2006.286.03:52:20.63#ibcon#about to write, iclass 11, count 2 2006.286.03:52:20.63#ibcon#wrote, iclass 11, count 2 2006.286.03:52:20.63#ibcon#about to read 3, iclass 11, count 2 2006.286.03:52:20.66#ibcon#read 3, iclass 11, count 2 2006.286.03:52:20.66#ibcon#about to read 4, iclass 11, count 2 2006.286.03:52:20.66#ibcon#read 4, iclass 11, count 2 2006.286.03:52:20.66#ibcon#about to read 5, iclass 11, count 2 2006.286.03:52:20.66#ibcon#read 5, iclass 11, count 2 2006.286.03:52:20.66#ibcon#about to read 6, iclass 11, count 2 2006.286.03:52:20.66#ibcon#read 6, iclass 11, count 2 2006.286.03:52:20.66#ibcon#end of sib2, iclass 11, count 2 2006.286.03:52:20.66#ibcon#*after write, iclass 11, count 2 2006.286.03:52:20.66#ibcon#*before return 0, iclass 11, count 2 2006.286.03:52:20.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.03:52:20.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.03:52:20.66#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.03:52:20.66#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:20.66#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.03:52:20.78#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.03:52:20.78#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.03:52:20.78#ibcon#enter wrdev, iclass 11, count 0 2006.286.03:52:20.78#ibcon#first serial, iclass 11, count 0 2006.286.03:52:20.78#ibcon#enter sib2, iclass 11, count 0 2006.286.03:52:20.78#ibcon#flushed, iclass 11, count 0 2006.286.03:52:20.78#ibcon#about to write, iclass 11, count 0 2006.286.03:52:20.78#ibcon#wrote, iclass 11, count 0 2006.286.03:52:20.78#ibcon#about to read 3, iclass 11, count 0 2006.286.03:52:20.80#ibcon#read 3, iclass 11, count 0 2006.286.03:52:20.80#ibcon#about to read 4, iclass 11, count 0 2006.286.03:52:20.80#ibcon#read 4, iclass 11, count 0 2006.286.03:52:20.80#ibcon#about to read 5, iclass 11, count 0 2006.286.03:52:20.80#ibcon#read 5, iclass 11, count 0 2006.286.03:52:20.80#ibcon#about to read 6, iclass 11, count 0 2006.286.03:52:20.80#ibcon#read 6, iclass 11, count 0 2006.286.03:52:20.80#ibcon#end of sib2, iclass 11, count 0 2006.286.03:52:20.80#ibcon#*mode == 0, iclass 11, count 0 2006.286.03:52:20.80#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.03:52:20.80#ibcon#[27=USB\r\n] 2006.286.03:52:20.80#ibcon#*before write, iclass 11, count 0 2006.286.03:52:20.80#ibcon#enter sib2, iclass 11, count 0 2006.286.03:52:20.80#ibcon#flushed, iclass 11, count 0 2006.286.03:52:20.80#ibcon#about to write, iclass 11, count 0 2006.286.03:52:20.80#ibcon#wrote, iclass 11, count 0 2006.286.03:52:20.80#ibcon#about to read 3, iclass 11, count 0 2006.286.03:52:20.83#ibcon#read 3, iclass 11, count 0 2006.286.03:52:20.83#ibcon#about to read 4, iclass 11, count 0 2006.286.03:52:20.83#ibcon#read 4, iclass 11, count 0 2006.286.03:52:20.83#ibcon#about to read 5, iclass 11, count 0 2006.286.03:52:20.83#ibcon#read 5, iclass 11, count 0 2006.286.03:52:20.83#ibcon#about to read 6, iclass 11, count 0 2006.286.03:52:20.83#ibcon#read 6, iclass 11, count 0 2006.286.03:52:20.83#ibcon#end of sib2, iclass 11, count 0 2006.286.03:52:20.83#ibcon#*after write, iclass 11, count 0 2006.286.03:52:20.83#ibcon#*before return 0, iclass 11, count 0 2006.286.03:52:20.83#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.03:52:20.83#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.03:52:20.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.03:52:20.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.03:52:20.83$vck44/vblo=8,744.99 2006.286.03:52:20.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.03:52:20.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.03:52:20.83#ibcon#ireg 17 cls_cnt 0 2006.286.03:52:20.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:52:20.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:52:20.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:52:20.83#ibcon#enter wrdev, iclass 13, count 0 2006.286.03:52:20.83#ibcon#first serial, iclass 13, count 0 2006.286.03:52:20.83#ibcon#enter sib2, iclass 13, count 0 2006.286.03:52:20.83#ibcon#flushed, iclass 13, count 0 2006.286.03:52:20.83#ibcon#about to write, iclass 13, count 0 2006.286.03:52:20.83#ibcon#wrote, iclass 13, count 0 2006.286.03:52:20.83#ibcon#about to read 3, iclass 13, count 0 2006.286.03:52:20.85#ibcon#read 3, iclass 13, count 0 2006.286.03:52:20.85#ibcon#about to read 4, iclass 13, count 0 2006.286.03:52:20.85#ibcon#read 4, iclass 13, count 0 2006.286.03:52:20.85#ibcon#about to read 5, iclass 13, count 0 2006.286.03:52:20.85#ibcon#read 5, iclass 13, count 0 2006.286.03:52:20.85#ibcon#about to read 6, iclass 13, count 0 2006.286.03:52:20.85#ibcon#read 6, iclass 13, count 0 2006.286.03:52:20.85#ibcon#end of sib2, iclass 13, count 0 2006.286.03:52:20.85#ibcon#*mode == 0, iclass 13, count 0 2006.286.03:52:20.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.03:52:20.85#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.03:52:20.85#ibcon#*before write, iclass 13, count 0 2006.286.03:52:20.85#ibcon#enter sib2, iclass 13, count 0 2006.286.03:52:20.85#ibcon#flushed, iclass 13, count 0 2006.286.03:52:20.85#ibcon#about to write, iclass 13, count 0 2006.286.03:52:20.85#ibcon#wrote, iclass 13, count 0 2006.286.03:52:20.85#ibcon#about to read 3, iclass 13, count 0 2006.286.03:52:20.89#ibcon#read 3, iclass 13, count 0 2006.286.03:52:20.89#ibcon#about to read 4, iclass 13, count 0 2006.286.03:52:20.89#ibcon#read 4, iclass 13, count 0 2006.286.03:52:20.89#ibcon#about to read 5, iclass 13, count 0 2006.286.03:52:20.89#ibcon#read 5, iclass 13, count 0 2006.286.03:52:20.89#ibcon#about to read 6, iclass 13, count 0 2006.286.03:52:20.89#ibcon#read 6, iclass 13, count 0 2006.286.03:52:20.89#ibcon#end of sib2, iclass 13, count 0 2006.286.03:52:20.89#ibcon#*after write, iclass 13, count 0 2006.286.03:52:20.89#ibcon#*before return 0, iclass 13, count 0 2006.286.03:52:20.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:52:20.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.03:52:20.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.03:52:20.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.03:52:20.89$vck44/vb=8,4 2006.286.03:52:20.89#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.03:52:20.89#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.03:52:20.89#ibcon#ireg 11 cls_cnt 2 2006.286.03:52:20.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:52:20.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:52:20.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:52:20.95#ibcon#enter wrdev, iclass 15, count 2 2006.286.03:52:20.95#ibcon#first serial, iclass 15, count 2 2006.286.03:52:20.95#ibcon#enter sib2, iclass 15, count 2 2006.286.03:52:20.95#ibcon#flushed, iclass 15, count 2 2006.286.03:52:20.95#ibcon#about to write, iclass 15, count 2 2006.286.03:52:20.95#ibcon#wrote, iclass 15, count 2 2006.286.03:52:20.95#ibcon#about to read 3, iclass 15, count 2 2006.286.03:52:20.97#ibcon#read 3, iclass 15, count 2 2006.286.03:52:20.97#ibcon#about to read 4, iclass 15, count 2 2006.286.03:52:20.97#ibcon#read 4, iclass 15, count 2 2006.286.03:52:20.97#ibcon#about to read 5, iclass 15, count 2 2006.286.03:52:20.97#ibcon#read 5, iclass 15, count 2 2006.286.03:52:20.97#ibcon#about to read 6, iclass 15, count 2 2006.286.03:52:20.97#ibcon#read 6, iclass 15, count 2 2006.286.03:52:20.97#ibcon#end of sib2, iclass 15, count 2 2006.286.03:52:20.97#ibcon#*mode == 0, iclass 15, count 2 2006.286.03:52:20.97#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.03:52:20.97#ibcon#[27=AT08-04\r\n] 2006.286.03:52:20.97#ibcon#*before write, iclass 15, count 2 2006.286.03:52:20.97#ibcon#enter sib2, iclass 15, count 2 2006.286.03:52:20.97#ibcon#flushed, iclass 15, count 2 2006.286.03:52:20.97#ibcon#about to write, iclass 15, count 2 2006.286.03:52:20.97#ibcon#wrote, iclass 15, count 2 2006.286.03:52:20.97#ibcon#about to read 3, iclass 15, count 2 2006.286.03:52:21.00#ibcon#read 3, iclass 15, count 2 2006.286.03:52:21.00#ibcon#about to read 4, iclass 15, count 2 2006.286.03:52:21.00#ibcon#read 4, iclass 15, count 2 2006.286.03:52:21.00#ibcon#about to read 5, iclass 15, count 2 2006.286.03:52:21.00#ibcon#read 5, iclass 15, count 2 2006.286.03:52:21.00#ibcon#about to read 6, iclass 15, count 2 2006.286.03:52:21.00#ibcon#read 6, iclass 15, count 2 2006.286.03:52:21.00#ibcon#end of sib2, iclass 15, count 2 2006.286.03:52:21.00#ibcon#*after write, iclass 15, count 2 2006.286.03:52:21.00#ibcon#*before return 0, iclass 15, count 2 2006.286.03:52:21.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:52:21.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.03:52:21.00#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.03:52:21.00#ibcon#ireg 7 cls_cnt 0 2006.286.03:52:21.00#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:52:21.12#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:52:21.12#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:52:21.12#ibcon#enter wrdev, iclass 15, count 0 2006.286.03:52:21.12#ibcon#first serial, iclass 15, count 0 2006.286.03:52:21.12#ibcon#enter sib2, iclass 15, count 0 2006.286.03:52:21.12#ibcon#flushed, iclass 15, count 0 2006.286.03:52:21.12#ibcon#about to write, iclass 15, count 0 2006.286.03:52:21.12#ibcon#wrote, iclass 15, count 0 2006.286.03:52:21.12#ibcon#about to read 3, iclass 15, count 0 2006.286.03:52:21.14#ibcon#read 3, iclass 15, count 0 2006.286.03:52:21.14#ibcon#about to read 4, iclass 15, count 0 2006.286.03:52:21.14#ibcon#read 4, iclass 15, count 0 2006.286.03:52:21.14#ibcon#about to read 5, iclass 15, count 0 2006.286.03:52:21.14#ibcon#read 5, iclass 15, count 0 2006.286.03:52:21.14#ibcon#about to read 6, iclass 15, count 0 2006.286.03:52:21.14#ibcon#read 6, iclass 15, count 0 2006.286.03:52:21.14#ibcon#end of sib2, iclass 15, count 0 2006.286.03:52:21.14#ibcon#*mode == 0, iclass 15, count 0 2006.286.03:52:21.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.03:52:21.14#ibcon#[27=USB\r\n] 2006.286.03:52:21.14#ibcon#*before write, iclass 15, count 0 2006.286.03:52:21.14#ibcon#enter sib2, iclass 15, count 0 2006.286.03:52:21.14#ibcon#flushed, iclass 15, count 0 2006.286.03:52:21.14#ibcon#about to write, iclass 15, count 0 2006.286.03:52:21.14#ibcon#wrote, iclass 15, count 0 2006.286.03:52:21.14#ibcon#about to read 3, iclass 15, count 0 2006.286.03:52:21.17#ibcon#read 3, iclass 15, count 0 2006.286.03:52:21.17#ibcon#about to read 4, iclass 15, count 0 2006.286.03:52:21.17#ibcon#read 4, iclass 15, count 0 2006.286.03:52:21.17#ibcon#about to read 5, iclass 15, count 0 2006.286.03:52:21.17#ibcon#read 5, iclass 15, count 0 2006.286.03:52:21.17#ibcon#about to read 6, iclass 15, count 0 2006.286.03:52:21.17#ibcon#read 6, iclass 15, count 0 2006.286.03:52:21.17#ibcon#end of sib2, iclass 15, count 0 2006.286.03:52:21.17#ibcon#*after write, iclass 15, count 0 2006.286.03:52:21.17#ibcon#*before return 0, iclass 15, count 0 2006.286.03:52:21.17#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:52:21.17#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.03:52:21.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.03:52:21.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.03:52:21.17$vck44/vabw=wide 2006.286.03:52:21.17#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.03:52:21.17#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.03:52:21.17#ibcon#ireg 8 cls_cnt 0 2006.286.03:52:21.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:52:21.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:52:21.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:52:21.17#ibcon#enter wrdev, iclass 17, count 0 2006.286.03:52:21.17#ibcon#first serial, iclass 17, count 0 2006.286.03:52:21.17#ibcon#enter sib2, iclass 17, count 0 2006.286.03:52:21.17#ibcon#flushed, iclass 17, count 0 2006.286.03:52:21.17#ibcon#about to write, iclass 17, count 0 2006.286.03:52:21.17#ibcon#wrote, iclass 17, count 0 2006.286.03:52:21.17#ibcon#about to read 3, iclass 17, count 0 2006.286.03:52:21.19#ibcon#read 3, iclass 17, count 0 2006.286.03:52:21.19#ibcon#about to read 4, iclass 17, count 0 2006.286.03:52:21.19#ibcon#read 4, iclass 17, count 0 2006.286.03:52:21.19#ibcon#about to read 5, iclass 17, count 0 2006.286.03:52:21.19#ibcon#read 5, iclass 17, count 0 2006.286.03:52:21.19#ibcon#about to read 6, iclass 17, count 0 2006.286.03:52:21.19#ibcon#read 6, iclass 17, count 0 2006.286.03:52:21.19#ibcon#end of sib2, iclass 17, count 0 2006.286.03:52:21.19#ibcon#*mode == 0, iclass 17, count 0 2006.286.03:52:21.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.03:52:21.19#ibcon#[25=BW32\r\n] 2006.286.03:52:21.19#ibcon#*before write, iclass 17, count 0 2006.286.03:52:21.19#ibcon#enter sib2, iclass 17, count 0 2006.286.03:52:21.19#ibcon#flushed, iclass 17, count 0 2006.286.03:52:21.19#ibcon#about to write, iclass 17, count 0 2006.286.03:52:21.19#ibcon#wrote, iclass 17, count 0 2006.286.03:52:21.19#ibcon#about to read 3, iclass 17, count 0 2006.286.03:52:21.22#ibcon#read 3, iclass 17, count 0 2006.286.03:52:21.22#ibcon#about to read 4, iclass 17, count 0 2006.286.03:52:21.22#ibcon#read 4, iclass 17, count 0 2006.286.03:52:21.22#ibcon#about to read 5, iclass 17, count 0 2006.286.03:52:21.22#ibcon#read 5, iclass 17, count 0 2006.286.03:52:21.22#ibcon#about to read 6, iclass 17, count 0 2006.286.03:52:21.22#ibcon#read 6, iclass 17, count 0 2006.286.03:52:21.22#ibcon#end of sib2, iclass 17, count 0 2006.286.03:52:21.22#ibcon#*after write, iclass 17, count 0 2006.286.03:52:21.22#ibcon#*before return 0, iclass 17, count 0 2006.286.03:52:21.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:52:21.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.03:52:21.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.03:52:21.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.03:52:21.22$vck44/vbbw=wide 2006.286.03:52:21.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.03:52:21.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.03:52:21.22#ibcon#ireg 8 cls_cnt 0 2006.286.03:52:21.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:52:21.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:52:21.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:52:21.29#ibcon#enter wrdev, iclass 19, count 0 2006.286.03:52:21.29#ibcon#first serial, iclass 19, count 0 2006.286.03:52:21.29#ibcon#enter sib2, iclass 19, count 0 2006.286.03:52:21.29#ibcon#flushed, iclass 19, count 0 2006.286.03:52:21.29#ibcon#about to write, iclass 19, count 0 2006.286.03:52:21.29#ibcon#wrote, iclass 19, count 0 2006.286.03:52:21.29#ibcon#about to read 3, iclass 19, count 0 2006.286.03:52:21.31#ibcon#read 3, iclass 19, count 0 2006.286.03:52:21.42#ibcon#about to read 4, iclass 19, count 0 2006.286.03:52:21.42#ibcon#read 4, iclass 19, count 0 2006.286.03:52:21.42#ibcon#about to read 5, iclass 19, count 0 2006.286.03:52:21.42#ibcon#read 5, iclass 19, count 0 2006.286.03:52:21.42#ibcon#about to read 6, iclass 19, count 0 2006.286.03:52:21.42#ibcon#read 6, iclass 19, count 0 2006.286.03:52:21.42#ibcon#end of sib2, iclass 19, count 0 2006.286.03:52:21.42#ibcon#*mode == 0, iclass 19, count 0 2006.286.03:52:21.42#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.03:52:21.42#ibcon#[27=BW32\r\n] 2006.286.03:52:21.42#ibcon#*before write, iclass 19, count 0 2006.286.03:52:21.42#ibcon#enter sib2, iclass 19, count 0 2006.286.03:52:21.42#ibcon#flushed, iclass 19, count 0 2006.286.03:52:21.42#ibcon#about to write, iclass 19, count 0 2006.286.03:52:21.42#ibcon#wrote, iclass 19, count 0 2006.286.03:52:21.42#ibcon#about to read 3, iclass 19, count 0 2006.286.03:52:21.44#ibcon#read 3, iclass 19, count 0 2006.286.03:52:21.44#ibcon#about to read 4, iclass 19, count 0 2006.286.03:52:21.44#ibcon#read 4, iclass 19, count 0 2006.286.03:52:21.44#ibcon#about to read 5, iclass 19, count 0 2006.286.03:52:21.44#ibcon#read 5, iclass 19, count 0 2006.286.03:52:21.44#ibcon#about to read 6, iclass 19, count 0 2006.286.03:52:21.44#ibcon#read 6, iclass 19, count 0 2006.286.03:52:21.44#ibcon#end of sib2, iclass 19, count 0 2006.286.03:52:21.44#ibcon#*after write, iclass 19, count 0 2006.286.03:52:21.44#ibcon#*before return 0, iclass 19, count 0 2006.286.03:52:21.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:52:21.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.03:52:21.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.03:52:21.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.03:52:21.44$setupk4/ifdk4 2006.286.03:52:21.44$ifdk4/lo= 2006.286.03:52:21.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.03:52:21.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.03:52:21.45$ifdk4/patch= 2006.286.03:52:21.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.03:52:21.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.03:52:21.45$setupk4/!*+20s 2006.286.03:52:27.86#abcon#<5=/04 3.4 7.0 21.79 771015.0\r\n> 2006.286.03:52:27.88#abcon#{5=INTERFACE CLEAR} 2006.286.03:52:27.94#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:52:34.94$setupk4/"tpicd 2006.286.03:52:34.94$setupk4/echo=off 2006.286.03:52:34.94$setupk4/xlog=off 2006.286.03:52:34.94:!2006.286.03:56:58 2006.286.03:53:16.14#trakl#Source acquired 2006.286.03:53:16.14#flagr#flagr/antenna,acquired 2006.286.03:56:58.00:preob 2006.286.03:56:59.13/onsource/TRACKING 2006.286.03:56:59.13:!2006.286.03:57:08 2006.286.03:57:08.00:"tape 2006.286.03:57:08.00:"st=record 2006.286.03:57:08.00:data_valid=on 2006.286.03:57:08.00:midob 2006.286.03:57:08.13/onsource/TRACKING 2006.286.03:57:08.13/wx/21.84,1015.0,75 2006.286.03:57:08.19/cable/+6.4967E-03 2006.286.03:57:09.28/va/01,07,usb,yes,33,35 2006.286.03:57:09.28/va/02,06,usb,yes,33,33 2006.286.03:57:09.28/va/03,07,usb,yes,32,34 2006.286.03:57:09.28/va/04,06,usb,yes,34,35 2006.286.03:57:09.28/va/05,03,usb,yes,33,34 2006.286.03:57:09.28/va/06,04,usb,yes,30,29 2006.286.03:57:09.28/va/07,04,usb,yes,30,31 2006.286.03:57:09.28/va/08,03,usb,yes,31,38 2006.286.03:57:09.51/valo/01,524.99,yes,locked 2006.286.03:57:09.51/valo/02,534.99,yes,locked 2006.286.03:57:09.51/valo/03,564.99,yes,locked 2006.286.03:57:09.51/valo/04,624.99,yes,locked 2006.286.03:57:09.51/valo/05,734.99,yes,locked 2006.286.03:57:09.51/valo/06,814.99,yes,locked 2006.286.03:57:09.51/valo/07,864.99,yes,locked 2006.286.03:57:09.51/valo/08,884.99,yes,locked 2006.286.03:57:10.60/vb/01,04,usb,yes,31,29 2006.286.03:57:10.60/vb/02,05,usb,yes,29,29 2006.286.03:57:10.60/vb/03,04,usb,yes,30,33 2006.286.03:57:10.60/vb/04,05,usb,yes,30,29 2006.286.03:57:10.60/vb/05,04,usb,yes,27,29 2006.286.03:57:10.60/vb/06,03,usb,yes,39,34 2006.286.03:57:10.60/vb/07,04,usb,yes,31,31 2006.286.03:57:10.60/vb/08,04,usb,yes,28,32 2006.286.03:57:10.84/vblo/01,629.99,yes,locked 2006.286.03:57:10.84/vblo/02,634.99,yes,locked 2006.286.03:57:10.84/vblo/03,649.99,yes,locked 2006.286.03:57:10.84/vblo/04,679.99,yes,locked 2006.286.03:57:10.84/vblo/05,709.99,yes,locked 2006.286.03:57:10.84/vblo/06,719.99,yes,locked 2006.286.03:57:10.84/vblo/07,734.99,yes,locked 2006.286.03:57:10.84/vblo/08,744.99,yes,locked 2006.286.03:57:10.99/vabw/8 2006.286.03:57:11.14/vbbw/8 2006.286.03:57:11.23/xfe/off,on,12.2 2006.286.03:57:11.61/ifatt/23,28,28,28 2006.286.03:57:12.07/fmout-gps/S +2.40E-07 2006.286.03:57:12.09:!2006.286.03:57:48 2006.286.03:57:48.00:data_valid=off 2006.286.03:57:48.00:"et 2006.286.03:57:48.00:!+3s 2006.286.03:57:51.01:"tape 2006.286.03:57:51.01:postob 2006.286.03:57:51.12/cable/+6.4957E-03 2006.286.03:57:51.12/wx/21.86,1015.0,76 2006.286.03:57:52.07/fmout-gps/S +2.42E-07 2006.286.03:57:52.07:scan_name=286-0359,jd0610,50 2006.286.03:57:52.07:source=1611+343,161341.06,341247.9,2000.0,cw 2006.286.03:57:53.13#flagr#flagr/antenna,new-source 2006.286.03:57:53.13:checkk5 2006.286.03:57:54.00/chk_autoobs//k5ts1/ autoobs is running! 2006.286.03:57:54.39/chk_autoobs//k5ts2/ autoobs is running! 2006.286.03:57:54.88/chk_autoobs//k5ts3/ autoobs is running! 2006.286.03:57:55.24/chk_autoobs//k5ts4/ autoobs is running! 2006.286.03:57:55.86/chk_obsdata//k5ts1/T2860357??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:57:56.23/chk_obsdata//k5ts2/T2860357??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:57:56.74/chk_obsdata//k5ts3/T2860357??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:57:57.40/chk_obsdata//k5ts4/T2860357??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.03:57:58.21/k5log//k5ts1_log_newline 2006.286.03:57:59.04/k5log//k5ts2_log_newline 2006.286.03:57:59.81/k5log//k5ts3_log_newline 2006.286.03:58:00.55/k5log//k5ts4_log_newline 2006.286.03:58:00.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.03:58:00.58:setupk4=1 2006.286.03:58:00.58$setupk4/echo=on 2006.286.03:58:00.58$setupk4/pcalon 2006.286.03:58:00.58$pcalon/"no phase cal control is implemented here 2006.286.03:58:00.58$setupk4/"tpicd=stop 2006.286.03:58:00.58$setupk4/"rec=synch_on 2006.286.03:58:00.58$setupk4/"rec_mode=128 2006.286.03:58:00.58$setupk4/!* 2006.286.03:58:00.58$setupk4/recpk4 2006.286.03:58:00.58$recpk4/recpatch= 2006.286.03:58:00.58$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.03:58:00.58$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.03:58:00.58$setupk4/vck44 2006.286.03:58:00.58$vck44/valo=1,524.99 2006.286.03:58:00.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.03:58:00.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.03:58:00.58#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:00.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:58:00.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:58:00.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:58:00.58#ibcon#enter wrdev, iclass 12, count 0 2006.286.03:58:00.58#ibcon#first serial, iclass 12, count 0 2006.286.03:58:00.58#ibcon#enter sib2, iclass 12, count 0 2006.286.03:58:00.58#ibcon#flushed, iclass 12, count 0 2006.286.03:58:00.58#ibcon#about to write, iclass 12, count 0 2006.286.03:58:00.58#ibcon#wrote, iclass 12, count 0 2006.286.03:58:00.58#ibcon#about to read 3, iclass 12, count 0 2006.286.03:58:00.59#ibcon#read 3, iclass 12, count 0 2006.286.03:58:00.59#ibcon#about to read 4, iclass 12, count 0 2006.286.03:58:00.59#ibcon#read 4, iclass 12, count 0 2006.286.03:58:00.59#ibcon#about to read 5, iclass 12, count 0 2006.286.03:58:00.59#ibcon#read 5, iclass 12, count 0 2006.286.03:58:00.59#ibcon#about to read 6, iclass 12, count 0 2006.286.03:58:00.59#ibcon#read 6, iclass 12, count 0 2006.286.03:58:00.59#ibcon#end of sib2, iclass 12, count 0 2006.286.03:58:00.59#ibcon#*mode == 0, iclass 12, count 0 2006.286.03:58:00.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.03:58:00.59#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.03:58:00.59#ibcon#*before write, iclass 12, count 0 2006.286.03:58:00.59#ibcon#enter sib2, iclass 12, count 0 2006.286.03:58:00.59#ibcon#flushed, iclass 12, count 0 2006.286.03:58:00.59#ibcon#about to write, iclass 12, count 0 2006.286.03:58:00.59#ibcon#wrote, iclass 12, count 0 2006.286.03:58:00.59#ibcon#about to read 3, iclass 12, count 0 2006.286.03:58:00.64#ibcon#read 3, iclass 12, count 0 2006.286.03:58:00.64#ibcon#about to read 4, iclass 12, count 0 2006.286.03:58:00.64#ibcon#read 4, iclass 12, count 0 2006.286.03:58:00.64#ibcon#about to read 5, iclass 12, count 0 2006.286.03:58:00.64#ibcon#read 5, iclass 12, count 0 2006.286.03:58:00.64#ibcon#about to read 6, iclass 12, count 0 2006.286.03:58:00.64#ibcon#read 6, iclass 12, count 0 2006.286.03:58:00.64#ibcon#end of sib2, iclass 12, count 0 2006.286.03:58:00.64#ibcon#*after write, iclass 12, count 0 2006.286.03:58:00.64#ibcon#*before return 0, iclass 12, count 0 2006.286.03:58:00.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:58:00.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:58:00.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.03:58:00.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.03:58:00.64$vck44/va=1,7 2006.286.03:58:00.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.03:58:00.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.03:58:00.64#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:00.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:58:00.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:58:00.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:58:00.64#ibcon#enter wrdev, iclass 14, count 2 2006.286.03:58:00.64#ibcon#first serial, iclass 14, count 2 2006.286.03:58:00.64#ibcon#enter sib2, iclass 14, count 2 2006.286.03:58:00.64#ibcon#flushed, iclass 14, count 2 2006.286.03:58:00.64#ibcon#about to write, iclass 14, count 2 2006.286.03:58:00.64#ibcon#wrote, iclass 14, count 2 2006.286.03:58:00.64#ibcon#about to read 3, iclass 14, count 2 2006.286.03:58:00.66#ibcon#read 3, iclass 14, count 2 2006.286.03:58:00.66#ibcon#about to read 4, iclass 14, count 2 2006.286.03:58:00.66#ibcon#read 4, iclass 14, count 2 2006.286.03:58:00.66#ibcon#about to read 5, iclass 14, count 2 2006.286.03:58:00.66#ibcon#read 5, iclass 14, count 2 2006.286.03:58:00.66#ibcon#about to read 6, iclass 14, count 2 2006.286.03:58:00.66#ibcon#read 6, iclass 14, count 2 2006.286.03:58:00.66#ibcon#end of sib2, iclass 14, count 2 2006.286.03:58:00.66#ibcon#*mode == 0, iclass 14, count 2 2006.286.03:58:00.66#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.03:58:00.66#ibcon#[25=AT01-07\r\n] 2006.286.03:58:00.66#ibcon#*before write, iclass 14, count 2 2006.286.03:58:00.66#ibcon#enter sib2, iclass 14, count 2 2006.286.03:58:00.66#ibcon#flushed, iclass 14, count 2 2006.286.03:58:00.66#ibcon#about to write, iclass 14, count 2 2006.286.03:58:00.66#ibcon#wrote, iclass 14, count 2 2006.286.03:58:00.66#ibcon#about to read 3, iclass 14, count 2 2006.286.03:58:00.69#ibcon#read 3, iclass 14, count 2 2006.286.03:58:00.69#ibcon#about to read 4, iclass 14, count 2 2006.286.03:58:00.69#ibcon#read 4, iclass 14, count 2 2006.286.03:58:00.69#ibcon#about to read 5, iclass 14, count 2 2006.286.03:58:00.69#ibcon#read 5, iclass 14, count 2 2006.286.03:58:00.69#ibcon#about to read 6, iclass 14, count 2 2006.286.03:58:00.69#ibcon#read 6, iclass 14, count 2 2006.286.03:58:00.69#ibcon#end of sib2, iclass 14, count 2 2006.286.03:58:00.69#ibcon#*after write, iclass 14, count 2 2006.286.03:58:00.69#ibcon#*before return 0, iclass 14, count 2 2006.286.03:58:00.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:58:00.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:58:00.69#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.03:58:00.69#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:00.69#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:58:00.81#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:58:00.81#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:58:00.81#ibcon#enter wrdev, iclass 14, count 0 2006.286.03:58:00.81#ibcon#first serial, iclass 14, count 0 2006.286.03:58:00.81#ibcon#enter sib2, iclass 14, count 0 2006.286.03:58:00.81#ibcon#flushed, iclass 14, count 0 2006.286.03:58:00.81#ibcon#about to write, iclass 14, count 0 2006.286.03:58:00.81#ibcon#wrote, iclass 14, count 0 2006.286.03:58:00.81#ibcon#about to read 3, iclass 14, count 0 2006.286.03:58:00.83#ibcon#read 3, iclass 14, count 0 2006.286.03:58:00.83#ibcon#about to read 4, iclass 14, count 0 2006.286.03:58:00.83#ibcon#read 4, iclass 14, count 0 2006.286.03:58:00.83#ibcon#about to read 5, iclass 14, count 0 2006.286.03:58:00.83#ibcon#read 5, iclass 14, count 0 2006.286.03:58:00.83#ibcon#about to read 6, iclass 14, count 0 2006.286.03:58:00.83#ibcon#read 6, iclass 14, count 0 2006.286.03:58:00.83#ibcon#end of sib2, iclass 14, count 0 2006.286.03:58:00.83#ibcon#*mode == 0, iclass 14, count 0 2006.286.03:58:00.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.03:58:00.83#ibcon#[25=USB\r\n] 2006.286.03:58:00.83#ibcon#*before write, iclass 14, count 0 2006.286.03:58:00.83#ibcon#enter sib2, iclass 14, count 0 2006.286.03:58:00.83#ibcon#flushed, iclass 14, count 0 2006.286.03:58:00.83#ibcon#about to write, iclass 14, count 0 2006.286.03:58:00.83#ibcon#wrote, iclass 14, count 0 2006.286.03:58:00.83#ibcon#about to read 3, iclass 14, count 0 2006.286.03:58:00.86#ibcon#read 3, iclass 14, count 0 2006.286.03:58:00.86#ibcon#about to read 4, iclass 14, count 0 2006.286.03:58:00.86#ibcon#read 4, iclass 14, count 0 2006.286.03:58:00.86#ibcon#about to read 5, iclass 14, count 0 2006.286.03:58:00.86#ibcon#read 5, iclass 14, count 0 2006.286.03:58:00.86#ibcon#about to read 6, iclass 14, count 0 2006.286.03:58:00.86#ibcon#read 6, iclass 14, count 0 2006.286.03:58:00.86#ibcon#end of sib2, iclass 14, count 0 2006.286.03:58:00.86#ibcon#*after write, iclass 14, count 0 2006.286.03:58:00.86#ibcon#*before return 0, iclass 14, count 0 2006.286.03:58:00.86#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:58:00.86#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:58:00.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.03:58:00.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.03:58:00.86$vck44/valo=2,534.99 2006.286.03:58:00.86#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.03:58:00.86#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.03:58:00.86#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:00.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:58:00.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:58:00.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:58:00.86#ibcon#enter wrdev, iclass 16, count 0 2006.286.03:58:00.86#ibcon#first serial, iclass 16, count 0 2006.286.03:58:00.86#ibcon#enter sib2, iclass 16, count 0 2006.286.03:58:00.86#ibcon#flushed, iclass 16, count 0 2006.286.03:58:00.86#ibcon#about to write, iclass 16, count 0 2006.286.03:58:00.86#ibcon#wrote, iclass 16, count 0 2006.286.03:58:00.86#ibcon#about to read 3, iclass 16, count 0 2006.286.03:58:00.88#ibcon#read 3, iclass 16, count 0 2006.286.03:58:00.88#ibcon#about to read 4, iclass 16, count 0 2006.286.03:58:00.88#ibcon#read 4, iclass 16, count 0 2006.286.03:58:00.88#ibcon#about to read 5, iclass 16, count 0 2006.286.03:58:00.88#ibcon#read 5, iclass 16, count 0 2006.286.03:58:00.88#ibcon#about to read 6, iclass 16, count 0 2006.286.03:58:00.88#ibcon#read 6, iclass 16, count 0 2006.286.03:58:00.88#ibcon#end of sib2, iclass 16, count 0 2006.286.03:58:00.88#ibcon#*mode == 0, iclass 16, count 0 2006.286.03:58:00.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.03:58:00.88#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.03:58:00.88#ibcon#*before write, iclass 16, count 0 2006.286.03:58:00.88#ibcon#enter sib2, iclass 16, count 0 2006.286.03:58:00.88#ibcon#flushed, iclass 16, count 0 2006.286.03:58:00.88#ibcon#about to write, iclass 16, count 0 2006.286.03:58:00.88#ibcon#wrote, iclass 16, count 0 2006.286.03:58:00.88#ibcon#about to read 3, iclass 16, count 0 2006.286.03:58:00.92#ibcon#read 3, iclass 16, count 0 2006.286.03:58:00.92#ibcon#about to read 4, iclass 16, count 0 2006.286.03:58:00.92#ibcon#read 4, iclass 16, count 0 2006.286.03:58:00.92#ibcon#about to read 5, iclass 16, count 0 2006.286.03:58:00.92#ibcon#read 5, iclass 16, count 0 2006.286.03:58:00.92#ibcon#about to read 6, iclass 16, count 0 2006.286.03:58:00.92#ibcon#read 6, iclass 16, count 0 2006.286.03:58:00.92#ibcon#end of sib2, iclass 16, count 0 2006.286.03:58:00.92#ibcon#*after write, iclass 16, count 0 2006.286.03:58:00.92#ibcon#*before return 0, iclass 16, count 0 2006.286.03:58:00.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:58:00.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:58:00.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.03:58:00.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.03:58:00.92$vck44/va=2,6 2006.286.03:58:00.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.03:58:00.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.03:58:00.92#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:00.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:58:00.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:58:00.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:58:00.98#ibcon#enter wrdev, iclass 18, count 2 2006.286.03:58:00.98#ibcon#first serial, iclass 18, count 2 2006.286.03:58:00.98#ibcon#enter sib2, iclass 18, count 2 2006.286.03:58:00.98#ibcon#flushed, iclass 18, count 2 2006.286.03:58:00.98#ibcon#about to write, iclass 18, count 2 2006.286.03:58:00.98#ibcon#wrote, iclass 18, count 2 2006.286.03:58:00.98#ibcon#about to read 3, iclass 18, count 2 2006.286.03:58:01.00#ibcon#read 3, iclass 18, count 2 2006.286.03:58:01.00#ibcon#about to read 4, iclass 18, count 2 2006.286.03:58:01.00#ibcon#read 4, iclass 18, count 2 2006.286.03:58:01.00#ibcon#about to read 5, iclass 18, count 2 2006.286.03:58:01.00#ibcon#read 5, iclass 18, count 2 2006.286.03:58:01.00#ibcon#about to read 6, iclass 18, count 2 2006.286.03:58:01.00#ibcon#read 6, iclass 18, count 2 2006.286.03:58:01.00#ibcon#end of sib2, iclass 18, count 2 2006.286.03:58:01.00#ibcon#*mode == 0, iclass 18, count 2 2006.286.03:58:01.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.03:58:01.00#ibcon#[25=AT02-06\r\n] 2006.286.03:58:01.00#ibcon#*before write, iclass 18, count 2 2006.286.03:58:01.00#ibcon#enter sib2, iclass 18, count 2 2006.286.03:58:01.00#ibcon#flushed, iclass 18, count 2 2006.286.03:58:01.00#ibcon#about to write, iclass 18, count 2 2006.286.03:58:01.00#ibcon#wrote, iclass 18, count 2 2006.286.03:58:01.00#ibcon#about to read 3, iclass 18, count 2 2006.286.03:58:01.03#ibcon#read 3, iclass 18, count 2 2006.286.03:58:01.03#ibcon#about to read 4, iclass 18, count 2 2006.286.03:58:01.03#ibcon#read 4, iclass 18, count 2 2006.286.03:58:01.03#ibcon#about to read 5, iclass 18, count 2 2006.286.03:58:01.03#ibcon#read 5, iclass 18, count 2 2006.286.03:58:01.03#ibcon#about to read 6, iclass 18, count 2 2006.286.03:58:01.03#ibcon#read 6, iclass 18, count 2 2006.286.03:58:01.03#ibcon#end of sib2, iclass 18, count 2 2006.286.03:58:01.03#ibcon#*after write, iclass 18, count 2 2006.286.03:58:01.03#ibcon#*before return 0, iclass 18, count 2 2006.286.03:58:01.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:58:01.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:58:01.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.03:58:01.03#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:01.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:58:01.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:58:01.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:58:01.15#ibcon#enter wrdev, iclass 18, count 0 2006.286.03:58:01.15#ibcon#first serial, iclass 18, count 0 2006.286.03:58:01.15#ibcon#enter sib2, iclass 18, count 0 2006.286.03:58:01.15#ibcon#flushed, iclass 18, count 0 2006.286.03:58:01.15#ibcon#about to write, iclass 18, count 0 2006.286.03:58:01.15#ibcon#wrote, iclass 18, count 0 2006.286.03:58:01.15#ibcon#about to read 3, iclass 18, count 0 2006.286.03:58:01.17#ibcon#read 3, iclass 18, count 0 2006.286.03:58:01.17#ibcon#about to read 4, iclass 18, count 0 2006.286.03:58:01.17#ibcon#read 4, iclass 18, count 0 2006.286.03:58:01.17#ibcon#about to read 5, iclass 18, count 0 2006.286.03:58:01.17#ibcon#read 5, iclass 18, count 0 2006.286.03:58:01.17#ibcon#about to read 6, iclass 18, count 0 2006.286.03:58:01.17#ibcon#read 6, iclass 18, count 0 2006.286.03:58:01.17#ibcon#end of sib2, iclass 18, count 0 2006.286.03:58:01.17#ibcon#*mode == 0, iclass 18, count 0 2006.286.03:58:01.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.03:58:01.17#ibcon#[25=USB\r\n] 2006.286.03:58:01.17#ibcon#*before write, iclass 18, count 0 2006.286.03:58:01.17#ibcon#enter sib2, iclass 18, count 0 2006.286.03:58:01.17#ibcon#flushed, iclass 18, count 0 2006.286.03:58:01.17#ibcon#about to write, iclass 18, count 0 2006.286.03:58:01.17#ibcon#wrote, iclass 18, count 0 2006.286.03:58:01.17#ibcon#about to read 3, iclass 18, count 0 2006.286.03:58:01.20#ibcon#read 3, iclass 18, count 0 2006.286.03:58:01.20#ibcon#about to read 4, iclass 18, count 0 2006.286.03:58:01.20#ibcon#read 4, iclass 18, count 0 2006.286.03:58:01.20#ibcon#about to read 5, iclass 18, count 0 2006.286.03:58:01.20#ibcon#read 5, iclass 18, count 0 2006.286.03:58:01.20#ibcon#about to read 6, iclass 18, count 0 2006.286.03:58:01.20#ibcon#read 6, iclass 18, count 0 2006.286.03:58:01.20#ibcon#end of sib2, iclass 18, count 0 2006.286.03:58:01.20#ibcon#*after write, iclass 18, count 0 2006.286.03:58:01.20#ibcon#*before return 0, iclass 18, count 0 2006.286.03:58:01.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:58:01.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:58:01.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.03:58:01.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.03:58:01.20$vck44/valo=3,564.99 2006.286.03:58:01.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.03:58:01.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.03:58:01.20#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:01.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:58:01.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:58:01.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:58:01.20#ibcon#enter wrdev, iclass 20, count 0 2006.286.03:58:01.20#ibcon#first serial, iclass 20, count 0 2006.286.03:58:01.20#ibcon#enter sib2, iclass 20, count 0 2006.286.03:58:01.20#ibcon#flushed, iclass 20, count 0 2006.286.03:58:01.20#ibcon#about to write, iclass 20, count 0 2006.286.03:58:01.20#ibcon#wrote, iclass 20, count 0 2006.286.03:58:01.20#ibcon#about to read 3, iclass 20, count 0 2006.286.03:58:01.22#ibcon#read 3, iclass 20, count 0 2006.286.03:58:01.22#ibcon#about to read 4, iclass 20, count 0 2006.286.03:58:01.22#ibcon#read 4, iclass 20, count 0 2006.286.03:58:01.22#ibcon#about to read 5, iclass 20, count 0 2006.286.03:58:01.22#ibcon#read 5, iclass 20, count 0 2006.286.03:58:01.22#ibcon#about to read 6, iclass 20, count 0 2006.286.03:58:01.22#ibcon#read 6, iclass 20, count 0 2006.286.03:58:01.22#ibcon#end of sib2, iclass 20, count 0 2006.286.03:58:01.22#ibcon#*mode == 0, iclass 20, count 0 2006.286.03:58:01.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.03:58:01.22#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.03:58:01.22#ibcon#*before write, iclass 20, count 0 2006.286.03:58:01.22#ibcon#enter sib2, iclass 20, count 0 2006.286.03:58:01.22#ibcon#flushed, iclass 20, count 0 2006.286.03:58:01.22#ibcon#about to write, iclass 20, count 0 2006.286.03:58:01.22#ibcon#wrote, iclass 20, count 0 2006.286.03:58:01.22#ibcon#about to read 3, iclass 20, count 0 2006.286.03:58:01.26#ibcon#read 3, iclass 20, count 0 2006.286.03:58:01.26#ibcon#about to read 4, iclass 20, count 0 2006.286.03:58:01.26#ibcon#read 4, iclass 20, count 0 2006.286.03:58:01.26#ibcon#about to read 5, iclass 20, count 0 2006.286.03:58:01.26#ibcon#read 5, iclass 20, count 0 2006.286.03:58:01.26#ibcon#about to read 6, iclass 20, count 0 2006.286.03:58:01.26#ibcon#read 6, iclass 20, count 0 2006.286.03:58:01.26#ibcon#end of sib2, iclass 20, count 0 2006.286.03:58:01.26#ibcon#*after write, iclass 20, count 0 2006.286.03:58:01.26#ibcon#*before return 0, iclass 20, count 0 2006.286.03:58:01.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:58:01.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:58:01.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.03:58:01.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.03:58:01.26$vck44/va=3,7 2006.286.03:58:01.26#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.03:58:01.26#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.03:58:01.26#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:01.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:58:01.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:58:01.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:58:01.32#ibcon#enter wrdev, iclass 22, count 2 2006.286.03:58:01.32#ibcon#first serial, iclass 22, count 2 2006.286.03:58:01.32#ibcon#enter sib2, iclass 22, count 2 2006.286.03:58:01.32#ibcon#flushed, iclass 22, count 2 2006.286.03:58:01.32#ibcon#about to write, iclass 22, count 2 2006.286.03:58:01.32#ibcon#wrote, iclass 22, count 2 2006.286.03:58:01.32#ibcon#about to read 3, iclass 22, count 2 2006.286.03:58:01.34#ibcon#read 3, iclass 22, count 2 2006.286.03:58:01.34#ibcon#about to read 4, iclass 22, count 2 2006.286.03:58:01.34#ibcon#read 4, iclass 22, count 2 2006.286.03:58:01.34#ibcon#about to read 5, iclass 22, count 2 2006.286.03:58:01.34#ibcon#read 5, iclass 22, count 2 2006.286.03:58:01.34#ibcon#about to read 6, iclass 22, count 2 2006.286.03:58:01.34#ibcon#read 6, iclass 22, count 2 2006.286.03:58:01.34#ibcon#end of sib2, iclass 22, count 2 2006.286.03:58:01.34#ibcon#*mode == 0, iclass 22, count 2 2006.286.03:58:01.34#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.03:58:01.34#ibcon#[25=AT03-07\r\n] 2006.286.03:58:01.34#ibcon#*before write, iclass 22, count 2 2006.286.03:58:01.34#ibcon#enter sib2, iclass 22, count 2 2006.286.03:58:01.34#ibcon#flushed, iclass 22, count 2 2006.286.03:58:01.34#ibcon#about to write, iclass 22, count 2 2006.286.03:58:01.34#ibcon#wrote, iclass 22, count 2 2006.286.03:58:01.34#ibcon#about to read 3, iclass 22, count 2 2006.286.03:58:01.37#ibcon#read 3, iclass 22, count 2 2006.286.03:58:01.37#ibcon#about to read 4, iclass 22, count 2 2006.286.03:58:01.37#ibcon#read 4, iclass 22, count 2 2006.286.03:58:01.37#ibcon#about to read 5, iclass 22, count 2 2006.286.03:58:01.37#ibcon#read 5, iclass 22, count 2 2006.286.03:58:01.37#ibcon#about to read 6, iclass 22, count 2 2006.286.03:58:01.37#ibcon#read 6, iclass 22, count 2 2006.286.03:58:01.37#ibcon#end of sib2, iclass 22, count 2 2006.286.03:58:01.37#ibcon#*after write, iclass 22, count 2 2006.286.03:58:01.37#ibcon#*before return 0, iclass 22, count 2 2006.286.03:58:01.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:58:01.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:58:01.37#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.03:58:01.37#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:01.37#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:58:01.49#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:58:01.49#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:58:01.49#ibcon#enter wrdev, iclass 22, count 0 2006.286.03:58:01.49#ibcon#first serial, iclass 22, count 0 2006.286.03:58:01.49#ibcon#enter sib2, iclass 22, count 0 2006.286.03:58:01.49#ibcon#flushed, iclass 22, count 0 2006.286.03:58:01.49#ibcon#about to write, iclass 22, count 0 2006.286.03:58:01.49#ibcon#wrote, iclass 22, count 0 2006.286.03:58:01.49#ibcon#about to read 3, iclass 22, count 0 2006.286.03:58:01.51#ibcon#read 3, iclass 22, count 0 2006.286.03:58:01.51#ibcon#about to read 4, iclass 22, count 0 2006.286.03:58:01.51#ibcon#read 4, iclass 22, count 0 2006.286.03:58:01.51#ibcon#about to read 5, iclass 22, count 0 2006.286.03:58:01.51#ibcon#read 5, iclass 22, count 0 2006.286.03:58:01.51#ibcon#about to read 6, iclass 22, count 0 2006.286.03:58:01.51#ibcon#read 6, iclass 22, count 0 2006.286.03:58:01.51#ibcon#end of sib2, iclass 22, count 0 2006.286.03:58:01.51#ibcon#*mode == 0, iclass 22, count 0 2006.286.03:58:01.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.03:58:01.51#ibcon#[25=USB\r\n] 2006.286.03:58:01.51#ibcon#*before write, iclass 22, count 0 2006.286.03:58:01.51#ibcon#enter sib2, iclass 22, count 0 2006.286.03:58:01.51#ibcon#flushed, iclass 22, count 0 2006.286.03:58:01.51#ibcon#about to write, iclass 22, count 0 2006.286.03:58:01.51#ibcon#wrote, iclass 22, count 0 2006.286.03:58:01.51#ibcon#about to read 3, iclass 22, count 0 2006.286.03:58:01.54#ibcon#read 3, iclass 22, count 0 2006.286.03:58:01.54#ibcon#about to read 4, iclass 22, count 0 2006.286.03:58:01.54#ibcon#read 4, iclass 22, count 0 2006.286.03:58:01.54#ibcon#about to read 5, iclass 22, count 0 2006.286.03:58:01.54#ibcon#read 5, iclass 22, count 0 2006.286.03:58:01.54#ibcon#about to read 6, iclass 22, count 0 2006.286.03:58:01.54#ibcon#read 6, iclass 22, count 0 2006.286.03:58:01.54#ibcon#end of sib2, iclass 22, count 0 2006.286.03:58:01.54#ibcon#*after write, iclass 22, count 0 2006.286.03:58:01.54#ibcon#*before return 0, iclass 22, count 0 2006.286.03:58:01.54#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:58:01.54#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:58:01.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.03:58:01.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.03:58:01.54$vck44/valo=4,624.99 2006.286.03:58:01.54#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.03:58:01.54#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.03:58:01.54#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:01.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:58:01.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:58:01.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:58:01.54#ibcon#enter wrdev, iclass 24, count 0 2006.286.03:58:01.54#ibcon#first serial, iclass 24, count 0 2006.286.03:58:01.54#ibcon#enter sib2, iclass 24, count 0 2006.286.03:58:01.54#ibcon#flushed, iclass 24, count 0 2006.286.03:58:01.54#ibcon#about to write, iclass 24, count 0 2006.286.03:58:01.54#ibcon#wrote, iclass 24, count 0 2006.286.03:58:01.54#ibcon#about to read 3, iclass 24, count 0 2006.286.03:58:01.56#ibcon#read 3, iclass 24, count 0 2006.286.03:58:01.56#ibcon#about to read 4, iclass 24, count 0 2006.286.03:58:01.56#ibcon#read 4, iclass 24, count 0 2006.286.03:58:01.56#ibcon#about to read 5, iclass 24, count 0 2006.286.03:58:01.56#ibcon#read 5, iclass 24, count 0 2006.286.03:58:01.56#ibcon#about to read 6, iclass 24, count 0 2006.286.03:58:01.56#ibcon#read 6, iclass 24, count 0 2006.286.03:58:01.56#ibcon#end of sib2, iclass 24, count 0 2006.286.03:58:01.56#ibcon#*mode == 0, iclass 24, count 0 2006.286.03:58:01.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.03:58:01.56#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.03:58:01.56#ibcon#*before write, iclass 24, count 0 2006.286.03:58:01.56#ibcon#enter sib2, iclass 24, count 0 2006.286.03:58:01.56#ibcon#flushed, iclass 24, count 0 2006.286.03:58:01.56#ibcon#about to write, iclass 24, count 0 2006.286.03:58:01.56#ibcon#wrote, iclass 24, count 0 2006.286.03:58:01.56#ibcon#about to read 3, iclass 24, count 0 2006.286.03:58:01.60#ibcon#read 3, iclass 24, count 0 2006.286.03:58:01.60#ibcon#about to read 4, iclass 24, count 0 2006.286.03:58:01.60#ibcon#read 4, iclass 24, count 0 2006.286.03:58:01.60#ibcon#about to read 5, iclass 24, count 0 2006.286.03:58:01.60#ibcon#read 5, iclass 24, count 0 2006.286.03:58:01.60#ibcon#about to read 6, iclass 24, count 0 2006.286.03:58:01.60#ibcon#read 6, iclass 24, count 0 2006.286.03:58:01.60#ibcon#end of sib2, iclass 24, count 0 2006.286.03:58:01.60#ibcon#*after write, iclass 24, count 0 2006.286.03:58:01.60#ibcon#*before return 0, iclass 24, count 0 2006.286.03:58:01.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:58:01.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:58:01.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.03:58:01.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.03:58:01.60$vck44/va=4,6 2006.286.03:58:01.60#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.03:58:01.60#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.03:58:01.60#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:01.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:58:01.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:58:01.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:58:01.66#ibcon#enter wrdev, iclass 26, count 2 2006.286.03:58:01.66#ibcon#first serial, iclass 26, count 2 2006.286.03:58:01.66#ibcon#enter sib2, iclass 26, count 2 2006.286.03:58:01.66#ibcon#flushed, iclass 26, count 2 2006.286.03:58:01.66#ibcon#about to write, iclass 26, count 2 2006.286.03:58:01.66#ibcon#wrote, iclass 26, count 2 2006.286.03:58:01.66#ibcon#about to read 3, iclass 26, count 2 2006.286.03:58:01.68#ibcon#read 3, iclass 26, count 2 2006.286.03:58:01.68#ibcon#about to read 4, iclass 26, count 2 2006.286.03:58:01.68#ibcon#read 4, iclass 26, count 2 2006.286.03:58:01.68#ibcon#about to read 5, iclass 26, count 2 2006.286.03:58:01.68#ibcon#read 5, iclass 26, count 2 2006.286.03:58:01.68#ibcon#about to read 6, iclass 26, count 2 2006.286.03:58:01.68#ibcon#read 6, iclass 26, count 2 2006.286.03:58:01.68#ibcon#end of sib2, iclass 26, count 2 2006.286.03:58:01.68#ibcon#*mode == 0, iclass 26, count 2 2006.286.03:58:01.68#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.03:58:01.68#ibcon#[25=AT04-06\r\n] 2006.286.03:58:01.68#ibcon#*before write, iclass 26, count 2 2006.286.03:58:01.68#ibcon#enter sib2, iclass 26, count 2 2006.286.03:58:01.68#ibcon#flushed, iclass 26, count 2 2006.286.03:58:01.68#ibcon#about to write, iclass 26, count 2 2006.286.03:58:01.68#ibcon#wrote, iclass 26, count 2 2006.286.03:58:01.68#ibcon#about to read 3, iclass 26, count 2 2006.286.03:58:01.71#ibcon#read 3, iclass 26, count 2 2006.286.03:58:01.97#ibcon#about to read 4, iclass 26, count 2 2006.286.03:58:01.97#ibcon#read 4, iclass 26, count 2 2006.286.03:58:01.97#ibcon#about to read 5, iclass 26, count 2 2006.286.03:58:01.97#ibcon#read 5, iclass 26, count 2 2006.286.03:58:01.97#ibcon#about to read 6, iclass 26, count 2 2006.286.03:58:01.97#ibcon#read 6, iclass 26, count 2 2006.286.03:58:01.97#ibcon#end of sib2, iclass 26, count 2 2006.286.03:58:01.97#ibcon#*after write, iclass 26, count 2 2006.286.03:58:01.97#ibcon#*before return 0, iclass 26, count 2 2006.286.03:58:01.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:58:01.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:58:01.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.03:58:01.97#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:01.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:58:02.08#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:58:02.08#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:58:02.08#ibcon#enter wrdev, iclass 26, count 0 2006.286.03:58:02.08#ibcon#first serial, iclass 26, count 0 2006.286.03:58:02.08#ibcon#enter sib2, iclass 26, count 0 2006.286.03:58:02.08#ibcon#flushed, iclass 26, count 0 2006.286.03:58:02.08#ibcon#about to write, iclass 26, count 0 2006.286.03:58:02.08#ibcon#wrote, iclass 26, count 0 2006.286.03:58:02.08#ibcon#about to read 3, iclass 26, count 0 2006.286.03:58:02.10#ibcon#read 3, iclass 26, count 0 2006.286.03:58:02.10#ibcon#about to read 4, iclass 26, count 0 2006.286.03:58:02.10#ibcon#read 4, iclass 26, count 0 2006.286.03:58:02.10#ibcon#about to read 5, iclass 26, count 0 2006.286.03:58:02.10#ibcon#read 5, iclass 26, count 0 2006.286.03:58:02.10#ibcon#about to read 6, iclass 26, count 0 2006.286.03:58:02.10#ibcon#read 6, iclass 26, count 0 2006.286.03:58:02.10#ibcon#end of sib2, iclass 26, count 0 2006.286.03:58:02.10#ibcon#*mode == 0, iclass 26, count 0 2006.286.03:58:02.10#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.03:58:02.10#ibcon#[25=USB\r\n] 2006.286.03:58:02.10#ibcon#*before write, iclass 26, count 0 2006.286.03:58:02.10#ibcon#enter sib2, iclass 26, count 0 2006.286.03:58:02.10#ibcon#flushed, iclass 26, count 0 2006.286.03:58:02.10#ibcon#about to write, iclass 26, count 0 2006.286.03:58:02.10#ibcon#wrote, iclass 26, count 0 2006.286.03:58:02.10#ibcon#about to read 3, iclass 26, count 0 2006.286.03:58:02.13#ibcon#read 3, iclass 26, count 0 2006.286.03:58:02.13#ibcon#about to read 4, iclass 26, count 0 2006.286.03:58:02.13#ibcon#read 4, iclass 26, count 0 2006.286.03:58:02.13#ibcon#about to read 5, iclass 26, count 0 2006.286.03:58:02.13#ibcon#read 5, iclass 26, count 0 2006.286.03:58:02.13#ibcon#about to read 6, iclass 26, count 0 2006.286.03:58:02.13#ibcon#read 6, iclass 26, count 0 2006.286.03:58:02.13#ibcon#end of sib2, iclass 26, count 0 2006.286.03:58:02.13#ibcon#*after write, iclass 26, count 0 2006.286.03:58:02.13#ibcon#*before return 0, iclass 26, count 0 2006.286.03:58:02.13#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:58:02.13#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:58:02.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.03:58:02.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.03:58:02.13$vck44/valo=5,734.99 2006.286.03:58:02.13#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.03:58:02.13#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.03:58:02.13#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:02.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:58:02.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:58:02.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:58:02.13#ibcon#enter wrdev, iclass 28, count 0 2006.286.03:58:02.13#ibcon#first serial, iclass 28, count 0 2006.286.03:58:02.13#ibcon#enter sib2, iclass 28, count 0 2006.286.03:58:02.13#ibcon#flushed, iclass 28, count 0 2006.286.03:58:02.13#ibcon#about to write, iclass 28, count 0 2006.286.03:58:02.13#ibcon#wrote, iclass 28, count 0 2006.286.03:58:02.13#ibcon#about to read 3, iclass 28, count 0 2006.286.03:58:02.15#ibcon#read 3, iclass 28, count 0 2006.286.03:58:02.15#ibcon#about to read 4, iclass 28, count 0 2006.286.03:58:02.15#ibcon#read 4, iclass 28, count 0 2006.286.03:58:02.15#ibcon#about to read 5, iclass 28, count 0 2006.286.03:58:02.15#ibcon#read 5, iclass 28, count 0 2006.286.03:58:02.15#ibcon#about to read 6, iclass 28, count 0 2006.286.03:58:02.15#ibcon#read 6, iclass 28, count 0 2006.286.03:58:02.15#ibcon#end of sib2, iclass 28, count 0 2006.286.03:58:02.15#ibcon#*mode == 0, iclass 28, count 0 2006.286.03:58:02.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.03:58:02.15#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.03:58:02.15#ibcon#*before write, iclass 28, count 0 2006.286.03:58:02.15#ibcon#enter sib2, iclass 28, count 0 2006.286.03:58:02.15#ibcon#flushed, iclass 28, count 0 2006.286.03:58:02.15#ibcon#about to write, iclass 28, count 0 2006.286.03:58:02.15#ibcon#wrote, iclass 28, count 0 2006.286.03:58:02.15#ibcon#about to read 3, iclass 28, count 0 2006.286.03:58:02.19#ibcon#read 3, iclass 28, count 0 2006.286.03:58:02.19#ibcon#about to read 4, iclass 28, count 0 2006.286.03:58:02.19#ibcon#read 4, iclass 28, count 0 2006.286.03:58:02.19#ibcon#about to read 5, iclass 28, count 0 2006.286.03:58:02.19#ibcon#read 5, iclass 28, count 0 2006.286.03:58:02.19#ibcon#about to read 6, iclass 28, count 0 2006.286.03:58:02.19#ibcon#read 6, iclass 28, count 0 2006.286.03:58:02.19#ibcon#end of sib2, iclass 28, count 0 2006.286.03:58:02.19#ibcon#*after write, iclass 28, count 0 2006.286.03:58:02.19#ibcon#*before return 0, iclass 28, count 0 2006.286.03:58:02.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:58:02.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:58:02.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.03:58:02.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.03:58:02.19$vck44/va=5,3 2006.286.03:58:02.19#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.03:58:02.19#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.03:58:02.19#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:02.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:58:02.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:58:02.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:58:02.25#ibcon#enter wrdev, iclass 30, count 2 2006.286.03:58:02.25#ibcon#first serial, iclass 30, count 2 2006.286.03:58:02.25#ibcon#enter sib2, iclass 30, count 2 2006.286.03:58:02.25#ibcon#flushed, iclass 30, count 2 2006.286.03:58:02.25#ibcon#about to write, iclass 30, count 2 2006.286.03:58:02.25#ibcon#wrote, iclass 30, count 2 2006.286.03:58:02.25#ibcon#about to read 3, iclass 30, count 2 2006.286.03:58:02.27#ibcon#read 3, iclass 30, count 2 2006.286.03:58:02.27#ibcon#about to read 4, iclass 30, count 2 2006.286.03:58:02.27#ibcon#read 4, iclass 30, count 2 2006.286.03:58:02.27#ibcon#about to read 5, iclass 30, count 2 2006.286.03:58:02.27#ibcon#read 5, iclass 30, count 2 2006.286.03:58:02.27#ibcon#about to read 6, iclass 30, count 2 2006.286.03:58:02.27#ibcon#read 6, iclass 30, count 2 2006.286.03:58:02.27#ibcon#end of sib2, iclass 30, count 2 2006.286.03:58:02.27#ibcon#*mode == 0, iclass 30, count 2 2006.286.03:58:02.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.03:58:02.27#ibcon#[25=AT05-03\r\n] 2006.286.03:58:02.27#ibcon#*before write, iclass 30, count 2 2006.286.03:58:02.27#ibcon#enter sib2, iclass 30, count 2 2006.286.03:58:02.27#ibcon#flushed, iclass 30, count 2 2006.286.03:58:02.27#ibcon#about to write, iclass 30, count 2 2006.286.03:58:02.27#ibcon#wrote, iclass 30, count 2 2006.286.03:58:02.27#ibcon#about to read 3, iclass 30, count 2 2006.286.03:58:02.30#ibcon#read 3, iclass 30, count 2 2006.286.03:58:02.30#ibcon#about to read 4, iclass 30, count 2 2006.286.03:58:02.30#ibcon#read 4, iclass 30, count 2 2006.286.03:58:02.30#ibcon#about to read 5, iclass 30, count 2 2006.286.03:58:02.30#ibcon#read 5, iclass 30, count 2 2006.286.03:58:02.30#ibcon#about to read 6, iclass 30, count 2 2006.286.03:58:02.30#ibcon#read 6, iclass 30, count 2 2006.286.03:58:02.30#ibcon#end of sib2, iclass 30, count 2 2006.286.03:58:02.30#ibcon#*after write, iclass 30, count 2 2006.286.03:58:02.30#ibcon#*before return 0, iclass 30, count 2 2006.286.03:58:02.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:58:02.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:58:02.30#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.03:58:02.30#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:02.30#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:58:02.42#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:58:02.42#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:58:02.42#ibcon#enter wrdev, iclass 30, count 0 2006.286.03:58:02.42#ibcon#first serial, iclass 30, count 0 2006.286.03:58:02.42#ibcon#enter sib2, iclass 30, count 0 2006.286.03:58:02.42#ibcon#flushed, iclass 30, count 0 2006.286.03:58:02.42#ibcon#about to write, iclass 30, count 0 2006.286.03:58:02.42#ibcon#wrote, iclass 30, count 0 2006.286.03:58:02.42#ibcon#about to read 3, iclass 30, count 0 2006.286.03:58:02.44#ibcon#read 3, iclass 30, count 0 2006.286.03:58:02.44#ibcon#about to read 4, iclass 30, count 0 2006.286.03:58:02.44#ibcon#read 4, iclass 30, count 0 2006.286.03:58:02.44#ibcon#about to read 5, iclass 30, count 0 2006.286.03:58:02.44#ibcon#read 5, iclass 30, count 0 2006.286.03:58:02.44#ibcon#about to read 6, iclass 30, count 0 2006.286.03:58:02.44#ibcon#read 6, iclass 30, count 0 2006.286.03:58:02.44#ibcon#end of sib2, iclass 30, count 0 2006.286.03:58:02.44#ibcon#*mode == 0, iclass 30, count 0 2006.286.03:58:02.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.03:58:02.44#ibcon#[25=USB\r\n] 2006.286.03:58:02.44#ibcon#*before write, iclass 30, count 0 2006.286.03:58:02.44#ibcon#enter sib2, iclass 30, count 0 2006.286.03:58:02.44#ibcon#flushed, iclass 30, count 0 2006.286.03:58:02.44#ibcon#about to write, iclass 30, count 0 2006.286.03:58:02.44#ibcon#wrote, iclass 30, count 0 2006.286.03:58:02.44#ibcon#about to read 3, iclass 30, count 0 2006.286.03:58:02.47#ibcon#read 3, iclass 30, count 0 2006.286.03:58:02.47#ibcon#about to read 4, iclass 30, count 0 2006.286.03:58:02.47#ibcon#read 4, iclass 30, count 0 2006.286.03:58:02.47#ibcon#about to read 5, iclass 30, count 0 2006.286.03:58:02.47#ibcon#read 5, iclass 30, count 0 2006.286.03:58:02.47#ibcon#about to read 6, iclass 30, count 0 2006.286.03:58:02.47#ibcon#read 6, iclass 30, count 0 2006.286.03:58:02.47#ibcon#end of sib2, iclass 30, count 0 2006.286.03:58:02.47#ibcon#*after write, iclass 30, count 0 2006.286.03:58:02.47#ibcon#*before return 0, iclass 30, count 0 2006.286.03:58:02.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:58:02.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:58:02.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.03:58:02.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.03:58:02.47$vck44/valo=6,814.99 2006.286.03:58:02.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.03:58:02.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.03:58:02.47#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:02.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:58:02.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:58:02.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:58:02.47#ibcon#enter wrdev, iclass 32, count 0 2006.286.03:58:02.47#ibcon#first serial, iclass 32, count 0 2006.286.03:58:02.47#ibcon#enter sib2, iclass 32, count 0 2006.286.03:58:02.47#ibcon#flushed, iclass 32, count 0 2006.286.03:58:02.81#ibcon#about to write, iclass 32, count 0 2006.286.03:58:02.81#ibcon#wrote, iclass 32, count 0 2006.286.03:58:02.81#ibcon#about to read 3, iclass 32, count 0 2006.286.03:58:02.82#ibcon#read 3, iclass 32, count 0 2006.286.03:58:02.82#ibcon#about to read 4, iclass 32, count 0 2006.286.03:58:02.82#ibcon#read 4, iclass 32, count 0 2006.286.03:58:02.82#ibcon#about to read 5, iclass 32, count 0 2006.286.03:58:02.82#ibcon#read 5, iclass 32, count 0 2006.286.03:58:02.82#ibcon#about to read 6, iclass 32, count 0 2006.286.03:58:02.82#ibcon#read 6, iclass 32, count 0 2006.286.03:58:02.82#ibcon#end of sib2, iclass 32, count 0 2006.286.03:58:02.82#ibcon#*mode == 0, iclass 32, count 0 2006.286.03:58:02.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.03:58:02.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.03:58:02.82#ibcon#*before write, iclass 32, count 0 2006.286.03:58:02.82#ibcon#enter sib2, iclass 32, count 0 2006.286.03:58:02.82#ibcon#flushed, iclass 32, count 0 2006.286.03:58:02.82#ibcon#about to write, iclass 32, count 0 2006.286.03:58:02.82#ibcon#wrote, iclass 32, count 0 2006.286.03:58:02.82#ibcon#about to read 3, iclass 32, count 0 2006.286.03:58:02.86#ibcon#read 3, iclass 32, count 0 2006.286.03:58:02.86#ibcon#about to read 4, iclass 32, count 0 2006.286.03:58:02.86#ibcon#read 4, iclass 32, count 0 2006.286.03:58:02.86#ibcon#about to read 5, iclass 32, count 0 2006.286.03:58:02.86#ibcon#read 5, iclass 32, count 0 2006.286.03:58:02.86#ibcon#about to read 6, iclass 32, count 0 2006.286.03:58:02.86#ibcon#read 6, iclass 32, count 0 2006.286.03:58:02.86#ibcon#end of sib2, iclass 32, count 0 2006.286.03:58:02.86#ibcon#*after write, iclass 32, count 0 2006.286.03:58:02.86#ibcon#*before return 0, iclass 32, count 0 2006.286.03:58:02.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:58:02.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:58:02.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.03:58:02.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.03:58:02.86$vck44/va=6,4 2006.286.03:58:02.86#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.03:58:02.86#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.03:58:02.86#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:02.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:58:02.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:58:02.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:58:02.86#ibcon#enter wrdev, iclass 34, count 2 2006.286.03:58:02.86#ibcon#first serial, iclass 34, count 2 2006.286.03:58:02.86#ibcon#enter sib2, iclass 34, count 2 2006.286.03:58:02.86#ibcon#flushed, iclass 34, count 2 2006.286.03:58:02.86#ibcon#about to write, iclass 34, count 2 2006.286.03:58:02.86#ibcon#wrote, iclass 34, count 2 2006.286.03:58:02.86#ibcon#about to read 3, iclass 34, count 2 2006.286.03:58:02.88#ibcon#read 3, iclass 34, count 2 2006.286.03:58:02.88#ibcon#about to read 4, iclass 34, count 2 2006.286.03:58:02.88#ibcon#read 4, iclass 34, count 2 2006.286.03:58:02.88#ibcon#about to read 5, iclass 34, count 2 2006.286.03:58:02.88#ibcon#read 5, iclass 34, count 2 2006.286.03:58:02.88#ibcon#about to read 6, iclass 34, count 2 2006.286.03:58:02.88#ibcon#read 6, iclass 34, count 2 2006.286.03:58:02.88#ibcon#end of sib2, iclass 34, count 2 2006.286.03:58:02.88#ibcon#*mode == 0, iclass 34, count 2 2006.286.03:58:02.88#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.03:58:02.88#ibcon#[25=AT06-04\r\n] 2006.286.03:58:02.88#ibcon#*before write, iclass 34, count 2 2006.286.03:58:02.88#ibcon#enter sib2, iclass 34, count 2 2006.286.03:58:02.88#ibcon#flushed, iclass 34, count 2 2006.286.03:58:02.88#ibcon#about to write, iclass 34, count 2 2006.286.03:58:02.88#ibcon#wrote, iclass 34, count 2 2006.286.03:58:02.88#ibcon#about to read 3, iclass 34, count 2 2006.286.03:58:02.91#ibcon#read 3, iclass 34, count 2 2006.286.03:58:02.91#ibcon#about to read 4, iclass 34, count 2 2006.286.03:58:02.91#ibcon#read 4, iclass 34, count 2 2006.286.03:58:02.91#ibcon#about to read 5, iclass 34, count 2 2006.286.03:58:02.91#ibcon#read 5, iclass 34, count 2 2006.286.03:58:02.91#ibcon#about to read 6, iclass 34, count 2 2006.286.03:58:02.91#ibcon#read 6, iclass 34, count 2 2006.286.03:58:02.91#ibcon#end of sib2, iclass 34, count 2 2006.286.03:58:02.91#ibcon#*after write, iclass 34, count 2 2006.286.03:58:02.91#ibcon#*before return 0, iclass 34, count 2 2006.286.03:58:02.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:58:02.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:58:02.91#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.03:58:02.91#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:02.91#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:58:03.03#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:58:03.03#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:58:03.03#ibcon#enter wrdev, iclass 34, count 0 2006.286.03:58:03.03#ibcon#first serial, iclass 34, count 0 2006.286.03:58:03.03#ibcon#enter sib2, iclass 34, count 0 2006.286.03:58:03.03#ibcon#flushed, iclass 34, count 0 2006.286.03:58:03.03#ibcon#about to write, iclass 34, count 0 2006.286.03:58:03.03#ibcon#wrote, iclass 34, count 0 2006.286.03:58:03.03#ibcon#about to read 3, iclass 34, count 0 2006.286.03:58:03.05#ibcon#read 3, iclass 34, count 0 2006.286.03:58:03.05#ibcon#about to read 4, iclass 34, count 0 2006.286.03:58:03.05#ibcon#read 4, iclass 34, count 0 2006.286.03:58:03.05#ibcon#about to read 5, iclass 34, count 0 2006.286.03:58:03.05#ibcon#read 5, iclass 34, count 0 2006.286.03:58:03.05#ibcon#about to read 6, iclass 34, count 0 2006.286.03:58:03.05#ibcon#read 6, iclass 34, count 0 2006.286.03:58:03.05#ibcon#end of sib2, iclass 34, count 0 2006.286.03:58:03.05#ibcon#*mode == 0, iclass 34, count 0 2006.286.03:58:03.05#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.03:58:03.05#ibcon#[25=USB\r\n] 2006.286.03:58:03.05#ibcon#*before write, iclass 34, count 0 2006.286.03:58:03.05#ibcon#enter sib2, iclass 34, count 0 2006.286.03:58:03.05#ibcon#flushed, iclass 34, count 0 2006.286.03:58:03.05#ibcon#about to write, iclass 34, count 0 2006.286.03:58:03.05#ibcon#wrote, iclass 34, count 0 2006.286.03:58:03.05#ibcon#about to read 3, iclass 34, count 0 2006.286.03:58:03.08#ibcon#read 3, iclass 34, count 0 2006.286.03:58:03.08#ibcon#about to read 4, iclass 34, count 0 2006.286.03:58:03.08#ibcon#read 4, iclass 34, count 0 2006.286.03:58:03.08#ibcon#about to read 5, iclass 34, count 0 2006.286.03:58:03.08#ibcon#read 5, iclass 34, count 0 2006.286.03:58:03.08#ibcon#about to read 6, iclass 34, count 0 2006.286.03:58:03.08#ibcon#read 6, iclass 34, count 0 2006.286.03:58:03.08#ibcon#end of sib2, iclass 34, count 0 2006.286.03:58:03.08#ibcon#*after write, iclass 34, count 0 2006.286.03:58:03.08#ibcon#*before return 0, iclass 34, count 0 2006.286.03:58:03.08#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:58:03.08#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:58:03.08#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.03:58:03.08#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.03:58:03.08$vck44/valo=7,864.99 2006.286.03:58:03.08#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.03:58:03.08#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.03:58:03.08#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:03.08#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:58:03.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:58:03.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:58:03.08#ibcon#enter wrdev, iclass 36, count 0 2006.286.03:58:03.08#ibcon#first serial, iclass 36, count 0 2006.286.03:58:03.08#ibcon#enter sib2, iclass 36, count 0 2006.286.03:58:03.08#ibcon#flushed, iclass 36, count 0 2006.286.03:58:03.34#ibcon#about to write, iclass 36, count 0 2006.286.03:58:03.34#ibcon#wrote, iclass 36, count 0 2006.286.03:58:03.34#ibcon#about to read 3, iclass 36, count 0 2006.286.03:58:03.35#ibcon#read 3, iclass 36, count 0 2006.286.03:58:03.35#ibcon#about to read 4, iclass 36, count 0 2006.286.03:58:03.35#ibcon#read 4, iclass 36, count 0 2006.286.03:58:03.35#ibcon#about to read 5, iclass 36, count 0 2006.286.03:58:03.35#ibcon#read 5, iclass 36, count 0 2006.286.03:58:03.35#ibcon#about to read 6, iclass 36, count 0 2006.286.03:58:03.35#ibcon#read 6, iclass 36, count 0 2006.286.03:58:03.35#ibcon#end of sib2, iclass 36, count 0 2006.286.03:58:03.35#ibcon#*mode == 0, iclass 36, count 0 2006.286.03:58:03.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.03:58:03.35#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.03:58:03.35#ibcon#*before write, iclass 36, count 0 2006.286.03:58:03.35#ibcon#enter sib2, iclass 36, count 0 2006.286.03:58:03.35#ibcon#flushed, iclass 36, count 0 2006.286.03:58:03.35#ibcon#about to write, iclass 36, count 0 2006.286.03:58:03.35#ibcon#wrote, iclass 36, count 0 2006.286.03:58:03.35#ibcon#about to read 3, iclass 36, count 0 2006.286.03:58:03.39#ibcon#read 3, iclass 36, count 0 2006.286.03:58:03.39#ibcon#about to read 4, iclass 36, count 0 2006.286.03:58:03.39#ibcon#read 4, iclass 36, count 0 2006.286.03:58:03.39#ibcon#about to read 5, iclass 36, count 0 2006.286.03:58:03.39#ibcon#read 5, iclass 36, count 0 2006.286.03:58:03.39#ibcon#about to read 6, iclass 36, count 0 2006.286.03:58:03.39#ibcon#read 6, iclass 36, count 0 2006.286.03:58:03.39#ibcon#end of sib2, iclass 36, count 0 2006.286.03:58:03.39#ibcon#*after write, iclass 36, count 0 2006.286.03:58:03.39#ibcon#*before return 0, iclass 36, count 0 2006.286.03:58:03.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:58:03.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:58:03.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.03:58:03.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.03:58:03.39$vck44/va=7,4 2006.286.03:58:03.39#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.03:58:03.39#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.03:58:03.39#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:03.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:58:03.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:58:03.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:58:03.39#ibcon#enter wrdev, iclass 38, count 2 2006.286.03:58:03.39#ibcon#first serial, iclass 38, count 2 2006.286.03:58:03.39#ibcon#enter sib2, iclass 38, count 2 2006.286.03:58:03.39#ibcon#flushed, iclass 38, count 2 2006.286.03:58:03.39#ibcon#about to write, iclass 38, count 2 2006.286.03:58:03.39#ibcon#wrote, iclass 38, count 2 2006.286.03:58:03.39#ibcon#about to read 3, iclass 38, count 2 2006.286.03:58:03.41#ibcon#read 3, iclass 38, count 2 2006.286.03:58:03.41#ibcon#about to read 4, iclass 38, count 2 2006.286.03:58:03.41#ibcon#read 4, iclass 38, count 2 2006.286.03:58:03.41#ibcon#about to read 5, iclass 38, count 2 2006.286.03:58:03.41#ibcon#read 5, iclass 38, count 2 2006.286.03:58:03.41#ibcon#about to read 6, iclass 38, count 2 2006.286.03:58:03.41#ibcon#read 6, iclass 38, count 2 2006.286.03:58:03.41#ibcon#end of sib2, iclass 38, count 2 2006.286.03:58:03.41#ibcon#*mode == 0, iclass 38, count 2 2006.286.03:58:03.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.03:58:03.41#ibcon#[25=AT07-04\r\n] 2006.286.03:58:03.41#ibcon#*before write, iclass 38, count 2 2006.286.03:58:03.41#ibcon#enter sib2, iclass 38, count 2 2006.286.03:58:03.41#ibcon#flushed, iclass 38, count 2 2006.286.03:58:03.41#ibcon#about to write, iclass 38, count 2 2006.286.03:58:03.41#ibcon#wrote, iclass 38, count 2 2006.286.03:58:03.41#ibcon#about to read 3, iclass 38, count 2 2006.286.03:58:03.44#ibcon#read 3, iclass 38, count 2 2006.286.03:58:03.44#ibcon#about to read 4, iclass 38, count 2 2006.286.03:58:03.44#ibcon#read 4, iclass 38, count 2 2006.286.03:58:03.44#ibcon#about to read 5, iclass 38, count 2 2006.286.03:58:03.44#ibcon#read 5, iclass 38, count 2 2006.286.03:58:03.44#ibcon#about to read 6, iclass 38, count 2 2006.286.03:58:03.44#ibcon#read 6, iclass 38, count 2 2006.286.03:58:03.44#ibcon#end of sib2, iclass 38, count 2 2006.286.03:58:03.44#ibcon#*after write, iclass 38, count 2 2006.286.03:58:03.44#ibcon#*before return 0, iclass 38, count 2 2006.286.03:58:03.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:58:03.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:58:03.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.03:58:03.44#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:03.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:58:03.47#abcon#<5=/04 3.6 6.9 21.86 761015.0\r\n> 2006.286.03:58:03.49#abcon#{5=INTERFACE CLEAR} 2006.286.03:58:03.55#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:58:03.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:58:03.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:58:03.56#ibcon#enter wrdev, iclass 38, count 0 2006.286.03:58:03.56#ibcon#first serial, iclass 38, count 0 2006.286.03:58:03.56#ibcon#enter sib2, iclass 38, count 0 2006.286.03:58:03.56#ibcon#flushed, iclass 38, count 0 2006.286.03:58:03.56#ibcon#about to write, iclass 38, count 0 2006.286.03:58:03.56#ibcon#wrote, iclass 38, count 0 2006.286.03:58:03.56#ibcon#about to read 3, iclass 38, count 0 2006.286.03:58:03.58#ibcon#read 3, iclass 38, count 0 2006.286.03:58:03.58#ibcon#about to read 4, iclass 38, count 0 2006.286.03:58:03.58#ibcon#read 4, iclass 38, count 0 2006.286.03:58:03.58#ibcon#about to read 5, iclass 38, count 0 2006.286.03:58:03.58#ibcon#read 5, iclass 38, count 0 2006.286.03:58:03.58#ibcon#about to read 6, iclass 38, count 0 2006.286.03:58:03.58#ibcon#read 6, iclass 38, count 0 2006.286.03:58:03.58#ibcon#end of sib2, iclass 38, count 0 2006.286.03:58:03.58#ibcon#*mode == 0, iclass 38, count 0 2006.286.03:58:03.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.03:58:03.58#ibcon#[25=USB\r\n] 2006.286.03:58:03.58#ibcon#*before write, iclass 38, count 0 2006.286.03:58:03.58#ibcon#enter sib2, iclass 38, count 0 2006.286.03:58:03.58#ibcon#flushed, iclass 38, count 0 2006.286.03:58:03.58#ibcon#about to write, iclass 38, count 0 2006.286.03:58:03.58#ibcon#wrote, iclass 38, count 0 2006.286.03:58:03.58#ibcon#about to read 3, iclass 38, count 0 2006.286.03:58:03.61#ibcon#read 3, iclass 38, count 0 2006.286.03:58:03.61#ibcon#about to read 4, iclass 38, count 0 2006.286.03:58:03.61#ibcon#read 4, iclass 38, count 0 2006.286.03:58:03.61#ibcon#about to read 5, iclass 38, count 0 2006.286.03:58:03.61#ibcon#read 5, iclass 38, count 0 2006.286.03:58:03.61#ibcon#about to read 6, iclass 38, count 0 2006.286.03:58:03.61#ibcon#read 6, iclass 38, count 0 2006.286.03:58:03.61#ibcon#end of sib2, iclass 38, count 0 2006.286.03:58:03.61#ibcon#*after write, iclass 38, count 0 2006.286.03:58:03.61#ibcon#*before return 0, iclass 38, count 0 2006.286.03:58:03.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:58:03.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:58:03.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.03:58:03.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.03:58:03.61$vck44/valo=8,884.99 2006.286.03:58:03.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.03:58:03.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.03:58:03.61#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:03.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:58:03.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:58:03.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:58:03.61#ibcon#enter wrdev, iclass 6, count 0 2006.286.03:58:03.61#ibcon#first serial, iclass 6, count 0 2006.286.03:58:03.61#ibcon#enter sib2, iclass 6, count 0 2006.286.03:58:03.61#ibcon#flushed, iclass 6, count 0 2006.286.03:58:03.61#ibcon#about to write, iclass 6, count 0 2006.286.03:58:03.61#ibcon#wrote, iclass 6, count 0 2006.286.03:58:03.61#ibcon#about to read 3, iclass 6, count 0 2006.286.03:58:03.63#ibcon#read 3, iclass 6, count 0 2006.286.03:58:03.63#ibcon#about to read 4, iclass 6, count 0 2006.286.03:58:03.63#ibcon#read 4, iclass 6, count 0 2006.286.03:58:03.63#ibcon#about to read 5, iclass 6, count 0 2006.286.03:58:03.63#ibcon#read 5, iclass 6, count 0 2006.286.03:58:03.63#ibcon#about to read 6, iclass 6, count 0 2006.286.03:58:03.63#ibcon#read 6, iclass 6, count 0 2006.286.03:58:03.63#ibcon#end of sib2, iclass 6, count 0 2006.286.03:58:03.63#ibcon#*mode == 0, iclass 6, count 0 2006.286.03:58:03.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.03:58:03.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.03:58:03.63#ibcon#*before write, iclass 6, count 0 2006.286.03:58:03.63#ibcon#enter sib2, iclass 6, count 0 2006.286.03:58:03.63#ibcon#flushed, iclass 6, count 0 2006.286.03:58:03.63#ibcon#about to write, iclass 6, count 0 2006.286.03:58:03.63#ibcon#wrote, iclass 6, count 0 2006.286.03:58:03.63#ibcon#about to read 3, iclass 6, count 0 2006.286.03:58:03.67#ibcon#read 3, iclass 6, count 0 2006.286.03:58:03.67#ibcon#about to read 4, iclass 6, count 0 2006.286.03:58:03.76#ibcon#read 4, iclass 6, count 0 2006.286.03:58:03.76#ibcon#about to read 5, iclass 6, count 0 2006.286.03:58:03.76#ibcon#read 5, iclass 6, count 0 2006.286.03:58:03.76#ibcon#about to read 6, iclass 6, count 0 2006.286.03:58:03.76#ibcon#read 6, iclass 6, count 0 2006.286.03:58:03.76#ibcon#end of sib2, iclass 6, count 0 2006.286.03:58:03.76#ibcon#*after write, iclass 6, count 0 2006.286.03:58:03.76#ibcon#*before return 0, iclass 6, count 0 2006.286.03:58:03.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:58:03.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:58:03.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.03:58:03.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.03:58:03.76$vck44/va=8,3 2006.286.03:58:03.76#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.03:58:03.76#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.03:58:03.76#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:03.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:58:03.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:58:03.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:58:03.76#ibcon#enter wrdev, iclass 10, count 2 2006.286.03:58:03.76#ibcon#first serial, iclass 10, count 2 2006.286.03:58:03.76#ibcon#enter sib2, iclass 10, count 2 2006.286.03:58:03.76#ibcon#flushed, iclass 10, count 2 2006.286.03:58:03.76#ibcon#about to write, iclass 10, count 2 2006.286.03:58:03.76#ibcon#wrote, iclass 10, count 2 2006.286.03:58:03.76#ibcon#about to read 3, iclass 10, count 2 2006.286.03:58:03.77#ibcon#read 3, iclass 10, count 2 2006.286.03:58:03.77#ibcon#about to read 4, iclass 10, count 2 2006.286.03:58:03.77#ibcon#read 4, iclass 10, count 2 2006.286.03:58:03.77#ibcon#about to read 5, iclass 10, count 2 2006.286.03:58:03.77#ibcon#read 5, iclass 10, count 2 2006.286.03:58:03.77#ibcon#about to read 6, iclass 10, count 2 2006.286.03:58:03.77#ibcon#read 6, iclass 10, count 2 2006.286.03:58:03.77#ibcon#end of sib2, iclass 10, count 2 2006.286.03:58:03.77#ibcon#*mode == 0, iclass 10, count 2 2006.286.03:58:03.77#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.03:58:03.77#ibcon#[25=AT08-03\r\n] 2006.286.03:58:03.77#ibcon#*before write, iclass 10, count 2 2006.286.03:58:03.77#ibcon#enter sib2, iclass 10, count 2 2006.286.03:58:03.77#ibcon#flushed, iclass 10, count 2 2006.286.03:58:03.77#ibcon#about to write, iclass 10, count 2 2006.286.03:58:03.77#ibcon#wrote, iclass 10, count 2 2006.286.03:58:03.77#ibcon#about to read 3, iclass 10, count 2 2006.286.03:58:03.80#ibcon#read 3, iclass 10, count 2 2006.286.03:58:03.80#ibcon#about to read 4, iclass 10, count 2 2006.286.03:58:03.80#ibcon#read 4, iclass 10, count 2 2006.286.03:58:03.80#ibcon#about to read 5, iclass 10, count 2 2006.286.03:58:03.80#ibcon#read 5, iclass 10, count 2 2006.286.03:58:03.80#ibcon#about to read 6, iclass 10, count 2 2006.286.03:58:03.80#ibcon#read 6, iclass 10, count 2 2006.286.03:58:03.80#ibcon#end of sib2, iclass 10, count 2 2006.286.03:58:03.80#ibcon#*after write, iclass 10, count 2 2006.286.03:58:03.80#ibcon#*before return 0, iclass 10, count 2 2006.286.03:58:03.80#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:58:03.80#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.03:58:03.80#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.03:58:03.80#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:03.80#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:58:03.92#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:58:03.92#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:58:03.92#ibcon#enter wrdev, iclass 10, count 0 2006.286.03:58:03.92#ibcon#first serial, iclass 10, count 0 2006.286.03:58:03.92#ibcon#enter sib2, iclass 10, count 0 2006.286.03:58:03.92#ibcon#flushed, iclass 10, count 0 2006.286.03:58:03.92#ibcon#about to write, iclass 10, count 0 2006.286.03:58:03.92#ibcon#wrote, iclass 10, count 0 2006.286.03:58:03.92#ibcon#about to read 3, iclass 10, count 0 2006.286.03:58:03.94#ibcon#read 3, iclass 10, count 0 2006.286.03:58:03.94#ibcon#about to read 4, iclass 10, count 0 2006.286.03:58:03.94#ibcon#read 4, iclass 10, count 0 2006.286.03:58:03.94#ibcon#about to read 5, iclass 10, count 0 2006.286.03:58:03.94#ibcon#read 5, iclass 10, count 0 2006.286.03:58:03.94#ibcon#about to read 6, iclass 10, count 0 2006.286.03:58:03.94#ibcon#read 6, iclass 10, count 0 2006.286.03:58:03.94#ibcon#end of sib2, iclass 10, count 0 2006.286.03:58:03.94#ibcon#*mode == 0, iclass 10, count 0 2006.286.03:58:03.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.03:58:03.94#ibcon#[25=USB\r\n] 2006.286.03:58:03.94#ibcon#*before write, iclass 10, count 0 2006.286.03:58:03.94#ibcon#enter sib2, iclass 10, count 0 2006.286.03:58:03.94#ibcon#flushed, iclass 10, count 0 2006.286.03:58:03.94#ibcon#about to write, iclass 10, count 0 2006.286.03:58:03.94#ibcon#wrote, iclass 10, count 0 2006.286.03:58:03.94#ibcon#about to read 3, iclass 10, count 0 2006.286.03:58:03.97#ibcon#read 3, iclass 10, count 0 2006.286.03:58:03.97#ibcon#about to read 4, iclass 10, count 0 2006.286.03:58:03.97#ibcon#read 4, iclass 10, count 0 2006.286.03:58:03.97#ibcon#about to read 5, iclass 10, count 0 2006.286.03:58:03.97#ibcon#read 5, iclass 10, count 0 2006.286.03:58:03.97#ibcon#about to read 6, iclass 10, count 0 2006.286.03:58:03.97#ibcon#read 6, iclass 10, count 0 2006.286.03:58:03.97#ibcon#end of sib2, iclass 10, count 0 2006.286.03:58:03.97#ibcon#*after write, iclass 10, count 0 2006.286.03:58:03.97#ibcon#*before return 0, iclass 10, count 0 2006.286.03:58:03.97#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:58:03.97#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.03:58:03.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.03:58:03.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.03:58:03.97$vck44/vblo=1,629.99 2006.286.03:58:03.97#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.03:58:03.97#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.03:58:03.97#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:03.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:58:03.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:58:03.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:58:03.97#ibcon#enter wrdev, iclass 12, count 0 2006.286.03:58:03.97#ibcon#first serial, iclass 12, count 0 2006.286.03:58:03.97#ibcon#enter sib2, iclass 12, count 0 2006.286.03:58:03.97#ibcon#flushed, iclass 12, count 0 2006.286.03:58:03.97#ibcon#about to write, iclass 12, count 0 2006.286.03:58:03.97#ibcon#wrote, iclass 12, count 0 2006.286.03:58:03.97#ibcon#about to read 3, iclass 12, count 0 2006.286.03:58:03.99#ibcon#read 3, iclass 12, count 0 2006.286.03:58:03.99#ibcon#about to read 4, iclass 12, count 0 2006.286.03:58:03.99#ibcon#read 4, iclass 12, count 0 2006.286.03:58:03.99#ibcon#about to read 5, iclass 12, count 0 2006.286.03:58:03.99#ibcon#read 5, iclass 12, count 0 2006.286.03:58:03.99#ibcon#about to read 6, iclass 12, count 0 2006.286.03:58:03.99#ibcon#read 6, iclass 12, count 0 2006.286.03:58:03.99#ibcon#end of sib2, iclass 12, count 0 2006.286.03:58:03.99#ibcon#*mode == 0, iclass 12, count 0 2006.286.03:58:03.99#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.03:58:03.99#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.03:58:03.99#ibcon#*before write, iclass 12, count 0 2006.286.03:58:03.99#ibcon#enter sib2, iclass 12, count 0 2006.286.03:58:03.99#ibcon#flushed, iclass 12, count 0 2006.286.03:58:03.99#ibcon#about to write, iclass 12, count 0 2006.286.03:58:03.99#ibcon#wrote, iclass 12, count 0 2006.286.03:58:03.99#ibcon#about to read 3, iclass 12, count 0 2006.286.03:58:04.03#ibcon#read 3, iclass 12, count 0 2006.286.03:58:04.03#ibcon#about to read 4, iclass 12, count 0 2006.286.03:58:04.03#ibcon#read 4, iclass 12, count 0 2006.286.03:58:04.03#ibcon#about to read 5, iclass 12, count 0 2006.286.03:58:04.03#ibcon#read 5, iclass 12, count 0 2006.286.03:58:04.03#ibcon#about to read 6, iclass 12, count 0 2006.286.03:58:04.03#ibcon#read 6, iclass 12, count 0 2006.286.03:58:04.03#ibcon#end of sib2, iclass 12, count 0 2006.286.03:58:04.03#ibcon#*after write, iclass 12, count 0 2006.286.03:58:04.03#ibcon#*before return 0, iclass 12, count 0 2006.286.03:58:04.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:58:04.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.03:58:04.03#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.03:58:04.03#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.03:58:04.03$vck44/vb=1,4 2006.286.03:58:04.03#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.03:58:04.03#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.03:58:04.03#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:04.03#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:58:04.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:58:04.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:58:04.03#ibcon#enter wrdev, iclass 14, count 2 2006.286.03:58:04.03#ibcon#first serial, iclass 14, count 2 2006.286.03:58:04.03#ibcon#enter sib2, iclass 14, count 2 2006.286.03:58:04.03#ibcon#flushed, iclass 14, count 2 2006.286.03:58:04.03#ibcon#about to write, iclass 14, count 2 2006.286.03:58:04.03#ibcon#wrote, iclass 14, count 2 2006.286.03:58:04.03#ibcon#about to read 3, iclass 14, count 2 2006.286.03:58:04.05#ibcon#read 3, iclass 14, count 2 2006.286.03:58:04.05#ibcon#about to read 4, iclass 14, count 2 2006.286.03:58:04.05#ibcon#read 4, iclass 14, count 2 2006.286.03:58:04.05#ibcon#about to read 5, iclass 14, count 2 2006.286.03:58:04.05#ibcon#read 5, iclass 14, count 2 2006.286.03:58:04.05#ibcon#about to read 6, iclass 14, count 2 2006.286.03:58:04.05#ibcon#read 6, iclass 14, count 2 2006.286.03:58:04.05#ibcon#end of sib2, iclass 14, count 2 2006.286.03:58:04.05#ibcon#*mode == 0, iclass 14, count 2 2006.286.03:58:04.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.03:58:04.05#ibcon#[27=AT01-04\r\n] 2006.286.03:58:04.05#ibcon#*before write, iclass 14, count 2 2006.286.03:58:04.05#ibcon#enter sib2, iclass 14, count 2 2006.286.03:58:04.05#ibcon#flushed, iclass 14, count 2 2006.286.03:58:04.05#ibcon#about to write, iclass 14, count 2 2006.286.03:58:04.05#ibcon#wrote, iclass 14, count 2 2006.286.03:58:04.05#ibcon#about to read 3, iclass 14, count 2 2006.286.03:58:04.08#ibcon#read 3, iclass 14, count 2 2006.286.03:58:04.08#ibcon#about to read 4, iclass 14, count 2 2006.286.03:58:04.08#ibcon#read 4, iclass 14, count 2 2006.286.03:58:04.08#ibcon#about to read 5, iclass 14, count 2 2006.286.03:58:04.08#ibcon#read 5, iclass 14, count 2 2006.286.03:58:04.08#ibcon#about to read 6, iclass 14, count 2 2006.286.03:58:04.08#ibcon#read 6, iclass 14, count 2 2006.286.03:58:04.08#ibcon#end of sib2, iclass 14, count 2 2006.286.03:58:04.08#ibcon#*after write, iclass 14, count 2 2006.286.03:58:04.08#ibcon#*before return 0, iclass 14, count 2 2006.286.03:58:04.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:58:04.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.03:58:04.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.03:58:04.08#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:04.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:58:04.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:58:04.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:58:04.20#ibcon#enter wrdev, iclass 14, count 0 2006.286.03:58:04.20#ibcon#first serial, iclass 14, count 0 2006.286.03:58:04.20#ibcon#enter sib2, iclass 14, count 0 2006.286.03:58:04.20#ibcon#flushed, iclass 14, count 0 2006.286.03:58:04.20#ibcon#about to write, iclass 14, count 0 2006.286.03:58:04.20#ibcon#wrote, iclass 14, count 0 2006.286.03:58:04.20#ibcon#about to read 3, iclass 14, count 0 2006.286.03:58:04.22#ibcon#read 3, iclass 14, count 0 2006.286.03:58:04.22#ibcon#about to read 4, iclass 14, count 0 2006.286.03:58:04.22#ibcon#read 4, iclass 14, count 0 2006.286.03:58:04.22#ibcon#about to read 5, iclass 14, count 0 2006.286.03:58:04.22#ibcon#read 5, iclass 14, count 0 2006.286.03:58:04.22#ibcon#about to read 6, iclass 14, count 0 2006.286.03:58:04.22#ibcon#read 6, iclass 14, count 0 2006.286.03:58:04.22#ibcon#end of sib2, iclass 14, count 0 2006.286.03:58:04.22#ibcon#*mode == 0, iclass 14, count 0 2006.286.03:58:04.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.03:58:04.22#ibcon#[27=USB\r\n] 2006.286.03:58:04.22#ibcon#*before write, iclass 14, count 0 2006.286.03:58:04.22#ibcon#enter sib2, iclass 14, count 0 2006.286.03:58:04.22#ibcon#flushed, iclass 14, count 0 2006.286.03:58:04.22#ibcon#about to write, iclass 14, count 0 2006.286.03:58:04.22#ibcon#wrote, iclass 14, count 0 2006.286.03:58:04.22#ibcon#about to read 3, iclass 14, count 0 2006.286.03:58:04.25#ibcon#read 3, iclass 14, count 0 2006.286.03:58:04.25#ibcon#about to read 4, iclass 14, count 0 2006.286.03:58:04.25#ibcon#read 4, iclass 14, count 0 2006.286.03:58:04.25#ibcon#about to read 5, iclass 14, count 0 2006.286.03:58:04.25#ibcon#read 5, iclass 14, count 0 2006.286.03:58:04.25#ibcon#about to read 6, iclass 14, count 0 2006.286.03:58:04.25#ibcon#read 6, iclass 14, count 0 2006.286.03:58:04.25#ibcon#end of sib2, iclass 14, count 0 2006.286.03:58:04.25#ibcon#*after write, iclass 14, count 0 2006.286.03:58:04.25#ibcon#*before return 0, iclass 14, count 0 2006.286.03:58:04.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:58:04.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.03:58:04.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.03:58:04.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.03:58:04.25$vck44/vblo=2,634.99 2006.286.03:58:04.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.03:58:04.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.03:58:04.25#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:04.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:58:04.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:58:04.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:58:04.25#ibcon#enter wrdev, iclass 16, count 0 2006.286.03:58:04.25#ibcon#first serial, iclass 16, count 0 2006.286.03:58:04.25#ibcon#enter sib2, iclass 16, count 0 2006.286.03:58:04.25#ibcon#flushed, iclass 16, count 0 2006.286.03:58:04.25#ibcon#about to write, iclass 16, count 0 2006.286.03:58:04.25#ibcon#wrote, iclass 16, count 0 2006.286.03:58:04.25#ibcon#about to read 3, iclass 16, count 0 2006.286.03:58:04.27#ibcon#read 3, iclass 16, count 0 2006.286.03:58:04.27#ibcon#about to read 4, iclass 16, count 0 2006.286.03:58:04.27#ibcon#read 4, iclass 16, count 0 2006.286.03:58:04.27#ibcon#about to read 5, iclass 16, count 0 2006.286.03:58:04.27#ibcon#read 5, iclass 16, count 0 2006.286.03:58:04.27#ibcon#about to read 6, iclass 16, count 0 2006.286.03:58:04.27#ibcon#read 6, iclass 16, count 0 2006.286.03:58:04.27#ibcon#end of sib2, iclass 16, count 0 2006.286.03:58:04.27#ibcon#*mode == 0, iclass 16, count 0 2006.286.03:58:04.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.03:58:04.27#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.03:58:04.27#ibcon#*before write, iclass 16, count 0 2006.286.03:58:04.27#ibcon#enter sib2, iclass 16, count 0 2006.286.03:58:04.27#ibcon#flushed, iclass 16, count 0 2006.286.03:58:04.27#ibcon#about to write, iclass 16, count 0 2006.286.03:58:04.27#ibcon#wrote, iclass 16, count 0 2006.286.03:58:04.27#ibcon#about to read 3, iclass 16, count 0 2006.286.03:58:04.31#ibcon#read 3, iclass 16, count 0 2006.286.03:58:04.31#ibcon#about to read 4, iclass 16, count 0 2006.286.03:58:04.31#ibcon#read 4, iclass 16, count 0 2006.286.03:58:04.31#ibcon#about to read 5, iclass 16, count 0 2006.286.03:58:04.31#ibcon#read 5, iclass 16, count 0 2006.286.03:58:04.31#ibcon#about to read 6, iclass 16, count 0 2006.286.03:58:04.31#ibcon#read 6, iclass 16, count 0 2006.286.03:58:04.31#ibcon#end of sib2, iclass 16, count 0 2006.286.03:58:04.31#ibcon#*after write, iclass 16, count 0 2006.286.03:58:04.31#ibcon#*before return 0, iclass 16, count 0 2006.286.03:58:04.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:58:04.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.03:58:04.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.03:58:04.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.03:58:04.31$vck44/vb=2,5 2006.286.03:58:04.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.03:58:04.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.03:58:04.31#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:04.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:58:04.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:58:04.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:58:04.37#ibcon#enter wrdev, iclass 18, count 2 2006.286.03:58:04.37#ibcon#first serial, iclass 18, count 2 2006.286.03:58:04.37#ibcon#enter sib2, iclass 18, count 2 2006.286.03:58:04.37#ibcon#flushed, iclass 18, count 2 2006.286.03:58:04.37#ibcon#about to write, iclass 18, count 2 2006.286.03:58:04.37#ibcon#wrote, iclass 18, count 2 2006.286.03:58:04.37#ibcon#about to read 3, iclass 18, count 2 2006.286.03:58:04.39#ibcon#read 3, iclass 18, count 2 2006.286.03:58:04.39#ibcon#about to read 4, iclass 18, count 2 2006.286.03:58:04.39#ibcon#read 4, iclass 18, count 2 2006.286.03:58:04.39#ibcon#about to read 5, iclass 18, count 2 2006.286.03:58:04.39#ibcon#read 5, iclass 18, count 2 2006.286.03:58:04.39#ibcon#about to read 6, iclass 18, count 2 2006.286.03:58:04.39#ibcon#read 6, iclass 18, count 2 2006.286.03:58:04.39#ibcon#end of sib2, iclass 18, count 2 2006.286.03:58:04.39#ibcon#*mode == 0, iclass 18, count 2 2006.286.03:58:04.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.03:58:04.39#ibcon#[27=AT02-05\r\n] 2006.286.03:58:04.39#ibcon#*before write, iclass 18, count 2 2006.286.03:58:04.39#ibcon#enter sib2, iclass 18, count 2 2006.286.03:58:04.39#ibcon#flushed, iclass 18, count 2 2006.286.03:58:04.39#ibcon#about to write, iclass 18, count 2 2006.286.03:58:04.39#ibcon#wrote, iclass 18, count 2 2006.286.03:58:04.39#ibcon#about to read 3, iclass 18, count 2 2006.286.03:58:04.42#ibcon#read 3, iclass 18, count 2 2006.286.03:58:04.42#ibcon#about to read 4, iclass 18, count 2 2006.286.03:58:04.42#ibcon#read 4, iclass 18, count 2 2006.286.03:58:04.42#ibcon#about to read 5, iclass 18, count 2 2006.286.03:58:04.42#ibcon#read 5, iclass 18, count 2 2006.286.03:58:04.42#ibcon#about to read 6, iclass 18, count 2 2006.286.03:58:04.42#ibcon#read 6, iclass 18, count 2 2006.286.03:58:04.42#ibcon#end of sib2, iclass 18, count 2 2006.286.03:58:04.42#ibcon#*after write, iclass 18, count 2 2006.286.03:58:04.42#ibcon#*before return 0, iclass 18, count 2 2006.286.03:58:04.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:58:04.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.03:58:04.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.03:58:04.42#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:04.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:58:04.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:58:04.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:58:04.54#ibcon#enter wrdev, iclass 18, count 0 2006.286.03:58:04.54#ibcon#first serial, iclass 18, count 0 2006.286.03:58:04.54#ibcon#enter sib2, iclass 18, count 0 2006.286.03:58:04.54#ibcon#flushed, iclass 18, count 0 2006.286.03:58:04.54#ibcon#about to write, iclass 18, count 0 2006.286.03:58:04.54#ibcon#wrote, iclass 18, count 0 2006.286.03:58:04.54#ibcon#about to read 3, iclass 18, count 0 2006.286.03:58:04.56#ibcon#read 3, iclass 18, count 0 2006.286.03:58:04.56#ibcon#about to read 4, iclass 18, count 0 2006.286.03:58:04.56#ibcon#read 4, iclass 18, count 0 2006.286.03:58:04.56#ibcon#about to read 5, iclass 18, count 0 2006.286.03:58:04.56#ibcon#read 5, iclass 18, count 0 2006.286.03:58:04.56#ibcon#about to read 6, iclass 18, count 0 2006.286.03:58:04.56#ibcon#read 6, iclass 18, count 0 2006.286.03:58:04.56#ibcon#end of sib2, iclass 18, count 0 2006.286.03:58:04.56#ibcon#*mode == 0, iclass 18, count 0 2006.286.03:58:04.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.03:58:04.56#ibcon#[27=USB\r\n] 2006.286.03:58:04.56#ibcon#*before write, iclass 18, count 0 2006.286.03:58:04.56#ibcon#enter sib2, iclass 18, count 0 2006.286.03:58:04.56#ibcon#flushed, iclass 18, count 0 2006.286.03:58:04.56#ibcon#about to write, iclass 18, count 0 2006.286.03:58:04.56#ibcon#wrote, iclass 18, count 0 2006.286.03:58:04.56#ibcon#about to read 3, iclass 18, count 0 2006.286.03:58:04.59#ibcon#read 3, iclass 18, count 0 2006.286.03:58:04.59#ibcon#about to read 4, iclass 18, count 0 2006.286.03:58:04.59#ibcon#read 4, iclass 18, count 0 2006.286.03:58:04.59#ibcon#about to read 5, iclass 18, count 0 2006.286.03:58:04.59#ibcon#read 5, iclass 18, count 0 2006.286.03:58:04.59#ibcon#about to read 6, iclass 18, count 0 2006.286.03:58:04.59#ibcon#read 6, iclass 18, count 0 2006.286.03:58:04.59#ibcon#end of sib2, iclass 18, count 0 2006.286.03:58:04.59#ibcon#*after write, iclass 18, count 0 2006.286.03:58:04.59#ibcon#*before return 0, iclass 18, count 0 2006.286.03:58:04.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:58:04.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.03:58:04.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.03:58:04.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.03:58:04.59$vck44/vblo=3,649.99 2006.286.03:58:04.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.03:58:04.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.03:58:04.59#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:04.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:58:04.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:58:04.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:58:04.59#ibcon#enter wrdev, iclass 20, count 0 2006.286.03:58:04.59#ibcon#first serial, iclass 20, count 0 2006.286.03:58:04.59#ibcon#enter sib2, iclass 20, count 0 2006.286.03:58:04.59#ibcon#flushed, iclass 20, count 0 2006.286.03:58:04.59#ibcon#about to write, iclass 20, count 0 2006.286.03:58:04.59#ibcon#wrote, iclass 20, count 0 2006.286.03:58:04.59#ibcon#about to read 3, iclass 20, count 0 2006.286.03:58:04.61#ibcon#read 3, iclass 20, count 0 2006.286.03:58:04.61#ibcon#about to read 4, iclass 20, count 0 2006.286.03:58:04.61#ibcon#read 4, iclass 20, count 0 2006.286.03:58:04.61#ibcon#about to read 5, iclass 20, count 0 2006.286.03:58:04.61#ibcon#read 5, iclass 20, count 0 2006.286.03:58:04.61#ibcon#about to read 6, iclass 20, count 0 2006.286.03:58:04.61#ibcon#read 6, iclass 20, count 0 2006.286.03:58:04.61#ibcon#end of sib2, iclass 20, count 0 2006.286.03:58:04.61#ibcon#*mode == 0, iclass 20, count 0 2006.286.03:58:04.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.03:58:04.61#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.03:58:04.61#ibcon#*before write, iclass 20, count 0 2006.286.03:58:04.61#ibcon#enter sib2, iclass 20, count 0 2006.286.03:58:04.61#ibcon#flushed, iclass 20, count 0 2006.286.03:58:04.61#ibcon#about to write, iclass 20, count 0 2006.286.03:58:04.61#ibcon#wrote, iclass 20, count 0 2006.286.03:58:04.61#ibcon#about to read 3, iclass 20, count 0 2006.286.03:58:04.65#ibcon#read 3, iclass 20, count 0 2006.286.03:58:04.65#ibcon#about to read 4, iclass 20, count 0 2006.286.03:58:04.65#ibcon#read 4, iclass 20, count 0 2006.286.03:58:04.65#ibcon#about to read 5, iclass 20, count 0 2006.286.03:58:04.65#ibcon#read 5, iclass 20, count 0 2006.286.03:58:04.65#ibcon#about to read 6, iclass 20, count 0 2006.286.03:58:04.65#ibcon#read 6, iclass 20, count 0 2006.286.03:58:04.65#ibcon#end of sib2, iclass 20, count 0 2006.286.03:58:04.65#ibcon#*after write, iclass 20, count 0 2006.286.03:58:04.65#ibcon#*before return 0, iclass 20, count 0 2006.286.03:58:04.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:58:04.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.03:58:04.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.03:58:04.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.03:58:04.65$vck44/vb=3,4 2006.286.03:58:04.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.03:58:04.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.03:58:04.65#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:04.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:58:04.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:58:04.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:58:04.71#ibcon#enter wrdev, iclass 22, count 2 2006.286.03:58:04.71#ibcon#first serial, iclass 22, count 2 2006.286.03:58:04.71#ibcon#enter sib2, iclass 22, count 2 2006.286.03:58:04.71#ibcon#flushed, iclass 22, count 2 2006.286.03:58:04.71#ibcon#about to write, iclass 22, count 2 2006.286.03:58:04.71#ibcon#wrote, iclass 22, count 2 2006.286.03:58:04.71#ibcon#about to read 3, iclass 22, count 2 2006.286.03:58:04.73#ibcon#read 3, iclass 22, count 2 2006.286.03:58:04.86#ibcon#about to read 4, iclass 22, count 2 2006.286.03:58:04.86#ibcon#read 4, iclass 22, count 2 2006.286.03:58:04.86#ibcon#about to read 5, iclass 22, count 2 2006.286.03:58:04.86#ibcon#read 5, iclass 22, count 2 2006.286.03:58:04.86#ibcon#about to read 6, iclass 22, count 2 2006.286.03:58:04.86#ibcon#read 6, iclass 22, count 2 2006.286.03:58:04.86#ibcon#end of sib2, iclass 22, count 2 2006.286.03:58:04.86#ibcon#*mode == 0, iclass 22, count 2 2006.286.03:58:04.86#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.03:58:04.86#ibcon#[27=AT03-04\r\n] 2006.286.03:58:04.86#ibcon#*before write, iclass 22, count 2 2006.286.03:58:04.86#ibcon#enter sib2, iclass 22, count 2 2006.286.03:58:04.86#ibcon#flushed, iclass 22, count 2 2006.286.03:58:04.86#ibcon#about to write, iclass 22, count 2 2006.286.03:58:04.86#ibcon#wrote, iclass 22, count 2 2006.286.03:58:04.86#ibcon#about to read 3, iclass 22, count 2 2006.286.03:58:04.88#ibcon#read 3, iclass 22, count 2 2006.286.03:58:04.88#ibcon#about to read 4, iclass 22, count 2 2006.286.03:58:04.88#ibcon#read 4, iclass 22, count 2 2006.286.03:58:04.88#ibcon#about to read 5, iclass 22, count 2 2006.286.03:58:04.88#ibcon#read 5, iclass 22, count 2 2006.286.03:58:04.88#ibcon#about to read 6, iclass 22, count 2 2006.286.03:58:04.88#ibcon#read 6, iclass 22, count 2 2006.286.03:58:04.88#ibcon#end of sib2, iclass 22, count 2 2006.286.03:58:04.88#ibcon#*after write, iclass 22, count 2 2006.286.03:58:04.88#ibcon#*before return 0, iclass 22, count 2 2006.286.03:58:04.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:58:04.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.03:58:04.88#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.03:58:04.88#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:04.88#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:58:05.00#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:58:05.00#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:58:05.00#ibcon#enter wrdev, iclass 22, count 0 2006.286.03:58:05.00#ibcon#first serial, iclass 22, count 0 2006.286.03:58:05.00#ibcon#enter sib2, iclass 22, count 0 2006.286.03:58:05.00#ibcon#flushed, iclass 22, count 0 2006.286.03:58:05.00#ibcon#about to write, iclass 22, count 0 2006.286.03:58:05.00#ibcon#wrote, iclass 22, count 0 2006.286.03:58:05.00#ibcon#about to read 3, iclass 22, count 0 2006.286.03:58:05.02#ibcon#read 3, iclass 22, count 0 2006.286.03:58:05.02#ibcon#about to read 4, iclass 22, count 0 2006.286.03:58:05.02#ibcon#read 4, iclass 22, count 0 2006.286.03:58:05.02#ibcon#about to read 5, iclass 22, count 0 2006.286.03:58:05.02#ibcon#read 5, iclass 22, count 0 2006.286.03:58:05.02#ibcon#about to read 6, iclass 22, count 0 2006.286.03:58:05.02#ibcon#read 6, iclass 22, count 0 2006.286.03:58:05.02#ibcon#end of sib2, iclass 22, count 0 2006.286.03:58:05.02#ibcon#*mode == 0, iclass 22, count 0 2006.286.03:58:05.02#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.03:58:05.02#ibcon#[27=USB\r\n] 2006.286.03:58:05.02#ibcon#*before write, iclass 22, count 0 2006.286.03:58:05.02#ibcon#enter sib2, iclass 22, count 0 2006.286.03:58:05.02#ibcon#flushed, iclass 22, count 0 2006.286.03:58:05.02#ibcon#about to write, iclass 22, count 0 2006.286.03:58:05.02#ibcon#wrote, iclass 22, count 0 2006.286.03:58:05.02#ibcon#about to read 3, iclass 22, count 0 2006.286.03:58:05.05#ibcon#read 3, iclass 22, count 0 2006.286.03:58:05.05#ibcon#about to read 4, iclass 22, count 0 2006.286.03:58:05.05#ibcon#read 4, iclass 22, count 0 2006.286.03:58:05.05#ibcon#about to read 5, iclass 22, count 0 2006.286.03:58:05.05#ibcon#read 5, iclass 22, count 0 2006.286.03:58:05.05#ibcon#about to read 6, iclass 22, count 0 2006.286.03:58:05.05#ibcon#read 6, iclass 22, count 0 2006.286.03:58:05.05#ibcon#end of sib2, iclass 22, count 0 2006.286.03:58:05.05#ibcon#*after write, iclass 22, count 0 2006.286.03:58:05.05#ibcon#*before return 0, iclass 22, count 0 2006.286.03:58:05.05#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:58:05.05#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.03:58:05.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.03:58:05.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.03:58:05.05$vck44/vblo=4,679.99 2006.286.03:58:05.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.03:58:05.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.03:58:05.05#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:05.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:58:05.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:58:05.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:58:05.05#ibcon#enter wrdev, iclass 24, count 0 2006.286.03:58:05.05#ibcon#first serial, iclass 24, count 0 2006.286.03:58:05.05#ibcon#enter sib2, iclass 24, count 0 2006.286.03:58:05.05#ibcon#flushed, iclass 24, count 0 2006.286.03:58:05.05#ibcon#about to write, iclass 24, count 0 2006.286.03:58:05.05#ibcon#wrote, iclass 24, count 0 2006.286.03:58:05.05#ibcon#about to read 3, iclass 24, count 0 2006.286.03:58:05.07#ibcon#read 3, iclass 24, count 0 2006.286.03:58:05.07#ibcon#about to read 4, iclass 24, count 0 2006.286.03:58:05.07#ibcon#read 4, iclass 24, count 0 2006.286.03:58:05.07#ibcon#about to read 5, iclass 24, count 0 2006.286.03:58:05.07#ibcon#read 5, iclass 24, count 0 2006.286.03:58:05.07#ibcon#about to read 6, iclass 24, count 0 2006.286.03:58:05.07#ibcon#read 6, iclass 24, count 0 2006.286.03:58:05.07#ibcon#end of sib2, iclass 24, count 0 2006.286.03:58:05.07#ibcon#*mode == 0, iclass 24, count 0 2006.286.03:58:05.07#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.03:58:05.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.03:58:05.07#ibcon#*before write, iclass 24, count 0 2006.286.03:58:05.07#ibcon#enter sib2, iclass 24, count 0 2006.286.03:58:05.07#ibcon#flushed, iclass 24, count 0 2006.286.03:58:05.07#ibcon#about to write, iclass 24, count 0 2006.286.03:58:05.07#ibcon#wrote, iclass 24, count 0 2006.286.03:58:05.07#ibcon#about to read 3, iclass 24, count 0 2006.286.03:58:05.11#ibcon#read 3, iclass 24, count 0 2006.286.03:58:05.11#ibcon#about to read 4, iclass 24, count 0 2006.286.03:58:05.11#ibcon#read 4, iclass 24, count 0 2006.286.03:58:05.11#ibcon#about to read 5, iclass 24, count 0 2006.286.03:58:05.11#ibcon#read 5, iclass 24, count 0 2006.286.03:58:05.11#ibcon#about to read 6, iclass 24, count 0 2006.286.03:58:05.11#ibcon#read 6, iclass 24, count 0 2006.286.03:58:05.11#ibcon#end of sib2, iclass 24, count 0 2006.286.03:58:05.11#ibcon#*after write, iclass 24, count 0 2006.286.03:58:05.11#ibcon#*before return 0, iclass 24, count 0 2006.286.03:58:05.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:58:05.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.03:58:05.11#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.03:58:05.11#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.03:58:05.11$vck44/vb=4,5 2006.286.03:58:05.11#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.03:58:05.11#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.03:58:05.11#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:05.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:58:05.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:58:05.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:58:05.17#ibcon#enter wrdev, iclass 26, count 2 2006.286.03:58:05.17#ibcon#first serial, iclass 26, count 2 2006.286.03:58:05.17#ibcon#enter sib2, iclass 26, count 2 2006.286.03:58:05.17#ibcon#flushed, iclass 26, count 2 2006.286.03:58:05.17#ibcon#about to write, iclass 26, count 2 2006.286.03:58:05.17#ibcon#wrote, iclass 26, count 2 2006.286.03:58:05.17#ibcon#about to read 3, iclass 26, count 2 2006.286.03:58:05.19#ibcon#read 3, iclass 26, count 2 2006.286.03:58:05.19#ibcon#about to read 4, iclass 26, count 2 2006.286.03:58:05.19#ibcon#read 4, iclass 26, count 2 2006.286.03:58:05.19#ibcon#about to read 5, iclass 26, count 2 2006.286.03:58:05.19#ibcon#read 5, iclass 26, count 2 2006.286.03:58:05.19#ibcon#about to read 6, iclass 26, count 2 2006.286.03:58:05.19#ibcon#read 6, iclass 26, count 2 2006.286.03:58:05.19#ibcon#end of sib2, iclass 26, count 2 2006.286.03:58:05.19#ibcon#*mode == 0, iclass 26, count 2 2006.286.03:58:05.19#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.03:58:05.19#ibcon#[27=AT04-05\r\n] 2006.286.03:58:05.19#ibcon#*before write, iclass 26, count 2 2006.286.03:58:05.19#ibcon#enter sib2, iclass 26, count 2 2006.286.03:58:05.19#ibcon#flushed, iclass 26, count 2 2006.286.03:58:05.19#ibcon#about to write, iclass 26, count 2 2006.286.03:58:05.19#ibcon#wrote, iclass 26, count 2 2006.286.03:58:05.19#ibcon#about to read 3, iclass 26, count 2 2006.286.03:58:05.22#ibcon#read 3, iclass 26, count 2 2006.286.03:58:05.22#ibcon#about to read 4, iclass 26, count 2 2006.286.03:58:05.22#ibcon#read 4, iclass 26, count 2 2006.286.03:58:05.22#ibcon#about to read 5, iclass 26, count 2 2006.286.03:58:05.22#ibcon#read 5, iclass 26, count 2 2006.286.03:58:05.22#ibcon#about to read 6, iclass 26, count 2 2006.286.03:58:05.22#ibcon#read 6, iclass 26, count 2 2006.286.03:58:05.22#ibcon#end of sib2, iclass 26, count 2 2006.286.03:58:05.22#ibcon#*after write, iclass 26, count 2 2006.286.03:58:05.22#ibcon#*before return 0, iclass 26, count 2 2006.286.03:58:05.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:58:05.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.03:58:05.22#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.03:58:05.22#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:05.22#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:58:05.34#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:58:05.34#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:58:05.34#ibcon#enter wrdev, iclass 26, count 0 2006.286.03:58:05.34#ibcon#first serial, iclass 26, count 0 2006.286.03:58:05.34#ibcon#enter sib2, iclass 26, count 0 2006.286.03:58:05.34#ibcon#flushed, iclass 26, count 0 2006.286.03:58:05.34#ibcon#about to write, iclass 26, count 0 2006.286.03:58:05.34#ibcon#wrote, iclass 26, count 0 2006.286.03:58:05.34#ibcon#about to read 3, iclass 26, count 0 2006.286.03:58:05.36#ibcon#read 3, iclass 26, count 0 2006.286.03:58:05.36#ibcon#about to read 4, iclass 26, count 0 2006.286.03:58:05.36#ibcon#read 4, iclass 26, count 0 2006.286.03:58:05.36#ibcon#about to read 5, iclass 26, count 0 2006.286.03:58:05.36#ibcon#read 5, iclass 26, count 0 2006.286.03:58:05.36#ibcon#about to read 6, iclass 26, count 0 2006.286.03:58:05.36#ibcon#read 6, iclass 26, count 0 2006.286.03:58:05.36#ibcon#end of sib2, iclass 26, count 0 2006.286.03:58:05.36#ibcon#*mode == 0, iclass 26, count 0 2006.286.03:58:05.36#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.03:58:05.36#ibcon#[27=USB\r\n] 2006.286.03:58:05.36#ibcon#*before write, iclass 26, count 0 2006.286.03:58:05.36#ibcon#enter sib2, iclass 26, count 0 2006.286.03:58:05.36#ibcon#flushed, iclass 26, count 0 2006.286.03:58:05.36#ibcon#about to write, iclass 26, count 0 2006.286.03:58:05.36#ibcon#wrote, iclass 26, count 0 2006.286.03:58:05.36#ibcon#about to read 3, iclass 26, count 0 2006.286.03:58:05.39#ibcon#read 3, iclass 26, count 0 2006.286.03:58:05.39#ibcon#about to read 4, iclass 26, count 0 2006.286.03:58:05.39#ibcon#read 4, iclass 26, count 0 2006.286.03:58:05.39#ibcon#about to read 5, iclass 26, count 0 2006.286.03:58:05.39#ibcon#read 5, iclass 26, count 0 2006.286.03:58:05.39#ibcon#about to read 6, iclass 26, count 0 2006.286.03:58:05.39#ibcon#read 6, iclass 26, count 0 2006.286.03:58:05.39#ibcon#end of sib2, iclass 26, count 0 2006.286.03:58:05.39#ibcon#*after write, iclass 26, count 0 2006.286.03:58:05.39#ibcon#*before return 0, iclass 26, count 0 2006.286.03:58:05.39#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:58:05.39#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.03:58:05.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.03:58:05.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.03:58:05.39$vck44/vblo=5,709.99 2006.286.03:58:05.39#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.03:58:05.39#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.03:58:05.39#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:05.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:58:05.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:58:05.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:58:05.39#ibcon#enter wrdev, iclass 28, count 0 2006.286.03:58:05.39#ibcon#first serial, iclass 28, count 0 2006.286.03:58:05.39#ibcon#enter sib2, iclass 28, count 0 2006.286.03:58:05.39#ibcon#flushed, iclass 28, count 0 2006.286.03:58:05.39#ibcon#about to write, iclass 28, count 0 2006.286.03:58:05.39#ibcon#wrote, iclass 28, count 0 2006.286.03:58:05.39#ibcon#about to read 3, iclass 28, count 0 2006.286.03:58:05.41#ibcon#read 3, iclass 28, count 0 2006.286.03:58:05.41#ibcon#about to read 4, iclass 28, count 0 2006.286.03:58:05.41#ibcon#read 4, iclass 28, count 0 2006.286.03:58:05.41#ibcon#about to read 5, iclass 28, count 0 2006.286.03:58:05.41#ibcon#read 5, iclass 28, count 0 2006.286.03:58:05.41#ibcon#about to read 6, iclass 28, count 0 2006.286.03:58:05.41#ibcon#read 6, iclass 28, count 0 2006.286.03:58:05.41#ibcon#end of sib2, iclass 28, count 0 2006.286.03:58:05.41#ibcon#*mode == 0, iclass 28, count 0 2006.286.03:58:05.41#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.03:58:05.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.03:58:05.41#ibcon#*before write, iclass 28, count 0 2006.286.03:58:05.41#ibcon#enter sib2, iclass 28, count 0 2006.286.03:58:05.41#ibcon#flushed, iclass 28, count 0 2006.286.03:58:05.41#ibcon#about to write, iclass 28, count 0 2006.286.03:58:05.41#ibcon#wrote, iclass 28, count 0 2006.286.03:58:05.41#ibcon#about to read 3, iclass 28, count 0 2006.286.03:58:05.45#ibcon#read 3, iclass 28, count 0 2006.286.03:58:05.45#ibcon#about to read 4, iclass 28, count 0 2006.286.03:58:05.45#ibcon#read 4, iclass 28, count 0 2006.286.03:58:05.45#ibcon#about to read 5, iclass 28, count 0 2006.286.03:58:05.45#ibcon#read 5, iclass 28, count 0 2006.286.03:58:05.45#ibcon#about to read 6, iclass 28, count 0 2006.286.03:58:05.45#ibcon#read 6, iclass 28, count 0 2006.286.03:58:05.45#ibcon#end of sib2, iclass 28, count 0 2006.286.03:58:05.45#ibcon#*after write, iclass 28, count 0 2006.286.03:58:05.45#ibcon#*before return 0, iclass 28, count 0 2006.286.03:58:05.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:58:05.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.03:58:05.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.03:58:05.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.03:58:05.45$vck44/vb=5,4 2006.286.03:58:05.45#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.03:58:05.45#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.03:58:05.45#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:05.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:58:05.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:58:05.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:58:05.51#ibcon#enter wrdev, iclass 30, count 2 2006.286.03:58:05.51#ibcon#first serial, iclass 30, count 2 2006.286.03:58:05.51#ibcon#enter sib2, iclass 30, count 2 2006.286.03:58:05.51#ibcon#flushed, iclass 30, count 2 2006.286.03:58:05.51#ibcon#about to write, iclass 30, count 2 2006.286.03:58:05.51#ibcon#wrote, iclass 30, count 2 2006.286.03:58:05.51#ibcon#about to read 3, iclass 30, count 2 2006.286.03:58:05.53#ibcon#read 3, iclass 30, count 2 2006.286.03:58:05.53#ibcon#about to read 4, iclass 30, count 2 2006.286.03:58:05.53#ibcon#read 4, iclass 30, count 2 2006.286.03:58:05.53#ibcon#about to read 5, iclass 30, count 2 2006.286.03:58:05.53#ibcon#read 5, iclass 30, count 2 2006.286.03:58:05.53#ibcon#about to read 6, iclass 30, count 2 2006.286.03:58:05.53#ibcon#read 6, iclass 30, count 2 2006.286.03:58:05.53#ibcon#end of sib2, iclass 30, count 2 2006.286.03:58:05.53#ibcon#*mode == 0, iclass 30, count 2 2006.286.03:58:05.53#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.03:58:05.53#ibcon#[27=AT05-04\r\n] 2006.286.03:58:05.53#ibcon#*before write, iclass 30, count 2 2006.286.03:58:05.53#ibcon#enter sib2, iclass 30, count 2 2006.286.03:58:05.53#ibcon#flushed, iclass 30, count 2 2006.286.03:58:05.53#ibcon#about to write, iclass 30, count 2 2006.286.03:58:05.53#ibcon#wrote, iclass 30, count 2 2006.286.03:58:05.53#ibcon#about to read 3, iclass 30, count 2 2006.286.03:58:05.56#ibcon#read 3, iclass 30, count 2 2006.286.03:58:05.56#ibcon#about to read 4, iclass 30, count 2 2006.286.03:58:05.56#ibcon#read 4, iclass 30, count 2 2006.286.03:58:05.56#ibcon#about to read 5, iclass 30, count 2 2006.286.03:58:05.56#ibcon#read 5, iclass 30, count 2 2006.286.03:58:05.56#ibcon#about to read 6, iclass 30, count 2 2006.286.03:58:05.56#ibcon#read 6, iclass 30, count 2 2006.286.03:58:05.56#ibcon#end of sib2, iclass 30, count 2 2006.286.03:58:05.56#ibcon#*after write, iclass 30, count 2 2006.286.03:58:05.56#ibcon#*before return 0, iclass 30, count 2 2006.286.03:58:05.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:58:05.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.03:58:05.56#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.03:58:05.56#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:05.56#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:58:05.68#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:58:05.68#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:58:05.68#ibcon#enter wrdev, iclass 30, count 0 2006.286.03:58:05.68#ibcon#first serial, iclass 30, count 0 2006.286.03:58:05.68#ibcon#enter sib2, iclass 30, count 0 2006.286.03:58:05.68#ibcon#flushed, iclass 30, count 0 2006.286.03:58:05.68#ibcon#about to write, iclass 30, count 0 2006.286.03:58:05.68#ibcon#wrote, iclass 30, count 0 2006.286.03:58:05.68#ibcon#about to read 3, iclass 30, count 0 2006.286.03:58:05.70#ibcon#read 3, iclass 30, count 0 2006.286.03:58:05.70#ibcon#about to read 4, iclass 30, count 0 2006.286.03:58:05.70#ibcon#read 4, iclass 30, count 0 2006.286.03:58:05.70#ibcon#about to read 5, iclass 30, count 0 2006.286.03:58:05.70#ibcon#read 5, iclass 30, count 0 2006.286.03:58:05.70#ibcon#about to read 6, iclass 30, count 0 2006.286.03:58:05.70#ibcon#read 6, iclass 30, count 0 2006.286.03:58:05.70#ibcon#end of sib2, iclass 30, count 0 2006.286.03:58:05.70#ibcon#*mode == 0, iclass 30, count 0 2006.286.03:58:05.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.03:58:05.70#ibcon#[27=USB\r\n] 2006.286.03:58:05.70#ibcon#*before write, iclass 30, count 0 2006.286.03:58:05.70#ibcon#enter sib2, iclass 30, count 0 2006.286.03:58:05.70#ibcon#flushed, iclass 30, count 0 2006.286.03:58:05.70#ibcon#about to write, iclass 30, count 0 2006.286.03:58:05.70#ibcon#wrote, iclass 30, count 0 2006.286.03:58:05.70#ibcon#about to read 3, iclass 30, count 0 2006.286.03:58:05.73#ibcon#read 3, iclass 30, count 0 2006.286.03:58:05.73#ibcon#about to read 4, iclass 30, count 0 2006.286.03:58:05.73#ibcon#read 4, iclass 30, count 0 2006.286.03:58:05.73#ibcon#about to read 5, iclass 30, count 0 2006.286.03:58:05.73#ibcon#read 5, iclass 30, count 0 2006.286.03:58:05.73#ibcon#about to read 6, iclass 30, count 0 2006.286.03:58:05.73#ibcon#read 6, iclass 30, count 0 2006.286.03:58:05.73#ibcon#end of sib2, iclass 30, count 0 2006.286.03:58:05.73#ibcon#*after write, iclass 30, count 0 2006.286.03:58:05.73#ibcon#*before return 0, iclass 30, count 0 2006.286.03:58:05.73#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:58:05.73#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.03:58:05.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.03:58:05.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.03:58:05.73$vck44/vblo=6,719.99 2006.286.03:58:05.73#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.03:58:05.73#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.03:58:05.73#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:05.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:58:05.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:58:05.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:58:05.73#ibcon#enter wrdev, iclass 32, count 0 2006.286.03:58:05.73#ibcon#first serial, iclass 32, count 0 2006.286.03:58:05.73#ibcon#enter sib2, iclass 32, count 0 2006.286.03:58:05.73#ibcon#flushed, iclass 32, count 0 2006.286.03:58:05.73#ibcon#about to write, iclass 32, count 0 2006.286.03:58:05.73#ibcon#wrote, iclass 32, count 0 2006.286.03:58:05.73#ibcon#about to read 3, iclass 32, count 0 2006.286.03:58:05.75#ibcon#read 3, iclass 32, count 0 2006.286.03:58:05.79#ibcon#about to read 4, iclass 32, count 0 2006.286.03:58:05.79#ibcon#read 4, iclass 32, count 0 2006.286.03:58:05.79#ibcon#about to read 5, iclass 32, count 0 2006.286.03:58:05.79#ibcon#read 5, iclass 32, count 0 2006.286.03:58:05.79#ibcon#about to read 6, iclass 32, count 0 2006.286.03:58:05.79#ibcon#read 6, iclass 32, count 0 2006.286.03:58:05.79#ibcon#end of sib2, iclass 32, count 0 2006.286.03:58:05.79#ibcon#*mode == 0, iclass 32, count 0 2006.286.03:58:05.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.03:58:05.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.03:58:05.79#ibcon#*before write, iclass 32, count 0 2006.286.03:58:05.79#ibcon#enter sib2, iclass 32, count 0 2006.286.03:58:05.79#ibcon#flushed, iclass 32, count 0 2006.286.03:58:05.79#ibcon#about to write, iclass 32, count 0 2006.286.03:58:05.79#ibcon#wrote, iclass 32, count 0 2006.286.03:58:05.79#ibcon#about to read 3, iclass 32, count 0 2006.286.03:58:05.83#ibcon#read 3, iclass 32, count 0 2006.286.03:58:05.83#ibcon#about to read 4, iclass 32, count 0 2006.286.03:58:05.83#ibcon#read 4, iclass 32, count 0 2006.286.03:58:05.83#ibcon#about to read 5, iclass 32, count 0 2006.286.03:58:05.83#ibcon#read 5, iclass 32, count 0 2006.286.03:58:05.83#ibcon#about to read 6, iclass 32, count 0 2006.286.03:58:05.83#ibcon#read 6, iclass 32, count 0 2006.286.03:58:05.83#ibcon#end of sib2, iclass 32, count 0 2006.286.03:58:05.83#ibcon#*after write, iclass 32, count 0 2006.286.03:58:05.83#ibcon#*before return 0, iclass 32, count 0 2006.286.03:58:05.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:58:05.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.03:58:05.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.03:58:05.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.03:58:05.83$vck44/vb=6,3 2006.286.03:58:05.83#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.03:58:05.83#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.03:58:05.83#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:05.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:58:05.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:58:05.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:58:05.85#ibcon#enter wrdev, iclass 34, count 2 2006.286.03:58:05.85#ibcon#first serial, iclass 34, count 2 2006.286.03:58:05.85#ibcon#enter sib2, iclass 34, count 2 2006.286.03:58:05.85#ibcon#flushed, iclass 34, count 2 2006.286.03:58:05.85#ibcon#about to write, iclass 34, count 2 2006.286.03:58:05.85#ibcon#wrote, iclass 34, count 2 2006.286.03:58:05.85#ibcon#about to read 3, iclass 34, count 2 2006.286.03:58:05.87#ibcon#read 3, iclass 34, count 2 2006.286.03:58:05.87#ibcon#about to read 4, iclass 34, count 2 2006.286.03:58:05.87#ibcon#read 4, iclass 34, count 2 2006.286.03:58:05.87#ibcon#about to read 5, iclass 34, count 2 2006.286.03:58:05.87#ibcon#read 5, iclass 34, count 2 2006.286.03:58:05.87#ibcon#about to read 6, iclass 34, count 2 2006.286.03:58:05.87#ibcon#read 6, iclass 34, count 2 2006.286.03:58:05.87#ibcon#end of sib2, iclass 34, count 2 2006.286.03:58:05.87#ibcon#*mode == 0, iclass 34, count 2 2006.286.03:58:05.87#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.03:58:05.87#ibcon#[27=AT06-03\r\n] 2006.286.03:58:05.87#ibcon#*before write, iclass 34, count 2 2006.286.03:58:05.87#ibcon#enter sib2, iclass 34, count 2 2006.286.03:58:05.87#ibcon#flushed, iclass 34, count 2 2006.286.03:58:05.87#ibcon#about to write, iclass 34, count 2 2006.286.03:58:05.87#ibcon#wrote, iclass 34, count 2 2006.286.03:58:05.87#ibcon#about to read 3, iclass 34, count 2 2006.286.03:58:05.90#ibcon#read 3, iclass 34, count 2 2006.286.03:58:05.90#ibcon#about to read 4, iclass 34, count 2 2006.286.03:58:05.90#ibcon#read 4, iclass 34, count 2 2006.286.03:58:05.90#ibcon#about to read 5, iclass 34, count 2 2006.286.03:58:05.90#ibcon#read 5, iclass 34, count 2 2006.286.03:58:05.90#ibcon#about to read 6, iclass 34, count 2 2006.286.03:58:05.90#ibcon#read 6, iclass 34, count 2 2006.286.03:58:05.90#ibcon#end of sib2, iclass 34, count 2 2006.286.03:58:05.90#ibcon#*after write, iclass 34, count 2 2006.286.03:58:05.90#ibcon#*before return 0, iclass 34, count 2 2006.286.03:58:05.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:58:05.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.03:58:05.90#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.03:58:05.90#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:05.90#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:58:06.02#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:58:06.02#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:58:06.02#ibcon#enter wrdev, iclass 34, count 0 2006.286.03:58:06.02#ibcon#first serial, iclass 34, count 0 2006.286.03:58:06.02#ibcon#enter sib2, iclass 34, count 0 2006.286.03:58:06.02#ibcon#flushed, iclass 34, count 0 2006.286.03:58:06.02#ibcon#about to write, iclass 34, count 0 2006.286.03:58:06.02#ibcon#wrote, iclass 34, count 0 2006.286.03:58:06.02#ibcon#about to read 3, iclass 34, count 0 2006.286.03:58:06.04#ibcon#read 3, iclass 34, count 0 2006.286.03:58:06.04#ibcon#about to read 4, iclass 34, count 0 2006.286.03:58:06.04#ibcon#read 4, iclass 34, count 0 2006.286.03:58:06.04#ibcon#about to read 5, iclass 34, count 0 2006.286.03:58:06.04#ibcon#read 5, iclass 34, count 0 2006.286.03:58:06.04#ibcon#about to read 6, iclass 34, count 0 2006.286.03:58:06.04#ibcon#read 6, iclass 34, count 0 2006.286.03:58:06.04#ibcon#end of sib2, iclass 34, count 0 2006.286.03:58:06.04#ibcon#*mode == 0, iclass 34, count 0 2006.286.03:58:06.04#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.03:58:06.04#ibcon#[27=USB\r\n] 2006.286.03:58:06.04#ibcon#*before write, iclass 34, count 0 2006.286.03:58:06.04#ibcon#enter sib2, iclass 34, count 0 2006.286.03:58:06.04#ibcon#flushed, iclass 34, count 0 2006.286.03:58:06.04#ibcon#about to write, iclass 34, count 0 2006.286.03:58:06.04#ibcon#wrote, iclass 34, count 0 2006.286.03:58:06.04#ibcon#about to read 3, iclass 34, count 0 2006.286.03:58:06.07#ibcon#read 3, iclass 34, count 0 2006.286.03:58:06.07#ibcon#about to read 4, iclass 34, count 0 2006.286.03:58:06.07#ibcon#read 4, iclass 34, count 0 2006.286.03:58:06.07#ibcon#about to read 5, iclass 34, count 0 2006.286.03:58:06.07#ibcon#read 5, iclass 34, count 0 2006.286.03:58:06.07#ibcon#about to read 6, iclass 34, count 0 2006.286.03:58:06.07#ibcon#read 6, iclass 34, count 0 2006.286.03:58:06.07#ibcon#end of sib2, iclass 34, count 0 2006.286.03:58:06.07#ibcon#*after write, iclass 34, count 0 2006.286.03:58:06.07#ibcon#*before return 0, iclass 34, count 0 2006.286.03:58:06.07#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:58:06.07#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.03:58:06.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.03:58:06.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.03:58:06.07$vck44/vblo=7,734.99 2006.286.03:58:06.07#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.03:58:06.07#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.03:58:06.07#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:06.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:58:06.07#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:58:06.07#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:58:06.07#ibcon#enter wrdev, iclass 36, count 0 2006.286.03:58:06.07#ibcon#first serial, iclass 36, count 0 2006.286.03:58:06.07#ibcon#enter sib2, iclass 36, count 0 2006.286.03:58:06.07#ibcon#flushed, iclass 36, count 0 2006.286.03:58:06.07#ibcon#about to write, iclass 36, count 0 2006.286.03:58:06.07#ibcon#wrote, iclass 36, count 0 2006.286.03:58:06.07#ibcon#about to read 3, iclass 36, count 0 2006.286.03:58:06.09#ibcon#read 3, iclass 36, count 0 2006.286.03:58:06.09#ibcon#about to read 4, iclass 36, count 0 2006.286.03:58:06.09#ibcon#read 4, iclass 36, count 0 2006.286.03:58:06.09#ibcon#about to read 5, iclass 36, count 0 2006.286.03:58:06.09#ibcon#read 5, iclass 36, count 0 2006.286.03:58:06.09#ibcon#about to read 6, iclass 36, count 0 2006.286.03:58:06.09#ibcon#read 6, iclass 36, count 0 2006.286.03:58:06.09#ibcon#end of sib2, iclass 36, count 0 2006.286.03:58:06.09#ibcon#*mode == 0, iclass 36, count 0 2006.286.03:58:06.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.03:58:06.09#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.03:58:06.09#ibcon#*before write, iclass 36, count 0 2006.286.03:58:06.09#ibcon#enter sib2, iclass 36, count 0 2006.286.03:58:06.09#ibcon#flushed, iclass 36, count 0 2006.286.03:58:06.09#ibcon#about to write, iclass 36, count 0 2006.286.03:58:06.09#ibcon#wrote, iclass 36, count 0 2006.286.03:58:06.09#ibcon#about to read 3, iclass 36, count 0 2006.286.03:58:06.13#ibcon#read 3, iclass 36, count 0 2006.286.03:58:06.13#ibcon#about to read 4, iclass 36, count 0 2006.286.03:58:06.13#ibcon#read 4, iclass 36, count 0 2006.286.03:58:06.13#ibcon#about to read 5, iclass 36, count 0 2006.286.03:58:06.13#ibcon#read 5, iclass 36, count 0 2006.286.03:58:06.13#ibcon#about to read 6, iclass 36, count 0 2006.286.03:58:06.13#ibcon#read 6, iclass 36, count 0 2006.286.03:58:06.13#ibcon#end of sib2, iclass 36, count 0 2006.286.03:58:06.13#ibcon#*after write, iclass 36, count 0 2006.286.03:58:06.13#ibcon#*before return 0, iclass 36, count 0 2006.286.03:58:06.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:58:06.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.03:58:06.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.03:58:06.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.03:58:06.13$vck44/vb=7,4 2006.286.03:58:06.13#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.03:58:06.13#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.03:58:06.13#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:06.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:58:06.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:58:06.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:58:06.19#ibcon#enter wrdev, iclass 38, count 2 2006.286.03:58:06.19#ibcon#first serial, iclass 38, count 2 2006.286.03:58:06.19#ibcon#enter sib2, iclass 38, count 2 2006.286.03:58:06.19#ibcon#flushed, iclass 38, count 2 2006.286.03:58:06.19#ibcon#about to write, iclass 38, count 2 2006.286.03:58:06.19#ibcon#wrote, iclass 38, count 2 2006.286.03:58:06.19#ibcon#about to read 3, iclass 38, count 2 2006.286.03:58:06.21#ibcon#read 3, iclass 38, count 2 2006.286.03:58:06.21#ibcon#about to read 4, iclass 38, count 2 2006.286.03:58:06.21#ibcon#read 4, iclass 38, count 2 2006.286.03:58:06.21#ibcon#about to read 5, iclass 38, count 2 2006.286.03:58:06.21#ibcon#read 5, iclass 38, count 2 2006.286.03:58:06.21#ibcon#about to read 6, iclass 38, count 2 2006.286.03:58:06.21#ibcon#read 6, iclass 38, count 2 2006.286.03:58:06.21#ibcon#end of sib2, iclass 38, count 2 2006.286.03:58:06.21#ibcon#*mode == 0, iclass 38, count 2 2006.286.03:58:06.21#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.03:58:06.21#ibcon#[27=AT07-04\r\n] 2006.286.03:58:06.21#ibcon#*before write, iclass 38, count 2 2006.286.03:58:06.21#ibcon#enter sib2, iclass 38, count 2 2006.286.03:58:06.21#ibcon#flushed, iclass 38, count 2 2006.286.03:58:06.21#ibcon#about to write, iclass 38, count 2 2006.286.03:58:06.21#ibcon#wrote, iclass 38, count 2 2006.286.03:58:06.21#ibcon#about to read 3, iclass 38, count 2 2006.286.03:58:06.24#ibcon#read 3, iclass 38, count 2 2006.286.03:58:06.24#ibcon#about to read 4, iclass 38, count 2 2006.286.03:58:06.24#ibcon#read 4, iclass 38, count 2 2006.286.03:58:06.24#ibcon#about to read 5, iclass 38, count 2 2006.286.03:58:06.24#ibcon#read 5, iclass 38, count 2 2006.286.03:58:06.24#ibcon#about to read 6, iclass 38, count 2 2006.286.03:58:06.24#ibcon#read 6, iclass 38, count 2 2006.286.03:58:06.24#ibcon#end of sib2, iclass 38, count 2 2006.286.03:58:06.24#ibcon#*after write, iclass 38, count 2 2006.286.03:58:06.24#ibcon#*before return 0, iclass 38, count 2 2006.286.03:58:06.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:58:06.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.03:58:06.24#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.03:58:06.24#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:06.24#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:58:06.36#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:58:06.36#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:58:06.36#ibcon#enter wrdev, iclass 38, count 0 2006.286.03:58:06.36#ibcon#first serial, iclass 38, count 0 2006.286.03:58:06.36#ibcon#enter sib2, iclass 38, count 0 2006.286.03:58:06.36#ibcon#flushed, iclass 38, count 0 2006.286.03:58:06.36#ibcon#about to write, iclass 38, count 0 2006.286.03:58:06.36#ibcon#wrote, iclass 38, count 0 2006.286.03:58:06.36#ibcon#about to read 3, iclass 38, count 0 2006.286.03:58:06.38#ibcon#read 3, iclass 38, count 0 2006.286.03:58:06.38#ibcon#about to read 4, iclass 38, count 0 2006.286.03:58:06.38#ibcon#read 4, iclass 38, count 0 2006.286.03:58:06.38#ibcon#about to read 5, iclass 38, count 0 2006.286.03:58:06.38#ibcon#read 5, iclass 38, count 0 2006.286.03:58:06.38#ibcon#about to read 6, iclass 38, count 0 2006.286.03:58:06.38#ibcon#read 6, iclass 38, count 0 2006.286.03:58:06.38#ibcon#end of sib2, iclass 38, count 0 2006.286.03:58:06.38#ibcon#*mode == 0, iclass 38, count 0 2006.286.03:58:06.38#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.03:58:06.38#ibcon#[27=USB\r\n] 2006.286.03:58:06.38#ibcon#*before write, iclass 38, count 0 2006.286.03:58:06.38#ibcon#enter sib2, iclass 38, count 0 2006.286.03:58:06.38#ibcon#flushed, iclass 38, count 0 2006.286.03:58:06.38#ibcon#about to write, iclass 38, count 0 2006.286.03:58:06.38#ibcon#wrote, iclass 38, count 0 2006.286.03:58:06.38#ibcon#about to read 3, iclass 38, count 0 2006.286.03:58:06.41#ibcon#read 3, iclass 38, count 0 2006.286.03:58:06.41#ibcon#about to read 4, iclass 38, count 0 2006.286.03:58:06.41#ibcon#read 4, iclass 38, count 0 2006.286.03:58:06.41#ibcon#about to read 5, iclass 38, count 0 2006.286.03:58:06.41#ibcon#read 5, iclass 38, count 0 2006.286.03:58:06.41#ibcon#about to read 6, iclass 38, count 0 2006.286.03:58:06.41#ibcon#read 6, iclass 38, count 0 2006.286.03:58:06.41#ibcon#end of sib2, iclass 38, count 0 2006.286.03:58:06.41#ibcon#*after write, iclass 38, count 0 2006.286.03:58:06.41#ibcon#*before return 0, iclass 38, count 0 2006.286.03:58:06.41#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:58:06.41#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.03:58:06.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.03:58:06.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.03:58:06.41$vck44/vblo=8,744.99 2006.286.03:58:06.41#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.03:58:06.41#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.03:58:06.41#ibcon#ireg 17 cls_cnt 0 2006.286.03:58:06.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:58:06.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:58:06.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:58:06.41#ibcon#enter wrdev, iclass 40, count 0 2006.286.03:58:06.41#ibcon#first serial, iclass 40, count 0 2006.286.03:58:06.41#ibcon#enter sib2, iclass 40, count 0 2006.286.03:58:06.41#ibcon#flushed, iclass 40, count 0 2006.286.03:58:06.41#ibcon#about to write, iclass 40, count 0 2006.286.03:58:06.41#ibcon#wrote, iclass 40, count 0 2006.286.03:58:06.41#ibcon#about to read 3, iclass 40, count 0 2006.286.03:58:06.43#ibcon#read 3, iclass 40, count 0 2006.286.03:58:06.43#ibcon#about to read 4, iclass 40, count 0 2006.286.03:58:06.43#ibcon#read 4, iclass 40, count 0 2006.286.03:58:06.43#ibcon#about to read 5, iclass 40, count 0 2006.286.03:58:06.43#ibcon#read 5, iclass 40, count 0 2006.286.03:58:06.43#ibcon#about to read 6, iclass 40, count 0 2006.286.03:58:06.43#ibcon#read 6, iclass 40, count 0 2006.286.03:58:06.43#ibcon#end of sib2, iclass 40, count 0 2006.286.03:58:06.43#ibcon#*mode == 0, iclass 40, count 0 2006.286.03:58:06.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.03:58:06.43#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.03:58:06.43#ibcon#*before write, iclass 40, count 0 2006.286.03:58:06.43#ibcon#enter sib2, iclass 40, count 0 2006.286.03:58:06.43#ibcon#flushed, iclass 40, count 0 2006.286.03:58:06.43#ibcon#about to write, iclass 40, count 0 2006.286.03:58:06.43#ibcon#wrote, iclass 40, count 0 2006.286.03:58:06.43#ibcon#about to read 3, iclass 40, count 0 2006.286.03:58:06.47#ibcon#read 3, iclass 40, count 0 2006.286.03:58:06.47#ibcon#about to read 4, iclass 40, count 0 2006.286.03:58:06.47#ibcon#read 4, iclass 40, count 0 2006.286.03:58:06.47#ibcon#about to read 5, iclass 40, count 0 2006.286.03:58:06.47#ibcon#read 5, iclass 40, count 0 2006.286.03:58:06.47#ibcon#about to read 6, iclass 40, count 0 2006.286.03:58:06.47#ibcon#read 6, iclass 40, count 0 2006.286.03:58:06.47#ibcon#end of sib2, iclass 40, count 0 2006.286.03:58:06.47#ibcon#*after write, iclass 40, count 0 2006.286.03:58:06.47#ibcon#*before return 0, iclass 40, count 0 2006.286.03:58:06.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:58:06.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.03:58:06.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.03:58:06.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.03:58:06.47$vck44/vb=8,4 2006.286.03:58:06.47#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.03:58:06.47#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.03:58:06.47#ibcon#ireg 11 cls_cnt 2 2006.286.03:58:06.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:58:06.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:58:06.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:58:06.53#ibcon#enter wrdev, iclass 4, count 2 2006.286.03:58:06.53#ibcon#first serial, iclass 4, count 2 2006.286.03:58:06.53#ibcon#enter sib2, iclass 4, count 2 2006.286.03:58:06.53#ibcon#flushed, iclass 4, count 2 2006.286.03:58:06.53#ibcon#about to write, iclass 4, count 2 2006.286.03:58:06.53#ibcon#wrote, iclass 4, count 2 2006.286.03:58:06.53#ibcon#about to read 3, iclass 4, count 2 2006.286.03:58:06.55#ibcon#read 3, iclass 4, count 2 2006.286.03:58:06.55#ibcon#about to read 4, iclass 4, count 2 2006.286.03:58:06.55#ibcon#read 4, iclass 4, count 2 2006.286.03:58:06.55#ibcon#about to read 5, iclass 4, count 2 2006.286.03:58:06.55#ibcon#read 5, iclass 4, count 2 2006.286.03:58:06.55#ibcon#about to read 6, iclass 4, count 2 2006.286.03:58:06.55#ibcon#read 6, iclass 4, count 2 2006.286.03:58:06.55#ibcon#end of sib2, iclass 4, count 2 2006.286.03:58:06.55#ibcon#*mode == 0, iclass 4, count 2 2006.286.03:58:06.55#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.03:58:06.55#ibcon#[27=AT08-04\r\n] 2006.286.03:58:06.55#ibcon#*before write, iclass 4, count 2 2006.286.03:58:06.55#ibcon#enter sib2, iclass 4, count 2 2006.286.03:58:06.55#ibcon#flushed, iclass 4, count 2 2006.286.03:58:06.55#ibcon#about to write, iclass 4, count 2 2006.286.03:58:06.55#ibcon#wrote, iclass 4, count 2 2006.286.03:58:06.55#ibcon#about to read 3, iclass 4, count 2 2006.286.03:58:06.58#ibcon#read 3, iclass 4, count 2 2006.286.03:58:06.58#ibcon#about to read 4, iclass 4, count 2 2006.286.03:58:06.58#ibcon#read 4, iclass 4, count 2 2006.286.03:58:06.58#ibcon#about to read 5, iclass 4, count 2 2006.286.03:58:06.58#ibcon#read 5, iclass 4, count 2 2006.286.03:58:06.58#ibcon#about to read 6, iclass 4, count 2 2006.286.03:58:06.58#ibcon#read 6, iclass 4, count 2 2006.286.03:58:06.58#ibcon#end of sib2, iclass 4, count 2 2006.286.03:58:06.58#ibcon#*after write, iclass 4, count 2 2006.286.03:58:06.58#ibcon#*before return 0, iclass 4, count 2 2006.286.03:58:06.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:58:06.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.03:58:06.58#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.03:58:06.58#ibcon#ireg 7 cls_cnt 0 2006.286.03:58:06.58#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:58:06.70#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:58:06.70#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:58:06.70#ibcon#enter wrdev, iclass 4, count 0 2006.286.03:58:06.70#ibcon#first serial, iclass 4, count 0 2006.286.03:58:06.70#ibcon#enter sib2, iclass 4, count 0 2006.286.03:58:06.70#ibcon#flushed, iclass 4, count 0 2006.286.03:58:06.70#ibcon#about to write, iclass 4, count 0 2006.286.03:58:06.70#ibcon#wrote, iclass 4, count 0 2006.286.03:58:06.70#ibcon#about to read 3, iclass 4, count 0 2006.286.03:58:06.72#ibcon#read 3, iclass 4, count 0 2006.286.03:58:06.72#ibcon#about to read 4, iclass 4, count 0 2006.286.03:58:06.72#ibcon#read 4, iclass 4, count 0 2006.286.03:58:06.72#ibcon#about to read 5, iclass 4, count 0 2006.286.03:58:06.72#ibcon#read 5, iclass 4, count 0 2006.286.03:58:06.72#ibcon#about to read 6, iclass 4, count 0 2006.286.03:58:06.72#ibcon#read 6, iclass 4, count 0 2006.286.03:58:06.72#ibcon#end of sib2, iclass 4, count 0 2006.286.03:58:06.72#ibcon#*mode == 0, iclass 4, count 0 2006.286.03:58:06.72#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.03:58:06.72#ibcon#[27=USB\r\n] 2006.286.03:58:06.72#ibcon#*before write, iclass 4, count 0 2006.286.03:58:06.72#ibcon#enter sib2, iclass 4, count 0 2006.286.03:58:06.72#ibcon#flushed, iclass 4, count 0 2006.286.03:58:06.72#ibcon#about to write, iclass 4, count 0 2006.286.03:58:06.72#ibcon#wrote, iclass 4, count 0 2006.286.03:58:06.72#ibcon#about to read 3, iclass 4, count 0 2006.286.03:58:06.75#ibcon#read 3, iclass 4, count 0 2006.286.03:58:06.75#ibcon#about to read 4, iclass 4, count 0 2006.286.03:58:06.75#ibcon#read 4, iclass 4, count 0 2006.286.03:58:06.75#ibcon#about to read 5, iclass 4, count 0 2006.286.03:58:06.75#ibcon#read 5, iclass 4, count 0 2006.286.03:58:06.75#ibcon#about to read 6, iclass 4, count 0 2006.286.03:58:06.75#ibcon#read 6, iclass 4, count 0 2006.286.03:58:06.75#ibcon#end of sib2, iclass 4, count 0 2006.286.03:58:06.75#ibcon#*after write, iclass 4, count 0 2006.286.03:58:06.75#ibcon#*before return 0, iclass 4, count 0 2006.286.03:58:06.75#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:58:06.75#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.03:58:06.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.03:58:06.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.03:58:06.75$vck44/vabw=wide 2006.286.03:58:06.75#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.03:58:06.75#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.03:58:06.75#ibcon#ireg 8 cls_cnt 0 2006.286.03:58:06.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:58:06.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:58:06.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:58:06.75#ibcon#enter wrdev, iclass 6, count 0 2006.286.03:58:06.75#ibcon#first serial, iclass 6, count 0 2006.286.03:58:06.75#ibcon#enter sib2, iclass 6, count 0 2006.286.03:58:06.75#ibcon#flushed, iclass 6, count 0 2006.286.03:58:06.75#ibcon#about to write, iclass 6, count 0 2006.286.03:58:06.75#ibcon#wrote, iclass 6, count 0 2006.286.03:58:06.75#ibcon#about to read 3, iclass 6, count 0 2006.286.03:58:06.86#ibcon#read 3, iclass 6, count 0 2006.286.03:58:06.86#ibcon#about to read 4, iclass 6, count 0 2006.286.03:58:06.86#ibcon#read 4, iclass 6, count 0 2006.286.03:58:06.86#ibcon#about to read 5, iclass 6, count 0 2006.286.03:58:06.86#ibcon#read 5, iclass 6, count 0 2006.286.03:58:06.86#ibcon#about to read 6, iclass 6, count 0 2006.286.03:58:06.86#ibcon#read 6, iclass 6, count 0 2006.286.03:58:06.86#ibcon#end of sib2, iclass 6, count 0 2006.286.03:58:06.86#ibcon#*mode == 0, iclass 6, count 0 2006.286.03:58:06.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.03:58:06.86#ibcon#[25=BW32\r\n] 2006.286.03:58:06.86#ibcon#*before write, iclass 6, count 0 2006.286.03:58:06.86#ibcon#enter sib2, iclass 6, count 0 2006.286.03:58:06.86#ibcon#flushed, iclass 6, count 0 2006.286.03:58:06.86#ibcon#about to write, iclass 6, count 0 2006.286.03:58:06.86#ibcon#wrote, iclass 6, count 0 2006.286.03:58:06.86#ibcon#about to read 3, iclass 6, count 0 2006.286.03:58:06.89#ibcon#read 3, iclass 6, count 0 2006.286.03:58:06.89#ibcon#about to read 4, iclass 6, count 0 2006.286.03:58:06.89#ibcon#read 4, iclass 6, count 0 2006.286.03:58:06.89#ibcon#about to read 5, iclass 6, count 0 2006.286.03:58:06.89#ibcon#read 5, iclass 6, count 0 2006.286.03:58:06.89#ibcon#about to read 6, iclass 6, count 0 2006.286.03:58:06.89#ibcon#read 6, iclass 6, count 0 2006.286.03:58:06.89#ibcon#end of sib2, iclass 6, count 0 2006.286.03:58:06.89#ibcon#*after write, iclass 6, count 0 2006.286.03:58:06.89#ibcon#*before return 0, iclass 6, count 0 2006.286.03:58:06.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:58:06.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.03:58:06.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.03:58:06.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.03:58:06.89$vck44/vbbw=wide 2006.286.03:58:06.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.03:58:06.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.03:58:06.89#ibcon#ireg 8 cls_cnt 0 2006.286.03:58:06.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:58:06.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:58:06.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:58:06.89#ibcon#enter wrdev, iclass 10, count 0 2006.286.03:58:06.89#ibcon#first serial, iclass 10, count 0 2006.286.03:58:06.89#ibcon#enter sib2, iclass 10, count 0 2006.286.03:58:06.89#ibcon#flushed, iclass 10, count 0 2006.286.03:58:06.89#ibcon#about to write, iclass 10, count 0 2006.286.03:58:06.89#ibcon#wrote, iclass 10, count 0 2006.286.03:58:06.89#ibcon#about to read 3, iclass 10, count 0 2006.286.03:58:06.91#ibcon#read 3, iclass 10, count 0 2006.286.03:58:06.91#ibcon#about to read 4, iclass 10, count 0 2006.286.03:58:06.91#ibcon#read 4, iclass 10, count 0 2006.286.03:58:06.91#ibcon#about to read 5, iclass 10, count 0 2006.286.03:58:06.91#ibcon#read 5, iclass 10, count 0 2006.286.03:58:06.91#ibcon#about to read 6, iclass 10, count 0 2006.286.03:58:06.91#ibcon#read 6, iclass 10, count 0 2006.286.03:58:06.91#ibcon#end of sib2, iclass 10, count 0 2006.286.03:58:06.91#ibcon#*mode == 0, iclass 10, count 0 2006.286.03:58:06.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.03:58:06.91#ibcon#[27=BW32\r\n] 2006.286.03:58:06.91#ibcon#*before write, iclass 10, count 0 2006.286.03:58:06.91#ibcon#enter sib2, iclass 10, count 0 2006.286.03:58:06.91#ibcon#flushed, iclass 10, count 0 2006.286.03:58:06.91#ibcon#about to write, iclass 10, count 0 2006.286.03:58:06.91#ibcon#wrote, iclass 10, count 0 2006.286.03:58:06.91#ibcon#about to read 3, iclass 10, count 0 2006.286.03:58:06.94#ibcon#read 3, iclass 10, count 0 2006.286.03:58:06.94#ibcon#about to read 4, iclass 10, count 0 2006.286.03:58:06.94#ibcon#read 4, iclass 10, count 0 2006.286.03:58:06.94#ibcon#about to read 5, iclass 10, count 0 2006.286.03:58:06.94#ibcon#read 5, iclass 10, count 0 2006.286.03:58:06.94#ibcon#about to read 6, iclass 10, count 0 2006.286.03:58:06.94#ibcon#read 6, iclass 10, count 0 2006.286.03:58:06.94#ibcon#end of sib2, iclass 10, count 0 2006.286.03:58:06.94#ibcon#*after write, iclass 10, count 0 2006.286.03:58:06.94#ibcon#*before return 0, iclass 10, count 0 2006.286.03:58:06.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:58:06.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.03:58:06.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.03:58:06.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.03:58:06.94$setupk4/ifdk4 2006.286.03:58:06.94$ifdk4/lo= 2006.286.03:58:06.94$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.03:58:06.94$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.03:58:06.94$ifdk4/patch= 2006.286.03:58:06.94$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.03:58:06.94$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.03:58:06.94$setupk4/!*+20s 2006.286.03:58:13.64#abcon#<5=/04 3.6 6.9 21.87 771015.0\r\n> 2006.286.03:58:13.66#abcon#{5=INTERFACE CLEAR} 2006.286.03:58:13.72#abcon#[5=S1D000X0/0*\r\n] 2006.286.03:58:16.13#trakl#Source acquired 2006.286.03:58:18.13#flagr#flagr/antenna,acquired 2006.286.03:58:20.59$setupk4/"tpicd 2006.286.03:58:20.59$setupk4/echo=off 2006.286.03:58:20.59$setupk4/xlog=off 2006.286.03:58:20.59:!2006.286.03:59:15 2006.286.03:59:15.00:preob 2006.286.03:59:16.14/onsource/TRACKING 2006.286.03:59:16.14:!2006.286.03:59:25 2006.286.03:59:25.00:"tape 2006.286.03:59:25.00:"st=record 2006.286.03:59:25.00:data_valid=on 2006.286.03:59:25.00:midob 2006.286.03:59:25.14/onsource/TRACKING 2006.286.03:59:25.14/wx/21.87,1014.9,76 2006.286.03:59:25.30/cable/+6.4955E-03 2006.286.03:59:26.39/va/01,07,usb,yes,31,34 2006.286.03:59:26.39/va/02,06,usb,yes,32,32 2006.286.03:59:26.39/va/03,07,usb,yes,31,33 2006.286.03:59:26.39/va/04,06,usb,yes,32,34 2006.286.03:59:26.39/va/05,03,usb,yes,32,32 2006.286.03:59:26.39/va/06,04,usb,yes,29,28 2006.286.03:59:26.39/va/07,04,usb,yes,29,30 2006.286.03:59:26.39/va/08,03,usb,yes,30,37 2006.286.03:59:26.62/valo/01,524.99,yes,locked 2006.286.03:59:26.62/valo/02,534.99,yes,locked 2006.286.03:59:26.62/valo/03,564.99,yes,locked 2006.286.03:59:26.62/valo/04,624.99,yes,locked 2006.286.03:59:26.62/valo/05,734.99,yes,locked 2006.286.03:59:26.62/valo/06,814.99,yes,locked 2006.286.03:59:26.62/valo/07,864.99,yes,locked 2006.286.03:59:26.62/valo/08,884.99,yes,locked 2006.286.03:59:27.71/vb/01,04,usb,yes,30,28 2006.286.03:59:27.71/vb/02,05,usb,yes,29,28 2006.286.03:59:27.71/vb/03,04,usb,yes,29,33 2006.286.03:59:27.71/vb/04,05,usb,yes,30,29 2006.286.03:59:27.71/vb/05,04,usb,yes,26,29 2006.286.03:59:27.71/vb/06,03,usb,yes,38,33 2006.286.03:59:27.71/vb/07,04,usb,yes,30,30 2006.286.03:59:27.71/vb/08,04,usb,yes,28,31 2006.286.03:59:27.94/vblo/01,629.99,yes,locked 2006.286.03:59:27.94/vblo/02,634.99,yes,locked 2006.286.03:59:27.94/vblo/03,649.99,yes,locked 2006.286.03:59:27.94/vblo/04,679.99,yes,locked 2006.286.03:59:27.94/vblo/05,709.99,yes,locked 2006.286.03:59:27.94/vblo/06,719.99,yes,locked 2006.286.03:59:27.94/vblo/07,734.99,yes,locked 2006.286.03:59:27.94/vblo/08,744.99,yes,locked 2006.286.03:59:28.09/vabw/8 2006.286.03:59:28.24/vbbw/8 2006.286.03:59:28.34/xfe/off,on,12.2 2006.286.03:59:28.72/ifatt/23,28,28,28 2006.286.03:59:29.07/fmout-gps/S +2.41E-07 2006.286.03:59:29.09:!2006.286.04:00:15 2006.286.04:00:15.01:data_valid=off 2006.286.04:00:15.01:"et 2006.286.04:00:15.01:!+3s 2006.286.04:00:18.02:"tape 2006.286.04:00:18.02:postob 2006.286.04:00:18.15/cable/+6.4955E-03 2006.286.04:00:18.15/wx/21.87,1014.9,77 2006.286.04:00:18.21/fmout-gps/S +2.41E-07 2006.286.04:00:18.21:scan_name=286-0404,jd0610,240 2006.286.04:00:18.21:source=1803+784,180045.68,782804.0,2000.0,cw 2006.286.04:00:19.14#flagr#flagr/antenna,new-source 2006.286.04:00:19.14:checkk5 2006.286.04:00:19.72/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:00:20.45/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:00:20.94/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:00:21.60/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:00:22.00/chk_obsdata//k5ts1/T2860359??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.04:00:22.45/chk_obsdata//k5ts2/T2860359??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.04:00:22.83/chk_obsdata//k5ts3/T2860359??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.04:00:23.28/chk_obsdata//k5ts4/T2860359??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.04:00:24.34/k5log//k5ts1_log_newline 2006.286.04:00:25.20/k5log//k5ts2_log_newline 2006.286.04:00:26.08/k5log//k5ts3_log_newline 2006.286.04:00:26.89/k5log//k5ts4_log_newline 2006.286.04:00:26.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:00:26.92:setupk4=1 2006.286.04:00:26.92$setupk4/echo=on 2006.286.04:00:26.92$setupk4/pcalon 2006.286.04:00:26.92$pcalon/"no phase cal control is implemented here 2006.286.04:00:26.92$setupk4/"tpicd=stop 2006.286.04:00:26.92$setupk4/"rec=synch_on 2006.286.04:00:26.92$setupk4/"rec_mode=128 2006.286.04:00:26.92$setupk4/!* 2006.286.04:00:26.92$setupk4/recpk4 2006.286.04:00:26.92$recpk4/recpatch= 2006.286.04:00:26.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:00:26.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:00:26.92$setupk4/vck44 2006.286.04:00:26.92$vck44/valo=1,524.99 2006.286.04:00:26.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.04:00:26.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.04:00:26.92#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:26.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:00:26.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:00:26.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:00:26.92#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:00:26.92#ibcon#first serial, iclass 35, count 0 2006.286.04:00:26.92#ibcon#enter sib2, iclass 35, count 0 2006.286.04:00:26.92#ibcon#flushed, iclass 35, count 0 2006.286.04:00:26.92#ibcon#about to write, iclass 35, count 0 2006.286.04:00:26.92#ibcon#wrote, iclass 35, count 0 2006.286.04:00:26.92#ibcon#about to read 3, iclass 35, count 0 2006.286.04:00:26.93#ibcon#read 3, iclass 35, count 0 2006.286.04:00:26.93#ibcon#about to read 4, iclass 35, count 0 2006.286.04:00:26.93#ibcon#read 4, iclass 35, count 0 2006.286.04:00:26.93#ibcon#about to read 5, iclass 35, count 0 2006.286.04:00:26.93#ibcon#read 5, iclass 35, count 0 2006.286.04:00:26.93#ibcon#about to read 6, iclass 35, count 0 2006.286.04:00:26.93#ibcon#read 6, iclass 35, count 0 2006.286.04:00:26.93#ibcon#end of sib2, iclass 35, count 0 2006.286.04:00:26.93#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:00:26.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:00:26.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:00:26.93#ibcon#*before write, iclass 35, count 0 2006.286.04:00:26.93#ibcon#enter sib2, iclass 35, count 0 2006.286.04:00:26.93#ibcon#flushed, iclass 35, count 0 2006.286.04:00:26.93#ibcon#about to write, iclass 35, count 0 2006.286.04:00:26.93#ibcon#wrote, iclass 35, count 0 2006.286.04:00:26.93#ibcon#about to read 3, iclass 35, count 0 2006.286.04:00:26.98#ibcon#read 3, iclass 35, count 0 2006.286.04:00:26.98#ibcon#about to read 4, iclass 35, count 0 2006.286.04:00:26.98#ibcon#read 4, iclass 35, count 0 2006.286.04:00:26.98#ibcon#about to read 5, iclass 35, count 0 2006.286.04:00:26.98#ibcon#read 5, iclass 35, count 0 2006.286.04:00:26.98#ibcon#about to read 6, iclass 35, count 0 2006.286.04:00:26.98#ibcon#read 6, iclass 35, count 0 2006.286.04:00:26.98#ibcon#end of sib2, iclass 35, count 0 2006.286.04:00:26.98#ibcon#*after write, iclass 35, count 0 2006.286.04:00:26.98#ibcon#*before return 0, iclass 35, count 0 2006.286.04:00:26.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:00:26.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:00:26.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:00:26.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:00:26.98$vck44/va=1,7 2006.286.04:00:26.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.04:00:26.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.04:00:26.98#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:26.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:00:26.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:00:26.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:00:26.98#ibcon#enter wrdev, iclass 37, count 2 2006.286.04:00:26.98#ibcon#first serial, iclass 37, count 2 2006.286.04:00:26.98#ibcon#enter sib2, iclass 37, count 2 2006.286.04:00:26.98#ibcon#flushed, iclass 37, count 2 2006.286.04:00:26.98#ibcon#about to write, iclass 37, count 2 2006.286.04:00:26.98#ibcon#wrote, iclass 37, count 2 2006.286.04:00:26.98#ibcon#about to read 3, iclass 37, count 2 2006.286.04:00:27.00#ibcon#read 3, iclass 37, count 2 2006.286.04:00:27.00#ibcon#about to read 4, iclass 37, count 2 2006.286.04:00:27.00#ibcon#read 4, iclass 37, count 2 2006.286.04:00:27.00#ibcon#about to read 5, iclass 37, count 2 2006.286.04:00:27.00#ibcon#read 5, iclass 37, count 2 2006.286.04:00:27.00#ibcon#about to read 6, iclass 37, count 2 2006.286.04:00:27.00#ibcon#read 6, iclass 37, count 2 2006.286.04:00:27.00#ibcon#end of sib2, iclass 37, count 2 2006.286.04:00:27.00#ibcon#*mode == 0, iclass 37, count 2 2006.286.04:00:27.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.04:00:27.00#ibcon#[25=AT01-07\r\n] 2006.286.04:00:27.00#ibcon#*before write, iclass 37, count 2 2006.286.04:00:27.00#ibcon#enter sib2, iclass 37, count 2 2006.286.04:00:27.00#ibcon#flushed, iclass 37, count 2 2006.286.04:00:27.00#ibcon#about to write, iclass 37, count 2 2006.286.04:00:27.00#ibcon#wrote, iclass 37, count 2 2006.286.04:00:27.00#ibcon#about to read 3, iclass 37, count 2 2006.286.04:00:27.03#ibcon#read 3, iclass 37, count 2 2006.286.04:00:27.03#ibcon#about to read 4, iclass 37, count 2 2006.286.04:00:27.03#ibcon#read 4, iclass 37, count 2 2006.286.04:00:27.03#ibcon#about to read 5, iclass 37, count 2 2006.286.04:00:27.03#ibcon#read 5, iclass 37, count 2 2006.286.04:00:27.03#ibcon#about to read 6, iclass 37, count 2 2006.286.04:00:27.03#ibcon#read 6, iclass 37, count 2 2006.286.04:00:27.03#ibcon#end of sib2, iclass 37, count 2 2006.286.04:00:27.03#ibcon#*after write, iclass 37, count 2 2006.286.04:00:27.03#ibcon#*before return 0, iclass 37, count 2 2006.286.04:00:27.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:00:27.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:00:27.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.04:00:27.03#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:27.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:00:27.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:00:27.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:00:27.15#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:00:27.15#ibcon#first serial, iclass 37, count 0 2006.286.04:00:27.15#ibcon#enter sib2, iclass 37, count 0 2006.286.04:00:27.15#ibcon#flushed, iclass 37, count 0 2006.286.04:00:27.15#ibcon#about to write, iclass 37, count 0 2006.286.04:00:27.15#ibcon#wrote, iclass 37, count 0 2006.286.04:00:27.15#ibcon#about to read 3, iclass 37, count 0 2006.286.04:00:27.17#ibcon#read 3, iclass 37, count 0 2006.286.04:00:27.17#ibcon#about to read 4, iclass 37, count 0 2006.286.04:00:27.17#ibcon#read 4, iclass 37, count 0 2006.286.04:00:27.17#ibcon#about to read 5, iclass 37, count 0 2006.286.04:00:27.17#ibcon#read 5, iclass 37, count 0 2006.286.04:00:27.17#ibcon#about to read 6, iclass 37, count 0 2006.286.04:00:27.17#ibcon#read 6, iclass 37, count 0 2006.286.04:00:27.17#ibcon#end of sib2, iclass 37, count 0 2006.286.04:00:27.17#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:00:27.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:00:27.17#ibcon#[25=USB\r\n] 2006.286.04:00:27.17#ibcon#*before write, iclass 37, count 0 2006.286.04:00:27.17#ibcon#enter sib2, iclass 37, count 0 2006.286.04:00:27.17#ibcon#flushed, iclass 37, count 0 2006.286.04:00:27.17#ibcon#about to write, iclass 37, count 0 2006.286.04:00:27.17#ibcon#wrote, iclass 37, count 0 2006.286.04:00:27.17#ibcon#about to read 3, iclass 37, count 0 2006.286.04:00:27.20#ibcon#read 3, iclass 37, count 0 2006.286.04:00:27.43#ibcon#about to read 4, iclass 37, count 0 2006.286.04:00:27.43#ibcon#read 4, iclass 37, count 0 2006.286.04:00:27.43#ibcon#about to read 5, iclass 37, count 0 2006.286.04:00:27.43#ibcon#read 5, iclass 37, count 0 2006.286.04:00:27.43#ibcon#about to read 6, iclass 37, count 0 2006.286.04:00:27.43#ibcon#read 6, iclass 37, count 0 2006.286.04:00:27.43#ibcon#end of sib2, iclass 37, count 0 2006.286.04:00:27.43#ibcon#*after write, iclass 37, count 0 2006.286.04:00:27.43#ibcon#*before return 0, iclass 37, count 0 2006.286.04:00:27.43#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:00:27.43#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:00:27.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:00:27.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:00:27.43$vck44/valo=2,534.99 2006.286.04:00:27.43#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.04:00:27.43#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.04:00:27.43#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:27.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:00:27.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:00:27.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:00:27.43#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:00:27.43#ibcon#first serial, iclass 39, count 0 2006.286.04:00:27.43#ibcon#enter sib2, iclass 39, count 0 2006.286.04:00:27.43#ibcon#flushed, iclass 39, count 0 2006.286.04:00:27.43#ibcon#about to write, iclass 39, count 0 2006.286.04:00:27.43#ibcon#wrote, iclass 39, count 0 2006.286.04:00:27.43#ibcon#about to read 3, iclass 39, count 0 2006.286.04:00:27.44#ibcon#read 3, iclass 39, count 0 2006.286.04:00:27.44#ibcon#about to read 4, iclass 39, count 0 2006.286.04:00:27.44#ibcon#read 4, iclass 39, count 0 2006.286.04:00:27.44#ibcon#about to read 5, iclass 39, count 0 2006.286.04:00:27.44#ibcon#read 5, iclass 39, count 0 2006.286.04:00:27.44#ibcon#about to read 6, iclass 39, count 0 2006.286.04:00:27.44#ibcon#read 6, iclass 39, count 0 2006.286.04:00:27.44#ibcon#end of sib2, iclass 39, count 0 2006.286.04:00:27.44#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:00:27.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:00:27.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:00:27.44#ibcon#*before write, iclass 39, count 0 2006.286.04:00:27.44#ibcon#enter sib2, iclass 39, count 0 2006.286.04:00:27.44#ibcon#flushed, iclass 39, count 0 2006.286.04:00:27.44#ibcon#about to write, iclass 39, count 0 2006.286.04:00:27.44#ibcon#wrote, iclass 39, count 0 2006.286.04:00:27.44#ibcon#about to read 3, iclass 39, count 0 2006.286.04:00:27.48#ibcon#read 3, iclass 39, count 0 2006.286.04:00:27.48#ibcon#about to read 4, iclass 39, count 0 2006.286.04:00:27.48#ibcon#read 4, iclass 39, count 0 2006.286.04:00:27.48#ibcon#about to read 5, iclass 39, count 0 2006.286.04:00:27.48#ibcon#read 5, iclass 39, count 0 2006.286.04:00:27.48#ibcon#about to read 6, iclass 39, count 0 2006.286.04:00:27.48#ibcon#read 6, iclass 39, count 0 2006.286.04:00:27.48#ibcon#end of sib2, iclass 39, count 0 2006.286.04:00:27.48#ibcon#*after write, iclass 39, count 0 2006.286.04:00:27.48#ibcon#*before return 0, iclass 39, count 0 2006.286.04:00:27.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:00:27.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:00:27.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:00:27.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:00:27.48$vck44/va=2,6 2006.286.04:00:27.48#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.04:00:27.48#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.04:00:27.48#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:27.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:00:27.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:00:27.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:00:27.55#ibcon#enter wrdev, iclass 3, count 2 2006.286.04:00:27.55#ibcon#first serial, iclass 3, count 2 2006.286.04:00:27.55#ibcon#enter sib2, iclass 3, count 2 2006.286.04:00:27.55#ibcon#flushed, iclass 3, count 2 2006.286.04:00:27.55#ibcon#about to write, iclass 3, count 2 2006.286.04:00:27.55#ibcon#wrote, iclass 3, count 2 2006.286.04:00:27.55#ibcon#about to read 3, iclass 3, count 2 2006.286.04:00:27.57#ibcon#read 3, iclass 3, count 2 2006.286.04:00:27.57#ibcon#about to read 4, iclass 3, count 2 2006.286.04:00:27.57#ibcon#read 4, iclass 3, count 2 2006.286.04:00:27.57#ibcon#about to read 5, iclass 3, count 2 2006.286.04:00:27.57#ibcon#read 5, iclass 3, count 2 2006.286.04:00:27.57#ibcon#about to read 6, iclass 3, count 2 2006.286.04:00:27.57#ibcon#read 6, iclass 3, count 2 2006.286.04:00:27.57#ibcon#end of sib2, iclass 3, count 2 2006.286.04:00:27.57#ibcon#*mode == 0, iclass 3, count 2 2006.286.04:00:27.57#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.04:00:27.57#ibcon#[25=AT02-06\r\n] 2006.286.04:00:27.57#ibcon#*before write, iclass 3, count 2 2006.286.04:00:27.57#ibcon#enter sib2, iclass 3, count 2 2006.286.04:00:27.57#ibcon#flushed, iclass 3, count 2 2006.286.04:00:27.57#ibcon#about to write, iclass 3, count 2 2006.286.04:00:27.57#ibcon#wrote, iclass 3, count 2 2006.286.04:00:27.57#ibcon#about to read 3, iclass 3, count 2 2006.286.04:00:27.60#ibcon#read 3, iclass 3, count 2 2006.286.04:00:27.60#ibcon#about to read 4, iclass 3, count 2 2006.286.04:00:27.60#ibcon#read 4, iclass 3, count 2 2006.286.04:00:27.60#ibcon#about to read 5, iclass 3, count 2 2006.286.04:00:27.60#ibcon#read 5, iclass 3, count 2 2006.286.04:00:27.60#ibcon#about to read 6, iclass 3, count 2 2006.286.04:00:27.60#ibcon#read 6, iclass 3, count 2 2006.286.04:00:27.60#ibcon#end of sib2, iclass 3, count 2 2006.286.04:00:27.60#ibcon#*after write, iclass 3, count 2 2006.286.04:00:27.60#ibcon#*before return 0, iclass 3, count 2 2006.286.04:00:27.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:00:27.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:00:27.60#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.04:00:27.60#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:27.60#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:00:27.72#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:00:27.72#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:00:27.72#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:00:27.72#ibcon#first serial, iclass 3, count 0 2006.286.04:00:27.72#ibcon#enter sib2, iclass 3, count 0 2006.286.04:00:27.72#ibcon#flushed, iclass 3, count 0 2006.286.04:00:27.72#ibcon#about to write, iclass 3, count 0 2006.286.04:00:27.72#ibcon#wrote, iclass 3, count 0 2006.286.04:00:27.72#ibcon#about to read 3, iclass 3, count 0 2006.286.04:00:27.74#ibcon#read 3, iclass 3, count 0 2006.286.04:00:27.74#ibcon#about to read 4, iclass 3, count 0 2006.286.04:00:27.74#ibcon#read 4, iclass 3, count 0 2006.286.04:00:27.74#ibcon#about to read 5, iclass 3, count 0 2006.286.04:00:27.74#ibcon#read 5, iclass 3, count 0 2006.286.04:00:27.74#ibcon#about to read 6, iclass 3, count 0 2006.286.04:00:27.74#ibcon#read 6, iclass 3, count 0 2006.286.04:00:27.74#ibcon#end of sib2, iclass 3, count 0 2006.286.04:00:27.74#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:00:27.74#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:00:27.74#ibcon#[25=USB\r\n] 2006.286.04:00:27.74#ibcon#*before write, iclass 3, count 0 2006.286.04:00:27.74#ibcon#enter sib2, iclass 3, count 0 2006.286.04:00:27.74#ibcon#flushed, iclass 3, count 0 2006.286.04:00:27.74#ibcon#about to write, iclass 3, count 0 2006.286.04:00:27.74#ibcon#wrote, iclass 3, count 0 2006.286.04:00:27.74#ibcon#about to read 3, iclass 3, count 0 2006.286.04:00:27.77#ibcon#read 3, iclass 3, count 0 2006.286.04:00:27.77#ibcon#about to read 4, iclass 3, count 0 2006.286.04:00:27.77#ibcon#read 4, iclass 3, count 0 2006.286.04:00:27.77#ibcon#about to read 5, iclass 3, count 0 2006.286.04:00:27.77#ibcon#read 5, iclass 3, count 0 2006.286.04:00:27.77#ibcon#about to read 6, iclass 3, count 0 2006.286.04:00:27.77#ibcon#read 6, iclass 3, count 0 2006.286.04:00:27.77#ibcon#end of sib2, iclass 3, count 0 2006.286.04:00:27.77#ibcon#*after write, iclass 3, count 0 2006.286.04:00:27.77#ibcon#*before return 0, iclass 3, count 0 2006.286.04:00:27.77#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:00:27.77#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:00:27.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:00:27.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:00:27.77$vck44/valo=3,564.99 2006.286.04:00:27.77#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.04:00:27.77#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.04:00:27.77#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:27.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:00:27.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:00:27.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:00:27.77#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:00:27.77#ibcon#first serial, iclass 5, count 0 2006.286.04:00:27.77#ibcon#enter sib2, iclass 5, count 0 2006.286.04:00:27.77#ibcon#flushed, iclass 5, count 0 2006.286.04:00:27.77#ibcon#about to write, iclass 5, count 0 2006.286.04:00:27.77#ibcon#wrote, iclass 5, count 0 2006.286.04:00:27.77#ibcon#about to read 3, iclass 5, count 0 2006.286.04:00:27.79#ibcon#read 3, iclass 5, count 0 2006.286.04:00:27.92#ibcon#about to read 4, iclass 5, count 0 2006.286.04:00:27.92#ibcon#read 4, iclass 5, count 0 2006.286.04:00:27.92#ibcon#about to read 5, iclass 5, count 0 2006.286.04:00:27.92#ibcon#read 5, iclass 5, count 0 2006.286.04:00:27.92#ibcon#about to read 6, iclass 5, count 0 2006.286.04:00:27.92#ibcon#read 6, iclass 5, count 0 2006.286.04:00:27.92#ibcon#end of sib2, iclass 5, count 0 2006.286.04:00:27.92#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:00:27.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:00:27.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:00:27.92#ibcon#*before write, iclass 5, count 0 2006.286.04:00:27.92#ibcon#enter sib2, iclass 5, count 0 2006.286.04:00:27.92#ibcon#flushed, iclass 5, count 0 2006.286.04:00:27.92#ibcon#about to write, iclass 5, count 0 2006.286.04:00:27.92#ibcon#wrote, iclass 5, count 0 2006.286.04:00:27.92#ibcon#about to read 3, iclass 5, count 0 2006.286.04:00:27.96#ibcon#read 3, iclass 5, count 0 2006.286.04:00:27.96#ibcon#about to read 4, iclass 5, count 0 2006.286.04:00:27.96#ibcon#read 4, iclass 5, count 0 2006.286.04:00:27.96#ibcon#about to read 5, iclass 5, count 0 2006.286.04:00:27.96#ibcon#read 5, iclass 5, count 0 2006.286.04:00:27.96#ibcon#about to read 6, iclass 5, count 0 2006.286.04:00:27.96#ibcon#read 6, iclass 5, count 0 2006.286.04:00:27.96#ibcon#end of sib2, iclass 5, count 0 2006.286.04:00:27.96#ibcon#*after write, iclass 5, count 0 2006.286.04:00:27.96#ibcon#*before return 0, iclass 5, count 0 2006.286.04:00:27.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:00:27.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:00:27.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:00:27.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:00:27.96$vck44/va=3,7 2006.286.04:00:27.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.04:00:27.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.04:00:27.96#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:27.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:00:27.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:00:27.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:00:27.96#ibcon#enter wrdev, iclass 7, count 2 2006.286.04:00:27.96#ibcon#first serial, iclass 7, count 2 2006.286.04:00:27.96#ibcon#enter sib2, iclass 7, count 2 2006.286.04:00:27.96#ibcon#flushed, iclass 7, count 2 2006.286.04:00:27.96#ibcon#about to write, iclass 7, count 2 2006.286.04:00:27.96#ibcon#wrote, iclass 7, count 2 2006.286.04:00:27.96#ibcon#about to read 3, iclass 7, count 2 2006.286.04:00:27.98#ibcon#read 3, iclass 7, count 2 2006.286.04:00:27.98#ibcon#about to read 4, iclass 7, count 2 2006.286.04:00:27.98#ibcon#read 4, iclass 7, count 2 2006.286.04:00:27.98#ibcon#about to read 5, iclass 7, count 2 2006.286.04:00:27.98#ibcon#read 5, iclass 7, count 2 2006.286.04:00:27.98#ibcon#about to read 6, iclass 7, count 2 2006.286.04:00:27.98#ibcon#read 6, iclass 7, count 2 2006.286.04:00:27.98#ibcon#end of sib2, iclass 7, count 2 2006.286.04:00:27.98#ibcon#*mode == 0, iclass 7, count 2 2006.286.04:00:27.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.04:00:27.98#ibcon#[25=AT03-07\r\n] 2006.286.04:00:27.98#ibcon#*before write, iclass 7, count 2 2006.286.04:00:27.98#ibcon#enter sib2, iclass 7, count 2 2006.286.04:00:27.98#ibcon#flushed, iclass 7, count 2 2006.286.04:00:27.98#ibcon#about to write, iclass 7, count 2 2006.286.04:00:27.98#ibcon#wrote, iclass 7, count 2 2006.286.04:00:27.98#ibcon#about to read 3, iclass 7, count 2 2006.286.04:00:28.01#ibcon#read 3, iclass 7, count 2 2006.286.04:00:28.01#ibcon#about to read 4, iclass 7, count 2 2006.286.04:00:28.01#ibcon#read 4, iclass 7, count 2 2006.286.04:00:28.01#ibcon#about to read 5, iclass 7, count 2 2006.286.04:00:28.01#ibcon#read 5, iclass 7, count 2 2006.286.04:00:28.01#ibcon#about to read 6, iclass 7, count 2 2006.286.04:00:28.01#ibcon#read 6, iclass 7, count 2 2006.286.04:00:28.01#ibcon#end of sib2, iclass 7, count 2 2006.286.04:00:28.01#ibcon#*after write, iclass 7, count 2 2006.286.04:00:28.01#ibcon#*before return 0, iclass 7, count 2 2006.286.04:00:28.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:00:28.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:00:28.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.04:00:28.01#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:28.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:00:28.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:00:28.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:00:28.13#ibcon#enter wrdev, iclass 7, count 0 2006.286.04:00:28.13#ibcon#first serial, iclass 7, count 0 2006.286.04:00:28.13#ibcon#enter sib2, iclass 7, count 0 2006.286.04:00:28.13#ibcon#flushed, iclass 7, count 0 2006.286.04:00:28.13#ibcon#about to write, iclass 7, count 0 2006.286.04:00:28.13#ibcon#wrote, iclass 7, count 0 2006.286.04:00:28.13#ibcon#about to read 3, iclass 7, count 0 2006.286.04:00:28.15#ibcon#read 3, iclass 7, count 0 2006.286.04:00:28.15#ibcon#about to read 4, iclass 7, count 0 2006.286.04:00:28.15#ibcon#read 4, iclass 7, count 0 2006.286.04:00:28.15#ibcon#about to read 5, iclass 7, count 0 2006.286.04:00:28.15#ibcon#read 5, iclass 7, count 0 2006.286.04:00:28.15#ibcon#about to read 6, iclass 7, count 0 2006.286.04:00:28.15#ibcon#read 6, iclass 7, count 0 2006.286.04:00:28.15#ibcon#end of sib2, iclass 7, count 0 2006.286.04:00:28.15#ibcon#*mode == 0, iclass 7, count 0 2006.286.04:00:28.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.04:00:28.15#ibcon#[25=USB\r\n] 2006.286.04:00:28.15#ibcon#*before write, iclass 7, count 0 2006.286.04:00:28.15#ibcon#enter sib2, iclass 7, count 0 2006.286.04:00:28.15#ibcon#flushed, iclass 7, count 0 2006.286.04:00:28.15#ibcon#about to write, iclass 7, count 0 2006.286.04:00:28.15#ibcon#wrote, iclass 7, count 0 2006.286.04:00:28.15#ibcon#about to read 3, iclass 7, count 0 2006.286.04:00:28.18#ibcon#read 3, iclass 7, count 0 2006.286.04:00:28.18#ibcon#about to read 4, iclass 7, count 0 2006.286.04:00:28.18#ibcon#read 4, iclass 7, count 0 2006.286.04:00:28.18#ibcon#about to read 5, iclass 7, count 0 2006.286.04:00:28.18#ibcon#read 5, iclass 7, count 0 2006.286.04:00:28.18#ibcon#about to read 6, iclass 7, count 0 2006.286.04:00:28.18#ibcon#read 6, iclass 7, count 0 2006.286.04:00:28.18#ibcon#end of sib2, iclass 7, count 0 2006.286.04:00:28.18#ibcon#*after write, iclass 7, count 0 2006.286.04:00:28.18#ibcon#*before return 0, iclass 7, count 0 2006.286.04:00:28.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:00:28.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:00:28.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.04:00:28.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.04:00:28.18$vck44/valo=4,624.99 2006.286.04:00:28.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.04:00:28.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.04:00:28.18#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:28.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:00:28.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:00:28.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:00:28.18#ibcon#enter wrdev, iclass 11, count 0 2006.286.04:00:28.18#ibcon#first serial, iclass 11, count 0 2006.286.04:00:28.18#ibcon#enter sib2, iclass 11, count 0 2006.286.04:00:28.18#ibcon#flushed, iclass 11, count 0 2006.286.04:00:28.18#ibcon#about to write, iclass 11, count 0 2006.286.04:00:28.18#ibcon#wrote, iclass 11, count 0 2006.286.04:00:28.25#ibcon#about to read 3, iclass 11, count 0 2006.286.04:00:28.25#ibcon#read 3, iclass 11, count 0 2006.286.04:00:28.25#ibcon#about to read 4, iclass 11, count 0 2006.286.04:00:28.25#ibcon#read 4, iclass 11, count 0 2006.286.04:00:28.25#ibcon#about to read 5, iclass 11, count 0 2006.286.04:00:28.25#ibcon#read 5, iclass 11, count 0 2006.286.04:00:28.25#ibcon#about to read 6, iclass 11, count 0 2006.286.04:00:28.25#ibcon#read 6, iclass 11, count 0 2006.286.04:00:28.25#ibcon#end of sib2, iclass 11, count 0 2006.286.04:00:28.25#ibcon#*mode == 0, iclass 11, count 0 2006.286.04:00:28.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.04:00:28.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:00:28.25#ibcon#*before write, iclass 11, count 0 2006.286.04:00:28.25#ibcon#enter sib2, iclass 11, count 0 2006.286.04:00:28.25#ibcon#flushed, iclass 11, count 0 2006.286.04:00:28.25#ibcon#about to write, iclass 11, count 0 2006.286.04:00:28.25#ibcon#wrote, iclass 11, count 0 2006.286.04:00:28.25#ibcon#about to read 3, iclass 11, count 0 2006.286.04:00:28.29#ibcon#read 3, iclass 11, count 0 2006.286.04:00:28.29#ibcon#about to read 4, iclass 11, count 0 2006.286.04:00:28.29#ibcon#read 4, iclass 11, count 0 2006.286.04:00:28.29#ibcon#about to read 5, iclass 11, count 0 2006.286.04:00:28.29#ibcon#read 5, iclass 11, count 0 2006.286.04:00:28.29#ibcon#about to read 6, iclass 11, count 0 2006.286.04:00:28.29#ibcon#read 6, iclass 11, count 0 2006.286.04:00:28.29#ibcon#end of sib2, iclass 11, count 0 2006.286.04:00:28.29#ibcon#*after write, iclass 11, count 0 2006.286.04:00:28.29#ibcon#*before return 0, iclass 11, count 0 2006.286.04:00:28.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:00:28.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:00:28.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.04:00:28.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.04:00:28.29$vck44/va=4,6 2006.286.04:00:28.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.04:00:28.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.04:00:28.29#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:28.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:00:28.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:00:28.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:00:28.29#ibcon#enter wrdev, iclass 13, count 2 2006.286.04:00:28.29#ibcon#first serial, iclass 13, count 2 2006.286.04:00:28.29#ibcon#enter sib2, iclass 13, count 2 2006.286.04:00:28.29#ibcon#flushed, iclass 13, count 2 2006.286.04:00:28.29#ibcon#about to write, iclass 13, count 2 2006.286.04:00:28.29#ibcon#wrote, iclass 13, count 2 2006.286.04:00:28.29#ibcon#about to read 3, iclass 13, count 2 2006.286.04:00:28.31#ibcon#read 3, iclass 13, count 2 2006.286.04:00:28.31#ibcon#about to read 4, iclass 13, count 2 2006.286.04:00:28.31#ibcon#read 4, iclass 13, count 2 2006.286.04:00:28.31#ibcon#about to read 5, iclass 13, count 2 2006.286.04:00:28.31#ibcon#read 5, iclass 13, count 2 2006.286.04:00:28.31#ibcon#about to read 6, iclass 13, count 2 2006.286.04:00:28.31#ibcon#read 6, iclass 13, count 2 2006.286.04:00:28.31#ibcon#end of sib2, iclass 13, count 2 2006.286.04:00:28.31#ibcon#*mode == 0, iclass 13, count 2 2006.286.04:00:28.31#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.04:00:28.31#ibcon#[25=AT04-06\r\n] 2006.286.04:00:28.31#ibcon#*before write, iclass 13, count 2 2006.286.04:00:28.31#ibcon#enter sib2, iclass 13, count 2 2006.286.04:00:28.31#ibcon#flushed, iclass 13, count 2 2006.286.04:00:28.31#ibcon#about to write, iclass 13, count 2 2006.286.04:00:28.31#ibcon#wrote, iclass 13, count 2 2006.286.04:00:28.31#ibcon#about to read 3, iclass 13, count 2 2006.286.04:00:28.34#ibcon#read 3, iclass 13, count 2 2006.286.04:00:28.34#ibcon#about to read 4, iclass 13, count 2 2006.286.04:00:28.34#ibcon#read 4, iclass 13, count 2 2006.286.04:00:28.34#ibcon#about to read 5, iclass 13, count 2 2006.286.04:00:28.34#ibcon#read 5, iclass 13, count 2 2006.286.04:00:28.34#ibcon#about to read 6, iclass 13, count 2 2006.286.04:00:28.34#ibcon#read 6, iclass 13, count 2 2006.286.04:00:28.34#ibcon#end of sib2, iclass 13, count 2 2006.286.04:00:28.34#ibcon#*after write, iclass 13, count 2 2006.286.04:00:28.34#ibcon#*before return 0, iclass 13, count 2 2006.286.04:00:28.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:00:28.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:00:28.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.04:00:28.34#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:28.34#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:00:28.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:00:28.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:00:28.46#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:00:28.46#ibcon#first serial, iclass 13, count 0 2006.286.04:00:28.46#ibcon#enter sib2, iclass 13, count 0 2006.286.04:00:28.46#ibcon#flushed, iclass 13, count 0 2006.286.04:00:28.46#ibcon#about to write, iclass 13, count 0 2006.286.04:00:28.46#ibcon#wrote, iclass 13, count 0 2006.286.04:00:28.46#ibcon#about to read 3, iclass 13, count 0 2006.286.04:00:28.48#ibcon#read 3, iclass 13, count 0 2006.286.04:00:28.48#ibcon#about to read 4, iclass 13, count 0 2006.286.04:00:28.48#ibcon#read 4, iclass 13, count 0 2006.286.04:00:28.48#ibcon#about to read 5, iclass 13, count 0 2006.286.04:00:28.48#ibcon#read 5, iclass 13, count 0 2006.286.04:00:28.48#ibcon#about to read 6, iclass 13, count 0 2006.286.04:00:28.48#ibcon#read 6, iclass 13, count 0 2006.286.04:00:28.48#ibcon#end of sib2, iclass 13, count 0 2006.286.04:00:28.48#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:00:28.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:00:28.48#ibcon#[25=USB\r\n] 2006.286.04:00:28.48#ibcon#*before write, iclass 13, count 0 2006.286.04:00:28.48#ibcon#enter sib2, iclass 13, count 0 2006.286.04:00:28.48#ibcon#flushed, iclass 13, count 0 2006.286.04:00:28.48#ibcon#about to write, iclass 13, count 0 2006.286.04:00:28.48#ibcon#wrote, iclass 13, count 0 2006.286.04:00:28.48#ibcon#about to read 3, iclass 13, count 0 2006.286.04:00:28.51#ibcon#read 3, iclass 13, count 0 2006.286.04:00:28.51#ibcon#about to read 4, iclass 13, count 0 2006.286.04:00:28.51#ibcon#read 4, iclass 13, count 0 2006.286.04:00:28.51#ibcon#about to read 5, iclass 13, count 0 2006.286.04:00:28.51#ibcon#read 5, iclass 13, count 0 2006.286.04:00:28.51#ibcon#about to read 6, iclass 13, count 0 2006.286.04:00:28.51#ibcon#read 6, iclass 13, count 0 2006.286.04:00:28.51#ibcon#end of sib2, iclass 13, count 0 2006.286.04:00:28.51#ibcon#*after write, iclass 13, count 0 2006.286.04:00:28.51#ibcon#*before return 0, iclass 13, count 0 2006.286.04:00:28.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:00:28.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:00:28.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:00:28.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:00:28.51$vck44/valo=5,734.99 2006.286.04:00:28.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.04:00:28.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.04:00:28.51#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:28.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:00:28.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:00:28.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:00:28.51#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:00:28.51#ibcon#first serial, iclass 15, count 0 2006.286.04:00:28.51#ibcon#enter sib2, iclass 15, count 0 2006.286.04:00:28.51#ibcon#flushed, iclass 15, count 0 2006.286.04:00:28.51#ibcon#about to write, iclass 15, count 0 2006.286.04:00:28.51#ibcon#wrote, iclass 15, count 0 2006.286.04:00:28.51#ibcon#about to read 3, iclass 15, count 0 2006.286.04:00:28.53#ibcon#read 3, iclass 15, count 0 2006.286.04:00:28.53#ibcon#about to read 4, iclass 15, count 0 2006.286.04:00:28.53#ibcon#read 4, iclass 15, count 0 2006.286.04:00:28.53#ibcon#about to read 5, iclass 15, count 0 2006.286.04:00:28.53#ibcon#read 5, iclass 15, count 0 2006.286.04:00:28.53#ibcon#about to read 6, iclass 15, count 0 2006.286.04:00:28.53#ibcon#read 6, iclass 15, count 0 2006.286.04:00:28.53#ibcon#end of sib2, iclass 15, count 0 2006.286.04:00:28.53#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:00:28.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:00:28.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:00:28.53#ibcon#*before write, iclass 15, count 0 2006.286.04:00:28.53#ibcon#enter sib2, iclass 15, count 0 2006.286.04:00:28.53#ibcon#flushed, iclass 15, count 0 2006.286.04:00:28.53#ibcon#about to write, iclass 15, count 0 2006.286.04:00:28.53#ibcon#wrote, iclass 15, count 0 2006.286.04:00:28.53#ibcon#about to read 3, iclass 15, count 0 2006.286.04:00:28.57#ibcon#read 3, iclass 15, count 0 2006.286.04:00:28.57#ibcon#about to read 4, iclass 15, count 0 2006.286.04:00:28.57#ibcon#read 4, iclass 15, count 0 2006.286.04:00:28.57#ibcon#about to read 5, iclass 15, count 0 2006.286.04:00:28.57#ibcon#read 5, iclass 15, count 0 2006.286.04:00:28.57#ibcon#about to read 6, iclass 15, count 0 2006.286.04:00:28.57#ibcon#read 6, iclass 15, count 0 2006.286.04:00:28.57#ibcon#end of sib2, iclass 15, count 0 2006.286.04:00:28.57#ibcon#*after write, iclass 15, count 0 2006.286.04:00:28.57#ibcon#*before return 0, iclass 15, count 0 2006.286.04:00:28.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:00:28.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:00:28.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:00:28.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:00:28.57$vck44/va=5,3 2006.286.04:00:28.57#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.04:00:28.57#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.04:00:28.57#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:28.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:00:28.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:00:28.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:00:28.63#ibcon#enter wrdev, iclass 17, count 2 2006.286.04:00:28.63#ibcon#first serial, iclass 17, count 2 2006.286.04:00:28.63#ibcon#enter sib2, iclass 17, count 2 2006.286.04:00:28.63#ibcon#flushed, iclass 17, count 2 2006.286.04:00:28.63#ibcon#about to write, iclass 17, count 2 2006.286.04:00:28.63#ibcon#wrote, iclass 17, count 2 2006.286.04:00:28.63#ibcon#about to read 3, iclass 17, count 2 2006.286.04:00:28.65#ibcon#read 3, iclass 17, count 2 2006.286.04:00:28.65#ibcon#about to read 4, iclass 17, count 2 2006.286.04:00:28.65#ibcon#read 4, iclass 17, count 2 2006.286.04:00:28.65#ibcon#about to read 5, iclass 17, count 2 2006.286.04:00:28.65#ibcon#read 5, iclass 17, count 2 2006.286.04:00:28.65#ibcon#about to read 6, iclass 17, count 2 2006.286.04:00:28.65#ibcon#read 6, iclass 17, count 2 2006.286.04:00:28.65#ibcon#end of sib2, iclass 17, count 2 2006.286.04:00:28.65#ibcon#*mode == 0, iclass 17, count 2 2006.286.04:00:28.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.04:00:28.65#ibcon#[25=AT05-03\r\n] 2006.286.04:00:28.65#ibcon#*before write, iclass 17, count 2 2006.286.04:00:28.65#ibcon#enter sib2, iclass 17, count 2 2006.286.04:00:28.65#ibcon#flushed, iclass 17, count 2 2006.286.04:00:28.65#ibcon#about to write, iclass 17, count 2 2006.286.04:00:28.65#ibcon#wrote, iclass 17, count 2 2006.286.04:00:28.65#ibcon#about to read 3, iclass 17, count 2 2006.286.04:00:28.68#ibcon#read 3, iclass 17, count 2 2006.286.04:00:28.68#ibcon#about to read 4, iclass 17, count 2 2006.286.04:00:28.68#ibcon#read 4, iclass 17, count 2 2006.286.04:00:28.68#ibcon#about to read 5, iclass 17, count 2 2006.286.04:00:28.68#ibcon#read 5, iclass 17, count 2 2006.286.04:00:28.68#ibcon#about to read 6, iclass 17, count 2 2006.286.04:00:28.68#ibcon#read 6, iclass 17, count 2 2006.286.04:00:28.68#ibcon#end of sib2, iclass 17, count 2 2006.286.04:00:28.68#ibcon#*after write, iclass 17, count 2 2006.286.04:00:28.68#ibcon#*before return 0, iclass 17, count 2 2006.286.04:00:28.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:00:28.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:00:28.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.04:00:28.68#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:28.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:00:28.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:00:28.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:00:28.80#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:00:28.80#ibcon#first serial, iclass 17, count 0 2006.286.04:00:28.80#ibcon#enter sib2, iclass 17, count 0 2006.286.04:00:28.80#ibcon#flushed, iclass 17, count 0 2006.286.04:00:28.80#ibcon#about to write, iclass 17, count 0 2006.286.04:00:28.80#ibcon#wrote, iclass 17, count 0 2006.286.04:00:28.80#ibcon#about to read 3, iclass 17, count 0 2006.286.04:00:28.82#ibcon#read 3, iclass 17, count 0 2006.286.04:00:28.82#ibcon#about to read 4, iclass 17, count 0 2006.286.04:00:28.82#ibcon#read 4, iclass 17, count 0 2006.286.04:00:28.82#ibcon#about to read 5, iclass 17, count 0 2006.286.04:00:28.82#ibcon#read 5, iclass 17, count 0 2006.286.04:00:28.82#ibcon#about to read 6, iclass 17, count 0 2006.286.04:00:28.82#ibcon#read 6, iclass 17, count 0 2006.286.04:00:28.82#ibcon#end of sib2, iclass 17, count 0 2006.286.04:00:28.82#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:00:28.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:00:28.82#ibcon#[25=USB\r\n] 2006.286.04:00:28.82#ibcon#*before write, iclass 17, count 0 2006.286.04:00:28.82#ibcon#enter sib2, iclass 17, count 0 2006.286.04:00:28.82#ibcon#flushed, iclass 17, count 0 2006.286.04:00:28.82#ibcon#about to write, iclass 17, count 0 2006.286.04:00:28.82#ibcon#wrote, iclass 17, count 0 2006.286.04:00:28.82#ibcon#about to read 3, iclass 17, count 0 2006.286.04:00:28.85#ibcon#read 3, iclass 17, count 0 2006.286.04:00:28.85#ibcon#about to read 4, iclass 17, count 0 2006.286.04:00:28.85#ibcon#read 4, iclass 17, count 0 2006.286.04:00:28.85#ibcon#about to read 5, iclass 17, count 0 2006.286.04:00:28.85#ibcon#read 5, iclass 17, count 0 2006.286.04:00:28.85#ibcon#about to read 6, iclass 17, count 0 2006.286.04:00:28.85#ibcon#read 6, iclass 17, count 0 2006.286.04:00:28.85#ibcon#end of sib2, iclass 17, count 0 2006.286.04:00:28.85#ibcon#*after write, iclass 17, count 0 2006.286.04:00:28.85#ibcon#*before return 0, iclass 17, count 0 2006.286.04:00:28.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:00:28.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:00:28.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:00:28.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:00:28.85$vck44/valo=6,814.99 2006.286.04:00:28.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.04:00:28.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.04:00:28.85#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:28.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:00:28.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:00:28.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:00:28.85#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:00:28.85#ibcon#first serial, iclass 19, count 0 2006.286.04:00:28.85#ibcon#enter sib2, iclass 19, count 0 2006.286.04:00:28.85#ibcon#flushed, iclass 19, count 0 2006.286.04:00:28.85#ibcon#about to write, iclass 19, count 0 2006.286.04:00:28.85#ibcon#wrote, iclass 19, count 0 2006.286.04:00:28.85#ibcon#about to read 3, iclass 19, count 0 2006.286.04:00:28.87#ibcon#read 3, iclass 19, count 0 2006.286.04:00:28.87#ibcon#about to read 4, iclass 19, count 0 2006.286.04:00:28.87#ibcon#read 4, iclass 19, count 0 2006.286.04:00:28.87#ibcon#about to read 5, iclass 19, count 0 2006.286.04:00:28.87#ibcon#read 5, iclass 19, count 0 2006.286.04:00:28.87#ibcon#about to read 6, iclass 19, count 0 2006.286.04:00:28.87#ibcon#read 6, iclass 19, count 0 2006.286.04:00:28.87#ibcon#end of sib2, iclass 19, count 0 2006.286.04:00:28.87#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:00:28.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:00:28.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:00:28.87#ibcon#*before write, iclass 19, count 0 2006.286.04:00:28.87#ibcon#enter sib2, iclass 19, count 0 2006.286.04:00:28.87#ibcon#flushed, iclass 19, count 0 2006.286.04:00:28.87#ibcon#about to write, iclass 19, count 0 2006.286.04:00:28.87#ibcon#wrote, iclass 19, count 0 2006.286.04:00:28.87#ibcon#about to read 3, iclass 19, count 0 2006.286.04:00:28.91#ibcon#read 3, iclass 19, count 0 2006.286.04:00:28.91#ibcon#about to read 4, iclass 19, count 0 2006.286.04:00:28.91#ibcon#read 4, iclass 19, count 0 2006.286.04:00:28.91#ibcon#about to read 5, iclass 19, count 0 2006.286.04:00:28.91#ibcon#read 5, iclass 19, count 0 2006.286.04:00:28.91#ibcon#about to read 6, iclass 19, count 0 2006.286.04:00:28.91#ibcon#read 6, iclass 19, count 0 2006.286.04:00:28.91#ibcon#end of sib2, iclass 19, count 0 2006.286.04:00:28.91#ibcon#*after write, iclass 19, count 0 2006.286.04:00:28.91#ibcon#*before return 0, iclass 19, count 0 2006.286.04:00:28.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:00:28.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:00:28.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:00:28.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:00:28.91$vck44/va=6,4 2006.286.04:00:28.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.04:00:28.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.04:00:28.91#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:28.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:00:28.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:00:28.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:00:28.97#ibcon#enter wrdev, iclass 21, count 2 2006.286.04:00:28.97#ibcon#first serial, iclass 21, count 2 2006.286.04:00:28.97#ibcon#enter sib2, iclass 21, count 2 2006.286.04:00:28.97#ibcon#flushed, iclass 21, count 2 2006.286.04:00:28.97#ibcon#about to write, iclass 21, count 2 2006.286.04:00:28.97#ibcon#wrote, iclass 21, count 2 2006.286.04:00:28.97#ibcon#about to read 3, iclass 21, count 2 2006.286.04:00:28.99#ibcon#read 3, iclass 21, count 2 2006.286.04:00:28.99#ibcon#about to read 4, iclass 21, count 2 2006.286.04:00:28.99#ibcon#read 4, iclass 21, count 2 2006.286.04:00:28.99#ibcon#about to read 5, iclass 21, count 2 2006.286.04:00:28.99#ibcon#read 5, iclass 21, count 2 2006.286.04:00:28.99#ibcon#about to read 6, iclass 21, count 2 2006.286.04:00:28.99#ibcon#read 6, iclass 21, count 2 2006.286.04:00:28.99#ibcon#end of sib2, iclass 21, count 2 2006.286.04:00:28.99#ibcon#*mode == 0, iclass 21, count 2 2006.286.04:00:28.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.04:00:28.99#ibcon#[25=AT06-04\r\n] 2006.286.04:00:28.99#ibcon#*before write, iclass 21, count 2 2006.286.04:00:28.99#ibcon#enter sib2, iclass 21, count 2 2006.286.04:00:28.99#ibcon#flushed, iclass 21, count 2 2006.286.04:00:28.99#ibcon#about to write, iclass 21, count 2 2006.286.04:00:28.99#ibcon#wrote, iclass 21, count 2 2006.286.04:00:28.99#ibcon#about to read 3, iclass 21, count 2 2006.286.04:00:29.02#ibcon#read 3, iclass 21, count 2 2006.286.04:00:29.02#ibcon#about to read 4, iclass 21, count 2 2006.286.04:00:29.02#ibcon#read 4, iclass 21, count 2 2006.286.04:00:29.02#ibcon#about to read 5, iclass 21, count 2 2006.286.04:00:29.02#ibcon#read 5, iclass 21, count 2 2006.286.04:00:29.02#ibcon#about to read 6, iclass 21, count 2 2006.286.04:00:29.02#ibcon#read 6, iclass 21, count 2 2006.286.04:00:29.02#ibcon#end of sib2, iclass 21, count 2 2006.286.04:00:29.02#ibcon#*after write, iclass 21, count 2 2006.286.04:00:29.02#ibcon#*before return 0, iclass 21, count 2 2006.286.04:00:29.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:00:29.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:00:29.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.04:00:29.02#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:29.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:00:29.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:00:29.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:00:29.14#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:00:29.14#ibcon#first serial, iclass 21, count 0 2006.286.04:00:29.14#ibcon#enter sib2, iclass 21, count 0 2006.286.04:00:29.14#ibcon#flushed, iclass 21, count 0 2006.286.04:00:29.14#ibcon#about to write, iclass 21, count 0 2006.286.04:00:29.14#ibcon#wrote, iclass 21, count 0 2006.286.04:00:29.14#ibcon#about to read 3, iclass 21, count 0 2006.286.04:00:29.16#ibcon#read 3, iclass 21, count 0 2006.286.04:00:29.16#ibcon#about to read 4, iclass 21, count 0 2006.286.04:00:29.16#ibcon#read 4, iclass 21, count 0 2006.286.04:00:29.16#ibcon#about to read 5, iclass 21, count 0 2006.286.04:00:29.16#ibcon#read 5, iclass 21, count 0 2006.286.04:00:29.16#ibcon#about to read 6, iclass 21, count 0 2006.286.04:00:29.16#ibcon#read 6, iclass 21, count 0 2006.286.04:00:29.16#ibcon#end of sib2, iclass 21, count 0 2006.286.04:00:29.16#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:00:29.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:00:29.16#ibcon#[25=USB\r\n] 2006.286.04:00:29.16#ibcon#*before write, iclass 21, count 0 2006.286.04:00:29.16#ibcon#enter sib2, iclass 21, count 0 2006.286.04:00:29.16#ibcon#flushed, iclass 21, count 0 2006.286.04:00:29.16#ibcon#about to write, iclass 21, count 0 2006.286.04:00:29.16#ibcon#wrote, iclass 21, count 0 2006.286.04:00:29.16#ibcon#about to read 3, iclass 21, count 0 2006.286.04:00:29.19#ibcon#read 3, iclass 21, count 0 2006.286.04:00:29.19#ibcon#about to read 4, iclass 21, count 0 2006.286.04:00:29.19#ibcon#read 4, iclass 21, count 0 2006.286.04:00:29.19#ibcon#about to read 5, iclass 21, count 0 2006.286.04:00:29.19#ibcon#read 5, iclass 21, count 0 2006.286.04:00:29.19#ibcon#about to read 6, iclass 21, count 0 2006.286.04:00:29.19#ibcon#read 6, iclass 21, count 0 2006.286.04:00:29.19#ibcon#end of sib2, iclass 21, count 0 2006.286.04:00:29.19#ibcon#*after write, iclass 21, count 0 2006.286.04:00:29.19#ibcon#*before return 0, iclass 21, count 0 2006.286.04:00:29.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:00:29.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:00:29.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:00:29.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:00:29.19$vck44/valo=7,864.99 2006.286.04:00:29.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.04:00:29.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.04:00:29.19#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:29.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:00:29.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:00:29.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:00:29.19#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:00:29.19#ibcon#first serial, iclass 23, count 0 2006.286.04:00:29.19#ibcon#enter sib2, iclass 23, count 0 2006.286.04:00:29.19#ibcon#flushed, iclass 23, count 0 2006.286.04:00:29.19#ibcon#about to write, iclass 23, count 0 2006.286.04:00:29.19#ibcon#wrote, iclass 23, count 0 2006.286.04:00:29.19#ibcon#about to read 3, iclass 23, count 0 2006.286.04:00:29.21#ibcon#read 3, iclass 23, count 0 2006.286.04:00:29.35#ibcon#about to read 4, iclass 23, count 0 2006.286.04:00:29.35#ibcon#read 4, iclass 23, count 0 2006.286.04:00:29.35#ibcon#about to read 5, iclass 23, count 0 2006.286.04:00:29.35#ibcon#read 5, iclass 23, count 0 2006.286.04:00:29.35#ibcon#about to read 6, iclass 23, count 0 2006.286.04:00:29.35#ibcon#read 6, iclass 23, count 0 2006.286.04:00:29.35#ibcon#end of sib2, iclass 23, count 0 2006.286.04:00:29.35#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:00:29.35#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:00:29.35#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:00:29.35#ibcon#*before write, iclass 23, count 0 2006.286.04:00:29.35#ibcon#enter sib2, iclass 23, count 0 2006.286.04:00:29.35#ibcon#flushed, iclass 23, count 0 2006.286.04:00:29.35#ibcon#about to write, iclass 23, count 0 2006.286.04:00:29.35#ibcon#wrote, iclass 23, count 0 2006.286.04:00:29.35#ibcon#about to read 3, iclass 23, count 0 2006.286.04:00:29.38#ibcon#read 3, iclass 23, count 0 2006.286.04:00:29.38#ibcon#about to read 4, iclass 23, count 0 2006.286.04:00:29.38#ibcon#read 4, iclass 23, count 0 2006.286.04:00:29.38#ibcon#about to read 5, iclass 23, count 0 2006.286.04:00:29.38#ibcon#read 5, iclass 23, count 0 2006.286.04:00:29.38#ibcon#about to read 6, iclass 23, count 0 2006.286.04:00:29.38#ibcon#read 6, iclass 23, count 0 2006.286.04:00:29.38#ibcon#end of sib2, iclass 23, count 0 2006.286.04:00:29.38#ibcon#*after write, iclass 23, count 0 2006.286.04:00:29.38#ibcon#*before return 0, iclass 23, count 0 2006.286.04:00:29.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:00:29.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:00:29.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:00:29.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:00:29.38$vck44/va=7,4 2006.286.04:00:29.38#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.04:00:29.38#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.04:00:29.38#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:29.38#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:00:29.38#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:00:29.38#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:00:29.38#ibcon#enter wrdev, iclass 25, count 2 2006.286.04:00:29.38#ibcon#first serial, iclass 25, count 2 2006.286.04:00:29.38#ibcon#enter sib2, iclass 25, count 2 2006.286.04:00:29.38#ibcon#flushed, iclass 25, count 2 2006.286.04:00:29.38#ibcon#about to write, iclass 25, count 2 2006.286.04:00:29.38#ibcon#wrote, iclass 25, count 2 2006.286.04:00:29.38#ibcon#about to read 3, iclass 25, count 2 2006.286.04:00:29.40#ibcon#read 3, iclass 25, count 2 2006.286.04:00:29.40#ibcon#about to read 4, iclass 25, count 2 2006.286.04:00:29.40#ibcon#read 4, iclass 25, count 2 2006.286.04:00:29.40#ibcon#about to read 5, iclass 25, count 2 2006.286.04:00:29.40#ibcon#read 5, iclass 25, count 2 2006.286.04:00:29.40#ibcon#about to read 6, iclass 25, count 2 2006.286.04:00:29.40#ibcon#read 6, iclass 25, count 2 2006.286.04:00:29.40#ibcon#end of sib2, iclass 25, count 2 2006.286.04:00:29.40#ibcon#*mode == 0, iclass 25, count 2 2006.286.04:00:29.40#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.04:00:29.40#ibcon#[25=AT07-04\r\n] 2006.286.04:00:29.40#ibcon#*before write, iclass 25, count 2 2006.286.04:00:29.40#ibcon#enter sib2, iclass 25, count 2 2006.286.04:00:29.40#ibcon#flushed, iclass 25, count 2 2006.286.04:00:29.40#ibcon#about to write, iclass 25, count 2 2006.286.04:00:29.40#ibcon#wrote, iclass 25, count 2 2006.286.04:00:29.40#ibcon#about to read 3, iclass 25, count 2 2006.286.04:00:29.43#ibcon#read 3, iclass 25, count 2 2006.286.04:00:29.43#ibcon#about to read 4, iclass 25, count 2 2006.286.04:00:29.43#ibcon#read 4, iclass 25, count 2 2006.286.04:00:29.43#ibcon#about to read 5, iclass 25, count 2 2006.286.04:00:29.43#ibcon#read 5, iclass 25, count 2 2006.286.04:00:29.43#ibcon#about to read 6, iclass 25, count 2 2006.286.04:00:29.43#ibcon#read 6, iclass 25, count 2 2006.286.04:00:29.43#ibcon#end of sib2, iclass 25, count 2 2006.286.04:00:29.43#ibcon#*after write, iclass 25, count 2 2006.286.04:00:29.43#ibcon#*before return 0, iclass 25, count 2 2006.286.04:00:29.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:00:29.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:00:29.43#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.04:00:29.43#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:29.43#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:00:29.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:00:29.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:00:29.55#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:00:29.55#ibcon#first serial, iclass 25, count 0 2006.286.04:00:29.55#ibcon#enter sib2, iclass 25, count 0 2006.286.04:00:29.55#ibcon#flushed, iclass 25, count 0 2006.286.04:00:29.55#ibcon#about to write, iclass 25, count 0 2006.286.04:00:29.55#ibcon#wrote, iclass 25, count 0 2006.286.04:00:29.55#ibcon#about to read 3, iclass 25, count 0 2006.286.04:00:29.57#ibcon#read 3, iclass 25, count 0 2006.286.04:00:29.57#ibcon#about to read 4, iclass 25, count 0 2006.286.04:00:29.57#ibcon#read 4, iclass 25, count 0 2006.286.04:00:29.57#ibcon#about to read 5, iclass 25, count 0 2006.286.04:00:29.57#ibcon#read 5, iclass 25, count 0 2006.286.04:00:29.57#ibcon#about to read 6, iclass 25, count 0 2006.286.04:00:29.57#ibcon#read 6, iclass 25, count 0 2006.286.04:00:29.57#ibcon#end of sib2, iclass 25, count 0 2006.286.04:00:29.57#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:00:29.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:00:29.57#ibcon#[25=USB\r\n] 2006.286.04:00:29.57#ibcon#*before write, iclass 25, count 0 2006.286.04:00:29.57#ibcon#enter sib2, iclass 25, count 0 2006.286.04:00:29.57#ibcon#flushed, iclass 25, count 0 2006.286.04:00:29.57#ibcon#about to write, iclass 25, count 0 2006.286.04:00:29.57#ibcon#wrote, iclass 25, count 0 2006.286.04:00:29.57#ibcon#about to read 3, iclass 25, count 0 2006.286.04:00:29.60#ibcon#read 3, iclass 25, count 0 2006.286.04:00:29.60#ibcon#about to read 4, iclass 25, count 0 2006.286.04:00:29.60#ibcon#read 4, iclass 25, count 0 2006.286.04:00:29.60#ibcon#about to read 5, iclass 25, count 0 2006.286.04:00:29.60#ibcon#read 5, iclass 25, count 0 2006.286.04:00:29.60#ibcon#about to read 6, iclass 25, count 0 2006.286.04:00:29.60#ibcon#read 6, iclass 25, count 0 2006.286.04:00:29.60#ibcon#end of sib2, iclass 25, count 0 2006.286.04:00:29.60#ibcon#*after write, iclass 25, count 0 2006.286.04:00:29.60#ibcon#*before return 0, iclass 25, count 0 2006.286.04:00:29.60#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:00:29.60#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:00:29.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:00:29.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:00:29.60$vck44/valo=8,884.99 2006.286.04:00:29.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.04:00:29.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.04:00:29.60#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:29.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:00:29.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:00:29.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:00:29.60#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:00:29.60#ibcon#first serial, iclass 27, count 0 2006.286.04:00:29.60#ibcon#enter sib2, iclass 27, count 0 2006.286.04:00:29.60#ibcon#flushed, iclass 27, count 0 2006.286.04:00:29.60#ibcon#about to write, iclass 27, count 0 2006.286.04:00:29.60#ibcon#wrote, iclass 27, count 0 2006.286.04:00:29.60#ibcon#about to read 3, iclass 27, count 0 2006.286.04:00:29.62#ibcon#read 3, iclass 27, count 0 2006.286.04:00:29.62#ibcon#about to read 4, iclass 27, count 0 2006.286.04:00:29.62#ibcon#read 4, iclass 27, count 0 2006.286.04:00:29.62#ibcon#about to read 5, iclass 27, count 0 2006.286.04:00:29.62#ibcon#read 5, iclass 27, count 0 2006.286.04:00:29.62#ibcon#about to read 6, iclass 27, count 0 2006.286.04:00:29.62#ibcon#read 6, iclass 27, count 0 2006.286.04:00:29.62#ibcon#end of sib2, iclass 27, count 0 2006.286.04:00:29.62#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:00:29.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:00:29.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:00:29.62#ibcon#*before write, iclass 27, count 0 2006.286.04:00:29.62#ibcon#enter sib2, iclass 27, count 0 2006.286.04:00:29.62#ibcon#flushed, iclass 27, count 0 2006.286.04:00:29.62#ibcon#about to write, iclass 27, count 0 2006.286.04:00:29.62#ibcon#wrote, iclass 27, count 0 2006.286.04:00:29.62#ibcon#about to read 3, iclass 27, count 0 2006.286.04:00:29.66#ibcon#read 3, iclass 27, count 0 2006.286.04:00:29.66#ibcon#about to read 4, iclass 27, count 0 2006.286.04:00:29.66#ibcon#read 4, iclass 27, count 0 2006.286.04:00:29.66#ibcon#about to read 5, iclass 27, count 0 2006.286.04:00:29.66#ibcon#read 5, iclass 27, count 0 2006.286.04:00:29.66#ibcon#about to read 6, iclass 27, count 0 2006.286.04:00:29.66#ibcon#read 6, iclass 27, count 0 2006.286.04:00:29.66#ibcon#end of sib2, iclass 27, count 0 2006.286.04:00:29.66#ibcon#*after write, iclass 27, count 0 2006.286.04:00:29.66#ibcon#*before return 0, iclass 27, count 0 2006.286.04:00:29.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:00:29.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:00:29.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:00:29.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:00:29.66$vck44/va=8,3 2006.286.04:00:29.66#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.04:00:29.66#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.04:00:29.66#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:29.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:00:29.72#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:00:29.72#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:00:29.72#ibcon#enter wrdev, iclass 29, count 2 2006.286.04:00:29.72#ibcon#first serial, iclass 29, count 2 2006.286.04:00:29.72#ibcon#enter sib2, iclass 29, count 2 2006.286.04:00:29.72#ibcon#flushed, iclass 29, count 2 2006.286.04:00:29.72#ibcon#about to write, iclass 29, count 2 2006.286.04:00:29.72#ibcon#wrote, iclass 29, count 2 2006.286.04:00:29.72#ibcon#about to read 3, iclass 29, count 2 2006.286.04:00:29.74#ibcon#read 3, iclass 29, count 2 2006.286.04:00:29.74#ibcon#about to read 4, iclass 29, count 2 2006.286.04:00:29.74#ibcon#read 4, iclass 29, count 2 2006.286.04:00:29.74#ibcon#about to read 5, iclass 29, count 2 2006.286.04:00:29.74#ibcon#read 5, iclass 29, count 2 2006.286.04:00:29.74#ibcon#about to read 6, iclass 29, count 2 2006.286.04:00:29.74#ibcon#read 6, iclass 29, count 2 2006.286.04:00:29.74#ibcon#end of sib2, iclass 29, count 2 2006.286.04:00:29.74#ibcon#*mode == 0, iclass 29, count 2 2006.286.04:00:29.74#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.04:00:29.74#ibcon#[25=AT08-03\r\n] 2006.286.04:00:29.74#ibcon#*before write, iclass 29, count 2 2006.286.04:00:29.74#ibcon#enter sib2, iclass 29, count 2 2006.286.04:00:29.74#ibcon#flushed, iclass 29, count 2 2006.286.04:00:29.74#ibcon#about to write, iclass 29, count 2 2006.286.04:00:29.74#ibcon#wrote, iclass 29, count 2 2006.286.04:00:29.74#ibcon#about to read 3, iclass 29, count 2 2006.286.04:00:29.77#ibcon#read 3, iclass 29, count 2 2006.286.04:00:29.77#ibcon#about to read 4, iclass 29, count 2 2006.286.04:00:29.77#ibcon#read 4, iclass 29, count 2 2006.286.04:00:29.77#ibcon#about to read 5, iclass 29, count 2 2006.286.04:00:29.77#ibcon#read 5, iclass 29, count 2 2006.286.04:00:29.77#ibcon#about to read 6, iclass 29, count 2 2006.286.04:00:29.77#ibcon#read 6, iclass 29, count 2 2006.286.04:00:29.77#ibcon#end of sib2, iclass 29, count 2 2006.286.04:00:29.77#ibcon#*after write, iclass 29, count 2 2006.286.04:00:29.77#ibcon#*before return 0, iclass 29, count 2 2006.286.04:00:29.77#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:00:29.77#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:00:29.77#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.04:00:29.77#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:29.77#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:00:29.89#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:00:29.89#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:00:29.89#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:00:29.89#ibcon#first serial, iclass 29, count 0 2006.286.04:00:29.89#ibcon#enter sib2, iclass 29, count 0 2006.286.04:00:29.89#ibcon#flushed, iclass 29, count 0 2006.286.04:00:29.89#ibcon#about to write, iclass 29, count 0 2006.286.04:00:29.89#ibcon#wrote, iclass 29, count 0 2006.286.04:00:29.89#ibcon#about to read 3, iclass 29, count 0 2006.286.04:00:29.91#ibcon#read 3, iclass 29, count 0 2006.286.04:00:29.91#ibcon#about to read 4, iclass 29, count 0 2006.286.04:00:29.91#ibcon#read 4, iclass 29, count 0 2006.286.04:00:29.91#ibcon#about to read 5, iclass 29, count 0 2006.286.04:00:29.91#ibcon#read 5, iclass 29, count 0 2006.286.04:00:29.91#ibcon#about to read 6, iclass 29, count 0 2006.286.04:00:29.91#ibcon#read 6, iclass 29, count 0 2006.286.04:00:29.91#ibcon#end of sib2, iclass 29, count 0 2006.286.04:00:29.91#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:00:29.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:00:29.91#ibcon#[25=USB\r\n] 2006.286.04:00:29.91#ibcon#*before write, iclass 29, count 0 2006.286.04:00:29.91#ibcon#enter sib2, iclass 29, count 0 2006.286.04:00:29.91#ibcon#flushed, iclass 29, count 0 2006.286.04:00:29.91#ibcon#about to write, iclass 29, count 0 2006.286.04:00:29.91#ibcon#wrote, iclass 29, count 0 2006.286.04:00:29.91#ibcon#about to read 3, iclass 29, count 0 2006.286.04:00:29.94#ibcon#read 3, iclass 29, count 0 2006.286.04:00:29.94#ibcon#about to read 4, iclass 29, count 0 2006.286.04:00:29.94#ibcon#read 4, iclass 29, count 0 2006.286.04:00:29.94#ibcon#about to read 5, iclass 29, count 0 2006.286.04:00:29.94#ibcon#read 5, iclass 29, count 0 2006.286.04:00:29.94#ibcon#about to read 6, iclass 29, count 0 2006.286.04:00:29.94#ibcon#read 6, iclass 29, count 0 2006.286.04:00:29.94#ibcon#end of sib2, iclass 29, count 0 2006.286.04:00:29.94#ibcon#*after write, iclass 29, count 0 2006.286.04:00:29.94#ibcon#*before return 0, iclass 29, count 0 2006.286.04:00:29.94#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:00:29.94#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:00:29.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:00:29.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:00:29.94$vck44/vblo=1,629.99 2006.286.04:00:29.94#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.04:00:29.94#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.04:00:29.94#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:29.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:00:29.94#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:00:29.94#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:00:29.94#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:00:29.94#ibcon#first serial, iclass 31, count 0 2006.286.04:00:29.94#ibcon#enter sib2, iclass 31, count 0 2006.286.04:00:29.94#ibcon#flushed, iclass 31, count 0 2006.286.04:00:29.94#ibcon#about to write, iclass 31, count 0 2006.286.04:00:29.94#ibcon#wrote, iclass 31, count 0 2006.286.04:00:29.94#ibcon#about to read 3, iclass 31, count 0 2006.286.04:00:29.96#ibcon#read 3, iclass 31, count 0 2006.286.04:00:29.96#ibcon#about to read 4, iclass 31, count 0 2006.286.04:00:29.96#ibcon#read 4, iclass 31, count 0 2006.286.04:00:29.96#ibcon#about to read 5, iclass 31, count 0 2006.286.04:00:29.96#ibcon#read 5, iclass 31, count 0 2006.286.04:00:29.96#ibcon#about to read 6, iclass 31, count 0 2006.286.04:00:29.96#ibcon#read 6, iclass 31, count 0 2006.286.04:00:29.96#ibcon#end of sib2, iclass 31, count 0 2006.286.04:00:29.96#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:00:29.96#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:00:29.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:00:29.96#ibcon#*before write, iclass 31, count 0 2006.286.04:00:29.96#ibcon#enter sib2, iclass 31, count 0 2006.286.04:00:29.96#ibcon#flushed, iclass 31, count 0 2006.286.04:00:29.96#ibcon#about to write, iclass 31, count 0 2006.286.04:00:29.96#ibcon#wrote, iclass 31, count 0 2006.286.04:00:29.96#ibcon#about to read 3, iclass 31, count 0 2006.286.04:00:30.00#ibcon#read 3, iclass 31, count 0 2006.286.04:00:30.00#ibcon#about to read 4, iclass 31, count 0 2006.286.04:00:30.00#ibcon#read 4, iclass 31, count 0 2006.286.04:00:30.00#ibcon#about to read 5, iclass 31, count 0 2006.286.04:00:30.00#ibcon#read 5, iclass 31, count 0 2006.286.04:00:30.00#ibcon#about to read 6, iclass 31, count 0 2006.286.04:00:30.00#ibcon#read 6, iclass 31, count 0 2006.286.04:00:30.00#ibcon#end of sib2, iclass 31, count 0 2006.286.04:00:30.00#ibcon#*after write, iclass 31, count 0 2006.286.04:00:30.00#ibcon#*before return 0, iclass 31, count 0 2006.286.04:00:30.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:00:30.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:00:30.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:00:30.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:00:30.00$vck44/vb=1,4 2006.286.04:00:30.00#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.04:00:30.00#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.04:00:30.00#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:30.00#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:00:30.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:00:30.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:00:30.00#ibcon#enter wrdev, iclass 33, count 2 2006.286.04:00:30.00#ibcon#first serial, iclass 33, count 2 2006.286.04:00:30.00#ibcon#enter sib2, iclass 33, count 2 2006.286.04:00:30.00#ibcon#flushed, iclass 33, count 2 2006.286.04:00:30.00#ibcon#about to write, iclass 33, count 2 2006.286.04:00:30.00#ibcon#wrote, iclass 33, count 2 2006.286.04:00:30.00#ibcon#about to read 3, iclass 33, count 2 2006.286.04:00:30.02#ibcon#read 3, iclass 33, count 2 2006.286.04:00:30.02#ibcon#about to read 4, iclass 33, count 2 2006.286.04:00:30.02#ibcon#read 4, iclass 33, count 2 2006.286.04:00:30.02#ibcon#about to read 5, iclass 33, count 2 2006.286.04:00:30.02#ibcon#read 5, iclass 33, count 2 2006.286.04:00:30.02#ibcon#about to read 6, iclass 33, count 2 2006.286.04:00:30.02#ibcon#read 6, iclass 33, count 2 2006.286.04:00:30.02#ibcon#end of sib2, iclass 33, count 2 2006.286.04:00:30.02#ibcon#*mode == 0, iclass 33, count 2 2006.286.04:00:30.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.04:00:30.02#ibcon#[27=AT01-04\r\n] 2006.286.04:00:30.02#ibcon#*before write, iclass 33, count 2 2006.286.04:00:30.02#ibcon#enter sib2, iclass 33, count 2 2006.286.04:00:30.02#ibcon#flushed, iclass 33, count 2 2006.286.04:00:30.02#ibcon#about to write, iclass 33, count 2 2006.286.04:00:30.02#ibcon#wrote, iclass 33, count 2 2006.286.04:00:30.02#ibcon#about to read 3, iclass 33, count 2 2006.286.04:00:30.05#ibcon#read 3, iclass 33, count 2 2006.286.04:00:30.05#ibcon#about to read 4, iclass 33, count 2 2006.286.04:00:30.05#ibcon#read 4, iclass 33, count 2 2006.286.04:00:30.05#ibcon#about to read 5, iclass 33, count 2 2006.286.04:00:30.05#ibcon#read 5, iclass 33, count 2 2006.286.04:00:30.05#ibcon#about to read 6, iclass 33, count 2 2006.286.04:00:30.05#ibcon#read 6, iclass 33, count 2 2006.286.04:00:30.05#ibcon#end of sib2, iclass 33, count 2 2006.286.04:00:30.05#ibcon#*after write, iclass 33, count 2 2006.286.04:00:30.05#ibcon#*before return 0, iclass 33, count 2 2006.286.04:00:30.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:00:30.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:00:30.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.04:00:30.05#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:30.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:00:30.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:00:30.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:00:30.17#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:00:30.17#ibcon#first serial, iclass 33, count 0 2006.286.04:00:30.17#ibcon#enter sib2, iclass 33, count 0 2006.286.04:00:30.17#ibcon#flushed, iclass 33, count 0 2006.286.04:00:30.17#ibcon#about to write, iclass 33, count 0 2006.286.04:00:30.17#ibcon#wrote, iclass 33, count 0 2006.286.04:00:30.17#ibcon#about to read 3, iclass 33, count 0 2006.286.04:00:30.19#ibcon#read 3, iclass 33, count 0 2006.286.04:00:30.19#ibcon#about to read 4, iclass 33, count 0 2006.286.04:00:30.19#ibcon#read 4, iclass 33, count 0 2006.286.04:00:30.19#ibcon#about to read 5, iclass 33, count 0 2006.286.04:00:30.19#ibcon#read 5, iclass 33, count 0 2006.286.04:00:30.19#ibcon#about to read 6, iclass 33, count 0 2006.286.04:00:30.19#ibcon#read 6, iclass 33, count 0 2006.286.04:00:30.19#ibcon#end of sib2, iclass 33, count 0 2006.286.04:00:30.19#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:00:30.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:00:30.19#ibcon#[27=USB\r\n] 2006.286.04:00:30.19#ibcon#*before write, iclass 33, count 0 2006.286.04:00:30.19#ibcon#enter sib2, iclass 33, count 0 2006.286.04:00:30.19#ibcon#flushed, iclass 33, count 0 2006.286.04:00:30.19#ibcon#about to write, iclass 33, count 0 2006.286.04:00:30.19#ibcon#wrote, iclass 33, count 0 2006.286.04:00:30.19#ibcon#about to read 3, iclass 33, count 0 2006.286.04:00:30.22#ibcon#read 3, iclass 33, count 0 2006.286.04:00:30.22#ibcon#about to read 4, iclass 33, count 0 2006.286.04:00:30.22#ibcon#read 4, iclass 33, count 0 2006.286.04:00:30.22#ibcon#about to read 5, iclass 33, count 0 2006.286.04:00:30.22#ibcon#read 5, iclass 33, count 0 2006.286.04:00:30.22#ibcon#about to read 6, iclass 33, count 0 2006.286.04:00:30.22#ibcon#read 6, iclass 33, count 0 2006.286.04:00:30.22#ibcon#end of sib2, iclass 33, count 0 2006.286.04:00:30.22#ibcon#*after write, iclass 33, count 0 2006.286.04:00:30.22#ibcon#*before return 0, iclass 33, count 0 2006.286.04:00:30.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:00:30.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:00:30.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:00:30.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:00:30.22$vck44/vblo=2,634.99 2006.286.04:00:30.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.04:00:30.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.04:00:30.22#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:30.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:00:30.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:00:30.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:00:30.22#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:00:30.22#ibcon#first serial, iclass 35, count 0 2006.286.04:00:30.22#ibcon#enter sib2, iclass 35, count 0 2006.286.04:00:30.22#ibcon#flushed, iclass 35, count 0 2006.286.04:00:30.22#ibcon#about to write, iclass 35, count 0 2006.286.04:00:30.22#ibcon#wrote, iclass 35, count 0 2006.286.04:00:30.22#ibcon#about to read 3, iclass 35, count 0 2006.286.04:00:30.24#ibcon#read 3, iclass 35, count 0 2006.286.04:00:30.24#ibcon#about to read 4, iclass 35, count 0 2006.286.04:00:30.24#ibcon#read 4, iclass 35, count 0 2006.286.04:00:30.24#ibcon#about to read 5, iclass 35, count 0 2006.286.04:00:30.24#ibcon#read 5, iclass 35, count 0 2006.286.04:00:30.24#ibcon#about to read 6, iclass 35, count 0 2006.286.04:00:30.24#ibcon#read 6, iclass 35, count 0 2006.286.04:00:30.24#ibcon#end of sib2, iclass 35, count 0 2006.286.04:00:30.24#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:00:30.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:00:30.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:00:30.24#ibcon#*before write, iclass 35, count 0 2006.286.04:00:30.24#ibcon#enter sib2, iclass 35, count 0 2006.286.04:00:30.24#ibcon#flushed, iclass 35, count 0 2006.286.04:00:30.24#ibcon#about to write, iclass 35, count 0 2006.286.04:00:30.24#ibcon#wrote, iclass 35, count 0 2006.286.04:00:30.24#ibcon#about to read 3, iclass 35, count 0 2006.286.04:00:30.28#ibcon#read 3, iclass 35, count 0 2006.286.04:00:30.28#ibcon#about to read 4, iclass 35, count 0 2006.286.04:00:30.28#ibcon#read 4, iclass 35, count 0 2006.286.04:00:30.28#ibcon#about to read 5, iclass 35, count 0 2006.286.04:00:30.28#ibcon#read 5, iclass 35, count 0 2006.286.04:00:30.28#ibcon#about to read 6, iclass 35, count 0 2006.286.04:00:30.28#ibcon#read 6, iclass 35, count 0 2006.286.04:00:30.28#ibcon#end of sib2, iclass 35, count 0 2006.286.04:00:30.28#ibcon#*after write, iclass 35, count 0 2006.286.04:00:30.28#ibcon#*before return 0, iclass 35, count 0 2006.286.04:00:30.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:00:30.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:00:30.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:00:30.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:00:30.28$vck44/vb=2,5 2006.286.04:00:30.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.04:00:30.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.04:00:30.28#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:30.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:00:30.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:00:30.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:00:30.34#ibcon#enter wrdev, iclass 37, count 2 2006.286.04:00:30.34#ibcon#first serial, iclass 37, count 2 2006.286.04:00:30.34#ibcon#enter sib2, iclass 37, count 2 2006.286.04:00:30.34#ibcon#flushed, iclass 37, count 2 2006.286.04:00:30.34#ibcon#about to write, iclass 37, count 2 2006.286.04:00:30.34#ibcon#wrote, iclass 37, count 2 2006.286.04:00:30.34#ibcon#about to read 3, iclass 37, count 2 2006.286.04:00:30.36#ibcon#read 3, iclass 37, count 2 2006.286.04:00:30.36#ibcon#about to read 4, iclass 37, count 2 2006.286.04:00:30.36#ibcon#read 4, iclass 37, count 2 2006.286.04:00:30.36#ibcon#about to read 5, iclass 37, count 2 2006.286.04:00:30.36#ibcon#read 5, iclass 37, count 2 2006.286.04:00:30.36#ibcon#about to read 6, iclass 37, count 2 2006.286.04:00:30.36#ibcon#read 6, iclass 37, count 2 2006.286.04:00:30.36#ibcon#end of sib2, iclass 37, count 2 2006.286.04:00:30.36#ibcon#*mode == 0, iclass 37, count 2 2006.286.04:00:30.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.04:00:30.36#ibcon#[27=AT02-05\r\n] 2006.286.04:00:30.36#ibcon#*before write, iclass 37, count 2 2006.286.04:00:30.36#ibcon#enter sib2, iclass 37, count 2 2006.286.04:00:30.36#ibcon#flushed, iclass 37, count 2 2006.286.04:00:30.36#ibcon#about to write, iclass 37, count 2 2006.286.04:00:30.36#ibcon#wrote, iclass 37, count 2 2006.286.04:00:30.36#ibcon#about to read 3, iclass 37, count 2 2006.286.04:00:30.39#ibcon#read 3, iclass 37, count 2 2006.286.04:00:30.39#ibcon#about to read 4, iclass 37, count 2 2006.286.04:00:30.39#ibcon#read 4, iclass 37, count 2 2006.286.04:00:30.39#ibcon#about to read 5, iclass 37, count 2 2006.286.04:00:30.39#ibcon#read 5, iclass 37, count 2 2006.286.04:00:30.39#ibcon#about to read 6, iclass 37, count 2 2006.286.04:00:30.39#ibcon#read 6, iclass 37, count 2 2006.286.04:00:30.39#ibcon#end of sib2, iclass 37, count 2 2006.286.04:00:30.39#ibcon#*after write, iclass 37, count 2 2006.286.04:00:30.39#ibcon#*before return 0, iclass 37, count 2 2006.286.04:00:30.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:00:30.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:00:30.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.04:00:30.39#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:30.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:00:30.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:00:30.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:00:30.51#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:00:30.51#ibcon#first serial, iclass 37, count 0 2006.286.04:00:30.51#ibcon#enter sib2, iclass 37, count 0 2006.286.04:00:30.51#ibcon#flushed, iclass 37, count 0 2006.286.04:00:30.51#ibcon#about to write, iclass 37, count 0 2006.286.04:00:30.51#ibcon#wrote, iclass 37, count 0 2006.286.04:00:30.51#ibcon#about to read 3, iclass 37, count 0 2006.286.04:00:30.53#ibcon#read 3, iclass 37, count 0 2006.286.04:00:30.53#ibcon#about to read 4, iclass 37, count 0 2006.286.04:00:30.53#ibcon#read 4, iclass 37, count 0 2006.286.04:00:30.53#ibcon#about to read 5, iclass 37, count 0 2006.286.04:00:30.53#ibcon#read 5, iclass 37, count 0 2006.286.04:00:30.53#ibcon#about to read 6, iclass 37, count 0 2006.286.04:00:30.53#ibcon#read 6, iclass 37, count 0 2006.286.04:00:30.53#ibcon#end of sib2, iclass 37, count 0 2006.286.04:00:30.53#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:00:30.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:00:30.53#ibcon#[27=USB\r\n] 2006.286.04:00:30.53#ibcon#*before write, iclass 37, count 0 2006.286.04:00:30.53#ibcon#enter sib2, iclass 37, count 0 2006.286.04:00:30.53#ibcon#flushed, iclass 37, count 0 2006.286.04:00:30.53#ibcon#about to write, iclass 37, count 0 2006.286.04:00:30.53#ibcon#wrote, iclass 37, count 0 2006.286.04:00:30.53#ibcon#about to read 3, iclass 37, count 0 2006.286.04:00:30.56#ibcon#read 3, iclass 37, count 0 2006.286.04:00:30.56#ibcon#about to read 4, iclass 37, count 0 2006.286.04:00:30.56#ibcon#read 4, iclass 37, count 0 2006.286.04:00:30.56#ibcon#about to read 5, iclass 37, count 0 2006.286.04:00:30.56#ibcon#read 5, iclass 37, count 0 2006.286.04:00:30.56#ibcon#about to read 6, iclass 37, count 0 2006.286.04:00:30.56#ibcon#read 6, iclass 37, count 0 2006.286.04:00:30.56#ibcon#end of sib2, iclass 37, count 0 2006.286.04:00:30.56#ibcon#*after write, iclass 37, count 0 2006.286.04:00:30.56#ibcon#*before return 0, iclass 37, count 0 2006.286.04:00:30.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:00:30.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:00:30.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:00:30.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:00:30.56$vck44/vblo=3,649.99 2006.286.04:00:30.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.04:00:30.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.04:00:30.56#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:30.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:00:30.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:00:30.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:00:30.56#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:00:30.56#ibcon#first serial, iclass 39, count 0 2006.286.04:00:30.56#ibcon#enter sib2, iclass 39, count 0 2006.286.04:00:30.56#ibcon#flushed, iclass 39, count 0 2006.286.04:00:30.56#ibcon#about to write, iclass 39, count 0 2006.286.04:00:30.56#ibcon#wrote, iclass 39, count 0 2006.286.04:00:30.56#ibcon#about to read 3, iclass 39, count 0 2006.286.04:00:30.58#ibcon#read 3, iclass 39, count 0 2006.286.04:00:30.58#ibcon#about to read 4, iclass 39, count 0 2006.286.04:00:30.58#ibcon#read 4, iclass 39, count 0 2006.286.04:00:30.58#ibcon#about to read 5, iclass 39, count 0 2006.286.04:00:30.58#ibcon#read 5, iclass 39, count 0 2006.286.04:00:30.58#ibcon#about to read 6, iclass 39, count 0 2006.286.04:00:30.58#ibcon#read 6, iclass 39, count 0 2006.286.04:00:30.58#ibcon#end of sib2, iclass 39, count 0 2006.286.04:00:30.58#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:00:30.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:00:30.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:00:30.58#ibcon#*before write, iclass 39, count 0 2006.286.04:00:30.58#ibcon#enter sib2, iclass 39, count 0 2006.286.04:00:30.58#ibcon#flushed, iclass 39, count 0 2006.286.04:00:30.58#ibcon#about to write, iclass 39, count 0 2006.286.04:00:30.58#ibcon#wrote, iclass 39, count 0 2006.286.04:00:30.58#ibcon#about to read 3, iclass 39, count 0 2006.286.04:00:30.62#ibcon#read 3, iclass 39, count 0 2006.286.04:00:30.62#ibcon#about to read 4, iclass 39, count 0 2006.286.04:00:30.62#ibcon#read 4, iclass 39, count 0 2006.286.04:00:30.62#ibcon#about to read 5, iclass 39, count 0 2006.286.04:00:30.62#ibcon#read 5, iclass 39, count 0 2006.286.04:00:30.62#ibcon#about to read 6, iclass 39, count 0 2006.286.04:00:30.62#ibcon#read 6, iclass 39, count 0 2006.286.04:00:30.62#ibcon#end of sib2, iclass 39, count 0 2006.286.04:00:30.62#ibcon#*after write, iclass 39, count 0 2006.286.04:00:30.62#ibcon#*before return 0, iclass 39, count 0 2006.286.04:00:30.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:00:30.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:00:30.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:00:30.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:00:30.62$vck44/vb=3,4 2006.286.04:00:30.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.04:00:30.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.04:00:30.62#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:30.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:00:30.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:00:30.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:00:30.68#ibcon#enter wrdev, iclass 3, count 2 2006.286.04:00:30.68#ibcon#first serial, iclass 3, count 2 2006.286.04:00:30.68#ibcon#enter sib2, iclass 3, count 2 2006.286.04:00:30.68#ibcon#flushed, iclass 3, count 2 2006.286.04:00:30.68#ibcon#about to write, iclass 3, count 2 2006.286.04:00:30.68#ibcon#wrote, iclass 3, count 2 2006.286.04:00:30.68#ibcon#about to read 3, iclass 3, count 2 2006.286.04:00:30.70#ibcon#read 3, iclass 3, count 2 2006.286.04:00:30.70#ibcon#about to read 4, iclass 3, count 2 2006.286.04:00:30.70#ibcon#read 4, iclass 3, count 2 2006.286.04:00:30.70#ibcon#about to read 5, iclass 3, count 2 2006.286.04:00:30.70#ibcon#read 5, iclass 3, count 2 2006.286.04:00:30.70#ibcon#about to read 6, iclass 3, count 2 2006.286.04:00:30.70#ibcon#read 6, iclass 3, count 2 2006.286.04:00:30.70#ibcon#end of sib2, iclass 3, count 2 2006.286.04:00:30.70#ibcon#*mode == 0, iclass 3, count 2 2006.286.04:00:30.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.04:00:30.70#ibcon#[27=AT03-04\r\n] 2006.286.04:00:30.70#ibcon#*before write, iclass 3, count 2 2006.286.04:00:30.70#ibcon#enter sib2, iclass 3, count 2 2006.286.04:00:30.70#ibcon#flushed, iclass 3, count 2 2006.286.04:00:30.70#ibcon#about to write, iclass 3, count 2 2006.286.04:00:30.70#ibcon#wrote, iclass 3, count 2 2006.286.04:00:30.70#ibcon#about to read 3, iclass 3, count 2 2006.286.04:00:30.73#ibcon#read 3, iclass 3, count 2 2006.286.04:00:30.73#ibcon#about to read 4, iclass 3, count 2 2006.286.04:00:30.73#ibcon#read 4, iclass 3, count 2 2006.286.04:00:30.73#ibcon#about to read 5, iclass 3, count 2 2006.286.04:00:30.73#ibcon#read 5, iclass 3, count 2 2006.286.04:00:30.73#ibcon#about to read 6, iclass 3, count 2 2006.286.04:00:30.73#ibcon#read 6, iclass 3, count 2 2006.286.04:00:30.73#ibcon#end of sib2, iclass 3, count 2 2006.286.04:00:30.73#ibcon#*after write, iclass 3, count 2 2006.286.04:00:30.73#ibcon#*before return 0, iclass 3, count 2 2006.286.04:00:30.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:00:30.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:00:30.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.04:00:30.73#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:30.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:00:30.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:00:30.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:00:30.85#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:00:30.85#ibcon#first serial, iclass 3, count 0 2006.286.04:00:30.85#ibcon#enter sib2, iclass 3, count 0 2006.286.04:00:30.85#ibcon#flushed, iclass 3, count 0 2006.286.04:00:30.85#ibcon#about to write, iclass 3, count 0 2006.286.04:00:30.85#ibcon#wrote, iclass 3, count 0 2006.286.04:00:30.85#ibcon#about to read 3, iclass 3, count 0 2006.286.04:00:30.87#ibcon#read 3, iclass 3, count 0 2006.286.04:00:30.87#ibcon#about to read 4, iclass 3, count 0 2006.286.04:00:30.87#ibcon#read 4, iclass 3, count 0 2006.286.04:00:30.87#ibcon#about to read 5, iclass 3, count 0 2006.286.04:00:30.87#ibcon#read 5, iclass 3, count 0 2006.286.04:00:30.87#ibcon#about to read 6, iclass 3, count 0 2006.286.04:00:30.87#ibcon#read 6, iclass 3, count 0 2006.286.04:00:30.87#ibcon#end of sib2, iclass 3, count 0 2006.286.04:00:30.87#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:00:30.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:00:30.87#ibcon#[27=USB\r\n] 2006.286.04:00:30.87#ibcon#*before write, iclass 3, count 0 2006.286.04:00:30.87#ibcon#enter sib2, iclass 3, count 0 2006.286.04:00:30.87#ibcon#flushed, iclass 3, count 0 2006.286.04:00:30.87#ibcon#about to write, iclass 3, count 0 2006.286.04:00:30.87#ibcon#wrote, iclass 3, count 0 2006.286.04:00:30.87#ibcon#about to read 3, iclass 3, count 0 2006.286.04:00:30.90#ibcon#read 3, iclass 3, count 0 2006.286.04:00:30.90#ibcon#about to read 4, iclass 3, count 0 2006.286.04:00:30.90#ibcon#read 4, iclass 3, count 0 2006.286.04:00:30.90#ibcon#about to read 5, iclass 3, count 0 2006.286.04:00:30.90#ibcon#read 5, iclass 3, count 0 2006.286.04:00:30.90#ibcon#about to read 6, iclass 3, count 0 2006.286.04:00:30.90#ibcon#read 6, iclass 3, count 0 2006.286.04:00:30.90#ibcon#end of sib2, iclass 3, count 0 2006.286.04:00:30.90#ibcon#*after write, iclass 3, count 0 2006.286.04:00:30.90#ibcon#*before return 0, iclass 3, count 0 2006.286.04:00:30.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:00:30.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:00:30.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:00:30.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:00:30.90$vck44/vblo=4,679.99 2006.286.04:00:30.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.04:00:30.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.04:00:30.90#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:30.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:00:30.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:00:30.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:00:30.90#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:00:30.90#ibcon#first serial, iclass 5, count 0 2006.286.04:00:30.90#ibcon#enter sib2, iclass 5, count 0 2006.286.04:00:30.90#ibcon#flushed, iclass 5, count 0 2006.286.04:00:30.90#ibcon#about to write, iclass 5, count 0 2006.286.04:00:30.90#ibcon#wrote, iclass 5, count 0 2006.286.04:00:30.90#ibcon#about to read 3, iclass 5, count 0 2006.286.04:00:30.92#ibcon#read 3, iclass 5, count 0 2006.286.04:00:30.92#ibcon#about to read 4, iclass 5, count 0 2006.286.04:00:30.92#ibcon#read 4, iclass 5, count 0 2006.286.04:00:30.92#ibcon#about to read 5, iclass 5, count 0 2006.286.04:00:30.92#ibcon#read 5, iclass 5, count 0 2006.286.04:00:30.92#ibcon#about to read 6, iclass 5, count 0 2006.286.04:00:30.92#ibcon#read 6, iclass 5, count 0 2006.286.04:00:30.92#ibcon#end of sib2, iclass 5, count 0 2006.286.04:00:30.92#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:00:30.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:00:30.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:00:30.92#ibcon#*before write, iclass 5, count 0 2006.286.04:00:30.92#ibcon#enter sib2, iclass 5, count 0 2006.286.04:00:30.92#ibcon#flushed, iclass 5, count 0 2006.286.04:00:30.92#ibcon#about to write, iclass 5, count 0 2006.286.04:00:30.92#ibcon#wrote, iclass 5, count 0 2006.286.04:00:30.92#ibcon#about to read 3, iclass 5, count 0 2006.286.04:00:30.96#ibcon#read 3, iclass 5, count 0 2006.286.04:00:30.96#ibcon#about to read 4, iclass 5, count 0 2006.286.04:00:30.96#ibcon#read 4, iclass 5, count 0 2006.286.04:00:30.96#ibcon#about to read 5, iclass 5, count 0 2006.286.04:00:30.96#ibcon#read 5, iclass 5, count 0 2006.286.04:00:30.96#ibcon#about to read 6, iclass 5, count 0 2006.286.04:00:30.96#ibcon#read 6, iclass 5, count 0 2006.286.04:00:30.96#ibcon#end of sib2, iclass 5, count 0 2006.286.04:00:30.96#ibcon#*after write, iclass 5, count 0 2006.286.04:00:30.96#ibcon#*before return 0, iclass 5, count 0 2006.286.04:00:30.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:00:30.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:00:30.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:00:30.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:00:30.96$vck44/vb=4,5 2006.286.04:00:30.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.04:00:30.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.04:00:30.96#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:30.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:00:31.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:00:31.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:00:31.02#ibcon#enter wrdev, iclass 7, count 2 2006.286.04:00:31.02#ibcon#first serial, iclass 7, count 2 2006.286.04:00:31.02#ibcon#enter sib2, iclass 7, count 2 2006.286.04:00:31.02#ibcon#flushed, iclass 7, count 2 2006.286.04:00:31.02#ibcon#about to write, iclass 7, count 2 2006.286.04:00:31.02#ibcon#wrote, iclass 7, count 2 2006.286.04:00:31.02#ibcon#about to read 3, iclass 7, count 2 2006.286.04:00:31.04#ibcon#read 3, iclass 7, count 2 2006.286.04:00:31.04#ibcon#about to read 4, iclass 7, count 2 2006.286.04:00:31.04#ibcon#read 4, iclass 7, count 2 2006.286.04:00:31.04#ibcon#about to read 5, iclass 7, count 2 2006.286.04:00:31.04#ibcon#read 5, iclass 7, count 2 2006.286.04:00:31.04#ibcon#about to read 6, iclass 7, count 2 2006.286.04:00:31.04#ibcon#read 6, iclass 7, count 2 2006.286.04:00:31.04#ibcon#end of sib2, iclass 7, count 2 2006.286.04:00:31.04#ibcon#*mode == 0, iclass 7, count 2 2006.286.04:00:31.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.04:00:31.04#ibcon#[27=AT04-05\r\n] 2006.286.04:00:31.04#ibcon#*before write, iclass 7, count 2 2006.286.04:00:31.04#ibcon#enter sib2, iclass 7, count 2 2006.286.04:00:31.04#ibcon#flushed, iclass 7, count 2 2006.286.04:00:31.04#ibcon#about to write, iclass 7, count 2 2006.286.04:00:31.04#ibcon#wrote, iclass 7, count 2 2006.286.04:00:31.04#ibcon#about to read 3, iclass 7, count 2 2006.286.04:00:31.07#ibcon#read 3, iclass 7, count 2 2006.286.04:00:31.07#ibcon#about to read 4, iclass 7, count 2 2006.286.04:00:31.07#ibcon#read 4, iclass 7, count 2 2006.286.04:00:31.07#ibcon#about to read 5, iclass 7, count 2 2006.286.04:00:31.07#ibcon#read 5, iclass 7, count 2 2006.286.04:00:31.07#ibcon#about to read 6, iclass 7, count 2 2006.286.04:00:31.07#ibcon#read 6, iclass 7, count 2 2006.286.04:00:31.07#ibcon#end of sib2, iclass 7, count 2 2006.286.04:00:31.07#ibcon#*after write, iclass 7, count 2 2006.286.04:00:31.07#ibcon#*before return 0, iclass 7, count 2 2006.286.04:00:31.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:00:31.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:00:31.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.04:00:31.07#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:31.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:00:31.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:00:31.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:00:31.19#ibcon#enter wrdev, iclass 7, count 0 2006.286.04:00:31.19#ibcon#first serial, iclass 7, count 0 2006.286.04:00:31.19#ibcon#enter sib2, iclass 7, count 0 2006.286.04:00:31.19#ibcon#flushed, iclass 7, count 0 2006.286.04:00:31.19#ibcon#about to write, iclass 7, count 0 2006.286.04:00:31.19#ibcon#wrote, iclass 7, count 0 2006.286.04:00:31.19#ibcon#about to read 3, iclass 7, count 0 2006.286.04:00:31.21#ibcon#read 3, iclass 7, count 0 2006.286.04:00:31.21#ibcon#about to read 4, iclass 7, count 0 2006.286.04:00:31.21#ibcon#read 4, iclass 7, count 0 2006.286.04:00:31.21#ibcon#about to read 5, iclass 7, count 0 2006.286.04:00:31.21#ibcon#read 5, iclass 7, count 0 2006.286.04:00:31.21#ibcon#about to read 6, iclass 7, count 0 2006.286.04:00:31.21#ibcon#read 6, iclass 7, count 0 2006.286.04:00:31.21#ibcon#end of sib2, iclass 7, count 0 2006.286.04:00:31.21#ibcon#*mode == 0, iclass 7, count 0 2006.286.04:00:31.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.04:00:31.21#ibcon#[27=USB\r\n] 2006.286.04:00:31.21#ibcon#*before write, iclass 7, count 0 2006.286.04:00:31.21#ibcon#enter sib2, iclass 7, count 0 2006.286.04:00:31.21#ibcon#flushed, iclass 7, count 0 2006.286.04:00:31.21#ibcon#about to write, iclass 7, count 0 2006.286.04:00:31.21#ibcon#wrote, iclass 7, count 0 2006.286.04:00:31.21#ibcon#about to read 3, iclass 7, count 0 2006.286.04:00:31.24#ibcon#read 3, iclass 7, count 0 2006.286.04:00:31.36#ibcon#about to read 4, iclass 7, count 0 2006.286.04:00:31.36#ibcon#read 4, iclass 7, count 0 2006.286.04:00:31.36#ibcon#about to read 5, iclass 7, count 0 2006.286.04:00:31.36#ibcon#read 5, iclass 7, count 0 2006.286.04:00:31.36#ibcon#about to read 6, iclass 7, count 0 2006.286.04:00:31.36#ibcon#read 6, iclass 7, count 0 2006.286.04:00:31.36#ibcon#end of sib2, iclass 7, count 0 2006.286.04:00:31.36#ibcon#*after write, iclass 7, count 0 2006.286.04:00:31.36#ibcon#*before return 0, iclass 7, count 0 2006.286.04:00:31.36#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:00:31.36#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:00:31.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.04:00:31.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.04:00:31.36$vck44/vblo=5,709.99 2006.286.04:00:31.36#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.04:00:31.36#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.04:00:31.36#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:31.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:00:31.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:00:31.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:00:31.36#ibcon#enter wrdev, iclass 11, count 0 2006.286.04:00:31.36#ibcon#first serial, iclass 11, count 0 2006.286.04:00:31.36#ibcon#enter sib2, iclass 11, count 0 2006.286.04:00:31.36#ibcon#flushed, iclass 11, count 0 2006.286.04:00:31.36#ibcon#about to write, iclass 11, count 0 2006.286.04:00:31.36#ibcon#wrote, iclass 11, count 0 2006.286.04:00:31.36#ibcon#about to read 3, iclass 11, count 0 2006.286.04:00:31.38#ibcon#read 3, iclass 11, count 0 2006.286.04:00:31.38#ibcon#about to read 4, iclass 11, count 0 2006.286.04:00:31.38#ibcon#read 4, iclass 11, count 0 2006.286.04:00:31.38#ibcon#about to read 5, iclass 11, count 0 2006.286.04:00:31.38#ibcon#read 5, iclass 11, count 0 2006.286.04:00:31.38#ibcon#about to read 6, iclass 11, count 0 2006.286.04:00:31.38#ibcon#read 6, iclass 11, count 0 2006.286.04:00:31.38#ibcon#end of sib2, iclass 11, count 0 2006.286.04:00:31.38#ibcon#*mode == 0, iclass 11, count 0 2006.286.04:00:31.38#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.04:00:31.38#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:00:31.38#ibcon#*before write, iclass 11, count 0 2006.286.04:00:31.38#ibcon#enter sib2, iclass 11, count 0 2006.286.04:00:31.38#ibcon#flushed, iclass 11, count 0 2006.286.04:00:31.38#ibcon#about to write, iclass 11, count 0 2006.286.04:00:31.38#ibcon#wrote, iclass 11, count 0 2006.286.04:00:31.38#ibcon#about to read 3, iclass 11, count 0 2006.286.04:00:31.42#ibcon#read 3, iclass 11, count 0 2006.286.04:00:31.42#ibcon#about to read 4, iclass 11, count 0 2006.286.04:00:31.42#ibcon#read 4, iclass 11, count 0 2006.286.04:00:31.42#ibcon#about to read 5, iclass 11, count 0 2006.286.04:00:31.42#ibcon#read 5, iclass 11, count 0 2006.286.04:00:31.42#ibcon#about to read 6, iclass 11, count 0 2006.286.04:00:31.42#ibcon#read 6, iclass 11, count 0 2006.286.04:00:31.42#ibcon#end of sib2, iclass 11, count 0 2006.286.04:00:31.42#ibcon#*after write, iclass 11, count 0 2006.286.04:00:31.42#ibcon#*before return 0, iclass 11, count 0 2006.286.04:00:31.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:00:31.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:00:31.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.04:00:31.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.04:00:31.42$vck44/vb=5,4 2006.286.04:00:31.42#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.04:00:31.42#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.04:00:31.42#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:31.42#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:00:31.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:00:31.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:00:31.48#ibcon#enter wrdev, iclass 13, count 2 2006.286.04:00:31.48#ibcon#first serial, iclass 13, count 2 2006.286.04:00:31.48#ibcon#enter sib2, iclass 13, count 2 2006.286.04:00:31.48#ibcon#flushed, iclass 13, count 2 2006.286.04:00:31.48#ibcon#about to write, iclass 13, count 2 2006.286.04:00:31.48#ibcon#wrote, iclass 13, count 2 2006.286.04:00:31.48#ibcon#about to read 3, iclass 13, count 2 2006.286.04:00:31.50#ibcon#read 3, iclass 13, count 2 2006.286.04:00:31.50#ibcon#about to read 4, iclass 13, count 2 2006.286.04:00:31.50#ibcon#read 4, iclass 13, count 2 2006.286.04:00:31.50#ibcon#about to read 5, iclass 13, count 2 2006.286.04:00:31.50#ibcon#read 5, iclass 13, count 2 2006.286.04:00:31.50#ibcon#about to read 6, iclass 13, count 2 2006.286.04:00:31.50#ibcon#read 6, iclass 13, count 2 2006.286.04:00:31.50#ibcon#end of sib2, iclass 13, count 2 2006.286.04:00:31.50#ibcon#*mode == 0, iclass 13, count 2 2006.286.04:00:31.50#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.04:00:31.50#ibcon#[27=AT05-04\r\n] 2006.286.04:00:31.50#ibcon#*before write, iclass 13, count 2 2006.286.04:00:31.50#ibcon#enter sib2, iclass 13, count 2 2006.286.04:00:31.50#ibcon#flushed, iclass 13, count 2 2006.286.04:00:31.50#ibcon#about to write, iclass 13, count 2 2006.286.04:00:31.50#ibcon#wrote, iclass 13, count 2 2006.286.04:00:31.50#ibcon#about to read 3, iclass 13, count 2 2006.286.04:00:31.53#ibcon#read 3, iclass 13, count 2 2006.286.04:00:31.53#ibcon#about to read 4, iclass 13, count 2 2006.286.04:00:31.53#ibcon#read 4, iclass 13, count 2 2006.286.04:00:31.53#ibcon#about to read 5, iclass 13, count 2 2006.286.04:00:31.53#ibcon#read 5, iclass 13, count 2 2006.286.04:00:31.53#ibcon#about to read 6, iclass 13, count 2 2006.286.04:00:31.53#ibcon#read 6, iclass 13, count 2 2006.286.04:00:31.53#ibcon#end of sib2, iclass 13, count 2 2006.286.04:00:31.53#ibcon#*after write, iclass 13, count 2 2006.286.04:00:31.53#ibcon#*before return 0, iclass 13, count 2 2006.286.04:00:31.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:00:31.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:00:31.53#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.04:00:31.53#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:31.53#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:00:31.65#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:00:31.65#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:00:31.65#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:00:31.65#ibcon#first serial, iclass 13, count 0 2006.286.04:00:31.65#ibcon#enter sib2, iclass 13, count 0 2006.286.04:00:31.65#ibcon#flushed, iclass 13, count 0 2006.286.04:00:31.65#ibcon#about to write, iclass 13, count 0 2006.286.04:00:31.65#ibcon#wrote, iclass 13, count 0 2006.286.04:00:31.65#ibcon#about to read 3, iclass 13, count 0 2006.286.04:00:31.67#ibcon#read 3, iclass 13, count 0 2006.286.04:00:31.67#ibcon#about to read 4, iclass 13, count 0 2006.286.04:00:31.67#ibcon#read 4, iclass 13, count 0 2006.286.04:00:31.67#ibcon#about to read 5, iclass 13, count 0 2006.286.04:00:31.67#ibcon#read 5, iclass 13, count 0 2006.286.04:00:31.67#ibcon#about to read 6, iclass 13, count 0 2006.286.04:00:31.67#ibcon#read 6, iclass 13, count 0 2006.286.04:00:31.67#ibcon#end of sib2, iclass 13, count 0 2006.286.04:00:31.67#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:00:31.67#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:00:31.67#ibcon#[27=USB\r\n] 2006.286.04:00:31.67#ibcon#*before write, iclass 13, count 0 2006.286.04:00:31.67#ibcon#enter sib2, iclass 13, count 0 2006.286.04:00:31.67#ibcon#flushed, iclass 13, count 0 2006.286.04:00:31.67#ibcon#about to write, iclass 13, count 0 2006.286.04:00:31.67#ibcon#wrote, iclass 13, count 0 2006.286.04:00:31.67#ibcon#about to read 3, iclass 13, count 0 2006.286.04:00:31.70#ibcon#read 3, iclass 13, count 0 2006.286.04:00:31.70#ibcon#about to read 4, iclass 13, count 0 2006.286.04:00:31.70#ibcon#read 4, iclass 13, count 0 2006.286.04:00:31.70#ibcon#about to read 5, iclass 13, count 0 2006.286.04:00:31.70#ibcon#read 5, iclass 13, count 0 2006.286.04:00:31.70#ibcon#about to read 6, iclass 13, count 0 2006.286.04:00:31.70#ibcon#read 6, iclass 13, count 0 2006.286.04:00:31.70#ibcon#end of sib2, iclass 13, count 0 2006.286.04:00:31.70#ibcon#*after write, iclass 13, count 0 2006.286.04:00:31.70#ibcon#*before return 0, iclass 13, count 0 2006.286.04:00:31.70#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:00:31.70#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:00:31.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:00:31.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:00:31.70$vck44/vblo=6,719.99 2006.286.04:00:31.70#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.04:00:31.70#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.04:00:31.70#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:31.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:00:31.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:00:31.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:00:31.70#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:00:31.70#ibcon#first serial, iclass 15, count 0 2006.286.04:00:31.70#ibcon#enter sib2, iclass 15, count 0 2006.286.04:00:31.70#ibcon#flushed, iclass 15, count 0 2006.286.04:00:31.70#ibcon#about to write, iclass 15, count 0 2006.286.04:00:31.70#ibcon#wrote, iclass 15, count 0 2006.286.04:00:31.70#ibcon#about to read 3, iclass 15, count 0 2006.286.04:00:31.72#ibcon#read 3, iclass 15, count 0 2006.286.04:00:31.72#ibcon#about to read 4, iclass 15, count 0 2006.286.04:00:31.72#ibcon#read 4, iclass 15, count 0 2006.286.04:00:31.72#ibcon#about to read 5, iclass 15, count 0 2006.286.04:00:31.72#ibcon#read 5, iclass 15, count 0 2006.286.04:00:31.72#ibcon#about to read 6, iclass 15, count 0 2006.286.04:00:31.72#ibcon#read 6, iclass 15, count 0 2006.286.04:00:31.72#ibcon#end of sib2, iclass 15, count 0 2006.286.04:00:31.72#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:00:31.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:00:31.72#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:00:31.72#ibcon#*before write, iclass 15, count 0 2006.286.04:00:31.72#ibcon#enter sib2, iclass 15, count 0 2006.286.04:00:31.72#ibcon#flushed, iclass 15, count 0 2006.286.04:00:31.72#ibcon#about to write, iclass 15, count 0 2006.286.04:00:31.72#ibcon#wrote, iclass 15, count 0 2006.286.04:00:31.72#ibcon#about to read 3, iclass 15, count 0 2006.286.04:00:31.76#ibcon#read 3, iclass 15, count 0 2006.286.04:00:31.76#ibcon#about to read 4, iclass 15, count 0 2006.286.04:00:31.76#ibcon#read 4, iclass 15, count 0 2006.286.04:00:31.76#ibcon#about to read 5, iclass 15, count 0 2006.286.04:00:31.76#ibcon#read 5, iclass 15, count 0 2006.286.04:00:31.76#ibcon#about to read 6, iclass 15, count 0 2006.286.04:00:31.76#ibcon#read 6, iclass 15, count 0 2006.286.04:00:31.76#ibcon#end of sib2, iclass 15, count 0 2006.286.04:00:31.76#ibcon#*after write, iclass 15, count 0 2006.286.04:00:31.76#ibcon#*before return 0, iclass 15, count 0 2006.286.04:00:31.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:00:31.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:00:31.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:00:31.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:00:31.76$vck44/vb=6,3 2006.286.04:00:31.76#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.04:00:31.76#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.04:00:31.76#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:31.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:00:31.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:00:31.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:00:31.82#ibcon#enter wrdev, iclass 17, count 2 2006.286.04:00:31.82#ibcon#first serial, iclass 17, count 2 2006.286.04:00:31.82#ibcon#enter sib2, iclass 17, count 2 2006.286.04:00:31.82#ibcon#flushed, iclass 17, count 2 2006.286.04:00:31.82#ibcon#about to write, iclass 17, count 2 2006.286.04:00:31.82#ibcon#wrote, iclass 17, count 2 2006.286.04:00:31.82#ibcon#about to read 3, iclass 17, count 2 2006.286.04:00:31.84#ibcon#read 3, iclass 17, count 2 2006.286.04:00:31.84#ibcon#about to read 4, iclass 17, count 2 2006.286.04:00:31.84#ibcon#read 4, iclass 17, count 2 2006.286.04:00:31.84#ibcon#about to read 5, iclass 17, count 2 2006.286.04:00:31.84#ibcon#read 5, iclass 17, count 2 2006.286.04:00:31.84#ibcon#about to read 6, iclass 17, count 2 2006.286.04:00:31.84#ibcon#read 6, iclass 17, count 2 2006.286.04:00:31.84#ibcon#end of sib2, iclass 17, count 2 2006.286.04:00:31.84#ibcon#*mode == 0, iclass 17, count 2 2006.286.04:00:31.84#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.04:00:31.84#ibcon#[27=AT06-03\r\n] 2006.286.04:00:31.84#ibcon#*before write, iclass 17, count 2 2006.286.04:00:31.84#ibcon#enter sib2, iclass 17, count 2 2006.286.04:00:31.84#ibcon#flushed, iclass 17, count 2 2006.286.04:00:31.84#ibcon#about to write, iclass 17, count 2 2006.286.04:00:31.84#ibcon#wrote, iclass 17, count 2 2006.286.04:00:31.84#ibcon#about to read 3, iclass 17, count 2 2006.286.04:00:31.87#ibcon#read 3, iclass 17, count 2 2006.286.04:00:31.87#ibcon#about to read 4, iclass 17, count 2 2006.286.04:00:31.87#ibcon#read 4, iclass 17, count 2 2006.286.04:00:31.87#ibcon#about to read 5, iclass 17, count 2 2006.286.04:00:31.87#ibcon#read 5, iclass 17, count 2 2006.286.04:00:31.87#ibcon#about to read 6, iclass 17, count 2 2006.286.04:00:31.87#ibcon#read 6, iclass 17, count 2 2006.286.04:00:31.87#ibcon#end of sib2, iclass 17, count 2 2006.286.04:00:31.87#ibcon#*after write, iclass 17, count 2 2006.286.04:00:31.87#ibcon#*before return 0, iclass 17, count 2 2006.286.04:00:31.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:00:31.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:00:31.87#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.04:00:31.87#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:31.87#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:00:31.99#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:00:31.99#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:00:31.99#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:00:31.99#ibcon#first serial, iclass 17, count 0 2006.286.04:00:31.99#ibcon#enter sib2, iclass 17, count 0 2006.286.04:00:31.99#ibcon#flushed, iclass 17, count 0 2006.286.04:00:31.99#ibcon#about to write, iclass 17, count 0 2006.286.04:00:31.99#ibcon#wrote, iclass 17, count 0 2006.286.04:00:31.99#ibcon#about to read 3, iclass 17, count 0 2006.286.04:00:32.01#ibcon#read 3, iclass 17, count 0 2006.286.04:00:32.01#ibcon#about to read 4, iclass 17, count 0 2006.286.04:00:32.01#ibcon#read 4, iclass 17, count 0 2006.286.04:00:32.01#ibcon#about to read 5, iclass 17, count 0 2006.286.04:00:32.01#ibcon#read 5, iclass 17, count 0 2006.286.04:00:32.01#ibcon#about to read 6, iclass 17, count 0 2006.286.04:00:32.01#ibcon#read 6, iclass 17, count 0 2006.286.04:00:32.01#ibcon#end of sib2, iclass 17, count 0 2006.286.04:00:32.01#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:00:32.01#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:00:32.01#ibcon#[27=USB\r\n] 2006.286.04:00:32.01#ibcon#*before write, iclass 17, count 0 2006.286.04:00:32.01#ibcon#enter sib2, iclass 17, count 0 2006.286.04:00:32.01#ibcon#flushed, iclass 17, count 0 2006.286.04:00:32.01#ibcon#about to write, iclass 17, count 0 2006.286.04:00:32.01#ibcon#wrote, iclass 17, count 0 2006.286.04:00:32.01#ibcon#about to read 3, iclass 17, count 0 2006.286.04:00:32.04#ibcon#read 3, iclass 17, count 0 2006.286.04:00:32.04#ibcon#about to read 4, iclass 17, count 0 2006.286.04:00:32.04#ibcon#read 4, iclass 17, count 0 2006.286.04:00:32.04#ibcon#about to read 5, iclass 17, count 0 2006.286.04:00:32.04#ibcon#read 5, iclass 17, count 0 2006.286.04:00:32.04#ibcon#about to read 6, iclass 17, count 0 2006.286.04:00:32.04#ibcon#read 6, iclass 17, count 0 2006.286.04:00:32.04#ibcon#end of sib2, iclass 17, count 0 2006.286.04:00:32.04#ibcon#*after write, iclass 17, count 0 2006.286.04:00:32.04#ibcon#*before return 0, iclass 17, count 0 2006.286.04:00:32.04#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:00:32.04#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:00:32.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:00:32.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:00:32.04$vck44/vblo=7,734.99 2006.286.04:00:32.04#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.04:00:32.04#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.04:00:32.04#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:32.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:00:32.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:00:32.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:00:32.04#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:00:32.04#ibcon#first serial, iclass 19, count 0 2006.286.04:00:32.04#ibcon#enter sib2, iclass 19, count 0 2006.286.04:00:32.04#ibcon#flushed, iclass 19, count 0 2006.286.04:00:32.04#ibcon#about to write, iclass 19, count 0 2006.286.04:00:32.04#ibcon#wrote, iclass 19, count 0 2006.286.04:00:32.04#ibcon#about to read 3, iclass 19, count 0 2006.286.04:00:32.06#ibcon#read 3, iclass 19, count 0 2006.286.04:00:32.06#ibcon#about to read 4, iclass 19, count 0 2006.286.04:00:32.06#ibcon#read 4, iclass 19, count 0 2006.286.04:00:32.06#ibcon#about to read 5, iclass 19, count 0 2006.286.04:00:32.06#ibcon#read 5, iclass 19, count 0 2006.286.04:00:32.06#ibcon#about to read 6, iclass 19, count 0 2006.286.04:00:32.06#ibcon#read 6, iclass 19, count 0 2006.286.04:00:32.06#ibcon#end of sib2, iclass 19, count 0 2006.286.04:00:32.06#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:00:32.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:00:32.06#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:00:32.06#ibcon#*before write, iclass 19, count 0 2006.286.04:00:32.06#ibcon#enter sib2, iclass 19, count 0 2006.286.04:00:32.06#ibcon#flushed, iclass 19, count 0 2006.286.04:00:32.06#ibcon#about to write, iclass 19, count 0 2006.286.04:00:32.06#ibcon#wrote, iclass 19, count 0 2006.286.04:00:32.06#ibcon#about to read 3, iclass 19, count 0 2006.286.04:00:32.10#ibcon#read 3, iclass 19, count 0 2006.286.04:00:32.10#ibcon#about to read 4, iclass 19, count 0 2006.286.04:00:32.10#ibcon#read 4, iclass 19, count 0 2006.286.04:00:32.10#ibcon#about to read 5, iclass 19, count 0 2006.286.04:00:32.10#ibcon#read 5, iclass 19, count 0 2006.286.04:00:32.10#ibcon#about to read 6, iclass 19, count 0 2006.286.04:00:32.10#ibcon#read 6, iclass 19, count 0 2006.286.04:00:32.10#ibcon#end of sib2, iclass 19, count 0 2006.286.04:00:32.10#ibcon#*after write, iclass 19, count 0 2006.286.04:00:32.10#ibcon#*before return 0, iclass 19, count 0 2006.286.04:00:32.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:00:32.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:00:32.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:00:32.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:00:32.10$vck44/vb=7,4 2006.286.04:00:32.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.04:00:32.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.04:00:32.10#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:32.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:00:32.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:00:32.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:00:32.16#ibcon#enter wrdev, iclass 21, count 2 2006.286.04:00:32.16#ibcon#first serial, iclass 21, count 2 2006.286.04:00:32.16#ibcon#enter sib2, iclass 21, count 2 2006.286.04:00:32.16#ibcon#flushed, iclass 21, count 2 2006.286.04:00:32.16#ibcon#about to write, iclass 21, count 2 2006.286.04:00:32.16#ibcon#wrote, iclass 21, count 2 2006.286.04:00:32.16#ibcon#about to read 3, iclass 21, count 2 2006.286.04:00:32.18#ibcon#read 3, iclass 21, count 2 2006.286.04:00:32.39#ibcon#about to read 4, iclass 21, count 2 2006.286.04:00:32.39#ibcon#read 4, iclass 21, count 2 2006.286.04:00:32.39#ibcon#about to read 5, iclass 21, count 2 2006.286.04:00:32.39#ibcon#read 5, iclass 21, count 2 2006.286.04:00:32.39#ibcon#about to read 6, iclass 21, count 2 2006.286.04:00:32.39#ibcon#read 6, iclass 21, count 2 2006.286.04:00:32.39#ibcon#end of sib2, iclass 21, count 2 2006.286.04:00:32.39#ibcon#*mode == 0, iclass 21, count 2 2006.286.04:00:32.39#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.04:00:32.39#ibcon#[27=AT07-04\r\n] 2006.286.04:00:32.39#ibcon#*before write, iclass 21, count 2 2006.286.04:00:32.39#ibcon#enter sib2, iclass 21, count 2 2006.286.04:00:32.39#ibcon#flushed, iclass 21, count 2 2006.286.04:00:32.39#ibcon#about to write, iclass 21, count 2 2006.286.04:00:32.39#ibcon#wrote, iclass 21, count 2 2006.286.04:00:32.39#ibcon#about to read 3, iclass 21, count 2 2006.286.04:00:32.42#ibcon#read 3, iclass 21, count 2 2006.286.04:00:32.42#ibcon#about to read 4, iclass 21, count 2 2006.286.04:00:32.42#ibcon#read 4, iclass 21, count 2 2006.286.04:00:32.42#ibcon#about to read 5, iclass 21, count 2 2006.286.04:00:32.42#ibcon#read 5, iclass 21, count 2 2006.286.04:00:32.42#ibcon#about to read 6, iclass 21, count 2 2006.286.04:00:32.42#ibcon#read 6, iclass 21, count 2 2006.286.04:00:32.42#ibcon#end of sib2, iclass 21, count 2 2006.286.04:00:32.42#ibcon#*after write, iclass 21, count 2 2006.286.04:00:32.42#ibcon#*before return 0, iclass 21, count 2 2006.286.04:00:32.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:00:32.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:00:32.42#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.04:00:32.42#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:32.42#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:00:32.54#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:00:32.54#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:00:32.54#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:00:32.54#ibcon#first serial, iclass 21, count 0 2006.286.04:00:32.54#ibcon#enter sib2, iclass 21, count 0 2006.286.04:00:32.54#ibcon#flushed, iclass 21, count 0 2006.286.04:00:32.54#ibcon#about to write, iclass 21, count 0 2006.286.04:00:32.54#ibcon#wrote, iclass 21, count 0 2006.286.04:00:32.54#ibcon#about to read 3, iclass 21, count 0 2006.286.04:00:32.56#ibcon#read 3, iclass 21, count 0 2006.286.04:00:32.56#ibcon#about to read 4, iclass 21, count 0 2006.286.04:00:32.56#ibcon#read 4, iclass 21, count 0 2006.286.04:00:32.56#ibcon#about to read 5, iclass 21, count 0 2006.286.04:00:32.56#ibcon#read 5, iclass 21, count 0 2006.286.04:00:32.56#ibcon#about to read 6, iclass 21, count 0 2006.286.04:00:32.56#ibcon#read 6, iclass 21, count 0 2006.286.04:00:32.56#ibcon#end of sib2, iclass 21, count 0 2006.286.04:00:32.56#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:00:32.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:00:32.56#ibcon#[27=USB\r\n] 2006.286.04:00:32.56#ibcon#*before write, iclass 21, count 0 2006.286.04:00:32.56#ibcon#enter sib2, iclass 21, count 0 2006.286.04:00:32.56#ibcon#flushed, iclass 21, count 0 2006.286.04:00:32.56#ibcon#about to write, iclass 21, count 0 2006.286.04:00:32.56#ibcon#wrote, iclass 21, count 0 2006.286.04:00:32.56#ibcon#about to read 3, iclass 21, count 0 2006.286.04:00:32.59#ibcon#read 3, iclass 21, count 0 2006.286.04:00:32.59#ibcon#about to read 4, iclass 21, count 0 2006.286.04:00:32.59#ibcon#read 4, iclass 21, count 0 2006.286.04:00:32.59#ibcon#about to read 5, iclass 21, count 0 2006.286.04:00:32.59#ibcon#read 5, iclass 21, count 0 2006.286.04:00:32.59#ibcon#about to read 6, iclass 21, count 0 2006.286.04:00:32.59#ibcon#read 6, iclass 21, count 0 2006.286.04:00:32.59#ibcon#end of sib2, iclass 21, count 0 2006.286.04:00:32.59#ibcon#*after write, iclass 21, count 0 2006.286.04:00:32.59#ibcon#*before return 0, iclass 21, count 0 2006.286.04:00:32.59#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:00:32.59#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:00:32.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:00:32.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:00:32.59$vck44/vblo=8,744.99 2006.286.04:00:32.59#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.04:00:32.59#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.04:00:32.59#ibcon#ireg 17 cls_cnt 0 2006.286.04:00:32.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:00:32.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:00:32.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:00:32.59#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:00:32.59#ibcon#first serial, iclass 23, count 0 2006.286.04:00:32.59#ibcon#enter sib2, iclass 23, count 0 2006.286.04:00:32.59#ibcon#flushed, iclass 23, count 0 2006.286.04:00:32.59#ibcon#about to write, iclass 23, count 0 2006.286.04:00:32.59#ibcon#wrote, iclass 23, count 0 2006.286.04:00:32.59#ibcon#about to read 3, iclass 23, count 0 2006.286.04:00:32.61#ibcon#read 3, iclass 23, count 0 2006.286.04:00:32.61#ibcon#about to read 4, iclass 23, count 0 2006.286.04:00:32.61#ibcon#read 4, iclass 23, count 0 2006.286.04:00:32.61#ibcon#about to read 5, iclass 23, count 0 2006.286.04:00:32.61#ibcon#read 5, iclass 23, count 0 2006.286.04:00:32.61#ibcon#about to read 6, iclass 23, count 0 2006.286.04:00:32.61#ibcon#read 6, iclass 23, count 0 2006.286.04:00:32.61#ibcon#end of sib2, iclass 23, count 0 2006.286.04:00:32.61#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:00:32.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:00:32.61#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:00:32.61#ibcon#*before write, iclass 23, count 0 2006.286.04:00:32.61#ibcon#enter sib2, iclass 23, count 0 2006.286.04:00:32.61#ibcon#flushed, iclass 23, count 0 2006.286.04:00:32.61#ibcon#about to write, iclass 23, count 0 2006.286.04:00:32.61#ibcon#wrote, iclass 23, count 0 2006.286.04:00:32.61#ibcon#about to read 3, iclass 23, count 0 2006.286.04:00:32.65#ibcon#read 3, iclass 23, count 0 2006.286.04:00:32.65#ibcon#about to read 4, iclass 23, count 0 2006.286.04:00:32.65#ibcon#read 4, iclass 23, count 0 2006.286.04:00:32.65#ibcon#about to read 5, iclass 23, count 0 2006.286.04:00:32.65#ibcon#read 5, iclass 23, count 0 2006.286.04:00:32.65#ibcon#about to read 6, iclass 23, count 0 2006.286.04:00:32.65#ibcon#read 6, iclass 23, count 0 2006.286.04:00:32.65#ibcon#end of sib2, iclass 23, count 0 2006.286.04:00:32.65#ibcon#*after write, iclass 23, count 0 2006.286.04:00:32.65#ibcon#*before return 0, iclass 23, count 0 2006.286.04:00:32.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:00:32.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:00:32.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:00:32.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:00:32.65$vck44/vb=8,4 2006.286.04:00:32.65#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.04:00:32.65#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.04:00:32.65#ibcon#ireg 11 cls_cnt 2 2006.286.04:00:32.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:00:32.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:00:32.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:00:32.71#ibcon#enter wrdev, iclass 25, count 2 2006.286.04:00:32.71#ibcon#first serial, iclass 25, count 2 2006.286.04:00:32.71#ibcon#enter sib2, iclass 25, count 2 2006.286.04:00:32.71#ibcon#flushed, iclass 25, count 2 2006.286.04:00:32.71#ibcon#about to write, iclass 25, count 2 2006.286.04:00:32.71#ibcon#wrote, iclass 25, count 2 2006.286.04:00:32.71#ibcon#about to read 3, iclass 25, count 2 2006.286.04:00:32.73#ibcon#read 3, iclass 25, count 2 2006.286.04:00:32.73#ibcon#about to read 4, iclass 25, count 2 2006.286.04:00:32.73#ibcon#read 4, iclass 25, count 2 2006.286.04:00:32.73#ibcon#about to read 5, iclass 25, count 2 2006.286.04:00:32.73#ibcon#read 5, iclass 25, count 2 2006.286.04:00:32.73#ibcon#about to read 6, iclass 25, count 2 2006.286.04:00:32.73#ibcon#read 6, iclass 25, count 2 2006.286.04:00:32.73#ibcon#end of sib2, iclass 25, count 2 2006.286.04:00:32.73#ibcon#*mode == 0, iclass 25, count 2 2006.286.04:00:32.73#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.04:00:32.73#ibcon#[27=AT08-04\r\n] 2006.286.04:00:32.73#ibcon#*before write, iclass 25, count 2 2006.286.04:00:32.73#ibcon#enter sib2, iclass 25, count 2 2006.286.04:00:32.73#ibcon#flushed, iclass 25, count 2 2006.286.04:00:32.73#ibcon#about to write, iclass 25, count 2 2006.286.04:00:32.73#ibcon#wrote, iclass 25, count 2 2006.286.04:00:32.73#ibcon#about to read 3, iclass 25, count 2 2006.286.04:00:32.76#ibcon#read 3, iclass 25, count 2 2006.286.04:00:32.76#ibcon#about to read 4, iclass 25, count 2 2006.286.04:00:32.76#ibcon#read 4, iclass 25, count 2 2006.286.04:00:32.76#ibcon#about to read 5, iclass 25, count 2 2006.286.04:00:32.76#ibcon#read 5, iclass 25, count 2 2006.286.04:00:32.76#ibcon#about to read 6, iclass 25, count 2 2006.286.04:00:32.76#ibcon#read 6, iclass 25, count 2 2006.286.04:00:32.76#ibcon#end of sib2, iclass 25, count 2 2006.286.04:00:32.76#ibcon#*after write, iclass 25, count 2 2006.286.04:00:32.76#ibcon#*before return 0, iclass 25, count 2 2006.286.04:00:32.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:00:32.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:00:32.76#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.04:00:32.76#ibcon#ireg 7 cls_cnt 0 2006.286.04:00:32.76#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:00:32.88#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:00:32.88#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:00:32.88#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:00:32.88#ibcon#first serial, iclass 25, count 0 2006.286.04:00:32.88#ibcon#enter sib2, iclass 25, count 0 2006.286.04:00:32.88#ibcon#flushed, iclass 25, count 0 2006.286.04:00:32.88#ibcon#about to write, iclass 25, count 0 2006.286.04:00:32.88#ibcon#wrote, iclass 25, count 0 2006.286.04:00:32.88#ibcon#about to read 3, iclass 25, count 0 2006.286.04:00:32.90#ibcon#read 3, iclass 25, count 0 2006.286.04:00:32.90#ibcon#about to read 4, iclass 25, count 0 2006.286.04:00:32.90#ibcon#read 4, iclass 25, count 0 2006.286.04:00:32.90#ibcon#about to read 5, iclass 25, count 0 2006.286.04:00:32.90#ibcon#read 5, iclass 25, count 0 2006.286.04:00:32.90#ibcon#about to read 6, iclass 25, count 0 2006.286.04:00:32.90#ibcon#read 6, iclass 25, count 0 2006.286.04:00:32.90#ibcon#end of sib2, iclass 25, count 0 2006.286.04:00:32.90#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:00:32.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:00:32.90#ibcon#[27=USB\r\n] 2006.286.04:00:32.90#ibcon#*before write, iclass 25, count 0 2006.286.04:00:32.90#ibcon#enter sib2, iclass 25, count 0 2006.286.04:00:32.90#ibcon#flushed, iclass 25, count 0 2006.286.04:00:32.90#ibcon#about to write, iclass 25, count 0 2006.286.04:00:32.90#ibcon#wrote, iclass 25, count 0 2006.286.04:00:32.90#ibcon#about to read 3, iclass 25, count 0 2006.286.04:00:32.93#ibcon#read 3, iclass 25, count 0 2006.286.04:00:32.93#ibcon#about to read 4, iclass 25, count 0 2006.286.04:00:32.93#ibcon#read 4, iclass 25, count 0 2006.286.04:00:32.93#ibcon#about to read 5, iclass 25, count 0 2006.286.04:00:32.93#ibcon#read 5, iclass 25, count 0 2006.286.04:00:32.93#ibcon#about to read 6, iclass 25, count 0 2006.286.04:00:32.93#ibcon#read 6, iclass 25, count 0 2006.286.04:00:32.93#ibcon#end of sib2, iclass 25, count 0 2006.286.04:00:32.93#ibcon#*after write, iclass 25, count 0 2006.286.04:00:32.93#ibcon#*before return 0, iclass 25, count 0 2006.286.04:00:32.93#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:00:32.93#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:00:32.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:00:32.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:00:32.93$vck44/vabw=wide 2006.286.04:00:32.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.04:00:32.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.04:00:32.93#ibcon#ireg 8 cls_cnt 0 2006.286.04:00:32.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:00:32.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:00:32.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:00:32.93#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:00:32.93#ibcon#first serial, iclass 27, count 0 2006.286.04:00:32.93#ibcon#enter sib2, iclass 27, count 0 2006.286.04:00:32.93#ibcon#flushed, iclass 27, count 0 2006.286.04:00:32.93#ibcon#about to write, iclass 27, count 0 2006.286.04:00:32.93#ibcon#wrote, iclass 27, count 0 2006.286.04:00:32.93#ibcon#about to read 3, iclass 27, count 0 2006.286.04:00:32.95#ibcon#read 3, iclass 27, count 0 2006.286.04:00:32.95#ibcon#about to read 4, iclass 27, count 0 2006.286.04:00:32.95#ibcon#read 4, iclass 27, count 0 2006.286.04:00:32.95#ibcon#about to read 5, iclass 27, count 0 2006.286.04:00:32.95#ibcon#read 5, iclass 27, count 0 2006.286.04:00:32.95#ibcon#about to read 6, iclass 27, count 0 2006.286.04:00:32.95#ibcon#read 6, iclass 27, count 0 2006.286.04:00:32.95#ibcon#end of sib2, iclass 27, count 0 2006.286.04:00:32.95#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:00:32.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:00:32.95#ibcon#[25=BW32\r\n] 2006.286.04:00:32.95#ibcon#*before write, iclass 27, count 0 2006.286.04:00:32.95#ibcon#enter sib2, iclass 27, count 0 2006.286.04:00:32.95#ibcon#flushed, iclass 27, count 0 2006.286.04:00:32.95#ibcon#about to write, iclass 27, count 0 2006.286.04:00:32.95#ibcon#wrote, iclass 27, count 0 2006.286.04:00:32.95#ibcon#about to read 3, iclass 27, count 0 2006.286.04:00:32.98#ibcon#read 3, iclass 27, count 0 2006.286.04:00:32.98#ibcon#about to read 4, iclass 27, count 0 2006.286.04:00:32.98#ibcon#read 4, iclass 27, count 0 2006.286.04:00:32.98#ibcon#about to read 5, iclass 27, count 0 2006.286.04:00:32.98#ibcon#read 5, iclass 27, count 0 2006.286.04:00:32.98#ibcon#about to read 6, iclass 27, count 0 2006.286.04:00:32.98#ibcon#read 6, iclass 27, count 0 2006.286.04:00:32.98#ibcon#end of sib2, iclass 27, count 0 2006.286.04:00:32.98#ibcon#*after write, iclass 27, count 0 2006.286.04:00:32.98#ibcon#*before return 0, iclass 27, count 0 2006.286.04:00:32.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:00:32.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:00:32.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:00:32.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:00:32.98$vck44/vbbw=wide 2006.286.04:00:32.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.04:00:32.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.04:00:32.98#ibcon#ireg 8 cls_cnt 0 2006.286.04:00:32.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:00:33.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:00:33.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:00:33.05#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:00:33.05#ibcon#first serial, iclass 29, count 0 2006.286.04:00:33.05#ibcon#enter sib2, iclass 29, count 0 2006.286.04:00:33.05#ibcon#flushed, iclass 29, count 0 2006.286.04:00:33.05#ibcon#about to write, iclass 29, count 0 2006.286.04:00:33.05#ibcon#wrote, iclass 29, count 0 2006.286.04:00:33.05#ibcon#about to read 3, iclass 29, count 0 2006.286.04:00:33.07#ibcon#read 3, iclass 29, count 0 2006.286.04:00:33.07#ibcon#about to read 4, iclass 29, count 0 2006.286.04:00:33.07#ibcon#read 4, iclass 29, count 0 2006.286.04:00:33.07#ibcon#about to read 5, iclass 29, count 0 2006.286.04:00:33.07#ibcon#read 5, iclass 29, count 0 2006.286.04:00:33.07#ibcon#about to read 6, iclass 29, count 0 2006.286.04:00:33.07#ibcon#read 6, iclass 29, count 0 2006.286.04:00:33.07#ibcon#end of sib2, iclass 29, count 0 2006.286.04:00:33.07#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:00:33.07#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:00:33.07#ibcon#[27=BW32\r\n] 2006.286.04:00:33.07#ibcon#*before write, iclass 29, count 0 2006.286.04:00:33.07#ibcon#enter sib2, iclass 29, count 0 2006.286.04:00:33.07#ibcon#flushed, iclass 29, count 0 2006.286.04:00:33.07#ibcon#about to write, iclass 29, count 0 2006.286.04:00:33.07#ibcon#wrote, iclass 29, count 0 2006.286.04:00:33.07#ibcon#about to read 3, iclass 29, count 0 2006.286.04:00:33.10#ibcon#read 3, iclass 29, count 0 2006.286.04:00:33.10#ibcon#about to read 4, iclass 29, count 0 2006.286.04:00:33.10#ibcon#read 4, iclass 29, count 0 2006.286.04:00:33.10#ibcon#about to read 5, iclass 29, count 0 2006.286.04:00:33.10#ibcon#read 5, iclass 29, count 0 2006.286.04:00:33.10#ibcon#about to read 6, iclass 29, count 0 2006.286.04:00:33.10#ibcon#read 6, iclass 29, count 0 2006.286.04:00:33.10#ibcon#end of sib2, iclass 29, count 0 2006.286.04:00:33.10#ibcon#*after write, iclass 29, count 0 2006.286.04:00:33.10#ibcon#*before return 0, iclass 29, count 0 2006.286.04:00:33.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:00:33.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:00:33.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:00:33.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:00:33.10$setupk4/ifdk4 2006.286.04:00:33.10$ifdk4/lo= 2006.286.04:00:33.10$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:00:33.10$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:00:33.27$ifdk4/patch= 2006.286.04:00:33.27$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:00:33.27$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:00:33.27$setupk4/!*+20s 2006.286.04:00:36.16#abcon#<5=/04 3.4 8.0 21.88 761014.9\r\n> 2006.286.04:00:36.18#abcon#{5=INTERFACE CLEAR} 2006.286.04:00:36.24#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:00:46.33#abcon#<5=/04 3.4 7.9 21.87 761014.9\r\n> 2006.286.04:00:46.35#abcon#{5=INTERFACE CLEAR} 2006.286.04:00:46.41#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:00:46.94$setupk4/"tpicd 2006.286.04:00:46.94$setupk4/echo=off 2006.286.04:00:46.94$setupk4/xlog=off 2006.286.04:00:46.94:!2006.286.04:04:43 2006.286.04:00:53.14#trakl#Source acquired 2006.286.04:00:53.14#flagr#flagr/antenna,acquired 2006.286.04:04:43.00:preob 2006.286.04:04:43.14/onsource/TRACKING 2006.286.04:04:43.14:!2006.286.04:04:53 2006.286.04:04:53.00:"tape 2006.286.04:04:53.00:"st=record 2006.286.04:04:53.00:data_valid=on 2006.286.04:04:53.00:midob 2006.286.04:04:53.14/onsource/TRACKING 2006.286.04:04:53.14/wx/21.88,1014.9,77 2006.286.04:04:53.36/cable/+6.4954E-03 2006.286.04:04:54.45/va/01,07,usb,yes,32,34 2006.286.04:04:54.45/va/02,06,usb,yes,32,32 2006.286.04:04:54.45/va/03,07,usb,yes,31,33 2006.286.04:04:54.45/va/04,06,usb,yes,33,34 2006.286.04:04:54.45/va/05,03,usb,yes,32,33 2006.286.04:04:54.45/va/06,04,usb,yes,29,29 2006.286.04:04:54.45/va/07,04,usb,yes,30,30 2006.286.04:04:54.45/va/08,03,usb,yes,30,37 2006.286.04:04:54.68/valo/01,524.99,yes,locked 2006.286.04:04:54.68/valo/02,534.99,yes,locked 2006.286.04:04:54.68/valo/03,564.99,yes,locked 2006.286.04:04:54.68/valo/04,624.99,yes,locked 2006.286.04:04:54.68/valo/05,734.99,yes,locked 2006.286.04:04:54.68/valo/06,814.99,yes,locked 2006.286.04:04:54.68/valo/07,864.99,yes,locked 2006.286.04:04:54.68/valo/08,884.99,yes,locked 2006.286.04:04:55.77/vb/01,04,usb,yes,30,28 2006.286.04:04:55.77/vb/02,05,usb,yes,28,28 2006.286.04:04:55.77/vb/03,04,usb,yes,29,32 2006.286.04:04:55.77/vb/04,05,usb,yes,30,29 2006.286.04:04:55.77/vb/05,04,usb,yes,26,29 2006.286.04:04:55.77/vb/06,03,usb,yes,38,34 2006.286.04:04:55.77/vb/07,04,usb,yes,30,30 2006.286.04:04:55.77/vb/08,04,usb,yes,28,31 2006.286.04:04:56.01/vblo/01,629.99,yes,locked 2006.286.04:04:56.01/vblo/02,634.99,yes,locked 2006.286.04:04:56.01/vblo/03,649.99,yes,locked 2006.286.04:04:56.01/vblo/04,679.99,yes,locked 2006.286.04:04:56.01/vblo/05,709.99,yes,locked 2006.286.04:04:56.01/vblo/06,719.99,yes,locked 2006.286.04:04:56.01/vblo/07,734.99,yes,locked 2006.286.04:04:56.01/vblo/08,744.99,yes,locked 2006.286.04:04:56.16/vabw/8 2006.286.04:04:56.31/vbbw/8 2006.286.04:04:56.40/xfe/off,on,12.2 2006.286.04:04:56.78/ifatt/23,28,28,28 2006.286.04:04:57.07/fmout-gps/S +2.50E-07 2006.286.04:04:57.09:!2006.286.04:08:53 2006.286.04:08:53.01:data_valid=off 2006.286.04:08:53.01:"et 2006.286.04:08:53.01:!+3s 2006.286.04:08:56.02:"tape 2006.286.04:08:56.02:postob 2006.286.04:08:56.20/cable/+6.4961E-03 2006.286.04:08:56.20/wx/21.85,1014.9,76 2006.286.04:08:57.07/fmout-gps/S +2.56E-07 2006.286.04:08:57.07:scan_name=286-0410,jd0610,350 2006.286.04:08:57.07:source=2201+315,220314.98,314538.3,2000.0,cw 2006.286.04:08:57.14#flagr#flagr/antenna,new-source 2006.286.04:08:58.14:checkk5 2006.286.04:08:58.63/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:08:58.99/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:08:59.43/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:08:59.84/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:09:00.28/chk_obsdata//k5ts1/T2860404??a.dat file size is correct (nominal:960MB, actual:956MB). 2006.286.04:09:00.66/chk_obsdata//k5ts2/T2860404??b.dat file size is correct (nominal:960MB, actual:956MB). 2006.286.04:09:01.04/chk_obsdata//k5ts3/T2860404??c.dat file size is correct (nominal:960MB, actual:956MB). 2006.286.04:09:01.60/chk_obsdata//k5ts4/T2860404??d.dat file size is correct (nominal:960MB, actual:956MB). 2006.286.04:09:02.56/k5log//k5ts1_log_newline 2006.286.04:09:03.51/k5log//k5ts2_log_newline 2006.286.04:09:04.54/k5log//k5ts3_log_newline 2006.286.04:09:05.59/k5log//k5ts4_log_newline 2006.286.04:09:05.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:09:05.61:setupk4=1 2006.286.04:09:05.61$setupk4/echo=on 2006.286.04:09:05.61$setupk4/pcalon 2006.286.04:09:05.61$pcalon/"no phase cal control is implemented here 2006.286.04:09:05.61$setupk4/"tpicd=stop 2006.286.04:09:05.61$setupk4/"rec=synch_on 2006.286.04:09:05.61$setupk4/"rec_mode=128 2006.286.04:09:05.61$setupk4/!* 2006.286.04:09:05.61$setupk4/recpk4 2006.286.04:09:05.61$recpk4/recpatch= 2006.286.04:09:05.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:09:05.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:09:05.62$setupk4/vck44 2006.286.04:09:05.62$vck44/valo=1,524.99 2006.286.04:09:05.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:09:05.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:09:05.62#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:05.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:09:05.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:09:05.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:09:05.62#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:09:05.62#ibcon#first serial, iclass 22, count 0 2006.286.04:09:05.62#ibcon#enter sib2, iclass 22, count 0 2006.286.04:09:05.62#ibcon#flushed, iclass 22, count 0 2006.286.04:09:05.62#ibcon#about to write, iclass 22, count 0 2006.286.04:09:05.62#ibcon#wrote, iclass 22, count 0 2006.286.04:09:05.62#ibcon#about to read 3, iclass 22, count 0 2006.286.04:09:05.64#ibcon#read 3, iclass 22, count 0 2006.286.04:09:05.64#ibcon#about to read 4, iclass 22, count 0 2006.286.04:09:05.64#ibcon#read 4, iclass 22, count 0 2006.286.04:09:05.64#ibcon#about to read 5, iclass 22, count 0 2006.286.04:09:05.64#ibcon#read 5, iclass 22, count 0 2006.286.04:09:05.64#ibcon#about to read 6, iclass 22, count 0 2006.286.04:09:05.64#ibcon#read 6, iclass 22, count 0 2006.286.04:09:05.64#ibcon#end of sib2, iclass 22, count 0 2006.286.04:09:05.64#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:09:05.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:09:05.64#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:09:05.64#ibcon#*before write, iclass 22, count 0 2006.286.04:09:05.64#ibcon#enter sib2, iclass 22, count 0 2006.286.04:09:05.64#ibcon#flushed, iclass 22, count 0 2006.286.04:09:05.64#ibcon#about to write, iclass 22, count 0 2006.286.04:09:05.64#ibcon#wrote, iclass 22, count 0 2006.286.04:09:05.64#ibcon#about to read 3, iclass 22, count 0 2006.286.04:09:05.69#ibcon#read 3, iclass 22, count 0 2006.286.04:09:05.69#ibcon#about to read 4, iclass 22, count 0 2006.286.04:09:05.69#ibcon#read 4, iclass 22, count 0 2006.286.04:09:05.69#ibcon#about to read 5, iclass 22, count 0 2006.286.04:09:05.69#ibcon#read 5, iclass 22, count 0 2006.286.04:09:05.69#ibcon#about to read 6, iclass 22, count 0 2006.286.04:09:05.69#ibcon#read 6, iclass 22, count 0 2006.286.04:09:05.69#ibcon#end of sib2, iclass 22, count 0 2006.286.04:09:05.69#ibcon#*after write, iclass 22, count 0 2006.286.04:09:05.69#ibcon#*before return 0, iclass 22, count 0 2006.286.04:09:05.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:09:05.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:09:05.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:09:05.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:09:05.69$vck44/va=1,7 2006.286.04:09:05.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.04:09:05.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.04:09:05.69#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:05.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:09:05.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:09:05.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:09:05.69#ibcon#enter wrdev, iclass 24, count 2 2006.286.04:09:05.69#ibcon#first serial, iclass 24, count 2 2006.286.04:09:05.69#ibcon#enter sib2, iclass 24, count 2 2006.286.04:09:05.69#ibcon#flushed, iclass 24, count 2 2006.286.04:09:05.69#ibcon#about to write, iclass 24, count 2 2006.286.04:09:05.69#ibcon#wrote, iclass 24, count 2 2006.286.04:09:05.69#ibcon#about to read 3, iclass 24, count 2 2006.286.04:09:05.71#ibcon#read 3, iclass 24, count 2 2006.286.04:09:05.71#ibcon#about to read 4, iclass 24, count 2 2006.286.04:09:05.71#ibcon#read 4, iclass 24, count 2 2006.286.04:09:05.71#ibcon#about to read 5, iclass 24, count 2 2006.286.04:09:05.71#ibcon#read 5, iclass 24, count 2 2006.286.04:09:05.71#ibcon#about to read 6, iclass 24, count 2 2006.286.04:09:05.71#ibcon#read 6, iclass 24, count 2 2006.286.04:09:05.71#ibcon#end of sib2, iclass 24, count 2 2006.286.04:09:05.71#ibcon#*mode == 0, iclass 24, count 2 2006.286.04:09:05.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.04:09:05.71#ibcon#[25=AT01-07\r\n] 2006.286.04:09:05.71#ibcon#*before write, iclass 24, count 2 2006.286.04:09:05.71#ibcon#enter sib2, iclass 24, count 2 2006.286.04:09:05.71#ibcon#flushed, iclass 24, count 2 2006.286.04:09:05.71#ibcon#about to write, iclass 24, count 2 2006.286.04:09:05.71#ibcon#wrote, iclass 24, count 2 2006.286.04:09:05.71#ibcon#about to read 3, iclass 24, count 2 2006.286.04:09:05.74#ibcon#read 3, iclass 24, count 2 2006.286.04:09:05.74#ibcon#about to read 4, iclass 24, count 2 2006.286.04:09:05.74#ibcon#read 4, iclass 24, count 2 2006.286.04:09:05.74#ibcon#about to read 5, iclass 24, count 2 2006.286.04:09:05.74#ibcon#read 5, iclass 24, count 2 2006.286.04:09:05.74#ibcon#about to read 6, iclass 24, count 2 2006.286.04:09:05.74#ibcon#read 6, iclass 24, count 2 2006.286.04:09:05.74#ibcon#end of sib2, iclass 24, count 2 2006.286.04:09:05.74#ibcon#*after write, iclass 24, count 2 2006.286.04:09:05.74#ibcon#*before return 0, iclass 24, count 2 2006.286.04:09:05.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:09:05.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:09:05.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.04:09:05.74#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:05.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:09:05.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:09:05.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:09:05.86#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:09:05.86#ibcon#first serial, iclass 24, count 0 2006.286.04:09:05.86#ibcon#enter sib2, iclass 24, count 0 2006.286.04:09:05.86#ibcon#flushed, iclass 24, count 0 2006.286.04:09:05.86#ibcon#about to write, iclass 24, count 0 2006.286.04:09:05.86#ibcon#wrote, iclass 24, count 0 2006.286.04:09:05.86#ibcon#about to read 3, iclass 24, count 0 2006.286.04:09:05.88#ibcon#read 3, iclass 24, count 0 2006.286.04:09:05.88#ibcon#about to read 4, iclass 24, count 0 2006.286.04:09:05.88#ibcon#read 4, iclass 24, count 0 2006.286.04:09:05.88#ibcon#about to read 5, iclass 24, count 0 2006.286.04:09:05.88#ibcon#read 5, iclass 24, count 0 2006.286.04:09:05.88#ibcon#about to read 6, iclass 24, count 0 2006.286.04:09:05.88#ibcon#read 6, iclass 24, count 0 2006.286.04:09:05.88#ibcon#end of sib2, iclass 24, count 0 2006.286.04:09:05.88#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:09:05.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:09:05.88#ibcon#[25=USB\r\n] 2006.286.04:09:05.88#ibcon#*before write, iclass 24, count 0 2006.286.04:09:05.88#ibcon#enter sib2, iclass 24, count 0 2006.286.04:09:05.88#ibcon#flushed, iclass 24, count 0 2006.286.04:09:05.88#ibcon#about to write, iclass 24, count 0 2006.286.04:09:05.88#ibcon#wrote, iclass 24, count 0 2006.286.04:09:05.88#ibcon#about to read 3, iclass 24, count 0 2006.286.04:09:05.91#ibcon#read 3, iclass 24, count 0 2006.286.04:09:05.91#ibcon#about to read 4, iclass 24, count 0 2006.286.04:09:05.91#ibcon#read 4, iclass 24, count 0 2006.286.04:09:05.91#ibcon#about to read 5, iclass 24, count 0 2006.286.04:09:05.91#ibcon#read 5, iclass 24, count 0 2006.286.04:09:05.91#ibcon#about to read 6, iclass 24, count 0 2006.286.04:09:05.91#ibcon#read 6, iclass 24, count 0 2006.286.04:09:05.91#ibcon#end of sib2, iclass 24, count 0 2006.286.04:09:05.91#ibcon#*after write, iclass 24, count 0 2006.286.04:09:05.91#ibcon#*before return 0, iclass 24, count 0 2006.286.04:09:05.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:09:05.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:09:05.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:09:05.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:09:05.91$vck44/valo=2,534.99 2006.286.04:09:05.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.04:09:05.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.04:09:05.91#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:05.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:09:05.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:09:05.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:09:05.91#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:09:05.91#ibcon#first serial, iclass 26, count 0 2006.286.04:09:05.91#ibcon#enter sib2, iclass 26, count 0 2006.286.04:09:05.91#ibcon#flushed, iclass 26, count 0 2006.286.04:09:05.91#ibcon#about to write, iclass 26, count 0 2006.286.04:09:05.91#ibcon#wrote, iclass 26, count 0 2006.286.04:09:05.91#ibcon#about to read 3, iclass 26, count 0 2006.286.04:09:05.93#ibcon#read 3, iclass 26, count 0 2006.286.04:09:05.93#ibcon#about to read 4, iclass 26, count 0 2006.286.04:09:05.93#ibcon#read 4, iclass 26, count 0 2006.286.04:09:05.93#ibcon#about to read 5, iclass 26, count 0 2006.286.04:09:05.93#ibcon#read 5, iclass 26, count 0 2006.286.04:09:05.93#ibcon#about to read 6, iclass 26, count 0 2006.286.04:09:05.93#ibcon#read 6, iclass 26, count 0 2006.286.04:09:05.93#ibcon#end of sib2, iclass 26, count 0 2006.286.04:09:05.93#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:09:05.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:09:05.93#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:09:05.93#ibcon#*before write, iclass 26, count 0 2006.286.04:09:05.93#ibcon#enter sib2, iclass 26, count 0 2006.286.04:09:05.93#ibcon#flushed, iclass 26, count 0 2006.286.04:09:05.93#ibcon#about to write, iclass 26, count 0 2006.286.04:09:05.93#ibcon#wrote, iclass 26, count 0 2006.286.04:09:05.93#ibcon#about to read 3, iclass 26, count 0 2006.286.04:09:05.97#ibcon#read 3, iclass 26, count 0 2006.286.04:09:05.97#ibcon#about to read 4, iclass 26, count 0 2006.286.04:09:05.97#ibcon#read 4, iclass 26, count 0 2006.286.04:09:05.97#ibcon#about to read 5, iclass 26, count 0 2006.286.04:09:05.97#ibcon#read 5, iclass 26, count 0 2006.286.04:09:05.97#ibcon#about to read 6, iclass 26, count 0 2006.286.04:09:05.97#ibcon#read 6, iclass 26, count 0 2006.286.04:09:05.97#ibcon#end of sib2, iclass 26, count 0 2006.286.04:09:05.97#ibcon#*after write, iclass 26, count 0 2006.286.04:09:05.97#ibcon#*before return 0, iclass 26, count 0 2006.286.04:09:05.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:09:05.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:09:05.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:09:05.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:09:05.97$vck44/va=2,6 2006.286.04:09:05.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.04:09:05.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.04:09:05.97#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:05.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:09:06.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:09:06.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:09:06.03#ibcon#enter wrdev, iclass 28, count 2 2006.286.04:09:06.03#ibcon#first serial, iclass 28, count 2 2006.286.04:09:06.03#ibcon#enter sib2, iclass 28, count 2 2006.286.04:09:06.03#ibcon#flushed, iclass 28, count 2 2006.286.04:09:06.03#ibcon#about to write, iclass 28, count 2 2006.286.04:09:06.03#ibcon#wrote, iclass 28, count 2 2006.286.04:09:06.03#ibcon#about to read 3, iclass 28, count 2 2006.286.04:09:06.05#ibcon#read 3, iclass 28, count 2 2006.286.04:09:06.05#ibcon#about to read 4, iclass 28, count 2 2006.286.04:09:06.05#ibcon#read 4, iclass 28, count 2 2006.286.04:09:06.05#ibcon#about to read 5, iclass 28, count 2 2006.286.04:09:06.05#ibcon#read 5, iclass 28, count 2 2006.286.04:09:06.05#ibcon#about to read 6, iclass 28, count 2 2006.286.04:09:06.05#ibcon#read 6, iclass 28, count 2 2006.286.04:09:06.05#ibcon#end of sib2, iclass 28, count 2 2006.286.04:09:06.05#ibcon#*mode == 0, iclass 28, count 2 2006.286.04:09:06.05#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.04:09:06.05#ibcon#[25=AT02-06\r\n] 2006.286.04:09:06.05#ibcon#*before write, iclass 28, count 2 2006.286.04:09:06.05#ibcon#enter sib2, iclass 28, count 2 2006.286.04:09:06.05#ibcon#flushed, iclass 28, count 2 2006.286.04:09:06.05#ibcon#about to write, iclass 28, count 2 2006.286.04:09:06.05#ibcon#wrote, iclass 28, count 2 2006.286.04:09:06.05#ibcon#about to read 3, iclass 28, count 2 2006.286.04:09:06.08#ibcon#read 3, iclass 28, count 2 2006.286.04:09:06.08#ibcon#about to read 4, iclass 28, count 2 2006.286.04:09:06.08#ibcon#read 4, iclass 28, count 2 2006.286.04:09:06.08#ibcon#about to read 5, iclass 28, count 2 2006.286.04:09:06.08#ibcon#read 5, iclass 28, count 2 2006.286.04:09:06.08#ibcon#about to read 6, iclass 28, count 2 2006.286.04:09:06.08#ibcon#read 6, iclass 28, count 2 2006.286.04:09:06.08#ibcon#end of sib2, iclass 28, count 2 2006.286.04:09:06.08#ibcon#*after write, iclass 28, count 2 2006.286.04:09:06.08#ibcon#*before return 0, iclass 28, count 2 2006.286.04:09:06.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:09:06.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:09:06.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.04:09:06.08#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:06.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:09:06.20#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:09:06.20#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:09:06.20#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:09:06.20#ibcon#first serial, iclass 28, count 0 2006.286.04:09:06.20#ibcon#enter sib2, iclass 28, count 0 2006.286.04:09:06.20#ibcon#flushed, iclass 28, count 0 2006.286.04:09:06.20#ibcon#about to write, iclass 28, count 0 2006.286.04:09:06.20#ibcon#wrote, iclass 28, count 0 2006.286.04:09:06.20#ibcon#about to read 3, iclass 28, count 0 2006.286.04:09:06.22#ibcon#read 3, iclass 28, count 0 2006.286.04:09:06.22#ibcon#about to read 4, iclass 28, count 0 2006.286.04:09:06.22#ibcon#read 4, iclass 28, count 0 2006.286.04:09:06.22#ibcon#about to read 5, iclass 28, count 0 2006.286.04:09:06.22#ibcon#read 5, iclass 28, count 0 2006.286.04:09:06.22#ibcon#about to read 6, iclass 28, count 0 2006.286.04:09:06.22#ibcon#read 6, iclass 28, count 0 2006.286.04:09:06.22#ibcon#end of sib2, iclass 28, count 0 2006.286.04:09:06.22#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:09:06.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:09:06.22#ibcon#[25=USB\r\n] 2006.286.04:09:06.22#ibcon#*before write, iclass 28, count 0 2006.286.04:09:06.22#ibcon#enter sib2, iclass 28, count 0 2006.286.04:09:06.22#ibcon#flushed, iclass 28, count 0 2006.286.04:09:06.22#ibcon#about to write, iclass 28, count 0 2006.286.04:09:06.22#ibcon#wrote, iclass 28, count 0 2006.286.04:09:06.22#ibcon#about to read 3, iclass 28, count 0 2006.286.04:09:06.25#ibcon#read 3, iclass 28, count 0 2006.286.04:09:06.25#ibcon#about to read 4, iclass 28, count 0 2006.286.04:09:06.25#ibcon#read 4, iclass 28, count 0 2006.286.04:09:06.25#ibcon#about to read 5, iclass 28, count 0 2006.286.04:09:06.25#ibcon#read 5, iclass 28, count 0 2006.286.04:09:06.25#ibcon#about to read 6, iclass 28, count 0 2006.286.04:09:06.25#ibcon#read 6, iclass 28, count 0 2006.286.04:09:06.25#ibcon#end of sib2, iclass 28, count 0 2006.286.04:09:06.25#ibcon#*after write, iclass 28, count 0 2006.286.04:09:06.25#ibcon#*before return 0, iclass 28, count 0 2006.286.04:09:06.25#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:09:06.25#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:09:06.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:09:06.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:09:06.25$vck44/valo=3,564.99 2006.286.04:09:06.25#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:09:06.25#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:09:06.25#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:06.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:09:06.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:09:06.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:09:06.25#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:09:06.25#ibcon#first serial, iclass 30, count 0 2006.286.04:09:06.25#ibcon#enter sib2, iclass 30, count 0 2006.286.04:09:06.25#ibcon#flushed, iclass 30, count 0 2006.286.04:09:06.25#ibcon#about to write, iclass 30, count 0 2006.286.04:09:06.25#ibcon#wrote, iclass 30, count 0 2006.286.04:09:06.25#ibcon#about to read 3, iclass 30, count 0 2006.286.04:09:06.68#ibcon#read 3, iclass 30, count 0 2006.286.04:09:06.68#ibcon#about to read 4, iclass 30, count 0 2006.286.04:09:06.68#ibcon#read 4, iclass 30, count 0 2006.286.04:09:06.68#ibcon#about to read 5, iclass 30, count 0 2006.286.04:09:06.68#ibcon#read 5, iclass 30, count 0 2006.286.04:09:06.68#ibcon#about to read 6, iclass 30, count 0 2006.286.04:09:06.68#ibcon#read 6, iclass 30, count 0 2006.286.04:09:06.68#ibcon#end of sib2, iclass 30, count 0 2006.286.04:09:06.68#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:09:06.68#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:09:06.68#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:09:06.68#ibcon#*before write, iclass 30, count 0 2006.286.04:09:06.68#ibcon#enter sib2, iclass 30, count 0 2006.286.04:09:06.68#ibcon#flushed, iclass 30, count 0 2006.286.04:09:06.68#ibcon#about to write, iclass 30, count 0 2006.286.04:09:06.68#ibcon#wrote, iclass 30, count 0 2006.286.04:09:06.68#ibcon#about to read 3, iclass 30, count 0 2006.286.04:09:06.73#ibcon#read 3, iclass 30, count 0 2006.286.04:09:06.73#ibcon#about to read 4, iclass 30, count 0 2006.286.04:09:06.73#ibcon#read 4, iclass 30, count 0 2006.286.04:09:06.73#ibcon#about to read 5, iclass 30, count 0 2006.286.04:09:06.73#ibcon#read 5, iclass 30, count 0 2006.286.04:09:06.73#ibcon#about to read 6, iclass 30, count 0 2006.286.04:09:06.73#ibcon#read 6, iclass 30, count 0 2006.286.04:09:06.73#ibcon#end of sib2, iclass 30, count 0 2006.286.04:09:06.73#ibcon#*after write, iclass 30, count 0 2006.286.04:09:06.73#ibcon#*before return 0, iclass 30, count 0 2006.286.04:09:06.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:09:06.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:09:06.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:09:06.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:09:06.73$vck44/va=3,7 2006.286.04:09:06.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.04:09:06.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.04:09:06.73#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:06.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:09:06.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:09:06.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:09:06.73#ibcon#enter wrdev, iclass 32, count 2 2006.286.04:09:06.73#ibcon#first serial, iclass 32, count 2 2006.286.04:09:06.73#ibcon#enter sib2, iclass 32, count 2 2006.286.04:09:06.73#ibcon#flushed, iclass 32, count 2 2006.286.04:09:06.73#ibcon#about to write, iclass 32, count 2 2006.286.04:09:06.73#ibcon#wrote, iclass 32, count 2 2006.286.04:09:06.73#ibcon#about to read 3, iclass 32, count 2 2006.286.04:09:06.75#ibcon#read 3, iclass 32, count 2 2006.286.04:09:06.75#ibcon#about to read 4, iclass 32, count 2 2006.286.04:09:06.75#ibcon#read 4, iclass 32, count 2 2006.286.04:09:06.75#ibcon#about to read 5, iclass 32, count 2 2006.286.04:09:06.75#ibcon#read 5, iclass 32, count 2 2006.286.04:09:06.75#ibcon#about to read 6, iclass 32, count 2 2006.286.04:09:06.75#ibcon#read 6, iclass 32, count 2 2006.286.04:09:06.75#ibcon#end of sib2, iclass 32, count 2 2006.286.04:09:06.75#ibcon#*mode == 0, iclass 32, count 2 2006.286.04:09:06.75#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.04:09:06.75#ibcon#[25=AT03-07\r\n] 2006.286.04:09:06.75#ibcon#*before write, iclass 32, count 2 2006.286.04:09:06.75#ibcon#enter sib2, iclass 32, count 2 2006.286.04:09:06.75#ibcon#flushed, iclass 32, count 2 2006.286.04:09:06.75#ibcon#about to write, iclass 32, count 2 2006.286.04:09:06.75#ibcon#wrote, iclass 32, count 2 2006.286.04:09:06.75#ibcon#about to read 3, iclass 32, count 2 2006.286.04:09:06.78#ibcon#read 3, iclass 32, count 2 2006.286.04:09:06.78#ibcon#about to read 4, iclass 32, count 2 2006.286.04:09:06.78#ibcon#read 4, iclass 32, count 2 2006.286.04:09:06.78#ibcon#about to read 5, iclass 32, count 2 2006.286.04:09:06.78#ibcon#read 5, iclass 32, count 2 2006.286.04:09:06.78#ibcon#about to read 6, iclass 32, count 2 2006.286.04:09:06.78#ibcon#read 6, iclass 32, count 2 2006.286.04:09:06.78#ibcon#end of sib2, iclass 32, count 2 2006.286.04:09:06.78#ibcon#*after write, iclass 32, count 2 2006.286.04:09:06.78#ibcon#*before return 0, iclass 32, count 2 2006.286.04:09:06.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:09:06.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:09:06.78#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.04:09:06.78#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:06.78#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:09:06.90#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:09:06.90#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:09:06.90#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:09:06.90#ibcon#first serial, iclass 32, count 0 2006.286.04:09:06.90#ibcon#enter sib2, iclass 32, count 0 2006.286.04:09:06.90#ibcon#flushed, iclass 32, count 0 2006.286.04:09:06.90#ibcon#about to write, iclass 32, count 0 2006.286.04:09:06.90#ibcon#wrote, iclass 32, count 0 2006.286.04:09:06.90#ibcon#about to read 3, iclass 32, count 0 2006.286.04:09:06.92#ibcon#read 3, iclass 32, count 0 2006.286.04:09:06.92#ibcon#about to read 4, iclass 32, count 0 2006.286.04:09:06.92#ibcon#read 4, iclass 32, count 0 2006.286.04:09:06.92#ibcon#about to read 5, iclass 32, count 0 2006.286.04:09:06.92#ibcon#read 5, iclass 32, count 0 2006.286.04:09:06.92#ibcon#about to read 6, iclass 32, count 0 2006.286.04:09:06.92#ibcon#read 6, iclass 32, count 0 2006.286.04:09:06.92#ibcon#end of sib2, iclass 32, count 0 2006.286.04:09:06.92#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:09:06.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:09:06.92#ibcon#[25=USB\r\n] 2006.286.04:09:06.92#ibcon#*before write, iclass 32, count 0 2006.286.04:09:06.92#ibcon#enter sib2, iclass 32, count 0 2006.286.04:09:06.92#ibcon#flushed, iclass 32, count 0 2006.286.04:09:06.92#ibcon#about to write, iclass 32, count 0 2006.286.04:09:06.92#ibcon#wrote, iclass 32, count 0 2006.286.04:09:06.92#ibcon#about to read 3, iclass 32, count 0 2006.286.04:09:06.95#ibcon#read 3, iclass 32, count 0 2006.286.04:09:06.95#ibcon#about to read 4, iclass 32, count 0 2006.286.04:09:06.95#ibcon#read 4, iclass 32, count 0 2006.286.04:09:06.95#ibcon#about to read 5, iclass 32, count 0 2006.286.04:09:06.95#ibcon#read 5, iclass 32, count 0 2006.286.04:09:06.95#ibcon#about to read 6, iclass 32, count 0 2006.286.04:09:06.95#ibcon#read 6, iclass 32, count 0 2006.286.04:09:06.95#ibcon#end of sib2, iclass 32, count 0 2006.286.04:09:06.95#ibcon#*after write, iclass 32, count 0 2006.286.04:09:06.95#ibcon#*before return 0, iclass 32, count 0 2006.286.04:09:06.95#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:09:06.95#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:09:06.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:09:06.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:09:06.95$vck44/valo=4,624.99 2006.286.04:09:06.95#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.04:09:06.95#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.04:09:06.95#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:06.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:09:06.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:09:06.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:09:06.95#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:09:06.95#ibcon#first serial, iclass 34, count 0 2006.286.04:09:06.95#ibcon#enter sib2, iclass 34, count 0 2006.286.04:09:06.95#ibcon#flushed, iclass 34, count 0 2006.286.04:09:06.95#ibcon#about to write, iclass 34, count 0 2006.286.04:09:06.95#ibcon#wrote, iclass 34, count 0 2006.286.04:09:06.95#ibcon#about to read 3, iclass 34, count 0 2006.286.04:09:06.97#ibcon#read 3, iclass 34, count 0 2006.286.04:09:06.97#ibcon#about to read 4, iclass 34, count 0 2006.286.04:09:06.97#ibcon#read 4, iclass 34, count 0 2006.286.04:09:06.97#ibcon#about to read 5, iclass 34, count 0 2006.286.04:09:06.97#ibcon#read 5, iclass 34, count 0 2006.286.04:09:06.97#ibcon#about to read 6, iclass 34, count 0 2006.286.04:09:06.97#ibcon#read 6, iclass 34, count 0 2006.286.04:09:06.97#ibcon#end of sib2, iclass 34, count 0 2006.286.04:09:06.97#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:09:06.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:09:06.97#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:09:06.97#ibcon#*before write, iclass 34, count 0 2006.286.04:09:06.97#ibcon#enter sib2, iclass 34, count 0 2006.286.04:09:06.97#ibcon#flushed, iclass 34, count 0 2006.286.04:09:06.97#ibcon#about to write, iclass 34, count 0 2006.286.04:09:06.97#ibcon#wrote, iclass 34, count 0 2006.286.04:09:06.97#ibcon#about to read 3, iclass 34, count 0 2006.286.04:09:07.01#ibcon#read 3, iclass 34, count 0 2006.286.04:09:07.01#ibcon#about to read 4, iclass 34, count 0 2006.286.04:09:07.01#ibcon#read 4, iclass 34, count 0 2006.286.04:09:07.01#ibcon#about to read 5, iclass 34, count 0 2006.286.04:09:07.01#ibcon#read 5, iclass 34, count 0 2006.286.04:09:07.01#ibcon#about to read 6, iclass 34, count 0 2006.286.04:09:07.01#ibcon#read 6, iclass 34, count 0 2006.286.04:09:07.01#ibcon#end of sib2, iclass 34, count 0 2006.286.04:09:07.01#ibcon#*after write, iclass 34, count 0 2006.286.04:09:07.01#ibcon#*before return 0, iclass 34, count 0 2006.286.04:09:07.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:09:07.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:09:07.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:09:07.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:09:07.01$vck44/va=4,6 2006.286.04:09:07.17#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.04:09:07.17#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.04:09:07.17#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:07.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:09:07.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:09:07.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:09:07.17#ibcon#enter wrdev, iclass 36, count 2 2006.286.04:09:07.17#ibcon#first serial, iclass 36, count 2 2006.286.04:09:07.17#ibcon#enter sib2, iclass 36, count 2 2006.286.04:09:07.17#ibcon#flushed, iclass 36, count 2 2006.286.04:09:07.17#ibcon#about to write, iclass 36, count 2 2006.286.04:09:07.17#ibcon#wrote, iclass 36, count 2 2006.286.04:09:07.17#ibcon#about to read 3, iclass 36, count 2 2006.286.04:09:07.19#ibcon#read 3, iclass 36, count 2 2006.286.04:09:07.19#ibcon#about to read 4, iclass 36, count 2 2006.286.04:09:07.19#ibcon#read 4, iclass 36, count 2 2006.286.04:09:07.19#ibcon#about to read 5, iclass 36, count 2 2006.286.04:09:07.19#ibcon#read 5, iclass 36, count 2 2006.286.04:09:07.19#ibcon#about to read 6, iclass 36, count 2 2006.286.04:09:07.19#ibcon#read 6, iclass 36, count 2 2006.286.04:09:07.19#ibcon#end of sib2, iclass 36, count 2 2006.286.04:09:07.19#ibcon#*mode == 0, iclass 36, count 2 2006.286.04:09:07.19#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.04:09:07.19#ibcon#[25=AT04-06\r\n] 2006.286.04:09:07.19#ibcon#*before write, iclass 36, count 2 2006.286.04:09:07.19#ibcon#enter sib2, iclass 36, count 2 2006.286.04:09:07.19#ibcon#flushed, iclass 36, count 2 2006.286.04:09:07.19#ibcon#about to write, iclass 36, count 2 2006.286.04:09:07.19#ibcon#wrote, iclass 36, count 2 2006.286.04:09:07.19#ibcon#about to read 3, iclass 36, count 2 2006.286.04:09:07.22#ibcon#read 3, iclass 36, count 2 2006.286.04:09:07.22#ibcon#about to read 4, iclass 36, count 2 2006.286.04:09:07.22#ibcon#read 4, iclass 36, count 2 2006.286.04:09:07.22#ibcon#about to read 5, iclass 36, count 2 2006.286.04:09:07.22#ibcon#read 5, iclass 36, count 2 2006.286.04:09:07.22#ibcon#about to read 6, iclass 36, count 2 2006.286.04:09:07.22#ibcon#read 6, iclass 36, count 2 2006.286.04:09:07.22#ibcon#end of sib2, iclass 36, count 2 2006.286.04:09:07.22#ibcon#*after write, iclass 36, count 2 2006.286.04:09:07.22#ibcon#*before return 0, iclass 36, count 2 2006.286.04:09:07.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:09:07.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:09:07.22#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.04:09:07.22#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:07.22#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:09:07.34#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:09:07.34#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:09:07.34#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:09:07.34#ibcon#first serial, iclass 36, count 0 2006.286.04:09:07.34#ibcon#enter sib2, iclass 36, count 0 2006.286.04:09:07.34#ibcon#flushed, iclass 36, count 0 2006.286.04:09:07.34#ibcon#about to write, iclass 36, count 0 2006.286.04:09:07.34#ibcon#wrote, iclass 36, count 0 2006.286.04:09:07.34#ibcon#about to read 3, iclass 36, count 0 2006.286.04:09:07.36#ibcon#read 3, iclass 36, count 0 2006.286.04:09:07.36#ibcon#about to read 4, iclass 36, count 0 2006.286.04:09:07.36#ibcon#read 4, iclass 36, count 0 2006.286.04:09:07.36#ibcon#about to read 5, iclass 36, count 0 2006.286.04:09:07.36#ibcon#read 5, iclass 36, count 0 2006.286.04:09:07.36#ibcon#about to read 6, iclass 36, count 0 2006.286.04:09:07.36#ibcon#read 6, iclass 36, count 0 2006.286.04:09:07.36#ibcon#end of sib2, iclass 36, count 0 2006.286.04:09:07.36#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:09:07.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:09:07.36#ibcon#[25=USB\r\n] 2006.286.04:09:07.36#ibcon#*before write, iclass 36, count 0 2006.286.04:09:07.36#ibcon#enter sib2, iclass 36, count 0 2006.286.04:09:07.36#ibcon#flushed, iclass 36, count 0 2006.286.04:09:07.36#ibcon#about to write, iclass 36, count 0 2006.286.04:09:07.36#ibcon#wrote, iclass 36, count 0 2006.286.04:09:07.36#ibcon#about to read 3, iclass 36, count 0 2006.286.04:09:07.39#ibcon#read 3, iclass 36, count 0 2006.286.04:09:07.39#ibcon#about to read 4, iclass 36, count 0 2006.286.04:09:07.39#ibcon#read 4, iclass 36, count 0 2006.286.04:09:07.39#ibcon#about to read 5, iclass 36, count 0 2006.286.04:09:07.39#ibcon#read 5, iclass 36, count 0 2006.286.04:09:07.39#ibcon#about to read 6, iclass 36, count 0 2006.286.04:09:07.39#ibcon#read 6, iclass 36, count 0 2006.286.04:09:07.39#ibcon#end of sib2, iclass 36, count 0 2006.286.04:09:07.39#ibcon#*after write, iclass 36, count 0 2006.286.04:09:07.39#ibcon#*before return 0, iclass 36, count 0 2006.286.04:09:07.39#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:09:07.39#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:09:07.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:09:07.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:09:07.39$vck44/valo=5,734.99 2006.286.04:09:07.39#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.04:09:07.39#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.04:09:07.39#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:07.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:09:07.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:09:07.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:09:07.39#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:09:07.39#ibcon#first serial, iclass 38, count 0 2006.286.04:09:07.39#ibcon#enter sib2, iclass 38, count 0 2006.286.04:09:07.39#ibcon#flushed, iclass 38, count 0 2006.286.04:09:07.39#ibcon#about to write, iclass 38, count 0 2006.286.04:09:07.39#ibcon#wrote, iclass 38, count 0 2006.286.04:09:07.39#ibcon#about to read 3, iclass 38, count 0 2006.286.04:09:07.41#ibcon#read 3, iclass 38, count 0 2006.286.04:09:07.41#ibcon#about to read 4, iclass 38, count 0 2006.286.04:09:07.41#ibcon#read 4, iclass 38, count 0 2006.286.04:09:07.41#ibcon#about to read 5, iclass 38, count 0 2006.286.04:09:07.41#ibcon#read 5, iclass 38, count 0 2006.286.04:09:07.41#ibcon#about to read 6, iclass 38, count 0 2006.286.04:09:07.41#ibcon#read 6, iclass 38, count 0 2006.286.04:09:07.41#ibcon#end of sib2, iclass 38, count 0 2006.286.04:09:07.41#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:09:07.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:09:07.41#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:09:07.41#ibcon#*before write, iclass 38, count 0 2006.286.04:09:07.41#ibcon#enter sib2, iclass 38, count 0 2006.286.04:09:07.41#ibcon#flushed, iclass 38, count 0 2006.286.04:09:07.41#ibcon#about to write, iclass 38, count 0 2006.286.04:09:07.41#ibcon#wrote, iclass 38, count 0 2006.286.04:09:07.41#ibcon#about to read 3, iclass 38, count 0 2006.286.04:09:07.45#ibcon#read 3, iclass 38, count 0 2006.286.04:09:07.45#ibcon#about to read 4, iclass 38, count 0 2006.286.04:09:07.45#ibcon#read 4, iclass 38, count 0 2006.286.04:09:07.45#ibcon#about to read 5, iclass 38, count 0 2006.286.04:09:07.45#ibcon#read 5, iclass 38, count 0 2006.286.04:09:07.45#ibcon#about to read 6, iclass 38, count 0 2006.286.04:09:07.45#ibcon#read 6, iclass 38, count 0 2006.286.04:09:07.45#ibcon#end of sib2, iclass 38, count 0 2006.286.04:09:07.45#ibcon#*after write, iclass 38, count 0 2006.286.04:09:07.45#ibcon#*before return 0, iclass 38, count 0 2006.286.04:09:07.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:09:07.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:09:07.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:09:07.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:09:07.45$vck44/va=5,3 2006.286.04:09:07.45#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.04:09:07.45#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.04:09:07.45#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:07.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:09:07.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:09:07.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:09:07.51#ibcon#enter wrdev, iclass 40, count 2 2006.286.04:09:07.51#ibcon#first serial, iclass 40, count 2 2006.286.04:09:07.51#ibcon#enter sib2, iclass 40, count 2 2006.286.04:09:07.51#ibcon#flushed, iclass 40, count 2 2006.286.04:09:07.51#ibcon#about to write, iclass 40, count 2 2006.286.04:09:07.51#ibcon#wrote, iclass 40, count 2 2006.286.04:09:07.51#ibcon#about to read 3, iclass 40, count 2 2006.286.04:09:07.53#ibcon#read 3, iclass 40, count 2 2006.286.04:09:07.53#ibcon#about to read 4, iclass 40, count 2 2006.286.04:09:07.53#ibcon#read 4, iclass 40, count 2 2006.286.04:09:07.53#ibcon#about to read 5, iclass 40, count 2 2006.286.04:09:07.53#ibcon#read 5, iclass 40, count 2 2006.286.04:09:07.53#ibcon#about to read 6, iclass 40, count 2 2006.286.04:09:07.53#ibcon#read 6, iclass 40, count 2 2006.286.04:09:07.53#ibcon#end of sib2, iclass 40, count 2 2006.286.04:09:07.53#ibcon#*mode == 0, iclass 40, count 2 2006.286.04:09:07.53#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.04:09:07.53#ibcon#[25=AT05-03\r\n] 2006.286.04:09:07.53#ibcon#*before write, iclass 40, count 2 2006.286.04:09:07.53#ibcon#enter sib2, iclass 40, count 2 2006.286.04:09:07.53#ibcon#flushed, iclass 40, count 2 2006.286.04:09:07.53#ibcon#about to write, iclass 40, count 2 2006.286.04:09:07.53#ibcon#wrote, iclass 40, count 2 2006.286.04:09:07.53#ibcon#about to read 3, iclass 40, count 2 2006.286.04:09:07.56#ibcon#read 3, iclass 40, count 2 2006.286.04:09:07.56#ibcon#about to read 4, iclass 40, count 2 2006.286.04:09:07.56#ibcon#read 4, iclass 40, count 2 2006.286.04:09:07.56#ibcon#about to read 5, iclass 40, count 2 2006.286.04:09:07.56#ibcon#read 5, iclass 40, count 2 2006.286.04:09:07.56#ibcon#about to read 6, iclass 40, count 2 2006.286.04:09:07.56#ibcon#read 6, iclass 40, count 2 2006.286.04:09:07.56#ibcon#end of sib2, iclass 40, count 2 2006.286.04:09:07.56#ibcon#*after write, iclass 40, count 2 2006.286.04:09:07.56#ibcon#*before return 0, iclass 40, count 2 2006.286.04:09:07.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:09:07.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:09:07.56#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.04:09:07.56#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:07.56#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:09:07.68#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:09:07.68#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:09:07.68#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:09:07.68#ibcon#first serial, iclass 40, count 0 2006.286.04:09:07.68#ibcon#enter sib2, iclass 40, count 0 2006.286.04:09:07.68#ibcon#flushed, iclass 40, count 0 2006.286.04:09:07.68#ibcon#about to write, iclass 40, count 0 2006.286.04:09:07.68#ibcon#wrote, iclass 40, count 0 2006.286.04:09:07.68#ibcon#about to read 3, iclass 40, count 0 2006.286.04:09:07.70#ibcon#read 3, iclass 40, count 0 2006.286.04:09:07.70#ibcon#about to read 4, iclass 40, count 0 2006.286.04:09:07.70#ibcon#read 4, iclass 40, count 0 2006.286.04:09:07.70#ibcon#about to read 5, iclass 40, count 0 2006.286.04:09:07.70#ibcon#read 5, iclass 40, count 0 2006.286.04:09:07.70#ibcon#about to read 6, iclass 40, count 0 2006.286.04:09:07.70#ibcon#read 6, iclass 40, count 0 2006.286.04:09:07.70#ibcon#end of sib2, iclass 40, count 0 2006.286.04:09:07.70#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:09:07.70#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:09:07.70#ibcon#[25=USB\r\n] 2006.286.04:09:07.70#ibcon#*before write, iclass 40, count 0 2006.286.04:09:07.70#ibcon#enter sib2, iclass 40, count 0 2006.286.04:09:07.70#ibcon#flushed, iclass 40, count 0 2006.286.04:09:07.70#ibcon#about to write, iclass 40, count 0 2006.286.04:09:07.70#ibcon#wrote, iclass 40, count 0 2006.286.04:09:07.70#ibcon#about to read 3, iclass 40, count 0 2006.286.04:09:07.73#ibcon#read 3, iclass 40, count 0 2006.286.04:09:07.73#ibcon#about to read 4, iclass 40, count 0 2006.286.04:09:07.73#ibcon#read 4, iclass 40, count 0 2006.286.04:09:07.73#ibcon#about to read 5, iclass 40, count 0 2006.286.04:09:07.73#ibcon#read 5, iclass 40, count 0 2006.286.04:09:07.73#ibcon#about to read 6, iclass 40, count 0 2006.286.04:09:07.73#ibcon#read 6, iclass 40, count 0 2006.286.04:09:07.73#ibcon#end of sib2, iclass 40, count 0 2006.286.04:09:07.73#ibcon#*after write, iclass 40, count 0 2006.286.04:09:07.73#ibcon#*before return 0, iclass 40, count 0 2006.286.04:09:07.73#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:09:07.73#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:09:07.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:09:07.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:09:07.73$vck44/valo=6,814.99 2006.286.04:09:07.73#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.04:09:07.73#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.04:09:07.73#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:07.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:09:07.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:09:07.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:09:07.73#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:09:07.73#ibcon#first serial, iclass 4, count 0 2006.286.04:09:07.73#ibcon#enter sib2, iclass 4, count 0 2006.286.04:09:07.73#ibcon#flushed, iclass 4, count 0 2006.286.04:09:07.73#ibcon#about to write, iclass 4, count 0 2006.286.04:09:07.73#ibcon#wrote, iclass 4, count 0 2006.286.04:09:07.73#ibcon#about to read 3, iclass 4, count 0 2006.286.04:09:07.75#ibcon#read 3, iclass 4, count 0 2006.286.04:09:07.75#ibcon#about to read 4, iclass 4, count 0 2006.286.04:09:07.75#ibcon#read 4, iclass 4, count 0 2006.286.04:09:07.75#ibcon#about to read 5, iclass 4, count 0 2006.286.04:09:07.75#ibcon#read 5, iclass 4, count 0 2006.286.04:09:07.75#ibcon#about to read 6, iclass 4, count 0 2006.286.04:09:07.75#ibcon#read 6, iclass 4, count 0 2006.286.04:09:07.75#ibcon#end of sib2, iclass 4, count 0 2006.286.04:09:07.75#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:09:07.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:09:07.75#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:09:07.75#ibcon#*before write, iclass 4, count 0 2006.286.04:09:07.75#ibcon#enter sib2, iclass 4, count 0 2006.286.04:09:07.75#ibcon#flushed, iclass 4, count 0 2006.286.04:09:07.75#ibcon#about to write, iclass 4, count 0 2006.286.04:09:07.75#ibcon#wrote, iclass 4, count 0 2006.286.04:09:07.75#ibcon#about to read 3, iclass 4, count 0 2006.286.04:09:07.79#ibcon#read 3, iclass 4, count 0 2006.286.04:09:07.79#ibcon#about to read 4, iclass 4, count 0 2006.286.04:09:07.79#ibcon#read 4, iclass 4, count 0 2006.286.04:09:07.79#ibcon#about to read 5, iclass 4, count 0 2006.286.04:09:07.79#ibcon#read 5, iclass 4, count 0 2006.286.04:09:07.79#ibcon#about to read 6, iclass 4, count 0 2006.286.04:09:07.79#ibcon#read 6, iclass 4, count 0 2006.286.04:09:07.79#ibcon#end of sib2, iclass 4, count 0 2006.286.04:09:07.79#ibcon#*after write, iclass 4, count 0 2006.286.04:09:07.79#ibcon#*before return 0, iclass 4, count 0 2006.286.04:09:07.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:09:07.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:09:07.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:09:07.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:09:07.79$vck44/va=6,4 2006.286.04:09:07.79#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.04:09:07.79#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.04:09:07.79#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:07.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:09:07.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:09:07.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:09:07.85#ibcon#enter wrdev, iclass 6, count 2 2006.286.04:09:07.85#ibcon#first serial, iclass 6, count 2 2006.286.04:09:07.85#ibcon#enter sib2, iclass 6, count 2 2006.286.04:09:07.85#ibcon#flushed, iclass 6, count 2 2006.286.04:09:07.85#ibcon#about to write, iclass 6, count 2 2006.286.04:09:07.85#ibcon#wrote, iclass 6, count 2 2006.286.04:09:07.85#ibcon#about to read 3, iclass 6, count 2 2006.286.04:09:07.87#ibcon#read 3, iclass 6, count 2 2006.286.04:09:07.87#ibcon#about to read 4, iclass 6, count 2 2006.286.04:09:07.87#ibcon#read 4, iclass 6, count 2 2006.286.04:09:07.87#ibcon#about to read 5, iclass 6, count 2 2006.286.04:09:07.87#ibcon#read 5, iclass 6, count 2 2006.286.04:09:07.87#ibcon#about to read 6, iclass 6, count 2 2006.286.04:09:07.87#ibcon#read 6, iclass 6, count 2 2006.286.04:09:07.87#ibcon#end of sib2, iclass 6, count 2 2006.286.04:09:07.87#ibcon#*mode == 0, iclass 6, count 2 2006.286.04:09:07.87#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.04:09:07.87#ibcon#[25=AT06-04\r\n] 2006.286.04:09:07.87#ibcon#*before write, iclass 6, count 2 2006.286.04:09:07.87#ibcon#enter sib2, iclass 6, count 2 2006.286.04:09:07.87#ibcon#flushed, iclass 6, count 2 2006.286.04:09:07.87#ibcon#about to write, iclass 6, count 2 2006.286.04:09:07.87#ibcon#wrote, iclass 6, count 2 2006.286.04:09:07.87#ibcon#about to read 3, iclass 6, count 2 2006.286.04:09:07.90#ibcon#read 3, iclass 6, count 2 2006.286.04:09:07.90#ibcon#about to read 4, iclass 6, count 2 2006.286.04:09:07.90#ibcon#read 4, iclass 6, count 2 2006.286.04:09:07.90#ibcon#about to read 5, iclass 6, count 2 2006.286.04:09:07.90#ibcon#read 5, iclass 6, count 2 2006.286.04:09:07.90#ibcon#about to read 6, iclass 6, count 2 2006.286.04:09:07.90#ibcon#read 6, iclass 6, count 2 2006.286.04:09:07.90#ibcon#end of sib2, iclass 6, count 2 2006.286.04:09:07.90#ibcon#*after write, iclass 6, count 2 2006.286.04:09:07.90#ibcon#*before return 0, iclass 6, count 2 2006.286.04:09:07.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:09:07.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:09:07.90#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.04:09:07.90#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:07.90#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:09:08.02#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:09:08.02#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:09:08.02#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:09:08.02#ibcon#first serial, iclass 6, count 0 2006.286.04:09:08.02#ibcon#enter sib2, iclass 6, count 0 2006.286.04:09:08.02#ibcon#flushed, iclass 6, count 0 2006.286.04:09:08.02#ibcon#about to write, iclass 6, count 0 2006.286.04:09:08.02#ibcon#wrote, iclass 6, count 0 2006.286.04:09:08.02#ibcon#about to read 3, iclass 6, count 0 2006.286.04:09:08.04#ibcon#read 3, iclass 6, count 0 2006.286.04:09:08.04#ibcon#about to read 4, iclass 6, count 0 2006.286.04:09:08.04#ibcon#read 4, iclass 6, count 0 2006.286.04:09:08.04#ibcon#about to read 5, iclass 6, count 0 2006.286.04:09:08.04#ibcon#read 5, iclass 6, count 0 2006.286.04:09:08.04#ibcon#about to read 6, iclass 6, count 0 2006.286.04:09:08.04#ibcon#read 6, iclass 6, count 0 2006.286.04:09:08.04#ibcon#end of sib2, iclass 6, count 0 2006.286.04:09:08.04#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:09:08.04#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:09:08.04#ibcon#[25=USB\r\n] 2006.286.04:09:08.04#ibcon#*before write, iclass 6, count 0 2006.286.04:09:08.04#ibcon#enter sib2, iclass 6, count 0 2006.286.04:09:08.04#ibcon#flushed, iclass 6, count 0 2006.286.04:09:08.04#ibcon#about to write, iclass 6, count 0 2006.286.04:09:08.04#ibcon#wrote, iclass 6, count 0 2006.286.04:09:08.04#ibcon#about to read 3, iclass 6, count 0 2006.286.04:09:08.07#ibcon#read 3, iclass 6, count 0 2006.286.04:09:08.07#ibcon#about to read 4, iclass 6, count 0 2006.286.04:09:08.07#ibcon#read 4, iclass 6, count 0 2006.286.04:09:08.07#ibcon#about to read 5, iclass 6, count 0 2006.286.04:09:08.07#ibcon#read 5, iclass 6, count 0 2006.286.04:09:08.07#ibcon#about to read 6, iclass 6, count 0 2006.286.04:09:08.07#ibcon#read 6, iclass 6, count 0 2006.286.04:09:08.07#ibcon#end of sib2, iclass 6, count 0 2006.286.04:09:08.07#ibcon#*after write, iclass 6, count 0 2006.286.04:09:08.07#ibcon#*before return 0, iclass 6, count 0 2006.286.04:09:08.07#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:09:08.07#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:09:08.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:09:08.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:09:08.07$vck44/valo=7,864.99 2006.286.04:09:08.07#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.04:09:08.07#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.04:09:08.07#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:08.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:09:08.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:09:08.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:09:08.07#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:09:08.07#ibcon#first serial, iclass 10, count 0 2006.286.04:09:08.07#ibcon#enter sib2, iclass 10, count 0 2006.286.04:09:08.07#ibcon#flushed, iclass 10, count 0 2006.286.04:09:08.07#ibcon#about to write, iclass 10, count 0 2006.286.04:09:08.07#ibcon#wrote, iclass 10, count 0 2006.286.04:09:08.07#ibcon#about to read 3, iclass 10, count 0 2006.286.04:09:08.09#ibcon#read 3, iclass 10, count 0 2006.286.04:09:08.09#ibcon#about to read 4, iclass 10, count 0 2006.286.04:09:08.09#ibcon#read 4, iclass 10, count 0 2006.286.04:09:08.09#ibcon#about to read 5, iclass 10, count 0 2006.286.04:09:08.09#ibcon#read 5, iclass 10, count 0 2006.286.04:09:08.09#ibcon#about to read 6, iclass 10, count 0 2006.286.04:09:08.09#ibcon#read 6, iclass 10, count 0 2006.286.04:09:08.09#ibcon#end of sib2, iclass 10, count 0 2006.286.04:09:08.09#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:09:08.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:09:08.09#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:09:08.09#ibcon#*before write, iclass 10, count 0 2006.286.04:09:08.09#ibcon#enter sib2, iclass 10, count 0 2006.286.04:09:08.09#ibcon#flushed, iclass 10, count 0 2006.286.04:09:08.09#ibcon#about to write, iclass 10, count 0 2006.286.04:09:08.09#ibcon#wrote, iclass 10, count 0 2006.286.04:09:08.09#ibcon#about to read 3, iclass 10, count 0 2006.286.04:09:08.13#ibcon#read 3, iclass 10, count 0 2006.286.04:09:08.13#ibcon#about to read 4, iclass 10, count 0 2006.286.04:09:08.13#ibcon#read 4, iclass 10, count 0 2006.286.04:09:08.13#ibcon#about to read 5, iclass 10, count 0 2006.286.04:09:08.13#ibcon#read 5, iclass 10, count 0 2006.286.04:09:08.13#ibcon#about to read 6, iclass 10, count 0 2006.286.04:09:08.13#ibcon#read 6, iclass 10, count 0 2006.286.04:09:08.13#ibcon#end of sib2, iclass 10, count 0 2006.286.04:09:08.13#ibcon#*after write, iclass 10, count 0 2006.286.04:09:08.13#ibcon#*before return 0, iclass 10, count 0 2006.286.04:09:08.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:09:08.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:09:08.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:09:08.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:09:08.13$vck44/va=7,4 2006.286.04:09:08.13#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.04:09:08.13#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.04:09:08.13#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:08.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:09:08.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:09:08.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:09:08.19#ibcon#enter wrdev, iclass 12, count 2 2006.286.04:09:08.19#ibcon#first serial, iclass 12, count 2 2006.286.04:09:08.19#ibcon#enter sib2, iclass 12, count 2 2006.286.04:09:08.19#ibcon#flushed, iclass 12, count 2 2006.286.04:09:08.19#ibcon#about to write, iclass 12, count 2 2006.286.04:09:08.19#ibcon#wrote, iclass 12, count 2 2006.286.04:09:08.19#ibcon#about to read 3, iclass 12, count 2 2006.286.04:09:08.21#ibcon#read 3, iclass 12, count 2 2006.286.04:09:08.21#ibcon#about to read 4, iclass 12, count 2 2006.286.04:09:08.21#ibcon#read 4, iclass 12, count 2 2006.286.04:09:08.21#ibcon#about to read 5, iclass 12, count 2 2006.286.04:09:08.21#ibcon#read 5, iclass 12, count 2 2006.286.04:09:08.21#ibcon#about to read 6, iclass 12, count 2 2006.286.04:09:08.21#ibcon#read 6, iclass 12, count 2 2006.286.04:09:08.21#ibcon#end of sib2, iclass 12, count 2 2006.286.04:09:08.21#ibcon#*mode == 0, iclass 12, count 2 2006.286.04:09:08.21#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.04:09:08.21#ibcon#[25=AT07-04\r\n] 2006.286.04:09:08.21#ibcon#*before write, iclass 12, count 2 2006.286.04:09:08.21#ibcon#enter sib2, iclass 12, count 2 2006.286.04:09:08.21#ibcon#flushed, iclass 12, count 2 2006.286.04:09:08.21#ibcon#about to write, iclass 12, count 2 2006.286.04:09:08.21#ibcon#wrote, iclass 12, count 2 2006.286.04:09:08.21#ibcon#about to read 3, iclass 12, count 2 2006.286.04:09:08.24#ibcon#read 3, iclass 12, count 2 2006.286.04:09:08.24#ibcon#about to read 4, iclass 12, count 2 2006.286.04:09:08.24#ibcon#read 4, iclass 12, count 2 2006.286.04:09:08.24#ibcon#about to read 5, iclass 12, count 2 2006.286.04:09:08.24#ibcon#read 5, iclass 12, count 2 2006.286.04:09:08.24#ibcon#about to read 6, iclass 12, count 2 2006.286.04:09:08.24#ibcon#read 6, iclass 12, count 2 2006.286.04:09:08.24#ibcon#end of sib2, iclass 12, count 2 2006.286.04:09:08.24#ibcon#*after write, iclass 12, count 2 2006.286.04:09:08.24#ibcon#*before return 0, iclass 12, count 2 2006.286.04:09:08.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:09:08.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:09:08.24#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.04:09:08.24#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:08.24#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:09:08.36#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:09:08.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:09:08.42#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:09:08.42#ibcon#first serial, iclass 12, count 0 2006.286.04:09:08.42#ibcon#enter sib2, iclass 12, count 0 2006.286.04:09:08.42#ibcon#flushed, iclass 12, count 0 2006.286.04:09:08.42#ibcon#about to write, iclass 12, count 0 2006.286.04:09:08.42#ibcon#wrote, iclass 12, count 0 2006.286.04:09:08.42#ibcon#about to read 3, iclass 12, count 0 2006.286.04:09:08.43#ibcon#read 3, iclass 12, count 0 2006.286.04:09:08.43#ibcon#about to read 4, iclass 12, count 0 2006.286.04:09:08.43#ibcon#read 4, iclass 12, count 0 2006.286.04:09:08.43#ibcon#about to read 5, iclass 12, count 0 2006.286.04:09:08.43#ibcon#read 5, iclass 12, count 0 2006.286.04:09:08.43#ibcon#about to read 6, iclass 12, count 0 2006.286.04:09:08.43#ibcon#read 6, iclass 12, count 0 2006.286.04:09:08.43#ibcon#end of sib2, iclass 12, count 0 2006.286.04:09:08.43#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:09:08.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:09:08.43#ibcon#[25=USB\r\n] 2006.286.04:09:08.43#ibcon#*before write, iclass 12, count 0 2006.286.04:09:08.43#ibcon#enter sib2, iclass 12, count 0 2006.286.04:09:08.43#ibcon#flushed, iclass 12, count 0 2006.286.04:09:08.43#ibcon#about to write, iclass 12, count 0 2006.286.04:09:08.43#ibcon#wrote, iclass 12, count 0 2006.286.04:09:08.43#ibcon#about to read 3, iclass 12, count 0 2006.286.04:09:08.46#ibcon#read 3, iclass 12, count 0 2006.286.04:09:08.46#ibcon#about to read 4, iclass 12, count 0 2006.286.04:09:08.46#ibcon#read 4, iclass 12, count 0 2006.286.04:09:08.46#ibcon#about to read 5, iclass 12, count 0 2006.286.04:09:08.46#ibcon#read 5, iclass 12, count 0 2006.286.04:09:08.46#ibcon#about to read 6, iclass 12, count 0 2006.286.04:09:08.46#ibcon#read 6, iclass 12, count 0 2006.286.04:09:08.46#ibcon#end of sib2, iclass 12, count 0 2006.286.04:09:08.46#ibcon#*after write, iclass 12, count 0 2006.286.04:09:08.46#ibcon#*before return 0, iclass 12, count 0 2006.286.04:09:08.46#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:09:08.46#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:09:08.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:09:08.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:09:08.46$vck44/valo=8,884.99 2006.286.04:09:08.46#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.04:09:08.46#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.04:09:08.46#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:08.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:09:08.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:09:08.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:09:08.46#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:09:08.46#ibcon#first serial, iclass 14, count 0 2006.286.04:09:08.46#ibcon#enter sib2, iclass 14, count 0 2006.286.04:09:08.46#ibcon#flushed, iclass 14, count 0 2006.286.04:09:08.46#ibcon#about to write, iclass 14, count 0 2006.286.04:09:08.46#ibcon#wrote, iclass 14, count 0 2006.286.04:09:08.46#ibcon#about to read 3, iclass 14, count 0 2006.286.04:09:08.48#ibcon#read 3, iclass 14, count 0 2006.286.04:09:08.48#ibcon#about to read 4, iclass 14, count 0 2006.286.04:09:08.48#ibcon#read 4, iclass 14, count 0 2006.286.04:09:08.48#ibcon#about to read 5, iclass 14, count 0 2006.286.04:09:08.48#ibcon#read 5, iclass 14, count 0 2006.286.04:09:08.48#ibcon#about to read 6, iclass 14, count 0 2006.286.04:09:08.48#ibcon#read 6, iclass 14, count 0 2006.286.04:09:08.48#ibcon#end of sib2, iclass 14, count 0 2006.286.04:09:08.48#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:09:08.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:09:08.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:09:08.48#ibcon#*before write, iclass 14, count 0 2006.286.04:09:08.48#ibcon#enter sib2, iclass 14, count 0 2006.286.04:09:08.48#ibcon#flushed, iclass 14, count 0 2006.286.04:09:08.48#ibcon#about to write, iclass 14, count 0 2006.286.04:09:08.48#ibcon#wrote, iclass 14, count 0 2006.286.04:09:08.48#ibcon#about to read 3, iclass 14, count 0 2006.286.04:09:08.52#ibcon#read 3, iclass 14, count 0 2006.286.04:09:08.52#ibcon#about to read 4, iclass 14, count 0 2006.286.04:09:08.52#ibcon#read 4, iclass 14, count 0 2006.286.04:09:08.52#ibcon#about to read 5, iclass 14, count 0 2006.286.04:09:08.52#ibcon#read 5, iclass 14, count 0 2006.286.04:09:08.52#ibcon#about to read 6, iclass 14, count 0 2006.286.04:09:08.52#ibcon#read 6, iclass 14, count 0 2006.286.04:09:08.52#ibcon#end of sib2, iclass 14, count 0 2006.286.04:09:08.52#ibcon#*after write, iclass 14, count 0 2006.286.04:09:08.52#ibcon#*before return 0, iclass 14, count 0 2006.286.04:09:08.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:09:08.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:09:08.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:09:08.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:09:08.52$vck44/va=8,3 2006.286.04:09:08.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.04:09:08.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.04:09:08.52#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:08.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:09:08.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:09:08.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:09:08.58#ibcon#enter wrdev, iclass 16, count 2 2006.286.04:09:08.58#ibcon#first serial, iclass 16, count 2 2006.286.04:09:08.58#ibcon#enter sib2, iclass 16, count 2 2006.286.04:09:08.58#ibcon#flushed, iclass 16, count 2 2006.286.04:09:08.58#ibcon#about to write, iclass 16, count 2 2006.286.04:09:08.58#ibcon#wrote, iclass 16, count 2 2006.286.04:09:08.58#ibcon#about to read 3, iclass 16, count 2 2006.286.04:09:08.60#ibcon#read 3, iclass 16, count 2 2006.286.04:09:08.60#ibcon#about to read 4, iclass 16, count 2 2006.286.04:09:08.60#ibcon#read 4, iclass 16, count 2 2006.286.04:09:08.60#ibcon#about to read 5, iclass 16, count 2 2006.286.04:09:08.60#ibcon#read 5, iclass 16, count 2 2006.286.04:09:08.60#ibcon#about to read 6, iclass 16, count 2 2006.286.04:09:08.60#ibcon#read 6, iclass 16, count 2 2006.286.04:09:08.60#ibcon#end of sib2, iclass 16, count 2 2006.286.04:09:08.60#ibcon#*mode == 0, iclass 16, count 2 2006.286.04:09:08.60#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.04:09:08.60#ibcon#[25=AT08-03\r\n] 2006.286.04:09:08.60#ibcon#*before write, iclass 16, count 2 2006.286.04:09:08.60#ibcon#enter sib2, iclass 16, count 2 2006.286.04:09:08.60#ibcon#flushed, iclass 16, count 2 2006.286.04:09:08.60#ibcon#about to write, iclass 16, count 2 2006.286.04:09:08.60#ibcon#wrote, iclass 16, count 2 2006.286.04:09:08.60#ibcon#about to read 3, iclass 16, count 2 2006.286.04:09:08.63#ibcon#read 3, iclass 16, count 2 2006.286.04:09:08.63#ibcon#about to read 4, iclass 16, count 2 2006.286.04:09:08.63#ibcon#read 4, iclass 16, count 2 2006.286.04:09:08.63#ibcon#about to read 5, iclass 16, count 2 2006.286.04:09:08.63#ibcon#read 5, iclass 16, count 2 2006.286.04:09:08.63#ibcon#about to read 6, iclass 16, count 2 2006.286.04:09:08.63#ibcon#read 6, iclass 16, count 2 2006.286.04:09:08.63#ibcon#end of sib2, iclass 16, count 2 2006.286.04:09:08.63#ibcon#*after write, iclass 16, count 2 2006.286.04:09:08.63#ibcon#*before return 0, iclass 16, count 2 2006.286.04:09:08.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:09:08.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:09:08.63#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.04:09:08.63#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:08.63#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:09:08.75#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:09:08.75#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:09:08.75#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:09:08.75#ibcon#first serial, iclass 16, count 0 2006.286.04:09:08.75#ibcon#enter sib2, iclass 16, count 0 2006.286.04:09:08.75#ibcon#flushed, iclass 16, count 0 2006.286.04:09:08.75#ibcon#about to write, iclass 16, count 0 2006.286.04:09:08.75#ibcon#wrote, iclass 16, count 0 2006.286.04:09:08.75#ibcon#about to read 3, iclass 16, count 0 2006.286.04:09:08.77#ibcon#read 3, iclass 16, count 0 2006.286.04:09:08.77#ibcon#about to read 4, iclass 16, count 0 2006.286.04:09:08.77#ibcon#read 4, iclass 16, count 0 2006.286.04:09:08.77#ibcon#about to read 5, iclass 16, count 0 2006.286.04:09:08.77#ibcon#read 5, iclass 16, count 0 2006.286.04:09:08.77#ibcon#about to read 6, iclass 16, count 0 2006.286.04:09:08.77#ibcon#read 6, iclass 16, count 0 2006.286.04:09:08.77#ibcon#end of sib2, iclass 16, count 0 2006.286.04:09:08.77#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:09:08.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:09:08.77#ibcon#[25=USB\r\n] 2006.286.04:09:08.77#ibcon#*before write, iclass 16, count 0 2006.286.04:09:08.77#ibcon#enter sib2, iclass 16, count 0 2006.286.04:09:08.77#ibcon#flushed, iclass 16, count 0 2006.286.04:09:08.77#ibcon#about to write, iclass 16, count 0 2006.286.04:09:08.77#ibcon#wrote, iclass 16, count 0 2006.286.04:09:08.77#ibcon#about to read 3, iclass 16, count 0 2006.286.04:09:08.80#ibcon#read 3, iclass 16, count 0 2006.286.04:09:08.80#ibcon#about to read 4, iclass 16, count 0 2006.286.04:09:08.80#ibcon#read 4, iclass 16, count 0 2006.286.04:09:08.80#ibcon#about to read 5, iclass 16, count 0 2006.286.04:09:08.80#ibcon#read 5, iclass 16, count 0 2006.286.04:09:08.80#ibcon#about to read 6, iclass 16, count 0 2006.286.04:09:08.80#ibcon#read 6, iclass 16, count 0 2006.286.04:09:08.80#ibcon#end of sib2, iclass 16, count 0 2006.286.04:09:08.80#ibcon#*after write, iclass 16, count 0 2006.286.04:09:08.80#ibcon#*before return 0, iclass 16, count 0 2006.286.04:09:08.80#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:09:08.80#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:09:08.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:09:08.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:09:08.80$vck44/vblo=1,629.99 2006.286.04:09:08.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.04:09:08.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.04:09:08.80#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:08.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:09:08.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:09:08.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:09:08.80#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:09:08.80#ibcon#first serial, iclass 18, count 0 2006.286.04:09:08.80#ibcon#enter sib2, iclass 18, count 0 2006.286.04:09:08.80#ibcon#flushed, iclass 18, count 0 2006.286.04:09:08.80#ibcon#about to write, iclass 18, count 0 2006.286.04:09:08.80#ibcon#wrote, iclass 18, count 0 2006.286.04:09:08.80#ibcon#about to read 3, iclass 18, count 0 2006.286.04:09:08.82#ibcon#read 3, iclass 18, count 0 2006.286.04:09:08.82#ibcon#about to read 4, iclass 18, count 0 2006.286.04:09:08.82#ibcon#read 4, iclass 18, count 0 2006.286.04:09:08.82#ibcon#about to read 5, iclass 18, count 0 2006.286.04:09:08.82#ibcon#read 5, iclass 18, count 0 2006.286.04:09:08.82#ibcon#about to read 6, iclass 18, count 0 2006.286.04:09:08.82#ibcon#read 6, iclass 18, count 0 2006.286.04:09:08.82#ibcon#end of sib2, iclass 18, count 0 2006.286.04:09:08.82#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:09:08.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:09:08.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:09:08.82#ibcon#*before write, iclass 18, count 0 2006.286.04:09:08.82#ibcon#enter sib2, iclass 18, count 0 2006.286.04:09:08.82#ibcon#flushed, iclass 18, count 0 2006.286.04:09:08.82#ibcon#about to write, iclass 18, count 0 2006.286.04:09:08.82#ibcon#wrote, iclass 18, count 0 2006.286.04:09:08.82#ibcon#about to read 3, iclass 18, count 0 2006.286.04:09:08.86#ibcon#read 3, iclass 18, count 0 2006.286.04:09:08.86#ibcon#about to read 4, iclass 18, count 0 2006.286.04:09:08.86#ibcon#read 4, iclass 18, count 0 2006.286.04:09:08.86#ibcon#about to read 5, iclass 18, count 0 2006.286.04:09:08.86#ibcon#read 5, iclass 18, count 0 2006.286.04:09:08.86#ibcon#about to read 6, iclass 18, count 0 2006.286.04:09:08.86#ibcon#read 6, iclass 18, count 0 2006.286.04:09:08.86#ibcon#end of sib2, iclass 18, count 0 2006.286.04:09:08.86#ibcon#*after write, iclass 18, count 0 2006.286.04:09:08.86#ibcon#*before return 0, iclass 18, count 0 2006.286.04:09:08.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:09:08.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:09:08.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:09:08.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:09:08.86$vck44/vb=1,4 2006.286.04:09:08.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.04:09:08.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.04:09:08.86#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:08.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:09:08.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:09:08.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:09:08.86#ibcon#enter wrdev, iclass 20, count 2 2006.286.04:09:08.86#ibcon#first serial, iclass 20, count 2 2006.286.04:09:08.86#ibcon#enter sib2, iclass 20, count 2 2006.286.04:09:08.86#ibcon#flushed, iclass 20, count 2 2006.286.04:09:08.86#ibcon#about to write, iclass 20, count 2 2006.286.04:09:08.86#ibcon#wrote, iclass 20, count 2 2006.286.04:09:08.86#ibcon#about to read 3, iclass 20, count 2 2006.286.04:09:08.88#ibcon#read 3, iclass 20, count 2 2006.286.04:09:08.88#ibcon#about to read 4, iclass 20, count 2 2006.286.04:09:08.88#ibcon#read 4, iclass 20, count 2 2006.286.04:09:08.88#ibcon#about to read 5, iclass 20, count 2 2006.286.04:09:08.88#ibcon#read 5, iclass 20, count 2 2006.286.04:09:08.88#ibcon#about to read 6, iclass 20, count 2 2006.286.04:09:08.88#ibcon#read 6, iclass 20, count 2 2006.286.04:09:08.88#ibcon#end of sib2, iclass 20, count 2 2006.286.04:09:08.88#ibcon#*mode == 0, iclass 20, count 2 2006.286.04:09:08.88#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.04:09:08.88#ibcon#[27=AT01-04\r\n] 2006.286.04:09:08.88#ibcon#*before write, iclass 20, count 2 2006.286.04:09:08.88#ibcon#enter sib2, iclass 20, count 2 2006.286.04:09:08.88#ibcon#flushed, iclass 20, count 2 2006.286.04:09:08.88#ibcon#about to write, iclass 20, count 2 2006.286.04:09:08.88#ibcon#wrote, iclass 20, count 2 2006.286.04:09:08.88#ibcon#about to read 3, iclass 20, count 2 2006.286.04:09:08.91#ibcon#read 3, iclass 20, count 2 2006.286.04:09:08.91#ibcon#about to read 4, iclass 20, count 2 2006.286.04:09:08.91#ibcon#read 4, iclass 20, count 2 2006.286.04:09:08.91#ibcon#about to read 5, iclass 20, count 2 2006.286.04:09:08.91#ibcon#read 5, iclass 20, count 2 2006.286.04:09:08.91#ibcon#about to read 6, iclass 20, count 2 2006.286.04:09:08.91#ibcon#read 6, iclass 20, count 2 2006.286.04:09:08.91#ibcon#end of sib2, iclass 20, count 2 2006.286.04:09:08.91#ibcon#*after write, iclass 20, count 2 2006.286.04:09:08.91#ibcon#*before return 0, iclass 20, count 2 2006.286.04:09:08.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:09:08.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:09:08.91#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.04:09:08.91#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:08.91#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:09:09.03#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:09:09.03#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:09:09.03#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:09:09.03#ibcon#first serial, iclass 20, count 0 2006.286.04:09:09.03#ibcon#enter sib2, iclass 20, count 0 2006.286.04:09:09.03#ibcon#flushed, iclass 20, count 0 2006.286.04:09:09.03#ibcon#about to write, iclass 20, count 0 2006.286.04:09:09.03#ibcon#wrote, iclass 20, count 0 2006.286.04:09:09.03#ibcon#about to read 3, iclass 20, count 0 2006.286.04:09:09.05#ibcon#read 3, iclass 20, count 0 2006.286.04:09:09.05#ibcon#about to read 4, iclass 20, count 0 2006.286.04:09:09.05#ibcon#read 4, iclass 20, count 0 2006.286.04:09:09.05#ibcon#about to read 5, iclass 20, count 0 2006.286.04:09:09.05#ibcon#read 5, iclass 20, count 0 2006.286.04:09:09.05#ibcon#about to read 6, iclass 20, count 0 2006.286.04:09:09.05#ibcon#read 6, iclass 20, count 0 2006.286.04:09:09.05#ibcon#end of sib2, iclass 20, count 0 2006.286.04:09:09.05#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:09:09.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:09:09.05#ibcon#[27=USB\r\n] 2006.286.04:09:09.05#ibcon#*before write, iclass 20, count 0 2006.286.04:09:09.05#ibcon#enter sib2, iclass 20, count 0 2006.286.04:09:09.05#ibcon#flushed, iclass 20, count 0 2006.286.04:09:09.05#ibcon#about to write, iclass 20, count 0 2006.286.04:09:09.05#ibcon#wrote, iclass 20, count 0 2006.286.04:09:09.05#ibcon#about to read 3, iclass 20, count 0 2006.286.04:09:09.08#ibcon#read 3, iclass 20, count 0 2006.286.04:09:09.08#ibcon#about to read 4, iclass 20, count 0 2006.286.04:09:09.08#ibcon#read 4, iclass 20, count 0 2006.286.04:09:09.08#ibcon#about to read 5, iclass 20, count 0 2006.286.04:09:09.08#ibcon#read 5, iclass 20, count 0 2006.286.04:09:09.08#ibcon#about to read 6, iclass 20, count 0 2006.286.04:09:09.08#ibcon#read 6, iclass 20, count 0 2006.286.04:09:09.08#ibcon#end of sib2, iclass 20, count 0 2006.286.04:09:09.08#ibcon#*after write, iclass 20, count 0 2006.286.04:09:09.08#ibcon#*before return 0, iclass 20, count 0 2006.286.04:09:09.08#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:09:09.08#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:09:09.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:09:09.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:09:09.08$vck44/vblo=2,634.99 2006.286.04:09:09.08#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:09:09.08#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:09:09.08#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:09.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:09:09.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:09:09.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:09:09.08#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:09:09.08#ibcon#first serial, iclass 22, count 0 2006.286.04:09:09.08#ibcon#enter sib2, iclass 22, count 0 2006.286.04:09:09.08#ibcon#flushed, iclass 22, count 0 2006.286.04:09:09.08#ibcon#about to write, iclass 22, count 0 2006.286.04:09:09.08#ibcon#wrote, iclass 22, count 0 2006.286.04:09:09.08#ibcon#about to read 3, iclass 22, count 0 2006.286.04:09:09.10#ibcon#read 3, iclass 22, count 0 2006.286.04:09:09.10#ibcon#about to read 4, iclass 22, count 0 2006.286.04:09:09.10#ibcon#read 4, iclass 22, count 0 2006.286.04:09:09.10#ibcon#about to read 5, iclass 22, count 0 2006.286.04:09:09.10#ibcon#read 5, iclass 22, count 0 2006.286.04:09:09.10#ibcon#about to read 6, iclass 22, count 0 2006.286.04:09:09.10#ibcon#read 6, iclass 22, count 0 2006.286.04:09:09.10#ibcon#end of sib2, iclass 22, count 0 2006.286.04:09:09.10#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:09:09.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:09:09.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:09:09.10#ibcon#*before write, iclass 22, count 0 2006.286.04:09:09.10#ibcon#enter sib2, iclass 22, count 0 2006.286.04:09:09.10#ibcon#flushed, iclass 22, count 0 2006.286.04:09:09.10#ibcon#about to write, iclass 22, count 0 2006.286.04:09:09.10#ibcon#wrote, iclass 22, count 0 2006.286.04:09:09.10#ibcon#about to read 3, iclass 22, count 0 2006.286.04:09:09.14#ibcon#read 3, iclass 22, count 0 2006.286.04:09:09.14#ibcon#about to read 4, iclass 22, count 0 2006.286.04:09:09.14#ibcon#read 4, iclass 22, count 0 2006.286.04:09:09.14#ibcon#about to read 5, iclass 22, count 0 2006.286.04:09:09.14#ibcon#read 5, iclass 22, count 0 2006.286.04:09:09.14#ibcon#about to read 6, iclass 22, count 0 2006.286.04:09:09.14#ibcon#read 6, iclass 22, count 0 2006.286.04:09:09.14#ibcon#end of sib2, iclass 22, count 0 2006.286.04:09:09.14#ibcon#*after write, iclass 22, count 0 2006.286.04:09:09.14#ibcon#*before return 0, iclass 22, count 0 2006.286.04:09:09.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:09:09.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:09:09.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:09:09.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:09:09.14$vck44/vb=2,5 2006.286.04:09:09.14#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.04:09:09.14#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.04:09:09.14#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:09.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:09:09.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:09:09.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:09:09.20#ibcon#enter wrdev, iclass 24, count 2 2006.286.04:09:09.20#ibcon#first serial, iclass 24, count 2 2006.286.04:09:09.20#ibcon#enter sib2, iclass 24, count 2 2006.286.04:09:09.20#ibcon#flushed, iclass 24, count 2 2006.286.04:09:09.20#ibcon#about to write, iclass 24, count 2 2006.286.04:09:09.20#ibcon#wrote, iclass 24, count 2 2006.286.04:09:09.20#ibcon#about to read 3, iclass 24, count 2 2006.286.04:09:09.22#ibcon#read 3, iclass 24, count 2 2006.286.04:09:09.22#ibcon#about to read 4, iclass 24, count 2 2006.286.04:09:09.22#ibcon#read 4, iclass 24, count 2 2006.286.04:09:09.22#ibcon#about to read 5, iclass 24, count 2 2006.286.04:09:09.22#ibcon#read 5, iclass 24, count 2 2006.286.04:09:09.22#ibcon#about to read 6, iclass 24, count 2 2006.286.04:09:09.22#ibcon#read 6, iclass 24, count 2 2006.286.04:09:09.22#ibcon#end of sib2, iclass 24, count 2 2006.286.04:09:09.22#ibcon#*mode == 0, iclass 24, count 2 2006.286.04:09:09.22#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.04:09:09.22#ibcon#[27=AT02-05\r\n] 2006.286.04:09:09.22#ibcon#*before write, iclass 24, count 2 2006.286.04:09:09.22#ibcon#enter sib2, iclass 24, count 2 2006.286.04:09:09.22#ibcon#flushed, iclass 24, count 2 2006.286.04:09:09.22#ibcon#about to write, iclass 24, count 2 2006.286.04:09:09.22#ibcon#wrote, iclass 24, count 2 2006.286.04:09:09.22#ibcon#about to read 3, iclass 24, count 2 2006.286.04:09:09.25#ibcon#read 3, iclass 24, count 2 2006.286.04:09:09.25#ibcon#about to read 4, iclass 24, count 2 2006.286.04:09:09.25#ibcon#read 4, iclass 24, count 2 2006.286.04:09:09.25#ibcon#about to read 5, iclass 24, count 2 2006.286.04:09:09.25#ibcon#read 5, iclass 24, count 2 2006.286.04:09:09.25#ibcon#about to read 6, iclass 24, count 2 2006.286.04:09:09.25#ibcon#read 6, iclass 24, count 2 2006.286.04:09:09.25#ibcon#end of sib2, iclass 24, count 2 2006.286.04:09:09.25#ibcon#*after write, iclass 24, count 2 2006.286.04:09:09.25#ibcon#*before return 0, iclass 24, count 2 2006.286.04:09:09.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:09:09.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:09:09.25#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.04:09:09.25#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:09.25#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:09:09.37#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:09:09.37#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:09:09.40#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:09:09.40#ibcon#first serial, iclass 24, count 0 2006.286.04:09:09.40#ibcon#enter sib2, iclass 24, count 0 2006.286.04:09:09.40#ibcon#flushed, iclass 24, count 0 2006.286.04:09:09.40#ibcon#about to write, iclass 24, count 0 2006.286.04:09:09.40#ibcon#wrote, iclass 24, count 0 2006.286.04:09:09.40#ibcon#about to read 3, iclass 24, count 0 2006.286.04:09:09.42#ibcon#read 3, iclass 24, count 0 2006.286.04:09:09.42#ibcon#about to read 4, iclass 24, count 0 2006.286.04:09:09.42#ibcon#read 4, iclass 24, count 0 2006.286.04:09:09.42#ibcon#about to read 5, iclass 24, count 0 2006.286.04:09:09.42#ibcon#read 5, iclass 24, count 0 2006.286.04:09:09.42#ibcon#about to read 6, iclass 24, count 0 2006.286.04:09:09.42#ibcon#read 6, iclass 24, count 0 2006.286.04:09:09.42#ibcon#end of sib2, iclass 24, count 0 2006.286.04:09:09.42#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:09:09.42#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:09:09.42#ibcon#[27=USB\r\n] 2006.286.04:09:09.42#ibcon#*before write, iclass 24, count 0 2006.286.04:09:09.42#ibcon#enter sib2, iclass 24, count 0 2006.286.04:09:09.42#ibcon#flushed, iclass 24, count 0 2006.286.04:09:09.42#ibcon#about to write, iclass 24, count 0 2006.286.04:09:09.42#ibcon#wrote, iclass 24, count 0 2006.286.04:09:09.42#ibcon#about to read 3, iclass 24, count 0 2006.286.04:09:09.45#ibcon#read 3, iclass 24, count 0 2006.286.04:09:09.45#ibcon#about to read 4, iclass 24, count 0 2006.286.04:09:09.45#ibcon#read 4, iclass 24, count 0 2006.286.04:09:09.45#ibcon#about to read 5, iclass 24, count 0 2006.286.04:09:09.45#ibcon#read 5, iclass 24, count 0 2006.286.04:09:09.45#ibcon#about to read 6, iclass 24, count 0 2006.286.04:09:09.45#ibcon#read 6, iclass 24, count 0 2006.286.04:09:09.45#ibcon#end of sib2, iclass 24, count 0 2006.286.04:09:09.45#ibcon#*after write, iclass 24, count 0 2006.286.04:09:09.45#ibcon#*before return 0, iclass 24, count 0 2006.286.04:09:09.45#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:09:09.45#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:09:09.45#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:09:09.45#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:09:09.45$vck44/vblo=3,649.99 2006.286.04:09:09.45#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.04:09:09.45#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.04:09:09.45#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:09.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:09:09.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:09:09.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:09:09.45#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:09:09.45#ibcon#first serial, iclass 26, count 0 2006.286.04:09:09.45#ibcon#enter sib2, iclass 26, count 0 2006.286.04:09:09.45#ibcon#flushed, iclass 26, count 0 2006.286.04:09:09.45#ibcon#about to write, iclass 26, count 0 2006.286.04:09:09.45#ibcon#wrote, iclass 26, count 0 2006.286.04:09:09.45#ibcon#about to read 3, iclass 26, count 0 2006.286.04:09:09.47#ibcon#read 3, iclass 26, count 0 2006.286.04:09:09.47#ibcon#about to read 4, iclass 26, count 0 2006.286.04:09:09.47#ibcon#read 4, iclass 26, count 0 2006.286.04:09:09.47#ibcon#about to read 5, iclass 26, count 0 2006.286.04:09:09.47#ibcon#read 5, iclass 26, count 0 2006.286.04:09:09.47#ibcon#about to read 6, iclass 26, count 0 2006.286.04:09:09.47#ibcon#read 6, iclass 26, count 0 2006.286.04:09:09.47#ibcon#end of sib2, iclass 26, count 0 2006.286.04:09:09.47#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:09:09.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:09:09.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:09:09.47#ibcon#*before write, iclass 26, count 0 2006.286.04:09:09.47#ibcon#enter sib2, iclass 26, count 0 2006.286.04:09:09.47#ibcon#flushed, iclass 26, count 0 2006.286.04:09:09.47#ibcon#about to write, iclass 26, count 0 2006.286.04:09:09.47#ibcon#wrote, iclass 26, count 0 2006.286.04:09:09.47#ibcon#about to read 3, iclass 26, count 0 2006.286.04:09:09.51#ibcon#read 3, iclass 26, count 0 2006.286.04:09:09.51#ibcon#about to read 4, iclass 26, count 0 2006.286.04:09:09.51#ibcon#read 4, iclass 26, count 0 2006.286.04:09:09.51#ibcon#about to read 5, iclass 26, count 0 2006.286.04:09:09.51#ibcon#read 5, iclass 26, count 0 2006.286.04:09:09.51#ibcon#about to read 6, iclass 26, count 0 2006.286.04:09:09.51#ibcon#read 6, iclass 26, count 0 2006.286.04:09:09.51#ibcon#end of sib2, iclass 26, count 0 2006.286.04:09:09.51#ibcon#*after write, iclass 26, count 0 2006.286.04:09:09.51#ibcon#*before return 0, iclass 26, count 0 2006.286.04:09:09.51#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:09:09.51#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:09:09.51#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:09:09.51#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:09:09.51$vck44/vb=3,4 2006.286.04:09:09.51#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.04:09:09.51#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.04:09:09.51#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:09.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:09:09.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:09:09.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:09:09.57#ibcon#enter wrdev, iclass 28, count 2 2006.286.04:09:09.57#ibcon#first serial, iclass 28, count 2 2006.286.04:09:09.57#ibcon#enter sib2, iclass 28, count 2 2006.286.04:09:09.57#ibcon#flushed, iclass 28, count 2 2006.286.04:09:09.57#ibcon#about to write, iclass 28, count 2 2006.286.04:09:09.57#ibcon#wrote, iclass 28, count 2 2006.286.04:09:09.57#ibcon#about to read 3, iclass 28, count 2 2006.286.04:09:09.59#ibcon#read 3, iclass 28, count 2 2006.286.04:09:09.59#ibcon#about to read 4, iclass 28, count 2 2006.286.04:09:09.59#ibcon#read 4, iclass 28, count 2 2006.286.04:09:09.59#ibcon#about to read 5, iclass 28, count 2 2006.286.04:09:09.59#ibcon#read 5, iclass 28, count 2 2006.286.04:09:09.59#ibcon#about to read 6, iclass 28, count 2 2006.286.04:09:09.59#ibcon#read 6, iclass 28, count 2 2006.286.04:09:09.59#ibcon#end of sib2, iclass 28, count 2 2006.286.04:09:09.59#ibcon#*mode == 0, iclass 28, count 2 2006.286.04:09:09.59#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.04:09:09.59#ibcon#[27=AT03-04\r\n] 2006.286.04:09:09.59#ibcon#*before write, iclass 28, count 2 2006.286.04:09:09.59#ibcon#enter sib2, iclass 28, count 2 2006.286.04:09:09.59#ibcon#flushed, iclass 28, count 2 2006.286.04:09:09.59#ibcon#about to write, iclass 28, count 2 2006.286.04:09:09.59#ibcon#wrote, iclass 28, count 2 2006.286.04:09:09.59#ibcon#about to read 3, iclass 28, count 2 2006.286.04:09:09.62#ibcon#read 3, iclass 28, count 2 2006.286.04:09:09.62#ibcon#about to read 4, iclass 28, count 2 2006.286.04:09:09.62#ibcon#read 4, iclass 28, count 2 2006.286.04:09:09.62#ibcon#about to read 5, iclass 28, count 2 2006.286.04:09:09.62#ibcon#read 5, iclass 28, count 2 2006.286.04:09:09.62#ibcon#about to read 6, iclass 28, count 2 2006.286.04:09:09.62#ibcon#read 6, iclass 28, count 2 2006.286.04:09:09.62#ibcon#end of sib2, iclass 28, count 2 2006.286.04:09:09.62#ibcon#*after write, iclass 28, count 2 2006.286.04:09:09.62#ibcon#*before return 0, iclass 28, count 2 2006.286.04:09:09.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:09:09.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:09:09.62#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.04:09:09.62#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:09.62#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:09:09.74#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:09:09.74#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:09:09.74#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:09:09.74#ibcon#first serial, iclass 28, count 0 2006.286.04:09:09.74#ibcon#enter sib2, iclass 28, count 0 2006.286.04:09:09.74#ibcon#flushed, iclass 28, count 0 2006.286.04:09:09.74#ibcon#about to write, iclass 28, count 0 2006.286.04:09:09.74#ibcon#wrote, iclass 28, count 0 2006.286.04:09:09.74#ibcon#about to read 3, iclass 28, count 0 2006.286.04:09:09.76#ibcon#read 3, iclass 28, count 0 2006.286.04:09:09.76#ibcon#about to read 4, iclass 28, count 0 2006.286.04:09:09.76#ibcon#read 4, iclass 28, count 0 2006.286.04:09:09.76#ibcon#about to read 5, iclass 28, count 0 2006.286.04:09:09.76#ibcon#read 5, iclass 28, count 0 2006.286.04:09:09.76#ibcon#about to read 6, iclass 28, count 0 2006.286.04:09:09.76#ibcon#read 6, iclass 28, count 0 2006.286.04:09:09.76#ibcon#end of sib2, iclass 28, count 0 2006.286.04:09:09.76#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:09:09.76#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:09:09.76#ibcon#[27=USB\r\n] 2006.286.04:09:09.76#ibcon#*before write, iclass 28, count 0 2006.286.04:09:09.76#ibcon#enter sib2, iclass 28, count 0 2006.286.04:09:09.76#ibcon#flushed, iclass 28, count 0 2006.286.04:09:09.76#ibcon#about to write, iclass 28, count 0 2006.286.04:09:09.76#ibcon#wrote, iclass 28, count 0 2006.286.04:09:09.76#ibcon#about to read 3, iclass 28, count 0 2006.286.04:09:09.79#ibcon#read 3, iclass 28, count 0 2006.286.04:09:09.79#ibcon#about to read 4, iclass 28, count 0 2006.286.04:09:09.79#ibcon#read 4, iclass 28, count 0 2006.286.04:09:09.79#ibcon#about to read 5, iclass 28, count 0 2006.286.04:09:09.79#ibcon#read 5, iclass 28, count 0 2006.286.04:09:09.79#ibcon#about to read 6, iclass 28, count 0 2006.286.04:09:09.79#ibcon#read 6, iclass 28, count 0 2006.286.04:09:09.79#ibcon#end of sib2, iclass 28, count 0 2006.286.04:09:09.79#ibcon#*after write, iclass 28, count 0 2006.286.04:09:09.79#ibcon#*before return 0, iclass 28, count 0 2006.286.04:09:09.79#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:09:09.79#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:09:09.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:09:09.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:09:09.79$vck44/vblo=4,679.99 2006.286.04:09:09.79#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:09:09.79#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:09:09.79#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:09.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:09:09.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:09:09.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:09:09.79#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:09:09.79#ibcon#first serial, iclass 30, count 0 2006.286.04:09:09.79#ibcon#enter sib2, iclass 30, count 0 2006.286.04:09:09.79#ibcon#flushed, iclass 30, count 0 2006.286.04:09:09.79#ibcon#about to write, iclass 30, count 0 2006.286.04:09:09.79#ibcon#wrote, iclass 30, count 0 2006.286.04:09:09.79#ibcon#about to read 3, iclass 30, count 0 2006.286.04:09:09.81#ibcon#read 3, iclass 30, count 0 2006.286.04:09:09.81#ibcon#about to read 4, iclass 30, count 0 2006.286.04:09:09.81#ibcon#read 4, iclass 30, count 0 2006.286.04:09:09.81#ibcon#about to read 5, iclass 30, count 0 2006.286.04:09:09.81#ibcon#read 5, iclass 30, count 0 2006.286.04:09:09.81#ibcon#about to read 6, iclass 30, count 0 2006.286.04:09:09.81#ibcon#read 6, iclass 30, count 0 2006.286.04:09:09.81#ibcon#end of sib2, iclass 30, count 0 2006.286.04:09:09.81#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:09:09.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:09:09.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:09:09.81#ibcon#*before write, iclass 30, count 0 2006.286.04:09:09.81#ibcon#enter sib2, iclass 30, count 0 2006.286.04:09:09.81#ibcon#flushed, iclass 30, count 0 2006.286.04:09:09.81#ibcon#about to write, iclass 30, count 0 2006.286.04:09:09.81#ibcon#wrote, iclass 30, count 0 2006.286.04:09:09.81#ibcon#about to read 3, iclass 30, count 0 2006.286.04:09:09.85#ibcon#read 3, iclass 30, count 0 2006.286.04:09:09.85#ibcon#about to read 4, iclass 30, count 0 2006.286.04:09:09.85#ibcon#read 4, iclass 30, count 0 2006.286.04:09:09.85#ibcon#about to read 5, iclass 30, count 0 2006.286.04:09:09.85#ibcon#read 5, iclass 30, count 0 2006.286.04:09:09.85#ibcon#about to read 6, iclass 30, count 0 2006.286.04:09:09.85#ibcon#read 6, iclass 30, count 0 2006.286.04:09:09.85#ibcon#end of sib2, iclass 30, count 0 2006.286.04:09:09.85#ibcon#*after write, iclass 30, count 0 2006.286.04:09:09.85#ibcon#*before return 0, iclass 30, count 0 2006.286.04:09:09.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:09:09.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:09:09.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:09:09.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:09:09.85$vck44/vb=4,5 2006.286.04:09:09.85#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.04:09:09.85#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.04:09:09.85#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:09.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:09:09.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:09:09.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:09:09.91#ibcon#enter wrdev, iclass 32, count 2 2006.286.04:09:09.91#ibcon#first serial, iclass 32, count 2 2006.286.04:09:09.91#ibcon#enter sib2, iclass 32, count 2 2006.286.04:09:09.91#ibcon#flushed, iclass 32, count 2 2006.286.04:09:09.91#ibcon#about to write, iclass 32, count 2 2006.286.04:09:09.91#ibcon#wrote, iclass 32, count 2 2006.286.04:09:09.91#ibcon#about to read 3, iclass 32, count 2 2006.286.04:09:09.93#ibcon#read 3, iclass 32, count 2 2006.286.04:09:09.93#ibcon#about to read 4, iclass 32, count 2 2006.286.04:09:09.93#ibcon#read 4, iclass 32, count 2 2006.286.04:09:09.93#ibcon#about to read 5, iclass 32, count 2 2006.286.04:09:09.93#ibcon#read 5, iclass 32, count 2 2006.286.04:09:09.93#ibcon#about to read 6, iclass 32, count 2 2006.286.04:09:09.93#ibcon#read 6, iclass 32, count 2 2006.286.04:09:09.93#ibcon#end of sib2, iclass 32, count 2 2006.286.04:09:09.93#ibcon#*mode == 0, iclass 32, count 2 2006.286.04:09:09.93#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.04:09:09.93#ibcon#[27=AT04-05\r\n] 2006.286.04:09:09.93#ibcon#*before write, iclass 32, count 2 2006.286.04:09:09.93#ibcon#enter sib2, iclass 32, count 2 2006.286.04:09:09.93#ibcon#flushed, iclass 32, count 2 2006.286.04:09:09.93#ibcon#about to write, iclass 32, count 2 2006.286.04:09:09.93#ibcon#wrote, iclass 32, count 2 2006.286.04:09:09.93#ibcon#about to read 3, iclass 32, count 2 2006.286.04:09:09.96#ibcon#read 3, iclass 32, count 2 2006.286.04:09:09.96#ibcon#about to read 4, iclass 32, count 2 2006.286.04:09:09.96#ibcon#read 4, iclass 32, count 2 2006.286.04:09:09.96#ibcon#about to read 5, iclass 32, count 2 2006.286.04:09:09.96#ibcon#read 5, iclass 32, count 2 2006.286.04:09:09.96#ibcon#about to read 6, iclass 32, count 2 2006.286.04:09:09.96#ibcon#read 6, iclass 32, count 2 2006.286.04:09:09.96#ibcon#end of sib2, iclass 32, count 2 2006.286.04:09:09.96#ibcon#*after write, iclass 32, count 2 2006.286.04:09:09.96#ibcon#*before return 0, iclass 32, count 2 2006.286.04:09:09.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:09:09.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:09:09.96#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.04:09:09.96#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:09.96#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:09:10.08#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:09:10.08#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:09:10.08#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:09:10.08#ibcon#first serial, iclass 32, count 0 2006.286.04:09:10.08#ibcon#enter sib2, iclass 32, count 0 2006.286.04:09:10.08#ibcon#flushed, iclass 32, count 0 2006.286.04:09:10.08#ibcon#about to write, iclass 32, count 0 2006.286.04:09:10.08#ibcon#wrote, iclass 32, count 0 2006.286.04:09:10.08#ibcon#about to read 3, iclass 32, count 0 2006.286.04:09:10.10#ibcon#read 3, iclass 32, count 0 2006.286.04:09:10.10#ibcon#about to read 4, iclass 32, count 0 2006.286.04:09:10.10#ibcon#read 4, iclass 32, count 0 2006.286.04:09:10.10#ibcon#about to read 5, iclass 32, count 0 2006.286.04:09:10.10#ibcon#read 5, iclass 32, count 0 2006.286.04:09:10.10#ibcon#about to read 6, iclass 32, count 0 2006.286.04:09:10.10#ibcon#read 6, iclass 32, count 0 2006.286.04:09:10.10#ibcon#end of sib2, iclass 32, count 0 2006.286.04:09:10.10#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:09:10.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:09:10.10#ibcon#[27=USB\r\n] 2006.286.04:09:10.10#ibcon#*before write, iclass 32, count 0 2006.286.04:09:10.10#ibcon#enter sib2, iclass 32, count 0 2006.286.04:09:10.10#ibcon#flushed, iclass 32, count 0 2006.286.04:09:10.10#ibcon#about to write, iclass 32, count 0 2006.286.04:09:10.10#ibcon#wrote, iclass 32, count 0 2006.286.04:09:10.10#ibcon#about to read 3, iclass 32, count 0 2006.286.04:09:10.13#ibcon#read 3, iclass 32, count 0 2006.286.04:09:10.13#ibcon#about to read 4, iclass 32, count 0 2006.286.04:09:10.13#ibcon#read 4, iclass 32, count 0 2006.286.04:09:10.13#ibcon#about to read 5, iclass 32, count 0 2006.286.04:09:10.13#ibcon#read 5, iclass 32, count 0 2006.286.04:09:10.13#ibcon#about to read 6, iclass 32, count 0 2006.286.04:09:10.13#ibcon#read 6, iclass 32, count 0 2006.286.04:09:10.13#ibcon#end of sib2, iclass 32, count 0 2006.286.04:09:10.13#ibcon#*after write, iclass 32, count 0 2006.286.04:09:10.13#ibcon#*before return 0, iclass 32, count 0 2006.286.04:09:10.13#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:09:10.13#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:09:10.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:09:10.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:09:10.13$vck44/vblo=5,709.99 2006.286.04:09:10.13#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.04:09:10.13#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.04:09:10.13#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:10.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:09:10.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:09:10.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:09:10.13#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:09:10.13#ibcon#first serial, iclass 34, count 0 2006.286.04:09:10.13#ibcon#enter sib2, iclass 34, count 0 2006.286.04:09:10.13#ibcon#flushed, iclass 34, count 0 2006.286.04:09:10.13#ibcon#about to write, iclass 34, count 0 2006.286.04:09:10.13#ibcon#wrote, iclass 34, count 0 2006.286.04:09:10.13#ibcon#about to read 3, iclass 34, count 0 2006.286.04:09:10.15#ibcon#read 3, iclass 34, count 0 2006.286.04:09:10.15#ibcon#about to read 4, iclass 34, count 0 2006.286.04:09:10.15#ibcon#read 4, iclass 34, count 0 2006.286.04:09:10.15#ibcon#about to read 5, iclass 34, count 0 2006.286.04:09:10.15#ibcon#read 5, iclass 34, count 0 2006.286.04:09:10.15#ibcon#about to read 6, iclass 34, count 0 2006.286.04:09:10.15#ibcon#read 6, iclass 34, count 0 2006.286.04:09:10.15#ibcon#end of sib2, iclass 34, count 0 2006.286.04:09:10.15#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:09:10.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:09:10.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:09:10.15#ibcon#*before write, iclass 34, count 0 2006.286.04:09:10.15#ibcon#enter sib2, iclass 34, count 0 2006.286.04:09:10.15#ibcon#flushed, iclass 34, count 0 2006.286.04:09:10.15#ibcon#about to write, iclass 34, count 0 2006.286.04:09:10.15#ibcon#wrote, iclass 34, count 0 2006.286.04:09:10.15#ibcon#about to read 3, iclass 34, count 0 2006.286.04:09:10.19#ibcon#read 3, iclass 34, count 0 2006.286.04:09:10.19#ibcon#about to read 4, iclass 34, count 0 2006.286.04:09:10.19#ibcon#read 4, iclass 34, count 0 2006.286.04:09:10.19#ibcon#about to read 5, iclass 34, count 0 2006.286.04:09:10.19#ibcon#read 5, iclass 34, count 0 2006.286.04:09:10.19#ibcon#about to read 6, iclass 34, count 0 2006.286.04:09:10.19#ibcon#read 6, iclass 34, count 0 2006.286.04:09:10.19#ibcon#end of sib2, iclass 34, count 0 2006.286.04:09:10.19#ibcon#*after write, iclass 34, count 0 2006.286.04:09:10.19#ibcon#*before return 0, iclass 34, count 0 2006.286.04:09:10.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:09:10.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:09:10.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:09:10.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:09:10.19$vck44/vb=5,4 2006.286.04:09:10.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.04:09:10.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.04:09:10.19#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:10.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:09:10.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:09:10.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:09:10.25#ibcon#enter wrdev, iclass 36, count 2 2006.286.04:09:10.25#ibcon#first serial, iclass 36, count 2 2006.286.04:09:10.25#ibcon#enter sib2, iclass 36, count 2 2006.286.04:09:10.25#ibcon#flushed, iclass 36, count 2 2006.286.04:09:10.25#ibcon#about to write, iclass 36, count 2 2006.286.04:09:10.25#ibcon#wrote, iclass 36, count 2 2006.286.04:09:10.25#ibcon#about to read 3, iclass 36, count 2 2006.286.04:09:10.27#ibcon#read 3, iclass 36, count 2 2006.286.04:09:10.27#ibcon#about to read 4, iclass 36, count 2 2006.286.04:09:10.27#ibcon#read 4, iclass 36, count 2 2006.286.04:09:10.27#ibcon#about to read 5, iclass 36, count 2 2006.286.04:09:10.27#ibcon#read 5, iclass 36, count 2 2006.286.04:09:10.27#ibcon#about to read 6, iclass 36, count 2 2006.286.04:09:10.27#ibcon#read 6, iclass 36, count 2 2006.286.04:09:10.27#ibcon#end of sib2, iclass 36, count 2 2006.286.04:09:10.27#ibcon#*mode == 0, iclass 36, count 2 2006.286.04:09:10.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.04:09:10.27#ibcon#[27=AT05-04\r\n] 2006.286.04:09:10.27#ibcon#*before write, iclass 36, count 2 2006.286.04:09:10.27#ibcon#enter sib2, iclass 36, count 2 2006.286.04:09:10.27#ibcon#flushed, iclass 36, count 2 2006.286.04:09:10.27#ibcon#about to write, iclass 36, count 2 2006.286.04:09:10.27#ibcon#wrote, iclass 36, count 2 2006.286.04:09:10.27#ibcon#about to read 3, iclass 36, count 2 2006.286.04:09:10.30#ibcon#read 3, iclass 36, count 2 2006.286.04:09:10.30#ibcon#about to read 4, iclass 36, count 2 2006.286.04:09:10.30#ibcon#read 4, iclass 36, count 2 2006.286.04:09:10.30#ibcon#about to read 5, iclass 36, count 2 2006.286.04:09:10.30#ibcon#read 5, iclass 36, count 2 2006.286.04:09:10.30#ibcon#about to read 6, iclass 36, count 2 2006.286.04:09:10.30#ibcon#read 6, iclass 36, count 2 2006.286.04:09:10.30#ibcon#end of sib2, iclass 36, count 2 2006.286.04:09:10.30#ibcon#*after write, iclass 36, count 2 2006.286.04:09:10.30#ibcon#*before return 0, iclass 36, count 2 2006.286.04:09:10.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:09:10.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:09:10.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.04:09:10.34#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:10.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:09:10.41#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:09:10.41#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:09:10.41#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:09:10.41#ibcon#first serial, iclass 36, count 0 2006.286.04:09:10.41#ibcon#enter sib2, iclass 36, count 0 2006.286.04:09:10.41#ibcon#flushed, iclass 36, count 0 2006.286.04:09:10.41#ibcon#about to write, iclass 36, count 0 2006.286.04:09:10.41#ibcon#wrote, iclass 36, count 0 2006.286.04:09:10.41#ibcon#about to read 3, iclass 36, count 0 2006.286.04:09:10.43#ibcon#read 3, iclass 36, count 0 2006.286.04:09:10.43#ibcon#about to read 4, iclass 36, count 0 2006.286.04:09:10.43#ibcon#read 4, iclass 36, count 0 2006.286.04:09:10.43#ibcon#about to read 5, iclass 36, count 0 2006.286.04:09:10.43#ibcon#read 5, iclass 36, count 0 2006.286.04:09:10.43#ibcon#about to read 6, iclass 36, count 0 2006.286.04:09:10.43#ibcon#read 6, iclass 36, count 0 2006.286.04:09:10.43#ibcon#end of sib2, iclass 36, count 0 2006.286.04:09:10.43#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:09:10.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:09:10.43#ibcon#[27=USB\r\n] 2006.286.04:09:10.43#ibcon#*before write, iclass 36, count 0 2006.286.04:09:10.43#ibcon#enter sib2, iclass 36, count 0 2006.286.04:09:10.43#ibcon#flushed, iclass 36, count 0 2006.286.04:09:10.43#ibcon#about to write, iclass 36, count 0 2006.286.04:09:10.43#ibcon#wrote, iclass 36, count 0 2006.286.04:09:10.43#ibcon#about to read 3, iclass 36, count 0 2006.286.04:09:10.46#ibcon#read 3, iclass 36, count 0 2006.286.04:09:10.46#ibcon#about to read 4, iclass 36, count 0 2006.286.04:09:10.46#ibcon#read 4, iclass 36, count 0 2006.286.04:09:10.46#ibcon#about to read 5, iclass 36, count 0 2006.286.04:09:10.46#ibcon#read 5, iclass 36, count 0 2006.286.04:09:10.46#ibcon#about to read 6, iclass 36, count 0 2006.286.04:09:10.46#ibcon#read 6, iclass 36, count 0 2006.286.04:09:10.46#ibcon#end of sib2, iclass 36, count 0 2006.286.04:09:10.46#ibcon#*after write, iclass 36, count 0 2006.286.04:09:10.46#ibcon#*before return 0, iclass 36, count 0 2006.286.04:09:10.46#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:09:10.46#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:09:10.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:09:10.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:09:10.46$vck44/vblo=6,719.99 2006.286.04:09:10.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.04:09:10.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.04:09:10.46#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:10.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:09:10.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:09:10.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:09:10.46#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:09:10.46#ibcon#first serial, iclass 38, count 0 2006.286.04:09:10.46#ibcon#enter sib2, iclass 38, count 0 2006.286.04:09:10.46#ibcon#flushed, iclass 38, count 0 2006.286.04:09:10.46#ibcon#about to write, iclass 38, count 0 2006.286.04:09:10.46#ibcon#wrote, iclass 38, count 0 2006.286.04:09:10.46#ibcon#about to read 3, iclass 38, count 0 2006.286.04:09:10.48#ibcon#read 3, iclass 38, count 0 2006.286.04:09:10.48#ibcon#about to read 4, iclass 38, count 0 2006.286.04:09:10.48#ibcon#read 4, iclass 38, count 0 2006.286.04:09:10.48#ibcon#about to read 5, iclass 38, count 0 2006.286.04:09:10.48#ibcon#read 5, iclass 38, count 0 2006.286.04:09:10.48#ibcon#about to read 6, iclass 38, count 0 2006.286.04:09:10.48#ibcon#read 6, iclass 38, count 0 2006.286.04:09:10.48#ibcon#end of sib2, iclass 38, count 0 2006.286.04:09:10.48#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:09:10.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:09:10.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:09:10.48#ibcon#*before write, iclass 38, count 0 2006.286.04:09:10.48#ibcon#enter sib2, iclass 38, count 0 2006.286.04:09:10.48#ibcon#flushed, iclass 38, count 0 2006.286.04:09:10.48#ibcon#about to write, iclass 38, count 0 2006.286.04:09:10.48#ibcon#wrote, iclass 38, count 0 2006.286.04:09:10.48#ibcon#about to read 3, iclass 38, count 0 2006.286.04:09:10.52#ibcon#read 3, iclass 38, count 0 2006.286.04:09:10.52#ibcon#about to read 4, iclass 38, count 0 2006.286.04:09:10.52#ibcon#read 4, iclass 38, count 0 2006.286.04:09:10.52#ibcon#about to read 5, iclass 38, count 0 2006.286.04:09:10.52#ibcon#read 5, iclass 38, count 0 2006.286.04:09:10.52#ibcon#about to read 6, iclass 38, count 0 2006.286.04:09:10.52#ibcon#read 6, iclass 38, count 0 2006.286.04:09:10.52#ibcon#end of sib2, iclass 38, count 0 2006.286.04:09:10.52#ibcon#*after write, iclass 38, count 0 2006.286.04:09:10.52#ibcon#*before return 0, iclass 38, count 0 2006.286.04:09:10.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:09:10.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:09:10.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:09:10.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:09:10.52$vck44/vb=6,3 2006.286.04:09:10.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.04:09:10.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.04:09:10.52#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:10.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:09:10.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:09:10.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:09:10.58#ibcon#enter wrdev, iclass 40, count 2 2006.286.04:09:10.58#ibcon#first serial, iclass 40, count 2 2006.286.04:09:10.58#ibcon#enter sib2, iclass 40, count 2 2006.286.04:09:10.58#ibcon#flushed, iclass 40, count 2 2006.286.04:09:10.58#ibcon#about to write, iclass 40, count 2 2006.286.04:09:10.58#ibcon#wrote, iclass 40, count 2 2006.286.04:09:10.58#ibcon#about to read 3, iclass 40, count 2 2006.286.04:09:10.60#ibcon#read 3, iclass 40, count 2 2006.286.04:09:10.60#ibcon#about to read 4, iclass 40, count 2 2006.286.04:09:10.60#ibcon#read 4, iclass 40, count 2 2006.286.04:09:10.60#ibcon#about to read 5, iclass 40, count 2 2006.286.04:09:10.60#ibcon#read 5, iclass 40, count 2 2006.286.04:09:10.60#ibcon#about to read 6, iclass 40, count 2 2006.286.04:09:10.60#ibcon#read 6, iclass 40, count 2 2006.286.04:09:10.60#ibcon#end of sib2, iclass 40, count 2 2006.286.04:09:10.60#ibcon#*mode == 0, iclass 40, count 2 2006.286.04:09:10.60#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.04:09:10.60#ibcon#[27=AT06-03\r\n] 2006.286.04:09:10.60#ibcon#*before write, iclass 40, count 2 2006.286.04:09:10.60#ibcon#enter sib2, iclass 40, count 2 2006.286.04:09:10.60#ibcon#flushed, iclass 40, count 2 2006.286.04:09:10.60#ibcon#about to write, iclass 40, count 2 2006.286.04:09:10.60#ibcon#wrote, iclass 40, count 2 2006.286.04:09:10.60#ibcon#about to read 3, iclass 40, count 2 2006.286.04:09:10.63#ibcon#read 3, iclass 40, count 2 2006.286.04:09:10.63#ibcon#about to read 4, iclass 40, count 2 2006.286.04:09:10.63#ibcon#read 4, iclass 40, count 2 2006.286.04:09:10.63#ibcon#about to read 5, iclass 40, count 2 2006.286.04:09:10.63#ibcon#read 5, iclass 40, count 2 2006.286.04:09:10.63#ibcon#about to read 6, iclass 40, count 2 2006.286.04:09:10.63#ibcon#read 6, iclass 40, count 2 2006.286.04:09:10.63#ibcon#end of sib2, iclass 40, count 2 2006.286.04:09:10.63#ibcon#*after write, iclass 40, count 2 2006.286.04:09:10.63#ibcon#*before return 0, iclass 40, count 2 2006.286.04:09:10.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:09:10.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:09:10.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.04:09:10.63#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:10.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:09:10.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:09:10.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:09:10.75#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:09:10.75#ibcon#first serial, iclass 40, count 0 2006.286.04:09:10.75#ibcon#enter sib2, iclass 40, count 0 2006.286.04:09:10.75#ibcon#flushed, iclass 40, count 0 2006.286.04:09:10.75#ibcon#about to write, iclass 40, count 0 2006.286.04:09:10.75#ibcon#wrote, iclass 40, count 0 2006.286.04:09:10.75#ibcon#about to read 3, iclass 40, count 0 2006.286.04:09:10.77#ibcon#read 3, iclass 40, count 0 2006.286.04:09:10.77#ibcon#about to read 4, iclass 40, count 0 2006.286.04:09:10.77#ibcon#read 4, iclass 40, count 0 2006.286.04:09:10.77#ibcon#about to read 5, iclass 40, count 0 2006.286.04:09:10.77#ibcon#read 5, iclass 40, count 0 2006.286.04:09:10.77#ibcon#about to read 6, iclass 40, count 0 2006.286.04:09:10.77#ibcon#read 6, iclass 40, count 0 2006.286.04:09:10.77#ibcon#end of sib2, iclass 40, count 0 2006.286.04:09:10.77#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:09:10.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:09:10.77#ibcon#[27=USB\r\n] 2006.286.04:09:10.77#ibcon#*before write, iclass 40, count 0 2006.286.04:09:10.77#ibcon#enter sib2, iclass 40, count 0 2006.286.04:09:10.77#ibcon#flushed, iclass 40, count 0 2006.286.04:09:10.77#ibcon#about to write, iclass 40, count 0 2006.286.04:09:10.77#ibcon#wrote, iclass 40, count 0 2006.286.04:09:10.77#ibcon#about to read 3, iclass 40, count 0 2006.286.04:09:10.80#ibcon#read 3, iclass 40, count 0 2006.286.04:09:10.80#ibcon#about to read 4, iclass 40, count 0 2006.286.04:09:10.80#ibcon#read 4, iclass 40, count 0 2006.286.04:09:10.80#ibcon#about to read 5, iclass 40, count 0 2006.286.04:09:10.80#ibcon#read 5, iclass 40, count 0 2006.286.04:09:10.80#ibcon#about to read 6, iclass 40, count 0 2006.286.04:09:10.80#ibcon#read 6, iclass 40, count 0 2006.286.04:09:10.80#ibcon#end of sib2, iclass 40, count 0 2006.286.04:09:10.80#ibcon#*after write, iclass 40, count 0 2006.286.04:09:10.80#ibcon#*before return 0, iclass 40, count 0 2006.286.04:09:10.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:09:10.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:09:10.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:09:10.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:09:10.80$vck44/vblo=7,734.99 2006.286.04:09:10.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.04:09:10.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.04:09:10.80#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:10.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:09:10.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:09:10.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:09:10.80#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:09:10.80#ibcon#first serial, iclass 4, count 0 2006.286.04:09:10.80#ibcon#enter sib2, iclass 4, count 0 2006.286.04:09:10.80#ibcon#flushed, iclass 4, count 0 2006.286.04:09:10.80#ibcon#about to write, iclass 4, count 0 2006.286.04:09:10.80#ibcon#wrote, iclass 4, count 0 2006.286.04:09:10.80#ibcon#about to read 3, iclass 4, count 0 2006.286.04:09:10.82#ibcon#read 3, iclass 4, count 0 2006.286.04:09:10.82#ibcon#about to read 4, iclass 4, count 0 2006.286.04:09:10.82#ibcon#read 4, iclass 4, count 0 2006.286.04:09:10.82#ibcon#about to read 5, iclass 4, count 0 2006.286.04:09:10.82#ibcon#read 5, iclass 4, count 0 2006.286.04:09:10.82#ibcon#about to read 6, iclass 4, count 0 2006.286.04:09:10.82#ibcon#read 6, iclass 4, count 0 2006.286.04:09:10.82#ibcon#end of sib2, iclass 4, count 0 2006.286.04:09:10.82#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:09:10.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:09:10.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:09:10.82#ibcon#*before write, iclass 4, count 0 2006.286.04:09:10.82#ibcon#enter sib2, iclass 4, count 0 2006.286.04:09:10.82#ibcon#flushed, iclass 4, count 0 2006.286.04:09:10.82#ibcon#about to write, iclass 4, count 0 2006.286.04:09:10.82#ibcon#wrote, iclass 4, count 0 2006.286.04:09:10.82#ibcon#about to read 3, iclass 4, count 0 2006.286.04:09:10.86#ibcon#read 3, iclass 4, count 0 2006.286.04:09:10.86#ibcon#about to read 4, iclass 4, count 0 2006.286.04:09:10.86#ibcon#read 4, iclass 4, count 0 2006.286.04:09:10.86#ibcon#about to read 5, iclass 4, count 0 2006.286.04:09:10.86#ibcon#read 5, iclass 4, count 0 2006.286.04:09:10.86#ibcon#about to read 6, iclass 4, count 0 2006.286.04:09:10.86#ibcon#read 6, iclass 4, count 0 2006.286.04:09:10.86#ibcon#end of sib2, iclass 4, count 0 2006.286.04:09:10.86#ibcon#*after write, iclass 4, count 0 2006.286.04:09:10.86#ibcon#*before return 0, iclass 4, count 0 2006.286.04:09:10.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:09:10.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:09:10.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:09:10.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:09:10.86$vck44/vb=7,4 2006.286.04:09:10.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.04:09:10.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.04:09:10.86#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:10.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:09:10.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:09:10.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:09:10.92#ibcon#enter wrdev, iclass 6, count 2 2006.286.04:09:10.92#ibcon#first serial, iclass 6, count 2 2006.286.04:09:10.92#ibcon#enter sib2, iclass 6, count 2 2006.286.04:09:10.92#ibcon#flushed, iclass 6, count 2 2006.286.04:09:10.92#ibcon#about to write, iclass 6, count 2 2006.286.04:09:10.92#ibcon#wrote, iclass 6, count 2 2006.286.04:09:10.92#ibcon#about to read 3, iclass 6, count 2 2006.286.04:09:10.94#ibcon#read 3, iclass 6, count 2 2006.286.04:09:10.94#ibcon#about to read 4, iclass 6, count 2 2006.286.04:09:10.94#ibcon#read 4, iclass 6, count 2 2006.286.04:09:10.94#ibcon#about to read 5, iclass 6, count 2 2006.286.04:09:10.94#ibcon#read 5, iclass 6, count 2 2006.286.04:09:10.94#ibcon#about to read 6, iclass 6, count 2 2006.286.04:09:10.94#ibcon#read 6, iclass 6, count 2 2006.286.04:09:10.94#ibcon#end of sib2, iclass 6, count 2 2006.286.04:09:10.94#ibcon#*mode == 0, iclass 6, count 2 2006.286.04:09:10.94#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.04:09:10.94#ibcon#[27=AT07-04\r\n] 2006.286.04:09:10.94#ibcon#*before write, iclass 6, count 2 2006.286.04:09:10.94#ibcon#enter sib2, iclass 6, count 2 2006.286.04:09:10.94#ibcon#flushed, iclass 6, count 2 2006.286.04:09:10.94#ibcon#about to write, iclass 6, count 2 2006.286.04:09:10.94#ibcon#wrote, iclass 6, count 2 2006.286.04:09:10.94#ibcon#about to read 3, iclass 6, count 2 2006.286.04:09:10.97#ibcon#read 3, iclass 6, count 2 2006.286.04:09:10.97#ibcon#about to read 4, iclass 6, count 2 2006.286.04:09:10.97#ibcon#read 4, iclass 6, count 2 2006.286.04:09:10.97#ibcon#about to read 5, iclass 6, count 2 2006.286.04:09:10.97#ibcon#read 5, iclass 6, count 2 2006.286.04:09:10.97#ibcon#about to read 6, iclass 6, count 2 2006.286.04:09:10.97#ibcon#read 6, iclass 6, count 2 2006.286.04:09:10.97#ibcon#end of sib2, iclass 6, count 2 2006.286.04:09:10.97#ibcon#*after write, iclass 6, count 2 2006.286.04:09:10.97#ibcon#*before return 0, iclass 6, count 2 2006.286.04:09:10.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:09:10.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:09:10.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.04:09:10.97#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:10.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:09:11.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:09:11.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:09:11.09#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:09:11.09#ibcon#first serial, iclass 6, count 0 2006.286.04:09:11.09#ibcon#enter sib2, iclass 6, count 0 2006.286.04:09:11.09#ibcon#flushed, iclass 6, count 0 2006.286.04:09:11.09#ibcon#about to write, iclass 6, count 0 2006.286.04:09:11.09#ibcon#wrote, iclass 6, count 0 2006.286.04:09:11.09#ibcon#about to read 3, iclass 6, count 0 2006.286.04:09:11.11#ibcon#read 3, iclass 6, count 0 2006.286.04:09:11.11#ibcon#about to read 4, iclass 6, count 0 2006.286.04:09:11.11#ibcon#read 4, iclass 6, count 0 2006.286.04:09:11.11#ibcon#about to read 5, iclass 6, count 0 2006.286.04:09:11.11#ibcon#read 5, iclass 6, count 0 2006.286.04:09:11.11#ibcon#about to read 6, iclass 6, count 0 2006.286.04:09:11.11#ibcon#read 6, iclass 6, count 0 2006.286.04:09:11.11#ibcon#end of sib2, iclass 6, count 0 2006.286.04:09:11.11#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:09:11.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:09:11.11#ibcon#[27=USB\r\n] 2006.286.04:09:11.11#ibcon#*before write, iclass 6, count 0 2006.286.04:09:11.11#ibcon#enter sib2, iclass 6, count 0 2006.286.04:09:11.11#ibcon#flushed, iclass 6, count 0 2006.286.04:09:11.11#ibcon#about to write, iclass 6, count 0 2006.286.04:09:11.11#ibcon#wrote, iclass 6, count 0 2006.286.04:09:11.11#ibcon#about to read 3, iclass 6, count 0 2006.286.04:09:11.14#ibcon#read 3, iclass 6, count 0 2006.286.04:09:11.14#ibcon#about to read 4, iclass 6, count 0 2006.286.04:09:11.14#ibcon#read 4, iclass 6, count 0 2006.286.04:09:11.14#ibcon#about to read 5, iclass 6, count 0 2006.286.04:09:11.14#ibcon#read 5, iclass 6, count 0 2006.286.04:09:11.14#ibcon#about to read 6, iclass 6, count 0 2006.286.04:09:11.14#ibcon#read 6, iclass 6, count 0 2006.286.04:09:11.14#ibcon#end of sib2, iclass 6, count 0 2006.286.04:09:11.14#ibcon#*after write, iclass 6, count 0 2006.286.04:09:11.14#ibcon#*before return 0, iclass 6, count 0 2006.286.04:09:11.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:09:11.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:09:11.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:09:11.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:09:11.14$vck44/vblo=8,744.99 2006.286.04:09:11.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.04:09:11.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.04:09:11.14#ibcon#ireg 17 cls_cnt 0 2006.286.04:09:11.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:09:11.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:09:11.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:09:11.14#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:09:11.14#ibcon#first serial, iclass 10, count 0 2006.286.04:09:11.14#ibcon#enter sib2, iclass 10, count 0 2006.286.04:09:11.14#ibcon#flushed, iclass 10, count 0 2006.286.04:09:11.14#ibcon#about to write, iclass 10, count 0 2006.286.04:09:11.14#ibcon#wrote, iclass 10, count 0 2006.286.04:09:11.14#ibcon#about to read 3, iclass 10, count 0 2006.286.04:09:11.16#ibcon#read 3, iclass 10, count 0 2006.286.04:09:11.16#ibcon#about to read 4, iclass 10, count 0 2006.286.04:09:11.16#ibcon#read 4, iclass 10, count 0 2006.286.04:09:11.16#ibcon#about to read 5, iclass 10, count 0 2006.286.04:09:11.16#ibcon#read 5, iclass 10, count 0 2006.286.04:09:11.16#ibcon#about to read 6, iclass 10, count 0 2006.286.04:09:11.16#ibcon#read 6, iclass 10, count 0 2006.286.04:09:11.16#ibcon#end of sib2, iclass 10, count 0 2006.286.04:09:11.16#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:09:11.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:09:11.16#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:09:11.16#ibcon#*before write, iclass 10, count 0 2006.286.04:09:11.16#ibcon#enter sib2, iclass 10, count 0 2006.286.04:09:11.16#ibcon#flushed, iclass 10, count 0 2006.286.04:09:11.16#ibcon#about to write, iclass 10, count 0 2006.286.04:09:11.16#ibcon#wrote, iclass 10, count 0 2006.286.04:09:11.16#ibcon#about to read 3, iclass 10, count 0 2006.286.04:09:11.20#ibcon#read 3, iclass 10, count 0 2006.286.04:09:11.20#ibcon#about to read 4, iclass 10, count 0 2006.286.04:09:11.20#ibcon#read 4, iclass 10, count 0 2006.286.04:09:11.20#ibcon#about to read 5, iclass 10, count 0 2006.286.04:09:11.20#ibcon#read 5, iclass 10, count 0 2006.286.04:09:11.20#ibcon#about to read 6, iclass 10, count 0 2006.286.04:09:11.20#ibcon#read 6, iclass 10, count 0 2006.286.04:09:11.20#ibcon#end of sib2, iclass 10, count 0 2006.286.04:09:11.20#ibcon#*after write, iclass 10, count 0 2006.286.04:09:11.20#ibcon#*before return 0, iclass 10, count 0 2006.286.04:09:11.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:09:11.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:09:11.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:09:11.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:09:11.20$vck44/vb=8,4 2006.286.04:09:11.20#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.04:09:11.20#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.04:09:11.20#ibcon#ireg 11 cls_cnt 2 2006.286.04:09:11.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:09:11.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:09:11.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:09:11.26#ibcon#enter wrdev, iclass 12, count 2 2006.286.04:09:11.26#ibcon#first serial, iclass 12, count 2 2006.286.04:09:11.26#ibcon#enter sib2, iclass 12, count 2 2006.286.04:09:11.26#ibcon#flushed, iclass 12, count 2 2006.286.04:09:11.26#ibcon#about to write, iclass 12, count 2 2006.286.04:09:11.26#ibcon#wrote, iclass 12, count 2 2006.286.04:09:11.26#ibcon#about to read 3, iclass 12, count 2 2006.286.04:09:11.28#ibcon#read 3, iclass 12, count 2 2006.286.04:09:11.28#ibcon#about to read 4, iclass 12, count 2 2006.286.04:09:11.28#ibcon#read 4, iclass 12, count 2 2006.286.04:09:11.28#ibcon#about to read 5, iclass 12, count 2 2006.286.04:09:11.28#ibcon#read 5, iclass 12, count 2 2006.286.04:09:11.28#ibcon#about to read 6, iclass 12, count 2 2006.286.04:09:11.28#ibcon#read 6, iclass 12, count 2 2006.286.04:09:11.28#ibcon#end of sib2, iclass 12, count 2 2006.286.04:09:11.28#ibcon#*mode == 0, iclass 12, count 2 2006.286.04:09:11.28#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.04:09:11.28#ibcon#[27=AT08-04\r\n] 2006.286.04:09:11.28#ibcon#*before write, iclass 12, count 2 2006.286.04:09:11.28#ibcon#enter sib2, iclass 12, count 2 2006.286.04:09:11.28#ibcon#flushed, iclass 12, count 2 2006.286.04:09:11.28#ibcon#about to write, iclass 12, count 2 2006.286.04:09:11.28#ibcon#wrote, iclass 12, count 2 2006.286.04:09:11.28#ibcon#about to read 3, iclass 12, count 2 2006.286.04:09:11.31#ibcon#read 3, iclass 12, count 2 2006.286.04:09:11.31#ibcon#about to read 4, iclass 12, count 2 2006.286.04:09:11.31#ibcon#read 4, iclass 12, count 2 2006.286.04:09:11.31#ibcon#about to read 5, iclass 12, count 2 2006.286.04:09:11.31#ibcon#read 5, iclass 12, count 2 2006.286.04:09:11.31#ibcon#about to read 6, iclass 12, count 2 2006.286.04:09:11.31#ibcon#read 6, iclass 12, count 2 2006.286.04:09:11.31#ibcon#end of sib2, iclass 12, count 2 2006.286.04:09:11.31#ibcon#*after write, iclass 12, count 2 2006.286.04:09:11.31#ibcon#*before return 0, iclass 12, count 2 2006.286.04:09:11.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:09:11.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:09:11.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.04:09:11.39#ibcon#ireg 7 cls_cnt 0 2006.286.04:09:11.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:09:11.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:09:11.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:09:11.42#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:09:11.42#ibcon#first serial, iclass 12, count 0 2006.286.04:09:11.42#ibcon#enter sib2, iclass 12, count 0 2006.286.04:09:11.42#ibcon#flushed, iclass 12, count 0 2006.286.04:09:11.42#ibcon#about to write, iclass 12, count 0 2006.286.04:09:11.42#ibcon#wrote, iclass 12, count 0 2006.286.04:09:11.42#ibcon#about to read 3, iclass 12, count 0 2006.286.04:09:11.44#ibcon#read 3, iclass 12, count 0 2006.286.04:09:11.44#ibcon#about to read 4, iclass 12, count 0 2006.286.04:09:11.44#ibcon#read 4, iclass 12, count 0 2006.286.04:09:11.44#ibcon#about to read 5, iclass 12, count 0 2006.286.04:09:11.44#ibcon#read 5, iclass 12, count 0 2006.286.04:09:11.44#ibcon#about to read 6, iclass 12, count 0 2006.286.04:09:11.44#ibcon#read 6, iclass 12, count 0 2006.286.04:09:11.44#ibcon#end of sib2, iclass 12, count 0 2006.286.04:09:11.44#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:09:11.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:09:11.44#ibcon#[27=USB\r\n] 2006.286.04:09:11.44#ibcon#*before write, iclass 12, count 0 2006.286.04:09:11.44#ibcon#enter sib2, iclass 12, count 0 2006.286.04:09:11.44#ibcon#flushed, iclass 12, count 0 2006.286.04:09:11.44#ibcon#about to write, iclass 12, count 0 2006.286.04:09:11.44#ibcon#wrote, iclass 12, count 0 2006.286.04:09:11.44#ibcon#about to read 3, iclass 12, count 0 2006.286.04:09:11.47#ibcon#read 3, iclass 12, count 0 2006.286.04:09:11.47#ibcon#about to read 4, iclass 12, count 0 2006.286.04:09:11.47#ibcon#read 4, iclass 12, count 0 2006.286.04:09:11.47#ibcon#about to read 5, iclass 12, count 0 2006.286.04:09:11.47#ibcon#read 5, iclass 12, count 0 2006.286.04:09:11.47#ibcon#about to read 6, iclass 12, count 0 2006.286.04:09:11.47#ibcon#read 6, iclass 12, count 0 2006.286.04:09:11.47#ibcon#end of sib2, iclass 12, count 0 2006.286.04:09:11.47#ibcon#*after write, iclass 12, count 0 2006.286.04:09:11.47#ibcon#*before return 0, iclass 12, count 0 2006.286.04:09:11.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:09:11.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:09:11.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:09:11.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:09:11.47$vck44/vabw=wide 2006.286.04:09:11.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.04:09:11.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.04:09:11.47#ibcon#ireg 8 cls_cnt 0 2006.286.04:09:11.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:09:11.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:09:11.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:09:11.47#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:09:11.47#ibcon#first serial, iclass 14, count 0 2006.286.04:09:11.47#ibcon#enter sib2, iclass 14, count 0 2006.286.04:09:11.47#ibcon#flushed, iclass 14, count 0 2006.286.04:09:11.47#ibcon#about to write, iclass 14, count 0 2006.286.04:09:11.47#ibcon#wrote, iclass 14, count 0 2006.286.04:09:11.47#ibcon#about to read 3, iclass 14, count 0 2006.286.04:09:11.49#ibcon#read 3, iclass 14, count 0 2006.286.04:09:11.49#ibcon#about to read 4, iclass 14, count 0 2006.286.04:09:11.49#ibcon#read 4, iclass 14, count 0 2006.286.04:09:11.49#ibcon#about to read 5, iclass 14, count 0 2006.286.04:09:11.49#ibcon#read 5, iclass 14, count 0 2006.286.04:09:11.49#ibcon#about to read 6, iclass 14, count 0 2006.286.04:09:11.49#ibcon#read 6, iclass 14, count 0 2006.286.04:09:11.49#ibcon#end of sib2, iclass 14, count 0 2006.286.04:09:11.49#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:09:11.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:09:11.49#ibcon#[25=BW32\r\n] 2006.286.04:09:11.49#ibcon#*before write, iclass 14, count 0 2006.286.04:09:11.49#ibcon#enter sib2, iclass 14, count 0 2006.286.04:09:11.49#ibcon#flushed, iclass 14, count 0 2006.286.04:09:11.49#ibcon#about to write, iclass 14, count 0 2006.286.04:09:11.49#ibcon#wrote, iclass 14, count 0 2006.286.04:09:11.49#ibcon#about to read 3, iclass 14, count 0 2006.286.04:09:11.52#ibcon#read 3, iclass 14, count 0 2006.286.04:09:11.52#ibcon#about to read 4, iclass 14, count 0 2006.286.04:09:11.52#ibcon#read 4, iclass 14, count 0 2006.286.04:09:11.52#ibcon#about to read 5, iclass 14, count 0 2006.286.04:09:11.52#ibcon#read 5, iclass 14, count 0 2006.286.04:09:11.52#ibcon#about to read 6, iclass 14, count 0 2006.286.04:09:11.52#ibcon#read 6, iclass 14, count 0 2006.286.04:09:11.52#ibcon#end of sib2, iclass 14, count 0 2006.286.04:09:11.52#ibcon#*after write, iclass 14, count 0 2006.286.04:09:11.52#ibcon#*before return 0, iclass 14, count 0 2006.286.04:09:11.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:09:11.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:09:11.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:09:11.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:09:11.52$vck44/vbbw=wide 2006.286.04:09:11.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.04:09:11.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.04:09:11.52#ibcon#ireg 8 cls_cnt 0 2006.286.04:09:11.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:09:11.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:09:11.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:09:11.59#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:09:11.59#ibcon#first serial, iclass 16, count 0 2006.286.04:09:11.59#ibcon#enter sib2, iclass 16, count 0 2006.286.04:09:11.59#ibcon#flushed, iclass 16, count 0 2006.286.04:09:11.59#ibcon#about to write, iclass 16, count 0 2006.286.04:09:11.59#ibcon#wrote, iclass 16, count 0 2006.286.04:09:11.59#ibcon#about to read 3, iclass 16, count 0 2006.286.04:09:11.61#ibcon#read 3, iclass 16, count 0 2006.286.04:09:11.61#ibcon#about to read 4, iclass 16, count 0 2006.286.04:09:11.61#ibcon#read 4, iclass 16, count 0 2006.286.04:09:11.61#ibcon#about to read 5, iclass 16, count 0 2006.286.04:09:11.61#ibcon#read 5, iclass 16, count 0 2006.286.04:09:11.61#ibcon#about to read 6, iclass 16, count 0 2006.286.04:09:11.61#ibcon#read 6, iclass 16, count 0 2006.286.04:09:11.61#ibcon#end of sib2, iclass 16, count 0 2006.286.04:09:11.61#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:09:11.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:09:11.61#ibcon#[27=BW32\r\n] 2006.286.04:09:11.61#ibcon#*before write, iclass 16, count 0 2006.286.04:09:11.61#ibcon#enter sib2, iclass 16, count 0 2006.286.04:09:11.61#ibcon#flushed, iclass 16, count 0 2006.286.04:09:11.61#ibcon#about to write, iclass 16, count 0 2006.286.04:09:11.61#ibcon#wrote, iclass 16, count 0 2006.286.04:09:11.61#ibcon#about to read 3, iclass 16, count 0 2006.286.04:09:11.64#ibcon#read 3, iclass 16, count 0 2006.286.04:09:11.64#ibcon#about to read 4, iclass 16, count 0 2006.286.04:09:11.64#ibcon#read 4, iclass 16, count 0 2006.286.04:09:11.64#ibcon#about to read 5, iclass 16, count 0 2006.286.04:09:11.64#ibcon#read 5, iclass 16, count 0 2006.286.04:09:11.64#ibcon#about to read 6, iclass 16, count 0 2006.286.04:09:11.64#ibcon#read 6, iclass 16, count 0 2006.286.04:09:11.64#ibcon#end of sib2, iclass 16, count 0 2006.286.04:09:11.64#ibcon#*after write, iclass 16, count 0 2006.286.04:09:11.64#ibcon#*before return 0, iclass 16, count 0 2006.286.04:09:11.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:09:11.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:09:11.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:09:11.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:09:11.64$setupk4/ifdk4 2006.286.04:09:11.64$ifdk4/lo= 2006.286.04:09:11.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:09:11.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:09:11.64$ifdk4/patch= 2006.286.04:09:11.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:09:11.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:09:11.64$setupk4/!*+20s 2006.286.04:09:14.93#abcon#<5=/04 4.3 7.8 21.85 751014.9\r\n> 2006.286.04:09:14.95#abcon#{5=INTERFACE CLEAR} 2006.286.04:09:15.01#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:09:22.14#trakl#Source acquired 2006.286.04:09:24.14#flagr#flagr/antenna,acquired 2006.286.04:09:25.10#abcon#<5=/04 4.3 7.8 21.84 751014.9\r\n> 2006.286.04:09:25.12#abcon#{5=INTERFACE CLEAR} 2006.286.04:09:25.18#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:09:25.62$setupk4/"tpicd 2006.286.04:09:25.62$setupk4/echo=off 2006.286.04:09:25.62$setupk4/xlog=off 2006.286.04:09:25.62:!2006.286.04:09:54 2006.286.04:09:54.00:preob 2006.286.04:09:55.14/onsource/TRACKING 2006.286.04:09:55.14:!2006.286.04:10:04 2006.286.04:10:04.00:"tape 2006.286.04:10:04.00:"st=record 2006.286.04:10:04.00:data_valid=on 2006.286.04:10:04.00:midob 2006.286.04:10:04.14/onsource/TRACKING 2006.286.04:10:04.14/wx/21.83,1014.9,77 2006.286.04:10:04.20/cable/+6.4957E-03 2006.286.04:10:05.29/va/01,07,usb,yes,40,44 2006.286.04:10:05.29/va/02,06,usb,yes,40,41 2006.286.04:10:05.29/va/03,07,usb,yes,40,42 2006.286.04:10:05.29/va/04,06,usb,yes,42,44 2006.286.04:10:05.29/va/05,03,usb,yes,41,42 2006.286.04:10:05.29/va/06,04,usb,yes,37,37 2006.286.04:10:05.29/va/07,04,usb,yes,38,39 2006.286.04:10:05.29/va/08,03,usb,yes,39,47 2006.286.04:10:05.52/valo/01,524.99,yes,locked 2006.286.04:10:05.52/valo/02,534.99,yes,locked 2006.286.04:10:05.52/valo/03,564.99,yes,locked 2006.286.04:10:05.52/valo/04,624.99,yes,locked 2006.286.04:10:05.52/valo/05,734.99,yes,locked 2006.286.04:10:05.52/valo/06,814.99,yes,locked 2006.286.04:10:05.52/valo/07,864.99,yes,locked 2006.286.04:10:05.52/valo/08,884.99,yes,locked 2006.286.04:10:06.61/vb/01,04,usb,yes,35,33 2006.286.04:10:06.61/vb/02,05,usb,yes,34,33 2006.286.04:10:06.61/vb/03,04,usb,yes,35,38 2006.286.04:10:06.61/vb/04,05,usb,yes,35,34 2006.286.04:10:06.61/vb/05,04,usb,yes,31,34 2006.286.04:10:06.61/vb/06,03,usb,yes,44,39 2006.286.04:10:06.61/vb/07,04,usb,yes,36,36 2006.286.04:10:06.61/vb/08,04,usb,yes,33,37 2006.286.04:10:06.85/vblo/01,629.99,yes,locked 2006.286.04:10:06.85/vblo/02,634.99,yes,locked 2006.286.04:10:06.85/vblo/03,649.99,yes,locked 2006.286.04:10:06.85/vblo/04,679.99,yes,locked 2006.286.04:10:06.85/vblo/05,709.99,yes,locked 2006.286.04:10:06.85/vblo/06,719.99,yes,locked 2006.286.04:10:06.85/vblo/07,734.99,yes,locked 2006.286.04:10:06.85/vblo/08,744.99,yes,locked 2006.286.04:10:07.00/vabw/8 2006.286.04:10:07.15/vbbw/8 2006.286.04:10:07.24/xfe/off,on,12.0 2006.286.04:10:07.63/ifatt/23,28,28,28 2006.286.04:10:08.07/fmout-gps/S +2.58E-07 2006.286.04:10:08.09:!2006.286.04:15:54 2006.286.04:15:54.00:data_valid=off 2006.286.04:15:54.00:"et 2006.286.04:15:54.00:!+3s 2006.286.04:15:57.01:"tape 2006.286.04:15:57.01:postob 2006.286.04:15:57.23/cable/+6.4958E-03 2006.286.04:15:57.23/wx/21.90,1014.8,76 2006.286.04:15:58.08/fmout-gps/S +2.65E-07 2006.286.04:15:58.08:scan_name=286-0418,jd0610,40 2006.286.04:15:58.08:source=oj287,085448.87,200630.6,2000.0,ccw 2006.286.04:15:59.13#flagr#flagr/antenna,new-source 2006.286.04:15:59.14:checkk5 2006.286.04:15:59.59/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:15:59.97/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:16:00.43/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:16:00.83/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:16:01.25/chk_obsdata//k5ts1/T2860410??a.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.286.04:16:01.72/chk_obsdata//k5ts2/T2860410??b.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.286.04:16:02.10/chk_obsdata//k5ts3/T2860410??c.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.286.04:16:02.62/chk_obsdata//k5ts4/T2860410??d.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.286.04:16:03.53/k5log//k5ts1_log_newline 2006.286.04:16:04.36/k5log//k5ts2_log_newline 2006.286.04:16:05.29/k5log//k5ts3_log_newline 2006.286.04:16:06.11/k5log//k5ts4_log_newline 2006.286.04:16:06.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:16:06.13:setupk4=1 2006.286.04:16:06.14$setupk4/echo=on 2006.286.04:16:06.14$setupk4/pcalon 2006.286.04:16:06.14$pcalon/"no phase cal control is implemented here 2006.286.04:16:06.14$setupk4/"tpicd=stop 2006.286.04:16:06.14$setupk4/"rec=synch_on 2006.286.04:16:06.14$setupk4/"rec_mode=128 2006.286.04:16:06.14$setupk4/!* 2006.286.04:16:06.14$setupk4/recpk4 2006.286.04:16:06.14$recpk4/recpatch= 2006.286.04:16:06.14$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:16:06.14$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:16:06.14$setupk4/vck44 2006.286.04:16:06.14$vck44/valo=1,524.99 2006.286.04:16:06.14#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.04:16:06.14#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.04:16:06.14#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:06.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:16:06.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:16:06.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:16:06.14#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:16:06.14#ibcon#first serial, iclass 36, count 0 2006.286.04:16:06.14#ibcon#enter sib2, iclass 36, count 0 2006.286.04:16:06.14#ibcon#flushed, iclass 36, count 0 2006.286.04:16:06.14#ibcon#about to write, iclass 36, count 0 2006.286.04:16:06.14#ibcon#wrote, iclass 36, count 0 2006.286.04:16:06.14#ibcon#about to read 3, iclass 36, count 0 2006.286.04:16:06.16#ibcon#read 3, iclass 36, count 0 2006.286.04:16:06.16#ibcon#about to read 4, iclass 36, count 0 2006.286.04:16:06.16#ibcon#read 4, iclass 36, count 0 2006.286.04:16:06.16#ibcon#about to read 5, iclass 36, count 0 2006.286.04:16:06.16#ibcon#read 5, iclass 36, count 0 2006.286.04:16:06.16#ibcon#about to read 6, iclass 36, count 0 2006.286.04:16:06.16#ibcon#read 6, iclass 36, count 0 2006.286.04:16:06.16#ibcon#end of sib2, iclass 36, count 0 2006.286.04:16:06.16#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:16:06.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:16:06.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:16:06.16#ibcon#*before write, iclass 36, count 0 2006.286.04:16:06.16#ibcon#enter sib2, iclass 36, count 0 2006.286.04:16:06.16#ibcon#flushed, iclass 36, count 0 2006.286.04:16:06.16#ibcon#about to write, iclass 36, count 0 2006.286.04:16:06.16#ibcon#wrote, iclass 36, count 0 2006.286.04:16:06.16#ibcon#about to read 3, iclass 36, count 0 2006.286.04:16:06.21#ibcon#read 3, iclass 36, count 0 2006.286.04:16:06.21#ibcon#about to read 4, iclass 36, count 0 2006.286.04:16:06.21#ibcon#read 4, iclass 36, count 0 2006.286.04:16:06.21#ibcon#about to read 5, iclass 36, count 0 2006.286.04:16:06.21#ibcon#read 5, iclass 36, count 0 2006.286.04:16:06.21#ibcon#about to read 6, iclass 36, count 0 2006.286.04:16:06.21#ibcon#read 6, iclass 36, count 0 2006.286.04:16:06.21#ibcon#end of sib2, iclass 36, count 0 2006.286.04:16:06.21#ibcon#*after write, iclass 36, count 0 2006.286.04:16:06.21#ibcon#*before return 0, iclass 36, count 0 2006.286.04:16:06.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:16:06.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:16:06.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:16:06.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:16:06.21$vck44/va=1,7 2006.286.04:16:06.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.04:16:06.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.04:16:06.21#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:06.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:16:06.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:16:06.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:16:06.21#ibcon#enter wrdev, iclass 38, count 2 2006.286.04:16:06.21#ibcon#first serial, iclass 38, count 2 2006.286.04:16:06.21#ibcon#enter sib2, iclass 38, count 2 2006.286.04:16:06.21#ibcon#flushed, iclass 38, count 2 2006.286.04:16:06.21#ibcon#about to write, iclass 38, count 2 2006.286.04:16:06.21#ibcon#wrote, iclass 38, count 2 2006.286.04:16:06.21#ibcon#about to read 3, iclass 38, count 2 2006.286.04:16:06.23#ibcon#read 3, iclass 38, count 2 2006.286.04:16:06.23#ibcon#about to read 4, iclass 38, count 2 2006.286.04:16:06.23#ibcon#read 4, iclass 38, count 2 2006.286.04:16:06.23#ibcon#about to read 5, iclass 38, count 2 2006.286.04:16:06.23#ibcon#read 5, iclass 38, count 2 2006.286.04:16:06.23#ibcon#about to read 6, iclass 38, count 2 2006.286.04:16:06.23#ibcon#read 6, iclass 38, count 2 2006.286.04:16:06.23#ibcon#end of sib2, iclass 38, count 2 2006.286.04:16:06.23#ibcon#*mode == 0, iclass 38, count 2 2006.286.04:16:06.23#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.04:16:06.23#ibcon#[25=AT01-07\r\n] 2006.286.04:16:06.23#ibcon#*before write, iclass 38, count 2 2006.286.04:16:06.23#ibcon#enter sib2, iclass 38, count 2 2006.286.04:16:06.23#ibcon#flushed, iclass 38, count 2 2006.286.04:16:06.23#ibcon#about to write, iclass 38, count 2 2006.286.04:16:06.23#ibcon#wrote, iclass 38, count 2 2006.286.04:16:06.23#ibcon#about to read 3, iclass 38, count 2 2006.286.04:16:06.26#ibcon#read 3, iclass 38, count 2 2006.286.04:16:06.26#ibcon#about to read 4, iclass 38, count 2 2006.286.04:16:06.26#ibcon#read 4, iclass 38, count 2 2006.286.04:16:06.26#ibcon#about to read 5, iclass 38, count 2 2006.286.04:16:06.26#ibcon#read 5, iclass 38, count 2 2006.286.04:16:06.26#ibcon#about to read 6, iclass 38, count 2 2006.286.04:16:06.26#ibcon#read 6, iclass 38, count 2 2006.286.04:16:06.26#ibcon#end of sib2, iclass 38, count 2 2006.286.04:16:06.26#ibcon#*after write, iclass 38, count 2 2006.286.04:16:06.26#ibcon#*before return 0, iclass 38, count 2 2006.286.04:16:06.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:16:06.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:16:06.26#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.04:16:06.26#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:06.26#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:16:06.38#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:16:06.38#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:16:06.38#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:16:06.38#ibcon#first serial, iclass 38, count 0 2006.286.04:16:06.38#ibcon#enter sib2, iclass 38, count 0 2006.286.04:16:06.38#ibcon#flushed, iclass 38, count 0 2006.286.04:16:06.38#ibcon#about to write, iclass 38, count 0 2006.286.04:16:06.38#ibcon#wrote, iclass 38, count 0 2006.286.04:16:06.38#ibcon#about to read 3, iclass 38, count 0 2006.286.04:16:06.40#ibcon#read 3, iclass 38, count 0 2006.286.04:16:06.40#ibcon#about to read 4, iclass 38, count 0 2006.286.04:16:06.40#ibcon#read 4, iclass 38, count 0 2006.286.04:16:06.40#ibcon#about to read 5, iclass 38, count 0 2006.286.04:16:06.40#ibcon#read 5, iclass 38, count 0 2006.286.04:16:06.40#ibcon#about to read 6, iclass 38, count 0 2006.286.04:16:06.40#ibcon#read 6, iclass 38, count 0 2006.286.04:16:06.40#ibcon#end of sib2, iclass 38, count 0 2006.286.04:16:06.40#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:16:06.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:16:06.40#ibcon#[25=USB\r\n] 2006.286.04:16:06.40#ibcon#*before write, iclass 38, count 0 2006.286.04:16:06.40#ibcon#enter sib2, iclass 38, count 0 2006.286.04:16:06.40#ibcon#flushed, iclass 38, count 0 2006.286.04:16:06.40#ibcon#about to write, iclass 38, count 0 2006.286.04:16:06.40#ibcon#wrote, iclass 38, count 0 2006.286.04:16:06.40#ibcon#about to read 3, iclass 38, count 0 2006.286.04:16:06.43#ibcon#read 3, iclass 38, count 0 2006.286.04:16:06.43#ibcon#about to read 4, iclass 38, count 0 2006.286.04:16:06.43#ibcon#read 4, iclass 38, count 0 2006.286.04:16:06.43#ibcon#about to read 5, iclass 38, count 0 2006.286.04:16:06.43#ibcon#read 5, iclass 38, count 0 2006.286.04:16:06.43#ibcon#about to read 6, iclass 38, count 0 2006.286.04:16:06.43#ibcon#read 6, iclass 38, count 0 2006.286.04:16:06.43#ibcon#end of sib2, iclass 38, count 0 2006.286.04:16:06.43#ibcon#*after write, iclass 38, count 0 2006.286.04:16:06.43#ibcon#*before return 0, iclass 38, count 0 2006.286.04:16:06.43#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:16:06.43#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:16:06.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:16:06.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:16:06.43$vck44/valo=2,534.99 2006.286.04:16:06.43#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.04:16:06.43#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.04:16:06.43#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:06.43#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:16:06.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:16:06.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:16:06.43#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:16:06.43#ibcon#first serial, iclass 40, count 0 2006.286.04:16:06.43#ibcon#enter sib2, iclass 40, count 0 2006.286.04:16:06.43#ibcon#flushed, iclass 40, count 0 2006.286.04:16:06.43#ibcon#about to write, iclass 40, count 0 2006.286.04:16:06.43#ibcon#wrote, iclass 40, count 0 2006.286.04:16:06.43#ibcon#about to read 3, iclass 40, count 0 2006.286.04:16:06.45#ibcon#read 3, iclass 40, count 0 2006.286.04:16:06.84#ibcon#about to read 4, iclass 40, count 0 2006.286.04:16:06.84#ibcon#read 4, iclass 40, count 0 2006.286.04:16:06.84#ibcon#about to read 5, iclass 40, count 0 2006.286.04:16:06.84#ibcon#read 5, iclass 40, count 0 2006.286.04:16:06.84#ibcon#about to read 6, iclass 40, count 0 2006.286.04:16:06.84#ibcon#read 6, iclass 40, count 0 2006.286.04:16:06.84#ibcon#end of sib2, iclass 40, count 0 2006.286.04:16:06.84#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:16:06.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:16:06.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:16:06.84#ibcon#*before write, iclass 40, count 0 2006.286.04:16:06.84#ibcon#enter sib2, iclass 40, count 0 2006.286.04:16:06.84#ibcon#flushed, iclass 40, count 0 2006.286.04:16:06.84#ibcon#about to write, iclass 40, count 0 2006.286.04:16:06.84#ibcon#wrote, iclass 40, count 0 2006.286.04:16:06.84#ibcon#about to read 3, iclass 40, count 0 2006.286.04:16:06.88#ibcon#read 3, iclass 40, count 0 2006.286.04:16:06.88#ibcon#about to read 4, iclass 40, count 0 2006.286.04:16:06.88#ibcon#read 4, iclass 40, count 0 2006.286.04:16:06.88#ibcon#about to read 5, iclass 40, count 0 2006.286.04:16:06.88#ibcon#read 5, iclass 40, count 0 2006.286.04:16:06.88#ibcon#about to read 6, iclass 40, count 0 2006.286.04:16:06.88#ibcon#read 6, iclass 40, count 0 2006.286.04:16:06.88#ibcon#end of sib2, iclass 40, count 0 2006.286.04:16:06.88#ibcon#*after write, iclass 40, count 0 2006.286.04:16:06.88#ibcon#*before return 0, iclass 40, count 0 2006.286.04:16:06.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:16:06.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:16:06.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:16:06.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:16:06.88$vck44/va=2,6 2006.286.04:16:06.88#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.04:16:06.88#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.04:16:06.88#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:06.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:16:06.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:16:06.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:16:06.88#ibcon#enter wrdev, iclass 4, count 2 2006.286.04:16:06.88#ibcon#first serial, iclass 4, count 2 2006.286.04:16:06.88#ibcon#enter sib2, iclass 4, count 2 2006.286.04:16:06.88#ibcon#flushed, iclass 4, count 2 2006.286.04:16:06.88#ibcon#about to write, iclass 4, count 2 2006.286.04:16:06.88#ibcon#wrote, iclass 4, count 2 2006.286.04:16:06.88#ibcon#about to read 3, iclass 4, count 2 2006.286.04:16:06.90#ibcon#read 3, iclass 4, count 2 2006.286.04:16:06.90#ibcon#about to read 4, iclass 4, count 2 2006.286.04:16:06.90#ibcon#read 4, iclass 4, count 2 2006.286.04:16:06.90#ibcon#about to read 5, iclass 4, count 2 2006.286.04:16:06.90#ibcon#read 5, iclass 4, count 2 2006.286.04:16:06.90#ibcon#about to read 6, iclass 4, count 2 2006.286.04:16:06.90#ibcon#read 6, iclass 4, count 2 2006.286.04:16:06.90#ibcon#end of sib2, iclass 4, count 2 2006.286.04:16:06.90#ibcon#*mode == 0, iclass 4, count 2 2006.286.04:16:06.90#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.04:16:06.90#ibcon#[25=AT02-06\r\n] 2006.286.04:16:06.90#ibcon#*before write, iclass 4, count 2 2006.286.04:16:06.90#ibcon#enter sib2, iclass 4, count 2 2006.286.04:16:06.90#ibcon#flushed, iclass 4, count 2 2006.286.04:16:06.90#ibcon#about to write, iclass 4, count 2 2006.286.04:16:06.90#ibcon#wrote, iclass 4, count 2 2006.286.04:16:06.90#ibcon#about to read 3, iclass 4, count 2 2006.286.04:16:06.93#ibcon#read 3, iclass 4, count 2 2006.286.04:16:06.93#ibcon#about to read 4, iclass 4, count 2 2006.286.04:16:06.93#ibcon#read 4, iclass 4, count 2 2006.286.04:16:06.93#ibcon#about to read 5, iclass 4, count 2 2006.286.04:16:06.93#ibcon#read 5, iclass 4, count 2 2006.286.04:16:06.93#ibcon#about to read 6, iclass 4, count 2 2006.286.04:16:06.93#ibcon#read 6, iclass 4, count 2 2006.286.04:16:06.93#ibcon#end of sib2, iclass 4, count 2 2006.286.04:16:06.93#ibcon#*after write, iclass 4, count 2 2006.286.04:16:06.93#ibcon#*before return 0, iclass 4, count 2 2006.286.04:16:06.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:16:06.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:16:06.93#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.04:16:06.93#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:06.93#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:16:07.05#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:16:07.05#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:16:07.05#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:16:07.05#ibcon#first serial, iclass 4, count 0 2006.286.04:16:07.05#ibcon#enter sib2, iclass 4, count 0 2006.286.04:16:07.05#ibcon#flushed, iclass 4, count 0 2006.286.04:16:07.05#ibcon#about to write, iclass 4, count 0 2006.286.04:16:07.05#ibcon#wrote, iclass 4, count 0 2006.286.04:16:07.05#ibcon#about to read 3, iclass 4, count 0 2006.286.04:16:07.07#ibcon#read 3, iclass 4, count 0 2006.286.04:16:07.07#ibcon#about to read 4, iclass 4, count 0 2006.286.04:16:07.07#ibcon#read 4, iclass 4, count 0 2006.286.04:16:07.07#ibcon#about to read 5, iclass 4, count 0 2006.286.04:16:07.07#ibcon#read 5, iclass 4, count 0 2006.286.04:16:07.07#ibcon#about to read 6, iclass 4, count 0 2006.286.04:16:07.07#ibcon#read 6, iclass 4, count 0 2006.286.04:16:07.07#ibcon#end of sib2, iclass 4, count 0 2006.286.04:16:07.07#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:16:07.07#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:16:07.07#ibcon#[25=USB\r\n] 2006.286.04:16:07.07#ibcon#*before write, iclass 4, count 0 2006.286.04:16:07.07#ibcon#enter sib2, iclass 4, count 0 2006.286.04:16:07.07#ibcon#flushed, iclass 4, count 0 2006.286.04:16:07.07#ibcon#about to write, iclass 4, count 0 2006.286.04:16:07.07#ibcon#wrote, iclass 4, count 0 2006.286.04:16:07.07#ibcon#about to read 3, iclass 4, count 0 2006.286.04:16:07.10#ibcon#read 3, iclass 4, count 0 2006.286.04:16:07.10#ibcon#about to read 4, iclass 4, count 0 2006.286.04:16:07.10#ibcon#read 4, iclass 4, count 0 2006.286.04:16:07.10#ibcon#about to read 5, iclass 4, count 0 2006.286.04:16:07.10#ibcon#read 5, iclass 4, count 0 2006.286.04:16:07.10#ibcon#about to read 6, iclass 4, count 0 2006.286.04:16:07.10#ibcon#read 6, iclass 4, count 0 2006.286.04:16:07.10#ibcon#end of sib2, iclass 4, count 0 2006.286.04:16:07.10#ibcon#*after write, iclass 4, count 0 2006.286.04:16:07.10#ibcon#*before return 0, iclass 4, count 0 2006.286.04:16:07.10#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:16:07.10#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:16:07.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:16:07.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:16:07.10$vck44/valo=3,564.99 2006.286.04:16:07.10#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.04:16:07.10#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.04:16:07.10#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:07.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:16:07.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:16:07.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:16:07.10#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:16:07.10#ibcon#first serial, iclass 6, count 0 2006.286.04:16:07.10#ibcon#enter sib2, iclass 6, count 0 2006.286.04:16:07.10#ibcon#flushed, iclass 6, count 0 2006.286.04:16:07.10#ibcon#about to write, iclass 6, count 0 2006.286.04:16:07.10#ibcon#wrote, iclass 6, count 0 2006.286.04:16:07.10#ibcon#about to read 3, iclass 6, count 0 2006.286.04:16:07.12#ibcon#read 3, iclass 6, count 0 2006.286.04:16:07.12#ibcon#about to read 4, iclass 6, count 0 2006.286.04:16:07.12#ibcon#read 4, iclass 6, count 0 2006.286.04:16:07.12#ibcon#about to read 5, iclass 6, count 0 2006.286.04:16:07.12#ibcon#read 5, iclass 6, count 0 2006.286.04:16:07.12#ibcon#about to read 6, iclass 6, count 0 2006.286.04:16:07.12#ibcon#read 6, iclass 6, count 0 2006.286.04:16:07.12#ibcon#end of sib2, iclass 6, count 0 2006.286.04:16:07.12#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:16:07.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:16:07.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:16:07.12#ibcon#*before write, iclass 6, count 0 2006.286.04:16:07.12#ibcon#enter sib2, iclass 6, count 0 2006.286.04:16:07.12#ibcon#flushed, iclass 6, count 0 2006.286.04:16:07.12#ibcon#about to write, iclass 6, count 0 2006.286.04:16:07.12#ibcon#wrote, iclass 6, count 0 2006.286.04:16:07.12#ibcon#about to read 3, iclass 6, count 0 2006.286.04:16:07.16#ibcon#read 3, iclass 6, count 0 2006.286.04:16:07.16#ibcon#about to read 4, iclass 6, count 0 2006.286.04:16:07.16#ibcon#read 4, iclass 6, count 0 2006.286.04:16:07.16#ibcon#about to read 5, iclass 6, count 0 2006.286.04:16:07.16#ibcon#read 5, iclass 6, count 0 2006.286.04:16:07.16#ibcon#about to read 6, iclass 6, count 0 2006.286.04:16:07.16#ibcon#read 6, iclass 6, count 0 2006.286.04:16:07.16#ibcon#end of sib2, iclass 6, count 0 2006.286.04:16:07.16#ibcon#*after write, iclass 6, count 0 2006.286.04:16:07.16#ibcon#*before return 0, iclass 6, count 0 2006.286.04:16:07.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:16:07.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:16:07.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:16:07.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:16:07.16$vck44/va=3,7 2006.286.04:16:07.16#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.04:16:07.16#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.04:16:07.16#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:07.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:16:07.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:16:07.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:16:07.22#ibcon#enter wrdev, iclass 10, count 2 2006.286.04:16:07.22#ibcon#first serial, iclass 10, count 2 2006.286.04:16:07.22#ibcon#enter sib2, iclass 10, count 2 2006.286.04:16:07.22#ibcon#flushed, iclass 10, count 2 2006.286.04:16:07.22#ibcon#about to write, iclass 10, count 2 2006.286.04:16:07.22#ibcon#wrote, iclass 10, count 2 2006.286.04:16:07.22#ibcon#about to read 3, iclass 10, count 2 2006.286.04:16:07.24#ibcon#read 3, iclass 10, count 2 2006.286.04:16:07.24#ibcon#about to read 4, iclass 10, count 2 2006.286.04:16:07.24#ibcon#read 4, iclass 10, count 2 2006.286.04:16:07.24#ibcon#about to read 5, iclass 10, count 2 2006.286.04:16:07.24#ibcon#read 5, iclass 10, count 2 2006.286.04:16:07.24#ibcon#about to read 6, iclass 10, count 2 2006.286.04:16:07.24#ibcon#read 6, iclass 10, count 2 2006.286.04:16:07.24#ibcon#end of sib2, iclass 10, count 2 2006.286.04:16:07.24#ibcon#*mode == 0, iclass 10, count 2 2006.286.04:16:07.24#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.04:16:07.24#ibcon#[25=AT03-07\r\n] 2006.286.04:16:07.24#ibcon#*before write, iclass 10, count 2 2006.286.04:16:07.24#ibcon#enter sib2, iclass 10, count 2 2006.286.04:16:07.24#ibcon#flushed, iclass 10, count 2 2006.286.04:16:07.24#ibcon#about to write, iclass 10, count 2 2006.286.04:16:07.24#ibcon#wrote, iclass 10, count 2 2006.286.04:16:07.24#ibcon#about to read 3, iclass 10, count 2 2006.286.04:16:07.27#ibcon#read 3, iclass 10, count 2 2006.286.04:16:07.27#ibcon#about to read 4, iclass 10, count 2 2006.286.04:16:07.27#ibcon#read 4, iclass 10, count 2 2006.286.04:16:07.27#ibcon#about to read 5, iclass 10, count 2 2006.286.04:16:07.27#ibcon#read 5, iclass 10, count 2 2006.286.04:16:07.27#ibcon#about to read 6, iclass 10, count 2 2006.286.04:16:07.27#ibcon#read 6, iclass 10, count 2 2006.286.04:16:07.27#ibcon#end of sib2, iclass 10, count 2 2006.286.04:16:07.27#ibcon#*after write, iclass 10, count 2 2006.286.04:16:07.27#ibcon#*before return 0, iclass 10, count 2 2006.286.04:16:07.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:16:07.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:16:07.27#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.04:16:07.27#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:07.27#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:16:07.39#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:16:07.39#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:16:07.39#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:16:07.39#ibcon#first serial, iclass 10, count 0 2006.286.04:16:07.39#ibcon#enter sib2, iclass 10, count 0 2006.286.04:16:07.39#ibcon#flushed, iclass 10, count 0 2006.286.04:16:07.39#ibcon#about to write, iclass 10, count 0 2006.286.04:16:07.39#ibcon#wrote, iclass 10, count 0 2006.286.04:16:07.39#ibcon#about to read 3, iclass 10, count 0 2006.286.04:16:07.41#ibcon#read 3, iclass 10, count 0 2006.286.04:16:07.41#ibcon#about to read 4, iclass 10, count 0 2006.286.04:16:07.41#ibcon#read 4, iclass 10, count 0 2006.286.04:16:07.41#ibcon#about to read 5, iclass 10, count 0 2006.286.04:16:07.41#ibcon#read 5, iclass 10, count 0 2006.286.04:16:07.41#ibcon#about to read 6, iclass 10, count 0 2006.286.04:16:07.41#ibcon#read 6, iclass 10, count 0 2006.286.04:16:07.41#ibcon#end of sib2, iclass 10, count 0 2006.286.04:16:07.41#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:16:07.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:16:07.41#ibcon#[25=USB\r\n] 2006.286.04:16:07.41#ibcon#*before write, iclass 10, count 0 2006.286.04:16:07.41#ibcon#enter sib2, iclass 10, count 0 2006.286.04:16:07.41#ibcon#flushed, iclass 10, count 0 2006.286.04:16:07.41#ibcon#about to write, iclass 10, count 0 2006.286.04:16:07.41#ibcon#wrote, iclass 10, count 0 2006.286.04:16:07.41#ibcon#about to read 3, iclass 10, count 0 2006.286.04:16:07.44#ibcon#read 3, iclass 10, count 0 2006.286.04:16:07.44#ibcon#about to read 4, iclass 10, count 0 2006.286.04:16:07.44#ibcon#read 4, iclass 10, count 0 2006.286.04:16:07.44#ibcon#about to read 5, iclass 10, count 0 2006.286.04:16:07.44#ibcon#read 5, iclass 10, count 0 2006.286.04:16:07.44#ibcon#about to read 6, iclass 10, count 0 2006.286.04:16:07.44#ibcon#read 6, iclass 10, count 0 2006.286.04:16:07.44#ibcon#end of sib2, iclass 10, count 0 2006.286.04:16:07.44#ibcon#*after write, iclass 10, count 0 2006.286.04:16:07.44#ibcon#*before return 0, iclass 10, count 0 2006.286.04:16:07.44#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:16:07.44#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:16:07.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:16:07.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:16:07.44$vck44/valo=4,624.99 2006.286.04:16:07.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.04:16:07.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.04:16:07.44#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:07.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:16:07.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:16:07.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:16:07.44#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:16:07.44#ibcon#first serial, iclass 12, count 0 2006.286.04:16:07.44#ibcon#enter sib2, iclass 12, count 0 2006.286.04:16:07.44#ibcon#flushed, iclass 12, count 0 2006.286.04:16:07.96#ibcon#about to write, iclass 12, count 0 2006.286.04:16:07.96#ibcon#wrote, iclass 12, count 0 2006.286.04:16:07.96#ibcon#about to read 3, iclass 12, count 0 2006.286.04:16:07.97#ibcon#read 3, iclass 12, count 0 2006.286.04:16:07.97#ibcon#about to read 4, iclass 12, count 0 2006.286.04:16:07.97#ibcon#read 4, iclass 12, count 0 2006.286.04:16:07.97#ibcon#about to read 5, iclass 12, count 0 2006.286.04:16:07.97#ibcon#read 5, iclass 12, count 0 2006.286.04:16:07.97#ibcon#about to read 6, iclass 12, count 0 2006.286.04:16:07.97#ibcon#read 6, iclass 12, count 0 2006.286.04:16:07.97#ibcon#end of sib2, iclass 12, count 0 2006.286.04:16:07.97#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:16:07.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:16:07.97#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:16:07.97#ibcon#*before write, iclass 12, count 0 2006.286.04:16:07.97#ibcon#enter sib2, iclass 12, count 0 2006.286.04:16:07.97#ibcon#flushed, iclass 12, count 0 2006.286.04:16:07.97#ibcon#about to write, iclass 12, count 0 2006.286.04:16:07.97#ibcon#wrote, iclass 12, count 0 2006.286.04:16:07.97#ibcon#about to read 3, iclass 12, count 0 2006.286.04:16:08.01#ibcon#read 3, iclass 12, count 0 2006.286.04:16:08.01#ibcon#about to read 4, iclass 12, count 0 2006.286.04:16:08.01#ibcon#read 4, iclass 12, count 0 2006.286.04:16:08.01#ibcon#about to read 5, iclass 12, count 0 2006.286.04:16:08.01#ibcon#read 5, iclass 12, count 0 2006.286.04:16:08.01#ibcon#about to read 6, iclass 12, count 0 2006.286.04:16:08.01#ibcon#read 6, iclass 12, count 0 2006.286.04:16:08.01#ibcon#end of sib2, iclass 12, count 0 2006.286.04:16:08.01#ibcon#*after write, iclass 12, count 0 2006.286.04:16:08.01#ibcon#*before return 0, iclass 12, count 0 2006.286.04:16:08.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:16:08.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:16:08.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:16:08.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:16:08.01$vck44/va=4,6 2006.286.04:16:08.01#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.04:16:08.01#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.04:16:08.01#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:08.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:16:08.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:16:08.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:16:08.01#ibcon#enter wrdev, iclass 14, count 2 2006.286.04:16:08.01#ibcon#first serial, iclass 14, count 2 2006.286.04:16:08.01#ibcon#enter sib2, iclass 14, count 2 2006.286.04:16:08.01#ibcon#flushed, iclass 14, count 2 2006.286.04:16:08.01#ibcon#about to write, iclass 14, count 2 2006.286.04:16:08.01#ibcon#wrote, iclass 14, count 2 2006.286.04:16:08.01#ibcon#about to read 3, iclass 14, count 2 2006.286.04:16:08.03#ibcon#read 3, iclass 14, count 2 2006.286.04:16:08.03#ibcon#about to read 4, iclass 14, count 2 2006.286.04:16:08.03#ibcon#read 4, iclass 14, count 2 2006.286.04:16:08.03#ibcon#about to read 5, iclass 14, count 2 2006.286.04:16:08.03#ibcon#read 5, iclass 14, count 2 2006.286.04:16:08.03#ibcon#about to read 6, iclass 14, count 2 2006.286.04:16:08.03#ibcon#read 6, iclass 14, count 2 2006.286.04:16:08.03#ibcon#end of sib2, iclass 14, count 2 2006.286.04:16:08.03#ibcon#*mode == 0, iclass 14, count 2 2006.286.04:16:08.03#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.04:16:08.03#ibcon#[25=AT04-06\r\n] 2006.286.04:16:08.03#ibcon#*before write, iclass 14, count 2 2006.286.04:16:08.03#ibcon#enter sib2, iclass 14, count 2 2006.286.04:16:08.03#ibcon#flushed, iclass 14, count 2 2006.286.04:16:08.03#ibcon#about to write, iclass 14, count 2 2006.286.04:16:08.03#ibcon#wrote, iclass 14, count 2 2006.286.04:16:08.03#ibcon#about to read 3, iclass 14, count 2 2006.286.04:16:08.06#ibcon#read 3, iclass 14, count 2 2006.286.04:16:08.06#ibcon#about to read 4, iclass 14, count 2 2006.286.04:16:08.06#ibcon#read 4, iclass 14, count 2 2006.286.04:16:08.06#ibcon#about to read 5, iclass 14, count 2 2006.286.04:16:08.06#ibcon#read 5, iclass 14, count 2 2006.286.04:16:08.06#ibcon#about to read 6, iclass 14, count 2 2006.286.04:16:08.06#ibcon#read 6, iclass 14, count 2 2006.286.04:16:08.06#ibcon#end of sib2, iclass 14, count 2 2006.286.04:16:08.06#ibcon#*after write, iclass 14, count 2 2006.286.04:16:08.06#ibcon#*before return 0, iclass 14, count 2 2006.286.04:16:08.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:16:08.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:16:08.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.04:16:08.06#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:08.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:16:08.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:16:08.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:16:08.18#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:16:08.18#ibcon#first serial, iclass 14, count 0 2006.286.04:16:08.18#ibcon#enter sib2, iclass 14, count 0 2006.286.04:16:08.18#ibcon#flushed, iclass 14, count 0 2006.286.04:16:08.18#ibcon#about to write, iclass 14, count 0 2006.286.04:16:08.18#ibcon#wrote, iclass 14, count 0 2006.286.04:16:08.18#ibcon#about to read 3, iclass 14, count 0 2006.286.04:16:08.20#ibcon#read 3, iclass 14, count 0 2006.286.04:16:08.20#ibcon#about to read 4, iclass 14, count 0 2006.286.04:16:08.20#ibcon#read 4, iclass 14, count 0 2006.286.04:16:08.20#ibcon#about to read 5, iclass 14, count 0 2006.286.04:16:08.20#ibcon#read 5, iclass 14, count 0 2006.286.04:16:08.20#ibcon#about to read 6, iclass 14, count 0 2006.286.04:16:08.20#ibcon#read 6, iclass 14, count 0 2006.286.04:16:08.20#ibcon#end of sib2, iclass 14, count 0 2006.286.04:16:08.20#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:16:08.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:16:08.20#ibcon#[25=USB\r\n] 2006.286.04:16:08.20#ibcon#*before write, iclass 14, count 0 2006.286.04:16:08.20#ibcon#enter sib2, iclass 14, count 0 2006.286.04:16:08.20#ibcon#flushed, iclass 14, count 0 2006.286.04:16:08.20#ibcon#about to write, iclass 14, count 0 2006.286.04:16:08.20#ibcon#wrote, iclass 14, count 0 2006.286.04:16:08.20#ibcon#about to read 3, iclass 14, count 0 2006.286.04:16:08.23#ibcon#read 3, iclass 14, count 0 2006.286.04:16:08.23#ibcon#about to read 4, iclass 14, count 0 2006.286.04:16:08.23#ibcon#read 4, iclass 14, count 0 2006.286.04:16:08.23#ibcon#about to read 5, iclass 14, count 0 2006.286.04:16:08.23#ibcon#read 5, iclass 14, count 0 2006.286.04:16:08.23#ibcon#about to read 6, iclass 14, count 0 2006.286.04:16:08.23#ibcon#read 6, iclass 14, count 0 2006.286.04:16:08.23#ibcon#end of sib2, iclass 14, count 0 2006.286.04:16:08.23#ibcon#*after write, iclass 14, count 0 2006.286.04:16:08.23#ibcon#*before return 0, iclass 14, count 0 2006.286.04:16:08.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:16:08.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:16:08.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:16:08.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:16:08.23$vck44/valo=5,734.99 2006.286.04:16:08.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.04:16:08.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.04:16:08.23#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:08.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:16:08.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:16:08.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:16:08.23#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:16:08.23#ibcon#first serial, iclass 16, count 0 2006.286.04:16:08.23#ibcon#enter sib2, iclass 16, count 0 2006.286.04:16:08.23#ibcon#flushed, iclass 16, count 0 2006.286.04:16:08.23#ibcon#about to write, iclass 16, count 0 2006.286.04:16:08.23#ibcon#wrote, iclass 16, count 0 2006.286.04:16:08.23#ibcon#about to read 3, iclass 16, count 0 2006.286.04:16:08.25#ibcon#read 3, iclass 16, count 0 2006.286.04:16:08.25#ibcon#about to read 4, iclass 16, count 0 2006.286.04:16:08.25#ibcon#read 4, iclass 16, count 0 2006.286.04:16:08.25#ibcon#about to read 5, iclass 16, count 0 2006.286.04:16:08.25#ibcon#read 5, iclass 16, count 0 2006.286.04:16:08.25#ibcon#about to read 6, iclass 16, count 0 2006.286.04:16:08.25#ibcon#read 6, iclass 16, count 0 2006.286.04:16:08.25#ibcon#end of sib2, iclass 16, count 0 2006.286.04:16:08.25#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:16:08.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:16:08.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:16:08.25#ibcon#*before write, iclass 16, count 0 2006.286.04:16:08.25#ibcon#enter sib2, iclass 16, count 0 2006.286.04:16:08.25#ibcon#flushed, iclass 16, count 0 2006.286.04:16:08.25#ibcon#about to write, iclass 16, count 0 2006.286.04:16:08.25#ibcon#wrote, iclass 16, count 0 2006.286.04:16:08.25#ibcon#about to read 3, iclass 16, count 0 2006.286.04:16:08.29#ibcon#read 3, iclass 16, count 0 2006.286.04:16:08.29#ibcon#about to read 4, iclass 16, count 0 2006.286.04:16:08.29#ibcon#read 4, iclass 16, count 0 2006.286.04:16:08.29#ibcon#about to read 5, iclass 16, count 0 2006.286.04:16:08.29#ibcon#read 5, iclass 16, count 0 2006.286.04:16:08.29#ibcon#about to read 6, iclass 16, count 0 2006.286.04:16:08.29#ibcon#read 6, iclass 16, count 0 2006.286.04:16:08.29#ibcon#end of sib2, iclass 16, count 0 2006.286.04:16:08.29#ibcon#*after write, iclass 16, count 0 2006.286.04:16:08.29#ibcon#*before return 0, iclass 16, count 0 2006.286.04:16:08.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:16:08.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:16:08.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:16:08.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:16:08.29$vck44/va=5,3 2006.286.04:16:08.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.04:16:08.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.04:16:08.29#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:08.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:16:08.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:16:08.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:16:08.35#ibcon#enter wrdev, iclass 18, count 2 2006.286.04:16:08.35#ibcon#first serial, iclass 18, count 2 2006.286.04:16:08.35#ibcon#enter sib2, iclass 18, count 2 2006.286.04:16:08.35#ibcon#flushed, iclass 18, count 2 2006.286.04:16:08.35#ibcon#about to write, iclass 18, count 2 2006.286.04:16:08.35#ibcon#wrote, iclass 18, count 2 2006.286.04:16:08.35#ibcon#about to read 3, iclass 18, count 2 2006.286.04:16:08.37#ibcon#read 3, iclass 18, count 2 2006.286.04:16:08.37#ibcon#about to read 4, iclass 18, count 2 2006.286.04:16:08.37#ibcon#read 4, iclass 18, count 2 2006.286.04:16:08.37#ibcon#about to read 5, iclass 18, count 2 2006.286.04:16:08.37#ibcon#read 5, iclass 18, count 2 2006.286.04:16:08.37#ibcon#about to read 6, iclass 18, count 2 2006.286.04:16:08.37#ibcon#read 6, iclass 18, count 2 2006.286.04:16:08.37#ibcon#end of sib2, iclass 18, count 2 2006.286.04:16:08.37#ibcon#*mode == 0, iclass 18, count 2 2006.286.04:16:08.37#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.04:16:08.37#ibcon#[25=AT05-03\r\n] 2006.286.04:16:08.37#ibcon#*before write, iclass 18, count 2 2006.286.04:16:08.37#ibcon#enter sib2, iclass 18, count 2 2006.286.04:16:08.37#ibcon#flushed, iclass 18, count 2 2006.286.04:16:08.37#ibcon#about to write, iclass 18, count 2 2006.286.04:16:08.37#ibcon#wrote, iclass 18, count 2 2006.286.04:16:08.37#ibcon#about to read 3, iclass 18, count 2 2006.286.04:16:08.40#ibcon#read 3, iclass 18, count 2 2006.286.04:16:08.40#ibcon#about to read 4, iclass 18, count 2 2006.286.04:16:08.40#ibcon#read 4, iclass 18, count 2 2006.286.04:16:08.40#ibcon#about to read 5, iclass 18, count 2 2006.286.04:16:08.40#ibcon#read 5, iclass 18, count 2 2006.286.04:16:08.40#ibcon#about to read 6, iclass 18, count 2 2006.286.04:16:08.40#ibcon#read 6, iclass 18, count 2 2006.286.04:16:08.40#ibcon#end of sib2, iclass 18, count 2 2006.286.04:16:08.40#ibcon#*after write, iclass 18, count 2 2006.286.04:16:08.40#ibcon#*before return 0, iclass 18, count 2 2006.286.04:16:08.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:16:08.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:16:08.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.04:16:08.40#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:08.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:16:08.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:16:08.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:16:08.52#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:16:08.52#ibcon#first serial, iclass 18, count 0 2006.286.04:16:08.52#ibcon#enter sib2, iclass 18, count 0 2006.286.04:16:08.52#ibcon#flushed, iclass 18, count 0 2006.286.04:16:08.52#ibcon#about to write, iclass 18, count 0 2006.286.04:16:08.52#ibcon#wrote, iclass 18, count 0 2006.286.04:16:08.52#ibcon#about to read 3, iclass 18, count 0 2006.286.04:16:08.54#ibcon#read 3, iclass 18, count 0 2006.286.04:16:08.54#ibcon#about to read 4, iclass 18, count 0 2006.286.04:16:08.54#ibcon#read 4, iclass 18, count 0 2006.286.04:16:08.54#ibcon#about to read 5, iclass 18, count 0 2006.286.04:16:08.54#ibcon#read 5, iclass 18, count 0 2006.286.04:16:08.54#ibcon#about to read 6, iclass 18, count 0 2006.286.04:16:08.54#ibcon#read 6, iclass 18, count 0 2006.286.04:16:08.54#ibcon#end of sib2, iclass 18, count 0 2006.286.04:16:08.54#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:16:08.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:16:08.54#ibcon#[25=USB\r\n] 2006.286.04:16:08.54#ibcon#*before write, iclass 18, count 0 2006.286.04:16:08.54#ibcon#enter sib2, iclass 18, count 0 2006.286.04:16:08.54#ibcon#flushed, iclass 18, count 0 2006.286.04:16:08.54#ibcon#about to write, iclass 18, count 0 2006.286.04:16:08.54#ibcon#wrote, iclass 18, count 0 2006.286.04:16:08.54#ibcon#about to read 3, iclass 18, count 0 2006.286.04:16:08.57#ibcon#read 3, iclass 18, count 0 2006.286.04:16:08.57#ibcon#about to read 4, iclass 18, count 0 2006.286.04:16:08.57#ibcon#read 4, iclass 18, count 0 2006.286.04:16:08.57#ibcon#about to read 5, iclass 18, count 0 2006.286.04:16:08.57#ibcon#read 5, iclass 18, count 0 2006.286.04:16:08.57#ibcon#about to read 6, iclass 18, count 0 2006.286.04:16:08.57#ibcon#read 6, iclass 18, count 0 2006.286.04:16:08.57#ibcon#end of sib2, iclass 18, count 0 2006.286.04:16:08.57#ibcon#*after write, iclass 18, count 0 2006.286.04:16:08.57#ibcon#*before return 0, iclass 18, count 0 2006.286.04:16:08.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:16:08.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:16:08.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:16:08.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:16:08.57$vck44/valo=6,814.99 2006.286.04:16:08.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.04:16:08.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.04:16:08.57#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:08.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:16:08.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:16:08.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:16:08.57#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:16:08.57#ibcon#first serial, iclass 20, count 0 2006.286.04:16:08.57#ibcon#enter sib2, iclass 20, count 0 2006.286.04:16:08.57#ibcon#flushed, iclass 20, count 0 2006.286.04:16:08.57#ibcon#about to write, iclass 20, count 0 2006.286.04:16:08.57#ibcon#wrote, iclass 20, count 0 2006.286.04:16:08.57#ibcon#about to read 3, iclass 20, count 0 2006.286.04:16:08.59#ibcon#read 3, iclass 20, count 0 2006.286.04:16:08.59#ibcon#about to read 4, iclass 20, count 0 2006.286.04:16:08.59#ibcon#read 4, iclass 20, count 0 2006.286.04:16:08.59#ibcon#about to read 5, iclass 20, count 0 2006.286.04:16:08.59#ibcon#read 5, iclass 20, count 0 2006.286.04:16:08.59#ibcon#about to read 6, iclass 20, count 0 2006.286.04:16:08.59#ibcon#read 6, iclass 20, count 0 2006.286.04:16:08.59#ibcon#end of sib2, iclass 20, count 0 2006.286.04:16:08.59#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:16:08.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:16:08.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:16:08.59#ibcon#*before write, iclass 20, count 0 2006.286.04:16:08.59#ibcon#enter sib2, iclass 20, count 0 2006.286.04:16:08.59#ibcon#flushed, iclass 20, count 0 2006.286.04:16:08.59#ibcon#about to write, iclass 20, count 0 2006.286.04:16:08.59#ibcon#wrote, iclass 20, count 0 2006.286.04:16:08.59#ibcon#about to read 3, iclass 20, count 0 2006.286.04:16:08.63#ibcon#read 3, iclass 20, count 0 2006.286.04:16:08.63#ibcon#about to read 4, iclass 20, count 0 2006.286.04:16:08.63#ibcon#read 4, iclass 20, count 0 2006.286.04:16:08.63#ibcon#about to read 5, iclass 20, count 0 2006.286.04:16:08.63#ibcon#read 5, iclass 20, count 0 2006.286.04:16:08.63#ibcon#about to read 6, iclass 20, count 0 2006.286.04:16:08.63#ibcon#read 6, iclass 20, count 0 2006.286.04:16:08.63#ibcon#end of sib2, iclass 20, count 0 2006.286.04:16:08.63#ibcon#*after write, iclass 20, count 0 2006.286.04:16:08.63#ibcon#*before return 0, iclass 20, count 0 2006.286.04:16:08.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:16:08.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:16:08.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:16:08.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:16:08.63$vck44/va=6,4 2006.286.04:16:08.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.04:16:08.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.04:16:08.63#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:08.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:16:08.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:16:08.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:16:08.69#ibcon#enter wrdev, iclass 22, count 2 2006.286.04:16:08.69#ibcon#first serial, iclass 22, count 2 2006.286.04:16:08.69#ibcon#enter sib2, iclass 22, count 2 2006.286.04:16:08.69#ibcon#flushed, iclass 22, count 2 2006.286.04:16:08.69#ibcon#about to write, iclass 22, count 2 2006.286.04:16:08.69#ibcon#wrote, iclass 22, count 2 2006.286.04:16:08.69#ibcon#about to read 3, iclass 22, count 2 2006.286.04:16:08.71#ibcon#read 3, iclass 22, count 2 2006.286.04:16:08.71#ibcon#about to read 4, iclass 22, count 2 2006.286.04:16:08.71#ibcon#read 4, iclass 22, count 2 2006.286.04:16:08.71#ibcon#about to read 5, iclass 22, count 2 2006.286.04:16:08.71#ibcon#read 5, iclass 22, count 2 2006.286.04:16:08.71#ibcon#about to read 6, iclass 22, count 2 2006.286.04:16:08.71#ibcon#read 6, iclass 22, count 2 2006.286.04:16:08.71#ibcon#end of sib2, iclass 22, count 2 2006.286.04:16:08.71#ibcon#*mode == 0, iclass 22, count 2 2006.286.04:16:08.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.04:16:08.71#ibcon#[25=AT06-04\r\n] 2006.286.04:16:08.71#ibcon#*before write, iclass 22, count 2 2006.286.04:16:08.71#ibcon#enter sib2, iclass 22, count 2 2006.286.04:16:08.71#ibcon#flushed, iclass 22, count 2 2006.286.04:16:08.71#ibcon#about to write, iclass 22, count 2 2006.286.04:16:08.71#ibcon#wrote, iclass 22, count 2 2006.286.04:16:08.71#ibcon#about to read 3, iclass 22, count 2 2006.286.04:16:08.74#ibcon#read 3, iclass 22, count 2 2006.286.04:16:08.74#ibcon#about to read 4, iclass 22, count 2 2006.286.04:16:08.74#ibcon#read 4, iclass 22, count 2 2006.286.04:16:08.74#ibcon#about to read 5, iclass 22, count 2 2006.286.04:16:08.74#ibcon#read 5, iclass 22, count 2 2006.286.04:16:08.74#ibcon#about to read 6, iclass 22, count 2 2006.286.04:16:08.74#ibcon#read 6, iclass 22, count 2 2006.286.04:16:08.74#ibcon#end of sib2, iclass 22, count 2 2006.286.04:16:08.74#ibcon#*after write, iclass 22, count 2 2006.286.04:16:08.74#ibcon#*before return 0, iclass 22, count 2 2006.286.04:16:08.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:16:08.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:16:08.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.04:16:08.74#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:08.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:16:08.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:16:08.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:16:08.86#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:16:08.86#ibcon#first serial, iclass 22, count 0 2006.286.04:16:08.86#ibcon#enter sib2, iclass 22, count 0 2006.286.04:16:08.86#ibcon#flushed, iclass 22, count 0 2006.286.04:16:08.86#ibcon#about to write, iclass 22, count 0 2006.286.04:16:08.86#ibcon#wrote, iclass 22, count 0 2006.286.04:16:08.86#ibcon#about to read 3, iclass 22, count 0 2006.286.04:16:08.88#ibcon#read 3, iclass 22, count 0 2006.286.04:16:08.88#ibcon#about to read 4, iclass 22, count 0 2006.286.04:16:08.88#ibcon#read 4, iclass 22, count 0 2006.286.04:16:08.88#ibcon#about to read 5, iclass 22, count 0 2006.286.04:16:08.88#ibcon#read 5, iclass 22, count 0 2006.286.04:16:08.88#ibcon#about to read 6, iclass 22, count 0 2006.286.04:16:08.88#ibcon#read 6, iclass 22, count 0 2006.286.04:16:08.88#ibcon#end of sib2, iclass 22, count 0 2006.286.04:16:08.88#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:16:08.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:16:08.88#ibcon#[25=USB\r\n] 2006.286.04:16:08.88#ibcon#*before write, iclass 22, count 0 2006.286.04:16:08.88#ibcon#enter sib2, iclass 22, count 0 2006.286.04:16:08.88#ibcon#flushed, iclass 22, count 0 2006.286.04:16:08.88#ibcon#about to write, iclass 22, count 0 2006.286.04:16:08.88#ibcon#wrote, iclass 22, count 0 2006.286.04:16:08.88#ibcon#about to read 3, iclass 22, count 0 2006.286.04:16:08.91#ibcon#read 3, iclass 22, count 0 2006.286.04:16:08.91#ibcon#about to read 4, iclass 22, count 0 2006.286.04:16:08.91#ibcon#read 4, iclass 22, count 0 2006.286.04:16:08.91#ibcon#about to read 5, iclass 22, count 0 2006.286.04:16:08.91#ibcon#read 5, iclass 22, count 0 2006.286.04:16:08.91#ibcon#about to read 6, iclass 22, count 0 2006.286.04:16:08.91#ibcon#read 6, iclass 22, count 0 2006.286.04:16:08.91#ibcon#end of sib2, iclass 22, count 0 2006.286.04:16:08.91#ibcon#*after write, iclass 22, count 0 2006.286.04:16:08.91#ibcon#*before return 0, iclass 22, count 0 2006.286.04:16:08.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:16:08.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:16:08.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:16:08.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:16:08.91$vck44/valo=7,864.99 2006.286.04:16:08.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.04:16:08.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.04:16:08.91#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:08.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:16:08.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:16:08.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:16:08.91#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:16:08.91#ibcon#first serial, iclass 24, count 0 2006.286.04:16:08.91#ibcon#enter sib2, iclass 24, count 0 2006.286.04:16:08.91#ibcon#flushed, iclass 24, count 0 2006.286.04:16:08.91#ibcon#about to write, iclass 24, count 0 2006.286.04:16:08.91#ibcon#wrote, iclass 24, count 0 2006.286.04:16:08.91#ibcon#about to read 3, iclass 24, count 0 2006.286.04:16:08.93#ibcon#read 3, iclass 24, count 0 2006.286.04:16:08.93#ibcon#about to read 4, iclass 24, count 0 2006.286.04:16:08.93#ibcon#read 4, iclass 24, count 0 2006.286.04:16:08.93#ibcon#about to read 5, iclass 24, count 0 2006.286.04:16:08.93#ibcon#read 5, iclass 24, count 0 2006.286.04:16:08.93#ibcon#about to read 6, iclass 24, count 0 2006.286.04:16:08.93#ibcon#read 6, iclass 24, count 0 2006.286.04:16:08.93#ibcon#end of sib2, iclass 24, count 0 2006.286.04:16:08.93#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:16:08.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:16:08.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:16:08.93#ibcon#*before write, iclass 24, count 0 2006.286.04:16:08.93#ibcon#enter sib2, iclass 24, count 0 2006.286.04:16:08.93#ibcon#flushed, iclass 24, count 0 2006.286.04:16:08.93#ibcon#about to write, iclass 24, count 0 2006.286.04:16:08.93#ibcon#wrote, iclass 24, count 0 2006.286.04:16:08.93#ibcon#about to read 3, iclass 24, count 0 2006.286.04:16:08.97#ibcon#read 3, iclass 24, count 0 2006.286.04:16:08.97#ibcon#about to read 4, iclass 24, count 0 2006.286.04:16:08.97#ibcon#read 4, iclass 24, count 0 2006.286.04:16:08.97#ibcon#about to read 5, iclass 24, count 0 2006.286.04:16:08.97#ibcon#read 5, iclass 24, count 0 2006.286.04:16:08.97#ibcon#about to read 6, iclass 24, count 0 2006.286.04:16:08.97#ibcon#read 6, iclass 24, count 0 2006.286.04:16:08.97#ibcon#end of sib2, iclass 24, count 0 2006.286.04:16:08.97#ibcon#*after write, iclass 24, count 0 2006.286.04:16:08.97#ibcon#*before return 0, iclass 24, count 0 2006.286.04:16:08.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:16:08.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:16:08.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:16:08.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:16:08.97$vck44/va=7,4 2006.286.04:16:08.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.04:16:08.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.04:16:08.97#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:08.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:16:09.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:16:09.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:16:09.03#ibcon#enter wrdev, iclass 26, count 2 2006.286.04:16:09.03#ibcon#first serial, iclass 26, count 2 2006.286.04:16:09.03#ibcon#enter sib2, iclass 26, count 2 2006.286.04:16:09.03#ibcon#flushed, iclass 26, count 2 2006.286.04:16:09.03#ibcon#about to write, iclass 26, count 2 2006.286.04:16:09.03#ibcon#wrote, iclass 26, count 2 2006.286.04:16:09.03#ibcon#about to read 3, iclass 26, count 2 2006.286.04:16:09.05#ibcon#read 3, iclass 26, count 2 2006.286.04:16:09.05#ibcon#about to read 4, iclass 26, count 2 2006.286.04:16:09.05#ibcon#read 4, iclass 26, count 2 2006.286.04:16:09.05#ibcon#about to read 5, iclass 26, count 2 2006.286.04:16:09.05#ibcon#read 5, iclass 26, count 2 2006.286.04:16:09.05#ibcon#about to read 6, iclass 26, count 2 2006.286.04:16:09.05#ibcon#read 6, iclass 26, count 2 2006.286.04:16:09.05#ibcon#end of sib2, iclass 26, count 2 2006.286.04:16:09.05#ibcon#*mode == 0, iclass 26, count 2 2006.286.04:16:09.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.04:16:09.05#ibcon#[25=AT07-04\r\n] 2006.286.04:16:09.05#ibcon#*before write, iclass 26, count 2 2006.286.04:16:09.05#ibcon#enter sib2, iclass 26, count 2 2006.286.04:16:09.05#ibcon#flushed, iclass 26, count 2 2006.286.04:16:09.05#ibcon#about to write, iclass 26, count 2 2006.286.04:16:09.05#ibcon#wrote, iclass 26, count 2 2006.286.04:16:09.05#ibcon#about to read 3, iclass 26, count 2 2006.286.04:16:09.08#ibcon#read 3, iclass 26, count 2 2006.286.04:16:09.08#ibcon#about to read 4, iclass 26, count 2 2006.286.04:16:09.08#ibcon#read 4, iclass 26, count 2 2006.286.04:16:09.08#ibcon#about to read 5, iclass 26, count 2 2006.286.04:16:09.08#ibcon#read 5, iclass 26, count 2 2006.286.04:16:09.08#ibcon#about to read 6, iclass 26, count 2 2006.286.04:16:09.08#ibcon#read 6, iclass 26, count 2 2006.286.04:16:09.08#ibcon#end of sib2, iclass 26, count 2 2006.286.04:16:09.08#ibcon#*after write, iclass 26, count 2 2006.286.04:16:09.08#ibcon#*before return 0, iclass 26, count 2 2006.286.04:16:09.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:16:09.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:16:09.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.04:16:09.08#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:09.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:16:09.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:16:09.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:16:09.20#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:16:09.20#ibcon#first serial, iclass 26, count 0 2006.286.04:16:09.20#ibcon#enter sib2, iclass 26, count 0 2006.286.04:16:09.20#ibcon#flushed, iclass 26, count 0 2006.286.04:16:09.20#ibcon#about to write, iclass 26, count 0 2006.286.04:16:09.20#ibcon#wrote, iclass 26, count 0 2006.286.04:16:09.20#ibcon#about to read 3, iclass 26, count 0 2006.286.04:16:09.22#ibcon#read 3, iclass 26, count 0 2006.286.04:16:09.22#ibcon#about to read 4, iclass 26, count 0 2006.286.04:16:09.22#ibcon#read 4, iclass 26, count 0 2006.286.04:16:09.22#ibcon#about to read 5, iclass 26, count 0 2006.286.04:16:09.22#ibcon#read 5, iclass 26, count 0 2006.286.04:16:09.22#ibcon#about to read 6, iclass 26, count 0 2006.286.04:16:09.22#ibcon#read 6, iclass 26, count 0 2006.286.04:16:09.22#ibcon#end of sib2, iclass 26, count 0 2006.286.04:16:09.22#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:16:09.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:16:09.22#ibcon#[25=USB\r\n] 2006.286.04:16:09.22#ibcon#*before write, iclass 26, count 0 2006.286.04:16:09.22#ibcon#enter sib2, iclass 26, count 0 2006.286.04:16:09.22#ibcon#flushed, iclass 26, count 0 2006.286.04:16:09.22#ibcon#about to write, iclass 26, count 0 2006.286.04:16:09.22#ibcon#wrote, iclass 26, count 0 2006.286.04:16:09.22#ibcon#about to read 3, iclass 26, count 0 2006.286.04:16:09.25#ibcon#read 3, iclass 26, count 0 2006.286.04:16:09.25#ibcon#about to read 4, iclass 26, count 0 2006.286.04:16:09.25#ibcon#read 4, iclass 26, count 0 2006.286.04:16:09.25#ibcon#about to read 5, iclass 26, count 0 2006.286.04:16:09.25#ibcon#read 5, iclass 26, count 0 2006.286.04:16:09.25#ibcon#about to read 6, iclass 26, count 0 2006.286.04:16:09.25#ibcon#read 6, iclass 26, count 0 2006.286.04:16:09.25#ibcon#end of sib2, iclass 26, count 0 2006.286.04:16:09.25#ibcon#*after write, iclass 26, count 0 2006.286.04:16:09.25#ibcon#*before return 0, iclass 26, count 0 2006.286.04:16:09.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:16:09.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:16:09.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:16:09.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:16:09.25$vck44/valo=8,884.99 2006.286.04:16:09.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.04:16:09.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.04:16:09.25#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:09.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:16:09.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:16:09.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:16:09.25#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:16:09.25#ibcon#first serial, iclass 28, count 0 2006.286.04:16:09.25#ibcon#enter sib2, iclass 28, count 0 2006.286.04:16:09.25#ibcon#flushed, iclass 28, count 0 2006.286.04:16:09.25#ibcon#about to write, iclass 28, count 0 2006.286.04:16:09.25#ibcon#wrote, iclass 28, count 0 2006.286.04:16:09.25#ibcon#about to read 3, iclass 28, count 0 2006.286.04:16:09.27#ibcon#read 3, iclass 28, count 0 2006.286.04:16:09.27#ibcon#about to read 4, iclass 28, count 0 2006.286.04:16:09.27#ibcon#read 4, iclass 28, count 0 2006.286.04:16:09.27#ibcon#about to read 5, iclass 28, count 0 2006.286.04:16:09.27#ibcon#read 5, iclass 28, count 0 2006.286.04:16:09.27#ibcon#about to read 6, iclass 28, count 0 2006.286.04:16:09.27#ibcon#read 6, iclass 28, count 0 2006.286.04:16:09.27#ibcon#end of sib2, iclass 28, count 0 2006.286.04:16:09.27#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:16:09.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:16:09.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:16:09.27#ibcon#*before write, iclass 28, count 0 2006.286.04:16:09.27#ibcon#enter sib2, iclass 28, count 0 2006.286.04:16:09.27#ibcon#flushed, iclass 28, count 0 2006.286.04:16:09.27#ibcon#about to write, iclass 28, count 0 2006.286.04:16:09.27#ibcon#wrote, iclass 28, count 0 2006.286.04:16:09.27#ibcon#about to read 3, iclass 28, count 0 2006.286.04:16:09.31#ibcon#read 3, iclass 28, count 0 2006.286.04:16:09.31#ibcon#about to read 4, iclass 28, count 0 2006.286.04:16:09.31#ibcon#read 4, iclass 28, count 0 2006.286.04:16:09.31#ibcon#about to read 5, iclass 28, count 0 2006.286.04:16:09.31#ibcon#read 5, iclass 28, count 0 2006.286.04:16:09.31#ibcon#about to read 6, iclass 28, count 0 2006.286.04:16:09.31#ibcon#read 6, iclass 28, count 0 2006.286.04:16:09.31#ibcon#end of sib2, iclass 28, count 0 2006.286.04:16:09.31#ibcon#*after write, iclass 28, count 0 2006.286.04:16:09.31#ibcon#*before return 0, iclass 28, count 0 2006.286.04:16:09.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:16:09.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:16:09.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:16:09.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:16:09.31$vck44/va=8,3 2006.286.04:16:09.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.04:16:09.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.04:16:09.31#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:09.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:16:09.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:16:09.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:16:09.37#ibcon#enter wrdev, iclass 30, count 2 2006.286.04:16:09.37#ibcon#first serial, iclass 30, count 2 2006.286.04:16:09.37#ibcon#enter sib2, iclass 30, count 2 2006.286.04:16:09.37#ibcon#flushed, iclass 30, count 2 2006.286.04:16:09.37#ibcon#about to write, iclass 30, count 2 2006.286.04:16:09.37#ibcon#wrote, iclass 30, count 2 2006.286.04:16:09.37#ibcon#about to read 3, iclass 30, count 2 2006.286.04:16:09.39#ibcon#read 3, iclass 30, count 2 2006.286.04:16:09.39#ibcon#about to read 4, iclass 30, count 2 2006.286.04:16:09.39#ibcon#read 4, iclass 30, count 2 2006.286.04:16:09.39#ibcon#about to read 5, iclass 30, count 2 2006.286.04:16:09.39#ibcon#read 5, iclass 30, count 2 2006.286.04:16:09.39#ibcon#about to read 6, iclass 30, count 2 2006.286.04:16:09.39#ibcon#read 6, iclass 30, count 2 2006.286.04:16:09.39#ibcon#end of sib2, iclass 30, count 2 2006.286.04:16:09.39#ibcon#*mode == 0, iclass 30, count 2 2006.286.04:16:09.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.04:16:09.39#ibcon#[25=AT08-03\r\n] 2006.286.04:16:09.39#ibcon#*before write, iclass 30, count 2 2006.286.04:16:09.39#ibcon#enter sib2, iclass 30, count 2 2006.286.04:16:09.39#ibcon#flushed, iclass 30, count 2 2006.286.04:16:09.39#ibcon#about to write, iclass 30, count 2 2006.286.04:16:09.39#ibcon#wrote, iclass 30, count 2 2006.286.04:16:09.39#ibcon#about to read 3, iclass 30, count 2 2006.286.04:16:09.42#ibcon#read 3, iclass 30, count 2 2006.286.04:16:09.42#ibcon#about to read 4, iclass 30, count 2 2006.286.04:16:09.42#ibcon#read 4, iclass 30, count 2 2006.286.04:16:09.42#ibcon#about to read 5, iclass 30, count 2 2006.286.04:16:09.42#ibcon#read 5, iclass 30, count 2 2006.286.04:16:09.42#ibcon#about to read 6, iclass 30, count 2 2006.286.04:16:09.42#ibcon#read 6, iclass 30, count 2 2006.286.04:16:09.42#ibcon#end of sib2, iclass 30, count 2 2006.286.04:16:09.42#ibcon#*after write, iclass 30, count 2 2006.286.04:16:09.42#ibcon#*before return 0, iclass 30, count 2 2006.286.04:16:09.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:16:09.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:16:09.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.04:16:09.42#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:09.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:16:09.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:16:09.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:16:09.57#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:16:09.57#ibcon#first serial, iclass 30, count 0 2006.286.04:16:09.57#ibcon#enter sib2, iclass 30, count 0 2006.286.04:16:09.57#ibcon#flushed, iclass 30, count 0 2006.286.04:16:09.57#ibcon#about to write, iclass 30, count 0 2006.286.04:16:09.57#ibcon#wrote, iclass 30, count 0 2006.286.04:16:09.57#ibcon#about to read 3, iclass 30, count 0 2006.286.04:16:09.59#ibcon#read 3, iclass 30, count 0 2006.286.04:16:09.59#ibcon#about to read 4, iclass 30, count 0 2006.286.04:16:09.59#ibcon#read 4, iclass 30, count 0 2006.286.04:16:09.59#ibcon#about to read 5, iclass 30, count 0 2006.286.04:16:09.59#ibcon#read 5, iclass 30, count 0 2006.286.04:16:09.59#ibcon#about to read 6, iclass 30, count 0 2006.286.04:16:09.59#ibcon#read 6, iclass 30, count 0 2006.286.04:16:09.59#ibcon#end of sib2, iclass 30, count 0 2006.286.04:16:09.59#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:16:09.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:16:09.59#ibcon#[25=USB\r\n] 2006.286.04:16:09.59#ibcon#*before write, iclass 30, count 0 2006.286.04:16:09.59#ibcon#enter sib2, iclass 30, count 0 2006.286.04:16:09.59#ibcon#flushed, iclass 30, count 0 2006.286.04:16:09.59#ibcon#about to write, iclass 30, count 0 2006.286.04:16:09.59#ibcon#wrote, iclass 30, count 0 2006.286.04:16:09.59#ibcon#about to read 3, iclass 30, count 0 2006.286.04:16:09.62#ibcon#read 3, iclass 30, count 0 2006.286.04:16:09.62#ibcon#about to read 4, iclass 30, count 0 2006.286.04:16:09.62#ibcon#read 4, iclass 30, count 0 2006.286.04:16:09.62#ibcon#about to read 5, iclass 30, count 0 2006.286.04:16:09.62#ibcon#read 5, iclass 30, count 0 2006.286.04:16:09.62#ibcon#about to read 6, iclass 30, count 0 2006.286.04:16:09.62#ibcon#read 6, iclass 30, count 0 2006.286.04:16:09.62#ibcon#end of sib2, iclass 30, count 0 2006.286.04:16:09.62#ibcon#*after write, iclass 30, count 0 2006.286.04:16:09.62#ibcon#*before return 0, iclass 30, count 0 2006.286.04:16:09.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:16:09.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:16:09.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:16:09.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:16:09.62$vck44/vblo=1,629.99 2006.286.04:16:09.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.04:16:09.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.04:16:09.62#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:09.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:16:09.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:16:09.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:16:09.62#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:16:09.62#ibcon#first serial, iclass 32, count 0 2006.286.04:16:09.62#ibcon#enter sib2, iclass 32, count 0 2006.286.04:16:09.62#ibcon#flushed, iclass 32, count 0 2006.286.04:16:09.62#ibcon#about to write, iclass 32, count 0 2006.286.04:16:09.62#ibcon#wrote, iclass 32, count 0 2006.286.04:16:09.62#ibcon#about to read 3, iclass 32, count 0 2006.286.04:16:09.64#ibcon#read 3, iclass 32, count 0 2006.286.04:16:09.64#ibcon#about to read 4, iclass 32, count 0 2006.286.04:16:09.64#ibcon#read 4, iclass 32, count 0 2006.286.04:16:09.64#ibcon#about to read 5, iclass 32, count 0 2006.286.04:16:09.64#ibcon#read 5, iclass 32, count 0 2006.286.04:16:09.64#ibcon#about to read 6, iclass 32, count 0 2006.286.04:16:09.64#ibcon#read 6, iclass 32, count 0 2006.286.04:16:09.64#ibcon#end of sib2, iclass 32, count 0 2006.286.04:16:09.64#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:16:09.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:16:09.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:16:09.64#ibcon#*before write, iclass 32, count 0 2006.286.04:16:09.64#ibcon#enter sib2, iclass 32, count 0 2006.286.04:16:09.64#ibcon#flushed, iclass 32, count 0 2006.286.04:16:09.64#ibcon#about to write, iclass 32, count 0 2006.286.04:16:09.64#ibcon#wrote, iclass 32, count 0 2006.286.04:16:09.64#ibcon#about to read 3, iclass 32, count 0 2006.286.04:16:09.68#ibcon#read 3, iclass 32, count 0 2006.286.04:16:09.68#ibcon#about to read 4, iclass 32, count 0 2006.286.04:16:09.68#ibcon#read 4, iclass 32, count 0 2006.286.04:16:09.68#ibcon#about to read 5, iclass 32, count 0 2006.286.04:16:09.68#ibcon#read 5, iclass 32, count 0 2006.286.04:16:09.68#ibcon#about to read 6, iclass 32, count 0 2006.286.04:16:09.68#ibcon#read 6, iclass 32, count 0 2006.286.04:16:09.68#ibcon#end of sib2, iclass 32, count 0 2006.286.04:16:09.68#ibcon#*after write, iclass 32, count 0 2006.286.04:16:09.68#ibcon#*before return 0, iclass 32, count 0 2006.286.04:16:09.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:16:09.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:16:09.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:16:09.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:16:09.68$vck44/vb=1,4 2006.286.04:16:09.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.04:16:09.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.04:16:09.68#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:09.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:16:09.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:16:09.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:16:09.68#ibcon#enter wrdev, iclass 34, count 2 2006.286.04:16:09.68#ibcon#first serial, iclass 34, count 2 2006.286.04:16:09.68#ibcon#enter sib2, iclass 34, count 2 2006.286.04:16:09.68#ibcon#flushed, iclass 34, count 2 2006.286.04:16:09.68#ibcon#about to write, iclass 34, count 2 2006.286.04:16:09.68#ibcon#wrote, iclass 34, count 2 2006.286.04:16:09.68#ibcon#about to read 3, iclass 34, count 2 2006.286.04:16:09.70#ibcon#read 3, iclass 34, count 2 2006.286.04:16:09.70#ibcon#about to read 4, iclass 34, count 2 2006.286.04:16:09.70#ibcon#read 4, iclass 34, count 2 2006.286.04:16:09.70#ibcon#about to read 5, iclass 34, count 2 2006.286.04:16:09.70#ibcon#read 5, iclass 34, count 2 2006.286.04:16:09.70#ibcon#about to read 6, iclass 34, count 2 2006.286.04:16:09.70#ibcon#read 6, iclass 34, count 2 2006.286.04:16:09.70#ibcon#end of sib2, iclass 34, count 2 2006.286.04:16:09.70#ibcon#*mode == 0, iclass 34, count 2 2006.286.04:16:09.70#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.04:16:09.70#ibcon#[27=AT01-04\r\n] 2006.286.04:16:09.70#ibcon#*before write, iclass 34, count 2 2006.286.04:16:09.70#ibcon#enter sib2, iclass 34, count 2 2006.286.04:16:09.70#ibcon#flushed, iclass 34, count 2 2006.286.04:16:09.70#ibcon#about to write, iclass 34, count 2 2006.286.04:16:09.70#ibcon#wrote, iclass 34, count 2 2006.286.04:16:09.70#ibcon#about to read 3, iclass 34, count 2 2006.286.04:16:09.73#ibcon#read 3, iclass 34, count 2 2006.286.04:16:09.73#ibcon#about to read 4, iclass 34, count 2 2006.286.04:16:09.73#ibcon#read 4, iclass 34, count 2 2006.286.04:16:09.73#ibcon#about to read 5, iclass 34, count 2 2006.286.04:16:09.73#ibcon#read 5, iclass 34, count 2 2006.286.04:16:09.73#ibcon#about to read 6, iclass 34, count 2 2006.286.04:16:09.73#ibcon#read 6, iclass 34, count 2 2006.286.04:16:09.73#ibcon#end of sib2, iclass 34, count 2 2006.286.04:16:09.73#ibcon#*after write, iclass 34, count 2 2006.286.04:16:09.73#ibcon#*before return 0, iclass 34, count 2 2006.286.04:16:09.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:16:09.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:16:09.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.04:16:09.73#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:09.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:16:09.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:16:09.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:16:09.85#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:16:09.85#ibcon#first serial, iclass 34, count 0 2006.286.04:16:09.85#ibcon#enter sib2, iclass 34, count 0 2006.286.04:16:09.85#ibcon#flushed, iclass 34, count 0 2006.286.04:16:09.85#ibcon#about to write, iclass 34, count 0 2006.286.04:16:09.85#ibcon#wrote, iclass 34, count 0 2006.286.04:16:09.85#ibcon#about to read 3, iclass 34, count 0 2006.286.04:16:09.87#ibcon#read 3, iclass 34, count 0 2006.286.04:16:09.87#ibcon#about to read 4, iclass 34, count 0 2006.286.04:16:09.87#ibcon#read 4, iclass 34, count 0 2006.286.04:16:09.87#ibcon#about to read 5, iclass 34, count 0 2006.286.04:16:09.87#ibcon#read 5, iclass 34, count 0 2006.286.04:16:09.87#ibcon#about to read 6, iclass 34, count 0 2006.286.04:16:09.87#ibcon#read 6, iclass 34, count 0 2006.286.04:16:09.87#ibcon#end of sib2, iclass 34, count 0 2006.286.04:16:09.87#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:16:09.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:16:09.87#ibcon#[27=USB\r\n] 2006.286.04:16:09.87#ibcon#*before write, iclass 34, count 0 2006.286.04:16:09.87#ibcon#enter sib2, iclass 34, count 0 2006.286.04:16:09.87#ibcon#flushed, iclass 34, count 0 2006.286.04:16:09.87#ibcon#about to write, iclass 34, count 0 2006.286.04:16:09.87#ibcon#wrote, iclass 34, count 0 2006.286.04:16:09.87#ibcon#about to read 3, iclass 34, count 0 2006.286.04:16:09.90#ibcon#read 3, iclass 34, count 0 2006.286.04:16:09.90#ibcon#about to read 4, iclass 34, count 0 2006.286.04:16:09.90#ibcon#read 4, iclass 34, count 0 2006.286.04:16:09.90#ibcon#about to read 5, iclass 34, count 0 2006.286.04:16:09.90#ibcon#read 5, iclass 34, count 0 2006.286.04:16:09.90#ibcon#about to read 6, iclass 34, count 0 2006.286.04:16:09.90#ibcon#read 6, iclass 34, count 0 2006.286.04:16:09.90#ibcon#end of sib2, iclass 34, count 0 2006.286.04:16:09.90#ibcon#*after write, iclass 34, count 0 2006.286.04:16:09.90#ibcon#*before return 0, iclass 34, count 0 2006.286.04:16:09.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:16:09.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:16:09.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:16:09.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:16:09.90$vck44/vblo=2,634.99 2006.286.04:16:09.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.04:16:09.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.04:16:09.90#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:09.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:16:09.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:16:09.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:16:09.90#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:16:09.90#ibcon#first serial, iclass 36, count 0 2006.286.04:16:09.90#ibcon#enter sib2, iclass 36, count 0 2006.286.04:16:09.90#ibcon#flushed, iclass 36, count 0 2006.286.04:16:09.90#ibcon#about to write, iclass 36, count 0 2006.286.04:16:09.90#ibcon#wrote, iclass 36, count 0 2006.286.04:16:09.90#ibcon#about to read 3, iclass 36, count 0 2006.286.04:16:09.92#ibcon#read 3, iclass 36, count 0 2006.286.04:16:09.92#ibcon#about to read 4, iclass 36, count 0 2006.286.04:16:09.92#ibcon#read 4, iclass 36, count 0 2006.286.04:16:09.92#ibcon#about to read 5, iclass 36, count 0 2006.286.04:16:09.92#ibcon#read 5, iclass 36, count 0 2006.286.04:16:09.92#ibcon#about to read 6, iclass 36, count 0 2006.286.04:16:09.92#ibcon#read 6, iclass 36, count 0 2006.286.04:16:09.92#ibcon#end of sib2, iclass 36, count 0 2006.286.04:16:09.92#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:16:09.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:16:09.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:16:09.92#ibcon#*before write, iclass 36, count 0 2006.286.04:16:09.92#ibcon#enter sib2, iclass 36, count 0 2006.286.04:16:09.92#ibcon#flushed, iclass 36, count 0 2006.286.04:16:09.92#ibcon#about to write, iclass 36, count 0 2006.286.04:16:09.92#ibcon#wrote, iclass 36, count 0 2006.286.04:16:09.92#ibcon#about to read 3, iclass 36, count 0 2006.286.04:16:09.96#ibcon#read 3, iclass 36, count 0 2006.286.04:16:09.96#ibcon#about to read 4, iclass 36, count 0 2006.286.04:16:09.96#ibcon#read 4, iclass 36, count 0 2006.286.04:16:09.96#ibcon#about to read 5, iclass 36, count 0 2006.286.04:16:09.96#ibcon#read 5, iclass 36, count 0 2006.286.04:16:09.96#ibcon#about to read 6, iclass 36, count 0 2006.286.04:16:09.96#ibcon#read 6, iclass 36, count 0 2006.286.04:16:09.96#ibcon#end of sib2, iclass 36, count 0 2006.286.04:16:09.96#ibcon#*after write, iclass 36, count 0 2006.286.04:16:09.96#ibcon#*before return 0, iclass 36, count 0 2006.286.04:16:09.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:16:09.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:16:09.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:16:09.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:16:09.96$vck44/vb=2,5 2006.286.04:16:09.96#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.04:16:09.96#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.04:16:09.96#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:09.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:16:10.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:16:10.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:16:10.02#ibcon#enter wrdev, iclass 38, count 2 2006.286.04:16:10.02#ibcon#first serial, iclass 38, count 2 2006.286.04:16:10.02#ibcon#enter sib2, iclass 38, count 2 2006.286.04:16:10.02#ibcon#flushed, iclass 38, count 2 2006.286.04:16:10.02#ibcon#about to write, iclass 38, count 2 2006.286.04:16:10.02#ibcon#wrote, iclass 38, count 2 2006.286.04:16:10.02#ibcon#about to read 3, iclass 38, count 2 2006.286.04:16:10.04#ibcon#read 3, iclass 38, count 2 2006.286.04:16:10.04#ibcon#about to read 4, iclass 38, count 2 2006.286.04:16:10.04#ibcon#read 4, iclass 38, count 2 2006.286.04:16:10.04#ibcon#about to read 5, iclass 38, count 2 2006.286.04:16:10.04#ibcon#read 5, iclass 38, count 2 2006.286.04:16:10.04#ibcon#about to read 6, iclass 38, count 2 2006.286.04:16:10.04#ibcon#read 6, iclass 38, count 2 2006.286.04:16:10.04#ibcon#end of sib2, iclass 38, count 2 2006.286.04:16:10.04#ibcon#*mode == 0, iclass 38, count 2 2006.286.04:16:10.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.04:16:10.04#ibcon#[27=AT02-05\r\n] 2006.286.04:16:10.04#ibcon#*before write, iclass 38, count 2 2006.286.04:16:10.04#ibcon#enter sib2, iclass 38, count 2 2006.286.04:16:10.04#ibcon#flushed, iclass 38, count 2 2006.286.04:16:10.04#ibcon#about to write, iclass 38, count 2 2006.286.04:16:10.04#ibcon#wrote, iclass 38, count 2 2006.286.04:16:10.04#ibcon#about to read 3, iclass 38, count 2 2006.286.04:16:10.07#ibcon#read 3, iclass 38, count 2 2006.286.04:16:10.07#ibcon#about to read 4, iclass 38, count 2 2006.286.04:16:10.07#ibcon#read 4, iclass 38, count 2 2006.286.04:16:10.07#ibcon#about to read 5, iclass 38, count 2 2006.286.04:16:10.07#ibcon#read 5, iclass 38, count 2 2006.286.04:16:10.07#ibcon#about to read 6, iclass 38, count 2 2006.286.04:16:10.07#ibcon#read 6, iclass 38, count 2 2006.286.04:16:10.07#ibcon#end of sib2, iclass 38, count 2 2006.286.04:16:10.07#ibcon#*after write, iclass 38, count 2 2006.286.04:16:10.07#ibcon#*before return 0, iclass 38, count 2 2006.286.04:16:10.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:16:10.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:16:10.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.04:16:10.07#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:10.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:16:10.19#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:16:10.19#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:16:10.19#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:16:10.19#ibcon#first serial, iclass 38, count 0 2006.286.04:16:10.19#ibcon#enter sib2, iclass 38, count 0 2006.286.04:16:10.19#ibcon#flushed, iclass 38, count 0 2006.286.04:16:10.19#ibcon#about to write, iclass 38, count 0 2006.286.04:16:10.19#ibcon#wrote, iclass 38, count 0 2006.286.04:16:10.19#ibcon#about to read 3, iclass 38, count 0 2006.286.04:16:10.21#ibcon#read 3, iclass 38, count 0 2006.286.04:16:10.21#ibcon#about to read 4, iclass 38, count 0 2006.286.04:16:10.21#ibcon#read 4, iclass 38, count 0 2006.286.04:16:10.21#ibcon#about to read 5, iclass 38, count 0 2006.286.04:16:10.21#ibcon#read 5, iclass 38, count 0 2006.286.04:16:10.21#ibcon#about to read 6, iclass 38, count 0 2006.286.04:16:10.21#ibcon#read 6, iclass 38, count 0 2006.286.04:16:10.21#ibcon#end of sib2, iclass 38, count 0 2006.286.04:16:10.21#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:16:10.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:16:10.21#ibcon#[27=USB\r\n] 2006.286.04:16:10.21#ibcon#*before write, iclass 38, count 0 2006.286.04:16:10.21#ibcon#enter sib2, iclass 38, count 0 2006.286.04:16:10.21#ibcon#flushed, iclass 38, count 0 2006.286.04:16:10.21#ibcon#about to write, iclass 38, count 0 2006.286.04:16:10.21#ibcon#wrote, iclass 38, count 0 2006.286.04:16:10.21#ibcon#about to read 3, iclass 38, count 0 2006.286.04:16:10.24#ibcon#read 3, iclass 38, count 0 2006.286.04:16:10.24#ibcon#about to read 4, iclass 38, count 0 2006.286.04:16:10.24#ibcon#read 4, iclass 38, count 0 2006.286.04:16:10.24#ibcon#about to read 5, iclass 38, count 0 2006.286.04:16:10.24#ibcon#read 5, iclass 38, count 0 2006.286.04:16:10.24#ibcon#about to read 6, iclass 38, count 0 2006.286.04:16:10.24#ibcon#read 6, iclass 38, count 0 2006.286.04:16:10.24#ibcon#end of sib2, iclass 38, count 0 2006.286.04:16:10.24#ibcon#*after write, iclass 38, count 0 2006.286.04:16:10.24#ibcon#*before return 0, iclass 38, count 0 2006.286.04:16:10.24#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:16:10.24#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:16:10.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:16:10.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:16:10.24$vck44/vblo=3,649.99 2006.286.04:16:10.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.04:16:10.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.04:16:10.24#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:10.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:16:10.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:16:10.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:16:10.24#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:16:10.24#ibcon#first serial, iclass 40, count 0 2006.286.04:16:10.24#ibcon#enter sib2, iclass 40, count 0 2006.286.04:16:10.24#ibcon#flushed, iclass 40, count 0 2006.286.04:16:10.24#ibcon#about to write, iclass 40, count 0 2006.286.04:16:10.24#ibcon#wrote, iclass 40, count 0 2006.286.04:16:10.24#ibcon#about to read 3, iclass 40, count 0 2006.286.04:16:10.26#ibcon#read 3, iclass 40, count 0 2006.286.04:16:10.26#ibcon#about to read 4, iclass 40, count 0 2006.286.04:16:10.26#ibcon#read 4, iclass 40, count 0 2006.286.04:16:10.26#ibcon#about to read 5, iclass 40, count 0 2006.286.04:16:10.26#ibcon#read 5, iclass 40, count 0 2006.286.04:16:10.26#ibcon#about to read 6, iclass 40, count 0 2006.286.04:16:10.26#ibcon#read 6, iclass 40, count 0 2006.286.04:16:10.26#ibcon#end of sib2, iclass 40, count 0 2006.286.04:16:10.26#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:16:10.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:16:10.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:16:10.26#ibcon#*before write, iclass 40, count 0 2006.286.04:16:10.26#ibcon#enter sib2, iclass 40, count 0 2006.286.04:16:10.26#ibcon#flushed, iclass 40, count 0 2006.286.04:16:10.26#ibcon#about to write, iclass 40, count 0 2006.286.04:16:10.26#ibcon#wrote, iclass 40, count 0 2006.286.04:16:10.26#ibcon#about to read 3, iclass 40, count 0 2006.286.04:16:10.30#ibcon#read 3, iclass 40, count 0 2006.286.04:16:10.30#ibcon#about to read 4, iclass 40, count 0 2006.286.04:16:10.30#ibcon#read 4, iclass 40, count 0 2006.286.04:16:10.30#ibcon#about to read 5, iclass 40, count 0 2006.286.04:16:10.30#ibcon#read 5, iclass 40, count 0 2006.286.04:16:10.30#ibcon#about to read 6, iclass 40, count 0 2006.286.04:16:10.30#ibcon#read 6, iclass 40, count 0 2006.286.04:16:10.30#ibcon#end of sib2, iclass 40, count 0 2006.286.04:16:10.30#ibcon#*after write, iclass 40, count 0 2006.286.04:16:10.30#ibcon#*before return 0, iclass 40, count 0 2006.286.04:16:10.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:16:10.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:16:10.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:16:10.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:16:10.30$vck44/vb=3,4 2006.286.04:16:10.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.04:16:10.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.04:16:10.30#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:10.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:16:10.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:16:10.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:16:10.36#ibcon#enter wrdev, iclass 4, count 2 2006.286.04:16:10.36#ibcon#first serial, iclass 4, count 2 2006.286.04:16:10.36#ibcon#enter sib2, iclass 4, count 2 2006.286.04:16:10.36#ibcon#flushed, iclass 4, count 2 2006.286.04:16:10.36#ibcon#about to write, iclass 4, count 2 2006.286.04:16:10.36#ibcon#wrote, iclass 4, count 2 2006.286.04:16:10.36#ibcon#about to read 3, iclass 4, count 2 2006.286.04:16:10.38#ibcon#read 3, iclass 4, count 2 2006.286.04:16:10.38#ibcon#about to read 4, iclass 4, count 2 2006.286.04:16:10.38#ibcon#read 4, iclass 4, count 2 2006.286.04:16:10.38#ibcon#about to read 5, iclass 4, count 2 2006.286.04:16:10.38#ibcon#read 5, iclass 4, count 2 2006.286.04:16:10.38#ibcon#about to read 6, iclass 4, count 2 2006.286.04:16:10.38#ibcon#read 6, iclass 4, count 2 2006.286.04:16:10.38#ibcon#end of sib2, iclass 4, count 2 2006.286.04:16:10.38#ibcon#*mode == 0, iclass 4, count 2 2006.286.04:16:10.38#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.04:16:10.38#ibcon#[27=AT03-04\r\n] 2006.286.04:16:10.38#ibcon#*before write, iclass 4, count 2 2006.286.04:16:10.38#ibcon#enter sib2, iclass 4, count 2 2006.286.04:16:10.38#ibcon#flushed, iclass 4, count 2 2006.286.04:16:10.38#ibcon#about to write, iclass 4, count 2 2006.286.04:16:10.38#ibcon#wrote, iclass 4, count 2 2006.286.04:16:10.38#ibcon#about to read 3, iclass 4, count 2 2006.286.04:16:10.41#ibcon#read 3, iclass 4, count 2 2006.286.04:16:10.41#ibcon#about to read 4, iclass 4, count 2 2006.286.04:16:10.41#ibcon#read 4, iclass 4, count 2 2006.286.04:16:10.41#ibcon#about to read 5, iclass 4, count 2 2006.286.04:16:10.41#ibcon#read 5, iclass 4, count 2 2006.286.04:16:10.41#ibcon#about to read 6, iclass 4, count 2 2006.286.04:16:10.41#ibcon#read 6, iclass 4, count 2 2006.286.04:16:10.41#ibcon#end of sib2, iclass 4, count 2 2006.286.04:16:10.41#ibcon#*after write, iclass 4, count 2 2006.286.04:16:10.41#ibcon#*before return 0, iclass 4, count 2 2006.286.04:16:10.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:16:10.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:16:10.41#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.04:16:10.41#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:10.41#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:16:10.53#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:16:10.60#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:16:10.60#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:16:10.60#ibcon#first serial, iclass 4, count 0 2006.286.04:16:10.60#ibcon#enter sib2, iclass 4, count 0 2006.286.04:16:10.60#ibcon#flushed, iclass 4, count 0 2006.286.04:16:10.60#ibcon#about to write, iclass 4, count 0 2006.286.04:16:10.60#ibcon#wrote, iclass 4, count 0 2006.286.04:16:10.60#ibcon#about to read 3, iclass 4, count 0 2006.286.04:16:10.62#ibcon#read 3, iclass 4, count 0 2006.286.04:16:10.62#ibcon#about to read 4, iclass 4, count 0 2006.286.04:16:10.62#ibcon#read 4, iclass 4, count 0 2006.286.04:16:10.62#ibcon#about to read 5, iclass 4, count 0 2006.286.04:16:10.62#ibcon#read 5, iclass 4, count 0 2006.286.04:16:10.62#ibcon#about to read 6, iclass 4, count 0 2006.286.04:16:10.62#ibcon#read 6, iclass 4, count 0 2006.286.04:16:10.62#ibcon#end of sib2, iclass 4, count 0 2006.286.04:16:10.62#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:16:10.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:16:10.62#ibcon#[27=USB\r\n] 2006.286.04:16:10.62#ibcon#*before write, iclass 4, count 0 2006.286.04:16:10.62#ibcon#enter sib2, iclass 4, count 0 2006.286.04:16:10.62#ibcon#flushed, iclass 4, count 0 2006.286.04:16:10.62#ibcon#about to write, iclass 4, count 0 2006.286.04:16:10.62#ibcon#wrote, iclass 4, count 0 2006.286.04:16:10.62#ibcon#about to read 3, iclass 4, count 0 2006.286.04:16:10.65#ibcon#read 3, iclass 4, count 0 2006.286.04:16:10.65#ibcon#about to read 4, iclass 4, count 0 2006.286.04:16:10.65#ibcon#read 4, iclass 4, count 0 2006.286.04:16:10.65#ibcon#about to read 5, iclass 4, count 0 2006.286.04:16:10.65#ibcon#read 5, iclass 4, count 0 2006.286.04:16:10.65#ibcon#about to read 6, iclass 4, count 0 2006.286.04:16:10.65#ibcon#read 6, iclass 4, count 0 2006.286.04:16:10.65#ibcon#end of sib2, iclass 4, count 0 2006.286.04:16:10.65#ibcon#*after write, iclass 4, count 0 2006.286.04:16:10.65#ibcon#*before return 0, iclass 4, count 0 2006.286.04:16:10.65#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:16:10.65#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:16:10.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:16:10.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:16:10.65$vck44/vblo=4,679.99 2006.286.04:16:10.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.04:16:10.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.04:16:10.65#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:10.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:16:10.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:16:10.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:16:10.65#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:16:10.65#ibcon#first serial, iclass 6, count 0 2006.286.04:16:10.65#ibcon#enter sib2, iclass 6, count 0 2006.286.04:16:10.65#ibcon#flushed, iclass 6, count 0 2006.286.04:16:10.65#ibcon#about to write, iclass 6, count 0 2006.286.04:16:10.65#ibcon#wrote, iclass 6, count 0 2006.286.04:16:10.65#ibcon#about to read 3, iclass 6, count 0 2006.286.04:16:10.67#ibcon#read 3, iclass 6, count 0 2006.286.04:16:10.67#ibcon#about to read 4, iclass 6, count 0 2006.286.04:16:10.67#ibcon#read 4, iclass 6, count 0 2006.286.04:16:10.67#ibcon#about to read 5, iclass 6, count 0 2006.286.04:16:10.67#ibcon#read 5, iclass 6, count 0 2006.286.04:16:10.67#ibcon#about to read 6, iclass 6, count 0 2006.286.04:16:10.67#ibcon#read 6, iclass 6, count 0 2006.286.04:16:10.67#ibcon#end of sib2, iclass 6, count 0 2006.286.04:16:10.67#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:16:10.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:16:10.67#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:16:10.67#ibcon#*before write, iclass 6, count 0 2006.286.04:16:10.67#ibcon#enter sib2, iclass 6, count 0 2006.286.04:16:10.67#ibcon#flushed, iclass 6, count 0 2006.286.04:16:10.67#ibcon#about to write, iclass 6, count 0 2006.286.04:16:10.67#ibcon#wrote, iclass 6, count 0 2006.286.04:16:10.67#ibcon#about to read 3, iclass 6, count 0 2006.286.04:16:10.71#ibcon#read 3, iclass 6, count 0 2006.286.04:16:10.71#ibcon#about to read 4, iclass 6, count 0 2006.286.04:16:10.71#ibcon#read 4, iclass 6, count 0 2006.286.04:16:10.71#ibcon#about to read 5, iclass 6, count 0 2006.286.04:16:10.71#ibcon#read 5, iclass 6, count 0 2006.286.04:16:10.71#ibcon#about to read 6, iclass 6, count 0 2006.286.04:16:10.71#ibcon#read 6, iclass 6, count 0 2006.286.04:16:10.71#ibcon#end of sib2, iclass 6, count 0 2006.286.04:16:10.71#ibcon#*after write, iclass 6, count 0 2006.286.04:16:10.71#ibcon#*before return 0, iclass 6, count 0 2006.286.04:16:10.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:16:10.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:16:10.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:16:10.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:16:10.71$vck44/vb=4,5 2006.286.04:16:10.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.04:16:10.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.04:16:10.71#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:10.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:16:10.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:16:10.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:16:10.77#ibcon#enter wrdev, iclass 10, count 2 2006.286.04:16:10.77#ibcon#first serial, iclass 10, count 2 2006.286.04:16:10.77#ibcon#enter sib2, iclass 10, count 2 2006.286.04:16:10.77#ibcon#flushed, iclass 10, count 2 2006.286.04:16:10.77#ibcon#about to write, iclass 10, count 2 2006.286.04:16:10.77#ibcon#wrote, iclass 10, count 2 2006.286.04:16:10.77#ibcon#about to read 3, iclass 10, count 2 2006.286.04:16:10.79#ibcon#read 3, iclass 10, count 2 2006.286.04:16:10.79#ibcon#about to read 4, iclass 10, count 2 2006.286.04:16:10.79#ibcon#read 4, iclass 10, count 2 2006.286.04:16:10.79#ibcon#about to read 5, iclass 10, count 2 2006.286.04:16:10.79#ibcon#read 5, iclass 10, count 2 2006.286.04:16:10.79#ibcon#about to read 6, iclass 10, count 2 2006.286.04:16:10.79#ibcon#read 6, iclass 10, count 2 2006.286.04:16:10.79#ibcon#end of sib2, iclass 10, count 2 2006.286.04:16:10.79#ibcon#*mode == 0, iclass 10, count 2 2006.286.04:16:10.79#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.04:16:10.79#ibcon#[27=AT04-05\r\n] 2006.286.04:16:10.79#ibcon#*before write, iclass 10, count 2 2006.286.04:16:10.79#ibcon#enter sib2, iclass 10, count 2 2006.286.04:16:10.79#ibcon#flushed, iclass 10, count 2 2006.286.04:16:10.79#ibcon#about to write, iclass 10, count 2 2006.286.04:16:10.79#ibcon#wrote, iclass 10, count 2 2006.286.04:16:10.79#ibcon#about to read 3, iclass 10, count 2 2006.286.04:16:10.82#ibcon#read 3, iclass 10, count 2 2006.286.04:16:10.82#ibcon#about to read 4, iclass 10, count 2 2006.286.04:16:10.82#ibcon#read 4, iclass 10, count 2 2006.286.04:16:10.82#ibcon#about to read 5, iclass 10, count 2 2006.286.04:16:10.82#ibcon#read 5, iclass 10, count 2 2006.286.04:16:10.82#ibcon#about to read 6, iclass 10, count 2 2006.286.04:16:10.82#ibcon#read 6, iclass 10, count 2 2006.286.04:16:10.82#ibcon#end of sib2, iclass 10, count 2 2006.286.04:16:10.82#ibcon#*after write, iclass 10, count 2 2006.286.04:16:10.82#ibcon#*before return 0, iclass 10, count 2 2006.286.04:16:10.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:16:10.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:16:10.82#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.04:16:10.82#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:10.82#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:16:10.94#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:16:10.94#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:16:10.94#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:16:10.94#ibcon#first serial, iclass 10, count 0 2006.286.04:16:10.94#ibcon#enter sib2, iclass 10, count 0 2006.286.04:16:10.94#ibcon#flushed, iclass 10, count 0 2006.286.04:16:10.94#ibcon#about to write, iclass 10, count 0 2006.286.04:16:10.94#ibcon#wrote, iclass 10, count 0 2006.286.04:16:10.94#ibcon#about to read 3, iclass 10, count 0 2006.286.04:16:10.96#ibcon#read 3, iclass 10, count 0 2006.286.04:16:10.96#ibcon#about to read 4, iclass 10, count 0 2006.286.04:16:10.96#ibcon#read 4, iclass 10, count 0 2006.286.04:16:10.96#ibcon#about to read 5, iclass 10, count 0 2006.286.04:16:10.96#ibcon#read 5, iclass 10, count 0 2006.286.04:16:10.96#ibcon#about to read 6, iclass 10, count 0 2006.286.04:16:10.96#ibcon#read 6, iclass 10, count 0 2006.286.04:16:10.96#ibcon#end of sib2, iclass 10, count 0 2006.286.04:16:10.96#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:16:10.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:16:10.96#ibcon#[27=USB\r\n] 2006.286.04:16:10.96#ibcon#*before write, iclass 10, count 0 2006.286.04:16:10.96#ibcon#enter sib2, iclass 10, count 0 2006.286.04:16:10.96#ibcon#flushed, iclass 10, count 0 2006.286.04:16:10.96#ibcon#about to write, iclass 10, count 0 2006.286.04:16:10.96#ibcon#wrote, iclass 10, count 0 2006.286.04:16:10.96#ibcon#about to read 3, iclass 10, count 0 2006.286.04:16:10.99#ibcon#read 3, iclass 10, count 0 2006.286.04:16:10.99#ibcon#about to read 4, iclass 10, count 0 2006.286.04:16:10.99#ibcon#read 4, iclass 10, count 0 2006.286.04:16:10.99#ibcon#about to read 5, iclass 10, count 0 2006.286.04:16:10.99#ibcon#read 5, iclass 10, count 0 2006.286.04:16:10.99#ibcon#about to read 6, iclass 10, count 0 2006.286.04:16:10.99#ibcon#read 6, iclass 10, count 0 2006.286.04:16:10.99#ibcon#end of sib2, iclass 10, count 0 2006.286.04:16:10.99#ibcon#*after write, iclass 10, count 0 2006.286.04:16:10.99#ibcon#*before return 0, iclass 10, count 0 2006.286.04:16:10.99#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:16:10.99#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:16:10.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:16:10.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:16:10.99$vck44/vblo=5,709.99 2006.286.04:16:10.99#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.04:16:10.99#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.04:16:10.99#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:10.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:16:10.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:16:10.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:16:10.99#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:16:10.99#ibcon#first serial, iclass 12, count 0 2006.286.04:16:10.99#ibcon#enter sib2, iclass 12, count 0 2006.286.04:16:10.99#ibcon#flushed, iclass 12, count 0 2006.286.04:16:10.99#ibcon#about to write, iclass 12, count 0 2006.286.04:16:10.99#ibcon#wrote, iclass 12, count 0 2006.286.04:16:10.99#ibcon#about to read 3, iclass 12, count 0 2006.286.04:16:11.01#ibcon#read 3, iclass 12, count 0 2006.286.04:16:11.01#ibcon#about to read 4, iclass 12, count 0 2006.286.04:16:11.01#ibcon#read 4, iclass 12, count 0 2006.286.04:16:11.01#ibcon#about to read 5, iclass 12, count 0 2006.286.04:16:11.01#ibcon#read 5, iclass 12, count 0 2006.286.04:16:11.01#ibcon#about to read 6, iclass 12, count 0 2006.286.04:16:11.01#ibcon#read 6, iclass 12, count 0 2006.286.04:16:11.01#ibcon#end of sib2, iclass 12, count 0 2006.286.04:16:11.01#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:16:11.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:16:11.01#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:16:11.01#ibcon#*before write, iclass 12, count 0 2006.286.04:16:11.01#ibcon#enter sib2, iclass 12, count 0 2006.286.04:16:11.01#ibcon#flushed, iclass 12, count 0 2006.286.04:16:11.01#ibcon#about to write, iclass 12, count 0 2006.286.04:16:11.01#ibcon#wrote, iclass 12, count 0 2006.286.04:16:11.01#ibcon#about to read 3, iclass 12, count 0 2006.286.04:16:11.05#ibcon#read 3, iclass 12, count 0 2006.286.04:16:11.05#ibcon#about to read 4, iclass 12, count 0 2006.286.04:16:11.05#ibcon#read 4, iclass 12, count 0 2006.286.04:16:11.05#ibcon#about to read 5, iclass 12, count 0 2006.286.04:16:11.05#ibcon#read 5, iclass 12, count 0 2006.286.04:16:11.05#ibcon#about to read 6, iclass 12, count 0 2006.286.04:16:11.05#ibcon#read 6, iclass 12, count 0 2006.286.04:16:11.05#ibcon#end of sib2, iclass 12, count 0 2006.286.04:16:11.05#ibcon#*after write, iclass 12, count 0 2006.286.04:16:11.05#ibcon#*before return 0, iclass 12, count 0 2006.286.04:16:11.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:16:11.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:16:11.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:16:11.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:16:11.05$vck44/vb=5,4 2006.286.04:16:11.05#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.04:16:11.05#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.04:16:11.05#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:11.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:16:11.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:16:11.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:16:11.11#ibcon#enter wrdev, iclass 14, count 2 2006.286.04:16:11.11#ibcon#first serial, iclass 14, count 2 2006.286.04:16:11.11#ibcon#enter sib2, iclass 14, count 2 2006.286.04:16:11.11#ibcon#flushed, iclass 14, count 2 2006.286.04:16:11.11#ibcon#about to write, iclass 14, count 2 2006.286.04:16:11.11#ibcon#wrote, iclass 14, count 2 2006.286.04:16:11.11#ibcon#about to read 3, iclass 14, count 2 2006.286.04:16:11.13#ibcon#read 3, iclass 14, count 2 2006.286.04:16:11.13#ibcon#about to read 4, iclass 14, count 2 2006.286.04:16:11.13#ibcon#read 4, iclass 14, count 2 2006.286.04:16:11.13#ibcon#about to read 5, iclass 14, count 2 2006.286.04:16:11.13#ibcon#read 5, iclass 14, count 2 2006.286.04:16:11.13#ibcon#about to read 6, iclass 14, count 2 2006.286.04:16:11.13#ibcon#read 6, iclass 14, count 2 2006.286.04:16:11.13#ibcon#end of sib2, iclass 14, count 2 2006.286.04:16:11.13#ibcon#*mode == 0, iclass 14, count 2 2006.286.04:16:11.13#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.04:16:11.13#ibcon#[27=AT05-04\r\n] 2006.286.04:16:11.13#ibcon#*before write, iclass 14, count 2 2006.286.04:16:11.13#ibcon#enter sib2, iclass 14, count 2 2006.286.04:16:11.13#ibcon#flushed, iclass 14, count 2 2006.286.04:16:11.13#ibcon#about to write, iclass 14, count 2 2006.286.04:16:11.13#ibcon#wrote, iclass 14, count 2 2006.286.04:16:11.13#ibcon#about to read 3, iclass 14, count 2 2006.286.04:16:11.16#ibcon#read 3, iclass 14, count 2 2006.286.04:16:11.16#ibcon#about to read 4, iclass 14, count 2 2006.286.04:16:11.16#ibcon#read 4, iclass 14, count 2 2006.286.04:16:11.16#ibcon#about to read 5, iclass 14, count 2 2006.286.04:16:11.16#ibcon#read 5, iclass 14, count 2 2006.286.04:16:11.16#ibcon#about to read 6, iclass 14, count 2 2006.286.04:16:11.16#ibcon#read 6, iclass 14, count 2 2006.286.04:16:11.16#ibcon#end of sib2, iclass 14, count 2 2006.286.04:16:11.16#ibcon#*after write, iclass 14, count 2 2006.286.04:16:11.16#ibcon#*before return 0, iclass 14, count 2 2006.286.04:16:11.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:16:11.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:16:11.16#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.04:16:11.16#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:11.16#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:16:11.28#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:16:11.28#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:16:11.28#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:16:11.28#ibcon#first serial, iclass 14, count 0 2006.286.04:16:11.28#ibcon#enter sib2, iclass 14, count 0 2006.286.04:16:11.28#ibcon#flushed, iclass 14, count 0 2006.286.04:16:11.28#ibcon#about to write, iclass 14, count 0 2006.286.04:16:11.28#ibcon#wrote, iclass 14, count 0 2006.286.04:16:11.28#ibcon#about to read 3, iclass 14, count 0 2006.286.04:16:11.30#ibcon#read 3, iclass 14, count 0 2006.286.04:16:11.30#ibcon#about to read 4, iclass 14, count 0 2006.286.04:16:11.30#ibcon#read 4, iclass 14, count 0 2006.286.04:16:11.30#ibcon#about to read 5, iclass 14, count 0 2006.286.04:16:11.30#ibcon#read 5, iclass 14, count 0 2006.286.04:16:11.30#ibcon#about to read 6, iclass 14, count 0 2006.286.04:16:11.30#ibcon#read 6, iclass 14, count 0 2006.286.04:16:11.30#ibcon#end of sib2, iclass 14, count 0 2006.286.04:16:11.30#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:16:11.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:16:11.30#ibcon#[27=USB\r\n] 2006.286.04:16:11.30#ibcon#*before write, iclass 14, count 0 2006.286.04:16:11.30#ibcon#enter sib2, iclass 14, count 0 2006.286.04:16:11.30#ibcon#flushed, iclass 14, count 0 2006.286.04:16:11.30#ibcon#about to write, iclass 14, count 0 2006.286.04:16:11.30#ibcon#wrote, iclass 14, count 0 2006.286.04:16:11.30#ibcon#about to read 3, iclass 14, count 0 2006.286.04:16:11.33#ibcon#read 3, iclass 14, count 0 2006.286.04:16:11.33#ibcon#about to read 4, iclass 14, count 0 2006.286.04:16:11.33#ibcon#read 4, iclass 14, count 0 2006.286.04:16:11.33#ibcon#about to read 5, iclass 14, count 0 2006.286.04:16:11.33#ibcon#read 5, iclass 14, count 0 2006.286.04:16:11.33#ibcon#about to read 6, iclass 14, count 0 2006.286.04:16:11.33#ibcon#read 6, iclass 14, count 0 2006.286.04:16:11.33#ibcon#end of sib2, iclass 14, count 0 2006.286.04:16:11.33#ibcon#*after write, iclass 14, count 0 2006.286.04:16:11.33#ibcon#*before return 0, iclass 14, count 0 2006.286.04:16:11.33#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:16:11.33#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:16:11.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:16:11.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:16:11.33$vck44/vblo=6,719.99 2006.286.04:16:11.33#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.04:16:11.33#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.04:16:11.33#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:11.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:16:11.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:16:11.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:16:11.33#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:16:11.33#ibcon#first serial, iclass 16, count 0 2006.286.04:16:11.33#ibcon#enter sib2, iclass 16, count 0 2006.286.04:16:11.33#ibcon#flushed, iclass 16, count 0 2006.286.04:16:11.33#ibcon#about to write, iclass 16, count 0 2006.286.04:16:11.33#ibcon#wrote, iclass 16, count 0 2006.286.04:16:11.33#ibcon#about to read 3, iclass 16, count 0 2006.286.04:16:11.35#ibcon#read 3, iclass 16, count 0 2006.286.04:16:11.35#ibcon#about to read 4, iclass 16, count 0 2006.286.04:16:11.35#ibcon#read 4, iclass 16, count 0 2006.286.04:16:11.35#ibcon#about to read 5, iclass 16, count 0 2006.286.04:16:11.35#ibcon#read 5, iclass 16, count 0 2006.286.04:16:11.35#ibcon#about to read 6, iclass 16, count 0 2006.286.04:16:11.35#ibcon#read 6, iclass 16, count 0 2006.286.04:16:11.35#ibcon#end of sib2, iclass 16, count 0 2006.286.04:16:11.35#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:16:11.35#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:16:11.35#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:16:11.35#ibcon#*before write, iclass 16, count 0 2006.286.04:16:11.35#ibcon#enter sib2, iclass 16, count 0 2006.286.04:16:11.35#ibcon#flushed, iclass 16, count 0 2006.286.04:16:11.35#ibcon#about to write, iclass 16, count 0 2006.286.04:16:11.35#ibcon#wrote, iclass 16, count 0 2006.286.04:16:11.35#ibcon#about to read 3, iclass 16, count 0 2006.286.04:16:11.39#ibcon#read 3, iclass 16, count 0 2006.286.04:16:11.39#ibcon#about to read 4, iclass 16, count 0 2006.286.04:16:11.39#ibcon#read 4, iclass 16, count 0 2006.286.04:16:11.39#ibcon#about to read 5, iclass 16, count 0 2006.286.04:16:11.39#ibcon#read 5, iclass 16, count 0 2006.286.04:16:11.39#ibcon#about to read 6, iclass 16, count 0 2006.286.04:16:11.39#ibcon#read 6, iclass 16, count 0 2006.286.04:16:11.39#ibcon#end of sib2, iclass 16, count 0 2006.286.04:16:11.39#ibcon#*after write, iclass 16, count 0 2006.286.04:16:11.39#ibcon#*before return 0, iclass 16, count 0 2006.286.04:16:11.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:16:11.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:16:11.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:16:11.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:16:11.39$vck44/vb=6,3 2006.286.04:16:11.39#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.04:16:11.39#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.04:16:11.39#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:11.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:16:11.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:16:11.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:16:11.45#ibcon#enter wrdev, iclass 18, count 2 2006.286.04:16:11.45#ibcon#first serial, iclass 18, count 2 2006.286.04:16:11.45#ibcon#enter sib2, iclass 18, count 2 2006.286.04:16:11.45#ibcon#flushed, iclass 18, count 2 2006.286.04:16:11.45#ibcon#about to write, iclass 18, count 2 2006.286.04:16:11.45#ibcon#wrote, iclass 18, count 2 2006.286.04:16:11.45#ibcon#about to read 3, iclass 18, count 2 2006.286.04:16:11.47#ibcon#read 3, iclass 18, count 2 2006.286.04:16:11.47#ibcon#about to read 4, iclass 18, count 2 2006.286.04:16:11.47#ibcon#read 4, iclass 18, count 2 2006.286.04:16:11.47#ibcon#about to read 5, iclass 18, count 2 2006.286.04:16:11.47#ibcon#read 5, iclass 18, count 2 2006.286.04:16:11.47#ibcon#about to read 6, iclass 18, count 2 2006.286.04:16:11.47#ibcon#read 6, iclass 18, count 2 2006.286.04:16:11.47#ibcon#end of sib2, iclass 18, count 2 2006.286.04:16:11.47#ibcon#*mode == 0, iclass 18, count 2 2006.286.04:16:11.47#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.04:16:11.47#ibcon#[27=AT06-03\r\n] 2006.286.04:16:11.47#ibcon#*before write, iclass 18, count 2 2006.286.04:16:11.47#ibcon#enter sib2, iclass 18, count 2 2006.286.04:16:11.47#ibcon#flushed, iclass 18, count 2 2006.286.04:16:11.47#ibcon#about to write, iclass 18, count 2 2006.286.04:16:11.47#ibcon#wrote, iclass 18, count 2 2006.286.04:16:11.47#ibcon#about to read 3, iclass 18, count 2 2006.286.04:16:11.50#ibcon#read 3, iclass 18, count 2 2006.286.04:16:11.50#ibcon#about to read 4, iclass 18, count 2 2006.286.04:16:11.50#ibcon#read 4, iclass 18, count 2 2006.286.04:16:11.50#ibcon#about to read 5, iclass 18, count 2 2006.286.04:16:11.50#ibcon#read 5, iclass 18, count 2 2006.286.04:16:11.50#ibcon#about to read 6, iclass 18, count 2 2006.286.04:16:11.50#ibcon#read 6, iclass 18, count 2 2006.286.04:16:11.50#ibcon#end of sib2, iclass 18, count 2 2006.286.04:16:11.50#ibcon#*after write, iclass 18, count 2 2006.286.04:16:11.50#ibcon#*before return 0, iclass 18, count 2 2006.286.04:16:11.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:16:11.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:16:11.50#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.04:16:11.50#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:11.50#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:16:11.62#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:16:11.62#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:16:11.62#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:16:11.62#ibcon#first serial, iclass 18, count 0 2006.286.04:16:11.62#ibcon#enter sib2, iclass 18, count 0 2006.286.04:16:11.62#ibcon#flushed, iclass 18, count 0 2006.286.04:16:11.62#ibcon#about to write, iclass 18, count 0 2006.286.04:16:11.62#ibcon#wrote, iclass 18, count 0 2006.286.04:16:11.62#ibcon#about to read 3, iclass 18, count 0 2006.286.04:16:11.64#ibcon#read 3, iclass 18, count 0 2006.286.04:16:11.64#ibcon#about to read 4, iclass 18, count 0 2006.286.04:16:11.64#ibcon#read 4, iclass 18, count 0 2006.286.04:16:11.64#ibcon#about to read 5, iclass 18, count 0 2006.286.04:16:11.64#ibcon#read 5, iclass 18, count 0 2006.286.04:16:11.64#ibcon#about to read 6, iclass 18, count 0 2006.286.04:16:11.64#ibcon#read 6, iclass 18, count 0 2006.286.04:16:11.64#ibcon#end of sib2, iclass 18, count 0 2006.286.04:16:11.64#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:16:11.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:16:11.64#ibcon#[27=USB\r\n] 2006.286.04:16:11.64#ibcon#*before write, iclass 18, count 0 2006.286.04:16:11.64#ibcon#enter sib2, iclass 18, count 0 2006.286.04:16:11.64#ibcon#flushed, iclass 18, count 0 2006.286.04:16:11.64#ibcon#about to write, iclass 18, count 0 2006.286.04:16:11.64#ibcon#wrote, iclass 18, count 0 2006.286.04:16:11.64#ibcon#about to read 3, iclass 18, count 0 2006.286.04:16:11.67#ibcon#read 3, iclass 18, count 0 2006.286.04:16:11.67#ibcon#about to read 4, iclass 18, count 0 2006.286.04:16:11.67#ibcon#read 4, iclass 18, count 0 2006.286.04:16:11.67#ibcon#about to read 5, iclass 18, count 0 2006.286.04:16:11.67#ibcon#read 5, iclass 18, count 0 2006.286.04:16:11.67#ibcon#about to read 6, iclass 18, count 0 2006.286.04:16:11.67#ibcon#read 6, iclass 18, count 0 2006.286.04:16:11.67#ibcon#end of sib2, iclass 18, count 0 2006.286.04:16:11.67#ibcon#*after write, iclass 18, count 0 2006.286.04:16:11.67#ibcon#*before return 0, iclass 18, count 0 2006.286.04:16:11.67#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:16:11.67#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:16:11.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:16:11.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:16:11.67$vck44/vblo=7,734.99 2006.286.04:16:11.67#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.04:16:11.67#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.04:16:11.67#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:11.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:16:11.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:16:11.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:16:11.67#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:16:11.67#ibcon#first serial, iclass 20, count 0 2006.286.04:16:11.67#ibcon#enter sib2, iclass 20, count 0 2006.286.04:16:11.67#ibcon#flushed, iclass 20, count 0 2006.286.04:16:11.67#ibcon#about to write, iclass 20, count 0 2006.286.04:16:11.67#ibcon#wrote, iclass 20, count 0 2006.286.04:16:11.67#ibcon#about to read 3, iclass 20, count 0 2006.286.04:16:11.69#ibcon#read 3, iclass 20, count 0 2006.286.04:16:11.69#ibcon#about to read 4, iclass 20, count 0 2006.286.04:16:11.69#ibcon#read 4, iclass 20, count 0 2006.286.04:16:11.69#ibcon#about to read 5, iclass 20, count 0 2006.286.04:16:11.69#ibcon#read 5, iclass 20, count 0 2006.286.04:16:11.69#ibcon#about to read 6, iclass 20, count 0 2006.286.04:16:11.69#ibcon#read 6, iclass 20, count 0 2006.286.04:16:11.69#ibcon#end of sib2, iclass 20, count 0 2006.286.04:16:11.69#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:16:11.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:16:11.69#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:16:11.69#ibcon#*before write, iclass 20, count 0 2006.286.04:16:11.69#ibcon#enter sib2, iclass 20, count 0 2006.286.04:16:11.69#ibcon#flushed, iclass 20, count 0 2006.286.04:16:11.69#ibcon#about to write, iclass 20, count 0 2006.286.04:16:11.69#ibcon#wrote, iclass 20, count 0 2006.286.04:16:11.69#ibcon#about to read 3, iclass 20, count 0 2006.286.04:16:11.73#ibcon#read 3, iclass 20, count 0 2006.286.04:16:11.73#ibcon#about to read 4, iclass 20, count 0 2006.286.04:16:11.73#ibcon#read 4, iclass 20, count 0 2006.286.04:16:11.73#ibcon#about to read 5, iclass 20, count 0 2006.286.04:16:11.73#ibcon#read 5, iclass 20, count 0 2006.286.04:16:11.73#ibcon#about to read 6, iclass 20, count 0 2006.286.04:16:11.73#ibcon#read 6, iclass 20, count 0 2006.286.04:16:11.73#ibcon#end of sib2, iclass 20, count 0 2006.286.04:16:11.73#ibcon#*after write, iclass 20, count 0 2006.286.04:16:11.73#ibcon#*before return 0, iclass 20, count 0 2006.286.04:16:11.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:16:11.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:16:11.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:16:11.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:16:11.73$vck44/vb=7,4 2006.286.04:16:11.73#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.04:16:11.73#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.04:16:11.73#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:11.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:16:11.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:16:11.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:16:11.79#ibcon#enter wrdev, iclass 22, count 2 2006.286.04:16:11.79#ibcon#first serial, iclass 22, count 2 2006.286.04:16:11.79#ibcon#enter sib2, iclass 22, count 2 2006.286.04:16:11.79#ibcon#flushed, iclass 22, count 2 2006.286.04:16:11.79#ibcon#about to write, iclass 22, count 2 2006.286.04:16:11.79#ibcon#wrote, iclass 22, count 2 2006.286.04:16:11.79#ibcon#about to read 3, iclass 22, count 2 2006.286.04:16:11.81#ibcon#read 3, iclass 22, count 2 2006.286.04:16:11.81#ibcon#about to read 4, iclass 22, count 2 2006.286.04:16:11.81#ibcon#read 4, iclass 22, count 2 2006.286.04:16:11.81#ibcon#about to read 5, iclass 22, count 2 2006.286.04:16:11.81#ibcon#read 5, iclass 22, count 2 2006.286.04:16:11.81#ibcon#about to read 6, iclass 22, count 2 2006.286.04:16:11.81#ibcon#read 6, iclass 22, count 2 2006.286.04:16:11.81#ibcon#end of sib2, iclass 22, count 2 2006.286.04:16:11.81#ibcon#*mode == 0, iclass 22, count 2 2006.286.04:16:11.81#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.04:16:11.81#ibcon#[27=AT07-04\r\n] 2006.286.04:16:11.81#ibcon#*before write, iclass 22, count 2 2006.286.04:16:11.81#ibcon#enter sib2, iclass 22, count 2 2006.286.04:16:11.81#ibcon#flushed, iclass 22, count 2 2006.286.04:16:11.81#ibcon#about to write, iclass 22, count 2 2006.286.04:16:11.81#ibcon#wrote, iclass 22, count 2 2006.286.04:16:11.81#ibcon#about to read 3, iclass 22, count 2 2006.286.04:16:11.84#ibcon#read 3, iclass 22, count 2 2006.286.04:16:11.84#ibcon#about to read 4, iclass 22, count 2 2006.286.04:16:11.84#ibcon#read 4, iclass 22, count 2 2006.286.04:16:11.84#ibcon#about to read 5, iclass 22, count 2 2006.286.04:16:11.84#ibcon#read 5, iclass 22, count 2 2006.286.04:16:11.84#ibcon#about to read 6, iclass 22, count 2 2006.286.04:16:11.84#ibcon#read 6, iclass 22, count 2 2006.286.04:16:11.84#ibcon#end of sib2, iclass 22, count 2 2006.286.04:16:11.84#ibcon#*after write, iclass 22, count 2 2006.286.04:16:11.84#ibcon#*before return 0, iclass 22, count 2 2006.286.04:16:11.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:16:11.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:16:11.84#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.04:16:11.84#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:11.84#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:16:11.96#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:16:11.96#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:16:11.96#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:16:11.96#ibcon#first serial, iclass 22, count 0 2006.286.04:16:11.96#ibcon#enter sib2, iclass 22, count 0 2006.286.04:16:11.96#ibcon#flushed, iclass 22, count 0 2006.286.04:16:11.96#ibcon#about to write, iclass 22, count 0 2006.286.04:16:11.96#ibcon#wrote, iclass 22, count 0 2006.286.04:16:11.96#ibcon#about to read 3, iclass 22, count 0 2006.286.04:16:11.98#ibcon#read 3, iclass 22, count 0 2006.286.04:16:11.98#ibcon#about to read 4, iclass 22, count 0 2006.286.04:16:11.98#ibcon#read 4, iclass 22, count 0 2006.286.04:16:11.98#ibcon#about to read 5, iclass 22, count 0 2006.286.04:16:11.98#ibcon#read 5, iclass 22, count 0 2006.286.04:16:11.98#ibcon#about to read 6, iclass 22, count 0 2006.286.04:16:11.98#ibcon#read 6, iclass 22, count 0 2006.286.04:16:11.98#ibcon#end of sib2, iclass 22, count 0 2006.286.04:16:11.98#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:16:11.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:16:11.98#ibcon#[27=USB\r\n] 2006.286.04:16:11.98#ibcon#*before write, iclass 22, count 0 2006.286.04:16:11.98#ibcon#enter sib2, iclass 22, count 0 2006.286.04:16:11.98#ibcon#flushed, iclass 22, count 0 2006.286.04:16:11.98#ibcon#about to write, iclass 22, count 0 2006.286.04:16:11.98#ibcon#wrote, iclass 22, count 0 2006.286.04:16:11.98#ibcon#about to read 3, iclass 22, count 0 2006.286.04:16:12.01#ibcon#read 3, iclass 22, count 0 2006.286.04:16:12.01#ibcon#about to read 4, iclass 22, count 0 2006.286.04:16:12.01#ibcon#read 4, iclass 22, count 0 2006.286.04:16:12.01#ibcon#about to read 5, iclass 22, count 0 2006.286.04:16:12.01#ibcon#read 5, iclass 22, count 0 2006.286.04:16:12.01#ibcon#about to read 6, iclass 22, count 0 2006.286.04:16:12.01#ibcon#read 6, iclass 22, count 0 2006.286.04:16:12.01#ibcon#end of sib2, iclass 22, count 0 2006.286.04:16:12.01#ibcon#*after write, iclass 22, count 0 2006.286.04:16:12.01#ibcon#*before return 0, iclass 22, count 0 2006.286.04:16:12.01#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:16:12.01#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:16:12.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:16:12.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:16:12.01$vck44/vblo=8,744.99 2006.286.04:16:12.01#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.04:16:12.01#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.04:16:12.01#ibcon#ireg 17 cls_cnt 0 2006.286.04:16:12.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:16:12.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:16:12.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:16:12.01#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:16:12.01#ibcon#first serial, iclass 24, count 0 2006.286.04:16:12.01#ibcon#enter sib2, iclass 24, count 0 2006.286.04:16:12.01#ibcon#flushed, iclass 24, count 0 2006.286.04:16:12.01#ibcon#about to write, iclass 24, count 0 2006.286.04:16:12.01#ibcon#wrote, iclass 24, count 0 2006.286.04:16:12.01#ibcon#about to read 3, iclass 24, count 0 2006.286.04:16:12.03#ibcon#read 3, iclass 24, count 0 2006.286.04:16:12.03#ibcon#about to read 4, iclass 24, count 0 2006.286.04:16:12.03#ibcon#read 4, iclass 24, count 0 2006.286.04:16:12.03#ibcon#about to read 5, iclass 24, count 0 2006.286.04:16:12.03#ibcon#read 5, iclass 24, count 0 2006.286.04:16:12.03#ibcon#about to read 6, iclass 24, count 0 2006.286.04:16:12.03#ibcon#read 6, iclass 24, count 0 2006.286.04:16:12.03#ibcon#end of sib2, iclass 24, count 0 2006.286.04:16:12.03#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:16:12.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:16:12.03#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:16:12.03#ibcon#*before write, iclass 24, count 0 2006.286.04:16:12.03#ibcon#enter sib2, iclass 24, count 0 2006.286.04:16:12.03#ibcon#flushed, iclass 24, count 0 2006.286.04:16:12.03#ibcon#about to write, iclass 24, count 0 2006.286.04:16:12.03#ibcon#wrote, iclass 24, count 0 2006.286.04:16:12.03#ibcon#about to read 3, iclass 24, count 0 2006.286.04:16:12.07#ibcon#read 3, iclass 24, count 0 2006.286.04:16:12.07#ibcon#about to read 4, iclass 24, count 0 2006.286.04:16:12.07#ibcon#read 4, iclass 24, count 0 2006.286.04:16:12.07#ibcon#about to read 5, iclass 24, count 0 2006.286.04:16:12.07#ibcon#read 5, iclass 24, count 0 2006.286.04:16:12.07#ibcon#about to read 6, iclass 24, count 0 2006.286.04:16:12.07#ibcon#read 6, iclass 24, count 0 2006.286.04:16:12.07#ibcon#end of sib2, iclass 24, count 0 2006.286.04:16:12.07#ibcon#*after write, iclass 24, count 0 2006.286.04:16:12.07#ibcon#*before return 0, iclass 24, count 0 2006.286.04:16:12.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:16:12.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:16:12.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:16:12.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:16:12.07$vck44/vb=8,4 2006.286.04:16:12.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.04:16:12.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.04:16:12.07#ibcon#ireg 11 cls_cnt 2 2006.286.04:16:12.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:16:12.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:16:12.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:16:12.13#ibcon#enter wrdev, iclass 26, count 2 2006.286.04:16:12.13#ibcon#first serial, iclass 26, count 2 2006.286.04:16:12.13#ibcon#enter sib2, iclass 26, count 2 2006.286.04:16:12.13#ibcon#flushed, iclass 26, count 2 2006.286.04:16:12.13#ibcon#about to write, iclass 26, count 2 2006.286.04:16:12.13#ibcon#wrote, iclass 26, count 2 2006.286.04:16:12.13#ibcon#about to read 3, iclass 26, count 2 2006.286.04:16:12.15#ibcon#read 3, iclass 26, count 2 2006.286.04:16:12.15#ibcon#about to read 4, iclass 26, count 2 2006.286.04:16:12.15#ibcon#read 4, iclass 26, count 2 2006.286.04:16:12.15#ibcon#about to read 5, iclass 26, count 2 2006.286.04:16:12.15#ibcon#read 5, iclass 26, count 2 2006.286.04:16:12.15#ibcon#about to read 6, iclass 26, count 2 2006.286.04:16:12.15#ibcon#read 6, iclass 26, count 2 2006.286.04:16:12.15#ibcon#end of sib2, iclass 26, count 2 2006.286.04:16:12.15#ibcon#*mode == 0, iclass 26, count 2 2006.286.04:16:12.15#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.04:16:12.15#ibcon#[27=AT08-04\r\n] 2006.286.04:16:12.15#ibcon#*before write, iclass 26, count 2 2006.286.04:16:12.15#ibcon#enter sib2, iclass 26, count 2 2006.286.04:16:12.15#ibcon#flushed, iclass 26, count 2 2006.286.04:16:12.15#ibcon#about to write, iclass 26, count 2 2006.286.04:16:12.15#ibcon#wrote, iclass 26, count 2 2006.286.04:16:12.15#ibcon#about to read 3, iclass 26, count 2 2006.286.04:16:12.18#ibcon#read 3, iclass 26, count 2 2006.286.04:16:12.18#ibcon#about to read 4, iclass 26, count 2 2006.286.04:16:12.18#ibcon#read 4, iclass 26, count 2 2006.286.04:16:12.18#ibcon#about to read 5, iclass 26, count 2 2006.286.04:16:12.18#ibcon#read 5, iclass 26, count 2 2006.286.04:16:12.18#ibcon#about to read 6, iclass 26, count 2 2006.286.04:16:12.18#ibcon#read 6, iclass 26, count 2 2006.286.04:16:12.18#ibcon#end of sib2, iclass 26, count 2 2006.286.04:16:12.18#ibcon#*after write, iclass 26, count 2 2006.286.04:16:12.18#ibcon#*before return 0, iclass 26, count 2 2006.286.04:16:12.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:16:12.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:16:12.18#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.04:16:12.18#ibcon#ireg 7 cls_cnt 0 2006.286.04:16:12.18#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:16:12.30#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:16:12.30#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:16:12.30#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:16:12.30#ibcon#first serial, iclass 26, count 0 2006.286.04:16:12.30#ibcon#enter sib2, iclass 26, count 0 2006.286.04:16:12.30#ibcon#flushed, iclass 26, count 0 2006.286.04:16:12.30#ibcon#about to write, iclass 26, count 0 2006.286.04:16:12.30#ibcon#wrote, iclass 26, count 0 2006.286.04:16:12.30#ibcon#about to read 3, iclass 26, count 0 2006.286.04:16:12.32#ibcon#read 3, iclass 26, count 0 2006.286.04:16:12.32#ibcon#about to read 4, iclass 26, count 0 2006.286.04:16:12.32#ibcon#read 4, iclass 26, count 0 2006.286.04:16:12.32#ibcon#about to read 5, iclass 26, count 0 2006.286.04:16:12.32#ibcon#read 5, iclass 26, count 0 2006.286.04:16:12.32#ibcon#about to read 6, iclass 26, count 0 2006.286.04:16:12.32#ibcon#read 6, iclass 26, count 0 2006.286.04:16:12.32#ibcon#end of sib2, iclass 26, count 0 2006.286.04:16:12.32#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:16:12.32#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:16:12.32#ibcon#[27=USB\r\n] 2006.286.04:16:12.32#ibcon#*before write, iclass 26, count 0 2006.286.04:16:12.32#ibcon#enter sib2, iclass 26, count 0 2006.286.04:16:12.32#ibcon#flushed, iclass 26, count 0 2006.286.04:16:12.32#ibcon#about to write, iclass 26, count 0 2006.286.04:16:12.32#ibcon#wrote, iclass 26, count 0 2006.286.04:16:12.32#ibcon#about to read 3, iclass 26, count 0 2006.286.04:16:12.35#ibcon#read 3, iclass 26, count 0 2006.286.04:16:12.35#ibcon#about to read 4, iclass 26, count 0 2006.286.04:16:12.35#ibcon#read 4, iclass 26, count 0 2006.286.04:16:12.35#ibcon#about to read 5, iclass 26, count 0 2006.286.04:16:12.35#ibcon#read 5, iclass 26, count 0 2006.286.04:16:12.35#ibcon#about to read 6, iclass 26, count 0 2006.286.04:16:12.35#ibcon#read 6, iclass 26, count 0 2006.286.04:16:12.35#ibcon#end of sib2, iclass 26, count 0 2006.286.04:16:12.35#ibcon#*after write, iclass 26, count 0 2006.286.04:16:12.35#ibcon#*before return 0, iclass 26, count 0 2006.286.04:16:12.35#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:16:12.35#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:16:12.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:16:12.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:16:12.35$vck44/vabw=wide 2006.286.04:16:12.35#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.04:16:12.35#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.04:16:12.35#ibcon#ireg 8 cls_cnt 0 2006.286.04:16:12.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:16:12.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:16:12.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:16:12.35#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:16:12.35#ibcon#first serial, iclass 28, count 0 2006.286.04:16:12.35#ibcon#enter sib2, iclass 28, count 0 2006.286.04:16:12.35#ibcon#flushed, iclass 28, count 0 2006.286.04:16:12.35#ibcon#about to write, iclass 28, count 0 2006.286.04:16:12.35#ibcon#wrote, iclass 28, count 0 2006.286.04:16:12.35#ibcon#about to read 3, iclass 28, count 0 2006.286.04:16:12.37#ibcon#read 3, iclass 28, count 0 2006.286.04:16:12.37#ibcon#about to read 4, iclass 28, count 0 2006.286.04:16:12.37#ibcon#read 4, iclass 28, count 0 2006.286.04:16:12.37#ibcon#about to read 5, iclass 28, count 0 2006.286.04:16:12.37#ibcon#read 5, iclass 28, count 0 2006.286.04:16:12.37#ibcon#about to read 6, iclass 28, count 0 2006.286.04:16:12.37#ibcon#read 6, iclass 28, count 0 2006.286.04:16:12.37#ibcon#end of sib2, iclass 28, count 0 2006.286.04:16:12.37#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:16:12.37#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:16:12.37#ibcon#[25=BW32\r\n] 2006.286.04:16:12.37#ibcon#*before write, iclass 28, count 0 2006.286.04:16:12.37#ibcon#enter sib2, iclass 28, count 0 2006.286.04:16:12.37#ibcon#flushed, iclass 28, count 0 2006.286.04:16:12.37#ibcon#about to write, iclass 28, count 0 2006.286.04:16:12.37#ibcon#wrote, iclass 28, count 0 2006.286.04:16:12.37#ibcon#about to read 3, iclass 28, count 0 2006.286.04:16:12.40#ibcon#read 3, iclass 28, count 0 2006.286.04:16:12.40#ibcon#about to read 4, iclass 28, count 0 2006.286.04:16:12.40#ibcon#read 4, iclass 28, count 0 2006.286.04:16:12.40#ibcon#about to read 5, iclass 28, count 0 2006.286.04:16:12.40#ibcon#read 5, iclass 28, count 0 2006.286.04:16:12.40#ibcon#about to read 6, iclass 28, count 0 2006.286.04:16:12.40#ibcon#read 6, iclass 28, count 0 2006.286.04:16:12.40#ibcon#end of sib2, iclass 28, count 0 2006.286.04:16:12.40#ibcon#*after write, iclass 28, count 0 2006.286.04:16:12.40#ibcon#*before return 0, iclass 28, count 0 2006.286.04:16:12.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:16:12.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:16:12.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:16:12.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:16:12.40$vck44/vbbw=wide 2006.286.04:16:12.40#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:16:12.40#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:16:12.40#ibcon#ireg 8 cls_cnt 0 2006.286.04:16:12.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:16:12.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:16:12.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:16:12.47#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:16:12.47#ibcon#first serial, iclass 30, count 0 2006.286.04:16:12.47#ibcon#enter sib2, iclass 30, count 0 2006.286.04:16:12.47#ibcon#flushed, iclass 30, count 0 2006.286.04:16:12.47#ibcon#about to write, iclass 30, count 0 2006.286.04:16:12.47#ibcon#wrote, iclass 30, count 0 2006.286.04:16:12.47#ibcon#about to read 3, iclass 30, count 0 2006.286.04:16:12.49#ibcon#read 3, iclass 30, count 0 2006.286.04:16:12.49#ibcon#about to read 4, iclass 30, count 0 2006.286.04:16:12.49#ibcon#read 4, iclass 30, count 0 2006.286.04:16:12.49#ibcon#about to read 5, iclass 30, count 0 2006.286.04:16:12.49#ibcon#read 5, iclass 30, count 0 2006.286.04:16:12.49#ibcon#about to read 6, iclass 30, count 0 2006.286.04:16:12.49#ibcon#read 6, iclass 30, count 0 2006.286.04:16:12.49#ibcon#end of sib2, iclass 30, count 0 2006.286.04:16:12.49#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:16:12.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:16:12.49#ibcon#[27=BW32\r\n] 2006.286.04:16:12.49#ibcon#*before write, iclass 30, count 0 2006.286.04:16:12.49#ibcon#enter sib2, iclass 30, count 0 2006.286.04:16:12.49#ibcon#flushed, iclass 30, count 0 2006.286.04:16:12.49#ibcon#about to write, iclass 30, count 0 2006.286.04:16:12.49#ibcon#wrote, iclass 30, count 0 2006.286.04:16:12.49#ibcon#about to read 3, iclass 30, count 0 2006.286.04:16:12.52#ibcon#read 3, iclass 30, count 0 2006.286.04:16:12.52#ibcon#about to read 4, iclass 30, count 0 2006.286.04:16:12.57#ibcon#read 4, iclass 30, count 0 2006.286.04:16:12.57#ibcon#about to read 5, iclass 30, count 0 2006.286.04:16:12.57#ibcon#read 5, iclass 30, count 0 2006.286.04:16:12.57#ibcon#about to read 6, iclass 30, count 0 2006.286.04:16:12.57#ibcon#read 6, iclass 30, count 0 2006.286.04:16:12.57#ibcon#end of sib2, iclass 30, count 0 2006.286.04:16:12.57#ibcon#*after write, iclass 30, count 0 2006.286.04:16:12.57#ibcon#*before return 0, iclass 30, count 0 2006.286.04:16:12.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:16:12.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:16:12.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:16:12.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:16:12.57$setupk4/ifdk4 2006.286.04:16:12.57$ifdk4/lo= 2006.286.04:16:12.57$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:16:12.57$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:16:12.57$ifdk4/patch= 2006.286.04:16:12.57$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:16:12.57$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:16:12.57$setupk4/!*+20s 2006.286.04:16:14.73#abcon#<5=/04 3.1 7.7 21.91 751014.8\r\n> 2006.286.04:16:14.75#abcon#{5=INTERFACE CLEAR} 2006.286.04:16:14.81#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:16:24.90#abcon#<5=/04 3.1 6.9 21.92 741014.8\r\n> 2006.286.04:16:24.92#abcon#{5=INTERFACE CLEAR} 2006.286.04:16:24.98#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:16:26.15$setupk4/"tpicd 2006.286.04:16:26.15$setupk4/echo=off 2006.286.04:16:26.15$setupk4/xlog=off 2006.286.04:16:26.15:!2006.286.04:18:39 2006.286.04:16:50.14#trakl#Source acquired 2006.286.04:16:52.14#flagr#flagr/antenna,acquired 2006.286.04:18:39.00:preob 2006.286.04:18:39.14/onsource/TRACKING 2006.286.04:18:39.14:!2006.286.04:18:49 2006.286.04:18:49.00:"tape 2006.286.04:18:49.00:"st=record 2006.286.04:18:49.00:data_valid=on 2006.286.04:18:49.00:midob 2006.286.04:18:49.14/onsource/TRACKING 2006.286.04:18:49.14/wx/21.98,1014.8,74 2006.286.04:18:49.31/cable/+6.4970E-03 2006.286.04:18:50.40/va/01,07,usb,yes,38,41 2006.286.04:18:50.40/va/02,06,usb,yes,38,39 2006.286.04:18:50.40/va/03,07,usb,yes,38,40 2006.286.04:18:50.40/va/04,06,usb,yes,39,41 2006.286.04:18:50.40/va/05,03,usb,yes,39,39 2006.286.04:18:50.40/va/06,04,usb,yes,35,34 2006.286.04:18:50.40/va/07,04,usb,yes,36,36 2006.286.04:18:50.40/va/08,03,usb,yes,36,44 2006.286.04:18:50.63/valo/01,524.99,yes,locked 2006.286.04:18:50.63/valo/02,534.99,yes,locked 2006.286.04:18:50.63/valo/03,564.99,yes,locked 2006.286.04:18:50.63/valo/04,624.99,yes,locked 2006.286.04:18:50.63/valo/05,734.99,yes,locked 2006.286.04:18:50.63/valo/06,814.99,yes,locked 2006.286.04:18:50.63/valo/07,864.99,yes,locked 2006.286.04:18:50.63/valo/08,884.99,yes,locked 2006.286.04:18:51.72/vb/01,04,usb,yes,32,30 2006.286.04:18:51.72/vb/02,05,usb,yes,30,30 2006.286.04:18:51.72/vb/03,04,usb,yes,31,34 2006.286.04:18:51.72/vb/04,05,usb,yes,32,31 2006.286.04:18:51.72/vb/05,04,usb,yes,28,31 2006.286.04:18:51.72/vb/06,03,usb,yes,40,35 2006.286.04:18:51.72/vb/07,04,usb,yes,32,32 2006.286.04:18:51.72/vb/08,04,usb,yes,30,33 2006.286.04:18:51.95/vblo/01,629.99,yes,locked 2006.286.04:18:51.95/vblo/02,634.99,yes,locked 2006.286.04:18:51.95/vblo/03,649.99,yes,locked 2006.286.04:18:51.95/vblo/04,679.99,yes,locked 2006.286.04:18:51.95/vblo/05,709.99,yes,locked 2006.286.04:18:51.95/vblo/06,719.99,yes,locked 2006.286.04:18:51.95/vblo/07,734.99,yes,locked 2006.286.04:18:51.95/vblo/08,744.99,yes,locked 2006.286.04:18:52.10/vabw/8 2006.286.04:18:52.25/vbbw/8 2006.286.04:18:52.34/xfe/off,on,12.0 2006.286.04:18:52.71/ifatt/23,28,28,28 2006.286.04:18:53.08/fmout-gps/S +2.69E-07 2006.286.04:18:53.10:!2006.286.04:19:29 2006.286.04:19:29.01:data_valid=off 2006.286.04:19:29.01:"et 2006.286.04:19:29.01:!+3s 2006.286.04:19:32.02:"tape 2006.286.04:19:32.02:postob 2006.286.04:19:32.14/cable/+6.4946E-03 2006.286.04:19:32.14/wx/22.00,1014.8,75 2006.286.04:19:32.20/fmout-gps/S +2.70E-07 2006.286.04:19:32.20:scan_name=286-0420,jd0610,90 2006.286.04:19:32.20:source=3c274,123049.42,122328.0,2000.0,ccw 2006.286.04:19:34.14#flagr#flagr/antenna,new-source 2006.286.04:19:34.14:checkk5 2006.286.04:19:34.56/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:19:35.18/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:19:35.58/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:19:36.18/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:19:36.68/chk_obsdata//k5ts1/T2860418??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:19:37.08/chk_obsdata//k5ts2/T2860418??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:19:37.49/chk_obsdata//k5ts3/T2860418??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:19:38.06/chk_obsdata//k5ts4/T2860418??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:19:39.21/k5log//k5ts1_log_newline 2006.286.04:19:40.26/k5log//k5ts2_log_newline 2006.286.04:19:41.30/k5log//k5ts3_log_newline 2006.286.04:19:42.26/k5log//k5ts4_log_newline 2006.286.04:19:42.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:19:42.28:setupk4=1 2006.286.04:19:42.28$setupk4/echo=on 2006.286.04:19:42.28$setupk4/pcalon 2006.286.04:19:42.28$pcalon/"no phase cal control is implemented here 2006.286.04:19:42.28$setupk4/"tpicd=stop 2006.286.04:19:42.28$setupk4/"rec=synch_on 2006.286.04:19:42.28$setupk4/"rec_mode=128 2006.286.04:19:42.28$setupk4/!* 2006.286.04:19:42.28$setupk4/recpk4 2006.286.04:19:42.28$recpk4/recpatch= 2006.286.04:19:42.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:19:42.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:19:42.28$setupk4/vck44 2006.286.04:19:42.28$vck44/valo=1,524.99 2006.286.04:19:42.28#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.04:19:42.28#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.04:19:42.28#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:42.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:19:42.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:19:42.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:19:42.28#ibcon#enter wrdev, iclass 11, count 0 2006.286.04:19:42.28#ibcon#first serial, iclass 11, count 0 2006.286.04:19:42.28#ibcon#enter sib2, iclass 11, count 0 2006.286.04:19:42.28#ibcon#flushed, iclass 11, count 0 2006.286.04:19:42.28#ibcon#about to write, iclass 11, count 0 2006.286.04:19:42.28#ibcon#wrote, iclass 11, count 0 2006.286.04:19:42.28#ibcon#about to read 3, iclass 11, count 0 2006.286.04:19:42.30#ibcon#read 3, iclass 11, count 0 2006.286.04:19:42.30#ibcon#about to read 4, iclass 11, count 0 2006.286.04:19:42.30#ibcon#read 4, iclass 11, count 0 2006.286.04:19:42.30#ibcon#about to read 5, iclass 11, count 0 2006.286.04:19:42.30#ibcon#read 5, iclass 11, count 0 2006.286.04:19:42.30#ibcon#about to read 6, iclass 11, count 0 2006.286.04:19:42.30#ibcon#read 6, iclass 11, count 0 2006.286.04:19:42.30#ibcon#end of sib2, iclass 11, count 0 2006.286.04:19:42.30#ibcon#*mode == 0, iclass 11, count 0 2006.286.04:19:42.30#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.04:19:42.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:19:42.30#ibcon#*before write, iclass 11, count 0 2006.286.04:19:42.30#ibcon#enter sib2, iclass 11, count 0 2006.286.04:19:42.30#ibcon#flushed, iclass 11, count 0 2006.286.04:19:42.30#ibcon#about to write, iclass 11, count 0 2006.286.04:19:42.30#ibcon#wrote, iclass 11, count 0 2006.286.04:19:42.30#ibcon#about to read 3, iclass 11, count 0 2006.286.04:19:42.35#ibcon#read 3, iclass 11, count 0 2006.286.04:19:42.35#ibcon#about to read 4, iclass 11, count 0 2006.286.04:19:42.35#ibcon#read 4, iclass 11, count 0 2006.286.04:19:42.35#ibcon#about to read 5, iclass 11, count 0 2006.286.04:19:42.35#ibcon#read 5, iclass 11, count 0 2006.286.04:19:42.35#ibcon#about to read 6, iclass 11, count 0 2006.286.04:19:42.35#ibcon#read 6, iclass 11, count 0 2006.286.04:19:42.35#ibcon#end of sib2, iclass 11, count 0 2006.286.04:19:42.35#ibcon#*after write, iclass 11, count 0 2006.286.04:19:42.35#ibcon#*before return 0, iclass 11, count 0 2006.286.04:19:42.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:19:42.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:19:42.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.04:19:42.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.04:19:42.35$vck44/va=1,7 2006.286.04:19:42.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.04:19:42.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.04:19:42.35#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:42.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:19:42.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:19:42.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:19:42.35#ibcon#enter wrdev, iclass 13, count 2 2006.286.04:19:42.35#ibcon#first serial, iclass 13, count 2 2006.286.04:19:42.35#ibcon#enter sib2, iclass 13, count 2 2006.286.04:19:42.35#ibcon#flushed, iclass 13, count 2 2006.286.04:19:42.35#ibcon#about to write, iclass 13, count 2 2006.286.04:19:42.35#ibcon#wrote, iclass 13, count 2 2006.286.04:19:42.35#ibcon#about to read 3, iclass 13, count 2 2006.286.04:19:42.37#ibcon#read 3, iclass 13, count 2 2006.286.04:19:42.37#ibcon#about to read 4, iclass 13, count 2 2006.286.04:19:42.37#ibcon#read 4, iclass 13, count 2 2006.286.04:19:42.37#ibcon#about to read 5, iclass 13, count 2 2006.286.04:19:42.37#ibcon#read 5, iclass 13, count 2 2006.286.04:19:42.37#ibcon#about to read 6, iclass 13, count 2 2006.286.04:19:42.37#ibcon#read 6, iclass 13, count 2 2006.286.04:19:42.37#ibcon#end of sib2, iclass 13, count 2 2006.286.04:19:42.37#ibcon#*mode == 0, iclass 13, count 2 2006.286.04:19:42.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.04:19:42.37#ibcon#[25=AT01-07\r\n] 2006.286.04:19:42.37#ibcon#*before write, iclass 13, count 2 2006.286.04:19:42.37#ibcon#enter sib2, iclass 13, count 2 2006.286.04:19:42.37#ibcon#flushed, iclass 13, count 2 2006.286.04:19:42.37#ibcon#about to write, iclass 13, count 2 2006.286.04:19:42.37#ibcon#wrote, iclass 13, count 2 2006.286.04:19:42.37#ibcon#about to read 3, iclass 13, count 2 2006.286.04:19:42.40#ibcon#read 3, iclass 13, count 2 2006.286.04:19:42.40#ibcon#about to read 4, iclass 13, count 2 2006.286.04:19:42.40#ibcon#read 4, iclass 13, count 2 2006.286.04:19:42.40#ibcon#about to read 5, iclass 13, count 2 2006.286.04:19:42.40#ibcon#read 5, iclass 13, count 2 2006.286.04:19:42.40#ibcon#about to read 6, iclass 13, count 2 2006.286.04:19:42.40#ibcon#read 6, iclass 13, count 2 2006.286.04:19:42.40#ibcon#end of sib2, iclass 13, count 2 2006.286.04:19:42.40#ibcon#*after write, iclass 13, count 2 2006.286.04:19:42.40#ibcon#*before return 0, iclass 13, count 2 2006.286.04:19:42.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:19:42.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:19:42.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.04:19:42.40#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:42.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:19:42.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:19:42.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:19:42.52#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:19:42.52#ibcon#first serial, iclass 13, count 0 2006.286.04:19:42.52#ibcon#enter sib2, iclass 13, count 0 2006.286.04:19:42.52#ibcon#flushed, iclass 13, count 0 2006.286.04:19:42.52#ibcon#about to write, iclass 13, count 0 2006.286.04:19:42.52#ibcon#wrote, iclass 13, count 0 2006.286.04:19:42.52#ibcon#about to read 3, iclass 13, count 0 2006.286.04:19:42.54#ibcon#read 3, iclass 13, count 0 2006.286.04:19:42.54#ibcon#about to read 4, iclass 13, count 0 2006.286.04:19:42.54#ibcon#read 4, iclass 13, count 0 2006.286.04:19:42.54#ibcon#about to read 5, iclass 13, count 0 2006.286.04:19:42.54#ibcon#read 5, iclass 13, count 0 2006.286.04:19:42.54#ibcon#about to read 6, iclass 13, count 0 2006.286.04:19:42.54#ibcon#read 6, iclass 13, count 0 2006.286.04:19:42.54#ibcon#end of sib2, iclass 13, count 0 2006.286.04:19:42.54#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:19:42.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:19:42.54#ibcon#[25=USB\r\n] 2006.286.04:19:42.54#ibcon#*before write, iclass 13, count 0 2006.286.04:19:42.54#ibcon#enter sib2, iclass 13, count 0 2006.286.04:19:42.54#ibcon#flushed, iclass 13, count 0 2006.286.04:19:42.54#ibcon#about to write, iclass 13, count 0 2006.286.04:19:42.54#ibcon#wrote, iclass 13, count 0 2006.286.04:19:42.54#ibcon#about to read 3, iclass 13, count 0 2006.286.04:19:42.57#ibcon#read 3, iclass 13, count 0 2006.286.04:19:42.57#ibcon#about to read 4, iclass 13, count 0 2006.286.04:19:42.57#ibcon#read 4, iclass 13, count 0 2006.286.04:19:42.57#ibcon#about to read 5, iclass 13, count 0 2006.286.04:19:42.57#ibcon#read 5, iclass 13, count 0 2006.286.04:19:42.57#ibcon#about to read 6, iclass 13, count 0 2006.286.04:19:42.57#ibcon#read 6, iclass 13, count 0 2006.286.04:19:42.57#ibcon#end of sib2, iclass 13, count 0 2006.286.04:19:42.57#ibcon#*after write, iclass 13, count 0 2006.286.04:19:42.57#ibcon#*before return 0, iclass 13, count 0 2006.286.04:19:42.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:19:42.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:19:42.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:19:42.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:19:42.57$vck44/valo=2,534.99 2006.286.04:19:42.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.04:19:42.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.04:19:42.57#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:42.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:19:42.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:19:42.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:19:42.57#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:19:42.57#ibcon#first serial, iclass 15, count 0 2006.286.04:19:42.57#ibcon#enter sib2, iclass 15, count 0 2006.286.04:19:42.57#ibcon#flushed, iclass 15, count 0 2006.286.04:19:42.57#ibcon#about to write, iclass 15, count 0 2006.286.04:19:42.57#ibcon#wrote, iclass 15, count 0 2006.286.04:19:42.57#ibcon#about to read 3, iclass 15, count 0 2006.286.04:19:42.59#ibcon#read 3, iclass 15, count 0 2006.286.04:19:43.10#ibcon#about to read 4, iclass 15, count 0 2006.286.04:19:43.10#ibcon#read 4, iclass 15, count 0 2006.286.04:19:43.10#ibcon#about to read 5, iclass 15, count 0 2006.286.04:19:43.10#ibcon#read 5, iclass 15, count 0 2006.286.04:19:43.10#ibcon#about to read 6, iclass 15, count 0 2006.286.04:19:43.10#ibcon#read 6, iclass 15, count 0 2006.286.04:19:43.10#ibcon#end of sib2, iclass 15, count 0 2006.286.04:19:43.10#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:19:43.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:19:43.10#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:19:43.10#ibcon#*before write, iclass 15, count 0 2006.286.04:19:43.10#ibcon#enter sib2, iclass 15, count 0 2006.286.04:19:43.10#ibcon#flushed, iclass 15, count 0 2006.286.04:19:43.10#ibcon#about to write, iclass 15, count 0 2006.286.04:19:43.10#ibcon#wrote, iclass 15, count 0 2006.286.04:19:43.10#ibcon#about to read 3, iclass 15, count 0 2006.286.04:19:43.14#ibcon#read 3, iclass 15, count 0 2006.286.04:19:43.14#ibcon#about to read 4, iclass 15, count 0 2006.286.04:19:43.14#ibcon#read 4, iclass 15, count 0 2006.286.04:19:43.14#ibcon#about to read 5, iclass 15, count 0 2006.286.04:19:43.14#ibcon#read 5, iclass 15, count 0 2006.286.04:19:43.14#ibcon#about to read 6, iclass 15, count 0 2006.286.04:19:43.14#ibcon#read 6, iclass 15, count 0 2006.286.04:19:43.14#ibcon#end of sib2, iclass 15, count 0 2006.286.04:19:43.14#ibcon#*after write, iclass 15, count 0 2006.286.04:19:43.14#ibcon#*before return 0, iclass 15, count 0 2006.286.04:19:43.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:19:43.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:19:43.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:19:43.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:19:43.14$vck44/va=2,6 2006.286.04:19:43.14#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.04:19:43.14#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.04:19:43.14#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:43.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:19:43.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:19:43.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:19:43.14#ibcon#enter wrdev, iclass 17, count 2 2006.286.04:19:43.14#ibcon#first serial, iclass 17, count 2 2006.286.04:19:43.14#ibcon#enter sib2, iclass 17, count 2 2006.286.04:19:43.14#ibcon#flushed, iclass 17, count 2 2006.286.04:19:43.14#ibcon#about to write, iclass 17, count 2 2006.286.04:19:43.14#ibcon#wrote, iclass 17, count 2 2006.286.04:19:43.14#ibcon#about to read 3, iclass 17, count 2 2006.286.04:19:43.16#ibcon#read 3, iclass 17, count 2 2006.286.04:19:43.16#ibcon#about to read 4, iclass 17, count 2 2006.286.04:19:43.16#ibcon#read 4, iclass 17, count 2 2006.286.04:19:43.16#ibcon#about to read 5, iclass 17, count 2 2006.286.04:19:43.16#ibcon#read 5, iclass 17, count 2 2006.286.04:19:43.16#ibcon#about to read 6, iclass 17, count 2 2006.286.04:19:43.16#ibcon#read 6, iclass 17, count 2 2006.286.04:19:43.16#ibcon#end of sib2, iclass 17, count 2 2006.286.04:19:43.16#ibcon#*mode == 0, iclass 17, count 2 2006.286.04:19:43.16#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.04:19:43.16#ibcon#[25=AT02-06\r\n] 2006.286.04:19:43.16#ibcon#*before write, iclass 17, count 2 2006.286.04:19:43.16#ibcon#enter sib2, iclass 17, count 2 2006.286.04:19:43.16#ibcon#flushed, iclass 17, count 2 2006.286.04:19:43.16#ibcon#about to write, iclass 17, count 2 2006.286.04:19:43.16#ibcon#wrote, iclass 17, count 2 2006.286.04:19:43.16#ibcon#about to read 3, iclass 17, count 2 2006.286.04:19:43.19#ibcon#read 3, iclass 17, count 2 2006.286.04:19:43.19#ibcon#about to read 4, iclass 17, count 2 2006.286.04:19:43.19#ibcon#read 4, iclass 17, count 2 2006.286.04:19:43.19#ibcon#about to read 5, iclass 17, count 2 2006.286.04:19:43.19#ibcon#read 5, iclass 17, count 2 2006.286.04:19:43.19#ibcon#about to read 6, iclass 17, count 2 2006.286.04:19:43.19#ibcon#read 6, iclass 17, count 2 2006.286.04:19:43.19#ibcon#end of sib2, iclass 17, count 2 2006.286.04:19:43.19#ibcon#*after write, iclass 17, count 2 2006.286.04:19:43.19#ibcon#*before return 0, iclass 17, count 2 2006.286.04:19:43.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:19:43.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:19:43.19#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.04:19:43.19#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:43.19#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:19:43.31#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:19:43.31#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:19:43.31#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:19:43.31#ibcon#first serial, iclass 17, count 0 2006.286.04:19:43.31#ibcon#enter sib2, iclass 17, count 0 2006.286.04:19:43.31#ibcon#flushed, iclass 17, count 0 2006.286.04:19:43.31#ibcon#about to write, iclass 17, count 0 2006.286.04:19:43.31#ibcon#wrote, iclass 17, count 0 2006.286.04:19:43.31#ibcon#about to read 3, iclass 17, count 0 2006.286.04:19:43.33#ibcon#read 3, iclass 17, count 0 2006.286.04:19:43.33#ibcon#about to read 4, iclass 17, count 0 2006.286.04:19:43.33#ibcon#read 4, iclass 17, count 0 2006.286.04:19:43.33#ibcon#about to read 5, iclass 17, count 0 2006.286.04:19:43.33#ibcon#read 5, iclass 17, count 0 2006.286.04:19:43.33#ibcon#about to read 6, iclass 17, count 0 2006.286.04:19:43.33#ibcon#read 6, iclass 17, count 0 2006.286.04:19:43.33#ibcon#end of sib2, iclass 17, count 0 2006.286.04:19:43.33#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:19:43.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:19:43.33#ibcon#[25=USB\r\n] 2006.286.04:19:43.33#ibcon#*before write, iclass 17, count 0 2006.286.04:19:43.33#ibcon#enter sib2, iclass 17, count 0 2006.286.04:19:43.33#ibcon#flushed, iclass 17, count 0 2006.286.04:19:43.33#ibcon#about to write, iclass 17, count 0 2006.286.04:19:43.33#ibcon#wrote, iclass 17, count 0 2006.286.04:19:43.33#ibcon#about to read 3, iclass 17, count 0 2006.286.04:19:43.36#ibcon#read 3, iclass 17, count 0 2006.286.04:19:43.36#ibcon#about to read 4, iclass 17, count 0 2006.286.04:19:43.36#ibcon#read 4, iclass 17, count 0 2006.286.04:19:43.36#ibcon#about to read 5, iclass 17, count 0 2006.286.04:19:43.36#ibcon#read 5, iclass 17, count 0 2006.286.04:19:43.36#ibcon#about to read 6, iclass 17, count 0 2006.286.04:19:43.36#ibcon#read 6, iclass 17, count 0 2006.286.04:19:43.36#ibcon#end of sib2, iclass 17, count 0 2006.286.04:19:43.36#ibcon#*after write, iclass 17, count 0 2006.286.04:19:43.36#ibcon#*before return 0, iclass 17, count 0 2006.286.04:19:43.36#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:19:43.36#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:19:43.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:19:43.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:19:43.36$vck44/valo=3,564.99 2006.286.04:19:43.36#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.04:19:43.36#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.04:19:43.36#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:43.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:19:43.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:19:43.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:19:43.36#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:19:43.36#ibcon#first serial, iclass 19, count 0 2006.286.04:19:43.36#ibcon#enter sib2, iclass 19, count 0 2006.286.04:19:43.36#ibcon#flushed, iclass 19, count 0 2006.286.04:19:43.36#ibcon#about to write, iclass 19, count 0 2006.286.04:19:43.36#ibcon#wrote, iclass 19, count 0 2006.286.04:19:43.36#ibcon#about to read 3, iclass 19, count 0 2006.286.04:19:43.38#ibcon#read 3, iclass 19, count 0 2006.286.04:19:43.38#ibcon#about to read 4, iclass 19, count 0 2006.286.04:19:43.38#ibcon#read 4, iclass 19, count 0 2006.286.04:19:43.38#ibcon#about to read 5, iclass 19, count 0 2006.286.04:19:43.38#ibcon#read 5, iclass 19, count 0 2006.286.04:19:43.38#ibcon#about to read 6, iclass 19, count 0 2006.286.04:19:43.38#ibcon#read 6, iclass 19, count 0 2006.286.04:19:43.38#ibcon#end of sib2, iclass 19, count 0 2006.286.04:19:43.38#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:19:43.38#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:19:43.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:19:43.38#ibcon#*before write, iclass 19, count 0 2006.286.04:19:43.38#ibcon#enter sib2, iclass 19, count 0 2006.286.04:19:43.38#ibcon#flushed, iclass 19, count 0 2006.286.04:19:43.38#ibcon#about to write, iclass 19, count 0 2006.286.04:19:43.38#ibcon#wrote, iclass 19, count 0 2006.286.04:19:43.38#ibcon#about to read 3, iclass 19, count 0 2006.286.04:19:43.42#ibcon#read 3, iclass 19, count 0 2006.286.04:19:43.42#ibcon#about to read 4, iclass 19, count 0 2006.286.04:19:43.42#ibcon#read 4, iclass 19, count 0 2006.286.04:19:43.42#ibcon#about to read 5, iclass 19, count 0 2006.286.04:19:43.42#ibcon#read 5, iclass 19, count 0 2006.286.04:19:43.42#ibcon#about to read 6, iclass 19, count 0 2006.286.04:19:43.42#ibcon#read 6, iclass 19, count 0 2006.286.04:19:43.42#ibcon#end of sib2, iclass 19, count 0 2006.286.04:19:43.42#ibcon#*after write, iclass 19, count 0 2006.286.04:19:43.42#ibcon#*before return 0, iclass 19, count 0 2006.286.04:19:43.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:19:43.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:19:43.42#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:19:43.42#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:19:43.42$vck44/va=3,7 2006.286.04:19:43.42#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.04:19:43.42#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.04:19:43.42#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:43.42#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:19:43.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:19:43.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:19:43.48#ibcon#enter wrdev, iclass 21, count 2 2006.286.04:19:43.48#ibcon#first serial, iclass 21, count 2 2006.286.04:19:43.48#ibcon#enter sib2, iclass 21, count 2 2006.286.04:19:43.48#ibcon#flushed, iclass 21, count 2 2006.286.04:19:43.48#ibcon#about to write, iclass 21, count 2 2006.286.04:19:43.48#ibcon#wrote, iclass 21, count 2 2006.286.04:19:43.48#ibcon#about to read 3, iclass 21, count 2 2006.286.04:19:43.50#ibcon#read 3, iclass 21, count 2 2006.286.04:19:43.50#ibcon#about to read 4, iclass 21, count 2 2006.286.04:19:43.50#ibcon#read 4, iclass 21, count 2 2006.286.04:19:43.50#ibcon#about to read 5, iclass 21, count 2 2006.286.04:19:43.50#ibcon#read 5, iclass 21, count 2 2006.286.04:19:43.50#ibcon#about to read 6, iclass 21, count 2 2006.286.04:19:43.50#ibcon#read 6, iclass 21, count 2 2006.286.04:19:43.50#ibcon#end of sib2, iclass 21, count 2 2006.286.04:19:43.50#ibcon#*mode == 0, iclass 21, count 2 2006.286.04:19:43.50#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.04:19:43.50#ibcon#[25=AT03-07\r\n] 2006.286.04:19:43.50#ibcon#*before write, iclass 21, count 2 2006.286.04:19:43.50#ibcon#enter sib2, iclass 21, count 2 2006.286.04:19:43.50#ibcon#flushed, iclass 21, count 2 2006.286.04:19:43.50#ibcon#about to write, iclass 21, count 2 2006.286.04:19:43.50#ibcon#wrote, iclass 21, count 2 2006.286.04:19:43.50#ibcon#about to read 3, iclass 21, count 2 2006.286.04:19:43.53#ibcon#read 3, iclass 21, count 2 2006.286.04:19:43.54#ibcon#about to read 4, iclass 21, count 2 2006.286.04:19:43.54#ibcon#read 4, iclass 21, count 2 2006.286.04:19:43.54#ibcon#about to read 5, iclass 21, count 2 2006.286.04:19:43.54#ibcon#read 5, iclass 21, count 2 2006.286.04:19:43.54#ibcon#about to read 6, iclass 21, count 2 2006.286.04:19:43.54#ibcon#read 6, iclass 21, count 2 2006.286.04:19:43.54#ibcon#end of sib2, iclass 21, count 2 2006.286.04:19:43.54#ibcon#*after write, iclass 21, count 2 2006.286.04:19:43.54#ibcon#*before return 0, iclass 21, count 2 2006.286.04:19:43.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:19:43.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:19:43.54#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.04:19:43.54#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:43.54#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:19:43.65#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:19:43.65#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:19:43.65#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:19:43.65#ibcon#first serial, iclass 21, count 0 2006.286.04:19:43.65#ibcon#enter sib2, iclass 21, count 0 2006.286.04:19:43.65#ibcon#flushed, iclass 21, count 0 2006.286.04:19:43.65#ibcon#about to write, iclass 21, count 0 2006.286.04:19:43.65#ibcon#wrote, iclass 21, count 0 2006.286.04:19:43.65#ibcon#about to read 3, iclass 21, count 0 2006.286.04:19:43.67#ibcon#read 3, iclass 21, count 0 2006.286.04:19:43.67#ibcon#about to read 4, iclass 21, count 0 2006.286.04:19:43.67#ibcon#read 4, iclass 21, count 0 2006.286.04:19:43.67#ibcon#about to read 5, iclass 21, count 0 2006.286.04:19:43.67#ibcon#read 5, iclass 21, count 0 2006.286.04:19:43.67#ibcon#about to read 6, iclass 21, count 0 2006.286.04:19:43.67#ibcon#read 6, iclass 21, count 0 2006.286.04:19:43.67#ibcon#end of sib2, iclass 21, count 0 2006.286.04:19:43.67#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:19:43.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:19:43.67#ibcon#[25=USB\r\n] 2006.286.04:19:43.67#ibcon#*before write, iclass 21, count 0 2006.286.04:19:43.67#ibcon#enter sib2, iclass 21, count 0 2006.286.04:19:43.67#ibcon#flushed, iclass 21, count 0 2006.286.04:19:43.67#ibcon#about to write, iclass 21, count 0 2006.286.04:19:43.67#ibcon#wrote, iclass 21, count 0 2006.286.04:19:43.67#ibcon#about to read 3, iclass 21, count 0 2006.286.04:19:43.70#ibcon#read 3, iclass 21, count 0 2006.286.04:19:43.70#ibcon#about to read 4, iclass 21, count 0 2006.286.04:19:43.70#ibcon#read 4, iclass 21, count 0 2006.286.04:19:43.70#ibcon#about to read 5, iclass 21, count 0 2006.286.04:19:43.70#ibcon#read 5, iclass 21, count 0 2006.286.04:19:43.70#ibcon#about to read 6, iclass 21, count 0 2006.286.04:19:43.70#ibcon#read 6, iclass 21, count 0 2006.286.04:19:43.70#ibcon#end of sib2, iclass 21, count 0 2006.286.04:19:43.70#ibcon#*after write, iclass 21, count 0 2006.286.04:19:43.70#ibcon#*before return 0, iclass 21, count 0 2006.286.04:19:43.70#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:19:43.70#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:19:43.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:19:43.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:19:43.70$vck44/valo=4,624.99 2006.286.04:19:43.70#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.04:19:43.70#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.04:19:43.70#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:43.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:19:43.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:19:43.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:19:43.70#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:19:43.70#ibcon#first serial, iclass 23, count 0 2006.286.04:19:43.70#ibcon#enter sib2, iclass 23, count 0 2006.286.04:19:43.70#ibcon#flushed, iclass 23, count 0 2006.286.04:19:43.70#ibcon#about to write, iclass 23, count 0 2006.286.04:19:43.70#ibcon#wrote, iclass 23, count 0 2006.286.04:19:43.70#ibcon#about to read 3, iclass 23, count 0 2006.286.04:19:43.72#ibcon#read 3, iclass 23, count 0 2006.286.04:19:43.88#ibcon#about to read 4, iclass 23, count 0 2006.286.04:19:43.88#ibcon#read 4, iclass 23, count 0 2006.286.04:19:43.88#ibcon#about to read 5, iclass 23, count 0 2006.286.04:19:43.88#ibcon#read 5, iclass 23, count 0 2006.286.04:19:43.88#ibcon#about to read 6, iclass 23, count 0 2006.286.04:19:43.88#ibcon#read 6, iclass 23, count 0 2006.286.04:19:43.88#ibcon#end of sib2, iclass 23, count 0 2006.286.04:19:43.88#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:19:43.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:19:43.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:19:43.88#ibcon#*before write, iclass 23, count 0 2006.286.04:19:43.88#ibcon#enter sib2, iclass 23, count 0 2006.286.04:19:43.88#ibcon#flushed, iclass 23, count 0 2006.286.04:19:43.88#ibcon#about to write, iclass 23, count 0 2006.286.04:19:43.88#ibcon#wrote, iclass 23, count 0 2006.286.04:19:43.88#ibcon#about to read 3, iclass 23, count 0 2006.286.04:19:43.92#ibcon#read 3, iclass 23, count 0 2006.286.04:19:43.92#ibcon#about to read 4, iclass 23, count 0 2006.286.04:19:43.92#ibcon#read 4, iclass 23, count 0 2006.286.04:19:43.92#ibcon#about to read 5, iclass 23, count 0 2006.286.04:19:43.92#ibcon#read 5, iclass 23, count 0 2006.286.04:19:43.92#ibcon#about to read 6, iclass 23, count 0 2006.286.04:19:43.92#ibcon#read 6, iclass 23, count 0 2006.286.04:19:43.92#ibcon#end of sib2, iclass 23, count 0 2006.286.04:19:43.92#ibcon#*after write, iclass 23, count 0 2006.286.04:19:43.92#ibcon#*before return 0, iclass 23, count 0 2006.286.04:19:43.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:19:43.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:19:43.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:19:43.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:19:43.92$vck44/va=4,6 2006.286.04:19:43.92#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.04:19:43.92#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.04:19:43.92#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:43.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:19:43.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:19:43.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:19:43.92#ibcon#enter wrdev, iclass 25, count 2 2006.286.04:19:43.92#ibcon#first serial, iclass 25, count 2 2006.286.04:19:43.92#ibcon#enter sib2, iclass 25, count 2 2006.286.04:19:43.92#ibcon#flushed, iclass 25, count 2 2006.286.04:19:43.92#ibcon#about to write, iclass 25, count 2 2006.286.04:19:43.92#ibcon#wrote, iclass 25, count 2 2006.286.04:19:43.92#ibcon#about to read 3, iclass 25, count 2 2006.286.04:19:43.94#ibcon#read 3, iclass 25, count 2 2006.286.04:19:43.94#ibcon#about to read 4, iclass 25, count 2 2006.286.04:19:43.94#ibcon#read 4, iclass 25, count 2 2006.286.04:19:43.94#ibcon#about to read 5, iclass 25, count 2 2006.286.04:19:43.94#ibcon#read 5, iclass 25, count 2 2006.286.04:19:43.94#ibcon#about to read 6, iclass 25, count 2 2006.286.04:19:43.94#ibcon#read 6, iclass 25, count 2 2006.286.04:19:43.94#ibcon#end of sib2, iclass 25, count 2 2006.286.04:19:43.94#ibcon#*mode == 0, iclass 25, count 2 2006.286.04:19:43.94#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.04:19:43.94#ibcon#[25=AT04-06\r\n] 2006.286.04:19:43.94#ibcon#*before write, iclass 25, count 2 2006.286.04:19:43.94#ibcon#enter sib2, iclass 25, count 2 2006.286.04:19:43.94#ibcon#flushed, iclass 25, count 2 2006.286.04:19:43.94#ibcon#about to write, iclass 25, count 2 2006.286.04:19:43.94#ibcon#wrote, iclass 25, count 2 2006.286.04:19:43.94#ibcon#about to read 3, iclass 25, count 2 2006.286.04:19:43.97#ibcon#read 3, iclass 25, count 2 2006.286.04:19:43.97#ibcon#about to read 4, iclass 25, count 2 2006.286.04:19:43.97#ibcon#read 4, iclass 25, count 2 2006.286.04:19:43.97#ibcon#about to read 5, iclass 25, count 2 2006.286.04:19:43.97#ibcon#read 5, iclass 25, count 2 2006.286.04:19:43.97#ibcon#about to read 6, iclass 25, count 2 2006.286.04:19:43.97#ibcon#read 6, iclass 25, count 2 2006.286.04:19:43.97#ibcon#end of sib2, iclass 25, count 2 2006.286.04:19:43.97#ibcon#*after write, iclass 25, count 2 2006.286.04:19:43.97#ibcon#*before return 0, iclass 25, count 2 2006.286.04:19:43.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:19:43.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:19:43.97#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.04:19:43.97#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:43.97#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:19:44.09#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:19:44.09#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:19:44.09#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:19:44.09#ibcon#first serial, iclass 25, count 0 2006.286.04:19:44.09#ibcon#enter sib2, iclass 25, count 0 2006.286.04:19:44.09#ibcon#flushed, iclass 25, count 0 2006.286.04:19:44.09#ibcon#about to write, iclass 25, count 0 2006.286.04:19:44.09#ibcon#wrote, iclass 25, count 0 2006.286.04:19:44.09#ibcon#about to read 3, iclass 25, count 0 2006.286.04:19:44.11#ibcon#read 3, iclass 25, count 0 2006.286.04:19:44.11#ibcon#about to read 4, iclass 25, count 0 2006.286.04:19:44.11#ibcon#read 4, iclass 25, count 0 2006.286.04:19:44.11#ibcon#about to read 5, iclass 25, count 0 2006.286.04:19:44.11#ibcon#read 5, iclass 25, count 0 2006.286.04:19:44.11#ibcon#about to read 6, iclass 25, count 0 2006.286.04:19:44.11#ibcon#read 6, iclass 25, count 0 2006.286.04:19:44.11#ibcon#end of sib2, iclass 25, count 0 2006.286.04:19:44.11#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:19:44.11#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:19:44.11#ibcon#[25=USB\r\n] 2006.286.04:19:44.11#ibcon#*before write, iclass 25, count 0 2006.286.04:19:44.11#ibcon#enter sib2, iclass 25, count 0 2006.286.04:19:44.11#ibcon#flushed, iclass 25, count 0 2006.286.04:19:44.11#ibcon#about to write, iclass 25, count 0 2006.286.04:19:44.11#ibcon#wrote, iclass 25, count 0 2006.286.04:19:44.11#ibcon#about to read 3, iclass 25, count 0 2006.286.04:19:44.14#ibcon#read 3, iclass 25, count 0 2006.286.04:19:44.14#ibcon#about to read 4, iclass 25, count 0 2006.286.04:19:44.14#ibcon#read 4, iclass 25, count 0 2006.286.04:19:44.14#ibcon#about to read 5, iclass 25, count 0 2006.286.04:19:44.14#ibcon#read 5, iclass 25, count 0 2006.286.04:19:44.14#ibcon#about to read 6, iclass 25, count 0 2006.286.04:19:44.14#ibcon#read 6, iclass 25, count 0 2006.286.04:19:44.14#ibcon#end of sib2, iclass 25, count 0 2006.286.04:19:44.14#ibcon#*after write, iclass 25, count 0 2006.286.04:19:44.14#ibcon#*before return 0, iclass 25, count 0 2006.286.04:19:44.14#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:19:44.14#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:19:44.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:19:44.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:19:44.14$vck44/valo=5,734.99 2006.286.04:19:44.14#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.04:19:44.14#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.04:19:44.14#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:44.14#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:19:44.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:19:44.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:19:44.14#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:19:44.14#ibcon#first serial, iclass 27, count 0 2006.286.04:19:44.14#ibcon#enter sib2, iclass 27, count 0 2006.286.04:19:44.14#ibcon#flushed, iclass 27, count 0 2006.286.04:19:44.14#ibcon#about to write, iclass 27, count 0 2006.286.04:19:44.14#ibcon#wrote, iclass 27, count 0 2006.286.04:19:44.14#ibcon#about to read 3, iclass 27, count 0 2006.286.04:19:44.16#ibcon#read 3, iclass 27, count 0 2006.286.04:19:44.16#ibcon#about to read 4, iclass 27, count 0 2006.286.04:19:44.16#ibcon#read 4, iclass 27, count 0 2006.286.04:19:44.16#ibcon#about to read 5, iclass 27, count 0 2006.286.04:19:44.16#ibcon#read 5, iclass 27, count 0 2006.286.04:19:44.16#ibcon#about to read 6, iclass 27, count 0 2006.286.04:19:44.16#ibcon#read 6, iclass 27, count 0 2006.286.04:19:44.16#ibcon#end of sib2, iclass 27, count 0 2006.286.04:19:44.16#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:19:44.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:19:44.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:19:44.16#ibcon#*before write, iclass 27, count 0 2006.286.04:19:44.16#ibcon#enter sib2, iclass 27, count 0 2006.286.04:19:44.16#ibcon#flushed, iclass 27, count 0 2006.286.04:19:44.16#ibcon#about to write, iclass 27, count 0 2006.286.04:19:44.16#ibcon#wrote, iclass 27, count 0 2006.286.04:19:44.16#ibcon#about to read 3, iclass 27, count 0 2006.286.04:19:44.20#ibcon#read 3, iclass 27, count 0 2006.286.04:19:44.20#ibcon#about to read 4, iclass 27, count 0 2006.286.04:19:44.20#ibcon#read 4, iclass 27, count 0 2006.286.04:19:44.20#ibcon#about to read 5, iclass 27, count 0 2006.286.04:19:44.20#ibcon#read 5, iclass 27, count 0 2006.286.04:19:44.20#ibcon#about to read 6, iclass 27, count 0 2006.286.04:19:44.20#ibcon#read 6, iclass 27, count 0 2006.286.04:19:44.20#ibcon#end of sib2, iclass 27, count 0 2006.286.04:19:44.20#ibcon#*after write, iclass 27, count 0 2006.286.04:19:44.20#ibcon#*before return 0, iclass 27, count 0 2006.286.04:19:44.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:19:44.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:19:44.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:19:44.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:19:44.20$vck44/va=5,3 2006.286.04:19:44.20#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.04:19:44.20#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.04:19:44.20#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:44.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:19:44.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:19:44.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:19:44.26#ibcon#enter wrdev, iclass 29, count 2 2006.286.04:19:44.26#ibcon#first serial, iclass 29, count 2 2006.286.04:19:44.26#ibcon#enter sib2, iclass 29, count 2 2006.286.04:19:44.26#ibcon#flushed, iclass 29, count 2 2006.286.04:19:44.26#ibcon#about to write, iclass 29, count 2 2006.286.04:19:44.26#ibcon#wrote, iclass 29, count 2 2006.286.04:19:44.26#ibcon#about to read 3, iclass 29, count 2 2006.286.04:19:44.28#ibcon#read 3, iclass 29, count 2 2006.286.04:19:44.28#ibcon#about to read 4, iclass 29, count 2 2006.286.04:19:44.28#ibcon#read 4, iclass 29, count 2 2006.286.04:19:44.28#ibcon#about to read 5, iclass 29, count 2 2006.286.04:19:44.28#ibcon#read 5, iclass 29, count 2 2006.286.04:19:44.28#ibcon#about to read 6, iclass 29, count 2 2006.286.04:19:44.28#ibcon#read 6, iclass 29, count 2 2006.286.04:19:44.28#ibcon#end of sib2, iclass 29, count 2 2006.286.04:19:44.28#ibcon#*mode == 0, iclass 29, count 2 2006.286.04:19:44.28#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.04:19:44.28#ibcon#[25=AT05-03\r\n] 2006.286.04:19:44.28#ibcon#*before write, iclass 29, count 2 2006.286.04:19:44.28#ibcon#enter sib2, iclass 29, count 2 2006.286.04:19:44.28#ibcon#flushed, iclass 29, count 2 2006.286.04:19:44.28#ibcon#about to write, iclass 29, count 2 2006.286.04:19:44.28#ibcon#wrote, iclass 29, count 2 2006.286.04:19:44.28#ibcon#about to read 3, iclass 29, count 2 2006.286.04:19:44.31#ibcon#read 3, iclass 29, count 2 2006.286.04:19:44.31#ibcon#about to read 4, iclass 29, count 2 2006.286.04:19:44.31#ibcon#read 4, iclass 29, count 2 2006.286.04:19:44.31#ibcon#about to read 5, iclass 29, count 2 2006.286.04:19:44.31#ibcon#read 5, iclass 29, count 2 2006.286.04:19:44.31#ibcon#about to read 6, iclass 29, count 2 2006.286.04:19:44.31#ibcon#read 6, iclass 29, count 2 2006.286.04:19:44.31#ibcon#end of sib2, iclass 29, count 2 2006.286.04:19:44.31#ibcon#*after write, iclass 29, count 2 2006.286.04:19:44.31#ibcon#*before return 0, iclass 29, count 2 2006.286.04:19:44.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:19:44.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:19:44.31#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.04:19:44.31#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:44.31#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:19:44.43#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:19:44.43#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:19:44.43#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:19:44.43#ibcon#first serial, iclass 29, count 0 2006.286.04:19:44.43#ibcon#enter sib2, iclass 29, count 0 2006.286.04:19:44.43#ibcon#flushed, iclass 29, count 0 2006.286.04:19:44.43#ibcon#about to write, iclass 29, count 0 2006.286.04:19:44.43#ibcon#wrote, iclass 29, count 0 2006.286.04:19:44.43#ibcon#about to read 3, iclass 29, count 0 2006.286.04:19:44.45#ibcon#read 3, iclass 29, count 0 2006.286.04:19:44.45#ibcon#about to read 4, iclass 29, count 0 2006.286.04:19:44.45#ibcon#read 4, iclass 29, count 0 2006.286.04:19:44.45#ibcon#about to read 5, iclass 29, count 0 2006.286.04:19:44.45#ibcon#read 5, iclass 29, count 0 2006.286.04:19:44.45#ibcon#about to read 6, iclass 29, count 0 2006.286.04:19:44.45#ibcon#read 6, iclass 29, count 0 2006.286.04:19:44.45#ibcon#end of sib2, iclass 29, count 0 2006.286.04:19:44.45#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:19:44.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:19:44.45#ibcon#[25=USB\r\n] 2006.286.04:19:44.45#ibcon#*before write, iclass 29, count 0 2006.286.04:19:44.45#ibcon#enter sib2, iclass 29, count 0 2006.286.04:19:44.45#ibcon#flushed, iclass 29, count 0 2006.286.04:19:44.45#ibcon#about to write, iclass 29, count 0 2006.286.04:19:44.45#ibcon#wrote, iclass 29, count 0 2006.286.04:19:44.45#ibcon#about to read 3, iclass 29, count 0 2006.286.04:19:44.48#ibcon#read 3, iclass 29, count 0 2006.286.04:19:44.48#ibcon#about to read 4, iclass 29, count 0 2006.286.04:19:44.48#ibcon#read 4, iclass 29, count 0 2006.286.04:19:44.48#ibcon#about to read 5, iclass 29, count 0 2006.286.04:19:44.48#ibcon#read 5, iclass 29, count 0 2006.286.04:19:44.48#ibcon#about to read 6, iclass 29, count 0 2006.286.04:19:44.48#ibcon#read 6, iclass 29, count 0 2006.286.04:19:44.48#ibcon#end of sib2, iclass 29, count 0 2006.286.04:19:44.48#ibcon#*after write, iclass 29, count 0 2006.286.04:19:44.48#ibcon#*before return 0, iclass 29, count 0 2006.286.04:19:44.48#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:19:44.48#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:19:44.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:19:44.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:19:44.48$vck44/valo=6,814.99 2006.286.04:19:44.48#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.04:19:44.48#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.04:19:44.48#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:44.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:19:44.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:19:44.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:19:44.48#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:19:44.48#ibcon#first serial, iclass 31, count 0 2006.286.04:19:44.48#ibcon#enter sib2, iclass 31, count 0 2006.286.04:19:44.48#ibcon#flushed, iclass 31, count 0 2006.286.04:19:44.48#ibcon#about to write, iclass 31, count 0 2006.286.04:19:44.48#ibcon#wrote, iclass 31, count 0 2006.286.04:19:44.48#ibcon#about to read 3, iclass 31, count 0 2006.286.04:19:44.50#ibcon#read 3, iclass 31, count 0 2006.286.04:19:44.50#ibcon#about to read 4, iclass 31, count 0 2006.286.04:19:44.50#ibcon#read 4, iclass 31, count 0 2006.286.04:19:44.50#ibcon#about to read 5, iclass 31, count 0 2006.286.04:19:44.50#ibcon#read 5, iclass 31, count 0 2006.286.04:19:44.50#ibcon#about to read 6, iclass 31, count 0 2006.286.04:19:44.50#ibcon#read 6, iclass 31, count 0 2006.286.04:19:44.50#ibcon#end of sib2, iclass 31, count 0 2006.286.04:19:44.50#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:19:44.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:19:44.50#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:19:44.50#ibcon#*before write, iclass 31, count 0 2006.286.04:19:44.50#ibcon#enter sib2, iclass 31, count 0 2006.286.04:19:44.50#ibcon#flushed, iclass 31, count 0 2006.286.04:19:44.50#ibcon#about to write, iclass 31, count 0 2006.286.04:19:44.50#ibcon#wrote, iclass 31, count 0 2006.286.04:19:44.50#ibcon#about to read 3, iclass 31, count 0 2006.286.04:19:44.54#ibcon#read 3, iclass 31, count 0 2006.286.04:19:44.54#ibcon#about to read 4, iclass 31, count 0 2006.286.04:19:44.54#ibcon#read 4, iclass 31, count 0 2006.286.04:19:44.54#ibcon#about to read 5, iclass 31, count 0 2006.286.04:19:44.54#ibcon#read 5, iclass 31, count 0 2006.286.04:19:44.54#ibcon#about to read 6, iclass 31, count 0 2006.286.04:19:44.54#ibcon#read 6, iclass 31, count 0 2006.286.04:19:44.54#ibcon#end of sib2, iclass 31, count 0 2006.286.04:19:44.54#ibcon#*after write, iclass 31, count 0 2006.286.04:19:44.54#ibcon#*before return 0, iclass 31, count 0 2006.286.04:19:44.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:19:44.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:19:44.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:19:44.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:19:44.54$vck44/va=6,4 2006.286.04:19:44.54#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.04:19:44.54#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.04:19:44.54#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:44.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:19:44.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:19:44.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:19:44.60#ibcon#enter wrdev, iclass 33, count 2 2006.286.04:19:44.60#ibcon#first serial, iclass 33, count 2 2006.286.04:19:44.60#ibcon#enter sib2, iclass 33, count 2 2006.286.04:19:44.60#ibcon#flushed, iclass 33, count 2 2006.286.04:19:44.60#ibcon#about to write, iclass 33, count 2 2006.286.04:19:44.60#ibcon#wrote, iclass 33, count 2 2006.286.04:19:44.60#ibcon#about to read 3, iclass 33, count 2 2006.286.04:19:44.62#ibcon#read 3, iclass 33, count 2 2006.286.04:19:44.69#ibcon#about to read 4, iclass 33, count 2 2006.286.04:19:44.69#ibcon#read 4, iclass 33, count 2 2006.286.04:19:44.69#ibcon#about to read 5, iclass 33, count 2 2006.286.04:19:44.69#ibcon#read 5, iclass 33, count 2 2006.286.04:19:44.69#ibcon#about to read 6, iclass 33, count 2 2006.286.04:19:44.69#ibcon#read 6, iclass 33, count 2 2006.286.04:19:44.69#ibcon#end of sib2, iclass 33, count 2 2006.286.04:19:44.69#ibcon#*mode == 0, iclass 33, count 2 2006.286.04:19:44.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.04:19:44.69#ibcon#[25=AT06-04\r\n] 2006.286.04:19:44.69#ibcon#*before write, iclass 33, count 2 2006.286.04:19:44.69#ibcon#enter sib2, iclass 33, count 2 2006.286.04:19:44.69#ibcon#flushed, iclass 33, count 2 2006.286.04:19:44.69#ibcon#about to write, iclass 33, count 2 2006.286.04:19:44.69#ibcon#wrote, iclass 33, count 2 2006.286.04:19:44.69#ibcon#about to read 3, iclass 33, count 2 2006.286.04:19:44.73#ibcon#read 3, iclass 33, count 2 2006.286.04:19:44.73#ibcon#about to read 4, iclass 33, count 2 2006.286.04:19:44.73#ibcon#read 4, iclass 33, count 2 2006.286.04:19:44.73#ibcon#about to read 5, iclass 33, count 2 2006.286.04:19:44.73#ibcon#read 5, iclass 33, count 2 2006.286.04:19:44.73#ibcon#about to read 6, iclass 33, count 2 2006.286.04:19:44.73#ibcon#read 6, iclass 33, count 2 2006.286.04:19:44.73#ibcon#end of sib2, iclass 33, count 2 2006.286.04:19:44.73#ibcon#*after write, iclass 33, count 2 2006.286.04:19:44.73#ibcon#*before return 0, iclass 33, count 2 2006.286.04:19:44.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:19:44.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:19:44.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.04:19:44.73#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:44.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:19:44.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:19:44.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:19:44.85#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:19:44.85#ibcon#first serial, iclass 33, count 0 2006.286.04:19:44.85#ibcon#enter sib2, iclass 33, count 0 2006.286.04:19:44.85#ibcon#flushed, iclass 33, count 0 2006.286.04:19:44.85#ibcon#about to write, iclass 33, count 0 2006.286.04:19:44.85#ibcon#wrote, iclass 33, count 0 2006.286.04:19:44.85#ibcon#about to read 3, iclass 33, count 0 2006.286.04:19:44.87#ibcon#read 3, iclass 33, count 0 2006.286.04:19:44.87#ibcon#about to read 4, iclass 33, count 0 2006.286.04:19:44.87#ibcon#read 4, iclass 33, count 0 2006.286.04:19:44.87#ibcon#about to read 5, iclass 33, count 0 2006.286.04:19:44.87#ibcon#read 5, iclass 33, count 0 2006.286.04:19:44.87#ibcon#about to read 6, iclass 33, count 0 2006.286.04:19:44.87#ibcon#read 6, iclass 33, count 0 2006.286.04:19:44.87#ibcon#end of sib2, iclass 33, count 0 2006.286.04:19:44.87#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:19:44.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:19:44.87#ibcon#[25=USB\r\n] 2006.286.04:19:44.87#ibcon#*before write, iclass 33, count 0 2006.286.04:19:44.87#ibcon#enter sib2, iclass 33, count 0 2006.286.04:19:44.87#ibcon#flushed, iclass 33, count 0 2006.286.04:19:44.87#ibcon#about to write, iclass 33, count 0 2006.286.04:19:44.87#ibcon#wrote, iclass 33, count 0 2006.286.04:19:44.87#ibcon#about to read 3, iclass 33, count 0 2006.286.04:19:44.90#ibcon#read 3, iclass 33, count 0 2006.286.04:19:44.90#ibcon#about to read 4, iclass 33, count 0 2006.286.04:19:44.90#ibcon#read 4, iclass 33, count 0 2006.286.04:19:44.90#ibcon#about to read 5, iclass 33, count 0 2006.286.04:19:44.90#ibcon#read 5, iclass 33, count 0 2006.286.04:19:44.90#ibcon#about to read 6, iclass 33, count 0 2006.286.04:19:44.90#ibcon#read 6, iclass 33, count 0 2006.286.04:19:44.90#ibcon#end of sib2, iclass 33, count 0 2006.286.04:19:44.90#ibcon#*after write, iclass 33, count 0 2006.286.04:19:44.90#ibcon#*before return 0, iclass 33, count 0 2006.286.04:19:44.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:19:44.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:19:44.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:19:44.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:19:44.90$vck44/valo=7,864.99 2006.286.04:19:44.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.04:19:44.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.04:19:44.90#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:44.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:19:44.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:19:44.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:19:44.90#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:19:44.90#ibcon#first serial, iclass 35, count 0 2006.286.04:19:44.90#ibcon#enter sib2, iclass 35, count 0 2006.286.04:19:44.90#ibcon#flushed, iclass 35, count 0 2006.286.04:19:44.90#ibcon#about to write, iclass 35, count 0 2006.286.04:19:44.90#ibcon#wrote, iclass 35, count 0 2006.286.04:19:44.90#ibcon#about to read 3, iclass 35, count 0 2006.286.04:19:44.92#ibcon#read 3, iclass 35, count 0 2006.286.04:19:44.92#ibcon#about to read 4, iclass 35, count 0 2006.286.04:19:44.92#ibcon#read 4, iclass 35, count 0 2006.286.04:19:44.92#ibcon#about to read 5, iclass 35, count 0 2006.286.04:19:44.92#ibcon#read 5, iclass 35, count 0 2006.286.04:19:44.92#ibcon#about to read 6, iclass 35, count 0 2006.286.04:19:44.92#ibcon#read 6, iclass 35, count 0 2006.286.04:19:44.92#ibcon#end of sib2, iclass 35, count 0 2006.286.04:19:44.92#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:19:44.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:19:44.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:19:44.92#ibcon#*before write, iclass 35, count 0 2006.286.04:19:44.92#ibcon#enter sib2, iclass 35, count 0 2006.286.04:19:44.92#ibcon#flushed, iclass 35, count 0 2006.286.04:19:44.92#ibcon#about to write, iclass 35, count 0 2006.286.04:19:44.92#ibcon#wrote, iclass 35, count 0 2006.286.04:19:44.92#ibcon#about to read 3, iclass 35, count 0 2006.286.04:19:44.96#ibcon#read 3, iclass 35, count 0 2006.286.04:19:44.96#ibcon#about to read 4, iclass 35, count 0 2006.286.04:19:44.96#ibcon#read 4, iclass 35, count 0 2006.286.04:19:44.96#ibcon#about to read 5, iclass 35, count 0 2006.286.04:19:44.96#ibcon#read 5, iclass 35, count 0 2006.286.04:19:44.96#ibcon#about to read 6, iclass 35, count 0 2006.286.04:19:44.96#ibcon#read 6, iclass 35, count 0 2006.286.04:19:44.96#ibcon#end of sib2, iclass 35, count 0 2006.286.04:19:44.96#ibcon#*after write, iclass 35, count 0 2006.286.04:19:44.96#ibcon#*before return 0, iclass 35, count 0 2006.286.04:19:44.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:19:44.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:19:44.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:19:44.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:19:44.96$vck44/va=7,4 2006.286.04:19:44.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.04:19:44.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.04:19:44.96#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:44.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:19:45.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:19:45.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:19:45.02#ibcon#enter wrdev, iclass 37, count 2 2006.286.04:19:45.02#ibcon#first serial, iclass 37, count 2 2006.286.04:19:45.02#ibcon#enter sib2, iclass 37, count 2 2006.286.04:19:45.02#ibcon#flushed, iclass 37, count 2 2006.286.04:19:45.02#ibcon#about to write, iclass 37, count 2 2006.286.04:19:45.02#ibcon#wrote, iclass 37, count 2 2006.286.04:19:45.02#ibcon#about to read 3, iclass 37, count 2 2006.286.04:19:45.04#ibcon#read 3, iclass 37, count 2 2006.286.04:19:45.04#ibcon#about to read 4, iclass 37, count 2 2006.286.04:19:45.04#ibcon#read 4, iclass 37, count 2 2006.286.04:19:45.04#ibcon#about to read 5, iclass 37, count 2 2006.286.04:19:45.04#ibcon#read 5, iclass 37, count 2 2006.286.04:19:45.04#ibcon#about to read 6, iclass 37, count 2 2006.286.04:19:45.04#ibcon#read 6, iclass 37, count 2 2006.286.04:19:45.04#ibcon#end of sib2, iclass 37, count 2 2006.286.04:19:45.04#ibcon#*mode == 0, iclass 37, count 2 2006.286.04:19:45.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.04:19:45.04#ibcon#[25=AT07-04\r\n] 2006.286.04:19:45.04#ibcon#*before write, iclass 37, count 2 2006.286.04:19:45.04#ibcon#enter sib2, iclass 37, count 2 2006.286.04:19:45.04#ibcon#flushed, iclass 37, count 2 2006.286.04:19:45.04#ibcon#about to write, iclass 37, count 2 2006.286.04:19:45.04#ibcon#wrote, iclass 37, count 2 2006.286.04:19:45.04#ibcon#about to read 3, iclass 37, count 2 2006.286.04:19:45.07#ibcon#read 3, iclass 37, count 2 2006.286.04:19:45.07#ibcon#about to read 4, iclass 37, count 2 2006.286.04:19:45.07#ibcon#read 4, iclass 37, count 2 2006.286.04:19:45.07#ibcon#about to read 5, iclass 37, count 2 2006.286.04:19:45.07#ibcon#read 5, iclass 37, count 2 2006.286.04:19:45.07#ibcon#about to read 6, iclass 37, count 2 2006.286.04:19:45.07#ibcon#read 6, iclass 37, count 2 2006.286.04:19:45.07#ibcon#end of sib2, iclass 37, count 2 2006.286.04:19:45.07#ibcon#*after write, iclass 37, count 2 2006.286.04:19:45.07#ibcon#*before return 0, iclass 37, count 2 2006.286.04:19:45.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:19:45.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:19:45.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.04:19:45.07#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:45.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:19:45.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:19:45.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:19:45.19#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:19:45.19#ibcon#first serial, iclass 37, count 0 2006.286.04:19:45.19#ibcon#enter sib2, iclass 37, count 0 2006.286.04:19:45.19#ibcon#flushed, iclass 37, count 0 2006.286.04:19:45.19#ibcon#about to write, iclass 37, count 0 2006.286.04:19:45.19#ibcon#wrote, iclass 37, count 0 2006.286.04:19:45.19#ibcon#about to read 3, iclass 37, count 0 2006.286.04:19:45.21#ibcon#read 3, iclass 37, count 0 2006.286.04:19:45.21#ibcon#about to read 4, iclass 37, count 0 2006.286.04:19:45.21#ibcon#read 4, iclass 37, count 0 2006.286.04:19:45.21#ibcon#about to read 5, iclass 37, count 0 2006.286.04:19:45.21#ibcon#read 5, iclass 37, count 0 2006.286.04:19:45.21#ibcon#about to read 6, iclass 37, count 0 2006.286.04:19:45.21#ibcon#read 6, iclass 37, count 0 2006.286.04:19:45.21#ibcon#end of sib2, iclass 37, count 0 2006.286.04:19:45.21#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:19:45.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:19:45.21#ibcon#[25=USB\r\n] 2006.286.04:19:45.21#ibcon#*before write, iclass 37, count 0 2006.286.04:19:45.21#ibcon#enter sib2, iclass 37, count 0 2006.286.04:19:45.21#ibcon#flushed, iclass 37, count 0 2006.286.04:19:45.21#ibcon#about to write, iclass 37, count 0 2006.286.04:19:45.21#ibcon#wrote, iclass 37, count 0 2006.286.04:19:45.21#ibcon#about to read 3, iclass 37, count 0 2006.286.04:19:45.24#ibcon#read 3, iclass 37, count 0 2006.286.04:19:45.24#ibcon#about to read 4, iclass 37, count 0 2006.286.04:19:45.24#ibcon#read 4, iclass 37, count 0 2006.286.04:19:45.24#ibcon#about to read 5, iclass 37, count 0 2006.286.04:19:45.24#ibcon#read 5, iclass 37, count 0 2006.286.04:19:45.24#ibcon#about to read 6, iclass 37, count 0 2006.286.04:19:45.24#ibcon#read 6, iclass 37, count 0 2006.286.04:19:45.24#ibcon#end of sib2, iclass 37, count 0 2006.286.04:19:45.24#ibcon#*after write, iclass 37, count 0 2006.286.04:19:45.24#ibcon#*before return 0, iclass 37, count 0 2006.286.04:19:45.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:19:45.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:19:45.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:19:45.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:19:45.24$vck44/valo=8,884.99 2006.286.04:19:45.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.04:19:45.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.04:19:45.24#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:45.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:19:45.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:19:45.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:19:45.24#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:19:45.24#ibcon#first serial, iclass 39, count 0 2006.286.04:19:45.24#ibcon#enter sib2, iclass 39, count 0 2006.286.04:19:45.24#ibcon#flushed, iclass 39, count 0 2006.286.04:19:45.24#ibcon#about to write, iclass 39, count 0 2006.286.04:19:45.24#ibcon#wrote, iclass 39, count 0 2006.286.04:19:45.24#ibcon#about to read 3, iclass 39, count 0 2006.286.04:19:45.26#ibcon#read 3, iclass 39, count 0 2006.286.04:19:45.26#ibcon#about to read 4, iclass 39, count 0 2006.286.04:19:45.26#ibcon#read 4, iclass 39, count 0 2006.286.04:19:45.26#ibcon#about to read 5, iclass 39, count 0 2006.286.04:19:45.26#ibcon#read 5, iclass 39, count 0 2006.286.04:19:45.26#ibcon#about to read 6, iclass 39, count 0 2006.286.04:19:45.26#ibcon#read 6, iclass 39, count 0 2006.286.04:19:45.26#ibcon#end of sib2, iclass 39, count 0 2006.286.04:19:45.26#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:19:45.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:19:45.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:19:45.26#ibcon#*before write, iclass 39, count 0 2006.286.04:19:45.26#ibcon#enter sib2, iclass 39, count 0 2006.286.04:19:45.26#ibcon#flushed, iclass 39, count 0 2006.286.04:19:45.26#ibcon#about to write, iclass 39, count 0 2006.286.04:19:45.26#ibcon#wrote, iclass 39, count 0 2006.286.04:19:45.26#ibcon#about to read 3, iclass 39, count 0 2006.286.04:19:45.30#ibcon#read 3, iclass 39, count 0 2006.286.04:19:45.30#ibcon#about to read 4, iclass 39, count 0 2006.286.04:19:45.30#ibcon#read 4, iclass 39, count 0 2006.286.04:19:45.30#ibcon#about to read 5, iclass 39, count 0 2006.286.04:19:45.30#ibcon#read 5, iclass 39, count 0 2006.286.04:19:45.30#ibcon#about to read 6, iclass 39, count 0 2006.286.04:19:45.30#ibcon#read 6, iclass 39, count 0 2006.286.04:19:45.30#ibcon#end of sib2, iclass 39, count 0 2006.286.04:19:45.30#ibcon#*after write, iclass 39, count 0 2006.286.04:19:45.30#ibcon#*before return 0, iclass 39, count 0 2006.286.04:19:45.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:19:45.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:19:45.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:19:45.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:19:45.30$vck44/va=8,3 2006.286.04:19:45.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.04:19:45.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.04:19:45.30#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:45.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:19:45.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:19:45.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:19:45.36#ibcon#enter wrdev, iclass 3, count 2 2006.286.04:19:45.36#ibcon#first serial, iclass 3, count 2 2006.286.04:19:45.36#ibcon#enter sib2, iclass 3, count 2 2006.286.04:19:45.36#ibcon#flushed, iclass 3, count 2 2006.286.04:19:45.36#ibcon#about to write, iclass 3, count 2 2006.286.04:19:45.36#ibcon#wrote, iclass 3, count 2 2006.286.04:19:45.36#ibcon#about to read 3, iclass 3, count 2 2006.286.04:19:45.38#ibcon#read 3, iclass 3, count 2 2006.286.04:19:45.38#ibcon#about to read 4, iclass 3, count 2 2006.286.04:19:45.38#ibcon#read 4, iclass 3, count 2 2006.286.04:19:45.38#ibcon#about to read 5, iclass 3, count 2 2006.286.04:19:45.38#ibcon#read 5, iclass 3, count 2 2006.286.04:19:45.38#ibcon#about to read 6, iclass 3, count 2 2006.286.04:19:45.38#ibcon#read 6, iclass 3, count 2 2006.286.04:19:45.38#ibcon#end of sib2, iclass 3, count 2 2006.286.04:19:45.38#ibcon#*mode == 0, iclass 3, count 2 2006.286.04:19:45.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.04:19:45.38#ibcon#[25=AT08-03\r\n] 2006.286.04:19:45.38#ibcon#*before write, iclass 3, count 2 2006.286.04:19:45.38#ibcon#enter sib2, iclass 3, count 2 2006.286.04:19:45.38#ibcon#flushed, iclass 3, count 2 2006.286.04:19:45.38#ibcon#about to write, iclass 3, count 2 2006.286.04:19:45.38#ibcon#wrote, iclass 3, count 2 2006.286.04:19:45.38#ibcon#about to read 3, iclass 3, count 2 2006.286.04:19:45.41#ibcon#read 3, iclass 3, count 2 2006.286.04:19:45.41#ibcon#about to read 4, iclass 3, count 2 2006.286.04:19:45.41#ibcon#read 4, iclass 3, count 2 2006.286.04:19:45.41#ibcon#about to read 5, iclass 3, count 2 2006.286.04:19:45.41#ibcon#read 5, iclass 3, count 2 2006.286.04:19:45.41#ibcon#about to read 6, iclass 3, count 2 2006.286.04:19:45.41#ibcon#read 6, iclass 3, count 2 2006.286.04:19:45.41#ibcon#end of sib2, iclass 3, count 2 2006.286.04:19:45.41#ibcon#*after write, iclass 3, count 2 2006.286.04:19:45.41#ibcon#*before return 0, iclass 3, count 2 2006.286.04:19:45.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:19:45.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:19:45.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.04:19:45.41#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:45.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:19:45.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:19:45.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:19:45.53#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:19:45.53#ibcon#first serial, iclass 3, count 0 2006.286.04:19:45.53#ibcon#enter sib2, iclass 3, count 0 2006.286.04:19:45.53#ibcon#flushed, iclass 3, count 0 2006.286.04:19:45.53#ibcon#about to write, iclass 3, count 0 2006.286.04:19:45.53#ibcon#wrote, iclass 3, count 0 2006.286.04:19:45.53#ibcon#about to read 3, iclass 3, count 0 2006.286.04:19:45.55#ibcon#read 3, iclass 3, count 0 2006.286.04:19:45.55#ibcon#about to read 4, iclass 3, count 0 2006.286.04:19:45.55#ibcon#read 4, iclass 3, count 0 2006.286.04:19:45.55#ibcon#about to read 5, iclass 3, count 0 2006.286.04:19:45.55#ibcon#read 5, iclass 3, count 0 2006.286.04:19:45.55#ibcon#about to read 6, iclass 3, count 0 2006.286.04:19:45.55#ibcon#read 6, iclass 3, count 0 2006.286.04:19:45.55#ibcon#end of sib2, iclass 3, count 0 2006.286.04:19:45.55#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:19:45.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:19:45.55#ibcon#[25=USB\r\n] 2006.286.04:19:45.55#ibcon#*before write, iclass 3, count 0 2006.286.04:19:45.55#ibcon#enter sib2, iclass 3, count 0 2006.286.04:19:45.55#ibcon#flushed, iclass 3, count 0 2006.286.04:19:45.55#ibcon#about to write, iclass 3, count 0 2006.286.04:19:45.55#ibcon#wrote, iclass 3, count 0 2006.286.04:19:45.55#ibcon#about to read 3, iclass 3, count 0 2006.286.04:19:45.58#ibcon#read 3, iclass 3, count 0 2006.286.04:19:45.58#ibcon#about to read 4, iclass 3, count 0 2006.286.04:19:45.58#ibcon#read 4, iclass 3, count 0 2006.286.04:19:45.58#ibcon#about to read 5, iclass 3, count 0 2006.286.04:19:45.58#ibcon#read 5, iclass 3, count 0 2006.286.04:19:45.58#ibcon#about to read 6, iclass 3, count 0 2006.286.04:19:45.58#ibcon#read 6, iclass 3, count 0 2006.286.04:19:45.58#ibcon#end of sib2, iclass 3, count 0 2006.286.04:19:45.58#ibcon#*after write, iclass 3, count 0 2006.286.04:19:45.58#ibcon#*before return 0, iclass 3, count 0 2006.286.04:19:45.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:19:45.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:19:45.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:19:45.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:19:45.58$vck44/vblo=1,629.99 2006.286.04:19:45.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.04:19:45.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.04:19:45.58#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:45.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:19:45.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:19:45.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:19:45.58#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:19:45.58#ibcon#first serial, iclass 5, count 0 2006.286.04:19:45.58#ibcon#enter sib2, iclass 5, count 0 2006.286.04:19:45.58#ibcon#flushed, iclass 5, count 0 2006.286.04:19:45.58#ibcon#about to write, iclass 5, count 0 2006.286.04:19:45.58#ibcon#wrote, iclass 5, count 0 2006.286.04:19:45.58#ibcon#about to read 3, iclass 5, count 0 2006.286.04:19:45.60#ibcon#read 3, iclass 5, count 0 2006.286.04:19:45.67#ibcon#about to read 4, iclass 5, count 0 2006.286.04:19:45.67#ibcon#read 4, iclass 5, count 0 2006.286.04:19:45.67#ibcon#about to read 5, iclass 5, count 0 2006.286.04:19:45.67#ibcon#read 5, iclass 5, count 0 2006.286.04:19:45.67#ibcon#about to read 6, iclass 5, count 0 2006.286.04:19:45.67#ibcon#read 6, iclass 5, count 0 2006.286.04:19:45.67#ibcon#end of sib2, iclass 5, count 0 2006.286.04:19:45.67#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:19:45.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:19:45.67#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:19:45.67#ibcon#*before write, iclass 5, count 0 2006.286.04:19:45.67#ibcon#enter sib2, iclass 5, count 0 2006.286.04:19:45.67#ibcon#flushed, iclass 5, count 0 2006.286.04:19:45.67#ibcon#about to write, iclass 5, count 0 2006.286.04:19:45.67#ibcon#wrote, iclass 5, count 0 2006.286.04:19:45.67#ibcon#about to read 3, iclass 5, count 0 2006.286.04:19:45.71#ibcon#read 3, iclass 5, count 0 2006.286.04:19:45.71#ibcon#about to read 4, iclass 5, count 0 2006.286.04:19:45.71#ibcon#read 4, iclass 5, count 0 2006.286.04:19:45.71#ibcon#about to read 5, iclass 5, count 0 2006.286.04:19:45.71#ibcon#read 5, iclass 5, count 0 2006.286.04:19:45.71#ibcon#about to read 6, iclass 5, count 0 2006.286.04:19:45.71#ibcon#read 6, iclass 5, count 0 2006.286.04:19:45.71#ibcon#end of sib2, iclass 5, count 0 2006.286.04:19:45.71#ibcon#*after write, iclass 5, count 0 2006.286.04:19:45.71#ibcon#*before return 0, iclass 5, count 0 2006.286.04:19:45.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:19:45.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:19:45.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:19:45.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:19:45.71$vck44/vb=1,4 2006.286.04:19:45.71#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.04:19:45.71#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.04:19:45.71#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:45.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:19:45.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:19:45.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:19:45.71#ibcon#enter wrdev, iclass 7, count 2 2006.286.04:19:45.71#ibcon#first serial, iclass 7, count 2 2006.286.04:19:45.71#ibcon#enter sib2, iclass 7, count 2 2006.286.04:19:45.71#ibcon#flushed, iclass 7, count 2 2006.286.04:19:45.71#ibcon#about to write, iclass 7, count 2 2006.286.04:19:45.71#ibcon#wrote, iclass 7, count 2 2006.286.04:19:45.71#ibcon#about to read 3, iclass 7, count 2 2006.286.04:19:45.73#ibcon#read 3, iclass 7, count 2 2006.286.04:19:45.73#ibcon#about to read 4, iclass 7, count 2 2006.286.04:19:45.73#ibcon#read 4, iclass 7, count 2 2006.286.04:19:45.73#ibcon#about to read 5, iclass 7, count 2 2006.286.04:19:45.73#ibcon#read 5, iclass 7, count 2 2006.286.04:19:45.73#ibcon#about to read 6, iclass 7, count 2 2006.286.04:19:45.73#ibcon#read 6, iclass 7, count 2 2006.286.04:19:45.73#ibcon#end of sib2, iclass 7, count 2 2006.286.04:19:45.73#ibcon#*mode == 0, iclass 7, count 2 2006.286.04:19:45.73#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.04:19:45.73#ibcon#[27=AT01-04\r\n] 2006.286.04:19:45.73#ibcon#*before write, iclass 7, count 2 2006.286.04:19:45.73#ibcon#enter sib2, iclass 7, count 2 2006.286.04:19:45.73#ibcon#flushed, iclass 7, count 2 2006.286.04:19:45.73#ibcon#about to write, iclass 7, count 2 2006.286.04:19:45.73#ibcon#wrote, iclass 7, count 2 2006.286.04:19:45.73#ibcon#about to read 3, iclass 7, count 2 2006.286.04:19:45.76#ibcon#read 3, iclass 7, count 2 2006.286.04:19:45.76#ibcon#about to read 4, iclass 7, count 2 2006.286.04:19:45.76#ibcon#read 4, iclass 7, count 2 2006.286.04:19:45.76#ibcon#about to read 5, iclass 7, count 2 2006.286.04:19:45.76#ibcon#read 5, iclass 7, count 2 2006.286.04:19:45.76#ibcon#about to read 6, iclass 7, count 2 2006.286.04:19:45.76#ibcon#read 6, iclass 7, count 2 2006.286.04:19:45.76#ibcon#end of sib2, iclass 7, count 2 2006.286.04:19:45.76#ibcon#*after write, iclass 7, count 2 2006.286.04:19:45.76#ibcon#*before return 0, iclass 7, count 2 2006.286.04:19:45.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:19:45.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:19:45.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.04:19:45.76#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:45.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:19:45.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:19:45.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:19:45.88#ibcon#enter wrdev, iclass 7, count 0 2006.286.04:19:45.88#ibcon#first serial, iclass 7, count 0 2006.286.04:19:45.88#ibcon#enter sib2, iclass 7, count 0 2006.286.04:19:45.88#ibcon#flushed, iclass 7, count 0 2006.286.04:19:45.88#ibcon#about to write, iclass 7, count 0 2006.286.04:19:45.88#ibcon#wrote, iclass 7, count 0 2006.286.04:19:45.88#ibcon#about to read 3, iclass 7, count 0 2006.286.04:19:45.90#ibcon#read 3, iclass 7, count 0 2006.286.04:19:45.90#ibcon#about to read 4, iclass 7, count 0 2006.286.04:19:45.90#ibcon#read 4, iclass 7, count 0 2006.286.04:19:45.90#ibcon#about to read 5, iclass 7, count 0 2006.286.04:19:45.90#ibcon#read 5, iclass 7, count 0 2006.286.04:19:45.90#ibcon#about to read 6, iclass 7, count 0 2006.286.04:19:45.90#ibcon#read 6, iclass 7, count 0 2006.286.04:19:45.90#ibcon#end of sib2, iclass 7, count 0 2006.286.04:19:45.90#ibcon#*mode == 0, iclass 7, count 0 2006.286.04:19:45.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.04:19:45.90#ibcon#[27=USB\r\n] 2006.286.04:19:45.90#ibcon#*before write, iclass 7, count 0 2006.286.04:19:45.90#ibcon#enter sib2, iclass 7, count 0 2006.286.04:19:45.90#ibcon#flushed, iclass 7, count 0 2006.286.04:19:45.90#ibcon#about to write, iclass 7, count 0 2006.286.04:19:45.90#ibcon#wrote, iclass 7, count 0 2006.286.04:19:45.90#ibcon#about to read 3, iclass 7, count 0 2006.286.04:19:45.93#ibcon#read 3, iclass 7, count 0 2006.286.04:19:45.93#ibcon#about to read 4, iclass 7, count 0 2006.286.04:19:45.93#ibcon#read 4, iclass 7, count 0 2006.286.04:19:45.93#ibcon#about to read 5, iclass 7, count 0 2006.286.04:19:45.93#ibcon#read 5, iclass 7, count 0 2006.286.04:19:45.93#ibcon#about to read 6, iclass 7, count 0 2006.286.04:19:45.93#ibcon#read 6, iclass 7, count 0 2006.286.04:19:45.93#ibcon#end of sib2, iclass 7, count 0 2006.286.04:19:45.93#ibcon#*after write, iclass 7, count 0 2006.286.04:19:45.93#ibcon#*before return 0, iclass 7, count 0 2006.286.04:19:45.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:19:45.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:19:45.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.04:19:45.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.04:19:45.93$vck44/vblo=2,634.99 2006.286.04:19:45.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.04:19:45.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.04:19:45.93#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:45.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:19:45.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:19:45.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:19:45.93#ibcon#enter wrdev, iclass 11, count 0 2006.286.04:19:45.93#ibcon#first serial, iclass 11, count 0 2006.286.04:19:45.93#ibcon#enter sib2, iclass 11, count 0 2006.286.04:19:45.93#ibcon#flushed, iclass 11, count 0 2006.286.04:19:45.93#ibcon#about to write, iclass 11, count 0 2006.286.04:19:45.93#ibcon#wrote, iclass 11, count 0 2006.286.04:19:45.93#ibcon#about to read 3, iclass 11, count 0 2006.286.04:19:45.95#ibcon#read 3, iclass 11, count 0 2006.286.04:19:45.95#ibcon#about to read 4, iclass 11, count 0 2006.286.04:19:45.95#ibcon#read 4, iclass 11, count 0 2006.286.04:19:45.95#ibcon#about to read 5, iclass 11, count 0 2006.286.04:19:45.95#ibcon#read 5, iclass 11, count 0 2006.286.04:19:45.95#ibcon#about to read 6, iclass 11, count 0 2006.286.04:19:45.95#ibcon#read 6, iclass 11, count 0 2006.286.04:19:45.95#ibcon#end of sib2, iclass 11, count 0 2006.286.04:19:45.95#ibcon#*mode == 0, iclass 11, count 0 2006.286.04:19:45.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.04:19:45.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:19:45.95#ibcon#*before write, iclass 11, count 0 2006.286.04:19:45.95#ibcon#enter sib2, iclass 11, count 0 2006.286.04:19:45.95#ibcon#flushed, iclass 11, count 0 2006.286.04:19:45.95#ibcon#about to write, iclass 11, count 0 2006.286.04:19:45.95#ibcon#wrote, iclass 11, count 0 2006.286.04:19:45.95#ibcon#about to read 3, iclass 11, count 0 2006.286.04:19:45.99#ibcon#read 3, iclass 11, count 0 2006.286.04:19:45.99#ibcon#about to read 4, iclass 11, count 0 2006.286.04:19:45.99#ibcon#read 4, iclass 11, count 0 2006.286.04:19:45.99#ibcon#about to read 5, iclass 11, count 0 2006.286.04:19:45.99#ibcon#read 5, iclass 11, count 0 2006.286.04:19:45.99#ibcon#about to read 6, iclass 11, count 0 2006.286.04:19:45.99#ibcon#read 6, iclass 11, count 0 2006.286.04:19:45.99#ibcon#end of sib2, iclass 11, count 0 2006.286.04:19:45.99#ibcon#*after write, iclass 11, count 0 2006.286.04:19:45.99#ibcon#*before return 0, iclass 11, count 0 2006.286.04:19:45.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:19:45.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:19:45.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.04:19:45.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.04:19:45.99$vck44/vb=2,5 2006.286.04:19:45.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.04:19:45.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.04:19:45.99#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:45.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:19:46.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:19:46.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:19:46.05#ibcon#enter wrdev, iclass 13, count 2 2006.286.04:19:46.05#ibcon#first serial, iclass 13, count 2 2006.286.04:19:46.05#ibcon#enter sib2, iclass 13, count 2 2006.286.04:19:46.05#ibcon#flushed, iclass 13, count 2 2006.286.04:19:46.05#ibcon#about to write, iclass 13, count 2 2006.286.04:19:46.05#ibcon#wrote, iclass 13, count 2 2006.286.04:19:46.05#ibcon#about to read 3, iclass 13, count 2 2006.286.04:19:46.07#ibcon#read 3, iclass 13, count 2 2006.286.04:19:46.07#ibcon#about to read 4, iclass 13, count 2 2006.286.04:19:46.07#ibcon#read 4, iclass 13, count 2 2006.286.04:19:46.07#ibcon#about to read 5, iclass 13, count 2 2006.286.04:19:46.07#ibcon#read 5, iclass 13, count 2 2006.286.04:19:46.07#ibcon#about to read 6, iclass 13, count 2 2006.286.04:19:46.07#ibcon#read 6, iclass 13, count 2 2006.286.04:19:46.07#ibcon#end of sib2, iclass 13, count 2 2006.286.04:19:46.07#ibcon#*mode == 0, iclass 13, count 2 2006.286.04:19:46.07#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.04:19:46.07#ibcon#[27=AT02-05\r\n] 2006.286.04:19:46.07#ibcon#*before write, iclass 13, count 2 2006.286.04:19:46.07#ibcon#enter sib2, iclass 13, count 2 2006.286.04:19:46.07#ibcon#flushed, iclass 13, count 2 2006.286.04:19:46.07#ibcon#about to write, iclass 13, count 2 2006.286.04:19:46.07#ibcon#wrote, iclass 13, count 2 2006.286.04:19:46.07#ibcon#about to read 3, iclass 13, count 2 2006.286.04:19:46.10#ibcon#read 3, iclass 13, count 2 2006.286.04:19:46.10#ibcon#about to read 4, iclass 13, count 2 2006.286.04:19:46.10#ibcon#read 4, iclass 13, count 2 2006.286.04:19:46.10#ibcon#about to read 5, iclass 13, count 2 2006.286.04:19:46.10#ibcon#read 5, iclass 13, count 2 2006.286.04:19:46.10#ibcon#about to read 6, iclass 13, count 2 2006.286.04:19:46.10#ibcon#read 6, iclass 13, count 2 2006.286.04:19:46.10#ibcon#end of sib2, iclass 13, count 2 2006.286.04:19:46.10#ibcon#*after write, iclass 13, count 2 2006.286.04:19:46.10#ibcon#*before return 0, iclass 13, count 2 2006.286.04:19:46.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:19:46.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:19:46.10#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.04:19:46.10#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:46.10#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:19:46.22#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:19:46.22#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:19:46.22#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:19:46.22#ibcon#first serial, iclass 13, count 0 2006.286.04:19:46.22#ibcon#enter sib2, iclass 13, count 0 2006.286.04:19:46.22#ibcon#flushed, iclass 13, count 0 2006.286.04:19:46.22#ibcon#about to write, iclass 13, count 0 2006.286.04:19:46.22#ibcon#wrote, iclass 13, count 0 2006.286.04:19:46.22#ibcon#about to read 3, iclass 13, count 0 2006.286.04:19:46.24#ibcon#read 3, iclass 13, count 0 2006.286.04:19:46.24#ibcon#about to read 4, iclass 13, count 0 2006.286.04:19:46.24#ibcon#read 4, iclass 13, count 0 2006.286.04:19:46.24#ibcon#about to read 5, iclass 13, count 0 2006.286.04:19:46.24#ibcon#read 5, iclass 13, count 0 2006.286.04:19:46.24#ibcon#about to read 6, iclass 13, count 0 2006.286.04:19:46.24#ibcon#read 6, iclass 13, count 0 2006.286.04:19:46.24#ibcon#end of sib2, iclass 13, count 0 2006.286.04:19:46.24#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:19:46.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:19:46.24#ibcon#[27=USB\r\n] 2006.286.04:19:46.24#ibcon#*before write, iclass 13, count 0 2006.286.04:19:46.24#ibcon#enter sib2, iclass 13, count 0 2006.286.04:19:46.24#ibcon#flushed, iclass 13, count 0 2006.286.04:19:46.24#ibcon#about to write, iclass 13, count 0 2006.286.04:19:46.24#ibcon#wrote, iclass 13, count 0 2006.286.04:19:46.24#ibcon#about to read 3, iclass 13, count 0 2006.286.04:19:46.27#ibcon#read 3, iclass 13, count 0 2006.286.04:19:46.27#ibcon#about to read 4, iclass 13, count 0 2006.286.04:19:46.27#ibcon#read 4, iclass 13, count 0 2006.286.04:19:46.27#ibcon#about to read 5, iclass 13, count 0 2006.286.04:19:46.27#ibcon#read 5, iclass 13, count 0 2006.286.04:19:46.27#ibcon#about to read 6, iclass 13, count 0 2006.286.04:19:46.27#ibcon#read 6, iclass 13, count 0 2006.286.04:19:46.27#ibcon#end of sib2, iclass 13, count 0 2006.286.04:19:46.27#ibcon#*after write, iclass 13, count 0 2006.286.04:19:46.27#ibcon#*before return 0, iclass 13, count 0 2006.286.04:19:46.27#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:19:46.27#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:19:46.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:19:46.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:19:46.27$vck44/vblo=3,649.99 2006.286.04:19:46.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.04:19:46.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.04:19:46.27#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:46.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:19:46.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:19:46.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:19:46.27#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:19:46.27#ibcon#first serial, iclass 15, count 0 2006.286.04:19:46.27#ibcon#enter sib2, iclass 15, count 0 2006.286.04:19:46.27#ibcon#flushed, iclass 15, count 0 2006.286.04:19:46.27#ibcon#about to write, iclass 15, count 0 2006.286.04:19:46.27#ibcon#wrote, iclass 15, count 0 2006.286.04:19:46.27#ibcon#about to read 3, iclass 15, count 0 2006.286.04:19:46.29#ibcon#read 3, iclass 15, count 0 2006.286.04:19:46.29#ibcon#about to read 4, iclass 15, count 0 2006.286.04:19:46.29#ibcon#read 4, iclass 15, count 0 2006.286.04:19:46.29#ibcon#about to read 5, iclass 15, count 0 2006.286.04:19:46.29#ibcon#read 5, iclass 15, count 0 2006.286.04:19:46.29#ibcon#about to read 6, iclass 15, count 0 2006.286.04:19:46.29#ibcon#read 6, iclass 15, count 0 2006.286.04:19:46.29#ibcon#end of sib2, iclass 15, count 0 2006.286.04:19:46.29#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:19:46.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:19:46.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:19:46.29#ibcon#*before write, iclass 15, count 0 2006.286.04:19:46.29#ibcon#enter sib2, iclass 15, count 0 2006.286.04:19:46.29#ibcon#flushed, iclass 15, count 0 2006.286.04:19:46.29#ibcon#about to write, iclass 15, count 0 2006.286.04:19:46.29#ibcon#wrote, iclass 15, count 0 2006.286.04:19:46.29#ibcon#about to read 3, iclass 15, count 0 2006.286.04:19:46.33#ibcon#read 3, iclass 15, count 0 2006.286.04:19:46.33#ibcon#about to read 4, iclass 15, count 0 2006.286.04:19:46.33#ibcon#read 4, iclass 15, count 0 2006.286.04:19:46.33#ibcon#about to read 5, iclass 15, count 0 2006.286.04:19:46.33#ibcon#read 5, iclass 15, count 0 2006.286.04:19:46.33#ibcon#about to read 6, iclass 15, count 0 2006.286.04:19:46.33#ibcon#read 6, iclass 15, count 0 2006.286.04:19:46.33#ibcon#end of sib2, iclass 15, count 0 2006.286.04:19:46.33#ibcon#*after write, iclass 15, count 0 2006.286.04:19:46.33#ibcon#*before return 0, iclass 15, count 0 2006.286.04:19:46.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:19:46.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:19:46.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:19:46.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:19:46.33$vck44/vb=3,4 2006.286.04:19:46.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.04:19:46.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.04:19:46.33#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:46.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:19:46.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:19:46.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:19:46.39#ibcon#enter wrdev, iclass 17, count 2 2006.286.04:19:46.39#ibcon#first serial, iclass 17, count 2 2006.286.04:19:46.39#ibcon#enter sib2, iclass 17, count 2 2006.286.04:19:46.39#ibcon#flushed, iclass 17, count 2 2006.286.04:19:46.39#ibcon#about to write, iclass 17, count 2 2006.286.04:19:46.39#ibcon#wrote, iclass 17, count 2 2006.286.04:19:46.39#ibcon#about to read 3, iclass 17, count 2 2006.286.04:19:46.41#ibcon#read 3, iclass 17, count 2 2006.286.04:19:46.41#ibcon#about to read 4, iclass 17, count 2 2006.286.04:19:46.41#ibcon#read 4, iclass 17, count 2 2006.286.04:19:46.41#ibcon#about to read 5, iclass 17, count 2 2006.286.04:19:46.41#ibcon#read 5, iclass 17, count 2 2006.286.04:19:46.41#ibcon#about to read 6, iclass 17, count 2 2006.286.04:19:46.41#ibcon#read 6, iclass 17, count 2 2006.286.04:19:46.41#ibcon#end of sib2, iclass 17, count 2 2006.286.04:19:46.41#ibcon#*mode == 0, iclass 17, count 2 2006.286.04:19:46.41#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.04:19:46.41#ibcon#[27=AT03-04\r\n] 2006.286.04:19:46.41#ibcon#*before write, iclass 17, count 2 2006.286.04:19:46.41#ibcon#enter sib2, iclass 17, count 2 2006.286.04:19:46.41#ibcon#flushed, iclass 17, count 2 2006.286.04:19:46.41#ibcon#about to write, iclass 17, count 2 2006.286.04:19:46.41#ibcon#wrote, iclass 17, count 2 2006.286.04:19:46.41#ibcon#about to read 3, iclass 17, count 2 2006.286.04:19:46.44#ibcon#read 3, iclass 17, count 2 2006.286.04:19:46.44#ibcon#about to read 4, iclass 17, count 2 2006.286.04:19:46.44#ibcon#read 4, iclass 17, count 2 2006.286.04:19:46.44#ibcon#about to read 5, iclass 17, count 2 2006.286.04:19:46.44#ibcon#read 5, iclass 17, count 2 2006.286.04:19:46.44#ibcon#about to read 6, iclass 17, count 2 2006.286.04:19:46.44#ibcon#read 6, iclass 17, count 2 2006.286.04:19:46.44#ibcon#end of sib2, iclass 17, count 2 2006.286.04:19:46.44#ibcon#*after write, iclass 17, count 2 2006.286.04:19:46.44#ibcon#*before return 0, iclass 17, count 2 2006.286.04:19:46.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:19:46.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:19:46.44#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.04:19:46.44#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:46.44#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:19:46.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:19:46.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:19:46.56#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:19:46.56#ibcon#first serial, iclass 17, count 0 2006.286.04:19:46.56#ibcon#enter sib2, iclass 17, count 0 2006.286.04:19:46.56#ibcon#flushed, iclass 17, count 0 2006.286.04:19:46.56#ibcon#about to write, iclass 17, count 0 2006.286.04:19:46.56#ibcon#wrote, iclass 17, count 0 2006.286.04:19:46.56#ibcon#about to read 3, iclass 17, count 0 2006.286.04:19:46.58#ibcon#read 3, iclass 17, count 0 2006.286.04:19:46.58#ibcon#about to read 4, iclass 17, count 0 2006.286.04:19:46.58#ibcon#read 4, iclass 17, count 0 2006.286.04:19:46.58#ibcon#about to read 5, iclass 17, count 0 2006.286.04:19:46.58#ibcon#read 5, iclass 17, count 0 2006.286.04:19:46.58#ibcon#about to read 6, iclass 17, count 0 2006.286.04:19:46.58#ibcon#read 6, iclass 17, count 0 2006.286.04:19:46.58#ibcon#end of sib2, iclass 17, count 0 2006.286.04:19:46.58#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:19:46.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:19:46.58#ibcon#[27=USB\r\n] 2006.286.04:19:46.58#ibcon#*before write, iclass 17, count 0 2006.286.04:19:46.58#ibcon#enter sib2, iclass 17, count 0 2006.286.04:19:46.58#ibcon#flushed, iclass 17, count 0 2006.286.04:19:46.58#ibcon#about to write, iclass 17, count 0 2006.286.04:19:46.58#ibcon#wrote, iclass 17, count 0 2006.286.04:19:46.58#ibcon#about to read 3, iclass 17, count 0 2006.286.04:19:46.61#ibcon#read 3, iclass 17, count 0 2006.286.04:19:46.61#ibcon#about to read 4, iclass 17, count 0 2006.286.04:19:46.61#ibcon#read 4, iclass 17, count 0 2006.286.04:19:46.61#ibcon#about to read 5, iclass 17, count 0 2006.286.04:19:46.61#ibcon#read 5, iclass 17, count 0 2006.286.04:19:46.61#ibcon#about to read 6, iclass 17, count 0 2006.286.04:19:46.61#ibcon#read 6, iclass 17, count 0 2006.286.04:19:46.61#ibcon#end of sib2, iclass 17, count 0 2006.286.04:19:46.61#ibcon#*after write, iclass 17, count 0 2006.286.04:19:46.61#ibcon#*before return 0, iclass 17, count 0 2006.286.04:19:46.61#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:19:46.61#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:19:46.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:19:46.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:19:46.61$vck44/vblo=4,679.99 2006.286.04:19:46.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.04:19:46.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.04:19:46.61#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:46.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:19:46.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:19:46.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:19:46.61#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:19:46.61#ibcon#first serial, iclass 19, count 0 2006.286.04:19:46.61#ibcon#enter sib2, iclass 19, count 0 2006.286.04:19:46.61#ibcon#flushed, iclass 19, count 0 2006.286.04:19:46.61#ibcon#about to write, iclass 19, count 0 2006.286.04:19:46.61#ibcon#wrote, iclass 19, count 0 2006.286.04:19:46.61#ibcon#about to read 3, iclass 19, count 0 2006.286.04:19:46.63#ibcon#read 3, iclass 19, count 0 2006.286.04:19:46.71#ibcon#about to read 4, iclass 19, count 0 2006.286.04:19:46.71#ibcon#read 4, iclass 19, count 0 2006.286.04:19:46.71#ibcon#about to read 5, iclass 19, count 0 2006.286.04:19:46.71#ibcon#read 5, iclass 19, count 0 2006.286.04:19:46.71#ibcon#about to read 6, iclass 19, count 0 2006.286.04:19:46.71#ibcon#read 6, iclass 19, count 0 2006.286.04:19:46.71#ibcon#end of sib2, iclass 19, count 0 2006.286.04:19:46.71#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:19:46.71#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:19:46.71#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:19:46.71#ibcon#*before write, iclass 19, count 0 2006.286.04:19:46.71#ibcon#enter sib2, iclass 19, count 0 2006.286.04:19:46.71#ibcon#flushed, iclass 19, count 0 2006.286.04:19:46.71#ibcon#about to write, iclass 19, count 0 2006.286.04:19:46.71#ibcon#wrote, iclass 19, count 0 2006.286.04:19:46.71#ibcon#about to read 3, iclass 19, count 0 2006.286.04:19:46.75#ibcon#read 3, iclass 19, count 0 2006.286.04:19:46.75#ibcon#about to read 4, iclass 19, count 0 2006.286.04:19:46.75#ibcon#read 4, iclass 19, count 0 2006.286.04:19:46.75#ibcon#about to read 5, iclass 19, count 0 2006.286.04:19:46.75#ibcon#read 5, iclass 19, count 0 2006.286.04:19:46.75#ibcon#about to read 6, iclass 19, count 0 2006.286.04:19:46.75#ibcon#read 6, iclass 19, count 0 2006.286.04:19:46.75#ibcon#end of sib2, iclass 19, count 0 2006.286.04:19:46.75#ibcon#*after write, iclass 19, count 0 2006.286.04:19:46.75#ibcon#*before return 0, iclass 19, count 0 2006.286.04:19:46.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:19:46.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:19:46.75#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:19:46.75#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:19:46.75$vck44/vb=4,5 2006.286.04:19:46.75#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.04:19:46.75#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.04:19:46.75#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:46.75#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:19:46.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:19:46.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:19:46.75#ibcon#enter wrdev, iclass 21, count 2 2006.286.04:19:46.75#ibcon#first serial, iclass 21, count 2 2006.286.04:19:46.75#ibcon#enter sib2, iclass 21, count 2 2006.286.04:19:46.75#ibcon#flushed, iclass 21, count 2 2006.286.04:19:46.75#ibcon#about to write, iclass 21, count 2 2006.286.04:19:46.75#ibcon#wrote, iclass 21, count 2 2006.286.04:19:46.75#ibcon#about to read 3, iclass 21, count 2 2006.286.04:19:46.77#ibcon#read 3, iclass 21, count 2 2006.286.04:19:46.77#ibcon#about to read 4, iclass 21, count 2 2006.286.04:19:46.77#ibcon#read 4, iclass 21, count 2 2006.286.04:19:46.77#ibcon#about to read 5, iclass 21, count 2 2006.286.04:19:46.77#ibcon#read 5, iclass 21, count 2 2006.286.04:19:46.77#ibcon#about to read 6, iclass 21, count 2 2006.286.04:19:46.77#ibcon#read 6, iclass 21, count 2 2006.286.04:19:46.77#ibcon#end of sib2, iclass 21, count 2 2006.286.04:19:46.77#ibcon#*mode == 0, iclass 21, count 2 2006.286.04:19:46.77#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.04:19:46.77#ibcon#[27=AT04-05\r\n] 2006.286.04:19:46.77#ibcon#*before write, iclass 21, count 2 2006.286.04:19:46.77#ibcon#enter sib2, iclass 21, count 2 2006.286.04:19:46.77#ibcon#flushed, iclass 21, count 2 2006.286.04:19:46.77#ibcon#about to write, iclass 21, count 2 2006.286.04:19:46.77#ibcon#wrote, iclass 21, count 2 2006.286.04:19:46.77#ibcon#about to read 3, iclass 21, count 2 2006.286.04:19:46.80#ibcon#read 3, iclass 21, count 2 2006.286.04:19:46.80#ibcon#about to read 4, iclass 21, count 2 2006.286.04:19:46.80#ibcon#read 4, iclass 21, count 2 2006.286.04:19:46.80#ibcon#about to read 5, iclass 21, count 2 2006.286.04:19:46.80#ibcon#read 5, iclass 21, count 2 2006.286.04:19:46.80#ibcon#about to read 6, iclass 21, count 2 2006.286.04:19:46.80#ibcon#read 6, iclass 21, count 2 2006.286.04:19:46.80#ibcon#end of sib2, iclass 21, count 2 2006.286.04:19:46.80#ibcon#*after write, iclass 21, count 2 2006.286.04:19:46.80#ibcon#*before return 0, iclass 21, count 2 2006.286.04:19:46.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:19:46.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:19:46.80#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.04:19:46.80#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:46.80#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:19:46.92#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:19:46.92#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:19:46.92#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:19:46.92#ibcon#first serial, iclass 21, count 0 2006.286.04:19:46.92#ibcon#enter sib2, iclass 21, count 0 2006.286.04:19:46.92#ibcon#flushed, iclass 21, count 0 2006.286.04:19:46.92#ibcon#about to write, iclass 21, count 0 2006.286.04:19:46.92#ibcon#wrote, iclass 21, count 0 2006.286.04:19:46.92#ibcon#about to read 3, iclass 21, count 0 2006.286.04:19:46.94#ibcon#read 3, iclass 21, count 0 2006.286.04:19:46.94#ibcon#about to read 4, iclass 21, count 0 2006.286.04:19:46.94#ibcon#read 4, iclass 21, count 0 2006.286.04:19:46.94#ibcon#about to read 5, iclass 21, count 0 2006.286.04:19:46.94#ibcon#read 5, iclass 21, count 0 2006.286.04:19:46.94#ibcon#about to read 6, iclass 21, count 0 2006.286.04:19:46.94#ibcon#read 6, iclass 21, count 0 2006.286.04:19:46.94#ibcon#end of sib2, iclass 21, count 0 2006.286.04:19:46.94#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:19:46.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:19:46.94#ibcon#[27=USB\r\n] 2006.286.04:19:46.94#ibcon#*before write, iclass 21, count 0 2006.286.04:19:46.94#ibcon#enter sib2, iclass 21, count 0 2006.286.04:19:46.94#ibcon#flushed, iclass 21, count 0 2006.286.04:19:46.94#ibcon#about to write, iclass 21, count 0 2006.286.04:19:46.94#ibcon#wrote, iclass 21, count 0 2006.286.04:19:46.94#ibcon#about to read 3, iclass 21, count 0 2006.286.04:19:46.97#ibcon#read 3, iclass 21, count 0 2006.286.04:19:46.97#ibcon#about to read 4, iclass 21, count 0 2006.286.04:19:46.97#ibcon#read 4, iclass 21, count 0 2006.286.04:19:46.97#ibcon#about to read 5, iclass 21, count 0 2006.286.04:19:46.97#ibcon#read 5, iclass 21, count 0 2006.286.04:19:46.97#ibcon#about to read 6, iclass 21, count 0 2006.286.04:19:46.97#ibcon#read 6, iclass 21, count 0 2006.286.04:19:46.97#ibcon#end of sib2, iclass 21, count 0 2006.286.04:19:46.97#ibcon#*after write, iclass 21, count 0 2006.286.04:19:46.97#ibcon#*before return 0, iclass 21, count 0 2006.286.04:19:46.97#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:19:46.97#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:19:46.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:19:46.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:19:46.97$vck44/vblo=5,709.99 2006.286.04:19:46.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.04:19:46.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.04:19:46.97#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:46.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:19:46.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:19:46.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:19:46.97#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:19:46.97#ibcon#first serial, iclass 23, count 0 2006.286.04:19:46.97#ibcon#enter sib2, iclass 23, count 0 2006.286.04:19:46.97#ibcon#flushed, iclass 23, count 0 2006.286.04:19:46.97#ibcon#about to write, iclass 23, count 0 2006.286.04:19:46.97#ibcon#wrote, iclass 23, count 0 2006.286.04:19:46.97#ibcon#about to read 3, iclass 23, count 0 2006.286.04:19:46.99#ibcon#read 3, iclass 23, count 0 2006.286.04:19:46.99#ibcon#about to read 4, iclass 23, count 0 2006.286.04:19:46.99#ibcon#read 4, iclass 23, count 0 2006.286.04:19:46.99#ibcon#about to read 5, iclass 23, count 0 2006.286.04:19:46.99#ibcon#read 5, iclass 23, count 0 2006.286.04:19:46.99#ibcon#about to read 6, iclass 23, count 0 2006.286.04:19:46.99#ibcon#read 6, iclass 23, count 0 2006.286.04:19:46.99#ibcon#end of sib2, iclass 23, count 0 2006.286.04:19:46.99#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:19:46.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:19:46.99#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:19:46.99#ibcon#*before write, iclass 23, count 0 2006.286.04:19:46.99#ibcon#enter sib2, iclass 23, count 0 2006.286.04:19:46.99#ibcon#flushed, iclass 23, count 0 2006.286.04:19:46.99#ibcon#about to write, iclass 23, count 0 2006.286.04:19:46.99#ibcon#wrote, iclass 23, count 0 2006.286.04:19:46.99#ibcon#about to read 3, iclass 23, count 0 2006.286.04:19:47.03#ibcon#read 3, iclass 23, count 0 2006.286.04:19:47.03#ibcon#about to read 4, iclass 23, count 0 2006.286.04:19:47.03#ibcon#read 4, iclass 23, count 0 2006.286.04:19:47.03#ibcon#about to read 5, iclass 23, count 0 2006.286.04:19:47.03#ibcon#read 5, iclass 23, count 0 2006.286.04:19:47.03#ibcon#about to read 6, iclass 23, count 0 2006.286.04:19:47.03#ibcon#read 6, iclass 23, count 0 2006.286.04:19:47.03#ibcon#end of sib2, iclass 23, count 0 2006.286.04:19:47.03#ibcon#*after write, iclass 23, count 0 2006.286.04:19:47.03#ibcon#*before return 0, iclass 23, count 0 2006.286.04:19:47.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:19:47.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:19:47.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:19:47.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:19:47.03$vck44/vb=5,4 2006.286.04:19:47.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.04:19:47.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.04:19:47.03#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:47.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:19:47.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:19:47.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:19:47.09#ibcon#enter wrdev, iclass 25, count 2 2006.286.04:19:47.09#ibcon#first serial, iclass 25, count 2 2006.286.04:19:47.09#ibcon#enter sib2, iclass 25, count 2 2006.286.04:19:47.09#ibcon#flushed, iclass 25, count 2 2006.286.04:19:47.09#ibcon#about to write, iclass 25, count 2 2006.286.04:19:47.09#ibcon#wrote, iclass 25, count 2 2006.286.04:19:47.09#ibcon#about to read 3, iclass 25, count 2 2006.286.04:19:47.11#ibcon#read 3, iclass 25, count 2 2006.286.04:19:47.11#ibcon#about to read 4, iclass 25, count 2 2006.286.04:19:47.11#ibcon#read 4, iclass 25, count 2 2006.286.04:19:47.11#ibcon#about to read 5, iclass 25, count 2 2006.286.04:19:47.11#ibcon#read 5, iclass 25, count 2 2006.286.04:19:47.11#ibcon#about to read 6, iclass 25, count 2 2006.286.04:19:47.11#ibcon#read 6, iclass 25, count 2 2006.286.04:19:47.11#ibcon#end of sib2, iclass 25, count 2 2006.286.04:19:47.11#ibcon#*mode == 0, iclass 25, count 2 2006.286.04:19:47.11#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.04:19:47.11#ibcon#[27=AT05-04\r\n] 2006.286.04:19:47.11#ibcon#*before write, iclass 25, count 2 2006.286.04:19:47.11#ibcon#enter sib2, iclass 25, count 2 2006.286.04:19:47.11#ibcon#flushed, iclass 25, count 2 2006.286.04:19:47.11#ibcon#about to write, iclass 25, count 2 2006.286.04:19:47.11#ibcon#wrote, iclass 25, count 2 2006.286.04:19:47.11#ibcon#about to read 3, iclass 25, count 2 2006.286.04:19:47.14#ibcon#read 3, iclass 25, count 2 2006.286.04:19:47.14#ibcon#about to read 4, iclass 25, count 2 2006.286.04:19:47.14#ibcon#read 4, iclass 25, count 2 2006.286.04:19:47.14#ibcon#about to read 5, iclass 25, count 2 2006.286.04:19:47.14#ibcon#read 5, iclass 25, count 2 2006.286.04:19:47.14#ibcon#about to read 6, iclass 25, count 2 2006.286.04:19:47.14#ibcon#read 6, iclass 25, count 2 2006.286.04:19:47.14#ibcon#end of sib2, iclass 25, count 2 2006.286.04:19:47.14#ibcon#*after write, iclass 25, count 2 2006.286.04:19:47.14#ibcon#*before return 0, iclass 25, count 2 2006.286.04:19:47.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:19:47.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:19:47.14#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.04:19:47.14#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:47.14#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:19:47.26#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:19:47.26#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:19:47.26#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:19:47.26#ibcon#first serial, iclass 25, count 0 2006.286.04:19:47.26#ibcon#enter sib2, iclass 25, count 0 2006.286.04:19:47.26#ibcon#flushed, iclass 25, count 0 2006.286.04:19:47.26#ibcon#about to write, iclass 25, count 0 2006.286.04:19:47.26#ibcon#wrote, iclass 25, count 0 2006.286.04:19:47.26#ibcon#about to read 3, iclass 25, count 0 2006.286.04:19:47.28#ibcon#read 3, iclass 25, count 0 2006.286.04:19:47.28#ibcon#about to read 4, iclass 25, count 0 2006.286.04:19:47.28#ibcon#read 4, iclass 25, count 0 2006.286.04:19:47.28#ibcon#about to read 5, iclass 25, count 0 2006.286.04:19:47.28#ibcon#read 5, iclass 25, count 0 2006.286.04:19:47.28#ibcon#about to read 6, iclass 25, count 0 2006.286.04:19:47.28#ibcon#read 6, iclass 25, count 0 2006.286.04:19:47.28#ibcon#end of sib2, iclass 25, count 0 2006.286.04:19:47.28#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:19:47.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:19:47.28#ibcon#[27=USB\r\n] 2006.286.04:19:47.28#ibcon#*before write, iclass 25, count 0 2006.286.04:19:47.28#ibcon#enter sib2, iclass 25, count 0 2006.286.04:19:47.28#ibcon#flushed, iclass 25, count 0 2006.286.04:19:47.28#ibcon#about to write, iclass 25, count 0 2006.286.04:19:47.28#ibcon#wrote, iclass 25, count 0 2006.286.04:19:47.28#ibcon#about to read 3, iclass 25, count 0 2006.286.04:19:47.31#ibcon#read 3, iclass 25, count 0 2006.286.04:19:47.31#ibcon#about to read 4, iclass 25, count 0 2006.286.04:19:47.31#ibcon#read 4, iclass 25, count 0 2006.286.04:19:47.31#ibcon#about to read 5, iclass 25, count 0 2006.286.04:19:47.31#ibcon#read 5, iclass 25, count 0 2006.286.04:19:47.31#ibcon#about to read 6, iclass 25, count 0 2006.286.04:19:47.31#ibcon#read 6, iclass 25, count 0 2006.286.04:19:47.31#ibcon#end of sib2, iclass 25, count 0 2006.286.04:19:47.31#ibcon#*after write, iclass 25, count 0 2006.286.04:19:47.31#ibcon#*before return 0, iclass 25, count 0 2006.286.04:19:47.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:19:47.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:19:47.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:19:47.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:19:47.31$vck44/vblo=6,719.99 2006.286.04:19:47.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.04:19:47.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.04:19:47.31#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:47.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:19:47.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:19:47.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:19:47.31#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:19:47.31#ibcon#first serial, iclass 27, count 0 2006.286.04:19:47.31#ibcon#enter sib2, iclass 27, count 0 2006.286.04:19:47.31#ibcon#flushed, iclass 27, count 0 2006.286.04:19:47.31#ibcon#about to write, iclass 27, count 0 2006.286.04:19:47.31#ibcon#wrote, iclass 27, count 0 2006.286.04:19:47.31#ibcon#about to read 3, iclass 27, count 0 2006.286.04:19:47.33#ibcon#read 3, iclass 27, count 0 2006.286.04:19:47.33#ibcon#about to read 4, iclass 27, count 0 2006.286.04:19:47.33#ibcon#read 4, iclass 27, count 0 2006.286.04:19:47.33#ibcon#about to read 5, iclass 27, count 0 2006.286.04:19:47.33#ibcon#read 5, iclass 27, count 0 2006.286.04:19:47.33#ibcon#about to read 6, iclass 27, count 0 2006.286.04:19:47.33#ibcon#read 6, iclass 27, count 0 2006.286.04:19:47.33#ibcon#end of sib2, iclass 27, count 0 2006.286.04:19:47.33#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:19:47.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:19:47.33#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:19:47.33#ibcon#*before write, iclass 27, count 0 2006.286.04:19:47.33#ibcon#enter sib2, iclass 27, count 0 2006.286.04:19:47.33#ibcon#flushed, iclass 27, count 0 2006.286.04:19:47.33#ibcon#about to write, iclass 27, count 0 2006.286.04:19:47.33#ibcon#wrote, iclass 27, count 0 2006.286.04:19:47.33#ibcon#about to read 3, iclass 27, count 0 2006.286.04:19:47.37#ibcon#read 3, iclass 27, count 0 2006.286.04:19:47.37#ibcon#about to read 4, iclass 27, count 0 2006.286.04:19:47.37#ibcon#read 4, iclass 27, count 0 2006.286.04:19:47.37#ibcon#about to read 5, iclass 27, count 0 2006.286.04:19:47.37#ibcon#read 5, iclass 27, count 0 2006.286.04:19:47.37#ibcon#about to read 6, iclass 27, count 0 2006.286.04:19:47.37#ibcon#read 6, iclass 27, count 0 2006.286.04:19:47.37#ibcon#end of sib2, iclass 27, count 0 2006.286.04:19:47.37#ibcon#*after write, iclass 27, count 0 2006.286.04:19:47.37#ibcon#*before return 0, iclass 27, count 0 2006.286.04:19:47.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:19:47.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:19:47.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:19:47.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:19:47.37$vck44/vb=6,3 2006.286.04:19:47.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.04:19:47.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.04:19:47.37#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:47.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:19:47.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:19:47.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:19:47.43#ibcon#enter wrdev, iclass 29, count 2 2006.286.04:19:47.43#ibcon#first serial, iclass 29, count 2 2006.286.04:19:47.43#ibcon#enter sib2, iclass 29, count 2 2006.286.04:19:47.43#ibcon#flushed, iclass 29, count 2 2006.286.04:19:47.43#ibcon#about to write, iclass 29, count 2 2006.286.04:19:47.43#ibcon#wrote, iclass 29, count 2 2006.286.04:19:47.43#ibcon#about to read 3, iclass 29, count 2 2006.286.04:19:47.45#ibcon#read 3, iclass 29, count 2 2006.286.04:19:47.45#ibcon#about to read 4, iclass 29, count 2 2006.286.04:19:47.45#ibcon#read 4, iclass 29, count 2 2006.286.04:19:47.45#ibcon#about to read 5, iclass 29, count 2 2006.286.04:19:47.45#ibcon#read 5, iclass 29, count 2 2006.286.04:19:47.45#ibcon#about to read 6, iclass 29, count 2 2006.286.04:19:47.45#ibcon#read 6, iclass 29, count 2 2006.286.04:19:47.45#ibcon#end of sib2, iclass 29, count 2 2006.286.04:19:47.45#ibcon#*mode == 0, iclass 29, count 2 2006.286.04:19:47.45#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.04:19:47.45#ibcon#[27=AT06-03\r\n] 2006.286.04:19:47.45#ibcon#*before write, iclass 29, count 2 2006.286.04:19:47.45#ibcon#enter sib2, iclass 29, count 2 2006.286.04:19:47.45#ibcon#flushed, iclass 29, count 2 2006.286.04:19:47.45#ibcon#about to write, iclass 29, count 2 2006.286.04:19:47.45#ibcon#wrote, iclass 29, count 2 2006.286.04:19:47.45#ibcon#about to read 3, iclass 29, count 2 2006.286.04:19:47.48#ibcon#read 3, iclass 29, count 2 2006.286.04:19:47.48#ibcon#about to read 4, iclass 29, count 2 2006.286.04:19:47.48#ibcon#read 4, iclass 29, count 2 2006.286.04:19:47.48#ibcon#about to read 5, iclass 29, count 2 2006.286.04:19:47.48#ibcon#read 5, iclass 29, count 2 2006.286.04:19:47.48#ibcon#about to read 6, iclass 29, count 2 2006.286.04:19:47.48#ibcon#read 6, iclass 29, count 2 2006.286.04:19:47.48#ibcon#end of sib2, iclass 29, count 2 2006.286.04:19:47.48#ibcon#*after write, iclass 29, count 2 2006.286.04:19:47.48#ibcon#*before return 0, iclass 29, count 2 2006.286.04:19:47.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:19:47.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:19:47.48#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.04:19:47.48#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:47.48#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:19:47.60#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:19:47.60#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:19:47.60#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:19:47.60#ibcon#first serial, iclass 29, count 0 2006.286.04:19:47.60#ibcon#enter sib2, iclass 29, count 0 2006.286.04:19:47.60#ibcon#flushed, iclass 29, count 0 2006.286.04:19:47.60#ibcon#about to write, iclass 29, count 0 2006.286.04:19:47.60#ibcon#wrote, iclass 29, count 0 2006.286.04:19:47.60#ibcon#about to read 3, iclass 29, count 0 2006.286.04:19:47.62#ibcon#read 3, iclass 29, count 0 2006.286.04:19:47.62#ibcon#about to read 4, iclass 29, count 0 2006.286.04:19:47.62#ibcon#read 4, iclass 29, count 0 2006.286.04:19:47.62#ibcon#about to read 5, iclass 29, count 0 2006.286.04:19:47.62#ibcon#read 5, iclass 29, count 0 2006.286.04:19:47.62#ibcon#about to read 6, iclass 29, count 0 2006.286.04:19:47.62#ibcon#read 6, iclass 29, count 0 2006.286.04:19:47.62#ibcon#end of sib2, iclass 29, count 0 2006.286.04:19:47.62#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:19:47.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:19:47.62#ibcon#[27=USB\r\n] 2006.286.04:19:47.62#ibcon#*before write, iclass 29, count 0 2006.286.04:19:47.62#ibcon#enter sib2, iclass 29, count 0 2006.286.04:19:47.62#ibcon#flushed, iclass 29, count 0 2006.286.04:19:47.62#ibcon#about to write, iclass 29, count 0 2006.286.04:19:47.62#ibcon#wrote, iclass 29, count 0 2006.286.04:19:47.62#ibcon#about to read 3, iclass 29, count 0 2006.286.04:19:47.65#ibcon#read 3, iclass 29, count 0 2006.286.04:19:47.65#ibcon#about to read 4, iclass 29, count 0 2006.286.04:19:47.65#ibcon#read 4, iclass 29, count 0 2006.286.04:19:47.65#ibcon#about to read 5, iclass 29, count 0 2006.286.04:19:47.65#ibcon#read 5, iclass 29, count 0 2006.286.04:19:47.65#ibcon#about to read 6, iclass 29, count 0 2006.286.04:19:47.65#ibcon#read 6, iclass 29, count 0 2006.286.04:19:47.65#ibcon#end of sib2, iclass 29, count 0 2006.286.04:19:47.65#ibcon#*after write, iclass 29, count 0 2006.286.04:19:47.65#ibcon#*before return 0, iclass 29, count 0 2006.286.04:19:47.65#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:19:47.65#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:19:47.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:19:47.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:19:47.65$vck44/vblo=7,734.99 2006.286.04:19:47.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.04:19:47.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.04:19:47.65#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:47.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:19:47.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:19:47.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:19:47.65#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:19:47.65#ibcon#first serial, iclass 31, count 0 2006.286.04:19:47.65#ibcon#enter sib2, iclass 31, count 0 2006.286.04:19:47.65#ibcon#flushed, iclass 31, count 0 2006.286.04:19:47.65#ibcon#about to write, iclass 31, count 0 2006.286.04:19:47.65#ibcon#wrote, iclass 31, count 0 2006.286.04:19:47.65#ibcon#about to read 3, iclass 31, count 0 2006.286.04:19:47.67#ibcon#read 3, iclass 31, count 0 2006.286.04:19:47.85#ibcon#about to read 4, iclass 31, count 0 2006.286.04:19:47.85#ibcon#read 4, iclass 31, count 0 2006.286.04:19:47.85#ibcon#about to read 5, iclass 31, count 0 2006.286.04:19:47.85#ibcon#read 5, iclass 31, count 0 2006.286.04:19:47.85#ibcon#about to read 6, iclass 31, count 0 2006.286.04:19:47.85#ibcon#read 6, iclass 31, count 0 2006.286.04:19:47.85#ibcon#end of sib2, iclass 31, count 0 2006.286.04:19:47.85#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:19:47.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:19:47.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:19:47.85#ibcon#*before write, iclass 31, count 0 2006.286.04:19:47.85#ibcon#enter sib2, iclass 31, count 0 2006.286.04:19:47.85#ibcon#flushed, iclass 31, count 0 2006.286.04:19:47.85#ibcon#about to write, iclass 31, count 0 2006.286.04:19:47.85#ibcon#wrote, iclass 31, count 0 2006.286.04:19:47.85#ibcon#about to read 3, iclass 31, count 0 2006.286.04:19:47.89#ibcon#read 3, iclass 31, count 0 2006.286.04:19:47.89#ibcon#about to read 4, iclass 31, count 0 2006.286.04:19:47.89#ibcon#read 4, iclass 31, count 0 2006.286.04:19:47.89#ibcon#about to read 5, iclass 31, count 0 2006.286.04:19:47.89#ibcon#read 5, iclass 31, count 0 2006.286.04:19:47.89#ibcon#about to read 6, iclass 31, count 0 2006.286.04:19:47.89#ibcon#read 6, iclass 31, count 0 2006.286.04:19:47.89#ibcon#end of sib2, iclass 31, count 0 2006.286.04:19:47.89#ibcon#*after write, iclass 31, count 0 2006.286.04:19:47.89#ibcon#*before return 0, iclass 31, count 0 2006.286.04:19:47.89#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:19:47.89#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:19:47.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:19:47.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:19:47.89$vck44/vb=7,4 2006.286.04:19:47.89#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.04:19:47.89#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.04:19:47.89#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:47.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:19:47.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:19:47.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:19:47.89#ibcon#enter wrdev, iclass 33, count 2 2006.286.04:19:47.89#ibcon#first serial, iclass 33, count 2 2006.286.04:19:47.89#ibcon#enter sib2, iclass 33, count 2 2006.286.04:19:47.89#ibcon#flushed, iclass 33, count 2 2006.286.04:19:47.89#ibcon#about to write, iclass 33, count 2 2006.286.04:19:47.89#ibcon#wrote, iclass 33, count 2 2006.286.04:19:47.89#ibcon#about to read 3, iclass 33, count 2 2006.286.04:19:47.91#ibcon#read 3, iclass 33, count 2 2006.286.04:19:47.91#ibcon#about to read 4, iclass 33, count 2 2006.286.04:19:47.91#ibcon#read 4, iclass 33, count 2 2006.286.04:19:47.91#ibcon#about to read 5, iclass 33, count 2 2006.286.04:19:47.91#ibcon#read 5, iclass 33, count 2 2006.286.04:19:47.91#ibcon#about to read 6, iclass 33, count 2 2006.286.04:19:47.91#ibcon#read 6, iclass 33, count 2 2006.286.04:19:47.91#ibcon#end of sib2, iclass 33, count 2 2006.286.04:19:47.91#ibcon#*mode == 0, iclass 33, count 2 2006.286.04:19:47.91#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.04:19:47.91#ibcon#[27=AT07-04\r\n] 2006.286.04:19:47.91#ibcon#*before write, iclass 33, count 2 2006.286.04:19:47.91#ibcon#enter sib2, iclass 33, count 2 2006.286.04:19:47.91#ibcon#flushed, iclass 33, count 2 2006.286.04:19:47.91#ibcon#about to write, iclass 33, count 2 2006.286.04:19:47.91#ibcon#wrote, iclass 33, count 2 2006.286.04:19:47.91#ibcon#about to read 3, iclass 33, count 2 2006.286.04:19:47.94#ibcon#read 3, iclass 33, count 2 2006.286.04:19:47.94#ibcon#about to read 4, iclass 33, count 2 2006.286.04:19:47.94#ibcon#read 4, iclass 33, count 2 2006.286.04:19:47.94#ibcon#about to read 5, iclass 33, count 2 2006.286.04:19:47.94#ibcon#read 5, iclass 33, count 2 2006.286.04:19:47.94#ibcon#about to read 6, iclass 33, count 2 2006.286.04:19:47.94#ibcon#read 6, iclass 33, count 2 2006.286.04:19:47.94#ibcon#end of sib2, iclass 33, count 2 2006.286.04:19:47.94#ibcon#*after write, iclass 33, count 2 2006.286.04:19:47.94#ibcon#*before return 0, iclass 33, count 2 2006.286.04:19:47.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:19:47.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:19:47.94#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.04:19:47.94#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:47.94#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:19:48.06#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:19:48.06#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:19:48.06#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:19:48.06#ibcon#first serial, iclass 33, count 0 2006.286.04:19:48.06#ibcon#enter sib2, iclass 33, count 0 2006.286.04:19:48.06#ibcon#flushed, iclass 33, count 0 2006.286.04:19:48.06#ibcon#about to write, iclass 33, count 0 2006.286.04:19:48.06#ibcon#wrote, iclass 33, count 0 2006.286.04:19:48.06#ibcon#about to read 3, iclass 33, count 0 2006.286.04:19:48.08#ibcon#read 3, iclass 33, count 0 2006.286.04:19:48.08#ibcon#about to read 4, iclass 33, count 0 2006.286.04:19:48.08#ibcon#read 4, iclass 33, count 0 2006.286.04:19:48.08#ibcon#about to read 5, iclass 33, count 0 2006.286.04:19:48.08#ibcon#read 5, iclass 33, count 0 2006.286.04:19:48.08#ibcon#about to read 6, iclass 33, count 0 2006.286.04:19:48.08#ibcon#read 6, iclass 33, count 0 2006.286.04:19:48.08#ibcon#end of sib2, iclass 33, count 0 2006.286.04:19:48.08#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:19:48.08#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:19:48.08#ibcon#[27=USB\r\n] 2006.286.04:19:48.08#ibcon#*before write, iclass 33, count 0 2006.286.04:19:48.08#ibcon#enter sib2, iclass 33, count 0 2006.286.04:19:48.08#ibcon#flushed, iclass 33, count 0 2006.286.04:19:48.08#ibcon#about to write, iclass 33, count 0 2006.286.04:19:48.08#ibcon#wrote, iclass 33, count 0 2006.286.04:19:48.08#ibcon#about to read 3, iclass 33, count 0 2006.286.04:19:48.11#ibcon#read 3, iclass 33, count 0 2006.286.04:19:48.11#ibcon#about to read 4, iclass 33, count 0 2006.286.04:19:48.11#ibcon#read 4, iclass 33, count 0 2006.286.04:19:48.11#ibcon#about to read 5, iclass 33, count 0 2006.286.04:19:48.11#ibcon#read 5, iclass 33, count 0 2006.286.04:19:48.11#ibcon#about to read 6, iclass 33, count 0 2006.286.04:19:48.11#ibcon#read 6, iclass 33, count 0 2006.286.04:19:48.11#ibcon#end of sib2, iclass 33, count 0 2006.286.04:19:48.11#ibcon#*after write, iclass 33, count 0 2006.286.04:19:48.11#ibcon#*before return 0, iclass 33, count 0 2006.286.04:19:48.11#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:19:48.11#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:19:48.11#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:19:48.11#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:19:48.11$vck44/vblo=8,744.99 2006.286.04:19:48.11#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.04:19:48.11#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.04:19:48.11#ibcon#ireg 17 cls_cnt 0 2006.286.04:19:48.11#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:19:48.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:19:48.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:19:48.11#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:19:48.11#ibcon#first serial, iclass 35, count 0 2006.286.04:19:48.11#ibcon#enter sib2, iclass 35, count 0 2006.286.04:19:48.11#ibcon#flushed, iclass 35, count 0 2006.286.04:19:48.11#ibcon#about to write, iclass 35, count 0 2006.286.04:19:48.11#ibcon#wrote, iclass 35, count 0 2006.286.04:19:48.11#ibcon#about to read 3, iclass 35, count 0 2006.286.04:19:48.13#ibcon#read 3, iclass 35, count 0 2006.286.04:19:48.13#ibcon#about to read 4, iclass 35, count 0 2006.286.04:19:48.13#ibcon#read 4, iclass 35, count 0 2006.286.04:19:48.13#ibcon#about to read 5, iclass 35, count 0 2006.286.04:19:48.13#ibcon#read 5, iclass 35, count 0 2006.286.04:19:48.13#ibcon#about to read 6, iclass 35, count 0 2006.286.04:19:48.13#ibcon#read 6, iclass 35, count 0 2006.286.04:19:48.13#ibcon#end of sib2, iclass 35, count 0 2006.286.04:19:48.13#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:19:48.13#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:19:48.13#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:19:48.13#ibcon#*before write, iclass 35, count 0 2006.286.04:19:48.13#ibcon#enter sib2, iclass 35, count 0 2006.286.04:19:48.13#ibcon#flushed, iclass 35, count 0 2006.286.04:19:48.13#ibcon#about to write, iclass 35, count 0 2006.286.04:19:48.13#ibcon#wrote, iclass 35, count 0 2006.286.04:19:48.13#ibcon#about to read 3, iclass 35, count 0 2006.286.04:19:48.17#ibcon#read 3, iclass 35, count 0 2006.286.04:19:48.17#ibcon#about to read 4, iclass 35, count 0 2006.286.04:19:48.17#ibcon#read 4, iclass 35, count 0 2006.286.04:19:48.17#ibcon#about to read 5, iclass 35, count 0 2006.286.04:19:48.17#ibcon#read 5, iclass 35, count 0 2006.286.04:19:48.17#ibcon#about to read 6, iclass 35, count 0 2006.286.04:19:48.17#ibcon#read 6, iclass 35, count 0 2006.286.04:19:48.17#ibcon#end of sib2, iclass 35, count 0 2006.286.04:19:48.17#ibcon#*after write, iclass 35, count 0 2006.286.04:19:48.17#ibcon#*before return 0, iclass 35, count 0 2006.286.04:19:48.17#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:19:48.17#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:19:48.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:19:48.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:19:48.17$vck44/vb=8,4 2006.286.04:19:48.17#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.04:19:48.17#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.04:19:48.17#ibcon#ireg 11 cls_cnt 2 2006.286.04:19:48.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:19:48.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:19:48.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:19:48.23#ibcon#enter wrdev, iclass 37, count 2 2006.286.04:19:48.23#ibcon#first serial, iclass 37, count 2 2006.286.04:19:48.23#ibcon#enter sib2, iclass 37, count 2 2006.286.04:19:48.23#ibcon#flushed, iclass 37, count 2 2006.286.04:19:48.23#ibcon#about to write, iclass 37, count 2 2006.286.04:19:48.23#ibcon#wrote, iclass 37, count 2 2006.286.04:19:48.23#ibcon#about to read 3, iclass 37, count 2 2006.286.04:19:48.25#ibcon#read 3, iclass 37, count 2 2006.286.04:19:48.25#ibcon#about to read 4, iclass 37, count 2 2006.286.04:19:48.25#ibcon#read 4, iclass 37, count 2 2006.286.04:19:48.25#ibcon#about to read 5, iclass 37, count 2 2006.286.04:19:48.25#ibcon#read 5, iclass 37, count 2 2006.286.04:19:48.25#ibcon#about to read 6, iclass 37, count 2 2006.286.04:19:48.25#ibcon#read 6, iclass 37, count 2 2006.286.04:19:48.25#ibcon#end of sib2, iclass 37, count 2 2006.286.04:19:48.25#ibcon#*mode == 0, iclass 37, count 2 2006.286.04:19:48.25#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.04:19:48.25#ibcon#[27=AT08-04\r\n] 2006.286.04:19:48.25#ibcon#*before write, iclass 37, count 2 2006.286.04:19:48.25#ibcon#enter sib2, iclass 37, count 2 2006.286.04:19:48.25#ibcon#flushed, iclass 37, count 2 2006.286.04:19:48.25#ibcon#about to write, iclass 37, count 2 2006.286.04:19:48.25#ibcon#wrote, iclass 37, count 2 2006.286.04:19:48.25#ibcon#about to read 3, iclass 37, count 2 2006.286.04:19:48.28#ibcon#read 3, iclass 37, count 2 2006.286.04:19:48.28#ibcon#about to read 4, iclass 37, count 2 2006.286.04:19:48.28#ibcon#read 4, iclass 37, count 2 2006.286.04:19:48.28#ibcon#about to read 5, iclass 37, count 2 2006.286.04:19:48.28#ibcon#read 5, iclass 37, count 2 2006.286.04:19:48.28#ibcon#about to read 6, iclass 37, count 2 2006.286.04:19:48.28#ibcon#read 6, iclass 37, count 2 2006.286.04:19:48.28#ibcon#end of sib2, iclass 37, count 2 2006.286.04:19:48.28#ibcon#*after write, iclass 37, count 2 2006.286.04:19:48.28#ibcon#*before return 0, iclass 37, count 2 2006.286.04:19:48.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:19:48.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:19:48.28#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.04:19:48.28#ibcon#ireg 7 cls_cnt 0 2006.286.04:19:48.28#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:19:48.38#abcon#<5=/03 2.5 6.3 22.01 761014.8\r\n> 2006.286.04:19:48.40#abcon#{5=INTERFACE CLEAR} 2006.286.04:19:48.40#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:19:48.40#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:19:48.40#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:19:48.40#ibcon#first serial, iclass 37, count 0 2006.286.04:19:48.40#ibcon#enter sib2, iclass 37, count 0 2006.286.04:19:48.40#ibcon#flushed, iclass 37, count 0 2006.286.04:19:48.40#ibcon#about to write, iclass 37, count 0 2006.286.04:19:48.40#ibcon#wrote, iclass 37, count 0 2006.286.04:19:48.40#ibcon#about to read 3, iclass 37, count 0 2006.286.04:19:48.42#ibcon#read 3, iclass 37, count 0 2006.286.04:19:48.42#ibcon#about to read 4, iclass 37, count 0 2006.286.04:19:48.42#ibcon#read 4, iclass 37, count 0 2006.286.04:19:48.42#ibcon#about to read 5, iclass 37, count 0 2006.286.04:19:48.42#ibcon#read 5, iclass 37, count 0 2006.286.04:19:48.42#ibcon#about to read 6, iclass 37, count 0 2006.286.04:19:48.42#ibcon#read 6, iclass 37, count 0 2006.286.04:19:48.42#ibcon#end of sib2, iclass 37, count 0 2006.286.04:19:48.42#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:19:48.42#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:19:48.42#ibcon#[27=USB\r\n] 2006.286.04:19:48.42#ibcon#*before write, iclass 37, count 0 2006.286.04:19:48.42#ibcon#enter sib2, iclass 37, count 0 2006.286.04:19:48.42#ibcon#flushed, iclass 37, count 0 2006.286.04:19:48.42#ibcon#about to write, iclass 37, count 0 2006.286.04:19:48.42#ibcon#wrote, iclass 37, count 0 2006.286.04:19:48.42#ibcon#about to read 3, iclass 37, count 0 2006.286.04:19:48.45#ibcon#read 3, iclass 37, count 0 2006.286.04:19:48.45#ibcon#about to read 4, iclass 37, count 0 2006.286.04:19:48.45#ibcon#read 4, iclass 37, count 0 2006.286.04:19:48.45#ibcon#about to read 5, iclass 37, count 0 2006.286.04:19:48.45#ibcon#read 5, iclass 37, count 0 2006.286.04:19:48.45#ibcon#about to read 6, iclass 37, count 0 2006.286.04:19:48.45#ibcon#read 6, iclass 37, count 0 2006.286.04:19:48.45#ibcon#end of sib2, iclass 37, count 0 2006.286.04:19:48.45#ibcon#*after write, iclass 37, count 0 2006.286.04:19:48.45#ibcon#*before return 0, iclass 37, count 0 2006.286.04:19:48.45#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:19:48.45#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:19:48.45#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:19:48.45#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:19:48.45$vck44/vabw=wide 2006.286.04:19:48.45#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.04:19:48.45#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.04:19:48.45#ibcon#ireg 8 cls_cnt 0 2006.286.04:19:48.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:19:48.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:19:48.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:19:48.45#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:19:48.45#ibcon#first serial, iclass 5, count 0 2006.286.04:19:48.45#ibcon#enter sib2, iclass 5, count 0 2006.286.04:19:48.45#ibcon#flushed, iclass 5, count 0 2006.286.04:19:48.45#ibcon#about to write, iclass 5, count 0 2006.286.04:19:48.45#ibcon#wrote, iclass 5, count 0 2006.286.04:19:48.45#ibcon#about to read 3, iclass 5, count 0 2006.286.04:19:48.46#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:19:48.47#ibcon#read 3, iclass 5, count 0 2006.286.04:19:48.47#ibcon#about to read 4, iclass 5, count 0 2006.286.04:19:48.47#ibcon#read 4, iclass 5, count 0 2006.286.04:19:48.47#ibcon#about to read 5, iclass 5, count 0 2006.286.04:19:48.47#ibcon#read 5, iclass 5, count 0 2006.286.04:19:48.47#ibcon#about to read 6, iclass 5, count 0 2006.286.04:19:48.47#ibcon#read 6, iclass 5, count 0 2006.286.04:19:48.47#ibcon#end of sib2, iclass 5, count 0 2006.286.04:19:48.47#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:19:48.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:19:48.47#ibcon#[25=BW32\r\n] 2006.286.04:19:48.47#ibcon#*before write, iclass 5, count 0 2006.286.04:19:48.47#ibcon#enter sib2, iclass 5, count 0 2006.286.04:19:48.47#ibcon#flushed, iclass 5, count 0 2006.286.04:19:48.47#ibcon#about to write, iclass 5, count 0 2006.286.04:19:48.47#ibcon#wrote, iclass 5, count 0 2006.286.04:19:48.47#ibcon#about to read 3, iclass 5, count 0 2006.286.04:19:48.50#ibcon#read 3, iclass 5, count 0 2006.286.04:19:48.50#ibcon#about to read 4, iclass 5, count 0 2006.286.04:19:48.50#ibcon#read 4, iclass 5, count 0 2006.286.04:19:48.50#ibcon#about to read 5, iclass 5, count 0 2006.286.04:19:48.50#ibcon#read 5, iclass 5, count 0 2006.286.04:19:48.50#ibcon#about to read 6, iclass 5, count 0 2006.286.04:19:48.50#ibcon#read 6, iclass 5, count 0 2006.286.04:19:48.50#ibcon#end of sib2, iclass 5, count 0 2006.286.04:19:48.50#ibcon#*after write, iclass 5, count 0 2006.286.04:19:48.50#ibcon#*before return 0, iclass 5, count 0 2006.286.04:19:48.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:19:48.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:19:48.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:19:48.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:19:48.50$vck44/vbbw=wide 2006.286.04:19:48.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.04:19:48.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.04:19:48.50#ibcon#ireg 8 cls_cnt 0 2006.286.04:19:48.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:19:48.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:19:48.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:19:48.57#ibcon#enter wrdev, iclass 7, count 0 2006.286.04:19:48.57#ibcon#first serial, iclass 7, count 0 2006.286.04:19:48.57#ibcon#enter sib2, iclass 7, count 0 2006.286.04:19:48.57#ibcon#flushed, iclass 7, count 0 2006.286.04:19:48.57#ibcon#about to write, iclass 7, count 0 2006.286.04:19:48.57#ibcon#wrote, iclass 7, count 0 2006.286.04:19:48.57#ibcon#about to read 3, iclass 7, count 0 2006.286.04:19:48.59#ibcon#read 3, iclass 7, count 0 2006.286.04:19:48.59#ibcon#about to read 4, iclass 7, count 0 2006.286.04:19:48.59#ibcon#read 4, iclass 7, count 0 2006.286.04:19:48.59#ibcon#about to read 5, iclass 7, count 0 2006.286.04:19:48.59#ibcon#read 5, iclass 7, count 0 2006.286.04:19:48.59#ibcon#about to read 6, iclass 7, count 0 2006.286.04:19:48.59#ibcon#read 6, iclass 7, count 0 2006.286.04:19:48.59#ibcon#end of sib2, iclass 7, count 0 2006.286.04:19:48.59#ibcon#*mode == 0, iclass 7, count 0 2006.286.04:19:48.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.04:19:48.59#ibcon#[27=BW32\r\n] 2006.286.04:19:48.59#ibcon#*before write, iclass 7, count 0 2006.286.04:19:48.59#ibcon#enter sib2, iclass 7, count 0 2006.286.04:19:48.59#ibcon#flushed, iclass 7, count 0 2006.286.04:19:48.59#ibcon#about to write, iclass 7, count 0 2006.286.04:19:48.59#ibcon#wrote, iclass 7, count 0 2006.286.04:19:48.59#ibcon#about to read 3, iclass 7, count 0 2006.286.04:19:48.62#ibcon#read 3, iclass 7, count 0 2006.286.04:19:48.62#ibcon#about to read 4, iclass 7, count 0 2006.286.04:19:48.62#ibcon#read 4, iclass 7, count 0 2006.286.04:19:48.62#ibcon#about to read 5, iclass 7, count 0 2006.286.04:19:48.62#ibcon#read 5, iclass 7, count 0 2006.286.04:19:48.62#ibcon#about to read 6, iclass 7, count 0 2006.286.04:19:48.62#ibcon#read 6, iclass 7, count 0 2006.286.04:19:48.62#ibcon#end of sib2, iclass 7, count 0 2006.286.04:19:48.62#ibcon#*after write, iclass 7, count 0 2006.286.04:19:48.62#ibcon#*before return 0, iclass 7, count 0 2006.286.04:19:48.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:19:48.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:19:48.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.04:19:48.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.04:19:48.62$setupk4/ifdk4 2006.286.04:19:48.62$ifdk4/lo= 2006.286.04:19:48.62$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:19:48.62$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:19:48.62$ifdk4/patch= 2006.286.04:19:48.90$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:19:48.90$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:19:48.90$setupk4/!*+20s 2006.286.04:19:57.14#trakl#Source acquired 2006.286.04:19:58.55#abcon#<5=/03 2.5 6.4 22.02 741014.8\r\n> 2006.286.04:19:58.57#abcon#{5=INTERFACE CLEAR} 2006.286.04:19:58.63#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:19:59.14#flagr#flagr/antenna,acquired 2006.286.04:20:02.29$setupk4/"tpicd 2006.286.04:20:02.29$setupk4/echo=off 2006.286.04:20:02.29$setupk4/xlog=off 2006.286.04:20:02.29:!2006.286.04:20:14 2006.286.04:20:14.00:preob 2006.286.04:20:15.14/onsource/TRACKING 2006.286.04:20:15.14:!2006.286.04:20:24 2006.286.04:20:24.00:"tape 2006.286.04:20:24.00:"st=record 2006.286.04:20:24.00:data_valid=on 2006.286.04:20:24.00:midob 2006.286.04:20:24.14/onsource/TRACKING 2006.286.04:20:24.14/wx/22.03,1014.8,75 2006.286.04:20:24.31/cable/+6.4978E-03 2006.286.04:20:25.40/va/01,07,usb,yes,35,38 2006.286.04:20:25.40/va/02,06,usb,yes,35,35 2006.286.04:20:25.40/va/03,07,usb,yes,34,36 2006.286.04:20:25.40/va/04,06,usb,yes,36,38 2006.286.04:20:25.40/va/05,03,usb,yes,35,36 2006.286.04:20:25.40/va/06,04,usb,yes,32,31 2006.286.04:20:25.40/va/07,04,usb,yes,32,33 2006.286.04:20:25.40/va/08,03,usb,yes,33,40 2006.286.04:20:25.63/valo/01,524.99,yes,locked 2006.286.04:20:25.63/valo/02,534.99,yes,locked 2006.286.04:20:25.63/valo/03,564.99,yes,locked 2006.286.04:20:25.63/valo/04,624.99,yes,locked 2006.286.04:20:25.63/valo/05,734.99,yes,locked 2006.286.04:20:25.63/valo/06,814.99,yes,locked 2006.286.04:20:25.63/valo/07,864.99,yes,locked 2006.286.04:20:25.63/valo/08,884.99,yes,locked 2006.286.04:20:26.72/vb/01,04,usb,yes,38,35 2006.286.04:20:26.72/vb/02,05,usb,yes,36,35 2006.286.04:20:26.72/vb/03,04,usb,yes,37,41 2006.286.04:20:26.72/vb/04,05,usb,yes,37,36 2006.286.04:20:26.72/vb/05,04,usb,yes,33,36 2006.286.04:20:26.72/vb/06,03,usb,yes,47,42 2006.286.04:20:26.72/vb/07,04,usb,yes,38,38 2006.286.04:20:26.72/vb/08,04,usb,yes,34,39 2006.286.04:20:26.95/vblo/01,629.99,yes,locked 2006.286.04:20:26.95/vblo/02,634.99,yes,locked 2006.286.04:20:26.95/vblo/03,649.99,yes,locked 2006.286.04:20:26.95/vblo/04,679.99,yes,locked 2006.286.04:20:26.95/vblo/05,709.99,yes,locked 2006.286.04:20:26.95/vblo/06,719.99,yes,locked 2006.286.04:20:26.95/vblo/07,734.99,yes,locked 2006.286.04:20:26.95/vblo/08,744.99,yes,locked 2006.286.04:20:27.10/vabw/8 2006.286.04:20:27.25/vbbw/8 2006.286.04:20:27.34/xfe/off,on,12.0 2006.286.04:20:27.71/ifatt/23,28,28,28 2006.286.04:20:28.08/fmout-gps/S +2.72E-07 2006.286.04:20:28.10:!2006.286.04:21:54 2006.286.04:21:54.01:data_valid=off 2006.286.04:21:54.01:"et 2006.286.04:21:54.01:!+3s 2006.286.04:21:57.02:"tape 2006.286.04:21:57.02:postob 2006.286.04:21:57.24/cable/+6.4962E-03 2006.286.04:21:57.24/wx/22.07,1014.8,74 2006.286.04:21:58.07/fmout-gps/S +2.73E-07 2006.286.04:21:58.07:scan_name=286-0424,jd0610,170 2006.286.04:21:58.07:source=0059+581,010245.76,582411.1,2000.0,cw 2006.286.04:21:58.14#flagr#flagr/antenna,new-source 2006.286.04:21:59.14:checkk5 2006.286.04:21:59.66/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:22:00.11/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:22:00.51/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:22:00.89/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:22:01.33/chk_obsdata//k5ts1/T2860420??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.286.04:22:01.73/chk_obsdata//k5ts2/T2860420??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.286.04:22:02.29/chk_obsdata//k5ts3/T2860420??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.286.04:22:02.69/chk_obsdata//k5ts4/T2860420??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.286.04:22:03.62/k5log//k5ts1_log_newline 2006.286.04:22:04.53/k5log//k5ts2_log_newline 2006.286.04:22:05.32/k5log//k5ts3_log_newline 2006.286.04:22:06.14/k5log//k5ts4_log_newline 2006.286.04:22:06.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:22:06.16:setupk4=1 2006.286.04:22:06.16$setupk4/echo=on 2006.286.04:22:06.16$setupk4/pcalon 2006.286.04:22:06.16$pcalon/"no phase cal control is implemented here 2006.286.04:22:06.16$setupk4/"tpicd=stop 2006.286.04:22:06.16$setupk4/"rec=synch_on 2006.286.04:22:06.16$setupk4/"rec_mode=128 2006.286.04:22:06.16$setupk4/!* 2006.286.04:22:06.16$setupk4/recpk4 2006.286.04:22:06.16$recpk4/recpatch= 2006.286.04:22:06.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:22:06.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:22:06.16$setupk4/vck44 2006.286.04:22:06.16$vck44/valo=1,524.99 2006.286.04:22:06.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:22:06.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:22:06.17#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:06.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:22:06.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:22:06.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:22:06.17#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:22:06.17#ibcon#first serial, iclass 30, count 0 2006.286.04:22:06.17#ibcon#enter sib2, iclass 30, count 0 2006.286.04:22:06.17#ibcon#flushed, iclass 30, count 0 2006.286.04:22:06.17#ibcon#about to write, iclass 30, count 0 2006.286.04:22:06.17#ibcon#wrote, iclass 30, count 0 2006.286.04:22:06.17#ibcon#about to read 3, iclass 30, count 0 2006.286.04:22:06.19#ibcon#read 3, iclass 30, count 0 2006.286.04:22:06.19#ibcon#about to read 4, iclass 30, count 0 2006.286.04:22:06.19#ibcon#read 4, iclass 30, count 0 2006.286.04:22:06.19#ibcon#about to read 5, iclass 30, count 0 2006.286.04:22:06.19#ibcon#read 5, iclass 30, count 0 2006.286.04:22:06.19#ibcon#about to read 6, iclass 30, count 0 2006.286.04:22:06.19#ibcon#read 6, iclass 30, count 0 2006.286.04:22:06.19#ibcon#end of sib2, iclass 30, count 0 2006.286.04:22:06.19#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:22:06.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:22:06.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:22:06.19#ibcon#*before write, iclass 30, count 0 2006.286.04:22:06.19#ibcon#enter sib2, iclass 30, count 0 2006.286.04:22:06.19#ibcon#flushed, iclass 30, count 0 2006.286.04:22:06.19#ibcon#about to write, iclass 30, count 0 2006.286.04:22:06.19#ibcon#wrote, iclass 30, count 0 2006.286.04:22:06.19#ibcon#about to read 3, iclass 30, count 0 2006.286.04:22:06.24#ibcon#read 3, iclass 30, count 0 2006.286.04:22:06.24#ibcon#about to read 4, iclass 30, count 0 2006.286.04:22:06.24#ibcon#read 4, iclass 30, count 0 2006.286.04:22:06.24#ibcon#about to read 5, iclass 30, count 0 2006.286.04:22:06.24#ibcon#read 5, iclass 30, count 0 2006.286.04:22:06.24#ibcon#about to read 6, iclass 30, count 0 2006.286.04:22:06.24#ibcon#read 6, iclass 30, count 0 2006.286.04:22:06.24#ibcon#end of sib2, iclass 30, count 0 2006.286.04:22:06.24#ibcon#*after write, iclass 30, count 0 2006.286.04:22:06.24#ibcon#*before return 0, iclass 30, count 0 2006.286.04:22:06.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:22:06.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:22:06.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:22:06.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:22:06.24$vck44/va=1,7 2006.286.04:22:06.24#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.04:22:06.24#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.04:22:06.24#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:06.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:22:06.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:22:06.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:22:06.24#ibcon#enter wrdev, iclass 32, count 2 2006.286.04:22:06.24#ibcon#first serial, iclass 32, count 2 2006.286.04:22:06.24#ibcon#enter sib2, iclass 32, count 2 2006.286.04:22:06.24#ibcon#flushed, iclass 32, count 2 2006.286.04:22:06.24#ibcon#about to write, iclass 32, count 2 2006.286.04:22:06.24#ibcon#wrote, iclass 32, count 2 2006.286.04:22:06.24#ibcon#about to read 3, iclass 32, count 2 2006.286.04:22:06.26#ibcon#read 3, iclass 32, count 2 2006.286.04:22:06.26#ibcon#about to read 4, iclass 32, count 2 2006.286.04:22:06.26#ibcon#read 4, iclass 32, count 2 2006.286.04:22:06.26#ibcon#about to read 5, iclass 32, count 2 2006.286.04:22:06.26#ibcon#read 5, iclass 32, count 2 2006.286.04:22:06.26#ibcon#about to read 6, iclass 32, count 2 2006.286.04:22:06.26#ibcon#read 6, iclass 32, count 2 2006.286.04:22:06.26#ibcon#end of sib2, iclass 32, count 2 2006.286.04:22:06.26#ibcon#*mode == 0, iclass 32, count 2 2006.286.04:22:06.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.04:22:06.26#ibcon#[25=AT01-07\r\n] 2006.286.04:22:06.26#ibcon#*before write, iclass 32, count 2 2006.286.04:22:06.26#ibcon#enter sib2, iclass 32, count 2 2006.286.04:22:06.26#ibcon#flushed, iclass 32, count 2 2006.286.04:22:06.26#ibcon#about to write, iclass 32, count 2 2006.286.04:22:06.26#ibcon#wrote, iclass 32, count 2 2006.286.04:22:06.26#ibcon#about to read 3, iclass 32, count 2 2006.286.04:22:06.29#ibcon#read 3, iclass 32, count 2 2006.286.04:22:06.29#ibcon#about to read 4, iclass 32, count 2 2006.286.04:22:06.29#ibcon#read 4, iclass 32, count 2 2006.286.04:22:06.29#ibcon#about to read 5, iclass 32, count 2 2006.286.04:22:06.29#ibcon#read 5, iclass 32, count 2 2006.286.04:22:06.29#ibcon#about to read 6, iclass 32, count 2 2006.286.04:22:06.29#ibcon#read 6, iclass 32, count 2 2006.286.04:22:06.29#ibcon#end of sib2, iclass 32, count 2 2006.286.04:22:06.29#ibcon#*after write, iclass 32, count 2 2006.286.04:22:06.29#ibcon#*before return 0, iclass 32, count 2 2006.286.04:22:06.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:22:06.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:22:06.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.04:22:06.29#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:06.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:22:06.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:22:06.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:22:06.41#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:22:06.41#ibcon#first serial, iclass 32, count 0 2006.286.04:22:06.41#ibcon#enter sib2, iclass 32, count 0 2006.286.04:22:06.41#ibcon#flushed, iclass 32, count 0 2006.286.04:22:06.41#ibcon#about to write, iclass 32, count 0 2006.286.04:22:06.41#ibcon#wrote, iclass 32, count 0 2006.286.04:22:06.41#ibcon#about to read 3, iclass 32, count 0 2006.286.04:22:06.43#ibcon#read 3, iclass 32, count 0 2006.286.04:22:06.43#ibcon#about to read 4, iclass 32, count 0 2006.286.04:22:06.43#ibcon#read 4, iclass 32, count 0 2006.286.04:22:06.43#ibcon#about to read 5, iclass 32, count 0 2006.286.04:22:06.43#ibcon#read 5, iclass 32, count 0 2006.286.04:22:06.43#ibcon#about to read 6, iclass 32, count 0 2006.286.04:22:06.43#ibcon#read 6, iclass 32, count 0 2006.286.04:22:06.43#ibcon#end of sib2, iclass 32, count 0 2006.286.04:22:06.43#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:22:06.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:22:06.43#ibcon#[25=USB\r\n] 2006.286.04:22:06.43#ibcon#*before write, iclass 32, count 0 2006.286.04:22:06.43#ibcon#enter sib2, iclass 32, count 0 2006.286.04:22:06.43#ibcon#flushed, iclass 32, count 0 2006.286.04:22:06.43#ibcon#about to write, iclass 32, count 0 2006.286.04:22:06.43#ibcon#wrote, iclass 32, count 0 2006.286.04:22:06.43#ibcon#about to read 3, iclass 32, count 0 2006.286.04:22:06.46#ibcon#read 3, iclass 32, count 0 2006.286.04:22:06.46#ibcon#about to read 4, iclass 32, count 0 2006.286.04:22:06.46#ibcon#read 4, iclass 32, count 0 2006.286.04:22:06.46#ibcon#about to read 5, iclass 32, count 0 2006.286.04:22:06.46#ibcon#read 5, iclass 32, count 0 2006.286.04:22:06.46#ibcon#about to read 6, iclass 32, count 0 2006.286.04:22:06.46#ibcon#read 6, iclass 32, count 0 2006.286.04:22:06.46#ibcon#end of sib2, iclass 32, count 0 2006.286.04:22:06.46#ibcon#*after write, iclass 32, count 0 2006.286.04:22:06.46#ibcon#*before return 0, iclass 32, count 0 2006.286.04:22:06.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:22:06.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:22:06.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:22:06.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:22:06.46$vck44/valo=2,534.99 2006.286.04:22:06.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.04:22:06.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.04:22:06.46#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:06.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:22:06.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:22:06.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:22:06.46#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:22:06.46#ibcon#first serial, iclass 34, count 0 2006.286.04:22:06.46#ibcon#enter sib2, iclass 34, count 0 2006.286.04:22:06.46#ibcon#flushed, iclass 34, count 0 2006.286.04:22:06.46#ibcon#about to write, iclass 34, count 0 2006.286.04:22:06.46#ibcon#wrote, iclass 34, count 0 2006.286.04:22:06.46#ibcon#about to read 3, iclass 34, count 0 2006.286.04:22:06.48#ibcon#read 3, iclass 34, count 0 2006.286.04:22:06.48#ibcon#about to read 4, iclass 34, count 0 2006.286.04:22:06.48#ibcon#read 4, iclass 34, count 0 2006.286.04:22:06.48#ibcon#about to read 5, iclass 34, count 0 2006.286.04:22:06.48#ibcon#read 5, iclass 34, count 0 2006.286.04:22:06.48#ibcon#about to read 6, iclass 34, count 0 2006.286.04:22:06.48#ibcon#read 6, iclass 34, count 0 2006.286.04:22:06.48#ibcon#end of sib2, iclass 34, count 0 2006.286.04:22:06.48#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:22:06.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:22:06.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:22:06.48#ibcon#*before write, iclass 34, count 0 2006.286.04:22:06.48#ibcon#enter sib2, iclass 34, count 0 2006.286.04:22:06.48#ibcon#flushed, iclass 34, count 0 2006.286.04:22:06.48#ibcon#about to write, iclass 34, count 0 2006.286.04:22:06.48#ibcon#wrote, iclass 34, count 0 2006.286.04:22:06.48#ibcon#about to read 3, iclass 34, count 0 2006.286.04:22:06.52#ibcon#read 3, iclass 34, count 0 2006.286.04:22:06.52#ibcon#about to read 4, iclass 34, count 0 2006.286.04:22:06.52#ibcon#read 4, iclass 34, count 0 2006.286.04:22:06.52#ibcon#about to read 5, iclass 34, count 0 2006.286.04:22:06.52#ibcon#read 5, iclass 34, count 0 2006.286.04:22:06.52#ibcon#about to read 6, iclass 34, count 0 2006.286.04:22:06.52#ibcon#read 6, iclass 34, count 0 2006.286.04:22:06.52#ibcon#end of sib2, iclass 34, count 0 2006.286.04:22:06.52#ibcon#*after write, iclass 34, count 0 2006.286.04:22:06.52#ibcon#*before return 0, iclass 34, count 0 2006.286.04:22:06.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:22:06.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:22:06.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:22:06.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:22:06.52$vck44/va=2,6 2006.286.04:22:06.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.04:22:06.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.04:22:06.52#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:06.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:22:06.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:22:06.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:22:06.58#ibcon#enter wrdev, iclass 36, count 2 2006.286.04:22:06.58#ibcon#first serial, iclass 36, count 2 2006.286.04:22:06.58#ibcon#enter sib2, iclass 36, count 2 2006.286.04:22:06.58#ibcon#flushed, iclass 36, count 2 2006.286.04:22:06.58#ibcon#about to write, iclass 36, count 2 2006.286.04:22:06.58#ibcon#wrote, iclass 36, count 2 2006.286.04:22:06.58#ibcon#about to read 3, iclass 36, count 2 2006.286.04:22:06.60#ibcon#read 3, iclass 36, count 2 2006.286.04:22:06.60#ibcon#about to read 4, iclass 36, count 2 2006.286.04:22:06.60#ibcon#read 4, iclass 36, count 2 2006.286.04:22:06.60#ibcon#about to read 5, iclass 36, count 2 2006.286.04:22:06.60#ibcon#read 5, iclass 36, count 2 2006.286.04:22:06.60#ibcon#about to read 6, iclass 36, count 2 2006.286.04:22:06.60#ibcon#read 6, iclass 36, count 2 2006.286.04:22:06.60#ibcon#end of sib2, iclass 36, count 2 2006.286.04:22:06.60#ibcon#*mode == 0, iclass 36, count 2 2006.286.04:22:06.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.04:22:06.60#ibcon#[25=AT02-06\r\n] 2006.286.04:22:06.60#ibcon#*before write, iclass 36, count 2 2006.286.04:22:06.60#ibcon#enter sib2, iclass 36, count 2 2006.286.04:22:06.60#ibcon#flushed, iclass 36, count 2 2006.286.04:22:06.60#ibcon#about to write, iclass 36, count 2 2006.286.04:22:06.60#ibcon#wrote, iclass 36, count 2 2006.286.04:22:06.60#ibcon#about to read 3, iclass 36, count 2 2006.286.04:22:06.63#ibcon#read 3, iclass 36, count 2 2006.286.04:22:06.63#ibcon#about to read 4, iclass 36, count 2 2006.286.04:22:06.63#ibcon#read 4, iclass 36, count 2 2006.286.04:22:06.63#ibcon#about to read 5, iclass 36, count 2 2006.286.04:22:06.63#ibcon#read 5, iclass 36, count 2 2006.286.04:22:06.63#ibcon#about to read 6, iclass 36, count 2 2006.286.04:22:06.63#ibcon#read 6, iclass 36, count 2 2006.286.04:22:06.63#ibcon#end of sib2, iclass 36, count 2 2006.286.04:22:06.63#ibcon#*after write, iclass 36, count 2 2006.286.04:22:06.63#ibcon#*before return 0, iclass 36, count 2 2006.286.04:22:06.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:22:06.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:22:06.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.04:22:06.63#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:06.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:22:06.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:22:06.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:22:06.75#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:22:06.75#ibcon#first serial, iclass 36, count 0 2006.286.04:22:06.75#ibcon#enter sib2, iclass 36, count 0 2006.286.04:22:06.75#ibcon#flushed, iclass 36, count 0 2006.286.04:22:06.75#ibcon#about to write, iclass 36, count 0 2006.286.04:22:06.75#ibcon#wrote, iclass 36, count 0 2006.286.04:22:06.75#ibcon#about to read 3, iclass 36, count 0 2006.286.04:22:06.77#ibcon#read 3, iclass 36, count 0 2006.286.04:22:06.77#ibcon#about to read 4, iclass 36, count 0 2006.286.04:22:06.77#ibcon#read 4, iclass 36, count 0 2006.286.04:22:06.77#ibcon#about to read 5, iclass 36, count 0 2006.286.04:22:06.77#ibcon#read 5, iclass 36, count 0 2006.286.04:22:06.77#ibcon#about to read 6, iclass 36, count 0 2006.286.04:22:06.77#ibcon#read 6, iclass 36, count 0 2006.286.04:22:06.77#ibcon#end of sib2, iclass 36, count 0 2006.286.04:22:06.77#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:22:06.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:22:06.77#ibcon#[25=USB\r\n] 2006.286.04:22:06.77#ibcon#*before write, iclass 36, count 0 2006.286.04:22:06.77#ibcon#enter sib2, iclass 36, count 0 2006.286.04:22:06.77#ibcon#flushed, iclass 36, count 0 2006.286.04:22:06.77#ibcon#about to write, iclass 36, count 0 2006.286.04:22:06.77#ibcon#wrote, iclass 36, count 0 2006.286.04:22:06.77#ibcon#about to read 3, iclass 36, count 0 2006.286.04:22:06.80#ibcon#read 3, iclass 36, count 0 2006.286.04:22:06.80#ibcon#about to read 4, iclass 36, count 0 2006.286.04:22:06.80#ibcon#read 4, iclass 36, count 0 2006.286.04:22:06.80#ibcon#about to read 5, iclass 36, count 0 2006.286.04:22:06.80#ibcon#read 5, iclass 36, count 0 2006.286.04:22:06.80#ibcon#about to read 6, iclass 36, count 0 2006.286.04:22:06.80#ibcon#read 6, iclass 36, count 0 2006.286.04:22:06.80#ibcon#end of sib2, iclass 36, count 0 2006.286.04:22:06.80#ibcon#*after write, iclass 36, count 0 2006.286.04:22:06.80#ibcon#*before return 0, iclass 36, count 0 2006.286.04:22:06.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:22:06.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:22:06.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:22:06.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:22:06.80$vck44/valo=3,564.99 2006.286.04:22:06.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.04:22:06.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.04:22:06.80#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:06.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:22:06.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:22:06.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:22:06.80#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:22:06.80#ibcon#first serial, iclass 38, count 0 2006.286.04:22:06.80#ibcon#enter sib2, iclass 38, count 0 2006.286.04:22:06.80#ibcon#flushed, iclass 38, count 0 2006.286.04:22:06.80#ibcon#about to write, iclass 38, count 0 2006.286.04:22:06.80#ibcon#wrote, iclass 38, count 0 2006.286.04:22:06.80#ibcon#about to read 3, iclass 38, count 0 2006.286.04:22:06.82#ibcon#read 3, iclass 38, count 0 2006.286.04:22:06.82#ibcon#about to read 4, iclass 38, count 0 2006.286.04:22:06.82#ibcon#read 4, iclass 38, count 0 2006.286.04:22:06.82#ibcon#about to read 5, iclass 38, count 0 2006.286.04:22:06.82#ibcon#read 5, iclass 38, count 0 2006.286.04:22:06.82#ibcon#about to read 6, iclass 38, count 0 2006.286.04:22:06.82#ibcon#read 6, iclass 38, count 0 2006.286.04:22:06.82#ibcon#end of sib2, iclass 38, count 0 2006.286.04:22:06.82#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:22:06.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:22:06.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:22:06.82#ibcon#*before write, iclass 38, count 0 2006.286.04:22:06.82#ibcon#enter sib2, iclass 38, count 0 2006.286.04:22:06.82#ibcon#flushed, iclass 38, count 0 2006.286.04:22:06.82#ibcon#about to write, iclass 38, count 0 2006.286.04:22:06.82#ibcon#wrote, iclass 38, count 0 2006.286.04:22:06.82#ibcon#about to read 3, iclass 38, count 0 2006.286.04:22:06.86#ibcon#read 3, iclass 38, count 0 2006.286.04:22:06.86#ibcon#about to read 4, iclass 38, count 0 2006.286.04:22:06.86#ibcon#read 4, iclass 38, count 0 2006.286.04:22:06.86#ibcon#about to read 5, iclass 38, count 0 2006.286.04:22:06.86#ibcon#read 5, iclass 38, count 0 2006.286.04:22:06.86#ibcon#about to read 6, iclass 38, count 0 2006.286.04:22:06.86#ibcon#read 6, iclass 38, count 0 2006.286.04:22:06.86#ibcon#end of sib2, iclass 38, count 0 2006.286.04:22:06.86#ibcon#*after write, iclass 38, count 0 2006.286.04:22:06.86#ibcon#*before return 0, iclass 38, count 0 2006.286.04:22:06.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:22:06.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:22:06.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:22:06.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:22:06.86$vck44/va=3,7 2006.286.04:22:06.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.04:22:06.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.04:22:06.86#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:06.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:22:06.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:22:06.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:22:06.92#ibcon#enter wrdev, iclass 40, count 2 2006.286.04:22:06.92#ibcon#first serial, iclass 40, count 2 2006.286.04:22:06.92#ibcon#enter sib2, iclass 40, count 2 2006.286.04:22:06.92#ibcon#flushed, iclass 40, count 2 2006.286.04:22:06.92#ibcon#about to write, iclass 40, count 2 2006.286.04:22:06.92#ibcon#wrote, iclass 40, count 2 2006.286.04:22:06.92#ibcon#about to read 3, iclass 40, count 2 2006.286.04:22:06.94#ibcon#read 3, iclass 40, count 2 2006.286.04:22:06.94#ibcon#about to read 4, iclass 40, count 2 2006.286.04:22:06.94#ibcon#read 4, iclass 40, count 2 2006.286.04:22:06.94#ibcon#about to read 5, iclass 40, count 2 2006.286.04:22:06.94#ibcon#read 5, iclass 40, count 2 2006.286.04:22:06.94#ibcon#about to read 6, iclass 40, count 2 2006.286.04:22:06.94#ibcon#read 6, iclass 40, count 2 2006.286.04:22:06.94#ibcon#end of sib2, iclass 40, count 2 2006.286.04:22:06.94#ibcon#*mode == 0, iclass 40, count 2 2006.286.04:22:06.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.04:22:06.94#ibcon#[25=AT03-07\r\n] 2006.286.04:22:06.94#ibcon#*before write, iclass 40, count 2 2006.286.04:22:06.94#ibcon#enter sib2, iclass 40, count 2 2006.286.04:22:06.94#ibcon#flushed, iclass 40, count 2 2006.286.04:22:06.94#ibcon#about to write, iclass 40, count 2 2006.286.04:22:06.94#ibcon#wrote, iclass 40, count 2 2006.286.04:22:06.94#ibcon#about to read 3, iclass 40, count 2 2006.286.04:22:06.97#ibcon#read 3, iclass 40, count 2 2006.286.04:22:06.97#ibcon#about to read 4, iclass 40, count 2 2006.286.04:22:06.97#ibcon#read 4, iclass 40, count 2 2006.286.04:22:06.97#ibcon#about to read 5, iclass 40, count 2 2006.286.04:22:06.97#ibcon#read 5, iclass 40, count 2 2006.286.04:22:06.97#ibcon#about to read 6, iclass 40, count 2 2006.286.04:22:06.97#ibcon#read 6, iclass 40, count 2 2006.286.04:22:06.97#ibcon#end of sib2, iclass 40, count 2 2006.286.04:22:06.97#ibcon#*after write, iclass 40, count 2 2006.286.04:22:06.97#ibcon#*before return 0, iclass 40, count 2 2006.286.04:22:06.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:22:06.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:22:06.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.04:22:06.97#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:06.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:22:07.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:22:07.41#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:22:07.41#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:22:07.41#ibcon#first serial, iclass 40, count 0 2006.286.04:22:07.41#ibcon#enter sib2, iclass 40, count 0 2006.286.04:22:07.41#ibcon#flushed, iclass 40, count 0 2006.286.04:22:07.41#ibcon#about to write, iclass 40, count 0 2006.286.04:22:07.41#ibcon#wrote, iclass 40, count 0 2006.286.04:22:07.41#ibcon#about to read 3, iclass 40, count 0 2006.286.04:22:07.43#ibcon#read 3, iclass 40, count 0 2006.286.04:22:07.43#ibcon#about to read 4, iclass 40, count 0 2006.286.04:22:07.43#ibcon#read 4, iclass 40, count 0 2006.286.04:22:07.43#ibcon#about to read 5, iclass 40, count 0 2006.286.04:22:07.43#ibcon#read 5, iclass 40, count 0 2006.286.04:22:07.43#ibcon#about to read 6, iclass 40, count 0 2006.286.04:22:07.43#ibcon#read 6, iclass 40, count 0 2006.286.04:22:07.43#ibcon#end of sib2, iclass 40, count 0 2006.286.04:22:07.43#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:22:07.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:22:07.43#ibcon#[25=USB\r\n] 2006.286.04:22:07.43#ibcon#*before write, iclass 40, count 0 2006.286.04:22:07.43#ibcon#enter sib2, iclass 40, count 0 2006.286.04:22:07.43#ibcon#flushed, iclass 40, count 0 2006.286.04:22:07.43#ibcon#about to write, iclass 40, count 0 2006.286.04:22:07.43#ibcon#wrote, iclass 40, count 0 2006.286.04:22:07.43#ibcon#about to read 3, iclass 40, count 0 2006.286.04:22:07.46#ibcon#read 3, iclass 40, count 0 2006.286.04:22:07.46#ibcon#about to read 4, iclass 40, count 0 2006.286.04:22:07.46#ibcon#read 4, iclass 40, count 0 2006.286.04:22:07.46#ibcon#about to read 5, iclass 40, count 0 2006.286.04:22:07.46#ibcon#read 5, iclass 40, count 0 2006.286.04:22:07.46#ibcon#about to read 6, iclass 40, count 0 2006.286.04:22:07.46#ibcon#read 6, iclass 40, count 0 2006.286.04:22:07.46#ibcon#end of sib2, iclass 40, count 0 2006.286.04:22:07.46#ibcon#*after write, iclass 40, count 0 2006.286.04:22:07.46#ibcon#*before return 0, iclass 40, count 0 2006.286.04:22:07.46#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:22:07.46#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:22:07.46#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:22:07.46#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:22:07.46$vck44/valo=4,624.99 2006.286.04:22:07.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.04:22:07.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.04:22:07.46#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:07.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:22:07.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:22:07.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:22:07.46#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:22:07.46#ibcon#first serial, iclass 4, count 0 2006.286.04:22:07.46#ibcon#enter sib2, iclass 4, count 0 2006.286.04:22:07.46#ibcon#flushed, iclass 4, count 0 2006.286.04:22:07.46#ibcon#about to write, iclass 4, count 0 2006.286.04:22:07.46#ibcon#wrote, iclass 4, count 0 2006.286.04:22:07.46#ibcon#about to read 3, iclass 4, count 0 2006.286.04:22:07.48#ibcon#read 3, iclass 4, count 0 2006.286.04:22:07.48#ibcon#about to read 4, iclass 4, count 0 2006.286.04:22:07.48#ibcon#read 4, iclass 4, count 0 2006.286.04:22:07.48#ibcon#about to read 5, iclass 4, count 0 2006.286.04:22:07.48#ibcon#read 5, iclass 4, count 0 2006.286.04:22:07.48#ibcon#about to read 6, iclass 4, count 0 2006.286.04:22:07.48#ibcon#read 6, iclass 4, count 0 2006.286.04:22:07.48#ibcon#end of sib2, iclass 4, count 0 2006.286.04:22:07.48#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:22:07.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:22:07.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:22:07.48#ibcon#*before write, iclass 4, count 0 2006.286.04:22:07.48#ibcon#enter sib2, iclass 4, count 0 2006.286.04:22:07.48#ibcon#flushed, iclass 4, count 0 2006.286.04:22:07.48#ibcon#about to write, iclass 4, count 0 2006.286.04:22:07.48#ibcon#wrote, iclass 4, count 0 2006.286.04:22:07.48#ibcon#about to read 3, iclass 4, count 0 2006.286.04:22:07.52#ibcon#read 3, iclass 4, count 0 2006.286.04:22:07.52#ibcon#about to read 4, iclass 4, count 0 2006.286.04:22:07.52#ibcon#read 4, iclass 4, count 0 2006.286.04:22:07.52#ibcon#about to read 5, iclass 4, count 0 2006.286.04:22:07.52#ibcon#read 5, iclass 4, count 0 2006.286.04:22:07.52#ibcon#about to read 6, iclass 4, count 0 2006.286.04:22:07.52#ibcon#read 6, iclass 4, count 0 2006.286.04:22:07.52#ibcon#end of sib2, iclass 4, count 0 2006.286.04:22:07.52#ibcon#*after write, iclass 4, count 0 2006.286.04:22:07.52#ibcon#*before return 0, iclass 4, count 0 2006.286.04:22:07.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:22:07.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:22:07.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:22:07.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:22:07.52$vck44/va=4,6 2006.286.04:22:07.52#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.04:22:07.52#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.04:22:07.52#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:07.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:22:07.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:22:07.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:22:07.58#ibcon#enter wrdev, iclass 6, count 2 2006.286.04:22:07.58#ibcon#first serial, iclass 6, count 2 2006.286.04:22:07.58#ibcon#enter sib2, iclass 6, count 2 2006.286.04:22:07.58#ibcon#flushed, iclass 6, count 2 2006.286.04:22:07.58#ibcon#about to write, iclass 6, count 2 2006.286.04:22:07.58#ibcon#wrote, iclass 6, count 2 2006.286.04:22:07.58#ibcon#about to read 3, iclass 6, count 2 2006.286.04:22:07.60#ibcon#read 3, iclass 6, count 2 2006.286.04:22:07.60#ibcon#about to read 4, iclass 6, count 2 2006.286.04:22:07.60#ibcon#read 4, iclass 6, count 2 2006.286.04:22:07.60#ibcon#about to read 5, iclass 6, count 2 2006.286.04:22:07.60#ibcon#read 5, iclass 6, count 2 2006.286.04:22:07.60#ibcon#about to read 6, iclass 6, count 2 2006.286.04:22:07.60#ibcon#read 6, iclass 6, count 2 2006.286.04:22:07.60#ibcon#end of sib2, iclass 6, count 2 2006.286.04:22:07.60#ibcon#*mode == 0, iclass 6, count 2 2006.286.04:22:07.60#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.04:22:07.60#ibcon#[25=AT04-06\r\n] 2006.286.04:22:07.60#ibcon#*before write, iclass 6, count 2 2006.286.04:22:07.60#ibcon#enter sib2, iclass 6, count 2 2006.286.04:22:07.60#ibcon#flushed, iclass 6, count 2 2006.286.04:22:07.60#ibcon#about to write, iclass 6, count 2 2006.286.04:22:07.60#ibcon#wrote, iclass 6, count 2 2006.286.04:22:07.60#ibcon#about to read 3, iclass 6, count 2 2006.286.04:22:07.63#ibcon#read 3, iclass 6, count 2 2006.286.04:22:07.63#ibcon#about to read 4, iclass 6, count 2 2006.286.04:22:07.63#ibcon#read 4, iclass 6, count 2 2006.286.04:22:07.63#ibcon#about to read 5, iclass 6, count 2 2006.286.04:22:07.63#ibcon#read 5, iclass 6, count 2 2006.286.04:22:07.63#ibcon#about to read 6, iclass 6, count 2 2006.286.04:22:07.63#ibcon#read 6, iclass 6, count 2 2006.286.04:22:07.63#ibcon#end of sib2, iclass 6, count 2 2006.286.04:22:07.63#ibcon#*after write, iclass 6, count 2 2006.286.04:22:07.63#ibcon#*before return 0, iclass 6, count 2 2006.286.04:22:07.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:22:07.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:22:07.63#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.04:22:07.63#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:07.63#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:22:07.75#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:22:07.75#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:22:07.75#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:22:07.75#ibcon#first serial, iclass 6, count 0 2006.286.04:22:07.75#ibcon#enter sib2, iclass 6, count 0 2006.286.04:22:07.75#ibcon#flushed, iclass 6, count 0 2006.286.04:22:07.75#ibcon#about to write, iclass 6, count 0 2006.286.04:22:07.75#ibcon#wrote, iclass 6, count 0 2006.286.04:22:07.75#ibcon#about to read 3, iclass 6, count 0 2006.286.04:22:07.77#ibcon#read 3, iclass 6, count 0 2006.286.04:22:07.77#ibcon#about to read 4, iclass 6, count 0 2006.286.04:22:07.77#ibcon#read 4, iclass 6, count 0 2006.286.04:22:07.77#ibcon#about to read 5, iclass 6, count 0 2006.286.04:22:07.77#ibcon#read 5, iclass 6, count 0 2006.286.04:22:07.77#ibcon#about to read 6, iclass 6, count 0 2006.286.04:22:07.77#ibcon#read 6, iclass 6, count 0 2006.286.04:22:07.77#ibcon#end of sib2, iclass 6, count 0 2006.286.04:22:07.77#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:22:07.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:22:07.77#ibcon#[25=USB\r\n] 2006.286.04:22:07.77#ibcon#*before write, iclass 6, count 0 2006.286.04:22:08.10#ibcon#enter sib2, iclass 6, count 0 2006.286.04:22:08.10#ibcon#flushed, iclass 6, count 0 2006.286.04:22:08.10#ibcon#about to write, iclass 6, count 0 2006.286.04:22:08.10#ibcon#wrote, iclass 6, count 0 2006.286.04:22:08.10#ibcon#about to read 3, iclass 6, count 0 2006.286.04:22:08.13#ibcon#read 3, iclass 6, count 0 2006.286.04:22:08.13#ibcon#about to read 4, iclass 6, count 0 2006.286.04:22:08.13#ibcon#read 4, iclass 6, count 0 2006.286.04:22:08.13#ibcon#about to read 5, iclass 6, count 0 2006.286.04:22:08.13#ibcon#read 5, iclass 6, count 0 2006.286.04:22:08.13#ibcon#about to read 6, iclass 6, count 0 2006.286.04:22:08.13#ibcon#read 6, iclass 6, count 0 2006.286.04:22:08.13#ibcon#end of sib2, iclass 6, count 0 2006.286.04:22:08.13#ibcon#*after write, iclass 6, count 0 2006.286.04:22:08.13#ibcon#*before return 0, iclass 6, count 0 2006.286.04:22:08.13#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:22:08.13#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:22:08.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:22:08.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:22:08.13$vck44/valo=5,734.99 2006.286.04:22:08.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.04:22:08.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.04:22:08.13#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:08.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:22:08.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:22:08.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:22:08.13#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:22:08.13#ibcon#first serial, iclass 10, count 0 2006.286.04:22:08.13#ibcon#enter sib2, iclass 10, count 0 2006.286.04:22:08.13#ibcon#flushed, iclass 10, count 0 2006.286.04:22:08.13#ibcon#about to write, iclass 10, count 0 2006.286.04:22:08.13#ibcon#wrote, iclass 10, count 0 2006.286.04:22:08.13#ibcon#about to read 3, iclass 10, count 0 2006.286.04:22:08.15#ibcon#read 3, iclass 10, count 0 2006.286.04:22:08.15#ibcon#about to read 4, iclass 10, count 0 2006.286.04:22:08.15#ibcon#read 4, iclass 10, count 0 2006.286.04:22:08.15#ibcon#about to read 5, iclass 10, count 0 2006.286.04:22:08.15#ibcon#read 5, iclass 10, count 0 2006.286.04:22:08.15#ibcon#about to read 6, iclass 10, count 0 2006.286.04:22:08.15#ibcon#read 6, iclass 10, count 0 2006.286.04:22:08.15#ibcon#end of sib2, iclass 10, count 0 2006.286.04:22:08.15#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:22:08.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:22:08.15#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:22:08.15#ibcon#*before write, iclass 10, count 0 2006.286.04:22:08.15#ibcon#enter sib2, iclass 10, count 0 2006.286.04:22:08.15#ibcon#flushed, iclass 10, count 0 2006.286.04:22:08.15#ibcon#about to write, iclass 10, count 0 2006.286.04:22:08.15#ibcon#wrote, iclass 10, count 0 2006.286.04:22:08.15#ibcon#about to read 3, iclass 10, count 0 2006.286.04:22:08.19#ibcon#read 3, iclass 10, count 0 2006.286.04:22:08.19#ibcon#about to read 4, iclass 10, count 0 2006.286.04:22:08.19#ibcon#read 4, iclass 10, count 0 2006.286.04:22:08.19#ibcon#about to read 5, iclass 10, count 0 2006.286.04:22:08.19#ibcon#read 5, iclass 10, count 0 2006.286.04:22:08.19#ibcon#about to read 6, iclass 10, count 0 2006.286.04:22:08.19#ibcon#read 6, iclass 10, count 0 2006.286.04:22:08.19#ibcon#end of sib2, iclass 10, count 0 2006.286.04:22:08.19#ibcon#*after write, iclass 10, count 0 2006.286.04:22:08.19#ibcon#*before return 0, iclass 10, count 0 2006.286.04:22:08.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:22:08.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:22:08.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:22:08.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:22:08.19$vck44/va=5,3 2006.286.04:22:08.19#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.04:22:08.19#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.04:22:08.19#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:08.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:22:08.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:22:08.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:22:08.25#ibcon#enter wrdev, iclass 12, count 2 2006.286.04:22:08.25#ibcon#first serial, iclass 12, count 2 2006.286.04:22:08.25#ibcon#enter sib2, iclass 12, count 2 2006.286.04:22:08.25#ibcon#flushed, iclass 12, count 2 2006.286.04:22:08.25#ibcon#about to write, iclass 12, count 2 2006.286.04:22:08.25#ibcon#wrote, iclass 12, count 2 2006.286.04:22:08.25#ibcon#about to read 3, iclass 12, count 2 2006.286.04:22:08.27#ibcon#read 3, iclass 12, count 2 2006.286.04:22:08.27#ibcon#about to read 4, iclass 12, count 2 2006.286.04:22:08.27#ibcon#read 4, iclass 12, count 2 2006.286.04:22:08.27#ibcon#about to read 5, iclass 12, count 2 2006.286.04:22:08.27#ibcon#read 5, iclass 12, count 2 2006.286.04:22:08.27#ibcon#about to read 6, iclass 12, count 2 2006.286.04:22:08.27#ibcon#read 6, iclass 12, count 2 2006.286.04:22:08.27#ibcon#end of sib2, iclass 12, count 2 2006.286.04:22:08.27#ibcon#*mode == 0, iclass 12, count 2 2006.286.04:22:08.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.04:22:08.27#ibcon#[25=AT05-03\r\n] 2006.286.04:22:08.27#ibcon#*before write, iclass 12, count 2 2006.286.04:22:08.27#ibcon#enter sib2, iclass 12, count 2 2006.286.04:22:08.27#ibcon#flushed, iclass 12, count 2 2006.286.04:22:08.27#ibcon#about to write, iclass 12, count 2 2006.286.04:22:08.27#ibcon#wrote, iclass 12, count 2 2006.286.04:22:08.27#ibcon#about to read 3, iclass 12, count 2 2006.286.04:22:08.30#ibcon#read 3, iclass 12, count 2 2006.286.04:22:08.30#ibcon#about to read 4, iclass 12, count 2 2006.286.04:22:08.30#ibcon#read 4, iclass 12, count 2 2006.286.04:22:08.30#ibcon#about to read 5, iclass 12, count 2 2006.286.04:22:08.30#ibcon#read 5, iclass 12, count 2 2006.286.04:22:08.30#ibcon#about to read 6, iclass 12, count 2 2006.286.04:22:08.30#ibcon#read 6, iclass 12, count 2 2006.286.04:22:08.30#ibcon#end of sib2, iclass 12, count 2 2006.286.04:22:08.30#ibcon#*after write, iclass 12, count 2 2006.286.04:22:08.30#ibcon#*before return 0, iclass 12, count 2 2006.286.04:22:08.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:22:08.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:22:08.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.04:22:08.30#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:08.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:22:08.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:22:08.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:22:08.42#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:22:08.42#ibcon#first serial, iclass 12, count 0 2006.286.04:22:08.42#ibcon#enter sib2, iclass 12, count 0 2006.286.04:22:08.42#ibcon#flushed, iclass 12, count 0 2006.286.04:22:08.42#ibcon#about to write, iclass 12, count 0 2006.286.04:22:08.42#ibcon#wrote, iclass 12, count 0 2006.286.04:22:08.42#ibcon#about to read 3, iclass 12, count 0 2006.286.04:22:08.44#ibcon#read 3, iclass 12, count 0 2006.286.04:22:08.44#ibcon#about to read 4, iclass 12, count 0 2006.286.04:22:08.44#ibcon#read 4, iclass 12, count 0 2006.286.04:22:08.44#ibcon#about to read 5, iclass 12, count 0 2006.286.04:22:08.44#ibcon#read 5, iclass 12, count 0 2006.286.04:22:08.44#ibcon#about to read 6, iclass 12, count 0 2006.286.04:22:08.44#ibcon#read 6, iclass 12, count 0 2006.286.04:22:08.44#ibcon#end of sib2, iclass 12, count 0 2006.286.04:22:08.44#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:22:08.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:22:08.44#ibcon#[25=USB\r\n] 2006.286.04:22:08.44#ibcon#*before write, iclass 12, count 0 2006.286.04:22:08.44#ibcon#enter sib2, iclass 12, count 0 2006.286.04:22:08.44#ibcon#flushed, iclass 12, count 0 2006.286.04:22:08.44#ibcon#about to write, iclass 12, count 0 2006.286.04:22:08.44#ibcon#wrote, iclass 12, count 0 2006.286.04:22:08.44#ibcon#about to read 3, iclass 12, count 0 2006.286.04:22:08.47#ibcon#read 3, iclass 12, count 0 2006.286.04:22:08.47#ibcon#about to read 4, iclass 12, count 0 2006.286.04:22:08.47#ibcon#read 4, iclass 12, count 0 2006.286.04:22:08.47#ibcon#about to read 5, iclass 12, count 0 2006.286.04:22:08.47#ibcon#read 5, iclass 12, count 0 2006.286.04:22:08.47#ibcon#about to read 6, iclass 12, count 0 2006.286.04:22:08.47#ibcon#read 6, iclass 12, count 0 2006.286.04:22:08.47#ibcon#end of sib2, iclass 12, count 0 2006.286.04:22:08.47#ibcon#*after write, iclass 12, count 0 2006.286.04:22:08.47#ibcon#*before return 0, iclass 12, count 0 2006.286.04:22:08.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:22:08.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:22:08.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:22:08.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:22:08.47$vck44/valo=6,814.99 2006.286.04:22:08.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.04:22:08.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.04:22:08.47#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:08.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:22:08.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:22:08.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:22:08.47#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:22:08.47#ibcon#first serial, iclass 14, count 0 2006.286.04:22:08.47#ibcon#enter sib2, iclass 14, count 0 2006.286.04:22:08.47#ibcon#flushed, iclass 14, count 0 2006.286.04:22:08.47#ibcon#about to write, iclass 14, count 0 2006.286.04:22:08.47#ibcon#wrote, iclass 14, count 0 2006.286.04:22:08.47#ibcon#about to read 3, iclass 14, count 0 2006.286.04:22:08.49#ibcon#read 3, iclass 14, count 0 2006.286.04:22:08.49#ibcon#about to read 4, iclass 14, count 0 2006.286.04:22:08.49#ibcon#read 4, iclass 14, count 0 2006.286.04:22:08.49#ibcon#about to read 5, iclass 14, count 0 2006.286.04:22:08.49#ibcon#read 5, iclass 14, count 0 2006.286.04:22:08.49#ibcon#about to read 6, iclass 14, count 0 2006.286.04:22:08.49#ibcon#read 6, iclass 14, count 0 2006.286.04:22:08.49#ibcon#end of sib2, iclass 14, count 0 2006.286.04:22:08.49#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:22:08.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:22:08.49#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:22:08.49#ibcon#*before write, iclass 14, count 0 2006.286.04:22:08.49#ibcon#enter sib2, iclass 14, count 0 2006.286.04:22:08.49#ibcon#flushed, iclass 14, count 0 2006.286.04:22:08.49#ibcon#about to write, iclass 14, count 0 2006.286.04:22:08.49#ibcon#wrote, iclass 14, count 0 2006.286.04:22:08.49#ibcon#about to read 3, iclass 14, count 0 2006.286.04:22:08.53#ibcon#read 3, iclass 14, count 0 2006.286.04:22:08.53#ibcon#about to read 4, iclass 14, count 0 2006.286.04:22:08.53#ibcon#read 4, iclass 14, count 0 2006.286.04:22:08.53#ibcon#about to read 5, iclass 14, count 0 2006.286.04:22:08.53#ibcon#read 5, iclass 14, count 0 2006.286.04:22:08.53#ibcon#about to read 6, iclass 14, count 0 2006.286.04:22:08.53#ibcon#read 6, iclass 14, count 0 2006.286.04:22:08.53#ibcon#end of sib2, iclass 14, count 0 2006.286.04:22:08.53#ibcon#*after write, iclass 14, count 0 2006.286.04:22:08.53#ibcon#*before return 0, iclass 14, count 0 2006.286.04:22:08.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:22:08.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:22:08.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:22:08.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:22:08.53$vck44/va=6,4 2006.286.04:22:08.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.04:22:08.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.04:22:08.53#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:08.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:22:08.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:22:08.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:22:08.59#ibcon#enter wrdev, iclass 16, count 2 2006.286.04:22:08.59#ibcon#first serial, iclass 16, count 2 2006.286.04:22:08.59#ibcon#enter sib2, iclass 16, count 2 2006.286.04:22:08.59#ibcon#flushed, iclass 16, count 2 2006.286.04:22:08.59#ibcon#about to write, iclass 16, count 2 2006.286.04:22:08.59#ibcon#wrote, iclass 16, count 2 2006.286.04:22:08.59#ibcon#about to read 3, iclass 16, count 2 2006.286.04:22:08.61#ibcon#read 3, iclass 16, count 2 2006.286.04:22:08.61#ibcon#about to read 4, iclass 16, count 2 2006.286.04:22:08.61#ibcon#read 4, iclass 16, count 2 2006.286.04:22:08.61#ibcon#about to read 5, iclass 16, count 2 2006.286.04:22:08.61#ibcon#read 5, iclass 16, count 2 2006.286.04:22:08.61#ibcon#about to read 6, iclass 16, count 2 2006.286.04:22:08.61#ibcon#read 6, iclass 16, count 2 2006.286.04:22:08.61#ibcon#end of sib2, iclass 16, count 2 2006.286.04:22:08.61#ibcon#*mode == 0, iclass 16, count 2 2006.286.04:22:08.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.04:22:08.61#ibcon#[25=AT06-04\r\n] 2006.286.04:22:08.61#ibcon#*before write, iclass 16, count 2 2006.286.04:22:08.61#ibcon#enter sib2, iclass 16, count 2 2006.286.04:22:08.61#ibcon#flushed, iclass 16, count 2 2006.286.04:22:08.61#ibcon#about to write, iclass 16, count 2 2006.286.04:22:08.61#ibcon#wrote, iclass 16, count 2 2006.286.04:22:08.61#ibcon#about to read 3, iclass 16, count 2 2006.286.04:22:08.64#ibcon#read 3, iclass 16, count 2 2006.286.04:22:08.64#ibcon#about to read 4, iclass 16, count 2 2006.286.04:22:08.64#ibcon#read 4, iclass 16, count 2 2006.286.04:22:08.64#ibcon#about to read 5, iclass 16, count 2 2006.286.04:22:08.64#ibcon#read 5, iclass 16, count 2 2006.286.04:22:08.64#ibcon#about to read 6, iclass 16, count 2 2006.286.04:22:08.64#ibcon#read 6, iclass 16, count 2 2006.286.04:22:08.64#ibcon#end of sib2, iclass 16, count 2 2006.286.04:22:08.64#ibcon#*after write, iclass 16, count 2 2006.286.04:22:08.64#ibcon#*before return 0, iclass 16, count 2 2006.286.04:22:08.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:22:08.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:22:08.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.04:22:08.64#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:08.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:22:08.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:22:08.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:22:08.76#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:22:08.76#ibcon#first serial, iclass 16, count 0 2006.286.04:22:08.76#ibcon#enter sib2, iclass 16, count 0 2006.286.04:22:08.76#ibcon#flushed, iclass 16, count 0 2006.286.04:22:08.76#ibcon#about to write, iclass 16, count 0 2006.286.04:22:08.76#ibcon#wrote, iclass 16, count 0 2006.286.04:22:08.76#ibcon#about to read 3, iclass 16, count 0 2006.286.04:22:08.78#ibcon#read 3, iclass 16, count 0 2006.286.04:22:08.78#ibcon#about to read 4, iclass 16, count 0 2006.286.04:22:08.78#ibcon#read 4, iclass 16, count 0 2006.286.04:22:08.78#ibcon#about to read 5, iclass 16, count 0 2006.286.04:22:08.78#ibcon#read 5, iclass 16, count 0 2006.286.04:22:08.78#ibcon#about to read 6, iclass 16, count 0 2006.286.04:22:08.78#ibcon#read 6, iclass 16, count 0 2006.286.04:22:08.78#ibcon#end of sib2, iclass 16, count 0 2006.286.04:22:08.78#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:22:08.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:22:08.78#ibcon#[25=USB\r\n] 2006.286.04:22:08.78#ibcon#*before write, iclass 16, count 0 2006.286.04:22:08.78#ibcon#enter sib2, iclass 16, count 0 2006.286.04:22:08.78#ibcon#flushed, iclass 16, count 0 2006.286.04:22:08.78#ibcon#about to write, iclass 16, count 0 2006.286.04:22:08.78#ibcon#wrote, iclass 16, count 0 2006.286.04:22:08.78#ibcon#about to read 3, iclass 16, count 0 2006.286.04:22:08.81#ibcon#read 3, iclass 16, count 0 2006.286.04:22:08.81#ibcon#about to read 4, iclass 16, count 0 2006.286.04:22:08.81#ibcon#read 4, iclass 16, count 0 2006.286.04:22:08.81#ibcon#about to read 5, iclass 16, count 0 2006.286.04:22:08.81#ibcon#read 5, iclass 16, count 0 2006.286.04:22:08.81#ibcon#about to read 6, iclass 16, count 0 2006.286.04:22:08.81#ibcon#read 6, iclass 16, count 0 2006.286.04:22:08.81#ibcon#end of sib2, iclass 16, count 0 2006.286.04:22:08.81#ibcon#*after write, iclass 16, count 0 2006.286.04:22:08.81#ibcon#*before return 0, iclass 16, count 0 2006.286.04:22:08.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:22:08.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:22:08.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:22:08.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:22:08.81$vck44/valo=7,864.99 2006.286.04:22:08.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.04:22:08.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.04:22:08.81#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:08.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:22:08.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:22:08.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:22:08.81#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:22:08.81#ibcon#first serial, iclass 18, count 0 2006.286.04:22:08.81#ibcon#enter sib2, iclass 18, count 0 2006.286.04:22:08.81#ibcon#flushed, iclass 18, count 0 2006.286.04:22:08.81#ibcon#about to write, iclass 18, count 0 2006.286.04:22:08.81#ibcon#wrote, iclass 18, count 0 2006.286.04:22:08.81#ibcon#about to read 3, iclass 18, count 0 2006.286.04:22:08.83#ibcon#read 3, iclass 18, count 0 2006.286.04:22:08.83#ibcon#about to read 4, iclass 18, count 0 2006.286.04:22:08.83#ibcon#read 4, iclass 18, count 0 2006.286.04:22:08.83#ibcon#about to read 5, iclass 18, count 0 2006.286.04:22:08.83#ibcon#read 5, iclass 18, count 0 2006.286.04:22:08.83#ibcon#about to read 6, iclass 18, count 0 2006.286.04:22:08.83#ibcon#read 6, iclass 18, count 0 2006.286.04:22:08.83#ibcon#end of sib2, iclass 18, count 0 2006.286.04:22:08.83#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:22:08.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:22:08.83#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:22:08.83#ibcon#*before write, iclass 18, count 0 2006.286.04:22:08.83#ibcon#enter sib2, iclass 18, count 0 2006.286.04:22:08.83#ibcon#flushed, iclass 18, count 0 2006.286.04:22:08.83#ibcon#about to write, iclass 18, count 0 2006.286.04:22:08.83#ibcon#wrote, iclass 18, count 0 2006.286.04:22:08.83#ibcon#about to read 3, iclass 18, count 0 2006.286.04:22:08.87#ibcon#read 3, iclass 18, count 0 2006.286.04:22:08.87#ibcon#about to read 4, iclass 18, count 0 2006.286.04:22:08.87#ibcon#read 4, iclass 18, count 0 2006.286.04:22:08.87#ibcon#about to read 5, iclass 18, count 0 2006.286.04:22:08.87#ibcon#read 5, iclass 18, count 0 2006.286.04:22:08.87#ibcon#about to read 6, iclass 18, count 0 2006.286.04:22:08.87#ibcon#read 6, iclass 18, count 0 2006.286.04:22:08.87#ibcon#end of sib2, iclass 18, count 0 2006.286.04:22:08.87#ibcon#*after write, iclass 18, count 0 2006.286.04:22:08.87#ibcon#*before return 0, iclass 18, count 0 2006.286.04:22:08.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:22:08.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:22:08.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:22:08.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:22:08.87$vck44/va=7,4 2006.286.04:22:08.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.04:22:08.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.04:22:08.87#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:08.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:22:08.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:22:08.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:22:08.93#ibcon#enter wrdev, iclass 20, count 2 2006.286.04:22:08.93#ibcon#first serial, iclass 20, count 2 2006.286.04:22:08.93#ibcon#enter sib2, iclass 20, count 2 2006.286.04:22:08.93#ibcon#flushed, iclass 20, count 2 2006.286.04:22:08.93#ibcon#about to write, iclass 20, count 2 2006.286.04:22:08.93#ibcon#wrote, iclass 20, count 2 2006.286.04:22:08.93#ibcon#about to read 3, iclass 20, count 2 2006.286.04:22:08.95#ibcon#read 3, iclass 20, count 2 2006.286.04:22:08.95#ibcon#about to read 4, iclass 20, count 2 2006.286.04:22:08.95#ibcon#read 4, iclass 20, count 2 2006.286.04:22:08.95#ibcon#about to read 5, iclass 20, count 2 2006.286.04:22:08.95#ibcon#read 5, iclass 20, count 2 2006.286.04:22:08.95#ibcon#about to read 6, iclass 20, count 2 2006.286.04:22:08.95#ibcon#read 6, iclass 20, count 2 2006.286.04:22:08.95#ibcon#end of sib2, iclass 20, count 2 2006.286.04:22:08.95#ibcon#*mode == 0, iclass 20, count 2 2006.286.04:22:08.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.04:22:08.95#ibcon#[25=AT07-04\r\n] 2006.286.04:22:08.95#ibcon#*before write, iclass 20, count 2 2006.286.04:22:08.95#ibcon#enter sib2, iclass 20, count 2 2006.286.04:22:08.95#ibcon#flushed, iclass 20, count 2 2006.286.04:22:08.95#ibcon#about to write, iclass 20, count 2 2006.286.04:22:08.95#ibcon#wrote, iclass 20, count 2 2006.286.04:22:08.95#ibcon#about to read 3, iclass 20, count 2 2006.286.04:22:08.98#ibcon#read 3, iclass 20, count 2 2006.286.04:22:08.98#ibcon#about to read 4, iclass 20, count 2 2006.286.04:22:08.98#ibcon#read 4, iclass 20, count 2 2006.286.04:22:08.98#ibcon#about to read 5, iclass 20, count 2 2006.286.04:22:08.98#ibcon#read 5, iclass 20, count 2 2006.286.04:22:08.98#ibcon#about to read 6, iclass 20, count 2 2006.286.04:22:08.98#ibcon#read 6, iclass 20, count 2 2006.286.04:22:08.98#ibcon#end of sib2, iclass 20, count 2 2006.286.04:22:08.98#ibcon#*after write, iclass 20, count 2 2006.286.04:22:08.98#ibcon#*before return 0, iclass 20, count 2 2006.286.04:22:08.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:22:08.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:22:08.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.04:22:08.98#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:08.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:22:09.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:22:09.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:22:09.10#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:22:09.10#ibcon#first serial, iclass 20, count 0 2006.286.04:22:09.10#ibcon#enter sib2, iclass 20, count 0 2006.286.04:22:09.10#ibcon#flushed, iclass 20, count 0 2006.286.04:22:09.10#ibcon#about to write, iclass 20, count 0 2006.286.04:22:09.10#ibcon#wrote, iclass 20, count 0 2006.286.04:22:09.10#ibcon#about to read 3, iclass 20, count 0 2006.286.04:22:09.12#ibcon#read 3, iclass 20, count 0 2006.286.04:22:09.12#ibcon#about to read 4, iclass 20, count 0 2006.286.04:22:09.12#ibcon#read 4, iclass 20, count 0 2006.286.04:22:09.12#ibcon#about to read 5, iclass 20, count 0 2006.286.04:22:09.12#ibcon#read 5, iclass 20, count 0 2006.286.04:22:09.12#ibcon#about to read 6, iclass 20, count 0 2006.286.04:22:09.12#ibcon#read 6, iclass 20, count 0 2006.286.04:22:09.12#ibcon#end of sib2, iclass 20, count 0 2006.286.04:22:09.12#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:22:09.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:22:09.12#ibcon#[25=USB\r\n] 2006.286.04:22:09.12#ibcon#*before write, iclass 20, count 0 2006.286.04:22:09.12#ibcon#enter sib2, iclass 20, count 0 2006.286.04:22:09.12#ibcon#flushed, iclass 20, count 0 2006.286.04:22:09.12#ibcon#about to write, iclass 20, count 0 2006.286.04:22:09.12#ibcon#wrote, iclass 20, count 0 2006.286.04:22:09.12#ibcon#about to read 3, iclass 20, count 0 2006.286.04:22:09.15#ibcon#read 3, iclass 20, count 0 2006.286.04:22:09.15#ibcon#about to read 4, iclass 20, count 0 2006.286.04:22:09.15#ibcon#read 4, iclass 20, count 0 2006.286.04:22:09.15#ibcon#about to read 5, iclass 20, count 0 2006.286.04:22:09.15#ibcon#read 5, iclass 20, count 0 2006.286.04:22:09.15#ibcon#about to read 6, iclass 20, count 0 2006.286.04:22:09.15#ibcon#read 6, iclass 20, count 0 2006.286.04:22:09.15#ibcon#end of sib2, iclass 20, count 0 2006.286.04:22:09.15#ibcon#*after write, iclass 20, count 0 2006.286.04:22:09.15#ibcon#*before return 0, iclass 20, count 0 2006.286.04:22:09.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:22:09.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:22:09.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:22:09.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:22:09.15$vck44/valo=8,884.99 2006.286.04:22:09.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:22:09.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:22:09.15#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:09.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:22:09.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:22:09.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:22:09.15#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:22:09.15#ibcon#first serial, iclass 22, count 0 2006.286.04:22:09.15#ibcon#enter sib2, iclass 22, count 0 2006.286.04:22:09.15#ibcon#flushed, iclass 22, count 0 2006.286.04:22:09.15#ibcon#about to write, iclass 22, count 0 2006.286.04:22:09.15#ibcon#wrote, iclass 22, count 0 2006.286.04:22:09.15#ibcon#about to read 3, iclass 22, count 0 2006.286.04:22:09.17#ibcon#read 3, iclass 22, count 0 2006.286.04:22:09.17#ibcon#about to read 4, iclass 22, count 0 2006.286.04:22:09.17#ibcon#read 4, iclass 22, count 0 2006.286.04:22:09.17#ibcon#about to read 5, iclass 22, count 0 2006.286.04:22:09.17#ibcon#read 5, iclass 22, count 0 2006.286.04:22:09.17#ibcon#about to read 6, iclass 22, count 0 2006.286.04:22:09.17#ibcon#read 6, iclass 22, count 0 2006.286.04:22:09.17#ibcon#end of sib2, iclass 22, count 0 2006.286.04:22:09.17#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:22:09.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:22:09.17#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:22:09.17#ibcon#*before write, iclass 22, count 0 2006.286.04:22:09.17#ibcon#enter sib2, iclass 22, count 0 2006.286.04:22:09.17#ibcon#flushed, iclass 22, count 0 2006.286.04:22:09.17#ibcon#about to write, iclass 22, count 0 2006.286.04:22:09.17#ibcon#wrote, iclass 22, count 0 2006.286.04:22:09.17#ibcon#about to read 3, iclass 22, count 0 2006.286.04:22:09.21#ibcon#read 3, iclass 22, count 0 2006.286.04:22:09.21#ibcon#about to read 4, iclass 22, count 0 2006.286.04:22:09.21#ibcon#read 4, iclass 22, count 0 2006.286.04:22:09.21#ibcon#about to read 5, iclass 22, count 0 2006.286.04:22:09.21#ibcon#read 5, iclass 22, count 0 2006.286.04:22:09.21#ibcon#about to read 6, iclass 22, count 0 2006.286.04:22:09.21#ibcon#read 6, iclass 22, count 0 2006.286.04:22:09.21#ibcon#end of sib2, iclass 22, count 0 2006.286.04:22:09.21#ibcon#*after write, iclass 22, count 0 2006.286.04:22:09.21#ibcon#*before return 0, iclass 22, count 0 2006.286.04:22:09.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:22:09.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:22:09.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:22:09.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:22:09.21$vck44/va=8,3 2006.286.04:22:09.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.04:22:09.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.04:22:09.21#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:09.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:22:09.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:22:09.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:22:09.27#ibcon#enter wrdev, iclass 24, count 2 2006.286.04:22:09.27#ibcon#first serial, iclass 24, count 2 2006.286.04:22:09.27#ibcon#enter sib2, iclass 24, count 2 2006.286.04:22:09.27#ibcon#flushed, iclass 24, count 2 2006.286.04:22:09.27#ibcon#about to write, iclass 24, count 2 2006.286.04:22:09.27#ibcon#wrote, iclass 24, count 2 2006.286.04:22:09.27#ibcon#about to read 3, iclass 24, count 2 2006.286.04:22:09.29#ibcon#read 3, iclass 24, count 2 2006.286.04:22:09.29#ibcon#about to read 4, iclass 24, count 2 2006.286.04:22:09.29#ibcon#read 4, iclass 24, count 2 2006.286.04:22:09.29#ibcon#about to read 5, iclass 24, count 2 2006.286.04:22:09.29#ibcon#read 5, iclass 24, count 2 2006.286.04:22:09.29#ibcon#about to read 6, iclass 24, count 2 2006.286.04:22:09.29#ibcon#read 6, iclass 24, count 2 2006.286.04:22:09.29#ibcon#end of sib2, iclass 24, count 2 2006.286.04:22:09.29#ibcon#*mode == 0, iclass 24, count 2 2006.286.04:22:09.29#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.04:22:09.29#ibcon#[25=AT08-03\r\n] 2006.286.04:22:09.29#ibcon#*before write, iclass 24, count 2 2006.286.04:22:09.29#ibcon#enter sib2, iclass 24, count 2 2006.286.04:22:09.29#ibcon#flushed, iclass 24, count 2 2006.286.04:22:09.29#ibcon#about to write, iclass 24, count 2 2006.286.04:22:09.29#ibcon#wrote, iclass 24, count 2 2006.286.04:22:09.29#ibcon#about to read 3, iclass 24, count 2 2006.286.04:22:09.32#ibcon#read 3, iclass 24, count 2 2006.286.04:22:09.32#ibcon#about to read 4, iclass 24, count 2 2006.286.04:22:09.32#ibcon#read 4, iclass 24, count 2 2006.286.04:22:09.32#ibcon#about to read 5, iclass 24, count 2 2006.286.04:22:09.32#ibcon#read 5, iclass 24, count 2 2006.286.04:22:09.32#ibcon#about to read 6, iclass 24, count 2 2006.286.04:22:09.32#ibcon#read 6, iclass 24, count 2 2006.286.04:22:09.32#ibcon#end of sib2, iclass 24, count 2 2006.286.04:22:09.32#ibcon#*after write, iclass 24, count 2 2006.286.04:22:09.32#ibcon#*before return 0, iclass 24, count 2 2006.286.04:22:09.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:22:09.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:22:09.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.04:22:09.32#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:09.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:22:09.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:22:09.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:22:09.44#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:22:09.44#ibcon#first serial, iclass 24, count 0 2006.286.04:22:09.44#ibcon#enter sib2, iclass 24, count 0 2006.286.04:22:09.44#ibcon#flushed, iclass 24, count 0 2006.286.04:22:09.44#ibcon#about to write, iclass 24, count 0 2006.286.04:22:09.44#ibcon#wrote, iclass 24, count 0 2006.286.04:22:09.44#ibcon#about to read 3, iclass 24, count 0 2006.286.04:22:09.46#ibcon#read 3, iclass 24, count 0 2006.286.04:22:09.46#ibcon#about to read 4, iclass 24, count 0 2006.286.04:22:09.46#ibcon#read 4, iclass 24, count 0 2006.286.04:22:09.46#ibcon#about to read 5, iclass 24, count 0 2006.286.04:22:09.46#ibcon#read 5, iclass 24, count 0 2006.286.04:22:09.46#ibcon#about to read 6, iclass 24, count 0 2006.286.04:22:09.46#ibcon#read 6, iclass 24, count 0 2006.286.04:22:09.46#ibcon#end of sib2, iclass 24, count 0 2006.286.04:22:09.46#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:22:09.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:22:09.46#ibcon#[25=USB\r\n] 2006.286.04:22:09.46#ibcon#*before write, iclass 24, count 0 2006.286.04:22:09.46#ibcon#enter sib2, iclass 24, count 0 2006.286.04:22:09.46#ibcon#flushed, iclass 24, count 0 2006.286.04:22:09.46#ibcon#about to write, iclass 24, count 0 2006.286.04:22:09.46#ibcon#wrote, iclass 24, count 0 2006.286.04:22:09.46#ibcon#about to read 3, iclass 24, count 0 2006.286.04:22:09.49#ibcon#read 3, iclass 24, count 0 2006.286.04:22:09.49#ibcon#about to read 4, iclass 24, count 0 2006.286.04:22:09.49#ibcon#read 4, iclass 24, count 0 2006.286.04:22:09.49#ibcon#about to read 5, iclass 24, count 0 2006.286.04:22:09.49#ibcon#read 5, iclass 24, count 0 2006.286.04:22:09.49#ibcon#about to read 6, iclass 24, count 0 2006.286.04:22:09.49#ibcon#read 6, iclass 24, count 0 2006.286.04:22:09.49#ibcon#end of sib2, iclass 24, count 0 2006.286.04:22:09.49#ibcon#*after write, iclass 24, count 0 2006.286.04:22:09.49#ibcon#*before return 0, iclass 24, count 0 2006.286.04:22:09.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:22:09.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:22:09.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:22:09.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:22:09.49$vck44/vblo=1,629.99 2006.286.04:22:09.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.04:22:09.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.04:22:09.49#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:09.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:22:09.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:22:09.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:22:09.49#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:22:09.49#ibcon#first serial, iclass 26, count 0 2006.286.04:22:09.49#ibcon#enter sib2, iclass 26, count 0 2006.286.04:22:09.49#ibcon#flushed, iclass 26, count 0 2006.286.04:22:09.49#ibcon#about to write, iclass 26, count 0 2006.286.04:22:09.49#ibcon#wrote, iclass 26, count 0 2006.286.04:22:09.49#ibcon#about to read 3, iclass 26, count 0 2006.286.04:22:09.51#ibcon#read 3, iclass 26, count 0 2006.286.04:22:09.51#ibcon#about to read 4, iclass 26, count 0 2006.286.04:22:09.51#ibcon#read 4, iclass 26, count 0 2006.286.04:22:09.51#ibcon#about to read 5, iclass 26, count 0 2006.286.04:22:09.51#ibcon#read 5, iclass 26, count 0 2006.286.04:22:09.51#ibcon#about to read 6, iclass 26, count 0 2006.286.04:22:09.51#ibcon#read 6, iclass 26, count 0 2006.286.04:22:09.51#ibcon#end of sib2, iclass 26, count 0 2006.286.04:22:09.51#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:22:09.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:22:09.51#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:22:09.51#ibcon#*before write, iclass 26, count 0 2006.286.04:22:09.51#ibcon#enter sib2, iclass 26, count 0 2006.286.04:22:09.51#ibcon#flushed, iclass 26, count 0 2006.286.04:22:09.51#ibcon#about to write, iclass 26, count 0 2006.286.04:22:09.51#ibcon#wrote, iclass 26, count 0 2006.286.04:22:09.51#ibcon#about to read 3, iclass 26, count 0 2006.286.04:22:09.55#ibcon#read 3, iclass 26, count 0 2006.286.04:22:09.55#ibcon#about to read 4, iclass 26, count 0 2006.286.04:22:09.55#ibcon#read 4, iclass 26, count 0 2006.286.04:22:09.55#ibcon#about to read 5, iclass 26, count 0 2006.286.04:22:09.55#ibcon#read 5, iclass 26, count 0 2006.286.04:22:09.55#ibcon#about to read 6, iclass 26, count 0 2006.286.04:22:09.55#ibcon#read 6, iclass 26, count 0 2006.286.04:22:09.55#ibcon#end of sib2, iclass 26, count 0 2006.286.04:22:09.55#ibcon#*after write, iclass 26, count 0 2006.286.04:22:09.55#ibcon#*before return 0, iclass 26, count 0 2006.286.04:22:09.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:22:09.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:22:09.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:22:09.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:22:09.55$vck44/vb=1,4 2006.286.04:22:09.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.04:22:09.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.04:22:09.55#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:09.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:22:09.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:22:09.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:22:09.55#ibcon#enter wrdev, iclass 28, count 2 2006.286.04:22:09.55#ibcon#first serial, iclass 28, count 2 2006.286.04:22:09.55#ibcon#enter sib2, iclass 28, count 2 2006.286.04:22:09.55#ibcon#flushed, iclass 28, count 2 2006.286.04:22:09.55#ibcon#about to write, iclass 28, count 2 2006.286.04:22:09.55#ibcon#wrote, iclass 28, count 2 2006.286.04:22:09.55#ibcon#about to read 3, iclass 28, count 2 2006.286.04:22:09.57#ibcon#read 3, iclass 28, count 2 2006.286.04:22:09.57#ibcon#about to read 4, iclass 28, count 2 2006.286.04:22:09.57#ibcon#read 4, iclass 28, count 2 2006.286.04:22:09.57#ibcon#about to read 5, iclass 28, count 2 2006.286.04:22:09.57#ibcon#read 5, iclass 28, count 2 2006.286.04:22:09.57#ibcon#about to read 6, iclass 28, count 2 2006.286.04:22:09.57#ibcon#read 6, iclass 28, count 2 2006.286.04:22:09.57#ibcon#end of sib2, iclass 28, count 2 2006.286.04:22:09.57#ibcon#*mode == 0, iclass 28, count 2 2006.286.04:22:09.57#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.04:22:09.57#ibcon#[27=AT01-04\r\n] 2006.286.04:22:09.57#ibcon#*before write, iclass 28, count 2 2006.286.04:22:09.57#ibcon#enter sib2, iclass 28, count 2 2006.286.04:22:09.57#ibcon#flushed, iclass 28, count 2 2006.286.04:22:09.57#ibcon#about to write, iclass 28, count 2 2006.286.04:22:09.57#ibcon#wrote, iclass 28, count 2 2006.286.04:22:09.57#ibcon#about to read 3, iclass 28, count 2 2006.286.04:22:09.60#ibcon#read 3, iclass 28, count 2 2006.286.04:22:09.60#ibcon#about to read 4, iclass 28, count 2 2006.286.04:22:09.60#ibcon#read 4, iclass 28, count 2 2006.286.04:22:09.60#ibcon#about to read 5, iclass 28, count 2 2006.286.04:22:09.60#ibcon#read 5, iclass 28, count 2 2006.286.04:22:09.60#ibcon#about to read 6, iclass 28, count 2 2006.286.04:22:09.60#ibcon#read 6, iclass 28, count 2 2006.286.04:22:09.60#ibcon#end of sib2, iclass 28, count 2 2006.286.04:22:09.60#ibcon#*after write, iclass 28, count 2 2006.286.04:22:09.60#ibcon#*before return 0, iclass 28, count 2 2006.286.04:22:09.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:22:09.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:22:09.60#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.04:22:09.60#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:09.60#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:22:09.72#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:22:09.72#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:22:09.72#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:22:09.72#ibcon#first serial, iclass 28, count 0 2006.286.04:22:09.72#ibcon#enter sib2, iclass 28, count 0 2006.286.04:22:09.72#ibcon#flushed, iclass 28, count 0 2006.286.04:22:09.72#ibcon#about to write, iclass 28, count 0 2006.286.04:22:09.72#ibcon#wrote, iclass 28, count 0 2006.286.04:22:09.72#ibcon#about to read 3, iclass 28, count 0 2006.286.04:22:09.74#ibcon#read 3, iclass 28, count 0 2006.286.04:22:09.74#ibcon#about to read 4, iclass 28, count 0 2006.286.04:22:09.74#ibcon#read 4, iclass 28, count 0 2006.286.04:22:09.74#ibcon#about to read 5, iclass 28, count 0 2006.286.04:22:09.74#ibcon#read 5, iclass 28, count 0 2006.286.04:22:09.74#ibcon#about to read 6, iclass 28, count 0 2006.286.04:22:09.74#ibcon#read 6, iclass 28, count 0 2006.286.04:22:09.74#ibcon#end of sib2, iclass 28, count 0 2006.286.04:22:09.74#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:22:09.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:22:09.74#ibcon#[27=USB\r\n] 2006.286.04:22:09.74#ibcon#*before write, iclass 28, count 0 2006.286.04:22:09.74#ibcon#enter sib2, iclass 28, count 0 2006.286.04:22:09.74#ibcon#flushed, iclass 28, count 0 2006.286.04:22:09.74#ibcon#about to write, iclass 28, count 0 2006.286.04:22:09.74#ibcon#wrote, iclass 28, count 0 2006.286.04:22:09.74#ibcon#about to read 3, iclass 28, count 0 2006.286.04:22:09.77#ibcon#read 3, iclass 28, count 0 2006.286.04:22:09.77#ibcon#about to read 4, iclass 28, count 0 2006.286.04:22:09.77#ibcon#read 4, iclass 28, count 0 2006.286.04:22:09.77#ibcon#about to read 5, iclass 28, count 0 2006.286.04:22:09.77#ibcon#read 5, iclass 28, count 0 2006.286.04:22:09.77#ibcon#about to read 6, iclass 28, count 0 2006.286.04:22:09.77#ibcon#read 6, iclass 28, count 0 2006.286.04:22:09.77#ibcon#end of sib2, iclass 28, count 0 2006.286.04:22:09.77#ibcon#*after write, iclass 28, count 0 2006.286.04:22:09.77#ibcon#*before return 0, iclass 28, count 0 2006.286.04:22:09.77#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:22:09.77#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:22:09.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:22:09.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:22:09.77$vck44/vblo=2,634.99 2006.286.04:22:09.77#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:22:09.77#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:22:09.77#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:09.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:22:09.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:22:09.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:22:09.77#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:22:09.77#ibcon#first serial, iclass 30, count 0 2006.286.04:22:09.77#ibcon#enter sib2, iclass 30, count 0 2006.286.04:22:09.77#ibcon#flushed, iclass 30, count 0 2006.286.04:22:09.77#ibcon#about to write, iclass 30, count 0 2006.286.04:22:09.77#ibcon#wrote, iclass 30, count 0 2006.286.04:22:09.77#ibcon#about to read 3, iclass 30, count 0 2006.286.04:22:09.79#ibcon#read 3, iclass 30, count 0 2006.286.04:22:09.79#ibcon#about to read 4, iclass 30, count 0 2006.286.04:22:09.79#ibcon#read 4, iclass 30, count 0 2006.286.04:22:09.79#ibcon#about to read 5, iclass 30, count 0 2006.286.04:22:09.79#ibcon#read 5, iclass 30, count 0 2006.286.04:22:09.79#ibcon#about to read 6, iclass 30, count 0 2006.286.04:22:09.79#ibcon#read 6, iclass 30, count 0 2006.286.04:22:09.79#ibcon#end of sib2, iclass 30, count 0 2006.286.04:22:09.79#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:22:09.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:22:09.79#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:22:09.79#ibcon#*before write, iclass 30, count 0 2006.286.04:22:09.79#ibcon#enter sib2, iclass 30, count 0 2006.286.04:22:09.79#ibcon#flushed, iclass 30, count 0 2006.286.04:22:09.79#ibcon#about to write, iclass 30, count 0 2006.286.04:22:09.79#ibcon#wrote, iclass 30, count 0 2006.286.04:22:09.79#ibcon#about to read 3, iclass 30, count 0 2006.286.04:22:09.83#ibcon#read 3, iclass 30, count 0 2006.286.04:22:09.83#ibcon#about to read 4, iclass 30, count 0 2006.286.04:22:09.83#ibcon#read 4, iclass 30, count 0 2006.286.04:22:09.83#ibcon#about to read 5, iclass 30, count 0 2006.286.04:22:09.83#ibcon#read 5, iclass 30, count 0 2006.286.04:22:09.83#ibcon#about to read 6, iclass 30, count 0 2006.286.04:22:09.83#ibcon#read 6, iclass 30, count 0 2006.286.04:22:09.83#ibcon#end of sib2, iclass 30, count 0 2006.286.04:22:09.83#ibcon#*after write, iclass 30, count 0 2006.286.04:22:09.83#ibcon#*before return 0, iclass 30, count 0 2006.286.04:22:09.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:22:09.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:22:09.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:22:09.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:22:09.83$vck44/vb=2,5 2006.286.04:22:09.83#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.04:22:09.83#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.04:22:09.83#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:09.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:22:09.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:22:09.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:22:09.89#ibcon#enter wrdev, iclass 32, count 2 2006.286.04:22:09.89#ibcon#first serial, iclass 32, count 2 2006.286.04:22:09.89#ibcon#enter sib2, iclass 32, count 2 2006.286.04:22:09.89#ibcon#flushed, iclass 32, count 2 2006.286.04:22:09.89#ibcon#about to write, iclass 32, count 2 2006.286.04:22:09.89#ibcon#wrote, iclass 32, count 2 2006.286.04:22:09.89#ibcon#about to read 3, iclass 32, count 2 2006.286.04:22:09.91#ibcon#read 3, iclass 32, count 2 2006.286.04:22:09.91#ibcon#about to read 4, iclass 32, count 2 2006.286.04:22:09.91#ibcon#read 4, iclass 32, count 2 2006.286.04:22:09.91#ibcon#about to read 5, iclass 32, count 2 2006.286.04:22:09.91#ibcon#read 5, iclass 32, count 2 2006.286.04:22:09.91#ibcon#about to read 6, iclass 32, count 2 2006.286.04:22:09.91#ibcon#read 6, iclass 32, count 2 2006.286.04:22:09.91#ibcon#end of sib2, iclass 32, count 2 2006.286.04:22:09.91#ibcon#*mode == 0, iclass 32, count 2 2006.286.04:22:09.91#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.04:22:09.91#ibcon#[27=AT02-05\r\n] 2006.286.04:22:09.91#ibcon#*before write, iclass 32, count 2 2006.286.04:22:09.91#ibcon#enter sib2, iclass 32, count 2 2006.286.04:22:09.91#ibcon#flushed, iclass 32, count 2 2006.286.04:22:09.91#ibcon#about to write, iclass 32, count 2 2006.286.04:22:09.91#ibcon#wrote, iclass 32, count 2 2006.286.04:22:09.91#ibcon#about to read 3, iclass 32, count 2 2006.286.04:22:09.94#ibcon#read 3, iclass 32, count 2 2006.286.04:22:09.94#ibcon#about to read 4, iclass 32, count 2 2006.286.04:22:09.94#ibcon#read 4, iclass 32, count 2 2006.286.04:22:09.94#ibcon#about to read 5, iclass 32, count 2 2006.286.04:22:09.94#ibcon#read 5, iclass 32, count 2 2006.286.04:22:09.94#ibcon#about to read 6, iclass 32, count 2 2006.286.04:22:09.94#ibcon#read 6, iclass 32, count 2 2006.286.04:22:09.94#ibcon#end of sib2, iclass 32, count 2 2006.286.04:22:09.94#ibcon#*after write, iclass 32, count 2 2006.286.04:22:09.94#ibcon#*before return 0, iclass 32, count 2 2006.286.04:22:09.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:22:09.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:22:09.94#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.04:22:09.94#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:09.94#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:22:10.06#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:22:10.06#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:22:10.06#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:22:10.06#ibcon#first serial, iclass 32, count 0 2006.286.04:22:10.06#ibcon#enter sib2, iclass 32, count 0 2006.286.04:22:10.06#ibcon#flushed, iclass 32, count 0 2006.286.04:22:10.06#ibcon#about to write, iclass 32, count 0 2006.286.04:22:10.06#ibcon#wrote, iclass 32, count 0 2006.286.04:22:10.06#ibcon#about to read 3, iclass 32, count 0 2006.286.04:22:10.08#ibcon#read 3, iclass 32, count 0 2006.286.04:22:10.08#ibcon#about to read 4, iclass 32, count 0 2006.286.04:22:10.08#ibcon#read 4, iclass 32, count 0 2006.286.04:22:10.08#ibcon#about to read 5, iclass 32, count 0 2006.286.04:22:10.08#ibcon#read 5, iclass 32, count 0 2006.286.04:22:10.08#ibcon#about to read 6, iclass 32, count 0 2006.286.04:22:10.08#ibcon#read 6, iclass 32, count 0 2006.286.04:22:10.08#ibcon#end of sib2, iclass 32, count 0 2006.286.04:22:10.08#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:22:10.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:22:10.08#ibcon#[27=USB\r\n] 2006.286.04:22:10.08#ibcon#*before write, iclass 32, count 0 2006.286.04:22:10.08#ibcon#enter sib2, iclass 32, count 0 2006.286.04:22:10.08#ibcon#flushed, iclass 32, count 0 2006.286.04:22:10.08#ibcon#about to write, iclass 32, count 0 2006.286.04:22:10.08#ibcon#wrote, iclass 32, count 0 2006.286.04:22:10.08#ibcon#about to read 3, iclass 32, count 0 2006.286.04:22:10.11#ibcon#read 3, iclass 32, count 0 2006.286.04:22:10.11#ibcon#about to read 4, iclass 32, count 0 2006.286.04:22:10.11#ibcon#read 4, iclass 32, count 0 2006.286.04:22:10.11#ibcon#about to read 5, iclass 32, count 0 2006.286.04:22:10.11#ibcon#read 5, iclass 32, count 0 2006.286.04:22:10.11#ibcon#about to read 6, iclass 32, count 0 2006.286.04:22:10.11#ibcon#read 6, iclass 32, count 0 2006.286.04:22:10.11#ibcon#end of sib2, iclass 32, count 0 2006.286.04:22:10.11#ibcon#*after write, iclass 32, count 0 2006.286.04:22:10.11#ibcon#*before return 0, iclass 32, count 0 2006.286.04:22:10.11#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:22:10.11#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:22:10.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:22:10.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:22:10.11$vck44/vblo=3,649.99 2006.286.04:22:10.13#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.04:22:10.13#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.04:22:10.13#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:10.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:22:10.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:22:10.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:22:10.13#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:22:10.13#ibcon#first serial, iclass 34, count 0 2006.286.04:22:10.13#ibcon#enter sib2, iclass 34, count 0 2006.286.04:22:10.13#ibcon#flushed, iclass 34, count 0 2006.286.04:22:10.13#ibcon#about to write, iclass 34, count 0 2006.286.04:22:10.13#ibcon#wrote, iclass 34, count 0 2006.286.04:22:10.13#ibcon#about to read 3, iclass 34, count 0 2006.286.04:22:10.15#ibcon#read 3, iclass 34, count 0 2006.286.04:22:10.15#ibcon#about to read 4, iclass 34, count 0 2006.286.04:22:10.15#ibcon#read 4, iclass 34, count 0 2006.286.04:22:10.15#ibcon#about to read 5, iclass 34, count 0 2006.286.04:22:10.15#ibcon#read 5, iclass 34, count 0 2006.286.04:22:10.15#ibcon#about to read 6, iclass 34, count 0 2006.286.04:22:10.15#ibcon#read 6, iclass 34, count 0 2006.286.04:22:10.15#ibcon#end of sib2, iclass 34, count 0 2006.286.04:22:10.15#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:22:10.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:22:10.15#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:22:10.15#ibcon#*before write, iclass 34, count 0 2006.286.04:22:10.15#ibcon#enter sib2, iclass 34, count 0 2006.286.04:22:10.15#ibcon#flushed, iclass 34, count 0 2006.286.04:22:10.15#ibcon#about to write, iclass 34, count 0 2006.286.04:22:10.15#ibcon#wrote, iclass 34, count 0 2006.286.04:22:10.15#ibcon#about to read 3, iclass 34, count 0 2006.286.04:22:10.19#ibcon#read 3, iclass 34, count 0 2006.286.04:22:10.19#ibcon#about to read 4, iclass 34, count 0 2006.286.04:22:10.19#ibcon#read 4, iclass 34, count 0 2006.286.04:22:10.19#ibcon#about to read 5, iclass 34, count 0 2006.286.04:22:10.19#ibcon#read 5, iclass 34, count 0 2006.286.04:22:10.19#ibcon#about to read 6, iclass 34, count 0 2006.286.04:22:10.19#ibcon#read 6, iclass 34, count 0 2006.286.04:22:10.19#ibcon#end of sib2, iclass 34, count 0 2006.286.04:22:10.19#ibcon#*after write, iclass 34, count 0 2006.286.04:22:10.19#ibcon#*before return 0, iclass 34, count 0 2006.286.04:22:10.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:22:10.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:22:10.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:22:10.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:22:10.19$vck44/vb=3,4 2006.286.04:22:10.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.04:22:10.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.04:22:10.19#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:10.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:22:10.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:22:10.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:22:10.23#ibcon#enter wrdev, iclass 36, count 2 2006.286.04:22:10.23#ibcon#first serial, iclass 36, count 2 2006.286.04:22:10.23#ibcon#enter sib2, iclass 36, count 2 2006.286.04:22:10.23#ibcon#flushed, iclass 36, count 2 2006.286.04:22:10.23#ibcon#about to write, iclass 36, count 2 2006.286.04:22:10.23#ibcon#wrote, iclass 36, count 2 2006.286.04:22:10.23#ibcon#about to read 3, iclass 36, count 2 2006.286.04:22:10.25#ibcon#read 3, iclass 36, count 2 2006.286.04:22:10.25#ibcon#about to read 4, iclass 36, count 2 2006.286.04:22:10.25#ibcon#read 4, iclass 36, count 2 2006.286.04:22:10.25#ibcon#about to read 5, iclass 36, count 2 2006.286.04:22:10.25#ibcon#read 5, iclass 36, count 2 2006.286.04:22:10.25#ibcon#about to read 6, iclass 36, count 2 2006.286.04:22:10.25#ibcon#read 6, iclass 36, count 2 2006.286.04:22:10.25#ibcon#end of sib2, iclass 36, count 2 2006.286.04:22:10.25#ibcon#*mode == 0, iclass 36, count 2 2006.286.04:22:10.25#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.04:22:10.25#ibcon#[27=AT03-04\r\n] 2006.286.04:22:10.25#ibcon#*before write, iclass 36, count 2 2006.286.04:22:10.25#ibcon#enter sib2, iclass 36, count 2 2006.286.04:22:10.25#ibcon#flushed, iclass 36, count 2 2006.286.04:22:10.25#ibcon#about to write, iclass 36, count 2 2006.286.04:22:10.25#ibcon#wrote, iclass 36, count 2 2006.286.04:22:10.25#ibcon#about to read 3, iclass 36, count 2 2006.286.04:22:10.28#ibcon#read 3, iclass 36, count 2 2006.286.04:22:10.28#ibcon#about to read 4, iclass 36, count 2 2006.286.04:22:10.28#ibcon#read 4, iclass 36, count 2 2006.286.04:22:10.28#ibcon#about to read 5, iclass 36, count 2 2006.286.04:22:10.28#ibcon#read 5, iclass 36, count 2 2006.286.04:22:10.28#ibcon#about to read 6, iclass 36, count 2 2006.286.04:22:10.28#ibcon#read 6, iclass 36, count 2 2006.286.04:22:10.28#ibcon#end of sib2, iclass 36, count 2 2006.286.04:22:10.28#ibcon#*after write, iclass 36, count 2 2006.286.04:22:10.28#ibcon#*before return 0, iclass 36, count 2 2006.286.04:22:10.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:22:10.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:22:10.28#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.04:22:10.28#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:10.28#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:22:10.40#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:22:10.40#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:22:10.40#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:22:10.40#ibcon#first serial, iclass 36, count 0 2006.286.04:22:10.40#ibcon#enter sib2, iclass 36, count 0 2006.286.04:22:10.40#ibcon#flushed, iclass 36, count 0 2006.286.04:22:10.40#ibcon#about to write, iclass 36, count 0 2006.286.04:22:10.40#ibcon#wrote, iclass 36, count 0 2006.286.04:22:10.40#ibcon#about to read 3, iclass 36, count 0 2006.286.04:22:10.42#ibcon#read 3, iclass 36, count 0 2006.286.04:22:10.42#ibcon#about to read 4, iclass 36, count 0 2006.286.04:22:10.42#ibcon#read 4, iclass 36, count 0 2006.286.04:22:10.42#ibcon#about to read 5, iclass 36, count 0 2006.286.04:22:10.42#ibcon#read 5, iclass 36, count 0 2006.286.04:22:10.42#ibcon#about to read 6, iclass 36, count 0 2006.286.04:22:10.42#ibcon#read 6, iclass 36, count 0 2006.286.04:22:10.42#ibcon#end of sib2, iclass 36, count 0 2006.286.04:22:10.42#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:22:10.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:22:10.42#ibcon#[27=USB\r\n] 2006.286.04:22:10.42#ibcon#*before write, iclass 36, count 0 2006.286.04:22:10.42#ibcon#enter sib2, iclass 36, count 0 2006.286.04:22:10.42#ibcon#flushed, iclass 36, count 0 2006.286.04:22:10.42#ibcon#about to write, iclass 36, count 0 2006.286.04:22:10.42#ibcon#wrote, iclass 36, count 0 2006.286.04:22:10.42#ibcon#about to read 3, iclass 36, count 0 2006.286.04:22:10.45#ibcon#read 3, iclass 36, count 0 2006.286.04:22:10.45#ibcon#about to read 4, iclass 36, count 0 2006.286.04:22:10.45#ibcon#read 4, iclass 36, count 0 2006.286.04:22:10.45#ibcon#about to read 5, iclass 36, count 0 2006.286.04:22:10.45#ibcon#read 5, iclass 36, count 0 2006.286.04:22:10.45#ibcon#about to read 6, iclass 36, count 0 2006.286.04:22:10.45#ibcon#read 6, iclass 36, count 0 2006.286.04:22:10.45#ibcon#end of sib2, iclass 36, count 0 2006.286.04:22:10.45#ibcon#*after write, iclass 36, count 0 2006.286.04:22:10.45#ibcon#*before return 0, iclass 36, count 0 2006.286.04:22:10.45#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:22:10.45#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:22:10.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:22:10.45#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:22:10.45$vck44/vblo=4,679.99 2006.286.04:22:10.45#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.04:22:10.45#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.04:22:10.45#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:10.45#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:22:10.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:22:10.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:22:10.45#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:22:10.45#ibcon#first serial, iclass 38, count 0 2006.286.04:22:10.45#ibcon#enter sib2, iclass 38, count 0 2006.286.04:22:10.45#ibcon#flushed, iclass 38, count 0 2006.286.04:22:10.45#ibcon#about to write, iclass 38, count 0 2006.286.04:22:10.45#ibcon#wrote, iclass 38, count 0 2006.286.04:22:10.45#ibcon#about to read 3, iclass 38, count 0 2006.286.04:22:10.47#ibcon#read 3, iclass 38, count 0 2006.286.04:22:10.47#ibcon#about to read 4, iclass 38, count 0 2006.286.04:22:10.47#ibcon#read 4, iclass 38, count 0 2006.286.04:22:10.47#ibcon#about to read 5, iclass 38, count 0 2006.286.04:22:10.47#ibcon#read 5, iclass 38, count 0 2006.286.04:22:10.47#ibcon#about to read 6, iclass 38, count 0 2006.286.04:22:10.47#ibcon#read 6, iclass 38, count 0 2006.286.04:22:10.47#ibcon#end of sib2, iclass 38, count 0 2006.286.04:22:10.47#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:22:10.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:22:10.47#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:22:10.47#ibcon#*before write, iclass 38, count 0 2006.286.04:22:10.47#ibcon#enter sib2, iclass 38, count 0 2006.286.04:22:10.47#ibcon#flushed, iclass 38, count 0 2006.286.04:22:10.47#ibcon#about to write, iclass 38, count 0 2006.286.04:22:10.47#ibcon#wrote, iclass 38, count 0 2006.286.04:22:10.47#ibcon#about to read 3, iclass 38, count 0 2006.286.04:22:10.51#ibcon#read 3, iclass 38, count 0 2006.286.04:22:10.51#ibcon#about to read 4, iclass 38, count 0 2006.286.04:22:10.51#ibcon#read 4, iclass 38, count 0 2006.286.04:22:10.51#ibcon#about to read 5, iclass 38, count 0 2006.286.04:22:10.51#ibcon#read 5, iclass 38, count 0 2006.286.04:22:10.51#ibcon#about to read 6, iclass 38, count 0 2006.286.04:22:10.51#ibcon#read 6, iclass 38, count 0 2006.286.04:22:10.51#ibcon#end of sib2, iclass 38, count 0 2006.286.04:22:10.51#ibcon#*after write, iclass 38, count 0 2006.286.04:22:10.51#ibcon#*before return 0, iclass 38, count 0 2006.286.04:22:10.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:22:10.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:22:10.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:22:10.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:22:10.51$vck44/vb=4,5 2006.286.04:22:10.51#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.04:22:10.51#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.04:22:10.51#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:10.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:22:10.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:22:10.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:22:10.57#ibcon#enter wrdev, iclass 40, count 2 2006.286.04:22:10.57#ibcon#first serial, iclass 40, count 2 2006.286.04:22:10.57#ibcon#enter sib2, iclass 40, count 2 2006.286.04:22:10.57#ibcon#flushed, iclass 40, count 2 2006.286.04:22:10.57#ibcon#about to write, iclass 40, count 2 2006.286.04:22:10.57#ibcon#wrote, iclass 40, count 2 2006.286.04:22:10.57#ibcon#about to read 3, iclass 40, count 2 2006.286.04:22:10.59#ibcon#read 3, iclass 40, count 2 2006.286.04:22:10.59#ibcon#about to read 4, iclass 40, count 2 2006.286.04:22:10.59#ibcon#read 4, iclass 40, count 2 2006.286.04:22:10.59#ibcon#about to read 5, iclass 40, count 2 2006.286.04:22:10.59#ibcon#read 5, iclass 40, count 2 2006.286.04:22:10.59#ibcon#about to read 6, iclass 40, count 2 2006.286.04:22:10.59#ibcon#read 6, iclass 40, count 2 2006.286.04:22:10.59#ibcon#end of sib2, iclass 40, count 2 2006.286.04:22:10.59#ibcon#*mode == 0, iclass 40, count 2 2006.286.04:22:10.59#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.04:22:10.59#ibcon#[27=AT04-05\r\n] 2006.286.04:22:10.59#ibcon#*before write, iclass 40, count 2 2006.286.04:22:10.59#ibcon#enter sib2, iclass 40, count 2 2006.286.04:22:10.59#ibcon#flushed, iclass 40, count 2 2006.286.04:22:10.59#ibcon#about to write, iclass 40, count 2 2006.286.04:22:10.59#ibcon#wrote, iclass 40, count 2 2006.286.04:22:10.59#ibcon#about to read 3, iclass 40, count 2 2006.286.04:22:10.62#ibcon#read 3, iclass 40, count 2 2006.286.04:22:10.62#ibcon#about to read 4, iclass 40, count 2 2006.286.04:22:10.62#ibcon#read 4, iclass 40, count 2 2006.286.04:22:10.62#ibcon#about to read 5, iclass 40, count 2 2006.286.04:22:10.62#ibcon#read 5, iclass 40, count 2 2006.286.04:22:10.62#ibcon#about to read 6, iclass 40, count 2 2006.286.04:22:10.62#ibcon#read 6, iclass 40, count 2 2006.286.04:22:10.62#ibcon#end of sib2, iclass 40, count 2 2006.286.04:22:10.62#ibcon#*after write, iclass 40, count 2 2006.286.04:22:10.62#ibcon#*before return 0, iclass 40, count 2 2006.286.04:22:10.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:22:10.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:22:10.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.04:22:10.62#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:10.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:22:10.74#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:22:10.74#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:22:10.74#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:22:10.74#ibcon#first serial, iclass 40, count 0 2006.286.04:22:10.74#ibcon#enter sib2, iclass 40, count 0 2006.286.04:22:10.74#ibcon#flushed, iclass 40, count 0 2006.286.04:22:10.74#ibcon#about to write, iclass 40, count 0 2006.286.04:22:10.74#ibcon#wrote, iclass 40, count 0 2006.286.04:22:10.74#ibcon#about to read 3, iclass 40, count 0 2006.286.04:22:10.76#ibcon#read 3, iclass 40, count 0 2006.286.04:22:10.76#ibcon#about to read 4, iclass 40, count 0 2006.286.04:22:10.76#ibcon#read 4, iclass 40, count 0 2006.286.04:22:10.76#ibcon#about to read 5, iclass 40, count 0 2006.286.04:22:10.76#ibcon#read 5, iclass 40, count 0 2006.286.04:22:10.76#ibcon#about to read 6, iclass 40, count 0 2006.286.04:22:10.76#ibcon#read 6, iclass 40, count 0 2006.286.04:22:10.76#ibcon#end of sib2, iclass 40, count 0 2006.286.04:22:10.76#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:22:10.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:22:10.76#ibcon#[27=USB\r\n] 2006.286.04:22:10.76#ibcon#*before write, iclass 40, count 0 2006.286.04:22:10.76#ibcon#enter sib2, iclass 40, count 0 2006.286.04:22:10.76#ibcon#flushed, iclass 40, count 0 2006.286.04:22:10.76#ibcon#about to write, iclass 40, count 0 2006.286.04:22:10.76#ibcon#wrote, iclass 40, count 0 2006.286.04:22:10.76#ibcon#about to read 3, iclass 40, count 0 2006.286.04:22:10.77#abcon#<5=/03 2.7 6.4 22.08 731014.8\r\n> 2006.286.04:22:10.79#abcon#{5=INTERFACE CLEAR} 2006.286.04:22:10.79#ibcon#read 3, iclass 40, count 0 2006.286.04:22:10.79#ibcon#about to read 4, iclass 40, count 0 2006.286.04:22:10.79#ibcon#read 4, iclass 40, count 0 2006.286.04:22:10.79#ibcon#about to read 5, iclass 40, count 0 2006.286.04:22:10.79#ibcon#read 5, iclass 40, count 0 2006.286.04:22:10.79#ibcon#about to read 6, iclass 40, count 0 2006.286.04:22:10.79#ibcon#read 6, iclass 40, count 0 2006.286.04:22:10.79#ibcon#end of sib2, iclass 40, count 0 2006.286.04:22:10.79#ibcon#*after write, iclass 40, count 0 2006.286.04:22:10.79#ibcon#*before return 0, iclass 40, count 0 2006.286.04:22:10.79#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:22:10.79#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:22:10.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:22:10.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:22:10.79$vck44/vblo=5,709.99 2006.286.04:22:10.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.04:22:10.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.04:22:10.79#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:10.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:22:10.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:22:10.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:22:10.79#ibcon#enter wrdev, iclass 7, count 0 2006.286.04:22:10.79#ibcon#first serial, iclass 7, count 0 2006.286.04:22:10.79#ibcon#enter sib2, iclass 7, count 0 2006.286.04:22:10.79#ibcon#flushed, iclass 7, count 0 2006.286.04:22:10.79#ibcon#about to write, iclass 7, count 0 2006.286.04:22:10.79#ibcon#wrote, iclass 7, count 0 2006.286.04:22:10.79#ibcon#about to read 3, iclass 7, count 0 2006.286.04:22:10.81#ibcon#read 3, iclass 7, count 0 2006.286.04:22:10.81#ibcon#about to read 4, iclass 7, count 0 2006.286.04:22:10.81#ibcon#read 4, iclass 7, count 0 2006.286.04:22:10.81#ibcon#about to read 5, iclass 7, count 0 2006.286.04:22:10.81#ibcon#read 5, iclass 7, count 0 2006.286.04:22:10.81#ibcon#about to read 6, iclass 7, count 0 2006.286.04:22:10.81#ibcon#read 6, iclass 7, count 0 2006.286.04:22:10.81#ibcon#end of sib2, iclass 7, count 0 2006.286.04:22:10.81#ibcon#*mode == 0, iclass 7, count 0 2006.286.04:22:10.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.04:22:10.81#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:22:10.81#ibcon#*before write, iclass 7, count 0 2006.286.04:22:10.81#ibcon#enter sib2, iclass 7, count 0 2006.286.04:22:10.81#ibcon#flushed, iclass 7, count 0 2006.286.04:22:10.81#ibcon#about to write, iclass 7, count 0 2006.286.04:22:10.81#ibcon#wrote, iclass 7, count 0 2006.286.04:22:10.81#ibcon#about to read 3, iclass 7, count 0 2006.286.04:22:10.85#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:22:10.85#ibcon#read 3, iclass 7, count 0 2006.286.04:22:10.85#ibcon#about to read 4, iclass 7, count 0 2006.286.04:22:10.85#ibcon#read 4, iclass 7, count 0 2006.286.04:22:10.85#ibcon#about to read 5, iclass 7, count 0 2006.286.04:22:10.85#ibcon#read 5, iclass 7, count 0 2006.286.04:22:10.85#ibcon#about to read 6, iclass 7, count 0 2006.286.04:22:10.85#ibcon#read 6, iclass 7, count 0 2006.286.04:22:10.85#ibcon#end of sib2, iclass 7, count 0 2006.286.04:22:10.85#ibcon#*after write, iclass 7, count 0 2006.286.04:22:10.85#ibcon#*before return 0, iclass 7, count 0 2006.286.04:22:10.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:22:10.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:22:10.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.04:22:10.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.04:22:10.85$vck44/vb=5,4 2006.286.04:22:10.85#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.04:22:10.85#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.04:22:10.85#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:10.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:22:10.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:22:10.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:22:10.91#ibcon#enter wrdev, iclass 12, count 2 2006.286.04:22:10.91#ibcon#first serial, iclass 12, count 2 2006.286.04:22:10.91#ibcon#enter sib2, iclass 12, count 2 2006.286.04:22:10.91#ibcon#flushed, iclass 12, count 2 2006.286.04:22:10.91#ibcon#about to write, iclass 12, count 2 2006.286.04:22:10.91#ibcon#wrote, iclass 12, count 2 2006.286.04:22:10.91#ibcon#about to read 3, iclass 12, count 2 2006.286.04:22:10.93#ibcon#read 3, iclass 12, count 2 2006.286.04:22:10.93#ibcon#about to read 4, iclass 12, count 2 2006.286.04:22:10.93#ibcon#read 4, iclass 12, count 2 2006.286.04:22:10.93#ibcon#about to read 5, iclass 12, count 2 2006.286.04:22:10.93#ibcon#read 5, iclass 12, count 2 2006.286.04:22:10.93#ibcon#about to read 6, iclass 12, count 2 2006.286.04:22:10.93#ibcon#read 6, iclass 12, count 2 2006.286.04:22:10.93#ibcon#end of sib2, iclass 12, count 2 2006.286.04:22:10.93#ibcon#*mode == 0, iclass 12, count 2 2006.286.04:22:10.93#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.04:22:10.93#ibcon#[27=AT05-04\r\n] 2006.286.04:22:10.93#ibcon#*before write, iclass 12, count 2 2006.286.04:22:10.93#ibcon#enter sib2, iclass 12, count 2 2006.286.04:22:10.93#ibcon#flushed, iclass 12, count 2 2006.286.04:22:10.93#ibcon#about to write, iclass 12, count 2 2006.286.04:22:10.93#ibcon#wrote, iclass 12, count 2 2006.286.04:22:10.93#ibcon#about to read 3, iclass 12, count 2 2006.286.04:22:10.96#ibcon#read 3, iclass 12, count 2 2006.286.04:22:10.96#ibcon#about to read 4, iclass 12, count 2 2006.286.04:22:10.96#ibcon#read 4, iclass 12, count 2 2006.286.04:22:10.96#ibcon#about to read 5, iclass 12, count 2 2006.286.04:22:10.96#ibcon#read 5, iclass 12, count 2 2006.286.04:22:10.96#ibcon#about to read 6, iclass 12, count 2 2006.286.04:22:10.96#ibcon#read 6, iclass 12, count 2 2006.286.04:22:10.96#ibcon#end of sib2, iclass 12, count 2 2006.286.04:22:10.96#ibcon#*after write, iclass 12, count 2 2006.286.04:22:10.96#ibcon#*before return 0, iclass 12, count 2 2006.286.04:22:10.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:22:10.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:22:10.96#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.04:22:10.96#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:10.96#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:22:11.08#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:22:11.08#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:22:11.08#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:22:11.08#ibcon#first serial, iclass 12, count 0 2006.286.04:22:11.08#ibcon#enter sib2, iclass 12, count 0 2006.286.04:22:11.08#ibcon#flushed, iclass 12, count 0 2006.286.04:22:11.08#ibcon#about to write, iclass 12, count 0 2006.286.04:22:11.08#ibcon#wrote, iclass 12, count 0 2006.286.04:22:11.08#ibcon#about to read 3, iclass 12, count 0 2006.286.04:22:11.10#ibcon#read 3, iclass 12, count 0 2006.286.04:22:11.10#ibcon#about to read 4, iclass 12, count 0 2006.286.04:22:11.10#ibcon#read 4, iclass 12, count 0 2006.286.04:22:11.10#ibcon#about to read 5, iclass 12, count 0 2006.286.04:22:11.10#ibcon#read 5, iclass 12, count 0 2006.286.04:22:11.10#ibcon#about to read 6, iclass 12, count 0 2006.286.04:22:11.10#ibcon#read 6, iclass 12, count 0 2006.286.04:22:11.10#ibcon#end of sib2, iclass 12, count 0 2006.286.04:22:11.10#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:22:11.10#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:22:11.10#ibcon#[27=USB\r\n] 2006.286.04:22:11.10#ibcon#*before write, iclass 12, count 0 2006.286.04:22:11.10#ibcon#enter sib2, iclass 12, count 0 2006.286.04:22:11.10#ibcon#flushed, iclass 12, count 0 2006.286.04:22:11.10#ibcon#about to write, iclass 12, count 0 2006.286.04:22:11.10#ibcon#wrote, iclass 12, count 0 2006.286.04:22:11.10#ibcon#about to read 3, iclass 12, count 0 2006.286.04:22:11.13#ibcon#read 3, iclass 12, count 0 2006.286.04:22:11.13#ibcon#about to read 4, iclass 12, count 0 2006.286.04:22:11.13#ibcon#read 4, iclass 12, count 0 2006.286.04:22:11.13#ibcon#about to read 5, iclass 12, count 0 2006.286.04:22:11.13#ibcon#read 5, iclass 12, count 0 2006.286.04:22:11.13#ibcon#about to read 6, iclass 12, count 0 2006.286.04:22:11.13#ibcon#read 6, iclass 12, count 0 2006.286.04:22:11.13#ibcon#end of sib2, iclass 12, count 0 2006.286.04:22:11.13#ibcon#*after write, iclass 12, count 0 2006.286.04:22:11.13#ibcon#*before return 0, iclass 12, count 0 2006.286.04:22:11.13#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:22:11.13#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:22:11.13#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:22:11.13#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:22:11.13$vck44/vblo=6,719.99 2006.286.04:22:11.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.04:22:11.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.04:22:11.26#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:11.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:22:11.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:22:11.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:22:11.26#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:22:11.26#ibcon#first serial, iclass 14, count 0 2006.286.04:22:11.26#ibcon#enter sib2, iclass 14, count 0 2006.286.04:22:11.26#ibcon#flushed, iclass 14, count 0 2006.286.04:22:11.26#ibcon#about to write, iclass 14, count 0 2006.286.04:22:11.26#ibcon#wrote, iclass 14, count 0 2006.286.04:22:11.26#ibcon#about to read 3, iclass 14, count 0 2006.286.04:22:11.28#ibcon#read 3, iclass 14, count 0 2006.286.04:22:11.28#ibcon#about to read 4, iclass 14, count 0 2006.286.04:22:11.28#ibcon#read 4, iclass 14, count 0 2006.286.04:22:11.28#ibcon#about to read 5, iclass 14, count 0 2006.286.04:22:11.28#ibcon#read 5, iclass 14, count 0 2006.286.04:22:11.28#ibcon#about to read 6, iclass 14, count 0 2006.286.04:22:11.28#ibcon#read 6, iclass 14, count 0 2006.286.04:22:11.28#ibcon#end of sib2, iclass 14, count 0 2006.286.04:22:11.28#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:22:11.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:22:11.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:22:11.28#ibcon#*before write, iclass 14, count 0 2006.286.04:22:11.28#ibcon#enter sib2, iclass 14, count 0 2006.286.04:22:11.28#ibcon#flushed, iclass 14, count 0 2006.286.04:22:11.28#ibcon#about to write, iclass 14, count 0 2006.286.04:22:11.28#ibcon#wrote, iclass 14, count 0 2006.286.04:22:11.28#ibcon#about to read 3, iclass 14, count 0 2006.286.04:22:11.32#ibcon#read 3, iclass 14, count 0 2006.286.04:22:11.32#ibcon#about to read 4, iclass 14, count 0 2006.286.04:22:11.32#ibcon#read 4, iclass 14, count 0 2006.286.04:22:11.32#ibcon#about to read 5, iclass 14, count 0 2006.286.04:22:11.32#ibcon#read 5, iclass 14, count 0 2006.286.04:22:11.32#ibcon#about to read 6, iclass 14, count 0 2006.286.04:22:11.32#ibcon#read 6, iclass 14, count 0 2006.286.04:22:11.32#ibcon#end of sib2, iclass 14, count 0 2006.286.04:22:11.32#ibcon#*after write, iclass 14, count 0 2006.286.04:22:11.32#ibcon#*before return 0, iclass 14, count 0 2006.286.04:22:11.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:22:11.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:22:11.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:22:11.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:22:11.32$vck44/vb=6,3 2006.286.04:22:11.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.04:22:11.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.04:22:11.32#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:11.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:22:11.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:22:11.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:22:11.32#ibcon#enter wrdev, iclass 16, count 2 2006.286.04:22:11.32#ibcon#first serial, iclass 16, count 2 2006.286.04:22:11.32#ibcon#enter sib2, iclass 16, count 2 2006.286.04:22:11.32#ibcon#flushed, iclass 16, count 2 2006.286.04:22:11.32#ibcon#about to write, iclass 16, count 2 2006.286.04:22:11.32#ibcon#wrote, iclass 16, count 2 2006.286.04:22:11.32#ibcon#about to read 3, iclass 16, count 2 2006.286.04:22:11.34#ibcon#read 3, iclass 16, count 2 2006.286.04:22:11.34#ibcon#about to read 4, iclass 16, count 2 2006.286.04:22:11.34#ibcon#read 4, iclass 16, count 2 2006.286.04:22:11.34#ibcon#about to read 5, iclass 16, count 2 2006.286.04:22:11.34#ibcon#read 5, iclass 16, count 2 2006.286.04:22:11.34#ibcon#about to read 6, iclass 16, count 2 2006.286.04:22:11.34#ibcon#read 6, iclass 16, count 2 2006.286.04:22:11.34#ibcon#end of sib2, iclass 16, count 2 2006.286.04:22:11.34#ibcon#*mode == 0, iclass 16, count 2 2006.286.04:22:11.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.04:22:11.34#ibcon#[27=AT06-03\r\n] 2006.286.04:22:11.34#ibcon#*before write, iclass 16, count 2 2006.286.04:22:11.34#ibcon#enter sib2, iclass 16, count 2 2006.286.04:22:11.34#ibcon#flushed, iclass 16, count 2 2006.286.04:22:11.34#ibcon#about to write, iclass 16, count 2 2006.286.04:22:11.34#ibcon#wrote, iclass 16, count 2 2006.286.04:22:11.34#ibcon#about to read 3, iclass 16, count 2 2006.286.04:22:11.37#ibcon#read 3, iclass 16, count 2 2006.286.04:22:11.37#ibcon#about to read 4, iclass 16, count 2 2006.286.04:22:11.37#ibcon#read 4, iclass 16, count 2 2006.286.04:22:11.37#ibcon#about to read 5, iclass 16, count 2 2006.286.04:22:11.37#ibcon#read 5, iclass 16, count 2 2006.286.04:22:11.37#ibcon#about to read 6, iclass 16, count 2 2006.286.04:22:11.37#ibcon#read 6, iclass 16, count 2 2006.286.04:22:11.37#ibcon#end of sib2, iclass 16, count 2 2006.286.04:22:11.37#ibcon#*after write, iclass 16, count 2 2006.286.04:22:11.37#ibcon#*before return 0, iclass 16, count 2 2006.286.04:22:11.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:22:11.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:22:11.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.04:22:11.37#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:11.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:22:11.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:22:11.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:22:11.49#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:22:11.49#ibcon#first serial, iclass 16, count 0 2006.286.04:22:11.49#ibcon#enter sib2, iclass 16, count 0 2006.286.04:22:11.49#ibcon#flushed, iclass 16, count 0 2006.286.04:22:11.49#ibcon#about to write, iclass 16, count 0 2006.286.04:22:11.49#ibcon#wrote, iclass 16, count 0 2006.286.04:22:11.49#ibcon#about to read 3, iclass 16, count 0 2006.286.04:22:11.51#ibcon#read 3, iclass 16, count 0 2006.286.04:22:11.51#ibcon#about to read 4, iclass 16, count 0 2006.286.04:22:11.51#ibcon#read 4, iclass 16, count 0 2006.286.04:22:11.51#ibcon#about to read 5, iclass 16, count 0 2006.286.04:22:11.51#ibcon#read 5, iclass 16, count 0 2006.286.04:22:11.51#ibcon#about to read 6, iclass 16, count 0 2006.286.04:22:11.51#ibcon#read 6, iclass 16, count 0 2006.286.04:22:11.51#ibcon#end of sib2, iclass 16, count 0 2006.286.04:22:11.51#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:22:11.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:22:11.51#ibcon#[27=USB\r\n] 2006.286.04:22:11.51#ibcon#*before write, iclass 16, count 0 2006.286.04:22:11.51#ibcon#enter sib2, iclass 16, count 0 2006.286.04:22:11.51#ibcon#flushed, iclass 16, count 0 2006.286.04:22:11.51#ibcon#about to write, iclass 16, count 0 2006.286.04:22:11.51#ibcon#wrote, iclass 16, count 0 2006.286.04:22:11.51#ibcon#about to read 3, iclass 16, count 0 2006.286.04:22:11.54#ibcon#read 3, iclass 16, count 0 2006.286.04:22:11.54#ibcon#about to read 4, iclass 16, count 0 2006.286.04:22:11.54#ibcon#read 4, iclass 16, count 0 2006.286.04:22:11.54#ibcon#about to read 5, iclass 16, count 0 2006.286.04:22:11.54#ibcon#read 5, iclass 16, count 0 2006.286.04:22:11.54#ibcon#about to read 6, iclass 16, count 0 2006.286.04:22:11.54#ibcon#read 6, iclass 16, count 0 2006.286.04:22:11.54#ibcon#end of sib2, iclass 16, count 0 2006.286.04:22:11.54#ibcon#*after write, iclass 16, count 0 2006.286.04:22:11.54#ibcon#*before return 0, iclass 16, count 0 2006.286.04:22:11.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:22:11.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:22:11.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:22:11.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:22:11.54$vck44/vblo=7,734.99 2006.286.04:22:11.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.04:22:11.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.04:22:11.54#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:11.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:22:11.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:22:11.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:22:11.54#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:22:11.54#ibcon#first serial, iclass 18, count 0 2006.286.04:22:11.54#ibcon#enter sib2, iclass 18, count 0 2006.286.04:22:11.54#ibcon#flushed, iclass 18, count 0 2006.286.04:22:11.54#ibcon#about to write, iclass 18, count 0 2006.286.04:22:11.54#ibcon#wrote, iclass 18, count 0 2006.286.04:22:11.54#ibcon#about to read 3, iclass 18, count 0 2006.286.04:22:11.56#ibcon#read 3, iclass 18, count 0 2006.286.04:22:11.56#ibcon#about to read 4, iclass 18, count 0 2006.286.04:22:11.56#ibcon#read 4, iclass 18, count 0 2006.286.04:22:11.56#ibcon#about to read 5, iclass 18, count 0 2006.286.04:22:11.56#ibcon#read 5, iclass 18, count 0 2006.286.04:22:11.56#ibcon#about to read 6, iclass 18, count 0 2006.286.04:22:11.56#ibcon#read 6, iclass 18, count 0 2006.286.04:22:11.56#ibcon#end of sib2, iclass 18, count 0 2006.286.04:22:11.56#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:22:11.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:22:11.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:22:11.56#ibcon#*before write, iclass 18, count 0 2006.286.04:22:11.56#ibcon#enter sib2, iclass 18, count 0 2006.286.04:22:11.56#ibcon#flushed, iclass 18, count 0 2006.286.04:22:11.56#ibcon#about to write, iclass 18, count 0 2006.286.04:22:11.56#ibcon#wrote, iclass 18, count 0 2006.286.04:22:11.56#ibcon#about to read 3, iclass 18, count 0 2006.286.04:22:11.60#ibcon#read 3, iclass 18, count 0 2006.286.04:22:11.60#ibcon#about to read 4, iclass 18, count 0 2006.286.04:22:11.60#ibcon#read 4, iclass 18, count 0 2006.286.04:22:11.60#ibcon#about to read 5, iclass 18, count 0 2006.286.04:22:11.60#ibcon#read 5, iclass 18, count 0 2006.286.04:22:11.60#ibcon#about to read 6, iclass 18, count 0 2006.286.04:22:11.60#ibcon#read 6, iclass 18, count 0 2006.286.04:22:11.60#ibcon#end of sib2, iclass 18, count 0 2006.286.04:22:11.60#ibcon#*after write, iclass 18, count 0 2006.286.04:22:11.60#ibcon#*before return 0, iclass 18, count 0 2006.286.04:22:11.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:22:11.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:22:11.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:22:11.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:22:11.60$vck44/vb=7,4 2006.286.04:22:11.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.04:22:11.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.04:22:11.60#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:11.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:22:11.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:22:11.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:22:11.66#ibcon#enter wrdev, iclass 20, count 2 2006.286.04:22:11.66#ibcon#first serial, iclass 20, count 2 2006.286.04:22:11.66#ibcon#enter sib2, iclass 20, count 2 2006.286.04:22:11.66#ibcon#flushed, iclass 20, count 2 2006.286.04:22:11.66#ibcon#about to write, iclass 20, count 2 2006.286.04:22:11.66#ibcon#wrote, iclass 20, count 2 2006.286.04:22:11.66#ibcon#about to read 3, iclass 20, count 2 2006.286.04:22:11.68#ibcon#read 3, iclass 20, count 2 2006.286.04:22:11.68#ibcon#about to read 4, iclass 20, count 2 2006.286.04:22:11.68#ibcon#read 4, iclass 20, count 2 2006.286.04:22:11.68#ibcon#about to read 5, iclass 20, count 2 2006.286.04:22:11.68#ibcon#read 5, iclass 20, count 2 2006.286.04:22:11.68#ibcon#about to read 6, iclass 20, count 2 2006.286.04:22:11.68#ibcon#read 6, iclass 20, count 2 2006.286.04:22:11.68#ibcon#end of sib2, iclass 20, count 2 2006.286.04:22:11.68#ibcon#*mode == 0, iclass 20, count 2 2006.286.04:22:11.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.04:22:11.68#ibcon#[27=AT07-04\r\n] 2006.286.04:22:11.68#ibcon#*before write, iclass 20, count 2 2006.286.04:22:11.68#ibcon#enter sib2, iclass 20, count 2 2006.286.04:22:11.68#ibcon#flushed, iclass 20, count 2 2006.286.04:22:11.68#ibcon#about to write, iclass 20, count 2 2006.286.04:22:11.68#ibcon#wrote, iclass 20, count 2 2006.286.04:22:11.68#ibcon#about to read 3, iclass 20, count 2 2006.286.04:22:11.71#ibcon#read 3, iclass 20, count 2 2006.286.04:22:11.71#ibcon#about to read 4, iclass 20, count 2 2006.286.04:22:11.71#ibcon#read 4, iclass 20, count 2 2006.286.04:22:11.71#ibcon#about to read 5, iclass 20, count 2 2006.286.04:22:11.71#ibcon#read 5, iclass 20, count 2 2006.286.04:22:11.71#ibcon#about to read 6, iclass 20, count 2 2006.286.04:22:11.71#ibcon#read 6, iclass 20, count 2 2006.286.04:22:11.71#ibcon#end of sib2, iclass 20, count 2 2006.286.04:22:11.71#ibcon#*after write, iclass 20, count 2 2006.286.04:22:11.71#ibcon#*before return 0, iclass 20, count 2 2006.286.04:22:11.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:22:11.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:22:11.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.04:22:11.71#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:11.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:22:11.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:22:11.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:22:11.83#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:22:11.83#ibcon#first serial, iclass 20, count 0 2006.286.04:22:11.83#ibcon#enter sib2, iclass 20, count 0 2006.286.04:22:11.83#ibcon#flushed, iclass 20, count 0 2006.286.04:22:11.83#ibcon#about to write, iclass 20, count 0 2006.286.04:22:11.83#ibcon#wrote, iclass 20, count 0 2006.286.04:22:11.83#ibcon#about to read 3, iclass 20, count 0 2006.286.04:22:11.85#ibcon#read 3, iclass 20, count 0 2006.286.04:22:11.85#ibcon#about to read 4, iclass 20, count 0 2006.286.04:22:11.85#ibcon#read 4, iclass 20, count 0 2006.286.04:22:11.85#ibcon#about to read 5, iclass 20, count 0 2006.286.04:22:11.85#ibcon#read 5, iclass 20, count 0 2006.286.04:22:11.85#ibcon#about to read 6, iclass 20, count 0 2006.286.04:22:11.85#ibcon#read 6, iclass 20, count 0 2006.286.04:22:11.85#ibcon#end of sib2, iclass 20, count 0 2006.286.04:22:11.85#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:22:11.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:22:11.85#ibcon#[27=USB\r\n] 2006.286.04:22:11.85#ibcon#*before write, iclass 20, count 0 2006.286.04:22:11.85#ibcon#enter sib2, iclass 20, count 0 2006.286.04:22:11.85#ibcon#flushed, iclass 20, count 0 2006.286.04:22:11.85#ibcon#about to write, iclass 20, count 0 2006.286.04:22:11.85#ibcon#wrote, iclass 20, count 0 2006.286.04:22:11.85#ibcon#about to read 3, iclass 20, count 0 2006.286.04:22:11.88#ibcon#read 3, iclass 20, count 0 2006.286.04:22:11.88#ibcon#about to read 4, iclass 20, count 0 2006.286.04:22:11.88#ibcon#read 4, iclass 20, count 0 2006.286.04:22:11.88#ibcon#about to read 5, iclass 20, count 0 2006.286.04:22:11.88#ibcon#read 5, iclass 20, count 0 2006.286.04:22:11.88#ibcon#about to read 6, iclass 20, count 0 2006.286.04:22:11.88#ibcon#read 6, iclass 20, count 0 2006.286.04:22:11.88#ibcon#end of sib2, iclass 20, count 0 2006.286.04:22:11.88#ibcon#*after write, iclass 20, count 0 2006.286.04:22:11.88#ibcon#*before return 0, iclass 20, count 0 2006.286.04:22:11.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:22:11.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:22:11.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:22:11.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:22:11.88$vck44/vblo=8,744.99 2006.286.04:22:11.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:22:11.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:22:11.88#ibcon#ireg 17 cls_cnt 0 2006.286.04:22:11.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:22:11.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:22:11.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:22:11.88#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:22:11.88#ibcon#first serial, iclass 22, count 0 2006.286.04:22:11.88#ibcon#enter sib2, iclass 22, count 0 2006.286.04:22:11.88#ibcon#flushed, iclass 22, count 0 2006.286.04:22:11.88#ibcon#about to write, iclass 22, count 0 2006.286.04:22:11.88#ibcon#wrote, iclass 22, count 0 2006.286.04:22:11.88#ibcon#about to read 3, iclass 22, count 0 2006.286.04:22:11.90#ibcon#read 3, iclass 22, count 0 2006.286.04:22:11.90#ibcon#about to read 4, iclass 22, count 0 2006.286.04:22:11.90#ibcon#read 4, iclass 22, count 0 2006.286.04:22:11.90#ibcon#about to read 5, iclass 22, count 0 2006.286.04:22:11.90#ibcon#read 5, iclass 22, count 0 2006.286.04:22:11.90#ibcon#about to read 6, iclass 22, count 0 2006.286.04:22:11.90#ibcon#read 6, iclass 22, count 0 2006.286.04:22:11.90#ibcon#end of sib2, iclass 22, count 0 2006.286.04:22:11.90#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:22:11.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:22:11.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:22:11.90#ibcon#*before write, iclass 22, count 0 2006.286.04:22:11.90#ibcon#enter sib2, iclass 22, count 0 2006.286.04:22:11.90#ibcon#flushed, iclass 22, count 0 2006.286.04:22:11.90#ibcon#about to write, iclass 22, count 0 2006.286.04:22:11.90#ibcon#wrote, iclass 22, count 0 2006.286.04:22:11.90#ibcon#about to read 3, iclass 22, count 0 2006.286.04:22:11.94#ibcon#read 3, iclass 22, count 0 2006.286.04:22:11.94#ibcon#about to read 4, iclass 22, count 0 2006.286.04:22:11.94#ibcon#read 4, iclass 22, count 0 2006.286.04:22:11.94#ibcon#about to read 5, iclass 22, count 0 2006.286.04:22:11.94#ibcon#read 5, iclass 22, count 0 2006.286.04:22:11.94#ibcon#about to read 6, iclass 22, count 0 2006.286.04:22:11.94#ibcon#read 6, iclass 22, count 0 2006.286.04:22:11.94#ibcon#end of sib2, iclass 22, count 0 2006.286.04:22:11.94#ibcon#*after write, iclass 22, count 0 2006.286.04:22:11.94#ibcon#*before return 0, iclass 22, count 0 2006.286.04:22:11.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:22:11.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:22:11.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:22:11.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:22:11.94$vck44/vb=8,4 2006.286.04:22:11.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.04:22:11.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.04:22:11.94#ibcon#ireg 11 cls_cnt 2 2006.286.04:22:11.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:22:12.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:22:12.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:22:12.00#ibcon#enter wrdev, iclass 24, count 2 2006.286.04:22:12.00#ibcon#first serial, iclass 24, count 2 2006.286.04:22:12.00#ibcon#enter sib2, iclass 24, count 2 2006.286.04:22:12.00#ibcon#flushed, iclass 24, count 2 2006.286.04:22:12.00#ibcon#about to write, iclass 24, count 2 2006.286.04:22:12.00#ibcon#wrote, iclass 24, count 2 2006.286.04:22:12.00#ibcon#about to read 3, iclass 24, count 2 2006.286.04:22:12.02#ibcon#read 3, iclass 24, count 2 2006.286.04:22:12.02#ibcon#about to read 4, iclass 24, count 2 2006.286.04:22:12.02#ibcon#read 4, iclass 24, count 2 2006.286.04:22:12.02#ibcon#about to read 5, iclass 24, count 2 2006.286.04:22:12.02#ibcon#read 5, iclass 24, count 2 2006.286.04:22:12.02#ibcon#about to read 6, iclass 24, count 2 2006.286.04:22:12.02#ibcon#read 6, iclass 24, count 2 2006.286.04:22:12.02#ibcon#end of sib2, iclass 24, count 2 2006.286.04:22:12.02#ibcon#*mode == 0, iclass 24, count 2 2006.286.04:22:12.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.04:22:12.02#ibcon#[27=AT08-04\r\n] 2006.286.04:22:12.02#ibcon#*before write, iclass 24, count 2 2006.286.04:22:12.02#ibcon#enter sib2, iclass 24, count 2 2006.286.04:22:12.02#ibcon#flushed, iclass 24, count 2 2006.286.04:22:12.02#ibcon#about to write, iclass 24, count 2 2006.286.04:22:12.02#ibcon#wrote, iclass 24, count 2 2006.286.04:22:12.02#ibcon#about to read 3, iclass 24, count 2 2006.286.04:22:12.05#ibcon#read 3, iclass 24, count 2 2006.286.04:22:12.05#ibcon#about to read 4, iclass 24, count 2 2006.286.04:22:12.05#ibcon#read 4, iclass 24, count 2 2006.286.04:22:12.05#ibcon#about to read 5, iclass 24, count 2 2006.286.04:22:12.05#ibcon#read 5, iclass 24, count 2 2006.286.04:22:12.05#ibcon#about to read 6, iclass 24, count 2 2006.286.04:22:12.05#ibcon#read 6, iclass 24, count 2 2006.286.04:22:12.05#ibcon#end of sib2, iclass 24, count 2 2006.286.04:22:12.05#ibcon#*after write, iclass 24, count 2 2006.286.04:22:12.05#ibcon#*before return 0, iclass 24, count 2 2006.286.04:22:12.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:22:12.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:22:12.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.04:22:12.05#ibcon#ireg 7 cls_cnt 0 2006.286.04:22:12.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:22:12.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:22:12.24#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:22:12.24#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:22:12.24#ibcon#first serial, iclass 24, count 0 2006.286.04:22:12.24#ibcon#enter sib2, iclass 24, count 0 2006.286.04:22:12.24#ibcon#flushed, iclass 24, count 0 2006.286.04:22:12.24#ibcon#about to write, iclass 24, count 0 2006.286.04:22:12.24#ibcon#wrote, iclass 24, count 0 2006.286.04:22:12.24#ibcon#about to read 3, iclass 24, count 0 2006.286.04:22:12.26#ibcon#read 3, iclass 24, count 0 2006.286.04:22:12.26#ibcon#about to read 4, iclass 24, count 0 2006.286.04:22:12.26#ibcon#read 4, iclass 24, count 0 2006.286.04:22:12.26#ibcon#about to read 5, iclass 24, count 0 2006.286.04:22:12.26#ibcon#read 5, iclass 24, count 0 2006.286.04:22:12.26#ibcon#about to read 6, iclass 24, count 0 2006.286.04:22:12.26#ibcon#read 6, iclass 24, count 0 2006.286.04:22:12.26#ibcon#end of sib2, iclass 24, count 0 2006.286.04:22:12.26#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:22:12.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:22:12.26#ibcon#[27=USB\r\n] 2006.286.04:22:12.26#ibcon#*before write, iclass 24, count 0 2006.286.04:22:12.26#ibcon#enter sib2, iclass 24, count 0 2006.286.04:22:12.26#ibcon#flushed, iclass 24, count 0 2006.286.04:22:12.26#ibcon#about to write, iclass 24, count 0 2006.286.04:22:12.26#ibcon#wrote, iclass 24, count 0 2006.286.04:22:12.26#ibcon#about to read 3, iclass 24, count 0 2006.286.04:22:12.29#ibcon#read 3, iclass 24, count 0 2006.286.04:22:12.29#ibcon#about to read 4, iclass 24, count 0 2006.286.04:22:12.29#ibcon#read 4, iclass 24, count 0 2006.286.04:22:12.29#ibcon#about to read 5, iclass 24, count 0 2006.286.04:22:12.29#ibcon#read 5, iclass 24, count 0 2006.286.04:22:12.29#ibcon#about to read 6, iclass 24, count 0 2006.286.04:22:12.29#ibcon#read 6, iclass 24, count 0 2006.286.04:22:12.29#ibcon#end of sib2, iclass 24, count 0 2006.286.04:22:12.29#ibcon#*after write, iclass 24, count 0 2006.286.04:22:12.29#ibcon#*before return 0, iclass 24, count 0 2006.286.04:22:12.29#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:22:12.29#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:22:12.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:22:12.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:22:12.29$vck44/vabw=wide 2006.286.04:22:12.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.04:22:12.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.04:22:12.29#ibcon#ireg 8 cls_cnt 0 2006.286.04:22:12.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:22:12.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:22:12.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:22:12.29#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:22:12.29#ibcon#first serial, iclass 26, count 0 2006.286.04:22:12.29#ibcon#enter sib2, iclass 26, count 0 2006.286.04:22:12.29#ibcon#flushed, iclass 26, count 0 2006.286.04:22:12.29#ibcon#about to write, iclass 26, count 0 2006.286.04:22:12.29#ibcon#wrote, iclass 26, count 0 2006.286.04:22:12.29#ibcon#about to read 3, iclass 26, count 0 2006.286.04:22:12.31#ibcon#read 3, iclass 26, count 0 2006.286.04:22:12.31#ibcon#about to read 4, iclass 26, count 0 2006.286.04:22:12.31#ibcon#read 4, iclass 26, count 0 2006.286.04:22:12.31#ibcon#about to read 5, iclass 26, count 0 2006.286.04:22:12.31#ibcon#read 5, iclass 26, count 0 2006.286.04:22:12.31#ibcon#about to read 6, iclass 26, count 0 2006.286.04:22:12.31#ibcon#read 6, iclass 26, count 0 2006.286.04:22:12.31#ibcon#end of sib2, iclass 26, count 0 2006.286.04:22:12.31#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:22:12.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:22:12.31#ibcon#[25=BW32\r\n] 2006.286.04:22:12.31#ibcon#*before write, iclass 26, count 0 2006.286.04:22:12.31#ibcon#enter sib2, iclass 26, count 0 2006.286.04:22:12.31#ibcon#flushed, iclass 26, count 0 2006.286.04:22:12.31#ibcon#about to write, iclass 26, count 0 2006.286.04:22:12.31#ibcon#wrote, iclass 26, count 0 2006.286.04:22:12.31#ibcon#about to read 3, iclass 26, count 0 2006.286.04:22:12.34#ibcon#read 3, iclass 26, count 0 2006.286.04:22:12.34#ibcon#about to read 4, iclass 26, count 0 2006.286.04:22:12.34#ibcon#read 4, iclass 26, count 0 2006.286.04:22:12.34#ibcon#about to read 5, iclass 26, count 0 2006.286.04:22:12.34#ibcon#read 5, iclass 26, count 0 2006.286.04:22:12.34#ibcon#about to read 6, iclass 26, count 0 2006.286.04:22:12.34#ibcon#read 6, iclass 26, count 0 2006.286.04:22:12.34#ibcon#end of sib2, iclass 26, count 0 2006.286.04:22:12.34#ibcon#*after write, iclass 26, count 0 2006.286.04:22:12.34#ibcon#*before return 0, iclass 26, count 0 2006.286.04:22:12.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:22:12.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:22:12.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:22:12.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:22:12.34$vck44/vbbw=wide 2006.286.04:22:12.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.04:22:12.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.04:22:12.34#ibcon#ireg 8 cls_cnt 0 2006.286.04:22:12.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:22:12.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:22:12.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:22:12.41#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:22:12.41#ibcon#first serial, iclass 28, count 0 2006.286.04:22:12.41#ibcon#enter sib2, iclass 28, count 0 2006.286.04:22:12.41#ibcon#flushed, iclass 28, count 0 2006.286.04:22:12.41#ibcon#about to write, iclass 28, count 0 2006.286.04:22:12.41#ibcon#wrote, iclass 28, count 0 2006.286.04:22:12.41#ibcon#about to read 3, iclass 28, count 0 2006.286.04:22:12.43#ibcon#read 3, iclass 28, count 0 2006.286.04:22:12.43#ibcon#about to read 4, iclass 28, count 0 2006.286.04:22:12.43#ibcon#read 4, iclass 28, count 0 2006.286.04:22:12.43#ibcon#about to read 5, iclass 28, count 0 2006.286.04:22:12.43#ibcon#read 5, iclass 28, count 0 2006.286.04:22:12.43#ibcon#about to read 6, iclass 28, count 0 2006.286.04:22:12.43#ibcon#read 6, iclass 28, count 0 2006.286.04:22:12.43#ibcon#end of sib2, iclass 28, count 0 2006.286.04:22:12.43#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:22:12.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:22:12.43#ibcon#[27=BW32\r\n] 2006.286.04:22:12.43#ibcon#*before write, iclass 28, count 0 2006.286.04:22:12.43#ibcon#enter sib2, iclass 28, count 0 2006.286.04:22:12.43#ibcon#flushed, iclass 28, count 0 2006.286.04:22:12.43#ibcon#about to write, iclass 28, count 0 2006.286.04:22:12.43#ibcon#wrote, iclass 28, count 0 2006.286.04:22:12.43#ibcon#about to read 3, iclass 28, count 0 2006.286.04:22:12.46#ibcon#read 3, iclass 28, count 0 2006.286.04:22:12.46#ibcon#about to read 4, iclass 28, count 0 2006.286.04:22:12.46#ibcon#read 4, iclass 28, count 0 2006.286.04:22:12.46#ibcon#about to read 5, iclass 28, count 0 2006.286.04:22:12.46#ibcon#read 5, iclass 28, count 0 2006.286.04:22:12.46#ibcon#about to read 6, iclass 28, count 0 2006.286.04:22:12.46#ibcon#read 6, iclass 28, count 0 2006.286.04:22:12.46#ibcon#end of sib2, iclass 28, count 0 2006.286.04:22:12.46#ibcon#*after write, iclass 28, count 0 2006.286.04:22:12.46#ibcon#*before return 0, iclass 28, count 0 2006.286.04:22:12.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:22:12.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:22:12.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:22:12.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:22:12.46$setupk4/ifdk4 2006.286.04:22:12.46$ifdk4/lo= 2006.286.04:22:12.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:22:12.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:22:12.46$ifdk4/patch= 2006.286.04:22:12.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:22:12.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:22:12.46$setupk4/!*+20s 2006.286.04:22:20.94#abcon#<5=/03 2.8 6.4 22.08 741014.8\r\n> 2006.286.04:22:20.96#abcon#{5=INTERFACE CLEAR} 2006.286.04:22:21.02#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:22:26.17$setupk4/"tpicd 2006.286.04:22:26.17$setupk4/echo=off 2006.286.04:22:26.17$setupk4/xlog=off 2006.286.04:22:26.17:!2006.286.04:24:27 2006.286.04:22:49.13#trakl#Source acquired 2006.286.04:22:49.13#flagr#flagr/antenna,acquired 2006.286.04:24:27.00:preob 2006.286.04:24:27.13/onsource/TRACKING 2006.286.04:24:27.13:!2006.286.04:24:37 2006.286.04:24:37.00:"tape 2006.286.04:24:37.00:"st=record 2006.286.04:24:37.00:data_valid=on 2006.286.04:24:37.00:midob 2006.286.04:24:37.13/onsource/TRACKING 2006.286.04:24:37.13/wx/22.10,1014.8,76 2006.286.04:24:37.32/cable/+6.4970E-03 2006.286.04:24:38.41/va/01,07,usb,yes,39,42 2006.286.04:24:38.41/va/02,06,usb,yes,39,40 2006.286.04:24:38.41/va/03,07,usb,yes,39,41 2006.286.04:24:38.41/va/04,06,usb,yes,41,43 2006.286.04:24:38.41/va/05,03,usb,yes,40,41 2006.286.04:24:38.41/va/06,04,usb,yes,36,36 2006.286.04:24:38.41/va/07,04,usb,yes,37,38 2006.286.04:24:38.41/va/08,03,usb,yes,38,46 2006.286.04:24:38.64/valo/01,524.99,yes,locked 2006.286.04:24:38.64/valo/02,534.99,yes,locked 2006.286.04:24:38.64/valo/03,564.99,yes,locked 2006.286.04:24:38.64/valo/04,624.99,yes,locked 2006.286.04:24:38.64/valo/05,734.99,yes,locked 2006.286.04:24:38.64/valo/06,814.99,yes,locked 2006.286.04:24:38.64/valo/07,864.99,yes,locked 2006.286.04:24:38.64/valo/08,884.99,yes,locked 2006.286.04:24:39.73/vb/01,04,usb,yes,46,98 2006.286.04:24:39.73/vb/02,05,usb,yes,31,96 2006.286.04:24:39.73/vb/03,04,usb,yes,32,77 2006.286.04:24:39.73/vb/04,05,usb,yes,31,30 2006.286.04:24:39.73/vb/05,04,usb,yes,30,32 2006.286.04:24:39.73/vb/06,03,usb,yes,42,37 2006.286.04:24:39.73/vb/07,04,usb,yes,33,33 2006.286.04:24:39.73/vb/08,04,usb,yes,30,34 2006.286.04:24:39.97/vblo/01,629.99,yes,locked 2006.286.04:24:39.97/vblo/02,634.99,yes,locked 2006.286.04:24:39.97/vblo/03,649.99,yes,locked 2006.286.04:24:39.97/vblo/04,679.99,yes,locked 2006.286.04:24:39.97/vblo/05,709.99,yes,locked 2006.286.04:24:39.97/vblo/06,719.99,yes,locked 2006.286.04:24:39.97/vblo/07,734.99,yes,locked 2006.286.04:24:39.97/vblo/08,744.99,yes,locked 2006.286.04:24:40.12/vabw/8 2006.286.04:24:40.27/vbbw/8 2006.286.04:24:40.36/xfe/off,on,12.2 2006.286.04:24:40.74/ifatt/23,28,28,28 2006.286.04:24:41.07/fmout-gps/S +2.80E-07 2006.286.04:24:41.09:!2006.286.04:27:27 2006.286.04:27:27.02:data_valid=off 2006.286.04:27:27.02:"et 2006.286.04:27:27.02:!+3s 2006.286.04:27:30.04:"tape 2006.286.04:27:30.05:postob 2006.286.04:27:30.27/cable/+6.4954E-03 2006.286.04:27:30.28/wx/22.15,1014.8,74 2006.286.04:27:30.33/fmout-gps/S +2.77E-07 2006.286.04:27:30.34:scan_name=286-0429,jd0610,40 2006.286.04:27:30.34:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.286.04:27:31.15#flagr#flagr/antenna,new-source 2006.286.04:27:31.15:checkk5 2006.286.04:27:32.02/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:27:32.50/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:27:32.88/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:27:33.37/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:27:33.82/chk_obsdata//k5ts1/T2860424??a.dat file size is correct (nominal:680MB, actual:676MB). 2006.286.04:27:34.16/chk_obsdata//k5ts2/T2860424??b.dat file size is correct (nominal:680MB, actual:676MB). 2006.286.04:27:34.71/chk_obsdata//k5ts3/T2860424??c.dat file size is correct (nominal:680MB, actual:676MB). 2006.286.04:27:35.10/chk_obsdata//k5ts4/T2860424??d.dat file size is correct (nominal:680MB, actual:676MB). 2006.286.04:27:35.98/k5log//k5ts1_log_newline 2006.286.04:27:36.68/k5log//k5ts2_log_newline 2006.286.04:27:37.73/k5log//k5ts3_log_newline 2006.286.04:27:38.57/k5log//k5ts4_log_newline 2006.286.04:27:38.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:27:38.60:setupk4=1 2006.286.04:27:38.60$setupk4/echo=on 2006.286.04:27:38.60$setupk4/pcalon 2006.286.04:27:38.60$pcalon/"no phase cal control is implemented here 2006.286.04:27:38.60$setupk4/"tpicd=stop 2006.286.04:27:38.60$setupk4/"rec=synch_on 2006.286.04:27:38.60$setupk4/"rec_mode=128 2006.286.04:27:38.60$setupk4/!* 2006.286.04:27:38.60$setupk4/recpk4 2006.286.04:27:38.60$recpk4/recpatch= 2006.286.04:27:38.60$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:27:38.60$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:27:38.60$setupk4/vck44 2006.286.04:27:38.60$vck44/valo=1,524.99 2006.286.04:27:38.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.04:27:38.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.04:27:38.60#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:38.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:27:38.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:27:38.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:27:38.60#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:27:38.60#ibcon#first serial, iclass 6, count 0 2006.286.04:27:38.60#ibcon#enter sib2, iclass 6, count 0 2006.286.04:27:38.60#ibcon#flushed, iclass 6, count 0 2006.286.04:27:38.60#ibcon#about to write, iclass 6, count 0 2006.286.04:27:38.60#ibcon#wrote, iclass 6, count 0 2006.286.04:27:38.60#ibcon#about to read 3, iclass 6, count 0 2006.286.04:27:38.61#ibcon#read 3, iclass 6, count 0 2006.286.04:27:38.61#ibcon#about to read 4, iclass 6, count 0 2006.286.04:27:38.61#ibcon#read 4, iclass 6, count 0 2006.286.04:27:38.61#ibcon#about to read 5, iclass 6, count 0 2006.286.04:27:38.61#ibcon#read 5, iclass 6, count 0 2006.286.04:27:38.61#ibcon#about to read 6, iclass 6, count 0 2006.286.04:27:38.61#ibcon#read 6, iclass 6, count 0 2006.286.04:27:38.61#ibcon#end of sib2, iclass 6, count 0 2006.286.04:27:38.61#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:27:38.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:27:38.61#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:27:38.61#ibcon#*before write, iclass 6, count 0 2006.286.04:27:38.61#ibcon#enter sib2, iclass 6, count 0 2006.286.04:27:38.61#ibcon#flushed, iclass 6, count 0 2006.286.04:27:38.61#ibcon#about to write, iclass 6, count 0 2006.286.04:27:38.61#ibcon#wrote, iclass 6, count 0 2006.286.04:27:38.61#ibcon#about to read 3, iclass 6, count 0 2006.286.04:27:38.66#ibcon#read 3, iclass 6, count 0 2006.286.04:27:38.66#ibcon#about to read 4, iclass 6, count 0 2006.286.04:27:38.66#ibcon#read 4, iclass 6, count 0 2006.286.04:27:38.66#ibcon#about to read 5, iclass 6, count 0 2006.286.04:27:38.66#ibcon#read 5, iclass 6, count 0 2006.286.04:27:38.66#ibcon#about to read 6, iclass 6, count 0 2006.286.04:27:38.66#ibcon#read 6, iclass 6, count 0 2006.286.04:27:38.66#ibcon#end of sib2, iclass 6, count 0 2006.286.04:27:38.66#ibcon#*after write, iclass 6, count 0 2006.286.04:27:38.66#ibcon#*before return 0, iclass 6, count 0 2006.286.04:27:38.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:27:38.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:27:38.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:27:38.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:27:38.66$vck44/va=1,7 2006.286.04:27:38.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.04:27:38.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.04:27:38.67#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:38.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:27:38.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:27:38.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:27:38.67#ibcon#enter wrdev, iclass 10, count 2 2006.286.04:27:38.67#ibcon#first serial, iclass 10, count 2 2006.286.04:27:38.67#ibcon#enter sib2, iclass 10, count 2 2006.286.04:27:38.67#ibcon#flushed, iclass 10, count 2 2006.286.04:27:38.67#ibcon#about to write, iclass 10, count 2 2006.286.04:27:38.67#ibcon#wrote, iclass 10, count 2 2006.286.04:27:38.67#ibcon#about to read 3, iclass 10, count 2 2006.286.04:27:38.68#ibcon#read 3, iclass 10, count 2 2006.286.04:27:38.68#ibcon#about to read 4, iclass 10, count 2 2006.286.04:27:38.68#ibcon#read 4, iclass 10, count 2 2006.286.04:27:38.68#ibcon#about to read 5, iclass 10, count 2 2006.286.04:27:38.68#ibcon#read 5, iclass 10, count 2 2006.286.04:27:38.68#ibcon#about to read 6, iclass 10, count 2 2006.286.04:27:38.68#ibcon#read 6, iclass 10, count 2 2006.286.04:27:38.68#ibcon#end of sib2, iclass 10, count 2 2006.286.04:27:38.68#ibcon#*mode == 0, iclass 10, count 2 2006.286.04:27:38.68#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.04:27:38.68#ibcon#[25=AT01-07\r\n] 2006.286.04:27:38.68#ibcon#*before write, iclass 10, count 2 2006.286.04:27:38.68#ibcon#enter sib2, iclass 10, count 2 2006.286.04:27:38.68#ibcon#flushed, iclass 10, count 2 2006.286.04:27:38.68#ibcon#about to write, iclass 10, count 2 2006.286.04:27:38.68#ibcon#wrote, iclass 10, count 2 2006.286.04:27:38.68#ibcon#about to read 3, iclass 10, count 2 2006.286.04:27:38.71#ibcon#read 3, iclass 10, count 2 2006.286.04:27:38.71#ibcon#about to read 4, iclass 10, count 2 2006.286.04:27:38.71#ibcon#read 4, iclass 10, count 2 2006.286.04:27:38.71#ibcon#about to read 5, iclass 10, count 2 2006.286.04:27:38.71#ibcon#read 5, iclass 10, count 2 2006.286.04:27:38.71#ibcon#about to read 6, iclass 10, count 2 2006.286.04:27:38.71#ibcon#read 6, iclass 10, count 2 2006.286.04:27:38.71#ibcon#end of sib2, iclass 10, count 2 2006.286.04:27:38.71#ibcon#*after write, iclass 10, count 2 2006.286.04:27:38.71#ibcon#*before return 0, iclass 10, count 2 2006.286.04:27:38.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:27:38.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:27:38.71#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.04:27:38.71#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:38.71#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:27:38.83#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:27:38.83#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:27:38.83#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:27:38.83#ibcon#first serial, iclass 10, count 0 2006.286.04:27:38.83#ibcon#enter sib2, iclass 10, count 0 2006.286.04:27:38.83#ibcon#flushed, iclass 10, count 0 2006.286.04:27:38.83#ibcon#about to write, iclass 10, count 0 2006.286.04:27:38.83#ibcon#wrote, iclass 10, count 0 2006.286.04:27:38.83#ibcon#about to read 3, iclass 10, count 0 2006.286.04:27:38.85#ibcon#read 3, iclass 10, count 0 2006.286.04:27:38.85#ibcon#about to read 4, iclass 10, count 0 2006.286.04:27:38.85#ibcon#read 4, iclass 10, count 0 2006.286.04:27:38.85#ibcon#about to read 5, iclass 10, count 0 2006.286.04:27:38.85#ibcon#read 5, iclass 10, count 0 2006.286.04:27:38.85#ibcon#about to read 6, iclass 10, count 0 2006.286.04:27:38.85#ibcon#read 6, iclass 10, count 0 2006.286.04:27:38.85#ibcon#end of sib2, iclass 10, count 0 2006.286.04:27:38.85#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:27:38.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:27:38.85#ibcon#[25=USB\r\n] 2006.286.04:27:38.85#ibcon#*before write, iclass 10, count 0 2006.286.04:27:38.85#ibcon#enter sib2, iclass 10, count 0 2006.286.04:27:38.85#ibcon#flushed, iclass 10, count 0 2006.286.04:27:38.85#ibcon#about to write, iclass 10, count 0 2006.286.04:27:38.85#ibcon#wrote, iclass 10, count 0 2006.286.04:27:38.85#ibcon#about to read 3, iclass 10, count 0 2006.286.04:27:38.88#ibcon#read 3, iclass 10, count 0 2006.286.04:27:38.88#ibcon#about to read 4, iclass 10, count 0 2006.286.04:27:38.88#ibcon#read 4, iclass 10, count 0 2006.286.04:27:38.88#ibcon#about to read 5, iclass 10, count 0 2006.286.04:27:38.88#ibcon#read 5, iclass 10, count 0 2006.286.04:27:38.88#ibcon#about to read 6, iclass 10, count 0 2006.286.04:27:38.88#ibcon#read 6, iclass 10, count 0 2006.286.04:27:38.88#ibcon#end of sib2, iclass 10, count 0 2006.286.04:27:38.88#ibcon#*after write, iclass 10, count 0 2006.286.04:27:38.88#ibcon#*before return 0, iclass 10, count 0 2006.286.04:27:38.88#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:27:38.88#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:27:38.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:27:38.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:27:38.88$vck44/valo=2,534.99 2006.286.04:27:38.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.04:27:38.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.04:27:38.89#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:38.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:27:38.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:27:38.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:27:38.89#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:27:38.89#ibcon#first serial, iclass 12, count 0 2006.286.04:27:38.89#ibcon#enter sib2, iclass 12, count 0 2006.286.04:27:38.89#ibcon#flushed, iclass 12, count 0 2006.286.04:27:38.89#ibcon#about to write, iclass 12, count 0 2006.286.04:27:38.89#ibcon#wrote, iclass 12, count 0 2006.286.04:27:38.89#ibcon#about to read 3, iclass 12, count 0 2006.286.04:27:38.90#ibcon#read 3, iclass 12, count 0 2006.286.04:27:38.90#ibcon#about to read 4, iclass 12, count 0 2006.286.04:27:38.90#ibcon#read 4, iclass 12, count 0 2006.286.04:27:38.90#ibcon#about to read 5, iclass 12, count 0 2006.286.04:27:38.90#ibcon#read 5, iclass 12, count 0 2006.286.04:27:38.90#ibcon#about to read 6, iclass 12, count 0 2006.286.04:27:38.90#ibcon#read 6, iclass 12, count 0 2006.286.04:27:38.90#ibcon#end of sib2, iclass 12, count 0 2006.286.04:27:38.90#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:27:38.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:27:38.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:27:38.90#ibcon#*before write, iclass 12, count 0 2006.286.04:27:38.90#ibcon#enter sib2, iclass 12, count 0 2006.286.04:27:38.90#ibcon#flushed, iclass 12, count 0 2006.286.04:27:38.90#ibcon#about to write, iclass 12, count 0 2006.286.04:27:38.90#ibcon#wrote, iclass 12, count 0 2006.286.04:27:38.90#ibcon#about to read 3, iclass 12, count 0 2006.286.04:27:38.94#ibcon#read 3, iclass 12, count 0 2006.286.04:27:38.94#ibcon#about to read 4, iclass 12, count 0 2006.286.04:27:38.94#ibcon#read 4, iclass 12, count 0 2006.286.04:27:38.94#ibcon#about to read 5, iclass 12, count 0 2006.286.04:27:38.94#ibcon#read 5, iclass 12, count 0 2006.286.04:27:38.94#ibcon#about to read 6, iclass 12, count 0 2006.286.04:27:38.94#ibcon#read 6, iclass 12, count 0 2006.286.04:27:38.94#ibcon#end of sib2, iclass 12, count 0 2006.286.04:27:38.94#ibcon#*after write, iclass 12, count 0 2006.286.04:27:38.94#ibcon#*before return 0, iclass 12, count 0 2006.286.04:27:38.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:27:38.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:27:38.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:27:38.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:27:38.94$vck44/va=2,6 2006.286.04:27:38.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.04:27:38.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.04:27:38.95#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:38.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:27:38.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:27:38.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:27:38.99#ibcon#enter wrdev, iclass 14, count 2 2006.286.04:27:38.99#ibcon#first serial, iclass 14, count 2 2006.286.04:27:38.99#ibcon#enter sib2, iclass 14, count 2 2006.286.04:27:38.99#ibcon#flushed, iclass 14, count 2 2006.286.04:27:38.99#ibcon#about to write, iclass 14, count 2 2006.286.04:27:38.99#ibcon#wrote, iclass 14, count 2 2006.286.04:27:38.99#ibcon#about to read 3, iclass 14, count 2 2006.286.04:27:39.01#ibcon#read 3, iclass 14, count 2 2006.286.04:27:39.01#ibcon#about to read 4, iclass 14, count 2 2006.286.04:27:39.01#ibcon#read 4, iclass 14, count 2 2006.286.04:27:39.01#ibcon#about to read 5, iclass 14, count 2 2006.286.04:27:39.01#ibcon#read 5, iclass 14, count 2 2006.286.04:27:39.01#ibcon#about to read 6, iclass 14, count 2 2006.286.04:27:39.01#ibcon#read 6, iclass 14, count 2 2006.286.04:27:39.01#ibcon#end of sib2, iclass 14, count 2 2006.286.04:27:39.01#ibcon#*mode == 0, iclass 14, count 2 2006.286.04:27:39.01#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.04:27:39.01#ibcon#[25=AT02-06\r\n] 2006.286.04:27:39.01#ibcon#*before write, iclass 14, count 2 2006.286.04:27:39.01#ibcon#enter sib2, iclass 14, count 2 2006.286.04:27:39.01#ibcon#flushed, iclass 14, count 2 2006.286.04:27:39.01#ibcon#about to write, iclass 14, count 2 2006.286.04:27:39.01#ibcon#wrote, iclass 14, count 2 2006.286.04:27:39.01#ibcon#about to read 3, iclass 14, count 2 2006.286.04:27:39.03#abcon#<5=/04 3.4 7.2 22.15 751014.8\r\n> 2006.286.04:27:39.04#ibcon#read 3, iclass 14, count 2 2006.286.04:27:39.04#ibcon#about to read 4, iclass 14, count 2 2006.286.04:27:39.04#ibcon#read 4, iclass 14, count 2 2006.286.04:27:39.04#ibcon#about to read 5, iclass 14, count 2 2006.286.04:27:39.04#ibcon#read 5, iclass 14, count 2 2006.286.04:27:39.04#ibcon#about to read 6, iclass 14, count 2 2006.286.04:27:39.04#ibcon#read 6, iclass 14, count 2 2006.286.04:27:39.04#ibcon#end of sib2, iclass 14, count 2 2006.286.04:27:39.04#ibcon#*after write, iclass 14, count 2 2006.286.04:27:39.04#ibcon#*before return 0, iclass 14, count 2 2006.286.04:27:39.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:27:39.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:27:39.04#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.04:27:39.04#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:39.04#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:27:39.05#abcon#{5=INTERFACE CLEAR} 2006.286.04:27:39.11#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:27:39.16#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:27:39.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:27:39.16#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:27:39.16#ibcon#first serial, iclass 14, count 0 2006.286.04:27:39.16#ibcon#enter sib2, iclass 14, count 0 2006.286.04:27:39.16#ibcon#flushed, iclass 14, count 0 2006.286.04:27:39.16#ibcon#about to write, iclass 14, count 0 2006.286.04:27:39.16#ibcon#wrote, iclass 14, count 0 2006.286.04:27:39.16#ibcon#about to read 3, iclass 14, count 0 2006.286.04:27:39.18#ibcon#read 3, iclass 14, count 0 2006.286.04:27:39.18#ibcon#about to read 4, iclass 14, count 0 2006.286.04:27:39.18#ibcon#read 4, iclass 14, count 0 2006.286.04:27:39.18#ibcon#about to read 5, iclass 14, count 0 2006.286.04:27:39.18#ibcon#read 5, iclass 14, count 0 2006.286.04:27:39.18#ibcon#about to read 6, iclass 14, count 0 2006.286.04:27:39.18#ibcon#read 6, iclass 14, count 0 2006.286.04:27:39.18#ibcon#end of sib2, iclass 14, count 0 2006.286.04:27:39.18#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:27:39.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:27:39.18#ibcon#[25=USB\r\n] 2006.286.04:27:39.18#ibcon#*before write, iclass 14, count 0 2006.286.04:27:39.18#ibcon#enter sib2, iclass 14, count 0 2006.286.04:27:39.18#ibcon#flushed, iclass 14, count 0 2006.286.04:27:39.18#ibcon#about to write, iclass 14, count 0 2006.286.04:27:39.18#ibcon#wrote, iclass 14, count 0 2006.286.04:27:39.18#ibcon#about to read 3, iclass 14, count 0 2006.286.04:27:39.21#ibcon#read 3, iclass 14, count 0 2006.286.04:27:39.21#ibcon#about to read 4, iclass 14, count 0 2006.286.04:27:39.21#ibcon#read 4, iclass 14, count 0 2006.286.04:27:39.21#ibcon#about to read 5, iclass 14, count 0 2006.286.04:27:39.21#ibcon#read 5, iclass 14, count 0 2006.286.04:27:39.21#ibcon#about to read 6, iclass 14, count 0 2006.286.04:27:39.21#ibcon#read 6, iclass 14, count 0 2006.286.04:27:39.21#ibcon#end of sib2, iclass 14, count 0 2006.286.04:27:39.21#ibcon#*after write, iclass 14, count 0 2006.286.04:27:39.21#ibcon#*before return 0, iclass 14, count 0 2006.286.04:27:39.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:27:39.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:27:39.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:27:39.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:27:39.22$vck44/valo=3,564.99 2006.286.04:27:39.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.04:27:39.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.04:27:39.22#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:39.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:27:39.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:27:39.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:27:39.22#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:27:39.22#ibcon#first serial, iclass 20, count 0 2006.286.04:27:39.22#ibcon#enter sib2, iclass 20, count 0 2006.286.04:27:39.22#ibcon#flushed, iclass 20, count 0 2006.286.04:27:39.22#ibcon#about to write, iclass 20, count 0 2006.286.04:27:39.22#ibcon#wrote, iclass 20, count 0 2006.286.04:27:39.22#ibcon#about to read 3, iclass 20, count 0 2006.286.04:27:39.23#ibcon#read 3, iclass 20, count 0 2006.286.04:27:39.57#ibcon#about to read 4, iclass 20, count 0 2006.286.04:27:39.57#ibcon#read 4, iclass 20, count 0 2006.286.04:27:39.57#ibcon#about to read 5, iclass 20, count 0 2006.286.04:27:39.57#ibcon#read 5, iclass 20, count 0 2006.286.04:27:39.57#ibcon#about to read 6, iclass 20, count 0 2006.286.04:27:39.57#ibcon#read 6, iclass 20, count 0 2006.286.04:27:39.57#ibcon#end of sib2, iclass 20, count 0 2006.286.04:27:39.57#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:27:39.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:27:39.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:27:39.57#ibcon#*before write, iclass 20, count 0 2006.286.04:27:39.57#ibcon#enter sib2, iclass 20, count 0 2006.286.04:27:39.57#ibcon#flushed, iclass 20, count 0 2006.286.04:27:39.57#ibcon#about to write, iclass 20, count 0 2006.286.04:27:39.57#ibcon#wrote, iclass 20, count 0 2006.286.04:27:39.57#ibcon#about to read 3, iclass 20, count 0 2006.286.04:27:39.60#ibcon#read 3, iclass 20, count 0 2006.286.04:27:39.60#ibcon#about to read 4, iclass 20, count 0 2006.286.04:27:39.60#ibcon#read 4, iclass 20, count 0 2006.286.04:27:39.60#ibcon#about to read 5, iclass 20, count 0 2006.286.04:27:39.60#ibcon#read 5, iclass 20, count 0 2006.286.04:27:39.60#ibcon#about to read 6, iclass 20, count 0 2006.286.04:27:39.60#ibcon#read 6, iclass 20, count 0 2006.286.04:27:39.60#ibcon#end of sib2, iclass 20, count 0 2006.286.04:27:39.60#ibcon#*after write, iclass 20, count 0 2006.286.04:27:39.60#ibcon#*before return 0, iclass 20, count 0 2006.286.04:27:39.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:27:39.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:27:39.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:27:39.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:27:39.61$vck44/va=3,7 2006.286.04:27:39.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.04:27:39.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.04:27:39.61#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:39.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:27:39.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:27:39.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:27:39.61#ibcon#enter wrdev, iclass 22, count 2 2006.286.04:27:39.61#ibcon#first serial, iclass 22, count 2 2006.286.04:27:39.61#ibcon#enter sib2, iclass 22, count 2 2006.286.04:27:39.61#ibcon#flushed, iclass 22, count 2 2006.286.04:27:39.61#ibcon#about to write, iclass 22, count 2 2006.286.04:27:39.61#ibcon#wrote, iclass 22, count 2 2006.286.04:27:39.61#ibcon#about to read 3, iclass 22, count 2 2006.286.04:27:39.62#ibcon#read 3, iclass 22, count 2 2006.286.04:27:39.62#ibcon#about to read 4, iclass 22, count 2 2006.286.04:27:39.62#ibcon#read 4, iclass 22, count 2 2006.286.04:27:39.62#ibcon#about to read 5, iclass 22, count 2 2006.286.04:27:39.62#ibcon#read 5, iclass 22, count 2 2006.286.04:27:39.62#ibcon#about to read 6, iclass 22, count 2 2006.286.04:27:39.62#ibcon#read 6, iclass 22, count 2 2006.286.04:27:39.62#ibcon#end of sib2, iclass 22, count 2 2006.286.04:27:39.62#ibcon#*mode == 0, iclass 22, count 2 2006.286.04:27:39.62#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.04:27:39.62#ibcon#[25=AT03-07\r\n] 2006.286.04:27:39.62#ibcon#*before write, iclass 22, count 2 2006.286.04:27:39.62#ibcon#enter sib2, iclass 22, count 2 2006.286.04:27:39.62#ibcon#flushed, iclass 22, count 2 2006.286.04:27:39.62#ibcon#about to write, iclass 22, count 2 2006.286.04:27:39.62#ibcon#wrote, iclass 22, count 2 2006.286.04:27:39.62#ibcon#about to read 3, iclass 22, count 2 2006.286.04:27:39.65#ibcon#read 3, iclass 22, count 2 2006.286.04:27:39.65#ibcon#about to read 4, iclass 22, count 2 2006.286.04:27:39.65#ibcon#read 4, iclass 22, count 2 2006.286.04:27:39.65#ibcon#about to read 5, iclass 22, count 2 2006.286.04:27:39.65#ibcon#read 5, iclass 22, count 2 2006.286.04:27:39.65#ibcon#about to read 6, iclass 22, count 2 2006.286.04:27:39.65#ibcon#read 6, iclass 22, count 2 2006.286.04:27:39.65#ibcon#end of sib2, iclass 22, count 2 2006.286.04:27:39.65#ibcon#*after write, iclass 22, count 2 2006.286.04:27:39.65#ibcon#*before return 0, iclass 22, count 2 2006.286.04:27:39.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:27:39.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:27:39.65#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.04:27:39.65#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:39.65#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:27:39.77#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:27:39.77#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:27:39.77#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:27:39.77#ibcon#first serial, iclass 22, count 0 2006.286.04:27:39.77#ibcon#enter sib2, iclass 22, count 0 2006.286.04:27:39.77#ibcon#flushed, iclass 22, count 0 2006.286.04:27:39.77#ibcon#about to write, iclass 22, count 0 2006.286.04:27:39.77#ibcon#wrote, iclass 22, count 0 2006.286.04:27:39.77#ibcon#about to read 3, iclass 22, count 0 2006.286.04:27:39.79#ibcon#read 3, iclass 22, count 0 2006.286.04:27:39.79#ibcon#about to read 4, iclass 22, count 0 2006.286.04:27:39.79#ibcon#read 4, iclass 22, count 0 2006.286.04:27:39.79#ibcon#about to read 5, iclass 22, count 0 2006.286.04:27:39.79#ibcon#read 5, iclass 22, count 0 2006.286.04:27:39.79#ibcon#about to read 6, iclass 22, count 0 2006.286.04:27:39.79#ibcon#read 6, iclass 22, count 0 2006.286.04:27:39.79#ibcon#end of sib2, iclass 22, count 0 2006.286.04:27:39.79#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:27:39.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:27:39.79#ibcon#[25=USB\r\n] 2006.286.04:27:39.79#ibcon#*before write, iclass 22, count 0 2006.286.04:27:39.79#ibcon#enter sib2, iclass 22, count 0 2006.286.04:27:39.79#ibcon#flushed, iclass 22, count 0 2006.286.04:27:39.79#ibcon#about to write, iclass 22, count 0 2006.286.04:27:39.79#ibcon#wrote, iclass 22, count 0 2006.286.04:27:39.79#ibcon#about to read 3, iclass 22, count 0 2006.286.04:27:39.82#ibcon#read 3, iclass 22, count 0 2006.286.04:27:39.82#ibcon#about to read 4, iclass 22, count 0 2006.286.04:27:39.82#ibcon#read 4, iclass 22, count 0 2006.286.04:27:39.82#ibcon#about to read 5, iclass 22, count 0 2006.286.04:27:39.82#ibcon#read 5, iclass 22, count 0 2006.286.04:27:39.82#ibcon#about to read 6, iclass 22, count 0 2006.286.04:27:39.82#ibcon#read 6, iclass 22, count 0 2006.286.04:27:39.82#ibcon#end of sib2, iclass 22, count 0 2006.286.04:27:39.82#ibcon#*after write, iclass 22, count 0 2006.286.04:27:39.82#ibcon#*before return 0, iclass 22, count 0 2006.286.04:27:39.82#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:27:39.82#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:27:39.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:27:39.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:27:39.83$vck44/valo=4,624.99 2006.286.04:27:39.83#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.04:27:39.83#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.04:27:39.83#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:39.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:27:39.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:27:39.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:27:39.83#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:27:39.83#ibcon#first serial, iclass 24, count 0 2006.286.04:27:39.83#ibcon#enter sib2, iclass 24, count 0 2006.286.04:27:39.83#ibcon#flushed, iclass 24, count 0 2006.286.04:27:39.83#ibcon#about to write, iclass 24, count 0 2006.286.04:27:39.83#ibcon#wrote, iclass 24, count 0 2006.286.04:27:39.83#ibcon#about to read 3, iclass 24, count 0 2006.286.04:27:39.84#ibcon#read 3, iclass 24, count 0 2006.286.04:27:40.31#ibcon#about to read 4, iclass 24, count 0 2006.286.04:27:40.31#ibcon#read 4, iclass 24, count 0 2006.286.04:27:40.31#ibcon#about to read 5, iclass 24, count 0 2006.286.04:27:40.31#ibcon#read 5, iclass 24, count 0 2006.286.04:27:40.31#ibcon#about to read 6, iclass 24, count 0 2006.286.04:27:40.31#ibcon#read 6, iclass 24, count 0 2006.286.04:27:40.31#ibcon#end of sib2, iclass 24, count 0 2006.286.04:27:40.31#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:27:40.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:27:40.31#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:27:40.31#ibcon#*before write, iclass 24, count 0 2006.286.04:27:40.31#ibcon#enter sib2, iclass 24, count 0 2006.286.04:27:40.31#ibcon#flushed, iclass 24, count 0 2006.286.04:27:40.31#ibcon#about to write, iclass 24, count 0 2006.286.04:27:40.31#ibcon#wrote, iclass 24, count 0 2006.286.04:27:40.31#ibcon#about to read 3, iclass 24, count 0 2006.286.04:27:40.34#ibcon#read 3, iclass 24, count 0 2006.286.04:27:40.34#ibcon#about to read 4, iclass 24, count 0 2006.286.04:27:40.34#ibcon#read 4, iclass 24, count 0 2006.286.04:27:40.34#ibcon#about to read 5, iclass 24, count 0 2006.286.04:27:40.34#ibcon#read 5, iclass 24, count 0 2006.286.04:27:40.34#ibcon#about to read 6, iclass 24, count 0 2006.286.04:27:40.34#ibcon#read 6, iclass 24, count 0 2006.286.04:27:40.34#ibcon#end of sib2, iclass 24, count 0 2006.286.04:27:40.34#ibcon#*after write, iclass 24, count 0 2006.286.04:27:40.34#ibcon#*before return 0, iclass 24, count 0 2006.286.04:27:40.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:27:40.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:27:40.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:27:40.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:27:40.35$vck44/va=4,6 2006.286.04:27:40.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.04:27:40.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.04:27:40.35#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:40.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:27:40.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:27:40.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:27:40.35#ibcon#enter wrdev, iclass 26, count 2 2006.286.04:27:40.35#ibcon#first serial, iclass 26, count 2 2006.286.04:27:40.35#ibcon#enter sib2, iclass 26, count 2 2006.286.04:27:40.35#ibcon#flushed, iclass 26, count 2 2006.286.04:27:40.35#ibcon#about to write, iclass 26, count 2 2006.286.04:27:40.35#ibcon#wrote, iclass 26, count 2 2006.286.04:27:40.35#ibcon#about to read 3, iclass 26, count 2 2006.286.04:27:40.36#ibcon#read 3, iclass 26, count 2 2006.286.04:27:40.36#ibcon#about to read 4, iclass 26, count 2 2006.286.04:27:40.36#ibcon#read 4, iclass 26, count 2 2006.286.04:27:40.36#ibcon#about to read 5, iclass 26, count 2 2006.286.04:27:40.36#ibcon#read 5, iclass 26, count 2 2006.286.04:27:40.36#ibcon#about to read 6, iclass 26, count 2 2006.286.04:27:40.36#ibcon#read 6, iclass 26, count 2 2006.286.04:27:40.36#ibcon#end of sib2, iclass 26, count 2 2006.286.04:27:40.36#ibcon#*mode == 0, iclass 26, count 2 2006.286.04:27:40.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.04:27:40.36#ibcon#[25=AT04-06\r\n] 2006.286.04:27:40.36#ibcon#*before write, iclass 26, count 2 2006.286.04:27:40.36#ibcon#enter sib2, iclass 26, count 2 2006.286.04:27:40.36#ibcon#flushed, iclass 26, count 2 2006.286.04:27:40.36#ibcon#about to write, iclass 26, count 2 2006.286.04:27:40.36#ibcon#wrote, iclass 26, count 2 2006.286.04:27:40.36#ibcon#about to read 3, iclass 26, count 2 2006.286.04:27:40.39#ibcon#read 3, iclass 26, count 2 2006.286.04:27:40.39#ibcon#about to read 4, iclass 26, count 2 2006.286.04:27:40.39#ibcon#read 4, iclass 26, count 2 2006.286.04:27:40.39#ibcon#about to read 5, iclass 26, count 2 2006.286.04:27:40.39#ibcon#read 5, iclass 26, count 2 2006.286.04:27:40.39#ibcon#about to read 6, iclass 26, count 2 2006.286.04:27:40.39#ibcon#read 6, iclass 26, count 2 2006.286.04:27:40.39#ibcon#end of sib2, iclass 26, count 2 2006.286.04:27:40.39#ibcon#*after write, iclass 26, count 2 2006.286.04:27:40.39#ibcon#*before return 0, iclass 26, count 2 2006.286.04:27:40.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:27:40.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:27:40.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.04:27:40.39#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:40.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:27:40.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:27:40.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:27:40.51#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:27:40.51#ibcon#first serial, iclass 26, count 0 2006.286.04:27:40.51#ibcon#enter sib2, iclass 26, count 0 2006.286.04:27:40.51#ibcon#flushed, iclass 26, count 0 2006.286.04:27:40.51#ibcon#about to write, iclass 26, count 0 2006.286.04:27:40.51#ibcon#wrote, iclass 26, count 0 2006.286.04:27:40.51#ibcon#about to read 3, iclass 26, count 0 2006.286.04:27:40.53#ibcon#read 3, iclass 26, count 0 2006.286.04:27:40.53#ibcon#about to read 4, iclass 26, count 0 2006.286.04:27:40.53#ibcon#read 4, iclass 26, count 0 2006.286.04:27:40.53#ibcon#about to read 5, iclass 26, count 0 2006.286.04:27:40.53#ibcon#read 5, iclass 26, count 0 2006.286.04:27:40.53#ibcon#about to read 6, iclass 26, count 0 2006.286.04:27:40.53#ibcon#read 6, iclass 26, count 0 2006.286.04:27:40.53#ibcon#end of sib2, iclass 26, count 0 2006.286.04:27:40.53#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:27:40.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:27:40.53#ibcon#[25=USB\r\n] 2006.286.04:27:40.53#ibcon#*before write, iclass 26, count 0 2006.286.04:27:40.53#ibcon#enter sib2, iclass 26, count 0 2006.286.04:27:40.53#ibcon#flushed, iclass 26, count 0 2006.286.04:27:40.53#ibcon#about to write, iclass 26, count 0 2006.286.04:27:40.53#ibcon#wrote, iclass 26, count 0 2006.286.04:27:40.53#ibcon#about to read 3, iclass 26, count 0 2006.286.04:27:40.56#ibcon#read 3, iclass 26, count 0 2006.286.04:27:40.56#ibcon#about to read 4, iclass 26, count 0 2006.286.04:27:40.56#ibcon#read 4, iclass 26, count 0 2006.286.04:27:40.56#ibcon#about to read 5, iclass 26, count 0 2006.286.04:27:40.56#ibcon#read 5, iclass 26, count 0 2006.286.04:27:40.56#ibcon#about to read 6, iclass 26, count 0 2006.286.04:27:40.56#ibcon#read 6, iclass 26, count 0 2006.286.04:27:40.56#ibcon#end of sib2, iclass 26, count 0 2006.286.04:27:40.56#ibcon#*after write, iclass 26, count 0 2006.286.04:27:40.56#ibcon#*before return 0, iclass 26, count 0 2006.286.04:27:40.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:27:40.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:27:40.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:27:40.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:27:40.57$vck44/valo=5,734.99 2006.286.04:27:40.57#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.04:27:40.57#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.04:27:40.57#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:40.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:27:40.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:27:40.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:27:40.57#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:27:40.57#ibcon#first serial, iclass 28, count 0 2006.286.04:27:40.57#ibcon#enter sib2, iclass 28, count 0 2006.286.04:27:40.57#ibcon#flushed, iclass 28, count 0 2006.286.04:27:40.57#ibcon#about to write, iclass 28, count 0 2006.286.04:27:40.57#ibcon#wrote, iclass 28, count 0 2006.286.04:27:40.57#ibcon#about to read 3, iclass 28, count 0 2006.286.04:27:40.58#ibcon#read 3, iclass 28, count 0 2006.286.04:27:40.59#ibcon#about to read 4, iclass 28, count 0 2006.286.04:27:40.59#ibcon#read 4, iclass 28, count 0 2006.286.04:27:40.59#ibcon#about to read 5, iclass 28, count 0 2006.286.04:27:40.59#ibcon#read 5, iclass 28, count 0 2006.286.04:27:40.59#ibcon#about to read 6, iclass 28, count 0 2006.286.04:27:40.59#ibcon#read 6, iclass 28, count 0 2006.286.04:27:40.59#ibcon#end of sib2, iclass 28, count 0 2006.286.04:27:40.59#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:27:40.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:27:40.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:27:40.59#ibcon#*before write, iclass 28, count 0 2006.286.04:27:40.59#ibcon#enter sib2, iclass 28, count 0 2006.286.04:27:40.59#ibcon#flushed, iclass 28, count 0 2006.286.04:27:40.59#ibcon#about to write, iclass 28, count 0 2006.286.04:27:40.59#ibcon#wrote, iclass 28, count 0 2006.286.04:27:40.59#ibcon#about to read 3, iclass 28, count 0 2006.286.04:27:40.63#ibcon#read 3, iclass 28, count 0 2006.286.04:27:40.63#ibcon#about to read 4, iclass 28, count 0 2006.286.04:27:40.63#ibcon#read 4, iclass 28, count 0 2006.286.04:27:40.63#ibcon#about to read 5, iclass 28, count 0 2006.286.04:27:40.63#ibcon#read 5, iclass 28, count 0 2006.286.04:27:40.63#ibcon#about to read 6, iclass 28, count 0 2006.286.04:27:40.63#ibcon#read 6, iclass 28, count 0 2006.286.04:27:40.63#ibcon#end of sib2, iclass 28, count 0 2006.286.04:27:40.63#ibcon#*after write, iclass 28, count 0 2006.286.04:27:40.63#ibcon#*before return 0, iclass 28, count 0 2006.286.04:27:40.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:27:40.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:27:40.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:27:40.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:27:40.64$vck44/va=5,3 2006.286.04:27:40.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.04:27:40.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.04:27:40.64#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:40.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:27:40.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:27:40.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:27:40.67#ibcon#enter wrdev, iclass 30, count 2 2006.286.04:27:40.67#ibcon#first serial, iclass 30, count 2 2006.286.04:27:40.67#ibcon#enter sib2, iclass 30, count 2 2006.286.04:27:40.67#ibcon#flushed, iclass 30, count 2 2006.286.04:27:40.67#ibcon#about to write, iclass 30, count 2 2006.286.04:27:40.67#ibcon#wrote, iclass 30, count 2 2006.286.04:27:40.67#ibcon#about to read 3, iclass 30, count 2 2006.286.04:27:40.69#ibcon#read 3, iclass 30, count 2 2006.286.04:27:40.69#ibcon#about to read 4, iclass 30, count 2 2006.286.04:27:40.69#ibcon#read 4, iclass 30, count 2 2006.286.04:27:40.69#ibcon#about to read 5, iclass 30, count 2 2006.286.04:27:40.69#ibcon#read 5, iclass 30, count 2 2006.286.04:27:40.69#ibcon#about to read 6, iclass 30, count 2 2006.286.04:27:40.69#ibcon#read 6, iclass 30, count 2 2006.286.04:27:40.69#ibcon#end of sib2, iclass 30, count 2 2006.286.04:27:40.69#ibcon#*mode == 0, iclass 30, count 2 2006.286.04:27:40.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.04:27:40.69#ibcon#[25=AT05-03\r\n] 2006.286.04:27:40.69#ibcon#*before write, iclass 30, count 2 2006.286.04:27:40.69#ibcon#enter sib2, iclass 30, count 2 2006.286.04:27:40.69#ibcon#flushed, iclass 30, count 2 2006.286.04:27:40.69#ibcon#about to write, iclass 30, count 2 2006.286.04:27:40.69#ibcon#wrote, iclass 30, count 2 2006.286.04:27:40.69#ibcon#about to read 3, iclass 30, count 2 2006.286.04:27:40.72#ibcon#read 3, iclass 30, count 2 2006.286.04:27:40.72#ibcon#about to read 4, iclass 30, count 2 2006.286.04:27:40.72#ibcon#read 4, iclass 30, count 2 2006.286.04:27:40.72#ibcon#about to read 5, iclass 30, count 2 2006.286.04:27:40.72#ibcon#read 5, iclass 30, count 2 2006.286.04:27:40.72#ibcon#about to read 6, iclass 30, count 2 2006.286.04:27:40.72#ibcon#read 6, iclass 30, count 2 2006.286.04:27:40.72#ibcon#end of sib2, iclass 30, count 2 2006.286.04:27:40.72#ibcon#*after write, iclass 30, count 2 2006.286.04:27:40.72#ibcon#*before return 0, iclass 30, count 2 2006.286.04:27:40.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:27:40.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:27:40.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.04:27:40.72#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:40.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:27:40.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:27:40.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:27:40.84#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:27:40.84#ibcon#first serial, iclass 30, count 0 2006.286.04:27:40.84#ibcon#enter sib2, iclass 30, count 0 2006.286.04:27:40.84#ibcon#flushed, iclass 30, count 0 2006.286.04:27:40.84#ibcon#about to write, iclass 30, count 0 2006.286.04:27:40.84#ibcon#wrote, iclass 30, count 0 2006.286.04:27:40.84#ibcon#about to read 3, iclass 30, count 0 2006.286.04:27:40.86#ibcon#read 3, iclass 30, count 0 2006.286.04:27:40.86#ibcon#about to read 4, iclass 30, count 0 2006.286.04:27:40.86#ibcon#read 4, iclass 30, count 0 2006.286.04:27:40.86#ibcon#about to read 5, iclass 30, count 0 2006.286.04:27:40.86#ibcon#read 5, iclass 30, count 0 2006.286.04:27:40.86#ibcon#about to read 6, iclass 30, count 0 2006.286.04:27:40.86#ibcon#read 6, iclass 30, count 0 2006.286.04:27:40.86#ibcon#end of sib2, iclass 30, count 0 2006.286.04:27:40.86#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:27:40.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:27:40.86#ibcon#[25=USB\r\n] 2006.286.04:27:40.86#ibcon#*before write, iclass 30, count 0 2006.286.04:27:40.86#ibcon#enter sib2, iclass 30, count 0 2006.286.04:27:40.86#ibcon#flushed, iclass 30, count 0 2006.286.04:27:40.86#ibcon#about to write, iclass 30, count 0 2006.286.04:27:40.86#ibcon#wrote, iclass 30, count 0 2006.286.04:27:40.86#ibcon#about to read 3, iclass 30, count 0 2006.286.04:27:40.89#ibcon#read 3, iclass 30, count 0 2006.286.04:27:40.89#ibcon#about to read 4, iclass 30, count 0 2006.286.04:27:40.89#ibcon#read 4, iclass 30, count 0 2006.286.04:27:40.89#ibcon#about to read 5, iclass 30, count 0 2006.286.04:27:40.89#ibcon#read 5, iclass 30, count 0 2006.286.04:27:40.89#ibcon#about to read 6, iclass 30, count 0 2006.286.04:27:40.89#ibcon#read 6, iclass 30, count 0 2006.286.04:27:40.89#ibcon#end of sib2, iclass 30, count 0 2006.286.04:27:40.89#ibcon#*after write, iclass 30, count 0 2006.286.04:27:40.89#ibcon#*before return 0, iclass 30, count 0 2006.286.04:27:40.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:27:40.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:27:40.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:27:40.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:27:40.89$vck44/valo=6,814.99 2006.286.04:27:40.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.04:27:40.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.04:27:40.90#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:40.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:27:40.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:27:40.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:27:40.90#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:27:40.90#ibcon#first serial, iclass 32, count 0 2006.286.04:27:40.90#ibcon#enter sib2, iclass 32, count 0 2006.286.04:27:40.90#ibcon#flushed, iclass 32, count 0 2006.286.04:27:40.90#ibcon#about to write, iclass 32, count 0 2006.286.04:27:40.90#ibcon#wrote, iclass 32, count 0 2006.286.04:27:40.90#ibcon#about to read 3, iclass 32, count 0 2006.286.04:27:40.91#ibcon#read 3, iclass 32, count 0 2006.286.04:27:40.91#ibcon#about to read 4, iclass 32, count 0 2006.286.04:27:40.91#ibcon#read 4, iclass 32, count 0 2006.286.04:27:40.91#ibcon#about to read 5, iclass 32, count 0 2006.286.04:27:40.91#ibcon#read 5, iclass 32, count 0 2006.286.04:27:40.91#ibcon#about to read 6, iclass 32, count 0 2006.286.04:27:40.91#ibcon#read 6, iclass 32, count 0 2006.286.04:27:40.91#ibcon#end of sib2, iclass 32, count 0 2006.286.04:27:40.91#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:27:40.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:27:40.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:27:40.91#ibcon#*before write, iclass 32, count 0 2006.286.04:27:40.91#ibcon#enter sib2, iclass 32, count 0 2006.286.04:27:40.91#ibcon#flushed, iclass 32, count 0 2006.286.04:27:40.91#ibcon#about to write, iclass 32, count 0 2006.286.04:27:40.91#ibcon#wrote, iclass 32, count 0 2006.286.04:27:40.91#ibcon#about to read 3, iclass 32, count 0 2006.286.04:27:40.95#ibcon#read 3, iclass 32, count 0 2006.286.04:27:40.95#ibcon#about to read 4, iclass 32, count 0 2006.286.04:27:40.95#ibcon#read 4, iclass 32, count 0 2006.286.04:27:40.95#ibcon#about to read 5, iclass 32, count 0 2006.286.04:27:40.95#ibcon#read 5, iclass 32, count 0 2006.286.04:27:40.95#ibcon#about to read 6, iclass 32, count 0 2006.286.04:27:40.95#ibcon#read 6, iclass 32, count 0 2006.286.04:27:40.95#ibcon#end of sib2, iclass 32, count 0 2006.286.04:27:40.95#ibcon#*after write, iclass 32, count 0 2006.286.04:27:40.95#ibcon#*before return 0, iclass 32, count 0 2006.286.04:27:40.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:27:40.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:27:40.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:27:40.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:27:40.95$vck44/va=6,4 2006.286.04:27:40.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.04:27:40.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.04:27:40.96#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:40.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:27:41.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:27:41.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:27:41.00#ibcon#enter wrdev, iclass 34, count 2 2006.286.04:27:41.00#ibcon#first serial, iclass 34, count 2 2006.286.04:27:41.00#ibcon#enter sib2, iclass 34, count 2 2006.286.04:27:41.00#ibcon#flushed, iclass 34, count 2 2006.286.04:27:41.00#ibcon#about to write, iclass 34, count 2 2006.286.04:27:41.00#ibcon#wrote, iclass 34, count 2 2006.286.04:27:41.00#ibcon#about to read 3, iclass 34, count 2 2006.286.04:27:41.02#ibcon#read 3, iclass 34, count 2 2006.286.04:27:41.02#ibcon#about to read 4, iclass 34, count 2 2006.286.04:27:41.02#ibcon#read 4, iclass 34, count 2 2006.286.04:27:41.02#ibcon#about to read 5, iclass 34, count 2 2006.286.04:27:41.02#ibcon#read 5, iclass 34, count 2 2006.286.04:27:41.02#ibcon#about to read 6, iclass 34, count 2 2006.286.04:27:41.02#ibcon#read 6, iclass 34, count 2 2006.286.04:27:41.02#ibcon#end of sib2, iclass 34, count 2 2006.286.04:27:41.02#ibcon#*mode == 0, iclass 34, count 2 2006.286.04:27:41.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.04:27:41.02#ibcon#[25=AT06-04\r\n] 2006.286.04:27:41.02#ibcon#*before write, iclass 34, count 2 2006.286.04:27:41.02#ibcon#enter sib2, iclass 34, count 2 2006.286.04:27:41.02#ibcon#flushed, iclass 34, count 2 2006.286.04:27:41.02#ibcon#about to write, iclass 34, count 2 2006.286.04:27:41.02#ibcon#wrote, iclass 34, count 2 2006.286.04:27:41.02#ibcon#about to read 3, iclass 34, count 2 2006.286.04:27:41.05#ibcon#read 3, iclass 34, count 2 2006.286.04:27:41.05#ibcon#about to read 4, iclass 34, count 2 2006.286.04:27:41.05#ibcon#read 4, iclass 34, count 2 2006.286.04:27:41.05#ibcon#about to read 5, iclass 34, count 2 2006.286.04:27:41.05#ibcon#read 5, iclass 34, count 2 2006.286.04:27:41.05#ibcon#about to read 6, iclass 34, count 2 2006.286.04:27:41.05#ibcon#read 6, iclass 34, count 2 2006.286.04:27:41.05#ibcon#end of sib2, iclass 34, count 2 2006.286.04:27:41.05#ibcon#*after write, iclass 34, count 2 2006.286.04:27:41.05#ibcon#*before return 0, iclass 34, count 2 2006.286.04:27:41.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:27:41.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:27:41.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.04:27:41.05#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:41.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:27:41.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:27:41.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:27:41.17#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:27:41.17#ibcon#first serial, iclass 34, count 0 2006.286.04:27:41.17#ibcon#enter sib2, iclass 34, count 0 2006.286.04:27:41.17#ibcon#flushed, iclass 34, count 0 2006.286.04:27:41.17#ibcon#about to write, iclass 34, count 0 2006.286.04:27:41.17#ibcon#wrote, iclass 34, count 0 2006.286.04:27:41.17#ibcon#about to read 3, iclass 34, count 0 2006.286.04:27:41.19#ibcon#read 3, iclass 34, count 0 2006.286.04:27:41.19#ibcon#about to read 4, iclass 34, count 0 2006.286.04:27:41.19#ibcon#read 4, iclass 34, count 0 2006.286.04:27:41.19#ibcon#about to read 5, iclass 34, count 0 2006.286.04:27:41.19#ibcon#read 5, iclass 34, count 0 2006.286.04:27:41.19#ibcon#about to read 6, iclass 34, count 0 2006.286.04:27:41.19#ibcon#read 6, iclass 34, count 0 2006.286.04:27:41.19#ibcon#end of sib2, iclass 34, count 0 2006.286.04:27:41.19#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:27:41.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:27:41.19#ibcon#[25=USB\r\n] 2006.286.04:27:41.19#ibcon#*before write, iclass 34, count 0 2006.286.04:27:41.19#ibcon#enter sib2, iclass 34, count 0 2006.286.04:27:41.19#ibcon#flushed, iclass 34, count 0 2006.286.04:27:41.19#ibcon#about to write, iclass 34, count 0 2006.286.04:27:41.19#ibcon#wrote, iclass 34, count 0 2006.286.04:27:41.19#ibcon#about to read 3, iclass 34, count 0 2006.286.04:27:41.22#ibcon#read 3, iclass 34, count 0 2006.286.04:27:41.22#ibcon#about to read 4, iclass 34, count 0 2006.286.04:27:41.22#ibcon#read 4, iclass 34, count 0 2006.286.04:27:41.22#ibcon#about to read 5, iclass 34, count 0 2006.286.04:27:41.22#ibcon#read 5, iclass 34, count 0 2006.286.04:27:41.22#ibcon#about to read 6, iclass 34, count 0 2006.286.04:27:41.22#ibcon#read 6, iclass 34, count 0 2006.286.04:27:41.22#ibcon#end of sib2, iclass 34, count 0 2006.286.04:27:41.22#ibcon#*after write, iclass 34, count 0 2006.286.04:27:41.22#ibcon#*before return 0, iclass 34, count 0 2006.286.04:27:41.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:27:41.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:27:41.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:27:41.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:27:41.23$vck44/valo=7,864.99 2006.286.04:27:41.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.04:27:41.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.04:27:41.23#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:41.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:27:41.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:27:41.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:27:41.23#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:27:41.23#ibcon#first serial, iclass 36, count 0 2006.286.04:27:41.23#ibcon#enter sib2, iclass 36, count 0 2006.286.04:27:41.23#ibcon#flushed, iclass 36, count 0 2006.286.04:27:41.23#ibcon#about to write, iclass 36, count 0 2006.286.04:27:41.23#ibcon#wrote, iclass 36, count 0 2006.286.04:27:41.23#ibcon#about to read 3, iclass 36, count 0 2006.286.04:27:41.24#ibcon#read 3, iclass 36, count 0 2006.286.04:27:41.24#ibcon#about to read 4, iclass 36, count 0 2006.286.04:27:41.24#ibcon#read 4, iclass 36, count 0 2006.286.04:27:41.24#ibcon#about to read 5, iclass 36, count 0 2006.286.04:27:41.24#ibcon#read 5, iclass 36, count 0 2006.286.04:27:41.24#ibcon#about to read 6, iclass 36, count 0 2006.286.04:27:41.24#ibcon#read 6, iclass 36, count 0 2006.286.04:27:41.24#ibcon#end of sib2, iclass 36, count 0 2006.286.04:27:41.24#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:27:41.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:27:41.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:27:41.24#ibcon#*before write, iclass 36, count 0 2006.286.04:27:41.24#ibcon#enter sib2, iclass 36, count 0 2006.286.04:27:41.24#ibcon#flushed, iclass 36, count 0 2006.286.04:27:41.24#ibcon#about to write, iclass 36, count 0 2006.286.04:27:41.24#ibcon#wrote, iclass 36, count 0 2006.286.04:27:41.24#ibcon#about to read 3, iclass 36, count 0 2006.286.04:27:41.28#ibcon#read 3, iclass 36, count 0 2006.286.04:27:41.28#ibcon#about to read 4, iclass 36, count 0 2006.286.04:27:41.28#ibcon#read 4, iclass 36, count 0 2006.286.04:27:41.28#ibcon#about to read 5, iclass 36, count 0 2006.286.04:27:41.28#ibcon#read 5, iclass 36, count 0 2006.286.04:27:41.28#ibcon#about to read 6, iclass 36, count 0 2006.286.04:27:41.28#ibcon#read 6, iclass 36, count 0 2006.286.04:27:41.28#ibcon#end of sib2, iclass 36, count 0 2006.286.04:27:41.28#ibcon#*after write, iclass 36, count 0 2006.286.04:27:41.28#ibcon#*before return 0, iclass 36, count 0 2006.286.04:27:41.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:27:41.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:27:41.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:27:41.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:27:41.29$vck44/va=7,4 2006.286.04:27:41.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.04:27:41.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.04:27:41.29#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:41.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:27:41.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:27:41.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:27:41.33#ibcon#enter wrdev, iclass 38, count 2 2006.286.04:27:41.33#ibcon#first serial, iclass 38, count 2 2006.286.04:27:41.33#ibcon#enter sib2, iclass 38, count 2 2006.286.04:27:41.33#ibcon#flushed, iclass 38, count 2 2006.286.04:27:41.33#ibcon#about to write, iclass 38, count 2 2006.286.04:27:41.33#ibcon#wrote, iclass 38, count 2 2006.286.04:27:41.33#ibcon#about to read 3, iclass 38, count 2 2006.286.04:27:41.35#ibcon#read 3, iclass 38, count 2 2006.286.04:27:41.35#ibcon#about to read 4, iclass 38, count 2 2006.286.04:27:41.35#ibcon#read 4, iclass 38, count 2 2006.286.04:27:41.35#ibcon#about to read 5, iclass 38, count 2 2006.286.04:27:41.35#ibcon#read 5, iclass 38, count 2 2006.286.04:27:41.35#ibcon#about to read 6, iclass 38, count 2 2006.286.04:27:41.35#ibcon#read 6, iclass 38, count 2 2006.286.04:27:41.35#ibcon#end of sib2, iclass 38, count 2 2006.286.04:27:41.35#ibcon#*mode == 0, iclass 38, count 2 2006.286.04:27:41.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.04:27:41.35#ibcon#[25=AT07-04\r\n] 2006.286.04:27:41.35#ibcon#*before write, iclass 38, count 2 2006.286.04:27:41.35#ibcon#enter sib2, iclass 38, count 2 2006.286.04:27:41.35#ibcon#flushed, iclass 38, count 2 2006.286.04:27:41.35#ibcon#about to write, iclass 38, count 2 2006.286.04:27:41.35#ibcon#wrote, iclass 38, count 2 2006.286.04:27:41.35#ibcon#about to read 3, iclass 38, count 2 2006.286.04:27:41.38#ibcon#read 3, iclass 38, count 2 2006.286.04:27:41.38#ibcon#about to read 4, iclass 38, count 2 2006.286.04:27:41.38#ibcon#read 4, iclass 38, count 2 2006.286.04:27:41.38#ibcon#about to read 5, iclass 38, count 2 2006.286.04:27:41.38#ibcon#read 5, iclass 38, count 2 2006.286.04:27:41.38#ibcon#about to read 6, iclass 38, count 2 2006.286.04:27:41.38#ibcon#read 6, iclass 38, count 2 2006.286.04:27:41.38#ibcon#end of sib2, iclass 38, count 2 2006.286.04:27:41.38#ibcon#*after write, iclass 38, count 2 2006.286.04:27:41.38#ibcon#*before return 0, iclass 38, count 2 2006.286.04:27:41.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:27:41.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:27:41.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.04:27:41.38#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:41.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:27:41.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:27:41.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:27:41.50#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:27:41.50#ibcon#first serial, iclass 38, count 0 2006.286.04:27:41.50#ibcon#enter sib2, iclass 38, count 0 2006.286.04:27:41.50#ibcon#flushed, iclass 38, count 0 2006.286.04:27:41.50#ibcon#about to write, iclass 38, count 0 2006.286.04:27:41.50#ibcon#wrote, iclass 38, count 0 2006.286.04:27:41.50#ibcon#about to read 3, iclass 38, count 0 2006.286.04:27:41.52#ibcon#read 3, iclass 38, count 0 2006.286.04:27:41.52#ibcon#about to read 4, iclass 38, count 0 2006.286.04:27:41.52#ibcon#read 4, iclass 38, count 0 2006.286.04:27:41.52#ibcon#about to read 5, iclass 38, count 0 2006.286.04:27:41.52#ibcon#read 5, iclass 38, count 0 2006.286.04:27:41.52#ibcon#about to read 6, iclass 38, count 0 2006.286.04:27:41.52#ibcon#read 6, iclass 38, count 0 2006.286.04:27:41.52#ibcon#end of sib2, iclass 38, count 0 2006.286.04:27:41.52#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:27:41.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:27:41.52#ibcon#[25=USB\r\n] 2006.286.04:27:41.52#ibcon#*before write, iclass 38, count 0 2006.286.04:27:41.52#ibcon#enter sib2, iclass 38, count 0 2006.286.04:27:41.52#ibcon#flushed, iclass 38, count 0 2006.286.04:27:41.52#ibcon#about to write, iclass 38, count 0 2006.286.04:27:41.52#ibcon#wrote, iclass 38, count 0 2006.286.04:27:41.52#ibcon#about to read 3, iclass 38, count 0 2006.286.04:27:41.55#ibcon#read 3, iclass 38, count 0 2006.286.04:27:41.55#ibcon#about to read 4, iclass 38, count 0 2006.286.04:27:41.55#ibcon#read 4, iclass 38, count 0 2006.286.04:27:41.55#ibcon#about to read 5, iclass 38, count 0 2006.286.04:27:41.55#ibcon#read 5, iclass 38, count 0 2006.286.04:27:41.55#ibcon#about to read 6, iclass 38, count 0 2006.286.04:27:41.55#ibcon#read 6, iclass 38, count 0 2006.286.04:27:41.55#ibcon#end of sib2, iclass 38, count 0 2006.286.04:27:41.55#ibcon#*after write, iclass 38, count 0 2006.286.04:27:41.55#ibcon#*before return 0, iclass 38, count 0 2006.286.04:27:41.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:27:41.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:27:41.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:27:41.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:27:41.56$vck44/valo=8,884.99 2006.286.04:27:41.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.04:27:41.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.04:27:41.56#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:41.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:27:41.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:27:41.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:27:41.56#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:27:41.56#ibcon#first serial, iclass 40, count 0 2006.286.04:27:41.56#ibcon#enter sib2, iclass 40, count 0 2006.286.04:27:41.56#ibcon#flushed, iclass 40, count 0 2006.286.04:27:41.56#ibcon#about to write, iclass 40, count 0 2006.286.04:27:41.56#ibcon#wrote, iclass 40, count 0 2006.286.04:27:41.56#ibcon#about to read 3, iclass 40, count 0 2006.286.04:27:41.57#ibcon#read 3, iclass 40, count 0 2006.286.04:27:41.57#ibcon#about to read 4, iclass 40, count 0 2006.286.04:27:41.57#ibcon#read 4, iclass 40, count 0 2006.286.04:27:41.57#ibcon#about to read 5, iclass 40, count 0 2006.286.04:27:41.57#ibcon#read 5, iclass 40, count 0 2006.286.04:27:41.57#ibcon#about to read 6, iclass 40, count 0 2006.286.04:27:41.57#ibcon#read 6, iclass 40, count 0 2006.286.04:27:41.57#ibcon#end of sib2, iclass 40, count 0 2006.286.04:27:41.57#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:27:41.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:27:41.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:27:41.57#ibcon#*before write, iclass 40, count 0 2006.286.04:27:41.57#ibcon#enter sib2, iclass 40, count 0 2006.286.04:27:41.57#ibcon#flushed, iclass 40, count 0 2006.286.04:27:41.57#ibcon#about to write, iclass 40, count 0 2006.286.04:27:41.57#ibcon#wrote, iclass 40, count 0 2006.286.04:27:41.57#ibcon#about to read 3, iclass 40, count 0 2006.286.04:27:41.61#ibcon#read 3, iclass 40, count 0 2006.286.04:27:41.61#ibcon#about to read 4, iclass 40, count 0 2006.286.04:27:41.61#ibcon#read 4, iclass 40, count 0 2006.286.04:27:41.61#ibcon#about to read 5, iclass 40, count 0 2006.286.04:27:41.61#ibcon#read 5, iclass 40, count 0 2006.286.04:27:41.61#ibcon#about to read 6, iclass 40, count 0 2006.286.04:27:41.61#ibcon#read 6, iclass 40, count 0 2006.286.04:27:41.61#ibcon#end of sib2, iclass 40, count 0 2006.286.04:27:41.61#ibcon#*after write, iclass 40, count 0 2006.286.04:27:41.61#ibcon#*before return 0, iclass 40, count 0 2006.286.04:27:41.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:27:41.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:27:41.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:27:41.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:27:41.62$vck44/va=8,3 2006.286.04:27:41.62#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.04:27:41.62#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.04:27:41.62#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:41.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:27:41.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:27:41.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:27:41.66#ibcon#enter wrdev, iclass 4, count 2 2006.286.04:27:41.66#ibcon#first serial, iclass 4, count 2 2006.286.04:27:41.66#ibcon#enter sib2, iclass 4, count 2 2006.286.04:27:41.66#ibcon#flushed, iclass 4, count 2 2006.286.04:27:41.66#ibcon#about to write, iclass 4, count 2 2006.286.04:27:41.66#ibcon#wrote, iclass 4, count 2 2006.286.04:27:41.66#ibcon#about to read 3, iclass 4, count 2 2006.286.04:27:41.68#ibcon#read 3, iclass 4, count 2 2006.286.04:27:41.68#ibcon#about to read 4, iclass 4, count 2 2006.286.04:27:41.68#ibcon#read 4, iclass 4, count 2 2006.286.04:27:41.68#ibcon#about to read 5, iclass 4, count 2 2006.286.04:27:41.68#ibcon#read 5, iclass 4, count 2 2006.286.04:27:41.68#ibcon#about to read 6, iclass 4, count 2 2006.286.04:27:41.68#ibcon#read 6, iclass 4, count 2 2006.286.04:27:41.68#ibcon#end of sib2, iclass 4, count 2 2006.286.04:27:41.68#ibcon#*mode == 0, iclass 4, count 2 2006.286.04:27:41.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.04:27:41.68#ibcon#[25=AT08-03\r\n] 2006.286.04:27:41.68#ibcon#*before write, iclass 4, count 2 2006.286.04:27:41.68#ibcon#enter sib2, iclass 4, count 2 2006.286.04:27:41.68#ibcon#flushed, iclass 4, count 2 2006.286.04:27:41.68#ibcon#about to write, iclass 4, count 2 2006.286.04:27:41.68#ibcon#wrote, iclass 4, count 2 2006.286.04:27:41.68#ibcon#about to read 3, iclass 4, count 2 2006.286.04:27:41.71#ibcon#read 3, iclass 4, count 2 2006.286.04:27:41.71#ibcon#about to read 4, iclass 4, count 2 2006.286.04:27:41.71#ibcon#read 4, iclass 4, count 2 2006.286.04:27:41.71#ibcon#about to read 5, iclass 4, count 2 2006.286.04:27:41.71#ibcon#read 5, iclass 4, count 2 2006.286.04:27:41.71#ibcon#about to read 6, iclass 4, count 2 2006.286.04:27:41.71#ibcon#read 6, iclass 4, count 2 2006.286.04:27:41.71#ibcon#end of sib2, iclass 4, count 2 2006.286.04:27:41.71#ibcon#*after write, iclass 4, count 2 2006.286.04:27:41.71#ibcon#*before return 0, iclass 4, count 2 2006.286.04:27:41.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:27:41.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:27:41.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.04:27:41.71#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:41.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:27:41.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:27:41.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:27:41.83#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:27:41.83#ibcon#first serial, iclass 4, count 0 2006.286.04:27:41.83#ibcon#enter sib2, iclass 4, count 0 2006.286.04:27:41.83#ibcon#flushed, iclass 4, count 0 2006.286.04:27:41.83#ibcon#about to write, iclass 4, count 0 2006.286.04:27:41.83#ibcon#wrote, iclass 4, count 0 2006.286.04:27:41.83#ibcon#about to read 3, iclass 4, count 0 2006.286.04:27:41.85#ibcon#read 3, iclass 4, count 0 2006.286.04:27:41.85#ibcon#about to read 4, iclass 4, count 0 2006.286.04:27:41.85#ibcon#read 4, iclass 4, count 0 2006.286.04:27:41.85#ibcon#about to read 5, iclass 4, count 0 2006.286.04:27:41.85#ibcon#read 5, iclass 4, count 0 2006.286.04:27:41.85#ibcon#about to read 6, iclass 4, count 0 2006.286.04:27:41.85#ibcon#read 6, iclass 4, count 0 2006.286.04:27:41.85#ibcon#end of sib2, iclass 4, count 0 2006.286.04:27:41.85#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:27:41.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:27:41.85#ibcon#[25=USB\r\n] 2006.286.04:27:41.85#ibcon#*before write, iclass 4, count 0 2006.286.04:27:41.85#ibcon#enter sib2, iclass 4, count 0 2006.286.04:27:41.85#ibcon#flushed, iclass 4, count 0 2006.286.04:27:41.85#ibcon#about to write, iclass 4, count 0 2006.286.04:27:41.85#ibcon#wrote, iclass 4, count 0 2006.286.04:27:41.85#ibcon#about to read 3, iclass 4, count 0 2006.286.04:27:41.88#ibcon#read 3, iclass 4, count 0 2006.286.04:27:41.88#ibcon#about to read 4, iclass 4, count 0 2006.286.04:27:41.88#ibcon#read 4, iclass 4, count 0 2006.286.04:27:41.88#ibcon#about to read 5, iclass 4, count 0 2006.286.04:27:41.88#ibcon#read 5, iclass 4, count 0 2006.286.04:27:41.88#ibcon#about to read 6, iclass 4, count 0 2006.286.04:27:41.88#ibcon#read 6, iclass 4, count 0 2006.286.04:27:41.88#ibcon#end of sib2, iclass 4, count 0 2006.286.04:27:41.88#ibcon#*after write, iclass 4, count 0 2006.286.04:27:41.88#ibcon#*before return 0, iclass 4, count 0 2006.286.04:27:41.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:27:41.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:27:41.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:27:41.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:27:41.88$vck44/vblo=1,629.99 2006.286.04:27:41.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.04:27:41.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.04:27:41.89#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:41.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:27:41.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:27:41.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:27:41.89#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:27:41.89#ibcon#first serial, iclass 6, count 0 2006.286.04:27:41.89#ibcon#enter sib2, iclass 6, count 0 2006.286.04:27:41.89#ibcon#flushed, iclass 6, count 0 2006.286.04:27:41.89#ibcon#about to write, iclass 6, count 0 2006.286.04:27:41.89#ibcon#wrote, iclass 6, count 0 2006.286.04:27:41.89#ibcon#about to read 3, iclass 6, count 0 2006.286.04:27:41.90#ibcon#read 3, iclass 6, count 0 2006.286.04:27:41.90#ibcon#about to read 4, iclass 6, count 0 2006.286.04:27:41.90#ibcon#read 4, iclass 6, count 0 2006.286.04:27:41.90#ibcon#about to read 5, iclass 6, count 0 2006.286.04:27:41.90#ibcon#read 5, iclass 6, count 0 2006.286.04:27:41.90#ibcon#about to read 6, iclass 6, count 0 2006.286.04:27:41.90#ibcon#read 6, iclass 6, count 0 2006.286.04:27:41.90#ibcon#end of sib2, iclass 6, count 0 2006.286.04:27:41.90#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:27:41.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:27:41.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:27:41.90#ibcon#*before write, iclass 6, count 0 2006.286.04:27:41.90#ibcon#enter sib2, iclass 6, count 0 2006.286.04:27:41.90#ibcon#flushed, iclass 6, count 0 2006.286.04:27:41.90#ibcon#about to write, iclass 6, count 0 2006.286.04:27:41.90#ibcon#wrote, iclass 6, count 0 2006.286.04:27:41.90#ibcon#about to read 3, iclass 6, count 0 2006.286.04:27:41.94#ibcon#read 3, iclass 6, count 0 2006.286.04:27:41.94#ibcon#about to read 4, iclass 6, count 0 2006.286.04:27:41.94#ibcon#read 4, iclass 6, count 0 2006.286.04:27:41.94#ibcon#about to read 5, iclass 6, count 0 2006.286.04:27:41.94#ibcon#read 5, iclass 6, count 0 2006.286.04:27:41.94#ibcon#about to read 6, iclass 6, count 0 2006.286.04:27:41.94#ibcon#read 6, iclass 6, count 0 2006.286.04:27:41.94#ibcon#end of sib2, iclass 6, count 0 2006.286.04:27:41.94#ibcon#*after write, iclass 6, count 0 2006.286.04:27:41.94#ibcon#*before return 0, iclass 6, count 0 2006.286.04:27:41.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:27:41.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:27:41.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:27:41.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:27:41.94$vck44/vb=1,4 2006.286.04:27:41.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.04:27:41.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.04:27:41.95#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:41.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:27:41.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:27:41.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:27:41.95#ibcon#enter wrdev, iclass 10, count 2 2006.286.04:27:41.95#ibcon#first serial, iclass 10, count 2 2006.286.04:27:41.95#ibcon#enter sib2, iclass 10, count 2 2006.286.04:27:41.95#ibcon#flushed, iclass 10, count 2 2006.286.04:27:41.95#ibcon#about to write, iclass 10, count 2 2006.286.04:27:41.95#ibcon#wrote, iclass 10, count 2 2006.286.04:27:41.95#ibcon#about to read 3, iclass 10, count 2 2006.286.04:27:41.96#ibcon#read 3, iclass 10, count 2 2006.286.04:27:41.96#ibcon#about to read 4, iclass 10, count 2 2006.286.04:27:41.96#ibcon#read 4, iclass 10, count 2 2006.286.04:27:41.96#ibcon#about to read 5, iclass 10, count 2 2006.286.04:27:41.96#ibcon#read 5, iclass 10, count 2 2006.286.04:27:41.96#ibcon#about to read 6, iclass 10, count 2 2006.286.04:27:41.96#ibcon#read 6, iclass 10, count 2 2006.286.04:27:41.96#ibcon#end of sib2, iclass 10, count 2 2006.286.04:27:41.96#ibcon#*mode == 0, iclass 10, count 2 2006.286.04:27:41.96#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.04:27:41.96#ibcon#[27=AT01-04\r\n] 2006.286.04:27:41.96#ibcon#*before write, iclass 10, count 2 2006.286.04:27:41.96#ibcon#enter sib2, iclass 10, count 2 2006.286.04:27:41.96#ibcon#flushed, iclass 10, count 2 2006.286.04:27:41.96#ibcon#about to write, iclass 10, count 2 2006.286.04:27:41.96#ibcon#wrote, iclass 10, count 2 2006.286.04:27:41.96#ibcon#about to read 3, iclass 10, count 2 2006.286.04:27:41.99#ibcon#read 3, iclass 10, count 2 2006.286.04:27:41.99#ibcon#about to read 4, iclass 10, count 2 2006.286.04:27:41.99#ibcon#read 4, iclass 10, count 2 2006.286.04:27:41.99#ibcon#about to read 5, iclass 10, count 2 2006.286.04:27:41.99#ibcon#read 5, iclass 10, count 2 2006.286.04:27:41.99#ibcon#about to read 6, iclass 10, count 2 2006.286.04:27:41.99#ibcon#read 6, iclass 10, count 2 2006.286.04:27:41.99#ibcon#end of sib2, iclass 10, count 2 2006.286.04:27:41.99#ibcon#*after write, iclass 10, count 2 2006.286.04:27:41.99#ibcon#*before return 0, iclass 10, count 2 2006.286.04:27:41.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:27:41.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:27:41.99#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.04:27:41.99#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:41.99#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:27:42.11#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:27:42.11#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:27:42.11#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:27:42.11#ibcon#first serial, iclass 10, count 0 2006.286.04:27:42.11#ibcon#enter sib2, iclass 10, count 0 2006.286.04:27:42.11#ibcon#flushed, iclass 10, count 0 2006.286.04:27:42.11#ibcon#about to write, iclass 10, count 0 2006.286.04:27:42.11#ibcon#wrote, iclass 10, count 0 2006.286.04:27:42.11#ibcon#about to read 3, iclass 10, count 0 2006.286.04:27:42.13#ibcon#read 3, iclass 10, count 0 2006.286.04:27:42.13#ibcon#about to read 4, iclass 10, count 0 2006.286.04:27:42.13#ibcon#read 4, iclass 10, count 0 2006.286.04:27:42.13#ibcon#about to read 5, iclass 10, count 0 2006.286.04:27:42.13#ibcon#read 5, iclass 10, count 0 2006.286.04:27:42.13#ibcon#about to read 6, iclass 10, count 0 2006.286.04:27:42.13#ibcon#read 6, iclass 10, count 0 2006.286.04:27:42.13#ibcon#end of sib2, iclass 10, count 0 2006.286.04:27:42.13#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:27:42.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:27:42.13#ibcon#[27=USB\r\n] 2006.286.04:27:42.13#ibcon#*before write, iclass 10, count 0 2006.286.04:27:42.13#ibcon#enter sib2, iclass 10, count 0 2006.286.04:27:42.13#ibcon#flushed, iclass 10, count 0 2006.286.04:27:42.13#ibcon#about to write, iclass 10, count 0 2006.286.04:27:42.13#ibcon#wrote, iclass 10, count 0 2006.286.04:27:42.13#ibcon#about to read 3, iclass 10, count 0 2006.286.04:27:42.16#ibcon#read 3, iclass 10, count 0 2006.286.04:27:42.16#ibcon#about to read 4, iclass 10, count 0 2006.286.04:27:42.16#ibcon#read 4, iclass 10, count 0 2006.286.04:27:42.16#ibcon#about to read 5, iclass 10, count 0 2006.286.04:27:42.16#ibcon#read 5, iclass 10, count 0 2006.286.04:27:42.16#ibcon#about to read 6, iclass 10, count 0 2006.286.04:27:42.16#ibcon#read 6, iclass 10, count 0 2006.286.04:27:42.16#ibcon#end of sib2, iclass 10, count 0 2006.286.04:27:42.16#ibcon#*after write, iclass 10, count 0 2006.286.04:27:42.16#ibcon#*before return 0, iclass 10, count 0 2006.286.04:27:42.16#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:27:42.16#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:27:42.16#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:27:42.16#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:27:42.16$vck44/vblo=2,634.99 2006.286.04:27:42.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.04:27:42.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.04:27:42.17#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:42.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:27:42.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:27:42.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:27:42.17#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:27:42.17#ibcon#first serial, iclass 12, count 0 2006.286.04:27:42.17#ibcon#enter sib2, iclass 12, count 0 2006.286.04:27:42.17#ibcon#flushed, iclass 12, count 0 2006.286.04:27:42.17#ibcon#about to write, iclass 12, count 0 2006.286.04:27:42.17#ibcon#wrote, iclass 12, count 0 2006.286.04:27:42.17#ibcon#about to read 3, iclass 12, count 0 2006.286.04:27:42.18#ibcon#read 3, iclass 12, count 0 2006.286.04:27:42.18#ibcon#about to read 4, iclass 12, count 0 2006.286.04:27:42.18#ibcon#read 4, iclass 12, count 0 2006.286.04:27:42.18#ibcon#about to read 5, iclass 12, count 0 2006.286.04:27:42.18#ibcon#read 5, iclass 12, count 0 2006.286.04:27:42.18#ibcon#about to read 6, iclass 12, count 0 2006.286.04:27:42.18#ibcon#read 6, iclass 12, count 0 2006.286.04:27:42.18#ibcon#end of sib2, iclass 12, count 0 2006.286.04:27:42.18#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:27:42.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:27:42.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:27:42.18#ibcon#*before write, iclass 12, count 0 2006.286.04:27:42.18#ibcon#enter sib2, iclass 12, count 0 2006.286.04:27:42.18#ibcon#flushed, iclass 12, count 0 2006.286.04:27:42.18#ibcon#about to write, iclass 12, count 0 2006.286.04:27:42.18#ibcon#wrote, iclass 12, count 0 2006.286.04:27:42.18#ibcon#about to read 3, iclass 12, count 0 2006.286.04:27:42.22#ibcon#read 3, iclass 12, count 0 2006.286.04:27:42.22#ibcon#about to read 4, iclass 12, count 0 2006.286.04:27:42.22#ibcon#read 4, iclass 12, count 0 2006.286.04:27:42.22#ibcon#about to read 5, iclass 12, count 0 2006.286.04:27:42.22#ibcon#read 5, iclass 12, count 0 2006.286.04:27:42.22#ibcon#about to read 6, iclass 12, count 0 2006.286.04:27:42.22#ibcon#read 6, iclass 12, count 0 2006.286.04:27:42.22#ibcon#end of sib2, iclass 12, count 0 2006.286.04:27:42.22#ibcon#*after write, iclass 12, count 0 2006.286.04:27:42.22#ibcon#*before return 0, iclass 12, count 0 2006.286.04:27:42.22#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:27:42.22#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:27:42.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:27:42.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:27:42.23$vck44/vb=2,5 2006.286.04:27:42.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.04:27:42.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.04:27:42.23#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:42.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:27:42.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:27:42.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:27:42.27#ibcon#enter wrdev, iclass 14, count 2 2006.286.04:27:42.27#ibcon#first serial, iclass 14, count 2 2006.286.04:27:42.27#ibcon#enter sib2, iclass 14, count 2 2006.286.04:27:42.27#ibcon#flushed, iclass 14, count 2 2006.286.04:27:42.27#ibcon#about to write, iclass 14, count 2 2006.286.04:27:42.27#ibcon#wrote, iclass 14, count 2 2006.286.04:27:42.27#ibcon#about to read 3, iclass 14, count 2 2006.286.04:27:42.29#ibcon#read 3, iclass 14, count 2 2006.286.04:27:42.29#ibcon#about to read 4, iclass 14, count 2 2006.286.04:27:42.29#ibcon#read 4, iclass 14, count 2 2006.286.04:27:42.29#ibcon#about to read 5, iclass 14, count 2 2006.286.04:27:42.29#ibcon#read 5, iclass 14, count 2 2006.286.04:27:42.29#ibcon#about to read 6, iclass 14, count 2 2006.286.04:27:42.29#ibcon#read 6, iclass 14, count 2 2006.286.04:27:42.29#ibcon#end of sib2, iclass 14, count 2 2006.286.04:27:42.29#ibcon#*mode == 0, iclass 14, count 2 2006.286.04:27:42.29#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.04:27:42.29#ibcon#[27=AT02-05\r\n] 2006.286.04:27:42.29#ibcon#*before write, iclass 14, count 2 2006.286.04:27:42.29#ibcon#enter sib2, iclass 14, count 2 2006.286.04:27:42.29#ibcon#flushed, iclass 14, count 2 2006.286.04:27:42.29#ibcon#about to write, iclass 14, count 2 2006.286.04:27:42.29#ibcon#wrote, iclass 14, count 2 2006.286.04:27:42.29#ibcon#about to read 3, iclass 14, count 2 2006.286.04:27:42.32#ibcon#read 3, iclass 14, count 2 2006.286.04:27:42.32#ibcon#about to read 4, iclass 14, count 2 2006.286.04:27:42.32#ibcon#read 4, iclass 14, count 2 2006.286.04:27:42.32#ibcon#about to read 5, iclass 14, count 2 2006.286.04:27:42.32#ibcon#read 5, iclass 14, count 2 2006.286.04:27:42.32#ibcon#about to read 6, iclass 14, count 2 2006.286.04:27:42.32#ibcon#read 6, iclass 14, count 2 2006.286.04:27:42.32#ibcon#end of sib2, iclass 14, count 2 2006.286.04:27:42.32#ibcon#*after write, iclass 14, count 2 2006.286.04:27:42.32#ibcon#*before return 0, iclass 14, count 2 2006.286.04:27:42.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:27:42.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:27:42.32#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.04:27:42.32#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:42.32#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:27:42.44#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:27:42.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:27:42.50#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:27:42.50#ibcon#first serial, iclass 14, count 0 2006.286.04:27:42.50#ibcon#enter sib2, iclass 14, count 0 2006.286.04:27:42.50#ibcon#flushed, iclass 14, count 0 2006.286.04:27:42.50#ibcon#about to write, iclass 14, count 0 2006.286.04:27:42.50#ibcon#wrote, iclass 14, count 0 2006.286.04:27:42.50#ibcon#about to read 3, iclass 14, count 0 2006.286.04:27:42.52#ibcon#read 3, iclass 14, count 0 2006.286.04:27:42.52#ibcon#about to read 4, iclass 14, count 0 2006.286.04:27:42.52#ibcon#read 4, iclass 14, count 0 2006.286.04:27:42.52#ibcon#about to read 5, iclass 14, count 0 2006.286.04:27:42.52#ibcon#read 5, iclass 14, count 0 2006.286.04:27:42.52#ibcon#about to read 6, iclass 14, count 0 2006.286.04:27:42.52#ibcon#read 6, iclass 14, count 0 2006.286.04:27:42.53#ibcon#end of sib2, iclass 14, count 0 2006.286.04:27:42.53#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:27:42.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:27:42.53#ibcon#[27=USB\r\n] 2006.286.04:27:42.53#ibcon#*before write, iclass 14, count 0 2006.286.04:27:42.53#ibcon#enter sib2, iclass 14, count 0 2006.286.04:27:42.53#ibcon#flushed, iclass 14, count 0 2006.286.04:27:42.53#ibcon#about to write, iclass 14, count 0 2006.286.04:27:42.53#ibcon#wrote, iclass 14, count 0 2006.286.04:27:42.53#ibcon#about to read 3, iclass 14, count 0 2006.286.04:27:42.55#ibcon#read 3, iclass 14, count 0 2006.286.04:27:42.55#ibcon#about to read 4, iclass 14, count 0 2006.286.04:27:42.55#ibcon#read 4, iclass 14, count 0 2006.286.04:27:42.55#ibcon#about to read 5, iclass 14, count 0 2006.286.04:27:42.55#ibcon#read 5, iclass 14, count 0 2006.286.04:27:42.55#ibcon#about to read 6, iclass 14, count 0 2006.286.04:27:42.55#ibcon#read 6, iclass 14, count 0 2006.286.04:27:42.56#ibcon#end of sib2, iclass 14, count 0 2006.286.04:27:42.56#ibcon#*after write, iclass 14, count 0 2006.286.04:27:42.56#ibcon#*before return 0, iclass 14, count 0 2006.286.04:27:42.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:27:42.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:27:42.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:27:42.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:27:42.56$vck44/vblo=3,649.99 2006.286.04:27:42.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.04:27:42.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.04:27:42.56#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:42.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:27:42.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:27:42.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:27:42.56#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:27:42.56#ibcon#first serial, iclass 16, count 0 2006.286.04:27:42.56#ibcon#enter sib2, iclass 16, count 0 2006.286.04:27:42.56#ibcon#flushed, iclass 16, count 0 2006.286.04:27:42.56#ibcon#about to write, iclass 16, count 0 2006.286.04:27:42.56#ibcon#wrote, iclass 16, count 0 2006.286.04:27:42.56#ibcon#about to read 3, iclass 16, count 0 2006.286.04:27:42.57#ibcon#read 3, iclass 16, count 0 2006.286.04:27:42.57#ibcon#about to read 4, iclass 16, count 0 2006.286.04:27:42.57#ibcon#read 4, iclass 16, count 0 2006.286.04:27:42.57#ibcon#about to read 5, iclass 16, count 0 2006.286.04:27:42.57#ibcon#read 5, iclass 16, count 0 2006.286.04:27:42.57#ibcon#about to read 6, iclass 16, count 0 2006.286.04:27:42.57#ibcon#read 6, iclass 16, count 0 2006.286.04:27:42.58#ibcon#end of sib2, iclass 16, count 0 2006.286.04:27:42.58#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:27:42.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:27:42.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:27:42.58#ibcon#*before write, iclass 16, count 0 2006.286.04:27:42.58#ibcon#enter sib2, iclass 16, count 0 2006.286.04:27:42.58#ibcon#flushed, iclass 16, count 0 2006.286.04:27:42.58#ibcon#about to write, iclass 16, count 0 2006.286.04:27:42.58#ibcon#wrote, iclass 16, count 0 2006.286.04:27:42.58#ibcon#about to read 3, iclass 16, count 0 2006.286.04:27:42.61#ibcon#read 3, iclass 16, count 0 2006.286.04:27:42.61#ibcon#about to read 4, iclass 16, count 0 2006.286.04:27:42.61#ibcon#read 4, iclass 16, count 0 2006.286.04:27:42.61#ibcon#about to read 5, iclass 16, count 0 2006.286.04:27:42.61#ibcon#read 5, iclass 16, count 0 2006.286.04:27:42.61#ibcon#about to read 6, iclass 16, count 0 2006.286.04:27:42.61#ibcon#read 6, iclass 16, count 0 2006.286.04:27:42.62#ibcon#end of sib2, iclass 16, count 0 2006.286.04:27:42.62#ibcon#*after write, iclass 16, count 0 2006.286.04:27:42.62#ibcon#*before return 0, iclass 16, count 0 2006.286.04:27:42.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:27:42.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:27:42.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:27:42.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:27:42.62$vck44/vb=3,4 2006.286.04:27:42.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.04:27:42.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.04:27:42.62#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:42.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:27:42.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:27:42.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:27:42.67#ibcon#enter wrdev, iclass 18, count 2 2006.286.04:27:42.67#ibcon#first serial, iclass 18, count 2 2006.286.04:27:42.67#ibcon#enter sib2, iclass 18, count 2 2006.286.04:27:42.67#ibcon#flushed, iclass 18, count 2 2006.286.04:27:42.67#ibcon#about to write, iclass 18, count 2 2006.286.04:27:42.68#ibcon#wrote, iclass 18, count 2 2006.286.04:27:42.68#ibcon#about to read 3, iclass 18, count 2 2006.286.04:27:42.69#ibcon#read 3, iclass 18, count 2 2006.286.04:27:42.69#ibcon#about to read 4, iclass 18, count 2 2006.286.04:27:42.69#ibcon#read 4, iclass 18, count 2 2006.286.04:27:42.69#ibcon#about to read 5, iclass 18, count 2 2006.286.04:27:42.69#ibcon#read 5, iclass 18, count 2 2006.286.04:27:42.69#ibcon#about to read 6, iclass 18, count 2 2006.286.04:27:42.69#ibcon#read 6, iclass 18, count 2 2006.286.04:27:42.70#ibcon#end of sib2, iclass 18, count 2 2006.286.04:27:42.70#ibcon#*mode == 0, iclass 18, count 2 2006.286.04:27:42.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.04:27:42.70#ibcon#[27=AT03-04\r\n] 2006.286.04:27:42.70#ibcon#*before write, iclass 18, count 2 2006.286.04:27:42.70#ibcon#enter sib2, iclass 18, count 2 2006.286.04:27:42.70#ibcon#flushed, iclass 18, count 2 2006.286.04:27:42.70#ibcon#about to write, iclass 18, count 2 2006.286.04:27:42.70#ibcon#wrote, iclass 18, count 2 2006.286.04:27:42.70#ibcon#about to read 3, iclass 18, count 2 2006.286.04:27:42.72#ibcon#read 3, iclass 18, count 2 2006.286.04:27:42.72#ibcon#about to read 4, iclass 18, count 2 2006.286.04:27:42.72#ibcon#read 4, iclass 18, count 2 2006.286.04:27:42.72#ibcon#about to read 5, iclass 18, count 2 2006.286.04:27:42.72#ibcon#read 5, iclass 18, count 2 2006.286.04:27:42.72#ibcon#about to read 6, iclass 18, count 2 2006.286.04:27:42.73#ibcon#read 6, iclass 18, count 2 2006.286.04:27:42.73#ibcon#end of sib2, iclass 18, count 2 2006.286.04:27:42.73#ibcon#*after write, iclass 18, count 2 2006.286.04:27:42.73#ibcon#*before return 0, iclass 18, count 2 2006.286.04:27:42.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:27:42.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:27:42.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.04:27:42.73#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:42.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:27:42.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:27:42.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:27:42.84#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:27:42.84#ibcon#first serial, iclass 18, count 0 2006.286.04:27:42.84#ibcon#enter sib2, iclass 18, count 0 2006.286.04:27:42.84#ibcon#flushed, iclass 18, count 0 2006.286.04:27:42.84#ibcon#about to write, iclass 18, count 0 2006.286.04:27:42.85#ibcon#wrote, iclass 18, count 0 2006.286.04:27:42.85#ibcon#about to read 3, iclass 18, count 0 2006.286.04:27:42.86#ibcon#read 3, iclass 18, count 0 2006.286.04:27:42.86#ibcon#about to read 4, iclass 18, count 0 2006.286.04:27:42.86#ibcon#read 4, iclass 18, count 0 2006.286.04:27:42.86#ibcon#about to read 5, iclass 18, count 0 2006.286.04:27:42.86#ibcon#read 5, iclass 18, count 0 2006.286.04:27:42.86#ibcon#about to read 6, iclass 18, count 0 2006.286.04:27:42.86#ibcon#read 6, iclass 18, count 0 2006.286.04:27:42.86#ibcon#end of sib2, iclass 18, count 0 2006.286.04:27:42.86#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:27:42.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:27:42.87#ibcon#[27=USB\r\n] 2006.286.04:27:42.87#ibcon#*before write, iclass 18, count 0 2006.286.04:27:42.87#ibcon#enter sib2, iclass 18, count 0 2006.286.04:27:42.87#ibcon#flushed, iclass 18, count 0 2006.286.04:27:42.87#ibcon#about to write, iclass 18, count 0 2006.286.04:27:42.87#ibcon#wrote, iclass 18, count 0 2006.286.04:27:42.87#ibcon#about to read 3, iclass 18, count 0 2006.286.04:27:42.89#ibcon#read 3, iclass 18, count 0 2006.286.04:27:42.89#ibcon#about to read 4, iclass 18, count 0 2006.286.04:27:42.89#ibcon#read 4, iclass 18, count 0 2006.286.04:27:42.89#ibcon#about to read 5, iclass 18, count 0 2006.286.04:27:42.89#ibcon#read 5, iclass 18, count 0 2006.286.04:27:42.89#ibcon#about to read 6, iclass 18, count 0 2006.286.04:27:42.89#ibcon#read 6, iclass 18, count 0 2006.286.04:27:42.89#ibcon#end of sib2, iclass 18, count 0 2006.286.04:27:42.89#ibcon#*after write, iclass 18, count 0 2006.286.04:27:42.90#ibcon#*before return 0, iclass 18, count 0 2006.286.04:27:42.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:27:42.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:27:42.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:27:42.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:27:42.90$vck44/vblo=4,679.99 2006.286.04:27:42.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.04:27:42.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.04:27:42.90#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:42.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:27:42.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:27:42.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:27:42.90#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:27:42.90#ibcon#first serial, iclass 20, count 0 2006.286.04:27:42.90#ibcon#enter sib2, iclass 20, count 0 2006.286.04:27:42.90#ibcon#flushed, iclass 20, count 0 2006.286.04:27:42.90#ibcon#about to write, iclass 20, count 0 2006.286.04:27:42.90#ibcon#wrote, iclass 20, count 0 2006.286.04:27:42.90#ibcon#about to read 3, iclass 20, count 0 2006.286.04:27:42.91#ibcon#read 3, iclass 20, count 0 2006.286.04:27:42.91#ibcon#about to read 4, iclass 20, count 0 2006.286.04:27:42.91#ibcon#read 4, iclass 20, count 0 2006.286.04:27:42.91#ibcon#about to read 5, iclass 20, count 0 2006.286.04:27:42.91#ibcon#read 5, iclass 20, count 0 2006.286.04:27:42.91#ibcon#about to read 6, iclass 20, count 0 2006.286.04:27:42.91#ibcon#read 6, iclass 20, count 0 2006.286.04:27:42.91#ibcon#end of sib2, iclass 20, count 0 2006.286.04:27:42.91#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:27:42.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:27:42.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:27:42.92#ibcon#*before write, iclass 20, count 0 2006.286.04:27:42.92#ibcon#enter sib2, iclass 20, count 0 2006.286.04:27:42.92#ibcon#flushed, iclass 20, count 0 2006.286.04:27:42.92#ibcon#about to write, iclass 20, count 0 2006.286.04:27:42.92#ibcon#wrote, iclass 20, count 0 2006.286.04:27:42.92#ibcon#about to read 3, iclass 20, count 0 2006.286.04:27:42.95#ibcon#read 3, iclass 20, count 0 2006.286.04:27:42.95#ibcon#about to read 4, iclass 20, count 0 2006.286.04:27:42.95#ibcon#read 4, iclass 20, count 0 2006.286.04:27:42.95#ibcon#about to read 5, iclass 20, count 0 2006.286.04:27:42.95#ibcon#read 5, iclass 20, count 0 2006.286.04:27:42.95#ibcon#about to read 6, iclass 20, count 0 2006.286.04:27:42.95#ibcon#read 6, iclass 20, count 0 2006.286.04:27:42.95#ibcon#end of sib2, iclass 20, count 0 2006.286.04:27:42.95#ibcon#*after write, iclass 20, count 0 2006.286.04:27:42.96#ibcon#*before return 0, iclass 20, count 0 2006.286.04:27:42.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:27:42.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:27:42.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:27:42.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:27:42.96$vck44/vb=4,5 2006.286.04:27:42.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.04:27:42.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.04:27:42.96#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:42.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:27:43.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:27:43.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:27:43.02#ibcon#enter wrdev, iclass 22, count 2 2006.286.04:27:43.02#ibcon#first serial, iclass 22, count 2 2006.286.04:27:43.02#ibcon#enter sib2, iclass 22, count 2 2006.286.04:27:43.02#ibcon#flushed, iclass 22, count 2 2006.286.04:27:43.02#ibcon#about to write, iclass 22, count 2 2006.286.04:27:43.02#ibcon#wrote, iclass 22, count 2 2006.286.04:27:43.02#ibcon#about to read 3, iclass 22, count 2 2006.286.04:27:43.03#ibcon#read 3, iclass 22, count 2 2006.286.04:27:43.03#ibcon#about to read 4, iclass 22, count 2 2006.286.04:27:43.03#ibcon#read 4, iclass 22, count 2 2006.286.04:27:43.03#ibcon#about to read 5, iclass 22, count 2 2006.286.04:27:43.03#ibcon#read 5, iclass 22, count 2 2006.286.04:27:43.03#ibcon#about to read 6, iclass 22, count 2 2006.286.04:27:43.03#ibcon#read 6, iclass 22, count 2 2006.286.04:27:43.03#ibcon#end of sib2, iclass 22, count 2 2006.286.04:27:43.03#ibcon#*mode == 0, iclass 22, count 2 2006.286.04:27:43.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.04:27:43.04#ibcon#[27=AT04-05\r\n] 2006.286.04:27:43.04#ibcon#*before write, iclass 22, count 2 2006.286.04:27:43.04#ibcon#enter sib2, iclass 22, count 2 2006.286.04:27:43.04#ibcon#flushed, iclass 22, count 2 2006.286.04:27:43.04#ibcon#about to write, iclass 22, count 2 2006.286.04:27:43.04#ibcon#wrote, iclass 22, count 2 2006.286.04:27:43.04#ibcon#about to read 3, iclass 22, count 2 2006.286.04:27:43.06#ibcon#read 3, iclass 22, count 2 2006.286.04:27:43.06#ibcon#about to read 4, iclass 22, count 2 2006.286.04:27:43.06#ibcon#read 4, iclass 22, count 2 2006.286.04:27:43.06#ibcon#about to read 5, iclass 22, count 2 2006.286.04:27:43.06#ibcon#read 5, iclass 22, count 2 2006.286.04:27:43.06#ibcon#about to read 6, iclass 22, count 2 2006.286.04:27:43.06#ibcon#read 6, iclass 22, count 2 2006.286.04:27:43.06#ibcon#end of sib2, iclass 22, count 2 2006.286.04:27:43.06#ibcon#*after write, iclass 22, count 2 2006.286.04:27:43.07#ibcon#*before return 0, iclass 22, count 2 2006.286.04:27:43.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:27:43.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:27:43.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.04:27:43.07#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:43.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:27:43.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:27:43.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:27:43.18#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:27:43.18#ibcon#first serial, iclass 22, count 0 2006.286.04:27:43.18#ibcon#enter sib2, iclass 22, count 0 2006.286.04:27:43.18#ibcon#flushed, iclass 22, count 0 2006.286.04:27:43.18#ibcon#about to write, iclass 22, count 0 2006.286.04:27:43.19#ibcon#wrote, iclass 22, count 0 2006.286.04:27:43.19#ibcon#about to read 3, iclass 22, count 0 2006.286.04:27:43.20#ibcon#read 3, iclass 22, count 0 2006.286.04:27:43.21#ibcon#about to read 4, iclass 22, count 0 2006.286.04:27:43.21#ibcon#read 4, iclass 22, count 0 2006.286.04:27:43.21#ibcon#about to read 5, iclass 22, count 0 2006.286.04:27:43.21#ibcon#read 5, iclass 22, count 0 2006.286.04:27:43.21#ibcon#about to read 6, iclass 22, count 0 2006.286.04:27:43.21#ibcon#read 6, iclass 22, count 0 2006.286.04:27:43.21#ibcon#end of sib2, iclass 22, count 0 2006.286.04:27:43.21#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:27:43.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:27:43.21#ibcon#[27=USB\r\n] 2006.286.04:27:43.21#ibcon#*before write, iclass 22, count 0 2006.286.04:27:43.21#ibcon#enter sib2, iclass 22, count 0 2006.286.04:27:43.21#ibcon#flushed, iclass 22, count 0 2006.286.04:27:43.21#ibcon#about to write, iclass 22, count 0 2006.286.04:27:43.21#ibcon#wrote, iclass 22, count 0 2006.286.04:27:43.21#ibcon#about to read 3, iclass 22, count 0 2006.286.04:27:43.23#ibcon#read 3, iclass 22, count 0 2006.286.04:27:43.23#ibcon#about to read 4, iclass 22, count 0 2006.286.04:27:43.23#ibcon#read 4, iclass 22, count 0 2006.286.04:27:43.23#ibcon#about to read 5, iclass 22, count 0 2006.286.04:27:43.23#ibcon#read 5, iclass 22, count 0 2006.286.04:27:43.23#ibcon#about to read 6, iclass 22, count 0 2006.286.04:27:43.23#ibcon#read 6, iclass 22, count 0 2006.286.04:27:43.24#ibcon#end of sib2, iclass 22, count 0 2006.286.04:27:43.24#ibcon#*after write, iclass 22, count 0 2006.286.04:27:43.24#ibcon#*before return 0, iclass 22, count 0 2006.286.04:27:43.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:27:43.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:27:43.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:27:43.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:27:43.24$vck44/vblo=5,709.99 2006.286.04:27:43.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.04:27:43.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.04:27:43.24#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:43.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:27:43.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:27:43.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:27:43.24#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:27:43.24#ibcon#first serial, iclass 24, count 0 2006.286.04:27:43.24#ibcon#enter sib2, iclass 24, count 0 2006.286.04:27:43.24#ibcon#flushed, iclass 24, count 0 2006.286.04:27:43.24#ibcon#about to write, iclass 24, count 0 2006.286.04:27:43.24#ibcon#wrote, iclass 24, count 0 2006.286.04:27:43.24#ibcon#about to read 3, iclass 24, count 0 2006.286.04:27:43.25#ibcon#read 3, iclass 24, count 0 2006.286.04:27:43.25#ibcon#about to read 4, iclass 24, count 0 2006.286.04:27:43.25#ibcon#read 4, iclass 24, count 0 2006.286.04:27:43.25#ibcon#about to read 5, iclass 24, count 0 2006.286.04:27:43.25#ibcon#read 5, iclass 24, count 0 2006.286.04:27:43.25#ibcon#about to read 6, iclass 24, count 0 2006.286.04:27:43.25#ibcon#read 6, iclass 24, count 0 2006.286.04:27:43.25#ibcon#end of sib2, iclass 24, count 0 2006.286.04:27:43.26#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:27:43.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:27:43.26#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:27:43.26#ibcon#*before write, iclass 24, count 0 2006.286.04:27:43.26#ibcon#enter sib2, iclass 24, count 0 2006.286.04:27:43.26#ibcon#flushed, iclass 24, count 0 2006.286.04:27:43.26#ibcon#about to write, iclass 24, count 0 2006.286.04:27:43.26#ibcon#wrote, iclass 24, count 0 2006.286.04:27:43.26#ibcon#about to read 3, iclass 24, count 0 2006.286.04:27:43.29#ibcon#read 3, iclass 24, count 0 2006.286.04:27:43.29#ibcon#about to read 4, iclass 24, count 0 2006.286.04:27:43.29#ibcon#read 4, iclass 24, count 0 2006.286.04:27:43.29#ibcon#about to read 5, iclass 24, count 0 2006.286.04:27:43.29#ibcon#read 5, iclass 24, count 0 2006.286.04:27:43.29#ibcon#about to read 6, iclass 24, count 0 2006.286.04:27:43.29#ibcon#read 6, iclass 24, count 0 2006.286.04:27:43.30#ibcon#end of sib2, iclass 24, count 0 2006.286.04:27:43.30#ibcon#*after write, iclass 24, count 0 2006.286.04:27:43.30#ibcon#*before return 0, iclass 24, count 0 2006.286.04:27:43.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:27:43.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:27:43.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:27:43.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:27:43.30$vck44/vb=5,4 2006.286.04:27:43.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.04:27:43.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.04:27:43.30#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:43.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:27:43.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:27:43.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:27:43.35#ibcon#enter wrdev, iclass 26, count 2 2006.286.04:27:43.35#ibcon#first serial, iclass 26, count 2 2006.286.04:27:43.35#ibcon#enter sib2, iclass 26, count 2 2006.286.04:27:43.35#ibcon#flushed, iclass 26, count 2 2006.286.04:27:43.35#ibcon#about to write, iclass 26, count 2 2006.286.04:27:43.35#ibcon#wrote, iclass 26, count 2 2006.286.04:27:43.35#ibcon#about to read 3, iclass 26, count 2 2006.286.04:27:43.37#ibcon#read 3, iclass 26, count 2 2006.286.04:27:43.54#ibcon#about to read 4, iclass 26, count 2 2006.286.04:27:43.54#ibcon#read 4, iclass 26, count 2 2006.286.04:27:43.54#ibcon#about to read 5, iclass 26, count 2 2006.286.04:27:43.54#ibcon#read 5, iclass 26, count 2 2006.286.04:27:43.54#ibcon#about to read 6, iclass 26, count 2 2006.286.04:27:43.54#ibcon#read 6, iclass 26, count 2 2006.286.04:27:43.54#ibcon#end of sib2, iclass 26, count 2 2006.286.04:27:43.54#ibcon#*mode == 0, iclass 26, count 2 2006.286.04:27:43.54#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.04:27:43.54#ibcon#[27=AT05-04\r\n] 2006.286.04:27:43.54#ibcon#*before write, iclass 26, count 2 2006.286.04:27:43.54#ibcon#enter sib2, iclass 26, count 2 2006.286.04:27:43.54#ibcon#flushed, iclass 26, count 2 2006.286.04:27:43.54#ibcon#about to write, iclass 26, count 2 2006.286.04:27:43.54#ibcon#wrote, iclass 26, count 2 2006.286.04:27:43.54#ibcon#about to read 3, iclass 26, count 2 2006.286.04:27:43.56#ibcon#read 3, iclass 26, count 2 2006.286.04:27:43.56#ibcon#about to read 4, iclass 26, count 2 2006.286.04:27:43.56#ibcon#read 4, iclass 26, count 2 2006.286.04:27:43.56#ibcon#about to read 5, iclass 26, count 2 2006.286.04:27:43.56#ibcon#read 5, iclass 26, count 2 2006.286.04:27:43.56#ibcon#about to read 6, iclass 26, count 2 2006.286.04:27:43.56#ibcon#read 6, iclass 26, count 2 2006.286.04:27:43.57#ibcon#end of sib2, iclass 26, count 2 2006.286.04:27:43.57#ibcon#*after write, iclass 26, count 2 2006.286.04:27:43.57#ibcon#*before return 0, iclass 26, count 2 2006.286.04:27:43.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:27:43.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:27:43.57#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.04:27:43.57#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:43.57#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:27:43.68#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:27:43.68#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:27:43.68#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:27:43.68#ibcon#first serial, iclass 26, count 0 2006.286.04:27:43.68#ibcon#enter sib2, iclass 26, count 0 2006.286.04:27:43.68#ibcon#flushed, iclass 26, count 0 2006.286.04:27:43.68#ibcon#about to write, iclass 26, count 0 2006.286.04:27:43.69#ibcon#wrote, iclass 26, count 0 2006.286.04:27:43.69#ibcon#about to read 3, iclass 26, count 0 2006.286.04:27:43.70#ibcon#read 3, iclass 26, count 0 2006.286.04:27:43.70#ibcon#about to read 4, iclass 26, count 0 2006.286.04:27:43.70#ibcon#read 4, iclass 26, count 0 2006.286.04:27:43.70#ibcon#about to read 5, iclass 26, count 0 2006.286.04:27:43.70#ibcon#read 5, iclass 26, count 0 2006.286.04:27:43.70#ibcon#about to read 6, iclass 26, count 0 2006.286.04:27:43.70#ibcon#read 6, iclass 26, count 0 2006.286.04:27:43.71#ibcon#end of sib2, iclass 26, count 0 2006.286.04:27:43.71#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:27:43.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:27:43.71#ibcon#[27=USB\r\n] 2006.286.04:27:43.71#ibcon#*before write, iclass 26, count 0 2006.286.04:27:43.71#ibcon#enter sib2, iclass 26, count 0 2006.286.04:27:43.71#ibcon#flushed, iclass 26, count 0 2006.286.04:27:43.71#ibcon#about to write, iclass 26, count 0 2006.286.04:27:43.71#ibcon#wrote, iclass 26, count 0 2006.286.04:27:43.71#ibcon#about to read 3, iclass 26, count 0 2006.286.04:27:43.73#ibcon#read 3, iclass 26, count 0 2006.286.04:27:43.73#ibcon#about to read 4, iclass 26, count 0 2006.286.04:27:43.73#ibcon#read 4, iclass 26, count 0 2006.286.04:27:43.73#ibcon#about to read 5, iclass 26, count 0 2006.286.04:27:43.73#ibcon#read 5, iclass 26, count 0 2006.286.04:27:43.73#ibcon#about to read 6, iclass 26, count 0 2006.286.04:27:43.73#ibcon#read 6, iclass 26, count 0 2006.286.04:27:43.73#ibcon#end of sib2, iclass 26, count 0 2006.286.04:27:43.74#ibcon#*after write, iclass 26, count 0 2006.286.04:27:43.74#ibcon#*before return 0, iclass 26, count 0 2006.286.04:27:43.74#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:27:43.74#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:27:43.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:27:43.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:27:43.74$vck44/vblo=6,719.99 2006.286.04:27:43.74#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.04:27:43.74#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.04:27:43.74#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:43.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:27:43.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:27:43.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:27:43.74#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:27:43.74#ibcon#first serial, iclass 28, count 0 2006.286.04:27:43.74#ibcon#enter sib2, iclass 28, count 0 2006.286.04:27:43.74#ibcon#flushed, iclass 28, count 0 2006.286.04:27:43.74#ibcon#about to write, iclass 28, count 0 2006.286.04:27:43.74#ibcon#wrote, iclass 28, count 0 2006.286.04:27:43.74#ibcon#about to read 3, iclass 28, count 0 2006.286.04:27:43.75#ibcon#read 3, iclass 28, count 0 2006.286.04:27:43.75#ibcon#about to read 4, iclass 28, count 0 2006.286.04:27:43.75#ibcon#read 4, iclass 28, count 0 2006.286.04:27:43.75#ibcon#about to read 5, iclass 28, count 0 2006.286.04:27:43.75#ibcon#read 5, iclass 28, count 0 2006.286.04:27:43.75#ibcon#about to read 6, iclass 28, count 0 2006.286.04:27:43.75#ibcon#read 6, iclass 28, count 0 2006.286.04:27:43.75#ibcon#end of sib2, iclass 28, count 0 2006.286.04:27:43.75#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:27:43.76#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:27:43.76#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:27:43.76#ibcon#*before write, iclass 28, count 0 2006.286.04:27:43.76#ibcon#enter sib2, iclass 28, count 0 2006.286.04:27:43.76#ibcon#flushed, iclass 28, count 0 2006.286.04:27:43.76#ibcon#about to write, iclass 28, count 0 2006.286.04:27:43.76#ibcon#wrote, iclass 28, count 0 2006.286.04:27:43.76#ibcon#about to read 3, iclass 28, count 0 2006.286.04:27:43.79#ibcon#read 3, iclass 28, count 0 2006.286.04:27:43.79#ibcon#about to read 4, iclass 28, count 0 2006.286.04:27:43.79#ibcon#read 4, iclass 28, count 0 2006.286.04:27:43.79#ibcon#about to read 5, iclass 28, count 0 2006.286.04:27:43.79#ibcon#read 5, iclass 28, count 0 2006.286.04:27:43.79#ibcon#about to read 6, iclass 28, count 0 2006.286.04:27:43.79#ibcon#read 6, iclass 28, count 0 2006.286.04:27:43.79#ibcon#end of sib2, iclass 28, count 0 2006.286.04:27:43.79#ibcon#*after write, iclass 28, count 0 2006.286.04:27:43.80#ibcon#*before return 0, iclass 28, count 0 2006.286.04:27:43.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:27:43.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:27:43.80#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:27:43.80#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:27:43.80$vck44/vb=6,3 2006.286.04:27:43.80#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.04:27:43.80#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.04:27:43.80#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:43.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:27:43.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:27:43.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:27:43.85#ibcon#enter wrdev, iclass 30, count 2 2006.286.04:27:43.85#ibcon#first serial, iclass 30, count 2 2006.286.04:27:43.85#ibcon#enter sib2, iclass 30, count 2 2006.286.04:27:43.85#ibcon#flushed, iclass 30, count 2 2006.286.04:27:43.85#ibcon#about to write, iclass 30, count 2 2006.286.04:27:43.85#ibcon#wrote, iclass 30, count 2 2006.286.04:27:43.86#ibcon#about to read 3, iclass 30, count 2 2006.286.04:27:43.87#ibcon#read 3, iclass 30, count 2 2006.286.04:27:43.87#ibcon#about to read 4, iclass 30, count 2 2006.286.04:27:43.87#ibcon#read 4, iclass 30, count 2 2006.286.04:27:43.87#ibcon#about to read 5, iclass 30, count 2 2006.286.04:27:43.87#ibcon#read 5, iclass 30, count 2 2006.286.04:27:43.87#ibcon#about to read 6, iclass 30, count 2 2006.286.04:27:43.87#ibcon#read 6, iclass 30, count 2 2006.286.04:27:43.87#ibcon#end of sib2, iclass 30, count 2 2006.286.04:27:43.87#ibcon#*mode == 0, iclass 30, count 2 2006.286.04:27:43.88#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.04:27:43.88#ibcon#[27=AT06-03\r\n] 2006.286.04:27:43.88#ibcon#*before write, iclass 30, count 2 2006.286.04:27:43.88#ibcon#enter sib2, iclass 30, count 2 2006.286.04:27:43.88#ibcon#flushed, iclass 30, count 2 2006.286.04:27:43.88#ibcon#about to write, iclass 30, count 2 2006.286.04:27:43.88#ibcon#wrote, iclass 30, count 2 2006.286.04:27:43.88#ibcon#about to read 3, iclass 30, count 2 2006.286.04:27:43.90#ibcon#read 3, iclass 30, count 2 2006.286.04:27:43.90#ibcon#about to read 4, iclass 30, count 2 2006.286.04:27:43.90#ibcon#read 4, iclass 30, count 2 2006.286.04:27:43.90#ibcon#about to read 5, iclass 30, count 2 2006.286.04:27:43.90#ibcon#read 5, iclass 30, count 2 2006.286.04:27:43.90#ibcon#about to read 6, iclass 30, count 2 2006.286.04:27:43.90#ibcon#read 6, iclass 30, count 2 2006.286.04:27:43.90#ibcon#end of sib2, iclass 30, count 2 2006.286.04:27:43.90#ibcon#*after write, iclass 30, count 2 2006.286.04:27:43.91#ibcon#*before return 0, iclass 30, count 2 2006.286.04:27:43.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:27:43.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:27:43.91#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.04:27:43.91#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:43.91#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:27:44.02#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:27:44.02#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:27:44.02#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:27:44.02#ibcon#first serial, iclass 30, count 0 2006.286.04:27:44.02#ibcon#enter sib2, iclass 30, count 0 2006.286.04:27:44.02#ibcon#flushed, iclass 30, count 0 2006.286.04:27:44.02#ibcon#about to write, iclass 30, count 0 2006.286.04:27:44.03#ibcon#wrote, iclass 30, count 0 2006.286.04:27:44.03#ibcon#about to read 3, iclass 30, count 0 2006.286.04:27:44.04#ibcon#read 3, iclass 30, count 0 2006.286.04:27:44.04#ibcon#about to read 4, iclass 30, count 0 2006.286.04:27:44.04#ibcon#read 4, iclass 30, count 0 2006.286.04:27:44.04#ibcon#about to read 5, iclass 30, count 0 2006.286.04:27:44.04#ibcon#read 5, iclass 30, count 0 2006.286.04:27:44.04#ibcon#about to read 6, iclass 30, count 0 2006.286.04:27:44.04#ibcon#read 6, iclass 30, count 0 2006.286.04:27:44.04#ibcon#end of sib2, iclass 30, count 0 2006.286.04:27:44.04#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:27:44.05#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:27:44.05#ibcon#[27=USB\r\n] 2006.286.04:27:44.05#ibcon#*before write, iclass 30, count 0 2006.286.04:27:44.05#ibcon#enter sib2, iclass 30, count 0 2006.286.04:27:44.05#ibcon#flushed, iclass 30, count 0 2006.286.04:27:44.05#ibcon#about to write, iclass 30, count 0 2006.286.04:27:44.05#ibcon#wrote, iclass 30, count 0 2006.286.04:27:44.05#ibcon#about to read 3, iclass 30, count 0 2006.286.04:27:44.07#ibcon#read 3, iclass 30, count 0 2006.286.04:27:44.07#ibcon#about to read 4, iclass 30, count 0 2006.286.04:27:44.07#ibcon#read 4, iclass 30, count 0 2006.286.04:27:44.07#ibcon#about to read 5, iclass 30, count 0 2006.286.04:27:44.07#ibcon#read 5, iclass 30, count 0 2006.286.04:27:44.08#ibcon#about to read 6, iclass 30, count 0 2006.286.04:27:44.08#ibcon#read 6, iclass 30, count 0 2006.286.04:27:44.08#ibcon#end of sib2, iclass 30, count 0 2006.286.04:27:44.08#ibcon#*after write, iclass 30, count 0 2006.286.04:27:44.08#ibcon#*before return 0, iclass 30, count 0 2006.286.04:27:44.08#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:27:44.08#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:27:44.08#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:27:44.08#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:27:44.08$vck44/vblo=7,734.99 2006.286.04:27:44.08#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.04:27:44.08#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.04:27:44.08#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:44.08#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:27:44.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:27:44.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:27:44.08#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:27:44.08#ibcon#first serial, iclass 32, count 0 2006.286.04:27:44.08#ibcon#enter sib2, iclass 32, count 0 2006.286.04:27:44.08#ibcon#flushed, iclass 32, count 0 2006.286.04:27:44.08#ibcon#about to write, iclass 32, count 0 2006.286.04:27:44.08#ibcon#wrote, iclass 32, count 0 2006.286.04:27:44.08#ibcon#about to read 3, iclass 32, count 0 2006.286.04:27:44.09#ibcon#read 3, iclass 32, count 0 2006.286.04:27:44.09#ibcon#about to read 4, iclass 32, count 0 2006.286.04:27:44.09#ibcon#read 4, iclass 32, count 0 2006.286.04:27:44.09#ibcon#about to read 5, iclass 32, count 0 2006.286.04:27:44.09#ibcon#read 5, iclass 32, count 0 2006.286.04:27:44.09#ibcon#about to read 6, iclass 32, count 0 2006.286.04:27:44.09#ibcon#read 6, iclass 32, count 0 2006.286.04:27:44.09#ibcon#end of sib2, iclass 32, count 0 2006.286.04:27:44.10#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:27:44.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:27:44.10#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:27:44.10#ibcon#*before write, iclass 32, count 0 2006.286.04:27:44.10#ibcon#enter sib2, iclass 32, count 0 2006.286.04:27:44.10#ibcon#flushed, iclass 32, count 0 2006.286.04:27:44.10#ibcon#about to write, iclass 32, count 0 2006.286.04:27:44.10#ibcon#wrote, iclass 32, count 0 2006.286.04:27:44.10#ibcon#about to read 3, iclass 32, count 0 2006.286.04:27:44.13#ibcon#read 3, iclass 32, count 0 2006.286.04:27:44.13#ibcon#about to read 4, iclass 32, count 0 2006.286.04:27:44.13#ibcon#read 4, iclass 32, count 0 2006.286.04:27:44.13#ibcon#about to read 5, iclass 32, count 0 2006.286.04:27:44.13#ibcon#read 5, iclass 32, count 0 2006.286.04:27:44.13#ibcon#about to read 6, iclass 32, count 0 2006.286.04:27:44.13#ibcon#read 6, iclass 32, count 0 2006.286.04:27:44.13#ibcon#end of sib2, iclass 32, count 0 2006.286.04:27:44.13#ibcon#*after write, iclass 32, count 0 2006.286.04:27:44.14#ibcon#*before return 0, iclass 32, count 0 2006.286.04:27:44.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:27:44.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:27:44.14#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:27:44.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:27:44.14$vck44/vb=7,4 2006.286.04:27:44.14#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.04:27:44.14#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.04:27:44.14#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:44.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:27:44.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:27:44.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:27:44.19#ibcon#enter wrdev, iclass 34, count 2 2006.286.04:27:44.19#ibcon#first serial, iclass 34, count 2 2006.286.04:27:44.19#ibcon#enter sib2, iclass 34, count 2 2006.286.04:27:44.19#ibcon#flushed, iclass 34, count 2 2006.286.04:27:44.19#ibcon#about to write, iclass 34, count 2 2006.286.04:27:44.20#ibcon#wrote, iclass 34, count 2 2006.286.04:27:44.20#ibcon#about to read 3, iclass 34, count 2 2006.286.04:27:44.21#ibcon#read 3, iclass 34, count 2 2006.286.04:27:44.22#ibcon#about to read 4, iclass 34, count 2 2006.286.04:27:44.22#ibcon#read 4, iclass 34, count 2 2006.286.04:27:44.22#ibcon#about to read 5, iclass 34, count 2 2006.286.04:27:44.22#ibcon#read 5, iclass 34, count 2 2006.286.04:27:44.22#ibcon#about to read 6, iclass 34, count 2 2006.286.04:27:44.22#ibcon#read 6, iclass 34, count 2 2006.286.04:27:44.22#ibcon#end of sib2, iclass 34, count 2 2006.286.04:27:44.22#ibcon#*mode == 0, iclass 34, count 2 2006.286.04:27:44.22#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.04:27:44.22#ibcon#[27=AT07-04\r\n] 2006.286.04:27:44.22#ibcon#*before write, iclass 34, count 2 2006.286.04:27:44.22#ibcon#enter sib2, iclass 34, count 2 2006.286.04:27:44.22#ibcon#flushed, iclass 34, count 2 2006.286.04:27:44.22#ibcon#about to write, iclass 34, count 2 2006.286.04:27:44.22#ibcon#wrote, iclass 34, count 2 2006.286.04:27:44.22#ibcon#about to read 3, iclass 34, count 2 2006.286.04:27:44.24#ibcon#read 3, iclass 34, count 2 2006.286.04:27:44.24#ibcon#about to read 4, iclass 34, count 2 2006.286.04:27:44.24#ibcon#read 4, iclass 34, count 2 2006.286.04:27:44.24#ibcon#about to read 5, iclass 34, count 2 2006.286.04:27:44.24#ibcon#read 5, iclass 34, count 2 2006.286.04:27:44.24#ibcon#about to read 6, iclass 34, count 2 2006.286.04:27:44.25#ibcon#read 6, iclass 34, count 2 2006.286.04:27:44.25#ibcon#end of sib2, iclass 34, count 2 2006.286.04:27:44.25#ibcon#*after write, iclass 34, count 2 2006.286.04:27:44.25#ibcon#*before return 0, iclass 34, count 2 2006.286.04:27:44.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:27:44.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:27:44.25#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.04:27:44.25#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:44.25#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:27:44.36#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:27:44.36#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:27:44.36#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:27:44.36#ibcon#first serial, iclass 34, count 0 2006.286.04:27:44.36#ibcon#enter sib2, iclass 34, count 0 2006.286.04:27:44.36#ibcon#flushed, iclass 34, count 0 2006.286.04:27:44.36#ibcon#about to write, iclass 34, count 0 2006.286.04:27:44.37#ibcon#wrote, iclass 34, count 0 2006.286.04:27:44.37#ibcon#about to read 3, iclass 34, count 0 2006.286.04:27:44.38#ibcon#read 3, iclass 34, count 0 2006.286.04:27:44.38#ibcon#about to read 4, iclass 34, count 0 2006.286.04:27:44.38#ibcon#read 4, iclass 34, count 0 2006.286.04:27:44.38#ibcon#about to read 5, iclass 34, count 0 2006.286.04:27:44.38#ibcon#read 5, iclass 34, count 0 2006.286.04:27:44.38#ibcon#about to read 6, iclass 34, count 0 2006.286.04:27:44.38#ibcon#read 6, iclass 34, count 0 2006.286.04:27:44.38#ibcon#end of sib2, iclass 34, count 0 2006.286.04:27:44.38#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:27:44.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:27:44.39#ibcon#[27=USB\r\n] 2006.286.04:27:44.39#ibcon#*before write, iclass 34, count 0 2006.286.04:27:44.39#ibcon#enter sib2, iclass 34, count 0 2006.286.04:27:44.39#ibcon#flushed, iclass 34, count 0 2006.286.04:27:44.39#ibcon#about to write, iclass 34, count 0 2006.286.04:27:44.39#ibcon#wrote, iclass 34, count 0 2006.286.04:27:44.39#ibcon#about to read 3, iclass 34, count 0 2006.286.04:27:44.41#ibcon#read 3, iclass 34, count 0 2006.286.04:27:44.41#ibcon#about to read 4, iclass 34, count 0 2006.286.04:27:44.41#ibcon#read 4, iclass 34, count 0 2006.286.04:27:44.41#ibcon#about to read 5, iclass 34, count 0 2006.286.04:27:44.41#ibcon#read 5, iclass 34, count 0 2006.286.04:27:44.41#ibcon#about to read 6, iclass 34, count 0 2006.286.04:27:44.41#ibcon#read 6, iclass 34, count 0 2006.286.04:27:44.41#ibcon#end of sib2, iclass 34, count 0 2006.286.04:27:44.41#ibcon#*after write, iclass 34, count 0 2006.286.04:27:44.41#ibcon#*before return 0, iclass 34, count 0 2006.286.04:27:44.41#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:27:44.41#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:27:44.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:27:44.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:27:44.42$vck44/vblo=8,744.99 2006.286.04:27:44.42#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.04:27:44.42#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.04:27:44.42#ibcon#ireg 17 cls_cnt 0 2006.286.04:27:44.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:27:44.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:27:44.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:27:44.42#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:27:44.42#ibcon#first serial, iclass 36, count 0 2006.286.04:27:44.42#ibcon#enter sib2, iclass 36, count 0 2006.286.04:27:44.42#ibcon#flushed, iclass 36, count 0 2006.286.04:27:44.42#ibcon#about to write, iclass 36, count 0 2006.286.04:27:44.42#ibcon#wrote, iclass 36, count 0 2006.286.04:27:44.42#ibcon#about to read 3, iclass 36, count 0 2006.286.04:27:44.77#ibcon#read 3, iclass 36, count 0 2006.286.04:27:44.77#ibcon#about to read 4, iclass 36, count 0 2006.286.04:27:44.77#ibcon#read 4, iclass 36, count 0 2006.286.04:27:44.77#ibcon#about to read 5, iclass 36, count 0 2006.286.04:27:44.77#ibcon#read 5, iclass 36, count 0 2006.286.04:27:44.77#ibcon#about to read 6, iclass 36, count 0 2006.286.04:27:44.77#ibcon#read 6, iclass 36, count 0 2006.286.04:27:44.77#ibcon#end of sib2, iclass 36, count 0 2006.286.04:27:44.77#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:27:44.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:27:44.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:27:44.77#ibcon#*before write, iclass 36, count 0 2006.286.04:27:44.77#ibcon#enter sib2, iclass 36, count 0 2006.286.04:27:44.77#ibcon#flushed, iclass 36, count 0 2006.286.04:27:44.77#ibcon#about to write, iclass 36, count 0 2006.286.04:27:44.77#ibcon#wrote, iclass 36, count 0 2006.286.04:27:44.77#ibcon#about to read 3, iclass 36, count 0 2006.286.04:27:44.80#ibcon#read 3, iclass 36, count 0 2006.286.04:27:44.80#ibcon#about to read 4, iclass 36, count 0 2006.286.04:27:44.80#ibcon#read 4, iclass 36, count 0 2006.286.04:27:44.80#ibcon#about to read 5, iclass 36, count 0 2006.286.04:27:44.80#ibcon#read 5, iclass 36, count 0 2006.286.04:27:44.80#ibcon#about to read 6, iclass 36, count 0 2006.286.04:27:44.80#ibcon#read 6, iclass 36, count 0 2006.286.04:27:44.81#ibcon#end of sib2, iclass 36, count 0 2006.286.04:27:44.81#ibcon#*after write, iclass 36, count 0 2006.286.04:27:44.81#ibcon#*before return 0, iclass 36, count 0 2006.286.04:27:44.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:27:44.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:27:44.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:27:44.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:27:44.81$vck44/vb=8,4 2006.286.04:27:44.81#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.04:27:44.81#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.04:27:44.81#ibcon#ireg 11 cls_cnt 2 2006.286.04:27:44.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:27:44.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:27:44.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:27:44.81#ibcon#enter wrdev, iclass 38, count 2 2006.286.04:27:44.81#ibcon#first serial, iclass 38, count 2 2006.286.04:27:44.81#ibcon#enter sib2, iclass 38, count 2 2006.286.04:27:44.81#ibcon#flushed, iclass 38, count 2 2006.286.04:27:44.81#ibcon#about to write, iclass 38, count 2 2006.286.04:27:44.81#ibcon#wrote, iclass 38, count 2 2006.286.04:27:44.81#ibcon#about to read 3, iclass 38, count 2 2006.286.04:27:44.82#ibcon#read 3, iclass 38, count 2 2006.286.04:27:44.82#ibcon#about to read 4, iclass 38, count 2 2006.286.04:27:44.82#ibcon#read 4, iclass 38, count 2 2006.286.04:27:44.82#ibcon#about to read 5, iclass 38, count 2 2006.286.04:27:44.82#ibcon#read 5, iclass 38, count 2 2006.286.04:27:44.82#ibcon#about to read 6, iclass 38, count 2 2006.286.04:27:44.82#ibcon#read 6, iclass 38, count 2 2006.286.04:27:44.82#ibcon#end of sib2, iclass 38, count 2 2006.286.04:27:44.83#ibcon#*mode == 0, iclass 38, count 2 2006.286.04:27:44.83#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.04:27:44.83#ibcon#[27=AT08-04\r\n] 2006.286.04:27:44.83#ibcon#*before write, iclass 38, count 2 2006.286.04:27:44.83#ibcon#enter sib2, iclass 38, count 2 2006.286.04:27:44.83#ibcon#flushed, iclass 38, count 2 2006.286.04:27:44.83#ibcon#about to write, iclass 38, count 2 2006.286.04:27:44.83#ibcon#wrote, iclass 38, count 2 2006.286.04:27:44.83#ibcon#about to read 3, iclass 38, count 2 2006.286.04:27:44.85#ibcon#read 3, iclass 38, count 2 2006.286.04:27:44.85#ibcon#about to read 4, iclass 38, count 2 2006.286.04:27:44.85#ibcon#read 4, iclass 38, count 2 2006.286.04:27:44.85#ibcon#about to read 5, iclass 38, count 2 2006.286.04:27:44.85#ibcon#read 5, iclass 38, count 2 2006.286.04:27:44.85#ibcon#about to read 6, iclass 38, count 2 2006.286.04:27:44.85#ibcon#read 6, iclass 38, count 2 2006.286.04:27:44.86#ibcon#end of sib2, iclass 38, count 2 2006.286.04:27:44.86#ibcon#*after write, iclass 38, count 2 2006.286.04:27:44.86#ibcon#*before return 0, iclass 38, count 2 2006.286.04:27:44.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:27:44.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:27:44.86#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.04:27:44.86#ibcon#ireg 7 cls_cnt 0 2006.286.04:27:44.86#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:27:44.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:27:44.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:27:44.97#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:27:44.97#ibcon#first serial, iclass 38, count 0 2006.286.04:27:44.97#ibcon#enter sib2, iclass 38, count 0 2006.286.04:27:44.97#ibcon#flushed, iclass 38, count 0 2006.286.04:27:44.97#ibcon#about to write, iclass 38, count 0 2006.286.04:27:44.98#ibcon#wrote, iclass 38, count 0 2006.286.04:27:44.98#ibcon#about to read 3, iclass 38, count 0 2006.286.04:27:44.99#ibcon#read 3, iclass 38, count 0 2006.286.04:27:44.99#ibcon#about to read 4, iclass 38, count 0 2006.286.04:27:44.99#ibcon#read 4, iclass 38, count 0 2006.286.04:27:44.99#ibcon#about to read 5, iclass 38, count 0 2006.286.04:27:44.99#ibcon#read 5, iclass 38, count 0 2006.286.04:27:44.99#ibcon#about to read 6, iclass 38, count 0 2006.286.04:27:44.99#ibcon#read 6, iclass 38, count 0 2006.286.04:27:45.00#ibcon#end of sib2, iclass 38, count 0 2006.286.04:27:45.00#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:27:45.00#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:27:45.00#ibcon#[27=USB\r\n] 2006.286.04:27:45.00#ibcon#*before write, iclass 38, count 0 2006.286.04:27:45.00#ibcon#enter sib2, iclass 38, count 0 2006.286.04:27:45.00#ibcon#flushed, iclass 38, count 0 2006.286.04:27:45.00#ibcon#about to write, iclass 38, count 0 2006.286.04:27:45.00#ibcon#wrote, iclass 38, count 0 2006.286.04:27:45.00#ibcon#about to read 3, iclass 38, count 0 2006.286.04:27:45.02#ibcon#read 3, iclass 38, count 0 2006.286.04:27:45.02#ibcon#about to read 4, iclass 38, count 0 2006.286.04:27:45.02#ibcon#read 4, iclass 38, count 0 2006.286.04:27:45.02#ibcon#about to read 5, iclass 38, count 0 2006.286.04:27:45.02#ibcon#read 5, iclass 38, count 0 2006.286.04:27:45.02#ibcon#about to read 6, iclass 38, count 0 2006.286.04:27:45.02#ibcon#read 6, iclass 38, count 0 2006.286.04:27:45.02#ibcon#end of sib2, iclass 38, count 0 2006.286.04:27:45.03#ibcon#*after write, iclass 38, count 0 2006.286.04:27:45.03#ibcon#*before return 0, iclass 38, count 0 2006.286.04:27:45.03#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:27:45.03#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:27:45.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:27:45.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:27:45.03$vck44/vabw=wide 2006.286.04:27:45.03#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.04:27:45.03#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.04:27:45.03#ibcon#ireg 8 cls_cnt 0 2006.286.04:27:45.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:27:45.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:27:45.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:27:45.03#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:27:45.03#ibcon#first serial, iclass 40, count 0 2006.286.04:27:45.03#ibcon#enter sib2, iclass 40, count 0 2006.286.04:27:45.03#ibcon#flushed, iclass 40, count 0 2006.286.04:27:45.03#ibcon#about to write, iclass 40, count 0 2006.286.04:27:45.03#ibcon#wrote, iclass 40, count 0 2006.286.04:27:45.03#ibcon#about to read 3, iclass 40, count 0 2006.286.04:27:45.04#ibcon#read 3, iclass 40, count 0 2006.286.04:27:45.04#ibcon#about to read 4, iclass 40, count 0 2006.286.04:27:45.04#ibcon#read 4, iclass 40, count 0 2006.286.04:27:45.04#ibcon#about to read 5, iclass 40, count 0 2006.286.04:27:45.04#ibcon#read 5, iclass 40, count 0 2006.286.04:27:45.04#ibcon#about to read 6, iclass 40, count 0 2006.286.04:27:45.04#ibcon#read 6, iclass 40, count 0 2006.286.04:27:45.04#ibcon#end of sib2, iclass 40, count 0 2006.286.04:27:45.04#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:27:45.05#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:27:45.05#ibcon#[25=BW32\r\n] 2006.286.04:27:45.05#ibcon#*before write, iclass 40, count 0 2006.286.04:27:45.05#ibcon#enter sib2, iclass 40, count 0 2006.286.04:27:45.05#ibcon#flushed, iclass 40, count 0 2006.286.04:27:45.05#ibcon#about to write, iclass 40, count 0 2006.286.04:27:45.05#ibcon#wrote, iclass 40, count 0 2006.286.04:27:45.05#ibcon#about to read 3, iclass 40, count 0 2006.286.04:27:45.07#ibcon#read 3, iclass 40, count 0 2006.286.04:27:45.07#ibcon#about to read 4, iclass 40, count 0 2006.286.04:27:45.07#ibcon#read 4, iclass 40, count 0 2006.286.04:27:45.07#ibcon#about to read 5, iclass 40, count 0 2006.286.04:27:45.07#ibcon#read 5, iclass 40, count 0 2006.286.04:27:45.08#ibcon#about to read 6, iclass 40, count 0 2006.286.04:27:45.08#ibcon#read 6, iclass 40, count 0 2006.286.04:27:45.08#ibcon#end of sib2, iclass 40, count 0 2006.286.04:27:45.08#ibcon#*after write, iclass 40, count 0 2006.286.04:27:45.08#ibcon#*before return 0, iclass 40, count 0 2006.286.04:27:45.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:27:45.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:27:45.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:27:45.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:27:45.08$vck44/vbbw=wide 2006.286.04:27:45.08#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.04:27:45.08#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.04:27:45.08#ibcon#ireg 8 cls_cnt 0 2006.286.04:27:45.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:27:45.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:27:45.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:27:45.15#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:27:45.15#ibcon#first serial, iclass 4, count 0 2006.286.04:27:45.15#ibcon#enter sib2, iclass 4, count 0 2006.286.04:27:45.15#ibcon#flushed, iclass 4, count 0 2006.286.04:27:45.15#ibcon#about to write, iclass 4, count 0 2006.286.04:27:45.15#ibcon#wrote, iclass 4, count 0 2006.286.04:27:45.15#ibcon#about to read 3, iclass 4, count 0 2006.286.04:27:45.16#ibcon#read 3, iclass 4, count 0 2006.286.04:27:45.16#ibcon#about to read 4, iclass 4, count 0 2006.286.04:27:45.16#ibcon#read 4, iclass 4, count 0 2006.286.04:27:45.16#ibcon#about to read 5, iclass 4, count 0 2006.286.04:27:45.16#ibcon#read 5, iclass 4, count 0 2006.286.04:27:45.16#ibcon#about to read 6, iclass 4, count 0 2006.286.04:27:45.16#ibcon#read 6, iclass 4, count 0 2006.286.04:27:45.16#ibcon#end of sib2, iclass 4, count 0 2006.286.04:27:45.16#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:27:45.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:27:45.17#ibcon#[27=BW32\r\n] 2006.286.04:27:45.17#ibcon#*before write, iclass 4, count 0 2006.286.04:27:45.17#ibcon#enter sib2, iclass 4, count 0 2006.286.04:27:45.17#ibcon#flushed, iclass 4, count 0 2006.286.04:27:45.17#ibcon#about to write, iclass 4, count 0 2006.286.04:27:45.17#ibcon#wrote, iclass 4, count 0 2006.286.04:27:45.17#ibcon#about to read 3, iclass 4, count 0 2006.286.04:27:45.19#ibcon#read 3, iclass 4, count 0 2006.286.04:27:45.19#ibcon#about to read 4, iclass 4, count 0 2006.286.04:27:45.19#ibcon#read 4, iclass 4, count 0 2006.286.04:27:45.19#ibcon#about to read 5, iclass 4, count 0 2006.286.04:27:45.19#ibcon#read 5, iclass 4, count 0 2006.286.04:27:45.19#ibcon#about to read 6, iclass 4, count 0 2006.286.04:27:45.19#ibcon#read 6, iclass 4, count 0 2006.286.04:27:45.19#ibcon#end of sib2, iclass 4, count 0 2006.286.04:27:45.19#ibcon#*after write, iclass 4, count 0 2006.286.04:27:45.20#ibcon#*before return 0, iclass 4, count 0 2006.286.04:27:45.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:27:45.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:27:45.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:27:45.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:27:45.20$setupk4/ifdk4 2006.286.04:27:45.20$ifdk4/lo= 2006.286.04:27:45.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:27:45.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:27:45.20$ifdk4/patch= 2006.286.04:27:45.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:27:45.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:27:45.20$setupk4/!*+20s 2006.286.04:27:49.20#abcon#<5=/04 3.5 7.2 22.16 741014.8\r\n> 2006.286.04:27:49.22#abcon#{5=INTERFACE CLEAR} 2006.286.04:27:49.28#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:27:58.62$setupk4/"tpicd 2006.286.04:27:58.62$setupk4/echo=off 2006.286.04:27:58.62$setupk4/xlog=off 2006.286.04:27:58.62:!2006.286.04:28:55 2006.286.04:28:34.14#trakl#Source acquired 2006.286.04:28:35.14#flagr#flagr/antenna,acquired 2006.286.04:28:55.00:preob 2006.286.04:28:55.14/onsource/TRACKING 2006.286.04:28:55.14:!2006.286.04:29:05 2006.286.04:29:00.14#trakl#Off source 2006.286.04:29:00.14?ERROR st -7 Antenna off-source! 2006.286.04:29:00.14#trakl#az 188.919 el 11.054 azerr*cos(el) 0.0182 elerr -0.0008 2006.286.04:29:00.14#flagr#flagr/antenna,off-source 2006.286.04:29:05.01:"tape 2006.286.04:29:05.01:"st=record 2006.286.04:29:05.01:data_valid=on 2006.286.04:29:05.02:midob 2006.286.04:29:06.14#trakl#Source re-acquired 2006.286.04:29:06.14/onsource/TRACKING 2006.286.04:29:06.15/wx/22.16,1014.7,74 2006.286.04:29:06.32/cable/+6.4959E-03 2006.286.04:29:07.14#flagr#flagr/antenna,re-acquired 2006.286.04:29:07.41/va/01,07,usb,yes,37,40 2006.286.04:29:07.41/va/02,06,usb,yes,37,37 2006.286.04:29:07.41/va/03,07,usb,yes,36,38 2006.286.04:29:07.41/va/04,06,usb,yes,38,40 2006.286.04:29:07.41/va/05,03,usb,yes,37,38 2006.286.04:29:07.41/va/06,04,usb,yes,34,33 2006.286.04:29:07.41/va/07,04,usb,yes,34,35 2006.286.04:29:07.41/va/08,03,usb,yes,35,43 2006.286.04:29:07.64/valo/01,524.99,yes,locked 2006.286.04:29:07.64/valo/02,534.99,yes,locked 2006.286.04:29:07.64/valo/03,564.99,yes,locked 2006.286.04:29:07.64/valo/04,624.99,yes,locked 2006.286.04:29:07.64/valo/05,734.99,yes,locked 2006.286.04:29:07.64/valo/06,814.99,yes,locked 2006.286.04:29:07.64/valo/07,864.99,yes,locked 2006.286.04:29:07.64/valo/08,884.99,yes,locked 2006.286.04:29:08.73/vb/01,04,usb,yes,33,31 2006.286.04:29:08.73/vb/02,05,usb,yes,32,31 2006.286.04:29:08.73/vb/03,04,usb,yes,32,36 2006.286.04:29:08.73/vb/04,05,usb,yes,33,32 2006.286.04:29:08.73/vb/05,04,usb,yes,29,32 2006.286.04:29:08.73/vb/06,03,usb,yes,42,37 2006.286.04:29:08.73/vb/07,04,usb,yes,34,34 2006.286.04:29:08.73/vb/08,04,usb,yes,31,34 2006.286.04:29:08.96/vblo/01,629.99,yes,locked 2006.286.04:29:08.96/vblo/02,634.99,yes,locked 2006.286.04:29:08.96/vblo/03,649.99,yes,locked 2006.286.04:29:08.96/vblo/04,679.99,yes,locked 2006.286.04:29:08.96/vblo/05,709.99,yes,locked 2006.286.04:29:08.96/vblo/06,719.99,yes,locked 2006.286.04:29:08.96/vblo/07,734.99,yes,locked 2006.286.04:29:08.96/vblo/08,744.99,yes,locked 2006.286.04:29:09.11/vabw/8 2006.286.04:29:09.26/vbbw/8 2006.286.04:29:09.35/xfe/off,on,12.2 2006.286.04:29:09.73/ifatt/23,28,28,28 2006.286.04:29:10.07/fmout-gps/S +2.73E-07 2006.286.04:29:10.10:!2006.286.04:29:45 2006.286.04:29:45.01:data_valid=off 2006.286.04:29:45.02:"et 2006.286.04:29:45.02:!+3s 2006.286.04:29:48.04:"tape 2006.286.04:29:48.04:postob 2006.286.04:29:48.18/cable/+6.4959E-03 2006.286.04:29:48.19/wx/22.16,1014.7,75 2006.286.04:29:48.24/fmout-gps/S +2.71E-07 2006.286.04:29:48.24:scan_name=286-0434,jd0610,280 2006.286.04:29:48.25:source=1622-253,162546.89,-252738.3,2000.0,cw 2006.286.04:29:49.14#flagr#flagr/antenna,new-source 2006.286.04:29:49.15:checkk5 2006.286.04:29:49.51/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:29:49.93/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:29:50.33/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:29:50.85/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:29:51.22/chk_obsdata//k5ts1/T2860429??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:29:51.70/chk_obsdata//k5ts2/T2860429??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:29:52.04/chk_obsdata//k5ts3/T2860429??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:29:52.41/chk_obsdata//k5ts4/T2860429??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:29:53.40/k5log//k5ts1_log_newline 2006.286.04:29:54.15/k5log//k5ts2_log_newline 2006.286.04:29:55.04/k5log//k5ts3_log_newline 2006.286.04:29:56.25/k5log//k5ts4_log_newline 2006.286.04:29:56.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:29:56.27:setupk4=1 2006.286.04:29:56.27$setupk4/echo=on 2006.286.04:29:56.27$setupk4/pcalon 2006.286.04:29:56.27$pcalon/"no phase cal control is implemented here 2006.286.04:29:56.27$setupk4/"tpicd=stop 2006.286.04:29:56.27$setupk4/"rec=synch_on 2006.286.04:29:56.27$setupk4/"rec_mode=128 2006.286.04:29:56.27$setupk4/!* 2006.286.04:29:56.27$setupk4/recpk4 2006.286.04:29:56.27$recpk4/recpatch= 2006.286.04:29:56.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:29:56.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:29:56.28$setupk4/vck44 2006.286.04:29:56.28$vck44/valo=1,524.99 2006.286.04:29:56.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.04:29:56.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.04:29:56.28#ibcon#ireg 17 cls_cnt 0 2006.286.04:29:56.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:29:56.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:29:56.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:29:56.28#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:29:56.28#ibcon#first serial, iclass 29, count 0 2006.286.04:29:56.28#ibcon#enter sib2, iclass 29, count 0 2006.286.04:29:56.28#ibcon#flushed, iclass 29, count 0 2006.286.04:29:56.28#ibcon#about to write, iclass 29, count 0 2006.286.04:29:56.28#ibcon#wrote, iclass 29, count 0 2006.286.04:29:56.28#ibcon#about to read 3, iclass 29, count 0 2006.286.04:29:56.29#ibcon#read 3, iclass 29, count 0 2006.286.04:29:56.29#ibcon#about to read 4, iclass 29, count 0 2006.286.04:29:56.29#ibcon#read 4, iclass 29, count 0 2006.286.04:29:56.29#ibcon#about to read 5, iclass 29, count 0 2006.286.04:29:56.29#ibcon#read 5, iclass 29, count 0 2006.286.04:29:56.29#ibcon#about to read 6, iclass 29, count 0 2006.286.04:29:56.29#ibcon#read 6, iclass 29, count 0 2006.286.04:29:56.29#ibcon#end of sib2, iclass 29, count 0 2006.286.04:29:56.29#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:29:56.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:29:56.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:29:56.29#ibcon#*before write, iclass 29, count 0 2006.286.04:29:56.29#ibcon#enter sib2, iclass 29, count 0 2006.286.04:29:56.29#ibcon#flushed, iclass 29, count 0 2006.286.04:29:56.29#ibcon#about to write, iclass 29, count 0 2006.286.04:29:56.29#ibcon#wrote, iclass 29, count 0 2006.286.04:29:56.29#ibcon#about to read 3, iclass 29, count 0 2006.286.04:29:56.34#ibcon#read 3, iclass 29, count 0 2006.286.04:29:56.34#ibcon#about to read 4, iclass 29, count 0 2006.286.04:29:56.34#ibcon#read 4, iclass 29, count 0 2006.286.04:29:56.34#ibcon#about to read 5, iclass 29, count 0 2006.286.04:29:56.34#ibcon#read 5, iclass 29, count 0 2006.286.04:29:56.34#ibcon#about to read 6, iclass 29, count 0 2006.286.04:29:56.34#ibcon#read 6, iclass 29, count 0 2006.286.04:29:56.34#ibcon#end of sib2, iclass 29, count 0 2006.286.04:29:56.34#ibcon#*after write, iclass 29, count 0 2006.286.04:29:56.34#ibcon#*before return 0, iclass 29, count 0 2006.286.04:29:56.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:29:56.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:29:56.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:29:56.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:29:56.35$vck44/va=1,7 2006.286.04:29:56.35#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.04:29:56.35#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.04:29:56.35#ibcon#ireg 11 cls_cnt 2 2006.286.04:29:56.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:29:56.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:29:56.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:29:56.35#ibcon#enter wrdev, iclass 31, count 2 2006.286.04:29:56.35#ibcon#first serial, iclass 31, count 2 2006.286.04:29:56.35#ibcon#enter sib2, iclass 31, count 2 2006.286.04:29:56.35#ibcon#flushed, iclass 31, count 2 2006.286.04:29:56.35#ibcon#about to write, iclass 31, count 2 2006.286.04:29:56.35#ibcon#wrote, iclass 31, count 2 2006.286.04:29:56.35#ibcon#about to read 3, iclass 31, count 2 2006.286.04:29:56.36#ibcon#read 3, iclass 31, count 2 2006.286.04:29:56.36#ibcon#about to read 4, iclass 31, count 2 2006.286.04:29:56.36#ibcon#read 4, iclass 31, count 2 2006.286.04:29:56.36#ibcon#about to read 5, iclass 31, count 2 2006.286.04:29:56.36#ibcon#read 5, iclass 31, count 2 2006.286.04:29:56.36#ibcon#about to read 6, iclass 31, count 2 2006.286.04:29:56.36#ibcon#read 6, iclass 31, count 2 2006.286.04:29:56.36#ibcon#end of sib2, iclass 31, count 2 2006.286.04:29:56.36#ibcon#*mode == 0, iclass 31, count 2 2006.286.04:29:56.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.04:29:56.36#ibcon#[25=AT01-07\r\n] 2006.286.04:29:56.36#ibcon#*before write, iclass 31, count 2 2006.286.04:29:56.36#ibcon#enter sib2, iclass 31, count 2 2006.286.04:29:56.36#ibcon#flushed, iclass 31, count 2 2006.286.04:29:56.36#ibcon#about to write, iclass 31, count 2 2006.286.04:29:56.36#ibcon#wrote, iclass 31, count 2 2006.286.04:29:56.36#ibcon#about to read 3, iclass 31, count 2 2006.286.04:29:56.39#ibcon#read 3, iclass 31, count 2 2006.286.04:29:56.39#ibcon#about to read 4, iclass 31, count 2 2006.286.04:29:56.39#ibcon#read 4, iclass 31, count 2 2006.286.04:29:56.39#ibcon#about to read 5, iclass 31, count 2 2006.286.04:29:56.39#ibcon#read 5, iclass 31, count 2 2006.286.04:29:56.39#ibcon#about to read 6, iclass 31, count 2 2006.286.04:29:56.39#ibcon#read 6, iclass 31, count 2 2006.286.04:29:56.39#ibcon#end of sib2, iclass 31, count 2 2006.286.04:29:56.39#ibcon#*after write, iclass 31, count 2 2006.286.04:29:56.39#ibcon#*before return 0, iclass 31, count 2 2006.286.04:29:56.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:29:56.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:29:56.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.04:29:56.39#ibcon#ireg 7 cls_cnt 0 2006.286.04:29:56.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:29:56.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:29:56.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:29:56.51#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:29:56.51#ibcon#first serial, iclass 31, count 0 2006.286.04:29:56.51#ibcon#enter sib2, iclass 31, count 0 2006.286.04:29:56.51#ibcon#flushed, iclass 31, count 0 2006.286.04:29:56.51#ibcon#about to write, iclass 31, count 0 2006.286.04:29:56.51#ibcon#wrote, iclass 31, count 0 2006.286.04:29:56.51#ibcon#about to read 3, iclass 31, count 0 2006.286.04:29:56.53#ibcon#read 3, iclass 31, count 0 2006.286.04:29:56.53#ibcon#about to read 4, iclass 31, count 0 2006.286.04:29:56.53#ibcon#read 4, iclass 31, count 0 2006.286.04:29:56.53#ibcon#about to read 5, iclass 31, count 0 2006.286.04:29:56.53#ibcon#read 5, iclass 31, count 0 2006.286.04:29:56.53#ibcon#about to read 6, iclass 31, count 0 2006.286.04:29:56.53#ibcon#read 6, iclass 31, count 0 2006.286.04:29:56.53#ibcon#end of sib2, iclass 31, count 0 2006.286.04:29:56.53#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:29:56.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:29:56.53#ibcon#[25=USB\r\n] 2006.286.04:29:56.53#ibcon#*before write, iclass 31, count 0 2006.286.04:29:56.53#ibcon#enter sib2, iclass 31, count 0 2006.286.04:29:56.53#ibcon#flushed, iclass 31, count 0 2006.286.04:29:56.53#ibcon#about to write, iclass 31, count 0 2006.286.04:29:56.53#ibcon#wrote, iclass 31, count 0 2006.286.04:29:56.53#ibcon#about to read 3, iclass 31, count 0 2006.286.04:29:56.56#ibcon#read 3, iclass 31, count 0 2006.286.04:29:56.56#ibcon#about to read 4, iclass 31, count 0 2006.286.04:29:56.56#ibcon#read 4, iclass 31, count 0 2006.286.04:29:56.56#ibcon#about to read 5, iclass 31, count 0 2006.286.04:29:56.56#ibcon#read 5, iclass 31, count 0 2006.286.04:29:56.56#ibcon#about to read 6, iclass 31, count 0 2006.286.04:29:56.56#ibcon#read 6, iclass 31, count 0 2006.286.04:29:56.56#ibcon#end of sib2, iclass 31, count 0 2006.286.04:29:56.56#ibcon#*after write, iclass 31, count 0 2006.286.04:29:56.56#ibcon#*before return 0, iclass 31, count 0 2006.286.04:29:56.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:29:56.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:29:56.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:29:56.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:29:56.56$vck44/valo=2,534.99 2006.286.04:29:56.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.04:29:56.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.04:29:56.56#ibcon#ireg 17 cls_cnt 0 2006.286.04:29:56.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:29:56.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:29:56.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:29:56.56#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:29:56.56#ibcon#first serial, iclass 33, count 0 2006.286.04:29:56.56#ibcon#enter sib2, iclass 33, count 0 2006.286.04:29:56.56#ibcon#flushed, iclass 33, count 0 2006.286.04:29:56.56#ibcon#about to write, iclass 33, count 0 2006.286.04:29:56.57#ibcon#wrote, iclass 33, count 0 2006.286.04:29:56.57#ibcon#about to read 3, iclass 33, count 0 2006.286.04:29:56.58#ibcon#read 3, iclass 33, count 0 2006.286.04:29:56.58#ibcon#about to read 4, iclass 33, count 0 2006.286.04:29:56.58#ibcon#read 4, iclass 33, count 0 2006.286.04:29:56.67#ibcon#about to read 5, iclass 33, count 0 2006.286.04:29:56.67#ibcon#read 5, iclass 33, count 0 2006.286.04:29:56.67#ibcon#about to read 6, iclass 33, count 0 2006.286.04:29:56.67#ibcon#read 6, iclass 33, count 0 2006.286.04:29:56.67#ibcon#end of sib2, iclass 33, count 0 2006.286.04:29:56.67#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:29:56.67#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:29:56.67#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:29:56.67#ibcon#*before write, iclass 33, count 0 2006.286.04:29:56.67#ibcon#enter sib2, iclass 33, count 0 2006.286.04:29:56.67#ibcon#flushed, iclass 33, count 0 2006.286.04:29:56.67#ibcon#about to write, iclass 33, count 0 2006.286.04:29:56.67#ibcon#wrote, iclass 33, count 0 2006.286.04:29:56.67#ibcon#about to read 3, iclass 33, count 0 2006.286.04:29:56.71#ibcon#read 3, iclass 33, count 0 2006.286.04:29:56.71#ibcon#about to read 4, iclass 33, count 0 2006.286.04:29:56.71#ibcon#read 4, iclass 33, count 0 2006.286.04:29:56.71#ibcon#about to read 5, iclass 33, count 0 2006.286.04:29:56.71#ibcon#read 5, iclass 33, count 0 2006.286.04:29:56.71#ibcon#about to read 6, iclass 33, count 0 2006.286.04:29:56.71#ibcon#read 6, iclass 33, count 0 2006.286.04:29:56.71#ibcon#end of sib2, iclass 33, count 0 2006.286.04:29:56.71#ibcon#*after write, iclass 33, count 0 2006.286.04:29:56.71#ibcon#*before return 0, iclass 33, count 0 2006.286.04:29:56.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:29:56.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:29:56.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:29:56.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:29:56.72$vck44/va=2,6 2006.286.04:29:56.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.04:29:56.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.04:29:56.72#ibcon#ireg 11 cls_cnt 2 2006.286.04:29:56.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:29:56.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:29:56.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:29:56.72#ibcon#enter wrdev, iclass 35, count 2 2006.286.04:29:56.72#ibcon#first serial, iclass 35, count 2 2006.286.04:29:56.72#ibcon#enter sib2, iclass 35, count 2 2006.286.04:29:56.72#ibcon#flushed, iclass 35, count 2 2006.286.04:29:56.72#ibcon#about to write, iclass 35, count 2 2006.286.04:29:56.72#ibcon#wrote, iclass 35, count 2 2006.286.04:29:56.72#ibcon#about to read 3, iclass 35, count 2 2006.286.04:29:56.73#ibcon#read 3, iclass 35, count 2 2006.286.04:29:56.73#ibcon#about to read 4, iclass 35, count 2 2006.286.04:29:56.73#ibcon#read 4, iclass 35, count 2 2006.286.04:29:56.73#ibcon#about to read 5, iclass 35, count 2 2006.286.04:29:56.73#ibcon#read 5, iclass 35, count 2 2006.286.04:29:56.73#ibcon#about to read 6, iclass 35, count 2 2006.286.04:29:56.73#ibcon#read 6, iclass 35, count 2 2006.286.04:29:56.73#ibcon#end of sib2, iclass 35, count 2 2006.286.04:29:56.73#ibcon#*mode == 0, iclass 35, count 2 2006.286.04:29:56.73#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.04:29:56.73#ibcon#[25=AT02-06\r\n] 2006.286.04:29:56.73#ibcon#*before write, iclass 35, count 2 2006.286.04:29:56.73#ibcon#enter sib2, iclass 35, count 2 2006.286.04:29:56.73#ibcon#flushed, iclass 35, count 2 2006.286.04:29:56.73#ibcon#about to write, iclass 35, count 2 2006.286.04:29:56.73#ibcon#wrote, iclass 35, count 2 2006.286.04:29:56.73#ibcon#about to read 3, iclass 35, count 2 2006.286.04:29:56.76#ibcon#read 3, iclass 35, count 2 2006.286.04:29:56.76#ibcon#about to read 4, iclass 35, count 2 2006.286.04:29:56.76#ibcon#read 4, iclass 35, count 2 2006.286.04:29:56.76#ibcon#about to read 5, iclass 35, count 2 2006.286.04:29:56.76#ibcon#read 5, iclass 35, count 2 2006.286.04:29:56.76#ibcon#about to read 6, iclass 35, count 2 2006.286.04:29:56.76#ibcon#read 6, iclass 35, count 2 2006.286.04:29:56.76#ibcon#end of sib2, iclass 35, count 2 2006.286.04:29:56.76#ibcon#*after write, iclass 35, count 2 2006.286.04:29:56.76#ibcon#*before return 0, iclass 35, count 2 2006.286.04:29:56.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:29:56.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:29:56.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.04:29:56.76#ibcon#ireg 7 cls_cnt 0 2006.286.04:29:56.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:29:56.88#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:29:56.88#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:29:56.88#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:29:56.88#ibcon#first serial, iclass 35, count 0 2006.286.04:29:56.88#ibcon#enter sib2, iclass 35, count 0 2006.286.04:29:56.88#ibcon#flushed, iclass 35, count 0 2006.286.04:29:56.88#ibcon#about to write, iclass 35, count 0 2006.286.04:29:56.88#ibcon#wrote, iclass 35, count 0 2006.286.04:29:56.88#ibcon#about to read 3, iclass 35, count 0 2006.286.04:29:56.90#ibcon#read 3, iclass 35, count 0 2006.286.04:29:57.54#ibcon#about to read 4, iclass 35, count 0 2006.286.04:29:57.54#ibcon#read 4, iclass 35, count 0 2006.286.04:29:57.54#ibcon#about to read 5, iclass 35, count 0 2006.286.04:29:57.54#ibcon#read 5, iclass 35, count 0 2006.286.04:29:57.54#ibcon#about to read 6, iclass 35, count 0 2006.286.04:29:57.54#ibcon#read 6, iclass 35, count 0 2006.286.04:29:57.54#ibcon#end of sib2, iclass 35, count 0 2006.286.04:29:57.54#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:29:57.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:29:57.54#ibcon#[25=USB\r\n] 2006.286.04:29:57.54#ibcon#*before write, iclass 35, count 0 2006.286.04:29:57.54#ibcon#enter sib2, iclass 35, count 0 2006.286.04:29:57.54#ibcon#flushed, iclass 35, count 0 2006.286.04:29:57.54#ibcon#about to write, iclass 35, count 0 2006.286.04:29:57.54#ibcon#wrote, iclass 35, count 0 2006.286.04:29:57.54#ibcon#about to read 3, iclass 35, count 0 2006.286.04:29:57.56#ibcon#read 3, iclass 35, count 0 2006.286.04:29:57.56#ibcon#about to read 4, iclass 35, count 0 2006.286.04:29:57.56#ibcon#read 4, iclass 35, count 0 2006.286.04:29:57.56#ibcon#about to read 5, iclass 35, count 0 2006.286.04:29:57.56#ibcon#read 5, iclass 35, count 0 2006.286.04:29:57.56#ibcon#about to read 6, iclass 35, count 0 2006.286.04:29:57.56#ibcon#read 6, iclass 35, count 0 2006.286.04:29:57.56#ibcon#end of sib2, iclass 35, count 0 2006.286.04:29:57.56#ibcon#*after write, iclass 35, count 0 2006.286.04:29:57.56#ibcon#*before return 0, iclass 35, count 0 2006.286.04:29:57.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:29:57.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:29:57.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:29:57.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:29:57.57$vck44/valo=3,564.99 2006.286.04:29:57.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.04:29:57.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.04:29:57.57#ibcon#ireg 17 cls_cnt 0 2006.286.04:29:57.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:29:57.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:29:57.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:29:57.57#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:29:57.57#ibcon#first serial, iclass 37, count 0 2006.286.04:29:57.57#ibcon#enter sib2, iclass 37, count 0 2006.286.04:29:57.57#ibcon#flushed, iclass 37, count 0 2006.286.04:29:57.57#ibcon#about to write, iclass 37, count 0 2006.286.04:29:57.57#ibcon#wrote, iclass 37, count 0 2006.286.04:29:57.57#ibcon#about to read 3, iclass 37, count 0 2006.286.04:29:57.58#ibcon#read 3, iclass 37, count 0 2006.286.04:29:57.58#ibcon#about to read 4, iclass 37, count 0 2006.286.04:29:57.58#ibcon#read 4, iclass 37, count 0 2006.286.04:29:57.58#ibcon#about to read 5, iclass 37, count 0 2006.286.04:29:57.58#ibcon#read 5, iclass 37, count 0 2006.286.04:29:57.58#ibcon#about to read 6, iclass 37, count 0 2006.286.04:29:57.58#ibcon#read 6, iclass 37, count 0 2006.286.04:29:57.58#ibcon#end of sib2, iclass 37, count 0 2006.286.04:29:57.58#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:29:57.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:29:57.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:29:57.58#ibcon#*before write, iclass 37, count 0 2006.286.04:29:57.58#ibcon#enter sib2, iclass 37, count 0 2006.286.04:29:57.58#ibcon#flushed, iclass 37, count 0 2006.286.04:29:57.58#ibcon#about to write, iclass 37, count 0 2006.286.04:29:57.58#ibcon#wrote, iclass 37, count 0 2006.286.04:29:57.58#ibcon#about to read 3, iclass 37, count 0 2006.286.04:29:57.62#ibcon#read 3, iclass 37, count 0 2006.286.04:29:57.62#ibcon#about to read 4, iclass 37, count 0 2006.286.04:29:57.62#ibcon#read 4, iclass 37, count 0 2006.286.04:29:57.62#ibcon#about to read 5, iclass 37, count 0 2006.286.04:29:57.62#ibcon#read 5, iclass 37, count 0 2006.286.04:29:57.62#ibcon#about to read 6, iclass 37, count 0 2006.286.04:29:57.62#ibcon#read 6, iclass 37, count 0 2006.286.04:29:57.62#ibcon#end of sib2, iclass 37, count 0 2006.286.04:29:57.62#ibcon#*after write, iclass 37, count 0 2006.286.04:29:57.62#ibcon#*before return 0, iclass 37, count 0 2006.286.04:29:57.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:29:57.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:29:57.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:29:57.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:29:57.63$vck44/va=3,7 2006.286.04:29:57.63#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.04:29:57.63#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.04:29:57.63#ibcon#ireg 11 cls_cnt 2 2006.286.04:29:57.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:29:57.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:29:57.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:29:57.67#ibcon#enter wrdev, iclass 39, count 2 2006.286.04:29:57.67#ibcon#first serial, iclass 39, count 2 2006.286.04:29:57.67#ibcon#enter sib2, iclass 39, count 2 2006.286.04:29:57.67#ibcon#flushed, iclass 39, count 2 2006.286.04:29:57.67#ibcon#about to write, iclass 39, count 2 2006.286.04:29:57.67#ibcon#wrote, iclass 39, count 2 2006.286.04:29:57.67#ibcon#about to read 3, iclass 39, count 2 2006.286.04:29:57.69#ibcon#read 3, iclass 39, count 2 2006.286.04:29:57.69#ibcon#about to read 4, iclass 39, count 2 2006.286.04:29:57.69#ibcon#read 4, iclass 39, count 2 2006.286.04:29:57.69#ibcon#about to read 5, iclass 39, count 2 2006.286.04:29:57.69#ibcon#read 5, iclass 39, count 2 2006.286.04:29:57.69#ibcon#about to read 6, iclass 39, count 2 2006.286.04:29:57.69#ibcon#read 6, iclass 39, count 2 2006.286.04:29:57.69#ibcon#end of sib2, iclass 39, count 2 2006.286.04:29:57.69#ibcon#*mode == 0, iclass 39, count 2 2006.286.04:29:57.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.04:29:57.69#ibcon#[25=AT03-07\r\n] 2006.286.04:29:57.69#ibcon#*before write, iclass 39, count 2 2006.286.04:29:57.69#ibcon#enter sib2, iclass 39, count 2 2006.286.04:29:57.69#ibcon#flushed, iclass 39, count 2 2006.286.04:29:57.69#ibcon#about to write, iclass 39, count 2 2006.286.04:29:57.69#ibcon#wrote, iclass 39, count 2 2006.286.04:29:57.69#ibcon#about to read 3, iclass 39, count 2 2006.286.04:29:57.72#ibcon#read 3, iclass 39, count 2 2006.286.04:29:57.72#ibcon#about to read 4, iclass 39, count 2 2006.286.04:29:57.72#ibcon#read 4, iclass 39, count 2 2006.286.04:29:57.72#ibcon#about to read 5, iclass 39, count 2 2006.286.04:29:57.72#ibcon#read 5, iclass 39, count 2 2006.286.04:29:57.72#ibcon#about to read 6, iclass 39, count 2 2006.286.04:29:57.72#ibcon#read 6, iclass 39, count 2 2006.286.04:29:57.72#ibcon#end of sib2, iclass 39, count 2 2006.286.04:29:57.72#ibcon#*after write, iclass 39, count 2 2006.286.04:29:57.72#ibcon#*before return 0, iclass 39, count 2 2006.286.04:29:57.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:29:57.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:29:57.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.04:29:57.72#ibcon#ireg 7 cls_cnt 0 2006.286.04:29:57.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:29:57.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:29:57.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:29:57.84#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:29:57.84#ibcon#first serial, iclass 39, count 0 2006.286.04:29:57.84#ibcon#enter sib2, iclass 39, count 0 2006.286.04:29:57.84#ibcon#flushed, iclass 39, count 0 2006.286.04:29:57.84#ibcon#about to write, iclass 39, count 0 2006.286.04:29:57.84#ibcon#wrote, iclass 39, count 0 2006.286.04:29:57.84#ibcon#about to read 3, iclass 39, count 0 2006.286.04:29:57.86#ibcon#read 3, iclass 39, count 0 2006.286.04:29:57.86#ibcon#about to read 4, iclass 39, count 0 2006.286.04:29:57.86#ibcon#read 4, iclass 39, count 0 2006.286.04:29:57.86#ibcon#about to read 5, iclass 39, count 0 2006.286.04:29:57.86#ibcon#read 5, iclass 39, count 0 2006.286.04:29:57.86#ibcon#about to read 6, iclass 39, count 0 2006.286.04:29:57.86#ibcon#read 6, iclass 39, count 0 2006.286.04:29:57.86#ibcon#end of sib2, iclass 39, count 0 2006.286.04:29:57.86#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:29:57.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:29:57.86#ibcon#[25=USB\r\n] 2006.286.04:29:57.86#ibcon#*before write, iclass 39, count 0 2006.286.04:29:57.86#ibcon#enter sib2, iclass 39, count 0 2006.286.04:29:57.86#ibcon#flushed, iclass 39, count 0 2006.286.04:29:57.86#ibcon#about to write, iclass 39, count 0 2006.286.04:29:57.86#ibcon#wrote, iclass 39, count 0 2006.286.04:29:57.86#ibcon#about to read 3, iclass 39, count 0 2006.286.04:29:57.89#ibcon#read 3, iclass 39, count 0 2006.286.04:29:57.89#ibcon#about to read 4, iclass 39, count 0 2006.286.04:29:57.89#ibcon#read 4, iclass 39, count 0 2006.286.04:29:57.89#ibcon#about to read 5, iclass 39, count 0 2006.286.04:29:57.89#ibcon#read 5, iclass 39, count 0 2006.286.04:29:57.89#ibcon#about to read 6, iclass 39, count 0 2006.286.04:29:57.89#ibcon#read 6, iclass 39, count 0 2006.286.04:29:57.89#ibcon#end of sib2, iclass 39, count 0 2006.286.04:29:57.89#ibcon#*after write, iclass 39, count 0 2006.286.04:29:57.89#ibcon#*before return 0, iclass 39, count 0 2006.286.04:29:57.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:29:57.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:29:57.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:29:57.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:29:57.90$vck44/valo=4,624.99 2006.286.04:29:57.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.04:29:57.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.04:29:57.90#ibcon#ireg 17 cls_cnt 0 2006.286.04:29:57.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:29:57.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:29:57.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:29:57.90#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:29:57.90#ibcon#first serial, iclass 3, count 0 2006.286.04:29:57.90#ibcon#enter sib2, iclass 3, count 0 2006.286.04:29:57.90#ibcon#flushed, iclass 3, count 0 2006.286.04:29:57.90#ibcon#about to write, iclass 3, count 0 2006.286.04:29:57.90#ibcon#wrote, iclass 3, count 0 2006.286.04:29:57.90#ibcon#about to read 3, iclass 3, count 0 2006.286.04:29:57.91#ibcon#read 3, iclass 3, count 0 2006.286.04:29:57.91#ibcon#about to read 4, iclass 3, count 0 2006.286.04:29:57.91#ibcon#read 4, iclass 3, count 0 2006.286.04:29:57.91#ibcon#about to read 5, iclass 3, count 0 2006.286.04:29:57.91#ibcon#read 5, iclass 3, count 0 2006.286.04:29:57.91#ibcon#about to read 6, iclass 3, count 0 2006.286.04:29:57.91#ibcon#read 6, iclass 3, count 0 2006.286.04:29:57.91#ibcon#end of sib2, iclass 3, count 0 2006.286.04:29:57.91#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:29:57.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:29:57.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:29:57.91#ibcon#*before write, iclass 3, count 0 2006.286.04:29:57.91#ibcon#enter sib2, iclass 3, count 0 2006.286.04:29:57.91#ibcon#flushed, iclass 3, count 0 2006.286.04:29:57.91#ibcon#about to write, iclass 3, count 0 2006.286.04:29:57.91#ibcon#wrote, iclass 3, count 0 2006.286.04:29:57.91#ibcon#about to read 3, iclass 3, count 0 2006.286.04:29:57.95#ibcon#read 3, iclass 3, count 0 2006.286.04:29:57.95#ibcon#about to read 4, iclass 3, count 0 2006.286.04:29:57.95#ibcon#read 4, iclass 3, count 0 2006.286.04:29:57.95#ibcon#about to read 5, iclass 3, count 0 2006.286.04:29:57.95#ibcon#read 5, iclass 3, count 0 2006.286.04:29:57.95#ibcon#about to read 6, iclass 3, count 0 2006.286.04:29:57.95#ibcon#read 6, iclass 3, count 0 2006.286.04:29:57.95#ibcon#end of sib2, iclass 3, count 0 2006.286.04:29:57.95#ibcon#*after write, iclass 3, count 0 2006.286.04:29:57.95#ibcon#*before return 0, iclass 3, count 0 2006.286.04:29:57.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:29:57.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:29:57.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:29:57.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:29:57.96$vck44/va=4,6 2006.286.04:29:57.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.04:29:57.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.04:29:57.96#ibcon#ireg 11 cls_cnt 2 2006.286.04:29:57.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:29:58.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:29:58.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:29:58.00#ibcon#enter wrdev, iclass 5, count 2 2006.286.04:29:58.00#ibcon#first serial, iclass 5, count 2 2006.286.04:29:58.00#ibcon#enter sib2, iclass 5, count 2 2006.286.04:29:58.00#ibcon#flushed, iclass 5, count 2 2006.286.04:29:58.00#ibcon#about to write, iclass 5, count 2 2006.286.04:29:58.00#ibcon#wrote, iclass 5, count 2 2006.286.04:29:58.00#ibcon#about to read 3, iclass 5, count 2 2006.286.04:29:58.02#ibcon#read 3, iclass 5, count 2 2006.286.04:29:58.02#ibcon#about to read 4, iclass 5, count 2 2006.286.04:29:58.02#ibcon#read 4, iclass 5, count 2 2006.286.04:29:58.02#ibcon#about to read 5, iclass 5, count 2 2006.286.04:29:58.02#ibcon#read 5, iclass 5, count 2 2006.286.04:29:58.02#ibcon#about to read 6, iclass 5, count 2 2006.286.04:29:58.02#ibcon#read 6, iclass 5, count 2 2006.286.04:29:58.02#ibcon#end of sib2, iclass 5, count 2 2006.286.04:29:58.02#ibcon#*mode == 0, iclass 5, count 2 2006.286.04:29:58.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.04:29:58.02#ibcon#[25=AT04-06\r\n] 2006.286.04:29:58.02#ibcon#*before write, iclass 5, count 2 2006.286.04:29:58.02#ibcon#enter sib2, iclass 5, count 2 2006.286.04:29:58.02#ibcon#flushed, iclass 5, count 2 2006.286.04:29:58.02#ibcon#about to write, iclass 5, count 2 2006.286.04:29:58.02#ibcon#wrote, iclass 5, count 2 2006.286.04:29:58.02#ibcon#about to read 3, iclass 5, count 2 2006.286.04:29:58.05#ibcon#read 3, iclass 5, count 2 2006.286.04:29:58.05#ibcon#about to read 4, iclass 5, count 2 2006.286.04:29:58.05#ibcon#read 4, iclass 5, count 2 2006.286.04:29:58.05#ibcon#about to read 5, iclass 5, count 2 2006.286.04:29:58.05#ibcon#read 5, iclass 5, count 2 2006.286.04:29:58.05#ibcon#about to read 6, iclass 5, count 2 2006.286.04:29:58.05#ibcon#read 6, iclass 5, count 2 2006.286.04:29:58.05#ibcon#end of sib2, iclass 5, count 2 2006.286.04:29:58.05#ibcon#*after write, iclass 5, count 2 2006.286.04:29:58.05#ibcon#*before return 0, iclass 5, count 2 2006.286.04:29:58.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:29:58.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:29:58.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.04:29:58.05#ibcon#ireg 7 cls_cnt 0 2006.286.04:29:58.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:29:58.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:29:58.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:29:58.17#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:29:58.17#ibcon#first serial, iclass 5, count 0 2006.286.04:29:58.17#ibcon#enter sib2, iclass 5, count 0 2006.286.04:29:58.17#ibcon#flushed, iclass 5, count 0 2006.286.04:29:58.17#ibcon#about to write, iclass 5, count 0 2006.286.04:29:58.17#ibcon#wrote, iclass 5, count 0 2006.286.04:29:58.17#ibcon#about to read 3, iclass 5, count 0 2006.286.04:29:58.19#ibcon#read 3, iclass 5, count 0 2006.286.04:29:58.19#ibcon#about to read 4, iclass 5, count 0 2006.286.04:29:58.19#ibcon#read 4, iclass 5, count 0 2006.286.04:29:58.19#ibcon#about to read 5, iclass 5, count 0 2006.286.04:29:58.19#ibcon#read 5, iclass 5, count 0 2006.286.04:29:58.19#ibcon#about to read 6, iclass 5, count 0 2006.286.04:29:58.19#ibcon#read 6, iclass 5, count 0 2006.286.04:29:58.19#ibcon#end of sib2, iclass 5, count 0 2006.286.04:29:58.19#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:29:58.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:29:58.19#ibcon#[25=USB\r\n] 2006.286.04:29:58.19#ibcon#*before write, iclass 5, count 0 2006.286.04:29:58.19#ibcon#enter sib2, iclass 5, count 0 2006.286.04:29:58.19#ibcon#flushed, iclass 5, count 0 2006.286.04:29:58.19#ibcon#about to write, iclass 5, count 0 2006.286.04:29:58.19#ibcon#wrote, iclass 5, count 0 2006.286.04:29:58.19#ibcon#about to read 3, iclass 5, count 0 2006.286.04:29:58.22#ibcon#read 3, iclass 5, count 0 2006.286.04:29:58.22#ibcon#about to read 4, iclass 5, count 0 2006.286.04:29:58.22#ibcon#read 4, iclass 5, count 0 2006.286.04:29:58.22#ibcon#about to read 5, iclass 5, count 0 2006.286.04:29:58.22#ibcon#read 5, iclass 5, count 0 2006.286.04:29:58.22#ibcon#about to read 6, iclass 5, count 0 2006.286.04:29:58.22#ibcon#read 6, iclass 5, count 0 2006.286.04:29:58.22#ibcon#end of sib2, iclass 5, count 0 2006.286.04:29:58.22#ibcon#*after write, iclass 5, count 0 2006.286.04:29:58.22#ibcon#*before return 0, iclass 5, count 0 2006.286.04:29:58.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:29:58.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:29:58.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:29:58.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:29:58.23$vck44/valo=5,734.99 2006.286.04:29:58.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.04:29:58.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.04:29:58.23#ibcon#ireg 17 cls_cnt 0 2006.286.04:29:58.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:29:58.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:29:58.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:29:58.23#ibcon#enter wrdev, iclass 7, count 0 2006.286.04:29:58.23#ibcon#first serial, iclass 7, count 0 2006.286.04:29:58.23#ibcon#enter sib2, iclass 7, count 0 2006.286.04:29:58.23#ibcon#flushed, iclass 7, count 0 2006.286.04:29:58.23#ibcon#about to write, iclass 7, count 0 2006.286.04:29:58.23#ibcon#wrote, iclass 7, count 0 2006.286.04:29:58.23#ibcon#about to read 3, iclass 7, count 0 2006.286.04:29:58.24#ibcon#read 3, iclass 7, count 0 2006.286.04:29:58.24#ibcon#about to read 4, iclass 7, count 0 2006.286.04:29:58.24#ibcon#read 4, iclass 7, count 0 2006.286.04:29:58.24#ibcon#about to read 5, iclass 7, count 0 2006.286.04:29:58.24#ibcon#read 5, iclass 7, count 0 2006.286.04:29:58.24#ibcon#about to read 6, iclass 7, count 0 2006.286.04:29:58.24#ibcon#read 6, iclass 7, count 0 2006.286.04:29:58.24#ibcon#end of sib2, iclass 7, count 0 2006.286.04:29:58.24#ibcon#*mode == 0, iclass 7, count 0 2006.286.04:29:58.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.04:29:58.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:29:58.24#ibcon#*before write, iclass 7, count 0 2006.286.04:29:58.24#ibcon#enter sib2, iclass 7, count 0 2006.286.04:29:58.24#ibcon#flushed, iclass 7, count 0 2006.286.04:29:58.24#ibcon#about to write, iclass 7, count 0 2006.286.04:29:58.24#ibcon#wrote, iclass 7, count 0 2006.286.04:29:58.24#ibcon#about to read 3, iclass 7, count 0 2006.286.04:29:58.28#ibcon#read 3, iclass 7, count 0 2006.286.04:29:58.28#ibcon#about to read 4, iclass 7, count 0 2006.286.04:29:58.28#ibcon#read 4, iclass 7, count 0 2006.286.04:29:58.28#ibcon#about to read 5, iclass 7, count 0 2006.286.04:29:58.28#ibcon#read 5, iclass 7, count 0 2006.286.04:29:58.28#ibcon#about to read 6, iclass 7, count 0 2006.286.04:29:58.28#ibcon#read 6, iclass 7, count 0 2006.286.04:29:58.28#ibcon#end of sib2, iclass 7, count 0 2006.286.04:29:58.28#ibcon#*after write, iclass 7, count 0 2006.286.04:29:58.28#ibcon#*before return 0, iclass 7, count 0 2006.286.04:29:58.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:29:58.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:29:58.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.04:29:58.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.04:29:58.29$vck44/va=5,3 2006.286.04:29:58.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.04:29:58.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.04:29:58.29#ibcon#ireg 11 cls_cnt 2 2006.286.04:29:58.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.04:29:58.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.04:29:58.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.04:29:58.33#ibcon#enter wrdev, iclass 11, count 2 2006.286.04:29:58.33#ibcon#first serial, iclass 11, count 2 2006.286.04:29:58.33#ibcon#enter sib2, iclass 11, count 2 2006.286.04:29:58.33#ibcon#flushed, iclass 11, count 2 2006.286.04:29:58.33#ibcon#about to write, iclass 11, count 2 2006.286.04:29:58.33#ibcon#wrote, iclass 11, count 2 2006.286.04:29:58.33#ibcon#about to read 3, iclass 11, count 2 2006.286.04:29:58.35#ibcon#read 3, iclass 11, count 2 2006.286.04:29:58.35#ibcon#about to read 4, iclass 11, count 2 2006.286.04:29:58.35#ibcon#read 4, iclass 11, count 2 2006.286.04:29:58.35#ibcon#about to read 5, iclass 11, count 2 2006.286.04:29:58.35#ibcon#read 5, iclass 11, count 2 2006.286.04:29:58.35#ibcon#about to read 6, iclass 11, count 2 2006.286.04:29:58.35#ibcon#read 6, iclass 11, count 2 2006.286.04:29:58.35#ibcon#end of sib2, iclass 11, count 2 2006.286.04:29:58.35#ibcon#*mode == 0, iclass 11, count 2 2006.286.04:29:58.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.04:29:58.35#ibcon#[25=AT05-03\r\n] 2006.286.04:29:58.35#ibcon#*before write, iclass 11, count 2 2006.286.04:29:58.35#ibcon#enter sib2, iclass 11, count 2 2006.286.04:29:58.35#ibcon#flushed, iclass 11, count 2 2006.286.04:29:58.35#ibcon#about to write, iclass 11, count 2 2006.286.04:29:58.35#ibcon#wrote, iclass 11, count 2 2006.286.04:29:58.35#ibcon#about to read 3, iclass 11, count 2 2006.286.04:29:58.38#ibcon#read 3, iclass 11, count 2 2006.286.04:29:58.38#ibcon#about to read 4, iclass 11, count 2 2006.286.04:29:58.38#ibcon#read 4, iclass 11, count 2 2006.286.04:29:58.38#ibcon#about to read 5, iclass 11, count 2 2006.286.04:29:58.38#ibcon#read 5, iclass 11, count 2 2006.286.04:29:58.38#ibcon#about to read 6, iclass 11, count 2 2006.286.04:29:58.38#ibcon#read 6, iclass 11, count 2 2006.286.04:29:58.38#ibcon#end of sib2, iclass 11, count 2 2006.286.04:29:58.38#ibcon#*after write, iclass 11, count 2 2006.286.04:29:58.38#ibcon#*before return 0, iclass 11, count 2 2006.286.04:29:58.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.04:29:58.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.04:29:58.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.04:29:58.38#ibcon#ireg 7 cls_cnt 0 2006.286.04:29:58.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.04:29:58.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.04:29:58.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.04:29:58.50#ibcon#enter wrdev, iclass 11, count 0 2006.286.04:29:58.50#ibcon#first serial, iclass 11, count 0 2006.286.04:29:58.50#ibcon#enter sib2, iclass 11, count 0 2006.286.04:29:58.50#ibcon#flushed, iclass 11, count 0 2006.286.04:29:58.50#ibcon#about to write, iclass 11, count 0 2006.286.04:29:58.50#ibcon#wrote, iclass 11, count 0 2006.286.04:29:58.50#ibcon#about to read 3, iclass 11, count 0 2006.286.04:29:58.52#ibcon#read 3, iclass 11, count 0 2006.286.04:29:58.52#ibcon#about to read 4, iclass 11, count 0 2006.286.04:29:58.52#ibcon#read 4, iclass 11, count 0 2006.286.04:29:58.52#ibcon#about to read 5, iclass 11, count 0 2006.286.04:29:58.52#ibcon#read 5, iclass 11, count 0 2006.286.04:29:58.52#ibcon#about to read 6, iclass 11, count 0 2006.286.04:29:58.52#ibcon#read 6, iclass 11, count 0 2006.286.04:29:58.52#ibcon#end of sib2, iclass 11, count 0 2006.286.04:29:58.52#ibcon#*mode == 0, iclass 11, count 0 2006.286.04:29:58.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.04:29:58.52#ibcon#[25=USB\r\n] 2006.286.04:29:58.52#ibcon#*before write, iclass 11, count 0 2006.286.04:29:58.52#ibcon#enter sib2, iclass 11, count 0 2006.286.04:29:58.52#ibcon#flushed, iclass 11, count 0 2006.286.04:29:58.52#ibcon#about to write, iclass 11, count 0 2006.286.04:29:58.52#ibcon#wrote, iclass 11, count 0 2006.286.04:29:58.52#ibcon#about to read 3, iclass 11, count 0 2006.286.04:29:58.55#ibcon#read 3, iclass 11, count 0 2006.286.04:29:58.55#ibcon#about to read 4, iclass 11, count 0 2006.286.04:29:58.55#ibcon#read 4, iclass 11, count 0 2006.286.04:29:58.55#ibcon#about to read 5, iclass 11, count 0 2006.286.04:29:58.55#ibcon#read 5, iclass 11, count 0 2006.286.04:29:58.55#ibcon#about to read 6, iclass 11, count 0 2006.286.04:29:58.55#ibcon#read 6, iclass 11, count 0 2006.286.04:29:58.55#ibcon#end of sib2, iclass 11, count 0 2006.286.04:29:58.55#ibcon#*after write, iclass 11, count 0 2006.286.04:29:58.55#ibcon#*before return 0, iclass 11, count 0 2006.286.04:29:58.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.04:29:58.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.04:29:58.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.04:29:58.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.04:29:58.56$vck44/valo=6,814.99 2006.286.04:29:58.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.04:29:58.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.04:29:58.56#ibcon#ireg 17 cls_cnt 0 2006.286.04:29:58.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:29:58.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:29:58.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:29:58.56#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:29:58.56#ibcon#first serial, iclass 13, count 0 2006.286.04:29:58.56#ibcon#enter sib2, iclass 13, count 0 2006.286.04:29:58.56#ibcon#flushed, iclass 13, count 0 2006.286.04:29:58.56#ibcon#about to write, iclass 13, count 0 2006.286.04:29:58.56#ibcon#wrote, iclass 13, count 0 2006.286.04:29:58.56#ibcon#about to read 3, iclass 13, count 0 2006.286.04:29:58.57#ibcon#read 3, iclass 13, count 0 2006.286.04:29:58.57#ibcon#about to read 4, iclass 13, count 0 2006.286.04:29:58.57#ibcon#read 4, iclass 13, count 0 2006.286.04:29:58.57#ibcon#about to read 5, iclass 13, count 0 2006.286.04:29:58.57#ibcon#read 5, iclass 13, count 0 2006.286.04:29:58.57#ibcon#about to read 6, iclass 13, count 0 2006.286.04:29:58.57#ibcon#read 6, iclass 13, count 0 2006.286.04:29:58.57#ibcon#end of sib2, iclass 13, count 0 2006.286.04:29:58.57#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:29:58.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:29:58.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:29:58.57#ibcon#*before write, iclass 13, count 0 2006.286.04:29:58.57#ibcon#enter sib2, iclass 13, count 0 2006.286.04:29:58.57#ibcon#flushed, iclass 13, count 0 2006.286.04:29:58.57#ibcon#about to write, iclass 13, count 0 2006.286.04:29:58.57#ibcon#wrote, iclass 13, count 0 2006.286.04:29:58.57#ibcon#about to read 3, iclass 13, count 0 2006.286.04:29:58.61#ibcon#read 3, iclass 13, count 0 2006.286.04:29:58.61#ibcon#about to read 4, iclass 13, count 0 2006.286.04:29:58.61#ibcon#read 4, iclass 13, count 0 2006.286.04:29:58.61#ibcon#about to read 5, iclass 13, count 0 2006.286.04:29:58.61#ibcon#read 5, iclass 13, count 0 2006.286.04:29:58.61#ibcon#about to read 6, iclass 13, count 0 2006.286.04:29:58.61#ibcon#read 6, iclass 13, count 0 2006.286.04:29:58.61#ibcon#end of sib2, iclass 13, count 0 2006.286.04:29:58.61#ibcon#*after write, iclass 13, count 0 2006.286.04:29:58.61#ibcon#*before return 0, iclass 13, count 0 2006.286.04:29:58.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:29:58.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:29:58.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:29:58.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:29:58.62$vck44/va=6,4 2006.286.04:29:58.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.04:29:58.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.04:29:58.62#ibcon#ireg 11 cls_cnt 2 2006.286.04:29:58.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:29:58.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:29:58.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:29:58.66#ibcon#enter wrdev, iclass 15, count 2 2006.286.04:29:58.66#ibcon#first serial, iclass 15, count 2 2006.286.04:29:58.66#ibcon#enter sib2, iclass 15, count 2 2006.286.04:29:58.66#ibcon#flushed, iclass 15, count 2 2006.286.04:29:58.66#ibcon#about to write, iclass 15, count 2 2006.286.04:29:58.66#ibcon#wrote, iclass 15, count 2 2006.286.04:29:58.66#ibcon#about to read 3, iclass 15, count 2 2006.286.04:29:58.68#ibcon#read 3, iclass 15, count 2 2006.286.04:29:58.68#ibcon#about to read 4, iclass 15, count 2 2006.286.04:29:58.68#ibcon#read 4, iclass 15, count 2 2006.286.04:29:58.68#ibcon#about to read 5, iclass 15, count 2 2006.286.04:29:58.68#ibcon#read 5, iclass 15, count 2 2006.286.04:29:58.68#ibcon#about to read 6, iclass 15, count 2 2006.286.04:29:58.68#ibcon#read 6, iclass 15, count 2 2006.286.04:29:58.68#ibcon#end of sib2, iclass 15, count 2 2006.286.04:29:58.68#ibcon#*mode == 0, iclass 15, count 2 2006.286.04:29:58.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.04:29:58.68#ibcon#[25=AT06-04\r\n] 2006.286.04:29:58.68#ibcon#*before write, iclass 15, count 2 2006.286.04:29:58.68#ibcon#enter sib2, iclass 15, count 2 2006.286.04:29:58.68#ibcon#flushed, iclass 15, count 2 2006.286.04:29:58.68#ibcon#about to write, iclass 15, count 2 2006.286.04:29:58.68#ibcon#wrote, iclass 15, count 2 2006.286.04:29:58.68#ibcon#about to read 3, iclass 15, count 2 2006.286.04:29:58.71#ibcon#read 3, iclass 15, count 2 2006.286.04:29:58.84#ibcon#about to read 4, iclass 15, count 2 2006.286.04:29:58.84#ibcon#read 4, iclass 15, count 2 2006.286.04:29:58.84#ibcon#about to read 5, iclass 15, count 2 2006.286.04:29:58.84#ibcon#read 5, iclass 15, count 2 2006.286.04:29:58.84#ibcon#about to read 6, iclass 15, count 2 2006.286.04:29:58.84#ibcon#read 6, iclass 15, count 2 2006.286.04:29:58.84#ibcon#end of sib2, iclass 15, count 2 2006.286.04:29:58.84#ibcon#*after write, iclass 15, count 2 2006.286.04:29:58.84#ibcon#*before return 0, iclass 15, count 2 2006.286.04:29:58.84#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:29:58.84#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:29:58.84#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.04:29:58.84#ibcon#ireg 7 cls_cnt 0 2006.286.04:29:58.84#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:29:58.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:29:58.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:29:58.95#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:29:58.95#ibcon#first serial, iclass 15, count 0 2006.286.04:29:58.95#ibcon#enter sib2, iclass 15, count 0 2006.286.04:29:58.95#ibcon#flushed, iclass 15, count 0 2006.286.04:29:58.95#ibcon#about to write, iclass 15, count 0 2006.286.04:29:58.95#ibcon#wrote, iclass 15, count 0 2006.286.04:29:58.95#ibcon#about to read 3, iclass 15, count 0 2006.286.04:29:58.97#ibcon#read 3, iclass 15, count 0 2006.286.04:29:58.97#ibcon#about to read 4, iclass 15, count 0 2006.286.04:29:58.97#ibcon#read 4, iclass 15, count 0 2006.286.04:29:58.97#ibcon#about to read 5, iclass 15, count 0 2006.286.04:29:58.97#ibcon#read 5, iclass 15, count 0 2006.286.04:29:58.97#ibcon#about to read 6, iclass 15, count 0 2006.286.04:29:58.97#ibcon#read 6, iclass 15, count 0 2006.286.04:29:58.97#ibcon#end of sib2, iclass 15, count 0 2006.286.04:29:58.97#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:29:58.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:29:58.97#ibcon#[25=USB\r\n] 2006.286.04:29:58.97#ibcon#*before write, iclass 15, count 0 2006.286.04:29:58.97#ibcon#enter sib2, iclass 15, count 0 2006.286.04:29:58.97#ibcon#flushed, iclass 15, count 0 2006.286.04:29:58.97#ibcon#about to write, iclass 15, count 0 2006.286.04:29:58.97#ibcon#wrote, iclass 15, count 0 2006.286.04:29:58.97#ibcon#about to read 3, iclass 15, count 0 2006.286.04:29:59.00#ibcon#read 3, iclass 15, count 0 2006.286.04:29:59.00#ibcon#about to read 4, iclass 15, count 0 2006.286.04:29:59.00#ibcon#read 4, iclass 15, count 0 2006.286.04:29:59.00#ibcon#about to read 5, iclass 15, count 0 2006.286.04:29:59.00#ibcon#read 5, iclass 15, count 0 2006.286.04:29:59.00#ibcon#about to read 6, iclass 15, count 0 2006.286.04:29:59.00#ibcon#read 6, iclass 15, count 0 2006.286.04:29:59.00#ibcon#end of sib2, iclass 15, count 0 2006.286.04:29:59.00#ibcon#*after write, iclass 15, count 0 2006.286.04:29:59.00#ibcon#*before return 0, iclass 15, count 0 2006.286.04:29:59.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:29:59.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:29:59.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:29:59.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:29:59.00$vck44/valo=7,864.99 2006.286.04:29:59.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.04:29:59.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.04:29:59.00#ibcon#ireg 17 cls_cnt 0 2006.286.04:29:59.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:29:59.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:29:59.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:29:59.00#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:29:59.00#ibcon#first serial, iclass 17, count 0 2006.286.04:29:59.00#ibcon#enter sib2, iclass 17, count 0 2006.286.04:29:59.00#ibcon#flushed, iclass 17, count 0 2006.286.04:29:59.01#ibcon#about to write, iclass 17, count 0 2006.286.04:29:59.01#ibcon#wrote, iclass 17, count 0 2006.286.04:29:59.01#ibcon#about to read 3, iclass 17, count 0 2006.286.04:29:59.02#ibcon#read 3, iclass 17, count 0 2006.286.04:29:59.02#ibcon#about to read 4, iclass 17, count 0 2006.286.04:29:59.02#ibcon#read 4, iclass 17, count 0 2006.286.04:29:59.02#ibcon#about to read 5, iclass 17, count 0 2006.286.04:29:59.02#ibcon#read 5, iclass 17, count 0 2006.286.04:29:59.02#ibcon#about to read 6, iclass 17, count 0 2006.286.04:29:59.02#ibcon#read 6, iclass 17, count 0 2006.286.04:29:59.02#ibcon#end of sib2, iclass 17, count 0 2006.286.04:29:59.02#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:29:59.02#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:29:59.02#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:29:59.02#ibcon#*before write, iclass 17, count 0 2006.286.04:29:59.02#ibcon#enter sib2, iclass 17, count 0 2006.286.04:29:59.02#ibcon#flushed, iclass 17, count 0 2006.286.04:29:59.02#ibcon#about to write, iclass 17, count 0 2006.286.04:29:59.02#ibcon#wrote, iclass 17, count 0 2006.286.04:29:59.02#ibcon#about to read 3, iclass 17, count 0 2006.286.04:29:59.06#ibcon#read 3, iclass 17, count 0 2006.286.04:29:59.06#ibcon#about to read 4, iclass 17, count 0 2006.286.04:29:59.06#ibcon#read 4, iclass 17, count 0 2006.286.04:29:59.06#ibcon#about to read 5, iclass 17, count 0 2006.286.04:29:59.06#ibcon#read 5, iclass 17, count 0 2006.286.04:29:59.06#ibcon#about to read 6, iclass 17, count 0 2006.286.04:29:59.06#ibcon#read 6, iclass 17, count 0 2006.286.04:29:59.06#ibcon#end of sib2, iclass 17, count 0 2006.286.04:29:59.06#ibcon#*after write, iclass 17, count 0 2006.286.04:29:59.06#ibcon#*before return 0, iclass 17, count 0 2006.286.04:29:59.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:29:59.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:29:59.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:29:59.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:29:59.06$vck44/va=7,4 2006.286.04:29:59.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.04:29:59.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.04:29:59.06#ibcon#ireg 11 cls_cnt 2 2006.286.04:29:59.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:29:59.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:29:59.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:29:59.12#ibcon#enter wrdev, iclass 19, count 2 2006.286.04:29:59.12#ibcon#first serial, iclass 19, count 2 2006.286.04:29:59.12#ibcon#enter sib2, iclass 19, count 2 2006.286.04:29:59.12#ibcon#flushed, iclass 19, count 2 2006.286.04:29:59.12#ibcon#about to write, iclass 19, count 2 2006.286.04:29:59.12#ibcon#wrote, iclass 19, count 2 2006.286.04:29:59.12#ibcon#about to read 3, iclass 19, count 2 2006.286.04:29:59.14#ibcon#read 3, iclass 19, count 2 2006.286.04:29:59.14#ibcon#about to read 4, iclass 19, count 2 2006.286.04:29:59.14#ibcon#read 4, iclass 19, count 2 2006.286.04:29:59.14#ibcon#about to read 5, iclass 19, count 2 2006.286.04:29:59.14#ibcon#read 5, iclass 19, count 2 2006.286.04:29:59.14#ibcon#about to read 6, iclass 19, count 2 2006.286.04:29:59.14#ibcon#read 6, iclass 19, count 2 2006.286.04:29:59.14#ibcon#end of sib2, iclass 19, count 2 2006.286.04:29:59.14#ibcon#*mode == 0, iclass 19, count 2 2006.286.04:29:59.14#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.04:29:59.14#ibcon#[25=AT07-04\r\n] 2006.286.04:29:59.14#ibcon#*before write, iclass 19, count 2 2006.286.04:29:59.14#ibcon#enter sib2, iclass 19, count 2 2006.286.04:29:59.14#ibcon#flushed, iclass 19, count 2 2006.286.04:29:59.14#ibcon#about to write, iclass 19, count 2 2006.286.04:29:59.14#ibcon#wrote, iclass 19, count 2 2006.286.04:29:59.14#ibcon#about to read 3, iclass 19, count 2 2006.286.04:29:59.17#ibcon#read 3, iclass 19, count 2 2006.286.04:29:59.17#ibcon#about to read 4, iclass 19, count 2 2006.286.04:29:59.17#ibcon#read 4, iclass 19, count 2 2006.286.04:29:59.17#ibcon#about to read 5, iclass 19, count 2 2006.286.04:29:59.17#ibcon#read 5, iclass 19, count 2 2006.286.04:29:59.17#ibcon#about to read 6, iclass 19, count 2 2006.286.04:29:59.17#ibcon#read 6, iclass 19, count 2 2006.286.04:29:59.17#ibcon#end of sib2, iclass 19, count 2 2006.286.04:29:59.17#ibcon#*after write, iclass 19, count 2 2006.286.04:29:59.17#ibcon#*before return 0, iclass 19, count 2 2006.286.04:29:59.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:29:59.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:29:59.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.04:29:59.17#ibcon#ireg 7 cls_cnt 0 2006.286.04:29:59.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:29:59.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:29:59.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:29:59.29#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:29:59.29#ibcon#first serial, iclass 19, count 0 2006.286.04:29:59.29#ibcon#enter sib2, iclass 19, count 0 2006.286.04:29:59.29#ibcon#flushed, iclass 19, count 0 2006.286.04:29:59.29#ibcon#about to write, iclass 19, count 0 2006.286.04:29:59.29#ibcon#wrote, iclass 19, count 0 2006.286.04:29:59.29#ibcon#about to read 3, iclass 19, count 0 2006.286.04:29:59.31#ibcon#read 3, iclass 19, count 0 2006.286.04:29:59.31#ibcon#about to read 4, iclass 19, count 0 2006.286.04:29:59.31#ibcon#read 4, iclass 19, count 0 2006.286.04:29:59.31#ibcon#about to read 5, iclass 19, count 0 2006.286.04:29:59.31#ibcon#read 5, iclass 19, count 0 2006.286.04:29:59.31#ibcon#about to read 6, iclass 19, count 0 2006.286.04:29:59.31#ibcon#read 6, iclass 19, count 0 2006.286.04:29:59.31#ibcon#end of sib2, iclass 19, count 0 2006.286.04:29:59.31#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:29:59.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:29:59.31#ibcon#[25=USB\r\n] 2006.286.04:29:59.31#ibcon#*before write, iclass 19, count 0 2006.286.04:29:59.31#ibcon#enter sib2, iclass 19, count 0 2006.286.04:29:59.31#ibcon#flushed, iclass 19, count 0 2006.286.04:29:59.31#ibcon#about to write, iclass 19, count 0 2006.286.04:29:59.31#ibcon#wrote, iclass 19, count 0 2006.286.04:29:59.31#ibcon#about to read 3, iclass 19, count 0 2006.286.04:29:59.34#ibcon#read 3, iclass 19, count 0 2006.286.04:29:59.34#ibcon#about to read 4, iclass 19, count 0 2006.286.04:29:59.34#ibcon#read 4, iclass 19, count 0 2006.286.04:29:59.34#ibcon#about to read 5, iclass 19, count 0 2006.286.04:29:59.34#ibcon#read 5, iclass 19, count 0 2006.286.04:29:59.34#ibcon#about to read 6, iclass 19, count 0 2006.286.04:29:59.34#ibcon#read 6, iclass 19, count 0 2006.286.04:29:59.34#ibcon#end of sib2, iclass 19, count 0 2006.286.04:29:59.34#ibcon#*after write, iclass 19, count 0 2006.286.04:29:59.34#ibcon#*before return 0, iclass 19, count 0 2006.286.04:29:59.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:29:59.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:29:59.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:29:59.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:29:59.34$vck44/valo=8,884.99 2006.286.04:29:59.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.04:29:59.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.04:29:59.34#ibcon#ireg 17 cls_cnt 0 2006.286.04:29:59.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:29:59.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:29:59.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:29:59.34#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:29:59.34#ibcon#first serial, iclass 21, count 0 2006.286.04:29:59.34#ibcon#enter sib2, iclass 21, count 0 2006.286.04:29:59.34#ibcon#flushed, iclass 21, count 0 2006.286.04:29:59.34#ibcon#about to write, iclass 21, count 0 2006.286.04:29:59.34#ibcon#wrote, iclass 21, count 0 2006.286.04:29:59.34#ibcon#about to read 3, iclass 21, count 0 2006.286.04:29:59.36#ibcon#read 3, iclass 21, count 0 2006.286.04:29:59.36#ibcon#about to read 4, iclass 21, count 0 2006.286.04:29:59.36#ibcon#read 4, iclass 21, count 0 2006.286.04:29:59.36#ibcon#about to read 5, iclass 21, count 0 2006.286.04:29:59.36#ibcon#read 5, iclass 21, count 0 2006.286.04:29:59.36#ibcon#about to read 6, iclass 21, count 0 2006.286.04:29:59.36#ibcon#read 6, iclass 21, count 0 2006.286.04:29:59.36#ibcon#end of sib2, iclass 21, count 0 2006.286.04:29:59.36#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:29:59.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:29:59.36#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:29:59.36#ibcon#*before write, iclass 21, count 0 2006.286.04:29:59.36#ibcon#enter sib2, iclass 21, count 0 2006.286.04:29:59.36#ibcon#flushed, iclass 21, count 0 2006.286.04:29:59.36#ibcon#about to write, iclass 21, count 0 2006.286.04:29:59.36#ibcon#wrote, iclass 21, count 0 2006.286.04:29:59.36#ibcon#about to read 3, iclass 21, count 0 2006.286.04:29:59.40#ibcon#read 3, iclass 21, count 0 2006.286.04:29:59.40#ibcon#about to read 4, iclass 21, count 0 2006.286.04:29:59.40#ibcon#read 4, iclass 21, count 0 2006.286.04:29:59.40#ibcon#about to read 5, iclass 21, count 0 2006.286.04:29:59.40#ibcon#read 5, iclass 21, count 0 2006.286.04:29:59.40#ibcon#about to read 6, iclass 21, count 0 2006.286.04:29:59.40#ibcon#read 6, iclass 21, count 0 2006.286.04:29:59.40#ibcon#end of sib2, iclass 21, count 0 2006.286.04:29:59.40#ibcon#*after write, iclass 21, count 0 2006.286.04:29:59.40#ibcon#*before return 0, iclass 21, count 0 2006.286.04:29:59.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:29:59.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:29:59.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:29:59.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:29:59.40$vck44/va=8,3 2006.286.04:29:59.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.04:29:59.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.04:29:59.40#ibcon#ireg 11 cls_cnt 2 2006.286.04:29:59.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:29:59.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:29:59.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:29:59.46#ibcon#enter wrdev, iclass 23, count 2 2006.286.04:29:59.46#ibcon#first serial, iclass 23, count 2 2006.286.04:29:59.46#ibcon#enter sib2, iclass 23, count 2 2006.286.04:29:59.46#ibcon#flushed, iclass 23, count 2 2006.286.04:29:59.46#ibcon#about to write, iclass 23, count 2 2006.286.04:29:59.46#ibcon#wrote, iclass 23, count 2 2006.286.04:29:59.46#ibcon#about to read 3, iclass 23, count 2 2006.286.04:29:59.48#ibcon#read 3, iclass 23, count 2 2006.286.04:29:59.48#ibcon#about to read 4, iclass 23, count 2 2006.286.04:29:59.48#ibcon#read 4, iclass 23, count 2 2006.286.04:29:59.48#ibcon#about to read 5, iclass 23, count 2 2006.286.04:29:59.48#ibcon#read 5, iclass 23, count 2 2006.286.04:29:59.48#ibcon#about to read 6, iclass 23, count 2 2006.286.04:29:59.48#ibcon#read 6, iclass 23, count 2 2006.286.04:29:59.48#ibcon#end of sib2, iclass 23, count 2 2006.286.04:29:59.48#ibcon#*mode == 0, iclass 23, count 2 2006.286.04:29:59.48#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.04:29:59.48#ibcon#[25=AT08-03\r\n] 2006.286.04:29:59.48#ibcon#*before write, iclass 23, count 2 2006.286.04:29:59.48#ibcon#enter sib2, iclass 23, count 2 2006.286.04:29:59.48#ibcon#flushed, iclass 23, count 2 2006.286.04:29:59.48#ibcon#about to write, iclass 23, count 2 2006.286.04:29:59.48#ibcon#wrote, iclass 23, count 2 2006.286.04:29:59.48#ibcon#about to read 3, iclass 23, count 2 2006.286.04:29:59.51#ibcon#read 3, iclass 23, count 2 2006.286.04:29:59.51#ibcon#about to read 4, iclass 23, count 2 2006.286.04:29:59.51#ibcon#read 4, iclass 23, count 2 2006.286.04:29:59.51#ibcon#about to read 5, iclass 23, count 2 2006.286.04:29:59.51#ibcon#read 5, iclass 23, count 2 2006.286.04:29:59.51#ibcon#about to read 6, iclass 23, count 2 2006.286.04:29:59.51#ibcon#read 6, iclass 23, count 2 2006.286.04:29:59.51#ibcon#end of sib2, iclass 23, count 2 2006.286.04:29:59.51#ibcon#*after write, iclass 23, count 2 2006.286.04:29:59.51#ibcon#*before return 0, iclass 23, count 2 2006.286.04:29:59.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:29:59.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:29:59.51#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.04:29:59.51#ibcon#ireg 7 cls_cnt 0 2006.286.04:29:59.51#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:29:59.63#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:29:59.63#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:29:59.63#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:29:59.63#ibcon#first serial, iclass 23, count 0 2006.286.04:29:59.63#ibcon#enter sib2, iclass 23, count 0 2006.286.04:29:59.63#ibcon#flushed, iclass 23, count 0 2006.286.04:29:59.63#ibcon#about to write, iclass 23, count 0 2006.286.04:29:59.63#ibcon#wrote, iclass 23, count 0 2006.286.04:29:59.63#ibcon#about to read 3, iclass 23, count 0 2006.286.04:29:59.65#ibcon#read 3, iclass 23, count 0 2006.286.04:29:59.65#ibcon#about to read 4, iclass 23, count 0 2006.286.04:29:59.65#ibcon#read 4, iclass 23, count 0 2006.286.04:29:59.65#ibcon#about to read 5, iclass 23, count 0 2006.286.04:29:59.65#ibcon#read 5, iclass 23, count 0 2006.286.04:29:59.65#ibcon#about to read 6, iclass 23, count 0 2006.286.04:29:59.65#ibcon#read 6, iclass 23, count 0 2006.286.04:29:59.65#ibcon#end of sib2, iclass 23, count 0 2006.286.04:29:59.65#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:29:59.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:29:59.65#ibcon#[25=USB\r\n] 2006.286.04:29:59.65#ibcon#*before write, iclass 23, count 0 2006.286.04:29:59.65#ibcon#enter sib2, iclass 23, count 0 2006.286.04:29:59.65#ibcon#flushed, iclass 23, count 0 2006.286.04:29:59.65#ibcon#about to write, iclass 23, count 0 2006.286.04:29:59.65#ibcon#wrote, iclass 23, count 0 2006.286.04:29:59.65#ibcon#about to read 3, iclass 23, count 0 2006.286.04:29:59.68#ibcon#read 3, iclass 23, count 0 2006.286.04:29:59.68#ibcon#about to read 4, iclass 23, count 0 2006.286.04:29:59.68#ibcon#read 4, iclass 23, count 0 2006.286.04:29:59.68#ibcon#about to read 5, iclass 23, count 0 2006.286.04:29:59.68#ibcon#read 5, iclass 23, count 0 2006.286.04:29:59.68#ibcon#about to read 6, iclass 23, count 0 2006.286.04:29:59.68#ibcon#read 6, iclass 23, count 0 2006.286.04:29:59.68#ibcon#end of sib2, iclass 23, count 0 2006.286.04:29:59.68#ibcon#*after write, iclass 23, count 0 2006.286.04:29:59.68#ibcon#*before return 0, iclass 23, count 0 2006.286.04:29:59.68#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:29:59.68#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:29:59.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:29:59.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:29:59.68$vck44/vblo=1,629.99 2006.286.04:29:59.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.04:29:59.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.04:29:59.68#ibcon#ireg 17 cls_cnt 0 2006.286.04:29:59.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:29:59.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:29:59.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:29:59.68#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:29:59.68#ibcon#first serial, iclass 25, count 0 2006.286.04:29:59.68#ibcon#enter sib2, iclass 25, count 0 2006.286.04:29:59.68#ibcon#flushed, iclass 25, count 0 2006.286.04:29:59.68#ibcon#about to write, iclass 25, count 0 2006.286.04:29:59.68#ibcon#wrote, iclass 25, count 0 2006.286.04:29:59.69#ibcon#about to read 3, iclass 25, count 0 2006.286.04:29:59.70#ibcon#read 3, iclass 25, count 0 2006.286.04:29:59.78#ibcon#about to read 4, iclass 25, count 0 2006.286.04:29:59.78#ibcon#read 4, iclass 25, count 0 2006.286.04:29:59.78#ibcon#about to read 5, iclass 25, count 0 2006.286.04:29:59.78#ibcon#read 5, iclass 25, count 0 2006.286.04:29:59.78#ibcon#about to read 6, iclass 25, count 0 2006.286.04:29:59.78#ibcon#read 6, iclass 25, count 0 2006.286.04:29:59.78#ibcon#end of sib2, iclass 25, count 0 2006.286.04:29:59.78#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:29:59.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:29:59.78#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:29:59.78#ibcon#*before write, iclass 25, count 0 2006.286.04:29:59.78#ibcon#enter sib2, iclass 25, count 0 2006.286.04:29:59.78#ibcon#flushed, iclass 25, count 0 2006.286.04:29:59.78#ibcon#about to write, iclass 25, count 0 2006.286.04:29:59.78#ibcon#wrote, iclass 25, count 0 2006.286.04:29:59.78#ibcon#about to read 3, iclass 25, count 0 2006.286.04:29:59.82#ibcon#read 3, iclass 25, count 0 2006.286.04:29:59.82#ibcon#about to read 4, iclass 25, count 0 2006.286.04:29:59.82#ibcon#read 4, iclass 25, count 0 2006.286.04:29:59.82#ibcon#about to read 5, iclass 25, count 0 2006.286.04:29:59.82#ibcon#read 5, iclass 25, count 0 2006.286.04:29:59.82#ibcon#about to read 6, iclass 25, count 0 2006.286.04:29:59.82#ibcon#read 6, iclass 25, count 0 2006.286.04:29:59.82#ibcon#end of sib2, iclass 25, count 0 2006.286.04:29:59.82#ibcon#*after write, iclass 25, count 0 2006.286.04:29:59.82#ibcon#*before return 0, iclass 25, count 0 2006.286.04:29:59.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:29:59.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:29:59.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:29:59.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:29:59.82$vck44/vb=1,4 2006.286.04:29:59.82#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.04:29:59.82#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.04:29:59.82#ibcon#ireg 11 cls_cnt 2 2006.286.04:29:59.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:29:59.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:29:59.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:29:59.82#ibcon#enter wrdev, iclass 27, count 2 2006.286.04:29:59.82#ibcon#first serial, iclass 27, count 2 2006.286.04:29:59.82#ibcon#enter sib2, iclass 27, count 2 2006.286.04:29:59.82#ibcon#flushed, iclass 27, count 2 2006.286.04:29:59.82#ibcon#about to write, iclass 27, count 2 2006.286.04:29:59.83#ibcon#wrote, iclass 27, count 2 2006.286.04:29:59.83#ibcon#about to read 3, iclass 27, count 2 2006.286.04:29:59.84#ibcon#read 3, iclass 27, count 2 2006.286.04:29:59.84#ibcon#about to read 4, iclass 27, count 2 2006.286.04:29:59.84#ibcon#read 4, iclass 27, count 2 2006.286.04:29:59.84#ibcon#about to read 5, iclass 27, count 2 2006.286.04:29:59.84#ibcon#read 5, iclass 27, count 2 2006.286.04:29:59.84#ibcon#about to read 6, iclass 27, count 2 2006.286.04:29:59.84#ibcon#read 6, iclass 27, count 2 2006.286.04:29:59.84#ibcon#end of sib2, iclass 27, count 2 2006.286.04:29:59.84#ibcon#*mode == 0, iclass 27, count 2 2006.286.04:29:59.84#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.04:29:59.84#ibcon#[27=AT01-04\r\n] 2006.286.04:29:59.84#ibcon#*before write, iclass 27, count 2 2006.286.04:29:59.84#ibcon#enter sib2, iclass 27, count 2 2006.286.04:29:59.84#ibcon#flushed, iclass 27, count 2 2006.286.04:29:59.84#ibcon#about to write, iclass 27, count 2 2006.286.04:29:59.84#ibcon#wrote, iclass 27, count 2 2006.286.04:29:59.84#ibcon#about to read 3, iclass 27, count 2 2006.286.04:29:59.87#ibcon#read 3, iclass 27, count 2 2006.286.04:29:59.87#ibcon#about to read 4, iclass 27, count 2 2006.286.04:29:59.87#ibcon#read 4, iclass 27, count 2 2006.286.04:29:59.87#ibcon#about to read 5, iclass 27, count 2 2006.286.04:29:59.87#ibcon#read 5, iclass 27, count 2 2006.286.04:29:59.87#ibcon#about to read 6, iclass 27, count 2 2006.286.04:29:59.87#ibcon#read 6, iclass 27, count 2 2006.286.04:29:59.87#ibcon#end of sib2, iclass 27, count 2 2006.286.04:29:59.87#ibcon#*after write, iclass 27, count 2 2006.286.04:29:59.87#ibcon#*before return 0, iclass 27, count 2 2006.286.04:29:59.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:29:59.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:29:59.87#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.04:29:59.87#ibcon#ireg 7 cls_cnt 0 2006.286.04:29:59.87#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:29:59.99#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:29:59.99#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:29:59.99#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:29:59.99#ibcon#first serial, iclass 27, count 0 2006.286.04:29:59.99#ibcon#enter sib2, iclass 27, count 0 2006.286.04:29:59.99#ibcon#flushed, iclass 27, count 0 2006.286.04:29:59.99#ibcon#about to write, iclass 27, count 0 2006.286.04:29:59.99#ibcon#wrote, iclass 27, count 0 2006.286.04:29:59.99#ibcon#about to read 3, iclass 27, count 0 2006.286.04:30:00.01#ibcon#read 3, iclass 27, count 0 2006.286.04:30:00.01#ibcon#about to read 4, iclass 27, count 0 2006.286.04:30:00.01#ibcon#read 4, iclass 27, count 0 2006.286.04:30:00.01#ibcon#about to read 5, iclass 27, count 0 2006.286.04:30:00.01#ibcon#read 5, iclass 27, count 0 2006.286.04:30:00.01#ibcon#about to read 6, iclass 27, count 0 2006.286.04:30:00.01#ibcon#read 6, iclass 27, count 0 2006.286.04:30:00.01#ibcon#end of sib2, iclass 27, count 0 2006.286.04:30:00.01#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:30:00.01#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:30:00.01#ibcon#[27=USB\r\n] 2006.286.04:30:00.01#ibcon#*before write, iclass 27, count 0 2006.286.04:30:00.01#ibcon#enter sib2, iclass 27, count 0 2006.286.04:30:00.01#ibcon#flushed, iclass 27, count 0 2006.286.04:30:00.01#ibcon#about to write, iclass 27, count 0 2006.286.04:30:00.01#ibcon#wrote, iclass 27, count 0 2006.286.04:30:00.01#ibcon#about to read 3, iclass 27, count 0 2006.286.04:30:00.04#ibcon#read 3, iclass 27, count 0 2006.286.04:30:00.04#ibcon#about to read 4, iclass 27, count 0 2006.286.04:30:00.04#ibcon#read 4, iclass 27, count 0 2006.286.04:30:00.04#ibcon#about to read 5, iclass 27, count 0 2006.286.04:30:00.04#ibcon#read 5, iclass 27, count 0 2006.286.04:30:00.04#ibcon#about to read 6, iclass 27, count 0 2006.286.04:30:00.04#ibcon#read 6, iclass 27, count 0 2006.286.04:30:00.04#ibcon#end of sib2, iclass 27, count 0 2006.286.04:30:00.04#ibcon#*after write, iclass 27, count 0 2006.286.04:30:00.04#ibcon#*before return 0, iclass 27, count 0 2006.286.04:30:00.04#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:30:00.04#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:30:00.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:30:00.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:30:00.04$vck44/vblo=2,634.99 2006.286.04:30:00.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.04:30:00.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.04:30:00.04#ibcon#ireg 17 cls_cnt 0 2006.286.04:30:00.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:30:00.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:30:00.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:30:00.04#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:30:00.04#ibcon#first serial, iclass 29, count 0 2006.286.04:30:00.04#ibcon#enter sib2, iclass 29, count 0 2006.286.04:30:00.04#ibcon#flushed, iclass 29, count 0 2006.286.04:30:00.04#ibcon#about to write, iclass 29, count 0 2006.286.04:30:00.04#ibcon#wrote, iclass 29, count 0 2006.286.04:30:00.04#ibcon#about to read 3, iclass 29, count 0 2006.286.04:30:00.06#ibcon#read 3, iclass 29, count 0 2006.286.04:30:00.06#ibcon#about to read 4, iclass 29, count 0 2006.286.04:30:00.06#ibcon#read 4, iclass 29, count 0 2006.286.04:30:00.06#ibcon#about to read 5, iclass 29, count 0 2006.286.04:30:00.06#ibcon#read 5, iclass 29, count 0 2006.286.04:30:00.06#ibcon#about to read 6, iclass 29, count 0 2006.286.04:30:00.06#ibcon#read 6, iclass 29, count 0 2006.286.04:30:00.06#ibcon#end of sib2, iclass 29, count 0 2006.286.04:30:00.06#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:30:00.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:30:00.06#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:30:00.06#ibcon#*before write, iclass 29, count 0 2006.286.04:30:00.06#ibcon#enter sib2, iclass 29, count 0 2006.286.04:30:00.06#ibcon#flushed, iclass 29, count 0 2006.286.04:30:00.06#ibcon#about to write, iclass 29, count 0 2006.286.04:30:00.06#ibcon#wrote, iclass 29, count 0 2006.286.04:30:00.06#ibcon#about to read 3, iclass 29, count 0 2006.286.04:30:00.10#ibcon#read 3, iclass 29, count 0 2006.286.04:30:00.10#ibcon#about to read 4, iclass 29, count 0 2006.286.04:30:00.10#ibcon#read 4, iclass 29, count 0 2006.286.04:30:00.10#ibcon#about to read 5, iclass 29, count 0 2006.286.04:30:00.10#ibcon#read 5, iclass 29, count 0 2006.286.04:30:00.10#ibcon#about to read 6, iclass 29, count 0 2006.286.04:30:00.10#ibcon#read 6, iclass 29, count 0 2006.286.04:30:00.10#ibcon#end of sib2, iclass 29, count 0 2006.286.04:30:00.10#ibcon#*after write, iclass 29, count 0 2006.286.04:30:00.10#ibcon#*before return 0, iclass 29, count 0 2006.286.04:30:00.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:30:00.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:30:00.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:30:00.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:30:00.10$vck44/vb=2,5 2006.286.04:30:00.10#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.04:30:00.10#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.04:30:00.10#ibcon#ireg 11 cls_cnt 2 2006.286.04:30:00.10#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:30:00.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:30:00.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:30:00.16#ibcon#enter wrdev, iclass 31, count 2 2006.286.04:30:00.16#ibcon#first serial, iclass 31, count 2 2006.286.04:30:00.16#ibcon#enter sib2, iclass 31, count 2 2006.286.04:30:00.16#ibcon#flushed, iclass 31, count 2 2006.286.04:30:00.16#ibcon#about to write, iclass 31, count 2 2006.286.04:30:00.16#ibcon#wrote, iclass 31, count 2 2006.286.04:30:00.16#ibcon#about to read 3, iclass 31, count 2 2006.286.04:30:00.18#ibcon#read 3, iclass 31, count 2 2006.286.04:30:00.18#ibcon#about to read 4, iclass 31, count 2 2006.286.04:30:00.18#ibcon#read 4, iclass 31, count 2 2006.286.04:30:00.18#ibcon#about to read 5, iclass 31, count 2 2006.286.04:30:00.18#ibcon#read 5, iclass 31, count 2 2006.286.04:30:00.18#ibcon#about to read 6, iclass 31, count 2 2006.286.04:30:00.18#ibcon#read 6, iclass 31, count 2 2006.286.04:30:00.18#ibcon#end of sib2, iclass 31, count 2 2006.286.04:30:00.18#ibcon#*mode == 0, iclass 31, count 2 2006.286.04:30:00.18#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.04:30:00.18#ibcon#[27=AT02-05\r\n] 2006.286.04:30:00.18#ibcon#*before write, iclass 31, count 2 2006.286.04:30:00.18#ibcon#enter sib2, iclass 31, count 2 2006.286.04:30:00.18#ibcon#flushed, iclass 31, count 2 2006.286.04:30:00.18#ibcon#about to write, iclass 31, count 2 2006.286.04:30:00.18#ibcon#wrote, iclass 31, count 2 2006.286.04:30:00.18#ibcon#about to read 3, iclass 31, count 2 2006.286.04:30:00.21#ibcon#read 3, iclass 31, count 2 2006.286.04:30:00.21#ibcon#about to read 4, iclass 31, count 2 2006.286.04:30:00.21#ibcon#read 4, iclass 31, count 2 2006.286.04:30:00.21#ibcon#about to read 5, iclass 31, count 2 2006.286.04:30:00.21#ibcon#read 5, iclass 31, count 2 2006.286.04:30:00.21#ibcon#about to read 6, iclass 31, count 2 2006.286.04:30:00.21#ibcon#read 6, iclass 31, count 2 2006.286.04:30:00.21#ibcon#end of sib2, iclass 31, count 2 2006.286.04:30:00.21#ibcon#*after write, iclass 31, count 2 2006.286.04:30:00.21#ibcon#*before return 0, iclass 31, count 2 2006.286.04:30:00.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:30:00.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:30:00.21#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.04:30:00.21#ibcon#ireg 7 cls_cnt 0 2006.286.04:30:00.21#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:30:00.33#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:30:00.33#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:30:00.33#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:30:00.33#ibcon#first serial, iclass 31, count 0 2006.286.04:30:00.33#ibcon#enter sib2, iclass 31, count 0 2006.286.04:30:00.33#ibcon#flushed, iclass 31, count 0 2006.286.04:30:00.33#ibcon#about to write, iclass 31, count 0 2006.286.04:30:00.33#ibcon#wrote, iclass 31, count 0 2006.286.04:30:00.33#ibcon#about to read 3, iclass 31, count 0 2006.286.04:30:00.35#ibcon#read 3, iclass 31, count 0 2006.286.04:30:00.35#ibcon#about to read 4, iclass 31, count 0 2006.286.04:30:00.35#ibcon#read 4, iclass 31, count 0 2006.286.04:30:00.35#ibcon#about to read 5, iclass 31, count 0 2006.286.04:30:00.35#ibcon#read 5, iclass 31, count 0 2006.286.04:30:00.35#ibcon#about to read 6, iclass 31, count 0 2006.286.04:30:00.35#ibcon#read 6, iclass 31, count 0 2006.286.04:30:00.35#ibcon#end of sib2, iclass 31, count 0 2006.286.04:30:00.35#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:30:00.35#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:30:00.35#ibcon#[27=USB\r\n] 2006.286.04:30:00.35#ibcon#*before write, iclass 31, count 0 2006.286.04:30:00.35#ibcon#enter sib2, iclass 31, count 0 2006.286.04:30:00.35#ibcon#flushed, iclass 31, count 0 2006.286.04:30:00.35#ibcon#about to write, iclass 31, count 0 2006.286.04:30:00.35#ibcon#wrote, iclass 31, count 0 2006.286.04:30:00.35#ibcon#about to read 3, iclass 31, count 0 2006.286.04:30:00.38#ibcon#read 3, iclass 31, count 0 2006.286.04:30:00.38#ibcon#about to read 4, iclass 31, count 0 2006.286.04:30:00.38#ibcon#read 4, iclass 31, count 0 2006.286.04:30:00.38#ibcon#about to read 5, iclass 31, count 0 2006.286.04:30:00.38#ibcon#read 5, iclass 31, count 0 2006.286.04:30:00.38#ibcon#about to read 6, iclass 31, count 0 2006.286.04:30:00.38#ibcon#read 6, iclass 31, count 0 2006.286.04:30:00.38#ibcon#end of sib2, iclass 31, count 0 2006.286.04:30:00.38#ibcon#*after write, iclass 31, count 0 2006.286.04:30:00.38#ibcon#*before return 0, iclass 31, count 0 2006.286.04:30:00.38#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:30:00.38#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:30:00.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:30:00.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:30:00.38$vck44/vblo=3,649.99 2006.286.04:30:00.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.04:30:00.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.04:30:00.38#ibcon#ireg 17 cls_cnt 0 2006.286.04:30:00.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:30:00.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:30:00.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:30:00.38#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:30:00.38#ibcon#first serial, iclass 33, count 0 2006.286.04:30:00.38#ibcon#enter sib2, iclass 33, count 0 2006.286.04:30:00.38#ibcon#flushed, iclass 33, count 0 2006.286.04:30:00.38#ibcon#about to write, iclass 33, count 0 2006.286.04:30:00.38#ibcon#wrote, iclass 33, count 0 2006.286.04:30:00.38#ibcon#about to read 3, iclass 33, count 0 2006.286.04:30:00.40#ibcon#read 3, iclass 33, count 0 2006.286.04:30:00.40#ibcon#about to read 4, iclass 33, count 0 2006.286.04:30:00.40#ibcon#read 4, iclass 33, count 0 2006.286.04:30:00.40#ibcon#about to read 5, iclass 33, count 0 2006.286.04:30:00.40#ibcon#read 5, iclass 33, count 0 2006.286.04:30:00.40#ibcon#about to read 6, iclass 33, count 0 2006.286.04:30:00.40#ibcon#read 6, iclass 33, count 0 2006.286.04:30:00.40#ibcon#end of sib2, iclass 33, count 0 2006.286.04:30:00.40#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:30:00.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:30:00.40#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:30:00.40#ibcon#*before write, iclass 33, count 0 2006.286.04:30:00.40#ibcon#enter sib2, iclass 33, count 0 2006.286.04:30:00.40#ibcon#flushed, iclass 33, count 0 2006.286.04:30:00.40#ibcon#about to write, iclass 33, count 0 2006.286.04:30:00.40#ibcon#wrote, iclass 33, count 0 2006.286.04:30:00.40#ibcon#about to read 3, iclass 33, count 0 2006.286.04:30:00.44#ibcon#read 3, iclass 33, count 0 2006.286.04:30:00.44#ibcon#about to read 4, iclass 33, count 0 2006.286.04:30:00.44#ibcon#read 4, iclass 33, count 0 2006.286.04:30:00.44#ibcon#about to read 5, iclass 33, count 0 2006.286.04:30:00.44#ibcon#read 5, iclass 33, count 0 2006.286.04:30:00.44#ibcon#about to read 6, iclass 33, count 0 2006.286.04:30:00.44#ibcon#read 6, iclass 33, count 0 2006.286.04:30:00.44#ibcon#end of sib2, iclass 33, count 0 2006.286.04:30:00.44#ibcon#*after write, iclass 33, count 0 2006.286.04:30:00.44#ibcon#*before return 0, iclass 33, count 0 2006.286.04:30:00.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:30:00.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:30:00.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:30:00.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:30:00.44$vck44/vb=3,4 2006.286.04:30:00.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.04:30:00.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.04:30:00.44#ibcon#ireg 11 cls_cnt 2 2006.286.04:30:00.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:30:00.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:30:00.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:30:00.50#ibcon#enter wrdev, iclass 35, count 2 2006.286.04:30:00.50#ibcon#first serial, iclass 35, count 2 2006.286.04:30:00.50#ibcon#enter sib2, iclass 35, count 2 2006.286.04:30:00.50#ibcon#flushed, iclass 35, count 2 2006.286.04:30:00.50#ibcon#about to write, iclass 35, count 2 2006.286.04:30:00.50#ibcon#wrote, iclass 35, count 2 2006.286.04:30:00.50#ibcon#about to read 3, iclass 35, count 2 2006.286.04:30:00.52#ibcon#read 3, iclass 35, count 2 2006.286.04:30:00.52#ibcon#about to read 4, iclass 35, count 2 2006.286.04:30:00.52#ibcon#read 4, iclass 35, count 2 2006.286.04:30:00.52#ibcon#about to read 5, iclass 35, count 2 2006.286.04:30:00.52#ibcon#read 5, iclass 35, count 2 2006.286.04:30:00.52#ibcon#about to read 6, iclass 35, count 2 2006.286.04:30:00.52#ibcon#read 6, iclass 35, count 2 2006.286.04:30:00.52#ibcon#end of sib2, iclass 35, count 2 2006.286.04:30:00.52#ibcon#*mode == 0, iclass 35, count 2 2006.286.04:30:00.52#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.04:30:00.52#ibcon#[27=AT03-04\r\n] 2006.286.04:30:00.52#ibcon#*before write, iclass 35, count 2 2006.286.04:30:00.52#ibcon#enter sib2, iclass 35, count 2 2006.286.04:30:00.52#ibcon#flushed, iclass 35, count 2 2006.286.04:30:00.52#ibcon#about to write, iclass 35, count 2 2006.286.04:30:00.52#ibcon#wrote, iclass 35, count 2 2006.286.04:30:00.52#ibcon#about to read 3, iclass 35, count 2 2006.286.04:30:00.55#ibcon#read 3, iclass 35, count 2 2006.286.04:30:00.55#ibcon#about to read 4, iclass 35, count 2 2006.286.04:30:00.55#ibcon#read 4, iclass 35, count 2 2006.286.04:30:00.55#ibcon#about to read 5, iclass 35, count 2 2006.286.04:30:00.55#ibcon#read 5, iclass 35, count 2 2006.286.04:30:00.55#ibcon#about to read 6, iclass 35, count 2 2006.286.04:30:00.55#ibcon#read 6, iclass 35, count 2 2006.286.04:30:00.55#ibcon#end of sib2, iclass 35, count 2 2006.286.04:30:00.55#ibcon#*after write, iclass 35, count 2 2006.286.04:30:00.55#ibcon#*before return 0, iclass 35, count 2 2006.286.04:30:00.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:30:00.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:30:00.55#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.04:30:00.55#ibcon#ireg 7 cls_cnt 0 2006.286.04:30:00.55#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:30:00.67#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:30:00.67#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:30:00.67#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:30:00.67#ibcon#first serial, iclass 35, count 0 2006.286.04:30:00.67#ibcon#enter sib2, iclass 35, count 0 2006.286.04:30:00.67#ibcon#flushed, iclass 35, count 0 2006.286.04:30:00.67#ibcon#about to write, iclass 35, count 0 2006.286.04:30:00.67#ibcon#wrote, iclass 35, count 0 2006.286.04:30:00.67#ibcon#about to read 3, iclass 35, count 0 2006.286.04:30:00.69#ibcon#read 3, iclass 35, count 0 2006.286.04:30:00.69#ibcon#about to read 4, iclass 35, count 0 2006.286.04:30:00.69#ibcon#read 4, iclass 35, count 0 2006.286.04:30:00.69#ibcon#about to read 5, iclass 35, count 0 2006.286.04:30:00.69#ibcon#read 5, iclass 35, count 0 2006.286.04:30:00.69#ibcon#about to read 6, iclass 35, count 0 2006.286.04:30:00.69#ibcon#read 6, iclass 35, count 0 2006.286.04:30:00.69#ibcon#end of sib2, iclass 35, count 0 2006.286.04:30:00.69#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:30:00.69#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:30:00.69#ibcon#[27=USB\r\n] 2006.286.04:30:00.69#ibcon#*before write, iclass 35, count 0 2006.286.04:30:00.69#ibcon#enter sib2, iclass 35, count 0 2006.286.04:30:00.69#ibcon#flushed, iclass 35, count 0 2006.286.04:30:00.69#ibcon#about to write, iclass 35, count 0 2006.286.04:30:00.69#ibcon#wrote, iclass 35, count 0 2006.286.04:30:00.69#ibcon#about to read 3, iclass 35, count 0 2006.286.04:30:00.72#ibcon#read 3, iclass 35, count 0 2006.286.04:30:00.72#ibcon#about to read 4, iclass 35, count 0 2006.286.04:30:00.72#ibcon#read 4, iclass 35, count 0 2006.286.04:30:00.72#ibcon#about to read 5, iclass 35, count 0 2006.286.04:30:00.72#ibcon#read 5, iclass 35, count 0 2006.286.04:30:00.72#ibcon#about to read 6, iclass 35, count 0 2006.286.04:30:00.72#ibcon#read 6, iclass 35, count 0 2006.286.04:30:00.72#ibcon#end of sib2, iclass 35, count 0 2006.286.04:30:00.72#ibcon#*after write, iclass 35, count 0 2006.286.04:30:00.72#ibcon#*before return 0, iclass 35, count 0 2006.286.04:30:00.72#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:30:00.72#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:30:00.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:30:00.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:30:00.72$vck44/vblo=4,679.99 2006.286.04:30:00.72#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.04:30:00.72#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.04:30:00.72#ibcon#ireg 17 cls_cnt 0 2006.286.04:30:00.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:30:00.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:30:00.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:30:00.72#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:30:00.72#ibcon#first serial, iclass 37, count 0 2006.286.04:30:00.72#ibcon#enter sib2, iclass 37, count 0 2006.286.04:30:00.72#ibcon#flushed, iclass 37, count 0 2006.286.04:30:00.72#ibcon#about to write, iclass 37, count 0 2006.286.04:30:00.72#ibcon#wrote, iclass 37, count 0 2006.286.04:30:00.72#ibcon#about to read 3, iclass 37, count 0 2006.286.04:30:00.74#ibcon#read 3, iclass 37, count 0 2006.286.04:30:00.88#ibcon#about to read 4, iclass 37, count 0 2006.286.04:30:00.88#ibcon#read 4, iclass 37, count 0 2006.286.04:30:00.88#ibcon#about to read 5, iclass 37, count 0 2006.286.04:30:00.88#ibcon#read 5, iclass 37, count 0 2006.286.04:30:00.88#ibcon#about to read 6, iclass 37, count 0 2006.286.04:30:00.88#ibcon#read 6, iclass 37, count 0 2006.286.04:30:00.88#ibcon#end of sib2, iclass 37, count 0 2006.286.04:30:00.88#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:30:00.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:30:00.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:30:00.88#ibcon#*before write, iclass 37, count 0 2006.286.04:30:00.88#ibcon#enter sib2, iclass 37, count 0 2006.286.04:30:00.88#ibcon#flushed, iclass 37, count 0 2006.286.04:30:00.88#ibcon#about to write, iclass 37, count 0 2006.286.04:30:00.88#ibcon#wrote, iclass 37, count 0 2006.286.04:30:00.88#ibcon#about to read 3, iclass 37, count 0 2006.286.04:30:00.92#ibcon#read 3, iclass 37, count 0 2006.286.04:30:00.92#ibcon#about to read 4, iclass 37, count 0 2006.286.04:30:00.92#ibcon#read 4, iclass 37, count 0 2006.286.04:30:00.92#ibcon#about to read 5, iclass 37, count 0 2006.286.04:30:00.92#ibcon#read 5, iclass 37, count 0 2006.286.04:30:00.92#ibcon#about to read 6, iclass 37, count 0 2006.286.04:30:00.92#ibcon#read 6, iclass 37, count 0 2006.286.04:30:00.92#ibcon#end of sib2, iclass 37, count 0 2006.286.04:30:00.92#ibcon#*after write, iclass 37, count 0 2006.286.04:30:00.92#ibcon#*before return 0, iclass 37, count 0 2006.286.04:30:00.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:30:00.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:30:00.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:30:00.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:30:00.92$vck44/vb=4,5 2006.286.04:30:00.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.04:30:00.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.04:30:00.92#ibcon#ireg 11 cls_cnt 2 2006.286.04:30:00.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:30:00.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:30:00.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:30:00.92#ibcon#enter wrdev, iclass 39, count 2 2006.286.04:30:00.92#ibcon#first serial, iclass 39, count 2 2006.286.04:30:00.92#ibcon#enter sib2, iclass 39, count 2 2006.286.04:30:00.92#ibcon#flushed, iclass 39, count 2 2006.286.04:30:00.92#ibcon#about to write, iclass 39, count 2 2006.286.04:30:00.93#ibcon#wrote, iclass 39, count 2 2006.286.04:30:00.93#ibcon#about to read 3, iclass 39, count 2 2006.286.04:30:00.94#ibcon#read 3, iclass 39, count 2 2006.286.04:30:00.94#ibcon#about to read 4, iclass 39, count 2 2006.286.04:30:00.94#ibcon#read 4, iclass 39, count 2 2006.286.04:30:00.94#ibcon#about to read 5, iclass 39, count 2 2006.286.04:30:00.94#ibcon#read 5, iclass 39, count 2 2006.286.04:30:00.94#ibcon#about to read 6, iclass 39, count 2 2006.286.04:30:00.94#ibcon#read 6, iclass 39, count 2 2006.286.04:30:00.94#ibcon#end of sib2, iclass 39, count 2 2006.286.04:30:00.94#ibcon#*mode == 0, iclass 39, count 2 2006.286.04:30:00.94#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.04:30:00.94#ibcon#[27=AT04-05\r\n] 2006.286.04:30:00.94#ibcon#*before write, iclass 39, count 2 2006.286.04:30:00.94#ibcon#enter sib2, iclass 39, count 2 2006.286.04:30:00.94#ibcon#flushed, iclass 39, count 2 2006.286.04:30:00.94#ibcon#about to write, iclass 39, count 2 2006.286.04:30:00.94#ibcon#wrote, iclass 39, count 2 2006.286.04:30:00.94#ibcon#about to read 3, iclass 39, count 2 2006.286.04:30:00.97#ibcon#read 3, iclass 39, count 2 2006.286.04:30:00.97#ibcon#about to read 4, iclass 39, count 2 2006.286.04:30:00.97#ibcon#read 4, iclass 39, count 2 2006.286.04:30:00.97#ibcon#about to read 5, iclass 39, count 2 2006.286.04:30:00.97#ibcon#read 5, iclass 39, count 2 2006.286.04:30:00.97#ibcon#about to read 6, iclass 39, count 2 2006.286.04:30:00.97#ibcon#read 6, iclass 39, count 2 2006.286.04:30:00.97#ibcon#end of sib2, iclass 39, count 2 2006.286.04:30:00.97#ibcon#*after write, iclass 39, count 2 2006.286.04:30:00.97#ibcon#*before return 0, iclass 39, count 2 2006.286.04:30:00.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:30:00.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:30:00.97#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.04:30:00.97#ibcon#ireg 7 cls_cnt 0 2006.286.04:30:00.97#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:30:01.09#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:30:01.09#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:30:01.09#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:30:01.09#ibcon#first serial, iclass 39, count 0 2006.286.04:30:01.09#ibcon#enter sib2, iclass 39, count 0 2006.286.04:30:01.09#ibcon#flushed, iclass 39, count 0 2006.286.04:30:01.09#ibcon#about to write, iclass 39, count 0 2006.286.04:30:01.09#ibcon#wrote, iclass 39, count 0 2006.286.04:30:01.09#ibcon#about to read 3, iclass 39, count 0 2006.286.04:30:01.11#ibcon#read 3, iclass 39, count 0 2006.286.04:30:01.11#ibcon#about to read 4, iclass 39, count 0 2006.286.04:30:01.11#ibcon#read 4, iclass 39, count 0 2006.286.04:30:01.11#ibcon#about to read 5, iclass 39, count 0 2006.286.04:30:01.11#ibcon#read 5, iclass 39, count 0 2006.286.04:30:01.11#ibcon#about to read 6, iclass 39, count 0 2006.286.04:30:01.11#ibcon#read 6, iclass 39, count 0 2006.286.04:30:01.11#ibcon#end of sib2, iclass 39, count 0 2006.286.04:30:01.11#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:30:01.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:30:01.11#ibcon#[27=USB\r\n] 2006.286.04:30:01.11#ibcon#*before write, iclass 39, count 0 2006.286.04:30:01.11#ibcon#enter sib2, iclass 39, count 0 2006.286.04:30:01.11#ibcon#flushed, iclass 39, count 0 2006.286.04:30:01.11#ibcon#about to write, iclass 39, count 0 2006.286.04:30:01.11#ibcon#wrote, iclass 39, count 0 2006.286.04:30:01.11#ibcon#about to read 3, iclass 39, count 0 2006.286.04:30:01.14#ibcon#read 3, iclass 39, count 0 2006.286.04:30:01.14#ibcon#about to read 4, iclass 39, count 0 2006.286.04:30:01.14#ibcon#read 4, iclass 39, count 0 2006.286.04:30:01.14#ibcon#about to read 5, iclass 39, count 0 2006.286.04:30:01.14#ibcon#read 5, iclass 39, count 0 2006.286.04:30:01.14#ibcon#about to read 6, iclass 39, count 0 2006.286.04:30:01.14#ibcon#read 6, iclass 39, count 0 2006.286.04:30:01.14#ibcon#end of sib2, iclass 39, count 0 2006.286.04:30:01.14#ibcon#*after write, iclass 39, count 0 2006.286.04:30:01.14#ibcon#*before return 0, iclass 39, count 0 2006.286.04:30:01.14#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:30:01.14#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:30:01.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:30:01.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:30:01.15$vck44/vblo=5,709.99 2006.286.04:30:01.15#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.04:30:01.15#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.04:30:01.15#ibcon#ireg 17 cls_cnt 0 2006.286.04:30:01.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:30:01.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:30:01.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:30:01.15#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:30:01.15#ibcon#first serial, iclass 3, count 0 2006.286.04:30:01.15#ibcon#enter sib2, iclass 3, count 0 2006.286.04:30:01.15#ibcon#flushed, iclass 3, count 0 2006.286.04:30:01.15#ibcon#about to write, iclass 3, count 0 2006.286.04:30:01.15#ibcon#wrote, iclass 3, count 0 2006.286.04:30:01.15#ibcon#about to read 3, iclass 3, count 0 2006.286.04:30:01.16#ibcon#read 3, iclass 3, count 0 2006.286.04:30:01.16#ibcon#about to read 4, iclass 3, count 0 2006.286.04:30:01.16#ibcon#read 4, iclass 3, count 0 2006.286.04:30:01.16#ibcon#about to read 5, iclass 3, count 0 2006.286.04:30:01.16#ibcon#read 5, iclass 3, count 0 2006.286.04:30:01.16#ibcon#about to read 6, iclass 3, count 0 2006.286.04:30:01.16#ibcon#read 6, iclass 3, count 0 2006.286.04:30:01.16#ibcon#end of sib2, iclass 3, count 0 2006.286.04:30:01.16#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:30:01.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:30:01.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:30:01.16#ibcon#*before write, iclass 3, count 0 2006.286.04:30:01.16#ibcon#enter sib2, iclass 3, count 0 2006.286.04:30:01.16#ibcon#flushed, iclass 3, count 0 2006.286.04:30:01.16#ibcon#about to write, iclass 3, count 0 2006.286.04:30:01.16#ibcon#wrote, iclass 3, count 0 2006.286.04:30:01.16#ibcon#about to read 3, iclass 3, count 0 2006.286.04:30:01.20#ibcon#read 3, iclass 3, count 0 2006.286.04:30:01.20#ibcon#about to read 4, iclass 3, count 0 2006.286.04:30:01.20#ibcon#read 4, iclass 3, count 0 2006.286.04:30:01.20#ibcon#about to read 5, iclass 3, count 0 2006.286.04:30:01.20#ibcon#read 5, iclass 3, count 0 2006.286.04:30:01.20#ibcon#about to read 6, iclass 3, count 0 2006.286.04:30:01.20#ibcon#read 6, iclass 3, count 0 2006.286.04:30:01.20#ibcon#end of sib2, iclass 3, count 0 2006.286.04:30:01.20#ibcon#*after write, iclass 3, count 0 2006.286.04:30:01.20#ibcon#*before return 0, iclass 3, count 0 2006.286.04:30:01.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:30:01.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:30:01.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:30:01.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:30:01.20$vck44/vb=5,4 2006.286.04:30:01.20#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.04:30:01.20#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.04:30:01.20#ibcon#ireg 11 cls_cnt 2 2006.286.04:30:01.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:30:01.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:30:01.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:30:01.26#ibcon#enter wrdev, iclass 5, count 2 2006.286.04:30:01.26#ibcon#first serial, iclass 5, count 2 2006.286.04:30:01.26#ibcon#enter sib2, iclass 5, count 2 2006.286.04:30:01.26#ibcon#flushed, iclass 5, count 2 2006.286.04:30:01.26#ibcon#about to write, iclass 5, count 2 2006.286.04:30:01.26#ibcon#wrote, iclass 5, count 2 2006.286.04:30:01.26#ibcon#about to read 3, iclass 5, count 2 2006.286.04:30:01.28#ibcon#read 3, iclass 5, count 2 2006.286.04:30:01.28#ibcon#about to read 4, iclass 5, count 2 2006.286.04:30:01.28#ibcon#read 4, iclass 5, count 2 2006.286.04:30:01.28#ibcon#about to read 5, iclass 5, count 2 2006.286.04:30:01.28#ibcon#read 5, iclass 5, count 2 2006.286.04:30:01.28#ibcon#about to read 6, iclass 5, count 2 2006.286.04:30:01.28#ibcon#read 6, iclass 5, count 2 2006.286.04:30:01.28#ibcon#end of sib2, iclass 5, count 2 2006.286.04:30:01.28#ibcon#*mode == 0, iclass 5, count 2 2006.286.04:30:01.28#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.04:30:01.28#ibcon#[27=AT05-04\r\n] 2006.286.04:30:01.28#ibcon#*before write, iclass 5, count 2 2006.286.04:30:01.28#ibcon#enter sib2, iclass 5, count 2 2006.286.04:30:01.28#ibcon#flushed, iclass 5, count 2 2006.286.04:30:01.28#ibcon#about to write, iclass 5, count 2 2006.286.04:30:01.28#ibcon#wrote, iclass 5, count 2 2006.286.04:30:01.28#ibcon#about to read 3, iclass 5, count 2 2006.286.04:30:01.31#ibcon#read 3, iclass 5, count 2 2006.286.04:30:01.31#ibcon#about to read 4, iclass 5, count 2 2006.286.04:30:01.31#ibcon#read 4, iclass 5, count 2 2006.286.04:30:01.31#ibcon#about to read 5, iclass 5, count 2 2006.286.04:30:01.31#ibcon#read 5, iclass 5, count 2 2006.286.04:30:01.31#ibcon#about to read 6, iclass 5, count 2 2006.286.04:30:01.31#ibcon#read 6, iclass 5, count 2 2006.286.04:30:01.31#ibcon#end of sib2, iclass 5, count 2 2006.286.04:30:01.31#ibcon#*after write, iclass 5, count 2 2006.286.04:30:01.31#ibcon#*before return 0, iclass 5, count 2 2006.286.04:30:01.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:30:01.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:30:01.31#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.04:30:01.31#ibcon#ireg 7 cls_cnt 0 2006.286.04:30:01.31#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:30:01.42#abcon#<5=/05 4.2 7.7 22.16 741014.7\r\n> 2006.286.04:30:01.43#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:30:01.43#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:30:01.43#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:30:01.43#ibcon#first serial, iclass 5, count 0 2006.286.04:30:01.43#ibcon#enter sib2, iclass 5, count 0 2006.286.04:30:01.43#ibcon#flushed, iclass 5, count 0 2006.286.04:30:01.43#ibcon#about to write, iclass 5, count 0 2006.286.04:30:01.43#ibcon#wrote, iclass 5, count 0 2006.286.04:30:01.43#ibcon#about to read 3, iclass 5, count 0 2006.286.04:30:01.44#abcon#{5=INTERFACE CLEAR} 2006.286.04:30:01.45#ibcon#read 3, iclass 5, count 0 2006.286.04:30:01.45#ibcon#about to read 4, iclass 5, count 0 2006.286.04:30:01.45#ibcon#read 4, iclass 5, count 0 2006.286.04:30:01.45#ibcon#about to read 5, iclass 5, count 0 2006.286.04:30:01.45#ibcon#read 5, iclass 5, count 0 2006.286.04:30:01.45#ibcon#about to read 6, iclass 5, count 0 2006.286.04:30:01.45#ibcon#read 6, iclass 5, count 0 2006.286.04:30:01.45#ibcon#end of sib2, iclass 5, count 0 2006.286.04:30:01.45#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:30:01.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:30:01.45#ibcon#[27=USB\r\n] 2006.286.04:30:01.45#ibcon#*before write, iclass 5, count 0 2006.286.04:30:01.45#ibcon#enter sib2, iclass 5, count 0 2006.286.04:30:01.45#ibcon#flushed, iclass 5, count 0 2006.286.04:30:01.45#ibcon#about to write, iclass 5, count 0 2006.286.04:30:01.45#ibcon#wrote, iclass 5, count 0 2006.286.04:30:01.45#ibcon#about to read 3, iclass 5, count 0 2006.286.04:30:01.48#ibcon#read 3, iclass 5, count 0 2006.286.04:30:01.48#ibcon#about to read 4, iclass 5, count 0 2006.286.04:30:01.48#ibcon#read 4, iclass 5, count 0 2006.286.04:30:01.48#ibcon#about to read 5, iclass 5, count 0 2006.286.04:30:01.48#ibcon#read 5, iclass 5, count 0 2006.286.04:30:01.48#ibcon#about to read 6, iclass 5, count 0 2006.286.04:30:01.48#ibcon#read 6, iclass 5, count 0 2006.286.04:30:01.48#ibcon#end of sib2, iclass 5, count 0 2006.286.04:30:01.48#ibcon#*after write, iclass 5, count 0 2006.286.04:30:01.48#ibcon#*before return 0, iclass 5, count 0 2006.286.04:30:01.48#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:30:01.48#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:30:01.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:30:01.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:30:01.48$vck44/vblo=6,719.99 2006.286.04:30:01.48#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.04:30:01.48#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.04:30:01.48#ibcon#ireg 17 cls_cnt 0 2006.286.04:30:01.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:30:01.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:30:01.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:30:01.48#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:30:01.49#ibcon#first serial, iclass 13, count 0 2006.286.04:30:01.49#ibcon#enter sib2, iclass 13, count 0 2006.286.04:30:01.49#ibcon#flushed, iclass 13, count 0 2006.286.04:30:01.49#ibcon#about to write, iclass 13, count 0 2006.286.04:30:01.49#ibcon#wrote, iclass 13, count 0 2006.286.04:30:01.49#ibcon#about to read 3, iclass 13, count 0 2006.286.04:30:01.50#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:30:01.50#ibcon#read 3, iclass 13, count 0 2006.286.04:30:01.50#ibcon#about to read 4, iclass 13, count 0 2006.286.04:30:01.50#ibcon#read 4, iclass 13, count 0 2006.286.04:30:01.50#ibcon#about to read 5, iclass 13, count 0 2006.286.04:30:01.50#ibcon#read 5, iclass 13, count 0 2006.286.04:30:01.50#ibcon#about to read 6, iclass 13, count 0 2006.286.04:30:01.50#ibcon#read 6, iclass 13, count 0 2006.286.04:30:01.50#ibcon#end of sib2, iclass 13, count 0 2006.286.04:30:01.50#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:30:01.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:30:01.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:30:01.50#ibcon#*before write, iclass 13, count 0 2006.286.04:30:01.50#ibcon#enter sib2, iclass 13, count 0 2006.286.04:30:01.50#ibcon#flushed, iclass 13, count 0 2006.286.04:30:01.50#ibcon#about to write, iclass 13, count 0 2006.286.04:30:01.50#ibcon#wrote, iclass 13, count 0 2006.286.04:30:01.50#ibcon#about to read 3, iclass 13, count 0 2006.286.04:30:01.54#ibcon#read 3, iclass 13, count 0 2006.286.04:30:01.54#ibcon#about to read 4, iclass 13, count 0 2006.286.04:30:01.54#ibcon#read 4, iclass 13, count 0 2006.286.04:30:01.54#ibcon#about to read 5, iclass 13, count 0 2006.286.04:30:01.54#ibcon#read 5, iclass 13, count 0 2006.286.04:30:01.54#ibcon#about to read 6, iclass 13, count 0 2006.286.04:30:01.54#ibcon#read 6, iclass 13, count 0 2006.286.04:30:01.54#ibcon#end of sib2, iclass 13, count 0 2006.286.04:30:01.54#ibcon#*after write, iclass 13, count 0 2006.286.04:30:01.54#ibcon#*before return 0, iclass 13, count 0 2006.286.04:30:01.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:30:01.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:30:01.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:30:01.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:30:01.54$vck44/vb=6,3 2006.286.04:30:01.54#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.04:30:01.54#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.04:30:01.54#ibcon#ireg 11 cls_cnt 2 2006.286.04:30:01.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:30:01.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:30:01.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:30:01.60#ibcon#enter wrdev, iclass 15, count 2 2006.286.04:30:01.60#ibcon#first serial, iclass 15, count 2 2006.286.04:30:01.60#ibcon#enter sib2, iclass 15, count 2 2006.286.04:30:01.60#ibcon#flushed, iclass 15, count 2 2006.286.04:30:01.60#ibcon#about to write, iclass 15, count 2 2006.286.04:30:01.60#ibcon#wrote, iclass 15, count 2 2006.286.04:30:01.60#ibcon#about to read 3, iclass 15, count 2 2006.286.04:30:01.62#ibcon#read 3, iclass 15, count 2 2006.286.04:30:01.62#ibcon#about to read 4, iclass 15, count 2 2006.286.04:30:01.62#ibcon#read 4, iclass 15, count 2 2006.286.04:30:01.62#ibcon#about to read 5, iclass 15, count 2 2006.286.04:30:01.62#ibcon#read 5, iclass 15, count 2 2006.286.04:30:01.62#ibcon#about to read 6, iclass 15, count 2 2006.286.04:30:01.62#ibcon#read 6, iclass 15, count 2 2006.286.04:30:01.62#ibcon#end of sib2, iclass 15, count 2 2006.286.04:30:01.62#ibcon#*mode == 0, iclass 15, count 2 2006.286.04:30:01.62#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.04:30:01.62#ibcon#[27=AT06-03\r\n] 2006.286.04:30:01.62#ibcon#*before write, iclass 15, count 2 2006.286.04:30:01.62#ibcon#enter sib2, iclass 15, count 2 2006.286.04:30:01.62#ibcon#flushed, iclass 15, count 2 2006.286.04:30:01.62#ibcon#about to write, iclass 15, count 2 2006.286.04:30:01.62#ibcon#wrote, iclass 15, count 2 2006.286.04:30:01.62#ibcon#about to read 3, iclass 15, count 2 2006.286.04:30:01.65#ibcon#read 3, iclass 15, count 2 2006.286.04:30:01.65#ibcon#about to read 4, iclass 15, count 2 2006.286.04:30:01.65#ibcon#read 4, iclass 15, count 2 2006.286.04:30:01.65#ibcon#about to read 5, iclass 15, count 2 2006.286.04:30:01.65#ibcon#read 5, iclass 15, count 2 2006.286.04:30:01.65#ibcon#about to read 6, iclass 15, count 2 2006.286.04:30:01.65#ibcon#read 6, iclass 15, count 2 2006.286.04:30:01.65#ibcon#end of sib2, iclass 15, count 2 2006.286.04:30:01.65#ibcon#*after write, iclass 15, count 2 2006.286.04:30:01.65#ibcon#*before return 0, iclass 15, count 2 2006.286.04:30:01.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:30:01.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:30:01.65#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.04:30:01.65#ibcon#ireg 7 cls_cnt 0 2006.286.04:30:01.65#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:30:01.77#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:30:01.77#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:30:01.77#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:30:01.77#ibcon#first serial, iclass 15, count 0 2006.286.04:30:01.77#ibcon#enter sib2, iclass 15, count 0 2006.286.04:30:01.77#ibcon#flushed, iclass 15, count 0 2006.286.04:30:01.77#ibcon#about to write, iclass 15, count 0 2006.286.04:30:01.77#ibcon#wrote, iclass 15, count 0 2006.286.04:30:01.77#ibcon#about to read 3, iclass 15, count 0 2006.286.04:30:01.79#ibcon#read 3, iclass 15, count 0 2006.286.04:30:01.79#ibcon#about to read 4, iclass 15, count 0 2006.286.04:30:01.79#ibcon#read 4, iclass 15, count 0 2006.286.04:30:01.79#ibcon#about to read 5, iclass 15, count 0 2006.286.04:30:01.79#ibcon#read 5, iclass 15, count 0 2006.286.04:30:01.79#ibcon#about to read 6, iclass 15, count 0 2006.286.04:30:01.79#ibcon#read 6, iclass 15, count 0 2006.286.04:30:01.95#ibcon#end of sib2, iclass 15, count 0 2006.286.04:30:01.95#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:30:01.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:30:01.95#ibcon#[27=USB\r\n] 2006.286.04:30:01.95#ibcon#*before write, iclass 15, count 0 2006.286.04:30:01.95#ibcon#enter sib2, iclass 15, count 0 2006.286.04:30:01.95#ibcon#flushed, iclass 15, count 0 2006.286.04:30:01.95#ibcon#about to write, iclass 15, count 0 2006.286.04:30:01.95#ibcon#wrote, iclass 15, count 0 2006.286.04:30:01.95#ibcon#about to read 3, iclass 15, count 0 2006.286.04:30:01.98#ibcon#read 3, iclass 15, count 0 2006.286.04:30:01.98#ibcon#about to read 4, iclass 15, count 0 2006.286.04:30:01.98#ibcon#read 4, iclass 15, count 0 2006.286.04:30:01.98#ibcon#about to read 5, iclass 15, count 0 2006.286.04:30:01.98#ibcon#read 5, iclass 15, count 0 2006.286.04:30:01.98#ibcon#about to read 6, iclass 15, count 0 2006.286.04:30:01.98#ibcon#read 6, iclass 15, count 0 2006.286.04:30:01.98#ibcon#end of sib2, iclass 15, count 0 2006.286.04:30:01.98#ibcon#*after write, iclass 15, count 0 2006.286.04:30:01.98#ibcon#*before return 0, iclass 15, count 0 2006.286.04:30:01.98#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:30:01.98#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:30:01.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:30:01.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:30:01.98$vck44/vblo=7,734.99 2006.286.04:30:01.98#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.04:30:01.98#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.04:30:01.98#ibcon#ireg 17 cls_cnt 0 2006.286.04:30:01.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:30:01.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:30:01.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:30:01.98#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:30:01.98#ibcon#first serial, iclass 17, count 0 2006.286.04:30:01.98#ibcon#enter sib2, iclass 17, count 0 2006.286.04:30:01.98#ibcon#flushed, iclass 17, count 0 2006.286.04:30:01.98#ibcon#about to write, iclass 17, count 0 2006.286.04:30:01.98#ibcon#wrote, iclass 17, count 0 2006.286.04:30:01.99#ibcon#about to read 3, iclass 17, count 0 2006.286.04:30:02.00#ibcon#read 3, iclass 17, count 0 2006.286.04:30:02.00#ibcon#about to read 4, iclass 17, count 0 2006.286.04:30:02.00#ibcon#read 4, iclass 17, count 0 2006.286.04:30:02.00#ibcon#about to read 5, iclass 17, count 0 2006.286.04:30:02.00#ibcon#read 5, iclass 17, count 0 2006.286.04:30:02.00#ibcon#about to read 6, iclass 17, count 0 2006.286.04:30:02.00#ibcon#read 6, iclass 17, count 0 2006.286.04:30:02.00#ibcon#end of sib2, iclass 17, count 0 2006.286.04:30:02.00#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:30:02.00#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:30:02.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:30:02.00#ibcon#*before write, iclass 17, count 0 2006.286.04:30:02.00#ibcon#enter sib2, iclass 17, count 0 2006.286.04:30:02.00#ibcon#flushed, iclass 17, count 0 2006.286.04:30:02.00#ibcon#about to write, iclass 17, count 0 2006.286.04:30:02.00#ibcon#wrote, iclass 17, count 0 2006.286.04:30:02.00#ibcon#about to read 3, iclass 17, count 0 2006.286.04:30:02.04#ibcon#read 3, iclass 17, count 0 2006.286.04:30:02.04#ibcon#about to read 4, iclass 17, count 0 2006.286.04:30:02.04#ibcon#read 4, iclass 17, count 0 2006.286.04:30:02.04#ibcon#about to read 5, iclass 17, count 0 2006.286.04:30:02.04#ibcon#read 5, iclass 17, count 0 2006.286.04:30:02.04#ibcon#about to read 6, iclass 17, count 0 2006.286.04:30:02.04#ibcon#read 6, iclass 17, count 0 2006.286.04:30:02.04#ibcon#end of sib2, iclass 17, count 0 2006.286.04:30:02.04#ibcon#*after write, iclass 17, count 0 2006.286.04:30:02.04#ibcon#*before return 0, iclass 17, count 0 2006.286.04:30:02.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:30:02.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:30:02.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:30:02.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:30:02.04$vck44/vb=7,4 2006.286.04:30:02.04#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.04:30:02.04#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.04:30:02.04#ibcon#ireg 11 cls_cnt 2 2006.286.04:30:02.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:30:02.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:30:02.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:30:02.10#ibcon#enter wrdev, iclass 19, count 2 2006.286.04:30:02.10#ibcon#first serial, iclass 19, count 2 2006.286.04:30:02.10#ibcon#enter sib2, iclass 19, count 2 2006.286.04:30:02.10#ibcon#flushed, iclass 19, count 2 2006.286.04:30:02.10#ibcon#about to write, iclass 19, count 2 2006.286.04:30:02.10#ibcon#wrote, iclass 19, count 2 2006.286.04:30:02.10#ibcon#about to read 3, iclass 19, count 2 2006.286.04:30:02.12#ibcon#read 3, iclass 19, count 2 2006.286.04:30:02.12#ibcon#about to read 4, iclass 19, count 2 2006.286.04:30:02.12#ibcon#read 4, iclass 19, count 2 2006.286.04:30:02.12#ibcon#about to read 5, iclass 19, count 2 2006.286.04:30:02.12#ibcon#read 5, iclass 19, count 2 2006.286.04:30:02.12#ibcon#about to read 6, iclass 19, count 2 2006.286.04:30:02.12#ibcon#read 6, iclass 19, count 2 2006.286.04:30:02.12#ibcon#end of sib2, iclass 19, count 2 2006.286.04:30:02.12#ibcon#*mode == 0, iclass 19, count 2 2006.286.04:30:02.12#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.04:30:02.12#ibcon#[27=AT07-04\r\n] 2006.286.04:30:02.12#ibcon#*before write, iclass 19, count 2 2006.286.04:30:02.12#ibcon#enter sib2, iclass 19, count 2 2006.286.04:30:02.12#ibcon#flushed, iclass 19, count 2 2006.286.04:30:02.12#ibcon#about to write, iclass 19, count 2 2006.286.04:30:02.12#ibcon#wrote, iclass 19, count 2 2006.286.04:30:02.12#ibcon#about to read 3, iclass 19, count 2 2006.286.04:30:02.15#ibcon#read 3, iclass 19, count 2 2006.286.04:30:02.15#ibcon#about to read 4, iclass 19, count 2 2006.286.04:30:02.15#ibcon#read 4, iclass 19, count 2 2006.286.04:30:02.15#ibcon#about to read 5, iclass 19, count 2 2006.286.04:30:02.15#ibcon#read 5, iclass 19, count 2 2006.286.04:30:02.15#ibcon#about to read 6, iclass 19, count 2 2006.286.04:30:02.15#ibcon#read 6, iclass 19, count 2 2006.286.04:30:02.15#ibcon#end of sib2, iclass 19, count 2 2006.286.04:30:02.15#ibcon#*after write, iclass 19, count 2 2006.286.04:30:02.15#ibcon#*before return 0, iclass 19, count 2 2006.286.04:30:02.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:30:02.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:30:02.15#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.04:30:02.15#ibcon#ireg 7 cls_cnt 0 2006.286.04:30:02.15#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:30:02.27#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:30:02.27#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:30:02.27#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:30:02.27#ibcon#first serial, iclass 19, count 0 2006.286.04:30:02.27#ibcon#enter sib2, iclass 19, count 0 2006.286.04:30:02.27#ibcon#flushed, iclass 19, count 0 2006.286.04:30:02.27#ibcon#about to write, iclass 19, count 0 2006.286.04:30:02.27#ibcon#wrote, iclass 19, count 0 2006.286.04:30:02.27#ibcon#about to read 3, iclass 19, count 0 2006.286.04:30:02.29#ibcon#read 3, iclass 19, count 0 2006.286.04:30:02.29#ibcon#about to read 4, iclass 19, count 0 2006.286.04:30:02.29#ibcon#read 4, iclass 19, count 0 2006.286.04:30:02.29#ibcon#about to read 5, iclass 19, count 0 2006.286.04:30:02.29#ibcon#read 5, iclass 19, count 0 2006.286.04:30:02.29#ibcon#about to read 6, iclass 19, count 0 2006.286.04:30:02.29#ibcon#read 6, iclass 19, count 0 2006.286.04:30:02.29#ibcon#end of sib2, iclass 19, count 0 2006.286.04:30:02.29#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:30:02.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:30:02.29#ibcon#[27=USB\r\n] 2006.286.04:30:02.29#ibcon#*before write, iclass 19, count 0 2006.286.04:30:02.29#ibcon#enter sib2, iclass 19, count 0 2006.286.04:30:02.29#ibcon#flushed, iclass 19, count 0 2006.286.04:30:02.29#ibcon#about to write, iclass 19, count 0 2006.286.04:30:02.29#ibcon#wrote, iclass 19, count 0 2006.286.04:30:02.29#ibcon#about to read 3, iclass 19, count 0 2006.286.04:30:02.32#ibcon#read 3, iclass 19, count 0 2006.286.04:30:02.32#ibcon#about to read 4, iclass 19, count 0 2006.286.04:30:02.32#ibcon#read 4, iclass 19, count 0 2006.286.04:30:02.32#ibcon#about to read 5, iclass 19, count 0 2006.286.04:30:02.32#ibcon#read 5, iclass 19, count 0 2006.286.04:30:02.32#ibcon#about to read 6, iclass 19, count 0 2006.286.04:30:02.32#ibcon#read 6, iclass 19, count 0 2006.286.04:30:02.32#ibcon#end of sib2, iclass 19, count 0 2006.286.04:30:02.32#ibcon#*after write, iclass 19, count 0 2006.286.04:30:02.32#ibcon#*before return 0, iclass 19, count 0 2006.286.04:30:02.32#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:30:02.32#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:30:02.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:30:02.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:30:02.32$vck44/vblo=8,744.99 2006.286.04:30:02.32#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.04:30:02.32#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.04:30:02.32#ibcon#ireg 17 cls_cnt 0 2006.286.04:30:02.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:30:02.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:30:02.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:30:02.32#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:30:02.32#ibcon#first serial, iclass 21, count 0 2006.286.04:30:02.32#ibcon#enter sib2, iclass 21, count 0 2006.286.04:30:02.32#ibcon#flushed, iclass 21, count 0 2006.286.04:30:02.32#ibcon#about to write, iclass 21, count 0 2006.286.04:30:02.32#ibcon#wrote, iclass 21, count 0 2006.286.04:30:02.32#ibcon#about to read 3, iclass 21, count 0 2006.286.04:30:02.34#ibcon#read 3, iclass 21, count 0 2006.286.04:30:02.34#ibcon#about to read 4, iclass 21, count 0 2006.286.04:30:02.34#ibcon#read 4, iclass 21, count 0 2006.286.04:30:02.34#ibcon#about to read 5, iclass 21, count 0 2006.286.04:30:02.34#ibcon#read 5, iclass 21, count 0 2006.286.04:30:02.34#ibcon#about to read 6, iclass 21, count 0 2006.286.04:30:02.34#ibcon#read 6, iclass 21, count 0 2006.286.04:30:02.34#ibcon#end of sib2, iclass 21, count 0 2006.286.04:30:02.34#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:30:02.34#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:30:02.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:30:02.34#ibcon#*before write, iclass 21, count 0 2006.286.04:30:02.34#ibcon#enter sib2, iclass 21, count 0 2006.286.04:30:02.34#ibcon#flushed, iclass 21, count 0 2006.286.04:30:02.34#ibcon#about to write, iclass 21, count 0 2006.286.04:30:02.34#ibcon#wrote, iclass 21, count 0 2006.286.04:30:02.34#ibcon#about to read 3, iclass 21, count 0 2006.286.04:30:02.38#ibcon#read 3, iclass 21, count 0 2006.286.04:30:02.38#ibcon#about to read 4, iclass 21, count 0 2006.286.04:30:02.38#ibcon#read 4, iclass 21, count 0 2006.286.04:30:02.38#ibcon#about to read 5, iclass 21, count 0 2006.286.04:30:02.38#ibcon#read 5, iclass 21, count 0 2006.286.04:30:02.38#ibcon#about to read 6, iclass 21, count 0 2006.286.04:30:02.38#ibcon#read 6, iclass 21, count 0 2006.286.04:30:02.38#ibcon#end of sib2, iclass 21, count 0 2006.286.04:30:02.38#ibcon#*after write, iclass 21, count 0 2006.286.04:30:02.38#ibcon#*before return 0, iclass 21, count 0 2006.286.04:30:02.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:30:02.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:30:02.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:30:02.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:30:02.38$vck44/vb=8,4 2006.286.04:30:02.38#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.04:30:02.38#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.04:30:02.38#ibcon#ireg 11 cls_cnt 2 2006.286.04:30:02.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:30:02.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:30:02.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:30:02.44#ibcon#enter wrdev, iclass 23, count 2 2006.286.04:30:02.44#ibcon#first serial, iclass 23, count 2 2006.286.04:30:02.44#ibcon#enter sib2, iclass 23, count 2 2006.286.04:30:02.44#ibcon#flushed, iclass 23, count 2 2006.286.04:30:02.44#ibcon#about to write, iclass 23, count 2 2006.286.04:30:02.44#ibcon#wrote, iclass 23, count 2 2006.286.04:30:02.44#ibcon#about to read 3, iclass 23, count 2 2006.286.04:30:02.46#ibcon#read 3, iclass 23, count 2 2006.286.04:30:02.46#ibcon#about to read 4, iclass 23, count 2 2006.286.04:30:02.46#ibcon#read 4, iclass 23, count 2 2006.286.04:30:02.46#ibcon#about to read 5, iclass 23, count 2 2006.286.04:30:02.46#ibcon#read 5, iclass 23, count 2 2006.286.04:30:02.46#ibcon#about to read 6, iclass 23, count 2 2006.286.04:30:02.46#ibcon#read 6, iclass 23, count 2 2006.286.04:30:02.46#ibcon#end of sib2, iclass 23, count 2 2006.286.04:30:02.46#ibcon#*mode == 0, iclass 23, count 2 2006.286.04:30:02.46#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.04:30:02.46#ibcon#[27=AT08-04\r\n] 2006.286.04:30:02.46#ibcon#*before write, iclass 23, count 2 2006.286.04:30:02.46#ibcon#enter sib2, iclass 23, count 2 2006.286.04:30:02.46#ibcon#flushed, iclass 23, count 2 2006.286.04:30:02.46#ibcon#about to write, iclass 23, count 2 2006.286.04:30:02.46#ibcon#wrote, iclass 23, count 2 2006.286.04:30:02.46#ibcon#about to read 3, iclass 23, count 2 2006.286.04:30:02.49#ibcon#read 3, iclass 23, count 2 2006.286.04:30:02.49#ibcon#about to read 4, iclass 23, count 2 2006.286.04:30:02.49#ibcon#read 4, iclass 23, count 2 2006.286.04:30:02.49#ibcon#about to read 5, iclass 23, count 2 2006.286.04:30:02.49#ibcon#read 5, iclass 23, count 2 2006.286.04:30:02.49#ibcon#about to read 6, iclass 23, count 2 2006.286.04:30:02.49#ibcon#read 6, iclass 23, count 2 2006.286.04:30:02.49#ibcon#end of sib2, iclass 23, count 2 2006.286.04:30:02.49#ibcon#*after write, iclass 23, count 2 2006.286.04:30:02.49#ibcon#*before return 0, iclass 23, count 2 2006.286.04:30:02.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:30:02.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:30:02.49#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.04:30:02.49#ibcon#ireg 7 cls_cnt 0 2006.286.04:30:02.49#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:30:02.61#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:30:02.61#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:30:02.61#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:30:02.61#ibcon#first serial, iclass 23, count 0 2006.286.04:30:02.61#ibcon#enter sib2, iclass 23, count 0 2006.286.04:30:02.61#ibcon#flushed, iclass 23, count 0 2006.286.04:30:02.61#ibcon#about to write, iclass 23, count 0 2006.286.04:30:02.61#ibcon#wrote, iclass 23, count 0 2006.286.04:30:02.61#ibcon#about to read 3, iclass 23, count 0 2006.286.04:30:02.63#ibcon#read 3, iclass 23, count 0 2006.286.04:30:02.63#ibcon#about to read 4, iclass 23, count 0 2006.286.04:30:02.63#ibcon#read 4, iclass 23, count 0 2006.286.04:30:02.63#ibcon#about to read 5, iclass 23, count 0 2006.286.04:30:02.63#ibcon#read 5, iclass 23, count 0 2006.286.04:30:02.63#ibcon#about to read 6, iclass 23, count 0 2006.286.04:30:02.63#ibcon#read 6, iclass 23, count 0 2006.286.04:30:02.63#ibcon#end of sib2, iclass 23, count 0 2006.286.04:30:02.63#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:30:02.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:30:02.63#ibcon#[27=USB\r\n] 2006.286.04:30:02.63#ibcon#*before write, iclass 23, count 0 2006.286.04:30:02.63#ibcon#enter sib2, iclass 23, count 0 2006.286.04:30:02.63#ibcon#flushed, iclass 23, count 0 2006.286.04:30:02.63#ibcon#about to write, iclass 23, count 0 2006.286.04:30:02.63#ibcon#wrote, iclass 23, count 0 2006.286.04:30:02.63#ibcon#about to read 3, iclass 23, count 0 2006.286.04:30:02.66#ibcon#read 3, iclass 23, count 0 2006.286.04:30:02.66#ibcon#about to read 4, iclass 23, count 0 2006.286.04:30:02.66#ibcon#read 4, iclass 23, count 0 2006.286.04:30:02.66#ibcon#about to read 5, iclass 23, count 0 2006.286.04:30:02.66#ibcon#read 5, iclass 23, count 0 2006.286.04:30:02.66#ibcon#about to read 6, iclass 23, count 0 2006.286.04:30:02.66#ibcon#read 6, iclass 23, count 0 2006.286.04:30:02.66#ibcon#end of sib2, iclass 23, count 0 2006.286.04:30:02.66#ibcon#*after write, iclass 23, count 0 2006.286.04:30:02.66#ibcon#*before return 0, iclass 23, count 0 2006.286.04:30:02.66#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:30:02.66#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:30:02.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:30:02.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:30:02.66$vck44/vabw=wide 2006.286.04:30:02.66#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.04:30:02.66#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.04:30:02.66#ibcon#ireg 8 cls_cnt 0 2006.286.04:30:02.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:30:02.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:30:02.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:30:02.66#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:30:02.66#ibcon#first serial, iclass 25, count 0 2006.286.04:30:02.66#ibcon#enter sib2, iclass 25, count 0 2006.286.04:30:02.66#ibcon#flushed, iclass 25, count 0 2006.286.04:30:02.66#ibcon#about to write, iclass 25, count 0 2006.286.04:30:02.66#ibcon#wrote, iclass 25, count 0 2006.286.04:30:02.66#ibcon#about to read 3, iclass 25, count 0 2006.286.04:30:02.68#ibcon#read 3, iclass 25, count 0 2006.286.04:30:02.68#ibcon#about to read 4, iclass 25, count 0 2006.286.04:30:02.68#ibcon#read 4, iclass 25, count 0 2006.286.04:30:02.78#ibcon#about to read 5, iclass 25, count 0 2006.286.04:30:02.78#ibcon#read 5, iclass 25, count 0 2006.286.04:30:02.78#ibcon#about to read 6, iclass 25, count 0 2006.286.04:30:02.78#ibcon#read 6, iclass 25, count 0 2006.286.04:30:02.78#ibcon#end of sib2, iclass 25, count 0 2006.286.04:30:02.78#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:30:02.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:30:02.78#ibcon#[25=BW32\r\n] 2006.286.04:30:02.78#ibcon#*before write, iclass 25, count 0 2006.286.04:30:02.78#ibcon#enter sib2, iclass 25, count 0 2006.286.04:30:02.78#ibcon#flushed, iclass 25, count 0 2006.286.04:30:02.78#ibcon#about to write, iclass 25, count 0 2006.286.04:30:02.78#ibcon#wrote, iclass 25, count 0 2006.286.04:30:02.78#ibcon#about to read 3, iclass 25, count 0 2006.286.04:30:02.81#ibcon#read 3, iclass 25, count 0 2006.286.04:30:02.81#ibcon#about to read 4, iclass 25, count 0 2006.286.04:30:02.81#ibcon#read 4, iclass 25, count 0 2006.286.04:30:02.81#ibcon#about to read 5, iclass 25, count 0 2006.286.04:30:02.81#ibcon#read 5, iclass 25, count 0 2006.286.04:30:02.81#ibcon#about to read 6, iclass 25, count 0 2006.286.04:30:02.81#ibcon#read 6, iclass 25, count 0 2006.286.04:30:02.81#ibcon#end of sib2, iclass 25, count 0 2006.286.04:30:02.81#ibcon#*after write, iclass 25, count 0 2006.286.04:30:02.81#ibcon#*before return 0, iclass 25, count 0 2006.286.04:30:02.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:30:02.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:30:02.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:30:02.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:30:02.81$vck44/vbbw=wide 2006.286.04:30:02.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.04:30:02.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.04:30:02.81#ibcon#ireg 8 cls_cnt 0 2006.286.04:30:02.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:30:02.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:30:02.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:30:02.81#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:30:02.81#ibcon#first serial, iclass 27, count 0 2006.286.04:30:02.81#ibcon#enter sib2, iclass 27, count 0 2006.286.04:30:02.81#ibcon#flushed, iclass 27, count 0 2006.286.04:30:02.81#ibcon#about to write, iclass 27, count 0 2006.286.04:30:02.81#ibcon#wrote, iclass 27, count 0 2006.286.04:30:02.82#ibcon#about to read 3, iclass 27, count 0 2006.286.04:30:02.83#ibcon#read 3, iclass 27, count 0 2006.286.04:30:02.83#ibcon#about to read 4, iclass 27, count 0 2006.286.04:30:02.83#ibcon#read 4, iclass 27, count 0 2006.286.04:30:02.83#ibcon#about to read 5, iclass 27, count 0 2006.286.04:30:02.83#ibcon#read 5, iclass 27, count 0 2006.286.04:30:02.83#ibcon#about to read 6, iclass 27, count 0 2006.286.04:30:02.83#ibcon#read 6, iclass 27, count 0 2006.286.04:30:02.83#ibcon#end of sib2, iclass 27, count 0 2006.286.04:30:02.83#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:30:02.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:30:02.83#ibcon#[27=BW32\r\n] 2006.286.04:30:02.83#ibcon#*before write, iclass 27, count 0 2006.286.04:30:02.83#ibcon#enter sib2, iclass 27, count 0 2006.286.04:30:02.83#ibcon#flushed, iclass 27, count 0 2006.286.04:30:02.83#ibcon#about to write, iclass 27, count 0 2006.286.04:30:02.83#ibcon#wrote, iclass 27, count 0 2006.286.04:30:02.83#ibcon#about to read 3, iclass 27, count 0 2006.286.04:30:02.86#ibcon#read 3, iclass 27, count 0 2006.286.04:30:02.86#ibcon#about to read 4, iclass 27, count 0 2006.286.04:30:02.86#ibcon#read 4, iclass 27, count 0 2006.286.04:30:02.86#ibcon#about to read 5, iclass 27, count 0 2006.286.04:30:02.86#ibcon#read 5, iclass 27, count 0 2006.286.04:30:02.86#ibcon#about to read 6, iclass 27, count 0 2006.286.04:30:02.86#ibcon#read 6, iclass 27, count 0 2006.286.04:30:02.86#ibcon#end of sib2, iclass 27, count 0 2006.286.04:30:02.86#ibcon#*after write, iclass 27, count 0 2006.286.04:30:02.86#ibcon#*before return 0, iclass 27, count 0 2006.286.04:30:02.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:30:02.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:30:02.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:30:02.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:30:02.86$setupk4/ifdk4 2006.286.04:30:02.86$ifdk4/lo= 2006.286.04:30:02.87$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:30:02.87$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:30:02.87$ifdk4/patch= 2006.286.04:30:02.87$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:30:02.87$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:30:02.87$setupk4/!*+20s 2006.286.04:30:07.14#trakl#Source acquired 2006.286.04:30:09.14#flagr#flagr/antenna,acquired 2006.286.04:30:11.59#abcon#<5=/05 4.2 7.7 22.16 751014.7\r\n> 2006.286.04:30:11.61#abcon#{5=INTERFACE CLEAR} 2006.286.04:30:11.67#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:30:16.29$setupk4/"tpicd 2006.286.04:30:16.29$setupk4/echo=off 2006.286.04:30:16.29$setupk4/xlog=off 2006.286.04:30:16.29:!2006.286.04:33:52 2006.286.04:33:52.00:preob 2006.286.04:33:52.14/onsource/TRACKING 2006.286.04:33:52.14:!2006.286.04:34:02 2006.286.04:34:02.00:"tape 2006.286.04:34:02.00:"st=record 2006.286.04:34:02.00:data_valid=on 2006.286.04:34:02.00:midob 2006.286.04:34:03.14/onsource/TRACKING 2006.286.04:34:03.14/wx/22.18,1014.8,74 2006.286.04:34:03.19/cable/+6.4948E-03 2006.286.04:34:04.28/va/01,07,usb,yes,33,36 2006.286.04:34:04.28/va/02,06,usb,yes,33,33 2006.286.04:34:04.28/va/03,07,usb,yes,32,34 2006.286.04:34:04.28/va/04,06,usb,yes,34,35 2006.286.04:34:04.28/va/05,03,usb,yes,33,34 2006.286.04:34:04.28/va/06,04,usb,yes,30,30 2006.286.04:34:04.28/va/07,04,usb,yes,31,31 2006.286.04:34:04.28/va/08,03,usb,yes,31,38 2006.286.04:34:04.51/valo/01,524.99,yes,locked 2006.286.04:34:04.51/valo/02,534.99,yes,locked 2006.286.04:34:04.51/valo/03,564.99,yes,locked 2006.286.04:34:04.51/valo/04,624.99,yes,locked 2006.286.04:34:04.51/valo/05,734.99,yes,locked 2006.286.04:34:04.51/valo/06,814.99,yes,locked 2006.286.04:34:04.51/valo/07,864.99,yes,locked 2006.286.04:34:04.51/valo/08,884.99,yes,locked 2006.286.04:34:05.60/vb/01,04,usb,yes,31,28 2006.286.04:34:05.60/vb/02,05,usb,yes,29,29 2006.286.04:34:05.60/vb/03,04,usb,yes,30,33 2006.286.04:34:05.60/vb/04,05,usb,yes,30,29 2006.286.04:34:05.60/vb/05,04,usb,yes,27,29 2006.286.04:34:05.60/vb/06,03,usb,yes,38,34 2006.286.04:34:05.60/vb/07,04,usb,yes,31,31 2006.286.04:34:05.60/vb/08,04,usb,yes,28,32 2006.286.04:34:05.83/vblo/01,629.99,yes,locked 2006.286.04:34:05.83/vblo/02,634.99,yes,locked 2006.286.04:34:05.83/vblo/03,649.99,yes,locked 2006.286.04:34:05.83/vblo/04,679.99,yes,locked 2006.286.04:34:05.83/vblo/05,709.99,yes,locked 2006.286.04:34:05.83/vblo/06,719.99,yes,locked 2006.286.04:34:05.83/vblo/07,734.99,yes,locked 2006.286.04:34:05.83/vblo/08,744.99,yes,locked 2006.286.04:34:05.98/vabw/8 2006.286.04:34:06.13/vbbw/8 2006.286.04:34:06.34/xfe/off,on,12.2 2006.286.04:34:06.74/ifatt/23,28,28,28 2006.286.04:34:07.07/fmout-gps/S +2.66E-07 2006.286.04:34:07.09:!2006.286.04:38:42 2006.286.04:38:42.01:data_valid=off 2006.286.04:38:42.01:"et 2006.286.04:38:42.01:!+3s 2006.286.04:38:45.02:"tape 2006.286.04:38:45.02:postob 2006.286.04:38:45.12/cable/+6.4954E-03 2006.286.04:38:45.12/wx/22.18,1014.8,76 2006.286.04:38:45.18/fmout-gps/S +2.58E-07 2006.286.04:38:45.18:scan_name=286-0442,jd0610,40 2006.286.04:38:45.18:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.286.04:38:47.14#flagr#flagr/antenna,new-source 2006.286.04:38:47.14:checkk5 2006.286.04:38:47.57/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:38:48.04/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:38:48.47/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:38:48.91/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:38:49.34/chk_obsdata//k5ts1/T2860434??a.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.286.04:38:49.73/chk_obsdata//k5ts2/T2860434??b.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.286.04:38:50.30/chk_obsdata//k5ts3/T2860434??c.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.286.04:38:50.64/chk_obsdata//k5ts4/T2860434??d.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.286.04:38:51.76/k5log//k5ts1_log_newline 2006.286.04:38:52.82/k5log//k5ts2_log_newline 2006.286.04:38:53.59/k5log//k5ts3_log_newline 2006.286.04:38:54.56/k5log//k5ts4_log_newline 2006.286.04:38:54.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:38:54.58:setupk4=1 2006.286.04:38:54.58$setupk4/echo=on 2006.286.04:38:54.58$setupk4/pcalon 2006.286.04:38:54.58$pcalon/"no phase cal control is implemented here 2006.286.04:38:54.58$setupk4/"tpicd=stop 2006.286.04:38:54.58$setupk4/"rec=synch_on 2006.286.04:38:54.58$setupk4/"rec_mode=128 2006.286.04:38:54.58$setupk4/!* 2006.286.04:38:54.58$setupk4/recpk4 2006.286.04:38:54.58$recpk4/recpatch= 2006.286.04:38:54.59$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:38:54.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:38:54.59$setupk4/vck44 2006.286.04:38:54.59$vck44/valo=1,524.99 2006.286.04:38:54.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.04:38:54.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.04:38:54.59#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:54.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:38:54.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:38:54.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:38:54.59#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:38:54.59#ibcon#first serial, iclass 24, count 0 2006.286.04:38:54.59#ibcon#enter sib2, iclass 24, count 0 2006.286.04:38:54.59#ibcon#flushed, iclass 24, count 0 2006.286.04:38:54.59#ibcon#about to write, iclass 24, count 0 2006.286.04:38:54.59#ibcon#wrote, iclass 24, count 0 2006.286.04:38:54.59#ibcon#about to read 3, iclass 24, count 0 2006.286.04:38:54.60#ibcon#read 3, iclass 24, count 0 2006.286.04:38:54.60#ibcon#about to read 4, iclass 24, count 0 2006.286.04:38:54.60#ibcon#read 4, iclass 24, count 0 2006.286.04:38:54.60#ibcon#about to read 5, iclass 24, count 0 2006.286.04:38:54.60#ibcon#read 5, iclass 24, count 0 2006.286.04:38:54.60#ibcon#about to read 6, iclass 24, count 0 2006.286.04:38:54.60#ibcon#read 6, iclass 24, count 0 2006.286.04:38:54.60#ibcon#end of sib2, iclass 24, count 0 2006.286.04:38:54.60#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:38:54.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:38:54.60#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:38:54.60#ibcon#*before write, iclass 24, count 0 2006.286.04:38:54.60#ibcon#enter sib2, iclass 24, count 0 2006.286.04:38:54.60#ibcon#flushed, iclass 24, count 0 2006.286.04:38:54.60#ibcon#about to write, iclass 24, count 0 2006.286.04:38:54.60#ibcon#wrote, iclass 24, count 0 2006.286.04:38:54.60#ibcon#about to read 3, iclass 24, count 0 2006.286.04:38:54.65#ibcon#read 3, iclass 24, count 0 2006.286.04:38:54.65#ibcon#about to read 4, iclass 24, count 0 2006.286.04:38:54.65#ibcon#read 4, iclass 24, count 0 2006.286.04:38:54.65#ibcon#about to read 5, iclass 24, count 0 2006.286.04:38:54.65#ibcon#read 5, iclass 24, count 0 2006.286.04:38:54.65#ibcon#about to read 6, iclass 24, count 0 2006.286.04:38:54.65#ibcon#read 6, iclass 24, count 0 2006.286.04:38:54.65#ibcon#end of sib2, iclass 24, count 0 2006.286.04:38:54.65#ibcon#*after write, iclass 24, count 0 2006.286.04:38:54.65#ibcon#*before return 0, iclass 24, count 0 2006.286.04:38:54.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:38:54.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:38:54.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:38:54.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:38:54.65$vck44/va=1,7 2006.286.04:38:54.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.04:38:54.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.04:38:54.65#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:54.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:38:54.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:38:54.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:38:54.65#ibcon#enter wrdev, iclass 26, count 2 2006.286.04:38:54.65#ibcon#first serial, iclass 26, count 2 2006.286.04:38:54.65#ibcon#enter sib2, iclass 26, count 2 2006.286.04:38:54.65#ibcon#flushed, iclass 26, count 2 2006.286.04:38:54.65#ibcon#about to write, iclass 26, count 2 2006.286.04:38:54.65#ibcon#wrote, iclass 26, count 2 2006.286.04:38:54.65#ibcon#about to read 3, iclass 26, count 2 2006.286.04:38:54.67#ibcon#read 3, iclass 26, count 2 2006.286.04:38:54.67#ibcon#about to read 4, iclass 26, count 2 2006.286.04:38:54.67#ibcon#read 4, iclass 26, count 2 2006.286.04:38:54.67#ibcon#about to read 5, iclass 26, count 2 2006.286.04:38:54.67#ibcon#read 5, iclass 26, count 2 2006.286.04:38:54.67#ibcon#about to read 6, iclass 26, count 2 2006.286.04:38:54.67#ibcon#read 6, iclass 26, count 2 2006.286.04:38:54.67#ibcon#end of sib2, iclass 26, count 2 2006.286.04:38:54.67#ibcon#*mode == 0, iclass 26, count 2 2006.286.04:38:54.67#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.04:38:54.67#ibcon#[25=AT01-07\r\n] 2006.286.04:38:54.67#ibcon#*before write, iclass 26, count 2 2006.286.04:38:54.67#ibcon#enter sib2, iclass 26, count 2 2006.286.04:38:54.67#ibcon#flushed, iclass 26, count 2 2006.286.04:38:54.67#ibcon#about to write, iclass 26, count 2 2006.286.04:38:54.67#ibcon#wrote, iclass 26, count 2 2006.286.04:38:54.67#ibcon#about to read 3, iclass 26, count 2 2006.286.04:38:54.70#ibcon#read 3, iclass 26, count 2 2006.286.04:38:54.70#ibcon#about to read 4, iclass 26, count 2 2006.286.04:38:54.70#ibcon#read 4, iclass 26, count 2 2006.286.04:38:54.70#ibcon#about to read 5, iclass 26, count 2 2006.286.04:38:54.70#ibcon#read 5, iclass 26, count 2 2006.286.04:38:54.70#ibcon#about to read 6, iclass 26, count 2 2006.286.04:38:54.70#ibcon#read 6, iclass 26, count 2 2006.286.04:38:54.70#ibcon#end of sib2, iclass 26, count 2 2006.286.04:38:54.70#ibcon#*after write, iclass 26, count 2 2006.286.04:38:54.70#ibcon#*before return 0, iclass 26, count 2 2006.286.04:38:54.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:38:54.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:38:54.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.04:38:54.70#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:54.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:38:54.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:38:54.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:38:54.82#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:38:54.82#ibcon#first serial, iclass 26, count 0 2006.286.04:38:54.82#ibcon#enter sib2, iclass 26, count 0 2006.286.04:38:54.82#ibcon#flushed, iclass 26, count 0 2006.286.04:38:54.82#ibcon#about to write, iclass 26, count 0 2006.286.04:38:54.82#ibcon#wrote, iclass 26, count 0 2006.286.04:38:54.82#ibcon#about to read 3, iclass 26, count 0 2006.286.04:38:54.84#ibcon#read 3, iclass 26, count 0 2006.286.04:38:54.84#ibcon#about to read 4, iclass 26, count 0 2006.286.04:38:54.84#ibcon#read 4, iclass 26, count 0 2006.286.04:38:54.84#ibcon#about to read 5, iclass 26, count 0 2006.286.04:38:54.84#ibcon#read 5, iclass 26, count 0 2006.286.04:38:54.84#ibcon#about to read 6, iclass 26, count 0 2006.286.04:38:54.84#ibcon#read 6, iclass 26, count 0 2006.286.04:38:54.84#ibcon#end of sib2, iclass 26, count 0 2006.286.04:38:54.84#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:38:54.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:38:54.84#ibcon#[25=USB\r\n] 2006.286.04:38:54.84#ibcon#*before write, iclass 26, count 0 2006.286.04:38:54.84#ibcon#enter sib2, iclass 26, count 0 2006.286.04:38:54.84#ibcon#flushed, iclass 26, count 0 2006.286.04:38:54.84#ibcon#about to write, iclass 26, count 0 2006.286.04:38:54.84#ibcon#wrote, iclass 26, count 0 2006.286.04:38:54.84#ibcon#about to read 3, iclass 26, count 0 2006.286.04:38:54.87#ibcon#read 3, iclass 26, count 0 2006.286.04:38:54.87#ibcon#about to read 4, iclass 26, count 0 2006.286.04:38:54.87#ibcon#read 4, iclass 26, count 0 2006.286.04:38:54.87#ibcon#about to read 5, iclass 26, count 0 2006.286.04:38:54.87#ibcon#read 5, iclass 26, count 0 2006.286.04:38:54.87#ibcon#about to read 6, iclass 26, count 0 2006.286.04:38:54.87#ibcon#read 6, iclass 26, count 0 2006.286.04:38:54.87#ibcon#end of sib2, iclass 26, count 0 2006.286.04:38:54.87#ibcon#*after write, iclass 26, count 0 2006.286.04:38:54.87#ibcon#*before return 0, iclass 26, count 0 2006.286.04:38:54.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:38:54.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:38:54.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:38:54.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:38:54.87$vck44/valo=2,534.99 2006.286.04:38:54.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.04:38:54.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.04:38:54.87#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:54.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:38:54.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:38:54.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:38:54.87#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:38:54.87#ibcon#first serial, iclass 28, count 0 2006.286.04:38:54.87#ibcon#enter sib2, iclass 28, count 0 2006.286.04:38:54.87#ibcon#flushed, iclass 28, count 0 2006.286.04:38:54.87#ibcon#about to write, iclass 28, count 0 2006.286.04:38:54.87#ibcon#wrote, iclass 28, count 0 2006.286.04:38:54.87#ibcon#about to read 3, iclass 28, count 0 2006.286.04:38:54.89#ibcon#read 3, iclass 28, count 0 2006.286.04:38:54.89#ibcon#about to read 4, iclass 28, count 0 2006.286.04:38:54.89#ibcon#read 4, iclass 28, count 0 2006.286.04:38:54.89#ibcon#about to read 5, iclass 28, count 0 2006.286.04:38:54.89#ibcon#read 5, iclass 28, count 0 2006.286.04:38:54.89#ibcon#about to read 6, iclass 28, count 0 2006.286.04:38:54.89#ibcon#read 6, iclass 28, count 0 2006.286.04:38:54.89#ibcon#end of sib2, iclass 28, count 0 2006.286.04:38:54.89#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:38:54.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:38:54.89#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:38:54.89#ibcon#*before write, iclass 28, count 0 2006.286.04:38:54.89#ibcon#enter sib2, iclass 28, count 0 2006.286.04:38:54.89#ibcon#flushed, iclass 28, count 0 2006.286.04:38:54.89#ibcon#about to write, iclass 28, count 0 2006.286.04:38:54.89#ibcon#wrote, iclass 28, count 0 2006.286.04:38:54.89#ibcon#about to read 3, iclass 28, count 0 2006.286.04:38:54.93#ibcon#read 3, iclass 28, count 0 2006.286.04:38:54.93#ibcon#about to read 4, iclass 28, count 0 2006.286.04:38:54.93#ibcon#read 4, iclass 28, count 0 2006.286.04:38:54.93#ibcon#about to read 5, iclass 28, count 0 2006.286.04:38:54.93#ibcon#read 5, iclass 28, count 0 2006.286.04:38:54.93#ibcon#about to read 6, iclass 28, count 0 2006.286.04:38:54.93#ibcon#read 6, iclass 28, count 0 2006.286.04:38:54.93#ibcon#end of sib2, iclass 28, count 0 2006.286.04:38:54.93#ibcon#*after write, iclass 28, count 0 2006.286.04:38:54.93#ibcon#*before return 0, iclass 28, count 0 2006.286.04:38:54.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:38:54.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:38:54.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:38:54.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:38:54.93$vck44/va=2,6 2006.286.04:38:54.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.04:38:54.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.04:38:54.93#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:54.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:38:54.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:38:54.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:38:54.99#ibcon#enter wrdev, iclass 30, count 2 2006.286.04:38:54.99#ibcon#first serial, iclass 30, count 2 2006.286.04:38:54.99#ibcon#enter sib2, iclass 30, count 2 2006.286.04:38:54.99#ibcon#flushed, iclass 30, count 2 2006.286.04:38:54.99#ibcon#about to write, iclass 30, count 2 2006.286.04:38:54.99#ibcon#wrote, iclass 30, count 2 2006.286.04:38:54.99#ibcon#about to read 3, iclass 30, count 2 2006.286.04:38:55.01#ibcon#read 3, iclass 30, count 2 2006.286.04:38:55.01#ibcon#about to read 4, iclass 30, count 2 2006.286.04:38:55.01#ibcon#read 4, iclass 30, count 2 2006.286.04:38:55.01#ibcon#about to read 5, iclass 30, count 2 2006.286.04:38:55.01#ibcon#read 5, iclass 30, count 2 2006.286.04:38:55.01#ibcon#about to read 6, iclass 30, count 2 2006.286.04:38:55.01#ibcon#read 6, iclass 30, count 2 2006.286.04:38:55.01#ibcon#end of sib2, iclass 30, count 2 2006.286.04:38:55.01#ibcon#*mode == 0, iclass 30, count 2 2006.286.04:38:55.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.04:38:55.01#ibcon#[25=AT02-06\r\n] 2006.286.04:38:55.01#ibcon#*before write, iclass 30, count 2 2006.286.04:38:55.01#ibcon#enter sib2, iclass 30, count 2 2006.286.04:38:55.01#ibcon#flushed, iclass 30, count 2 2006.286.04:38:55.01#ibcon#about to write, iclass 30, count 2 2006.286.04:38:55.01#ibcon#wrote, iclass 30, count 2 2006.286.04:38:55.01#ibcon#about to read 3, iclass 30, count 2 2006.286.04:38:55.04#ibcon#read 3, iclass 30, count 2 2006.286.04:38:55.37#ibcon#about to read 4, iclass 30, count 2 2006.286.04:38:55.37#ibcon#read 4, iclass 30, count 2 2006.286.04:38:55.37#ibcon#about to read 5, iclass 30, count 2 2006.286.04:38:55.37#ibcon#read 5, iclass 30, count 2 2006.286.04:38:55.37#ibcon#about to read 6, iclass 30, count 2 2006.286.04:38:55.37#ibcon#read 6, iclass 30, count 2 2006.286.04:38:55.37#ibcon#end of sib2, iclass 30, count 2 2006.286.04:38:55.37#ibcon#*after write, iclass 30, count 2 2006.286.04:38:55.37#ibcon#*before return 0, iclass 30, count 2 2006.286.04:38:55.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:38:55.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:38:55.37#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.04:38:55.37#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:55.37#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:38:55.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:38:55.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:38:55.48#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:38:55.48#ibcon#first serial, iclass 30, count 0 2006.286.04:38:55.48#ibcon#enter sib2, iclass 30, count 0 2006.286.04:38:55.48#ibcon#flushed, iclass 30, count 0 2006.286.04:38:55.48#ibcon#about to write, iclass 30, count 0 2006.286.04:38:55.48#ibcon#wrote, iclass 30, count 0 2006.286.04:38:55.48#ibcon#about to read 3, iclass 30, count 0 2006.286.04:38:55.50#ibcon#read 3, iclass 30, count 0 2006.286.04:38:55.50#ibcon#about to read 4, iclass 30, count 0 2006.286.04:38:55.50#ibcon#read 4, iclass 30, count 0 2006.286.04:38:55.50#ibcon#about to read 5, iclass 30, count 0 2006.286.04:38:55.50#ibcon#read 5, iclass 30, count 0 2006.286.04:38:55.50#ibcon#about to read 6, iclass 30, count 0 2006.286.04:38:55.50#ibcon#read 6, iclass 30, count 0 2006.286.04:38:55.50#ibcon#end of sib2, iclass 30, count 0 2006.286.04:38:55.50#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:38:55.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:38:55.50#ibcon#[25=USB\r\n] 2006.286.04:38:55.50#ibcon#*before write, iclass 30, count 0 2006.286.04:38:55.50#ibcon#enter sib2, iclass 30, count 0 2006.286.04:38:55.50#ibcon#flushed, iclass 30, count 0 2006.286.04:38:55.50#ibcon#about to write, iclass 30, count 0 2006.286.04:38:55.50#ibcon#wrote, iclass 30, count 0 2006.286.04:38:55.50#ibcon#about to read 3, iclass 30, count 0 2006.286.04:38:55.53#ibcon#read 3, iclass 30, count 0 2006.286.04:38:55.53#ibcon#about to read 4, iclass 30, count 0 2006.286.04:38:55.53#ibcon#read 4, iclass 30, count 0 2006.286.04:38:55.53#ibcon#about to read 5, iclass 30, count 0 2006.286.04:38:55.53#ibcon#read 5, iclass 30, count 0 2006.286.04:38:55.53#ibcon#about to read 6, iclass 30, count 0 2006.286.04:38:55.53#ibcon#read 6, iclass 30, count 0 2006.286.04:38:55.53#ibcon#end of sib2, iclass 30, count 0 2006.286.04:38:55.53#ibcon#*after write, iclass 30, count 0 2006.286.04:38:55.53#ibcon#*before return 0, iclass 30, count 0 2006.286.04:38:55.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:38:55.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:38:55.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:38:55.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:38:55.53$vck44/valo=3,564.99 2006.286.04:38:55.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.04:38:55.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.04:38:55.53#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:55.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:38:55.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:38:55.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:38:55.53#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:38:55.53#ibcon#first serial, iclass 32, count 0 2006.286.04:38:55.53#ibcon#enter sib2, iclass 32, count 0 2006.286.04:38:55.53#ibcon#flushed, iclass 32, count 0 2006.286.04:38:55.53#ibcon#about to write, iclass 32, count 0 2006.286.04:38:55.53#ibcon#wrote, iclass 32, count 0 2006.286.04:38:55.53#ibcon#about to read 3, iclass 32, count 0 2006.286.04:38:55.55#ibcon#read 3, iclass 32, count 0 2006.286.04:38:55.55#ibcon#about to read 4, iclass 32, count 0 2006.286.04:38:55.55#ibcon#read 4, iclass 32, count 0 2006.286.04:38:55.55#ibcon#about to read 5, iclass 32, count 0 2006.286.04:38:55.55#ibcon#read 5, iclass 32, count 0 2006.286.04:38:55.55#ibcon#about to read 6, iclass 32, count 0 2006.286.04:38:55.55#ibcon#read 6, iclass 32, count 0 2006.286.04:38:55.55#ibcon#end of sib2, iclass 32, count 0 2006.286.04:38:55.55#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:38:55.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:38:55.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:38:55.55#ibcon#*before write, iclass 32, count 0 2006.286.04:38:55.55#ibcon#enter sib2, iclass 32, count 0 2006.286.04:38:55.55#ibcon#flushed, iclass 32, count 0 2006.286.04:38:55.55#ibcon#about to write, iclass 32, count 0 2006.286.04:38:55.55#ibcon#wrote, iclass 32, count 0 2006.286.04:38:55.55#ibcon#about to read 3, iclass 32, count 0 2006.286.04:38:55.59#ibcon#read 3, iclass 32, count 0 2006.286.04:38:55.59#ibcon#about to read 4, iclass 32, count 0 2006.286.04:38:55.59#ibcon#read 4, iclass 32, count 0 2006.286.04:38:55.59#ibcon#about to read 5, iclass 32, count 0 2006.286.04:38:55.59#ibcon#read 5, iclass 32, count 0 2006.286.04:38:55.59#ibcon#about to read 6, iclass 32, count 0 2006.286.04:38:55.59#ibcon#read 6, iclass 32, count 0 2006.286.04:38:55.59#ibcon#end of sib2, iclass 32, count 0 2006.286.04:38:55.59#ibcon#*after write, iclass 32, count 0 2006.286.04:38:55.59#ibcon#*before return 0, iclass 32, count 0 2006.286.04:38:55.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:38:55.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:38:55.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:38:55.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:38:55.59$vck44/va=3,7 2006.286.04:38:55.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.04:38:55.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.04:38:55.59#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:55.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:38:55.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:38:55.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:38:55.65#ibcon#enter wrdev, iclass 34, count 2 2006.286.04:38:55.65#ibcon#first serial, iclass 34, count 2 2006.286.04:38:55.65#ibcon#enter sib2, iclass 34, count 2 2006.286.04:38:55.65#ibcon#flushed, iclass 34, count 2 2006.286.04:38:55.65#ibcon#about to write, iclass 34, count 2 2006.286.04:38:55.65#ibcon#wrote, iclass 34, count 2 2006.286.04:38:55.65#ibcon#about to read 3, iclass 34, count 2 2006.286.04:38:55.67#ibcon#read 3, iclass 34, count 2 2006.286.04:38:55.67#ibcon#about to read 4, iclass 34, count 2 2006.286.04:38:55.67#ibcon#read 4, iclass 34, count 2 2006.286.04:38:55.67#ibcon#about to read 5, iclass 34, count 2 2006.286.04:38:55.67#ibcon#read 5, iclass 34, count 2 2006.286.04:38:55.67#ibcon#about to read 6, iclass 34, count 2 2006.286.04:38:55.67#ibcon#read 6, iclass 34, count 2 2006.286.04:38:55.67#ibcon#end of sib2, iclass 34, count 2 2006.286.04:38:55.67#ibcon#*mode == 0, iclass 34, count 2 2006.286.04:38:55.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.04:38:55.67#ibcon#[25=AT03-07\r\n] 2006.286.04:38:55.67#ibcon#*before write, iclass 34, count 2 2006.286.04:38:55.67#ibcon#enter sib2, iclass 34, count 2 2006.286.04:38:55.67#ibcon#flushed, iclass 34, count 2 2006.286.04:38:55.67#ibcon#about to write, iclass 34, count 2 2006.286.04:38:55.67#ibcon#wrote, iclass 34, count 2 2006.286.04:38:55.67#ibcon#about to read 3, iclass 34, count 2 2006.286.04:38:55.70#ibcon#read 3, iclass 34, count 2 2006.286.04:38:55.81#ibcon#about to read 4, iclass 34, count 2 2006.286.04:38:55.81#ibcon#read 4, iclass 34, count 2 2006.286.04:38:55.81#ibcon#about to read 5, iclass 34, count 2 2006.286.04:38:55.81#ibcon#read 5, iclass 34, count 2 2006.286.04:38:55.81#ibcon#about to read 6, iclass 34, count 2 2006.286.04:38:55.81#ibcon#read 6, iclass 34, count 2 2006.286.04:38:55.81#ibcon#end of sib2, iclass 34, count 2 2006.286.04:38:55.81#ibcon#*after write, iclass 34, count 2 2006.286.04:38:55.81#ibcon#*before return 0, iclass 34, count 2 2006.286.04:38:55.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:38:55.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:38:55.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.04:38:55.81#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:55.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:38:55.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:38:55.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:38:55.92#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:38:55.92#ibcon#first serial, iclass 34, count 0 2006.286.04:38:55.92#ibcon#enter sib2, iclass 34, count 0 2006.286.04:38:55.92#ibcon#flushed, iclass 34, count 0 2006.286.04:38:55.92#ibcon#about to write, iclass 34, count 0 2006.286.04:38:55.92#ibcon#wrote, iclass 34, count 0 2006.286.04:38:55.92#ibcon#about to read 3, iclass 34, count 0 2006.286.04:38:55.94#ibcon#read 3, iclass 34, count 0 2006.286.04:38:55.94#ibcon#about to read 4, iclass 34, count 0 2006.286.04:38:55.94#ibcon#read 4, iclass 34, count 0 2006.286.04:38:55.94#ibcon#about to read 5, iclass 34, count 0 2006.286.04:38:55.94#ibcon#read 5, iclass 34, count 0 2006.286.04:38:55.94#ibcon#about to read 6, iclass 34, count 0 2006.286.04:38:55.94#ibcon#read 6, iclass 34, count 0 2006.286.04:38:55.94#ibcon#end of sib2, iclass 34, count 0 2006.286.04:38:55.94#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:38:55.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:38:55.94#ibcon#[25=USB\r\n] 2006.286.04:38:55.94#ibcon#*before write, iclass 34, count 0 2006.286.04:38:55.94#ibcon#enter sib2, iclass 34, count 0 2006.286.04:38:55.94#ibcon#flushed, iclass 34, count 0 2006.286.04:38:55.94#ibcon#about to write, iclass 34, count 0 2006.286.04:38:55.94#ibcon#wrote, iclass 34, count 0 2006.286.04:38:55.94#ibcon#about to read 3, iclass 34, count 0 2006.286.04:38:55.97#ibcon#read 3, iclass 34, count 0 2006.286.04:38:55.97#ibcon#about to read 4, iclass 34, count 0 2006.286.04:38:55.97#ibcon#read 4, iclass 34, count 0 2006.286.04:38:55.97#ibcon#about to read 5, iclass 34, count 0 2006.286.04:38:55.97#ibcon#read 5, iclass 34, count 0 2006.286.04:38:55.97#ibcon#about to read 6, iclass 34, count 0 2006.286.04:38:55.97#ibcon#read 6, iclass 34, count 0 2006.286.04:38:55.97#ibcon#end of sib2, iclass 34, count 0 2006.286.04:38:55.97#ibcon#*after write, iclass 34, count 0 2006.286.04:38:55.97#ibcon#*before return 0, iclass 34, count 0 2006.286.04:38:55.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:38:55.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:38:55.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:38:55.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:38:55.97$vck44/valo=4,624.99 2006.286.04:38:55.97#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.04:38:55.97#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.04:38:55.97#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:55.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:38:55.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:38:55.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:38:55.97#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:38:55.97#ibcon#first serial, iclass 36, count 0 2006.286.04:38:55.97#ibcon#enter sib2, iclass 36, count 0 2006.286.04:38:55.97#ibcon#flushed, iclass 36, count 0 2006.286.04:38:55.97#ibcon#about to write, iclass 36, count 0 2006.286.04:38:55.97#ibcon#wrote, iclass 36, count 0 2006.286.04:38:55.97#ibcon#about to read 3, iclass 36, count 0 2006.286.04:38:55.99#ibcon#read 3, iclass 36, count 0 2006.286.04:38:55.99#ibcon#about to read 4, iclass 36, count 0 2006.286.04:38:55.99#ibcon#read 4, iclass 36, count 0 2006.286.04:38:55.99#ibcon#about to read 5, iclass 36, count 0 2006.286.04:38:55.99#ibcon#read 5, iclass 36, count 0 2006.286.04:38:55.99#ibcon#about to read 6, iclass 36, count 0 2006.286.04:38:55.99#ibcon#read 6, iclass 36, count 0 2006.286.04:38:55.99#ibcon#end of sib2, iclass 36, count 0 2006.286.04:38:55.99#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:38:55.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:38:55.99#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:38:55.99#ibcon#*before write, iclass 36, count 0 2006.286.04:38:55.99#ibcon#enter sib2, iclass 36, count 0 2006.286.04:38:55.99#ibcon#flushed, iclass 36, count 0 2006.286.04:38:55.99#ibcon#about to write, iclass 36, count 0 2006.286.04:38:55.99#ibcon#wrote, iclass 36, count 0 2006.286.04:38:55.99#ibcon#about to read 3, iclass 36, count 0 2006.286.04:38:56.03#ibcon#read 3, iclass 36, count 0 2006.286.04:38:56.03#ibcon#about to read 4, iclass 36, count 0 2006.286.04:38:56.03#ibcon#read 4, iclass 36, count 0 2006.286.04:38:56.03#ibcon#about to read 5, iclass 36, count 0 2006.286.04:38:56.03#ibcon#read 5, iclass 36, count 0 2006.286.04:38:56.03#ibcon#about to read 6, iclass 36, count 0 2006.286.04:38:56.03#ibcon#read 6, iclass 36, count 0 2006.286.04:38:56.03#ibcon#end of sib2, iclass 36, count 0 2006.286.04:38:56.03#ibcon#*after write, iclass 36, count 0 2006.286.04:38:56.03#ibcon#*before return 0, iclass 36, count 0 2006.286.04:38:56.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:38:56.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:38:56.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:38:56.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:38:56.03$vck44/va=4,6 2006.286.04:38:56.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.04:38:56.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.04:38:56.32#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:56.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:38:56.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:38:56.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:38:56.32#ibcon#enter wrdev, iclass 38, count 2 2006.286.04:38:56.32#ibcon#first serial, iclass 38, count 2 2006.286.04:38:56.32#ibcon#enter sib2, iclass 38, count 2 2006.286.04:38:56.32#ibcon#flushed, iclass 38, count 2 2006.286.04:38:56.32#ibcon#about to write, iclass 38, count 2 2006.286.04:38:56.32#ibcon#wrote, iclass 38, count 2 2006.286.04:38:56.32#ibcon#about to read 3, iclass 38, count 2 2006.286.04:38:56.33#ibcon#read 3, iclass 38, count 2 2006.286.04:38:56.33#ibcon#about to read 4, iclass 38, count 2 2006.286.04:38:56.33#ibcon#read 4, iclass 38, count 2 2006.286.04:38:56.33#ibcon#about to read 5, iclass 38, count 2 2006.286.04:38:56.33#ibcon#read 5, iclass 38, count 2 2006.286.04:38:56.33#ibcon#about to read 6, iclass 38, count 2 2006.286.04:38:56.33#ibcon#read 6, iclass 38, count 2 2006.286.04:38:56.33#ibcon#end of sib2, iclass 38, count 2 2006.286.04:38:56.33#ibcon#*mode == 0, iclass 38, count 2 2006.286.04:38:56.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.04:38:56.33#ibcon#[25=AT04-06\r\n] 2006.286.04:38:56.33#ibcon#*before write, iclass 38, count 2 2006.286.04:38:56.33#ibcon#enter sib2, iclass 38, count 2 2006.286.04:38:56.33#ibcon#flushed, iclass 38, count 2 2006.286.04:38:56.33#ibcon#about to write, iclass 38, count 2 2006.286.04:38:56.33#ibcon#wrote, iclass 38, count 2 2006.286.04:38:56.33#ibcon#about to read 3, iclass 38, count 2 2006.286.04:38:56.36#ibcon#read 3, iclass 38, count 2 2006.286.04:38:56.36#ibcon#about to read 4, iclass 38, count 2 2006.286.04:38:56.36#ibcon#read 4, iclass 38, count 2 2006.286.04:38:56.36#ibcon#about to read 5, iclass 38, count 2 2006.286.04:38:56.36#ibcon#read 5, iclass 38, count 2 2006.286.04:38:56.36#ibcon#about to read 6, iclass 38, count 2 2006.286.04:38:56.36#ibcon#read 6, iclass 38, count 2 2006.286.04:38:56.36#ibcon#end of sib2, iclass 38, count 2 2006.286.04:38:56.36#ibcon#*after write, iclass 38, count 2 2006.286.04:38:56.36#ibcon#*before return 0, iclass 38, count 2 2006.286.04:38:56.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:38:56.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:38:56.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.04:38:56.36#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:56.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:38:56.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:38:56.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:38:56.48#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:38:56.48#ibcon#first serial, iclass 38, count 0 2006.286.04:38:56.48#ibcon#enter sib2, iclass 38, count 0 2006.286.04:38:56.48#ibcon#flushed, iclass 38, count 0 2006.286.04:38:56.48#ibcon#about to write, iclass 38, count 0 2006.286.04:38:56.48#ibcon#wrote, iclass 38, count 0 2006.286.04:38:56.48#ibcon#about to read 3, iclass 38, count 0 2006.286.04:38:56.50#ibcon#read 3, iclass 38, count 0 2006.286.04:38:56.50#ibcon#about to read 4, iclass 38, count 0 2006.286.04:38:56.50#ibcon#read 4, iclass 38, count 0 2006.286.04:38:56.50#ibcon#about to read 5, iclass 38, count 0 2006.286.04:38:56.50#ibcon#read 5, iclass 38, count 0 2006.286.04:38:56.50#ibcon#about to read 6, iclass 38, count 0 2006.286.04:38:56.50#ibcon#read 6, iclass 38, count 0 2006.286.04:38:56.50#ibcon#end of sib2, iclass 38, count 0 2006.286.04:38:56.50#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:38:56.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:38:56.50#ibcon#[25=USB\r\n] 2006.286.04:38:56.50#ibcon#*before write, iclass 38, count 0 2006.286.04:38:56.50#ibcon#enter sib2, iclass 38, count 0 2006.286.04:38:56.50#ibcon#flushed, iclass 38, count 0 2006.286.04:38:56.50#ibcon#about to write, iclass 38, count 0 2006.286.04:38:56.50#ibcon#wrote, iclass 38, count 0 2006.286.04:38:56.50#ibcon#about to read 3, iclass 38, count 0 2006.286.04:38:56.53#ibcon#read 3, iclass 38, count 0 2006.286.04:38:56.53#ibcon#about to read 4, iclass 38, count 0 2006.286.04:38:56.53#ibcon#read 4, iclass 38, count 0 2006.286.04:38:56.53#ibcon#about to read 5, iclass 38, count 0 2006.286.04:38:56.53#ibcon#read 5, iclass 38, count 0 2006.286.04:38:56.53#ibcon#about to read 6, iclass 38, count 0 2006.286.04:38:56.53#ibcon#read 6, iclass 38, count 0 2006.286.04:38:56.53#ibcon#end of sib2, iclass 38, count 0 2006.286.04:38:56.53#ibcon#*after write, iclass 38, count 0 2006.286.04:38:56.53#ibcon#*before return 0, iclass 38, count 0 2006.286.04:38:56.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:38:56.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:38:56.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:38:56.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:38:56.53$vck44/valo=5,734.99 2006.286.04:38:56.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.04:38:56.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.04:38:56.53#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:56.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:38:56.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:38:56.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:38:56.53#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:38:56.53#ibcon#first serial, iclass 40, count 0 2006.286.04:38:56.53#ibcon#enter sib2, iclass 40, count 0 2006.286.04:38:56.53#ibcon#flushed, iclass 40, count 0 2006.286.04:38:56.53#ibcon#about to write, iclass 40, count 0 2006.286.04:38:56.53#ibcon#wrote, iclass 40, count 0 2006.286.04:38:56.53#ibcon#about to read 3, iclass 40, count 0 2006.286.04:38:56.55#ibcon#read 3, iclass 40, count 0 2006.286.04:38:56.55#ibcon#about to read 4, iclass 40, count 0 2006.286.04:38:56.55#ibcon#read 4, iclass 40, count 0 2006.286.04:38:56.55#ibcon#about to read 5, iclass 40, count 0 2006.286.04:38:56.55#ibcon#read 5, iclass 40, count 0 2006.286.04:38:56.55#ibcon#about to read 6, iclass 40, count 0 2006.286.04:38:56.55#ibcon#read 6, iclass 40, count 0 2006.286.04:38:56.55#ibcon#end of sib2, iclass 40, count 0 2006.286.04:38:56.55#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:38:56.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:38:56.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:38:56.55#ibcon#*before write, iclass 40, count 0 2006.286.04:38:56.55#ibcon#enter sib2, iclass 40, count 0 2006.286.04:38:56.55#ibcon#flushed, iclass 40, count 0 2006.286.04:38:56.55#ibcon#about to write, iclass 40, count 0 2006.286.04:38:56.55#ibcon#wrote, iclass 40, count 0 2006.286.04:38:56.55#ibcon#about to read 3, iclass 40, count 0 2006.286.04:38:56.59#ibcon#read 3, iclass 40, count 0 2006.286.04:38:56.59#ibcon#about to read 4, iclass 40, count 0 2006.286.04:38:56.59#ibcon#read 4, iclass 40, count 0 2006.286.04:38:56.59#ibcon#about to read 5, iclass 40, count 0 2006.286.04:38:56.59#ibcon#read 5, iclass 40, count 0 2006.286.04:38:56.59#ibcon#about to read 6, iclass 40, count 0 2006.286.04:38:56.59#ibcon#read 6, iclass 40, count 0 2006.286.04:38:56.59#ibcon#end of sib2, iclass 40, count 0 2006.286.04:38:56.59#ibcon#*after write, iclass 40, count 0 2006.286.04:38:56.59#ibcon#*before return 0, iclass 40, count 0 2006.286.04:38:56.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:38:56.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:38:56.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:38:56.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:38:56.59$vck44/va=5,3 2006.286.04:38:56.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.04:38:56.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.04:38:56.59#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:56.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:38:56.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:38:56.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:38:56.65#ibcon#enter wrdev, iclass 4, count 2 2006.286.04:38:56.65#ibcon#first serial, iclass 4, count 2 2006.286.04:38:56.65#ibcon#enter sib2, iclass 4, count 2 2006.286.04:38:56.65#ibcon#flushed, iclass 4, count 2 2006.286.04:38:56.65#ibcon#about to write, iclass 4, count 2 2006.286.04:38:56.65#ibcon#wrote, iclass 4, count 2 2006.286.04:38:56.65#ibcon#about to read 3, iclass 4, count 2 2006.286.04:38:56.67#ibcon#read 3, iclass 4, count 2 2006.286.04:38:56.67#ibcon#about to read 4, iclass 4, count 2 2006.286.04:38:56.67#ibcon#read 4, iclass 4, count 2 2006.286.04:38:56.67#ibcon#about to read 5, iclass 4, count 2 2006.286.04:38:56.67#ibcon#read 5, iclass 4, count 2 2006.286.04:38:56.67#ibcon#about to read 6, iclass 4, count 2 2006.286.04:38:56.67#ibcon#read 6, iclass 4, count 2 2006.286.04:38:56.67#ibcon#end of sib2, iclass 4, count 2 2006.286.04:38:56.67#ibcon#*mode == 0, iclass 4, count 2 2006.286.04:38:56.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.04:38:56.67#ibcon#[25=AT05-03\r\n] 2006.286.04:38:56.67#ibcon#*before write, iclass 4, count 2 2006.286.04:38:56.67#ibcon#enter sib2, iclass 4, count 2 2006.286.04:38:56.67#ibcon#flushed, iclass 4, count 2 2006.286.04:38:56.67#ibcon#about to write, iclass 4, count 2 2006.286.04:38:56.67#ibcon#wrote, iclass 4, count 2 2006.286.04:38:56.67#ibcon#about to read 3, iclass 4, count 2 2006.286.04:38:56.70#ibcon#read 3, iclass 4, count 2 2006.286.04:38:56.70#ibcon#about to read 4, iclass 4, count 2 2006.286.04:38:56.70#ibcon#read 4, iclass 4, count 2 2006.286.04:38:56.70#ibcon#about to read 5, iclass 4, count 2 2006.286.04:38:56.70#ibcon#read 5, iclass 4, count 2 2006.286.04:38:56.70#ibcon#about to read 6, iclass 4, count 2 2006.286.04:38:56.70#ibcon#read 6, iclass 4, count 2 2006.286.04:38:56.70#ibcon#end of sib2, iclass 4, count 2 2006.286.04:38:56.70#ibcon#*after write, iclass 4, count 2 2006.286.04:38:56.70#ibcon#*before return 0, iclass 4, count 2 2006.286.04:38:56.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:38:56.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:38:56.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.04:38:56.70#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:56.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:38:56.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:38:56.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:38:56.82#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:38:56.82#ibcon#first serial, iclass 4, count 0 2006.286.04:38:56.82#ibcon#enter sib2, iclass 4, count 0 2006.286.04:38:56.82#ibcon#flushed, iclass 4, count 0 2006.286.04:38:56.82#ibcon#about to write, iclass 4, count 0 2006.286.04:38:56.82#ibcon#wrote, iclass 4, count 0 2006.286.04:38:56.82#ibcon#about to read 3, iclass 4, count 0 2006.286.04:38:56.84#ibcon#read 3, iclass 4, count 0 2006.286.04:38:56.84#ibcon#about to read 4, iclass 4, count 0 2006.286.04:38:56.84#ibcon#read 4, iclass 4, count 0 2006.286.04:38:56.84#ibcon#about to read 5, iclass 4, count 0 2006.286.04:38:56.84#ibcon#read 5, iclass 4, count 0 2006.286.04:38:56.84#ibcon#about to read 6, iclass 4, count 0 2006.286.04:38:56.84#ibcon#read 6, iclass 4, count 0 2006.286.04:38:56.84#ibcon#end of sib2, iclass 4, count 0 2006.286.04:38:56.84#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:38:56.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:38:56.84#ibcon#[25=USB\r\n] 2006.286.04:38:56.84#ibcon#*before write, iclass 4, count 0 2006.286.04:38:56.84#ibcon#enter sib2, iclass 4, count 0 2006.286.04:38:56.84#ibcon#flushed, iclass 4, count 0 2006.286.04:38:56.84#ibcon#about to write, iclass 4, count 0 2006.286.04:38:56.84#ibcon#wrote, iclass 4, count 0 2006.286.04:38:56.84#ibcon#about to read 3, iclass 4, count 0 2006.286.04:38:56.87#ibcon#read 3, iclass 4, count 0 2006.286.04:38:56.87#ibcon#about to read 4, iclass 4, count 0 2006.286.04:38:56.87#ibcon#read 4, iclass 4, count 0 2006.286.04:38:56.87#ibcon#about to read 5, iclass 4, count 0 2006.286.04:38:56.87#ibcon#read 5, iclass 4, count 0 2006.286.04:38:56.87#ibcon#about to read 6, iclass 4, count 0 2006.286.04:38:56.87#ibcon#read 6, iclass 4, count 0 2006.286.04:38:56.87#ibcon#end of sib2, iclass 4, count 0 2006.286.04:38:56.87#ibcon#*after write, iclass 4, count 0 2006.286.04:38:56.87#ibcon#*before return 0, iclass 4, count 0 2006.286.04:38:56.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:38:56.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:38:56.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:38:56.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:38:56.87$vck44/valo=6,814.99 2006.286.04:38:56.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.04:38:56.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.04:38:56.87#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:56.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:38:56.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:38:56.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:38:56.87#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:38:56.87#ibcon#first serial, iclass 6, count 0 2006.286.04:38:56.87#ibcon#enter sib2, iclass 6, count 0 2006.286.04:38:56.87#ibcon#flushed, iclass 6, count 0 2006.286.04:38:56.87#ibcon#about to write, iclass 6, count 0 2006.286.04:38:56.87#ibcon#wrote, iclass 6, count 0 2006.286.04:38:56.87#ibcon#about to read 3, iclass 6, count 0 2006.286.04:38:56.89#ibcon#read 3, iclass 6, count 0 2006.286.04:38:56.89#ibcon#about to read 4, iclass 6, count 0 2006.286.04:38:56.89#ibcon#read 4, iclass 6, count 0 2006.286.04:38:56.89#ibcon#about to read 5, iclass 6, count 0 2006.286.04:38:56.89#ibcon#read 5, iclass 6, count 0 2006.286.04:38:56.89#ibcon#about to read 6, iclass 6, count 0 2006.286.04:38:56.89#ibcon#read 6, iclass 6, count 0 2006.286.04:38:56.89#ibcon#end of sib2, iclass 6, count 0 2006.286.04:38:56.89#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:38:56.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:38:56.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:38:56.89#ibcon#*before write, iclass 6, count 0 2006.286.04:38:56.89#ibcon#enter sib2, iclass 6, count 0 2006.286.04:38:56.89#ibcon#flushed, iclass 6, count 0 2006.286.04:38:56.89#ibcon#about to write, iclass 6, count 0 2006.286.04:38:56.89#ibcon#wrote, iclass 6, count 0 2006.286.04:38:56.89#ibcon#about to read 3, iclass 6, count 0 2006.286.04:38:56.93#ibcon#read 3, iclass 6, count 0 2006.286.04:38:56.93#ibcon#about to read 4, iclass 6, count 0 2006.286.04:38:56.93#ibcon#read 4, iclass 6, count 0 2006.286.04:38:56.93#ibcon#about to read 5, iclass 6, count 0 2006.286.04:38:56.93#ibcon#read 5, iclass 6, count 0 2006.286.04:38:56.93#ibcon#about to read 6, iclass 6, count 0 2006.286.04:38:56.93#ibcon#read 6, iclass 6, count 0 2006.286.04:38:56.93#ibcon#end of sib2, iclass 6, count 0 2006.286.04:38:56.93#ibcon#*after write, iclass 6, count 0 2006.286.04:38:56.93#ibcon#*before return 0, iclass 6, count 0 2006.286.04:38:56.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:38:56.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:38:56.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:38:56.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:38:56.93$vck44/va=6,4 2006.286.04:38:56.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.04:38:56.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.04:38:56.93#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:56.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:38:56.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:38:56.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:38:56.99#ibcon#enter wrdev, iclass 10, count 2 2006.286.04:38:56.99#ibcon#first serial, iclass 10, count 2 2006.286.04:38:56.99#ibcon#enter sib2, iclass 10, count 2 2006.286.04:38:56.99#ibcon#flushed, iclass 10, count 2 2006.286.04:38:56.99#ibcon#about to write, iclass 10, count 2 2006.286.04:38:56.99#ibcon#wrote, iclass 10, count 2 2006.286.04:38:56.99#ibcon#about to read 3, iclass 10, count 2 2006.286.04:38:57.01#ibcon#read 3, iclass 10, count 2 2006.286.04:38:57.01#ibcon#about to read 4, iclass 10, count 2 2006.286.04:38:57.01#ibcon#read 4, iclass 10, count 2 2006.286.04:38:57.01#ibcon#about to read 5, iclass 10, count 2 2006.286.04:38:57.01#ibcon#read 5, iclass 10, count 2 2006.286.04:38:57.01#ibcon#about to read 6, iclass 10, count 2 2006.286.04:38:57.01#ibcon#read 6, iclass 10, count 2 2006.286.04:38:57.01#ibcon#end of sib2, iclass 10, count 2 2006.286.04:38:57.01#ibcon#*mode == 0, iclass 10, count 2 2006.286.04:38:57.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.04:38:57.01#ibcon#[25=AT06-04\r\n] 2006.286.04:38:57.01#ibcon#*before write, iclass 10, count 2 2006.286.04:38:57.01#ibcon#enter sib2, iclass 10, count 2 2006.286.04:38:57.01#ibcon#flushed, iclass 10, count 2 2006.286.04:38:57.01#ibcon#about to write, iclass 10, count 2 2006.286.04:38:57.01#ibcon#wrote, iclass 10, count 2 2006.286.04:38:57.01#ibcon#about to read 3, iclass 10, count 2 2006.286.04:38:57.04#ibcon#read 3, iclass 10, count 2 2006.286.04:38:57.04#ibcon#about to read 4, iclass 10, count 2 2006.286.04:38:57.04#ibcon#read 4, iclass 10, count 2 2006.286.04:38:57.04#ibcon#about to read 5, iclass 10, count 2 2006.286.04:38:57.04#ibcon#read 5, iclass 10, count 2 2006.286.04:38:57.04#ibcon#about to read 6, iclass 10, count 2 2006.286.04:38:57.04#ibcon#read 6, iclass 10, count 2 2006.286.04:38:57.04#ibcon#end of sib2, iclass 10, count 2 2006.286.04:38:57.04#ibcon#*after write, iclass 10, count 2 2006.286.04:38:57.04#ibcon#*before return 0, iclass 10, count 2 2006.286.04:38:57.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:38:57.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:38:57.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.04:38:57.04#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:57.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:38:57.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:38:57.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:38:57.18#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:38:57.18#ibcon#first serial, iclass 10, count 0 2006.286.04:38:57.18#ibcon#enter sib2, iclass 10, count 0 2006.286.04:38:57.18#ibcon#flushed, iclass 10, count 0 2006.286.04:38:57.18#ibcon#about to write, iclass 10, count 0 2006.286.04:38:57.18#ibcon#wrote, iclass 10, count 0 2006.286.04:38:57.18#ibcon#about to read 3, iclass 10, count 0 2006.286.04:38:57.19#ibcon#read 3, iclass 10, count 0 2006.286.04:38:57.19#ibcon#about to read 4, iclass 10, count 0 2006.286.04:38:57.19#ibcon#read 4, iclass 10, count 0 2006.286.04:38:57.19#ibcon#about to read 5, iclass 10, count 0 2006.286.04:38:57.19#ibcon#read 5, iclass 10, count 0 2006.286.04:38:57.19#ibcon#about to read 6, iclass 10, count 0 2006.286.04:38:57.19#ibcon#read 6, iclass 10, count 0 2006.286.04:38:57.19#ibcon#end of sib2, iclass 10, count 0 2006.286.04:38:57.19#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:38:57.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:38:57.19#ibcon#[25=USB\r\n] 2006.286.04:38:57.19#ibcon#*before write, iclass 10, count 0 2006.286.04:38:57.19#ibcon#enter sib2, iclass 10, count 0 2006.286.04:38:57.19#ibcon#flushed, iclass 10, count 0 2006.286.04:38:57.19#ibcon#about to write, iclass 10, count 0 2006.286.04:38:57.19#ibcon#wrote, iclass 10, count 0 2006.286.04:38:57.19#ibcon#about to read 3, iclass 10, count 0 2006.286.04:38:57.22#ibcon#read 3, iclass 10, count 0 2006.286.04:38:57.22#ibcon#about to read 4, iclass 10, count 0 2006.286.04:38:57.22#ibcon#read 4, iclass 10, count 0 2006.286.04:38:57.22#ibcon#about to read 5, iclass 10, count 0 2006.286.04:38:57.22#ibcon#read 5, iclass 10, count 0 2006.286.04:38:57.22#ibcon#about to read 6, iclass 10, count 0 2006.286.04:38:57.22#ibcon#read 6, iclass 10, count 0 2006.286.04:38:57.22#ibcon#end of sib2, iclass 10, count 0 2006.286.04:38:57.22#ibcon#*after write, iclass 10, count 0 2006.286.04:38:57.22#ibcon#*before return 0, iclass 10, count 0 2006.286.04:38:57.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:38:57.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:38:57.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:38:57.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:38:57.22$vck44/valo=7,864.99 2006.286.04:38:57.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.04:38:57.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.04:38:57.22#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:57.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:38:57.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:38:57.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:38:57.22#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:38:57.22#ibcon#first serial, iclass 12, count 0 2006.286.04:38:57.22#ibcon#enter sib2, iclass 12, count 0 2006.286.04:38:57.22#ibcon#flushed, iclass 12, count 0 2006.286.04:38:57.22#ibcon#about to write, iclass 12, count 0 2006.286.04:38:57.22#ibcon#wrote, iclass 12, count 0 2006.286.04:38:57.22#ibcon#about to read 3, iclass 12, count 0 2006.286.04:38:57.24#ibcon#read 3, iclass 12, count 0 2006.286.04:38:57.24#ibcon#about to read 4, iclass 12, count 0 2006.286.04:38:57.24#ibcon#read 4, iclass 12, count 0 2006.286.04:38:57.24#ibcon#about to read 5, iclass 12, count 0 2006.286.04:38:57.24#ibcon#read 5, iclass 12, count 0 2006.286.04:38:57.24#ibcon#about to read 6, iclass 12, count 0 2006.286.04:38:57.24#ibcon#read 6, iclass 12, count 0 2006.286.04:38:57.24#ibcon#end of sib2, iclass 12, count 0 2006.286.04:38:57.24#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:38:57.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:38:57.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:38:57.24#ibcon#*before write, iclass 12, count 0 2006.286.04:38:57.24#ibcon#enter sib2, iclass 12, count 0 2006.286.04:38:57.24#ibcon#flushed, iclass 12, count 0 2006.286.04:38:57.24#ibcon#about to write, iclass 12, count 0 2006.286.04:38:57.24#ibcon#wrote, iclass 12, count 0 2006.286.04:38:57.24#ibcon#about to read 3, iclass 12, count 0 2006.286.04:38:57.28#ibcon#read 3, iclass 12, count 0 2006.286.04:38:57.28#ibcon#about to read 4, iclass 12, count 0 2006.286.04:38:57.28#ibcon#read 4, iclass 12, count 0 2006.286.04:38:57.28#ibcon#about to read 5, iclass 12, count 0 2006.286.04:38:57.28#ibcon#read 5, iclass 12, count 0 2006.286.04:38:57.28#ibcon#about to read 6, iclass 12, count 0 2006.286.04:38:57.28#ibcon#read 6, iclass 12, count 0 2006.286.04:38:57.28#ibcon#end of sib2, iclass 12, count 0 2006.286.04:38:57.28#ibcon#*after write, iclass 12, count 0 2006.286.04:38:57.28#ibcon#*before return 0, iclass 12, count 0 2006.286.04:38:57.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:38:57.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:38:57.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:38:57.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:38:57.28$vck44/va=7,4 2006.286.04:38:57.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.04:38:57.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.04:38:57.28#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:57.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:38:57.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:38:57.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:38:57.34#ibcon#enter wrdev, iclass 14, count 2 2006.286.04:38:57.34#ibcon#first serial, iclass 14, count 2 2006.286.04:38:57.34#ibcon#enter sib2, iclass 14, count 2 2006.286.04:38:57.34#ibcon#flushed, iclass 14, count 2 2006.286.04:38:57.34#ibcon#about to write, iclass 14, count 2 2006.286.04:38:57.34#ibcon#wrote, iclass 14, count 2 2006.286.04:38:57.34#ibcon#about to read 3, iclass 14, count 2 2006.286.04:38:57.36#ibcon#read 3, iclass 14, count 2 2006.286.04:38:57.36#ibcon#about to read 4, iclass 14, count 2 2006.286.04:38:57.36#ibcon#read 4, iclass 14, count 2 2006.286.04:38:57.36#ibcon#about to read 5, iclass 14, count 2 2006.286.04:38:57.36#ibcon#read 5, iclass 14, count 2 2006.286.04:38:57.36#ibcon#about to read 6, iclass 14, count 2 2006.286.04:38:57.36#ibcon#read 6, iclass 14, count 2 2006.286.04:38:57.36#ibcon#end of sib2, iclass 14, count 2 2006.286.04:38:57.36#ibcon#*mode == 0, iclass 14, count 2 2006.286.04:38:57.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.04:38:57.36#ibcon#[25=AT07-04\r\n] 2006.286.04:38:57.36#ibcon#*before write, iclass 14, count 2 2006.286.04:38:57.36#ibcon#enter sib2, iclass 14, count 2 2006.286.04:38:57.36#ibcon#flushed, iclass 14, count 2 2006.286.04:38:57.36#ibcon#about to write, iclass 14, count 2 2006.286.04:38:57.36#ibcon#wrote, iclass 14, count 2 2006.286.04:38:57.36#ibcon#about to read 3, iclass 14, count 2 2006.286.04:38:57.39#ibcon#read 3, iclass 14, count 2 2006.286.04:38:57.39#ibcon#about to read 4, iclass 14, count 2 2006.286.04:38:57.39#ibcon#read 4, iclass 14, count 2 2006.286.04:38:57.39#ibcon#about to read 5, iclass 14, count 2 2006.286.04:38:57.39#ibcon#read 5, iclass 14, count 2 2006.286.04:38:57.39#ibcon#about to read 6, iclass 14, count 2 2006.286.04:38:57.39#ibcon#read 6, iclass 14, count 2 2006.286.04:38:57.39#ibcon#end of sib2, iclass 14, count 2 2006.286.04:38:57.39#ibcon#*after write, iclass 14, count 2 2006.286.04:38:57.39#ibcon#*before return 0, iclass 14, count 2 2006.286.04:38:57.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:38:57.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:38:57.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.04:38:57.39#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:57.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:38:57.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:38:57.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:38:57.51#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:38:57.51#ibcon#first serial, iclass 14, count 0 2006.286.04:38:57.51#ibcon#enter sib2, iclass 14, count 0 2006.286.04:38:57.51#ibcon#flushed, iclass 14, count 0 2006.286.04:38:57.51#ibcon#about to write, iclass 14, count 0 2006.286.04:38:57.51#ibcon#wrote, iclass 14, count 0 2006.286.04:38:57.51#ibcon#about to read 3, iclass 14, count 0 2006.286.04:38:57.53#ibcon#read 3, iclass 14, count 0 2006.286.04:38:57.53#ibcon#about to read 4, iclass 14, count 0 2006.286.04:38:57.53#ibcon#read 4, iclass 14, count 0 2006.286.04:38:57.53#ibcon#about to read 5, iclass 14, count 0 2006.286.04:38:57.53#ibcon#read 5, iclass 14, count 0 2006.286.04:38:57.53#ibcon#about to read 6, iclass 14, count 0 2006.286.04:38:57.53#ibcon#read 6, iclass 14, count 0 2006.286.04:38:57.53#ibcon#end of sib2, iclass 14, count 0 2006.286.04:38:57.53#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:38:57.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:38:57.53#ibcon#[25=USB\r\n] 2006.286.04:38:57.53#ibcon#*before write, iclass 14, count 0 2006.286.04:38:57.53#ibcon#enter sib2, iclass 14, count 0 2006.286.04:38:57.53#ibcon#flushed, iclass 14, count 0 2006.286.04:38:57.53#ibcon#about to write, iclass 14, count 0 2006.286.04:38:57.53#ibcon#wrote, iclass 14, count 0 2006.286.04:38:57.53#ibcon#about to read 3, iclass 14, count 0 2006.286.04:38:57.56#ibcon#read 3, iclass 14, count 0 2006.286.04:38:57.56#ibcon#about to read 4, iclass 14, count 0 2006.286.04:38:57.56#ibcon#read 4, iclass 14, count 0 2006.286.04:38:57.56#ibcon#about to read 5, iclass 14, count 0 2006.286.04:38:57.56#ibcon#read 5, iclass 14, count 0 2006.286.04:38:57.56#ibcon#about to read 6, iclass 14, count 0 2006.286.04:38:57.56#ibcon#read 6, iclass 14, count 0 2006.286.04:38:57.56#ibcon#end of sib2, iclass 14, count 0 2006.286.04:38:57.56#ibcon#*after write, iclass 14, count 0 2006.286.04:38:57.56#ibcon#*before return 0, iclass 14, count 0 2006.286.04:38:57.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:38:57.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:38:57.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:38:57.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:38:57.56$vck44/valo=8,884.99 2006.286.04:38:57.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.04:38:57.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.04:38:57.56#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:57.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:38:57.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:38:57.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:38:57.56#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:38:57.56#ibcon#first serial, iclass 16, count 0 2006.286.04:38:57.56#ibcon#enter sib2, iclass 16, count 0 2006.286.04:38:57.56#ibcon#flushed, iclass 16, count 0 2006.286.04:38:57.56#ibcon#about to write, iclass 16, count 0 2006.286.04:38:57.56#ibcon#wrote, iclass 16, count 0 2006.286.04:38:57.56#ibcon#about to read 3, iclass 16, count 0 2006.286.04:38:57.58#ibcon#read 3, iclass 16, count 0 2006.286.04:38:57.58#ibcon#about to read 4, iclass 16, count 0 2006.286.04:38:57.58#ibcon#read 4, iclass 16, count 0 2006.286.04:38:57.58#ibcon#about to read 5, iclass 16, count 0 2006.286.04:38:57.58#ibcon#read 5, iclass 16, count 0 2006.286.04:38:57.58#ibcon#about to read 6, iclass 16, count 0 2006.286.04:38:57.58#ibcon#read 6, iclass 16, count 0 2006.286.04:38:57.58#ibcon#end of sib2, iclass 16, count 0 2006.286.04:38:57.58#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:38:57.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:38:57.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:38:57.58#ibcon#*before write, iclass 16, count 0 2006.286.04:38:57.58#ibcon#enter sib2, iclass 16, count 0 2006.286.04:38:57.58#ibcon#flushed, iclass 16, count 0 2006.286.04:38:57.58#ibcon#about to write, iclass 16, count 0 2006.286.04:38:57.58#ibcon#wrote, iclass 16, count 0 2006.286.04:38:57.58#ibcon#about to read 3, iclass 16, count 0 2006.286.04:38:57.62#ibcon#read 3, iclass 16, count 0 2006.286.04:38:57.62#ibcon#about to read 4, iclass 16, count 0 2006.286.04:38:57.62#ibcon#read 4, iclass 16, count 0 2006.286.04:38:57.62#ibcon#about to read 5, iclass 16, count 0 2006.286.04:38:57.62#ibcon#read 5, iclass 16, count 0 2006.286.04:38:57.62#ibcon#about to read 6, iclass 16, count 0 2006.286.04:38:57.62#ibcon#read 6, iclass 16, count 0 2006.286.04:38:57.62#ibcon#end of sib2, iclass 16, count 0 2006.286.04:38:57.62#ibcon#*after write, iclass 16, count 0 2006.286.04:38:57.62#ibcon#*before return 0, iclass 16, count 0 2006.286.04:38:57.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:38:57.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.04:38:57.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:38:57.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:38:57.62$vck44/va=8,3 2006.286.04:38:57.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.04:38:57.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.04:38:57.62#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:57.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:38:57.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:38:57.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:38:57.68#ibcon#enter wrdev, iclass 18, count 2 2006.286.04:38:57.68#ibcon#first serial, iclass 18, count 2 2006.286.04:38:57.68#ibcon#enter sib2, iclass 18, count 2 2006.286.04:38:57.68#ibcon#flushed, iclass 18, count 2 2006.286.04:38:57.68#ibcon#about to write, iclass 18, count 2 2006.286.04:38:57.68#ibcon#wrote, iclass 18, count 2 2006.286.04:38:57.68#ibcon#about to read 3, iclass 18, count 2 2006.286.04:38:57.70#ibcon#read 3, iclass 18, count 2 2006.286.04:38:57.70#ibcon#about to read 4, iclass 18, count 2 2006.286.04:38:57.70#ibcon#read 4, iclass 18, count 2 2006.286.04:38:57.70#ibcon#about to read 5, iclass 18, count 2 2006.286.04:38:57.70#ibcon#read 5, iclass 18, count 2 2006.286.04:38:57.70#ibcon#about to read 6, iclass 18, count 2 2006.286.04:38:57.70#ibcon#read 6, iclass 18, count 2 2006.286.04:38:57.70#ibcon#end of sib2, iclass 18, count 2 2006.286.04:38:57.70#ibcon#*mode == 0, iclass 18, count 2 2006.286.04:38:57.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.04:38:57.70#ibcon#[25=AT08-03\r\n] 2006.286.04:38:57.70#ibcon#*before write, iclass 18, count 2 2006.286.04:38:57.70#ibcon#enter sib2, iclass 18, count 2 2006.286.04:38:57.70#ibcon#flushed, iclass 18, count 2 2006.286.04:38:57.70#ibcon#about to write, iclass 18, count 2 2006.286.04:38:57.70#ibcon#wrote, iclass 18, count 2 2006.286.04:38:57.70#ibcon#about to read 3, iclass 18, count 2 2006.286.04:38:57.73#ibcon#read 3, iclass 18, count 2 2006.286.04:38:57.73#ibcon#about to read 4, iclass 18, count 2 2006.286.04:38:57.73#ibcon#read 4, iclass 18, count 2 2006.286.04:38:57.73#ibcon#about to read 5, iclass 18, count 2 2006.286.04:38:57.73#ibcon#read 5, iclass 18, count 2 2006.286.04:38:57.73#ibcon#about to read 6, iclass 18, count 2 2006.286.04:38:57.73#ibcon#read 6, iclass 18, count 2 2006.286.04:38:57.73#ibcon#end of sib2, iclass 18, count 2 2006.286.04:38:57.73#ibcon#*after write, iclass 18, count 2 2006.286.04:38:57.73#ibcon#*before return 0, iclass 18, count 2 2006.286.04:38:57.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:38:57.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.04:38:57.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.04:38:57.73#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:57.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:38:57.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:38:57.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:38:57.85#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:38:57.85#ibcon#first serial, iclass 18, count 0 2006.286.04:38:57.85#ibcon#enter sib2, iclass 18, count 0 2006.286.04:38:57.85#ibcon#flushed, iclass 18, count 0 2006.286.04:38:57.85#ibcon#about to write, iclass 18, count 0 2006.286.04:38:57.85#ibcon#wrote, iclass 18, count 0 2006.286.04:38:57.85#ibcon#about to read 3, iclass 18, count 0 2006.286.04:38:57.87#ibcon#read 3, iclass 18, count 0 2006.286.04:38:57.87#ibcon#about to read 4, iclass 18, count 0 2006.286.04:38:57.87#ibcon#read 4, iclass 18, count 0 2006.286.04:38:57.87#ibcon#about to read 5, iclass 18, count 0 2006.286.04:38:57.87#ibcon#read 5, iclass 18, count 0 2006.286.04:38:57.87#ibcon#about to read 6, iclass 18, count 0 2006.286.04:38:57.87#ibcon#read 6, iclass 18, count 0 2006.286.04:38:57.87#ibcon#end of sib2, iclass 18, count 0 2006.286.04:38:57.87#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:38:57.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:38:57.87#ibcon#[25=USB\r\n] 2006.286.04:38:57.87#ibcon#*before write, iclass 18, count 0 2006.286.04:38:57.87#ibcon#enter sib2, iclass 18, count 0 2006.286.04:38:57.87#ibcon#flushed, iclass 18, count 0 2006.286.04:38:57.87#ibcon#about to write, iclass 18, count 0 2006.286.04:38:57.87#ibcon#wrote, iclass 18, count 0 2006.286.04:38:57.87#ibcon#about to read 3, iclass 18, count 0 2006.286.04:38:57.90#ibcon#read 3, iclass 18, count 0 2006.286.04:38:57.90#ibcon#about to read 4, iclass 18, count 0 2006.286.04:38:57.90#ibcon#read 4, iclass 18, count 0 2006.286.04:38:57.90#ibcon#about to read 5, iclass 18, count 0 2006.286.04:38:57.90#ibcon#read 5, iclass 18, count 0 2006.286.04:38:57.90#ibcon#about to read 6, iclass 18, count 0 2006.286.04:38:57.90#ibcon#read 6, iclass 18, count 0 2006.286.04:38:57.90#ibcon#end of sib2, iclass 18, count 0 2006.286.04:38:57.90#ibcon#*after write, iclass 18, count 0 2006.286.04:38:57.90#ibcon#*before return 0, iclass 18, count 0 2006.286.04:38:57.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:38:57.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.04:38:57.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:38:57.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:38:57.90$vck44/vblo=1,629.99 2006.286.04:38:57.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.04:38:57.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.04:38:57.90#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:57.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:38:57.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:38:57.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:38:57.90#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:38:57.90#ibcon#first serial, iclass 20, count 0 2006.286.04:38:57.90#ibcon#enter sib2, iclass 20, count 0 2006.286.04:38:57.90#ibcon#flushed, iclass 20, count 0 2006.286.04:38:57.90#ibcon#about to write, iclass 20, count 0 2006.286.04:38:57.90#ibcon#wrote, iclass 20, count 0 2006.286.04:38:57.90#ibcon#about to read 3, iclass 20, count 0 2006.286.04:38:57.92#ibcon#read 3, iclass 20, count 0 2006.286.04:38:57.92#ibcon#about to read 4, iclass 20, count 0 2006.286.04:38:57.92#ibcon#read 4, iclass 20, count 0 2006.286.04:38:57.92#ibcon#about to read 5, iclass 20, count 0 2006.286.04:38:57.92#ibcon#read 5, iclass 20, count 0 2006.286.04:38:57.92#ibcon#about to read 6, iclass 20, count 0 2006.286.04:38:57.92#ibcon#read 6, iclass 20, count 0 2006.286.04:38:57.92#ibcon#end of sib2, iclass 20, count 0 2006.286.04:38:57.92#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:38:57.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:38:57.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:38:57.92#ibcon#*before write, iclass 20, count 0 2006.286.04:38:57.92#ibcon#enter sib2, iclass 20, count 0 2006.286.04:38:57.92#ibcon#flushed, iclass 20, count 0 2006.286.04:38:57.92#ibcon#about to write, iclass 20, count 0 2006.286.04:38:57.92#ibcon#wrote, iclass 20, count 0 2006.286.04:38:57.92#ibcon#about to read 3, iclass 20, count 0 2006.286.04:38:57.96#ibcon#read 3, iclass 20, count 0 2006.286.04:38:57.96#ibcon#about to read 4, iclass 20, count 0 2006.286.04:38:57.96#ibcon#read 4, iclass 20, count 0 2006.286.04:38:57.96#ibcon#about to read 5, iclass 20, count 0 2006.286.04:38:57.96#ibcon#read 5, iclass 20, count 0 2006.286.04:38:57.96#ibcon#about to read 6, iclass 20, count 0 2006.286.04:38:57.96#ibcon#read 6, iclass 20, count 0 2006.286.04:38:57.96#ibcon#end of sib2, iclass 20, count 0 2006.286.04:38:57.96#ibcon#*after write, iclass 20, count 0 2006.286.04:38:57.96#ibcon#*before return 0, iclass 20, count 0 2006.286.04:38:57.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:38:57.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.04:38:57.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:38:57.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:38:57.96$vck44/vb=1,4 2006.286.04:38:57.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.04:38:57.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.04:38:57.96#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:57.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:38:57.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:38:57.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:38:57.96#ibcon#enter wrdev, iclass 22, count 2 2006.286.04:38:57.96#ibcon#first serial, iclass 22, count 2 2006.286.04:38:57.96#ibcon#enter sib2, iclass 22, count 2 2006.286.04:38:57.96#ibcon#flushed, iclass 22, count 2 2006.286.04:38:57.96#ibcon#about to write, iclass 22, count 2 2006.286.04:38:57.96#ibcon#wrote, iclass 22, count 2 2006.286.04:38:57.96#ibcon#about to read 3, iclass 22, count 2 2006.286.04:38:57.98#ibcon#read 3, iclass 22, count 2 2006.286.04:38:57.98#ibcon#about to read 4, iclass 22, count 2 2006.286.04:38:57.98#ibcon#read 4, iclass 22, count 2 2006.286.04:38:57.98#ibcon#about to read 5, iclass 22, count 2 2006.286.04:38:57.98#ibcon#read 5, iclass 22, count 2 2006.286.04:38:57.98#ibcon#about to read 6, iclass 22, count 2 2006.286.04:38:57.98#ibcon#read 6, iclass 22, count 2 2006.286.04:38:57.98#ibcon#end of sib2, iclass 22, count 2 2006.286.04:38:57.98#ibcon#*mode == 0, iclass 22, count 2 2006.286.04:38:57.98#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.04:38:57.98#ibcon#[27=AT01-04\r\n] 2006.286.04:38:57.98#ibcon#*before write, iclass 22, count 2 2006.286.04:38:57.98#ibcon#enter sib2, iclass 22, count 2 2006.286.04:38:57.98#ibcon#flushed, iclass 22, count 2 2006.286.04:38:57.98#ibcon#about to write, iclass 22, count 2 2006.286.04:38:57.98#ibcon#wrote, iclass 22, count 2 2006.286.04:38:57.98#ibcon#about to read 3, iclass 22, count 2 2006.286.04:38:58.01#ibcon#read 3, iclass 22, count 2 2006.286.04:38:58.01#ibcon#about to read 4, iclass 22, count 2 2006.286.04:38:58.01#ibcon#read 4, iclass 22, count 2 2006.286.04:38:58.01#ibcon#about to read 5, iclass 22, count 2 2006.286.04:38:58.01#ibcon#read 5, iclass 22, count 2 2006.286.04:38:58.01#ibcon#about to read 6, iclass 22, count 2 2006.286.04:38:58.01#ibcon#read 6, iclass 22, count 2 2006.286.04:38:58.01#ibcon#end of sib2, iclass 22, count 2 2006.286.04:38:58.01#ibcon#*after write, iclass 22, count 2 2006.286.04:38:58.01#ibcon#*before return 0, iclass 22, count 2 2006.286.04:38:58.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:38:58.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.04:38:58.01#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.04:38:58.01#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:58.01#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:38:58.13#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:38:58.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:38:58.15#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:38:58.15#ibcon#first serial, iclass 22, count 0 2006.286.04:38:58.15#ibcon#enter sib2, iclass 22, count 0 2006.286.04:38:58.15#ibcon#flushed, iclass 22, count 0 2006.286.04:38:58.15#ibcon#about to write, iclass 22, count 0 2006.286.04:38:58.15#ibcon#wrote, iclass 22, count 0 2006.286.04:38:58.15#ibcon#about to read 3, iclass 22, count 0 2006.286.04:38:58.17#ibcon#read 3, iclass 22, count 0 2006.286.04:38:58.17#ibcon#about to read 4, iclass 22, count 0 2006.286.04:38:58.17#ibcon#read 4, iclass 22, count 0 2006.286.04:38:58.17#ibcon#about to read 5, iclass 22, count 0 2006.286.04:38:58.17#ibcon#read 5, iclass 22, count 0 2006.286.04:38:58.17#ibcon#about to read 6, iclass 22, count 0 2006.286.04:38:58.17#ibcon#read 6, iclass 22, count 0 2006.286.04:38:58.17#ibcon#end of sib2, iclass 22, count 0 2006.286.04:38:58.17#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:38:58.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:38:58.17#ibcon#[27=USB\r\n] 2006.286.04:38:58.17#ibcon#*before write, iclass 22, count 0 2006.286.04:38:58.17#ibcon#enter sib2, iclass 22, count 0 2006.286.04:38:58.17#ibcon#flushed, iclass 22, count 0 2006.286.04:38:58.17#ibcon#about to write, iclass 22, count 0 2006.286.04:38:58.17#ibcon#wrote, iclass 22, count 0 2006.286.04:38:58.17#ibcon#about to read 3, iclass 22, count 0 2006.286.04:38:58.20#ibcon#read 3, iclass 22, count 0 2006.286.04:38:58.20#ibcon#about to read 4, iclass 22, count 0 2006.286.04:38:58.20#ibcon#read 4, iclass 22, count 0 2006.286.04:38:58.20#ibcon#about to read 5, iclass 22, count 0 2006.286.04:38:58.20#ibcon#read 5, iclass 22, count 0 2006.286.04:38:58.20#ibcon#about to read 6, iclass 22, count 0 2006.286.04:38:58.20#ibcon#read 6, iclass 22, count 0 2006.286.04:38:58.20#ibcon#end of sib2, iclass 22, count 0 2006.286.04:38:58.20#ibcon#*after write, iclass 22, count 0 2006.286.04:38:58.20#ibcon#*before return 0, iclass 22, count 0 2006.286.04:38:58.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:38:58.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.04:38:58.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:38:58.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:38:58.20$vck44/vblo=2,634.99 2006.286.04:38:58.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.04:38:58.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.04:38:58.20#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:58.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:38:58.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:38:58.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:38:58.20#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:38:58.20#ibcon#first serial, iclass 24, count 0 2006.286.04:38:58.20#ibcon#enter sib2, iclass 24, count 0 2006.286.04:38:58.20#ibcon#flushed, iclass 24, count 0 2006.286.04:38:58.20#ibcon#about to write, iclass 24, count 0 2006.286.04:38:58.20#ibcon#wrote, iclass 24, count 0 2006.286.04:38:58.20#ibcon#about to read 3, iclass 24, count 0 2006.286.04:38:58.22#ibcon#read 3, iclass 24, count 0 2006.286.04:38:58.22#ibcon#about to read 4, iclass 24, count 0 2006.286.04:38:58.22#ibcon#read 4, iclass 24, count 0 2006.286.04:38:58.22#ibcon#about to read 5, iclass 24, count 0 2006.286.04:38:58.22#ibcon#read 5, iclass 24, count 0 2006.286.04:38:58.22#ibcon#about to read 6, iclass 24, count 0 2006.286.04:38:58.22#ibcon#read 6, iclass 24, count 0 2006.286.04:38:58.22#ibcon#end of sib2, iclass 24, count 0 2006.286.04:38:58.22#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:38:58.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:38:58.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:38:58.22#ibcon#*before write, iclass 24, count 0 2006.286.04:38:58.22#ibcon#enter sib2, iclass 24, count 0 2006.286.04:38:58.22#ibcon#flushed, iclass 24, count 0 2006.286.04:38:58.22#ibcon#about to write, iclass 24, count 0 2006.286.04:38:58.22#ibcon#wrote, iclass 24, count 0 2006.286.04:38:58.22#ibcon#about to read 3, iclass 24, count 0 2006.286.04:38:58.26#ibcon#read 3, iclass 24, count 0 2006.286.04:38:58.26#ibcon#about to read 4, iclass 24, count 0 2006.286.04:38:58.26#ibcon#read 4, iclass 24, count 0 2006.286.04:38:58.26#ibcon#about to read 5, iclass 24, count 0 2006.286.04:38:58.26#ibcon#read 5, iclass 24, count 0 2006.286.04:38:58.26#ibcon#about to read 6, iclass 24, count 0 2006.286.04:38:58.26#ibcon#read 6, iclass 24, count 0 2006.286.04:38:58.26#ibcon#end of sib2, iclass 24, count 0 2006.286.04:38:58.26#ibcon#*after write, iclass 24, count 0 2006.286.04:38:58.26#ibcon#*before return 0, iclass 24, count 0 2006.286.04:38:58.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:38:58.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.04:38:58.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:38:58.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:38:58.26$vck44/vb=2,5 2006.286.04:38:58.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.04:38:58.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.04:38:58.26#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:58.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:38:58.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:38:58.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:38:58.32#ibcon#enter wrdev, iclass 26, count 2 2006.286.04:38:58.32#ibcon#first serial, iclass 26, count 2 2006.286.04:38:58.32#ibcon#enter sib2, iclass 26, count 2 2006.286.04:38:58.32#ibcon#flushed, iclass 26, count 2 2006.286.04:38:58.32#ibcon#about to write, iclass 26, count 2 2006.286.04:38:58.32#ibcon#wrote, iclass 26, count 2 2006.286.04:38:58.32#ibcon#about to read 3, iclass 26, count 2 2006.286.04:38:58.34#ibcon#read 3, iclass 26, count 2 2006.286.04:38:58.34#ibcon#about to read 4, iclass 26, count 2 2006.286.04:38:58.34#ibcon#read 4, iclass 26, count 2 2006.286.04:38:58.34#ibcon#about to read 5, iclass 26, count 2 2006.286.04:38:58.34#ibcon#read 5, iclass 26, count 2 2006.286.04:38:58.34#ibcon#about to read 6, iclass 26, count 2 2006.286.04:38:58.34#ibcon#read 6, iclass 26, count 2 2006.286.04:38:58.34#ibcon#end of sib2, iclass 26, count 2 2006.286.04:38:58.34#ibcon#*mode == 0, iclass 26, count 2 2006.286.04:38:58.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.04:38:58.34#ibcon#[27=AT02-05\r\n] 2006.286.04:38:58.34#ibcon#*before write, iclass 26, count 2 2006.286.04:38:58.34#ibcon#enter sib2, iclass 26, count 2 2006.286.04:38:58.34#ibcon#flushed, iclass 26, count 2 2006.286.04:38:58.34#ibcon#about to write, iclass 26, count 2 2006.286.04:38:58.34#ibcon#wrote, iclass 26, count 2 2006.286.04:38:58.34#ibcon#about to read 3, iclass 26, count 2 2006.286.04:38:58.37#ibcon#read 3, iclass 26, count 2 2006.286.04:38:58.37#ibcon#about to read 4, iclass 26, count 2 2006.286.04:38:58.37#ibcon#read 4, iclass 26, count 2 2006.286.04:38:58.37#ibcon#about to read 5, iclass 26, count 2 2006.286.04:38:58.37#ibcon#read 5, iclass 26, count 2 2006.286.04:38:58.37#ibcon#about to read 6, iclass 26, count 2 2006.286.04:38:58.37#ibcon#read 6, iclass 26, count 2 2006.286.04:38:58.37#ibcon#end of sib2, iclass 26, count 2 2006.286.04:38:58.37#ibcon#*after write, iclass 26, count 2 2006.286.04:38:58.37#ibcon#*before return 0, iclass 26, count 2 2006.286.04:38:58.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:38:58.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.04:38:58.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.04:38:58.37#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:58.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:38:58.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:38:58.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:38:58.49#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:38:58.49#ibcon#first serial, iclass 26, count 0 2006.286.04:38:58.49#ibcon#enter sib2, iclass 26, count 0 2006.286.04:38:58.49#ibcon#flushed, iclass 26, count 0 2006.286.04:38:58.49#ibcon#about to write, iclass 26, count 0 2006.286.04:38:58.49#ibcon#wrote, iclass 26, count 0 2006.286.04:38:58.49#ibcon#about to read 3, iclass 26, count 0 2006.286.04:38:58.51#ibcon#read 3, iclass 26, count 0 2006.286.04:38:58.51#ibcon#about to read 4, iclass 26, count 0 2006.286.04:38:58.51#ibcon#read 4, iclass 26, count 0 2006.286.04:38:58.51#ibcon#about to read 5, iclass 26, count 0 2006.286.04:38:58.51#ibcon#read 5, iclass 26, count 0 2006.286.04:38:58.51#ibcon#about to read 6, iclass 26, count 0 2006.286.04:38:58.51#ibcon#read 6, iclass 26, count 0 2006.286.04:38:58.51#ibcon#end of sib2, iclass 26, count 0 2006.286.04:38:58.51#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:38:58.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:38:58.51#ibcon#[27=USB\r\n] 2006.286.04:38:58.51#ibcon#*before write, iclass 26, count 0 2006.286.04:38:58.51#ibcon#enter sib2, iclass 26, count 0 2006.286.04:38:58.51#ibcon#flushed, iclass 26, count 0 2006.286.04:38:58.51#ibcon#about to write, iclass 26, count 0 2006.286.04:38:58.51#ibcon#wrote, iclass 26, count 0 2006.286.04:38:58.51#ibcon#about to read 3, iclass 26, count 0 2006.286.04:38:58.54#ibcon#read 3, iclass 26, count 0 2006.286.04:38:58.54#ibcon#about to read 4, iclass 26, count 0 2006.286.04:38:58.54#ibcon#read 4, iclass 26, count 0 2006.286.04:38:58.54#ibcon#about to read 5, iclass 26, count 0 2006.286.04:38:58.54#ibcon#read 5, iclass 26, count 0 2006.286.04:38:58.54#ibcon#about to read 6, iclass 26, count 0 2006.286.04:38:58.54#ibcon#read 6, iclass 26, count 0 2006.286.04:38:58.54#ibcon#end of sib2, iclass 26, count 0 2006.286.04:38:58.54#ibcon#*after write, iclass 26, count 0 2006.286.04:38:58.54#ibcon#*before return 0, iclass 26, count 0 2006.286.04:38:58.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:38:58.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.04:38:58.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:38:58.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:38:58.54$vck44/vblo=3,649.99 2006.286.04:38:58.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.04:38:58.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.04:38:58.54#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:58.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:38:58.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:38:58.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:38:58.54#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:38:58.54#ibcon#first serial, iclass 28, count 0 2006.286.04:38:58.54#ibcon#enter sib2, iclass 28, count 0 2006.286.04:38:58.54#ibcon#flushed, iclass 28, count 0 2006.286.04:38:58.54#ibcon#about to write, iclass 28, count 0 2006.286.04:38:58.54#ibcon#wrote, iclass 28, count 0 2006.286.04:38:58.54#ibcon#about to read 3, iclass 28, count 0 2006.286.04:38:58.56#ibcon#read 3, iclass 28, count 0 2006.286.04:38:58.56#ibcon#about to read 4, iclass 28, count 0 2006.286.04:38:58.56#ibcon#read 4, iclass 28, count 0 2006.286.04:38:58.56#ibcon#about to read 5, iclass 28, count 0 2006.286.04:38:58.56#ibcon#read 5, iclass 28, count 0 2006.286.04:38:58.56#ibcon#about to read 6, iclass 28, count 0 2006.286.04:38:58.56#ibcon#read 6, iclass 28, count 0 2006.286.04:38:58.56#ibcon#end of sib2, iclass 28, count 0 2006.286.04:38:58.56#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:38:58.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:38:58.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:38:58.56#ibcon#*before write, iclass 28, count 0 2006.286.04:38:58.56#ibcon#enter sib2, iclass 28, count 0 2006.286.04:38:58.56#ibcon#flushed, iclass 28, count 0 2006.286.04:38:58.56#ibcon#about to write, iclass 28, count 0 2006.286.04:38:58.56#ibcon#wrote, iclass 28, count 0 2006.286.04:38:58.56#ibcon#about to read 3, iclass 28, count 0 2006.286.04:38:58.60#ibcon#read 3, iclass 28, count 0 2006.286.04:38:58.60#ibcon#about to read 4, iclass 28, count 0 2006.286.04:38:58.60#ibcon#read 4, iclass 28, count 0 2006.286.04:38:58.60#ibcon#about to read 5, iclass 28, count 0 2006.286.04:38:58.60#ibcon#read 5, iclass 28, count 0 2006.286.04:38:58.60#ibcon#about to read 6, iclass 28, count 0 2006.286.04:38:58.60#ibcon#read 6, iclass 28, count 0 2006.286.04:38:58.60#ibcon#end of sib2, iclass 28, count 0 2006.286.04:38:58.60#ibcon#*after write, iclass 28, count 0 2006.286.04:38:58.60#ibcon#*before return 0, iclass 28, count 0 2006.286.04:38:58.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:38:58.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:38:58.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:38:58.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:38:58.60$vck44/vb=3,4 2006.286.04:38:58.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.04:38:58.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.04:38:58.60#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:58.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:38:58.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:38:58.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:38:58.66#ibcon#enter wrdev, iclass 30, count 2 2006.286.04:38:58.66#ibcon#first serial, iclass 30, count 2 2006.286.04:38:58.66#ibcon#enter sib2, iclass 30, count 2 2006.286.04:38:58.66#ibcon#flushed, iclass 30, count 2 2006.286.04:38:58.66#ibcon#about to write, iclass 30, count 2 2006.286.04:38:58.66#ibcon#wrote, iclass 30, count 2 2006.286.04:38:58.66#ibcon#about to read 3, iclass 30, count 2 2006.286.04:38:58.68#ibcon#read 3, iclass 30, count 2 2006.286.04:38:58.68#ibcon#about to read 4, iclass 30, count 2 2006.286.04:38:58.68#ibcon#read 4, iclass 30, count 2 2006.286.04:38:58.68#ibcon#about to read 5, iclass 30, count 2 2006.286.04:38:58.68#ibcon#read 5, iclass 30, count 2 2006.286.04:38:58.68#ibcon#about to read 6, iclass 30, count 2 2006.286.04:38:58.68#ibcon#read 6, iclass 30, count 2 2006.286.04:38:58.68#ibcon#end of sib2, iclass 30, count 2 2006.286.04:38:58.68#ibcon#*mode == 0, iclass 30, count 2 2006.286.04:38:58.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.04:38:58.68#ibcon#[27=AT03-04\r\n] 2006.286.04:38:58.68#ibcon#*before write, iclass 30, count 2 2006.286.04:38:58.68#ibcon#enter sib2, iclass 30, count 2 2006.286.04:38:58.68#ibcon#flushed, iclass 30, count 2 2006.286.04:38:58.68#ibcon#about to write, iclass 30, count 2 2006.286.04:38:58.68#ibcon#wrote, iclass 30, count 2 2006.286.04:38:58.68#ibcon#about to read 3, iclass 30, count 2 2006.286.04:38:58.71#ibcon#read 3, iclass 30, count 2 2006.286.04:38:58.71#ibcon#about to read 4, iclass 30, count 2 2006.286.04:38:58.71#ibcon#read 4, iclass 30, count 2 2006.286.04:38:58.71#ibcon#about to read 5, iclass 30, count 2 2006.286.04:38:58.71#ibcon#read 5, iclass 30, count 2 2006.286.04:38:58.71#ibcon#about to read 6, iclass 30, count 2 2006.286.04:38:58.71#ibcon#read 6, iclass 30, count 2 2006.286.04:38:58.71#ibcon#end of sib2, iclass 30, count 2 2006.286.04:38:58.71#ibcon#*after write, iclass 30, count 2 2006.286.04:38:58.71#ibcon#*before return 0, iclass 30, count 2 2006.286.04:38:58.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:38:58.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.04:38:58.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.04:38:58.71#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:58.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:38:58.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:38:58.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:38:58.83#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:38:58.83#ibcon#first serial, iclass 30, count 0 2006.286.04:38:58.83#ibcon#enter sib2, iclass 30, count 0 2006.286.04:38:58.83#ibcon#flushed, iclass 30, count 0 2006.286.04:38:58.83#ibcon#about to write, iclass 30, count 0 2006.286.04:38:58.83#ibcon#wrote, iclass 30, count 0 2006.286.04:38:58.83#ibcon#about to read 3, iclass 30, count 0 2006.286.04:38:58.85#ibcon#read 3, iclass 30, count 0 2006.286.04:38:58.85#ibcon#about to read 4, iclass 30, count 0 2006.286.04:38:58.85#ibcon#read 4, iclass 30, count 0 2006.286.04:38:58.85#ibcon#about to read 5, iclass 30, count 0 2006.286.04:38:58.85#ibcon#read 5, iclass 30, count 0 2006.286.04:38:58.85#ibcon#about to read 6, iclass 30, count 0 2006.286.04:38:58.85#ibcon#read 6, iclass 30, count 0 2006.286.04:38:58.85#ibcon#end of sib2, iclass 30, count 0 2006.286.04:38:58.85#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:38:58.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:38:58.85#ibcon#[27=USB\r\n] 2006.286.04:38:58.85#ibcon#*before write, iclass 30, count 0 2006.286.04:38:58.85#ibcon#enter sib2, iclass 30, count 0 2006.286.04:38:58.85#ibcon#flushed, iclass 30, count 0 2006.286.04:38:58.85#ibcon#about to write, iclass 30, count 0 2006.286.04:38:58.85#ibcon#wrote, iclass 30, count 0 2006.286.04:38:58.85#ibcon#about to read 3, iclass 30, count 0 2006.286.04:38:58.88#ibcon#read 3, iclass 30, count 0 2006.286.04:38:58.88#ibcon#about to read 4, iclass 30, count 0 2006.286.04:38:58.88#ibcon#read 4, iclass 30, count 0 2006.286.04:38:58.88#ibcon#about to read 5, iclass 30, count 0 2006.286.04:38:58.88#ibcon#read 5, iclass 30, count 0 2006.286.04:38:58.88#ibcon#about to read 6, iclass 30, count 0 2006.286.04:38:58.88#ibcon#read 6, iclass 30, count 0 2006.286.04:38:58.88#ibcon#end of sib2, iclass 30, count 0 2006.286.04:38:58.88#ibcon#*after write, iclass 30, count 0 2006.286.04:38:58.88#ibcon#*before return 0, iclass 30, count 0 2006.286.04:38:58.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:38:58.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.04:38:58.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:38:58.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:38:58.88$vck44/vblo=4,679.99 2006.286.04:38:58.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.04:38:58.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.04:38:58.88#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:58.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:38:58.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:38:58.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:38:58.88#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:38:58.88#ibcon#first serial, iclass 32, count 0 2006.286.04:38:58.88#ibcon#enter sib2, iclass 32, count 0 2006.286.04:38:58.88#ibcon#flushed, iclass 32, count 0 2006.286.04:38:58.88#ibcon#about to write, iclass 32, count 0 2006.286.04:38:58.88#ibcon#wrote, iclass 32, count 0 2006.286.04:38:58.88#ibcon#about to read 3, iclass 32, count 0 2006.286.04:38:58.90#ibcon#read 3, iclass 32, count 0 2006.286.04:38:58.90#ibcon#about to read 4, iclass 32, count 0 2006.286.04:38:58.90#ibcon#read 4, iclass 32, count 0 2006.286.04:38:58.90#ibcon#about to read 5, iclass 32, count 0 2006.286.04:38:58.90#ibcon#read 5, iclass 32, count 0 2006.286.04:38:58.90#ibcon#about to read 6, iclass 32, count 0 2006.286.04:38:58.90#ibcon#read 6, iclass 32, count 0 2006.286.04:38:58.90#ibcon#end of sib2, iclass 32, count 0 2006.286.04:38:58.90#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:38:58.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:38:58.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:38:58.90#ibcon#*before write, iclass 32, count 0 2006.286.04:38:58.90#ibcon#enter sib2, iclass 32, count 0 2006.286.04:38:58.90#ibcon#flushed, iclass 32, count 0 2006.286.04:38:58.90#ibcon#about to write, iclass 32, count 0 2006.286.04:38:58.90#ibcon#wrote, iclass 32, count 0 2006.286.04:38:58.90#ibcon#about to read 3, iclass 32, count 0 2006.286.04:38:58.94#ibcon#read 3, iclass 32, count 0 2006.286.04:38:58.94#ibcon#about to read 4, iclass 32, count 0 2006.286.04:38:58.94#ibcon#read 4, iclass 32, count 0 2006.286.04:38:58.94#ibcon#about to read 5, iclass 32, count 0 2006.286.04:38:58.94#ibcon#read 5, iclass 32, count 0 2006.286.04:38:58.94#ibcon#about to read 6, iclass 32, count 0 2006.286.04:38:58.94#ibcon#read 6, iclass 32, count 0 2006.286.04:38:58.94#ibcon#end of sib2, iclass 32, count 0 2006.286.04:38:58.94#ibcon#*after write, iclass 32, count 0 2006.286.04:38:58.94#ibcon#*before return 0, iclass 32, count 0 2006.286.04:38:58.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:38:58.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.04:38:58.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:38:58.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:38:58.94$vck44/vb=4,5 2006.286.04:38:58.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.04:38:58.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.04:38:58.94#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:58.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:38:59.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:38:59.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:38:59.00#ibcon#enter wrdev, iclass 34, count 2 2006.286.04:38:59.00#ibcon#first serial, iclass 34, count 2 2006.286.04:38:59.00#ibcon#enter sib2, iclass 34, count 2 2006.286.04:38:59.00#ibcon#flushed, iclass 34, count 2 2006.286.04:38:59.00#ibcon#about to write, iclass 34, count 2 2006.286.04:38:59.00#ibcon#wrote, iclass 34, count 2 2006.286.04:38:59.00#ibcon#about to read 3, iclass 34, count 2 2006.286.04:38:59.02#ibcon#read 3, iclass 34, count 2 2006.286.04:38:59.02#ibcon#about to read 4, iclass 34, count 2 2006.286.04:38:59.02#ibcon#read 4, iclass 34, count 2 2006.286.04:38:59.02#ibcon#about to read 5, iclass 34, count 2 2006.286.04:38:59.02#ibcon#read 5, iclass 34, count 2 2006.286.04:38:59.02#ibcon#about to read 6, iclass 34, count 2 2006.286.04:38:59.02#ibcon#read 6, iclass 34, count 2 2006.286.04:38:59.02#ibcon#end of sib2, iclass 34, count 2 2006.286.04:38:59.02#ibcon#*mode == 0, iclass 34, count 2 2006.286.04:38:59.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.04:38:59.02#ibcon#[27=AT04-05\r\n] 2006.286.04:38:59.02#ibcon#*before write, iclass 34, count 2 2006.286.04:38:59.02#ibcon#enter sib2, iclass 34, count 2 2006.286.04:38:59.02#ibcon#flushed, iclass 34, count 2 2006.286.04:38:59.02#ibcon#about to write, iclass 34, count 2 2006.286.04:38:59.02#ibcon#wrote, iclass 34, count 2 2006.286.04:38:59.02#ibcon#about to read 3, iclass 34, count 2 2006.286.04:38:59.05#ibcon#read 3, iclass 34, count 2 2006.286.04:38:59.05#ibcon#about to read 4, iclass 34, count 2 2006.286.04:38:59.05#ibcon#read 4, iclass 34, count 2 2006.286.04:38:59.05#ibcon#about to read 5, iclass 34, count 2 2006.286.04:38:59.05#ibcon#read 5, iclass 34, count 2 2006.286.04:38:59.05#ibcon#about to read 6, iclass 34, count 2 2006.286.04:38:59.05#ibcon#read 6, iclass 34, count 2 2006.286.04:38:59.05#ibcon#end of sib2, iclass 34, count 2 2006.286.04:38:59.05#ibcon#*after write, iclass 34, count 2 2006.286.04:38:59.05#ibcon#*before return 0, iclass 34, count 2 2006.286.04:38:59.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:38:59.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.04:38:59.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.04:38:59.05#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:59.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:38:59.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:38:59.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:38:59.18#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:38:59.18#ibcon#first serial, iclass 34, count 0 2006.286.04:38:59.18#ibcon#enter sib2, iclass 34, count 0 2006.286.04:38:59.18#ibcon#flushed, iclass 34, count 0 2006.286.04:38:59.18#ibcon#about to write, iclass 34, count 0 2006.286.04:38:59.18#ibcon#wrote, iclass 34, count 0 2006.286.04:38:59.18#ibcon#about to read 3, iclass 34, count 0 2006.286.04:38:59.20#ibcon#read 3, iclass 34, count 0 2006.286.04:38:59.20#ibcon#about to read 4, iclass 34, count 0 2006.286.04:38:59.20#ibcon#read 4, iclass 34, count 0 2006.286.04:38:59.20#ibcon#about to read 5, iclass 34, count 0 2006.286.04:38:59.20#ibcon#read 5, iclass 34, count 0 2006.286.04:38:59.20#ibcon#about to read 6, iclass 34, count 0 2006.286.04:38:59.20#ibcon#read 6, iclass 34, count 0 2006.286.04:38:59.20#ibcon#end of sib2, iclass 34, count 0 2006.286.04:38:59.20#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:38:59.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:38:59.20#ibcon#[27=USB\r\n] 2006.286.04:38:59.20#ibcon#*before write, iclass 34, count 0 2006.286.04:38:59.20#ibcon#enter sib2, iclass 34, count 0 2006.286.04:38:59.20#ibcon#flushed, iclass 34, count 0 2006.286.04:38:59.20#ibcon#about to write, iclass 34, count 0 2006.286.04:38:59.20#ibcon#wrote, iclass 34, count 0 2006.286.04:38:59.20#ibcon#about to read 3, iclass 34, count 0 2006.286.04:38:59.23#ibcon#read 3, iclass 34, count 0 2006.286.04:38:59.23#ibcon#about to read 4, iclass 34, count 0 2006.286.04:38:59.23#ibcon#read 4, iclass 34, count 0 2006.286.04:38:59.23#ibcon#about to read 5, iclass 34, count 0 2006.286.04:38:59.23#ibcon#read 5, iclass 34, count 0 2006.286.04:38:59.23#ibcon#about to read 6, iclass 34, count 0 2006.286.04:38:59.23#ibcon#read 6, iclass 34, count 0 2006.286.04:38:59.23#ibcon#end of sib2, iclass 34, count 0 2006.286.04:38:59.23#ibcon#*after write, iclass 34, count 0 2006.286.04:38:59.23#ibcon#*before return 0, iclass 34, count 0 2006.286.04:38:59.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:38:59.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.04:38:59.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:38:59.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:38:59.23$vck44/vblo=5,709.99 2006.286.04:38:59.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.04:38:59.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.04:38:59.23#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:59.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:38:59.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:38:59.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:38:59.23#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:38:59.23#ibcon#first serial, iclass 36, count 0 2006.286.04:38:59.23#ibcon#enter sib2, iclass 36, count 0 2006.286.04:38:59.23#ibcon#flushed, iclass 36, count 0 2006.286.04:38:59.23#ibcon#about to write, iclass 36, count 0 2006.286.04:38:59.23#ibcon#wrote, iclass 36, count 0 2006.286.04:38:59.23#ibcon#about to read 3, iclass 36, count 0 2006.286.04:38:59.25#ibcon#read 3, iclass 36, count 0 2006.286.04:38:59.25#ibcon#about to read 4, iclass 36, count 0 2006.286.04:38:59.25#ibcon#read 4, iclass 36, count 0 2006.286.04:38:59.25#ibcon#about to read 5, iclass 36, count 0 2006.286.04:38:59.25#ibcon#read 5, iclass 36, count 0 2006.286.04:38:59.25#ibcon#about to read 6, iclass 36, count 0 2006.286.04:38:59.25#ibcon#read 6, iclass 36, count 0 2006.286.04:38:59.25#ibcon#end of sib2, iclass 36, count 0 2006.286.04:38:59.25#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:38:59.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:38:59.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:38:59.25#ibcon#*before write, iclass 36, count 0 2006.286.04:38:59.25#ibcon#enter sib2, iclass 36, count 0 2006.286.04:38:59.25#ibcon#flushed, iclass 36, count 0 2006.286.04:38:59.25#ibcon#about to write, iclass 36, count 0 2006.286.04:38:59.25#ibcon#wrote, iclass 36, count 0 2006.286.04:38:59.25#ibcon#about to read 3, iclass 36, count 0 2006.286.04:38:59.29#ibcon#read 3, iclass 36, count 0 2006.286.04:38:59.29#ibcon#about to read 4, iclass 36, count 0 2006.286.04:38:59.29#ibcon#read 4, iclass 36, count 0 2006.286.04:38:59.29#ibcon#about to read 5, iclass 36, count 0 2006.286.04:38:59.29#ibcon#read 5, iclass 36, count 0 2006.286.04:38:59.29#ibcon#about to read 6, iclass 36, count 0 2006.286.04:38:59.29#ibcon#read 6, iclass 36, count 0 2006.286.04:38:59.29#ibcon#end of sib2, iclass 36, count 0 2006.286.04:38:59.29#ibcon#*after write, iclass 36, count 0 2006.286.04:38:59.29#ibcon#*before return 0, iclass 36, count 0 2006.286.04:38:59.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:38:59.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.04:38:59.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:38:59.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:38:59.29$vck44/vb=5,4 2006.286.04:38:59.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.04:38:59.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.04:38:59.29#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:59.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:38:59.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:38:59.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:38:59.35#ibcon#enter wrdev, iclass 38, count 2 2006.286.04:38:59.35#ibcon#first serial, iclass 38, count 2 2006.286.04:38:59.35#ibcon#enter sib2, iclass 38, count 2 2006.286.04:38:59.35#ibcon#flushed, iclass 38, count 2 2006.286.04:38:59.35#ibcon#about to write, iclass 38, count 2 2006.286.04:38:59.35#ibcon#wrote, iclass 38, count 2 2006.286.04:38:59.35#ibcon#about to read 3, iclass 38, count 2 2006.286.04:38:59.37#ibcon#read 3, iclass 38, count 2 2006.286.04:38:59.37#ibcon#about to read 4, iclass 38, count 2 2006.286.04:38:59.37#ibcon#read 4, iclass 38, count 2 2006.286.04:38:59.37#ibcon#about to read 5, iclass 38, count 2 2006.286.04:38:59.37#ibcon#read 5, iclass 38, count 2 2006.286.04:38:59.37#ibcon#about to read 6, iclass 38, count 2 2006.286.04:38:59.37#ibcon#read 6, iclass 38, count 2 2006.286.04:38:59.37#ibcon#end of sib2, iclass 38, count 2 2006.286.04:38:59.37#ibcon#*mode == 0, iclass 38, count 2 2006.286.04:38:59.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.04:38:59.37#ibcon#[27=AT05-04\r\n] 2006.286.04:38:59.37#ibcon#*before write, iclass 38, count 2 2006.286.04:38:59.37#ibcon#enter sib2, iclass 38, count 2 2006.286.04:38:59.37#ibcon#flushed, iclass 38, count 2 2006.286.04:38:59.37#ibcon#about to write, iclass 38, count 2 2006.286.04:38:59.37#ibcon#wrote, iclass 38, count 2 2006.286.04:38:59.37#ibcon#about to read 3, iclass 38, count 2 2006.286.04:38:59.40#ibcon#read 3, iclass 38, count 2 2006.286.04:38:59.40#ibcon#about to read 4, iclass 38, count 2 2006.286.04:38:59.40#ibcon#read 4, iclass 38, count 2 2006.286.04:38:59.40#ibcon#about to read 5, iclass 38, count 2 2006.286.04:38:59.40#ibcon#read 5, iclass 38, count 2 2006.286.04:38:59.40#ibcon#about to read 6, iclass 38, count 2 2006.286.04:38:59.40#ibcon#read 6, iclass 38, count 2 2006.286.04:38:59.40#ibcon#end of sib2, iclass 38, count 2 2006.286.04:38:59.40#ibcon#*after write, iclass 38, count 2 2006.286.04:38:59.40#ibcon#*before return 0, iclass 38, count 2 2006.286.04:38:59.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:38:59.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.04:38:59.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.04:38:59.40#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:59.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:38:59.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:38:59.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:38:59.52#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:38:59.52#ibcon#first serial, iclass 38, count 0 2006.286.04:38:59.52#ibcon#enter sib2, iclass 38, count 0 2006.286.04:38:59.52#ibcon#flushed, iclass 38, count 0 2006.286.04:38:59.52#ibcon#about to write, iclass 38, count 0 2006.286.04:38:59.52#ibcon#wrote, iclass 38, count 0 2006.286.04:38:59.52#ibcon#about to read 3, iclass 38, count 0 2006.286.04:38:59.54#ibcon#read 3, iclass 38, count 0 2006.286.04:38:59.54#ibcon#about to read 4, iclass 38, count 0 2006.286.04:38:59.54#ibcon#read 4, iclass 38, count 0 2006.286.04:38:59.54#ibcon#about to read 5, iclass 38, count 0 2006.286.04:38:59.54#ibcon#read 5, iclass 38, count 0 2006.286.04:38:59.54#ibcon#about to read 6, iclass 38, count 0 2006.286.04:38:59.54#ibcon#read 6, iclass 38, count 0 2006.286.04:38:59.54#ibcon#end of sib2, iclass 38, count 0 2006.286.04:38:59.54#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:38:59.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:38:59.54#ibcon#[27=USB\r\n] 2006.286.04:38:59.54#ibcon#*before write, iclass 38, count 0 2006.286.04:38:59.54#ibcon#enter sib2, iclass 38, count 0 2006.286.04:38:59.54#ibcon#flushed, iclass 38, count 0 2006.286.04:38:59.54#ibcon#about to write, iclass 38, count 0 2006.286.04:38:59.54#ibcon#wrote, iclass 38, count 0 2006.286.04:38:59.54#ibcon#about to read 3, iclass 38, count 0 2006.286.04:38:59.57#ibcon#read 3, iclass 38, count 0 2006.286.04:38:59.57#ibcon#about to read 4, iclass 38, count 0 2006.286.04:38:59.57#ibcon#read 4, iclass 38, count 0 2006.286.04:38:59.57#ibcon#about to read 5, iclass 38, count 0 2006.286.04:38:59.57#ibcon#read 5, iclass 38, count 0 2006.286.04:38:59.57#ibcon#about to read 6, iclass 38, count 0 2006.286.04:38:59.57#ibcon#read 6, iclass 38, count 0 2006.286.04:38:59.57#ibcon#end of sib2, iclass 38, count 0 2006.286.04:38:59.57#ibcon#*after write, iclass 38, count 0 2006.286.04:38:59.57#ibcon#*before return 0, iclass 38, count 0 2006.286.04:38:59.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:38:59.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.04:38:59.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:38:59.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:38:59.57$vck44/vblo=6,719.99 2006.286.04:38:59.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.04:38:59.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.04:38:59.57#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:59.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:38:59.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:38:59.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:38:59.57#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:38:59.57#ibcon#first serial, iclass 40, count 0 2006.286.04:38:59.57#ibcon#enter sib2, iclass 40, count 0 2006.286.04:38:59.57#ibcon#flushed, iclass 40, count 0 2006.286.04:38:59.57#ibcon#about to write, iclass 40, count 0 2006.286.04:38:59.57#ibcon#wrote, iclass 40, count 0 2006.286.04:38:59.57#ibcon#about to read 3, iclass 40, count 0 2006.286.04:38:59.59#ibcon#read 3, iclass 40, count 0 2006.286.04:38:59.59#ibcon#about to read 4, iclass 40, count 0 2006.286.04:38:59.59#ibcon#read 4, iclass 40, count 0 2006.286.04:38:59.59#ibcon#about to read 5, iclass 40, count 0 2006.286.04:38:59.59#ibcon#read 5, iclass 40, count 0 2006.286.04:38:59.59#ibcon#about to read 6, iclass 40, count 0 2006.286.04:38:59.59#ibcon#read 6, iclass 40, count 0 2006.286.04:38:59.59#ibcon#end of sib2, iclass 40, count 0 2006.286.04:38:59.59#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:38:59.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:38:59.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:38:59.59#ibcon#*before write, iclass 40, count 0 2006.286.04:38:59.59#ibcon#enter sib2, iclass 40, count 0 2006.286.04:38:59.59#ibcon#flushed, iclass 40, count 0 2006.286.04:38:59.59#ibcon#about to write, iclass 40, count 0 2006.286.04:38:59.59#ibcon#wrote, iclass 40, count 0 2006.286.04:38:59.59#ibcon#about to read 3, iclass 40, count 0 2006.286.04:38:59.63#ibcon#read 3, iclass 40, count 0 2006.286.04:38:59.63#ibcon#about to read 4, iclass 40, count 0 2006.286.04:38:59.63#ibcon#read 4, iclass 40, count 0 2006.286.04:38:59.63#ibcon#about to read 5, iclass 40, count 0 2006.286.04:38:59.63#ibcon#read 5, iclass 40, count 0 2006.286.04:38:59.63#ibcon#about to read 6, iclass 40, count 0 2006.286.04:38:59.63#ibcon#read 6, iclass 40, count 0 2006.286.04:38:59.63#ibcon#end of sib2, iclass 40, count 0 2006.286.04:38:59.63#ibcon#*after write, iclass 40, count 0 2006.286.04:38:59.63#ibcon#*before return 0, iclass 40, count 0 2006.286.04:38:59.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:38:59.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.04:38:59.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:38:59.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:38:59.63$vck44/vb=6,3 2006.286.04:38:59.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.04:38:59.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.04:38:59.63#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:59.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:38:59.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:38:59.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:38:59.69#ibcon#enter wrdev, iclass 4, count 2 2006.286.04:38:59.69#ibcon#first serial, iclass 4, count 2 2006.286.04:38:59.69#ibcon#enter sib2, iclass 4, count 2 2006.286.04:38:59.69#ibcon#flushed, iclass 4, count 2 2006.286.04:38:59.69#ibcon#about to write, iclass 4, count 2 2006.286.04:38:59.69#ibcon#wrote, iclass 4, count 2 2006.286.04:38:59.69#ibcon#about to read 3, iclass 4, count 2 2006.286.04:38:59.71#ibcon#read 3, iclass 4, count 2 2006.286.04:38:59.71#ibcon#about to read 4, iclass 4, count 2 2006.286.04:38:59.71#ibcon#read 4, iclass 4, count 2 2006.286.04:38:59.71#ibcon#about to read 5, iclass 4, count 2 2006.286.04:38:59.71#ibcon#read 5, iclass 4, count 2 2006.286.04:38:59.71#ibcon#about to read 6, iclass 4, count 2 2006.286.04:38:59.71#ibcon#read 6, iclass 4, count 2 2006.286.04:38:59.71#ibcon#end of sib2, iclass 4, count 2 2006.286.04:38:59.71#ibcon#*mode == 0, iclass 4, count 2 2006.286.04:38:59.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.04:38:59.71#ibcon#[27=AT06-03\r\n] 2006.286.04:38:59.71#ibcon#*before write, iclass 4, count 2 2006.286.04:38:59.71#ibcon#enter sib2, iclass 4, count 2 2006.286.04:38:59.71#ibcon#flushed, iclass 4, count 2 2006.286.04:38:59.71#ibcon#about to write, iclass 4, count 2 2006.286.04:38:59.71#ibcon#wrote, iclass 4, count 2 2006.286.04:38:59.71#ibcon#about to read 3, iclass 4, count 2 2006.286.04:38:59.74#ibcon#read 3, iclass 4, count 2 2006.286.04:38:59.74#ibcon#about to read 4, iclass 4, count 2 2006.286.04:38:59.74#ibcon#read 4, iclass 4, count 2 2006.286.04:38:59.74#ibcon#about to read 5, iclass 4, count 2 2006.286.04:38:59.74#ibcon#read 5, iclass 4, count 2 2006.286.04:38:59.74#ibcon#about to read 6, iclass 4, count 2 2006.286.04:38:59.74#ibcon#read 6, iclass 4, count 2 2006.286.04:38:59.74#ibcon#end of sib2, iclass 4, count 2 2006.286.04:38:59.74#ibcon#*after write, iclass 4, count 2 2006.286.04:38:59.74#ibcon#*before return 0, iclass 4, count 2 2006.286.04:38:59.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:38:59.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.04:38:59.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.04:38:59.74#ibcon#ireg 7 cls_cnt 0 2006.286.04:38:59.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:38:59.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:38:59.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:38:59.86#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:38:59.86#ibcon#first serial, iclass 4, count 0 2006.286.04:38:59.86#ibcon#enter sib2, iclass 4, count 0 2006.286.04:38:59.86#ibcon#flushed, iclass 4, count 0 2006.286.04:38:59.86#ibcon#about to write, iclass 4, count 0 2006.286.04:38:59.86#ibcon#wrote, iclass 4, count 0 2006.286.04:38:59.86#ibcon#about to read 3, iclass 4, count 0 2006.286.04:38:59.88#ibcon#read 3, iclass 4, count 0 2006.286.04:38:59.88#ibcon#about to read 4, iclass 4, count 0 2006.286.04:38:59.88#ibcon#read 4, iclass 4, count 0 2006.286.04:38:59.88#ibcon#about to read 5, iclass 4, count 0 2006.286.04:38:59.88#ibcon#read 5, iclass 4, count 0 2006.286.04:38:59.88#ibcon#about to read 6, iclass 4, count 0 2006.286.04:38:59.88#ibcon#read 6, iclass 4, count 0 2006.286.04:38:59.88#ibcon#end of sib2, iclass 4, count 0 2006.286.04:38:59.88#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:38:59.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:38:59.88#ibcon#[27=USB\r\n] 2006.286.04:38:59.88#ibcon#*before write, iclass 4, count 0 2006.286.04:38:59.88#ibcon#enter sib2, iclass 4, count 0 2006.286.04:38:59.88#ibcon#flushed, iclass 4, count 0 2006.286.04:38:59.88#ibcon#about to write, iclass 4, count 0 2006.286.04:38:59.88#ibcon#wrote, iclass 4, count 0 2006.286.04:38:59.88#ibcon#about to read 3, iclass 4, count 0 2006.286.04:38:59.91#ibcon#read 3, iclass 4, count 0 2006.286.04:38:59.91#ibcon#about to read 4, iclass 4, count 0 2006.286.04:38:59.91#ibcon#read 4, iclass 4, count 0 2006.286.04:38:59.91#ibcon#about to read 5, iclass 4, count 0 2006.286.04:38:59.91#ibcon#read 5, iclass 4, count 0 2006.286.04:38:59.91#ibcon#about to read 6, iclass 4, count 0 2006.286.04:38:59.91#ibcon#read 6, iclass 4, count 0 2006.286.04:38:59.91#ibcon#end of sib2, iclass 4, count 0 2006.286.04:38:59.91#ibcon#*after write, iclass 4, count 0 2006.286.04:38:59.91#ibcon#*before return 0, iclass 4, count 0 2006.286.04:38:59.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:38:59.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.04:38:59.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:38:59.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:38:59.91$vck44/vblo=7,734.99 2006.286.04:38:59.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.04:38:59.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.04:38:59.91#ibcon#ireg 17 cls_cnt 0 2006.286.04:38:59.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:38:59.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:38:59.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:38:59.91#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:38:59.91#ibcon#first serial, iclass 6, count 0 2006.286.04:38:59.91#ibcon#enter sib2, iclass 6, count 0 2006.286.04:38:59.91#ibcon#flushed, iclass 6, count 0 2006.286.04:38:59.91#ibcon#about to write, iclass 6, count 0 2006.286.04:38:59.91#ibcon#wrote, iclass 6, count 0 2006.286.04:38:59.91#ibcon#about to read 3, iclass 6, count 0 2006.286.04:38:59.93#ibcon#read 3, iclass 6, count 0 2006.286.04:38:59.93#ibcon#about to read 4, iclass 6, count 0 2006.286.04:38:59.93#ibcon#read 4, iclass 6, count 0 2006.286.04:38:59.93#ibcon#about to read 5, iclass 6, count 0 2006.286.04:38:59.93#ibcon#read 5, iclass 6, count 0 2006.286.04:38:59.93#ibcon#about to read 6, iclass 6, count 0 2006.286.04:38:59.93#ibcon#read 6, iclass 6, count 0 2006.286.04:38:59.93#ibcon#end of sib2, iclass 6, count 0 2006.286.04:38:59.93#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:38:59.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:38:59.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:38:59.93#ibcon#*before write, iclass 6, count 0 2006.286.04:38:59.93#ibcon#enter sib2, iclass 6, count 0 2006.286.04:38:59.93#ibcon#flushed, iclass 6, count 0 2006.286.04:38:59.93#ibcon#about to write, iclass 6, count 0 2006.286.04:38:59.93#ibcon#wrote, iclass 6, count 0 2006.286.04:38:59.93#ibcon#about to read 3, iclass 6, count 0 2006.286.04:38:59.97#ibcon#read 3, iclass 6, count 0 2006.286.04:38:59.97#ibcon#about to read 4, iclass 6, count 0 2006.286.04:38:59.97#ibcon#read 4, iclass 6, count 0 2006.286.04:38:59.97#ibcon#about to read 5, iclass 6, count 0 2006.286.04:38:59.97#ibcon#read 5, iclass 6, count 0 2006.286.04:38:59.97#ibcon#about to read 6, iclass 6, count 0 2006.286.04:38:59.97#ibcon#read 6, iclass 6, count 0 2006.286.04:38:59.97#ibcon#end of sib2, iclass 6, count 0 2006.286.04:38:59.97#ibcon#*after write, iclass 6, count 0 2006.286.04:38:59.97#ibcon#*before return 0, iclass 6, count 0 2006.286.04:38:59.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:38:59.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:38:59.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:38:59.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:38:59.97$vck44/vb=7,4 2006.286.04:38:59.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.04:38:59.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.04:38:59.97#ibcon#ireg 11 cls_cnt 2 2006.286.04:38:59.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:39:00.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:39:00.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:39:00.03#ibcon#enter wrdev, iclass 10, count 2 2006.286.04:39:00.03#ibcon#first serial, iclass 10, count 2 2006.286.04:39:00.03#ibcon#enter sib2, iclass 10, count 2 2006.286.04:39:00.03#ibcon#flushed, iclass 10, count 2 2006.286.04:39:00.03#ibcon#about to write, iclass 10, count 2 2006.286.04:39:00.03#ibcon#wrote, iclass 10, count 2 2006.286.04:39:00.03#ibcon#about to read 3, iclass 10, count 2 2006.286.04:39:00.05#ibcon#read 3, iclass 10, count 2 2006.286.04:39:00.05#ibcon#about to read 4, iclass 10, count 2 2006.286.04:39:00.05#ibcon#read 4, iclass 10, count 2 2006.286.04:39:00.05#ibcon#about to read 5, iclass 10, count 2 2006.286.04:39:00.05#ibcon#read 5, iclass 10, count 2 2006.286.04:39:00.05#ibcon#about to read 6, iclass 10, count 2 2006.286.04:39:00.05#ibcon#read 6, iclass 10, count 2 2006.286.04:39:00.05#ibcon#end of sib2, iclass 10, count 2 2006.286.04:39:00.05#ibcon#*mode == 0, iclass 10, count 2 2006.286.04:39:00.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.04:39:00.05#ibcon#[27=AT07-04\r\n] 2006.286.04:39:00.05#ibcon#*before write, iclass 10, count 2 2006.286.04:39:00.05#ibcon#enter sib2, iclass 10, count 2 2006.286.04:39:00.05#ibcon#flushed, iclass 10, count 2 2006.286.04:39:00.05#ibcon#about to write, iclass 10, count 2 2006.286.04:39:00.05#ibcon#wrote, iclass 10, count 2 2006.286.04:39:00.05#ibcon#about to read 3, iclass 10, count 2 2006.286.04:39:00.08#ibcon#read 3, iclass 10, count 2 2006.286.04:39:00.08#ibcon#about to read 4, iclass 10, count 2 2006.286.04:39:00.08#ibcon#read 4, iclass 10, count 2 2006.286.04:39:00.08#ibcon#about to read 5, iclass 10, count 2 2006.286.04:39:00.08#ibcon#read 5, iclass 10, count 2 2006.286.04:39:00.08#ibcon#about to read 6, iclass 10, count 2 2006.286.04:39:00.08#ibcon#read 6, iclass 10, count 2 2006.286.04:39:00.08#ibcon#end of sib2, iclass 10, count 2 2006.286.04:39:00.08#ibcon#*after write, iclass 10, count 2 2006.286.04:39:00.08#ibcon#*before return 0, iclass 10, count 2 2006.286.04:39:00.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:39:00.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.04:39:00.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.04:39:00.08#ibcon#ireg 7 cls_cnt 0 2006.286.04:39:00.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:39:00.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:39:00.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:39:00.21#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:39:00.21#ibcon#first serial, iclass 10, count 0 2006.286.04:39:00.21#ibcon#enter sib2, iclass 10, count 0 2006.286.04:39:00.21#ibcon#flushed, iclass 10, count 0 2006.286.04:39:00.21#ibcon#about to write, iclass 10, count 0 2006.286.04:39:00.21#ibcon#wrote, iclass 10, count 0 2006.286.04:39:00.21#ibcon#about to read 3, iclass 10, count 0 2006.286.04:39:00.23#ibcon#read 3, iclass 10, count 0 2006.286.04:39:00.23#ibcon#about to read 4, iclass 10, count 0 2006.286.04:39:00.23#ibcon#read 4, iclass 10, count 0 2006.286.04:39:00.23#ibcon#about to read 5, iclass 10, count 0 2006.286.04:39:00.23#ibcon#read 5, iclass 10, count 0 2006.286.04:39:00.23#ibcon#about to read 6, iclass 10, count 0 2006.286.04:39:00.23#ibcon#read 6, iclass 10, count 0 2006.286.04:39:00.23#ibcon#end of sib2, iclass 10, count 0 2006.286.04:39:00.23#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:39:00.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:39:00.23#ibcon#[27=USB\r\n] 2006.286.04:39:00.23#ibcon#*before write, iclass 10, count 0 2006.286.04:39:00.23#ibcon#enter sib2, iclass 10, count 0 2006.286.04:39:00.23#ibcon#flushed, iclass 10, count 0 2006.286.04:39:00.23#ibcon#about to write, iclass 10, count 0 2006.286.04:39:00.23#ibcon#wrote, iclass 10, count 0 2006.286.04:39:00.23#ibcon#about to read 3, iclass 10, count 0 2006.286.04:39:00.26#ibcon#read 3, iclass 10, count 0 2006.286.04:39:00.26#ibcon#about to read 4, iclass 10, count 0 2006.286.04:39:00.26#ibcon#read 4, iclass 10, count 0 2006.286.04:39:00.26#ibcon#about to read 5, iclass 10, count 0 2006.286.04:39:00.26#ibcon#read 5, iclass 10, count 0 2006.286.04:39:00.26#ibcon#about to read 6, iclass 10, count 0 2006.286.04:39:00.26#ibcon#read 6, iclass 10, count 0 2006.286.04:39:00.26#ibcon#end of sib2, iclass 10, count 0 2006.286.04:39:00.26#ibcon#*after write, iclass 10, count 0 2006.286.04:39:00.26#ibcon#*before return 0, iclass 10, count 0 2006.286.04:39:00.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:39:00.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.04:39:00.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:39:00.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:39:00.26$vck44/vblo=8,744.99 2006.286.04:39:00.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.04:39:00.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.04:39:00.26#ibcon#ireg 17 cls_cnt 0 2006.286.04:39:00.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:39:00.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:39:00.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:39:00.26#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:39:00.26#ibcon#first serial, iclass 12, count 0 2006.286.04:39:00.26#ibcon#enter sib2, iclass 12, count 0 2006.286.04:39:00.26#ibcon#flushed, iclass 12, count 0 2006.286.04:39:00.26#ibcon#about to write, iclass 12, count 0 2006.286.04:39:00.26#ibcon#wrote, iclass 12, count 0 2006.286.04:39:00.26#ibcon#about to read 3, iclass 12, count 0 2006.286.04:39:00.28#ibcon#read 3, iclass 12, count 0 2006.286.04:39:00.28#ibcon#about to read 4, iclass 12, count 0 2006.286.04:39:00.28#ibcon#read 4, iclass 12, count 0 2006.286.04:39:00.28#ibcon#about to read 5, iclass 12, count 0 2006.286.04:39:00.28#ibcon#read 5, iclass 12, count 0 2006.286.04:39:00.28#ibcon#about to read 6, iclass 12, count 0 2006.286.04:39:00.28#ibcon#read 6, iclass 12, count 0 2006.286.04:39:00.28#ibcon#end of sib2, iclass 12, count 0 2006.286.04:39:00.28#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:39:00.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:39:00.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:39:00.28#ibcon#*before write, iclass 12, count 0 2006.286.04:39:00.28#ibcon#enter sib2, iclass 12, count 0 2006.286.04:39:00.28#ibcon#flushed, iclass 12, count 0 2006.286.04:39:00.28#ibcon#about to write, iclass 12, count 0 2006.286.04:39:00.28#ibcon#wrote, iclass 12, count 0 2006.286.04:39:00.28#ibcon#about to read 3, iclass 12, count 0 2006.286.04:39:00.32#ibcon#read 3, iclass 12, count 0 2006.286.04:39:00.32#ibcon#about to read 4, iclass 12, count 0 2006.286.04:39:00.32#ibcon#read 4, iclass 12, count 0 2006.286.04:39:00.32#ibcon#about to read 5, iclass 12, count 0 2006.286.04:39:00.32#ibcon#read 5, iclass 12, count 0 2006.286.04:39:00.32#ibcon#about to read 6, iclass 12, count 0 2006.286.04:39:00.32#ibcon#read 6, iclass 12, count 0 2006.286.04:39:00.32#ibcon#end of sib2, iclass 12, count 0 2006.286.04:39:00.32#ibcon#*after write, iclass 12, count 0 2006.286.04:39:00.32#ibcon#*before return 0, iclass 12, count 0 2006.286.04:39:00.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:39:00.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:39:00.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:39:00.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:39:00.32$vck44/vb=8,4 2006.286.04:39:00.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.04:39:00.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.04:39:00.32#ibcon#ireg 11 cls_cnt 2 2006.286.04:39:00.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:39:00.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:39:00.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:39:00.38#ibcon#enter wrdev, iclass 14, count 2 2006.286.04:39:00.38#ibcon#first serial, iclass 14, count 2 2006.286.04:39:00.38#ibcon#enter sib2, iclass 14, count 2 2006.286.04:39:00.38#ibcon#flushed, iclass 14, count 2 2006.286.04:39:00.38#ibcon#about to write, iclass 14, count 2 2006.286.04:39:00.38#ibcon#wrote, iclass 14, count 2 2006.286.04:39:00.38#ibcon#about to read 3, iclass 14, count 2 2006.286.04:39:00.40#ibcon#read 3, iclass 14, count 2 2006.286.04:39:00.40#ibcon#about to read 4, iclass 14, count 2 2006.286.04:39:00.40#ibcon#read 4, iclass 14, count 2 2006.286.04:39:00.40#ibcon#about to read 5, iclass 14, count 2 2006.286.04:39:00.40#ibcon#read 5, iclass 14, count 2 2006.286.04:39:00.40#ibcon#about to read 6, iclass 14, count 2 2006.286.04:39:00.40#ibcon#read 6, iclass 14, count 2 2006.286.04:39:00.40#ibcon#end of sib2, iclass 14, count 2 2006.286.04:39:00.40#ibcon#*mode == 0, iclass 14, count 2 2006.286.04:39:00.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.04:39:00.40#ibcon#[27=AT08-04\r\n] 2006.286.04:39:00.40#ibcon#*before write, iclass 14, count 2 2006.286.04:39:00.40#ibcon#enter sib2, iclass 14, count 2 2006.286.04:39:00.40#ibcon#flushed, iclass 14, count 2 2006.286.04:39:00.40#ibcon#about to write, iclass 14, count 2 2006.286.04:39:00.40#ibcon#wrote, iclass 14, count 2 2006.286.04:39:00.40#ibcon#about to read 3, iclass 14, count 2 2006.286.04:39:00.43#ibcon#read 3, iclass 14, count 2 2006.286.04:39:00.43#ibcon#about to read 4, iclass 14, count 2 2006.286.04:39:00.43#ibcon#read 4, iclass 14, count 2 2006.286.04:39:00.43#ibcon#about to read 5, iclass 14, count 2 2006.286.04:39:00.43#ibcon#read 5, iclass 14, count 2 2006.286.04:39:00.43#ibcon#about to read 6, iclass 14, count 2 2006.286.04:39:00.43#ibcon#read 6, iclass 14, count 2 2006.286.04:39:00.43#ibcon#end of sib2, iclass 14, count 2 2006.286.04:39:00.43#ibcon#*after write, iclass 14, count 2 2006.286.04:39:00.43#ibcon#*before return 0, iclass 14, count 2 2006.286.04:39:00.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:39:00.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.04:39:00.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.04:39:00.43#ibcon#ireg 7 cls_cnt 0 2006.286.04:39:00.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:39:00.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:39:00.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:39:00.55#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:39:00.55#ibcon#first serial, iclass 14, count 0 2006.286.04:39:00.55#ibcon#enter sib2, iclass 14, count 0 2006.286.04:39:00.55#ibcon#flushed, iclass 14, count 0 2006.286.04:39:00.55#ibcon#about to write, iclass 14, count 0 2006.286.04:39:00.55#ibcon#wrote, iclass 14, count 0 2006.286.04:39:00.55#ibcon#about to read 3, iclass 14, count 0 2006.286.04:39:00.57#ibcon#read 3, iclass 14, count 0 2006.286.04:39:00.57#ibcon#about to read 4, iclass 14, count 0 2006.286.04:39:00.57#ibcon#read 4, iclass 14, count 0 2006.286.04:39:00.57#ibcon#about to read 5, iclass 14, count 0 2006.286.04:39:00.57#ibcon#read 5, iclass 14, count 0 2006.286.04:39:00.57#ibcon#about to read 6, iclass 14, count 0 2006.286.04:39:00.57#ibcon#read 6, iclass 14, count 0 2006.286.04:39:00.57#ibcon#end of sib2, iclass 14, count 0 2006.286.04:39:00.57#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:39:00.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:39:00.57#ibcon#[27=USB\r\n] 2006.286.04:39:00.57#ibcon#*before write, iclass 14, count 0 2006.286.04:39:00.57#ibcon#enter sib2, iclass 14, count 0 2006.286.04:39:00.57#ibcon#flushed, iclass 14, count 0 2006.286.04:39:00.57#ibcon#about to write, iclass 14, count 0 2006.286.04:39:00.57#ibcon#wrote, iclass 14, count 0 2006.286.04:39:00.57#ibcon#about to read 3, iclass 14, count 0 2006.286.04:39:00.58#abcon#<5=/04 3.8 7.5 22.18 751014.8\r\n> 2006.286.04:39:00.60#abcon#{5=INTERFACE CLEAR} 2006.286.04:39:00.60#ibcon#read 3, iclass 14, count 0 2006.286.04:39:00.60#ibcon#about to read 4, iclass 14, count 0 2006.286.04:39:00.60#ibcon#read 4, iclass 14, count 0 2006.286.04:39:00.60#ibcon#about to read 5, iclass 14, count 0 2006.286.04:39:00.60#ibcon#read 5, iclass 14, count 0 2006.286.04:39:00.60#ibcon#about to read 6, iclass 14, count 0 2006.286.04:39:00.60#ibcon#read 6, iclass 14, count 0 2006.286.04:39:00.60#ibcon#end of sib2, iclass 14, count 0 2006.286.04:39:00.60#ibcon#*after write, iclass 14, count 0 2006.286.04:39:00.60#ibcon#*before return 0, iclass 14, count 0 2006.286.04:39:00.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:39:00.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.04:39:00.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:39:00.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:39:00.60$vck44/vabw=wide 2006.286.04:39:00.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.04:39:00.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.04:39:00.60#ibcon#ireg 8 cls_cnt 0 2006.286.04:39:00.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:39:00.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:39:00.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:39:00.60#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:39:00.60#ibcon#first serial, iclass 19, count 0 2006.286.04:39:00.60#ibcon#enter sib2, iclass 19, count 0 2006.286.04:39:00.60#ibcon#flushed, iclass 19, count 0 2006.286.04:39:00.60#ibcon#about to write, iclass 19, count 0 2006.286.04:39:00.60#ibcon#wrote, iclass 19, count 0 2006.286.04:39:00.60#ibcon#about to read 3, iclass 19, count 0 2006.286.04:39:00.62#ibcon#read 3, iclass 19, count 0 2006.286.04:39:00.62#ibcon#about to read 4, iclass 19, count 0 2006.286.04:39:00.62#ibcon#read 4, iclass 19, count 0 2006.286.04:39:00.62#ibcon#about to read 5, iclass 19, count 0 2006.286.04:39:00.62#ibcon#read 5, iclass 19, count 0 2006.286.04:39:00.62#ibcon#about to read 6, iclass 19, count 0 2006.286.04:39:00.62#ibcon#read 6, iclass 19, count 0 2006.286.04:39:00.62#ibcon#end of sib2, iclass 19, count 0 2006.286.04:39:00.62#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:39:00.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:39:00.62#ibcon#[25=BW32\r\n] 2006.286.04:39:00.62#ibcon#*before write, iclass 19, count 0 2006.286.04:39:00.62#ibcon#enter sib2, iclass 19, count 0 2006.286.04:39:00.62#ibcon#flushed, iclass 19, count 0 2006.286.04:39:00.62#ibcon#about to write, iclass 19, count 0 2006.286.04:39:00.62#ibcon#wrote, iclass 19, count 0 2006.286.04:39:00.62#ibcon#about to read 3, iclass 19, count 0 2006.286.04:39:00.65#ibcon#read 3, iclass 19, count 0 2006.286.04:39:00.65#ibcon#about to read 4, iclass 19, count 0 2006.286.04:39:00.65#ibcon#read 4, iclass 19, count 0 2006.286.04:39:00.65#ibcon#about to read 5, iclass 19, count 0 2006.286.04:39:00.65#ibcon#read 5, iclass 19, count 0 2006.286.04:39:00.65#ibcon#about to read 6, iclass 19, count 0 2006.286.04:39:00.65#ibcon#read 6, iclass 19, count 0 2006.286.04:39:00.65#ibcon#end of sib2, iclass 19, count 0 2006.286.04:39:00.65#ibcon#*after write, iclass 19, count 0 2006.286.04:39:00.65#ibcon#*before return 0, iclass 19, count 0 2006.286.04:39:00.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:39:00.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:39:00.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:39:00.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:39:00.65$vck44/vbbw=wide 2006.286.04:39:00.65#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:39:00.65#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:39:00.65#ibcon#ireg 8 cls_cnt 0 2006.286.04:39:00.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:39:00.66#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:39:00.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:39:00.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:39:00.72#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:39:00.72#ibcon#first serial, iclass 22, count 0 2006.286.04:39:00.72#ibcon#enter sib2, iclass 22, count 0 2006.286.04:39:00.72#ibcon#flushed, iclass 22, count 0 2006.286.04:39:00.72#ibcon#about to write, iclass 22, count 0 2006.286.04:39:00.72#ibcon#wrote, iclass 22, count 0 2006.286.04:39:00.72#ibcon#about to read 3, iclass 22, count 0 2006.286.04:39:00.74#ibcon#read 3, iclass 22, count 0 2006.286.04:39:00.74#ibcon#about to read 4, iclass 22, count 0 2006.286.04:39:00.74#ibcon#read 4, iclass 22, count 0 2006.286.04:39:00.74#ibcon#about to read 5, iclass 22, count 0 2006.286.04:39:00.74#ibcon#read 5, iclass 22, count 0 2006.286.04:39:00.74#ibcon#about to read 6, iclass 22, count 0 2006.286.04:39:00.74#ibcon#read 6, iclass 22, count 0 2006.286.04:39:00.74#ibcon#end of sib2, iclass 22, count 0 2006.286.04:39:00.74#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:39:00.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:39:00.74#ibcon#[27=BW32\r\n] 2006.286.04:39:00.74#ibcon#*before write, iclass 22, count 0 2006.286.04:39:00.74#ibcon#enter sib2, iclass 22, count 0 2006.286.04:39:00.74#ibcon#flushed, iclass 22, count 0 2006.286.04:39:00.74#ibcon#about to write, iclass 22, count 0 2006.286.04:39:00.74#ibcon#wrote, iclass 22, count 0 2006.286.04:39:00.74#ibcon#about to read 3, iclass 22, count 0 2006.286.04:39:00.77#ibcon#read 3, iclass 22, count 0 2006.286.04:39:00.77#ibcon#about to read 4, iclass 22, count 0 2006.286.04:39:00.77#ibcon#read 4, iclass 22, count 0 2006.286.04:39:00.77#ibcon#about to read 5, iclass 22, count 0 2006.286.04:39:00.77#ibcon#read 5, iclass 22, count 0 2006.286.04:39:00.77#ibcon#about to read 6, iclass 22, count 0 2006.286.04:39:00.77#ibcon#read 6, iclass 22, count 0 2006.286.04:39:00.77#ibcon#end of sib2, iclass 22, count 0 2006.286.04:39:00.77#ibcon#*after write, iclass 22, count 0 2006.286.04:39:00.77#ibcon#*before return 0, iclass 22, count 0 2006.286.04:39:00.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:39:00.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:39:00.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:39:00.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:39:00.77$setupk4/ifdk4 2006.286.04:39:00.77$ifdk4/lo= 2006.286.04:39:00.77$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:39:00.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:39:00.77$ifdk4/patch= 2006.286.04:39:00.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:39:00.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:39:00.77$setupk4/!*+20s 2006.286.04:39:07.14#trakl#Source acquired 2006.286.04:39:09.14#flagr#flagr/antenna,acquired 2006.286.04:39:10.75#abcon#<5=/04 3.8 7.5 22.18 751014.8\r\n> 2006.286.04:39:10.77#abcon#{5=INTERFACE CLEAR} 2006.286.04:39:10.83#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:39:14.59$setupk4/"tpicd 2006.286.04:39:14.59$setupk4/echo=off 2006.286.04:39:14.59$setupk4/xlog=off 2006.286.04:39:14.59:!2006.286.04:41:59 2006.286.04:41:59.00:preob 2006.286.04:41:59.14/onsource/TRACKING 2006.286.04:41:59.14:!2006.286.04:42:09 2006.286.04:42:09.00:"tape 2006.286.04:42:09.00:"st=record 2006.286.04:42:09.00:data_valid=on 2006.286.04:42:09.00:midob 2006.286.04:42:09.14/onsource/TRACKING 2006.286.04:42:09.14/wx/22.20,1014.8,76 2006.286.04:42:09.31/cable/+6.4953E-03 2006.286.04:42:10.40/va/01,07,usb,yes,32,35 2006.286.04:42:10.40/va/02,06,usb,yes,32,33 2006.286.04:42:10.40/va/03,07,usb,yes,32,34 2006.286.04:42:10.40/va/04,06,usb,yes,33,35 2006.286.04:42:10.40/va/05,03,usb,yes,33,33 2006.286.04:42:10.40/va/06,04,usb,yes,30,29 2006.286.04:42:10.40/va/07,04,usb,yes,30,31 2006.286.04:42:10.40/va/08,03,usb,yes,31,38 2006.286.04:42:10.63/valo/01,524.99,yes,locked 2006.286.04:42:10.63/valo/02,534.99,yes,locked 2006.286.04:42:10.63/valo/03,564.99,yes,locked 2006.286.04:42:10.63/valo/04,624.99,yes,locked 2006.286.04:42:10.63/valo/05,734.99,yes,locked 2006.286.04:42:10.63/valo/06,814.99,yes,locked 2006.286.04:42:10.63/valo/07,864.99,yes,locked 2006.286.04:42:10.63/valo/08,884.99,yes,locked 2006.286.04:42:11.72/vb/01,04,usb,yes,31,28 2006.286.04:42:11.72/vb/02,05,usb,yes,29,29 2006.286.04:42:11.72/vb/03,04,usb,yes,30,33 2006.286.04:42:11.72/vb/04,05,usb,yes,30,29 2006.286.04:42:11.72/vb/05,04,usb,yes,27,29 2006.286.04:42:11.72/vb/06,03,usb,yes,38,34 2006.286.04:42:11.72/vb/07,04,usb,yes,31,31 2006.286.04:42:11.72/vb/08,04,usb,yes,28,32 2006.286.04:42:11.95/vblo/01,629.99,yes,locked 2006.286.04:42:11.95/vblo/02,634.99,yes,locked 2006.286.04:42:11.95/vblo/03,649.99,yes,locked 2006.286.04:42:11.95/vblo/04,679.99,yes,locked 2006.286.04:42:11.95/vblo/05,709.99,yes,locked 2006.286.04:42:11.95/vblo/06,719.99,yes,locked 2006.286.04:42:11.95/vblo/07,734.99,yes,locked 2006.286.04:42:11.95/vblo/08,744.99,yes,locked 2006.286.04:42:12.10/vabw/8 2006.286.04:42:12.25/vbbw/8 2006.286.04:42:12.34/xfe/off,on,12.2 2006.286.04:42:12.72/ifatt/23,28,28,28 2006.286.04:42:13.08/fmout-gps/S +2.53E-07 2006.286.04:42:13.10:!2006.286.04:42:49 2006.286.04:42:49.01:data_valid=off 2006.286.04:42:49.01:"et 2006.286.04:42:49.01:!+3s 2006.286.04:42:52.02:"tape 2006.286.04:42:52.02:postob 2006.286.04:42:52.11/cable/+6.4947E-03 2006.286.04:42:52.11/wx/22.20,1014.8,77 2006.286.04:42:52.17/fmout-gps/S +2.52E-07 2006.286.04:42:52.17:scan_name=286-0444,jd0610,50 2006.286.04:42:52.17:source=1611+343,161341.06,341247.9,2000.0,cw 2006.286.04:42:54.14#flagr#flagr/antenna,new-source 2006.286.04:42:54.14:checkk5 2006.286.04:42:54.64/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:42:55.04/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:42:55.45/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:42:55.82/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:42:56.18/chk_obsdata//k5ts1/T2860442??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:42:56.65/chk_obsdata//k5ts2/T2860442??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:42:56.99/chk_obsdata//k5ts3/T2860442??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:42:57.40/chk_obsdata//k5ts4/T2860442??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.286.04:42:58.21/k5log//k5ts1_log_newline 2006.286.04:42:59.07/k5log//k5ts2_log_newline 2006.286.04:42:59.89/k5log//k5ts3_log_newline 2006.286.04:43:00.78/k5log//k5ts4_log_newline 2006.286.04:43:00.80/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:43:00.80:setupk4=1 2006.286.04:43:00.80$setupk4/echo=on 2006.286.04:43:00.80$setupk4/pcalon 2006.286.04:43:00.80$pcalon/"no phase cal control is implemented here 2006.286.04:43:00.80$setupk4/"tpicd=stop 2006.286.04:43:00.80$setupk4/"rec=synch_on 2006.286.04:43:00.80$setupk4/"rec_mode=128 2006.286.04:43:00.80$setupk4/!* 2006.286.04:43:00.80$setupk4/recpk4 2006.286.04:43:00.80$recpk4/recpatch= 2006.286.04:43:00.80$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:43:00.81$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:43:00.81$setupk4/vck44 2006.286.04:43:00.81$vck44/valo=1,524.99 2006.286.04:43:00.81#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.04:43:00.81#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.04:43:00.81#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:00.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:43:00.81#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:43:00.81#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:43:00.81#ibcon#enter wrdev, iclass 11, count 0 2006.286.04:43:00.81#ibcon#first serial, iclass 11, count 0 2006.286.04:43:00.81#ibcon#enter sib2, iclass 11, count 0 2006.286.04:43:00.81#ibcon#flushed, iclass 11, count 0 2006.286.04:43:00.81#ibcon#about to write, iclass 11, count 0 2006.286.04:43:00.81#ibcon#wrote, iclass 11, count 0 2006.286.04:43:00.81#ibcon#about to read 3, iclass 11, count 0 2006.286.04:43:00.82#ibcon#read 3, iclass 11, count 0 2006.286.04:43:00.82#ibcon#about to read 4, iclass 11, count 0 2006.286.04:43:00.82#ibcon#read 4, iclass 11, count 0 2006.286.04:43:00.82#ibcon#about to read 5, iclass 11, count 0 2006.286.04:43:00.82#ibcon#read 5, iclass 11, count 0 2006.286.04:43:00.82#ibcon#about to read 6, iclass 11, count 0 2006.286.04:43:00.82#ibcon#read 6, iclass 11, count 0 2006.286.04:43:00.82#ibcon#end of sib2, iclass 11, count 0 2006.286.04:43:00.82#ibcon#*mode == 0, iclass 11, count 0 2006.286.04:43:00.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.04:43:00.82#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:43:00.82#ibcon#*before write, iclass 11, count 0 2006.286.04:43:00.82#ibcon#enter sib2, iclass 11, count 0 2006.286.04:43:00.82#ibcon#flushed, iclass 11, count 0 2006.286.04:43:00.82#ibcon#about to write, iclass 11, count 0 2006.286.04:43:00.82#ibcon#wrote, iclass 11, count 0 2006.286.04:43:00.82#ibcon#about to read 3, iclass 11, count 0 2006.286.04:43:00.87#ibcon#read 3, iclass 11, count 0 2006.286.04:43:00.87#ibcon#about to read 4, iclass 11, count 0 2006.286.04:43:00.87#ibcon#read 4, iclass 11, count 0 2006.286.04:43:00.87#ibcon#about to read 5, iclass 11, count 0 2006.286.04:43:00.87#ibcon#read 5, iclass 11, count 0 2006.286.04:43:00.87#ibcon#about to read 6, iclass 11, count 0 2006.286.04:43:00.87#ibcon#read 6, iclass 11, count 0 2006.286.04:43:00.87#ibcon#end of sib2, iclass 11, count 0 2006.286.04:43:00.87#ibcon#*after write, iclass 11, count 0 2006.286.04:43:00.87#ibcon#*before return 0, iclass 11, count 0 2006.286.04:43:00.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:43:00.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:43:00.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.04:43:00.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.04:43:00.87$vck44/va=1,7 2006.286.04:43:00.87#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.04:43:00.87#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.04:43:00.87#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:00.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:43:00.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:43:00.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:43:00.87#ibcon#enter wrdev, iclass 13, count 2 2006.286.04:43:00.87#ibcon#first serial, iclass 13, count 2 2006.286.04:43:00.87#ibcon#enter sib2, iclass 13, count 2 2006.286.04:43:00.87#ibcon#flushed, iclass 13, count 2 2006.286.04:43:00.87#ibcon#about to write, iclass 13, count 2 2006.286.04:43:00.87#ibcon#wrote, iclass 13, count 2 2006.286.04:43:00.87#ibcon#about to read 3, iclass 13, count 2 2006.286.04:43:00.89#ibcon#read 3, iclass 13, count 2 2006.286.04:43:00.89#ibcon#about to read 4, iclass 13, count 2 2006.286.04:43:00.89#ibcon#read 4, iclass 13, count 2 2006.286.04:43:00.89#ibcon#about to read 5, iclass 13, count 2 2006.286.04:43:00.89#ibcon#read 5, iclass 13, count 2 2006.286.04:43:00.89#ibcon#about to read 6, iclass 13, count 2 2006.286.04:43:00.89#ibcon#read 6, iclass 13, count 2 2006.286.04:43:00.89#ibcon#end of sib2, iclass 13, count 2 2006.286.04:43:00.89#ibcon#*mode == 0, iclass 13, count 2 2006.286.04:43:00.89#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.04:43:00.89#ibcon#[25=AT01-07\r\n] 2006.286.04:43:00.89#ibcon#*before write, iclass 13, count 2 2006.286.04:43:00.89#ibcon#enter sib2, iclass 13, count 2 2006.286.04:43:00.89#ibcon#flushed, iclass 13, count 2 2006.286.04:43:00.89#ibcon#about to write, iclass 13, count 2 2006.286.04:43:00.89#ibcon#wrote, iclass 13, count 2 2006.286.04:43:00.89#ibcon#about to read 3, iclass 13, count 2 2006.286.04:43:00.92#ibcon#read 3, iclass 13, count 2 2006.286.04:43:00.92#ibcon#about to read 4, iclass 13, count 2 2006.286.04:43:00.92#ibcon#read 4, iclass 13, count 2 2006.286.04:43:00.92#ibcon#about to read 5, iclass 13, count 2 2006.286.04:43:00.92#ibcon#read 5, iclass 13, count 2 2006.286.04:43:00.92#ibcon#about to read 6, iclass 13, count 2 2006.286.04:43:00.92#ibcon#read 6, iclass 13, count 2 2006.286.04:43:00.92#ibcon#end of sib2, iclass 13, count 2 2006.286.04:43:00.92#ibcon#*after write, iclass 13, count 2 2006.286.04:43:00.92#ibcon#*before return 0, iclass 13, count 2 2006.286.04:43:00.92#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:43:00.92#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:43:00.92#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.04:43:00.92#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:00.92#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:43:01.04#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:43:01.04#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:43:01.04#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:43:01.04#ibcon#first serial, iclass 13, count 0 2006.286.04:43:01.04#ibcon#enter sib2, iclass 13, count 0 2006.286.04:43:01.04#ibcon#flushed, iclass 13, count 0 2006.286.04:43:01.04#ibcon#about to write, iclass 13, count 0 2006.286.04:43:01.04#ibcon#wrote, iclass 13, count 0 2006.286.04:43:01.04#ibcon#about to read 3, iclass 13, count 0 2006.286.04:43:01.06#ibcon#read 3, iclass 13, count 0 2006.286.04:43:01.06#ibcon#about to read 4, iclass 13, count 0 2006.286.04:43:01.06#ibcon#read 4, iclass 13, count 0 2006.286.04:43:01.06#ibcon#about to read 5, iclass 13, count 0 2006.286.04:43:01.06#ibcon#read 5, iclass 13, count 0 2006.286.04:43:01.06#ibcon#about to read 6, iclass 13, count 0 2006.286.04:43:01.06#ibcon#read 6, iclass 13, count 0 2006.286.04:43:01.06#ibcon#end of sib2, iclass 13, count 0 2006.286.04:43:01.06#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:43:01.06#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:43:01.06#ibcon#[25=USB\r\n] 2006.286.04:43:01.06#ibcon#*before write, iclass 13, count 0 2006.286.04:43:01.06#ibcon#enter sib2, iclass 13, count 0 2006.286.04:43:01.06#ibcon#flushed, iclass 13, count 0 2006.286.04:43:01.06#ibcon#about to write, iclass 13, count 0 2006.286.04:43:01.06#ibcon#wrote, iclass 13, count 0 2006.286.04:43:01.06#ibcon#about to read 3, iclass 13, count 0 2006.286.04:43:01.09#ibcon#read 3, iclass 13, count 0 2006.286.04:43:01.09#ibcon#about to read 4, iclass 13, count 0 2006.286.04:43:01.09#ibcon#read 4, iclass 13, count 0 2006.286.04:43:01.09#ibcon#about to read 5, iclass 13, count 0 2006.286.04:43:01.09#ibcon#read 5, iclass 13, count 0 2006.286.04:43:01.09#ibcon#about to read 6, iclass 13, count 0 2006.286.04:43:01.09#ibcon#read 6, iclass 13, count 0 2006.286.04:43:01.09#ibcon#end of sib2, iclass 13, count 0 2006.286.04:43:01.09#ibcon#*after write, iclass 13, count 0 2006.286.04:43:01.09#ibcon#*before return 0, iclass 13, count 0 2006.286.04:43:01.09#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:43:01.09#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:43:01.09#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:43:01.09#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:43:01.09$vck44/valo=2,534.99 2006.286.04:43:01.09#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.04:43:01.09#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.04:43:01.09#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:01.09#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:43:01.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:43:01.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:43:01.09#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:43:01.09#ibcon#first serial, iclass 15, count 0 2006.286.04:43:01.09#ibcon#enter sib2, iclass 15, count 0 2006.286.04:43:01.09#ibcon#flushed, iclass 15, count 0 2006.286.04:43:01.09#ibcon#about to write, iclass 15, count 0 2006.286.04:43:01.09#ibcon#wrote, iclass 15, count 0 2006.286.04:43:01.09#ibcon#about to read 3, iclass 15, count 0 2006.286.04:43:01.11#ibcon#read 3, iclass 15, count 0 2006.286.04:43:01.11#ibcon#about to read 4, iclass 15, count 0 2006.286.04:43:01.11#ibcon#read 4, iclass 15, count 0 2006.286.04:43:01.11#ibcon#about to read 5, iclass 15, count 0 2006.286.04:43:01.11#ibcon#read 5, iclass 15, count 0 2006.286.04:43:01.11#ibcon#about to read 6, iclass 15, count 0 2006.286.04:43:01.11#ibcon#read 6, iclass 15, count 0 2006.286.04:43:01.11#ibcon#end of sib2, iclass 15, count 0 2006.286.04:43:01.11#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:43:01.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:43:01.11#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:43:01.11#ibcon#*before write, iclass 15, count 0 2006.286.04:43:01.11#ibcon#enter sib2, iclass 15, count 0 2006.286.04:43:01.11#ibcon#flushed, iclass 15, count 0 2006.286.04:43:01.11#ibcon#about to write, iclass 15, count 0 2006.286.04:43:01.11#ibcon#wrote, iclass 15, count 0 2006.286.04:43:01.11#ibcon#about to read 3, iclass 15, count 0 2006.286.04:43:01.15#ibcon#read 3, iclass 15, count 0 2006.286.04:43:01.15#ibcon#about to read 4, iclass 15, count 0 2006.286.04:43:01.15#ibcon#read 4, iclass 15, count 0 2006.286.04:43:01.15#ibcon#about to read 5, iclass 15, count 0 2006.286.04:43:01.15#ibcon#read 5, iclass 15, count 0 2006.286.04:43:01.15#ibcon#about to read 6, iclass 15, count 0 2006.286.04:43:01.15#ibcon#read 6, iclass 15, count 0 2006.286.04:43:01.15#ibcon#end of sib2, iclass 15, count 0 2006.286.04:43:01.15#ibcon#*after write, iclass 15, count 0 2006.286.04:43:01.15#ibcon#*before return 0, iclass 15, count 0 2006.286.04:43:01.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:43:01.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:43:01.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:43:01.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:43:01.15$vck44/va=2,6 2006.286.04:43:01.15#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.04:43:01.15#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.04:43:01.15#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:01.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:43:01.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:43:01.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:43:01.21#ibcon#enter wrdev, iclass 17, count 2 2006.286.04:43:01.21#ibcon#first serial, iclass 17, count 2 2006.286.04:43:01.21#ibcon#enter sib2, iclass 17, count 2 2006.286.04:43:01.21#ibcon#flushed, iclass 17, count 2 2006.286.04:43:01.21#ibcon#about to write, iclass 17, count 2 2006.286.04:43:01.21#ibcon#wrote, iclass 17, count 2 2006.286.04:43:01.21#ibcon#about to read 3, iclass 17, count 2 2006.286.04:43:01.23#ibcon#read 3, iclass 17, count 2 2006.286.04:43:01.23#ibcon#about to read 4, iclass 17, count 2 2006.286.04:43:01.23#ibcon#read 4, iclass 17, count 2 2006.286.04:43:01.23#ibcon#about to read 5, iclass 17, count 2 2006.286.04:43:01.23#ibcon#read 5, iclass 17, count 2 2006.286.04:43:01.23#ibcon#about to read 6, iclass 17, count 2 2006.286.04:43:01.23#ibcon#read 6, iclass 17, count 2 2006.286.04:43:01.23#ibcon#end of sib2, iclass 17, count 2 2006.286.04:43:01.23#ibcon#*mode == 0, iclass 17, count 2 2006.286.04:43:01.23#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.04:43:01.23#ibcon#[25=AT02-06\r\n] 2006.286.04:43:01.23#ibcon#*before write, iclass 17, count 2 2006.286.04:43:01.23#ibcon#enter sib2, iclass 17, count 2 2006.286.04:43:01.23#ibcon#flushed, iclass 17, count 2 2006.286.04:43:01.23#ibcon#about to write, iclass 17, count 2 2006.286.04:43:01.23#ibcon#wrote, iclass 17, count 2 2006.286.04:43:01.23#ibcon#about to read 3, iclass 17, count 2 2006.286.04:43:01.26#ibcon#read 3, iclass 17, count 2 2006.286.04:43:01.26#ibcon#about to read 4, iclass 17, count 2 2006.286.04:43:01.26#ibcon#read 4, iclass 17, count 2 2006.286.04:43:01.26#ibcon#about to read 5, iclass 17, count 2 2006.286.04:43:01.26#ibcon#read 5, iclass 17, count 2 2006.286.04:43:01.26#ibcon#about to read 6, iclass 17, count 2 2006.286.04:43:01.26#ibcon#read 6, iclass 17, count 2 2006.286.04:43:01.26#ibcon#end of sib2, iclass 17, count 2 2006.286.04:43:01.26#ibcon#*after write, iclass 17, count 2 2006.286.04:43:01.26#ibcon#*before return 0, iclass 17, count 2 2006.286.04:43:01.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:43:01.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:43:01.26#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.04:43:01.26#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:01.26#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:43:01.38#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:43:01.38#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:43:01.38#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:43:01.38#ibcon#first serial, iclass 17, count 0 2006.286.04:43:01.38#ibcon#enter sib2, iclass 17, count 0 2006.286.04:43:01.38#ibcon#flushed, iclass 17, count 0 2006.286.04:43:01.38#ibcon#about to write, iclass 17, count 0 2006.286.04:43:01.38#ibcon#wrote, iclass 17, count 0 2006.286.04:43:01.38#ibcon#about to read 3, iclass 17, count 0 2006.286.04:43:01.40#ibcon#read 3, iclass 17, count 0 2006.286.04:43:01.40#ibcon#about to read 4, iclass 17, count 0 2006.286.04:43:01.40#ibcon#read 4, iclass 17, count 0 2006.286.04:43:01.40#ibcon#about to read 5, iclass 17, count 0 2006.286.04:43:01.40#ibcon#read 5, iclass 17, count 0 2006.286.04:43:01.40#ibcon#about to read 6, iclass 17, count 0 2006.286.04:43:01.40#ibcon#read 6, iclass 17, count 0 2006.286.04:43:01.40#ibcon#end of sib2, iclass 17, count 0 2006.286.04:43:01.40#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:43:01.40#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:43:01.40#ibcon#[25=USB\r\n] 2006.286.04:43:01.40#ibcon#*before write, iclass 17, count 0 2006.286.04:43:01.40#ibcon#enter sib2, iclass 17, count 0 2006.286.04:43:01.40#ibcon#flushed, iclass 17, count 0 2006.286.04:43:01.40#ibcon#about to write, iclass 17, count 0 2006.286.04:43:01.40#ibcon#wrote, iclass 17, count 0 2006.286.04:43:01.40#ibcon#about to read 3, iclass 17, count 0 2006.286.04:43:01.43#ibcon#read 3, iclass 17, count 0 2006.286.04:43:01.43#ibcon#about to read 4, iclass 17, count 0 2006.286.04:43:01.43#ibcon#read 4, iclass 17, count 0 2006.286.04:43:01.43#ibcon#about to read 5, iclass 17, count 0 2006.286.04:43:01.43#ibcon#read 5, iclass 17, count 0 2006.286.04:43:01.43#ibcon#about to read 6, iclass 17, count 0 2006.286.04:43:01.43#ibcon#read 6, iclass 17, count 0 2006.286.04:43:01.43#ibcon#end of sib2, iclass 17, count 0 2006.286.04:43:01.43#ibcon#*after write, iclass 17, count 0 2006.286.04:43:01.43#ibcon#*before return 0, iclass 17, count 0 2006.286.04:43:01.43#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:43:01.43#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:43:01.43#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:43:01.43#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:43:01.43$vck44/valo=3,564.99 2006.286.04:43:01.43#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.04:43:01.43#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.04:43:01.43#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:01.43#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:43:01.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:43:01.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:43:01.43#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:43:01.43#ibcon#first serial, iclass 19, count 0 2006.286.04:43:01.43#ibcon#enter sib2, iclass 19, count 0 2006.286.04:43:01.43#ibcon#flushed, iclass 19, count 0 2006.286.04:43:01.43#ibcon#about to write, iclass 19, count 0 2006.286.04:43:01.43#ibcon#wrote, iclass 19, count 0 2006.286.04:43:01.43#ibcon#about to read 3, iclass 19, count 0 2006.286.04:43:01.83#ibcon#read 3, iclass 19, count 0 2006.286.04:43:01.83#ibcon#about to read 4, iclass 19, count 0 2006.286.04:43:01.83#ibcon#read 4, iclass 19, count 0 2006.286.04:43:01.83#ibcon#about to read 5, iclass 19, count 0 2006.286.04:43:01.83#ibcon#read 5, iclass 19, count 0 2006.286.04:43:01.83#ibcon#about to read 6, iclass 19, count 0 2006.286.04:43:01.83#ibcon#read 6, iclass 19, count 0 2006.286.04:43:01.83#ibcon#end of sib2, iclass 19, count 0 2006.286.04:43:01.83#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:43:01.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:43:01.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:43:01.83#ibcon#*before write, iclass 19, count 0 2006.286.04:43:01.83#ibcon#enter sib2, iclass 19, count 0 2006.286.04:43:01.83#ibcon#flushed, iclass 19, count 0 2006.286.04:43:01.83#ibcon#about to write, iclass 19, count 0 2006.286.04:43:01.83#ibcon#wrote, iclass 19, count 0 2006.286.04:43:01.83#ibcon#about to read 3, iclass 19, count 0 2006.286.04:43:01.87#ibcon#read 3, iclass 19, count 0 2006.286.04:43:01.87#ibcon#about to read 4, iclass 19, count 0 2006.286.04:43:01.87#ibcon#read 4, iclass 19, count 0 2006.286.04:43:01.87#ibcon#about to read 5, iclass 19, count 0 2006.286.04:43:01.87#ibcon#read 5, iclass 19, count 0 2006.286.04:43:01.87#ibcon#about to read 6, iclass 19, count 0 2006.286.04:43:01.87#ibcon#read 6, iclass 19, count 0 2006.286.04:43:01.87#ibcon#end of sib2, iclass 19, count 0 2006.286.04:43:01.87#ibcon#*after write, iclass 19, count 0 2006.286.04:43:01.87#ibcon#*before return 0, iclass 19, count 0 2006.286.04:43:01.87#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:43:01.87#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:43:01.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:43:01.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:43:01.87$vck44/va=3,7 2006.286.04:43:01.87#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.04:43:01.87#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.04:43:01.87#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:01.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:43:01.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:43:01.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:43:01.87#ibcon#enter wrdev, iclass 21, count 2 2006.286.04:43:01.87#ibcon#first serial, iclass 21, count 2 2006.286.04:43:01.87#ibcon#enter sib2, iclass 21, count 2 2006.286.04:43:01.87#ibcon#flushed, iclass 21, count 2 2006.286.04:43:01.87#ibcon#about to write, iclass 21, count 2 2006.286.04:43:01.87#ibcon#wrote, iclass 21, count 2 2006.286.04:43:01.87#ibcon#about to read 3, iclass 21, count 2 2006.286.04:43:01.89#ibcon#read 3, iclass 21, count 2 2006.286.04:43:01.89#ibcon#about to read 4, iclass 21, count 2 2006.286.04:43:01.89#ibcon#read 4, iclass 21, count 2 2006.286.04:43:01.89#ibcon#about to read 5, iclass 21, count 2 2006.286.04:43:01.89#ibcon#read 5, iclass 21, count 2 2006.286.04:43:01.89#ibcon#about to read 6, iclass 21, count 2 2006.286.04:43:01.89#ibcon#read 6, iclass 21, count 2 2006.286.04:43:01.89#ibcon#end of sib2, iclass 21, count 2 2006.286.04:43:01.89#ibcon#*mode == 0, iclass 21, count 2 2006.286.04:43:01.89#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.04:43:01.89#ibcon#[25=AT03-07\r\n] 2006.286.04:43:01.89#ibcon#*before write, iclass 21, count 2 2006.286.04:43:01.89#ibcon#enter sib2, iclass 21, count 2 2006.286.04:43:01.89#ibcon#flushed, iclass 21, count 2 2006.286.04:43:01.89#ibcon#about to write, iclass 21, count 2 2006.286.04:43:01.89#ibcon#wrote, iclass 21, count 2 2006.286.04:43:01.89#ibcon#about to read 3, iclass 21, count 2 2006.286.04:43:01.92#ibcon#read 3, iclass 21, count 2 2006.286.04:43:01.92#ibcon#about to read 4, iclass 21, count 2 2006.286.04:43:01.92#ibcon#read 4, iclass 21, count 2 2006.286.04:43:01.92#ibcon#about to read 5, iclass 21, count 2 2006.286.04:43:01.92#ibcon#read 5, iclass 21, count 2 2006.286.04:43:01.92#ibcon#about to read 6, iclass 21, count 2 2006.286.04:43:01.92#ibcon#read 6, iclass 21, count 2 2006.286.04:43:01.92#ibcon#end of sib2, iclass 21, count 2 2006.286.04:43:01.92#ibcon#*after write, iclass 21, count 2 2006.286.04:43:01.92#ibcon#*before return 0, iclass 21, count 2 2006.286.04:43:01.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:43:01.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:43:01.92#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.04:43:01.92#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:01.92#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:43:02.04#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:43:02.04#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:43:02.04#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:43:02.04#ibcon#first serial, iclass 21, count 0 2006.286.04:43:02.04#ibcon#enter sib2, iclass 21, count 0 2006.286.04:43:02.04#ibcon#flushed, iclass 21, count 0 2006.286.04:43:02.04#ibcon#about to write, iclass 21, count 0 2006.286.04:43:02.04#ibcon#wrote, iclass 21, count 0 2006.286.04:43:02.04#ibcon#about to read 3, iclass 21, count 0 2006.286.04:43:02.06#ibcon#read 3, iclass 21, count 0 2006.286.04:43:02.06#ibcon#about to read 4, iclass 21, count 0 2006.286.04:43:02.06#ibcon#read 4, iclass 21, count 0 2006.286.04:43:02.06#ibcon#about to read 5, iclass 21, count 0 2006.286.04:43:02.06#ibcon#read 5, iclass 21, count 0 2006.286.04:43:02.06#ibcon#about to read 6, iclass 21, count 0 2006.286.04:43:02.06#ibcon#read 6, iclass 21, count 0 2006.286.04:43:02.06#ibcon#end of sib2, iclass 21, count 0 2006.286.04:43:02.06#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:43:02.06#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:43:02.06#ibcon#[25=USB\r\n] 2006.286.04:43:02.06#ibcon#*before write, iclass 21, count 0 2006.286.04:43:02.06#ibcon#enter sib2, iclass 21, count 0 2006.286.04:43:02.06#ibcon#flushed, iclass 21, count 0 2006.286.04:43:02.06#ibcon#about to write, iclass 21, count 0 2006.286.04:43:02.06#ibcon#wrote, iclass 21, count 0 2006.286.04:43:02.06#ibcon#about to read 3, iclass 21, count 0 2006.286.04:43:02.09#ibcon#read 3, iclass 21, count 0 2006.286.04:43:02.09#ibcon#about to read 4, iclass 21, count 0 2006.286.04:43:02.09#ibcon#read 4, iclass 21, count 0 2006.286.04:43:02.09#ibcon#about to read 5, iclass 21, count 0 2006.286.04:43:02.09#ibcon#read 5, iclass 21, count 0 2006.286.04:43:02.09#ibcon#about to read 6, iclass 21, count 0 2006.286.04:43:02.09#ibcon#read 6, iclass 21, count 0 2006.286.04:43:02.09#ibcon#end of sib2, iclass 21, count 0 2006.286.04:43:02.09#ibcon#*after write, iclass 21, count 0 2006.286.04:43:02.09#ibcon#*before return 0, iclass 21, count 0 2006.286.04:43:02.09#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:43:02.09#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:43:02.09#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:43:02.09#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:43:02.09$vck44/valo=4,624.99 2006.286.04:43:02.09#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.04:43:02.09#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.04:43:02.09#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:02.09#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:43:02.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:43:02.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:43:02.09#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:43:02.09#ibcon#first serial, iclass 23, count 0 2006.286.04:43:02.09#ibcon#enter sib2, iclass 23, count 0 2006.286.04:43:02.09#ibcon#flushed, iclass 23, count 0 2006.286.04:43:02.09#ibcon#about to write, iclass 23, count 0 2006.286.04:43:02.09#ibcon#wrote, iclass 23, count 0 2006.286.04:43:02.09#ibcon#about to read 3, iclass 23, count 0 2006.286.04:43:02.26#ibcon#read 3, iclass 23, count 0 2006.286.04:43:02.26#ibcon#about to read 4, iclass 23, count 0 2006.286.04:43:02.26#ibcon#read 4, iclass 23, count 0 2006.286.04:43:02.26#ibcon#about to read 5, iclass 23, count 0 2006.286.04:43:02.26#ibcon#read 5, iclass 23, count 0 2006.286.04:43:02.26#ibcon#about to read 6, iclass 23, count 0 2006.286.04:43:02.26#ibcon#read 6, iclass 23, count 0 2006.286.04:43:02.26#ibcon#end of sib2, iclass 23, count 0 2006.286.04:43:02.26#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:43:02.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:43:02.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:43:02.26#ibcon#*before write, iclass 23, count 0 2006.286.04:43:02.26#ibcon#enter sib2, iclass 23, count 0 2006.286.04:43:02.26#ibcon#flushed, iclass 23, count 0 2006.286.04:43:02.26#ibcon#about to write, iclass 23, count 0 2006.286.04:43:02.26#ibcon#wrote, iclass 23, count 0 2006.286.04:43:02.26#ibcon#about to read 3, iclass 23, count 0 2006.286.04:43:02.30#ibcon#read 3, iclass 23, count 0 2006.286.04:43:02.30#ibcon#about to read 4, iclass 23, count 0 2006.286.04:43:02.30#ibcon#read 4, iclass 23, count 0 2006.286.04:43:02.30#ibcon#about to read 5, iclass 23, count 0 2006.286.04:43:02.30#ibcon#read 5, iclass 23, count 0 2006.286.04:43:02.30#ibcon#about to read 6, iclass 23, count 0 2006.286.04:43:02.30#ibcon#read 6, iclass 23, count 0 2006.286.04:43:02.30#ibcon#end of sib2, iclass 23, count 0 2006.286.04:43:02.30#ibcon#*after write, iclass 23, count 0 2006.286.04:43:02.30#ibcon#*before return 0, iclass 23, count 0 2006.286.04:43:02.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:43:02.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:43:02.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:43:02.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:43:02.30$vck44/va=4,6 2006.286.04:43:02.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.04:43:02.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.04:43:02.30#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:02.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:43:02.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:43:02.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:43:02.30#ibcon#enter wrdev, iclass 25, count 2 2006.286.04:43:02.30#ibcon#first serial, iclass 25, count 2 2006.286.04:43:02.30#ibcon#enter sib2, iclass 25, count 2 2006.286.04:43:02.30#ibcon#flushed, iclass 25, count 2 2006.286.04:43:02.30#ibcon#about to write, iclass 25, count 2 2006.286.04:43:02.30#ibcon#wrote, iclass 25, count 2 2006.286.04:43:02.30#ibcon#about to read 3, iclass 25, count 2 2006.286.04:43:02.32#ibcon#read 3, iclass 25, count 2 2006.286.04:43:02.32#ibcon#about to read 4, iclass 25, count 2 2006.286.04:43:02.32#ibcon#read 4, iclass 25, count 2 2006.286.04:43:02.32#ibcon#about to read 5, iclass 25, count 2 2006.286.04:43:02.32#ibcon#read 5, iclass 25, count 2 2006.286.04:43:02.32#ibcon#about to read 6, iclass 25, count 2 2006.286.04:43:02.32#ibcon#read 6, iclass 25, count 2 2006.286.04:43:02.32#ibcon#end of sib2, iclass 25, count 2 2006.286.04:43:02.32#ibcon#*mode == 0, iclass 25, count 2 2006.286.04:43:02.32#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.04:43:02.32#ibcon#[25=AT04-06\r\n] 2006.286.04:43:02.32#ibcon#*before write, iclass 25, count 2 2006.286.04:43:02.32#ibcon#enter sib2, iclass 25, count 2 2006.286.04:43:02.32#ibcon#flushed, iclass 25, count 2 2006.286.04:43:02.32#ibcon#about to write, iclass 25, count 2 2006.286.04:43:02.32#ibcon#wrote, iclass 25, count 2 2006.286.04:43:02.32#ibcon#about to read 3, iclass 25, count 2 2006.286.04:43:02.35#ibcon#read 3, iclass 25, count 2 2006.286.04:43:02.35#ibcon#about to read 4, iclass 25, count 2 2006.286.04:43:02.35#ibcon#read 4, iclass 25, count 2 2006.286.04:43:02.35#ibcon#about to read 5, iclass 25, count 2 2006.286.04:43:02.35#ibcon#read 5, iclass 25, count 2 2006.286.04:43:02.35#ibcon#about to read 6, iclass 25, count 2 2006.286.04:43:02.35#ibcon#read 6, iclass 25, count 2 2006.286.04:43:02.35#ibcon#end of sib2, iclass 25, count 2 2006.286.04:43:02.35#ibcon#*after write, iclass 25, count 2 2006.286.04:43:02.35#ibcon#*before return 0, iclass 25, count 2 2006.286.04:43:02.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:43:02.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:43:02.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.04:43:02.35#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:02.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:43:02.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:43:02.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:43:02.47#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:43:02.47#ibcon#first serial, iclass 25, count 0 2006.286.04:43:02.47#ibcon#enter sib2, iclass 25, count 0 2006.286.04:43:02.47#ibcon#flushed, iclass 25, count 0 2006.286.04:43:02.47#ibcon#about to write, iclass 25, count 0 2006.286.04:43:02.47#ibcon#wrote, iclass 25, count 0 2006.286.04:43:02.47#ibcon#about to read 3, iclass 25, count 0 2006.286.04:43:02.49#ibcon#read 3, iclass 25, count 0 2006.286.04:43:02.49#ibcon#about to read 4, iclass 25, count 0 2006.286.04:43:02.49#ibcon#read 4, iclass 25, count 0 2006.286.04:43:02.49#ibcon#about to read 5, iclass 25, count 0 2006.286.04:43:02.49#ibcon#read 5, iclass 25, count 0 2006.286.04:43:02.49#ibcon#about to read 6, iclass 25, count 0 2006.286.04:43:02.49#ibcon#read 6, iclass 25, count 0 2006.286.04:43:02.49#ibcon#end of sib2, iclass 25, count 0 2006.286.04:43:02.49#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:43:02.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:43:02.49#ibcon#[25=USB\r\n] 2006.286.04:43:02.49#ibcon#*before write, iclass 25, count 0 2006.286.04:43:02.49#ibcon#enter sib2, iclass 25, count 0 2006.286.04:43:02.49#ibcon#flushed, iclass 25, count 0 2006.286.04:43:02.49#ibcon#about to write, iclass 25, count 0 2006.286.04:43:02.49#ibcon#wrote, iclass 25, count 0 2006.286.04:43:02.49#ibcon#about to read 3, iclass 25, count 0 2006.286.04:43:02.52#ibcon#read 3, iclass 25, count 0 2006.286.04:43:02.52#ibcon#about to read 4, iclass 25, count 0 2006.286.04:43:02.52#ibcon#read 4, iclass 25, count 0 2006.286.04:43:02.52#ibcon#about to read 5, iclass 25, count 0 2006.286.04:43:02.52#ibcon#read 5, iclass 25, count 0 2006.286.04:43:02.52#ibcon#about to read 6, iclass 25, count 0 2006.286.04:43:02.52#ibcon#read 6, iclass 25, count 0 2006.286.04:43:02.52#ibcon#end of sib2, iclass 25, count 0 2006.286.04:43:02.52#ibcon#*after write, iclass 25, count 0 2006.286.04:43:02.52#ibcon#*before return 0, iclass 25, count 0 2006.286.04:43:02.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:43:02.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:43:02.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:43:02.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:43:02.52$vck44/valo=5,734.99 2006.286.04:43:02.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.04:43:02.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.04:43:02.52#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:02.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:43:02.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:43:02.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:43:02.52#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:43:02.52#ibcon#first serial, iclass 27, count 0 2006.286.04:43:02.52#ibcon#enter sib2, iclass 27, count 0 2006.286.04:43:02.52#ibcon#flushed, iclass 27, count 0 2006.286.04:43:02.52#ibcon#about to write, iclass 27, count 0 2006.286.04:43:02.52#ibcon#wrote, iclass 27, count 0 2006.286.04:43:02.52#ibcon#about to read 3, iclass 27, count 0 2006.286.04:43:02.56#ibcon#read 3, iclass 27, count 0 2006.286.04:43:02.56#ibcon#about to read 4, iclass 27, count 0 2006.286.04:43:02.56#ibcon#read 4, iclass 27, count 0 2006.286.04:43:02.56#ibcon#about to read 5, iclass 27, count 0 2006.286.04:43:02.56#ibcon#read 5, iclass 27, count 0 2006.286.04:43:02.56#ibcon#about to read 6, iclass 27, count 0 2006.286.04:43:02.56#ibcon#read 6, iclass 27, count 0 2006.286.04:43:02.56#ibcon#end of sib2, iclass 27, count 0 2006.286.04:43:02.56#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:43:02.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:43:02.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:43:02.56#ibcon#*before write, iclass 27, count 0 2006.286.04:43:02.56#ibcon#enter sib2, iclass 27, count 0 2006.286.04:43:02.56#ibcon#flushed, iclass 27, count 0 2006.286.04:43:02.56#ibcon#about to write, iclass 27, count 0 2006.286.04:43:02.56#ibcon#wrote, iclass 27, count 0 2006.286.04:43:02.56#ibcon#about to read 3, iclass 27, count 0 2006.286.04:43:02.60#ibcon#read 3, iclass 27, count 0 2006.286.04:43:02.60#ibcon#about to read 4, iclass 27, count 0 2006.286.04:43:02.60#ibcon#read 4, iclass 27, count 0 2006.286.04:43:02.60#ibcon#about to read 5, iclass 27, count 0 2006.286.04:43:02.60#ibcon#read 5, iclass 27, count 0 2006.286.04:43:02.60#ibcon#about to read 6, iclass 27, count 0 2006.286.04:43:02.60#ibcon#read 6, iclass 27, count 0 2006.286.04:43:02.60#ibcon#end of sib2, iclass 27, count 0 2006.286.04:43:02.60#ibcon#*after write, iclass 27, count 0 2006.286.04:43:02.60#ibcon#*before return 0, iclass 27, count 0 2006.286.04:43:02.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:43:02.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:43:02.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:43:02.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:43:02.60$vck44/va=5,3 2006.286.04:43:02.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.04:43:02.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.04:43:02.60#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:02.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:43:02.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:43:02.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:43:02.64#ibcon#enter wrdev, iclass 29, count 2 2006.286.04:43:02.64#ibcon#first serial, iclass 29, count 2 2006.286.04:43:02.64#ibcon#enter sib2, iclass 29, count 2 2006.286.04:43:02.64#ibcon#flushed, iclass 29, count 2 2006.286.04:43:02.64#ibcon#about to write, iclass 29, count 2 2006.286.04:43:02.64#ibcon#wrote, iclass 29, count 2 2006.286.04:43:02.64#ibcon#about to read 3, iclass 29, count 2 2006.286.04:43:02.66#ibcon#read 3, iclass 29, count 2 2006.286.04:43:02.66#ibcon#about to read 4, iclass 29, count 2 2006.286.04:43:02.66#ibcon#read 4, iclass 29, count 2 2006.286.04:43:02.66#ibcon#about to read 5, iclass 29, count 2 2006.286.04:43:02.66#ibcon#read 5, iclass 29, count 2 2006.286.04:43:02.66#ibcon#about to read 6, iclass 29, count 2 2006.286.04:43:02.66#ibcon#read 6, iclass 29, count 2 2006.286.04:43:02.66#ibcon#end of sib2, iclass 29, count 2 2006.286.04:43:02.66#ibcon#*mode == 0, iclass 29, count 2 2006.286.04:43:02.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.04:43:02.66#ibcon#[25=AT05-03\r\n] 2006.286.04:43:02.66#ibcon#*before write, iclass 29, count 2 2006.286.04:43:02.66#ibcon#enter sib2, iclass 29, count 2 2006.286.04:43:02.66#ibcon#flushed, iclass 29, count 2 2006.286.04:43:02.66#ibcon#about to write, iclass 29, count 2 2006.286.04:43:02.66#ibcon#wrote, iclass 29, count 2 2006.286.04:43:02.66#ibcon#about to read 3, iclass 29, count 2 2006.286.04:43:02.69#ibcon#read 3, iclass 29, count 2 2006.286.04:43:02.69#ibcon#about to read 4, iclass 29, count 2 2006.286.04:43:02.69#ibcon#read 4, iclass 29, count 2 2006.286.04:43:02.69#ibcon#about to read 5, iclass 29, count 2 2006.286.04:43:02.69#ibcon#read 5, iclass 29, count 2 2006.286.04:43:02.69#ibcon#about to read 6, iclass 29, count 2 2006.286.04:43:02.69#ibcon#read 6, iclass 29, count 2 2006.286.04:43:02.69#ibcon#end of sib2, iclass 29, count 2 2006.286.04:43:02.69#ibcon#*after write, iclass 29, count 2 2006.286.04:43:02.69#ibcon#*before return 0, iclass 29, count 2 2006.286.04:43:02.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:43:02.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:43:02.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.04:43:02.69#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:02.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:43:02.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:43:02.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:43:02.81#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:43:02.81#ibcon#first serial, iclass 29, count 0 2006.286.04:43:02.81#ibcon#enter sib2, iclass 29, count 0 2006.286.04:43:02.81#ibcon#flushed, iclass 29, count 0 2006.286.04:43:02.81#ibcon#about to write, iclass 29, count 0 2006.286.04:43:02.81#ibcon#wrote, iclass 29, count 0 2006.286.04:43:02.81#ibcon#about to read 3, iclass 29, count 0 2006.286.04:43:02.83#ibcon#read 3, iclass 29, count 0 2006.286.04:43:02.83#ibcon#about to read 4, iclass 29, count 0 2006.286.04:43:02.83#ibcon#read 4, iclass 29, count 0 2006.286.04:43:02.83#ibcon#about to read 5, iclass 29, count 0 2006.286.04:43:02.83#ibcon#read 5, iclass 29, count 0 2006.286.04:43:02.83#ibcon#about to read 6, iclass 29, count 0 2006.286.04:43:02.83#ibcon#read 6, iclass 29, count 0 2006.286.04:43:02.83#ibcon#end of sib2, iclass 29, count 0 2006.286.04:43:02.83#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:43:02.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:43:02.83#ibcon#[25=USB\r\n] 2006.286.04:43:02.83#ibcon#*before write, iclass 29, count 0 2006.286.04:43:02.83#ibcon#enter sib2, iclass 29, count 0 2006.286.04:43:02.83#ibcon#flushed, iclass 29, count 0 2006.286.04:43:02.83#ibcon#about to write, iclass 29, count 0 2006.286.04:43:02.83#ibcon#wrote, iclass 29, count 0 2006.286.04:43:02.83#ibcon#about to read 3, iclass 29, count 0 2006.286.04:43:02.86#ibcon#read 3, iclass 29, count 0 2006.286.04:43:02.86#ibcon#about to read 4, iclass 29, count 0 2006.286.04:43:02.86#ibcon#read 4, iclass 29, count 0 2006.286.04:43:02.86#ibcon#about to read 5, iclass 29, count 0 2006.286.04:43:02.86#ibcon#read 5, iclass 29, count 0 2006.286.04:43:02.86#ibcon#about to read 6, iclass 29, count 0 2006.286.04:43:02.86#ibcon#read 6, iclass 29, count 0 2006.286.04:43:02.86#ibcon#end of sib2, iclass 29, count 0 2006.286.04:43:02.86#ibcon#*after write, iclass 29, count 0 2006.286.04:43:02.86#ibcon#*before return 0, iclass 29, count 0 2006.286.04:43:02.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:43:02.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:43:02.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:43:02.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:43:02.86$vck44/valo=6,814.99 2006.286.04:43:02.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.04:43:02.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.04:43:02.86#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:02.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:43:02.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:43:02.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:43:02.86#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:43:02.86#ibcon#first serial, iclass 31, count 0 2006.286.04:43:02.86#ibcon#enter sib2, iclass 31, count 0 2006.286.04:43:02.86#ibcon#flushed, iclass 31, count 0 2006.286.04:43:02.86#ibcon#about to write, iclass 31, count 0 2006.286.04:43:02.86#ibcon#wrote, iclass 31, count 0 2006.286.04:43:02.86#ibcon#about to read 3, iclass 31, count 0 2006.286.04:43:02.88#ibcon#read 3, iclass 31, count 0 2006.286.04:43:02.88#ibcon#about to read 4, iclass 31, count 0 2006.286.04:43:02.88#ibcon#read 4, iclass 31, count 0 2006.286.04:43:02.88#ibcon#about to read 5, iclass 31, count 0 2006.286.04:43:02.88#ibcon#read 5, iclass 31, count 0 2006.286.04:43:02.88#ibcon#about to read 6, iclass 31, count 0 2006.286.04:43:02.88#ibcon#read 6, iclass 31, count 0 2006.286.04:43:02.88#ibcon#end of sib2, iclass 31, count 0 2006.286.04:43:02.88#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:43:02.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:43:02.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:43:02.88#ibcon#*before write, iclass 31, count 0 2006.286.04:43:02.88#ibcon#enter sib2, iclass 31, count 0 2006.286.04:43:02.88#ibcon#flushed, iclass 31, count 0 2006.286.04:43:02.88#ibcon#about to write, iclass 31, count 0 2006.286.04:43:02.88#ibcon#wrote, iclass 31, count 0 2006.286.04:43:02.88#ibcon#about to read 3, iclass 31, count 0 2006.286.04:43:02.92#ibcon#read 3, iclass 31, count 0 2006.286.04:43:02.92#ibcon#about to read 4, iclass 31, count 0 2006.286.04:43:02.92#ibcon#read 4, iclass 31, count 0 2006.286.04:43:02.92#ibcon#about to read 5, iclass 31, count 0 2006.286.04:43:02.92#ibcon#read 5, iclass 31, count 0 2006.286.04:43:02.92#ibcon#about to read 6, iclass 31, count 0 2006.286.04:43:02.92#ibcon#read 6, iclass 31, count 0 2006.286.04:43:02.92#ibcon#end of sib2, iclass 31, count 0 2006.286.04:43:02.92#ibcon#*after write, iclass 31, count 0 2006.286.04:43:02.92#ibcon#*before return 0, iclass 31, count 0 2006.286.04:43:02.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:43:02.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:43:02.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:43:02.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:43:02.92$vck44/va=6,4 2006.286.04:43:02.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.04:43:02.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.04:43:02.92#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:02.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:43:02.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:43:02.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:43:02.98#ibcon#enter wrdev, iclass 33, count 2 2006.286.04:43:02.98#ibcon#first serial, iclass 33, count 2 2006.286.04:43:02.98#ibcon#enter sib2, iclass 33, count 2 2006.286.04:43:02.98#ibcon#flushed, iclass 33, count 2 2006.286.04:43:02.98#ibcon#about to write, iclass 33, count 2 2006.286.04:43:02.98#ibcon#wrote, iclass 33, count 2 2006.286.04:43:02.98#ibcon#about to read 3, iclass 33, count 2 2006.286.04:43:03.00#ibcon#read 3, iclass 33, count 2 2006.286.04:43:03.00#ibcon#about to read 4, iclass 33, count 2 2006.286.04:43:03.00#ibcon#read 4, iclass 33, count 2 2006.286.04:43:03.00#ibcon#about to read 5, iclass 33, count 2 2006.286.04:43:03.00#ibcon#read 5, iclass 33, count 2 2006.286.04:43:03.00#ibcon#about to read 6, iclass 33, count 2 2006.286.04:43:03.00#ibcon#read 6, iclass 33, count 2 2006.286.04:43:03.00#ibcon#end of sib2, iclass 33, count 2 2006.286.04:43:03.00#ibcon#*mode == 0, iclass 33, count 2 2006.286.04:43:03.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.04:43:03.00#ibcon#[25=AT06-04\r\n] 2006.286.04:43:03.00#ibcon#*before write, iclass 33, count 2 2006.286.04:43:03.00#ibcon#enter sib2, iclass 33, count 2 2006.286.04:43:03.00#ibcon#flushed, iclass 33, count 2 2006.286.04:43:03.00#ibcon#about to write, iclass 33, count 2 2006.286.04:43:03.00#ibcon#wrote, iclass 33, count 2 2006.286.04:43:03.00#ibcon#about to read 3, iclass 33, count 2 2006.286.04:43:03.03#ibcon#read 3, iclass 33, count 2 2006.286.04:43:03.03#ibcon#about to read 4, iclass 33, count 2 2006.286.04:43:03.03#ibcon#read 4, iclass 33, count 2 2006.286.04:43:03.03#ibcon#about to read 5, iclass 33, count 2 2006.286.04:43:03.03#ibcon#read 5, iclass 33, count 2 2006.286.04:43:03.03#ibcon#about to read 6, iclass 33, count 2 2006.286.04:43:03.03#ibcon#read 6, iclass 33, count 2 2006.286.04:43:03.03#ibcon#end of sib2, iclass 33, count 2 2006.286.04:43:03.03#ibcon#*after write, iclass 33, count 2 2006.286.04:43:03.03#ibcon#*before return 0, iclass 33, count 2 2006.286.04:43:03.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:43:03.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:43:03.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.04:43:03.03#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:03.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:43:03.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:43:03.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:43:03.15#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:43:03.15#ibcon#first serial, iclass 33, count 0 2006.286.04:43:03.15#ibcon#enter sib2, iclass 33, count 0 2006.286.04:43:03.15#ibcon#flushed, iclass 33, count 0 2006.286.04:43:03.15#ibcon#about to write, iclass 33, count 0 2006.286.04:43:03.15#ibcon#wrote, iclass 33, count 0 2006.286.04:43:03.15#ibcon#about to read 3, iclass 33, count 0 2006.286.04:43:03.17#ibcon#read 3, iclass 33, count 0 2006.286.04:43:03.17#ibcon#about to read 4, iclass 33, count 0 2006.286.04:43:03.17#ibcon#read 4, iclass 33, count 0 2006.286.04:43:03.17#ibcon#about to read 5, iclass 33, count 0 2006.286.04:43:03.17#ibcon#read 5, iclass 33, count 0 2006.286.04:43:03.17#ibcon#about to read 6, iclass 33, count 0 2006.286.04:43:03.17#ibcon#read 6, iclass 33, count 0 2006.286.04:43:03.17#ibcon#end of sib2, iclass 33, count 0 2006.286.04:43:03.17#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:43:03.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:43:03.17#ibcon#[25=USB\r\n] 2006.286.04:43:03.17#ibcon#*before write, iclass 33, count 0 2006.286.04:43:03.17#ibcon#enter sib2, iclass 33, count 0 2006.286.04:43:03.17#ibcon#flushed, iclass 33, count 0 2006.286.04:43:03.17#ibcon#about to write, iclass 33, count 0 2006.286.04:43:03.17#ibcon#wrote, iclass 33, count 0 2006.286.04:43:03.17#ibcon#about to read 3, iclass 33, count 0 2006.286.04:43:03.20#ibcon#read 3, iclass 33, count 0 2006.286.04:43:03.20#ibcon#about to read 4, iclass 33, count 0 2006.286.04:43:03.20#ibcon#read 4, iclass 33, count 0 2006.286.04:43:03.20#ibcon#about to read 5, iclass 33, count 0 2006.286.04:43:03.20#ibcon#read 5, iclass 33, count 0 2006.286.04:43:03.20#ibcon#about to read 6, iclass 33, count 0 2006.286.04:43:03.20#ibcon#read 6, iclass 33, count 0 2006.286.04:43:03.20#ibcon#end of sib2, iclass 33, count 0 2006.286.04:43:03.20#ibcon#*after write, iclass 33, count 0 2006.286.04:43:03.20#ibcon#*before return 0, iclass 33, count 0 2006.286.04:43:03.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:43:03.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:43:03.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:43:03.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:43:03.20$vck44/valo=7,864.99 2006.286.04:43:03.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.04:43:03.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.04:43:03.20#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:03.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:43:03.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:43:03.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:43:03.20#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:43:03.20#ibcon#first serial, iclass 35, count 0 2006.286.04:43:03.20#ibcon#enter sib2, iclass 35, count 0 2006.286.04:43:03.20#ibcon#flushed, iclass 35, count 0 2006.286.04:43:03.20#ibcon#about to write, iclass 35, count 0 2006.286.04:43:03.20#ibcon#wrote, iclass 35, count 0 2006.286.04:43:03.20#ibcon#about to read 3, iclass 35, count 0 2006.286.04:43:03.22#ibcon#read 3, iclass 35, count 0 2006.286.04:43:03.22#ibcon#about to read 4, iclass 35, count 0 2006.286.04:43:03.22#ibcon#read 4, iclass 35, count 0 2006.286.04:43:03.22#ibcon#about to read 5, iclass 35, count 0 2006.286.04:43:03.22#ibcon#read 5, iclass 35, count 0 2006.286.04:43:03.22#ibcon#about to read 6, iclass 35, count 0 2006.286.04:43:03.22#ibcon#read 6, iclass 35, count 0 2006.286.04:43:03.22#ibcon#end of sib2, iclass 35, count 0 2006.286.04:43:03.22#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:43:03.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:43:03.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:43:03.22#ibcon#*before write, iclass 35, count 0 2006.286.04:43:03.22#ibcon#enter sib2, iclass 35, count 0 2006.286.04:43:03.22#ibcon#flushed, iclass 35, count 0 2006.286.04:43:03.22#ibcon#about to write, iclass 35, count 0 2006.286.04:43:03.22#ibcon#wrote, iclass 35, count 0 2006.286.04:43:03.22#ibcon#about to read 3, iclass 35, count 0 2006.286.04:43:03.26#ibcon#read 3, iclass 35, count 0 2006.286.04:43:03.26#ibcon#about to read 4, iclass 35, count 0 2006.286.04:43:03.26#ibcon#read 4, iclass 35, count 0 2006.286.04:43:03.26#ibcon#about to read 5, iclass 35, count 0 2006.286.04:43:03.26#ibcon#read 5, iclass 35, count 0 2006.286.04:43:03.26#ibcon#about to read 6, iclass 35, count 0 2006.286.04:43:03.26#ibcon#read 6, iclass 35, count 0 2006.286.04:43:03.26#ibcon#end of sib2, iclass 35, count 0 2006.286.04:43:03.26#ibcon#*after write, iclass 35, count 0 2006.286.04:43:03.26#ibcon#*before return 0, iclass 35, count 0 2006.286.04:43:03.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:43:03.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:43:03.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:43:03.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:43:03.26$vck44/va=7,4 2006.286.04:43:03.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.04:43:03.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.04:43:03.26#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:03.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:43:03.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:43:03.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:43:03.32#ibcon#enter wrdev, iclass 37, count 2 2006.286.04:43:03.32#ibcon#first serial, iclass 37, count 2 2006.286.04:43:03.32#ibcon#enter sib2, iclass 37, count 2 2006.286.04:43:03.32#ibcon#flushed, iclass 37, count 2 2006.286.04:43:03.32#ibcon#about to write, iclass 37, count 2 2006.286.04:43:03.32#ibcon#wrote, iclass 37, count 2 2006.286.04:43:03.32#ibcon#about to read 3, iclass 37, count 2 2006.286.04:43:03.34#ibcon#read 3, iclass 37, count 2 2006.286.04:43:03.34#ibcon#about to read 4, iclass 37, count 2 2006.286.04:43:03.34#ibcon#read 4, iclass 37, count 2 2006.286.04:43:03.34#ibcon#about to read 5, iclass 37, count 2 2006.286.04:43:03.34#ibcon#read 5, iclass 37, count 2 2006.286.04:43:03.34#ibcon#about to read 6, iclass 37, count 2 2006.286.04:43:03.34#ibcon#read 6, iclass 37, count 2 2006.286.04:43:03.34#ibcon#end of sib2, iclass 37, count 2 2006.286.04:43:03.34#ibcon#*mode == 0, iclass 37, count 2 2006.286.04:43:03.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.04:43:03.34#ibcon#[25=AT07-04\r\n] 2006.286.04:43:03.34#ibcon#*before write, iclass 37, count 2 2006.286.04:43:03.34#ibcon#enter sib2, iclass 37, count 2 2006.286.04:43:03.34#ibcon#flushed, iclass 37, count 2 2006.286.04:43:03.34#ibcon#about to write, iclass 37, count 2 2006.286.04:43:03.34#ibcon#wrote, iclass 37, count 2 2006.286.04:43:03.34#ibcon#about to read 3, iclass 37, count 2 2006.286.04:43:03.37#ibcon#read 3, iclass 37, count 2 2006.286.04:43:03.37#ibcon#about to read 4, iclass 37, count 2 2006.286.04:43:03.37#ibcon#read 4, iclass 37, count 2 2006.286.04:43:03.37#ibcon#about to read 5, iclass 37, count 2 2006.286.04:43:03.37#ibcon#read 5, iclass 37, count 2 2006.286.04:43:03.37#ibcon#about to read 6, iclass 37, count 2 2006.286.04:43:03.37#ibcon#read 6, iclass 37, count 2 2006.286.04:43:03.37#ibcon#end of sib2, iclass 37, count 2 2006.286.04:43:03.37#ibcon#*after write, iclass 37, count 2 2006.286.04:43:03.37#ibcon#*before return 0, iclass 37, count 2 2006.286.04:43:03.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:43:03.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:43:03.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.04:43:03.37#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:03.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:43:03.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:43:03.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:43:03.49#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:43:03.49#ibcon#first serial, iclass 37, count 0 2006.286.04:43:03.49#ibcon#enter sib2, iclass 37, count 0 2006.286.04:43:03.49#ibcon#flushed, iclass 37, count 0 2006.286.04:43:03.49#ibcon#about to write, iclass 37, count 0 2006.286.04:43:03.49#ibcon#wrote, iclass 37, count 0 2006.286.04:43:03.49#ibcon#about to read 3, iclass 37, count 0 2006.286.04:43:03.51#ibcon#read 3, iclass 37, count 0 2006.286.04:43:03.51#ibcon#about to read 4, iclass 37, count 0 2006.286.04:43:03.51#ibcon#read 4, iclass 37, count 0 2006.286.04:43:03.51#ibcon#about to read 5, iclass 37, count 0 2006.286.04:43:03.51#ibcon#read 5, iclass 37, count 0 2006.286.04:43:03.51#ibcon#about to read 6, iclass 37, count 0 2006.286.04:43:03.51#ibcon#read 6, iclass 37, count 0 2006.286.04:43:03.51#ibcon#end of sib2, iclass 37, count 0 2006.286.04:43:03.51#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:43:03.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:43:03.51#ibcon#[25=USB\r\n] 2006.286.04:43:03.51#ibcon#*before write, iclass 37, count 0 2006.286.04:43:03.51#ibcon#enter sib2, iclass 37, count 0 2006.286.04:43:03.51#ibcon#flushed, iclass 37, count 0 2006.286.04:43:03.51#ibcon#about to write, iclass 37, count 0 2006.286.04:43:03.51#ibcon#wrote, iclass 37, count 0 2006.286.04:43:03.51#ibcon#about to read 3, iclass 37, count 0 2006.286.04:43:03.54#ibcon#read 3, iclass 37, count 0 2006.286.04:43:03.54#ibcon#about to read 4, iclass 37, count 0 2006.286.04:43:03.54#ibcon#read 4, iclass 37, count 0 2006.286.04:43:03.54#ibcon#about to read 5, iclass 37, count 0 2006.286.04:43:03.54#ibcon#read 5, iclass 37, count 0 2006.286.04:43:03.54#ibcon#about to read 6, iclass 37, count 0 2006.286.04:43:03.54#ibcon#read 6, iclass 37, count 0 2006.286.04:43:03.54#ibcon#end of sib2, iclass 37, count 0 2006.286.04:43:03.54#ibcon#*after write, iclass 37, count 0 2006.286.04:43:03.54#ibcon#*before return 0, iclass 37, count 0 2006.286.04:43:03.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:43:03.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:43:03.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:43:03.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:43:03.54$vck44/valo=8,884.99 2006.286.04:43:03.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.04:43:03.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.04:43:03.54#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:03.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:43:03.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:43:03.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:43:03.54#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:43:03.54#ibcon#first serial, iclass 39, count 0 2006.286.04:43:03.54#ibcon#enter sib2, iclass 39, count 0 2006.286.04:43:03.54#ibcon#flushed, iclass 39, count 0 2006.286.04:43:03.54#ibcon#about to write, iclass 39, count 0 2006.286.04:43:03.54#ibcon#wrote, iclass 39, count 0 2006.286.04:43:03.54#ibcon#about to read 3, iclass 39, count 0 2006.286.04:43:03.69#ibcon#read 3, iclass 39, count 0 2006.286.04:43:03.69#ibcon#about to read 4, iclass 39, count 0 2006.286.04:43:03.69#ibcon#read 4, iclass 39, count 0 2006.286.04:43:03.69#ibcon#about to read 5, iclass 39, count 0 2006.286.04:43:03.69#ibcon#read 5, iclass 39, count 0 2006.286.04:43:03.69#ibcon#about to read 6, iclass 39, count 0 2006.286.04:43:03.69#ibcon#read 6, iclass 39, count 0 2006.286.04:43:03.69#ibcon#end of sib2, iclass 39, count 0 2006.286.04:43:03.69#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:43:03.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:43:03.69#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:43:03.69#ibcon#*before write, iclass 39, count 0 2006.286.04:43:03.69#ibcon#enter sib2, iclass 39, count 0 2006.286.04:43:03.69#ibcon#flushed, iclass 39, count 0 2006.286.04:43:03.69#ibcon#about to write, iclass 39, count 0 2006.286.04:43:03.69#ibcon#wrote, iclass 39, count 0 2006.286.04:43:03.69#ibcon#about to read 3, iclass 39, count 0 2006.286.04:43:03.73#ibcon#read 3, iclass 39, count 0 2006.286.04:43:03.73#ibcon#about to read 4, iclass 39, count 0 2006.286.04:43:03.73#ibcon#read 4, iclass 39, count 0 2006.286.04:43:03.73#ibcon#about to read 5, iclass 39, count 0 2006.286.04:43:03.73#ibcon#read 5, iclass 39, count 0 2006.286.04:43:03.73#ibcon#about to read 6, iclass 39, count 0 2006.286.04:43:03.73#ibcon#read 6, iclass 39, count 0 2006.286.04:43:03.73#ibcon#end of sib2, iclass 39, count 0 2006.286.04:43:03.73#ibcon#*after write, iclass 39, count 0 2006.286.04:43:03.73#ibcon#*before return 0, iclass 39, count 0 2006.286.04:43:03.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:43:03.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:43:03.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:43:03.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:43:03.73$vck44/va=8,3 2006.286.04:43:03.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.04:43:03.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.04:43:03.73#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:03.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:43:03.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:43:03.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:43:03.73#ibcon#enter wrdev, iclass 3, count 2 2006.286.04:43:03.73#ibcon#first serial, iclass 3, count 2 2006.286.04:43:03.73#ibcon#enter sib2, iclass 3, count 2 2006.286.04:43:03.73#ibcon#flushed, iclass 3, count 2 2006.286.04:43:03.73#ibcon#about to write, iclass 3, count 2 2006.286.04:43:03.73#ibcon#wrote, iclass 3, count 2 2006.286.04:43:03.73#ibcon#about to read 3, iclass 3, count 2 2006.286.04:43:03.75#ibcon#read 3, iclass 3, count 2 2006.286.04:43:03.75#ibcon#about to read 4, iclass 3, count 2 2006.286.04:43:03.75#ibcon#read 4, iclass 3, count 2 2006.286.04:43:03.75#ibcon#about to read 5, iclass 3, count 2 2006.286.04:43:03.75#ibcon#read 5, iclass 3, count 2 2006.286.04:43:03.75#ibcon#about to read 6, iclass 3, count 2 2006.286.04:43:03.75#ibcon#read 6, iclass 3, count 2 2006.286.04:43:03.75#ibcon#end of sib2, iclass 3, count 2 2006.286.04:43:03.75#ibcon#*mode == 0, iclass 3, count 2 2006.286.04:43:03.75#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.04:43:03.75#ibcon#[25=AT08-03\r\n] 2006.286.04:43:03.75#ibcon#*before write, iclass 3, count 2 2006.286.04:43:03.75#ibcon#enter sib2, iclass 3, count 2 2006.286.04:43:03.75#ibcon#flushed, iclass 3, count 2 2006.286.04:43:03.75#ibcon#about to write, iclass 3, count 2 2006.286.04:43:03.75#ibcon#wrote, iclass 3, count 2 2006.286.04:43:03.75#ibcon#about to read 3, iclass 3, count 2 2006.286.04:43:03.78#ibcon#read 3, iclass 3, count 2 2006.286.04:43:03.78#ibcon#about to read 4, iclass 3, count 2 2006.286.04:43:03.78#ibcon#read 4, iclass 3, count 2 2006.286.04:43:03.78#ibcon#about to read 5, iclass 3, count 2 2006.286.04:43:03.78#ibcon#read 5, iclass 3, count 2 2006.286.04:43:03.78#ibcon#about to read 6, iclass 3, count 2 2006.286.04:43:03.78#ibcon#read 6, iclass 3, count 2 2006.286.04:43:03.78#ibcon#end of sib2, iclass 3, count 2 2006.286.04:43:03.78#ibcon#*after write, iclass 3, count 2 2006.286.04:43:03.78#ibcon#*before return 0, iclass 3, count 2 2006.286.04:43:03.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:43:03.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:43:03.78#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.04:43:03.78#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:03.78#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:43:03.90#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:43:03.90#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:43:03.90#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:43:03.90#ibcon#first serial, iclass 3, count 0 2006.286.04:43:03.90#ibcon#enter sib2, iclass 3, count 0 2006.286.04:43:03.90#ibcon#flushed, iclass 3, count 0 2006.286.04:43:03.90#ibcon#about to write, iclass 3, count 0 2006.286.04:43:03.90#ibcon#wrote, iclass 3, count 0 2006.286.04:43:03.90#ibcon#about to read 3, iclass 3, count 0 2006.286.04:43:03.92#ibcon#read 3, iclass 3, count 0 2006.286.04:43:03.92#ibcon#about to read 4, iclass 3, count 0 2006.286.04:43:03.92#ibcon#read 4, iclass 3, count 0 2006.286.04:43:03.92#ibcon#about to read 5, iclass 3, count 0 2006.286.04:43:03.92#ibcon#read 5, iclass 3, count 0 2006.286.04:43:03.92#ibcon#about to read 6, iclass 3, count 0 2006.286.04:43:03.92#ibcon#read 6, iclass 3, count 0 2006.286.04:43:03.92#ibcon#end of sib2, iclass 3, count 0 2006.286.04:43:03.92#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:43:03.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:43:03.92#ibcon#[25=USB\r\n] 2006.286.04:43:03.92#ibcon#*before write, iclass 3, count 0 2006.286.04:43:03.92#ibcon#enter sib2, iclass 3, count 0 2006.286.04:43:03.92#ibcon#flushed, iclass 3, count 0 2006.286.04:43:03.92#ibcon#about to write, iclass 3, count 0 2006.286.04:43:03.92#ibcon#wrote, iclass 3, count 0 2006.286.04:43:03.92#ibcon#about to read 3, iclass 3, count 0 2006.286.04:43:03.95#ibcon#read 3, iclass 3, count 0 2006.286.04:43:03.95#ibcon#about to read 4, iclass 3, count 0 2006.286.04:43:03.95#ibcon#read 4, iclass 3, count 0 2006.286.04:43:03.95#ibcon#about to read 5, iclass 3, count 0 2006.286.04:43:03.95#ibcon#read 5, iclass 3, count 0 2006.286.04:43:03.95#ibcon#about to read 6, iclass 3, count 0 2006.286.04:43:03.95#ibcon#read 6, iclass 3, count 0 2006.286.04:43:03.95#ibcon#end of sib2, iclass 3, count 0 2006.286.04:43:03.95#ibcon#*after write, iclass 3, count 0 2006.286.04:43:03.95#ibcon#*before return 0, iclass 3, count 0 2006.286.04:43:03.95#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:43:03.95#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:43:03.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:43:03.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:43:03.95$vck44/vblo=1,629.99 2006.286.04:43:03.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.04:43:03.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.04:43:03.95#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:03.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:43:03.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:43:03.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:43:03.95#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:43:03.95#ibcon#first serial, iclass 5, count 0 2006.286.04:43:03.95#ibcon#enter sib2, iclass 5, count 0 2006.286.04:43:03.95#ibcon#flushed, iclass 5, count 0 2006.286.04:43:03.95#ibcon#about to write, iclass 5, count 0 2006.286.04:43:03.95#ibcon#wrote, iclass 5, count 0 2006.286.04:43:03.95#ibcon#about to read 3, iclass 5, count 0 2006.286.04:43:03.97#ibcon#read 3, iclass 5, count 0 2006.286.04:43:03.97#ibcon#about to read 4, iclass 5, count 0 2006.286.04:43:03.97#ibcon#read 4, iclass 5, count 0 2006.286.04:43:03.97#ibcon#about to read 5, iclass 5, count 0 2006.286.04:43:03.97#ibcon#read 5, iclass 5, count 0 2006.286.04:43:03.97#ibcon#about to read 6, iclass 5, count 0 2006.286.04:43:03.97#ibcon#read 6, iclass 5, count 0 2006.286.04:43:03.97#ibcon#end of sib2, iclass 5, count 0 2006.286.04:43:03.97#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:43:03.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:43:03.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:43:03.97#ibcon#*before write, iclass 5, count 0 2006.286.04:43:03.97#ibcon#enter sib2, iclass 5, count 0 2006.286.04:43:03.97#ibcon#flushed, iclass 5, count 0 2006.286.04:43:03.97#ibcon#about to write, iclass 5, count 0 2006.286.04:43:03.97#ibcon#wrote, iclass 5, count 0 2006.286.04:43:03.97#ibcon#about to read 3, iclass 5, count 0 2006.286.04:43:04.01#ibcon#read 3, iclass 5, count 0 2006.286.04:43:04.01#ibcon#about to read 4, iclass 5, count 0 2006.286.04:43:04.01#ibcon#read 4, iclass 5, count 0 2006.286.04:43:04.01#ibcon#about to read 5, iclass 5, count 0 2006.286.04:43:04.01#ibcon#read 5, iclass 5, count 0 2006.286.04:43:04.01#ibcon#about to read 6, iclass 5, count 0 2006.286.04:43:04.01#ibcon#read 6, iclass 5, count 0 2006.286.04:43:04.01#ibcon#end of sib2, iclass 5, count 0 2006.286.04:43:04.01#ibcon#*after write, iclass 5, count 0 2006.286.04:43:04.01#ibcon#*before return 0, iclass 5, count 0 2006.286.04:43:04.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:43:04.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:43:04.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:43:04.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:43:04.01$vck44/vb=1,4 2006.286.04:43:04.01#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.04:43:04.01#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.04:43:04.01#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:04.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:43:04.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:43:04.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:43:04.01#ibcon#enter wrdev, iclass 7, count 2 2006.286.04:43:04.01#ibcon#first serial, iclass 7, count 2 2006.286.04:43:04.01#ibcon#enter sib2, iclass 7, count 2 2006.286.04:43:04.01#ibcon#flushed, iclass 7, count 2 2006.286.04:43:04.01#ibcon#about to write, iclass 7, count 2 2006.286.04:43:04.01#ibcon#wrote, iclass 7, count 2 2006.286.04:43:04.01#ibcon#about to read 3, iclass 7, count 2 2006.286.04:43:04.03#ibcon#read 3, iclass 7, count 2 2006.286.04:43:04.03#ibcon#about to read 4, iclass 7, count 2 2006.286.04:43:04.03#ibcon#read 4, iclass 7, count 2 2006.286.04:43:04.03#ibcon#about to read 5, iclass 7, count 2 2006.286.04:43:04.03#ibcon#read 5, iclass 7, count 2 2006.286.04:43:04.03#ibcon#about to read 6, iclass 7, count 2 2006.286.04:43:04.03#ibcon#read 6, iclass 7, count 2 2006.286.04:43:04.03#ibcon#end of sib2, iclass 7, count 2 2006.286.04:43:04.03#ibcon#*mode == 0, iclass 7, count 2 2006.286.04:43:04.03#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.04:43:04.03#ibcon#[27=AT01-04\r\n] 2006.286.04:43:04.03#ibcon#*before write, iclass 7, count 2 2006.286.04:43:04.03#ibcon#enter sib2, iclass 7, count 2 2006.286.04:43:04.03#ibcon#flushed, iclass 7, count 2 2006.286.04:43:04.03#ibcon#about to write, iclass 7, count 2 2006.286.04:43:04.03#ibcon#wrote, iclass 7, count 2 2006.286.04:43:04.03#ibcon#about to read 3, iclass 7, count 2 2006.286.04:43:04.06#ibcon#read 3, iclass 7, count 2 2006.286.04:43:04.06#ibcon#about to read 4, iclass 7, count 2 2006.286.04:43:04.06#ibcon#read 4, iclass 7, count 2 2006.286.04:43:04.06#ibcon#about to read 5, iclass 7, count 2 2006.286.04:43:04.06#ibcon#read 5, iclass 7, count 2 2006.286.04:43:04.06#ibcon#about to read 6, iclass 7, count 2 2006.286.04:43:04.06#ibcon#read 6, iclass 7, count 2 2006.286.04:43:04.06#ibcon#end of sib2, iclass 7, count 2 2006.286.04:43:04.06#ibcon#*after write, iclass 7, count 2 2006.286.04:43:04.06#ibcon#*before return 0, iclass 7, count 2 2006.286.04:43:04.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:43:04.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:43:04.06#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.04:43:04.06#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:04.06#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:43:04.18#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:43:04.18#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:43:04.18#ibcon#enter wrdev, iclass 7, count 0 2006.286.04:43:04.18#ibcon#first serial, iclass 7, count 0 2006.286.04:43:04.18#ibcon#enter sib2, iclass 7, count 0 2006.286.04:43:04.18#ibcon#flushed, iclass 7, count 0 2006.286.04:43:04.18#ibcon#about to write, iclass 7, count 0 2006.286.04:43:04.18#ibcon#wrote, iclass 7, count 0 2006.286.04:43:04.18#ibcon#about to read 3, iclass 7, count 0 2006.286.04:43:04.20#ibcon#read 3, iclass 7, count 0 2006.286.04:43:04.20#ibcon#about to read 4, iclass 7, count 0 2006.286.04:43:04.20#ibcon#read 4, iclass 7, count 0 2006.286.04:43:04.20#ibcon#about to read 5, iclass 7, count 0 2006.286.04:43:04.20#ibcon#read 5, iclass 7, count 0 2006.286.04:43:04.20#ibcon#about to read 6, iclass 7, count 0 2006.286.04:43:04.20#ibcon#read 6, iclass 7, count 0 2006.286.04:43:04.20#ibcon#end of sib2, iclass 7, count 0 2006.286.04:43:04.20#ibcon#*mode == 0, iclass 7, count 0 2006.286.04:43:04.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.04:43:04.20#ibcon#[27=USB\r\n] 2006.286.04:43:04.20#ibcon#*before write, iclass 7, count 0 2006.286.04:43:04.20#ibcon#enter sib2, iclass 7, count 0 2006.286.04:43:04.20#ibcon#flushed, iclass 7, count 0 2006.286.04:43:04.20#ibcon#about to write, iclass 7, count 0 2006.286.04:43:04.20#ibcon#wrote, iclass 7, count 0 2006.286.04:43:04.20#ibcon#about to read 3, iclass 7, count 0 2006.286.04:43:04.23#ibcon#read 3, iclass 7, count 0 2006.286.04:43:04.23#ibcon#about to read 4, iclass 7, count 0 2006.286.04:43:04.23#ibcon#read 4, iclass 7, count 0 2006.286.04:43:04.23#ibcon#about to read 5, iclass 7, count 0 2006.286.04:43:04.23#ibcon#read 5, iclass 7, count 0 2006.286.04:43:04.23#ibcon#about to read 6, iclass 7, count 0 2006.286.04:43:04.23#ibcon#read 6, iclass 7, count 0 2006.286.04:43:04.23#ibcon#end of sib2, iclass 7, count 0 2006.286.04:43:04.23#ibcon#*after write, iclass 7, count 0 2006.286.04:43:04.23#ibcon#*before return 0, iclass 7, count 0 2006.286.04:43:04.23#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:43:04.23#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:43:04.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.04:43:04.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.04:43:04.23$vck44/vblo=2,634.99 2006.286.04:43:04.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.04:43:04.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.04:43:04.23#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:04.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:43:04.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:43:04.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:43:04.23#ibcon#enter wrdev, iclass 11, count 0 2006.286.04:43:04.23#ibcon#first serial, iclass 11, count 0 2006.286.04:43:04.23#ibcon#enter sib2, iclass 11, count 0 2006.286.04:43:04.23#ibcon#flushed, iclass 11, count 0 2006.286.04:43:04.23#ibcon#about to write, iclass 11, count 0 2006.286.04:43:04.23#ibcon#wrote, iclass 11, count 0 2006.286.04:43:04.23#ibcon#about to read 3, iclass 11, count 0 2006.286.04:43:04.25#ibcon#read 3, iclass 11, count 0 2006.286.04:43:04.25#ibcon#about to read 4, iclass 11, count 0 2006.286.04:43:04.25#ibcon#read 4, iclass 11, count 0 2006.286.04:43:04.25#ibcon#about to read 5, iclass 11, count 0 2006.286.04:43:04.25#ibcon#read 5, iclass 11, count 0 2006.286.04:43:04.25#ibcon#about to read 6, iclass 11, count 0 2006.286.04:43:04.25#ibcon#read 6, iclass 11, count 0 2006.286.04:43:04.25#ibcon#end of sib2, iclass 11, count 0 2006.286.04:43:04.25#ibcon#*mode == 0, iclass 11, count 0 2006.286.04:43:04.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.04:43:04.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:43:04.25#ibcon#*before write, iclass 11, count 0 2006.286.04:43:04.25#ibcon#enter sib2, iclass 11, count 0 2006.286.04:43:04.25#ibcon#flushed, iclass 11, count 0 2006.286.04:43:04.25#ibcon#about to write, iclass 11, count 0 2006.286.04:43:04.25#ibcon#wrote, iclass 11, count 0 2006.286.04:43:04.25#ibcon#about to read 3, iclass 11, count 0 2006.286.04:43:04.29#ibcon#read 3, iclass 11, count 0 2006.286.04:43:04.29#ibcon#about to read 4, iclass 11, count 0 2006.286.04:43:04.29#ibcon#read 4, iclass 11, count 0 2006.286.04:43:04.29#ibcon#about to read 5, iclass 11, count 0 2006.286.04:43:04.29#ibcon#read 5, iclass 11, count 0 2006.286.04:43:04.29#ibcon#about to read 6, iclass 11, count 0 2006.286.04:43:04.29#ibcon#read 6, iclass 11, count 0 2006.286.04:43:04.29#ibcon#end of sib2, iclass 11, count 0 2006.286.04:43:04.29#ibcon#*after write, iclass 11, count 0 2006.286.04:43:04.29#ibcon#*before return 0, iclass 11, count 0 2006.286.04:43:04.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:43:04.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:43:04.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.04:43:04.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.04:43:04.29$vck44/vb=2,5 2006.286.04:43:04.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.04:43:04.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.04:43:04.29#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:04.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:43:04.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:43:04.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:43:04.35#ibcon#enter wrdev, iclass 13, count 2 2006.286.04:43:04.35#ibcon#first serial, iclass 13, count 2 2006.286.04:43:04.35#ibcon#enter sib2, iclass 13, count 2 2006.286.04:43:04.35#ibcon#flushed, iclass 13, count 2 2006.286.04:43:04.35#ibcon#about to write, iclass 13, count 2 2006.286.04:43:04.35#ibcon#wrote, iclass 13, count 2 2006.286.04:43:04.35#ibcon#about to read 3, iclass 13, count 2 2006.286.04:43:04.37#ibcon#read 3, iclass 13, count 2 2006.286.04:43:04.37#ibcon#about to read 4, iclass 13, count 2 2006.286.04:43:04.37#ibcon#read 4, iclass 13, count 2 2006.286.04:43:04.37#ibcon#about to read 5, iclass 13, count 2 2006.286.04:43:04.37#ibcon#read 5, iclass 13, count 2 2006.286.04:43:04.37#ibcon#about to read 6, iclass 13, count 2 2006.286.04:43:04.37#ibcon#read 6, iclass 13, count 2 2006.286.04:43:04.37#ibcon#end of sib2, iclass 13, count 2 2006.286.04:43:04.37#ibcon#*mode == 0, iclass 13, count 2 2006.286.04:43:04.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.04:43:04.37#ibcon#[27=AT02-05\r\n] 2006.286.04:43:04.37#ibcon#*before write, iclass 13, count 2 2006.286.04:43:04.37#ibcon#enter sib2, iclass 13, count 2 2006.286.04:43:04.37#ibcon#flushed, iclass 13, count 2 2006.286.04:43:04.37#ibcon#about to write, iclass 13, count 2 2006.286.04:43:04.37#ibcon#wrote, iclass 13, count 2 2006.286.04:43:04.37#ibcon#about to read 3, iclass 13, count 2 2006.286.04:43:04.40#ibcon#read 3, iclass 13, count 2 2006.286.04:43:04.40#ibcon#about to read 4, iclass 13, count 2 2006.286.04:43:04.40#ibcon#read 4, iclass 13, count 2 2006.286.04:43:04.40#ibcon#about to read 5, iclass 13, count 2 2006.286.04:43:04.40#ibcon#read 5, iclass 13, count 2 2006.286.04:43:04.40#ibcon#about to read 6, iclass 13, count 2 2006.286.04:43:04.40#ibcon#read 6, iclass 13, count 2 2006.286.04:43:04.40#ibcon#end of sib2, iclass 13, count 2 2006.286.04:43:04.40#ibcon#*after write, iclass 13, count 2 2006.286.04:43:04.40#ibcon#*before return 0, iclass 13, count 2 2006.286.04:43:04.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:43:04.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:43:04.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.04:43:04.40#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:04.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:43:04.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:43:04.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:43:04.52#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:43:04.52#ibcon#first serial, iclass 13, count 0 2006.286.04:43:04.52#ibcon#enter sib2, iclass 13, count 0 2006.286.04:43:04.52#ibcon#flushed, iclass 13, count 0 2006.286.04:43:04.52#ibcon#about to write, iclass 13, count 0 2006.286.04:43:04.52#ibcon#wrote, iclass 13, count 0 2006.286.04:43:04.52#ibcon#about to read 3, iclass 13, count 0 2006.286.04:43:04.54#ibcon#read 3, iclass 13, count 0 2006.286.04:43:04.54#ibcon#about to read 4, iclass 13, count 0 2006.286.04:43:04.54#ibcon#read 4, iclass 13, count 0 2006.286.04:43:04.54#ibcon#about to read 5, iclass 13, count 0 2006.286.04:43:04.54#ibcon#read 5, iclass 13, count 0 2006.286.04:43:04.54#ibcon#about to read 6, iclass 13, count 0 2006.286.04:43:04.54#ibcon#read 6, iclass 13, count 0 2006.286.04:43:04.54#ibcon#end of sib2, iclass 13, count 0 2006.286.04:43:04.54#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:43:04.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:43:04.54#ibcon#[27=USB\r\n] 2006.286.04:43:04.54#ibcon#*before write, iclass 13, count 0 2006.286.04:43:04.54#ibcon#enter sib2, iclass 13, count 0 2006.286.04:43:04.54#ibcon#flushed, iclass 13, count 0 2006.286.04:43:04.54#ibcon#about to write, iclass 13, count 0 2006.286.04:43:04.54#ibcon#wrote, iclass 13, count 0 2006.286.04:43:04.54#ibcon#about to read 3, iclass 13, count 0 2006.286.04:43:04.57#ibcon#read 3, iclass 13, count 0 2006.286.04:43:04.57#ibcon#about to read 4, iclass 13, count 0 2006.286.04:43:04.57#ibcon#read 4, iclass 13, count 0 2006.286.04:43:04.57#ibcon#about to read 5, iclass 13, count 0 2006.286.04:43:04.57#ibcon#read 5, iclass 13, count 0 2006.286.04:43:04.57#ibcon#about to read 6, iclass 13, count 0 2006.286.04:43:04.57#ibcon#read 6, iclass 13, count 0 2006.286.04:43:04.57#ibcon#end of sib2, iclass 13, count 0 2006.286.04:43:04.57#ibcon#*after write, iclass 13, count 0 2006.286.04:43:04.57#ibcon#*before return 0, iclass 13, count 0 2006.286.04:43:04.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:43:04.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:43:04.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:43:04.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:43:04.57$vck44/vblo=3,649.99 2006.286.04:43:04.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.04:43:04.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.04:43:04.67#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:04.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:43:04.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:43:04.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:43:04.67#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:43:04.67#ibcon#first serial, iclass 15, count 0 2006.286.04:43:04.67#ibcon#enter sib2, iclass 15, count 0 2006.286.04:43:04.67#ibcon#flushed, iclass 15, count 0 2006.286.04:43:04.67#ibcon#about to write, iclass 15, count 0 2006.286.04:43:04.67#ibcon#wrote, iclass 15, count 0 2006.286.04:43:04.67#ibcon#about to read 3, iclass 15, count 0 2006.286.04:43:04.68#ibcon#read 3, iclass 15, count 0 2006.286.04:43:04.68#ibcon#about to read 4, iclass 15, count 0 2006.286.04:43:04.68#ibcon#read 4, iclass 15, count 0 2006.286.04:43:04.68#ibcon#about to read 5, iclass 15, count 0 2006.286.04:43:04.68#ibcon#read 5, iclass 15, count 0 2006.286.04:43:04.68#ibcon#about to read 6, iclass 15, count 0 2006.286.04:43:04.68#ibcon#read 6, iclass 15, count 0 2006.286.04:43:04.68#ibcon#end of sib2, iclass 15, count 0 2006.286.04:43:04.68#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:43:04.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:43:04.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:43:04.68#ibcon#*before write, iclass 15, count 0 2006.286.04:43:04.68#ibcon#enter sib2, iclass 15, count 0 2006.286.04:43:04.68#ibcon#flushed, iclass 15, count 0 2006.286.04:43:04.68#ibcon#about to write, iclass 15, count 0 2006.286.04:43:04.68#ibcon#wrote, iclass 15, count 0 2006.286.04:43:04.68#ibcon#about to read 3, iclass 15, count 0 2006.286.04:43:04.71#abcon#<5=/04 3.8 7.1 22.20 761014.8\r\n> 2006.286.04:43:04.72#ibcon#read 3, iclass 15, count 0 2006.286.04:43:04.72#ibcon#about to read 4, iclass 15, count 0 2006.286.04:43:04.72#ibcon#read 4, iclass 15, count 0 2006.286.04:43:04.72#ibcon#about to read 5, iclass 15, count 0 2006.286.04:43:04.72#ibcon#read 5, iclass 15, count 0 2006.286.04:43:04.72#ibcon#about to read 6, iclass 15, count 0 2006.286.04:43:04.72#ibcon#read 6, iclass 15, count 0 2006.286.04:43:04.72#ibcon#end of sib2, iclass 15, count 0 2006.286.04:43:04.72#ibcon#*after write, iclass 15, count 0 2006.286.04:43:04.72#ibcon#*before return 0, iclass 15, count 0 2006.286.04:43:04.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:43:04.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:43:04.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:43:04.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:43:04.72$vck44/vb=3,4 2006.286.04:43:04.72#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.04:43:04.72#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.04:43:04.72#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:04.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:43:04.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:43:04.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:43:04.72#ibcon#enter wrdev, iclass 20, count 2 2006.286.04:43:04.72#ibcon#first serial, iclass 20, count 2 2006.286.04:43:04.72#ibcon#enter sib2, iclass 20, count 2 2006.286.04:43:04.72#ibcon#flushed, iclass 20, count 2 2006.286.04:43:04.72#ibcon#about to write, iclass 20, count 2 2006.286.04:43:04.72#ibcon#wrote, iclass 20, count 2 2006.286.04:43:04.72#ibcon#about to read 3, iclass 20, count 2 2006.286.04:43:04.73#abcon#{5=INTERFACE CLEAR} 2006.286.04:43:04.74#ibcon#read 3, iclass 20, count 2 2006.286.04:43:04.74#ibcon#about to read 4, iclass 20, count 2 2006.286.04:43:04.74#ibcon#read 4, iclass 20, count 2 2006.286.04:43:04.74#ibcon#about to read 5, iclass 20, count 2 2006.286.04:43:04.74#ibcon#read 5, iclass 20, count 2 2006.286.04:43:04.74#ibcon#about to read 6, iclass 20, count 2 2006.286.04:43:04.74#ibcon#read 6, iclass 20, count 2 2006.286.04:43:04.74#ibcon#end of sib2, iclass 20, count 2 2006.286.04:43:04.74#ibcon#*mode == 0, iclass 20, count 2 2006.286.04:43:04.74#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.04:43:04.74#ibcon#[27=AT03-04\r\n] 2006.286.04:43:04.74#ibcon#*before write, iclass 20, count 2 2006.286.04:43:04.74#ibcon#enter sib2, iclass 20, count 2 2006.286.04:43:04.74#ibcon#flushed, iclass 20, count 2 2006.286.04:43:04.74#ibcon#about to write, iclass 20, count 2 2006.286.04:43:04.74#ibcon#wrote, iclass 20, count 2 2006.286.04:43:04.74#ibcon#about to read 3, iclass 20, count 2 2006.286.04:43:04.77#ibcon#read 3, iclass 20, count 2 2006.286.04:43:04.77#ibcon#about to read 4, iclass 20, count 2 2006.286.04:43:04.77#ibcon#read 4, iclass 20, count 2 2006.286.04:43:04.77#ibcon#about to read 5, iclass 20, count 2 2006.286.04:43:04.77#ibcon#read 5, iclass 20, count 2 2006.286.04:43:04.77#ibcon#about to read 6, iclass 20, count 2 2006.286.04:43:04.77#ibcon#read 6, iclass 20, count 2 2006.286.04:43:04.77#ibcon#end of sib2, iclass 20, count 2 2006.286.04:43:04.77#ibcon#*after write, iclass 20, count 2 2006.286.04:43:04.77#ibcon#*before return 0, iclass 20, count 2 2006.286.04:43:04.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:43:04.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:43:04.77#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.04:43:04.77#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:04.77#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:43:04.79#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:43:04.89#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:43:04.89#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:43:04.89#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:43:04.89#ibcon#first serial, iclass 20, count 0 2006.286.04:43:04.89#ibcon#enter sib2, iclass 20, count 0 2006.286.04:43:04.89#ibcon#flushed, iclass 20, count 0 2006.286.04:43:04.89#ibcon#about to write, iclass 20, count 0 2006.286.04:43:04.89#ibcon#wrote, iclass 20, count 0 2006.286.04:43:04.89#ibcon#about to read 3, iclass 20, count 0 2006.286.04:43:04.91#ibcon#read 3, iclass 20, count 0 2006.286.04:43:04.91#ibcon#about to read 4, iclass 20, count 0 2006.286.04:43:04.91#ibcon#read 4, iclass 20, count 0 2006.286.04:43:04.91#ibcon#about to read 5, iclass 20, count 0 2006.286.04:43:04.91#ibcon#read 5, iclass 20, count 0 2006.286.04:43:04.91#ibcon#about to read 6, iclass 20, count 0 2006.286.04:43:04.91#ibcon#read 6, iclass 20, count 0 2006.286.04:43:04.91#ibcon#end of sib2, iclass 20, count 0 2006.286.04:43:04.91#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:43:04.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:43:04.91#ibcon#[27=USB\r\n] 2006.286.04:43:04.91#ibcon#*before write, iclass 20, count 0 2006.286.04:43:04.91#ibcon#enter sib2, iclass 20, count 0 2006.286.04:43:04.91#ibcon#flushed, iclass 20, count 0 2006.286.04:43:04.91#ibcon#about to write, iclass 20, count 0 2006.286.04:43:04.91#ibcon#wrote, iclass 20, count 0 2006.286.04:43:04.91#ibcon#about to read 3, iclass 20, count 0 2006.286.04:43:04.94#ibcon#read 3, iclass 20, count 0 2006.286.04:43:04.94#ibcon#about to read 4, iclass 20, count 0 2006.286.04:43:04.94#ibcon#read 4, iclass 20, count 0 2006.286.04:43:04.94#ibcon#about to read 5, iclass 20, count 0 2006.286.04:43:04.94#ibcon#read 5, iclass 20, count 0 2006.286.04:43:04.94#ibcon#about to read 6, iclass 20, count 0 2006.286.04:43:04.94#ibcon#read 6, iclass 20, count 0 2006.286.04:43:04.94#ibcon#end of sib2, iclass 20, count 0 2006.286.04:43:04.94#ibcon#*after write, iclass 20, count 0 2006.286.04:43:04.94#ibcon#*before return 0, iclass 20, count 0 2006.286.04:43:04.94#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:43:04.94#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:43:04.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:43:04.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:43:04.94$vck44/vblo=4,679.99 2006.286.04:43:04.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.04:43:04.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.04:43:04.94#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:04.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:43:04.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:43:04.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:43:04.94#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:43:04.94#ibcon#first serial, iclass 23, count 0 2006.286.04:43:04.94#ibcon#enter sib2, iclass 23, count 0 2006.286.04:43:04.94#ibcon#flushed, iclass 23, count 0 2006.286.04:43:04.94#ibcon#about to write, iclass 23, count 0 2006.286.04:43:04.94#ibcon#wrote, iclass 23, count 0 2006.286.04:43:04.94#ibcon#about to read 3, iclass 23, count 0 2006.286.04:43:04.96#ibcon#read 3, iclass 23, count 0 2006.286.04:43:04.96#ibcon#about to read 4, iclass 23, count 0 2006.286.04:43:04.96#ibcon#read 4, iclass 23, count 0 2006.286.04:43:04.96#ibcon#about to read 5, iclass 23, count 0 2006.286.04:43:04.96#ibcon#read 5, iclass 23, count 0 2006.286.04:43:04.96#ibcon#about to read 6, iclass 23, count 0 2006.286.04:43:04.96#ibcon#read 6, iclass 23, count 0 2006.286.04:43:04.96#ibcon#end of sib2, iclass 23, count 0 2006.286.04:43:04.96#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:43:04.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:43:04.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:43:04.96#ibcon#*before write, iclass 23, count 0 2006.286.04:43:04.96#ibcon#enter sib2, iclass 23, count 0 2006.286.04:43:04.96#ibcon#flushed, iclass 23, count 0 2006.286.04:43:04.96#ibcon#about to write, iclass 23, count 0 2006.286.04:43:04.96#ibcon#wrote, iclass 23, count 0 2006.286.04:43:04.96#ibcon#about to read 3, iclass 23, count 0 2006.286.04:43:05.00#ibcon#read 3, iclass 23, count 0 2006.286.04:43:05.00#ibcon#about to read 4, iclass 23, count 0 2006.286.04:43:05.00#ibcon#read 4, iclass 23, count 0 2006.286.04:43:05.00#ibcon#about to read 5, iclass 23, count 0 2006.286.04:43:05.00#ibcon#read 5, iclass 23, count 0 2006.286.04:43:05.00#ibcon#about to read 6, iclass 23, count 0 2006.286.04:43:05.00#ibcon#read 6, iclass 23, count 0 2006.286.04:43:05.00#ibcon#end of sib2, iclass 23, count 0 2006.286.04:43:05.00#ibcon#*after write, iclass 23, count 0 2006.286.04:43:05.00#ibcon#*before return 0, iclass 23, count 0 2006.286.04:43:05.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:43:05.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:43:05.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:43:05.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:43:05.00$vck44/vb=4,5 2006.286.04:43:05.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.04:43:05.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.04:43:05.00#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:05.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:43:05.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:43:05.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:43:05.06#ibcon#enter wrdev, iclass 25, count 2 2006.286.04:43:05.06#ibcon#first serial, iclass 25, count 2 2006.286.04:43:05.06#ibcon#enter sib2, iclass 25, count 2 2006.286.04:43:05.06#ibcon#flushed, iclass 25, count 2 2006.286.04:43:05.06#ibcon#about to write, iclass 25, count 2 2006.286.04:43:05.06#ibcon#wrote, iclass 25, count 2 2006.286.04:43:05.06#ibcon#about to read 3, iclass 25, count 2 2006.286.04:43:05.08#ibcon#read 3, iclass 25, count 2 2006.286.04:43:05.08#ibcon#about to read 4, iclass 25, count 2 2006.286.04:43:05.08#ibcon#read 4, iclass 25, count 2 2006.286.04:43:05.08#ibcon#about to read 5, iclass 25, count 2 2006.286.04:43:05.08#ibcon#read 5, iclass 25, count 2 2006.286.04:43:05.08#ibcon#about to read 6, iclass 25, count 2 2006.286.04:43:05.08#ibcon#read 6, iclass 25, count 2 2006.286.04:43:05.08#ibcon#end of sib2, iclass 25, count 2 2006.286.04:43:05.08#ibcon#*mode == 0, iclass 25, count 2 2006.286.04:43:05.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.04:43:05.08#ibcon#[27=AT04-05\r\n] 2006.286.04:43:05.08#ibcon#*before write, iclass 25, count 2 2006.286.04:43:05.08#ibcon#enter sib2, iclass 25, count 2 2006.286.04:43:05.08#ibcon#flushed, iclass 25, count 2 2006.286.04:43:05.08#ibcon#about to write, iclass 25, count 2 2006.286.04:43:05.08#ibcon#wrote, iclass 25, count 2 2006.286.04:43:05.08#ibcon#about to read 3, iclass 25, count 2 2006.286.04:43:05.11#ibcon#read 3, iclass 25, count 2 2006.286.04:43:05.11#ibcon#about to read 4, iclass 25, count 2 2006.286.04:43:05.11#ibcon#read 4, iclass 25, count 2 2006.286.04:43:05.11#ibcon#about to read 5, iclass 25, count 2 2006.286.04:43:05.11#ibcon#read 5, iclass 25, count 2 2006.286.04:43:05.11#ibcon#about to read 6, iclass 25, count 2 2006.286.04:43:05.11#ibcon#read 6, iclass 25, count 2 2006.286.04:43:05.11#ibcon#end of sib2, iclass 25, count 2 2006.286.04:43:05.11#ibcon#*after write, iclass 25, count 2 2006.286.04:43:05.11#ibcon#*before return 0, iclass 25, count 2 2006.286.04:43:05.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:43:05.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:43:05.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.04:43:05.11#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:05.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:43:05.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:43:05.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:43:05.23#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:43:05.23#ibcon#first serial, iclass 25, count 0 2006.286.04:43:05.23#ibcon#enter sib2, iclass 25, count 0 2006.286.04:43:05.23#ibcon#flushed, iclass 25, count 0 2006.286.04:43:05.23#ibcon#about to write, iclass 25, count 0 2006.286.04:43:05.23#ibcon#wrote, iclass 25, count 0 2006.286.04:43:05.23#ibcon#about to read 3, iclass 25, count 0 2006.286.04:43:05.25#ibcon#read 3, iclass 25, count 0 2006.286.04:43:05.25#ibcon#about to read 4, iclass 25, count 0 2006.286.04:43:05.25#ibcon#read 4, iclass 25, count 0 2006.286.04:43:05.25#ibcon#about to read 5, iclass 25, count 0 2006.286.04:43:05.25#ibcon#read 5, iclass 25, count 0 2006.286.04:43:05.25#ibcon#about to read 6, iclass 25, count 0 2006.286.04:43:05.25#ibcon#read 6, iclass 25, count 0 2006.286.04:43:05.25#ibcon#end of sib2, iclass 25, count 0 2006.286.04:43:05.25#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:43:05.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:43:05.25#ibcon#[27=USB\r\n] 2006.286.04:43:05.25#ibcon#*before write, iclass 25, count 0 2006.286.04:43:05.25#ibcon#enter sib2, iclass 25, count 0 2006.286.04:43:05.25#ibcon#flushed, iclass 25, count 0 2006.286.04:43:05.25#ibcon#about to write, iclass 25, count 0 2006.286.04:43:05.25#ibcon#wrote, iclass 25, count 0 2006.286.04:43:05.25#ibcon#about to read 3, iclass 25, count 0 2006.286.04:43:05.28#ibcon#read 3, iclass 25, count 0 2006.286.04:43:05.28#ibcon#about to read 4, iclass 25, count 0 2006.286.04:43:05.28#ibcon#read 4, iclass 25, count 0 2006.286.04:43:05.28#ibcon#about to read 5, iclass 25, count 0 2006.286.04:43:05.28#ibcon#read 5, iclass 25, count 0 2006.286.04:43:05.28#ibcon#about to read 6, iclass 25, count 0 2006.286.04:43:05.28#ibcon#read 6, iclass 25, count 0 2006.286.04:43:05.28#ibcon#end of sib2, iclass 25, count 0 2006.286.04:43:05.28#ibcon#*after write, iclass 25, count 0 2006.286.04:43:05.28#ibcon#*before return 0, iclass 25, count 0 2006.286.04:43:05.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:43:05.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:43:05.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:43:05.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:43:05.28$vck44/vblo=5,709.99 2006.286.04:43:05.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.04:43:05.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.04:43:05.28#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:05.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:43:05.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:43:05.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:43:05.28#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:43:05.28#ibcon#first serial, iclass 27, count 0 2006.286.04:43:05.28#ibcon#enter sib2, iclass 27, count 0 2006.286.04:43:05.28#ibcon#flushed, iclass 27, count 0 2006.286.04:43:05.28#ibcon#about to write, iclass 27, count 0 2006.286.04:43:05.28#ibcon#wrote, iclass 27, count 0 2006.286.04:43:05.28#ibcon#about to read 3, iclass 27, count 0 2006.286.04:43:05.30#ibcon#read 3, iclass 27, count 0 2006.286.04:43:05.30#ibcon#about to read 4, iclass 27, count 0 2006.286.04:43:05.30#ibcon#read 4, iclass 27, count 0 2006.286.04:43:05.30#ibcon#about to read 5, iclass 27, count 0 2006.286.04:43:05.30#ibcon#read 5, iclass 27, count 0 2006.286.04:43:05.30#ibcon#about to read 6, iclass 27, count 0 2006.286.04:43:05.30#ibcon#read 6, iclass 27, count 0 2006.286.04:43:05.30#ibcon#end of sib2, iclass 27, count 0 2006.286.04:43:05.30#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:43:05.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:43:05.30#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:43:05.30#ibcon#*before write, iclass 27, count 0 2006.286.04:43:05.30#ibcon#enter sib2, iclass 27, count 0 2006.286.04:43:05.30#ibcon#flushed, iclass 27, count 0 2006.286.04:43:05.30#ibcon#about to write, iclass 27, count 0 2006.286.04:43:05.30#ibcon#wrote, iclass 27, count 0 2006.286.04:43:05.30#ibcon#about to read 3, iclass 27, count 0 2006.286.04:43:05.34#ibcon#read 3, iclass 27, count 0 2006.286.04:43:05.34#ibcon#about to read 4, iclass 27, count 0 2006.286.04:43:05.34#ibcon#read 4, iclass 27, count 0 2006.286.04:43:05.34#ibcon#about to read 5, iclass 27, count 0 2006.286.04:43:05.34#ibcon#read 5, iclass 27, count 0 2006.286.04:43:05.34#ibcon#about to read 6, iclass 27, count 0 2006.286.04:43:05.34#ibcon#read 6, iclass 27, count 0 2006.286.04:43:05.34#ibcon#end of sib2, iclass 27, count 0 2006.286.04:43:05.34#ibcon#*after write, iclass 27, count 0 2006.286.04:43:05.34#ibcon#*before return 0, iclass 27, count 0 2006.286.04:43:05.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:43:05.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:43:05.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:43:05.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:43:05.34$vck44/vb=5,4 2006.286.04:43:05.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.04:43:05.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.04:43:05.34#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:05.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:43:05.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:43:05.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:43:05.40#ibcon#enter wrdev, iclass 29, count 2 2006.286.04:43:05.40#ibcon#first serial, iclass 29, count 2 2006.286.04:43:05.40#ibcon#enter sib2, iclass 29, count 2 2006.286.04:43:05.40#ibcon#flushed, iclass 29, count 2 2006.286.04:43:05.40#ibcon#about to write, iclass 29, count 2 2006.286.04:43:05.40#ibcon#wrote, iclass 29, count 2 2006.286.04:43:05.40#ibcon#about to read 3, iclass 29, count 2 2006.286.04:43:05.42#ibcon#read 3, iclass 29, count 2 2006.286.04:43:05.42#ibcon#about to read 4, iclass 29, count 2 2006.286.04:43:05.42#ibcon#read 4, iclass 29, count 2 2006.286.04:43:05.42#ibcon#about to read 5, iclass 29, count 2 2006.286.04:43:05.42#ibcon#read 5, iclass 29, count 2 2006.286.04:43:05.42#ibcon#about to read 6, iclass 29, count 2 2006.286.04:43:05.42#ibcon#read 6, iclass 29, count 2 2006.286.04:43:05.42#ibcon#end of sib2, iclass 29, count 2 2006.286.04:43:05.42#ibcon#*mode == 0, iclass 29, count 2 2006.286.04:43:05.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.04:43:05.42#ibcon#[27=AT05-04\r\n] 2006.286.04:43:05.42#ibcon#*before write, iclass 29, count 2 2006.286.04:43:05.42#ibcon#enter sib2, iclass 29, count 2 2006.286.04:43:05.42#ibcon#flushed, iclass 29, count 2 2006.286.04:43:05.42#ibcon#about to write, iclass 29, count 2 2006.286.04:43:05.42#ibcon#wrote, iclass 29, count 2 2006.286.04:43:05.42#ibcon#about to read 3, iclass 29, count 2 2006.286.04:43:05.45#ibcon#read 3, iclass 29, count 2 2006.286.04:43:05.45#ibcon#about to read 4, iclass 29, count 2 2006.286.04:43:05.45#ibcon#read 4, iclass 29, count 2 2006.286.04:43:05.45#ibcon#about to read 5, iclass 29, count 2 2006.286.04:43:05.45#ibcon#read 5, iclass 29, count 2 2006.286.04:43:05.45#ibcon#about to read 6, iclass 29, count 2 2006.286.04:43:05.45#ibcon#read 6, iclass 29, count 2 2006.286.04:43:05.45#ibcon#end of sib2, iclass 29, count 2 2006.286.04:43:05.45#ibcon#*after write, iclass 29, count 2 2006.286.04:43:05.45#ibcon#*before return 0, iclass 29, count 2 2006.286.04:43:05.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:43:05.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:43:05.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.04:43:05.45#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:05.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:43:05.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:43:05.73#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:43:05.73#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:43:05.73#ibcon#first serial, iclass 29, count 0 2006.286.04:43:05.73#ibcon#enter sib2, iclass 29, count 0 2006.286.04:43:05.73#ibcon#flushed, iclass 29, count 0 2006.286.04:43:05.73#ibcon#about to write, iclass 29, count 0 2006.286.04:43:05.73#ibcon#wrote, iclass 29, count 0 2006.286.04:43:05.73#ibcon#about to read 3, iclass 29, count 0 2006.286.04:43:05.74#ibcon#read 3, iclass 29, count 0 2006.286.04:43:05.74#ibcon#about to read 4, iclass 29, count 0 2006.286.04:43:05.74#ibcon#read 4, iclass 29, count 0 2006.286.04:43:05.74#ibcon#about to read 5, iclass 29, count 0 2006.286.04:43:05.74#ibcon#read 5, iclass 29, count 0 2006.286.04:43:05.74#ibcon#about to read 6, iclass 29, count 0 2006.286.04:43:05.74#ibcon#read 6, iclass 29, count 0 2006.286.04:43:05.74#ibcon#end of sib2, iclass 29, count 0 2006.286.04:43:05.74#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:43:05.74#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:43:05.74#ibcon#[27=USB\r\n] 2006.286.04:43:05.74#ibcon#*before write, iclass 29, count 0 2006.286.04:43:05.74#ibcon#enter sib2, iclass 29, count 0 2006.286.04:43:05.74#ibcon#flushed, iclass 29, count 0 2006.286.04:43:05.74#ibcon#about to write, iclass 29, count 0 2006.286.04:43:05.74#ibcon#wrote, iclass 29, count 0 2006.286.04:43:05.74#ibcon#about to read 3, iclass 29, count 0 2006.286.04:43:05.77#ibcon#read 3, iclass 29, count 0 2006.286.04:43:05.77#ibcon#about to read 4, iclass 29, count 0 2006.286.04:43:05.77#ibcon#read 4, iclass 29, count 0 2006.286.04:43:05.77#ibcon#about to read 5, iclass 29, count 0 2006.286.04:43:05.77#ibcon#read 5, iclass 29, count 0 2006.286.04:43:05.77#ibcon#about to read 6, iclass 29, count 0 2006.286.04:43:05.77#ibcon#read 6, iclass 29, count 0 2006.286.04:43:05.77#ibcon#end of sib2, iclass 29, count 0 2006.286.04:43:05.77#ibcon#*after write, iclass 29, count 0 2006.286.04:43:05.77#ibcon#*before return 0, iclass 29, count 0 2006.286.04:43:05.77#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:43:05.77#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:43:05.77#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:43:05.77#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:43:05.77$vck44/vblo=6,719.99 2006.286.04:43:05.77#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.04:43:05.77#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.04:43:05.77#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:05.77#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:43:05.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:43:05.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:43:05.77#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:43:05.77#ibcon#first serial, iclass 31, count 0 2006.286.04:43:05.77#ibcon#enter sib2, iclass 31, count 0 2006.286.04:43:05.77#ibcon#flushed, iclass 31, count 0 2006.286.04:43:05.77#ibcon#about to write, iclass 31, count 0 2006.286.04:43:05.77#ibcon#wrote, iclass 31, count 0 2006.286.04:43:05.77#ibcon#about to read 3, iclass 31, count 0 2006.286.04:43:05.79#ibcon#read 3, iclass 31, count 0 2006.286.04:43:05.79#ibcon#about to read 4, iclass 31, count 0 2006.286.04:43:05.79#ibcon#read 4, iclass 31, count 0 2006.286.04:43:05.79#ibcon#about to read 5, iclass 31, count 0 2006.286.04:43:05.79#ibcon#read 5, iclass 31, count 0 2006.286.04:43:05.79#ibcon#about to read 6, iclass 31, count 0 2006.286.04:43:05.79#ibcon#read 6, iclass 31, count 0 2006.286.04:43:05.79#ibcon#end of sib2, iclass 31, count 0 2006.286.04:43:05.79#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:43:05.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:43:05.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:43:05.79#ibcon#*before write, iclass 31, count 0 2006.286.04:43:05.79#ibcon#enter sib2, iclass 31, count 0 2006.286.04:43:05.79#ibcon#flushed, iclass 31, count 0 2006.286.04:43:05.79#ibcon#about to write, iclass 31, count 0 2006.286.04:43:05.79#ibcon#wrote, iclass 31, count 0 2006.286.04:43:05.79#ibcon#about to read 3, iclass 31, count 0 2006.286.04:43:05.83#ibcon#read 3, iclass 31, count 0 2006.286.04:43:05.83#ibcon#about to read 4, iclass 31, count 0 2006.286.04:43:05.83#ibcon#read 4, iclass 31, count 0 2006.286.04:43:05.83#ibcon#about to read 5, iclass 31, count 0 2006.286.04:43:05.83#ibcon#read 5, iclass 31, count 0 2006.286.04:43:05.83#ibcon#about to read 6, iclass 31, count 0 2006.286.04:43:05.83#ibcon#read 6, iclass 31, count 0 2006.286.04:43:05.83#ibcon#end of sib2, iclass 31, count 0 2006.286.04:43:05.83#ibcon#*after write, iclass 31, count 0 2006.286.04:43:05.83#ibcon#*before return 0, iclass 31, count 0 2006.286.04:43:05.83#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:43:05.83#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:43:05.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:43:05.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:43:05.83$vck44/vb=6,3 2006.286.04:43:05.83#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.04:43:05.83#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.04:43:05.83#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:05.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:43:05.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:43:05.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:43:05.89#ibcon#enter wrdev, iclass 33, count 2 2006.286.04:43:05.89#ibcon#first serial, iclass 33, count 2 2006.286.04:43:05.89#ibcon#enter sib2, iclass 33, count 2 2006.286.04:43:05.89#ibcon#flushed, iclass 33, count 2 2006.286.04:43:05.89#ibcon#about to write, iclass 33, count 2 2006.286.04:43:05.89#ibcon#wrote, iclass 33, count 2 2006.286.04:43:05.89#ibcon#about to read 3, iclass 33, count 2 2006.286.04:43:05.91#ibcon#read 3, iclass 33, count 2 2006.286.04:43:05.91#ibcon#about to read 4, iclass 33, count 2 2006.286.04:43:05.91#ibcon#read 4, iclass 33, count 2 2006.286.04:43:05.91#ibcon#about to read 5, iclass 33, count 2 2006.286.04:43:05.91#ibcon#read 5, iclass 33, count 2 2006.286.04:43:05.91#ibcon#about to read 6, iclass 33, count 2 2006.286.04:43:05.91#ibcon#read 6, iclass 33, count 2 2006.286.04:43:05.91#ibcon#end of sib2, iclass 33, count 2 2006.286.04:43:05.91#ibcon#*mode == 0, iclass 33, count 2 2006.286.04:43:05.91#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.04:43:05.91#ibcon#[27=AT06-03\r\n] 2006.286.04:43:05.91#ibcon#*before write, iclass 33, count 2 2006.286.04:43:05.91#ibcon#enter sib2, iclass 33, count 2 2006.286.04:43:05.91#ibcon#flushed, iclass 33, count 2 2006.286.04:43:05.91#ibcon#about to write, iclass 33, count 2 2006.286.04:43:05.91#ibcon#wrote, iclass 33, count 2 2006.286.04:43:05.91#ibcon#about to read 3, iclass 33, count 2 2006.286.04:43:05.94#ibcon#read 3, iclass 33, count 2 2006.286.04:43:05.94#ibcon#about to read 4, iclass 33, count 2 2006.286.04:43:05.94#ibcon#read 4, iclass 33, count 2 2006.286.04:43:05.94#ibcon#about to read 5, iclass 33, count 2 2006.286.04:43:05.94#ibcon#read 5, iclass 33, count 2 2006.286.04:43:05.94#ibcon#about to read 6, iclass 33, count 2 2006.286.04:43:05.94#ibcon#read 6, iclass 33, count 2 2006.286.04:43:05.94#ibcon#end of sib2, iclass 33, count 2 2006.286.04:43:05.94#ibcon#*after write, iclass 33, count 2 2006.286.04:43:05.94#ibcon#*before return 0, iclass 33, count 2 2006.286.04:43:05.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:43:05.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:43:05.94#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.04:43:05.94#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:05.94#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:43:06.06#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:43:06.06#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:43:06.06#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:43:06.06#ibcon#first serial, iclass 33, count 0 2006.286.04:43:06.06#ibcon#enter sib2, iclass 33, count 0 2006.286.04:43:06.06#ibcon#flushed, iclass 33, count 0 2006.286.04:43:06.06#ibcon#about to write, iclass 33, count 0 2006.286.04:43:06.06#ibcon#wrote, iclass 33, count 0 2006.286.04:43:06.06#ibcon#about to read 3, iclass 33, count 0 2006.286.04:43:06.08#ibcon#read 3, iclass 33, count 0 2006.286.04:43:06.08#ibcon#about to read 4, iclass 33, count 0 2006.286.04:43:06.08#ibcon#read 4, iclass 33, count 0 2006.286.04:43:06.08#ibcon#about to read 5, iclass 33, count 0 2006.286.04:43:06.08#ibcon#read 5, iclass 33, count 0 2006.286.04:43:06.08#ibcon#about to read 6, iclass 33, count 0 2006.286.04:43:06.08#ibcon#read 6, iclass 33, count 0 2006.286.04:43:06.08#ibcon#end of sib2, iclass 33, count 0 2006.286.04:43:06.08#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:43:06.08#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:43:06.08#ibcon#[27=USB\r\n] 2006.286.04:43:06.08#ibcon#*before write, iclass 33, count 0 2006.286.04:43:06.08#ibcon#enter sib2, iclass 33, count 0 2006.286.04:43:06.08#ibcon#flushed, iclass 33, count 0 2006.286.04:43:06.08#ibcon#about to write, iclass 33, count 0 2006.286.04:43:06.08#ibcon#wrote, iclass 33, count 0 2006.286.04:43:06.08#ibcon#about to read 3, iclass 33, count 0 2006.286.04:43:06.11#ibcon#read 3, iclass 33, count 0 2006.286.04:43:06.11#ibcon#about to read 4, iclass 33, count 0 2006.286.04:43:06.11#ibcon#read 4, iclass 33, count 0 2006.286.04:43:06.11#ibcon#about to read 5, iclass 33, count 0 2006.286.04:43:06.11#ibcon#read 5, iclass 33, count 0 2006.286.04:43:06.11#ibcon#about to read 6, iclass 33, count 0 2006.286.04:43:06.11#ibcon#read 6, iclass 33, count 0 2006.286.04:43:06.11#ibcon#end of sib2, iclass 33, count 0 2006.286.04:43:06.11#ibcon#*after write, iclass 33, count 0 2006.286.04:43:06.11#ibcon#*before return 0, iclass 33, count 0 2006.286.04:43:06.11#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:43:06.11#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:43:06.11#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:43:06.11#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:43:06.11$vck44/vblo=7,734.99 2006.286.04:43:06.11#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.04:43:06.11#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.04:43:06.11#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:06.11#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:43:06.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:43:06.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:43:06.11#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:43:06.11#ibcon#first serial, iclass 35, count 0 2006.286.04:43:06.11#ibcon#enter sib2, iclass 35, count 0 2006.286.04:43:06.11#ibcon#flushed, iclass 35, count 0 2006.286.04:43:06.11#ibcon#about to write, iclass 35, count 0 2006.286.04:43:06.11#ibcon#wrote, iclass 35, count 0 2006.286.04:43:06.11#ibcon#about to read 3, iclass 35, count 0 2006.286.04:43:06.13#ibcon#read 3, iclass 35, count 0 2006.286.04:43:06.13#ibcon#about to read 4, iclass 35, count 0 2006.286.04:43:06.13#ibcon#read 4, iclass 35, count 0 2006.286.04:43:06.13#ibcon#about to read 5, iclass 35, count 0 2006.286.04:43:06.13#ibcon#read 5, iclass 35, count 0 2006.286.04:43:06.13#ibcon#about to read 6, iclass 35, count 0 2006.286.04:43:06.13#ibcon#read 6, iclass 35, count 0 2006.286.04:43:06.13#ibcon#end of sib2, iclass 35, count 0 2006.286.04:43:06.13#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:43:06.13#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:43:06.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:43:06.13#ibcon#*before write, iclass 35, count 0 2006.286.04:43:06.13#ibcon#enter sib2, iclass 35, count 0 2006.286.04:43:06.13#ibcon#flushed, iclass 35, count 0 2006.286.04:43:06.13#ibcon#about to write, iclass 35, count 0 2006.286.04:43:06.13#ibcon#wrote, iclass 35, count 0 2006.286.04:43:06.13#ibcon#about to read 3, iclass 35, count 0 2006.286.04:43:06.17#ibcon#read 3, iclass 35, count 0 2006.286.04:43:06.17#ibcon#about to read 4, iclass 35, count 0 2006.286.04:43:06.17#ibcon#read 4, iclass 35, count 0 2006.286.04:43:06.17#ibcon#about to read 5, iclass 35, count 0 2006.286.04:43:06.17#ibcon#read 5, iclass 35, count 0 2006.286.04:43:06.17#ibcon#about to read 6, iclass 35, count 0 2006.286.04:43:06.17#ibcon#read 6, iclass 35, count 0 2006.286.04:43:06.17#ibcon#end of sib2, iclass 35, count 0 2006.286.04:43:06.17#ibcon#*after write, iclass 35, count 0 2006.286.04:43:06.17#ibcon#*before return 0, iclass 35, count 0 2006.286.04:43:06.17#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:43:06.17#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:43:06.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:43:06.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:43:06.17$vck44/vb=7,4 2006.286.04:43:06.17#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.04:43:06.17#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.04:43:06.17#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:06.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:43:06.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:43:06.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:43:06.23#ibcon#enter wrdev, iclass 37, count 2 2006.286.04:43:06.23#ibcon#first serial, iclass 37, count 2 2006.286.04:43:06.23#ibcon#enter sib2, iclass 37, count 2 2006.286.04:43:06.23#ibcon#flushed, iclass 37, count 2 2006.286.04:43:06.23#ibcon#about to write, iclass 37, count 2 2006.286.04:43:06.23#ibcon#wrote, iclass 37, count 2 2006.286.04:43:06.23#ibcon#about to read 3, iclass 37, count 2 2006.286.04:43:06.25#ibcon#read 3, iclass 37, count 2 2006.286.04:43:06.25#ibcon#about to read 4, iclass 37, count 2 2006.286.04:43:06.25#ibcon#read 4, iclass 37, count 2 2006.286.04:43:06.25#ibcon#about to read 5, iclass 37, count 2 2006.286.04:43:06.25#ibcon#read 5, iclass 37, count 2 2006.286.04:43:06.25#ibcon#about to read 6, iclass 37, count 2 2006.286.04:43:06.25#ibcon#read 6, iclass 37, count 2 2006.286.04:43:06.25#ibcon#end of sib2, iclass 37, count 2 2006.286.04:43:06.25#ibcon#*mode == 0, iclass 37, count 2 2006.286.04:43:06.25#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.04:43:06.25#ibcon#[27=AT07-04\r\n] 2006.286.04:43:06.25#ibcon#*before write, iclass 37, count 2 2006.286.04:43:06.25#ibcon#enter sib2, iclass 37, count 2 2006.286.04:43:06.25#ibcon#flushed, iclass 37, count 2 2006.286.04:43:06.25#ibcon#about to write, iclass 37, count 2 2006.286.04:43:06.25#ibcon#wrote, iclass 37, count 2 2006.286.04:43:06.25#ibcon#about to read 3, iclass 37, count 2 2006.286.04:43:06.28#ibcon#read 3, iclass 37, count 2 2006.286.04:43:06.28#ibcon#about to read 4, iclass 37, count 2 2006.286.04:43:06.28#ibcon#read 4, iclass 37, count 2 2006.286.04:43:06.28#ibcon#about to read 5, iclass 37, count 2 2006.286.04:43:06.28#ibcon#read 5, iclass 37, count 2 2006.286.04:43:06.28#ibcon#about to read 6, iclass 37, count 2 2006.286.04:43:06.28#ibcon#read 6, iclass 37, count 2 2006.286.04:43:06.28#ibcon#end of sib2, iclass 37, count 2 2006.286.04:43:06.28#ibcon#*after write, iclass 37, count 2 2006.286.04:43:06.28#ibcon#*before return 0, iclass 37, count 2 2006.286.04:43:06.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:43:06.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:43:06.28#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.04:43:06.28#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:06.28#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:43:06.40#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:43:06.40#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:43:06.40#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:43:06.40#ibcon#first serial, iclass 37, count 0 2006.286.04:43:06.40#ibcon#enter sib2, iclass 37, count 0 2006.286.04:43:06.40#ibcon#flushed, iclass 37, count 0 2006.286.04:43:06.40#ibcon#about to write, iclass 37, count 0 2006.286.04:43:06.40#ibcon#wrote, iclass 37, count 0 2006.286.04:43:06.40#ibcon#about to read 3, iclass 37, count 0 2006.286.04:43:06.42#ibcon#read 3, iclass 37, count 0 2006.286.04:43:06.42#ibcon#about to read 4, iclass 37, count 0 2006.286.04:43:06.42#ibcon#read 4, iclass 37, count 0 2006.286.04:43:06.42#ibcon#about to read 5, iclass 37, count 0 2006.286.04:43:06.42#ibcon#read 5, iclass 37, count 0 2006.286.04:43:06.42#ibcon#about to read 6, iclass 37, count 0 2006.286.04:43:06.42#ibcon#read 6, iclass 37, count 0 2006.286.04:43:06.42#ibcon#end of sib2, iclass 37, count 0 2006.286.04:43:06.42#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:43:06.42#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:43:06.42#ibcon#[27=USB\r\n] 2006.286.04:43:06.42#ibcon#*before write, iclass 37, count 0 2006.286.04:43:06.42#ibcon#enter sib2, iclass 37, count 0 2006.286.04:43:06.42#ibcon#flushed, iclass 37, count 0 2006.286.04:43:06.42#ibcon#about to write, iclass 37, count 0 2006.286.04:43:06.42#ibcon#wrote, iclass 37, count 0 2006.286.04:43:06.42#ibcon#about to read 3, iclass 37, count 0 2006.286.04:43:06.45#ibcon#read 3, iclass 37, count 0 2006.286.04:43:06.45#ibcon#about to read 4, iclass 37, count 0 2006.286.04:43:06.45#ibcon#read 4, iclass 37, count 0 2006.286.04:43:06.45#ibcon#about to read 5, iclass 37, count 0 2006.286.04:43:06.45#ibcon#read 5, iclass 37, count 0 2006.286.04:43:06.45#ibcon#about to read 6, iclass 37, count 0 2006.286.04:43:06.45#ibcon#read 6, iclass 37, count 0 2006.286.04:43:06.45#ibcon#end of sib2, iclass 37, count 0 2006.286.04:43:06.45#ibcon#*after write, iclass 37, count 0 2006.286.04:43:06.45#ibcon#*before return 0, iclass 37, count 0 2006.286.04:43:06.45#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:43:06.45#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:43:06.45#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:43:06.45#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:43:06.45$vck44/vblo=8,744.99 2006.286.04:43:06.45#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.04:43:06.45#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.04:43:06.45#ibcon#ireg 17 cls_cnt 0 2006.286.04:43:06.45#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:43:06.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:43:06.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:43:06.45#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:43:06.45#ibcon#first serial, iclass 39, count 0 2006.286.04:43:06.45#ibcon#enter sib2, iclass 39, count 0 2006.286.04:43:06.45#ibcon#flushed, iclass 39, count 0 2006.286.04:43:06.45#ibcon#about to write, iclass 39, count 0 2006.286.04:43:06.45#ibcon#wrote, iclass 39, count 0 2006.286.04:43:06.45#ibcon#about to read 3, iclass 39, count 0 2006.286.04:43:06.47#ibcon#read 3, iclass 39, count 0 2006.286.04:43:06.47#ibcon#about to read 4, iclass 39, count 0 2006.286.04:43:06.47#ibcon#read 4, iclass 39, count 0 2006.286.04:43:06.65#ibcon#about to read 5, iclass 39, count 0 2006.286.04:43:06.65#ibcon#read 5, iclass 39, count 0 2006.286.04:43:06.65#ibcon#about to read 6, iclass 39, count 0 2006.286.04:43:06.65#ibcon#read 6, iclass 39, count 0 2006.286.04:43:06.65#ibcon#end of sib2, iclass 39, count 0 2006.286.04:43:06.65#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:43:06.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:43:06.65#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:43:06.65#ibcon#*before write, iclass 39, count 0 2006.286.04:43:06.65#ibcon#enter sib2, iclass 39, count 0 2006.286.04:43:06.65#ibcon#flushed, iclass 39, count 0 2006.286.04:43:06.65#ibcon#about to write, iclass 39, count 0 2006.286.04:43:06.65#ibcon#wrote, iclass 39, count 0 2006.286.04:43:06.65#ibcon#about to read 3, iclass 39, count 0 2006.286.04:43:06.69#ibcon#read 3, iclass 39, count 0 2006.286.04:43:06.69#ibcon#about to read 4, iclass 39, count 0 2006.286.04:43:06.69#ibcon#read 4, iclass 39, count 0 2006.286.04:43:06.69#ibcon#about to read 5, iclass 39, count 0 2006.286.04:43:06.69#ibcon#read 5, iclass 39, count 0 2006.286.04:43:06.69#ibcon#about to read 6, iclass 39, count 0 2006.286.04:43:06.69#ibcon#read 6, iclass 39, count 0 2006.286.04:43:06.69#ibcon#end of sib2, iclass 39, count 0 2006.286.04:43:06.69#ibcon#*after write, iclass 39, count 0 2006.286.04:43:06.69#ibcon#*before return 0, iclass 39, count 0 2006.286.04:43:06.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:43:06.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:43:06.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:43:06.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:43:06.69$vck44/vb=8,4 2006.286.04:43:06.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.04:43:06.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.04:43:06.69#ibcon#ireg 11 cls_cnt 2 2006.286.04:43:06.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:43:06.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:43:06.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:43:06.69#ibcon#enter wrdev, iclass 3, count 2 2006.286.04:43:06.69#ibcon#first serial, iclass 3, count 2 2006.286.04:43:06.69#ibcon#enter sib2, iclass 3, count 2 2006.286.04:43:06.69#ibcon#flushed, iclass 3, count 2 2006.286.04:43:06.69#ibcon#about to write, iclass 3, count 2 2006.286.04:43:06.69#ibcon#wrote, iclass 3, count 2 2006.286.04:43:06.69#ibcon#about to read 3, iclass 3, count 2 2006.286.04:43:06.71#ibcon#read 3, iclass 3, count 2 2006.286.04:43:06.71#ibcon#about to read 4, iclass 3, count 2 2006.286.04:43:06.71#ibcon#read 4, iclass 3, count 2 2006.286.04:43:06.71#ibcon#about to read 5, iclass 3, count 2 2006.286.04:43:06.71#ibcon#read 5, iclass 3, count 2 2006.286.04:43:06.71#ibcon#about to read 6, iclass 3, count 2 2006.286.04:43:06.71#ibcon#read 6, iclass 3, count 2 2006.286.04:43:06.71#ibcon#end of sib2, iclass 3, count 2 2006.286.04:43:06.71#ibcon#*mode == 0, iclass 3, count 2 2006.286.04:43:06.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.04:43:06.71#ibcon#[27=AT08-04\r\n] 2006.286.04:43:06.71#ibcon#*before write, iclass 3, count 2 2006.286.04:43:06.71#ibcon#enter sib2, iclass 3, count 2 2006.286.04:43:06.71#ibcon#flushed, iclass 3, count 2 2006.286.04:43:06.71#ibcon#about to write, iclass 3, count 2 2006.286.04:43:06.71#ibcon#wrote, iclass 3, count 2 2006.286.04:43:06.71#ibcon#about to read 3, iclass 3, count 2 2006.286.04:43:06.74#ibcon#read 3, iclass 3, count 2 2006.286.04:43:06.74#ibcon#about to read 4, iclass 3, count 2 2006.286.04:43:06.74#ibcon#read 4, iclass 3, count 2 2006.286.04:43:06.74#ibcon#about to read 5, iclass 3, count 2 2006.286.04:43:06.74#ibcon#read 5, iclass 3, count 2 2006.286.04:43:06.74#ibcon#about to read 6, iclass 3, count 2 2006.286.04:43:06.74#ibcon#read 6, iclass 3, count 2 2006.286.04:43:06.74#ibcon#end of sib2, iclass 3, count 2 2006.286.04:43:06.74#ibcon#*after write, iclass 3, count 2 2006.286.04:43:06.74#ibcon#*before return 0, iclass 3, count 2 2006.286.04:43:06.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:43:06.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:43:06.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.04:43:06.74#ibcon#ireg 7 cls_cnt 0 2006.286.04:43:06.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:43:06.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:43:06.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:43:06.86#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:43:06.86#ibcon#first serial, iclass 3, count 0 2006.286.04:43:06.86#ibcon#enter sib2, iclass 3, count 0 2006.286.04:43:06.86#ibcon#flushed, iclass 3, count 0 2006.286.04:43:06.86#ibcon#about to write, iclass 3, count 0 2006.286.04:43:06.86#ibcon#wrote, iclass 3, count 0 2006.286.04:43:06.86#ibcon#about to read 3, iclass 3, count 0 2006.286.04:43:06.88#ibcon#read 3, iclass 3, count 0 2006.286.04:43:06.88#ibcon#about to read 4, iclass 3, count 0 2006.286.04:43:06.88#ibcon#read 4, iclass 3, count 0 2006.286.04:43:06.88#ibcon#about to read 5, iclass 3, count 0 2006.286.04:43:06.88#ibcon#read 5, iclass 3, count 0 2006.286.04:43:06.88#ibcon#about to read 6, iclass 3, count 0 2006.286.04:43:06.88#ibcon#read 6, iclass 3, count 0 2006.286.04:43:06.88#ibcon#end of sib2, iclass 3, count 0 2006.286.04:43:06.88#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:43:06.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:43:06.88#ibcon#[27=USB\r\n] 2006.286.04:43:06.88#ibcon#*before write, iclass 3, count 0 2006.286.04:43:06.88#ibcon#enter sib2, iclass 3, count 0 2006.286.04:43:06.88#ibcon#flushed, iclass 3, count 0 2006.286.04:43:06.88#ibcon#about to write, iclass 3, count 0 2006.286.04:43:06.88#ibcon#wrote, iclass 3, count 0 2006.286.04:43:06.88#ibcon#about to read 3, iclass 3, count 0 2006.286.04:43:06.91#ibcon#read 3, iclass 3, count 0 2006.286.04:43:06.91#ibcon#about to read 4, iclass 3, count 0 2006.286.04:43:06.91#ibcon#read 4, iclass 3, count 0 2006.286.04:43:06.91#ibcon#about to read 5, iclass 3, count 0 2006.286.04:43:06.91#ibcon#read 5, iclass 3, count 0 2006.286.04:43:06.91#ibcon#about to read 6, iclass 3, count 0 2006.286.04:43:06.91#ibcon#read 6, iclass 3, count 0 2006.286.04:43:06.91#ibcon#end of sib2, iclass 3, count 0 2006.286.04:43:06.91#ibcon#*after write, iclass 3, count 0 2006.286.04:43:06.91#ibcon#*before return 0, iclass 3, count 0 2006.286.04:43:06.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:43:06.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:43:06.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:43:06.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:43:06.91$vck44/vabw=wide 2006.286.04:43:06.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.04:43:06.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.04:43:06.91#ibcon#ireg 8 cls_cnt 0 2006.286.04:43:06.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:43:06.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:43:06.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:43:06.91#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:43:06.91#ibcon#first serial, iclass 5, count 0 2006.286.04:43:06.91#ibcon#enter sib2, iclass 5, count 0 2006.286.04:43:06.91#ibcon#flushed, iclass 5, count 0 2006.286.04:43:06.91#ibcon#about to write, iclass 5, count 0 2006.286.04:43:06.91#ibcon#wrote, iclass 5, count 0 2006.286.04:43:06.91#ibcon#about to read 3, iclass 5, count 0 2006.286.04:43:06.93#ibcon#read 3, iclass 5, count 0 2006.286.04:43:06.93#ibcon#about to read 4, iclass 5, count 0 2006.286.04:43:06.93#ibcon#read 4, iclass 5, count 0 2006.286.04:43:06.93#ibcon#about to read 5, iclass 5, count 0 2006.286.04:43:06.93#ibcon#read 5, iclass 5, count 0 2006.286.04:43:06.93#ibcon#about to read 6, iclass 5, count 0 2006.286.04:43:06.93#ibcon#read 6, iclass 5, count 0 2006.286.04:43:06.93#ibcon#end of sib2, iclass 5, count 0 2006.286.04:43:06.93#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:43:06.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:43:06.93#ibcon#[25=BW32\r\n] 2006.286.04:43:06.93#ibcon#*before write, iclass 5, count 0 2006.286.04:43:06.93#ibcon#enter sib2, iclass 5, count 0 2006.286.04:43:06.93#ibcon#flushed, iclass 5, count 0 2006.286.04:43:06.93#ibcon#about to write, iclass 5, count 0 2006.286.04:43:06.93#ibcon#wrote, iclass 5, count 0 2006.286.04:43:06.93#ibcon#about to read 3, iclass 5, count 0 2006.286.04:43:06.96#ibcon#read 3, iclass 5, count 0 2006.286.04:43:06.96#ibcon#about to read 4, iclass 5, count 0 2006.286.04:43:06.96#ibcon#read 4, iclass 5, count 0 2006.286.04:43:06.96#ibcon#about to read 5, iclass 5, count 0 2006.286.04:43:06.96#ibcon#read 5, iclass 5, count 0 2006.286.04:43:06.96#ibcon#about to read 6, iclass 5, count 0 2006.286.04:43:06.96#ibcon#read 6, iclass 5, count 0 2006.286.04:43:06.96#ibcon#end of sib2, iclass 5, count 0 2006.286.04:43:06.96#ibcon#*after write, iclass 5, count 0 2006.286.04:43:06.96#ibcon#*before return 0, iclass 5, count 0 2006.286.04:43:06.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:43:06.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:43:06.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:43:06.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:43:06.96$vck44/vbbw=wide 2006.286.04:43:06.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.04:43:06.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.04:43:06.96#ibcon#ireg 8 cls_cnt 0 2006.286.04:43:06.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:43:07.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:43:07.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:43:07.03#ibcon#enter wrdev, iclass 7, count 0 2006.286.04:43:07.03#ibcon#first serial, iclass 7, count 0 2006.286.04:43:07.03#ibcon#enter sib2, iclass 7, count 0 2006.286.04:43:07.03#ibcon#flushed, iclass 7, count 0 2006.286.04:43:07.03#ibcon#about to write, iclass 7, count 0 2006.286.04:43:07.03#ibcon#wrote, iclass 7, count 0 2006.286.04:43:07.03#ibcon#about to read 3, iclass 7, count 0 2006.286.04:43:07.05#ibcon#read 3, iclass 7, count 0 2006.286.04:43:07.05#ibcon#about to read 4, iclass 7, count 0 2006.286.04:43:07.05#ibcon#read 4, iclass 7, count 0 2006.286.04:43:07.05#ibcon#about to read 5, iclass 7, count 0 2006.286.04:43:07.05#ibcon#read 5, iclass 7, count 0 2006.286.04:43:07.05#ibcon#about to read 6, iclass 7, count 0 2006.286.04:43:07.05#ibcon#read 6, iclass 7, count 0 2006.286.04:43:07.05#ibcon#end of sib2, iclass 7, count 0 2006.286.04:43:07.05#ibcon#*mode == 0, iclass 7, count 0 2006.286.04:43:07.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.04:43:07.05#ibcon#[27=BW32\r\n] 2006.286.04:43:07.05#ibcon#*before write, iclass 7, count 0 2006.286.04:43:07.05#ibcon#enter sib2, iclass 7, count 0 2006.286.04:43:07.05#ibcon#flushed, iclass 7, count 0 2006.286.04:43:07.05#ibcon#about to write, iclass 7, count 0 2006.286.04:43:07.05#ibcon#wrote, iclass 7, count 0 2006.286.04:43:07.05#ibcon#about to read 3, iclass 7, count 0 2006.286.04:43:07.08#ibcon#read 3, iclass 7, count 0 2006.286.04:43:07.08#ibcon#about to read 4, iclass 7, count 0 2006.286.04:43:07.08#ibcon#read 4, iclass 7, count 0 2006.286.04:43:07.08#ibcon#about to read 5, iclass 7, count 0 2006.286.04:43:07.08#ibcon#read 5, iclass 7, count 0 2006.286.04:43:07.08#ibcon#about to read 6, iclass 7, count 0 2006.286.04:43:07.08#ibcon#read 6, iclass 7, count 0 2006.286.04:43:07.08#ibcon#end of sib2, iclass 7, count 0 2006.286.04:43:07.08#ibcon#*after write, iclass 7, count 0 2006.286.04:43:07.08#ibcon#*before return 0, iclass 7, count 0 2006.286.04:43:07.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:43:07.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:43:07.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.04:43:07.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.04:43:07.08$setupk4/ifdk4 2006.286.04:43:07.08$ifdk4/lo= 2006.286.04:43:07.08$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:43:07.08$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:43:07.08$ifdk4/patch= 2006.286.04:43:07.08$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:43:07.08$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:43:07.08$setupk4/!*+20s 2006.286.04:43:14.88#abcon#<5=/04 3.7 7.1 22.20 761014.8\r\n> 2006.286.04:43:14.90#abcon#{5=INTERFACE CLEAR} 2006.286.04:43:14.96#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:43:19.14#trakl#Source acquired 2006.286.04:43:19.14#flagr#flagr/antenna,acquired 2006.286.04:43:20.81$setupk4/"tpicd 2006.286.04:43:20.81$setupk4/echo=off 2006.286.04:43:20.81$setupk4/xlog=off 2006.286.04:43:20.81:!2006.286.04:44:14 2006.286.04:44:14.00:preob 2006.286.04:44:14.14/onsource/TRACKING 2006.286.04:44:14.14:!2006.286.04:44:24 2006.286.04:44:24.00:"tape 2006.286.04:44:24.00:"st=record 2006.286.04:44:24.00:data_valid=on 2006.286.04:44:24.00:midob 2006.286.04:44:25.14/onsource/TRACKING 2006.286.04:44:25.14/wx/22.22,1014.8,76 2006.286.04:44:25.22/cable/+6.4953E-03 2006.286.04:44:26.31/va/01,07,usb,yes,31,34 2006.286.04:44:26.31/va/02,06,usb,yes,32,32 2006.286.04:44:26.31/va/03,07,usb,yes,31,33 2006.286.04:44:26.31/va/04,06,usb,yes,32,34 2006.286.04:44:26.31/va/05,03,usb,yes,32,32 2006.286.04:44:26.31/va/06,04,usb,yes,29,28 2006.286.04:44:26.31/va/07,04,usb,yes,29,30 2006.286.04:44:26.31/va/08,03,usb,yes,30,37 2006.286.04:44:26.54/valo/01,524.99,yes,locked 2006.286.04:44:26.54/valo/02,534.99,yes,locked 2006.286.04:44:26.54/valo/03,564.99,yes,locked 2006.286.04:44:26.54/valo/04,624.99,yes,locked 2006.286.04:44:26.54/valo/05,734.99,yes,locked 2006.286.04:44:26.54/valo/06,814.99,yes,locked 2006.286.04:44:26.54/valo/07,864.99,yes,locked 2006.286.04:44:26.54/valo/08,884.99,yes,locked 2006.286.04:44:27.63/vb/01,04,usb,yes,30,28 2006.286.04:44:27.63/vb/02,05,usb,yes,28,28 2006.286.04:44:27.63/vb/03,04,usb,yes,29,32 2006.286.04:44:27.63/vb/04,05,usb,yes,29,28 2006.286.04:44:27.63/vb/05,04,usb,yes,26,28 2006.286.04:44:27.63/vb/06,03,usb,yes,37,33 2006.286.04:44:27.63/vb/07,04,usb,yes,29,30 2006.286.04:44:27.63/vb/08,04,usb,yes,27,30 2006.286.04:44:27.86/vblo/01,629.99,yes,locked 2006.286.04:44:27.86/vblo/02,634.99,yes,locked 2006.286.04:44:27.86/vblo/03,649.99,yes,locked 2006.286.04:44:27.86/vblo/04,679.99,yes,locked 2006.286.04:44:27.86/vblo/05,709.99,yes,locked 2006.286.04:44:27.86/vblo/06,719.99,yes,locked 2006.286.04:44:27.86/vblo/07,734.99,yes,locked 2006.286.04:44:27.86/vblo/08,744.99,yes,locked 2006.286.04:44:28.01/vabw/8 2006.286.04:44:28.16/vbbw/8 2006.286.04:44:28.25/xfe/off,on,12.2 2006.286.04:44:28.62/ifatt/23,28,28,28 2006.286.04:44:29.07/fmout-gps/S +2.50E-07 2006.286.04:44:29.09:!2006.286.04:45:14 2006.286.04:45:14.01:data_valid=off 2006.286.04:45:14.01:"et 2006.286.04:45:14.01:!+3s 2006.286.04:45:17.02:"tape 2006.286.04:45:17.02:postob 2006.286.04:45:17.24/cable/+6.4941E-03 2006.286.04:45:17.24/wx/22.25,1014.8,74 2006.286.04:45:17.30/fmout-gps/S +2.49E-07 2006.286.04:45:17.30:scan_name=286-0449,jd0610,40 2006.286.04:45:17.30:source=1958-179,200057.09,-174857.7,2000.0,cw 2006.286.04:45:18.14#flagr#flagr/antenna,new-source 2006.286.04:45:18.14:checkk5 2006.286.04:45:18.51/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:45:19.03/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:45:19.43/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:45:19.84/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:45:20.39/chk_obsdata//k5ts1/T2860444??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.04:45:20.80/chk_obsdata//k5ts2/T2860444??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.04:45:21.24/chk_obsdata//k5ts3/T2860444??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.04:45:21.67/chk_obsdata//k5ts4/T2860444??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.286.04:45:22.51/k5log//k5ts1_log_newline 2006.286.04:45:23.24/k5log//k5ts2_log_newline 2006.286.04:45:23.97/k5log//k5ts3_log_newline 2006.286.04:45:24.86/k5log//k5ts4_log_newline 2006.286.04:45:24.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:45:24.88:setupk4=1 2006.286.04:45:24.88$setupk4/echo=on 2006.286.04:45:24.88$setupk4/pcalon 2006.286.04:45:24.88$pcalon/"no phase cal control is implemented here 2006.286.04:45:24.88$setupk4/"tpicd=stop 2006.286.04:45:24.88$setupk4/"rec=synch_on 2006.286.04:45:24.88$setupk4/"rec_mode=128 2006.286.04:45:24.88$setupk4/!* 2006.286.04:45:24.88$setupk4/recpk4 2006.286.04:45:24.88$recpk4/recpatch= 2006.286.04:45:24.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:45:24.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:45:24.89$setupk4/vck44 2006.286.04:45:24.89$vck44/valo=1,524.99 2006.286.04:45:24.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:45:24.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:45:24.89#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:24.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:45:24.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:45:24.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:45:24.89#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:45:24.89#ibcon#first serial, iclass 30, count 0 2006.286.04:45:24.89#ibcon#enter sib2, iclass 30, count 0 2006.286.04:45:24.89#ibcon#flushed, iclass 30, count 0 2006.286.04:45:24.89#ibcon#about to write, iclass 30, count 0 2006.286.04:45:24.89#ibcon#wrote, iclass 30, count 0 2006.286.04:45:24.89#ibcon#about to read 3, iclass 30, count 0 2006.286.04:45:24.90#ibcon#read 3, iclass 30, count 0 2006.286.04:45:24.90#ibcon#about to read 4, iclass 30, count 0 2006.286.04:45:24.90#ibcon#read 4, iclass 30, count 0 2006.286.04:45:24.90#ibcon#about to read 5, iclass 30, count 0 2006.286.04:45:24.90#ibcon#read 5, iclass 30, count 0 2006.286.04:45:24.90#ibcon#about to read 6, iclass 30, count 0 2006.286.04:45:24.90#ibcon#read 6, iclass 30, count 0 2006.286.04:45:24.90#ibcon#end of sib2, iclass 30, count 0 2006.286.04:45:24.90#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:45:24.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:45:24.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:45:24.90#ibcon#*before write, iclass 30, count 0 2006.286.04:45:24.90#ibcon#enter sib2, iclass 30, count 0 2006.286.04:45:24.90#ibcon#flushed, iclass 30, count 0 2006.286.04:45:24.90#ibcon#about to write, iclass 30, count 0 2006.286.04:45:24.90#ibcon#wrote, iclass 30, count 0 2006.286.04:45:24.90#ibcon#about to read 3, iclass 30, count 0 2006.286.04:45:24.95#ibcon#read 3, iclass 30, count 0 2006.286.04:45:24.95#ibcon#about to read 4, iclass 30, count 0 2006.286.04:45:24.95#ibcon#read 4, iclass 30, count 0 2006.286.04:45:24.95#ibcon#about to read 5, iclass 30, count 0 2006.286.04:45:24.95#ibcon#read 5, iclass 30, count 0 2006.286.04:45:24.95#ibcon#about to read 6, iclass 30, count 0 2006.286.04:45:24.95#ibcon#read 6, iclass 30, count 0 2006.286.04:45:24.95#ibcon#end of sib2, iclass 30, count 0 2006.286.04:45:24.95#ibcon#*after write, iclass 30, count 0 2006.286.04:45:24.95#ibcon#*before return 0, iclass 30, count 0 2006.286.04:45:24.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:45:24.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:45:24.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:45:24.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:45:24.95$vck44/va=1,7 2006.286.04:45:24.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.04:45:24.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.04:45:24.95#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:24.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:45:24.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:45:24.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:45:24.95#ibcon#enter wrdev, iclass 32, count 2 2006.286.04:45:24.95#ibcon#first serial, iclass 32, count 2 2006.286.04:45:24.95#ibcon#enter sib2, iclass 32, count 2 2006.286.04:45:24.95#ibcon#flushed, iclass 32, count 2 2006.286.04:45:24.95#ibcon#about to write, iclass 32, count 2 2006.286.04:45:24.95#ibcon#wrote, iclass 32, count 2 2006.286.04:45:24.95#ibcon#about to read 3, iclass 32, count 2 2006.286.04:45:24.97#ibcon#read 3, iclass 32, count 2 2006.286.04:45:24.97#ibcon#about to read 4, iclass 32, count 2 2006.286.04:45:24.97#ibcon#read 4, iclass 32, count 2 2006.286.04:45:24.97#ibcon#about to read 5, iclass 32, count 2 2006.286.04:45:24.97#ibcon#read 5, iclass 32, count 2 2006.286.04:45:24.97#ibcon#about to read 6, iclass 32, count 2 2006.286.04:45:24.97#ibcon#read 6, iclass 32, count 2 2006.286.04:45:24.97#ibcon#end of sib2, iclass 32, count 2 2006.286.04:45:24.97#ibcon#*mode == 0, iclass 32, count 2 2006.286.04:45:24.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.04:45:24.97#ibcon#[25=AT01-07\r\n] 2006.286.04:45:24.97#ibcon#*before write, iclass 32, count 2 2006.286.04:45:24.97#ibcon#enter sib2, iclass 32, count 2 2006.286.04:45:24.97#ibcon#flushed, iclass 32, count 2 2006.286.04:45:24.97#ibcon#about to write, iclass 32, count 2 2006.286.04:45:24.97#ibcon#wrote, iclass 32, count 2 2006.286.04:45:24.97#ibcon#about to read 3, iclass 32, count 2 2006.286.04:45:25.00#ibcon#read 3, iclass 32, count 2 2006.286.04:45:25.00#ibcon#about to read 4, iclass 32, count 2 2006.286.04:45:25.00#ibcon#read 4, iclass 32, count 2 2006.286.04:45:25.00#ibcon#about to read 5, iclass 32, count 2 2006.286.04:45:25.00#ibcon#read 5, iclass 32, count 2 2006.286.04:45:25.00#ibcon#about to read 6, iclass 32, count 2 2006.286.04:45:25.00#ibcon#read 6, iclass 32, count 2 2006.286.04:45:25.00#ibcon#end of sib2, iclass 32, count 2 2006.286.04:45:25.00#ibcon#*after write, iclass 32, count 2 2006.286.04:45:25.00#ibcon#*before return 0, iclass 32, count 2 2006.286.04:45:25.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:45:25.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:45:25.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.04:45:25.00#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:25.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:45:25.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:45:25.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:45:25.12#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:45:25.12#ibcon#first serial, iclass 32, count 0 2006.286.04:45:25.12#ibcon#enter sib2, iclass 32, count 0 2006.286.04:45:25.12#ibcon#flushed, iclass 32, count 0 2006.286.04:45:25.12#ibcon#about to write, iclass 32, count 0 2006.286.04:45:25.12#ibcon#wrote, iclass 32, count 0 2006.286.04:45:25.12#ibcon#about to read 3, iclass 32, count 0 2006.286.04:45:25.14#ibcon#read 3, iclass 32, count 0 2006.286.04:45:25.14#ibcon#about to read 4, iclass 32, count 0 2006.286.04:45:25.14#ibcon#read 4, iclass 32, count 0 2006.286.04:45:25.14#ibcon#about to read 5, iclass 32, count 0 2006.286.04:45:25.14#ibcon#read 5, iclass 32, count 0 2006.286.04:45:25.14#ibcon#about to read 6, iclass 32, count 0 2006.286.04:45:25.14#ibcon#read 6, iclass 32, count 0 2006.286.04:45:25.14#ibcon#end of sib2, iclass 32, count 0 2006.286.04:45:25.14#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:45:25.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:45:25.14#ibcon#[25=USB\r\n] 2006.286.04:45:25.14#ibcon#*before write, iclass 32, count 0 2006.286.04:45:25.14#ibcon#enter sib2, iclass 32, count 0 2006.286.04:45:25.14#ibcon#flushed, iclass 32, count 0 2006.286.04:45:25.14#ibcon#about to write, iclass 32, count 0 2006.286.04:45:25.14#ibcon#wrote, iclass 32, count 0 2006.286.04:45:25.14#ibcon#about to read 3, iclass 32, count 0 2006.286.04:45:25.17#ibcon#read 3, iclass 32, count 0 2006.286.04:45:25.17#ibcon#about to read 4, iclass 32, count 0 2006.286.04:45:25.17#ibcon#read 4, iclass 32, count 0 2006.286.04:45:25.17#ibcon#about to read 5, iclass 32, count 0 2006.286.04:45:25.17#ibcon#read 5, iclass 32, count 0 2006.286.04:45:25.17#ibcon#about to read 6, iclass 32, count 0 2006.286.04:45:25.17#ibcon#read 6, iclass 32, count 0 2006.286.04:45:25.17#ibcon#end of sib2, iclass 32, count 0 2006.286.04:45:25.17#ibcon#*after write, iclass 32, count 0 2006.286.04:45:25.17#ibcon#*before return 0, iclass 32, count 0 2006.286.04:45:25.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:45:25.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:45:25.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:45:25.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:45:25.17$vck44/valo=2,534.99 2006.286.04:45:25.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.04:45:25.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.04:45:25.17#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:25.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:45:25.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:45:25.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:45:25.17#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:45:25.17#ibcon#first serial, iclass 34, count 0 2006.286.04:45:25.17#ibcon#enter sib2, iclass 34, count 0 2006.286.04:45:25.17#ibcon#flushed, iclass 34, count 0 2006.286.04:45:25.17#ibcon#about to write, iclass 34, count 0 2006.286.04:45:25.17#ibcon#wrote, iclass 34, count 0 2006.286.04:45:25.17#ibcon#about to read 3, iclass 34, count 0 2006.286.04:45:25.19#ibcon#read 3, iclass 34, count 0 2006.286.04:45:25.19#ibcon#about to read 4, iclass 34, count 0 2006.286.04:45:25.19#ibcon#read 4, iclass 34, count 0 2006.286.04:45:25.19#ibcon#about to read 5, iclass 34, count 0 2006.286.04:45:25.19#ibcon#read 5, iclass 34, count 0 2006.286.04:45:25.19#ibcon#about to read 6, iclass 34, count 0 2006.286.04:45:25.19#ibcon#read 6, iclass 34, count 0 2006.286.04:45:25.19#ibcon#end of sib2, iclass 34, count 0 2006.286.04:45:25.19#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:45:25.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:45:25.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:45:25.19#ibcon#*before write, iclass 34, count 0 2006.286.04:45:25.19#ibcon#enter sib2, iclass 34, count 0 2006.286.04:45:25.19#ibcon#flushed, iclass 34, count 0 2006.286.04:45:25.19#ibcon#about to write, iclass 34, count 0 2006.286.04:45:25.19#ibcon#wrote, iclass 34, count 0 2006.286.04:45:25.19#ibcon#about to read 3, iclass 34, count 0 2006.286.04:45:25.23#ibcon#read 3, iclass 34, count 0 2006.286.04:45:25.23#ibcon#about to read 4, iclass 34, count 0 2006.286.04:45:25.23#ibcon#read 4, iclass 34, count 0 2006.286.04:45:25.23#ibcon#about to read 5, iclass 34, count 0 2006.286.04:45:25.23#ibcon#read 5, iclass 34, count 0 2006.286.04:45:25.23#ibcon#about to read 6, iclass 34, count 0 2006.286.04:45:25.23#ibcon#read 6, iclass 34, count 0 2006.286.04:45:25.23#ibcon#end of sib2, iclass 34, count 0 2006.286.04:45:25.23#ibcon#*after write, iclass 34, count 0 2006.286.04:45:25.23#ibcon#*before return 0, iclass 34, count 0 2006.286.04:45:25.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:45:25.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:45:25.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:45:25.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:45:25.23$vck44/va=2,6 2006.286.04:45:25.23#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.04:45:25.23#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.04:45:25.23#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:25.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:45:25.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:45:25.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:45:25.29#ibcon#enter wrdev, iclass 36, count 2 2006.286.04:45:25.29#ibcon#first serial, iclass 36, count 2 2006.286.04:45:25.29#ibcon#enter sib2, iclass 36, count 2 2006.286.04:45:25.29#ibcon#flushed, iclass 36, count 2 2006.286.04:45:25.29#ibcon#about to write, iclass 36, count 2 2006.286.04:45:25.29#ibcon#wrote, iclass 36, count 2 2006.286.04:45:25.29#ibcon#about to read 3, iclass 36, count 2 2006.286.04:45:25.31#ibcon#read 3, iclass 36, count 2 2006.286.04:45:25.31#ibcon#about to read 4, iclass 36, count 2 2006.286.04:45:25.31#ibcon#read 4, iclass 36, count 2 2006.286.04:45:25.31#ibcon#about to read 5, iclass 36, count 2 2006.286.04:45:25.31#ibcon#read 5, iclass 36, count 2 2006.286.04:45:25.31#ibcon#about to read 6, iclass 36, count 2 2006.286.04:45:25.31#ibcon#read 6, iclass 36, count 2 2006.286.04:45:25.31#ibcon#end of sib2, iclass 36, count 2 2006.286.04:45:25.31#ibcon#*mode == 0, iclass 36, count 2 2006.286.04:45:25.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.04:45:25.31#ibcon#[25=AT02-06\r\n] 2006.286.04:45:25.31#ibcon#*before write, iclass 36, count 2 2006.286.04:45:25.31#ibcon#enter sib2, iclass 36, count 2 2006.286.04:45:25.31#ibcon#flushed, iclass 36, count 2 2006.286.04:45:25.31#ibcon#about to write, iclass 36, count 2 2006.286.04:45:25.31#ibcon#wrote, iclass 36, count 2 2006.286.04:45:25.31#ibcon#about to read 3, iclass 36, count 2 2006.286.04:45:25.34#ibcon#read 3, iclass 36, count 2 2006.286.04:45:25.34#ibcon#about to read 4, iclass 36, count 2 2006.286.04:45:25.34#ibcon#read 4, iclass 36, count 2 2006.286.04:45:25.34#ibcon#about to read 5, iclass 36, count 2 2006.286.04:45:25.34#ibcon#read 5, iclass 36, count 2 2006.286.04:45:25.34#ibcon#about to read 6, iclass 36, count 2 2006.286.04:45:25.34#ibcon#read 6, iclass 36, count 2 2006.286.04:45:25.34#ibcon#end of sib2, iclass 36, count 2 2006.286.04:45:25.34#ibcon#*after write, iclass 36, count 2 2006.286.04:45:25.34#ibcon#*before return 0, iclass 36, count 2 2006.286.04:45:25.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:45:25.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:45:25.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.04:45:25.34#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:25.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:45:25.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:45:25.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:45:25.46#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:45:25.46#ibcon#first serial, iclass 36, count 0 2006.286.04:45:25.46#ibcon#enter sib2, iclass 36, count 0 2006.286.04:45:25.46#ibcon#flushed, iclass 36, count 0 2006.286.04:45:25.46#ibcon#about to write, iclass 36, count 0 2006.286.04:45:25.46#ibcon#wrote, iclass 36, count 0 2006.286.04:45:25.46#ibcon#about to read 3, iclass 36, count 0 2006.286.04:45:25.48#ibcon#read 3, iclass 36, count 0 2006.286.04:45:25.48#ibcon#about to read 4, iclass 36, count 0 2006.286.04:45:25.48#ibcon#read 4, iclass 36, count 0 2006.286.04:45:25.48#ibcon#about to read 5, iclass 36, count 0 2006.286.04:45:25.48#ibcon#read 5, iclass 36, count 0 2006.286.04:45:25.48#ibcon#about to read 6, iclass 36, count 0 2006.286.04:45:25.48#ibcon#read 6, iclass 36, count 0 2006.286.04:45:25.48#ibcon#end of sib2, iclass 36, count 0 2006.286.04:45:25.48#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:45:25.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:45:25.48#ibcon#[25=USB\r\n] 2006.286.04:45:25.48#ibcon#*before write, iclass 36, count 0 2006.286.04:45:25.48#ibcon#enter sib2, iclass 36, count 0 2006.286.04:45:25.48#ibcon#flushed, iclass 36, count 0 2006.286.04:45:25.48#ibcon#about to write, iclass 36, count 0 2006.286.04:45:25.48#ibcon#wrote, iclass 36, count 0 2006.286.04:45:25.48#ibcon#about to read 3, iclass 36, count 0 2006.286.04:45:25.51#ibcon#read 3, iclass 36, count 0 2006.286.04:45:25.51#ibcon#about to read 4, iclass 36, count 0 2006.286.04:45:25.51#ibcon#read 4, iclass 36, count 0 2006.286.04:45:25.51#ibcon#about to read 5, iclass 36, count 0 2006.286.04:45:25.51#ibcon#read 5, iclass 36, count 0 2006.286.04:45:25.51#ibcon#about to read 6, iclass 36, count 0 2006.286.04:45:25.51#ibcon#read 6, iclass 36, count 0 2006.286.04:45:25.51#ibcon#end of sib2, iclass 36, count 0 2006.286.04:45:25.51#ibcon#*after write, iclass 36, count 0 2006.286.04:45:25.51#ibcon#*before return 0, iclass 36, count 0 2006.286.04:45:25.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:45:25.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:45:25.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:45:25.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:45:25.51$vck44/valo=3,564.99 2006.286.04:45:25.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.04:45:25.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.04:45:25.51#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:25.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:45:25.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:45:25.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:45:25.51#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:45:25.51#ibcon#first serial, iclass 38, count 0 2006.286.04:45:25.51#ibcon#enter sib2, iclass 38, count 0 2006.286.04:45:25.51#ibcon#flushed, iclass 38, count 0 2006.286.04:45:25.51#ibcon#about to write, iclass 38, count 0 2006.286.04:45:25.51#ibcon#wrote, iclass 38, count 0 2006.286.04:45:25.51#ibcon#about to read 3, iclass 38, count 0 2006.286.04:45:25.53#ibcon#read 3, iclass 38, count 0 2006.286.04:45:25.53#ibcon#about to read 4, iclass 38, count 0 2006.286.04:45:25.53#ibcon#read 4, iclass 38, count 0 2006.286.04:45:25.53#ibcon#about to read 5, iclass 38, count 0 2006.286.04:45:25.53#ibcon#read 5, iclass 38, count 0 2006.286.04:45:25.53#ibcon#about to read 6, iclass 38, count 0 2006.286.04:45:25.53#ibcon#read 6, iclass 38, count 0 2006.286.04:45:25.53#ibcon#end of sib2, iclass 38, count 0 2006.286.04:45:25.53#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:45:25.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:45:25.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:45:25.53#ibcon#*before write, iclass 38, count 0 2006.286.04:45:25.53#ibcon#enter sib2, iclass 38, count 0 2006.286.04:45:25.53#ibcon#flushed, iclass 38, count 0 2006.286.04:45:25.53#ibcon#about to write, iclass 38, count 0 2006.286.04:45:25.53#ibcon#wrote, iclass 38, count 0 2006.286.04:45:25.53#ibcon#about to read 3, iclass 38, count 0 2006.286.04:45:25.57#ibcon#read 3, iclass 38, count 0 2006.286.04:45:25.57#ibcon#about to read 4, iclass 38, count 0 2006.286.04:45:25.57#ibcon#read 4, iclass 38, count 0 2006.286.04:45:25.57#ibcon#about to read 5, iclass 38, count 0 2006.286.04:45:25.57#ibcon#read 5, iclass 38, count 0 2006.286.04:45:25.57#ibcon#about to read 6, iclass 38, count 0 2006.286.04:45:25.57#ibcon#read 6, iclass 38, count 0 2006.286.04:45:25.57#ibcon#end of sib2, iclass 38, count 0 2006.286.04:45:25.57#ibcon#*after write, iclass 38, count 0 2006.286.04:45:25.57#ibcon#*before return 0, iclass 38, count 0 2006.286.04:45:25.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:45:25.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:45:25.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:45:25.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:45:25.57$vck44/va=3,7 2006.286.04:45:25.57#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.04:45:25.57#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.04:45:25.57#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:25.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:45:25.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:45:25.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:45:25.63#ibcon#enter wrdev, iclass 40, count 2 2006.286.04:45:25.63#ibcon#first serial, iclass 40, count 2 2006.286.04:45:25.63#ibcon#enter sib2, iclass 40, count 2 2006.286.04:45:25.63#ibcon#flushed, iclass 40, count 2 2006.286.04:45:25.63#ibcon#about to write, iclass 40, count 2 2006.286.04:45:25.63#ibcon#wrote, iclass 40, count 2 2006.286.04:45:25.63#ibcon#about to read 3, iclass 40, count 2 2006.286.04:45:25.65#ibcon#read 3, iclass 40, count 2 2006.286.04:45:25.65#ibcon#about to read 4, iclass 40, count 2 2006.286.04:45:25.65#ibcon#read 4, iclass 40, count 2 2006.286.04:45:25.65#ibcon#about to read 5, iclass 40, count 2 2006.286.04:45:25.65#ibcon#read 5, iclass 40, count 2 2006.286.04:45:25.65#ibcon#about to read 6, iclass 40, count 2 2006.286.04:45:25.65#ibcon#read 6, iclass 40, count 2 2006.286.04:45:25.65#ibcon#end of sib2, iclass 40, count 2 2006.286.04:45:25.65#ibcon#*mode == 0, iclass 40, count 2 2006.286.04:45:25.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.04:45:25.65#ibcon#[25=AT03-07\r\n] 2006.286.04:45:25.65#ibcon#*before write, iclass 40, count 2 2006.286.04:45:25.65#ibcon#enter sib2, iclass 40, count 2 2006.286.04:45:25.65#ibcon#flushed, iclass 40, count 2 2006.286.04:45:25.65#ibcon#about to write, iclass 40, count 2 2006.286.04:45:25.65#ibcon#wrote, iclass 40, count 2 2006.286.04:45:25.65#ibcon#about to read 3, iclass 40, count 2 2006.286.04:45:25.68#ibcon#read 3, iclass 40, count 2 2006.286.04:45:25.68#ibcon#about to read 4, iclass 40, count 2 2006.286.04:45:25.68#ibcon#read 4, iclass 40, count 2 2006.286.04:45:25.68#ibcon#about to read 5, iclass 40, count 2 2006.286.04:45:25.68#ibcon#read 5, iclass 40, count 2 2006.286.04:45:25.68#ibcon#about to read 6, iclass 40, count 2 2006.286.04:45:25.68#ibcon#read 6, iclass 40, count 2 2006.286.04:45:25.68#ibcon#end of sib2, iclass 40, count 2 2006.286.04:45:25.68#ibcon#*after write, iclass 40, count 2 2006.286.04:45:25.68#ibcon#*before return 0, iclass 40, count 2 2006.286.04:45:25.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:45:25.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:45:25.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.04:45:25.68#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:25.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:45:25.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:45:25.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:45:25.80#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:45:25.80#ibcon#first serial, iclass 40, count 0 2006.286.04:45:25.80#ibcon#enter sib2, iclass 40, count 0 2006.286.04:45:25.80#ibcon#flushed, iclass 40, count 0 2006.286.04:45:25.80#ibcon#about to write, iclass 40, count 0 2006.286.04:45:25.80#ibcon#wrote, iclass 40, count 0 2006.286.04:45:25.80#ibcon#about to read 3, iclass 40, count 0 2006.286.04:45:25.82#ibcon#read 3, iclass 40, count 0 2006.286.04:45:25.82#ibcon#about to read 4, iclass 40, count 0 2006.286.04:45:25.82#ibcon#read 4, iclass 40, count 0 2006.286.04:45:25.82#ibcon#about to read 5, iclass 40, count 0 2006.286.04:45:25.82#ibcon#read 5, iclass 40, count 0 2006.286.04:45:25.82#ibcon#about to read 6, iclass 40, count 0 2006.286.04:45:25.82#ibcon#read 6, iclass 40, count 0 2006.286.04:45:25.82#ibcon#end of sib2, iclass 40, count 0 2006.286.04:45:25.82#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:45:25.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:45:25.82#ibcon#[25=USB\r\n] 2006.286.04:45:25.82#ibcon#*before write, iclass 40, count 0 2006.286.04:45:25.82#ibcon#enter sib2, iclass 40, count 0 2006.286.04:45:25.82#ibcon#flushed, iclass 40, count 0 2006.286.04:45:25.82#ibcon#about to write, iclass 40, count 0 2006.286.04:45:25.82#ibcon#wrote, iclass 40, count 0 2006.286.04:45:25.82#ibcon#about to read 3, iclass 40, count 0 2006.286.04:45:25.85#ibcon#read 3, iclass 40, count 0 2006.286.04:45:25.85#ibcon#about to read 4, iclass 40, count 0 2006.286.04:45:25.85#ibcon#read 4, iclass 40, count 0 2006.286.04:45:25.85#ibcon#about to read 5, iclass 40, count 0 2006.286.04:45:25.85#ibcon#read 5, iclass 40, count 0 2006.286.04:45:25.85#ibcon#about to read 6, iclass 40, count 0 2006.286.04:45:25.85#ibcon#read 6, iclass 40, count 0 2006.286.04:45:25.85#ibcon#end of sib2, iclass 40, count 0 2006.286.04:45:25.85#ibcon#*after write, iclass 40, count 0 2006.286.04:45:25.85#ibcon#*before return 0, iclass 40, count 0 2006.286.04:45:25.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:45:25.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:45:25.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:45:25.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:45:25.85$vck44/valo=4,624.99 2006.286.04:45:25.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.04:45:25.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.04:45:25.85#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:25.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:45:25.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:45:25.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:45:25.85#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:45:25.85#ibcon#first serial, iclass 4, count 0 2006.286.04:45:25.85#ibcon#enter sib2, iclass 4, count 0 2006.286.04:45:25.85#ibcon#flushed, iclass 4, count 0 2006.286.04:45:25.85#ibcon#about to write, iclass 4, count 0 2006.286.04:45:25.85#ibcon#wrote, iclass 4, count 0 2006.286.04:45:25.85#ibcon#about to read 3, iclass 4, count 0 2006.286.04:45:26.33#ibcon#read 3, iclass 4, count 0 2006.286.04:45:26.33#ibcon#about to read 4, iclass 4, count 0 2006.286.04:45:26.33#ibcon#read 4, iclass 4, count 0 2006.286.04:45:26.33#ibcon#about to read 5, iclass 4, count 0 2006.286.04:45:26.33#ibcon#read 5, iclass 4, count 0 2006.286.04:45:26.33#ibcon#about to read 6, iclass 4, count 0 2006.286.04:45:26.33#ibcon#read 6, iclass 4, count 0 2006.286.04:45:26.33#ibcon#end of sib2, iclass 4, count 0 2006.286.04:45:26.33#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:45:26.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:45:26.33#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:45:26.33#ibcon#*before write, iclass 4, count 0 2006.286.04:45:26.33#ibcon#enter sib2, iclass 4, count 0 2006.286.04:45:26.33#ibcon#flushed, iclass 4, count 0 2006.286.04:45:26.33#ibcon#about to write, iclass 4, count 0 2006.286.04:45:26.33#ibcon#wrote, iclass 4, count 0 2006.286.04:45:26.33#ibcon#about to read 3, iclass 4, count 0 2006.286.04:45:26.37#ibcon#read 3, iclass 4, count 0 2006.286.04:45:26.37#ibcon#about to read 4, iclass 4, count 0 2006.286.04:45:26.37#ibcon#read 4, iclass 4, count 0 2006.286.04:45:26.37#ibcon#about to read 5, iclass 4, count 0 2006.286.04:45:26.37#ibcon#read 5, iclass 4, count 0 2006.286.04:45:26.37#ibcon#about to read 6, iclass 4, count 0 2006.286.04:45:26.37#ibcon#read 6, iclass 4, count 0 2006.286.04:45:26.37#ibcon#end of sib2, iclass 4, count 0 2006.286.04:45:26.37#ibcon#*after write, iclass 4, count 0 2006.286.04:45:26.37#ibcon#*before return 0, iclass 4, count 0 2006.286.04:45:26.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:45:26.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:45:26.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:45:26.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:45:26.37$vck44/va=4,6 2006.286.04:45:26.37#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.04:45:26.37#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.04:45:26.37#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:26.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:45:26.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:45:26.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:45:26.37#ibcon#enter wrdev, iclass 6, count 2 2006.286.04:45:26.37#ibcon#first serial, iclass 6, count 2 2006.286.04:45:26.37#ibcon#enter sib2, iclass 6, count 2 2006.286.04:45:26.37#ibcon#flushed, iclass 6, count 2 2006.286.04:45:26.37#ibcon#about to write, iclass 6, count 2 2006.286.04:45:26.37#ibcon#wrote, iclass 6, count 2 2006.286.04:45:26.37#ibcon#about to read 3, iclass 6, count 2 2006.286.04:45:26.39#ibcon#read 3, iclass 6, count 2 2006.286.04:45:26.39#ibcon#about to read 4, iclass 6, count 2 2006.286.04:45:26.39#ibcon#read 4, iclass 6, count 2 2006.286.04:45:26.39#ibcon#about to read 5, iclass 6, count 2 2006.286.04:45:26.39#ibcon#read 5, iclass 6, count 2 2006.286.04:45:26.39#ibcon#about to read 6, iclass 6, count 2 2006.286.04:45:26.39#ibcon#read 6, iclass 6, count 2 2006.286.04:45:26.39#ibcon#end of sib2, iclass 6, count 2 2006.286.04:45:26.39#ibcon#*mode == 0, iclass 6, count 2 2006.286.04:45:26.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.04:45:26.39#ibcon#[25=AT04-06\r\n] 2006.286.04:45:26.39#ibcon#*before write, iclass 6, count 2 2006.286.04:45:26.39#ibcon#enter sib2, iclass 6, count 2 2006.286.04:45:26.39#ibcon#flushed, iclass 6, count 2 2006.286.04:45:26.39#ibcon#about to write, iclass 6, count 2 2006.286.04:45:26.39#ibcon#wrote, iclass 6, count 2 2006.286.04:45:26.39#ibcon#about to read 3, iclass 6, count 2 2006.286.04:45:26.42#ibcon#read 3, iclass 6, count 2 2006.286.04:45:26.42#ibcon#about to read 4, iclass 6, count 2 2006.286.04:45:26.42#ibcon#read 4, iclass 6, count 2 2006.286.04:45:26.42#ibcon#about to read 5, iclass 6, count 2 2006.286.04:45:26.42#ibcon#read 5, iclass 6, count 2 2006.286.04:45:26.42#ibcon#about to read 6, iclass 6, count 2 2006.286.04:45:26.42#ibcon#read 6, iclass 6, count 2 2006.286.04:45:26.42#ibcon#end of sib2, iclass 6, count 2 2006.286.04:45:26.42#ibcon#*after write, iclass 6, count 2 2006.286.04:45:26.42#ibcon#*before return 0, iclass 6, count 2 2006.286.04:45:26.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:45:26.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:45:26.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.04:45:26.42#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:26.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:45:26.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:45:26.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:45:26.54#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:45:26.54#ibcon#first serial, iclass 6, count 0 2006.286.04:45:26.54#ibcon#enter sib2, iclass 6, count 0 2006.286.04:45:26.54#ibcon#flushed, iclass 6, count 0 2006.286.04:45:26.54#ibcon#about to write, iclass 6, count 0 2006.286.04:45:26.54#ibcon#wrote, iclass 6, count 0 2006.286.04:45:26.54#ibcon#about to read 3, iclass 6, count 0 2006.286.04:45:26.56#ibcon#read 3, iclass 6, count 0 2006.286.04:45:26.56#ibcon#about to read 4, iclass 6, count 0 2006.286.04:45:26.56#ibcon#read 4, iclass 6, count 0 2006.286.04:45:26.56#ibcon#about to read 5, iclass 6, count 0 2006.286.04:45:26.56#ibcon#read 5, iclass 6, count 0 2006.286.04:45:26.56#ibcon#about to read 6, iclass 6, count 0 2006.286.04:45:26.56#ibcon#read 6, iclass 6, count 0 2006.286.04:45:26.56#ibcon#end of sib2, iclass 6, count 0 2006.286.04:45:26.56#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:45:26.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:45:26.56#ibcon#[25=USB\r\n] 2006.286.04:45:26.56#ibcon#*before write, iclass 6, count 0 2006.286.04:45:26.56#ibcon#enter sib2, iclass 6, count 0 2006.286.04:45:26.56#ibcon#flushed, iclass 6, count 0 2006.286.04:45:26.56#ibcon#about to write, iclass 6, count 0 2006.286.04:45:26.56#ibcon#wrote, iclass 6, count 0 2006.286.04:45:26.56#ibcon#about to read 3, iclass 6, count 0 2006.286.04:45:26.59#ibcon#read 3, iclass 6, count 0 2006.286.04:45:26.59#ibcon#about to read 4, iclass 6, count 0 2006.286.04:45:26.59#ibcon#read 4, iclass 6, count 0 2006.286.04:45:26.59#ibcon#about to read 5, iclass 6, count 0 2006.286.04:45:26.59#ibcon#read 5, iclass 6, count 0 2006.286.04:45:26.59#ibcon#about to read 6, iclass 6, count 0 2006.286.04:45:26.59#ibcon#read 6, iclass 6, count 0 2006.286.04:45:26.59#ibcon#end of sib2, iclass 6, count 0 2006.286.04:45:26.59#ibcon#*after write, iclass 6, count 0 2006.286.04:45:26.59#ibcon#*before return 0, iclass 6, count 0 2006.286.04:45:26.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:45:26.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:45:26.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:45:26.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:45:26.59$vck44/valo=5,734.99 2006.286.04:45:26.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.04:45:26.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.04:45:26.59#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:26.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:45:26.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:45:26.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:45:26.59#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:45:26.59#ibcon#first serial, iclass 10, count 0 2006.286.04:45:26.59#ibcon#enter sib2, iclass 10, count 0 2006.286.04:45:26.59#ibcon#flushed, iclass 10, count 0 2006.286.04:45:26.59#ibcon#about to write, iclass 10, count 0 2006.286.04:45:26.59#ibcon#wrote, iclass 10, count 0 2006.286.04:45:26.59#ibcon#about to read 3, iclass 10, count 0 2006.286.04:45:26.84#ibcon#read 3, iclass 10, count 0 2006.286.04:45:26.84#ibcon#about to read 4, iclass 10, count 0 2006.286.04:45:26.84#ibcon#read 4, iclass 10, count 0 2006.286.04:45:26.84#ibcon#about to read 5, iclass 10, count 0 2006.286.04:45:26.84#ibcon#read 5, iclass 10, count 0 2006.286.04:45:26.84#ibcon#about to read 6, iclass 10, count 0 2006.286.04:45:26.84#ibcon#read 6, iclass 10, count 0 2006.286.04:45:26.84#ibcon#end of sib2, iclass 10, count 0 2006.286.04:45:26.84#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:45:26.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:45:26.84#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:45:26.84#ibcon#*before write, iclass 10, count 0 2006.286.04:45:26.84#ibcon#enter sib2, iclass 10, count 0 2006.286.04:45:26.84#ibcon#flushed, iclass 10, count 0 2006.286.04:45:26.84#ibcon#about to write, iclass 10, count 0 2006.286.04:45:26.84#ibcon#wrote, iclass 10, count 0 2006.286.04:45:26.84#ibcon#about to read 3, iclass 10, count 0 2006.286.04:45:26.88#ibcon#read 3, iclass 10, count 0 2006.286.04:45:26.88#ibcon#about to read 4, iclass 10, count 0 2006.286.04:45:26.88#ibcon#read 4, iclass 10, count 0 2006.286.04:45:26.88#ibcon#about to read 5, iclass 10, count 0 2006.286.04:45:26.88#ibcon#read 5, iclass 10, count 0 2006.286.04:45:26.88#ibcon#about to read 6, iclass 10, count 0 2006.286.04:45:26.88#ibcon#read 6, iclass 10, count 0 2006.286.04:45:26.88#ibcon#end of sib2, iclass 10, count 0 2006.286.04:45:26.88#ibcon#*after write, iclass 10, count 0 2006.286.04:45:26.88#ibcon#*before return 0, iclass 10, count 0 2006.286.04:45:26.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:45:26.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:45:26.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:45:26.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:45:26.88$vck44/va=5,3 2006.286.04:45:26.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.04:45:26.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.04:45:26.88#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:26.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:45:26.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:45:26.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:45:26.88#ibcon#enter wrdev, iclass 12, count 2 2006.286.04:45:26.88#ibcon#first serial, iclass 12, count 2 2006.286.04:45:26.88#ibcon#enter sib2, iclass 12, count 2 2006.286.04:45:26.88#ibcon#flushed, iclass 12, count 2 2006.286.04:45:26.88#ibcon#about to write, iclass 12, count 2 2006.286.04:45:26.88#ibcon#wrote, iclass 12, count 2 2006.286.04:45:26.88#ibcon#about to read 3, iclass 12, count 2 2006.286.04:45:26.90#ibcon#read 3, iclass 12, count 2 2006.286.04:45:26.90#ibcon#about to read 4, iclass 12, count 2 2006.286.04:45:26.90#ibcon#read 4, iclass 12, count 2 2006.286.04:45:26.90#ibcon#about to read 5, iclass 12, count 2 2006.286.04:45:26.90#ibcon#read 5, iclass 12, count 2 2006.286.04:45:26.90#ibcon#about to read 6, iclass 12, count 2 2006.286.04:45:26.90#ibcon#read 6, iclass 12, count 2 2006.286.04:45:26.90#ibcon#end of sib2, iclass 12, count 2 2006.286.04:45:26.90#ibcon#*mode == 0, iclass 12, count 2 2006.286.04:45:26.90#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.04:45:26.90#ibcon#[25=AT05-03\r\n] 2006.286.04:45:26.90#ibcon#*before write, iclass 12, count 2 2006.286.04:45:26.90#ibcon#enter sib2, iclass 12, count 2 2006.286.04:45:26.90#ibcon#flushed, iclass 12, count 2 2006.286.04:45:26.90#ibcon#about to write, iclass 12, count 2 2006.286.04:45:26.90#ibcon#wrote, iclass 12, count 2 2006.286.04:45:26.90#ibcon#about to read 3, iclass 12, count 2 2006.286.04:45:26.93#ibcon#read 3, iclass 12, count 2 2006.286.04:45:26.93#ibcon#about to read 4, iclass 12, count 2 2006.286.04:45:26.93#ibcon#read 4, iclass 12, count 2 2006.286.04:45:26.93#ibcon#about to read 5, iclass 12, count 2 2006.286.04:45:26.93#ibcon#read 5, iclass 12, count 2 2006.286.04:45:26.93#ibcon#about to read 6, iclass 12, count 2 2006.286.04:45:26.93#ibcon#read 6, iclass 12, count 2 2006.286.04:45:26.93#ibcon#end of sib2, iclass 12, count 2 2006.286.04:45:26.93#ibcon#*after write, iclass 12, count 2 2006.286.04:45:26.93#ibcon#*before return 0, iclass 12, count 2 2006.286.04:45:26.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:45:26.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:45:26.93#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.04:45:26.93#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:26.93#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:45:27.05#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:45:27.05#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:45:27.05#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:45:27.05#ibcon#first serial, iclass 12, count 0 2006.286.04:45:27.05#ibcon#enter sib2, iclass 12, count 0 2006.286.04:45:27.05#ibcon#flushed, iclass 12, count 0 2006.286.04:45:27.05#ibcon#about to write, iclass 12, count 0 2006.286.04:45:27.05#ibcon#wrote, iclass 12, count 0 2006.286.04:45:27.05#ibcon#about to read 3, iclass 12, count 0 2006.286.04:45:27.07#ibcon#read 3, iclass 12, count 0 2006.286.04:45:27.07#ibcon#about to read 4, iclass 12, count 0 2006.286.04:45:27.07#ibcon#read 4, iclass 12, count 0 2006.286.04:45:27.07#ibcon#about to read 5, iclass 12, count 0 2006.286.04:45:27.07#ibcon#read 5, iclass 12, count 0 2006.286.04:45:27.07#ibcon#about to read 6, iclass 12, count 0 2006.286.04:45:27.07#ibcon#read 6, iclass 12, count 0 2006.286.04:45:27.07#ibcon#end of sib2, iclass 12, count 0 2006.286.04:45:27.07#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:45:27.07#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:45:27.07#ibcon#[25=USB\r\n] 2006.286.04:45:27.07#ibcon#*before write, iclass 12, count 0 2006.286.04:45:27.07#ibcon#enter sib2, iclass 12, count 0 2006.286.04:45:27.07#ibcon#flushed, iclass 12, count 0 2006.286.04:45:27.07#ibcon#about to write, iclass 12, count 0 2006.286.04:45:27.07#ibcon#wrote, iclass 12, count 0 2006.286.04:45:27.07#ibcon#about to read 3, iclass 12, count 0 2006.286.04:45:27.10#ibcon#read 3, iclass 12, count 0 2006.286.04:45:27.10#ibcon#about to read 4, iclass 12, count 0 2006.286.04:45:27.10#ibcon#read 4, iclass 12, count 0 2006.286.04:45:27.10#ibcon#about to read 5, iclass 12, count 0 2006.286.04:45:27.10#ibcon#read 5, iclass 12, count 0 2006.286.04:45:27.10#ibcon#about to read 6, iclass 12, count 0 2006.286.04:45:27.10#ibcon#read 6, iclass 12, count 0 2006.286.04:45:27.10#ibcon#end of sib2, iclass 12, count 0 2006.286.04:45:27.10#ibcon#*after write, iclass 12, count 0 2006.286.04:45:27.10#ibcon#*before return 0, iclass 12, count 0 2006.286.04:45:27.10#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:45:27.10#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:45:27.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:45:27.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:45:27.10$vck44/valo=6,814.99 2006.286.04:45:27.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.04:45:27.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.04:45:27.10#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:27.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:45:27.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:45:27.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:45:27.10#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:45:27.10#ibcon#first serial, iclass 14, count 0 2006.286.04:45:27.10#ibcon#enter sib2, iclass 14, count 0 2006.286.04:45:27.10#ibcon#flushed, iclass 14, count 0 2006.286.04:45:27.10#ibcon#about to write, iclass 14, count 0 2006.286.04:45:27.10#ibcon#wrote, iclass 14, count 0 2006.286.04:45:27.10#ibcon#about to read 3, iclass 14, count 0 2006.286.04:45:27.12#ibcon#read 3, iclass 14, count 0 2006.286.04:45:27.12#ibcon#about to read 4, iclass 14, count 0 2006.286.04:45:27.12#ibcon#read 4, iclass 14, count 0 2006.286.04:45:27.12#ibcon#about to read 5, iclass 14, count 0 2006.286.04:45:27.12#ibcon#read 5, iclass 14, count 0 2006.286.04:45:27.12#ibcon#about to read 6, iclass 14, count 0 2006.286.04:45:27.12#ibcon#read 6, iclass 14, count 0 2006.286.04:45:27.12#ibcon#end of sib2, iclass 14, count 0 2006.286.04:45:27.12#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:45:27.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:45:27.12#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:45:27.12#ibcon#*before write, iclass 14, count 0 2006.286.04:45:27.12#ibcon#enter sib2, iclass 14, count 0 2006.286.04:45:27.12#ibcon#flushed, iclass 14, count 0 2006.286.04:45:27.12#ibcon#about to write, iclass 14, count 0 2006.286.04:45:27.12#ibcon#wrote, iclass 14, count 0 2006.286.04:45:27.12#ibcon#about to read 3, iclass 14, count 0 2006.286.04:45:27.16#ibcon#read 3, iclass 14, count 0 2006.286.04:45:27.16#ibcon#about to read 4, iclass 14, count 0 2006.286.04:45:27.16#ibcon#read 4, iclass 14, count 0 2006.286.04:45:27.16#ibcon#about to read 5, iclass 14, count 0 2006.286.04:45:27.16#ibcon#read 5, iclass 14, count 0 2006.286.04:45:27.16#ibcon#about to read 6, iclass 14, count 0 2006.286.04:45:27.16#ibcon#read 6, iclass 14, count 0 2006.286.04:45:27.16#ibcon#end of sib2, iclass 14, count 0 2006.286.04:45:27.16#ibcon#*after write, iclass 14, count 0 2006.286.04:45:27.16#ibcon#*before return 0, iclass 14, count 0 2006.286.04:45:27.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:45:27.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:45:27.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:45:27.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:45:27.16$vck44/va=6,4 2006.286.04:45:27.16#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.04:45:27.16#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.04:45:27.16#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:27.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:45:27.18#abcon#<5=/04 3.8 6.3 22.25 741014.8\r\n> 2006.286.04:45:27.20#abcon#{5=INTERFACE CLEAR} 2006.286.04:45:27.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:45:27.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:45:27.22#ibcon#enter wrdev, iclass 17, count 2 2006.286.04:45:27.22#ibcon#first serial, iclass 17, count 2 2006.286.04:45:27.22#ibcon#enter sib2, iclass 17, count 2 2006.286.04:45:27.22#ibcon#flushed, iclass 17, count 2 2006.286.04:45:27.22#ibcon#about to write, iclass 17, count 2 2006.286.04:45:27.22#ibcon#wrote, iclass 17, count 2 2006.286.04:45:27.22#ibcon#about to read 3, iclass 17, count 2 2006.286.04:45:27.24#ibcon#read 3, iclass 17, count 2 2006.286.04:45:27.24#ibcon#about to read 4, iclass 17, count 2 2006.286.04:45:27.24#ibcon#read 4, iclass 17, count 2 2006.286.04:45:27.24#ibcon#about to read 5, iclass 17, count 2 2006.286.04:45:27.24#ibcon#read 5, iclass 17, count 2 2006.286.04:45:27.24#ibcon#about to read 6, iclass 17, count 2 2006.286.04:45:27.24#ibcon#read 6, iclass 17, count 2 2006.286.04:45:27.24#ibcon#end of sib2, iclass 17, count 2 2006.286.04:45:27.24#ibcon#*mode == 0, iclass 17, count 2 2006.286.04:45:27.24#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.04:45:27.24#ibcon#[25=AT06-04\r\n] 2006.286.04:45:27.24#ibcon#*before write, iclass 17, count 2 2006.286.04:45:27.24#ibcon#enter sib2, iclass 17, count 2 2006.286.04:45:27.24#ibcon#flushed, iclass 17, count 2 2006.286.04:45:27.24#ibcon#about to write, iclass 17, count 2 2006.286.04:45:27.24#ibcon#wrote, iclass 17, count 2 2006.286.04:45:27.24#ibcon#about to read 3, iclass 17, count 2 2006.286.04:45:27.26#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:45:27.27#ibcon#read 3, iclass 17, count 2 2006.286.04:45:27.27#ibcon#about to read 4, iclass 17, count 2 2006.286.04:45:27.27#ibcon#read 4, iclass 17, count 2 2006.286.04:45:27.27#ibcon#about to read 5, iclass 17, count 2 2006.286.04:45:27.27#ibcon#read 5, iclass 17, count 2 2006.286.04:45:27.27#ibcon#about to read 6, iclass 17, count 2 2006.286.04:45:27.27#ibcon#read 6, iclass 17, count 2 2006.286.04:45:27.27#ibcon#end of sib2, iclass 17, count 2 2006.286.04:45:27.27#ibcon#*after write, iclass 17, count 2 2006.286.04:45:27.27#ibcon#*before return 0, iclass 17, count 2 2006.286.04:45:27.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:45:27.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:45:27.27#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.04:45:27.27#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:27.27#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:45:27.39#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:45:27.39#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:45:27.39#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:45:27.39#ibcon#first serial, iclass 17, count 0 2006.286.04:45:27.39#ibcon#enter sib2, iclass 17, count 0 2006.286.04:45:27.39#ibcon#flushed, iclass 17, count 0 2006.286.04:45:27.39#ibcon#about to write, iclass 17, count 0 2006.286.04:45:27.39#ibcon#wrote, iclass 17, count 0 2006.286.04:45:27.39#ibcon#about to read 3, iclass 17, count 0 2006.286.04:45:27.41#ibcon#read 3, iclass 17, count 0 2006.286.04:45:27.41#ibcon#about to read 4, iclass 17, count 0 2006.286.04:45:27.41#ibcon#read 4, iclass 17, count 0 2006.286.04:45:27.41#ibcon#about to read 5, iclass 17, count 0 2006.286.04:45:27.41#ibcon#read 5, iclass 17, count 0 2006.286.04:45:27.41#ibcon#about to read 6, iclass 17, count 0 2006.286.04:45:27.41#ibcon#read 6, iclass 17, count 0 2006.286.04:45:27.41#ibcon#end of sib2, iclass 17, count 0 2006.286.04:45:27.41#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:45:27.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:45:27.41#ibcon#[25=USB\r\n] 2006.286.04:45:27.41#ibcon#*before write, iclass 17, count 0 2006.286.04:45:27.41#ibcon#enter sib2, iclass 17, count 0 2006.286.04:45:27.41#ibcon#flushed, iclass 17, count 0 2006.286.04:45:27.41#ibcon#about to write, iclass 17, count 0 2006.286.04:45:27.41#ibcon#wrote, iclass 17, count 0 2006.286.04:45:27.41#ibcon#about to read 3, iclass 17, count 0 2006.286.04:45:27.44#ibcon#read 3, iclass 17, count 0 2006.286.04:45:27.44#ibcon#about to read 4, iclass 17, count 0 2006.286.04:45:27.44#ibcon#read 4, iclass 17, count 0 2006.286.04:45:27.44#ibcon#about to read 5, iclass 17, count 0 2006.286.04:45:27.44#ibcon#read 5, iclass 17, count 0 2006.286.04:45:27.44#ibcon#about to read 6, iclass 17, count 0 2006.286.04:45:27.44#ibcon#read 6, iclass 17, count 0 2006.286.04:45:27.44#ibcon#end of sib2, iclass 17, count 0 2006.286.04:45:27.44#ibcon#*after write, iclass 17, count 0 2006.286.04:45:27.44#ibcon#*before return 0, iclass 17, count 0 2006.286.04:45:27.44#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:45:27.44#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:45:27.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:45:27.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:45:27.44$vck44/valo=7,864.99 2006.286.04:45:27.44#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:45:27.44#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:45:27.44#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:27.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:45:27.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:45:27.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:45:27.44#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:45:27.44#ibcon#first serial, iclass 22, count 0 2006.286.04:45:27.44#ibcon#enter sib2, iclass 22, count 0 2006.286.04:45:27.44#ibcon#flushed, iclass 22, count 0 2006.286.04:45:27.44#ibcon#about to write, iclass 22, count 0 2006.286.04:45:27.44#ibcon#wrote, iclass 22, count 0 2006.286.04:45:27.44#ibcon#about to read 3, iclass 22, count 0 2006.286.04:45:27.46#ibcon#read 3, iclass 22, count 0 2006.286.04:45:27.46#ibcon#about to read 4, iclass 22, count 0 2006.286.04:45:27.46#ibcon#read 4, iclass 22, count 0 2006.286.04:45:27.46#ibcon#about to read 5, iclass 22, count 0 2006.286.04:45:27.46#ibcon#read 5, iclass 22, count 0 2006.286.04:45:27.46#ibcon#about to read 6, iclass 22, count 0 2006.286.04:45:27.46#ibcon#read 6, iclass 22, count 0 2006.286.04:45:27.46#ibcon#end of sib2, iclass 22, count 0 2006.286.04:45:27.46#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:45:27.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:45:27.46#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:45:27.46#ibcon#*before write, iclass 22, count 0 2006.286.04:45:27.46#ibcon#enter sib2, iclass 22, count 0 2006.286.04:45:27.46#ibcon#flushed, iclass 22, count 0 2006.286.04:45:27.46#ibcon#about to write, iclass 22, count 0 2006.286.04:45:27.46#ibcon#wrote, iclass 22, count 0 2006.286.04:45:27.46#ibcon#about to read 3, iclass 22, count 0 2006.286.04:45:27.50#ibcon#read 3, iclass 22, count 0 2006.286.04:45:27.50#ibcon#about to read 4, iclass 22, count 0 2006.286.04:45:27.50#ibcon#read 4, iclass 22, count 0 2006.286.04:45:27.50#ibcon#about to read 5, iclass 22, count 0 2006.286.04:45:27.50#ibcon#read 5, iclass 22, count 0 2006.286.04:45:27.50#ibcon#about to read 6, iclass 22, count 0 2006.286.04:45:27.50#ibcon#read 6, iclass 22, count 0 2006.286.04:45:27.50#ibcon#end of sib2, iclass 22, count 0 2006.286.04:45:27.50#ibcon#*after write, iclass 22, count 0 2006.286.04:45:27.50#ibcon#*before return 0, iclass 22, count 0 2006.286.04:45:27.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:45:27.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:45:27.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:45:27.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:45:27.50$vck44/va=7,4 2006.286.04:45:27.50#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.04:45:27.50#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.04:45:27.50#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:27.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:45:27.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:45:27.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:45:27.56#ibcon#enter wrdev, iclass 24, count 2 2006.286.04:45:27.56#ibcon#first serial, iclass 24, count 2 2006.286.04:45:27.56#ibcon#enter sib2, iclass 24, count 2 2006.286.04:45:27.56#ibcon#flushed, iclass 24, count 2 2006.286.04:45:27.56#ibcon#about to write, iclass 24, count 2 2006.286.04:45:27.56#ibcon#wrote, iclass 24, count 2 2006.286.04:45:27.56#ibcon#about to read 3, iclass 24, count 2 2006.286.04:45:27.58#ibcon#read 3, iclass 24, count 2 2006.286.04:45:27.58#ibcon#about to read 4, iclass 24, count 2 2006.286.04:45:27.58#ibcon#read 4, iclass 24, count 2 2006.286.04:45:27.58#ibcon#about to read 5, iclass 24, count 2 2006.286.04:45:27.58#ibcon#read 5, iclass 24, count 2 2006.286.04:45:27.58#ibcon#about to read 6, iclass 24, count 2 2006.286.04:45:27.58#ibcon#read 6, iclass 24, count 2 2006.286.04:45:27.58#ibcon#end of sib2, iclass 24, count 2 2006.286.04:45:27.58#ibcon#*mode == 0, iclass 24, count 2 2006.286.04:45:27.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.04:45:27.58#ibcon#[25=AT07-04\r\n] 2006.286.04:45:27.58#ibcon#*before write, iclass 24, count 2 2006.286.04:45:27.58#ibcon#enter sib2, iclass 24, count 2 2006.286.04:45:27.58#ibcon#flushed, iclass 24, count 2 2006.286.04:45:27.58#ibcon#about to write, iclass 24, count 2 2006.286.04:45:27.58#ibcon#wrote, iclass 24, count 2 2006.286.04:45:27.58#ibcon#about to read 3, iclass 24, count 2 2006.286.04:45:27.61#ibcon#read 3, iclass 24, count 2 2006.286.04:45:27.61#ibcon#about to read 4, iclass 24, count 2 2006.286.04:45:27.61#ibcon#read 4, iclass 24, count 2 2006.286.04:45:27.61#ibcon#about to read 5, iclass 24, count 2 2006.286.04:45:27.61#ibcon#read 5, iclass 24, count 2 2006.286.04:45:27.61#ibcon#about to read 6, iclass 24, count 2 2006.286.04:45:27.61#ibcon#read 6, iclass 24, count 2 2006.286.04:45:27.61#ibcon#end of sib2, iclass 24, count 2 2006.286.04:45:27.61#ibcon#*after write, iclass 24, count 2 2006.286.04:45:27.61#ibcon#*before return 0, iclass 24, count 2 2006.286.04:45:27.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:45:27.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:45:27.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.04:45:27.61#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:27.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:45:27.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:45:27.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:45:27.73#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:45:27.73#ibcon#first serial, iclass 24, count 0 2006.286.04:45:27.73#ibcon#enter sib2, iclass 24, count 0 2006.286.04:45:27.73#ibcon#flushed, iclass 24, count 0 2006.286.04:45:27.73#ibcon#about to write, iclass 24, count 0 2006.286.04:45:27.73#ibcon#wrote, iclass 24, count 0 2006.286.04:45:27.73#ibcon#about to read 3, iclass 24, count 0 2006.286.04:45:27.75#ibcon#read 3, iclass 24, count 0 2006.286.04:45:27.75#ibcon#about to read 4, iclass 24, count 0 2006.286.04:45:27.75#ibcon#read 4, iclass 24, count 0 2006.286.04:45:27.75#ibcon#about to read 5, iclass 24, count 0 2006.286.04:45:27.75#ibcon#read 5, iclass 24, count 0 2006.286.04:45:27.75#ibcon#about to read 6, iclass 24, count 0 2006.286.04:45:27.75#ibcon#read 6, iclass 24, count 0 2006.286.04:45:27.75#ibcon#end of sib2, iclass 24, count 0 2006.286.04:45:27.75#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:45:27.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:45:27.75#ibcon#[25=USB\r\n] 2006.286.04:45:27.75#ibcon#*before write, iclass 24, count 0 2006.286.04:45:27.75#ibcon#enter sib2, iclass 24, count 0 2006.286.04:45:27.75#ibcon#flushed, iclass 24, count 0 2006.286.04:45:27.75#ibcon#about to write, iclass 24, count 0 2006.286.04:45:27.75#ibcon#wrote, iclass 24, count 0 2006.286.04:45:27.75#ibcon#about to read 3, iclass 24, count 0 2006.286.04:45:27.78#ibcon#read 3, iclass 24, count 0 2006.286.04:45:27.78#ibcon#about to read 4, iclass 24, count 0 2006.286.04:45:27.78#ibcon#read 4, iclass 24, count 0 2006.286.04:45:27.78#ibcon#about to read 5, iclass 24, count 0 2006.286.04:45:27.78#ibcon#read 5, iclass 24, count 0 2006.286.04:45:27.78#ibcon#about to read 6, iclass 24, count 0 2006.286.04:45:27.78#ibcon#read 6, iclass 24, count 0 2006.286.04:45:27.78#ibcon#end of sib2, iclass 24, count 0 2006.286.04:45:27.78#ibcon#*after write, iclass 24, count 0 2006.286.04:45:27.78#ibcon#*before return 0, iclass 24, count 0 2006.286.04:45:27.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:45:27.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:45:27.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:45:27.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:45:27.78$vck44/valo=8,884.99 2006.286.04:45:27.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.04:45:27.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.04:45:27.78#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:27.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:45:27.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:45:27.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:45:27.78#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:45:27.78#ibcon#first serial, iclass 26, count 0 2006.286.04:45:27.78#ibcon#enter sib2, iclass 26, count 0 2006.286.04:45:27.78#ibcon#flushed, iclass 26, count 0 2006.286.04:45:27.78#ibcon#about to write, iclass 26, count 0 2006.286.04:45:27.78#ibcon#wrote, iclass 26, count 0 2006.286.04:45:27.78#ibcon#about to read 3, iclass 26, count 0 2006.286.04:45:27.80#ibcon#read 3, iclass 26, count 0 2006.286.04:45:27.80#ibcon#about to read 4, iclass 26, count 0 2006.286.04:45:27.80#ibcon#read 4, iclass 26, count 0 2006.286.04:45:27.80#ibcon#about to read 5, iclass 26, count 0 2006.286.04:45:27.80#ibcon#read 5, iclass 26, count 0 2006.286.04:45:27.80#ibcon#about to read 6, iclass 26, count 0 2006.286.04:45:27.80#ibcon#read 6, iclass 26, count 0 2006.286.04:45:27.80#ibcon#end of sib2, iclass 26, count 0 2006.286.04:45:27.80#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:45:27.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:45:27.80#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:45:27.80#ibcon#*before write, iclass 26, count 0 2006.286.04:45:27.80#ibcon#enter sib2, iclass 26, count 0 2006.286.04:45:27.80#ibcon#flushed, iclass 26, count 0 2006.286.04:45:27.80#ibcon#about to write, iclass 26, count 0 2006.286.04:45:27.80#ibcon#wrote, iclass 26, count 0 2006.286.04:45:27.80#ibcon#about to read 3, iclass 26, count 0 2006.286.04:45:27.84#ibcon#read 3, iclass 26, count 0 2006.286.04:45:27.84#ibcon#about to read 4, iclass 26, count 0 2006.286.04:45:27.84#ibcon#read 4, iclass 26, count 0 2006.286.04:45:27.84#ibcon#about to read 5, iclass 26, count 0 2006.286.04:45:27.84#ibcon#read 5, iclass 26, count 0 2006.286.04:45:27.84#ibcon#about to read 6, iclass 26, count 0 2006.286.04:45:27.84#ibcon#read 6, iclass 26, count 0 2006.286.04:45:27.84#ibcon#end of sib2, iclass 26, count 0 2006.286.04:45:27.84#ibcon#*after write, iclass 26, count 0 2006.286.04:45:27.84#ibcon#*before return 0, iclass 26, count 0 2006.286.04:45:27.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:45:27.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:45:27.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:45:27.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:45:27.84$vck44/va=8,3 2006.286.04:45:27.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.04:45:27.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.04:45:27.84#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:27.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:45:27.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:45:27.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:45:27.90#ibcon#enter wrdev, iclass 28, count 2 2006.286.04:45:27.90#ibcon#first serial, iclass 28, count 2 2006.286.04:45:27.90#ibcon#enter sib2, iclass 28, count 2 2006.286.04:45:27.90#ibcon#flushed, iclass 28, count 2 2006.286.04:45:27.90#ibcon#about to write, iclass 28, count 2 2006.286.04:45:27.90#ibcon#wrote, iclass 28, count 2 2006.286.04:45:27.90#ibcon#about to read 3, iclass 28, count 2 2006.286.04:45:27.92#ibcon#read 3, iclass 28, count 2 2006.286.04:45:27.92#ibcon#about to read 4, iclass 28, count 2 2006.286.04:45:27.92#ibcon#read 4, iclass 28, count 2 2006.286.04:45:27.92#ibcon#about to read 5, iclass 28, count 2 2006.286.04:45:27.92#ibcon#read 5, iclass 28, count 2 2006.286.04:45:27.92#ibcon#about to read 6, iclass 28, count 2 2006.286.04:45:27.92#ibcon#read 6, iclass 28, count 2 2006.286.04:45:27.92#ibcon#end of sib2, iclass 28, count 2 2006.286.04:45:27.92#ibcon#*mode == 0, iclass 28, count 2 2006.286.04:45:27.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.04:45:27.92#ibcon#[25=AT08-03\r\n] 2006.286.04:45:27.92#ibcon#*before write, iclass 28, count 2 2006.286.04:45:27.92#ibcon#enter sib2, iclass 28, count 2 2006.286.04:45:27.92#ibcon#flushed, iclass 28, count 2 2006.286.04:45:27.92#ibcon#about to write, iclass 28, count 2 2006.286.04:45:27.92#ibcon#wrote, iclass 28, count 2 2006.286.04:45:27.92#ibcon#about to read 3, iclass 28, count 2 2006.286.04:45:27.95#ibcon#read 3, iclass 28, count 2 2006.286.04:45:27.95#ibcon#about to read 4, iclass 28, count 2 2006.286.04:45:28.34#ibcon#read 4, iclass 28, count 2 2006.286.04:45:28.34#ibcon#about to read 5, iclass 28, count 2 2006.286.04:45:28.34#ibcon#read 5, iclass 28, count 2 2006.286.04:45:28.34#ibcon#about to read 6, iclass 28, count 2 2006.286.04:45:28.34#ibcon#read 6, iclass 28, count 2 2006.286.04:45:28.34#ibcon#end of sib2, iclass 28, count 2 2006.286.04:45:28.34#ibcon#*after write, iclass 28, count 2 2006.286.04:45:28.34#ibcon#*before return 0, iclass 28, count 2 2006.286.04:45:28.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:45:28.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:45:28.34#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.04:45:28.34#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:28.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:45:28.45#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:45:28.45#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:45:28.45#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:45:28.45#ibcon#first serial, iclass 28, count 0 2006.286.04:45:28.45#ibcon#enter sib2, iclass 28, count 0 2006.286.04:45:28.45#ibcon#flushed, iclass 28, count 0 2006.286.04:45:28.45#ibcon#about to write, iclass 28, count 0 2006.286.04:45:28.45#ibcon#wrote, iclass 28, count 0 2006.286.04:45:28.45#ibcon#about to read 3, iclass 28, count 0 2006.286.04:45:28.47#ibcon#read 3, iclass 28, count 0 2006.286.04:45:28.47#ibcon#about to read 4, iclass 28, count 0 2006.286.04:45:28.47#ibcon#read 4, iclass 28, count 0 2006.286.04:45:28.47#ibcon#about to read 5, iclass 28, count 0 2006.286.04:45:28.47#ibcon#read 5, iclass 28, count 0 2006.286.04:45:28.47#ibcon#about to read 6, iclass 28, count 0 2006.286.04:45:28.47#ibcon#read 6, iclass 28, count 0 2006.286.04:45:28.47#ibcon#end of sib2, iclass 28, count 0 2006.286.04:45:28.47#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:45:28.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:45:28.47#ibcon#[25=USB\r\n] 2006.286.04:45:28.47#ibcon#*before write, iclass 28, count 0 2006.286.04:45:28.47#ibcon#enter sib2, iclass 28, count 0 2006.286.04:45:28.47#ibcon#flushed, iclass 28, count 0 2006.286.04:45:28.47#ibcon#about to write, iclass 28, count 0 2006.286.04:45:28.47#ibcon#wrote, iclass 28, count 0 2006.286.04:45:28.47#ibcon#about to read 3, iclass 28, count 0 2006.286.04:45:28.50#ibcon#read 3, iclass 28, count 0 2006.286.04:45:28.50#ibcon#about to read 4, iclass 28, count 0 2006.286.04:45:28.50#ibcon#read 4, iclass 28, count 0 2006.286.04:45:28.50#ibcon#about to read 5, iclass 28, count 0 2006.286.04:45:28.50#ibcon#read 5, iclass 28, count 0 2006.286.04:45:28.50#ibcon#about to read 6, iclass 28, count 0 2006.286.04:45:28.50#ibcon#read 6, iclass 28, count 0 2006.286.04:45:28.50#ibcon#end of sib2, iclass 28, count 0 2006.286.04:45:28.50#ibcon#*after write, iclass 28, count 0 2006.286.04:45:28.50#ibcon#*before return 0, iclass 28, count 0 2006.286.04:45:28.50#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:45:28.50#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:45:28.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:45:28.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:45:28.50$vck44/vblo=1,629.99 2006.286.04:45:28.50#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:45:28.50#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:45:28.50#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:28.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:45:28.50#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:45:28.50#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:45:28.50#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:45:28.50#ibcon#first serial, iclass 30, count 0 2006.286.04:45:28.50#ibcon#enter sib2, iclass 30, count 0 2006.286.04:45:28.50#ibcon#flushed, iclass 30, count 0 2006.286.04:45:28.50#ibcon#about to write, iclass 30, count 0 2006.286.04:45:28.50#ibcon#wrote, iclass 30, count 0 2006.286.04:45:28.50#ibcon#about to read 3, iclass 30, count 0 2006.286.04:45:28.52#ibcon#read 3, iclass 30, count 0 2006.286.04:45:28.52#ibcon#about to read 4, iclass 30, count 0 2006.286.04:45:28.52#ibcon#read 4, iclass 30, count 0 2006.286.04:45:28.52#ibcon#about to read 5, iclass 30, count 0 2006.286.04:45:28.52#ibcon#read 5, iclass 30, count 0 2006.286.04:45:28.52#ibcon#about to read 6, iclass 30, count 0 2006.286.04:45:28.52#ibcon#read 6, iclass 30, count 0 2006.286.04:45:28.52#ibcon#end of sib2, iclass 30, count 0 2006.286.04:45:28.52#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:45:28.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:45:28.52#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:45:28.52#ibcon#*before write, iclass 30, count 0 2006.286.04:45:28.52#ibcon#enter sib2, iclass 30, count 0 2006.286.04:45:28.52#ibcon#flushed, iclass 30, count 0 2006.286.04:45:28.52#ibcon#about to write, iclass 30, count 0 2006.286.04:45:28.52#ibcon#wrote, iclass 30, count 0 2006.286.04:45:28.52#ibcon#about to read 3, iclass 30, count 0 2006.286.04:45:28.56#ibcon#read 3, iclass 30, count 0 2006.286.04:45:28.56#ibcon#about to read 4, iclass 30, count 0 2006.286.04:45:28.56#ibcon#read 4, iclass 30, count 0 2006.286.04:45:28.56#ibcon#about to read 5, iclass 30, count 0 2006.286.04:45:28.56#ibcon#read 5, iclass 30, count 0 2006.286.04:45:28.56#ibcon#about to read 6, iclass 30, count 0 2006.286.04:45:28.56#ibcon#read 6, iclass 30, count 0 2006.286.04:45:28.56#ibcon#end of sib2, iclass 30, count 0 2006.286.04:45:28.56#ibcon#*after write, iclass 30, count 0 2006.286.04:45:28.56#ibcon#*before return 0, iclass 30, count 0 2006.286.04:45:28.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:45:28.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:45:28.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:45:28.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:45:28.56$vck44/vb=1,4 2006.286.04:45:28.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.04:45:28.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.04:45:28.56#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:28.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:45:28.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:45:28.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:45:28.56#ibcon#enter wrdev, iclass 32, count 2 2006.286.04:45:28.56#ibcon#first serial, iclass 32, count 2 2006.286.04:45:28.56#ibcon#enter sib2, iclass 32, count 2 2006.286.04:45:28.56#ibcon#flushed, iclass 32, count 2 2006.286.04:45:28.56#ibcon#about to write, iclass 32, count 2 2006.286.04:45:28.56#ibcon#wrote, iclass 32, count 2 2006.286.04:45:28.56#ibcon#about to read 3, iclass 32, count 2 2006.286.04:45:28.58#ibcon#read 3, iclass 32, count 2 2006.286.04:45:28.58#ibcon#about to read 4, iclass 32, count 2 2006.286.04:45:28.58#ibcon#read 4, iclass 32, count 2 2006.286.04:45:28.58#ibcon#about to read 5, iclass 32, count 2 2006.286.04:45:28.58#ibcon#read 5, iclass 32, count 2 2006.286.04:45:28.58#ibcon#about to read 6, iclass 32, count 2 2006.286.04:45:28.58#ibcon#read 6, iclass 32, count 2 2006.286.04:45:28.58#ibcon#end of sib2, iclass 32, count 2 2006.286.04:45:28.58#ibcon#*mode == 0, iclass 32, count 2 2006.286.04:45:28.58#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.04:45:28.58#ibcon#[27=AT01-04\r\n] 2006.286.04:45:28.58#ibcon#*before write, iclass 32, count 2 2006.286.04:45:28.58#ibcon#enter sib2, iclass 32, count 2 2006.286.04:45:28.58#ibcon#flushed, iclass 32, count 2 2006.286.04:45:28.58#ibcon#about to write, iclass 32, count 2 2006.286.04:45:28.58#ibcon#wrote, iclass 32, count 2 2006.286.04:45:28.58#ibcon#about to read 3, iclass 32, count 2 2006.286.04:45:28.61#ibcon#read 3, iclass 32, count 2 2006.286.04:45:28.61#ibcon#about to read 4, iclass 32, count 2 2006.286.04:45:28.61#ibcon#read 4, iclass 32, count 2 2006.286.04:45:28.61#ibcon#about to read 5, iclass 32, count 2 2006.286.04:45:28.61#ibcon#read 5, iclass 32, count 2 2006.286.04:45:28.61#ibcon#about to read 6, iclass 32, count 2 2006.286.04:45:28.61#ibcon#read 6, iclass 32, count 2 2006.286.04:45:28.61#ibcon#end of sib2, iclass 32, count 2 2006.286.04:45:28.61#ibcon#*after write, iclass 32, count 2 2006.286.04:45:28.61#ibcon#*before return 0, iclass 32, count 2 2006.286.04:45:28.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:45:28.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:45:28.61#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.04:45:28.61#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:28.61#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:45:28.73#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:45:28.73#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:45:28.73#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:45:28.73#ibcon#first serial, iclass 32, count 0 2006.286.04:45:28.73#ibcon#enter sib2, iclass 32, count 0 2006.286.04:45:28.73#ibcon#flushed, iclass 32, count 0 2006.286.04:45:28.73#ibcon#about to write, iclass 32, count 0 2006.286.04:45:28.73#ibcon#wrote, iclass 32, count 0 2006.286.04:45:28.73#ibcon#about to read 3, iclass 32, count 0 2006.286.04:45:28.75#ibcon#read 3, iclass 32, count 0 2006.286.04:45:28.75#ibcon#about to read 4, iclass 32, count 0 2006.286.04:45:28.75#ibcon#read 4, iclass 32, count 0 2006.286.04:45:28.75#ibcon#about to read 5, iclass 32, count 0 2006.286.04:45:28.75#ibcon#read 5, iclass 32, count 0 2006.286.04:45:28.75#ibcon#about to read 6, iclass 32, count 0 2006.286.04:45:28.75#ibcon#read 6, iclass 32, count 0 2006.286.04:45:28.75#ibcon#end of sib2, iclass 32, count 0 2006.286.04:45:28.75#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:45:28.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:45:28.75#ibcon#[27=USB\r\n] 2006.286.04:45:28.75#ibcon#*before write, iclass 32, count 0 2006.286.04:45:28.75#ibcon#enter sib2, iclass 32, count 0 2006.286.04:45:28.75#ibcon#flushed, iclass 32, count 0 2006.286.04:45:28.75#ibcon#about to write, iclass 32, count 0 2006.286.04:45:28.75#ibcon#wrote, iclass 32, count 0 2006.286.04:45:28.75#ibcon#about to read 3, iclass 32, count 0 2006.286.04:45:28.78#ibcon#read 3, iclass 32, count 0 2006.286.04:45:28.78#ibcon#about to read 4, iclass 32, count 0 2006.286.04:45:28.78#ibcon#read 4, iclass 32, count 0 2006.286.04:45:28.78#ibcon#about to read 5, iclass 32, count 0 2006.286.04:45:28.78#ibcon#read 5, iclass 32, count 0 2006.286.04:45:28.78#ibcon#about to read 6, iclass 32, count 0 2006.286.04:45:28.78#ibcon#read 6, iclass 32, count 0 2006.286.04:45:28.78#ibcon#end of sib2, iclass 32, count 0 2006.286.04:45:28.78#ibcon#*after write, iclass 32, count 0 2006.286.04:45:28.78#ibcon#*before return 0, iclass 32, count 0 2006.286.04:45:28.78#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:45:28.78#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:45:28.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:45:28.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:45:28.78$vck44/vblo=2,634.99 2006.286.04:45:28.78#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.04:45:28.78#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.04:45:28.78#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:28.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:45:28.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:45:28.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:45:28.78#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:45:28.78#ibcon#first serial, iclass 34, count 0 2006.286.04:45:28.78#ibcon#enter sib2, iclass 34, count 0 2006.286.04:45:28.78#ibcon#flushed, iclass 34, count 0 2006.286.04:45:28.78#ibcon#about to write, iclass 34, count 0 2006.286.04:45:28.78#ibcon#wrote, iclass 34, count 0 2006.286.04:45:28.78#ibcon#about to read 3, iclass 34, count 0 2006.286.04:45:28.80#ibcon#read 3, iclass 34, count 0 2006.286.04:45:28.80#ibcon#about to read 4, iclass 34, count 0 2006.286.04:45:28.80#ibcon#read 4, iclass 34, count 0 2006.286.04:45:28.80#ibcon#about to read 5, iclass 34, count 0 2006.286.04:45:28.80#ibcon#read 5, iclass 34, count 0 2006.286.04:45:28.80#ibcon#about to read 6, iclass 34, count 0 2006.286.04:45:28.80#ibcon#read 6, iclass 34, count 0 2006.286.04:45:28.80#ibcon#end of sib2, iclass 34, count 0 2006.286.04:45:28.80#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:45:28.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:45:28.80#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:45:28.80#ibcon#*before write, iclass 34, count 0 2006.286.04:45:28.80#ibcon#enter sib2, iclass 34, count 0 2006.286.04:45:28.80#ibcon#flushed, iclass 34, count 0 2006.286.04:45:28.80#ibcon#about to write, iclass 34, count 0 2006.286.04:45:28.80#ibcon#wrote, iclass 34, count 0 2006.286.04:45:28.80#ibcon#about to read 3, iclass 34, count 0 2006.286.04:45:28.84#ibcon#read 3, iclass 34, count 0 2006.286.04:45:28.84#ibcon#about to read 4, iclass 34, count 0 2006.286.04:45:28.84#ibcon#read 4, iclass 34, count 0 2006.286.04:45:28.84#ibcon#about to read 5, iclass 34, count 0 2006.286.04:45:28.84#ibcon#read 5, iclass 34, count 0 2006.286.04:45:28.84#ibcon#about to read 6, iclass 34, count 0 2006.286.04:45:28.84#ibcon#read 6, iclass 34, count 0 2006.286.04:45:28.84#ibcon#end of sib2, iclass 34, count 0 2006.286.04:45:28.84#ibcon#*after write, iclass 34, count 0 2006.286.04:45:28.84#ibcon#*before return 0, iclass 34, count 0 2006.286.04:45:28.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:45:28.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:45:28.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:45:28.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:45:28.84$vck44/vb=2,5 2006.286.04:45:28.84#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.04:45:28.84#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.04:45:28.84#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:28.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:45:28.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:45:28.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:45:28.90#ibcon#enter wrdev, iclass 36, count 2 2006.286.04:45:28.90#ibcon#first serial, iclass 36, count 2 2006.286.04:45:28.90#ibcon#enter sib2, iclass 36, count 2 2006.286.04:45:28.90#ibcon#flushed, iclass 36, count 2 2006.286.04:45:28.90#ibcon#about to write, iclass 36, count 2 2006.286.04:45:28.90#ibcon#wrote, iclass 36, count 2 2006.286.04:45:28.90#ibcon#about to read 3, iclass 36, count 2 2006.286.04:45:28.92#ibcon#read 3, iclass 36, count 2 2006.286.04:45:28.92#ibcon#about to read 4, iclass 36, count 2 2006.286.04:45:28.92#ibcon#read 4, iclass 36, count 2 2006.286.04:45:28.92#ibcon#about to read 5, iclass 36, count 2 2006.286.04:45:28.92#ibcon#read 5, iclass 36, count 2 2006.286.04:45:28.92#ibcon#about to read 6, iclass 36, count 2 2006.286.04:45:28.92#ibcon#read 6, iclass 36, count 2 2006.286.04:45:28.92#ibcon#end of sib2, iclass 36, count 2 2006.286.04:45:28.92#ibcon#*mode == 0, iclass 36, count 2 2006.286.04:45:28.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.04:45:28.92#ibcon#[27=AT02-05\r\n] 2006.286.04:45:28.92#ibcon#*before write, iclass 36, count 2 2006.286.04:45:28.92#ibcon#enter sib2, iclass 36, count 2 2006.286.04:45:28.92#ibcon#flushed, iclass 36, count 2 2006.286.04:45:28.92#ibcon#about to write, iclass 36, count 2 2006.286.04:45:28.92#ibcon#wrote, iclass 36, count 2 2006.286.04:45:28.92#ibcon#about to read 3, iclass 36, count 2 2006.286.04:45:28.95#ibcon#read 3, iclass 36, count 2 2006.286.04:45:28.95#ibcon#about to read 4, iclass 36, count 2 2006.286.04:45:28.98#ibcon#read 4, iclass 36, count 2 2006.286.04:45:28.98#ibcon#about to read 5, iclass 36, count 2 2006.286.04:45:28.98#ibcon#read 5, iclass 36, count 2 2006.286.04:45:28.98#ibcon#about to read 6, iclass 36, count 2 2006.286.04:45:28.98#ibcon#read 6, iclass 36, count 2 2006.286.04:45:28.98#ibcon#end of sib2, iclass 36, count 2 2006.286.04:45:28.98#ibcon#*after write, iclass 36, count 2 2006.286.04:45:28.98#ibcon#*before return 0, iclass 36, count 2 2006.286.04:45:28.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:45:28.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:45:28.98#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.04:45:28.98#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:28.98#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:45:29.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:45:29.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:45:29.09#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:45:29.09#ibcon#first serial, iclass 36, count 0 2006.286.04:45:29.09#ibcon#enter sib2, iclass 36, count 0 2006.286.04:45:29.09#ibcon#flushed, iclass 36, count 0 2006.286.04:45:29.09#ibcon#about to write, iclass 36, count 0 2006.286.04:45:29.09#ibcon#wrote, iclass 36, count 0 2006.286.04:45:29.09#ibcon#about to read 3, iclass 36, count 0 2006.286.04:45:29.11#ibcon#read 3, iclass 36, count 0 2006.286.04:45:29.11#ibcon#about to read 4, iclass 36, count 0 2006.286.04:45:29.11#ibcon#read 4, iclass 36, count 0 2006.286.04:45:29.11#ibcon#about to read 5, iclass 36, count 0 2006.286.04:45:29.11#ibcon#read 5, iclass 36, count 0 2006.286.04:45:29.11#ibcon#about to read 6, iclass 36, count 0 2006.286.04:45:29.11#ibcon#read 6, iclass 36, count 0 2006.286.04:45:29.11#ibcon#end of sib2, iclass 36, count 0 2006.286.04:45:29.11#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:45:29.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:45:29.11#ibcon#[27=USB\r\n] 2006.286.04:45:29.11#ibcon#*before write, iclass 36, count 0 2006.286.04:45:29.11#ibcon#enter sib2, iclass 36, count 0 2006.286.04:45:29.11#ibcon#flushed, iclass 36, count 0 2006.286.04:45:29.11#ibcon#about to write, iclass 36, count 0 2006.286.04:45:29.11#ibcon#wrote, iclass 36, count 0 2006.286.04:45:29.11#ibcon#about to read 3, iclass 36, count 0 2006.286.04:45:29.14#ibcon#read 3, iclass 36, count 0 2006.286.04:45:29.14#ibcon#about to read 4, iclass 36, count 0 2006.286.04:45:29.14#ibcon#read 4, iclass 36, count 0 2006.286.04:45:29.14#ibcon#about to read 5, iclass 36, count 0 2006.286.04:45:29.14#ibcon#read 5, iclass 36, count 0 2006.286.04:45:29.14#ibcon#about to read 6, iclass 36, count 0 2006.286.04:45:29.14#ibcon#read 6, iclass 36, count 0 2006.286.04:45:29.14#ibcon#end of sib2, iclass 36, count 0 2006.286.04:45:29.14#ibcon#*after write, iclass 36, count 0 2006.286.04:45:29.14#ibcon#*before return 0, iclass 36, count 0 2006.286.04:45:29.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:45:29.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:45:29.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:45:29.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:45:29.14$vck44/vblo=3,649.99 2006.286.04:45:29.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.04:45:29.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.04:45:29.14#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:29.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:45:29.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:45:29.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:45:29.14#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:45:29.14#ibcon#first serial, iclass 38, count 0 2006.286.04:45:29.14#ibcon#enter sib2, iclass 38, count 0 2006.286.04:45:29.14#ibcon#flushed, iclass 38, count 0 2006.286.04:45:29.14#ibcon#about to write, iclass 38, count 0 2006.286.04:45:29.14#ibcon#wrote, iclass 38, count 0 2006.286.04:45:29.14#ibcon#about to read 3, iclass 38, count 0 2006.286.04:45:29.16#ibcon#read 3, iclass 38, count 0 2006.286.04:45:29.16#ibcon#about to read 4, iclass 38, count 0 2006.286.04:45:29.16#ibcon#read 4, iclass 38, count 0 2006.286.04:45:29.16#ibcon#about to read 5, iclass 38, count 0 2006.286.04:45:29.16#ibcon#read 5, iclass 38, count 0 2006.286.04:45:29.16#ibcon#about to read 6, iclass 38, count 0 2006.286.04:45:29.16#ibcon#read 6, iclass 38, count 0 2006.286.04:45:29.16#ibcon#end of sib2, iclass 38, count 0 2006.286.04:45:29.16#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:45:29.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:45:29.16#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:45:29.16#ibcon#*before write, iclass 38, count 0 2006.286.04:45:29.16#ibcon#enter sib2, iclass 38, count 0 2006.286.04:45:29.16#ibcon#flushed, iclass 38, count 0 2006.286.04:45:29.16#ibcon#about to write, iclass 38, count 0 2006.286.04:45:29.16#ibcon#wrote, iclass 38, count 0 2006.286.04:45:29.16#ibcon#about to read 3, iclass 38, count 0 2006.286.04:45:29.20#ibcon#read 3, iclass 38, count 0 2006.286.04:45:29.20#ibcon#about to read 4, iclass 38, count 0 2006.286.04:45:29.20#ibcon#read 4, iclass 38, count 0 2006.286.04:45:29.20#ibcon#about to read 5, iclass 38, count 0 2006.286.04:45:29.20#ibcon#read 5, iclass 38, count 0 2006.286.04:45:29.20#ibcon#about to read 6, iclass 38, count 0 2006.286.04:45:29.20#ibcon#read 6, iclass 38, count 0 2006.286.04:45:29.20#ibcon#end of sib2, iclass 38, count 0 2006.286.04:45:29.20#ibcon#*after write, iclass 38, count 0 2006.286.04:45:29.20#ibcon#*before return 0, iclass 38, count 0 2006.286.04:45:29.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:45:29.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:45:29.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:45:29.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:45:29.20$vck44/vb=3,4 2006.286.04:45:29.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.04:45:29.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.04:45:29.20#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:29.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:45:29.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:45:29.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:45:29.26#ibcon#enter wrdev, iclass 40, count 2 2006.286.04:45:29.26#ibcon#first serial, iclass 40, count 2 2006.286.04:45:29.26#ibcon#enter sib2, iclass 40, count 2 2006.286.04:45:29.26#ibcon#flushed, iclass 40, count 2 2006.286.04:45:29.26#ibcon#about to write, iclass 40, count 2 2006.286.04:45:29.26#ibcon#wrote, iclass 40, count 2 2006.286.04:45:29.26#ibcon#about to read 3, iclass 40, count 2 2006.286.04:45:29.28#ibcon#read 3, iclass 40, count 2 2006.286.04:45:29.28#ibcon#about to read 4, iclass 40, count 2 2006.286.04:45:29.28#ibcon#read 4, iclass 40, count 2 2006.286.04:45:29.28#ibcon#about to read 5, iclass 40, count 2 2006.286.04:45:29.28#ibcon#read 5, iclass 40, count 2 2006.286.04:45:29.28#ibcon#about to read 6, iclass 40, count 2 2006.286.04:45:29.28#ibcon#read 6, iclass 40, count 2 2006.286.04:45:29.28#ibcon#end of sib2, iclass 40, count 2 2006.286.04:45:29.28#ibcon#*mode == 0, iclass 40, count 2 2006.286.04:45:29.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.04:45:29.28#ibcon#[27=AT03-04\r\n] 2006.286.04:45:29.28#ibcon#*before write, iclass 40, count 2 2006.286.04:45:29.28#ibcon#enter sib2, iclass 40, count 2 2006.286.04:45:29.28#ibcon#flushed, iclass 40, count 2 2006.286.04:45:29.28#ibcon#about to write, iclass 40, count 2 2006.286.04:45:29.28#ibcon#wrote, iclass 40, count 2 2006.286.04:45:29.28#ibcon#about to read 3, iclass 40, count 2 2006.286.04:45:29.31#ibcon#read 3, iclass 40, count 2 2006.286.04:45:29.31#ibcon#about to read 4, iclass 40, count 2 2006.286.04:45:29.31#ibcon#read 4, iclass 40, count 2 2006.286.04:45:29.31#ibcon#about to read 5, iclass 40, count 2 2006.286.04:45:29.31#ibcon#read 5, iclass 40, count 2 2006.286.04:45:29.31#ibcon#about to read 6, iclass 40, count 2 2006.286.04:45:29.31#ibcon#read 6, iclass 40, count 2 2006.286.04:45:29.31#ibcon#end of sib2, iclass 40, count 2 2006.286.04:45:29.31#ibcon#*after write, iclass 40, count 2 2006.286.04:45:29.31#ibcon#*before return 0, iclass 40, count 2 2006.286.04:45:29.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:45:29.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:45:29.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.04:45:29.31#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:29.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:45:29.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:45:29.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:45:29.43#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:45:29.43#ibcon#first serial, iclass 40, count 0 2006.286.04:45:29.43#ibcon#enter sib2, iclass 40, count 0 2006.286.04:45:29.43#ibcon#flushed, iclass 40, count 0 2006.286.04:45:29.43#ibcon#about to write, iclass 40, count 0 2006.286.04:45:29.43#ibcon#wrote, iclass 40, count 0 2006.286.04:45:29.43#ibcon#about to read 3, iclass 40, count 0 2006.286.04:45:29.45#ibcon#read 3, iclass 40, count 0 2006.286.04:45:29.45#ibcon#about to read 4, iclass 40, count 0 2006.286.04:45:29.45#ibcon#read 4, iclass 40, count 0 2006.286.04:45:29.45#ibcon#about to read 5, iclass 40, count 0 2006.286.04:45:29.45#ibcon#read 5, iclass 40, count 0 2006.286.04:45:29.45#ibcon#about to read 6, iclass 40, count 0 2006.286.04:45:29.45#ibcon#read 6, iclass 40, count 0 2006.286.04:45:29.45#ibcon#end of sib2, iclass 40, count 0 2006.286.04:45:29.45#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:45:29.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:45:29.45#ibcon#[27=USB\r\n] 2006.286.04:45:29.45#ibcon#*before write, iclass 40, count 0 2006.286.04:45:29.45#ibcon#enter sib2, iclass 40, count 0 2006.286.04:45:29.45#ibcon#flushed, iclass 40, count 0 2006.286.04:45:29.45#ibcon#about to write, iclass 40, count 0 2006.286.04:45:29.45#ibcon#wrote, iclass 40, count 0 2006.286.04:45:29.45#ibcon#about to read 3, iclass 40, count 0 2006.286.04:45:29.48#ibcon#read 3, iclass 40, count 0 2006.286.04:45:29.48#ibcon#about to read 4, iclass 40, count 0 2006.286.04:45:29.48#ibcon#read 4, iclass 40, count 0 2006.286.04:45:29.48#ibcon#about to read 5, iclass 40, count 0 2006.286.04:45:29.48#ibcon#read 5, iclass 40, count 0 2006.286.04:45:29.48#ibcon#about to read 6, iclass 40, count 0 2006.286.04:45:29.48#ibcon#read 6, iclass 40, count 0 2006.286.04:45:29.48#ibcon#end of sib2, iclass 40, count 0 2006.286.04:45:29.48#ibcon#*after write, iclass 40, count 0 2006.286.04:45:29.48#ibcon#*before return 0, iclass 40, count 0 2006.286.04:45:29.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:45:29.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:45:29.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:45:29.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:45:29.48$vck44/vblo=4,679.99 2006.286.04:45:29.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.04:45:29.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.04:45:29.48#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:29.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:45:29.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:45:29.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:45:29.48#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:45:29.48#ibcon#first serial, iclass 4, count 0 2006.286.04:45:29.48#ibcon#enter sib2, iclass 4, count 0 2006.286.04:45:29.48#ibcon#flushed, iclass 4, count 0 2006.286.04:45:29.48#ibcon#about to write, iclass 4, count 0 2006.286.04:45:29.48#ibcon#wrote, iclass 4, count 0 2006.286.04:45:29.48#ibcon#about to read 3, iclass 4, count 0 2006.286.04:45:29.50#ibcon#read 3, iclass 4, count 0 2006.286.04:45:29.50#ibcon#about to read 4, iclass 4, count 0 2006.286.04:45:29.50#ibcon#read 4, iclass 4, count 0 2006.286.04:45:29.50#ibcon#about to read 5, iclass 4, count 0 2006.286.04:45:29.50#ibcon#read 5, iclass 4, count 0 2006.286.04:45:29.50#ibcon#about to read 6, iclass 4, count 0 2006.286.04:45:29.50#ibcon#read 6, iclass 4, count 0 2006.286.04:45:29.50#ibcon#end of sib2, iclass 4, count 0 2006.286.04:45:29.50#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:45:29.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:45:29.50#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:45:29.50#ibcon#*before write, iclass 4, count 0 2006.286.04:45:29.50#ibcon#enter sib2, iclass 4, count 0 2006.286.04:45:29.50#ibcon#flushed, iclass 4, count 0 2006.286.04:45:29.50#ibcon#about to write, iclass 4, count 0 2006.286.04:45:29.50#ibcon#wrote, iclass 4, count 0 2006.286.04:45:29.50#ibcon#about to read 3, iclass 4, count 0 2006.286.04:45:29.54#ibcon#read 3, iclass 4, count 0 2006.286.04:45:29.54#ibcon#about to read 4, iclass 4, count 0 2006.286.04:45:29.54#ibcon#read 4, iclass 4, count 0 2006.286.04:45:29.54#ibcon#about to read 5, iclass 4, count 0 2006.286.04:45:29.54#ibcon#read 5, iclass 4, count 0 2006.286.04:45:29.54#ibcon#about to read 6, iclass 4, count 0 2006.286.04:45:29.54#ibcon#read 6, iclass 4, count 0 2006.286.04:45:29.54#ibcon#end of sib2, iclass 4, count 0 2006.286.04:45:29.54#ibcon#*after write, iclass 4, count 0 2006.286.04:45:29.54#ibcon#*before return 0, iclass 4, count 0 2006.286.04:45:29.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:45:29.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:45:29.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:45:29.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:45:29.54$vck44/vb=4,5 2006.286.04:45:29.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.04:45:29.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.04:45:29.54#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:29.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:45:29.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:45:29.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:45:29.60#ibcon#enter wrdev, iclass 6, count 2 2006.286.04:45:29.60#ibcon#first serial, iclass 6, count 2 2006.286.04:45:29.60#ibcon#enter sib2, iclass 6, count 2 2006.286.04:45:29.60#ibcon#flushed, iclass 6, count 2 2006.286.04:45:29.60#ibcon#about to write, iclass 6, count 2 2006.286.04:45:29.60#ibcon#wrote, iclass 6, count 2 2006.286.04:45:29.60#ibcon#about to read 3, iclass 6, count 2 2006.286.04:45:29.62#ibcon#read 3, iclass 6, count 2 2006.286.04:45:29.62#ibcon#about to read 4, iclass 6, count 2 2006.286.04:45:29.62#ibcon#read 4, iclass 6, count 2 2006.286.04:45:29.62#ibcon#about to read 5, iclass 6, count 2 2006.286.04:45:29.62#ibcon#read 5, iclass 6, count 2 2006.286.04:45:29.62#ibcon#about to read 6, iclass 6, count 2 2006.286.04:45:29.62#ibcon#read 6, iclass 6, count 2 2006.286.04:45:29.62#ibcon#end of sib2, iclass 6, count 2 2006.286.04:45:29.62#ibcon#*mode == 0, iclass 6, count 2 2006.286.04:45:29.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.04:45:29.62#ibcon#[27=AT04-05\r\n] 2006.286.04:45:29.62#ibcon#*before write, iclass 6, count 2 2006.286.04:45:29.62#ibcon#enter sib2, iclass 6, count 2 2006.286.04:45:29.62#ibcon#flushed, iclass 6, count 2 2006.286.04:45:29.62#ibcon#about to write, iclass 6, count 2 2006.286.04:45:29.62#ibcon#wrote, iclass 6, count 2 2006.286.04:45:29.62#ibcon#about to read 3, iclass 6, count 2 2006.286.04:45:29.65#ibcon#read 3, iclass 6, count 2 2006.286.04:45:29.65#ibcon#about to read 4, iclass 6, count 2 2006.286.04:45:29.65#ibcon#read 4, iclass 6, count 2 2006.286.04:45:29.65#ibcon#about to read 5, iclass 6, count 2 2006.286.04:45:29.65#ibcon#read 5, iclass 6, count 2 2006.286.04:45:29.65#ibcon#about to read 6, iclass 6, count 2 2006.286.04:45:29.65#ibcon#read 6, iclass 6, count 2 2006.286.04:45:29.65#ibcon#end of sib2, iclass 6, count 2 2006.286.04:45:29.65#ibcon#*after write, iclass 6, count 2 2006.286.04:45:29.65#ibcon#*before return 0, iclass 6, count 2 2006.286.04:45:29.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:45:29.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:45:29.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.04:45:29.65#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:29.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:45:29.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:45:29.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:45:29.77#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:45:29.77#ibcon#first serial, iclass 6, count 0 2006.286.04:45:29.77#ibcon#enter sib2, iclass 6, count 0 2006.286.04:45:29.77#ibcon#flushed, iclass 6, count 0 2006.286.04:45:29.77#ibcon#about to write, iclass 6, count 0 2006.286.04:45:29.77#ibcon#wrote, iclass 6, count 0 2006.286.04:45:29.77#ibcon#about to read 3, iclass 6, count 0 2006.286.04:45:29.79#ibcon#read 3, iclass 6, count 0 2006.286.04:45:29.79#ibcon#about to read 4, iclass 6, count 0 2006.286.04:45:29.79#ibcon#read 4, iclass 6, count 0 2006.286.04:45:29.79#ibcon#about to read 5, iclass 6, count 0 2006.286.04:45:29.79#ibcon#read 5, iclass 6, count 0 2006.286.04:45:29.79#ibcon#about to read 6, iclass 6, count 0 2006.286.04:45:29.79#ibcon#read 6, iclass 6, count 0 2006.286.04:45:29.79#ibcon#end of sib2, iclass 6, count 0 2006.286.04:45:29.79#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:45:29.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:45:29.79#ibcon#[27=USB\r\n] 2006.286.04:45:29.79#ibcon#*before write, iclass 6, count 0 2006.286.04:45:29.79#ibcon#enter sib2, iclass 6, count 0 2006.286.04:45:29.79#ibcon#flushed, iclass 6, count 0 2006.286.04:45:29.79#ibcon#about to write, iclass 6, count 0 2006.286.04:45:29.79#ibcon#wrote, iclass 6, count 0 2006.286.04:45:29.79#ibcon#about to read 3, iclass 6, count 0 2006.286.04:45:29.82#ibcon#read 3, iclass 6, count 0 2006.286.04:45:29.82#ibcon#about to read 4, iclass 6, count 0 2006.286.04:45:29.82#ibcon#read 4, iclass 6, count 0 2006.286.04:45:29.82#ibcon#about to read 5, iclass 6, count 0 2006.286.04:45:29.82#ibcon#read 5, iclass 6, count 0 2006.286.04:45:29.82#ibcon#about to read 6, iclass 6, count 0 2006.286.04:45:29.82#ibcon#read 6, iclass 6, count 0 2006.286.04:45:29.82#ibcon#end of sib2, iclass 6, count 0 2006.286.04:45:29.82#ibcon#*after write, iclass 6, count 0 2006.286.04:45:29.82#ibcon#*before return 0, iclass 6, count 0 2006.286.04:45:29.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:45:29.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:45:29.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:45:29.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:45:29.82$vck44/vblo=5,709.99 2006.286.04:45:29.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.04:45:29.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.04:45:29.82#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:29.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:45:29.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:45:29.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:45:29.82#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:45:29.82#ibcon#first serial, iclass 10, count 0 2006.286.04:45:29.82#ibcon#enter sib2, iclass 10, count 0 2006.286.04:45:29.82#ibcon#flushed, iclass 10, count 0 2006.286.04:45:29.82#ibcon#about to write, iclass 10, count 0 2006.286.04:45:29.82#ibcon#wrote, iclass 10, count 0 2006.286.04:45:29.82#ibcon#about to read 3, iclass 10, count 0 2006.286.04:45:29.84#ibcon#read 3, iclass 10, count 0 2006.286.04:45:29.84#ibcon#about to read 4, iclass 10, count 0 2006.286.04:45:29.84#ibcon#read 4, iclass 10, count 0 2006.286.04:45:29.84#ibcon#about to read 5, iclass 10, count 0 2006.286.04:45:29.84#ibcon#read 5, iclass 10, count 0 2006.286.04:45:29.84#ibcon#about to read 6, iclass 10, count 0 2006.286.04:45:29.84#ibcon#read 6, iclass 10, count 0 2006.286.04:45:29.84#ibcon#end of sib2, iclass 10, count 0 2006.286.04:45:29.84#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:45:29.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:45:29.84#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:45:29.84#ibcon#*before write, iclass 10, count 0 2006.286.04:45:29.84#ibcon#enter sib2, iclass 10, count 0 2006.286.04:45:29.84#ibcon#flushed, iclass 10, count 0 2006.286.04:45:29.84#ibcon#about to write, iclass 10, count 0 2006.286.04:45:29.84#ibcon#wrote, iclass 10, count 0 2006.286.04:45:29.84#ibcon#about to read 3, iclass 10, count 0 2006.286.04:45:29.88#ibcon#read 3, iclass 10, count 0 2006.286.04:45:29.88#ibcon#about to read 4, iclass 10, count 0 2006.286.04:45:29.88#ibcon#read 4, iclass 10, count 0 2006.286.04:45:29.88#ibcon#about to read 5, iclass 10, count 0 2006.286.04:45:29.88#ibcon#read 5, iclass 10, count 0 2006.286.04:45:29.88#ibcon#about to read 6, iclass 10, count 0 2006.286.04:45:29.88#ibcon#read 6, iclass 10, count 0 2006.286.04:45:29.88#ibcon#end of sib2, iclass 10, count 0 2006.286.04:45:29.88#ibcon#*after write, iclass 10, count 0 2006.286.04:45:29.88#ibcon#*before return 0, iclass 10, count 0 2006.286.04:45:29.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:45:29.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:45:29.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:45:29.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:45:29.88$vck44/vb=5,4 2006.286.04:45:29.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.04:45:29.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.04:45:29.88#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:29.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:45:29.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:45:29.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:45:29.94#ibcon#enter wrdev, iclass 12, count 2 2006.286.04:45:29.94#ibcon#first serial, iclass 12, count 2 2006.286.04:45:29.94#ibcon#enter sib2, iclass 12, count 2 2006.286.04:45:29.94#ibcon#flushed, iclass 12, count 2 2006.286.04:45:29.94#ibcon#about to write, iclass 12, count 2 2006.286.04:45:29.94#ibcon#wrote, iclass 12, count 2 2006.286.04:45:29.94#ibcon#about to read 3, iclass 12, count 2 2006.286.04:45:29.96#ibcon#read 3, iclass 12, count 2 2006.286.04:45:30.26#ibcon#about to read 4, iclass 12, count 2 2006.286.04:45:30.26#ibcon#read 4, iclass 12, count 2 2006.286.04:45:30.26#ibcon#about to read 5, iclass 12, count 2 2006.286.04:45:30.26#ibcon#read 5, iclass 12, count 2 2006.286.04:45:30.26#ibcon#about to read 6, iclass 12, count 2 2006.286.04:45:30.26#ibcon#read 6, iclass 12, count 2 2006.286.04:45:30.26#ibcon#end of sib2, iclass 12, count 2 2006.286.04:45:30.26#ibcon#*mode == 0, iclass 12, count 2 2006.286.04:45:30.26#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.04:45:30.26#ibcon#[27=AT05-04\r\n] 2006.286.04:45:30.26#ibcon#*before write, iclass 12, count 2 2006.286.04:45:30.26#ibcon#enter sib2, iclass 12, count 2 2006.286.04:45:30.26#ibcon#flushed, iclass 12, count 2 2006.286.04:45:30.26#ibcon#about to write, iclass 12, count 2 2006.286.04:45:30.26#ibcon#wrote, iclass 12, count 2 2006.286.04:45:30.26#ibcon#about to read 3, iclass 12, count 2 2006.286.04:45:30.29#ibcon#read 3, iclass 12, count 2 2006.286.04:45:30.29#ibcon#about to read 4, iclass 12, count 2 2006.286.04:45:30.29#ibcon#read 4, iclass 12, count 2 2006.286.04:45:30.29#ibcon#about to read 5, iclass 12, count 2 2006.286.04:45:30.29#ibcon#read 5, iclass 12, count 2 2006.286.04:45:30.29#ibcon#about to read 6, iclass 12, count 2 2006.286.04:45:30.29#ibcon#read 6, iclass 12, count 2 2006.286.04:45:30.29#ibcon#end of sib2, iclass 12, count 2 2006.286.04:45:30.29#ibcon#*after write, iclass 12, count 2 2006.286.04:45:30.29#ibcon#*before return 0, iclass 12, count 2 2006.286.04:45:30.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:45:30.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:45:30.29#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.04:45:30.29#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:30.29#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:45:30.41#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:45:30.41#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:45:30.41#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:45:30.41#ibcon#first serial, iclass 12, count 0 2006.286.04:45:30.41#ibcon#enter sib2, iclass 12, count 0 2006.286.04:45:30.41#ibcon#flushed, iclass 12, count 0 2006.286.04:45:30.41#ibcon#about to write, iclass 12, count 0 2006.286.04:45:30.41#ibcon#wrote, iclass 12, count 0 2006.286.04:45:30.41#ibcon#about to read 3, iclass 12, count 0 2006.286.04:45:30.43#ibcon#read 3, iclass 12, count 0 2006.286.04:45:30.43#ibcon#about to read 4, iclass 12, count 0 2006.286.04:45:30.43#ibcon#read 4, iclass 12, count 0 2006.286.04:45:30.43#ibcon#about to read 5, iclass 12, count 0 2006.286.04:45:30.43#ibcon#read 5, iclass 12, count 0 2006.286.04:45:30.43#ibcon#about to read 6, iclass 12, count 0 2006.286.04:45:30.43#ibcon#read 6, iclass 12, count 0 2006.286.04:45:30.43#ibcon#end of sib2, iclass 12, count 0 2006.286.04:45:30.43#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:45:30.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:45:30.43#ibcon#[27=USB\r\n] 2006.286.04:45:30.43#ibcon#*before write, iclass 12, count 0 2006.286.04:45:30.43#ibcon#enter sib2, iclass 12, count 0 2006.286.04:45:30.43#ibcon#flushed, iclass 12, count 0 2006.286.04:45:30.43#ibcon#about to write, iclass 12, count 0 2006.286.04:45:30.43#ibcon#wrote, iclass 12, count 0 2006.286.04:45:30.43#ibcon#about to read 3, iclass 12, count 0 2006.286.04:45:30.46#ibcon#read 3, iclass 12, count 0 2006.286.04:45:30.46#ibcon#about to read 4, iclass 12, count 0 2006.286.04:45:30.46#ibcon#read 4, iclass 12, count 0 2006.286.04:45:30.46#ibcon#about to read 5, iclass 12, count 0 2006.286.04:45:30.46#ibcon#read 5, iclass 12, count 0 2006.286.04:45:30.46#ibcon#about to read 6, iclass 12, count 0 2006.286.04:45:30.46#ibcon#read 6, iclass 12, count 0 2006.286.04:45:30.46#ibcon#end of sib2, iclass 12, count 0 2006.286.04:45:30.46#ibcon#*after write, iclass 12, count 0 2006.286.04:45:30.46#ibcon#*before return 0, iclass 12, count 0 2006.286.04:45:30.46#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:45:30.46#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:45:30.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:45:30.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:45:30.46$vck44/vblo=6,719.99 2006.286.04:45:30.46#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.04:45:30.46#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.04:45:30.46#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:30.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:45:30.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:45:30.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:45:30.46#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:45:30.46#ibcon#first serial, iclass 14, count 0 2006.286.04:45:30.46#ibcon#enter sib2, iclass 14, count 0 2006.286.04:45:30.46#ibcon#flushed, iclass 14, count 0 2006.286.04:45:30.46#ibcon#about to write, iclass 14, count 0 2006.286.04:45:30.46#ibcon#wrote, iclass 14, count 0 2006.286.04:45:30.46#ibcon#about to read 3, iclass 14, count 0 2006.286.04:45:30.48#ibcon#read 3, iclass 14, count 0 2006.286.04:45:30.48#ibcon#about to read 4, iclass 14, count 0 2006.286.04:45:30.48#ibcon#read 4, iclass 14, count 0 2006.286.04:45:30.48#ibcon#about to read 5, iclass 14, count 0 2006.286.04:45:30.48#ibcon#read 5, iclass 14, count 0 2006.286.04:45:30.48#ibcon#about to read 6, iclass 14, count 0 2006.286.04:45:30.48#ibcon#read 6, iclass 14, count 0 2006.286.04:45:30.48#ibcon#end of sib2, iclass 14, count 0 2006.286.04:45:30.48#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:45:30.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:45:30.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:45:30.48#ibcon#*before write, iclass 14, count 0 2006.286.04:45:30.48#ibcon#enter sib2, iclass 14, count 0 2006.286.04:45:30.48#ibcon#flushed, iclass 14, count 0 2006.286.04:45:30.48#ibcon#about to write, iclass 14, count 0 2006.286.04:45:30.48#ibcon#wrote, iclass 14, count 0 2006.286.04:45:30.48#ibcon#about to read 3, iclass 14, count 0 2006.286.04:45:30.52#ibcon#read 3, iclass 14, count 0 2006.286.04:45:30.52#ibcon#about to read 4, iclass 14, count 0 2006.286.04:45:30.52#ibcon#read 4, iclass 14, count 0 2006.286.04:45:30.52#ibcon#about to read 5, iclass 14, count 0 2006.286.04:45:30.52#ibcon#read 5, iclass 14, count 0 2006.286.04:45:30.52#ibcon#about to read 6, iclass 14, count 0 2006.286.04:45:30.52#ibcon#read 6, iclass 14, count 0 2006.286.04:45:30.52#ibcon#end of sib2, iclass 14, count 0 2006.286.04:45:30.52#ibcon#*after write, iclass 14, count 0 2006.286.04:45:30.52#ibcon#*before return 0, iclass 14, count 0 2006.286.04:45:30.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:45:30.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:45:30.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:45:30.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:45:30.52$vck44/vb=6,3 2006.286.04:45:30.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.04:45:30.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.04:45:30.52#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:30.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:45:30.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:45:30.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:45:30.58#ibcon#enter wrdev, iclass 16, count 2 2006.286.04:45:30.58#ibcon#first serial, iclass 16, count 2 2006.286.04:45:30.58#ibcon#enter sib2, iclass 16, count 2 2006.286.04:45:30.58#ibcon#flushed, iclass 16, count 2 2006.286.04:45:30.58#ibcon#about to write, iclass 16, count 2 2006.286.04:45:30.58#ibcon#wrote, iclass 16, count 2 2006.286.04:45:30.58#ibcon#about to read 3, iclass 16, count 2 2006.286.04:45:30.60#ibcon#read 3, iclass 16, count 2 2006.286.04:45:30.60#ibcon#about to read 4, iclass 16, count 2 2006.286.04:45:30.60#ibcon#read 4, iclass 16, count 2 2006.286.04:45:30.60#ibcon#about to read 5, iclass 16, count 2 2006.286.04:45:30.60#ibcon#read 5, iclass 16, count 2 2006.286.04:45:30.60#ibcon#about to read 6, iclass 16, count 2 2006.286.04:45:30.60#ibcon#read 6, iclass 16, count 2 2006.286.04:45:30.60#ibcon#end of sib2, iclass 16, count 2 2006.286.04:45:30.60#ibcon#*mode == 0, iclass 16, count 2 2006.286.04:45:30.60#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.04:45:30.60#ibcon#[27=AT06-03\r\n] 2006.286.04:45:30.60#ibcon#*before write, iclass 16, count 2 2006.286.04:45:30.60#ibcon#enter sib2, iclass 16, count 2 2006.286.04:45:30.60#ibcon#flushed, iclass 16, count 2 2006.286.04:45:30.60#ibcon#about to write, iclass 16, count 2 2006.286.04:45:30.60#ibcon#wrote, iclass 16, count 2 2006.286.04:45:30.60#ibcon#about to read 3, iclass 16, count 2 2006.286.04:45:30.63#ibcon#read 3, iclass 16, count 2 2006.286.04:45:30.63#ibcon#about to read 4, iclass 16, count 2 2006.286.04:45:30.63#ibcon#read 4, iclass 16, count 2 2006.286.04:45:30.63#ibcon#about to read 5, iclass 16, count 2 2006.286.04:45:30.63#ibcon#read 5, iclass 16, count 2 2006.286.04:45:30.63#ibcon#about to read 6, iclass 16, count 2 2006.286.04:45:30.63#ibcon#read 6, iclass 16, count 2 2006.286.04:45:30.63#ibcon#end of sib2, iclass 16, count 2 2006.286.04:45:30.63#ibcon#*after write, iclass 16, count 2 2006.286.04:45:30.63#ibcon#*before return 0, iclass 16, count 2 2006.286.04:45:30.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:45:30.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:45:30.63#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.04:45:30.63#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:30.63#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:45:30.75#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:45:30.75#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:45:30.75#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:45:30.75#ibcon#first serial, iclass 16, count 0 2006.286.04:45:30.75#ibcon#enter sib2, iclass 16, count 0 2006.286.04:45:30.75#ibcon#flushed, iclass 16, count 0 2006.286.04:45:30.75#ibcon#about to write, iclass 16, count 0 2006.286.04:45:30.75#ibcon#wrote, iclass 16, count 0 2006.286.04:45:30.75#ibcon#about to read 3, iclass 16, count 0 2006.286.04:45:30.77#ibcon#read 3, iclass 16, count 0 2006.286.04:45:30.77#ibcon#about to read 4, iclass 16, count 0 2006.286.04:45:30.77#ibcon#read 4, iclass 16, count 0 2006.286.04:45:30.77#ibcon#about to read 5, iclass 16, count 0 2006.286.04:45:30.77#ibcon#read 5, iclass 16, count 0 2006.286.04:45:30.77#ibcon#about to read 6, iclass 16, count 0 2006.286.04:45:30.77#ibcon#read 6, iclass 16, count 0 2006.286.04:45:30.77#ibcon#end of sib2, iclass 16, count 0 2006.286.04:45:30.77#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:45:30.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:45:30.77#ibcon#[27=USB\r\n] 2006.286.04:45:30.77#ibcon#*before write, iclass 16, count 0 2006.286.04:45:30.77#ibcon#enter sib2, iclass 16, count 0 2006.286.04:45:30.77#ibcon#flushed, iclass 16, count 0 2006.286.04:45:30.77#ibcon#about to write, iclass 16, count 0 2006.286.04:45:30.77#ibcon#wrote, iclass 16, count 0 2006.286.04:45:30.77#ibcon#about to read 3, iclass 16, count 0 2006.286.04:45:30.80#ibcon#read 3, iclass 16, count 0 2006.286.04:45:30.80#ibcon#about to read 4, iclass 16, count 0 2006.286.04:45:30.80#ibcon#read 4, iclass 16, count 0 2006.286.04:45:30.80#ibcon#about to read 5, iclass 16, count 0 2006.286.04:45:30.80#ibcon#read 5, iclass 16, count 0 2006.286.04:45:30.80#ibcon#about to read 6, iclass 16, count 0 2006.286.04:45:30.80#ibcon#read 6, iclass 16, count 0 2006.286.04:45:30.80#ibcon#end of sib2, iclass 16, count 0 2006.286.04:45:30.80#ibcon#*after write, iclass 16, count 0 2006.286.04:45:30.80#ibcon#*before return 0, iclass 16, count 0 2006.286.04:45:30.80#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:45:30.80#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:45:30.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:45:30.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:45:30.80$vck44/vblo=7,734.99 2006.286.04:45:30.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.04:45:30.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.04:45:30.80#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:30.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:45:30.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:45:30.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:45:30.80#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:45:30.80#ibcon#first serial, iclass 18, count 0 2006.286.04:45:30.80#ibcon#enter sib2, iclass 18, count 0 2006.286.04:45:30.80#ibcon#flushed, iclass 18, count 0 2006.286.04:45:30.80#ibcon#about to write, iclass 18, count 0 2006.286.04:45:30.80#ibcon#wrote, iclass 18, count 0 2006.286.04:45:30.80#ibcon#about to read 3, iclass 18, count 0 2006.286.04:45:30.82#ibcon#read 3, iclass 18, count 0 2006.286.04:45:30.82#ibcon#about to read 4, iclass 18, count 0 2006.286.04:45:30.82#ibcon#read 4, iclass 18, count 0 2006.286.04:45:30.82#ibcon#about to read 5, iclass 18, count 0 2006.286.04:45:30.82#ibcon#read 5, iclass 18, count 0 2006.286.04:45:30.82#ibcon#about to read 6, iclass 18, count 0 2006.286.04:45:30.82#ibcon#read 6, iclass 18, count 0 2006.286.04:45:30.82#ibcon#end of sib2, iclass 18, count 0 2006.286.04:45:30.82#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:45:30.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:45:30.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:45:30.82#ibcon#*before write, iclass 18, count 0 2006.286.04:45:30.82#ibcon#enter sib2, iclass 18, count 0 2006.286.04:45:30.82#ibcon#flushed, iclass 18, count 0 2006.286.04:45:30.82#ibcon#about to write, iclass 18, count 0 2006.286.04:45:30.82#ibcon#wrote, iclass 18, count 0 2006.286.04:45:30.82#ibcon#about to read 3, iclass 18, count 0 2006.286.04:45:30.86#ibcon#read 3, iclass 18, count 0 2006.286.04:45:30.86#ibcon#about to read 4, iclass 18, count 0 2006.286.04:45:30.86#ibcon#read 4, iclass 18, count 0 2006.286.04:45:30.86#ibcon#about to read 5, iclass 18, count 0 2006.286.04:45:30.86#ibcon#read 5, iclass 18, count 0 2006.286.04:45:30.86#ibcon#about to read 6, iclass 18, count 0 2006.286.04:45:30.86#ibcon#read 6, iclass 18, count 0 2006.286.04:45:30.86#ibcon#end of sib2, iclass 18, count 0 2006.286.04:45:30.86#ibcon#*after write, iclass 18, count 0 2006.286.04:45:30.86#ibcon#*before return 0, iclass 18, count 0 2006.286.04:45:30.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:45:30.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:45:30.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:45:30.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:45:30.86$vck44/vb=7,4 2006.286.04:45:30.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.04:45:30.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.04:45:30.86#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:30.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:45:30.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:45:30.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:45:30.92#ibcon#enter wrdev, iclass 20, count 2 2006.286.04:45:30.92#ibcon#first serial, iclass 20, count 2 2006.286.04:45:30.92#ibcon#enter sib2, iclass 20, count 2 2006.286.04:45:30.92#ibcon#flushed, iclass 20, count 2 2006.286.04:45:30.92#ibcon#about to write, iclass 20, count 2 2006.286.04:45:30.92#ibcon#wrote, iclass 20, count 2 2006.286.04:45:30.92#ibcon#about to read 3, iclass 20, count 2 2006.286.04:45:30.94#ibcon#read 3, iclass 20, count 2 2006.286.04:45:30.94#ibcon#about to read 4, iclass 20, count 2 2006.286.04:45:30.94#ibcon#read 4, iclass 20, count 2 2006.286.04:45:30.94#ibcon#about to read 5, iclass 20, count 2 2006.286.04:45:30.94#ibcon#read 5, iclass 20, count 2 2006.286.04:45:30.94#ibcon#about to read 6, iclass 20, count 2 2006.286.04:45:30.94#ibcon#read 6, iclass 20, count 2 2006.286.04:45:30.94#ibcon#end of sib2, iclass 20, count 2 2006.286.04:45:30.94#ibcon#*mode == 0, iclass 20, count 2 2006.286.04:45:30.94#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.04:45:30.94#ibcon#[27=AT07-04\r\n] 2006.286.04:45:30.94#ibcon#*before write, iclass 20, count 2 2006.286.04:45:30.94#ibcon#enter sib2, iclass 20, count 2 2006.286.04:45:30.94#ibcon#flushed, iclass 20, count 2 2006.286.04:45:30.94#ibcon#about to write, iclass 20, count 2 2006.286.04:45:30.94#ibcon#wrote, iclass 20, count 2 2006.286.04:45:30.94#ibcon#about to read 3, iclass 20, count 2 2006.286.04:45:30.97#ibcon#read 3, iclass 20, count 2 2006.286.04:45:30.97#ibcon#about to read 4, iclass 20, count 2 2006.286.04:45:31.03#ibcon#read 4, iclass 20, count 2 2006.286.04:45:31.03#ibcon#about to read 5, iclass 20, count 2 2006.286.04:45:31.03#ibcon#read 5, iclass 20, count 2 2006.286.04:45:31.03#ibcon#about to read 6, iclass 20, count 2 2006.286.04:45:31.03#ibcon#read 6, iclass 20, count 2 2006.286.04:45:31.03#ibcon#end of sib2, iclass 20, count 2 2006.286.04:45:31.03#ibcon#*after write, iclass 20, count 2 2006.286.04:45:31.03#ibcon#*before return 0, iclass 20, count 2 2006.286.04:45:31.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:45:31.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:45:31.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.04:45:31.03#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:31.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:45:31.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:45:31.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:45:31.14#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:45:31.14#ibcon#first serial, iclass 20, count 0 2006.286.04:45:31.14#ibcon#enter sib2, iclass 20, count 0 2006.286.04:45:31.14#ibcon#flushed, iclass 20, count 0 2006.286.04:45:31.14#ibcon#about to write, iclass 20, count 0 2006.286.04:45:31.14#ibcon#wrote, iclass 20, count 0 2006.286.04:45:31.14#ibcon#about to read 3, iclass 20, count 0 2006.286.04:45:31.16#ibcon#read 3, iclass 20, count 0 2006.286.04:45:31.16#ibcon#about to read 4, iclass 20, count 0 2006.286.04:45:31.16#ibcon#read 4, iclass 20, count 0 2006.286.04:45:31.16#ibcon#about to read 5, iclass 20, count 0 2006.286.04:45:31.16#ibcon#read 5, iclass 20, count 0 2006.286.04:45:31.16#ibcon#about to read 6, iclass 20, count 0 2006.286.04:45:31.16#ibcon#read 6, iclass 20, count 0 2006.286.04:45:31.16#ibcon#end of sib2, iclass 20, count 0 2006.286.04:45:31.16#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:45:31.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:45:31.16#ibcon#[27=USB\r\n] 2006.286.04:45:31.16#ibcon#*before write, iclass 20, count 0 2006.286.04:45:31.16#ibcon#enter sib2, iclass 20, count 0 2006.286.04:45:31.16#ibcon#flushed, iclass 20, count 0 2006.286.04:45:31.16#ibcon#about to write, iclass 20, count 0 2006.286.04:45:31.16#ibcon#wrote, iclass 20, count 0 2006.286.04:45:31.16#ibcon#about to read 3, iclass 20, count 0 2006.286.04:45:31.19#ibcon#read 3, iclass 20, count 0 2006.286.04:45:31.19#ibcon#about to read 4, iclass 20, count 0 2006.286.04:45:31.19#ibcon#read 4, iclass 20, count 0 2006.286.04:45:31.19#ibcon#about to read 5, iclass 20, count 0 2006.286.04:45:31.19#ibcon#read 5, iclass 20, count 0 2006.286.04:45:31.19#ibcon#about to read 6, iclass 20, count 0 2006.286.04:45:31.19#ibcon#read 6, iclass 20, count 0 2006.286.04:45:31.19#ibcon#end of sib2, iclass 20, count 0 2006.286.04:45:31.19#ibcon#*after write, iclass 20, count 0 2006.286.04:45:31.19#ibcon#*before return 0, iclass 20, count 0 2006.286.04:45:31.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:45:31.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:45:31.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:45:31.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:45:31.19$vck44/vblo=8,744.99 2006.286.04:45:31.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:45:31.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:45:31.19#ibcon#ireg 17 cls_cnt 0 2006.286.04:45:31.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:45:31.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:45:31.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:45:31.19#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:45:31.19#ibcon#first serial, iclass 22, count 0 2006.286.04:45:31.19#ibcon#enter sib2, iclass 22, count 0 2006.286.04:45:31.19#ibcon#flushed, iclass 22, count 0 2006.286.04:45:31.19#ibcon#about to write, iclass 22, count 0 2006.286.04:45:31.19#ibcon#wrote, iclass 22, count 0 2006.286.04:45:31.19#ibcon#about to read 3, iclass 22, count 0 2006.286.04:45:31.21#ibcon#read 3, iclass 22, count 0 2006.286.04:45:31.21#ibcon#about to read 4, iclass 22, count 0 2006.286.04:45:31.21#ibcon#read 4, iclass 22, count 0 2006.286.04:45:31.21#ibcon#about to read 5, iclass 22, count 0 2006.286.04:45:31.21#ibcon#read 5, iclass 22, count 0 2006.286.04:45:31.21#ibcon#about to read 6, iclass 22, count 0 2006.286.04:45:31.21#ibcon#read 6, iclass 22, count 0 2006.286.04:45:31.21#ibcon#end of sib2, iclass 22, count 0 2006.286.04:45:31.21#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:45:31.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:45:31.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:45:31.21#ibcon#*before write, iclass 22, count 0 2006.286.04:45:31.21#ibcon#enter sib2, iclass 22, count 0 2006.286.04:45:31.21#ibcon#flushed, iclass 22, count 0 2006.286.04:45:31.21#ibcon#about to write, iclass 22, count 0 2006.286.04:45:31.21#ibcon#wrote, iclass 22, count 0 2006.286.04:45:31.21#ibcon#about to read 3, iclass 22, count 0 2006.286.04:45:31.25#ibcon#read 3, iclass 22, count 0 2006.286.04:45:31.25#ibcon#about to read 4, iclass 22, count 0 2006.286.04:45:31.25#ibcon#read 4, iclass 22, count 0 2006.286.04:45:31.25#ibcon#about to read 5, iclass 22, count 0 2006.286.04:45:31.25#ibcon#read 5, iclass 22, count 0 2006.286.04:45:31.25#ibcon#about to read 6, iclass 22, count 0 2006.286.04:45:31.25#ibcon#read 6, iclass 22, count 0 2006.286.04:45:31.25#ibcon#end of sib2, iclass 22, count 0 2006.286.04:45:31.25#ibcon#*after write, iclass 22, count 0 2006.286.04:45:31.25#ibcon#*before return 0, iclass 22, count 0 2006.286.04:45:31.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:45:31.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:45:31.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:45:31.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:45:31.25$vck44/vb=8,4 2006.286.04:45:31.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.04:45:31.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.04:45:31.25#ibcon#ireg 11 cls_cnt 2 2006.286.04:45:31.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:45:31.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:45:31.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:45:31.31#ibcon#enter wrdev, iclass 24, count 2 2006.286.04:45:31.31#ibcon#first serial, iclass 24, count 2 2006.286.04:45:31.31#ibcon#enter sib2, iclass 24, count 2 2006.286.04:45:31.31#ibcon#flushed, iclass 24, count 2 2006.286.04:45:31.31#ibcon#about to write, iclass 24, count 2 2006.286.04:45:31.31#ibcon#wrote, iclass 24, count 2 2006.286.04:45:31.31#ibcon#about to read 3, iclass 24, count 2 2006.286.04:45:31.33#ibcon#read 3, iclass 24, count 2 2006.286.04:45:31.33#ibcon#about to read 4, iclass 24, count 2 2006.286.04:45:31.33#ibcon#read 4, iclass 24, count 2 2006.286.04:45:31.33#ibcon#about to read 5, iclass 24, count 2 2006.286.04:45:31.33#ibcon#read 5, iclass 24, count 2 2006.286.04:45:31.33#ibcon#about to read 6, iclass 24, count 2 2006.286.04:45:31.33#ibcon#read 6, iclass 24, count 2 2006.286.04:45:31.33#ibcon#end of sib2, iclass 24, count 2 2006.286.04:45:31.33#ibcon#*mode == 0, iclass 24, count 2 2006.286.04:45:31.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.04:45:31.33#ibcon#[27=AT08-04\r\n] 2006.286.04:45:31.33#ibcon#*before write, iclass 24, count 2 2006.286.04:45:31.33#ibcon#enter sib2, iclass 24, count 2 2006.286.04:45:31.33#ibcon#flushed, iclass 24, count 2 2006.286.04:45:31.33#ibcon#about to write, iclass 24, count 2 2006.286.04:45:31.33#ibcon#wrote, iclass 24, count 2 2006.286.04:45:31.33#ibcon#about to read 3, iclass 24, count 2 2006.286.04:45:31.36#ibcon#read 3, iclass 24, count 2 2006.286.04:45:31.36#ibcon#about to read 4, iclass 24, count 2 2006.286.04:45:31.36#ibcon#read 4, iclass 24, count 2 2006.286.04:45:31.36#ibcon#about to read 5, iclass 24, count 2 2006.286.04:45:31.36#ibcon#read 5, iclass 24, count 2 2006.286.04:45:31.36#ibcon#about to read 6, iclass 24, count 2 2006.286.04:45:31.36#ibcon#read 6, iclass 24, count 2 2006.286.04:45:31.36#ibcon#end of sib2, iclass 24, count 2 2006.286.04:45:31.36#ibcon#*after write, iclass 24, count 2 2006.286.04:45:31.36#ibcon#*before return 0, iclass 24, count 2 2006.286.04:45:31.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:45:31.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:45:31.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.04:45:31.36#ibcon#ireg 7 cls_cnt 0 2006.286.04:45:31.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:45:31.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:45:31.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:45:31.48#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:45:31.48#ibcon#first serial, iclass 24, count 0 2006.286.04:45:31.48#ibcon#enter sib2, iclass 24, count 0 2006.286.04:45:31.48#ibcon#flushed, iclass 24, count 0 2006.286.04:45:31.48#ibcon#about to write, iclass 24, count 0 2006.286.04:45:31.48#ibcon#wrote, iclass 24, count 0 2006.286.04:45:31.48#ibcon#about to read 3, iclass 24, count 0 2006.286.04:45:31.50#ibcon#read 3, iclass 24, count 0 2006.286.04:45:31.50#ibcon#about to read 4, iclass 24, count 0 2006.286.04:45:31.50#ibcon#read 4, iclass 24, count 0 2006.286.04:45:31.50#ibcon#about to read 5, iclass 24, count 0 2006.286.04:45:31.50#ibcon#read 5, iclass 24, count 0 2006.286.04:45:31.50#ibcon#about to read 6, iclass 24, count 0 2006.286.04:45:31.50#ibcon#read 6, iclass 24, count 0 2006.286.04:45:31.50#ibcon#end of sib2, iclass 24, count 0 2006.286.04:45:31.50#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:45:31.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:45:31.50#ibcon#[27=USB\r\n] 2006.286.04:45:31.50#ibcon#*before write, iclass 24, count 0 2006.286.04:45:31.50#ibcon#enter sib2, iclass 24, count 0 2006.286.04:45:31.50#ibcon#flushed, iclass 24, count 0 2006.286.04:45:31.50#ibcon#about to write, iclass 24, count 0 2006.286.04:45:31.50#ibcon#wrote, iclass 24, count 0 2006.286.04:45:31.50#ibcon#about to read 3, iclass 24, count 0 2006.286.04:45:31.53#ibcon#read 3, iclass 24, count 0 2006.286.04:45:31.53#ibcon#about to read 4, iclass 24, count 0 2006.286.04:45:31.53#ibcon#read 4, iclass 24, count 0 2006.286.04:45:31.53#ibcon#about to read 5, iclass 24, count 0 2006.286.04:45:31.53#ibcon#read 5, iclass 24, count 0 2006.286.04:45:31.53#ibcon#about to read 6, iclass 24, count 0 2006.286.04:45:31.53#ibcon#read 6, iclass 24, count 0 2006.286.04:45:31.53#ibcon#end of sib2, iclass 24, count 0 2006.286.04:45:31.53#ibcon#*after write, iclass 24, count 0 2006.286.04:45:31.53#ibcon#*before return 0, iclass 24, count 0 2006.286.04:45:31.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:45:31.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:45:31.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:45:31.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:45:31.53$vck44/vabw=wide 2006.286.04:45:31.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.04:45:31.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.04:45:31.53#ibcon#ireg 8 cls_cnt 0 2006.286.04:45:31.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:45:31.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:45:31.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:45:31.53#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:45:31.53#ibcon#first serial, iclass 26, count 0 2006.286.04:45:31.53#ibcon#enter sib2, iclass 26, count 0 2006.286.04:45:31.53#ibcon#flushed, iclass 26, count 0 2006.286.04:45:31.53#ibcon#about to write, iclass 26, count 0 2006.286.04:45:31.53#ibcon#wrote, iclass 26, count 0 2006.286.04:45:31.53#ibcon#about to read 3, iclass 26, count 0 2006.286.04:45:31.55#ibcon#read 3, iclass 26, count 0 2006.286.04:45:31.55#ibcon#about to read 4, iclass 26, count 0 2006.286.04:45:31.55#ibcon#read 4, iclass 26, count 0 2006.286.04:45:31.55#ibcon#about to read 5, iclass 26, count 0 2006.286.04:45:31.55#ibcon#read 5, iclass 26, count 0 2006.286.04:45:31.55#ibcon#about to read 6, iclass 26, count 0 2006.286.04:45:31.55#ibcon#read 6, iclass 26, count 0 2006.286.04:45:31.55#ibcon#end of sib2, iclass 26, count 0 2006.286.04:45:31.55#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:45:31.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:45:31.55#ibcon#[25=BW32\r\n] 2006.286.04:45:31.55#ibcon#*before write, iclass 26, count 0 2006.286.04:45:31.55#ibcon#enter sib2, iclass 26, count 0 2006.286.04:45:31.55#ibcon#flushed, iclass 26, count 0 2006.286.04:45:31.55#ibcon#about to write, iclass 26, count 0 2006.286.04:45:31.55#ibcon#wrote, iclass 26, count 0 2006.286.04:45:31.55#ibcon#about to read 3, iclass 26, count 0 2006.286.04:45:31.58#ibcon#read 3, iclass 26, count 0 2006.286.04:45:31.58#ibcon#about to read 4, iclass 26, count 0 2006.286.04:45:31.58#ibcon#read 4, iclass 26, count 0 2006.286.04:45:31.58#ibcon#about to read 5, iclass 26, count 0 2006.286.04:45:31.58#ibcon#read 5, iclass 26, count 0 2006.286.04:45:31.58#ibcon#about to read 6, iclass 26, count 0 2006.286.04:45:31.58#ibcon#read 6, iclass 26, count 0 2006.286.04:45:31.58#ibcon#end of sib2, iclass 26, count 0 2006.286.04:45:31.58#ibcon#*after write, iclass 26, count 0 2006.286.04:45:31.58#ibcon#*before return 0, iclass 26, count 0 2006.286.04:45:31.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:45:31.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:45:31.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:45:31.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:45:31.58$vck44/vbbw=wide 2006.286.04:45:31.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.04:45:31.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.04:45:31.58#ibcon#ireg 8 cls_cnt 0 2006.286.04:45:31.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:45:31.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:45:31.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:45:31.65#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:45:31.65#ibcon#first serial, iclass 28, count 0 2006.286.04:45:31.65#ibcon#enter sib2, iclass 28, count 0 2006.286.04:45:31.65#ibcon#flushed, iclass 28, count 0 2006.286.04:45:31.65#ibcon#about to write, iclass 28, count 0 2006.286.04:45:31.65#ibcon#wrote, iclass 28, count 0 2006.286.04:45:31.65#ibcon#about to read 3, iclass 28, count 0 2006.286.04:45:31.67#ibcon#read 3, iclass 28, count 0 2006.286.04:45:31.67#ibcon#about to read 4, iclass 28, count 0 2006.286.04:45:31.67#ibcon#read 4, iclass 28, count 0 2006.286.04:45:31.67#ibcon#about to read 5, iclass 28, count 0 2006.286.04:45:31.67#ibcon#read 5, iclass 28, count 0 2006.286.04:45:31.67#ibcon#about to read 6, iclass 28, count 0 2006.286.04:45:31.67#ibcon#read 6, iclass 28, count 0 2006.286.04:45:31.67#ibcon#end of sib2, iclass 28, count 0 2006.286.04:45:31.67#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:45:31.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:45:31.67#ibcon#[27=BW32\r\n] 2006.286.04:45:31.67#ibcon#*before write, iclass 28, count 0 2006.286.04:45:31.67#ibcon#enter sib2, iclass 28, count 0 2006.286.04:45:31.67#ibcon#flushed, iclass 28, count 0 2006.286.04:45:31.67#ibcon#about to write, iclass 28, count 0 2006.286.04:45:31.67#ibcon#wrote, iclass 28, count 0 2006.286.04:45:31.67#ibcon#about to read 3, iclass 28, count 0 2006.286.04:45:31.70#ibcon#read 3, iclass 28, count 0 2006.286.04:45:31.70#ibcon#about to read 4, iclass 28, count 0 2006.286.04:45:31.70#ibcon#read 4, iclass 28, count 0 2006.286.04:45:31.70#ibcon#about to read 5, iclass 28, count 0 2006.286.04:45:31.70#ibcon#read 5, iclass 28, count 0 2006.286.04:45:31.70#ibcon#about to read 6, iclass 28, count 0 2006.286.04:45:31.70#ibcon#read 6, iclass 28, count 0 2006.286.04:45:31.70#ibcon#end of sib2, iclass 28, count 0 2006.286.04:45:31.70#ibcon#*after write, iclass 28, count 0 2006.286.04:45:31.70#ibcon#*before return 0, iclass 28, count 0 2006.286.04:45:31.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:45:31.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.04:45:31.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:45:31.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:45:31.70$setupk4/ifdk4 2006.286.04:45:31.70$ifdk4/lo= 2006.286.04:45:31.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:45:31.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:45:31.70$ifdk4/patch= 2006.286.04:45:31.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:45:31.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:45:31.70$setupk4/!*+20s 2006.286.04:45:37.35#abcon#<5=/04 3.8 6.3 22.25 731014.8\r\n> 2006.286.04:45:37.37#abcon#{5=INTERFACE CLEAR} 2006.286.04:45:37.43#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:45:44.89$setupk4/"tpicd 2006.286.04:45:44.89$setupk4/echo=off 2006.286.04:45:44.89$setupk4/xlog=off 2006.286.04:45:44.89:!2006.286.04:49:47 2006.286.04:45:54.14#trakl#Source acquired 2006.286.04:45:55.14#flagr#flagr/antenna,acquired 2006.286.04:47:12.14#trakl#Off source 2006.286.04:47:12.14?ERROR st -7 Antenna off-source! 2006.286.04:47:12.14#trakl#az 118.107 el 7.122 azerr*cos(el) -0.0016 elerr 0.0169 2006.286.04:47:13.14#flagr#flagr/antenna,off-source 2006.286.04:47:18.14#trakl#Source re-acquired 2006.286.04:47:19.14#flagr#flagr/antenna,re-acquired 2006.286.04:49:47.00:preob 2006.286.04:49:47.13/onsource/TRACKING 2006.286.04:49:47.13:!2006.286.04:49:57 2006.286.04:49:57.00:"tape 2006.286.04:49:57.00:"st=record 2006.286.04:49:57.00:data_valid=on 2006.286.04:49:57.00:midob 2006.286.04:49:58.13/onsource/TRACKING 2006.286.04:49:58.13/wx/22.19,1014.8,75 2006.286.04:49:58.23/cable/+6.4953E-03 2006.286.04:49:59.32/va/01,07,usb,yes,39,42 2006.286.04:49:59.32/va/02,06,usb,yes,39,40 2006.286.04:49:59.32/va/03,07,usb,yes,39,41 2006.286.04:49:59.32/va/04,06,usb,yes,40,42 2006.286.04:49:59.32/va/05,03,usb,yes,40,41 2006.286.04:49:59.32/va/06,04,usb,yes,36,36 2006.286.04:49:59.32/va/07,04,usb,yes,37,38 2006.286.04:49:59.32/va/08,03,usb,yes,38,46 2006.286.04:49:59.55/valo/01,524.99,yes,locked 2006.286.04:49:59.55/valo/02,534.99,yes,locked 2006.286.04:49:59.55/valo/03,564.99,yes,locked 2006.286.04:49:59.55/valo/04,624.99,yes,locked 2006.286.04:49:59.55/valo/05,734.99,yes,locked 2006.286.04:49:59.55/valo/06,814.99,yes,locked 2006.286.04:49:59.55/valo/07,864.99,yes,locked 2006.286.04:49:59.55/valo/08,884.99,yes,locked 2006.286.04:50:00.64/vb/01,04,usb,yes,32,32 2006.286.04:50:00.64/vb/02,05,usb,yes,31,32 2006.286.04:50:00.64/vb/03,04,usb,yes,32,35 2006.286.04:50:00.64/vb/04,05,usb,yes,32,31 2006.286.04:50:00.64/vb/05,04,usb,yes,28,31 2006.286.04:50:00.64/vb/06,03,usb,yes,41,36 2006.286.04:50:00.64/vb/07,04,usb,yes,33,33 2006.286.04:50:00.64/vb/08,04,usb,yes,30,34 2006.286.04:50:00.87/vblo/01,629.99,yes,locked 2006.286.04:50:00.87/vblo/02,634.99,yes,locked 2006.286.04:50:00.87/vblo/03,649.99,yes,locked 2006.286.04:50:00.87/vblo/04,679.99,yes,locked 2006.286.04:50:00.87/vblo/05,709.99,yes,locked 2006.286.04:50:00.87/vblo/06,719.99,yes,locked 2006.286.04:50:00.87/vblo/07,734.99,yes,locked 2006.286.04:50:00.87/vblo/08,744.99,yes,locked 2006.286.04:50:01.02/vabw/8 2006.286.04:50:01.17/vbbw/8 2006.286.04:50:01.34/xfe/off,on,12.2 2006.286.04:50:01.72/ifatt/23,28,28,28 2006.286.04:50:02.07/fmout-gps/S +2.40E-07 2006.286.04:50:02.09:!2006.286.04:50:37 2006.286.04:50:37.01:data_valid=off 2006.286.04:50:37.01:"et 2006.286.04:50:37.01:!+3s 2006.286.04:50:40.02:"tape 2006.286.04:50:40.02:postob 2006.286.04:50:40.12/cable/+6.4940E-03 2006.286.04:50:40.12/wx/22.18,1014.8,77 2006.286.04:50:41.07/fmout-gps/S +2.41E-07 2006.286.04:50:41.07:scan_name=286-0451,jd0610,40 2006.286.04:50:41.07:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.286.04:50:42.14#flagr#flagr/antenna,new-source 2006.286.04:50:42.14:checkk5 2006.286.04:50:42.63/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:50:43.02/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:50:43.75/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:50:44.26/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:50:44.61/chk_obsdata//k5ts1/T2860449??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:50:45.03/chk_obsdata//k5ts2/T2860449??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:50:45.55/chk_obsdata//k5ts3/T2860449??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:50:45.95/chk_obsdata//k5ts4/T2860449??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:50:46.90/k5log//k5ts1_log_newline 2006.286.04:50:47.68/k5log//k5ts2_log_newline 2006.286.04:50:48.61/k5log//k5ts3_log_newline 2006.286.04:50:49.70/k5log//k5ts4_log_newline 2006.286.04:50:49.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:50:49.72:setupk4=1 2006.286.04:50:49.72$setupk4/echo=on 2006.286.04:50:49.72$setupk4/pcalon 2006.286.04:50:49.72$pcalon/"no phase cal control is implemented here 2006.286.04:50:49.72$setupk4/"tpicd=stop 2006.286.04:50:49.72$setupk4/"rec=synch_on 2006.286.04:50:49.72$setupk4/"rec_mode=128 2006.286.04:50:49.72$setupk4/!* 2006.286.04:50:49.72$setupk4/recpk4 2006.286.04:50:49.72$recpk4/recpatch= 2006.286.04:50:49.72$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:50:49.72$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:50:49.72$setupk4/vck44 2006.286.04:50:49.73$vck44/valo=1,524.99 2006.286.04:50:49.73#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.04:50:49.73#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.04:50:49.73#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:49.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:50:49.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:50:49.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:50:49.73#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:50:49.73#ibcon#first serial, iclass 15, count 0 2006.286.04:50:49.73#ibcon#enter sib2, iclass 15, count 0 2006.286.04:50:49.73#ibcon#flushed, iclass 15, count 0 2006.286.04:50:49.73#ibcon#about to write, iclass 15, count 0 2006.286.04:50:49.73#ibcon#wrote, iclass 15, count 0 2006.286.04:50:49.73#ibcon#about to read 3, iclass 15, count 0 2006.286.04:50:49.74#ibcon#read 3, iclass 15, count 0 2006.286.04:50:49.74#ibcon#about to read 4, iclass 15, count 0 2006.286.04:50:49.74#ibcon#read 4, iclass 15, count 0 2006.286.04:50:49.74#ibcon#about to read 5, iclass 15, count 0 2006.286.04:50:49.74#ibcon#read 5, iclass 15, count 0 2006.286.04:50:49.74#ibcon#about to read 6, iclass 15, count 0 2006.286.04:50:49.74#ibcon#read 6, iclass 15, count 0 2006.286.04:50:49.74#ibcon#end of sib2, iclass 15, count 0 2006.286.04:50:49.74#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:50:49.74#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:50:49.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:50:49.74#ibcon#*before write, iclass 15, count 0 2006.286.04:50:49.74#ibcon#enter sib2, iclass 15, count 0 2006.286.04:50:49.74#ibcon#flushed, iclass 15, count 0 2006.286.04:50:49.74#ibcon#about to write, iclass 15, count 0 2006.286.04:50:49.74#ibcon#wrote, iclass 15, count 0 2006.286.04:50:49.74#ibcon#about to read 3, iclass 15, count 0 2006.286.04:50:49.79#ibcon#read 3, iclass 15, count 0 2006.286.04:50:49.79#ibcon#about to read 4, iclass 15, count 0 2006.286.04:50:49.79#ibcon#read 4, iclass 15, count 0 2006.286.04:50:49.79#ibcon#about to read 5, iclass 15, count 0 2006.286.04:50:49.79#ibcon#read 5, iclass 15, count 0 2006.286.04:50:49.79#ibcon#about to read 6, iclass 15, count 0 2006.286.04:50:49.79#ibcon#read 6, iclass 15, count 0 2006.286.04:50:49.79#ibcon#end of sib2, iclass 15, count 0 2006.286.04:50:49.79#ibcon#*after write, iclass 15, count 0 2006.286.04:50:49.79#ibcon#*before return 0, iclass 15, count 0 2006.286.04:50:49.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:50:49.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:50:49.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:50:49.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:50:49.79$vck44/va=1,7 2006.286.04:50:49.79#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.04:50:49.79#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.04:50:49.79#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:49.79#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:50:49.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:50:49.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:50:49.79#ibcon#enter wrdev, iclass 17, count 2 2006.286.04:50:49.79#ibcon#first serial, iclass 17, count 2 2006.286.04:50:49.79#ibcon#enter sib2, iclass 17, count 2 2006.286.04:50:49.79#ibcon#flushed, iclass 17, count 2 2006.286.04:50:49.79#ibcon#about to write, iclass 17, count 2 2006.286.04:50:49.79#ibcon#wrote, iclass 17, count 2 2006.286.04:50:49.79#ibcon#about to read 3, iclass 17, count 2 2006.286.04:50:49.81#ibcon#read 3, iclass 17, count 2 2006.286.04:50:49.81#ibcon#about to read 4, iclass 17, count 2 2006.286.04:50:49.81#ibcon#read 4, iclass 17, count 2 2006.286.04:50:49.81#ibcon#about to read 5, iclass 17, count 2 2006.286.04:50:49.81#ibcon#read 5, iclass 17, count 2 2006.286.04:50:49.81#ibcon#about to read 6, iclass 17, count 2 2006.286.04:50:49.81#ibcon#read 6, iclass 17, count 2 2006.286.04:50:49.81#ibcon#end of sib2, iclass 17, count 2 2006.286.04:50:49.81#ibcon#*mode == 0, iclass 17, count 2 2006.286.04:50:49.81#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.04:50:49.81#ibcon#[25=AT01-07\r\n] 2006.286.04:50:49.81#ibcon#*before write, iclass 17, count 2 2006.286.04:50:49.81#ibcon#enter sib2, iclass 17, count 2 2006.286.04:50:49.81#ibcon#flushed, iclass 17, count 2 2006.286.04:50:49.81#ibcon#about to write, iclass 17, count 2 2006.286.04:50:49.81#ibcon#wrote, iclass 17, count 2 2006.286.04:50:49.81#ibcon#about to read 3, iclass 17, count 2 2006.286.04:50:49.84#ibcon#read 3, iclass 17, count 2 2006.286.04:50:49.84#ibcon#about to read 4, iclass 17, count 2 2006.286.04:50:49.84#ibcon#read 4, iclass 17, count 2 2006.286.04:50:49.84#ibcon#about to read 5, iclass 17, count 2 2006.286.04:50:49.84#ibcon#read 5, iclass 17, count 2 2006.286.04:50:49.84#ibcon#about to read 6, iclass 17, count 2 2006.286.04:50:49.84#ibcon#read 6, iclass 17, count 2 2006.286.04:50:49.84#ibcon#end of sib2, iclass 17, count 2 2006.286.04:50:49.84#ibcon#*after write, iclass 17, count 2 2006.286.04:50:49.84#ibcon#*before return 0, iclass 17, count 2 2006.286.04:50:49.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:50:49.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:50:49.84#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.04:50:49.84#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:49.84#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:50:49.96#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:50:49.96#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:50:49.96#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:50:49.96#ibcon#first serial, iclass 17, count 0 2006.286.04:50:49.96#ibcon#enter sib2, iclass 17, count 0 2006.286.04:50:49.96#ibcon#flushed, iclass 17, count 0 2006.286.04:50:49.96#ibcon#about to write, iclass 17, count 0 2006.286.04:50:49.96#ibcon#wrote, iclass 17, count 0 2006.286.04:50:49.96#ibcon#about to read 3, iclass 17, count 0 2006.286.04:50:49.98#ibcon#read 3, iclass 17, count 0 2006.286.04:50:49.98#ibcon#about to read 4, iclass 17, count 0 2006.286.04:50:49.98#ibcon#read 4, iclass 17, count 0 2006.286.04:50:49.98#ibcon#about to read 5, iclass 17, count 0 2006.286.04:50:49.98#ibcon#read 5, iclass 17, count 0 2006.286.04:50:49.98#ibcon#about to read 6, iclass 17, count 0 2006.286.04:50:49.98#ibcon#read 6, iclass 17, count 0 2006.286.04:50:49.98#ibcon#end of sib2, iclass 17, count 0 2006.286.04:50:49.98#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:50:49.98#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:50:49.98#ibcon#[25=USB\r\n] 2006.286.04:50:49.98#ibcon#*before write, iclass 17, count 0 2006.286.04:50:49.98#ibcon#enter sib2, iclass 17, count 0 2006.286.04:50:49.98#ibcon#flushed, iclass 17, count 0 2006.286.04:50:49.98#ibcon#about to write, iclass 17, count 0 2006.286.04:50:49.98#ibcon#wrote, iclass 17, count 0 2006.286.04:50:49.98#ibcon#about to read 3, iclass 17, count 0 2006.286.04:50:50.01#ibcon#read 3, iclass 17, count 0 2006.286.04:50:50.01#ibcon#about to read 4, iclass 17, count 0 2006.286.04:50:50.01#ibcon#read 4, iclass 17, count 0 2006.286.04:50:50.01#ibcon#about to read 5, iclass 17, count 0 2006.286.04:50:50.01#ibcon#read 5, iclass 17, count 0 2006.286.04:50:50.01#ibcon#about to read 6, iclass 17, count 0 2006.286.04:50:50.01#ibcon#read 6, iclass 17, count 0 2006.286.04:50:50.01#ibcon#end of sib2, iclass 17, count 0 2006.286.04:50:50.01#ibcon#*after write, iclass 17, count 0 2006.286.04:50:50.01#ibcon#*before return 0, iclass 17, count 0 2006.286.04:50:50.01#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:50:50.01#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:50:50.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:50:50.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:50:50.01$vck44/valo=2,534.99 2006.286.04:50:50.01#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.04:50:50.01#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.04:50:50.01#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:50.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:50:50.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:50:50.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:50:50.01#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:50:50.01#ibcon#first serial, iclass 19, count 0 2006.286.04:50:50.01#ibcon#enter sib2, iclass 19, count 0 2006.286.04:50:50.01#ibcon#flushed, iclass 19, count 0 2006.286.04:50:50.01#ibcon#about to write, iclass 19, count 0 2006.286.04:50:50.01#ibcon#wrote, iclass 19, count 0 2006.286.04:50:50.01#ibcon#about to read 3, iclass 19, count 0 2006.286.04:50:50.03#ibcon#read 3, iclass 19, count 0 2006.286.04:50:50.03#ibcon#about to read 4, iclass 19, count 0 2006.286.04:50:50.03#ibcon#read 4, iclass 19, count 0 2006.286.04:50:50.03#ibcon#about to read 5, iclass 19, count 0 2006.286.04:50:50.03#ibcon#read 5, iclass 19, count 0 2006.286.04:50:50.03#ibcon#about to read 6, iclass 19, count 0 2006.286.04:50:50.03#ibcon#read 6, iclass 19, count 0 2006.286.04:50:50.03#ibcon#end of sib2, iclass 19, count 0 2006.286.04:50:50.03#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:50:50.03#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:50:50.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:50:50.03#ibcon#*before write, iclass 19, count 0 2006.286.04:50:50.03#ibcon#enter sib2, iclass 19, count 0 2006.286.04:50:50.03#ibcon#flushed, iclass 19, count 0 2006.286.04:50:50.03#ibcon#about to write, iclass 19, count 0 2006.286.04:50:50.03#ibcon#wrote, iclass 19, count 0 2006.286.04:50:50.03#ibcon#about to read 3, iclass 19, count 0 2006.286.04:50:50.07#ibcon#read 3, iclass 19, count 0 2006.286.04:50:50.53#ibcon#about to read 4, iclass 19, count 0 2006.286.04:50:50.53#ibcon#read 4, iclass 19, count 0 2006.286.04:50:50.53#ibcon#about to read 5, iclass 19, count 0 2006.286.04:50:50.53#ibcon#read 5, iclass 19, count 0 2006.286.04:50:50.53#ibcon#about to read 6, iclass 19, count 0 2006.286.04:50:50.53#ibcon#read 6, iclass 19, count 0 2006.286.04:50:50.53#ibcon#end of sib2, iclass 19, count 0 2006.286.04:50:50.53#ibcon#*after write, iclass 19, count 0 2006.286.04:50:50.53#ibcon#*before return 0, iclass 19, count 0 2006.286.04:50:50.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:50:50.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:50:50.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:50:50.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:50:50.53$vck44/va=2,6 2006.286.04:50:50.53#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.04:50:50.53#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.04:50:50.53#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:50.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:50:50.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:50:50.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:50:50.53#ibcon#enter wrdev, iclass 21, count 2 2006.286.04:50:50.53#ibcon#first serial, iclass 21, count 2 2006.286.04:50:50.53#ibcon#enter sib2, iclass 21, count 2 2006.286.04:50:50.53#ibcon#flushed, iclass 21, count 2 2006.286.04:50:50.53#ibcon#about to write, iclass 21, count 2 2006.286.04:50:50.53#ibcon#wrote, iclass 21, count 2 2006.286.04:50:50.53#ibcon#about to read 3, iclass 21, count 2 2006.286.04:50:50.55#ibcon#read 3, iclass 21, count 2 2006.286.04:50:50.55#ibcon#about to read 4, iclass 21, count 2 2006.286.04:50:50.55#ibcon#read 4, iclass 21, count 2 2006.286.04:50:50.55#ibcon#about to read 5, iclass 21, count 2 2006.286.04:50:50.55#ibcon#read 5, iclass 21, count 2 2006.286.04:50:50.55#ibcon#about to read 6, iclass 21, count 2 2006.286.04:50:50.55#ibcon#read 6, iclass 21, count 2 2006.286.04:50:50.55#ibcon#end of sib2, iclass 21, count 2 2006.286.04:50:50.55#ibcon#*mode == 0, iclass 21, count 2 2006.286.04:50:50.55#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.04:50:50.55#ibcon#[25=AT02-06\r\n] 2006.286.04:50:50.55#ibcon#*before write, iclass 21, count 2 2006.286.04:50:50.55#ibcon#enter sib2, iclass 21, count 2 2006.286.04:50:50.55#ibcon#flushed, iclass 21, count 2 2006.286.04:50:50.55#ibcon#about to write, iclass 21, count 2 2006.286.04:50:50.55#ibcon#wrote, iclass 21, count 2 2006.286.04:50:50.55#ibcon#about to read 3, iclass 21, count 2 2006.286.04:50:50.58#ibcon#read 3, iclass 21, count 2 2006.286.04:50:50.58#ibcon#about to read 4, iclass 21, count 2 2006.286.04:50:50.58#ibcon#read 4, iclass 21, count 2 2006.286.04:50:50.58#ibcon#about to read 5, iclass 21, count 2 2006.286.04:50:50.58#ibcon#read 5, iclass 21, count 2 2006.286.04:50:50.58#ibcon#about to read 6, iclass 21, count 2 2006.286.04:50:50.58#ibcon#read 6, iclass 21, count 2 2006.286.04:50:50.58#ibcon#end of sib2, iclass 21, count 2 2006.286.04:50:50.58#ibcon#*after write, iclass 21, count 2 2006.286.04:50:50.58#ibcon#*before return 0, iclass 21, count 2 2006.286.04:50:50.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:50:50.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:50:50.58#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.04:50:50.58#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:50.58#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:50:50.70#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:50:50.70#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:50:50.70#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:50:50.70#ibcon#first serial, iclass 21, count 0 2006.286.04:50:50.70#ibcon#enter sib2, iclass 21, count 0 2006.286.04:50:50.70#ibcon#flushed, iclass 21, count 0 2006.286.04:50:50.70#ibcon#about to write, iclass 21, count 0 2006.286.04:50:50.70#ibcon#wrote, iclass 21, count 0 2006.286.04:50:50.70#ibcon#about to read 3, iclass 21, count 0 2006.286.04:50:50.72#ibcon#read 3, iclass 21, count 0 2006.286.04:50:50.72#ibcon#about to read 4, iclass 21, count 0 2006.286.04:50:50.72#ibcon#read 4, iclass 21, count 0 2006.286.04:50:50.72#ibcon#about to read 5, iclass 21, count 0 2006.286.04:50:50.72#ibcon#read 5, iclass 21, count 0 2006.286.04:50:50.72#ibcon#about to read 6, iclass 21, count 0 2006.286.04:50:50.72#ibcon#read 6, iclass 21, count 0 2006.286.04:50:50.72#ibcon#end of sib2, iclass 21, count 0 2006.286.04:50:50.72#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:50:50.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:50:50.72#ibcon#[25=USB\r\n] 2006.286.04:50:50.72#ibcon#*before write, iclass 21, count 0 2006.286.04:50:50.72#ibcon#enter sib2, iclass 21, count 0 2006.286.04:50:50.72#ibcon#flushed, iclass 21, count 0 2006.286.04:50:50.72#ibcon#about to write, iclass 21, count 0 2006.286.04:50:50.72#ibcon#wrote, iclass 21, count 0 2006.286.04:50:50.72#ibcon#about to read 3, iclass 21, count 0 2006.286.04:50:50.75#ibcon#read 3, iclass 21, count 0 2006.286.04:50:50.75#ibcon#about to read 4, iclass 21, count 0 2006.286.04:50:50.75#ibcon#read 4, iclass 21, count 0 2006.286.04:50:50.75#ibcon#about to read 5, iclass 21, count 0 2006.286.04:50:50.75#ibcon#read 5, iclass 21, count 0 2006.286.04:50:50.75#ibcon#about to read 6, iclass 21, count 0 2006.286.04:50:50.75#ibcon#read 6, iclass 21, count 0 2006.286.04:50:50.75#ibcon#end of sib2, iclass 21, count 0 2006.286.04:50:50.75#ibcon#*after write, iclass 21, count 0 2006.286.04:50:50.75#ibcon#*before return 0, iclass 21, count 0 2006.286.04:50:50.75#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:50:50.75#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:50:50.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:50:50.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:50:50.75$vck44/valo=3,564.99 2006.286.04:50:50.75#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.04:50:50.75#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.04:50:50.75#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:50.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:50:50.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:50:50.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:50:50.75#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:50:50.75#ibcon#first serial, iclass 23, count 0 2006.286.04:50:50.75#ibcon#enter sib2, iclass 23, count 0 2006.286.04:50:50.75#ibcon#flushed, iclass 23, count 0 2006.286.04:50:50.75#ibcon#about to write, iclass 23, count 0 2006.286.04:50:50.75#ibcon#wrote, iclass 23, count 0 2006.286.04:50:50.75#ibcon#about to read 3, iclass 23, count 0 2006.286.04:50:50.77#ibcon#read 3, iclass 23, count 0 2006.286.04:50:50.77#ibcon#about to read 4, iclass 23, count 0 2006.286.04:50:50.77#ibcon#read 4, iclass 23, count 0 2006.286.04:50:50.77#ibcon#about to read 5, iclass 23, count 0 2006.286.04:50:50.77#ibcon#read 5, iclass 23, count 0 2006.286.04:50:50.77#ibcon#about to read 6, iclass 23, count 0 2006.286.04:50:50.77#ibcon#read 6, iclass 23, count 0 2006.286.04:50:50.77#ibcon#end of sib2, iclass 23, count 0 2006.286.04:50:50.77#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:50:50.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:50:50.77#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:50:50.77#ibcon#*before write, iclass 23, count 0 2006.286.04:50:50.77#ibcon#enter sib2, iclass 23, count 0 2006.286.04:50:50.77#ibcon#flushed, iclass 23, count 0 2006.286.04:50:50.77#ibcon#about to write, iclass 23, count 0 2006.286.04:50:50.77#ibcon#wrote, iclass 23, count 0 2006.286.04:50:50.77#ibcon#about to read 3, iclass 23, count 0 2006.286.04:50:50.81#ibcon#read 3, iclass 23, count 0 2006.286.04:50:50.81#ibcon#about to read 4, iclass 23, count 0 2006.286.04:50:50.81#ibcon#read 4, iclass 23, count 0 2006.286.04:50:50.81#ibcon#about to read 5, iclass 23, count 0 2006.286.04:50:50.81#ibcon#read 5, iclass 23, count 0 2006.286.04:50:50.81#ibcon#about to read 6, iclass 23, count 0 2006.286.04:50:50.81#ibcon#read 6, iclass 23, count 0 2006.286.04:50:50.81#ibcon#end of sib2, iclass 23, count 0 2006.286.04:50:50.81#ibcon#*after write, iclass 23, count 0 2006.286.04:50:50.81#ibcon#*before return 0, iclass 23, count 0 2006.286.04:50:50.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:50:50.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:50:50.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:50:50.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:50:50.81$vck44/va=3,7 2006.286.04:50:50.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.04:50:50.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.04:50:50.97#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:50.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:50:50.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:50:50.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:50:50.97#ibcon#enter wrdev, iclass 25, count 2 2006.286.04:50:50.97#ibcon#first serial, iclass 25, count 2 2006.286.04:50:50.97#ibcon#enter sib2, iclass 25, count 2 2006.286.04:50:50.97#ibcon#flushed, iclass 25, count 2 2006.286.04:50:50.97#ibcon#about to write, iclass 25, count 2 2006.286.04:50:50.97#ibcon#wrote, iclass 25, count 2 2006.286.04:50:50.97#ibcon#about to read 3, iclass 25, count 2 2006.286.04:50:50.98#ibcon#read 3, iclass 25, count 2 2006.286.04:50:50.98#ibcon#about to read 4, iclass 25, count 2 2006.286.04:50:50.98#ibcon#read 4, iclass 25, count 2 2006.286.04:50:50.98#ibcon#about to read 5, iclass 25, count 2 2006.286.04:50:50.98#ibcon#read 5, iclass 25, count 2 2006.286.04:50:50.98#ibcon#about to read 6, iclass 25, count 2 2006.286.04:50:50.98#ibcon#read 6, iclass 25, count 2 2006.286.04:50:50.98#ibcon#end of sib2, iclass 25, count 2 2006.286.04:50:50.98#ibcon#*mode == 0, iclass 25, count 2 2006.286.04:50:50.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.04:50:50.98#ibcon#[25=AT03-07\r\n] 2006.286.04:50:50.98#ibcon#*before write, iclass 25, count 2 2006.286.04:50:50.98#ibcon#enter sib2, iclass 25, count 2 2006.286.04:50:50.98#ibcon#flushed, iclass 25, count 2 2006.286.04:50:50.98#ibcon#about to write, iclass 25, count 2 2006.286.04:50:50.98#ibcon#wrote, iclass 25, count 2 2006.286.04:50:50.98#ibcon#about to read 3, iclass 25, count 2 2006.286.04:50:51.01#ibcon#read 3, iclass 25, count 2 2006.286.04:50:51.01#ibcon#about to read 4, iclass 25, count 2 2006.286.04:50:51.01#ibcon#read 4, iclass 25, count 2 2006.286.04:50:51.01#ibcon#about to read 5, iclass 25, count 2 2006.286.04:50:51.01#ibcon#read 5, iclass 25, count 2 2006.286.04:50:51.01#ibcon#about to read 6, iclass 25, count 2 2006.286.04:50:51.01#ibcon#read 6, iclass 25, count 2 2006.286.04:50:51.01#ibcon#end of sib2, iclass 25, count 2 2006.286.04:50:51.01#ibcon#*after write, iclass 25, count 2 2006.286.04:50:51.01#ibcon#*before return 0, iclass 25, count 2 2006.286.04:50:51.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:50:51.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:50:51.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.04:50:51.01#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:51.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:50:51.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:50:51.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:50:51.13#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:50:51.13#ibcon#first serial, iclass 25, count 0 2006.286.04:50:51.13#ibcon#enter sib2, iclass 25, count 0 2006.286.04:50:51.13#ibcon#flushed, iclass 25, count 0 2006.286.04:50:51.13#ibcon#about to write, iclass 25, count 0 2006.286.04:50:51.13#ibcon#wrote, iclass 25, count 0 2006.286.04:50:51.13#ibcon#about to read 3, iclass 25, count 0 2006.286.04:50:51.15#ibcon#read 3, iclass 25, count 0 2006.286.04:50:51.15#ibcon#about to read 4, iclass 25, count 0 2006.286.04:50:51.15#ibcon#read 4, iclass 25, count 0 2006.286.04:50:51.15#ibcon#about to read 5, iclass 25, count 0 2006.286.04:50:51.15#ibcon#read 5, iclass 25, count 0 2006.286.04:50:51.15#ibcon#about to read 6, iclass 25, count 0 2006.286.04:50:51.15#ibcon#read 6, iclass 25, count 0 2006.286.04:50:51.15#ibcon#end of sib2, iclass 25, count 0 2006.286.04:50:51.15#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:50:51.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:50:51.15#ibcon#[25=USB\r\n] 2006.286.04:50:51.15#ibcon#*before write, iclass 25, count 0 2006.286.04:50:51.15#ibcon#enter sib2, iclass 25, count 0 2006.286.04:50:51.15#ibcon#flushed, iclass 25, count 0 2006.286.04:50:51.15#ibcon#about to write, iclass 25, count 0 2006.286.04:50:51.15#ibcon#wrote, iclass 25, count 0 2006.286.04:50:51.15#ibcon#about to read 3, iclass 25, count 0 2006.286.04:50:51.18#ibcon#read 3, iclass 25, count 0 2006.286.04:50:51.18#ibcon#about to read 4, iclass 25, count 0 2006.286.04:50:51.18#ibcon#read 4, iclass 25, count 0 2006.286.04:50:51.18#ibcon#about to read 5, iclass 25, count 0 2006.286.04:50:51.18#ibcon#read 5, iclass 25, count 0 2006.286.04:50:51.18#ibcon#about to read 6, iclass 25, count 0 2006.286.04:50:51.18#ibcon#read 6, iclass 25, count 0 2006.286.04:50:51.18#ibcon#end of sib2, iclass 25, count 0 2006.286.04:50:51.18#ibcon#*after write, iclass 25, count 0 2006.286.04:50:51.18#ibcon#*before return 0, iclass 25, count 0 2006.286.04:50:51.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:50:51.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:50:51.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:50:51.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:50:51.18$vck44/valo=4,624.99 2006.286.04:50:51.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.04:50:51.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.04:50:51.18#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:51.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:50:51.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:50:51.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:50:51.18#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:50:51.18#ibcon#first serial, iclass 27, count 0 2006.286.04:50:51.18#ibcon#enter sib2, iclass 27, count 0 2006.286.04:50:51.18#ibcon#flushed, iclass 27, count 0 2006.286.04:50:51.18#ibcon#about to write, iclass 27, count 0 2006.286.04:50:51.18#ibcon#wrote, iclass 27, count 0 2006.286.04:50:51.18#ibcon#about to read 3, iclass 27, count 0 2006.286.04:50:51.20#ibcon#read 3, iclass 27, count 0 2006.286.04:50:51.31#ibcon#about to read 4, iclass 27, count 0 2006.286.04:50:51.31#ibcon#read 4, iclass 27, count 0 2006.286.04:50:51.31#ibcon#about to read 5, iclass 27, count 0 2006.286.04:50:51.31#ibcon#read 5, iclass 27, count 0 2006.286.04:50:51.31#ibcon#about to read 6, iclass 27, count 0 2006.286.04:50:51.31#ibcon#read 6, iclass 27, count 0 2006.286.04:50:51.31#ibcon#end of sib2, iclass 27, count 0 2006.286.04:50:51.31#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:50:51.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:50:51.31#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:50:51.31#ibcon#*before write, iclass 27, count 0 2006.286.04:50:51.31#ibcon#enter sib2, iclass 27, count 0 2006.286.04:50:51.31#ibcon#flushed, iclass 27, count 0 2006.286.04:50:51.31#ibcon#about to write, iclass 27, count 0 2006.286.04:50:51.31#ibcon#wrote, iclass 27, count 0 2006.286.04:50:51.31#ibcon#about to read 3, iclass 27, count 0 2006.286.04:50:51.35#ibcon#read 3, iclass 27, count 0 2006.286.04:50:51.35#ibcon#about to read 4, iclass 27, count 0 2006.286.04:50:51.35#ibcon#read 4, iclass 27, count 0 2006.286.04:50:51.35#ibcon#about to read 5, iclass 27, count 0 2006.286.04:50:51.35#ibcon#read 5, iclass 27, count 0 2006.286.04:50:51.35#ibcon#about to read 6, iclass 27, count 0 2006.286.04:50:51.35#ibcon#read 6, iclass 27, count 0 2006.286.04:50:51.35#ibcon#end of sib2, iclass 27, count 0 2006.286.04:50:51.35#ibcon#*after write, iclass 27, count 0 2006.286.04:50:51.35#ibcon#*before return 0, iclass 27, count 0 2006.286.04:50:51.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:50:51.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:50:51.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:50:51.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:50:51.35$vck44/va=4,6 2006.286.04:50:51.35#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.04:50:51.35#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.04:50:51.35#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:51.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:50:51.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:50:51.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:50:51.35#ibcon#enter wrdev, iclass 29, count 2 2006.286.04:50:51.35#ibcon#first serial, iclass 29, count 2 2006.286.04:50:51.35#ibcon#enter sib2, iclass 29, count 2 2006.286.04:50:51.35#ibcon#flushed, iclass 29, count 2 2006.286.04:50:51.35#ibcon#about to write, iclass 29, count 2 2006.286.04:50:51.35#ibcon#wrote, iclass 29, count 2 2006.286.04:50:51.35#ibcon#about to read 3, iclass 29, count 2 2006.286.04:50:51.37#ibcon#read 3, iclass 29, count 2 2006.286.04:50:51.37#ibcon#about to read 4, iclass 29, count 2 2006.286.04:50:51.37#ibcon#read 4, iclass 29, count 2 2006.286.04:50:51.37#ibcon#about to read 5, iclass 29, count 2 2006.286.04:50:51.37#ibcon#read 5, iclass 29, count 2 2006.286.04:50:51.37#ibcon#about to read 6, iclass 29, count 2 2006.286.04:50:51.37#ibcon#read 6, iclass 29, count 2 2006.286.04:50:51.37#ibcon#end of sib2, iclass 29, count 2 2006.286.04:50:51.37#ibcon#*mode == 0, iclass 29, count 2 2006.286.04:50:51.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.04:50:51.37#ibcon#[25=AT04-06\r\n] 2006.286.04:50:51.37#ibcon#*before write, iclass 29, count 2 2006.286.04:50:51.37#ibcon#enter sib2, iclass 29, count 2 2006.286.04:50:51.37#ibcon#flushed, iclass 29, count 2 2006.286.04:50:51.37#ibcon#about to write, iclass 29, count 2 2006.286.04:50:51.37#ibcon#wrote, iclass 29, count 2 2006.286.04:50:51.37#ibcon#about to read 3, iclass 29, count 2 2006.286.04:50:51.40#ibcon#read 3, iclass 29, count 2 2006.286.04:50:51.40#ibcon#about to read 4, iclass 29, count 2 2006.286.04:50:51.40#ibcon#read 4, iclass 29, count 2 2006.286.04:50:51.40#ibcon#about to read 5, iclass 29, count 2 2006.286.04:50:51.40#ibcon#read 5, iclass 29, count 2 2006.286.04:50:51.40#ibcon#about to read 6, iclass 29, count 2 2006.286.04:50:51.40#ibcon#read 6, iclass 29, count 2 2006.286.04:50:51.40#ibcon#end of sib2, iclass 29, count 2 2006.286.04:50:51.40#ibcon#*after write, iclass 29, count 2 2006.286.04:50:51.40#ibcon#*before return 0, iclass 29, count 2 2006.286.04:50:51.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:50:51.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:50:51.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.04:50:51.40#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:51.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:50:51.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:50:51.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:50:51.52#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:50:51.52#ibcon#first serial, iclass 29, count 0 2006.286.04:50:51.52#ibcon#enter sib2, iclass 29, count 0 2006.286.04:50:51.52#ibcon#flushed, iclass 29, count 0 2006.286.04:50:51.52#ibcon#about to write, iclass 29, count 0 2006.286.04:50:51.52#ibcon#wrote, iclass 29, count 0 2006.286.04:50:51.52#ibcon#about to read 3, iclass 29, count 0 2006.286.04:50:51.54#ibcon#read 3, iclass 29, count 0 2006.286.04:50:51.54#ibcon#about to read 4, iclass 29, count 0 2006.286.04:50:51.54#ibcon#read 4, iclass 29, count 0 2006.286.04:50:51.54#ibcon#about to read 5, iclass 29, count 0 2006.286.04:50:51.54#ibcon#read 5, iclass 29, count 0 2006.286.04:50:51.54#ibcon#about to read 6, iclass 29, count 0 2006.286.04:50:51.54#ibcon#read 6, iclass 29, count 0 2006.286.04:50:51.54#ibcon#end of sib2, iclass 29, count 0 2006.286.04:50:51.54#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:50:51.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:50:51.54#ibcon#[25=USB\r\n] 2006.286.04:50:51.54#ibcon#*before write, iclass 29, count 0 2006.286.04:50:51.54#ibcon#enter sib2, iclass 29, count 0 2006.286.04:50:51.54#ibcon#flushed, iclass 29, count 0 2006.286.04:50:51.54#ibcon#about to write, iclass 29, count 0 2006.286.04:50:51.54#ibcon#wrote, iclass 29, count 0 2006.286.04:50:51.54#ibcon#about to read 3, iclass 29, count 0 2006.286.04:50:51.57#ibcon#read 3, iclass 29, count 0 2006.286.04:50:51.57#ibcon#about to read 4, iclass 29, count 0 2006.286.04:50:51.57#ibcon#read 4, iclass 29, count 0 2006.286.04:50:51.57#ibcon#about to read 5, iclass 29, count 0 2006.286.04:50:51.57#ibcon#read 5, iclass 29, count 0 2006.286.04:50:51.57#ibcon#about to read 6, iclass 29, count 0 2006.286.04:50:51.57#ibcon#read 6, iclass 29, count 0 2006.286.04:50:51.57#ibcon#end of sib2, iclass 29, count 0 2006.286.04:50:51.57#ibcon#*after write, iclass 29, count 0 2006.286.04:50:51.57#ibcon#*before return 0, iclass 29, count 0 2006.286.04:50:51.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:50:51.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:50:51.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:50:51.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:50:51.57$vck44/valo=5,734.99 2006.286.04:50:51.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.04:50:51.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.04:50:51.57#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:51.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:50:51.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:50:51.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:50:51.57#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:50:51.57#ibcon#first serial, iclass 31, count 0 2006.286.04:50:51.57#ibcon#enter sib2, iclass 31, count 0 2006.286.04:50:51.57#ibcon#flushed, iclass 31, count 0 2006.286.04:50:51.57#ibcon#about to write, iclass 31, count 0 2006.286.04:50:51.57#ibcon#wrote, iclass 31, count 0 2006.286.04:50:51.57#ibcon#about to read 3, iclass 31, count 0 2006.286.04:50:51.59#ibcon#read 3, iclass 31, count 0 2006.286.04:50:51.59#ibcon#about to read 4, iclass 31, count 0 2006.286.04:50:51.59#ibcon#read 4, iclass 31, count 0 2006.286.04:50:51.59#ibcon#about to read 5, iclass 31, count 0 2006.286.04:50:51.59#ibcon#read 5, iclass 31, count 0 2006.286.04:50:51.59#ibcon#about to read 6, iclass 31, count 0 2006.286.04:50:51.59#ibcon#read 6, iclass 31, count 0 2006.286.04:50:51.59#ibcon#end of sib2, iclass 31, count 0 2006.286.04:50:51.59#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:50:51.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:50:51.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:50:51.59#ibcon#*before write, iclass 31, count 0 2006.286.04:50:51.59#ibcon#enter sib2, iclass 31, count 0 2006.286.04:50:51.59#ibcon#flushed, iclass 31, count 0 2006.286.04:50:51.59#ibcon#about to write, iclass 31, count 0 2006.286.04:50:51.59#ibcon#wrote, iclass 31, count 0 2006.286.04:50:51.59#ibcon#about to read 3, iclass 31, count 0 2006.286.04:50:51.63#ibcon#read 3, iclass 31, count 0 2006.286.04:50:51.63#ibcon#about to read 4, iclass 31, count 0 2006.286.04:50:51.63#ibcon#read 4, iclass 31, count 0 2006.286.04:50:51.63#ibcon#about to read 5, iclass 31, count 0 2006.286.04:50:51.63#ibcon#read 5, iclass 31, count 0 2006.286.04:50:51.63#ibcon#about to read 6, iclass 31, count 0 2006.286.04:50:51.63#ibcon#read 6, iclass 31, count 0 2006.286.04:50:51.63#ibcon#end of sib2, iclass 31, count 0 2006.286.04:50:51.63#ibcon#*after write, iclass 31, count 0 2006.286.04:50:51.63#ibcon#*before return 0, iclass 31, count 0 2006.286.04:50:51.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:50:51.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:50:51.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:50:51.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:50:51.63$vck44/va=5,3 2006.286.04:50:51.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.04:50:51.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.04:50:51.63#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:51.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:50:51.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:50:51.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:50:51.69#ibcon#enter wrdev, iclass 33, count 2 2006.286.04:50:51.69#ibcon#first serial, iclass 33, count 2 2006.286.04:50:51.69#ibcon#enter sib2, iclass 33, count 2 2006.286.04:50:51.69#ibcon#flushed, iclass 33, count 2 2006.286.04:50:51.69#ibcon#about to write, iclass 33, count 2 2006.286.04:50:51.69#ibcon#wrote, iclass 33, count 2 2006.286.04:50:51.69#ibcon#about to read 3, iclass 33, count 2 2006.286.04:50:51.71#ibcon#read 3, iclass 33, count 2 2006.286.04:50:51.71#ibcon#about to read 4, iclass 33, count 2 2006.286.04:50:51.71#ibcon#read 4, iclass 33, count 2 2006.286.04:50:51.71#ibcon#about to read 5, iclass 33, count 2 2006.286.04:50:51.71#ibcon#read 5, iclass 33, count 2 2006.286.04:50:51.71#ibcon#about to read 6, iclass 33, count 2 2006.286.04:50:51.71#ibcon#read 6, iclass 33, count 2 2006.286.04:50:51.71#ibcon#end of sib2, iclass 33, count 2 2006.286.04:50:51.71#ibcon#*mode == 0, iclass 33, count 2 2006.286.04:50:51.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.04:50:51.71#ibcon#[25=AT05-03\r\n] 2006.286.04:50:51.71#ibcon#*before write, iclass 33, count 2 2006.286.04:50:51.71#ibcon#enter sib2, iclass 33, count 2 2006.286.04:50:51.71#ibcon#flushed, iclass 33, count 2 2006.286.04:50:51.71#ibcon#about to write, iclass 33, count 2 2006.286.04:50:51.71#ibcon#wrote, iclass 33, count 2 2006.286.04:50:51.71#ibcon#about to read 3, iclass 33, count 2 2006.286.04:50:51.74#ibcon#read 3, iclass 33, count 2 2006.286.04:50:51.74#ibcon#about to read 4, iclass 33, count 2 2006.286.04:50:51.74#ibcon#read 4, iclass 33, count 2 2006.286.04:50:51.74#ibcon#about to read 5, iclass 33, count 2 2006.286.04:50:51.74#ibcon#read 5, iclass 33, count 2 2006.286.04:50:51.74#ibcon#about to read 6, iclass 33, count 2 2006.286.04:50:51.74#ibcon#read 6, iclass 33, count 2 2006.286.04:50:51.74#ibcon#end of sib2, iclass 33, count 2 2006.286.04:50:51.74#ibcon#*after write, iclass 33, count 2 2006.286.04:50:51.74#ibcon#*before return 0, iclass 33, count 2 2006.286.04:50:51.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:50:51.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:50:51.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.04:50:51.74#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:51.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:50:51.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:50:51.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:50:51.86#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:50:51.86#ibcon#first serial, iclass 33, count 0 2006.286.04:50:51.86#ibcon#enter sib2, iclass 33, count 0 2006.286.04:50:51.86#ibcon#flushed, iclass 33, count 0 2006.286.04:50:51.86#ibcon#about to write, iclass 33, count 0 2006.286.04:50:51.86#ibcon#wrote, iclass 33, count 0 2006.286.04:50:51.86#ibcon#about to read 3, iclass 33, count 0 2006.286.04:50:51.88#ibcon#read 3, iclass 33, count 0 2006.286.04:50:51.88#ibcon#about to read 4, iclass 33, count 0 2006.286.04:50:51.88#ibcon#read 4, iclass 33, count 0 2006.286.04:50:51.88#ibcon#about to read 5, iclass 33, count 0 2006.286.04:50:51.88#ibcon#read 5, iclass 33, count 0 2006.286.04:50:51.88#ibcon#about to read 6, iclass 33, count 0 2006.286.04:50:51.88#ibcon#read 6, iclass 33, count 0 2006.286.04:50:51.88#ibcon#end of sib2, iclass 33, count 0 2006.286.04:50:51.88#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:50:51.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:50:51.88#ibcon#[25=USB\r\n] 2006.286.04:50:51.88#ibcon#*before write, iclass 33, count 0 2006.286.04:50:51.88#ibcon#enter sib2, iclass 33, count 0 2006.286.04:50:51.88#ibcon#flushed, iclass 33, count 0 2006.286.04:50:51.88#ibcon#about to write, iclass 33, count 0 2006.286.04:50:51.88#ibcon#wrote, iclass 33, count 0 2006.286.04:50:51.88#ibcon#about to read 3, iclass 33, count 0 2006.286.04:50:51.91#ibcon#read 3, iclass 33, count 0 2006.286.04:50:51.91#ibcon#about to read 4, iclass 33, count 0 2006.286.04:50:51.91#ibcon#read 4, iclass 33, count 0 2006.286.04:50:51.91#ibcon#about to read 5, iclass 33, count 0 2006.286.04:50:51.91#ibcon#read 5, iclass 33, count 0 2006.286.04:50:51.91#ibcon#about to read 6, iclass 33, count 0 2006.286.04:50:51.91#ibcon#read 6, iclass 33, count 0 2006.286.04:50:51.91#ibcon#end of sib2, iclass 33, count 0 2006.286.04:50:51.91#ibcon#*after write, iclass 33, count 0 2006.286.04:50:51.91#ibcon#*before return 0, iclass 33, count 0 2006.286.04:50:51.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:50:51.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:50:51.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:50:51.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:50:51.91$vck44/valo=6,814.99 2006.286.04:50:51.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.04:50:51.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.04:50:51.91#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:51.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:50:51.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:50:51.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:50:51.91#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:50:51.91#ibcon#first serial, iclass 35, count 0 2006.286.04:50:51.91#ibcon#enter sib2, iclass 35, count 0 2006.286.04:50:51.91#ibcon#flushed, iclass 35, count 0 2006.286.04:50:51.91#ibcon#about to write, iclass 35, count 0 2006.286.04:50:51.91#ibcon#wrote, iclass 35, count 0 2006.286.04:50:51.91#ibcon#about to read 3, iclass 35, count 0 2006.286.04:50:51.93#ibcon#read 3, iclass 35, count 0 2006.286.04:50:51.93#ibcon#about to read 4, iclass 35, count 0 2006.286.04:50:51.93#ibcon#read 4, iclass 35, count 0 2006.286.04:50:51.93#ibcon#about to read 5, iclass 35, count 0 2006.286.04:50:51.93#ibcon#read 5, iclass 35, count 0 2006.286.04:50:51.93#ibcon#about to read 6, iclass 35, count 0 2006.286.04:50:51.93#ibcon#read 6, iclass 35, count 0 2006.286.04:50:51.93#ibcon#end of sib2, iclass 35, count 0 2006.286.04:50:51.93#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:50:51.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:50:51.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:50:51.93#ibcon#*before write, iclass 35, count 0 2006.286.04:50:51.93#ibcon#enter sib2, iclass 35, count 0 2006.286.04:50:51.93#ibcon#flushed, iclass 35, count 0 2006.286.04:50:51.93#ibcon#about to write, iclass 35, count 0 2006.286.04:50:51.93#ibcon#wrote, iclass 35, count 0 2006.286.04:50:51.93#ibcon#about to read 3, iclass 35, count 0 2006.286.04:50:51.97#ibcon#read 3, iclass 35, count 0 2006.286.04:50:51.97#ibcon#about to read 4, iclass 35, count 0 2006.286.04:50:51.97#ibcon#read 4, iclass 35, count 0 2006.286.04:50:51.97#ibcon#about to read 5, iclass 35, count 0 2006.286.04:50:51.97#ibcon#read 5, iclass 35, count 0 2006.286.04:50:51.97#ibcon#about to read 6, iclass 35, count 0 2006.286.04:50:51.97#ibcon#read 6, iclass 35, count 0 2006.286.04:50:51.97#ibcon#end of sib2, iclass 35, count 0 2006.286.04:50:51.97#ibcon#*after write, iclass 35, count 0 2006.286.04:50:51.97#ibcon#*before return 0, iclass 35, count 0 2006.286.04:50:51.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:50:51.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:50:51.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:50:51.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:50:51.97$vck44/va=6,4 2006.286.04:50:51.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.04:50:51.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.04:50:51.97#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:51.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:50:52.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:50:52.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:50:52.03#ibcon#enter wrdev, iclass 37, count 2 2006.286.04:50:52.03#ibcon#first serial, iclass 37, count 2 2006.286.04:50:52.03#ibcon#enter sib2, iclass 37, count 2 2006.286.04:50:52.03#ibcon#flushed, iclass 37, count 2 2006.286.04:50:52.03#ibcon#about to write, iclass 37, count 2 2006.286.04:50:52.03#ibcon#wrote, iclass 37, count 2 2006.286.04:50:52.03#ibcon#about to read 3, iclass 37, count 2 2006.286.04:50:52.05#ibcon#read 3, iclass 37, count 2 2006.286.04:50:52.05#ibcon#about to read 4, iclass 37, count 2 2006.286.04:50:52.05#ibcon#read 4, iclass 37, count 2 2006.286.04:50:52.05#ibcon#about to read 5, iclass 37, count 2 2006.286.04:50:52.05#ibcon#read 5, iclass 37, count 2 2006.286.04:50:52.05#ibcon#about to read 6, iclass 37, count 2 2006.286.04:50:52.05#ibcon#read 6, iclass 37, count 2 2006.286.04:50:52.05#ibcon#end of sib2, iclass 37, count 2 2006.286.04:50:52.05#ibcon#*mode == 0, iclass 37, count 2 2006.286.04:50:52.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.04:50:52.05#ibcon#[25=AT06-04\r\n] 2006.286.04:50:52.05#ibcon#*before write, iclass 37, count 2 2006.286.04:50:52.05#ibcon#enter sib2, iclass 37, count 2 2006.286.04:50:52.05#ibcon#flushed, iclass 37, count 2 2006.286.04:50:52.05#ibcon#about to write, iclass 37, count 2 2006.286.04:50:52.05#ibcon#wrote, iclass 37, count 2 2006.286.04:50:52.05#ibcon#about to read 3, iclass 37, count 2 2006.286.04:50:52.08#ibcon#read 3, iclass 37, count 2 2006.286.04:50:52.08#ibcon#about to read 4, iclass 37, count 2 2006.286.04:50:52.08#ibcon#read 4, iclass 37, count 2 2006.286.04:50:52.08#ibcon#about to read 5, iclass 37, count 2 2006.286.04:50:52.08#ibcon#read 5, iclass 37, count 2 2006.286.04:50:52.08#ibcon#about to read 6, iclass 37, count 2 2006.286.04:50:52.08#ibcon#read 6, iclass 37, count 2 2006.286.04:50:52.08#ibcon#end of sib2, iclass 37, count 2 2006.286.04:50:52.08#ibcon#*after write, iclass 37, count 2 2006.286.04:50:52.08#ibcon#*before return 0, iclass 37, count 2 2006.286.04:50:52.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:50:52.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:50:52.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.04:50:52.08#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:52.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:50:52.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:50:52.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:50:52.20#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:50:52.20#ibcon#first serial, iclass 37, count 0 2006.286.04:50:52.20#ibcon#enter sib2, iclass 37, count 0 2006.286.04:50:52.20#ibcon#flushed, iclass 37, count 0 2006.286.04:50:52.20#ibcon#about to write, iclass 37, count 0 2006.286.04:50:52.20#ibcon#wrote, iclass 37, count 0 2006.286.04:50:52.20#ibcon#about to read 3, iclass 37, count 0 2006.286.04:50:52.22#ibcon#read 3, iclass 37, count 0 2006.286.04:50:52.22#ibcon#about to read 4, iclass 37, count 0 2006.286.04:50:52.22#ibcon#read 4, iclass 37, count 0 2006.286.04:50:52.22#ibcon#about to read 5, iclass 37, count 0 2006.286.04:50:52.22#ibcon#read 5, iclass 37, count 0 2006.286.04:50:52.22#ibcon#about to read 6, iclass 37, count 0 2006.286.04:50:52.25#ibcon#read 6, iclass 37, count 0 2006.286.04:50:52.25#ibcon#end of sib2, iclass 37, count 0 2006.286.04:50:52.25#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:50:52.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:50:52.25#ibcon#[25=USB\r\n] 2006.286.04:50:52.25#ibcon#*before write, iclass 37, count 0 2006.286.04:50:52.25#ibcon#enter sib2, iclass 37, count 0 2006.286.04:50:52.25#ibcon#flushed, iclass 37, count 0 2006.286.04:50:52.25#ibcon#about to write, iclass 37, count 0 2006.286.04:50:52.25#ibcon#wrote, iclass 37, count 0 2006.286.04:50:52.25#ibcon#about to read 3, iclass 37, count 0 2006.286.04:50:52.28#ibcon#read 3, iclass 37, count 0 2006.286.04:50:52.28#ibcon#about to read 4, iclass 37, count 0 2006.286.04:50:52.28#ibcon#read 4, iclass 37, count 0 2006.286.04:50:52.28#ibcon#about to read 5, iclass 37, count 0 2006.286.04:50:52.28#ibcon#read 5, iclass 37, count 0 2006.286.04:50:52.28#ibcon#about to read 6, iclass 37, count 0 2006.286.04:50:52.28#ibcon#read 6, iclass 37, count 0 2006.286.04:50:52.28#ibcon#end of sib2, iclass 37, count 0 2006.286.04:50:52.28#ibcon#*after write, iclass 37, count 0 2006.286.04:50:52.28#ibcon#*before return 0, iclass 37, count 0 2006.286.04:50:52.28#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:50:52.28#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:50:52.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:50:52.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:50:52.28$vck44/valo=7,864.99 2006.286.04:50:52.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.04:50:52.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.04:50:52.28#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:52.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:50:52.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:50:52.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:50:52.28#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:50:52.28#ibcon#first serial, iclass 39, count 0 2006.286.04:50:52.28#ibcon#enter sib2, iclass 39, count 0 2006.286.04:50:52.28#ibcon#flushed, iclass 39, count 0 2006.286.04:50:52.28#ibcon#about to write, iclass 39, count 0 2006.286.04:50:52.28#ibcon#wrote, iclass 39, count 0 2006.286.04:50:52.28#ibcon#about to read 3, iclass 39, count 0 2006.286.04:50:52.30#ibcon#read 3, iclass 39, count 0 2006.286.04:50:52.30#ibcon#about to read 4, iclass 39, count 0 2006.286.04:50:52.30#ibcon#read 4, iclass 39, count 0 2006.286.04:50:52.30#ibcon#about to read 5, iclass 39, count 0 2006.286.04:50:52.30#ibcon#read 5, iclass 39, count 0 2006.286.04:50:52.30#ibcon#about to read 6, iclass 39, count 0 2006.286.04:50:52.30#ibcon#read 6, iclass 39, count 0 2006.286.04:50:52.30#ibcon#end of sib2, iclass 39, count 0 2006.286.04:50:52.30#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:50:52.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:50:52.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:50:52.30#ibcon#*before write, iclass 39, count 0 2006.286.04:50:52.30#ibcon#enter sib2, iclass 39, count 0 2006.286.04:50:52.30#ibcon#flushed, iclass 39, count 0 2006.286.04:50:52.30#ibcon#about to write, iclass 39, count 0 2006.286.04:50:52.30#ibcon#wrote, iclass 39, count 0 2006.286.04:50:52.30#ibcon#about to read 3, iclass 39, count 0 2006.286.04:50:52.34#ibcon#read 3, iclass 39, count 0 2006.286.04:50:52.34#ibcon#about to read 4, iclass 39, count 0 2006.286.04:50:52.34#ibcon#read 4, iclass 39, count 0 2006.286.04:50:52.34#ibcon#about to read 5, iclass 39, count 0 2006.286.04:50:52.34#ibcon#read 5, iclass 39, count 0 2006.286.04:50:52.34#ibcon#about to read 6, iclass 39, count 0 2006.286.04:50:52.34#ibcon#read 6, iclass 39, count 0 2006.286.04:50:52.34#ibcon#end of sib2, iclass 39, count 0 2006.286.04:50:52.34#ibcon#*after write, iclass 39, count 0 2006.286.04:50:52.34#ibcon#*before return 0, iclass 39, count 0 2006.286.04:50:52.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:50:52.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:50:52.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:50:52.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:50:52.34$vck44/va=7,4 2006.286.04:50:52.34#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.04:50:52.34#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.04:50:52.34#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:52.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:50:52.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:50:52.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:50:52.40#ibcon#enter wrdev, iclass 3, count 2 2006.286.04:50:52.40#ibcon#first serial, iclass 3, count 2 2006.286.04:50:52.40#ibcon#enter sib2, iclass 3, count 2 2006.286.04:50:52.40#ibcon#flushed, iclass 3, count 2 2006.286.04:50:52.40#ibcon#about to write, iclass 3, count 2 2006.286.04:50:52.40#ibcon#wrote, iclass 3, count 2 2006.286.04:50:52.40#ibcon#about to read 3, iclass 3, count 2 2006.286.04:50:52.42#ibcon#read 3, iclass 3, count 2 2006.286.04:50:52.42#ibcon#about to read 4, iclass 3, count 2 2006.286.04:50:52.42#ibcon#read 4, iclass 3, count 2 2006.286.04:50:52.42#ibcon#about to read 5, iclass 3, count 2 2006.286.04:50:52.42#ibcon#read 5, iclass 3, count 2 2006.286.04:50:52.42#ibcon#about to read 6, iclass 3, count 2 2006.286.04:50:52.42#ibcon#read 6, iclass 3, count 2 2006.286.04:50:52.42#ibcon#end of sib2, iclass 3, count 2 2006.286.04:50:52.42#ibcon#*mode == 0, iclass 3, count 2 2006.286.04:50:52.42#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.04:50:52.42#ibcon#[25=AT07-04\r\n] 2006.286.04:50:52.42#ibcon#*before write, iclass 3, count 2 2006.286.04:50:52.42#ibcon#enter sib2, iclass 3, count 2 2006.286.04:50:52.42#ibcon#flushed, iclass 3, count 2 2006.286.04:50:52.42#ibcon#about to write, iclass 3, count 2 2006.286.04:50:52.42#ibcon#wrote, iclass 3, count 2 2006.286.04:50:52.42#ibcon#about to read 3, iclass 3, count 2 2006.286.04:50:52.45#ibcon#read 3, iclass 3, count 2 2006.286.04:50:52.45#ibcon#about to read 4, iclass 3, count 2 2006.286.04:50:52.45#ibcon#read 4, iclass 3, count 2 2006.286.04:50:52.45#ibcon#about to read 5, iclass 3, count 2 2006.286.04:50:52.45#ibcon#read 5, iclass 3, count 2 2006.286.04:50:52.45#ibcon#about to read 6, iclass 3, count 2 2006.286.04:50:52.45#ibcon#read 6, iclass 3, count 2 2006.286.04:50:52.45#ibcon#end of sib2, iclass 3, count 2 2006.286.04:50:52.45#ibcon#*after write, iclass 3, count 2 2006.286.04:50:52.45#ibcon#*before return 0, iclass 3, count 2 2006.286.04:50:52.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:50:52.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:50:52.45#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.04:50:52.45#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:52.45#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:50:52.57#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:50:52.57#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:50:52.57#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:50:52.57#ibcon#first serial, iclass 3, count 0 2006.286.04:50:52.57#ibcon#enter sib2, iclass 3, count 0 2006.286.04:50:52.57#ibcon#flushed, iclass 3, count 0 2006.286.04:50:52.57#ibcon#about to write, iclass 3, count 0 2006.286.04:50:52.57#ibcon#wrote, iclass 3, count 0 2006.286.04:50:52.57#ibcon#about to read 3, iclass 3, count 0 2006.286.04:50:52.59#ibcon#read 3, iclass 3, count 0 2006.286.04:50:52.59#ibcon#about to read 4, iclass 3, count 0 2006.286.04:50:52.59#ibcon#read 4, iclass 3, count 0 2006.286.04:50:52.59#ibcon#about to read 5, iclass 3, count 0 2006.286.04:50:52.59#ibcon#read 5, iclass 3, count 0 2006.286.04:50:52.59#ibcon#about to read 6, iclass 3, count 0 2006.286.04:50:52.59#ibcon#read 6, iclass 3, count 0 2006.286.04:50:52.59#ibcon#end of sib2, iclass 3, count 0 2006.286.04:50:52.59#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:50:52.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:50:52.59#ibcon#[25=USB\r\n] 2006.286.04:50:52.59#ibcon#*before write, iclass 3, count 0 2006.286.04:50:52.59#ibcon#enter sib2, iclass 3, count 0 2006.286.04:50:52.59#ibcon#flushed, iclass 3, count 0 2006.286.04:50:52.59#ibcon#about to write, iclass 3, count 0 2006.286.04:50:52.59#ibcon#wrote, iclass 3, count 0 2006.286.04:50:52.59#ibcon#about to read 3, iclass 3, count 0 2006.286.04:50:52.62#abcon#<5=/04 4.0 8.6 22.17 761014.8\r\n> 2006.286.04:50:52.62#ibcon#read 3, iclass 3, count 0 2006.286.04:50:52.62#ibcon#about to read 4, iclass 3, count 0 2006.286.04:50:52.62#ibcon#read 4, iclass 3, count 0 2006.286.04:50:52.62#ibcon#about to read 5, iclass 3, count 0 2006.286.04:50:52.62#ibcon#read 5, iclass 3, count 0 2006.286.04:50:52.62#ibcon#about to read 6, iclass 3, count 0 2006.286.04:50:52.62#ibcon#read 6, iclass 3, count 0 2006.286.04:50:52.62#ibcon#end of sib2, iclass 3, count 0 2006.286.04:50:52.62#ibcon#*after write, iclass 3, count 0 2006.286.04:50:52.62#ibcon#*before return 0, iclass 3, count 0 2006.286.04:50:52.62#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:50:52.62#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:50:52.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:50:52.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:50:52.62$vck44/valo=8,884.99 2006.286.04:50:52.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.04:50:52.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.04:50:52.62#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:52.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:50:52.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:50:52.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:50:52.62#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:50:52.62#ibcon#first serial, iclass 10, count 0 2006.286.04:50:52.62#ibcon#enter sib2, iclass 10, count 0 2006.286.04:50:52.62#ibcon#flushed, iclass 10, count 0 2006.286.04:50:52.62#ibcon#about to write, iclass 10, count 0 2006.286.04:50:52.62#ibcon#wrote, iclass 10, count 0 2006.286.04:50:52.62#ibcon#about to read 3, iclass 10, count 0 2006.286.04:50:52.64#abcon#{5=INTERFACE CLEAR} 2006.286.04:50:52.64#ibcon#read 3, iclass 10, count 0 2006.286.04:50:52.64#ibcon#about to read 4, iclass 10, count 0 2006.286.04:50:52.64#ibcon#read 4, iclass 10, count 0 2006.286.04:50:52.64#ibcon#about to read 5, iclass 10, count 0 2006.286.04:50:52.64#ibcon#read 5, iclass 10, count 0 2006.286.04:50:52.64#ibcon#about to read 6, iclass 10, count 0 2006.286.04:50:52.64#ibcon#read 6, iclass 10, count 0 2006.286.04:50:52.64#ibcon#end of sib2, iclass 10, count 0 2006.286.04:50:52.64#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:50:52.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:50:52.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:50:52.64#ibcon#*before write, iclass 10, count 0 2006.286.04:50:52.64#ibcon#enter sib2, iclass 10, count 0 2006.286.04:50:52.64#ibcon#flushed, iclass 10, count 0 2006.286.04:50:52.64#ibcon#about to write, iclass 10, count 0 2006.286.04:50:52.64#ibcon#wrote, iclass 10, count 0 2006.286.04:50:52.64#ibcon#about to read 3, iclass 10, count 0 2006.286.04:50:52.68#ibcon#read 3, iclass 10, count 0 2006.286.04:50:52.68#ibcon#about to read 4, iclass 10, count 0 2006.286.04:50:52.68#ibcon#read 4, iclass 10, count 0 2006.286.04:50:52.68#ibcon#about to read 5, iclass 10, count 0 2006.286.04:50:52.68#ibcon#read 5, iclass 10, count 0 2006.286.04:50:52.68#ibcon#about to read 6, iclass 10, count 0 2006.286.04:50:52.68#ibcon#read 6, iclass 10, count 0 2006.286.04:50:52.68#ibcon#end of sib2, iclass 10, count 0 2006.286.04:50:52.68#ibcon#*after write, iclass 10, count 0 2006.286.04:50:52.68#ibcon#*before return 0, iclass 10, count 0 2006.286.04:50:52.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:50:52.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:50:52.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:50:52.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:50:52.68$vck44/va=8,3 2006.286.04:50:52.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.04:50:52.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.04:50:52.68#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:52.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:50:52.70#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:50:52.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:50:52.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:50:52.74#ibcon#enter wrdev, iclass 13, count 2 2006.286.04:50:52.74#ibcon#first serial, iclass 13, count 2 2006.286.04:50:52.74#ibcon#enter sib2, iclass 13, count 2 2006.286.04:50:52.74#ibcon#flushed, iclass 13, count 2 2006.286.04:50:52.74#ibcon#about to write, iclass 13, count 2 2006.286.04:50:52.74#ibcon#wrote, iclass 13, count 2 2006.286.04:50:52.74#ibcon#about to read 3, iclass 13, count 2 2006.286.04:50:52.76#ibcon#read 3, iclass 13, count 2 2006.286.04:50:52.76#ibcon#about to read 4, iclass 13, count 2 2006.286.04:50:52.76#ibcon#read 4, iclass 13, count 2 2006.286.04:50:52.76#ibcon#about to read 5, iclass 13, count 2 2006.286.04:50:52.76#ibcon#read 5, iclass 13, count 2 2006.286.04:50:52.76#ibcon#about to read 6, iclass 13, count 2 2006.286.04:50:52.76#ibcon#read 6, iclass 13, count 2 2006.286.04:50:52.76#ibcon#end of sib2, iclass 13, count 2 2006.286.04:50:52.76#ibcon#*mode == 0, iclass 13, count 2 2006.286.04:50:52.76#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.04:50:52.76#ibcon#[25=AT08-03\r\n] 2006.286.04:50:52.76#ibcon#*before write, iclass 13, count 2 2006.286.04:50:52.76#ibcon#enter sib2, iclass 13, count 2 2006.286.04:50:52.76#ibcon#flushed, iclass 13, count 2 2006.286.04:50:52.76#ibcon#about to write, iclass 13, count 2 2006.286.04:50:52.76#ibcon#wrote, iclass 13, count 2 2006.286.04:50:52.76#ibcon#about to read 3, iclass 13, count 2 2006.286.04:50:52.79#ibcon#read 3, iclass 13, count 2 2006.286.04:50:52.79#ibcon#about to read 4, iclass 13, count 2 2006.286.04:50:52.79#ibcon#read 4, iclass 13, count 2 2006.286.04:50:52.79#ibcon#about to read 5, iclass 13, count 2 2006.286.04:50:52.79#ibcon#read 5, iclass 13, count 2 2006.286.04:50:52.79#ibcon#about to read 6, iclass 13, count 2 2006.286.04:50:52.79#ibcon#read 6, iclass 13, count 2 2006.286.04:50:52.79#ibcon#end of sib2, iclass 13, count 2 2006.286.04:50:52.79#ibcon#*after write, iclass 13, count 2 2006.286.04:50:52.79#ibcon#*before return 0, iclass 13, count 2 2006.286.04:50:52.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:50:52.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.04:50:52.79#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.04:50:52.79#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:52.79#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:50:52.91#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:50:52.91#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:50:52.91#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:50:52.91#ibcon#first serial, iclass 13, count 0 2006.286.04:50:52.91#ibcon#enter sib2, iclass 13, count 0 2006.286.04:50:52.91#ibcon#flushed, iclass 13, count 0 2006.286.04:50:52.91#ibcon#about to write, iclass 13, count 0 2006.286.04:50:52.91#ibcon#wrote, iclass 13, count 0 2006.286.04:50:52.91#ibcon#about to read 3, iclass 13, count 0 2006.286.04:50:52.93#ibcon#read 3, iclass 13, count 0 2006.286.04:50:52.93#ibcon#about to read 4, iclass 13, count 0 2006.286.04:50:52.93#ibcon#read 4, iclass 13, count 0 2006.286.04:50:52.93#ibcon#about to read 5, iclass 13, count 0 2006.286.04:50:52.93#ibcon#read 5, iclass 13, count 0 2006.286.04:50:52.93#ibcon#about to read 6, iclass 13, count 0 2006.286.04:50:52.93#ibcon#read 6, iclass 13, count 0 2006.286.04:50:52.93#ibcon#end of sib2, iclass 13, count 0 2006.286.04:50:52.93#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:50:52.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:50:52.93#ibcon#[25=USB\r\n] 2006.286.04:50:52.93#ibcon#*before write, iclass 13, count 0 2006.286.04:50:52.93#ibcon#enter sib2, iclass 13, count 0 2006.286.04:50:52.93#ibcon#flushed, iclass 13, count 0 2006.286.04:50:52.93#ibcon#about to write, iclass 13, count 0 2006.286.04:50:52.93#ibcon#wrote, iclass 13, count 0 2006.286.04:50:52.93#ibcon#about to read 3, iclass 13, count 0 2006.286.04:50:52.96#ibcon#read 3, iclass 13, count 0 2006.286.04:50:52.96#ibcon#about to read 4, iclass 13, count 0 2006.286.04:50:52.96#ibcon#read 4, iclass 13, count 0 2006.286.04:50:52.96#ibcon#about to read 5, iclass 13, count 0 2006.286.04:50:52.96#ibcon#read 5, iclass 13, count 0 2006.286.04:50:52.96#ibcon#about to read 6, iclass 13, count 0 2006.286.04:50:52.96#ibcon#read 6, iclass 13, count 0 2006.286.04:50:52.96#ibcon#end of sib2, iclass 13, count 0 2006.286.04:50:52.96#ibcon#*after write, iclass 13, count 0 2006.286.04:50:52.96#ibcon#*before return 0, iclass 13, count 0 2006.286.04:50:52.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:50:52.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.04:50:52.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:50:52.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:50:52.96$vck44/vblo=1,629.99 2006.286.04:50:52.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.04:50:52.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.04:50:52.96#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:52.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:50:52.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:50:52.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:50:52.96#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:50:52.96#ibcon#first serial, iclass 15, count 0 2006.286.04:50:52.96#ibcon#enter sib2, iclass 15, count 0 2006.286.04:50:52.96#ibcon#flushed, iclass 15, count 0 2006.286.04:50:52.96#ibcon#about to write, iclass 15, count 0 2006.286.04:50:52.96#ibcon#wrote, iclass 15, count 0 2006.286.04:50:52.96#ibcon#about to read 3, iclass 15, count 0 2006.286.04:50:52.98#ibcon#read 3, iclass 15, count 0 2006.286.04:50:52.98#ibcon#about to read 4, iclass 15, count 0 2006.286.04:50:52.98#ibcon#read 4, iclass 15, count 0 2006.286.04:50:52.98#ibcon#about to read 5, iclass 15, count 0 2006.286.04:50:52.98#ibcon#read 5, iclass 15, count 0 2006.286.04:50:52.98#ibcon#about to read 6, iclass 15, count 0 2006.286.04:50:52.98#ibcon#read 6, iclass 15, count 0 2006.286.04:50:52.98#ibcon#end of sib2, iclass 15, count 0 2006.286.04:50:52.98#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:50:52.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:50:52.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:50:52.98#ibcon#*before write, iclass 15, count 0 2006.286.04:50:52.98#ibcon#enter sib2, iclass 15, count 0 2006.286.04:50:52.98#ibcon#flushed, iclass 15, count 0 2006.286.04:50:52.98#ibcon#about to write, iclass 15, count 0 2006.286.04:50:52.98#ibcon#wrote, iclass 15, count 0 2006.286.04:50:52.98#ibcon#about to read 3, iclass 15, count 0 2006.286.04:50:53.02#ibcon#read 3, iclass 15, count 0 2006.286.04:50:53.02#ibcon#about to read 4, iclass 15, count 0 2006.286.04:50:53.02#ibcon#read 4, iclass 15, count 0 2006.286.04:50:53.02#ibcon#about to read 5, iclass 15, count 0 2006.286.04:50:53.02#ibcon#read 5, iclass 15, count 0 2006.286.04:50:53.02#ibcon#about to read 6, iclass 15, count 0 2006.286.04:50:53.02#ibcon#read 6, iclass 15, count 0 2006.286.04:50:53.02#ibcon#end of sib2, iclass 15, count 0 2006.286.04:50:53.02#ibcon#*after write, iclass 15, count 0 2006.286.04:50:53.02#ibcon#*before return 0, iclass 15, count 0 2006.286.04:50:53.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:50:53.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.04:50:53.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:50:53.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:50:53.02$vck44/vb=1,4 2006.286.04:50:53.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.04:50:53.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.04:50:53.02#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:53.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:50:53.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:50:53.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:50:53.02#ibcon#enter wrdev, iclass 17, count 2 2006.286.04:50:53.02#ibcon#first serial, iclass 17, count 2 2006.286.04:50:53.02#ibcon#enter sib2, iclass 17, count 2 2006.286.04:50:53.02#ibcon#flushed, iclass 17, count 2 2006.286.04:50:53.02#ibcon#about to write, iclass 17, count 2 2006.286.04:50:53.02#ibcon#wrote, iclass 17, count 2 2006.286.04:50:53.02#ibcon#about to read 3, iclass 17, count 2 2006.286.04:50:53.04#ibcon#read 3, iclass 17, count 2 2006.286.04:50:53.04#ibcon#about to read 4, iclass 17, count 2 2006.286.04:50:53.04#ibcon#read 4, iclass 17, count 2 2006.286.04:50:53.04#ibcon#about to read 5, iclass 17, count 2 2006.286.04:50:53.04#ibcon#read 5, iclass 17, count 2 2006.286.04:50:53.04#ibcon#about to read 6, iclass 17, count 2 2006.286.04:50:53.04#ibcon#read 6, iclass 17, count 2 2006.286.04:50:53.04#ibcon#end of sib2, iclass 17, count 2 2006.286.04:50:53.04#ibcon#*mode == 0, iclass 17, count 2 2006.286.04:50:53.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.04:50:53.04#ibcon#[27=AT01-04\r\n] 2006.286.04:50:53.04#ibcon#*before write, iclass 17, count 2 2006.286.04:50:53.04#ibcon#enter sib2, iclass 17, count 2 2006.286.04:50:53.04#ibcon#flushed, iclass 17, count 2 2006.286.04:50:53.04#ibcon#about to write, iclass 17, count 2 2006.286.04:50:53.04#ibcon#wrote, iclass 17, count 2 2006.286.04:50:53.04#ibcon#about to read 3, iclass 17, count 2 2006.286.04:50:53.07#ibcon#read 3, iclass 17, count 2 2006.286.04:50:53.07#ibcon#about to read 4, iclass 17, count 2 2006.286.04:50:53.07#ibcon#read 4, iclass 17, count 2 2006.286.04:50:53.07#ibcon#about to read 5, iclass 17, count 2 2006.286.04:50:53.07#ibcon#read 5, iclass 17, count 2 2006.286.04:50:53.07#ibcon#about to read 6, iclass 17, count 2 2006.286.04:50:53.07#ibcon#read 6, iclass 17, count 2 2006.286.04:50:53.07#ibcon#end of sib2, iclass 17, count 2 2006.286.04:50:53.07#ibcon#*after write, iclass 17, count 2 2006.286.04:50:53.07#ibcon#*before return 0, iclass 17, count 2 2006.286.04:50:53.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:50:53.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.04:50:53.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.04:50:53.07#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:53.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:50:53.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:50:53.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:50:53.19#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:50:53.19#ibcon#first serial, iclass 17, count 0 2006.286.04:50:53.19#ibcon#enter sib2, iclass 17, count 0 2006.286.04:50:53.19#ibcon#flushed, iclass 17, count 0 2006.286.04:50:53.19#ibcon#about to write, iclass 17, count 0 2006.286.04:50:53.19#ibcon#wrote, iclass 17, count 0 2006.286.04:50:53.19#ibcon#about to read 3, iclass 17, count 0 2006.286.04:50:53.21#ibcon#read 3, iclass 17, count 0 2006.286.04:50:53.21#ibcon#about to read 4, iclass 17, count 0 2006.286.04:50:53.21#ibcon#read 4, iclass 17, count 0 2006.286.04:50:53.21#ibcon#about to read 5, iclass 17, count 0 2006.286.04:50:53.21#ibcon#read 5, iclass 17, count 0 2006.286.04:50:53.21#ibcon#about to read 6, iclass 17, count 0 2006.286.04:50:53.21#ibcon#read 6, iclass 17, count 0 2006.286.04:50:53.21#ibcon#end of sib2, iclass 17, count 0 2006.286.04:50:53.21#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:50:53.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:50:53.21#ibcon#[27=USB\r\n] 2006.286.04:50:53.21#ibcon#*before write, iclass 17, count 0 2006.286.04:50:53.21#ibcon#enter sib2, iclass 17, count 0 2006.286.04:50:53.21#ibcon#flushed, iclass 17, count 0 2006.286.04:50:53.21#ibcon#about to write, iclass 17, count 0 2006.286.04:50:53.21#ibcon#wrote, iclass 17, count 0 2006.286.04:50:53.21#ibcon#about to read 3, iclass 17, count 0 2006.286.04:50:53.24#ibcon#read 3, iclass 17, count 0 2006.286.04:50:53.24#ibcon#about to read 4, iclass 17, count 0 2006.286.04:50:53.24#ibcon#read 4, iclass 17, count 0 2006.286.04:50:53.24#ibcon#about to read 5, iclass 17, count 0 2006.286.04:50:53.24#ibcon#read 5, iclass 17, count 0 2006.286.04:50:53.24#ibcon#about to read 6, iclass 17, count 0 2006.286.04:50:53.24#ibcon#read 6, iclass 17, count 0 2006.286.04:50:53.24#ibcon#end of sib2, iclass 17, count 0 2006.286.04:50:53.24#ibcon#*after write, iclass 17, count 0 2006.286.04:50:53.24#ibcon#*before return 0, iclass 17, count 0 2006.286.04:50:53.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:50:53.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.04:50:53.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:50:53.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:50:53.24$vck44/vblo=2,634.99 2006.286.04:50:53.32#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.04:50:53.32#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.04:50:53.32#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:53.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:50:53.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:50:53.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:50:53.32#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:50:53.32#ibcon#first serial, iclass 19, count 0 2006.286.04:50:53.32#ibcon#enter sib2, iclass 19, count 0 2006.286.04:50:53.32#ibcon#flushed, iclass 19, count 0 2006.286.04:50:53.32#ibcon#about to write, iclass 19, count 0 2006.286.04:50:53.32#ibcon#wrote, iclass 19, count 0 2006.286.04:50:53.32#ibcon#about to read 3, iclass 19, count 0 2006.286.04:50:53.34#ibcon#read 3, iclass 19, count 0 2006.286.04:50:53.34#ibcon#about to read 4, iclass 19, count 0 2006.286.04:50:53.34#ibcon#read 4, iclass 19, count 0 2006.286.04:50:53.34#ibcon#about to read 5, iclass 19, count 0 2006.286.04:50:53.34#ibcon#read 5, iclass 19, count 0 2006.286.04:50:53.34#ibcon#about to read 6, iclass 19, count 0 2006.286.04:50:53.34#ibcon#read 6, iclass 19, count 0 2006.286.04:50:53.34#ibcon#end of sib2, iclass 19, count 0 2006.286.04:50:53.34#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:50:53.34#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:50:53.34#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:50:53.34#ibcon#*before write, iclass 19, count 0 2006.286.04:50:53.34#ibcon#enter sib2, iclass 19, count 0 2006.286.04:50:53.34#ibcon#flushed, iclass 19, count 0 2006.286.04:50:53.34#ibcon#about to write, iclass 19, count 0 2006.286.04:50:53.34#ibcon#wrote, iclass 19, count 0 2006.286.04:50:53.34#ibcon#about to read 3, iclass 19, count 0 2006.286.04:50:53.38#ibcon#read 3, iclass 19, count 0 2006.286.04:50:53.38#ibcon#about to read 4, iclass 19, count 0 2006.286.04:50:53.38#ibcon#read 4, iclass 19, count 0 2006.286.04:50:53.38#ibcon#about to read 5, iclass 19, count 0 2006.286.04:50:53.38#ibcon#read 5, iclass 19, count 0 2006.286.04:50:53.38#ibcon#about to read 6, iclass 19, count 0 2006.286.04:50:53.38#ibcon#read 6, iclass 19, count 0 2006.286.04:50:53.38#ibcon#end of sib2, iclass 19, count 0 2006.286.04:50:53.38#ibcon#*after write, iclass 19, count 0 2006.286.04:50:53.38#ibcon#*before return 0, iclass 19, count 0 2006.286.04:50:53.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:50:53.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.04:50:53.38#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:50:53.38#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:50:53.38$vck44/vb=2,5 2006.286.04:50:53.38#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.04:50:53.38#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.04:50:53.38#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:53.38#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:50:53.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:50:53.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:50:53.38#ibcon#enter wrdev, iclass 21, count 2 2006.286.04:50:53.38#ibcon#first serial, iclass 21, count 2 2006.286.04:50:53.38#ibcon#enter sib2, iclass 21, count 2 2006.286.04:50:53.38#ibcon#flushed, iclass 21, count 2 2006.286.04:50:53.38#ibcon#about to write, iclass 21, count 2 2006.286.04:50:53.38#ibcon#wrote, iclass 21, count 2 2006.286.04:50:53.38#ibcon#about to read 3, iclass 21, count 2 2006.286.04:50:53.40#ibcon#read 3, iclass 21, count 2 2006.286.04:50:53.40#ibcon#about to read 4, iclass 21, count 2 2006.286.04:50:53.40#ibcon#read 4, iclass 21, count 2 2006.286.04:50:53.40#ibcon#about to read 5, iclass 21, count 2 2006.286.04:50:53.40#ibcon#read 5, iclass 21, count 2 2006.286.04:50:53.40#ibcon#about to read 6, iclass 21, count 2 2006.286.04:50:53.40#ibcon#read 6, iclass 21, count 2 2006.286.04:50:53.40#ibcon#end of sib2, iclass 21, count 2 2006.286.04:50:53.40#ibcon#*mode == 0, iclass 21, count 2 2006.286.04:50:53.40#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.04:50:53.40#ibcon#[27=AT02-05\r\n] 2006.286.04:50:53.40#ibcon#*before write, iclass 21, count 2 2006.286.04:50:53.40#ibcon#enter sib2, iclass 21, count 2 2006.286.04:50:53.40#ibcon#flushed, iclass 21, count 2 2006.286.04:50:53.40#ibcon#about to write, iclass 21, count 2 2006.286.04:50:53.40#ibcon#wrote, iclass 21, count 2 2006.286.04:50:53.40#ibcon#about to read 3, iclass 21, count 2 2006.286.04:50:53.43#ibcon#read 3, iclass 21, count 2 2006.286.04:50:53.43#ibcon#about to read 4, iclass 21, count 2 2006.286.04:50:53.43#ibcon#read 4, iclass 21, count 2 2006.286.04:50:53.43#ibcon#about to read 5, iclass 21, count 2 2006.286.04:50:53.43#ibcon#read 5, iclass 21, count 2 2006.286.04:50:53.43#ibcon#about to read 6, iclass 21, count 2 2006.286.04:50:53.43#ibcon#read 6, iclass 21, count 2 2006.286.04:50:53.43#ibcon#end of sib2, iclass 21, count 2 2006.286.04:50:53.43#ibcon#*after write, iclass 21, count 2 2006.286.04:50:53.43#ibcon#*before return 0, iclass 21, count 2 2006.286.04:50:53.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:50:53.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.04:50:53.43#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.04:50:53.43#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:53.43#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:50:53.55#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:50:53.55#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:50:53.55#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:50:53.55#ibcon#first serial, iclass 21, count 0 2006.286.04:50:53.55#ibcon#enter sib2, iclass 21, count 0 2006.286.04:50:53.55#ibcon#flushed, iclass 21, count 0 2006.286.04:50:53.55#ibcon#about to write, iclass 21, count 0 2006.286.04:50:53.55#ibcon#wrote, iclass 21, count 0 2006.286.04:50:53.55#ibcon#about to read 3, iclass 21, count 0 2006.286.04:50:53.57#ibcon#read 3, iclass 21, count 0 2006.286.04:50:53.57#ibcon#about to read 4, iclass 21, count 0 2006.286.04:50:53.57#ibcon#read 4, iclass 21, count 0 2006.286.04:50:53.57#ibcon#about to read 5, iclass 21, count 0 2006.286.04:50:53.57#ibcon#read 5, iclass 21, count 0 2006.286.04:50:53.57#ibcon#about to read 6, iclass 21, count 0 2006.286.04:50:53.57#ibcon#read 6, iclass 21, count 0 2006.286.04:50:53.57#ibcon#end of sib2, iclass 21, count 0 2006.286.04:50:53.57#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:50:53.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:50:53.57#ibcon#[27=USB\r\n] 2006.286.04:50:53.57#ibcon#*before write, iclass 21, count 0 2006.286.04:50:53.57#ibcon#enter sib2, iclass 21, count 0 2006.286.04:50:53.57#ibcon#flushed, iclass 21, count 0 2006.286.04:50:53.57#ibcon#about to write, iclass 21, count 0 2006.286.04:50:53.57#ibcon#wrote, iclass 21, count 0 2006.286.04:50:53.57#ibcon#about to read 3, iclass 21, count 0 2006.286.04:50:53.60#ibcon#read 3, iclass 21, count 0 2006.286.04:50:53.60#ibcon#about to read 4, iclass 21, count 0 2006.286.04:50:53.60#ibcon#read 4, iclass 21, count 0 2006.286.04:50:53.60#ibcon#about to read 5, iclass 21, count 0 2006.286.04:50:53.60#ibcon#read 5, iclass 21, count 0 2006.286.04:50:53.60#ibcon#about to read 6, iclass 21, count 0 2006.286.04:50:53.60#ibcon#read 6, iclass 21, count 0 2006.286.04:50:53.60#ibcon#end of sib2, iclass 21, count 0 2006.286.04:50:53.60#ibcon#*after write, iclass 21, count 0 2006.286.04:50:53.60#ibcon#*before return 0, iclass 21, count 0 2006.286.04:50:53.60#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:50:53.60#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.04:50:53.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:50:53.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:50:53.60$vck44/vblo=3,649.99 2006.286.04:50:53.60#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.04:50:53.60#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.04:50:53.60#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:53.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:50:53.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:50:53.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:50:53.60#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:50:53.60#ibcon#first serial, iclass 23, count 0 2006.286.04:50:53.60#ibcon#enter sib2, iclass 23, count 0 2006.286.04:50:53.60#ibcon#flushed, iclass 23, count 0 2006.286.04:50:53.60#ibcon#about to write, iclass 23, count 0 2006.286.04:50:53.60#ibcon#wrote, iclass 23, count 0 2006.286.04:50:53.60#ibcon#about to read 3, iclass 23, count 0 2006.286.04:50:53.62#ibcon#read 3, iclass 23, count 0 2006.286.04:50:53.62#ibcon#about to read 4, iclass 23, count 0 2006.286.04:50:53.62#ibcon#read 4, iclass 23, count 0 2006.286.04:50:53.62#ibcon#about to read 5, iclass 23, count 0 2006.286.04:50:53.62#ibcon#read 5, iclass 23, count 0 2006.286.04:50:53.62#ibcon#about to read 6, iclass 23, count 0 2006.286.04:50:53.62#ibcon#read 6, iclass 23, count 0 2006.286.04:50:53.62#ibcon#end of sib2, iclass 23, count 0 2006.286.04:50:53.62#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:50:53.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:50:53.62#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:50:53.62#ibcon#*before write, iclass 23, count 0 2006.286.04:50:53.62#ibcon#enter sib2, iclass 23, count 0 2006.286.04:50:53.62#ibcon#flushed, iclass 23, count 0 2006.286.04:50:53.62#ibcon#about to write, iclass 23, count 0 2006.286.04:50:53.62#ibcon#wrote, iclass 23, count 0 2006.286.04:50:53.62#ibcon#about to read 3, iclass 23, count 0 2006.286.04:50:53.66#ibcon#read 3, iclass 23, count 0 2006.286.04:50:53.66#ibcon#about to read 4, iclass 23, count 0 2006.286.04:50:53.66#ibcon#read 4, iclass 23, count 0 2006.286.04:50:53.66#ibcon#about to read 5, iclass 23, count 0 2006.286.04:50:53.66#ibcon#read 5, iclass 23, count 0 2006.286.04:50:53.66#ibcon#about to read 6, iclass 23, count 0 2006.286.04:50:53.66#ibcon#read 6, iclass 23, count 0 2006.286.04:50:53.66#ibcon#end of sib2, iclass 23, count 0 2006.286.04:50:53.66#ibcon#*after write, iclass 23, count 0 2006.286.04:50:53.66#ibcon#*before return 0, iclass 23, count 0 2006.286.04:50:53.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:50:53.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.04:50:53.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:50:53.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:50:53.66$vck44/vb=3,4 2006.286.04:50:53.66#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.04:50:53.66#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.04:50:53.66#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:53.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:50:53.72#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:50:53.72#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:50:53.72#ibcon#enter wrdev, iclass 25, count 2 2006.286.04:50:53.72#ibcon#first serial, iclass 25, count 2 2006.286.04:50:53.72#ibcon#enter sib2, iclass 25, count 2 2006.286.04:50:53.72#ibcon#flushed, iclass 25, count 2 2006.286.04:50:53.72#ibcon#about to write, iclass 25, count 2 2006.286.04:50:53.72#ibcon#wrote, iclass 25, count 2 2006.286.04:50:53.72#ibcon#about to read 3, iclass 25, count 2 2006.286.04:50:53.74#ibcon#read 3, iclass 25, count 2 2006.286.04:50:53.74#ibcon#about to read 4, iclass 25, count 2 2006.286.04:50:53.74#ibcon#read 4, iclass 25, count 2 2006.286.04:50:53.74#ibcon#about to read 5, iclass 25, count 2 2006.286.04:50:53.74#ibcon#read 5, iclass 25, count 2 2006.286.04:50:53.74#ibcon#about to read 6, iclass 25, count 2 2006.286.04:50:53.74#ibcon#read 6, iclass 25, count 2 2006.286.04:50:53.74#ibcon#end of sib2, iclass 25, count 2 2006.286.04:50:53.74#ibcon#*mode == 0, iclass 25, count 2 2006.286.04:50:53.74#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.04:50:53.74#ibcon#[27=AT03-04\r\n] 2006.286.04:50:53.74#ibcon#*before write, iclass 25, count 2 2006.286.04:50:53.74#ibcon#enter sib2, iclass 25, count 2 2006.286.04:50:53.74#ibcon#flushed, iclass 25, count 2 2006.286.04:50:53.74#ibcon#about to write, iclass 25, count 2 2006.286.04:50:53.74#ibcon#wrote, iclass 25, count 2 2006.286.04:50:53.74#ibcon#about to read 3, iclass 25, count 2 2006.286.04:50:53.77#ibcon#read 3, iclass 25, count 2 2006.286.04:50:53.77#ibcon#about to read 4, iclass 25, count 2 2006.286.04:50:53.77#ibcon#read 4, iclass 25, count 2 2006.286.04:50:53.77#ibcon#about to read 5, iclass 25, count 2 2006.286.04:50:53.77#ibcon#read 5, iclass 25, count 2 2006.286.04:50:53.77#ibcon#about to read 6, iclass 25, count 2 2006.286.04:50:53.77#ibcon#read 6, iclass 25, count 2 2006.286.04:50:53.77#ibcon#end of sib2, iclass 25, count 2 2006.286.04:50:53.77#ibcon#*after write, iclass 25, count 2 2006.286.04:50:53.77#ibcon#*before return 0, iclass 25, count 2 2006.286.04:50:53.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:50:53.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:50:53.77#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.04:50:53.77#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:53.77#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:50:53.89#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:50:53.89#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:50:53.89#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:50:53.89#ibcon#first serial, iclass 25, count 0 2006.286.04:50:53.89#ibcon#enter sib2, iclass 25, count 0 2006.286.04:50:53.89#ibcon#flushed, iclass 25, count 0 2006.286.04:50:53.89#ibcon#about to write, iclass 25, count 0 2006.286.04:50:53.89#ibcon#wrote, iclass 25, count 0 2006.286.04:50:53.89#ibcon#about to read 3, iclass 25, count 0 2006.286.04:50:53.91#ibcon#read 3, iclass 25, count 0 2006.286.04:50:53.91#ibcon#about to read 4, iclass 25, count 0 2006.286.04:50:53.91#ibcon#read 4, iclass 25, count 0 2006.286.04:50:53.91#ibcon#about to read 5, iclass 25, count 0 2006.286.04:50:53.91#ibcon#read 5, iclass 25, count 0 2006.286.04:50:53.91#ibcon#about to read 6, iclass 25, count 0 2006.286.04:50:53.91#ibcon#read 6, iclass 25, count 0 2006.286.04:50:53.91#ibcon#end of sib2, iclass 25, count 0 2006.286.04:50:53.91#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:50:53.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:50:53.91#ibcon#[27=USB\r\n] 2006.286.04:50:53.91#ibcon#*before write, iclass 25, count 0 2006.286.04:50:53.91#ibcon#enter sib2, iclass 25, count 0 2006.286.04:50:53.91#ibcon#flushed, iclass 25, count 0 2006.286.04:50:53.91#ibcon#about to write, iclass 25, count 0 2006.286.04:50:53.91#ibcon#wrote, iclass 25, count 0 2006.286.04:50:53.91#ibcon#about to read 3, iclass 25, count 0 2006.286.04:50:53.94#ibcon#read 3, iclass 25, count 0 2006.286.04:50:53.94#ibcon#about to read 4, iclass 25, count 0 2006.286.04:50:53.94#ibcon#read 4, iclass 25, count 0 2006.286.04:50:53.94#ibcon#about to read 5, iclass 25, count 0 2006.286.04:50:53.94#ibcon#read 5, iclass 25, count 0 2006.286.04:50:53.94#ibcon#about to read 6, iclass 25, count 0 2006.286.04:50:53.94#ibcon#read 6, iclass 25, count 0 2006.286.04:50:53.94#ibcon#end of sib2, iclass 25, count 0 2006.286.04:50:53.94#ibcon#*after write, iclass 25, count 0 2006.286.04:50:53.94#ibcon#*before return 0, iclass 25, count 0 2006.286.04:50:53.94#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:50:53.94#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:50:53.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:50:53.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:50:53.94$vck44/vblo=4,679.99 2006.286.04:50:53.94#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.04:50:53.94#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.04:50:53.94#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:53.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:50:53.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:50:53.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:50:53.94#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:50:53.94#ibcon#first serial, iclass 27, count 0 2006.286.04:50:53.94#ibcon#enter sib2, iclass 27, count 0 2006.286.04:50:53.94#ibcon#flushed, iclass 27, count 0 2006.286.04:50:53.94#ibcon#about to write, iclass 27, count 0 2006.286.04:50:53.94#ibcon#wrote, iclass 27, count 0 2006.286.04:50:53.94#ibcon#about to read 3, iclass 27, count 0 2006.286.04:50:53.96#ibcon#read 3, iclass 27, count 0 2006.286.04:50:53.96#ibcon#about to read 4, iclass 27, count 0 2006.286.04:50:53.96#ibcon#read 4, iclass 27, count 0 2006.286.04:50:53.96#ibcon#about to read 5, iclass 27, count 0 2006.286.04:50:53.96#ibcon#read 5, iclass 27, count 0 2006.286.04:50:53.96#ibcon#about to read 6, iclass 27, count 0 2006.286.04:50:53.96#ibcon#read 6, iclass 27, count 0 2006.286.04:50:53.96#ibcon#end of sib2, iclass 27, count 0 2006.286.04:50:53.96#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:50:53.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:50:53.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:50:53.96#ibcon#*before write, iclass 27, count 0 2006.286.04:50:53.96#ibcon#enter sib2, iclass 27, count 0 2006.286.04:50:53.96#ibcon#flushed, iclass 27, count 0 2006.286.04:50:53.96#ibcon#about to write, iclass 27, count 0 2006.286.04:50:53.96#ibcon#wrote, iclass 27, count 0 2006.286.04:50:53.96#ibcon#about to read 3, iclass 27, count 0 2006.286.04:50:54.00#ibcon#read 3, iclass 27, count 0 2006.286.04:50:54.00#ibcon#about to read 4, iclass 27, count 0 2006.286.04:50:54.00#ibcon#read 4, iclass 27, count 0 2006.286.04:50:54.00#ibcon#about to read 5, iclass 27, count 0 2006.286.04:50:54.00#ibcon#read 5, iclass 27, count 0 2006.286.04:50:54.00#ibcon#about to read 6, iclass 27, count 0 2006.286.04:50:54.00#ibcon#read 6, iclass 27, count 0 2006.286.04:50:54.00#ibcon#end of sib2, iclass 27, count 0 2006.286.04:50:54.00#ibcon#*after write, iclass 27, count 0 2006.286.04:50:54.00#ibcon#*before return 0, iclass 27, count 0 2006.286.04:50:54.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:50:54.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.04:50:54.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:50:54.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:50:54.00$vck44/vb=4,5 2006.286.04:50:54.00#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.04:50:54.00#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.04:50:54.00#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:54.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:50:54.06#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:50:54.06#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:50:54.06#ibcon#enter wrdev, iclass 29, count 2 2006.286.04:50:54.06#ibcon#first serial, iclass 29, count 2 2006.286.04:50:54.06#ibcon#enter sib2, iclass 29, count 2 2006.286.04:50:54.06#ibcon#flushed, iclass 29, count 2 2006.286.04:50:54.06#ibcon#about to write, iclass 29, count 2 2006.286.04:50:54.06#ibcon#wrote, iclass 29, count 2 2006.286.04:50:54.06#ibcon#about to read 3, iclass 29, count 2 2006.286.04:50:54.08#ibcon#read 3, iclass 29, count 2 2006.286.04:50:54.08#ibcon#about to read 4, iclass 29, count 2 2006.286.04:50:54.08#ibcon#read 4, iclass 29, count 2 2006.286.04:50:54.08#ibcon#about to read 5, iclass 29, count 2 2006.286.04:50:54.08#ibcon#read 5, iclass 29, count 2 2006.286.04:50:54.08#ibcon#about to read 6, iclass 29, count 2 2006.286.04:50:54.08#ibcon#read 6, iclass 29, count 2 2006.286.04:50:54.08#ibcon#end of sib2, iclass 29, count 2 2006.286.04:50:54.08#ibcon#*mode == 0, iclass 29, count 2 2006.286.04:50:54.08#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.04:50:54.08#ibcon#[27=AT04-05\r\n] 2006.286.04:50:54.08#ibcon#*before write, iclass 29, count 2 2006.286.04:50:54.08#ibcon#enter sib2, iclass 29, count 2 2006.286.04:50:54.08#ibcon#flushed, iclass 29, count 2 2006.286.04:50:54.08#ibcon#about to write, iclass 29, count 2 2006.286.04:50:54.08#ibcon#wrote, iclass 29, count 2 2006.286.04:50:54.08#ibcon#about to read 3, iclass 29, count 2 2006.286.04:50:54.11#ibcon#read 3, iclass 29, count 2 2006.286.04:50:54.11#ibcon#about to read 4, iclass 29, count 2 2006.286.04:50:54.11#ibcon#read 4, iclass 29, count 2 2006.286.04:50:54.11#ibcon#about to read 5, iclass 29, count 2 2006.286.04:50:54.11#ibcon#read 5, iclass 29, count 2 2006.286.04:50:54.11#ibcon#about to read 6, iclass 29, count 2 2006.286.04:50:54.11#ibcon#read 6, iclass 29, count 2 2006.286.04:50:54.11#ibcon#end of sib2, iclass 29, count 2 2006.286.04:50:54.11#ibcon#*after write, iclass 29, count 2 2006.286.04:50:54.11#ibcon#*before return 0, iclass 29, count 2 2006.286.04:50:54.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:50:54.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.04:50:54.11#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.04:50:54.11#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:54.11#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:50:54.23#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:50:54.32#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:50:54.32#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:50:54.32#ibcon#first serial, iclass 29, count 0 2006.286.04:50:54.32#ibcon#enter sib2, iclass 29, count 0 2006.286.04:50:54.32#ibcon#flushed, iclass 29, count 0 2006.286.04:50:54.32#ibcon#about to write, iclass 29, count 0 2006.286.04:50:54.32#ibcon#wrote, iclass 29, count 0 2006.286.04:50:54.32#ibcon#about to read 3, iclass 29, count 0 2006.286.04:50:54.34#ibcon#read 3, iclass 29, count 0 2006.286.04:50:54.34#ibcon#about to read 4, iclass 29, count 0 2006.286.04:50:54.34#ibcon#read 4, iclass 29, count 0 2006.286.04:50:54.34#ibcon#about to read 5, iclass 29, count 0 2006.286.04:50:54.34#ibcon#read 5, iclass 29, count 0 2006.286.04:50:54.34#ibcon#about to read 6, iclass 29, count 0 2006.286.04:50:54.34#ibcon#read 6, iclass 29, count 0 2006.286.04:50:54.34#ibcon#end of sib2, iclass 29, count 0 2006.286.04:50:54.34#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:50:54.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:50:54.34#ibcon#[27=USB\r\n] 2006.286.04:50:54.34#ibcon#*before write, iclass 29, count 0 2006.286.04:50:54.34#ibcon#enter sib2, iclass 29, count 0 2006.286.04:50:54.34#ibcon#flushed, iclass 29, count 0 2006.286.04:50:54.34#ibcon#about to write, iclass 29, count 0 2006.286.04:50:54.34#ibcon#wrote, iclass 29, count 0 2006.286.04:50:54.34#ibcon#about to read 3, iclass 29, count 0 2006.286.04:50:54.37#ibcon#read 3, iclass 29, count 0 2006.286.04:50:54.37#ibcon#about to read 4, iclass 29, count 0 2006.286.04:50:54.37#ibcon#read 4, iclass 29, count 0 2006.286.04:50:54.37#ibcon#about to read 5, iclass 29, count 0 2006.286.04:50:54.37#ibcon#read 5, iclass 29, count 0 2006.286.04:50:54.37#ibcon#about to read 6, iclass 29, count 0 2006.286.04:50:54.37#ibcon#read 6, iclass 29, count 0 2006.286.04:50:54.37#ibcon#end of sib2, iclass 29, count 0 2006.286.04:50:54.37#ibcon#*after write, iclass 29, count 0 2006.286.04:50:54.37#ibcon#*before return 0, iclass 29, count 0 2006.286.04:50:54.37#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:50:54.37#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.04:50:54.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:50:54.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:50:54.37$vck44/vblo=5,709.99 2006.286.04:50:54.37#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.04:50:54.37#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.04:50:54.37#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:54.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:50:54.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:50:54.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:50:54.37#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:50:54.37#ibcon#first serial, iclass 31, count 0 2006.286.04:50:54.37#ibcon#enter sib2, iclass 31, count 0 2006.286.04:50:54.37#ibcon#flushed, iclass 31, count 0 2006.286.04:50:54.37#ibcon#about to write, iclass 31, count 0 2006.286.04:50:54.37#ibcon#wrote, iclass 31, count 0 2006.286.04:50:54.37#ibcon#about to read 3, iclass 31, count 0 2006.286.04:50:54.39#ibcon#read 3, iclass 31, count 0 2006.286.04:50:54.39#ibcon#about to read 4, iclass 31, count 0 2006.286.04:50:54.39#ibcon#read 4, iclass 31, count 0 2006.286.04:50:54.39#ibcon#about to read 5, iclass 31, count 0 2006.286.04:50:54.39#ibcon#read 5, iclass 31, count 0 2006.286.04:50:54.39#ibcon#about to read 6, iclass 31, count 0 2006.286.04:50:54.39#ibcon#read 6, iclass 31, count 0 2006.286.04:50:54.39#ibcon#end of sib2, iclass 31, count 0 2006.286.04:50:54.39#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:50:54.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:50:54.39#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:50:54.39#ibcon#*before write, iclass 31, count 0 2006.286.04:50:54.39#ibcon#enter sib2, iclass 31, count 0 2006.286.04:50:54.39#ibcon#flushed, iclass 31, count 0 2006.286.04:50:54.39#ibcon#about to write, iclass 31, count 0 2006.286.04:50:54.39#ibcon#wrote, iclass 31, count 0 2006.286.04:50:54.39#ibcon#about to read 3, iclass 31, count 0 2006.286.04:50:54.43#ibcon#read 3, iclass 31, count 0 2006.286.04:50:54.43#ibcon#about to read 4, iclass 31, count 0 2006.286.04:50:54.43#ibcon#read 4, iclass 31, count 0 2006.286.04:50:54.43#ibcon#about to read 5, iclass 31, count 0 2006.286.04:50:54.43#ibcon#read 5, iclass 31, count 0 2006.286.04:50:54.43#ibcon#about to read 6, iclass 31, count 0 2006.286.04:50:54.43#ibcon#read 6, iclass 31, count 0 2006.286.04:50:54.43#ibcon#end of sib2, iclass 31, count 0 2006.286.04:50:54.43#ibcon#*after write, iclass 31, count 0 2006.286.04:50:54.43#ibcon#*before return 0, iclass 31, count 0 2006.286.04:50:54.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:50:54.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.04:50:54.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:50:54.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:50:54.43$vck44/vb=5,4 2006.286.04:50:54.43#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.04:50:54.43#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.04:50:54.43#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:54.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:50:54.49#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:50:54.49#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:50:54.49#ibcon#enter wrdev, iclass 33, count 2 2006.286.04:50:54.49#ibcon#first serial, iclass 33, count 2 2006.286.04:50:54.49#ibcon#enter sib2, iclass 33, count 2 2006.286.04:50:54.49#ibcon#flushed, iclass 33, count 2 2006.286.04:50:54.49#ibcon#about to write, iclass 33, count 2 2006.286.04:50:54.49#ibcon#wrote, iclass 33, count 2 2006.286.04:50:54.49#ibcon#about to read 3, iclass 33, count 2 2006.286.04:50:54.51#ibcon#read 3, iclass 33, count 2 2006.286.04:50:54.51#ibcon#about to read 4, iclass 33, count 2 2006.286.04:50:54.51#ibcon#read 4, iclass 33, count 2 2006.286.04:50:54.51#ibcon#about to read 5, iclass 33, count 2 2006.286.04:50:54.51#ibcon#read 5, iclass 33, count 2 2006.286.04:50:54.51#ibcon#about to read 6, iclass 33, count 2 2006.286.04:50:54.51#ibcon#read 6, iclass 33, count 2 2006.286.04:50:54.51#ibcon#end of sib2, iclass 33, count 2 2006.286.04:50:54.51#ibcon#*mode == 0, iclass 33, count 2 2006.286.04:50:54.51#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.04:50:54.51#ibcon#[27=AT05-04\r\n] 2006.286.04:50:54.51#ibcon#*before write, iclass 33, count 2 2006.286.04:50:54.51#ibcon#enter sib2, iclass 33, count 2 2006.286.04:50:54.51#ibcon#flushed, iclass 33, count 2 2006.286.04:50:54.51#ibcon#about to write, iclass 33, count 2 2006.286.04:50:54.51#ibcon#wrote, iclass 33, count 2 2006.286.04:50:54.51#ibcon#about to read 3, iclass 33, count 2 2006.286.04:50:54.54#ibcon#read 3, iclass 33, count 2 2006.286.04:50:54.54#ibcon#about to read 4, iclass 33, count 2 2006.286.04:50:54.54#ibcon#read 4, iclass 33, count 2 2006.286.04:50:54.54#ibcon#about to read 5, iclass 33, count 2 2006.286.04:50:54.54#ibcon#read 5, iclass 33, count 2 2006.286.04:50:54.54#ibcon#about to read 6, iclass 33, count 2 2006.286.04:50:54.54#ibcon#read 6, iclass 33, count 2 2006.286.04:50:54.54#ibcon#end of sib2, iclass 33, count 2 2006.286.04:50:54.54#ibcon#*after write, iclass 33, count 2 2006.286.04:50:54.54#ibcon#*before return 0, iclass 33, count 2 2006.286.04:50:54.54#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:50:54.54#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.04:50:54.54#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.04:50:54.54#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:54.54#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:50:54.66#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:50:54.66#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:50:54.66#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:50:54.66#ibcon#first serial, iclass 33, count 0 2006.286.04:50:54.66#ibcon#enter sib2, iclass 33, count 0 2006.286.04:50:54.66#ibcon#flushed, iclass 33, count 0 2006.286.04:50:54.66#ibcon#about to write, iclass 33, count 0 2006.286.04:50:54.66#ibcon#wrote, iclass 33, count 0 2006.286.04:50:54.66#ibcon#about to read 3, iclass 33, count 0 2006.286.04:50:54.68#ibcon#read 3, iclass 33, count 0 2006.286.04:50:54.68#ibcon#about to read 4, iclass 33, count 0 2006.286.04:50:54.68#ibcon#read 4, iclass 33, count 0 2006.286.04:50:54.68#ibcon#about to read 5, iclass 33, count 0 2006.286.04:50:54.68#ibcon#read 5, iclass 33, count 0 2006.286.04:50:54.68#ibcon#about to read 6, iclass 33, count 0 2006.286.04:50:54.68#ibcon#read 6, iclass 33, count 0 2006.286.04:50:54.68#ibcon#end of sib2, iclass 33, count 0 2006.286.04:50:54.68#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:50:54.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:50:54.68#ibcon#[27=USB\r\n] 2006.286.04:50:54.68#ibcon#*before write, iclass 33, count 0 2006.286.04:50:54.68#ibcon#enter sib2, iclass 33, count 0 2006.286.04:50:54.68#ibcon#flushed, iclass 33, count 0 2006.286.04:50:54.68#ibcon#about to write, iclass 33, count 0 2006.286.04:50:54.68#ibcon#wrote, iclass 33, count 0 2006.286.04:50:54.68#ibcon#about to read 3, iclass 33, count 0 2006.286.04:50:54.71#ibcon#read 3, iclass 33, count 0 2006.286.04:50:54.71#ibcon#about to read 4, iclass 33, count 0 2006.286.04:50:54.71#ibcon#read 4, iclass 33, count 0 2006.286.04:50:54.71#ibcon#about to read 5, iclass 33, count 0 2006.286.04:50:54.71#ibcon#read 5, iclass 33, count 0 2006.286.04:50:54.71#ibcon#about to read 6, iclass 33, count 0 2006.286.04:50:54.71#ibcon#read 6, iclass 33, count 0 2006.286.04:50:54.71#ibcon#end of sib2, iclass 33, count 0 2006.286.04:50:54.71#ibcon#*after write, iclass 33, count 0 2006.286.04:50:54.71#ibcon#*before return 0, iclass 33, count 0 2006.286.04:50:54.71#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:50:54.71#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.04:50:54.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:50:54.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:50:54.71$vck44/vblo=6,719.99 2006.286.04:50:54.71#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.04:50:54.71#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.04:50:54.71#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:54.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:50:54.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:50:54.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:50:54.71#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:50:54.71#ibcon#first serial, iclass 35, count 0 2006.286.04:50:54.71#ibcon#enter sib2, iclass 35, count 0 2006.286.04:50:54.71#ibcon#flushed, iclass 35, count 0 2006.286.04:50:54.71#ibcon#about to write, iclass 35, count 0 2006.286.04:50:54.71#ibcon#wrote, iclass 35, count 0 2006.286.04:50:54.71#ibcon#about to read 3, iclass 35, count 0 2006.286.04:50:54.73#ibcon#read 3, iclass 35, count 0 2006.286.04:50:54.73#ibcon#about to read 4, iclass 35, count 0 2006.286.04:50:54.73#ibcon#read 4, iclass 35, count 0 2006.286.04:50:54.73#ibcon#about to read 5, iclass 35, count 0 2006.286.04:50:54.73#ibcon#read 5, iclass 35, count 0 2006.286.04:50:54.73#ibcon#about to read 6, iclass 35, count 0 2006.286.04:50:54.73#ibcon#read 6, iclass 35, count 0 2006.286.04:50:54.73#ibcon#end of sib2, iclass 35, count 0 2006.286.04:50:54.73#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:50:54.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:50:54.73#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:50:54.73#ibcon#*before write, iclass 35, count 0 2006.286.04:50:54.73#ibcon#enter sib2, iclass 35, count 0 2006.286.04:50:54.73#ibcon#flushed, iclass 35, count 0 2006.286.04:50:54.73#ibcon#about to write, iclass 35, count 0 2006.286.04:50:54.73#ibcon#wrote, iclass 35, count 0 2006.286.04:50:54.73#ibcon#about to read 3, iclass 35, count 0 2006.286.04:50:54.77#ibcon#read 3, iclass 35, count 0 2006.286.04:50:54.77#ibcon#about to read 4, iclass 35, count 0 2006.286.04:50:54.77#ibcon#read 4, iclass 35, count 0 2006.286.04:50:54.77#ibcon#about to read 5, iclass 35, count 0 2006.286.04:50:54.77#ibcon#read 5, iclass 35, count 0 2006.286.04:50:54.77#ibcon#about to read 6, iclass 35, count 0 2006.286.04:50:54.77#ibcon#read 6, iclass 35, count 0 2006.286.04:50:54.77#ibcon#end of sib2, iclass 35, count 0 2006.286.04:50:54.77#ibcon#*after write, iclass 35, count 0 2006.286.04:50:54.77#ibcon#*before return 0, iclass 35, count 0 2006.286.04:50:54.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:50:54.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.04:50:54.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:50:54.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:50:54.77$vck44/vb=6,3 2006.286.04:50:54.77#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.04:50:54.77#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.04:50:54.77#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:54.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:50:54.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:50:54.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:50:54.83#ibcon#enter wrdev, iclass 37, count 2 2006.286.04:50:54.83#ibcon#first serial, iclass 37, count 2 2006.286.04:50:54.83#ibcon#enter sib2, iclass 37, count 2 2006.286.04:50:54.83#ibcon#flushed, iclass 37, count 2 2006.286.04:50:54.83#ibcon#about to write, iclass 37, count 2 2006.286.04:50:54.83#ibcon#wrote, iclass 37, count 2 2006.286.04:50:54.83#ibcon#about to read 3, iclass 37, count 2 2006.286.04:50:54.85#ibcon#read 3, iclass 37, count 2 2006.286.04:50:54.85#ibcon#about to read 4, iclass 37, count 2 2006.286.04:50:54.85#ibcon#read 4, iclass 37, count 2 2006.286.04:50:54.85#ibcon#about to read 5, iclass 37, count 2 2006.286.04:50:54.85#ibcon#read 5, iclass 37, count 2 2006.286.04:50:54.85#ibcon#about to read 6, iclass 37, count 2 2006.286.04:50:54.85#ibcon#read 6, iclass 37, count 2 2006.286.04:50:54.85#ibcon#end of sib2, iclass 37, count 2 2006.286.04:50:54.85#ibcon#*mode == 0, iclass 37, count 2 2006.286.04:50:54.85#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.04:50:54.85#ibcon#[27=AT06-03\r\n] 2006.286.04:50:54.85#ibcon#*before write, iclass 37, count 2 2006.286.04:50:54.85#ibcon#enter sib2, iclass 37, count 2 2006.286.04:50:54.85#ibcon#flushed, iclass 37, count 2 2006.286.04:50:54.85#ibcon#about to write, iclass 37, count 2 2006.286.04:50:54.85#ibcon#wrote, iclass 37, count 2 2006.286.04:50:54.85#ibcon#about to read 3, iclass 37, count 2 2006.286.04:50:54.88#ibcon#read 3, iclass 37, count 2 2006.286.04:50:54.88#ibcon#about to read 4, iclass 37, count 2 2006.286.04:50:54.88#ibcon#read 4, iclass 37, count 2 2006.286.04:50:54.88#ibcon#about to read 5, iclass 37, count 2 2006.286.04:50:54.88#ibcon#read 5, iclass 37, count 2 2006.286.04:50:54.88#ibcon#about to read 6, iclass 37, count 2 2006.286.04:50:54.88#ibcon#read 6, iclass 37, count 2 2006.286.04:50:54.88#ibcon#end of sib2, iclass 37, count 2 2006.286.04:50:54.88#ibcon#*after write, iclass 37, count 2 2006.286.04:50:54.88#ibcon#*before return 0, iclass 37, count 2 2006.286.04:50:54.88#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:50:54.88#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.04:50:54.88#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.04:50:54.88#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:54.88#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:50:55.00#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:50:55.00#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:50:55.00#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:50:55.00#ibcon#first serial, iclass 37, count 0 2006.286.04:50:55.00#ibcon#enter sib2, iclass 37, count 0 2006.286.04:50:55.00#ibcon#flushed, iclass 37, count 0 2006.286.04:50:55.00#ibcon#about to write, iclass 37, count 0 2006.286.04:50:55.00#ibcon#wrote, iclass 37, count 0 2006.286.04:50:55.00#ibcon#about to read 3, iclass 37, count 0 2006.286.04:50:55.02#ibcon#read 3, iclass 37, count 0 2006.286.04:50:55.02#ibcon#about to read 4, iclass 37, count 0 2006.286.04:50:55.02#ibcon#read 4, iclass 37, count 0 2006.286.04:50:55.02#ibcon#about to read 5, iclass 37, count 0 2006.286.04:50:55.02#ibcon#read 5, iclass 37, count 0 2006.286.04:50:55.02#ibcon#about to read 6, iclass 37, count 0 2006.286.04:50:55.02#ibcon#read 6, iclass 37, count 0 2006.286.04:50:55.02#ibcon#end of sib2, iclass 37, count 0 2006.286.04:50:55.02#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:50:55.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:50:55.02#ibcon#[27=USB\r\n] 2006.286.04:50:55.02#ibcon#*before write, iclass 37, count 0 2006.286.04:50:55.02#ibcon#enter sib2, iclass 37, count 0 2006.286.04:50:55.02#ibcon#flushed, iclass 37, count 0 2006.286.04:50:55.02#ibcon#about to write, iclass 37, count 0 2006.286.04:50:55.02#ibcon#wrote, iclass 37, count 0 2006.286.04:50:55.02#ibcon#about to read 3, iclass 37, count 0 2006.286.04:50:55.05#ibcon#read 3, iclass 37, count 0 2006.286.04:50:55.05#ibcon#about to read 4, iclass 37, count 0 2006.286.04:50:55.05#ibcon#read 4, iclass 37, count 0 2006.286.04:50:55.05#ibcon#about to read 5, iclass 37, count 0 2006.286.04:50:55.05#ibcon#read 5, iclass 37, count 0 2006.286.04:50:55.05#ibcon#about to read 6, iclass 37, count 0 2006.286.04:50:55.05#ibcon#read 6, iclass 37, count 0 2006.286.04:50:55.05#ibcon#end of sib2, iclass 37, count 0 2006.286.04:50:55.05#ibcon#*after write, iclass 37, count 0 2006.286.04:50:55.05#ibcon#*before return 0, iclass 37, count 0 2006.286.04:50:55.05#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:50:55.05#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.04:50:55.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:50:55.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:50:55.05$vck44/vblo=7,734.99 2006.286.04:50:55.05#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.04:50:55.05#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.04:50:55.05#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:55.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:50:55.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:50:55.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:50:55.05#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:50:55.05#ibcon#first serial, iclass 39, count 0 2006.286.04:50:55.05#ibcon#enter sib2, iclass 39, count 0 2006.286.04:50:55.05#ibcon#flushed, iclass 39, count 0 2006.286.04:50:55.05#ibcon#about to write, iclass 39, count 0 2006.286.04:50:55.05#ibcon#wrote, iclass 39, count 0 2006.286.04:50:55.05#ibcon#about to read 3, iclass 39, count 0 2006.286.04:50:55.07#ibcon#read 3, iclass 39, count 0 2006.286.04:50:55.07#ibcon#about to read 4, iclass 39, count 0 2006.286.04:50:55.07#ibcon#read 4, iclass 39, count 0 2006.286.04:50:55.07#ibcon#about to read 5, iclass 39, count 0 2006.286.04:50:55.07#ibcon#read 5, iclass 39, count 0 2006.286.04:50:55.07#ibcon#about to read 6, iclass 39, count 0 2006.286.04:50:55.07#ibcon#read 6, iclass 39, count 0 2006.286.04:50:55.07#ibcon#end of sib2, iclass 39, count 0 2006.286.04:50:55.07#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:50:55.07#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:50:55.07#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:50:55.07#ibcon#*before write, iclass 39, count 0 2006.286.04:50:55.07#ibcon#enter sib2, iclass 39, count 0 2006.286.04:50:55.07#ibcon#flushed, iclass 39, count 0 2006.286.04:50:55.07#ibcon#about to write, iclass 39, count 0 2006.286.04:50:55.07#ibcon#wrote, iclass 39, count 0 2006.286.04:50:55.07#ibcon#about to read 3, iclass 39, count 0 2006.286.04:50:55.11#ibcon#read 3, iclass 39, count 0 2006.286.04:50:55.11#ibcon#about to read 4, iclass 39, count 0 2006.286.04:50:55.11#ibcon#read 4, iclass 39, count 0 2006.286.04:50:55.11#ibcon#about to read 5, iclass 39, count 0 2006.286.04:50:55.11#ibcon#read 5, iclass 39, count 0 2006.286.04:50:55.11#ibcon#about to read 6, iclass 39, count 0 2006.286.04:50:55.11#ibcon#read 6, iclass 39, count 0 2006.286.04:50:55.11#ibcon#end of sib2, iclass 39, count 0 2006.286.04:50:55.11#ibcon#*after write, iclass 39, count 0 2006.286.04:50:55.11#ibcon#*before return 0, iclass 39, count 0 2006.286.04:50:55.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:50:55.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.04:50:55.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:50:55.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:50:55.11$vck44/vb=7,4 2006.286.04:50:55.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.04:50:55.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.04:50:55.27#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:55.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:50:55.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:50:55.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:50:55.27#ibcon#enter wrdev, iclass 3, count 2 2006.286.04:50:55.27#ibcon#first serial, iclass 3, count 2 2006.286.04:50:55.27#ibcon#enter sib2, iclass 3, count 2 2006.286.04:50:55.27#ibcon#flushed, iclass 3, count 2 2006.286.04:50:55.27#ibcon#about to write, iclass 3, count 2 2006.286.04:50:55.27#ibcon#wrote, iclass 3, count 2 2006.286.04:50:55.27#ibcon#about to read 3, iclass 3, count 2 2006.286.04:50:55.14#trakl#Source acquired 2006.286.04:50:55.27#flagr#flagr/antenna,acquired 2006.286.04:50:55.28#ibcon#read 3, iclass 3, count 2 2006.286.04:50:55.28#ibcon#about to read 4, iclass 3, count 2 2006.286.04:50:55.28#ibcon#read 4, iclass 3, count 2 2006.286.04:50:55.28#ibcon#about to read 5, iclass 3, count 2 2006.286.04:50:55.28#ibcon#read 5, iclass 3, count 2 2006.286.04:50:55.28#ibcon#about to read 6, iclass 3, count 2 2006.286.04:50:55.28#ibcon#read 6, iclass 3, count 2 2006.286.04:50:55.28#ibcon#end of sib2, iclass 3, count 2 2006.286.04:50:55.28#ibcon#*mode == 0, iclass 3, count 2 2006.286.04:50:55.28#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.04:50:55.28#ibcon#[27=AT07-04\r\n] 2006.286.04:50:55.28#ibcon#*before write, iclass 3, count 2 2006.286.04:50:55.28#ibcon#enter sib2, iclass 3, count 2 2006.286.04:50:55.28#ibcon#flushed, iclass 3, count 2 2006.286.04:50:55.28#ibcon#about to write, iclass 3, count 2 2006.286.04:50:55.28#ibcon#wrote, iclass 3, count 2 2006.286.04:50:55.28#ibcon#about to read 3, iclass 3, count 2 2006.286.04:50:55.31#ibcon#read 3, iclass 3, count 2 2006.286.04:50:55.31#ibcon#about to read 4, iclass 3, count 2 2006.286.04:50:55.31#ibcon#read 4, iclass 3, count 2 2006.286.04:50:55.31#ibcon#about to read 5, iclass 3, count 2 2006.286.04:50:55.31#ibcon#read 5, iclass 3, count 2 2006.286.04:50:55.31#ibcon#about to read 6, iclass 3, count 2 2006.286.04:50:55.31#ibcon#read 6, iclass 3, count 2 2006.286.04:50:55.31#ibcon#end of sib2, iclass 3, count 2 2006.286.04:50:55.31#ibcon#*after write, iclass 3, count 2 2006.286.04:50:55.31#ibcon#*before return 0, iclass 3, count 2 2006.286.04:50:55.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:50:55.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.04:50:55.31#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.04:50:55.31#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:55.31#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:50:55.43#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:50:55.43#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:50:55.43#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:50:55.43#ibcon#first serial, iclass 3, count 0 2006.286.04:50:55.43#ibcon#enter sib2, iclass 3, count 0 2006.286.04:50:55.43#ibcon#flushed, iclass 3, count 0 2006.286.04:50:55.43#ibcon#about to write, iclass 3, count 0 2006.286.04:50:55.43#ibcon#wrote, iclass 3, count 0 2006.286.04:50:55.43#ibcon#about to read 3, iclass 3, count 0 2006.286.04:50:55.45#ibcon#read 3, iclass 3, count 0 2006.286.04:50:55.45#ibcon#about to read 4, iclass 3, count 0 2006.286.04:50:55.45#ibcon#read 4, iclass 3, count 0 2006.286.04:50:55.45#ibcon#about to read 5, iclass 3, count 0 2006.286.04:50:55.45#ibcon#read 5, iclass 3, count 0 2006.286.04:50:55.45#ibcon#about to read 6, iclass 3, count 0 2006.286.04:50:55.45#ibcon#read 6, iclass 3, count 0 2006.286.04:50:55.45#ibcon#end of sib2, iclass 3, count 0 2006.286.04:50:55.45#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:50:55.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:50:55.45#ibcon#[27=USB\r\n] 2006.286.04:50:55.45#ibcon#*before write, iclass 3, count 0 2006.286.04:50:55.45#ibcon#enter sib2, iclass 3, count 0 2006.286.04:50:55.45#ibcon#flushed, iclass 3, count 0 2006.286.04:50:55.45#ibcon#about to write, iclass 3, count 0 2006.286.04:50:55.45#ibcon#wrote, iclass 3, count 0 2006.286.04:50:55.45#ibcon#about to read 3, iclass 3, count 0 2006.286.04:50:55.48#ibcon#read 3, iclass 3, count 0 2006.286.04:50:55.48#ibcon#about to read 4, iclass 3, count 0 2006.286.04:50:55.48#ibcon#read 4, iclass 3, count 0 2006.286.04:50:55.48#ibcon#about to read 5, iclass 3, count 0 2006.286.04:50:55.48#ibcon#read 5, iclass 3, count 0 2006.286.04:50:55.48#ibcon#about to read 6, iclass 3, count 0 2006.286.04:50:55.48#ibcon#read 6, iclass 3, count 0 2006.286.04:50:55.48#ibcon#end of sib2, iclass 3, count 0 2006.286.04:50:55.48#ibcon#*after write, iclass 3, count 0 2006.286.04:50:55.48#ibcon#*before return 0, iclass 3, count 0 2006.286.04:50:55.48#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:50:55.48#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.04:50:55.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:50:55.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:50:55.48$vck44/vblo=8,744.99 2006.286.04:50:55.48#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.04:50:55.48#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.04:50:55.48#ibcon#ireg 17 cls_cnt 0 2006.286.04:50:55.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:50:55.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:50:55.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:50:55.48#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:50:55.48#ibcon#first serial, iclass 5, count 0 2006.286.04:50:55.48#ibcon#enter sib2, iclass 5, count 0 2006.286.04:50:55.48#ibcon#flushed, iclass 5, count 0 2006.286.04:50:55.48#ibcon#about to write, iclass 5, count 0 2006.286.04:50:55.48#ibcon#wrote, iclass 5, count 0 2006.286.04:50:55.48#ibcon#about to read 3, iclass 5, count 0 2006.286.04:50:55.50#ibcon#read 3, iclass 5, count 0 2006.286.04:50:55.50#ibcon#about to read 4, iclass 5, count 0 2006.286.04:50:55.50#ibcon#read 4, iclass 5, count 0 2006.286.04:50:55.50#ibcon#about to read 5, iclass 5, count 0 2006.286.04:50:55.50#ibcon#read 5, iclass 5, count 0 2006.286.04:50:55.50#ibcon#about to read 6, iclass 5, count 0 2006.286.04:50:55.50#ibcon#read 6, iclass 5, count 0 2006.286.04:50:55.50#ibcon#end of sib2, iclass 5, count 0 2006.286.04:50:55.50#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:50:55.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:50:55.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:50:55.50#ibcon#*before write, iclass 5, count 0 2006.286.04:50:55.50#ibcon#enter sib2, iclass 5, count 0 2006.286.04:50:55.50#ibcon#flushed, iclass 5, count 0 2006.286.04:50:55.50#ibcon#about to write, iclass 5, count 0 2006.286.04:50:55.50#ibcon#wrote, iclass 5, count 0 2006.286.04:50:55.50#ibcon#about to read 3, iclass 5, count 0 2006.286.04:50:55.54#ibcon#read 3, iclass 5, count 0 2006.286.04:50:55.54#ibcon#about to read 4, iclass 5, count 0 2006.286.04:50:55.54#ibcon#read 4, iclass 5, count 0 2006.286.04:50:55.54#ibcon#about to read 5, iclass 5, count 0 2006.286.04:50:55.54#ibcon#read 5, iclass 5, count 0 2006.286.04:50:55.54#ibcon#about to read 6, iclass 5, count 0 2006.286.04:50:55.54#ibcon#read 6, iclass 5, count 0 2006.286.04:50:55.54#ibcon#end of sib2, iclass 5, count 0 2006.286.04:50:55.54#ibcon#*after write, iclass 5, count 0 2006.286.04:50:55.54#ibcon#*before return 0, iclass 5, count 0 2006.286.04:50:55.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:50:55.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:50:55.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:50:55.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:50:55.54$vck44/vb=8,4 2006.286.04:50:55.54#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.04:50:55.54#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.04:50:55.54#ibcon#ireg 11 cls_cnt 2 2006.286.04:50:55.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:50:55.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:50:55.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:50:55.60#ibcon#enter wrdev, iclass 7, count 2 2006.286.04:50:55.60#ibcon#first serial, iclass 7, count 2 2006.286.04:50:55.60#ibcon#enter sib2, iclass 7, count 2 2006.286.04:50:55.60#ibcon#flushed, iclass 7, count 2 2006.286.04:50:55.60#ibcon#about to write, iclass 7, count 2 2006.286.04:50:55.60#ibcon#wrote, iclass 7, count 2 2006.286.04:50:55.60#ibcon#about to read 3, iclass 7, count 2 2006.286.04:50:55.62#ibcon#read 3, iclass 7, count 2 2006.286.04:50:55.62#ibcon#about to read 4, iclass 7, count 2 2006.286.04:50:55.62#ibcon#read 4, iclass 7, count 2 2006.286.04:50:55.62#ibcon#about to read 5, iclass 7, count 2 2006.286.04:50:55.62#ibcon#read 5, iclass 7, count 2 2006.286.04:50:55.62#ibcon#about to read 6, iclass 7, count 2 2006.286.04:50:55.62#ibcon#read 6, iclass 7, count 2 2006.286.04:50:55.62#ibcon#end of sib2, iclass 7, count 2 2006.286.04:50:55.62#ibcon#*mode == 0, iclass 7, count 2 2006.286.04:50:55.62#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.04:50:55.62#ibcon#[27=AT08-04\r\n] 2006.286.04:50:55.62#ibcon#*before write, iclass 7, count 2 2006.286.04:50:55.62#ibcon#enter sib2, iclass 7, count 2 2006.286.04:50:55.62#ibcon#flushed, iclass 7, count 2 2006.286.04:50:55.62#ibcon#about to write, iclass 7, count 2 2006.286.04:50:55.62#ibcon#wrote, iclass 7, count 2 2006.286.04:50:55.62#ibcon#about to read 3, iclass 7, count 2 2006.286.04:50:55.65#ibcon#read 3, iclass 7, count 2 2006.286.04:50:55.65#ibcon#about to read 4, iclass 7, count 2 2006.286.04:50:55.65#ibcon#read 4, iclass 7, count 2 2006.286.04:50:55.65#ibcon#about to read 5, iclass 7, count 2 2006.286.04:50:55.65#ibcon#read 5, iclass 7, count 2 2006.286.04:50:55.65#ibcon#about to read 6, iclass 7, count 2 2006.286.04:50:55.65#ibcon#read 6, iclass 7, count 2 2006.286.04:50:55.65#ibcon#end of sib2, iclass 7, count 2 2006.286.04:50:55.65#ibcon#*after write, iclass 7, count 2 2006.286.04:50:55.65#ibcon#*before return 0, iclass 7, count 2 2006.286.04:50:55.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:50:55.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.04:50:55.65#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.04:50:55.65#ibcon#ireg 7 cls_cnt 0 2006.286.04:50:55.65#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:50:55.77#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:50:55.77#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:50:55.77#ibcon#enter wrdev, iclass 7, count 0 2006.286.04:50:55.77#ibcon#first serial, iclass 7, count 0 2006.286.04:50:55.77#ibcon#enter sib2, iclass 7, count 0 2006.286.04:50:55.77#ibcon#flushed, iclass 7, count 0 2006.286.04:50:55.77#ibcon#about to write, iclass 7, count 0 2006.286.04:50:55.77#ibcon#wrote, iclass 7, count 0 2006.286.04:50:55.77#ibcon#about to read 3, iclass 7, count 0 2006.286.04:50:55.79#ibcon#read 3, iclass 7, count 0 2006.286.04:50:55.79#ibcon#about to read 4, iclass 7, count 0 2006.286.04:50:55.79#ibcon#read 4, iclass 7, count 0 2006.286.04:50:55.79#ibcon#about to read 5, iclass 7, count 0 2006.286.04:50:55.79#ibcon#read 5, iclass 7, count 0 2006.286.04:50:55.79#ibcon#about to read 6, iclass 7, count 0 2006.286.04:50:55.79#ibcon#read 6, iclass 7, count 0 2006.286.04:50:55.79#ibcon#end of sib2, iclass 7, count 0 2006.286.04:50:55.79#ibcon#*mode == 0, iclass 7, count 0 2006.286.04:50:55.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.04:50:55.79#ibcon#[27=USB\r\n] 2006.286.04:50:55.79#ibcon#*before write, iclass 7, count 0 2006.286.04:50:55.79#ibcon#enter sib2, iclass 7, count 0 2006.286.04:50:55.79#ibcon#flushed, iclass 7, count 0 2006.286.04:50:55.79#ibcon#about to write, iclass 7, count 0 2006.286.04:50:55.79#ibcon#wrote, iclass 7, count 0 2006.286.04:50:55.79#ibcon#about to read 3, iclass 7, count 0 2006.286.04:50:55.82#ibcon#read 3, iclass 7, count 0 2006.286.04:50:55.82#ibcon#about to read 4, iclass 7, count 0 2006.286.04:50:55.82#ibcon#read 4, iclass 7, count 0 2006.286.04:50:55.82#ibcon#about to read 5, iclass 7, count 0 2006.286.04:50:55.82#ibcon#read 5, iclass 7, count 0 2006.286.04:50:55.82#ibcon#about to read 6, iclass 7, count 0 2006.286.04:50:55.82#ibcon#read 6, iclass 7, count 0 2006.286.04:50:55.82#ibcon#end of sib2, iclass 7, count 0 2006.286.04:50:55.82#ibcon#*after write, iclass 7, count 0 2006.286.04:50:55.82#ibcon#*before return 0, iclass 7, count 0 2006.286.04:50:55.82#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:50:55.82#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.04:50:55.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.04:50:55.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.04:50:55.82$vck44/vabw=wide 2006.286.04:50:55.82#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.04:50:55.82#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.04:50:55.82#ibcon#ireg 8 cls_cnt 0 2006.286.04:50:55.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:50:55.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:50:55.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:50:55.82#ibcon#enter wrdev, iclass 11, count 0 2006.286.04:50:55.82#ibcon#first serial, iclass 11, count 0 2006.286.04:50:55.82#ibcon#enter sib2, iclass 11, count 0 2006.286.04:50:55.82#ibcon#flushed, iclass 11, count 0 2006.286.04:50:55.82#ibcon#about to write, iclass 11, count 0 2006.286.04:50:55.82#ibcon#wrote, iclass 11, count 0 2006.286.04:50:55.82#ibcon#about to read 3, iclass 11, count 0 2006.286.04:50:55.84#ibcon#read 3, iclass 11, count 0 2006.286.04:50:55.84#ibcon#about to read 4, iclass 11, count 0 2006.286.04:50:55.84#ibcon#read 4, iclass 11, count 0 2006.286.04:50:55.84#ibcon#about to read 5, iclass 11, count 0 2006.286.04:50:55.84#ibcon#read 5, iclass 11, count 0 2006.286.04:50:55.84#ibcon#about to read 6, iclass 11, count 0 2006.286.04:50:55.84#ibcon#read 6, iclass 11, count 0 2006.286.04:50:55.84#ibcon#end of sib2, iclass 11, count 0 2006.286.04:50:55.84#ibcon#*mode == 0, iclass 11, count 0 2006.286.04:50:55.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.04:50:55.84#ibcon#[25=BW32\r\n] 2006.286.04:50:55.84#ibcon#*before write, iclass 11, count 0 2006.286.04:50:55.84#ibcon#enter sib2, iclass 11, count 0 2006.286.04:50:55.84#ibcon#flushed, iclass 11, count 0 2006.286.04:50:55.84#ibcon#about to write, iclass 11, count 0 2006.286.04:50:55.84#ibcon#wrote, iclass 11, count 0 2006.286.04:50:55.84#ibcon#about to read 3, iclass 11, count 0 2006.286.04:50:55.87#ibcon#read 3, iclass 11, count 0 2006.286.04:50:55.87#ibcon#about to read 4, iclass 11, count 0 2006.286.04:50:55.87#ibcon#read 4, iclass 11, count 0 2006.286.04:50:55.87#ibcon#about to read 5, iclass 11, count 0 2006.286.04:50:55.87#ibcon#read 5, iclass 11, count 0 2006.286.04:50:55.87#ibcon#about to read 6, iclass 11, count 0 2006.286.04:50:55.87#ibcon#read 6, iclass 11, count 0 2006.286.04:50:55.87#ibcon#end of sib2, iclass 11, count 0 2006.286.04:50:55.87#ibcon#*after write, iclass 11, count 0 2006.286.04:50:55.87#ibcon#*before return 0, iclass 11, count 0 2006.286.04:50:55.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:50:55.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.04:50:55.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.04:50:55.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.04:50:55.87$vck44/vbbw=wide 2006.286.04:50:55.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.04:50:55.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.04:50:55.87#ibcon#ireg 8 cls_cnt 0 2006.286.04:50:55.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:50:55.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:50:55.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:50:55.94#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:50:55.94#ibcon#first serial, iclass 13, count 0 2006.286.04:50:55.94#ibcon#enter sib2, iclass 13, count 0 2006.286.04:50:55.94#ibcon#flushed, iclass 13, count 0 2006.286.04:50:55.94#ibcon#about to write, iclass 13, count 0 2006.286.04:50:55.94#ibcon#wrote, iclass 13, count 0 2006.286.04:50:55.94#ibcon#about to read 3, iclass 13, count 0 2006.286.04:50:55.96#ibcon#read 3, iclass 13, count 0 2006.286.04:50:55.96#ibcon#about to read 4, iclass 13, count 0 2006.286.04:50:55.96#ibcon#read 4, iclass 13, count 0 2006.286.04:50:55.96#ibcon#about to read 5, iclass 13, count 0 2006.286.04:50:55.96#ibcon#read 5, iclass 13, count 0 2006.286.04:50:55.96#ibcon#about to read 6, iclass 13, count 0 2006.286.04:50:55.96#ibcon#read 6, iclass 13, count 0 2006.286.04:50:55.96#ibcon#end of sib2, iclass 13, count 0 2006.286.04:50:55.96#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:50:55.96#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:50:55.96#ibcon#[27=BW32\r\n] 2006.286.04:50:55.96#ibcon#*before write, iclass 13, count 0 2006.286.04:50:55.96#ibcon#enter sib2, iclass 13, count 0 2006.286.04:50:55.96#ibcon#flushed, iclass 13, count 0 2006.286.04:50:55.96#ibcon#about to write, iclass 13, count 0 2006.286.04:50:55.96#ibcon#wrote, iclass 13, count 0 2006.286.04:50:55.96#ibcon#about to read 3, iclass 13, count 0 2006.286.04:50:55.99#ibcon#read 3, iclass 13, count 0 2006.286.04:50:55.99#ibcon#about to read 4, iclass 13, count 0 2006.286.04:50:55.99#ibcon#read 4, iclass 13, count 0 2006.286.04:50:55.99#ibcon#about to read 5, iclass 13, count 0 2006.286.04:50:55.99#ibcon#read 5, iclass 13, count 0 2006.286.04:50:55.99#ibcon#about to read 6, iclass 13, count 0 2006.286.04:50:55.99#ibcon#read 6, iclass 13, count 0 2006.286.04:50:55.99#ibcon#end of sib2, iclass 13, count 0 2006.286.04:50:55.99#ibcon#*after write, iclass 13, count 0 2006.286.04:50:55.99#ibcon#*before return 0, iclass 13, count 0 2006.286.04:50:55.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:50:55.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:50:55.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:50:55.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:50:55.99$setupk4/ifdk4 2006.286.04:50:55.99$ifdk4/lo= 2006.286.04:50:55.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:50:55.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:50:55.99$ifdk4/patch= 2006.286.04:50:55.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:50:55.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:50:55.99$setupk4/!*+20s 2006.286.04:51:02.79#abcon#<5=/04 4.0 8.6 22.17 761014.8\r\n> 2006.286.04:51:02.81#abcon#{5=INTERFACE CLEAR} 2006.286.04:51:02.87#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:51:09.73$setupk4/"tpicd 2006.286.04:51:09.73$setupk4/echo=off 2006.286.04:51:09.73$setupk4/xlog=off 2006.286.04:51:09.73:!2006.286.04:51:14 2006.286.04:51:14.00:preob 2006.286.04:51:14.14/onsource/TRACKING 2006.286.04:51:14.14:!2006.286.04:51:24 2006.286.04:51:24.00:"tape 2006.286.04:51:24.00:"st=record 2006.286.04:51:24.00:data_valid=on 2006.286.04:51:24.00:midob 2006.286.04:51:25.14/onsource/TRACKING 2006.286.04:51:25.14/wx/22.17,1014.8,75 2006.286.04:51:25.23/cable/+6.4937E-03 2006.286.04:51:26.32/va/01,07,usb,yes,35,38 2006.286.04:51:26.32/va/02,06,usb,yes,35,36 2006.286.04:51:26.32/va/03,07,usb,yes,35,37 2006.286.04:51:26.32/va/04,06,usb,yes,36,38 2006.286.04:51:26.32/va/05,03,usb,yes,36,36 2006.286.04:51:26.32/va/06,04,usb,yes,32,32 2006.286.04:51:26.32/va/07,04,usb,yes,33,34 2006.286.04:51:26.32/va/08,03,usb,yes,34,41 2006.286.04:51:26.55/valo/01,524.99,yes,locked 2006.286.04:51:26.55/valo/02,534.99,yes,locked 2006.286.04:51:26.55/valo/03,564.99,yes,locked 2006.286.04:51:26.55/valo/04,624.99,yes,locked 2006.286.04:51:26.55/valo/05,734.99,yes,locked 2006.286.04:51:26.55/valo/06,814.99,yes,locked 2006.286.04:51:26.55/valo/07,864.99,yes,locked 2006.286.04:51:26.55/valo/08,884.99,yes,locked 2006.286.04:51:27.64/vb/01,04,usb,yes,31,29 2006.286.04:51:27.64/vb/02,05,usb,yes,29,29 2006.286.04:51:27.64/vb/03,04,usb,yes,30,33 2006.286.04:51:27.64/vb/04,05,usb,yes,30,29 2006.286.04:51:27.64/vb/05,04,usb,yes,27,30 2006.286.04:51:27.64/vb/06,03,usb,yes,39,35 2006.286.04:51:27.64/vb/07,04,usb,yes,31,32 2006.286.04:51:27.64/vb/08,04,usb,yes,29,32 2006.286.04:51:27.87/vblo/01,629.99,yes,locked 2006.286.04:51:27.87/vblo/02,634.99,yes,locked 2006.286.04:51:27.87/vblo/03,649.99,yes,locked 2006.286.04:51:27.87/vblo/04,679.99,yes,locked 2006.286.04:51:27.87/vblo/05,709.99,yes,locked 2006.286.04:51:27.87/vblo/06,719.99,yes,locked 2006.286.04:51:27.87/vblo/07,734.99,yes,locked 2006.286.04:51:27.87/vblo/08,744.99,yes,locked 2006.286.04:51:28.02/vabw/8 2006.286.04:51:28.17/vbbw/8 2006.286.04:51:28.35/xfe/off,on,12.2 2006.286.04:51:28.73/ifatt/23,28,28,28 2006.286.04:51:29.07/fmout-gps/S +2.40E-07 2006.286.04:51:29.09:!2006.286.04:52:04 2006.286.04:52:04.00:data_valid=off 2006.286.04:52:04.00:"et 2006.286.04:52:04.00:!+3s 2006.286.04:52:07.01:"tape 2006.286.04:52:07.01:postob 2006.286.04:52:07.19/cable/+6.4933E-03 2006.286.04:52:07.19/wx/22.15,1014.9,75 2006.286.04:52:08.07/fmout-gps/S +2.39E-07 2006.286.04:52:08.07:scan_name=286-0457,jd0610,40 2006.286.04:52:08.07:source=2136+141,213901.31,142336.0,2000.0,cw 2006.286.04:52:09.14#flagr#flagr/antenna,new-source 2006.286.04:52:09.14:checkk5 2006.286.04:52:09.54/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:52:09.99/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:52:10.42/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:52:10.82/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:52:11.46/chk_obsdata//k5ts1/T2860451??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:52:11.85/chk_obsdata//k5ts2/T2860451??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:52:12.26/chk_obsdata//k5ts3/T2860451??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:52:12.66/chk_obsdata//k5ts4/T2860451??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:52:13.60/k5log//k5ts1_log_newline 2006.286.04:52:14.41/k5log//k5ts2_log_newline 2006.286.04:52:15.39/k5log//k5ts3_log_newline 2006.286.04:52:16.40/k5log//k5ts4_log_newline 2006.286.04:52:16.42/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:52:16.42:setupk4=1 2006.286.04:52:16.42$setupk4/echo=on 2006.286.04:52:16.42$setupk4/pcalon 2006.286.04:52:16.42$pcalon/"no phase cal control is implemented here 2006.286.04:52:16.42$setupk4/"tpicd=stop 2006.286.04:52:16.42$setupk4/"rec=synch_on 2006.286.04:52:16.42$setupk4/"rec_mode=128 2006.286.04:52:16.42$setupk4/!* 2006.286.04:52:16.43$setupk4/recpk4 2006.286.04:52:16.43$recpk4/recpatch= 2006.286.04:52:16.43$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:52:16.43$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:52:16.43$setupk4/vck44 2006.286.04:52:16.43$vck44/valo=1,524.99 2006.286.04:52:16.43#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.04:52:16.43#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.04:52:16.43#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:16.43#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:52:16.43#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:52:16.43#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:52:16.43#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:52:16.43#ibcon#first serial, iclass 14, count 0 2006.286.04:52:16.43#ibcon#enter sib2, iclass 14, count 0 2006.286.04:52:16.43#ibcon#flushed, iclass 14, count 0 2006.286.04:52:16.43#ibcon#about to write, iclass 14, count 0 2006.286.04:52:16.43#ibcon#wrote, iclass 14, count 0 2006.286.04:52:16.43#ibcon#about to read 3, iclass 14, count 0 2006.286.04:52:16.45#ibcon#read 3, iclass 14, count 0 2006.286.04:52:16.45#ibcon#about to read 4, iclass 14, count 0 2006.286.04:52:16.45#ibcon#read 4, iclass 14, count 0 2006.286.04:52:16.45#ibcon#about to read 5, iclass 14, count 0 2006.286.04:52:16.45#ibcon#read 5, iclass 14, count 0 2006.286.04:52:16.45#ibcon#about to read 6, iclass 14, count 0 2006.286.04:52:16.45#ibcon#read 6, iclass 14, count 0 2006.286.04:52:16.45#ibcon#end of sib2, iclass 14, count 0 2006.286.04:52:16.45#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:52:16.45#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:52:16.45#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:52:16.45#ibcon#*before write, iclass 14, count 0 2006.286.04:52:16.45#ibcon#enter sib2, iclass 14, count 0 2006.286.04:52:16.45#ibcon#flushed, iclass 14, count 0 2006.286.04:52:16.45#ibcon#about to write, iclass 14, count 0 2006.286.04:52:16.45#ibcon#wrote, iclass 14, count 0 2006.286.04:52:16.45#ibcon#about to read 3, iclass 14, count 0 2006.286.04:52:16.50#ibcon#read 3, iclass 14, count 0 2006.286.04:52:16.50#ibcon#about to read 4, iclass 14, count 0 2006.286.04:52:16.50#ibcon#read 4, iclass 14, count 0 2006.286.04:52:16.50#ibcon#about to read 5, iclass 14, count 0 2006.286.04:52:16.50#ibcon#read 5, iclass 14, count 0 2006.286.04:52:16.50#ibcon#about to read 6, iclass 14, count 0 2006.286.04:52:16.50#ibcon#read 6, iclass 14, count 0 2006.286.04:52:16.50#ibcon#end of sib2, iclass 14, count 0 2006.286.04:52:16.50#ibcon#*after write, iclass 14, count 0 2006.286.04:52:16.50#ibcon#*before return 0, iclass 14, count 0 2006.286.04:52:16.50#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:52:16.50#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:52:16.50#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:52:16.50#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:52:16.50$vck44/va=1,7 2006.286.04:52:16.50#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.04:52:16.50#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.04:52:16.50#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:16.50#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:52:16.50#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:52:16.50#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:52:16.50#ibcon#enter wrdev, iclass 16, count 2 2006.286.04:52:16.50#ibcon#first serial, iclass 16, count 2 2006.286.04:52:16.50#ibcon#enter sib2, iclass 16, count 2 2006.286.04:52:16.50#ibcon#flushed, iclass 16, count 2 2006.286.04:52:16.50#ibcon#about to write, iclass 16, count 2 2006.286.04:52:16.50#ibcon#wrote, iclass 16, count 2 2006.286.04:52:16.50#ibcon#about to read 3, iclass 16, count 2 2006.286.04:52:16.52#ibcon#read 3, iclass 16, count 2 2006.286.04:52:16.52#ibcon#about to read 4, iclass 16, count 2 2006.286.04:52:16.52#ibcon#read 4, iclass 16, count 2 2006.286.04:52:16.52#ibcon#about to read 5, iclass 16, count 2 2006.286.04:52:16.52#ibcon#read 5, iclass 16, count 2 2006.286.04:52:16.52#ibcon#about to read 6, iclass 16, count 2 2006.286.04:52:16.52#ibcon#read 6, iclass 16, count 2 2006.286.04:52:16.52#ibcon#end of sib2, iclass 16, count 2 2006.286.04:52:16.52#ibcon#*mode == 0, iclass 16, count 2 2006.286.04:52:16.52#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.04:52:16.52#ibcon#[25=AT01-07\r\n] 2006.286.04:52:16.52#ibcon#*before write, iclass 16, count 2 2006.286.04:52:16.52#ibcon#enter sib2, iclass 16, count 2 2006.286.04:52:16.52#ibcon#flushed, iclass 16, count 2 2006.286.04:52:16.52#ibcon#about to write, iclass 16, count 2 2006.286.04:52:16.52#ibcon#wrote, iclass 16, count 2 2006.286.04:52:16.52#ibcon#about to read 3, iclass 16, count 2 2006.286.04:52:16.55#ibcon#read 3, iclass 16, count 2 2006.286.04:52:16.55#ibcon#about to read 4, iclass 16, count 2 2006.286.04:52:16.55#ibcon#read 4, iclass 16, count 2 2006.286.04:52:16.55#ibcon#about to read 5, iclass 16, count 2 2006.286.04:52:16.55#ibcon#read 5, iclass 16, count 2 2006.286.04:52:16.55#ibcon#about to read 6, iclass 16, count 2 2006.286.04:52:16.55#ibcon#read 6, iclass 16, count 2 2006.286.04:52:16.55#ibcon#end of sib2, iclass 16, count 2 2006.286.04:52:16.55#ibcon#*after write, iclass 16, count 2 2006.286.04:52:16.55#ibcon#*before return 0, iclass 16, count 2 2006.286.04:52:16.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:52:16.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:52:16.55#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.04:52:16.55#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:16.55#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:52:16.67#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:52:16.67#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:52:16.67#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:52:16.67#ibcon#first serial, iclass 16, count 0 2006.286.04:52:16.67#ibcon#enter sib2, iclass 16, count 0 2006.286.04:52:16.67#ibcon#flushed, iclass 16, count 0 2006.286.04:52:16.67#ibcon#about to write, iclass 16, count 0 2006.286.04:52:16.67#ibcon#wrote, iclass 16, count 0 2006.286.04:52:16.67#ibcon#about to read 3, iclass 16, count 0 2006.286.04:52:16.69#ibcon#read 3, iclass 16, count 0 2006.286.04:52:16.69#ibcon#about to read 4, iclass 16, count 0 2006.286.04:52:16.69#ibcon#read 4, iclass 16, count 0 2006.286.04:52:16.69#ibcon#about to read 5, iclass 16, count 0 2006.286.04:52:16.69#ibcon#read 5, iclass 16, count 0 2006.286.04:52:16.69#ibcon#about to read 6, iclass 16, count 0 2006.286.04:52:16.69#ibcon#read 6, iclass 16, count 0 2006.286.04:52:16.69#ibcon#end of sib2, iclass 16, count 0 2006.286.04:52:16.69#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:52:16.69#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:52:16.69#ibcon#[25=USB\r\n] 2006.286.04:52:16.69#ibcon#*before write, iclass 16, count 0 2006.286.04:52:16.69#ibcon#enter sib2, iclass 16, count 0 2006.286.04:52:16.69#ibcon#flushed, iclass 16, count 0 2006.286.04:52:16.69#ibcon#about to write, iclass 16, count 0 2006.286.04:52:16.69#ibcon#wrote, iclass 16, count 0 2006.286.04:52:16.69#ibcon#about to read 3, iclass 16, count 0 2006.286.04:52:16.72#ibcon#read 3, iclass 16, count 0 2006.286.04:52:16.72#ibcon#about to read 4, iclass 16, count 0 2006.286.04:52:16.72#ibcon#read 4, iclass 16, count 0 2006.286.04:52:16.72#ibcon#about to read 5, iclass 16, count 0 2006.286.04:52:16.72#ibcon#read 5, iclass 16, count 0 2006.286.04:52:16.72#ibcon#about to read 6, iclass 16, count 0 2006.286.04:52:16.72#ibcon#read 6, iclass 16, count 0 2006.286.04:52:16.72#ibcon#end of sib2, iclass 16, count 0 2006.286.04:52:16.72#ibcon#*after write, iclass 16, count 0 2006.286.04:52:16.72#ibcon#*before return 0, iclass 16, count 0 2006.286.04:52:16.72#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:52:16.72#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:52:16.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:52:16.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:52:16.72$vck44/valo=2,534.99 2006.286.04:52:16.72#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.04:52:16.72#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.04:52:16.72#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:16.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:52:16.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:52:16.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:52:16.72#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:52:16.72#ibcon#first serial, iclass 18, count 0 2006.286.04:52:16.72#ibcon#enter sib2, iclass 18, count 0 2006.286.04:52:16.72#ibcon#flushed, iclass 18, count 0 2006.286.04:52:16.72#ibcon#about to write, iclass 18, count 0 2006.286.04:52:16.72#ibcon#wrote, iclass 18, count 0 2006.286.04:52:16.72#ibcon#about to read 3, iclass 18, count 0 2006.286.04:52:16.74#ibcon#read 3, iclass 18, count 0 2006.286.04:52:16.74#ibcon#about to read 4, iclass 18, count 0 2006.286.04:52:16.74#ibcon#read 4, iclass 18, count 0 2006.286.04:52:16.74#ibcon#about to read 5, iclass 18, count 0 2006.286.04:52:16.74#ibcon#read 5, iclass 18, count 0 2006.286.04:52:16.74#ibcon#about to read 6, iclass 18, count 0 2006.286.04:52:16.74#ibcon#read 6, iclass 18, count 0 2006.286.04:52:16.74#ibcon#end of sib2, iclass 18, count 0 2006.286.04:52:16.74#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:52:16.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:52:16.74#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:52:16.74#ibcon#*before write, iclass 18, count 0 2006.286.04:52:16.74#ibcon#enter sib2, iclass 18, count 0 2006.286.04:52:16.74#ibcon#flushed, iclass 18, count 0 2006.286.04:52:16.74#ibcon#about to write, iclass 18, count 0 2006.286.04:52:16.74#ibcon#wrote, iclass 18, count 0 2006.286.04:52:16.74#ibcon#about to read 3, iclass 18, count 0 2006.286.04:52:16.78#ibcon#read 3, iclass 18, count 0 2006.286.04:52:16.78#ibcon#about to read 4, iclass 18, count 0 2006.286.04:52:16.78#ibcon#read 4, iclass 18, count 0 2006.286.04:52:16.78#ibcon#about to read 5, iclass 18, count 0 2006.286.04:52:16.78#ibcon#read 5, iclass 18, count 0 2006.286.04:52:16.78#ibcon#about to read 6, iclass 18, count 0 2006.286.04:52:16.78#ibcon#read 6, iclass 18, count 0 2006.286.04:52:16.78#ibcon#end of sib2, iclass 18, count 0 2006.286.04:52:16.78#ibcon#*after write, iclass 18, count 0 2006.286.04:52:16.78#ibcon#*before return 0, iclass 18, count 0 2006.286.04:52:16.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:52:16.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:52:16.78#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:52:16.78#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:52:16.78$vck44/va=2,6 2006.286.04:52:16.78#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.04:52:16.78#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.04:52:16.78#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:16.78#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:52:16.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:52:16.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:52:16.85#ibcon#enter wrdev, iclass 20, count 2 2006.286.04:52:16.85#ibcon#first serial, iclass 20, count 2 2006.286.04:52:16.85#ibcon#enter sib2, iclass 20, count 2 2006.286.04:52:16.85#ibcon#flushed, iclass 20, count 2 2006.286.04:52:16.85#ibcon#about to write, iclass 20, count 2 2006.286.04:52:16.85#ibcon#wrote, iclass 20, count 2 2006.286.04:52:16.85#ibcon#about to read 3, iclass 20, count 2 2006.286.04:52:16.87#ibcon#read 3, iclass 20, count 2 2006.286.04:52:16.87#ibcon#about to read 4, iclass 20, count 2 2006.286.04:52:16.87#ibcon#read 4, iclass 20, count 2 2006.286.04:52:16.87#ibcon#about to read 5, iclass 20, count 2 2006.286.04:52:16.87#ibcon#read 5, iclass 20, count 2 2006.286.04:52:16.87#ibcon#about to read 6, iclass 20, count 2 2006.286.04:52:16.87#ibcon#read 6, iclass 20, count 2 2006.286.04:52:16.87#ibcon#end of sib2, iclass 20, count 2 2006.286.04:52:16.87#ibcon#*mode == 0, iclass 20, count 2 2006.286.04:52:16.87#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.04:52:16.87#ibcon#[25=AT02-06\r\n] 2006.286.04:52:16.87#ibcon#*before write, iclass 20, count 2 2006.286.04:52:16.87#ibcon#enter sib2, iclass 20, count 2 2006.286.04:52:16.87#ibcon#flushed, iclass 20, count 2 2006.286.04:52:16.87#ibcon#about to write, iclass 20, count 2 2006.286.04:52:16.87#ibcon#wrote, iclass 20, count 2 2006.286.04:52:16.87#ibcon#about to read 3, iclass 20, count 2 2006.286.04:52:16.90#ibcon#read 3, iclass 20, count 2 2006.286.04:52:16.90#ibcon#about to read 4, iclass 20, count 2 2006.286.04:52:16.90#ibcon#read 4, iclass 20, count 2 2006.286.04:52:16.90#ibcon#about to read 5, iclass 20, count 2 2006.286.04:52:16.90#ibcon#read 5, iclass 20, count 2 2006.286.04:52:16.90#ibcon#about to read 6, iclass 20, count 2 2006.286.04:52:16.90#ibcon#read 6, iclass 20, count 2 2006.286.04:52:16.90#ibcon#end of sib2, iclass 20, count 2 2006.286.04:52:16.90#ibcon#*after write, iclass 20, count 2 2006.286.04:52:16.90#ibcon#*before return 0, iclass 20, count 2 2006.286.04:52:16.90#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:52:16.90#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:52:16.90#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.04:52:16.90#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:16.90#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:52:17.02#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:52:17.02#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:52:17.02#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:52:17.02#ibcon#first serial, iclass 20, count 0 2006.286.04:52:17.02#ibcon#enter sib2, iclass 20, count 0 2006.286.04:52:17.02#ibcon#flushed, iclass 20, count 0 2006.286.04:52:17.02#ibcon#about to write, iclass 20, count 0 2006.286.04:52:17.02#ibcon#wrote, iclass 20, count 0 2006.286.04:52:17.02#ibcon#about to read 3, iclass 20, count 0 2006.286.04:52:17.04#ibcon#read 3, iclass 20, count 0 2006.286.04:52:17.04#ibcon#about to read 4, iclass 20, count 0 2006.286.04:52:17.04#ibcon#read 4, iclass 20, count 0 2006.286.04:52:17.04#ibcon#about to read 5, iclass 20, count 0 2006.286.04:52:17.04#ibcon#read 5, iclass 20, count 0 2006.286.04:52:17.04#ibcon#about to read 6, iclass 20, count 0 2006.286.04:52:17.04#ibcon#read 6, iclass 20, count 0 2006.286.04:52:17.04#ibcon#end of sib2, iclass 20, count 0 2006.286.04:52:17.04#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:52:17.04#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:52:17.04#ibcon#[25=USB\r\n] 2006.286.04:52:17.04#ibcon#*before write, iclass 20, count 0 2006.286.04:52:17.04#ibcon#enter sib2, iclass 20, count 0 2006.286.04:52:17.04#ibcon#flushed, iclass 20, count 0 2006.286.04:52:17.04#ibcon#about to write, iclass 20, count 0 2006.286.04:52:17.04#ibcon#wrote, iclass 20, count 0 2006.286.04:52:17.04#ibcon#about to read 3, iclass 20, count 0 2006.286.04:52:17.07#ibcon#read 3, iclass 20, count 0 2006.286.04:52:17.35#ibcon#about to read 4, iclass 20, count 0 2006.286.04:52:17.35#ibcon#read 4, iclass 20, count 0 2006.286.04:52:17.35#ibcon#about to read 5, iclass 20, count 0 2006.286.04:52:17.35#ibcon#read 5, iclass 20, count 0 2006.286.04:52:17.35#ibcon#about to read 6, iclass 20, count 0 2006.286.04:52:17.35#ibcon#read 6, iclass 20, count 0 2006.286.04:52:17.35#ibcon#end of sib2, iclass 20, count 0 2006.286.04:52:17.35#ibcon#*after write, iclass 20, count 0 2006.286.04:52:17.35#ibcon#*before return 0, iclass 20, count 0 2006.286.04:52:17.35#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:52:17.35#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:52:17.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:52:17.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:52:17.35$vck44/valo=3,564.99 2006.286.04:52:17.35#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:52:17.35#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:52:17.35#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:17.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:52:17.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:52:17.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:52:17.35#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:52:17.35#ibcon#first serial, iclass 22, count 0 2006.286.04:52:17.35#ibcon#enter sib2, iclass 22, count 0 2006.286.04:52:17.35#ibcon#flushed, iclass 22, count 0 2006.286.04:52:17.35#ibcon#about to write, iclass 22, count 0 2006.286.04:52:17.35#ibcon#wrote, iclass 22, count 0 2006.286.04:52:17.35#ibcon#about to read 3, iclass 22, count 0 2006.286.04:52:17.37#ibcon#read 3, iclass 22, count 0 2006.286.04:52:17.37#ibcon#about to read 4, iclass 22, count 0 2006.286.04:52:17.37#ibcon#read 4, iclass 22, count 0 2006.286.04:52:17.37#ibcon#about to read 5, iclass 22, count 0 2006.286.04:52:17.37#ibcon#read 5, iclass 22, count 0 2006.286.04:52:17.37#ibcon#about to read 6, iclass 22, count 0 2006.286.04:52:17.37#ibcon#read 6, iclass 22, count 0 2006.286.04:52:17.37#ibcon#end of sib2, iclass 22, count 0 2006.286.04:52:17.37#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:52:17.37#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:52:17.37#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:52:17.37#ibcon#*before write, iclass 22, count 0 2006.286.04:52:17.37#ibcon#enter sib2, iclass 22, count 0 2006.286.04:52:17.37#ibcon#flushed, iclass 22, count 0 2006.286.04:52:17.37#ibcon#about to write, iclass 22, count 0 2006.286.04:52:17.37#ibcon#wrote, iclass 22, count 0 2006.286.04:52:17.37#ibcon#about to read 3, iclass 22, count 0 2006.286.04:52:17.41#ibcon#read 3, iclass 22, count 0 2006.286.04:52:17.41#ibcon#about to read 4, iclass 22, count 0 2006.286.04:52:17.41#ibcon#read 4, iclass 22, count 0 2006.286.04:52:17.41#ibcon#about to read 5, iclass 22, count 0 2006.286.04:52:17.41#ibcon#read 5, iclass 22, count 0 2006.286.04:52:17.41#ibcon#about to read 6, iclass 22, count 0 2006.286.04:52:17.41#ibcon#read 6, iclass 22, count 0 2006.286.04:52:17.41#ibcon#end of sib2, iclass 22, count 0 2006.286.04:52:17.41#ibcon#*after write, iclass 22, count 0 2006.286.04:52:17.41#ibcon#*before return 0, iclass 22, count 0 2006.286.04:52:17.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:52:17.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:52:17.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:52:17.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:52:17.41$vck44/va=3,7 2006.286.04:52:17.41#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.04:52:17.41#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.04:52:17.41#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:17.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:52:17.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:52:17.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:52:17.47#ibcon#enter wrdev, iclass 24, count 2 2006.286.04:52:17.47#ibcon#first serial, iclass 24, count 2 2006.286.04:52:17.47#ibcon#enter sib2, iclass 24, count 2 2006.286.04:52:17.47#ibcon#flushed, iclass 24, count 2 2006.286.04:52:17.47#ibcon#about to write, iclass 24, count 2 2006.286.04:52:17.47#ibcon#wrote, iclass 24, count 2 2006.286.04:52:17.47#ibcon#about to read 3, iclass 24, count 2 2006.286.04:52:17.49#ibcon#read 3, iclass 24, count 2 2006.286.04:52:17.49#ibcon#about to read 4, iclass 24, count 2 2006.286.04:52:17.49#ibcon#read 4, iclass 24, count 2 2006.286.04:52:17.49#ibcon#about to read 5, iclass 24, count 2 2006.286.04:52:17.49#ibcon#read 5, iclass 24, count 2 2006.286.04:52:17.49#ibcon#about to read 6, iclass 24, count 2 2006.286.04:52:17.49#ibcon#read 6, iclass 24, count 2 2006.286.04:52:17.49#ibcon#end of sib2, iclass 24, count 2 2006.286.04:52:17.49#ibcon#*mode == 0, iclass 24, count 2 2006.286.04:52:17.49#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.04:52:17.49#ibcon#[25=AT03-07\r\n] 2006.286.04:52:17.49#ibcon#*before write, iclass 24, count 2 2006.286.04:52:17.49#ibcon#enter sib2, iclass 24, count 2 2006.286.04:52:17.49#ibcon#flushed, iclass 24, count 2 2006.286.04:52:17.49#ibcon#about to write, iclass 24, count 2 2006.286.04:52:17.49#ibcon#wrote, iclass 24, count 2 2006.286.04:52:17.49#ibcon#about to read 3, iclass 24, count 2 2006.286.04:52:17.52#ibcon#read 3, iclass 24, count 2 2006.286.04:52:17.52#ibcon#about to read 4, iclass 24, count 2 2006.286.04:52:17.52#ibcon#read 4, iclass 24, count 2 2006.286.04:52:17.52#ibcon#about to read 5, iclass 24, count 2 2006.286.04:52:17.52#ibcon#read 5, iclass 24, count 2 2006.286.04:52:17.52#ibcon#about to read 6, iclass 24, count 2 2006.286.04:52:17.52#ibcon#read 6, iclass 24, count 2 2006.286.04:52:17.52#ibcon#end of sib2, iclass 24, count 2 2006.286.04:52:17.52#ibcon#*after write, iclass 24, count 2 2006.286.04:52:17.52#ibcon#*before return 0, iclass 24, count 2 2006.286.04:52:17.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:52:17.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:52:17.52#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.04:52:17.52#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:17.52#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:52:17.64#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:52:17.64#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:52:17.64#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:52:17.64#ibcon#first serial, iclass 24, count 0 2006.286.04:52:17.64#ibcon#enter sib2, iclass 24, count 0 2006.286.04:52:17.64#ibcon#flushed, iclass 24, count 0 2006.286.04:52:17.64#ibcon#about to write, iclass 24, count 0 2006.286.04:52:17.64#ibcon#wrote, iclass 24, count 0 2006.286.04:52:17.64#ibcon#about to read 3, iclass 24, count 0 2006.286.04:52:17.66#ibcon#read 3, iclass 24, count 0 2006.286.04:52:17.66#ibcon#about to read 4, iclass 24, count 0 2006.286.04:52:17.66#ibcon#read 4, iclass 24, count 0 2006.286.04:52:17.66#ibcon#about to read 5, iclass 24, count 0 2006.286.04:52:17.66#ibcon#read 5, iclass 24, count 0 2006.286.04:52:17.66#ibcon#about to read 6, iclass 24, count 0 2006.286.04:52:17.66#ibcon#read 6, iclass 24, count 0 2006.286.04:52:17.66#ibcon#end of sib2, iclass 24, count 0 2006.286.04:52:17.66#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:52:17.66#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:52:17.66#ibcon#[25=USB\r\n] 2006.286.04:52:17.66#ibcon#*before write, iclass 24, count 0 2006.286.04:52:17.66#ibcon#enter sib2, iclass 24, count 0 2006.286.04:52:17.66#ibcon#flushed, iclass 24, count 0 2006.286.04:52:17.66#ibcon#about to write, iclass 24, count 0 2006.286.04:52:17.66#ibcon#wrote, iclass 24, count 0 2006.286.04:52:17.66#ibcon#about to read 3, iclass 24, count 0 2006.286.04:52:17.69#ibcon#read 3, iclass 24, count 0 2006.286.04:52:17.69#ibcon#about to read 4, iclass 24, count 0 2006.286.04:52:17.69#ibcon#read 4, iclass 24, count 0 2006.286.04:52:17.69#ibcon#about to read 5, iclass 24, count 0 2006.286.04:52:17.69#ibcon#read 5, iclass 24, count 0 2006.286.04:52:17.69#ibcon#about to read 6, iclass 24, count 0 2006.286.04:52:17.69#ibcon#read 6, iclass 24, count 0 2006.286.04:52:17.69#ibcon#end of sib2, iclass 24, count 0 2006.286.04:52:17.69#ibcon#*after write, iclass 24, count 0 2006.286.04:52:17.69#ibcon#*before return 0, iclass 24, count 0 2006.286.04:52:17.69#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:52:17.69#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:52:17.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:52:17.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:52:17.69$vck44/valo=4,624.99 2006.286.04:52:17.69#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.04:52:17.69#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.04:52:17.69#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:17.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:52:17.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:52:17.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:52:17.69#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:52:17.69#ibcon#first serial, iclass 26, count 0 2006.286.04:52:17.69#ibcon#enter sib2, iclass 26, count 0 2006.286.04:52:17.69#ibcon#flushed, iclass 26, count 0 2006.286.04:52:17.69#ibcon#about to write, iclass 26, count 0 2006.286.04:52:17.69#ibcon#wrote, iclass 26, count 0 2006.286.04:52:17.69#ibcon#about to read 3, iclass 26, count 0 2006.286.04:52:17.71#ibcon#read 3, iclass 26, count 0 2006.286.04:52:17.71#ibcon#about to read 4, iclass 26, count 0 2006.286.04:52:17.71#ibcon#read 4, iclass 26, count 0 2006.286.04:52:17.71#ibcon#about to read 5, iclass 26, count 0 2006.286.04:52:17.71#ibcon#read 5, iclass 26, count 0 2006.286.04:52:17.71#ibcon#about to read 6, iclass 26, count 0 2006.286.04:52:17.71#ibcon#read 6, iclass 26, count 0 2006.286.04:52:17.71#ibcon#end of sib2, iclass 26, count 0 2006.286.04:52:17.71#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:52:17.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:52:17.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:52:17.71#ibcon#*before write, iclass 26, count 0 2006.286.04:52:17.71#ibcon#enter sib2, iclass 26, count 0 2006.286.04:52:17.71#ibcon#flushed, iclass 26, count 0 2006.286.04:52:17.71#ibcon#about to write, iclass 26, count 0 2006.286.04:52:17.71#ibcon#wrote, iclass 26, count 0 2006.286.04:52:17.71#ibcon#about to read 3, iclass 26, count 0 2006.286.04:52:17.75#ibcon#read 3, iclass 26, count 0 2006.286.04:52:17.75#ibcon#about to read 4, iclass 26, count 0 2006.286.04:52:17.75#ibcon#read 4, iclass 26, count 0 2006.286.04:52:17.75#ibcon#about to read 5, iclass 26, count 0 2006.286.04:52:17.75#ibcon#read 5, iclass 26, count 0 2006.286.04:52:17.75#ibcon#about to read 6, iclass 26, count 0 2006.286.04:52:17.75#ibcon#read 6, iclass 26, count 0 2006.286.04:52:17.75#ibcon#end of sib2, iclass 26, count 0 2006.286.04:52:17.75#ibcon#*after write, iclass 26, count 0 2006.286.04:52:17.75#ibcon#*before return 0, iclass 26, count 0 2006.286.04:52:17.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:52:17.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:52:17.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:52:17.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:52:17.75$vck44/va=4,6 2006.286.04:52:17.75#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.04:52:17.75#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.04:52:17.75#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:17.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:52:17.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:52:17.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:52:17.81#ibcon#enter wrdev, iclass 28, count 2 2006.286.04:52:17.81#ibcon#first serial, iclass 28, count 2 2006.286.04:52:17.81#ibcon#enter sib2, iclass 28, count 2 2006.286.04:52:17.81#ibcon#flushed, iclass 28, count 2 2006.286.04:52:17.81#ibcon#about to write, iclass 28, count 2 2006.286.04:52:17.81#ibcon#wrote, iclass 28, count 2 2006.286.04:52:17.81#ibcon#about to read 3, iclass 28, count 2 2006.286.04:52:17.83#ibcon#read 3, iclass 28, count 2 2006.286.04:52:17.83#ibcon#about to read 4, iclass 28, count 2 2006.286.04:52:17.83#ibcon#read 4, iclass 28, count 2 2006.286.04:52:17.83#ibcon#about to read 5, iclass 28, count 2 2006.286.04:52:17.83#ibcon#read 5, iclass 28, count 2 2006.286.04:52:17.83#ibcon#about to read 6, iclass 28, count 2 2006.286.04:52:17.83#ibcon#read 6, iclass 28, count 2 2006.286.04:52:17.83#ibcon#end of sib2, iclass 28, count 2 2006.286.04:52:17.83#ibcon#*mode == 0, iclass 28, count 2 2006.286.04:52:17.83#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.04:52:17.83#ibcon#[25=AT04-06\r\n] 2006.286.04:52:17.83#ibcon#*before write, iclass 28, count 2 2006.286.04:52:17.83#ibcon#enter sib2, iclass 28, count 2 2006.286.04:52:17.83#ibcon#flushed, iclass 28, count 2 2006.286.04:52:17.83#ibcon#about to write, iclass 28, count 2 2006.286.04:52:17.83#ibcon#wrote, iclass 28, count 2 2006.286.04:52:17.83#ibcon#about to read 3, iclass 28, count 2 2006.286.04:52:17.86#ibcon#read 3, iclass 28, count 2 2006.286.04:52:17.86#ibcon#about to read 4, iclass 28, count 2 2006.286.04:52:17.86#ibcon#read 4, iclass 28, count 2 2006.286.04:52:17.86#ibcon#about to read 5, iclass 28, count 2 2006.286.04:52:17.86#ibcon#read 5, iclass 28, count 2 2006.286.04:52:17.86#ibcon#about to read 6, iclass 28, count 2 2006.286.04:52:17.86#ibcon#read 6, iclass 28, count 2 2006.286.04:52:17.86#ibcon#end of sib2, iclass 28, count 2 2006.286.04:52:17.86#ibcon#*after write, iclass 28, count 2 2006.286.04:52:17.86#ibcon#*before return 0, iclass 28, count 2 2006.286.04:52:17.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:52:17.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:52:17.86#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.04:52:17.86#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:17.86#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:52:17.98#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:52:17.98#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:52:17.98#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:52:17.98#ibcon#first serial, iclass 28, count 0 2006.286.04:52:17.98#ibcon#enter sib2, iclass 28, count 0 2006.286.04:52:17.98#ibcon#flushed, iclass 28, count 0 2006.286.04:52:17.98#ibcon#about to write, iclass 28, count 0 2006.286.04:52:17.98#ibcon#wrote, iclass 28, count 0 2006.286.04:52:17.98#ibcon#about to read 3, iclass 28, count 0 2006.286.04:52:18.00#ibcon#read 3, iclass 28, count 0 2006.286.04:52:18.00#ibcon#about to read 4, iclass 28, count 0 2006.286.04:52:18.00#ibcon#read 4, iclass 28, count 0 2006.286.04:52:18.00#ibcon#about to read 5, iclass 28, count 0 2006.286.04:52:18.00#ibcon#read 5, iclass 28, count 0 2006.286.04:52:18.00#ibcon#about to read 6, iclass 28, count 0 2006.286.04:52:18.00#ibcon#read 6, iclass 28, count 0 2006.286.04:52:18.00#ibcon#end of sib2, iclass 28, count 0 2006.286.04:52:18.00#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:52:18.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:52:18.00#ibcon#[25=USB\r\n] 2006.286.04:52:18.00#ibcon#*before write, iclass 28, count 0 2006.286.04:52:18.00#ibcon#enter sib2, iclass 28, count 0 2006.286.04:52:18.00#ibcon#flushed, iclass 28, count 0 2006.286.04:52:18.00#ibcon#about to write, iclass 28, count 0 2006.286.04:52:18.00#ibcon#wrote, iclass 28, count 0 2006.286.04:52:18.00#ibcon#about to read 3, iclass 28, count 0 2006.286.04:52:18.03#ibcon#read 3, iclass 28, count 0 2006.286.04:52:18.03#ibcon#about to read 4, iclass 28, count 0 2006.286.04:52:18.03#ibcon#read 4, iclass 28, count 0 2006.286.04:52:18.03#ibcon#about to read 5, iclass 28, count 0 2006.286.04:52:18.03#ibcon#read 5, iclass 28, count 0 2006.286.04:52:18.03#ibcon#about to read 6, iclass 28, count 0 2006.286.04:52:18.03#ibcon#read 6, iclass 28, count 0 2006.286.04:52:18.03#ibcon#end of sib2, iclass 28, count 0 2006.286.04:52:18.03#ibcon#*after write, iclass 28, count 0 2006.286.04:52:18.03#ibcon#*before return 0, iclass 28, count 0 2006.286.04:52:18.03#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:52:18.03#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:52:18.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:52:18.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:52:18.03$vck44/valo=5,734.99 2006.286.04:52:18.03#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:52:18.03#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:52:18.03#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:18.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:52:18.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:52:18.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:52:18.03#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:52:18.03#ibcon#first serial, iclass 30, count 0 2006.286.04:52:18.03#ibcon#enter sib2, iclass 30, count 0 2006.286.04:52:18.03#ibcon#flushed, iclass 30, count 0 2006.286.04:52:18.03#ibcon#about to write, iclass 30, count 0 2006.286.04:52:18.03#ibcon#wrote, iclass 30, count 0 2006.286.04:52:18.03#ibcon#about to read 3, iclass 30, count 0 2006.286.04:52:18.05#ibcon#read 3, iclass 30, count 0 2006.286.04:52:18.05#ibcon#about to read 4, iclass 30, count 0 2006.286.04:52:18.05#ibcon#read 4, iclass 30, count 0 2006.286.04:52:18.05#ibcon#about to read 5, iclass 30, count 0 2006.286.04:52:18.05#ibcon#read 5, iclass 30, count 0 2006.286.04:52:18.05#ibcon#about to read 6, iclass 30, count 0 2006.286.04:52:18.05#ibcon#read 6, iclass 30, count 0 2006.286.04:52:18.05#ibcon#end of sib2, iclass 30, count 0 2006.286.04:52:18.05#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:52:18.05#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:52:18.05#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:52:18.05#ibcon#*before write, iclass 30, count 0 2006.286.04:52:18.05#ibcon#enter sib2, iclass 30, count 0 2006.286.04:52:18.05#ibcon#flushed, iclass 30, count 0 2006.286.04:52:18.05#ibcon#about to write, iclass 30, count 0 2006.286.04:52:18.05#ibcon#wrote, iclass 30, count 0 2006.286.04:52:18.05#ibcon#about to read 3, iclass 30, count 0 2006.286.04:52:18.09#ibcon#read 3, iclass 30, count 0 2006.286.04:52:18.09#ibcon#about to read 4, iclass 30, count 0 2006.286.04:52:18.09#ibcon#read 4, iclass 30, count 0 2006.286.04:52:18.09#ibcon#about to read 5, iclass 30, count 0 2006.286.04:52:18.09#ibcon#read 5, iclass 30, count 0 2006.286.04:52:18.09#ibcon#about to read 6, iclass 30, count 0 2006.286.04:52:18.09#ibcon#read 6, iclass 30, count 0 2006.286.04:52:18.09#ibcon#end of sib2, iclass 30, count 0 2006.286.04:52:18.09#ibcon#*after write, iclass 30, count 0 2006.286.04:52:18.09#ibcon#*before return 0, iclass 30, count 0 2006.286.04:52:18.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:52:18.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:52:18.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:52:18.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:52:18.09$vck44/va=5,3 2006.286.04:52:18.09#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.04:52:18.09#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.04:52:18.09#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:18.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:52:18.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:52:18.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:52:18.15#ibcon#enter wrdev, iclass 32, count 2 2006.286.04:52:18.15#ibcon#first serial, iclass 32, count 2 2006.286.04:52:18.15#ibcon#enter sib2, iclass 32, count 2 2006.286.04:52:18.15#ibcon#flushed, iclass 32, count 2 2006.286.04:52:18.15#ibcon#about to write, iclass 32, count 2 2006.286.04:52:18.15#ibcon#wrote, iclass 32, count 2 2006.286.04:52:18.15#ibcon#about to read 3, iclass 32, count 2 2006.286.04:52:18.17#ibcon#read 3, iclass 32, count 2 2006.286.04:52:18.17#ibcon#about to read 4, iclass 32, count 2 2006.286.04:52:18.17#ibcon#read 4, iclass 32, count 2 2006.286.04:52:18.17#ibcon#about to read 5, iclass 32, count 2 2006.286.04:52:18.17#ibcon#read 5, iclass 32, count 2 2006.286.04:52:18.17#ibcon#about to read 6, iclass 32, count 2 2006.286.04:52:18.17#ibcon#read 6, iclass 32, count 2 2006.286.04:52:18.17#ibcon#end of sib2, iclass 32, count 2 2006.286.04:52:18.17#ibcon#*mode == 0, iclass 32, count 2 2006.286.04:52:18.17#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.04:52:18.17#ibcon#[25=AT05-03\r\n] 2006.286.04:52:18.17#ibcon#*before write, iclass 32, count 2 2006.286.04:52:18.17#ibcon#enter sib2, iclass 32, count 2 2006.286.04:52:18.17#ibcon#flushed, iclass 32, count 2 2006.286.04:52:18.17#ibcon#about to write, iclass 32, count 2 2006.286.04:52:18.17#ibcon#wrote, iclass 32, count 2 2006.286.04:52:18.17#ibcon#about to read 3, iclass 32, count 2 2006.286.04:52:18.20#ibcon#read 3, iclass 32, count 2 2006.286.04:52:18.20#ibcon#about to read 4, iclass 32, count 2 2006.286.04:52:18.20#ibcon#read 4, iclass 32, count 2 2006.286.04:52:18.20#ibcon#about to read 5, iclass 32, count 2 2006.286.04:52:18.20#ibcon#read 5, iclass 32, count 2 2006.286.04:52:18.20#ibcon#about to read 6, iclass 32, count 2 2006.286.04:52:18.20#ibcon#read 6, iclass 32, count 2 2006.286.04:52:18.20#ibcon#end of sib2, iclass 32, count 2 2006.286.04:52:18.20#ibcon#*after write, iclass 32, count 2 2006.286.04:52:18.20#ibcon#*before return 0, iclass 32, count 2 2006.286.04:52:18.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:52:18.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:52:18.20#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.04:52:18.20#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:18.20#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:52:18.32#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:52:18.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:52:18.58#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:52:18.58#ibcon#first serial, iclass 32, count 0 2006.286.04:52:18.58#ibcon#enter sib2, iclass 32, count 0 2006.286.04:52:18.58#ibcon#flushed, iclass 32, count 0 2006.286.04:52:18.58#ibcon#about to write, iclass 32, count 0 2006.286.04:52:18.58#ibcon#wrote, iclass 32, count 0 2006.286.04:52:18.58#ibcon#about to read 3, iclass 32, count 0 2006.286.04:52:18.60#ibcon#read 3, iclass 32, count 0 2006.286.04:52:18.60#ibcon#about to read 4, iclass 32, count 0 2006.286.04:52:18.60#ibcon#read 4, iclass 32, count 0 2006.286.04:52:18.60#ibcon#about to read 5, iclass 32, count 0 2006.286.04:52:18.60#ibcon#read 5, iclass 32, count 0 2006.286.04:52:18.60#ibcon#about to read 6, iclass 32, count 0 2006.286.04:52:18.60#ibcon#read 6, iclass 32, count 0 2006.286.04:52:18.60#ibcon#end of sib2, iclass 32, count 0 2006.286.04:52:18.60#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:52:18.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:52:18.60#ibcon#[25=USB\r\n] 2006.286.04:52:18.60#ibcon#*before write, iclass 32, count 0 2006.286.04:52:18.60#ibcon#enter sib2, iclass 32, count 0 2006.286.04:52:18.60#ibcon#flushed, iclass 32, count 0 2006.286.04:52:18.60#ibcon#about to write, iclass 32, count 0 2006.286.04:52:18.60#ibcon#wrote, iclass 32, count 0 2006.286.04:52:18.60#ibcon#about to read 3, iclass 32, count 0 2006.286.04:52:18.63#ibcon#read 3, iclass 32, count 0 2006.286.04:52:18.63#ibcon#about to read 4, iclass 32, count 0 2006.286.04:52:18.63#ibcon#read 4, iclass 32, count 0 2006.286.04:52:18.63#ibcon#about to read 5, iclass 32, count 0 2006.286.04:52:18.63#ibcon#read 5, iclass 32, count 0 2006.286.04:52:18.63#ibcon#about to read 6, iclass 32, count 0 2006.286.04:52:18.63#ibcon#read 6, iclass 32, count 0 2006.286.04:52:18.63#ibcon#end of sib2, iclass 32, count 0 2006.286.04:52:18.63#ibcon#*after write, iclass 32, count 0 2006.286.04:52:18.63#ibcon#*before return 0, iclass 32, count 0 2006.286.04:52:18.63#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:52:18.63#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:52:18.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:52:18.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:52:18.63$vck44/valo=6,814.99 2006.286.04:52:18.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.04:52:18.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.04:52:18.63#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:18.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:52:18.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:52:18.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:52:18.63#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:52:18.63#ibcon#first serial, iclass 34, count 0 2006.286.04:52:18.63#ibcon#enter sib2, iclass 34, count 0 2006.286.04:52:18.63#ibcon#flushed, iclass 34, count 0 2006.286.04:52:18.63#ibcon#about to write, iclass 34, count 0 2006.286.04:52:18.63#ibcon#wrote, iclass 34, count 0 2006.286.04:52:18.63#ibcon#about to read 3, iclass 34, count 0 2006.286.04:52:18.65#ibcon#read 3, iclass 34, count 0 2006.286.04:52:18.65#ibcon#about to read 4, iclass 34, count 0 2006.286.04:52:18.65#ibcon#read 4, iclass 34, count 0 2006.286.04:52:18.65#ibcon#about to read 5, iclass 34, count 0 2006.286.04:52:18.65#ibcon#read 5, iclass 34, count 0 2006.286.04:52:18.65#ibcon#about to read 6, iclass 34, count 0 2006.286.04:52:18.65#ibcon#read 6, iclass 34, count 0 2006.286.04:52:18.65#ibcon#end of sib2, iclass 34, count 0 2006.286.04:52:18.65#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:52:18.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:52:18.65#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:52:18.65#ibcon#*before write, iclass 34, count 0 2006.286.04:52:18.65#ibcon#enter sib2, iclass 34, count 0 2006.286.04:52:18.65#ibcon#flushed, iclass 34, count 0 2006.286.04:52:18.65#ibcon#about to write, iclass 34, count 0 2006.286.04:52:18.65#ibcon#wrote, iclass 34, count 0 2006.286.04:52:18.65#ibcon#about to read 3, iclass 34, count 0 2006.286.04:52:18.69#ibcon#read 3, iclass 34, count 0 2006.286.04:52:18.69#ibcon#about to read 4, iclass 34, count 0 2006.286.04:52:18.69#ibcon#read 4, iclass 34, count 0 2006.286.04:52:18.69#ibcon#about to read 5, iclass 34, count 0 2006.286.04:52:18.69#ibcon#read 5, iclass 34, count 0 2006.286.04:52:18.69#ibcon#about to read 6, iclass 34, count 0 2006.286.04:52:18.69#ibcon#read 6, iclass 34, count 0 2006.286.04:52:18.69#ibcon#end of sib2, iclass 34, count 0 2006.286.04:52:18.69#ibcon#*after write, iclass 34, count 0 2006.286.04:52:18.69#ibcon#*before return 0, iclass 34, count 0 2006.286.04:52:18.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:52:18.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:52:18.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:52:18.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:52:18.69$vck44/va=6,4 2006.286.04:52:18.69#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.04:52:18.69#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.04:52:18.69#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:18.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:52:18.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:52:18.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:52:18.75#ibcon#enter wrdev, iclass 36, count 2 2006.286.04:52:18.75#ibcon#first serial, iclass 36, count 2 2006.286.04:52:18.75#ibcon#enter sib2, iclass 36, count 2 2006.286.04:52:18.75#ibcon#flushed, iclass 36, count 2 2006.286.04:52:18.75#ibcon#about to write, iclass 36, count 2 2006.286.04:52:18.75#ibcon#wrote, iclass 36, count 2 2006.286.04:52:18.75#ibcon#about to read 3, iclass 36, count 2 2006.286.04:52:18.77#ibcon#read 3, iclass 36, count 2 2006.286.04:52:18.77#ibcon#about to read 4, iclass 36, count 2 2006.286.04:52:18.77#ibcon#read 4, iclass 36, count 2 2006.286.04:52:18.77#ibcon#about to read 5, iclass 36, count 2 2006.286.04:52:18.77#ibcon#read 5, iclass 36, count 2 2006.286.04:52:18.77#ibcon#about to read 6, iclass 36, count 2 2006.286.04:52:18.77#ibcon#read 6, iclass 36, count 2 2006.286.04:52:18.77#ibcon#end of sib2, iclass 36, count 2 2006.286.04:52:18.77#ibcon#*mode == 0, iclass 36, count 2 2006.286.04:52:18.77#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.04:52:18.77#ibcon#[25=AT06-04\r\n] 2006.286.04:52:18.77#ibcon#*before write, iclass 36, count 2 2006.286.04:52:18.77#ibcon#enter sib2, iclass 36, count 2 2006.286.04:52:18.77#ibcon#flushed, iclass 36, count 2 2006.286.04:52:18.77#ibcon#about to write, iclass 36, count 2 2006.286.04:52:18.77#ibcon#wrote, iclass 36, count 2 2006.286.04:52:18.77#ibcon#about to read 3, iclass 36, count 2 2006.286.04:52:18.80#ibcon#read 3, iclass 36, count 2 2006.286.04:52:18.80#ibcon#about to read 4, iclass 36, count 2 2006.286.04:52:18.80#ibcon#read 4, iclass 36, count 2 2006.286.04:52:18.80#ibcon#about to read 5, iclass 36, count 2 2006.286.04:52:18.80#ibcon#read 5, iclass 36, count 2 2006.286.04:52:18.80#ibcon#about to read 6, iclass 36, count 2 2006.286.04:52:18.80#ibcon#read 6, iclass 36, count 2 2006.286.04:52:18.80#ibcon#end of sib2, iclass 36, count 2 2006.286.04:52:18.80#ibcon#*after write, iclass 36, count 2 2006.286.04:52:18.80#ibcon#*before return 0, iclass 36, count 2 2006.286.04:52:18.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:52:18.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:52:18.80#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.04:52:18.80#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:18.80#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:52:18.92#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:52:18.92#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:52:18.92#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:52:18.92#ibcon#first serial, iclass 36, count 0 2006.286.04:52:18.92#ibcon#enter sib2, iclass 36, count 0 2006.286.04:52:18.92#ibcon#flushed, iclass 36, count 0 2006.286.04:52:18.92#ibcon#about to write, iclass 36, count 0 2006.286.04:52:18.92#ibcon#wrote, iclass 36, count 0 2006.286.04:52:18.92#ibcon#about to read 3, iclass 36, count 0 2006.286.04:52:18.94#ibcon#read 3, iclass 36, count 0 2006.286.04:52:18.94#ibcon#about to read 4, iclass 36, count 0 2006.286.04:52:18.94#ibcon#read 4, iclass 36, count 0 2006.286.04:52:18.94#ibcon#about to read 5, iclass 36, count 0 2006.286.04:52:18.94#ibcon#read 5, iclass 36, count 0 2006.286.04:52:18.94#ibcon#about to read 6, iclass 36, count 0 2006.286.04:52:18.94#ibcon#read 6, iclass 36, count 0 2006.286.04:52:18.94#ibcon#end of sib2, iclass 36, count 0 2006.286.04:52:18.94#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:52:18.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:52:18.94#ibcon#[25=USB\r\n] 2006.286.04:52:18.94#ibcon#*before write, iclass 36, count 0 2006.286.04:52:18.94#ibcon#enter sib2, iclass 36, count 0 2006.286.04:52:18.94#ibcon#flushed, iclass 36, count 0 2006.286.04:52:18.94#ibcon#about to write, iclass 36, count 0 2006.286.04:52:18.94#ibcon#wrote, iclass 36, count 0 2006.286.04:52:18.94#ibcon#about to read 3, iclass 36, count 0 2006.286.04:52:18.97#ibcon#read 3, iclass 36, count 0 2006.286.04:52:18.97#ibcon#about to read 4, iclass 36, count 0 2006.286.04:52:18.97#ibcon#read 4, iclass 36, count 0 2006.286.04:52:18.97#ibcon#about to read 5, iclass 36, count 0 2006.286.04:52:18.97#ibcon#read 5, iclass 36, count 0 2006.286.04:52:18.97#ibcon#about to read 6, iclass 36, count 0 2006.286.04:52:18.97#ibcon#read 6, iclass 36, count 0 2006.286.04:52:18.97#ibcon#end of sib2, iclass 36, count 0 2006.286.04:52:18.97#ibcon#*after write, iclass 36, count 0 2006.286.04:52:18.97#ibcon#*before return 0, iclass 36, count 0 2006.286.04:52:18.97#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:52:18.97#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:52:18.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:52:18.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:52:18.97$vck44/valo=7,864.99 2006.286.04:52:18.97#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.04:52:18.97#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.04:52:18.97#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:18.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:52:18.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:52:18.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:52:18.97#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:52:18.97#ibcon#first serial, iclass 38, count 0 2006.286.04:52:18.97#ibcon#enter sib2, iclass 38, count 0 2006.286.04:52:18.97#ibcon#flushed, iclass 38, count 0 2006.286.04:52:18.97#ibcon#about to write, iclass 38, count 0 2006.286.04:52:18.97#ibcon#wrote, iclass 38, count 0 2006.286.04:52:18.97#ibcon#about to read 3, iclass 38, count 0 2006.286.04:52:19.03#ibcon#read 3, iclass 38, count 0 2006.286.04:52:19.03#ibcon#about to read 4, iclass 38, count 0 2006.286.04:52:19.03#ibcon#read 4, iclass 38, count 0 2006.286.04:52:19.03#ibcon#about to read 5, iclass 38, count 0 2006.286.04:52:19.03#ibcon#read 5, iclass 38, count 0 2006.286.04:52:19.03#ibcon#about to read 6, iclass 38, count 0 2006.286.04:52:19.03#ibcon#read 6, iclass 38, count 0 2006.286.04:52:19.03#ibcon#end of sib2, iclass 38, count 0 2006.286.04:52:19.03#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:52:19.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:52:19.03#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:52:19.03#ibcon#*before write, iclass 38, count 0 2006.286.04:52:19.03#ibcon#enter sib2, iclass 38, count 0 2006.286.04:52:19.03#ibcon#flushed, iclass 38, count 0 2006.286.04:52:19.03#ibcon#about to write, iclass 38, count 0 2006.286.04:52:19.03#ibcon#wrote, iclass 38, count 0 2006.286.04:52:19.03#ibcon#about to read 3, iclass 38, count 0 2006.286.04:52:19.07#ibcon#read 3, iclass 38, count 0 2006.286.04:52:19.07#ibcon#about to read 4, iclass 38, count 0 2006.286.04:52:19.07#ibcon#read 4, iclass 38, count 0 2006.286.04:52:19.07#ibcon#about to read 5, iclass 38, count 0 2006.286.04:52:19.07#ibcon#read 5, iclass 38, count 0 2006.286.04:52:19.07#ibcon#about to read 6, iclass 38, count 0 2006.286.04:52:19.07#ibcon#read 6, iclass 38, count 0 2006.286.04:52:19.07#ibcon#end of sib2, iclass 38, count 0 2006.286.04:52:19.07#ibcon#*after write, iclass 38, count 0 2006.286.04:52:19.07#ibcon#*before return 0, iclass 38, count 0 2006.286.04:52:19.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:52:19.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:52:19.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:52:19.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:52:19.07$vck44/va=7,4 2006.286.04:52:19.07#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.04:52:19.07#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.04:52:19.07#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:19.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:52:19.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:52:19.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:52:19.09#ibcon#enter wrdev, iclass 40, count 2 2006.286.04:52:19.09#ibcon#first serial, iclass 40, count 2 2006.286.04:52:19.09#ibcon#enter sib2, iclass 40, count 2 2006.286.04:52:19.09#ibcon#flushed, iclass 40, count 2 2006.286.04:52:19.09#ibcon#about to write, iclass 40, count 2 2006.286.04:52:19.09#ibcon#wrote, iclass 40, count 2 2006.286.04:52:19.09#ibcon#about to read 3, iclass 40, count 2 2006.286.04:52:19.11#ibcon#read 3, iclass 40, count 2 2006.286.04:52:19.11#ibcon#about to read 4, iclass 40, count 2 2006.286.04:52:19.11#ibcon#read 4, iclass 40, count 2 2006.286.04:52:19.11#ibcon#about to read 5, iclass 40, count 2 2006.286.04:52:19.11#ibcon#read 5, iclass 40, count 2 2006.286.04:52:19.11#ibcon#about to read 6, iclass 40, count 2 2006.286.04:52:19.11#ibcon#read 6, iclass 40, count 2 2006.286.04:52:19.11#ibcon#end of sib2, iclass 40, count 2 2006.286.04:52:19.11#ibcon#*mode == 0, iclass 40, count 2 2006.286.04:52:19.11#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.04:52:19.11#ibcon#[25=AT07-04\r\n] 2006.286.04:52:19.11#ibcon#*before write, iclass 40, count 2 2006.286.04:52:19.11#ibcon#enter sib2, iclass 40, count 2 2006.286.04:52:19.11#ibcon#flushed, iclass 40, count 2 2006.286.04:52:19.11#ibcon#about to write, iclass 40, count 2 2006.286.04:52:19.11#ibcon#wrote, iclass 40, count 2 2006.286.04:52:19.11#ibcon#about to read 3, iclass 40, count 2 2006.286.04:52:19.14#ibcon#read 3, iclass 40, count 2 2006.286.04:52:19.14#ibcon#about to read 4, iclass 40, count 2 2006.286.04:52:19.14#ibcon#read 4, iclass 40, count 2 2006.286.04:52:19.14#ibcon#about to read 5, iclass 40, count 2 2006.286.04:52:19.14#ibcon#read 5, iclass 40, count 2 2006.286.04:52:19.14#ibcon#about to read 6, iclass 40, count 2 2006.286.04:52:19.14#ibcon#read 6, iclass 40, count 2 2006.286.04:52:19.14#ibcon#end of sib2, iclass 40, count 2 2006.286.04:52:19.14#ibcon#*after write, iclass 40, count 2 2006.286.04:52:19.14#ibcon#*before return 0, iclass 40, count 2 2006.286.04:52:19.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:52:19.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:52:19.14#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.04:52:19.14#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:19.14#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:52:19.26#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:52:19.26#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:52:19.26#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:52:19.26#ibcon#first serial, iclass 40, count 0 2006.286.04:52:19.26#ibcon#enter sib2, iclass 40, count 0 2006.286.04:52:19.26#ibcon#flushed, iclass 40, count 0 2006.286.04:52:19.26#ibcon#about to write, iclass 40, count 0 2006.286.04:52:19.26#ibcon#wrote, iclass 40, count 0 2006.286.04:52:19.26#ibcon#about to read 3, iclass 40, count 0 2006.286.04:52:19.28#ibcon#read 3, iclass 40, count 0 2006.286.04:52:19.28#ibcon#about to read 4, iclass 40, count 0 2006.286.04:52:19.28#ibcon#read 4, iclass 40, count 0 2006.286.04:52:19.28#ibcon#about to read 5, iclass 40, count 0 2006.286.04:52:19.28#ibcon#read 5, iclass 40, count 0 2006.286.04:52:19.28#ibcon#about to read 6, iclass 40, count 0 2006.286.04:52:19.28#ibcon#read 6, iclass 40, count 0 2006.286.04:52:19.28#ibcon#end of sib2, iclass 40, count 0 2006.286.04:52:19.28#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:52:19.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:52:19.28#ibcon#[25=USB\r\n] 2006.286.04:52:19.28#ibcon#*before write, iclass 40, count 0 2006.286.04:52:19.28#ibcon#enter sib2, iclass 40, count 0 2006.286.04:52:19.28#ibcon#flushed, iclass 40, count 0 2006.286.04:52:19.28#ibcon#about to write, iclass 40, count 0 2006.286.04:52:19.28#ibcon#wrote, iclass 40, count 0 2006.286.04:52:19.28#ibcon#about to read 3, iclass 40, count 0 2006.286.04:52:19.31#ibcon#read 3, iclass 40, count 0 2006.286.04:52:19.31#ibcon#about to read 4, iclass 40, count 0 2006.286.04:52:19.31#ibcon#read 4, iclass 40, count 0 2006.286.04:52:19.31#ibcon#about to read 5, iclass 40, count 0 2006.286.04:52:19.31#ibcon#read 5, iclass 40, count 0 2006.286.04:52:19.31#ibcon#about to read 6, iclass 40, count 0 2006.286.04:52:19.31#ibcon#read 6, iclass 40, count 0 2006.286.04:52:19.31#ibcon#end of sib2, iclass 40, count 0 2006.286.04:52:19.31#ibcon#*after write, iclass 40, count 0 2006.286.04:52:19.31#ibcon#*before return 0, iclass 40, count 0 2006.286.04:52:19.31#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:52:19.31#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:52:19.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:52:19.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:52:19.31$vck44/valo=8,884.99 2006.286.04:52:19.31#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.04:52:19.31#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.04:52:19.31#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:19.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:52:19.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:52:19.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:52:19.31#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:52:19.31#ibcon#first serial, iclass 4, count 0 2006.286.04:52:19.31#ibcon#enter sib2, iclass 4, count 0 2006.286.04:52:19.31#ibcon#flushed, iclass 4, count 0 2006.286.04:52:19.31#ibcon#about to write, iclass 4, count 0 2006.286.04:52:19.31#ibcon#wrote, iclass 4, count 0 2006.286.04:52:19.31#ibcon#about to read 3, iclass 4, count 0 2006.286.04:52:19.33#ibcon#read 3, iclass 4, count 0 2006.286.04:52:19.33#ibcon#about to read 4, iclass 4, count 0 2006.286.04:52:19.33#ibcon#read 4, iclass 4, count 0 2006.286.04:52:19.33#ibcon#about to read 5, iclass 4, count 0 2006.286.04:52:19.33#ibcon#read 5, iclass 4, count 0 2006.286.04:52:19.33#ibcon#about to read 6, iclass 4, count 0 2006.286.04:52:19.33#ibcon#read 6, iclass 4, count 0 2006.286.04:52:19.33#ibcon#end of sib2, iclass 4, count 0 2006.286.04:52:19.33#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:52:19.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:52:19.33#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:52:19.33#ibcon#*before write, iclass 4, count 0 2006.286.04:52:19.33#ibcon#enter sib2, iclass 4, count 0 2006.286.04:52:19.33#ibcon#flushed, iclass 4, count 0 2006.286.04:52:19.33#ibcon#about to write, iclass 4, count 0 2006.286.04:52:19.33#ibcon#wrote, iclass 4, count 0 2006.286.04:52:19.33#ibcon#about to read 3, iclass 4, count 0 2006.286.04:52:19.37#ibcon#read 3, iclass 4, count 0 2006.286.04:52:19.37#ibcon#about to read 4, iclass 4, count 0 2006.286.04:52:19.37#ibcon#read 4, iclass 4, count 0 2006.286.04:52:19.37#ibcon#about to read 5, iclass 4, count 0 2006.286.04:52:19.37#ibcon#read 5, iclass 4, count 0 2006.286.04:52:19.37#ibcon#about to read 6, iclass 4, count 0 2006.286.04:52:19.37#ibcon#read 6, iclass 4, count 0 2006.286.04:52:19.37#ibcon#end of sib2, iclass 4, count 0 2006.286.04:52:19.37#ibcon#*after write, iclass 4, count 0 2006.286.04:52:19.37#ibcon#*before return 0, iclass 4, count 0 2006.286.04:52:19.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:52:19.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:52:19.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:52:19.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:52:19.37$vck44/va=8,3 2006.286.04:52:19.37#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.04:52:19.37#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.04:52:19.37#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:19.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:52:19.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:52:19.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:52:19.43#ibcon#enter wrdev, iclass 6, count 2 2006.286.04:52:19.43#ibcon#first serial, iclass 6, count 2 2006.286.04:52:19.43#ibcon#enter sib2, iclass 6, count 2 2006.286.04:52:19.43#ibcon#flushed, iclass 6, count 2 2006.286.04:52:19.43#ibcon#about to write, iclass 6, count 2 2006.286.04:52:19.43#ibcon#wrote, iclass 6, count 2 2006.286.04:52:19.43#ibcon#about to read 3, iclass 6, count 2 2006.286.04:52:19.45#ibcon#read 3, iclass 6, count 2 2006.286.04:52:19.45#ibcon#about to read 4, iclass 6, count 2 2006.286.04:52:19.45#ibcon#read 4, iclass 6, count 2 2006.286.04:52:19.45#ibcon#about to read 5, iclass 6, count 2 2006.286.04:52:19.45#ibcon#read 5, iclass 6, count 2 2006.286.04:52:19.45#ibcon#about to read 6, iclass 6, count 2 2006.286.04:52:19.45#ibcon#read 6, iclass 6, count 2 2006.286.04:52:19.45#ibcon#end of sib2, iclass 6, count 2 2006.286.04:52:19.45#ibcon#*mode == 0, iclass 6, count 2 2006.286.04:52:19.45#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.04:52:19.45#ibcon#[25=AT08-03\r\n] 2006.286.04:52:19.45#ibcon#*before write, iclass 6, count 2 2006.286.04:52:19.45#ibcon#enter sib2, iclass 6, count 2 2006.286.04:52:19.45#ibcon#flushed, iclass 6, count 2 2006.286.04:52:19.45#ibcon#about to write, iclass 6, count 2 2006.286.04:52:19.45#ibcon#wrote, iclass 6, count 2 2006.286.04:52:19.45#ibcon#about to read 3, iclass 6, count 2 2006.286.04:52:19.48#ibcon#read 3, iclass 6, count 2 2006.286.04:52:19.48#ibcon#about to read 4, iclass 6, count 2 2006.286.04:52:19.48#ibcon#read 4, iclass 6, count 2 2006.286.04:52:19.48#ibcon#about to read 5, iclass 6, count 2 2006.286.04:52:19.48#ibcon#read 5, iclass 6, count 2 2006.286.04:52:19.48#ibcon#about to read 6, iclass 6, count 2 2006.286.04:52:19.48#ibcon#read 6, iclass 6, count 2 2006.286.04:52:19.48#ibcon#end of sib2, iclass 6, count 2 2006.286.04:52:19.48#ibcon#*after write, iclass 6, count 2 2006.286.04:52:19.48#ibcon#*before return 0, iclass 6, count 2 2006.286.04:52:19.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:52:19.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:52:19.48#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.04:52:19.48#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:19.48#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:52:19.60#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:52:19.60#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:52:19.60#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:52:19.60#ibcon#first serial, iclass 6, count 0 2006.286.04:52:19.60#ibcon#enter sib2, iclass 6, count 0 2006.286.04:52:19.60#ibcon#flushed, iclass 6, count 0 2006.286.04:52:19.60#ibcon#about to write, iclass 6, count 0 2006.286.04:52:19.60#ibcon#wrote, iclass 6, count 0 2006.286.04:52:19.60#ibcon#about to read 3, iclass 6, count 0 2006.286.04:52:19.62#ibcon#read 3, iclass 6, count 0 2006.286.04:52:19.62#ibcon#about to read 4, iclass 6, count 0 2006.286.04:52:19.62#ibcon#read 4, iclass 6, count 0 2006.286.04:52:19.62#ibcon#about to read 5, iclass 6, count 0 2006.286.04:52:19.62#ibcon#read 5, iclass 6, count 0 2006.286.04:52:19.62#ibcon#about to read 6, iclass 6, count 0 2006.286.04:52:19.62#ibcon#read 6, iclass 6, count 0 2006.286.04:52:19.62#ibcon#end of sib2, iclass 6, count 0 2006.286.04:52:19.62#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:52:19.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:52:19.62#ibcon#[25=USB\r\n] 2006.286.04:52:19.62#ibcon#*before write, iclass 6, count 0 2006.286.04:52:19.62#ibcon#enter sib2, iclass 6, count 0 2006.286.04:52:19.62#ibcon#flushed, iclass 6, count 0 2006.286.04:52:19.62#ibcon#about to write, iclass 6, count 0 2006.286.04:52:19.62#ibcon#wrote, iclass 6, count 0 2006.286.04:52:19.62#ibcon#about to read 3, iclass 6, count 0 2006.286.04:52:19.65#ibcon#read 3, iclass 6, count 0 2006.286.04:52:19.65#ibcon#about to read 4, iclass 6, count 0 2006.286.04:52:19.65#ibcon#read 4, iclass 6, count 0 2006.286.04:52:19.65#ibcon#about to read 5, iclass 6, count 0 2006.286.04:52:19.65#ibcon#read 5, iclass 6, count 0 2006.286.04:52:19.65#ibcon#about to read 6, iclass 6, count 0 2006.286.04:52:19.65#ibcon#read 6, iclass 6, count 0 2006.286.04:52:19.65#ibcon#end of sib2, iclass 6, count 0 2006.286.04:52:19.65#ibcon#*after write, iclass 6, count 0 2006.286.04:52:19.65#ibcon#*before return 0, iclass 6, count 0 2006.286.04:52:19.65#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:52:19.65#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:52:19.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:52:19.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:52:19.65$vck44/vblo=1,629.99 2006.286.04:52:19.65#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.04:52:19.65#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.04:52:19.65#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:19.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:52:19.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:52:19.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:52:19.65#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:52:19.65#ibcon#first serial, iclass 10, count 0 2006.286.04:52:19.65#ibcon#enter sib2, iclass 10, count 0 2006.286.04:52:19.65#ibcon#flushed, iclass 10, count 0 2006.286.04:52:19.65#ibcon#about to write, iclass 10, count 0 2006.286.04:52:19.65#ibcon#wrote, iclass 10, count 0 2006.286.04:52:19.65#ibcon#about to read 3, iclass 10, count 0 2006.286.04:52:19.67#ibcon#read 3, iclass 10, count 0 2006.286.04:52:19.67#ibcon#about to read 4, iclass 10, count 0 2006.286.04:52:19.67#ibcon#read 4, iclass 10, count 0 2006.286.04:52:19.67#ibcon#about to read 5, iclass 10, count 0 2006.286.04:52:19.67#ibcon#read 5, iclass 10, count 0 2006.286.04:52:19.67#ibcon#about to read 6, iclass 10, count 0 2006.286.04:52:19.67#ibcon#read 6, iclass 10, count 0 2006.286.04:52:19.67#ibcon#end of sib2, iclass 10, count 0 2006.286.04:52:19.67#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:52:19.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:52:19.67#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:52:19.67#ibcon#*before write, iclass 10, count 0 2006.286.04:52:19.67#ibcon#enter sib2, iclass 10, count 0 2006.286.04:52:19.67#ibcon#flushed, iclass 10, count 0 2006.286.04:52:19.67#ibcon#about to write, iclass 10, count 0 2006.286.04:52:19.67#ibcon#wrote, iclass 10, count 0 2006.286.04:52:19.67#ibcon#about to read 3, iclass 10, count 0 2006.286.04:52:19.71#ibcon#read 3, iclass 10, count 0 2006.286.04:52:19.71#ibcon#about to read 4, iclass 10, count 0 2006.286.04:52:19.71#ibcon#read 4, iclass 10, count 0 2006.286.04:52:19.71#ibcon#about to read 5, iclass 10, count 0 2006.286.04:52:19.71#ibcon#read 5, iclass 10, count 0 2006.286.04:52:19.71#ibcon#about to read 6, iclass 10, count 0 2006.286.04:52:19.71#ibcon#read 6, iclass 10, count 0 2006.286.04:52:19.71#ibcon#end of sib2, iclass 10, count 0 2006.286.04:52:19.71#ibcon#*after write, iclass 10, count 0 2006.286.04:52:19.71#ibcon#*before return 0, iclass 10, count 0 2006.286.04:52:19.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:52:19.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:52:19.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:52:19.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:52:19.71$vck44/vb=1,4 2006.286.04:52:19.71#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.04:52:19.71#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.04:52:19.71#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:19.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:52:19.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:52:19.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:52:19.71#ibcon#enter wrdev, iclass 12, count 2 2006.286.04:52:19.71#ibcon#first serial, iclass 12, count 2 2006.286.04:52:19.71#ibcon#enter sib2, iclass 12, count 2 2006.286.04:52:19.71#ibcon#flushed, iclass 12, count 2 2006.286.04:52:19.71#ibcon#about to write, iclass 12, count 2 2006.286.04:52:19.71#ibcon#wrote, iclass 12, count 2 2006.286.04:52:19.71#ibcon#about to read 3, iclass 12, count 2 2006.286.04:52:19.73#ibcon#read 3, iclass 12, count 2 2006.286.04:52:19.73#ibcon#about to read 4, iclass 12, count 2 2006.286.04:52:19.73#ibcon#read 4, iclass 12, count 2 2006.286.04:52:19.73#ibcon#about to read 5, iclass 12, count 2 2006.286.04:52:19.73#ibcon#read 5, iclass 12, count 2 2006.286.04:52:19.73#ibcon#about to read 6, iclass 12, count 2 2006.286.04:52:19.73#ibcon#read 6, iclass 12, count 2 2006.286.04:52:19.73#ibcon#end of sib2, iclass 12, count 2 2006.286.04:52:19.73#ibcon#*mode == 0, iclass 12, count 2 2006.286.04:52:19.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.04:52:19.73#ibcon#[27=AT01-04\r\n] 2006.286.04:52:19.73#ibcon#*before write, iclass 12, count 2 2006.286.04:52:19.73#ibcon#enter sib2, iclass 12, count 2 2006.286.04:52:19.73#ibcon#flushed, iclass 12, count 2 2006.286.04:52:19.73#ibcon#about to write, iclass 12, count 2 2006.286.04:52:19.73#ibcon#wrote, iclass 12, count 2 2006.286.04:52:19.73#ibcon#about to read 3, iclass 12, count 2 2006.286.04:52:19.76#ibcon#read 3, iclass 12, count 2 2006.286.04:52:19.76#ibcon#about to read 4, iclass 12, count 2 2006.286.04:52:19.76#ibcon#read 4, iclass 12, count 2 2006.286.04:52:19.76#ibcon#about to read 5, iclass 12, count 2 2006.286.04:52:19.76#ibcon#read 5, iclass 12, count 2 2006.286.04:52:19.76#ibcon#about to read 6, iclass 12, count 2 2006.286.04:52:19.76#ibcon#read 6, iclass 12, count 2 2006.286.04:52:19.76#ibcon#end of sib2, iclass 12, count 2 2006.286.04:52:19.76#ibcon#*after write, iclass 12, count 2 2006.286.04:52:19.76#ibcon#*before return 0, iclass 12, count 2 2006.286.04:52:19.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:52:19.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:52:19.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.04:52:19.76#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:19.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:52:19.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:52:19.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:52:19.88#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:52:19.88#ibcon#first serial, iclass 12, count 0 2006.286.04:52:19.88#ibcon#enter sib2, iclass 12, count 0 2006.286.04:52:19.88#ibcon#flushed, iclass 12, count 0 2006.286.04:52:19.88#ibcon#about to write, iclass 12, count 0 2006.286.04:52:19.88#ibcon#wrote, iclass 12, count 0 2006.286.04:52:19.88#ibcon#about to read 3, iclass 12, count 0 2006.286.04:52:19.90#ibcon#read 3, iclass 12, count 0 2006.286.04:52:19.90#ibcon#about to read 4, iclass 12, count 0 2006.286.04:52:19.90#ibcon#read 4, iclass 12, count 0 2006.286.04:52:19.90#ibcon#about to read 5, iclass 12, count 0 2006.286.04:52:19.90#ibcon#read 5, iclass 12, count 0 2006.286.04:52:19.90#ibcon#about to read 6, iclass 12, count 0 2006.286.04:52:19.90#ibcon#read 6, iclass 12, count 0 2006.286.04:52:19.90#ibcon#end of sib2, iclass 12, count 0 2006.286.04:52:19.90#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:52:19.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:52:19.90#ibcon#[27=USB\r\n] 2006.286.04:52:19.90#ibcon#*before write, iclass 12, count 0 2006.286.04:52:19.90#ibcon#enter sib2, iclass 12, count 0 2006.286.04:52:19.90#ibcon#flushed, iclass 12, count 0 2006.286.04:52:19.90#ibcon#about to write, iclass 12, count 0 2006.286.04:52:19.90#ibcon#wrote, iclass 12, count 0 2006.286.04:52:19.90#ibcon#about to read 3, iclass 12, count 0 2006.286.04:52:19.93#ibcon#read 3, iclass 12, count 0 2006.286.04:52:19.93#ibcon#about to read 4, iclass 12, count 0 2006.286.04:52:19.93#ibcon#read 4, iclass 12, count 0 2006.286.04:52:19.93#ibcon#about to read 5, iclass 12, count 0 2006.286.04:52:19.93#ibcon#read 5, iclass 12, count 0 2006.286.04:52:19.93#ibcon#about to read 6, iclass 12, count 0 2006.286.04:52:19.93#ibcon#read 6, iclass 12, count 0 2006.286.04:52:19.93#ibcon#end of sib2, iclass 12, count 0 2006.286.04:52:19.93#ibcon#*after write, iclass 12, count 0 2006.286.04:52:19.93#ibcon#*before return 0, iclass 12, count 0 2006.286.04:52:19.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:52:19.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:52:19.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:52:19.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:52:19.93$vck44/vblo=2,634.99 2006.286.04:52:19.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.04:52:19.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.04:52:19.93#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:19.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:52:19.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:52:19.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:52:19.93#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:52:19.93#ibcon#first serial, iclass 14, count 0 2006.286.04:52:19.93#ibcon#enter sib2, iclass 14, count 0 2006.286.04:52:19.93#ibcon#flushed, iclass 14, count 0 2006.286.04:52:19.93#ibcon#about to write, iclass 14, count 0 2006.286.04:52:19.93#ibcon#wrote, iclass 14, count 0 2006.286.04:52:19.93#ibcon#about to read 3, iclass 14, count 0 2006.286.04:52:19.95#ibcon#read 3, iclass 14, count 0 2006.286.04:52:19.95#ibcon#about to read 4, iclass 14, count 0 2006.286.04:52:19.95#ibcon#read 4, iclass 14, count 0 2006.286.04:52:19.95#ibcon#about to read 5, iclass 14, count 0 2006.286.04:52:19.95#ibcon#read 5, iclass 14, count 0 2006.286.04:52:19.95#ibcon#about to read 6, iclass 14, count 0 2006.286.04:52:19.95#ibcon#read 6, iclass 14, count 0 2006.286.04:52:19.95#ibcon#end of sib2, iclass 14, count 0 2006.286.04:52:19.95#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:52:19.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:52:19.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:52:19.95#ibcon#*before write, iclass 14, count 0 2006.286.04:52:19.95#ibcon#enter sib2, iclass 14, count 0 2006.286.04:52:19.95#ibcon#flushed, iclass 14, count 0 2006.286.04:52:19.95#ibcon#about to write, iclass 14, count 0 2006.286.04:52:19.95#ibcon#wrote, iclass 14, count 0 2006.286.04:52:19.95#ibcon#about to read 3, iclass 14, count 0 2006.286.04:52:19.99#ibcon#read 3, iclass 14, count 0 2006.286.04:52:19.99#ibcon#about to read 4, iclass 14, count 0 2006.286.04:52:19.99#ibcon#read 4, iclass 14, count 0 2006.286.04:52:19.99#ibcon#about to read 5, iclass 14, count 0 2006.286.04:52:19.99#ibcon#read 5, iclass 14, count 0 2006.286.04:52:19.99#ibcon#about to read 6, iclass 14, count 0 2006.286.04:52:19.99#ibcon#read 6, iclass 14, count 0 2006.286.04:52:19.99#ibcon#end of sib2, iclass 14, count 0 2006.286.04:52:19.99#ibcon#*after write, iclass 14, count 0 2006.286.04:52:19.99#ibcon#*before return 0, iclass 14, count 0 2006.286.04:52:19.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:52:19.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:52:19.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:52:19.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:52:19.99$vck44/vb=2,5 2006.286.04:52:20.16#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.04:52:20.16#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.04:52:20.16#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:20.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:52:20.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:52:20.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:52:20.16#ibcon#enter wrdev, iclass 16, count 2 2006.286.04:52:20.16#ibcon#first serial, iclass 16, count 2 2006.286.04:52:20.16#ibcon#enter sib2, iclass 16, count 2 2006.286.04:52:20.16#ibcon#flushed, iclass 16, count 2 2006.286.04:52:20.16#ibcon#about to write, iclass 16, count 2 2006.286.04:52:20.16#ibcon#wrote, iclass 16, count 2 2006.286.04:52:20.16#ibcon#about to read 3, iclass 16, count 2 2006.286.04:52:20.17#ibcon#read 3, iclass 16, count 2 2006.286.04:52:20.17#ibcon#about to read 4, iclass 16, count 2 2006.286.04:52:20.17#ibcon#read 4, iclass 16, count 2 2006.286.04:52:20.17#ibcon#about to read 5, iclass 16, count 2 2006.286.04:52:20.17#ibcon#read 5, iclass 16, count 2 2006.286.04:52:20.17#ibcon#about to read 6, iclass 16, count 2 2006.286.04:52:20.17#ibcon#read 6, iclass 16, count 2 2006.286.04:52:20.17#ibcon#end of sib2, iclass 16, count 2 2006.286.04:52:20.17#ibcon#*mode == 0, iclass 16, count 2 2006.286.04:52:20.17#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.04:52:20.17#ibcon#[27=AT02-05\r\n] 2006.286.04:52:20.17#ibcon#*before write, iclass 16, count 2 2006.286.04:52:20.17#ibcon#enter sib2, iclass 16, count 2 2006.286.04:52:20.17#ibcon#flushed, iclass 16, count 2 2006.286.04:52:20.17#ibcon#about to write, iclass 16, count 2 2006.286.04:52:20.17#ibcon#wrote, iclass 16, count 2 2006.286.04:52:20.17#ibcon#about to read 3, iclass 16, count 2 2006.286.04:52:20.20#ibcon#read 3, iclass 16, count 2 2006.286.04:52:20.20#ibcon#about to read 4, iclass 16, count 2 2006.286.04:52:20.20#ibcon#read 4, iclass 16, count 2 2006.286.04:52:20.20#ibcon#about to read 5, iclass 16, count 2 2006.286.04:52:20.20#ibcon#read 5, iclass 16, count 2 2006.286.04:52:20.20#ibcon#about to read 6, iclass 16, count 2 2006.286.04:52:20.20#ibcon#read 6, iclass 16, count 2 2006.286.04:52:20.20#ibcon#end of sib2, iclass 16, count 2 2006.286.04:52:20.20#ibcon#*after write, iclass 16, count 2 2006.286.04:52:20.20#ibcon#*before return 0, iclass 16, count 2 2006.286.04:52:20.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:52:20.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:52:20.20#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.04:52:20.20#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:20.20#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:52:20.32#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:52:20.32#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:52:20.32#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:52:20.32#ibcon#first serial, iclass 16, count 0 2006.286.04:52:20.32#ibcon#enter sib2, iclass 16, count 0 2006.286.04:52:20.32#ibcon#flushed, iclass 16, count 0 2006.286.04:52:20.32#ibcon#about to write, iclass 16, count 0 2006.286.04:52:20.32#ibcon#wrote, iclass 16, count 0 2006.286.04:52:20.32#ibcon#about to read 3, iclass 16, count 0 2006.286.04:52:20.34#ibcon#read 3, iclass 16, count 0 2006.286.04:52:20.34#ibcon#about to read 4, iclass 16, count 0 2006.286.04:52:20.34#ibcon#read 4, iclass 16, count 0 2006.286.04:52:20.34#ibcon#about to read 5, iclass 16, count 0 2006.286.04:52:20.34#ibcon#read 5, iclass 16, count 0 2006.286.04:52:20.34#ibcon#about to read 6, iclass 16, count 0 2006.286.04:52:20.34#ibcon#read 6, iclass 16, count 0 2006.286.04:52:20.34#ibcon#end of sib2, iclass 16, count 0 2006.286.04:52:20.34#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:52:20.34#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:52:20.34#ibcon#[27=USB\r\n] 2006.286.04:52:20.34#ibcon#*before write, iclass 16, count 0 2006.286.04:52:20.34#ibcon#enter sib2, iclass 16, count 0 2006.286.04:52:20.34#ibcon#flushed, iclass 16, count 0 2006.286.04:52:20.34#ibcon#about to write, iclass 16, count 0 2006.286.04:52:20.34#ibcon#wrote, iclass 16, count 0 2006.286.04:52:20.34#ibcon#about to read 3, iclass 16, count 0 2006.286.04:52:20.37#ibcon#read 3, iclass 16, count 0 2006.286.04:52:20.37#ibcon#about to read 4, iclass 16, count 0 2006.286.04:52:20.37#ibcon#read 4, iclass 16, count 0 2006.286.04:52:20.37#ibcon#about to read 5, iclass 16, count 0 2006.286.04:52:20.37#ibcon#read 5, iclass 16, count 0 2006.286.04:52:20.37#ibcon#about to read 6, iclass 16, count 0 2006.286.04:52:20.37#ibcon#read 6, iclass 16, count 0 2006.286.04:52:20.37#ibcon#end of sib2, iclass 16, count 0 2006.286.04:52:20.37#ibcon#*after write, iclass 16, count 0 2006.286.04:52:20.37#ibcon#*before return 0, iclass 16, count 0 2006.286.04:52:20.37#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:52:20.37#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:52:20.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:52:20.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:52:20.37$vck44/vblo=3,649.99 2006.286.04:52:20.37#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.04:52:20.37#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.04:52:20.37#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:20.37#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:52:20.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:52:20.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:52:20.37#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:52:20.37#ibcon#first serial, iclass 18, count 0 2006.286.04:52:20.37#ibcon#enter sib2, iclass 18, count 0 2006.286.04:52:20.37#ibcon#flushed, iclass 18, count 0 2006.286.04:52:20.37#ibcon#about to write, iclass 18, count 0 2006.286.04:52:20.37#ibcon#wrote, iclass 18, count 0 2006.286.04:52:20.37#ibcon#about to read 3, iclass 18, count 0 2006.286.04:52:20.39#ibcon#read 3, iclass 18, count 0 2006.286.04:52:20.39#ibcon#about to read 4, iclass 18, count 0 2006.286.04:52:20.39#ibcon#read 4, iclass 18, count 0 2006.286.04:52:20.39#ibcon#about to read 5, iclass 18, count 0 2006.286.04:52:20.39#ibcon#read 5, iclass 18, count 0 2006.286.04:52:20.39#ibcon#about to read 6, iclass 18, count 0 2006.286.04:52:20.39#ibcon#read 6, iclass 18, count 0 2006.286.04:52:20.39#ibcon#end of sib2, iclass 18, count 0 2006.286.04:52:20.39#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:52:20.39#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:52:20.39#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:52:20.39#ibcon#*before write, iclass 18, count 0 2006.286.04:52:20.39#ibcon#enter sib2, iclass 18, count 0 2006.286.04:52:20.39#ibcon#flushed, iclass 18, count 0 2006.286.04:52:20.39#ibcon#about to write, iclass 18, count 0 2006.286.04:52:20.39#ibcon#wrote, iclass 18, count 0 2006.286.04:52:20.39#ibcon#about to read 3, iclass 18, count 0 2006.286.04:52:20.43#ibcon#read 3, iclass 18, count 0 2006.286.04:52:20.43#ibcon#about to read 4, iclass 18, count 0 2006.286.04:52:20.43#ibcon#read 4, iclass 18, count 0 2006.286.04:52:20.43#ibcon#about to read 5, iclass 18, count 0 2006.286.04:52:20.43#ibcon#read 5, iclass 18, count 0 2006.286.04:52:20.43#ibcon#about to read 6, iclass 18, count 0 2006.286.04:52:20.43#ibcon#read 6, iclass 18, count 0 2006.286.04:52:20.43#ibcon#end of sib2, iclass 18, count 0 2006.286.04:52:20.43#ibcon#*after write, iclass 18, count 0 2006.286.04:52:20.43#ibcon#*before return 0, iclass 18, count 0 2006.286.04:52:20.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:52:20.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:52:20.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:52:20.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:52:20.43$vck44/vb=3,4 2006.286.04:52:20.43#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.04:52:20.43#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.04:52:20.43#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:20.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:52:20.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:52:20.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:52:20.49#ibcon#enter wrdev, iclass 20, count 2 2006.286.04:52:20.49#ibcon#first serial, iclass 20, count 2 2006.286.04:52:20.49#ibcon#enter sib2, iclass 20, count 2 2006.286.04:52:20.49#ibcon#flushed, iclass 20, count 2 2006.286.04:52:20.49#ibcon#about to write, iclass 20, count 2 2006.286.04:52:20.49#ibcon#wrote, iclass 20, count 2 2006.286.04:52:20.49#ibcon#about to read 3, iclass 20, count 2 2006.286.04:52:20.51#ibcon#read 3, iclass 20, count 2 2006.286.04:52:20.51#ibcon#about to read 4, iclass 20, count 2 2006.286.04:52:20.51#ibcon#read 4, iclass 20, count 2 2006.286.04:52:20.51#ibcon#about to read 5, iclass 20, count 2 2006.286.04:52:20.51#ibcon#read 5, iclass 20, count 2 2006.286.04:52:20.51#ibcon#about to read 6, iclass 20, count 2 2006.286.04:52:20.51#ibcon#read 6, iclass 20, count 2 2006.286.04:52:20.51#ibcon#end of sib2, iclass 20, count 2 2006.286.04:52:20.51#ibcon#*mode == 0, iclass 20, count 2 2006.286.04:52:20.51#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.04:52:20.51#ibcon#[27=AT03-04\r\n] 2006.286.04:52:20.51#ibcon#*before write, iclass 20, count 2 2006.286.04:52:20.51#ibcon#enter sib2, iclass 20, count 2 2006.286.04:52:20.51#ibcon#flushed, iclass 20, count 2 2006.286.04:52:20.51#ibcon#about to write, iclass 20, count 2 2006.286.04:52:20.51#ibcon#wrote, iclass 20, count 2 2006.286.04:52:20.51#ibcon#about to read 3, iclass 20, count 2 2006.286.04:52:20.54#ibcon#read 3, iclass 20, count 2 2006.286.04:52:20.54#ibcon#about to read 4, iclass 20, count 2 2006.286.04:52:20.54#ibcon#read 4, iclass 20, count 2 2006.286.04:52:20.54#ibcon#about to read 5, iclass 20, count 2 2006.286.04:52:20.54#ibcon#read 5, iclass 20, count 2 2006.286.04:52:20.54#ibcon#about to read 6, iclass 20, count 2 2006.286.04:52:20.54#ibcon#read 6, iclass 20, count 2 2006.286.04:52:20.54#ibcon#end of sib2, iclass 20, count 2 2006.286.04:52:20.54#ibcon#*after write, iclass 20, count 2 2006.286.04:52:20.54#ibcon#*before return 0, iclass 20, count 2 2006.286.04:52:20.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:52:20.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:52:20.54#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.04:52:20.54#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:20.54#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:52:20.66#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:52:20.66#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:52:20.66#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:52:20.66#ibcon#first serial, iclass 20, count 0 2006.286.04:52:20.66#ibcon#enter sib2, iclass 20, count 0 2006.286.04:52:20.66#ibcon#flushed, iclass 20, count 0 2006.286.04:52:20.66#ibcon#about to write, iclass 20, count 0 2006.286.04:52:20.66#ibcon#wrote, iclass 20, count 0 2006.286.04:52:20.66#ibcon#about to read 3, iclass 20, count 0 2006.286.04:52:20.68#ibcon#read 3, iclass 20, count 0 2006.286.04:52:20.68#ibcon#about to read 4, iclass 20, count 0 2006.286.04:52:20.68#ibcon#read 4, iclass 20, count 0 2006.286.04:52:20.68#ibcon#about to read 5, iclass 20, count 0 2006.286.04:52:20.68#ibcon#read 5, iclass 20, count 0 2006.286.04:52:20.68#ibcon#about to read 6, iclass 20, count 0 2006.286.04:52:20.68#ibcon#read 6, iclass 20, count 0 2006.286.04:52:20.68#ibcon#end of sib2, iclass 20, count 0 2006.286.04:52:20.68#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:52:20.68#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:52:20.68#ibcon#[27=USB\r\n] 2006.286.04:52:20.68#ibcon#*before write, iclass 20, count 0 2006.286.04:52:20.68#ibcon#enter sib2, iclass 20, count 0 2006.286.04:52:20.68#ibcon#flushed, iclass 20, count 0 2006.286.04:52:20.68#ibcon#about to write, iclass 20, count 0 2006.286.04:52:20.68#ibcon#wrote, iclass 20, count 0 2006.286.04:52:20.68#ibcon#about to read 3, iclass 20, count 0 2006.286.04:52:20.71#ibcon#read 3, iclass 20, count 0 2006.286.04:52:20.71#ibcon#about to read 4, iclass 20, count 0 2006.286.04:52:20.71#ibcon#read 4, iclass 20, count 0 2006.286.04:52:20.71#ibcon#about to read 5, iclass 20, count 0 2006.286.04:52:20.71#ibcon#read 5, iclass 20, count 0 2006.286.04:52:20.71#ibcon#about to read 6, iclass 20, count 0 2006.286.04:52:20.71#ibcon#read 6, iclass 20, count 0 2006.286.04:52:20.71#ibcon#end of sib2, iclass 20, count 0 2006.286.04:52:20.71#ibcon#*after write, iclass 20, count 0 2006.286.04:52:20.71#ibcon#*before return 0, iclass 20, count 0 2006.286.04:52:20.71#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:52:20.71#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:52:20.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:52:20.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:52:20.71$vck44/vblo=4,679.99 2006.286.04:52:20.71#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:52:20.71#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:52:20.71#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:20.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:52:20.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:52:20.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:52:20.71#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:52:20.71#ibcon#first serial, iclass 22, count 0 2006.286.04:52:20.71#ibcon#enter sib2, iclass 22, count 0 2006.286.04:52:20.71#ibcon#flushed, iclass 22, count 0 2006.286.04:52:20.71#ibcon#about to write, iclass 22, count 0 2006.286.04:52:20.71#ibcon#wrote, iclass 22, count 0 2006.286.04:52:20.71#ibcon#about to read 3, iclass 22, count 0 2006.286.04:52:20.73#ibcon#read 3, iclass 22, count 0 2006.286.04:52:20.73#ibcon#about to read 4, iclass 22, count 0 2006.286.04:52:20.73#ibcon#read 4, iclass 22, count 0 2006.286.04:52:20.73#ibcon#about to read 5, iclass 22, count 0 2006.286.04:52:20.73#ibcon#read 5, iclass 22, count 0 2006.286.04:52:20.73#ibcon#about to read 6, iclass 22, count 0 2006.286.04:52:20.73#ibcon#read 6, iclass 22, count 0 2006.286.04:52:20.73#ibcon#end of sib2, iclass 22, count 0 2006.286.04:52:20.73#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:52:20.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:52:20.73#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:52:20.73#ibcon#*before write, iclass 22, count 0 2006.286.04:52:20.73#ibcon#enter sib2, iclass 22, count 0 2006.286.04:52:20.73#ibcon#flushed, iclass 22, count 0 2006.286.04:52:20.73#ibcon#about to write, iclass 22, count 0 2006.286.04:52:20.73#ibcon#wrote, iclass 22, count 0 2006.286.04:52:20.73#ibcon#about to read 3, iclass 22, count 0 2006.286.04:52:20.77#ibcon#read 3, iclass 22, count 0 2006.286.04:52:20.77#ibcon#about to read 4, iclass 22, count 0 2006.286.04:52:20.77#ibcon#read 4, iclass 22, count 0 2006.286.04:52:20.77#ibcon#about to read 5, iclass 22, count 0 2006.286.04:52:20.77#ibcon#read 5, iclass 22, count 0 2006.286.04:52:20.77#ibcon#about to read 6, iclass 22, count 0 2006.286.04:52:20.77#ibcon#read 6, iclass 22, count 0 2006.286.04:52:20.77#ibcon#end of sib2, iclass 22, count 0 2006.286.04:52:20.77#ibcon#*after write, iclass 22, count 0 2006.286.04:52:20.77#ibcon#*before return 0, iclass 22, count 0 2006.286.04:52:20.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:52:20.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:52:20.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:52:20.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:52:20.77$vck44/vb=4,5 2006.286.04:52:20.77#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.04:52:20.77#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.04:52:20.77#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:20.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:52:20.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:52:20.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:52:20.83#ibcon#enter wrdev, iclass 24, count 2 2006.286.04:52:20.83#ibcon#first serial, iclass 24, count 2 2006.286.04:52:20.83#ibcon#enter sib2, iclass 24, count 2 2006.286.04:52:20.83#ibcon#flushed, iclass 24, count 2 2006.286.04:52:20.83#ibcon#about to write, iclass 24, count 2 2006.286.04:52:20.83#ibcon#wrote, iclass 24, count 2 2006.286.04:52:20.83#ibcon#about to read 3, iclass 24, count 2 2006.286.04:52:20.85#ibcon#read 3, iclass 24, count 2 2006.286.04:52:20.85#ibcon#about to read 4, iclass 24, count 2 2006.286.04:52:20.85#ibcon#read 4, iclass 24, count 2 2006.286.04:52:20.85#ibcon#about to read 5, iclass 24, count 2 2006.286.04:52:20.85#ibcon#read 5, iclass 24, count 2 2006.286.04:52:20.85#ibcon#about to read 6, iclass 24, count 2 2006.286.04:52:20.85#ibcon#read 6, iclass 24, count 2 2006.286.04:52:20.85#ibcon#end of sib2, iclass 24, count 2 2006.286.04:52:20.85#ibcon#*mode == 0, iclass 24, count 2 2006.286.04:52:20.85#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.04:52:20.85#ibcon#[27=AT04-05\r\n] 2006.286.04:52:20.85#ibcon#*before write, iclass 24, count 2 2006.286.04:52:20.85#ibcon#enter sib2, iclass 24, count 2 2006.286.04:52:20.85#ibcon#flushed, iclass 24, count 2 2006.286.04:52:20.85#ibcon#about to write, iclass 24, count 2 2006.286.04:52:20.85#ibcon#wrote, iclass 24, count 2 2006.286.04:52:20.85#ibcon#about to read 3, iclass 24, count 2 2006.286.04:52:20.88#ibcon#read 3, iclass 24, count 2 2006.286.04:52:20.88#ibcon#about to read 4, iclass 24, count 2 2006.286.04:52:20.88#ibcon#read 4, iclass 24, count 2 2006.286.04:52:20.88#ibcon#about to read 5, iclass 24, count 2 2006.286.04:52:20.88#ibcon#read 5, iclass 24, count 2 2006.286.04:52:20.88#ibcon#about to read 6, iclass 24, count 2 2006.286.04:52:20.88#ibcon#read 6, iclass 24, count 2 2006.286.04:52:20.88#ibcon#end of sib2, iclass 24, count 2 2006.286.04:52:20.88#ibcon#*after write, iclass 24, count 2 2006.286.04:52:20.88#ibcon#*before return 0, iclass 24, count 2 2006.286.04:52:20.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:52:20.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:52:20.88#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.04:52:20.88#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:20.88#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:52:21.00#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:52:21.00#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:52:21.00#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:52:21.00#ibcon#first serial, iclass 24, count 0 2006.286.04:52:21.00#ibcon#enter sib2, iclass 24, count 0 2006.286.04:52:21.00#ibcon#flushed, iclass 24, count 0 2006.286.04:52:21.00#ibcon#about to write, iclass 24, count 0 2006.286.04:52:21.00#ibcon#wrote, iclass 24, count 0 2006.286.04:52:21.00#ibcon#about to read 3, iclass 24, count 0 2006.286.04:52:21.02#ibcon#read 3, iclass 24, count 0 2006.286.04:52:21.02#ibcon#about to read 4, iclass 24, count 0 2006.286.04:52:21.02#ibcon#read 4, iclass 24, count 0 2006.286.04:52:21.02#ibcon#about to read 5, iclass 24, count 0 2006.286.04:52:21.02#ibcon#read 5, iclass 24, count 0 2006.286.04:52:21.02#ibcon#about to read 6, iclass 24, count 0 2006.286.04:52:21.02#ibcon#read 6, iclass 24, count 0 2006.286.04:52:21.02#ibcon#end of sib2, iclass 24, count 0 2006.286.04:52:21.02#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:52:21.02#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:52:21.02#ibcon#[27=USB\r\n] 2006.286.04:52:21.02#ibcon#*before write, iclass 24, count 0 2006.286.04:52:21.02#ibcon#enter sib2, iclass 24, count 0 2006.286.04:52:21.02#ibcon#flushed, iclass 24, count 0 2006.286.04:52:21.02#ibcon#about to write, iclass 24, count 0 2006.286.04:52:21.02#ibcon#wrote, iclass 24, count 0 2006.286.04:52:21.02#ibcon#about to read 3, iclass 24, count 0 2006.286.04:52:21.05#ibcon#read 3, iclass 24, count 0 2006.286.04:52:21.05#ibcon#about to read 4, iclass 24, count 0 2006.286.04:52:21.05#ibcon#read 4, iclass 24, count 0 2006.286.04:52:21.05#ibcon#about to read 5, iclass 24, count 0 2006.286.04:52:21.05#ibcon#read 5, iclass 24, count 0 2006.286.04:52:21.05#ibcon#about to read 6, iclass 24, count 0 2006.286.04:52:21.05#ibcon#read 6, iclass 24, count 0 2006.286.04:52:21.05#ibcon#end of sib2, iclass 24, count 0 2006.286.04:52:21.05#ibcon#*after write, iclass 24, count 0 2006.286.04:52:21.05#ibcon#*before return 0, iclass 24, count 0 2006.286.04:52:21.05#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:52:21.05#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:52:21.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:52:21.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:52:21.05$vck44/vblo=5,709.99 2006.286.04:52:21.05#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.04:52:21.05#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.04:52:21.05#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:21.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:52:21.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:52:21.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:52:21.05#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:52:21.05#ibcon#first serial, iclass 26, count 0 2006.286.04:52:21.05#ibcon#enter sib2, iclass 26, count 0 2006.286.04:52:21.05#ibcon#flushed, iclass 26, count 0 2006.286.04:52:21.05#ibcon#about to write, iclass 26, count 0 2006.286.04:52:21.05#ibcon#wrote, iclass 26, count 0 2006.286.04:52:21.05#ibcon#about to read 3, iclass 26, count 0 2006.286.04:52:21.07#ibcon#read 3, iclass 26, count 0 2006.286.04:52:21.15#ibcon#about to read 4, iclass 26, count 0 2006.286.04:52:21.15#ibcon#read 4, iclass 26, count 0 2006.286.04:52:21.15#ibcon#about to read 5, iclass 26, count 0 2006.286.04:52:21.15#ibcon#read 5, iclass 26, count 0 2006.286.04:52:21.15#ibcon#about to read 6, iclass 26, count 0 2006.286.04:52:21.15#ibcon#read 6, iclass 26, count 0 2006.286.04:52:21.15#ibcon#end of sib2, iclass 26, count 0 2006.286.04:52:21.15#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:52:21.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:52:21.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:52:21.15#ibcon#*before write, iclass 26, count 0 2006.286.04:52:21.15#ibcon#enter sib2, iclass 26, count 0 2006.286.04:52:21.15#ibcon#flushed, iclass 26, count 0 2006.286.04:52:21.15#ibcon#about to write, iclass 26, count 0 2006.286.04:52:21.15#ibcon#wrote, iclass 26, count 0 2006.286.04:52:21.15#ibcon#about to read 3, iclass 26, count 0 2006.286.04:52:21.19#ibcon#read 3, iclass 26, count 0 2006.286.04:52:21.19#ibcon#about to read 4, iclass 26, count 0 2006.286.04:52:21.19#ibcon#read 4, iclass 26, count 0 2006.286.04:52:21.19#ibcon#about to read 5, iclass 26, count 0 2006.286.04:52:21.19#ibcon#read 5, iclass 26, count 0 2006.286.04:52:21.19#ibcon#about to read 6, iclass 26, count 0 2006.286.04:52:21.19#ibcon#read 6, iclass 26, count 0 2006.286.04:52:21.19#ibcon#end of sib2, iclass 26, count 0 2006.286.04:52:21.19#ibcon#*after write, iclass 26, count 0 2006.286.04:52:21.19#ibcon#*before return 0, iclass 26, count 0 2006.286.04:52:21.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:52:21.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:52:21.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:52:21.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:52:21.19$vck44/vb=5,4 2006.286.04:52:21.19#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.04:52:21.19#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.04:52:21.19#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:21.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:52:21.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:52:21.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:52:21.19#ibcon#enter wrdev, iclass 28, count 2 2006.286.04:52:21.19#ibcon#first serial, iclass 28, count 2 2006.286.04:52:21.19#ibcon#enter sib2, iclass 28, count 2 2006.286.04:52:21.19#ibcon#flushed, iclass 28, count 2 2006.286.04:52:21.19#ibcon#about to write, iclass 28, count 2 2006.286.04:52:21.19#ibcon#wrote, iclass 28, count 2 2006.286.04:52:21.19#ibcon#about to read 3, iclass 28, count 2 2006.286.04:52:21.21#ibcon#read 3, iclass 28, count 2 2006.286.04:52:21.21#ibcon#about to read 4, iclass 28, count 2 2006.286.04:52:21.21#ibcon#read 4, iclass 28, count 2 2006.286.04:52:21.21#ibcon#about to read 5, iclass 28, count 2 2006.286.04:52:21.21#ibcon#read 5, iclass 28, count 2 2006.286.04:52:21.21#ibcon#about to read 6, iclass 28, count 2 2006.286.04:52:21.21#ibcon#read 6, iclass 28, count 2 2006.286.04:52:21.21#ibcon#end of sib2, iclass 28, count 2 2006.286.04:52:21.21#ibcon#*mode == 0, iclass 28, count 2 2006.286.04:52:21.21#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.04:52:21.21#ibcon#[27=AT05-04\r\n] 2006.286.04:52:21.21#ibcon#*before write, iclass 28, count 2 2006.286.04:52:21.21#ibcon#enter sib2, iclass 28, count 2 2006.286.04:52:21.21#ibcon#flushed, iclass 28, count 2 2006.286.04:52:21.21#ibcon#about to write, iclass 28, count 2 2006.286.04:52:21.21#ibcon#wrote, iclass 28, count 2 2006.286.04:52:21.21#ibcon#about to read 3, iclass 28, count 2 2006.286.04:52:21.24#ibcon#read 3, iclass 28, count 2 2006.286.04:52:21.24#ibcon#about to read 4, iclass 28, count 2 2006.286.04:52:21.24#ibcon#read 4, iclass 28, count 2 2006.286.04:52:21.24#ibcon#about to read 5, iclass 28, count 2 2006.286.04:52:21.24#ibcon#read 5, iclass 28, count 2 2006.286.04:52:21.24#ibcon#about to read 6, iclass 28, count 2 2006.286.04:52:21.24#ibcon#read 6, iclass 28, count 2 2006.286.04:52:21.24#ibcon#end of sib2, iclass 28, count 2 2006.286.04:52:21.24#ibcon#*after write, iclass 28, count 2 2006.286.04:52:21.24#ibcon#*before return 0, iclass 28, count 2 2006.286.04:52:21.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:52:21.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:52:21.24#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.04:52:21.24#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:21.24#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:52:21.36#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:52:21.36#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:52:21.36#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:52:21.36#ibcon#first serial, iclass 28, count 0 2006.286.04:52:21.36#ibcon#enter sib2, iclass 28, count 0 2006.286.04:52:21.36#ibcon#flushed, iclass 28, count 0 2006.286.04:52:21.36#ibcon#about to write, iclass 28, count 0 2006.286.04:52:21.36#ibcon#wrote, iclass 28, count 0 2006.286.04:52:21.36#ibcon#about to read 3, iclass 28, count 0 2006.286.04:52:21.38#ibcon#read 3, iclass 28, count 0 2006.286.04:52:21.38#ibcon#about to read 4, iclass 28, count 0 2006.286.04:52:21.38#ibcon#read 4, iclass 28, count 0 2006.286.04:52:21.38#ibcon#about to read 5, iclass 28, count 0 2006.286.04:52:21.38#ibcon#read 5, iclass 28, count 0 2006.286.04:52:21.38#ibcon#about to read 6, iclass 28, count 0 2006.286.04:52:21.38#ibcon#read 6, iclass 28, count 0 2006.286.04:52:21.38#ibcon#end of sib2, iclass 28, count 0 2006.286.04:52:21.38#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:52:21.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:52:21.38#ibcon#[27=USB\r\n] 2006.286.04:52:21.38#ibcon#*before write, iclass 28, count 0 2006.286.04:52:21.38#ibcon#enter sib2, iclass 28, count 0 2006.286.04:52:21.38#ibcon#flushed, iclass 28, count 0 2006.286.04:52:21.38#ibcon#about to write, iclass 28, count 0 2006.286.04:52:21.38#ibcon#wrote, iclass 28, count 0 2006.286.04:52:21.38#ibcon#about to read 3, iclass 28, count 0 2006.286.04:52:21.41#ibcon#read 3, iclass 28, count 0 2006.286.04:52:21.41#ibcon#about to read 4, iclass 28, count 0 2006.286.04:52:21.41#ibcon#read 4, iclass 28, count 0 2006.286.04:52:21.41#ibcon#about to read 5, iclass 28, count 0 2006.286.04:52:21.41#ibcon#read 5, iclass 28, count 0 2006.286.04:52:21.41#ibcon#about to read 6, iclass 28, count 0 2006.286.04:52:21.41#ibcon#read 6, iclass 28, count 0 2006.286.04:52:21.41#ibcon#end of sib2, iclass 28, count 0 2006.286.04:52:21.41#ibcon#*after write, iclass 28, count 0 2006.286.04:52:21.41#ibcon#*before return 0, iclass 28, count 0 2006.286.04:52:21.41#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:52:21.41#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:52:21.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:52:21.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:52:21.41$vck44/vblo=6,719.99 2006.286.04:52:21.41#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:52:21.41#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:52:21.41#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:21.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:52:21.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:52:21.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:52:21.41#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:52:21.41#ibcon#first serial, iclass 30, count 0 2006.286.04:52:21.41#ibcon#enter sib2, iclass 30, count 0 2006.286.04:52:21.41#ibcon#flushed, iclass 30, count 0 2006.286.04:52:21.41#ibcon#about to write, iclass 30, count 0 2006.286.04:52:21.41#ibcon#wrote, iclass 30, count 0 2006.286.04:52:21.41#ibcon#about to read 3, iclass 30, count 0 2006.286.04:52:21.43#ibcon#read 3, iclass 30, count 0 2006.286.04:52:21.43#ibcon#about to read 4, iclass 30, count 0 2006.286.04:52:21.43#ibcon#read 4, iclass 30, count 0 2006.286.04:52:21.43#ibcon#about to read 5, iclass 30, count 0 2006.286.04:52:21.43#ibcon#read 5, iclass 30, count 0 2006.286.04:52:21.43#ibcon#about to read 6, iclass 30, count 0 2006.286.04:52:21.43#ibcon#read 6, iclass 30, count 0 2006.286.04:52:21.43#ibcon#end of sib2, iclass 30, count 0 2006.286.04:52:21.43#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:52:21.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:52:21.43#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:52:21.43#ibcon#*before write, iclass 30, count 0 2006.286.04:52:21.43#ibcon#enter sib2, iclass 30, count 0 2006.286.04:52:21.43#ibcon#flushed, iclass 30, count 0 2006.286.04:52:21.43#ibcon#about to write, iclass 30, count 0 2006.286.04:52:21.43#ibcon#wrote, iclass 30, count 0 2006.286.04:52:21.43#ibcon#about to read 3, iclass 30, count 0 2006.286.04:52:21.47#ibcon#read 3, iclass 30, count 0 2006.286.04:52:21.47#ibcon#about to read 4, iclass 30, count 0 2006.286.04:52:21.47#ibcon#read 4, iclass 30, count 0 2006.286.04:52:21.47#ibcon#about to read 5, iclass 30, count 0 2006.286.04:52:21.47#ibcon#read 5, iclass 30, count 0 2006.286.04:52:21.47#ibcon#about to read 6, iclass 30, count 0 2006.286.04:52:21.47#ibcon#read 6, iclass 30, count 0 2006.286.04:52:21.47#ibcon#end of sib2, iclass 30, count 0 2006.286.04:52:21.47#ibcon#*after write, iclass 30, count 0 2006.286.04:52:21.47#ibcon#*before return 0, iclass 30, count 0 2006.286.04:52:21.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:52:21.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:52:21.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:52:21.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:52:21.47$vck44/vb=6,3 2006.286.04:52:21.47#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.04:52:21.47#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.04:52:21.47#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:21.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:52:21.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:52:21.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:52:21.53#ibcon#enter wrdev, iclass 32, count 2 2006.286.04:52:21.53#ibcon#first serial, iclass 32, count 2 2006.286.04:52:21.53#ibcon#enter sib2, iclass 32, count 2 2006.286.04:52:21.53#ibcon#flushed, iclass 32, count 2 2006.286.04:52:21.53#ibcon#about to write, iclass 32, count 2 2006.286.04:52:21.53#ibcon#wrote, iclass 32, count 2 2006.286.04:52:21.53#ibcon#about to read 3, iclass 32, count 2 2006.286.04:52:21.55#ibcon#read 3, iclass 32, count 2 2006.286.04:52:21.55#ibcon#about to read 4, iclass 32, count 2 2006.286.04:52:21.55#ibcon#read 4, iclass 32, count 2 2006.286.04:52:21.55#ibcon#about to read 5, iclass 32, count 2 2006.286.04:52:21.55#ibcon#read 5, iclass 32, count 2 2006.286.04:52:21.55#ibcon#about to read 6, iclass 32, count 2 2006.286.04:52:21.55#ibcon#read 6, iclass 32, count 2 2006.286.04:52:21.55#ibcon#end of sib2, iclass 32, count 2 2006.286.04:52:21.55#ibcon#*mode == 0, iclass 32, count 2 2006.286.04:52:21.55#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.04:52:21.55#ibcon#[27=AT06-03\r\n] 2006.286.04:52:21.55#ibcon#*before write, iclass 32, count 2 2006.286.04:52:21.55#ibcon#enter sib2, iclass 32, count 2 2006.286.04:52:21.55#ibcon#flushed, iclass 32, count 2 2006.286.04:52:21.55#ibcon#about to write, iclass 32, count 2 2006.286.04:52:21.55#ibcon#wrote, iclass 32, count 2 2006.286.04:52:21.55#ibcon#about to read 3, iclass 32, count 2 2006.286.04:52:21.58#ibcon#read 3, iclass 32, count 2 2006.286.04:52:21.58#ibcon#about to read 4, iclass 32, count 2 2006.286.04:52:21.58#ibcon#read 4, iclass 32, count 2 2006.286.04:52:21.58#ibcon#about to read 5, iclass 32, count 2 2006.286.04:52:21.58#ibcon#read 5, iclass 32, count 2 2006.286.04:52:21.58#ibcon#about to read 6, iclass 32, count 2 2006.286.04:52:21.58#ibcon#read 6, iclass 32, count 2 2006.286.04:52:21.58#ibcon#end of sib2, iclass 32, count 2 2006.286.04:52:21.58#ibcon#*after write, iclass 32, count 2 2006.286.04:52:21.58#ibcon#*before return 0, iclass 32, count 2 2006.286.04:52:21.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:52:21.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:52:21.58#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.04:52:21.58#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:21.58#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:52:21.70#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:52:21.70#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:52:21.70#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:52:21.70#ibcon#first serial, iclass 32, count 0 2006.286.04:52:21.70#ibcon#enter sib2, iclass 32, count 0 2006.286.04:52:21.70#ibcon#flushed, iclass 32, count 0 2006.286.04:52:21.70#ibcon#about to write, iclass 32, count 0 2006.286.04:52:21.70#ibcon#wrote, iclass 32, count 0 2006.286.04:52:21.70#ibcon#about to read 3, iclass 32, count 0 2006.286.04:52:21.72#ibcon#read 3, iclass 32, count 0 2006.286.04:52:21.72#ibcon#about to read 4, iclass 32, count 0 2006.286.04:52:21.72#ibcon#read 4, iclass 32, count 0 2006.286.04:52:21.72#ibcon#about to read 5, iclass 32, count 0 2006.286.04:52:21.72#ibcon#read 5, iclass 32, count 0 2006.286.04:52:21.72#ibcon#about to read 6, iclass 32, count 0 2006.286.04:52:21.72#ibcon#read 6, iclass 32, count 0 2006.286.04:52:21.72#ibcon#end of sib2, iclass 32, count 0 2006.286.04:52:21.72#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:52:21.72#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:52:21.72#ibcon#[27=USB\r\n] 2006.286.04:52:21.72#ibcon#*before write, iclass 32, count 0 2006.286.04:52:21.72#ibcon#enter sib2, iclass 32, count 0 2006.286.04:52:21.72#ibcon#flushed, iclass 32, count 0 2006.286.04:52:21.72#ibcon#about to write, iclass 32, count 0 2006.286.04:52:21.72#ibcon#wrote, iclass 32, count 0 2006.286.04:52:21.72#ibcon#about to read 3, iclass 32, count 0 2006.286.04:52:21.75#ibcon#read 3, iclass 32, count 0 2006.286.04:52:21.75#ibcon#about to read 4, iclass 32, count 0 2006.286.04:52:21.75#ibcon#read 4, iclass 32, count 0 2006.286.04:52:21.75#ibcon#about to read 5, iclass 32, count 0 2006.286.04:52:21.75#ibcon#read 5, iclass 32, count 0 2006.286.04:52:21.75#ibcon#about to read 6, iclass 32, count 0 2006.286.04:52:21.75#ibcon#read 6, iclass 32, count 0 2006.286.04:52:21.75#ibcon#end of sib2, iclass 32, count 0 2006.286.04:52:21.75#ibcon#*after write, iclass 32, count 0 2006.286.04:52:21.75#ibcon#*before return 0, iclass 32, count 0 2006.286.04:52:21.75#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:52:21.75#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:52:21.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:52:21.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:52:21.75$vck44/vblo=7,734.99 2006.286.04:52:21.75#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.04:52:21.75#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.04:52:21.75#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:21.75#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:52:21.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:52:21.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:52:21.75#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:52:21.75#ibcon#first serial, iclass 34, count 0 2006.286.04:52:21.75#ibcon#enter sib2, iclass 34, count 0 2006.286.04:52:21.75#ibcon#flushed, iclass 34, count 0 2006.286.04:52:21.75#ibcon#about to write, iclass 34, count 0 2006.286.04:52:21.75#ibcon#wrote, iclass 34, count 0 2006.286.04:52:21.75#ibcon#about to read 3, iclass 34, count 0 2006.286.04:52:21.77#ibcon#read 3, iclass 34, count 0 2006.286.04:52:21.77#ibcon#about to read 4, iclass 34, count 0 2006.286.04:52:21.77#ibcon#read 4, iclass 34, count 0 2006.286.04:52:21.77#ibcon#about to read 5, iclass 34, count 0 2006.286.04:52:21.77#ibcon#read 5, iclass 34, count 0 2006.286.04:52:21.77#ibcon#about to read 6, iclass 34, count 0 2006.286.04:52:21.77#ibcon#read 6, iclass 34, count 0 2006.286.04:52:21.77#ibcon#end of sib2, iclass 34, count 0 2006.286.04:52:21.77#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:52:21.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:52:21.77#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:52:21.77#ibcon#*before write, iclass 34, count 0 2006.286.04:52:21.77#ibcon#enter sib2, iclass 34, count 0 2006.286.04:52:21.77#ibcon#flushed, iclass 34, count 0 2006.286.04:52:21.77#ibcon#about to write, iclass 34, count 0 2006.286.04:52:21.77#ibcon#wrote, iclass 34, count 0 2006.286.04:52:21.77#ibcon#about to read 3, iclass 34, count 0 2006.286.04:52:21.81#ibcon#read 3, iclass 34, count 0 2006.286.04:52:21.81#ibcon#about to read 4, iclass 34, count 0 2006.286.04:52:21.81#ibcon#read 4, iclass 34, count 0 2006.286.04:52:21.81#ibcon#about to read 5, iclass 34, count 0 2006.286.04:52:21.81#ibcon#read 5, iclass 34, count 0 2006.286.04:52:21.81#ibcon#about to read 6, iclass 34, count 0 2006.286.04:52:21.81#ibcon#read 6, iclass 34, count 0 2006.286.04:52:21.81#ibcon#end of sib2, iclass 34, count 0 2006.286.04:52:21.81#ibcon#*after write, iclass 34, count 0 2006.286.04:52:21.81#ibcon#*before return 0, iclass 34, count 0 2006.286.04:52:21.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:52:21.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:52:21.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:52:21.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:52:21.81$vck44/vb=7,4 2006.286.04:52:21.81#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.04:52:21.81#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.04:52:21.81#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:21.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:52:21.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:52:21.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:52:21.87#ibcon#enter wrdev, iclass 36, count 2 2006.286.04:52:21.87#ibcon#first serial, iclass 36, count 2 2006.286.04:52:21.87#ibcon#enter sib2, iclass 36, count 2 2006.286.04:52:21.87#ibcon#flushed, iclass 36, count 2 2006.286.04:52:21.87#ibcon#about to write, iclass 36, count 2 2006.286.04:52:21.87#ibcon#wrote, iclass 36, count 2 2006.286.04:52:21.87#ibcon#about to read 3, iclass 36, count 2 2006.286.04:52:21.89#ibcon#read 3, iclass 36, count 2 2006.286.04:52:21.89#ibcon#about to read 4, iclass 36, count 2 2006.286.04:52:21.89#ibcon#read 4, iclass 36, count 2 2006.286.04:52:21.89#ibcon#about to read 5, iclass 36, count 2 2006.286.04:52:21.89#ibcon#read 5, iclass 36, count 2 2006.286.04:52:21.89#ibcon#about to read 6, iclass 36, count 2 2006.286.04:52:21.89#ibcon#read 6, iclass 36, count 2 2006.286.04:52:21.89#ibcon#end of sib2, iclass 36, count 2 2006.286.04:52:21.89#ibcon#*mode == 0, iclass 36, count 2 2006.286.04:52:21.89#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.04:52:21.89#ibcon#[27=AT07-04\r\n] 2006.286.04:52:21.89#ibcon#*before write, iclass 36, count 2 2006.286.04:52:21.89#ibcon#enter sib2, iclass 36, count 2 2006.286.04:52:21.89#ibcon#flushed, iclass 36, count 2 2006.286.04:52:21.89#ibcon#about to write, iclass 36, count 2 2006.286.04:52:21.89#ibcon#wrote, iclass 36, count 2 2006.286.04:52:21.89#ibcon#about to read 3, iclass 36, count 2 2006.286.04:52:21.92#ibcon#read 3, iclass 36, count 2 2006.286.04:52:21.92#ibcon#about to read 4, iclass 36, count 2 2006.286.04:52:21.92#ibcon#read 4, iclass 36, count 2 2006.286.04:52:21.92#ibcon#about to read 5, iclass 36, count 2 2006.286.04:52:21.92#ibcon#read 5, iclass 36, count 2 2006.286.04:52:21.92#ibcon#about to read 6, iclass 36, count 2 2006.286.04:52:21.92#ibcon#read 6, iclass 36, count 2 2006.286.04:52:21.92#ibcon#end of sib2, iclass 36, count 2 2006.286.04:52:21.92#ibcon#*after write, iclass 36, count 2 2006.286.04:52:21.92#ibcon#*before return 0, iclass 36, count 2 2006.286.04:52:21.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:52:21.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:52:21.92#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.04:52:21.92#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:21.92#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:52:22.04#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:52:22.04#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:52:22.04#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:52:22.04#ibcon#first serial, iclass 36, count 0 2006.286.04:52:22.04#ibcon#enter sib2, iclass 36, count 0 2006.286.04:52:22.04#ibcon#flushed, iclass 36, count 0 2006.286.04:52:22.04#ibcon#about to write, iclass 36, count 0 2006.286.04:52:22.04#ibcon#wrote, iclass 36, count 0 2006.286.04:52:22.04#ibcon#about to read 3, iclass 36, count 0 2006.286.04:52:22.06#ibcon#read 3, iclass 36, count 0 2006.286.04:52:22.06#ibcon#about to read 4, iclass 36, count 0 2006.286.04:52:22.06#ibcon#read 4, iclass 36, count 0 2006.286.04:52:22.06#ibcon#about to read 5, iclass 36, count 0 2006.286.04:52:22.06#ibcon#read 5, iclass 36, count 0 2006.286.04:52:22.06#ibcon#about to read 6, iclass 36, count 0 2006.286.04:52:22.06#ibcon#read 6, iclass 36, count 0 2006.286.04:52:22.06#ibcon#end of sib2, iclass 36, count 0 2006.286.04:52:22.06#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:52:22.06#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:52:22.06#ibcon#[27=USB\r\n] 2006.286.04:52:22.06#ibcon#*before write, iclass 36, count 0 2006.286.04:52:22.06#ibcon#enter sib2, iclass 36, count 0 2006.286.04:52:22.06#ibcon#flushed, iclass 36, count 0 2006.286.04:52:22.06#ibcon#about to write, iclass 36, count 0 2006.286.04:52:22.06#ibcon#wrote, iclass 36, count 0 2006.286.04:52:22.06#ibcon#about to read 3, iclass 36, count 0 2006.286.04:52:22.09#ibcon#read 3, iclass 36, count 0 2006.286.04:52:22.09#ibcon#about to read 4, iclass 36, count 0 2006.286.04:52:22.09#ibcon#read 4, iclass 36, count 0 2006.286.04:52:22.09#ibcon#about to read 5, iclass 36, count 0 2006.286.04:52:22.09#ibcon#read 5, iclass 36, count 0 2006.286.04:52:22.09#ibcon#about to read 6, iclass 36, count 0 2006.286.04:52:22.09#ibcon#read 6, iclass 36, count 0 2006.286.04:52:22.09#ibcon#end of sib2, iclass 36, count 0 2006.286.04:52:22.09#ibcon#*after write, iclass 36, count 0 2006.286.04:52:22.09#ibcon#*before return 0, iclass 36, count 0 2006.286.04:52:22.09#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:52:22.09#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:52:22.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:52:22.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:52:22.09$vck44/vblo=8,744.99 2006.286.04:52:22.09#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.04:52:22.09#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.04:52:22.09#ibcon#ireg 17 cls_cnt 0 2006.286.04:52:22.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:52:22.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:52:22.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:52:22.09#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:52:22.09#ibcon#first serial, iclass 38, count 0 2006.286.04:52:22.09#ibcon#enter sib2, iclass 38, count 0 2006.286.04:52:22.09#ibcon#flushed, iclass 38, count 0 2006.286.04:52:22.09#ibcon#about to write, iclass 38, count 0 2006.286.04:52:22.09#ibcon#wrote, iclass 38, count 0 2006.286.04:52:22.09#ibcon#about to read 3, iclass 38, count 0 2006.286.04:52:22.11#ibcon#read 3, iclass 38, count 0 2006.286.04:52:22.28#ibcon#about to read 4, iclass 38, count 0 2006.286.04:52:22.28#ibcon#read 4, iclass 38, count 0 2006.286.04:52:22.28#ibcon#about to read 5, iclass 38, count 0 2006.286.04:52:22.28#ibcon#read 5, iclass 38, count 0 2006.286.04:52:22.28#ibcon#about to read 6, iclass 38, count 0 2006.286.04:52:22.28#ibcon#read 6, iclass 38, count 0 2006.286.04:52:22.28#ibcon#end of sib2, iclass 38, count 0 2006.286.04:52:22.28#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:52:22.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:52:22.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:52:22.28#ibcon#*before write, iclass 38, count 0 2006.286.04:52:22.28#ibcon#enter sib2, iclass 38, count 0 2006.286.04:52:22.28#ibcon#flushed, iclass 38, count 0 2006.286.04:52:22.28#ibcon#about to write, iclass 38, count 0 2006.286.04:52:22.28#ibcon#wrote, iclass 38, count 0 2006.286.04:52:22.28#ibcon#about to read 3, iclass 38, count 0 2006.286.04:52:22.32#ibcon#read 3, iclass 38, count 0 2006.286.04:52:22.32#ibcon#about to read 4, iclass 38, count 0 2006.286.04:52:22.32#ibcon#read 4, iclass 38, count 0 2006.286.04:52:22.32#ibcon#about to read 5, iclass 38, count 0 2006.286.04:52:22.32#ibcon#read 5, iclass 38, count 0 2006.286.04:52:22.32#ibcon#about to read 6, iclass 38, count 0 2006.286.04:52:22.32#ibcon#read 6, iclass 38, count 0 2006.286.04:52:22.32#ibcon#end of sib2, iclass 38, count 0 2006.286.04:52:22.32#ibcon#*after write, iclass 38, count 0 2006.286.04:52:22.32#ibcon#*before return 0, iclass 38, count 0 2006.286.04:52:22.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:52:22.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:52:22.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:52:22.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:52:22.32$vck44/vb=8,4 2006.286.04:52:22.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.04:52:22.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.04:52:22.32#ibcon#ireg 11 cls_cnt 2 2006.286.04:52:22.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:52:22.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:52:22.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:52:22.32#ibcon#enter wrdev, iclass 40, count 2 2006.286.04:52:22.32#ibcon#first serial, iclass 40, count 2 2006.286.04:52:22.32#ibcon#enter sib2, iclass 40, count 2 2006.286.04:52:22.32#ibcon#flushed, iclass 40, count 2 2006.286.04:52:22.32#ibcon#about to write, iclass 40, count 2 2006.286.04:52:22.32#ibcon#wrote, iclass 40, count 2 2006.286.04:52:22.32#ibcon#about to read 3, iclass 40, count 2 2006.286.04:52:22.34#ibcon#read 3, iclass 40, count 2 2006.286.04:52:22.34#ibcon#about to read 4, iclass 40, count 2 2006.286.04:52:22.34#ibcon#read 4, iclass 40, count 2 2006.286.04:52:22.34#ibcon#about to read 5, iclass 40, count 2 2006.286.04:52:22.34#ibcon#read 5, iclass 40, count 2 2006.286.04:52:22.34#ibcon#about to read 6, iclass 40, count 2 2006.286.04:52:22.34#ibcon#read 6, iclass 40, count 2 2006.286.04:52:22.34#ibcon#end of sib2, iclass 40, count 2 2006.286.04:52:22.34#ibcon#*mode == 0, iclass 40, count 2 2006.286.04:52:22.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.04:52:22.34#ibcon#[27=AT08-04\r\n] 2006.286.04:52:22.34#ibcon#*before write, iclass 40, count 2 2006.286.04:52:22.34#ibcon#enter sib2, iclass 40, count 2 2006.286.04:52:22.34#ibcon#flushed, iclass 40, count 2 2006.286.04:52:22.34#ibcon#about to write, iclass 40, count 2 2006.286.04:52:22.34#ibcon#wrote, iclass 40, count 2 2006.286.04:52:22.34#ibcon#about to read 3, iclass 40, count 2 2006.286.04:52:22.37#ibcon#read 3, iclass 40, count 2 2006.286.04:52:22.37#ibcon#about to read 4, iclass 40, count 2 2006.286.04:52:22.37#ibcon#read 4, iclass 40, count 2 2006.286.04:52:22.37#ibcon#about to read 5, iclass 40, count 2 2006.286.04:52:22.37#ibcon#read 5, iclass 40, count 2 2006.286.04:52:22.37#ibcon#about to read 6, iclass 40, count 2 2006.286.04:52:22.37#ibcon#read 6, iclass 40, count 2 2006.286.04:52:22.37#ibcon#end of sib2, iclass 40, count 2 2006.286.04:52:22.37#ibcon#*after write, iclass 40, count 2 2006.286.04:52:22.37#ibcon#*before return 0, iclass 40, count 2 2006.286.04:52:22.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:52:22.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:52:22.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.04:52:22.37#ibcon#ireg 7 cls_cnt 0 2006.286.04:52:22.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:52:22.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:52:22.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:52:22.49#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:52:22.49#ibcon#first serial, iclass 40, count 0 2006.286.04:52:22.49#ibcon#enter sib2, iclass 40, count 0 2006.286.04:52:22.49#ibcon#flushed, iclass 40, count 0 2006.286.04:52:22.49#ibcon#about to write, iclass 40, count 0 2006.286.04:52:22.49#ibcon#wrote, iclass 40, count 0 2006.286.04:52:22.49#ibcon#about to read 3, iclass 40, count 0 2006.286.04:52:22.51#ibcon#read 3, iclass 40, count 0 2006.286.04:52:22.51#ibcon#about to read 4, iclass 40, count 0 2006.286.04:52:22.51#ibcon#read 4, iclass 40, count 0 2006.286.04:52:22.51#ibcon#about to read 5, iclass 40, count 0 2006.286.04:52:22.51#ibcon#read 5, iclass 40, count 0 2006.286.04:52:22.51#ibcon#about to read 6, iclass 40, count 0 2006.286.04:52:22.51#ibcon#read 6, iclass 40, count 0 2006.286.04:52:22.51#ibcon#end of sib2, iclass 40, count 0 2006.286.04:52:22.51#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:52:22.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:52:22.51#ibcon#[27=USB\r\n] 2006.286.04:52:22.51#ibcon#*before write, iclass 40, count 0 2006.286.04:52:22.51#ibcon#enter sib2, iclass 40, count 0 2006.286.04:52:22.51#ibcon#flushed, iclass 40, count 0 2006.286.04:52:22.51#ibcon#about to write, iclass 40, count 0 2006.286.04:52:22.51#ibcon#wrote, iclass 40, count 0 2006.286.04:52:22.51#ibcon#about to read 3, iclass 40, count 0 2006.286.04:52:22.54#ibcon#read 3, iclass 40, count 0 2006.286.04:52:22.54#ibcon#about to read 4, iclass 40, count 0 2006.286.04:52:22.54#ibcon#read 4, iclass 40, count 0 2006.286.04:52:22.54#ibcon#about to read 5, iclass 40, count 0 2006.286.04:52:22.54#ibcon#read 5, iclass 40, count 0 2006.286.04:52:22.54#ibcon#about to read 6, iclass 40, count 0 2006.286.04:52:22.54#ibcon#read 6, iclass 40, count 0 2006.286.04:52:22.54#ibcon#end of sib2, iclass 40, count 0 2006.286.04:52:22.54#ibcon#*after write, iclass 40, count 0 2006.286.04:52:22.54#ibcon#*before return 0, iclass 40, count 0 2006.286.04:52:22.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:52:22.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:52:22.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:52:22.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:52:22.54$vck44/vabw=wide 2006.286.04:52:22.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.04:52:22.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.04:52:22.54#ibcon#ireg 8 cls_cnt 0 2006.286.04:52:22.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:52:22.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:52:22.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:52:22.54#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:52:22.54#ibcon#first serial, iclass 4, count 0 2006.286.04:52:22.54#ibcon#enter sib2, iclass 4, count 0 2006.286.04:52:22.54#ibcon#flushed, iclass 4, count 0 2006.286.04:52:22.54#ibcon#about to write, iclass 4, count 0 2006.286.04:52:22.54#ibcon#wrote, iclass 4, count 0 2006.286.04:52:22.54#ibcon#about to read 3, iclass 4, count 0 2006.286.04:52:22.56#ibcon#read 3, iclass 4, count 0 2006.286.04:52:22.56#ibcon#about to read 4, iclass 4, count 0 2006.286.04:52:22.56#ibcon#read 4, iclass 4, count 0 2006.286.04:52:22.56#ibcon#about to read 5, iclass 4, count 0 2006.286.04:52:22.56#ibcon#read 5, iclass 4, count 0 2006.286.04:52:22.56#ibcon#about to read 6, iclass 4, count 0 2006.286.04:52:22.56#ibcon#read 6, iclass 4, count 0 2006.286.04:52:22.56#ibcon#end of sib2, iclass 4, count 0 2006.286.04:52:22.56#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:52:22.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:52:22.56#ibcon#[25=BW32\r\n] 2006.286.04:52:22.56#ibcon#*before write, iclass 4, count 0 2006.286.04:52:22.56#ibcon#enter sib2, iclass 4, count 0 2006.286.04:52:22.56#ibcon#flushed, iclass 4, count 0 2006.286.04:52:22.56#ibcon#about to write, iclass 4, count 0 2006.286.04:52:22.56#ibcon#wrote, iclass 4, count 0 2006.286.04:52:22.56#ibcon#about to read 3, iclass 4, count 0 2006.286.04:52:22.59#ibcon#read 3, iclass 4, count 0 2006.286.04:52:22.59#ibcon#about to read 4, iclass 4, count 0 2006.286.04:52:22.59#ibcon#read 4, iclass 4, count 0 2006.286.04:52:22.59#ibcon#about to read 5, iclass 4, count 0 2006.286.04:52:22.59#ibcon#read 5, iclass 4, count 0 2006.286.04:52:22.59#ibcon#about to read 6, iclass 4, count 0 2006.286.04:52:22.59#ibcon#read 6, iclass 4, count 0 2006.286.04:52:22.59#ibcon#end of sib2, iclass 4, count 0 2006.286.04:52:22.59#ibcon#*after write, iclass 4, count 0 2006.286.04:52:22.59#ibcon#*before return 0, iclass 4, count 0 2006.286.04:52:22.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:52:22.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:52:22.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:52:22.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:52:22.59$vck44/vbbw=wide 2006.286.04:52:22.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.04:52:22.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.04:52:22.59#ibcon#ireg 8 cls_cnt 0 2006.286.04:52:22.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:52:22.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:52:22.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:52:22.66#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:52:22.66#ibcon#first serial, iclass 6, count 0 2006.286.04:52:22.66#ibcon#enter sib2, iclass 6, count 0 2006.286.04:52:22.66#ibcon#flushed, iclass 6, count 0 2006.286.04:52:22.66#ibcon#about to write, iclass 6, count 0 2006.286.04:52:22.66#ibcon#wrote, iclass 6, count 0 2006.286.04:52:22.66#ibcon#about to read 3, iclass 6, count 0 2006.286.04:52:22.68#ibcon#read 3, iclass 6, count 0 2006.286.04:52:22.68#ibcon#about to read 4, iclass 6, count 0 2006.286.04:52:22.68#ibcon#read 4, iclass 6, count 0 2006.286.04:52:22.68#ibcon#about to read 5, iclass 6, count 0 2006.286.04:52:22.68#ibcon#read 5, iclass 6, count 0 2006.286.04:52:22.68#ibcon#about to read 6, iclass 6, count 0 2006.286.04:52:22.68#ibcon#read 6, iclass 6, count 0 2006.286.04:52:22.68#ibcon#end of sib2, iclass 6, count 0 2006.286.04:52:22.68#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:52:22.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:52:22.68#ibcon#[27=BW32\r\n] 2006.286.04:52:22.68#ibcon#*before write, iclass 6, count 0 2006.286.04:52:22.68#ibcon#enter sib2, iclass 6, count 0 2006.286.04:52:22.68#ibcon#flushed, iclass 6, count 0 2006.286.04:52:22.68#ibcon#about to write, iclass 6, count 0 2006.286.04:52:22.68#ibcon#wrote, iclass 6, count 0 2006.286.04:52:22.68#ibcon#about to read 3, iclass 6, count 0 2006.286.04:52:22.71#ibcon#read 3, iclass 6, count 0 2006.286.04:52:22.71#ibcon#about to read 4, iclass 6, count 0 2006.286.04:52:22.71#ibcon#read 4, iclass 6, count 0 2006.286.04:52:22.71#ibcon#about to read 5, iclass 6, count 0 2006.286.04:52:22.71#ibcon#read 5, iclass 6, count 0 2006.286.04:52:22.71#ibcon#about to read 6, iclass 6, count 0 2006.286.04:52:22.71#ibcon#read 6, iclass 6, count 0 2006.286.04:52:22.71#ibcon#end of sib2, iclass 6, count 0 2006.286.04:52:22.71#ibcon#*after write, iclass 6, count 0 2006.286.04:52:22.71#ibcon#*before return 0, iclass 6, count 0 2006.286.04:52:22.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:52:22.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.04:52:22.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:52:22.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:52:22.71$setupk4/ifdk4 2006.286.04:52:22.71$ifdk4/lo= 2006.286.04:52:22.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:52:22.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:52:22.71$ifdk4/patch= 2006.286.04:52:22.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:52:22.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:52:22.71$setupk4/!*+20s 2006.286.04:52:24.15#abcon#<5=/04 4.0 8.6 22.15 751014.9\r\n> 2006.286.04:52:24.17#abcon#{5=INTERFACE CLEAR} 2006.286.04:52:24.23#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:52:34.32#abcon#<5=/04 4.0 8.6 22.15 751014.9\r\n> 2006.286.04:52:34.34#abcon#{5=INTERFACE CLEAR} 2006.286.04:52:34.40#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:52:36.43$setupk4/"tpicd 2006.286.04:52:36.43$setupk4/echo=off 2006.286.04:52:36.43$setupk4/xlog=off 2006.286.04:52:36.43:!2006.286.04:57:21 2006.286.04:52:37.14#trakl#Source acquired 2006.286.04:52:37.14#flagr#flagr/antenna,acquired 2006.286.04:57:21.00:preob 2006.286.04:57:21.13/onsource/TRACKING 2006.286.04:57:21.13:!2006.286.04:57:31 2006.286.04:57:31.00:"tape 2006.286.04:57:31.00:"st=record 2006.286.04:57:31.00:data_valid=on 2006.286.04:57:31.00:midob 2006.286.04:57:31.13/onsource/TRACKING 2006.286.04:57:31.13/wx/22.10,1014.9,74 2006.286.04:57:31.19/cable/+6.4934E-03 2006.286.04:57:32.28/va/01,07,usb,yes,38,41 2006.286.04:57:32.28/va/02,06,usb,yes,38,38 2006.286.04:57:32.28/va/03,07,usb,yes,37,39 2006.286.04:57:32.28/va/04,06,usb,yes,39,41 2006.286.04:57:32.28/va/05,03,usb,yes,39,39 2006.286.04:57:32.28/va/06,04,usb,yes,35,34 2006.286.04:57:32.28/va/07,04,usb,yes,35,36 2006.286.04:57:32.28/va/08,03,usb,yes,36,44 2006.286.04:57:32.51/valo/01,524.99,yes,locked 2006.286.04:57:32.51/valo/02,534.99,yes,locked 2006.286.04:57:32.51/valo/03,564.99,yes,locked 2006.286.04:57:32.51/valo/04,624.99,yes,locked 2006.286.04:57:32.51/valo/05,734.99,yes,locked 2006.286.04:57:32.51/valo/06,814.99,yes,locked 2006.286.04:57:32.51/valo/07,864.99,yes,locked 2006.286.04:57:32.51/valo/08,884.99,yes,locked 2006.286.04:57:33.60/vb/01,04,usb,yes,33,31 2006.286.04:57:33.60/vb/02,05,usb,yes,32,31 2006.286.04:57:33.60/vb/03,04,usb,yes,33,36 2006.286.04:57:33.60/vb/04,05,usb,yes,33,32 2006.286.04:57:33.60/vb/05,04,usb,yes,29,32 2006.286.04:57:33.60/vb/06,03,usb,yes,42,37 2006.286.04:57:33.60/vb/07,04,usb,yes,34,34 2006.286.04:57:33.60/vb/08,04,usb,yes,31,35 2006.286.04:57:33.84/vblo/01,629.99,yes,locked 2006.286.04:57:33.84/vblo/02,634.99,yes,locked 2006.286.04:57:33.84/vblo/03,649.99,yes,locked 2006.286.04:57:33.84/vblo/04,679.99,yes,locked 2006.286.04:57:33.84/vblo/05,709.99,yes,locked 2006.286.04:57:33.84/vblo/06,719.99,yes,locked 2006.286.04:57:33.84/vblo/07,734.99,yes,locked 2006.286.04:57:33.84/vblo/08,744.99,yes,locked 2006.286.04:57:33.99/vabw/8 2006.286.04:57:34.14/vbbw/8 2006.286.04:57:34.23/xfe/off,on,12.2 2006.286.04:57:34.63/ifatt/23,28,28,28 2006.286.04:57:35.08/fmout-gps/S +2.39E-07 2006.286.04:57:35.10:!2006.286.04:58:11 2006.286.04:58:11.00:data_valid=off 2006.286.04:58:11.00:"et 2006.286.04:58:11.00:!+3s 2006.286.04:58:14.01:"tape 2006.286.04:58:14.01:postob 2006.286.04:58:14.07/cable/+6.4931E-03 2006.286.04:58:14.07/wx/22.09,1014.9,75 2006.286.04:58:15.08/fmout-gps/S +2.39E-07 2006.286.04:58:15.08:scan_name=286-0458,jd0610,40 2006.286.04:58:15.08:source=2121+053,212344.52,053522.1,2000.0,cw 2006.286.04:58:16.13#flagr#flagr/antenna,new-source 2006.286.04:58:16.13:checkk5 2006.286.04:58:16.61/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:58:17.04/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:58:17.41/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:58:17.83/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:58:18.21/chk_obsdata//k5ts1/T2860457??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:58:18.71/chk_obsdata//k5ts2/T2860457??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:58:19.12/chk_obsdata//k5ts3/T2860457??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:58:19.63/chk_obsdata//k5ts4/T2860457??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:58:20.44/k5log//k5ts1_log_newline 2006.286.04:58:21.25/k5log//k5ts2_log_newline 2006.286.04:58:22.00/k5log//k5ts3_log_newline 2006.286.04:58:23.29/k5log//k5ts4_log_newline 2006.286.04:58:23.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:58:23.31:setupk4=1 2006.286.04:58:23.31$setupk4/echo=on 2006.286.04:58:23.31$setupk4/pcalon 2006.286.04:58:23.31$pcalon/"no phase cal control is implemented here 2006.286.04:58:23.31$setupk4/"tpicd=stop 2006.286.04:58:23.31$setupk4/"rec=synch_on 2006.286.04:58:23.31$setupk4/"rec_mode=128 2006.286.04:58:23.31$setupk4/!* 2006.286.04:58:23.31$setupk4/recpk4 2006.286.04:58:23.31$recpk4/recpatch= 2006.286.04:58:23.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:58:23.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:58:23.31$setupk4/vck44 2006.286.04:58:23.31$vck44/valo=1,524.99 2006.286.04:58:23.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.04:58:23.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.04:58:23.31#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:23.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:58:23.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:58:23.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:58:23.31#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:58:23.31#ibcon#first serial, iclass 13, count 0 2006.286.04:58:23.31#ibcon#enter sib2, iclass 13, count 0 2006.286.04:58:23.31#ibcon#flushed, iclass 13, count 0 2006.286.04:58:23.31#ibcon#about to write, iclass 13, count 0 2006.286.04:58:23.32#ibcon#wrote, iclass 13, count 0 2006.286.04:58:23.32#ibcon#about to read 3, iclass 13, count 0 2006.286.04:58:23.33#ibcon#read 3, iclass 13, count 0 2006.286.04:58:23.33#ibcon#about to read 4, iclass 13, count 0 2006.286.04:58:23.33#ibcon#read 4, iclass 13, count 0 2006.286.04:58:23.33#ibcon#about to read 5, iclass 13, count 0 2006.286.04:58:23.33#ibcon#read 5, iclass 13, count 0 2006.286.04:58:23.33#ibcon#about to read 6, iclass 13, count 0 2006.286.04:58:23.33#ibcon#read 6, iclass 13, count 0 2006.286.04:58:23.33#ibcon#end of sib2, iclass 13, count 0 2006.286.04:58:23.33#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:58:23.33#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:58:23.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:58:23.33#ibcon#*before write, iclass 13, count 0 2006.286.04:58:23.33#ibcon#enter sib2, iclass 13, count 0 2006.286.04:58:23.33#ibcon#flushed, iclass 13, count 0 2006.286.04:58:23.33#ibcon#about to write, iclass 13, count 0 2006.286.04:58:23.33#ibcon#wrote, iclass 13, count 0 2006.286.04:58:23.33#ibcon#about to read 3, iclass 13, count 0 2006.286.04:58:23.38#ibcon#read 3, iclass 13, count 0 2006.286.04:58:23.38#ibcon#about to read 4, iclass 13, count 0 2006.286.04:58:23.38#ibcon#read 4, iclass 13, count 0 2006.286.04:58:23.38#ibcon#about to read 5, iclass 13, count 0 2006.286.04:58:23.38#ibcon#read 5, iclass 13, count 0 2006.286.04:58:23.38#ibcon#about to read 6, iclass 13, count 0 2006.286.04:58:23.38#ibcon#read 6, iclass 13, count 0 2006.286.04:58:23.38#ibcon#end of sib2, iclass 13, count 0 2006.286.04:58:23.38#ibcon#*after write, iclass 13, count 0 2006.286.04:58:23.38#ibcon#*before return 0, iclass 13, count 0 2006.286.04:58:23.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:58:23.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:58:23.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:58:23.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:58:23.38$vck44/va=1,7 2006.286.04:58:23.38#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.04:58:23.38#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.04:58:23.38#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:23.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:58:23.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:58:23.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:58:23.38#ibcon#enter wrdev, iclass 15, count 2 2006.286.04:58:23.38#ibcon#first serial, iclass 15, count 2 2006.286.04:58:23.38#ibcon#enter sib2, iclass 15, count 2 2006.286.04:58:23.38#ibcon#flushed, iclass 15, count 2 2006.286.04:58:23.38#ibcon#about to write, iclass 15, count 2 2006.286.04:58:23.38#ibcon#wrote, iclass 15, count 2 2006.286.04:58:23.38#ibcon#about to read 3, iclass 15, count 2 2006.286.04:58:23.40#ibcon#read 3, iclass 15, count 2 2006.286.04:58:23.40#ibcon#about to read 4, iclass 15, count 2 2006.286.04:58:23.40#ibcon#read 4, iclass 15, count 2 2006.286.04:58:23.40#ibcon#about to read 5, iclass 15, count 2 2006.286.04:58:23.40#ibcon#read 5, iclass 15, count 2 2006.286.04:58:23.40#ibcon#about to read 6, iclass 15, count 2 2006.286.04:58:23.40#ibcon#read 6, iclass 15, count 2 2006.286.04:58:23.40#ibcon#end of sib2, iclass 15, count 2 2006.286.04:58:23.40#ibcon#*mode == 0, iclass 15, count 2 2006.286.04:58:23.40#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.04:58:23.40#ibcon#[25=AT01-07\r\n] 2006.286.04:58:23.40#ibcon#*before write, iclass 15, count 2 2006.286.04:58:23.40#ibcon#enter sib2, iclass 15, count 2 2006.286.04:58:23.40#ibcon#flushed, iclass 15, count 2 2006.286.04:58:23.40#ibcon#about to write, iclass 15, count 2 2006.286.04:58:23.40#ibcon#wrote, iclass 15, count 2 2006.286.04:58:23.40#ibcon#about to read 3, iclass 15, count 2 2006.286.04:58:23.43#ibcon#read 3, iclass 15, count 2 2006.286.04:58:23.43#ibcon#about to read 4, iclass 15, count 2 2006.286.04:58:23.43#ibcon#read 4, iclass 15, count 2 2006.286.04:58:23.43#ibcon#about to read 5, iclass 15, count 2 2006.286.04:58:23.43#ibcon#read 5, iclass 15, count 2 2006.286.04:58:23.43#ibcon#about to read 6, iclass 15, count 2 2006.286.04:58:23.43#ibcon#read 6, iclass 15, count 2 2006.286.04:58:23.43#ibcon#end of sib2, iclass 15, count 2 2006.286.04:58:23.43#ibcon#*after write, iclass 15, count 2 2006.286.04:58:23.43#ibcon#*before return 0, iclass 15, count 2 2006.286.04:58:23.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:58:23.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:58:23.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.04:58:23.43#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:23.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:58:23.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:58:23.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:58:23.55#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:58:23.55#ibcon#first serial, iclass 15, count 0 2006.286.04:58:23.55#ibcon#enter sib2, iclass 15, count 0 2006.286.04:58:23.55#ibcon#flushed, iclass 15, count 0 2006.286.04:58:23.55#ibcon#about to write, iclass 15, count 0 2006.286.04:58:23.55#ibcon#wrote, iclass 15, count 0 2006.286.04:58:23.55#ibcon#about to read 3, iclass 15, count 0 2006.286.04:58:23.57#ibcon#read 3, iclass 15, count 0 2006.286.04:58:23.57#ibcon#about to read 4, iclass 15, count 0 2006.286.04:58:23.57#ibcon#read 4, iclass 15, count 0 2006.286.04:58:23.57#ibcon#about to read 5, iclass 15, count 0 2006.286.04:58:23.57#ibcon#read 5, iclass 15, count 0 2006.286.04:58:23.57#ibcon#about to read 6, iclass 15, count 0 2006.286.04:58:23.57#ibcon#read 6, iclass 15, count 0 2006.286.04:58:23.57#ibcon#end of sib2, iclass 15, count 0 2006.286.04:58:23.57#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:58:23.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:58:23.57#ibcon#[25=USB\r\n] 2006.286.04:58:23.57#ibcon#*before write, iclass 15, count 0 2006.286.04:58:23.57#ibcon#enter sib2, iclass 15, count 0 2006.286.04:58:23.57#ibcon#flushed, iclass 15, count 0 2006.286.04:58:23.57#ibcon#about to write, iclass 15, count 0 2006.286.04:58:23.57#ibcon#wrote, iclass 15, count 0 2006.286.04:58:23.57#ibcon#about to read 3, iclass 15, count 0 2006.286.04:58:23.60#ibcon#read 3, iclass 15, count 0 2006.286.04:58:23.60#ibcon#about to read 4, iclass 15, count 0 2006.286.04:58:23.60#ibcon#read 4, iclass 15, count 0 2006.286.04:58:23.60#ibcon#about to read 5, iclass 15, count 0 2006.286.04:58:23.60#ibcon#read 5, iclass 15, count 0 2006.286.04:58:23.60#ibcon#about to read 6, iclass 15, count 0 2006.286.04:58:23.60#ibcon#read 6, iclass 15, count 0 2006.286.04:58:23.60#ibcon#end of sib2, iclass 15, count 0 2006.286.04:58:23.60#ibcon#*after write, iclass 15, count 0 2006.286.04:58:23.60#ibcon#*before return 0, iclass 15, count 0 2006.286.04:58:23.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:58:23.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:58:23.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:58:23.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:58:23.60$vck44/valo=2,534.99 2006.286.04:58:23.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.04:58:23.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.04:58:23.60#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:23.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:58:23.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:58:23.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:58:23.60#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:58:23.60#ibcon#first serial, iclass 17, count 0 2006.286.04:58:23.60#ibcon#enter sib2, iclass 17, count 0 2006.286.04:58:23.60#ibcon#flushed, iclass 17, count 0 2006.286.04:58:23.60#ibcon#about to write, iclass 17, count 0 2006.286.04:58:23.60#ibcon#wrote, iclass 17, count 0 2006.286.04:58:23.60#ibcon#about to read 3, iclass 17, count 0 2006.286.04:58:24.08#ibcon#read 3, iclass 17, count 0 2006.286.04:58:24.08#ibcon#about to read 4, iclass 17, count 0 2006.286.04:58:24.08#ibcon#read 4, iclass 17, count 0 2006.286.04:58:24.08#ibcon#about to read 5, iclass 17, count 0 2006.286.04:58:24.08#ibcon#read 5, iclass 17, count 0 2006.286.04:58:24.08#ibcon#about to read 6, iclass 17, count 0 2006.286.04:58:24.08#ibcon#read 6, iclass 17, count 0 2006.286.04:58:24.08#ibcon#end of sib2, iclass 17, count 0 2006.286.04:58:24.08#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:58:24.08#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:58:24.08#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:58:24.08#ibcon#*before write, iclass 17, count 0 2006.286.04:58:24.08#ibcon#enter sib2, iclass 17, count 0 2006.286.04:58:24.08#ibcon#flushed, iclass 17, count 0 2006.286.04:58:24.08#ibcon#about to write, iclass 17, count 0 2006.286.04:58:24.08#ibcon#wrote, iclass 17, count 0 2006.286.04:58:24.08#ibcon#about to read 3, iclass 17, count 0 2006.286.04:58:24.12#ibcon#read 3, iclass 17, count 0 2006.286.04:58:24.12#ibcon#about to read 4, iclass 17, count 0 2006.286.04:58:24.12#ibcon#read 4, iclass 17, count 0 2006.286.04:58:24.12#ibcon#about to read 5, iclass 17, count 0 2006.286.04:58:24.12#ibcon#read 5, iclass 17, count 0 2006.286.04:58:24.12#ibcon#about to read 6, iclass 17, count 0 2006.286.04:58:24.12#ibcon#read 6, iclass 17, count 0 2006.286.04:58:24.12#ibcon#end of sib2, iclass 17, count 0 2006.286.04:58:24.12#ibcon#*after write, iclass 17, count 0 2006.286.04:58:24.12#ibcon#*before return 0, iclass 17, count 0 2006.286.04:58:24.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:58:24.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:58:24.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:58:24.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:58:24.12$vck44/va=2,6 2006.286.04:58:24.12#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.04:58:24.12#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.04:58:24.12#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:24.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:58:24.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:58:24.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:58:24.12#ibcon#enter wrdev, iclass 19, count 2 2006.286.04:58:24.12#ibcon#first serial, iclass 19, count 2 2006.286.04:58:24.12#ibcon#enter sib2, iclass 19, count 2 2006.286.04:58:24.12#ibcon#flushed, iclass 19, count 2 2006.286.04:58:24.12#ibcon#about to write, iclass 19, count 2 2006.286.04:58:24.12#ibcon#wrote, iclass 19, count 2 2006.286.04:58:24.12#ibcon#about to read 3, iclass 19, count 2 2006.286.04:58:24.14#ibcon#read 3, iclass 19, count 2 2006.286.04:58:24.14#ibcon#about to read 4, iclass 19, count 2 2006.286.04:58:24.14#ibcon#read 4, iclass 19, count 2 2006.286.04:58:24.14#ibcon#about to read 5, iclass 19, count 2 2006.286.04:58:24.14#ibcon#read 5, iclass 19, count 2 2006.286.04:58:24.14#ibcon#about to read 6, iclass 19, count 2 2006.286.04:58:24.14#ibcon#read 6, iclass 19, count 2 2006.286.04:58:24.14#ibcon#end of sib2, iclass 19, count 2 2006.286.04:58:24.14#ibcon#*mode == 0, iclass 19, count 2 2006.286.04:58:24.14#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.04:58:24.14#ibcon#[25=AT02-06\r\n] 2006.286.04:58:24.14#ibcon#*before write, iclass 19, count 2 2006.286.04:58:24.14#ibcon#enter sib2, iclass 19, count 2 2006.286.04:58:24.14#ibcon#flushed, iclass 19, count 2 2006.286.04:58:24.14#ibcon#about to write, iclass 19, count 2 2006.286.04:58:24.14#ibcon#wrote, iclass 19, count 2 2006.286.04:58:24.14#ibcon#about to read 3, iclass 19, count 2 2006.286.04:58:24.17#ibcon#read 3, iclass 19, count 2 2006.286.04:58:24.17#ibcon#about to read 4, iclass 19, count 2 2006.286.04:58:24.17#ibcon#read 4, iclass 19, count 2 2006.286.04:58:24.17#ibcon#about to read 5, iclass 19, count 2 2006.286.04:58:24.17#ibcon#read 5, iclass 19, count 2 2006.286.04:58:24.17#ibcon#about to read 6, iclass 19, count 2 2006.286.04:58:24.17#ibcon#read 6, iclass 19, count 2 2006.286.04:58:24.17#ibcon#end of sib2, iclass 19, count 2 2006.286.04:58:24.17#ibcon#*after write, iclass 19, count 2 2006.286.04:58:24.17#ibcon#*before return 0, iclass 19, count 2 2006.286.04:58:24.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:58:24.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:58:24.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.04:58:24.17#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:24.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:58:24.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:58:24.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:58:24.29#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:58:24.29#ibcon#first serial, iclass 19, count 0 2006.286.04:58:24.29#ibcon#enter sib2, iclass 19, count 0 2006.286.04:58:24.29#ibcon#flushed, iclass 19, count 0 2006.286.04:58:24.29#ibcon#about to write, iclass 19, count 0 2006.286.04:58:24.29#ibcon#wrote, iclass 19, count 0 2006.286.04:58:24.29#ibcon#about to read 3, iclass 19, count 0 2006.286.04:58:24.31#ibcon#read 3, iclass 19, count 0 2006.286.04:58:24.31#ibcon#about to read 4, iclass 19, count 0 2006.286.04:58:24.31#ibcon#read 4, iclass 19, count 0 2006.286.04:58:24.31#ibcon#about to read 5, iclass 19, count 0 2006.286.04:58:24.31#ibcon#read 5, iclass 19, count 0 2006.286.04:58:24.31#ibcon#about to read 6, iclass 19, count 0 2006.286.04:58:24.31#ibcon#read 6, iclass 19, count 0 2006.286.04:58:24.31#ibcon#end of sib2, iclass 19, count 0 2006.286.04:58:24.31#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:58:24.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:58:24.31#ibcon#[25=USB\r\n] 2006.286.04:58:24.31#ibcon#*before write, iclass 19, count 0 2006.286.04:58:24.31#ibcon#enter sib2, iclass 19, count 0 2006.286.04:58:24.31#ibcon#flushed, iclass 19, count 0 2006.286.04:58:24.31#ibcon#about to write, iclass 19, count 0 2006.286.04:58:24.31#ibcon#wrote, iclass 19, count 0 2006.286.04:58:24.31#ibcon#about to read 3, iclass 19, count 0 2006.286.04:58:24.34#ibcon#read 3, iclass 19, count 0 2006.286.04:58:24.34#ibcon#about to read 4, iclass 19, count 0 2006.286.04:58:24.34#ibcon#read 4, iclass 19, count 0 2006.286.04:58:24.34#ibcon#about to read 5, iclass 19, count 0 2006.286.04:58:24.34#ibcon#read 5, iclass 19, count 0 2006.286.04:58:24.34#ibcon#about to read 6, iclass 19, count 0 2006.286.04:58:24.34#ibcon#read 6, iclass 19, count 0 2006.286.04:58:24.34#ibcon#end of sib2, iclass 19, count 0 2006.286.04:58:24.34#ibcon#*after write, iclass 19, count 0 2006.286.04:58:24.34#ibcon#*before return 0, iclass 19, count 0 2006.286.04:58:24.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:58:24.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:58:24.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:58:24.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:58:24.34$vck44/valo=3,564.99 2006.286.04:58:24.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.04:58:24.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.04:58:24.34#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:24.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:58:24.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:58:24.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:58:24.34#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:58:24.34#ibcon#first serial, iclass 21, count 0 2006.286.04:58:24.34#ibcon#enter sib2, iclass 21, count 0 2006.286.04:58:24.34#ibcon#flushed, iclass 21, count 0 2006.286.04:58:24.34#ibcon#about to write, iclass 21, count 0 2006.286.04:58:24.34#ibcon#wrote, iclass 21, count 0 2006.286.04:58:24.34#ibcon#about to read 3, iclass 21, count 0 2006.286.04:58:24.36#ibcon#read 3, iclass 21, count 0 2006.286.04:58:24.36#ibcon#about to read 4, iclass 21, count 0 2006.286.04:58:24.36#ibcon#read 4, iclass 21, count 0 2006.286.04:58:24.36#ibcon#about to read 5, iclass 21, count 0 2006.286.04:58:24.36#ibcon#read 5, iclass 21, count 0 2006.286.04:58:24.36#ibcon#about to read 6, iclass 21, count 0 2006.286.04:58:24.36#ibcon#read 6, iclass 21, count 0 2006.286.04:58:24.36#ibcon#end of sib2, iclass 21, count 0 2006.286.04:58:24.36#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:58:24.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:58:24.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:58:24.36#ibcon#*before write, iclass 21, count 0 2006.286.04:58:24.36#ibcon#enter sib2, iclass 21, count 0 2006.286.04:58:24.36#ibcon#flushed, iclass 21, count 0 2006.286.04:58:24.36#ibcon#about to write, iclass 21, count 0 2006.286.04:58:24.36#ibcon#wrote, iclass 21, count 0 2006.286.04:58:24.36#ibcon#about to read 3, iclass 21, count 0 2006.286.04:58:24.40#ibcon#read 3, iclass 21, count 0 2006.286.04:58:24.40#ibcon#about to read 4, iclass 21, count 0 2006.286.04:58:24.40#ibcon#read 4, iclass 21, count 0 2006.286.04:58:24.40#ibcon#about to read 5, iclass 21, count 0 2006.286.04:58:24.40#ibcon#read 5, iclass 21, count 0 2006.286.04:58:24.40#ibcon#about to read 6, iclass 21, count 0 2006.286.04:58:24.40#ibcon#read 6, iclass 21, count 0 2006.286.04:58:24.40#ibcon#end of sib2, iclass 21, count 0 2006.286.04:58:24.40#ibcon#*after write, iclass 21, count 0 2006.286.04:58:24.40#ibcon#*before return 0, iclass 21, count 0 2006.286.04:58:24.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:58:24.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:58:24.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:58:24.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:58:24.40$vck44/va=3,7 2006.286.04:58:24.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.04:58:24.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.04:58:24.40#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:24.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:58:24.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:58:24.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:58:24.46#ibcon#enter wrdev, iclass 23, count 2 2006.286.04:58:24.46#ibcon#first serial, iclass 23, count 2 2006.286.04:58:24.46#ibcon#enter sib2, iclass 23, count 2 2006.286.04:58:24.46#ibcon#flushed, iclass 23, count 2 2006.286.04:58:24.46#ibcon#about to write, iclass 23, count 2 2006.286.04:58:24.46#ibcon#wrote, iclass 23, count 2 2006.286.04:58:24.46#ibcon#about to read 3, iclass 23, count 2 2006.286.04:58:24.48#ibcon#read 3, iclass 23, count 2 2006.286.04:58:24.48#ibcon#about to read 4, iclass 23, count 2 2006.286.04:58:24.48#ibcon#read 4, iclass 23, count 2 2006.286.04:58:24.48#ibcon#about to read 5, iclass 23, count 2 2006.286.04:58:24.48#ibcon#read 5, iclass 23, count 2 2006.286.04:58:24.48#ibcon#about to read 6, iclass 23, count 2 2006.286.04:58:24.48#ibcon#read 6, iclass 23, count 2 2006.286.04:58:24.48#ibcon#end of sib2, iclass 23, count 2 2006.286.04:58:24.48#ibcon#*mode == 0, iclass 23, count 2 2006.286.04:58:24.48#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.04:58:24.48#ibcon#[25=AT03-07\r\n] 2006.286.04:58:24.48#ibcon#*before write, iclass 23, count 2 2006.286.04:58:24.48#ibcon#enter sib2, iclass 23, count 2 2006.286.04:58:24.48#ibcon#flushed, iclass 23, count 2 2006.286.04:58:24.48#ibcon#about to write, iclass 23, count 2 2006.286.04:58:24.48#ibcon#wrote, iclass 23, count 2 2006.286.04:58:24.48#ibcon#about to read 3, iclass 23, count 2 2006.286.04:58:24.51#ibcon#read 3, iclass 23, count 2 2006.286.04:58:24.51#ibcon#about to read 4, iclass 23, count 2 2006.286.04:58:24.51#ibcon#read 4, iclass 23, count 2 2006.286.04:58:24.51#ibcon#about to read 5, iclass 23, count 2 2006.286.04:58:24.51#ibcon#read 5, iclass 23, count 2 2006.286.04:58:24.51#ibcon#about to read 6, iclass 23, count 2 2006.286.04:58:24.51#ibcon#read 6, iclass 23, count 2 2006.286.04:58:24.51#ibcon#end of sib2, iclass 23, count 2 2006.286.04:58:24.51#ibcon#*after write, iclass 23, count 2 2006.286.04:58:24.51#ibcon#*before return 0, iclass 23, count 2 2006.286.04:58:24.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:58:24.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:58:24.51#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.04:58:24.51#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:24.51#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:58:24.63#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:58:24.63#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:58:24.63#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:58:24.63#ibcon#first serial, iclass 23, count 0 2006.286.04:58:24.63#ibcon#enter sib2, iclass 23, count 0 2006.286.04:58:24.63#ibcon#flushed, iclass 23, count 0 2006.286.04:58:24.63#ibcon#about to write, iclass 23, count 0 2006.286.04:58:24.63#ibcon#wrote, iclass 23, count 0 2006.286.04:58:24.63#ibcon#about to read 3, iclass 23, count 0 2006.286.04:58:24.65#ibcon#read 3, iclass 23, count 0 2006.286.04:58:24.65#ibcon#about to read 4, iclass 23, count 0 2006.286.04:58:24.65#ibcon#read 4, iclass 23, count 0 2006.286.04:58:24.65#ibcon#about to read 5, iclass 23, count 0 2006.286.04:58:24.65#ibcon#read 5, iclass 23, count 0 2006.286.04:58:24.65#ibcon#about to read 6, iclass 23, count 0 2006.286.04:58:24.65#ibcon#read 6, iclass 23, count 0 2006.286.04:58:24.65#ibcon#end of sib2, iclass 23, count 0 2006.286.04:58:24.65#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:58:24.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:58:24.65#ibcon#[25=USB\r\n] 2006.286.04:58:24.65#ibcon#*before write, iclass 23, count 0 2006.286.04:58:24.65#ibcon#enter sib2, iclass 23, count 0 2006.286.04:58:24.65#ibcon#flushed, iclass 23, count 0 2006.286.04:58:24.65#ibcon#about to write, iclass 23, count 0 2006.286.04:58:24.65#ibcon#wrote, iclass 23, count 0 2006.286.04:58:24.65#ibcon#about to read 3, iclass 23, count 0 2006.286.04:58:24.68#ibcon#read 3, iclass 23, count 0 2006.286.04:58:24.68#ibcon#about to read 4, iclass 23, count 0 2006.286.04:58:24.68#ibcon#read 4, iclass 23, count 0 2006.286.04:58:24.68#ibcon#about to read 5, iclass 23, count 0 2006.286.04:58:24.68#ibcon#read 5, iclass 23, count 0 2006.286.04:58:24.68#ibcon#about to read 6, iclass 23, count 0 2006.286.04:58:24.68#ibcon#read 6, iclass 23, count 0 2006.286.04:58:24.68#ibcon#end of sib2, iclass 23, count 0 2006.286.04:58:24.68#ibcon#*after write, iclass 23, count 0 2006.286.04:58:24.68#ibcon#*before return 0, iclass 23, count 0 2006.286.04:58:24.68#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:58:24.68#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:58:24.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:58:24.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:58:24.68$vck44/valo=4,624.99 2006.286.04:58:24.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.04:58:24.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.04:58:24.68#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:24.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:58:24.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:58:24.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:58:24.68#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:58:24.68#ibcon#first serial, iclass 25, count 0 2006.286.04:58:24.68#ibcon#enter sib2, iclass 25, count 0 2006.286.04:58:24.68#ibcon#flushed, iclass 25, count 0 2006.286.04:58:24.68#ibcon#about to write, iclass 25, count 0 2006.286.04:58:24.68#ibcon#wrote, iclass 25, count 0 2006.286.04:58:24.68#ibcon#about to read 3, iclass 25, count 0 2006.286.04:58:24.83#ibcon#read 3, iclass 25, count 0 2006.286.04:58:24.83#ibcon#about to read 4, iclass 25, count 0 2006.286.04:58:24.83#ibcon#read 4, iclass 25, count 0 2006.286.04:58:24.83#ibcon#about to read 5, iclass 25, count 0 2006.286.04:58:24.83#ibcon#read 5, iclass 25, count 0 2006.286.04:58:24.83#ibcon#about to read 6, iclass 25, count 0 2006.286.04:58:24.83#ibcon#read 6, iclass 25, count 0 2006.286.04:58:24.83#ibcon#end of sib2, iclass 25, count 0 2006.286.04:58:24.83#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:58:24.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:58:24.83#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:58:24.83#ibcon#*before write, iclass 25, count 0 2006.286.04:58:24.83#ibcon#enter sib2, iclass 25, count 0 2006.286.04:58:24.83#ibcon#flushed, iclass 25, count 0 2006.286.04:58:24.83#ibcon#about to write, iclass 25, count 0 2006.286.04:58:24.83#ibcon#wrote, iclass 25, count 0 2006.286.04:58:24.83#ibcon#about to read 3, iclass 25, count 0 2006.286.04:58:24.88#ibcon#read 3, iclass 25, count 0 2006.286.04:58:24.88#ibcon#about to read 4, iclass 25, count 0 2006.286.04:58:24.88#ibcon#read 4, iclass 25, count 0 2006.286.04:58:24.88#ibcon#about to read 5, iclass 25, count 0 2006.286.04:58:24.88#ibcon#read 5, iclass 25, count 0 2006.286.04:58:24.88#ibcon#about to read 6, iclass 25, count 0 2006.286.04:58:24.88#ibcon#read 6, iclass 25, count 0 2006.286.04:58:24.88#ibcon#end of sib2, iclass 25, count 0 2006.286.04:58:24.88#ibcon#*after write, iclass 25, count 0 2006.286.04:58:24.88#ibcon#*before return 0, iclass 25, count 0 2006.286.04:58:24.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:58:24.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:58:24.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:58:24.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:58:24.88$vck44/va=4,6 2006.286.04:58:24.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.04:58:24.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.04:58:24.88#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:24.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:58:24.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:58:24.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:58:24.88#ibcon#enter wrdev, iclass 27, count 2 2006.286.04:58:24.88#ibcon#first serial, iclass 27, count 2 2006.286.04:58:24.88#ibcon#enter sib2, iclass 27, count 2 2006.286.04:58:24.88#ibcon#flushed, iclass 27, count 2 2006.286.04:58:24.88#ibcon#about to write, iclass 27, count 2 2006.286.04:58:24.88#ibcon#wrote, iclass 27, count 2 2006.286.04:58:24.88#ibcon#about to read 3, iclass 27, count 2 2006.286.04:58:24.90#ibcon#read 3, iclass 27, count 2 2006.286.04:58:24.90#ibcon#about to read 4, iclass 27, count 2 2006.286.04:58:24.90#ibcon#read 4, iclass 27, count 2 2006.286.04:58:24.90#ibcon#about to read 5, iclass 27, count 2 2006.286.04:58:24.90#ibcon#read 5, iclass 27, count 2 2006.286.04:58:24.90#ibcon#about to read 6, iclass 27, count 2 2006.286.04:58:24.90#ibcon#read 6, iclass 27, count 2 2006.286.04:58:24.90#ibcon#end of sib2, iclass 27, count 2 2006.286.04:58:24.90#ibcon#*mode == 0, iclass 27, count 2 2006.286.04:58:24.90#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.04:58:24.90#ibcon#[25=AT04-06\r\n] 2006.286.04:58:24.90#ibcon#*before write, iclass 27, count 2 2006.286.04:58:24.90#ibcon#enter sib2, iclass 27, count 2 2006.286.04:58:24.90#ibcon#flushed, iclass 27, count 2 2006.286.04:58:24.90#ibcon#about to write, iclass 27, count 2 2006.286.04:58:24.90#ibcon#wrote, iclass 27, count 2 2006.286.04:58:24.90#ibcon#about to read 3, iclass 27, count 2 2006.286.04:58:24.93#ibcon#read 3, iclass 27, count 2 2006.286.04:58:24.93#ibcon#about to read 4, iclass 27, count 2 2006.286.04:58:24.93#ibcon#read 4, iclass 27, count 2 2006.286.04:58:24.93#ibcon#about to read 5, iclass 27, count 2 2006.286.04:58:24.93#ibcon#read 5, iclass 27, count 2 2006.286.04:58:24.93#ibcon#about to read 6, iclass 27, count 2 2006.286.04:58:24.93#ibcon#read 6, iclass 27, count 2 2006.286.04:58:24.93#ibcon#end of sib2, iclass 27, count 2 2006.286.04:58:24.93#ibcon#*after write, iclass 27, count 2 2006.286.04:58:24.93#ibcon#*before return 0, iclass 27, count 2 2006.286.04:58:24.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:58:24.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:58:24.93#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.04:58:24.93#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:24.93#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:58:25.05#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:58:25.05#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:58:25.05#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:58:25.05#ibcon#first serial, iclass 27, count 0 2006.286.04:58:25.05#ibcon#enter sib2, iclass 27, count 0 2006.286.04:58:25.05#ibcon#flushed, iclass 27, count 0 2006.286.04:58:25.05#ibcon#about to write, iclass 27, count 0 2006.286.04:58:25.05#ibcon#wrote, iclass 27, count 0 2006.286.04:58:25.05#ibcon#about to read 3, iclass 27, count 0 2006.286.04:58:25.07#ibcon#read 3, iclass 27, count 0 2006.286.04:58:25.07#ibcon#about to read 4, iclass 27, count 0 2006.286.04:58:25.07#ibcon#read 4, iclass 27, count 0 2006.286.04:58:25.07#ibcon#about to read 5, iclass 27, count 0 2006.286.04:58:25.07#ibcon#read 5, iclass 27, count 0 2006.286.04:58:25.07#ibcon#about to read 6, iclass 27, count 0 2006.286.04:58:25.07#ibcon#read 6, iclass 27, count 0 2006.286.04:58:25.07#ibcon#end of sib2, iclass 27, count 0 2006.286.04:58:25.07#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:58:25.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:58:25.07#ibcon#[25=USB\r\n] 2006.286.04:58:25.07#ibcon#*before write, iclass 27, count 0 2006.286.04:58:25.07#ibcon#enter sib2, iclass 27, count 0 2006.286.04:58:25.07#ibcon#flushed, iclass 27, count 0 2006.286.04:58:25.07#ibcon#about to write, iclass 27, count 0 2006.286.04:58:25.07#ibcon#wrote, iclass 27, count 0 2006.286.04:58:25.07#ibcon#about to read 3, iclass 27, count 0 2006.286.04:58:25.10#ibcon#read 3, iclass 27, count 0 2006.286.04:58:25.10#ibcon#about to read 4, iclass 27, count 0 2006.286.04:58:25.10#ibcon#read 4, iclass 27, count 0 2006.286.04:58:25.10#ibcon#about to read 5, iclass 27, count 0 2006.286.04:58:25.10#ibcon#read 5, iclass 27, count 0 2006.286.04:58:25.10#ibcon#about to read 6, iclass 27, count 0 2006.286.04:58:25.10#ibcon#read 6, iclass 27, count 0 2006.286.04:58:25.10#ibcon#end of sib2, iclass 27, count 0 2006.286.04:58:25.10#ibcon#*after write, iclass 27, count 0 2006.286.04:58:25.10#ibcon#*before return 0, iclass 27, count 0 2006.286.04:58:25.10#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:58:25.10#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:58:25.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:58:25.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:58:25.10$vck44/valo=5,734.99 2006.286.04:58:25.10#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.04:58:25.10#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.04:58:25.10#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:25.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:58:25.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:58:25.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:58:25.10#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:58:25.10#ibcon#first serial, iclass 29, count 0 2006.286.04:58:25.10#ibcon#enter sib2, iclass 29, count 0 2006.286.04:58:25.10#ibcon#flushed, iclass 29, count 0 2006.286.04:58:25.10#ibcon#about to write, iclass 29, count 0 2006.286.04:58:25.10#ibcon#wrote, iclass 29, count 0 2006.286.04:58:25.10#ibcon#about to read 3, iclass 29, count 0 2006.286.04:58:25.12#ibcon#read 3, iclass 29, count 0 2006.286.04:58:25.12#ibcon#about to read 4, iclass 29, count 0 2006.286.04:58:25.12#ibcon#read 4, iclass 29, count 0 2006.286.04:58:25.12#ibcon#about to read 5, iclass 29, count 0 2006.286.04:58:25.12#ibcon#read 5, iclass 29, count 0 2006.286.04:58:25.12#ibcon#about to read 6, iclass 29, count 0 2006.286.04:58:25.12#ibcon#read 6, iclass 29, count 0 2006.286.04:58:25.12#ibcon#end of sib2, iclass 29, count 0 2006.286.04:58:25.12#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:58:25.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:58:25.12#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:58:25.12#ibcon#*before write, iclass 29, count 0 2006.286.04:58:25.12#ibcon#enter sib2, iclass 29, count 0 2006.286.04:58:25.12#ibcon#flushed, iclass 29, count 0 2006.286.04:58:25.12#ibcon#about to write, iclass 29, count 0 2006.286.04:58:25.12#ibcon#wrote, iclass 29, count 0 2006.286.04:58:25.12#ibcon#about to read 3, iclass 29, count 0 2006.286.04:58:25.16#ibcon#read 3, iclass 29, count 0 2006.286.04:58:25.16#ibcon#about to read 4, iclass 29, count 0 2006.286.04:58:25.16#ibcon#read 4, iclass 29, count 0 2006.286.04:58:25.16#ibcon#about to read 5, iclass 29, count 0 2006.286.04:58:25.16#ibcon#read 5, iclass 29, count 0 2006.286.04:58:25.16#ibcon#about to read 6, iclass 29, count 0 2006.286.04:58:25.16#ibcon#read 6, iclass 29, count 0 2006.286.04:58:25.16#ibcon#end of sib2, iclass 29, count 0 2006.286.04:58:25.16#ibcon#*after write, iclass 29, count 0 2006.286.04:58:25.16#ibcon#*before return 0, iclass 29, count 0 2006.286.04:58:25.16#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:58:25.16#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:58:25.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:58:25.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:58:25.16$vck44/va=5,3 2006.286.04:58:25.16#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.04:58:25.16#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.04:58:25.16#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:25.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:58:25.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:58:25.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:58:25.22#ibcon#enter wrdev, iclass 31, count 2 2006.286.04:58:25.22#ibcon#first serial, iclass 31, count 2 2006.286.04:58:25.22#ibcon#enter sib2, iclass 31, count 2 2006.286.04:58:25.22#ibcon#flushed, iclass 31, count 2 2006.286.04:58:25.22#ibcon#about to write, iclass 31, count 2 2006.286.04:58:25.22#ibcon#wrote, iclass 31, count 2 2006.286.04:58:25.22#ibcon#about to read 3, iclass 31, count 2 2006.286.04:58:25.24#ibcon#read 3, iclass 31, count 2 2006.286.04:58:25.24#ibcon#about to read 4, iclass 31, count 2 2006.286.04:58:25.24#ibcon#read 4, iclass 31, count 2 2006.286.04:58:25.24#ibcon#about to read 5, iclass 31, count 2 2006.286.04:58:25.24#ibcon#read 5, iclass 31, count 2 2006.286.04:58:25.24#ibcon#about to read 6, iclass 31, count 2 2006.286.04:58:25.24#ibcon#read 6, iclass 31, count 2 2006.286.04:58:25.24#ibcon#end of sib2, iclass 31, count 2 2006.286.04:58:25.24#ibcon#*mode == 0, iclass 31, count 2 2006.286.04:58:25.24#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.04:58:25.24#ibcon#[25=AT05-03\r\n] 2006.286.04:58:25.24#ibcon#*before write, iclass 31, count 2 2006.286.04:58:25.24#ibcon#enter sib2, iclass 31, count 2 2006.286.04:58:25.24#ibcon#flushed, iclass 31, count 2 2006.286.04:58:25.24#ibcon#about to write, iclass 31, count 2 2006.286.04:58:25.24#ibcon#wrote, iclass 31, count 2 2006.286.04:58:25.24#ibcon#about to read 3, iclass 31, count 2 2006.286.04:58:25.27#ibcon#read 3, iclass 31, count 2 2006.286.04:58:25.27#ibcon#about to read 4, iclass 31, count 2 2006.286.04:58:25.27#ibcon#read 4, iclass 31, count 2 2006.286.04:58:25.27#ibcon#about to read 5, iclass 31, count 2 2006.286.04:58:25.27#ibcon#read 5, iclass 31, count 2 2006.286.04:58:25.27#ibcon#about to read 6, iclass 31, count 2 2006.286.04:58:25.27#ibcon#read 6, iclass 31, count 2 2006.286.04:58:25.27#ibcon#end of sib2, iclass 31, count 2 2006.286.04:58:25.27#ibcon#*after write, iclass 31, count 2 2006.286.04:58:25.27#ibcon#*before return 0, iclass 31, count 2 2006.286.04:58:25.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:58:25.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:58:25.27#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.04:58:25.27#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:25.27#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:58:25.39#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:58:25.39#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:58:25.39#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:58:25.39#ibcon#first serial, iclass 31, count 0 2006.286.04:58:25.39#ibcon#enter sib2, iclass 31, count 0 2006.286.04:58:25.39#ibcon#flushed, iclass 31, count 0 2006.286.04:58:25.39#ibcon#about to write, iclass 31, count 0 2006.286.04:58:25.39#ibcon#wrote, iclass 31, count 0 2006.286.04:58:25.39#ibcon#about to read 3, iclass 31, count 0 2006.286.04:58:25.41#ibcon#read 3, iclass 31, count 0 2006.286.04:58:25.41#ibcon#about to read 4, iclass 31, count 0 2006.286.04:58:25.41#ibcon#read 4, iclass 31, count 0 2006.286.04:58:25.41#ibcon#about to read 5, iclass 31, count 0 2006.286.04:58:25.41#ibcon#read 5, iclass 31, count 0 2006.286.04:58:25.41#ibcon#about to read 6, iclass 31, count 0 2006.286.04:58:25.41#ibcon#read 6, iclass 31, count 0 2006.286.04:58:25.41#ibcon#end of sib2, iclass 31, count 0 2006.286.04:58:25.41#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:58:25.41#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:58:25.41#ibcon#[25=USB\r\n] 2006.286.04:58:25.41#ibcon#*before write, iclass 31, count 0 2006.286.04:58:25.41#ibcon#enter sib2, iclass 31, count 0 2006.286.04:58:25.41#ibcon#flushed, iclass 31, count 0 2006.286.04:58:25.41#ibcon#about to write, iclass 31, count 0 2006.286.04:58:25.41#ibcon#wrote, iclass 31, count 0 2006.286.04:58:25.41#ibcon#about to read 3, iclass 31, count 0 2006.286.04:58:25.44#ibcon#read 3, iclass 31, count 0 2006.286.04:58:25.44#ibcon#about to read 4, iclass 31, count 0 2006.286.04:58:25.44#ibcon#read 4, iclass 31, count 0 2006.286.04:58:25.44#ibcon#about to read 5, iclass 31, count 0 2006.286.04:58:25.44#ibcon#read 5, iclass 31, count 0 2006.286.04:58:25.44#ibcon#about to read 6, iclass 31, count 0 2006.286.04:58:25.44#ibcon#read 6, iclass 31, count 0 2006.286.04:58:25.44#ibcon#end of sib2, iclass 31, count 0 2006.286.04:58:25.44#ibcon#*after write, iclass 31, count 0 2006.286.04:58:25.44#ibcon#*before return 0, iclass 31, count 0 2006.286.04:58:25.44#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:58:25.44#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:58:25.44#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:58:25.44#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:58:25.44$vck44/valo=6,814.99 2006.286.04:58:25.44#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.04:58:25.44#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.04:58:25.44#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:25.44#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:58:25.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:58:25.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:58:25.44#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:58:25.44#ibcon#first serial, iclass 33, count 0 2006.286.04:58:25.44#ibcon#enter sib2, iclass 33, count 0 2006.286.04:58:25.44#ibcon#flushed, iclass 33, count 0 2006.286.04:58:25.44#ibcon#about to write, iclass 33, count 0 2006.286.04:58:25.44#ibcon#wrote, iclass 33, count 0 2006.286.04:58:25.44#ibcon#about to read 3, iclass 33, count 0 2006.286.04:58:25.46#ibcon#read 3, iclass 33, count 0 2006.286.04:58:25.46#ibcon#about to read 4, iclass 33, count 0 2006.286.04:58:25.46#ibcon#read 4, iclass 33, count 0 2006.286.04:58:25.46#ibcon#about to read 5, iclass 33, count 0 2006.286.04:58:25.46#ibcon#read 5, iclass 33, count 0 2006.286.04:58:25.46#ibcon#about to read 6, iclass 33, count 0 2006.286.04:58:25.46#ibcon#read 6, iclass 33, count 0 2006.286.04:58:25.46#ibcon#end of sib2, iclass 33, count 0 2006.286.04:58:25.46#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:58:25.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:58:25.46#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:58:25.46#ibcon#*before write, iclass 33, count 0 2006.286.04:58:25.46#ibcon#enter sib2, iclass 33, count 0 2006.286.04:58:25.46#ibcon#flushed, iclass 33, count 0 2006.286.04:58:25.46#ibcon#about to write, iclass 33, count 0 2006.286.04:58:25.46#ibcon#wrote, iclass 33, count 0 2006.286.04:58:25.46#ibcon#about to read 3, iclass 33, count 0 2006.286.04:58:25.50#ibcon#read 3, iclass 33, count 0 2006.286.04:58:25.50#ibcon#about to read 4, iclass 33, count 0 2006.286.04:58:25.50#ibcon#read 4, iclass 33, count 0 2006.286.04:58:25.50#ibcon#about to read 5, iclass 33, count 0 2006.286.04:58:25.50#ibcon#read 5, iclass 33, count 0 2006.286.04:58:25.50#ibcon#about to read 6, iclass 33, count 0 2006.286.04:58:25.50#ibcon#read 6, iclass 33, count 0 2006.286.04:58:25.50#ibcon#end of sib2, iclass 33, count 0 2006.286.04:58:25.50#ibcon#*after write, iclass 33, count 0 2006.286.04:58:25.50#ibcon#*before return 0, iclass 33, count 0 2006.286.04:58:25.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:58:25.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:58:25.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:58:25.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:58:25.50$vck44/va=6,4 2006.286.04:58:25.50#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.04:58:25.50#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.04:58:25.50#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:25.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:58:25.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:58:25.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:58:25.56#ibcon#enter wrdev, iclass 35, count 2 2006.286.04:58:25.56#ibcon#first serial, iclass 35, count 2 2006.286.04:58:25.56#ibcon#enter sib2, iclass 35, count 2 2006.286.04:58:25.56#ibcon#flushed, iclass 35, count 2 2006.286.04:58:25.56#ibcon#about to write, iclass 35, count 2 2006.286.04:58:25.56#ibcon#wrote, iclass 35, count 2 2006.286.04:58:25.56#ibcon#about to read 3, iclass 35, count 2 2006.286.04:58:25.58#ibcon#read 3, iclass 35, count 2 2006.286.04:58:25.58#ibcon#about to read 4, iclass 35, count 2 2006.286.04:58:25.58#ibcon#read 4, iclass 35, count 2 2006.286.04:58:25.58#ibcon#about to read 5, iclass 35, count 2 2006.286.04:58:25.58#ibcon#read 5, iclass 35, count 2 2006.286.04:58:25.58#ibcon#about to read 6, iclass 35, count 2 2006.286.04:58:25.58#ibcon#read 6, iclass 35, count 2 2006.286.04:58:25.58#ibcon#end of sib2, iclass 35, count 2 2006.286.04:58:25.58#ibcon#*mode == 0, iclass 35, count 2 2006.286.04:58:25.58#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.04:58:25.58#ibcon#[25=AT06-04\r\n] 2006.286.04:58:25.58#ibcon#*before write, iclass 35, count 2 2006.286.04:58:25.58#ibcon#enter sib2, iclass 35, count 2 2006.286.04:58:25.58#ibcon#flushed, iclass 35, count 2 2006.286.04:58:25.58#ibcon#about to write, iclass 35, count 2 2006.286.04:58:25.58#ibcon#wrote, iclass 35, count 2 2006.286.04:58:25.58#ibcon#about to read 3, iclass 35, count 2 2006.286.04:58:25.61#ibcon#read 3, iclass 35, count 2 2006.286.04:58:25.61#ibcon#about to read 4, iclass 35, count 2 2006.286.04:58:25.61#ibcon#read 4, iclass 35, count 2 2006.286.04:58:25.61#ibcon#about to read 5, iclass 35, count 2 2006.286.04:58:25.61#ibcon#read 5, iclass 35, count 2 2006.286.04:58:25.61#ibcon#about to read 6, iclass 35, count 2 2006.286.04:58:25.61#ibcon#read 6, iclass 35, count 2 2006.286.04:58:25.61#ibcon#end of sib2, iclass 35, count 2 2006.286.04:58:25.61#ibcon#*after write, iclass 35, count 2 2006.286.04:58:25.61#ibcon#*before return 0, iclass 35, count 2 2006.286.04:58:25.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:58:25.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:58:25.61#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.04:58:25.61#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:25.61#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:58:25.73#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:58:25.97#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:58:25.97#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:58:25.97#ibcon#first serial, iclass 35, count 0 2006.286.04:58:25.97#ibcon#enter sib2, iclass 35, count 0 2006.286.04:58:25.97#ibcon#flushed, iclass 35, count 0 2006.286.04:58:25.97#ibcon#about to write, iclass 35, count 0 2006.286.04:58:25.97#ibcon#wrote, iclass 35, count 0 2006.286.04:58:25.97#ibcon#about to read 3, iclass 35, count 0 2006.286.04:58:25.99#ibcon#read 3, iclass 35, count 0 2006.286.04:58:25.99#ibcon#about to read 4, iclass 35, count 0 2006.286.04:58:25.99#ibcon#read 4, iclass 35, count 0 2006.286.04:58:25.99#ibcon#about to read 5, iclass 35, count 0 2006.286.04:58:25.99#ibcon#read 5, iclass 35, count 0 2006.286.04:58:25.99#ibcon#about to read 6, iclass 35, count 0 2006.286.04:58:25.99#ibcon#read 6, iclass 35, count 0 2006.286.04:58:25.99#ibcon#end of sib2, iclass 35, count 0 2006.286.04:58:25.99#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:58:25.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:58:25.99#ibcon#[25=USB\r\n] 2006.286.04:58:25.99#ibcon#*before write, iclass 35, count 0 2006.286.04:58:25.99#ibcon#enter sib2, iclass 35, count 0 2006.286.04:58:25.99#ibcon#flushed, iclass 35, count 0 2006.286.04:58:25.99#ibcon#about to write, iclass 35, count 0 2006.286.04:58:25.99#ibcon#wrote, iclass 35, count 0 2006.286.04:58:25.99#ibcon#about to read 3, iclass 35, count 0 2006.286.04:58:26.02#ibcon#read 3, iclass 35, count 0 2006.286.04:58:26.02#ibcon#about to read 4, iclass 35, count 0 2006.286.04:58:26.02#ibcon#read 4, iclass 35, count 0 2006.286.04:58:26.02#ibcon#about to read 5, iclass 35, count 0 2006.286.04:58:26.02#ibcon#read 5, iclass 35, count 0 2006.286.04:58:26.02#ibcon#about to read 6, iclass 35, count 0 2006.286.04:58:26.02#ibcon#read 6, iclass 35, count 0 2006.286.04:58:26.02#ibcon#end of sib2, iclass 35, count 0 2006.286.04:58:26.02#ibcon#*after write, iclass 35, count 0 2006.286.04:58:26.02#ibcon#*before return 0, iclass 35, count 0 2006.286.04:58:26.02#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:58:26.02#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:58:26.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:58:26.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:58:26.02$vck44/valo=7,864.99 2006.286.04:58:26.02#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.04:58:26.02#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.04:58:26.02#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:26.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:58:26.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:58:26.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:58:26.02#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:58:26.02#ibcon#first serial, iclass 37, count 0 2006.286.04:58:26.02#ibcon#enter sib2, iclass 37, count 0 2006.286.04:58:26.02#ibcon#flushed, iclass 37, count 0 2006.286.04:58:26.02#ibcon#about to write, iclass 37, count 0 2006.286.04:58:26.02#ibcon#wrote, iclass 37, count 0 2006.286.04:58:26.02#ibcon#about to read 3, iclass 37, count 0 2006.286.04:58:26.04#ibcon#read 3, iclass 37, count 0 2006.286.04:58:26.04#ibcon#about to read 4, iclass 37, count 0 2006.286.04:58:26.04#ibcon#read 4, iclass 37, count 0 2006.286.04:58:26.04#ibcon#about to read 5, iclass 37, count 0 2006.286.04:58:26.04#ibcon#read 5, iclass 37, count 0 2006.286.04:58:26.04#ibcon#about to read 6, iclass 37, count 0 2006.286.04:58:26.04#ibcon#read 6, iclass 37, count 0 2006.286.04:58:26.04#ibcon#end of sib2, iclass 37, count 0 2006.286.04:58:26.04#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:58:26.04#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:58:26.04#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:58:26.04#ibcon#*before write, iclass 37, count 0 2006.286.04:58:26.04#ibcon#enter sib2, iclass 37, count 0 2006.286.04:58:26.04#ibcon#flushed, iclass 37, count 0 2006.286.04:58:26.04#ibcon#about to write, iclass 37, count 0 2006.286.04:58:26.04#ibcon#wrote, iclass 37, count 0 2006.286.04:58:26.04#ibcon#about to read 3, iclass 37, count 0 2006.286.04:58:26.08#ibcon#read 3, iclass 37, count 0 2006.286.04:58:26.08#ibcon#about to read 4, iclass 37, count 0 2006.286.04:58:26.08#ibcon#read 4, iclass 37, count 0 2006.286.04:58:26.08#ibcon#about to read 5, iclass 37, count 0 2006.286.04:58:26.08#ibcon#read 5, iclass 37, count 0 2006.286.04:58:26.08#ibcon#about to read 6, iclass 37, count 0 2006.286.04:58:26.08#ibcon#read 6, iclass 37, count 0 2006.286.04:58:26.08#ibcon#end of sib2, iclass 37, count 0 2006.286.04:58:26.08#ibcon#*after write, iclass 37, count 0 2006.286.04:58:26.08#ibcon#*before return 0, iclass 37, count 0 2006.286.04:58:26.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:58:26.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:58:26.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:58:26.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:58:26.08$vck44/va=7,4 2006.286.04:58:26.08#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.04:58:26.08#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.04:58:26.08#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:26.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:58:26.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:58:26.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:58:26.14#ibcon#enter wrdev, iclass 39, count 2 2006.286.04:58:26.14#ibcon#first serial, iclass 39, count 2 2006.286.04:58:26.14#ibcon#enter sib2, iclass 39, count 2 2006.286.04:58:26.14#ibcon#flushed, iclass 39, count 2 2006.286.04:58:26.14#ibcon#about to write, iclass 39, count 2 2006.286.04:58:26.14#ibcon#wrote, iclass 39, count 2 2006.286.04:58:26.14#ibcon#about to read 3, iclass 39, count 2 2006.286.04:58:26.16#ibcon#read 3, iclass 39, count 2 2006.286.04:58:26.16#ibcon#about to read 4, iclass 39, count 2 2006.286.04:58:26.16#ibcon#read 4, iclass 39, count 2 2006.286.04:58:26.16#ibcon#about to read 5, iclass 39, count 2 2006.286.04:58:26.16#ibcon#read 5, iclass 39, count 2 2006.286.04:58:26.16#ibcon#about to read 6, iclass 39, count 2 2006.286.04:58:26.16#ibcon#read 6, iclass 39, count 2 2006.286.04:58:26.16#ibcon#end of sib2, iclass 39, count 2 2006.286.04:58:26.16#ibcon#*mode == 0, iclass 39, count 2 2006.286.04:58:26.16#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.04:58:26.16#ibcon#[25=AT07-04\r\n] 2006.286.04:58:26.16#ibcon#*before write, iclass 39, count 2 2006.286.04:58:26.16#ibcon#enter sib2, iclass 39, count 2 2006.286.04:58:26.16#ibcon#flushed, iclass 39, count 2 2006.286.04:58:26.16#ibcon#about to write, iclass 39, count 2 2006.286.04:58:26.16#ibcon#wrote, iclass 39, count 2 2006.286.04:58:26.16#ibcon#about to read 3, iclass 39, count 2 2006.286.04:58:26.19#ibcon#read 3, iclass 39, count 2 2006.286.04:58:26.19#ibcon#about to read 4, iclass 39, count 2 2006.286.04:58:26.19#ibcon#read 4, iclass 39, count 2 2006.286.04:58:26.19#ibcon#about to read 5, iclass 39, count 2 2006.286.04:58:26.19#ibcon#read 5, iclass 39, count 2 2006.286.04:58:26.19#ibcon#about to read 6, iclass 39, count 2 2006.286.04:58:26.19#ibcon#read 6, iclass 39, count 2 2006.286.04:58:26.19#ibcon#end of sib2, iclass 39, count 2 2006.286.04:58:26.19#ibcon#*after write, iclass 39, count 2 2006.286.04:58:26.19#ibcon#*before return 0, iclass 39, count 2 2006.286.04:58:26.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:58:26.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:58:26.19#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.04:58:26.19#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:26.19#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:58:26.31#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:58:26.31#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:58:26.31#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:58:26.31#ibcon#first serial, iclass 39, count 0 2006.286.04:58:26.31#ibcon#enter sib2, iclass 39, count 0 2006.286.04:58:26.31#ibcon#flushed, iclass 39, count 0 2006.286.04:58:26.31#ibcon#about to write, iclass 39, count 0 2006.286.04:58:26.31#ibcon#wrote, iclass 39, count 0 2006.286.04:58:26.31#ibcon#about to read 3, iclass 39, count 0 2006.286.04:58:26.33#ibcon#read 3, iclass 39, count 0 2006.286.04:58:26.33#ibcon#about to read 4, iclass 39, count 0 2006.286.04:58:26.33#ibcon#read 4, iclass 39, count 0 2006.286.04:58:26.33#ibcon#about to read 5, iclass 39, count 0 2006.286.04:58:26.33#ibcon#read 5, iclass 39, count 0 2006.286.04:58:26.33#ibcon#about to read 6, iclass 39, count 0 2006.286.04:58:26.33#ibcon#read 6, iclass 39, count 0 2006.286.04:58:26.33#ibcon#end of sib2, iclass 39, count 0 2006.286.04:58:26.33#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:58:26.33#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:58:26.33#ibcon#[25=USB\r\n] 2006.286.04:58:26.33#ibcon#*before write, iclass 39, count 0 2006.286.04:58:26.33#ibcon#enter sib2, iclass 39, count 0 2006.286.04:58:26.33#ibcon#flushed, iclass 39, count 0 2006.286.04:58:26.33#ibcon#about to write, iclass 39, count 0 2006.286.04:58:26.33#ibcon#wrote, iclass 39, count 0 2006.286.04:58:26.33#ibcon#about to read 3, iclass 39, count 0 2006.286.04:58:26.36#ibcon#read 3, iclass 39, count 0 2006.286.04:58:26.36#ibcon#about to read 4, iclass 39, count 0 2006.286.04:58:26.36#ibcon#read 4, iclass 39, count 0 2006.286.04:58:26.36#ibcon#about to read 5, iclass 39, count 0 2006.286.04:58:26.36#ibcon#read 5, iclass 39, count 0 2006.286.04:58:26.36#ibcon#about to read 6, iclass 39, count 0 2006.286.04:58:26.36#ibcon#read 6, iclass 39, count 0 2006.286.04:58:26.36#ibcon#end of sib2, iclass 39, count 0 2006.286.04:58:26.36#ibcon#*after write, iclass 39, count 0 2006.286.04:58:26.36#ibcon#*before return 0, iclass 39, count 0 2006.286.04:58:26.36#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:58:26.36#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:58:26.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:58:26.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:58:26.36$vck44/valo=8,884.99 2006.286.04:58:26.36#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.04:58:26.36#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.04:58:26.36#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:26.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:58:26.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:58:26.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:58:26.36#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:58:26.36#ibcon#first serial, iclass 3, count 0 2006.286.04:58:26.36#ibcon#enter sib2, iclass 3, count 0 2006.286.04:58:26.36#ibcon#flushed, iclass 3, count 0 2006.286.04:58:26.36#ibcon#about to write, iclass 3, count 0 2006.286.04:58:26.36#ibcon#wrote, iclass 3, count 0 2006.286.04:58:26.36#ibcon#about to read 3, iclass 3, count 0 2006.286.04:58:26.38#ibcon#read 3, iclass 3, count 0 2006.286.04:58:26.38#ibcon#about to read 4, iclass 3, count 0 2006.286.04:58:26.38#ibcon#read 4, iclass 3, count 0 2006.286.04:58:26.38#ibcon#about to read 5, iclass 3, count 0 2006.286.04:58:26.38#ibcon#read 5, iclass 3, count 0 2006.286.04:58:26.38#ibcon#about to read 6, iclass 3, count 0 2006.286.04:58:26.38#ibcon#read 6, iclass 3, count 0 2006.286.04:58:26.38#ibcon#end of sib2, iclass 3, count 0 2006.286.04:58:26.38#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:58:26.38#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:58:26.38#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:58:26.38#ibcon#*before write, iclass 3, count 0 2006.286.04:58:26.38#ibcon#enter sib2, iclass 3, count 0 2006.286.04:58:26.38#ibcon#flushed, iclass 3, count 0 2006.286.04:58:26.38#ibcon#about to write, iclass 3, count 0 2006.286.04:58:26.38#ibcon#wrote, iclass 3, count 0 2006.286.04:58:26.38#ibcon#about to read 3, iclass 3, count 0 2006.286.04:58:26.42#ibcon#read 3, iclass 3, count 0 2006.286.04:58:26.42#ibcon#about to read 4, iclass 3, count 0 2006.286.04:58:26.42#ibcon#read 4, iclass 3, count 0 2006.286.04:58:26.42#ibcon#about to read 5, iclass 3, count 0 2006.286.04:58:26.42#ibcon#read 5, iclass 3, count 0 2006.286.04:58:26.42#ibcon#about to read 6, iclass 3, count 0 2006.286.04:58:26.42#ibcon#read 6, iclass 3, count 0 2006.286.04:58:26.42#ibcon#end of sib2, iclass 3, count 0 2006.286.04:58:26.42#ibcon#*after write, iclass 3, count 0 2006.286.04:58:26.42#ibcon#*before return 0, iclass 3, count 0 2006.286.04:58:26.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:58:26.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:58:26.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:58:26.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:58:26.42$vck44/va=8,3 2006.286.04:58:26.42#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.04:58:26.42#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.04:58:26.42#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:26.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:58:26.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:58:26.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:58:26.48#ibcon#enter wrdev, iclass 5, count 2 2006.286.04:58:26.48#ibcon#first serial, iclass 5, count 2 2006.286.04:58:26.48#ibcon#enter sib2, iclass 5, count 2 2006.286.04:58:26.48#ibcon#flushed, iclass 5, count 2 2006.286.04:58:26.48#ibcon#about to write, iclass 5, count 2 2006.286.04:58:26.48#ibcon#wrote, iclass 5, count 2 2006.286.04:58:26.48#ibcon#about to read 3, iclass 5, count 2 2006.286.04:58:26.50#ibcon#read 3, iclass 5, count 2 2006.286.04:58:26.50#ibcon#about to read 4, iclass 5, count 2 2006.286.04:58:26.50#ibcon#read 4, iclass 5, count 2 2006.286.04:58:26.50#ibcon#about to read 5, iclass 5, count 2 2006.286.04:58:26.50#ibcon#read 5, iclass 5, count 2 2006.286.04:58:26.50#ibcon#about to read 6, iclass 5, count 2 2006.286.04:58:26.50#ibcon#read 6, iclass 5, count 2 2006.286.04:58:26.50#ibcon#end of sib2, iclass 5, count 2 2006.286.04:58:26.50#ibcon#*mode == 0, iclass 5, count 2 2006.286.04:58:26.50#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.04:58:26.50#ibcon#[25=AT08-03\r\n] 2006.286.04:58:26.50#ibcon#*before write, iclass 5, count 2 2006.286.04:58:26.50#ibcon#enter sib2, iclass 5, count 2 2006.286.04:58:26.50#ibcon#flushed, iclass 5, count 2 2006.286.04:58:26.50#ibcon#about to write, iclass 5, count 2 2006.286.04:58:26.50#ibcon#wrote, iclass 5, count 2 2006.286.04:58:26.50#ibcon#about to read 3, iclass 5, count 2 2006.286.04:58:26.53#ibcon#read 3, iclass 5, count 2 2006.286.04:58:26.53#ibcon#about to read 4, iclass 5, count 2 2006.286.04:58:26.53#ibcon#read 4, iclass 5, count 2 2006.286.04:58:26.53#ibcon#about to read 5, iclass 5, count 2 2006.286.04:58:26.53#ibcon#read 5, iclass 5, count 2 2006.286.04:58:26.53#ibcon#about to read 6, iclass 5, count 2 2006.286.04:58:26.53#ibcon#read 6, iclass 5, count 2 2006.286.04:58:26.53#ibcon#end of sib2, iclass 5, count 2 2006.286.04:58:26.53#ibcon#*after write, iclass 5, count 2 2006.286.04:58:26.53#ibcon#*before return 0, iclass 5, count 2 2006.286.04:58:26.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:58:26.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.04:58:26.53#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.04:58:26.53#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:26.53#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:58:26.65#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:58:26.65#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:58:26.65#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:58:26.65#ibcon#first serial, iclass 5, count 0 2006.286.04:58:26.65#ibcon#enter sib2, iclass 5, count 0 2006.286.04:58:26.65#ibcon#flushed, iclass 5, count 0 2006.286.04:58:26.65#ibcon#about to write, iclass 5, count 0 2006.286.04:58:26.65#ibcon#wrote, iclass 5, count 0 2006.286.04:58:26.65#ibcon#about to read 3, iclass 5, count 0 2006.286.04:58:26.67#ibcon#read 3, iclass 5, count 0 2006.286.04:58:26.67#ibcon#about to read 4, iclass 5, count 0 2006.286.04:58:26.67#ibcon#read 4, iclass 5, count 0 2006.286.04:58:26.67#ibcon#about to read 5, iclass 5, count 0 2006.286.04:58:26.67#ibcon#read 5, iclass 5, count 0 2006.286.04:58:26.67#ibcon#about to read 6, iclass 5, count 0 2006.286.04:58:26.67#ibcon#read 6, iclass 5, count 0 2006.286.04:58:26.67#ibcon#end of sib2, iclass 5, count 0 2006.286.04:58:26.67#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:58:26.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:58:26.67#ibcon#[25=USB\r\n] 2006.286.04:58:26.67#ibcon#*before write, iclass 5, count 0 2006.286.04:58:26.67#ibcon#enter sib2, iclass 5, count 0 2006.286.04:58:26.67#ibcon#flushed, iclass 5, count 0 2006.286.04:58:26.67#ibcon#about to write, iclass 5, count 0 2006.286.04:58:26.67#ibcon#wrote, iclass 5, count 0 2006.286.04:58:26.67#ibcon#about to read 3, iclass 5, count 0 2006.286.04:58:26.70#ibcon#read 3, iclass 5, count 0 2006.286.04:58:26.70#ibcon#about to read 4, iclass 5, count 0 2006.286.04:58:26.70#ibcon#read 4, iclass 5, count 0 2006.286.04:58:26.70#ibcon#about to read 5, iclass 5, count 0 2006.286.04:58:26.70#ibcon#read 5, iclass 5, count 0 2006.286.04:58:26.70#ibcon#about to read 6, iclass 5, count 0 2006.286.04:58:26.70#ibcon#read 6, iclass 5, count 0 2006.286.04:58:26.70#ibcon#end of sib2, iclass 5, count 0 2006.286.04:58:26.70#ibcon#*after write, iclass 5, count 0 2006.286.04:58:26.70#ibcon#*before return 0, iclass 5, count 0 2006.286.04:58:26.70#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:58:26.70#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.04:58:26.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:58:26.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:58:26.70$vck44/vblo=1,629.99 2006.286.04:58:26.70#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.04:58:26.70#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.04:58:26.70#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:26.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:58:26.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:58:26.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:58:26.70#ibcon#enter wrdev, iclass 7, count 0 2006.286.04:58:26.70#ibcon#first serial, iclass 7, count 0 2006.286.04:58:26.70#ibcon#enter sib2, iclass 7, count 0 2006.286.04:58:26.70#ibcon#flushed, iclass 7, count 0 2006.286.04:58:26.70#ibcon#about to write, iclass 7, count 0 2006.286.04:58:26.70#ibcon#wrote, iclass 7, count 0 2006.286.04:58:26.70#ibcon#about to read 3, iclass 7, count 0 2006.286.04:58:26.72#ibcon#read 3, iclass 7, count 0 2006.286.04:58:26.73#ibcon#about to read 4, iclass 7, count 0 2006.286.04:58:26.73#ibcon#read 4, iclass 7, count 0 2006.286.04:58:26.73#ibcon#about to read 5, iclass 7, count 0 2006.286.04:58:26.73#ibcon#read 5, iclass 7, count 0 2006.286.04:58:26.73#ibcon#about to read 6, iclass 7, count 0 2006.286.04:58:26.73#ibcon#read 6, iclass 7, count 0 2006.286.04:58:26.73#ibcon#end of sib2, iclass 7, count 0 2006.286.04:58:26.73#ibcon#*mode == 0, iclass 7, count 0 2006.286.04:58:26.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.04:58:26.73#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:58:26.73#ibcon#*before write, iclass 7, count 0 2006.286.04:58:26.73#ibcon#enter sib2, iclass 7, count 0 2006.286.04:58:26.73#ibcon#flushed, iclass 7, count 0 2006.286.04:58:26.73#ibcon#about to write, iclass 7, count 0 2006.286.04:58:26.73#ibcon#wrote, iclass 7, count 0 2006.286.04:58:26.73#ibcon#about to read 3, iclass 7, count 0 2006.286.04:58:26.77#ibcon#read 3, iclass 7, count 0 2006.286.04:58:26.77#ibcon#about to read 4, iclass 7, count 0 2006.286.04:58:26.77#ibcon#read 4, iclass 7, count 0 2006.286.04:58:26.77#ibcon#about to read 5, iclass 7, count 0 2006.286.04:58:26.77#ibcon#read 5, iclass 7, count 0 2006.286.04:58:26.77#ibcon#about to read 6, iclass 7, count 0 2006.286.04:58:26.77#ibcon#read 6, iclass 7, count 0 2006.286.04:58:26.77#ibcon#end of sib2, iclass 7, count 0 2006.286.04:58:26.77#ibcon#*after write, iclass 7, count 0 2006.286.04:58:26.77#ibcon#*before return 0, iclass 7, count 0 2006.286.04:58:26.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:58:26.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.04:58:26.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.04:58:26.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.04:58:26.77$vck44/vb=1,4 2006.286.04:58:26.77#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.04:58:26.77#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.04:58:26.77#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:26.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.04:58:26.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.04:58:26.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.04:58:26.77#ibcon#enter wrdev, iclass 11, count 2 2006.286.04:58:26.77#ibcon#first serial, iclass 11, count 2 2006.286.04:58:26.77#ibcon#enter sib2, iclass 11, count 2 2006.286.04:58:26.77#ibcon#flushed, iclass 11, count 2 2006.286.04:58:26.77#ibcon#about to write, iclass 11, count 2 2006.286.04:58:26.77#ibcon#wrote, iclass 11, count 2 2006.286.04:58:26.77#ibcon#about to read 3, iclass 11, count 2 2006.286.04:58:26.79#ibcon#read 3, iclass 11, count 2 2006.286.04:58:26.79#ibcon#about to read 4, iclass 11, count 2 2006.286.04:58:26.79#ibcon#read 4, iclass 11, count 2 2006.286.04:58:26.79#ibcon#about to read 5, iclass 11, count 2 2006.286.04:58:26.79#ibcon#read 5, iclass 11, count 2 2006.286.04:58:26.79#ibcon#about to read 6, iclass 11, count 2 2006.286.04:58:26.79#ibcon#read 6, iclass 11, count 2 2006.286.04:58:26.79#ibcon#end of sib2, iclass 11, count 2 2006.286.04:58:26.79#ibcon#*mode == 0, iclass 11, count 2 2006.286.04:58:26.79#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.04:58:26.79#ibcon#[27=AT01-04\r\n] 2006.286.04:58:26.79#ibcon#*before write, iclass 11, count 2 2006.286.04:58:26.79#ibcon#enter sib2, iclass 11, count 2 2006.286.04:58:26.79#ibcon#flushed, iclass 11, count 2 2006.286.04:58:26.79#ibcon#about to write, iclass 11, count 2 2006.286.04:58:26.79#ibcon#wrote, iclass 11, count 2 2006.286.04:58:26.79#ibcon#about to read 3, iclass 11, count 2 2006.286.04:58:26.82#ibcon#read 3, iclass 11, count 2 2006.286.04:58:26.82#ibcon#about to read 4, iclass 11, count 2 2006.286.04:58:26.82#ibcon#read 4, iclass 11, count 2 2006.286.04:58:26.82#ibcon#about to read 5, iclass 11, count 2 2006.286.04:58:26.82#ibcon#read 5, iclass 11, count 2 2006.286.04:58:26.82#ibcon#about to read 6, iclass 11, count 2 2006.286.04:58:26.82#ibcon#read 6, iclass 11, count 2 2006.286.04:58:26.82#ibcon#end of sib2, iclass 11, count 2 2006.286.04:58:26.82#ibcon#*after write, iclass 11, count 2 2006.286.04:58:26.82#ibcon#*before return 0, iclass 11, count 2 2006.286.04:58:26.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.04:58:26.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.04:58:26.82#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.04:58:26.82#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:26.82#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.04:58:26.94#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.04:58:26.94#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.04:58:26.94#ibcon#enter wrdev, iclass 11, count 0 2006.286.04:58:26.94#ibcon#first serial, iclass 11, count 0 2006.286.04:58:26.94#ibcon#enter sib2, iclass 11, count 0 2006.286.04:58:26.94#ibcon#flushed, iclass 11, count 0 2006.286.04:58:26.94#ibcon#about to write, iclass 11, count 0 2006.286.04:58:26.94#ibcon#wrote, iclass 11, count 0 2006.286.04:58:26.94#ibcon#about to read 3, iclass 11, count 0 2006.286.04:58:26.96#ibcon#read 3, iclass 11, count 0 2006.286.04:58:26.96#ibcon#about to read 4, iclass 11, count 0 2006.286.04:58:26.96#ibcon#read 4, iclass 11, count 0 2006.286.04:58:26.96#ibcon#about to read 5, iclass 11, count 0 2006.286.04:58:26.96#ibcon#read 5, iclass 11, count 0 2006.286.04:58:26.96#ibcon#about to read 6, iclass 11, count 0 2006.286.04:58:26.96#ibcon#read 6, iclass 11, count 0 2006.286.04:58:26.96#ibcon#end of sib2, iclass 11, count 0 2006.286.04:58:26.96#ibcon#*mode == 0, iclass 11, count 0 2006.286.04:58:26.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.04:58:26.96#ibcon#[27=USB\r\n] 2006.286.04:58:26.96#ibcon#*before write, iclass 11, count 0 2006.286.04:58:26.96#ibcon#enter sib2, iclass 11, count 0 2006.286.04:58:26.96#ibcon#flushed, iclass 11, count 0 2006.286.04:58:26.96#ibcon#about to write, iclass 11, count 0 2006.286.04:58:26.96#ibcon#wrote, iclass 11, count 0 2006.286.04:58:26.96#ibcon#about to read 3, iclass 11, count 0 2006.286.04:58:26.99#ibcon#read 3, iclass 11, count 0 2006.286.04:58:26.99#ibcon#about to read 4, iclass 11, count 0 2006.286.04:58:26.99#ibcon#read 4, iclass 11, count 0 2006.286.04:58:26.99#ibcon#about to read 5, iclass 11, count 0 2006.286.04:58:26.99#ibcon#read 5, iclass 11, count 0 2006.286.04:58:26.99#ibcon#about to read 6, iclass 11, count 0 2006.286.04:58:26.99#ibcon#read 6, iclass 11, count 0 2006.286.04:58:26.99#ibcon#end of sib2, iclass 11, count 0 2006.286.04:58:26.99#ibcon#*after write, iclass 11, count 0 2006.286.04:58:26.99#ibcon#*before return 0, iclass 11, count 0 2006.286.04:58:26.99#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.04:58:26.99#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.04:58:26.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.04:58:26.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.04:58:26.99$vck44/vblo=2,634.99 2006.286.04:58:26.99#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.04:58:26.99#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.04:58:26.99#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:26.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:58:26.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:58:26.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:58:26.99#ibcon#enter wrdev, iclass 13, count 0 2006.286.04:58:26.99#ibcon#first serial, iclass 13, count 0 2006.286.04:58:26.99#ibcon#enter sib2, iclass 13, count 0 2006.286.04:58:26.99#ibcon#flushed, iclass 13, count 0 2006.286.04:58:26.99#ibcon#about to write, iclass 13, count 0 2006.286.04:58:26.99#ibcon#wrote, iclass 13, count 0 2006.286.04:58:26.99#ibcon#about to read 3, iclass 13, count 0 2006.286.04:58:27.01#ibcon#read 3, iclass 13, count 0 2006.286.04:58:27.01#ibcon#about to read 4, iclass 13, count 0 2006.286.04:58:27.01#ibcon#read 4, iclass 13, count 0 2006.286.04:58:27.01#ibcon#about to read 5, iclass 13, count 0 2006.286.04:58:27.01#ibcon#read 5, iclass 13, count 0 2006.286.04:58:27.01#ibcon#about to read 6, iclass 13, count 0 2006.286.04:58:27.01#ibcon#read 6, iclass 13, count 0 2006.286.04:58:27.01#ibcon#end of sib2, iclass 13, count 0 2006.286.04:58:27.01#ibcon#*mode == 0, iclass 13, count 0 2006.286.04:58:27.01#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.04:58:27.01#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:58:27.01#ibcon#*before write, iclass 13, count 0 2006.286.04:58:27.01#ibcon#enter sib2, iclass 13, count 0 2006.286.04:58:27.01#ibcon#flushed, iclass 13, count 0 2006.286.04:58:27.01#ibcon#about to write, iclass 13, count 0 2006.286.04:58:27.01#ibcon#wrote, iclass 13, count 0 2006.286.04:58:27.01#ibcon#about to read 3, iclass 13, count 0 2006.286.04:58:27.05#ibcon#read 3, iclass 13, count 0 2006.286.04:58:27.05#ibcon#about to read 4, iclass 13, count 0 2006.286.04:58:27.05#ibcon#read 4, iclass 13, count 0 2006.286.04:58:27.05#ibcon#about to read 5, iclass 13, count 0 2006.286.04:58:27.05#ibcon#read 5, iclass 13, count 0 2006.286.04:58:27.05#ibcon#about to read 6, iclass 13, count 0 2006.286.04:58:27.05#ibcon#read 6, iclass 13, count 0 2006.286.04:58:27.05#ibcon#end of sib2, iclass 13, count 0 2006.286.04:58:27.05#ibcon#*after write, iclass 13, count 0 2006.286.04:58:27.05#ibcon#*before return 0, iclass 13, count 0 2006.286.04:58:27.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:58:27.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.04:58:27.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.04:58:27.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.04:58:27.05$vck44/vb=2,5 2006.286.04:58:27.05#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.04:58:27.05#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.04:58:27.05#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:27.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:58:27.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:58:27.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:58:27.11#ibcon#enter wrdev, iclass 15, count 2 2006.286.04:58:27.11#ibcon#first serial, iclass 15, count 2 2006.286.04:58:27.11#ibcon#enter sib2, iclass 15, count 2 2006.286.04:58:27.11#ibcon#flushed, iclass 15, count 2 2006.286.04:58:27.11#ibcon#about to write, iclass 15, count 2 2006.286.04:58:27.11#ibcon#wrote, iclass 15, count 2 2006.286.04:58:27.11#ibcon#about to read 3, iclass 15, count 2 2006.286.04:58:27.13#ibcon#read 3, iclass 15, count 2 2006.286.04:58:27.13#ibcon#about to read 4, iclass 15, count 2 2006.286.04:58:27.13#ibcon#read 4, iclass 15, count 2 2006.286.04:58:27.13#ibcon#about to read 5, iclass 15, count 2 2006.286.04:58:27.13#ibcon#read 5, iclass 15, count 2 2006.286.04:58:27.13#ibcon#about to read 6, iclass 15, count 2 2006.286.04:58:27.13#ibcon#read 6, iclass 15, count 2 2006.286.04:58:27.13#ibcon#end of sib2, iclass 15, count 2 2006.286.04:58:27.13#ibcon#*mode == 0, iclass 15, count 2 2006.286.04:58:27.13#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.04:58:27.13#ibcon#[27=AT02-05\r\n] 2006.286.04:58:27.13#ibcon#*before write, iclass 15, count 2 2006.286.04:58:27.13#ibcon#enter sib2, iclass 15, count 2 2006.286.04:58:27.13#ibcon#flushed, iclass 15, count 2 2006.286.04:58:27.13#ibcon#about to write, iclass 15, count 2 2006.286.04:58:27.13#ibcon#wrote, iclass 15, count 2 2006.286.04:58:27.13#ibcon#about to read 3, iclass 15, count 2 2006.286.04:58:27.16#ibcon#read 3, iclass 15, count 2 2006.286.04:58:27.16#ibcon#about to read 4, iclass 15, count 2 2006.286.04:58:27.16#ibcon#read 4, iclass 15, count 2 2006.286.04:58:27.16#ibcon#about to read 5, iclass 15, count 2 2006.286.04:58:27.16#ibcon#read 5, iclass 15, count 2 2006.286.04:58:27.16#ibcon#about to read 6, iclass 15, count 2 2006.286.04:58:27.16#ibcon#read 6, iclass 15, count 2 2006.286.04:58:27.16#ibcon#end of sib2, iclass 15, count 2 2006.286.04:58:27.16#ibcon#*after write, iclass 15, count 2 2006.286.04:58:27.16#ibcon#*before return 0, iclass 15, count 2 2006.286.04:58:27.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:58:27.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.04:58:27.16#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.04:58:27.16#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:27.16#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:58:27.28#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:58:27.28#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:58:27.28#ibcon#enter wrdev, iclass 15, count 0 2006.286.04:58:27.28#ibcon#first serial, iclass 15, count 0 2006.286.04:58:27.28#ibcon#enter sib2, iclass 15, count 0 2006.286.04:58:27.28#ibcon#flushed, iclass 15, count 0 2006.286.04:58:27.28#ibcon#about to write, iclass 15, count 0 2006.286.04:58:27.28#ibcon#wrote, iclass 15, count 0 2006.286.04:58:27.28#ibcon#about to read 3, iclass 15, count 0 2006.286.04:58:27.30#ibcon#read 3, iclass 15, count 0 2006.286.04:58:27.30#ibcon#about to read 4, iclass 15, count 0 2006.286.04:58:27.30#ibcon#read 4, iclass 15, count 0 2006.286.04:58:27.30#ibcon#about to read 5, iclass 15, count 0 2006.286.04:58:27.30#ibcon#read 5, iclass 15, count 0 2006.286.04:58:27.30#ibcon#about to read 6, iclass 15, count 0 2006.286.04:58:27.30#ibcon#read 6, iclass 15, count 0 2006.286.04:58:27.30#ibcon#end of sib2, iclass 15, count 0 2006.286.04:58:27.30#ibcon#*mode == 0, iclass 15, count 0 2006.286.04:58:27.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.04:58:27.30#ibcon#[27=USB\r\n] 2006.286.04:58:27.30#ibcon#*before write, iclass 15, count 0 2006.286.04:58:27.30#ibcon#enter sib2, iclass 15, count 0 2006.286.04:58:27.30#ibcon#flushed, iclass 15, count 0 2006.286.04:58:27.30#ibcon#about to write, iclass 15, count 0 2006.286.04:58:27.30#ibcon#wrote, iclass 15, count 0 2006.286.04:58:27.30#ibcon#about to read 3, iclass 15, count 0 2006.286.04:58:27.33#ibcon#read 3, iclass 15, count 0 2006.286.04:58:27.33#ibcon#about to read 4, iclass 15, count 0 2006.286.04:58:27.33#ibcon#read 4, iclass 15, count 0 2006.286.04:58:27.33#ibcon#about to read 5, iclass 15, count 0 2006.286.04:58:27.33#ibcon#read 5, iclass 15, count 0 2006.286.04:58:27.33#ibcon#about to read 6, iclass 15, count 0 2006.286.04:58:27.33#ibcon#read 6, iclass 15, count 0 2006.286.04:58:27.33#ibcon#end of sib2, iclass 15, count 0 2006.286.04:58:27.33#ibcon#*after write, iclass 15, count 0 2006.286.04:58:27.33#ibcon#*before return 0, iclass 15, count 0 2006.286.04:58:27.33#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:58:27.33#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.04:58:27.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.04:58:27.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.04:58:27.33$vck44/vblo=3,649.99 2006.286.04:58:27.33#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.04:58:27.33#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.04:58:27.33#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:27.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:58:27.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:58:27.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:58:27.33#ibcon#enter wrdev, iclass 17, count 0 2006.286.04:58:27.33#ibcon#first serial, iclass 17, count 0 2006.286.04:58:27.33#ibcon#enter sib2, iclass 17, count 0 2006.286.04:58:27.33#ibcon#flushed, iclass 17, count 0 2006.286.04:58:27.33#ibcon#about to write, iclass 17, count 0 2006.286.04:58:27.33#ibcon#wrote, iclass 17, count 0 2006.286.04:58:27.33#ibcon#about to read 3, iclass 17, count 0 2006.286.04:58:27.35#ibcon#read 3, iclass 17, count 0 2006.286.04:58:27.35#ibcon#about to read 4, iclass 17, count 0 2006.286.04:58:27.35#ibcon#read 4, iclass 17, count 0 2006.286.04:58:27.35#ibcon#about to read 5, iclass 17, count 0 2006.286.04:58:27.35#ibcon#read 5, iclass 17, count 0 2006.286.04:58:27.35#ibcon#about to read 6, iclass 17, count 0 2006.286.04:58:27.35#ibcon#read 6, iclass 17, count 0 2006.286.04:58:27.35#ibcon#end of sib2, iclass 17, count 0 2006.286.04:58:27.35#ibcon#*mode == 0, iclass 17, count 0 2006.286.04:58:27.35#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.04:58:27.35#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:58:27.35#ibcon#*before write, iclass 17, count 0 2006.286.04:58:27.35#ibcon#enter sib2, iclass 17, count 0 2006.286.04:58:27.35#ibcon#flushed, iclass 17, count 0 2006.286.04:58:27.35#ibcon#about to write, iclass 17, count 0 2006.286.04:58:27.35#ibcon#wrote, iclass 17, count 0 2006.286.04:58:27.35#ibcon#about to read 3, iclass 17, count 0 2006.286.04:58:27.39#ibcon#read 3, iclass 17, count 0 2006.286.04:58:27.39#ibcon#about to read 4, iclass 17, count 0 2006.286.04:58:27.39#ibcon#read 4, iclass 17, count 0 2006.286.04:58:27.39#ibcon#about to read 5, iclass 17, count 0 2006.286.04:58:27.39#ibcon#read 5, iclass 17, count 0 2006.286.04:58:27.39#ibcon#about to read 6, iclass 17, count 0 2006.286.04:58:27.39#ibcon#read 6, iclass 17, count 0 2006.286.04:58:27.39#ibcon#end of sib2, iclass 17, count 0 2006.286.04:58:27.39#ibcon#*after write, iclass 17, count 0 2006.286.04:58:27.39#ibcon#*before return 0, iclass 17, count 0 2006.286.04:58:27.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:58:27.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.04:58:27.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.04:58:27.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.04:58:27.39$vck44/vb=3,4 2006.286.04:58:27.39#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.04:58:27.39#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.04:58:27.39#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:27.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:58:27.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:58:27.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:58:27.45#ibcon#enter wrdev, iclass 19, count 2 2006.286.04:58:27.45#ibcon#first serial, iclass 19, count 2 2006.286.04:58:27.45#ibcon#enter sib2, iclass 19, count 2 2006.286.04:58:27.45#ibcon#flushed, iclass 19, count 2 2006.286.04:58:27.45#ibcon#about to write, iclass 19, count 2 2006.286.04:58:27.45#ibcon#wrote, iclass 19, count 2 2006.286.04:58:27.45#ibcon#about to read 3, iclass 19, count 2 2006.286.04:58:27.47#ibcon#read 3, iclass 19, count 2 2006.286.04:58:27.47#ibcon#about to read 4, iclass 19, count 2 2006.286.04:58:27.47#ibcon#read 4, iclass 19, count 2 2006.286.04:58:27.47#ibcon#about to read 5, iclass 19, count 2 2006.286.04:58:27.47#ibcon#read 5, iclass 19, count 2 2006.286.04:58:27.47#ibcon#about to read 6, iclass 19, count 2 2006.286.04:58:27.47#ibcon#read 6, iclass 19, count 2 2006.286.04:58:27.47#ibcon#end of sib2, iclass 19, count 2 2006.286.04:58:27.47#ibcon#*mode == 0, iclass 19, count 2 2006.286.04:58:27.47#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.04:58:27.47#ibcon#[27=AT03-04\r\n] 2006.286.04:58:27.47#ibcon#*before write, iclass 19, count 2 2006.286.04:58:27.47#ibcon#enter sib2, iclass 19, count 2 2006.286.04:58:27.47#ibcon#flushed, iclass 19, count 2 2006.286.04:58:27.47#ibcon#about to write, iclass 19, count 2 2006.286.04:58:27.47#ibcon#wrote, iclass 19, count 2 2006.286.04:58:27.47#ibcon#about to read 3, iclass 19, count 2 2006.286.04:58:27.50#ibcon#read 3, iclass 19, count 2 2006.286.04:58:27.50#ibcon#about to read 4, iclass 19, count 2 2006.286.04:58:27.50#ibcon#read 4, iclass 19, count 2 2006.286.04:58:27.50#ibcon#about to read 5, iclass 19, count 2 2006.286.04:58:27.50#ibcon#read 5, iclass 19, count 2 2006.286.04:58:27.50#ibcon#about to read 6, iclass 19, count 2 2006.286.04:58:27.50#ibcon#read 6, iclass 19, count 2 2006.286.04:58:27.50#ibcon#end of sib2, iclass 19, count 2 2006.286.04:58:27.50#ibcon#*after write, iclass 19, count 2 2006.286.04:58:27.50#ibcon#*before return 0, iclass 19, count 2 2006.286.04:58:27.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:58:27.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.04:58:27.50#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.04:58:27.50#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:27.50#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:58:27.62#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:58:27.62#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:58:27.62#ibcon#enter wrdev, iclass 19, count 0 2006.286.04:58:27.62#ibcon#first serial, iclass 19, count 0 2006.286.04:58:27.62#ibcon#enter sib2, iclass 19, count 0 2006.286.04:58:27.62#ibcon#flushed, iclass 19, count 0 2006.286.04:58:27.62#ibcon#about to write, iclass 19, count 0 2006.286.04:58:27.62#ibcon#wrote, iclass 19, count 0 2006.286.04:58:27.62#ibcon#about to read 3, iclass 19, count 0 2006.286.04:58:27.64#ibcon#read 3, iclass 19, count 0 2006.286.04:58:27.64#ibcon#about to read 4, iclass 19, count 0 2006.286.04:58:27.64#ibcon#read 4, iclass 19, count 0 2006.286.04:58:27.64#ibcon#about to read 5, iclass 19, count 0 2006.286.04:58:27.64#ibcon#read 5, iclass 19, count 0 2006.286.04:58:27.64#ibcon#about to read 6, iclass 19, count 0 2006.286.04:58:27.64#ibcon#read 6, iclass 19, count 0 2006.286.04:58:27.64#ibcon#end of sib2, iclass 19, count 0 2006.286.04:58:27.64#ibcon#*mode == 0, iclass 19, count 0 2006.286.04:58:27.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.04:58:27.64#ibcon#[27=USB\r\n] 2006.286.04:58:27.64#ibcon#*before write, iclass 19, count 0 2006.286.04:58:27.64#ibcon#enter sib2, iclass 19, count 0 2006.286.04:58:27.64#ibcon#flushed, iclass 19, count 0 2006.286.04:58:27.64#ibcon#about to write, iclass 19, count 0 2006.286.04:58:27.64#ibcon#wrote, iclass 19, count 0 2006.286.04:58:27.64#ibcon#about to read 3, iclass 19, count 0 2006.286.04:58:27.67#ibcon#read 3, iclass 19, count 0 2006.286.04:58:27.67#ibcon#about to read 4, iclass 19, count 0 2006.286.04:58:27.67#ibcon#read 4, iclass 19, count 0 2006.286.04:58:27.67#ibcon#about to read 5, iclass 19, count 0 2006.286.04:58:27.67#ibcon#read 5, iclass 19, count 0 2006.286.04:58:27.67#ibcon#about to read 6, iclass 19, count 0 2006.286.04:58:27.67#ibcon#read 6, iclass 19, count 0 2006.286.04:58:27.67#ibcon#end of sib2, iclass 19, count 0 2006.286.04:58:27.67#ibcon#*after write, iclass 19, count 0 2006.286.04:58:27.67#ibcon#*before return 0, iclass 19, count 0 2006.286.04:58:27.67#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:58:27.67#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.04:58:27.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.04:58:27.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.04:58:27.67$vck44/vblo=4,679.99 2006.286.04:58:27.67#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.04:58:27.67#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.04:58:27.67#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:27.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:58:27.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:58:27.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:58:27.67#ibcon#enter wrdev, iclass 21, count 0 2006.286.04:58:27.67#ibcon#first serial, iclass 21, count 0 2006.286.04:58:27.67#ibcon#enter sib2, iclass 21, count 0 2006.286.04:58:27.67#ibcon#flushed, iclass 21, count 0 2006.286.04:58:27.67#ibcon#about to write, iclass 21, count 0 2006.286.04:58:27.67#ibcon#wrote, iclass 21, count 0 2006.286.04:58:27.67#ibcon#about to read 3, iclass 21, count 0 2006.286.04:58:27.69#ibcon#read 3, iclass 21, count 0 2006.286.04:58:27.83#ibcon#about to read 4, iclass 21, count 0 2006.286.04:58:27.83#ibcon#read 4, iclass 21, count 0 2006.286.04:58:27.83#ibcon#about to read 5, iclass 21, count 0 2006.286.04:58:27.83#ibcon#read 5, iclass 21, count 0 2006.286.04:58:27.83#ibcon#about to read 6, iclass 21, count 0 2006.286.04:58:27.83#ibcon#read 6, iclass 21, count 0 2006.286.04:58:27.83#ibcon#end of sib2, iclass 21, count 0 2006.286.04:58:27.83#ibcon#*mode == 0, iclass 21, count 0 2006.286.04:58:27.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.04:58:27.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:58:27.83#ibcon#*before write, iclass 21, count 0 2006.286.04:58:27.83#ibcon#enter sib2, iclass 21, count 0 2006.286.04:58:27.83#ibcon#flushed, iclass 21, count 0 2006.286.04:58:27.83#ibcon#about to write, iclass 21, count 0 2006.286.04:58:27.83#ibcon#wrote, iclass 21, count 0 2006.286.04:58:27.83#ibcon#about to read 3, iclass 21, count 0 2006.286.04:58:27.87#ibcon#read 3, iclass 21, count 0 2006.286.04:58:27.87#ibcon#about to read 4, iclass 21, count 0 2006.286.04:58:27.87#ibcon#read 4, iclass 21, count 0 2006.286.04:58:27.87#ibcon#about to read 5, iclass 21, count 0 2006.286.04:58:27.87#ibcon#read 5, iclass 21, count 0 2006.286.04:58:27.87#ibcon#about to read 6, iclass 21, count 0 2006.286.04:58:27.87#ibcon#read 6, iclass 21, count 0 2006.286.04:58:27.87#ibcon#end of sib2, iclass 21, count 0 2006.286.04:58:27.87#ibcon#*after write, iclass 21, count 0 2006.286.04:58:27.87#ibcon#*before return 0, iclass 21, count 0 2006.286.04:58:27.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:58:27.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.04:58:27.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.04:58:27.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.04:58:27.87$vck44/vb=4,5 2006.286.04:58:27.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.04:58:27.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.04:58:27.87#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:27.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:58:27.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:58:27.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:58:27.87#ibcon#enter wrdev, iclass 23, count 2 2006.286.04:58:27.87#ibcon#first serial, iclass 23, count 2 2006.286.04:58:27.87#ibcon#enter sib2, iclass 23, count 2 2006.286.04:58:27.87#ibcon#flushed, iclass 23, count 2 2006.286.04:58:27.87#ibcon#about to write, iclass 23, count 2 2006.286.04:58:27.87#ibcon#wrote, iclass 23, count 2 2006.286.04:58:27.87#ibcon#about to read 3, iclass 23, count 2 2006.286.04:58:27.89#ibcon#read 3, iclass 23, count 2 2006.286.04:58:27.89#ibcon#about to read 4, iclass 23, count 2 2006.286.04:58:27.89#ibcon#read 4, iclass 23, count 2 2006.286.04:58:27.89#ibcon#about to read 5, iclass 23, count 2 2006.286.04:58:27.89#ibcon#read 5, iclass 23, count 2 2006.286.04:58:27.89#ibcon#about to read 6, iclass 23, count 2 2006.286.04:58:27.89#ibcon#read 6, iclass 23, count 2 2006.286.04:58:27.89#ibcon#end of sib2, iclass 23, count 2 2006.286.04:58:27.89#ibcon#*mode == 0, iclass 23, count 2 2006.286.04:58:27.89#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.04:58:27.89#ibcon#[27=AT04-05\r\n] 2006.286.04:58:27.89#ibcon#*before write, iclass 23, count 2 2006.286.04:58:27.89#ibcon#enter sib2, iclass 23, count 2 2006.286.04:58:27.89#ibcon#flushed, iclass 23, count 2 2006.286.04:58:27.89#ibcon#about to write, iclass 23, count 2 2006.286.04:58:27.89#ibcon#wrote, iclass 23, count 2 2006.286.04:58:27.89#ibcon#about to read 3, iclass 23, count 2 2006.286.04:58:27.92#ibcon#read 3, iclass 23, count 2 2006.286.04:58:27.92#ibcon#about to read 4, iclass 23, count 2 2006.286.04:58:27.92#ibcon#read 4, iclass 23, count 2 2006.286.04:58:27.92#ibcon#about to read 5, iclass 23, count 2 2006.286.04:58:27.92#ibcon#read 5, iclass 23, count 2 2006.286.04:58:27.92#ibcon#about to read 6, iclass 23, count 2 2006.286.04:58:27.92#ibcon#read 6, iclass 23, count 2 2006.286.04:58:27.92#ibcon#end of sib2, iclass 23, count 2 2006.286.04:58:27.92#ibcon#*after write, iclass 23, count 2 2006.286.04:58:27.92#ibcon#*before return 0, iclass 23, count 2 2006.286.04:58:27.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:58:27.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.04:58:27.92#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.04:58:27.92#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:27.92#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:58:28.04#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:58:28.04#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:58:28.04#ibcon#enter wrdev, iclass 23, count 0 2006.286.04:58:28.04#ibcon#first serial, iclass 23, count 0 2006.286.04:58:28.04#ibcon#enter sib2, iclass 23, count 0 2006.286.04:58:28.04#ibcon#flushed, iclass 23, count 0 2006.286.04:58:28.04#ibcon#about to write, iclass 23, count 0 2006.286.04:58:28.04#ibcon#wrote, iclass 23, count 0 2006.286.04:58:28.04#ibcon#about to read 3, iclass 23, count 0 2006.286.04:58:28.06#ibcon#read 3, iclass 23, count 0 2006.286.04:58:28.06#ibcon#about to read 4, iclass 23, count 0 2006.286.04:58:28.06#ibcon#read 4, iclass 23, count 0 2006.286.04:58:28.06#ibcon#about to read 5, iclass 23, count 0 2006.286.04:58:28.06#ibcon#read 5, iclass 23, count 0 2006.286.04:58:28.06#ibcon#about to read 6, iclass 23, count 0 2006.286.04:58:28.06#ibcon#read 6, iclass 23, count 0 2006.286.04:58:28.06#ibcon#end of sib2, iclass 23, count 0 2006.286.04:58:28.06#ibcon#*mode == 0, iclass 23, count 0 2006.286.04:58:28.06#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.04:58:28.06#ibcon#[27=USB\r\n] 2006.286.04:58:28.06#ibcon#*before write, iclass 23, count 0 2006.286.04:58:28.06#ibcon#enter sib2, iclass 23, count 0 2006.286.04:58:28.06#ibcon#flushed, iclass 23, count 0 2006.286.04:58:28.06#ibcon#about to write, iclass 23, count 0 2006.286.04:58:28.06#ibcon#wrote, iclass 23, count 0 2006.286.04:58:28.06#ibcon#about to read 3, iclass 23, count 0 2006.286.04:58:28.09#ibcon#read 3, iclass 23, count 0 2006.286.04:58:28.09#ibcon#about to read 4, iclass 23, count 0 2006.286.04:58:28.09#ibcon#read 4, iclass 23, count 0 2006.286.04:58:28.09#ibcon#about to read 5, iclass 23, count 0 2006.286.04:58:28.09#ibcon#read 5, iclass 23, count 0 2006.286.04:58:28.09#ibcon#about to read 6, iclass 23, count 0 2006.286.04:58:28.09#ibcon#read 6, iclass 23, count 0 2006.286.04:58:28.09#ibcon#end of sib2, iclass 23, count 0 2006.286.04:58:28.09#ibcon#*after write, iclass 23, count 0 2006.286.04:58:28.09#ibcon#*before return 0, iclass 23, count 0 2006.286.04:58:28.09#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:58:28.09#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.04:58:28.09#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.04:58:28.09#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.04:58:28.09$vck44/vblo=5,709.99 2006.286.04:58:28.09#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.04:58:28.09#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.04:58:28.09#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:28.09#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:58:28.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:58:28.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:58:28.09#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:58:28.09#ibcon#first serial, iclass 25, count 0 2006.286.04:58:28.09#ibcon#enter sib2, iclass 25, count 0 2006.286.04:58:28.09#ibcon#flushed, iclass 25, count 0 2006.286.04:58:28.09#ibcon#about to write, iclass 25, count 0 2006.286.04:58:28.09#ibcon#wrote, iclass 25, count 0 2006.286.04:58:28.09#ibcon#about to read 3, iclass 25, count 0 2006.286.04:58:28.11#ibcon#read 3, iclass 25, count 0 2006.286.04:58:28.11#ibcon#about to read 4, iclass 25, count 0 2006.286.04:58:28.11#ibcon#read 4, iclass 25, count 0 2006.286.04:58:28.11#ibcon#about to read 5, iclass 25, count 0 2006.286.04:58:28.11#ibcon#read 5, iclass 25, count 0 2006.286.04:58:28.11#ibcon#about to read 6, iclass 25, count 0 2006.286.04:58:28.11#ibcon#read 6, iclass 25, count 0 2006.286.04:58:28.11#ibcon#end of sib2, iclass 25, count 0 2006.286.04:58:28.11#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:58:28.11#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:58:28.11#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:58:28.11#ibcon#*before write, iclass 25, count 0 2006.286.04:58:28.11#ibcon#enter sib2, iclass 25, count 0 2006.286.04:58:28.11#ibcon#flushed, iclass 25, count 0 2006.286.04:58:28.11#ibcon#about to write, iclass 25, count 0 2006.286.04:58:28.11#ibcon#wrote, iclass 25, count 0 2006.286.04:58:28.11#ibcon#about to read 3, iclass 25, count 0 2006.286.04:58:28.15#ibcon#read 3, iclass 25, count 0 2006.286.04:58:28.15#ibcon#about to read 4, iclass 25, count 0 2006.286.04:58:28.15#ibcon#read 4, iclass 25, count 0 2006.286.04:58:28.15#ibcon#about to read 5, iclass 25, count 0 2006.286.04:58:28.15#ibcon#read 5, iclass 25, count 0 2006.286.04:58:28.15#ibcon#about to read 6, iclass 25, count 0 2006.286.04:58:28.15#ibcon#read 6, iclass 25, count 0 2006.286.04:58:28.15#ibcon#end of sib2, iclass 25, count 0 2006.286.04:58:28.15#ibcon#*after write, iclass 25, count 0 2006.286.04:58:28.15#ibcon#*before return 0, iclass 25, count 0 2006.286.04:58:28.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:58:28.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.04:58:28.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:58:28.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:58:28.15$vck44/vb=5,4 2006.286.04:58:28.15#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.04:58:28.15#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.04:58:28.15#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:28.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:58:28.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:58:28.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:58:28.21#ibcon#enter wrdev, iclass 27, count 2 2006.286.04:58:28.21#ibcon#first serial, iclass 27, count 2 2006.286.04:58:28.21#ibcon#enter sib2, iclass 27, count 2 2006.286.04:58:28.21#ibcon#flushed, iclass 27, count 2 2006.286.04:58:28.21#ibcon#about to write, iclass 27, count 2 2006.286.04:58:28.21#ibcon#wrote, iclass 27, count 2 2006.286.04:58:28.21#ibcon#about to read 3, iclass 27, count 2 2006.286.04:58:28.23#ibcon#read 3, iclass 27, count 2 2006.286.04:58:28.23#ibcon#about to read 4, iclass 27, count 2 2006.286.04:58:28.23#ibcon#read 4, iclass 27, count 2 2006.286.04:58:28.23#ibcon#about to read 5, iclass 27, count 2 2006.286.04:58:28.23#ibcon#read 5, iclass 27, count 2 2006.286.04:58:28.23#ibcon#about to read 6, iclass 27, count 2 2006.286.04:58:28.23#ibcon#read 6, iclass 27, count 2 2006.286.04:58:28.23#ibcon#end of sib2, iclass 27, count 2 2006.286.04:58:28.23#ibcon#*mode == 0, iclass 27, count 2 2006.286.04:58:28.23#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.04:58:28.23#ibcon#[27=AT05-04\r\n] 2006.286.04:58:28.23#ibcon#*before write, iclass 27, count 2 2006.286.04:58:28.23#ibcon#enter sib2, iclass 27, count 2 2006.286.04:58:28.23#ibcon#flushed, iclass 27, count 2 2006.286.04:58:28.23#ibcon#about to write, iclass 27, count 2 2006.286.04:58:28.23#ibcon#wrote, iclass 27, count 2 2006.286.04:58:28.23#ibcon#about to read 3, iclass 27, count 2 2006.286.04:58:28.26#ibcon#read 3, iclass 27, count 2 2006.286.04:58:28.26#ibcon#about to read 4, iclass 27, count 2 2006.286.04:58:28.26#ibcon#read 4, iclass 27, count 2 2006.286.04:58:28.26#ibcon#about to read 5, iclass 27, count 2 2006.286.04:58:28.26#ibcon#read 5, iclass 27, count 2 2006.286.04:58:28.26#ibcon#about to read 6, iclass 27, count 2 2006.286.04:58:28.26#ibcon#read 6, iclass 27, count 2 2006.286.04:58:28.26#ibcon#end of sib2, iclass 27, count 2 2006.286.04:58:28.26#ibcon#*after write, iclass 27, count 2 2006.286.04:58:28.26#ibcon#*before return 0, iclass 27, count 2 2006.286.04:58:28.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:58:28.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.04:58:28.26#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.04:58:28.26#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:28.26#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:58:28.38#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:58:28.38#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:58:28.38#ibcon#enter wrdev, iclass 27, count 0 2006.286.04:58:28.38#ibcon#first serial, iclass 27, count 0 2006.286.04:58:28.38#ibcon#enter sib2, iclass 27, count 0 2006.286.04:58:28.38#ibcon#flushed, iclass 27, count 0 2006.286.04:58:28.38#ibcon#about to write, iclass 27, count 0 2006.286.04:58:28.38#ibcon#wrote, iclass 27, count 0 2006.286.04:58:28.38#ibcon#about to read 3, iclass 27, count 0 2006.286.04:58:28.40#ibcon#read 3, iclass 27, count 0 2006.286.04:58:28.40#ibcon#about to read 4, iclass 27, count 0 2006.286.04:58:28.40#ibcon#read 4, iclass 27, count 0 2006.286.04:58:28.40#ibcon#about to read 5, iclass 27, count 0 2006.286.04:58:28.40#ibcon#read 5, iclass 27, count 0 2006.286.04:58:28.40#ibcon#about to read 6, iclass 27, count 0 2006.286.04:58:28.40#ibcon#read 6, iclass 27, count 0 2006.286.04:58:28.40#ibcon#end of sib2, iclass 27, count 0 2006.286.04:58:28.40#ibcon#*mode == 0, iclass 27, count 0 2006.286.04:58:28.40#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.04:58:28.40#ibcon#[27=USB\r\n] 2006.286.04:58:28.40#ibcon#*before write, iclass 27, count 0 2006.286.04:58:28.40#ibcon#enter sib2, iclass 27, count 0 2006.286.04:58:28.40#ibcon#flushed, iclass 27, count 0 2006.286.04:58:28.40#ibcon#about to write, iclass 27, count 0 2006.286.04:58:28.40#ibcon#wrote, iclass 27, count 0 2006.286.04:58:28.40#ibcon#about to read 3, iclass 27, count 0 2006.286.04:58:28.43#ibcon#read 3, iclass 27, count 0 2006.286.04:58:28.43#ibcon#about to read 4, iclass 27, count 0 2006.286.04:58:28.43#ibcon#read 4, iclass 27, count 0 2006.286.04:58:28.43#ibcon#about to read 5, iclass 27, count 0 2006.286.04:58:28.43#ibcon#read 5, iclass 27, count 0 2006.286.04:58:28.43#ibcon#about to read 6, iclass 27, count 0 2006.286.04:58:28.43#ibcon#read 6, iclass 27, count 0 2006.286.04:58:28.43#ibcon#end of sib2, iclass 27, count 0 2006.286.04:58:28.43#ibcon#*after write, iclass 27, count 0 2006.286.04:58:28.43#ibcon#*before return 0, iclass 27, count 0 2006.286.04:58:28.43#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:58:28.43#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.04:58:28.43#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.04:58:28.43#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.04:58:28.43$vck44/vblo=6,719.99 2006.286.04:58:28.43#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.04:58:28.43#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.04:58:28.43#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:28.43#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:58:28.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:58:28.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:58:28.43#ibcon#enter wrdev, iclass 29, count 0 2006.286.04:58:28.43#ibcon#first serial, iclass 29, count 0 2006.286.04:58:28.43#ibcon#enter sib2, iclass 29, count 0 2006.286.04:58:28.43#ibcon#flushed, iclass 29, count 0 2006.286.04:58:28.43#ibcon#about to write, iclass 29, count 0 2006.286.04:58:28.43#ibcon#wrote, iclass 29, count 0 2006.286.04:58:28.43#ibcon#about to read 3, iclass 29, count 0 2006.286.04:58:28.45#ibcon#read 3, iclass 29, count 0 2006.286.04:58:28.45#ibcon#about to read 4, iclass 29, count 0 2006.286.04:58:28.45#ibcon#read 4, iclass 29, count 0 2006.286.04:58:28.45#ibcon#about to read 5, iclass 29, count 0 2006.286.04:58:28.45#ibcon#read 5, iclass 29, count 0 2006.286.04:58:28.45#ibcon#about to read 6, iclass 29, count 0 2006.286.04:58:28.45#ibcon#read 6, iclass 29, count 0 2006.286.04:58:28.45#ibcon#end of sib2, iclass 29, count 0 2006.286.04:58:28.45#ibcon#*mode == 0, iclass 29, count 0 2006.286.04:58:28.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.04:58:28.45#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:58:28.45#ibcon#*before write, iclass 29, count 0 2006.286.04:58:28.45#ibcon#enter sib2, iclass 29, count 0 2006.286.04:58:28.45#ibcon#flushed, iclass 29, count 0 2006.286.04:58:28.45#ibcon#about to write, iclass 29, count 0 2006.286.04:58:28.45#ibcon#wrote, iclass 29, count 0 2006.286.04:58:28.45#ibcon#about to read 3, iclass 29, count 0 2006.286.04:58:28.49#ibcon#read 3, iclass 29, count 0 2006.286.04:58:28.49#ibcon#about to read 4, iclass 29, count 0 2006.286.04:58:28.49#ibcon#read 4, iclass 29, count 0 2006.286.04:58:28.49#ibcon#about to read 5, iclass 29, count 0 2006.286.04:58:28.49#ibcon#read 5, iclass 29, count 0 2006.286.04:58:28.49#ibcon#about to read 6, iclass 29, count 0 2006.286.04:58:28.49#ibcon#read 6, iclass 29, count 0 2006.286.04:58:28.49#ibcon#end of sib2, iclass 29, count 0 2006.286.04:58:28.49#ibcon#*after write, iclass 29, count 0 2006.286.04:58:28.49#ibcon#*before return 0, iclass 29, count 0 2006.286.04:58:28.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:58:28.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.04:58:28.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.04:58:28.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.04:58:28.49$vck44/vb=6,3 2006.286.04:58:28.49#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.04:58:28.49#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.04:58:28.49#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:28.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:58:28.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:58:28.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:58:28.55#ibcon#enter wrdev, iclass 31, count 2 2006.286.04:58:28.55#ibcon#first serial, iclass 31, count 2 2006.286.04:58:28.55#ibcon#enter sib2, iclass 31, count 2 2006.286.04:58:28.55#ibcon#flushed, iclass 31, count 2 2006.286.04:58:28.55#ibcon#about to write, iclass 31, count 2 2006.286.04:58:28.55#ibcon#wrote, iclass 31, count 2 2006.286.04:58:28.55#ibcon#about to read 3, iclass 31, count 2 2006.286.04:58:28.57#ibcon#read 3, iclass 31, count 2 2006.286.04:58:28.57#ibcon#about to read 4, iclass 31, count 2 2006.286.04:58:28.57#ibcon#read 4, iclass 31, count 2 2006.286.04:58:28.57#ibcon#about to read 5, iclass 31, count 2 2006.286.04:58:28.57#ibcon#read 5, iclass 31, count 2 2006.286.04:58:28.57#ibcon#about to read 6, iclass 31, count 2 2006.286.04:58:28.57#ibcon#read 6, iclass 31, count 2 2006.286.04:58:28.57#ibcon#end of sib2, iclass 31, count 2 2006.286.04:58:28.57#ibcon#*mode == 0, iclass 31, count 2 2006.286.04:58:28.57#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.04:58:28.57#ibcon#[27=AT06-03\r\n] 2006.286.04:58:28.57#ibcon#*before write, iclass 31, count 2 2006.286.04:58:28.57#ibcon#enter sib2, iclass 31, count 2 2006.286.04:58:28.57#ibcon#flushed, iclass 31, count 2 2006.286.04:58:28.57#ibcon#about to write, iclass 31, count 2 2006.286.04:58:28.57#ibcon#wrote, iclass 31, count 2 2006.286.04:58:28.57#ibcon#about to read 3, iclass 31, count 2 2006.286.04:58:28.60#ibcon#read 3, iclass 31, count 2 2006.286.04:58:28.60#ibcon#about to read 4, iclass 31, count 2 2006.286.04:58:28.60#ibcon#read 4, iclass 31, count 2 2006.286.04:58:28.60#ibcon#about to read 5, iclass 31, count 2 2006.286.04:58:28.60#ibcon#read 5, iclass 31, count 2 2006.286.04:58:28.60#ibcon#about to read 6, iclass 31, count 2 2006.286.04:58:28.60#ibcon#read 6, iclass 31, count 2 2006.286.04:58:28.60#ibcon#end of sib2, iclass 31, count 2 2006.286.04:58:28.60#ibcon#*after write, iclass 31, count 2 2006.286.04:58:28.60#ibcon#*before return 0, iclass 31, count 2 2006.286.04:58:28.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:58:28.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.04:58:28.60#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.04:58:28.60#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:28.60#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:58:28.72#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:58:28.72#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:58:28.72#ibcon#enter wrdev, iclass 31, count 0 2006.286.04:58:28.72#ibcon#first serial, iclass 31, count 0 2006.286.04:58:28.72#ibcon#enter sib2, iclass 31, count 0 2006.286.04:58:28.72#ibcon#flushed, iclass 31, count 0 2006.286.04:58:28.72#ibcon#about to write, iclass 31, count 0 2006.286.04:58:28.72#ibcon#wrote, iclass 31, count 0 2006.286.04:58:28.72#ibcon#about to read 3, iclass 31, count 0 2006.286.04:58:28.74#ibcon#read 3, iclass 31, count 0 2006.286.04:58:28.74#ibcon#about to read 4, iclass 31, count 0 2006.286.04:58:28.74#ibcon#read 4, iclass 31, count 0 2006.286.04:58:28.74#ibcon#about to read 5, iclass 31, count 0 2006.286.04:58:28.74#ibcon#read 5, iclass 31, count 0 2006.286.04:58:28.74#ibcon#about to read 6, iclass 31, count 0 2006.286.04:58:28.74#ibcon#read 6, iclass 31, count 0 2006.286.04:58:28.74#ibcon#end of sib2, iclass 31, count 0 2006.286.04:58:28.74#ibcon#*mode == 0, iclass 31, count 0 2006.286.04:58:28.74#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.04:58:28.74#ibcon#[27=USB\r\n] 2006.286.04:58:28.74#ibcon#*before write, iclass 31, count 0 2006.286.04:58:28.74#ibcon#enter sib2, iclass 31, count 0 2006.286.04:58:28.74#ibcon#flushed, iclass 31, count 0 2006.286.04:58:28.74#ibcon#about to write, iclass 31, count 0 2006.286.04:58:28.74#ibcon#wrote, iclass 31, count 0 2006.286.04:58:28.74#ibcon#about to read 3, iclass 31, count 0 2006.286.04:58:28.77#ibcon#read 3, iclass 31, count 0 2006.286.04:58:28.77#ibcon#about to read 4, iclass 31, count 0 2006.286.04:58:28.77#ibcon#read 4, iclass 31, count 0 2006.286.04:58:28.77#ibcon#about to read 5, iclass 31, count 0 2006.286.04:58:28.77#ibcon#read 5, iclass 31, count 0 2006.286.04:58:28.77#ibcon#about to read 6, iclass 31, count 0 2006.286.04:58:28.77#ibcon#read 6, iclass 31, count 0 2006.286.04:58:28.77#ibcon#end of sib2, iclass 31, count 0 2006.286.04:58:28.77#ibcon#*after write, iclass 31, count 0 2006.286.04:58:28.77#ibcon#*before return 0, iclass 31, count 0 2006.286.04:58:28.77#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:58:28.77#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.04:58:28.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.04:58:28.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.04:58:28.77$vck44/vblo=7,734.99 2006.286.04:58:28.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.04:58:28.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.04:58:28.87#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:28.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:58:28.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:58:28.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:58:28.87#ibcon#enter wrdev, iclass 33, count 0 2006.286.04:58:28.87#ibcon#first serial, iclass 33, count 0 2006.286.04:58:28.87#ibcon#enter sib2, iclass 33, count 0 2006.286.04:58:28.87#ibcon#flushed, iclass 33, count 0 2006.286.04:58:28.87#ibcon#about to write, iclass 33, count 0 2006.286.04:58:28.87#ibcon#wrote, iclass 33, count 0 2006.286.04:58:28.87#ibcon#about to read 3, iclass 33, count 0 2006.286.04:58:28.89#ibcon#read 3, iclass 33, count 0 2006.286.04:58:28.89#ibcon#about to read 4, iclass 33, count 0 2006.286.04:58:28.89#ibcon#read 4, iclass 33, count 0 2006.286.04:58:28.89#ibcon#about to read 5, iclass 33, count 0 2006.286.04:58:28.89#ibcon#read 5, iclass 33, count 0 2006.286.04:58:28.89#ibcon#about to read 6, iclass 33, count 0 2006.286.04:58:28.89#ibcon#read 6, iclass 33, count 0 2006.286.04:58:28.89#ibcon#end of sib2, iclass 33, count 0 2006.286.04:58:28.89#ibcon#*mode == 0, iclass 33, count 0 2006.286.04:58:28.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.04:58:28.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:58:28.89#ibcon#*before write, iclass 33, count 0 2006.286.04:58:28.89#ibcon#enter sib2, iclass 33, count 0 2006.286.04:58:28.89#ibcon#flushed, iclass 33, count 0 2006.286.04:58:28.89#ibcon#about to write, iclass 33, count 0 2006.286.04:58:28.89#ibcon#wrote, iclass 33, count 0 2006.286.04:58:28.89#ibcon#about to read 3, iclass 33, count 0 2006.286.04:58:28.93#ibcon#read 3, iclass 33, count 0 2006.286.04:58:28.93#ibcon#about to read 4, iclass 33, count 0 2006.286.04:58:28.93#ibcon#read 4, iclass 33, count 0 2006.286.04:58:28.93#ibcon#about to read 5, iclass 33, count 0 2006.286.04:58:28.93#ibcon#read 5, iclass 33, count 0 2006.286.04:58:28.93#ibcon#about to read 6, iclass 33, count 0 2006.286.04:58:28.93#ibcon#read 6, iclass 33, count 0 2006.286.04:58:28.93#ibcon#end of sib2, iclass 33, count 0 2006.286.04:58:28.93#ibcon#*after write, iclass 33, count 0 2006.286.04:58:28.93#ibcon#*before return 0, iclass 33, count 0 2006.286.04:58:28.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:58:28.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.04:58:28.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.04:58:28.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.04:58:28.93$vck44/vb=7,4 2006.286.04:58:28.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.04:58:28.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.04:58:28.93#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:28.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:58:28.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:58:28.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:58:28.93#ibcon#enter wrdev, iclass 35, count 2 2006.286.04:58:28.93#ibcon#first serial, iclass 35, count 2 2006.286.04:58:28.93#ibcon#enter sib2, iclass 35, count 2 2006.286.04:58:28.93#ibcon#flushed, iclass 35, count 2 2006.286.04:58:28.93#ibcon#about to write, iclass 35, count 2 2006.286.04:58:28.93#ibcon#wrote, iclass 35, count 2 2006.286.04:58:28.93#ibcon#about to read 3, iclass 35, count 2 2006.286.04:58:28.95#ibcon#read 3, iclass 35, count 2 2006.286.04:58:28.95#ibcon#about to read 4, iclass 35, count 2 2006.286.04:58:28.95#ibcon#read 4, iclass 35, count 2 2006.286.04:58:28.95#ibcon#about to read 5, iclass 35, count 2 2006.286.04:58:28.95#ibcon#read 5, iclass 35, count 2 2006.286.04:58:28.95#ibcon#about to read 6, iclass 35, count 2 2006.286.04:58:28.95#ibcon#read 6, iclass 35, count 2 2006.286.04:58:28.95#ibcon#end of sib2, iclass 35, count 2 2006.286.04:58:28.95#ibcon#*mode == 0, iclass 35, count 2 2006.286.04:58:28.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.04:58:28.95#ibcon#[27=AT07-04\r\n] 2006.286.04:58:28.95#ibcon#*before write, iclass 35, count 2 2006.286.04:58:28.95#ibcon#enter sib2, iclass 35, count 2 2006.286.04:58:28.95#ibcon#flushed, iclass 35, count 2 2006.286.04:58:28.95#ibcon#about to write, iclass 35, count 2 2006.286.04:58:28.95#ibcon#wrote, iclass 35, count 2 2006.286.04:58:28.95#ibcon#about to read 3, iclass 35, count 2 2006.286.04:58:28.98#ibcon#read 3, iclass 35, count 2 2006.286.04:58:28.98#ibcon#about to read 4, iclass 35, count 2 2006.286.04:58:28.98#ibcon#read 4, iclass 35, count 2 2006.286.04:58:28.98#ibcon#about to read 5, iclass 35, count 2 2006.286.04:58:28.98#ibcon#read 5, iclass 35, count 2 2006.286.04:58:28.98#ibcon#about to read 6, iclass 35, count 2 2006.286.04:58:28.98#ibcon#read 6, iclass 35, count 2 2006.286.04:58:28.98#ibcon#end of sib2, iclass 35, count 2 2006.286.04:58:28.98#ibcon#*after write, iclass 35, count 2 2006.286.04:58:28.98#ibcon#*before return 0, iclass 35, count 2 2006.286.04:58:28.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:58:28.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.04:58:28.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.04:58:28.98#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:28.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:58:29.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:58:29.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:58:29.10#ibcon#enter wrdev, iclass 35, count 0 2006.286.04:58:29.10#ibcon#first serial, iclass 35, count 0 2006.286.04:58:29.10#ibcon#enter sib2, iclass 35, count 0 2006.286.04:58:29.10#ibcon#flushed, iclass 35, count 0 2006.286.04:58:29.10#ibcon#about to write, iclass 35, count 0 2006.286.04:58:29.10#ibcon#wrote, iclass 35, count 0 2006.286.04:58:29.10#ibcon#about to read 3, iclass 35, count 0 2006.286.04:58:29.12#ibcon#read 3, iclass 35, count 0 2006.286.04:58:29.12#ibcon#about to read 4, iclass 35, count 0 2006.286.04:58:29.12#ibcon#read 4, iclass 35, count 0 2006.286.04:58:29.12#ibcon#about to read 5, iclass 35, count 0 2006.286.04:58:29.12#ibcon#read 5, iclass 35, count 0 2006.286.04:58:29.12#ibcon#about to read 6, iclass 35, count 0 2006.286.04:58:29.12#ibcon#read 6, iclass 35, count 0 2006.286.04:58:29.12#ibcon#end of sib2, iclass 35, count 0 2006.286.04:58:29.12#ibcon#*mode == 0, iclass 35, count 0 2006.286.04:58:29.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.04:58:29.12#ibcon#[27=USB\r\n] 2006.286.04:58:29.12#ibcon#*before write, iclass 35, count 0 2006.286.04:58:29.12#ibcon#enter sib2, iclass 35, count 0 2006.286.04:58:29.12#ibcon#flushed, iclass 35, count 0 2006.286.04:58:29.12#ibcon#about to write, iclass 35, count 0 2006.286.04:58:29.12#ibcon#wrote, iclass 35, count 0 2006.286.04:58:29.12#ibcon#about to read 3, iclass 35, count 0 2006.286.04:58:29.13#trakl#Source acquired 2006.286.04:58:29.13#flagr#flagr/antenna,acquired 2006.286.04:58:29.15#ibcon#read 3, iclass 35, count 0 2006.286.04:58:29.15#ibcon#about to read 4, iclass 35, count 0 2006.286.04:58:29.15#ibcon#read 4, iclass 35, count 0 2006.286.04:58:29.15#ibcon#about to read 5, iclass 35, count 0 2006.286.04:58:29.15#ibcon#read 5, iclass 35, count 0 2006.286.04:58:29.15#ibcon#about to read 6, iclass 35, count 0 2006.286.04:58:29.15#ibcon#read 6, iclass 35, count 0 2006.286.04:58:29.15#ibcon#end of sib2, iclass 35, count 0 2006.286.04:58:29.15#ibcon#*after write, iclass 35, count 0 2006.286.04:58:29.15#ibcon#*before return 0, iclass 35, count 0 2006.286.04:58:29.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:58:29.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.04:58:29.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.04:58:29.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.04:58:29.15$vck44/vblo=8,744.99 2006.286.04:58:29.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.04:58:29.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.04:58:29.15#ibcon#ireg 17 cls_cnt 0 2006.286.04:58:29.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:58:29.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:58:29.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:58:29.15#ibcon#enter wrdev, iclass 37, count 0 2006.286.04:58:29.15#ibcon#first serial, iclass 37, count 0 2006.286.04:58:29.15#ibcon#enter sib2, iclass 37, count 0 2006.286.04:58:29.15#ibcon#flushed, iclass 37, count 0 2006.286.04:58:29.15#ibcon#about to write, iclass 37, count 0 2006.286.04:58:29.15#ibcon#wrote, iclass 37, count 0 2006.286.04:58:29.15#ibcon#about to read 3, iclass 37, count 0 2006.286.04:58:29.17#ibcon#read 3, iclass 37, count 0 2006.286.04:58:29.17#ibcon#about to read 4, iclass 37, count 0 2006.286.04:58:29.17#ibcon#read 4, iclass 37, count 0 2006.286.04:58:29.17#ibcon#about to read 5, iclass 37, count 0 2006.286.04:58:29.17#ibcon#read 5, iclass 37, count 0 2006.286.04:58:29.17#ibcon#about to read 6, iclass 37, count 0 2006.286.04:58:29.17#ibcon#read 6, iclass 37, count 0 2006.286.04:58:29.17#ibcon#end of sib2, iclass 37, count 0 2006.286.04:58:29.17#ibcon#*mode == 0, iclass 37, count 0 2006.286.04:58:29.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.04:58:29.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:58:29.17#ibcon#*before write, iclass 37, count 0 2006.286.04:58:29.17#ibcon#enter sib2, iclass 37, count 0 2006.286.04:58:29.17#ibcon#flushed, iclass 37, count 0 2006.286.04:58:29.17#ibcon#about to write, iclass 37, count 0 2006.286.04:58:29.17#ibcon#wrote, iclass 37, count 0 2006.286.04:58:29.17#ibcon#about to read 3, iclass 37, count 0 2006.286.04:58:29.21#ibcon#read 3, iclass 37, count 0 2006.286.04:58:29.21#ibcon#about to read 4, iclass 37, count 0 2006.286.04:58:29.21#ibcon#read 4, iclass 37, count 0 2006.286.04:58:29.21#ibcon#about to read 5, iclass 37, count 0 2006.286.04:58:29.21#ibcon#read 5, iclass 37, count 0 2006.286.04:58:29.21#ibcon#about to read 6, iclass 37, count 0 2006.286.04:58:29.21#ibcon#read 6, iclass 37, count 0 2006.286.04:58:29.21#ibcon#end of sib2, iclass 37, count 0 2006.286.04:58:29.21#ibcon#*after write, iclass 37, count 0 2006.286.04:58:29.21#ibcon#*before return 0, iclass 37, count 0 2006.286.04:58:29.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:58:29.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.04:58:29.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.04:58:29.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.04:58:29.21$vck44/vb=8,4 2006.286.04:58:29.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.04:58:29.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.04:58:29.21#ibcon#ireg 11 cls_cnt 2 2006.286.04:58:29.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:58:29.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:58:29.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:58:29.27#ibcon#enter wrdev, iclass 39, count 2 2006.286.04:58:29.27#ibcon#first serial, iclass 39, count 2 2006.286.04:58:29.27#ibcon#enter sib2, iclass 39, count 2 2006.286.04:58:29.27#ibcon#flushed, iclass 39, count 2 2006.286.04:58:29.27#ibcon#about to write, iclass 39, count 2 2006.286.04:58:29.27#ibcon#wrote, iclass 39, count 2 2006.286.04:58:29.27#ibcon#about to read 3, iclass 39, count 2 2006.286.04:58:29.29#ibcon#read 3, iclass 39, count 2 2006.286.04:58:29.29#ibcon#about to read 4, iclass 39, count 2 2006.286.04:58:29.29#ibcon#read 4, iclass 39, count 2 2006.286.04:58:29.29#ibcon#about to read 5, iclass 39, count 2 2006.286.04:58:29.29#ibcon#read 5, iclass 39, count 2 2006.286.04:58:29.29#ibcon#about to read 6, iclass 39, count 2 2006.286.04:58:29.29#ibcon#read 6, iclass 39, count 2 2006.286.04:58:29.29#ibcon#end of sib2, iclass 39, count 2 2006.286.04:58:29.29#ibcon#*mode == 0, iclass 39, count 2 2006.286.04:58:29.29#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.04:58:29.29#ibcon#[27=AT08-04\r\n] 2006.286.04:58:29.29#ibcon#*before write, iclass 39, count 2 2006.286.04:58:29.29#ibcon#enter sib2, iclass 39, count 2 2006.286.04:58:29.29#ibcon#flushed, iclass 39, count 2 2006.286.04:58:29.29#ibcon#about to write, iclass 39, count 2 2006.286.04:58:29.29#ibcon#wrote, iclass 39, count 2 2006.286.04:58:29.29#ibcon#about to read 3, iclass 39, count 2 2006.286.04:58:29.32#ibcon#read 3, iclass 39, count 2 2006.286.04:58:29.32#ibcon#about to read 4, iclass 39, count 2 2006.286.04:58:29.32#ibcon#read 4, iclass 39, count 2 2006.286.04:58:29.32#ibcon#about to read 5, iclass 39, count 2 2006.286.04:58:29.32#ibcon#read 5, iclass 39, count 2 2006.286.04:58:29.32#ibcon#about to read 6, iclass 39, count 2 2006.286.04:58:29.32#ibcon#read 6, iclass 39, count 2 2006.286.04:58:29.32#ibcon#end of sib2, iclass 39, count 2 2006.286.04:58:29.32#ibcon#*after write, iclass 39, count 2 2006.286.04:58:29.32#ibcon#*before return 0, iclass 39, count 2 2006.286.04:58:29.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:58:29.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.04:58:29.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.04:58:29.32#ibcon#ireg 7 cls_cnt 0 2006.286.04:58:29.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:58:29.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:58:29.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:58:29.44#ibcon#enter wrdev, iclass 39, count 0 2006.286.04:58:29.44#ibcon#first serial, iclass 39, count 0 2006.286.04:58:29.44#ibcon#enter sib2, iclass 39, count 0 2006.286.04:58:29.44#ibcon#flushed, iclass 39, count 0 2006.286.04:58:29.44#ibcon#about to write, iclass 39, count 0 2006.286.04:58:29.44#ibcon#wrote, iclass 39, count 0 2006.286.04:58:29.44#ibcon#about to read 3, iclass 39, count 0 2006.286.04:58:29.46#ibcon#read 3, iclass 39, count 0 2006.286.04:58:29.46#ibcon#about to read 4, iclass 39, count 0 2006.286.04:58:29.46#ibcon#read 4, iclass 39, count 0 2006.286.04:58:29.46#ibcon#about to read 5, iclass 39, count 0 2006.286.04:58:29.46#ibcon#read 5, iclass 39, count 0 2006.286.04:58:29.46#ibcon#about to read 6, iclass 39, count 0 2006.286.04:58:29.46#ibcon#read 6, iclass 39, count 0 2006.286.04:58:29.46#ibcon#end of sib2, iclass 39, count 0 2006.286.04:58:29.46#ibcon#*mode == 0, iclass 39, count 0 2006.286.04:58:29.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.04:58:29.46#ibcon#[27=USB\r\n] 2006.286.04:58:29.46#ibcon#*before write, iclass 39, count 0 2006.286.04:58:29.46#ibcon#enter sib2, iclass 39, count 0 2006.286.04:58:29.46#ibcon#flushed, iclass 39, count 0 2006.286.04:58:29.46#ibcon#about to write, iclass 39, count 0 2006.286.04:58:29.46#ibcon#wrote, iclass 39, count 0 2006.286.04:58:29.46#ibcon#about to read 3, iclass 39, count 0 2006.286.04:58:29.49#ibcon#read 3, iclass 39, count 0 2006.286.04:58:29.49#ibcon#about to read 4, iclass 39, count 0 2006.286.04:58:29.49#ibcon#read 4, iclass 39, count 0 2006.286.04:58:29.49#ibcon#about to read 5, iclass 39, count 0 2006.286.04:58:29.49#ibcon#read 5, iclass 39, count 0 2006.286.04:58:29.49#ibcon#about to read 6, iclass 39, count 0 2006.286.04:58:29.49#ibcon#read 6, iclass 39, count 0 2006.286.04:58:29.49#ibcon#end of sib2, iclass 39, count 0 2006.286.04:58:29.49#ibcon#*after write, iclass 39, count 0 2006.286.04:58:29.49#ibcon#*before return 0, iclass 39, count 0 2006.286.04:58:29.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:58:29.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.04:58:29.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.04:58:29.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.04:58:29.49$vck44/vabw=wide 2006.286.04:58:29.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.04:58:29.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.04:58:29.49#ibcon#ireg 8 cls_cnt 0 2006.286.04:58:29.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:58:29.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:58:29.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:58:29.49#ibcon#enter wrdev, iclass 3, count 0 2006.286.04:58:29.49#ibcon#first serial, iclass 3, count 0 2006.286.04:58:29.49#ibcon#enter sib2, iclass 3, count 0 2006.286.04:58:29.49#ibcon#flushed, iclass 3, count 0 2006.286.04:58:29.49#ibcon#about to write, iclass 3, count 0 2006.286.04:58:29.49#ibcon#wrote, iclass 3, count 0 2006.286.04:58:29.49#ibcon#about to read 3, iclass 3, count 0 2006.286.04:58:29.51#ibcon#read 3, iclass 3, count 0 2006.286.04:58:29.51#ibcon#about to read 4, iclass 3, count 0 2006.286.04:58:29.51#ibcon#read 4, iclass 3, count 0 2006.286.04:58:29.51#ibcon#about to read 5, iclass 3, count 0 2006.286.04:58:29.51#ibcon#read 5, iclass 3, count 0 2006.286.04:58:29.51#ibcon#about to read 6, iclass 3, count 0 2006.286.04:58:29.51#ibcon#read 6, iclass 3, count 0 2006.286.04:58:29.51#ibcon#end of sib2, iclass 3, count 0 2006.286.04:58:29.51#ibcon#*mode == 0, iclass 3, count 0 2006.286.04:58:29.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.04:58:29.51#ibcon#[25=BW32\r\n] 2006.286.04:58:29.51#ibcon#*before write, iclass 3, count 0 2006.286.04:58:29.51#ibcon#enter sib2, iclass 3, count 0 2006.286.04:58:29.51#ibcon#flushed, iclass 3, count 0 2006.286.04:58:29.51#ibcon#about to write, iclass 3, count 0 2006.286.04:58:29.51#ibcon#wrote, iclass 3, count 0 2006.286.04:58:29.51#ibcon#about to read 3, iclass 3, count 0 2006.286.04:58:29.54#ibcon#read 3, iclass 3, count 0 2006.286.04:58:29.54#ibcon#about to read 4, iclass 3, count 0 2006.286.04:58:29.54#ibcon#read 4, iclass 3, count 0 2006.286.04:58:29.54#ibcon#about to read 5, iclass 3, count 0 2006.286.04:58:29.54#ibcon#read 5, iclass 3, count 0 2006.286.04:58:29.54#ibcon#about to read 6, iclass 3, count 0 2006.286.04:58:29.54#ibcon#read 6, iclass 3, count 0 2006.286.04:58:29.54#ibcon#end of sib2, iclass 3, count 0 2006.286.04:58:29.54#ibcon#*after write, iclass 3, count 0 2006.286.04:58:29.54#ibcon#*before return 0, iclass 3, count 0 2006.286.04:58:29.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:58:29.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.04:58:29.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.04:58:29.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.04:58:29.54$vck44/vbbw=wide 2006.286.04:58:29.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.04:58:29.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.04:58:29.54#ibcon#ireg 8 cls_cnt 0 2006.286.04:58:29.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:58:29.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:58:29.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:58:29.61#ibcon#enter wrdev, iclass 5, count 0 2006.286.04:58:29.61#ibcon#first serial, iclass 5, count 0 2006.286.04:58:29.61#ibcon#enter sib2, iclass 5, count 0 2006.286.04:58:29.61#ibcon#flushed, iclass 5, count 0 2006.286.04:58:29.61#ibcon#about to write, iclass 5, count 0 2006.286.04:58:29.61#ibcon#wrote, iclass 5, count 0 2006.286.04:58:29.61#ibcon#about to read 3, iclass 5, count 0 2006.286.04:58:29.63#ibcon#read 3, iclass 5, count 0 2006.286.04:58:29.63#ibcon#about to read 4, iclass 5, count 0 2006.286.04:58:29.63#ibcon#read 4, iclass 5, count 0 2006.286.04:58:29.63#ibcon#about to read 5, iclass 5, count 0 2006.286.04:58:29.63#ibcon#read 5, iclass 5, count 0 2006.286.04:58:29.63#ibcon#about to read 6, iclass 5, count 0 2006.286.04:58:29.63#ibcon#read 6, iclass 5, count 0 2006.286.04:58:29.63#ibcon#end of sib2, iclass 5, count 0 2006.286.04:58:29.63#ibcon#*mode == 0, iclass 5, count 0 2006.286.04:58:29.63#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.04:58:29.63#ibcon#[27=BW32\r\n] 2006.286.04:58:29.63#ibcon#*before write, iclass 5, count 0 2006.286.04:58:29.63#ibcon#enter sib2, iclass 5, count 0 2006.286.04:58:29.63#ibcon#flushed, iclass 5, count 0 2006.286.04:58:29.63#ibcon#about to write, iclass 5, count 0 2006.286.04:58:29.63#ibcon#wrote, iclass 5, count 0 2006.286.04:58:29.63#ibcon#about to read 3, iclass 5, count 0 2006.286.04:58:29.66#ibcon#read 3, iclass 5, count 0 2006.286.04:58:29.66#ibcon#about to read 4, iclass 5, count 0 2006.286.04:58:29.66#ibcon#read 4, iclass 5, count 0 2006.286.04:58:29.66#ibcon#about to read 5, iclass 5, count 0 2006.286.04:58:29.66#ibcon#read 5, iclass 5, count 0 2006.286.04:58:29.66#ibcon#about to read 6, iclass 5, count 0 2006.286.04:58:29.66#ibcon#read 6, iclass 5, count 0 2006.286.04:58:29.66#ibcon#end of sib2, iclass 5, count 0 2006.286.04:58:29.66#ibcon#*after write, iclass 5, count 0 2006.286.04:58:29.66#ibcon#*before return 0, iclass 5, count 0 2006.286.04:58:29.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:58:29.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.04:58:29.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.04:58:29.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.04:58:29.66$setupk4/ifdk4 2006.286.04:58:29.66$ifdk4/lo= 2006.286.04:58:29.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:58:29.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:58:29.88$ifdk4/patch= 2006.286.04:58:29.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:58:29.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:58:29.88$setupk4/!*+20s 2006.286.04:58:30.41#abcon#<5=/04 3.2 7.5 22.09 751014.9\r\n> 2006.286.04:58:30.43#abcon#{5=INTERFACE CLEAR} 2006.286.04:58:30.49#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:58:40.58#abcon#<5=/04 3.3 7.5 22.09 741014.9\r\n> 2006.286.04:58:40.60#abcon#{5=INTERFACE CLEAR} 2006.286.04:58:40.66#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:58:43.32$setupk4/"tpicd 2006.286.04:58:43.32$setupk4/echo=off 2006.286.04:58:43.32$setupk4/xlog=off 2006.286.04:58:43.32:!2006.286.04:58:48 2006.286.04:58:44.14#trakl#Off source 2006.286.04:58:44.14?ERROR st -7 Antenna off-source! 2006.286.04:58:44.14#trakl#az 88.592 el 7.714 azerr*cos(el) 0.0182 elerr -0.0010 2006.286.04:58:44.14#flagr#flagr/antenna,off-source 2006.286.04:58:48.00:preob 2006.286.04:58:48.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.286.04:58:48.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.286.04:58:48.14/onsource/SLEWING 2006.286.04:58:48.14:!2006.286.04:58:58 2006.286.04:58:50.14#trakl#Source re-acquired 2006.286.04:58:52.14#flagr#flagr/antenna,re-acquired 2006.286.04:58:58.00:"tape 2006.286.04:58:58.00:"st=record 2006.286.04:58:58.00:data_valid=on 2006.286.04:58:58.00:midob 2006.286.04:58:59.14/onsource/TRACKING 2006.286.04:58:59.14/wx/22.09,1014.9,76 2006.286.04:58:59.28/cable/+6.4930E-03 2006.286.04:59:00.37/va/01,07,usb,yes,39,43 2006.286.04:59:00.37/va/02,06,usb,yes,40,40 2006.286.04:59:00.37/va/03,07,usb,yes,39,41 2006.286.04:59:00.37/va/04,06,usb,yes,41,43 2006.286.04:59:00.37/va/05,03,usb,yes,40,41 2006.286.04:59:00.37/va/06,04,usb,yes,37,36 2006.286.04:59:00.37/va/07,04,usb,yes,37,38 2006.286.04:59:00.37/va/08,03,usb,yes,38,46 2006.286.04:59:00.60/valo/01,524.99,yes,locked 2006.286.04:59:00.60/valo/02,534.99,yes,locked 2006.286.04:59:00.60/valo/03,564.99,yes,locked 2006.286.04:59:00.60/valo/04,624.99,yes,locked 2006.286.04:59:00.60/valo/05,734.99,yes,locked 2006.286.04:59:00.60/valo/06,814.99,yes,locked 2006.286.04:59:00.60/valo/07,864.99,yes,locked 2006.286.04:59:00.60/valo/08,884.99,yes,locked 2006.286.04:59:01.69/vb/01,04,usb,yes,34,32 2006.286.04:59:01.69/vb/02,05,usb,yes,32,32 2006.286.04:59:01.69/vb/03,04,usb,yes,33,37 2006.286.04:59:01.69/vb/04,05,usb,yes,33,32 2006.286.04:59:01.69/vb/05,04,usb,yes,30,33 2006.286.04:59:01.69/vb/06,03,usb,yes,43,38 2006.286.04:59:01.69/vb/07,04,usb,yes,35,35 2006.286.04:59:01.69/vb/08,04,usb,yes,31,35 2006.286.04:59:01.92/vblo/01,629.99,yes,locked 2006.286.04:59:01.92/vblo/02,634.99,yes,locked 2006.286.04:59:01.92/vblo/03,649.99,yes,locked 2006.286.04:59:01.92/vblo/04,679.99,yes,locked 2006.286.04:59:01.92/vblo/05,709.99,yes,locked 2006.286.04:59:01.92/vblo/06,719.99,yes,locked 2006.286.04:59:01.92/vblo/07,734.99,yes,locked 2006.286.04:59:01.92/vblo/08,744.99,yes,locked 2006.286.04:59:02.07/vabw/8 2006.286.04:59:02.22/vbbw/8 2006.286.04:59:02.31/xfe/off,on,12.2 2006.286.04:59:02.68/ifatt/23,28,28,28 2006.286.04:59:03.08/fmout-gps/S +2.40E-07 2006.286.04:59:03.10:!2006.286.04:59:38 2006.286.04:59:38.01:data_valid=off 2006.286.04:59:38.01:"et 2006.286.04:59:38.01:!+3s 2006.286.04:59:41.02:"tape 2006.286.04:59:41.02:postob 2006.286.04:59:41.19/cable/+6.4944E-03 2006.286.04:59:41.19/wx/22.09,1014.9,76 2006.286.04:59:42.08/fmout-gps/S +2.40E-07 2006.286.04:59:42.08:scan_name=286-0500,jd0610,200 2006.286.04:59:42.08:source=2201+315,220314.98,314538.3,2000.0,cw 2006.286.04:59:43.14#flagr#flagr/antenna,new-source 2006.286.04:59:43.14:checkk5 2006.286.04:59:43.65/chk_autoobs//k5ts1/ autoobs is running! 2006.286.04:59:44.06/chk_autoobs//k5ts2/ autoobs is running! 2006.286.04:59:44.55/chk_autoobs//k5ts3/ autoobs is running! 2006.286.04:59:44.97/chk_autoobs//k5ts4/ autoobs is running! 2006.286.04:59:45.40/chk_obsdata//k5ts1/T2860458??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:59:46.15/chk_obsdata//k5ts2/T2860458??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:59:46.64/chk_obsdata//k5ts3/T2860458??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:59:46.98/chk_obsdata//k5ts4/T2860458??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.04:59:48.04/k5log//k5ts1_log_newline 2006.286.04:59:48.93/k5log//k5ts2_log_newline 2006.286.04:59:49.79/k5log//k5ts3_log_newline 2006.286.04:59:50.80/k5log//k5ts4_log_newline 2006.286.04:59:50.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.04:59:50.82:setupk4=1 2006.286.04:59:50.82$setupk4/echo=on 2006.286.04:59:50.82$setupk4/pcalon 2006.286.04:59:50.82$pcalon/"no phase cal control is implemented here 2006.286.04:59:50.82$setupk4/"tpicd=stop 2006.286.04:59:50.82$setupk4/"rec=synch_on 2006.286.04:59:50.82$setupk4/"rec_mode=128 2006.286.04:59:50.82$setupk4/!* 2006.286.04:59:50.82$setupk4/recpk4 2006.286.04:59:50.82$recpk4/recpatch= 2006.286.04:59:50.82$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.04:59:50.83$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.04:59:50.83$setupk4/vck44 2006.286.04:59:50.83$vck44/valo=1,524.99 2006.286.04:59:50.83#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.04:59:50.83#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.04:59:50.83#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:50.83#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:59:50.83#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:59:50.83#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:59:50.83#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:59:50.83#ibcon#first serial, iclass 14, count 0 2006.286.04:59:50.83#ibcon#enter sib2, iclass 14, count 0 2006.286.04:59:50.83#ibcon#flushed, iclass 14, count 0 2006.286.04:59:50.83#ibcon#about to write, iclass 14, count 0 2006.286.04:59:50.83#ibcon#wrote, iclass 14, count 0 2006.286.04:59:50.83#ibcon#about to read 3, iclass 14, count 0 2006.286.04:59:50.85#ibcon#read 3, iclass 14, count 0 2006.286.04:59:50.85#ibcon#about to read 4, iclass 14, count 0 2006.286.04:59:50.85#ibcon#read 4, iclass 14, count 0 2006.286.04:59:50.85#ibcon#about to read 5, iclass 14, count 0 2006.286.04:59:50.85#ibcon#read 5, iclass 14, count 0 2006.286.04:59:50.85#ibcon#about to read 6, iclass 14, count 0 2006.286.04:59:50.85#ibcon#read 6, iclass 14, count 0 2006.286.04:59:50.85#ibcon#end of sib2, iclass 14, count 0 2006.286.04:59:50.85#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:59:50.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:59:50.85#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.04:59:50.85#ibcon#*before write, iclass 14, count 0 2006.286.04:59:50.85#ibcon#enter sib2, iclass 14, count 0 2006.286.04:59:50.85#ibcon#flushed, iclass 14, count 0 2006.286.04:59:50.85#ibcon#about to write, iclass 14, count 0 2006.286.04:59:50.85#ibcon#wrote, iclass 14, count 0 2006.286.04:59:50.85#ibcon#about to read 3, iclass 14, count 0 2006.286.04:59:50.90#ibcon#read 3, iclass 14, count 0 2006.286.04:59:50.90#ibcon#about to read 4, iclass 14, count 0 2006.286.04:59:50.90#ibcon#read 4, iclass 14, count 0 2006.286.04:59:50.90#ibcon#about to read 5, iclass 14, count 0 2006.286.04:59:50.90#ibcon#read 5, iclass 14, count 0 2006.286.04:59:50.90#ibcon#about to read 6, iclass 14, count 0 2006.286.04:59:50.90#ibcon#read 6, iclass 14, count 0 2006.286.04:59:50.90#ibcon#end of sib2, iclass 14, count 0 2006.286.04:59:50.90#ibcon#*after write, iclass 14, count 0 2006.286.04:59:50.90#ibcon#*before return 0, iclass 14, count 0 2006.286.04:59:50.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:59:50.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:59:50.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:59:50.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:59:50.90$vck44/va=1,7 2006.286.04:59:50.90#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.04:59:50.90#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.04:59:50.90#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:50.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:59:50.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:59:50.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:59:50.90#ibcon#enter wrdev, iclass 16, count 2 2006.286.04:59:50.90#ibcon#first serial, iclass 16, count 2 2006.286.04:59:50.90#ibcon#enter sib2, iclass 16, count 2 2006.286.04:59:50.90#ibcon#flushed, iclass 16, count 2 2006.286.04:59:50.90#ibcon#about to write, iclass 16, count 2 2006.286.04:59:50.90#ibcon#wrote, iclass 16, count 2 2006.286.04:59:50.90#ibcon#about to read 3, iclass 16, count 2 2006.286.04:59:50.92#ibcon#read 3, iclass 16, count 2 2006.286.04:59:50.92#ibcon#about to read 4, iclass 16, count 2 2006.286.04:59:50.92#ibcon#read 4, iclass 16, count 2 2006.286.04:59:50.92#ibcon#about to read 5, iclass 16, count 2 2006.286.04:59:50.92#ibcon#read 5, iclass 16, count 2 2006.286.04:59:50.92#ibcon#about to read 6, iclass 16, count 2 2006.286.04:59:50.92#ibcon#read 6, iclass 16, count 2 2006.286.04:59:50.92#ibcon#end of sib2, iclass 16, count 2 2006.286.04:59:50.92#ibcon#*mode == 0, iclass 16, count 2 2006.286.04:59:50.92#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.04:59:50.92#ibcon#[25=AT01-07\r\n] 2006.286.04:59:50.92#ibcon#*before write, iclass 16, count 2 2006.286.04:59:50.92#ibcon#enter sib2, iclass 16, count 2 2006.286.04:59:50.92#ibcon#flushed, iclass 16, count 2 2006.286.04:59:50.92#ibcon#about to write, iclass 16, count 2 2006.286.04:59:50.92#ibcon#wrote, iclass 16, count 2 2006.286.04:59:50.92#ibcon#about to read 3, iclass 16, count 2 2006.286.04:59:50.95#ibcon#read 3, iclass 16, count 2 2006.286.04:59:50.95#ibcon#about to read 4, iclass 16, count 2 2006.286.04:59:50.95#ibcon#read 4, iclass 16, count 2 2006.286.04:59:50.95#ibcon#about to read 5, iclass 16, count 2 2006.286.04:59:50.95#ibcon#read 5, iclass 16, count 2 2006.286.04:59:50.95#ibcon#about to read 6, iclass 16, count 2 2006.286.04:59:50.95#ibcon#read 6, iclass 16, count 2 2006.286.04:59:50.95#ibcon#end of sib2, iclass 16, count 2 2006.286.04:59:50.95#ibcon#*after write, iclass 16, count 2 2006.286.04:59:50.95#ibcon#*before return 0, iclass 16, count 2 2006.286.04:59:50.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:59:50.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:59:50.95#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.04:59:50.95#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:50.95#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:59:51.07#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:59:51.07#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:59:51.07#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:59:51.07#ibcon#first serial, iclass 16, count 0 2006.286.04:59:51.07#ibcon#enter sib2, iclass 16, count 0 2006.286.04:59:51.07#ibcon#flushed, iclass 16, count 0 2006.286.04:59:51.07#ibcon#about to write, iclass 16, count 0 2006.286.04:59:51.07#ibcon#wrote, iclass 16, count 0 2006.286.04:59:51.07#ibcon#about to read 3, iclass 16, count 0 2006.286.04:59:51.09#ibcon#read 3, iclass 16, count 0 2006.286.04:59:51.09#ibcon#about to read 4, iclass 16, count 0 2006.286.04:59:51.09#ibcon#read 4, iclass 16, count 0 2006.286.04:59:51.09#ibcon#about to read 5, iclass 16, count 0 2006.286.04:59:51.09#ibcon#read 5, iclass 16, count 0 2006.286.04:59:51.09#ibcon#about to read 6, iclass 16, count 0 2006.286.04:59:51.09#ibcon#read 6, iclass 16, count 0 2006.286.04:59:51.09#ibcon#end of sib2, iclass 16, count 0 2006.286.04:59:51.09#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:59:51.09#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:59:51.09#ibcon#[25=USB\r\n] 2006.286.04:59:51.09#ibcon#*before write, iclass 16, count 0 2006.286.04:59:51.09#ibcon#enter sib2, iclass 16, count 0 2006.286.04:59:51.09#ibcon#flushed, iclass 16, count 0 2006.286.04:59:51.09#ibcon#about to write, iclass 16, count 0 2006.286.04:59:51.09#ibcon#wrote, iclass 16, count 0 2006.286.04:59:51.09#ibcon#about to read 3, iclass 16, count 0 2006.286.04:59:51.12#ibcon#read 3, iclass 16, count 0 2006.286.04:59:51.12#ibcon#about to read 4, iclass 16, count 0 2006.286.04:59:51.12#ibcon#read 4, iclass 16, count 0 2006.286.04:59:51.12#ibcon#about to read 5, iclass 16, count 0 2006.286.04:59:51.12#ibcon#read 5, iclass 16, count 0 2006.286.04:59:51.12#ibcon#about to read 6, iclass 16, count 0 2006.286.04:59:51.12#ibcon#read 6, iclass 16, count 0 2006.286.04:59:51.12#ibcon#end of sib2, iclass 16, count 0 2006.286.04:59:51.12#ibcon#*after write, iclass 16, count 0 2006.286.04:59:51.12#ibcon#*before return 0, iclass 16, count 0 2006.286.04:59:51.12#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:59:51.12#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:59:51.12#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:59:51.12#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:59:51.12$vck44/valo=2,534.99 2006.286.04:59:51.12#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.04:59:51.12#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.04:59:51.12#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:51.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:59:51.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:59:51.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:59:51.12#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:59:51.12#ibcon#first serial, iclass 18, count 0 2006.286.04:59:51.12#ibcon#enter sib2, iclass 18, count 0 2006.286.04:59:51.12#ibcon#flushed, iclass 18, count 0 2006.286.04:59:51.12#ibcon#about to write, iclass 18, count 0 2006.286.04:59:51.12#ibcon#wrote, iclass 18, count 0 2006.286.04:59:51.12#ibcon#about to read 3, iclass 18, count 0 2006.286.04:59:51.14#ibcon#read 3, iclass 18, count 0 2006.286.04:59:51.14#ibcon#about to read 4, iclass 18, count 0 2006.286.04:59:51.14#ibcon#read 4, iclass 18, count 0 2006.286.04:59:51.14#ibcon#about to read 5, iclass 18, count 0 2006.286.04:59:51.14#ibcon#read 5, iclass 18, count 0 2006.286.04:59:51.14#ibcon#about to read 6, iclass 18, count 0 2006.286.04:59:51.14#ibcon#read 6, iclass 18, count 0 2006.286.04:59:51.14#ibcon#end of sib2, iclass 18, count 0 2006.286.04:59:51.14#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:59:51.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:59:51.14#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.04:59:51.14#ibcon#*before write, iclass 18, count 0 2006.286.04:59:51.14#ibcon#enter sib2, iclass 18, count 0 2006.286.04:59:51.14#ibcon#flushed, iclass 18, count 0 2006.286.04:59:51.14#ibcon#about to write, iclass 18, count 0 2006.286.04:59:51.14#ibcon#wrote, iclass 18, count 0 2006.286.04:59:51.14#ibcon#about to read 3, iclass 18, count 0 2006.286.04:59:51.18#ibcon#read 3, iclass 18, count 0 2006.286.04:59:51.18#ibcon#about to read 4, iclass 18, count 0 2006.286.04:59:51.18#ibcon#read 4, iclass 18, count 0 2006.286.04:59:51.18#ibcon#about to read 5, iclass 18, count 0 2006.286.04:59:51.18#ibcon#read 5, iclass 18, count 0 2006.286.04:59:51.18#ibcon#about to read 6, iclass 18, count 0 2006.286.04:59:51.18#ibcon#read 6, iclass 18, count 0 2006.286.04:59:51.18#ibcon#end of sib2, iclass 18, count 0 2006.286.04:59:51.18#ibcon#*after write, iclass 18, count 0 2006.286.04:59:51.18#ibcon#*before return 0, iclass 18, count 0 2006.286.04:59:51.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:59:51.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:59:51.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:59:51.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:59:51.18$vck44/va=2,6 2006.286.04:59:51.18#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.04:59:51.18#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.04:59:51.18#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:51.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:59:51.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:59:51.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:59:51.24#ibcon#enter wrdev, iclass 20, count 2 2006.286.04:59:51.24#ibcon#first serial, iclass 20, count 2 2006.286.04:59:51.24#ibcon#enter sib2, iclass 20, count 2 2006.286.04:59:51.24#ibcon#flushed, iclass 20, count 2 2006.286.04:59:51.24#ibcon#about to write, iclass 20, count 2 2006.286.04:59:51.24#ibcon#wrote, iclass 20, count 2 2006.286.04:59:51.24#ibcon#about to read 3, iclass 20, count 2 2006.286.04:59:51.26#ibcon#read 3, iclass 20, count 2 2006.286.04:59:51.26#ibcon#about to read 4, iclass 20, count 2 2006.286.04:59:51.26#ibcon#read 4, iclass 20, count 2 2006.286.04:59:51.26#ibcon#about to read 5, iclass 20, count 2 2006.286.04:59:51.26#ibcon#read 5, iclass 20, count 2 2006.286.04:59:51.26#ibcon#about to read 6, iclass 20, count 2 2006.286.04:59:51.26#ibcon#read 6, iclass 20, count 2 2006.286.04:59:51.26#ibcon#end of sib2, iclass 20, count 2 2006.286.04:59:51.26#ibcon#*mode == 0, iclass 20, count 2 2006.286.04:59:51.26#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.04:59:51.26#ibcon#[25=AT02-06\r\n] 2006.286.04:59:51.26#ibcon#*before write, iclass 20, count 2 2006.286.04:59:51.26#ibcon#enter sib2, iclass 20, count 2 2006.286.04:59:51.26#ibcon#flushed, iclass 20, count 2 2006.286.04:59:51.26#ibcon#about to write, iclass 20, count 2 2006.286.04:59:51.26#ibcon#wrote, iclass 20, count 2 2006.286.04:59:51.26#ibcon#about to read 3, iclass 20, count 2 2006.286.04:59:51.29#ibcon#read 3, iclass 20, count 2 2006.286.04:59:51.29#ibcon#about to read 4, iclass 20, count 2 2006.286.04:59:51.29#ibcon#read 4, iclass 20, count 2 2006.286.04:59:51.29#ibcon#about to read 5, iclass 20, count 2 2006.286.04:59:51.29#ibcon#read 5, iclass 20, count 2 2006.286.04:59:51.29#ibcon#about to read 6, iclass 20, count 2 2006.286.04:59:51.29#ibcon#read 6, iclass 20, count 2 2006.286.04:59:51.29#ibcon#end of sib2, iclass 20, count 2 2006.286.04:59:51.29#ibcon#*after write, iclass 20, count 2 2006.286.04:59:51.29#ibcon#*before return 0, iclass 20, count 2 2006.286.04:59:51.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:59:51.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:59:51.29#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.04:59:51.29#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:51.29#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:59:51.41#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:59:51.41#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:59:51.41#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:59:51.41#ibcon#first serial, iclass 20, count 0 2006.286.04:59:51.41#ibcon#enter sib2, iclass 20, count 0 2006.286.04:59:51.41#ibcon#flushed, iclass 20, count 0 2006.286.04:59:51.41#ibcon#about to write, iclass 20, count 0 2006.286.04:59:51.41#ibcon#wrote, iclass 20, count 0 2006.286.04:59:51.41#ibcon#about to read 3, iclass 20, count 0 2006.286.04:59:51.43#ibcon#read 3, iclass 20, count 0 2006.286.04:59:51.43#ibcon#about to read 4, iclass 20, count 0 2006.286.04:59:51.43#ibcon#read 4, iclass 20, count 0 2006.286.04:59:51.43#ibcon#about to read 5, iclass 20, count 0 2006.286.04:59:51.43#ibcon#read 5, iclass 20, count 0 2006.286.04:59:51.43#ibcon#about to read 6, iclass 20, count 0 2006.286.04:59:51.43#ibcon#read 6, iclass 20, count 0 2006.286.04:59:51.43#ibcon#end of sib2, iclass 20, count 0 2006.286.04:59:51.43#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:59:51.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:59:51.43#ibcon#[25=USB\r\n] 2006.286.04:59:51.43#ibcon#*before write, iclass 20, count 0 2006.286.04:59:51.43#ibcon#enter sib2, iclass 20, count 0 2006.286.04:59:51.43#ibcon#flushed, iclass 20, count 0 2006.286.04:59:51.43#ibcon#about to write, iclass 20, count 0 2006.286.04:59:51.43#ibcon#wrote, iclass 20, count 0 2006.286.04:59:51.43#ibcon#about to read 3, iclass 20, count 0 2006.286.04:59:51.46#ibcon#read 3, iclass 20, count 0 2006.286.04:59:51.46#ibcon#about to read 4, iclass 20, count 0 2006.286.04:59:51.46#ibcon#read 4, iclass 20, count 0 2006.286.04:59:51.46#ibcon#about to read 5, iclass 20, count 0 2006.286.04:59:51.46#ibcon#read 5, iclass 20, count 0 2006.286.04:59:51.46#ibcon#about to read 6, iclass 20, count 0 2006.286.04:59:51.46#ibcon#read 6, iclass 20, count 0 2006.286.04:59:51.46#ibcon#end of sib2, iclass 20, count 0 2006.286.04:59:51.46#ibcon#*after write, iclass 20, count 0 2006.286.04:59:51.46#ibcon#*before return 0, iclass 20, count 0 2006.286.04:59:51.46#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:59:51.46#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:59:51.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:59:51.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:59:51.46$vck44/valo=3,564.99 2006.286.04:59:51.46#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:59:51.46#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:59:51.46#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:51.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:59:51.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:59:51.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:59:51.46#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:59:51.46#ibcon#first serial, iclass 22, count 0 2006.286.04:59:51.46#ibcon#enter sib2, iclass 22, count 0 2006.286.04:59:51.46#ibcon#flushed, iclass 22, count 0 2006.286.04:59:51.46#ibcon#about to write, iclass 22, count 0 2006.286.04:59:51.46#ibcon#wrote, iclass 22, count 0 2006.286.04:59:51.46#ibcon#about to read 3, iclass 22, count 0 2006.286.04:59:51.48#ibcon#read 3, iclass 22, count 0 2006.286.04:59:52.09#ibcon#about to read 4, iclass 22, count 0 2006.286.04:59:52.09#ibcon#read 4, iclass 22, count 0 2006.286.04:59:52.09#ibcon#about to read 5, iclass 22, count 0 2006.286.04:59:52.09#ibcon#read 5, iclass 22, count 0 2006.286.04:59:52.09#ibcon#about to read 6, iclass 22, count 0 2006.286.04:59:52.09#ibcon#read 6, iclass 22, count 0 2006.286.04:59:52.09#ibcon#end of sib2, iclass 22, count 0 2006.286.04:59:52.09#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:59:52.09#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:59:52.09#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.04:59:52.09#ibcon#*before write, iclass 22, count 0 2006.286.04:59:52.09#ibcon#enter sib2, iclass 22, count 0 2006.286.04:59:52.09#ibcon#flushed, iclass 22, count 0 2006.286.04:59:52.09#ibcon#about to write, iclass 22, count 0 2006.286.04:59:52.09#ibcon#wrote, iclass 22, count 0 2006.286.04:59:52.09#ibcon#about to read 3, iclass 22, count 0 2006.286.04:59:52.13#ibcon#read 3, iclass 22, count 0 2006.286.04:59:52.13#ibcon#about to read 4, iclass 22, count 0 2006.286.04:59:52.13#ibcon#read 4, iclass 22, count 0 2006.286.04:59:52.13#ibcon#about to read 5, iclass 22, count 0 2006.286.04:59:52.13#ibcon#read 5, iclass 22, count 0 2006.286.04:59:52.13#ibcon#about to read 6, iclass 22, count 0 2006.286.04:59:52.13#ibcon#read 6, iclass 22, count 0 2006.286.04:59:52.13#ibcon#end of sib2, iclass 22, count 0 2006.286.04:59:52.13#ibcon#*after write, iclass 22, count 0 2006.286.04:59:52.13#ibcon#*before return 0, iclass 22, count 0 2006.286.04:59:52.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:59:52.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:59:52.13#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:59:52.13#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:59:52.13$vck44/va=3,7 2006.286.04:59:52.13#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.04:59:52.13#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.04:59:52.13#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:52.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:59:52.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:59:52.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:59:52.13#ibcon#enter wrdev, iclass 25, count 2 2006.286.04:59:52.13#ibcon#first serial, iclass 25, count 2 2006.286.04:59:52.13#ibcon#enter sib2, iclass 25, count 2 2006.286.04:59:52.13#ibcon#flushed, iclass 25, count 2 2006.286.04:59:52.13#ibcon#about to write, iclass 25, count 2 2006.286.04:59:52.13#ibcon#wrote, iclass 25, count 2 2006.286.04:59:52.13#ibcon#about to read 3, iclass 25, count 2 2006.286.04:59:52.14#abcon#<5=/04 3.3 7.5 22.10 761014.9\r\n> 2006.286.04:59:52.15#ibcon#read 3, iclass 25, count 2 2006.286.04:59:52.15#ibcon#about to read 4, iclass 25, count 2 2006.286.04:59:52.15#ibcon#read 4, iclass 25, count 2 2006.286.04:59:52.15#ibcon#about to read 5, iclass 25, count 2 2006.286.04:59:52.15#ibcon#read 5, iclass 25, count 2 2006.286.04:59:52.15#ibcon#about to read 6, iclass 25, count 2 2006.286.04:59:52.15#ibcon#read 6, iclass 25, count 2 2006.286.04:59:52.15#ibcon#end of sib2, iclass 25, count 2 2006.286.04:59:52.15#ibcon#*mode == 0, iclass 25, count 2 2006.286.04:59:52.15#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.04:59:52.15#ibcon#[25=AT03-07\r\n] 2006.286.04:59:52.15#ibcon#*before write, iclass 25, count 2 2006.286.04:59:52.15#ibcon#enter sib2, iclass 25, count 2 2006.286.04:59:52.15#ibcon#flushed, iclass 25, count 2 2006.286.04:59:52.15#ibcon#about to write, iclass 25, count 2 2006.286.04:59:52.15#ibcon#wrote, iclass 25, count 2 2006.286.04:59:52.15#ibcon#about to read 3, iclass 25, count 2 2006.286.04:59:52.16#abcon#{5=INTERFACE CLEAR} 2006.286.04:59:52.18#ibcon#read 3, iclass 25, count 2 2006.286.04:59:52.18#ibcon#about to read 4, iclass 25, count 2 2006.286.04:59:52.18#ibcon#read 4, iclass 25, count 2 2006.286.04:59:52.18#ibcon#about to read 5, iclass 25, count 2 2006.286.04:59:52.18#ibcon#read 5, iclass 25, count 2 2006.286.04:59:52.18#ibcon#about to read 6, iclass 25, count 2 2006.286.04:59:52.18#ibcon#read 6, iclass 25, count 2 2006.286.04:59:52.18#ibcon#end of sib2, iclass 25, count 2 2006.286.04:59:52.18#ibcon#*after write, iclass 25, count 2 2006.286.04:59:52.18#ibcon#*before return 0, iclass 25, count 2 2006.286.04:59:52.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:59:52.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.04:59:52.18#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.04:59:52.18#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:52.18#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:59:52.22#abcon#[5=S1D000X0/0*\r\n] 2006.286.04:59:52.30#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:59:52.30#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:59:52.30#ibcon#enter wrdev, iclass 25, count 0 2006.286.04:59:52.30#ibcon#first serial, iclass 25, count 0 2006.286.04:59:52.30#ibcon#enter sib2, iclass 25, count 0 2006.286.04:59:52.30#ibcon#flushed, iclass 25, count 0 2006.286.04:59:52.30#ibcon#about to write, iclass 25, count 0 2006.286.04:59:52.30#ibcon#wrote, iclass 25, count 0 2006.286.04:59:52.30#ibcon#about to read 3, iclass 25, count 0 2006.286.04:59:52.32#ibcon#read 3, iclass 25, count 0 2006.286.04:59:52.32#ibcon#about to read 4, iclass 25, count 0 2006.286.04:59:52.32#ibcon#read 4, iclass 25, count 0 2006.286.04:59:52.32#ibcon#about to read 5, iclass 25, count 0 2006.286.04:59:52.32#ibcon#read 5, iclass 25, count 0 2006.286.04:59:52.32#ibcon#about to read 6, iclass 25, count 0 2006.286.04:59:52.32#ibcon#read 6, iclass 25, count 0 2006.286.04:59:52.32#ibcon#end of sib2, iclass 25, count 0 2006.286.04:59:52.32#ibcon#*mode == 0, iclass 25, count 0 2006.286.04:59:52.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.04:59:52.32#ibcon#[25=USB\r\n] 2006.286.04:59:52.32#ibcon#*before write, iclass 25, count 0 2006.286.04:59:52.32#ibcon#enter sib2, iclass 25, count 0 2006.286.04:59:52.32#ibcon#flushed, iclass 25, count 0 2006.286.04:59:52.32#ibcon#about to write, iclass 25, count 0 2006.286.04:59:52.32#ibcon#wrote, iclass 25, count 0 2006.286.04:59:52.32#ibcon#about to read 3, iclass 25, count 0 2006.286.04:59:52.35#ibcon#read 3, iclass 25, count 0 2006.286.04:59:52.35#ibcon#about to read 4, iclass 25, count 0 2006.286.04:59:52.35#ibcon#read 4, iclass 25, count 0 2006.286.04:59:52.35#ibcon#about to read 5, iclass 25, count 0 2006.286.04:59:52.35#ibcon#read 5, iclass 25, count 0 2006.286.04:59:52.35#ibcon#about to read 6, iclass 25, count 0 2006.286.04:59:52.35#ibcon#read 6, iclass 25, count 0 2006.286.04:59:52.35#ibcon#end of sib2, iclass 25, count 0 2006.286.04:59:52.35#ibcon#*after write, iclass 25, count 0 2006.286.04:59:52.35#ibcon#*before return 0, iclass 25, count 0 2006.286.04:59:52.35#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:59:52.35#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.04:59:52.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.04:59:52.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.04:59:52.35$vck44/valo=4,624.99 2006.286.04:59:52.35#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:59:52.35#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:59:52.35#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:52.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:59:52.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:59:52.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:59:52.35#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:59:52.35#ibcon#first serial, iclass 30, count 0 2006.286.04:59:52.35#ibcon#enter sib2, iclass 30, count 0 2006.286.04:59:52.35#ibcon#flushed, iclass 30, count 0 2006.286.04:59:52.35#ibcon#about to write, iclass 30, count 0 2006.286.04:59:52.35#ibcon#wrote, iclass 30, count 0 2006.286.04:59:52.35#ibcon#about to read 3, iclass 30, count 0 2006.286.04:59:52.37#ibcon#read 3, iclass 30, count 0 2006.286.04:59:52.51#ibcon#about to read 4, iclass 30, count 0 2006.286.04:59:52.51#ibcon#read 4, iclass 30, count 0 2006.286.04:59:52.51#ibcon#about to read 5, iclass 30, count 0 2006.286.04:59:52.51#ibcon#read 5, iclass 30, count 0 2006.286.04:59:52.51#ibcon#about to read 6, iclass 30, count 0 2006.286.04:59:52.51#ibcon#read 6, iclass 30, count 0 2006.286.04:59:52.51#ibcon#end of sib2, iclass 30, count 0 2006.286.04:59:52.51#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:59:52.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:59:52.51#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.04:59:52.51#ibcon#*before write, iclass 30, count 0 2006.286.04:59:52.51#ibcon#enter sib2, iclass 30, count 0 2006.286.04:59:52.51#ibcon#flushed, iclass 30, count 0 2006.286.04:59:52.51#ibcon#about to write, iclass 30, count 0 2006.286.04:59:52.51#ibcon#wrote, iclass 30, count 0 2006.286.04:59:52.51#ibcon#about to read 3, iclass 30, count 0 2006.286.04:59:52.55#ibcon#read 3, iclass 30, count 0 2006.286.04:59:52.55#ibcon#about to read 4, iclass 30, count 0 2006.286.04:59:52.55#ibcon#read 4, iclass 30, count 0 2006.286.04:59:52.55#ibcon#about to read 5, iclass 30, count 0 2006.286.04:59:52.55#ibcon#read 5, iclass 30, count 0 2006.286.04:59:52.55#ibcon#about to read 6, iclass 30, count 0 2006.286.04:59:52.55#ibcon#read 6, iclass 30, count 0 2006.286.04:59:52.55#ibcon#end of sib2, iclass 30, count 0 2006.286.04:59:52.55#ibcon#*after write, iclass 30, count 0 2006.286.04:59:52.55#ibcon#*before return 0, iclass 30, count 0 2006.286.04:59:52.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:59:52.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:59:52.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:59:52.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:59:52.55$vck44/va=4,6 2006.286.04:59:52.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.04:59:52.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.04:59:52.55#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:52.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:59:52.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:59:52.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:59:52.55#ibcon#enter wrdev, iclass 32, count 2 2006.286.04:59:52.55#ibcon#first serial, iclass 32, count 2 2006.286.04:59:52.55#ibcon#enter sib2, iclass 32, count 2 2006.286.04:59:52.55#ibcon#flushed, iclass 32, count 2 2006.286.04:59:52.55#ibcon#about to write, iclass 32, count 2 2006.286.04:59:52.55#ibcon#wrote, iclass 32, count 2 2006.286.04:59:52.55#ibcon#about to read 3, iclass 32, count 2 2006.286.04:59:52.57#ibcon#read 3, iclass 32, count 2 2006.286.04:59:52.57#ibcon#about to read 4, iclass 32, count 2 2006.286.04:59:52.57#ibcon#read 4, iclass 32, count 2 2006.286.04:59:52.57#ibcon#about to read 5, iclass 32, count 2 2006.286.04:59:52.57#ibcon#read 5, iclass 32, count 2 2006.286.04:59:52.57#ibcon#about to read 6, iclass 32, count 2 2006.286.04:59:52.57#ibcon#read 6, iclass 32, count 2 2006.286.04:59:52.57#ibcon#end of sib2, iclass 32, count 2 2006.286.04:59:52.57#ibcon#*mode == 0, iclass 32, count 2 2006.286.04:59:52.57#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.04:59:52.57#ibcon#[25=AT04-06\r\n] 2006.286.04:59:52.57#ibcon#*before write, iclass 32, count 2 2006.286.04:59:52.57#ibcon#enter sib2, iclass 32, count 2 2006.286.04:59:52.57#ibcon#flushed, iclass 32, count 2 2006.286.04:59:52.57#ibcon#about to write, iclass 32, count 2 2006.286.04:59:52.57#ibcon#wrote, iclass 32, count 2 2006.286.04:59:52.57#ibcon#about to read 3, iclass 32, count 2 2006.286.04:59:52.60#ibcon#read 3, iclass 32, count 2 2006.286.04:59:52.60#ibcon#about to read 4, iclass 32, count 2 2006.286.04:59:52.60#ibcon#read 4, iclass 32, count 2 2006.286.04:59:52.60#ibcon#about to read 5, iclass 32, count 2 2006.286.04:59:52.60#ibcon#read 5, iclass 32, count 2 2006.286.04:59:52.60#ibcon#about to read 6, iclass 32, count 2 2006.286.04:59:52.60#ibcon#read 6, iclass 32, count 2 2006.286.04:59:52.60#ibcon#end of sib2, iclass 32, count 2 2006.286.04:59:52.60#ibcon#*after write, iclass 32, count 2 2006.286.04:59:52.60#ibcon#*before return 0, iclass 32, count 2 2006.286.04:59:52.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:59:52.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:59:52.60#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.04:59:52.60#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:52.60#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:59:52.72#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:59:52.72#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:59:52.72#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:59:52.72#ibcon#first serial, iclass 32, count 0 2006.286.04:59:52.72#ibcon#enter sib2, iclass 32, count 0 2006.286.04:59:52.72#ibcon#flushed, iclass 32, count 0 2006.286.04:59:52.72#ibcon#about to write, iclass 32, count 0 2006.286.04:59:52.72#ibcon#wrote, iclass 32, count 0 2006.286.04:59:52.72#ibcon#about to read 3, iclass 32, count 0 2006.286.04:59:52.74#ibcon#read 3, iclass 32, count 0 2006.286.04:59:52.74#ibcon#about to read 4, iclass 32, count 0 2006.286.04:59:52.74#ibcon#read 4, iclass 32, count 0 2006.286.04:59:52.74#ibcon#about to read 5, iclass 32, count 0 2006.286.04:59:52.74#ibcon#read 5, iclass 32, count 0 2006.286.04:59:52.74#ibcon#about to read 6, iclass 32, count 0 2006.286.04:59:52.74#ibcon#read 6, iclass 32, count 0 2006.286.04:59:52.74#ibcon#end of sib2, iclass 32, count 0 2006.286.04:59:52.74#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:59:52.74#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:59:52.74#ibcon#[25=USB\r\n] 2006.286.04:59:52.74#ibcon#*before write, iclass 32, count 0 2006.286.04:59:52.74#ibcon#enter sib2, iclass 32, count 0 2006.286.04:59:52.74#ibcon#flushed, iclass 32, count 0 2006.286.04:59:52.74#ibcon#about to write, iclass 32, count 0 2006.286.04:59:52.74#ibcon#wrote, iclass 32, count 0 2006.286.04:59:52.74#ibcon#about to read 3, iclass 32, count 0 2006.286.04:59:52.77#ibcon#read 3, iclass 32, count 0 2006.286.04:59:52.77#ibcon#about to read 4, iclass 32, count 0 2006.286.04:59:52.77#ibcon#read 4, iclass 32, count 0 2006.286.04:59:52.77#ibcon#about to read 5, iclass 32, count 0 2006.286.04:59:52.77#ibcon#read 5, iclass 32, count 0 2006.286.04:59:52.77#ibcon#about to read 6, iclass 32, count 0 2006.286.04:59:52.77#ibcon#read 6, iclass 32, count 0 2006.286.04:59:52.77#ibcon#end of sib2, iclass 32, count 0 2006.286.04:59:52.77#ibcon#*after write, iclass 32, count 0 2006.286.04:59:52.77#ibcon#*before return 0, iclass 32, count 0 2006.286.04:59:52.77#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:59:52.77#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:59:52.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:59:52.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:59:52.77$vck44/valo=5,734.99 2006.286.04:59:52.77#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.04:59:52.77#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.04:59:52.77#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:52.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:59:52.77#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:59:52.77#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:59:52.77#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:59:52.77#ibcon#first serial, iclass 34, count 0 2006.286.04:59:52.77#ibcon#enter sib2, iclass 34, count 0 2006.286.04:59:52.77#ibcon#flushed, iclass 34, count 0 2006.286.04:59:52.77#ibcon#about to write, iclass 34, count 0 2006.286.04:59:52.77#ibcon#wrote, iclass 34, count 0 2006.286.04:59:52.77#ibcon#about to read 3, iclass 34, count 0 2006.286.04:59:52.79#ibcon#read 3, iclass 34, count 0 2006.286.04:59:52.91#ibcon#about to read 4, iclass 34, count 0 2006.286.04:59:52.91#ibcon#read 4, iclass 34, count 0 2006.286.04:59:52.91#ibcon#about to read 5, iclass 34, count 0 2006.286.04:59:52.91#ibcon#read 5, iclass 34, count 0 2006.286.04:59:52.91#ibcon#about to read 6, iclass 34, count 0 2006.286.04:59:52.91#ibcon#read 6, iclass 34, count 0 2006.286.04:59:52.91#ibcon#end of sib2, iclass 34, count 0 2006.286.04:59:52.91#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:59:52.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:59:52.91#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.04:59:52.91#ibcon#*before write, iclass 34, count 0 2006.286.04:59:52.91#ibcon#enter sib2, iclass 34, count 0 2006.286.04:59:52.91#ibcon#flushed, iclass 34, count 0 2006.286.04:59:52.91#ibcon#about to write, iclass 34, count 0 2006.286.04:59:52.91#ibcon#wrote, iclass 34, count 0 2006.286.04:59:52.91#ibcon#about to read 3, iclass 34, count 0 2006.286.04:59:52.96#ibcon#read 3, iclass 34, count 0 2006.286.04:59:52.96#ibcon#about to read 4, iclass 34, count 0 2006.286.04:59:52.96#ibcon#read 4, iclass 34, count 0 2006.286.04:59:52.96#ibcon#about to read 5, iclass 34, count 0 2006.286.04:59:52.96#ibcon#read 5, iclass 34, count 0 2006.286.04:59:52.96#ibcon#about to read 6, iclass 34, count 0 2006.286.04:59:52.96#ibcon#read 6, iclass 34, count 0 2006.286.04:59:52.96#ibcon#end of sib2, iclass 34, count 0 2006.286.04:59:52.96#ibcon#*after write, iclass 34, count 0 2006.286.04:59:52.96#ibcon#*before return 0, iclass 34, count 0 2006.286.04:59:52.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:59:52.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:59:52.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:59:52.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:59:52.96$vck44/va=5,3 2006.286.04:59:52.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.04:59:52.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.04:59:52.96#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:52.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:59:52.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:59:52.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:59:52.96#ibcon#enter wrdev, iclass 36, count 2 2006.286.04:59:52.96#ibcon#first serial, iclass 36, count 2 2006.286.04:59:52.96#ibcon#enter sib2, iclass 36, count 2 2006.286.04:59:52.96#ibcon#flushed, iclass 36, count 2 2006.286.04:59:52.96#ibcon#about to write, iclass 36, count 2 2006.286.04:59:52.96#ibcon#wrote, iclass 36, count 2 2006.286.04:59:52.96#ibcon#about to read 3, iclass 36, count 2 2006.286.04:59:52.98#ibcon#read 3, iclass 36, count 2 2006.286.04:59:52.98#ibcon#about to read 4, iclass 36, count 2 2006.286.04:59:52.98#ibcon#read 4, iclass 36, count 2 2006.286.04:59:52.98#ibcon#about to read 5, iclass 36, count 2 2006.286.04:59:52.98#ibcon#read 5, iclass 36, count 2 2006.286.04:59:52.98#ibcon#about to read 6, iclass 36, count 2 2006.286.04:59:52.98#ibcon#read 6, iclass 36, count 2 2006.286.04:59:52.98#ibcon#end of sib2, iclass 36, count 2 2006.286.04:59:52.98#ibcon#*mode == 0, iclass 36, count 2 2006.286.04:59:52.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.04:59:52.98#ibcon#[25=AT05-03\r\n] 2006.286.04:59:52.98#ibcon#*before write, iclass 36, count 2 2006.286.04:59:52.98#ibcon#enter sib2, iclass 36, count 2 2006.286.04:59:52.98#ibcon#flushed, iclass 36, count 2 2006.286.04:59:52.98#ibcon#about to write, iclass 36, count 2 2006.286.04:59:52.98#ibcon#wrote, iclass 36, count 2 2006.286.04:59:52.98#ibcon#about to read 3, iclass 36, count 2 2006.286.04:59:53.01#ibcon#read 3, iclass 36, count 2 2006.286.04:59:53.01#ibcon#about to read 4, iclass 36, count 2 2006.286.04:59:53.01#ibcon#read 4, iclass 36, count 2 2006.286.04:59:53.01#ibcon#about to read 5, iclass 36, count 2 2006.286.04:59:53.01#ibcon#read 5, iclass 36, count 2 2006.286.04:59:53.01#ibcon#about to read 6, iclass 36, count 2 2006.286.04:59:53.01#ibcon#read 6, iclass 36, count 2 2006.286.04:59:53.01#ibcon#end of sib2, iclass 36, count 2 2006.286.04:59:53.01#ibcon#*after write, iclass 36, count 2 2006.286.04:59:53.01#ibcon#*before return 0, iclass 36, count 2 2006.286.04:59:53.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:59:53.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:59:53.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.04:59:53.01#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:53.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:59:53.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:59:53.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:59:53.13#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:59:53.13#ibcon#first serial, iclass 36, count 0 2006.286.04:59:53.13#ibcon#enter sib2, iclass 36, count 0 2006.286.04:59:53.13#ibcon#flushed, iclass 36, count 0 2006.286.04:59:53.13#ibcon#about to write, iclass 36, count 0 2006.286.04:59:53.13#ibcon#wrote, iclass 36, count 0 2006.286.04:59:53.13#ibcon#about to read 3, iclass 36, count 0 2006.286.04:59:53.15#ibcon#read 3, iclass 36, count 0 2006.286.04:59:53.15#ibcon#about to read 4, iclass 36, count 0 2006.286.04:59:53.15#ibcon#read 4, iclass 36, count 0 2006.286.04:59:53.15#ibcon#about to read 5, iclass 36, count 0 2006.286.04:59:53.15#ibcon#read 5, iclass 36, count 0 2006.286.04:59:53.15#ibcon#about to read 6, iclass 36, count 0 2006.286.04:59:53.15#ibcon#read 6, iclass 36, count 0 2006.286.04:59:53.15#ibcon#end of sib2, iclass 36, count 0 2006.286.04:59:53.15#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:59:53.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:59:53.15#ibcon#[25=USB\r\n] 2006.286.04:59:53.15#ibcon#*before write, iclass 36, count 0 2006.286.04:59:53.15#ibcon#enter sib2, iclass 36, count 0 2006.286.04:59:53.15#ibcon#flushed, iclass 36, count 0 2006.286.04:59:53.15#ibcon#about to write, iclass 36, count 0 2006.286.04:59:53.15#ibcon#wrote, iclass 36, count 0 2006.286.04:59:53.15#ibcon#about to read 3, iclass 36, count 0 2006.286.04:59:53.18#ibcon#read 3, iclass 36, count 0 2006.286.04:59:53.18#ibcon#about to read 4, iclass 36, count 0 2006.286.04:59:53.18#ibcon#read 4, iclass 36, count 0 2006.286.04:59:53.18#ibcon#about to read 5, iclass 36, count 0 2006.286.04:59:53.18#ibcon#read 5, iclass 36, count 0 2006.286.04:59:53.18#ibcon#about to read 6, iclass 36, count 0 2006.286.04:59:53.18#ibcon#read 6, iclass 36, count 0 2006.286.04:59:53.18#ibcon#end of sib2, iclass 36, count 0 2006.286.04:59:53.18#ibcon#*after write, iclass 36, count 0 2006.286.04:59:53.18#ibcon#*before return 0, iclass 36, count 0 2006.286.04:59:53.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:59:53.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:59:53.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:59:53.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:59:53.18$vck44/valo=6,814.99 2006.286.04:59:53.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.04:59:53.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.04:59:53.18#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:53.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:59:53.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:59:53.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:59:53.18#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:59:53.18#ibcon#first serial, iclass 38, count 0 2006.286.04:59:53.18#ibcon#enter sib2, iclass 38, count 0 2006.286.04:59:53.18#ibcon#flushed, iclass 38, count 0 2006.286.04:59:53.18#ibcon#about to write, iclass 38, count 0 2006.286.04:59:53.18#ibcon#wrote, iclass 38, count 0 2006.286.04:59:53.18#ibcon#about to read 3, iclass 38, count 0 2006.286.04:59:53.20#ibcon#read 3, iclass 38, count 0 2006.286.04:59:53.20#ibcon#about to read 4, iclass 38, count 0 2006.286.04:59:53.20#ibcon#read 4, iclass 38, count 0 2006.286.04:59:53.20#ibcon#about to read 5, iclass 38, count 0 2006.286.04:59:53.20#ibcon#read 5, iclass 38, count 0 2006.286.04:59:53.20#ibcon#about to read 6, iclass 38, count 0 2006.286.04:59:53.20#ibcon#read 6, iclass 38, count 0 2006.286.04:59:53.20#ibcon#end of sib2, iclass 38, count 0 2006.286.04:59:53.20#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:59:53.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:59:53.20#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.04:59:53.20#ibcon#*before write, iclass 38, count 0 2006.286.04:59:53.20#ibcon#enter sib2, iclass 38, count 0 2006.286.04:59:53.20#ibcon#flushed, iclass 38, count 0 2006.286.04:59:53.20#ibcon#about to write, iclass 38, count 0 2006.286.04:59:53.20#ibcon#wrote, iclass 38, count 0 2006.286.04:59:53.20#ibcon#about to read 3, iclass 38, count 0 2006.286.04:59:53.24#ibcon#read 3, iclass 38, count 0 2006.286.04:59:53.24#ibcon#about to read 4, iclass 38, count 0 2006.286.04:59:53.24#ibcon#read 4, iclass 38, count 0 2006.286.04:59:53.24#ibcon#about to read 5, iclass 38, count 0 2006.286.04:59:53.24#ibcon#read 5, iclass 38, count 0 2006.286.04:59:53.24#ibcon#about to read 6, iclass 38, count 0 2006.286.04:59:53.24#ibcon#read 6, iclass 38, count 0 2006.286.04:59:53.24#ibcon#end of sib2, iclass 38, count 0 2006.286.04:59:53.24#ibcon#*after write, iclass 38, count 0 2006.286.04:59:53.24#ibcon#*before return 0, iclass 38, count 0 2006.286.04:59:53.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:59:53.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:59:53.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:59:53.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:59:53.24$vck44/va=6,4 2006.286.04:59:53.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.04:59:53.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.04:59:53.24#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:53.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:59:53.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:59:53.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:59:53.30#ibcon#enter wrdev, iclass 40, count 2 2006.286.04:59:53.30#ibcon#first serial, iclass 40, count 2 2006.286.04:59:53.30#ibcon#enter sib2, iclass 40, count 2 2006.286.04:59:53.30#ibcon#flushed, iclass 40, count 2 2006.286.04:59:53.30#ibcon#about to write, iclass 40, count 2 2006.286.04:59:53.30#ibcon#wrote, iclass 40, count 2 2006.286.04:59:53.30#ibcon#about to read 3, iclass 40, count 2 2006.286.04:59:53.32#ibcon#read 3, iclass 40, count 2 2006.286.04:59:53.32#ibcon#about to read 4, iclass 40, count 2 2006.286.04:59:53.32#ibcon#read 4, iclass 40, count 2 2006.286.04:59:53.32#ibcon#about to read 5, iclass 40, count 2 2006.286.04:59:53.32#ibcon#read 5, iclass 40, count 2 2006.286.04:59:53.32#ibcon#about to read 6, iclass 40, count 2 2006.286.04:59:53.32#ibcon#read 6, iclass 40, count 2 2006.286.04:59:53.32#ibcon#end of sib2, iclass 40, count 2 2006.286.04:59:53.32#ibcon#*mode == 0, iclass 40, count 2 2006.286.04:59:53.32#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.04:59:53.32#ibcon#[25=AT06-04\r\n] 2006.286.04:59:53.32#ibcon#*before write, iclass 40, count 2 2006.286.04:59:53.32#ibcon#enter sib2, iclass 40, count 2 2006.286.04:59:53.32#ibcon#flushed, iclass 40, count 2 2006.286.04:59:53.32#ibcon#about to write, iclass 40, count 2 2006.286.04:59:53.32#ibcon#wrote, iclass 40, count 2 2006.286.04:59:53.32#ibcon#about to read 3, iclass 40, count 2 2006.286.04:59:53.35#ibcon#read 3, iclass 40, count 2 2006.286.04:59:53.35#ibcon#about to read 4, iclass 40, count 2 2006.286.04:59:53.35#ibcon#read 4, iclass 40, count 2 2006.286.04:59:53.35#ibcon#about to read 5, iclass 40, count 2 2006.286.04:59:53.35#ibcon#read 5, iclass 40, count 2 2006.286.04:59:53.35#ibcon#about to read 6, iclass 40, count 2 2006.286.04:59:53.35#ibcon#read 6, iclass 40, count 2 2006.286.04:59:53.35#ibcon#end of sib2, iclass 40, count 2 2006.286.04:59:53.35#ibcon#*after write, iclass 40, count 2 2006.286.04:59:53.35#ibcon#*before return 0, iclass 40, count 2 2006.286.04:59:53.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:59:53.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:59:53.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.04:59:53.35#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:53.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:59:53.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:59:53.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:59:53.47#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:59:53.47#ibcon#first serial, iclass 40, count 0 2006.286.04:59:53.47#ibcon#enter sib2, iclass 40, count 0 2006.286.04:59:53.47#ibcon#flushed, iclass 40, count 0 2006.286.04:59:53.47#ibcon#about to write, iclass 40, count 0 2006.286.04:59:53.47#ibcon#wrote, iclass 40, count 0 2006.286.04:59:53.47#ibcon#about to read 3, iclass 40, count 0 2006.286.04:59:53.49#ibcon#read 3, iclass 40, count 0 2006.286.04:59:53.49#ibcon#about to read 4, iclass 40, count 0 2006.286.04:59:53.49#ibcon#read 4, iclass 40, count 0 2006.286.04:59:53.49#ibcon#about to read 5, iclass 40, count 0 2006.286.04:59:53.49#ibcon#read 5, iclass 40, count 0 2006.286.04:59:53.49#ibcon#about to read 6, iclass 40, count 0 2006.286.04:59:53.49#ibcon#read 6, iclass 40, count 0 2006.286.04:59:53.49#ibcon#end of sib2, iclass 40, count 0 2006.286.04:59:53.49#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:59:53.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:59:53.49#ibcon#[25=USB\r\n] 2006.286.04:59:53.49#ibcon#*before write, iclass 40, count 0 2006.286.04:59:53.49#ibcon#enter sib2, iclass 40, count 0 2006.286.04:59:53.49#ibcon#flushed, iclass 40, count 0 2006.286.04:59:53.49#ibcon#about to write, iclass 40, count 0 2006.286.04:59:53.49#ibcon#wrote, iclass 40, count 0 2006.286.04:59:53.49#ibcon#about to read 3, iclass 40, count 0 2006.286.04:59:53.52#ibcon#read 3, iclass 40, count 0 2006.286.04:59:53.52#ibcon#about to read 4, iclass 40, count 0 2006.286.04:59:53.52#ibcon#read 4, iclass 40, count 0 2006.286.04:59:53.52#ibcon#about to read 5, iclass 40, count 0 2006.286.04:59:53.52#ibcon#read 5, iclass 40, count 0 2006.286.04:59:53.52#ibcon#about to read 6, iclass 40, count 0 2006.286.04:59:53.52#ibcon#read 6, iclass 40, count 0 2006.286.04:59:53.52#ibcon#end of sib2, iclass 40, count 0 2006.286.04:59:53.52#ibcon#*after write, iclass 40, count 0 2006.286.04:59:53.52#ibcon#*before return 0, iclass 40, count 0 2006.286.04:59:53.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:59:53.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:59:53.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:59:53.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:59:53.52$vck44/valo=7,864.99 2006.286.04:59:53.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.04:59:53.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.04:59:53.52#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:53.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:59:53.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:59:53.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:59:53.52#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:59:53.52#ibcon#first serial, iclass 4, count 0 2006.286.04:59:53.52#ibcon#enter sib2, iclass 4, count 0 2006.286.04:59:53.52#ibcon#flushed, iclass 4, count 0 2006.286.04:59:53.52#ibcon#about to write, iclass 4, count 0 2006.286.04:59:53.52#ibcon#wrote, iclass 4, count 0 2006.286.04:59:53.52#ibcon#about to read 3, iclass 4, count 0 2006.286.04:59:53.54#ibcon#read 3, iclass 4, count 0 2006.286.04:59:53.64#ibcon#about to read 4, iclass 4, count 0 2006.286.04:59:53.64#ibcon#read 4, iclass 4, count 0 2006.286.04:59:53.64#ibcon#about to read 5, iclass 4, count 0 2006.286.04:59:53.64#ibcon#read 5, iclass 4, count 0 2006.286.04:59:53.64#ibcon#about to read 6, iclass 4, count 0 2006.286.04:59:53.64#ibcon#read 6, iclass 4, count 0 2006.286.04:59:53.64#ibcon#end of sib2, iclass 4, count 0 2006.286.04:59:53.64#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:59:53.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:59:53.64#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.04:59:53.64#ibcon#*before write, iclass 4, count 0 2006.286.04:59:53.64#ibcon#enter sib2, iclass 4, count 0 2006.286.04:59:53.64#ibcon#flushed, iclass 4, count 0 2006.286.04:59:53.64#ibcon#about to write, iclass 4, count 0 2006.286.04:59:53.64#ibcon#wrote, iclass 4, count 0 2006.286.04:59:53.64#ibcon#about to read 3, iclass 4, count 0 2006.286.04:59:53.68#ibcon#read 3, iclass 4, count 0 2006.286.04:59:53.68#ibcon#about to read 4, iclass 4, count 0 2006.286.04:59:53.68#ibcon#read 4, iclass 4, count 0 2006.286.04:59:53.68#ibcon#about to read 5, iclass 4, count 0 2006.286.04:59:53.68#ibcon#read 5, iclass 4, count 0 2006.286.04:59:53.68#ibcon#about to read 6, iclass 4, count 0 2006.286.04:59:53.68#ibcon#read 6, iclass 4, count 0 2006.286.04:59:53.68#ibcon#end of sib2, iclass 4, count 0 2006.286.04:59:53.68#ibcon#*after write, iclass 4, count 0 2006.286.04:59:53.68#ibcon#*before return 0, iclass 4, count 0 2006.286.04:59:53.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:59:53.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:59:53.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:59:53.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:59:53.68$vck44/va=7,4 2006.286.04:59:53.68#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.04:59:53.68#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.04:59:53.68#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:53.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:59:53.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:59:53.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:59:53.68#ibcon#enter wrdev, iclass 6, count 2 2006.286.04:59:53.68#ibcon#first serial, iclass 6, count 2 2006.286.04:59:53.68#ibcon#enter sib2, iclass 6, count 2 2006.286.04:59:53.68#ibcon#flushed, iclass 6, count 2 2006.286.04:59:53.68#ibcon#about to write, iclass 6, count 2 2006.286.04:59:53.68#ibcon#wrote, iclass 6, count 2 2006.286.04:59:53.68#ibcon#about to read 3, iclass 6, count 2 2006.286.04:59:53.70#ibcon#read 3, iclass 6, count 2 2006.286.04:59:53.70#ibcon#about to read 4, iclass 6, count 2 2006.286.04:59:53.70#ibcon#read 4, iclass 6, count 2 2006.286.04:59:53.70#ibcon#about to read 5, iclass 6, count 2 2006.286.04:59:53.70#ibcon#read 5, iclass 6, count 2 2006.286.04:59:53.70#ibcon#about to read 6, iclass 6, count 2 2006.286.04:59:53.70#ibcon#read 6, iclass 6, count 2 2006.286.04:59:53.70#ibcon#end of sib2, iclass 6, count 2 2006.286.04:59:53.70#ibcon#*mode == 0, iclass 6, count 2 2006.286.04:59:53.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.04:59:53.70#ibcon#[25=AT07-04\r\n] 2006.286.04:59:53.70#ibcon#*before write, iclass 6, count 2 2006.286.04:59:53.70#ibcon#enter sib2, iclass 6, count 2 2006.286.04:59:53.70#ibcon#flushed, iclass 6, count 2 2006.286.04:59:53.70#ibcon#about to write, iclass 6, count 2 2006.286.04:59:53.70#ibcon#wrote, iclass 6, count 2 2006.286.04:59:53.70#ibcon#about to read 3, iclass 6, count 2 2006.286.04:59:53.73#ibcon#read 3, iclass 6, count 2 2006.286.04:59:53.73#ibcon#about to read 4, iclass 6, count 2 2006.286.04:59:53.73#ibcon#read 4, iclass 6, count 2 2006.286.04:59:53.73#ibcon#about to read 5, iclass 6, count 2 2006.286.04:59:53.73#ibcon#read 5, iclass 6, count 2 2006.286.04:59:53.73#ibcon#about to read 6, iclass 6, count 2 2006.286.04:59:53.73#ibcon#read 6, iclass 6, count 2 2006.286.04:59:53.73#ibcon#end of sib2, iclass 6, count 2 2006.286.04:59:53.73#ibcon#*after write, iclass 6, count 2 2006.286.04:59:53.73#ibcon#*before return 0, iclass 6, count 2 2006.286.04:59:53.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:59:53.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:59:53.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.04:59:53.73#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:53.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:59:53.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:59:53.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:59:53.85#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:59:53.85#ibcon#first serial, iclass 6, count 0 2006.286.04:59:53.85#ibcon#enter sib2, iclass 6, count 0 2006.286.04:59:53.85#ibcon#flushed, iclass 6, count 0 2006.286.04:59:53.85#ibcon#about to write, iclass 6, count 0 2006.286.04:59:53.85#ibcon#wrote, iclass 6, count 0 2006.286.04:59:53.85#ibcon#about to read 3, iclass 6, count 0 2006.286.04:59:53.87#ibcon#read 3, iclass 6, count 0 2006.286.04:59:53.87#ibcon#about to read 4, iclass 6, count 0 2006.286.04:59:53.87#ibcon#read 4, iclass 6, count 0 2006.286.04:59:53.87#ibcon#about to read 5, iclass 6, count 0 2006.286.04:59:53.87#ibcon#read 5, iclass 6, count 0 2006.286.04:59:53.87#ibcon#about to read 6, iclass 6, count 0 2006.286.04:59:53.87#ibcon#read 6, iclass 6, count 0 2006.286.04:59:53.87#ibcon#end of sib2, iclass 6, count 0 2006.286.04:59:53.87#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:59:53.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:59:53.87#ibcon#[25=USB\r\n] 2006.286.04:59:53.87#ibcon#*before write, iclass 6, count 0 2006.286.04:59:53.87#ibcon#enter sib2, iclass 6, count 0 2006.286.04:59:53.87#ibcon#flushed, iclass 6, count 0 2006.286.04:59:53.87#ibcon#about to write, iclass 6, count 0 2006.286.04:59:53.87#ibcon#wrote, iclass 6, count 0 2006.286.04:59:53.87#ibcon#about to read 3, iclass 6, count 0 2006.286.04:59:53.90#ibcon#read 3, iclass 6, count 0 2006.286.04:59:53.90#ibcon#about to read 4, iclass 6, count 0 2006.286.04:59:53.90#ibcon#read 4, iclass 6, count 0 2006.286.04:59:53.90#ibcon#about to read 5, iclass 6, count 0 2006.286.04:59:53.90#ibcon#read 5, iclass 6, count 0 2006.286.04:59:53.90#ibcon#about to read 6, iclass 6, count 0 2006.286.04:59:53.90#ibcon#read 6, iclass 6, count 0 2006.286.04:59:53.90#ibcon#end of sib2, iclass 6, count 0 2006.286.04:59:53.90#ibcon#*after write, iclass 6, count 0 2006.286.04:59:53.90#ibcon#*before return 0, iclass 6, count 0 2006.286.04:59:53.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:59:53.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:59:53.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:59:53.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:59:53.90$vck44/valo=8,884.99 2006.286.04:59:53.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.04:59:53.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.04:59:53.90#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:53.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:59:53.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:59:53.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:59:53.90#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:59:53.90#ibcon#first serial, iclass 10, count 0 2006.286.04:59:53.90#ibcon#enter sib2, iclass 10, count 0 2006.286.04:59:53.90#ibcon#flushed, iclass 10, count 0 2006.286.04:59:53.90#ibcon#about to write, iclass 10, count 0 2006.286.04:59:53.90#ibcon#wrote, iclass 10, count 0 2006.286.04:59:53.90#ibcon#about to read 3, iclass 10, count 0 2006.286.04:59:53.92#ibcon#read 3, iclass 10, count 0 2006.286.04:59:53.92#ibcon#about to read 4, iclass 10, count 0 2006.286.04:59:53.92#ibcon#read 4, iclass 10, count 0 2006.286.04:59:53.92#ibcon#about to read 5, iclass 10, count 0 2006.286.04:59:53.92#ibcon#read 5, iclass 10, count 0 2006.286.04:59:53.92#ibcon#about to read 6, iclass 10, count 0 2006.286.04:59:53.92#ibcon#read 6, iclass 10, count 0 2006.286.04:59:53.92#ibcon#end of sib2, iclass 10, count 0 2006.286.04:59:53.92#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:59:53.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:59:53.92#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.04:59:53.92#ibcon#*before write, iclass 10, count 0 2006.286.04:59:53.92#ibcon#enter sib2, iclass 10, count 0 2006.286.04:59:53.92#ibcon#flushed, iclass 10, count 0 2006.286.04:59:53.92#ibcon#about to write, iclass 10, count 0 2006.286.04:59:53.92#ibcon#wrote, iclass 10, count 0 2006.286.04:59:53.92#ibcon#about to read 3, iclass 10, count 0 2006.286.04:59:53.96#ibcon#read 3, iclass 10, count 0 2006.286.04:59:53.96#ibcon#about to read 4, iclass 10, count 0 2006.286.04:59:53.96#ibcon#read 4, iclass 10, count 0 2006.286.04:59:53.96#ibcon#about to read 5, iclass 10, count 0 2006.286.04:59:53.96#ibcon#read 5, iclass 10, count 0 2006.286.04:59:53.96#ibcon#about to read 6, iclass 10, count 0 2006.286.04:59:53.96#ibcon#read 6, iclass 10, count 0 2006.286.04:59:53.96#ibcon#end of sib2, iclass 10, count 0 2006.286.04:59:53.96#ibcon#*after write, iclass 10, count 0 2006.286.04:59:53.96#ibcon#*before return 0, iclass 10, count 0 2006.286.04:59:53.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:59:53.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:59:53.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:59:53.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:59:53.96$vck44/va=8,3 2006.286.04:59:53.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.04:59:53.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.04:59:53.96#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:53.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:59:54.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:59:54.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:59:54.02#ibcon#enter wrdev, iclass 12, count 2 2006.286.04:59:54.02#ibcon#first serial, iclass 12, count 2 2006.286.04:59:54.02#ibcon#enter sib2, iclass 12, count 2 2006.286.04:59:54.02#ibcon#flushed, iclass 12, count 2 2006.286.04:59:54.02#ibcon#about to write, iclass 12, count 2 2006.286.04:59:54.02#ibcon#wrote, iclass 12, count 2 2006.286.04:59:54.02#ibcon#about to read 3, iclass 12, count 2 2006.286.04:59:54.04#ibcon#read 3, iclass 12, count 2 2006.286.04:59:54.04#ibcon#about to read 4, iclass 12, count 2 2006.286.04:59:54.04#ibcon#read 4, iclass 12, count 2 2006.286.04:59:54.04#ibcon#about to read 5, iclass 12, count 2 2006.286.04:59:54.04#ibcon#read 5, iclass 12, count 2 2006.286.04:59:54.04#ibcon#about to read 6, iclass 12, count 2 2006.286.04:59:54.04#ibcon#read 6, iclass 12, count 2 2006.286.04:59:54.04#ibcon#end of sib2, iclass 12, count 2 2006.286.04:59:54.04#ibcon#*mode == 0, iclass 12, count 2 2006.286.04:59:54.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.04:59:54.04#ibcon#[25=AT08-03\r\n] 2006.286.04:59:54.04#ibcon#*before write, iclass 12, count 2 2006.286.04:59:54.04#ibcon#enter sib2, iclass 12, count 2 2006.286.04:59:54.04#ibcon#flushed, iclass 12, count 2 2006.286.04:59:54.04#ibcon#about to write, iclass 12, count 2 2006.286.04:59:54.04#ibcon#wrote, iclass 12, count 2 2006.286.04:59:54.04#ibcon#about to read 3, iclass 12, count 2 2006.286.04:59:54.07#ibcon#read 3, iclass 12, count 2 2006.286.04:59:54.07#ibcon#about to read 4, iclass 12, count 2 2006.286.04:59:54.07#ibcon#read 4, iclass 12, count 2 2006.286.04:59:54.07#ibcon#about to read 5, iclass 12, count 2 2006.286.04:59:54.07#ibcon#read 5, iclass 12, count 2 2006.286.04:59:54.07#ibcon#about to read 6, iclass 12, count 2 2006.286.04:59:54.07#ibcon#read 6, iclass 12, count 2 2006.286.04:59:54.07#ibcon#end of sib2, iclass 12, count 2 2006.286.04:59:54.07#ibcon#*after write, iclass 12, count 2 2006.286.04:59:54.07#ibcon#*before return 0, iclass 12, count 2 2006.286.04:59:54.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:59:54.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.04:59:54.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.04:59:54.07#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:54.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:59:54.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:59:54.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:59:54.19#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:59:54.19#ibcon#first serial, iclass 12, count 0 2006.286.04:59:54.19#ibcon#enter sib2, iclass 12, count 0 2006.286.04:59:54.19#ibcon#flushed, iclass 12, count 0 2006.286.04:59:54.19#ibcon#about to write, iclass 12, count 0 2006.286.04:59:54.19#ibcon#wrote, iclass 12, count 0 2006.286.04:59:54.19#ibcon#about to read 3, iclass 12, count 0 2006.286.04:59:54.21#ibcon#read 3, iclass 12, count 0 2006.286.04:59:54.21#ibcon#about to read 4, iclass 12, count 0 2006.286.04:59:54.21#ibcon#read 4, iclass 12, count 0 2006.286.04:59:54.21#ibcon#about to read 5, iclass 12, count 0 2006.286.04:59:54.21#ibcon#read 5, iclass 12, count 0 2006.286.04:59:54.21#ibcon#about to read 6, iclass 12, count 0 2006.286.04:59:54.21#ibcon#read 6, iclass 12, count 0 2006.286.04:59:54.21#ibcon#end of sib2, iclass 12, count 0 2006.286.04:59:54.21#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:59:54.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:59:54.21#ibcon#[25=USB\r\n] 2006.286.04:59:54.21#ibcon#*before write, iclass 12, count 0 2006.286.04:59:54.21#ibcon#enter sib2, iclass 12, count 0 2006.286.04:59:54.21#ibcon#flushed, iclass 12, count 0 2006.286.04:59:54.21#ibcon#about to write, iclass 12, count 0 2006.286.04:59:54.21#ibcon#wrote, iclass 12, count 0 2006.286.04:59:54.21#ibcon#about to read 3, iclass 12, count 0 2006.286.04:59:54.24#ibcon#read 3, iclass 12, count 0 2006.286.04:59:54.24#ibcon#about to read 4, iclass 12, count 0 2006.286.04:59:54.24#ibcon#read 4, iclass 12, count 0 2006.286.04:59:54.24#ibcon#about to read 5, iclass 12, count 0 2006.286.04:59:54.24#ibcon#read 5, iclass 12, count 0 2006.286.04:59:54.24#ibcon#about to read 6, iclass 12, count 0 2006.286.04:59:54.24#ibcon#read 6, iclass 12, count 0 2006.286.04:59:54.24#ibcon#end of sib2, iclass 12, count 0 2006.286.04:59:54.24#ibcon#*after write, iclass 12, count 0 2006.286.04:59:54.24#ibcon#*before return 0, iclass 12, count 0 2006.286.04:59:54.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:59:54.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.04:59:54.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:59:54.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:59:54.24$vck44/vblo=1,629.99 2006.286.04:59:54.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.04:59:54.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.04:59:54.24#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:54.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:59:54.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:59:54.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:59:54.24#ibcon#enter wrdev, iclass 14, count 0 2006.286.04:59:54.24#ibcon#first serial, iclass 14, count 0 2006.286.04:59:54.24#ibcon#enter sib2, iclass 14, count 0 2006.286.04:59:54.24#ibcon#flushed, iclass 14, count 0 2006.286.04:59:54.24#ibcon#about to write, iclass 14, count 0 2006.286.04:59:54.24#ibcon#wrote, iclass 14, count 0 2006.286.04:59:54.24#ibcon#about to read 3, iclass 14, count 0 2006.286.04:59:54.26#ibcon#read 3, iclass 14, count 0 2006.286.04:59:54.26#ibcon#about to read 4, iclass 14, count 0 2006.286.04:59:54.26#ibcon#read 4, iclass 14, count 0 2006.286.04:59:54.26#ibcon#about to read 5, iclass 14, count 0 2006.286.04:59:54.26#ibcon#read 5, iclass 14, count 0 2006.286.04:59:54.26#ibcon#about to read 6, iclass 14, count 0 2006.286.04:59:54.26#ibcon#read 6, iclass 14, count 0 2006.286.04:59:54.26#ibcon#end of sib2, iclass 14, count 0 2006.286.04:59:54.26#ibcon#*mode == 0, iclass 14, count 0 2006.286.04:59:54.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.04:59:54.26#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.04:59:54.26#ibcon#*before write, iclass 14, count 0 2006.286.04:59:54.26#ibcon#enter sib2, iclass 14, count 0 2006.286.04:59:54.26#ibcon#flushed, iclass 14, count 0 2006.286.04:59:54.26#ibcon#about to write, iclass 14, count 0 2006.286.04:59:54.26#ibcon#wrote, iclass 14, count 0 2006.286.04:59:54.26#ibcon#about to read 3, iclass 14, count 0 2006.286.04:59:54.30#ibcon#read 3, iclass 14, count 0 2006.286.04:59:54.30#ibcon#about to read 4, iclass 14, count 0 2006.286.04:59:54.30#ibcon#read 4, iclass 14, count 0 2006.286.04:59:54.30#ibcon#about to read 5, iclass 14, count 0 2006.286.04:59:54.30#ibcon#read 5, iclass 14, count 0 2006.286.04:59:54.30#ibcon#about to read 6, iclass 14, count 0 2006.286.04:59:54.30#ibcon#read 6, iclass 14, count 0 2006.286.04:59:54.30#ibcon#end of sib2, iclass 14, count 0 2006.286.04:59:54.30#ibcon#*after write, iclass 14, count 0 2006.286.04:59:54.30#ibcon#*before return 0, iclass 14, count 0 2006.286.04:59:54.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:59:54.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.04:59:54.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.04:59:54.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.04:59:54.30$vck44/vb=1,4 2006.286.04:59:54.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.04:59:54.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.04:59:54.30#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:54.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:59:54.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:59:54.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:59:54.30#ibcon#enter wrdev, iclass 16, count 2 2006.286.04:59:54.30#ibcon#first serial, iclass 16, count 2 2006.286.04:59:54.30#ibcon#enter sib2, iclass 16, count 2 2006.286.04:59:54.30#ibcon#flushed, iclass 16, count 2 2006.286.04:59:54.30#ibcon#about to write, iclass 16, count 2 2006.286.04:59:54.30#ibcon#wrote, iclass 16, count 2 2006.286.04:59:54.30#ibcon#about to read 3, iclass 16, count 2 2006.286.04:59:54.32#ibcon#read 3, iclass 16, count 2 2006.286.04:59:54.32#ibcon#about to read 4, iclass 16, count 2 2006.286.04:59:54.32#ibcon#read 4, iclass 16, count 2 2006.286.04:59:54.32#ibcon#about to read 5, iclass 16, count 2 2006.286.04:59:54.32#ibcon#read 5, iclass 16, count 2 2006.286.04:59:54.32#ibcon#about to read 6, iclass 16, count 2 2006.286.04:59:54.32#ibcon#read 6, iclass 16, count 2 2006.286.04:59:54.32#ibcon#end of sib2, iclass 16, count 2 2006.286.04:59:54.32#ibcon#*mode == 0, iclass 16, count 2 2006.286.04:59:54.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.04:59:54.32#ibcon#[27=AT01-04\r\n] 2006.286.04:59:54.32#ibcon#*before write, iclass 16, count 2 2006.286.04:59:54.32#ibcon#enter sib2, iclass 16, count 2 2006.286.04:59:54.32#ibcon#flushed, iclass 16, count 2 2006.286.04:59:54.32#ibcon#about to write, iclass 16, count 2 2006.286.04:59:54.32#ibcon#wrote, iclass 16, count 2 2006.286.04:59:54.32#ibcon#about to read 3, iclass 16, count 2 2006.286.04:59:54.35#ibcon#read 3, iclass 16, count 2 2006.286.04:59:54.35#ibcon#about to read 4, iclass 16, count 2 2006.286.04:59:54.35#ibcon#read 4, iclass 16, count 2 2006.286.04:59:54.35#ibcon#about to read 5, iclass 16, count 2 2006.286.04:59:54.35#ibcon#read 5, iclass 16, count 2 2006.286.04:59:54.35#ibcon#about to read 6, iclass 16, count 2 2006.286.04:59:54.35#ibcon#read 6, iclass 16, count 2 2006.286.04:59:54.35#ibcon#end of sib2, iclass 16, count 2 2006.286.04:59:54.35#ibcon#*after write, iclass 16, count 2 2006.286.04:59:54.35#ibcon#*before return 0, iclass 16, count 2 2006.286.04:59:54.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:59:54.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.04:59:54.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.04:59:54.35#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:54.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:59:54.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:59:54.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:59:54.47#ibcon#enter wrdev, iclass 16, count 0 2006.286.04:59:54.47#ibcon#first serial, iclass 16, count 0 2006.286.04:59:54.47#ibcon#enter sib2, iclass 16, count 0 2006.286.04:59:54.47#ibcon#flushed, iclass 16, count 0 2006.286.04:59:54.47#ibcon#about to write, iclass 16, count 0 2006.286.04:59:54.47#ibcon#wrote, iclass 16, count 0 2006.286.04:59:54.47#ibcon#about to read 3, iclass 16, count 0 2006.286.04:59:54.49#ibcon#read 3, iclass 16, count 0 2006.286.04:59:54.49#ibcon#about to read 4, iclass 16, count 0 2006.286.04:59:54.49#ibcon#read 4, iclass 16, count 0 2006.286.04:59:54.49#ibcon#about to read 5, iclass 16, count 0 2006.286.04:59:54.49#ibcon#read 5, iclass 16, count 0 2006.286.04:59:54.49#ibcon#about to read 6, iclass 16, count 0 2006.286.04:59:54.49#ibcon#read 6, iclass 16, count 0 2006.286.04:59:54.49#ibcon#end of sib2, iclass 16, count 0 2006.286.04:59:54.49#ibcon#*mode == 0, iclass 16, count 0 2006.286.04:59:54.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.04:59:54.49#ibcon#[27=USB\r\n] 2006.286.04:59:54.49#ibcon#*before write, iclass 16, count 0 2006.286.04:59:54.49#ibcon#enter sib2, iclass 16, count 0 2006.286.04:59:54.49#ibcon#flushed, iclass 16, count 0 2006.286.04:59:54.49#ibcon#about to write, iclass 16, count 0 2006.286.04:59:54.49#ibcon#wrote, iclass 16, count 0 2006.286.04:59:54.49#ibcon#about to read 3, iclass 16, count 0 2006.286.04:59:54.52#ibcon#read 3, iclass 16, count 0 2006.286.04:59:54.52#ibcon#about to read 4, iclass 16, count 0 2006.286.04:59:54.52#ibcon#read 4, iclass 16, count 0 2006.286.04:59:54.52#ibcon#about to read 5, iclass 16, count 0 2006.286.04:59:54.52#ibcon#read 5, iclass 16, count 0 2006.286.04:59:54.52#ibcon#about to read 6, iclass 16, count 0 2006.286.04:59:54.52#ibcon#read 6, iclass 16, count 0 2006.286.04:59:54.52#ibcon#end of sib2, iclass 16, count 0 2006.286.04:59:54.52#ibcon#*after write, iclass 16, count 0 2006.286.04:59:54.52#ibcon#*before return 0, iclass 16, count 0 2006.286.04:59:54.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:59:54.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.04:59:54.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.04:59:54.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.04:59:54.52$vck44/vblo=2,634.99 2006.286.04:59:54.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.04:59:54.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.04:59:54.52#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:54.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:59:54.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:59:54.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:59:54.52#ibcon#enter wrdev, iclass 18, count 0 2006.286.04:59:54.52#ibcon#first serial, iclass 18, count 0 2006.286.04:59:54.52#ibcon#enter sib2, iclass 18, count 0 2006.286.04:59:54.52#ibcon#flushed, iclass 18, count 0 2006.286.04:59:54.52#ibcon#about to write, iclass 18, count 0 2006.286.04:59:54.52#ibcon#wrote, iclass 18, count 0 2006.286.04:59:54.52#ibcon#about to read 3, iclass 18, count 0 2006.286.04:59:54.54#ibcon#read 3, iclass 18, count 0 2006.286.04:59:54.68#ibcon#about to read 4, iclass 18, count 0 2006.286.04:59:54.68#ibcon#read 4, iclass 18, count 0 2006.286.04:59:54.68#ibcon#about to read 5, iclass 18, count 0 2006.286.04:59:54.68#ibcon#read 5, iclass 18, count 0 2006.286.04:59:54.68#ibcon#about to read 6, iclass 18, count 0 2006.286.04:59:54.68#ibcon#read 6, iclass 18, count 0 2006.286.04:59:54.68#ibcon#end of sib2, iclass 18, count 0 2006.286.04:59:54.68#ibcon#*mode == 0, iclass 18, count 0 2006.286.04:59:54.68#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.04:59:54.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.04:59:54.68#ibcon#*before write, iclass 18, count 0 2006.286.04:59:54.68#ibcon#enter sib2, iclass 18, count 0 2006.286.04:59:54.68#ibcon#flushed, iclass 18, count 0 2006.286.04:59:54.68#ibcon#about to write, iclass 18, count 0 2006.286.04:59:54.68#ibcon#wrote, iclass 18, count 0 2006.286.04:59:54.68#ibcon#about to read 3, iclass 18, count 0 2006.286.04:59:54.72#ibcon#read 3, iclass 18, count 0 2006.286.04:59:54.72#ibcon#about to read 4, iclass 18, count 0 2006.286.04:59:54.72#ibcon#read 4, iclass 18, count 0 2006.286.04:59:54.72#ibcon#about to read 5, iclass 18, count 0 2006.286.04:59:54.72#ibcon#read 5, iclass 18, count 0 2006.286.04:59:54.72#ibcon#about to read 6, iclass 18, count 0 2006.286.04:59:54.72#ibcon#read 6, iclass 18, count 0 2006.286.04:59:54.72#ibcon#end of sib2, iclass 18, count 0 2006.286.04:59:54.72#ibcon#*after write, iclass 18, count 0 2006.286.04:59:54.72#ibcon#*before return 0, iclass 18, count 0 2006.286.04:59:54.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:59:54.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.04:59:54.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.04:59:54.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.04:59:54.72$vck44/vb=2,5 2006.286.04:59:54.72#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.04:59:54.72#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.04:59:54.72#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:54.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:59:54.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:59:54.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:59:54.72#ibcon#enter wrdev, iclass 20, count 2 2006.286.04:59:54.72#ibcon#first serial, iclass 20, count 2 2006.286.04:59:54.72#ibcon#enter sib2, iclass 20, count 2 2006.286.04:59:54.72#ibcon#flushed, iclass 20, count 2 2006.286.04:59:54.72#ibcon#about to write, iclass 20, count 2 2006.286.04:59:54.72#ibcon#wrote, iclass 20, count 2 2006.286.04:59:54.72#ibcon#about to read 3, iclass 20, count 2 2006.286.04:59:54.74#ibcon#read 3, iclass 20, count 2 2006.286.04:59:54.74#ibcon#about to read 4, iclass 20, count 2 2006.286.04:59:54.74#ibcon#read 4, iclass 20, count 2 2006.286.04:59:54.74#ibcon#about to read 5, iclass 20, count 2 2006.286.04:59:54.74#ibcon#read 5, iclass 20, count 2 2006.286.04:59:54.74#ibcon#about to read 6, iclass 20, count 2 2006.286.04:59:54.74#ibcon#read 6, iclass 20, count 2 2006.286.04:59:54.74#ibcon#end of sib2, iclass 20, count 2 2006.286.04:59:54.74#ibcon#*mode == 0, iclass 20, count 2 2006.286.04:59:54.74#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.04:59:54.74#ibcon#[27=AT02-05\r\n] 2006.286.04:59:54.74#ibcon#*before write, iclass 20, count 2 2006.286.04:59:54.74#ibcon#enter sib2, iclass 20, count 2 2006.286.04:59:54.74#ibcon#flushed, iclass 20, count 2 2006.286.04:59:54.74#ibcon#about to write, iclass 20, count 2 2006.286.04:59:54.74#ibcon#wrote, iclass 20, count 2 2006.286.04:59:54.74#ibcon#about to read 3, iclass 20, count 2 2006.286.04:59:54.77#ibcon#read 3, iclass 20, count 2 2006.286.04:59:54.77#ibcon#about to read 4, iclass 20, count 2 2006.286.04:59:54.77#ibcon#read 4, iclass 20, count 2 2006.286.04:59:54.77#ibcon#about to read 5, iclass 20, count 2 2006.286.04:59:54.77#ibcon#read 5, iclass 20, count 2 2006.286.04:59:54.77#ibcon#about to read 6, iclass 20, count 2 2006.286.04:59:54.77#ibcon#read 6, iclass 20, count 2 2006.286.04:59:54.77#ibcon#end of sib2, iclass 20, count 2 2006.286.04:59:54.77#ibcon#*after write, iclass 20, count 2 2006.286.04:59:54.77#ibcon#*before return 0, iclass 20, count 2 2006.286.04:59:54.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:59:54.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.04:59:54.77#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.04:59:54.77#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:54.77#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:59:54.89#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:59:54.89#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:59:54.89#ibcon#enter wrdev, iclass 20, count 0 2006.286.04:59:54.89#ibcon#first serial, iclass 20, count 0 2006.286.04:59:54.89#ibcon#enter sib2, iclass 20, count 0 2006.286.04:59:54.89#ibcon#flushed, iclass 20, count 0 2006.286.04:59:54.89#ibcon#about to write, iclass 20, count 0 2006.286.04:59:54.89#ibcon#wrote, iclass 20, count 0 2006.286.04:59:54.89#ibcon#about to read 3, iclass 20, count 0 2006.286.04:59:54.91#ibcon#read 3, iclass 20, count 0 2006.286.04:59:54.91#ibcon#about to read 4, iclass 20, count 0 2006.286.04:59:54.91#ibcon#read 4, iclass 20, count 0 2006.286.04:59:54.91#ibcon#about to read 5, iclass 20, count 0 2006.286.04:59:54.91#ibcon#read 5, iclass 20, count 0 2006.286.04:59:54.91#ibcon#about to read 6, iclass 20, count 0 2006.286.04:59:54.91#ibcon#read 6, iclass 20, count 0 2006.286.04:59:54.91#ibcon#end of sib2, iclass 20, count 0 2006.286.04:59:54.91#ibcon#*mode == 0, iclass 20, count 0 2006.286.04:59:54.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.04:59:54.91#ibcon#[27=USB\r\n] 2006.286.04:59:54.91#ibcon#*before write, iclass 20, count 0 2006.286.04:59:54.91#ibcon#enter sib2, iclass 20, count 0 2006.286.04:59:54.91#ibcon#flushed, iclass 20, count 0 2006.286.04:59:54.91#ibcon#about to write, iclass 20, count 0 2006.286.04:59:54.91#ibcon#wrote, iclass 20, count 0 2006.286.04:59:54.91#ibcon#about to read 3, iclass 20, count 0 2006.286.04:59:54.94#ibcon#read 3, iclass 20, count 0 2006.286.04:59:54.94#ibcon#about to read 4, iclass 20, count 0 2006.286.04:59:54.94#ibcon#read 4, iclass 20, count 0 2006.286.04:59:54.94#ibcon#about to read 5, iclass 20, count 0 2006.286.04:59:54.94#ibcon#read 5, iclass 20, count 0 2006.286.04:59:54.94#ibcon#about to read 6, iclass 20, count 0 2006.286.04:59:54.94#ibcon#read 6, iclass 20, count 0 2006.286.04:59:54.94#ibcon#end of sib2, iclass 20, count 0 2006.286.04:59:54.94#ibcon#*after write, iclass 20, count 0 2006.286.04:59:54.94#ibcon#*before return 0, iclass 20, count 0 2006.286.04:59:54.94#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:59:54.94#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.04:59:54.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.04:59:54.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.04:59:54.94$vck44/vblo=3,649.99 2006.286.04:59:54.94#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.04:59:54.94#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.04:59:54.94#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:54.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:59:54.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:59:54.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:59:54.94#ibcon#enter wrdev, iclass 22, count 0 2006.286.04:59:54.94#ibcon#first serial, iclass 22, count 0 2006.286.04:59:54.94#ibcon#enter sib2, iclass 22, count 0 2006.286.04:59:54.94#ibcon#flushed, iclass 22, count 0 2006.286.04:59:54.94#ibcon#about to write, iclass 22, count 0 2006.286.04:59:54.94#ibcon#wrote, iclass 22, count 0 2006.286.04:59:54.94#ibcon#about to read 3, iclass 22, count 0 2006.286.04:59:54.96#ibcon#read 3, iclass 22, count 0 2006.286.04:59:54.96#ibcon#about to read 4, iclass 22, count 0 2006.286.04:59:54.96#ibcon#read 4, iclass 22, count 0 2006.286.04:59:54.96#ibcon#about to read 5, iclass 22, count 0 2006.286.04:59:54.96#ibcon#read 5, iclass 22, count 0 2006.286.04:59:54.96#ibcon#about to read 6, iclass 22, count 0 2006.286.04:59:54.96#ibcon#read 6, iclass 22, count 0 2006.286.04:59:54.96#ibcon#end of sib2, iclass 22, count 0 2006.286.04:59:54.96#ibcon#*mode == 0, iclass 22, count 0 2006.286.04:59:54.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.04:59:54.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.04:59:54.96#ibcon#*before write, iclass 22, count 0 2006.286.04:59:54.96#ibcon#enter sib2, iclass 22, count 0 2006.286.04:59:54.96#ibcon#flushed, iclass 22, count 0 2006.286.04:59:54.96#ibcon#about to write, iclass 22, count 0 2006.286.04:59:54.96#ibcon#wrote, iclass 22, count 0 2006.286.04:59:54.96#ibcon#about to read 3, iclass 22, count 0 2006.286.04:59:55.00#ibcon#read 3, iclass 22, count 0 2006.286.04:59:55.00#ibcon#about to read 4, iclass 22, count 0 2006.286.04:59:55.00#ibcon#read 4, iclass 22, count 0 2006.286.04:59:55.00#ibcon#about to read 5, iclass 22, count 0 2006.286.04:59:55.00#ibcon#read 5, iclass 22, count 0 2006.286.04:59:55.00#ibcon#about to read 6, iclass 22, count 0 2006.286.04:59:55.00#ibcon#read 6, iclass 22, count 0 2006.286.04:59:55.00#ibcon#end of sib2, iclass 22, count 0 2006.286.04:59:55.00#ibcon#*after write, iclass 22, count 0 2006.286.04:59:55.00#ibcon#*before return 0, iclass 22, count 0 2006.286.04:59:55.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:59:55.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.04:59:55.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.04:59:55.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.04:59:55.00$vck44/vb=3,4 2006.286.04:59:55.00#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.04:59:55.00#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.04:59:55.00#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:55.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:59:55.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:59:55.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:59:55.06#ibcon#enter wrdev, iclass 24, count 2 2006.286.04:59:55.06#ibcon#first serial, iclass 24, count 2 2006.286.04:59:55.06#ibcon#enter sib2, iclass 24, count 2 2006.286.04:59:55.06#ibcon#flushed, iclass 24, count 2 2006.286.04:59:55.06#ibcon#about to write, iclass 24, count 2 2006.286.04:59:55.06#ibcon#wrote, iclass 24, count 2 2006.286.04:59:55.06#ibcon#about to read 3, iclass 24, count 2 2006.286.04:59:55.08#ibcon#read 3, iclass 24, count 2 2006.286.04:59:55.08#ibcon#about to read 4, iclass 24, count 2 2006.286.04:59:55.08#ibcon#read 4, iclass 24, count 2 2006.286.04:59:55.08#ibcon#about to read 5, iclass 24, count 2 2006.286.04:59:55.08#ibcon#read 5, iclass 24, count 2 2006.286.04:59:55.08#ibcon#about to read 6, iclass 24, count 2 2006.286.04:59:55.08#ibcon#read 6, iclass 24, count 2 2006.286.04:59:55.08#ibcon#end of sib2, iclass 24, count 2 2006.286.04:59:55.08#ibcon#*mode == 0, iclass 24, count 2 2006.286.04:59:55.08#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.04:59:55.08#ibcon#[27=AT03-04\r\n] 2006.286.04:59:55.08#ibcon#*before write, iclass 24, count 2 2006.286.04:59:55.08#ibcon#enter sib2, iclass 24, count 2 2006.286.04:59:55.08#ibcon#flushed, iclass 24, count 2 2006.286.04:59:55.08#ibcon#about to write, iclass 24, count 2 2006.286.04:59:55.08#ibcon#wrote, iclass 24, count 2 2006.286.04:59:55.08#ibcon#about to read 3, iclass 24, count 2 2006.286.04:59:55.11#ibcon#read 3, iclass 24, count 2 2006.286.04:59:55.11#ibcon#about to read 4, iclass 24, count 2 2006.286.04:59:55.11#ibcon#read 4, iclass 24, count 2 2006.286.04:59:55.11#ibcon#about to read 5, iclass 24, count 2 2006.286.04:59:55.11#ibcon#read 5, iclass 24, count 2 2006.286.04:59:55.11#ibcon#about to read 6, iclass 24, count 2 2006.286.04:59:55.11#ibcon#read 6, iclass 24, count 2 2006.286.04:59:55.11#ibcon#end of sib2, iclass 24, count 2 2006.286.04:59:55.11#ibcon#*after write, iclass 24, count 2 2006.286.04:59:55.11#ibcon#*before return 0, iclass 24, count 2 2006.286.04:59:55.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:59:55.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.04:59:55.11#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.04:59:55.11#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:55.11#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:59:55.23#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:59:55.23#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:59:55.23#ibcon#enter wrdev, iclass 24, count 0 2006.286.04:59:55.23#ibcon#first serial, iclass 24, count 0 2006.286.04:59:55.23#ibcon#enter sib2, iclass 24, count 0 2006.286.04:59:55.23#ibcon#flushed, iclass 24, count 0 2006.286.04:59:55.23#ibcon#about to write, iclass 24, count 0 2006.286.04:59:55.23#ibcon#wrote, iclass 24, count 0 2006.286.04:59:55.23#ibcon#about to read 3, iclass 24, count 0 2006.286.04:59:55.25#ibcon#read 3, iclass 24, count 0 2006.286.04:59:55.25#ibcon#about to read 4, iclass 24, count 0 2006.286.04:59:55.25#ibcon#read 4, iclass 24, count 0 2006.286.04:59:55.25#ibcon#about to read 5, iclass 24, count 0 2006.286.04:59:55.25#ibcon#read 5, iclass 24, count 0 2006.286.04:59:55.25#ibcon#about to read 6, iclass 24, count 0 2006.286.04:59:55.25#ibcon#read 6, iclass 24, count 0 2006.286.04:59:55.25#ibcon#end of sib2, iclass 24, count 0 2006.286.04:59:55.25#ibcon#*mode == 0, iclass 24, count 0 2006.286.04:59:55.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.04:59:55.25#ibcon#[27=USB\r\n] 2006.286.04:59:55.25#ibcon#*before write, iclass 24, count 0 2006.286.04:59:55.25#ibcon#enter sib2, iclass 24, count 0 2006.286.04:59:55.25#ibcon#flushed, iclass 24, count 0 2006.286.04:59:55.25#ibcon#about to write, iclass 24, count 0 2006.286.04:59:55.25#ibcon#wrote, iclass 24, count 0 2006.286.04:59:55.25#ibcon#about to read 3, iclass 24, count 0 2006.286.04:59:55.28#ibcon#read 3, iclass 24, count 0 2006.286.04:59:55.28#ibcon#about to read 4, iclass 24, count 0 2006.286.04:59:55.28#ibcon#read 4, iclass 24, count 0 2006.286.04:59:55.28#ibcon#about to read 5, iclass 24, count 0 2006.286.04:59:55.28#ibcon#read 5, iclass 24, count 0 2006.286.04:59:55.28#ibcon#about to read 6, iclass 24, count 0 2006.286.04:59:55.28#ibcon#read 6, iclass 24, count 0 2006.286.04:59:55.28#ibcon#end of sib2, iclass 24, count 0 2006.286.04:59:55.28#ibcon#*after write, iclass 24, count 0 2006.286.04:59:55.28#ibcon#*before return 0, iclass 24, count 0 2006.286.04:59:55.28#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:59:55.28#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.04:59:55.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.04:59:55.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.04:59:55.28$vck44/vblo=4,679.99 2006.286.04:59:55.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.04:59:55.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.04:59:55.28#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:55.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:59:55.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:59:55.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:59:55.28#ibcon#enter wrdev, iclass 26, count 0 2006.286.04:59:55.28#ibcon#first serial, iclass 26, count 0 2006.286.04:59:55.28#ibcon#enter sib2, iclass 26, count 0 2006.286.04:59:55.28#ibcon#flushed, iclass 26, count 0 2006.286.04:59:55.28#ibcon#about to write, iclass 26, count 0 2006.286.04:59:55.28#ibcon#wrote, iclass 26, count 0 2006.286.04:59:55.28#ibcon#about to read 3, iclass 26, count 0 2006.286.04:59:55.30#ibcon#read 3, iclass 26, count 0 2006.286.04:59:55.30#ibcon#about to read 4, iclass 26, count 0 2006.286.04:59:55.30#ibcon#read 4, iclass 26, count 0 2006.286.04:59:55.30#ibcon#about to read 5, iclass 26, count 0 2006.286.04:59:55.30#ibcon#read 5, iclass 26, count 0 2006.286.04:59:55.30#ibcon#about to read 6, iclass 26, count 0 2006.286.04:59:55.30#ibcon#read 6, iclass 26, count 0 2006.286.04:59:55.30#ibcon#end of sib2, iclass 26, count 0 2006.286.04:59:55.30#ibcon#*mode == 0, iclass 26, count 0 2006.286.04:59:55.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.04:59:55.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.04:59:55.30#ibcon#*before write, iclass 26, count 0 2006.286.04:59:55.30#ibcon#enter sib2, iclass 26, count 0 2006.286.04:59:55.30#ibcon#flushed, iclass 26, count 0 2006.286.04:59:55.30#ibcon#about to write, iclass 26, count 0 2006.286.04:59:55.30#ibcon#wrote, iclass 26, count 0 2006.286.04:59:55.30#ibcon#about to read 3, iclass 26, count 0 2006.286.04:59:55.34#ibcon#read 3, iclass 26, count 0 2006.286.04:59:55.34#ibcon#about to read 4, iclass 26, count 0 2006.286.04:59:55.34#ibcon#read 4, iclass 26, count 0 2006.286.04:59:55.34#ibcon#about to read 5, iclass 26, count 0 2006.286.04:59:55.34#ibcon#read 5, iclass 26, count 0 2006.286.04:59:55.34#ibcon#about to read 6, iclass 26, count 0 2006.286.04:59:55.34#ibcon#read 6, iclass 26, count 0 2006.286.04:59:55.34#ibcon#end of sib2, iclass 26, count 0 2006.286.04:59:55.34#ibcon#*after write, iclass 26, count 0 2006.286.04:59:55.34#ibcon#*before return 0, iclass 26, count 0 2006.286.04:59:55.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:59:55.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.04:59:55.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.04:59:55.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.04:59:55.34$vck44/vb=4,5 2006.286.04:59:55.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.04:59:55.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.04:59:55.34#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:55.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:59:55.40#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:59:55.40#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:59:55.40#ibcon#enter wrdev, iclass 28, count 2 2006.286.04:59:55.40#ibcon#first serial, iclass 28, count 2 2006.286.04:59:55.40#ibcon#enter sib2, iclass 28, count 2 2006.286.04:59:55.40#ibcon#flushed, iclass 28, count 2 2006.286.04:59:55.40#ibcon#about to write, iclass 28, count 2 2006.286.04:59:55.40#ibcon#wrote, iclass 28, count 2 2006.286.04:59:55.40#ibcon#about to read 3, iclass 28, count 2 2006.286.04:59:55.42#ibcon#read 3, iclass 28, count 2 2006.286.04:59:55.42#ibcon#about to read 4, iclass 28, count 2 2006.286.04:59:55.42#ibcon#read 4, iclass 28, count 2 2006.286.04:59:55.42#ibcon#about to read 5, iclass 28, count 2 2006.286.04:59:55.42#ibcon#read 5, iclass 28, count 2 2006.286.04:59:55.42#ibcon#about to read 6, iclass 28, count 2 2006.286.04:59:55.42#ibcon#read 6, iclass 28, count 2 2006.286.04:59:55.42#ibcon#end of sib2, iclass 28, count 2 2006.286.04:59:55.42#ibcon#*mode == 0, iclass 28, count 2 2006.286.04:59:55.42#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.04:59:55.42#ibcon#[27=AT04-05\r\n] 2006.286.04:59:55.42#ibcon#*before write, iclass 28, count 2 2006.286.04:59:55.42#ibcon#enter sib2, iclass 28, count 2 2006.286.04:59:55.42#ibcon#flushed, iclass 28, count 2 2006.286.04:59:55.42#ibcon#about to write, iclass 28, count 2 2006.286.04:59:55.42#ibcon#wrote, iclass 28, count 2 2006.286.04:59:55.42#ibcon#about to read 3, iclass 28, count 2 2006.286.04:59:55.45#ibcon#read 3, iclass 28, count 2 2006.286.04:59:55.45#ibcon#about to read 4, iclass 28, count 2 2006.286.04:59:55.45#ibcon#read 4, iclass 28, count 2 2006.286.04:59:55.45#ibcon#about to read 5, iclass 28, count 2 2006.286.04:59:55.45#ibcon#read 5, iclass 28, count 2 2006.286.04:59:55.45#ibcon#about to read 6, iclass 28, count 2 2006.286.04:59:55.45#ibcon#read 6, iclass 28, count 2 2006.286.04:59:55.45#ibcon#end of sib2, iclass 28, count 2 2006.286.04:59:55.45#ibcon#*after write, iclass 28, count 2 2006.286.04:59:55.45#ibcon#*before return 0, iclass 28, count 2 2006.286.04:59:55.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:59:55.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.04:59:55.45#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.04:59:55.45#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:55.45#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:59:55.57#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:59:55.57#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:59:55.57#ibcon#enter wrdev, iclass 28, count 0 2006.286.04:59:55.57#ibcon#first serial, iclass 28, count 0 2006.286.04:59:55.57#ibcon#enter sib2, iclass 28, count 0 2006.286.04:59:55.57#ibcon#flushed, iclass 28, count 0 2006.286.04:59:55.57#ibcon#about to write, iclass 28, count 0 2006.286.04:59:55.57#ibcon#wrote, iclass 28, count 0 2006.286.04:59:55.57#ibcon#about to read 3, iclass 28, count 0 2006.286.04:59:55.59#ibcon#read 3, iclass 28, count 0 2006.286.04:59:55.59#ibcon#about to read 4, iclass 28, count 0 2006.286.04:59:55.59#ibcon#read 4, iclass 28, count 0 2006.286.04:59:55.59#ibcon#about to read 5, iclass 28, count 0 2006.286.04:59:55.59#ibcon#read 5, iclass 28, count 0 2006.286.04:59:55.59#ibcon#about to read 6, iclass 28, count 0 2006.286.04:59:55.59#ibcon#read 6, iclass 28, count 0 2006.286.04:59:55.59#ibcon#end of sib2, iclass 28, count 0 2006.286.04:59:55.59#ibcon#*mode == 0, iclass 28, count 0 2006.286.04:59:55.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.04:59:55.59#ibcon#[27=USB\r\n] 2006.286.04:59:55.59#ibcon#*before write, iclass 28, count 0 2006.286.04:59:55.59#ibcon#enter sib2, iclass 28, count 0 2006.286.04:59:55.59#ibcon#flushed, iclass 28, count 0 2006.286.04:59:55.59#ibcon#about to write, iclass 28, count 0 2006.286.04:59:55.59#ibcon#wrote, iclass 28, count 0 2006.286.04:59:55.59#ibcon#about to read 3, iclass 28, count 0 2006.286.04:59:55.62#ibcon#read 3, iclass 28, count 0 2006.286.04:59:55.62#ibcon#about to read 4, iclass 28, count 0 2006.286.04:59:55.62#ibcon#read 4, iclass 28, count 0 2006.286.04:59:55.62#ibcon#about to read 5, iclass 28, count 0 2006.286.04:59:55.62#ibcon#read 5, iclass 28, count 0 2006.286.04:59:55.62#ibcon#about to read 6, iclass 28, count 0 2006.286.04:59:55.62#ibcon#read 6, iclass 28, count 0 2006.286.04:59:55.62#ibcon#end of sib2, iclass 28, count 0 2006.286.04:59:55.62#ibcon#*after write, iclass 28, count 0 2006.286.04:59:55.62#ibcon#*before return 0, iclass 28, count 0 2006.286.04:59:55.62#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:59:55.62#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.04:59:55.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.04:59:55.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.04:59:55.62$vck44/vblo=5,709.99 2006.286.04:59:55.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.04:59:55.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.04:59:55.68#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:55.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:59:55.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:59:55.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:59:55.68#ibcon#enter wrdev, iclass 30, count 0 2006.286.04:59:55.68#ibcon#first serial, iclass 30, count 0 2006.286.04:59:55.68#ibcon#enter sib2, iclass 30, count 0 2006.286.04:59:55.68#ibcon#flushed, iclass 30, count 0 2006.286.04:59:55.68#ibcon#about to write, iclass 30, count 0 2006.286.04:59:55.68#ibcon#wrote, iclass 30, count 0 2006.286.04:59:55.68#ibcon#about to read 3, iclass 30, count 0 2006.286.04:59:55.70#ibcon#read 3, iclass 30, count 0 2006.286.04:59:55.70#ibcon#about to read 4, iclass 30, count 0 2006.286.04:59:55.70#ibcon#read 4, iclass 30, count 0 2006.286.04:59:55.70#ibcon#about to read 5, iclass 30, count 0 2006.286.04:59:55.70#ibcon#read 5, iclass 30, count 0 2006.286.04:59:55.70#ibcon#about to read 6, iclass 30, count 0 2006.286.04:59:55.70#ibcon#read 6, iclass 30, count 0 2006.286.04:59:55.70#ibcon#end of sib2, iclass 30, count 0 2006.286.04:59:55.70#ibcon#*mode == 0, iclass 30, count 0 2006.286.04:59:55.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.04:59:55.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.04:59:55.70#ibcon#*before write, iclass 30, count 0 2006.286.04:59:55.70#ibcon#enter sib2, iclass 30, count 0 2006.286.04:59:55.70#ibcon#flushed, iclass 30, count 0 2006.286.04:59:55.70#ibcon#about to write, iclass 30, count 0 2006.286.04:59:55.70#ibcon#wrote, iclass 30, count 0 2006.286.04:59:55.70#ibcon#about to read 3, iclass 30, count 0 2006.286.04:59:55.74#ibcon#read 3, iclass 30, count 0 2006.286.04:59:55.74#ibcon#about to read 4, iclass 30, count 0 2006.286.04:59:55.74#ibcon#read 4, iclass 30, count 0 2006.286.04:59:55.74#ibcon#about to read 5, iclass 30, count 0 2006.286.04:59:55.74#ibcon#read 5, iclass 30, count 0 2006.286.04:59:55.74#ibcon#about to read 6, iclass 30, count 0 2006.286.04:59:55.74#ibcon#read 6, iclass 30, count 0 2006.286.04:59:55.74#ibcon#end of sib2, iclass 30, count 0 2006.286.04:59:55.74#ibcon#*after write, iclass 30, count 0 2006.286.04:59:55.74#ibcon#*before return 0, iclass 30, count 0 2006.286.04:59:55.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:59:55.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.04:59:55.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.04:59:55.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.04:59:55.74$vck44/vb=5,4 2006.286.04:59:55.74#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.04:59:55.74#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.04:59:55.74#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:55.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:59:55.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:59:55.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:59:55.74#ibcon#enter wrdev, iclass 32, count 2 2006.286.04:59:55.74#ibcon#first serial, iclass 32, count 2 2006.286.04:59:55.74#ibcon#enter sib2, iclass 32, count 2 2006.286.04:59:55.74#ibcon#flushed, iclass 32, count 2 2006.286.04:59:55.74#ibcon#about to write, iclass 32, count 2 2006.286.04:59:55.74#ibcon#wrote, iclass 32, count 2 2006.286.04:59:55.74#ibcon#about to read 3, iclass 32, count 2 2006.286.04:59:55.76#ibcon#read 3, iclass 32, count 2 2006.286.04:59:55.76#ibcon#about to read 4, iclass 32, count 2 2006.286.04:59:55.76#ibcon#read 4, iclass 32, count 2 2006.286.04:59:55.76#ibcon#about to read 5, iclass 32, count 2 2006.286.04:59:55.76#ibcon#read 5, iclass 32, count 2 2006.286.04:59:55.76#ibcon#about to read 6, iclass 32, count 2 2006.286.04:59:55.76#ibcon#read 6, iclass 32, count 2 2006.286.04:59:55.76#ibcon#end of sib2, iclass 32, count 2 2006.286.04:59:55.76#ibcon#*mode == 0, iclass 32, count 2 2006.286.04:59:55.76#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.04:59:55.76#ibcon#[27=AT05-04\r\n] 2006.286.04:59:55.76#ibcon#*before write, iclass 32, count 2 2006.286.04:59:55.76#ibcon#enter sib2, iclass 32, count 2 2006.286.04:59:55.76#ibcon#flushed, iclass 32, count 2 2006.286.04:59:55.76#ibcon#about to write, iclass 32, count 2 2006.286.04:59:55.76#ibcon#wrote, iclass 32, count 2 2006.286.04:59:55.76#ibcon#about to read 3, iclass 32, count 2 2006.286.04:59:55.79#ibcon#read 3, iclass 32, count 2 2006.286.04:59:55.79#ibcon#about to read 4, iclass 32, count 2 2006.286.04:59:55.79#ibcon#read 4, iclass 32, count 2 2006.286.04:59:55.79#ibcon#about to read 5, iclass 32, count 2 2006.286.04:59:55.79#ibcon#read 5, iclass 32, count 2 2006.286.04:59:55.79#ibcon#about to read 6, iclass 32, count 2 2006.286.04:59:55.79#ibcon#read 6, iclass 32, count 2 2006.286.04:59:55.79#ibcon#end of sib2, iclass 32, count 2 2006.286.04:59:55.79#ibcon#*after write, iclass 32, count 2 2006.286.04:59:55.79#ibcon#*before return 0, iclass 32, count 2 2006.286.04:59:55.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:59:55.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.04:59:55.79#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.04:59:55.79#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:55.79#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:59:55.91#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:59:55.91#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:59:55.91#ibcon#enter wrdev, iclass 32, count 0 2006.286.04:59:55.91#ibcon#first serial, iclass 32, count 0 2006.286.04:59:55.91#ibcon#enter sib2, iclass 32, count 0 2006.286.04:59:55.91#ibcon#flushed, iclass 32, count 0 2006.286.04:59:55.91#ibcon#about to write, iclass 32, count 0 2006.286.04:59:55.91#ibcon#wrote, iclass 32, count 0 2006.286.04:59:55.91#ibcon#about to read 3, iclass 32, count 0 2006.286.04:59:55.93#ibcon#read 3, iclass 32, count 0 2006.286.04:59:55.93#ibcon#about to read 4, iclass 32, count 0 2006.286.04:59:55.93#ibcon#read 4, iclass 32, count 0 2006.286.04:59:55.93#ibcon#about to read 5, iclass 32, count 0 2006.286.04:59:55.93#ibcon#read 5, iclass 32, count 0 2006.286.04:59:55.93#ibcon#about to read 6, iclass 32, count 0 2006.286.04:59:55.93#ibcon#read 6, iclass 32, count 0 2006.286.04:59:55.93#ibcon#end of sib2, iclass 32, count 0 2006.286.04:59:55.93#ibcon#*mode == 0, iclass 32, count 0 2006.286.04:59:55.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.04:59:55.93#ibcon#[27=USB\r\n] 2006.286.04:59:55.93#ibcon#*before write, iclass 32, count 0 2006.286.04:59:55.93#ibcon#enter sib2, iclass 32, count 0 2006.286.04:59:55.93#ibcon#flushed, iclass 32, count 0 2006.286.04:59:55.93#ibcon#about to write, iclass 32, count 0 2006.286.04:59:55.93#ibcon#wrote, iclass 32, count 0 2006.286.04:59:55.93#ibcon#about to read 3, iclass 32, count 0 2006.286.04:59:55.96#ibcon#read 3, iclass 32, count 0 2006.286.04:59:55.96#ibcon#about to read 4, iclass 32, count 0 2006.286.04:59:55.96#ibcon#read 4, iclass 32, count 0 2006.286.04:59:55.96#ibcon#about to read 5, iclass 32, count 0 2006.286.04:59:55.96#ibcon#read 5, iclass 32, count 0 2006.286.04:59:55.96#ibcon#about to read 6, iclass 32, count 0 2006.286.04:59:55.96#ibcon#read 6, iclass 32, count 0 2006.286.04:59:55.96#ibcon#end of sib2, iclass 32, count 0 2006.286.04:59:55.96#ibcon#*after write, iclass 32, count 0 2006.286.04:59:55.96#ibcon#*before return 0, iclass 32, count 0 2006.286.04:59:55.96#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:59:55.96#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.04:59:55.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.04:59:55.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.04:59:55.96$vck44/vblo=6,719.99 2006.286.04:59:55.96#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.04:59:55.96#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.04:59:55.96#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:55.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:59:55.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:59:55.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:59:55.96#ibcon#enter wrdev, iclass 34, count 0 2006.286.04:59:55.96#ibcon#first serial, iclass 34, count 0 2006.286.04:59:55.96#ibcon#enter sib2, iclass 34, count 0 2006.286.04:59:55.96#ibcon#flushed, iclass 34, count 0 2006.286.04:59:55.96#ibcon#about to write, iclass 34, count 0 2006.286.04:59:55.96#ibcon#wrote, iclass 34, count 0 2006.286.04:59:55.96#ibcon#about to read 3, iclass 34, count 0 2006.286.04:59:55.98#ibcon#read 3, iclass 34, count 0 2006.286.04:59:55.98#ibcon#about to read 4, iclass 34, count 0 2006.286.04:59:55.98#ibcon#read 4, iclass 34, count 0 2006.286.04:59:55.98#ibcon#about to read 5, iclass 34, count 0 2006.286.04:59:55.98#ibcon#read 5, iclass 34, count 0 2006.286.04:59:55.98#ibcon#about to read 6, iclass 34, count 0 2006.286.04:59:55.98#ibcon#read 6, iclass 34, count 0 2006.286.04:59:55.98#ibcon#end of sib2, iclass 34, count 0 2006.286.04:59:55.98#ibcon#*mode == 0, iclass 34, count 0 2006.286.04:59:55.98#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.04:59:55.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.04:59:55.98#ibcon#*before write, iclass 34, count 0 2006.286.04:59:55.98#ibcon#enter sib2, iclass 34, count 0 2006.286.04:59:55.98#ibcon#flushed, iclass 34, count 0 2006.286.04:59:55.98#ibcon#about to write, iclass 34, count 0 2006.286.04:59:55.98#ibcon#wrote, iclass 34, count 0 2006.286.04:59:55.98#ibcon#about to read 3, iclass 34, count 0 2006.286.04:59:56.02#ibcon#read 3, iclass 34, count 0 2006.286.04:59:56.02#ibcon#about to read 4, iclass 34, count 0 2006.286.04:59:56.02#ibcon#read 4, iclass 34, count 0 2006.286.04:59:56.02#ibcon#about to read 5, iclass 34, count 0 2006.286.04:59:56.02#ibcon#read 5, iclass 34, count 0 2006.286.04:59:56.02#ibcon#about to read 6, iclass 34, count 0 2006.286.04:59:56.02#ibcon#read 6, iclass 34, count 0 2006.286.04:59:56.02#ibcon#end of sib2, iclass 34, count 0 2006.286.04:59:56.02#ibcon#*after write, iclass 34, count 0 2006.286.04:59:56.02#ibcon#*before return 0, iclass 34, count 0 2006.286.04:59:56.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:59:56.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.04:59:56.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.04:59:56.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.04:59:56.02$vck44/vb=6,3 2006.286.04:59:56.02#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.04:59:56.02#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.04:59:56.02#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:56.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:59:56.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:59:56.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:59:56.08#ibcon#enter wrdev, iclass 36, count 2 2006.286.04:59:56.08#ibcon#first serial, iclass 36, count 2 2006.286.04:59:56.08#ibcon#enter sib2, iclass 36, count 2 2006.286.04:59:56.08#ibcon#flushed, iclass 36, count 2 2006.286.04:59:56.08#ibcon#about to write, iclass 36, count 2 2006.286.04:59:56.08#ibcon#wrote, iclass 36, count 2 2006.286.04:59:56.08#ibcon#about to read 3, iclass 36, count 2 2006.286.04:59:56.10#ibcon#read 3, iclass 36, count 2 2006.286.04:59:56.10#ibcon#about to read 4, iclass 36, count 2 2006.286.04:59:56.10#ibcon#read 4, iclass 36, count 2 2006.286.04:59:56.10#ibcon#about to read 5, iclass 36, count 2 2006.286.04:59:56.10#ibcon#read 5, iclass 36, count 2 2006.286.04:59:56.10#ibcon#about to read 6, iclass 36, count 2 2006.286.04:59:56.10#ibcon#read 6, iclass 36, count 2 2006.286.04:59:56.10#ibcon#end of sib2, iclass 36, count 2 2006.286.04:59:56.10#ibcon#*mode == 0, iclass 36, count 2 2006.286.04:59:56.10#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.04:59:56.10#ibcon#[27=AT06-03\r\n] 2006.286.04:59:56.10#ibcon#*before write, iclass 36, count 2 2006.286.04:59:56.10#ibcon#enter sib2, iclass 36, count 2 2006.286.04:59:56.10#ibcon#flushed, iclass 36, count 2 2006.286.04:59:56.10#ibcon#about to write, iclass 36, count 2 2006.286.04:59:56.10#ibcon#wrote, iclass 36, count 2 2006.286.04:59:56.10#ibcon#about to read 3, iclass 36, count 2 2006.286.04:59:56.13#ibcon#read 3, iclass 36, count 2 2006.286.04:59:56.13#ibcon#about to read 4, iclass 36, count 2 2006.286.04:59:56.13#ibcon#read 4, iclass 36, count 2 2006.286.04:59:56.13#ibcon#about to read 5, iclass 36, count 2 2006.286.04:59:56.13#ibcon#read 5, iclass 36, count 2 2006.286.04:59:56.13#ibcon#about to read 6, iclass 36, count 2 2006.286.04:59:56.13#ibcon#read 6, iclass 36, count 2 2006.286.04:59:56.13#ibcon#end of sib2, iclass 36, count 2 2006.286.04:59:56.13#ibcon#*after write, iclass 36, count 2 2006.286.04:59:56.13#ibcon#*before return 0, iclass 36, count 2 2006.286.04:59:56.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:59:56.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.04:59:56.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.04:59:56.13#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:56.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:59:56.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:59:56.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:59:56.25#ibcon#enter wrdev, iclass 36, count 0 2006.286.04:59:56.25#ibcon#first serial, iclass 36, count 0 2006.286.04:59:56.25#ibcon#enter sib2, iclass 36, count 0 2006.286.04:59:56.25#ibcon#flushed, iclass 36, count 0 2006.286.04:59:56.25#ibcon#about to write, iclass 36, count 0 2006.286.04:59:56.25#ibcon#wrote, iclass 36, count 0 2006.286.04:59:56.25#ibcon#about to read 3, iclass 36, count 0 2006.286.04:59:56.27#ibcon#read 3, iclass 36, count 0 2006.286.04:59:56.27#ibcon#about to read 4, iclass 36, count 0 2006.286.04:59:56.27#ibcon#read 4, iclass 36, count 0 2006.286.04:59:56.27#ibcon#about to read 5, iclass 36, count 0 2006.286.04:59:56.27#ibcon#read 5, iclass 36, count 0 2006.286.04:59:56.27#ibcon#about to read 6, iclass 36, count 0 2006.286.04:59:56.27#ibcon#read 6, iclass 36, count 0 2006.286.04:59:56.27#ibcon#end of sib2, iclass 36, count 0 2006.286.04:59:56.27#ibcon#*mode == 0, iclass 36, count 0 2006.286.04:59:56.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.04:59:56.27#ibcon#[27=USB\r\n] 2006.286.04:59:56.27#ibcon#*before write, iclass 36, count 0 2006.286.04:59:56.27#ibcon#enter sib2, iclass 36, count 0 2006.286.04:59:56.27#ibcon#flushed, iclass 36, count 0 2006.286.04:59:56.27#ibcon#about to write, iclass 36, count 0 2006.286.04:59:56.27#ibcon#wrote, iclass 36, count 0 2006.286.04:59:56.27#ibcon#about to read 3, iclass 36, count 0 2006.286.04:59:56.30#ibcon#read 3, iclass 36, count 0 2006.286.04:59:56.30#ibcon#about to read 4, iclass 36, count 0 2006.286.04:59:56.30#ibcon#read 4, iclass 36, count 0 2006.286.04:59:56.30#ibcon#about to read 5, iclass 36, count 0 2006.286.04:59:56.30#ibcon#read 5, iclass 36, count 0 2006.286.04:59:56.30#ibcon#about to read 6, iclass 36, count 0 2006.286.04:59:56.30#ibcon#read 6, iclass 36, count 0 2006.286.04:59:56.30#ibcon#end of sib2, iclass 36, count 0 2006.286.04:59:56.30#ibcon#*after write, iclass 36, count 0 2006.286.04:59:56.30#ibcon#*before return 0, iclass 36, count 0 2006.286.04:59:56.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:59:56.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.04:59:56.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.04:59:56.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.04:59:56.30$vck44/vblo=7,734.99 2006.286.04:59:56.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.04:59:56.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.04:59:56.30#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:56.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:59:56.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:59:56.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:59:56.30#ibcon#enter wrdev, iclass 38, count 0 2006.286.04:59:56.30#ibcon#first serial, iclass 38, count 0 2006.286.04:59:56.30#ibcon#enter sib2, iclass 38, count 0 2006.286.04:59:56.30#ibcon#flushed, iclass 38, count 0 2006.286.04:59:56.30#ibcon#about to write, iclass 38, count 0 2006.286.04:59:56.30#ibcon#wrote, iclass 38, count 0 2006.286.04:59:56.30#ibcon#about to read 3, iclass 38, count 0 2006.286.04:59:56.32#ibcon#read 3, iclass 38, count 0 2006.286.04:59:56.32#ibcon#about to read 4, iclass 38, count 0 2006.286.04:59:56.32#ibcon#read 4, iclass 38, count 0 2006.286.04:59:56.32#ibcon#about to read 5, iclass 38, count 0 2006.286.04:59:56.32#ibcon#read 5, iclass 38, count 0 2006.286.04:59:56.32#ibcon#about to read 6, iclass 38, count 0 2006.286.04:59:56.32#ibcon#read 6, iclass 38, count 0 2006.286.04:59:56.32#ibcon#end of sib2, iclass 38, count 0 2006.286.04:59:56.32#ibcon#*mode == 0, iclass 38, count 0 2006.286.04:59:56.32#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.04:59:56.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.04:59:56.32#ibcon#*before write, iclass 38, count 0 2006.286.04:59:56.32#ibcon#enter sib2, iclass 38, count 0 2006.286.04:59:56.32#ibcon#flushed, iclass 38, count 0 2006.286.04:59:56.32#ibcon#about to write, iclass 38, count 0 2006.286.04:59:56.32#ibcon#wrote, iclass 38, count 0 2006.286.04:59:56.32#ibcon#about to read 3, iclass 38, count 0 2006.286.04:59:56.36#ibcon#read 3, iclass 38, count 0 2006.286.04:59:56.36#ibcon#about to read 4, iclass 38, count 0 2006.286.04:59:56.36#ibcon#read 4, iclass 38, count 0 2006.286.04:59:56.36#ibcon#about to read 5, iclass 38, count 0 2006.286.04:59:56.36#ibcon#read 5, iclass 38, count 0 2006.286.04:59:56.36#ibcon#about to read 6, iclass 38, count 0 2006.286.04:59:56.36#ibcon#read 6, iclass 38, count 0 2006.286.04:59:56.36#ibcon#end of sib2, iclass 38, count 0 2006.286.04:59:56.36#ibcon#*after write, iclass 38, count 0 2006.286.04:59:56.36#ibcon#*before return 0, iclass 38, count 0 2006.286.04:59:56.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:59:56.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.04:59:56.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.04:59:56.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.04:59:56.36$vck44/vb=7,4 2006.286.04:59:56.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.04:59:56.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.04:59:56.36#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:56.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:59:56.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:59:56.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:59:56.42#ibcon#enter wrdev, iclass 40, count 2 2006.286.04:59:56.42#ibcon#first serial, iclass 40, count 2 2006.286.04:59:56.42#ibcon#enter sib2, iclass 40, count 2 2006.286.04:59:56.42#ibcon#flushed, iclass 40, count 2 2006.286.04:59:56.42#ibcon#about to write, iclass 40, count 2 2006.286.04:59:56.42#ibcon#wrote, iclass 40, count 2 2006.286.04:59:56.42#ibcon#about to read 3, iclass 40, count 2 2006.286.04:59:56.44#ibcon#read 3, iclass 40, count 2 2006.286.04:59:56.44#ibcon#about to read 4, iclass 40, count 2 2006.286.04:59:56.44#ibcon#read 4, iclass 40, count 2 2006.286.04:59:56.44#ibcon#about to read 5, iclass 40, count 2 2006.286.04:59:56.44#ibcon#read 5, iclass 40, count 2 2006.286.04:59:56.44#ibcon#about to read 6, iclass 40, count 2 2006.286.04:59:56.44#ibcon#read 6, iclass 40, count 2 2006.286.04:59:56.44#ibcon#end of sib2, iclass 40, count 2 2006.286.04:59:56.44#ibcon#*mode == 0, iclass 40, count 2 2006.286.04:59:56.44#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.04:59:56.44#ibcon#[27=AT07-04\r\n] 2006.286.04:59:56.44#ibcon#*before write, iclass 40, count 2 2006.286.04:59:56.44#ibcon#enter sib2, iclass 40, count 2 2006.286.04:59:56.44#ibcon#flushed, iclass 40, count 2 2006.286.04:59:56.44#ibcon#about to write, iclass 40, count 2 2006.286.04:59:56.44#ibcon#wrote, iclass 40, count 2 2006.286.04:59:56.44#ibcon#about to read 3, iclass 40, count 2 2006.286.04:59:56.47#ibcon#read 3, iclass 40, count 2 2006.286.04:59:56.47#ibcon#about to read 4, iclass 40, count 2 2006.286.04:59:56.47#ibcon#read 4, iclass 40, count 2 2006.286.04:59:56.47#ibcon#about to read 5, iclass 40, count 2 2006.286.04:59:56.47#ibcon#read 5, iclass 40, count 2 2006.286.04:59:56.47#ibcon#about to read 6, iclass 40, count 2 2006.286.04:59:56.47#ibcon#read 6, iclass 40, count 2 2006.286.04:59:56.47#ibcon#end of sib2, iclass 40, count 2 2006.286.04:59:56.47#ibcon#*after write, iclass 40, count 2 2006.286.04:59:56.47#ibcon#*before return 0, iclass 40, count 2 2006.286.04:59:56.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:59:56.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.04:59:56.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.04:59:56.47#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:56.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:59:56.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:59:56.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:59:56.59#ibcon#enter wrdev, iclass 40, count 0 2006.286.04:59:56.59#ibcon#first serial, iclass 40, count 0 2006.286.04:59:56.59#ibcon#enter sib2, iclass 40, count 0 2006.286.04:59:56.59#ibcon#flushed, iclass 40, count 0 2006.286.04:59:56.59#ibcon#about to write, iclass 40, count 0 2006.286.04:59:56.59#ibcon#wrote, iclass 40, count 0 2006.286.04:59:56.59#ibcon#about to read 3, iclass 40, count 0 2006.286.04:59:56.61#ibcon#read 3, iclass 40, count 0 2006.286.04:59:56.61#ibcon#about to read 4, iclass 40, count 0 2006.286.04:59:56.61#ibcon#read 4, iclass 40, count 0 2006.286.04:59:56.61#ibcon#about to read 5, iclass 40, count 0 2006.286.04:59:56.61#ibcon#read 5, iclass 40, count 0 2006.286.04:59:56.61#ibcon#about to read 6, iclass 40, count 0 2006.286.04:59:56.61#ibcon#read 6, iclass 40, count 0 2006.286.04:59:56.61#ibcon#end of sib2, iclass 40, count 0 2006.286.04:59:56.61#ibcon#*mode == 0, iclass 40, count 0 2006.286.04:59:56.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.04:59:56.61#ibcon#[27=USB\r\n] 2006.286.04:59:56.61#ibcon#*before write, iclass 40, count 0 2006.286.04:59:56.61#ibcon#enter sib2, iclass 40, count 0 2006.286.04:59:56.61#ibcon#flushed, iclass 40, count 0 2006.286.04:59:56.61#ibcon#about to write, iclass 40, count 0 2006.286.04:59:56.61#ibcon#wrote, iclass 40, count 0 2006.286.04:59:56.61#ibcon#about to read 3, iclass 40, count 0 2006.286.04:59:56.64#ibcon#read 3, iclass 40, count 0 2006.286.04:59:56.64#ibcon#about to read 4, iclass 40, count 0 2006.286.04:59:56.64#ibcon#read 4, iclass 40, count 0 2006.286.04:59:56.64#ibcon#about to read 5, iclass 40, count 0 2006.286.04:59:56.64#ibcon#read 5, iclass 40, count 0 2006.286.04:59:56.64#ibcon#about to read 6, iclass 40, count 0 2006.286.04:59:56.64#ibcon#read 6, iclass 40, count 0 2006.286.04:59:56.64#ibcon#end of sib2, iclass 40, count 0 2006.286.04:59:56.64#ibcon#*after write, iclass 40, count 0 2006.286.04:59:56.64#ibcon#*before return 0, iclass 40, count 0 2006.286.04:59:56.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:59:56.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.04:59:56.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.04:59:56.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.04:59:56.64$vck44/vblo=8,744.99 2006.286.04:59:56.70#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.04:59:56.70#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.04:59:56.70#ibcon#ireg 17 cls_cnt 0 2006.286.04:59:56.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:59:56.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:59:56.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:59:56.70#ibcon#enter wrdev, iclass 4, count 0 2006.286.04:59:56.70#ibcon#first serial, iclass 4, count 0 2006.286.04:59:56.70#ibcon#enter sib2, iclass 4, count 0 2006.286.04:59:56.70#ibcon#flushed, iclass 4, count 0 2006.286.04:59:56.70#ibcon#about to write, iclass 4, count 0 2006.286.04:59:56.70#ibcon#wrote, iclass 4, count 0 2006.286.04:59:56.70#ibcon#about to read 3, iclass 4, count 0 2006.286.04:59:56.72#ibcon#read 3, iclass 4, count 0 2006.286.04:59:56.72#ibcon#about to read 4, iclass 4, count 0 2006.286.04:59:56.72#ibcon#read 4, iclass 4, count 0 2006.286.04:59:56.72#ibcon#about to read 5, iclass 4, count 0 2006.286.04:59:56.72#ibcon#read 5, iclass 4, count 0 2006.286.04:59:56.72#ibcon#about to read 6, iclass 4, count 0 2006.286.04:59:56.72#ibcon#read 6, iclass 4, count 0 2006.286.04:59:56.72#ibcon#end of sib2, iclass 4, count 0 2006.286.04:59:56.72#ibcon#*mode == 0, iclass 4, count 0 2006.286.04:59:56.72#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.04:59:56.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.04:59:56.72#ibcon#*before write, iclass 4, count 0 2006.286.04:59:56.72#ibcon#enter sib2, iclass 4, count 0 2006.286.04:59:56.72#ibcon#flushed, iclass 4, count 0 2006.286.04:59:56.72#ibcon#about to write, iclass 4, count 0 2006.286.04:59:56.72#ibcon#wrote, iclass 4, count 0 2006.286.04:59:56.72#ibcon#about to read 3, iclass 4, count 0 2006.286.04:59:56.76#ibcon#read 3, iclass 4, count 0 2006.286.04:59:56.76#ibcon#about to read 4, iclass 4, count 0 2006.286.04:59:56.76#ibcon#read 4, iclass 4, count 0 2006.286.04:59:56.76#ibcon#about to read 5, iclass 4, count 0 2006.286.04:59:56.76#ibcon#read 5, iclass 4, count 0 2006.286.04:59:56.76#ibcon#about to read 6, iclass 4, count 0 2006.286.04:59:56.76#ibcon#read 6, iclass 4, count 0 2006.286.04:59:56.76#ibcon#end of sib2, iclass 4, count 0 2006.286.04:59:56.76#ibcon#*after write, iclass 4, count 0 2006.286.04:59:56.76#ibcon#*before return 0, iclass 4, count 0 2006.286.04:59:56.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:59:56.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.04:59:56.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.04:59:56.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.04:59:56.76$vck44/vb=8,4 2006.286.04:59:56.76#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.04:59:56.76#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.04:59:56.76#ibcon#ireg 11 cls_cnt 2 2006.286.04:59:56.76#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:59:56.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:59:56.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:59:56.76#ibcon#enter wrdev, iclass 6, count 2 2006.286.04:59:56.76#ibcon#first serial, iclass 6, count 2 2006.286.04:59:56.76#ibcon#enter sib2, iclass 6, count 2 2006.286.04:59:56.76#ibcon#flushed, iclass 6, count 2 2006.286.04:59:56.76#ibcon#about to write, iclass 6, count 2 2006.286.04:59:56.76#ibcon#wrote, iclass 6, count 2 2006.286.04:59:56.76#ibcon#about to read 3, iclass 6, count 2 2006.286.04:59:56.78#ibcon#read 3, iclass 6, count 2 2006.286.04:59:56.78#ibcon#about to read 4, iclass 6, count 2 2006.286.04:59:56.78#ibcon#read 4, iclass 6, count 2 2006.286.04:59:56.78#ibcon#about to read 5, iclass 6, count 2 2006.286.04:59:56.78#ibcon#read 5, iclass 6, count 2 2006.286.04:59:56.78#ibcon#about to read 6, iclass 6, count 2 2006.286.04:59:56.78#ibcon#read 6, iclass 6, count 2 2006.286.04:59:56.78#ibcon#end of sib2, iclass 6, count 2 2006.286.04:59:56.78#ibcon#*mode == 0, iclass 6, count 2 2006.286.04:59:56.78#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.04:59:56.78#ibcon#[27=AT08-04\r\n] 2006.286.04:59:56.78#ibcon#*before write, iclass 6, count 2 2006.286.04:59:56.78#ibcon#enter sib2, iclass 6, count 2 2006.286.04:59:56.78#ibcon#flushed, iclass 6, count 2 2006.286.04:59:56.78#ibcon#about to write, iclass 6, count 2 2006.286.04:59:56.78#ibcon#wrote, iclass 6, count 2 2006.286.04:59:56.78#ibcon#about to read 3, iclass 6, count 2 2006.286.04:59:56.81#ibcon#read 3, iclass 6, count 2 2006.286.04:59:56.81#ibcon#about to read 4, iclass 6, count 2 2006.286.04:59:56.81#ibcon#read 4, iclass 6, count 2 2006.286.04:59:56.81#ibcon#about to read 5, iclass 6, count 2 2006.286.04:59:56.81#ibcon#read 5, iclass 6, count 2 2006.286.04:59:56.81#ibcon#about to read 6, iclass 6, count 2 2006.286.04:59:56.81#ibcon#read 6, iclass 6, count 2 2006.286.04:59:56.81#ibcon#end of sib2, iclass 6, count 2 2006.286.04:59:56.81#ibcon#*after write, iclass 6, count 2 2006.286.04:59:56.81#ibcon#*before return 0, iclass 6, count 2 2006.286.04:59:56.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:59:56.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.04:59:56.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.04:59:56.81#ibcon#ireg 7 cls_cnt 0 2006.286.04:59:56.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:59:56.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:59:56.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:59:56.93#ibcon#enter wrdev, iclass 6, count 0 2006.286.04:59:56.93#ibcon#first serial, iclass 6, count 0 2006.286.04:59:56.93#ibcon#enter sib2, iclass 6, count 0 2006.286.04:59:56.93#ibcon#flushed, iclass 6, count 0 2006.286.04:59:56.93#ibcon#about to write, iclass 6, count 0 2006.286.04:59:56.93#ibcon#wrote, iclass 6, count 0 2006.286.04:59:56.93#ibcon#about to read 3, iclass 6, count 0 2006.286.04:59:56.95#ibcon#read 3, iclass 6, count 0 2006.286.04:59:56.95#ibcon#about to read 4, iclass 6, count 0 2006.286.04:59:56.95#ibcon#read 4, iclass 6, count 0 2006.286.04:59:56.95#ibcon#about to read 5, iclass 6, count 0 2006.286.04:59:56.95#ibcon#read 5, iclass 6, count 0 2006.286.04:59:56.95#ibcon#about to read 6, iclass 6, count 0 2006.286.04:59:56.95#ibcon#read 6, iclass 6, count 0 2006.286.04:59:56.95#ibcon#end of sib2, iclass 6, count 0 2006.286.04:59:56.95#ibcon#*mode == 0, iclass 6, count 0 2006.286.04:59:56.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.04:59:56.95#ibcon#[27=USB\r\n] 2006.286.04:59:56.95#ibcon#*before write, iclass 6, count 0 2006.286.04:59:56.95#ibcon#enter sib2, iclass 6, count 0 2006.286.04:59:56.95#ibcon#flushed, iclass 6, count 0 2006.286.04:59:56.95#ibcon#about to write, iclass 6, count 0 2006.286.04:59:56.95#ibcon#wrote, iclass 6, count 0 2006.286.04:59:56.95#ibcon#about to read 3, iclass 6, count 0 2006.286.04:59:56.98#ibcon#read 3, iclass 6, count 0 2006.286.04:59:56.98#ibcon#about to read 4, iclass 6, count 0 2006.286.04:59:56.98#ibcon#read 4, iclass 6, count 0 2006.286.04:59:56.98#ibcon#about to read 5, iclass 6, count 0 2006.286.04:59:56.98#ibcon#read 5, iclass 6, count 0 2006.286.04:59:56.98#ibcon#about to read 6, iclass 6, count 0 2006.286.04:59:56.98#ibcon#read 6, iclass 6, count 0 2006.286.04:59:56.98#ibcon#end of sib2, iclass 6, count 0 2006.286.04:59:56.98#ibcon#*after write, iclass 6, count 0 2006.286.04:59:56.98#ibcon#*before return 0, iclass 6, count 0 2006.286.04:59:56.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:59:56.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.04:59:56.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.04:59:56.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.04:59:56.98$vck44/vabw=wide 2006.286.04:59:56.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.04:59:56.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.04:59:56.98#ibcon#ireg 8 cls_cnt 0 2006.286.04:59:56.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:59:56.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:59:56.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:59:56.98#ibcon#enter wrdev, iclass 10, count 0 2006.286.04:59:56.98#ibcon#first serial, iclass 10, count 0 2006.286.04:59:56.98#ibcon#enter sib2, iclass 10, count 0 2006.286.04:59:56.98#ibcon#flushed, iclass 10, count 0 2006.286.04:59:56.98#ibcon#about to write, iclass 10, count 0 2006.286.04:59:56.98#ibcon#wrote, iclass 10, count 0 2006.286.04:59:56.98#ibcon#about to read 3, iclass 10, count 0 2006.286.04:59:57.00#ibcon#read 3, iclass 10, count 0 2006.286.04:59:57.00#ibcon#about to read 4, iclass 10, count 0 2006.286.04:59:57.00#ibcon#read 4, iclass 10, count 0 2006.286.04:59:57.00#ibcon#about to read 5, iclass 10, count 0 2006.286.04:59:57.00#ibcon#read 5, iclass 10, count 0 2006.286.04:59:57.00#ibcon#about to read 6, iclass 10, count 0 2006.286.04:59:57.00#ibcon#read 6, iclass 10, count 0 2006.286.04:59:57.00#ibcon#end of sib2, iclass 10, count 0 2006.286.04:59:57.00#ibcon#*mode == 0, iclass 10, count 0 2006.286.04:59:57.00#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.04:59:57.00#ibcon#[25=BW32\r\n] 2006.286.04:59:57.00#ibcon#*before write, iclass 10, count 0 2006.286.04:59:57.00#ibcon#enter sib2, iclass 10, count 0 2006.286.04:59:57.00#ibcon#flushed, iclass 10, count 0 2006.286.04:59:57.00#ibcon#about to write, iclass 10, count 0 2006.286.04:59:57.00#ibcon#wrote, iclass 10, count 0 2006.286.04:59:57.00#ibcon#about to read 3, iclass 10, count 0 2006.286.04:59:57.03#ibcon#read 3, iclass 10, count 0 2006.286.04:59:57.03#ibcon#about to read 4, iclass 10, count 0 2006.286.04:59:57.03#ibcon#read 4, iclass 10, count 0 2006.286.04:59:57.03#ibcon#about to read 5, iclass 10, count 0 2006.286.04:59:57.03#ibcon#read 5, iclass 10, count 0 2006.286.04:59:57.03#ibcon#about to read 6, iclass 10, count 0 2006.286.04:59:57.03#ibcon#read 6, iclass 10, count 0 2006.286.04:59:57.03#ibcon#end of sib2, iclass 10, count 0 2006.286.04:59:57.03#ibcon#*after write, iclass 10, count 0 2006.286.04:59:57.03#ibcon#*before return 0, iclass 10, count 0 2006.286.04:59:57.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:59:57.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.04:59:57.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.04:59:57.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.04:59:57.03$vck44/vbbw=wide 2006.286.04:59:57.03#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.04:59:57.03#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.04:59:57.03#ibcon#ireg 8 cls_cnt 0 2006.286.04:59:57.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:59:57.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:59:57.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:59:57.10#ibcon#enter wrdev, iclass 12, count 0 2006.286.04:59:57.10#ibcon#first serial, iclass 12, count 0 2006.286.04:59:57.10#ibcon#enter sib2, iclass 12, count 0 2006.286.04:59:57.10#ibcon#flushed, iclass 12, count 0 2006.286.04:59:57.10#ibcon#about to write, iclass 12, count 0 2006.286.04:59:57.10#ibcon#wrote, iclass 12, count 0 2006.286.04:59:57.10#ibcon#about to read 3, iclass 12, count 0 2006.286.04:59:57.12#ibcon#read 3, iclass 12, count 0 2006.286.04:59:57.12#ibcon#about to read 4, iclass 12, count 0 2006.286.04:59:57.12#ibcon#read 4, iclass 12, count 0 2006.286.04:59:57.12#ibcon#about to read 5, iclass 12, count 0 2006.286.04:59:57.12#ibcon#read 5, iclass 12, count 0 2006.286.04:59:57.12#ibcon#about to read 6, iclass 12, count 0 2006.286.04:59:57.12#ibcon#read 6, iclass 12, count 0 2006.286.04:59:57.12#ibcon#end of sib2, iclass 12, count 0 2006.286.04:59:57.12#ibcon#*mode == 0, iclass 12, count 0 2006.286.04:59:57.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.04:59:57.12#ibcon#[27=BW32\r\n] 2006.286.04:59:57.12#ibcon#*before write, iclass 12, count 0 2006.286.04:59:57.12#ibcon#enter sib2, iclass 12, count 0 2006.286.04:59:57.12#ibcon#flushed, iclass 12, count 0 2006.286.04:59:57.12#ibcon#about to write, iclass 12, count 0 2006.286.04:59:57.12#ibcon#wrote, iclass 12, count 0 2006.286.04:59:57.12#ibcon#about to read 3, iclass 12, count 0 2006.286.04:59:57.15#ibcon#read 3, iclass 12, count 0 2006.286.04:59:57.15#ibcon#about to read 4, iclass 12, count 0 2006.286.04:59:57.15#ibcon#read 4, iclass 12, count 0 2006.286.04:59:57.15#ibcon#about to read 5, iclass 12, count 0 2006.286.04:59:57.15#ibcon#read 5, iclass 12, count 0 2006.286.04:59:57.15#ibcon#about to read 6, iclass 12, count 0 2006.286.04:59:57.15#ibcon#read 6, iclass 12, count 0 2006.286.04:59:57.15#ibcon#end of sib2, iclass 12, count 0 2006.286.04:59:57.15#ibcon#*after write, iclass 12, count 0 2006.286.04:59:57.15#ibcon#*before return 0, iclass 12, count 0 2006.286.04:59:57.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:59:57.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.04:59:57.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.04:59:57.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.04:59:57.15$setupk4/ifdk4 2006.286.04:59:57.15$ifdk4/lo= 2006.286.04:59:57.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.04:59:57.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.04:59:57.15$ifdk4/patch= 2006.286.04:59:57.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.04:59:57.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.04:59:57.15$setupk4/!*+20s 2006.286.05:00:01.14#trakl#Source acquired 2006.286.05:00:02.14#flagr#flagr/antenna,acquired 2006.286.05:00:02.31#abcon#<5=/03 3.3 7.5 22.10 761014.9\r\n> 2006.286.05:00:02.33#abcon#{5=INTERFACE CLEAR} 2006.286.05:00:02.39#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:00:10.83$setupk4/"tpicd 2006.286.05:00:10.83$setupk4/echo=off 2006.286.05:00:10.83$setupk4/xlog=off 2006.286.05:00:10.83:!2006.286.05:00:18 2006.286.05:00:18.00:preob 2006.286.05:00:18.14/onsource/TRACKING 2006.286.05:00:18.14:!2006.286.05:00:28 2006.286.05:00:28.00:"tape 2006.286.05:00:28.00:"st=record 2006.286.05:00:28.00:data_valid=on 2006.286.05:00:28.00:midob 2006.286.05:00:29.14/onsource/TRACKING 2006.286.05:00:29.14/wx/22.10,1014.9,75 2006.286.05:00:29.22/cable/+6.4940E-03 2006.286.05:00:30.31/va/01,07,usb,yes,35,38 2006.286.05:00:30.31/va/02,06,usb,yes,35,35 2006.286.05:00:30.31/va/03,07,usb,yes,34,36 2006.286.05:00:30.31/va/04,06,usb,yes,36,38 2006.286.05:00:30.31/va/05,03,usb,yes,36,36 2006.286.05:00:30.31/va/06,04,usb,yes,32,32 2006.286.05:00:30.31/va/07,04,usb,yes,33,33 2006.286.05:00:30.31/va/08,03,usb,yes,33,41 2006.286.05:00:30.54/valo/01,524.99,yes,locked 2006.286.05:00:30.54/valo/02,534.99,yes,locked 2006.286.05:00:30.54/valo/03,564.99,yes,locked 2006.286.05:00:30.54/valo/04,624.99,yes,locked 2006.286.05:00:30.54/valo/05,734.99,yes,locked 2006.286.05:00:30.54/valo/06,814.99,yes,locked 2006.286.05:00:30.54/valo/07,864.99,yes,locked 2006.286.05:00:30.54/valo/08,884.99,yes,locked 2006.286.05:00:31.63/vb/01,04,usb,yes,32,30 2006.286.05:00:31.63/vb/02,05,usb,yes,31,30 2006.286.05:00:31.63/vb/03,04,usb,yes,32,35 2006.286.05:00:31.63/vb/04,05,usb,yes,32,31 2006.286.05:00:31.63/vb/05,04,usb,yes,28,31 2006.286.05:00:31.63/vb/06,03,usb,yes,41,36 2006.286.05:00:31.63/vb/07,04,usb,yes,33,33 2006.286.05:00:31.63/vb/08,04,usb,yes,30,34 2006.286.05:00:31.86/vblo/01,629.99,yes,locked 2006.286.05:00:31.86/vblo/02,634.99,yes,locked 2006.286.05:00:31.86/vblo/03,649.99,yes,locked 2006.286.05:00:31.86/vblo/04,679.99,yes,locked 2006.286.05:00:31.86/vblo/05,709.99,yes,locked 2006.286.05:00:31.86/vblo/06,719.99,yes,locked 2006.286.05:00:31.86/vblo/07,734.99,yes,locked 2006.286.05:00:31.86/vblo/08,744.99,yes,locked 2006.286.05:00:32.01/vabw/8 2006.286.05:00:32.16/vbbw/8 2006.286.05:00:32.25/xfe/off,on,12.2 2006.286.05:00:32.63/ifatt/23,28,28,28 2006.286.05:00:33.07/fmout-gps/S +2.41E-07 2006.286.05:00:33.09:!2006.286.05:03:48 2006.286.05:01:06.14#trakl#Off source 2006.286.05:01:06.14?ERROR st -7 Antenna off-source! 2006.286.05:01:06.14#trakl#az 61.521 el 15.298 azerr*cos(el) 0.0213 elerr 0.0041 2006.286.05:01:06.14#flagr#flagr/antenna,off-source 2006.286.05:01:12.14#trakl#Source re-acquired 2006.286.05:01:12.14#flagr#flagr/antenna,re-acquired 2006.286.05:03:48.01:data_valid=off 2006.286.05:03:48.01:"et 2006.286.05:03:48.01:!+3s 2006.286.05:03:51.02:"tape 2006.286.05:03:51.02:postob 2006.286.05:03:51.11/cable/+6.4936E-03 2006.286.05:03:51.11/wx/22.07,1015.0,76 2006.286.05:03:52.08/fmout-gps/S +2.42E-07 2006.286.05:03:52.08:scan_name=286-0515,jd0610,90 2006.286.05:03:52.08:source=3c274,123049.42,122328.0,2000.0,ccw 2006.286.05:03:53.14#flagr#flagr/antenna,new-source 2006.286.05:03:53.14:checkk5 2006.286.05:03:53.49/chk_autoobs//k5ts1/ autoobs is running! 2006.286.05:03:53.94/chk_autoobs//k5ts2/ autoobs is running! 2006.286.05:03:54.69/chk_autoobs//k5ts3/ autoobs is running! 2006.286.05:03:55.16/chk_autoobs//k5ts4/ autoobs is running! 2006.286.05:03:55.73/chk_obsdata//k5ts1/T2860500??a.dat file size is correct (nominal:800MB, actual:796MB). 2006.286.05:03:56.18/chk_obsdata//k5ts2/T2860500??b.dat file size is correct (nominal:800MB, actual:796MB). 2006.286.05:03:56.59/chk_obsdata//k5ts3/T2860500??c.dat file size is correct (nominal:800MB, actual:796MB). 2006.286.05:03:57.24/chk_obsdata//k5ts4/T2860500??d.dat file size is correct (nominal:800MB, actual:796MB). 2006.286.05:03:58.26/k5log//k5ts1_log_newline 2006.286.05:03:59.33/k5log//k5ts2_log_newline 2006.286.05:04:00.64/k5log//k5ts3_log_newline 2006.286.05:04:01.42/k5log//k5ts4_log_newline 2006.286.05:04:01.45/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.05:04:01.45:setupk4=1 2006.286.05:04:01.45$setupk4/echo=on 2006.286.05:04:01.45$setupk4/pcalon 2006.286.05:04:01.45$pcalon/"no phase cal control is implemented here 2006.286.05:04:01.45$setupk4/"tpicd=stop 2006.286.05:04:01.45$setupk4/"rec=synch_on 2006.286.05:04:01.45$setupk4/"rec_mode=128 2006.286.05:04:01.45$setupk4/!* 2006.286.05:04:01.45$setupk4/recpk4 2006.286.05:04:01.45$recpk4/recpatch= 2006.286.05:04:01.45$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.05:04:01.45$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.05:04:01.45$setupk4/vck44 2006.286.05:04:01.45$vck44/valo=1,524.99 2006.286.05:04:01.45#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.05:04:01.45#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.05:04:01.45#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:01.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:04:01.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:04:01.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:04:01.45#ibcon#enter wrdev, iclass 5, count 0 2006.286.05:04:01.45#ibcon#first serial, iclass 5, count 0 2006.286.05:04:01.45#ibcon#enter sib2, iclass 5, count 0 2006.286.05:04:01.45#ibcon#flushed, iclass 5, count 0 2006.286.05:04:01.45#ibcon#about to write, iclass 5, count 0 2006.286.05:04:01.45#ibcon#wrote, iclass 5, count 0 2006.286.05:04:01.45#ibcon#about to read 3, iclass 5, count 0 2006.286.05:04:01.47#ibcon#read 3, iclass 5, count 0 2006.286.05:04:01.47#ibcon#about to read 4, iclass 5, count 0 2006.286.05:04:01.47#ibcon#read 4, iclass 5, count 0 2006.286.05:04:01.47#ibcon#about to read 5, iclass 5, count 0 2006.286.05:04:01.47#ibcon#read 5, iclass 5, count 0 2006.286.05:04:01.47#ibcon#about to read 6, iclass 5, count 0 2006.286.05:04:01.47#ibcon#read 6, iclass 5, count 0 2006.286.05:04:01.47#ibcon#end of sib2, iclass 5, count 0 2006.286.05:04:01.47#ibcon#*mode == 0, iclass 5, count 0 2006.286.05:04:01.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.05:04:01.47#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.05:04:01.47#ibcon#*before write, iclass 5, count 0 2006.286.05:04:01.47#ibcon#enter sib2, iclass 5, count 0 2006.286.05:04:01.47#ibcon#flushed, iclass 5, count 0 2006.286.05:04:01.47#ibcon#about to write, iclass 5, count 0 2006.286.05:04:01.47#ibcon#wrote, iclass 5, count 0 2006.286.05:04:01.47#ibcon#about to read 3, iclass 5, count 0 2006.286.05:04:01.52#ibcon#read 3, iclass 5, count 0 2006.286.05:04:01.52#ibcon#about to read 4, iclass 5, count 0 2006.286.05:04:01.52#ibcon#read 4, iclass 5, count 0 2006.286.05:04:01.52#ibcon#about to read 5, iclass 5, count 0 2006.286.05:04:01.52#ibcon#read 5, iclass 5, count 0 2006.286.05:04:01.52#ibcon#about to read 6, iclass 5, count 0 2006.286.05:04:01.52#ibcon#read 6, iclass 5, count 0 2006.286.05:04:01.52#ibcon#end of sib2, iclass 5, count 0 2006.286.05:04:01.52#ibcon#*after write, iclass 5, count 0 2006.286.05:04:01.52#ibcon#*before return 0, iclass 5, count 0 2006.286.05:04:01.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:04:01.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:04:01.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.05:04:01.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.05:04:01.52$vck44/va=1,7 2006.286.05:04:01.52#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.05:04:01.52#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.05:04:01.52#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:01.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:04:01.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:04:01.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:04:01.52#ibcon#enter wrdev, iclass 7, count 2 2006.286.05:04:01.52#ibcon#first serial, iclass 7, count 2 2006.286.05:04:01.52#ibcon#enter sib2, iclass 7, count 2 2006.286.05:04:01.52#ibcon#flushed, iclass 7, count 2 2006.286.05:04:01.52#ibcon#about to write, iclass 7, count 2 2006.286.05:04:01.52#ibcon#wrote, iclass 7, count 2 2006.286.05:04:01.52#ibcon#about to read 3, iclass 7, count 2 2006.286.05:04:01.54#ibcon#read 3, iclass 7, count 2 2006.286.05:04:01.54#ibcon#about to read 4, iclass 7, count 2 2006.286.05:04:01.54#ibcon#read 4, iclass 7, count 2 2006.286.05:04:01.54#ibcon#about to read 5, iclass 7, count 2 2006.286.05:04:01.54#ibcon#read 5, iclass 7, count 2 2006.286.05:04:01.54#ibcon#about to read 6, iclass 7, count 2 2006.286.05:04:01.54#ibcon#read 6, iclass 7, count 2 2006.286.05:04:01.54#ibcon#end of sib2, iclass 7, count 2 2006.286.05:04:01.54#ibcon#*mode == 0, iclass 7, count 2 2006.286.05:04:01.54#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.05:04:01.54#ibcon#[25=AT01-07\r\n] 2006.286.05:04:01.54#ibcon#*before write, iclass 7, count 2 2006.286.05:04:01.54#ibcon#enter sib2, iclass 7, count 2 2006.286.05:04:01.54#ibcon#flushed, iclass 7, count 2 2006.286.05:04:01.54#ibcon#about to write, iclass 7, count 2 2006.286.05:04:01.54#ibcon#wrote, iclass 7, count 2 2006.286.05:04:01.54#ibcon#about to read 3, iclass 7, count 2 2006.286.05:04:01.57#ibcon#read 3, iclass 7, count 2 2006.286.05:04:01.57#ibcon#about to read 4, iclass 7, count 2 2006.286.05:04:01.57#ibcon#read 4, iclass 7, count 2 2006.286.05:04:01.57#ibcon#about to read 5, iclass 7, count 2 2006.286.05:04:01.57#ibcon#read 5, iclass 7, count 2 2006.286.05:04:01.57#ibcon#about to read 6, iclass 7, count 2 2006.286.05:04:01.57#ibcon#read 6, iclass 7, count 2 2006.286.05:04:01.57#ibcon#end of sib2, iclass 7, count 2 2006.286.05:04:01.57#ibcon#*after write, iclass 7, count 2 2006.286.05:04:01.57#ibcon#*before return 0, iclass 7, count 2 2006.286.05:04:01.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:04:01.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:04:01.57#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.05:04:01.57#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:01.57#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:04:01.69#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:04:01.69#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:04:01.69#ibcon#enter wrdev, iclass 7, count 0 2006.286.05:04:01.69#ibcon#first serial, iclass 7, count 0 2006.286.05:04:01.69#ibcon#enter sib2, iclass 7, count 0 2006.286.05:04:01.69#ibcon#flushed, iclass 7, count 0 2006.286.05:04:01.69#ibcon#about to write, iclass 7, count 0 2006.286.05:04:01.69#ibcon#wrote, iclass 7, count 0 2006.286.05:04:01.69#ibcon#about to read 3, iclass 7, count 0 2006.286.05:04:01.71#ibcon#read 3, iclass 7, count 0 2006.286.05:04:01.71#ibcon#about to read 4, iclass 7, count 0 2006.286.05:04:01.71#ibcon#read 4, iclass 7, count 0 2006.286.05:04:01.71#ibcon#about to read 5, iclass 7, count 0 2006.286.05:04:01.71#ibcon#read 5, iclass 7, count 0 2006.286.05:04:01.71#ibcon#about to read 6, iclass 7, count 0 2006.286.05:04:01.71#ibcon#read 6, iclass 7, count 0 2006.286.05:04:01.71#ibcon#end of sib2, iclass 7, count 0 2006.286.05:04:01.71#ibcon#*mode == 0, iclass 7, count 0 2006.286.05:04:01.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.05:04:01.71#ibcon#[25=USB\r\n] 2006.286.05:04:01.71#ibcon#*before write, iclass 7, count 0 2006.286.05:04:01.71#ibcon#enter sib2, iclass 7, count 0 2006.286.05:04:01.71#ibcon#flushed, iclass 7, count 0 2006.286.05:04:01.71#ibcon#about to write, iclass 7, count 0 2006.286.05:04:01.71#ibcon#wrote, iclass 7, count 0 2006.286.05:04:01.71#ibcon#about to read 3, iclass 7, count 0 2006.286.05:04:01.74#ibcon#read 3, iclass 7, count 0 2006.286.05:04:01.74#ibcon#about to read 4, iclass 7, count 0 2006.286.05:04:01.74#ibcon#read 4, iclass 7, count 0 2006.286.05:04:01.74#ibcon#about to read 5, iclass 7, count 0 2006.286.05:04:01.74#ibcon#read 5, iclass 7, count 0 2006.286.05:04:01.74#ibcon#about to read 6, iclass 7, count 0 2006.286.05:04:01.74#ibcon#read 6, iclass 7, count 0 2006.286.05:04:01.74#ibcon#end of sib2, iclass 7, count 0 2006.286.05:04:01.74#ibcon#*after write, iclass 7, count 0 2006.286.05:04:01.74#ibcon#*before return 0, iclass 7, count 0 2006.286.05:04:01.74#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:04:01.74#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:04:01.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.05:04:01.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.05:04:01.74$vck44/valo=2,534.99 2006.286.05:04:01.74#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.05:04:01.74#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.05:04:01.74#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:01.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:04:01.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:04:01.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:04:01.74#ibcon#enter wrdev, iclass 11, count 0 2006.286.05:04:01.74#ibcon#first serial, iclass 11, count 0 2006.286.05:04:01.74#ibcon#enter sib2, iclass 11, count 0 2006.286.05:04:01.74#ibcon#flushed, iclass 11, count 0 2006.286.05:04:01.74#ibcon#about to write, iclass 11, count 0 2006.286.05:04:01.74#ibcon#wrote, iclass 11, count 0 2006.286.05:04:01.74#ibcon#about to read 3, iclass 11, count 0 2006.286.05:04:01.76#ibcon#read 3, iclass 11, count 0 2006.286.05:04:01.76#ibcon#about to read 4, iclass 11, count 0 2006.286.05:04:01.76#ibcon#read 4, iclass 11, count 0 2006.286.05:04:01.76#ibcon#about to read 5, iclass 11, count 0 2006.286.05:04:01.76#ibcon#read 5, iclass 11, count 0 2006.286.05:04:01.76#ibcon#about to read 6, iclass 11, count 0 2006.286.05:04:01.76#ibcon#read 6, iclass 11, count 0 2006.286.05:04:01.76#ibcon#end of sib2, iclass 11, count 0 2006.286.05:04:01.76#ibcon#*mode == 0, iclass 11, count 0 2006.286.05:04:01.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.05:04:01.76#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.05:04:01.76#ibcon#*before write, iclass 11, count 0 2006.286.05:04:01.76#ibcon#enter sib2, iclass 11, count 0 2006.286.05:04:01.76#ibcon#flushed, iclass 11, count 0 2006.286.05:04:01.76#ibcon#about to write, iclass 11, count 0 2006.286.05:04:01.76#ibcon#wrote, iclass 11, count 0 2006.286.05:04:01.76#ibcon#about to read 3, iclass 11, count 0 2006.286.05:04:01.80#ibcon#read 3, iclass 11, count 0 2006.286.05:04:01.80#ibcon#about to read 4, iclass 11, count 0 2006.286.05:04:01.80#ibcon#read 4, iclass 11, count 0 2006.286.05:04:01.80#ibcon#about to read 5, iclass 11, count 0 2006.286.05:04:01.80#ibcon#read 5, iclass 11, count 0 2006.286.05:04:01.80#ibcon#about to read 6, iclass 11, count 0 2006.286.05:04:01.80#ibcon#read 6, iclass 11, count 0 2006.286.05:04:01.80#ibcon#end of sib2, iclass 11, count 0 2006.286.05:04:01.80#ibcon#*after write, iclass 11, count 0 2006.286.05:04:01.80#ibcon#*before return 0, iclass 11, count 0 2006.286.05:04:01.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:04:01.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:04:01.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.05:04:01.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.05:04:01.80$vck44/va=2,6 2006.286.05:04:01.80#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.05:04:01.80#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.05:04:01.80#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:01.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:04:01.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:04:01.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:04:01.86#ibcon#enter wrdev, iclass 13, count 2 2006.286.05:04:01.86#ibcon#first serial, iclass 13, count 2 2006.286.05:04:01.86#ibcon#enter sib2, iclass 13, count 2 2006.286.05:04:01.86#ibcon#flushed, iclass 13, count 2 2006.286.05:04:01.86#ibcon#about to write, iclass 13, count 2 2006.286.05:04:01.86#ibcon#wrote, iclass 13, count 2 2006.286.05:04:01.86#ibcon#about to read 3, iclass 13, count 2 2006.286.05:04:01.88#ibcon#read 3, iclass 13, count 2 2006.286.05:04:01.88#ibcon#about to read 4, iclass 13, count 2 2006.286.05:04:01.88#ibcon#read 4, iclass 13, count 2 2006.286.05:04:01.88#ibcon#about to read 5, iclass 13, count 2 2006.286.05:04:01.88#ibcon#read 5, iclass 13, count 2 2006.286.05:04:01.88#ibcon#about to read 6, iclass 13, count 2 2006.286.05:04:01.88#ibcon#read 6, iclass 13, count 2 2006.286.05:04:01.88#ibcon#end of sib2, iclass 13, count 2 2006.286.05:04:01.88#ibcon#*mode == 0, iclass 13, count 2 2006.286.05:04:01.88#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.05:04:01.88#ibcon#[25=AT02-06\r\n] 2006.286.05:04:01.88#ibcon#*before write, iclass 13, count 2 2006.286.05:04:01.88#ibcon#enter sib2, iclass 13, count 2 2006.286.05:04:01.88#ibcon#flushed, iclass 13, count 2 2006.286.05:04:01.88#ibcon#about to write, iclass 13, count 2 2006.286.05:04:01.88#ibcon#wrote, iclass 13, count 2 2006.286.05:04:01.88#ibcon#about to read 3, iclass 13, count 2 2006.286.05:04:01.91#ibcon#read 3, iclass 13, count 2 2006.286.05:04:01.91#ibcon#about to read 4, iclass 13, count 2 2006.286.05:04:01.91#ibcon#read 4, iclass 13, count 2 2006.286.05:04:01.91#ibcon#about to read 5, iclass 13, count 2 2006.286.05:04:01.91#ibcon#read 5, iclass 13, count 2 2006.286.05:04:01.91#ibcon#about to read 6, iclass 13, count 2 2006.286.05:04:01.91#ibcon#read 6, iclass 13, count 2 2006.286.05:04:01.91#ibcon#end of sib2, iclass 13, count 2 2006.286.05:04:01.91#ibcon#*after write, iclass 13, count 2 2006.286.05:04:01.91#ibcon#*before return 0, iclass 13, count 2 2006.286.05:04:01.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:04:01.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:04:01.91#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.05:04:01.91#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:01.91#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:04:02.03#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:04:02.03#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:04:02.03#ibcon#enter wrdev, iclass 13, count 0 2006.286.05:04:02.03#ibcon#first serial, iclass 13, count 0 2006.286.05:04:02.03#ibcon#enter sib2, iclass 13, count 0 2006.286.05:04:02.03#ibcon#flushed, iclass 13, count 0 2006.286.05:04:02.03#ibcon#about to write, iclass 13, count 0 2006.286.05:04:02.03#ibcon#wrote, iclass 13, count 0 2006.286.05:04:02.03#ibcon#about to read 3, iclass 13, count 0 2006.286.05:04:02.05#ibcon#read 3, iclass 13, count 0 2006.286.05:04:02.05#ibcon#about to read 4, iclass 13, count 0 2006.286.05:04:02.05#ibcon#read 4, iclass 13, count 0 2006.286.05:04:02.05#ibcon#about to read 5, iclass 13, count 0 2006.286.05:04:02.05#ibcon#read 5, iclass 13, count 0 2006.286.05:04:02.05#ibcon#about to read 6, iclass 13, count 0 2006.286.05:04:02.05#ibcon#read 6, iclass 13, count 0 2006.286.05:04:02.05#ibcon#end of sib2, iclass 13, count 0 2006.286.05:04:02.05#ibcon#*mode == 0, iclass 13, count 0 2006.286.05:04:02.05#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.05:04:02.05#ibcon#[25=USB\r\n] 2006.286.05:04:02.05#ibcon#*before write, iclass 13, count 0 2006.286.05:04:02.05#ibcon#enter sib2, iclass 13, count 0 2006.286.05:04:02.05#ibcon#flushed, iclass 13, count 0 2006.286.05:04:02.05#ibcon#about to write, iclass 13, count 0 2006.286.05:04:02.05#ibcon#wrote, iclass 13, count 0 2006.286.05:04:02.05#ibcon#about to read 3, iclass 13, count 0 2006.286.05:04:02.08#ibcon#read 3, iclass 13, count 0 2006.286.05:04:02.45#ibcon#about to read 4, iclass 13, count 0 2006.286.05:04:02.45#ibcon#read 4, iclass 13, count 0 2006.286.05:04:02.45#ibcon#about to read 5, iclass 13, count 0 2006.286.05:04:02.45#ibcon#read 5, iclass 13, count 0 2006.286.05:04:02.45#ibcon#about to read 6, iclass 13, count 0 2006.286.05:04:02.45#ibcon#read 6, iclass 13, count 0 2006.286.05:04:02.45#ibcon#end of sib2, iclass 13, count 0 2006.286.05:04:02.45#ibcon#*after write, iclass 13, count 0 2006.286.05:04:02.45#ibcon#*before return 0, iclass 13, count 0 2006.286.05:04:02.45#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:04:02.45#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:04:02.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.05:04:02.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.05:04:02.45$vck44/valo=3,564.99 2006.286.05:04:02.45#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.05:04:02.45#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.05:04:02.45#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:02.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:04:02.45#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:04:02.45#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:04:02.45#ibcon#enter wrdev, iclass 15, count 0 2006.286.05:04:02.45#ibcon#first serial, iclass 15, count 0 2006.286.05:04:02.45#ibcon#enter sib2, iclass 15, count 0 2006.286.05:04:02.45#ibcon#flushed, iclass 15, count 0 2006.286.05:04:02.45#ibcon#about to write, iclass 15, count 0 2006.286.05:04:02.45#ibcon#wrote, iclass 15, count 0 2006.286.05:04:02.45#ibcon#about to read 3, iclass 15, count 0 2006.286.05:04:02.47#ibcon#read 3, iclass 15, count 0 2006.286.05:04:02.47#ibcon#about to read 4, iclass 15, count 0 2006.286.05:04:02.47#ibcon#read 4, iclass 15, count 0 2006.286.05:04:02.47#ibcon#about to read 5, iclass 15, count 0 2006.286.05:04:02.47#ibcon#read 5, iclass 15, count 0 2006.286.05:04:02.47#ibcon#about to read 6, iclass 15, count 0 2006.286.05:04:02.47#ibcon#read 6, iclass 15, count 0 2006.286.05:04:02.47#ibcon#end of sib2, iclass 15, count 0 2006.286.05:04:02.47#ibcon#*mode == 0, iclass 15, count 0 2006.286.05:04:02.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.05:04:02.47#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.05:04:02.47#ibcon#*before write, iclass 15, count 0 2006.286.05:04:02.47#ibcon#enter sib2, iclass 15, count 0 2006.286.05:04:02.47#ibcon#flushed, iclass 15, count 0 2006.286.05:04:02.47#ibcon#about to write, iclass 15, count 0 2006.286.05:04:02.47#ibcon#wrote, iclass 15, count 0 2006.286.05:04:02.47#ibcon#about to read 3, iclass 15, count 0 2006.286.05:04:02.51#ibcon#read 3, iclass 15, count 0 2006.286.05:04:02.51#ibcon#about to read 4, iclass 15, count 0 2006.286.05:04:02.51#ibcon#read 4, iclass 15, count 0 2006.286.05:04:02.51#ibcon#about to read 5, iclass 15, count 0 2006.286.05:04:02.51#ibcon#read 5, iclass 15, count 0 2006.286.05:04:02.51#ibcon#about to read 6, iclass 15, count 0 2006.286.05:04:02.51#ibcon#read 6, iclass 15, count 0 2006.286.05:04:02.51#ibcon#end of sib2, iclass 15, count 0 2006.286.05:04:02.51#ibcon#*after write, iclass 15, count 0 2006.286.05:04:02.51#ibcon#*before return 0, iclass 15, count 0 2006.286.05:04:02.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:04:02.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:04:02.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.05:04:02.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.05:04:02.51$vck44/va=3,7 2006.286.05:04:02.51#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.05:04:02.51#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.05:04:02.51#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:02.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:04:02.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:04:02.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:04:02.57#ibcon#enter wrdev, iclass 17, count 2 2006.286.05:04:02.57#ibcon#first serial, iclass 17, count 2 2006.286.05:04:02.57#ibcon#enter sib2, iclass 17, count 2 2006.286.05:04:02.57#ibcon#flushed, iclass 17, count 2 2006.286.05:04:02.57#ibcon#about to write, iclass 17, count 2 2006.286.05:04:02.57#ibcon#wrote, iclass 17, count 2 2006.286.05:04:02.57#ibcon#about to read 3, iclass 17, count 2 2006.286.05:04:02.59#ibcon#read 3, iclass 17, count 2 2006.286.05:04:02.59#ibcon#about to read 4, iclass 17, count 2 2006.286.05:04:02.59#ibcon#read 4, iclass 17, count 2 2006.286.05:04:02.59#ibcon#about to read 5, iclass 17, count 2 2006.286.05:04:02.59#ibcon#read 5, iclass 17, count 2 2006.286.05:04:02.59#ibcon#about to read 6, iclass 17, count 2 2006.286.05:04:02.59#ibcon#read 6, iclass 17, count 2 2006.286.05:04:02.59#ibcon#end of sib2, iclass 17, count 2 2006.286.05:04:02.59#ibcon#*mode == 0, iclass 17, count 2 2006.286.05:04:02.59#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.05:04:02.59#ibcon#[25=AT03-07\r\n] 2006.286.05:04:02.59#ibcon#*before write, iclass 17, count 2 2006.286.05:04:02.59#ibcon#enter sib2, iclass 17, count 2 2006.286.05:04:02.59#ibcon#flushed, iclass 17, count 2 2006.286.05:04:02.59#ibcon#about to write, iclass 17, count 2 2006.286.05:04:02.59#ibcon#wrote, iclass 17, count 2 2006.286.05:04:02.59#ibcon#about to read 3, iclass 17, count 2 2006.286.05:04:02.62#ibcon#read 3, iclass 17, count 2 2006.286.05:04:02.62#ibcon#about to read 4, iclass 17, count 2 2006.286.05:04:02.62#ibcon#read 4, iclass 17, count 2 2006.286.05:04:02.62#ibcon#about to read 5, iclass 17, count 2 2006.286.05:04:02.62#ibcon#read 5, iclass 17, count 2 2006.286.05:04:02.62#ibcon#about to read 6, iclass 17, count 2 2006.286.05:04:02.62#ibcon#read 6, iclass 17, count 2 2006.286.05:04:02.62#ibcon#end of sib2, iclass 17, count 2 2006.286.05:04:02.62#ibcon#*after write, iclass 17, count 2 2006.286.05:04:02.62#ibcon#*before return 0, iclass 17, count 2 2006.286.05:04:02.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:04:02.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:04:02.62#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.05:04:02.62#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:02.62#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:04:02.74#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:04:02.74#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:04:02.74#ibcon#enter wrdev, iclass 17, count 0 2006.286.05:04:02.74#ibcon#first serial, iclass 17, count 0 2006.286.05:04:02.74#ibcon#enter sib2, iclass 17, count 0 2006.286.05:04:02.74#ibcon#flushed, iclass 17, count 0 2006.286.05:04:02.74#ibcon#about to write, iclass 17, count 0 2006.286.05:04:02.74#ibcon#wrote, iclass 17, count 0 2006.286.05:04:02.74#ibcon#about to read 3, iclass 17, count 0 2006.286.05:04:02.76#ibcon#read 3, iclass 17, count 0 2006.286.05:04:02.76#ibcon#about to read 4, iclass 17, count 0 2006.286.05:04:02.76#ibcon#read 4, iclass 17, count 0 2006.286.05:04:02.76#ibcon#about to read 5, iclass 17, count 0 2006.286.05:04:02.76#ibcon#read 5, iclass 17, count 0 2006.286.05:04:02.76#ibcon#about to read 6, iclass 17, count 0 2006.286.05:04:02.76#ibcon#read 6, iclass 17, count 0 2006.286.05:04:02.76#ibcon#end of sib2, iclass 17, count 0 2006.286.05:04:02.76#ibcon#*mode == 0, iclass 17, count 0 2006.286.05:04:02.76#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.05:04:02.76#ibcon#[25=USB\r\n] 2006.286.05:04:02.76#ibcon#*before write, iclass 17, count 0 2006.286.05:04:02.76#ibcon#enter sib2, iclass 17, count 0 2006.286.05:04:02.76#ibcon#flushed, iclass 17, count 0 2006.286.05:04:02.76#ibcon#about to write, iclass 17, count 0 2006.286.05:04:02.76#ibcon#wrote, iclass 17, count 0 2006.286.05:04:02.76#ibcon#about to read 3, iclass 17, count 0 2006.286.05:04:02.79#ibcon#read 3, iclass 17, count 0 2006.286.05:04:02.79#ibcon#about to read 4, iclass 17, count 0 2006.286.05:04:02.79#ibcon#read 4, iclass 17, count 0 2006.286.05:04:02.79#ibcon#about to read 5, iclass 17, count 0 2006.286.05:04:02.79#ibcon#read 5, iclass 17, count 0 2006.286.05:04:02.79#ibcon#about to read 6, iclass 17, count 0 2006.286.05:04:02.79#ibcon#read 6, iclass 17, count 0 2006.286.05:04:02.79#ibcon#end of sib2, iclass 17, count 0 2006.286.05:04:02.79#ibcon#*after write, iclass 17, count 0 2006.286.05:04:02.79#ibcon#*before return 0, iclass 17, count 0 2006.286.05:04:02.79#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:04:02.79#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:04:02.79#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.05:04:02.79#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.05:04:02.79$vck44/valo=4,624.99 2006.286.05:04:02.79#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.05:04:02.79#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.05:04:02.79#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:02.79#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:04:02.79#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:04:02.79#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:04:02.79#ibcon#enter wrdev, iclass 19, count 0 2006.286.05:04:02.79#ibcon#first serial, iclass 19, count 0 2006.286.05:04:02.79#ibcon#enter sib2, iclass 19, count 0 2006.286.05:04:02.79#ibcon#flushed, iclass 19, count 0 2006.286.05:04:02.97#ibcon#about to write, iclass 19, count 0 2006.286.05:04:02.97#ibcon#wrote, iclass 19, count 0 2006.286.05:04:02.97#ibcon#about to read 3, iclass 19, count 0 2006.286.05:04:02.99#ibcon#read 3, iclass 19, count 0 2006.286.05:04:02.99#ibcon#about to read 4, iclass 19, count 0 2006.286.05:04:02.99#ibcon#read 4, iclass 19, count 0 2006.286.05:04:02.99#ibcon#about to read 5, iclass 19, count 0 2006.286.05:04:02.99#ibcon#read 5, iclass 19, count 0 2006.286.05:04:02.99#ibcon#about to read 6, iclass 19, count 0 2006.286.05:04:02.99#ibcon#read 6, iclass 19, count 0 2006.286.05:04:02.99#ibcon#end of sib2, iclass 19, count 0 2006.286.05:04:02.99#ibcon#*mode == 0, iclass 19, count 0 2006.286.05:04:02.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.05:04:02.99#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.05:04:02.99#ibcon#*before write, iclass 19, count 0 2006.286.05:04:02.99#ibcon#enter sib2, iclass 19, count 0 2006.286.05:04:02.99#ibcon#flushed, iclass 19, count 0 2006.286.05:04:02.99#ibcon#about to write, iclass 19, count 0 2006.286.05:04:02.99#ibcon#wrote, iclass 19, count 0 2006.286.05:04:02.99#ibcon#about to read 3, iclass 19, count 0 2006.286.05:04:03.03#ibcon#read 3, iclass 19, count 0 2006.286.05:04:03.03#ibcon#about to read 4, iclass 19, count 0 2006.286.05:04:03.03#ibcon#read 4, iclass 19, count 0 2006.286.05:04:03.03#ibcon#about to read 5, iclass 19, count 0 2006.286.05:04:03.03#ibcon#read 5, iclass 19, count 0 2006.286.05:04:03.03#ibcon#about to read 6, iclass 19, count 0 2006.286.05:04:03.03#ibcon#read 6, iclass 19, count 0 2006.286.05:04:03.03#ibcon#end of sib2, iclass 19, count 0 2006.286.05:04:03.03#ibcon#*after write, iclass 19, count 0 2006.286.05:04:03.03#ibcon#*before return 0, iclass 19, count 0 2006.286.05:04:03.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:04:03.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:04:03.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.05:04:03.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.05:04:03.03$vck44/va=4,6 2006.286.05:04:03.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.05:04:03.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.05:04:03.03#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:03.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:04:03.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:04:03.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:04:03.03#ibcon#enter wrdev, iclass 21, count 2 2006.286.05:04:03.03#ibcon#first serial, iclass 21, count 2 2006.286.05:04:03.03#ibcon#enter sib2, iclass 21, count 2 2006.286.05:04:03.03#ibcon#flushed, iclass 21, count 2 2006.286.05:04:03.03#ibcon#about to write, iclass 21, count 2 2006.286.05:04:03.03#ibcon#wrote, iclass 21, count 2 2006.286.05:04:03.03#ibcon#about to read 3, iclass 21, count 2 2006.286.05:04:03.05#ibcon#read 3, iclass 21, count 2 2006.286.05:04:03.05#ibcon#about to read 4, iclass 21, count 2 2006.286.05:04:03.05#ibcon#read 4, iclass 21, count 2 2006.286.05:04:03.05#ibcon#about to read 5, iclass 21, count 2 2006.286.05:04:03.05#ibcon#read 5, iclass 21, count 2 2006.286.05:04:03.05#ibcon#about to read 6, iclass 21, count 2 2006.286.05:04:03.05#ibcon#read 6, iclass 21, count 2 2006.286.05:04:03.05#ibcon#end of sib2, iclass 21, count 2 2006.286.05:04:03.05#ibcon#*mode == 0, iclass 21, count 2 2006.286.05:04:03.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.05:04:03.05#ibcon#[25=AT04-06\r\n] 2006.286.05:04:03.05#ibcon#*before write, iclass 21, count 2 2006.286.05:04:03.05#ibcon#enter sib2, iclass 21, count 2 2006.286.05:04:03.05#ibcon#flushed, iclass 21, count 2 2006.286.05:04:03.05#ibcon#about to write, iclass 21, count 2 2006.286.05:04:03.05#ibcon#wrote, iclass 21, count 2 2006.286.05:04:03.05#ibcon#about to read 3, iclass 21, count 2 2006.286.05:04:03.08#ibcon#read 3, iclass 21, count 2 2006.286.05:04:03.08#ibcon#about to read 4, iclass 21, count 2 2006.286.05:04:03.08#ibcon#read 4, iclass 21, count 2 2006.286.05:04:03.08#ibcon#about to read 5, iclass 21, count 2 2006.286.05:04:03.08#ibcon#read 5, iclass 21, count 2 2006.286.05:04:03.08#ibcon#about to read 6, iclass 21, count 2 2006.286.05:04:03.08#ibcon#read 6, iclass 21, count 2 2006.286.05:04:03.08#ibcon#end of sib2, iclass 21, count 2 2006.286.05:04:03.08#ibcon#*after write, iclass 21, count 2 2006.286.05:04:03.08#ibcon#*before return 0, iclass 21, count 2 2006.286.05:04:03.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:04:03.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:04:03.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.05:04:03.08#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:03.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:04:03.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:04:03.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:04:03.20#ibcon#enter wrdev, iclass 21, count 0 2006.286.05:04:03.20#ibcon#first serial, iclass 21, count 0 2006.286.05:04:03.20#ibcon#enter sib2, iclass 21, count 0 2006.286.05:04:03.20#ibcon#flushed, iclass 21, count 0 2006.286.05:04:03.20#ibcon#about to write, iclass 21, count 0 2006.286.05:04:03.20#ibcon#wrote, iclass 21, count 0 2006.286.05:04:03.20#ibcon#about to read 3, iclass 21, count 0 2006.286.05:04:03.22#ibcon#read 3, iclass 21, count 0 2006.286.05:04:03.22#ibcon#about to read 4, iclass 21, count 0 2006.286.05:04:03.22#ibcon#read 4, iclass 21, count 0 2006.286.05:04:03.22#ibcon#about to read 5, iclass 21, count 0 2006.286.05:04:03.22#ibcon#read 5, iclass 21, count 0 2006.286.05:04:03.22#ibcon#about to read 6, iclass 21, count 0 2006.286.05:04:03.22#ibcon#read 6, iclass 21, count 0 2006.286.05:04:03.22#ibcon#end of sib2, iclass 21, count 0 2006.286.05:04:03.22#ibcon#*mode == 0, iclass 21, count 0 2006.286.05:04:03.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.05:04:03.22#ibcon#[25=USB\r\n] 2006.286.05:04:03.22#ibcon#*before write, iclass 21, count 0 2006.286.05:04:03.22#ibcon#enter sib2, iclass 21, count 0 2006.286.05:04:03.22#ibcon#flushed, iclass 21, count 0 2006.286.05:04:03.22#ibcon#about to write, iclass 21, count 0 2006.286.05:04:03.22#ibcon#wrote, iclass 21, count 0 2006.286.05:04:03.22#ibcon#about to read 3, iclass 21, count 0 2006.286.05:04:03.25#ibcon#read 3, iclass 21, count 0 2006.286.05:04:03.25#ibcon#about to read 4, iclass 21, count 0 2006.286.05:04:03.25#ibcon#read 4, iclass 21, count 0 2006.286.05:04:03.25#ibcon#about to read 5, iclass 21, count 0 2006.286.05:04:03.25#ibcon#read 5, iclass 21, count 0 2006.286.05:04:03.25#ibcon#about to read 6, iclass 21, count 0 2006.286.05:04:03.25#ibcon#read 6, iclass 21, count 0 2006.286.05:04:03.25#ibcon#end of sib2, iclass 21, count 0 2006.286.05:04:03.25#ibcon#*after write, iclass 21, count 0 2006.286.05:04:03.25#ibcon#*before return 0, iclass 21, count 0 2006.286.05:04:03.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:04:03.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:04:03.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.05:04:03.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.05:04:03.25$vck44/valo=5,734.99 2006.286.05:04:03.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.05:04:03.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.05:04:03.25#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:03.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:04:03.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:04:03.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:04:03.25#ibcon#enter wrdev, iclass 23, count 0 2006.286.05:04:03.25#ibcon#first serial, iclass 23, count 0 2006.286.05:04:03.25#ibcon#enter sib2, iclass 23, count 0 2006.286.05:04:03.25#ibcon#flushed, iclass 23, count 0 2006.286.05:04:03.25#ibcon#about to write, iclass 23, count 0 2006.286.05:04:03.25#ibcon#wrote, iclass 23, count 0 2006.286.05:04:03.25#ibcon#about to read 3, iclass 23, count 0 2006.286.05:04:03.27#ibcon#read 3, iclass 23, count 0 2006.286.05:04:03.27#ibcon#about to read 4, iclass 23, count 0 2006.286.05:04:03.27#ibcon#read 4, iclass 23, count 0 2006.286.05:04:03.27#ibcon#about to read 5, iclass 23, count 0 2006.286.05:04:03.27#ibcon#read 5, iclass 23, count 0 2006.286.05:04:03.27#ibcon#about to read 6, iclass 23, count 0 2006.286.05:04:03.27#ibcon#read 6, iclass 23, count 0 2006.286.05:04:03.27#ibcon#end of sib2, iclass 23, count 0 2006.286.05:04:03.27#ibcon#*mode == 0, iclass 23, count 0 2006.286.05:04:03.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.05:04:03.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.05:04:03.27#ibcon#*before write, iclass 23, count 0 2006.286.05:04:03.27#ibcon#enter sib2, iclass 23, count 0 2006.286.05:04:03.27#ibcon#flushed, iclass 23, count 0 2006.286.05:04:03.27#ibcon#about to write, iclass 23, count 0 2006.286.05:04:03.27#ibcon#wrote, iclass 23, count 0 2006.286.05:04:03.27#ibcon#about to read 3, iclass 23, count 0 2006.286.05:04:03.31#ibcon#read 3, iclass 23, count 0 2006.286.05:04:03.31#ibcon#about to read 4, iclass 23, count 0 2006.286.05:04:03.31#ibcon#read 4, iclass 23, count 0 2006.286.05:04:03.31#ibcon#about to read 5, iclass 23, count 0 2006.286.05:04:03.31#ibcon#read 5, iclass 23, count 0 2006.286.05:04:03.31#ibcon#about to read 6, iclass 23, count 0 2006.286.05:04:03.31#ibcon#read 6, iclass 23, count 0 2006.286.05:04:03.31#ibcon#end of sib2, iclass 23, count 0 2006.286.05:04:03.31#ibcon#*after write, iclass 23, count 0 2006.286.05:04:03.31#ibcon#*before return 0, iclass 23, count 0 2006.286.05:04:03.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:04:03.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:04:03.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.05:04:03.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.05:04:03.31$vck44/va=5,3 2006.286.05:04:03.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.05:04:03.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.05:04:03.31#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:03.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:04:03.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:04:03.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:04:03.37#ibcon#enter wrdev, iclass 25, count 2 2006.286.05:04:03.37#ibcon#first serial, iclass 25, count 2 2006.286.05:04:03.37#ibcon#enter sib2, iclass 25, count 2 2006.286.05:04:03.37#ibcon#flushed, iclass 25, count 2 2006.286.05:04:03.37#ibcon#about to write, iclass 25, count 2 2006.286.05:04:03.37#ibcon#wrote, iclass 25, count 2 2006.286.05:04:03.37#ibcon#about to read 3, iclass 25, count 2 2006.286.05:04:03.39#ibcon#read 3, iclass 25, count 2 2006.286.05:04:03.39#ibcon#about to read 4, iclass 25, count 2 2006.286.05:04:03.39#ibcon#read 4, iclass 25, count 2 2006.286.05:04:03.39#ibcon#about to read 5, iclass 25, count 2 2006.286.05:04:03.39#ibcon#read 5, iclass 25, count 2 2006.286.05:04:03.39#ibcon#about to read 6, iclass 25, count 2 2006.286.05:04:03.39#ibcon#read 6, iclass 25, count 2 2006.286.05:04:03.39#ibcon#end of sib2, iclass 25, count 2 2006.286.05:04:03.39#ibcon#*mode == 0, iclass 25, count 2 2006.286.05:04:03.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.05:04:03.39#ibcon#[25=AT05-03\r\n] 2006.286.05:04:03.39#ibcon#*before write, iclass 25, count 2 2006.286.05:04:03.39#ibcon#enter sib2, iclass 25, count 2 2006.286.05:04:03.39#ibcon#flushed, iclass 25, count 2 2006.286.05:04:03.39#ibcon#about to write, iclass 25, count 2 2006.286.05:04:03.39#ibcon#wrote, iclass 25, count 2 2006.286.05:04:03.39#ibcon#about to read 3, iclass 25, count 2 2006.286.05:04:03.42#ibcon#read 3, iclass 25, count 2 2006.286.05:04:03.42#ibcon#about to read 4, iclass 25, count 2 2006.286.05:04:03.42#ibcon#read 4, iclass 25, count 2 2006.286.05:04:03.42#ibcon#about to read 5, iclass 25, count 2 2006.286.05:04:03.42#ibcon#read 5, iclass 25, count 2 2006.286.05:04:03.42#ibcon#about to read 6, iclass 25, count 2 2006.286.05:04:03.42#ibcon#read 6, iclass 25, count 2 2006.286.05:04:03.42#ibcon#end of sib2, iclass 25, count 2 2006.286.05:04:03.42#ibcon#*after write, iclass 25, count 2 2006.286.05:04:03.42#ibcon#*before return 0, iclass 25, count 2 2006.286.05:04:03.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:04:03.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:04:03.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.05:04:03.42#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:03.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:04:03.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:04:03.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:04:03.54#ibcon#enter wrdev, iclass 25, count 0 2006.286.05:04:03.54#ibcon#first serial, iclass 25, count 0 2006.286.05:04:03.54#ibcon#enter sib2, iclass 25, count 0 2006.286.05:04:03.54#ibcon#flushed, iclass 25, count 0 2006.286.05:04:03.54#ibcon#about to write, iclass 25, count 0 2006.286.05:04:03.54#ibcon#wrote, iclass 25, count 0 2006.286.05:04:03.54#ibcon#about to read 3, iclass 25, count 0 2006.286.05:04:03.56#ibcon#read 3, iclass 25, count 0 2006.286.05:04:03.56#ibcon#about to read 4, iclass 25, count 0 2006.286.05:04:03.56#ibcon#read 4, iclass 25, count 0 2006.286.05:04:03.56#ibcon#about to read 5, iclass 25, count 0 2006.286.05:04:03.56#ibcon#read 5, iclass 25, count 0 2006.286.05:04:03.56#ibcon#about to read 6, iclass 25, count 0 2006.286.05:04:03.56#ibcon#read 6, iclass 25, count 0 2006.286.05:04:03.56#ibcon#end of sib2, iclass 25, count 0 2006.286.05:04:03.56#ibcon#*mode == 0, iclass 25, count 0 2006.286.05:04:03.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.05:04:03.56#ibcon#[25=USB\r\n] 2006.286.05:04:03.56#ibcon#*before write, iclass 25, count 0 2006.286.05:04:03.56#ibcon#enter sib2, iclass 25, count 0 2006.286.05:04:03.56#ibcon#flushed, iclass 25, count 0 2006.286.05:04:03.56#ibcon#about to write, iclass 25, count 0 2006.286.05:04:03.56#ibcon#wrote, iclass 25, count 0 2006.286.05:04:03.56#ibcon#about to read 3, iclass 25, count 0 2006.286.05:04:03.59#ibcon#read 3, iclass 25, count 0 2006.286.05:04:03.59#ibcon#about to read 4, iclass 25, count 0 2006.286.05:04:03.59#ibcon#read 4, iclass 25, count 0 2006.286.05:04:03.59#ibcon#about to read 5, iclass 25, count 0 2006.286.05:04:03.59#ibcon#read 5, iclass 25, count 0 2006.286.05:04:03.59#ibcon#about to read 6, iclass 25, count 0 2006.286.05:04:03.59#ibcon#read 6, iclass 25, count 0 2006.286.05:04:03.59#ibcon#end of sib2, iclass 25, count 0 2006.286.05:04:03.59#ibcon#*after write, iclass 25, count 0 2006.286.05:04:03.59#ibcon#*before return 0, iclass 25, count 0 2006.286.05:04:03.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:04:03.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:04:03.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.05:04:03.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.05:04:03.59$vck44/valo=6,814.99 2006.286.05:04:03.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.05:04:03.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.05:04:03.59#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:03.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:04:03.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:04:03.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:04:03.59#ibcon#enter wrdev, iclass 27, count 0 2006.286.05:04:03.59#ibcon#first serial, iclass 27, count 0 2006.286.05:04:03.59#ibcon#enter sib2, iclass 27, count 0 2006.286.05:04:03.59#ibcon#flushed, iclass 27, count 0 2006.286.05:04:03.59#ibcon#about to write, iclass 27, count 0 2006.286.05:04:03.59#ibcon#wrote, iclass 27, count 0 2006.286.05:04:03.59#ibcon#about to read 3, iclass 27, count 0 2006.286.05:04:03.61#ibcon#read 3, iclass 27, count 0 2006.286.05:04:03.61#ibcon#about to read 4, iclass 27, count 0 2006.286.05:04:03.61#ibcon#read 4, iclass 27, count 0 2006.286.05:04:03.61#ibcon#about to read 5, iclass 27, count 0 2006.286.05:04:03.61#ibcon#read 5, iclass 27, count 0 2006.286.05:04:03.61#ibcon#about to read 6, iclass 27, count 0 2006.286.05:04:03.61#ibcon#read 6, iclass 27, count 0 2006.286.05:04:03.61#ibcon#end of sib2, iclass 27, count 0 2006.286.05:04:03.61#ibcon#*mode == 0, iclass 27, count 0 2006.286.05:04:03.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.05:04:03.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.05:04:03.61#ibcon#*before write, iclass 27, count 0 2006.286.05:04:03.61#ibcon#enter sib2, iclass 27, count 0 2006.286.05:04:03.61#ibcon#flushed, iclass 27, count 0 2006.286.05:04:03.61#ibcon#about to write, iclass 27, count 0 2006.286.05:04:03.61#ibcon#wrote, iclass 27, count 0 2006.286.05:04:03.61#ibcon#about to read 3, iclass 27, count 0 2006.286.05:04:03.65#ibcon#read 3, iclass 27, count 0 2006.286.05:04:03.65#ibcon#about to read 4, iclass 27, count 0 2006.286.05:04:03.65#ibcon#read 4, iclass 27, count 0 2006.286.05:04:03.65#ibcon#about to read 5, iclass 27, count 0 2006.286.05:04:03.65#ibcon#read 5, iclass 27, count 0 2006.286.05:04:03.65#ibcon#about to read 6, iclass 27, count 0 2006.286.05:04:03.65#ibcon#read 6, iclass 27, count 0 2006.286.05:04:03.65#ibcon#end of sib2, iclass 27, count 0 2006.286.05:04:03.65#ibcon#*after write, iclass 27, count 0 2006.286.05:04:03.65#ibcon#*before return 0, iclass 27, count 0 2006.286.05:04:03.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:04:03.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:04:03.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.05:04:03.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.05:04:03.65$vck44/va=6,4 2006.286.05:04:03.65#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.05:04:03.65#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.05:04:03.65#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:03.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:04:03.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:04:03.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:04:03.71#ibcon#enter wrdev, iclass 29, count 2 2006.286.05:04:03.71#ibcon#first serial, iclass 29, count 2 2006.286.05:04:03.71#ibcon#enter sib2, iclass 29, count 2 2006.286.05:04:03.71#ibcon#flushed, iclass 29, count 2 2006.286.05:04:03.71#ibcon#about to write, iclass 29, count 2 2006.286.05:04:03.71#ibcon#wrote, iclass 29, count 2 2006.286.05:04:03.71#ibcon#about to read 3, iclass 29, count 2 2006.286.05:04:03.73#ibcon#read 3, iclass 29, count 2 2006.286.05:04:03.73#ibcon#about to read 4, iclass 29, count 2 2006.286.05:04:03.73#ibcon#read 4, iclass 29, count 2 2006.286.05:04:03.73#ibcon#about to read 5, iclass 29, count 2 2006.286.05:04:03.73#ibcon#read 5, iclass 29, count 2 2006.286.05:04:03.73#ibcon#about to read 6, iclass 29, count 2 2006.286.05:04:03.73#ibcon#read 6, iclass 29, count 2 2006.286.05:04:03.73#ibcon#end of sib2, iclass 29, count 2 2006.286.05:04:03.73#ibcon#*mode == 0, iclass 29, count 2 2006.286.05:04:03.73#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.05:04:03.73#ibcon#[25=AT06-04\r\n] 2006.286.05:04:03.73#ibcon#*before write, iclass 29, count 2 2006.286.05:04:03.73#ibcon#enter sib2, iclass 29, count 2 2006.286.05:04:03.73#ibcon#flushed, iclass 29, count 2 2006.286.05:04:03.73#ibcon#about to write, iclass 29, count 2 2006.286.05:04:03.73#ibcon#wrote, iclass 29, count 2 2006.286.05:04:03.73#ibcon#about to read 3, iclass 29, count 2 2006.286.05:04:03.76#ibcon#read 3, iclass 29, count 2 2006.286.05:04:03.76#ibcon#about to read 4, iclass 29, count 2 2006.286.05:04:03.76#ibcon#read 4, iclass 29, count 2 2006.286.05:04:03.76#ibcon#about to read 5, iclass 29, count 2 2006.286.05:04:03.76#ibcon#read 5, iclass 29, count 2 2006.286.05:04:03.76#ibcon#about to read 6, iclass 29, count 2 2006.286.05:04:03.76#ibcon#read 6, iclass 29, count 2 2006.286.05:04:03.76#ibcon#end of sib2, iclass 29, count 2 2006.286.05:04:03.76#ibcon#*after write, iclass 29, count 2 2006.286.05:04:03.76#ibcon#*before return 0, iclass 29, count 2 2006.286.05:04:03.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:04:03.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:04:03.76#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.05:04:03.76#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:03.76#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:04:03.88#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:04:03.88#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:04:03.88#ibcon#enter wrdev, iclass 29, count 0 2006.286.05:04:03.88#ibcon#first serial, iclass 29, count 0 2006.286.05:04:03.88#ibcon#enter sib2, iclass 29, count 0 2006.286.05:04:03.88#ibcon#flushed, iclass 29, count 0 2006.286.05:04:03.88#ibcon#about to write, iclass 29, count 0 2006.286.05:04:03.88#ibcon#wrote, iclass 29, count 0 2006.286.05:04:03.88#ibcon#about to read 3, iclass 29, count 0 2006.286.05:04:03.90#ibcon#read 3, iclass 29, count 0 2006.286.05:04:03.90#ibcon#about to read 4, iclass 29, count 0 2006.286.05:04:03.90#ibcon#read 4, iclass 29, count 0 2006.286.05:04:03.90#ibcon#about to read 5, iclass 29, count 0 2006.286.05:04:03.90#ibcon#read 5, iclass 29, count 0 2006.286.05:04:03.90#ibcon#about to read 6, iclass 29, count 0 2006.286.05:04:03.90#ibcon#read 6, iclass 29, count 0 2006.286.05:04:03.90#ibcon#end of sib2, iclass 29, count 0 2006.286.05:04:03.90#ibcon#*mode == 0, iclass 29, count 0 2006.286.05:04:03.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.05:04:03.90#ibcon#[25=USB\r\n] 2006.286.05:04:03.90#ibcon#*before write, iclass 29, count 0 2006.286.05:04:03.90#ibcon#enter sib2, iclass 29, count 0 2006.286.05:04:03.90#ibcon#flushed, iclass 29, count 0 2006.286.05:04:03.90#ibcon#about to write, iclass 29, count 0 2006.286.05:04:03.90#ibcon#wrote, iclass 29, count 0 2006.286.05:04:03.90#ibcon#about to read 3, iclass 29, count 0 2006.286.05:04:03.93#ibcon#read 3, iclass 29, count 0 2006.286.05:04:03.93#ibcon#about to read 4, iclass 29, count 0 2006.286.05:04:03.93#ibcon#read 4, iclass 29, count 0 2006.286.05:04:03.93#ibcon#about to read 5, iclass 29, count 0 2006.286.05:04:03.93#ibcon#read 5, iclass 29, count 0 2006.286.05:04:03.93#ibcon#about to read 6, iclass 29, count 0 2006.286.05:04:03.93#ibcon#read 6, iclass 29, count 0 2006.286.05:04:03.93#ibcon#end of sib2, iclass 29, count 0 2006.286.05:04:03.93#ibcon#*after write, iclass 29, count 0 2006.286.05:04:03.93#ibcon#*before return 0, iclass 29, count 0 2006.286.05:04:03.93#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:04:03.93#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:04:03.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.05:04:03.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.05:04:03.93$vck44/valo=7,864.99 2006.286.05:04:03.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.05:04:03.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.05:04:03.93#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:03.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:04:03.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:04:03.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:04:03.93#ibcon#enter wrdev, iclass 31, count 0 2006.286.05:04:03.93#ibcon#first serial, iclass 31, count 0 2006.286.05:04:03.93#ibcon#enter sib2, iclass 31, count 0 2006.286.05:04:03.93#ibcon#flushed, iclass 31, count 0 2006.286.05:04:03.93#ibcon#about to write, iclass 31, count 0 2006.286.05:04:03.93#ibcon#wrote, iclass 31, count 0 2006.286.05:04:03.93#ibcon#about to read 3, iclass 31, count 0 2006.286.05:04:03.95#ibcon#read 3, iclass 31, count 0 2006.286.05:04:03.95#ibcon#about to read 4, iclass 31, count 0 2006.286.05:04:03.95#ibcon#read 4, iclass 31, count 0 2006.286.05:04:03.95#ibcon#about to read 5, iclass 31, count 0 2006.286.05:04:03.95#ibcon#read 5, iclass 31, count 0 2006.286.05:04:03.95#ibcon#about to read 6, iclass 31, count 0 2006.286.05:04:03.95#ibcon#read 6, iclass 31, count 0 2006.286.05:04:03.95#ibcon#end of sib2, iclass 31, count 0 2006.286.05:04:03.95#ibcon#*mode == 0, iclass 31, count 0 2006.286.05:04:03.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.05:04:03.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.05:04:03.95#ibcon#*before write, iclass 31, count 0 2006.286.05:04:03.95#ibcon#enter sib2, iclass 31, count 0 2006.286.05:04:03.95#ibcon#flushed, iclass 31, count 0 2006.286.05:04:03.95#ibcon#about to write, iclass 31, count 0 2006.286.05:04:03.95#ibcon#wrote, iclass 31, count 0 2006.286.05:04:03.95#ibcon#about to read 3, iclass 31, count 0 2006.286.05:04:03.99#ibcon#read 3, iclass 31, count 0 2006.286.05:04:03.99#ibcon#about to read 4, iclass 31, count 0 2006.286.05:04:03.99#ibcon#read 4, iclass 31, count 0 2006.286.05:04:03.99#ibcon#about to read 5, iclass 31, count 0 2006.286.05:04:03.99#ibcon#read 5, iclass 31, count 0 2006.286.05:04:03.99#ibcon#about to read 6, iclass 31, count 0 2006.286.05:04:03.99#ibcon#read 6, iclass 31, count 0 2006.286.05:04:03.99#ibcon#end of sib2, iclass 31, count 0 2006.286.05:04:03.99#ibcon#*after write, iclass 31, count 0 2006.286.05:04:03.99#ibcon#*before return 0, iclass 31, count 0 2006.286.05:04:03.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:04:03.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:04:03.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.05:04:03.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.05:04:03.99$vck44/va=7,4 2006.286.05:04:04.12#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.05:04:04.12#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.05:04:04.12#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:04.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.05:04:04.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.05:04:04.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.05:04:04.12#ibcon#enter wrdev, iclass 33, count 2 2006.286.05:04:04.12#ibcon#first serial, iclass 33, count 2 2006.286.05:04:04.12#ibcon#enter sib2, iclass 33, count 2 2006.286.05:04:04.12#ibcon#flushed, iclass 33, count 2 2006.286.05:04:04.12#ibcon#about to write, iclass 33, count 2 2006.286.05:04:04.12#ibcon#wrote, iclass 33, count 2 2006.286.05:04:04.12#ibcon#about to read 3, iclass 33, count 2 2006.286.05:04:04.14#ibcon#read 3, iclass 33, count 2 2006.286.05:04:04.14#ibcon#about to read 4, iclass 33, count 2 2006.286.05:04:04.14#ibcon#read 4, iclass 33, count 2 2006.286.05:04:04.14#ibcon#about to read 5, iclass 33, count 2 2006.286.05:04:04.14#ibcon#read 5, iclass 33, count 2 2006.286.05:04:04.14#ibcon#about to read 6, iclass 33, count 2 2006.286.05:04:04.14#ibcon#read 6, iclass 33, count 2 2006.286.05:04:04.14#ibcon#end of sib2, iclass 33, count 2 2006.286.05:04:04.14#ibcon#*mode == 0, iclass 33, count 2 2006.286.05:04:04.14#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.05:04:04.14#ibcon#[25=AT07-04\r\n] 2006.286.05:04:04.14#ibcon#*before write, iclass 33, count 2 2006.286.05:04:04.14#ibcon#enter sib2, iclass 33, count 2 2006.286.05:04:04.14#ibcon#flushed, iclass 33, count 2 2006.286.05:04:04.14#ibcon#about to write, iclass 33, count 2 2006.286.05:04:04.14#ibcon#wrote, iclass 33, count 2 2006.286.05:04:04.14#ibcon#about to read 3, iclass 33, count 2 2006.286.05:04:04.17#ibcon#read 3, iclass 33, count 2 2006.286.05:04:04.17#ibcon#about to read 4, iclass 33, count 2 2006.286.05:04:04.17#ibcon#read 4, iclass 33, count 2 2006.286.05:04:04.17#ibcon#about to read 5, iclass 33, count 2 2006.286.05:04:04.17#ibcon#read 5, iclass 33, count 2 2006.286.05:04:04.17#ibcon#about to read 6, iclass 33, count 2 2006.286.05:04:04.17#ibcon#read 6, iclass 33, count 2 2006.286.05:04:04.17#ibcon#end of sib2, iclass 33, count 2 2006.286.05:04:04.17#ibcon#*after write, iclass 33, count 2 2006.286.05:04:04.17#ibcon#*before return 0, iclass 33, count 2 2006.286.05:04:04.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.05:04:04.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.05:04:04.17#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.05:04:04.17#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:04.17#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.05:04:04.29#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.05:04:04.29#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.05:04:04.29#ibcon#enter wrdev, iclass 33, count 0 2006.286.05:04:04.29#ibcon#first serial, iclass 33, count 0 2006.286.05:04:04.29#ibcon#enter sib2, iclass 33, count 0 2006.286.05:04:04.29#ibcon#flushed, iclass 33, count 0 2006.286.05:04:04.29#ibcon#about to write, iclass 33, count 0 2006.286.05:04:04.29#ibcon#wrote, iclass 33, count 0 2006.286.05:04:04.29#ibcon#about to read 3, iclass 33, count 0 2006.286.05:04:04.31#ibcon#read 3, iclass 33, count 0 2006.286.05:04:04.31#ibcon#about to read 4, iclass 33, count 0 2006.286.05:04:04.31#ibcon#read 4, iclass 33, count 0 2006.286.05:04:04.31#ibcon#about to read 5, iclass 33, count 0 2006.286.05:04:04.31#ibcon#read 5, iclass 33, count 0 2006.286.05:04:04.31#ibcon#about to read 6, iclass 33, count 0 2006.286.05:04:04.31#ibcon#read 6, iclass 33, count 0 2006.286.05:04:04.31#ibcon#end of sib2, iclass 33, count 0 2006.286.05:04:04.31#ibcon#*mode == 0, iclass 33, count 0 2006.286.05:04:04.31#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.05:04:04.31#ibcon#[25=USB\r\n] 2006.286.05:04:04.31#ibcon#*before write, iclass 33, count 0 2006.286.05:04:04.31#ibcon#enter sib2, iclass 33, count 0 2006.286.05:04:04.31#ibcon#flushed, iclass 33, count 0 2006.286.05:04:04.31#ibcon#about to write, iclass 33, count 0 2006.286.05:04:04.31#ibcon#wrote, iclass 33, count 0 2006.286.05:04:04.31#ibcon#about to read 3, iclass 33, count 0 2006.286.05:04:04.34#ibcon#read 3, iclass 33, count 0 2006.286.05:04:04.34#ibcon#about to read 4, iclass 33, count 0 2006.286.05:04:04.34#ibcon#read 4, iclass 33, count 0 2006.286.05:04:04.34#ibcon#about to read 5, iclass 33, count 0 2006.286.05:04:04.34#ibcon#read 5, iclass 33, count 0 2006.286.05:04:04.34#ibcon#about to read 6, iclass 33, count 0 2006.286.05:04:04.34#ibcon#read 6, iclass 33, count 0 2006.286.05:04:04.34#ibcon#end of sib2, iclass 33, count 0 2006.286.05:04:04.34#ibcon#*after write, iclass 33, count 0 2006.286.05:04:04.34#ibcon#*before return 0, iclass 33, count 0 2006.286.05:04:04.34#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.05:04:04.34#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.05:04:04.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.05:04:04.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.05:04:04.34$vck44/valo=8,884.99 2006.286.05:04:04.34#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.05:04:04.34#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.05:04:04.34#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:04.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:04:04.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:04:04.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:04:04.34#ibcon#enter wrdev, iclass 35, count 0 2006.286.05:04:04.34#ibcon#first serial, iclass 35, count 0 2006.286.05:04:04.34#ibcon#enter sib2, iclass 35, count 0 2006.286.05:04:04.34#ibcon#flushed, iclass 35, count 0 2006.286.05:04:04.34#ibcon#about to write, iclass 35, count 0 2006.286.05:04:04.34#ibcon#wrote, iclass 35, count 0 2006.286.05:04:04.34#ibcon#about to read 3, iclass 35, count 0 2006.286.05:04:04.36#ibcon#read 3, iclass 35, count 0 2006.286.05:04:04.36#ibcon#about to read 4, iclass 35, count 0 2006.286.05:04:04.36#ibcon#read 4, iclass 35, count 0 2006.286.05:04:04.36#ibcon#about to read 5, iclass 35, count 0 2006.286.05:04:04.36#ibcon#read 5, iclass 35, count 0 2006.286.05:04:04.36#ibcon#about to read 6, iclass 35, count 0 2006.286.05:04:04.36#ibcon#read 6, iclass 35, count 0 2006.286.05:04:04.36#ibcon#end of sib2, iclass 35, count 0 2006.286.05:04:04.36#ibcon#*mode == 0, iclass 35, count 0 2006.286.05:04:04.36#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.05:04:04.36#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.05:04:04.36#ibcon#*before write, iclass 35, count 0 2006.286.05:04:04.36#ibcon#enter sib2, iclass 35, count 0 2006.286.05:04:04.36#ibcon#flushed, iclass 35, count 0 2006.286.05:04:04.36#ibcon#about to write, iclass 35, count 0 2006.286.05:04:04.36#ibcon#wrote, iclass 35, count 0 2006.286.05:04:04.36#ibcon#about to read 3, iclass 35, count 0 2006.286.05:04:04.40#ibcon#read 3, iclass 35, count 0 2006.286.05:04:04.40#ibcon#about to read 4, iclass 35, count 0 2006.286.05:04:04.40#ibcon#read 4, iclass 35, count 0 2006.286.05:04:04.40#ibcon#about to read 5, iclass 35, count 0 2006.286.05:04:04.40#ibcon#read 5, iclass 35, count 0 2006.286.05:04:04.40#ibcon#about to read 6, iclass 35, count 0 2006.286.05:04:04.40#ibcon#read 6, iclass 35, count 0 2006.286.05:04:04.40#ibcon#end of sib2, iclass 35, count 0 2006.286.05:04:04.40#ibcon#*after write, iclass 35, count 0 2006.286.05:04:04.40#ibcon#*before return 0, iclass 35, count 0 2006.286.05:04:04.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:04:04.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:04:04.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.05:04:04.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.05:04:04.40$vck44/va=8,3 2006.286.05:04:04.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.05:04:04.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.05:04:04.40#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:04.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:04:04.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:04:04.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:04:04.46#ibcon#enter wrdev, iclass 37, count 2 2006.286.05:04:04.46#ibcon#first serial, iclass 37, count 2 2006.286.05:04:04.46#ibcon#enter sib2, iclass 37, count 2 2006.286.05:04:04.46#ibcon#flushed, iclass 37, count 2 2006.286.05:04:04.46#ibcon#about to write, iclass 37, count 2 2006.286.05:04:04.46#ibcon#wrote, iclass 37, count 2 2006.286.05:04:04.46#ibcon#about to read 3, iclass 37, count 2 2006.286.05:04:04.48#ibcon#read 3, iclass 37, count 2 2006.286.05:04:04.48#ibcon#about to read 4, iclass 37, count 2 2006.286.05:04:04.48#ibcon#read 4, iclass 37, count 2 2006.286.05:04:04.48#ibcon#about to read 5, iclass 37, count 2 2006.286.05:04:04.48#ibcon#read 5, iclass 37, count 2 2006.286.05:04:04.48#ibcon#about to read 6, iclass 37, count 2 2006.286.05:04:04.48#ibcon#read 6, iclass 37, count 2 2006.286.05:04:04.48#ibcon#end of sib2, iclass 37, count 2 2006.286.05:04:04.48#ibcon#*mode == 0, iclass 37, count 2 2006.286.05:04:04.48#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.05:04:04.48#ibcon#[25=AT08-03\r\n] 2006.286.05:04:04.48#ibcon#*before write, iclass 37, count 2 2006.286.05:04:04.48#ibcon#enter sib2, iclass 37, count 2 2006.286.05:04:04.48#ibcon#flushed, iclass 37, count 2 2006.286.05:04:04.48#ibcon#about to write, iclass 37, count 2 2006.286.05:04:04.48#ibcon#wrote, iclass 37, count 2 2006.286.05:04:04.48#ibcon#about to read 3, iclass 37, count 2 2006.286.05:04:04.51#ibcon#read 3, iclass 37, count 2 2006.286.05:04:04.51#ibcon#about to read 4, iclass 37, count 2 2006.286.05:04:04.51#ibcon#read 4, iclass 37, count 2 2006.286.05:04:04.51#ibcon#about to read 5, iclass 37, count 2 2006.286.05:04:04.51#ibcon#read 5, iclass 37, count 2 2006.286.05:04:04.51#ibcon#about to read 6, iclass 37, count 2 2006.286.05:04:04.51#ibcon#read 6, iclass 37, count 2 2006.286.05:04:04.51#ibcon#end of sib2, iclass 37, count 2 2006.286.05:04:04.51#ibcon#*after write, iclass 37, count 2 2006.286.05:04:04.51#ibcon#*before return 0, iclass 37, count 2 2006.286.05:04:04.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:04:04.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:04:04.51#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.05:04:04.51#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:04.51#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:04:04.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:04:04.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:04:04.63#ibcon#enter wrdev, iclass 37, count 0 2006.286.05:04:04.63#ibcon#first serial, iclass 37, count 0 2006.286.05:04:04.63#ibcon#enter sib2, iclass 37, count 0 2006.286.05:04:04.63#ibcon#flushed, iclass 37, count 0 2006.286.05:04:04.63#ibcon#about to write, iclass 37, count 0 2006.286.05:04:04.63#ibcon#wrote, iclass 37, count 0 2006.286.05:04:04.63#ibcon#about to read 3, iclass 37, count 0 2006.286.05:04:04.65#ibcon#read 3, iclass 37, count 0 2006.286.05:04:04.65#ibcon#about to read 4, iclass 37, count 0 2006.286.05:04:04.65#ibcon#read 4, iclass 37, count 0 2006.286.05:04:04.65#ibcon#about to read 5, iclass 37, count 0 2006.286.05:04:04.65#ibcon#read 5, iclass 37, count 0 2006.286.05:04:04.65#ibcon#about to read 6, iclass 37, count 0 2006.286.05:04:04.65#ibcon#read 6, iclass 37, count 0 2006.286.05:04:04.65#ibcon#end of sib2, iclass 37, count 0 2006.286.05:04:04.65#ibcon#*mode == 0, iclass 37, count 0 2006.286.05:04:04.65#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.05:04:04.65#ibcon#[25=USB\r\n] 2006.286.05:04:04.65#ibcon#*before write, iclass 37, count 0 2006.286.05:04:04.65#ibcon#enter sib2, iclass 37, count 0 2006.286.05:04:04.65#ibcon#flushed, iclass 37, count 0 2006.286.05:04:04.65#ibcon#about to write, iclass 37, count 0 2006.286.05:04:04.65#ibcon#wrote, iclass 37, count 0 2006.286.05:04:04.65#ibcon#about to read 3, iclass 37, count 0 2006.286.05:04:04.68#ibcon#read 3, iclass 37, count 0 2006.286.05:04:04.68#ibcon#about to read 4, iclass 37, count 0 2006.286.05:04:04.68#ibcon#read 4, iclass 37, count 0 2006.286.05:04:04.68#ibcon#about to read 5, iclass 37, count 0 2006.286.05:04:04.68#ibcon#read 5, iclass 37, count 0 2006.286.05:04:04.68#ibcon#about to read 6, iclass 37, count 0 2006.286.05:04:04.68#ibcon#read 6, iclass 37, count 0 2006.286.05:04:04.68#ibcon#end of sib2, iclass 37, count 0 2006.286.05:04:04.68#ibcon#*after write, iclass 37, count 0 2006.286.05:04:04.68#ibcon#*before return 0, iclass 37, count 0 2006.286.05:04:04.68#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:04:04.68#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:04:04.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.05:04:04.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.05:04:04.68$vck44/vblo=1,629.99 2006.286.05:04:04.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.05:04:04.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.05:04:04.68#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:04.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:04:04.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:04:04.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:04:04.68#ibcon#enter wrdev, iclass 39, count 0 2006.286.05:04:04.68#ibcon#first serial, iclass 39, count 0 2006.286.05:04:04.68#ibcon#enter sib2, iclass 39, count 0 2006.286.05:04:04.68#ibcon#flushed, iclass 39, count 0 2006.286.05:04:04.68#ibcon#about to write, iclass 39, count 0 2006.286.05:04:04.68#ibcon#wrote, iclass 39, count 0 2006.286.05:04:04.68#ibcon#about to read 3, iclass 39, count 0 2006.286.05:04:04.70#ibcon#read 3, iclass 39, count 0 2006.286.05:04:04.70#ibcon#about to read 4, iclass 39, count 0 2006.286.05:04:04.70#ibcon#read 4, iclass 39, count 0 2006.286.05:04:04.70#ibcon#about to read 5, iclass 39, count 0 2006.286.05:04:04.70#ibcon#read 5, iclass 39, count 0 2006.286.05:04:04.70#ibcon#about to read 6, iclass 39, count 0 2006.286.05:04:04.70#ibcon#read 6, iclass 39, count 0 2006.286.05:04:04.70#ibcon#end of sib2, iclass 39, count 0 2006.286.05:04:04.70#ibcon#*mode == 0, iclass 39, count 0 2006.286.05:04:04.70#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.05:04:04.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.05:04:04.70#ibcon#*before write, iclass 39, count 0 2006.286.05:04:04.70#ibcon#enter sib2, iclass 39, count 0 2006.286.05:04:04.70#ibcon#flushed, iclass 39, count 0 2006.286.05:04:04.70#ibcon#about to write, iclass 39, count 0 2006.286.05:04:04.70#ibcon#wrote, iclass 39, count 0 2006.286.05:04:04.70#ibcon#about to read 3, iclass 39, count 0 2006.286.05:04:04.74#ibcon#read 3, iclass 39, count 0 2006.286.05:04:04.74#ibcon#about to read 4, iclass 39, count 0 2006.286.05:04:04.74#ibcon#read 4, iclass 39, count 0 2006.286.05:04:04.74#ibcon#about to read 5, iclass 39, count 0 2006.286.05:04:04.74#ibcon#read 5, iclass 39, count 0 2006.286.05:04:04.74#ibcon#about to read 6, iclass 39, count 0 2006.286.05:04:04.74#ibcon#read 6, iclass 39, count 0 2006.286.05:04:04.74#ibcon#end of sib2, iclass 39, count 0 2006.286.05:04:04.74#ibcon#*after write, iclass 39, count 0 2006.286.05:04:04.74#ibcon#*before return 0, iclass 39, count 0 2006.286.05:04:04.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:04:04.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:04:04.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.05:04:04.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.05:04:04.74$vck44/vb=1,4 2006.286.05:04:04.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.05:04:04.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.05:04:04.74#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:04.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:04:04.74#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:04:04.74#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:04:04.74#ibcon#enter wrdev, iclass 3, count 2 2006.286.05:04:04.74#ibcon#first serial, iclass 3, count 2 2006.286.05:04:04.74#ibcon#enter sib2, iclass 3, count 2 2006.286.05:04:04.74#ibcon#flushed, iclass 3, count 2 2006.286.05:04:04.74#ibcon#about to write, iclass 3, count 2 2006.286.05:04:04.74#ibcon#wrote, iclass 3, count 2 2006.286.05:04:04.74#ibcon#about to read 3, iclass 3, count 2 2006.286.05:04:04.76#ibcon#read 3, iclass 3, count 2 2006.286.05:04:04.76#ibcon#about to read 4, iclass 3, count 2 2006.286.05:04:04.76#ibcon#read 4, iclass 3, count 2 2006.286.05:04:04.76#ibcon#about to read 5, iclass 3, count 2 2006.286.05:04:04.76#ibcon#read 5, iclass 3, count 2 2006.286.05:04:04.76#ibcon#about to read 6, iclass 3, count 2 2006.286.05:04:04.76#ibcon#read 6, iclass 3, count 2 2006.286.05:04:04.76#ibcon#end of sib2, iclass 3, count 2 2006.286.05:04:04.76#ibcon#*mode == 0, iclass 3, count 2 2006.286.05:04:04.76#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.05:04:04.76#ibcon#[27=AT01-04\r\n] 2006.286.05:04:04.76#ibcon#*before write, iclass 3, count 2 2006.286.05:04:04.76#ibcon#enter sib2, iclass 3, count 2 2006.286.05:04:04.76#ibcon#flushed, iclass 3, count 2 2006.286.05:04:04.76#ibcon#about to write, iclass 3, count 2 2006.286.05:04:04.76#ibcon#wrote, iclass 3, count 2 2006.286.05:04:04.76#ibcon#about to read 3, iclass 3, count 2 2006.286.05:04:04.79#ibcon#read 3, iclass 3, count 2 2006.286.05:04:04.79#ibcon#about to read 4, iclass 3, count 2 2006.286.05:04:04.79#ibcon#read 4, iclass 3, count 2 2006.286.05:04:04.79#ibcon#about to read 5, iclass 3, count 2 2006.286.05:04:04.79#ibcon#read 5, iclass 3, count 2 2006.286.05:04:04.79#ibcon#about to read 6, iclass 3, count 2 2006.286.05:04:04.79#ibcon#read 6, iclass 3, count 2 2006.286.05:04:04.79#ibcon#end of sib2, iclass 3, count 2 2006.286.05:04:04.79#ibcon#*after write, iclass 3, count 2 2006.286.05:04:04.79#ibcon#*before return 0, iclass 3, count 2 2006.286.05:04:04.79#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:04:04.79#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:04:04.79#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.05:04:04.79#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:04.79#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:04:04.91#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:04:04.91#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:04:04.91#ibcon#enter wrdev, iclass 3, count 0 2006.286.05:04:04.91#ibcon#first serial, iclass 3, count 0 2006.286.05:04:04.91#ibcon#enter sib2, iclass 3, count 0 2006.286.05:04:04.91#ibcon#flushed, iclass 3, count 0 2006.286.05:04:04.91#ibcon#about to write, iclass 3, count 0 2006.286.05:04:04.91#ibcon#wrote, iclass 3, count 0 2006.286.05:04:04.91#ibcon#about to read 3, iclass 3, count 0 2006.286.05:04:04.93#ibcon#read 3, iclass 3, count 0 2006.286.05:04:04.93#ibcon#about to read 4, iclass 3, count 0 2006.286.05:04:04.93#ibcon#read 4, iclass 3, count 0 2006.286.05:04:04.93#ibcon#about to read 5, iclass 3, count 0 2006.286.05:04:04.93#ibcon#read 5, iclass 3, count 0 2006.286.05:04:04.93#ibcon#about to read 6, iclass 3, count 0 2006.286.05:04:04.93#ibcon#read 6, iclass 3, count 0 2006.286.05:04:04.93#ibcon#end of sib2, iclass 3, count 0 2006.286.05:04:04.93#ibcon#*mode == 0, iclass 3, count 0 2006.286.05:04:04.93#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.05:04:04.93#ibcon#[27=USB\r\n] 2006.286.05:04:04.93#ibcon#*before write, iclass 3, count 0 2006.286.05:04:04.93#ibcon#enter sib2, iclass 3, count 0 2006.286.05:04:04.93#ibcon#flushed, iclass 3, count 0 2006.286.05:04:04.93#ibcon#about to write, iclass 3, count 0 2006.286.05:04:04.93#ibcon#wrote, iclass 3, count 0 2006.286.05:04:04.93#ibcon#about to read 3, iclass 3, count 0 2006.286.05:04:04.96#ibcon#read 3, iclass 3, count 0 2006.286.05:04:04.96#ibcon#about to read 4, iclass 3, count 0 2006.286.05:04:04.96#ibcon#read 4, iclass 3, count 0 2006.286.05:04:04.96#ibcon#about to read 5, iclass 3, count 0 2006.286.05:04:04.96#ibcon#read 5, iclass 3, count 0 2006.286.05:04:04.96#ibcon#about to read 6, iclass 3, count 0 2006.286.05:04:04.96#ibcon#read 6, iclass 3, count 0 2006.286.05:04:04.96#ibcon#end of sib2, iclass 3, count 0 2006.286.05:04:04.96#ibcon#*after write, iclass 3, count 0 2006.286.05:04:04.96#ibcon#*before return 0, iclass 3, count 0 2006.286.05:04:04.96#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:04:04.96#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:04:04.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.05:04:04.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.05:04:04.96$vck44/vblo=2,634.99 2006.286.05:04:04.96#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.05:04:04.96#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.05:04:04.96#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:04.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:04:04.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:04:04.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:04:04.96#ibcon#enter wrdev, iclass 5, count 0 2006.286.05:04:04.96#ibcon#first serial, iclass 5, count 0 2006.286.05:04:04.96#ibcon#enter sib2, iclass 5, count 0 2006.286.05:04:04.96#ibcon#flushed, iclass 5, count 0 2006.286.05:04:04.96#ibcon#about to write, iclass 5, count 0 2006.286.05:04:04.96#ibcon#wrote, iclass 5, count 0 2006.286.05:04:04.96#ibcon#about to read 3, iclass 5, count 0 2006.286.05:04:04.98#ibcon#read 3, iclass 5, count 0 2006.286.05:04:04.98#ibcon#about to read 4, iclass 5, count 0 2006.286.05:04:04.98#ibcon#read 4, iclass 5, count 0 2006.286.05:04:04.98#ibcon#about to read 5, iclass 5, count 0 2006.286.05:04:04.98#ibcon#read 5, iclass 5, count 0 2006.286.05:04:05.26#ibcon#about to read 6, iclass 5, count 0 2006.286.05:04:05.26#ibcon#read 6, iclass 5, count 0 2006.286.05:04:05.26#ibcon#end of sib2, iclass 5, count 0 2006.286.05:04:05.26#ibcon#*mode == 0, iclass 5, count 0 2006.286.05:04:05.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.05:04:05.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.05:04:05.26#ibcon#*before write, iclass 5, count 0 2006.286.05:04:05.26#ibcon#enter sib2, iclass 5, count 0 2006.286.05:04:05.26#ibcon#flushed, iclass 5, count 0 2006.286.05:04:05.26#ibcon#about to write, iclass 5, count 0 2006.286.05:04:05.26#ibcon#wrote, iclass 5, count 0 2006.286.05:04:05.26#ibcon#about to read 3, iclass 5, count 0 2006.286.05:04:05.31#ibcon#read 3, iclass 5, count 0 2006.286.05:04:05.31#ibcon#about to read 4, iclass 5, count 0 2006.286.05:04:05.31#ibcon#read 4, iclass 5, count 0 2006.286.05:04:05.31#ibcon#about to read 5, iclass 5, count 0 2006.286.05:04:05.31#ibcon#read 5, iclass 5, count 0 2006.286.05:04:05.31#ibcon#about to read 6, iclass 5, count 0 2006.286.05:04:05.31#ibcon#read 6, iclass 5, count 0 2006.286.05:04:05.31#ibcon#end of sib2, iclass 5, count 0 2006.286.05:04:05.31#ibcon#*after write, iclass 5, count 0 2006.286.05:04:05.31#ibcon#*before return 0, iclass 5, count 0 2006.286.05:04:05.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:04:05.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:04:05.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.05:04:05.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.05:04:05.31$vck44/vb=2,5 2006.286.05:04:05.31#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.05:04:05.31#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.05:04:05.31#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:05.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:04:05.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:04:05.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:04:05.31#ibcon#enter wrdev, iclass 7, count 2 2006.286.05:04:05.31#ibcon#first serial, iclass 7, count 2 2006.286.05:04:05.31#ibcon#enter sib2, iclass 7, count 2 2006.286.05:04:05.31#ibcon#flushed, iclass 7, count 2 2006.286.05:04:05.31#ibcon#about to write, iclass 7, count 2 2006.286.05:04:05.31#ibcon#wrote, iclass 7, count 2 2006.286.05:04:05.31#ibcon#about to read 3, iclass 7, count 2 2006.286.05:04:05.33#ibcon#read 3, iclass 7, count 2 2006.286.05:04:05.33#ibcon#about to read 4, iclass 7, count 2 2006.286.05:04:05.33#ibcon#read 4, iclass 7, count 2 2006.286.05:04:05.33#ibcon#about to read 5, iclass 7, count 2 2006.286.05:04:05.33#ibcon#read 5, iclass 7, count 2 2006.286.05:04:05.33#ibcon#about to read 6, iclass 7, count 2 2006.286.05:04:05.33#ibcon#read 6, iclass 7, count 2 2006.286.05:04:05.33#ibcon#end of sib2, iclass 7, count 2 2006.286.05:04:05.33#ibcon#*mode == 0, iclass 7, count 2 2006.286.05:04:05.33#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.05:04:05.33#ibcon#[27=AT02-05\r\n] 2006.286.05:04:05.33#ibcon#*before write, iclass 7, count 2 2006.286.05:04:05.33#ibcon#enter sib2, iclass 7, count 2 2006.286.05:04:05.33#ibcon#flushed, iclass 7, count 2 2006.286.05:04:05.33#ibcon#about to write, iclass 7, count 2 2006.286.05:04:05.33#ibcon#wrote, iclass 7, count 2 2006.286.05:04:05.33#ibcon#about to read 3, iclass 7, count 2 2006.286.05:04:05.36#ibcon#read 3, iclass 7, count 2 2006.286.05:04:05.36#ibcon#about to read 4, iclass 7, count 2 2006.286.05:04:05.36#ibcon#read 4, iclass 7, count 2 2006.286.05:04:05.36#ibcon#about to read 5, iclass 7, count 2 2006.286.05:04:05.36#ibcon#read 5, iclass 7, count 2 2006.286.05:04:05.36#ibcon#about to read 6, iclass 7, count 2 2006.286.05:04:05.36#ibcon#read 6, iclass 7, count 2 2006.286.05:04:05.36#ibcon#end of sib2, iclass 7, count 2 2006.286.05:04:05.36#ibcon#*after write, iclass 7, count 2 2006.286.05:04:05.36#ibcon#*before return 0, iclass 7, count 2 2006.286.05:04:05.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:04:05.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:04:05.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.05:04:05.36#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:05.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:04:05.48#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:04:05.48#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:04:05.48#ibcon#enter wrdev, iclass 7, count 0 2006.286.05:04:05.48#ibcon#first serial, iclass 7, count 0 2006.286.05:04:05.48#ibcon#enter sib2, iclass 7, count 0 2006.286.05:04:05.48#ibcon#flushed, iclass 7, count 0 2006.286.05:04:05.48#ibcon#about to write, iclass 7, count 0 2006.286.05:04:05.48#ibcon#wrote, iclass 7, count 0 2006.286.05:04:05.48#ibcon#about to read 3, iclass 7, count 0 2006.286.05:04:05.50#ibcon#read 3, iclass 7, count 0 2006.286.05:04:05.50#ibcon#about to read 4, iclass 7, count 0 2006.286.05:04:05.50#ibcon#read 4, iclass 7, count 0 2006.286.05:04:05.50#ibcon#about to read 5, iclass 7, count 0 2006.286.05:04:05.50#ibcon#read 5, iclass 7, count 0 2006.286.05:04:05.50#ibcon#about to read 6, iclass 7, count 0 2006.286.05:04:05.50#ibcon#read 6, iclass 7, count 0 2006.286.05:04:05.50#ibcon#end of sib2, iclass 7, count 0 2006.286.05:04:05.50#ibcon#*mode == 0, iclass 7, count 0 2006.286.05:04:05.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.05:04:05.50#ibcon#[27=USB\r\n] 2006.286.05:04:05.50#ibcon#*before write, iclass 7, count 0 2006.286.05:04:05.50#ibcon#enter sib2, iclass 7, count 0 2006.286.05:04:05.50#ibcon#flushed, iclass 7, count 0 2006.286.05:04:05.50#ibcon#about to write, iclass 7, count 0 2006.286.05:04:05.50#ibcon#wrote, iclass 7, count 0 2006.286.05:04:05.50#ibcon#about to read 3, iclass 7, count 0 2006.286.05:04:05.53#ibcon#read 3, iclass 7, count 0 2006.286.05:04:05.53#ibcon#about to read 4, iclass 7, count 0 2006.286.05:04:05.53#ibcon#read 4, iclass 7, count 0 2006.286.05:04:05.53#ibcon#about to read 5, iclass 7, count 0 2006.286.05:04:05.53#ibcon#read 5, iclass 7, count 0 2006.286.05:04:05.53#ibcon#about to read 6, iclass 7, count 0 2006.286.05:04:05.53#ibcon#read 6, iclass 7, count 0 2006.286.05:04:05.53#ibcon#end of sib2, iclass 7, count 0 2006.286.05:04:05.53#ibcon#*after write, iclass 7, count 0 2006.286.05:04:05.53#ibcon#*before return 0, iclass 7, count 0 2006.286.05:04:05.53#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:04:05.53#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:04:05.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.05:04:05.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.05:04:05.53$vck44/vblo=3,649.99 2006.286.05:04:05.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.05:04:05.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.05:04:05.53#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:05.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:04:05.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:04:05.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:04:05.53#ibcon#enter wrdev, iclass 11, count 0 2006.286.05:04:05.53#ibcon#first serial, iclass 11, count 0 2006.286.05:04:05.53#ibcon#enter sib2, iclass 11, count 0 2006.286.05:04:05.53#ibcon#flushed, iclass 11, count 0 2006.286.05:04:05.53#ibcon#about to write, iclass 11, count 0 2006.286.05:04:05.53#ibcon#wrote, iclass 11, count 0 2006.286.05:04:05.53#ibcon#about to read 3, iclass 11, count 0 2006.286.05:04:05.55#ibcon#read 3, iclass 11, count 0 2006.286.05:04:05.55#ibcon#about to read 4, iclass 11, count 0 2006.286.05:04:05.55#ibcon#read 4, iclass 11, count 0 2006.286.05:04:05.55#ibcon#about to read 5, iclass 11, count 0 2006.286.05:04:05.55#ibcon#read 5, iclass 11, count 0 2006.286.05:04:05.55#ibcon#about to read 6, iclass 11, count 0 2006.286.05:04:05.55#ibcon#read 6, iclass 11, count 0 2006.286.05:04:05.55#ibcon#end of sib2, iclass 11, count 0 2006.286.05:04:05.55#ibcon#*mode == 0, iclass 11, count 0 2006.286.05:04:05.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.05:04:05.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.05:04:05.55#ibcon#*before write, iclass 11, count 0 2006.286.05:04:05.55#ibcon#enter sib2, iclass 11, count 0 2006.286.05:04:05.55#ibcon#flushed, iclass 11, count 0 2006.286.05:04:05.55#ibcon#about to write, iclass 11, count 0 2006.286.05:04:05.55#ibcon#wrote, iclass 11, count 0 2006.286.05:04:05.55#ibcon#about to read 3, iclass 11, count 0 2006.286.05:04:05.59#ibcon#read 3, iclass 11, count 0 2006.286.05:04:05.59#ibcon#about to read 4, iclass 11, count 0 2006.286.05:04:05.59#ibcon#read 4, iclass 11, count 0 2006.286.05:04:05.59#ibcon#about to read 5, iclass 11, count 0 2006.286.05:04:05.59#ibcon#read 5, iclass 11, count 0 2006.286.05:04:05.59#ibcon#about to read 6, iclass 11, count 0 2006.286.05:04:05.59#ibcon#read 6, iclass 11, count 0 2006.286.05:04:05.59#ibcon#end of sib2, iclass 11, count 0 2006.286.05:04:05.59#ibcon#*after write, iclass 11, count 0 2006.286.05:04:05.59#ibcon#*before return 0, iclass 11, count 0 2006.286.05:04:05.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:04:05.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:04:05.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.05:04:05.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.05:04:05.59$vck44/vb=3,4 2006.286.05:04:05.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.05:04:05.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.05:04:05.59#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:05.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:04:05.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:04:05.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:04:05.65#ibcon#enter wrdev, iclass 13, count 2 2006.286.05:04:05.65#ibcon#first serial, iclass 13, count 2 2006.286.05:04:05.65#ibcon#enter sib2, iclass 13, count 2 2006.286.05:04:05.65#ibcon#flushed, iclass 13, count 2 2006.286.05:04:05.65#ibcon#about to write, iclass 13, count 2 2006.286.05:04:05.65#ibcon#wrote, iclass 13, count 2 2006.286.05:04:05.65#ibcon#about to read 3, iclass 13, count 2 2006.286.05:04:05.67#ibcon#read 3, iclass 13, count 2 2006.286.05:04:05.67#ibcon#about to read 4, iclass 13, count 2 2006.286.05:04:05.67#ibcon#read 4, iclass 13, count 2 2006.286.05:04:05.67#ibcon#about to read 5, iclass 13, count 2 2006.286.05:04:05.67#ibcon#read 5, iclass 13, count 2 2006.286.05:04:05.67#ibcon#about to read 6, iclass 13, count 2 2006.286.05:04:05.67#ibcon#read 6, iclass 13, count 2 2006.286.05:04:05.67#ibcon#end of sib2, iclass 13, count 2 2006.286.05:04:05.67#ibcon#*mode == 0, iclass 13, count 2 2006.286.05:04:05.67#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.05:04:05.67#ibcon#[27=AT03-04\r\n] 2006.286.05:04:05.67#ibcon#*before write, iclass 13, count 2 2006.286.05:04:05.67#ibcon#enter sib2, iclass 13, count 2 2006.286.05:04:05.67#ibcon#flushed, iclass 13, count 2 2006.286.05:04:05.67#ibcon#about to write, iclass 13, count 2 2006.286.05:04:05.67#ibcon#wrote, iclass 13, count 2 2006.286.05:04:05.67#ibcon#about to read 3, iclass 13, count 2 2006.286.05:04:05.70#ibcon#read 3, iclass 13, count 2 2006.286.05:04:05.70#ibcon#about to read 4, iclass 13, count 2 2006.286.05:04:05.70#ibcon#read 4, iclass 13, count 2 2006.286.05:04:05.70#ibcon#about to read 5, iclass 13, count 2 2006.286.05:04:05.70#ibcon#read 5, iclass 13, count 2 2006.286.05:04:05.70#ibcon#about to read 6, iclass 13, count 2 2006.286.05:04:05.70#ibcon#read 6, iclass 13, count 2 2006.286.05:04:05.70#ibcon#end of sib2, iclass 13, count 2 2006.286.05:04:05.70#ibcon#*after write, iclass 13, count 2 2006.286.05:04:05.70#ibcon#*before return 0, iclass 13, count 2 2006.286.05:04:05.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:04:05.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:04:05.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.05:04:05.70#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:05.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:04:05.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:04:05.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:04:05.82#ibcon#enter wrdev, iclass 13, count 0 2006.286.05:04:05.82#ibcon#first serial, iclass 13, count 0 2006.286.05:04:05.82#ibcon#enter sib2, iclass 13, count 0 2006.286.05:04:05.82#ibcon#flushed, iclass 13, count 0 2006.286.05:04:05.82#ibcon#about to write, iclass 13, count 0 2006.286.05:04:05.82#ibcon#wrote, iclass 13, count 0 2006.286.05:04:05.82#ibcon#about to read 3, iclass 13, count 0 2006.286.05:04:05.84#ibcon#read 3, iclass 13, count 0 2006.286.05:04:05.84#ibcon#about to read 4, iclass 13, count 0 2006.286.05:04:05.84#ibcon#read 4, iclass 13, count 0 2006.286.05:04:05.84#ibcon#about to read 5, iclass 13, count 0 2006.286.05:04:05.84#ibcon#read 5, iclass 13, count 0 2006.286.05:04:05.84#ibcon#about to read 6, iclass 13, count 0 2006.286.05:04:05.84#ibcon#read 6, iclass 13, count 0 2006.286.05:04:05.84#ibcon#end of sib2, iclass 13, count 0 2006.286.05:04:05.84#ibcon#*mode == 0, iclass 13, count 0 2006.286.05:04:05.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.05:04:05.84#ibcon#[27=USB\r\n] 2006.286.05:04:05.84#ibcon#*before write, iclass 13, count 0 2006.286.05:04:05.84#ibcon#enter sib2, iclass 13, count 0 2006.286.05:04:05.84#ibcon#flushed, iclass 13, count 0 2006.286.05:04:05.84#ibcon#about to write, iclass 13, count 0 2006.286.05:04:05.84#ibcon#wrote, iclass 13, count 0 2006.286.05:04:05.84#ibcon#about to read 3, iclass 13, count 0 2006.286.05:04:05.87#ibcon#read 3, iclass 13, count 0 2006.286.05:04:05.87#ibcon#about to read 4, iclass 13, count 0 2006.286.05:04:05.87#ibcon#read 4, iclass 13, count 0 2006.286.05:04:05.87#ibcon#about to read 5, iclass 13, count 0 2006.286.05:04:05.87#ibcon#read 5, iclass 13, count 0 2006.286.05:04:05.87#ibcon#about to read 6, iclass 13, count 0 2006.286.05:04:05.87#ibcon#read 6, iclass 13, count 0 2006.286.05:04:05.87#ibcon#end of sib2, iclass 13, count 0 2006.286.05:04:05.87#ibcon#*after write, iclass 13, count 0 2006.286.05:04:05.87#ibcon#*before return 0, iclass 13, count 0 2006.286.05:04:05.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:04:05.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:04:05.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.05:04:05.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.05:04:05.87$vck44/vblo=4,679.99 2006.286.05:04:05.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.05:04:05.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.05:04:05.87#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:05.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:04:05.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:04:05.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:04:05.87#ibcon#enter wrdev, iclass 15, count 0 2006.286.05:04:05.87#ibcon#first serial, iclass 15, count 0 2006.286.05:04:05.87#ibcon#enter sib2, iclass 15, count 0 2006.286.05:04:05.87#ibcon#flushed, iclass 15, count 0 2006.286.05:04:05.87#ibcon#about to write, iclass 15, count 0 2006.286.05:04:05.87#ibcon#wrote, iclass 15, count 0 2006.286.05:04:05.87#ibcon#about to read 3, iclass 15, count 0 2006.286.05:04:05.89#ibcon#read 3, iclass 15, count 0 2006.286.05:04:05.89#ibcon#about to read 4, iclass 15, count 0 2006.286.05:04:05.89#ibcon#read 4, iclass 15, count 0 2006.286.05:04:05.89#ibcon#about to read 5, iclass 15, count 0 2006.286.05:04:05.89#ibcon#read 5, iclass 15, count 0 2006.286.05:04:05.89#ibcon#about to read 6, iclass 15, count 0 2006.286.05:04:05.89#ibcon#read 6, iclass 15, count 0 2006.286.05:04:05.89#ibcon#end of sib2, iclass 15, count 0 2006.286.05:04:05.89#ibcon#*mode == 0, iclass 15, count 0 2006.286.05:04:05.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.05:04:05.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.05:04:05.89#ibcon#*before write, iclass 15, count 0 2006.286.05:04:05.89#ibcon#enter sib2, iclass 15, count 0 2006.286.05:04:05.89#ibcon#flushed, iclass 15, count 0 2006.286.05:04:05.89#ibcon#about to write, iclass 15, count 0 2006.286.05:04:05.89#ibcon#wrote, iclass 15, count 0 2006.286.05:04:05.89#ibcon#about to read 3, iclass 15, count 0 2006.286.05:04:05.93#ibcon#read 3, iclass 15, count 0 2006.286.05:04:05.93#ibcon#about to read 4, iclass 15, count 0 2006.286.05:04:05.93#ibcon#read 4, iclass 15, count 0 2006.286.05:04:05.93#ibcon#about to read 5, iclass 15, count 0 2006.286.05:04:05.93#ibcon#read 5, iclass 15, count 0 2006.286.05:04:05.93#ibcon#about to read 6, iclass 15, count 0 2006.286.05:04:05.93#ibcon#read 6, iclass 15, count 0 2006.286.05:04:05.93#ibcon#end of sib2, iclass 15, count 0 2006.286.05:04:05.93#ibcon#*after write, iclass 15, count 0 2006.286.05:04:05.93#ibcon#*before return 0, iclass 15, count 0 2006.286.05:04:05.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:04:05.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:04:05.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.05:04:05.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.05:04:05.93$vck44/vb=4,5 2006.286.05:04:05.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.05:04:05.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.05:04:05.93#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:05.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:04:05.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:04:05.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:04:05.99#ibcon#enter wrdev, iclass 17, count 2 2006.286.05:04:05.99#ibcon#first serial, iclass 17, count 2 2006.286.05:04:05.99#ibcon#enter sib2, iclass 17, count 2 2006.286.05:04:05.99#ibcon#flushed, iclass 17, count 2 2006.286.05:04:05.99#ibcon#about to write, iclass 17, count 2 2006.286.05:04:05.99#ibcon#wrote, iclass 17, count 2 2006.286.05:04:05.99#ibcon#about to read 3, iclass 17, count 2 2006.286.05:04:06.01#ibcon#read 3, iclass 17, count 2 2006.286.05:04:06.01#ibcon#about to read 4, iclass 17, count 2 2006.286.05:04:06.01#ibcon#read 4, iclass 17, count 2 2006.286.05:04:06.01#ibcon#about to read 5, iclass 17, count 2 2006.286.05:04:06.01#ibcon#read 5, iclass 17, count 2 2006.286.05:04:06.01#ibcon#about to read 6, iclass 17, count 2 2006.286.05:04:06.01#ibcon#read 6, iclass 17, count 2 2006.286.05:04:06.01#ibcon#end of sib2, iclass 17, count 2 2006.286.05:04:06.01#ibcon#*mode == 0, iclass 17, count 2 2006.286.05:04:06.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.05:04:06.01#ibcon#[27=AT04-05\r\n] 2006.286.05:04:06.01#ibcon#*before write, iclass 17, count 2 2006.286.05:04:06.01#ibcon#enter sib2, iclass 17, count 2 2006.286.05:04:06.01#ibcon#flushed, iclass 17, count 2 2006.286.05:04:06.01#ibcon#about to write, iclass 17, count 2 2006.286.05:04:06.01#ibcon#wrote, iclass 17, count 2 2006.286.05:04:06.01#ibcon#about to read 3, iclass 17, count 2 2006.286.05:04:06.04#ibcon#read 3, iclass 17, count 2 2006.286.05:04:06.04#ibcon#about to read 4, iclass 17, count 2 2006.286.05:04:06.04#ibcon#read 4, iclass 17, count 2 2006.286.05:04:06.04#ibcon#about to read 5, iclass 17, count 2 2006.286.05:04:06.04#ibcon#read 5, iclass 17, count 2 2006.286.05:04:06.04#ibcon#about to read 6, iclass 17, count 2 2006.286.05:04:06.04#ibcon#read 6, iclass 17, count 2 2006.286.05:04:06.04#ibcon#end of sib2, iclass 17, count 2 2006.286.05:04:06.04#ibcon#*after write, iclass 17, count 2 2006.286.05:04:06.04#ibcon#*before return 0, iclass 17, count 2 2006.286.05:04:06.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:04:06.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:04:06.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.05:04:06.04#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:06.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:04:06.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:04:06.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:04:06.16#ibcon#enter wrdev, iclass 17, count 0 2006.286.05:04:06.16#ibcon#first serial, iclass 17, count 0 2006.286.05:04:06.16#ibcon#enter sib2, iclass 17, count 0 2006.286.05:04:06.16#ibcon#flushed, iclass 17, count 0 2006.286.05:04:06.16#ibcon#about to write, iclass 17, count 0 2006.286.05:04:06.16#ibcon#wrote, iclass 17, count 0 2006.286.05:04:06.16#ibcon#about to read 3, iclass 17, count 0 2006.286.05:04:06.18#ibcon#read 3, iclass 17, count 0 2006.286.05:04:06.18#ibcon#about to read 4, iclass 17, count 0 2006.286.05:04:06.18#ibcon#read 4, iclass 17, count 0 2006.286.05:04:06.18#ibcon#about to read 5, iclass 17, count 0 2006.286.05:04:06.18#ibcon#read 5, iclass 17, count 0 2006.286.05:04:06.18#ibcon#about to read 6, iclass 17, count 0 2006.286.05:04:06.18#ibcon#read 6, iclass 17, count 0 2006.286.05:04:06.18#ibcon#end of sib2, iclass 17, count 0 2006.286.05:04:06.18#ibcon#*mode == 0, iclass 17, count 0 2006.286.05:04:06.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.05:04:06.18#ibcon#[27=USB\r\n] 2006.286.05:04:06.18#ibcon#*before write, iclass 17, count 0 2006.286.05:04:06.18#ibcon#enter sib2, iclass 17, count 0 2006.286.05:04:06.18#ibcon#flushed, iclass 17, count 0 2006.286.05:04:06.18#ibcon#about to write, iclass 17, count 0 2006.286.05:04:06.18#ibcon#wrote, iclass 17, count 0 2006.286.05:04:06.18#ibcon#about to read 3, iclass 17, count 0 2006.286.05:04:06.21#ibcon#read 3, iclass 17, count 0 2006.286.05:04:06.21#ibcon#about to read 4, iclass 17, count 0 2006.286.05:04:06.21#ibcon#read 4, iclass 17, count 0 2006.286.05:04:06.21#ibcon#about to read 5, iclass 17, count 0 2006.286.05:04:06.21#ibcon#read 5, iclass 17, count 0 2006.286.05:04:06.21#ibcon#about to read 6, iclass 17, count 0 2006.286.05:04:06.21#ibcon#read 6, iclass 17, count 0 2006.286.05:04:06.21#ibcon#end of sib2, iclass 17, count 0 2006.286.05:04:06.21#ibcon#*after write, iclass 17, count 0 2006.286.05:04:06.21#ibcon#*before return 0, iclass 17, count 0 2006.286.05:04:06.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:04:06.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:04:06.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.05:04:06.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.05:04:06.21$vck44/vblo=5,709.99 2006.286.05:04:06.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.05:04:06.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.05:04:06.21#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:06.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:04:06.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:04:06.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:04:06.21#ibcon#enter wrdev, iclass 19, count 0 2006.286.05:04:06.21#ibcon#first serial, iclass 19, count 0 2006.286.05:04:06.21#ibcon#enter sib2, iclass 19, count 0 2006.286.05:04:06.21#ibcon#flushed, iclass 19, count 0 2006.286.05:04:06.21#ibcon#about to write, iclass 19, count 0 2006.286.05:04:06.21#ibcon#wrote, iclass 19, count 0 2006.286.05:04:06.21#ibcon#about to read 3, iclass 19, count 0 2006.286.05:04:06.23#ibcon#read 3, iclass 19, count 0 2006.286.05:04:06.23#ibcon#about to read 4, iclass 19, count 0 2006.286.05:04:06.23#ibcon#read 4, iclass 19, count 0 2006.286.05:04:06.23#ibcon#about to read 5, iclass 19, count 0 2006.286.05:04:06.23#ibcon#read 5, iclass 19, count 0 2006.286.05:04:06.23#ibcon#about to read 6, iclass 19, count 0 2006.286.05:04:06.23#ibcon#read 6, iclass 19, count 0 2006.286.05:04:06.23#ibcon#end of sib2, iclass 19, count 0 2006.286.05:04:06.23#ibcon#*mode == 0, iclass 19, count 0 2006.286.05:04:06.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.05:04:06.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.05:04:06.23#ibcon#*before write, iclass 19, count 0 2006.286.05:04:06.23#ibcon#enter sib2, iclass 19, count 0 2006.286.05:04:06.23#ibcon#flushed, iclass 19, count 0 2006.286.05:04:06.23#ibcon#about to write, iclass 19, count 0 2006.286.05:04:06.23#ibcon#wrote, iclass 19, count 0 2006.286.05:04:06.23#ibcon#about to read 3, iclass 19, count 0 2006.286.05:04:06.27#ibcon#read 3, iclass 19, count 0 2006.286.05:04:06.27#ibcon#about to read 4, iclass 19, count 0 2006.286.05:04:06.27#ibcon#read 4, iclass 19, count 0 2006.286.05:04:06.27#ibcon#about to read 5, iclass 19, count 0 2006.286.05:04:06.27#ibcon#read 5, iclass 19, count 0 2006.286.05:04:06.27#ibcon#about to read 6, iclass 19, count 0 2006.286.05:04:06.27#ibcon#read 6, iclass 19, count 0 2006.286.05:04:06.27#ibcon#end of sib2, iclass 19, count 0 2006.286.05:04:06.27#ibcon#*after write, iclass 19, count 0 2006.286.05:04:06.27#ibcon#*before return 0, iclass 19, count 0 2006.286.05:04:06.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:04:06.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:04:06.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.05:04:06.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.05:04:06.27$vck44/vb=5,4 2006.286.05:04:06.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.05:04:06.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.05:04:06.27#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:06.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:04:06.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:04:06.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:04:06.33#ibcon#enter wrdev, iclass 21, count 2 2006.286.05:04:06.33#ibcon#first serial, iclass 21, count 2 2006.286.05:04:06.33#ibcon#enter sib2, iclass 21, count 2 2006.286.05:04:06.33#ibcon#flushed, iclass 21, count 2 2006.286.05:04:06.33#ibcon#about to write, iclass 21, count 2 2006.286.05:04:06.33#ibcon#wrote, iclass 21, count 2 2006.286.05:04:06.33#ibcon#about to read 3, iclass 21, count 2 2006.286.05:04:06.35#ibcon#read 3, iclass 21, count 2 2006.286.05:04:06.35#ibcon#about to read 4, iclass 21, count 2 2006.286.05:04:06.35#ibcon#read 4, iclass 21, count 2 2006.286.05:04:06.35#ibcon#about to read 5, iclass 21, count 2 2006.286.05:04:06.35#ibcon#read 5, iclass 21, count 2 2006.286.05:04:06.35#ibcon#about to read 6, iclass 21, count 2 2006.286.05:04:06.35#ibcon#read 6, iclass 21, count 2 2006.286.05:04:06.35#ibcon#end of sib2, iclass 21, count 2 2006.286.05:04:06.35#ibcon#*mode == 0, iclass 21, count 2 2006.286.05:04:06.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.05:04:06.35#ibcon#[27=AT05-04\r\n] 2006.286.05:04:06.35#ibcon#*before write, iclass 21, count 2 2006.286.05:04:06.35#ibcon#enter sib2, iclass 21, count 2 2006.286.05:04:06.35#ibcon#flushed, iclass 21, count 2 2006.286.05:04:06.35#ibcon#about to write, iclass 21, count 2 2006.286.05:04:06.35#ibcon#wrote, iclass 21, count 2 2006.286.05:04:06.35#ibcon#about to read 3, iclass 21, count 2 2006.286.05:04:06.38#ibcon#read 3, iclass 21, count 2 2006.286.05:04:06.38#ibcon#about to read 4, iclass 21, count 2 2006.286.05:04:06.38#ibcon#read 4, iclass 21, count 2 2006.286.05:04:06.38#ibcon#about to read 5, iclass 21, count 2 2006.286.05:04:06.38#ibcon#read 5, iclass 21, count 2 2006.286.05:04:06.38#ibcon#about to read 6, iclass 21, count 2 2006.286.05:04:06.38#ibcon#read 6, iclass 21, count 2 2006.286.05:04:06.38#ibcon#end of sib2, iclass 21, count 2 2006.286.05:04:06.38#ibcon#*after write, iclass 21, count 2 2006.286.05:04:06.38#ibcon#*before return 0, iclass 21, count 2 2006.286.05:04:06.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:04:06.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:04:06.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.05:04:06.38#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:06.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:04:06.50#abcon#<5=/04 3.3 8.6 22.06 761015.0\r\n> 2006.286.05:04:06.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:04:06.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:04:06.50#ibcon#enter wrdev, iclass 21, count 0 2006.286.05:04:06.50#ibcon#first serial, iclass 21, count 0 2006.286.05:04:06.50#ibcon#enter sib2, iclass 21, count 0 2006.286.05:04:06.50#ibcon#flushed, iclass 21, count 0 2006.286.05:04:06.50#ibcon#about to write, iclass 21, count 0 2006.286.05:04:06.50#ibcon#wrote, iclass 21, count 0 2006.286.05:04:06.50#ibcon#about to read 3, iclass 21, count 0 2006.286.05:04:06.52#ibcon#read 3, iclass 21, count 0 2006.286.05:04:06.52#ibcon#about to read 4, iclass 21, count 0 2006.286.05:04:06.52#ibcon#read 4, iclass 21, count 0 2006.286.05:04:06.52#ibcon#about to read 5, iclass 21, count 0 2006.286.05:04:06.52#ibcon#read 5, iclass 21, count 0 2006.286.05:04:06.52#ibcon#about to read 6, iclass 21, count 0 2006.286.05:04:06.52#ibcon#read 6, iclass 21, count 0 2006.286.05:04:06.52#ibcon#end of sib2, iclass 21, count 0 2006.286.05:04:06.52#ibcon#*mode == 0, iclass 21, count 0 2006.286.05:04:06.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.05:04:06.52#ibcon#[27=USB\r\n] 2006.286.05:04:06.52#ibcon#*before write, iclass 21, count 0 2006.286.05:04:06.52#ibcon#enter sib2, iclass 21, count 0 2006.286.05:04:06.52#ibcon#flushed, iclass 21, count 0 2006.286.05:04:06.52#ibcon#about to write, iclass 21, count 0 2006.286.05:04:06.52#ibcon#wrote, iclass 21, count 0 2006.286.05:04:06.52#ibcon#about to read 3, iclass 21, count 0 2006.286.05:04:06.52#abcon#{5=INTERFACE CLEAR} 2006.286.05:04:06.55#ibcon#read 3, iclass 21, count 0 2006.286.05:04:06.55#ibcon#about to read 4, iclass 21, count 0 2006.286.05:04:06.55#ibcon#read 4, iclass 21, count 0 2006.286.05:04:06.55#ibcon#about to read 5, iclass 21, count 0 2006.286.05:04:06.55#ibcon#read 5, iclass 21, count 0 2006.286.05:04:06.55#ibcon#about to read 6, iclass 21, count 0 2006.286.05:04:06.55#ibcon#read 6, iclass 21, count 0 2006.286.05:04:06.55#ibcon#end of sib2, iclass 21, count 0 2006.286.05:04:06.55#ibcon#*after write, iclass 21, count 0 2006.286.05:04:06.55#ibcon#*before return 0, iclass 21, count 0 2006.286.05:04:06.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:04:06.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:04:06.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.05:04:06.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.05:04:06.55$vck44/vblo=6,719.99 2006.286.05:04:06.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.05:04:06.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.05:04:06.55#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:06.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:04:06.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:04:06.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:04:06.55#ibcon#enter wrdev, iclass 26, count 0 2006.286.05:04:06.55#ibcon#first serial, iclass 26, count 0 2006.286.05:04:06.55#ibcon#enter sib2, iclass 26, count 0 2006.286.05:04:06.55#ibcon#flushed, iclass 26, count 0 2006.286.05:04:06.55#ibcon#about to write, iclass 26, count 0 2006.286.05:04:06.55#ibcon#wrote, iclass 26, count 0 2006.286.05:04:06.55#ibcon#about to read 3, iclass 26, count 0 2006.286.05:04:06.57#ibcon#read 3, iclass 26, count 0 2006.286.05:04:06.57#ibcon#about to read 4, iclass 26, count 0 2006.286.05:04:06.57#ibcon#read 4, iclass 26, count 0 2006.286.05:04:06.57#ibcon#about to read 5, iclass 26, count 0 2006.286.05:04:06.57#ibcon#read 5, iclass 26, count 0 2006.286.05:04:06.57#ibcon#about to read 6, iclass 26, count 0 2006.286.05:04:06.57#ibcon#read 6, iclass 26, count 0 2006.286.05:04:06.57#ibcon#end of sib2, iclass 26, count 0 2006.286.05:04:06.57#ibcon#*mode == 0, iclass 26, count 0 2006.286.05:04:06.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.05:04:06.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.05:04:06.57#ibcon#*before write, iclass 26, count 0 2006.286.05:04:06.57#ibcon#enter sib2, iclass 26, count 0 2006.286.05:04:06.57#ibcon#flushed, iclass 26, count 0 2006.286.05:04:06.57#ibcon#about to write, iclass 26, count 0 2006.286.05:04:06.57#ibcon#wrote, iclass 26, count 0 2006.286.05:04:06.57#ibcon#about to read 3, iclass 26, count 0 2006.286.05:04:06.58#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:04:06.61#ibcon#read 3, iclass 26, count 0 2006.286.05:04:06.61#ibcon#about to read 4, iclass 26, count 0 2006.286.05:04:06.61#ibcon#read 4, iclass 26, count 0 2006.286.05:04:06.61#ibcon#about to read 5, iclass 26, count 0 2006.286.05:04:06.61#ibcon#read 5, iclass 26, count 0 2006.286.05:04:06.61#ibcon#about to read 6, iclass 26, count 0 2006.286.05:04:06.61#ibcon#read 6, iclass 26, count 0 2006.286.05:04:06.61#ibcon#end of sib2, iclass 26, count 0 2006.286.05:04:06.61#ibcon#*after write, iclass 26, count 0 2006.286.05:04:06.61#ibcon#*before return 0, iclass 26, count 0 2006.286.05:04:06.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:04:06.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:04:06.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.05:04:06.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.05:04:06.61$vck44/vb=6,3 2006.286.05:04:06.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.05:04:06.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.05:04:06.61#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:06.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:04:06.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:04:06.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:04:06.67#ibcon#enter wrdev, iclass 29, count 2 2006.286.05:04:06.67#ibcon#first serial, iclass 29, count 2 2006.286.05:04:06.67#ibcon#enter sib2, iclass 29, count 2 2006.286.05:04:06.67#ibcon#flushed, iclass 29, count 2 2006.286.05:04:06.67#ibcon#about to write, iclass 29, count 2 2006.286.05:04:06.67#ibcon#wrote, iclass 29, count 2 2006.286.05:04:06.67#ibcon#about to read 3, iclass 29, count 2 2006.286.05:04:06.69#ibcon#read 3, iclass 29, count 2 2006.286.05:04:06.69#ibcon#about to read 4, iclass 29, count 2 2006.286.05:04:06.69#ibcon#read 4, iclass 29, count 2 2006.286.05:04:06.69#ibcon#about to read 5, iclass 29, count 2 2006.286.05:04:06.69#ibcon#read 5, iclass 29, count 2 2006.286.05:04:06.69#ibcon#about to read 6, iclass 29, count 2 2006.286.05:04:06.69#ibcon#read 6, iclass 29, count 2 2006.286.05:04:06.69#ibcon#end of sib2, iclass 29, count 2 2006.286.05:04:06.69#ibcon#*mode == 0, iclass 29, count 2 2006.286.05:04:06.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.05:04:06.69#ibcon#[27=AT06-03\r\n] 2006.286.05:04:06.69#ibcon#*before write, iclass 29, count 2 2006.286.05:04:06.69#ibcon#enter sib2, iclass 29, count 2 2006.286.05:04:06.69#ibcon#flushed, iclass 29, count 2 2006.286.05:04:06.69#ibcon#about to write, iclass 29, count 2 2006.286.05:04:06.69#ibcon#wrote, iclass 29, count 2 2006.286.05:04:06.69#ibcon#about to read 3, iclass 29, count 2 2006.286.05:04:06.72#ibcon#read 3, iclass 29, count 2 2006.286.05:04:06.72#ibcon#about to read 4, iclass 29, count 2 2006.286.05:04:06.72#ibcon#read 4, iclass 29, count 2 2006.286.05:04:06.72#ibcon#about to read 5, iclass 29, count 2 2006.286.05:04:06.72#ibcon#read 5, iclass 29, count 2 2006.286.05:04:06.72#ibcon#about to read 6, iclass 29, count 2 2006.286.05:04:06.72#ibcon#read 6, iclass 29, count 2 2006.286.05:04:06.72#ibcon#end of sib2, iclass 29, count 2 2006.286.05:04:06.72#ibcon#*after write, iclass 29, count 2 2006.286.05:04:06.72#ibcon#*before return 0, iclass 29, count 2 2006.286.05:04:06.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:04:06.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:04:06.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.05:04:06.72#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:06.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:04:06.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:04:06.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:04:06.84#ibcon#enter wrdev, iclass 29, count 0 2006.286.05:04:06.84#ibcon#first serial, iclass 29, count 0 2006.286.05:04:06.84#ibcon#enter sib2, iclass 29, count 0 2006.286.05:04:06.84#ibcon#flushed, iclass 29, count 0 2006.286.05:04:06.84#ibcon#about to write, iclass 29, count 0 2006.286.05:04:06.84#ibcon#wrote, iclass 29, count 0 2006.286.05:04:06.84#ibcon#about to read 3, iclass 29, count 0 2006.286.05:04:06.86#ibcon#read 3, iclass 29, count 0 2006.286.05:04:06.86#ibcon#about to read 4, iclass 29, count 0 2006.286.05:04:06.86#ibcon#read 4, iclass 29, count 0 2006.286.05:04:06.86#ibcon#about to read 5, iclass 29, count 0 2006.286.05:04:06.86#ibcon#read 5, iclass 29, count 0 2006.286.05:04:06.86#ibcon#about to read 6, iclass 29, count 0 2006.286.05:04:06.86#ibcon#read 6, iclass 29, count 0 2006.286.05:04:06.86#ibcon#end of sib2, iclass 29, count 0 2006.286.05:04:06.86#ibcon#*mode == 0, iclass 29, count 0 2006.286.05:04:06.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.05:04:06.86#ibcon#[27=USB\r\n] 2006.286.05:04:06.86#ibcon#*before write, iclass 29, count 0 2006.286.05:04:06.86#ibcon#enter sib2, iclass 29, count 0 2006.286.05:04:06.86#ibcon#flushed, iclass 29, count 0 2006.286.05:04:06.86#ibcon#about to write, iclass 29, count 0 2006.286.05:04:06.86#ibcon#wrote, iclass 29, count 0 2006.286.05:04:06.86#ibcon#about to read 3, iclass 29, count 0 2006.286.05:04:06.89#ibcon#read 3, iclass 29, count 0 2006.286.05:04:06.89#ibcon#about to read 4, iclass 29, count 0 2006.286.05:04:06.89#ibcon#read 4, iclass 29, count 0 2006.286.05:04:06.89#ibcon#about to read 5, iclass 29, count 0 2006.286.05:04:06.89#ibcon#read 5, iclass 29, count 0 2006.286.05:04:06.89#ibcon#about to read 6, iclass 29, count 0 2006.286.05:04:06.89#ibcon#read 6, iclass 29, count 0 2006.286.05:04:06.89#ibcon#end of sib2, iclass 29, count 0 2006.286.05:04:06.89#ibcon#*after write, iclass 29, count 0 2006.286.05:04:06.89#ibcon#*before return 0, iclass 29, count 0 2006.286.05:04:06.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:04:06.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:04:06.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.05:04:06.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.05:04:06.89$vck44/vblo=7,734.99 2006.286.05:04:06.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.05:04:06.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.05:04:06.89#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:06.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:04:06.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:04:06.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:04:06.89#ibcon#enter wrdev, iclass 31, count 0 2006.286.05:04:06.89#ibcon#first serial, iclass 31, count 0 2006.286.05:04:06.89#ibcon#enter sib2, iclass 31, count 0 2006.286.05:04:06.89#ibcon#flushed, iclass 31, count 0 2006.286.05:04:06.89#ibcon#about to write, iclass 31, count 0 2006.286.05:04:06.89#ibcon#wrote, iclass 31, count 0 2006.286.05:04:06.89#ibcon#about to read 3, iclass 31, count 0 2006.286.05:04:06.91#ibcon#read 3, iclass 31, count 0 2006.286.05:04:06.91#ibcon#about to read 4, iclass 31, count 0 2006.286.05:04:06.91#ibcon#read 4, iclass 31, count 0 2006.286.05:04:06.91#ibcon#about to read 5, iclass 31, count 0 2006.286.05:04:06.91#ibcon#read 5, iclass 31, count 0 2006.286.05:04:06.91#ibcon#about to read 6, iclass 31, count 0 2006.286.05:04:06.91#ibcon#read 6, iclass 31, count 0 2006.286.05:04:06.91#ibcon#end of sib2, iclass 31, count 0 2006.286.05:04:06.91#ibcon#*mode == 0, iclass 31, count 0 2006.286.05:04:06.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.05:04:06.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.05:04:06.91#ibcon#*before write, iclass 31, count 0 2006.286.05:04:06.91#ibcon#enter sib2, iclass 31, count 0 2006.286.05:04:06.91#ibcon#flushed, iclass 31, count 0 2006.286.05:04:06.91#ibcon#about to write, iclass 31, count 0 2006.286.05:04:06.91#ibcon#wrote, iclass 31, count 0 2006.286.05:04:06.91#ibcon#about to read 3, iclass 31, count 0 2006.286.05:04:06.95#ibcon#read 3, iclass 31, count 0 2006.286.05:04:06.95#ibcon#about to read 4, iclass 31, count 0 2006.286.05:04:06.95#ibcon#read 4, iclass 31, count 0 2006.286.05:04:06.95#ibcon#about to read 5, iclass 31, count 0 2006.286.05:04:06.95#ibcon#read 5, iclass 31, count 0 2006.286.05:04:06.95#ibcon#about to read 6, iclass 31, count 0 2006.286.05:04:06.95#ibcon#read 6, iclass 31, count 0 2006.286.05:04:06.95#ibcon#end of sib2, iclass 31, count 0 2006.286.05:04:06.95#ibcon#*after write, iclass 31, count 0 2006.286.05:04:06.95#ibcon#*before return 0, iclass 31, count 0 2006.286.05:04:06.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:04:06.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:04:06.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.05:04:06.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.05:04:06.95$vck44/vb=7,4 2006.286.05:04:06.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.286.05:04:06.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.286.05:04:06.95#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:06.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.05:04:07.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.286.05:04:07.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.05:04:07.01#ibcon#enter wrdev, iclass 33, count 2 2006.286.05:04:07.01#ibcon#first serial, iclass 33, count 2 2006.286.05:04:07.01#ibcon#enter sib2, iclass 33, count 2 2006.286.05:04:07.01#ibcon#flushed, iclass 33, count 2 2006.286.05:04:07.01#ibcon#about to write, iclass 33, count 2 2006.286.05:04:07.01#ibcon#wrote, iclass 33, count 2 2006.286.05:04:07.01#ibcon#about to read 3, iclass 33, count 2 2006.286.05:04:07.03#ibcon#read 3, iclass 33, count 2 2006.286.05:04:07.03#ibcon#about to read 4, iclass 33, count 2 2006.286.05:04:07.03#ibcon#read 4, iclass 33, count 2 2006.286.05:04:07.03#ibcon#about to read 5, iclass 33, count 2 2006.286.05:04:07.03#ibcon#read 5, iclass 33, count 2 2006.286.05:04:07.03#ibcon#about to read 6, iclass 33, count 2 2006.286.05:04:07.03#ibcon#read 6, iclass 33, count 2 2006.286.05:04:07.03#ibcon#end of sib2, iclass 33, count 2 2006.286.05:04:07.03#ibcon#*mode == 0, iclass 33, count 2 2006.286.05:04:07.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.286.05:04:07.03#ibcon#[27=AT07-04\r\n] 2006.286.05:04:07.03#ibcon#*before write, iclass 33, count 2 2006.286.05:04:07.03#ibcon#enter sib2, iclass 33, count 2 2006.286.05:04:07.03#ibcon#flushed, iclass 33, count 2 2006.286.05:04:07.03#ibcon#about to write, iclass 33, count 2 2006.286.05:04:07.03#ibcon#wrote, iclass 33, count 2 2006.286.05:04:07.03#ibcon#about to read 3, iclass 33, count 2 2006.286.05:04:07.06#ibcon#read 3, iclass 33, count 2 2006.286.05:04:07.06#ibcon#about to read 4, iclass 33, count 2 2006.286.05:04:07.06#ibcon#read 4, iclass 33, count 2 2006.286.05:04:07.06#ibcon#about to read 5, iclass 33, count 2 2006.286.05:04:07.06#ibcon#read 5, iclass 33, count 2 2006.286.05:04:07.06#ibcon#about to read 6, iclass 33, count 2 2006.286.05:04:07.06#ibcon#read 6, iclass 33, count 2 2006.286.05:04:07.06#ibcon#end of sib2, iclass 33, count 2 2006.286.05:04:07.06#ibcon#*after write, iclass 33, count 2 2006.286.05:04:07.06#ibcon#*before return 0, iclass 33, count 2 2006.286.05:04:07.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.286.05:04:07.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.286.05:04:07.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.286.05:04:07.06#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:07.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.05:04:07.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.286.05:04:07.32#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.05:04:07.32#ibcon#enter wrdev, iclass 33, count 0 2006.286.05:04:07.32#ibcon#first serial, iclass 33, count 0 2006.286.05:04:07.32#ibcon#enter sib2, iclass 33, count 0 2006.286.05:04:07.32#ibcon#flushed, iclass 33, count 0 2006.286.05:04:07.32#ibcon#about to write, iclass 33, count 0 2006.286.05:04:07.32#ibcon#wrote, iclass 33, count 0 2006.286.05:04:07.32#ibcon#about to read 3, iclass 33, count 0 2006.286.05:04:07.34#ibcon#read 3, iclass 33, count 0 2006.286.05:04:07.34#ibcon#about to read 4, iclass 33, count 0 2006.286.05:04:07.34#ibcon#read 4, iclass 33, count 0 2006.286.05:04:07.34#ibcon#about to read 5, iclass 33, count 0 2006.286.05:04:07.34#ibcon#read 5, iclass 33, count 0 2006.286.05:04:07.34#ibcon#about to read 6, iclass 33, count 0 2006.286.05:04:07.34#ibcon#read 6, iclass 33, count 0 2006.286.05:04:07.34#ibcon#end of sib2, iclass 33, count 0 2006.286.05:04:07.34#ibcon#*mode == 0, iclass 33, count 0 2006.286.05:04:07.34#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.05:04:07.34#ibcon#[27=USB\r\n] 2006.286.05:04:07.34#ibcon#*before write, iclass 33, count 0 2006.286.05:04:07.34#ibcon#enter sib2, iclass 33, count 0 2006.286.05:04:07.34#ibcon#flushed, iclass 33, count 0 2006.286.05:04:07.34#ibcon#about to write, iclass 33, count 0 2006.286.05:04:07.34#ibcon#wrote, iclass 33, count 0 2006.286.05:04:07.34#ibcon#about to read 3, iclass 33, count 0 2006.286.05:04:07.37#ibcon#read 3, iclass 33, count 0 2006.286.05:04:07.37#ibcon#about to read 4, iclass 33, count 0 2006.286.05:04:07.37#ibcon#read 4, iclass 33, count 0 2006.286.05:04:07.37#ibcon#about to read 5, iclass 33, count 0 2006.286.05:04:07.37#ibcon#read 5, iclass 33, count 0 2006.286.05:04:07.37#ibcon#about to read 6, iclass 33, count 0 2006.286.05:04:07.37#ibcon#read 6, iclass 33, count 0 2006.286.05:04:07.37#ibcon#end of sib2, iclass 33, count 0 2006.286.05:04:07.37#ibcon#*after write, iclass 33, count 0 2006.286.05:04:07.37#ibcon#*before return 0, iclass 33, count 0 2006.286.05:04:07.37#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.286.05:04:07.37#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.286.05:04:07.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.05:04:07.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.05:04:07.37$vck44/vblo=8,744.99 2006.286.05:04:07.37#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.05:04:07.37#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.05:04:07.37#ibcon#ireg 17 cls_cnt 0 2006.286.05:04:07.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:04:07.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:04:07.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:04:07.37#ibcon#enter wrdev, iclass 35, count 0 2006.286.05:04:07.37#ibcon#first serial, iclass 35, count 0 2006.286.05:04:07.37#ibcon#enter sib2, iclass 35, count 0 2006.286.05:04:07.37#ibcon#flushed, iclass 35, count 0 2006.286.05:04:07.37#ibcon#about to write, iclass 35, count 0 2006.286.05:04:07.37#ibcon#wrote, iclass 35, count 0 2006.286.05:04:07.37#ibcon#about to read 3, iclass 35, count 0 2006.286.05:04:07.39#ibcon#read 3, iclass 35, count 0 2006.286.05:04:07.39#ibcon#about to read 4, iclass 35, count 0 2006.286.05:04:07.39#ibcon#read 4, iclass 35, count 0 2006.286.05:04:07.39#ibcon#about to read 5, iclass 35, count 0 2006.286.05:04:07.39#ibcon#read 5, iclass 35, count 0 2006.286.05:04:07.39#ibcon#about to read 6, iclass 35, count 0 2006.286.05:04:07.39#ibcon#read 6, iclass 35, count 0 2006.286.05:04:07.39#ibcon#end of sib2, iclass 35, count 0 2006.286.05:04:07.39#ibcon#*mode == 0, iclass 35, count 0 2006.286.05:04:07.39#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.05:04:07.39#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.05:04:07.39#ibcon#*before write, iclass 35, count 0 2006.286.05:04:07.39#ibcon#enter sib2, iclass 35, count 0 2006.286.05:04:07.39#ibcon#flushed, iclass 35, count 0 2006.286.05:04:07.39#ibcon#about to write, iclass 35, count 0 2006.286.05:04:07.39#ibcon#wrote, iclass 35, count 0 2006.286.05:04:07.39#ibcon#about to read 3, iclass 35, count 0 2006.286.05:04:07.43#ibcon#read 3, iclass 35, count 0 2006.286.05:04:07.43#ibcon#about to read 4, iclass 35, count 0 2006.286.05:04:07.43#ibcon#read 4, iclass 35, count 0 2006.286.05:04:07.43#ibcon#about to read 5, iclass 35, count 0 2006.286.05:04:07.43#ibcon#read 5, iclass 35, count 0 2006.286.05:04:07.43#ibcon#about to read 6, iclass 35, count 0 2006.286.05:04:07.43#ibcon#read 6, iclass 35, count 0 2006.286.05:04:07.43#ibcon#end of sib2, iclass 35, count 0 2006.286.05:04:07.43#ibcon#*after write, iclass 35, count 0 2006.286.05:04:07.43#ibcon#*before return 0, iclass 35, count 0 2006.286.05:04:07.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:04:07.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:04:07.43#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.05:04:07.43#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.05:04:07.43$vck44/vb=8,4 2006.286.05:04:07.43#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.05:04:07.43#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.05:04:07.43#ibcon#ireg 11 cls_cnt 2 2006.286.05:04:07.43#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:04:07.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:04:07.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:04:07.49#ibcon#enter wrdev, iclass 37, count 2 2006.286.05:04:07.49#ibcon#first serial, iclass 37, count 2 2006.286.05:04:07.49#ibcon#enter sib2, iclass 37, count 2 2006.286.05:04:07.49#ibcon#flushed, iclass 37, count 2 2006.286.05:04:07.49#ibcon#about to write, iclass 37, count 2 2006.286.05:04:07.49#ibcon#wrote, iclass 37, count 2 2006.286.05:04:07.49#ibcon#about to read 3, iclass 37, count 2 2006.286.05:04:07.51#ibcon#read 3, iclass 37, count 2 2006.286.05:04:07.51#ibcon#about to read 4, iclass 37, count 2 2006.286.05:04:07.51#ibcon#read 4, iclass 37, count 2 2006.286.05:04:07.51#ibcon#about to read 5, iclass 37, count 2 2006.286.05:04:07.51#ibcon#read 5, iclass 37, count 2 2006.286.05:04:07.51#ibcon#about to read 6, iclass 37, count 2 2006.286.05:04:07.51#ibcon#read 6, iclass 37, count 2 2006.286.05:04:07.51#ibcon#end of sib2, iclass 37, count 2 2006.286.05:04:07.51#ibcon#*mode == 0, iclass 37, count 2 2006.286.05:04:07.51#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.05:04:07.51#ibcon#[27=AT08-04\r\n] 2006.286.05:04:07.51#ibcon#*before write, iclass 37, count 2 2006.286.05:04:07.51#ibcon#enter sib2, iclass 37, count 2 2006.286.05:04:07.51#ibcon#flushed, iclass 37, count 2 2006.286.05:04:07.51#ibcon#about to write, iclass 37, count 2 2006.286.05:04:07.51#ibcon#wrote, iclass 37, count 2 2006.286.05:04:07.51#ibcon#about to read 3, iclass 37, count 2 2006.286.05:04:07.54#ibcon#read 3, iclass 37, count 2 2006.286.05:04:07.54#ibcon#about to read 4, iclass 37, count 2 2006.286.05:04:07.54#ibcon#read 4, iclass 37, count 2 2006.286.05:04:07.54#ibcon#about to read 5, iclass 37, count 2 2006.286.05:04:07.54#ibcon#read 5, iclass 37, count 2 2006.286.05:04:07.54#ibcon#about to read 6, iclass 37, count 2 2006.286.05:04:07.54#ibcon#read 6, iclass 37, count 2 2006.286.05:04:07.54#ibcon#end of sib2, iclass 37, count 2 2006.286.05:04:07.54#ibcon#*after write, iclass 37, count 2 2006.286.05:04:07.54#ibcon#*before return 0, iclass 37, count 2 2006.286.05:04:07.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:04:07.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:04:07.54#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.05:04:07.54#ibcon#ireg 7 cls_cnt 0 2006.286.05:04:07.54#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:04:07.66#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:04:07.66#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:04:07.66#ibcon#enter wrdev, iclass 37, count 0 2006.286.05:04:07.66#ibcon#first serial, iclass 37, count 0 2006.286.05:04:07.66#ibcon#enter sib2, iclass 37, count 0 2006.286.05:04:07.66#ibcon#flushed, iclass 37, count 0 2006.286.05:04:07.66#ibcon#about to write, iclass 37, count 0 2006.286.05:04:07.66#ibcon#wrote, iclass 37, count 0 2006.286.05:04:07.66#ibcon#about to read 3, iclass 37, count 0 2006.286.05:04:07.68#ibcon#read 3, iclass 37, count 0 2006.286.05:04:07.68#ibcon#about to read 4, iclass 37, count 0 2006.286.05:04:07.68#ibcon#read 4, iclass 37, count 0 2006.286.05:04:07.68#ibcon#about to read 5, iclass 37, count 0 2006.286.05:04:07.68#ibcon#read 5, iclass 37, count 0 2006.286.05:04:07.68#ibcon#about to read 6, iclass 37, count 0 2006.286.05:04:07.68#ibcon#read 6, iclass 37, count 0 2006.286.05:04:07.68#ibcon#end of sib2, iclass 37, count 0 2006.286.05:04:07.68#ibcon#*mode == 0, iclass 37, count 0 2006.286.05:04:07.68#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.05:04:07.68#ibcon#[27=USB\r\n] 2006.286.05:04:07.68#ibcon#*before write, iclass 37, count 0 2006.286.05:04:07.68#ibcon#enter sib2, iclass 37, count 0 2006.286.05:04:07.68#ibcon#flushed, iclass 37, count 0 2006.286.05:04:07.68#ibcon#about to write, iclass 37, count 0 2006.286.05:04:07.68#ibcon#wrote, iclass 37, count 0 2006.286.05:04:07.68#ibcon#about to read 3, iclass 37, count 0 2006.286.05:04:07.71#ibcon#read 3, iclass 37, count 0 2006.286.05:04:07.71#ibcon#about to read 4, iclass 37, count 0 2006.286.05:04:07.71#ibcon#read 4, iclass 37, count 0 2006.286.05:04:07.71#ibcon#about to read 5, iclass 37, count 0 2006.286.05:04:07.71#ibcon#read 5, iclass 37, count 0 2006.286.05:04:07.71#ibcon#about to read 6, iclass 37, count 0 2006.286.05:04:07.71#ibcon#read 6, iclass 37, count 0 2006.286.05:04:07.71#ibcon#end of sib2, iclass 37, count 0 2006.286.05:04:07.71#ibcon#*after write, iclass 37, count 0 2006.286.05:04:07.71#ibcon#*before return 0, iclass 37, count 0 2006.286.05:04:07.71#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:04:07.71#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:04:07.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.05:04:07.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.05:04:07.71$vck44/vabw=wide 2006.286.05:04:07.71#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.05:04:07.71#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.05:04:07.71#ibcon#ireg 8 cls_cnt 0 2006.286.05:04:07.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:04:07.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:04:07.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:04:07.71#ibcon#enter wrdev, iclass 39, count 0 2006.286.05:04:07.71#ibcon#first serial, iclass 39, count 0 2006.286.05:04:07.71#ibcon#enter sib2, iclass 39, count 0 2006.286.05:04:07.71#ibcon#flushed, iclass 39, count 0 2006.286.05:04:07.71#ibcon#about to write, iclass 39, count 0 2006.286.05:04:07.71#ibcon#wrote, iclass 39, count 0 2006.286.05:04:07.71#ibcon#about to read 3, iclass 39, count 0 2006.286.05:04:07.73#ibcon#read 3, iclass 39, count 0 2006.286.05:04:07.73#ibcon#about to read 4, iclass 39, count 0 2006.286.05:04:07.73#ibcon#read 4, iclass 39, count 0 2006.286.05:04:07.73#ibcon#about to read 5, iclass 39, count 0 2006.286.05:04:07.73#ibcon#read 5, iclass 39, count 0 2006.286.05:04:07.73#ibcon#about to read 6, iclass 39, count 0 2006.286.05:04:07.73#ibcon#read 6, iclass 39, count 0 2006.286.05:04:07.73#ibcon#end of sib2, iclass 39, count 0 2006.286.05:04:07.73#ibcon#*mode == 0, iclass 39, count 0 2006.286.05:04:07.73#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.05:04:07.73#ibcon#[25=BW32\r\n] 2006.286.05:04:07.73#ibcon#*before write, iclass 39, count 0 2006.286.05:04:07.73#ibcon#enter sib2, iclass 39, count 0 2006.286.05:04:07.73#ibcon#flushed, iclass 39, count 0 2006.286.05:04:07.73#ibcon#about to write, iclass 39, count 0 2006.286.05:04:07.73#ibcon#wrote, iclass 39, count 0 2006.286.05:04:07.73#ibcon#about to read 3, iclass 39, count 0 2006.286.05:04:07.76#ibcon#read 3, iclass 39, count 0 2006.286.05:04:07.76#ibcon#about to read 4, iclass 39, count 0 2006.286.05:04:07.76#ibcon#read 4, iclass 39, count 0 2006.286.05:04:07.76#ibcon#about to read 5, iclass 39, count 0 2006.286.05:04:07.76#ibcon#read 5, iclass 39, count 0 2006.286.05:04:07.76#ibcon#about to read 6, iclass 39, count 0 2006.286.05:04:07.76#ibcon#read 6, iclass 39, count 0 2006.286.05:04:07.76#ibcon#end of sib2, iclass 39, count 0 2006.286.05:04:07.76#ibcon#*after write, iclass 39, count 0 2006.286.05:04:07.76#ibcon#*before return 0, iclass 39, count 0 2006.286.05:04:07.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:04:07.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:04:07.76#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.05:04:07.76#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.05:04:07.76$vck44/vbbw=wide 2006.286.05:04:07.76#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.05:04:07.76#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.05:04:07.76#ibcon#ireg 8 cls_cnt 0 2006.286.05:04:07.76#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:04:07.83#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:04:07.83#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:04:07.83#ibcon#enter wrdev, iclass 3, count 0 2006.286.05:04:07.83#ibcon#first serial, iclass 3, count 0 2006.286.05:04:07.83#ibcon#enter sib2, iclass 3, count 0 2006.286.05:04:07.83#ibcon#flushed, iclass 3, count 0 2006.286.05:04:07.83#ibcon#about to write, iclass 3, count 0 2006.286.05:04:07.83#ibcon#wrote, iclass 3, count 0 2006.286.05:04:07.83#ibcon#about to read 3, iclass 3, count 0 2006.286.05:04:07.85#ibcon#read 3, iclass 3, count 0 2006.286.05:04:07.85#ibcon#about to read 4, iclass 3, count 0 2006.286.05:04:07.85#ibcon#read 4, iclass 3, count 0 2006.286.05:04:07.85#ibcon#about to read 5, iclass 3, count 0 2006.286.05:04:07.85#ibcon#read 5, iclass 3, count 0 2006.286.05:04:07.85#ibcon#about to read 6, iclass 3, count 0 2006.286.05:04:07.85#ibcon#read 6, iclass 3, count 0 2006.286.05:04:07.85#ibcon#end of sib2, iclass 3, count 0 2006.286.05:04:07.85#ibcon#*mode == 0, iclass 3, count 0 2006.286.05:04:07.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.05:04:07.85#ibcon#[27=BW32\r\n] 2006.286.05:04:07.85#ibcon#*before write, iclass 3, count 0 2006.286.05:04:07.85#ibcon#enter sib2, iclass 3, count 0 2006.286.05:04:07.85#ibcon#flushed, iclass 3, count 0 2006.286.05:04:07.85#ibcon#about to write, iclass 3, count 0 2006.286.05:04:07.85#ibcon#wrote, iclass 3, count 0 2006.286.05:04:07.85#ibcon#about to read 3, iclass 3, count 0 2006.286.05:04:07.88#ibcon#read 3, iclass 3, count 0 2006.286.05:04:07.88#ibcon#about to read 4, iclass 3, count 0 2006.286.05:04:07.88#ibcon#read 4, iclass 3, count 0 2006.286.05:04:07.88#ibcon#about to read 5, iclass 3, count 0 2006.286.05:04:07.88#ibcon#read 5, iclass 3, count 0 2006.286.05:04:07.88#ibcon#about to read 6, iclass 3, count 0 2006.286.05:04:07.88#ibcon#read 6, iclass 3, count 0 2006.286.05:04:07.88#ibcon#end of sib2, iclass 3, count 0 2006.286.05:04:07.88#ibcon#*after write, iclass 3, count 0 2006.286.05:04:07.88#ibcon#*before return 0, iclass 3, count 0 2006.286.05:04:07.88#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:04:07.88#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:04:07.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.05:04:07.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.05:04:07.88$setupk4/ifdk4 2006.286.05:04:07.88$ifdk4/lo= 2006.286.05:04:07.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.05:04:07.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.05:04:07.88$ifdk4/patch= 2006.286.05:04:07.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.05:04:07.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.05:04:07.88$setupk4/!*+20s 2006.286.05:04:16.67#abcon#<5=/04 3.3 8.6 22.05 761015.0\r\n> 2006.286.05:04:16.69#abcon#{5=INTERFACE CLEAR} 2006.286.05:04:16.75#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:04:21.46$setupk4/"tpicd 2006.286.05:04:21.46$setupk4/echo=off 2006.286.05:04:21.46$setupk4/xlog=off 2006.286.05:04:21.46:!2006.286.05:14:56 2006.286.05:04:54.14#trakl#Source acquired 2006.286.05:04:55.14#flagr#flagr/antenna,acquired 2006.286.05:14:56.00:preob 2006.286.05:14:56.13/onsource/TRACKING 2006.286.05:14:56.13:!2006.286.05:15:06 2006.286.05:15:06.00:"tape 2006.286.05:15:06.00:"st=record 2006.286.05:15:06.00:data_valid=on 2006.286.05:15:06.00:midob 2006.286.05:15:07.13/onsource/TRACKING 2006.286.05:15:07.13/wx/21.68,1015.0,78 2006.286.05:15:07.27/cable/+6.4937E-03 2006.286.05:15:08.36/va/01,07,usb,yes,35,38 2006.286.05:15:08.36/va/02,06,usb,yes,35,36 2006.286.05:15:08.36/va/03,07,usb,yes,35,37 2006.286.05:15:08.36/va/04,06,usb,yes,36,38 2006.286.05:15:08.36/va/05,03,usb,yes,36,36 2006.286.05:15:08.36/va/06,04,usb,yes,32,32 2006.286.05:15:08.36/va/07,04,usb,yes,33,33 2006.286.05:15:08.36/va/08,03,usb,yes,33,41 2006.286.05:15:08.59/valo/01,524.99,yes,locked 2006.286.05:15:08.59/valo/02,534.99,yes,locked 2006.286.05:15:08.59/valo/03,564.99,yes,locked 2006.286.05:15:08.59/valo/04,624.99,yes,locked 2006.286.05:15:08.59/valo/05,734.99,yes,locked 2006.286.05:15:08.59/valo/06,814.99,yes,locked 2006.286.05:15:08.59/valo/07,864.99,yes,locked 2006.286.05:15:08.59/valo/08,884.99,yes,locked 2006.286.05:15:09.68/vb/01,04,usb,yes,38,35 2006.286.05:15:09.68/vb/02,05,usb,yes,36,36 2006.286.05:15:09.68/vb/03,04,usb,yes,37,41 2006.286.05:15:09.68/vb/04,05,usb,yes,37,36 2006.286.05:15:09.68/vb/05,04,usb,yes,33,36 2006.286.05:15:09.68/vb/06,03,usb,yes,47,42 2006.286.05:15:09.68/vb/07,04,usb,yes,38,38 2006.286.05:15:09.68/vb/08,04,usb,yes,34,39 2006.286.05:15:09.92/vblo/01,629.99,yes,locked 2006.286.05:15:09.92/vblo/02,634.99,yes,locked 2006.286.05:15:09.92/vblo/03,649.99,yes,locked 2006.286.05:15:09.92/vblo/04,679.99,yes,locked 2006.286.05:15:09.92/vblo/05,709.99,yes,locked 2006.286.05:15:09.92/vblo/06,719.99,yes,locked 2006.286.05:15:09.92/vblo/07,734.99,yes,locked 2006.286.05:15:09.92/vblo/08,744.99,yes,locked 2006.286.05:15:10.07/vabw/8 2006.286.05:15:10.22/vbbw/8 2006.286.05:15:10.31/xfe/off,on,12.0 2006.286.05:15:10.69/ifatt/23,28,28,28 2006.286.05:15:11.07/fmout-gps/S +2.42E-07 2006.286.05:15:11.09:!2006.286.05:16:36 2006.286.05:16:36.00:data_valid=off 2006.286.05:16:36.00:"et 2006.286.05:16:36.00:!+3s 2006.286.05:16:39.01:"tape 2006.286.05:16:39.01:postob 2006.286.05:16:39.12/cable/+6.4944E-03 2006.286.05:16:39.12/wx/21.64,1015.0,77 2006.286.05:16:40.08/fmout-gps/S +2.42E-07 2006.286.05:16:40.08:scan_name=286-0520,jd0610,280 2006.286.05:16:40.08:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.286.05:16:40.14#flagr#flagr/antenna,new-source 2006.286.05:16:41.14:checkk5 2006.286.05:16:41.60/chk_autoobs//k5ts1/ autoobs is running! 2006.286.05:16:42.08/chk_autoobs//k5ts2/ autoobs is running! 2006.286.05:16:42.46/chk_autoobs//k5ts3/ autoobs is running! 2006.286.05:16:42.92/chk_autoobs//k5ts4/ autoobs is running! 2006.286.05:16:43.29/chk_obsdata//k5ts1/T2860515??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.286.05:16:43.76/chk_obsdata//k5ts2/T2860515??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.286.05:16:44.16/chk_obsdata//k5ts3/T2860515??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.286.05:16:44.55/chk_obsdata//k5ts4/T2860515??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.286.05:16:45.39/k5log//k5ts1_log_newline 2006.286.05:16:46.24/k5log//k5ts2_log_newline 2006.286.05:16:47.11/k5log//k5ts3_log_newline 2006.286.05:16:47.94/k5log//k5ts4_log_newline 2006.286.05:16:47.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.05:16:47.96:setupk4=1 2006.286.05:16:47.96$setupk4/echo=on 2006.286.05:16:47.96$setupk4/pcalon 2006.286.05:16:47.96$pcalon/"no phase cal control is implemented here 2006.286.05:16:47.96$setupk4/"tpicd=stop 2006.286.05:16:47.96$setupk4/"rec=synch_on 2006.286.05:16:47.96$setupk4/"rec_mode=128 2006.286.05:16:47.96$setupk4/!* 2006.286.05:16:47.96$setupk4/recpk4 2006.286.05:16:47.96$recpk4/recpatch= 2006.286.05:16:47.96$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.05:16:47.96$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.05:16:47.96$setupk4/vck44 2006.286.05:16:47.96$vck44/valo=1,524.99 2006.286.05:16:47.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.05:16:47.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.05:16:47.96#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:47.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:16:47.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:16:47.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:16:47.96#ibcon#enter wrdev, iclass 18, count 0 2006.286.05:16:47.96#ibcon#first serial, iclass 18, count 0 2006.286.05:16:47.96#ibcon#enter sib2, iclass 18, count 0 2006.286.05:16:47.96#ibcon#flushed, iclass 18, count 0 2006.286.05:16:47.96#ibcon#about to write, iclass 18, count 0 2006.286.05:16:47.96#ibcon#wrote, iclass 18, count 0 2006.286.05:16:47.96#ibcon#about to read 3, iclass 18, count 0 2006.286.05:16:47.98#ibcon#read 3, iclass 18, count 0 2006.286.05:16:47.98#ibcon#about to read 4, iclass 18, count 0 2006.286.05:16:47.98#ibcon#read 4, iclass 18, count 0 2006.286.05:16:47.98#ibcon#about to read 5, iclass 18, count 0 2006.286.05:16:47.98#ibcon#read 5, iclass 18, count 0 2006.286.05:16:47.98#ibcon#about to read 6, iclass 18, count 0 2006.286.05:16:47.98#ibcon#read 6, iclass 18, count 0 2006.286.05:16:47.98#ibcon#end of sib2, iclass 18, count 0 2006.286.05:16:47.98#ibcon#*mode == 0, iclass 18, count 0 2006.286.05:16:47.98#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.05:16:47.98#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.05:16:47.98#ibcon#*before write, iclass 18, count 0 2006.286.05:16:47.98#ibcon#enter sib2, iclass 18, count 0 2006.286.05:16:47.98#ibcon#flushed, iclass 18, count 0 2006.286.05:16:47.98#ibcon#about to write, iclass 18, count 0 2006.286.05:16:47.98#ibcon#wrote, iclass 18, count 0 2006.286.05:16:47.98#ibcon#about to read 3, iclass 18, count 0 2006.286.05:16:48.03#ibcon#read 3, iclass 18, count 0 2006.286.05:16:48.03#ibcon#about to read 4, iclass 18, count 0 2006.286.05:16:48.03#ibcon#read 4, iclass 18, count 0 2006.286.05:16:48.03#ibcon#about to read 5, iclass 18, count 0 2006.286.05:16:48.03#ibcon#read 5, iclass 18, count 0 2006.286.05:16:48.03#ibcon#about to read 6, iclass 18, count 0 2006.286.05:16:48.03#ibcon#read 6, iclass 18, count 0 2006.286.05:16:48.03#ibcon#end of sib2, iclass 18, count 0 2006.286.05:16:48.03#ibcon#*after write, iclass 18, count 0 2006.286.05:16:48.03#ibcon#*before return 0, iclass 18, count 0 2006.286.05:16:48.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:16:48.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:16:48.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.05:16:48.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.05:16:48.03$vck44/va=1,7 2006.286.05:16:48.03#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.05:16:48.03#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.05:16:48.03#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:48.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:16:48.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:16:48.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:16:48.03#ibcon#enter wrdev, iclass 20, count 2 2006.286.05:16:48.03#ibcon#first serial, iclass 20, count 2 2006.286.05:16:48.03#ibcon#enter sib2, iclass 20, count 2 2006.286.05:16:48.03#ibcon#flushed, iclass 20, count 2 2006.286.05:16:48.03#ibcon#about to write, iclass 20, count 2 2006.286.05:16:48.03#ibcon#wrote, iclass 20, count 2 2006.286.05:16:48.03#ibcon#about to read 3, iclass 20, count 2 2006.286.05:16:48.05#ibcon#read 3, iclass 20, count 2 2006.286.05:16:48.05#ibcon#about to read 4, iclass 20, count 2 2006.286.05:16:48.05#ibcon#read 4, iclass 20, count 2 2006.286.05:16:48.05#ibcon#about to read 5, iclass 20, count 2 2006.286.05:16:48.05#ibcon#read 5, iclass 20, count 2 2006.286.05:16:48.05#ibcon#about to read 6, iclass 20, count 2 2006.286.05:16:48.05#ibcon#read 6, iclass 20, count 2 2006.286.05:16:48.05#ibcon#end of sib2, iclass 20, count 2 2006.286.05:16:48.05#ibcon#*mode == 0, iclass 20, count 2 2006.286.05:16:48.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.05:16:48.05#ibcon#[25=AT01-07\r\n] 2006.286.05:16:48.05#ibcon#*before write, iclass 20, count 2 2006.286.05:16:48.05#ibcon#enter sib2, iclass 20, count 2 2006.286.05:16:48.05#ibcon#flushed, iclass 20, count 2 2006.286.05:16:48.05#ibcon#about to write, iclass 20, count 2 2006.286.05:16:48.05#ibcon#wrote, iclass 20, count 2 2006.286.05:16:48.05#ibcon#about to read 3, iclass 20, count 2 2006.286.05:16:48.08#ibcon#read 3, iclass 20, count 2 2006.286.05:16:48.08#ibcon#about to read 4, iclass 20, count 2 2006.286.05:16:48.08#ibcon#read 4, iclass 20, count 2 2006.286.05:16:48.08#ibcon#about to read 5, iclass 20, count 2 2006.286.05:16:48.08#ibcon#read 5, iclass 20, count 2 2006.286.05:16:48.08#ibcon#about to read 6, iclass 20, count 2 2006.286.05:16:48.08#ibcon#read 6, iclass 20, count 2 2006.286.05:16:48.08#ibcon#end of sib2, iclass 20, count 2 2006.286.05:16:48.08#ibcon#*after write, iclass 20, count 2 2006.286.05:16:48.08#ibcon#*before return 0, iclass 20, count 2 2006.286.05:16:48.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:16:48.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:16:48.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.05:16:48.08#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:48.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:16:48.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:16:48.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:16:48.20#ibcon#enter wrdev, iclass 20, count 0 2006.286.05:16:48.20#ibcon#first serial, iclass 20, count 0 2006.286.05:16:48.20#ibcon#enter sib2, iclass 20, count 0 2006.286.05:16:48.20#ibcon#flushed, iclass 20, count 0 2006.286.05:16:48.20#ibcon#about to write, iclass 20, count 0 2006.286.05:16:48.20#ibcon#wrote, iclass 20, count 0 2006.286.05:16:48.20#ibcon#about to read 3, iclass 20, count 0 2006.286.05:16:48.22#ibcon#read 3, iclass 20, count 0 2006.286.05:16:48.22#ibcon#about to read 4, iclass 20, count 0 2006.286.05:16:48.22#ibcon#read 4, iclass 20, count 0 2006.286.05:16:48.22#ibcon#about to read 5, iclass 20, count 0 2006.286.05:16:48.22#ibcon#read 5, iclass 20, count 0 2006.286.05:16:48.22#ibcon#about to read 6, iclass 20, count 0 2006.286.05:16:48.22#ibcon#read 6, iclass 20, count 0 2006.286.05:16:48.22#ibcon#end of sib2, iclass 20, count 0 2006.286.05:16:48.22#ibcon#*mode == 0, iclass 20, count 0 2006.286.05:16:48.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.05:16:48.22#ibcon#[25=USB\r\n] 2006.286.05:16:48.22#ibcon#*before write, iclass 20, count 0 2006.286.05:16:48.22#ibcon#enter sib2, iclass 20, count 0 2006.286.05:16:48.22#ibcon#flushed, iclass 20, count 0 2006.286.05:16:48.22#ibcon#about to write, iclass 20, count 0 2006.286.05:16:48.22#ibcon#wrote, iclass 20, count 0 2006.286.05:16:48.22#ibcon#about to read 3, iclass 20, count 0 2006.286.05:16:48.25#ibcon#read 3, iclass 20, count 0 2006.286.05:16:48.25#ibcon#about to read 4, iclass 20, count 0 2006.286.05:16:48.25#ibcon#read 4, iclass 20, count 0 2006.286.05:16:48.25#ibcon#about to read 5, iclass 20, count 0 2006.286.05:16:48.25#ibcon#read 5, iclass 20, count 0 2006.286.05:16:48.25#ibcon#about to read 6, iclass 20, count 0 2006.286.05:16:48.25#ibcon#read 6, iclass 20, count 0 2006.286.05:16:48.25#ibcon#end of sib2, iclass 20, count 0 2006.286.05:16:48.25#ibcon#*after write, iclass 20, count 0 2006.286.05:16:48.25#ibcon#*before return 0, iclass 20, count 0 2006.286.05:16:48.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:16:48.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:16:48.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.05:16:48.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.05:16:48.25$vck44/valo=2,534.99 2006.286.05:16:48.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.05:16:48.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.05:16:48.25#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:48.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:16:48.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:16:48.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:16:48.25#ibcon#enter wrdev, iclass 22, count 0 2006.286.05:16:48.25#ibcon#first serial, iclass 22, count 0 2006.286.05:16:48.25#ibcon#enter sib2, iclass 22, count 0 2006.286.05:16:48.25#ibcon#flushed, iclass 22, count 0 2006.286.05:16:48.25#ibcon#about to write, iclass 22, count 0 2006.286.05:16:48.25#ibcon#wrote, iclass 22, count 0 2006.286.05:16:48.25#ibcon#about to read 3, iclass 22, count 0 2006.286.05:16:48.27#ibcon#read 3, iclass 22, count 0 2006.286.05:16:48.27#ibcon#about to read 4, iclass 22, count 0 2006.286.05:16:48.27#ibcon#read 4, iclass 22, count 0 2006.286.05:16:48.27#ibcon#about to read 5, iclass 22, count 0 2006.286.05:16:48.27#ibcon#read 5, iclass 22, count 0 2006.286.05:16:48.27#ibcon#about to read 6, iclass 22, count 0 2006.286.05:16:48.27#ibcon#read 6, iclass 22, count 0 2006.286.05:16:48.27#ibcon#end of sib2, iclass 22, count 0 2006.286.05:16:48.27#ibcon#*mode == 0, iclass 22, count 0 2006.286.05:16:48.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.05:16:48.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.05:16:48.27#ibcon#*before write, iclass 22, count 0 2006.286.05:16:48.27#ibcon#enter sib2, iclass 22, count 0 2006.286.05:16:48.27#ibcon#flushed, iclass 22, count 0 2006.286.05:16:48.27#ibcon#about to write, iclass 22, count 0 2006.286.05:16:48.27#ibcon#wrote, iclass 22, count 0 2006.286.05:16:48.27#ibcon#about to read 3, iclass 22, count 0 2006.286.05:16:48.31#ibcon#read 3, iclass 22, count 0 2006.286.05:16:48.31#ibcon#about to read 4, iclass 22, count 0 2006.286.05:16:48.31#ibcon#read 4, iclass 22, count 0 2006.286.05:16:48.31#ibcon#about to read 5, iclass 22, count 0 2006.286.05:16:48.31#ibcon#read 5, iclass 22, count 0 2006.286.05:16:48.31#ibcon#about to read 6, iclass 22, count 0 2006.286.05:16:48.31#ibcon#read 6, iclass 22, count 0 2006.286.05:16:48.31#ibcon#end of sib2, iclass 22, count 0 2006.286.05:16:48.31#ibcon#*after write, iclass 22, count 0 2006.286.05:16:48.31#ibcon#*before return 0, iclass 22, count 0 2006.286.05:16:48.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:16:48.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:16:48.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.05:16:48.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.05:16:48.31$vck44/va=2,6 2006.286.05:16:48.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.05:16:48.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.05:16:48.31#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:48.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:16:48.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:16:48.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:16:48.37#ibcon#enter wrdev, iclass 24, count 2 2006.286.05:16:48.37#ibcon#first serial, iclass 24, count 2 2006.286.05:16:48.37#ibcon#enter sib2, iclass 24, count 2 2006.286.05:16:48.37#ibcon#flushed, iclass 24, count 2 2006.286.05:16:48.37#ibcon#about to write, iclass 24, count 2 2006.286.05:16:48.37#ibcon#wrote, iclass 24, count 2 2006.286.05:16:48.37#ibcon#about to read 3, iclass 24, count 2 2006.286.05:16:48.39#ibcon#read 3, iclass 24, count 2 2006.286.05:16:48.39#ibcon#about to read 4, iclass 24, count 2 2006.286.05:16:48.39#ibcon#read 4, iclass 24, count 2 2006.286.05:16:48.39#ibcon#about to read 5, iclass 24, count 2 2006.286.05:16:48.39#ibcon#read 5, iclass 24, count 2 2006.286.05:16:48.39#ibcon#about to read 6, iclass 24, count 2 2006.286.05:16:48.39#ibcon#read 6, iclass 24, count 2 2006.286.05:16:48.39#ibcon#end of sib2, iclass 24, count 2 2006.286.05:16:48.39#ibcon#*mode == 0, iclass 24, count 2 2006.286.05:16:48.39#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.05:16:48.39#ibcon#[25=AT02-06\r\n] 2006.286.05:16:48.39#ibcon#*before write, iclass 24, count 2 2006.286.05:16:48.39#ibcon#enter sib2, iclass 24, count 2 2006.286.05:16:48.39#ibcon#flushed, iclass 24, count 2 2006.286.05:16:48.39#ibcon#about to write, iclass 24, count 2 2006.286.05:16:48.39#ibcon#wrote, iclass 24, count 2 2006.286.05:16:48.39#ibcon#about to read 3, iclass 24, count 2 2006.286.05:16:48.42#ibcon#read 3, iclass 24, count 2 2006.286.05:16:48.42#ibcon#about to read 4, iclass 24, count 2 2006.286.05:16:48.42#ibcon#read 4, iclass 24, count 2 2006.286.05:16:48.42#ibcon#about to read 5, iclass 24, count 2 2006.286.05:16:48.42#ibcon#read 5, iclass 24, count 2 2006.286.05:16:48.42#ibcon#about to read 6, iclass 24, count 2 2006.286.05:16:48.42#ibcon#read 6, iclass 24, count 2 2006.286.05:16:48.42#ibcon#end of sib2, iclass 24, count 2 2006.286.05:16:48.42#ibcon#*after write, iclass 24, count 2 2006.286.05:16:48.42#ibcon#*before return 0, iclass 24, count 2 2006.286.05:16:48.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:16:48.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:16:48.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.05:16:48.42#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:48.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:16:48.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:16:48.54#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:16:48.54#ibcon#enter wrdev, iclass 24, count 0 2006.286.05:16:48.54#ibcon#first serial, iclass 24, count 0 2006.286.05:16:48.54#ibcon#enter sib2, iclass 24, count 0 2006.286.05:16:48.54#ibcon#flushed, iclass 24, count 0 2006.286.05:16:48.54#ibcon#about to write, iclass 24, count 0 2006.286.05:16:48.54#ibcon#wrote, iclass 24, count 0 2006.286.05:16:48.54#ibcon#about to read 3, iclass 24, count 0 2006.286.05:16:48.56#ibcon#read 3, iclass 24, count 0 2006.286.05:16:48.56#ibcon#about to read 4, iclass 24, count 0 2006.286.05:16:48.56#ibcon#read 4, iclass 24, count 0 2006.286.05:16:48.56#ibcon#about to read 5, iclass 24, count 0 2006.286.05:16:48.56#ibcon#read 5, iclass 24, count 0 2006.286.05:16:48.56#ibcon#about to read 6, iclass 24, count 0 2006.286.05:16:48.56#ibcon#read 6, iclass 24, count 0 2006.286.05:16:48.56#ibcon#end of sib2, iclass 24, count 0 2006.286.05:16:48.56#ibcon#*mode == 0, iclass 24, count 0 2006.286.05:16:48.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.05:16:48.56#ibcon#[25=USB\r\n] 2006.286.05:16:48.56#ibcon#*before write, iclass 24, count 0 2006.286.05:16:48.56#ibcon#enter sib2, iclass 24, count 0 2006.286.05:16:48.56#ibcon#flushed, iclass 24, count 0 2006.286.05:16:48.56#ibcon#about to write, iclass 24, count 0 2006.286.05:16:48.56#ibcon#wrote, iclass 24, count 0 2006.286.05:16:48.56#ibcon#about to read 3, iclass 24, count 0 2006.286.05:16:48.59#ibcon#read 3, iclass 24, count 0 2006.286.05:16:48.59#ibcon#about to read 4, iclass 24, count 0 2006.286.05:16:48.59#ibcon#read 4, iclass 24, count 0 2006.286.05:16:48.59#ibcon#about to read 5, iclass 24, count 0 2006.286.05:16:48.59#ibcon#read 5, iclass 24, count 0 2006.286.05:16:48.59#ibcon#about to read 6, iclass 24, count 0 2006.286.05:16:48.59#ibcon#read 6, iclass 24, count 0 2006.286.05:16:48.59#ibcon#end of sib2, iclass 24, count 0 2006.286.05:16:48.59#ibcon#*after write, iclass 24, count 0 2006.286.05:16:48.59#ibcon#*before return 0, iclass 24, count 0 2006.286.05:16:48.59#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:16:48.59#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:16:48.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.05:16:48.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.05:16:48.59$vck44/valo=3,564.99 2006.286.05:16:48.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.05:16:48.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.05:16:48.59#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:48.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:16:48.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:16:48.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:16:48.59#ibcon#enter wrdev, iclass 26, count 0 2006.286.05:16:48.59#ibcon#first serial, iclass 26, count 0 2006.286.05:16:48.59#ibcon#enter sib2, iclass 26, count 0 2006.286.05:16:48.59#ibcon#flushed, iclass 26, count 0 2006.286.05:16:48.59#ibcon#about to write, iclass 26, count 0 2006.286.05:16:48.59#ibcon#wrote, iclass 26, count 0 2006.286.05:16:48.59#ibcon#about to read 3, iclass 26, count 0 2006.286.05:16:48.61#ibcon#read 3, iclass 26, count 0 2006.286.05:16:49.18#ibcon#about to read 4, iclass 26, count 0 2006.286.05:16:49.18#ibcon#read 4, iclass 26, count 0 2006.286.05:16:49.18#ibcon#about to read 5, iclass 26, count 0 2006.286.05:16:49.18#ibcon#read 5, iclass 26, count 0 2006.286.05:16:49.18#ibcon#about to read 6, iclass 26, count 0 2006.286.05:16:49.18#ibcon#read 6, iclass 26, count 0 2006.286.05:16:49.18#ibcon#end of sib2, iclass 26, count 0 2006.286.05:16:49.18#ibcon#*mode == 0, iclass 26, count 0 2006.286.05:16:49.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.05:16:49.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.05:16:49.18#ibcon#*before write, iclass 26, count 0 2006.286.05:16:49.18#ibcon#enter sib2, iclass 26, count 0 2006.286.05:16:49.18#ibcon#flushed, iclass 26, count 0 2006.286.05:16:49.18#ibcon#about to write, iclass 26, count 0 2006.286.05:16:49.18#ibcon#wrote, iclass 26, count 0 2006.286.05:16:49.18#ibcon#about to read 3, iclass 26, count 0 2006.286.05:16:49.22#ibcon#read 3, iclass 26, count 0 2006.286.05:16:49.22#ibcon#about to read 4, iclass 26, count 0 2006.286.05:16:49.22#ibcon#read 4, iclass 26, count 0 2006.286.05:16:49.22#ibcon#about to read 5, iclass 26, count 0 2006.286.05:16:49.22#ibcon#read 5, iclass 26, count 0 2006.286.05:16:49.22#ibcon#about to read 6, iclass 26, count 0 2006.286.05:16:49.22#ibcon#read 6, iclass 26, count 0 2006.286.05:16:49.22#ibcon#end of sib2, iclass 26, count 0 2006.286.05:16:49.22#ibcon#*after write, iclass 26, count 0 2006.286.05:16:49.22#ibcon#*before return 0, iclass 26, count 0 2006.286.05:16:49.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:16:49.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:16:49.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.05:16:49.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.05:16:49.22$vck44/va=3,7 2006.286.05:16:49.22#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.05:16:49.22#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.05:16:49.22#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:49.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:16:49.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:16:49.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:16:49.22#ibcon#enter wrdev, iclass 28, count 2 2006.286.05:16:49.22#ibcon#first serial, iclass 28, count 2 2006.286.05:16:49.22#ibcon#enter sib2, iclass 28, count 2 2006.286.05:16:49.22#ibcon#flushed, iclass 28, count 2 2006.286.05:16:49.22#ibcon#about to write, iclass 28, count 2 2006.286.05:16:49.22#ibcon#wrote, iclass 28, count 2 2006.286.05:16:49.22#ibcon#about to read 3, iclass 28, count 2 2006.286.05:16:49.24#ibcon#read 3, iclass 28, count 2 2006.286.05:16:49.24#ibcon#about to read 4, iclass 28, count 2 2006.286.05:16:49.24#ibcon#read 4, iclass 28, count 2 2006.286.05:16:49.24#ibcon#about to read 5, iclass 28, count 2 2006.286.05:16:49.24#ibcon#read 5, iclass 28, count 2 2006.286.05:16:49.24#ibcon#about to read 6, iclass 28, count 2 2006.286.05:16:49.24#ibcon#read 6, iclass 28, count 2 2006.286.05:16:49.24#ibcon#end of sib2, iclass 28, count 2 2006.286.05:16:49.24#ibcon#*mode == 0, iclass 28, count 2 2006.286.05:16:49.24#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.05:16:49.24#ibcon#[25=AT03-07\r\n] 2006.286.05:16:49.24#ibcon#*before write, iclass 28, count 2 2006.286.05:16:49.24#ibcon#enter sib2, iclass 28, count 2 2006.286.05:16:49.24#ibcon#flushed, iclass 28, count 2 2006.286.05:16:49.24#ibcon#about to write, iclass 28, count 2 2006.286.05:16:49.24#ibcon#wrote, iclass 28, count 2 2006.286.05:16:49.24#ibcon#about to read 3, iclass 28, count 2 2006.286.05:16:49.27#ibcon#read 3, iclass 28, count 2 2006.286.05:16:49.27#ibcon#about to read 4, iclass 28, count 2 2006.286.05:16:49.27#ibcon#read 4, iclass 28, count 2 2006.286.05:16:49.27#ibcon#about to read 5, iclass 28, count 2 2006.286.05:16:49.27#ibcon#read 5, iclass 28, count 2 2006.286.05:16:49.27#ibcon#about to read 6, iclass 28, count 2 2006.286.05:16:49.27#ibcon#read 6, iclass 28, count 2 2006.286.05:16:49.27#ibcon#end of sib2, iclass 28, count 2 2006.286.05:16:49.27#ibcon#*after write, iclass 28, count 2 2006.286.05:16:49.27#ibcon#*before return 0, iclass 28, count 2 2006.286.05:16:49.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:16:49.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:16:49.27#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.05:16:49.27#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:49.27#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:16:49.38#abcon#<5=/04 3.6 8.3 21.63 771015.0\r\n> 2006.286.05:16:49.39#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:16:49.39#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:16:49.39#ibcon#enter wrdev, iclass 28, count 0 2006.286.05:16:49.39#ibcon#first serial, iclass 28, count 0 2006.286.05:16:49.39#ibcon#enter sib2, iclass 28, count 0 2006.286.05:16:49.39#ibcon#flushed, iclass 28, count 0 2006.286.05:16:49.39#ibcon#about to write, iclass 28, count 0 2006.286.05:16:49.39#ibcon#wrote, iclass 28, count 0 2006.286.05:16:49.39#ibcon#about to read 3, iclass 28, count 0 2006.286.05:16:49.40#abcon#{5=INTERFACE CLEAR} 2006.286.05:16:49.41#ibcon#read 3, iclass 28, count 0 2006.286.05:16:49.41#ibcon#about to read 4, iclass 28, count 0 2006.286.05:16:49.41#ibcon#read 4, iclass 28, count 0 2006.286.05:16:49.41#ibcon#about to read 5, iclass 28, count 0 2006.286.05:16:49.41#ibcon#read 5, iclass 28, count 0 2006.286.05:16:49.41#ibcon#about to read 6, iclass 28, count 0 2006.286.05:16:49.41#ibcon#read 6, iclass 28, count 0 2006.286.05:16:49.41#ibcon#end of sib2, iclass 28, count 0 2006.286.05:16:49.41#ibcon#*mode == 0, iclass 28, count 0 2006.286.05:16:49.41#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.05:16:49.41#ibcon#[25=USB\r\n] 2006.286.05:16:49.41#ibcon#*before write, iclass 28, count 0 2006.286.05:16:49.41#ibcon#enter sib2, iclass 28, count 0 2006.286.05:16:49.41#ibcon#flushed, iclass 28, count 0 2006.286.05:16:49.41#ibcon#about to write, iclass 28, count 0 2006.286.05:16:49.41#ibcon#wrote, iclass 28, count 0 2006.286.05:16:49.41#ibcon#about to read 3, iclass 28, count 0 2006.286.05:16:49.44#ibcon#read 3, iclass 28, count 0 2006.286.05:16:49.44#ibcon#about to read 4, iclass 28, count 0 2006.286.05:16:49.44#ibcon#read 4, iclass 28, count 0 2006.286.05:16:49.44#ibcon#about to read 5, iclass 28, count 0 2006.286.05:16:49.44#ibcon#read 5, iclass 28, count 0 2006.286.05:16:49.44#ibcon#about to read 6, iclass 28, count 0 2006.286.05:16:49.44#ibcon#read 6, iclass 28, count 0 2006.286.05:16:49.44#ibcon#end of sib2, iclass 28, count 0 2006.286.05:16:49.44#ibcon#*after write, iclass 28, count 0 2006.286.05:16:49.44#ibcon#*before return 0, iclass 28, count 0 2006.286.05:16:49.44#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:16:49.44#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:16:49.44#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.05:16:49.44#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.05:16:49.44$vck44/valo=4,624.99 2006.286.05:16:49.44#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.05:16:49.44#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.05:16:49.44#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:49.44#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:16:49.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:16:49.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:16:49.44#ibcon#enter wrdev, iclass 33, count 0 2006.286.05:16:49.44#ibcon#first serial, iclass 33, count 0 2006.286.05:16:49.44#ibcon#enter sib2, iclass 33, count 0 2006.286.05:16:49.44#ibcon#flushed, iclass 33, count 0 2006.286.05:16:49.44#ibcon#about to write, iclass 33, count 0 2006.286.05:16:49.44#ibcon#wrote, iclass 33, count 0 2006.286.05:16:49.44#ibcon#about to read 3, iclass 33, count 0 2006.286.05:16:49.46#ibcon#read 3, iclass 33, count 0 2006.286.05:16:49.82#ibcon#about to read 4, iclass 33, count 0 2006.286.05:16:49.82#ibcon#read 4, iclass 33, count 0 2006.286.05:16:49.82#ibcon#about to read 5, iclass 33, count 0 2006.286.05:16:49.82#ibcon#read 5, iclass 33, count 0 2006.286.05:16:49.82#ibcon#about to read 6, iclass 33, count 0 2006.286.05:16:49.82#ibcon#read 6, iclass 33, count 0 2006.286.05:16:49.82#ibcon#end of sib2, iclass 33, count 0 2006.286.05:16:49.82#ibcon#*mode == 0, iclass 33, count 0 2006.286.05:16:49.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.05:16:49.82#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.05:16:49.82#ibcon#*before write, iclass 33, count 0 2006.286.05:16:49.82#ibcon#enter sib2, iclass 33, count 0 2006.286.05:16:49.82#ibcon#flushed, iclass 33, count 0 2006.286.05:16:49.82#ibcon#about to write, iclass 33, count 0 2006.286.05:16:49.82#ibcon#wrote, iclass 33, count 0 2006.286.05:16:49.82#ibcon#about to read 3, iclass 33, count 0 2006.286.05:16:49.46#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:16:49.85#ibcon#read 3, iclass 33, count 0 2006.286.05:16:49.85#ibcon#about to read 4, iclass 33, count 0 2006.286.05:16:49.85#ibcon#read 4, iclass 33, count 0 2006.286.05:16:49.85#ibcon#about to read 5, iclass 33, count 0 2006.286.05:16:49.85#ibcon#read 5, iclass 33, count 0 2006.286.05:16:49.85#ibcon#about to read 6, iclass 33, count 0 2006.286.05:16:49.85#ibcon#read 6, iclass 33, count 0 2006.286.05:16:49.85#ibcon#end of sib2, iclass 33, count 0 2006.286.05:16:49.85#ibcon#*after write, iclass 33, count 0 2006.286.05:16:49.85#ibcon#*before return 0, iclass 33, count 0 2006.286.05:16:49.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:16:49.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:16:49.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.05:16:49.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.05:16:49.85$vck44/va=4,6 2006.286.05:16:49.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.05:16:49.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.05:16:49.85#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:49.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:16:49.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:16:49.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:16:49.85#ibcon#enter wrdev, iclass 36, count 2 2006.286.05:16:49.85#ibcon#first serial, iclass 36, count 2 2006.286.05:16:49.85#ibcon#enter sib2, iclass 36, count 2 2006.286.05:16:49.85#ibcon#flushed, iclass 36, count 2 2006.286.05:16:49.85#ibcon#about to write, iclass 36, count 2 2006.286.05:16:49.85#ibcon#wrote, iclass 36, count 2 2006.286.05:16:49.85#ibcon#about to read 3, iclass 36, count 2 2006.286.05:16:49.87#ibcon#read 3, iclass 36, count 2 2006.286.05:16:49.87#ibcon#about to read 4, iclass 36, count 2 2006.286.05:16:49.87#ibcon#read 4, iclass 36, count 2 2006.286.05:16:49.87#ibcon#about to read 5, iclass 36, count 2 2006.286.05:16:49.87#ibcon#read 5, iclass 36, count 2 2006.286.05:16:49.87#ibcon#about to read 6, iclass 36, count 2 2006.286.05:16:49.87#ibcon#read 6, iclass 36, count 2 2006.286.05:16:49.87#ibcon#end of sib2, iclass 36, count 2 2006.286.05:16:49.87#ibcon#*mode == 0, iclass 36, count 2 2006.286.05:16:49.87#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.05:16:49.87#ibcon#[25=AT04-06\r\n] 2006.286.05:16:49.87#ibcon#*before write, iclass 36, count 2 2006.286.05:16:49.87#ibcon#enter sib2, iclass 36, count 2 2006.286.05:16:49.87#ibcon#flushed, iclass 36, count 2 2006.286.05:16:49.87#ibcon#about to write, iclass 36, count 2 2006.286.05:16:49.87#ibcon#wrote, iclass 36, count 2 2006.286.05:16:49.87#ibcon#about to read 3, iclass 36, count 2 2006.286.05:16:49.90#ibcon#read 3, iclass 36, count 2 2006.286.05:16:49.90#ibcon#about to read 4, iclass 36, count 2 2006.286.05:16:49.90#ibcon#read 4, iclass 36, count 2 2006.286.05:16:49.90#ibcon#about to read 5, iclass 36, count 2 2006.286.05:16:49.90#ibcon#read 5, iclass 36, count 2 2006.286.05:16:49.90#ibcon#about to read 6, iclass 36, count 2 2006.286.05:16:49.90#ibcon#read 6, iclass 36, count 2 2006.286.05:16:49.90#ibcon#end of sib2, iclass 36, count 2 2006.286.05:16:49.90#ibcon#*after write, iclass 36, count 2 2006.286.05:16:49.90#ibcon#*before return 0, iclass 36, count 2 2006.286.05:16:49.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:16:49.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:16:49.90#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.05:16:49.90#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:49.90#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:16:50.02#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:16:50.02#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:16:50.02#ibcon#enter wrdev, iclass 36, count 0 2006.286.05:16:50.02#ibcon#first serial, iclass 36, count 0 2006.286.05:16:50.02#ibcon#enter sib2, iclass 36, count 0 2006.286.05:16:50.02#ibcon#flushed, iclass 36, count 0 2006.286.05:16:50.02#ibcon#about to write, iclass 36, count 0 2006.286.05:16:50.02#ibcon#wrote, iclass 36, count 0 2006.286.05:16:50.02#ibcon#about to read 3, iclass 36, count 0 2006.286.05:16:50.04#ibcon#read 3, iclass 36, count 0 2006.286.05:16:50.04#ibcon#about to read 4, iclass 36, count 0 2006.286.05:16:50.04#ibcon#read 4, iclass 36, count 0 2006.286.05:16:50.04#ibcon#about to read 5, iclass 36, count 0 2006.286.05:16:50.04#ibcon#read 5, iclass 36, count 0 2006.286.05:16:50.04#ibcon#about to read 6, iclass 36, count 0 2006.286.05:16:50.04#ibcon#read 6, iclass 36, count 0 2006.286.05:16:50.04#ibcon#end of sib2, iclass 36, count 0 2006.286.05:16:50.04#ibcon#*mode == 0, iclass 36, count 0 2006.286.05:16:50.04#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.05:16:50.04#ibcon#[25=USB\r\n] 2006.286.05:16:50.04#ibcon#*before write, iclass 36, count 0 2006.286.05:16:50.04#ibcon#enter sib2, iclass 36, count 0 2006.286.05:16:50.04#ibcon#flushed, iclass 36, count 0 2006.286.05:16:50.04#ibcon#about to write, iclass 36, count 0 2006.286.05:16:50.04#ibcon#wrote, iclass 36, count 0 2006.286.05:16:50.04#ibcon#about to read 3, iclass 36, count 0 2006.286.05:16:50.07#ibcon#read 3, iclass 36, count 0 2006.286.05:16:50.07#ibcon#about to read 4, iclass 36, count 0 2006.286.05:16:50.07#ibcon#read 4, iclass 36, count 0 2006.286.05:16:50.07#ibcon#about to read 5, iclass 36, count 0 2006.286.05:16:50.07#ibcon#read 5, iclass 36, count 0 2006.286.05:16:50.07#ibcon#about to read 6, iclass 36, count 0 2006.286.05:16:50.07#ibcon#read 6, iclass 36, count 0 2006.286.05:16:50.07#ibcon#end of sib2, iclass 36, count 0 2006.286.05:16:50.07#ibcon#*after write, iclass 36, count 0 2006.286.05:16:50.07#ibcon#*before return 0, iclass 36, count 0 2006.286.05:16:50.07#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:16:50.07#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:16:50.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.05:16:50.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.05:16:50.07$vck44/valo=5,734.99 2006.286.05:16:50.07#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.05:16:50.07#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.05:16:50.07#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:50.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:16:50.07#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:16:50.07#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:16:50.07#ibcon#enter wrdev, iclass 38, count 0 2006.286.05:16:50.07#ibcon#first serial, iclass 38, count 0 2006.286.05:16:50.07#ibcon#enter sib2, iclass 38, count 0 2006.286.05:16:50.07#ibcon#flushed, iclass 38, count 0 2006.286.05:16:50.07#ibcon#about to write, iclass 38, count 0 2006.286.05:16:50.07#ibcon#wrote, iclass 38, count 0 2006.286.05:16:50.07#ibcon#about to read 3, iclass 38, count 0 2006.286.05:16:50.09#ibcon#read 3, iclass 38, count 0 2006.286.05:16:50.33#ibcon#about to read 4, iclass 38, count 0 2006.286.05:16:50.33#ibcon#read 4, iclass 38, count 0 2006.286.05:16:50.33#ibcon#about to read 5, iclass 38, count 0 2006.286.05:16:50.33#ibcon#read 5, iclass 38, count 0 2006.286.05:16:50.33#ibcon#about to read 6, iclass 38, count 0 2006.286.05:16:50.33#ibcon#read 6, iclass 38, count 0 2006.286.05:16:50.33#ibcon#end of sib2, iclass 38, count 0 2006.286.05:16:50.33#ibcon#*mode == 0, iclass 38, count 0 2006.286.05:16:50.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.05:16:50.33#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.05:16:50.33#ibcon#*before write, iclass 38, count 0 2006.286.05:16:50.33#ibcon#enter sib2, iclass 38, count 0 2006.286.05:16:50.33#ibcon#flushed, iclass 38, count 0 2006.286.05:16:50.33#ibcon#about to write, iclass 38, count 0 2006.286.05:16:50.33#ibcon#wrote, iclass 38, count 0 2006.286.05:16:50.33#ibcon#about to read 3, iclass 38, count 0 2006.286.05:16:50.37#ibcon#read 3, iclass 38, count 0 2006.286.05:16:50.37#ibcon#about to read 4, iclass 38, count 0 2006.286.05:16:50.37#ibcon#read 4, iclass 38, count 0 2006.286.05:16:50.37#ibcon#about to read 5, iclass 38, count 0 2006.286.05:16:50.37#ibcon#read 5, iclass 38, count 0 2006.286.05:16:50.37#ibcon#about to read 6, iclass 38, count 0 2006.286.05:16:50.37#ibcon#read 6, iclass 38, count 0 2006.286.05:16:50.37#ibcon#end of sib2, iclass 38, count 0 2006.286.05:16:50.37#ibcon#*after write, iclass 38, count 0 2006.286.05:16:50.37#ibcon#*before return 0, iclass 38, count 0 2006.286.05:16:50.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:16:50.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:16:50.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.05:16:50.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.05:16:50.37$vck44/va=5,3 2006.286.05:16:50.37#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.05:16:50.37#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.05:16:50.37#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:50.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:16:50.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:16:50.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:16:50.37#ibcon#enter wrdev, iclass 40, count 2 2006.286.05:16:50.37#ibcon#first serial, iclass 40, count 2 2006.286.05:16:50.37#ibcon#enter sib2, iclass 40, count 2 2006.286.05:16:50.37#ibcon#flushed, iclass 40, count 2 2006.286.05:16:50.37#ibcon#about to write, iclass 40, count 2 2006.286.05:16:50.37#ibcon#wrote, iclass 40, count 2 2006.286.05:16:50.37#ibcon#about to read 3, iclass 40, count 2 2006.286.05:16:50.39#ibcon#read 3, iclass 40, count 2 2006.286.05:16:50.39#ibcon#about to read 4, iclass 40, count 2 2006.286.05:16:50.39#ibcon#read 4, iclass 40, count 2 2006.286.05:16:50.39#ibcon#about to read 5, iclass 40, count 2 2006.286.05:16:50.39#ibcon#read 5, iclass 40, count 2 2006.286.05:16:50.39#ibcon#about to read 6, iclass 40, count 2 2006.286.05:16:50.39#ibcon#read 6, iclass 40, count 2 2006.286.05:16:50.39#ibcon#end of sib2, iclass 40, count 2 2006.286.05:16:50.39#ibcon#*mode == 0, iclass 40, count 2 2006.286.05:16:50.39#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.05:16:50.39#ibcon#[25=AT05-03\r\n] 2006.286.05:16:50.39#ibcon#*before write, iclass 40, count 2 2006.286.05:16:50.39#ibcon#enter sib2, iclass 40, count 2 2006.286.05:16:50.39#ibcon#flushed, iclass 40, count 2 2006.286.05:16:50.39#ibcon#about to write, iclass 40, count 2 2006.286.05:16:50.39#ibcon#wrote, iclass 40, count 2 2006.286.05:16:50.39#ibcon#about to read 3, iclass 40, count 2 2006.286.05:16:50.42#ibcon#read 3, iclass 40, count 2 2006.286.05:16:50.42#ibcon#about to read 4, iclass 40, count 2 2006.286.05:16:50.42#ibcon#read 4, iclass 40, count 2 2006.286.05:16:50.42#ibcon#about to read 5, iclass 40, count 2 2006.286.05:16:50.42#ibcon#read 5, iclass 40, count 2 2006.286.05:16:50.42#ibcon#about to read 6, iclass 40, count 2 2006.286.05:16:50.42#ibcon#read 6, iclass 40, count 2 2006.286.05:16:50.42#ibcon#end of sib2, iclass 40, count 2 2006.286.05:16:50.42#ibcon#*after write, iclass 40, count 2 2006.286.05:16:50.42#ibcon#*before return 0, iclass 40, count 2 2006.286.05:16:50.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:16:50.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:16:50.42#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.05:16:50.42#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:50.42#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:16:50.54#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:16:50.54#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:16:50.54#ibcon#enter wrdev, iclass 40, count 0 2006.286.05:16:50.54#ibcon#first serial, iclass 40, count 0 2006.286.05:16:50.54#ibcon#enter sib2, iclass 40, count 0 2006.286.05:16:50.54#ibcon#flushed, iclass 40, count 0 2006.286.05:16:50.54#ibcon#about to write, iclass 40, count 0 2006.286.05:16:50.54#ibcon#wrote, iclass 40, count 0 2006.286.05:16:50.54#ibcon#about to read 3, iclass 40, count 0 2006.286.05:16:50.56#ibcon#read 3, iclass 40, count 0 2006.286.05:16:50.56#ibcon#about to read 4, iclass 40, count 0 2006.286.05:16:50.56#ibcon#read 4, iclass 40, count 0 2006.286.05:16:50.56#ibcon#about to read 5, iclass 40, count 0 2006.286.05:16:50.56#ibcon#read 5, iclass 40, count 0 2006.286.05:16:50.56#ibcon#about to read 6, iclass 40, count 0 2006.286.05:16:50.56#ibcon#read 6, iclass 40, count 0 2006.286.05:16:50.56#ibcon#end of sib2, iclass 40, count 0 2006.286.05:16:50.56#ibcon#*mode == 0, iclass 40, count 0 2006.286.05:16:50.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.05:16:50.56#ibcon#[25=USB\r\n] 2006.286.05:16:50.56#ibcon#*before write, iclass 40, count 0 2006.286.05:16:50.56#ibcon#enter sib2, iclass 40, count 0 2006.286.05:16:50.56#ibcon#flushed, iclass 40, count 0 2006.286.05:16:50.56#ibcon#about to write, iclass 40, count 0 2006.286.05:16:50.56#ibcon#wrote, iclass 40, count 0 2006.286.05:16:50.56#ibcon#about to read 3, iclass 40, count 0 2006.286.05:16:50.59#ibcon#read 3, iclass 40, count 0 2006.286.05:16:50.59#ibcon#about to read 4, iclass 40, count 0 2006.286.05:16:50.59#ibcon#read 4, iclass 40, count 0 2006.286.05:16:50.59#ibcon#about to read 5, iclass 40, count 0 2006.286.05:16:50.59#ibcon#read 5, iclass 40, count 0 2006.286.05:16:50.59#ibcon#about to read 6, iclass 40, count 0 2006.286.05:16:50.59#ibcon#read 6, iclass 40, count 0 2006.286.05:16:50.59#ibcon#end of sib2, iclass 40, count 0 2006.286.05:16:50.59#ibcon#*after write, iclass 40, count 0 2006.286.05:16:50.59#ibcon#*before return 0, iclass 40, count 0 2006.286.05:16:50.59#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:16:50.59#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:16:50.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.05:16:50.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.05:16:50.59$vck44/valo=6,814.99 2006.286.05:16:50.59#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.05:16:50.59#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.05:16:50.59#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:50.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:16:50.59#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:16:50.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:16:50.59#ibcon#enter wrdev, iclass 4, count 0 2006.286.05:16:50.59#ibcon#first serial, iclass 4, count 0 2006.286.05:16:50.59#ibcon#enter sib2, iclass 4, count 0 2006.286.05:16:50.59#ibcon#flushed, iclass 4, count 0 2006.286.05:16:50.59#ibcon#about to write, iclass 4, count 0 2006.286.05:16:50.59#ibcon#wrote, iclass 4, count 0 2006.286.05:16:50.59#ibcon#about to read 3, iclass 4, count 0 2006.286.05:16:50.61#ibcon#read 3, iclass 4, count 0 2006.286.05:16:50.67#ibcon#about to read 4, iclass 4, count 0 2006.286.05:16:50.67#ibcon#read 4, iclass 4, count 0 2006.286.05:16:50.67#ibcon#about to read 5, iclass 4, count 0 2006.286.05:16:50.67#ibcon#read 5, iclass 4, count 0 2006.286.05:16:50.67#ibcon#about to read 6, iclass 4, count 0 2006.286.05:16:50.67#ibcon#read 6, iclass 4, count 0 2006.286.05:16:50.67#ibcon#end of sib2, iclass 4, count 0 2006.286.05:16:50.67#ibcon#*mode == 0, iclass 4, count 0 2006.286.05:16:50.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.05:16:50.67#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.05:16:50.67#ibcon#*before write, iclass 4, count 0 2006.286.05:16:50.67#ibcon#enter sib2, iclass 4, count 0 2006.286.05:16:50.67#ibcon#flushed, iclass 4, count 0 2006.286.05:16:50.67#ibcon#about to write, iclass 4, count 0 2006.286.05:16:50.67#ibcon#wrote, iclass 4, count 0 2006.286.05:16:50.67#ibcon#about to read 3, iclass 4, count 0 2006.286.05:16:50.71#ibcon#read 3, iclass 4, count 0 2006.286.05:16:50.71#ibcon#about to read 4, iclass 4, count 0 2006.286.05:16:50.71#ibcon#read 4, iclass 4, count 0 2006.286.05:16:50.71#ibcon#about to read 5, iclass 4, count 0 2006.286.05:16:50.71#ibcon#read 5, iclass 4, count 0 2006.286.05:16:50.71#ibcon#about to read 6, iclass 4, count 0 2006.286.05:16:50.71#ibcon#read 6, iclass 4, count 0 2006.286.05:16:50.71#ibcon#end of sib2, iclass 4, count 0 2006.286.05:16:50.71#ibcon#*after write, iclass 4, count 0 2006.286.05:16:50.71#ibcon#*before return 0, iclass 4, count 0 2006.286.05:16:50.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:16:50.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:16:50.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.05:16:50.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.05:16:50.71$vck44/va=6,4 2006.286.05:16:50.71#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.05:16:50.71#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.05:16:50.71#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:50.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:16:50.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:16:50.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:16:50.71#ibcon#enter wrdev, iclass 6, count 2 2006.286.05:16:50.71#ibcon#first serial, iclass 6, count 2 2006.286.05:16:50.71#ibcon#enter sib2, iclass 6, count 2 2006.286.05:16:50.71#ibcon#flushed, iclass 6, count 2 2006.286.05:16:50.71#ibcon#about to write, iclass 6, count 2 2006.286.05:16:50.71#ibcon#wrote, iclass 6, count 2 2006.286.05:16:50.71#ibcon#about to read 3, iclass 6, count 2 2006.286.05:16:50.73#ibcon#read 3, iclass 6, count 2 2006.286.05:16:50.73#ibcon#about to read 4, iclass 6, count 2 2006.286.05:16:50.73#ibcon#read 4, iclass 6, count 2 2006.286.05:16:50.73#ibcon#about to read 5, iclass 6, count 2 2006.286.05:16:50.73#ibcon#read 5, iclass 6, count 2 2006.286.05:16:50.73#ibcon#about to read 6, iclass 6, count 2 2006.286.05:16:50.73#ibcon#read 6, iclass 6, count 2 2006.286.05:16:50.73#ibcon#end of sib2, iclass 6, count 2 2006.286.05:16:50.73#ibcon#*mode == 0, iclass 6, count 2 2006.286.05:16:50.73#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.05:16:50.73#ibcon#[25=AT06-04\r\n] 2006.286.05:16:50.73#ibcon#*before write, iclass 6, count 2 2006.286.05:16:50.73#ibcon#enter sib2, iclass 6, count 2 2006.286.05:16:50.73#ibcon#flushed, iclass 6, count 2 2006.286.05:16:50.73#ibcon#about to write, iclass 6, count 2 2006.286.05:16:50.73#ibcon#wrote, iclass 6, count 2 2006.286.05:16:50.73#ibcon#about to read 3, iclass 6, count 2 2006.286.05:16:50.76#ibcon#read 3, iclass 6, count 2 2006.286.05:16:50.76#ibcon#about to read 4, iclass 6, count 2 2006.286.05:16:50.76#ibcon#read 4, iclass 6, count 2 2006.286.05:16:50.76#ibcon#about to read 5, iclass 6, count 2 2006.286.05:16:50.76#ibcon#read 5, iclass 6, count 2 2006.286.05:16:50.76#ibcon#about to read 6, iclass 6, count 2 2006.286.05:16:50.76#ibcon#read 6, iclass 6, count 2 2006.286.05:16:50.76#ibcon#end of sib2, iclass 6, count 2 2006.286.05:16:50.76#ibcon#*after write, iclass 6, count 2 2006.286.05:16:50.76#ibcon#*before return 0, iclass 6, count 2 2006.286.05:16:50.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:16:50.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:16:50.76#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.05:16:50.76#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:50.76#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:16:50.88#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:16:50.88#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:16:50.88#ibcon#enter wrdev, iclass 6, count 0 2006.286.05:16:50.88#ibcon#first serial, iclass 6, count 0 2006.286.05:16:50.88#ibcon#enter sib2, iclass 6, count 0 2006.286.05:16:50.88#ibcon#flushed, iclass 6, count 0 2006.286.05:16:50.88#ibcon#about to write, iclass 6, count 0 2006.286.05:16:50.88#ibcon#wrote, iclass 6, count 0 2006.286.05:16:50.88#ibcon#about to read 3, iclass 6, count 0 2006.286.05:16:50.90#ibcon#read 3, iclass 6, count 0 2006.286.05:16:50.90#ibcon#about to read 4, iclass 6, count 0 2006.286.05:16:50.90#ibcon#read 4, iclass 6, count 0 2006.286.05:16:50.90#ibcon#about to read 5, iclass 6, count 0 2006.286.05:16:50.90#ibcon#read 5, iclass 6, count 0 2006.286.05:16:50.90#ibcon#about to read 6, iclass 6, count 0 2006.286.05:16:50.90#ibcon#read 6, iclass 6, count 0 2006.286.05:16:50.90#ibcon#end of sib2, iclass 6, count 0 2006.286.05:16:50.90#ibcon#*mode == 0, iclass 6, count 0 2006.286.05:16:50.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.05:16:50.90#ibcon#[25=USB\r\n] 2006.286.05:16:50.90#ibcon#*before write, iclass 6, count 0 2006.286.05:16:50.90#ibcon#enter sib2, iclass 6, count 0 2006.286.05:16:50.90#ibcon#flushed, iclass 6, count 0 2006.286.05:16:50.90#ibcon#about to write, iclass 6, count 0 2006.286.05:16:50.90#ibcon#wrote, iclass 6, count 0 2006.286.05:16:50.90#ibcon#about to read 3, iclass 6, count 0 2006.286.05:16:50.93#ibcon#read 3, iclass 6, count 0 2006.286.05:16:50.93#ibcon#about to read 4, iclass 6, count 0 2006.286.05:16:50.93#ibcon#read 4, iclass 6, count 0 2006.286.05:16:50.93#ibcon#about to read 5, iclass 6, count 0 2006.286.05:16:50.93#ibcon#read 5, iclass 6, count 0 2006.286.05:16:50.93#ibcon#about to read 6, iclass 6, count 0 2006.286.05:16:50.93#ibcon#read 6, iclass 6, count 0 2006.286.05:16:50.93#ibcon#end of sib2, iclass 6, count 0 2006.286.05:16:50.93#ibcon#*after write, iclass 6, count 0 2006.286.05:16:50.93#ibcon#*before return 0, iclass 6, count 0 2006.286.05:16:50.93#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:16:50.93#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:16:50.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.05:16:50.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.05:16:50.93$vck44/valo=7,864.99 2006.286.05:16:50.93#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.05:16:50.93#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.05:16:50.93#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:50.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:16:50.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:16:50.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:16:50.93#ibcon#enter wrdev, iclass 10, count 0 2006.286.05:16:50.93#ibcon#first serial, iclass 10, count 0 2006.286.05:16:50.93#ibcon#enter sib2, iclass 10, count 0 2006.286.05:16:50.93#ibcon#flushed, iclass 10, count 0 2006.286.05:16:50.93#ibcon#about to write, iclass 10, count 0 2006.286.05:16:50.93#ibcon#wrote, iclass 10, count 0 2006.286.05:16:50.93#ibcon#about to read 3, iclass 10, count 0 2006.286.05:16:50.95#ibcon#read 3, iclass 10, count 0 2006.286.05:16:50.95#ibcon#about to read 4, iclass 10, count 0 2006.286.05:16:50.95#ibcon#read 4, iclass 10, count 0 2006.286.05:16:50.95#ibcon#about to read 5, iclass 10, count 0 2006.286.05:16:50.95#ibcon#read 5, iclass 10, count 0 2006.286.05:16:50.95#ibcon#about to read 6, iclass 10, count 0 2006.286.05:16:50.95#ibcon#read 6, iclass 10, count 0 2006.286.05:16:50.95#ibcon#end of sib2, iclass 10, count 0 2006.286.05:16:50.95#ibcon#*mode == 0, iclass 10, count 0 2006.286.05:16:50.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.05:16:50.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.05:16:50.95#ibcon#*before write, iclass 10, count 0 2006.286.05:16:50.95#ibcon#enter sib2, iclass 10, count 0 2006.286.05:16:50.95#ibcon#flushed, iclass 10, count 0 2006.286.05:16:50.95#ibcon#about to write, iclass 10, count 0 2006.286.05:16:50.95#ibcon#wrote, iclass 10, count 0 2006.286.05:16:50.95#ibcon#about to read 3, iclass 10, count 0 2006.286.05:16:50.99#ibcon#read 3, iclass 10, count 0 2006.286.05:16:50.99#ibcon#about to read 4, iclass 10, count 0 2006.286.05:16:50.99#ibcon#read 4, iclass 10, count 0 2006.286.05:16:50.99#ibcon#about to read 5, iclass 10, count 0 2006.286.05:16:50.99#ibcon#read 5, iclass 10, count 0 2006.286.05:16:50.99#ibcon#about to read 6, iclass 10, count 0 2006.286.05:16:50.99#ibcon#read 6, iclass 10, count 0 2006.286.05:16:50.99#ibcon#end of sib2, iclass 10, count 0 2006.286.05:16:50.99#ibcon#*after write, iclass 10, count 0 2006.286.05:16:50.99#ibcon#*before return 0, iclass 10, count 0 2006.286.05:16:50.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:16:50.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:16:50.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.05:16:50.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.05:16:50.99$vck44/va=7,4 2006.286.05:16:50.99#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.05:16:50.99#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.05:16:50.99#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:50.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:16:51.05#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:16:51.05#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:16:51.05#ibcon#enter wrdev, iclass 12, count 2 2006.286.05:16:51.05#ibcon#first serial, iclass 12, count 2 2006.286.05:16:51.05#ibcon#enter sib2, iclass 12, count 2 2006.286.05:16:51.05#ibcon#flushed, iclass 12, count 2 2006.286.05:16:51.05#ibcon#about to write, iclass 12, count 2 2006.286.05:16:51.05#ibcon#wrote, iclass 12, count 2 2006.286.05:16:51.05#ibcon#about to read 3, iclass 12, count 2 2006.286.05:16:51.07#ibcon#read 3, iclass 12, count 2 2006.286.05:16:51.07#ibcon#about to read 4, iclass 12, count 2 2006.286.05:16:51.07#ibcon#read 4, iclass 12, count 2 2006.286.05:16:51.07#ibcon#about to read 5, iclass 12, count 2 2006.286.05:16:51.07#ibcon#read 5, iclass 12, count 2 2006.286.05:16:51.07#ibcon#about to read 6, iclass 12, count 2 2006.286.05:16:51.07#ibcon#read 6, iclass 12, count 2 2006.286.05:16:51.07#ibcon#end of sib2, iclass 12, count 2 2006.286.05:16:51.07#ibcon#*mode == 0, iclass 12, count 2 2006.286.05:16:51.07#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.05:16:51.07#ibcon#[25=AT07-04\r\n] 2006.286.05:16:51.07#ibcon#*before write, iclass 12, count 2 2006.286.05:16:51.07#ibcon#enter sib2, iclass 12, count 2 2006.286.05:16:51.07#ibcon#flushed, iclass 12, count 2 2006.286.05:16:51.07#ibcon#about to write, iclass 12, count 2 2006.286.05:16:51.07#ibcon#wrote, iclass 12, count 2 2006.286.05:16:51.07#ibcon#about to read 3, iclass 12, count 2 2006.286.05:16:51.10#ibcon#read 3, iclass 12, count 2 2006.286.05:16:51.10#ibcon#about to read 4, iclass 12, count 2 2006.286.05:16:51.10#ibcon#read 4, iclass 12, count 2 2006.286.05:16:51.10#ibcon#about to read 5, iclass 12, count 2 2006.286.05:16:51.10#ibcon#read 5, iclass 12, count 2 2006.286.05:16:51.10#ibcon#about to read 6, iclass 12, count 2 2006.286.05:16:51.10#ibcon#read 6, iclass 12, count 2 2006.286.05:16:51.10#ibcon#end of sib2, iclass 12, count 2 2006.286.05:16:51.10#ibcon#*after write, iclass 12, count 2 2006.286.05:16:51.10#ibcon#*before return 0, iclass 12, count 2 2006.286.05:16:51.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:16:51.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:16:51.10#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.05:16:51.10#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:51.10#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:16:51.22#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:16:51.22#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:16:51.22#ibcon#enter wrdev, iclass 12, count 0 2006.286.05:16:51.22#ibcon#first serial, iclass 12, count 0 2006.286.05:16:51.22#ibcon#enter sib2, iclass 12, count 0 2006.286.05:16:51.22#ibcon#flushed, iclass 12, count 0 2006.286.05:16:51.22#ibcon#about to write, iclass 12, count 0 2006.286.05:16:51.22#ibcon#wrote, iclass 12, count 0 2006.286.05:16:51.22#ibcon#about to read 3, iclass 12, count 0 2006.286.05:16:51.24#ibcon#read 3, iclass 12, count 0 2006.286.05:16:51.24#ibcon#about to read 4, iclass 12, count 0 2006.286.05:16:51.24#ibcon#read 4, iclass 12, count 0 2006.286.05:16:51.24#ibcon#about to read 5, iclass 12, count 0 2006.286.05:16:51.24#ibcon#read 5, iclass 12, count 0 2006.286.05:16:51.24#ibcon#about to read 6, iclass 12, count 0 2006.286.05:16:51.24#ibcon#read 6, iclass 12, count 0 2006.286.05:16:51.24#ibcon#end of sib2, iclass 12, count 0 2006.286.05:16:51.24#ibcon#*mode == 0, iclass 12, count 0 2006.286.05:16:51.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.05:16:51.24#ibcon#[25=USB\r\n] 2006.286.05:16:51.24#ibcon#*before write, iclass 12, count 0 2006.286.05:16:51.24#ibcon#enter sib2, iclass 12, count 0 2006.286.05:16:51.24#ibcon#flushed, iclass 12, count 0 2006.286.05:16:51.24#ibcon#about to write, iclass 12, count 0 2006.286.05:16:51.24#ibcon#wrote, iclass 12, count 0 2006.286.05:16:51.24#ibcon#about to read 3, iclass 12, count 0 2006.286.05:16:51.27#ibcon#read 3, iclass 12, count 0 2006.286.05:16:51.27#ibcon#about to read 4, iclass 12, count 0 2006.286.05:16:51.27#ibcon#read 4, iclass 12, count 0 2006.286.05:16:51.27#ibcon#about to read 5, iclass 12, count 0 2006.286.05:16:51.27#ibcon#read 5, iclass 12, count 0 2006.286.05:16:51.27#ibcon#about to read 6, iclass 12, count 0 2006.286.05:16:51.27#ibcon#read 6, iclass 12, count 0 2006.286.05:16:51.27#ibcon#end of sib2, iclass 12, count 0 2006.286.05:16:51.27#ibcon#*after write, iclass 12, count 0 2006.286.05:16:51.27#ibcon#*before return 0, iclass 12, count 0 2006.286.05:16:51.27#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:16:51.27#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:16:51.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.05:16:51.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.05:16:51.27$vck44/valo=8,884.99 2006.286.05:16:51.27#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.05:16:51.27#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.05:16:51.27#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:51.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:16:51.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:16:51.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:16:51.27#ibcon#enter wrdev, iclass 14, count 0 2006.286.05:16:51.27#ibcon#first serial, iclass 14, count 0 2006.286.05:16:51.27#ibcon#enter sib2, iclass 14, count 0 2006.286.05:16:51.27#ibcon#flushed, iclass 14, count 0 2006.286.05:16:51.27#ibcon#about to write, iclass 14, count 0 2006.286.05:16:51.27#ibcon#wrote, iclass 14, count 0 2006.286.05:16:51.27#ibcon#about to read 3, iclass 14, count 0 2006.286.05:16:51.29#ibcon#read 3, iclass 14, count 0 2006.286.05:16:51.29#ibcon#about to read 4, iclass 14, count 0 2006.286.05:16:51.29#ibcon#read 4, iclass 14, count 0 2006.286.05:16:51.29#ibcon#about to read 5, iclass 14, count 0 2006.286.05:16:51.29#ibcon#read 5, iclass 14, count 0 2006.286.05:16:51.29#ibcon#about to read 6, iclass 14, count 0 2006.286.05:16:51.29#ibcon#read 6, iclass 14, count 0 2006.286.05:16:51.29#ibcon#end of sib2, iclass 14, count 0 2006.286.05:16:51.29#ibcon#*mode == 0, iclass 14, count 0 2006.286.05:16:51.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.05:16:51.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.05:16:51.29#ibcon#*before write, iclass 14, count 0 2006.286.05:16:51.29#ibcon#enter sib2, iclass 14, count 0 2006.286.05:16:51.29#ibcon#flushed, iclass 14, count 0 2006.286.05:16:51.29#ibcon#about to write, iclass 14, count 0 2006.286.05:16:51.29#ibcon#wrote, iclass 14, count 0 2006.286.05:16:51.29#ibcon#about to read 3, iclass 14, count 0 2006.286.05:16:51.33#ibcon#read 3, iclass 14, count 0 2006.286.05:16:51.33#ibcon#about to read 4, iclass 14, count 0 2006.286.05:16:51.33#ibcon#read 4, iclass 14, count 0 2006.286.05:16:51.33#ibcon#about to read 5, iclass 14, count 0 2006.286.05:16:51.33#ibcon#read 5, iclass 14, count 0 2006.286.05:16:51.33#ibcon#about to read 6, iclass 14, count 0 2006.286.05:16:51.33#ibcon#read 6, iclass 14, count 0 2006.286.05:16:51.33#ibcon#end of sib2, iclass 14, count 0 2006.286.05:16:51.33#ibcon#*after write, iclass 14, count 0 2006.286.05:16:51.33#ibcon#*before return 0, iclass 14, count 0 2006.286.05:16:51.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:16:51.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:16:51.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.05:16:51.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.05:16:51.33$vck44/va=8,3 2006.286.05:16:51.33#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.05:16:51.33#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.05:16:51.33#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:51.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:16:51.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:16:51.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:16:51.39#ibcon#enter wrdev, iclass 16, count 2 2006.286.05:16:51.39#ibcon#first serial, iclass 16, count 2 2006.286.05:16:51.39#ibcon#enter sib2, iclass 16, count 2 2006.286.05:16:51.39#ibcon#flushed, iclass 16, count 2 2006.286.05:16:51.39#ibcon#about to write, iclass 16, count 2 2006.286.05:16:51.39#ibcon#wrote, iclass 16, count 2 2006.286.05:16:51.39#ibcon#about to read 3, iclass 16, count 2 2006.286.05:16:51.41#ibcon#read 3, iclass 16, count 2 2006.286.05:16:51.41#ibcon#about to read 4, iclass 16, count 2 2006.286.05:16:51.41#ibcon#read 4, iclass 16, count 2 2006.286.05:16:51.41#ibcon#about to read 5, iclass 16, count 2 2006.286.05:16:51.41#ibcon#read 5, iclass 16, count 2 2006.286.05:16:51.41#ibcon#about to read 6, iclass 16, count 2 2006.286.05:16:51.41#ibcon#read 6, iclass 16, count 2 2006.286.05:16:51.41#ibcon#end of sib2, iclass 16, count 2 2006.286.05:16:51.41#ibcon#*mode == 0, iclass 16, count 2 2006.286.05:16:51.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.05:16:51.41#ibcon#[25=AT08-03\r\n] 2006.286.05:16:51.41#ibcon#*before write, iclass 16, count 2 2006.286.05:16:51.41#ibcon#enter sib2, iclass 16, count 2 2006.286.05:16:51.41#ibcon#flushed, iclass 16, count 2 2006.286.05:16:51.41#ibcon#about to write, iclass 16, count 2 2006.286.05:16:51.41#ibcon#wrote, iclass 16, count 2 2006.286.05:16:51.41#ibcon#about to read 3, iclass 16, count 2 2006.286.05:16:51.44#ibcon#read 3, iclass 16, count 2 2006.286.05:16:51.44#ibcon#about to read 4, iclass 16, count 2 2006.286.05:16:51.44#ibcon#read 4, iclass 16, count 2 2006.286.05:16:51.44#ibcon#about to read 5, iclass 16, count 2 2006.286.05:16:51.44#ibcon#read 5, iclass 16, count 2 2006.286.05:16:51.44#ibcon#about to read 6, iclass 16, count 2 2006.286.05:16:51.44#ibcon#read 6, iclass 16, count 2 2006.286.05:16:51.44#ibcon#end of sib2, iclass 16, count 2 2006.286.05:16:51.44#ibcon#*after write, iclass 16, count 2 2006.286.05:16:51.44#ibcon#*before return 0, iclass 16, count 2 2006.286.05:16:51.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:16:51.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:16:51.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.05:16:51.44#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:51.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:16:51.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:16:51.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:16:51.56#ibcon#enter wrdev, iclass 16, count 0 2006.286.05:16:51.56#ibcon#first serial, iclass 16, count 0 2006.286.05:16:51.56#ibcon#enter sib2, iclass 16, count 0 2006.286.05:16:51.56#ibcon#flushed, iclass 16, count 0 2006.286.05:16:51.56#ibcon#about to write, iclass 16, count 0 2006.286.05:16:51.56#ibcon#wrote, iclass 16, count 0 2006.286.05:16:51.56#ibcon#about to read 3, iclass 16, count 0 2006.286.05:16:51.58#ibcon#read 3, iclass 16, count 0 2006.286.05:16:51.58#ibcon#about to read 4, iclass 16, count 0 2006.286.05:16:51.58#ibcon#read 4, iclass 16, count 0 2006.286.05:16:51.58#ibcon#about to read 5, iclass 16, count 0 2006.286.05:16:51.58#ibcon#read 5, iclass 16, count 0 2006.286.05:16:51.58#ibcon#about to read 6, iclass 16, count 0 2006.286.05:16:51.58#ibcon#read 6, iclass 16, count 0 2006.286.05:16:51.58#ibcon#end of sib2, iclass 16, count 0 2006.286.05:16:51.58#ibcon#*mode == 0, iclass 16, count 0 2006.286.05:16:51.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.05:16:51.58#ibcon#[25=USB\r\n] 2006.286.05:16:51.58#ibcon#*before write, iclass 16, count 0 2006.286.05:16:51.58#ibcon#enter sib2, iclass 16, count 0 2006.286.05:16:51.58#ibcon#flushed, iclass 16, count 0 2006.286.05:16:51.58#ibcon#about to write, iclass 16, count 0 2006.286.05:16:51.58#ibcon#wrote, iclass 16, count 0 2006.286.05:16:51.58#ibcon#about to read 3, iclass 16, count 0 2006.286.05:16:51.61#ibcon#read 3, iclass 16, count 0 2006.286.05:16:51.61#ibcon#about to read 4, iclass 16, count 0 2006.286.05:16:51.61#ibcon#read 4, iclass 16, count 0 2006.286.05:16:51.61#ibcon#about to read 5, iclass 16, count 0 2006.286.05:16:51.61#ibcon#read 5, iclass 16, count 0 2006.286.05:16:51.61#ibcon#about to read 6, iclass 16, count 0 2006.286.05:16:51.61#ibcon#read 6, iclass 16, count 0 2006.286.05:16:51.61#ibcon#end of sib2, iclass 16, count 0 2006.286.05:16:51.61#ibcon#*after write, iclass 16, count 0 2006.286.05:16:51.61#ibcon#*before return 0, iclass 16, count 0 2006.286.05:16:51.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:16:51.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:16:51.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.05:16:51.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.05:16:51.61$vck44/vblo=1,629.99 2006.286.05:16:51.61#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.05:16:51.61#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.05:16:51.61#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:51.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:16:51.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:16:51.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:16:51.61#ibcon#enter wrdev, iclass 18, count 0 2006.286.05:16:51.61#ibcon#first serial, iclass 18, count 0 2006.286.05:16:51.61#ibcon#enter sib2, iclass 18, count 0 2006.286.05:16:51.61#ibcon#flushed, iclass 18, count 0 2006.286.05:16:51.61#ibcon#about to write, iclass 18, count 0 2006.286.05:16:51.61#ibcon#wrote, iclass 18, count 0 2006.286.05:16:51.61#ibcon#about to read 3, iclass 18, count 0 2006.286.05:16:51.63#ibcon#read 3, iclass 18, count 0 2006.286.05:16:51.71#ibcon#about to read 4, iclass 18, count 0 2006.286.05:16:51.71#ibcon#read 4, iclass 18, count 0 2006.286.05:16:51.71#ibcon#about to read 5, iclass 18, count 0 2006.286.05:16:51.71#ibcon#read 5, iclass 18, count 0 2006.286.05:16:51.71#ibcon#about to read 6, iclass 18, count 0 2006.286.05:16:51.71#ibcon#read 6, iclass 18, count 0 2006.286.05:16:51.71#ibcon#end of sib2, iclass 18, count 0 2006.286.05:16:51.71#ibcon#*mode == 0, iclass 18, count 0 2006.286.05:16:51.71#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.05:16:51.71#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.05:16:51.71#ibcon#*before write, iclass 18, count 0 2006.286.05:16:51.71#ibcon#enter sib2, iclass 18, count 0 2006.286.05:16:51.71#ibcon#flushed, iclass 18, count 0 2006.286.05:16:51.71#ibcon#about to write, iclass 18, count 0 2006.286.05:16:51.71#ibcon#wrote, iclass 18, count 0 2006.286.05:16:51.71#ibcon#about to read 3, iclass 18, count 0 2006.286.05:16:51.74#ibcon#read 3, iclass 18, count 0 2006.286.05:16:51.74#ibcon#about to read 4, iclass 18, count 0 2006.286.05:16:51.74#ibcon#read 4, iclass 18, count 0 2006.286.05:16:51.74#ibcon#about to read 5, iclass 18, count 0 2006.286.05:16:51.74#ibcon#read 5, iclass 18, count 0 2006.286.05:16:51.74#ibcon#about to read 6, iclass 18, count 0 2006.286.05:16:51.74#ibcon#read 6, iclass 18, count 0 2006.286.05:16:51.74#ibcon#end of sib2, iclass 18, count 0 2006.286.05:16:51.74#ibcon#*after write, iclass 18, count 0 2006.286.05:16:51.74#ibcon#*before return 0, iclass 18, count 0 2006.286.05:16:51.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:16:51.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:16:51.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.05:16:51.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.05:16:51.74$vck44/vb=1,4 2006.286.05:16:51.74#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.05:16:51.74#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.05:16:51.74#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:51.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:16:51.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:16:51.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:16:51.74#ibcon#enter wrdev, iclass 20, count 2 2006.286.05:16:51.74#ibcon#first serial, iclass 20, count 2 2006.286.05:16:51.74#ibcon#enter sib2, iclass 20, count 2 2006.286.05:16:51.74#ibcon#flushed, iclass 20, count 2 2006.286.05:16:51.74#ibcon#about to write, iclass 20, count 2 2006.286.05:16:51.74#ibcon#wrote, iclass 20, count 2 2006.286.05:16:51.74#ibcon#about to read 3, iclass 20, count 2 2006.286.05:16:51.76#ibcon#read 3, iclass 20, count 2 2006.286.05:16:51.76#ibcon#about to read 4, iclass 20, count 2 2006.286.05:16:51.76#ibcon#read 4, iclass 20, count 2 2006.286.05:16:51.76#ibcon#about to read 5, iclass 20, count 2 2006.286.05:16:51.76#ibcon#read 5, iclass 20, count 2 2006.286.05:16:51.76#ibcon#about to read 6, iclass 20, count 2 2006.286.05:16:51.76#ibcon#read 6, iclass 20, count 2 2006.286.05:16:51.76#ibcon#end of sib2, iclass 20, count 2 2006.286.05:16:51.76#ibcon#*mode == 0, iclass 20, count 2 2006.286.05:16:51.76#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.05:16:51.76#ibcon#[27=AT01-04\r\n] 2006.286.05:16:51.76#ibcon#*before write, iclass 20, count 2 2006.286.05:16:51.76#ibcon#enter sib2, iclass 20, count 2 2006.286.05:16:51.76#ibcon#flushed, iclass 20, count 2 2006.286.05:16:51.76#ibcon#about to write, iclass 20, count 2 2006.286.05:16:51.76#ibcon#wrote, iclass 20, count 2 2006.286.05:16:51.76#ibcon#about to read 3, iclass 20, count 2 2006.286.05:16:51.79#ibcon#read 3, iclass 20, count 2 2006.286.05:16:51.79#ibcon#about to read 4, iclass 20, count 2 2006.286.05:16:51.79#ibcon#read 4, iclass 20, count 2 2006.286.05:16:51.79#ibcon#about to read 5, iclass 20, count 2 2006.286.05:16:51.79#ibcon#read 5, iclass 20, count 2 2006.286.05:16:51.79#ibcon#about to read 6, iclass 20, count 2 2006.286.05:16:51.79#ibcon#read 6, iclass 20, count 2 2006.286.05:16:51.79#ibcon#end of sib2, iclass 20, count 2 2006.286.05:16:51.79#ibcon#*after write, iclass 20, count 2 2006.286.05:16:51.79#ibcon#*before return 0, iclass 20, count 2 2006.286.05:16:51.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:16:51.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:16:51.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.05:16:51.79#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:51.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:16:51.91#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:16:51.91#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:16:51.91#ibcon#enter wrdev, iclass 20, count 0 2006.286.05:16:51.91#ibcon#first serial, iclass 20, count 0 2006.286.05:16:51.91#ibcon#enter sib2, iclass 20, count 0 2006.286.05:16:51.91#ibcon#flushed, iclass 20, count 0 2006.286.05:16:51.91#ibcon#about to write, iclass 20, count 0 2006.286.05:16:51.91#ibcon#wrote, iclass 20, count 0 2006.286.05:16:51.91#ibcon#about to read 3, iclass 20, count 0 2006.286.05:16:51.93#ibcon#read 3, iclass 20, count 0 2006.286.05:16:51.93#ibcon#about to read 4, iclass 20, count 0 2006.286.05:16:51.93#ibcon#read 4, iclass 20, count 0 2006.286.05:16:51.93#ibcon#about to read 5, iclass 20, count 0 2006.286.05:16:51.93#ibcon#read 5, iclass 20, count 0 2006.286.05:16:51.93#ibcon#about to read 6, iclass 20, count 0 2006.286.05:16:51.93#ibcon#read 6, iclass 20, count 0 2006.286.05:16:51.93#ibcon#end of sib2, iclass 20, count 0 2006.286.05:16:51.93#ibcon#*mode == 0, iclass 20, count 0 2006.286.05:16:51.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.05:16:51.93#ibcon#[27=USB\r\n] 2006.286.05:16:51.93#ibcon#*before write, iclass 20, count 0 2006.286.05:16:51.93#ibcon#enter sib2, iclass 20, count 0 2006.286.05:16:51.93#ibcon#flushed, iclass 20, count 0 2006.286.05:16:51.93#ibcon#about to write, iclass 20, count 0 2006.286.05:16:51.93#ibcon#wrote, iclass 20, count 0 2006.286.05:16:51.93#ibcon#about to read 3, iclass 20, count 0 2006.286.05:16:51.96#ibcon#read 3, iclass 20, count 0 2006.286.05:16:51.96#ibcon#about to read 4, iclass 20, count 0 2006.286.05:16:51.96#ibcon#read 4, iclass 20, count 0 2006.286.05:16:51.96#ibcon#about to read 5, iclass 20, count 0 2006.286.05:16:51.96#ibcon#read 5, iclass 20, count 0 2006.286.05:16:51.96#ibcon#about to read 6, iclass 20, count 0 2006.286.05:16:51.96#ibcon#read 6, iclass 20, count 0 2006.286.05:16:51.96#ibcon#end of sib2, iclass 20, count 0 2006.286.05:16:51.96#ibcon#*after write, iclass 20, count 0 2006.286.05:16:51.96#ibcon#*before return 0, iclass 20, count 0 2006.286.05:16:51.96#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:16:51.96#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:16:51.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.05:16:51.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.05:16:51.96$vck44/vblo=2,634.99 2006.286.05:16:51.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.05:16:51.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.05:16:51.96#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:51.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:16:51.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:16:51.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:16:51.96#ibcon#enter wrdev, iclass 22, count 0 2006.286.05:16:51.96#ibcon#first serial, iclass 22, count 0 2006.286.05:16:51.96#ibcon#enter sib2, iclass 22, count 0 2006.286.05:16:51.96#ibcon#flushed, iclass 22, count 0 2006.286.05:16:51.96#ibcon#about to write, iclass 22, count 0 2006.286.05:16:51.96#ibcon#wrote, iclass 22, count 0 2006.286.05:16:51.96#ibcon#about to read 3, iclass 22, count 0 2006.286.05:16:51.98#ibcon#read 3, iclass 22, count 0 2006.286.05:16:51.98#ibcon#about to read 4, iclass 22, count 0 2006.286.05:16:51.98#ibcon#read 4, iclass 22, count 0 2006.286.05:16:51.98#ibcon#about to read 5, iclass 22, count 0 2006.286.05:16:51.98#ibcon#read 5, iclass 22, count 0 2006.286.05:16:51.98#ibcon#about to read 6, iclass 22, count 0 2006.286.05:16:51.98#ibcon#read 6, iclass 22, count 0 2006.286.05:16:51.98#ibcon#end of sib2, iclass 22, count 0 2006.286.05:16:51.98#ibcon#*mode == 0, iclass 22, count 0 2006.286.05:16:51.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.05:16:51.98#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.05:16:51.98#ibcon#*before write, iclass 22, count 0 2006.286.05:16:51.98#ibcon#enter sib2, iclass 22, count 0 2006.286.05:16:51.98#ibcon#flushed, iclass 22, count 0 2006.286.05:16:51.98#ibcon#about to write, iclass 22, count 0 2006.286.05:16:51.98#ibcon#wrote, iclass 22, count 0 2006.286.05:16:51.98#ibcon#about to read 3, iclass 22, count 0 2006.286.05:16:52.02#ibcon#read 3, iclass 22, count 0 2006.286.05:16:52.02#ibcon#about to read 4, iclass 22, count 0 2006.286.05:16:52.02#ibcon#read 4, iclass 22, count 0 2006.286.05:16:52.02#ibcon#about to read 5, iclass 22, count 0 2006.286.05:16:52.02#ibcon#read 5, iclass 22, count 0 2006.286.05:16:52.02#ibcon#about to read 6, iclass 22, count 0 2006.286.05:16:52.02#ibcon#read 6, iclass 22, count 0 2006.286.05:16:52.02#ibcon#end of sib2, iclass 22, count 0 2006.286.05:16:52.02#ibcon#*after write, iclass 22, count 0 2006.286.05:16:52.02#ibcon#*before return 0, iclass 22, count 0 2006.286.05:16:52.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:16:52.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:16:52.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.05:16:52.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.05:16:52.02$vck44/vb=2,5 2006.286.05:16:52.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.05:16:52.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.05:16:52.02#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:52.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:16:52.08#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:16:52.08#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:16:52.08#ibcon#enter wrdev, iclass 24, count 2 2006.286.05:16:52.08#ibcon#first serial, iclass 24, count 2 2006.286.05:16:52.08#ibcon#enter sib2, iclass 24, count 2 2006.286.05:16:52.08#ibcon#flushed, iclass 24, count 2 2006.286.05:16:52.08#ibcon#about to write, iclass 24, count 2 2006.286.05:16:52.08#ibcon#wrote, iclass 24, count 2 2006.286.05:16:52.08#ibcon#about to read 3, iclass 24, count 2 2006.286.05:16:52.10#ibcon#read 3, iclass 24, count 2 2006.286.05:16:52.10#ibcon#about to read 4, iclass 24, count 2 2006.286.05:16:52.10#ibcon#read 4, iclass 24, count 2 2006.286.05:16:52.10#ibcon#about to read 5, iclass 24, count 2 2006.286.05:16:52.10#ibcon#read 5, iclass 24, count 2 2006.286.05:16:52.10#ibcon#about to read 6, iclass 24, count 2 2006.286.05:16:52.10#ibcon#read 6, iclass 24, count 2 2006.286.05:16:52.10#ibcon#end of sib2, iclass 24, count 2 2006.286.05:16:52.10#ibcon#*mode == 0, iclass 24, count 2 2006.286.05:16:52.10#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.05:16:52.10#ibcon#[27=AT02-05\r\n] 2006.286.05:16:52.10#ibcon#*before write, iclass 24, count 2 2006.286.05:16:52.10#ibcon#enter sib2, iclass 24, count 2 2006.286.05:16:52.10#ibcon#flushed, iclass 24, count 2 2006.286.05:16:52.10#ibcon#about to write, iclass 24, count 2 2006.286.05:16:52.10#ibcon#wrote, iclass 24, count 2 2006.286.05:16:52.10#ibcon#about to read 3, iclass 24, count 2 2006.286.05:16:52.13#ibcon#read 3, iclass 24, count 2 2006.286.05:16:52.13#ibcon#about to read 4, iclass 24, count 2 2006.286.05:16:52.13#ibcon#read 4, iclass 24, count 2 2006.286.05:16:52.13#ibcon#about to read 5, iclass 24, count 2 2006.286.05:16:52.13#ibcon#read 5, iclass 24, count 2 2006.286.05:16:52.13#ibcon#about to read 6, iclass 24, count 2 2006.286.05:16:52.13#ibcon#read 6, iclass 24, count 2 2006.286.05:16:52.13#ibcon#end of sib2, iclass 24, count 2 2006.286.05:16:52.13#ibcon#*after write, iclass 24, count 2 2006.286.05:16:52.13#ibcon#*before return 0, iclass 24, count 2 2006.286.05:16:52.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:16:52.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:16:52.13#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.05:16:52.13#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:52.13#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:16:52.25#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:16:52.25#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:16:52.25#ibcon#enter wrdev, iclass 24, count 0 2006.286.05:16:52.25#ibcon#first serial, iclass 24, count 0 2006.286.05:16:52.25#ibcon#enter sib2, iclass 24, count 0 2006.286.05:16:52.25#ibcon#flushed, iclass 24, count 0 2006.286.05:16:52.25#ibcon#about to write, iclass 24, count 0 2006.286.05:16:52.25#ibcon#wrote, iclass 24, count 0 2006.286.05:16:52.25#ibcon#about to read 3, iclass 24, count 0 2006.286.05:16:52.27#ibcon#read 3, iclass 24, count 0 2006.286.05:16:52.27#ibcon#about to read 4, iclass 24, count 0 2006.286.05:16:52.27#ibcon#read 4, iclass 24, count 0 2006.286.05:16:52.27#ibcon#about to read 5, iclass 24, count 0 2006.286.05:16:52.27#ibcon#read 5, iclass 24, count 0 2006.286.05:16:52.27#ibcon#about to read 6, iclass 24, count 0 2006.286.05:16:52.27#ibcon#read 6, iclass 24, count 0 2006.286.05:16:52.27#ibcon#end of sib2, iclass 24, count 0 2006.286.05:16:52.27#ibcon#*mode == 0, iclass 24, count 0 2006.286.05:16:52.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.05:16:52.27#ibcon#[27=USB\r\n] 2006.286.05:16:52.27#ibcon#*before write, iclass 24, count 0 2006.286.05:16:52.27#ibcon#enter sib2, iclass 24, count 0 2006.286.05:16:52.27#ibcon#flushed, iclass 24, count 0 2006.286.05:16:52.27#ibcon#about to write, iclass 24, count 0 2006.286.05:16:52.27#ibcon#wrote, iclass 24, count 0 2006.286.05:16:52.27#ibcon#about to read 3, iclass 24, count 0 2006.286.05:16:52.30#ibcon#read 3, iclass 24, count 0 2006.286.05:16:52.30#ibcon#about to read 4, iclass 24, count 0 2006.286.05:16:52.30#ibcon#read 4, iclass 24, count 0 2006.286.05:16:52.30#ibcon#about to read 5, iclass 24, count 0 2006.286.05:16:52.30#ibcon#read 5, iclass 24, count 0 2006.286.05:16:52.30#ibcon#about to read 6, iclass 24, count 0 2006.286.05:16:52.30#ibcon#read 6, iclass 24, count 0 2006.286.05:16:52.30#ibcon#end of sib2, iclass 24, count 0 2006.286.05:16:52.30#ibcon#*after write, iclass 24, count 0 2006.286.05:16:52.30#ibcon#*before return 0, iclass 24, count 0 2006.286.05:16:52.30#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:16:52.30#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:16:52.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.05:16:52.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.05:16:52.30$vck44/vblo=3,649.99 2006.286.05:16:52.30#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.05:16:52.30#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.05:16:52.30#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:52.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:16:52.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:16:52.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:16:52.30#ibcon#enter wrdev, iclass 26, count 0 2006.286.05:16:52.30#ibcon#first serial, iclass 26, count 0 2006.286.05:16:52.30#ibcon#enter sib2, iclass 26, count 0 2006.286.05:16:52.30#ibcon#flushed, iclass 26, count 0 2006.286.05:16:52.30#ibcon#about to write, iclass 26, count 0 2006.286.05:16:52.30#ibcon#wrote, iclass 26, count 0 2006.286.05:16:52.30#ibcon#about to read 3, iclass 26, count 0 2006.286.05:16:52.32#ibcon#read 3, iclass 26, count 0 2006.286.05:16:52.32#ibcon#about to read 4, iclass 26, count 0 2006.286.05:16:52.32#ibcon#read 4, iclass 26, count 0 2006.286.05:16:52.32#ibcon#about to read 5, iclass 26, count 0 2006.286.05:16:52.32#ibcon#read 5, iclass 26, count 0 2006.286.05:16:52.32#ibcon#about to read 6, iclass 26, count 0 2006.286.05:16:52.32#ibcon#read 6, iclass 26, count 0 2006.286.05:16:52.32#ibcon#end of sib2, iclass 26, count 0 2006.286.05:16:52.32#ibcon#*mode == 0, iclass 26, count 0 2006.286.05:16:52.32#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.05:16:52.32#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.05:16:52.32#ibcon#*before write, iclass 26, count 0 2006.286.05:16:52.32#ibcon#enter sib2, iclass 26, count 0 2006.286.05:16:52.32#ibcon#flushed, iclass 26, count 0 2006.286.05:16:52.32#ibcon#about to write, iclass 26, count 0 2006.286.05:16:52.32#ibcon#wrote, iclass 26, count 0 2006.286.05:16:52.32#ibcon#about to read 3, iclass 26, count 0 2006.286.05:16:52.36#ibcon#read 3, iclass 26, count 0 2006.286.05:16:52.36#ibcon#about to read 4, iclass 26, count 0 2006.286.05:16:52.36#ibcon#read 4, iclass 26, count 0 2006.286.05:16:52.36#ibcon#about to read 5, iclass 26, count 0 2006.286.05:16:52.36#ibcon#read 5, iclass 26, count 0 2006.286.05:16:52.36#ibcon#about to read 6, iclass 26, count 0 2006.286.05:16:52.36#ibcon#read 6, iclass 26, count 0 2006.286.05:16:52.36#ibcon#end of sib2, iclass 26, count 0 2006.286.05:16:52.36#ibcon#*after write, iclass 26, count 0 2006.286.05:16:52.36#ibcon#*before return 0, iclass 26, count 0 2006.286.05:16:52.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:16:52.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:16:52.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.05:16:52.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.05:16:52.36$vck44/vb=3,4 2006.286.05:16:52.36#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.05:16:52.36#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.05:16:52.36#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:52.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:16:52.42#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:16:52.42#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:16:52.42#ibcon#enter wrdev, iclass 28, count 2 2006.286.05:16:52.42#ibcon#first serial, iclass 28, count 2 2006.286.05:16:52.42#ibcon#enter sib2, iclass 28, count 2 2006.286.05:16:52.42#ibcon#flushed, iclass 28, count 2 2006.286.05:16:52.42#ibcon#about to write, iclass 28, count 2 2006.286.05:16:52.42#ibcon#wrote, iclass 28, count 2 2006.286.05:16:52.42#ibcon#about to read 3, iclass 28, count 2 2006.286.05:16:52.44#ibcon#read 3, iclass 28, count 2 2006.286.05:16:52.44#ibcon#about to read 4, iclass 28, count 2 2006.286.05:16:52.44#ibcon#read 4, iclass 28, count 2 2006.286.05:16:52.44#ibcon#about to read 5, iclass 28, count 2 2006.286.05:16:52.44#ibcon#read 5, iclass 28, count 2 2006.286.05:16:52.44#ibcon#about to read 6, iclass 28, count 2 2006.286.05:16:52.44#ibcon#read 6, iclass 28, count 2 2006.286.05:16:52.44#ibcon#end of sib2, iclass 28, count 2 2006.286.05:16:52.44#ibcon#*mode == 0, iclass 28, count 2 2006.286.05:16:52.44#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.05:16:52.44#ibcon#[27=AT03-04\r\n] 2006.286.05:16:52.44#ibcon#*before write, iclass 28, count 2 2006.286.05:16:52.44#ibcon#enter sib2, iclass 28, count 2 2006.286.05:16:52.44#ibcon#flushed, iclass 28, count 2 2006.286.05:16:52.44#ibcon#about to write, iclass 28, count 2 2006.286.05:16:52.44#ibcon#wrote, iclass 28, count 2 2006.286.05:16:52.44#ibcon#about to read 3, iclass 28, count 2 2006.286.05:16:52.47#ibcon#read 3, iclass 28, count 2 2006.286.05:16:52.47#ibcon#about to read 4, iclass 28, count 2 2006.286.05:16:52.47#ibcon#read 4, iclass 28, count 2 2006.286.05:16:52.47#ibcon#about to read 5, iclass 28, count 2 2006.286.05:16:52.47#ibcon#read 5, iclass 28, count 2 2006.286.05:16:52.47#ibcon#about to read 6, iclass 28, count 2 2006.286.05:16:52.47#ibcon#read 6, iclass 28, count 2 2006.286.05:16:52.47#ibcon#end of sib2, iclass 28, count 2 2006.286.05:16:52.47#ibcon#*after write, iclass 28, count 2 2006.286.05:16:52.47#ibcon#*before return 0, iclass 28, count 2 2006.286.05:16:52.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:16:52.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:16:52.47#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.05:16:52.47#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:52.47#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:16:52.59#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:16:52.59#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:16:52.59#ibcon#enter wrdev, iclass 28, count 0 2006.286.05:16:52.59#ibcon#first serial, iclass 28, count 0 2006.286.05:16:52.59#ibcon#enter sib2, iclass 28, count 0 2006.286.05:16:52.59#ibcon#flushed, iclass 28, count 0 2006.286.05:16:52.59#ibcon#about to write, iclass 28, count 0 2006.286.05:16:52.59#ibcon#wrote, iclass 28, count 0 2006.286.05:16:52.59#ibcon#about to read 3, iclass 28, count 0 2006.286.05:16:52.61#ibcon#read 3, iclass 28, count 0 2006.286.05:16:52.61#ibcon#about to read 4, iclass 28, count 0 2006.286.05:16:52.61#ibcon#read 4, iclass 28, count 0 2006.286.05:16:52.61#ibcon#about to read 5, iclass 28, count 0 2006.286.05:16:52.61#ibcon#read 5, iclass 28, count 0 2006.286.05:16:52.61#ibcon#about to read 6, iclass 28, count 0 2006.286.05:16:52.61#ibcon#read 6, iclass 28, count 0 2006.286.05:16:52.61#ibcon#end of sib2, iclass 28, count 0 2006.286.05:16:52.61#ibcon#*mode == 0, iclass 28, count 0 2006.286.05:16:52.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.05:16:52.61#ibcon#[27=USB\r\n] 2006.286.05:16:52.61#ibcon#*before write, iclass 28, count 0 2006.286.05:16:52.61#ibcon#enter sib2, iclass 28, count 0 2006.286.05:16:52.61#ibcon#flushed, iclass 28, count 0 2006.286.05:16:52.61#ibcon#about to write, iclass 28, count 0 2006.286.05:16:52.61#ibcon#wrote, iclass 28, count 0 2006.286.05:16:52.61#ibcon#about to read 3, iclass 28, count 0 2006.286.05:16:52.64#ibcon#read 3, iclass 28, count 0 2006.286.05:16:52.64#ibcon#about to read 4, iclass 28, count 0 2006.286.05:16:52.64#ibcon#read 4, iclass 28, count 0 2006.286.05:16:52.64#ibcon#about to read 5, iclass 28, count 0 2006.286.05:16:52.64#ibcon#read 5, iclass 28, count 0 2006.286.05:16:52.64#ibcon#about to read 6, iclass 28, count 0 2006.286.05:16:52.64#ibcon#read 6, iclass 28, count 0 2006.286.05:16:52.64#ibcon#end of sib2, iclass 28, count 0 2006.286.05:16:52.64#ibcon#*after write, iclass 28, count 0 2006.286.05:16:52.64#ibcon#*before return 0, iclass 28, count 0 2006.286.05:16:52.64#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:16:52.64#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:16:52.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.05:16:52.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.05:16:52.64$vck44/vblo=4,679.99 2006.286.05:16:52.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.05:16:52.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.05:16:52.64#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:52.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:16:52.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:16:52.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:16:52.64#ibcon#enter wrdev, iclass 30, count 0 2006.286.05:16:52.64#ibcon#first serial, iclass 30, count 0 2006.286.05:16:52.64#ibcon#enter sib2, iclass 30, count 0 2006.286.05:16:52.64#ibcon#flushed, iclass 30, count 0 2006.286.05:16:52.64#ibcon#about to write, iclass 30, count 0 2006.286.05:16:52.64#ibcon#wrote, iclass 30, count 0 2006.286.05:16:52.64#ibcon#about to read 3, iclass 30, count 0 2006.286.05:16:52.66#ibcon#read 3, iclass 30, count 0 2006.286.05:16:52.76#ibcon#about to read 4, iclass 30, count 0 2006.286.05:16:52.76#ibcon#read 4, iclass 30, count 0 2006.286.05:16:52.76#ibcon#about to read 5, iclass 30, count 0 2006.286.05:16:52.76#ibcon#read 5, iclass 30, count 0 2006.286.05:16:52.76#ibcon#about to read 6, iclass 30, count 0 2006.286.05:16:52.76#ibcon#read 6, iclass 30, count 0 2006.286.05:16:52.76#ibcon#end of sib2, iclass 30, count 0 2006.286.05:16:52.76#ibcon#*mode == 0, iclass 30, count 0 2006.286.05:16:52.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.05:16:52.76#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.05:16:52.76#ibcon#*before write, iclass 30, count 0 2006.286.05:16:52.76#ibcon#enter sib2, iclass 30, count 0 2006.286.05:16:52.76#ibcon#flushed, iclass 30, count 0 2006.286.05:16:52.76#ibcon#about to write, iclass 30, count 0 2006.286.05:16:52.76#ibcon#wrote, iclass 30, count 0 2006.286.05:16:52.76#ibcon#about to read 3, iclass 30, count 0 2006.286.05:16:52.79#ibcon#read 3, iclass 30, count 0 2006.286.05:16:52.79#ibcon#about to read 4, iclass 30, count 0 2006.286.05:16:52.79#ibcon#read 4, iclass 30, count 0 2006.286.05:16:52.79#ibcon#about to read 5, iclass 30, count 0 2006.286.05:16:52.79#ibcon#read 5, iclass 30, count 0 2006.286.05:16:52.79#ibcon#about to read 6, iclass 30, count 0 2006.286.05:16:52.79#ibcon#read 6, iclass 30, count 0 2006.286.05:16:52.79#ibcon#end of sib2, iclass 30, count 0 2006.286.05:16:52.79#ibcon#*after write, iclass 30, count 0 2006.286.05:16:52.79#ibcon#*before return 0, iclass 30, count 0 2006.286.05:16:52.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:16:52.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:16:52.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.05:16:52.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.05:16:52.79$vck44/vb=4,5 2006.286.05:16:52.79#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.05:16:52.79#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.05:16:52.79#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:52.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:16:52.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:16:52.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:16:52.79#ibcon#enter wrdev, iclass 32, count 2 2006.286.05:16:52.79#ibcon#first serial, iclass 32, count 2 2006.286.05:16:52.79#ibcon#enter sib2, iclass 32, count 2 2006.286.05:16:52.79#ibcon#flushed, iclass 32, count 2 2006.286.05:16:52.79#ibcon#about to write, iclass 32, count 2 2006.286.05:16:52.79#ibcon#wrote, iclass 32, count 2 2006.286.05:16:52.79#ibcon#about to read 3, iclass 32, count 2 2006.286.05:16:52.81#ibcon#read 3, iclass 32, count 2 2006.286.05:16:52.81#ibcon#about to read 4, iclass 32, count 2 2006.286.05:16:52.81#ibcon#read 4, iclass 32, count 2 2006.286.05:16:52.81#ibcon#about to read 5, iclass 32, count 2 2006.286.05:16:52.81#ibcon#read 5, iclass 32, count 2 2006.286.05:16:52.81#ibcon#about to read 6, iclass 32, count 2 2006.286.05:16:52.81#ibcon#read 6, iclass 32, count 2 2006.286.05:16:52.81#ibcon#end of sib2, iclass 32, count 2 2006.286.05:16:52.81#ibcon#*mode == 0, iclass 32, count 2 2006.286.05:16:52.81#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.05:16:52.81#ibcon#[27=AT04-05\r\n] 2006.286.05:16:52.81#ibcon#*before write, iclass 32, count 2 2006.286.05:16:52.81#ibcon#enter sib2, iclass 32, count 2 2006.286.05:16:52.81#ibcon#flushed, iclass 32, count 2 2006.286.05:16:52.81#ibcon#about to write, iclass 32, count 2 2006.286.05:16:52.81#ibcon#wrote, iclass 32, count 2 2006.286.05:16:52.81#ibcon#about to read 3, iclass 32, count 2 2006.286.05:16:52.84#ibcon#read 3, iclass 32, count 2 2006.286.05:16:52.84#ibcon#about to read 4, iclass 32, count 2 2006.286.05:16:52.84#ibcon#read 4, iclass 32, count 2 2006.286.05:16:52.84#ibcon#about to read 5, iclass 32, count 2 2006.286.05:16:52.84#ibcon#read 5, iclass 32, count 2 2006.286.05:16:52.84#ibcon#about to read 6, iclass 32, count 2 2006.286.05:16:52.84#ibcon#read 6, iclass 32, count 2 2006.286.05:16:52.84#ibcon#end of sib2, iclass 32, count 2 2006.286.05:16:52.84#ibcon#*after write, iclass 32, count 2 2006.286.05:16:52.84#ibcon#*before return 0, iclass 32, count 2 2006.286.05:16:52.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:16:52.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:16:52.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.05:16:52.84#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:52.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:16:52.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:16:52.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:16:52.96#ibcon#enter wrdev, iclass 32, count 0 2006.286.05:16:52.96#ibcon#first serial, iclass 32, count 0 2006.286.05:16:52.96#ibcon#enter sib2, iclass 32, count 0 2006.286.05:16:52.96#ibcon#flushed, iclass 32, count 0 2006.286.05:16:52.96#ibcon#about to write, iclass 32, count 0 2006.286.05:16:52.96#ibcon#wrote, iclass 32, count 0 2006.286.05:16:52.96#ibcon#about to read 3, iclass 32, count 0 2006.286.05:16:52.98#ibcon#read 3, iclass 32, count 0 2006.286.05:16:52.98#ibcon#about to read 4, iclass 32, count 0 2006.286.05:16:52.98#ibcon#read 4, iclass 32, count 0 2006.286.05:16:52.98#ibcon#about to read 5, iclass 32, count 0 2006.286.05:16:52.98#ibcon#read 5, iclass 32, count 0 2006.286.05:16:52.98#ibcon#about to read 6, iclass 32, count 0 2006.286.05:16:52.98#ibcon#read 6, iclass 32, count 0 2006.286.05:16:52.98#ibcon#end of sib2, iclass 32, count 0 2006.286.05:16:52.98#ibcon#*mode == 0, iclass 32, count 0 2006.286.05:16:52.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.05:16:52.98#ibcon#[27=USB\r\n] 2006.286.05:16:52.98#ibcon#*before write, iclass 32, count 0 2006.286.05:16:52.98#ibcon#enter sib2, iclass 32, count 0 2006.286.05:16:52.98#ibcon#flushed, iclass 32, count 0 2006.286.05:16:52.98#ibcon#about to write, iclass 32, count 0 2006.286.05:16:52.98#ibcon#wrote, iclass 32, count 0 2006.286.05:16:52.98#ibcon#about to read 3, iclass 32, count 0 2006.286.05:16:53.01#ibcon#read 3, iclass 32, count 0 2006.286.05:16:53.01#ibcon#about to read 4, iclass 32, count 0 2006.286.05:16:53.01#ibcon#read 4, iclass 32, count 0 2006.286.05:16:53.01#ibcon#about to read 5, iclass 32, count 0 2006.286.05:16:53.01#ibcon#read 5, iclass 32, count 0 2006.286.05:16:53.01#ibcon#about to read 6, iclass 32, count 0 2006.286.05:16:53.01#ibcon#read 6, iclass 32, count 0 2006.286.05:16:53.01#ibcon#end of sib2, iclass 32, count 0 2006.286.05:16:53.01#ibcon#*after write, iclass 32, count 0 2006.286.05:16:53.01#ibcon#*before return 0, iclass 32, count 0 2006.286.05:16:53.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:16:53.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:16:53.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.05:16:53.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.05:16:53.01$vck44/vblo=5,709.99 2006.286.05:16:53.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.05:16:53.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.05:16:53.01#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:53.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:16:53.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:16:53.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:16:53.01#ibcon#enter wrdev, iclass 34, count 0 2006.286.05:16:53.01#ibcon#first serial, iclass 34, count 0 2006.286.05:16:53.01#ibcon#enter sib2, iclass 34, count 0 2006.286.05:16:53.01#ibcon#flushed, iclass 34, count 0 2006.286.05:16:53.01#ibcon#about to write, iclass 34, count 0 2006.286.05:16:53.01#ibcon#wrote, iclass 34, count 0 2006.286.05:16:53.01#ibcon#about to read 3, iclass 34, count 0 2006.286.05:16:53.03#ibcon#read 3, iclass 34, count 0 2006.286.05:16:53.03#ibcon#about to read 4, iclass 34, count 0 2006.286.05:16:53.03#ibcon#read 4, iclass 34, count 0 2006.286.05:16:53.03#ibcon#about to read 5, iclass 34, count 0 2006.286.05:16:53.03#ibcon#read 5, iclass 34, count 0 2006.286.05:16:53.03#ibcon#about to read 6, iclass 34, count 0 2006.286.05:16:53.03#ibcon#read 6, iclass 34, count 0 2006.286.05:16:53.03#ibcon#end of sib2, iclass 34, count 0 2006.286.05:16:53.03#ibcon#*mode == 0, iclass 34, count 0 2006.286.05:16:53.03#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.05:16:53.03#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.05:16:53.03#ibcon#*before write, iclass 34, count 0 2006.286.05:16:53.03#ibcon#enter sib2, iclass 34, count 0 2006.286.05:16:53.03#ibcon#flushed, iclass 34, count 0 2006.286.05:16:53.03#ibcon#about to write, iclass 34, count 0 2006.286.05:16:53.03#ibcon#wrote, iclass 34, count 0 2006.286.05:16:53.03#ibcon#about to read 3, iclass 34, count 0 2006.286.05:16:53.07#ibcon#read 3, iclass 34, count 0 2006.286.05:16:53.07#ibcon#about to read 4, iclass 34, count 0 2006.286.05:16:53.07#ibcon#read 4, iclass 34, count 0 2006.286.05:16:53.07#ibcon#about to read 5, iclass 34, count 0 2006.286.05:16:53.07#ibcon#read 5, iclass 34, count 0 2006.286.05:16:53.07#ibcon#about to read 6, iclass 34, count 0 2006.286.05:16:53.07#ibcon#read 6, iclass 34, count 0 2006.286.05:16:53.07#ibcon#end of sib2, iclass 34, count 0 2006.286.05:16:53.07#ibcon#*after write, iclass 34, count 0 2006.286.05:16:53.07#ibcon#*before return 0, iclass 34, count 0 2006.286.05:16:53.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:16:53.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:16:53.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.05:16:53.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.05:16:53.07$vck44/vb=5,4 2006.286.05:16:53.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.05:16:53.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.05:16:53.07#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:53.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:16:53.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:16:53.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:16:53.13#ibcon#enter wrdev, iclass 36, count 2 2006.286.05:16:53.13#ibcon#first serial, iclass 36, count 2 2006.286.05:16:53.13#ibcon#enter sib2, iclass 36, count 2 2006.286.05:16:53.13#ibcon#flushed, iclass 36, count 2 2006.286.05:16:53.13#ibcon#about to write, iclass 36, count 2 2006.286.05:16:53.13#ibcon#wrote, iclass 36, count 2 2006.286.05:16:53.13#ibcon#about to read 3, iclass 36, count 2 2006.286.05:16:53.15#ibcon#read 3, iclass 36, count 2 2006.286.05:16:53.15#ibcon#about to read 4, iclass 36, count 2 2006.286.05:16:53.15#ibcon#read 4, iclass 36, count 2 2006.286.05:16:53.15#ibcon#about to read 5, iclass 36, count 2 2006.286.05:16:53.15#ibcon#read 5, iclass 36, count 2 2006.286.05:16:53.15#ibcon#about to read 6, iclass 36, count 2 2006.286.05:16:53.15#ibcon#read 6, iclass 36, count 2 2006.286.05:16:53.15#ibcon#end of sib2, iclass 36, count 2 2006.286.05:16:53.15#ibcon#*mode == 0, iclass 36, count 2 2006.286.05:16:53.15#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.05:16:53.15#ibcon#[27=AT05-04\r\n] 2006.286.05:16:53.15#ibcon#*before write, iclass 36, count 2 2006.286.05:16:53.15#ibcon#enter sib2, iclass 36, count 2 2006.286.05:16:53.15#ibcon#flushed, iclass 36, count 2 2006.286.05:16:53.15#ibcon#about to write, iclass 36, count 2 2006.286.05:16:53.15#ibcon#wrote, iclass 36, count 2 2006.286.05:16:53.15#ibcon#about to read 3, iclass 36, count 2 2006.286.05:16:53.18#ibcon#read 3, iclass 36, count 2 2006.286.05:16:53.18#ibcon#about to read 4, iclass 36, count 2 2006.286.05:16:53.18#ibcon#read 4, iclass 36, count 2 2006.286.05:16:53.18#ibcon#about to read 5, iclass 36, count 2 2006.286.05:16:53.18#ibcon#read 5, iclass 36, count 2 2006.286.05:16:53.18#ibcon#about to read 6, iclass 36, count 2 2006.286.05:16:53.18#ibcon#read 6, iclass 36, count 2 2006.286.05:16:53.18#ibcon#end of sib2, iclass 36, count 2 2006.286.05:16:53.18#ibcon#*after write, iclass 36, count 2 2006.286.05:16:53.18#ibcon#*before return 0, iclass 36, count 2 2006.286.05:16:53.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:16:53.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:16:53.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.05:16:53.18#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:53.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:16:53.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:16:53.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:16:53.30#ibcon#enter wrdev, iclass 36, count 0 2006.286.05:16:53.30#ibcon#first serial, iclass 36, count 0 2006.286.05:16:53.30#ibcon#enter sib2, iclass 36, count 0 2006.286.05:16:53.30#ibcon#flushed, iclass 36, count 0 2006.286.05:16:53.30#ibcon#about to write, iclass 36, count 0 2006.286.05:16:53.30#ibcon#wrote, iclass 36, count 0 2006.286.05:16:53.30#ibcon#about to read 3, iclass 36, count 0 2006.286.05:16:53.32#ibcon#read 3, iclass 36, count 0 2006.286.05:16:53.32#ibcon#about to read 4, iclass 36, count 0 2006.286.05:16:53.32#ibcon#read 4, iclass 36, count 0 2006.286.05:16:53.32#ibcon#about to read 5, iclass 36, count 0 2006.286.05:16:53.32#ibcon#read 5, iclass 36, count 0 2006.286.05:16:53.32#ibcon#about to read 6, iclass 36, count 0 2006.286.05:16:53.32#ibcon#read 6, iclass 36, count 0 2006.286.05:16:53.32#ibcon#end of sib2, iclass 36, count 0 2006.286.05:16:53.32#ibcon#*mode == 0, iclass 36, count 0 2006.286.05:16:53.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.05:16:53.32#ibcon#[27=USB\r\n] 2006.286.05:16:53.32#ibcon#*before write, iclass 36, count 0 2006.286.05:16:53.32#ibcon#enter sib2, iclass 36, count 0 2006.286.05:16:53.32#ibcon#flushed, iclass 36, count 0 2006.286.05:16:53.32#ibcon#about to write, iclass 36, count 0 2006.286.05:16:53.32#ibcon#wrote, iclass 36, count 0 2006.286.05:16:53.32#ibcon#about to read 3, iclass 36, count 0 2006.286.05:16:53.35#ibcon#read 3, iclass 36, count 0 2006.286.05:16:53.35#ibcon#about to read 4, iclass 36, count 0 2006.286.05:16:53.35#ibcon#read 4, iclass 36, count 0 2006.286.05:16:53.35#ibcon#about to read 5, iclass 36, count 0 2006.286.05:16:53.35#ibcon#read 5, iclass 36, count 0 2006.286.05:16:53.35#ibcon#about to read 6, iclass 36, count 0 2006.286.05:16:53.35#ibcon#read 6, iclass 36, count 0 2006.286.05:16:53.35#ibcon#end of sib2, iclass 36, count 0 2006.286.05:16:53.35#ibcon#*after write, iclass 36, count 0 2006.286.05:16:53.35#ibcon#*before return 0, iclass 36, count 0 2006.286.05:16:53.35#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:16:53.35#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:16:53.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.05:16:53.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.05:16:53.35$vck44/vblo=6,719.99 2006.286.05:16:53.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.05:16:53.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.05:16:53.35#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:53.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:16:53.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:16:53.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:16:53.35#ibcon#enter wrdev, iclass 38, count 0 2006.286.05:16:53.35#ibcon#first serial, iclass 38, count 0 2006.286.05:16:53.35#ibcon#enter sib2, iclass 38, count 0 2006.286.05:16:53.35#ibcon#flushed, iclass 38, count 0 2006.286.05:16:53.35#ibcon#about to write, iclass 38, count 0 2006.286.05:16:53.35#ibcon#wrote, iclass 38, count 0 2006.286.05:16:53.35#ibcon#about to read 3, iclass 38, count 0 2006.286.05:16:53.37#ibcon#read 3, iclass 38, count 0 2006.286.05:16:53.37#ibcon#about to read 4, iclass 38, count 0 2006.286.05:16:53.37#ibcon#read 4, iclass 38, count 0 2006.286.05:16:53.37#ibcon#about to read 5, iclass 38, count 0 2006.286.05:16:53.37#ibcon#read 5, iclass 38, count 0 2006.286.05:16:53.37#ibcon#about to read 6, iclass 38, count 0 2006.286.05:16:53.37#ibcon#read 6, iclass 38, count 0 2006.286.05:16:53.37#ibcon#end of sib2, iclass 38, count 0 2006.286.05:16:53.37#ibcon#*mode == 0, iclass 38, count 0 2006.286.05:16:53.37#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.05:16:53.37#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.05:16:53.37#ibcon#*before write, iclass 38, count 0 2006.286.05:16:53.37#ibcon#enter sib2, iclass 38, count 0 2006.286.05:16:53.37#ibcon#flushed, iclass 38, count 0 2006.286.05:16:53.37#ibcon#about to write, iclass 38, count 0 2006.286.05:16:53.37#ibcon#wrote, iclass 38, count 0 2006.286.05:16:53.37#ibcon#about to read 3, iclass 38, count 0 2006.286.05:16:53.41#ibcon#read 3, iclass 38, count 0 2006.286.05:16:53.41#ibcon#about to read 4, iclass 38, count 0 2006.286.05:16:53.41#ibcon#read 4, iclass 38, count 0 2006.286.05:16:53.41#ibcon#about to read 5, iclass 38, count 0 2006.286.05:16:53.41#ibcon#read 5, iclass 38, count 0 2006.286.05:16:53.41#ibcon#about to read 6, iclass 38, count 0 2006.286.05:16:53.41#ibcon#read 6, iclass 38, count 0 2006.286.05:16:53.41#ibcon#end of sib2, iclass 38, count 0 2006.286.05:16:53.41#ibcon#*after write, iclass 38, count 0 2006.286.05:16:53.41#ibcon#*before return 0, iclass 38, count 0 2006.286.05:16:53.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:16:53.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:16:53.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.05:16:53.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.05:16:53.41$vck44/vb=6,3 2006.286.05:16:53.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.05:16:53.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.05:16:53.41#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:53.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:16:53.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:16:53.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:16:53.47#ibcon#enter wrdev, iclass 40, count 2 2006.286.05:16:53.47#ibcon#first serial, iclass 40, count 2 2006.286.05:16:53.47#ibcon#enter sib2, iclass 40, count 2 2006.286.05:16:53.47#ibcon#flushed, iclass 40, count 2 2006.286.05:16:53.47#ibcon#about to write, iclass 40, count 2 2006.286.05:16:53.47#ibcon#wrote, iclass 40, count 2 2006.286.05:16:53.47#ibcon#about to read 3, iclass 40, count 2 2006.286.05:16:53.49#ibcon#read 3, iclass 40, count 2 2006.286.05:16:53.49#ibcon#about to read 4, iclass 40, count 2 2006.286.05:16:53.49#ibcon#read 4, iclass 40, count 2 2006.286.05:16:53.49#ibcon#about to read 5, iclass 40, count 2 2006.286.05:16:53.49#ibcon#read 5, iclass 40, count 2 2006.286.05:16:53.49#ibcon#about to read 6, iclass 40, count 2 2006.286.05:16:53.49#ibcon#read 6, iclass 40, count 2 2006.286.05:16:53.49#ibcon#end of sib2, iclass 40, count 2 2006.286.05:16:53.49#ibcon#*mode == 0, iclass 40, count 2 2006.286.05:16:53.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.05:16:53.49#ibcon#[27=AT06-03\r\n] 2006.286.05:16:53.49#ibcon#*before write, iclass 40, count 2 2006.286.05:16:53.49#ibcon#enter sib2, iclass 40, count 2 2006.286.05:16:53.49#ibcon#flushed, iclass 40, count 2 2006.286.05:16:53.49#ibcon#about to write, iclass 40, count 2 2006.286.05:16:53.49#ibcon#wrote, iclass 40, count 2 2006.286.05:16:53.49#ibcon#about to read 3, iclass 40, count 2 2006.286.05:16:53.52#ibcon#read 3, iclass 40, count 2 2006.286.05:16:53.52#ibcon#about to read 4, iclass 40, count 2 2006.286.05:16:53.52#ibcon#read 4, iclass 40, count 2 2006.286.05:16:53.52#ibcon#about to read 5, iclass 40, count 2 2006.286.05:16:53.52#ibcon#read 5, iclass 40, count 2 2006.286.05:16:53.52#ibcon#about to read 6, iclass 40, count 2 2006.286.05:16:53.52#ibcon#read 6, iclass 40, count 2 2006.286.05:16:53.52#ibcon#end of sib2, iclass 40, count 2 2006.286.05:16:53.52#ibcon#*after write, iclass 40, count 2 2006.286.05:16:53.52#ibcon#*before return 0, iclass 40, count 2 2006.286.05:16:53.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:16:53.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:16:53.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.05:16:53.52#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:53.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:16:53.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:16:53.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:16:53.64#ibcon#enter wrdev, iclass 40, count 0 2006.286.05:16:53.64#ibcon#first serial, iclass 40, count 0 2006.286.05:16:53.64#ibcon#enter sib2, iclass 40, count 0 2006.286.05:16:53.64#ibcon#flushed, iclass 40, count 0 2006.286.05:16:53.64#ibcon#about to write, iclass 40, count 0 2006.286.05:16:53.64#ibcon#wrote, iclass 40, count 0 2006.286.05:16:53.64#ibcon#about to read 3, iclass 40, count 0 2006.286.05:16:53.66#ibcon#read 3, iclass 40, count 0 2006.286.05:16:53.66#ibcon#about to read 4, iclass 40, count 0 2006.286.05:16:53.66#ibcon#read 4, iclass 40, count 0 2006.286.05:16:53.66#ibcon#about to read 5, iclass 40, count 0 2006.286.05:16:53.66#ibcon#read 5, iclass 40, count 0 2006.286.05:16:53.66#ibcon#about to read 6, iclass 40, count 0 2006.286.05:16:53.66#ibcon#read 6, iclass 40, count 0 2006.286.05:16:53.66#ibcon#end of sib2, iclass 40, count 0 2006.286.05:16:53.66#ibcon#*mode == 0, iclass 40, count 0 2006.286.05:16:53.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.05:16:53.66#ibcon#[27=USB\r\n] 2006.286.05:16:53.66#ibcon#*before write, iclass 40, count 0 2006.286.05:16:53.66#ibcon#enter sib2, iclass 40, count 0 2006.286.05:16:53.66#ibcon#flushed, iclass 40, count 0 2006.286.05:16:53.66#ibcon#about to write, iclass 40, count 0 2006.286.05:16:53.66#ibcon#wrote, iclass 40, count 0 2006.286.05:16:53.66#ibcon#about to read 3, iclass 40, count 0 2006.286.05:16:53.69#ibcon#read 3, iclass 40, count 0 2006.286.05:16:53.69#ibcon#about to read 4, iclass 40, count 0 2006.286.05:16:53.69#ibcon#read 4, iclass 40, count 0 2006.286.05:16:53.69#ibcon#about to read 5, iclass 40, count 0 2006.286.05:16:53.69#ibcon#read 5, iclass 40, count 0 2006.286.05:16:53.69#ibcon#about to read 6, iclass 40, count 0 2006.286.05:16:53.69#ibcon#read 6, iclass 40, count 0 2006.286.05:16:53.69#ibcon#end of sib2, iclass 40, count 0 2006.286.05:16:53.69#ibcon#*after write, iclass 40, count 0 2006.286.05:16:53.69#ibcon#*before return 0, iclass 40, count 0 2006.286.05:16:53.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:16:53.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:16:53.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.05:16:53.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.05:16:53.69$vck44/vblo=7,734.99 2006.286.05:16:53.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.05:16:53.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.05:16:53.69#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:53.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:16:53.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:16:53.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:16:53.69#ibcon#enter wrdev, iclass 4, count 0 2006.286.05:16:53.69#ibcon#first serial, iclass 4, count 0 2006.286.05:16:53.69#ibcon#enter sib2, iclass 4, count 0 2006.286.05:16:53.69#ibcon#flushed, iclass 4, count 0 2006.286.05:16:53.69#ibcon#about to write, iclass 4, count 0 2006.286.05:16:53.69#ibcon#wrote, iclass 4, count 0 2006.286.05:16:53.69#ibcon#about to read 3, iclass 4, count 0 2006.286.05:16:53.71#ibcon#read 3, iclass 4, count 0 2006.286.05:16:53.75#ibcon#about to read 4, iclass 4, count 0 2006.286.05:16:53.75#ibcon#read 4, iclass 4, count 0 2006.286.05:16:53.75#ibcon#about to read 5, iclass 4, count 0 2006.286.05:16:53.75#ibcon#read 5, iclass 4, count 0 2006.286.05:16:53.75#ibcon#about to read 6, iclass 4, count 0 2006.286.05:16:53.75#ibcon#read 6, iclass 4, count 0 2006.286.05:16:53.75#ibcon#end of sib2, iclass 4, count 0 2006.286.05:16:53.75#ibcon#*mode == 0, iclass 4, count 0 2006.286.05:16:53.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.05:16:53.75#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.05:16:53.75#ibcon#*before write, iclass 4, count 0 2006.286.05:16:53.75#ibcon#enter sib2, iclass 4, count 0 2006.286.05:16:53.75#ibcon#flushed, iclass 4, count 0 2006.286.05:16:53.75#ibcon#about to write, iclass 4, count 0 2006.286.05:16:53.75#ibcon#wrote, iclass 4, count 0 2006.286.05:16:53.75#ibcon#about to read 3, iclass 4, count 0 2006.286.05:16:53.79#ibcon#read 3, iclass 4, count 0 2006.286.05:16:53.79#ibcon#about to read 4, iclass 4, count 0 2006.286.05:16:53.79#ibcon#read 4, iclass 4, count 0 2006.286.05:16:53.79#ibcon#about to read 5, iclass 4, count 0 2006.286.05:16:53.79#ibcon#read 5, iclass 4, count 0 2006.286.05:16:53.79#ibcon#about to read 6, iclass 4, count 0 2006.286.05:16:53.79#ibcon#read 6, iclass 4, count 0 2006.286.05:16:53.79#ibcon#end of sib2, iclass 4, count 0 2006.286.05:16:53.79#ibcon#*after write, iclass 4, count 0 2006.286.05:16:53.79#ibcon#*before return 0, iclass 4, count 0 2006.286.05:16:53.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:16:53.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:16:53.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.05:16:53.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.05:16:53.79$vck44/vb=7,4 2006.286.05:16:53.79#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.05:16:53.79#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.05:16:53.79#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:53.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:16:53.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:16:53.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:16:53.81#ibcon#enter wrdev, iclass 6, count 2 2006.286.05:16:53.81#ibcon#first serial, iclass 6, count 2 2006.286.05:16:53.81#ibcon#enter sib2, iclass 6, count 2 2006.286.05:16:53.81#ibcon#flushed, iclass 6, count 2 2006.286.05:16:53.81#ibcon#about to write, iclass 6, count 2 2006.286.05:16:53.81#ibcon#wrote, iclass 6, count 2 2006.286.05:16:53.81#ibcon#about to read 3, iclass 6, count 2 2006.286.05:16:53.83#ibcon#read 3, iclass 6, count 2 2006.286.05:16:53.83#ibcon#about to read 4, iclass 6, count 2 2006.286.05:16:53.83#ibcon#read 4, iclass 6, count 2 2006.286.05:16:53.83#ibcon#about to read 5, iclass 6, count 2 2006.286.05:16:53.83#ibcon#read 5, iclass 6, count 2 2006.286.05:16:53.83#ibcon#about to read 6, iclass 6, count 2 2006.286.05:16:53.83#ibcon#read 6, iclass 6, count 2 2006.286.05:16:53.83#ibcon#end of sib2, iclass 6, count 2 2006.286.05:16:53.83#ibcon#*mode == 0, iclass 6, count 2 2006.286.05:16:53.83#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.05:16:53.83#ibcon#[27=AT07-04\r\n] 2006.286.05:16:53.83#ibcon#*before write, iclass 6, count 2 2006.286.05:16:53.83#ibcon#enter sib2, iclass 6, count 2 2006.286.05:16:53.83#ibcon#flushed, iclass 6, count 2 2006.286.05:16:53.83#ibcon#about to write, iclass 6, count 2 2006.286.05:16:53.83#ibcon#wrote, iclass 6, count 2 2006.286.05:16:53.83#ibcon#about to read 3, iclass 6, count 2 2006.286.05:16:53.86#ibcon#read 3, iclass 6, count 2 2006.286.05:16:53.86#ibcon#about to read 4, iclass 6, count 2 2006.286.05:16:53.86#ibcon#read 4, iclass 6, count 2 2006.286.05:16:53.86#ibcon#about to read 5, iclass 6, count 2 2006.286.05:16:53.86#ibcon#read 5, iclass 6, count 2 2006.286.05:16:53.86#ibcon#about to read 6, iclass 6, count 2 2006.286.05:16:53.86#ibcon#read 6, iclass 6, count 2 2006.286.05:16:53.86#ibcon#end of sib2, iclass 6, count 2 2006.286.05:16:53.86#ibcon#*after write, iclass 6, count 2 2006.286.05:16:53.86#ibcon#*before return 0, iclass 6, count 2 2006.286.05:16:53.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:16:53.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:16:53.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.05:16:53.86#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:53.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:16:53.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:16:53.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:16:53.98#ibcon#enter wrdev, iclass 6, count 0 2006.286.05:16:53.98#ibcon#first serial, iclass 6, count 0 2006.286.05:16:53.98#ibcon#enter sib2, iclass 6, count 0 2006.286.05:16:53.98#ibcon#flushed, iclass 6, count 0 2006.286.05:16:53.98#ibcon#about to write, iclass 6, count 0 2006.286.05:16:53.98#ibcon#wrote, iclass 6, count 0 2006.286.05:16:53.98#ibcon#about to read 3, iclass 6, count 0 2006.286.05:16:54.00#ibcon#read 3, iclass 6, count 0 2006.286.05:16:54.00#ibcon#about to read 4, iclass 6, count 0 2006.286.05:16:54.00#ibcon#read 4, iclass 6, count 0 2006.286.05:16:54.00#ibcon#about to read 5, iclass 6, count 0 2006.286.05:16:54.00#ibcon#read 5, iclass 6, count 0 2006.286.05:16:54.00#ibcon#about to read 6, iclass 6, count 0 2006.286.05:16:54.00#ibcon#read 6, iclass 6, count 0 2006.286.05:16:54.00#ibcon#end of sib2, iclass 6, count 0 2006.286.05:16:54.00#ibcon#*mode == 0, iclass 6, count 0 2006.286.05:16:54.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.05:16:54.00#ibcon#[27=USB\r\n] 2006.286.05:16:54.00#ibcon#*before write, iclass 6, count 0 2006.286.05:16:54.00#ibcon#enter sib2, iclass 6, count 0 2006.286.05:16:54.00#ibcon#flushed, iclass 6, count 0 2006.286.05:16:54.00#ibcon#about to write, iclass 6, count 0 2006.286.05:16:54.00#ibcon#wrote, iclass 6, count 0 2006.286.05:16:54.00#ibcon#about to read 3, iclass 6, count 0 2006.286.05:16:54.03#ibcon#read 3, iclass 6, count 0 2006.286.05:16:54.03#ibcon#about to read 4, iclass 6, count 0 2006.286.05:16:54.03#ibcon#read 4, iclass 6, count 0 2006.286.05:16:54.03#ibcon#about to read 5, iclass 6, count 0 2006.286.05:16:54.03#ibcon#read 5, iclass 6, count 0 2006.286.05:16:54.03#ibcon#about to read 6, iclass 6, count 0 2006.286.05:16:54.03#ibcon#read 6, iclass 6, count 0 2006.286.05:16:54.03#ibcon#end of sib2, iclass 6, count 0 2006.286.05:16:54.03#ibcon#*after write, iclass 6, count 0 2006.286.05:16:54.03#ibcon#*before return 0, iclass 6, count 0 2006.286.05:16:54.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:16:54.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:16:54.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.05:16:54.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.05:16:54.03$vck44/vblo=8,744.99 2006.286.05:16:54.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.05:16:54.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.05:16:54.03#ibcon#ireg 17 cls_cnt 0 2006.286.05:16:54.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:16:54.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:16:54.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:16:54.03#ibcon#enter wrdev, iclass 10, count 0 2006.286.05:16:54.03#ibcon#first serial, iclass 10, count 0 2006.286.05:16:54.03#ibcon#enter sib2, iclass 10, count 0 2006.286.05:16:54.03#ibcon#flushed, iclass 10, count 0 2006.286.05:16:54.03#ibcon#about to write, iclass 10, count 0 2006.286.05:16:54.03#ibcon#wrote, iclass 10, count 0 2006.286.05:16:54.03#ibcon#about to read 3, iclass 10, count 0 2006.286.05:16:54.05#ibcon#read 3, iclass 10, count 0 2006.286.05:16:54.05#ibcon#about to read 4, iclass 10, count 0 2006.286.05:16:54.05#ibcon#read 4, iclass 10, count 0 2006.286.05:16:54.05#ibcon#about to read 5, iclass 10, count 0 2006.286.05:16:54.05#ibcon#read 5, iclass 10, count 0 2006.286.05:16:54.05#ibcon#about to read 6, iclass 10, count 0 2006.286.05:16:54.05#ibcon#read 6, iclass 10, count 0 2006.286.05:16:54.05#ibcon#end of sib2, iclass 10, count 0 2006.286.05:16:54.05#ibcon#*mode == 0, iclass 10, count 0 2006.286.05:16:54.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.05:16:54.05#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.05:16:54.05#ibcon#*before write, iclass 10, count 0 2006.286.05:16:54.05#ibcon#enter sib2, iclass 10, count 0 2006.286.05:16:54.05#ibcon#flushed, iclass 10, count 0 2006.286.05:16:54.05#ibcon#about to write, iclass 10, count 0 2006.286.05:16:54.05#ibcon#wrote, iclass 10, count 0 2006.286.05:16:54.05#ibcon#about to read 3, iclass 10, count 0 2006.286.05:16:54.09#ibcon#read 3, iclass 10, count 0 2006.286.05:16:54.09#ibcon#about to read 4, iclass 10, count 0 2006.286.05:16:54.09#ibcon#read 4, iclass 10, count 0 2006.286.05:16:54.09#ibcon#about to read 5, iclass 10, count 0 2006.286.05:16:54.09#ibcon#read 5, iclass 10, count 0 2006.286.05:16:54.09#ibcon#about to read 6, iclass 10, count 0 2006.286.05:16:54.09#ibcon#read 6, iclass 10, count 0 2006.286.05:16:54.09#ibcon#end of sib2, iclass 10, count 0 2006.286.05:16:54.09#ibcon#*after write, iclass 10, count 0 2006.286.05:16:54.09#ibcon#*before return 0, iclass 10, count 0 2006.286.05:16:54.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:16:54.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:16:54.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.05:16:54.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.05:16:54.09$vck44/vb=8,4 2006.286.05:16:54.09#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.05:16:54.09#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.05:16:54.09#ibcon#ireg 11 cls_cnt 2 2006.286.05:16:54.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:16:54.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:16:54.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:16:54.15#ibcon#enter wrdev, iclass 12, count 2 2006.286.05:16:54.15#ibcon#first serial, iclass 12, count 2 2006.286.05:16:54.15#ibcon#enter sib2, iclass 12, count 2 2006.286.05:16:54.15#ibcon#flushed, iclass 12, count 2 2006.286.05:16:54.15#ibcon#about to write, iclass 12, count 2 2006.286.05:16:54.15#ibcon#wrote, iclass 12, count 2 2006.286.05:16:54.15#ibcon#about to read 3, iclass 12, count 2 2006.286.05:16:54.17#ibcon#read 3, iclass 12, count 2 2006.286.05:16:54.17#ibcon#about to read 4, iclass 12, count 2 2006.286.05:16:54.17#ibcon#read 4, iclass 12, count 2 2006.286.05:16:54.17#ibcon#about to read 5, iclass 12, count 2 2006.286.05:16:54.17#ibcon#read 5, iclass 12, count 2 2006.286.05:16:54.17#ibcon#about to read 6, iclass 12, count 2 2006.286.05:16:54.17#ibcon#read 6, iclass 12, count 2 2006.286.05:16:54.17#ibcon#end of sib2, iclass 12, count 2 2006.286.05:16:54.17#ibcon#*mode == 0, iclass 12, count 2 2006.286.05:16:54.17#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.05:16:54.17#ibcon#[27=AT08-04\r\n] 2006.286.05:16:54.17#ibcon#*before write, iclass 12, count 2 2006.286.05:16:54.17#ibcon#enter sib2, iclass 12, count 2 2006.286.05:16:54.17#ibcon#flushed, iclass 12, count 2 2006.286.05:16:54.17#ibcon#about to write, iclass 12, count 2 2006.286.05:16:54.17#ibcon#wrote, iclass 12, count 2 2006.286.05:16:54.17#ibcon#about to read 3, iclass 12, count 2 2006.286.05:16:54.20#ibcon#read 3, iclass 12, count 2 2006.286.05:16:54.20#ibcon#about to read 4, iclass 12, count 2 2006.286.05:16:54.20#ibcon#read 4, iclass 12, count 2 2006.286.05:16:54.20#ibcon#about to read 5, iclass 12, count 2 2006.286.05:16:54.20#ibcon#read 5, iclass 12, count 2 2006.286.05:16:54.20#ibcon#about to read 6, iclass 12, count 2 2006.286.05:16:54.20#ibcon#read 6, iclass 12, count 2 2006.286.05:16:54.20#ibcon#end of sib2, iclass 12, count 2 2006.286.05:16:54.20#ibcon#*after write, iclass 12, count 2 2006.286.05:16:54.20#ibcon#*before return 0, iclass 12, count 2 2006.286.05:16:54.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:16:54.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:16:54.20#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.05:16:54.20#ibcon#ireg 7 cls_cnt 0 2006.286.05:16:54.20#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:16:54.32#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:16:54.32#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:16:54.32#ibcon#enter wrdev, iclass 12, count 0 2006.286.05:16:54.32#ibcon#first serial, iclass 12, count 0 2006.286.05:16:54.32#ibcon#enter sib2, iclass 12, count 0 2006.286.05:16:54.32#ibcon#flushed, iclass 12, count 0 2006.286.05:16:54.32#ibcon#about to write, iclass 12, count 0 2006.286.05:16:54.32#ibcon#wrote, iclass 12, count 0 2006.286.05:16:54.32#ibcon#about to read 3, iclass 12, count 0 2006.286.05:16:54.34#ibcon#read 3, iclass 12, count 0 2006.286.05:16:54.34#ibcon#about to read 4, iclass 12, count 0 2006.286.05:16:54.34#ibcon#read 4, iclass 12, count 0 2006.286.05:16:54.34#ibcon#about to read 5, iclass 12, count 0 2006.286.05:16:54.34#ibcon#read 5, iclass 12, count 0 2006.286.05:16:54.34#ibcon#about to read 6, iclass 12, count 0 2006.286.05:16:54.34#ibcon#read 6, iclass 12, count 0 2006.286.05:16:54.34#ibcon#end of sib2, iclass 12, count 0 2006.286.05:16:54.34#ibcon#*mode == 0, iclass 12, count 0 2006.286.05:16:54.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.05:16:54.34#ibcon#[27=USB\r\n] 2006.286.05:16:54.34#ibcon#*before write, iclass 12, count 0 2006.286.05:16:54.34#ibcon#enter sib2, iclass 12, count 0 2006.286.05:16:54.34#ibcon#flushed, iclass 12, count 0 2006.286.05:16:54.34#ibcon#about to write, iclass 12, count 0 2006.286.05:16:54.34#ibcon#wrote, iclass 12, count 0 2006.286.05:16:54.34#ibcon#about to read 3, iclass 12, count 0 2006.286.05:16:54.37#ibcon#read 3, iclass 12, count 0 2006.286.05:16:54.37#ibcon#about to read 4, iclass 12, count 0 2006.286.05:16:54.37#ibcon#read 4, iclass 12, count 0 2006.286.05:16:54.37#ibcon#about to read 5, iclass 12, count 0 2006.286.05:16:54.37#ibcon#read 5, iclass 12, count 0 2006.286.05:16:54.37#ibcon#about to read 6, iclass 12, count 0 2006.286.05:16:54.37#ibcon#read 6, iclass 12, count 0 2006.286.05:16:54.37#ibcon#end of sib2, iclass 12, count 0 2006.286.05:16:54.37#ibcon#*after write, iclass 12, count 0 2006.286.05:16:54.37#ibcon#*before return 0, iclass 12, count 0 2006.286.05:16:54.37#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:16:54.37#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:16:54.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.05:16:54.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.05:16:54.37$vck44/vabw=wide 2006.286.05:16:54.37#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.05:16:54.37#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.05:16:54.37#ibcon#ireg 8 cls_cnt 0 2006.286.05:16:54.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:16:54.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:16:54.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:16:54.37#ibcon#enter wrdev, iclass 14, count 0 2006.286.05:16:54.37#ibcon#first serial, iclass 14, count 0 2006.286.05:16:54.37#ibcon#enter sib2, iclass 14, count 0 2006.286.05:16:54.37#ibcon#flushed, iclass 14, count 0 2006.286.05:16:54.37#ibcon#about to write, iclass 14, count 0 2006.286.05:16:54.37#ibcon#wrote, iclass 14, count 0 2006.286.05:16:54.37#ibcon#about to read 3, iclass 14, count 0 2006.286.05:16:54.39#ibcon#read 3, iclass 14, count 0 2006.286.05:16:54.39#ibcon#about to read 4, iclass 14, count 0 2006.286.05:16:54.39#ibcon#read 4, iclass 14, count 0 2006.286.05:16:54.39#ibcon#about to read 5, iclass 14, count 0 2006.286.05:16:54.39#ibcon#read 5, iclass 14, count 0 2006.286.05:16:54.39#ibcon#about to read 6, iclass 14, count 0 2006.286.05:16:54.39#ibcon#read 6, iclass 14, count 0 2006.286.05:16:54.39#ibcon#end of sib2, iclass 14, count 0 2006.286.05:16:54.39#ibcon#*mode == 0, iclass 14, count 0 2006.286.05:16:54.39#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.05:16:54.39#ibcon#[25=BW32\r\n] 2006.286.05:16:54.39#ibcon#*before write, iclass 14, count 0 2006.286.05:16:54.39#ibcon#enter sib2, iclass 14, count 0 2006.286.05:16:54.39#ibcon#flushed, iclass 14, count 0 2006.286.05:16:54.39#ibcon#about to write, iclass 14, count 0 2006.286.05:16:54.39#ibcon#wrote, iclass 14, count 0 2006.286.05:16:54.39#ibcon#about to read 3, iclass 14, count 0 2006.286.05:16:54.42#ibcon#read 3, iclass 14, count 0 2006.286.05:16:54.42#ibcon#about to read 4, iclass 14, count 0 2006.286.05:16:54.42#ibcon#read 4, iclass 14, count 0 2006.286.05:16:54.42#ibcon#about to read 5, iclass 14, count 0 2006.286.05:16:54.42#ibcon#read 5, iclass 14, count 0 2006.286.05:16:54.42#ibcon#about to read 6, iclass 14, count 0 2006.286.05:16:54.42#ibcon#read 6, iclass 14, count 0 2006.286.05:16:54.42#ibcon#end of sib2, iclass 14, count 0 2006.286.05:16:54.42#ibcon#*after write, iclass 14, count 0 2006.286.05:16:54.42#ibcon#*before return 0, iclass 14, count 0 2006.286.05:16:54.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:16:54.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:16:54.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.05:16:54.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.05:16:54.42$vck44/vbbw=wide 2006.286.05:16:54.42#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.05:16:54.42#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.05:16:54.42#ibcon#ireg 8 cls_cnt 0 2006.286.05:16:54.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:16:54.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:16:54.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:16:54.49#ibcon#enter wrdev, iclass 16, count 0 2006.286.05:16:54.49#ibcon#first serial, iclass 16, count 0 2006.286.05:16:54.49#ibcon#enter sib2, iclass 16, count 0 2006.286.05:16:54.49#ibcon#flushed, iclass 16, count 0 2006.286.05:16:54.49#ibcon#about to write, iclass 16, count 0 2006.286.05:16:54.49#ibcon#wrote, iclass 16, count 0 2006.286.05:16:54.49#ibcon#about to read 3, iclass 16, count 0 2006.286.05:16:54.51#ibcon#read 3, iclass 16, count 0 2006.286.05:16:54.51#ibcon#about to read 4, iclass 16, count 0 2006.286.05:16:54.51#ibcon#read 4, iclass 16, count 0 2006.286.05:16:54.51#ibcon#about to read 5, iclass 16, count 0 2006.286.05:16:54.51#ibcon#read 5, iclass 16, count 0 2006.286.05:16:54.51#ibcon#about to read 6, iclass 16, count 0 2006.286.05:16:54.51#ibcon#read 6, iclass 16, count 0 2006.286.05:16:54.51#ibcon#end of sib2, iclass 16, count 0 2006.286.05:16:54.51#ibcon#*mode == 0, iclass 16, count 0 2006.286.05:16:54.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.05:16:54.51#ibcon#[27=BW32\r\n] 2006.286.05:16:54.51#ibcon#*before write, iclass 16, count 0 2006.286.05:16:54.51#ibcon#enter sib2, iclass 16, count 0 2006.286.05:16:54.51#ibcon#flushed, iclass 16, count 0 2006.286.05:16:54.51#ibcon#about to write, iclass 16, count 0 2006.286.05:16:54.51#ibcon#wrote, iclass 16, count 0 2006.286.05:16:54.51#ibcon#about to read 3, iclass 16, count 0 2006.286.05:16:54.54#ibcon#read 3, iclass 16, count 0 2006.286.05:16:54.54#ibcon#about to read 4, iclass 16, count 0 2006.286.05:16:54.54#ibcon#read 4, iclass 16, count 0 2006.286.05:16:54.54#ibcon#about to read 5, iclass 16, count 0 2006.286.05:16:54.54#ibcon#read 5, iclass 16, count 0 2006.286.05:16:54.54#ibcon#about to read 6, iclass 16, count 0 2006.286.05:16:54.54#ibcon#read 6, iclass 16, count 0 2006.286.05:16:54.54#ibcon#end of sib2, iclass 16, count 0 2006.286.05:16:54.54#ibcon#*after write, iclass 16, count 0 2006.286.05:16:54.54#ibcon#*before return 0, iclass 16, count 0 2006.286.05:16:54.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:16:54.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:16:54.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.05:16:54.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.05:16:54.54$setupk4/ifdk4 2006.286.05:16:54.54$ifdk4/lo= 2006.286.05:16:54.54$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.05:16:54.54$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.05:16:54.54$ifdk4/patch= 2006.286.05:16:54.54$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.05:16:54.54$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.05:16:54.54$setupk4/!*+20s 2006.286.05:16:59.91#abcon#<5=/04 3.6 8.2 21.62 771015.0\r\n> 2006.286.05:16:59.93#abcon#{5=INTERFACE CLEAR} 2006.286.05:16:59.99#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:17:07.97$setupk4/"tpicd 2006.286.05:17:07.97$setupk4/echo=off 2006.286.05:17:07.97$setupk4/xlog=off 2006.286.05:17:07.97:!2006.286.05:20:32 2006.286.05:17:18.14#trakl#Source acquired 2006.286.05:17:19.14#flagr#flagr/antenna,acquired 2006.286.05:20:18.14#trakl#Off source 2006.286.05:20:18.14?ERROR st -7 Antenna off-source! 2006.286.05:20:18.14#trakl#az 175.119 el 28.240 azerr*cos(el) 0.0171 elerr -0.0035 2006.286.05:20:19.14#flagr#flagr/antenna,off-source 2006.286.05:20:24.14#trakl#Source re-acquired 2006.286.05:20:25.14#flagr#flagr/antenna,re-acquired 2006.286.05:20:32.00:preob 2006.286.05:20:32.14/onsource/TRACKING 2006.286.05:20:32.14:!2006.286.05:20:42 2006.286.05:20:42.00:"tape 2006.286.05:20:42.00:"st=record 2006.286.05:20:42.00:data_valid=on 2006.286.05:20:42.00:midob 2006.286.05:20:43.14/onsource/TRACKING 2006.286.05:20:43.14/wx/21.52,1015.0,78 2006.286.05:20:43.27/cable/+6.4937E-03 2006.286.05:20:44.36/va/01,07,usb,yes,33,36 2006.286.05:20:44.36/va/02,06,usb,yes,33,33 2006.286.05:20:44.36/va/03,07,usb,yes,32,34 2006.286.05:20:44.36/va/04,06,usb,yes,34,35 2006.286.05:20:44.36/va/05,03,usb,yes,33,34 2006.286.05:20:44.36/va/06,04,usb,yes,30,30 2006.286.05:20:44.36/va/07,04,usb,yes,31,31 2006.286.05:20:44.36/va/08,03,usb,yes,31,38 2006.286.05:20:44.59/valo/01,524.99,yes,locked 2006.286.05:20:44.59/valo/02,534.99,yes,locked 2006.286.05:20:44.59/valo/03,564.99,yes,locked 2006.286.05:20:44.59/valo/04,624.99,yes,locked 2006.286.05:20:44.59/valo/05,734.99,yes,locked 2006.286.05:20:44.59/valo/06,814.99,yes,locked 2006.286.05:20:44.59/valo/07,864.99,yes,locked 2006.286.05:20:44.59/valo/08,884.99,yes,locked 2006.286.05:20:45.68/vb/01,04,usb,yes,31,29 2006.286.05:20:45.68/vb/02,05,usb,yes,29,29 2006.286.05:20:45.68/vb/03,04,usb,yes,30,33 2006.286.05:20:45.68/vb/04,05,usb,yes,30,29 2006.286.05:20:45.68/vb/05,04,usb,yes,27,29 2006.286.05:20:45.68/vb/06,03,usb,yes,38,34 2006.286.05:20:45.68/vb/07,04,usb,yes,31,31 2006.286.05:20:45.68/vb/08,04,usb,yes,28,32 2006.286.05:20:45.91/vblo/01,629.99,yes,locked 2006.286.05:20:45.91/vblo/02,634.99,yes,locked 2006.286.05:20:45.91/vblo/03,649.99,yes,locked 2006.286.05:20:45.91/vblo/04,679.99,yes,locked 2006.286.05:20:45.91/vblo/05,709.99,yes,locked 2006.286.05:20:45.91/vblo/06,719.99,yes,locked 2006.286.05:20:45.91/vblo/07,734.99,yes,locked 2006.286.05:20:45.91/vblo/08,744.99,yes,locked 2006.286.05:20:46.06/vabw/8 2006.286.05:20:46.21/vbbw/8 2006.286.05:20:46.30/xfe/off,on,12.2 2006.286.05:20:46.67/ifatt/23,28,28,28 2006.286.05:20:47.07/fmout-gps/S +2.41E-07 2006.286.05:20:47.09:!2006.286.05:25:22 2006.286.05:21:11.14#trakl#Off source 2006.286.05:21:11.14?ERROR st -7 Antenna off-source! 2006.286.05:21:11.14#trakl#az 175.345 el 28.255 azerr*cos(el) 0.0186 elerr -0.0043 2006.286.05:21:11.14#flagr#flagr/antenna,off-source 2006.286.05:21:17.14#trakl#Source re-acquired 2006.286.05:21:17.14#flagr#flagr/antenna,re-acquired 2006.286.05:21:39.14#trakl#Off source 2006.286.05:21:39.14?ERROR st -7 Antenna off-source! 2006.286.05:21:39.14#trakl#az 175.465 el 28.263 azerr*cos(el) 0.0180 elerr -0.0018 2006.286.05:21:41.14#flagr#flagr/antenna,off-source 2006.286.05:21:45.14#trakl#Source re-acquired 2006.286.05:21:47.14#flagr#flagr/antenna,re-acquired 2006.286.05:25:16.14#trakl#Off source 2006.286.05:25:16.14?ERROR st -7 Antenna off-source! 2006.286.05:25:16.14#trakl#az 176.392 el 28.315 azerr*cos(el) 0.0174 elerr -0.0007 2006.286.05:25:17.14#flagr#flagr/antenna,off-source 2006.286.05:25:22.01:data_valid=off 2006.286.05:25:22.01:"et 2006.286.05:25:22.01:!+3s 2006.286.05:25:22.14#trakl#Source re-acquired 2006.286.05:25:23.14#flagr#flagr/antenna,re-acquired 2006.286.05:25:25.02:"tape 2006.286.05:25:25.02:postob 2006.286.05:25:25.14/cable/+6.4922E-03 2006.286.05:25:25.14/wx/21.36,1015.1,79 2006.286.05:25:25.20/fmout-gps/S +2.39E-07 2006.286.05:25:25.20:scan_name=286-0528,jd0610,40 2006.286.05:25:25.20:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.286.05:25:27.14#flagr#flagr/antenna,new-source 2006.286.05:25:27.14:checkk5 2006.286.05:25:27.51/chk_autoobs//k5ts1/ autoobs is running! 2006.286.05:25:28.16/chk_autoobs//k5ts2/ autoobs is running! 2006.286.05:25:28.70/chk_autoobs//k5ts3/ autoobs is running! 2006.286.05:25:29.08/chk_autoobs//k5ts4/ autoobs is running! 2006.286.05:25:29.45/chk_obsdata//k5ts1/T2860520??a.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.286.05:25:29.96/chk_obsdata//k5ts2/T2860520??b.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.286.05:25:30.35/chk_obsdata//k5ts3/T2860520??c.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.286.05:25:30.79/chk_obsdata//k5ts4/T2860520??d.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.286.05:25:31.76/k5log//k5ts1_log_newline 2006.286.05:25:32.67/k5log//k5ts2_log_newline 2006.286.05:25:33.41/k5log//k5ts3_log_newline 2006.286.05:25:34.23/k5log//k5ts4_log_newline 2006.286.05:25:34.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.05:25:34.26:setupk4=1 2006.286.05:25:34.26$setupk4/echo=on 2006.286.05:25:34.26$setupk4/pcalon 2006.286.05:25:34.26$pcalon/"no phase cal control is implemented here 2006.286.05:25:34.26$setupk4/"tpicd=stop 2006.286.05:25:34.26$setupk4/"rec=synch_on 2006.286.05:25:34.26$setupk4/"rec_mode=128 2006.286.05:25:34.26$setupk4/!* 2006.286.05:25:34.26$setupk4/recpk4 2006.286.05:25:34.26$recpk4/recpatch= 2006.286.05:25:34.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.05:25:34.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.05:25:34.26$setupk4/vck44 2006.286.05:25:34.26$vck44/valo=1,524.99 2006.286.05:25:34.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.05:25:34.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.05:25:34.26#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:34.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.05:25:34.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.05:25:34.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.05:25:34.26#ibcon#enter wrdev, iclass 12, count 0 2006.286.05:25:34.26#ibcon#first serial, iclass 12, count 0 2006.286.05:25:34.26#ibcon#enter sib2, iclass 12, count 0 2006.286.05:25:34.26#ibcon#flushed, iclass 12, count 0 2006.286.05:25:34.26#ibcon#about to write, iclass 12, count 0 2006.286.05:25:34.26#ibcon#wrote, iclass 12, count 0 2006.286.05:25:34.26#ibcon#about to read 3, iclass 12, count 0 2006.286.05:25:34.28#ibcon#read 3, iclass 12, count 0 2006.286.05:25:34.28#ibcon#about to read 4, iclass 12, count 0 2006.286.05:25:34.28#ibcon#read 4, iclass 12, count 0 2006.286.05:25:34.28#ibcon#about to read 5, iclass 12, count 0 2006.286.05:25:34.28#ibcon#read 5, iclass 12, count 0 2006.286.05:25:34.28#ibcon#about to read 6, iclass 12, count 0 2006.286.05:25:34.28#ibcon#read 6, iclass 12, count 0 2006.286.05:25:34.28#ibcon#end of sib2, iclass 12, count 0 2006.286.05:25:34.28#ibcon#*mode == 0, iclass 12, count 0 2006.286.05:25:34.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.05:25:34.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.05:25:34.28#ibcon#*before write, iclass 12, count 0 2006.286.05:25:34.28#ibcon#enter sib2, iclass 12, count 0 2006.286.05:25:34.28#ibcon#flushed, iclass 12, count 0 2006.286.05:25:34.28#ibcon#about to write, iclass 12, count 0 2006.286.05:25:34.28#ibcon#wrote, iclass 12, count 0 2006.286.05:25:34.28#ibcon#about to read 3, iclass 12, count 0 2006.286.05:25:34.33#ibcon#read 3, iclass 12, count 0 2006.286.05:25:34.33#ibcon#about to read 4, iclass 12, count 0 2006.286.05:25:34.33#ibcon#read 4, iclass 12, count 0 2006.286.05:25:34.33#ibcon#about to read 5, iclass 12, count 0 2006.286.05:25:34.33#ibcon#read 5, iclass 12, count 0 2006.286.05:25:34.33#ibcon#about to read 6, iclass 12, count 0 2006.286.05:25:34.33#ibcon#read 6, iclass 12, count 0 2006.286.05:25:34.33#ibcon#end of sib2, iclass 12, count 0 2006.286.05:25:34.33#ibcon#*after write, iclass 12, count 0 2006.286.05:25:34.33#ibcon#*before return 0, iclass 12, count 0 2006.286.05:25:34.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.05:25:34.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.05:25:34.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.05:25:34.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.05:25:34.33$vck44/va=1,7 2006.286.05:25:34.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.05:25:34.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.05:25:34.33#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:34.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.05:25:34.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.05:25:34.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.05:25:34.33#ibcon#enter wrdev, iclass 14, count 2 2006.286.05:25:34.33#ibcon#first serial, iclass 14, count 2 2006.286.05:25:34.33#ibcon#enter sib2, iclass 14, count 2 2006.286.05:25:34.33#ibcon#flushed, iclass 14, count 2 2006.286.05:25:34.33#ibcon#about to write, iclass 14, count 2 2006.286.05:25:34.33#ibcon#wrote, iclass 14, count 2 2006.286.05:25:34.33#ibcon#about to read 3, iclass 14, count 2 2006.286.05:25:34.35#ibcon#read 3, iclass 14, count 2 2006.286.05:25:34.35#ibcon#about to read 4, iclass 14, count 2 2006.286.05:25:34.35#ibcon#read 4, iclass 14, count 2 2006.286.05:25:34.35#ibcon#about to read 5, iclass 14, count 2 2006.286.05:25:34.35#ibcon#read 5, iclass 14, count 2 2006.286.05:25:34.35#ibcon#about to read 6, iclass 14, count 2 2006.286.05:25:34.35#ibcon#read 6, iclass 14, count 2 2006.286.05:25:34.35#ibcon#end of sib2, iclass 14, count 2 2006.286.05:25:34.35#ibcon#*mode == 0, iclass 14, count 2 2006.286.05:25:34.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.05:25:34.35#ibcon#[25=AT01-07\r\n] 2006.286.05:25:34.35#ibcon#*before write, iclass 14, count 2 2006.286.05:25:34.35#ibcon#enter sib2, iclass 14, count 2 2006.286.05:25:34.35#ibcon#flushed, iclass 14, count 2 2006.286.05:25:34.35#ibcon#about to write, iclass 14, count 2 2006.286.05:25:34.35#ibcon#wrote, iclass 14, count 2 2006.286.05:25:34.35#ibcon#about to read 3, iclass 14, count 2 2006.286.05:25:34.38#ibcon#read 3, iclass 14, count 2 2006.286.05:25:34.38#ibcon#about to read 4, iclass 14, count 2 2006.286.05:25:34.38#ibcon#read 4, iclass 14, count 2 2006.286.05:25:34.38#ibcon#about to read 5, iclass 14, count 2 2006.286.05:25:34.38#ibcon#read 5, iclass 14, count 2 2006.286.05:25:34.38#ibcon#about to read 6, iclass 14, count 2 2006.286.05:25:34.38#ibcon#read 6, iclass 14, count 2 2006.286.05:25:34.38#ibcon#end of sib2, iclass 14, count 2 2006.286.05:25:34.38#ibcon#*after write, iclass 14, count 2 2006.286.05:25:34.38#ibcon#*before return 0, iclass 14, count 2 2006.286.05:25:34.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.05:25:34.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.05:25:34.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.05:25:34.38#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:34.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.05:25:34.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.05:25:34.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.05:25:34.50#ibcon#enter wrdev, iclass 14, count 0 2006.286.05:25:34.50#ibcon#first serial, iclass 14, count 0 2006.286.05:25:34.50#ibcon#enter sib2, iclass 14, count 0 2006.286.05:25:34.50#ibcon#flushed, iclass 14, count 0 2006.286.05:25:34.50#ibcon#about to write, iclass 14, count 0 2006.286.05:25:34.50#ibcon#wrote, iclass 14, count 0 2006.286.05:25:34.50#ibcon#about to read 3, iclass 14, count 0 2006.286.05:25:34.52#ibcon#read 3, iclass 14, count 0 2006.286.05:25:34.52#ibcon#about to read 4, iclass 14, count 0 2006.286.05:25:34.52#ibcon#read 4, iclass 14, count 0 2006.286.05:25:34.52#ibcon#about to read 5, iclass 14, count 0 2006.286.05:25:34.52#ibcon#read 5, iclass 14, count 0 2006.286.05:25:34.52#ibcon#about to read 6, iclass 14, count 0 2006.286.05:25:34.52#ibcon#read 6, iclass 14, count 0 2006.286.05:25:34.52#ibcon#end of sib2, iclass 14, count 0 2006.286.05:25:34.52#ibcon#*mode == 0, iclass 14, count 0 2006.286.05:25:34.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.05:25:34.52#ibcon#[25=USB\r\n] 2006.286.05:25:34.52#ibcon#*before write, iclass 14, count 0 2006.286.05:25:34.52#ibcon#enter sib2, iclass 14, count 0 2006.286.05:25:34.52#ibcon#flushed, iclass 14, count 0 2006.286.05:25:34.52#ibcon#about to write, iclass 14, count 0 2006.286.05:25:34.52#ibcon#wrote, iclass 14, count 0 2006.286.05:25:34.52#ibcon#about to read 3, iclass 14, count 0 2006.286.05:25:34.55#ibcon#read 3, iclass 14, count 0 2006.286.05:25:34.55#ibcon#about to read 4, iclass 14, count 0 2006.286.05:25:34.55#ibcon#read 4, iclass 14, count 0 2006.286.05:25:34.55#ibcon#about to read 5, iclass 14, count 0 2006.286.05:25:34.55#ibcon#read 5, iclass 14, count 0 2006.286.05:25:34.55#ibcon#about to read 6, iclass 14, count 0 2006.286.05:25:34.55#ibcon#read 6, iclass 14, count 0 2006.286.05:25:34.55#ibcon#end of sib2, iclass 14, count 0 2006.286.05:25:34.55#ibcon#*after write, iclass 14, count 0 2006.286.05:25:34.55#ibcon#*before return 0, iclass 14, count 0 2006.286.05:25:34.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.05:25:34.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.05:25:34.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.05:25:34.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.05:25:34.55$vck44/valo=2,534.99 2006.286.05:25:34.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.05:25:34.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.05:25:34.55#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:34.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:25:34.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:25:34.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:25:34.55#ibcon#enter wrdev, iclass 16, count 0 2006.286.05:25:34.55#ibcon#first serial, iclass 16, count 0 2006.286.05:25:34.55#ibcon#enter sib2, iclass 16, count 0 2006.286.05:25:34.55#ibcon#flushed, iclass 16, count 0 2006.286.05:25:34.55#ibcon#about to write, iclass 16, count 0 2006.286.05:25:34.55#ibcon#wrote, iclass 16, count 0 2006.286.05:25:34.55#ibcon#about to read 3, iclass 16, count 0 2006.286.05:25:34.57#ibcon#read 3, iclass 16, count 0 2006.286.05:25:34.57#ibcon#about to read 4, iclass 16, count 0 2006.286.05:25:34.57#ibcon#read 4, iclass 16, count 0 2006.286.05:25:34.57#ibcon#about to read 5, iclass 16, count 0 2006.286.05:25:34.57#ibcon#read 5, iclass 16, count 0 2006.286.05:25:34.57#ibcon#about to read 6, iclass 16, count 0 2006.286.05:25:34.57#ibcon#read 6, iclass 16, count 0 2006.286.05:25:34.57#ibcon#end of sib2, iclass 16, count 0 2006.286.05:25:34.57#ibcon#*mode == 0, iclass 16, count 0 2006.286.05:25:34.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.05:25:34.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.05:25:34.57#ibcon#*before write, iclass 16, count 0 2006.286.05:25:34.57#ibcon#enter sib2, iclass 16, count 0 2006.286.05:25:34.57#ibcon#flushed, iclass 16, count 0 2006.286.05:25:34.57#ibcon#about to write, iclass 16, count 0 2006.286.05:25:34.57#ibcon#wrote, iclass 16, count 0 2006.286.05:25:34.57#ibcon#about to read 3, iclass 16, count 0 2006.286.05:25:34.61#ibcon#read 3, iclass 16, count 0 2006.286.05:25:34.61#ibcon#about to read 4, iclass 16, count 0 2006.286.05:25:34.61#ibcon#read 4, iclass 16, count 0 2006.286.05:25:34.61#ibcon#about to read 5, iclass 16, count 0 2006.286.05:25:34.61#ibcon#read 5, iclass 16, count 0 2006.286.05:25:34.61#ibcon#about to read 6, iclass 16, count 0 2006.286.05:25:34.61#ibcon#read 6, iclass 16, count 0 2006.286.05:25:34.61#ibcon#end of sib2, iclass 16, count 0 2006.286.05:25:34.61#ibcon#*after write, iclass 16, count 0 2006.286.05:25:34.61#ibcon#*before return 0, iclass 16, count 0 2006.286.05:25:34.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:25:34.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:25:34.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.05:25:34.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.05:25:34.61$vck44/va=2,6 2006.286.05:25:34.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.05:25:34.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.05:25:34.61#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:34.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.05:25:34.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.05:25:34.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.05:25:34.67#ibcon#enter wrdev, iclass 18, count 2 2006.286.05:25:34.67#ibcon#first serial, iclass 18, count 2 2006.286.05:25:34.67#ibcon#enter sib2, iclass 18, count 2 2006.286.05:25:34.67#ibcon#flushed, iclass 18, count 2 2006.286.05:25:34.67#ibcon#about to write, iclass 18, count 2 2006.286.05:25:34.67#ibcon#wrote, iclass 18, count 2 2006.286.05:25:34.67#ibcon#about to read 3, iclass 18, count 2 2006.286.05:25:34.69#ibcon#read 3, iclass 18, count 2 2006.286.05:25:34.69#ibcon#about to read 4, iclass 18, count 2 2006.286.05:25:34.69#ibcon#read 4, iclass 18, count 2 2006.286.05:25:34.69#ibcon#about to read 5, iclass 18, count 2 2006.286.05:25:34.69#ibcon#read 5, iclass 18, count 2 2006.286.05:25:34.69#ibcon#about to read 6, iclass 18, count 2 2006.286.05:25:34.69#ibcon#read 6, iclass 18, count 2 2006.286.05:25:34.69#ibcon#end of sib2, iclass 18, count 2 2006.286.05:25:34.69#ibcon#*mode == 0, iclass 18, count 2 2006.286.05:25:34.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.05:25:34.69#ibcon#[25=AT02-06\r\n] 2006.286.05:25:34.69#ibcon#*before write, iclass 18, count 2 2006.286.05:25:34.69#ibcon#enter sib2, iclass 18, count 2 2006.286.05:25:34.69#ibcon#flushed, iclass 18, count 2 2006.286.05:25:34.69#ibcon#about to write, iclass 18, count 2 2006.286.05:25:34.69#ibcon#wrote, iclass 18, count 2 2006.286.05:25:34.69#ibcon#about to read 3, iclass 18, count 2 2006.286.05:25:34.72#ibcon#read 3, iclass 18, count 2 2006.286.05:25:34.72#ibcon#about to read 4, iclass 18, count 2 2006.286.05:25:34.72#ibcon#read 4, iclass 18, count 2 2006.286.05:25:34.72#ibcon#about to read 5, iclass 18, count 2 2006.286.05:25:34.72#ibcon#read 5, iclass 18, count 2 2006.286.05:25:34.72#ibcon#about to read 6, iclass 18, count 2 2006.286.05:25:34.72#ibcon#read 6, iclass 18, count 2 2006.286.05:25:34.72#ibcon#end of sib2, iclass 18, count 2 2006.286.05:25:34.72#ibcon#*after write, iclass 18, count 2 2006.286.05:25:34.72#ibcon#*before return 0, iclass 18, count 2 2006.286.05:25:34.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.05:25:34.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.05:25:34.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.05:25:34.72#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:34.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.05:25:34.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.05:25:34.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.05:25:34.84#ibcon#enter wrdev, iclass 18, count 0 2006.286.05:25:34.84#ibcon#first serial, iclass 18, count 0 2006.286.05:25:34.84#ibcon#enter sib2, iclass 18, count 0 2006.286.05:25:34.84#ibcon#flushed, iclass 18, count 0 2006.286.05:25:34.84#ibcon#about to write, iclass 18, count 0 2006.286.05:25:34.84#ibcon#wrote, iclass 18, count 0 2006.286.05:25:34.84#ibcon#about to read 3, iclass 18, count 0 2006.286.05:25:34.86#ibcon#read 3, iclass 18, count 0 2006.286.05:25:34.86#ibcon#about to read 4, iclass 18, count 0 2006.286.05:25:34.86#ibcon#read 4, iclass 18, count 0 2006.286.05:25:34.86#ibcon#about to read 5, iclass 18, count 0 2006.286.05:25:34.86#ibcon#read 5, iclass 18, count 0 2006.286.05:25:34.86#ibcon#about to read 6, iclass 18, count 0 2006.286.05:25:34.86#ibcon#read 6, iclass 18, count 0 2006.286.05:25:34.86#ibcon#end of sib2, iclass 18, count 0 2006.286.05:25:34.86#ibcon#*mode == 0, iclass 18, count 0 2006.286.05:25:34.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.05:25:34.86#ibcon#[25=USB\r\n] 2006.286.05:25:34.86#ibcon#*before write, iclass 18, count 0 2006.286.05:25:34.86#ibcon#enter sib2, iclass 18, count 0 2006.286.05:25:34.86#ibcon#flushed, iclass 18, count 0 2006.286.05:25:34.86#ibcon#about to write, iclass 18, count 0 2006.286.05:25:34.86#ibcon#wrote, iclass 18, count 0 2006.286.05:25:34.86#ibcon#about to read 3, iclass 18, count 0 2006.286.05:25:34.89#ibcon#read 3, iclass 18, count 0 2006.286.05:25:35.26#ibcon#about to read 4, iclass 18, count 0 2006.286.05:25:35.26#ibcon#read 4, iclass 18, count 0 2006.286.05:25:35.26#ibcon#about to read 5, iclass 18, count 0 2006.286.05:25:35.26#ibcon#read 5, iclass 18, count 0 2006.286.05:25:35.26#ibcon#about to read 6, iclass 18, count 0 2006.286.05:25:35.26#ibcon#read 6, iclass 18, count 0 2006.286.05:25:35.26#ibcon#end of sib2, iclass 18, count 0 2006.286.05:25:35.26#ibcon#*after write, iclass 18, count 0 2006.286.05:25:35.26#ibcon#*before return 0, iclass 18, count 0 2006.286.05:25:35.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.05:25:35.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.05:25:35.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.05:25:35.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.05:25:35.27$vck44/valo=3,564.99 2006.286.05:25:35.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.05:25:35.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.05:25:35.27#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:35.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:25:35.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:25:35.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:25:35.27#ibcon#enter wrdev, iclass 20, count 0 2006.286.05:25:35.27#ibcon#first serial, iclass 20, count 0 2006.286.05:25:35.27#ibcon#enter sib2, iclass 20, count 0 2006.286.05:25:35.27#ibcon#flushed, iclass 20, count 0 2006.286.05:25:35.27#ibcon#about to write, iclass 20, count 0 2006.286.05:25:35.27#ibcon#wrote, iclass 20, count 0 2006.286.05:25:35.27#ibcon#about to read 3, iclass 20, count 0 2006.286.05:25:35.28#ibcon#read 3, iclass 20, count 0 2006.286.05:25:35.28#ibcon#about to read 4, iclass 20, count 0 2006.286.05:25:35.28#ibcon#read 4, iclass 20, count 0 2006.286.05:25:35.28#ibcon#about to read 5, iclass 20, count 0 2006.286.05:25:35.28#ibcon#read 5, iclass 20, count 0 2006.286.05:25:35.28#ibcon#about to read 6, iclass 20, count 0 2006.286.05:25:35.28#ibcon#read 6, iclass 20, count 0 2006.286.05:25:35.28#ibcon#end of sib2, iclass 20, count 0 2006.286.05:25:35.28#ibcon#*mode == 0, iclass 20, count 0 2006.286.05:25:35.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.05:25:35.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.05:25:35.28#ibcon#*before write, iclass 20, count 0 2006.286.05:25:35.28#ibcon#enter sib2, iclass 20, count 0 2006.286.05:25:35.28#ibcon#flushed, iclass 20, count 0 2006.286.05:25:35.28#ibcon#about to write, iclass 20, count 0 2006.286.05:25:35.28#ibcon#wrote, iclass 20, count 0 2006.286.05:25:35.28#ibcon#about to read 3, iclass 20, count 0 2006.286.05:25:35.32#ibcon#read 3, iclass 20, count 0 2006.286.05:25:35.32#ibcon#about to read 4, iclass 20, count 0 2006.286.05:25:35.32#ibcon#read 4, iclass 20, count 0 2006.286.05:25:35.32#ibcon#about to read 5, iclass 20, count 0 2006.286.05:25:35.32#ibcon#read 5, iclass 20, count 0 2006.286.05:25:35.32#ibcon#about to read 6, iclass 20, count 0 2006.286.05:25:35.32#ibcon#read 6, iclass 20, count 0 2006.286.05:25:35.32#ibcon#end of sib2, iclass 20, count 0 2006.286.05:25:35.32#ibcon#*after write, iclass 20, count 0 2006.286.05:25:35.32#ibcon#*before return 0, iclass 20, count 0 2006.286.05:25:35.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:25:35.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:25:35.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.05:25:35.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.05:25:35.32$vck44/va=3,7 2006.286.05:25:35.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.05:25:35.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.05:25:35.32#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:35.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.05:25:35.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.05:25:35.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.05:25:35.38#ibcon#enter wrdev, iclass 22, count 2 2006.286.05:25:35.38#ibcon#first serial, iclass 22, count 2 2006.286.05:25:35.38#ibcon#enter sib2, iclass 22, count 2 2006.286.05:25:35.38#ibcon#flushed, iclass 22, count 2 2006.286.05:25:35.38#ibcon#about to write, iclass 22, count 2 2006.286.05:25:35.38#ibcon#wrote, iclass 22, count 2 2006.286.05:25:35.38#ibcon#about to read 3, iclass 22, count 2 2006.286.05:25:35.40#ibcon#read 3, iclass 22, count 2 2006.286.05:25:35.40#ibcon#about to read 4, iclass 22, count 2 2006.286.05:25:35.40#ibcon#read 4, iclass 22, count 2 2006.286.05:25:35.40#ibcon#about to read 5, iclass 22, count 2 2006.286.05:25:35.40#ibcon#read 5, iclass 22, count 2 2006.286.05:25:35.40#ibcon#about to read 6, iclass 22, count 2 2006.286.05:25:35.40#ibcon#read 6, iclass 22, count 2 2006.286.05:25:35.40#ibcon#end of sib2, iclass 22, count 2 2006.286.05:25:35.40#ibcon#*mode == 0, iclass 22, count 2 2006.286.05:25:35.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.05:25:35.40#ibcon#[25=AT03-07\r\n] 2006.286.05:25:35.40#ibcon#*before write, iclass 22, count 2 2006.286.05:25:35.40#ibcon#enter sib2, iclass 22, count 2 2006.286.05:25:35.40#ibcon#flushed, iclass 22, count 2 2006.286.05:25:35.40#ibcon#about to write, iclass 22, count 2 2006.286.05:25:35.40#ibcon#wrote, iclass 22, count 2 2006.286.05:25:35.40#ibcon#about to read 3, iclass 22, count 2 2006.286.05:25:35.43#ibcon#read 3, iclass 22, count 2 2006.286.05:25:35.43#ibcon#about to read 4, iclass 22, count 2 2006.286.05:25:35.43#ibcon#read 4, iclass 22, count 2 2006.286.05:25:35.43#ibcon#about to read 5, iclass 22, count 2 2006.286.05:25:35.43#ibcon#read 5, iclass 22, count 2 2006.286.05:25:35.43#ibcon#about to read 6, iclass 22, count 2 2006.286.05:25:35.43#ibcon#read 6, iclass 22, count 2 2006.286.05:25:35.43#ibcon#end of sib2, iclass 22, count 2 2006.286.05:25:35.43#ibcon#*after write, iclass 22, count 2 2006.286.05:25:35.43#ibcon#*before return 0, iclass 22, count 2 2006.286.05:25:35.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.05:25:35.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.05:25:35.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.05:25:35.43#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:35.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.05:25:35.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.05:25:35.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.05:25:35.55#ibcon#enter wrdev, iclass 22, count 0 2006.286.05:25:35.55#ibcon#first serial, iclass 22, count 0 2006.286.05:25:35.55#ibcon#enter sib2, iclass 22, count 0 2006.286.05:25:35.55#ibcon#flushed, iclass 22, count 0 2006.286.05:25:35.55#ibcon#about to write, iclass 22, count 0 2006.286.05:25:35.55#ibcon#wrote, iclass 22, count 0 2006.286.05:25:35.55#ibcon#about to read 3, iclass 22, count 0 2006.286.05:25:35.57#ibcon#read 3, iclass 22, count 0 2006.286.05:25:35.57#ibcon#about to read 4, iclass 22, count 0 2006.286.05:25:35.57#ibcon#read 4, iclass 22, count 0 2006.286.05:25:35.57#ibcon#about to read 5, iclass 22, count 0 2006.286.05:25:35.57#ibcon#read 5, iclass 22, count 0 2006.286.05:25:35.57#ibcon#about to read 6, iclass 22, count 0 2006.286.05:25:35.57#ibcon#read 6, iclass 22, count 0 2006.286.05:25:35.57#ibcon#end of sib2, iclass 22, count 0 2006.286.05:25:35.57#ibcon#*mode == 0, iclass 22, count 0 2006.286.05:25:35.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.05:25:35.57#ibcon#[25=USB\r\n] 2006.286.05:25:35.57#ibcon#*before write, iclass 22, count 0 2006.286.05:25:35.57#ibcon#enter sib2, iclass 22, count 0 2006.286.05:25:35.57#ibcon#flushed, iclass 22, count 0 2006.286.05:25:35.57#ibcon#about to write, iclass 22, count 0 2006.286.05:25:35.57#ibcon#wrote, iclass 22, count 0 2006.286.05:25:35.57#ibcon#about to read 3, iclass 22, count 0 2006.286.05:25:35.60#ibcon#read 3, iclass 22, count 0 2006.286.05:25:35.60#ibcon#about to read 4, iclass 22, count 0 2006.286.05:25:35.60#ibcon#read 4, iclass 22, count 0 2006.286.05:25:35.60#ibcon#about to read 5, iclass 22, count 0 2006.286.05:25:35.60#ibcon#read 5, iclass 22, count 0 2006.286.05:25:35.60#ibcon#about to read 6, iclass 22, count 0 2006.286.05:25:35.60#ibcon#read 6, iclass 22, count 0 2006.286.05:25:35.60#ibcon#end of sib2, iclass 22, count 0 2006.286.05:25:35.60#ibcon#*after write, iclass 22, count 0 2006.286.05:25:35.60#ibcon#*before return 0, iclass 22, count 0 2006.286.05:25:35.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.05:25:35.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.05:25:35.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.05:25:35.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.05:25:35.60$vck44/valo=4,624.99 2006.286.05:25:35.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.05:25:35.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.05:25:35.60#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:35.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.05:25:35.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.05:25:35.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.05:25:35.60#ibcon#enter wrdev, iclass 24, count 0 2006.286.05:25:35.60#ibcon#first serial, iclass 24, count 0 2006.286.05:25:35.60#ibcon#enter sib2, iclass 24, count 0 2006.286.05:25:35.60#ibcon#flushed, iclass 24, count 0 2006.286.05:25:35.60#ibcon#about to write, iclass 24, count 0 2006.286.05:25:35.60#ibcon#wrote, iclass 24, count 0 2006.286.05:25:35.60#ibcon#about to read 3, iclass 24, count 0 2006.286.05:25:35.62#ibcon#read 3, iclass 24, count 0 2006.286.05:25:35.87#ibcon#about to read 4, iclass 24, count 0 2006.286.05:25:35.87#ibcon#read 4, iclass 24, count 0 2006.286.05:25:35.87#ibcon#about to read 5, iclass 24, count 0 2006.286.05:25:35.87#ibcon#read 5, iclass 24, count 0 2006.286.05:25:35.87#ibcon#about to read 6, iclass 24, count 0 2006.286.05:25:35.87#ibcon#read 6, iclass 24, count 0 2006.286.05:25:35.87#ibcon#end of sib2, iclass 24, count 0 2006.286.05:25:35.87#ibcon#*mode == 0, iclass 24, count 0 2006.286.05:25:35.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.05:25:35.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.05:25:35.87#ibcon#*before write, iclass 24, count 0 2006.286.05:25:35.87#ibcon#enter sib2, iclass 24, count 0 2006.286.05:25:35.87#ibcon#flushed, iclass 24, count 0 2006.286.05:25:35.87#ibcon#about to write, iclass 24, count 0 2006.286.05:25:35.87#ibcon#wrote, iclass 24, count 0 2006.286.05:25:35.87#ibcon#about to read 3, iclass 24, count 0 2006.286.05:25:35.91#ibcon#read 3, iclass 24, count 0 2006.286.05:25:35.91#ibcon#about to read 4, iclass 24, count 0 2006.286.05:25:35.91#ibcon#read 4, iclass 24, count 0 2006.286.05:25:35.91#ibcon#about to read 5, iclass 24, count 0 2006.286.05:25:35.91#ibcon#read 5, iclass 24, count 0 2006.286.05:25:35.91#ibcon#about to read 6, iclass 24, count 0 2006.286.05:25:35.91#ibcon#read 6, iclass 24, count 0 2006.286.05:25:35.91#ibcon#end of sib2, iclass 24, count 0 2006.286.05:25:35.91#ibcon#*after write, iclass 24, count 0 2006.286.05:25:35.91#ibcon#*before return 0, iclass 24, count 0 2006.286.05:25:35.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.05:25:35.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.05:25:35.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.05:25:35.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.05:25:35.91$vck44/va=4,6 2006.286.05:25:35.91#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.05:25:35.91#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.05:25:35.91#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:35.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.05:25:35.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.05:25:35.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.05:25:35.91#ibcon#enter wrdev, iclass 26, count 2 2006.286.05:25:35.91#ibcon#first serial, iclass 26, count 2 2006.286.05:25:35.91#ibcon#enter sib2, iclass 26, count 2 2006.286.05:25:35.91#ibcon#flushed, iclass 26, count 2 2006.286.05:25:35.91#ibcon#about to write, iclass 26, count 2 2006.286.05:25:35.91#ibcon#wrote, iclass 26, count 2 2006.286.05:25:35.91#ibcon#about to read 3, iclass 26, count 2 2006.286.05:25:35.93#ibcon#read 3, iclass 26, count 2 2006.286.05:25:35.93#ibcon#about to read 4, iclass 26, count 2 2006.286.05:25:35.93#ibcon#read 4, iclass 26, count 2 2006.286.05:25:35.93#ibcon#about to read 5, iclass 26, count 2 2006.286.05:25:35.93#ibcon#read 5, iclass 26, count 2 2006.286.05:25:35.93#ibcon#about to read 6, iclass 26, count 2 2006.286.05:25:35.93#ibcon#read 6, iclass 26, count 2 2006.286.05:25:35.93#ibcon#end of sib2, iclass 26, count 2 2006.286.05:25:35.93#ibcon#*mode == 0, iclass 26, count 2 2006.286.05:25:35.93#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.05:25:35.93#ibcon#[25=AT04-06\r\n] 2006.286.05:25:35.93#ibcon#*before write, iclass 26, count 2 2006.286.05:25:35.93#ibcon#enter sib2, iclass 26, count 2 2006.286.05:25:35.93#ibcon#flushed, iclass 26, count 2 2006.286.05:25:35.93#ibcon#about to write, iclass 26, count 2 2006.286.05:25:35.93#ibcon#wrote, iclass 26, count 2 2006.286.05:25:35.93#ibcon#about to read 3, iclass 26, count 2 2006.286.05:25:35.96#ibcon#read 3, iclass 26, count 2 2006.286.05:25:35.96#ibcon#about to read 4, iclass 26, count 2 2006.286.05:25:35.96#ibcon#read 4, iclass 26, count 2 2006.286.05:25:35.96#ibcon#about to read 5, iclass 26, count 2 2006.286.05:25:35.96#ibcon#read 5, iclass 26, count 2 2006.286.05:25:35.96#ibcon#about to read 6, iclass 26, count 2 2006.286.05:25:35.96#ibcon#read 6, iclass 26, count 2 2006.286.05:25:35.96#ibcon#end of sib2, iclass 26, count 2 2006.286.05:25:35.96#ibcon#*after write, iclass 26, count 2 2006.286.05:25:35.96#ibcon#*before return 0, iclass 26, count 2 2006.286.05:25:35.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.05:25:35.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.05:25:35.96#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.05:25:35.96#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:35.96#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.05:25:36.08#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.05:25:36.08#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.05:25:36.08#ibcon#enter wrdev, iclass 26, count 0 2006.286.05:25:36.08#ibcon#first serial, iclass 26, count 0 2006.286.05:25:36.08#ibcon#enter sib2, iclass 26, count 0 2006.286.05:25:36.08#ibcon#flushed, iclass 26, count 0 2006.286.05:25:36.08#ibcon#about to write, iclass 26, count 0 2006.286.05:25:36.08#ibcon#wrote, iclass 26, count 0 2006.286.05:25:36.08#ibcon#about to read 3, iclass 26, count 0 2006.286.05:25:36.10#ibcon#read 3, iclass 26, count 0 2006.286.05:25:36.10#ibcon#about to read 4, iclass 26, count 0 2006.286.05:25:36.10#ibcon#read 4, iclass 26, count 0 2006.286.05:25:36.10#ibcon#about to read 5, iclass 26, count 0 2006.286.05:25:36.10#ibcon#read 5, iclass 26, count 0 2006.286.05:25:36.10#ibcon#about to read 6, iclass 26, count 0 2006.286.05:25:36.10#ibcon#read 6, iclass 26, count 0 2006.286.05:25:36.10#ibcon#end of sib2, iclass 26, count 0 2006.286.05:25:36.10#ibcon#*mode == 0, iclass 26, count 0 2006.286.05:25:36.10#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.05:25:36.10#ibcon#[25=USB\r\n] 2006.286.05:25:36.10#ibcon#*before write, iclass 26, count 0 2006.286.05:25:36.10#ibcon#enter sib2, iclass 26, count 0 2006.286.05:25:36.10#ibcon#flushed, iclass 26, count 0 2006.286.05:25:36.10#ibcon#about to write, iclass 26, count 0 2006.286.05:25:36.10#ibcon#wrote, iclass 26, count 0 2006.286.05:25:36.10#ibcon#about to read 3, iclass 26, count 0 2006.286.05:25:36.13#ibcon#read 3, iclass 26, count 0 2006.286.05:25:36.13#ibcon#about to read 4, iclass 26, count 0 2006.286.05:25:36.13#ibcon#read 4, iclass 26, count 0 2006.286.05:25:36.13#ibcon#about to read 5, iclass 26, count 0 2006.286.05:25:36.13#ibcon#read 5, iclass 26, count 0 2006.286.05:25:36.13#ibcon#about to read 6, iclass 26, count 0 2006.286.05:25:36.13#ibcon#read 6, iclass 26, count 0 2006.286.05:25:36.13#ibcon#end of sib2, iclass 26, count 0 2006.286.05:25:36.13#ibcon#*after write, iclass 26, count 0 2006.286.05:25:36.13#ibcon#*before return 0, iclass 26, count 0 2006.286.05:25:36.13#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.05:25:36.13#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.05:25:36.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.05:25:36.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.05:25:36.13$vck44/valo=5,734.99 2006.286.05:25:36.13#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.05:25:36.13#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.05:25:36.13#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:36.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.05:25:36.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.05:25:36.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.05:25:36.13#ibcon#enter wrdev, iclass 28, count 0 2006.286.05:25:36.13#ibcon#first serial, iclass 28, count 0 2006.286.05:25:36.13#ibcon#enter sib2, iclass 28, count 0 2006.286.05:25:36.13#ibcon#flushed, iclass 28, count 0 2006.286.05:25:36.13#ibcon#about to write, iclass 28, count 0 2006.286.05:25:36.13#ibcon#wrote, iclass 28, count 0 2006.286.05:25:36.13#ibcon#about to read 3, iclass 28, count 0 2006.286.05:25:36.15#ibcon#read 3, iclass 28, count 0 2006.286.05:25:36.15#ibcon#about to read 4, iclass 28, count 0 2006.286.05:25:36.15#ibcon#read 4, iclass 28, count 0 2006.286.05:25:36.15#ibcon#about to read 5, iclass 28, count 0 2006.286.05:25:36.15#ibcon#read 5, iclass 28, count 0 2006.286.05:25:36.15#ibcon#about to read 6, iclass 28, count 0 2006.286.05:25:36.15#ibcon#read 6, iclass 28, count 0 2006.286.05:25:36.15#ibcon#end of sib2, iclass 28, count 0 2006.286.05:25:36.15#ibcon#*mode == 0, iclass 28, count 0 2006.286.05:25:36.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.05:25:36.15#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.05:25:36.15#ibcon#*before write, iclass 28, count 0 2006.286.05:25:36.15#ibcon#enter sib2, iclass 28, count 0 2006.286.05:25:36.15#ibcon#flushed, iclass 28, count 0 2006.286.05:25:36.15#ibcon#about to write, iclass 28, count 0 2006.286.05:25:36.15#ibcon#wrote, iclass 28, count 0 2006.286.05:25:36.15#ibcon#about to read 3, iclass 28, count 0 2006.286.05:25:36.19#ibcon#read 3, iclass 28, count 0 2006.286.05:25:36.19#ibcon#about to read 4, iclass 28, count 0 2006.286.05:25:36.19#ibcon#read 4, iclass 28, count 0 2006.286.05:25:36.19#ibcon#about to read 5, iclass 28, count 0 2006.286.05:25:36.19#ibcon#read 5, iclass 28, count 0 2006.286.05:25:36.19#ibcon#about to read 6, iclass 28, count 0 2006.286.05:25:36.19#ibcon#read 6, iclass 28, count 0 2006.286.05:25:36.19#ibcon#end of sib2, iclass 28, count 0 2006.286.05:25:36.19#ibcon#*after write, iclass 28, count 0 2006.286.05:25:36.19#ibcon#*before return 0, iclass 28, count 0 2006.286.05:25:36.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.05:25:36.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.05:25:36.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.05:25:36.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.05:25:36.19$vck44/va=5,3 2006.286.05:25:36.19#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.05:25:36.19#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.05:25:36.19#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:36.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.05:25:36.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.05:25:36.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.05:25:36.25#ibcon#enter wrdev, iclass 30, count 2 2006.286.05:25:36.25#ibcon#first serial, iclass 30, count 2 2006.286.05:25:36.25#ibcon#enter sib2, iclass 30, count 2 2006.286.05:25:36.25#ibcon#flushed, iclass 30, count 2 2006.286.05:25:36.25#ibcon#about to write, iclass 30, count 2 2006.286.05:25:36.25#ibcon#wrote, iclass 30, count 2 2006.286.05:25:36.25#ibcon#about to read 3, iclass 30, count 2 2006.286.05:25:36.27#ibcon#read 3, iclass 30, count 2 2006.286.05:25:36.27#ibcon#about to read 4, iclass 30, count 2 2006.286.05:25:36.27#ibcon#read 4, iclass 30, count 2 2006.286.05:25:36.27#ibcon#about to read 5, iclass 30, count 2 2006.286.05:25:36.27#ibcon#read 5, iclass 30, count 2 2006.286.05:25:36.27#ibcon#about to read 6, iclass 30, count 2 2006.286.05:25:36.27#ibcon#read 6, iclass 30, count 2 2006.286.05:25:36.27#ibcon#end of sib2, iclass 30, count 2 2006.286.05:25:36.27#ibcon#*mode == 0, iclass 30, count 2 2006.286.05:25:36.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.05:25:36.27#ibcon#[25=AT05-03\r\n] 2006.286.05:25:36.27#ibcon#*before write, iclass 30, count 2 2006.286.05:25:36.27#ibcon#enter sib2, iclass 30, count 2 2006.286.05:25:36.27#ibcon#flushed, iclass 30, count 2 2006.286.05:25:36.27#ibcon#about to write, iclass 30, count 2 2006.286.05:25:36.27#ibcon#wrote, iclass 30, count 2 2006.286.05:25:36.27#ibcon#about to read 3, iclass 30, count 2 2006.286.05:25:36.30#ibcon#read 3, iclass 30, count 2 2006.286.05:25:36.30#ibcon#about to read 4, iclass 30, count 2 2006.286.05:25:36.30#ibcon#read 4, iclass 30, count 2 2006.286.05:25:36.30#ibcon#about to read 5, iclass 30, count 2 2006.286.05:25:36.30#ibcon#read 5, iclass 30, count 2 2006.286.05:25:36.30#ibcon#about to read 6, iclass 30, count 2 2006.286.05:25:36.30#ibcon#read 6, iclass 30, count 2 2006.286.05:25:36.30#ibcon#end of sib2, iclass 30, count 2 2006.286.05:25:36.30#ibcon#*after write, iclass 30, count 2 2006.286.05:25:36.30#ibcon#*before return 0, iclass 30, count 2 2006.286.05:25:36.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.05:25:36.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.05:25:36.30#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.05:25:36.30#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:36.30#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.05:25:36.42#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.05:25:36.42#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.05:25:36.42#ibcon#enter wrdev, iclass 30, count 0 2006.286.05:25:36.42#ibcon#first serial, iclass 30, count 0 2006.286.05:25:36.42#ibcon#enter sib2, iclass 30, count 0 2006.286.05:25:36.42#ibcon#flushed, iclass 30, count 0 2006.286.05:25:36.42#ibcon#about to write, iclass 30, count 0 2006.286.05:25:36.42#ibcon#wrote, iclass 30, count 0 2006.286.05:25:36.42#ibcon#about to read 3, iclass 30, count 0 2006.286.05:25:36.44#ibcon#read 3, iclass 30, count 0 2006.286.05:25:36.44#ibcon#about to read 4, iclass 30, count 0 2006.286.05:25:36.44#ibcon#read 4, iclass 30, count 0 2006.286.05:25:36.44#ibcon#about to read 5, iclass 30, count 0 2006.286.05:25:36.44#ibcon#read 5, iclass 30, count 0 2006.286.05:25:36.44#ibcon#about to read 6, iclass 30, count 0 2006.286.05:25:36.44#ibcon#read 6, iclass 30, count 0 2006.286.05:25:36.44#ibcon#end of sib2, iclass 30, count 0 2006.286.05:25:36.44#ibcon#*mode == 0, iclass 30, count 0 2006.286.05:25:36.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.05:25:36.44#ibcon#[25=USB\r\n] 2006.286.05:25:36.44#ibcon#*before write, iclass 30, count 0 2006.286.05:25:36.44#ibcon#enter sib2, iclass 30, count 0 2006.286.05:25:36.44#ibcon#flushed, iclass 30, count 0 2006.286.05:25:36.44#ibcon#about to write, iclass 30, count 0 2006.286.05:25:36.44#ibcon#wrote, iclass 30, count 0 2006.286.05:25:36.44#ibcon#about to read 3, iclass 30, count 0 2006.286.05:25:36.47#ibcon#read 3, iclass 30, count 0 2006.286.05:25:36.47#ibcon#about to read 4, iclass 30, count 0 2006.286.05:25:36.47#ibcon#read 4, iclass 30, count 0 2006.286.05:25:36.47#ibcon#about to read 5, iclass 30, count 0 2006.286.05:25:36.47#ibcon#read 5, iclass 30, count 0 2006.286.05:25:36.47#ibcon#about to read 6, iclass 30, count 0 2006.286.05:25:36.47#ibcon#read 6, iclass 30, count 0 2006.286.05:25:36.47#ibcon#end of sib2, iclass 30, count 0 2006.286.05:25:36.47#ibcon#*after write, iclass 30, count 0 2006.286.05:25:36.47#ibcon#*before return 0, iclass 30, count 0 2006.286.05:25:36.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.05:25:36.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.05:25:36.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.05:25:36.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.05:25:36.47$vck44/valo=6,814.99 2006.286.05:25:36.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.05:25:36.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.05:25:36.47#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:36.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.05:25:36.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.05:25:36.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.05:25:36.47#ibcon#enter wrdev, iclass 32, count 0 2006.286.05:25:36.47#ibcon#first serial, iclass 32, count 0 2006.286.05:25:36.47#ibcon#enter sib2, iclass 32, count 0 2006.286.05:25:36.47#ibcon#flushed, iclass 32, count 0 2006.286.05:25:36.47#ibcon#about to write, iclass 32, count 0 2006.286.05:25:36.47#ibcon#wrote, iclass 32, count 0 2006.286.05:25:36.47#ibcon#about to read 3, iclass 32, count 0 2006.286.05:25:36.49#ibcon#read 3, iclass 32, count 0 2006.286.05:25:36.49#ibcon#about to read 4, iclass 32, count 0 2006.286.05:25:36.49#ibcon#read 4, iclass 32, count 0 2006.286.05:25:36.49#ibcon#about to read 5, iclass 32, count 0 2006.286.05:25:36.49#ibcon#read 5, iclass 32, count 0 2006.286.05:25:36.49#ibcon#about to read 6, iclass 32, count 0 2006.286.05:25:36.49#ibcon#read 6, iclass 32, count 0 2006.286.05:25:36.49#ibcon#end of sib2, iclass 32, count 0 2006.286.05:25:36.49#ibcon#*mode == 0, iclass 32, count 0 2006.286.05:25:36.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.05:25:36.49#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.05:25:36.49#ibcon#*before write, iclass 32, count 0 2006.286.05:25:36.49#ibcon#enter sib2, iclass 32, count 0 2006.286.05:25:36.49#ibcon#flushed, iclass 32, count 0 2006.286.05:25:36.49#ibcon#about to write, iclass 32, count 0 2006.286.05:25:36.49#ibcon#wrote, iclass 32, count 0 2006.286.05:25:36.49#ibcon#about to read 3, iclass 32, count 0 2006.286.05:25:36.53#ibcon#read 3, iclass 32, count 0 2006.286.05:25:36.53#ibcon#about to read 4, iclass 32, count 0 2006.286.05:25:36.53#ibcon#read 4, iclass 32, count 0 2006.286.05:25:36.53#ibcon#about to read 5, iclass 32, count 0 2006.286.05:25:36.53#ibcon#read 5, iclass 32, count 0 2006.286.05:25:36.53#ibcon#about to read 6, iclass 32, count 0 2006.286.05:25:36.53#ibcon#read 6, iclass 32, count 0 2006.286.05:25:36.53#ibcon#end of sib2, iclass 32, count 0 2006.286.05:25:36.53#ibcon#*after write, iclass 32, count 0 2006.286.05:25:36.53#ibcon#*before return 0, iclass 32, count 0 2006.286.05:25:36.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.05:25:36.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.05:25:36.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.05:25:36.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.05:25:36.53$vck44/va=6,4 2006.286.05:25:36.53#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.05:25:36.53#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.05:25:36.53#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:36.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.05:25:36.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.05:25:36.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.05:25:36.59#ibcon#enter wrdev, iclass 34, count 2 2006.286.05:25:36.59#ibcon#first serial, iclass 34, count 2 2006.286.05:25:36.59#ibcon#enter sib2, iclass 34, count 2 2006.286.05:25:36.59#ibcon#flushed, iclass 34, count 2 2006.286.05:25:36.59#ibcon#about to write, iclass 34, count 2 2006.286.05:25:36.59#ibcon#wrote, iclass 34, count 2 2006.286.05:25:36.59#ibcon#about to read 3, iclass 34, count 2 2006.286.05:25:36.61#ibcon#read 3, iclass 34, count 2 2006.286.05:25:36.61#ibcon#about to read 4, iclass 34, count 2 2006.286.05:25:36.61#ibcon#read 4, iclass 34, count 2 2006.286.05:25:36.61#ibcon#about to read 5, iclass 34, count 2 2006.286.05:25:36.61#ibcon#read 5, iclass 34, count 2 2006.286.05:25:36.61#ibcon#about to read 6, iclass 34, count 2 2006.286.05:25:36.61#ibcon#read 6, iclass 34, count 2 2006.286.05:25:36.61#ibcon#end of sib2, iclass 34, count 2 2006.286.05:25:36.61#ibcon#*mode == 0, iclass 34, count 2 2006.286.05:25:36.61#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.05:25:36.61#ibcon#[25=AT06-04\r\n] 2006.286.05:25:36.61#ibcon#*before write, iclass 34, count 2 2006.286.05:25:36.61#ibcon#enter sib2, iclass 34, count 2 2006.286.05:25:36.61#ibcon#flushed, iclass 34, count 2 2006.286.05:25:36.61#ibcon#about to write, iclass 34, count 2 2006.286.05:25:36.61#ibcon#wrote, iclass 34, count 2 2006.286.05:25:36.61#ibcon#about to read 3, iclass 34, count 2 2006.286.05:25:36.64#ibcon#read 3, iclass 34, count 2 2006.286.05:25:36.64#ibcon#about to read 4, iclass 34, count 2 2006.286.05:25:36.64#ibcon#read 4, iclass 34, count 2 2006.286.05:25:36.64#ibcon#about to read 5, iclass 34, count 2 2006.286.05:25:36.64#ibcon#read 5, iclass 34, count 2 2006.286.05:25:36.64#ibcon#about to read 6, iclass 34, count 2 2006.286.05:25:36.64#ibcon#read 6, iclass 34, count 2 2006.286.05:25:36.64#ibcon#end of sib2, iclass 34, count 2 2006.286.05:25:36.64#ibcon#*after write, iclass 34, count 2 2006.286.05:25:36.64#ibcon#*before return 0, iclass 34, count 2 2006.286.05:25:36.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.05:25:36.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.05:25:36.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.05:25:36.64#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:36.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.05:25:36.76#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.05:25:36.76#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.05:25:36.76#ibcon#enter wrdev, iclass 34, count 0 2006.286.05:25:36.76#ibcon#first serial, iclass 34, count 0 2006.286.05:25:36.76#ibcon#enter sib2, iclass 34, count 0 2006.286.05:25:36.76#ibcon#flushed, iclass 34, count 0 2006.286.05:25:36.76#ibcon#about to write, iclass 34, count 0 2006.286.05:25:36.76#ibcon#wrote, iclass 34, count 0 2006.286.05:25:36.76#ibcon#about to read 3, iclass 34, count 0 2006.286.05:25:36.78#ibcon#read 3, iclass 34, count 0 2006.286.05:25:36.78#ibcon#about to read 4, iclass 34, count 0 2006.286.05:25:36.78#ibcon#read 4, iclass 34, count 0 2006.286.05:25:36.78#ibcon#about to read 5, iclass 34, count 0 2006.286.05:25:36.78#ibcon#read 5, iclass 34, count 0 2006.286.05:25:36.78#ibcon#about to read 6, iclass 34, count 0 2006.286.05:25:36.78#ibcon#read 6, iclass 34, count 0 2006.286.05:25:36.78#ibcon#end of sib2, iclass 34, count 0 2006.286.05:25:36.78#ibcon#*mode == 0, iclass 34, count 0 2006.286.05:25:36.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.05:25:36.78#ibcon#[25=USB\r\n] 2006.286.05:25:36.78#ibcon#*before write, iclass 34, count 0 2006.286.05:25:36.78#ibcon#enter sib2, iclass 34, count 0 2006.286.05:25:36.78#ibcon#flushed, iclass 34, count 0 2006.286.05:25:36.78#ibcon#about to write, iclass 34, count 0 2006.286.05:25:36.78#ibcon#wrote, iclass 34, count 0 2006.286.05:25:36.78#ibcon#about to read 3, iclass 34, count 0 2006.286.05:25:36.81#ibcon#read 3, iclass 34, count 0 2006.286.05:25:36.81#ibcon#about to read 4, iclass 34, count 0 2006.286.05:25:36.81#ibcon#read 4, iclass 34, count 0 2006.286.05:25:36.81#ibcon#about to read 5, iclass 34, count 0 2006.286.05:25:36.81#ibcon#read 5, iclass 34, count 0 2006.286.05:25:36.81#ibcon#about to read 6, iclass 34, count 0 2006.286.05:25:36.81#ibcon#read 6, iclass 34, count 0 2006.286.05:25:36.81#ibcon#end of sib2, iclass 34, count 0 2006.286.05:25:36.81#ibcon#*after write, iclass 34, count 0 2006.286.05:25:36.81#ibcon#*before return 0, iclass 34, count 0 2006.286.05:25:36.81#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.05:25:36.81#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.05:25:36.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.05:25:36.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.05:25:36.81$vck44/valo=7,864.99 2006.286.05:25:36.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.05:25:36.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.05:25:36.81#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:36.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.05:25:36.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.05:25:36.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.05:25:36.81#ibcon#enter wrdev, iclass 36, count 0 2006.286.05:25:36.81#ibcon#first serial, iclass 36, count 0 2006.286.05:25:36.81#ibcon#enter sib2, iclass 36, count 0 2006.286.05:25:36.81#ibcon#flushed, iclass 36, count 0 2006.286.05:25:36.81#ibcon#about to write, iclass 36, count 0 2006.286.05:25:36.81#ibcon#wrote, iclass 36, count 0 2006.286.05:25:36.81#ibcon#about to read 3, iclass 36, count 0 2006.286.05:25:36.83#ibcon#read 3, iclass 36, count 0 2006.286.05:25:36.95#ibcon#about to read 4, iclass 36, count 0 2006.286.05:25:36.95#ibcon#read 4, iclass 36, count 0 2006.286.05:25:36.95#ibcon#about to read 5, iclass 36, count 0 2006.286.05:25:36.95#ibcon#read 5, iclass 36, count 0 2006.286.05:25:36.95#ibcon#about to read 6, iclass 36, count 0 2006.286.05:25:36.95#ibcon#read 6, iclass 36, count 0 2006.286.05:25:36.95#ibcon#end of sib2, iclass 36, count 0 2006.286.05:25:36.95#ibcon#*mode == 0, iclass 36, count 0 2006.286.05:25:36.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.05:25:36.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.05:25:36.95#ibcon#*before write, iclass 36, count 0 2006.286.05:25:36.95#ibcon#enter sib2, iclass 36, count 0 2006.286.05:25:36.95#ibcon#flushed, iclass 36, count 0 2006.286.05:25:36.95#ibcon#about to write, iclass 36, count 0 2006.286.05:25:36.95#ibcon#wrote, iclass 36, count 0 2006.286.05:25:36.95#ibcon#about to read 3, iclass 36, count 0 2006.286.05:25:37.00#ibcon#read 3, iclass 36, count 0 2006.286.05:25:37.00#ibcon#about to read 4, iclass 36, count 0 2006.286.05:25:37.00#ibcon#read 4, iclass 36, count 0 2006.286.05:25:37.00#ibcon#about to read 5, iclass 36, count 0 2006.286.05:25:37.00#ibcon#read 5, iclass 36, count 0 2006.286.05:25:37.00#ibcon#about to read 6, iclass 36, count 0 2006.286.05:25:37.00#ibcon#read 6, iclass 36, count 0 2006.286.05:25:37.00#ibcon#end of sib2, iclass 36, count 0 2006.286.05:25:37.00#ibcon#*after write, iclass 36, count 0 2006.286.05:25:37.00#ibcon#*before return 0, iclass 36, count 0 2006.286.05:25:37.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.05:25:37.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.05:25:37.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.05:25:37.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.05:25:37.00$vck44/va=7,4 2006.286.05:25:37.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.05:25:37.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.05:25:37.00#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:37.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.05:25:37.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.05:25:37.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.05:25:37.00#ibcon#enter wrdev, iclass 38, count 2 2006.286.05:25:37.00#ibcon#first serial, iclass 38, count 2 2006.286.05:25:37.00#ibcon#enter sib2, iclass 38, count 2 2006.286.05:25:37.00#ibcon#flushed, iclass 38, count 2 2006.286.05:25:37.00#ibcon#about to write, iclass 38, count 2 2006.286.05:25:37.00#ibcon#wrote, iclass 38, count 2 2006.286.05:25:37.00#ibcon#about to read 3, iclass 38, count 2 2006.286.05:25:37.02#ibcon#read 3, iclass 38, count 2 2006.286.05:25:37.02#ibcon#about to read 4, iclass 38, count 2 2006.286.05:25:37.02#ibcon#read 4, iclass 38, count 2 2006.286.05:25:37.02#ibcon#about to read 5, iclass 38, count 2 2006.286.05:25:37.02#ibcon#read 5, iclass 38, count 2 2006.286.05:25:37.02#ibcon#about to read 6, iclass 38, count 2 2006.286.05:25:37.02#ibcon#read 6, iclass 38, count 2 2006.286.05:25:37.02#ibcon#end of sib2, iclass 38, count 2 2006.286.05:25:37.02#ibcon#*mode == 0, iclass 38, count 2 2006.286.05:25:37.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.05:25:37.02#ibcon#[25=AT07-04\r\n] 2006.286.05:25:37.02#ibcon#*before write, iclass 38, count 2 2006.286.05:25:37.02#ibcon#enter sib2, iclass 38, count 2 2006.286.05:25:37.02#ibcon#flushed, iclass 38, count 2 2006.286.05:25:37.02#ibcon#about to write, iclass 38, count 2 2006.286.05:25:37.02#ibcon#wrote, iclass 38, count 2 2006.286.05:25:37.02#ibcon#about to read 3, iclass 38, count 2 2006.286.05:25:37.05#ibcon#read 3, iclass 38, count 2 2006.286.05:25:37.05#ibcon#about to read 4, iclass 38, count 2 2006.286.05:25:37.05#ibcon#read 4, iclass 38, count 2 2006.286.05:25:37.05#ibcon#about to read 5, iclass 38, count 2 2006.286.05:25:37.05#ibcon#read 5, iclass 38, count 2 2006.286.05:25:37.05#ibcon#about to read 6, iclass 38, count 2 2006.286.05:25:37.05#ibcon#read 6, iclass 38, count 2 2006.286.05:25:37.05#ibcon#end of sib2, iclass 38, count 2 2006.286.05:25:37.05#ibcon#*after write, iclass 38, count 2 2006.286.05:25:37.05#ibcon#*before return 0, iclass 38, count 2 2006.286.05:25:37.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.05:25:37.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.05:25:37.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.05:25:37.05#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:37.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.05:25:37.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.05:25:37.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.05:25:37.17#ibcon#enter wrdev, iclass 38, count 0 2006.286.05:25:37.17#ibcon#first serial, iclass 38, count 0 2006.286.05:25:37.17#ibcon#enter sib2, iclass 38, count 0 2006.286.05:25:37.17#ibcon#flushed, iclass 38, count 0 2006.286.05:25:37.17#ibcon#about to write, iclass 38, count 0 2006.286.05:25:37.17#ibcon#wrote, iclass 38, count 0 2006.286.05:25:37.17#ibcon#about to read 3, iclass 38, count 0 2006.286.05:25:37.19#ibcon#read 3, iclass 38, count 0 2006.286.05:25:37.19#ibcon#about to read 4, iclass 38, count 0 2006.286.05:25:37.19#ibcon#read 4, iclass 38, count 0 2006.286.05:25:37.19#ibcon#about to read 5, iclass 38, count 0 2006.286.05:25:37.19#ibcon#read 5, iclass 38, count 0 2006.286.05:25:37.19#ibcon#about to read 6, iclass 38, count 0 2006.286.05:25:37.19#ibcon#read 6, iclass 38, count 0 2006.286.05:25:37.19#ibcon#end of sib2, iclass 38, count 0 2006.286.05:25:37.19#ibcon#*mode == 0, iclass 38, count 0 2006.286.05:25:37.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.05:25:37.19#ibcon#[25=USB\r\n] 2006.286.05:25:37.19#ibcon#*before write, iclass 38, count 0 2006.286.05:25:37.19#ibcon#enter sib2, iclass 38, count 0 2006.286.05:25:37.19#ibcon#flushed, iclass 38, count 0 2006.286.05:25:37.19#ibcon#about to write, iclass 38, count 0 2006.286.05:25:37.19#ibcon#wrote, iclass 38, count 0 2006.286.05:25:37.19#ibcon#about to read 3, iclass 38, count 0 2006.286.05:25:37.22#ibcon#read 3, iclass 38, count 0 2006.286.05:25:37.22#ibcon#about to read 4, iclass 38, count 0 2006.286.05:25:37.22#ibcon#read 4, iclass 38, count 0 2006.286.05:25:37.22#ibcon#about to read 5, iclass 38, count 0 2006.286.05:25:37.22#ibcon#read 5, iclass 38, count 0 2006.286.05:25:37.22#ibcon#about to read 6, iclass 38, count 0 2006.286.05:25:37.22#ibcon#read 6, iclass 38, count 0 2006.286.05:25:37.22#ibcon#end of sib2, iclass 38, count 0 2006.286.05:25:37.22#ibcon#*after write, iclass 38, count 0 2006.286.05:25:37.22#ibcon#*before return 0, iclass 38, count 0 2006.286.05:25:37.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.05:25:37.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.05:25:37.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.05:25:37.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.05:25:37.22$vck44/valo=8,884.99 2006.286.05:25:37.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.05:25:37.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.05:25:37.22#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:37.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.05:25:37.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.05:25:37.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.05:25:37.22#ibcon#enter wrdev, iclass 40, count 0 2006.286.05:25:37.22#ibcon#first serial, iclass 40, count 0 2006.286.05:25:37.22#ibcon#enter sib2, iclass 40, count 0 2006.286.05:25:37.22#ibcon#flushed, iclass 40, count 0 2006.286.05:25:37.22#ibcon#about to write, iclass 40, count 0 2006.286.05:25:37.22#ibcon#wrote, iclass 40, count 0 2006.286.05:25:37.22#ibcon#about to read 3, iclass 40, count 0 2006.286.05:25:37.24#ibcon#read 3, iclass 40, count 0 2006.286.05:25:37.24#ibcon#about to read 4, iclass 40, count 0 2006.286.05:25:37.24#ibcon#read 4, iclass 40, count 0 2006.286.05:25:37.24#ibcon#about to read 5, iclass 40, count 0 2006.286.05:25:37.24#ibcon#read 5, iclass 40, count 0 2006.286.05:25:37.24#ibcon#about to read 6, iclass 40, count 0 2006.286.05:25:37.24#ibcon#read 6, iclass 40, count 0 2006.286.05:25:37.24#ibcon#end of sib2, iclass 40, count 0 2006.286.05:25:37.24#ibcon#*mode == 0, iclass 40, count 0 2006.286.05:25:37.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.05:25:37.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.05:25:37.24#ibcon#*before write, iclass 40, count 0 2006.286.05:25:37.24#ibcon#enter sib2, iclass 40, count 0 2006.286.05:25:37.24#ibcon#flushed, iclass 40, count 0 2006.286.05:25:37.24#ibcon#about to write, iclass 40, count 0 2006.286.05:25:37.24#ibcon#wrote, iclass 40, count 0 2006.286.05:25:37.24#ibcon#about to read 3, iclass 40, count 0 2006.286.05:25:37.28#ibcon#read 3, iclass 40, count 0 2006.286.05:25:37.28#ibcon#about to read 4, iclass 40, count 0 2006.286.05:25:37.28#ibcon#read 4, iclass 40, count 0 2006.286.05:25:37.28#ibcon#about to read 5, iclass 40, count 0 2006.286.05:25:37.28#ibcon#read 5, iclass 40, count 0 2006.286.05:25:37.28#ibcon#about to read 6, iclass 40, count 0 2006.286.05:25:37.28#ibcon#read 6, iclass 40, count 0 2006.286.05:25:37.28#ibcon#end of sib2, iclass 40, count 0 2006.286.05:25:37.28#ibcon#*after write, iclass 40, count 0 2006.286.05:25:37.28#ibcon#*before return 0, iclass 40, count 0 2006.286.05:25:37.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.05:25:37.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.05:25:37.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.05:25:37.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.05:25:37.28$vck44/va=8,3 2006.286.05:25:37.28#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.286.05:25:37.28#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.286.05:25:37.28#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:37.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.05:25:37.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.286.05:25:37.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.05:25:37.34#ibcon#enter wrdev, iclass 4, count 2 2006.286.05:25:37.34#ibcon#first serial, iclass 4, count 2 2006.286.05:25:37.34#ibcon#enter sib2, iclass 4, count 2 2006.286.05:25:37.34#ibcon#flushed, iclass 4, count 2 2006.286.05:25:37.34#ibcon#about to write, iclass 4, count 2 2006.286.05:25:37.34#ibcon#wrote, iclass 4, count 2 2006.286.05:25:37.34#ibcon#about to read 3, iclass 4, count 2 2006.286.05:25:37.36#ibcon#read 3, iclass 4, count 2 2006.286.05:25:37.36#ibcon#about to read 4, iclass 4, count 2 2006.286.05:25:37.36#ibcon#read 4, iclass 4, count 2 2006.286.05:25:37.36#ibcon#about to read 5, iclass 4, count 2 2006.286.05:25:37.36#ibcon#read 5, iclass 4, count 2 2006.286.05:25:37.36#ibcon#about to read 6, iclass 4, count 2 2006.286.05:25:37.36#ibcon#read 6, iclass 4, count 2 2006.286.05:25:37.36#ibcon#end of sib2, iclass 4, count 2 2006.286.05:25:37.36#ibcon#*mode == 0, iclass 4, count 2 2006.286.05:25:37.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.286.05:25:37.36#ibcon#[25=AT08-03\r\n] 2006.286.05:25:37.36#ibcon#*before write, iclass 4, count 2 2006.286.05:25:37.36#ibcon#enter sib2, iclass 4, count 2 2006.286.05:25:37.36#ibcon#flushed, iclass 4, count 2 2006.286.05:25:37.36#ibcon#about to write, iclass 4, count 2 2006.286.05:25:37.36#ibcon#wrote, iclass 4, count 2 2006.286.05:25:37.36#ibcon#about to read 3, iclass 4, count 2 2006.286.05:25:37.39#ibcon#read 3, iclass 4, count 2 2006.286.05:25:37.39#ibcon#about to read 4, iclass 4, count 2 2006.286.05:25:37.39#ibcon#read 4, iclass 4, count 2 2006.286.05:25:37.39#ibcon#about to read 5, iclass 4, count 2 2006.286.05:25:37.39#ibcon#read 5, iclass 4, count 2 2006.286.05:25:37.39#ibcon#about to read 6, iclass 4, count 2 2006.286.05:25:37.39#ibcon#read 6, iclass 4, count 2 2006.286.05:25:37.39#ibcon#end of sib2, iclass 4, count 2 2006.286.05:25:37.39#ibcon#*after write, iclass 4, count 2 2006.286.05:25:37.39#ibcon#*before return 0, iclass 4, count 2 2006.286.05:25:37.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.286.05:25:37.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.286.05:25:37.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.286.05:25:37.39#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:37.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.05:25:37.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.286.05:25:37.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.05:25:37.51#ibcon#enter wrdev, iclass 4, count 0 2006.286.05:25:37.51#ibcon#first serial, iclass 4, count 0 2006.286.05:25:37.51#ibcon#enter sib2, iclass 4, count 0 2006.286.05:25:37.51#ibcon#flushed, iclass 4, count 0 2006.286.05:25:37.51#ibcon#about to write, iclass 4, count 0 2006.286.05:25:37.51#ibcon#wrote, iclass 4, count 0 2006.286.05:25:37.51#ibcon#about to read 3, iclass 4, count 0 2006.286.05:25:37.53#ibcon#read 3, iclass 4, count 0 2006.286.05:25:37.53#ibcon#about to read 4, iclass 4, count 0 2006.286.05:25:37.53#ibcon#read 4, iclass 4, count 0 2006.286.05:25:37.53#ibcon#about to read 5, iclass 4, count 0 2006.286.05:25:37.53#ibcon#read 5, iclass 4, count 0 2006.286.05:25:37.53#ibcon#about to read 6, iclass 4, count 0 2006.286.05:25:37.53#ibcon#read 6, iclass 4, count 0 2006.286.05:25:37.53#ibcon#end of sib2, iclass 4, count 0 2006.286.05:25:37.53#ibcon#*mode == 0, iclass 4, count 0 2006.286.05:25:37.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.05:25:37.53#ibcon#[25=USB\r\n] 2006.286.05:25:37.53#ibcon#*before write, iclass 4, count 0 2006.286.05:25:37.53#ibcon#enter sib2, iclass 4, count 0 2006.286.05:25:37.53#ibcon#flushed, iclass 4, count 0 2006.286.05:25:37.53#ibcon#about to write, iclass 4, count 0 2006.286.05:25:37.53#ibcon#wrote, iclass 4, count 0 2006.286.05:25:37.53#ibcon#about to read 3, iclass 4, count 0 2006.286.05:25:37.56#ibcon#read 3, iclass 4, count 0 2006.286.05:25:37.56#ibcon#about to read 4, iclass 4, count 0 2006.286.05:25:37.56#ibcon#read 4, iclass 4, count 0 2006.286.05:25:37.56#ibcon#about to read 5, iclass 4, count 0 2006.286.05:25:37.56#ibcon#read 5, iclass 4, count 0 2006.286.05:25:37.56#ibcon#about to read 6, iclass 4, count 0 2006.286.05:25:37.56#ibcon#read 6, iclass 4, count 0 2006.286.05:25:37.56#ibcon#end of sib2, iclass 4, count 0 2006.286.05:25:37.56#ibcon#*after write, iclass 4, count 0 2006.286.05:25:37.56#ibcon#*before return 0, iclass 4, count 0 2006.286.05:25:37.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.286.05:25:37.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.286.05:25:37.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.05:25:37.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.05:25:37.56$vck44/vblo=1,629.99 2006.286.05:25:37.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.05:25:37.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.05:25:37.56#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:37.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.05:25:37.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.05:25:37.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.05:25:37.56#ibcon#enter wrdev, iclass 6, count 0 2006.286.05:25:37.56#ibcon#first serial, iclass 6, count 0 2006.286.05:25:37.56#ibcon#enter sib2, iclass 6, count 0 2006.286.05:25:37.56#ibcon#flushed, iclass 6, count 0 2006.286.05:25:37.56#ibcon#about to write, iclass 6, count 0 2006.286.05:25:37.56#ibcon#wrote, iclass 6, count 0 2006.286.05:25:37.56#ibcon#about to read 3, iclass 6, count 0 2006.286.05:25:37.58#ibcon#read 3, iclass 6, count 0 2006.286.05:25:37.58#ibcon#about to read 4, iclass 6, count 0 2006.286.05:25:37.58#ibcon#read 4, iclass 6, count 0 2006.286.05:25:37.58#ibcon#about to read 5, iclass 6, count 0 2006.286.05:25:37.58#ibcon#read 5, iclass 6, count 0 2006.286.05:25:37.58#ibcon#about to read 6, iclass 6, count 0 2006.286.05:25:37.58#ibcon#read 6, iclass 6, count 0 2006.286.05:25:37.58#ibcon#end of sib2, iclass 6, count 0 2006.286.05:25:37.58#ibcon#*mode == 0, iclass 6, count 0 2006.286.05:25:37.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.05:25:37.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.05:25:37.58#ibcon#*before write, iclass 6, count 0 2006.286.05:25:37.58#ibcon#enter sib2, iclass 6, count 0 2006.286.05:25:37.58#ibcon#flushed, iclass 6, count 0 2006.286.05:25:37.58#ibcon#about to write, iclass 6, count 0 2006.286.05:25:37.58#ibcon#wrote, iclass 6, count 0 2006.286.05:25:37.58#ibcon#about to read 3, iclass 6, count 0 2006.286.05:25:37.62#ibcon#read 3, iclass 6, count 0 2006.286.05:25:37.62#ibcon#about to read 4, iclass 6, count 0 2006.286.05:25:37.62#ibcon#read 4, iclass 6, count 0 2006.286.05:25:37.62#ibcon#about to read 5, iclass 6, count 0 2006.286.05:25:37.62#ibcon#read 5, iclass 6, count 0 2006.286.05:25:37.62#ibcon#about to read 6, iclass 6, count 0 2006.286.05:25:37.62#ibcon#read 6, iclass 6, count 0 2006.286.05:25:37.62#ibcon#end of sib2, iclass 6, count 0 2006.286.05:25:37.62#ibcon#*after write, iclass 6, count 0 2006.286.05:25:37.62#ibcon#*before return 0, iclass 6, count 0 2006.286.05:25:37.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.05:25:37.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.05:25:37.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.05:25:37.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.05:25:37.62$vck44/vb=1,4 2006.286.05:25:37.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.286.05:25:37.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.286.05:25:37.62#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:37.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.05:25:37.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.286.05:25:37.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.05:25:37.62#ibcon#enter wrdev, iclass 10, count 2 2006.286.05:25:37.62#ibcon#first serial, iclass 10, count 2 2006.286.05:25:37.62#ibcon#enter sib2, iclass 10, count 2 2006.286.05:25:37.62#ibcon#flushed, iclass 10, count 2 2006.286.05:25:37.62#ibcon#about to write, iclass 10, count 2 2006.286.05:25:37.62#ibcon#wrote, iclass 10, count 2 2006.286.05:25:37.62#ibcon#about to read 3, iclass 10, count 2 2006.286.05:25:37.64#ibcon#read 3, iclass 10, count 2 2006.286.05:25:37.64#ibcon#about to read 4, iclass 10, count 2 2006.286.05:25:37.64#ibcon#read 4, iclass 10, count 2 2006.286.05:25:37.64#ibcon#about to read 5, iclass 10, count 2 2006.286.05:25:37.64#ibcon#read 5, iclass 10, count 2 2006.286.05:25:37.64#ibcon#about to read 6, iclass 10, count 2 2006.286.05:25:37.64#ibcon#read 6, iclass 10, count 2 2006.286.05:25:37.64#ibcon#end of sib2, iclass 10, count 2 2006.286.05:25:37.64#ibcon#*mode == 0, iclass 10, count 2 2006.286.05:25:37.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.286.05:25:37.64#ibcon#[27=AT01-04\r\n] 2006.286.05:25:37.64#ibcon#*before write, iclass 10, count 2 2006.286.05:25:37.64#ibcon#enter sib2, iclass 10, count 2 2006.286.05:25:37.64#ibcon#flushed, iclass 10, count 2 2006.286.05:25:37.64#ibcon#about to write, iclass 10, count 2 2006.286.05:25:37.64#ibcon#wrote, iclass 10, count 2 2006.286.05:25:37.64#ibcon#about to read 3, iclass 10, count 2 2006.286.05:25:37.67#ibcon#read 3, iclass 10, count 2 2006.286.05:25:37.67#ibcon#about to read 4, iclass 10, count 2 2006.286.05:25:37.67#ibcon#read 4, iclass 10, count 2 2006.286.05:25:37.67#ibcon#about to read 5, iclass 10, count 2 2006.286.05:25:37.67#ibcon#read 5, iclass 10, count 2 2006.286.05:25:37.67#ibcon#about to read 6, iclass 10, count 2 2006.286.05:25:37.67#ibcon#read 6, iclass 10, count 2 2006.286.05:25:37.67#ibcon#end of sib2, iclass 10, count 2 2006.286.05:25:37.67#ibcon#*after write, iclass 10, count 2 2006.286.05:25:37.67#ibcon#*before return 0, iclass 10, count 2 2006.286.05:25:37.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.286.05:25:37.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.286.05:25:37.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.286.05:25:37.67#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:37.67#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.05:25:37.79#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.286.05:25:37.79#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.05:25:37.79#ibcon#enter wrdev, iclass 10, count 0 2006.286.05:25:37.79#ibcon#first serial, iclass 10, count 0 2006.286.05:25:37.79#ibcon#enter sib2, iclass 10, count 0 2006.286.05:25:37.79#ibcon#flushed, iclass 10, count 0 2006.286.05:25:37.79#ibcon#about to write, iclass 10, count 0 2006.286.05:25:37.79#ibcon#wrote, iclass 10, count 0 2006.286.05:25:37.79#ibcon#about to read 3, iclass 10, count 0 2006.286.05:25:37.81#ibcon#read 3, iclass 10, count 0 2006.286.05:25:37.81#ibcon#about to read 4, iclass 10, count 0 2006.286.05:25:37.81#ibcon#read 4, iclass 10, count 0 2006.286.05:25:37.81#ibcon#about to read 5, iclass 10, count 0 2006.286.05:25:37.81#ibcon#read 5, iclass 10, count 0 2006.286.05:25:37.81#ibcon#about to read 6, iclass 10, count 0 2006.286.05:25:37.81#ibcon#read 6, iclass 10, count 0 2006.286.05:25:37.81#ibcon#end of sib2, iclass 10, count 0 2006.286.05:25:37.81#ibcon#*mode == 0, iclass 10, count 0 2006.286.05:25:37.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.05:25:37.81#ibcon#[27=USB\r\n] 2006.286.05:25:37.81#ibcon#*before write, iclass 10, count 0 2006.286.05:25:37.81#ibcon#enter sib2, iclass 10, count 0 2006.286.05:25:37.81#ibcon#flushed, iclass 10, count 0 2006.286.05:25:37.81#ibcon#about to write, iclass 10, count 0 2006.286.05:25:37.81#ibcon#wrote, iclass 10, count 0 2006.286.05:25:37.81#ibcon#about to read 3, iclass 10, count 0 2006.286.05:25:37.84#ibcon#read 3, iclass 10, count 0 2006.286.05:25:37.84#ibcon#about to read 4, iclass 10, count 0 2006.286.05:25:37.84#ibcon#read 4, iclass 10, count 0 2006.286.05:25:37.84#ibcon#about to read 5, iclass 10, count 0 2006.286.05:25:37.84#ibcon#read 5, iclass 10, count 0 2006.286.05:25:37.84#ibcon#about to read 6, iclass 10, count 0 2006.286.05:25:37.84#ibcon#read 6, iclass 10, count 0 2006.286.05:25:37.84#ibcon#end of sib2, iclass 10, count 0 2006.286.05:25:37.84#ibcon#*after write, iclass 10, count 0 2006.286.05:25:37.84#ibcon#*before return 0, iclass 10, count 0 2006.286.05:25:37.84#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.286.05:25:37.84#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.286.05:25:37.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.05:25:37.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.05:25:37.84$vck44/vblo=2,634.99 2006.286.05:25:37.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.286.05:25:37.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.286.05:25:37.84#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:37.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.05:25:37.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.286.05:25:37.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.05:25:37.84#ibcon#enter wrdev, iclass 12, count 0 2006.286.05:25:37.84#ibcon#first serial, iclass 12, count 0 2006.286.05:25:37.84#ibcon#enter sib2, iclass 12, count 0 2006.286.05:25:37.84#ibcon#flushed, iclass 12, count 0 2006.286.05:25:37.84#ibcon#about to write, iclass 12, count 0 2006.286.05:25:37.84#ibcon#wrote, iclass 12, count 0 2006.286.05:25:37.84#ibcon#about to read 3, iclass 12, count 0 2006.286.05:25:37.86#ibcon#read 3, iclass 12, count 0 2006.286.05:25:37.92#ibcon#about to read 4, iclass 12, count 0 2006.286.05:25:37.92#ibcon#read 4, iclass 12, count 0 2006.286.05:25:37.92#ibcon#about to read 5, iclass 12, count 0 2006.286.05:25:37.92#ibcon#read 5, iclass 12, count 0 2006.286.05:25:37.92#ibcon#about to read 6, iclass 12, count 0 2006.286.05:25:37.92#ibcon#read 6, iclass 12, count 0 2006.286.05:25:37.92#ibcon#end of sib2, iclass 12, count 0 2006.286.05:25:37.92#ibcon#*mode == 0, iclass 12, count 0 2006.286.05:25:37.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.05:25:37.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.05:25:37.92#ibcon#*before write, iclass 12, count 0 2006.286.05:25:37.92#ibcon#enter sib2, iclass 12, count 0 2006.286.05:25:37.92#ibcon#flushed, iclass 12, count 0 2006.286.05:25:37.92#ibcon#about to write, iclass 12, count 0 2006.286.05:25:37.92#ibcon#wrote, iclass 12, count 0 2006.286.05:25:37.92#ibcon#about to read 3, iclass 12, count 0 2006.286.05:25:37.96#ibcon#read 3, iclass 12, count 0 2006.286.05:25:37.96#ibcon#about to read 4, iclass 12, count 0 2006.286.05:25:37.96#ibcon#read 4, iclass 12, count 0 2006.286.05:25:37.96#ibcon#about to read 5, iclass 12, count 0 2006.286.05:25:37.96#ibcon#read 5, iclass 12, count 0 2006.286.05:25:37.96#ibcon#about to read 6, iclass 12, count 0 2006.286.05:25:37.96#ibcon#read 6, iclass 12, count 0 2006.286.05:25:37.96#ibcon#end of sib2, iclass 12, count 0 2006.286.05:25:37.96#ibcon#*after write, iclass 12, count 0 2006.286.05:25:37.96#ibcon#*before return 0, iclass 12, count 0 2006.286.05:25:37.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.286.05:25:37.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.286.05:25:37.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.05:25:37.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.05:25:37.96$vck44/vb=2,5 2006.286.05:25:37.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.286.05:25:37.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.286.05:25:37.96#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:37.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.05:25:37.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.286.05:25:37.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.05:25:37.96#ibcon#enter wrdev, iclass 14, count 2 2006.286.05:25:37.96#ibcon#first serial, iclass 14, count 2 2006.286.05:25:37.96#ibcon#enter sib2, iclass 14, count 2 2006.286.05:25:37.96#ibcon#flushed, iclass 14, count 2 2006.286.05:25:37.96#ibcon#about to write, iclass 14, count 2 2006.286.05:25:37.96#ibcon#wrote, iclass 14, count 2 2006.286.05:25:37.96#ibcon#about to read 3, iclass 14, count 2 2006.286.05:25:37.98#ibcon#read 3, iclass 14, count 2 2006.286.05:25:37.98#ibcon#about to read 4, iclass 14, count 2 2006.286.05:25:37.98#ibcon#read 4, iclass 14, count 2 2006.286.05:25:37.98#ibcon#about to read 5, iclass 14, count 2 2006.286.05:25:37.98#ibcon#read 5, iclass 14, count 2 2006.286.05:25:37.98#ibcon#about to read 6, iclass 14, count 2 2006.286.05:25:37.98#ibcon#read 6, iclass 14, count 2 2006.286.05:25:37.98#ibcon#end of sib2, iclass 14, count 2 2006.286.05:25:37.98#ibcon#*mode == 0, iclass 14, count 2 2006.286.05:25:37.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.286.05:25:37.98#ibcon#[27=AT02-05\r\n] 2006.286.05:25:37.98#ibcon#*before write, iclass 14, count 2 2006.286.05:25:37.98#ibcon#enter sib2, iclass 14, count 2 2006.286.05:25:37.98#ibcon#flushed, iclass 14, count 2 2006.286.05:25:37.98#ibcon#about to write, iclass 14, count 2 2006.286.05:25:37.98#ibcon#wrote, iclass 14, count 2 2006.286.05:25:37.98#ibcon#about to read 3, iclass 14, count 2 2006.286.05:25:38.01#ibcon#read 3, iclass 14, count 2 2006.286.05:25:38.01#ibcon#about to read 4, iclass 14, count 2 2006.286.05:25:38.01#ibcon#read 4, iclass 14, count 2 2006.286.05:25:38.01#ibcon#about to read 5, iclass 14, count 2 2006.286.05:25:38.01#ibcon#read 5, iclass 14, count 2 2006.286.05:25:38.01#ibcon#about to read 6, iclass 14, count 2 2006.286.05:25:38.01#ibcon#read 6, iclass 14, count 2 2006.286.05:25:38.01#ibcon#end of sib2, iclass 14, count 2 2006.286.05:25:38.01#ibcon#*after write, iclass 14, count 2 2006.286.05:25:38.01#ibcon#*before return 0, iclass 14, count 2 2006.286.05:25:38.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.286.05:25:38.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.286.05:25:38.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.286.05:25:38.01#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:38.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.05:25:38.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.286.05:25:38.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.05:25:38.13#ibcon#enter wrdev, iclass 14, count 0 2006.286.05:25:38.13#ibcon#first serial, iclass 14, count 0 2006.286.05:25:38.13#ibcon#enter sib2, iclass 14, count 0 2006.286.05:25:38.13#ibcon#flushed, iclass 14, count 0 2006.286.05:25:38.13#ibcon#about to write, iclass 14, count 0 2006.286.05:25:38.13#ibcon#wrote, iclass 14, count 0 2006.286.05:25:38.13#ibcon#about to read 3, iclass 14, count 0 2006.286.05:25:38.15#ibcon#read 3, iclass 14, count 0 2006.286.05:25:38.15#ibcon#about to read 4, iclass 14, count 0 2006.286.05:25:38.15#ibcon#read 4, iclass 14, count 0 2006.286.05:25:38.15#ibcon#about to read 5, iclass 14, count 0 2006.286.05:25:38.15#ibcon#read 5, iclass 14, count 0 2006.286.05:25:38.15#ibcon#about to read 6, iclass 14, count 0 2006.286.05:25:38.15#ibcon#read 6, iclass 14, count 0 2006.286.05:25:38.15#ibcon#end of sib2, iclass 14, count 0 2006.286.05:25:38.15#ibcon#*mode == 0, iclass 14, count 0 2006.286.05:25:38.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.05:25:38.15#ibcon#[27=USB\r\n] 2006.286.05:25:38.15#ibcon#*before write, iclass 14, count 0 2006.286.05:25:38.15#ibcon#enter sib2, iclass 14, count 0 2006.286.05:25:38.15#ibcon#flushed, iclass 14, count 0 2006.286.05:25:38.15#ibcon#about to write, iclass 14, count 0 2006.286.05:25:38.15#ibcon#wrote, iclass 14, count 0 2006.286.05:25:38.15#ibcon#about to read 3, iclass 14, count 0 2006.286.05:25:38.18#ibcon#read 3, iclass 14, count 0 2006.286.05:25:38.18#ibcon#about to read 4, iclass 14, count 0 2006.286.05:25:38.18#ibcon#read 4, iclass 14, count 0 2006.286.05:25:38.18#ibcon#about to read 5, iclass 14, count 0 2006.286.05:25:38.18#ibcon#read 5, iclass 14, count 0 2006.286.05:25:38.18#ibcon#about to read 6, iclass 14, count 0 2006.286.05:25:38.18#ibcon#read 6, iclass 14, count 0 2006.286.05:25:38.18#ibcon#end of sib2, iclass 14, count 0 2006.286.05:25:38.18#ibcon#*after write, iclass 14, count 0 2006.286.05:25:38.18#ibcon#*before return 0, iclass 14, count 0 2006.286.05:25:38.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.286.05:25:38.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.286.05:25:38.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.05:25:38.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.05:25:38.18$vck44/vblo=3,649.99 2006.286.05:25:38.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.286.05:25:38.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.286.05:25:38.18#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:38.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:25:38.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:25:38.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:25:38.18#ibcon#enter wrdev, iclass 16, count 0 2006.286.05:25:38.18#ibcon#first serial, iclass 16, count 0 2006.286.05:25:38.18#ibcon#enter sib2, iclass 16, count 0 2006.286.05:25:38.18#ibcon#flushed, iclass 16, count 0 2006.286.05:25:38.18#ibcon#about to write, iclass 16, count 0 2006.286.05:25:38.18#ibcon#wrote, iclass 16, count 0 2006.286.05:25:38.18#ibcon#about to read 3, iclass 16, count 0 2006.286.05:25:38.20#ibcon#read 3, iclass 16, count 0 2006.286.05:25:38.20#ibcon#about to read 4, iclass 16, count 0 2006.286.05:25:38.20#ibcon#read 4, iclass 16, count 0 2006.286.05:25:38.20#ibcon#about to read 5, iclass 16, count 0 2006.286.05:25:38.20#ibcon#read 5, iclass 16, count 0 2006.286.05:25:38.20#ibcon#about to read 6, iclass 16, count 0 2006.286.05:25:38.20#ibcon#read 6, iclass 16, count 0 2006.286.05:25:38.20#ibcon#end of sib2, iclass 16, count 0 2006.286.05:25:38.20#ibcon#*mode == 0, iclass 16, count 0 2006.286.05:25:38.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.05:25:38.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.05:25:38.20#ibcon#*before write, iclass 16, count 0 2006.286.05:25:38.20#ibcon#enter sib2, iclass 16, count 0 2006.286.05:25:38.20#ibcon#flushed, iclass 16, count 0 2006.286.05:25:38.20#ibcon#about to write, iclass 16, count 0 2006.286.05:25:38.20#ibcon#wrote, iclass 16, count 0 2006.286.05:25:38.20#ibcon#about to read 3, iclass 16, count 0 2006.286.05:25:38.24#ibcon#read 3, iclass 16, count 0 2006.286.05:25:38.24#ibcon#about to read 4, iclass 16, count 0 2006.286.05:25:38.24#ibcon#read 4, iclass 16, count 0 2006.286.05:25:38.24#ibcon#about to read 5, iclass 16, count 0 2006.286.05:25:38.24#ibcon#read 5, iclass 16, count 0 2006.286.05:25:38.24#ibcon#about to read 6, iclass 16, count 0 2006.286.05:25:38.24#ibcon#read 6, iclass 16, count 0 2006.286.05:25:38.24#ibcon#end of sib2, iclass 16, count 0 2006.286.05:25:38.24#ibcon#*after write, iclass 16, count 0 2006.286.05:25:38.24#ibcon#*before return 0, iclass 16, count 0 2006.286.05:25:38.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:25:38.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.286.05:25:38.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.05:25:38.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.05:25:38.24$vck44/vb=3,4 2006.286.05:25:38.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.286.05:25:38.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.286.05:25:38.24#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:38.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.05:25:38.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.286.05:25:38.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.05:25:38.30#ibcon#enter wrdev, iclass 18, count 2 2006.286.05:25:38.30#ibcon#first serial, iclass 18, count 2 2006.286.05:25:38.30#ibcon#enter sib2, iclass 18, count 2 2006.286.05:25:38.30#ibcon#flushed, iclass 18, count 2 2006.286.05:25:38.30#ibcon#about to write, iclass 18, count 2 2006.286.05:25:38.30#ibcon#wrote, iclass 18, count 2 2006.286.05:25:38.30#ibcon#about to read 3, iclass 18, count 2 2006.286.05:25:38.32#ibcon#read 3, iclass 18, count 2 2006.286.05:25:38.32#ibcon#about to read 4, iclass 18, count 2 2006.286.05:25:38.32#ibcon#read 4, iclass 18, count 2 2006.286.05:25:38.32#ibcon#about to read 5, iclass 18, count 2 2006.286.05:25:38.32#ibcon#read 5, iclass 18, count 2 2006.286.05:25:38.32#ibcon#about to read 6, iclass 18, count 2 2006.286.05:25:38.32#ibcon#read 6, iclass 18, count 2 2006.286.05:25:38.32#ibcon#end of sib2, iclass 18, count 2 2006.286.05:25:38.32#ibcon#*mode == 0, iclass 18, count 2 2006.286.05:25:38.32#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.286.05:25:38.32#ibcon#[27=AT03-04\r\n] 2006.286.05:25:38.32#ibcon#*before write, iclass 18, count 2 2006.286.05:25:38.32#ibcon#enter sib2, iclass 18, count 2 2006.286.05:25:38.32#ibcon#flushed, iclass 18, count 2 2006.286.05:25:38.32#ibcon#about to write, iclass 18, count 2 2006.286.05:25:38.32#ibcon#wrote, iclass 18, count 2 2006.286.05:25:38.32#ibcon#about to read 3, iclass 18, count 2 2006.286.05:25:38.35#ibcon#read 3, iclass 18, count 2 2006.286.05:25:38.35#ibcon#about to read 4, iclass 18, count 2 2006.286.05:25:38.35#ibcon#read 4, iclass 18, count 2 2006.286.05:25:38.35#ibcon#about to read 5, iclass 18, count 2 2006.286.05:25:38.35#ibcon#read 5, iclass 18, count 2 2006.286.05:25:38.35#ibcon#about to read 6, iclass 18, count 2 2006.286.05:25:38.35#ibcon#read 6, iclass 18, count 2 2006.286.05:25:38.35#ibcon#end of sib2, iclass 18, count 2 2006.286.05:25:38.35#ibcon#*after write, iclass 18, count 2 2006.286.05:25:38.35#ibcon#*before return 0, iclass 18, count 2 2006.286.05:25:38.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.286.05:25:38.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.286.05:25:38.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.286.05:25:38.35#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:38.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.05:25:38.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.286.05:25:38.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.05:25:38.47#ibcon#enter wrdev, iclass 18, count 0 2006.286.05:25:38.47#ibcon#first serial, iclass 18, count 0 2006.286.05:25:38.47#ibcon#enter sib2, iclass 18, count 0 2006.286.05:25:38.47#ibcon#flushed, iclass 18, count 0 2006.286.05:25:38.47#ibcon#about to write, iclass 18, count 0 2006.286.05:25:38.47#ibcon#wrote, iclass 18, count 0 2006.286.05:25:38.47#ibcon#about to read 3, iclass 18, count 0 2006.286.05:25:38.49#ibcon#read 3, iclass 18, count 0 2006.286.05:25:38.49#ibcon#about to read 4, iclass 18, count 0 2006.286.05:25:38.49#ibcon#read 4, iclass 18, count 0 2006.286.05:25:38.49#ibcon#about to read 5, iclass 18, count 0 2006.286.05:25:38.49#ibcon#read 5, iclass 18, count 0 2006.286.05:25:38.49#ibcon#about to read 6, iclass 18, count 0 2006.286.05:25:38.49#ibcon#read 6, iclass 18, count 0 2006.286.05:25:38.49#ibcon#end of sib2, iclass 18, count 0 2006.286.05:25:38.49#ibcon#*mode == 0, iclass 18, count 0 2006.286.05:25:38.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.05:25:38.49#ibcon#[27=USB\r\n] 2006.286.05:25:38.49#ibcon#*before write, iclass 18, count 0 2006.286.05:25:38.49#ibcon#enter sib2, iclass 18, count 0 2006.286.05:25:38.49#ibcon#flushed, iclass 18, count 0 2006.286.05:25:38.49#ibcon#about to write, iclass 18, count 0 2006.286.05:25:38.49#ibcon#wrote, iclass 18, count 0 2006.286.05:25:38.49#ibcon#about to read 3, iclass 18, count 0 2006.286.05:25:38.52#ibcon#read 3, iclass 18, count 0 2006.286.05:25:38.52#ibcon#about to read 4, iclass 18, count 0 2006.286.05:25:38.52#ibcon#read 4, iclass 18, count 0 2006.286.05:25:38.52#ibcon#about to read 5, iclass 18, count 0 2006.286.05:25:38.52#ibcon#read 5, iclass 18, count 0 2006.286.05:25:38.52#ibcon#about to read 6, iclass 18, count 0 2006.286.05:25:38.52#ibcon#read 6, iclass 18, count 0 2006.286.05:25:38.52#ibcon#end of sib2, iclass 18, count 0 2006.286.05:25:38.52#ibcon#*after write, iclass 18, count 0 2006.286.05:25:38.52#ibcon#*before return 0, iclass 18, count 0 2006.286.05:25:38.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.286.05:25:38.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.286.05:25:38.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.05:25:38.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.05:25:38.52$vck44/vblo=4,679.99 2006.286.05:25:38.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.05:25:38.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.05:25:38.52#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:38.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:25:38.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:25:38.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:25:38.52#ibcon#enter wrdev, iclass 20, count 0 2006.286.05:25:38.52#ibcon#first serial, iclass 20, count 0 2006.286.05:25:38.52#ibcon#enter sib2, iclass 20, count 0 2006.286.05:25:38.52#ibcon#flushed, iclass 20, count 0 2006.286.05:25:38.52#ibcon#about to write, iclass 20, count 0 2006.286.05:25:38.52#ibcon#wrote, iclass 20, count 0 2006.286.05:25:38.52#ibcon#about to read 3, iclass 20, count 0 2006.286.05:25:38.54#ibcon#read 3, iclass 20, count 0 2006.286.05:25:38.54#ibcon#about to read 4, iclass 20, count 0 2006.286.05:25:38.54#ibcon#read 4, iclass 20, count 0 2006.286.05:25:38.54#ibcon#about to read 5, iclass 20, count 0 2006.286.05:25:38.54#ibcon#read 5, iclass 20, count 0 2006.286.05:25:38.54#ibcon#about to read 6, iclass 20, count 0 2006.286.05:25:38.54#ibcon#read 6, iclass 20, count 0 2006.286.05:25:38.54#ibcon#end of sib2, iclass 20, count 0 2006.286.05:25:38.54#ibcon#*mode == 0, iclass 20, count 0 2006.286.05:25:38.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.05:25:38.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.05:25:38.54#ibcon#*before write, iclass 20, count 0 2006.286.05:25:38.54#ibcon#enter sib2, iclass 20, count 0 2006.286.05:25:38.54#ibcon#flushed, iclass 20, count 0 2006.286.05:25:38.54#ibcon#about to write, iclass 20, count 0 2006.286.05:25:38.54#ibcon#wrote, iclass 20, count 0 2006.286.05:25:38.54#ibcon#about to read 3, iclass 20, count 0 2006.286.05:25:38.58#ibcon#read 3, iclass 20, count 0 2006.286.05:25:38.58#ibcon#about to read 4, iclass 20, count 0 2006.286.05:25:38.58#ibcon#read 4, iclass 20, count 0 2006.286.05:25:38.58#ibcon#about to read 5, iclass 20, count 0 2006.286.05:25:38.58#ibcon#read 5, iclass 20, count 0 2006.286.05:25:38.58#ibcon#about to read 6, iclass 20, count 0 2006.286.05:25:38.58#ibcon#read 6, iclass 20, count 0 2006.286.05:25:38.58#ibcon#end of sib2, iclass 20, count 0 2006.286.05:25:38.58#ibcon#*after write, iclass 20, count 0 2006.286.05:25:38.58#ibcon#*before return 0, iclass 20, count 0 2006.286.05:25:38.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:25:38.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:25:38.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.05:25:38.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.05:25:38.58$vck44/vb=4,5 2006.286.05:25:38.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.286.05:25:38.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.286.05:25:38.58#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:38.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.05:25:38.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.286.05:25:38.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.05:25:38.64#ibcon#enter wrdev, iclass 22, count 2 2006.286.05:25:38.64#ibcon#first serial, iclass 22, count 2 2006.286.05:25:38.64#ibcon#enter sib2, iclass 22, count 2 2006.286.05:25:38.64#ibcon#flushed, iclass 22, count 2 2006.286.05:25:38.64#ibcon#about to write, iclass 22, count 2 2006.286.05:25:38.64#ibcon#wrote, iclass 22, count 2 2006.286.05:25:38.64#ibcon#about to read 3, iclass 22, count 2 2006.286.05:25:38.66#ibcon#read 3, iclass 22, count 2 2006.286.05:25:38.66#ibcon#about to read 4, iclass 22, count 2 2006.286.05:25:38.66#ibcon#read 4, iclass 22, count 2 2006.286.05:25:38.66#ibcon#about to read 5, iclass 22, count 2 2006.286.05:25:38.66#ibcon#read 5, iclass 22, count 2 2006.286.05:25:38.66#ibcon#about to read 6, iclass 22, count 2 2006.286.05:25:38.66#ibcon#read 6, iclass 22, count 2 2006.286.05:25:38.66#ibcon#end of sib2, iclass 22, count 2 2006.286.05:25:38.66#ibcon#*mode == 0, iclass 22, count 2 2006.286.05:25:38.66#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.286.05:25:38.66#ibcon#[27=AT04-05\r\n] 2006.286.05:25:38.66#ibcon#*before write, iclass 22, count 2 2006.286.05:25:38.66#ibcon#enter sib2, iclass 22, count 2 2006.286.05:25:38.66#ibcon#flushed, iclass 22, count 2 2006.286.05:25:38.66#ibcon#about to write, iclass 22, count 2 2006.286.05:25:38.66#ibcon#wrote, iclass 22, count 2 2006.286.05:25:38.66#ibcon#about to read 3, iclass 22, count 2 2006.286.05:25:38.69#ibcon#read 3, iclass 22, count 2 2006.286.05:25:38.69#ibcon#about to read 4, iclass 22, count 2 2006.286.05:25:38.69#ibcon#read 4, iclass 22, count 2 2006.286.05:25:38.69#ibcon#about to read 5, iclass 22, count 2 2006.286.05:25:38.69#ibcon#read 5, iclass 22, count 2 2006.286.05:25:38.69#ibcon#about to read 6, iclass 22, count 2 2006.286.05:25:38.69#ibcon#read 6, iclass 22, count 2 2006.286.05:25:38.69#ibcon#end of sib2, iclass 22, count 2 2006.286.05:25:38.69#ibcon#*after write, iclass 22, count 2 2006.286.05:25:38.69#ibcon#*before return 0, iclass 22, count 2 2006.286.05:25:38.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.286.05:25:38.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.286.05:25:38.69#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.286.05:25:38.69#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:38.69#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.05:25:38.81#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.286.05:25:38.81#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.05:25:38.81#ibcon#enter wrdev, iclass 22, count 0 2006.286.05:25:38.81#ibcon#first serial, iclass 22, count 0 2006.286.05:25:38.81#ibcon#enter sib2, iclass 22, count 0 2006.286.05:25:38.81#ibcon#flushed, iclass 22, count 0 2006.286.05:25:38.81#ibcon#about to write, iclass 22, count 0 2006.286.05:25:38.81#ibcon#wrote, iclass 22, count 0 2006.286.05:25:38.81#ibcon#about to read 3, iclass 22, count 0 2006.286.05:25:38.83#ibcon#read 3, iclass 22, count 0 2006.286.05:25:38.83#ibcon#about to read 4, iclass 22, count 0 2006.286.05:25:38.83#ibcon#read 4, iclass 22, count 0 2006.286.05:25:38.83#ibcon#about to read 5, iclass 22, count 0 2006.286.05:25:38.83#ibcon#read 5, iclass 22, count 0 2006.286.05:25:38.83#ibcon#about to read 6, iclass 22, count 0 2006.286.05:25:38.83#ibcon#read 6, iclass 22, count 0 2006.286.05:25:38.83#ibcon#end of sib2, iclass 22, count 0 2006.286.05:25:38.83#ibcon#*mode == 0, iclass 22, count 0 2006.286.05:25:38.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.05:25:38.83#ibcon#[27=USB\r\n] 2006.286.05:25:38.83#ibcon#*before write, iclass 22, count 0 2006.286.05:25:38.83#ibcon#enter sib2, iclass 22, count 0 2006.286.05:25:38.83#ibcon#flushed, iclass 22, count 0 2006.286.05:25:38.83#ibcon#about to write, iclass 22, count 0 2006.286.05:25:38.83#ibcon#wrote, iclass 22, count 0 2006.286.05:25:38.83#ibcon#about to read 3, iclass 22, count 0 2006.286.05:25:38.86#ibcon#read 3, iclass 22, count 0 2006.286.05:25:38.86#ibcon#about to read 4, iclass 22, count 0 2006.286.05:25:38.86#ibcon#read 4, iclass 22, count 0 2006.286.05:25:38.86#ibcon#about to read 5, iclass 22, count 0 2006.286.05:25:38.86#ibcon#read 5, iclass 22, count 0 2006.286.05:25:38.86#ibcon#about to read 6, iclass 22, count 0 2006.286.05:25:38.86#ibcon#read 6, iclass 22, count 0 2006.286.05:25:38.86#ibcon#end of sib2, iclass 22, count 0 2006.286.05:25:38.86#ibcon#*after write, iclass 22, count 0 2006.286.05:25:38.86#ibcon#*before return 0, iclass 22, count 0 2006.286.05:25:38.86#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.286.05:25:38.86#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.286.05:25:38.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.05:25:38.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.05:25:38.86$vck44/vblo=5,709.99 2006.286.05:25:38.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.286.05:25:38.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.286.05:25:38.86#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:38.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.05:25:38.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.286.05:25:38.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.05:25:38.86#ibcon#enter wrdev, iclass 24, count 0 2006.286.05:25:38.86#ibcon#first serial, iclass 24, count 0 2006.286.05:25:38.86#ibcon#enter sib2, iclass 24, count 0 2006.286.05:25:38.86#ibcon#flushed, iclass 24, count 0 2006.286.05:25:38.86#ibcon#about to write, iclass 24, count 0 2006.286.05:25:38.86#ibcon#wrote, iclass 24, count 0 2006.286.05:25:38.86#ibcon#about to read 3, iclass 24, count 0 2006.286.05:25:38.88#ibcon#read 3, iclass 24, count 0 2006.286.05:25:39.03#ibcon#about to read 4, iclass 24, count 0 2006.286.05:25:39.03#ibcon#read 4, iclass 24, count 0 2006.286.05:25:39.03#ibcon#about to read 5, iclass 24, count 0 2006.286.05:25:39.03#ibcon#read 5, iclass 24, count 0 2006.286.05:25:39.03#ibcon#about to read 6, iclass 24, count 0 2006.286.05:25:39.03#ibcon#read 6, iclass 24, count 0 2006.286.05:25:39.03#ibcon#end of sib2, iclass 24, count 0 2006.286.05:25:39.03#ibcon#*mode == 0, iclass 24, count 0 2006.286.05:25:39.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.05:25:39.03#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.05:25:39.03#ibcon#*before write, iclass 24, count 0 2006.286.05:25:39.03#ibcon#enter sib2, iclass 24, count 0 2006.286.05:25:39.03#ibcon#flushed, iclass 24, count 0 2006.286.05:25:39.03#ibcon#about to write, iclass 24, count 0 2006.286.05:25:39.03#ibcon#wrote, iclass 24, count 0 2006.286.05:25:39.03#ibcon#about to read 3, iclass 24, count 0 2006.286.05:25:39.07#ibcon#read 3, iclass 24, count 0 2006.286.05:25:39.07#ibcon#about to read 4, iclass 24, count 0 2006.286.05:25:39.07#ibcon#read 4, iclass 24, count 0 2006.286.05:25:39.07#ibcon#about to read 5, iclass 24, count 0 2006.286.05:25:39.07#ibcon#read 5, iclass 24, count 0 2006.286.05:25:39.07#ibcon#about to read 6, iclass 24, count 0 2006.286.05:25:39.07#ibcon#read 6, iclass 24, count 0 2006.286.05:25:39.07#ibcon#end of sib2, iclass 24, count 0 2006.286.05:25:39.07#ibcon#*after write, iclass 24, count 0 2006.286.05:25:39.07#ibcon#*before return 0, iclass 24, count 0 2006.286.05:25:39.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.286.05:25:39.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.286.05:25:39.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.05:25:39.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.05:25:39.07$vck44/vb=5,4 2006.286.05:25:39.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.286.05:25:39.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.286.05:25:39.07#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:39.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.05:25:39.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.286.05:25:39.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.05:25:39.07#ibcon#enter wrdev, iclass 26, count 2 2006.286.05:25:39.07#ibcon#first serial, iclass 26, count 2 2006.286.05:25:39.07#ibcon#enter sib2, iclass 26, count 2 2006.286.05:25:39.07#ibcon#flushed, iclass 26, count 2 2006.286.05:25:39.07#ibcon#about to write, iclass 26, count 2 2006.286.05:25:39.07#ibcon#wrote, iclass 26, count 2 2006.286.05:25:39.07#ibcon#about to read 3, iclass 26, count 2 2006.286.05:25:39.09#ibcon#read 3, iclass 26, count 2 2006.286.05:25:39.09#ibcon#about to read 4, iclass 26, count 2 2006.286.05:25:39.09#ibcon#read 4, iclass 26, count 2 2006.286.05:25:39.09#ibcon#about to read 5, iclass 26, count 2 2006.286.05:25:39.09#ibcon#read 5, iclass 26, count 2 2006.286.05:25:39.09#ibcon#about to read 6, iclass 26, count 2 2006.286.05:25:39.09#ibcon#read 6, iclass 26, count 2 2006.286.05:25:39.09#ibcon#end of sib2, iclass 26, count 2 2006.286.05:25:39.09#ibcon#*mode == 0, iclass 26, count 2 2006.286.05:25:39.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.286.05:25:39.09#ibcon#[27=AT05-04\r\n] 2006.286.05:25:39.09#ibcon#*before write, iclass 26, count 2 2006.286.05:25:39.09#ibcon#enter sib2, iclass 26, count 2 2006.286.05:25:39.09#ibcon#flushed, iclass 26, count 2 2006.286.05:25:39.09#ibcon#about to write, iclass 26, count 2 2006.286.05:25:39.09#ibcon#wrote, iclass 26, count 2 2006.286.05:25:39.09#ibcon#about to read 3, iclass 26, count 2 2006.286.05:25:39.12#ibcon#read 3, iclass 26, count 2 2006.286.05:25:39.12#ibcon#about to read 4, iclass 26, count 2 2006.286.05:25:39.12#ibcon#read 4, iclass 26, count 2 2006.286.05:25:39.12#ibcon#about to read 5, iclass 26, count 2 2006.286.05:25:39.12#ibcon#read 5, iclass 26, count 2 2006.286.05:25:39.12#ibcon#about to read 6, iclass 26, count 2 2006.286.05:25:39.12#ibcon#read 6, iclass 26, count 2 2006.286.05:25:39.12#ibcon#end of sib2, iclass 26, count 2 2006.286.05:25:39.12#ibcon#*after write, iclass 26, count 2 2006.286.05:25:39.12#ibcon#*before return 0, iclass 26, count 2 2006.286.05:25:39.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.286.05:25:39.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.286.05:25:39.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.286.05:25:39.12#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:39.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.05:25:39.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.286.05:25:39.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.05:25:39.24#ibcon#enter wrdev, iclass 26, count 0 2006.286.05:25:39.24#ibcon#first serial, iclass 26, count 0 2006.286.05:25:39.24#ibcon#enter sib2, iclass 26, count 0 2006.286.05:25:39.24#ibcon#flushed, iclass 26, count 0 2006.286.05:25:39.24#ibcon#about to write, iclass 26, count 0 2006.286.05:25:39.24#ibcon#wrote, iclass 26, count 0 2006.286.05:25:39.24#ibcon#about to read 3, iclass 26, count 0 2006.286.05:25:39.26#ibcon#read 3, iclass 26, count 0 2006.286.05:25:39.26#ibcon#about to read 4, iclass 26, count 0 2006.286.05:25:39.26#ibcon#read 4, iclass 26, count 0 2006.286.05:25:39.26#ibcon#about to read 5, iclass 26, count 0 2006.286.05:25:39.26#ibcon#read 5, iclass 26, count 0 2006.286.05:25:39.26#ibcon#about to read 6, iclass 26, count 0 2006.286.05:25:39.26#ibcon#read 6, iclass 26, count 0 2006.286.05:25:39.26#ibcon#end of sib2, iclass 26, count 0 2006.286.05:25:39.26#ibcon#*mode == 0, iclass 26, count 0 2006.286.05:25:39.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.05:25:39.26#ibcon#[27=USB\r\n] 2006.286.05:25:39.26#ibcon#*before write, iclass 26, count 0 2006.286.05:25:39.26#ibcon#enter sib2, iclass 26, count 0 2006.286.05:25:39.26#ibcon#flushed, iclass 26, count 0 2006.286.05:25:39.26#ibcon#about to write, iclass 26, count 0 2006.286.05:25:39.26#ibcon#wrote, iclass 26, count 0 2006.286.05:25:39.26#ibcon#about to read 3, iclass 26, count 0 2006.286.05:25:39.29#ibcon#read 3, iclass 26, count 0 2006.286.05:25:39.29#ibcon#about to read 4, iclass 26, count 0 2006.286.05:25:39.29#ibcon#read 4, iclass 26, count 0 2006.286.05:25:39.29#ibcon#about to read 5, iclass 26, count 0 2006.286.05:25:39.29#ibcon#read 5, iclass 26, count 0 2006.286.05:25:39.29#ibcon#about to read 6, iclass 26, count 0 2006.286.05:25:39.29#ibcon#read 6, iclass 26, count 0 2006.286.05:25:39.29#ibcon#end of sib2, iclass 26, count 0 2006.286.05:25:39.29#ibcon#*after write, iclass 26, count 0 2006.286.05:25:39.29#ibcon#*before return 0, iclass 26, count 0 2006.286.05:25:39.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.286.05:25:39.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.286.05:25:39.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.05:25:39.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.05:25:39.29$vck44/vblo=6,719.99 2006.286.05:25:39.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.286.05:25:39.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.286.05:25:39.29#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:39.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.05:25:39.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.286.05:25:39.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.05:25:39.29#ibcon#enter wrdev, iclass 28, count 0 2006.286.05:25:39.29#ibcon#first serial, iclass 28, count 0 2006.286.05:25:39.29#ibcon#enter sib2, iclass 28, count 0 2006.286.05:25:39.29#ibcon#flushed, iclass 28, count 0 2006.286.05:25:39.29#ibcon#about to write, iclass 28, count 0 2006.286.05:25:39.29#ibcon#wrote, iclass 28, count 0 2006.286.05:25:39.29#ibcon#about to read 3, iclass 28, count 0 2006.286.05:25:39.31#ibcon#read 3, iclass 28, count 0 2006.286.05:25:39.31#ibcon#about to read 4, iclass 28, count 0 2006.286.05:25:39.31#ibcon#read 4, iclass 28, count 0 2006.286.05:25:39.31#ibcon#about to read 5, iclass 28, count 0 2006.286.05:25:39.31#ibcon#read 5, iclass 28, count 0 2006.286.05:25:39.31#ibcon#about to read 6, iclass 28, count 0 2006.286.05:25:39.31#ibcon#read 6, iclass 28, count 0 2006.286.05:25:39.31#ibcon#end of sib2, iclass 28, count 0 2006.286.05:25:39.31#ibcon#*mode == 0, iclass 28, count 0 2006.286.05:25:39.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.05:25:39.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.05:25:39.31#ibcon#*before write, iclass 28, count 0 2006.286.05:25:39.31#ibcon#enter sib2, iclass 28, count 0 2006.286.05:25:39.31#ibcon#flushed, iclass 28, count 0 2006.286.05:25:39.31#ibcon#about to write, iclass 28, count 0 2006.286.05:25:39.31#ibcon#wrote, iclass 28, count 0 2006.286.05:25:39.31#ibcon#about to read 3, iclass 28, count 0 2006.286.05:25:39.35#ibcon#read 3, iclass 28, count 0 2006.286.05:25:39.35#ibcon#about to read 4, iclass 28, count 0 2006.286.05:25:39.35#ibcon#read 4, iclass 28, count 0 2006.286.05:25:39.35#ibcon#about to read 5, iclass 28, count 0 2006.286.05:25:39.35#ibcon#read 5, iclass 28, count 0 2006.286.05:25:39.35#ibcon#about to read 6, iclass 28, count 0 2006.286.05:25:39.35#ibcon#read 6, iclass 28, count 0 2006.286.05:25:39.35#ibcon#end of sib2, iclass 28, count 0 2006.286.05:25:39.35#ibcon#*after write, iclass 28, count 0 2006.286.05:25:39.35#ibcon#*before return 0, iclass 28, count 0 2006.286.05:25:39.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.286.05:25:39.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.286.05:25:39.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.05:25:39.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.05:25:39.35$vck44/vb=6,3 2006.286.05:25:39.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.286.05:25:39.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.286.05:25:39.35#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:39.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.05:25:39.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.286.05:25:39.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.05:25:39.41#ibcon#enter wrdev, iclass 30, count 2 2006.286.05:25:39.41#ibcon#first serial, iclass 30, count 2 2006.286.05:25:39.41#ibcon#enter sib2, iclass 30, count 2 2006.286.05:25:39.41#ibcon#flushed, iclass 30, count 2 2006.286.05:25:39.41#ibcon#about to write, iclass 30, count 2 2006.286.05:25:39.41#ibcon#wrote, iclass 30, count 2 2006.286.05:25:39.41#ibcon#about to read 3, iclass 30, count 2 2006.286.05:25:39.43#ibcon#read 3, iclass 30, count 2 2006.286.05:25:39.43#ibcon#about to read 4, iclass 30, count 2 2006.286.05:25:39.43#ibcon#read 4, iclass 30, count 2 2006.286.05:25:39.43#ibcon#about to read 5, iclass 30, count 2 2006.286.05:25:39.43#ibcon#read 5, iclass 30, count 2 2006.286.05:25:39.43#ibcon#about to read 6, iclass 30, count 2 2006.286.05:25:39.43#ibcon#read 6, iclass 30, count 2 2006.286.05:25:39.43#ibcon#end of sib2, iclass 30, count 2 2006.286.05:25:39.43#ibcon#*mode == 0, iclass 30, count 2 2006.286.05:25:39.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.286.05:25:39.43#ibcon#[27=AT06-03\r\n] 2006.286.05:25:39.43#ibcon#*before write, iclass 30, count 2 2006.286.05:25:39.43#ibcon#enter sib2, iclass 30, count 2 2006.286.05:25:39.43#ibcon#flushed, iclass 30, count 2 2006.286.05:25:39.43#ibcon#about to write, iclass 30, count 2 2006.286.05:25:39.43#ibcon#wrote, iclass 30, count 2 2006.286.05:25:39.43#ibcon#about to read 3, iclass 30, count 2 2006.286.05:25:39.46#ibcon#read 3, iclass 30, count 2 2006.286.05:25:39.46#ibcon#about to read 4, iclass 30, count 2 2006.286.05:25:39.46#ibcon#read 4, iclass 30, count 2 2006.286.05:25:39.46#ibcon#about to read 5, iclass 30, count 2 2006.286.05:25:39.46#ibcon#read 5, iclass 30, count 2 2006.286.05:25:39.46#ibcon#about to read 6, iclass 30, count 2 2006.286.05:25:39.46#ibcon#read 6, iclass 30, count 2 2006.286.05:25:39.46#ibcon#end of sib2, iclass 30, count 2 2006.286.05:25:39.46#ibcon#*after write, iclass 30, count 2 2006.286.05:25:39.46#ibcon#*before return 0, iclass 30, count 2 2006.286.05:25:39.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.286.05:25:39.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.286.05:25:39.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.286.05:25:39.46#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:39.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.05:25:39.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.286.05:25:39.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.05:25:39.58#ibcon#enter wrdev, iclass 30, count 0 2006.286.05:25:39.58#ibcon#first serial, iclass 30, count 0 2006.286.05:25:39.58#ibcon#enter sib2, iclass 30, count 0 2006.286.05:25:39.58#ibcon#flushed, iclass 30, count 0 2006.286.05:25:39.58#ibcon#about to write, iclass 30, count 0 2006.286.05:25:39.58#ibcon#wrote, iclass 30, count 0 2006.286.05:25:39.58#ibcon#about to read 3, iclass 30, count 0 2006.286.05:25:39.60#ibcon#read 3, iclass 30, count 0 2006.286.05:25:39.60#ibcon#about to read 4, iclass 30, count 0 2006.286.05:25:39.60#ibcon#read 4, iclass 30, count 0 2006.286.05:25:39.60#ibcon#about to read 5, iclass 30, count 0 2006.286.05:25:39.60#ibcon#read 5, iclass 30, count 0 2006.286.05:25:39.60#ibcon#about to read 6, iclass 30, count 0 2006.286.05:25:39.60#ibcon#read 6, iclass 30, count 0 2006.286.05:25:39.60#ibcon#end of sib2, iclass 30, count 0 2006.286.05:25:39.60#ibcon#*mode == 0, iclass 30, count 0 2006.286.05:25:39.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.05:25:39.60#ibcon#[27=USB\r\n] 2006.286.05:25:39.60#ibcon#*before write, iclass 30, count 0 2006.286.05:25:39.60#ibcon#enter sib2, iclass 30, count 0 2006.286.05:25:39.60#ibcon#flushed, iclass 30, count 0 2006.286.05:25:39.60#ibcon#about to write, iclass 30, count 0 2006.286.05:25:39.60#ibcon#wrote, iclass 30, count 0 2006.286.05:25:39.60#ibcon#about to read 3, iclass 30, count 0 2006.286.05:25:39.63#ibcon#read 3, iclass 30, count 0 2006.286.05:25:39.63#ibcon#about to read 4, iclass 30, count 0 2006.286.05:25:39.63#ibcon#read 4, iclass 30, count 0 2006.286.05:25:39.63#ibcon#about to read 5, iclass 30, count 0 2006.286.05:25:39.63#ibcon#read 5, iclass 30, count 0 2006.286.05:25:39.63#ibcon#about to read 6, iclass 30, count 0 2006.286.05:25:39.63#ibcon#read 6, iclass 30, count 0 2006.286.05:25:39.63#ibcon#end of sib2, iclass 30, count 0 2006.286.05:25:39.63#ibcon#*after write, iclass 30, count 0 2006.286.05:25:39.63#ibcon#*before return 0, iclass 30, count 0 2006.286.05:25:39.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.286.05:25:39.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.286.05:25:39.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.05:25:39.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.05:25:39.63$vck44/vblo=7,734.99 2006.286.05:25:39.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.286.05:25:39.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.286.05:25:39.63#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:39.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.05:25:39.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.286.05:25:39.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.05:25:39.63#ibcon#enter wrdev, iclass 32, count 0 2006.286.05:25:39.63#ibcon#first serial, iclass 32, count 0 2006.286.05:25:39.63#ibcon#enter sib2, iclass 32, count 0 2006.286.05:25:39.63#ibcon#flushed, iclass 32, count 0 2006.286.05:25:39.63#ibcon#about to write, iclass 32, count 0 2006.286.05:25:39.63#ibcon#wrote, iclass 32, count 0 2006.286.05:25:39.63#ibcon#about to read 3, iclass 32, count 0 2006.286.05:25:39.65#ibcon#read 3, iclass 32, count 0 2006.286.05:25:39.65#ibcon#about to read 4, iclass 32, count 0 2006.286.05:25:39.65#ibcon#read 4, iclass 32, count 0 2006.286.05:25:39.65#ibcon#about to read 5, iclass 32, count 0 2006.286.05:25:39.65#ibcon#read 5, iclass 32, count 0 2006.286.05:25:39.65#ibcon#about to read 6, iclass 32, count 0 2006.286.05:25:39.65#ibcon#read 6, iclass 32, count 0 2006.286.05:25:39.65#ibcon#end of sib2, iclass 32, count 0 2006.286.05:25:39.65#ibcon#*mode == 0, iclass 32, count 0 2006.286.05:25:39.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.05:25:39.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.05:25:39.65#ibcon#*before write, iclass 32, count 0 2006.286.05:25:39.65#ibcon#enter sib2, iclass 32, count 0 2006.286.05:25:39.65#ibcon#flushed, iclass 32, count 0 2006.286.05:25:39.65#ibcon#about to write, iclass 32, count 0 2006.286.05:25:39.65#ibcon#wrote, iclass 32, count 0 2006.286.05:25:39.65#ibcon#about to read 3, iclass 32, count 0 2006.286.05:25:39.69#ibcon#read 3, iclass 32, count 0 2006.286.05:25:39.69#ibcon#about to read 4, iclass 32, count 0 2006.286.05:25:39.69#ibcon#read 4, iclass 32, count 0 2006.286.05:25:39.69#ibcon#about to read 5, iclass 32, count 0 2006.286.05:25:39.69#ibcon#read 5, iclass 32, count 0 2006.286.05:25:39.69#ibcon#about to read 6, iclass 32, count 0 2006.286.05:25:39.69#ibcon#read 6, iclass 32, count 0 2006.286.05:25:39.69#ibcon#end of sib2, iclass 32, count 0 2006.286.05:25:39.69#ibcon#*after write, iclass 32, count 0 2006.286.05:25:39.69#ibcon#*before return 0, iclass 32, count 0 2006.286.05:25:39.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.286.05:25:39.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.286.05:25:39.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.05:25:39.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.05:25:39.69$vck44/vb=7,4 2006.286.05:25:39.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.286.05:25:39.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.286.05:25:39.69#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:39.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.05:25:39.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.286.05:25:39.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.05:25:39.75#ibcon#enter wrdev, iclass 34, count 2 2006.286.05:25:39.75#ibcon#first serial, iclass 34, count 2 2006.286.05:25:39.75#ibcon#enter sib2, iclass 34, count 2 2006.286.05:25:39.75#ibcon#flushed, iclass 34, count 2 2006.286.05:25:39.75#ibcon#about to write, iclass 34, count 2 2006.286.05:25:39.75#ibcon#wrote, iclass 34, count 2 2006.286.05:25:39.75#ibcon#about to read 3, iclass 34, count 2 2006.286.05:25:39.77#ibcon#read 3, iclass 34, count 2 2006.286.05:25:39.77#ibcon#about to read 4, iclass 34, count 2 2006.286.05:25:39.77#ibcon#read 4, iclass 34, count 2 2006.286.05:25:39.77#ibcon#about to read 5, iclass 34, count 2 2006.286.05:25:39.77#ibcon#read 5, iclass 34, count 2 2006.286.05:25:39.77#ibcon#about to read 6, iclass 34, count 2 2006.286.05:25:39.77#ibcon#read 6, iclass 34, count 2 2006.286.05:25:39.77#ibcon#end of sib2, iclass 34, count 2 2006.286.05:25:39.77#ibcon#*mode == 0, iclass 34, count 2 2006.286.05:25:39.77#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.286.05:25:39.77#ibcon#[27=AT07-04\r\n] 2006.286.05:25:39.77#ibcon#*before write, iclass 34, count 2 2006.286.05:25:39.77#ibcon#enter sib2, iclass 34, count 2 2006.286.05:25:39.77#ibcon#flushed, iclass 34, count 2 2006.286.05:25:39.77#ibcon#about to write, iclass 34, count 2 2006.286.05:25:39.77#ibcon#wrote, iclass 34, count 2 2006.286.05:25:39.77#ibcon#about to read 3, iclass 34, count 2 2006.286.05:25:39.80#ibcon#read 3, iclass 34, count 2 2006.286.05:25:39.80#ibcon#about to read 4, iclass 34, count 2 2006.286.05:25:39.80#ibcon#read 4, iclass 34, count 2 2006.286.05:25:39.80#ibcon#about to read 5, iclass 34, count 2 2006.286.05:25:39.80#ibcon#read 5, iclass 34, count 2 2006.286.05:25:39.80#ibcon#about to read 6, iclass 34, count 2 2006.286.05:25:39.80#ibcon#read 6, iclass 34, count 2 2006.286.05:25:39.80#ibcon#end of sib2, iclass 34, count 2 2006.286.05:25:39.80#ibcon#*after write, iclass 34, count 2 2006.286.05:25:39.80#ibcon#*before return 0, iclass 34, count 2 2006.286.05:25:39.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.286.05:25:39.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.286.05:25:39.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.286.05:25:39.80#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:39.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.05:25:39.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.286.05:25:39.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.05:25:39.92#ibcon#enter wrdev, iclass 34, count 0 2006.286.05:25:39.92#ibcon#first serial, iclass 34, count 0 2006.286.05:25:39.92#ibcon#enter sib2, iclass 34, count 0 2006.286.05:25:39.92#ibcon#flushed, iclass 34, count 0 2006.286.05:25:39.92#ibcon#about to write, iclass 34, count 0 2006.286.05:25:39.92#ibcon#wrote, iclass 34, count 0 2006.286.05:25:39.92#ibcon#about to read 3, iclass 34, count 0 2006.286.05:25:39.94#ibcon#read 3, iclass 34, count 0 2006.286.05:25:39.94#ibcon#about to read 4, iclass 34, count 0 2006.286.05:25:39.94#ibcon#read 4, iclass 34, count 0 2006.286.05:25:39.94#ibcon#about to read 5, iclass 34, count 0 2006.286.05:25:39.94#ibcon#read 5, iclass 34, count 0 2006.286.05:25:39.94#ibcon#about to read 6, iclass 34, count 0 2006.286.05:25:39.94#ibcon#read 6, iclass 34, count 0 2006.286.05:25:39.95#ibcon#end of sib2, iclass 34, count 0 2006.286.05:25:39.95#ibcon#*mode == 0, iclass 34, count 0 2006.286.05:25:39.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.05:25:39.95#ibcon#[27=USB\r\n] 2006.286.05:25:39.95#ibcon#*before write, iclass 34, count 0 2006.286.05:25:39.95#ibcon#enter sib2, iclass 34, count 0 2006.286.05:25:39.95#ibcon#flushed, iclass 34, count 0 2006.286.05:25:39.95#ibcon#about to write, iclass 34, count 0 2006.286.05:25:39.95#ibcon#wrote, iclass 34, count 0 2006.286.05:25:39.95#ibcon#about to read 3, iclass 34, count 0 2006.286.05:25:39.98#ibcon#read 3, iclass 34, count 0 2006.286.05:25:39.98#ibcon#about to read 4, iclass 34, count 0 2006.286.05:25:39.98#ibcon#read 4, iclass 34, count 0 2006.286.05:25:39.98#ibcon#about to read 5, iclass 34, count 0 2006.286.05:25:39.98#ibcon#read 5, iclass 34, count 0 2006.286.05:25:39.98#ibcon#about to read 6, iclass 34, count 0 2006.286.05:25:39.98#ibcon#read 6, iclass 34, count 0 2006.286.05:25:39.98#ibcon#end of sib2, iclass 34, count 0 2006.286.05:25:39.98#ibcon#*after write, iclass 34, count 0 2006.286.05:25:39.98#ibcon#*before return 0, iclass 34, count 0 2006.286.05:25:39.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.286.05:25:39.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.286.05:25:39.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.05:25:39.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.05:25:39.98$vck44/vblo=8,744.99 2006.286.05:25:39.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.286.05:25:39.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.286.05:25:39.98#ibcon#ireg 17 cls_cnt 0 2006.286.05:25:39.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.05:25:39.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.286.05:25:39.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.05:25:39.98#ibcon#enter wrdev, iclass 36, count 0 2006.286.05:25:39.98#ibcon#first serial, iclass 36, count 0 2006.286.05:25:39.98#ibcon#enter sib2, iclass 36, count 0 2006.286.05:25:39.98#ibcon#flushed, iclass 36, count 0 2006.286.05:25:39.98#ibcon#about to write, iclass 36, count 0 2006.286.05:25:39.98#ibcon#wrote, iclass 36, count 0 2006.286.05:25:39.98#ibcon#about to read 3, iclass 36, count 0 2006.286.05:25:40.00#ibcon#read 3, iclass 36, count 0 2006.286.05:25:40.00#ibcon#about to read 4, iclass 36, count 0 2006.286.05:25:40.00#ibcon#read 4, iclass 36, count 0 2006.286.05:25:40.00#ibcon#about to read 5, iclass 36, count 0 2006.286.05:25:40.00#ibcon#read 5, iclass 36, count 0 2006.286.05:25:40.00#ibcon#about to read 6, iclass 36, count 0 2006.286.05:25:40.00#ibcon#read 6, iclass 36, count 0 2006.286.05:25:40.00#ibcon#end of sib2, iclass 36, count 0 2006.286.05:25:40.00#ibcon#*mode == 0, iclass 36, count 0 2006.286.05:25:40.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.05:25:40.00#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.05:25:40.00#ibcon#*before write, iclass 36, count 0 2006.286.05:25:40.00#ibcon#enter sib2, iclass 36, count 0 2006.286.05:25:40.00#ibcon#flushed, iclass 36, count 0 2006.286.05:25:40.00#ibcon#about to write, iclass 36, count 0 2006.286.05:25:40.00#ibcon#wrote, iclass 36, count 0 2006.286.05:25:40.00#ibcon#about to read 3, iclass 36, count 0 2006.286.05:25:40.04#ibcon#read 3, iclass 36, count 0 2006.286.05:25:40.04#ibcon#about to read 4, iclass 36, count 0 2006.286.05:25:40.04#ibcon#read 4, iclass 36, count 0 2006.286.05:25:40.04#ibcon#about to read 5, iclass 36, count 0 2006.286.05:25:40.04#ibcon#read 5, iclass 36, count 0 2006.286.05:25:40.04#ibcon#about to read 6, iclass 36, count 0 2006.286.05:25:40.04#ibcon#read 6, iclass 36, count 0 2006.286.05:25:40.04#ibcon#end of sib2, iclass 36, count 0 2006.286.05:25:40.04#ibcon#*after write, iclass 36, count 0 2006.286.05:25:40.04#ibcon#*before return 0, iclass 36, count 0 2006.286.05:25:40.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.286.05:25:40.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.286.05:25:40.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.05:25:40.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.05:25:40.04$vck44/vb=8,4 2006.286.05:25:40.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.286.05:25:40.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.286.05:25:40.04#ibcon#ireg 11 cls_cnt 2 2006.286.05:25:40.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.05:25:40.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.286.05:25:40.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.05:25:40.10#ibcon#enter wrdev, iclass 38, count 2 2006.286.05:25:40.10#ibcon#first serial, iclass 38, count 2 2006.286.05:25:40.10#ibcon#enter sib2, iclass 38, count 2 2006.286.05:25:40.10#ibcon#flushed, iclass 38, count 2 2006.286.05:25:40.10#ibcon#about to write, iclass 38, count 2 2006.286.05:25:40.10#ibcon#wrote, iclass 38, count 2 2006.286.05:25:40.10#ibcon#about to read 3, iclass 38, count 2 2006.286.05:25:40.12#ibcon#read 3, iclass 38, count 2 2006.286.05:25:40.12#ibcon#about to read 4, iclass 38, count 2 2006.286.05:25:40.12#ibcon#read 4, iclass 38, count 2 2006.286.05:25:40.12#ibcon#about to read 5, iclass 38, count 2 2006.286.05:25:40.12#ibcon#read 5, iclass 38, count 2 2006.286.05:25:40.12#ibcon#about to read 6, iclass 38, count 2 2006.286.05:25:40.12#ibcon#read 6, iclass 38, count 2 2006.286.05:25:40.12#ibcon#end of sib2, iclass 38, count 2 2006.286.05:25:40.12#ibcon#*mode == 0, iclass 38, count 2 2006.286.05:25:40.12#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.286.05:25:40.12#ibcon#[27=AT08-04\r\n] 2006.286.05:25:40.12#ibcon#*before write, iclass 38, count 2 2006.286.05:25:40.12#ibcon#enter sib2, iclass 38, count 2 2006.286.05:25:40.12#ibcon#flushed, iclass 38, count 2 2006.286.05:25:40.12#ibcon#about to write, iclass 38, count 2 2006.286.05:25:40.12#ibcon#wrote, iclass 38, count 2 2006.286.05:25:40.12#ibcon#about to read 3, iclass 38, count 2 2006.286.05:25:40.15#ibcon#read 3, iclass 38, count 2 2006.286.05:25:40.15#ibcon#about to read 4, iclass 38, count 2 2006.286.05:25:40.15#ibcon#read 4, iclass 38, count 2 2006.286.05:25:40.15#ibcon#about to read 5, iclass 38, count 2 2006.286.05:25:40.15#ibcon#read 5, iclass 38, count 2 2006.286.05:25:40.15#ibcon#about to read 6, iclass 38, count 2 2006.286.05:25:40.15#ibcon#read 6, iclass 38, count 2 2006.286.05:25:40.15#ibcon#end of sib2, iclass 38, count 2 2006.286.05:25:40.15#ibcon#*after write, iclass 38, count 2 2006.286.05:25:40.15#ibcon#*before return 0, iclass 38, count 2 2006.286.05:25:40.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.286.05:25:40.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.286.05:25:40.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.286.05:25:40.15#ibcon#ireg 7 cls_cnt 0 2006.286.05:25:40.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.05:25:40.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.286.05:25:40.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.05:25:40.27#ibcon#enter wrdev, iclass 38, count 0 2006.286.05:25:40.27#ibcon#first serial, iclass 38, count 0 2006.286.05:25:40.27#ibcon#enter sib2, iclass 38, count 0 2006.286.05:25:40.27#ibcon#flushed, iclass 38, count 0 2006.286.05:25:40.27#ibcon#about to write, iclass 38, count 0 2006.286.05:25:40.27#ibcon#wrote, iclass 38, count 0 2006.286.05:25:40.27#ibcon#about to read 3, iclass 38, count 0 2006.286.05:25:40.29#ibcon#read 3, iclass 38, count 0 2006.286.05:25:40.29#ibcon#about to read 4, iclass 38, count 0 2006.286.05:25:40.29#ibcon#read 4, iclass 38, count 0 2006.286.05:25:40.29#ibcon#about to read 5, iclass 38, count 0 2006.286.05:25:40.29#ibcon#read 5, iclass 38, count 0 2006.286.05:25:40.29#ibcon#about to read 6, iclass 38, count 0 2006.286.05:25:40.29#ibcon#read 6, iclass 38, count 0 2006.286.05:25:40.29#ibcon#end of sib2, iclass 38, count 0 2006.286.05:25:40.29#ibcon#*mode == 0, iclass 38, count 0 2006.286.05:25:40.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.05:25:40.29#ibcon#[27=USB\r\n] 2006.286.05:25:40.29#ibcon#*before write, iclass 38, count 0 2006.286.05:25:40.29#ibcon#enter sib2, iclass 38, count 0 2006.286.05:25:40.29#ibcon#flushed, iclass 38, count 0 2006.286.05:25:40.29#ibcon#about to write, iclass 38, count 0 2006.286.05:25:40.29#ibcon#wrote, iclass 38, count 0 2006.286.05:25:40.29#ibcon#about to read 3, iclass 38, count 0 2006.286.05:25:40.32#ibcon#read 3, iclass 38, count 0 2006.286.05:25:40.32#ibcon#about to read 4, iclass 38, count 0 2006.286.05:25:40.32#ibcon#read 4, iclass 38, count 0 2006.286.05:25:40.32#ibcon#about to read 5, iclass 38, count 0 2006.286.05:25:40.32#ibcon#read 5, iclass 38, count 0 2006.286.05:25:40.32#ibcon#about to read 6, iclass 38, count 0 2006.286.05:25:40.32#ibcon#read 6, iclass 38, count 0 2006.286.05:25:40.32#ibcon#end of sib2, iclass 38, count 0 2006.286.05:25:40.32#ibcon#*after write, iclass 38, count 0 2006.286.05:25:40.32#ibcon#*before return 0, iclass 38, count 0 2006.286.05:25:40.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.286.05:25:40.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.286.05:25:40.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.05:25:40.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.05:25:40.32$vck44/vabw=wide 2006.286.05:25:40.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.286.05:25:40.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.286.05:25:40.32#ibcon#ireg 8 cls_cnt 0 2006.286.05:25:40.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.05:25:40.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.286.05:25:40.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.05:25:40.32#ibcon#enter wrdev, iclass 40, count 0 2006.286.05:25:40.32#ibcon#first serial, iclass 40, count 0 2006.286.05:25:40.32#ibcon#enter sib2, iclass 40, count 0 2006.286.05:25:40.32#ibcon#flushed, iclass 40, count 0 2006.286.05:25:40.32#ibcon#about to write, iclass 40, count 0 2006.286.05:25:40.32#ibcon#wrote, iclass 40, count 0 2006.286.05:25:40.32#ibcon#about to read 3, iclass 40, count 0 2006.286.05:25:40.34#ibcon#read 3, iclass 40, count 0 2006.286.05:25:40.34#ibcon#about to read 4, iclass 40, count 0 2006.286.05:25:40.34#ibcon#read 4, iclass 40, count 0 2006.286.05:25:40.34#ibcon#about to read 5, iclass 40, count 0 2006.286.05:25:40.34#ibcon#read 5, iclass 40, count 0 2006.286.05:25:40.34#ibcon#about to read 6, iclass 40, count 0 2006.286.05:25:40.34#ibcon#read 6, iclass 40, count 0 2006.286.05:25:40.34#ibcon#end of sib2, iclass 40, count 0 2006.286.05:25:40.34#ibcon#*mode == 0, iclass 40, count 0 2006.286.05:25:40.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.05:25:40.34#ibcon#[25=BW32\r\n] 2006.286.05:25:40.34#ibcon#*before write, iclass 40, count 0 2006.286.05:25:40.34#ibcon#enter sib2, iclass 40, count 0 2006.286.05:25:40.34#ibcon#flushed, iclass 40, count 0 2006.286.05:25:40.34#ibcon#about to write, iclass 40, count 0 2006.286.05:25:40.34#ibcon#wrote, iclass 40, count 0 2006.286.05:25:40.34#ibcon#about to read 3, iclass 40, count 0 2006.286.05:25:40.37#ibcon#read 3, iclass 40, count 0 2006.286.05:25:40.37#ibcon#about to read 4, iclass 40, count 0 2006.286.05:25:40.37#ibcon#read 4, iclass 40, count 0 2006.286.05:25:40.37#ibcon#about to read 5, iclass 40, count 0 2006.286.05:25:40.37#ibcon#read 5, iclass 40, count 0 2006.286.05:25:40.37#ibcon#about to read 6, iclass 40, count 0 2006.286.05:25:40.37#ibcon#read 6, iclass 40, count 0 2006.286.05:25:40.37#ibcon#end of sib2, iclass 40, count 0 2006.286.05:25:40.37#ibcon#*after write, iclass 40, count 0 2006.286.05:25:40.37#ibcon#*before return 0, iclass 40, count 0 2006.286.05:25:40.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.286.05:25:40.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.286.05:25:40.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.05:25:40.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.05:25:40.37$vck44/vbbw=wide 2006.286.05:25:40.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.05:25:40.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.05:25:40.37#ibcon#ireg 8 cls_cnt 0 2006.286.05:25:40.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:25:40.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:25:40.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:25:40.44#ibcon#enter wrdev, iclass 4, count 0 2006.286.05:25:40.44#ibcon#first serial, iclass 4, count 0 2006.286.05:25:40.44#ibcon#enter sib2, iclass 4, count 0 2006.286.05:25:40.44#ibcon#flushed, iclass 4, count 0 2006.286.05:25:40.44#ibcon#about to write, iclass 4, count 0 2006.286.05:25:40.44#ibcon#wrote, iclass 4, count 0 2006.286.05:25:40.44#ibcon#about to read 3, iclass 4, count 0 2006.286.05:25:40.46#ibcon#read 3, iclass 4, count 0 2006.286.05:25:40.46#ibcon#about to read 4, iclass 4, count 0 2006.286.05:25:40.46#ibcon#read 4, iclass 4, count 0 2006.286.05:25:40.46#ibcon#about to read 5, iclass 4, count 0 2006.286.05:25:40.46#ibcon#read 5, iclass 4, count 0 2006.286.05:25:40.46#ibcon#about to read 6, iclass 4, count 0 2006.286.05:25:40.46#ibcon#read 6, iclass 4, count 0 2006.286.05:25:40.46#ibcon#end of sib2, iclass 4, count 0 2006.286.05:25:40.46#ibcon#*mode == 0, iclass 4, count 0 2006.286.05:25:40.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.05:25:40.46#ibcon#[27=BW32\r\n] 2006.286.05:25:40.46#ibcon#*before write, iclass 4, count 0 2006.286.05:25:40.46#ibcon#enter sib2, iclass 4, count 0 2006.286.05:25:40.46#ibcon#flushed, iclass 4, count 0 2006.286.05:25:40.46#ibcon#about to write, iclass 4, count 0 2006.286.05:25:40.46#ibcon#wrote, iclass 4, count 0 2006.286.05:25:40.46#ibcon#about to read 3, iclass 4, count 0 2006.286.05:25:40.49#ibcon#read 3, iclass 4, count 0 2006.286.05:25:40.49#ibcon#about to read 4, iclass 4, count 0 2006.286.05:25:40.49#ibcon#read 4, iclass 4, count 0 2006.286.05:25:40.49#ibcon#about to read 5, iclass 4, count 0 2006.286.05:25:40.49#ibcon#read 5, iclass 4, count 0 2006.286.05:25:40.49#ibcon#about to read 6, iclass 4, count 0 2006.286.05:25:40.49#ibcon#read 6, iclass 4, count 0 2006.286.05:25:40.49#ibcon#end of sib2, iclass 4, count 0 2006.286.05:25:40.49#ibcon#*after write, iclass 4, count 0 2006.286.05:25:40.49#ibcon#*before return 0, iclass 4, count 0 2006.286.05:25:40.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:25:40.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:25:40.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.05:25:40.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.05:25:40.49$setupk4/ifdk4 2006.286.05:25:40.49$ifdk4/lo= 2006.286.05:25:40.49$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.05:25:40.49$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.05:25:40.49$ifdk4/patch= 2006.286.05:25:40.49$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.05:25:40.49$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.05:25:40.49$setupk4/!*+20s 2006.286.05:25:41.41#abcon#<5=/04 4.2 7.7 21.35 781015.1\r\n> 2006.286.05:25:41.43#abcon#{5=INTERFACE CLEAR} 2006.286.05:25:41.49#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:25:46.14#trakl#Source acquired 2006.286.05:25:46.14#flagr#flagr/antenna,acquired 2006.286.05:25:51.58#abcon#<5=/04 4.2 7.7 21.35 791015.1\r\n> 2006.286.05:25:51.60#abcon#{5=INTERFACE CLEAR} 2006.286.05:25:51.66#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:25:54.27$setupk4/"tpicd 2006.286.05:25:54.27$setupk4/echo=off 2006.286.05:25:54.27$setupk4/xlog=off 2006.286.05:25:54.27:!2006.286.05:28:39 2006.286.05:28:39.00:preob 2006.286.05:28:39.14/onsource/TRACKING 2006.286.05:28:39.14:!2006.286.05:28:49 2006.286.05:28:49.00:"tape 2006.286.05:28:49.00:"st=record 2006.286.05:28:49.00:data_valid=on 2006.286.05:28:49.00:midob 2006.286.05:28:49.14/onsource/TRACKING 2006.286.05:28:49.14/wx/21.25,1015.1,79 2006.286.05:28:49.28/cable/+6.4922E-03 2006.286.05:28:50.37/va/01,07,usb,yes,32,35 2006.286.05:28:50.37/va/02,06,usb,yes,32,33 2006.286.05:28:50.37/va/03,07,usb,yes,32,34 2006.286.05:28:50.37/va/04,06,usb,yes,33,35 2006.286.05:28:50.37/va/05,03,usb,yes,33,33 2006.286.05:28:50.37/va/06,04,usb,yes,29,29 2006.286.05:28:50.37/va/07,04,usb,yes,30,31 2006.286.05:28:50.37/va/08,03,usb,yes,31,37 2006.286.05:28:50.60/valo/01,524.99,yes,locked 2006.286.05:28:50.60/valo/02,534.99,yes,locked 2006.286.05:28:50.60/valo/03,564.99,yes,locked 2006.286.05:28:50.60/valo/04,624.99,yes,locked 2006.286.05:28:50.60/valo/05,734.99,yes,locked 2006.286.05:28:50.60/valo/06,814.99,yes,locked 2006.286.05:28:50.60/valo/07,864.99,yes,locked 2006.286.05:28:50.60/valo/08,884.99,yes,locked 2006.286.05:28:51.69/vb/01,04,usb,yes,30,28 2006.286.05:28:51.69/vb/02,05,usb,yes,29,28 2006.286.05:28:51.69/vb/03,04,usb,yes,29,32 2006.286.05:28:51.69/vb/04,05,usb,yes,30,29 2006.286.05:28:51.69/vb/05,04,usb,yes,26,28 2006.286.05:28:51.69/vb/06,03,usb,yes,37,33 2006.286.05:28:51.69/vb/07,04,usb,yes,30,30 2006.286.05:28:51.69/vb/08,04,usb,yes,27,31 2006.286.05:28:51.93/vblo/01,629.99,yes,locked 2006.286.05:28:51.93/vblo/02,634.99,yes,locked 2006.286.05:28:51.93/vblo/03,649.99,yes,locked 2006.286.05:28:51.93/vblo/04,679.99,yes,locked 2006.286.05:28:51.93/vblo/05,709.99,yes,locked 2006.286.05:28:51.93/vblo/06,719.99,yes,locked 2006.286.05:28:51.93/vblo/07,734.99,yes,locked 2006.286.05:28:51.93/vblo/08,744.99,yes,locked 2006.286.05:28:52.08/vabw/8 2006.286.05:28:52.23/vbbw/8 2006.286.05:28:52.32/xfe/off,on,12.2 2006.286.05:28:52.69/ifatt/23,28,28,28 2006.286.05:28:53.08/fmout-gps/S +2.35E-07 2006.286.05:28:53.10:!2006.286.05:29:29 2006.286.05:29:29.01:data_valid=off 2006.286.05:29:29.01:"et 2006.286.05:29:29.01:!+3s 2006.286.05:29:32.02:"tape 2006.286.05:29:32.02:postob 2006.286.05:29:32.24/cable/+6.4915E-03 2006.286.05:29:32.24/wx/21.23,1015.1,79 2006.286.05:29:33.08/fmout-gps/S +2.33E-07 2006.286.05:29:33.08:scan_name=286-0530,jd0610,40 2006.286.05:29:33.08:source=1424-418,142756.30,-420619.4,2000.0,ccw 2006.286.05:29:34.14#flagr#flagr/antenna,new-source 2006.286.05:29:34.14:checkk5 2006.286.05:29:34.65/chk_autoobs//k5ts1/ autoobs is running! 2006.286.05:29:35.03/chk_autoobs//k5ts2/ autoobs is running! 2006.286.05:29:35.53/chk_autoobs//k5ts3/ autoobs is running! 2006.286.05:29:36.10/chk_autoobs//k5ts4/ autoobs is running! 2006.286.05:29:36.50/chk_obsdata//k5ts1/T2860528??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.05:29:37.05/chk_obsdata//k5ts2/T2860528??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.05:29:37.57/chk_obsdata//k5ts3/T2860528??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.05:29:37.95/chk_obsdata//k5ts4/T2860528??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.05:29:38.86/k5log//k5ts1_log_newline 2006.286.05:29:39.81/k5log//k5ts2_log_newline 2006.286.05:29:41.16/k5log//k5ts3_log_newline 2006.286.05:29:41.88/k5log//k5ts4_log_newline 2006.286.05:29:41.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.05:29:41.90:setupk4=1 2006.286.05:29:41.90$setupk4/echo=on 2006.286.05:29:41.90$setupk4/pcalon 2006.286.05:29:41.90$pcalon/"no phase cal control is implemented here 2006.286.05:29:41.90$setupk4/"tpicd=stop 2006.286.05:29:41.90$setupk4/"rec=synch_on 2006.286.05:29:41.90$setupk4/"rec_mode=128 2006.286.05:29:41.90$setupk4/!* 2006.286.05:29:41.90$setupk4/recpk4 2006.286.05:29:41.90$recpk4/recpatch= 2006.286.05:29:41.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.05:29:41.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.05:29:41.90$setupk4/vck44 2006.286.05:29:41.90$vck44/valo=1,524.99 2006.286.05:29:41.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.286.05:29:41.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.286.05:29:41.90#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:41.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:29:41.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:29:41.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:29:41.90#ibcon#enter wrdev, iclass 35, count 0 2006.286.05:29:41.90#ibcon#first serial, iclass 35, count 0 2006.286.05:29:41.90#ibcon#enter sib2, iclass 35, count 0 2006.286.05:29:41.90#ibcon#flushed, iclass 35, count 0 2006.286.05:29:41.90#ibcon#about to write, iclass 35, count 0 2006.286.05:29:41.90#ibcon#wrote, iclass 35, count 0 2006.286.05:29:41.90#ibcon#about to read 3, iclass 35, count 0 2006.286.05:29:41.92#ibcon#read 3, iclass 35, count 0 2006.286.05:29:41.92#ibcon#about to read 4, iclass 35, count 0 2006.286.05:29:41.92#ibcon#read 4, iclass 35, count 0 2006.286.05:29:41.92#ibcon#about to read 5, iclass 35, count 0 2006.286.05:29:41.92#ibcon#read 5, iclass 35, count 0 2006.286.05:29:41.92#ibcon#about to read 6, iclass 35, count 0 2006.286.05:29:41.92#ibcon#read 6, iclass 35, count 0 2006.286.05:29:41.92#ibcon#end of sib2, iclass 35, count 0 2006.286.05:29:41.92#ibcon#*mode == 0, iclass 35, count 0 2006.286.05:29:41.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.05:29:41.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.05:29:41.92#ibcon#*before write, iclass 35, count 0 2006.286.05:29:41.92#ibcon#enter sib2, iclass 35, count 0 2006.286.05:29:41.92#ibcon#flushed, iclass 35, count 0 2006.286.05:29:41.92#ibcon#about to write, iclass 35, count 0 2006.286.05:29:41.92#ibcon#wrote, iclass 35, count 0 2006.286.05:29:41.92#ibcon#about to read 3, iclass 35, count 0 2006.286.05:29:41.97#ibcon#read 3, iclass 35, count 0 2006.286.05:29:41.97#ibcon#about to read 4, iclass 35, count 0 2006.286.05:29:41.97#ibcon#read 4, iclass 35, count 0 2006.286.05:29:41.97#ibcon#about to read 5, iclass 35, count 0 2006.286.05:29:41.97#ibcon#read 5, iclass 35, count 0 2006.286.05:29:41.97#ibcon#about to read 6, iclass 35, count 0 2006.286.05:29:41.97#ibcon#read 6, iclass 35, count 0 2006.286.05:29:41.97#ibcon#end of sib2, iclass 35, count 0 2006.286.05:29:41.97#ibcon#*after write, iclass 35, count 0 2006.286.05:29:41.97#ibcon#*before return 0, iclass 35, count 0 2006.286.05:29:41.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:29:41.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.286.05:29:41.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.05:29:41.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.05:29:41.97$vck44/va=1,7 2006.286.05:29:41.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.05:29:41.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.05:29:41.97#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:41.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:29:41.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:29:41.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:29:41.97#ibcon#enter wrdev, iclass 37, count 2 2006.286.05:29:41.97#ibcon#first serial, iclass 37, count 2 2006.286.05:29:41.97#ibcon#enter sib2, iclass 37, count 2 2006.286.05:29:41.97#ibcon#flushed, iclass 37, count 2 2006.286.05:29:41.97#ibcon#about to write, iclass 37, count 2 2006.286.05:29:41.97#ibcon#wrote, iclass 37, count 2 2006.286.05:29:41.97#ibcon#about to read 3, iclass 37, count 2 2006.286.05:29:41.99#ibcon#read 3, iclass 37, count 2 2006.286.05:29:41.99#ibcon#about to read 4, iclass 37, count 2 2006.286.05:29:41.99#ibcon#read 4, iclass 37, count 2 2006.286.05:29:41.99#ibcon#about to read 5, iclass 37, count 2 2006.286.05:29:41.99#ibcon#read 5, iclass 37, count 2 2006.286.05:29:41.99#ibcon#about to read 6, iclass 37, count 2 2006.286.05:29:41.99#ibcon#read 6, iclass 37, count 2 2006.286.05:29:41.99#ibcon#end of sib2, iclass 37, count 2 2006.286.05:29:41.99#ibcon#*mode == 0, iclass 37, count 2 2006.286.05:29:41.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.05:29:41.99#ibcon#[25=AT01-07\r\n] 2006.286.05:29:41.99#ibcon#*before write, iclass 37, count 2 2006.286.05:29:41.99#ibcon#enter sib2, iclass 37, count 2 2006.286.05:29:41.99#ibcon#flushed, iclass 37, count 2 2006.286.05:29:41.99#ibcon#about to write, iclass 37, count 2 2006.286.05:29:41.99#ibcon#wrote, iclass 37, count 2 2006.286.05:29:41.99#ibcon#about to read 3, iclass 37, count 2 2006.286.05:29:42.02#ibcon#read 3, iclass 37, count 2 2006.286.05:29:42.02#ibcon#about to read 4, iclass 37, count 2 2006.286.05:29:42.02#ibcon#read 4, iclass 37, count 2 2006.286.05:29:42.02#ibcon#about to read 5, iclass 37, count 2 2006.286.05:29:42.02#ibcon#read 5, iclass 37, count 2 2006.286.05:29:42.02#ibcon#about to read 6, iclass 37, count 2 2006.286.05:29:42.02#ibcon#read 6, iclass 37, count 2 2006.286.05:29:42.02#ibcon#end of sib2, iclass 37, count 2 2006.286.05:29:42.02#ibcon#*after write, iclass 37, count 2 2006.286.05:29:42.02#ibcon#*before return 0, iclass 37, count 2 2006.286.05:29:42.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:29:42.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:29:42.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.05:29:42.02#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:42.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:29:42.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:29:42.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:29:42.14#ibcon#enter wrdev, iclass 37, count 0 2006.286.05:29:42.14#ibcon#first serial, iclass 37, count 0 2006.286.05:29:42.14#ibcon#enter sib2, iclass 37, count 0 2006.286.05:29:42.14#ibcon#flushed, iclass 37, count 0 2006.286.05:29:42.14#ibcon#about to write, iclass 37, count 0 2006.286.05:29:42.14#ibcon#wrote, iclass 37, count 0 2006.286.05:29:42.14#ibcon#about to read 3, iclass 37, count 0 2006.286.05:29:42.16#ibcon#read 3, iclass 37, count 0 2006.286.05:29:42.16#ibcon#about to read 4, iclass 37, count 0 2006.286.05:29:42.16#ibcon#read 4, iclass 37, count 0 2006.286.05:29:42.16#ibcon#about to read 5, iclass 37, count 0 2006.286.05:29:42.16#ibcon#read 5, iclass 37, count 0 2006.286.05:29:42.16#ibcon#about to read 6, iclass 37, count 0 2006.286.05:29:42.16#ibcon#read 6, iclass 37, count 0 2006.286.05:29:42.16#ibcon#end of sib2, iclass 37, count 0 2006.286.05:29:42.16#ibcon#*mode == 0, iclass 37, count 0 2006.286.05:29:42.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.05:29:42.16#ibcon#[25=USB\r\n] 2006.286.05:29:42.16#ibcon#*before write, iclass 37, count 0 2006.286.05:29:42.16#ibcon#enter sib2, iclass 37, count 0 2006.286.05:29:42.16#ibcon#flushed, iclass 37, count 0 2006.286.05:29:42.16#ibcon#about to write, iclass 37, count 0 2006.286.05:29:42.16#ibcon#wrote, iclass 37, count 0 2006.286.05:29:42.16#ibcon#about to read 3, iclass 37, count 0 2006.286.05:29:42.19#ibcon#read 3, iclass 37, count 0 2006.286.05:29:42.19#ibcon#about to read 4, iclass 37, count 0 2006.286.05:29:42.19#ibcon#read 4, iclass 37, count 0 2006.286.05:29:42.19#ibcon#about to read 5, iclass 37, count 0 2006.286.05:29:42.19#ibcon#read 5, iclass 37, count 0 2006.286.05:29:42.19#ibcon#about to read 6, iclass 37, count 0 2006.286.05:29:42.19#ibcon#read 6, iclass 37, count 0 2006.286.05:29:42.19#ibcon#end of sib2, iclass 37, count 0 2006.286.05:29:42.19#ibcon#*after write, iclass 37, count 0 2006.286.05:29:42.19#ibcon#*before return 0, iclass 37, count 0 2006.286.05:29:42.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:29:42.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:29:42.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.05:29:42.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.05:29:42.19$vck44/valo=2,534.99 2006.286.05:29:42.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.05:29:42.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.05:29:42.19#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:42.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:29:42.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:29:42.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:29:42.19#ibcon#enter wrdev, iclass 39, count 0 2006.286.05:29:42.19#ibcon#first serial, iclass 39, count 0 2006.286.05:29:42.19#ibcon#enter sib2, iclass 39, count 0 2006.286.05:29:42.19#ibcon#flushed, iclass 39, count 0 2006.286.05:29:42.19#ibcon#about to write, iclass 39, count 0 2006.286.05:29:42.19#ibcon#wrote, iclass 39, count 0 2006.286.05:29:42.19#ibcon#about to read 3, iclass 39, count 0 2006.286.05:29:42.21#ibcon#read 3, iclass 39, count 0 2006.286.05:29:43.16#ibcon#about to read 4, iclass 39, count 0 2006.286.05:29:43.16#ibcon#read 4, iclass 39, count 0 2006.286.05:29:43.16#ibcon#about to read 5, iclass 39, count 0 2006.286.05:29:43.16#ibcon#read 5, iclass 39, count 0 2006.286.05:29:43.16#ibcon#about to read 6, iclass 39, count 0 2006.286.05:29:43.16#ibcon#read 6, iclass 39, count 0 2006.286.05:29:43.16#ibcon#end of sib2, iclass 39, count 0 2006.286.05:29:43.16#ibcon#*mode == 0, iclass 39, count 0 2006.286.05:29:43.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.05:29:43.16#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.05:29:43.16#ibcon#*before write, iclass 39, count 0 2006.286.05:29:43.16#ibcon#enter sib2, iclass 39, count 0 2006.286.05:29:43.16#ibcon#flushed, iclass 39, count 0 2006.286.05:29:43.16#ibcon#about to write, iclass 39, count 0 2006.286.05:29:43.16#ibcon#wrote, iclass 39, count 0 2006.286.05:29:43.16#ibcon#about to read 3, iclass 39, count 0 2006.286.05:29:43.20#ibcon#read 3, iclass 39, count 0 2006.286.05:29:43.20#ibcon#about to read 4, iclass 39, count 0 2006.286.05:29:43.20#ibcon#read 4, iclass 39, count 0 2006.286.05:29:43.20#ibcon#about to read 5, iclass 39, count 0 2006.286.05:29:43.20#ibcon#read 5, iclass 39, count 0 2006.286.05:29:43.20#ibcon#about to read 6, iclass 39, count 0 2006.286.05:29:43.20#ibcon#read 6, iclass 39, count 0 2006.286.05:29:43.20#ibcon#end of sib2, iclass 39, count 0 2006.286.05:29:43.20#ibcon#*after write, iclass 39, count 0 2006.286.05:29:43.20#ibcon#*before return 0, iclass 39, count 0 2006.286.05:29:43.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:29:43.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:29:43.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.05:29:43.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.05:29:43.20$vck44/va=2,6 2006.286.05:29:43.20#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.05:29:43.20#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.05:29:43.20#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:43.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:29:43.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:29:43.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:29:43.20#ibcon#enter wrdev, iclass 3, count 2 2006.286.05:29:43.20#ibcon#first serial, iclass 3, count 2 2006.286.05:29:43.20#ibcon#enter sib2, iclass 3, count 2 2006.286.05:29:43.20#ibcon#flushed, iclass 3, count 2 2006.286.05:29:43.20#ibcon#about to write, iclass 3, count 2 2006.286.05:29:43.20#ibcon#wrote, iclass 3, count 2 2006.286.05:29:43.20#ibcon#about to read 3, iclass 3, count 2 2006.286.05:29:43.22#ibcon#read 3, iclass 3, count 2 2006.286.05:29:43.22#ibcon#about to read 4, iclass 3, count 2 2006.286.05:29:43.22#ibcon#read 4, iclass 3, count 2 2006.286.05:29:43.22#ibcon#about to read 5, iclass 3, count 2 2006.286.05:29:43.22#ibcon#read 5, iclass 3, count 2 2006.286.05:29:43.22#ibcon#about to read 6, iclass 3, count 2 2006.286.05:29:43.22#ibcon#read 6, iclass 3, count 2 2006.286.05:29:43.22#ibcon#end of sib2, iclass 3, count 2 2006.286.05:29:43.22#ibcon#*mode == 0, iclass 3, count 2 2006.286.05:29:43.22#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.05:29:43.22#ibcon#[25=AT02-06\r\n] 2006.286.05:29:43.22#ibcon#*before write, iclass 3, count 2 2006.286.05:29:43.22#ibcon#enter sib2, iclass 3, count 2 2006.286.05:29:43.22#ibcon#flushed, iclass 3, count 2 2006.286.05:29:43.22#ibcon#about to write, iclass 3, count 2 2006.286.05:29:43.22#ibcon#wrote, iclass 3, count 2 2006.286.05:29:43.22#ibcon#about to read 3, iclass 3, count 2 2006.286.05:29:43.25#ibcon#read 3, iclass 3, count 2 2006.286.05:29:43.25#ibcon#about to read 4, iclass 3, count 2 2006.286.05:29:43.25#ibcon#read 4, iclass 3, count 2 2006.286.05:29:43.25#ibcon#about to read 5, iclass 3, count 2 2006.286.05:29:43.25#ibcon#read 5, iclass 3, count 2 2006.286.05:29:43.25#ibcon#about to read 6, iclass 3, count 2 2006.286.05:29:43.25#ibcon#read 6, iclass 3, count 2 2006.286.05:29:43.25#ibcon#end of sib2, iclass 3, count 2 2006.286.05:29:43.25#ibcon#*after write, iclass 3, count 2 2006.286.05:29:43.25#ibcon#*before return 0, iclass 3, count 2 2006.286.05:29:43.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:29:43.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:29:43.25#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.05:29:43.25#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:43.25#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:29:43.37#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:29:43.37#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:29:43.37#ibcon#enter wrdev, iclass 3, count 0 2006.286.05:29:43.37#ibcon#first serial, iclass 3, count 0 2006.286.05:29:43.37#ibcon#enter sib2, iclass 3, count 0 2006.286.05:29:43.37#ibcon#flushed, iclass 3, count 0 2006.286.05:29:43.37#ibcon#about to write, iclass 3, count 0 2006.286.05:29:43.37#ibcon#wrote, iclass 3, count 0 2006.286.05:29:43.37#ibcon#about to read 3, iclass 3, count 0 2006.286.05:29:43.39#ibcon#read 3, iclass 3, count 0 2006.286.05:29:43.39#ibcon#about to read 4, iclass 3, count 0 2006.286.05:29:43.39#ibcon#read 4, iclass 3, count 0 2006.286.05:29:43.39#ibcon#about to read 5, iclass 3, count 0 2006.286.05:29:43.39#ibcon#read 5, iclass 3, count 0 2006.286.05:29:43.39#ibcon#about to read 6, iclass 3, count 0 2006.286.05:29:43.39#ibcon#read 6, iclass 3, count 0 2006.286.05:29:43.39#ibcon#end of sib2, iclass 3, count 0 2006.286.05:29:43.39#ibcon#*mode == 0, iclass 3, count 0 2006.286.05:29:43.39#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.05:29:43.39#ibcon#[25=USB\r\n] 2006.286.05:29:43.39#ibcon#*before write, iclass 3, count 0 2006.286.05:29:43.39#ibcon#enter sib2, iclass 3, count 0 2006.286.05:29:43.39#ibcon#flushed, iclass 3, count 0 2006.286.05:29:43.39#ibcon#about to write, iclass 3, count 0 2006.286.05:29:43.39#ibcon#wrote, iclass 3, count 0 2006.286.05:29:43.39#ibcon#about to read 3, iclass 3, count 0 2006.286.05:29:43.42#ibcon#read 3, iclass 3, count 0 2006.286.05:29:43.42#ibcon#about to read 4, iclass 3, count 0 2006.286.05:29:43.42#ibcon#read 4, iclass 3, count 0 2006.286.05:29:43.42#ibcon#about to read 5, iclass 3, count 0 2006.286.05:29:43.42#ibcon#read 5, iclass 3, count 0 2006.286.05:29:43.42#ibcon#about to read 6, iclass 3, count 0 2006.286.05:29:43.42#ibcon#read 6, iclass 3, count 0 2006.286.05:29:43.42#ibcon#end of sib2, iclass 3, count 0 2006.286.05:29:43.42#ibcon#*after write, iclass 3, count 0 2006.286.05:29:43.42#ibcon#*before return 0, iclass 3, count 0 2006.286.05:29:43.42#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:29:43.42#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:29:43.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.05:29:43.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.05:29:43.42$vck44/valo=3,564.99 2006.286.05:29:43.42#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.05:29:43.42#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.05:29:43.42#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:43.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:29:43.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:29:43.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:29:43.42#ibcon#enter wrdev, iclass 5, count 0 2006.286.05:29:43.42#ibcon#first serial, iclass 5, count 0 2006.286.05:29:43.42#ibcon#enter sib2, iclass 5, count 0 2006.286.05:29:43.42#ibcon#flushed, iclass 5, count 0 2006.286.05:29:43.42#ibcon#about to write, iclass 5, count 0 2006.286.05:29:43.42#ibcon#wrote, iclass 5, count 0 2006.286.05:29:43.42#ibcon#about to read 3, iclass 5, count 0 2006.286.05:29:43.44#ibcon#read 3, iclass 5, count 0 2006.286.05:29:43.70#ibcon#about to read 4, iclass 5, count 0 2006.286.05:29:43.70#ibcon#read 4, iclass 5, count 0 2006.286.05:29:43.70#ibcon#about to read 5, iclass 5, count 0 2006.286.05:29:43.70#ibcon#read 5, iclass 5, count 0 2006.286.05:29:43.70#ibcon#about to read 6, iclass 5, count 0 2006.286.05:29:43.70#ibcon#read 6, iclass 5, count 0 2006.286.05:29:43.70#ibcon#end of sib2, iclass 5, count 0 2006.286.05:29:43.70#ibcon#*mode == 0, iclass 5, count 0 2006.286.05:29:43.70#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.05:29:43.70#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.05:29:43.70#ibcon#*before write, iclass 5, count 0 2006.286.05:29:43.70#ibcon#enter sib2, iclass 5, count 0 2006.286.05:29:43.70#ibcon#flushed, iclass 5, count 0 2006.286.05:29:43.70#ibcon#about to write, iclass 5, count 0 2006.286.05:29:43.70#ibcon#wrote, iclass 5, count 0 2006.286.05:29:43.70#ibcon#about to read 3, iclass 5, count 0 2006.286.05:29:43.75#ibcon#read 3, iclass 5, count 0 2006.286.05:29:43.75#ibcon#about to read 4, iclass 5, count 0 2006.286.05:29:43.75#ibcon#read 4, iclass 5, count 0 2006.286.05:29:43.75#ibcon#about to read 5, iclass 5, count 0 2006.286.05:29:43.75#ibcon#read 5, iclass 5, count 0 2006.286.05:29:43.75#ibcon#about to read 6, iclass 5, count 0 2006.286.05:29:43.75#ibcon#read 6, iclass 5, count 0 2006.286.05:29:43.75#ibcon#end of sib2, iclass 5, count 0 2006.286.05:29:43.75#ibcon#*after write, iclass 5, count 0 2006.286.05:29:43.75#ibcon#*before return 0, iclass 5, count 0 2006.286.05:29:43.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:29:43.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:29:43.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.05:29:43.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.05:29:43.75$vck44/va=3,7 2006.286.05:29:43.75#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.05:29:43.75#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.05:29:43.75#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:43.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:29:43.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:29:43.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:29:43.75#ibcon#enter wrdev, iclass 7, count 2 2006.286.05:29:43.75#ibcon#first serial, iclass 7, count 2 2006.286.05:29:43.75#ibcon#enter sib2, iclass 7, count 2 2006.286.05:29:43.75#ibcon#flushed, iclass 7, count 2 2006.286.05:29:43.75#ibcon#about to write, iclass 7, count 2 2006.286.05:29:43.75#ibcon#wrote, iclass 7, count 2 2006.286.05:29:43.75#ibcon#about to read 3, iclass 7, count 2 2006.286.05:29:43.77#ibcon#read 3, iclass 7, count 2 2006.286.05:29:43.77#ibcon#about to read 4, iclass 7, count 2 2006.286.05:29:43.77#ibcon#read 4, iclass 7, count 2 2006.286.05:29:43.77#ibcon#about to read 5, iclass 7, count 2 2006.286.05:29:43.77#ibcon#read 5, iclass 7, count 2 2006.286.05:29:43.77#ibcon#about to read 6, iclass 7, count 2 2006.286.05:29:43.77#ibcon#read 6, iclass 7, count 2 2006.286.05:29:43.77#ibcon#end of sib2, iclass 7, count 2 2006.286.05:29:43.77#ibcon#*mode == 0, iclass 7, count 2 2006.286.05:29:43.77#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.05:29:43.77#ibcon#[25=AT03-07\r\n] 2006.286.05:29:43.77#ibcon#*before write, iclass 7, count 2 2006.286.05:29:43.77#ibcon#enter sib2, iclass 7, count 2 2006.286.05:29:43.77#ibcon#flushed, iclass 7, count 2 2006.286.05:29:43.77#ibcon#about to write, iclass 7, count 2 2006.286.05:29:43.77#ibcon#wrote, iclass 7, count 2 2006.286.05:29:43.77#ibcon#about to read 3, iclass 7, count 2 2006.286.05:29:43.80#ibcon#read 3, iclass 7, count 2 2006.286.05:29:43.80#ibcon#about to read 4, iclass 7, count 2 2006.286.05:29:43.80#ibcon#read 4, iclass 7, count 2 2006.286.05:29:43.80#ibcon#about to read 5, iclass 7, count 2 2006.286.05:29:43.80#ibcon#read 5, iclass 7, count 2 2006.286.05:29:43.80#ibcon#about to read 6, iclass 7, count 2 2006.286.05:29:43.80#ibcon#read 6, iclass 7, count 2 2006.286.05:29:43.80#ibcon#end of sib2, iclass 7, count 2 2006.286.05:29:43.80#ibcon#*after write, iclass 7, count 2 2006.286.05:29:43.80#ibcon#*before return 0, iclass 7, count 2 2006.286.05:29:43.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:29:43.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:29:43.80#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.05:29:43.80#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:43.80#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:29:43.92#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:29:43.92#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:29:43.92#ibcon#enter wrdev, iclass 7, count 0 2006.286.05:29:43.92#ibcon#first serial, iclass 7, count 0 2006.286.05:29:43.92#ibcon#enter sib2, iclass 7, count 0 2006.286.05:29:43.92#ibcon#flushed, iclass 7, count 0 2006.286.05:29:43.92#ibcon#about to write, iclass 7, count 0 2006.286.05:29:43.92#ibcon#wrote, iclass 7, count 0 2006.286.05:29:43.92#ibcon#about to read 3, iclass 7, count 0 2006.286.05:29:43.94#ibcon#read 3, iclass 7, count 0 2006.286.05:29:43.94#ibcon#about to read 4, iclass 7, count 0 2006.286.05:29:43.94#ibcon#read 4, iclass 7, count 0 2006.286.05:29:43.94#ibcon#about to read 5, iclass 7, count 0 2006.286.05:29:43.94#ibcon#read 5, iclass 7, count 0 2006.286.05:29:43.94#ibcon#about to read 6, iclass 7, count 0 2006.286.05:29:43.94#ibcon#read 6, iclass 7, count 0 2006.286.05:29:43.94#ibcon#end of sib2, iclass 7, count 0 2006.286.05:29:43.94#ibcon#*mode == 0, iclass 7, count 0 2006.286.05:29:43.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.05:29:43.94#ibcon#[25=USB\r\n] 2006.286.05:29:43.94#ibcon#*before write, iclass 7, count 0 2006.286.05:29:43.94#ibcon#enter sib2, iclass 7, count 0 2006.286.05:29:43.94#ibcon#flushed, iclass 7, count 0 2006.286.05:29:43.94#ibcon#about to write, iclass 7, count 0 2006.286.05:29:43.94#ibcon#wrote, iclass 7, count 0 2006.286.05:29:43.94#ibcon#about to read 3, iclass 7, count 0 2006.286.05:29:43.97#ibcon#read 3, iclass 7, count 0 2006.286.05:29:43.97#ibcon#about to read 4, iclass 7, count 0 2006.286.05:29:43.97#ibcon#read 4, iclass 7, count 0 2006.286.05:29:43.97#ibcon#about to read 5, iclass 7, count 0 2006.286.05:29:43.97#ibcon#read 5, iclass 7, count 0 2006.286.05:29:43.97#ibcon#about to read 6, iclass 7, count 0 2006.286.05:29:43.97#ibcon#read 6, iclass 7, count 0 2006.286.05:29:43.97#ibcon#end of sib2, iclass 7, count 0 2006.286.05:29:43.97#ibcon#*after write, iclass 7, count 0 2006.286.05:29:43.97#ibcon#*before return 0, iclass 7, count 0 2006.286.05:29:43.97#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:29:43.97#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:29:43.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.05:29:43.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.05:29:43.97$vck44/valo=4,624.99 2006.286.05:29:43.97#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.05:29:43.97#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.05:29:43.97#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:43.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:29:43.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:29:43.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:29:43.97#ibcon#enter wrdev, iclass 11, count 0 2006.286.05:29:43.97#ibcon#first serial, iclass 11, count 0 2006.286.05:29:43.97#ibcon#enter sib2, iclass 11, count 0 2006.286.05:29:43.97#ibcon#flushed, iclass 11, count 0 2006.286.05:29:43.97#ibcon#about to write, iclass 11, count 0 2006.286.05:29:43.97#ibcon#wrote, iclass 11, count 0 2006.286.05:29:43.97#ibcon#about to read 3, iclass 11, count 0 2006.286.05:29:43.99#ibcon#read 3, iclass 11, count 0 2006.286.05:29:43.99#ibcon#about to read 4, iclass 11, count 0 2006.286.05:29:43.99#ibcon#read 4, iclass 11, count 0 2006.286.05:29:43.99#ibcon#about to read 5, iclass 11, count 0 2006.286.05:29:43.99#ibcon#read 5, iclass 11, count 0 2006.286.05:29:43.99#ibcon#about to read 6, iclass 11, count 0 2006.286.05:29:43.99#ibcon#read 6, iclass 11, count 0 2006.286.05:29:43.99#ibcon#end of sib2, iclass 11, count 0 2006.286.05:29:43.99#ibcon#*mode == 0, iclass 11, count 0 2006.286.05:29:43.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.05:29:43.99#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.05:29:43.99#ibcon#*before write, iclass 11, count 0 2006.286.05:29:43.99#ibcon#enter sib2, iclass 11, count 0 2006.286.05:29:43.99#ibcon#flushed, iclass 11, count 0 2006.286.05:29:43.99#ibcon#about to write, iclass 11, count 0 2006.286.05:29:43.99#ibcon#wrote, iclass 11, count 0 2006.286.05:29:43.99#ibcon#about to read 3, iclass 11, count 0 2006.286.05:29:44.03#ibcon#read 3, iclass 11, count 0 2006.286.05:29:44.03#ibcon#about to read 4, iclass 11, count 0 2006.286.05:29:44.03#ibcon#read 4, iclass 11, count 0 2006.286.05:29:44.03#ibcon#about to read 5, iclass 11, count 0 2006.286.05:29:44.03#ibcon#read 5, iclass 11, count 0 2006.286.05:29:44.03#ibcon#about to read 6, iclass 11, count 0 2006.286.05:29:44.03#ibcon#read 6, iclass 11, count 0 2006.286.05:29:44.03#ibcon#end of sib2, iclass 11, count 0 2006.286.05:29:44.03#ibcon#*after write, iclass 11, count 0 2006.286.05:29:44.03#ibcon#*before return 0, iclass 11, count 0 2006.286.05:29:44.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:29:44.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:29:44.03#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.05:29:44.03#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.05:29:44.03$vck44/va=4,6 2006.286.05:29:44.03#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.05:29:44.03#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.05:29:44.03#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:44.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:29:44.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:29:44.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:29:44.09#ibcon#enter wrdev, iclass 13, count 2 2006.286.05:29:44.09#ibcon#first serial, iclass 13, count 2 2006.286.05:29:44.09#ibcon#enter sib2, iclass 13, count 2 2006.286.05:29:44.09#ibcon#flushed, iclass 13, count 2 2006.286.05:29:44.09#ibcon#about to write, iclass 13, count 2 2006.286.05:29:44.09#ibcon#wrote, iclass 13, count 2 2006.286.05:29:44.09#ibcon#about to read 3, iclass 13, count 2 2006.286.05:29:44.11#ibcon#read 3, iclass 13, count 2 2006.286.05:29:44.11#ibcon#about to read 4, iclass 13, count 2 2006.286.05:29:44.11#ibcon#read 4, iclass 13, count 2 2006.286.05:29:44.11#ibcon#about to read 5, iclass 13, count 2 2006.286.05:29:44.11#ibcon#read 5, iclass 13, count 2 2006.286.05:29:44.11#ibcon#about to read 6, iclass 13, count 2 2006.286.05:29:44.11#ibcon#read 6, iclass 13, count 2 2006.286.05:29:44.11#ibcon#end of sib2, iclass 13, count 2 2006.286.05:29:44.11#ibcon#*mode == 0, iclass 13, count 2 2006.286.05:29:44.11#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.05:29:44.11#ibcon#[25=AT04-06\r\n] 2006.286.05:29:44.11#ibcon#*before write, iclass 13, count 2 2006.286.05:29:44.11#ibcon#enter sib2, iclass 13, count 2 2006.286.05:29:44.11#ibcon#flushed, iclass 13, count 2 2006.286.05:29:44.11#ibcon#about to write, iclass 13, count 2 2006.286.05:29:44.11#ibcon#wrote, iclass 13, count 2 2006.286.05:29:44.11#ibcon#about to read 3, iclass 13, count 2 2006.286.05:29:44.14#ibcon#read 3, iclass 13, count 2 2006.286.05:29:44.14#ibcon#about to read 4, iclass 13, count 2 2006.286.05:29:44.14#ibcon#read 4, iclass 13, count 2 2006.286.05:29:44.14#ibcon#about to read 5, iclass 13, count 2 2006.286.05:29:44.14#ibcon#read 5, iclass 13, count 2 2006.286.05:29:44.14#ibcon#about to read 6, iclass 13, count 2 2006.286.05:29:44.14#ibcon#read 6, iclass 13, count 2 2006.286.05:29:44.14#ibcon#end of sib2, iclass 13, count 2 2006.286.05:29:44.14#ibcon#*after write, iclass 13, count 2 2006.286.05:29:44.14#ibcon#*before return 0, iclass 13, count 2 2006.286.05:29:44.14#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:29:44.14#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:29:44.14#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.05:29:44.14#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:44.14#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:29:44.26#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:29:44.26#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:29:44.26#ibcon#enter wrdev, iclass 13, count 0 2006.286.05:29:44.26#ibcon#first serial, iclass 13, count 0 2006.286.05:29:44.26#ibcon#enter sib2, iclass 13, count 0 2006.286.05:29:44.26#ibcon#flushed, iclass 13, count 0 2006.286.05:29:44.26#ibcon#about to write, iclass 13, count 0 2006.286.05:29:44.26#ibcon#wrote, iclass 13, count 0 2006.286.05:29:44.26#ibcon#about to read 3, iclass 13, count 0 2006.286.05:29:44.28#ibcon#read 3, iclass 13, count 0 2006.286.05:29:44.28#ibcon#about to read 4, iclass 13, count 0 2006.286.05:29:44.28#ibcon#read 4, iclass 13, count 0 2006.286.05:29:44.28#ibcon#about to read 5, iclass 13, count 0 2006.286.05:29:44.28#ibcon#read 5, iclass 13, count 0 2006.286.05:29:44.28#ibcon#about to read 6, iclass 13, count 0 2006.286.05:29:44.28#ibcon#read 6, iclass 13, count 0 2006.286.05:29:44.28#ibcon#end of sib2, iclass 13, count 0 2006.286.05:29:44.28#ibcon#*mode == 0, iclass 13, count 0 2006.286.05:29:44.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.05:29:44.28#ibcon#[25=USB\r\n] 2006.286.05:29:44.28#ibcon#*before write, iclass 13, count 0 2006.286.05:29:44.28#ibcon#enter sib2, iclass 13, count 0 2006.286.05:29:44.28#ibcon#flushed, iclass 13, count 0 2006.286.05:29:44.28#ibcon#about to write, iclass 13, count 0 2006.286.05:29:44.28#ibcon#wrote, iclass 13, count 0 2006.286.05:29:44.28#ibcon#about to read 3, iclass 13, count 0 2006.286.05:29:44.31#ibcon#read 3, iclass 13, count 0 2006.286.05:29:44.31#ibcon#about to read 4, iclass 13, count 0 2006.286.05:29:44.31#ibcon#read 4, iclass 13, count 0 2006.286.05:29:44.31#ibcon#about to read 5, iclass 13, count 0 2006.286.05:29:44.31#ibcon#read 5, iclass 13, count 0 2006.286.05:29:44.31#ibcon#about to read 6, iclass 13, count 0 2006.286.05:29:44.31#ibcon#read 6, iclass 13, count 0 2006.286.05:29:44.31#ibcon#end of sib2, iclass 13, count 0 2006.286.05:29:44.31#ibcon#*after write, iclass 13, count 0 2006.286.05:29:44.31#ibcon#*before return 0, iclass 13, count 0 2006.286.05:29:44.31#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:29:44.31#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:29:44.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.05:29:44.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.05:29:44.31$vck44/valo=5,734.99 2006.286.05:29:44.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.05:29:44.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.05:29:44.31#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:44.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:29:44.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:29:44.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:29:44.31#ibcon#enter wrdev, iclass 15, count 0 2006.286.05:29:44.31#ibcon#first serial, iclass 15, count 0 2006.286.05:29:44.31#ibcon#enter sib2, iclass 15, count 0 2006.286.05:29:44.31#ibcon#flushed, iclass 15, count 0 2006.286.05:29:44.31#ibcon#about to write, iclass 15, count 0 2006.286.05:29:44.31#ibcon#wrote, iclass 15, count 0 2006.286.05:29:44.31#ibcon#about to read 3, iclass 15, count 0 2006.286.05:29:44.33#ibcon#read 3, iclass 15, count 0 2006.286.05:29:44.40#ibcon#about to read 4, iclass 15, count 0 2006.286.05:29:44.40#ibcon#read 4, iclass 15, count 0 2006.286.05:29:44.40#ibcon#about to read 5, iclass 15, count 0 2006.286.05:29:44.40#ibcon#read 5, iclass 15, count 0 2006.286.05:29:44.40#ibcon#about to read 6, iclass 15, count 0 2006.286.05:29:44.40#ibcon#read 6, iclass 15, count 0 2006.286.05:29:44.40#ibcon#end of sib2, iclass 15, count 0 2006.286.05:29:44.40#ibcon#*mode == 0, iclass 15, count 0 2006.286.05:29:44.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.05:29:44.40#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.05:29:44.40#ibcon#*before write, iclass 15, count 0 2006.286.05:29:44.40#ibcon#enter sib2, iclass 15, count 0 2006.286.05:29:44.40#ibcon#flushed, iclass 15, count 0 2006.286.05:29:44.40#ibcon#about to write, iclass 15, count 0 2006.286.05:29:44.40#ibcon#wrote, iclass 15, count 0 2006.286.05:29:44.40#ibcon#about to read 3, iclass 15, count 0 2006.286.05:29:44.45#ibcon#read 3, iclass 15, count 0 2006.286.05:29:44.45#ibcon#about to read 4, iclass 15, count 0 2006.286.05:29:44.45#ibcon#read 4, iclass 15, count 0 2006.286.05:29:44.45#ibcon#about to read 5, iclass 15, count 0 2006.286.05:29:44.45#ibcon#read 5, iclass 15, count 0 2006.286.05:29:44.45#ibcon#about to read 6, iclass 15, count 0 2006.286.05:29:44.45#ibcon#read 6, iclass 15, count 0 2006.286.05:29:44.45#ibcon#end of sib2, iclass 15, count 0 2006.286.05:29:44.45#ibcon#*after write, iclass 15, count 0 2006.286.05:29:44.45#ibcon#*before return 0, iclass 15, count 0 2006.286.05:29:44.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:29:44.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:29:44.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.05:29:44.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.05:29:44.45$vck44/va=5,3 2006.286.05:29:44.45#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.05:29:44.45#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.05:29:44.45#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:44.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:29:44.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:29:44.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:29:44.45#ibcon#enter wrdev, iclass 17, count 2 2006.286.05:29:44.45#ibcon#first serial, iclass 17, count 2 2006.286.05:29:44.45#ibcon#enter sib2, iclass 17, count 2 2006.286.05:29:44.45#ibcon#flushed, iclass 17, count 2 2006.286.05:29:44.45#ibcon#about to write, iclass 17, count 2 2006.286.05:29:44.45#ibcon#wrote, iclass 17, count 2 2006.286.05:29:44.45#ibcon#about to read 3, iclass 17, count 2 2006.286.05:29:44.47#ibcon#read 3, iclass 17, count 2 2006.286.05:29:44.47#ibcon#about to read 4, iclass 17, count 2 2006.286.05:29:44.47#ibcon#read 4, iclass 17, count 2 2006.286.05:29:44.47#ibcon#about to read 5, iclass 17, count 2 2006.286.05:29:44.47#ibcon#read 5, iclass 17, count 2 2006.286.05:29:44.47#ibcon#about to read 6, iclass 17, count 2 2006.286.05:29:44.47#ibcon#read 6, iclass 17, count 2 2006.286.05:29:44.47#ibcon#end of sib2, iclass 17, count 2 2006.286.05:29:44.47#ibcon#*mode == 0, iclass 17, count 2 2006.286.05:29:44.47#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.05:29:44.47#ibcon#[25=AT05-03\r\n] 2006.286.05:29:44.47#ibcon#*before write, iclass 17, count 2 2006.286.05:29:44.47#ibcon#enter sib2, iclass 17, count 2 2006.286.05:29:44.47#ibcon#flushed, iclass 17, count 2 2006.286.05:29:44.47#ibcon#about to write, iclass 17, count 2 2006.286.05:29:44.47#ibcon#wrote, iclass 17, count 2 2006.286.05:29:44.47#ibcon#about to read 3, iclass 17, count 2 2006.286.05:29:44.50#ibcon#read 3, iclass 17, count 2 2006.286.05:29:44.50#ibcon#about to read 4, iclass 17, count 2 2006.286.05:29:44.50#ibcon#read 4, iclass 17, count 2 2006.286.05:29:44.50#ibcon#about to read 5, iclass 17, count 2 2006.286.05:29:44.50#ibcon#read 5, iclass 17, count 2 2006.286.05:29:44.50#ibcon#about to read 6, iclass 17, count 2 2006.286.05:29:44.50#ibcon#read 6, iclass 17, count 2 2006.286.05:29:44.50#ibcon#end of sib2, iclass 17, count 2 2006.286.05:29:44.50#ibcon#*after write, iclass 17, count 2 2006.286.05:29:44.50#ibcon#*before return 0, iclass 17, count 2 2006.286.05:29:44.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:29:44.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:29:44.50#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.05:29:44.50#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:44.50#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:29:44.62#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:29:44.62#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:29:44.62#ibcon#enter wrdev, iclass 17, count 0 2006.286.05:29:44.62#ibcon#first serial, iclass 17, count 0 2006.286.05:29:44.62#ibcon#enter sib2, iclass 17, count 0 2006.286.05:29:44.62#ibcon#flushed, iclass 17, count 0 2006.286.05:29:44.62#ibcon#about to write, iclass 17, count 0 2006.286.05:29:44.62#ibcon#wrote, iclass 17, count 0 2006.286.05:29:44.62#ibcon#about to read 3, iclass 17, count 0 2006.286.05:29:44.64#ibcon#read 3, iclass 17, count 0 2006.286.05:29:44.64#ibcon#about to read 4, iclass 17, count 0 2006.286.05:29:44.64#ibcon#read 4, iclass 17, count 0 2006.286.05:29:44.64#ibcon#about to read 5, iclass 17, count 0 2006.286.05:29:44.64#ibcon#read 5, iclass 17, count 0 2006.286.05:29:44.64#ibcon#about to read 6, iclass 17, count 0 2006.286.05:29:44.64#ibcon#read 6, iclass 17, count 0 2006.286.05:29:44.64#ibcon#end of sib2, iclass 17, count 0 2006.286.05:29:44.64#ibcon#*mode == 0, iclass 17, count 0 2006.286.05:29:44.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.05:29:44.64#ibcon#[25=USB\r\n] 2006.286.05:29:44.64#ibcon#*before write, iclass 17, count 0 2006.286.05:29:44.64#ibcon#enter sib2, iclass 17, count 0 2006.286.05:29:44.64#ibcon#flushed, iclass 17, count 0 2006.286.05:29:44.64#ibcon#about to write, iclass 17, count 0 2006.286.05:29:44.64#ibcon#wrote, iclass 17, count 0 2006.286.05:29:44.64#ibcon#about to read 3, iclass 17, count 0 2006.286.05:29:44.67#ibcon#read 3, iclass 17, count 0 2006.286.05:29:44.67#ibcon#about to read 4, iclass 17, count 0 2006.286.05:29:44.67#ibcon#read 4, iclass 17, count 0 2006.286.05:29:44.67#ibcon#about to read 5, iclass 17, count 0 2006.286.05:29:44.67#ibcon#read 5, iclass 17, count 0 2006.286.05:29:44.67#ibcon#about to read 6, iclass 17, count 0 2006.286.05:29:44.67#ibcon#read 6, iclass 17, count 0 2006.286.05:29:44.67#ibcon#end of sib2, iclass 17, count 0 2006.286.05:29:44.67#ibcon#*after write, iclass 17, count 0 2006.286.05:29:44.67#ibcon#*before return 0, iclass 17, count 0 2006.286.05:29:44.67#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:29:44.67#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:29:44.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.05:29:44.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.05:29:44.67$vck44/valo=6,814.99 2006.286.05:29:44.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.05:29:44.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.05:29:44.67#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:44.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:29:44.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:29:44.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:29:44.67#ibcon#enter wrdev, iclass 19, count 0 2006.286.05:29:44.67#ibcon#first serial, iclass 19, count 0 2006.286.05:29:44.67#ibcon#enter sib2, iclass 19, count 0 2006.286.05:29:44.67#ibcon#flushed, iclass 19, count 0 2006.286.05:29:44.67#ibcon#about to write, iclass 19, count 0 2006.286.05:29:44.67#ibcon#wrote, iclass 19, count 0 2006.286.05:29:44.67#ibcon#about to read 3, iclass 19, count 0 2006.286.05:29:44.69#ibcon#read 3, iclass 19, count 0 2006.286.05:29:44.69#ibcon#about to read 4, iclass 19, count 0 2006.286.05:29:44.69#ibcon#read 4, iclass 19, count 0 2006.286.05:29:44.69#ibcon#about to read 5, iclass 19, count 0 2006.286.05:29:44.69#ibcon#read 5, iclass 19, count 0 2006.286.05:29:44.69#ibcon#about to read 6, iclass 19, count 0 2006.286.05:29:44.69#ibcon#read 6, iclass 19, count 0 2006.286.05:29:44.69#ibcon#end of sib2, iclass 19, count 0 2006.286.05:29:44.69#ibcon#*mode == 0, iclass 19, count 0 2006.286.05:29:44.69#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.05:29:44.69#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.05:29:44.69#ibcon#*before write, iclass 19, count 0 2006.286.05:29:44.69#ibcon#enter sib2, iclass 19, count 0 2006.286.05:29:44.69#ibcon#flushed, iclass 19, count 0 2006.286.05:29:44.69#ibcon#about to write, iclass 19, count 0 2006.286.05:29:44.69#ibcon#wrote, iclass 19, count 0 2006.286.05:29:44.69#ibcon#about to read 3, iclass 19, count 0 2006.286.05:29:44.73#ibcon#read 3, iclass 19, count 0 2006.286.05:29:44.73#ibcon#about to read 4, iclass 19, count 0 2006.286.05:29:44.73#ibcon#read 4, iclass 19, count 0 2006.286.05:29:44.73#ibcon#about to read 5, iclass 19, count 0 2006.286.05:29:44.73#ibcon#read 5, iclass 19, count 0 2006.286.05:29:44.73#ibcon#about to read 6, iclass 19, count 0 2006.286.05:29:44.73#ibcon#read 6, iclass 19, count 0 2006.286.05:29:44.73#ibcon#end of sib2, iclass 19, count 0 2006.286.05:29:44.73#ibcon#*after write, iclass 19, count 0 2006.286.05:29:44.73#ibcon#*before return 0, iclass 19, count 0 2006.286.05:29:44.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:29:44.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:29:44.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.05:29:44.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.05:29:44.73$vck44/va=6,4 2006.286.05:29:44.73#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.05:29:44.73#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.05:29:44.73#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:44.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:29:44.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:29:44.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:29:44.79#ibcon#enter wrdev, iclass 21, count 2 2006.286.05:29:44.79#ibcon#first serial, iclass 21, count 2 2006.286.05:29:44.79#ibcon#enter sib2, iclass 21, count 2 2006.286.05:29:44.79#ibcon#flushed, iclass 21, count 2 2006.286.05:29:44.79#ibcon#about to write, iclass 21, count 2 2006.286.05:29:44.79#ibcon#wrote, iclass 21, count 2 2006.286.05:29:44.79#ibcon#about to read 3, iclass 21, count 2 2006.286.05:29:44.81#ibcon#read 3, iclass 21, count 2 2006.286.05:29:44.81#ibcon#about to read 4, iclass 21, count 2 2006.286.05:29:44.81#ibcon#read 4, iclass 21, count 2 2006.286.05:29:44.81#ibcon#about to read 5, iclass 21, count 2 2006.286.05:29:44.81#ibcon#read 5, iclass 21, count 2 2006.286.05:29:44.81#ibcon#about to read 6, iclass 21, count 2 2006.286.05:29:44.81#ibcon#read 6, iclass 21, count 2 2006.286.05:29:44.81#ibcon#end of sib2, iclass 21, count 2 2006.286.05:29:44.81#ibcon#*mode == 0, iclass 21, count 2 2006.286.05:29:44.81#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.05:29:44.81#ibcon#[25=AT06-04\r\n] 2006.286.05:29:44.81#ibcon#*before write, iclass 21, count 2 2006.286.05:29:44.81#ibcon#enter sib2, iclass 21, count 2 2006.286.05:29:44.81#ibcon#flushed, iclass 21, count 2 2006.286.05:29:44.81#ibcon#about to write, iclass 21, count 2 2006.286.05:29:44.81#ibcon#wrote, iclass 21, count 2 2006.286.05:29:44.81#ibcon#about to read 3, iclass 21, count 2 2006.286.05:29:44.84#ibcon#read 3, iclass 21, count 2 2006.286.05:29:44.84#ibcon#about to read 4, iclass 21, count 2 2006.286.05:29:44.84#ibcon#read 4, iclass 21, count 2 2006.286.05:29:44.84#ibcon#about to read 5, iclass 21, count 2 2006.286.05:29:44.84#ibcon#read 5, iclass 21, count 2 2006.286.05:29:44.84#ibcon#about to read 6, iclass 21, count 2 2006.286.05:29:44.84#ibcon#read 6, iclass 21, count 2 2006.286.05:29:44.84#ibcon#end of sib2, iclass 21, count 2 2006.286.05:29:44.84#ibcon#*after write, iclass 21, count 2 2006.286.05:29:44.84#ibcon#*before return 0, iclass 21, count 2 2006.286.05:29:44.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:29:44.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:29:44.84#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.05:29:44.84#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:44.84#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:29:44.96#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:29:44.96#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:29:44.96#ibcon#enter wrdev, iclass 21, count 0 2006.286.05:29:44.96#ibcon#first serial, iclass 21, count 0 2006.286.05:29:44.96#ibcon#enter sib2, iclass 21, count 0 2006.286.05:29:44.96#ibcon#flushed, iclass 21, count 0 2006.286.05:29:44.96#ibcon#about to write, iclass 21, count 0 2006.286.05:29:44.96#ibcon#wrote, iclass 21, count 0 2006.286.05:29:44.96#ibcon#about to read 3, iclass 21, count 0 2006.286.05:29:44.98#ibcon#read 3, iclass 21, count 0 2006.286.05:29:44.98#ibcon#about to read 4, iclass 21, count 0 2006.286.05:29:44.98#ibcon#read 4, iclass 21, count 0 2006.286.05:29:44.98#ibcon#about to read 5, iclass 21, count 0 2006.286.05:29:44.98#ibcon#read 5, iclass 21, count 0 2006.286.05:29:44.98#ibcon#about to read 6, iclass 21, count 0 2006.286.05:29:44.98#ibcon#read 6, iclass 21, count 0 2006.286.05:29:44.98#ibcon#end of sib2, iclass 21, count 0 2006.286.05:29:44.98#ibcon#*mode == 0, iclass 21, count 0 2006.286.05:29:44.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.05:29:44.98#ibcon#[25=USB\r\n] 2006.286.05:29:44.98#ibcon#*before write, iclass 21, count 0 2006.286.05:29:44.98#ibcon#enter sib2, iclass 21, count 0 2006.286.05:29:44.98#ibcon#flushed, iclass 21, count 0 2006.286.05:29:44.98#ibcon#about to write, iclass 21, count 0 2006.286.05:29:44.98#ibcon#wrote, iclass 21, count 0 2006.286.05:29:44.98#ibcon#about to read 3, iclass 21, count 0 2006.286.05:29:45.01#ibcon#read 3, iclass 21, count 0 2006.286.05:29:45.01#ibcon#about to read 4, iclass 21, count 0 2006.286.05:29:45.01#ibcon#read 4, iclass 21, count 0 2006.286.05:29:45.01#ibcon#about to read 5, iclass 21, count 0 2006.286.05:29:45.01#ibcon#read 5, iclass 21, count 0 2006.286.05:29:45.01#ibcon#about to read 6, iclass 21, count 0 2006.286.05:29:45.01#ibcon#read 6, iclass 21, count 0 2006.286.05:29:45.01#ibcon#end of sib2, iclass 21, count 0 2006.286.05:29:45.01#ibcon#*after write, iclass 21, count 0 2006.286.05:29:45.01#ibcon#*before return 0, iclass 21, count 0 2006.286.05:29:45.01#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:29:45.01#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:29:45.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.05:29:45.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.05:29:45.01$vck44/valo=7,864.99 2006.286.05:29:45.01#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.05:29:45.01#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.05:29:45.01#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:45.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:29:45.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:29:45.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:29:45.01#ibcon#enter wrdev, iclass 23, count 0 2006.286.05:29:45.01#ibcon#first serial, iclass 23, count 0 2006.286.05:29:45.01#ibcon#enter sib2, iclass 23, count 0 2006.286.05:29:45.01#ibcon#flushed, iclass 23, count 0 2006.286.05:29:45.01#ibcon#about to write, iclass 23, count 0 2006.286.05:29:45.01#ibcon#wrote, iclass 23, count 0 2006.286.05:29:45.01#ibcon#about to read 3, iclass 23, count 0 2006.286.05:29:45.03#ibcon#read 3, iclass 23, count 0 2006.286.05:29:45.03#ibcon#about to read 4, iclass 23, count 0 2006.286.05:29:45.03#ibcon#read 4, iclass 23, count 0 2006.286.05:29:45.03#ibcon#about to read 5, iclass 23, count 0 2006.286.05:29:45.03#ibcon#read 5, iclass 23, count 0 2006.286.05:29:45.03#ibcon#about to read 6, iclass 23, count 0 2006.286.05:29:45.03#ibcon#read 6, iclass 23, count 0 2006.286.05:29:45.03#ibcon#end of sib2, iclass 23, count 0 2006.286.05:29:45.03#ibcon#*mode == 0, iclass 23, count 0 2006.286.05:29:45.03#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.05:29:45.03#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.05:29:45.03#ibcon#*before write, iclass 23, count 0 2006.286.05:29:45.03#ibcon#enter sib2, iclass 23, count 0 2006.286.05:29:45.03#ibcon#flushed, iclass 23, count 0 2006.286.05:29:45.03#ibcon#about to write, iclass 23, count 0 2006.286.05:29:45.03#ibcon#wrote, iclass 23, count 0 2006.286.05:29:45.03#ibcon#about to read 3, iclass 23, count 0 2006.286.05:29:45.07#ibcon#read 3, iclass 23, count 0 2006.286.05:29:45.07#ibcon#about to read 4, iclass 23, count 0 2006.286.05:29:45.07#ibcon#read 4, iclass 23, count 0 2006.286.05:29:45.07#ibcon#about to read 5, iclass 23, count 0 2006.286.05:29:45.07#ibcon#read 5, iclass 23, count 0 2006.286.05:29:45.07#ibcon#about to read 6, iclass 23, count 0 2006.286.05:29:45.07#ibcon#read 6, iclass 23, count 0 2006.286.05:29:45.07#ibcon#end of sib2, iclass 23, count 0 2006.286.05:29:45.07#ibcon#*after write, iclass 23, count 0 2006.286.05:29:45.07#ibcon#*before return 0, iclass 23, count 0 2006.286.05:29:45.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:29:45.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:29:45.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.05:29:45.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.05:29:45.07$vck44/va=7,4 2006.286.05:29:45.07#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.05:29:45.07#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.05:29:45.07#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:45.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:29:45.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:29:45.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:29:45.13#ibcon#enter wrdev, iclass 25, count 2 2006.286.05:29:45.13#ibcon#first serial, iclass 25, count 2 2006.286.05:29:45.13#ibcon#enter sib2, iclass 25, count 2 2006.286.05:29:45.13#ibcon#flushed, iclass 25, count 2 2006.286.05:29:45.13#ibcon#about to write, iclass 25, count 2 2006.286.05:29:45.13#ibcon#wrote, iclass 25, count 2 2006.286.05:29:45.13#ibcon#about to read 3, iclass 25, count 2 2006.286.05:29:45.15#ibcon#read 3, iclass 25, count 2 2006.286.05:29:45.15#ibcon#about to read 4, iclass 25, count 2 2006.286.05:29:45.15#ibcon#read 4, iclass 25, count 2 2006.286.05:29:45.15#ibcon#about to read 5, iclass 25, count 2 2006.286.05:29:45.15#ibcon#read 5, iclass 25, count 2 2006.286.05:29:45.15#ibcon#about to read 6, iclass 25, count 2 2006.286.05:29:45.15#ibcon#read 6, iclass 25, count 2 2006.286.05:29:45.15#ibcon#end of sib2, iclass 25, count 2 2006.286.05:29:45.15#ibcon#*mode == 0, iclass 25, count 2 2006.286.05:29:45.15#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.05:29:45.15#ibcon#[25=AT07-04\r\n] 2006.286.05:29:45.15#ibcon#*before write, iclass 25, count 2 2006.286.05:29:45.15#ibcon#enter sib2, iclass 25, count 2 2006.286.05:29:45.15#ibcon#flushed, iclass 25, count 2 2006.286.05:29:45.15#ibcon#about to write, iclass 25, count 2 2006.286.05:29:45.15#ibcon#wrote, iclass 25, count 2 2006.286.05:29:45.15#ibcon#about to read 3, iclass 25, count 2 2006.286.05:29:45.18#ibcon#read 3, iclass 25, count 2 2006.286.05:29:45.18#ibcon#about to read 4, iclass 25, count 2 2006.286.05:29:45.18#ibcon#read 4, iclass 25, count 2 2006.286.05:29:45.18#ibcon#about to read 5, iclass 25, count 2 2006.286.05:29:45.18#ibcon#read 5, iclass 25, count 2 2006.286.05:29:45.18#ibcon#about to read 6, iclass 25, count 2 2006.286.05:29:45.18#ibcon#read 6, iclass 25, count 2 2006.286.05:29:45.18#ibcon#end of sib2, iclass 25, count 2 2006.286.05:29:45.18#ibcon#*after write, iclass 25, count 2 2006.286.05:29:45.18#ibcon#*before return 0, iclass 25, count 2 2006.286.05:29:45.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:29:45.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:29:45.18#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.05:29:45.18#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:45.18#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:29:45.30#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:29:45.30#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:29:45.30#ibcon#enter wrdev, iclass 25, count 0 2006.286.05:29:45.30#ibcon#first serial, iclass 25, count 0 2006.286.05:29:45.30#ibcon#enter sib2, iclass 25, count 0 2006.286.05:29:45.30#ibcon#flushed, iclass 25, count 0 2006.286.05:29:45.30#ibcon#about to write, iclass 25, count 0 2006.286.05:29:45.30#ibcon#wrote, iclass 25, count 0 2006.286.05:29:45.30#ibcon#about to read 3, iclass 25, count 0 2006.286.05:29:45.32#ibcon#read 3, iclass 25, count 0 2006.286.05:29:45.32#ibcon#about to read 4, iclass 25, count 0 2006.286.05:29:45.32#ibcon#read 4, iclass 25, count 0 2006.286.05:29:45.32#ibcon#about to read 5, iclass 25, count 0 2006.286.05:29:45.32#ibcon#read 5, iclass 25, count 0 2006.286.05:29:45.32#ibcon#about to read 6, iclass 25, count 0 2006.286.05:29:45.32#ibcon#read 6, iclass 25, count 0 2006.286.05:29:45.32#ibcon#end of sib2, iclass 25, count 0 2006.286.05:29:45.32#ibcon#*mode == 0, iclass 25, count 0 2006.286.05:29:45.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.05:29:45.32#ibcon#[25=USB\r\n] 2006.286.05:29:45.32#ibcon#*before write, iclass 25, count 0 2006.286.05:29:45.32#ibcon#enter sib2, iclass 25, count 0 2006.286.05:29:45.32#ibcon#flushed, iclass 25, count 0 2006.286.05:29:45.32#ibcon#about to write, iclass 25, count 0 2006.286.05:29:45.32#ibcon#wrote, iclass 25, count 0 2006.286.05:29:45.32#ibcon#about to read 3, iclass 25, count 0 2006.286.05:29:45.35#ibcon#read 3, iclass 25, count 0 2006.286.05:29:45.35#ibcon#about to read 4, iclass 25, count 0 2006.286.05:29:45.38#ibcon#read 4, iclass 25, count 0 2006.286.05:29:45.38#ibcon#about to read 5, iclass 25, count 0 2006.286.05:29:45.38#ibcon#read 5, iclass 25, count 0 2006.286.05:29:45.38#ibcon#about to read 6, iclass 25, count 0 2006.286.05:29:45.38#ibcon#read 6, iclass 25, count 0 2006.286.05:29:45.38#ibcon#end of sib2, iclass 25, count 0 2006.286.05:29:45.38#ibcon#*after write, iclass 25, count 0 2006.286.05:29:45.38#ibcon#*before return 0, iclass 25, count 0 2006.286.05:29:45.38#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:29:45.38#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:29:45.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.05:29:45.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.05:29:45.38$vck44/valo=8,884.99 2006.286.05:29:45.38#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.05:29:45.38#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.05:29:45.38#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:45.38#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:29:45.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:29:45.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:29:45.38#ibcon#enter wrdev, iclass 27, count 0 2006.286.05:29:45.38#ibcon#first serial, iclass 27, count 0 2006.286.05:29:45.38#ibcon#enter sib2, iclass 27, count 0 2006.286.05:29:45.38#ibcon#flushed, iclass 27, count 0 2006.286.05:29:45.38#ibcon#about to write, iclass 27, count 0 2006.286.05:29:45.38#ibcon#wrote, iclass 27, count 0 2006.286.05:29:45.38#ibcon#about to read 3, iclass 27, count 0 2006.286.05:29:45.40#ibcon#read 3, iclass 27, count 0 2006.286.05:29:45.40#ibcon#about to read 4, iclass 27, count 0 2006.286.05:29:45.40#ibcon#read 4, iclass 27, count 0 2006.286.05:29:45.40#ibcon#about to read 5, iclass 27, count 0 2006.286.05:29:45.40#ibcon#read 5, iclass 27, count 0 2006.286.05:29:45.40#ibcon#about to read 6, iclass 27, count 0 2006.286.05:29:45.40#ibcon#read 6, iclass 27, count 0 2006.286.05:29:45.40#ibcon#end of sib2, iclass 27, count 0 2006.286.05:29:45.40#ibcon#*mode == 0, iclass 27, count 0 2006.286.05:29:45.40#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.05:29:45.40#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.05:29:45.40#ibcon#*before write, iclass 27, count 0 2006.286.05:29:45.40#ibcon#enter sib2, iclass 27, count 0 2006.286.05:29:45.40#ibcon#flushed, iclass 27, count 0 2006.286.05:29:45.40#ibcon#about to write, iclass 27, count 0 2006.286.05:29:45.40#ibcon#wrote, iclass 27, count 0 2006.286.05:29:45.40#ibcon#about to read 3, iclass 27, count 0 2006.286.05:29:45.44#ibcon#read 3, iclass 27, count 0 2006.286.05:29:45.44#ibcon#about to read 4, iclass 27, count 0 2006.286.05:29:45.44#ibcon#read 4, iclass 27, count 0 2006.286.05:29:45.44#ibcon#about to read 5, iclass 27, count 0 2006.286.05:29:45.44#ibcon#read 5, iclass 27, count 0 2006.286.05:29:45.44#ibcon#about to read 6, iclass 27, count 0 2006.286.05:29:45.44#ibcon#read 6, iclass 27, count 0 2006.286.05:29:45.44#ibcon#end of sib2, iclass 27, count 0 2006.286.05:29:45.44#ibcon#*after write, iclass 27, count 0 2006.286.05:29:45.44#ibcon#*before return 0, iclass 27, count 0 2006.286.05:29:45.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:29:45.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:29:45.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.05:29:45.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.05:29:45.44$vck44/va=8,3 2006.286.05:29:45.44#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.05:29:45.44#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.05:29:45.44#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:45.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:29:45.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:29:45.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:29:45.50#ibcon#enter wrdev, iclass 29, count 2 2006.286.05:29:45.50#ibcon#first serial, iclass 29, count 2 2006.286.05:29:45.50#ibcon#enter sib2, iclass 29, count 2 2006.286.05:29:45.50#ibcon#flushed, iclass 29, count 2 2006.286.05:29:45.50#ibcon#about to write, iclass 29, count 2 2006.286.05:29:45.50#ibcon#wrote, iclass 29, count 2 2006.286.05:29:45.50#ibcon#about to read 3, iclass 29, count 2 2006.286.05:29:45.52#ibcon#read 3, iclass 29, count 2 2006.286.05:29:45.52#ibcon#about to read 4, iclass 29, count 2 2006.286.05:29:45.52#ibcon#read 4, iclass 29, count 2 2006.286.05:29:45.52#ibcon#about to read 5, iclass 29, count 2 2006.286.05:29:45.52#ibcon#read 5, iclass 29, count 2 2006.286.05:29:45.52#ibcon#about to read 6, iclass 29, count 2 2006.286.05:29:45.52#ibcon#read 6, iclass 29, count 2 2006.286.05:29:45.52#ibcon#end of sib2, iclass 29, count 2 2006.286.05:29:45.52#ibcon#*mode == 0, iclass 29, count 2 2006.286.05:29:45.52#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.05:29:45.52#ibcon#[25=AT08-03\r\n] 2006.286.05:29:45.52#ibcon#*before write, iclass 29, count 2 2006.286.05:29:45.52#ibcon#enter sib2, iclass 29, count 2 2006.286.05:29:45.52#ibcon#flushed, iclass 29, count 2 2006.286.05:29:45.52#ibcon#about to write, iclass 29, count 2 2006.286.05:29:45.52#ibcon#wrote, iclass 29, count 2 2006.286.05:29:45.52#ibcon#about to read 3, iclass 29, count 2 2006.286.05:29:45.55#ibcon#read 3, iclass 29, count 2 2006.286.05:29:45.55#ibcon#about to read 4, iclass 29, count 2 2006.286.05:29:45.55#ibcon#read 4, iclass 29, count 2 2006.286.05:29:45.55#ibcon#about to read 5, iclass 29, count 2 2006.286.05:29:45.55#ibcon#read 5, iclass 29, count 2 2006.286.05:29:45.55#ibcon#about to read 6, iclass 29, count 2 2006.286.05:29:45.55#ibcon#read 6, iclass 29, count 2 2006.286.05:29:45.55#ibcon#end of sib2, iclass 29, count 2 2006.286.05:29:45.55#ibcon#*after write, iclass 29, count 2 2006.286.05:29:45.55#ibcon#*before return 0, iclass 29, count 2 2006.286.05:29:45.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:29:45.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:29:45.55#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.05:29:45.55#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:45.55#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:29:45.66#abcon#<5=/04 4.2 7.5 21.22 781015.1\r\n> 2006.286.05:29:45.67#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:29:45.67#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:29:45.67#ibcon#enter wrdev, iclass 29, count 0 2006.286.05:29:45.67#ibcon#first serial, iclass 29, count 0 2006.286.05:29:45.67#ibcon#enter sib2, iclass 29, count 0 2006.286.05:29:45.67#ibcon#flushed, iclass 29, count 0 2006.286.05:29:45.67#ibcon#about to write, iclass 29, count 0 2006.286.05:29:45.67#ibcon#wrote, iclass 29, count 0 2006.286.05:29:45.67#ibcon#about to read 3, iclass 29, count 0 2006.286.05:29:45.68#abcon#{5=INTERFACE CLEAR} 2006.286.05:29:45.69#ibcon#read 3, iclass 29, count 0 2006.286.05:29:45.69#ibcon#about to read 4, iclass 29, count 0 2006.286.05:29:45.69#ibcon#read 4, iclass 29, count 0 2006.286.05:29:45.69#ibcon#about to read 5, iclass 29, count 0 2006.286.05:29:45.69#ibcon#read 5, iclass 29, count 0 2006.286.05:29:45.69#ibcon#about to read 6, iclass 29, count 0 2006.286.05:29:45.69#ibcon#read 6, iclass 29, count 0 2006.286.05:29:45.69#ibcon#end of sib2, iclass 29, count 0 2006.286.05:29:45.69#ibcon#*mode == 0, iclass 29, count 0 2006.286.05:29:45.69#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.05:29:45.69#ibcon#[25=USB\r\n] 2006.286.05:29:45.69#ibcon#*before write, iclass 29, count 0 2006.286.05:29:45.69#ibcon#enter sib2, iclass 29, count 0 2006.286.05:29:45.69#ibcon#flushed, iclass 29, count 0 2006.286.05:29:45.69#ibcon#about to write, iclass 29, count 0 2006.286.05:29:45.69#ibcon#wrote, iclass 29, count 0 2006.286.05:29:45.69#ibcon#about to read 3, iclass 29, count 0 2006.286.05:29:45.72#ibcon#read 3, iclass 29, count 0 2006.286.05:29:45.72#ibcon#about to read 4, iclass 29, count 0 2006.286.05:29:45.72#ibcon#read 4, iclass 29, count 0 2006.286.05:29:45.72#ibcon#about to read 5, iclass 29, count 0 2006.286.05:29:45.72#ibcon#read 5, iclass 29, count 0 2006.286.05:29:45.72#ibcon#about to read 6, iclass 29, count 0 2006.286.05:29:45.72#ibcon#read 6, iclass 29, count 0 2006.286.05:29:45.72#ibcon#end of sib2, iclass 29, count 0 2006.286.05:29:45.72#ibcon#*after write, iclass 29, count 0 2006.286.05:29:45.72#ibcon#*before return 0, iclass 29, count 0 2006.286.05:29:45.72#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:29:45.72#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:29:45.72#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.05:29:45.72#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.05:29:45.72$vck44/vblo=1,629.99 2006.286.05:29:45.72#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.05:29:45.72#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.05:29:45.72#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:45.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:29:45.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:29:45.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:29:45.72#ibcon#enter wrdev, iclass 34, count 0 2006.286.05:29:45.72#ibcon#first serial, iclass 34, count 0 2006.286.05:29:45.72#ibcon#enter sib2, iclass 34, count 0 2006.286.05:29:45.72#ibcon#flushed, iclass 34, count 0 2006.286.05:29:45.72#ibcon#about to write, iclass 34, count 0 2006.286.05:29:45.72#ibcon#wrote, iclass 34, count 0 2006.286.05:29:45.72#ibcon#about to read 3, iclass 34, count 0 2006.286.05:29:45.74#ibcon#read 3, iclass 34, count 0 2006.286.05:29:45.74#ibcon#about to read 4, iclass 34, count 0 2006.286.05:29:45.74#ibcon#read 4, iclass 34, count 0 2006.286.05:29:45.74#ibcon#about to read 5, iclass 34, count 0 2006.286.05:29:45.74#ibcon#read 5, iclass 34, count 0 2006.286.05:29:45.74#ibcon#about to read 6, iclass 34, count 0 2006.286.05:29:45.74#ibcon#read 6, iclass 34, count 0 2006.286.05:29:45.74#ibcon#end of sib2, iclass 34, count 0 2006.286.05:29:45.74#ibcon#*mode == 0, iclass 34, count 0 2006.286.05:29:45.74#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.05:29:45.74#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.05:29:45.74#ibcon#*before write, iclass 34, count 0 2006.286.05:29:45.74#ibcon#enter sib2, iclass 34, count 0 2006.286.05:29:45.74#ibcon#flushed, iclass 34, count 0 2006.286.05:29:45.74#ibcon#about to write, iclass 34, count 0 2006.286.05:29:45.74#ibcon#wrote, iclass 34, count 0 2006.286.05:29:45.74#ibcon#about to read 3, iclass 34, count 0 2006.286.05:29:45.74#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:29:45.78#ibcon#read 3, iclass 34, count 0 2006.286.05:29:45.78#ibcon#about to read 4, iclass 34, count 0 2006.286.05:29:45.78#ibcon#read 4, iclass 34, count 0 2006.286.05:29:45.78#ibcon#about to read 5, iclass 34, count 0 2006.286.05:29:45.78#ibcon#read 5, iclass 34, count 0 2006.286.05:29:45.78#ibcon#about to read 6, iclass 34, count 0 2006.286.05:29:45.78#ibcon#read 6, iclass 34, count 0 2006.286.05:29:45.78#ibcon#end of sib2, iclass 34, count 0 2006.286.05:29:45.78#ibcon#*after write, iclass 34, count 0 2006.286.05:29:45.78#ibcon#*before return 0, iclass 34, count 0 2006.286.05:29:45.78#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:29:45.78#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:29:45.78#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.05:29:45.78#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.05:29:45.78$vck44/vb=1,4 2006.286.05:29:45.78#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.286.05:29:45.78#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.286.05:29:45.78#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:45.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:29:45.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:29:45.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:29:45.78#ibcon#enter wrdev, iclass 37, count 2 2006.286.05:29:45.78#ibcon#first serial, iclass 37, count 2 2006.286.05:29:45.78#ibcon#enter sib2, iclass 37, count 2 2006.286.05:29:45.78#ibcon#flushed, iclass 37, count 2 2006.286.05:29:45.78#ibcon#about to write, iclass 37, count 2 2006.286.05:29:45.78#ibcon#wrote, iclass 37, count 2 2006.286.05:29:45.78#ibcon#about to read 3, iclass 37, count 2 2006.286.05:29:45.80#ibcon#read 3, iclass 37, count 2 2006.286.05:29:45.80#ibcon#about to read 4, iclass 37, count 2 2006.286.05:29:45.80#ibcon#read 4, iclass 37, count 2 2006.286.05:29:45.80#ibcon#about to read 5, iclass 37, count 2 2006.286.05:29:45.80#ibcon#read 5, iclass 37, count 2 2006.286.05:29:45.80#ibcon#about to read 6, iclass 37, count 2 2006.286.05:29:45.80#ibcon#read 6, iclass 37, count 2 2006.286.05:29:45.80#ibcon#end of sib2, iclass 37, count 2 2006.286.05:29:45.80#ibcon#*mode == 0, iclass 37, count 2 2006.286.05:29:45.80#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.286.05:29:45.80#ibcon#[27=AT01-04\r\n] 2006.286.05:29:45.80#ibcon#*before write, iclass 37, count 2 2006.286.05:29:45.80#ibcon#enter sib2, iclass 37, count 2 2006.286.05:29:45.80#ibcon#flushed, iclass 37, count 2 2006.286.05:29:45.80#ibcon#about to write, iclass 37, count 2 2006.286.05:29:45.80#ibcon#wrote, iclass 37, count 2 2006.286.05:29:45.80#ibcon#about to read 3, iclass 37, count 2 2006.286.05:29:45.83#ibcon#read 3, iclass 37, count 2 2006.286.05:29:45.83#ibcon#about to read 4, iclass 37, count 2 2006.286.05:29:45.83#ibcon#read 4, iclass 37, count 2 2006.286.05:29:45.83#ibcon#about to read 5, iclass 37, count 2 2006.286.05:29:45.83#ibcon#read 5, iclass 37, count 2 2006.286.05:29:45.83#ibcon#about to read 6, iclass 37, count 2 2006.286.05:29:45.83#ibcon#read 6, iclass 37, count 2 2006.286.05:29:45.83#ibcon#end of sib2, iclass 37, count 2 2006.286.05:29:45.83#ibcon#*after write, iclass 37, count 2 2006.286.05:29:45.83#ibcon#*before return 0, iclass 37, count 2 2006.286.05:29:45.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:29:45.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.286.05:29:45.83#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.286.05:29:45.83#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:45.83#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:29:45.95#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:29:45.95#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:29:45.95#ibcon#enter wrdev, iclass 37, count 0 2006.286.05:29:45.95#ibcon#first serial, iclass 37, count 0 2006.286.05:29:45.95#ibcon#enter sib2, iclass 37, count 0 2006.286.05:29:45.95#ibcon#flushed, iclass 37, count 0 2006.286.05:29:45.95#ibcon#about to write, iclass 37, count 0 2006.286.05:29:45.95#ibcon#wrote, iclass 37, count 0 2006.286.05:29:45.95#ibcon#about to read 3, iclass 37, count 0 2006.286.05:29:45.97#ibcon#read 3, iclass 37, count 0 2006.286.05:29:45.97#ibcon#about to read 4, iclass 37, count 0 2006.286.05:29:45.97#ibcon#read 4, iclass 37, count 0 2006.286.05:29:45.97#ibcon#about to read 5, iclass 37, count 0 2006.286.05:29:45.97#ibcon#read 5, iclass 37, count 0 2006.286.05:29:45.97#ibcon#about to read 6, iclass 37, count 0 2006.286.05:29:45.97#ibcon#read 6, iclass 37, count 0 2006.286.05:29:45.97#ibcon#end of sib2, iclass 37, count 0 2006.286.05:29:45.97#ibcon#*mode == 0, iclass 37, count 0 2006.286.05:29:45.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.05:29:45.97#ibcon#[27=USB\r\n] 2006.286.05:29:45.97#ibcon#*before write, iclass 37, count 0 2006.286.05:29:45.97#ibcon#enter sib2, iclass 37, count 0 2006.286.05:29:45.97#ibcon#flushed, iclass 37, count 0 2006.286.05:29:45.97#ibcon#about to write, iclass 37, count 0 2006.286.05:29:45.97#ibcon#wrote, iclass 37, count 0 2006.286.05:29:45.97#ibcon#about to read 3, iclass 37, count 0 2006.286.05:29:46.00#ibcon#read 3, iclass 37, count 0 2006.286.05:29:46.00#ibcon#about to read 4, iclass 37, count 0 2006.286.05:29:46.00#ibcon#read 4, iclass 37, count 0 2006.286.05:29:46.00#ibcon#about to read 5, iclass 37, count 0 2006.286.05:29:46.00#ibcon#read 5, iclass 37, count 0 2006.286.05:29:46.00#ibcon#about to read 6, iclass 37, count 0 2006.286.05:29:46.00#ibcon#read 6, iclass 37, count 0 2006.286.05:29:46.00#ibcon#end of sib2, iclass 37, count 0 2006.286.05:29:46.00#ibcon#*after write, iclass 37, count 0 2006.286.05:29:46.00#ibcon#*before return 0, iclass 37, count 0 2006.286.05:29:46.00#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:29:46.00#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.286.05:29:46.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.05:29:46.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.05:29:46.00$vck44/vblo=2,634.99 2006.286.05:29:46.00#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.286.05:29:46.00#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.286.05:29:46.00#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:46.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:29:46.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:29:46.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:29:46.00#ibcon#enter wrdev, iclass 39, count 0 2006.286.05:29:46.00#ibcon#first serial, iclass 39, count 0 2006.286.05:29:46.00#ibcon#enter sib2, iclass 39, count 0 2006.286.05:29:46.00#ibcon#flushed, iclass 39, count 0 2006.286.05:29:46.00#ibcon#about to write, iclass 39, count 0 2006.286.05:29:46.00#ibcon#wrote, iclass 39, count 0 2006.286.05:29:46.00#ibcon#about to read 3, iclass 39, count 0 2006.286.05:29:46.02#ibcon#read 3, iclass 39, count 0 2006.286.05:29:46.02#ibcon#about to read 4, iclass 39, count 0 2006.286.05:29:46.02#ibcon#read 4, iclass 39, count 0 2006.286.05:29:46.02#ibcon#about to read 5, iclass 39, count 0 2006.286.05:29:46.02#ibcon#read 5, iclass 39, count 0 2006.286.05:29:46.02#ibcon#about to read 6, iclass 39, count 0 2006.286.05:29:46.02#ibcon#read 6, iclass 39, count 0 2006.286.05:29:46.02#ibcon#end of sib2, iclass 39, count 0 2006.286.05:29:46.02#ibcon#*mode == 0, iclass 39, count 0 2006.286.05:29:46.02#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.05:29:46.02#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.05:29:46.02#ibcon#*before write, iclass 39, count 0 2006.286.05:29:46.02#ibcon#enter sib2, iclass 39, count 0 2006.286.05:29:46.02#ibcon#flushed, iclass 39, count 0 2006.286.05:29:46.02#ibcon#about to write, iclass 39, count 0 2006.286.05:29:46.02#ibcon#wrote, iclass 39, count 0 2006.286.05:29:46.02#ibcon#about to read 3, iclass 39, count 0 2006.286.05:29:46.06#ibcon#read 3, iclass 39, count 0 2006.286.05:29:46.06#ibcon#about to read 4, iclass 39, count 0 2006.286.05:29:46.06#ibcon#read 4, iclass 39, count 0 2006.286.05:29:46.06#ibcon#about to read 5, iclass 39, count 0 2006.286.05:29:46.06#ibcon#read 5, iclass 39, count 0 2006.286.05:29:46.06#ibcon#about to read 6, iclass 39, count 0 2006.286.05:29:46.06#ibcon#read 6, iclass 39, count 0 2006.286.05:29:46.06#ibcon#end of sib2, iclass 39, count 0 2006.286.05:29:46.06#ibcon#*after write, iclass 39, count 0 2006.286.05:29:46.06#ibcon#*before return 0, iclass 39, count 0 2006.286.05:29:46.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:29:46.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.286.05:29:46.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.05:29:46.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.05:29:46.06$vck44/vb=2,5 2006.286.05:29:46.06#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.286.05:29:46.06#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.286.05:29:46.06#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:46.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:29:46.12#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:29:46.12#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:29:46.12#ibcon#enter wrdev, iclass 3, count 2 2006.286.05:29:46.12#ibcon#first serial, iclass 3, count 2 2006.286.05:29:46.12#ibcon#enter sib2, iclass 3, count 2 2006.286.05:29:46.12#ibcon#flushed, iclass 3, count 2 2006.286.05:29:46.12#ibcon#about to write, iclass 3, count 2 2006.286.05:29:46.12#ibcon#wrote, iclass 3, count 2 2006.286.05:29:46.12#ibcon#about to read 3, iclass 3, count 2 2006.286.05:29:46.14#ibcon#read 3, iclass 3, count 2 2006.286.05:29:46.14#ibcon#about to read 4, iclass 3, count 2 2006.286.05:29:46.14#ibcon#read 4, iclass 3, count 2 2006.286.05:29:46.14#ibcon#about to read 5, iclass 3, count 2 2006.286.05:29:46.14#ibcon#read 5, iclass 3, count 2 2006.286.05:29:46.14#ibcon#about to read 6, iclass 3, count 2 2006.286.05:29:46.14#ibcon#read 6, iclass 3, count 2 2006.286.05:29:46.14#ibcon#end of sib2, iclass 3, count 2 2006.286.05:29:46.14#ibcon#*mode == 0, iclass 3, count 2 2006.286.05:29:46.14#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.286.05:29:46.14#ibcon#[27=AT02-05\r\n] 2006.286.05:29:46.14#ibcon#*before write, iclass 3, count 2 2006.286.05:29:46.14#ibcon#enter sib2, iclass 3, count 2 2006.286.05:29:46.14#ibcon#flushed, iclass 3, count 2 2006.286.05:29:46.14#ibcon#about to write, iclass 3, count 2 2006.286.05:29:46.14#ibcon#wrote, iclass 3, count 2 2006.286.05:29:46.14#ibcon#about to read 3, iclass 3, count 2 2006.286.05:29:46.17#ibcon#read 3, iclass 3, count 2 2006.286.05:29:46.17#ibcon#about to read 4, iclass 3, count 2 2006.286.05:29:46.17#ibcon#read 4, iclass 3, count 2 2006.286.05:29:46.17#ibcon#about to read 5, iclass 3, count 2 2006.286.05:29:46.17#ibcon#read 5, iclass 3, count 2 2006.286.05:29:46.17#ibcon#about to read 6, iclass 3, count 2 2006.286.05:29:46.17#ibcon#read 6, iclass 3, count 2 2006.286.05:29:46.17#ibcon#end of sib2, iclass 3, count 2 2006.286.05:29:46.17#ibcon#*after write, iclass 3, count 2 2006.286.05:29:46.17#ibcon#*before return 0, iclass 3, count 2 2006.286.05:29:46.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:29:46.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.286.05:29:46.17#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.286.05:29:46.17#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:46.17#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:29:46.29#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:29:46.29#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:29:46.29#ibcon#enter wrdev, iclass 3, count 0 2006.286.05:29:46.29#ibcon#first serial, iclass 3, count 0 2006.286.05:29:46.29#ibcon#enter sib2, iclass 3, count 0 2006.286.05:29:46.29#ibcon#flushed, iclass 3, count 0 2006.286.05:29:46.29#ibcon#about to write, iclass 3, count 0 2006.286.05:29:46.29#ibcon#wrote, iclass 3, count 0 2006.286.05:29:46.29#ibcon#about to read 3, iclass 3, count 0 2006.286.05:29:46.31#ibcon#read 3, iclass 3, count 0 2006.286.05:29:46.31#ibcon#about to read 4, iclass 3, count 0 2006.286.05:29:46.31#ibcon#read 4, iclass 3, count 0 2006.286.05:29:46.31#ibcon#about to read 5, iclass 3, count 0 2006.286.05:29:46.31#ibcon#read 5, iclass 3, count 0 2006.286.05:29:46.31#ibcon#about to read 6, iclass 3, count 0 2006.286.05:29:46.31#ibcon#read 6, iclass 3, count 0 2006.286.05:29:46.31#ibcon#end of sib2, iclass 3, count 0 2006.286.05:29:46.31#ibcon#*mode == 0, iclass 3, count 0 2006.286.05:29:46.31#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.05:29:46.31#ibcon#[27=USB\r\n] 2006.286.05:29:46.31#ibcon#*before write, iclass 3, count 0 2006.286.05:29:46.31#ibcon#enter sib2, iclass 3, count 0 2006.286.05:29:46.31#ibcon#flushed, iclass 3, count 0 2006.286.05:29:46.31#ibcon#about to write, iclass 3, count 0 2006.286.05:29:46.31#ibcon#wrote, iclass 3, count 0 2006.286.05:29:46.31#ibcon#about to read 3, iclass 3, count 0 2006.286.05:29:46.34#ibcon#read 3, iclass 3, count 0 2006.286.05:29:46.34#ibcon#about to read 4, iclass 3, count 0 2006.286.05:29:46.34#ibcon#read 4, iclass 3, count 0 2006.286.05:29:46.34#ibcon#about to read 5, iclass 3, count 0 2006.286.05:29:46.34#ibcon#read 5, iclass 3, count 0 2006.286.05:29:46.34#ibcon#about to read 6, iclass 3, count 0 2006.286.05:29:46.34#ibcon#read 6, iclass 3, count 0 2006.286.05:29:46.34#ibcon#end of sib2, iclass 3, count 0 2006.286.05:29:46.34#ibcon#*after write, iclass 3, count 0 2006.286.05:29:46.34#ibcon#*before return 0, iclass 3, count 0 2006.286.05:29:46.34#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:29:46.34#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.286.05:29:46.34#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.05:29:46.34#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.05:29:46.34$vck44/vblo=3,649.99 2006.286.05:29:46.34#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.286.05:29:46.34#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.286.05:29:46.34#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:46.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:29:46.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:29:46.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:29:46.34#ibcon#enter wrdev, iclass 5, count 0 2006.286.05:29:46.34#ibcon#first serial, iclass 5, count 0 2006.286.05:29:46.34#ibcon#enter sib2, iclass 5, count 0 2006.286.05:29:46.34#ibcon#flushed, iclass 5, count 0 2006.286.05:29:46.34#ibcon#about to write, iclass 5, count 0 2006.286.05:29:46.34#ibcon#wrote, iclass 5, count 0 2006.286.05:29:46.34#ibcon#about to read 3, iclass 5, count 0 2006.286.05:29:46.36#ibcon#read 3, iclass 5, count 0 2006.286.05:29:46.48#ibcon#about to read 4, iclass 5, count 0 2006.286.05:29:46.48#ibcon#read 4, iclass 5, count 0 2006.286.05:29:46.48#ibcon#about to read 5, iclass 5, count 0 2006.286.05:29:46.48#ibcon#read 5, iclass 5, count 0 2006.286.05:29:46.48#ibcon#about to read 6, iclass 5, count 0 2006.286.05:29:46.48#ibcon#read 6, iclass 5, count 0 2006.286.05:29:46.48#ibcon#end of sib2, iclass 5, count 0 2006.286.05:29:46.48#ibcon#*mode == 0, iclass 5, count 0 2006.286.05:29:46.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.05:29:46.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.05:29:46.48#ibcon#*before write, iclass 5, count 0 2006.286.05:29:46.48#ibcon#enter sib2, iclass 5, count 0 2006.286.05:29:46.48#ibcon#flushed, iclass 5, count 0 2006.286.05:29:46.48#ibcon#about to write, iclass 5, count 0 2006.286.05:29:46.48#ibcon#wrote, iclass 5, count 0 2006.286.05:29:46.48#ibcon#about to read 3, iclass 5, count 0 2006.286.05:29:46.52#ibcon#read 3, iclass 5, count 0 2006.286.05:29:46.52#ibcon#about to read 4, iclass 5, count 0 2006.286.05:29:46.52#ibcon#read 4, iclass 5, count 0 2006.286.05:29:46.52#ibcon#about to read 5, iclass 5, count 0 2006.286.05:29:46.52#ibcon#read 5, iclass 5, count 0 2006.286.05:29:46.52#ibcon#about to read 6, iclass 5, count 0 2006.286.05:29:46.52#ibcon#read 6, iclass 5, count 0 2006.286.05:29:46.52#ibcon#end of sib2, iclass 5, count 0 2006.286.05:29:46.52#ibcon#*after write, iclass 5, count 0 2006.286.05:29:46.52#ibcon#*before return 0, iclass 5, count 0 2006.286.05:29:46.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:29:46.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.286.05:29:46.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.05:29:46.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.05:29:46.52$vck44/vb=3,4 2006.286.05:29:46.52#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.286.05:29:46.52#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.286.05:29:46.52#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:46.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:29:46.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:29:46.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:29:46.52#ibcon#enter wrdev, iclass 7, count 2 2006.286.05:29:46.52#ibcon#first serial, iclass 7, count 2 2006.286.05:29:46.52#ibcon#enter sib2, iclass 7, count 2 2006.286.05:29:46.52#ibcon#flushed, iclass 7, count 2 2006.286.05:29:46.52#ibcon#about to write, iclass 7, count 2 2006.286.05:29:46.52#ibcon#wrote, iclass 7, count 2 2006.286.05:29:46.52#ibcon#about to read 3, iclass 7, count 2 2006.286.05:29:46.54#ibcon#read 3, iclass 7, count 2 2006.286.05:29:46.54#ibcon#about to read 4, iclass 7, count 2 2006.286.05:29:46.54#ibcon#read 4, iclass 7, count 2 2006.286.05:29:46.54#ibcon#about to read 5, iclass 7, count 2 2006.286.05:29:46.54#ibcon#read 5, iclass 7, count 2 2006.286.05:29:46.54#ibcon#about to read 6, iclass 7, count 2 2006.286.05:29:46.54#ibcon#read 6, iclass 7, count 2 2006.286.05:29:46.54#ibcon#end of sib2, iclass 7, count 2 2006.286.05:29:46.54#ibcon#*mode == 0, iclass 7, count 2 2006.286.05:29:46.54#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.286.05:29:46.54#ibcon#[27=AT03-04\r\n] 2006.286.05:29:46.54#ibcon#*before write, iclass 7, count 2 2006.286.05:29:46.54#ibcon#enter sib2, iclass 7, count 2 2006.286.05:29:46.54#ibcon#flushed, iclass 7, count 2 2006.286.05:29:46.54#ibcon#about to write, iclass 7, count 2 2006.286.05:29:46.54#ibcon#wrote, iclass 7, count 2 2006.286.05:29:46.54#ibcon#about to read 3, iclass 7, count 2 2006.286.05:29:46.57#ibcon#read 3, iclass 7, count 2 2006.286.05:29:46.57#ibcon#about to read 4, iclass 7, count 2 2006.286.05:29:46.57#ibcon#read 4, iclass 7, count 2 2006.286.05:29:46.57#ibcon#about to read 5, iclass 7, count 2 2006.286.05:29:46.57#ibcon#read 5, iclass 7, count 2 2006.286.05:29:46.57#ibcon#about to read 6, iclass 7, count 2 2006.286.05:29:46.57#ibcon#read 6, iclass 7, count 2 2006.286.05:29:46.57#ibcon#end of sib2, iclass 7, count 2 2006.286.05:29:46.57#ibcon#*after write, iclass 7, count 2 2006.286.05:29:46.57#ibcon#*before return 0, iclass 7, count 2 2006.286.05:29:46.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:29:46.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.286.05:29:46.57#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.286.05:29:46.57#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:46.57#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:29:46.69#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:29:46.69#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:29:46.69#ibcon#enter wrdev, iclass 7, count 0 2006.286.05:29:46.69#ibcon#first serial, iclass 7, count 0 2006.286.05:29:46.69#ibcon#enter sib2, iclass 7, count 0 2006.286.05:29:46.69#ibcon#flushed, iclass 7, count 0 2006.286.05:29:46.69#ibcon#about to write, iclass 7, count 0 2006.286.05:29:46.69#ibcon#wrote, iclass 7, count 0 2006.286.05:29:46.69#ibcon#about to read 3, iclass 7, count 0 2006.286.05:29:46.71#ibcon#read 3, iclass 7, count 0 2006.286.05:29:46.71#ibcon#about to read 4, iclass 7, count 0 2006.286.05:29:46.71#ibcon#read 4, iclass 7, count 0 2006.286.05:29:46.71#ibcon#about to read 5, iclass 7, count 0 2006.286.05:29:46.71#ibcon#read 5, iclass 7, count 0 2006.286.05:29:46.71#ibcon#about to read 6, iclass 7, count 0 2006.286.05:29:46.71#ibcon#read 6, iclass 7, count 0 2006.286.05:29:46.71#ibcon#end of sib2, iclass 7, count 0 2006.286.05:29:46.71#ibcon#*mode == 0, iclass 7, count 0 2006.286.05:29:46.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.05:29:46.71#ibcon#[27=USB\r\n] 2006.286.05:29:46.71#ibcon#*before write, iclass 7, count 0 2006.286.05:29:46.71#ibcon#enter sib2, iclass 7, count 0 2006.286.05:29:46.71#ibcon#flushed, iclass 7, count 0 2006.286.05:29:46.71#ibcon#about to write, iclass 7, count 0 2006.286.05:29:46.71#ibcon#wrote, iclass 7, count 0 2006.286.05:29:46.71#ibcon#about to read 3, iclass 7, count 0 2006.286.05:29:46.74#ibcon#read 3, iclass 7, count 0 2006.286.05:29:46.74#ibcon#about to read 4, iclass 7, count 0 2006.286.05:29:46.74#ibcon#read 4, iclass 7, count 0 2006.286.05:29:46.74#ibcon#about to read 5, iclass 7, count 0 2006.286.05:29:46.74#ibcon#read 5, iclass 7, count 0 2006.286.05:29:46.74#ibcon#about to read 6, iclass 7, count 0 2006.286.05:29:46.74#ibcon#read 6, iclass 7, count 0 2006.286.05:29:46.74#ibcon#end of sib2, iclass 7, count 0 2006.286.05:29:46.74#ibcon#*after write, iclass 7, count 0 2006.286.05:29:46.74#ibcon#*before return 0, iclass 7, count 0 2006.286.05:29:46.74#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:29:46.74#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.286.05:29:46.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.05:29:46.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.05:29:46.74$vck44/vblo=4,679.99 2006.286.05:29:46.74#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.286.05:29:46.74#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.286.05:29:46.74#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:46.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:29:46.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:29:46.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:29:46.74#ibcon#enter wrdev, iclass 11, count 0 2006.286.05:29:46.74#ibcon#first serial, iclass 11, count 0 2006.286.05:29:46.74#ibcon#enter sib2, iclass 11, count 0 2006.286.05:29:46.74#ibcon#flushed, iclass 11, count 0 2006.286.05:29:46.74#ibcon#about to write, iclass 11, count 0 2006.286.05:29:46.74#ibcon#wrote, iclass 11, count 0 2006.286.05:29:46.74#ibcon#about to read 3, iclass 11, count 0 2006.286.05:29:46.76#ibcon#read 3, iclass 11, count 0 2006.286.05:29:46.76#ibcon#about to read 4, iclass 11, count 0 2006.286.05:29:46.76#ibcon#read 4, iclass 11, count 0 2006.286.05:29:46.76#ibcon#about to read 5, iclass 11, count 0 2006.286.05:29:46.76#ibcon#read 5, iclass 11, count 0 2006.286.05:29:46.76#ibcon#about to read 6, iclass 11, count 0 2006.286.05:29:46.76#ibcon#read 6, iclass 11, count 0 2006.286.05:29:46.76#ibcon#end of sib2, iclass 11, count 0 2006.286.05:29:46.76#ibcon#*mode == 0, iclass 11, count 0 2006.286.05:29:46.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.05:29:46.76#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.05:29:46.76#ibcon#*before write, iclass 11, count 0 2006.286.05:29:46.76#ibcon#enter sib2, iclass 11, count 0 2006.286.05:29:46.76#ibcon#flushed, iclass 11, count 0 2006.286.05:29:46.76#ibcon#about to write, iclass 11, count 0 2006.286.05:29:46.76#ibcon#wrote, iclass 11, count 0 2006.286.05:29:46.76#ibcon#about to read 3, iclass 11, count 0 2006.286.05:29:46.80#ibcon#read 3, iclass 11, count 0 2006.286.05:29:46.80#ibcon#about to read 4, iclass 11, count 0 2006.286.05:29:46.80#ibcon#read 4, iclass 11, count 0 2006.286.05:29:46.80#ibcon#about to read 5, iclass 11, count 0 2006.286.05:29:46.80#ibcon#read 5, iclass 11, count 0 2006.286.05:29:46.80#ibcon#about to read 6, iclass 11, count 0 2006.286.05:29:46.80#ibcon#read 6, iclass 11, count 0 2006.286.05:29:46.80#ibcon#end of sib2, iclass 11, count 0 2006.286.05:29:46.80#ibcon#*after write, iclass 11, count 0 2006.286.05:29:46.80#ibcon#*before return 0, iclass 11, count 0 2006.286.05:29:46.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:29:46.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.286.05:29:46.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.05:29:46.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.05:29:46.80$vck44/vb=4,5 2006.286.05:29:46.80#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.286.05:29:46.80#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.286.05:29:46.80#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:46.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:29:46.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:29:46.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:29:46.86#ibcon#enter wrdev, iclass 13, count 2 2006.286.05:29:46.86#ibcon#first serial, iclass 13, count 2 2006.286.05:29:46.86#ibcon#enter sib2, iclass 13, count 2 2006.286.05:29:46.86#ibcon#flushed, iclass 13, count 2 2006.286.05:29:46.86#ibcon#about to write, iclass 13, count 2 2006.286.05:29:46.86#ibcon#wrote, iclass 13, count 2 2006.286.05:29:46.86#ibcon#about to read 3, iclass 13, count 2 2006.286.05:29:46.88#ibcon#read 3, iclass 13, count 2 2006.286.05:29:46.88#ibcon#about to read 4, iclass 13, count 2 2006.286.05:29:46.88#ibcon#read 4, iclass 13, count 2 2006.286.05:29:46.88#ibcon#about to read 5, iclass 13, count 2 2006.286.05:29:46.88#ibcon#read 5, iclass 13, count 2 2006.286.05:29:46.88#ibcon#about to read 6, iclass 13, count 2 2006.286.05:29:46.88#ibcon#read 6, iclass 13, count 2 2006.286.05:29:46.88#ibcon#end of sib2, iclass 13, count 2 2006.286.05:29:46.88#ibcon#*mode == 0, iclass 13, count 2 2006.286.05:29:46.88#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.286.05:29:46.88#ibcon#[27=AT04-05\r\n] 2006.286.05:29:46.88#ibcon#*before write, iclass 13, count 2 2006.286.05:29:46.88#ibcon#enter sib2, iclass 13, count 2 2006.286.05:29:46.88#ibcon#flushed, iclass 13, count 2 2006.286.05:29:46.88#ibcon#about to write, iclass 13, count 2 2006.286.05:29:46.88#ibcon#wrote, iclass 13, count 2 2006.286.05:29:46.88#ibcon#about to read 3, iclass 13, count 2 2006.286.05:29:46.91#ibcon#read 3, iclass 13, count 2 2006.286.05:29:46.91#ibcon#about to read 4, iclass 13, count 2 2006.286.05:29:46.91#ibcon#read 4, iclass 13, count 2 2006.286.05:29:46.91#ibcon#about to read 5, iclass 13, count 2 2006.286.05:29:46.91#ibcon#read 5, iclass 13, count 2 2006.286.05:29:46.91#ibcon#about to read 6, iclass 13, count 2 2006.286.05:29:46.91#ibcon#read 6, iclass 13, count 2 2006.286.05:29:46.91#ibcon#end of sib2, iclass 13, count 2 2006.286.05:29:46.91#ibcon#*after write, iclass 13, count 2 2006.286.05:29:46.91#ibcon#*before return 0, iclass 13, count 2 2006.286.05:29:46.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:29:46.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.286.05:29:46.91#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.286.05:29:46.91#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:46.91#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:29:47.03#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:29:47.03#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:29:47.03#ibcon#enter wrdev, iclass 13, count 0 2006.286.05:29:47.03#ibcon#first serial, iclass 13, count 0 2006.286.05:29:47.03#ibcon#enter sib2, iclass 13, count 0 2006.286.05:29:47.03#ibcon#flushed, iclass 13, count 0 2006.286.05:29:47.03#ibcon#about to write, iclass 13, count 0 2006.286.05:29:47.03#ibcon#wrote, iclass 13, count 0 2006.286.05:29:47.03#ibcon#about to read 3, iclass 13, count 0 2006.286.05:29:47.05#ibcon#read 3, iclass 13, count 0 2006.286.05:29:47.05#ibcon#about to read 4, iclass 13, count 0 2006.286.05:29:47.05#ibcon#read 4, iclass 13, count 0 2006.286.05:29:47.05#ibcon#about to read 5, iclass 13, count 0 2006.286.05:29:47.05#ibcon#read 5, iclass 13, count 0 2006.286.05:29:47.05#ibcon#about to read 6, iclass 13, count 0 2006.286.05:29:47.05#ibcon#read 6, iclass 13, count 0 2006.286.05:29:47.05#ibcon#end of sib2, iclass 13, count 0 2006.286.05:29:47.05#ibcon#*mode == 0, iclass 13, count 0 2006.286.05:29:47.05#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.05:29:47.05#ibcon#[27=USB\r\n] 2006.286.05:29:47.05#ibcon#*before write, iclass 13, count 0 2006.286.05:29:47.05#ibcon#enter sib2, iclass 13, count 0 2006.286.05:29:47.05#ibcon#flushed, iclass 13, count 0 2006.286.05:29:47.05#ibcon#about to write, iclass 13, count 0 2006.286.05:29:47.05#ibcon#wrote, iclass 13, count 0 2006.286.05:29:47.05#ibcon#about to read 3, iclass 13, count 0 2006.286.05:29:47.08#ibcon#read 3, iclass 13, count 0 2006.286.05:29:47.08#ibcon#about to read 4, iclass 13, count 0 2006.286.05:29:47.08#ibcon#read 4, iclass 13, count 0 2006.286.05:29:47.08#ibcon#about to read 5, iclass 13, count 0 2006.286.05:29:47.08#ibcon#read 5, iclass 13, count 0 2006.286.05:29:47.08#ibcon#about to read 6, iclass 13, count 0 2006.286.05:29:47.08#ibcon#read 6, iclass 13, count 0 2006.286.05:29:47.08#ibcon#end of sib2, iclass 13, count 0 2006.286.05:29:47.08#ibcon#*after write, iclass 13, count 0 2006.286.05:29:47.08#ibcon#*before return 0, iclass 13, count 0 2006.286.05:29:47.08#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:29:47.08#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.286.05:29:47.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.05:29:47.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.05:29:47.08$vck44/vblo=5,709.99 2006.286.05:29:47.08#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.286.05:29:47.08#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.286.05:29:47.08#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:47.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:29:47.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:29:47.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:29:47.08#ibcon#enter wrdev, iclass 15, count 0 2006.286.05:29:47.08#ibcon#first serial, iclass 15, count 0 2006.286.05:29:47.08#ibcon#enter sib2, iclass 15, count 0 2006.286.05:29:47.08#ibcon#flushed, iclass 15, count 0 2006.286.05:29:47.08#ibcon#about to write, iclass 15, count 0 2006.286.05:29:47.08#ibcon#wrote, iclass 15, count 0 2006.286.05:29:47.08#ibcon#about to read 3, iclass 15, count 0 2006.286.05:29:47.10#ibcon#read 3, iclass 15, count 0 2006.286.05:29:47.10#ibcon#about to read 4, iclass 15, count 0 2006.286.05:29:47.10#ibcon#read 4, iclass 15, count 0 2006.286.05:29:47.10#ibcon#about to read 5, iclass 15, count 0 2006.286.05:29:47.10#ibcon#read 5, iclass 15, count 0 2006.286.05:29:47.10#ibcon#about to read 6, iclass 15, count 0 2006.286.05:29:47.10#ibcon#read 6, iclass 15, count 0 2006.286.05:29:47.10#ibcon#end of sib2, iclass 15, count 0 2006.286.05:29:47.10#ibcon#*mode == 0, iclass 15, count 0 2006.286.05:29:47.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.05:29:47.10#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.05:29:47.10#ibcon#*before write, iclass 15, count 0 2006.286.05:29:47.10#ibcon#enter sib2, iclass 15, count 0 2006.286.05:29:47.10#ibcon#flushed, iclass 15, count 0 2006.286.05:29:47.10#ibcon#about to write, iclass 15, count 0 2006.286.05:29:47.10#ibcon#wrote, iclass 15, count 0 2006.286.05:29:47.10#ibcon#about to read 3, iclass 15, count 0 2006.286.05:29:47.14#ibcon#read 3, iclass 15, count 0 2006.286.05:29:47.14#ibcon#about to read 4, iclass 15, count 0 2006.286.05:29:47.14#ibcon#read 4, iclass 15, count 0 2006.286.05:29:47.14#ibcon#about to read 5, iclass 15, count 0 2006.286.05:29:47.14#ibcon#read 5, iclass 15, count 0 2006.286.05:29:47.14#ibcon#about to read 6, iclass 15, count 0 2006.286.05:29:47.14#ibcon#read 6, iclass 15, count 0 2006.286.05:29:47.14#ibcon#end of sib2, iclass 15, count 0 2006.286.05:29:47.14#ibcon#*after write, iclass 15, count 0 2006.286.05:29:47.14#ibcon#*before return 0, iclass 15, count 0 2006.286.05:29:47.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:29:47.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.286.05:29:47.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.05:29:47.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.05:29:47.14$vck44/vb=5,4 2006.286.05:29:47.14#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.286.05:29:47.14#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.286.05:29:47.14#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:47.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:29:47.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:29:47.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:29:47.20#ibcon#enter wrdev, iclass 17, count 2 2006.286.05:29:47.20#ibcon#first serial, iclass 17, count 2 2006.286.05:29:47.20#ibcon#enter sib2, iclass 17, count 2 2006.286.05:29:47.20#ibcon#flushed, iclass 17, count 2 2006.286.05:29:47.20#ibcon#about to write, iclass 17, count 2 2006.286.05:29:47.20#ibcon#wrote, iclass 17, count 2 2006.286.05:29:47.20#ibcon#about to read 3, iclass 17, count 2 2006.286.05:29:47.22#ibcon#read 3, iclass 17, count 2 2006.286.05:29:47.22#ibcon#about to read 4, iclass 17, count 2 2006.286.05:29:47.22#ibcon#read 4, iclass 17, count 2 2006.286.05:29:47.22#ibcon#about to read 5, iclass 17, count 2 2006.286.05:29:47.22#ibcon#read 5, iclass 17, count 2 2006.286.05:29:47.22#ibcon#about to read 6, iclass 17, count 2 2006.286.05:29:47.22#ibcon#read 6, iclass 17, count 2 2006.286.05:29:47.22#ibcon#end of sib2, iclass 17, count 2 2006.286.05:29:47.22#ibcon#*mode == 0, iclass 17, count 2 2006.286.05:29:47.22#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.286.05:29:47.22#ibcon#[27=AT05-04\r\n] 2006.286.05:29:47.22#ibcon#*before write, iclass 17, count 2 2006.286.05:29:47.22#ibcon#enter sib2, iclass 17, count 2 2006.286.05:29:47.22#ibcon#flushed, iclass 17, count 2 2006.286.05:29:47.22#ibcon#about to write, iclass 17, count 2 2006.286.05:29:47.22#ibcon#wrote, iclass 17, count 2 2006.286.05:29:47.22#ibcon#about to read 3, iclass 17, count 2 2006.286.05:29:47.25#ibcon#read 3, iclass 17, count 2 2006.286.05:29:47.25#ibcon#about to read 4, iclass 17, count 2 2006.286.05:29:47.25#ibcon#read 4, iclass 17, count 2 2006.286.05:29:47.25#ibcon#about to read 5, iclass 17, count 2 2006.286.05:29:47.25#ibcon#read 5, iclass 17, count 2 2006.286.05:29:47.25#ibcon#about to read 6, iclass 17, count 2 2006.286.05:29:47.25#ibcon#read 6, iclass 17, count 2 2006.286.05:29:47.25#ibcon#end of sib2, iclass 17, count 2 2006.286.05:29:47.25#ibcon#*after write, iclass 17, count 2 2006.286.05:29:47.25#ibcon#*before return 0, iclass 17, count 2 2006.286.05:29:47.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:29:47.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.286.05:29:47.25#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.286.05:29:47.25#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:47.25#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:29:47.37#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:29:47.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:29:47.43#ibcon#enter wrdev, iclass 17, count 0 2006.286.05:29:47.43#ibcon#first serial, iclass 17, count 0 2006.286.05:29:47.43#ibcon#enter sib2, iclass 17, count 0 2006.286.05:29:47.43#ibcon#flushed, iclass 17, count 0 2006.286.05:29:47.43#ibcon#about to write, iclass 17, count 0 2006.286.05:29:47.43#ibcon#wrote, iclass 17, count 0 2006.286.05:29:47.43#ibcon#about to read 3, iclass 17, count 0 2006.286.05:29:47.44#ibcon#read 3, iclass 17, count 0 2006.286.05:29:47.44#ibcon#about to read 4, iclass 17, count 0 2006.286.05:29:47.44#ibcon#read 4, iclass 17, count 0 2006.286.05:29:47.44#ibcon#about to read 5, iclass 17, count 0 2006.286.05:29:47.44#ibcon#read 5, iclass 17, count 0 2006.286.05:29:47.44#ibcon#about to read 6, iclass 17, count 0 2006.286.05:29:47.44#ibcon#read 6, iclass 17, count 0 2006.286.05:29:47.44#ibcon#end of sib2, iclass 17, count 0 2006.286.05:29:47.44#ibcon#*mode == 0, iclass 17, count 0 2006.286.05:29:47.44#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.05:29:47.44#ibcon#[27=USB\r\n] 2006.286.05:29:47.44#ibcon#*before write, iclass 17, count 0 2006.286.05:29:47.44#ibcon#enter sib2, iclass 17, count 0 2006.286.05:29:47.44#ibcon#flushed, iclass 17, count 0 2006.286.05:29:47.44#ibcon#about to write, iclass 17, count 0 2006.286.05:29:47.44#ibcon#wrote, iclass 17, count 0 2006.286.05:29:47.44#ibcon#about to read 3, iclass 17, count 0 2006.286.05:29:47.47#ibcon#read 3, iclass 17, count 0 2006.286.05:29:47.47#ibcon#about to read 4, iclass 17, count 0 2006.286.05:29:47.47#ibcon#read 4, iclass 17, count 0 2006.286.05:29:47.47#ibcon#about to read 5, iclass 17, count 0 2006.286.05:29:47.47#ibcon#read 5, iclass 17, count 0 2006.286.05:29:47.47#ibcon#about to read 6, iclass 17, count 0 2006.286.05:29:47.47#ibcon#read 6, iclass 17, count 0 2006.286.05:29:47.47#ibcon#end of sib2, iclass 17, count 0 2006.286.05:29:47.47#ibcon#*after write, iclass 17, count 0 2006.286.05:29:47.47#ibcon#*before return 0, iclass 17, count 0 2006.286.05:29:47.47#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:29:47.47#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.286.05:29:47.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.05:29:47.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.05:29:47.47$vck44/vblo=6,719.99 2006.286.05:29:47.47#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.05:29:47.47#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.05:29:47.47#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:47.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:29:47.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:29:47.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:29:47.47#ibcon#enter wrdev, iclass 19, count 0 2006.286.05:29:47.47#ibcon#first serial, iclass 19, count 0 2006.286.05:29:47.47#ibcon#enter sib2, iclass 19, count 0 2006.286.05:29:47.47#ibcon#flushed, iclass 19, count 0 2006.286.05:29:47.47#ibcon#about to write, iclass 19, count 0 2006.286.05:29:47.47#ibcon#wrote, iclass 19, count 0 2006.286.05:29:47.47#ibcon#about to read 3, iclass 19, count 0 2006.286.05:29:47.49#ibcon#read 3, iclass 19, count 0 2006.286.05:29:47.49#ibcon#about to read 4, iclass 19, count 0 2006.286.05:29:47.49#ibcon#read 4, iclass 19, count 0 2006.286.05:29:47.49#ibcon#about to read 5, iclass 19, count 0 2006.286.05:29:47.49#ibcon#read 5, iclass 19, count 0 2006.286.05:29:47.49#ibcon#about to read 6, iclass 19, count 0 2006.286.05:29:47.49#ibcon#read 6, iclass 19, count 0 2006.286.05:29:47.49#ibcon#end of sib2, iclass 19, count 0 2006.286.05:29:47.49#ibcon#*mode == 0, iclass 19, count 0 2006.286.05:29:47.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.05:29:47.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.05:29:47.49#ibcon#*before write, iclass 19, count 0 2006.286.05:29:47.49#ibcon#enter sib2, iclass 19, count 0 2006.286.05:29:47.49#ibcon#flushed, iclass 19, count 0 2006.286.05:29:47.49#ibcon#about to write, iclass 19, count 0 2006.286.05:29:47.49#ibcon#wrote, iclass 19, count 0 2006.286.05:29:47.49#ibcon#about to read 3, iclass 19, count 0 2006.286.05:29:47.53#ibcon#read 3, iclass 19, count 0 2006.286.05:29:47.53#ibcon#about to read 4, iclass 19, count 0 2006.286.05:29:47.53#ibcon#read 4, iclass 19, count 0 2006.286.05:29:47.53#ibcon#about to read 5, iclass 19, count 0 2006.286.05:29:47.53#ibcon#read 5, iclass 19, count 0 2006.286.05:29:47.53#ibcon#about to read 6, iclass 19, count 0 2006.286.05:29:47.53#ibcon#read 6, iclass 19, count 0 2006.286.05:29:47.53#ibcon#end of sib2, iclass 19, count 0 2006.286.05:29:47.53#ibcon#*after write, iclass 19, count 0 2006.286.05:29:47.53#ibcon#*before return 0, iclass 19, count 0 2006.286.05:29:47.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:29:47.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:29:47.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.05:29:47.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.05:29:47.53$vck44/vb=6,3 2006.286.05:29:47.53#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.286.05:29:47.53#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.286.05:29:47.53#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:47.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:29:47.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:29:47.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:29:47.59#ibcon#enter wrdev, iclass 21, count 2 2006.286.05:29:47.59#ibcon#first serial, iclass 21, count 2 2006.286.05:29:47.59#ibcon#enter sib2, iclass 21, count 2 2006.286.05:29:47.59#ibcon#flushed, iclass 21, count 2 2006.286.05:29:47.59#ibcon#about to write, iclass 21, count 2 2006.286.05:29:47.59#ibcon#wrote, iclass 21, count 2 2006.286.05:29:47.59#ibcon#about to read 3, iclass 21, count 2 2006.286.05:29:47.61#ibcon#read 3, iclass 21, count 2 2006.286.05:29:47.61#ibcon#about to read 4, iclass 21, count 2 2006.286.05:29:47.61#ibcon#read 4, iclass 21, count 2 2006.286.05:29:47.61#ibcon#about to read 5, iclass 21, count 2 2006.286.05:29:47.61#ibcon#read 5, iclass 21, count 2 2006.286.05:29:47.61#ibcon#about to read 6, iclass 21, count 2 2006.286.05:29:47.61#ibcon#read 6, iclass 21, count 2 2006.286.05:29:47.61#ibcon#end of sib2, iclass 21, count 2 2006.286.05:29:47.61#ibcon#*mode == 0, iclass 21, count 2 2006.286.05:29:47.61#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.286.05:29:47.61#ibcon#[27=AT06-03\r\n] 2006.286.05:29:47.61#ibcon#*before write, iclass 21, count 2 2006.286.05:29:47.61#ibcon#enter sib2, iclass 21, count 2 2006.286.05:29:47.61#ibcon#flushed, iclass 21, count 2 2006.286.05:29:47.61#ibcon#about to write, iclass 21, count 2 2006.286.05:29:47.61#ibcon#wrote, iclass 21, count 2 2006.286.05:29:47.61#ibcon#about to read 3, iclass 21, count 2 2006.286.05:29:47.64#ibcon#read 3, iclass 21, count 2 2006.286.05:29:47.64#ibcon#about to read 4, iclass 21, count 2 2006.286.05:29:47.64#ibcon#read 4, iclass 21, count 2 2006.286.05:29:47.64#ibcon#about to read 5, iclass 21, count 2 2006.286.05:29:47.64#ibcon#read 5, iclass 21, count 2 2006.286.05:29:47.64#ibcon#about to read 6, iclass 21, count 2 2006.286.05:29:47.64#ibcon#read 6, iclass 21, count 2 2006.286.05:29:47.64#ibcon#end of sib2, iclass 21, count 2 2006.286.05:29:47.64#ibcon#*after write, iclass 21, count 2 2006.286.05:29:47.64#ibcon#*before return 0, iclass 21, count 2 2006.286.05:29:47.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:29:47.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.286.05:29:47.64#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.286.05:29:47.64#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:47.64#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:29:47.76#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:29:47.76#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:29:47.76#ibcon#enter wrdev, iclass 21, count 0 2006.286.05:29:47.76#ibcon#first serial, iclass 21, count 0 2006.286.05:29:47.76#ibcon#enter sib2, iclass 21, count 0 2006.286.05:29:47.76#ibcon#flushed, iclass 21, count 0 2006.286.05:29:47.76#ibcon#about to write, iclass 21, count 0 2006.286.05:29:47.76#ibcon#wrote, iclass 21, count 0 2006.286.05:29:47.76#ibcon#about to read 3, iclass 21, count 0 2006.286.05:29:47.78#ibcon#read 3, iclass 21, count 0 2006.286.05:29:47.78#ibcon#about to read 4, iclass 21, count 0 2006.286.05:29:47.78#ibcon#read 4, iclass 21, count 0 2006.286.05:29:47.78#ibcon#about to read 5, iclass 21, count 0 2006.286.05:29:47.78#ibcon#read 5, iclass 21, count 0 2006.286.05:29:47.78#ibcon#about to read 6, iclass 21, count 0 2006.286.05:29:47.78#ibcon#read 6, iclass 21, count 0 2006.286.05:29:47.78#ibcon#end of sib2, iclass 21, count 0 2006.286.05:29:47.78#ibcon#*mode == 0, iclass 21, count 0 2006.286.05:29:47.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.05:29:47.78#ibcon#[27=USB\r\n] 2006.286.05:29:47.78#ibcon#*before write, iclass 21, count 0 2006.286.05:29:47.78#ibcon#enter sib2, iclass 21, count 0 2006.286.05:29:47.78#ibcon#flushed, iclass 21, count 0 2006.286.05:29:47.78#ibcon#about to write, iclass 21, count 0 2006.286.05:29:47.78#ibcon#wrote, iclass 21, count 0 2006.286.05:29:47.78#ibcon#about to read 3, iclass 21, count 0 2006.286.05:29:47.81#ibcon#read 3, iclass 21, count 0 2006.286.05:29:47.81#ibcon#about to read 4, iclass 21, count 0 2006.286.05:29:47.81#ibcon#read 4, iclass 21, count 0 2006.286.05:29:47.81#ibcon#about to read 5, iclass 21, count 0 2006.286.05:29:47.81#ibcon#read 5, iclass 21, count 0 2006.286.05:29:47.81#ibcon#about to read 6, iclass 21, count 0 2006.286.05:29:47.81#ibcon#read 6, iclass 21, count 0 2006.286.05:29:47.81#ibcon#end of sib2, iclass 21, count 0 2006.286.05:29:47.81#ibcon#*after write, iclass 21, count 0 2006.286.05:29:47.81#ibcon#*before return 0, iclass 21, count 0 2006.286.05:29:47.81#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:29:47.81#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.286.05:29:47.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.05:29:47.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.05:29:47.81$vck44/vblo=7,734.99 2006.286.05:29:47.81#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.05:29:47.81#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.05:29:47.81#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:47.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:29:47.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:29:47.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:29:47.81#ibcon#enter wrdev, iclass 23, count 0 2006.286.05:29:47.81#ibcon#first serial, iclass 23, count 0 2006.286.05:29:47.81#ibcon#enter sib2, iclass 23, count 0 2006.286.05:29:47.81#ibcon#flushed, iclass 23, count 0 2006.286.05:29:47.81#ibcon#about to write, iclass 23, count 0 2006.286.05:29:47.81#ibcon#wrote, iclass 23, count 0 2006.286.05:29:47.81#ibcon#about to read 3, iclass 23, count 0 2006.286.05:29:47.83#ibcon#read 3, iclass 23, count 0 2006.286.05:29:47.83#ibcon#about to read 4, iclass 23, count 0 2006.286.05:29:47.83#ibcon#read 4, iclass 23, count 0 2006.286.05:29:47.83#ibcon#about to read 5, iclass 23, count 0 2006.286.05:29:47.83#ibcon#read 5, iclass 23, count 0 2006.286.05:29:47.83#ibcon#about to read 6, iclass 23, count 0 2006.286.05:29:47.83#ibcon#read 6, iclass 23, count 0 2006.286.05:29:47.83#ibcon#end of sib2, iclass 23, count 0 2006.286.05:29:47.83#ibcon#*mode == 0, iclass 23, count 0 2006.286.05:29:47.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.05:29:47.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.05:29:47.83#ibcon#*before write, iclass 23, count 0 2006.286.05:29:47.83#ibcon#enter sib2, iclass 23, count 0 2006.286.05:29:47.83#ibcon#flushed, iclass 23, count 0 2006.286.05:29:47.83#ibcon#about to write, iclass 23, count 0 2006.286.05:29:47.83#ibcon#wrote, iclass 23, count 0 2006.286.05:29:47.83#ibcon#about to read 3, iclass 23, count 0 2006.286.05:29:47.87#ibcon#read 3, iclass 23, count 0 2006.286.05:29:47.87#ibcon#about to read 4, iclass 23, count 0 2006.286.05:29:47.87#ibcon#read 4, iclass 23, count 0 2006.286.05:29:47.87#ibcon#about to read 5, iclass 23, count 0 2006.286.05:29:47.87#ibcon#read 5, iclass 23, count 0 2006.286.05:29:47.87#ibcon#about to read 6, iclass 23, count 0 2006.286.05:29:47.87#ibcon#read 6, iclass 23, count 0 2006.286.05:29:47.87#ibcon#end of sib2, iclass 23, count 0 2006.286.05:29:47.87#ibcon#*after write, iclass 23, count 0 2006.286.05:29:47.87#ibcon#*before return 0, iclass 23, count 0 2006.286.05:29:47.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:29:47.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:29:47.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.05:29:47.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.05:29:47.87$vck44/vb=7,4 2006.286.05:29:47.87#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.286.05:29:47.87#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.286.05:29:47.87#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:47.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:29:47.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:29:47.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:29:47.93#ibcon#enter wrdev, iclass 25, count 2 2006.286.05:29:47.93#ibcon#first serial, iclass 25, count 2 2006.286.05:29:47.93#ibcon#enter sib2, iclass 25, count 2 2006.286.05:29:47.93#ibcon#flushed, iclass 25, count 2 2006.286.05:29:47.93#ibcon#about to write, iclass 25, count 2 2006.286.05:29:47.93#ibcon#wrote, iclass 25, count 2 2006.286.05:29:47.93#ibcon#about to read 3, iclass 25, count 2 2006.286.05:29:47.95#ibcon#read 3, iclass 25, count 2 2006.286.05:29:47.95#ibcon#about to read 4, iclass 25, count 2 2006.286.05:29:47.95#ibcon#read 4, iclass 25, count 2 2006.286.05:29:47.95#ibcon#about to read 5, iclass 25, count 2 2006.286.05:29:47.95#ibcon#read 5, iclass 25, count 2 2006.286.05:29:47.95#ibcon#about to read 6, iclass 25, count 2 2006.286.05:29:47.95#ibcon#read 6, iclass 25, count 2 2006.286.05:29:47.95#ibcon#end of sib2, iclass 25, count 2 2006.286.05:29:47.95#ibcon#*mode == 0, iclass 25, count 2 2006.286.05:29:47.95#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.286.05:29:47.95#ibcon#[27=AT07-04\r\n] 2006.286.05:29:47.95#ibcon#*before write, iclass 25, count 2 2006.286.05:29:47.95#ibcon#enter sib2, iclass 25, count 2 2006.286.05:29:47.95#ibcon#flushed, iclass 25, count 2 2006.286.05:29:47.95#ibcon#about to write, iclass 25, count 2 2006.286.05:29:47.95#ibcon#wrote, iclass 25, count 2 2006.286.05:29:47.95#ibcon#about to read 3, iclass 25, count 2 2006.286.05:29:47.98#ibcon#read 3, iclass 25, count 2 2006.286.05:29:47.98#ibcon#about to read 4, iclass 25, count 2 2006.286.05:29:47.98#ibcon#read 4, iclass 25, count 2 2006.286.05:29:47.98#ibcon#about to read 5, iclass 25, count 2 2006.286.05:29:47.98#ibcon#read 5, iclass 25, count 2 2006.286.05:29:47.98#ibcon#about to read 6, iclass 25, count 2 2006.286.05:29:47.98#ibcon#read 6, iclass 25, count 2 2006.286.05:29:47.98#ibcon#end of sib2, iclass 25, count 2 2006.286.05:29:47.98#ibcon#*after write, iclass 25, count 2 2006.286.05:29:47.98#ibcon#*before return 0, iclass 25, count 2 2006.286.05:29:47.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:29:47.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.286.05:29:47.98#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.286.05:29:47.98#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:47.98#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:29:48.10#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:29:48.10#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:29:48.10#ibcon#enter wrdev, iclass 25, count 0 2006.286.05:29:48.10#ibcon#first serial, iclass 25, count 0 2006.286.05:29:48.10#ibcon#enter sib2, iclass 25, count 0 2006.286.05:29:48.10#ibcon#flushed, iclass 25, count 0 2006.286.05:29:48.10#ibcon#about to write, iclass 25, count 0 2006.286.05:29:48.10#ibcon#wrote, iclass 25, count 0 2006.286.05:29:48.10#ibcon#about to read 3, iclass 25, count 0 2006.286.05:29:48.12#ibcon#read 3, iclass 25, count 0 2006.286.05:29:48.12#ibcon#about to read 4, iclass 25, count 0 2006.286.05:29:48.12#ibcon#read 4, iclass 25, count 0 2006.286.05:29:48.12#ibcon#about to read 5, iclass 25, count 0 2006.286.05:29:48.12#ibcon#read 5, iclass 25, count 0 2006.286.05:29:48.12#ibcon#about to read 6, iclass 25, count 0 2006.286.05:29:48.12#ibcon#read 6, iclass 25, count 0 2006.286.05:29:48.12#ibcon#end of sib2, iclass 25, count 0 2006.286.05:29:48.12#ibcon#*mode == 0, iclass 25, count 0 2006.286.05:29:48.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.05:29:48.12#ibcon#[27=USB\r\n] 2006.286.05:29:48.12#ibcon#*before write, iclass 25, count 0 2006.286.05:29:48.12#ibcon#enter sib2, iclass 25, count 0 2006.286.05:29:48.12#ibcon#flushed, iclass 25, count 0 2006.286.05:29:48.12#ibcon#about to write, iclass 25, count 0 2006.286.05:29:48.12#ibcon#wrote, iclass 25, count 0 2006.286.05:29:48.12#ibcon#about to read 3, iclass 25, count 0 2006.286.05:29:48.15#ibcon#read 3, iclass 25, count 0 2006.286.05:29:48.15#ibcon#about to read 4, iclass 25, count 0 2006.286.05:29:48.15#ibcon#read 4, iclass 25, count 0 2006.286.05:29:48.15#ibcon#about to read 5, iclass 25, count 0 2006.286.05:29:48.15#ibcon#read 5, iclass 25, count 0 2006.286.05:29:48.15#ibcon#about to read 6, iclass 25, count 0 2006.286.05:29:48.15#ibcon#read 6, iclass 25, count 0 2006.286.05:29:48.15#ibcon#end of sib2, iclass 25, count 0 2006.286.05:29:48.15#ibcon#*after write, iclass 25, count 0 2006.286.05:29:48.15#ibcon#*before return 0, iclass 25, count 0 2006.286.05:29:48.15#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:29:48.15#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.286.05:29:48.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.05:29:48.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.05:29:48.15$vck44/vblo=8,744.99 2006.286.05:29:48.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.286.05:29:48.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.286.05:29:48.15#ibcon#ireg 17 cls_cnt 0 2006.286.05:29:48.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:29:48.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:29:48.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:29:48.15#ibcon#enter wrdev, iclass 27, count 0 2006.286.05:29:48.15#ibcon#first serial, iclass 27, count 0 2006.286.05:29:48.15#ibcon#enter sib2, iclass 27, count 0 2006.286.05:29:48.15#ibcon#flushed, iclass 27, count 0 2006.286.05:29:48.15#ibcon#about to write, iclass 27, count 0 2006.286.05:29:48.15#ibcon#wrote, iclass 27, count 0 2006.286.05:29:48.15#ibcon#about to read 3, iclass 27, count 0 2006.286.05:29:48.17#ibcon#read 3, iclass 27, count 0 2006.286.05:29:48.17#ibcon#about to read 4, iclass 27, count 0 2006.286.05:29:48.17#ibcon#read 4, iclass 27, count 0 2006.286.05:29:48.17#ibcon#about to read 5, iclass 27, count 0 2006.286.05:29:48.17#ibcon#read 5, iclass 27, count 0 2006.286.05:29:48.17#ibcon#about to read 6, iclass 27, count 0 2006.286.05:29:48.17#ibcon#read 6, iclass 27, count 0 2006.286.05:29:48.17#ibcon#end of sib2, iclass 27, count 0 2006.286.05:29:48.17#ibcon#*mode == 0, iclass 27, count 0 2006.286.05:29:48.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.05:29:48.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.05:29:48.17#ibcon#*before write, iclass 27, count 0 2006.286.05:29:48.17#ibcon#enter sib2, iclass 27, count 0 2006.286.05:29:48.17#ibcon#flushed, iclass 27, count 0 2006.286.05:29:48.17#ibcon#about to write, iclass 27, count 0 2006.286.05:29:48.17#ibcon#wrote, iclass 27, count 0 2006.286.05:29:48.17#ibcon#about to read 3, iclass 27, count 0 2006.286.05:29:48.21#ibcon#read 3, iclass 27, count 0 2006.286.05:29:48.21#ibcon#about to read 4, iclass 27, count 0 2006.286.05:29:48.21#ibcon#read 4, iclass 27, count 0 2006.286.05:29:48.21#ibcon#about to read 5, iclass 27, count 0 2006.286.05:29:48.21#ibcon#read 5, iclass 27, count 0 2006.286.05:29:48.21#ibcon#about to read 6, iclass 27, count 0 2006.286.05:29:48.21#ibcon#read 6, iclass 27, count 0 2006.286.05:29:48.21#ibcon#end of sib2, iclass 27, count 0 2006.286.05:29:48.21#ibcon#*after write, iclass 27, count 0 2006.286.05:29:48.21#ibcon#*before return 0, iclass 27, count 0 2006.286.05:29:48.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:29:48.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.286.05:29:48.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.05:29:48.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.05:29:48.21$vck44/vb=8,4 2006.286.05:29:48.21#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.05:29:48.21#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.05:29:48.21#ibcon#ireg 11 cls_cnt 2 2006.286.05:29:48.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:29:48.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:29:48.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:29:48.27#ibcon#enter wrdev, iclass 29, count 2 2006.286.05:29:48.27#ibcon#first serial, iclass 29, count 2 2006.286.05:29:48.27#ibcon#enter sib2, iclass 29, count 2 2006.286.05:29:48.27#ibcon#flushed, iclass 29, count 2 2006.286.05:29:48.27#ibcon#about to write, iclass 29, count 2 2006.286.05:29:48.27#ibcon#wrote, iclass 29, count 2 2006.286.05:29:48.27#ibcon#about to read 3, iclass 29, count 2 2006.286.05:29:48.29#ibcon#read 3, iclass 29, count 2 2006.286.05:29:48.29#ibcon#about to read 4, iclass 29, count 2 2006.286.05:29:48.29#ibcon#read 4, iclass 29, count 2 2006.286.05:29:48.29#ibcon#about to read 5, iclass 29, count 2 2006.286.05:29:48.29#ibcon#read 5, iclass 29, count 2 2006.286.05:29:48.29#ibcon#about to read 6, iclass 29, count 2 2006.286.05:29:48.29#ibcon#read 6, iclass 29, count 2 2006.286.05:29:48.29#ibcon#end of sib2, iclass 29, count 2 2006.286.05:29:48.29#ibcon#*mode == 0, iclass 29, count 2 2006.286.05:29:48.29#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.05:29:48.29#ibcon#[27=AT08-04\r\n] 2006.286.05:29:48.29#ibcon#*before write, iclass 29, count 2 2006.286.05:29:48.29#ibcon#enter sib2, iclass 29, count 2 2006.286.05:29:48.29#ibcon#flushed, iclass 29, count 2 2006.286.05:29:48.29#ibcon#about to write, iclass 29, count 2 2006.286.05:29:48.29#ibcon#wrote, iclass 29, count 2 2006.286.05:29:48.29#ibcon#about to read 3, iclass 29, count 2 2006.286.05:29:48.32#ibcon#read 3, iclass 29, count 2 2006.286.05:29:48.32#ibcon#about to read 4, iclass 29, count 2 2006.286.05:29:48.32#ibcon#read 4, iclass 29, count 2 2006.286.05:29:48.32#ibcon#about to read 5, iclass 29, count 2 2006.286.05:29:48.32#ibcon#read 5, iclass 29, count 2 2006.286.05:29:48.32#ibcon#about to read 6, iclass 29, count 2 2006.286.05:29:48.32#ibcon#read 6, iclass 29, count 2 2006.286.05:29:48.32#ibcon#end of sib2, iclass 29, count 2 2006.286.05:29:48.32#ibcon#*after write, iclass 29, count 2 2006.286.05:29:48.32#ibcon#*before return 0, iclass 29, count 2 2006.286.05:29:48.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:29:48.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:29:48.32#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.05:29:48.32#ibcon#ireg 7 cls_cnt 0 2006.286.05:29:48.32#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:29:48.44#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:29:48.44#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:29:48.44#ibcon#enter wrdev, iclass 29, count 0 2006.286.05:29:48.44#ibcon#first serial, iclass 29, count 0 2006.286.05:29:48.44#ibcon#enter sib2, iclass 29, count 0 2006.286.05:29:48.44#ibcon#flushed, iclass 29, count 0 2006.286.05:29:48.44#ibcon#about to write, iclass 29, count 0 2006.286.05:29:48.44#ibcon#wrote, iclass 29, count 0 2006.286.05:29:48.44#ibcon#about to read 3, iclass 29, count 0 2006.286.05:29:48.46#ibcon#read 3, iclass 29, count 0 2006.286.05:29:48.46#ibcon#about to read 4, iclass 29, count 0 2006.286.05:29:48.46#ibcon#read 4, iclass 29, count 0 2006.286.05:29:48.46#ibcon#about to read 5, iclass 29, count 0 2006.286.05:29:48.46#ibcon#read 5, iclass 29, count 0 2006.286.05:29:48.46#ibcon#about to read 6, iclass 29, count 0 2006.286.05:29:48.46#ibcon#read 6, iclass 29, count 0 2006.286.05:29:48.46#ibcon#end of sib2, iclass 29, count 0 2006.286.05:29:48.46#ibcon#*mode == 0, iclass 29, count 0 2006.286.05:29:48.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.05:29:48.46#ibcon#[27=USB\r\n] 2006.286.05:29:48.46#ibcon#*before write, iclass 29, count 0 2006.286.05:29:48.46#ibcon#enter sib2, iclass 29, count 0 2006.286.05:29:48.46#ibcon#flushed, iclass 29, count 0 2006.286.05:29:48.46#ibcon#about to write, iclass 29, count 0 2006.286.05:29:48.46#ibcon#wrote, iclass 29, count 0 2006.286.05:29:48.46#ibcon#about to read 3, iclass 29, count 0 2006.286.05:29:48.49#ibcon#read 3, iclass 29, count 0 2006.286.05:29:48.49#ibcon#about to read 4, iclass 29, count 0 2006.286.05:29:48.49#ibcon#read 4, iclass 29, count 0 2006.286.05:29:48.49#ibcon#about to read 5, iclass 29, count 0 2006.286.05:29:48.49#ibcon#read 5, iclass 29, count 0 2006.286.05:29:48.49#ibcon#about to read 6, iclass 29, count 0 2006.286.05:29:48.49#ibcon#read 6, iclass 29, count 0 2006.286.05:29:48.49#ibcon#end of sib2, iclass 29, count 0 2006.286.05:29:48.49#ibcon#*after write, iclass 29, count 0 2006.286.05:29:48.49#ibcon#*before return 0, iclass 29, count 0 2006.286.05:29:48.49#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:29:48.49#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:29:48.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.05:29:48.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.05:29:48.49$vck44/vabw=wide 2006.286.05:29:48.49#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.286.05:29:48.49#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.286.05:29:48.49#ibcon#ireg 8 cls_cnt 0 2006.286.05:29:48.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:29:48.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:29:48.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:29:48.49#ibcon#enter wrdev, iclass 31, count 0 2006.286.05:29:48.49#ibcon#first serial, iclass 31, count 0 2006.286.05:29:48.49#ibcon#enter sib2, iclass 31, count 0 2006.286.05:29:48.49#ibcon#flushed, iclass 31, count 0 2006.286.05:29:48.49#ibcon#about to write, iclass 31, count 0 2006.286.05:29:48.49#ibcon#wrote, iclass 31, count 0 2006.286.05:29:48.49#ibcon#about to read 3, iclass 31, count 0 2006.286.05:29:48.51#ibcon#read 3, iclass 31, count 0 2006.286.05:29:48.51#ibcon#about to read 4, iclass 31, count 0 2006.286.05:29:48.51#ibcon#read 4, iclass 31, count 0 2006.286.05:29:48.51#ibcon#about to read 5, iclass 31, count 0 2006.286.05:29:48.51#ibcon#read 5, iclass 31, count 0 2006.286.05:29:48.51#ibcon#about to read 6, iclass 31, count 0 2006.286.05:29:48.51#ibcon#read 6, iclass 31, count 0 2006.286.05:29:48.51#ibcon#end of sib2, iclass 31, count 0 2006.286.05:29:48.51#ibcon#*mode == 0, iclass 31, count 0 2006.286.05:29:48.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.05:29:48.51#ibcon#[25=BW32\r\n] 2006.286.05:29:48.51#ibcon#*before write, iclass 31, count 0 2006.286.05:29:48.51#ibcon#enter sib2, iclass 31, count 0 2006.286.05:29:48.51#ibcon#flushed, iclass 31, count 0 2006.286.05:29:48.51#ibcon#about to write, iclass 31, count 0 2006.286.05:29:48.51#ibcon#wrote, iclass 31, count 0 2006.286.05:29:48.51#ibcon#about to read 3, iclass 31, count 0 2006.286.05:29:48.54#ibcon#read 3, iclass 31, count 0 2006.286.05:29:48.54#ibcon#about to read 4, iclass 31, count 0 2006.286.05:29:48.54#ibcon#read 4, iclass 31, count 0 2006.286.05:29:48.54#ibcon#about to read 5, iclass 31, count 0 2006.286.05:29:48.54#ibcon#read 5, iclass 31, count 0 2006.286.05:29:48.54#ibcon#about to read 6, iclass 31, count 0 2006.286.05:29:48.54#ibcon#read 6, iclass 31, count 0 2006.286.05:29:48.54#ibcon#end of sib2, iclass 31, count 0 2006.286.05:29:48.54#ibcon#*after write, iclass 31, count 0 2006.286.05:29:48.54#ibcon#*before return 0, iclass 31, count 0 2006.286.05:29:48.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:29:48.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.286.05:29:48.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.05:29:48.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.05:29:48.54$vck44/vbbw=wide 2006.286.05:29:48.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.05:29:48.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.05:29:48.54#ibcon#ireg 8 cls_cnt 0 2006.286.05:29:48.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:29:48.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:29:48.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:29:48.61#ibcon#enter wrdev, iclass 33, count 0 2006.286.05:29:48.61#ibcon#first serial, iclass 33, count 0 2006.286.05:29:48.61#ibcon#enter sib2, iclass 33, count 0 2006.286.05:29:48.61#ibcon#flushed, iclass 33, count 0 2006.286.05:29:48.61#ibcon#about to write, iclass 33, count 0 2006.286.05:29:48.61#ibcon#wrote, iclass 33, count 0 2006.286.05:29:48.61#ibcon#about to read 3, iclass 33, count 0 2006.286.05:29:48.63#ibcon#read 3, iclass 33, count 0 2006.286.05:29:48.63#ibcon#about to read 4, iclass 33, count 0 2006.286.05:29:48.63#ibcon#read 4, iclass 33, count 0 2006.286.05:29:48.63#ibcon#about to read 5, iclass 33, count 0 2006.286.05:29:48.63#ibcon#read 5, iclass 33, count 0 2006.286.05:29:48.63#ibcon#about to read 6, iclass 33, count 0 2006.286.05:29:48.63#ibcon#read 6, iclass 33, count 0 2006.286.05:29:48.63#ibcon#end of sib2, iclass 33, count 0 2006.286.05:29:48.63#ibcon#*mode == 0, iclass 33, count 0 2006.286.05:29:48.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.05:29:48.63#ibcon#[27=BW32\r\n] 2006.286.05:29:48.63#ibcon#*before write, iclass 33, count 0 2006.286.05:29:48.63#ibcon#enter sib2, iclass 33, count 0 2006.286.05:29:48.63#ibcon#flushed, iclass 33, count 0 2006.286.05:29:48.63#ibcon#about to write, iclass 33, count 0 2006.286.05:29:48.63#ibcon#wrote, iclass 33, count 0 2006.286.05:29:48.63#ibcon#about to read 3, iclass 33, count 0 2006.286.05:29:48.66#ibcon#read 3, iclass 33, count 0 2006.286.05:29:48.66#ibcon#about to read 4, iclass 33, count 0 2006.286.05:29:48.66#ibcon#read 4, iclass 33, count 0 2006.286.05:29:48.66#ibcon#about to read 5, iclass 33, count 0 2006.286.05:29:48.66#ibcon#read 5, iclass 33, count 0 2006.286.05:29:48.66#ibcon#about to read 6, iclass 33, count 0 2006.286.05:29:48.66#ibcon#read 6, iclass 33, count 0 2006.286.05:29:48.66#ibcon#end of sib2, iclass 33, count 0 2006.286.05:29:48.66#ibcon#*after write, iclass 33, count 0 2006.286.05:29:48.66#ibcon#*before return 0, iclass 33, count 0 2006.286.05:29:48.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:29:48.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:29:48.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.05:29:48.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.05:29:48.66$setupk4/ifdk4 2006.286.05:29:48.66$ifdk4/lo= 2006.286.05:29:48.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.05:29:48.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.05:29:48.66$ifdk4/patch= 2006.286.05:29:48.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.05:29:48.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.05:29:48.66$setupk4/!*+20s 2006.286.05:29:55.83#abcon#<5=/04 4.1 7.5 21.21 781015.1\r\n> 2006.286.05:29:55.85#abcon#{5=INTERFACE CLEAR} 2006.286.05:29:55.91#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:30:00.14#trakl#Source acquired 2006.286.05:30:01.91$setupk4/"tpicd 2006.286.05:30:01.91$setupk4/echo=off 2006.286.05:30:01.91$setupk4/xlog=off 2006.286.05:30:01.91:!2006.286.05:30:46 2006.286.05:30:02.14#flagr#flagr/antenna,acquired 2006.286.05:30:46.00:preob 2006.286.05:30:46.13/onsource/TRACKING 2006.286.05:30:46.13:!2006.286.05:30:56 2006.286.05:30:56.00:"tape 2006.286.05:30:56.00:"st=record 2006.286.05:30:56.00:data_valid=on 2006.286.05:30:56.00:midob 2006.286.05:30:56.13/onsource/TRACKING 2006.286.05:30:56.13/wx/21.19,1015.1,78 2006.286.05:30:56.31/cable/+6.4921E-03 2006.286.05:30:57.40/va/01,07,usb,yes,40,43 2006.286.05:30:57.40/va/02,06,usb,yes,40,41 2006.286.05:30:57.40/va/03,07,usb,yes,39,42 2006.286.05:30:57.40/va/04,06,usb,yes,41,43 2006.286.05:30:57.40/va/05,03,usb,yes,41,41 2006.286.05:30:57.40/va/06,04,usb,yes,37,36 2006.286.05:30:57.40/va/07,04,usb,yes,38,38 2006.286.05:30:57.40/va/08,03,usb,yes,39,47 2006.286.05:30:57.63/valo/01,524.99,yes,locked 2006.286.05:30:57.63/valo/02,534.99,yes,locked 2006.286.05:30:57.63/valo/03,564.99,yes,locked 2006.286.05:30:57.63/valo/04,624.99,yes,locked 2006.286.05:30:57.63/valo/05,734.99,yes,locked 2006.286.05:30:57.63/valo/06,814.99,yes,locked 2006.286.05:30:57.63/valo/07,864.99,yes,locked 2006.286.05:30:57.63/valo/08,884.99,yes,locked 2006.286.05:30:58.72/vb/01,04,usb,yes,35,32 2006.286.05:30:58.72/vb/02,05,usb,yes,33,33 2006.286.05:30:58.72/vb/03,04,usb,yes,34,37 2006.286.05:30:58.72/vb/04,05,usb,yes,34,33 2006.286.05:30:58.72/vb/05,04,usb,yes,30,33 2006.286.05:30:58.72/vb/06,03,usb,yes,43,39 2006.286.05:30:58.72/vb/07,04,usb,yes,35,35 2006.286.05:30:58.72/vb/08,04,usb,yes,32,36 2006.286.05:30:58.95/vblo/01,629.99,yes,locked 2006.286.05:30:58.95/vblo/02,634.99,yes,locked 2006.286.05:30:58.95/vblo/03,649.99,yes,locked 2006.286.05:30:58.95/vblo/04,679.99,yes,locked 2006.286.05:30:58.95/vblo/05,709.99,yes,locked 2006.286.05:30:58.95/vblo/06,719.99,yes,locked 2006.286.05:30:58.95/vblo/07,734.99,yes,locked 2006.286.05:30:58.95/vblo/08,744.99,yes,locked 2006.286.05:30:59.10/vabw/8 2006.286.05:30:59.25/vbbw/8 2006.286.05:30:59.46/xfe/off,on,12.0 2006.286.05:30:59.85/ifatt/23,28,28,28 2006.286.05:31:00.08/fmout-gps/S +2.35E-07 2006.286.05:31:00.10:!2006.286.05:31:36 2006.286.05:31:36.01:data_valid=off 2006.286.05:31:36.01:"et 2006.286.05:31:36.01:!+3s 2006.286.05:31:39.02:"tape 2006.286.05:31:39.02:postob 2006.286.05:31:39.12/cable/+6.4917E-03 2006.286.05:31:39.12/wx/21.16,1015.2,79 2006.286.05:31:39.18/fmout-gps/S +2.37E-07 2006.286.05:31:39.18:scan_name=286-0536,jd0610,100 2006.286.05:31:39.18:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.286.05:31:41.13#flagr#flagr/antenna,new-source 2006.286.05:31:41.13:checkk5 2006.286.05:31:41.66/chk_autoobs//k5ts1/ autoobs is running! 2006.286.05:31:42.00/chk_autoobs//k5ts2/ autoobs is running! 2006.286.05:31:42.35/chk_autoobs//k5ts3/ autoobs is running! 2006.286.05:31:42.85/chk_autoobs//k5ts4/ autoobs is running! 2006.286.05:31:43.27/chk_obsdata//k5ts1/T2860530??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.05:31:43.78/chk_obsdata//k5ts2/T2860530??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.05:31:44.16/chk_obsdata//k5ts3/T2860530??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.05:31:44.66/chk_obsdata//k5ts4/T2860530??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.286.05:31:45.37/k5log//k5ts1_log_newline 2006.286.05:31:46.23/k5log//k5ts2_log_newline 2006.286.05:31:47.29/k5log//k5ts3_log_newline 2006.286.05:31:48.13/k5log//k5ts4_log_newline 2006.286.05:31:48.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.05:31:48.15:setupk4=1 2006.286.05:31:48.15$setupk4/echo=on 2006.286.05:31:48.15$setupk4/pcalon 2006.286.05:31:48.15$pcalon/"no phase cal control is implemented here 2006.286.05:31:48.15$setupk4/"tpicd=stop 2006.286.05:31:48.15$setupk4/"rec=synch_on 2006.286.05:31:48.15$setupk4/"rec_mode=128 2006.286.05:31:48.15$setupk4/!* 2006.286.05:31:48.15$setupk4/recpk4 2006.286.05:31:48.15$recpk4/recpatch= 2006.286.05:31:48.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.05:31:48.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.05:31:48.16$setupk4/vck44 2006.286.05:31:48.16$vck44/valo=1,524.99 2006.286.05:31:48.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.05:31:48.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.05:31:48.16#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:48.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:31:48.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:31:48.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:31:48.16#ibcon#enter wrdev, iclass 14, count 0 2006.286.05:31:48.16#ibcon#first serial, iclass 14, count 0 2006.286.05:31:48.16#ibcon#enter sib2, iclass 14, count 0 2006.286.05:31:48.16#ibcon#flushed, iclass 14, count 0 2006.286.05:31:48.16#ibcon#about to write, iclass 14, count 0 2006.286.05:31:48.16#ibcon#wrote, iclass 14, count 0 2006.286.05:31:48.16#ibcon#about to read 3, iclass 14, count 0 2006.286.05:31:48.18#ibcon#read 3, iclass 14, count 0 2006.286.05:31:48.18#ibcon#about to read 4, iclass 14, count 0 2006.286.05:31:48.18#ibcon#read 4, iclass 14, count 0 2006.286.05:31:48.18#ibcon#about to read 5, iclass 14, count 0 2006.286.05:31:48.18#ibcon#read 5, iclass 14, count 0 2006.286.05:31:48.18#ibcon#about to read 6, iclass 14, count 0 2006.286.05:31:48.18#ibcon#read 6, iclass 14, count 0 2006.286.05:31:48.18#ibcon#end of sib2, iclass 14, count 0 2006.286.05:31:48.18#ibcon#*mode == 0, iclass 14, count 0 2006.286.05:31:48.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.05:31:48.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.05:31:48.18#ibcon#*before write, iclass 14, count 0 2006.286.05:31:48.18#ibcon#enter sib2, iclass 14, count 0 2006.286.05:31:48.18#ibcon#flushed, iclass 14, count 0 2006.286.05:31:48.18#ibcon#about to write, iclass 14, count 0 2006.286.05:31:48.18#ibcon#wrote, iclass 14, count 0 2006.286.05:31:48.18#ibcon#about to read 3, iclass 14, count 0 2006.286.05:31:48.23#ibcon#read 3, iclass 14, count 0 2006.286.05:31:48.23#ibcon#about to read 4, iclass 14, count 0 2006.286.05:31:48.23#ibcon#read 4, iclass 14, count 0 2006.286.05:31:48.23#ibcon#about to read 5, iclass 14, count 0 2006.286.05:31:48.23#ibcon#read 5, iclass 14, count 0 2006.286.05:31:48.23#ibcon#about to read 6, iclass 14, count 0 2006.286.05:31:48.23#ibcon#read 6, iclass 14, count 0 2006.286.05:31:48.23#ibcon#end of sib2, iclass 14, count 0 2006.286.05:31:48.23#ibcon#*after write, iclass 14, count 0 2006.286.05:31:48.23#ibcon#*before return 0, iclass 14, count 0 2006.286.05:31:48.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:31:48.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:31:48.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.05:31:48.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.05:31:48.23$vck44/va=1,7 2006.286.05:31:48.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.05:31:48.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.05:31:48.23#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:48.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:31:48.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:31:48.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:31:48.23#ibcon#enter wrdev, iclass 16, count 2 2006.286.05:31:48.23#ibcon#first serial, iclass 16, count 2 2006.286.05:31:48.23#ibcon#enter sib2, iclass 16, count 2 2006.286.05:31:48.23#ibcon#flushed, iclass 16, count 2 2006.286.05:31:48.23#ibcon#about to write, iclass 16, count 2 2006.286.05:31:48.23#ibcon#wrote, iclass 16, count 2 2006.286.05:31:48.23#ibcon#about to read 3, iclass 16, count 2 2006.286.05:31:48.25#ibcon#read 3, iclass 16, count 2 2006.286.05:31:48.25#ibcon#about to read 4, iclass 16, count 2 2006.286.05:31:48.25#ibcon#read 4, iclass 16, count 2 2006.286.05:31:48.25#ibcon#about to read 5, iclass 16, count 2 2006.286.05:31:48.25#ibcon#read 5, iclass 16, count 2 2006.286.05:31:48.25#ibcon#about to read 6, iclass 16, count 2 2006.286.05:31:48.25#ibcon#read 6, iclass 16, count 2 2006.286.05:31:48.25#ibcon#end of sib2, iclass 16, count 2 2006.286.05:31:48.25#ibcon#*mode == 0, iclass 16, count 2 2006.286.05:31:48.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.05:31:48.25#ibcon#[25=AT01-07\r\n] 2006.286.05:31:48.25#ibcon#*before write, iclass 16, count 2 2006.286.05:31:48.25#ibcon#enter sib2, iclass 16, count 2 2006.286.05:31:48.25#ibcon#flushed, iclass 16, count 2 2006.286.05:31:48.25#ibcon#about to write, iclass 16, count 2 2006.286.05:31:48.25#ibcon#wrote, iclass 16, count 2 2006.286.05:31:48.25#ibcon#about to read 3, iclass 16, count 2 2006.286.05:31:48.28#ibcon#read 3, iclass 16, count 2 2006.286.05:31:48.28#ibcon#about to read 4, iclass 16, count 2 2006.286.05:31:48.28#ibcon#read 4, iclass 16, count 2 2006.286.05:31:48.28#ibcon#about to read 5, iclass 16, count 2 2006.286.05:31:48.28#ibcon#read 5, iclass 16, count 2 2006.286.05:31:48.28#ibcon#about to read 6, iclass 16, count 2 2006.286.05:31:48.28#ibcon#read 6, iclass 16, count 2 2006.286.05:31:48.28#ibcon#end of sib2, iclass 16, count 2 2006.286.05:31:48.28#ibcon#*after write, iclass 16, count 2 2006.286.05:31:48.28#ibcon#*before return 0, iclass 16, count 2 2006.286.05:31:48.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:31:48.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:31:48.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.05:31:48.28#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:48.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:31:48.40#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:31:48.40#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:31:48.40#ibcon#enter wrdev, iclass 16, count 0 2006.286.05:31:48.40#ibcon#first serial, iclass 16, count 0 2006.286.05:31:48.40#ibcon#enter sib2, iclass 16, count 0 2006.286.05:31:48.40#ibcon#flushed, iclass 16, count 0 2006.286.05:31:48.40#ibcon#about to write, iclass 16, count 0 2006.286.05:31:48.40#ibcon#wrote, iclass 16, count 0 2006.286.05:31:48.40#ibcon#about to read 3, iclass 16, count 0 2006.286.05:31:48.42#ibcon#read 3, iclass 16, count 0 2006.286.05:31:48.42#ibcon#about to read 4, iclass 16, count 0 2006.286.05:31:48.42#ibcon#read 4, iclass 16, count 0 2006.286.05:31:48.42#ibcon#about to read 5, iclass 16, count 0 2006.286.05:31:48.42#ibcon#read 5, iclass 16, count 0 2006.286.05:31:48.42#ibcon#about to read 6, iclass 16, count 0 2006.286.05:31:48.42#ibcon#read 6, iclass 16, count 0 2006.286.05:31:48.42#ibcon#end of sib2, iclass 16, count 0 2006.286.05:31:48.42#ibcon#*mode == 0, iclass 16, count 0 2006.286.05:31:48.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.05:31:48.42#ibcon#[25=USB\r\n] 2006.286.05:31:48.42#ibcon#*before write, iclass 16, count 0 2006.286.05:31:48.42#ibcon#enter sib2, iclass 16, count 0 2006.286.05:31:48.42#ibcon#flushed, iclass 16, count 0 2006.286.05:31:48.42#ibcon#about to write, iclass 16, count 0 2006.286.05:31:48.42#ibcon#wrote, iclass 16, count 0 2006.286.05:31:48.42#ibcon#about to read 3, iclass 16, count 0 2006.286.05:31:48.45#ibcon#read 3, iclass 16, count 0 2006.286.05:31:48.45#ibcon#about to read 4, iclass 16, count 0 2006.286.05:31:48.45#ibcon#read 4, iclass 16, count 0 2006.286.05:31:48.45#ibcon#about to read 5, iclass 16, count 0 2006.286.05:31:48.45#ibcon#read 5, iclass 16, count 0 2006.286.05:31:48.45#ibcon#about to read 6, iclass 16, count 0 2006.286.05:31:48.45#ibcon#read 6, iclass 16, count 0 2006.286.05:31:48.45#ibcon#end of sib2, iclass 16, count 0 2006.286.05:31:48.45#ibcon#*after write, iclass 16, count 0 2006.286.05:31:48.45#ibcon#*before return 0, iclass 16, count 0 2006.286.05:31:48.45#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:31:48.45#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:31:48.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.05:31:48.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.05:31:48.45$vck44/valo=2,534.99 2006.286.05:31:48.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.05:31:48.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.05:31:48.45#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:48.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:31:48.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:31:48.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:31:48.45#ibcon#enter wrdev, iclass 18, count 0 2006.286.05:31:48.45#ibcon#first serial, iclass 18, count 0 2006.286.05:31:48.45#ibcon#enter sib2, iclass 18, count 0 2006.286.05:31:48.45#ibcon#flushed, iclass 18, count 0 2006.286.05:31:48.45#ibcon#about to write, iclass 18, count 0 2006.286.05:31:48.45#ibcon#wrote, iclass 18, count 0 2006.286.05:31:48.45#ibcon#about to read 3, iclass 18, count 0 2006.286.05:31:48.47#ibcon#read 3, iclass 18, count 0 2006.286.05:31:49.15#ibcon#about to read 4, iclass 18, count 0 2006.286.05:31:49.15#ibcon#read 4, iclass 18, count 0 2006.286.05:31:49.15#ibcon#about to read 5, iclass 18, count 0 2006.286.05:31:49.15#ibcon#read 5, iclass 18, count 0 2006.286.05:31:49.15#ibcon#about to read 6, iclass 18, count 0 2006.286.05:31:49.15#ibcon#read 6, iclass 18, count 0 2006.286.05:31:49.15#ibcon#end of sib2, iclass 18, count 0 2006.286.05:31:49.15#ibcon#*mode == 0, iclass 18, count 0 2006.286.05:31:49.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.05:31:49.15#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.05:31:49.15#ibcon#*before write, iclass 18, count 0 2006.286.05:31:49.15#ibcon#enter sib2, iclass 18, count 0 2006.286.05:31:49.15#ibcon#flushed, iclass 18, count 0 2006.286.05:31:49.15#ibcon#about to write, iclass 18, count 0 2006.286.05:31:49.15#ibcon#wrote, iclass 18, count 0 2006.286.05:31:49.15#ibcon#about to read 3, iclass 18, count 0 2006.286.05:31:49.19#ibcon#read 3, iclass 18, count 0 2006.286.05:31:49.19#ibcon#about to read 4, iclass 18, count 0 2006.286.05:31:49.19#ibcon#read 4, iclass 18, count 0 2006.286.05:31:49.19#ibcon#about to read 5, iclass 18, count 0 2006.286.05:31:49.19#ibcon#read 5, iclass 18, count 0 2006.286.05:31:49.19#ibcon#about to read 6, iclass 18, count 0 2006.286.05:31:49.19#ibcon#read 6, iclass 18, count 0 2006.286.05:31:49.19#ibcon#end of sib2, iclass 18, count 0 2006.286.05:31:49.19#ibcon#*after write, iclass 18, count 0 2006.286.05:31:49.19#ibcon#*before return 0, iclass 18, count 0 2006.286.05:31:49.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:31:49.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:31:49.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.05:31:49.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.05:31:49.19$vck44/va=2,6 2006.286.05:31:49.19#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.05:31:49.19#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.05:31:49.19#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:49.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:31:49.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:31:49.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:31:49.19#ibcon#enter wrdev, iclass 20, count 2 2006.286.05:31:49.19#ibcon#first serial, iclass 20, count 2 2006.286.05:31:49.19#ibcon#enter sib2, iclass 20, count 2 2006.286.05:31:49.19#ibcon#flushed, iclass 20, count 2 2006.286.05:31:49.19#ibcon#about to write, iclass 20, count 2 2006.286.05:31:49.19#ibcon#wrote, iclass 20, count 2 2006.286.05:31:49.19#ibcon#about to read 3, iclass 20, count 2 2006.286.05:31:49.21#ibcon#read 3, iclass 20, count 2 2006.286.05:31:49.21#ibcon#about to read 4, iclass 20, count 2 2006.286.05:31:49.21#ibcon#read 4, iclass 20, count 2 2006.286.05:31:49.21#ibcon#about to read 5, iclass 20, count 2 2006.286.05:31:49.21#ibcon#read 5, iclass 20, count 2 2006.286.05:31:49.21#ibcon#about to read 6, iclass 20, count 2 2006.286.05:31:49.21#ibcon#read 6, iclass 20, count 2 2006.286.05:31:49.21#ibcon#end of sib2, iclass 20, count 2 2006.286.05:31:49.21#ibcon#*mode == 0, iclass 20, count 2 2006.286.05:31:49.21#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.05:31:49.21#ibcon#[25=AT02-06\r\n] 2006.286.05:31:49.21#ibcon#*before write, iclass 20, count 2 2006.286.05:31:49.21#ibcon#enter sib2, iclass 20, count 2 2006.286.05:31:49.21#ibcon#flushed, iclass 20, count 2 2006.286.05:31:49.21#ibcon#about to write, iclass 20, count 2 2006.286.05:31:49.21#ibcon#wrote, iclass 20, count 2 2006.286.05:31:49.21#ibcon#about to read 3, iclass 20, count 2 2006.286.05:31:49.24#ibcon#read 3, iclass 20, count 2 2006.286.05:31:49.24#ibcon#about to read 4, iclass 20, count 2 2006.286.05:31:49.24#ibcon#read 4, iclass 20, count 2 2006.286.05:31:49.24#ibcon#about to read 5, iclass 20, count 2 2006.286.05:31:49.24#ibcon#read 5, iclass 20, count 2 2006.286.05:31:49.24#ibcon#about to read 6, iclass 20, count 2 2006.286.05:31:49.24#ibcon#read 6, iclass 20, count 2 2006.286.05:31:49.24#ibcon#end of sib2, iclass 20, count 2 2006.286.05:31:49.24#ibcon#*after write, iclass 20, count 2 2006.286.05:31:49.24#ibcon#*before return 0, iclass 20, count 2 2006.286.05:31:49.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:31:49.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:31:49.24#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.05:31:49.24#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:49.24#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:31:49.36#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:31:49.36#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:31:49.36#ibcon#enter wrdev, iclass 20, count 0 2006.286.05:31:49.36#ibcon#first serial, iclass 20, count 0 2006.286.05:31:49.36#ibcon#enter sib2, iclass 20, count 0 2006.286.05:31:49.36#ibcon#flushed, iclass 20, count 0 2006.286.05:31:49.36#ibcon#about to write, iclass 20, count 0 2006.286.05:31:49.36#ibcon#wrote, iclass 20, count 0 2006.286.05:31:49.36#ibcon#about to read 3, iclass 20, count 0 2006.286.05:31:49.38#ibcon#read 3, iclass 20, count 0 2006.286.05:31:49.38#ibcon#about to read 4, iclass 20, count 0 2006.286.05:31:49.38#ibcon#read 4, iclass 20, count 0 2006.286.05:31:49.38#ibcon#about to read 5, iclass 20, count 0 2006.286.05:31:49.38#ibcon#read 5, iclass 20, count 0 2006.286.05:31:49.38#ibcon#about to read 6, iclass 20, count 0 2006.286.05:31:49.38#ibcon#read 6, iclass 20, count 0 2006.286.05:31:49.38#ibcon#end of sib2, iclass 20, count 0 2006.286.05:31:49.38#ibcon#*mode == 0, iclass 20, count 0 2006.286.05:31:49.38#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.05:31:49.38#ibcon#[25=USB\r\n] 2006.286.05:31:49.38#ibcon#*before write, iclass 20, count 0 2006.286.05:31:49.38#ibcon#enter sib2, iclass 20, count 0 2006.286.05:31:49.38#ibcon#flushed, iclass 20, count 0 2006.286.05:31:49.38#ibcon#about to write, iclass 20, count 0 2006.286.05:31:49.38#ibcon#wrote, iclass 20, count 0 2006.286.05:31:49.38#ibcon#about to read 3, iclass 20, count 0 2006.286.05:31:49.41#ibcon#read 3, iclass 20, count 0 2006.286.05:31:49.41#ibcon#about to read 4, iclass 20, count 0 2006.286.05:31:49.41#ibcon#read 4, iclass 20, count 0 2006.286.05:31:49.41#ibcon#about to read 5, iclass 20, count 0 2006.286.05:31:49.41#ibcon#read 5, iclass 20, count 0 2006.286.05:31:49.41#ibcon#about to read 6, iclass 20, count 0 2006.286.05:31:49.41#ibcon#read 6, iclass 20, count 0 2006.286.05:31:49.41#ibcon#end of sib2, iclass 20, count 0 2006.286.05:31:49.41#ibcon#*after write, iclass 20, count 0 2006.286.05:31:49.41#ibcon#*before return 0, iclass 20, count 0 2006.286.05:31:49.41#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:31:49.41#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:31:49.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.05:31:49.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.05:31:49.41$vck44/valo=3,564.99 2006.286.05:31:49.41#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.05:31:49.41#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.05:31:49.41#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:49.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:31:49.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:31:49.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:31:49.41#ibcon#enter wrdev, iclass 22, count 0 2006.286.05:31:49.41#ibcon#first serial, iclass 22, count 0 2006.286.05:31:49.41#ibcon#enter sib2, iclass 22, count 0 2006.286.05:31:49.41#ibcon#flushed, iclass 22, count 0 2006.286.05:31:49.41#ibcon#about to write, iclass 22, count 0 2006.286.05:31:49.41#ibcon#wrote, iclass 22, count 0 2006.286.05:31:49.41#ibcon#about to read 3, iclass 22, count 0 2006.286.05:31:49.43#ibcon#read 3, iclass 22, count 0 2006.286.05:31:49.54#ibcon#about to read 4, iclass 22, count 0 2006.286.05:31:49.54#ibcon#read 4, iclass 22, count 0 2006.286.05:31:49.54#ibcon#about to read 5, iclass 22, count 0 2006.286.05:31:49.54#ibcon#read 5, iclass 22, count 0 2006.286.05:31:49.54#ibcon#about to read 6, iclass 22, count 0 2006.286.05:31:49.54#ibcon#read 6, iclass 22, count 0 2006.286.05:31:49.54#ibcon#end of sib2, iclass 22, count 0 2006.286.05:31:49.54#ibcon#*mode == 0, iclass 22, count 0 2006.286.05:31:49.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.05:31:49.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.05:31:49.54#ibcon#*before write, iclass 22, count 0 2006.286.05:31:49.54#ibcon#enter sib2, iclass 22, count 0 2006.286.05:31:49.54#ibcon#flushed, iclass 22, count 0 2006.286.05:31:49.54#ibcon#about to write, iclass 22, count 0 2006.286.05:31:49.54#ibcon#wrote, iclass 22, count 0 2006.286.05:31:49.54#ibcon#about to read 3, iclass 22, count 0 2006.286.05:31:49.58#ibcon#read 3, iclass 22, count 0 2006.286.05:31:49.58#ibcon#about to read 4, iclass 22, count 0 2006.286.05:31:49.58#ibcon#read 4, iclass 22, count 0 2006.286.05:31:49.58#ibcon#about to read 5, iclass 22, count 0 2006.286.05:31:49.58#ibcon#read 5, iclass 22, count 0 2006.286.05:31:49.58#ibcon#about to read 6, iclass 22, count 0 2006.286.05:31:49.58#ibcon#read 6, iclass 22, count 0 2006.286.05:31:49.58#ibcon#end of sib2, iclass 22, count 0 2006.286.05:31:49.58#ibcon#*after write, iclass 22, count 0 2006.286.05:31:49.58#ibcon#*before return 0, iclass 22, count 0 2006.286.05:31:49.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:31:49.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:31:49.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.05:31:49.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.05:31:49.58$vck44/va=3,7 2006.286.05:31:49.58#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.05:31:49.58#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.05:31:49.58#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:49.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:31:49.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:31:49.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:31:49.58#ibcon#enter wrdev, iclass 24, count 2 2006.286.05:31:49.58#ibcon#first serial, iclass 24, count 2 2006.286.05:31:49.58#ibcon#enter sib2, iclass 24, count 2 2006.286.05:31:49.58#ibcon#flushed, iclass 24, count 2 2006.286.05:31:49.58#ibcon#about to write, iclass 24, count 2 2006.286.05:31:49.58#ibcon#wrote, iclass 24, count 2 2006.286.05:31:49.58#ibcon#about to read 3, iclass 24, count 2 2006.286.05:31:49.60#ibcon#read 3, iclass 24, count 2 2006.286.05:31:49.60#ibcon#about to read 4, iclass 24, count 2 2006.286.05:31:49.60#ibcon#read 4, iclass 24, count 2 2006.286.05:31:49.60#ibcon#about to read 5, iclass 24, count 2 2006.286.05:31:49.60#ibcon#read 5, iclass 24, count 2 2006.286.05:31:49.60#ibcon#about to read 6, iclass 24, count 2 2006.286.05:31:49.60#ibcon#read 6, iclass 24, count 2 2006.286.05:31:49.60#ibcon#end of sib2, iclass 24, count 2 2006.286.05:31:49.60#ibcon#*mode == 0, iclass 24, count 2 2006.286.05:31:49.60#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.05:31:49.60#ibcon#[25=AT03-07\r\n] 2006.286.05:31:49.60#ibcon#*before write, iclass 24, count 2 2006.286.05:31:49.60#ibcon#enter sib2, iclass 24, count 2 2006.286.05:31:49.60#ibcon#flushed, iclass 24, count 2 2006.286.05:31:49.60#ibcon#about to write, iclass 24, count 2 2006.286.05:31:49.60#ibcon#wrote, iclass 24, count 2 2006.286.05:31:49.60#ibcon#about to read 3, iclass 24, count 2 2006.286.05:31:49.63#ibcon#read 3, iclass 24, count 2 2006.286.05:31:49.63#ibcon#about to read 4, iclass 24, count 2 2006.286.05:31:49.63#ibcon#read 4, iclass 24, count 2 2006.286.05:31:49.63#ibcon#about to read 5, iclass 24, count 2 2006.286.05:31:49.63#ibcon#read 5, iclass 24, count 2 2006.286.05:31:49.63#ibcon#about to read 6, iclass 24, count 2 2006.286.05:31:49.63#ibcon#read 6, iclass 24, count 2 2006.286.05:31:49.63#ibcon#end of sib2, iclass 24, count 2 2006.286.05:31:49.63#ibcon#*after write, iclass 24, count 2 2006.286.05:31:49.63#ibcon#*before return 0, iclass 24, count 2 2006.286.05:31:49.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:31:49.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:31:49.63#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.05:31:49.63#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:49.63#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:31:49.75#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:31:49.75#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:31:49.75#ibcon#enter wrdev, iclass 24, count 0 2006.286.05:31:49.75#ibcon#first serial, iclass 24, count 0 2006.286.05:31:49.75#ibcon#enter sib2, iclass 24, count 0 2006.286.05:31:49.75#ibcon#flushed, iclass 24, count 0 2006.286.05:31:49.75#ibcon#about to write, iclass 24, count 0 2006.286.05:31:49.75#ibcon#wrote, iclass 24, count 0 2006.286.05:31:49.75#ibcon#about to read 3, iclass 24, count 0 2006.286.05:31:49.77#ibcon#read 3, iclass 24, count 0 2006.286.05:31:49.77#ibcon#about to read 4, iclass 24, count 0 2006.286.05:31:49.77#ibcon#read 4, iclass 24, count 0 2006.286.05:31:49.77#ibcon#about to read 5, iclass 24, count 0 2006.286.05:31:49.77#ibcon#read 5, iclass 24, count 0 2006.286.05:31:49.77#ibcon#about to read 6, iclass 24, count 0 2006.286.05:31:49.77#ibcon#read 6, iclass 24, count 0 2006.286.05:31:49.77#ibcon#end of sib2, iclass 24, count 0 2006.286.05:31:49.77#ibcon#*mode == 0, iclass 24, count 0 2006.286.05:31:49.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.05:31:49.77#ibcon#[25=USB\r\n] 2006.286.05:31:49.77#ibcon#*before write, iclass 24, count 0 2006.286.05:31:49.77#ibcon#enter sib2, iclass 24, count 0 2006.286.05:31:49.77#ibcon#flushed, iclass 24, count 0 2006.286.05:31:49.77#ibcon#about to write, iclass 24, count 0 2006.286.05:31:49.77#ibcon#wrote, iclass 24, count 0 2006.286.05:31:49.77#ibcon#about to read 3, iclass 24, count 0 2006.286.05:31:49.80#ibcon#read 3, iclass 24, count 0 2006.286.05:31:49.80#ibcon#about to read 4, iclass 24, count 0 2006.286.05:31:49.80#ibcon#read 4, iclass 24, count 0 2006.286.05:31:49.80#ibcon#about to read 5, iclass 24, count 0 2006.286.05:31:49.80#ibcon#read 5, iclass 24, count 0 2006.286.05:31:49.80#ibcon#about to read 6, iclass 24, count 0 2006.286.05:31:49.80#ibcon#read 6, iclass 24, count 0 2006.286.05:31:49.80#ibcon#end of sib2, iclass 24, count 0 2006.286.05:31:49.80#ibcon#*after write, iclass 24, count 0 2006.286.05:31:49.80#ibcon#*before return 0, iclass 24, count 0 2006.286.05:31:49.80#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:31:49.80#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:31:49.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.05:31:49.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.05:31:49.80$vck44/valo=4,624.99 2006.286.05:31:49.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.05:31:49.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.05:31:49.80#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:49.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:31:49.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:31:49.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:31:49.80#ibcon#enter wrdev, iclass 26, count 0 2006.286.05:31:49.80#ibcon#first serial, iclass 26, count 0 2006.286.05:31:49.80#ibcon#enter sib2, iclass 26, count 0 2006.286.05:31:49.80#ibcon#flushed, iclass 26, count 0 2006.286.05:31:49.80#ibcon#about to write, iclass 26, count 0 2006.286.05:31:49.80#ibcon#wrote, iclass 26, count 0 2006.286.05:31:49.80#ibcon#about to read 3, iclass 26, count 0 2006.286.05:31:49.82#ibcon#read 3, iclass 26, count 0 2006.286.05:31:49.82#ibcon#about to read 4, iclass 26, count 0 2006.286.05:31:49.82#ibcon#read 4, iclass 26, count 0 2006.286.05:31:49.82#ibcon#about to read 5, iclass 26, count 0 2006.286.05:31:49.82#ibcon#read 5, iclass 26, count 0 2006.286.05:31:49.82#ibcon#about to read 6, iclass 26, count 0 2006.286.05:31:49.82#ibcon#read 6, iclass 26, count 0 2006.286.05:31:49.82#ibcon#end of sib2, iclass 26, count 0 2006.286.05:31:49.82#ibcon#*mode == 0, iclass 26, count 0 2006.286.05:31:49.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.05:31:49.82#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.05:31:49.82#ibcon#*before write, iclass 26, count 0 2006.286.05:31:49.82#ibcon#enter sib2, iclass 26, count 0 2006.286.05:31:49.82#ibcon#flushed, iclass 26, count 0 2006.286.05:31:49.82#ibcon#about to write, iclass 26, count 0 2006.286.05:31:49.82#ibcon#wrote, iclass 26, count 0 2006.286.05:31:49.82#ibcon#about to read 3, iclass 26, count 0 2006.286.05:31:49.86#ibcon#read 3, iclass 26, count 0 2006.286.05:31:49.86#ibcon#about to read 4, iclass 26, count 0 2006.286.05:31:49.86#ibcon#read 4, iclass 26, count 0 2006.286.05:31:49.86#ibcon#about to read 5, iclass 26, count 0 2006.286.05:31:49.86#ibcon#read 5, iclass 26, count 0 2006.286.05:31:49.86#ibcon#about to read 6, iclass 26, count 0 2006.286.05:31:49.86#ibcon#read 6, iclass 26, count 0 2006.286.05:31:49.86#ibcon#end of sib2, iclass 26, count 0 2006.286.05:31:49.86#ibcon#*after write, iclass 26, count 0 2006.286.05:31:49.86#ibcon#*before return 0, iclass 26, count 0 2006.286.05:31:49.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:31:49.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:31:49.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.05:31:49.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.05:31:49.86$vck44/va=4,6 2006.286.05:31:49.86#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.05:31:49.86#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.05:31:49.86#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:49.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:31:49.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:31:49.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:31:49.92#ibcon#enter wrdev, iclass 28, count 2 2006.286.05:31:49.92#ibcon#first serial, iclass 28, count 2 2006.286.05:31:49.92#ibcon#enter sib2, iclass 28, count 2 2006.286.05:31:49.92#ibcon#flushed, iclass 28, count 2 2006.286.05:31:49.92#ibcon#about to write, iclass 28, count 2 2006.286.05:31:49.92#ibcon#wrote, iclass 28, count 2 2006.286.05:31:49.92#ibcon#about to read 3, iclass 28, count 2 2006.286.05:31:49.94#ibcon#read 3, iclass 28, count 2 2006.286.05:31:49.94#ibcon#about to read 4, iclass 28, count 2 2006.286.05:31:49.94#ibcon#read 4, iclass 28, count 2 2006.286.05:31:49.94#ibcon#about to read 5, iclass 28, count 2 2006.286.05:31:49.94#ibcon#read 5, iclass 28, count 2 2006.286.05:31:49.94#ibcon#about to read 6, iclass 28, count 2 2006.286.05:31:49.94#ibcon#read 6, iclass 28, count 2 2006.286.05:31:49.94#ibcon#end of sib2, iclass 28, count 2 2006.286.05:31:49.94#ibcon#*mode == 0, iclass 28, count 2 2006.286.05:31:49.94#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.05:31:49.94#ibcon#[25=AT04-06\r\n] 2006.286.05:31:49.94#ibcon#*before write, iclass 28, count 2 2006.286.05:31:49.94#ibcon#enter sib2, iclass 28, count 2 2006.286.05:31:49.94#ibcon#flushed, iclass 28, count 2 2006.286.05:31:49.94#ibcon#about to write, iclass 28, count 2 2006.286.05:31:49.94#ibcon#wrote, iclass 28, count 2 2006.286.05:31:49.94#ibcon#about to read 3, iclass 28, count 2 2006.286.05:31:49.97#ibcon#read 3, iclass 28, count 2 2006.286.05:31:49.97#ibcon#about to read 4, iclass 28, count 2 2006.286.05:31:49.97#ibcon#read 4, iclass 28, count 2 2006.286.05:31:49.97#ibcon#about to read 5, iclass 28, count 2 2006.286.05:31:49.97#ibcon#read 5, iclass 28, count 2 2006.286.05:31:49.97#ibcon#about to read 6, iclass 28, count 2 2006.286.05:31:49.97#ibcon#read 6, iclass 28, count 2 2006.286.05:31:49.97#ibcon#end of sib2, iclass 28, count 2 2006.286.05:31:49.97#ibcon#*after write, iclass 28, count 2 2006.286.05:31:49.97#ibcon#*before return 0, iclass 28, count 2 2006.286.05:31:49.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:31:49.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:31:49.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.05:31:49.97#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:49.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:31:50.09#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:31:50.09#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:31:50.09#ibcon#enter wrdev, iclass 28, count 0 2006.286.05:31:50.09#ibcon#first serial, iclass 28, count 0 2006.286.05:31:50.09#ibcon#enter sib2, iclass 28, count 0 2006.286.05:31:50.09#ibcon#flushed, iclass 28, count 0 2006.286.05:31:50.09#ibcon#about to write, iclass 28, count 0 2006.286.05:31:50.09#ibcon#wrote, iclass 28, count 0 2006.286.05:31:50.09#ibcon#about to read 3, iclass 28, count 0 2006.286.05:31:50.11#ibcon#read 3, iclass 28, count 0 2006.286.05:31:50.11#ibcon#about to read 4, iclass 28, count 0 2006.286.05:31:50.11#ibcon#read 4, iclass 28, count 0 2006.286.05:31:50.11#ibcon#about to read 5, iclass 28, count 0 2006.286.05:31:50.11#ibcon#read 5, iclass 28, count 0 2006.286.05:31:50.11#ibcon#about to read 6, iclass 28, count 0 2006.286.05:31:50.11#ibcon#read 6, iclass 28, count 0 2006.286.05:31:50.11#ibcon#end of sib2, iclass 28, count 0 2006.286.05:31:50.11#ibcon#*mode == 0, iclass 28, count 0 2006.286.05:31:50.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.05:31:50.11#ibcon#[25=USB\r\n] 2006.286.05:31:50.11#ibcon#*before write, iclass 28, count 0 2006.286.05:31:50.11#ibcon#enter sib2, iclass 28, count 0 2006.286.05:31:50.11#ibcon#flushed, iclass 28, count 0 2006.286.05:31:50.11#ibcon#about to write, iclass 28, count 0 2006.286.05:31:50.11#ibcon#wrote, iclass 28, count 0 2006.286.05:31:50.11#ibcon#about to read 3, iclass 28, count 0 2006.286.05:31:50.14#ibcon#read 3, iclass 28, count 0 2006.286.05:31:50.14#ibcon#about to read 4, iclass 28, count 0 2006.286.05:31:50.14#ibcon#read 4, iclass 28, count 0 2006.286.05:31:50.14#ibcon#about to read 5, iclass 28, count 0 2006.286.05:31:50.14#ibcon#read 5, iclass 28, count 0 2006.286.05:31:50.14#ibcon#about to read 6, iclass 28, count 0 2006.286.05:31:50.14#ibcon#read 6, iclass 28, count 0 2006.286.05:31:50.14#ibcon#end of sib2, iclass 28, count 0 2006.286.05:31:50.14#ibcon#*after write, iclass 28, count 0 2006.286.05:31:50.14#ibcon#*before return 0, iclass 28, count 0 2006.286.05:31:50.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:31:50.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:31:50.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.05:31:50.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.05:31:50.14$vck44/valo=5,734.99 2006.286.05:31:50.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.05:31:50.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.05:31:50.14#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:50.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:31:50.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:31:50.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:31:50.14#ibcon#enter wrdev, iclass 30, count 0 2006.286.05:31:50.14#ibcon#first serial, iclass 30, count 0 2006.286.05:31:50.14#ibcon#enter sib2, iclass 30, count 0 2006.286.05:31:50.14#ibcon#flushed, iclass 30, count 0 2006.286.05:31:50.14#ibcon#about to write, iclass 30, count 0 2006.286.05:31:50.14#ibcon#wrote, iclass 30, count 0 2006.286.05:31:50.14#ibcon#about to read 3, iclass 30, count 0 2006.286.05:31:50.16#ibcon#read 3, iclass 30, count 0 2006.286.05:31:50.16#ibcon#about to read 4, iclass 30, count 0 2006.286.05:31:50.16#ibcon#read 4, iclass 30, count 0 2006.286.05:31:50.16#ibcon#about to read 5, iclass 30, count 0 2006.286.05:31:50.16#ibcon#read 5, iclass 30, count 0 2006.286.05:31:50.16#ibcon#about to read 6, iclass 30, count 0 2006.286.05:31:50.16#ibcon#read 6, iclass 30, count 0 2006.286.05:31:50.16#ibcon#end of sib2, iclass 30, count 0 2006.286.05:31:50.16#ibcon#*mode == 0, iclass 30, count 0 2006.286.05:31:50.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.05:31:50.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.05:31:50.16#ibcon#*before write, iclass 30, count 0 2006.286.05:31:50.16#ibcon#enter sib2, iclass 30, count 0 2006.286.05:31:50.16#ibcon#flushed, iclass 30, count 0 2006.286.05:31:50.16#ibcon#about to write, iclass 30, count 0 2006.286.05:31:50.16#ibcon#wrote, iclass 30, count 0 2006.286.05:31:50.16#ibcon#about to read 3, iclass 30, count 0 2006.286.05:31:50.20#ibcon#read 3, iclass 30, count 0 2006.286.05:31:50.20#ibcon#about to read 4, iclass 30, count 0 2006.286.05:31:50.20#ibcon#read 4, iclass 30, count 0 2006.286.05:31:50.20#ibcon#about to read 5, iclass 30, count 0 2006.286.05:31:50.20#ibcon#read 5, iclass 30, count 0 2006.286.05:31:50.20#ibcon#about to read 6, iclass 30, count 0 2006.286.05:31:50.20#ibcon#read 6, iclass 30, count 0 2006.286.05:31:50.20#ibcon#end of sib2, iclass 30, count 0 2006.286.05:31:50.20#ibcon#*after write, iclass 30, count 0 2006.286.05:31:50.20#ibcon#*before return 0, iclass 30, count 0 2006.286.05:31:50.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:31:50.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:31:50.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.05:31:50.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.05:31:50.20$vck44/va=5,3 2006.286.05:31:50.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.05:31:50.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.05:31:50.20#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:50.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:31:50.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:31:50.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:31:50.26#ibcon#enter wrdev, iclass 32, count 2 2006.286.05:31:50.26#ibcon#first serial, iclass 32, count 2 2006.286.05:31:50.26#ibcon#enter sib2, iclass 32, count 2 2006.286.05:31:50.26#ibcon#flushed, iclass 32, count 2 2006.286.05:31:50.26#ibcon#about to write, iclass 32, count 2 2006.286.05:31:50.26#ibcon#wrote, iclass 32, count 2 2006.286.05:31:50.26#ibcon#about to read 3, iclass 32, count 2 2006.286.05:31:50.28#ibcon#read 3, iclass 32, count 2 2006.286.05:31:50.28#ibcon#about to read 4, iclass 32, count 2 2006.286.05:31:50.28#ibcon#read 4, iclass 32, count 2 2006.286.05:31:50.28#ibcon#about to read 5, iclass 32, count 2 2006.286.05:31:50.28#ibcon#read 5, iclass 32, count 2 2006.286.05:31:50.28#ibcon#about to read 6, iclass 32, count 2 2006.286.05:31:50.28#ibcon#read 6, iclass 32, count 2 2006.286.05:31:50.28#ibcon#end of sib2, iclass 32, count 2 2006.286.05:31:50.28#ibcon#*mode == 0, iclass 32, count 2 2006.286.05:31:50.28#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.05:31:50.28#ibcon#[25=AT05-03\r\n] 2006.286.05:31:50.28#ibcon#*before write, iclass 32, count 2 2006.286.05:31:50.28#ibcon#enter sib2, iclass 32, count 2 2006.286.05:31:50.28#ibcon#flushed, iclass 32, count 2 2006.286.05:31:50.28#ibcon#about to write, iclass 32, count 2 2006.286.05:31:50.28#ibcon#wrote, iclass 32, count 2 2006.286.05:31:50.28#ibcon#about to read 3, iclass 32, count 2 2006.286.05:31:50.31#ibcon#read 3, iclass 32, count 2 2006.286.05:31:50.31#ibcon#about to read 4, iclass 32, count 2 2006.286.05:31:50.31#ibcon#read 4, iclass 32, count 2 2006.286.05:31:50.31#ibcon#about to read 5, iclass 32, count 2 2006.286.05:31:50.31#ibcon#read 5, iclass 32, count 2 2006.286.05:31:50.31#ibcon#about to read 6, iclass 32, count 2 2006.286.05:31:50.31#ibcon#read 6, iclass 32, count 2 2006.286.05:31:50.31#ibcon#end of sib2, iclass 32, count 2 2006.286.05:31:50.31#ibcon#*after write, iclass 32, count 2 2006.286.05:31:50.31#ibcon#*before return 0, iclass 32, count 2 2006.286.05:31:50.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:31:50.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:31:50.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.05:31:50.31#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:50.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:31:50.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:31:50.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:31:50.43#ibcon#enter wrdev, iclass 32, count 0 2006.286.05:31:50.43#ibcon#first serial, iclass 32, count 0 2006.286.05:31:50.43#ibcon#enter sib2, iclass 32, count 0 2006.286.05:31:50.43#ibcon#flushed, iclass 32, count 0 2006.286.05:31:50.43#ibcon#about to write, iclass 32, count 0 2006.286.05:31:50.43#ibcon#wrote, iclass 32, count 0 2006.286.05:31:50.43#ibcon#about to read 3, iclass 32, count 0 2006.286.05:31:50.45#ibcon#read 3, iclass 32, count 0 2006.286.05:31:50.45#ibcon#about to read 4, iclass 32, count 0 2006.286.05:31:50.45#ibcon#read 4, iclass 32, count 0 2006.286.05:31:50.45#ibcon#about to read 5, iclass 32, count 0 2006.286.05:31:50.45#ibcon#read 5, iclass 32, count 0 2006.286.05:31:50.45#ibcon#about to read 6, iclass 32, count 0 2006.286.05:31:50.45#ibcon#read 6, iclass 32, count 0 2006.286.05:31:50.45#ibcon#end of sib2, iclass 32, count 0 2006.286.05:31:50.45#ibcon#*mode == 0, iclass 32, count 0 2006.286.05:31:50.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.05:31:50.45#ibcon#[25=USB\r\n] 2006.286.05:31:50.45#ibcon#*before write, iclass 32, count 0 2006.286.05:31:50.45#ibcon#enter sib2, iclass 32, count 0 2006.286.05:31:50.45#ibcon#flushed, iclass 32, count 0 2006.286.05:31:50.45#ibcon#about to write, iclass 32, count 0 2006.286.05:31:50.45#ibcon#wrote, iclass 32, count 0 2006.286.05:31:50.45#ibcon#about to read 3, iclass 32, count 0 2006.286.05:31:50.48#ibcon#read 3, iclass 32, count 0 2006.286.05:31:50.48#ibcon#about to read 4, iclass 32, count 0 2006.286.05:31:50.48#ibcon#read 4, iclass 32, count 0 2006.286.05:31:50.48#ibcon#about to read 5, iclass 32, count 0 2006.286.05:31:50.48#ibcon#read 5, iclass 32, count 0 2006.286.05:31:50.48#ibcon#about to read 6, iclass 32, count 0 2006.286.05:31:50.48#ibcon#read 6, iclass 32, count 0 2006.286.05:31:50.48#ibcon#end of sib2, iclass 32, count 0 2006.286.05:31:50.48#ibcon#*after write, iclass 32, count 0 2006.286.05:31:50.48#ibcon#*before return 0, iclass 32, count 0 2006.286.05:31:50.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:31:50.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:31:50.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.05:31:50.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.05:31:50.48$vck44/valo=6,814.99 2006.286.05:31:50.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.05:31:50.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.05:31:50.48#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:50.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:31:50.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:31:50.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:31:50.48#ibcon#enter wrdev, iclass 34, count 0 2006.286.05:31:50.48#ibcon#first serial, iclass 34, count 0 2006.286.05:31:50.48#ibcon#enter sib2, iclass 34, count 0 2006.286.05:31:50.48#ibcon#flushed, iclass 34, count 0 2006.286.05:31:50.48#ibcon#about to write, iclass 34, count 0 2006.286.05:31:50.48#ibcon#wrote, iclass 34, count 0 2006.286.05:31:50.48#ibcon#about to read 3, iclass 34, count 0 2006.286.05:31:50.50#ibcon#read 3, iclass 34, count 0 2006.286.05:31:50.70#ibcon#about to read 4, iclass 34, count 0 2006.286.05:31:50.70#ibcon#read 4, iclass 34, count 0 2006.286.05:31:50.70#ibcon#about to read 5, iclass 34, count 0 2006.286.05:31:50.70#ibcon#read 5, iclass 34, count 0 2006.286.05:31:50.70#ibcon#about to read 6, iclass 34, count 0 2006.286.05:31:50.70#ibcon#read 6, iclass 34, count 0 2006.286.05:31:50.70#ibcon#end of sib2, iclass 34, count 0 2006.286.05:31:50.70#ibcon#*mode == 0, iclass 34, count 0 2006.286.05:31:50.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.05:31:50.70#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.05:31:50.70#ibcon#*before write, iclass 34, count 0 2006.286.05:31:50.70#ibcon#enter sib2, iclass 34, count 0 2006.286.05:31:50.70#ibcon#flushed, iclass 34, count 0 2006.286.05:31:50.70#ibcon#about to write, iclass 34, count 0 2006.286.05:31:50.70#ibcon#wrote, iclass 34, count 0 2006.286.05:31:50.70#ibcon#about to read 3, iclass 34, count 0 2006.286.05:31:50.75#ibcon#read 3, iclass 34, count 0 2006.286.05:31:50.75#ibcon#about to read 4, iclass 34, count 0 2006.286.05:31:50.75#ibcon#read 4, iclass 34, count 0 2006.286.05:31:50.75#ibcon#about to read 5, iclass 34, count 0 2006.286.05:31:50.75#ibcon#read 5, iclass 34, count 0 2006.286.05:31:50.75#ibcon#about to read 6, iclass 34, count 0 2006.286.05:31:50.75#ibcon#read 6, iclass 34, count 0 2006.286.05:31:50.75#ibcon#end of sib2, iclass 34, count 0 2006.286.05:31:50.75#ibcon#*after write, iclass 34, count 0 2006.286.05:31:50.75#ibcon#*before return 0, iclass 34, count 0 2006.286.05:31:50.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:31:50.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:31:50.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.05:31:50.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.05:31:50.75$vck44/va=6,4 2006.286.05:31:50.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.05:31:50.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.05:31:50.75#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:50.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:31:50.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:31:50.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:31:50.75#ibcon#enter wrdev, iclass 36, count 2 2006.286.05:31:50.75#ibcon#first serial, iclass 36, count 2 2006.286.05:31:50.75#ibcon#enter sib2, iclass 36, count 2 2006.286.05:31:50.75#ibcon#flushed, iclass 36, count 2 2006.286.05:31:50.75#ibcon#about to write, iclass 36, count 2 2006.286.05:31:50.75#ibcon#wrote, iclass 36, count 2 2006.286.05:31:50.75#ibcon#about to read 3, iclass 36, count 2 2006.286.05:31:50.77#ibcon#read 3, iclass 36, count 2 2006.286.05:31:50.77#ibcon#about to read 4, iclass 36, count 2 2006.286.05:31:50.77#ibcon#read 4, iclass 36, count 2 2006.286.05:31:50.77#ibcon#about to read 5, iclass 36, count 2 2006.286.05:31:50.77#ibcon#read 5, iclass 36, count 2 2006.286.05:31:50.77#ibcon#about to read 6, iclass 36, count 2 2006.286.05:31:50.77#ibcon#read 6, iclass 36, count 2 2006.286.05:31:50.77#ibcon#end of sib2, iclass 36, count 2 2006.286.05:31:50.77#ibcon#*mode == 0, iclass 36, count 2 2006.286.05:31:50.77#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.05:31:50.77#ibcon#[25=AT06-04\r\n] 2006.286.05:31:50.77#ibcon#*before write, iclass 36, count 2 2006.286.05:31:50.77#ibcon#enter sib2, iclass 36, count 2 2006.286.05:31:50.77#ibcon#flushed, iclass 36, count 2 2006.286.05:31:50.77#ibcon#about to write, iclass 36, count 2 2006.286.05:31:50.77#ibcon#wrote, iclass 36, count 2 2006.286.05:31:50.77#ibcon#about to read 3, iclass 36, count 2 2006.286.05:31:50.80#ibcon#read 3, iclass 36, count 2 2006.286.05:31:50.80#ibcon#about to read 4, iclass 36, count 2 2006.286.05:31:50.80#ibcon#read 4, iclass 36, count 2 2006.286.05:31:50.80#ibcon#about to read 5, iclass 36, count 2 2006.286.05:31:50.80#ibcon#read 5, iclass 36, count 2 2006.286.05:31:50.80#ibcon#about to read 6, iclass 36, count 2 2006.286.05:31:50.80#ibcon#read 6, iclass 36, count 2 2006.286.05:31:50.80#ibcon#end of sib2, iclass 36, count 2 2006.286.05:31:50.80#ibcon#*after write, iclass 36, count 2 2006.286.05:31:50.80#ibcon#*before return 0, iclass 36, count 2 2006.286.05:31:50.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:31:50.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:31:50.80#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.05:31:50.80#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:50.80#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:31:50.92#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:31:50.92#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:31:50.92#ibcon#enter wrdev, iclass 36, count 0 2006.286.05:31:50.92#ibcon#first serial, iclass 36, count 0 2006.286.05:31:50.92#ibcon#enter sib2, iclass 36, count 0 2006.286.05:31:50.92#ibcon#flushed, iclass 36, count 0 2006.286.05:31:50.92#ibcon#about to write, iclass 36, count 0 2006.286.05:31:50.92#ibcon#wrote, iclass 36, count 0 2006.286.05:31:50.92#ibcon#about to read 3, iclass 36, count 0 2006.286.05:31:50.94#ibcon#read 3, iclass 36, count 0 2006.286.05:31:50.94#ibcon#about to read 4, iclass 36, count 0 2006.286.05:31:50.94#ibcon#read 4, iclass 36, count 0 2006.286.05:31:50.94#ibcon#about to read 5, iclass 36, count 0 2006.286.05:31:50.94#ibcon#read 5, iclass 36, count 0 2006.286.05:31:50.94#ibcon#about to read 6, iclass 36, count 0 2006.286.05:31:50.94#ibcon#read 6, iclass 36, count 0 2006.286.05:31:50.94#ibcon#end of sib2, iclass 36, count 0 2006.286.05:31:50.94#ibcon#*mode == 0, iclass 36, count 0 2006.286.05:31:50.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.05:31:50.94#ibcon#[25=USB\r\n] 2006.286.05:31:50.94#ibcon#*before write, iclass 36, count 0 2006.286.05:31:50.94#ibcon#enter sib2, iclass 36, count 0 2006.286.05:31:50.94#ibcon#flushed, iclass 36, count 0 2006.286.05:31:50.94#ibcon#about to write, iclass 36, count 0 2006.286.05:31:50.94#ibcon#wrote, iclass 36, count 0 2006.286.05:31:50.94#ibcon#about to read 3, iclass 36, count 0 2006.286.05:31:50.97#ibcon#read 3, iclass 36, count 0 2006.286.05:31:50.97#ibcon#about to read 4, iclass 36, count 0 2006.286.05:31:50.97#ibcon#read 4, iclass 36, count 0 2006.286.05:31:50.97#ibcon#about to read 5, iclass 36, count 0 2006.286.05:31:50.97#ibcon#read 5, iclass 36, count 0 2006.286.05:31:50.97#ibcon#about to read 6, iclass 36, count 0 2006.286.05:31:50.97#ibcon#read 6, iclass 36, count 0 2006.286.05:31:50.97#ibcon#end of sib2, iclass 36, count 0 2006.286.05:31:50.97#ibcon#*after write, iclass 36, count 0 2006.286.05:31:50.97#ibcon#*before return 0, iclass 36, count 0 2006.286.05:31:50.97#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:31:50.97#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:31:50.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.05:31:50.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.05:31:50.97$vck44/valo=7,864.99 2006.286.05:31:50.97#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.05:31:50.97#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.05:31:50.97#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:50.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:31:50.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:31:50.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:31:50.97#ibcon#enter wrdev, iclass 38, count 0 2006.286.05:31:50.97#ibcon#first serial, iclass 38, count 0 2006.286.05:31:50.97#ibcon#enter sib2, iclass 38, count 0 2006.286.05:31:50.97#ibcon#flushed, iclass 38, count 0 2006.286.05:31:50.97#ibcon#about to write, iclass 38, count 0 2006.286.05:31:50.97#ibcon#wrote, iclass 38, count 0 2006.286.05:31:50.97#ibcon#about to read 3, iclass 38, count 0 2006.286.05:31:50.99#ibcon#read 3, iclass 38, count 0 2006.286.05:31:50.99#ibcon#about to read 4, iclass 38, count 0 2006.286.05:31:50.99#ibcon#read 4, iclass 38, count 0 2006.286.05:31:50.99#ibcon#about to read 5, iclass 38, count 0 2006.286.05:31:50.99#ibcon#read 5, iclass 38, count 0 2006.286.05:31:50.99#ibcon#about to read 6, iclass 38, count 0 2006.286.05:31:50.99#ibcon#read 6, iclass 38, count 0 2006.286.05:31:50.99#ibcon#end of sib2, iclass 38, count 0 2006.286.05:31:50.99#ibcon#*mode == 0, iclass 38, count 0 2006.286.05:31:50.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.05:31:50.99#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.05:31:50.99#ibcon#*before write, iclass 38, count 0 2006.286.05:31:50.99#ibcon#enter sib2, iclass 38, count 0 2006.286.05:31:50.99#ibcon#flushed, iclass 38, count 0 2006.286.05:31:50.99#ibcon#about to write, iclass 38, count 0 2006.286.05:31:50.99#ibcon#wrote, iclass 38, count 0 2006.286.05:31:50.99#ibcon#about to read 3, iclass 38, count 0 2006.286.05:31:51.03#ibcon#read 3, iclass 38, count 0 2006.286.05:31:51.03#ibcon#about to read 4, iclass 38, count 0 2006.286.05:31:51.03#ibcon#read 4, iclass 38, count 0 2006.286.05:31:51.03#ibcon#about to read 5, iclass 38, count 0 2006.286.05:31:51.03#ibcon#read 5, iclass 38, count 0 2006.286.05:31:51.03#ibcon#about to read 6, iclass 38, count 0 2006.286.05:31:51.03#ibcon#read 6, iclass 38, count 0 2006.286.05:31:51.03#ibcon#end of sib2, iclass 38, count 0 2006.286.05:31:51.03#ibcon#*after write, iclass 38, count 0 2006.286.05:31:51.03#ibcon#*before return 0, iclass 38, count 0 2006.286.05:31:51.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:31:51.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:31:51.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.05:31:51.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.05:31:51.03$vck44/va=7,4 2006.286.05:31:51.03#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.05:31:51.03#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.05:31:51.03#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:51.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:31:51.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:31:51.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:31:51.09#ibcon#enter wrdev, iclass 40, count 2 2006.286.05:31:51.09#ibcon#first serial, iclass 40, count 2 2006.286.05:31:51.09#ibcon#enter sib2, iclass 40, count 2 2006.286.05:31:51.09#ibcon#flushed, iclass 40, count 2 2006.286.05:31:51.09#ibcon#about to write, iclass 40, count 2 2006.286.05:31:51.09#ibcon#wrote, iclass 40, count 2 2006.286.05:31:51.09#ibcon#about to read 3, iclass 40, count 2 2006.286.05:31:51.11#ibcon#read 3, iclass 40, count 2 2006.286.05:31:51.11#ibcon#about to read 4, iclass 40, count 2 2006.286.05:31:51.11#ibcon#read 4, iclass 40, count 2 2006.286.05:31:51.11#ibcon#about to read 5, iclass 40, count 2 2006.286.05:31:51.11#ibcon#read 5, iclass 40, count 2 2006.286.05:31:51.11#ibcon#about to read 6, iclass 40, count 2 2006.286.05:31:51.11#ibcon#read 6, iclass 40, count 2 2006.286.05:31:51.11#ibcon#end of sib2, iclass 40, count 2 2006.286.05:31:51.11#ibcon#*mode == 0, iclass 40, count 2 2006.286.05:31:51.11#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.05:31:51.11#ibcon#[25=AT07-04\r\n] 2006.286.05:31:51.11#ibcon#*before write, iclass 40, count 2 2006.286.05:31:51.11#ibcon#enter sib2, iclass 40, count 2 2006.286.05:31:51.11#ibcon#flushed, iclass 40, count 2 2006.286.05:31:51.11#ibcon#about to write, iclass 40, count 2 2006.286.05:31:51.11#ibcon#wrote, iclass 40, count 2 2006.286.05:31:51.11#ibcon#about to read 3, iclass 40, count 2 2006.286.05:31:51.14#ibcon#read 3, iclass 40, count 2 2006.286.05:31:51.14#ibcon#about to read 4, iclass 40, count 2 2006.286.05:31:51.14#ibcon#read 4, iclass 40, count 2 2006.286.05:31:51.14#ibcon#about to read 5, iclass 40, count 2 2006.286.05:31:51.14#ibcon#read 5, iclass 40, count 2 2006.286.05:31:51.14#ibcon#about to read 6, iclass 40, count 2 2006.286.05:31:51.14#ibcon#read 6, iclass 40, count 2 2006.286.05:31:51.14#ibcon#end of sib2, iclass 40, count 2 2006.286.05:31:51.14#ibcon#*after write, iclass 40, count 2 2006.286.05:31:51.14#ibcon#*before return 0, iclass 40, count 2 2006.286.05:31:51.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:31:51.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:31:51.14#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.05:31:51.14#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:51.14#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:31:51.26#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:31:51.26#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:31:51.26#ibcon#enter wrdev, iclass 40, count 0 2006.286.05:31:51.26#ibcon#first serial, iclass 40, count 0 2006.286.05:31:51.26#ibcon#enter sib2, iclass 40, count 0 2006.286.05:31:51.26#ibcon#flushed, iclass 40, count 0 2006.286.05:31:51.26#ibcon#about to write, iclass 40, count 0 2006.286.05:31:51.26#ibcon#wrote, iclass 40, count 0 2006.286.05:31:51.26#ibcon#about to read 3, iclass 40, count 0 2006.286.05:31:51.28#ibcon#read 3, iclass 40, count 0 2006.286.05:31:51.28#ibcon#about to read 4, iclass 40, count 0 2006.286.05:31:51.28#ibcon#read 4, iclass 40, count 0 2006.286.05:31:51.28#ibcon#about to read 5, iclass 40, count 0 2006.286.05:31:51.28#ibcon#read 5, iclass 40, count 0 2006.286.05:31:51.28#ibcon#about to read 6, iclass 40, count 0 2006.286.05:31:51.28#ibcon#read 6, iclass 40, count 0 2006.286.05:31:51.28#ibcon#end of sib2, iclass 40, count 0 2006.286.05:31:51.28#ibcon#*mode == 0, iclass 40, count 0 2006.286.05:31:51.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.05:31:51.28#ibcon#[25=USB\r\n] 2006.286.05:31:51.28#ibcon#*before write, iclass 40, count 0 2006.286.05:31:51.28#ibcon#enter sib2, iclass 40, count 0 2006.286.05:31:51.28#ibcon#flushed, iclass 40, count 0 2006.286.05:31:51.28#ibcon#about to write, iclass 40, count 0 2006.286.05:31:51.28#ibcon#wrote, iclass 40, count 0 2006.286.05:31:51.28#ibcon#about to read 3, iclass 40, count 0 2006.286.05:31:51.31#ibcon#read 3, iclass 40, count 0 2006.286.05:31:51.31#ibcon#about to read 4, iclass 40, count 0 2006.286.05:31:51.31#ibcon#read 4, iclass 40, count 0 2006.286.05:31:51.31#ibcon#about to read 5, iclass 40, count 0 2006.286.05:31:51.31#ibcon#read 5, iclass 40, count 0 2006.286.05:31:51.31#ibcon#about to read 6, iclass 40, count 0 2006.286.05:31:51.31#ibcon#read 6, iclass 40, count 0 2006.286.05:31:51.31#ibcon#end of sib2, iclass 40, count 0 2006.286.05:31:51.31#ibcon#*after write, iclass 40, count 0 2006.286.05:31:51.31#ibcon#*before return 0, iclass 40, count 0 2006.286.05:31:51.31#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:31:51.31#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:31:51.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.05:31:51.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.05:31:51.31$vck44/valo=8,884.99 2006.286.05:31:51.31#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.05:31:51.31#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.05:31:51.31#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:51.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:31:51.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:31:51.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:31:51.31#ibcon#enter wrdev, iclass 4, count 0 2006.286.05:31:51.31#ibcon#first serial, iclass 4, count 0 2006.286.05:31:51.31#ibcon#enter sib2, iclass 4, count 0 2006.286.05:31:51.31#ibcon#flushed, iclass 4, count 0 2006.286.05:31:51.31#ibcon#about to write, iclass 4, count 0 2006.286.05:31:51.31#ibcon#wrote, iclass 4, count 0 2006.286.05:31:51.31#ibcon#about to read 3, iclass 4, count 0 2006.286.05:31:51.33#ibcon#read 3, iclass 4, count 0 2006.286.05:31:51.33#ibcon#about to read 4, iclass 4, count 0 2006.286.05:31:51.33#ibcon#read 4, iclass 4, count 0 2006.286.05:31:51.33#ibcon#about to read 5, iclass 4, count 0 2006.286.05:31:51.33#ibcon#read 5, iclass 4, count 0 2006.286.05:31:51.33#ibcon#about to read 6, iclass 4, count 0 2006.286.05:31:51.33#ibcon#read 6, iclass 4, count 0 2006.286.05:31:51.33#ibcon#end of sib2, iclass 4, count 0 2006.286.05:31:51.33#ibcon#*mode == 0, iclass 4, count 0 2006.286.05:31:51.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.05:31:51.33#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.05:31:51.33#ibcon#*before write, iclass 4, count 0 2006.286.05:31:51.33#ibcon#enter sib2, iclass 4, count 0 2006.286.05:31:51.33#ibcon#flushed, iclass 4, count 0 2006.286.05:31:51.33#ibcon#about to write, iclass 4, count 0 2006.286.05:31:51.33#ibcon#wrote, iclass 4, count 0 2006.286.05:31:51.33#ibcon#about to read 3, iclass 4, count 0 2006.286.05:31:51.37#ibcon#read 3, iclass 4, count 0 2006.286.05:31:51.37#ibcon#about to read 4, iclass 4, count 0 2006.286.05:31:51.37#ibcon#read 4, iclass 4, count 0 2006.286.05:31:51.37#ibcon#about to read 5, iclass 4, count 0 2006.286.05:31:51.37#ibcon#read 5, iclass 4, count 0 2006.286.05:31:51.37#ibcon#about to read 6, iclass 4, count 0 2006.286.05:31:51.37#ibcon#read 6, iclass 4, count 0 2006.286.05:31:51.37#ibcon#end of sib2, iclass 4, count 0 2006.286.05:31:51.37#ibcon#*after write, iclass 4, count 0 2006.286.05:31:51.37#ibcon#*before return 0, iclass 4, count 0 2006.286.05:31:51.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:31:51.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:31:51.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.05:31:51.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.05:31:51.37$vck44/va=8,3 2006.286.05:31:51.37#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.05:31:51.37#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.05:31:51.37#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:51.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:31:51.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:31:51.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:31:51.43#ibcon#enter wrdev, iclass 6, count 2 2006.286.05:31:51.43#ibcon#first serial, iclass 6, count 2 2006.286.05:31:51.43#ibcon#enter sib2, iclass 6, count 2 2006.286.05:31:51.43#ibcon#flushed, iclass 6, count 2 2006.286.05:31:51.43#ibcon#about to write, iclass 6, count 2 2006.286.05:31:51.43#ibcon#wrote, iclass 6, count 2 2006.286.05:31:51.43#ibcon#about to read 3, iclass 6, count 2 2006.286.05:31:51.45#ibcon#read 3, iclass 6, count 2 2006.286.05:31:51.45#ibcon#about to read 4, iclass 6, count 2 2006.286.05:31:51.45#ibcon#read 4, iclass 6, count 2 2006.286.05:31:51.45#ibcon#about to read 5, iclass 6, count 2 2006.286.05:31:51.45#ibcon#read 5, iclass 6, count 2 2006.286.05:31:51.45#ibcon#about to read 6, iclass 6, count 2 2006.286.05:31:51.45#ibcon#read 6, iclass 6, count 2 2006.286.05:31:51.45#ibcon#end of sib2, iclass 6, count 2 2006.286.05:31:51.45#ibcon#*mode == 0, iclass 6, count 2 2006.286.05:31:51.45#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.05:31:51.45#ibcon#[25=AT08-03\r\n] 2006.286.05:31:51.45#ibcon#*before write, iclass 6, count 2 2006.286.05:31:51.45#ibcon#enter sib2, iclass 6, count 2 2006.286.05:31:51.45#ibcon#flushed, iclass 6, count 2 2006.286.05:31:51.45#ibcon#about to write, iclass 6, count 2 2006.286.05:31:51.45#ibcon#wrote, iclass 6, count 2 2006.286.05:31:51.45#ibcon#about to read 3, iclass 6, count 2 2006.286.05:31:51.48#ibcon#read 3, iclass 6, count 2 2006.286.05:31:51.48#ibcon#about to read 4, iclass 6, count 2 2006.286.05:31:51.48#ibcon#read 4, iclass 6, count 2 2006.286.05:31:51.48#ibcon#about to read 5, iclass 6, count 2 2006.286.05:31:51.48#ibcon#read 5, iclass 6, count 2 2006.286.05:31:51.48#ibcon#about to read 6, iclass 6, count 2 2006.286.05:31:51.48#ibcon#read 6, iclass 6, count 2 2006.286.05:31:51.48#ibcon#end of sib2, iclass 6, count 2 2006.286.05:31:51.48#ibcon#*after write, iclass 6, count 2 2006.286.05:31:51.48#ibcon#*before return 0, iclass 6, count 2 2006.286.05:31:51.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:31:51.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:31:51.48#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.05:31:51.48#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:51.48#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:31:51.60#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:31:51.60#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:31:51.60#ibcon#enter wrdev, iclass 6, count 0 2006.286.05:31:51.60#ibcon#first serial, iclass 6, count 0 2006.286.05:31:51.60#ibcon#enter sib2, iclass 6, count 0 2006.286.05:31:51.60#ibcon#flushed, iclass 6, count 0 2006.286.05:31:51.60#ibcon#about to write, iclass 6, count 0 2006.286.05:31:51.60#ibcon#wrote, iclass 6, count 0 2006.286.05:31:51.60#ibcon#about to read 3, iclass 6, count 0 2006.286.05:31:51.62#ibcon#read 3, iclass 6, count 0 2006.286.05:31:51.62#ibcon#about to read 4, iclass 6, count 0 2006.286.05:31:51.62#ibcon#read 4, iclass 6, count 0 2006.286.05:31:51.62#ibcon#about to read 5, iclass 6, count 0 2006.286.05:31:51.62#ibcon#read 5, iclass 6, count 0 2006.286.05:31:51.62#ibcon#about to read 6, iclass 6, count 0 2006.286.05:31:51.62#ibcon#read 6, iclass 6, count 0 2006.286.05:31:51.62#ibcon#end of sib2, iclass 6, count 0 2006.286.05:31:51.62#ibcon#*mode == 0, iclass 6, count 0 2006.286.05:31:51.65#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.05:31:51.65#ibcon#[25=USB\r\n] 2006.286.05:31:51.65#ibcon#*before write, iclass 6, count 0 2006.286.05:31:51.65#ibcon#enter sib2, iclass 6, count 0 2006.286.05:31:51.65#ibcon#flushed, iclass 6, count 0 2006.286.05:31:51.65#ibcon#about to write, iclass 6, count 0 2006.286.05:31:51.65#ibcon#wrote, iclass 6, count 0 2006.286.05:31:51.65#ibcon#about to read 3, iclass 6, count 0 2006.286.05:31:51.68#ibcon#read 3, iclass 6, count 0 2006.286.05:31:51.68#ibcon#about to read 4, iclass 6, count 0 2006.286.05:31:51.68#ibcon#read 4, iclass 6, count 0 2006.286.05:31:51.68#ibcon#about to read 5, iclass 6, count 0 2006.286.05:31:51.68#ibcon#read 5, iclass 6, count 0 2006.286.05:31:51.68#ibcon#about to read 6, iclass 6, count 0 2006.286.05:31:51.68#ibcon#read 6, iclass 6, count 0 2006.286.05:31:51.68#ibcon#end of sib2, iclass 6, count 0 2006.286.05:31:51.68#ibcon#*after write, iclass 6, count 0 2006.286.05:31:51.68#ibcon#*before return 0, iclass 6, count 0 2006.286.05:31:51.68#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:31:51.68#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:31:51.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.05:31:51.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.05:31:51.68$vck44/vblo=1,629.99 2006.286.05:31:51.68#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.05:31:51.68#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.05:31:51.68#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:51.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:31:51.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:31:51.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:31:51.68#ibcon#enter wrdev, iclass 10, count 0 2006.286.05:31:51.68#ibcon#first serial, iclass 10, count 0 2006.286.05:31:51.68#ibcon#enter sib2, iclass 10, count 0 2006.286.05:31:51.68#ibcon#flushed, iclass 10, count 0 2006.286.05:31:51.68#ibcon#about to write, iclass 10, count 0 2006.286.05:31:51.68#ibcon#wrote, iclass 10, count 0 2006.286.05:31:51.68#ibcon#about to read 3, iclass 10, count 0 2006.286.05:31:51.70#ibcon#read 3, iclass 10, count 0 2006.286.05:31:51.70#ibcon#about to read 4, iclass 10, count 0 2006.286.05:31:51.70#ibcon#read 4, iclass 10, count 0 2006.286.05:31:51.70#ibcon#about to read 5, iclass 10, count 0 2006.286.05:31:51.70#ibcon#read 5, iclass 10, count 0 2006.286.05:31:51.70#ibcon#about to read 6, iclass 10, count 0 2006.286.05:31:51.70#ibcon#read 6, iclass 10, count 0 2006.286.05:31:51.70#ibcon#end of sib2, iclass 10, count 0 2006.286.05:31:51.70#ibcon#*mode == 0, iclass 10, count 0 2006.286.05:31:51.70#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.05:31:51.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.05:31:51.70#ibcon#*before write, iclass 10, count 0 2006.286.05:31:51.70#ibcon#enter sib2, iclass 10, count 0 2006.286.05:31:51.70#ibcon#flushed, iclass 10, count 0 2006.286.05:31:51.70#ibcon#about to write, iclass 10, count 0 2006.286.05:31:51.70#ibcon#wrote, iclass 10, count 0 2006.286.05:31:51.70#ibcon#about to read 3, iclass 10, count 0 2006.286.05:31:51.74#ibcon#read 3, iclass 10, count 0 2006.286.05:31:51.74#ibcon#about to read 4, iclass 10, count 0 2006.286.05:31:51.74#ibcon#read 4, iclass 10, count 0 2006.286.05:31:51.74#ibcon#about to read 5, iclass 10, count 0 2006.286.05:31:51.74#ibcon#read 5, iclass 10, count 0 2006.286.05:31:51.74#ibcon#about to read 6, iclass 10, count 0 2006.286.05:31:51.74#ibcon#read 6, iclass 10, count 0 2006.286.05:31:51.74#ibcon#end of sib2, iclass 10, count 0 2006.286.05:31:51.74#ibcon#*after write, iclass 10, count 0 2006.286.05:31:51.74#ibcon#*before return 0, iclass 10, count 0 2006.286.05:31:51.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:31:51.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:31:51.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.05:31:51.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.05:31:51.74$vck44/vb=1,4 2006.286.05:31:51.74#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.05:31:51.74#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.05:31:51.74#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:51.74#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:31:51.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:31:51.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:31:51.74#ibcon#enter wrdev, iclass 12, count 2 2006.286.05:31:51.74#ibcon#first serial, iclass 12, count 2 2006.286.05:31:51.74#ibcon#enter sib2, iclass 12, count 2 2006.286.05:31:51.74#ibcon#flushed, iclass 12, count 2 2006.286.05:31:51.74#ibcon#about to write, iclass 12, count 2 2006.286.05:31:51.74#ibcon#wrote, iclass 12, count 2 2006.286.05:31:51.74#ibcon#about to read 3, iclass 12, count 2 2006.286.05:31:51.76#ibcon#read 3, iclass 12, count 2 2006.286.05:31:51.76#ibcon#about to read 4, iclass 12, count 2 2006.286.05:31:51.76#ibcon#read 4, iclass 12, count 2 2006.286.05:31:51.76#ibcon#about to read 5, iclass 12, count 2 2006.286.05:31:51.76#ibcon#read 5, iclass 12, count 2 2006.286.05:31:51.76#ibcon#about to read 6, iclass 12, count 2 2006.286.05:31:51.76#ibcon#read 6, iclass 12, count 2 2006.286.05:31:51.76#ibcon#end of sib2, iclass 12, count 2 2006.286.05:31:51.76#ibcon#*mode == 0, iclass 12, count 2 2006.286.05:31:51.76#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.05:31:51.76#ibcon#[27=AT01-04\r\n] 2006.286.05:31:51.76#ibcon#*before write, iclass 12, count 2 2006.286.05:31:51.76#ibcon#enter sib2, iclass 12, count 2 2006.286.05:31:51.76#ibcon#flushed, iclass 12, count 2 2006.286.05:31:51.76#ibcon#about to write, iclass 12, count 2 2006.286.05:31:51.76#ibcon#wrote, iclass 12, count 2 2006.286.05:31:51.76#ibcon#about to read 3, iclass 12, count 2 2006.286.05:31:51.79#ibcon#read 3, iclass 12, count 2 2006.286.05:31:51.79#ibcon#about to read 4, iclass 12, count 2 2006.286.05:31:51.79#ibcon#read 4, iclass 12, count 2 2006.286.05:31:51.79#ibcon#about to read 5, iclass 12, count 2 2006.286.05:31:51.79#ibcon#read 5, iclass 12, count 2 2006.286.05:31:51.79#ibcon#about to read 6, iclass 12, count 2 2006.286.05:31:51.79#ibcon#read 6, iclass 12, count 2 2006.286.05:31:51.79#ibcon#end of sib2, iclass 12, count 2 2006.286.05:31:51.79#ibcon#*after write, iclass 12, count 2 2006.286.05:31:51.79#ibcon#*before return 0, iclass 12, count 2 2006.286.05:31:51.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:31:51.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:31:51.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.05:31:51.79#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:51.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:31:51.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:31:51.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:31:51.91#ibcon#enter wrdev, iclass 12, count 0 2006.286.05:31:51.91#ibcon#first serial, iclass 12, count 0 2006.286.05:31:51.91#ibcon#enter sib2, iclass 12, count 0 2006.286.05:31:51.91#ibcon#flushed, iclass 12, count 0 2006.286.05:31:51.91#ibcon#about to write, iclass 12, count 0 2006.286.05:31:51.91#ibcon#wrote, iclass 12, count 0 2006.286.05:31:51.91#ibcon#about to read 3, iclass 12, count 0 2006.286.05:31:51.93#ibcon#read 3, iclass 12, count 0 2006.286.05:31:51.93#ibcon#about to read 4, iclass 12, count 0 2006.286.05:31:51.93#ibcon#read 4, iclass 12, count 0 2006.286.05:31:51.93#ibcon#about to read 5, iclass 12, count 0 2006.286.05:31:51.93#ibcon#read 5, iclass 12, count 0 2006.286.05:31:51.93#ibcon#about to read 6, iclass 12, count 0 2006.286.05:31:51.93#ibcon#read 6, iclass 12, count 0 2006.286.05:31:51.93#ibcon#end of sib2, iclass 12, count 0 2006.286.05:31:51.93#ibcon#*mode == 0, iclass 12, count 0 2006.286.05:31:51.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.05:31:51.93#ibcon#[27=USB\r\n] 2006.286.05:31:51.93#ibcon#*before write, iclass 12, count 0 2006.286.05:31:51.93#ibcon#enter sib2, iclass 12, count 0 2006.286.05:31:51.93#ibcon#flushed, iclass 12, count 0 2006.286.05:31:51.93#ibcon#about to write, iclass 12, count 0 2006.286.05:31:51.93#ibcon#wrote, iclass 12, count 0 2006.286.05:31:51.93#ibcon#about to read 3, iclass 12, count 0 2006.286.05:31:51.96#ibcon#read 3, iclass 12, count 0 2006.286.05:31:51.96#ibcon#about to read 4, iclass 12, count 0 2006.286.05:31:51.96#ibcon#read 4, iclass 12, count 0 2006.286.05:31:51.96#ibcon#about to read 5, iclass 12, count 0 2006.286.05:31:51.96#ibcon#read 5, iclass 12, count 0 2006.286.05:31:51.96#ibcon#about to read 6, iclass 12, count 0 2006.286.05:31:51.96#ibcon#read 6, iclass 12, count 0 2006.286.05:31:51.96#ibcon#end of sib2, iclass 12, count 0 2006.286.05:31:51.96#ibcon#*after write, iclass 12, count 0 2006.286.05:31:51.96#ibcon#*before return 0, iclass 12, count 0 2006.286.05:31:51.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:31:51.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:31:51.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.05:31:51.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.05:31:51.96$vck44/vblo=2,634.99 2006.286.05:31:51.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.05:31:51.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.05:31:51.96#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:51.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:31:51.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:31:51.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:31:51.96#ibcon#enter wrdev, iclass 14, count 0 2006.286.05:31:51.96#ibcon#first serial, iclass 14, count 0 2006.286.05:31:51.96#ibcon#enter sib2, iclass 14, count 0 2006.286.05:31:51.96#ibcon#flushed, iclass 14, count 0 2006.286.05:31:51.96#ibcon#about to write, iclass 14, count 0 2006.286.05:31:51.96#ibcon#wrote, iclass 14, count 0 2006.286.05:31:51.96#ibcon#about to read 3, iclass 14, count 0 2006.286.05:31:51.98#ibcon#read 3, iclass 14, count 0 2006.286.05:31:51.98#ibcon#about to read 4, iclass 14, count 0 2006.286.05:31:51.98#ibcon#read 4, iclass 14, count 0 2006.286.05:31:51.98#ibcon#about to read 5, iclass 14, count 0 2006.286.05:31:51.98#ibcon#read 5, iclass 14, count 0 2006.286.05:31:51.98#ibcon#about to read 6, iclass 14, count 0 2006.286.05:31:51.98#ibcon#read 6, iclass 14, count 0 2006.286.05:31:51.98#ibcon#end of sib2, iclass 14, count 0 2006.286.05:31:51.98#ibcon#*mode == 0, iclass 14, count 0 2006.286.05:31:51.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.05:31:51.98#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.05:31:51.98#ibcon#*before write, iclass 14, count 0 2006.286.05:31:51.98#ibcon#enter sib2, iclass 14, count 0 2006.286.05:31:51.98#ibcon#flushed, iclass 14, count 0 2006.286.05:31:51.98#ibcon#about to write, iclass 14, count 0 2006.286.05:31:51.98#ibcon#wrote, iclass 14, count 0 2006.286.05:31:51.98#ibcon#about to read 3, iclass 14, count 0 2006.286.05:31:52.02#ibcon#read 3, iclass 14, count 0 2006.286.05:31:52.02#ibcon#about to read 4, iclass 14, count 0 2006.286.05:31:52.02#ibcon#read 4, iclass 14, count 0 2006.286.05:31:52.02#ibcon#about to read 5, iclass 14, count 0 2006.286.05:31:52.02#ibcon#read 5, iclass 14, count 0 2006.286.05:31:52.02#ibcon#about to read 6, iclass 14, count 0 2006.286.05:31:52.02#ibcon#read 6, iclass 14, count 0 2006.286.05:31:52.02#ibcon#end of sib2, iclass 14, count 0 2006.286.05:31:52.02#ibcon#*after write, iclass 14, count 0 2006.286.05:31:52.02#ibcon#*before return 0, iclass 14, count 0 2006.286.05:31:52.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:31:52.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:31:52.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.05:31:52.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.05:31:52.02$vck44/vb=2,5 2006.286.05:31:52.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.05:31:52.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.05:31:52.02#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:52.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:31:52.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:31:52.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:31:52.08#ibcon#enter wrdev, iclass 16, count 2 2006.286.05:31:52.08#ibcon#first serial, iclass 16, count 2 2006.286.05:31:52.08#ibcon#enter sib2, iclass 16, count 2 2006.286.05:31:52.08#ibcon#flushed, iclass 16, count 2 2006.286.05:31:52.08#ibcon#about to write, iclass 16, count 2 2006.286.05:31:52.08#ibcon#wrote, iclass 16, count 2 2006.286.05:31:52.08#ibcon#about to read 3, iclass 16, count 2 2006.286.05:31:52.10#ibcon#read 3, iclass 16, count 2 2006.286.05:31:52.10#ibcon#about to read 4, iclass 16, count 2 2006.286.05:31:52.10#ibcon#read 4, iclass 16, count 2 2006.286.05:31:52.10#ibcon#about to read 5, iclass 16, count 2 2006.286.05:31:52.10#ibcon#read 5, iclass 16, count 2 2006.286.05:31:52.10#ibcon#about to read 6, iclass 16, count 2 2006.286.05:31:52.10#ibcon#read 6, iclass 16, count 2 2006.286.05:31:52.10#ibcon#end of sib2, iclass 16, count 2 2006.286.05:31:52.10#ibcon#*mode == 0, iclass 16, count 2 2006.286.05:31:52.10#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.05:31:52.10#ibcon#[27=AT02-05\r\n] 2006.286.05:31:52.10#ibcon#*before write, iclass 16, count 2 2006.286.05:31:52.10#ibcon#enter sib2, iclass 16, count 2 2006.286.05:31:52.10#ibcon#flushed, iclass 16, count 2 2006.286.05:31:52.10#ibcon#about to write, iclass 16, count 2 2006.286.05:31:52.10#ibcon#wrote, iclass 16, count 2 2006.286.05:31:52.10#ibcon#about to read 3, iclass 16, count 2 2006.286.05:31:52.13#ibcon#read 3, iclass 16, count 2 2006.286.05:31:52.13#ibcon#about to read 4, iclass 16, count 2 2006.286.05:31:52.13#ibcon#read 4, iclass 16, count 2 2006.286.05:31:52.13#ibcon#about to read 5, iclass 16, count 2 2006.286.05:31:52.13#ibcon#read 5, iclass 16, count 2 2006.286.05:31:52.13#ibcon#about to read 6, iclass 16, count 2 2006.286.05:31:52.13#ibcon#read 6, iclass 16, count 2 2006.286.05:31:52.13#ibcon#end of sib2, iclass 16, count 2 2006.286.05:31:52.13#ibcon#*after write, iclass 16, count 2 2006.286.05:31:52.13#ibcon#*before return 0, iclass 16, count 2 2006.286.05:31:52.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:31:52.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:31:52.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.05:31:52.13#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:52.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:31:52.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:31:52.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:31:52.25#ibcon#enter wrdev, iclass 16, count 0 2006.286.05:31:52.25#ibcon#first serial, iclass 16, count 0 2006.286.05:31:52.25#ibcon#enter sib2, iclass 16, count 0 2006.286.05:31:52.25#ibcon#flushed, iclass 16, count 0 2006.286.05:31:52.25#ibcon#about to write, iclass 16, count 0 2006.286.05:31:52.25#ibcon#wrote, iclass 16, count 0 2006.286.05:31:52.25#ibcon#about to read 3, iclass 16, count 0 2006.286.05:31:52.27#ibcon#read 3, iclass 16, count 0 2006.286.05:31:52.27#ibcon#about to read 4, iclass 16, count 0 2006.286.05:31:52.27#ibcon#read 4, iclass 16, count 0 2006.286.05:31:52.27#ibcon#about to read 5, iclass 16, count 0 2006.286.05:31:52.27#ibcon#read 5, iclass 16, count 0 2006.286.05:31:52.27#ibcon#about to read 6, iclass 16, count 0 2006.286.05:31:52.27#ibcon#read 6, iclass 16, count 0 2006.286.05:31:52.27#ibcon#end of sib2, iclass 16, count 0 2006.286.05:31:52.27#ibcon#*mode == 0, iclass 16, count 0 2006.286.05:31:52.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.05:31:52.27#ibcon#[27=USB\r\n] 2006.286.05:31:52.27#ibcon#*before write, iclass 16, count 0 2006.286.05:31:52.27#ibcon#enter sib2, iclass 16, count 0 2006.286.05:31:52.27#ibcon#flushed, iclass 16, count 0 2006.286.05:31:52.27#ibcon#about to write, iclass 16, count 0 2006.286.05:31:52.27#ibcon#wrote, iclass 16, count 0 2006.286.05:31:52.27#ibcon#about to read 3, iclass 16, count 0 2006.286.05:31:52.30#ibcon#read 3, iclass 16, count 0 2006.286.05:31:52.30#ibcon#about to read 4, iclass 16, count 0 2006.286.05:31:52.30#ibcon#read 4, iclass 16, count 0 2006.286.05:31:52.30#ibcon#about to read 5, iclass 16, count 0 2006.286.05:31:52.30#ibcon#read 5, iclass 16, count 0 2006.286.05:31:52.30#ibcon#about to read 6, iclass 16, count 0 2006.286.05:31:52.30#ibcon#read 6, iclass 16, count 0 2006.286.05:31:52.30#ibcon#end of sib2, iclass 16, count 0 2006.286.05:31:52.30#ibcon#*after write, iclass 16, count 0 2006.286.05:31:52.30#ibcon#*before return 0, iclass 16, count 0 2006.286.05:31:52.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:31:52.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:31:52.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.05:31:52.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.05:31:52.30$vck44/vblo=3,649.99 2006.286.05:31:52.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.05:31:52.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.05:31:52.30#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:52.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:31:52.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:31:52.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:31:52.30#ibcon#enter wrdev, iclass 18, count 0 2006.286.05:31:52.30#ibcon#first serial, iclass 18, count 0 2006.286.05:31:52.30#ibcon#enter sib2, iclass 18, count 0 2006.286.05:31:52.30#ibcon#flushed, iclass 18, count 0 2006.286.05:31:52.30#ibcon#about to write, iclass 18, count 0 2006.286.05:31:52.30#ibcon#wrote, iclass 18, count 0 2006.286.05:31:52.30#ibcon#about to read 3, iclass 18, count 0 2006.286.05:31:52.32#ibcon#read 3, iclass 18, count 0 2006.286.05:31:52.32#ibcon#about to read 4, iclass 18, count 0 2006.286.05:31:52.32#ibcon#read 4, iclass 18, count 0 2006.286.05:31:52.32#ibcon#about to read 5, iclass 18, count 0 2006.286.05:31:52.32#ibcon#read 5, iclass 18, count 0 2006.286.05:31:52.32#ibcon#about to read 6, iclass 18, count 0 2006.286.05:31:52.32#ibcon#read 6, iclass 18, count 0 2006.286.05:31:52.32#ibcon#end of sib2, iclass 18, count 0 2006.286.05:31:52.32#ibcon#*mode == 0, iclass 18, count 0 2006.286.05:31:52.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.05:31:52.32#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.05:31:52.32#ibcon#*before write, iclass 18, count 0 2006.286.05:31:52.32#ibcon#enter sib2, iclass 18, count 0 2006.286.05:31:52.32#ibcon#flushed, iclass 18, count 0 2006.286.05:31:52.32#ibcon#about to write, iclass 18, count 0 2006.286.05:31:52.32#ibcon#wrote, iclass 18, count 0 2006.286.05:31:52.32#ibcon#about to read 3, iclass 18, count 0 2006.286.05:31:52.36#ibcon#read 3, iclass 18, count 0 2006.286.05:31:52.36#ibcon#about to read 4, iclass 18, count 0 2006.286.05:31:52.36#ibcon#read 4, iclass 18, count 0 2006.286.05:31:52.36#ibcon#about to read 5, iclass 18, count 0 2006.286.05:31:52.36#ibcon#read 5, iclass 18, count 0 2006.286.05:31:52.36#ibcon#about to read 6, iclass 18, count 0 2006.286.05:31:52.36#ibcon#read 6, iclass 18, count 0 2006.286.05:31:52.36#ibcon#end of sib2, iclass 18, count 0 2006.286.05:31:52.36#ibcon#*after write, iclass 18, count 0 2006.286.05:31:52.36#ibcon#*before return 0, iclass 18, count 0 2006.286.05:31:52.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:31:52.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:31:52.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.05:31:52.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.05:31:52.36$vck44/vb=3,4 2006.286.05:31:52.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.05:31:52.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.05:31:52.36#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:52.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:31:52.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:31:52.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:31:52.42#ibcon#enter wrdev, iclass 20, count 2 2006.286.05:31:52.42#ibcon#first serial, iclass 20, count 2 2006.286.05:31:52.42#ibcon#enter sib2, iclass 20, count 2 2006.286.05:31:52.42#ibcon#flushed, iclass 20, count 2 2006.286.05:31:52.42#ibcon#about to write, iclass 20, count 2 2006.286.05:31:52.42#ibcon#wrote, iclass 20, count 2 2006.286.05:31:52.42#ibcon#about to read 3, iclass 20, count 2 2006.286.05:31:52.44#ibcon#read 3, iclass 20, count 2 2006.286.05:31:52.44#ibcon#about to read 4, iclass 20, count 2 2006.286.05:31:52.44#ibcon#read 4, iclass 20, count 2 2006.286.05:31:52.44#ibcon#about to read 5, iclass 20, count 2 2006.286.05:31:52.44#ibcon#read 5, iclass 20, count 2 2006.286.05:31:52.44#ibcon#about to read 6, iclass 20, count 2 2006.286.05:31:52.44#ibcon#read 6, iclass 20, count 2 2006.286.05:31:52.44#ibcon#end of sib2, iclass 20, count 2 2006.286.05:31:52.44#ibcon#*mode == 0, iclass 20, count 2 2006.286.05:31:52.44#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.05:31:52.44#ibcon#[27=AT03-04\r\n] 2006.286.05:31:52.44#ibcon#*before write, iclass 20, count 2 2006.286.05:31:52.44#ibcon#enter sib2, iclass 20, count 2 2006.286.05:31:52.44#ibcon#flushed, iclass 20, count 2 2006.286.05:31:52.44#ibcon#about to write, iclass 20, count 2 2006.286.05:31:52.44#ibcon#wrote, iclass 20, count 2 2006.286.05:31:52.44#ibcon#about to read 3, iclass 20, count 2 2006.286.05:31:52.47#ibcon#read 3, iclass 20, count 2 2006.286.05:31:52.47#ibcon#about to read 4, iclass 20, count 2 2006.286.05:31:52.47#ibcon#read 4, iclass 20, count 2 2006.286.05:31:52.47#ibcon#about to read 5, iclass 20, count 2 2006.286.05:31:52.47#ibcon#read 5, iclass 20, count 2 2006.286.05:31:52.47#ibcon#about to read 6, iclass 20, count 2 2006.286.05:31:52.47#ibcon#read 6, iclass 20, count 2 2006.286.05:31:52.47#ibcon#end of sib2, iclass 20, count 2 2006.286.05:31:52.47#ibcon#*after write, iclass 20, count 2 2006.286.05:31:52.47#ibcon#*before return 0, iclass 20, count 2 2006.286.05:31:52.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:31:52.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:31:52.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.05:31:52.47#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:52.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:31:52.59#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:31:52.59#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:31:52.59#ibcon#enter wrdev, iclass 20, count 0 2006.286.05:31:52.59#ibcon#first serial, iclass 20, count 0 2006.286.05:31:52.59#ibcon#enter sib2, iclass 20, count 0 2006.286.05:31:52.59#ibcon#flushed, iclass 20, count 0 2006.286.05:31:52.59#ibcon#about to write, iclass 20, count 0 2006.286.05:31:52.59#ibcon#wrote, iclass 20, count 0 2006.286.05:31:52.59#ibcon#about to read 3, iclass 20, count 0 2006.286.05:31:52.61#ibcon#read 3, iclass 20, count 0 2006.286.05:31:52.61#ibcon#about to read 4, iclass 20, count 0 2006.286.05:31:52.61#ibcon#read 4, iclass 20, count 0 2006.286.05:31:52.61#ibcon#about to read 5, iclass 20, count 0 2006.286.05:31:52.61#ibcon#read 5, iclass 20, count 0 2006.286.05:31:52.61#ibcon#about to read 6, iclass 20, count 0 2006.286.05:31:52.61#ibcon#read 6, iclass 20, count 0 2006.286.05:31:52.61#ibcon#end of sib2, iclass 20, count 0 2006.286.05:31:52.61#ibcon#*mode == 0, iclass 20, count 0 2006.286.05:31:52.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.05:31:52.61#ibcon#[27=USB\r\n] 2006.286.05:31:52.61#ibcon#*before write, iclass 20, count 0 2006.286.05:31:52.61#ibcon#enter sib2, iclass 20, count 0 2006.286.05:31:52.61#ibcon#flushed, iclass 20, count 0 2006.286.05:31:52.61#ibcon#about to write, iclass 20, count 0 2006.286.05:31:52.61#ibcon#wrote, iclass 20, count 0 2006.286.05:31:52.61#ibcon#about to read 3, iclass 20, count 0 2006.286.05:31:52.64#ibcon#read 3, iclass 20, count 0 2006.286.05:31:52.64#ibcon#about to read 4, iclass 20, count 0 2006.286.05:31:52.64#ibcon#read 4, iclass 20, count 0 2006.286.05:31:52.64#ibcon#about to read 5, iclass 20, count 0 2006.286.05:31:52.64#ibcon#read 5, iclass 20, count 0 2006.286.05:31:52.64#ibcon#about to read 6, iclass 20, count 0 2006.286.05:31:52.64#ibcon#read 6, iclass 20, count 0 2006.286.05:31:52.64#ibcon#end of sib2, iclass 20, count 0 2006.286.05:31:52.64#ibcon#*after write, iclass 20, count 0 2006.286.05:31:52.64#ibcon#*before return 0, iclass 20, count 0 2006.286.05:31:52.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:31:52.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:31:52.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.05:31:52.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.05:31:52.64$vck44/vblo=4,679.99 2006.286.05:31:52.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.05:31:52.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.05:31:52.78#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:52.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:31:52.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:31:52.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:31:52.78#ibcon#enter wrdev, iclass 22, count 0 2006.286.05:31:52.78#ibcon#first serial, iclass 22, count 0 2006.286.05:31:52.78#ibcon#enter sib2, iclass 22, count 0 2006.286.05:31:52.78#ibcon#flushed, iclass 22, count 0 2006.286.05:31:52.78#ibcon#about to write, iclass 22, count 0 2006.286.05:31:52.78#ibcon#wrote, iclass 22, count 0 2006.286.05:31:52.78#ibcon#about to read 3, iclass 22, count 0 2006.286.05:31:52.80#ibcon#read 3, iclass 22, count 0 2006.286.05:31:52.80#ibcon#about to read 4, iclass 22, count 0 2006.286.05:31:52.80#ibcon#read 4, iclass 22, count 0 2006.286.05:31:52.80#ibcon#about to read 5, iclass 22, count 0 2006.286.05:31:52.80#ibcon#read 5, iclass 22, count 0 2006.286.05:31:52.80#ibcon#about to read 6, iclass 22, count 0 2006.286.05:31:52.80#ibcon#read 6, iclass 22, count 0 2006.286.05:31:52.80#ibcon#end of sib2, iclass 22, count 0 2006.286.05:31:52.80#ibcon#*mode == 0, iclass 22, count 0 2006.286.05:31:52.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.05:31:52.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.05:31:52.80#ibcon#*before write, iclass 22, count 0 2006.286.05:31:52.80#ibcon#enter sib2, iclass 22, count 0 2006.286.05:31:52.80#ibcon#flushed, iclass 22, count 0 2006.286.05:31:52.80#ibcon#about to write, iclass 22, count 0 2006.286.05:31:52.80#ibcon#wrote, iclass 22, count 0 2006.286.05:31:52.80#ibcon#about to read 3, iclass 22, count 0 2006.286.05:31:52.84#ibcon#read 3, iclass 22, count 0 2006.286.05:31:52.84#ibcon#about to read 4, iclass 22, count 0 2006.286.05:31:52.84#ibcon#read 4, iclass 22, count 0 2006.286.05:31:52.84#ibcon#about to read 5, iclass 22, count 0 2006.286.05:31:52.84#ibcon#read 5, iclass 22, count 0 2006.286.05:31:52.84#ibcon#about to read 6, iclass 22, count 0 2006.286.05:31:52.84#ibcon#read 6, iclass 22, count 0 2006.286.05:31:52.84#ibcon#end of sib2, iclass 22, count 0 2006.286.05:31:52.84#ibcon#*after write, iclass 22, count 0 2006.286.05:31:52.84#ibcon#*before return 0, iclass 22, count 0 2006.286.05:31:52.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:31:52.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:31:52.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.05:31:52.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.05:31:52.84$vck44/vb=4,5 2006.286.05:31:52.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.05:31:52.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.05:31:52.84#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:52.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:31:52.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:31:52.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:31:52.84#ibcon#enter wrdev, iclass 24, count 2 2006.286.05:31:52.84#ibcon#first serial, iclass 24, count 2 2006.286.05:31:52.84#ibcon#enter sib2, iclass 24, count 2 2006.286.05:31:52.84#ibcon#flushed, iclass 24, count 2 2006.286.05:31:52.84#ibcon#about to write, iclass 24, count 2 2006.286.05:31:52.84#ibcon#wrote, iclass 24, count 2 2006.286.05:31:52.84#ibcon#about to read 3, iclass 24, count 2 2006.286.05:31:52.86#ibcon#read 3, iclass 24, count 2 2006.286.05:31:52.86#ibcon#about to read 4, iclass 24, count 2 2006.286.05:31:52.86#ibcon#read 4, iclass 24, count 2 2006.286.05:31:52.86#ibcon#about to read 5, iclass 24, count 2 2006.286.05:31:52.86#ibcon#read 5, iclass 24, count 2 2006.286.05:31:52.86#ibcon#about to read 6, iclass 24, count 2 2006.286.05:31:52.86#ibcon#read 6, iclass 24, count 2 2006.286.05:31:52.86#ibcon#end of sib2, iclass 24, count 2 2006.286.05:31:52.86#ibcon#*mode == 0, iclass 24, count 2 2006.286.05:31:52.86#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.05:31:52.86#ibcon#[27=AT04-05\r\n] 2006.286.05:31:52.86#ibcon#*before write, iclass 24, count 2 2006.286.05:31:52.86#ibcon#enter sib2, iclass 24, count 2 2006.286.05:31:52.86#ibcon#flushed, iclass 24, count 2 2006.286.05:31:52.86#ibcon#about to write, iclass 24, count 2 2006.286.05:31:52.86#ibcon#wrote, iclass 24, count 2 2006.286.05:31:52.86#ibcon#about to read 3, iclass 24, count 2 2006.286.05:31:52.89#ibcon#read 3, iclass 24, count 2 2006.286.05:31:52.89#ibcon#about to read 4, iclass 24, count 2 2006.286.05:31:52.89#ibcon#read 4, iclass 24, count 2 2006.286.05:31:52.89#ibcon#about to read 5, iclass 24, count 2 2006.286.05:31:52.89#ibcon#read 5, iclass 24, count 2 2006.286.05:31:52.89#ibcon#about to read 6, iclass 24, count 2 2006.286.05:31:52.89#ibcon#read 6, iclass 24, count 2 2006.286.05:31:52.89#ibcon#end of sib2, iclass 24, count 2 2006.286.05:31:52.89#ibcon#*after write, iclass 24, count 2 2006.286.05:31:52.89#ibcon#*before return 0, iclass 24, count 2 2006.286.05:31:52.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:31:52.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:31:52.89#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.05:31:52.89#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:52.89#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:31:53.01#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:31:53.01#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:31:53.01#ibcon#enter wrdev, iclass 24, count 0 2006.286.05:31:53.01#ibcon#first serial, iclass 24, count 0 2006.286.05:31:53.01#ibcon#enter sib2, iclass 24, count 0 2006.286.05:31:53.01#ibcon#flushed, iclass 24, count 0 2006.286.05:31:53.01#ibcon#about to write, iclass 24, count 0 2006.286.05:31:53.01#ibcon#wrote, iclass 24, count 0 2006.286.05:31:53.01#ibcon#about to read 3, iclass 24, count 0 2006.286.05:31:53.03#ibcon#read 3, iclass 24, count 0 2006.286.05:31:53.03#ibcon#about to read 4, iclass 24, count 0 2006.286.05:31:53.03#ibcon#read 4, iclass 24, count 0 2006.286.05:31:53.03#ibcon#about to read 5, iclass 24, count 0 2006.286.05:31:53.03#ibcon#read 5, iclass 24, count 0 2006.286.05:31:53.03#ibcon#about to read 6, iclass 24, count 0 2006.286.05:31:53.03#ibcon#read 6, iclass 24, count 0 2006.286.05:31:53.03#ibcon#end of sib2, iclass 24, count 0 2006.286.05:31:53.03#ibcon#*mode == 0, iclass 24, count 0 2006.286.05:31:53.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.05:31:53.03#ibcon#[27=USB\r\n] 2006.286.05:31:53.03#ibcon#*before write, iclass 24, count 0 2006.286.05:31:53.03#ibcon#enter sib2, iclass 24, count 0 2006.286.05:31:53.03#ibcon#flushed, iclass 24, count 0 2006.286.05:31:53.03#ibcon#about to write, iclass 24, count 0 2006.286.05:31:53.03#ibcon#wrote, iclass 24, count 0 2006.286.05:31:53.03#ibcon#about to read 3, iclass 24, count 0 2006.286.05:31:53.06#ibcon#read 3, iclass 24, count 0 2006.286.05:31:53.06#ibcon#about to read 4, iclass 24, count 0 2006.286.05:31:53.06#ibcon#read 4, iclass 24, count 0 2006.286.05:31:53.06#ibcon#about to read 5, iclass 24, count 0 2006.286.05:31:53.06#ibcon#read 5, iclass 24, count 0 2006.286.05:31:53.06#ibcon#about to read 6, iclass 24, count 0 2006.286.05:31:53.06#ibcon#read 6, iclass 24, count 0 2006.286.05:31:53.06#ibcon#end of sib2, iclass 24, count 0 2006.286.05:31:53.06#ibcon#*after write, iclass 24, count 0 2006.286.05:31:53.06#ibcon#*before return 0, iclass 24, count 0 2006.286.05:31:53.06#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:31:53.06#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:31:53.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.05:31:53.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.05:31:53.06$vck44/vblo=5,709.99 2006.286.05:31:53.06#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.05:31:53.06#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.05:31:53.06#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:53.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:31:53.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:31:53.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:31:53.06#ibcon#enter wrdev, iclass 26, count 0 2006.286.05:31:53.06#ibcon#first serial, iclass 26, count 0 2006.286.05:31:53.06#ibcon#enter sib2, iclass 26, count 0 2006.286.05:31:53.06#ibcon#flushed, iclass 26, count 0 2006.286.05:31:53.06#ibcon#about to write, iclass 26, count 0 2006.286.05:31:53.06#ibcon#wrote, iclass 26, count 0 2006.286.05:31:53.06#ibcon#about to read 3, iclass 26, count 0 2006.286.05:31:53.08#ibcon#read 3, iclass 26, count 0 2006.286.05:31:53.08#ibcon#about to read 4, iclass 26, count 0 2006.286.05:31:53.08#ibcon#read 4, iclass 26, count 0 2006.286.05:31:53.08#ibcon#about to read 5, iclass 26, count 0 2006.286.05:31:53.08#ibcon#read 5, iclass 26, count 0 2006.286.05:31:53.08#ibcon#about to read 6, iclass 26, count 0 2006.286.05:31:53.08#ibcon#read 6, iclass 26, count 0 2006.286.05:31:53.08#ibcon#end of sib2, iclass 26, count 0 2006.286.05:31:53.08#ibcon#*mode == 0, iclass 26, count 0 2006.286.05:31:53.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.05:31:53.08#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.05:31:53.08#ibcon#*before write, iclass 26, count 0 2006.286.05:31:53.08#ibcon#enter sib2, iclass 26, count 0 2006.286.05:31:53.08#ibcon#flushed, iclass 26, count 0 2006.286.05:31:53.08#ibcon#about to write, iclass 26, count 0 2006.286.05:31:53.08#ibcon#wrote, iclass 26, count 0 2006.286.05:31:53.08#ibcon#about to read 3, iclass 26, count 0 2006.286.05:31:53.12#ibcon#read 3, iclass 26, count 0 2006.286.05:31:53.12#ibcon#about to read 4, iclass 26, count 0 2006.286.05:31:53.12#ibcon#read 4, iclass 26, count 0 2006.286.05:31:53.12#ibcon#about to read 5, iclass 26, count 0 2006.286.05:31:53.12#ibcon#read 5, iclass 26, count 0 2006.286.05:31:53.12#ibcon#about to read 6, iclass 26, count 0 2006.286.05:31:53.12#ibcon#read 6, iclass 26, count 0 2006.286.05:31:53.12#ibcon#end of sib2, iclass 26, count 0 2006.286.05:31:53.12#ibcon#*after write, iclass 26, count 0 2006.286.05:31:53.12#ibcon#*before return 0, iclass 26, count 0 2006.286.05:31:53.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:31:53.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:31:53.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.05:31:53.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.05:31:53.12$vck44/vb=5,4 2006.286.05:31:53.12#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.05:31:53.12#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.05:31:53.12#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:53.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:31:53.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:31:53.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:31:53.18#ibcon#enter wrdev, iclass 28, count 2 2006.286.05:31:53.18#ibcon#first serial, iclass 28, count 2 2006.286.05:31:53.18#ibcon#enter sib2, iclass 28, count 2 2006.286.05:31:53.18#ibcon#flushed, iclass 28, count 2 2006.286.05:31:53.18#ibcon#about to write, iclass 28, count 2 2006.286.05:31:53.18#ibcon#wrote, iclass 28, count 2 2006.286.05:31:53.18#ibcon#about to read 3, iclass 28, count 2 2006.286.05:31:53.20#ibcon#read 3, iclass 28, count 2 2006.286.05:31:53.20#ibcon#about to read 4, iclass 28, count 2 2006.286.05:31:53.20#ibcon#read 4, iclass 28, count 2 2006.286.05:31:53.20#ibcon#about to read 5, iclass 28, count 2 2006.286.05:31:53.20#ibcon#read 5, iclass 28, count 2 2006.286.05:31:53.20#ibcon#about to read 6, iclass 28, count 2 2006.286.05:31:53.20#ibcon#read 6, iclass 28, count 2 2006.286.05:31:53.20#ibcon#end of sib2, iclass 28, count 2 2006.286.05:31:53.20#ibcon#*mode == 0, iclass 28, count 2 2006.286.05:31:53.20#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.05:31:53.20#ibcon#[27=AT05-04\r\n] 2006.286.05:31:53.20#ibcon#*before write, iclass 28, count 2 2006.286.05:31:53.20#ibcon#enter sib2, iclass 28, count 2 2006.286.05:31:53.20#ibcon#flushed, iclass 28, count 2 2006.286.05:31:53.20#ibcon#about to write, iclass 28, count 2 2006.286.05:31:53.20#ibcon#wrote, iclass 28, count 2 2006.286.05:31:53.20#ibcon#about to read 3, iclass 28, count 2 2006.286.05:31:53.23#ibcon#read 3, iclass 28, count 2 2006.286.05:31:53.23#ibcon#about to read 4, iclass 28, count 2 2006.286.05:31:53.23#ibcon#read 4, iclass 28, count 2 2006.286.05:31:53.23#ibcon#about to read 5, iclass 28, count 2 2006.286.05:31:53.23#ibcon#read 5, iclass 28, count 2 2006.286.05:31:53.23#ibcon#about to read 6, iclass 28, count 2 2006.286.05:31:53.23#ibcon#read 6, iclass 28, count 2 2006.286.05:31:53.23#ibcon#end of sib2, iclass 28, count 2 2006.286.05:31:53.23#ibcon#*after write, iclass 28, count 2 2006.286.05:31:53.23#ibcon#*before return 0, iclass 28, count 2 2006.286.05:31:53.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:31:53.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:31:53.23#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.05:31:53.23#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:53.23#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:31:53.35#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:31:53.35#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:31:53.35#ibcon#enter wrdev, iclass 28, count 0 2006.286.05:31:53.35#ibcon#first serial, iclass 28, count 0 2006.286.05:31:53.35#ibcon#enter sib2, iclass 28, count 0 2006.286.05:31:53.35#ibcon#flushed, iclass 28, count 0 2006.286.05:31:53.35#ibcon#about to write, iclass 28, count 0 2006.286.05:31:53.35#ibcon#wrote, iclass 28, count 0 2006.286.05:31:53.35#ibcon#about to read 3, iclass 28, count 0 2006.286.05:31:53.37#ibcon#read 3, iclass 28, count 0 2006.286.05:31:53.37#ibcon#about to read 4, iclass 28, count 0 2006.286.05:31:53.37#ibcon#read 4, iclass 28, count 0 2006.286.05:31:53.37#ibcon#about to read 5, iclass 28, count 0 2006.286.05:31:53.37#ibcon#read 5, iclass 28, count 0 2006.286.05:31:53.37#ibcon#about to read 6, iclass 28, count 0 2006.286.05:31:53.37#ibcon#read 6, iclass 28, count 0 2006.286.05:31:53.37#ibcon#end of sib2, iclass 28, count 0 2006.286.05:31:53.37#ibcon#*mode == 0, iclass 28, count 0 2006.286.05:31:53.37#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.05:31:53.37#ibcon#[27=USB\r\n] 2006.286.05:31:53.37#ibcon#*before write, iclass 28, count 0 2006.286.05:31:53.37#ibcon#enter sib2, iclass 28, count 0 2006.286.05:31:53.37#ibcon#flushed, iclass 28, count 0 2006.286.05:31:53.37#ibcon#about to write, iclass 28, count 0 2006.286.05:31:53.37#ibcon#wrote, iclass 28, count 0 2006.286.05:31:53.37#ibcon#about to read 3, iclass 28, count 0 2006.286.05:31:53.40#ibcon#read 3, iclass 28, count 0 2006.286.05:31:53.40#ibcon#about to read 4, iclass 28, count 0 2006.286.05:31:53.40#ibcon#read 4, iclass 28, count 0 2006.286.05:31:53.40#ibcon#about to read 5, iclass 28, count 0 2006.286.05:31:53.40#ibcon#read 5, iclass 28, count 0 2006.286.05:31:53.40#ibcon#about to read 6, iclass 28, count 0 2006.286.05:31:53.40#ibcon#read 6, iclass 28, count 0 2006.286.05:31:53.40#ibcon#end of sib2, iclass 28, count 0 2006.286.05:31:53.40#ibcon#*after write, iclass 28, count 0 2006.286.05:31:53.40#ibcon#*before return 0, iclass 28, count 0 2006.286.05:31:53.40#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:31:53.40#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:31:53.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.05:31:53.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.05:31:53.40$vck44/vblo=6,719.99 2006.286.05:31:53.40#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.05:31:53.40#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.05:31:53.40#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:53.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:31:53.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:31:53.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:31:53.40#ibcon#enter wrdev, iclass 30, count 0 2006.286.05:31:53.40#ibcon#first serial, iclass 30, count 0 2006.286.05:31:53.40#ibcon#enter sib2, iclass 30, count 0 2006.286.05:31:53.40#ibcon#flushed, iclass 30, count 0 2006.286.05:31:53.40#ibcon#about to write, iclass 30, count 0 2006.286.05:31:53.40#ibcon#wrote, iclass 30, count 0 2006.286.05:31:53.40#ibcon#about to read 3, iclass 30, count 0 2006.286.05:31:53.42#ibcon#read 3, iclass 30, count 0 2006.286.05:31:53.42#ibcon#about to read 4, iclass 30, count 0 2006.286.05:31:53.42#ibcon#read 4, iclass 30, count 0 2006.286.05:31:53.42#ibcon#about to read 5, iclass 30, count 0 2006.286.05:31:53.42#ibcon#read 5, iclass 30, count 0 2006.286.05:31:53.42#ibcon#about to read 6, iclass 30, count 0 2006.286.05:31:53.42#ibcon#read 6, iclass 30, count 0 2006.286.05:31:53.42#ibcon#end of sib2, iclass 30, count 0 2006.286.05:31:53.42#ibcon#*mode == 0, iclass 30, count 0 2006.286.05:31:53.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.05:31:53.42#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.05:31:53.42#ibcon#*before write, iclass 30, count 0 2006.286.05:31:53.42#ibcon#enter sib2, iclass 30, count 0 2006.286.05:31:53.42#ibcon#flushed, iclass 30, count 0 2006.286.05:31:53.42#ibcon#about to write, iclass 30, count 0 2006.286.05:31:53.42#ibcon#wrote, iclass 30, count 0 2006.286.05:31:53.42#ibcon#about to read 3, iclass 30, count 0 2006.286.05:31:53.46#ibcon#read 3, iclass 30, count 0 2006.286.05:31:53.46#ibcon#about to read 4, iclass 30, count 0 2006.286.05:31:53.46#ibcon#read 4, iclass 30, count 0 2006.286.05:31:53.46#ibcon#about to read 5, iclass 30, count 0 2006.286.05:31:53.46#ibcon#read 5, iclass 30, count 0 2006.286.05:31:53.46#ibcon#about to read 6, iclass 30, count 0 2006.286.05:31:53.46#ibcon#read 6, iclass 30, count 0 2006.286.05:31:53.46#ibcon#end of sib2, iclass 30, count 0 2006.286.05:31:53.46#ibcon#*after write, iclass 30, count 0 2006.286.05:31:53.46#ibcon#*before return 0, iclass 30, count 0 2006.286.05:31:53.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:31:53.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:31:53.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.05:31:53.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.05:31:53.46$vck44/vb=6,3 2006.286.05:31:53.46#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.05:31:53.46#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.05:31:53.46#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:53.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:31:53.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:31:53.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:31:53.52#ibcon#enter wrdev, iclass 32, count 2 2006.286.05:31:53.52#ibcon#first serial, iclass 32, count 2 2006.286.05:31:53.52#ibcon#enter sib2, iclass 32, count 2 2006.286.05:31:53.52#ibcon#flushed, iclass 32, count 2 2006.286.05:31:53.52#ibcon#about to write, iclass 32, count 2 2006.286.05:31:53.52#ibcon#wrote, iclass 32, count 2 2006.286.05:31:53.52#ibcon#about to read 3, iclass 32, count 2 2006.286.05:31:53.54#ibcon#read 3, iclass 32, count 2 2006.286.05:31:53.54#ibcon#about to read 4, iclass 32, count 2 2006.286.05:31:53.54#ibcon#read 4, iclass 32, count 2 2006.286.05:31:53.54#ibcon#about to read 5, iclass 32, count 2 2006.286.05:31:53.54#ibcon#read 5, iclass 32, count 2 2006.286.05:31:53.54#ibcon#about to read 6, iclass 32, count 2 2006.286.05:31:53.54#ibcon#read 6, iclass 32, count 2 2006.286.05:31:53.54#ibcon#end of sib2, iclass 32, count 2 2006.286.05:31:53.54#ibcon#*mode == 0, iclass 32, count 2 2006.286.05:31:53.54#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.05:31:53.54#ibcon#[27=AT06-03\r\n] 2006.286.05:31:53.54#ibcon#*before write, iclass 32, count 2 2006.286.05:31:53.54#ibcon#enter sib2, iclass 32, count 2 2006.286.05:31:53.54#ibcon#flushed, iclass 32, count 2 2006.286.05:31:53.54#ibcon#about to write, iclass 32, count 2 2006.286.05:31:53.54#ibcon#wrote, iclass 32, count 2 2006.286.05:31:53.54#ibcon#about to read 3, iclass 32, count 2 2006.286.05:31:53.57#ibcon#read 3, iclass 32, count 2 2006.286.05:31:53.57#ibcon#about to read 4, iclass 32, count 2 2006.286.05:31:53.57#ibcon#read 4, iclass 32, count 2 2006.286.05:31:53.57#ibcon#about to read 5, iclass 32, count 2 2006.286.05:31:53.57#ibcon#read 5, iclass 32, count 2 2006.286.05:31:53.57#ibcon#about to read 6, iclass 32, count 2 2006.286.05:31:53.57#ibcon#read 6, iclass 32, count 2 2006.286.05:31:53.57#ibcon#end of sib2, iclass 32, count 2 2006.286.05:31:53.57#ibcon#*after write, iclass 32, count 2 2006.286.05:31:53.57#ibcon#*before return 0, iclass 32, count 2 2006.286.05:31:53.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:31:53.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:31:53.57#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.05:31:53.57#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:53.57#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:31:53.69#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:31:53.69#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:31:53.69#ibcon#enter wrdev, iclass 32, count 0 2006.286.05:31:53.69#ibcon#first serial, iclass 32, count 0 2006.286.05:31:53.69#ibcon#enter sib2, iclass 32, count 0 2006.286.05:31:53.69#ibcon#flushed, iclass 32, count 0 2006.286.05:31:53.69#ibcon#about to write, iclass 32, count 0 2006.286.05:31:53.69#ibcon#wrote, iclass 32, count 0 2006.286.05:31:53.69#ibcon#about to read 3, iclass 32, count 0 2006.286.05:31:53.71#ibcon#read 3, iclass 32, count 0 2006.286.05:31:53.71#ibcon#about to read 4, iclass 32, count 0 2006.286.05:31:53.71#ibcon#read 4, iclass 32, count 0 2006.286.05:31:53.71#ibcon#about to read 5, iclass 32, count 0 2006.286.05:31:53.71#ibcon#read 5, iclass 32, count 0 2006.286.05:31:53.71#ibcon#about to read 6, iclass 32, count 0 2006.286.05:31:53.71#ibcon#read 6, iclass 32, count 0 2006.286.05:31:53.71#ibcon#end of sib2, iclass 32, count 0 2006.286.05:31:53.71#ibcon#*mode == 0, iclass 32, count 0 2006.286.05:31:53.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.05:31:53.71#ibcon#[27=USB\r\n] 2006.286.05:31:53.71#ibcon#*before write, iclass 32, count 0 2006.286.05:31:53.71#ibcon#enter sib2, iclass 32, count 0 2006.286.05:31:53.71#ibcon#flushed, iclass 32, count 0 2006.286.05:31:53.71#ibcon#about to write, iclass 32, count 0 2006.286.05:31:53.71#ibcon#wrote, iclass 32, count 0 2006.286.05:31:53.71#ibcon#about to read 3, iclass 32, count 0 2006.286.05:31:53.74#ibcon#read 3, iclass 32, count 0 2006.286.05:31:53.74#ibcon#about to read 4, iclass 32, count 0 2006.286.05:31:53.74#ibcon#read 4, iclass 32, count 0 2006.286.05:31:53.74#ibcon#about to read 5, iclass 32, count 0 2006.286.05:31:53.74#ibcon#read 5, iclass 32, count 0 2006.286.05:31:53.74#ibcon#about to read 6, iclass 32, count 0 2006.286.05:31:53.74#ibcon#read 6, iclass 32, count 0 2006.286.05:31:53.74#ibcon#end of sib2, iclass 32, count 0 2006.286.05:31:53.74#ibcon#*after write, iclass 32, count 0 2006.286.05:31:53.74#ibcon#*before return 0, iclass 32, count 0 2006.286.05:31:53.74#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:31:53.74#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:31:53.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.05:31:53.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.05:31:53.74$vck44/vblo=7,734.99 2006.286.05:31:53.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.05:31:53.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.05:31:53.74#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:53.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:31:53.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:31:53.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:31:53.74#ibcon#enter wrdev, iclass 34, count 0 2006.286.05:31:53.74#ibcon#first serial, iclass 34, count 0 2006.286.05:31:53.74#ibcon#enter sib2, iclass 34, count 0 2006.286.05:31:53.74#ibcon#flushed, iclass 34, count 0 2006.286.05:31:53.74#ibcon#about to write, iclass 34, count 0 2006.286.05:31:53.74#ibcon#wrote, iclass 34, count 0 2006.286.05:31:53.74#ibcon#about to read 3, iclass 34, count 0 2006.286.05:31:53.76#ibcon#read 3, iclass 34, count 0 2006.286.05:31:53.76#ibcon#about to read 4, iclass 34, count 0 2006.286.05:31:53.76#ibcon#read 4, iclass 34, count 0 2006.286.05:31:53.76#ibcon#about to read 5, iclass 34, count 0 2006.286.05:31:53.76#ibcon#read 5, iclass 34, count 0 2006.286.05:31:53.76#ibcon#about to read 6, iclass 34, count 0 2006.286.05:31:53.76#ibcon#read 6, iclass 34, count 0 2006.286.05:31:53.76#ibcon#end of sib2, iclass 34, count 0 2006.286.05:31:53.76#ibcon#*mode == 0, iclass 34, count 0 2006.286.05:31:53.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.05:31:53.76#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.05:31:53.76#ibcon#*before write, iclass 34, count 0 2006.286.05:31:53.76#ibcon#enter sib2, iclass 34, count 0 2006.286.05:31:53.76#ibcon#flushed, iclass 34, count 0 2006.286.05:31:53.76#ibcon#about to write, iclass 34, count 0 2006.286.05:31:53.76#ibcon#wrote, iclass 34, count 0 2006.286.05:31:53.76#ibcon#about to read 3, iclass 34, count 0 2006.286.05:31:53.80#ibcon#read 3, iclass 34, count 0 2006.286.05:31:53.80#ibcon#about to read 4, iclass 34, count 0 2006.286.05:31:53.80#ibcon#read 4, iclass 34, count 0 2006.286.05:31:53.80#ibcon#about to read 5, iclass 34, count 0 2006.286.05:31:53.80#ibcon#read 5, iclass 34, count 0 2006.286.05:31:53.80#ibcon#about to read 6, iclass 34, count 0 2006.286.05:31:53.80#ibcon#read 6, iclass 34, count 0 2006.286.05:31:53.80#ibcon#end of sib2, iclass 34, count 0 2006.286.05:31:53.80#ibcon#*after write, iclass 34, count 0 2006.286.05:31:53.80#ibcon#*before return 0, iclass 34, count 0 2006.286.05:31:53.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:31:53.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:31:53.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.05:31:53.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.05:31:53.80$vck44/vb=7,4 2006.286.05:31:53.80#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.05:31:53.80#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.05:31:53.80#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:53.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:31:53.86#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:31:53.86#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:31:53.86#ibcon#enter wrdev, iclass 36, count 2 2006.286.05:31:53.86#ibcon#first serial, iclass 36, count 2 2006.286.05:31:53.86#ibcon#enter sib2, iclass 36, count 2 2006.286.05:31:53.86#ibcon#flushed, iclass 36, count 2 2006.286.05:31:53.86#ibcon#about to write, iclass 36, count 2 2006.286.05:31:53.86#ibcon#wrote, iclass 36, count 2 2006.286.05:31:53.86#ibcon#about to read 3, iclass 36, count 2 2006.286.05:31:53.88#ibcon#read 3, iclass 36, count 2 2006.286.05:31:53.88#ibcon#about to read 4, iclass 36, count 2 2006.286.05:31:53.88#ibcon#read 4, iclass 36, count 2 2006.286.05:31:53.88#ibcon#about to read 5, iclass 36, count 2 2006.286.05:31:53.88#ibcon#read 5, iclass 36, count 2 2006.286.05:31:53.88#ibcon#about to read 6, iclass 36, count 2 2006.286.05:31:53.88#ibcon#read 6, iclass 36, count 2 2006.286.05:31:53.88#ibcon#end of sib2, iclass 36, count 2 2006.286.05:31:53.88#ibcon#*mode == 0, iclass 36, count 2 2006.286.05:31:53.88#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.05:31:53.88#ibcon#[27=AT07-04\r\n] 2006.286.05:31:53.88#ibcon#*before write, iclass 36, count 2 2006.286.05:31:53.88#ibcon#enter sib2, iclass 36, count 2 2006.286.05:31:53.88#ibcon#flushed, iclass 36, count 2 2006.286.05:31:53.88#ibcon#about to write, iclass 36, count 2 2006.286.05:31:53.88#ibcon#wrote, iclass 36, count 2 2006.286.05:31:53.88#ibcon#about to read 3, iclass 36, count 2 2006.286.05:31:53.91#ibcon#read 3, iclass 36, count 2 2006.286.05:31:53.91#ibcon#about to read 4, iclass 36, count 2 2006.286.05:31:53.91#ibcon#read 4, iclass 36, count 2 2006.286.05:31:53.91#ibcon#about to read 5, iclass 36, count 2 2006.286.05:31:53.91#ibcon#read 5, iclass 36, count 2 2006.286.05:31:53.91#ibcon#about to read 6, iclass 36, count 2 2006.286.05:31:53.91#ibcon#read 6, iclass 36, count 2 2006.286.05:31:53.91#ibcon#end of sib2, iclass 36, count 2 2006.286.05:31:53.91#ibcon#*after write, iclass 36, count 2 2006.286.05:31:53.91#ibcon#*before return 0, iclass 36, count 2 2006.286.05:31:53.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:31:53.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:31:53.91#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.05:31:53.91#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:53.91#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:31:54.03#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:31:54.03#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:31:54.03#ibcon#enter wrdev, iclass 36, count 0 2006.286.05:31:54.03#ibcon#first serial, iclass 36, count 0 2006.286.05:31:54.03#ibcon#enter sib2, iclass 36, count 0 2006.286.05:31:54.03#ibcon#flushed, iclass 36, count 0 2006.286.05:31:54.03#ibcon#about to write, iclass 36, count 0 2006.286.05:31:54.03#ibcon#wrote, iclass 36, count 0 2006.286.05:31:54.03#ibcon#about to read 3, iclass 36, count 0 2006.286.05:31:54.05#ibcon#read 3, iclass 36, count 0 2006.286.05:31:54.05#ibcon#about to read 4, iclass 36, count 0 2006.286.05:31:54.05#ibcon#read 4, iclass 36, count 0 2006.286.05:31:54.05#ibcon#about to read 5, iclass 36, count 0 2006.286.05:31:54.05#ibcon#read 5, iclass 36, count 0 2006.286.05:31:54.05#ibcon#about to read 6, iclass 36, count 0 2006.286.05:31:54.05#ibcon#read 6, iclass 36, count 0 2006.286.05:31:54.05#ibcon#end of sib2, iclass 36, count 0 2006.286.05:31:54.05#ibcon#*mode == 0, iclass 36, count 0 2006.286.05:31:54.05#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.05:31:54.05#ibcon#[27=USB\r\n] 2006.286.05:31:54.05#ibcon#*before write, iclass 36, count 0 2006.286.05:31:54.05#ibcon#enter sib2, iclass 36, count 0 2006.286.05:31:54.05#ibcon#flushed, iclass 36, count 0 2006.286.05:31:54.05#ibcon#about to write, iclass 36, count 0 2006.286.05:31:54.05#ibcon#wrote, iclass 36, count 0 2006.286.05:31:54.05#ibcon#about to read 3, iclass 36, count 0 2006.286.05:31:54.08#ibcon#read 3, iclass 36, count 0 2006.286.05:31:54.08#ibcon#about to read 4, iclass 36, count 0 2006.286.05:31:54.08#ibcon#read 4, iclass 36, count 0 2006.286.05:31:54.08#ibcon#about to read 5, iclass 36, count 0 2006.286.05:31:54.08#ibcon#read 5, iclass 36, count 0 2006.286.05:31:54.08#ibcon#about to read 6, iclass 36, count 0 2006.286.05:31:54.08#ibcon#read 6, iclass 36, count 0 2006.286.05:31:54.08#ibcon#end of sib2, iclass 36, count 0 2006.286.05:31:54.08#ibcon#*after write, iclass 36, count 0 2006.286.05:31:54.08#ibcon#*before return 0, iclass 36, count 0 2006.286.05:31:54.08#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:31:54.08#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:31:54.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.05:31:54.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.05:31:54.08$vck44/vblo=8,744.99 2006.286.05:31:54.08#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.05:31:54.08#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.05:31:54.08#ibcon#ireg 17 cls_cnt 0 2006.286.05:31:54.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:31:54.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:31:54.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:31:54.08#ibcon#enter wrdev, iclass 38, count 0 2006.286.05:31:54.08#ibcon#first serial, iclass 38, count 0 2006.286.05:31:54.08#ibcon#enter sib2, iclass 38, count 0 2006.286.05:31:54.08#ibcon#flushed, iclass 38, count 0 2006.286.05:31:54.08#ibcon#about to write, iclass 38, count 0 2006.286.05:31:54.08#ibcon#wrote, iclass 38, count 0 2006.286.05:31:54.08#ibcon#about to read 3, iclass 38, count 0 2006.286.05:31:54.10#ibcon#read 3, iclass 38, count 0 2006.286.05:31:54.10#ibcon#about to read 4, iclass 38, count 0 2006.286.05:31:54.10#ibcon#read 4, iclass 38, count 0 2006.286.05:31:54.10#ibcon#about to read 5, iclass 38, count 0 2006.286.05:31:54.10#ibcon#read 5, iclass 38, count 0 2006.286.05:31:54.10#ibcon#about to read 6, iclass 38, count 0 2006.286.05:31:54.10#ibcon#read 6, iclass 38, count 0 2006.286.05:31:54.10#ibcon#end of sib2, iclass 38, count 0 2006.286.05:31:54.10#ibcon#*mode == 0, iclass 38, count 0 2006.286.05:31:54.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.05:31:54.10#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.05:31:54.10#ibcon#*before write, iclass 38, count 0 2006.286.05:31:54.10#ibcon#enter sib2, iclass 38, count 0 2006.286.05:31:54.10#ibcon#flushed, iclass 38, count 0 2006.286.05:31:54.10#ibcon#about to write, iclass 38, count 0 2006.286.05:31:54.10#ibcon#wrote, iclass 38, count 0 2006.286.05:31:54.10#ibcon#about to read 3, iclass 38, count 0 2006.286.05:31:54.14#ibcon#read 3, iclass 38, count 0 2006.286.05:31:54.14#ibcon#about to read 4, iclass 38, count 0 2006.286.05:31:54.14#ibcon#read 4, iclass 38, count 0 2006.286.05:31:54.14#ibcon#about to read 5, iclass 38, count 0 2006.286.05:31:54.14#ibcon#read 5, iclass 38, count 0 2006.286.05:31:54.14#ibcon#about to read 6, iclass 38, count 0 2006.286.05:31:54.14#ibcon#read 6, iclass 38, count 0 2006.286.05:31:54.14#ibcon#end of sib2, iclass 38, count 0 2006.286.05:31:54.14#ibcon#*after write, iclass 38, count 0 2006.286.05:31:54.14#ibcon#*before return 0, iclass 38, count 0 2006.286.05:31:54.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:31:54.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:31:54.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.05:31:54.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.05:31:54.14$vck44/vb=8,4 2006.286.05:31:54.14#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.05:31:54.14#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.05:31:54.14#ibcon#ireg 11 cls_cnt 2 2006.286.05:31:54.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:31:54.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:31:54.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:31:54.20#ibcon#enter wrdev, iclass 40, count 2 2006.286.05:31:54.20#ibcon#first serial, iclass 40, count 2 2006.286.05:31:54.20#ibcon#enter sib2, iclass 40, count 2 2006.286.05:31:54.20#ibcon#flushed, iclass 40, count 2 2006.286.05:31:54.20#ibcon#about to write, iclass 40, count 2 2006.286.05:31:54.20#ibcon#wrote, iclass 40, count 2 2006.286.05:31:54.20#ibcon#about to read 3, iclass 40, count 2 2006.286.05:31:54.22#ibcon#read 3, iclass 40, count 2 2006.286.05:31:54.22#ibcon#about to read 4, iclass 40, count 2 2006.286.05:31:54.22#ibcon#read 4, iclass 40, count 2 2006.286.05:31:54.22#ibcon#about to read 5, iclass 40, count 2 2006.286.05:31:54.22#ibcon#read 5, iclass 40, count 2 2006.286.05:31:54.22#ibcon#about to read 6, iclass 40, count 2 2006.286.05:31:54.22#ibcon#read 6, iclass 40, count 2 2006.286.05:31:54.22#ibcon#end of sib2, iclass 40, count 2 2006.286.05:31:54.22#ibcon#*mode == 0, iclass 40, count 2 2006.286.05:31:54.22#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.05:31:54.22#ibcon#[27=AT08-04\r\n] 2006.286.05:31:54.22#ibcon#*before write, iclass 40, count 2 2006.286.05:31:54.22#ibcon#enter sib2, iclass 40, count 2 2006.286.05:31:54.22#ibcon#flushed, iclass 40, count 2 2006.286.05:31:54.22#ibcon#about to write, iclass 40, count 2 2006.286.05:31:54.22#ibcon#wrote, iclass 40, count 2 2006.286.05:31:54.22#ibcon#about to read 3, iclass 40, count 2 2006.286.05:31:54.25#ibcon#read 3, iclass 40, count 2 2006.286.05:31:54.25#ibcon#about to read 4, iclass 40, count 2 2006.286.05:31:54.25#ibcon#read 4, iclass 40, count 2 2006.286.05:31:54.25#ibcon#about to read 5, iclass 40, count 2 2006.286.05:31:54.25#ibcon#read 5, iclass 40, count 2 2006.286.05:31:54.25#ibcon#about to read 6, iclass 40, count 2 2006.286.05:31:54.25#ibcon#read 6, iclass 40, count 2 2006.286.05:31:54.25#ibcon#end of sib2, iclass 40, count 2 2006.286.05:31:54.25#ibcon#*after write, iclass 40, count 2 2006.286.05:31:54.25#ibcon#*before return 0, iclass 40, count 2 2006.286.05:31:54.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:31:54.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:31:54.25#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.05:31:54.25#ibcon#ireg 7 cls_cnt 0 2006.286.05:31:54.25#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:31:54.37#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:31:54.37#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:31:54.37#ibcon#enter wrdev, iclass 40, count 0 2006.286.05:31:54.37#ibcon#first serial, iclass 40, count 0 2006.286.05:31:54.37#ibcon#enter sib2, iclass 40, count 0 2006.286.05:31:54.37#ibcon#flushed, iclass 40, count 0 2006.286.05:31:54.37#ibcon#about to write, iclass 40, count 0 2006.286.05:31:54.37#ibcon#wrote, iclass 40, count 0 2006.286.05:31:54.37#ibcon#about to read 3, iclass 40, count 0 2006.286.05:31:54.39#ibcon#read 3, iclass 40, count 0 2006.286.05:31:54.39#ibcon#about to read 4, iclass 40, count 0 2006.286.05:31:54.39#ibcon#read 4, iclass 40, count 0 2006.286.05:31:54.39#ibcon#about to read 5, iclass 40, count 0 2006.286.05:31:54.39#ibcon#read 5, iclass 40, count 0 2006.286.05:31:54.39#ibcon#about to read 6, iclass 40, count 0 2006.286.05:31:54.39#ibcon#read 6, iclass 40, count 0 2006.286.05:31:54.39#ibcon#end of sib2, iclass 40, count 0 2006.286.05:31:54.39#ibcon#*mode == 0, iclass 40, count 0 2006.286.05:31:54.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.05:31:54.39#ibcon#[27=USB\r\n] 2006.286.05:31:54.39#ibcon#*before write, iclass 40, count 0 2006.286.05:31:54.39#ibcon#enter sib2, iclass 40, count 0 2006.286.05:31:54.39#ibcon#flushed, iclass 40, count 0 2006.286.05:31:54.39#ibcon#about to write, iclass 40, count 0 2006.286.05:31:54.39#ibcon#wrote, iclass 40, count 0 2006.286.05:31:54.39#ibcon#about to read 3, iclass 40, count 0 2006.286.05:31:54.42#ibcon#read 3, iclass 40, count 0 2006.286.05:31:54.42#ibcon#about to read 4, iclass 40, count 0 2006.286.05:31:54.42#ibcon#read 4, iclass 40, count 0 2006.286.05:31:54.42#ibcon#about to read 5, iclass 40, count 0 2006.286.05:31:54.42#ibcon#read 5, iclass 40, count 0 2006.286.05:31:54.42#ibcon#about to read 6, iclass 40, count 0 2006.286.05:31:54.42#ibcon#read 6, iclass 40, count 0 2006.286.05:31:54.42#ibcon#end of sib2, iclass 40, count 0 2006.286.05:31:54.42#ibcon#*after write, iclass 40, count 0 2006.286.05:31:54.42#ibcon#*before return 0, iclass 40, count 0 2006.286.05:31:54.42#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:31:54.42#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:31:54.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.05:31:54.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.05:31:54.42$vck44/vabw=wide 2006.286.05:31:54.42#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.05:31:54.42#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.05:31:54.42#ibcon#ireg 8 cls_cnt 0 2006.286.05:31:54.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:31:54.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:31:54.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:31:54.42#ibcon#enter wrdev, iclass 4, count 0 2006.286.05:31:54.42#ibcon#first serial, iclass 4, count 0 2006.286.05:31:54.42#ibcon#enter sib2, iclass 4, count 0 2006.286.05:31:54.42#ibcon#flushed, iclass 4, count 0 2006.286.05:31:54.42#ibcon#about to write, iclass 4, count 0 2006.286.05:31:54.42#ibcon#wrote, iclass 4, count 0 2006.286.05:31:54.42#ibcon#about to read 3, iclass 4, count 0 2006.286.05:31:54.44#ibcon#read 3, iclass 4, count 0 2006.286.05:31:54.44#ibcon#about to read 4, iclass 4, count 0 2006.286.05:31:54.44#ibcon#read 4, iclass 4, count 0 2006.286.05:31:54.44#ibcon#about to read 5, iclass 4, count 0 2006.286.05:31:54.44#ibcon#read 5, iclass 4, count 0 2006.286.05:31:54.44#ibcon#about to read 6, iclass 4, count 0 2006.286.05:31:54.44#ibcon#read 6, iclass 4, count 0 2006.286.05:31:54.44#ibcon#end of sib2, iclass 4, count 0 2006.286.05:31:54.44#ibcon#*mode == 0, iclass 4, count 0 2006.286.05:31:54.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.05:31:54.44#ibcon#[25=BW32\r\n] 2006.286.05:31:54.44#ibcon#*before write, iclass 4, count 0 2006.286.05:31:54.44#ibcon#enter sib2, iclass 4, count 0 2006.286.05:31:54.44#ibcon#flushed, iclass 4, count 0 2006.286.05:31:54.44#ibcon#about to write, iclass 4, count 0 2006.286.05:31:54.44#ibcon#wrote, iclass 4, count 0 2006.286.05:31:54.44#ibcon#about to read 3, iclass 4, count 0 2006.286.05:31:54.47#ibcon#read 3, iclass 4, count 0 2006.286.05:31:54.47#ibcon#about to read 4, iclass 4, count 0 2006.286.05:31:54.47#ibcon#read 4, iclass 4, count 0 2006.286.05:31:54.47#ibcon#about to read 5, iclass 4, count 0 2006.286.05:31:54.47#ibcon#read 5, iclass 4, count 0 2006.286.05:31:54.47#ibcon#about to read 6, iclass 4, count 0 2006.286.05:31:54.47#ibcon#read 6, iclass 4, count 0 2006.286.05:31:54.47#ibcon#end of sib2, iclass 4, count 0 2006.286.05:31:54.47#ibcon#*after write, iclass 4, count 0 2006.286.05:31:54.47#ibcon#*before return 0, iclass 4, count 0 2006.286.05:31:54.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:31:54.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:31:54.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.05:31:54.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.05:31:54.47$vck44/vbbw=wide 2006.286.05:31:54.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.286.05:31:54.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.286.05:31:54.47#ibcon#ireg 8 cls_cnt 0 2006.286.05:31:54.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.05:31:54.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.286.05:31:54.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.05:31:54.54#ibcon#enter wrdev, iclass 6, count 0 2006.286.05:31:54.54#ibcon#first serial, iclass 6, count 0 2006.286.05:31:54.54#ibcon#enter sib2, iclass 6, count 0 2006.286.05:31:54.54#ibcon#flushed, iclass 6, count 0 2006.286.05:31:54.54#ibcon#about to write, iclass 6, count 0 2006.286.05:31:54.54#ibcon#wrote, iclass 6, count 0 2006.286.05:31:54.54#ibcon#about to read 3, iclass 6, count 0 2006.286.05:31:54.56#ibcon#read 3, iclass 6, count 0 2006.286.05:31:54.56#ibcon#about to read 4, iclass 6, count 0 2006.286.05:31:54.56#ibcon#read 4, iclass 6, count 0 2006.286.05:31:54.56#ibcon#about to read 5, iclass 6, count 0 2006.286.05:31:54.56#ibcon#read 5, iclass 6, count 0 2006.286.05:31:54.56#ibcon#about to read 6, iclass 6, count 0 2006.286.05:31:54.56#ibcon#read 6, iclass 6, count 0 2006.286.05:31:54.56#ibcon#end of sib2, iclass 6, count 0 2006.286.05:31:54.56#ibcon#*mode == 0, iclass 6, count 0 2006.286.05:31:54.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.05:31:54.56#ibcon#[27=BW32\r\n] 2006.286.05:31:54.56#ibcon#*before write, iclass 6, count 0 2006.286.05:31:54.56#ibcon#enter sib2, iclass 6, count 0 2006.286.05:31:54.56#ibcon#flushed, iclass 6, count 0 2006.286.05:31:54.56#ibcon#about to write, iclass 6, count 0 2006.286.05:31:54.56#ibcon#wrote, iclass 6, count 0 2006.286.05:31:54.56#ibcon#about to read 3, iclass 6, count 0 2006.286.05:31:54.59#ibcon#read 3, iclass 6, count 0 2006.286.05:31:54.59#ibcon#about to read 4, iclass 6, count 0 2006.286.05:31:54.59#ibcon#read 4, iclass 6, count 0 2006.286.05:31:54.59#ibcon#about to read 5, iclass 6, count 0 2006.286.05:31:54.59#ibcon#read 5, iclass 6, count 0 2006.286.05:31:54.59#ibcon#about to read 6, iclass 6, count 0 2006.286.05:31:54.59#ibcon#read 6, iclass 6, count 0 2006.286.05:31:54.59#ibcon#end of sib2, iclass 6, count 0 2006.286.05:31:54.59#ibcon#*after write, iclass 6, count 0 2006.286.05:31:54.59#ibcon#*before return 0, iclass 6, count 0 2006.286.05:31:54.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.286.05:31:54.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.286.05:31:54.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.05:31:54.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.05:31:54.59$setupk4/ifdk4 2006.286.05:31:54.59$ifdk4/lo= 2006.286.05:31:54.59$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.05:31:54.59$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.05:31:54.59$ifdk4/patch= 2006.286.05:31:54.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.05:31:54.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.05:31:54.71$setupk4/!*+20s 2006.286.05:31:57.88#abcon#<5=/04 3.9 7.0 21.15 791015.1\r\n> 2006.286.05:31:57.90#abcon#{5=INTERFACE CLEAR} 2006.286.05:31:57.96#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:32:08.05#abcon#<5=/04 3.9 7.0 21.15 791015.1\r\n> 2006.286.05:32:08.07#abcon#{5=INTERFACE CLEAR} 2006.286.05:32:08.13#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:32:08.16$setupk4/"tpicd 2006.286.05:32:08.16$setupk4/echo=off 2006.286.05:32:08.16$setupk4/xlog=off 2006.286.05:32:08.16:!2006.286.05:36:29 2006.286.05:32:24.13#trakl#Source acquired 2006.286.05:32:24.13#flagr#flagr/antenna,acquired 2006.286.05:36:29.00:preob 2006.286.05:36:29.14/onsource/TRACKING 2006.286.05:36:29.14:!2006.286.05:36:39 2006.286.05:36:39.00:"tape 2006.286.05:36:39.00:"st=record 2006.286.05:36:39.00:data_valid=on 2006.286.05:36:39.00:midob 2006.286.05:36:39.14/onsource/TRACKING 2006.286.05:36:39.14/wx/21.02,1015.2,79 2006.286.05:36:39.28/cable/+6.4923E-03 2006.286.05:36:40.37/va/01,07,usb,yes,35,38 2006.286.05:36:40.37/va/02,06,usb,yes,35,35 2006.286.05:36:40.37/va/03,07,usb,yes,34,36 2006.286.05:36:40.37/va/04,06,usb,yes,36,38 2006.286.05:36:40.37/va/05,03,usb,yes,35,36 2006.286.05:36:40.37/va/06,04,usb,yes,32,31 2006.286.05:36:40.37/va/07,04,usb,yes,33,33 2006.286.05:36:40.37/va/08,03,usb,yes,33,40 2006.286.05:36:40.60/valo/01,524.99,yes,locked 2006.286.05:36:40.60/valo/02,534.99,yes,locked 2006.286.05:36:40.60/valo/03,564.99,yes,locked 2006.286.05:36:40.60/valo/04,624.99,yes,locked 2006.286.05:36:40.60/valo/05,734.99,yes,locked 2006.286.05:36:40.60/valo/06,814.99,yes,locked 2006.286.05:36:40.60/valo/07,864.99,yes,locked 2006.286.05:36:40.60/valo/08,884.99,yes,locked 2006.286.05:36:41.69/vb/01,04,usb,yes,32,29 2006.286.05:36:41.69/vb/02,05,usb,yes,30,30 2006.286.05:36:41.69/vb/03,04,usb,yes,31,34 2006.286.05:36:41.69/vb/04,05,usb,yes,31,30 2006.286.05:36:41.69/vb/05,04,usb,yes,28,30 2006.286.05:36:41.69/vb/06,03,usb,yes,40,35 2006.286.05:36:41.69/vb/07,04,usb,yes,32,32 2006.286.05:36:41.69/vb/08,04,usb,yes,29,33 2006.286.05:36:41.93/vblo/01,629.99,yes,locked 2006.286.05:36:41.93/vblo/02,634.99,yes,locked 2006.286.05:36:41.93/vblo/03,649.99,yes,locked 2006.286.05:36:41.93/vblo/04,679.99,yes,locked 2006.286.05:36:41.93/vblo/05,709.99,yes,locked 2006.286.05:36:41.93/vblo/06,719.99,yes,locked 2006.286.05:36:41.93/vblo/07,734.99,yes,locked 2006.286.05:36:41.93/vblo/08,744.99,yes,locked 2006.286.05:36:42.08/vabw/8 2006.286.05:36:42.23/vbbw/8 2006.286.05:36:42.32/xfe/off,on,12.0 2006.286.05:36:42.71/ifatt/23,28,28,28 2006.286.05:36:43.08/fmout-gps/S +2.42E-07 2006.286.05:36:43.10:!2006.286.05:38:19 2006.286.05:38:19.01:data_valid=off 2006.286.05:38:19.01:"et 2006.286.05:38:19.01:!+3s 2006.286.05:38:22.02:"tape 2006.286.05:38:22.02:postob 2006.286.05:38:22.11/cable/+6.4915E-03 2006.286.05:38:22.11/wx/20.96,1015.3,78 2006.286.05:38:23.08/fmout-gps/S +2.47E-07 2006.286.05:38:23.08:scan_name=286-0541,jd0610,140 2006.286.05:38:23.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.286.05:38:24.14#flagr#flagr/antenna,new-source 2006.286.05:38:24.14:checkk5 2006.286.05:38:24.65/chk_autoobs//k5ts1/ autoobs is running! 2006.286.05:38:25.02/chk_autoobs//k5ts2/ autoobs is running! 2006.286.05:38:25.44/chk_autoobs//k5ts3/ autoobs is running! 2006.286.05:38:25.86/chk_autoobs//k5ts4/ autoobs is running! 2006.286.05:38:26.22/chk_obsdata//k5ts1/T2860536??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.286.05:38:26.65/chk_obsdata//k5ts2/T2860536??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.286.05:38:27.02/chk_obsdata//k5ts3/T2860536??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.286.05:38:27.39/chk_obsdata//k5ts4/T2860536??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.286.05:38:28.25/k5log//k5ts1_log_newline 2006.286.05:38:29.05/k5log//k5ts2_log_newline 2006.286.05:38:29.91/k5log//k5ts3_log_newline 2006.286.05:38:30.75/k5log//k5ts4_log_newline 2006.286.05:38:30.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.05:38:30.77:setupk4=1 2006.286.05:38:30.77$setupk4/echo=on 2006.286.05:38:30.77$setupk4/pcalon 2006.286.05:38:30.77$pcalon/"no phase cal control is implemented here 2006.286.05:38:30.77$setupk4/"tpicd=stop 2006.286.05:38:30.77$setupk4/"rec=synch_on 2006.286.05:38:30.77$setupk4/"rec_mode=128 2006.286.05:38:30.77$setupk4/!* 2006.286.05:38:30.77$setupk4/recpk4 2006.286.05:38:30.77$recpk4/recpatch= 2006.286.05:38:30.77$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.05:38:30.77$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.05:38:30.77$setupk4/vck44 2006.286.05:38:30.77$vck44/valo=1,524.99 2006.286.05:38:30.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.05:38:30.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.05:38:30.77#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:30.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:38:30.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:38:30.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:38:30.77#ibcon#enter wrdev, iclass 25, count 0 2006.286.05:38:30.77#ibcon#first serial, iclass 25, count 0 2006.286.05:38:30.77#ibcon#enter sib2, iclass 25, count 0 2006.286.05:38:30.77#ibcon#flushed, iclass 25, count 0 2006.286.05:38:30.77#ibcon#about to write, iclass 25, count 0 2006.286.05:38:30.77#ibcon#wrote, iclass 25, count 0 2006.286.05:38:30.77#ibcon#about to read 3, iclass 25, count 0 2006.286.05:38:30.79#ibcon#read 3, iclass 25, count 0 2006.286.05:38:30.79#ibcon#about to read 4, iclass 25, count 0 2006.286.05:38:30.79#ibcon#read 4, iclass 25, count 0 2006.286.05:38:30.79#ibcon#about to read 5, iclass 25, count 0 2006.286.05:38:30.79#ibcon#read 5, iclass 25, count 0 2006.286.05:38:30.79#ibcon#about to read 6, iclass 25, count 0 2006.286.05:38:30.79#ibcon#read 6, iclass 25, count 0 2006.286.05:38:30.79#ibcon#end of sib2, iclass 25, count 0 2006.286.05:38:30.79#ibcon#*mode == 0, iclass 25, count 0 2006.286.05:38:30.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.05:38:30.79#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.05:38:30.79#ibcon#*before write, iclass 25, count 0 2006.286.05:38:30.79#ibcon#enter sib2, iclass 25, count 0 2006.286.05:38:30.79#ibcon#flushed, iclass 25, count 0 2006.286.05:38:30.79#ibcon#about to write, iclass 25, count 0 2006.286.05:38:30.79#ibcon#wrote, iclass 25, count 0 2006.286.05:38:30.79#ibcon#about to read 3, iclass 25, count 0 2006.286.05:38:30.84#ibcon#read 3, iclass 25, count 0 2006.286.05:38:30.84#ibcon#about to read 4, iclass 25, count 0 2006.286.05:38:30.84#ibcon#read 4, iclass 25, count 0 2006.286.05:38:30.84#ibcon#about to read 5, iclass 25, count 0 2006.286.05:38:30.84#ibcon#read 5, iclass 25, count 0 2006.286.05:38:30.84#ibcon#about to read 6, iclass 25, count 0 2006.286.05:38:30.84#ibcon#read 6, iclass 25, count 0 2006.286.05:38:30.84#ibcon#end of sib2, iclass 25, count 0 2006.286.05:38:30.84#ibcon#*after write, iclass 25, count 0 2006.286.05:38:30.84#ibcon#*before return 0, iclass 25, count 0 2006.286.05:38:30.84#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:38:30.84#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:38:30.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.05:38:30.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.05:38:30.84$vck44/va=1,7 2006.286.05:38:30.84#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.05:38:30.84#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.05:38:30.84#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:30.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:38:30.84#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:38:30.84#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:38:30.84#ibcon#enter wrdev, iclass 27, count 2 2006.286.05:38:30.84#ibcon#first serial, iclass 27, count 2 2006.286.05:38:30.84#ibcon#enter sib2, iclass 27, count 2 2006.286.05:38:30.84#ibcon#flushed, iclass 27, count 2 2006.286.05:38:30.84#ibcon#about to write, iclass 27, count 2 2006.286.05:38:30.84#ibcon#wrote, iclass 27, count 2 2006.286.05:38:30.84#ibcon#about to read 3, iclass 27, count 2 2006.286.05:38:30.86#ibcon#read 3, iclass 27, count 2 2006.286.05:38:30.86#ibcon#about to read 4, iclass 27, count 2 2006.286.05:38:30.86#ibcon#read 4, iclass 27, count 2 2006.286.05:38:30.86#ibcon#about to read 5, iclass 27, count 2 2006.286.05:38:30.86#ibcon#read 5, iclass 27, count 2 2006.286.05:38:30.86#ibcon#about to read 6, iclass 27, count 2 2006.286.05:38:30.86#ibcon#read 6, iclass 27, count 2 2006.286.05:38:30.86#ibcon#end of sib2, iclass 27, count 2 2006.286.05:38:30.86#ibcon#*mode == 0, iclass 27, count 2 2006.286.05:38:30.86#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.05:38:30.86#ibcon#[25=AT01-07\r\n] 2006.286.05:38:30.86#ibcon#*before write, iclass 27, count 2 2006.286.05:38:30.86#ibcon#enter sib2, iclass 27, count 2 2006.286.05:38:30.86#ibcon#flushed, iclass 27, count 2 2006.286.05:38:30.86#ibcon#about to write, iclass 27, count 2 2006.286.05:38:30.86#ibcon#wrote, iclass 27, count 2 2006.286.05:38:30.86#ibcon#about to read 3, iclass 27, count 2 2006.286.05:38:30.89#ibcon#read 3, iclass 27, count 2 2006.286.05:38:30.89#ibcon#about to read 4, iclass 27, count 2 2006.286.05:38:30.89#ibcon#read 4, iclass 27, count 2 2006.286.05:38:30.89#ibcon#about to read 5, iclass 27, count 2 2006.286.05:38:30.89#ibcon#read 5, iclass 27, count 2 2006.286.05:38:30.89#ibcon#about to read 6, iclass 27, count 2 2006.286.05:38:30.89#ibcon#read 6, iclass 27, count 2 2006.286.05:38:30.89#ibcon#end of sib2, iclass 27, count 2 2006.286.05:38:30.89#ibcon#*after write, iclass 27, count 2 2006.286.05:38:30.89#ibcon#*before return 0, iclass 27, count 2 2006.286.05:38:30.89#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:38:30.89#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:38:30.89#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.05:38:30.89#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:30.89#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:38:31.01#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:38:31.01#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:38:31.01#ibcon#enter wrdev, iclass 27, count 0 2006.286.05:38:31.01#ibcon#first serial, iclass 27, count 0 2006.286.05:38:31.01#ibcon#enter sib2, iclass 27, count 0 2006.286.05:38:31.01#ibcon#flushed, iclass 27, count 0 2006.286.05:38:31.01#ibcon#about to write, iclass 27, count 0 2006.286.05:38:31.01#ibcon#wrote, iclass 27, count 0 2006.286.05:38:31.01#ibcon#about to read 3, iclass 27, count 0 2006.286.05:38:31.03#ibcon#read 3, iclass 27, count 0 2006.286.05:38:31.03#ibcon#about to read 4, iclass 27, count 0 2006.286.05:38:31.03#ibcon#read 4, iclass 27, count 0 2006.286.05:38:31.03#ibcon#about to read 5, iclass 27, count 0 2006.286.05:38:31.03#ibcon#read 5, iclass 27, count 0 2006.286.05:38:31.03#ibcon#about to read 6, iclass 27, count 0 2006.286.05:38:31.03#ibcon#read 6, iclass 27, count 0 2006.286.05:38:31.03#ibcon#end of sib2, iclass 27, count 0 2006.286.05:38:31.03#ibcon#*mode == 0, iclass 27, count 0 2006.286.05:38:31.03#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.05:38:31.03#ibcon#[25=USB\r\n] 2006.286.05:38:31.03#ibcon#*before write, iclass 27, count 0 2006.286.05:38:31.03#ibcon#enter sib2, iclass 27, count 0 2006.286.05:38:31.03#ibcon#flushed, iclass 27, count 0 2006.286.05:38:31.03#ibcon#about to write, iclass 27, count 0 2006.286.05:38:31.03#ibcon#wrote, iclass 27, count 0 2006.286.05:38:31.03#ibcon#about to read 3, iclass 27, count 0 2006.286.05:38:31.06#ibcon#read 3, iclass 27, count 0 2006.286.05:38:31.06#ibcon#about to read 4, iclass 27, count 0 2006.286.05:38:31.06#ibcon#read 4, iclass 27, count 0 2006.286.05:38:31.06#ibcon#about to read 5, iclass 27, count 0 2006.286.05:38:31.06#ibcon#read 5, iclass 27, count 0 2006.286.05:38:31.06#ibcon#about to read 6, iclass 27, count 0 2006.286.05:38:31.06#ibcon#read 6, iclass 27, count 0 2006.286.05:38:31.06#ibcon#end of sib2, iclass 27, count 0 2006.286.05:38:31.06#ibcon#*after write, iclass 27, count 0 2006.286.05:38:31.06#ibcon#*before return 0, iclass 27, count 0 2006.286.05:38:31.06#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:38:31.06#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:38:31.06#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.05:38:31.06#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.05:38:31.06$vck44/valo=2,534.99 2006.286.05:38:31.06#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.05:38:31.06#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.05:38:31.06#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:31.06#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:38:31.06#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:38:31.06#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:38:31.06#ibcon#enter wrdev, iclass 29, count 0 2006.286.05:38:31.06#ibcon#first serial, iclass 29, count 0 2006.286.05:38:31.06#ibcon#enter sib2, iclass 29, count 0 2006.286.05:38:31.06#ibcon#flushed, iclass 29, count 0 2006.286.05:38:31.06#ibcon#about to write, iclass 29, count 0 2006.286.05:38:31.06#ibcon#wrote, iclass 29, count 0 2006.286.05:38:31.06#ibcon#about to read 3, iclass 29, count 0 2006.286.05:38:31.08#ibcon#read 3, iclass 29, count 0 2006.286.05:38:31.08#ibcon#about to read 4, iclass 29, count 0 2006.286.05:38:31.08#ibcon#read 4, iclass 29, count 0 2006.286.05:38:31.08#ibcon#about to read 5, iclass 29, count 0 2006.286.05:38:31.08#ibcon#read 5, iclass 29, count 0 2006.286.05:38:31.08#ibcon#about to read 6, iclass 29, count 0 2006.286.05:38:31.08#ibcon#read 6, iclass 29, count 0 2006.286.05:38:31.08#ibcon#end of sib2, iclass 29, count 0 2006.286.05:38:31.08#ibcon#*mode == 0, iclass 29, count 0 2006.286.05:38:31.08#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.05:38:31.08#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.05:38:31.08#ibcon#*before write, iclass 29, count 0 2006.286.05:38:31.08#ibcon#enter sib2, iclass 29, count 0 2006.286.05:38:31.08#ibcon#flushed, iclass 29, count 0 2006.286.05:38:31.08#ibcon#about to write, iclass 29, count 0 2006.286.05:38:31.08#ibcon#wrote, iclass 29, count 0 2006.286.05:38:31.08#ibcon#about to read 3, iclass 29, count 0 2006.286.05:38:31.12#ibcon#read 3, iclass 29, count 0 2006.286.05:38:31.12#ibcon#about to read 4, iclass 29, count 0 2006.286.05:38:31.12#ibcon#read 4, iclass 29, count 0 2006.286.05:38:31.12#ibcon#about to read 5, iclass 29, count 0 2006.286.05:38:31.12#ibcon#read 5, iclass 29, count 0 2006.286.05:38:31.12#ibcon#about to read 6, iclass 29, count 0 2006.286.05:38:31.12#ibcon#read 6, iclass 29, count 0 2006.286.05:38:31.12#ibcon#end of sib2, iclass 29, count 0 2006.286.05:38:31.12#ibcon#*after write, iclass 29, count 0 2006.286.05:38:31.12#ibcon#*before return 0, iclass 29, count 0 2006.286.05:38:31.12#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:38:31.12#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:38:31.12#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.05:38:31.12#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.05:38:31.12$vck44/va=2,6 2006.286.05:38:31.12#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.05:38:31.12#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.05:38:31.12#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:31.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:38:31.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:38:31.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:38:31.18#ibcon#enter wrdev, iclass 31, count 2 2006.286.05:38:31.18#ibcon#first serial, iclass 31, count 2 2006.286.05:38:31.18#ibcon#enter sib2, iclass 31, count 2 2006.286.05:38:31.18#ibcon#flushed, iclass 31, count 2 2006.286.05:38:31.18#ibcon#about to write, iclass 31, count 2 2006.286.05:38:31.18#ibcon#wrote, iclass 31, count 2 2006.286.05:38:31.18#ibcon#about to read 3, iclass 31, count 2 2006.286.05:38:31.20#ibcon#read 3, iclass 31, count 2 2006.286.05:38:31.20#ibcon#about to read 4, iclass 31, count 2 2006.286.05:38:31.20#ibcon#read 4, iclass 31, count 2 2006.286.05:38:31.20#ibcon#about to read 5, iclass 31, count 2 2006.286.05:38:31.20#ibcon#read 5, iclass 31, count 2 2006.286.05:38:31.20#ibcon#about to read 6, iclass 31, count 2 2006.286.05:38:31.20#ibcon#read 6, iclass 31, count 2 2006.286.05:38:31.20#ibcon#end of sib2, iclass 31, count 2 2006.286.05:38:31.20#ibcon#*mode == 0, iclass 31, count 2 2006.286.05:38:31.20#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.05:38:31.20#ibcon#[25=AT02-06\r\n] 2006.286.05:38:31.20#ibcon#*before write, iclass 31, count 2 2006.286.05:38:31.20#ibcon#enter sib2, iclass 31, count 2 2006.286.05:38:31.20#ibcon#flushed, iclass 31, count 2 2006.286.05:38:31.20#ibcon#about to write, iclass 31, count 2 2006.286.05:38:31.20#ibcon#wrote, iclass 31, count 2 2006.286.05:38:31.20#ibcon#about to read 3, iclass 31, count 2 2006.286.05:38:31.23#ibcon#read 3, iclass 31, count 2 2006.286.05:38:31.23#ibcon#about to read 4, iclass 31, count 2 2006.286.05:38:31.23#ibcon#read 4, iclass 31, count 2 2006.286.05:38:31.23#ibcon#about to read 5, iclass 31, count 2 2006.286.05:38:31.23#ibcon#read 5, iclass 31, count 2 2006.286.05:38:31.23#ibcon#about to read 6, iclass 31, count 2 2006.286.05:38:31.23#ibcon#read 6, iclass 31, count 2 2006.286.05:38:31.23#ibcon#end of sib2, iclass 31, count 2 2006.286.05:38:31.23#ibcon#*after write, iclass 31, count 2 2006.286.05:38:31.23#ibcon#*before return 0, iclass 31, count 2 2006.286.05:38:31.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:38:31.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:38:31.23#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.05:38:31.23#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:31.23#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:38:31.35#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:38:31.35#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:38:31.35#ibcon#enter wrdev, iclass 31, count 0 2006.286.05:38:31.35#ibcon#first serial, iclass 31, count 0 2006.286.05:38:31.35#ibcon#enter sib2, iclass 31, count 0 2006.286.05:38:31.35#ibcon#flushed, iclass 31, count 0 2006.286.05:38:31.35#ibcon#about to write, iclass 31, count 0 2006.286.05:38:31.35#ibcon#wrote, iclass 31, count 0 2006.286.05:38:31.35#ibcon#about to read 3, iclass 31, count 0 2006.286.05:38:31.37#ibcon#read 3, iclass 31, count 0 2006.286.05:38:31.37#ibcon#about to read 4, iclass 31, count 0 2006.286.05:38:31.37#ibcon#read 4, iclass 31, count 0 2006.286.05:38:31.37#ibcon#about to read 5, iclass 31, count 0 2006.286.05:38:31.37#ibcon#read 5, iclass 31, count 0 2006.286.05:38:31.37#ibcon#about to read 6, iclass 31, count 0 2006.286.05:38:31.37#ibcon#read 6, iclass 31, count 0 2006.286.05:38:31.37#ibcon#end of sib2, iclass 31, count 0 2006.286.05:38:31.37#ibcon#*mode == 0, iclass 31, count 0 2006.286.05:38:31.37#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.05:38:31.37#ibcon#[25=USB\r\n] 2006.286.05:38:31.37#ibcon#*before write, iclass 31, count 0 2006.286.05:38:31.37#ibcon#enter sib2, iclass 31, count 0 2006.286.05:38:31.37#ibcon#flushed, iclass 31, count 0 2006.286.05:38:31.37#ibcon#about to write, iclass 31, count 0 2006.286.05:38:31.37#ibcon#wrote, iclass 31, count 0 2006.286.05:38:31.37#ibcon#about to read 3, iclass 31, count 0 2006.286.05:38:31.40#ibcon#read 3, iclass 31, count 0 2006.286.05:38:31.40#ibcon#about to read 4, iclass 31, count 0 2006.286.05:38:31.40#ibcon#read 4, iclass 31, count 0 2006.286.05:38:31.40#ibcon#about to read 5, iclass 31, count 0 2006.286.05:38:31.40#ibcon#read 5, iclass 31, count 0 2006.286.05:38:31.40#ibcon#about to read 6, iclass 31, count 0 2006.286.05:38:31.40#ibcon#read 6, iclass 31, count 0 2006.286.05:38:31.40#ibcon#end of sib2, iclass 31, count 0 2006.286.05:38:31.40#ibcon#*after write, iclass 31, count 0 2006.286.05:38:31.40#ibcon#*before return 0, iclass 31, count 0 2006.286.05:38:31.40#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:38:31.40#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:38:31.40#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.05:38:31.40#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.05:38:31.40$vck44/valo=3,564.99 2006.286.05:38:31.40#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.05:38:31.40#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.05:38:31.40#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:31.40#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:38:31.40#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:38:31.40#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:38:31.40#ibcon#enter wrdev, iclass 33, count 0 2006.286.05:38:31.40#ibcon#first serial, iclass 33, count 0 2006.286.05:38:31.40#ibcon#enter sib2, iclass 33, count 0 2006.286.05:38:31.40#ibcon#flushed, iclass 33, count 0 2006.286.05:38:31.40#ibcon#about to write, iclass 33, count 0 2006.286.05:38:31.40#ibcon#wrote, iclass 33, count 0 2006.286.05:38:31.40#ibcon#about to read 3, iclass 33, count 0 2006.286.05:38:31.42#ibcon#read 3, iclass 33, count 0 2006.286.05:38:31.42#ibcon#about to read 4, iclass 33, count 0 2006.286.05:38:31.42#ibcon#read 4, iclass 33, count 0 2006.286.05:38:31.42#ibcon#about to read 5, iclass 33, count 0 2006.286.05:38:31.42#ibcon#read 5, iclass 33, count 0 2006.286.05:38:31.42#ibcon#about to read 6, iclass 33, count 0 2006.286.05:38:31.42#ibcon#read 6, iclass 33, count 0 2006.286.05:38:31.42#ibcon#end of sib2, iclass 33, count 0 2006.286.05:38:31.42#ibcon#*mode == 0, iclass 33, count 0 2006.286.05:38:31.42#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.05:38:31.42#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.05:38:31.42#ibcon#*before write, iclass 33, count 0 2006.286.05:38:31.42#ibcon#enter sib2, iclass 33, count 0 2006.286.05:38:31.42#ibcon#flushed, iclass 33, count 0 2006.286.05:38:31.42#ibcon#about to write, iclass 33, count 0 2006.286.05:38:31.42#ibcon#wrote, iclass 33, count 0 2006.286.05:38:31.42#ibcon#about to read 3, iclass 33, count 0 2006.286.05:38:31.46#ibcon#read 3, iclass 33, count 0 2006.286.05:38:31.46#ibcon#about to read 4, iclass 33, count 0 2006.286.05:38:31.46#ibcon#read 4, iclass 33, count 0 2006.286.05:38:31.46#ibcon#about to read 5, iclass 33, count 0 2006.286.05:38:31.46#ibcon#read 5, iclass 33, count 0 2006.286.05:38:31.46#ibcon#about to read 6, iclass 33, count 0 2006.286.05:38:31.46#ibcon#read 6, iclass 33, count 0 2006.286.05:38:31.46#ibcon#end of sib2, iclass 33, count 0 2006.286.05:38:31.46#ibcon#*after write, iclass 33, count 0 2006.286.05:38:31.46#ibcon#*before return 0, iclass 33, count 0 2006.286.05:38:31.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:38:31.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:38:31.46#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.05:38:31.46#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.05:38:31.46$vck44/va=3,7 2006.286.05:38:31.46#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.05:38:31.46#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.05:38:31.46#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:31.46#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:38:31.52#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:38:31.52#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:38:31.52#ibcon#enter wrdev, iclass 35, count 2 2006.286.05:38:31.52#ibcon#first serial, iclass 35, count 2 2006.286.05:38:31.52#ibcon#enter sib2, iclass 35, count 2 2006.286.05:38:31.52#ibcon#flushed, iclass 35, count 2 2006.286.05:38:31.52#ibcon#about to write, iclass 35, count 2 2006.286.05:38:31.52#ibcon#wrote, iclass 35, count 2 2006.286.05:38:31.52#ibcon#about to read 3, iclass 35, count 2 2006.286.05:38:31.54#ibcon#read 3, iclass 35, count 2 2006.286.05:38:32.32#ibcon#about to read 4, iclass 35, count 2 2006.286.05:38:32.32#ibcon#read 4, iclass 35, count 2 2006.286.05:38:32.32#ibcon#about to read 5, iclass 35, count 2 2006.286.05:38:32.32#ibcon#read 5, iclass 35, count 2 2006.286.05:38:32.32#ibcon#about to read 6, iclass 35, count 2 2006.286.05:38:32.32#ibcon#read 6, iclass 35, count 2 2006.286.05:38:32.32#ibcon#end of sib2, iclass 35, count 2 2006.286.05:38:32.32#ibcon#*mode == 0, iclass 35, count 2 2006.286.05:38:32.32#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.05:38:32.32#ibcon#[25=AT03-07\r\n] 2006.286.05:38:32.32#ibcon#*before write, iclass 35, count 2 2006.286.05:38:32.32#ibcon#enter sib2, iclass 35, count 2 2006.286.05:38:32.32#ibcon#flushed, iclass 35, count 2 2006.286.05:38:32.32#ibcon#about to write, iclass 35, count 2 2006.286.05:38:32.32#ibcon#wrote, iclass 35, count 2 2006.286.05:38:32.32#ibcon#about to read 3, iclass 35, count 2 2006.286.05:38:32.36#ibcon#read 3, iclass 35, count 2 2006.286.05:38:32.36#ibcon#about to read 4, iclass 35, count 2 2006.286.05:38:32.36#ibcon#read 4, iclass 35, count 2 2006.286.05:38:32.36#ibcon#about to read 5, iclass 35, count 2 2006.286.05:38:32.36#ibcon#read 5, iclass 35, count 2 2006.286.05:38:32.36#ibcon#about to read 6, iclass 35, count 2 2006.286.05:38:32.36#ibcon#read 6, iclass 35, count 2 2006.286.05:38:32.36#ibcon#end of sib2, iclass 35, count 2 2006.286.05:38:32.36#ibcon#*after write, iclass 35, count 2 2006.286.05:38:32.36#ibcon#*before return 0, iclass 35, count 2 2006.286.05:38:32.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:38:32.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:38:32.36#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.05:38:32.36#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:32.36#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:38:32.48#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:38:32.48#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:38:32.48#ibcon#enter wrdev, iclass 35, count 0 2006.286.05:38:32.48#ibcon#first serial, iclass 35, count 0 2006.286.05:38:32.48#ibcon#enter sib2, iclass 35, count 0 2006.286.05:38:32.48#ibcon#flushed, iclass 35, count 0 2006.286.05:38:32.48#ibcon#about to write, iclass 35, count 0 2006.286.05:38:32.48#ibcon#wrote, iclass 35, count 0 2006.286.05:38:32.48#ibcon#about to read 3, iclass 35, count 0 2006.286.05:38:32.50#ibcon#read 3, iclass 35, count 0 2006.286.05:38:32.50#ibcon#about to read 4, iclass 35, count 0 2006.286.05:38:32.50#ibcon#read 4, iclass 35, count 0 2006.286.05:38:32.50#ibcon#about to read 5, iclass 35, count 0 2006.286.05:38:32.50#ibcon#read 5, iclass 35, count 0 2006.286.05:38:32.50#ibcon#about to read 6, iclass 35, count 0 2006.286.05:38:32.50#ibcon#read 6, iclass 35, count 0 2006.286.05:38:32.50#ibcon#end of sib2, iclass 35, count 0 2006.286.05:38:32.50#ibcon#*mode == 0, iclass 35, count 0 2006.286.05:38:32.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.05:38:32.50#ibcon#[25=USB\r\n] 2006.286.05:38:32.50#ibcon#*before write, iclass 35, count 0 2006.286.05:38:32.50#ibcon#enter sib2, iclass 35, count 0 2006.286.05:38:32.50#ibcon#flushed, iclass 35, count 0 2006.286.05:38:32.50#ibcon#about to write, iclass 35, count 0 2006.286.05:38:32.50#ibcon#wrote, iclass 35, count 0 2006.286.05:38:32.50#ibcon#about to read 3, iclass 35, count 0 2006.286.05:38:32.53#ibcon#read 3, iclass 35, count 0 2006.286.05:38:32.53#ibcon#about to read 4, iclass 35, count 0 2006.286.05:38:32.53#ibcon#read 4, iclass 35, count 0 2006.286.05:38:32.53#ibcon#about to read 5, iclass 35, count 0 2006.286.05:38:32.53#ibcon#read 5, iclass 35, count 0 2006.286.05:38:32.53#ibcon#about to read 6, iclass 35, count 0 2006.286.05:38:32.53#ibcon#read 6, iclass 35, count 0 2006.286.05:38:32.53#ibcon#end of sib2, iclass 35, count 0 2006.286.05:38:32.53#ibcon#*after write, iclass 35, count 0 2006.286.05:38:32.53#ibcon#*before return 0, iclass 35, count 0 2006.286.05:38:32.53#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:38:32.53#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:38:32.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.05:38:32.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.05:38:32.53$vck44/valo=4,624.99 2006.286.05:38:32.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.05:38:32.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.05:38:32.53#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:32.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:38:32.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:38:32.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:38:32.53#ibcon#enter wrdev, iclass 37, count 0 2006.286.05:38:32.53#ibcon#first serial, iclass 37, count 0 2006.286.05:38:32.53#ibcon#enter sib2, iclass 37, count 0 2006.286.05:38:32.53#ibcon#flushed, iclass 37, count 0 2006.286.05:38:32.53#ibcon#about to write, iclass 37, count 0 2006.286.05:38:32.53#ibcon#wrote, iclass 37, count 0 2006.286.05:38:32.53#ibcon#about to read 3, iclass 37, count 0 2006.286.05:38:32.55#ibcon#read 3, iclass 37, count 0 2006.286.05:38:32.55#ibcon#about to read 4, iclass 37, count 0 2006.286.05:38:32.55#ibcon#read 4, iclass 37, count 0 2006.286.05:38:32.55#ibcon#about to read 5, iclass 37, count 0 2006.286.05:38:32.55#ibcon#read 5, iclass 37, count 0 2006.286.05:38:32.55#ibcon#about to read 6, iclass 37, count 0 2006.286.05:38:32.55#ibcon#read 6, iclass 37, count 0 2006.286.05:38:32.55#ibcon#end of sib2, iclass 37, count 0 2006.286.05:38:32.55#ibcon#*mode == 0, iclass 37, count 0 2006.286.05:38:32.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.05:38:32.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.05:38:32.55#ibcon#*before write, iclass 37, count 0 2006.286.05:38:32.55#ibcon#enter sib2, iclass 37, count 0 2006.286.05:38:32.55#ibcon#flushed, iclass 37, count 0 2006.286.05:38:32.55#ibcon#about to write, iclass 37, count 0 2006.286.05:38:32.55#ibcon#wrote, iclass 37, count 0 2006.286.05:38:32.55#ibcon#about to read 3, iclass 37, count 0 2006.286.05:38:32.59#ibcon#read 3, iclass 37, count 0 2006.286.05:38:32.59#ibcon#about to read 4, iclass 37, count 0 2006.286.05:38:32.59#ibcon#read 4, iclass 37, count 0 2006.286.05:38:32.59#ibcon#about to read 5, iclass 37, count 0 2006.286.05:38:32.59#ibcon#read 5, iclass 37, count 0 2006.286.05:38:32.59#ibcon#about to read 6, iclass 37, count 0 2006.286.05:38:32.59#ibcon#read 6, iclass 37, count 0 2006.286.05:38:32.59#ibcon#end of sib2, iclass 37, count 0 2006.286.05:38:32.59#ibcon#*after write, iclass 37, count 0 2006.286.05:38:32.59#ibcon#*before return 0, iclass 37, count 0 2006.286.05:38:32.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:38:32.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:38:32.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.05:38:32.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.05:38:32.59$vck44/va=4,6 2006.286.05:38:32.59#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.05:38:32.59#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.05:38:32.59#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:32.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:38:32.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:38:32.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:38:32.65#ibcon#enter wrdev, iclass 39, count 2 2006.286.05:38:32.65#ibcon#first serial, iclass 39, count 2 2006.286.05:38:32.65#ibcon#enter sib2, iclass 39, count 2 2006.286.05:38:32.65#ibcon#flushed, iclass 39, count 2 2006.286.05:38:32.65#ibcon#about to write, iclass 39, count 2 2006.286.05:38:32.65#ibcon#wrote, iclass 39, count 2 2006.286.05:38:32.65#ibcon#about to read 3, iclass 39, count 2 2006.286.05:38:32.67#ibcon#read 3, iclass 39, count 2 2006.286.05:38:32.67#ibcon#about to read 4, iclass 39, count 2 2006.286.05:38:32.67#ibcon#read 4, iclass 39, count 2 2006.286.05:38:32.67#ibcon#about to read 5, iclass 39, count 2 2006.286.05:38:32.67#ibcon#read 5, iclass 39, count 2 2006.286.05:38:32.67#ibcon#about to read 6, iclass 39, count 2 2006.286.05:38:32.67#ibcon#read 6, iclass 39, count 2 2006.286.05:38:32.67#ibcon#end of sib2, iclass 39, count 2 2006.286.05:38:32.67#ibcon#*mode == 0, iclass 39, count 2 2006.286.05:38:32.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.05:38:32.67#ibcon#[25=AT04-06\r\n] 2006.286.05:38:32.67#ibcon#*before write, iclass 39, count 2 2006.286.05:38:32.67#ibcon#enter sib2, iclass 39, count 2 2006.286.05:38:32.67#ibcon#flushed, iclass 39, count 2 2006.286.05:38:32.67#ibcon#about to write, iclass 39, count 2 2006.286.05:38:32.67#ibcon#wrote, iclass 39, count 2 2006.286.05:38:32.67#ibcon#about to read 3, iclass 39, count 2 2006.286.05:38:32.70#ibcon#read 3, iclass 39, count 2 2006.286.05:38:32.91#ibcon#about to read 4, iclass 39, count 2 2006.286.05:38:32.91#ibcon#read 4, iclass 39, count 2 2006.286.05:38:32.91#ibcon#about to read 5, iclass 39, count 2 2006.286.05:38:32.91#ibcon#read 5, iclass 39, count 2 2006.286.05:38:32.91#ibcon#about to read 6, iclass 39, count 2 2006.286.05:38:32.91#ibcon#read 6, iclass 39, count 2 2006.286.05:38:32.91#ibcon#end of sib2, iclass 39, count 2 2006.286.05:38:32.91#ibcon#*after write, iclass 39, count 2 2006.286.05:38:32.91#ibcon#*before return 0, iclass 39, count 2 2006.286.05:38:32.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:38:32.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:38:32.91#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.05:38:32.91#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:32.91#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:38:33.03#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:38:33.03#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:38:33.03#ibcon#enter wrdev, iclass 39, count 0 2006.286.05:38:33.03#ibcon#first serial, iclass 39, count 0 2006.286.05:38:33.03#ibcon#enter sib2, iclass 39, count 0 2006.286.05:38:33.03#ibcon#flushed, iclass 39, count 0 2006.286.05:38:33.03#ibcon#about to write, iclass 39, count 0 2006.286.05:38:33.03#ibcon#wrote, iclass 39, count 0 2006.286.05:38:33.03#ibcon#about to read 3, iclass 39, count 0 2006.286.05:38:33.05#ibcon#read 3, iclass 39, count 0 2006.286.05:38:33.05#ibcon#about to read 4, iclass 39, count 0 2006.286.05:38:33.05#ibcon#read 4, iclass 39, count 0 2006.286.05:38:33.05#ibcon#about to read 5, iclass 39, count 0 2006.286.05:38:33.05#ibcon#read 5, iclass 39, count 0 2006.286.05:38:33.05#ibcon#about to read 6, iclass 39, count 0 2006.286.05:38:33.05#ibcon#read 6, iclass 39, count 0 2006.286.05:38:33.05#ibcon#end of sib2, iclass 39, count 0 2006.286.05:38:33.05#ibcon#*mode == 0, iclass 39, count 0 2006.286.05:38:33.05#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.05:38:33.05#ibcon#[25=USB\r\n] 2006.286.05:38:33.05#ibcon#*before write, iclass 39, count 0 2006.286.05:38:33.05#ibcon#enter sib2, iclass 39, count 0 2006.286.05:38:33.05#ibcon#flushed, iclass 39, count 0 2006.286.05:38:33.05#ibcon#about to write, iclass 39, count 0 2006.286.05:38:33.05#ibcon#wrote, iclass 39, count 0 2006.286.05:38:33.05#ibcon#about to read 3, iclass 39, count 0 2006.286.05:38:33.08#ibcon#read 3, iclass 39, count 0 2006.286.05:38:33.08#ibcon#about to read 4, iclass 39, count 0 2006.286.05:38:33.08#ibcon#read 4, iclass 39, count 0 2006.286.05:38:33.08#ibcon#about to read 5, iclass 39, count 0 2006.286.05:38:33.08#ibcon#read 5, iclass 39, count 0 2006.286.05:38:33.08#ibcon#about to read 6, iclass 39, count 0 2006.286.05:38:33.08#ibcon#read 6, iclass 39, count 0 2006.286.05:38:33.08#ibcon#end of sib2, iclass 39, count 0 2006.286.05:38:33.08#ibcon#*after write, iclass 39, count 0 2006.286.05:38:33.08#ibcon#*before return 0, iclass 39, count 0 2006.286.05:38:33.08#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:38:33.08#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:38:33.08#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.05:38:33.08#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.05:38:33.08$vck44/valo=5,734.99 2006.286.05:38:33.08#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.05:38:33.08#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.05:38:33.08#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:33.08#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:38:33.08#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:38:33.08#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:38:33.08#ibcon#enter wrdev, iclass 3, count 0 2006.286.05:38:33.08#ibcon#first serial, iclass 3, count 0 2006.286.05:38:33.08#ibcon#enter sib2, iclass 3, count 0 2006.286.05:38:33.08#ibcon#flushed, iclass 3, count 0 2006.286.05:38:33.08#ibcon#about to write, iclass 3, count 0 2006.286.05:38:33.08#ibcon#wrote, iclass 3, count 0 2006.286.05:38:33.08#ibcon#about to read 3, iclass 3, count 0 2006.286.05:38:33.10#ibcon#read 3, iclass 3, count 0 2006.286.05:38:33.10#ibcon#about to read 4, iclass 3, count 0 2006.286.05:38:33.10#ibcon#read 4, iclass 3, count 0 2006.286.05:38:33.10#ibcon#about to read 5, iclass 3, count 0 2006.286.05:38:33.10#ibcon#read 5, iclass 3, count 0 2006.286.05:38:33.10#ibcon#about to read 6, iclass 3, count 0 2006.286.05:38:33.10#ibcon#read 6, iclass 3, count 0 2006.286.05:38:33.10#ibcon#end of sib2, iclass 3, count 0 2006.286.05:38:33.10#ibcon#*mode == 0, iclass 3, count 0 2006.286.05:38:33.10#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.05:38:33.10#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.05:38:33.10#ibcon#*before write, iclass 3, count 0 2006.286.05:38:33.10#ibcon#enter sib2, iclass 3, count 0 2006.286.05:38:33.10#ibcon#flushed, iclass 3, count 0 2006.286.05:38:33.10#ibcon#about to write, iclass 3, count 0 2006.286.05:38:33.10#ibcon#wrote, iclass 3, count 0 2006.286.05:38:33.10#ibcon#about to read 3, iclass 3, count 0 2006.286.05:38:33.14#ibcon#read 3, iclass 3, count 0 2006.286.05:38:33.14#ibcon#about to read 4, iclass 3, count 0 2006.286.05:38:33.14#ibcon#read 4, iclass 3, count 0 2006.286.05:38:33.14#ibcon#about to read 5, iclass 3, count 0 2006.286.05:38:33.14#ibcon#read 5, iclass 3, count 0 2006.286.05:38:33.14#ibcon#about to read 6, iclass 3, count 0 2006.286.05:38:33.14#ibcon#read 6, iclass 3, count 0 2006.286.05:38:33.14#ibcon#end of sib2, iclass 3, count 0 2006.286.05:38:33.14#ibcon#*after write, iclass 3, count 0 2006.286.05:38:33.14#ibcon#*before return 0, iclass 3, count 0 2006.286.05:38:33.14#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:38:33.14#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:38:33.14#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.05:38:33.14#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.05:38:33.14$vck44/va=5,3 2006.286.05:38:33.14#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.05:38:33.14#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.05:38:33.14#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:33.14#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:38:33.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:38:33.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:38:33.20#ibcon#enter wrdev, iclass 5, count 2 2006.286.05:38:33.20#ibcon#first serial, iclass 5, count 2 2006.286.05:38:33.20#ibcon#enter sib2, iclass 5, count 2 2006.286.05:38:33.20#ibcon#flushed, iclass 5, count 2 2006.286.05:38:33.20#ibcon#about to write, iclass 5, count 2 2006.286.05:38:33.20#ibcon#wrote, iclass 5, count 2 2006.286.05:38:33.20#ibcon#about to read 3, iclass 5, count 2 2006.286.05:38:33.22#ibcon#read 3, iclass 5, count 2 2006.286.05:38:33.22#ibcon#about to read 4, iclass 5, count 2 2006.286.05:38:33.22#ibcon#read 4, iclass 5, count 2 2006.286.05:38:33.22#ibcon#about to read 5, iclass 5, count 2 2006.286.05:38:33.22#ibcon#read 5, iclass 5, count 2 2006.286.05:38:33.22#ibcon#about to read 6, iclass 5, count 2 2006.286.05:38:33.22#ibcon#read 6, iclass 5, count 2 2006.286.05:38:33.22#ibcon#end of sib2, iclass 5, count 2 2006.286.05:38:33.22#ibcon#*mode == 0, iclass 5, count 2 2006.286.05:38:33.22#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.05:38:33.22#ibcon#[25=AT05-03\r\n] 2006.286.05:38:33.22#ibcon#*before write, iclass 5, count 2 2006.286.05:38:33.22#ibcon#enter sib2, iclass 5, count 2 2006.286.05:38:33.22#ibcon#flushed, iclass 5, count 2 2006.286.05:38:33.22#ibcon#about to write, iclass 5, count 2 2006.286.05:38:33.22#ibcon#wrote, iclass 5, count 2 2006.286.05:38:33.22#ibcon#about to read 3, iclass 5, count 2 2006.286.05:38:33.25#ibcon#read 3, iclass 5, count 2 2006.286.05:38:33.25#ibcon#about to read 4, iclass 5, count 2 2006.286.05:38:33.25#ibcon#read 4, iclass 5, count 2 2006.286.05:38:33.25#ibcon#about to read 5, iclass 5, count 2 2006.286.05:38:33.25#ibcon#read 5, iclass 5, count 2 2006.286.05:38:33.25#ibcon#about to read 6, iclass 5, count 2 2006.286.05:38:33.25#ibcon#read 6, iclass 5, count 2 2006.286.05:38:33.25#ibcon#end of sib2, iclass 5, count 2 2006.286.05:38:33.25#ibcon#*after write, iclass 5, count 2 2006.286.05:38:33.25#ibcon#*before return 0, iclass 5, count 2 2006.286.05:38:33.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:38:33.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:38:33.25#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.05:38:33.25#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:33.25#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:38:33.37#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:38:33.37#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:38:33.37#ibcon#enter wrdev, iclass 5, count 0 2006.286.05:38:33.37#ibcon#first serial, iclass 5, count 0 2006.286.05:38:33.37#ibcon#enter sib2, iclass 5, count 0 2006.286.05:38:33.37#ibcon#flushed, iclass 5, count 0 2006.286.05:38:33.37#ibcon#about to write, iclass 5, count 0 2006.286.05:38:33.37#ibcon#wrote, iclass 5, count 0 2006.286.05:38:33.37#ibcon#about to read 3, iclass 5, count 0 2006.286.05:38:33.39#ibcon#read 3, iclass 5, count 0 2006.286.05:38:33.39#ibcon#about to read 4, iclass 5, count 0 2006.286.05:38:33.39#ibcon#read 4, iclass 5, count 0 2006.286.05:38:33.39#ibcon#about to read 5, iclass 5, count 0 2006.286.05:38:33.39#ibcon#read 5, iclass 5, count 0 2006.286.05:38:33.39#ibcon#about to read 6, iclass 5, count 0 2006.286.05:38:33.39#ibcon#read 6, iclass 5, count 0 2006.286.05:38:33.39#ibcon#end of sib2, iclass 5, count 0 2006.286.05:38:33.39#ibcon#*mode == 0, iclass 5, count 0 2006.286.05:38:33.39#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.05:38:33.39#ibcon#[25=USB\r\n] 2006.286.05:38:33.39#ibcon#*before write, iclass 5, count 0 2006.286.05:38:33.39#ibcon#enter sib2, iclass 5, count 0 2006.286.05:38:33.39#ibcon#flushed, iclass 5, count 0 2006.286.05:38:33.39#ibcon#about to write, iclass 5, count 0 2006.286.05:38:33.39#ibcon#wrote, iclass 5, count 0 2006.286.05:38:33.39#ibcon#about to read 3, iclass 5, count 0 2006.286.05:38:33.42#ibcon#read 3, iclass 5, count 0 2006.286.05:38:33.42#ibcon#about to read 4, iclass 5, count 0 2006.286.05:38:33.42#ibcon#read 4, iclass 5, count 0 2006.286.05:38:33.42#ibcon#about to read 5, iclass 5, count 0 2006.286.05:38:33.42#ibcon#read 5, iclass 5, count 0 2006.286.05:38:33.42#ibcon#about to read 6, iclass 5, count 0 2006.286.05:38:33.42#ibcon#read 6, iclass 5, count 0 2006.286.05:38:33.42#ibcon#end of sib2, iclass 5, count 0 2006.286.05:38:33.42#ibcon#*after write, iclass 5, count 0 2006.286.05:38:33.42#ibcon#*before return 0, iclass 5, count 0 2006.286.05:38:33.42#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:38:33.42#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:38:33.42#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.05:38:33.42#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.05:38:33.42$vck44/valo=6,814.99 2006.286.05:38:33.42#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.05:38:33.42#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.05:38:33.42#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:33.42#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:38:33.42#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:38:33.42#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:38:33.42#ibcon#enter wrdev, iclass 7, count 0 2006.286.05:38:33.42#ibcon#first serial, iclass 7, count 0 2006.286.05:38:33.42#ibcon#enter sib2, iclass 7, count 0 2006.286.05:38:33.42#ibcon#flushed, iclass 7, count 0 2006.286.05:38:33.42#ibcon#about to write, iclass 7, count 0 2006.286.05:38:33.42#ibcon#wrote, iclass 7, count 0 2006.286.05:38:33.42#ibcon#about to read 3, iclass 7, count 0 2006.286.05:38:33.44#ibcon#read 3, iclass 7, count 0 2006.286.05:38:33.44#ibcon#about to read 4, iclass 7, count 0 2006.286.05:38:33.44#ibcon#read 4, iclass 7, count 0 2006.286.05:38:33.44#ibcon#about to read 5, iclass 7, count 0 2006.286.05:38:33.44#ibcon#read 5, iclass 7, count 0 2006.286.05:38:33.44#ibcon#about to read 6, iclass 7, count 0 2006.286.05:38:33.44#ibcon#read 6, iclass 7, count 0 2006.286.05:38:33.44#ibcon#end of sib2, iclass 7, count 0 2006.286.05:38:33.44#ibcon#*mode == 0, iclass 7, count 0 2006.286.05:38:33.44#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.05:38:33.44#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.05:38:33.44#ibcon#*before write, iclass 7, count 0 2006.286.05:38:33.44#ibcon#enter sib2, iclass 7, count 0 2006.286.05:38:33.44#ibcon#flushed, iclass 7, count 0 2006.286.05:38:33.44#ibcon#about to write, iclass 7, count 0 2006.286.05:38:33.44#ibcon#wrote, iclass 7, count 0 2006.286.05:38:33.44#ibcon#about to read 3, iclass 7, count 0 2006.286.05:38:33.48#ibcon#read 3, iclass 7, count 0 2006.286.05:38:33.48#ibcon#about to read 4, iclass 7, count 0 2006.286.05:38:33.48#ibcon#read 4, iclass 7, count 0 2006.286.05:38:33.48#ibcon#about to read 5, iclass 7, count 0 2006.286.05:38:33.48#ibcon#read 5, iclass 7, count 0 2006.286.05:38:33.48#ibcon#about to read 6, iclass 7, count 0 2006.286.05:38:33.48#ibcon#read 6, iclass 7, count 0 2006.286.05:38:33.48#ibcon#end of sib2, iclass 7, count 0 2006.286.05:38:33.48#ibcon#*after write, iclass 7, count 0 2006.286.05:38:33.48#ibcon#*before return 0, iclass 7, count 0 2006.286.05:38:33.48#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:38:33.48#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:38:33.48#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.05:38:33.48#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.05:38:33.48$vck44/va=6,4 2006.286.05:38:33.48#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.05:38:33.48#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.05:38:33.48#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:33.48#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:38:33.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:38:33.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:38:33.54#ibcon#enter wrdev, iclass 11, count 2 2006.286.05:38:33.54#ibcon#first serial, iclass 11, count 2 2006.286.05:38:33.54#ibcon#enter sib2, iclass 11, count 2 2006.286.05:38:33.54#ibcon#flushed, iclass 11, count 2 2006.286.05:38:33.54#ibcon#about to write, iclass 11, count 2 2006.286.05:38:33.54#ibcon#wrote, iclass 11, count 2 2006.286.05:38:33.54#ibcon#about to read 3, iclass 11, count 2 2006.286.05:38:33.56#ibcon#read 3, iclass 11, count 2 2006.286.05:38:33.58#ibcon#about to read 4, iclass 11, count 2 2006.286.05:38:33.58#ibcon#read 4, iclass 11, count 2 2006.286.05:38:33.58#ibcon#about to read 5, iclass 11, count 2 2006.286.05:38:33.58#ibcon#read 5, iclass 11, count 2 2006.286.05:38:33.58#ibcon#about to read 6, iclass 11, count 2 2006.286.05:38:33.58#ibcon#read 6, iclass 11, count 2 2006.286.05:38:33.58#ibcon#end of sib2, iclass 11, count 2 2006.286.05:38:33.58#ibcon#*mode == 0, iclass 11, count 2 2006.286.05:38:33.58#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.05:38:33.58#ibcon#[25=AT06-04\r\n] 2006.286.05:38:33.58#ibcon#*before write, iclass 11, count 2 2006.286.05:38:33.58#ibcon#enter sib2, iclass 11, count 2 2006.286.05:38:33.58#ibcon#flushed, iclass 11, count 2 2006.286.05:38:33.58#ibcon#about to write, iclass 11, count 2 2006.286.05:38:33.58#ibcon#wrote, iclass 11, count 2 2006.286.05:38:33.58#ibcon#about to read 3, iclass 11, count 2 2006.286.05:38:33.62#ibcon#read 3, iclass 11, count 2 2006.286.05:38:33.62#ibcon#about to read 4, iclass 11, count 2 2006.286.05:38:33.62#ibcon#read 4, iclass 11, count 2 2006.286.05:38:33.62#ibcon#about to read 5, iclass 11, count 2 2006.286.05:38:33.62#ibcon#read 5, iclass 11, count 2 2006.286.05:38:33.62#ibcon#about to read 6, iclass 11, count 2 2006.286.05:38:33.62#ibcon#read 6, iclass 11, count 2 2006.286.05:38:33.62#ibcon#end of sib2, iclass 11, count 2 2006.286.05:38:33.62#ibcon#*after write, iclass 11, count 2 2006.286.05:38:33.62#ibcon#*before return 0, iclass 11, count 2 2006.286.05:38:33.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:38:33.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:38:33.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.05:38:33.62#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:33.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:38:33.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:38:33.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:38:33.74#ibcon#enter wrdev, iclass 11, count 0 2006.286.05:38:33.74#ibcon#first serial, iclass 11, count 0 2006.286.05:38:33.74#ibcon#enter sib2, iclass 11, count 0 2006.286.05:38:33.74#ibcon#flushed, iclass 11, count 0 2006.286.05:38:33.74#ibcon#about to write, iclass 11, count 0 2006.286.05:38:33.74#ibcon#wrote, iclass 11, count 0 2006.286.05:38:33.74#ibcon#about to read 3, iclass 11, count 0 2006.286.05:38:33.76#ibcon#read 3, iclass 11, count 0 2006.286.05:38:33.76#ibcon#about to read 4, iclass 11, count 0 2006.286.05:38:33.76#ibcon#read 4, iclass 11, count 0 2006.286.05:38:33.76#ibcon#about to read 5, iclass 11, count 0 2006.286.05:38:33.76#ibcon#read 5, iclass 11, count 0 2006.286.05:38:33.76#ibcon#about to read 6, iclass 11, count 0 2006.286.05:38:33.76#ibcon#read 6, iclass 11, count 0 2006.286.05:38:33.76#ibcon#end of sib2, iclass 11, count 0 2006.286.05:38:33.76#ibcon#*mode == 0, iclass 11, count 0 2006.286.05:38:33.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.05:38:33.76#ibcon#[25=USB\r\n] 2006.286.05:38:33.76#ibcon#*before write, iclass 11, count 0 2006.286.05:38:33.76#ibcon#enter sib2, iclass 11, count 0 2006.286.05:38:33.76#ibcon#flushed, iclass 11, count 0 2006.286.05:38:33.76#ibcon#about to write, iclass 11, count 0 2006.286.05:38:33.76#ibcon#wrote, iclass 11, count 0 2006.286.05:38:33.76#ibcon#about to read 3, iclass 11, count 0 2006.286.05:38:33.79#ibcon#read 3, iclass 11, count 0 2006.286.05:38:33.79#ibcon#about to read 4, iclass 11, count 0 2006.286.05:38:33.79#ibcon#read 4, iclass 11, count 0 2006.286.05:38:33.79#ibcon#about to read 5, iclass 11, count 0 2006.286.05:38:33.79#ibcon#read 5, iclass 11, count 0 2006.286.05:38:33.79#ibcon#about to read 6, iclass 11, count 0 2006.286.05:38:33.79#ibcon#read 6, iclass 11, count 0 2006.286.05:38:33.79#ibcon#end of sib2, iclass 11, count 0 2006.286.05:38:33.79#ibcon#*after write, iclass 11, count 0 2006.286.05:38:33.79#ibcon#*before return 0, iclass 11, count 0 2006.286.05:38:33.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:38:33.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:38:33.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.05:38:33.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.05:38:33.79$vck44/valo=7,864.99 2006.286.05:38:33.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.05:38:33.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.05:38:33.79#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:33.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:38:33.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:38:33.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:38:33.79#ibcon#enter wrdev, iclass 13, count 0 2006.286.05:38:33.79#ibcon#first serial, iclass 13, count 0 2006.286.05:38:33.79#ibcon#enter sib2, iclass 13, count 0 2006.286.05:38:33.79#ibcon#flushed, iclass 13, count 0 2006.286.05:38:33.79#ibcon#about to write, iclass 13, count 0 2006.286.05:38:33.79#ibcon#wrote, iclass 13, count 0 2006.286.05:38:33.79#ibcon#about to read 3, iclass 13, count 0 2006.286.05:38:33.81#ibcon#read 3, iclass 13, count 0 2006.286.05:38:33.81#ibcon#about to read 4, iclass 13, count 0 2006.286.05:38:33.81#ibcon#read 4, iclass 13, count 0 2006.286.05:38:33.81#ibcon#about to read 5, iclass 13, count 0 2006.286.05:38:33.81#ibcon#read 5, iclass 13, count 0 2006.286.05:38:33.81#ibcon#about to read 6, iclass 13, count 0 2006.286.05:38:33.81#ibcon#read 6, iclass 13, count 0 2006.286.05:38:33.81#ibcon#end of sib2, iclass 13, count 0 2006.286.05:38:33.81#ibcon#*mode == 0, iclass 13, count 0 2006.286.05:38:33.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.05:38:33.81#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.05:38:33.81#ibcon#*before write, iclass 13, count 0 2006.286.05:38:33.81#ibcon#enter sib2, iclass 13, count 0 2006.286.05:38:33.81#ibcon#flushed, iclass 13, count 0 2006.286.05:38:33.81#ibcon#about to write, iclass 13, count 0 2006.286.05:38:33.81#ibcon#wrote, iclass 13, count 0 2006.286.05:38:33.81#ibcon#about to read 3, iclass 13, count 0 2006.286.05:38:33.85#ibcon#read 3, iclass 13, count 0 2006.286.05:38:33.85#ibcon#about to read 4, iclass 13, count 0 2006.286.05:38:33.85#ibcon#read 4, iclass 13, count 0 2006.286.05:38:33.85#ibcon#about to read 5, iclass 13, count 0 2006.286.05:38:33.85#ibcon#read 5, iclass 13, count 0 2006.286.05:38:33.85#ibcon#about to read 6, iclass 13, count 0 2006.286.05:38:33.85#ibcon#read 6, iclass 13, count 0 2006.286.05:38:33.85#ibcon#end of sib2, iclass 13, count 0 2006.286.05:38:33.85#ibcon#*after write, iclass 13, count 0 2006.286.05:38:33.85#ibcon#*before return 0, iclass 13, count 0 2006.286.05:38:33.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:38:33.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:38:33.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.05:38:33.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.05:38:33.85$vck44/va=7,4 2006.286.05:38:33.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.05:38:33.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.05:38:33.85#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:33.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:38:33.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:38:33.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:38:33.91#ibcon#enter wrdev, iclass 15, count 2 2006.286.05:38:33.91#ibcon#first serial, iclass 15, count 2 2006.286.05:38:33.91#ibcon#enter sib2, iclass 15, count 2 2006.286.05:38:33.91#ibcon#flushed, iclass 15, count 2 2006.286.05:38:33.91#ibcon#about to write, iclass 15, count 2 2006.286.05:38:33.91#ibcon#wrote, iclass 15, count 2 2006.286.05:38:33.91#ibcon#about to read 3, iclass 15, count 2 2006.286.05:38:33.93#ibcon#read 3, iclass 15, count 2 2006.286.05:38:33.93#ibcon#about to read 4, iclass 15, count 2 2006.286.05:38:33.93#ibcon#read 4, iclass 15, count 2 2006.286.05:38:33.93#ibcon#about to read 5, iclass 15, count 2 2006.286.05:38:33.93#ibcon#read 5, iclass 15, count 2 2006.286.05:38:33.93#ibcon#about to read 6, iclass 15, count 2 2006.286.05:38:33.93#ibcon#read 6, iclass 15, count 2 2006.286.05:38:33.93#ibcon#end of sib2, iclass 15, count 2 2006.286.05:38:33.93#ibcon#*mode == 0, iclass 15, count 2 2006.286.05:38:33.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.05:38:33.93#ibcon#[25=AT07-04\r\n] 2006.286.05:38:33.93#ibcon#*before write, iclass 15, count 2 2006.286.05:38:33.93#ibcon#enter sib2, iclass 15, count 2 2006.286.05:38:33.93#ibcon#flushed, iclass 15, count 2 2006.286.05:38:33.93#ibcon#about to write, iclass 15, count 2 2006.286.05:38:33.93#ibcon#wrote, iclass 15, count 2 2006.286.05:38:33.93#ibcon#about to read 3, iclass 15, count 2 2006.286.05:38:33.96#ibcon#read 3, iclass 15, count 2 2006.286.05:38:33.96#ibcon#about to read 4, iclass 15, count 2 2006.286.05:38:33.96#ibcon#read 4, iclass 15, count 2 2006.286.05:38:33.96#ibcon#about to read 5, iclass 15, count 2 2006.286.05:38:33.96#ibcon#read 5, iclass 15, count 2 2006.286.05:38:33.96#ibcon#about to read 6, iclass 15, count 2 2006.286.05:38:33.96#ibcon#read 6, iclass 15, count 2 2006.286.05:38:33.96#ibcon#end of sib2, iclass 15, count 2 2006.286.05:38:33.96#ibcon#*after write, iclass 15, count 2 2006.286.05:38:33.96#ibcon#*before return 0, iclass 15, count 2 2006.286.05:38:33.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:38:33.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:38:33.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.05:38:33.96#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:33.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:38:34.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:38:34.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:38:34.08#ibcon#enter wrdev, iclass 15, count 0 2006.286.05:38:34.08#ibcon#first serial, iclass 15, count 0 2006.286.05:38:34.08#ibcon#enter sib2, iclass 15, count 0 2006.286.05:38:34.08#ibcon#flushed, iclass 15, count 0 2006.286.05:38:34.08#ibcon#about to write, iclass 15, count 0 2006.286.05:38:34.08#ibcon#wrote, iclass 15, count 0 2006.286.05:38:34.08#ibcon#about to read 3, iclass 15, count 0 2006.286.05:38:34.10#ibcon#read 3, iclass 15, count 0 2006.286.05:38:34.10#ibcon#about to read 4, iclass 15, count 0 2006.286.05:38:34.10#ibcon#read 4, iclass 15, count 0 2006.286.05:38:34.10#ibcon#about to read 5, iclass 15, count 0 2006.286.05:38:34.10#ibcon#read 5, iclass 15, count 0 2006.286.05:38:34.10#ibcon#about to read 6, iclass 15, count 0 2006.286.05:38:34.10#ibcon#read 6, iclass 15, count 0 2006.286.05:38:34.10#ibcon#end of sib2, iclass 15, count 0 2006.286.05:38:34.10#ibcon#*mode == 0, iclass 15, count 0 2006.286.05:38:34.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.05:38:34.10#ibcon#[25=USB\r\n] 2006.286.05:38:34.10#ibcon#*before write, iclass 15, count 0 2006.286.05:38:34.10#ibcon#enter sib2, iclass 15, count 0 2006.286.05:38:34.10#ibcon#flushed, iclass 15, count 0 2006.286.05:38:34.10#ibcon#about to write, iclass 15, count 0 2006.286.05:38:34.10#ibcon#wrote, iclass 15, count 0 2006.286.05:38:34.10#ibcon#about to read 3, iclass 15, count 0 2006.286.05:38:34.13#ibcon#read 3, iclass 15, count 0 2006.286.05:38:34.13#ibcon#about to read 4, iclass 15, count 0 2006.286.05:38:34.13#ibcon#read 4, iclass 15, count 0 2006.286.05:38:34.13#ibcon#about to read 5, iclass 15, count 0 2006.286.05:38:34.13#ibcon#read 5, iclass 15, count 0 2006.286.05:38:34.13#ibcon#about to read 6, iclass 15, count 0 2006.286.05:38:34.13#ibcon#read 6, iclass 15, count 0 2006.286.05:38:34.13#ibcon#end of sib2, iclass 15, count 0 2006.286.05:38:34.13#ibcon#*after write, iclass 15, count 0 2006.286.05:38:34.13#ibcon#*before return 0, iclass 15, count 0 2006.286.05:38:34.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:38:34.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:38:34.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.05:38:34.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.05:38:34.13$vck44/valo=8,884.99 2006.286.05:38:34.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.05:38:34.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.05:38:34.13#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:34.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:38:34.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:38:34.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:38:34.13#ibcon#enter wrdev, iclass 17, count 0 2006.286.05:38:34.13#ibcon#first serial, iclass 17, count 0 2006.286.05:38:34.13#ibcon#enter sib2, iclass 17, count 0 2006.286.05:38:34.13#ibcon#flushed, iclass 17, count 0 2006.286.05:38:34.13#ibcon#about to write, iclass 17, count 0 2006.286.05:38:34.13#ibcon#wrote, iclass 17, count 0 2006.286.05:38:34.13#ibcon#about to read 3, iclass 17, count 0 2006.286.05:38:34.15#ibcon#read 3, iclass 17, count 0 2006.286.05:38:34.15#ibcon#about to read 4, iclass 17, count 0 2006.286.05:38:34.15#ibcon#read 4, iclass 17, count 0 2006.286.05:38:34.15#ibcon#about to read 5, iclass 17, count 0 2006.286.05:38:34.15#ibcon#read 5, iclass 17, count 0 2006.286.05:38:34.15#ibcon#about to read 6, iclass 17, count 0 2006.286.05:38:34.15#ibcon#read 6, iclass 17, count 0 2006.286.05:38:34.15#ibcon#end of sib2, iclass 17, count 0 2006.286.05:38:34.15#ibcon#*mode == 0, iclass 17, count 0 2006.286.05:38:34.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.05:38:34.15#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.05:38:34.15#ibcon#*before write, iclass 17, count 0 2006.286.05:38:34.15#ibcon#enter sib2, iclass 17, count 0 2006.286.05:38:34.15#ibcon#flushed, iclass 17, count 0 2006.286.05:38:34.15#ibcon#about to write, iclass 17, count 0 2006.286.05:38:34.15#ibcon#wrote, iclass 17, count 0 2006.286.05:38:34.15#ibcon#about to read 3, iclass 17, count 0 2006.286.05:38:34.19#ibcon#read 3, iclass 17, count 0 2006.286.05:38:34.19#ibcon#about to read 4, iclass 17, count 0 2006.286.05:38:34.19#ibcon#read 4, iclass 17, count 0 2006.286.05:38:34.19#ibcon#about to read 5, iclass 17, count 0 2006.286.05:38:34.19#ibcon#read 5, iclass 17, count 0 2006.286.05:38:34.19#ibcon#about to read 6, iclass 17, count 0 2006.286.05:38:34.19#ibcon#read 6, iclass 17, count 0 2006.286.05:38:34.19#ibcon#end of sib2, iclass 17, count 0 2006.286.05:38:34.19#ibcon#*after write, iclass 17, count 0 2006.286.05:38:34.19#ibcon#*before return 0, iclass 17, count 0 2006.286.05:38:34.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:38:34.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:38:34.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.05:38:34.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.05:38:34.19$vck44/va=8,3 2006.286.05:38:34.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.05:38:34.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.05:38:34.19#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:34.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:38:34.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:38:34.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:38:34.25#ibcon#enter wrdev, iclass 19, count 2 2006.286.05:38:34.25#ibcon#first serial, iclass 19, count 2 2006.286.05:38:34.25#ibcon#enter sib2, iclass 19, count 2 2006.286.05:38:34.25#ibcon#flushed, iclass 19, count 2 2006.286.05:38:34.25#ibcon#about to write, iclass 19, count 2 2006.286.05:38:34.25#ibcon#wrote, iclass 19, count 2 2006.286.05:38:34.25#ibcon#about to read 3, iclass 19, count 2 2006.286.05:38:34.27#ibcon#read 3, iclass 19, count 2 2006.286.05:38:34.27#ibcon#about to read 4, iclass 19, count 2 2006.286.05:38:34.27#ibcon#read 4, iclass 19, count 2 2006.286.05:38:34.27#ibcon#about to read 5, iclass 19, count 2 2006.286.05:38:34.27#ibcon#read 5, iclass 19, count 2 2006.286.05:38:34.27#ibcon#about to read 6, iclass 19, count 2 2006.286.05:38:34.27#ibcon#read 6, iclass 19, count 2 2006.286.05:38:34.27#ibcon#end of sib2, iclass 19, count 2 2006.286.05:38:34.27#ibcon#*mode == 0, iclass 19, count 2 2006.286.05:38:34.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.05:38:34.27#ibcon#[25=AT08-03\r\n] 2006.286.05:38:34.27#ibcon#*before write, iclass 19, count 2 2006.286.05:38:34.27#ibcon#enter sib2, iclass 19, count 2 2006.286.05:38:34.27#ibcon#flushed, iclass 19, count 2 2006.286.05:38:34.27#ibcon#about to write, iclass 19, count 2 2006.286.05:38:34.27#ibcon#wrote, iclass 19, count 2 2006.286.05:38:34.27#ibcon#about to read 3, iclass 19, count 2 2006.286.05:38:34.30#ibcon#read 3, iclass 19, count 2 2006.286.05:38:34.30#ibcon#about to read 4, iclass 19, count 2 2006.286.05:38:34.30#ibcon#read 4, iclass 19, count 2 2006.286.05:38:34.30#ibcon#about to read 5, iclass 19, count 2 2006.286.05:38:34.30#ibcon#read 5, iclass 19, count 2 2006.286.05:38:34.30#ibcon#about to read 6, iclass 19, count 2 2006.286.05:38:34.30#ibcon#read 6, iclass 19, count 2 2006.286.05:38:34.30#ibcon#end of sib2, iclass 19, count 2 2006.286.05:38:34.30#ibcon#*after write, iclass 19, count 2 2006.286.05:38:34.30#ibcon#*before return 0, iclass 19, count 2 2006.286.05:38:34.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:38:34.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:38:34.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.05:38:34.30#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:34.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:38:34.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:38:34.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:38:34.42#ibcon#enter wrdev, iclass 19, count 0 2006.286.05:38:34.42#ibcon#first serial, iclass 19, count 0 2006.286.05:38:34.42#ibcon#enter sib2, iclass 19, count 0 2006.286.05:38:34.42#ibcon#flushed, iclass 19, count 0 2006.286.05:38:34.42#ibcon#about to write, iclass 19, count 0 2006.286.05:38:34.42#ibcon#wrote, iclass 19, count 0 2006.286.05:38:34.42#ibcon#about to read 3, iclass 19, count 0 2006.286.05:38:34.44#ibcon#read 3, iclass 19, count 0 2006.286.05:38:34.44#ibcon#about to read 4, iclass 19, count 0 2006.286.05:38:34.44#ibcon#read 4, iclass 19, count 0 2006.286.05:38:34.44#ibcon#about to read 5, iclass 19, count 0 2006.286.05:38:34.44#ibcon#read 5, iclass 19, count 0 2006.286.05:38:34.44#ibcon#about to read 6, iclass 19, count 0 2006.286.05:38:34.44#ibcon#read 6, iclass 19, count 0 2006.286.05:38:34.44#ibcon#end of sib2, iclass 19, count 0 2006.286.05:38:34.44#ibcon#*mode == 0, iclass 19, count 0 2006.286.05:38:34.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.05:38:34.44#ibcon#[25=USB\r\n] 2006.286.05:38:34.44#ibcon#*before write, iclass 19, count 0 2006.286.05:38:34.44#ibcon#enter sib2, iclass 19, count 0 2006.286.05:38:34.44#ibcon#flushed, iclass 19, count 0 2006.286.05:38:34.44#ibcon#about to write, iclass 19, count 0 2006.286.05:38:34.44#ibcon#wrote, iclass 19, count 0 2006.286.05:38:34.44#ibcon#about to read 3, iclass 19, count 0 2006.286.05:38:34.47#ibcon#read 3, iclass 19, count 0 2006.286.05:38:34.47#ibcon#about to read 4, iclass 19, count 0 2006.286.05:38:34.47#ibcon#read 4, iclass 19, count 0 2006.286.05:38:34.47#ibcon#about to read 5, iclass 19, count 0 2006.286.05:38:34.47#ibcon#read 5, iclass 19, count 0 2006.286.05:38:34.47#ibcon#about to read 6, iclass 19, count 0 2006.286.05:38:34.47#ibcon#read 6, iclass 19, count 0 2006.286.05:38:34.47#ibcon#end of sib2, iclass 19, count 0 2006.286.05:38:34.47#ibcon#*after write, iclass 19, count 0 2006.286.05:38:34.47#ibcon#*before return 0, iclass 19, count 0 2006.286.05:38:34.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:38:34.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:38:34.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.05:38:34.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.05:38:34.47$vck44/vblo=1,629.99 2006.286.05:38:34.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.05:38:34.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.05:38:34.47#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:34.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:38:34.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:38:34.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:38:34.47#ibcon#enter wrdev, iclass 21, count 0 2006.286.05:38:34.47#ibcon#first serial, iclass 21, count 0 2006.286.05:38:34.47#ibcon#enter sib2, iclass 21, count 0 2006.286.05:38:34.47#ibcon#flushed, iclass 21, count 0 2006.286.05:38:34.47#ibcon#about to write, iclass 21, count 0 2006.286.05:38:34.47#ibcon#wrote, iclass 21, count 0 2006.286.05:38:34.47#ibcon#about to read 3, iclass 21, count 0 2006.286.05:38:34.49#ibcon#read 3, iclass 21, count 0 2006.286.05:38:34.71#ibcon#about to read 4, iclass 21, count 0 2006.286.05:38:34.71#ibcon#read 4, iclass 21, count 0 2006.286.05:38:34.71#ibcon#about to read 5, iclass 21, count 0 2006.286.05:38:34.71#ibcon#read 5, iclass 21, count 0 2006.286.05:38:34.71#ibcon#about to read 6, iclass 21, count 0 2006.286.05:38:34.71#ibcon#read 6, iclass 21, count 0 2006.286.05:38:34.71#ibcon#end of sib2, iclass 21, count 0 2006.286.05:38:34.71#ibcon#*mode == 0, iclass 21, count 0 2006.286.05:38:34.71#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.05:38:34.71#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.05:38:34.71#ibcon#*before write, iclass 21, count 0 2006.286.05:38:34.71#ibcon#enter sib2, iclass 21, count 0 2006.286.05:38:34.71#ibcon#flushed, iclass 21, count 0 2006.286.05:38:34.71#ibcon#about to write, iclass 21, count 0 2006.286.05:38:34.71#ibcon#wrote, iclass 21, count 0 2006.286.05:38:34.71#ibcon#about to read 3, iclass 21, count 0 2006.286.05:38:34.75#ibcon#read 3, iclass 21, count 0 2006.286.05:38:34.75#ibcon#about to read 4, iclass 21, count 0 2006.286.05:38:34.75#ibcon#read 4, iclass 21, count 0 2006.286.05:38:34.75#ibcon#about to read 5, iclass 21, count 0 2006.286.05:38:34.75#ibcon#read 5, iclass 21, count 0 2006.286.05:38:34.75#ibcon#about to read 6, iclass 21, count 0 2006.286.05:38:34.75#ibcon#read 6, iclass 21, count 0 2006.286.05:38:34.75#ibcon#end of sib2, iclass 21, count 0 2006.286.05:38:34.75#ibcon#*after write, iclass 21, count 0 2006.286.05:38:34.75#ibcon#*before return 0, iclass 21, count 0 2006.286.05:38:34.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:38:34.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:38:34.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.05:38:34.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.05:38:34.75$vck44/vb=1,4 2006.286.05:38:34.75#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.05:38:34.75#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.05:38:34.75#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:34.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:38:34.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:38:34.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:38:34.75#ibcon#enter wrdev, iclass 24, count 2 2006.286.05:38:34.75#ibcon#first serial, iclass 24, count 2 2006.286.05:38:34.75#ibcon#enter sib2, iclass 24, count 2 2006.286.05:38:34.75#ibcon#flushed, iclass 24, count 2 2006.286.05:38:34.75#ibcon#about to write, iclass 24, count 2 2006.286.05:38:34.75#ibcon#wrote, iclass 24, count 2 2006.286.05:38:34.75#ibcon#about to read 3, iclass 24, count 2 2006.286.05:38:34.76#abcon#<5=/04 3.5 7.5 20.94 781015.2\r\n> 2006.286.05:38:34.77#ibcon#read 3, iclass 24, count 2 2006.286.05:38:34.77#ibcon#about to read 4, iclass 24, count 2 2006.286.05:38:34.77#ibcon#read 4, iclass 24, count 2 2006.286.05:38:34.77#ibcon#about to read 5, iclass 24, count 2 2006.286.05:38:34.77#ibcon#read 5, iclass 24, count 2 2006.286.05:38:34.77#ibcon#about to read 6, iclass 24, count 2 2006.286.05:38:34.77#ibcon#read 6, iclass 24, count 2 2006.286.05:38:34.77#ibcon#end of sib2, iclass 24, count 2 2006.286.05:38:34.77#ibcon#*mode == 0, iclass 24, count 2 2006.286.05:38:34.77#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.05:38:34.77#ibcon#[27=AT01-04\r\n] 2006.286.05:38:34.77#ibcon#*before write, iclass 24, count 2 2006.286.05:38:34.77#ibcon#enter sib2, iclass 24, count 2 2006.286.05:38:34.77#ibcon#flushed, iclass 24, count 2 2006.286.05:38:34.77#ibcon#about to write, iclass 24, count 2 2006.286.05:38:34.77#ibcon#wrote, iclass 24, count 2 2006.286.05:38:34.77#ibcon#about to read 3, iclass 24, count 2 2006.286.05:38:34.78#abcon#{5=INTERFACE CLEAR} 2006.286.05:38:34.80#ibcon#read 3, iclass 24, count 2 2006.286.05:38:34.80#ibcon#about to read 4, iclass 24, count 2 2006.286.05:38:34.80#ibcon#read 4, iclass 24, count 2 2006.286.05:38:34.80#ibcon#about to read 5, iclass 24, count 2 2006.286.05:38:34.80#ibcon#read 5, iclass 24, count 2 2006.286.05:38:34.80#ibcon#about to read 6, iclass 24, count 2 2006.286.05:38:34.80#ibcon#read 6, iclass 24, count 2 2006.286.05:38:34.80#ibcon#end of sib2, iclass 24, count 2 2006.286.05:38:34.80#ibcon#*after write, iclass 24, count 2 2006.286.05:38:34.80#ibcon#*before return 0, iclass 24, count 2 2006.286.05:38:34.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:38:34.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:38:34.80#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.05:38:34.80#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:34.80#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:38:34.84#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:38:34.92#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:38:34.92#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:38:34.92#ibcon#enter wrdev, iclass 24, count 0 2006.286.05:38:34.92#ibcon#first serial, iclass 24, count 0 2006.286.05:38:34.92#ibcon#enter sib2, iclass 24, count 0 2006.286.05:38:34.92#ibcon#flushed, iclass 24, count 0 2006.286.05:38:34.92#ibcon#about to write, iclass 24, count 0 2006.286.05:38:34.92#ibcon#wrote, iclass 24, count 0 2006.286.05:38:34.92#ibcon#about to read 3, iclass 24, count 0 2006.286.05:38:34.94#ibcon#read 3, iclass 24, count 0 2006.286.05:38:34.94#ibcon#about to read 4, iclass 24, count 0 2006.286.05:38:34.94#ibcon#read 4, iclass 24, count 0 2006.286.05:38:34.94#ibcon#about to read 5, iclass 24, count 0 2006.286.05:38:34.94#ibcon#read 5, iclass 24, count 0 2006.286.05:38:34.94#ibcon#about to read 6, iclass 24, count 0 2006.286.05:38:34.94#ibcon#read 6, iclass 24, count 0 2006.286.05:38:34.94#ibcon#end of sib2, iclass 24, count 0 2006.286.05:38:34.94#ibcon#*mode == 0, iclass 24, count 0 2006.286.05:38:34.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.05:38:34.94#ibcon#[27=USB\r\n] 2006.286.05:38:34.94#ibcon#*before write, iclass 24, count 0 2006.286.05:38:34.94#ibcon#enter sib2, iclass 24, count 0 2006.286.05:38:34.94#ibcon#flushed, iclass 24, count 0 2006.286.05:38:34.94#ibcon#about to write, iclass 24, count 0 2006.286.05:38:34.94#ibcon#wrote, iclass 24, count 0 2006.286.05:38:34.94#ibcon#about to read 3, iclass 24, count 0 2006.286.05:38:34.97#ibcon#read 3, iclass 24, count 0 2006.286.05:38:34.97#ibcon#about to read 4, iclass 24, count 0 2006.286.05:38:34.97#ibcon#read 4, iclass 24, count 0 2006.286.05:38:34.97#ibcon#about to read 5, iclass 24, count 0 2006.286.05:38:34.97#ibcon#read 5, iclass 24, count 0 2006.286.05:38:34.97#ibcon#about to read 6, iclass 24, count 0 2006.286.05:38:34.97#ibcon#read 6, iclass 24, count 0 2006.286.05:38:34.97#ibcon#end of sib2, iclass 24, count 0 2006.286.05:38:34.97#ibcon#*after write, iclass 24, count 0 2006.286.05:38:34.97#ibcon#*before return 0, iclass 24, count 0 2006.286.05:38:34.97#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:38:34.97#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:38:34.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.05:38:34.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.05:38:34.97$vck44/vblo=2,634.99 2006.286.05:38:34.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.05:38:34.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.05:38:34.97#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:34.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:38:34.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:38:34.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:38:34.97#ibcon#enter wrdev, iclass 29, count 0 2006.286.05:38:34.97#ibcon#first serial, iclass 29, count 0 2006.286.05:38:34.97#ibcon#enter sib2, iclass 29, count 0 2006.286.05:38:34.97#ibcon#flushed, iclass 29, count 0 2006.286.05:38:34.97#ibcon#about to write, iclass 29, count 0 2006.286.05:38:34.97#ibcon#wrote, iclass 29, count 0 2006.286.05:38:34.97#ibcon#about to read 3, iclass 29, count 0 2006.286.05:38:34.99#ibcon#read 3, iclass 29, count 0 2006.286.05:38:34.99#ibcon#about to read 4, iclass 29, count 0 2006.286.05:38:34.99#ibcon#read 4, iclass 29, count 0 2006.286.05:38:34.99#ibcon#about to read 5, iclass 29, count 0 2006.286.05:38:34.99#ibcon#read 5, iclass 29, count 0 2006.286.05:38:34.99#ibcon#about to read 6, iclass 29, count 0 2006.286.05:38:34.99#ibcon#read 6, iclass 29, count 0 2006.286.05:38:34.99#ibcon#end of sib2, iclass 29, count 0 2006.286.05:38:34.99#ibcon#*mode == 0, iclass 29, count 0 2006.286.05:38:34.99#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.05:38:34.99#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.05:38:34.99#ibcon#*before write, iclass 29, count 0 2006.286.05:38:34.99#ibcon#enter sib2, iclass 29, count 0 2006.286.05:38:34.99#ibcon#flushed, iclass 29, count 0 2006.286.05:38:34.99#ibcon#about to write, iclass 29, count 0 2006.286.05:38:34.99#ibcon#wrote, iclass 29, count 0 2006.286.05:38:34.99#ibcon#about to read 3, iclass 29, count 0 2006.286.05:38:35.03#ibcon#read 3, iclass 29, count 0 2006.286.05:38:35.03#ibcon#about to read 4, iclass 29, count 0 2006.286.05:38:35.03#ibcon#read 4, iclass 29, count 0 2006.286.05:38:35.03#ibcon#about to read 5, iclass 29, count 0 2006.286.05:38:35.03#ibcon#read 5, iclass 29, count 0 2006.286.05:38:35.03#ibcon#about to read 6, iclass 29, count 0 2006.286.05:38:35.03#ibcon#read 6, iclass 29, count 0 2006.286.05:38:35.03#ibcon#end of sib2, iclass 29, count 0 2006.286.05:38:35.03#ibcon#*after write, iclass 29, count 0 2006.286.05:38:35.03#ibcon#*before return 0, iclass 29, count 0 2006.286.05:38:35.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:38:35.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:38:35.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.05:38:35.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.05:38:35.03$vck44/vb=2,5 2006.286.05:38:35.03#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.05:38:35.03#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.05:38:35.03#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:35.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:38:35.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:38:35.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:38:35.09#ibcon#enter wrdev, iclass 31, count 2 2006.286.05:38:35.09#ibcon#first serial, iclass 31, count 2 2006.286.05:38:35.09#ibcon#enter sib2, iclass 31, count 2 2006.286.05:38:35.09#ibcon#flushed, iclass 31, count 2 2006.286.05:38:35.09#ibcon#about to write, iclass 31, count 2 2006.286.05:38:35.09#ibcon#wrote, iclass 31, count 2 2006.286.05:38:35.09#ibcon#about to read 3, iclass 31, count 2 2006.286.05:38:35.11#ibcon#read 3, iclass 31, count 2 2006.286.05:38:35.11#ibcon#about to read 4, iclass 31, count 2 2006.286.05:38:35.11#ibcon#read 4, iclass 31, count 2 2006.286.05:38:35.11#ibcon#about to read 5, iclass 31, count 2 2006.286.05:38:35.11#ibcon#read 5, iclass 31, count 2 2006.286.05:38:35.11#ibcon#about to read 6, iclass 31, count 2 2006.286.05:38:35.11#ibcon#read 6, iclass 31, count 2 2006.286.05:38:35.11#ibcon#end of sib2, iclass 31, count 2 2006.286.05:38:35.11#ibcon#*mode == 0, iclass 31, count 2 2006.286.05:38:35.11#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.05:38:35.11#ibcon#[27=AT02-05\r\n] 2006.286.05:38:35.11#ibcon#*before write, iclass 31, count 2 2006.286.05:38:35.11#ibcon#enter sib2, iclass 31, count 2 2006.286.05:38:35.11#ibcon#flushed, iclass 31, count 2 2006.286.05:38:35.11#ibcon#about to write, iclass 31, count 2 2006.286.05:38:35.11#ibcon#wrote, iclass 31, count 2 2006.286.05:38:35.11#ibcon#about to read 3, iclass 31, count 2 2006.286.05:38:35.14#ibcon#read 3, iclass 31, count 2 2006.286.05:38:35.14#ibcon#about to read 4, iclass 31, count 2 2006.286.05:38:35.14#ibcon#read 4, iclass 31, count 2 2006.286.05:38:35.14#ibcon#about to read 5, iclass 31, count 2 2006.286.05:38:35.14#ibcon#read 5, iclass 31, count 2 2006.286.05:38:35.14#ibcon#about to read 6, iclass 31, count 2 2006.286.05:38:35.14#ibcon#read 6, iclass 31, count 2 2006.286.05:38:35.14#ibcon#end of sib2, iclass 31, count 2 2006.286.05:38:35.14#ibcon#*after write, iclass 31, count 2 2006.286.05:38:35.14#ibcon#*before return 0, iclass 31, count 2 2006.286.05:38:35.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:38:35.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:38:35.14#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.05:38:35.14#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:35.14#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:38:35.26#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:38:35.26#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:38:35.26#ibcon#enter wrdev, iclass 31, count 0 2006.286.05:38:35.26#ibcon#first serial, iclass 31, count 0 2006.286.05:38:35.26#ibcon#enter sib2, iclass 31, count 0 2006.286.05:38:35.26#ibcon#flushed, iclass 31, count 0 2006.286.05:38:35.26#ibcon#about to write, iclass 31, count 0 2006.286.05:38:35.26#ibcon#wrote, iclass 31, count 0 2006.286.05:38:35.26#ibcon#about to read 3, iclass 31, count 0 2006.286.05:38:35.28#ibcon#read 3, iclass 31, count 0 2006.286.05:38:35.28#ibcon#about to read 4, iclass 31, count 0 2006.286.05:38:35.28#ibcon#read 4, iclass 31, count 0 2006.286.05:38:35.28#ibcon#about to read 5, iclass 31, count 0 2006.286.05:38:35.28#ibcon#read 5, iclass 31, count 0 2006.286.05:38:35.28#ibcon#about to read 6, iclass 31, count 0 2006.286.05:38:35.28#ibcon#read 6, iclass 31, count 0 2006.286.05:38:35.28#ibcon#end of sib2, iclass 31, count 0 2006.286.05:38:35.28#ibcon#*mode == 0, iclass 31, count 0 2006.286.05:38:35.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.05:38:35.28#ibcon#[27=USB\r\n] 2006.286.05:38:35.28#ibcon#*before write, iclass 31, count 0 2006.286.05:38:35.28#ibcon#enter sib2, iclass 31, count 0 2006.286.05:38:35.28#ibcon#flushed, iclass 31, count 0 2006.286.05:38:35.28#ibcon#about to write, iclass 31, count 0 2006.286.05:38:35.28#ibcon#wrote, iclass 31, count 0 2006.286.05:38:35.28#ibcon#about to read 3, iclass 31, count 0 2006.286.05:38:35.31#ibcon#read 3, iclass 31, count 0 2006.286.05:38:35.31#ibcon#about to read 4, iclass 31, count 0 2006.286.05:38:35.31#ibcon#read 4, iclass 31, count 0 2006.286.05:38:35.31#ibcon#about to read 5, iclass 31, count 0 2006.286.05:38:35.31#ibcon#read 5, iclass 31, count 0 2006.286.05:38:35.31#ibcon#about to read 6, iclass 31, count 0 2006.286.05:38:35.31#ibcon#read 6, iclass 31, count 0 2006.286.05:38:35.31#ibcon#end of sib2, iclass 31, count 0 2006.286.05:38:35.31#ibcon#*after write, iclass 31, count 0 2006.286.05:38:35.31#ibcon#*before return 0, iclass 31, count 0 2006.286.05:38:35.31#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:38:35.31#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:38:35.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.05:38:35.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.05:38:35.31$vck44/vblo=3,649.99 2006.286.05:38:35.31#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.05:38:35.31#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.05:38:35.31#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:35.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:38:35.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:38:35.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:38:35.31#ibcon#enter wrdev, iclass 33, count 0 2006.286.05:38:35.31#ibcon#first serial, iclass 33, count 0 2006.286.05:38:35.31#ibcon#enter sib2, iclass 33, count 0 2006.286.05:38:35.31#ibcon#flushed, iclass 33, count 0 2006.286.05:38:35.31#ibcon#about to write, iclass 33, count 0 2006.286.05:38:35.31#ibcon#wrote, iclass 33, count 0 2006.286.05:38:35.31#ibcon#about to read 3, iclass 33, count 0 2006.286.05:38:35.33#ibcon#read 3, iclass 33, count 0 2006.286.05:38:35.33#ibcon#about to read 4, iclass 33, count 0 2006.286.05:38:35.33#ibcon#read 4, iclass 33, count 0 2006.286.05:38:35.33#ibcon#about to read 5, iclass 33, count 0 2006.286.05:38:35.33#ibcon#read 5, iclass 33, count 0 2006.286.05:38:35.33#ibcon#about to read 6, iclass 33, count 0 2006.286.05:38:35.33#ibcon#read 6, iclass 33, count 0 2006.286.05:38:35.33#ibcon#end of sib2, iclass 33, count 0 2006.286.05:38:35.33#ibcon#*mode == 0, iclass 33, count 0 2006.286.05:38:35.33#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.05:38:35.33#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.05:38:35.33#ibcon#*before write, iclass 33, count 0 2006.286.05:38:35.33#ibcon#enter sib2, iclass 33, count 0 2006.286.05:38:35.33#ibcon#flushed, iclass 33, count 0 2006.286.05:38:35.33#ibcon#about to write, iclass 33, count 0 2006.286.05:38:35.33#ibcon#wrote, iclass 33, count 0 2006.286.05:38:35.33#ibcon#about to read 3, iclass 33, count 0 2006.286.05:38:35.37#ibcon#read 3, iclass 33, count 0 2006.286.05:38:35.37#ibcon#about to read 4, iclass 33, count 0 2006.286.05:38:35.37#ibcon#read 4, iclass 33, count 0 2006.286.05:38:35.37#ibcon#about to read 5, iclass 33, count 0 2006.286.05:38:35.37#ibcon#read 5, iclass 33, count 0 2006.286.05:38:35.37#ibcon#about to read 6, iclass 33, count 0 2006.286.05:38:35.37#ibcon#read 6, iclass 33, count 0 2006.286.05:38:35.37#ibcon#end of sib2, iclass 33, count 0 2006.286.05:38:35.37#ibcon#*after write, iclass 33, count 0 2006.286.05:38:35.37#ibcon#*before return 0, iclass 33, count 0 2006.286.05:38:35.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:38:35.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:38:35.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.05:38:35.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.05:38:35.37$vck44/vb=3,4 2006.286.05:38:35.37#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.05:38:35.37#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.05:38:35.37#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:35.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:38:35.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:38:35.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:38:35.43#ibcon#enter wrdev, iclass 35, count 2 2006.286.05:38:35.43#ibcon#first serial, iclass 35, count 2 2006.286.05:38:35.43#ibcon#enter sib2, iclass 35, count 2 2006.286.05:38:35.43#ibcon#flushed, iclass 35, count 2 2006.286.05:38:35.43#ibcon#about to write, iclass 35, count 2 2006.286.05:38:35.43#ibcon#wrote, iclass 35, count 2 2006.286.05:38:35.43#ibcon#about to read 3, iclass 35, count 2 2006.286.05:38:35.45#ibcon#read 3, iclass 35, count 2 2006.286.05:38:35.45#ibcon#about to read 4, iclass 35, count 2 2006.286.05:38:35.45#ibcon#read 4, iclass 35, count 2 2006.286.05:38:35.45#ibcon#about to read 5, iclass 35, count 2 2006.286.05:38:35.45#ibcon#read 5, iclass 35, count 2 2006.286.05:38:35.45#ibcon#about to read 6, iclass 35, count 2 2006.286.05:38:35.45#ibcon#read 6, iclass 35, count 2 2006.286.05:38:35.45#ibcon#end of sib2, iclass 35, count 2 2006.286.05:38:35.45#ibcon#*mode == 0, iclass 35, count 2 2006.286.05:38:35.45#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.05:38:35.45#ibcon#[27=AT03-04\r\n] 2006.286.05:38:35.45#ibcon#*before write, iclass 35, count 2 2006.286.05:38:35.45#ibcon#enter sib2, iclass 35, count 2 2006.286.05:38:35.45#ibcon#flushed, iclass 35, count 2 2006.286.05:38:35.45#ibcon#about to write, iclass 35, count 2 2006.286.05:38:35.45#ibcon#wrote, iclass 35, count 2 2006.286.05:38:35.45#ibcon#about to read 3, iclass 35, count 2 2006.286.05:38:35.48#ibcon#read 3, iclass 35, count 2 2006.286.05:38:35.48#ibcon#about to read 4, iclass 35, count 2 2006.286.05:38:35.48#ibcon#read 4, iclass 35, count 2 2006.286.05:38:35.48#ibcon#about to read 5, iclass 35, count 2 2006.286.05:38:35.48#ibcon#read 5, iclass 35, count 2 2006.286.05:38:35.48#ibcon#about to read 6, iclass 35, count 2 2006.286.05:38:35.48#ibcon#read 6, iclass 35, count 2 2006.286.05:38:35.48#ibcon#end of sib2, iclass 35, count 2 2006.286.05:38:35.48#ibcon#*after write, iclass 35, count 2 2006.286.05:38:35.48#ibcon#*before return 0, iclass 35, count 2 2006.286.05:38:35.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:38:35.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:38:35.48#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.05:38:35.48#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:35.48#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:38:35.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:38:35.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:38:35.60#ibcon#enter wrdev, iclass 35, count 0 2006.286.05:38:35.60#ibcon#first serial, iclass 35, count 0 2006.286.05:38:35.60#ibcon#enter sib2, iclass 35, count 0 2006.286.05:38:35.60#ibcon#flushed, iclass 35, count 0 2006.286.05:38:35.60#ibcon#about to write, iclass 35, count 0 2006.286.05:38:35.60#ibcon#wrote, iclass 35, count 0 2006.286.05:38:35.60#ibcon#about to read 3, iclass 35, count 0 2006.286.05:38:35.62#ibcon#read 3, iclass 35, count 0 2006.286.05:38:35.62#ibcon#about to read 4, iclass 35, count 0 2006.286.05:38:35.62#ibcon#read 4, iclass 35, count 0 2006.286.05:38:35.62#ibcon#about to read 5, iclass 35, count 0 2006.286.05:38:35.62#ibcon#read 5, iclass 35, count 0 2006.286.05:38:35.62#ibcon#about to read 6, iclass 35, count 0 2006.286.05:38:35.62#ibcon#read 6, iclass 35, count 0 2006.286.05:38:35.75#ibcon#end of sib2, iclass 35, count 0 2006.286.05:38:35.75#ibcon#*mode == 0, iclass 35, count 0 2006.286.05:38:35.75#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.05:38:35.75#ibcon#[27=USB\r\n] 2006.286.05:38:35.75#ibcon#*before write, iclass 35, count 0 2006.286.05:38:35.75#ibcon#enter sib2, iclass 35, count 0 2006.286.05:38:35.75#ibcon#flushed, iclass 35, count 0 2006.286.05:38:35.75#ibcon#about to write, iclass 35, count 0 2006.286.05:38:35.75#ibcon#wrote, iclass 35, count 0 2006.286.05:38:35.75#ibcon#about to read 3, iclass 35, count 0 2006.286.05:38:35.78#ibcon#read 3, iclass 35, count 0 2006.286.05:38:35.78#ibcon#about to read 4, iclass 35, count 0 2006.286.05:38:35.78#ibcon#read 4, iclass 35, count 0 2006.286.05:38:35.78#ibcon#about to read 5, iclass 35, count 0 2006.286.05:38:35.78#ibcon#read 5, iclass 35, count 0 2006.286.05:38:35.78#ibcon#about to read 6, iclass 35, count 0 2006.286.05:38:35.78#ibcon#read 6, iclass 35, count 0 2006.286.05:38:35.78#ibcon#end of sib2, iclass 35, count 0 2006.286.05:38:35.78#ibcon#*after write, iclass 35, count 0 2006.286.05:38:35.78#ibcon#*before return 0, iclass 35, count 0 2006.286.05:38:35.78#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:38:35.78#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:38:35.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.05:38:35.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.05:38:35.78$vck44/vblo=4,679.99 2006.286.05:38:35.78#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.05:38:35.78#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.05:38:35.78#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:35.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:38:35.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:38:35.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:38:35.78#ibcon#enter wrdev, iclass 37, count 0 2006.286.05:38:35.78#ibcon#first serial, iclass 37, count 0 2006.286.05:38:35.78#ibcon#enter sib2, iclass 37, count 0 2006.286.05:38:35.78#ibcon#flushed, iclass 37, count 0 2006.286.05:38:35.78#ibcon#about to write, iclass 37, count 0 2006.286.05:38:35.78#ibcon#wrote, iclass 37, count 0 2006.286.05:38:35.78#ibcon#about to read 3, iclass 37, count 0 2006.286.05:38:35.80#ibcon#read 3, iclass 37, count 0 2006.286.05:38:35.80#ibcon#about to read 4, iclass 37, count 0 2006.286.05:38:35.80#ibcon#read 4, iclass 37, count 0 2006.286.05:38:35.80#ibcon#about to read 5, iclass 37, count 0 2006.286.05:38:35.80#ibcon#read 5, iclass 37, count 0 2006.286.05:38:35.80#ibcon#about to read 6, iclass 37, count 0 2006.286.05:38:35.80#ibcon#read 6, iclass 37, count 0 2006.286.05:38:35.80#ibcon#end of sib2, iclass 37, count 0 2006.286.05:38:35.80#ibcon#*mode == 0, iclass 37, count 0 2006.286.05:38:35.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.05:38:35.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.05:38:35.80#ibcon#*before write, iclass 37, count 0 2006.286.05:38:35.80#ibcon#enter sib2, iclass 37, count 0 2006.286.05:38:35.80#ibcon#flushed, iclass 37, count 0 2006.286.05:38:35.80#ibcon#about to write, iclass 37, count 0 2006.286.05:38:35.80#ibcon#wrote, iclass 37, count 0 2006.286.05:38:35.80#ibcon#about to read 3, iclass 37, count 0 2006.286.05:38:35.84#ibcon#read 3, iclass 37, count 0 2006.286.05:38:35.84#ibcon#about to read 4, iclass 37, count 0 2006.286.05:38:35.84#ibcon#read 4, iclass 37, count 0 2006.286.05:38:35.84#ibcon#about to read 5, iclass 37, count 0 2006.286.05:38:35.84#ibcon#read 5, iclass 37, count 0 2006.286.05:38:35.84#ibcon#about to read 6, iclass 37, count 0 2006.286.05:38:35.84#ibcon#read 6, iclass 37, count 0 2006.286.05:38:35.84#ibcon#end of sib2, iclass 37, count 0 2006.286.05:38:35.84#ibcon#*after write, iclass 37, count 0 2006.286.05:38:35.84#ibcon#*before return 0, iclass 37, count 0 2006.286.05:38:35.84#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:38:35.84#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:38:35.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.05:38:35.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.05:38:35.84$vck44/vb=4,5 2006.286.05:38:35.84#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.05:38:35.84#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.05:38:35.84#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:35.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:38:35.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:38:35.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:38:35.90#ibcon#enter wrdev, iclass 39, count 2 2006.286.05:38:35.90#ibcon#first serial, iclass 39, count 2 2006.286.05:38:35.90#ibcon#enter sib2, iclass 39, count 2 2006.286.05:38:35.90#ibcon#flushed, iclass 39, count 2 2006.286.05:38:35.90#ibcon#about to write, iclass 39, count 2 2006.286.05:38:35.90#ibcon#wrote, iclass 39, count 2 2006.286.05:38:35.90#ibcon#about to read 3, iclass 39, count 2 2006.286.05:38:35.92#ibcon#read 3, iclass 39, count 2 2006.286.05:38:35.92#ibcon#about to read 4, iclass 39, count 2 2006.286.05:38:35.92#ibcon#read 4, iclass 39, count 2 2006.286.05:38:35.92#ibcon#about to read 5, iclass 39, count 2 2006.286.05:38:35.92#ibcon#read 5, iclass 39, count 2 2006.286.05:38:35.92#ibcon#about to read 6, iclass 39, count 2 2006.286.05:38:35.92#ibcon#read 6, iclass 39, count 2 2006.286.05:38:35.92#ibcon#end of sib2, iclass 39, count 2 2006.286.05:38:35.92#ibcon#*mode == 0, iclass 39, count 2 2006.286.05:38:35.92#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.05:38:35.92#ibcon#[27=AT04-05\r\n] 2006.286.05:38:35.92#ibcon#*before write, iclass 39, count 2 2006.286.05:38:35.92#ibcon#enter sib2, iclass 39, count 2 2006.286.05:38:35.92#ibcon#flushed, iclass 39, count 2 2006.286.05:38:35.92#ibcon#about to write, iclass 39, count 2 2006.286.05:38:35.92#ibcon#wrote, iclass 39, count 2 2006.286.05:38:35.92#ibcon#about to read 3, iclass 39, count 2 2006.286.05:38:35.95#ibcon#read 3, iclass 39, count 2 2006.286.05:38:35.95#ibcon#about to read 4, iclass 39, count 2 2006.286.05:38:35.95#ibcon#read 4, iclass 39, count 2 2006.286.05:38:35.95#ibcon#about to read 5, iclass 39, count 2 2006.286.05:38:35.95#ibcon#read 5, iclass 39, count 2 2006.286.05:38:35.95#ibcon#about to read 6, iclass 39, count 2 2006.286.05:38:35.95#ibcon#read 6, iclass 39, count 2 2006.286.05:38:35.95#ibcon#end of sib2, iclass 39, count 2 2006.286.05:38:35.95#ibcon#*after write, iclass 39, count 2 2006.286.05:38:35.95#ibcon#*before return 0, iclass 39, count 2 2006.286.05:38:35.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:38:35.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:38:35.95#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.05:38:35.95#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:35.95#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:38:36.07#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:38:36.07#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:38:36.07#ibcon#enter wrdev, iclass 39, count 0 2006.286.05:38:36.07#ibcon#first serial, iclass 39, count 0 2006.286.05:38:36.07#ibcon#enter sib2, iclass 39, count 0 2006.286.05:38:36.07#ibcon#flushed, iclass 39, count 0 2006.286.05:38:36.07#ibcon#about to write, iclass 39, count 0 2006.286.05:38:36.07#ibcon#wrote, iclass 39, count 0 2006.286.05:38:36.07#ibcon#about to read 3, iclass 39, count 0 2006.286.05:38:36.09#ibcon#read 3, iclass 39, count 0 2006.286.05:38:36.09#ibcon#about to read 4, iclass 39, count 0 2006.286.05:38:36.09#ibcon#read 4, iclass 39, count 0 2006.286.05:38:36.09#ibcon#about to read 5, iclass 39, count 0 2006.286.05:38:36.09#ibcon#read 5, iclass 39, count 0 2006.286.05:38:36.09#ibcon#about to read 6, iclass 39, count 0 2006.286.05:38:36.09#ibcon#read 6, iclass 39, count 0 2006.286.05:38:36.09#ibcon#end of sib2, iclass 39, count 0 2006.286.05:38:36.09#ibcon#*mode == 0, iclass 39, count 0 2006.286.05:38:36.09#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.05:38:36.09#ibcon#[27=USB\r\n] 2006.286.05:38:36.09#ibcon#*before write, iclass 39, count 0 2006.286.05:38:36.09#ibcon#enter sib2, iclass 39, count 0 2006.286.05:38:36.09#ibcon#flushed, iclass 39, count 0 2006.286.05:38:36.09#ibcon#about to write, iclass 39, count 0 2006.286.05:38:36.09#ibcon#wrote, iclass 39, count 0 2006.286.05:38:36.09#ibcon#about to read 3, iclass 39, count 0 2006.286.05:38:36.12#ibcon#read 3, iclass 39, count 0 2006.286.05:38:36.12#ibcon#about to read 4, iclass 39, count 0 2006.286.05:38:36.12#ibcon#read 4, iclass 39, count 0 2006.286.05:38:36.12#ibcon#about to read 5, iclass 39, count 0 2006.286.05:38:36.12#ibcon#read 5, iclass 39, count 0 2006.286.05:38:36.12#ibcon#about to read 6, iclass 39, count 0 2006.286.05:38:36.12#ibcon#read 6, iclass 39, count 0 2006.286.05:38:36.12#ibcon#end of sib2, iclass 39, count 0 2006.286.05:38:36.12#ibcon#*after write, iclass 39, count 0 2006.286.05:38:36.12#ibcon#*before return 0, iclass 39, count 0 2006.286.05:38:36.12#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:38:36.12#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:38:36.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.05:38:36.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.05:38:36.12$vck44/vblo=5,709.99 2006.286.05:38:36.12#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.05:38:36.12#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.05:38:36.12#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:36.12#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:38:36.12#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:38:36.12#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:38:36.12#ibcon#enter wrdev, iclass 3, count 0 2006.286.05:38:36.12#ibcon#first serial, iclass 3, count 0 2006.286.05:38:36.12#ibcon#enter sib2, iclass 3, count 0 2006.286.05:38:36.12#ibcon#flushed, iclass 3, count 0 2006.286.05:38:36.12#ibcon#about to write, iclass 3, count 0 2006.286.05:38:36.12#ibcon#wrote, iclass 3, count 0 2006.286.05:38:36.12#ibcon#about to read 3, iclass 3, count 0 2006.286.05:38:36.14#ibcon#read 3, iclass 3, count 0 2006.286.05:38:36.14#ibcon#about to read 4, iclass 3, count 0 2006.286.05:38:36.14#ibcon#read 4, iclass 3, count 0 2006.286.05:38:36.14#ibcon#about to read 5, iclass 3, count 0 2006.286.05:38:36.14#ibcon#read 5, iclass 3, count 0 2006.286.05:38:36.14#ibcon#about to read 6, iclass 3, count 0 2006.286.05:38:36.14#ibcon#read 6, iclass 3, count 0 2006.286.05:38:36.14#ibcon#end of sib2, iclass 3, count 0 2006.286.05:38:36.14#ibcon#*mode == 0, iclass 3, count 0 2006.286.05:38:36.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.05:38:36.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.05:38:36.14#ibcon#*before write, iclass 3, count 0 2006.286.05:38:36.14#ibcon#enter sib2, iclass 3, count 0 2006.286.05:38:36.14#ibcon#flushed, iclass 3, count 0 2006.286.05:38:36.14#ibcon#about to write, iclass 3, count 0 2006.286.05:38:36.14#ibcon#wrote, iclass 3, count 0 2006.286.05:38:36.14#ibcon#about to read 3, iclass 3, count 0 2006.286.05:38:36.18#ibcon#read 3, iclass 3, count 0 2006.286.05:38:36.18#ibcon#about to read 4, iclass 3, count 0 2006.286.05:38:36.18#ibcon#read 4, iclass 3, count 0 2006.286.05:38:36.18#ibcon#about to read 5, iclass 3, count 0 2006.286.05:38:36.18#ibcon#read 5, iclass 3, count 0 2006.286.05:38:36.18#ibcon#about to read 6, iclass 3, count 0 2006.286.05:38:36.18#ibcon#read 6, iclass 3, count 0 2006.286.05:38:36.18#ibcon#end of sib2, iclass 3, count 0 2006.286.05:38:36.18#ibcon#*after write, iclass 3, count 0 2006.286.05:38:36.18#ibcon#*before return 0, iclass 3, count 0 2006.286.05:38:36.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:38:36.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:38:36.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.05:38:36.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.05:38:36.18$vck44/vb=5,4 2006.286.05:38:36.18#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.05:38:36.18#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.05:38:36.18#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:36.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:38:36.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:38:36.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:38:36.24#ibcon#enter wrdev, iclass 5, count 2 2006.286.05:38:36.24#ibcon#first serial, iclass 5, count 2 2006.286.05:38:36.24#ibcon#enter sib2, iclass 5, count 2 2006.286.05:38:36.24#ibcon#flushed, iclass 5, count 2 2006.286.05:38:36.24#ibcon#about to write, iclass 5, count 2 2006.286.05:38:36.24#ibcon#wrote, iclass 5, count 2 2006.286.05:38:36.24#ibcon#about to read 3, iclass 5, count 2 2006.286.05:38:36.26#ibcon#read 3, iclass 5, count 2 2006.286.05:38:36.26#ibcon#about to read 4, iclass 5, count 2 2006.286.05:38:36.26#ibcon#read 4, iclass 5, count 2 2006.286.05:38:36.26#ibcon#about to read 5, iclass 5, count 2 2006.286.05:38:36.26#ibcon#read 5, iclass 5, count 2 2006.286.05:38:36.26#ibcon#about to read 6, iclass 5, count 2 2006.286.05:38:36.26#ibcon#read 6, iclass 5, count 2 2006.286.05:38:36.26#ibcon#end of sib2, iclass 5, count 2 2006.286.05:38:36.26#ibcon#*mode == 0, iclass 5, count 2 2006.286.05:38:36.26#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.05:38:36.26#ibcon#[27=AT05-04\r\n] 2006.286.05:38:36.26#ibcon#*before write, iclass 5, count 2 2006.286.05:38:36.26#ibcon#enter sib2, iclass 5, count 2 2006.286.05:38:36.26#ibcon#flushed, iclass 5, count 2 2006.286.05:38:36.26#ibcon#about to write, iclass 5, count 2 2006.286.05:38:36.26#ibcon#wrote, iclass 5, count 2 2006.286.05:38:36.26#ibcon#about to read 3, iclass 5, count 2 2006.286.05:38:36.29#ibcon#read 3, iclass 5, count 2 2006.286.05:38:36.29#ibcon#about to read 4, iclass 5, count 2 2006.286.05:38:36.29#ibcon#read 4, iclass 5, count 2 2006.286.05:38:36.29#ibcon#about to read 5, iclass 5, count 2 2006.286.05:38:36.29#ibcon#read 5, iclass 5, count 2 2006.286.05:38:36.29#ibcon#about to read 6, iclass 5, count 2 2006.286.05:38:36.29#ibcon#read 6, iclass 5, count 2 2006.286.05:38:36.29#ibcon#end of sib2, iclass 5, count 2 2006.286.05:38:36.29#ibcon#*after write, iclass 5, count 2 2006.286.05:38:36.29#ibcon#*before return 0, iclass 5, count 2 2006.286.05:38:36.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:38:36.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:38:36.29#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.05:38:36.29#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:36.29#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:38:36.41#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:38:36.41#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:38:36.41#ibcon#enter wrdev, iclass 5, count 0 2006.286.05:38:36.41#ibcon#first serial, iclass 5, count 0 2006.286.05:38:36.41#ibcon#enter sib2, iclass 5, count 0 2006.286.05:38:36.41#ibcon#flushed, iclass 5, count 0 2006.286.05:38:36.41#ibcon#about to write, iclass 5, count 0 2006.286.05:38:36.41#ibcon#wrote, iclass 5, count 0 2006.286.05:38:36.41#ibcon#about to read 3, iclass 5, count 0 2006.286.05:38:36.43#ibcon#read 3, iclass 5, count 0 2006.286.05:38:36.43#ibcon#about to read 4, iclass 5, count 0 2006.286.05:38:36.43#ibcon#read 4, iclass 5, count 0 2006.286.05:38:36.43#ibcon#about to read 5, iclass 5, count 0 2006.286.05:38:36.43#ibcon#read 5, iclass 5, count 0 2006.286.05:38:36.43#ibcon#about to read 6, iclass 5, count 0 2006.286.05:38:36.43#ibcon#read 6, iclass 5, count 0 2006.286.05:38:36.43#ibcon#end of sib2, iclass 5, count 0 2006.286.05:38:36.43#ibcon#*mode == 0, iclass 5, count 0 2006.286.05:38:36.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.05:38:36.43#ibcon#[27=USB\r\n] 2006.286.05:38:36.43#ibcon#*before write, iclass 5, count 0 2006.286.05:38:36.43#ibcon#enter sib2, iclass 5, count 0 2006.286.05:38:36.43#ibcon#flushed, iclass 5, count 0 2006.286.05:38:36.43#ibcon#about to write, iclass 5, count 0 2006.286.05:38:36.43#ibcon#wrote, iclass 5, count 0 2006.286.05:38:36.43#ibcon#about to read 3, iclass 5, count 0 2006.286.05:38:36.46#ibcon#read 3, iclass 5, count 0 2006.286.05:38:36.46#ibcon#about to read 4, iclass 5, count 0 2006.286.05:38:36.46#ibcon#read 4, iclass 5, count 0 2006.286.05:38:36.46#ibcon#about to read 5, iclass 5, count 0 2006.286.05:38:36.46#ibcon#read 5, iclass 5, count 0 2006.286.05:38:36.46#ibcon#about to read 6, iclass 5, count 0 2006.286.05:38:36.46#ibcon#read 6, iclass 5, count 0 2006.286.05:38:36.46#ibcon#end of sib2, iclass 5, count 0 2006.286.05:38:36.46#ibcon#*after write, iclass 5, count 0 2006.286.05:38:36.46#ibcon#*before return 0, iclass 5, count 0 2006.286.05:38:36.46#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:38:36.46#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:38:36.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.05:38:36.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.05:38:36.46$vck44/vblo=6,719.99 2006.286.05:38:36.46#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.05:38:36.46#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.05:38:36.46#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:36.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:38:36.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:38:36.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:38:36.46#ibcon#enter wrdev, iclass 7, count 0 2006.286.05:38:36.46#ibcon#first serial, iclass 7, count 0 2006.286.05:38:36.46#ibcon#enter sib2, iclass 7, count 0 2006.286.05:38:36.46#ibcon#flushed, iclass 7, count 0 2006.286.05:38:36.46#ibcon#about to write, iclass 7, count 0 2006.286.05:38:36.46#ibcon#wrote, iclass 7, count 0 2006.286.05:38:36.46#ibcon#about to read 3, iclass 7, count 0 2006.286.05:38:36.48#ibcon#read 3, iclass 7, count 0 2006.286.05:38:36.48#ibcon#about to read 4, iclass 7, count 0 2006.286.05:38:36.48#ibcon#read 4, iclass 7, count 0 2006.286.05:38:36.48#ibcon#about to read 5, iclass 7, count 0 2006.286.05:38:36.48#ibcon#read 5, iclass 7, count 0 2006.286.05:38:36.48#ibcon#about to read 6, iclass 7, count 0 2006.286.05:38:36.48#ibcon#read 6, iclass 7, count 0 2006.286.05:38:36.48#ibcon#end of sib2, iclass 7, count 0 2006.286.05:38:36.48#ibcon#*mode == 0, iclass 7, count 0 2006.286.05:38:36.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.05:38:36.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.05:38:36.48#ibcon#*before write, iclass 7, count 0 2006.286.05:38:36.48#ibcon#enter sib2, iclass 7, count 0 2006.286.05:38:36.48#ibcon#flushed, iclass 7, count 0 2006.286.05:38:36.48#ibcon#about to write, iclass 7, count 0 2006.286.05:38:36.48#ibcon#wrote, iclass 7, count 0 2006.286.05:38:36.48#ibcon#about to read 3, iclass 7, count 0 2006.286.05:38:36.52#ibcon#read 3, iclass 7, count 0 2006.286.05:38:36.52#ibcon#about to read 4, iclass 7, count 0 2006.286.05:38:36.52#ibcon#read 4, iclass 7, count 0 2006.286.05:38:36.52#ibcon#about to read 5, iclass 7, count 0 2006.286.05:38:36.52#ibcon#read 5, iclass 7, count 0 2006.286.05:38:36.52#ibcon#about to read 6, iclass 7, count 0 2006.286.05:38:36.52#ibcon#read 6, iclass 7, count 0 2006.286.05:38:36.52#ibcon#end of sib2, iclass 7, count 0 2006.286.05:38:36.52#ibcon#*after write, iclass 7, count 0 2006.286.05:38:36.52#ibcon#*before return 0, iclass 7, count 0 2006.286.05:38:36.52#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:38:36.52#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:38:36.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.05:38:36.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.05:38:36.52$vck44/vb=6,3 2006.286.05:38:36.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.05:38:36.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.05:38:36.57#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:36.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:38:36.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:38:36.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:38:36.57#ibcon#enter wrdev, iclass 11, count 2 2006.286.05:38:36.57#ibcon#first serial, iclass 11, count 2 2006.286.05:38:36.57#ibcon#enter sib2, iclass 11, count 2 2006.286.05:38:36.57#ibcon#flushed, iclass 11, count 2 2006.286.05:38:36.57#ibcon#about to write, iclass 11, count 2 2006.286.05:38:36.57#ibcon#wrote, iclass 11, count 2 2006.286.05:38:36.57#ibcon#about to read 3, iclass 11, count 2 2006.286.05:38:36.59#ibcon#read 3, iclass 11, count 2 2006.286.05:38:36.59#ibcon#about to read 4, iclass 11, count 2 2006.286.05:38:36.59#ibcon#read 4, iclass 11, count 2 2006.286.05:38:36.59#ibcon#about to read 5, iclass 11, count 2 2006.286.05:38:36.59#ibcon#read 5, iclass 11, count 2 2006.286.05:38:36.59#ibcon#about to read 6, iclass 11, count 2 2006.286.05:38:36.59#ibcon#read 6, iclass 11, count 2 2006.286.05:38:36.59#ibcon#end of sib2, iclass 11, count 2 2006.286.05:38:36.59#ibcon#*mode == 0, iclass 11, count 2 2006.286.05:38:36.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.05:38:36.59#ibcon#[27=AT06-03\r\n] 2006.286.05:38:36.59#ibcon#*before write, iclass 11, count 2 2006.286.05:38:36.59#ibcon#enter sib2, iclass 11, count 2 2006.286.05:38:36.59#ibcon#flushed, iclass 11, count 2 2006.286.05:38:36.59#ibcon#about to write, iclass 11, count 2 2006.286.05:38:36.59#ibcon#wrote, iclass 11, count 2 2006.286.05:38:36.59#ibcon#about to read 3, iclass 11, count 2 2006.286.05:38:36.62#ibcon#read 3, iclass 11, count 2 2006.286.05:38:36.62#ibcon#about to read 4, iclass 11, count 2 2006.286.05:38:36.62#ibcon#read 4, iclass 11, count 2 2006.286.05:38:36.62#ibcon#about to read 5, iclass 11, count 2 2006.286.05:38:36.62#ibcon#read 5, iclass 11, count 2 2006.286.05:38:36.62#ibcon#about to read 6, iclass 11, count 2 2006.286.05:38:36.62#ibcon#read 6, iclass 11, count 2 2006.286.05:38:36.62#ibcon#end of sib2, iclass 11, count 2 2006.286.05:38:36.62#ibcon#*after write, iclass 11, count 2 2006.286.05:38:36.62#ibcon#*before return 0, iclass 11, count 2 2006.286.05:38:36.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:38:36.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:38:36.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.05:38:36.62#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:36.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:38:36.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:38:36.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:38:36.74#ibcon#enter wrdev, iclass 11, count 0 2006.286.05:38:36.74#ibcon#first serial, iclass 11, count 0 2006.286.05:38:36.74#ibcon#enter sib2, iclass 11, count 0 2006.286.05:38:36.74#ibcon#flushed, iclass 11, count 0 2006.286.05:38:36.74#ibcon#about to write, iclass 11, count 0 2006.286.05:38:36.74#ibcon#wrote, iclass 11, count 0 2006.286.05:38:36.74#ibcon#about to read 3, iclass 11, count 0 2006.286.05:38:36.76#ibcon#read 3, iclass 11, count 0 2006.286.05:38:36.76#ibcon#about to read 4, iclass 11, count 0 2006.286.05:38:36.76#ibcon#read 4, iclass 11, count 0 2006.286.05:38:36.76#ibcon#about to read 5, iclass 11, count 0 2006.286.05:38:36.76#ibcon#read 5, iclass 11, count 0 2006.286.05:38:36.76#ibcon#about to read 6, iclass 11, count 0 2006.286.05:38:36.76#ibcon#read 6, iclass 11, count 0 2006.286.05:38:36.76#ibcon#end of sib2, iclass 11, count 0 2006.286.05:38:36.76#ibcon#*mode == 0, iclass 11, count 0 2006.286.05:38:36.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.05:38:36.76#ibcon#[27=USB\r\n] 2006.286.05:38:36.76#ibcon#*before write, iclass 11, count 0 2006.286.05:38:36.76#ibcon#enter sib2, iclass 11, count 0 2006.286.05:38:36.76#ibcon#flushed, iclass 11, count 0 2006.286.05:38:36.76#ibcon#about to write, iclass 11, count 0 2006.286.05:38:36.76#ibcon#wrote, iclass 11, count 0 2006.286.05:38:36.76#ibcon#about to read 3, iclass 11, count 0 2006.286.05:38:36.79#ibcon#read 3, iclass 11, count 0 2006.286.05:38:36.79#ibcon#about to read 4, iclass 11, count 0 2006.286.05:38:36.79#ibcon#read 4, iclass 11, count 0 2006.286.05:38:36.79#ibcon#about to read 5, iclass 11, count 0 2006.286.05:38:36.79#ibcon#read 5, iclass 11, count 0 2006.286.05:38:36.79#ibcon#about to read 6, iclass 11, count 0 2006.286.05:38:36.79#ibcon#read 6, iclass 11, count 0 2006.286.05:38:36.79#ibcon#end of sib2, iclass 11, count 0 2006.286.05:38:36.79#ibcon#*after write, iclass 11, count 0 2006.286.05:38:36.79#ibcon#*before return 0, iclass 11, count 0 2006.286.05:38:36.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:38:36.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:38:36.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.05:38:36.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.05:38:36.79$vck44/vblo=7,734.99 2006.286.05:38:36.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.05:38:36.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.05:38:36.79#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:36.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:38:36.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:38:36.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:38:36.79#ibcon#enter wrdev, iclass 13, count 0 2006.286.05:38:36.79#ibcon#first serial, iclass 13, count 0 2006.286.05:38:36.79#ibcon#enter sib2, iclass 13, count 0 2006.286.05:38:36.79#ibcon#flushed, iclass 13, count 0 2006.286.05:38:36.79#ibcon#about to write, iclass 13, count 0 2006.286.05:38:36.79#ibcon#wrote, iclass 13, count 0 2006.286.05:38:36.79#ibcon#about to read 3, iclass 13, count 0 2006.286.05:38:36.81#ibcon#read 3, iclass 13, count 0 2006.286.05:38:36.81#ibcon#about to read 4, iclass 13, count 0 2006.286.05:38:36.81#ibcon#read 4, iclass 13, count 0 2006.286.05:38:36.81#ibcon#about to read 5, iclass 13, count 0 2006.286.05:38:36.81#ibcon#read 5, iclass 13, count 0 2006.286.05:38:36.81#ibcon#about to read 6, iclass 13, count 0 2006.286.05:38:36.81#ibcon#read 6, iclass 13, count 0 2006.286.05:38:36.81#ibcon#end of sib2, iclass 13, count 0 2006.286.05:38:36.81#ibcon#*mode == 0, iclass 13, count 0 2006.286.05:38:36.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.05:38:36.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.05:38:36.81#ibcon#*before write, iclass 13, count 0 2006.286.05:38:36.81#ibcon#enter sib2, iclass 13, count 0 2006.286.05:38:36.81#ibcon#flushed, iclass 13, count 0 2006.286.05:38:36.81#ibcon#about to write, iclass 13, count 0 2006.286.05:38:36.81#ibcon#wrote, iclass 13, count 0 2006.286.05:38:36.81#ibcon#about to read 3, iclass 13, count 0 2006.286.05:38:36.85#ibcon#read 3, iclass 13, count 0 2006.286.05:38:36.85#ibcon#about to read 4, iclass 13, count 0 2006.286.05:38:36.85#ibcon#read 4, iclass 13, count 0 2006.286.05:38:36.85#ibcon#about to read 5, iclass 13, count 0 2006.286.05:38:36.85#ibcon#read 5, iclass 13, count 0 2006.286.05:38:36.85#ibcon#about to read 6, iclass 13, count 0 2006.286.05:38:36.85#ibcon#read 6, iclass 13, count 0 2006.286.05:38:36.85#ibcon#end of sib2, iclass 13, count 0 2006.286.05:38:36.85#ibcon#*after write, iclass 13, count 0 2006.286.05:38:36.85#ibcon#*before return 0, iclass 13, count 0 2006.286.05:38:36.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:38:36.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:38:36.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.05:38:36.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.05:38:36.85$vck44/vb=7,4 2006.286.05:38:36.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.05:38:36.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.05:38:36.85#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:36.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:38:36.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:38:36.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:38:36.91#ibcon#enter wrdev, iclass 15, count 2 2006.286.05:38:36.91#ibcon#first serial, iclass 15, count 2 2006.286.05:38:36.91#ibcon#enter sib2, iclass 15, count 2 2006.286.05:38:36.91#ibcon#flushed, iclass 15, count 2 2006.286.05:38:36.91#ibcon#about to write, iclass 15, count 2 2006.286.05:38:36.91#ibcon#wrote, iclass 15, count 2 2006.286.05:38:36.91#ibcon#about to read 3, iclass 15, count 2 2006.286.05:38:36.93#ibcon#read 3, iclass 15, count 2 2006.286.05:38:36.93#ibcon#about to read 4, iclass 15, count 2 2006.286.05:38:36.93#ibcon#read 4, iclass 15, count 2 2006.286.05:38:36.93#ibcon#about to read 5, iclass 15, count 2 2006.286.05:38:36.93#ibcon#read 5, iclass 15, count 2 2006.286.05:38:36.93#ibcon#about to read 6, iclass 15, count 2 2006.286.05:38:36.93#ibcon#read 6, iclass 15, count 2 2006.286.05:38:36.93#ibcon#end of sib2, iclass 15, count 2 2006.286.05:38:36.93#ibcon#*mode == 0, iclass 15, count 2 2006.286.05:38:36.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.05:38:36.93#ibcon#[27=AT07-04\r\n] 2006.286.05:38:36.93#ibcon#*before write, iclass 15, count 2 2006.286.05:38:36.93#ibcon#enter sib2, iclass 15, count 2 2006.286.05:38:36.93#ibcon#flushed, iclass 15, count 2 2006.286.05:38:36.93#ibcon#about to write, iclass 15, count 2 2006.286.05:38:36.93#ibcon#wrote, iclass 15, count 2 2006.286.05:38:36.93#ibcon#about to read 3, iclass 15, count 2 2006.286.05:38:36.96#ibcon#read 3, iclass 15, count 2 2006.286.05:38:36.96#ibcon#about to read 4, iclass 15, count 2 2006.286.05:38:36.96#ibcon#read 4, iclass 15, count 2 2006.286.05:38:36.96#ibcon#about to read 5, iclass 15, count 2 2006.286.05:38:36.96#ibcon#read 5, iclass 15, count 2 2006.286.05:38:36.96#ibcon#about to read 6, iclass 15, count 2 2006.286.05:38:36.96#ibcon#read 6, iclass 15, count 2 2006.286.05:38:36.96#ibcon#end of sib2, iclass 15, count 2 2006.286.05:38:36.96#ibcon#*after write, iclass 15, count 2 2006.286.05:38:36.96#ibcon#*before return 0, iclass 15, count 2 2006.286.05:38:36.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:38:36.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:38:36.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.05:38:36.96#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:36.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:38:37.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:38:37.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:38:37.08#ibcon#enter wrdev, iclass 15, count 0 2006.286.05:38:37.08#ibcon#first serial, iclass 15, count 0 2006.286.05:38:37.08#ibcon#enter sib2, iclass 15, count 0 2006.286.05:38:37.08#ibcon#flushed, iclass 15, count 0 2006.286.05:38:37.08#ibcon#about to write, iclass 15, count 0 2006.286.05:38:37.08#ibcon#wrote, iclass 15, count 0 2006.286.05:38:37.08#ibcon#about to read 3, iclass 15, count 0 2006.286.05:38:37.10#ibcon#read 3, iclass 15, count 0 2006.286.05:38:37.10#ibcon#about to read 4, iclass 15, count 0 2006.286.05:38:37.10#ibcon#read 4, iclass 15, count 0 2006.286.05:38:37.10#ibcon#about to read 5, iclass 15, count 0 2006.286.05:38:37.10#ibcon#read 5, iclass 15, count 0 2006.286.05:38:37.10#ibcon#about to read 6, iclass 15, count 0 2006.286.05:38:37.10#ibcon#read 6, iclass 15, count 0 2006.286.05:38:37.10#ibcon#end of sib2, iclass 15, count 0 2006.286.05:38:37.10#ibcon#*mode == 0, iclass 15, count 0 2006.286.05:38:37.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.05:38:37.10#ibcon#[27=USB\r\n] 2006.286.05:38:37.10#ibcon#*before write, iclass 15, count 0 2006.286.05:38:37.10#ibcon#enter sib2, iclass 15, count 0 2006.286.05:38:37.10#ibcon#flushed, iclass 15, count 0 2006.286.05:38:37.10#ibcon#about to write, iclass 15, count 0 2006.286.05:38:37.10#ibcon#wrote, iclass 15, count 0 2006.286.05:38:37.10#ibcon#about to read 3, iclass 15, count 0 2006.286.05:38:37.13#ibcon#read 3, iclass 15, count 0 2006.286.05:38:37.13#ibcon#about to read 4, iclass 15, count 0 2006.286.05:38:37.13#ibcon#read 4, iclass 15, count 0 2006.286.05:38:37.13#ibcon#about to read 5, iclass 15, count 0 2006.286.05:38:37.13#ibcon#read 5, iclass 15, count 0 2006.286.05:38:37.13#ibcon#about to read 6, iclass 15, count 0 2006.286.05:38:37.13#ibcon#read 6, iclass 15, count 0 2006.286.05:38:37.13#ibcon#end of sib2, iclass 15, count 0 2006.286.05:38:37.13#ibcon#*after write, iclass 15, count 0 2006.286.05:38:37.13#ibcon#*before return 0, iclass 15, count 0 2006.286.05:38:37.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:38:37.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:38:37.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.05:38:37.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.05:38:37.13$vck44/vblo=8,744.99 2006.286.05:38:37.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.05:38:37.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.05:38:37.13#ibcon#ireg 17 cls_cnt 0 2006.286.05:38:37.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:38:37.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:38:37.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:38:37.13#ibcon#enter wrdev, iclass 17, count 0 2006.286.05:38:37.13#ibcon#first serial, iclass 17, count 0 2006.286.05:38:37.13#ibcon#enter sib2, iclass 17, count 0 2006.286.05:38:37.13#ibcon#flushed, iclass 17, count 0 2006.286.05:38:37.13#ibcon#about to write, iclass 17, count 0 2006.286.05:38:37.13#ibcon#wrote, iclass 17, count 0 2006.286.05:38:37.13#ibcon#about to read 3, iclass 17, count 0 2006.286.05:38:37.15#ibcon#read 3, iclass 17, count 0 2006.286.05:38:37.15#ibcon#about to read 4, iclass 17, count 0 2006.286.05:38:37.15#ibcon#read 4, iclass 17, count 0 2006.286.05:38:37.15#ibcon#about to read 5, iclass 17, count 0 2006.286.05:38:37.15#ibcon#read 5, iclass 17, count 0 2006.286.05:38:37.15#ibcon#about to read 6, iclass 17, count 0 2006.286.05:38:37.15#ibcon#read 6, iclass 17, count 0 2006.286.05:38:37.15#ibcon#end of sib2, iclass 17, count 0 2006.286.05:38:37.15#ibcon#*mode == 0, iclass 17, count 0 2006.286.05:38:37.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.05:38:37.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.05:38:37.15#ibcon#*before write, iclass 17, count 0 2006.286.05:38:37.15#ibcon#enter sib2, iclass 17, count 0 2006.286.05:38:37.15#ibcon#flushed, iclass 17, count 0 2006.286.05:38:37.15#ibcon#about to write, iclass 17, count 0 2006.286.05:38:37.15#ibcon#wrote, iclass 17, count 0 2006.286.05:38:37.15#ibcon#about to read 3, iclass 17, count 0 2006.286.05:38:37.19#ibcon#read 3, iclass 17, count 0 2006.286.05:38:37.19#ibcon#about to read 4, iclass 17, count 0 2006.286.05:38:37.19#ibcon#read 4, iclass 17, count 0 2006.286.05:38:37.19#ibcon#about to read 5, iclass 17, count 0 2006.286.05:38:37.19#ibcon#read 5, iclass 17, count 0 2006.286.05:38:37.19#ibcon#about to read 6, iclass 17, count 0 2006.286.05:38:37.19#ibcon#read 6, iclass 17, count 0 2006.286.05:38:37.19#ibcon#end of sib2, iclass 17, count 0 2006.286.05:38:37.19#ibcon#*after write, iclass 17, count 0 2006.286.05:38:37.19#ibcon#*before return 0, iclass 17, count 0 2006.286.05:38:37.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:38:37.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:38:37.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.05:38:37.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.05:38:37.19$vck44/vb=8,4 2006.286.05:38:37.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.05:38:37.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.05:38:37.19#ibcon#ireg 11 cls_cnt 2 2006.286.05:38:37.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:38:37.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:38:37.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:38:37.25#ibcon#enter wrdev, iclass 19, count 2 2006.286.05:38:37.25#ibcon#first serial, iclass 19, count 2 2006.286.05:38:37.25#ibcon#enter sib2, iclass 19, count 2 2006.286.05:38:37.25#ibcon#flushed, iclass 19, count 2 2006.286.05:38:37.25#ibcon#about to write, iclass 19, count 2 2006.286.05:38:37.25#ibcon#wrote, iclass 19, count 2 2006.286.05:38:37.25#ibcon#about to read 3, iclass 19, count 2 2006.286.05:38:37.27#ibcon#read 3, iclass 19, count 2 2006.286.05:38:37.27#ibcon#about to read 4, iclass 19, count 2 2006.286.05:38:37.27#ibcon#read 4, iclass 19, count 2 2006.286.05:38:37.27#ibcon#about to read 5, iclass 19, count 2 2006.286.05:38:37.27#ibcon#read 5, iclass 19, count 2 2006.286.05:38:37.27#ibcon#about to read 6, iclass 19, count 2 2006.286.05:38:37.27#ibcon#read 6, iclass 19, count 2 2006.286.05:38:37.27#ibcon#end of sib2, iclass 19, count 2 2006.286.05:38:37.27#ibcon#*mode == 0, iclass 19, count 2 2006.286.05:38:37.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.05:38:37.27#ibcon#[27=AT08-04\r\n] 2006.286.05:38:37.27#ibcon#*before write, iclass 19, count 2 2006.286.05:38:37.27#ibcon#enter sib2, iclass 19, count 2 2006.286.05:38:37.27#ibcon#flushed, iclass 19, count 2 2006.286.05:38:37.27#ibcon#about to write, iclass 19, count 2 2006.286.05:38:37.27#ibcon#wrote, iclass 19, count 2 2006.286.05:38:37.27#ibcon#about to read 3, iclass 19, count 2 2006.286.05:38:37.30#ibcon#read 3, iclass 19, count 2 2006.286.05:38:37.30#ibcon#about to read 4, iclass 19, count 2 2006.286.05:38:37.30#ibcon#read 4, iclass 19, count 2 2006.286.05:38:37.30#ibcon#about to read 5, iclass 19, count 2 2006.286.05:38:37.30#ibcon#read 5, iclass 19, count 2 2006.286.05:38:37.30#ibcon#about to read 6, iclass 19, count 2 2006.286.05:38:37.30#ibcon#read 6, iclass 19, count 2 2006.286.05:38:37.30#ibcon#end of sib2, iclass 19, count 2 2006.286.05:38:37.30#ibcon#*after write, iclass 19, count 2 2006.286.05:38:37.30#ibcon#*before return 0, iclass 19, count 2 2006.286.05:38:37.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:38:37.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:38:37.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.05:38:37.30#ibcon#ireg 7 cls_cnt 0 2006.286.05:38:37.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:38:37.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:38:37.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:38:37.42#ibcon#enter wrdev, iclass 19, count 0 2006.286.05:38:37.42#ibcon#first serial, iclass 19, count 0 2006.286.05:38:37.42#ibcon#enter sib2, iclass 19, count 0 2006.286.05:38:37.42#ibcon#flushed, iclass 19, count 0 2006.286.05:38:37.42#ibcon#about to write, iclass 19, count 0 2006.286.05:38:37.42#ibcon#wrote, iclass 19, count 0 2006.286.05:38:37.42#ibcon#about to read 3, iclass 19, count 0 2006.286.05:38:37.44#ibcon#read 3, iclass 19, count 0 2006.286.05:38:37.44#ibcon#about to read 4, iclass 19, count 0 2006.286.05:38:37.44#ibcon#read 4, iclass 19, count 0 2006.286.05:38:37.44#ibcon#about to read 5, iclass 19, count 0 2006.286.05:38:37.44#ibcon#read 5, iclass 19, count 0 2006.286.05:38:37.44#ibcon#about to read 6, iclass 19, count 0 2006.286.05:38:37.44#ibcon#read 6, iclass 19, count 0 2006.286.05:38:37.44#ibcon#end of sib2, iclass 19, count 0 2006.286.05:38:37.44#ibcon#*mode == 0, iclass 19, count 0 2006.286.05:38:37.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.05:38:37.44#ibcon#[27=USB\r\n] 2006.286.05:38:37.44#ibcon#*before write, iclass 19, count 0 2006.286.05:38:37.44#ibcon#enter sib2, iclass 19, count 0 2006.286.05:38:37.44#ibcon#flushed, iclass 19, count 0 2006.286.05:38:37.44#ibcon#about to write, iclass 19, count 0 2006.286.05:38:37.44#ibcon#wrote, iclass 19, count 0 2006.286.05:38:37.44#ibcon#about to read 3, iclass 19, count 0 2006.286.05:38:37.47#ibcon#read 3, iclass 19, count 0 2006.286.05:38:37.47#ibcon#about to read 4, iclass 19, count 0 2006.286.05:38:37.47#ibcon#read 4, iclass 19, count 0 2006.286.05:38:37.47#ibcon#about to read 5, iclass 19, count 0 2006.286.05:38:37.47#ibcon#read 5, iclass 19, count 0 2006.286.05:38:37.47#ibcon#about to read 6, iclass 19, count 0 2006.286.05:38:37.47#ibcon#read 6, iclass 19, count 0 2006.286.05:38:37.47#ibcon#end of sib2, iclass 19, count 0 2006.286.05:38:37.47#ibcon#*after write, iclass 19, count 0 2006.286.05:38:37.47#ibcon#*before return 0, iclass 19, count 0 2006.286.05:38:37.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:38:37.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:38:37.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.05:38:37.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.05:38:37.47$vck44/vabw=wide 2006.286.05:38:37.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.05:38:37.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.05:38:37.47#ibcon#ireg 8 cls_cnt 0 2006.286.05:38:37.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:38:37.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:38:37.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:38:37.47#ibcon#enter wrdev, iclass 21, count 0 2006.286.05:38:37.47#ibcon#first serial, iclass 21, count 0 2006.286.05:38:37.47#ibcon#enter sib2, iclass 21, count 0 2006.286.05:38:37.47#ibcon#flushed, iclass 21, count 0 2006.286.05:38:37.47#ibcon#about to write, iclass 21, count 0 2006.286.05:38:37.47#ibcon#wrote, iclass 21, count 0 2006.286.05:38:37.47#ibcon#about to read 3, iclass 21, count 0 2006.286.05:38:37.49#ibcon#read 3, iclass 21, count 0 2006.286.05:38:37.49#ibcon#about to read 4, iclass 21, count 0 2006.286.05:38:37.49#ibcon#read 4, iclass 21, count 0 2006.286.05:38:37.49#ibcon#about to read 5, iclass 21, count 0 2006.286.05:38:37.49#ibcon#read 5, iclass 21, count 0 2006.286.05:38:37.49#ibcon#about to read 6, iclass 21, count 0 2006.286.05:38:37.49#ibcon#read 6, iclass 21, count 0 2006.286.05:38:37.49#ibcon#end of sib2, iclass 21, count 0 2006.286.05:38:37.49#ibcon#*mode == 0, iclass 21, count 0 2006.286.05:38:37.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.05:38:37.49#ibcon#[25=BW32\r\n] 2006.286.05:38:37.49#ibcon#*before write, iclass 21, count 0 2006.286.05:38:37.49#ibcon#enter sib2, iclass 21, count 0 2006.286.05:38:37.49#ibcon#flushed, iclass 21, count 0 2006.286.05:38:37.49#ibcon#about to write, iclass 21, count 0 2006.286.05:38:37.49#ibcon#wrote, iclass 21, count 0 2006.286.05:38:37.49#ibcon#about to read 3, iclass 21, count 0 2006.286.05:38:37.52#ibcon#read 3, iclass 21, count 0 2006.286.05:38:37.52#ibcon#about to read 4, iclass 21, count 0 2006.286.05:38:37.52#ibcon#read 4, iclass 21, count 0 2006.286.05:38:37.52#ibcon#about to read 5, iclass 21, count 0 2006.286.05:38:37.52#ibcon#read 5, iclass 21, count 0 2006.286.05:38:37.52#ibcon#about to read 6, iclass 21, count 0 2006.286.05:38:37.52#ibcon#read 6, iclass 21, count 0 2006.286.05:38:37.52#ibcon#end of sib2, iclass 21, count 0 2006.286.05:38:37.52#ibcon#*after write, iclass 21, count 0 2006.286.05:38:37.52#ibcon#*before return 0, iclass 21, count 0 2006.286.05:38:37.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:38:37.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:38:37.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.05:38:37.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.05:38:37.52$vck44/vbbw=wide 2006.286.05:38:37.73#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.286.05:38:37.73#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.286.05:38:37.73#ibcon#ireg 8 cls_cnt 0 2006.286.05:38:37.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:38:37.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:38:37.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:38:37.73#ibcon#enter wrdev, iclass 23, count 0 2006.286.05:38:37.73#ibcon#first serial, iclass 23, count 0 2006.286.05:38:37.73#ibcon#enter sib2, iclass 23, count 0 2006.286.05:38:37.73#ibcon#flushed, iclass 23, count 0 2006.286.05:38:37.73#ibcon#about to write, iclass 23, count 0 2006.286.05:38:37.73#ibcon#wrote, iclass 23, count 0 2006.286.05:38:37.73#ibcon#about to read 3, iclass 23, count 0 2006.286.05:38:37.75#ibcon#read 3, iclass 23, count 0 2006.286.05:38:37.75#ibcon#about to read 4, iclass 23, count 0 2006.286.05:38:37.75#ibcon#read 4, iclass 23, count 0 2006.286.05:38:37.75#ibcon#about to read 5, iclass 23, count 0 2006.286.05:38:37.75#ibcon#read 5, iclass 23, count 0 2006.286.05:38:37.75#ibcon#about to read 6, iclass 23, count 0 2006.286.05:38:37.75#ibcon#read 6, iclass 23, count 0 2006.286.05:38:37.75#ibcon#end of sib2, iclass 23, count 0 2006.286.05:38:37.75#ibcon#*mode == 0, iclass 23, count 0 2006.286.05:38:37.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.05:38:37.75#ibcon#[27=BW32\r\n] 2006.286.05:38:37.75#ibcon#*before write, iclass 23, count 0 2006.286.05:38:37.75#ibcon#enter sib2, iclass 23, count 0 2006.286.05:38:37.75#ibcon#flushed, iclass 23, count 0 2006.286.05:38:37.75#ibcon#about to write, iclass 23, count 0 2006.286.05:38:37.75#ibcon#wrote, iclass 23, count 0 2006.286.05:38:37.75#ibcon#about to read 3, iclass 23, count 0 2006.286.05:38:37.78#ibcon#read 3, iclass 23, count 0 2006.286.05:38:37.78#ibcon#about to read 4, iclass 23, count 0 2006.286.05:38:37.78#ibcon#read 4, iclass 23, count 0 2006.286.05:38:37.78#ibcon#about to read 5, iclass 23, count 0 2006.286.05:38:37.78#ibcon#read 5, iclass 23, count 0 2006.286.05:38:37.78#ibcon#about to read 6, iclass 23, count 0 2006.286.05:38:37.78#ibcon#read 6, iclass 23, count 0 2006.286.05:38:37.78#ibcon#end of sib2, iclass 23, count 0 2006.286.05:38:37.78#ibcon#*after write, iclass 23, count 0 2006.286.05:38:37.78#ibcon#*before return 0, iclass 23, count 0 2006.286.05:38:37.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:38:37.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.286.05:38:37.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.05:38:37.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.05:38:37.78$setupk4/ifdk4 2006.286.05:38:37.78$ifdk4/lo= 2006.286.05:38:37.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.05:38:37.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.05:38:37.78$ifdk4/patch= 2006.286.05:38:37.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.05:38:37.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.05:38:37.78$setupk4/!*+20s 2006.286.05:38:44.93#abcon#<5=/04 3.5 7.5 20.94 781015.3\r\n> 2006.286.05:38:44.95#abcon#{5=INTERFACE CLEAR} 2006.286.05:38:45.01#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:38:50.78$setupk4/"tpicd 2006.286.05:38:50.78$setupk4/echo=off 2006.286.05:38:50.78$setupk4/xlog=off 2006.286.05:38:50.78:!2006.286.05:41:48 2006.286.05:38:55.14#trakl#Source acquired 2006.286.05:38:55.14#flagr#flagr/antenna,acquired 2006.286.05:41:48.01:preob 2006.286.05:41:49.14/onsource/TRACKING 2006.286.05:41:49.14:!2006.286.05:41:58 2006.286.05:41:58.00:"tape 2006.286.05:41:58.00:"st=record 2006.286.05:41:58.00:data_valid=on 2006.286.05:41:58.00:midob 2006.286.05:41:58.14/onsource/TRACKING 2006.286.05:41:58.15/wx/20.82,1015.3,79 2006.286.05:41:58.19/cable/+6.4922E-03 2006.286.05:41:59.28/va/01,07,usb,yes,35,38 2006.286.05:41:59.28/va/02,06,usb,yes,36,36 2006.286.05:41:59.28/va/03,07,usb,yes,35,37 2006.286.05:41:59.28/va/04,06,usb,yes,37,39 2006.286.05:41:59.28/va/05,03,usb,yes,36,37 2006.286.05:41:59.28/va/06,04,usb,yes,33,32 2006.286.05:41:59.28/va/07,04,usb,yes,33,34 2006.286.05:41:59.28/va/08,03,usb,yes,34,41 2006.286.05:41:59.51/valo/01,524.99,yes,locked 2006.286.05:41:59.51/valo/02,534.99,yes,locked 2006.286.05:41:59.51/valo/03,564.99,yes,locked 2006.286.05:41:59.51/valo/04,624.99,yes,locked 2006.286.05:41:59.51/valo/05,734.99,yes,locked 2006.286.05:41:59.51/valo/06,814.99,yes,locked 2006.286.05:41:59.51/valo/07,864.99,yes,locked 2006.286.05:41:59.51/valo/08,884.99,yes,locked 2006.286.05:42:00.60/vb/01,04,usb,yes,33,31 2006.286.05:42:00.60/vb/02,05,usb,yes,31,31 2006.286.05:42:00.60/vb/03,04,usb,yes,32,35 2006.286.05:42:00.60/vb/04,05,usb,yes,32,31 2006.286.05:42:00.60/vb/05,04,usb,yes,29,31 2006.286.05:42:00.60/vb/06,03,usb,yes,45,37 2006.286.05:42:00.60/vb/07,04,usb,yes,33,36 2006.286.05:42:00.60/vb/08,04,usb,yes,30,36 2006.286.05:42:00.83/vblo/01,629.99,yes,locked 2006.286.05:42:00.83/vblo/02,634.99,yes,locked 2006.286.05:42:00.83/vblo/03,649.99,yes,locked 2006.286.05:42:00.83/vblo/04,679.99,yes,locked 2006.286.05:42:00.83/vblo/05,709.99,yes,locked 2006.286.05:42:00.83/vblo/06,719.99,yes,locked 2006.286.05:42:00.83/vblo/07,734.99,yes,locked 2006.286.05:42:00.83/vblo/08,744.99,yes,locked 2006.286.05:42:00.98/vabw/8 2006.286.05:42:01.13/vbbw/8 2006.286.05:42:01.33/xfe/off,on,12.0 2006.286.05:42:01.71/ifatt/23,28,28,28 2006.286.05:42:02.07/fmout-gps/S +2.58E-07 2006.286.05:42:02.09:!2006.286.05:44:18 2006.286.05:42:36.14#trakl#Off source 2006.286.05:42:36.14?ERROR st -7 Antenna off-source! 2006.286.05:42:36.14#trakl#az 24.976 el 13.866 azerr*cos(el) 0.0182 elerr -0.0031 2006.286.05:42:38.14#flagr#flagr/antenna,off-source 2006.286.05:42:42.14#trakl#Source re-acquired 2006.286.05:42:44.14#flagr#flagr/antenna,re-acquired 2006.286.05:44:18.00:data_valid=off 2006.286.05:44:18.00:"et 2006.286.05:44:18.00:!+3s 2006.286.05:44:21.01:"tape 2006.286.05:44:21.01:postob 2006.286.05:44:21.07/cable/+6.4924E-03 2006.286.05:44:21.07/wx/20.74,1015.3,79 2006.286.05:44:22.07/fmout-gps/S +2.61E-07 2006.286.05:44:22.07:scan_name=286-0547,jd0610,50 2006.286.05:44:22.07:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.286.05:44:22.14#flagr#flagr/antenna,new-source 2006.286.05:44:23.14:checkk5 2006.286.05:44:23.58/chk_autoobs//k5ts1/ autoobs is running! 2006.286.05:44:23.95/chk_autoobs//k5ts2/ autoobs is running! 2006.286.05:44:24.45/chk_autoobs//k5ts3/ autoobs is running! 2006.286.05:44:24.83/chk_autoobs//k5ts4/ autoobs is running! 2006.286.05:44:25.26/chk_obsdata//k5ts1/T2860541??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.286.05:44:25.88/chk_obsdata//k5ts2/T2860541??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.286.05:44:26.36/chk_obsdata//k5ts3/T2860541??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.286.05:44:26.75/chk_obsdata//k5ts4/T2860541??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.286.05:44:27.71/k5log//k5ts1_log_newline 2006.286.05:44:28.73/k5log//k5ts2_log_newline 2006.286.05:44:29.82/k5log//k5ts3_log_newline 2006.286.05:44:30.52/k5log//k5ts4_log_newline 2006.286.05:44:30.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.05:44:30.54:setupk4=1 2006.286.05:44:30.54$setupk4/echo=on 2006.286.05:44:30.54$setupk4/pcalon 2006.286.05:44:30.54$pcalon/"no phase cal control is implemented here 2006.286.05:44:30.54$setupk4/"tpicd=stop 2006.286.05:44:30.54$setupk4/"rec=synch_on 2006.286.05:44:30.54$setupk4/"rec_mode=128 2006.286.05:44:30.54$setupk4/!* 2006.286.05:44:30.54$setupk4/recpk4 2006.286.05:44:30.54$recpk4/recpatch= 2006.286.05:44:30.54$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.05:44:30.54$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.05:44:30.54$setupk4/vck44 2006.286.05:44:30.54$vck44/valo=1,524.99 2006.286.05:44:30.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.05:44:30.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.05:44:30.54#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:30.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:44:30.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:44:30.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:44:30.55#ibcon#enter wrdev, iclass 22, count 0 2006.286.05:44:30.55#ibcon#first serial, iclass 22, count 0 2006.286.05:44:30.55#ibcon#enter sib2, iclass 22, count 0 2006.286.05:44:30.55#ibcon#flushed, iclass 22, count 0 2006.286.05:44:30.55#ibcon#about to write, iclass 22, count 0 2006.286.05:44:30.55#ibcon#wrote, iclass 22, count 0 2006.286.05:44:30.55#ibcon#about to read 3, iclass 22, count 0 2006.286.05:44:30.56#ibcon#read 3, iclass 22, count 0 2006.286.05:44:30.56#ibcon#about to read 4, iclass 22, count 0 2006.286.05:44:30.56#ibcon#read 4, iclass 22, count 0 2006.286.05:44:30.56#ibcon#about to read 5, iclass 22, count 0 2006.286.05:44:30.56#ibcon#read 5, iclass 22, count 0 2006.286.05:44:30.56#ibcon#about to read 6, iclass 22, count 0 2006.286.05:44:30.56#ibcon#read 6, iclass 22, count 0 2006.286.05:44:30.56#ibcon#end of sib2, iclass 22, count 0 2006.286.05:44:30.56#ibcon#*mode == 0, iclass 22, count 0 2006.286.05:44:30.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.05:44:30.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.05:44:30.56#ibcon#*before write, iclass 22, count 0 2006.286.05:44:30.56#ibcon#enter sib2, iclass 22, count 0 2006.286.05:44:30.56#ibcon#flushed, iclass 22, count 0 2006.286.05:44:30.56#ibcon#about to write, iclass 22, count 0 2006.286.05:44:30.56#ibcon#wrote, iclass 22, count 0 2006.286.05:44:30.56#ibcon#about to read 3, iclass 22, count 0 2006.286.05:44:30.61#ibcon#read 3, iclass 22, count 0 2006.286.05:44:30.61#ibcon#about to read 4, iclass 22, count 0 2006.286.05:44:30.61#ibcon#read 4, iclass 22, count 0 2006.286.05:44:30.61#ibcon#about to read 5, iclass 22, count 0 2006.286.05:44:30.61#ibcon#read 5, iclass 22, count 0 2006.286.05:44:30.61#ibcon#about to read 6, iclass 22, count 0 2006.286.05:44:30.61#ibcon#read 6, iclass 22, count 0 2006.286.05:44:30.61#ibcon#end of sib2, iclass 22, count 0 2006.286.05:44:30.61#ibcon#*after write, iclass 22, count 0 2006.286.05:44:30.61#ibcon#*before return 0, iclass 22, count 0 2006.286.05:44:30.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:44:30.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:44:30.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.05:44:30.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.05:44:30.61$vck44/va=1,7 2006.286.05:44:30.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.05:44:30.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.05:44:30.61#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:30.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:44:30.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:44:30.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:44:30.61#ibcon#enter wrdev, iclass 24, count 2 2006.286.05:44:30.61#ibcon#first serial, iclass 24, count 2 2006.286.05:44:30.61#ibcon#enter sib2, iclass 24, count 2 2006.286.05:44:30.61#ibcon#flushed, iclass 24, count 2 2006.286.05:44:30.61#ibcon#about to write, iclass 24, count 2 2006.286.05:44:30.61#ibcon#wrote, iclass 24, count 2 2006.286.05:44:30.61#ibcon#about to read 3, iclass 24, count 2 2006.286.05:44:30.63#ibcon#read 3, iclass 24, count 2 2006.286.05:44:30.63#ibcon#about to read 4, iclass 24, count 2 2006.286.05:44:30.63#ibcon#read 4, iclass 24, count 2 2006.286.05:44:30.63#ibcon#about to read 5, iclass 24, count 2 2006.286.05:44:30.63#ibcon#read 5, iclass 24, count 2 2006.286.05:44:30.63#ibcon#about to read 6, iclass 24, count 2 2006.286.05:44:30.63#ibcon#read 6, iclass 24, count 2 2006.286.05:44:30.63#ibcon#end of sib2, iclass 24, count 2 2006.286.05:44:30.63#ibcon#*mode == 0, iclass 24, count 2 2006.286.05:44:30.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.05:44:30.63#ibcon#[25=AT01-07\r\n] 2006.286.05:44:30.63#ibcon#*before write, iclass 24, count 2 2006.286.05:44:30.63#ibcon#enter sib2, iclass 24, count 2 2006.286.05:44:30.63#ibcon#flushed, iclass 24, count 2 2006.286.05:44:30.63#ibcon#about to write, iclass 24, count 2 2006.286.05:44:30.63#ibcon#wrote, iclass 24, count 2 2006.286.05:44:30.63#ibcon#about to read 3, iclass 24, count 2 2006.286.05:44:30.66#ibcon#read 3, iclass 24, count 2 2006.286.05:44:30.66#ibcon#about to read 4, iclass 24, count 2 2006.286.05:44:30.66#ibcon#read 4, iclass 24, count 2 2006.286.05:44:30.66#ibcon#about to read 5, iclass 24, count 2 2006.286.05:44:30.66#ibcon#read 5, iclass 24, count 2 2006.286.05:44:30.66#ibcon#about to read 6, iclass 24, count 2 2006.286.05:44:30.66#ibcon#read 6, iclass 24, count 2 2006.286.05:44:30.66#ibcon#end of sib2, iclass 24, count 2 2006.286.05:44:30.66#ibcon#*after write, iclass 24, count 2 2006.286.05:44:30.66#ibcon#*before return 0, iclass 24, count 2 2006.286.05:44:30.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:44:30.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:44:30.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.05:44:30.66#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:30.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:44:30.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:44:30.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:44:30.78#ibcon#enter wrdev, iclass 24, count 0 2006.286.05:44:30.78#ibcon#first serial, iclass 24, count 0 2006.286.05:44:30.78#ibcon#enter sib2, iclass 24, count 0 2006.286.05:44:30.78#ibcon#flushed, iclass 24, count 0 2006.286.05:44:30.78#ibcon#about to write, iclass 24, count 0 2006.286.05:44:30.78#ibcon#wrote, iclass 24, count 0 2006.286.05:44:30.78#ibcon#about to read 3, iclass 24, count 0 2006.286.05:44:30.80#ibcon#read 3, iclass 24, count 0 2006.286.05:44:30.80#ibcon#about to read 4, iclass 24, count 0 2006.286.05:44:30.80#ibcon#read 4, iclass 24, count 0 2006.286.05:44:30.80#ibcon#about to read 5, iclass 24, count 0 2006.286.05:44:30.80#ibcon#read 5, iclass 24, count 0 2006.286.05:44:30.80#ibcon#about to read 6, iclass 24, count 0 2006.286.05:44:30.80#ibcon#read 6, iclass 24, count 0 2006.286.05:44:30.80#ibcon#end of sib2, iclass 24, count 0 2006.286.05:44:30.80#ibcon#*mode == 0, iclass 24, count 0 2006.286.05:44:30.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.05:44:30.80#ibcon#[25=USB\r\n] 2006.286.05:44:30.80#ibcon#*before write, iclass 24, count 0 2006.286.05:44:30.80#ibcon#enter sib2, iclass 24, count 0 2006.286.05:44:30.80#ibcon#flushed, iclass 24, count 0 2006.286.05:44:30.80#ibcon#about to write, iclass 24, count 0 2006.286.05:44:30.80#ibcon#wrote, iclass 24, count 0 2006.286.05:44:30.80#ibcon#about to read 3, iclass 24, count 0 2006.286.05:44:30.83#ibcon#read 3, iclass 24, count 0 2006.286.05:44:30.83#ibcon#about to read 4, iclass 24, count 0 2006.286.05:44:30.83#ibcon#read 4, iclass 24, count 0 2006.286.05:44:30.83#ibcon#about to read 5, iclass 24, count 0 2006.286.05:44:30.83#ibcon#read 5, iclass 24, count 0 2006.286.05:44:30.83#ibcon#about to read 6, iclass 24, count 0 2006.286.05:44:30.83#ibcon#read 6, iclass 24, count 0 2006.286.05:44:30.83#ibcon#end of sib2, iclass 24, count 0 2006.286.05:44:30.83#ibcon#*after write, iclass 24, count 0 2006.286.05:44:30.83#ibcon#*before return 0, iclass 24, count 0 2006.286.05:44:30.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:44:30.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:44:30.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.05:44:30.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.05:44:30.83$vck44/valo=2,534.99 2006.286.05:44:30.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.05:44:30.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.05:44:30.83#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:30.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:44:30.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:44:30.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:44:30.83#ibcon#enter wrdev, iclass 26, count 0 2006.286.05:44:30.83#ibcon#first serial, iclass 26, count 0 2006.286.05:44:30.83#ibcon#enter sib2, iclass 26, count 0 2006.286.05:44:30.83#ibcon#flushed, iclass 26, count 0 2006.286.05:44:30.83#ibcon#about to write, iclass 26, count 0 2006.286.05:44:30.83#ibcon#wrote, iclass 26, count 0 2006.286.05:44:30.83#ibcon#about to read 3, iclass 26, count 0 2006.286.05:44:30.85#ibcon#read 3, iclass 26, count 0 2006.286.05:44:30.85#ibcon#about to read 4, iclass 26, count 0 2006.286.05:44:30.85#ibcon#read 4, iclass 26, count 0 2006.286.05:44:30.85#ibcon#about to read 5, iclass 26, count 0 2006.286.05:44:30.85#ibcon#read 5, iclass 26, count 0 2006.286.05:44:30.85#ibcon#about to read 6, iclass 26, count 0 2006.286.05:44:30.85#ibcon#read 6, iclass 26, count 0 2006.286.05:44:30.85#ibcon#end of sib2, iclass 26, count 0 2006.286.05:44:30.85#ibcon#*mode == 0, iclass 26, count 0 2006.286.05:44:30.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.05:44:30.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.05:44:30.85#ibcon#*before write, iclass 26, count 0 2006.286.05:44:30.85#ibcon#enter sib2, iclass 26, count 0 2006.286.05:44:30.85#ibcon#flushed, iclass 26, count 0 2006.286.05:44:30.85#ibcon#about to write, iclass 26, count 0 2006.286.05:44:30.85#ibcon#wrote, iclass 26, count 0 2006.286.05:44:30.85#ibcon#about to read 3, iclass 26, count 0 2006.286.05:44:30.89#ibcon#read 3, iclass 26, count 0 2006.286.05:44:30.89#ibcon#about to read 4, iclass 26, count 0 2006.286.05:44:30.89#ibcon#read 4, iclass 26, count 0 2006.286.05:44:30.89#ibcon#about to read 5, iclass 26, count 0 2006.286.05:44:30.89#ibcon#read 5, iclass 26, count 0 2006.286.05:44:30.89#ibcon#about to read 6, iclass 26, count 0 2006.286.05:44:30.89#ibcon#read 6, iclass 26, count 0 2006.286.05:44:30.89#ibcon#end of sib2, iclass 26, count 0 2006.286.05:44:30.89#ibcon#*after write, iclass 26, count 0 2006.286.05:44:30.89#ibcon#*before return 0, iclass 26, count 0 2006.286.05:44:30.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:44:30.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:44:30.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.05:44:30.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.05:44:30.89$vck44/va=2,6 2006.286.05:44:30.89#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.286.05:44:30.89#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.286.05:44:30.89#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:30.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:44:30.90#abcon#<5=/04 3.8 7.5 20.74 791015.3\r\n> 2006.286.05:44:30.92#abcon#{5=INTERFACE CLEAR} 2006.286.05:44:30.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:44:30.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:44:30.95#ibcon#enter wrdev, iclass 29, count 2 2006.286.05:44:30.95#ibcon#first serial, iclass 29, count 2 2006.286.05:44:30.95#ibcon#enter sib2, iclass 29, count 2 2006.286.05:44:30.95#ibcon#flushed, iclass 29, count 2 2006.286.05:44:30.95#ibcon#about to write, iclass 29, count 2 2006.286.05:44:30.95#ibcon#wrote, iclass 29, count 2 2006.286.05:44:30.95#ibcon#about to read 3, iclass 29, count 2 2006.286.05:44:30.97#ibcon#read 3, iclass 29, count 2 2006.286.05:44:30.97#ibcon#about to read 4, iclass 29, count 2 2006.286.05:44:30.97#ibcon#read 4, iclass 29, count 2 2006.286.05:44:30.97#ibcon#about to read 5, iclass 29, count 2 2006.286.05:44:30.97#ibcon#read 5, iclass 29, count 2 2006.286.05:44:30.97#ibcon#about to read 6, iclass 29, count 2 2006.286.05:44:30.97#ibcon#read 6, iclass 29, count 2 2006.286.05:44:30.97#ibcon#end of sib2, iclass 29, count 2 2006.286.05:44:30.97#ibcon#*mode == 0, iclass 29, count 2 2006.286.05:44:30.97#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.286.05:44:30.97#ibcon#[25=AT02-06\r\n] 2006.286.05:44:30.97#ibcon#*before write, iclass 29, count 2 2006.286.05:44:30.97#ibcon#enter sib2, iclass 29, count 2 2006.286.05:44:30.97#ibcon#flushed, iclass 29, count 2 2006.286.05:44:30.97#ibcon#about to write, iclass 29, count 2 2006.286.05:44:30.97#ibcon#wrote, iclass 29, count 2 2006.286.05:44:30.97#ibcon#about to read 3, iclass 29, count 2 2006.286.05:44:30.98#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:44:31.00#ibcon#read 3, iclass 29, count 2 2006.286.05:44:31.00#ibcon#about to read 4, iclass 29, count 2 2006.286.05:44:31.00#ibcon#read 4, iclass 29, count 2 2006.286.05:44:31.00#ibcon#about to read 5, iclass 29, count 2 2006.286.05:44:31.00#ibcon#read 5, iclass 29, count 2 2006.286.05:44:31.00#ibcon#about to read 6, iclass 29, count 2 2006.286.05:44:31.00#ibcon#read 6, iclass 29, count 2 2006.286.05:44:31.00#ibcon#end of sib2, iclass 29, count 2 2006.286.05:44:31.00#ibcon#*after write, iclass 29, count 2 2006.286.05:44:31.00#ibcon#*before return 0, iclass 29, count 2 2006.286.05:44:31.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:44:31.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.286.05:44:31.00#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.286.05:44:31.00#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:31.00#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:44:31.12#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:44:31.12#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:44:31.12#ibcon#enter wrdev, iclass 29, count 0 2006.286.05:44:31.12#ibcon#first serial, iclass 29, count 0 2006.286.05:44:31.12#ibcon#enter sib2, iclass 29, count 0 2006.286.05:44:31.12#ibcon#flushed, iclass 29, count 0 2006.286.05:44:31.12#ibcon#about to write, iclass 29, count 0 2006.286.05:44:31.12#ibcon#wrote, iclass 29, count 0 2006.286.05:44:31.12#ibcon#about to read 3, iclass 29, count 0 2006.286.05:44:31.14#ibcon#read 3, iclass 29, count 0 2006.286.05:44:31.48#ibcon#about to read 4, iclass 29, count 0 2006.286.05:44:31.48#ibcon#read 4, iclass 29, count 0 2006.286.05:44:31.48#ibcon#about to read 5, iclass 29, count 0 2006.286.05:44:31.48#ibcon#read 5, iclass 29, count 0 2006.286.05:44:31.48#ibcon#about to read 6, iclass 29, count 0 2006.286.05:44:31.48#ibcon#read 6, iclass 29, count 0 2006.286.05:44:31.48#ibcon#end of sib2, iclass 29, count 0 2006.286.05:44:31.48#ibcon#*mode == 0, iclass 29, count 0 2006.286.05:44:31.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.05:44:31.48#ibcon#[25=USB\r\n] 2006.286.05:44:31.48#ibcon#*before write, iclass 29, count 0 2006.286.05:44:31.48#ibcon#enter sib2, iclass 29, count 0 2006.286.05:44:31.48#ibcon#flushed, iclass 29, count 0 2006.286.05:44:31.48#ibcon#about to write, iclass 29, count 0 2006.286.05:44:31.48#ibcon#wrote, iclass 29, count 0 2006.286.05:44:31.48#ibcon#about to read 3, iclass 29, count 0 2006.286.05:44:31.50#ibcon#read 3, iclass 29, count 0 2006.286.05:44:31.50#ibcon#about to read 4, iclass 29, count 0 2006.286.05:44:31.50#ibcon#read 4, iclass 29, count 0 2006.286.05:44:31.50#ibcon#about to read 5, iclass 29, count 0 2006.286.05:44:31.50#ibcon#read 5, iclass 29, count 0 2006.286.05:44:31.50#ibcon#about to read 6, iclass 29, count 0 2006.286.05:44:31.50#ibcon#read 6, iclass 29, count 0 2006.286.05:44:31.50#ibcon#end of sib2, iclass 29, count 0 2006.286.05:44:31.50#ibcon#*after write, iclass 29, count 0 2006.286.05:44:31.50#ibcon#*before return 0, iclass 29, count 0 2006.286.05:44:31.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:44:31.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.286.05:44:31.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.05:44:31.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.05:44:31.50$vck44/valo=3,564.99 2006.286.05:44:31.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.05:44:31.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.05:44:31.50#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:31.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:44:31.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:44:31.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:44:31.50#ibcon#enter wrdev, iclass 34, count 0 2006.286.05:44:31.50#ibcon#first serial, iclass 34, count 0 2006.286.05:44:31.50#ibcon#enter sib2, iclass 34, count 0 2006.286.05:44:31.50#ibcon#flushed, iclass 34, count 0 2006.286.05:44:31.50#ibcon#about to write, iclass 34, count 0 2006.286.05:44:31.50#ibcon#wrote, iclass 34, count 0 2006.286.05:44:31.50#ibcon#about to read 3, iclass 34, count 0 2006.286.05:44:31.52#ibcon#read 3, iclass 34, count 0 2006.286.05:44:31.52#ibcon#about to read 4, iclass 34, count 0 2006.286.05:44:31.52#ibcon#read 4, iclass 34, count 0 2006.286.05:44:31.52#ibcon#about to read 5, iclass 34, count 0 2006.286.05:44:31.52#ibcon#read 5, iclass 34, count 0 2006.286.05:44:31.52#ibcon#about to read 6, iclass 34, count 0 2006.286.05:44:31.52#ibcon#read 6, iclass 34, count 0 2006.286.05:44:31.52#ibcon#end of sib2, iclass 34, count 0 2006.286.05:44:31.52#ibcon#*mode == 0, iclass 34, count 0 2006.286.05:44:31.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.05:44:31.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.05:44:31.52#ibcon#*before write, iclass 34, count 0 2006.286.05:44:31.52#ibcon#enter sib2, iclass 34, count 0 2006.286.05:44:31.52#ibcon#flushed, iclass 34, count 0 2006.286.05:44:31.52#ibcon#about to write, iclass 34, count 0 2006.286.05:44:31.52#ibcon#wrote, iclass 34, count 0 2006.286.05:44:31.52#ibcon#about to read 3, iclass 34, count 0 2006.286.05:44:31.56#ibcon#read 3, iclass 34, count 0 2006.286.05:44:31.56#ibcon#about to read 4, iclass 34, count 0 2006.286.05:44:31.56#ibcon#read 4, iclass 34, count 0 2006.286.05:44:31.56#ibcon#about to read 5, iclass 34, count 0 2006.286.05:44:31.56#ibcon#read 5, iclass 34, count 0 2006.286.05:44:31.56#ibcon#about to read 6, iclass 34, count 0 2006.286.05:44:31.56#ibcon#read 6, iclass 34, count 0 2006.286.05:44:31.56#ibcon#end of sib2, iclass 34, count 0 2006.286.05:44:31.56#ibcon#*after write, iclass 34, count 0 2006.286.05:44:31.56#ibcon#*before return 0, iclass 34, count 0 2006.286.05:44:31.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:44:31.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:44:31.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.05:44:31.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.05:44:31.56$vck44/va=3,7 2006.286.05:44:31.56#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.05:44:31.56#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.05:44:31.56#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:31.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:44:31.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:44:31.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:44:31.62#ibcon#enter wrdev, iclass 36, count 2 2006.286.05:44:31.62#ibcon#first serial, iclass 36, count 2 2006.286.05:44:31.62#ibcon#enter sib2, iclass 36, count 2 2006.286.05:44:31.62#ibcon#flushed, iclass 36, count 2 2006.286.05:44:31.62#ibcon#about to write, iclass 36, count 2 2006.286.05:44:31.62#ibcon#wrote, iclass 36, count 2 2006.286.05:44:31.62#ibcon#about to read 3, iclass 36, count 2 2006.286.05:44:31.64#ibcon#read 3, iclass 36, count 2 2006.286.05:44:31.64#ibcon#about to read 4, iclass 36, count 2 2006.286.05:44:31.64#ibcon#read 4, iclass 36, count 2 2006.286.05:44:31.64#ibcon#about to read 5, iclass 36, count 2 2006.286.05:44:31.64#ibcon#read 5, iclass 36, count 2 2006.286.05:44:31.64#ibcon#about to read 6, iclass 36, count 2 2006.286.05:44:31.64#ibcon#read 6, iclass 36, count 2 2006.286.05:44:31.64#ibcon#end of sib2, iclass 36, count 2 2006.286.05:44:31.64#ibcon#*mode == 0, iclass 36, count 2 2006.286.05:44:31.64#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.05:44:31.64#ibcon#[25=AT03-07\r\n] 2006.286.05:44:31.64#ibcon#*before write, iclass 36, count 2 2006.286.05:44:31.64#ibcon#enter sib2, iclass 36, count 2 2006.286.05:44:31.64#ibcon#flushed, iclass 36, count 2 2006.286.05:44:31.64#ibcon#about to write, iclass 36, count 2 2006.286.05:44:31.64#ibcon#wrote, iclass 36, count 2 2006.286.05:44:31.64#ibcon#about to read 3, iclass 36, count 2 2006.286.05:44:31.67#ibcon#read 3, iclass 36, count 2 2006.286.05:44:31.67#ibcon#about to read 4, iclass 36, count 2 2006.286.05:44:31.67#ibcon#read 4, iclass 36, count 2 2006.286.05:44:31.67#ibcon#about to read 5, iclass 36, count 2 2006.286.05:44:31.67#ibcon#read 5, iclass 36, count 2 2006.286.05:44:31.67#ibcon#about to read 6, iclass 36, count 2 2006.286.05:44:31.67#ibcon#read 6, iclass 36, count 2 2006.286.05:44:31.67#ibcon#end of sib2, iclass 36, count 2 2006.286.05:44:31.67#ibcon#*after write, iclass 36, count 2 2006.286.05:44:31.67#ibcon#*before return 0, iclass 36, count 2 2006.286.05:44:31.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:44:31.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:44:31.67#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.05:44:31.67#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:31.67#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:44:31.79#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:44:31.79#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:44:31.79#ibcon#enter wrdev, iclass 36, count 0 2006.286.05:44:31.79#ibcon#first serial, iclass 36, count 0 2006.286.05:44:31.79#ibcon#enter sib2, iclass 36, count 0 2006.286.05:44:31.79#ibcon#flushed, iclass 36, count 0 2006.286.05:44:31.79#ibcon#about to write, iclass 36, count 0 2006.286.05:44:31.79#ibcon#wrote, iclass 36, count 0 2006.286.05:44:31.79#ibcon#about to read 3, iclass 36, count 0 2006.286.05:44:31.81#ibcon#read 3, iclass 36, count 0 2006.286.05:44:31.81#ibcon#about to read 4, iclass 36, count 0 2006.286.05:44:31.81#ibcon#read 4, iclass 36, count 0 2006.286.05:44:31.81#ibcon#about to read 5, iclass 36, count 0 2006.286.05:44:31.81#ibcon#read 5, iclass 36, count 0 2006.286.05:44:31.81#ibcon#about to read 6, iclass 36, count 0 2006.286.05:44:31.81#ibcon#read 6, iclass 36, count 0 2006.286.05:44:31.81#ibcon#end of sib2, iclass 36, count 0 2006.286.05:44:31.81#ibcon#*mode == 0, iclass 36, count 0 2006.286.05:44:31.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.05:44:31.81#ibcon#[25=USB\r\n] 2006.286.05:44:31.81#ibcon#*before write, iclass 36, count 0 2006.286.05:44:31.81#ibcon#enter sib2, iclass 36, count 0 2006.286.05:44:31.81#ibcon#flushed, iclass 36, count 0 2006.286.05:44:31.81#ibcon#about to write, iclass 36, count 0 2006.286.05:44:31.81#ibcon#wrote, iclass 36, count 0 2006.286.05:44:31.81#ibcon#about to read 3, iclass 36, count 0 2006.286.05:44:31.84#ibcon#read 3, iclass 36, count 0 2006.286.05:44:31.84#ibcon#about to read 4, iclass 36, count 0 2006.286.05:44:32.03#ibcon#read 4, iclass 36, count 0 2006.286.05:44:32.03#ibcon#about to read 5, iclass 36, count 0 2006.286.05:44:32.03#ibcon#read 5, iclass 36, count 0 2006.286.05:44:32.03#ibcon#about to read 6, iclass 36, count 0 2006.286.05:44:32.03#ibcon#read 6, iclass 36, count 0 2006.286.05:44:32.03#ibcon#end of sib2, iclass 36, count 0 2006.286.05:44:32.03#ibcon#*after write, iclass 36, count 0 2006.286.05:44:32.03#ibcon#*before return 0, iclass 36, count 0 2006.286.05:44:32.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:44:32.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:44:32.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.05:44:32.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.05:44:32.03$vck44/valo=4,624.99 2006.286.05:44:32.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.05:44:32.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.05:44:32.03#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:32.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:44:32.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:44:32.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:44:32.03#ibcon#enter wrdev, iclass 38, count 0 2006.286.05:44:32.03#ibcon#first serial, iclass 38, count 0 2006.286.05:44:32.03#ibcon#enter sib2, iclass 38, count 0 2006.286.05:44:32.03#ibcon#flushed, iclass 38, count 0 2006.286.05:44:32.03#ibcon#about to write, iclass 38, count 0 2006.286.05:44:32.03#ibcon#wrote, iclass 38, count 0 2006.286.05:44:32.03#ibcon#about to read 3, iclass 38, count 0 2006.286.05:44:32.04#ibcon#read 3, iclass 38, count 0 2006.286.05:44:32.04#ibcon#about to read 4, iclass 38, count 0 2006.286.05:44:32.04#ibcon#read 4, iclass 38, count 0 2006.286.05:44:32.04#ibcon#about to read 5, iclass 38, count 0 2006.286.05:44:32.04#ibcon#read 5, iclass 38, count 0 2006.286.05:44:32.04#ibcon#about to read 6, iclass 38, count 0 2006.286.05:44:32.04#ibcon#read 6, iclass 38, count 0 2006.286.05:44:32.04#ibcon#end of sib2, iclass 38, count 0 2006.286.05:44:32.04#ibcon#*mode == 0, iclass 38, count 0 2006.286.05:44:32.04#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.05:44:32.04#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.05:44:32.04#ibcon#*before write, iclass 38, count 0 2006.286.05:44:32.04#ibcon#enter sib2, iclass 38, count 0 2006.286.05:44:32.04#ibcon#flushed, iclass 38, count 0 2006.286.05:44:32.04#ibcon#about to write, iclass 38, count 0 2006.286.05:44:32.04#ibcon#wrote, iclass 38, count 0 2006.286.05:44:32.04#ibcon#about to read 3, iclass 38, count 0 2006.286.05:44:32.08#ibcon#read 3, iclass 38, count 0 2006.286.05:44:32.08#ibcon#about to read 4, iclass 38, count 0 2006.286.05:44:32.08#ibcon#read 4, iclass 38, count 0 2006.286.05:44:32.08#ibcon#about to read 5, iclass 38, count 0 2006.286.05:44:32.08#ibcon#read 5, iclass 38, count 0 2006.286.05:44:32.08#ibcon#about to read 6, iclass 38, count 0 2006.286.05:44:32.08#ibcon#read 6, iclass 38, count 0 2006.286.05:44:32.08#ibcon#end of sib2, iclass 38, count 0 2006.286.05:44:32.08#ibcon#*after write, iclass 38, count 0 2006.286.05:44:32.08#ibcon#*before return 0, iclass 38, count 0 2006.286.05:44:32.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:44:32.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:44:32.08#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.05:44:32.08#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.05:44:32.08$vck44/va=4,6 2006.286.05:44:32.08#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.05:44:32.08#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.05:44:32.08#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:32.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:44:32.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:44:32.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:44:32.15#ibcon#enter wrdev, iclass 40, count 2 2006.286.05:44:32.15#ibcon#first serial, iclass 40, count 2 2006.286.05:44:32.15#ibcon#enter sib2, iclass 40, count 2 2006.286.05:44:32.15#ibcon#flushed, iclass 40, count 2 2006.286.05:44:32.15#ibcon#about to write, iclass 40, count 2 2006.286.05:44:32.15#ibcon#wrote, iclass 40, count 2 2006.286.05:44:32.15#ibcon#about to read 3, iclass 40, count 2 2006.286.05:44:32.17#ibcon#read 3, iclass 40, count 2 2006.286.05:44:32.17#ibcon#about to read 4, iclass 40, count 2 2006.286.05:44:32.17#ibcon#read 4, iclass 40, count 2 2006.286.05:44:32.17#ibcon#about to read 5, iclass 40, count 2 2006.286.05:44:32.17#ibcon#read 5, iclass 40, count 2 2006.286.05:44:32.17#ibcon#about to read 6, iclass 40, count 2 2006.286.05:44:32.17#ibcon#read 6, iclass 40, count 2 2006.286.05:44:32.17#ibcon#end of sib2, iclass 40, count 2 2006.286.05:44:32.17#ibcon#*mode == 0, iclass 40, count 2 2006.286.05:44:32.17#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.05:44:32.17#ibcon#[25=AT04-06\r\n] 2006.286.05:44:32.17#ibcon#*before write, iclass 40, count 2 2006.286.05:44:32.17#ibcon#enter sib2, iclass 40, count 2 2006.286.05:44:32.17#ibcon#flushed, iclass 40, count 2 2006.286.05:44:32.17#ibcon#about to write, iclass 40, count 2 2006.286.05:44:32.17#ibcon#wrote, iclass 40, count 2 2006.286.05:44:32.17#ibcon#about to read 3, iclass 40, count 2 2006.286.05:44:32.20#ibcon#read 3, iclass 40, count 2 2006.286.05:44:32.20#ibcon#about to read 4, iclass 40, count 2 2006.286.05:44:32.20#ibcon#read 4, iclass 40, count 2 2006.286.05:44:32.20#ibcon#about to read 5, iclass 40, count 2 2006.286.05:44:32.20#ibcon#read 5, iclass 40, count 2 2006.286.05:44:32.20#ibcon#about to read 6, iclass 40, count 2 2006.286.05:44:32.20#ibcon#read 6, iclass 40, count 2 2006.286.05:44:32.20#ibcon#end of sib2, iclass 40, count 2 2006.286.05:44:32.20#ibcon#*after write, iclass 40, count 2 2006.286.05:44:32.20#ibcon#*before return 0, iclass 40, count 2 2006.286.05:44:32.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:44:32.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:44:32.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.05:44:32.20#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:32.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:44:32.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:44:32.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:44:32.32#ibcon#enter wrdev, iclass 40, count 0 2006.286.05:44:32.32#ibcon#first serial, iclass 40, count 0 2006.286.05:44:32.32#ibcon#enter sib2, iclass 40, count 0 2006.286.05:44:32.32#ibcon#flushed, iclass 40, count 0 2006.286.05:44:32.32#ibcon#about to write, iclass 40, count 0 2006.286.05:44:32.32#ibcon#wrote, iclass 40, count 0 2006.286.05:44:32.32#ibcon#about to read 3, iclass 40, count 0 2006.286.05:44:32.34#ibcon#read 3, iclass 40, count 0 2006.286.05:44:32.34#ibcon#about to read 4, iclass 40, count 0 2006.286.05:44:32.34#ibcon#read 4, iclass 40, count 0 2006.286.05:44:32.34#ibcon#about to read 5, iclass 40, count 0 2006.286.05:44:32.34#ibcon#read 5, iclass 40, count 0 2006.286.05:44:32.34#ibcon#about to read 6, iclass 40, count 0 2006.286.05:44:32.34#ibcon#read 6, iclass 40, count 0 2006.286.05:44:32.34#ibcon#end of sib2, iclass 40, count 0 2006.286.05:44:32.34#ibcon#*mode == 0, iclass 40, count 0 2006.286.05:44:32.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.05:44:32.34#ibcon#[25=USB\r\n] 2006.286.05:44:32.34#ibcon#*before write, iclass 40, count 0 2006.286.05:44:32.34#ibcon#enter sib2, iclass 40, count 0 2006.286.05:44:32.34#ibcon#flushed, iclass 40, count 0 2006.286.05:44:32.34#ibcon#about to write, iclass 40, count 0 2006.286.05:44:32.34#ibcon#wrote, iclass 40, count 0 2006.286.05:44:32.34#ibcon#about to read 3, iclass 40, count 0 2006.286.05:44:32.37#ibcon#read 3, iclass 40, count 0 2006.286.05:44:32.37#ibcon#about to read 4, iclass 40, count 0 2006.286.05:44:32.37#ibcon#read 4, iclass 40, count 0 2006.286.05:44:32.37#ibcon#about to read 5, iclass 40, count 0 2006.286.05:44:32.37#ibcon#read 5, iclass 40, count 0 2006.286.05:44:32.37#ibcon#about to read 6, iclass 40, count 0 2006.286.05:44:32.37#ibcon#read 6, iclass 40, count 0 2006.286.05:44:32.37#ibcon#end of sib2, iclass 40, count 0 2006.286.05:44:32.37#ibcon#*after write, iclass 40, count 0 2006.286.05:44:32.37#ibcon#*before return 0, iclass 40, count 0 2006.286.05:44:32.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:44:32.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:44:32.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.05:44:32.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.05:44:32.37$vck44/valo=5,734.99 2006.286.05:44:32.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.05:44:32.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.05:44:32.37#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:32.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:44:32.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:44:32.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:44:32.37#ibcon#enter wrdev, iclass 4, count 0 2006.286.05:44:32.37#ibcon#first serial, iclass 4, count 0 2006.286.05:44:32.37#ibcon#enter sib2, iclass 4, count 0 2006.286.05:44:32.37#ibcon#flushed, iclass 4, count 0 2006.286.05:44:32.37#ibcon#about to write, iclass 4, count 0 2006.286.05:44:32.37#ibcon#wrote, iclass 4, count 0 2006.286.05:44:32.37#ibcon#about to read 3, iclass 4, count 0 2006.286.05:44:32.39#ibcon#read 3, iclass 4, count 0 2006.286.05:44:32.39#ibcon#about to read 4, iclass 4, count 0 2006.286.05:44:32.39#ibcon#read 4, iclass 4, count 0 2006.286.05:44:32.39#ibcon#about to read 5, iclass 4, count 0 2006.286.05:44:32.39#ibcon#read 5, iclass 4, count 0 2006.286.05:44:32.39#ibcon#about to read 6, iclass 4, count 0 2006.286.05:44:32.39#ibcon#read 6, iclass 4, count 0 2006.286.05:44:32.39#ibcon#end of sib2, iclass 4, count 0 2006.286.05:44:32.39#ibcon#*mode == 0, iclass 4, count 0 2006.286.05:44:32.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.05:44:32.39#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.05:44:32.39#ibcon#*before write, iclass 4, count 0 2006.286.05:44:32.39#ibcon#enter sib2, iclass 4, count 0 2006.286.05:44:32.39#ibcon#flushed, iclass 4, count 0 2006.286.05:44:32.39#ibcon#about to write, iclass 4, count 0 2006.286.05:44:32.39#ibcon#wrote, iclass 4, count 0 2006.286.05:44:32.39#ibcon#about to read 3, iclass 4, count 0 2006.286.05:44:32.43#ibcon#read 3, iclass 4, count 0 2006.286.05:44:32.43#ibcon#about to read 4, iclass 4, count 0 2006.286.05:44:32.43#ibcon#read 4, iclass 4, count 0 2006.286.05:44:32.43#ibcon#about to read 5, iclass 4, count 0 2006.286.05:44:32.43#ibcon#read 5, iclass 4, count 0 2006.286.05:44:32.43#ibcon#about to read 6, iclass 4, count 0 2006.286.05:44:32.43#ibcon#read 6, iclass 4, count 0 2006.286.05:44:32.43#ibcon#end of sib2, iclass 4, count 0 2006.286.05:44:32.43#ibcon#*after write, iclass 4, count 0 2006.286.05:44:32.43#ibcon#*before return 0, iclass 4, count 0 2006.286.05:44:32.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:44:32.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:44:32.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.05:44:32.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.05:44:32.43$vck44/va=5,3 2006.286.05:44:32.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.05:44:32.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.05:44:32.43#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:32.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:44:32.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:44:32.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:44:32.49#ibcon#enter wrdev, iclass 6, count 2 2006.286.05:44:32.49#ibcon#first serial, iclass 6, count 2 2006.286.05:44:32.49#ibcon#enter sib2, iclass 6, count 2 2006.286.05:44:32.49#ibcon#flushed, iclass 6, count 2 2006.286.05:44:32.49#ibcon#about to write, iclass 6, count 2 2006.286.05:44:32.49#ibcon#wrote, iclass 6, count 2 2006.286.05:44:32.49#ibcon#about to read 3, iclass 6, count 2 2006.286.05:44:32.51#ibcon#read 3, iclass 6, count 2 2006.286.05:44:32.51#ibcon#about to read 4, iclass 6, count 2 2006.286.05:44:32.51#ibcon#read 4, iclass 6, count 2 2006.286.05:44:32.51#ibcon#about to read 5, iclass 6, count 2 2006.286.05:44:32.51#ibcon#read 5, iclass 6, count 2 2006.286.05:44:32.51#ibcon#about to read 6, iclass 6, count 2 2006.286.05:44:32.51#ibcon#read 6, iclass 6, count 2 2006.286.05:44:32.51#ibcon#end of sib2, iclass 6, count 2 2006.286.05:44:32.51#ibcon#*mode == 0, iclass 6, count 2 2006.286.05:44:32.51#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.05:44:32.51#ibcon#[25=AT05-03\r\n] 2006.286.05:44:32.51#ibcon#*before write, iclass 6, count 2 2006.286.05:44:32.51#ibcon#enter sib2, iclass 6, count 2 2006.286.05:44:32.51#ibcon#flushed, iclass 6, count 2 2006.286.05:44:32.51#ibcon#about to write, iclass 6, count 2 2006.286.05:44:32.51#ibcon#wrote, iclass 6, count 2 2006.286.05:44:32.51#ibcon#about to read 3, iclass 6, count 2 2006.286.05:44:32.54#ibcon#read 3, iclass 6, count 2 2006.286.05:44:32.54#ibcon#about to read 4, iclass 6, count 2 2006.286.05:44:32.54#ibcon#read 4, iclass 6, count 2 2006.286.05:44:32.54#ibcon#about to read 5, iclass 6, count 2 2006.286.05:44:32.54#ibcon#read 5, iclass 6, count 2 2006.286.05:44:32.54#ibcon#about to read 6, iclass 6, count 2 2006.286.05:44:32.54#ibcon#read 6, iclass 6, count 2 2006.286.05:44:32.54#ibcon#end of sib2, iclass 6, count 2 2006.286.05:44:32.54#ibcon#*after write, iclass 6, count 2 2006.286.05:44:32.54#ibcon#*before return 0, iclass 6, count 2 2006.286.05:44:32.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:44:32.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:44:32.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.05:44:32.54#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:32.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:44:32.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:44:32.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:44:32.66#ibcon#enter wrdev, iclass 6, count 0 2006.286.05:44:32.66#ibcon#first serial, iclass 6, count 0 2006.286.05:44:32.66#ibcon#enter sib2, iclass 6, count 0 2006.286.05:44:32.66#ibcon#flushed, iclass 6, count 0 2006.286.05:44:32.66#ibcon#about to write, iclass 6, count 0 2006.286.05:44:32.66#ibcon#wrote, iclass 6, count 0 2006.286.05:44:32.66#ibcon#about to read 3, iclass 6, count 0 2006.286.05:44:32.68#ibcon#read 3, iclass 6, count 0 2006.286.05:44:32.68#ibcon#about to read 4, iclass 6, count 0 2006.286.05:44:32.68#ibcon#read 4, iclass 6, count 0 2006.286.05:44:32.68#ibcon#about to read 5, iclass 6, count 0 2006.286.05:44:32.68#ibcon#read 5, iclass 6, count 0 2006.286.05:44:32.68#ibcon#about to read 6, iclass 6, count 0 2006.286.05:44:32.68#ibcon#read 6, iclass 6, count 0 2006.286.05:44:32.68#ibcon#end of sib2, iclass 6, count 0 2006.286.05:44:32.68#ibcon#*mode == 0, iclass 6, count 0 2006.286.05:44:32.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.05:44:32.68#ibcon#[25=USB\r\n] 2006.286.05:44:32.68#ibcon#*before write, iclass 6, count 0 2006.286.05:44:32.68#ibcon#enter sib2, iclass 6, count 0 2006.286.05:44:32.68#ibcon#flushed, iclass 6, count 0 2006.286.05:44:32.68#ibcon#about to write, iclass 6, count 0 2006.286.05:44:32.68#ibcon#wrote, iclass 6, count 0 2006.286.05:44:32.68#ibcon#about to read 3, iclass 6, count 0 2006.286.05:44:32.71#ibcon#read 3, iclass 6, count 0 2006.286.05:44:32.71#ibcon#about to read 4, iclass 6, count 0 2006.286.05:44:32.71#ibcon#read 4, iclass 6, count 0 2006.286.05:44:32.71#ibcon#about to read 5, iclass 6, count 0 2006.286.05:44:32.71#ibcon#read 5, iclass 6, count 0 2006.286.05:44:32.71#ibcon#about to read 6, iclass 6, count 0 2006.286.05:44:32.71#ibcon#read 6, iclass 6, count 0 2006.286.05:44:32.71#ibcon#end of sib2, iclass 6, count 0 2006.286.05:44:32.71#ibcon#*after write, iclass 6, count 0 2006.286.05:44:32.71#ibcon#*before return 0, iclass 6, count 0 2006.286.05:44:32.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:44:32.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:44:32.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.05:44:32.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.05:44:32.71$vck44/valo=6,814.99 2006.286.05:44:32.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.05:44:32.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.05:44:32.71#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:32.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:44:32.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:44:32.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:44:32.71#ibcon#enter wrdev, iclass 10, count 0 2006.286.05:44:32.71#ibcon#first serial, iclass 10, count 0 2006.286.05:44:32.71#ibcon#enter sib2, iclass 10, count 0 2006.286.05:44:32.71#ibcon#flushed, iclass 10, count 0 2006.286.05:44:32.71#ibcon#about to write, iclass 10, count 0 2006.286.05:44:32.71#ibcon#wrote, iclass 10, count 0 2006.286.05:44:32.71#ibcon#about to read 3, iclass 10, count 0 2006.286.05:44:32.73#ibcon#read 3, iclass 10, count 0 2006.286.05:44:32.73#ibcon#about to read 4, iclass 10, count 0 2006.286.05:44:32.73#ibcon#read 4, iclass 10, count 0 2006.286.05:44:32.73#ibcon#about to read 5, iclass 10, count 0 2006.286.05:44:32.73#ibcon#read 5, iclass 10, count 0 2006.286.05:44:32.73#ibcon#about to read 6, iclass 10, count 0 2006.286.05:44:32.73#ibcon#read 6, iclass 10, count 0 2006.286.05:44:32.73#ibcon#end of sib2, iclass 10, count 0 2006.286.05:44:32.73#ibcon#*mode == 0, iclass 10, count 0 2006.286.05:44:32.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.05:44:32.73#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.05:44:32.73#ibcon#*before write, iclass 10, count 0 2006.286.05:44:32.73#ibcon#enter sib2, iclass 10, count 0 2006.286.05:44:32.73#ibcon#flushed, iclass 10, count 0 2006.286.05:44:32.73#ibcon#about to write, iclass 10, count 0 2006.286.05:44:32.73#ibcon#wrote, iclass 10, count 0 2006.286.05:44:32.73#ibcon#about to read 3, iclass 10, count 0 2006.286.05:44:32.77#ibcon#read 3, iclass 10, count 0 2006.286.05:44:32.77#ibcon#about to read 4, iclass 10, count 0 2006.286.05:44:32.77#ibcon#read 4, iclass 10, count 0 2006.286.05:44:32.77#ibcon#about to read 5, iclass 10, count 0 2006.286.05:44:32.77#ibcon#read 5, iclass 10, count 0 2006.286.05:44:32.77#ibcon#about to read 6, iclass 10, count 0 2006.286.05:44:32.77#ibcon#read 6, iclass 10, count 0 2006.286.05:44:32.77#ibcon#end of sib2, iclass 10, count 0 2006.286.05:44:32.77#ibcon#*after write, iclass 10, count 0 2006.286.05:44:32.77#ibcon#*before return 0, iclass 10, count 0 2006.286.05:44:32.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:44:32.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:44:32.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.05:44:32.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.05:44:32.77$vck44/va=6,4 2006.286.05:44:32.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.05:44:32.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.05:44:32.77#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:32.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:44:32.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:44:32.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:44:32.83#ibcon#enter wrdev, iclass 12, count 2 2006.286.05:44:32.83#ibcon#first serial, iclass 12, count 2 2006.286.05:44:32.83#ibcon#enter sib2, iclass 12, count 2 2006.286.05:44:32.83#ibcon#flushed, iclass 12, count 2 2006.286.05:44:32.83#ibcon#about to write, iclass 12, count 2 2006.286.05:44:32.83#ibcon#wrote, iclass 12, count 2 2006.286.05:44:32.83#ibcon#about to read 3, iclass 12, count 2 2006.286.05:44:32.85#ibcon#read 3, iclass 12, count 2 2006.286.05:44:32.85#ibcon#about to read 4, iclass 12, count 2 2006.286.05:44:32.85#ibcon#read 4, iclass 12, count 2 2006.286.05:44:32.85#ibcon#about to read 5, iclass 12, count 2 2006.286.05:44:32.85#ibcon#read 5, iclass 12, count 2 2006.286.05:44:32.85#ibcon#about to read 6, iclass 12, count 2 2006.286.05:44:32.85#ibcon#read 6, iclass 12, count 2 2006.286.05:44:32.85#ibcon#end of sib2, iclass 12, count 2 2006.286.05:44:32.85#ibcon#*mode == 0, iclass 12, count 2 2006.286.05:44:32.85#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.05:44:32.85#ibcon#[25=AT06-04\r\n] 2006.286.05:44:32.85#ibcon#*before write, iclass 12, count 2 2006.286.05:44:32.85#ibcon#enter sib2, iclass 12, count 2 2006.286.05:44:32.85#ibcon#flushed, iclass 12, count 2 2006.286.05:44:32.85#ibcon#about to write, iclass 12, count 2 2006.286.05:44:32.85#ibcon#wrote, iclass 12, count 2 2006.286.05:44:32.85#ibcon#about to read 3, iclass 12, count 2 2006.286.05:44:32.88#ibcon#read 3, iclass 12, count 2 2006.286.05:44:32.88#ibcon#about to read 4, iclass 12, count 2 2006.286.05:44:32.88#ibcon#read 4, iclass 12, count 2 2006.286.05:44:32.88#ibcon#about to read 5, iclass 12, count 2 2006.286.05:44:32.88#ibcon#read 5, iclass 12, count 2 2006.286.05:44:32.88#ibcon#about to read 6, iclass 12, count 2 2006.286.05:44:32.88#ibcon#read 6, iclass 12, count 2 2006.286.05:44:32.88#ibcon#end of sib2, iclass 12, count 2 2006.286.05:44:32.88#ibcon#*after write, iclass 12, count 2 2006.286.05:44:32.88#ibcon#*before return 0, iclass 12, count 2 2006.286.05:44:32.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:44:32.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:44:32.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.05:44:32.88#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:32.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:44:33.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:44:33.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:44:33.00#ibcon#enter wrdev, iclass 12, count 0 2006.286.05:44:33.00#ibcon#first serial, iclass 12, count 0 2006.286.05:44:33.00#ibcon#enter sib2, iclass 12, count 0 2006.286.05:44:33.00#ibcon#flushed, iclass 12, count 0 2006.286.05:44:33.00#ibcon#about to write, iclass 12, count 0 2006.286.05:44:33.00#ibcon#wrote, iclass 12, count 0 2006.286.05:44:33.00#ibcon#about to read 3, iclass 12, count 0 2006.286.05:44:33.02#ibcon#read 3, iclass 12, count 0 2006.286.05:44:33.02#ibcon#about to read 4, iclass 12, count 0 2006.286.05:44:33.02#ibcon#read 4, iclass 12, count 0 2006.286.05:44:33.02#ibcon#about to read 5, iclass 12, count 0 2006.286.05:44:33.02#ibcon#read 5, iclass 12, count 0 2006.286.05:44:33.02#ibcon#about to read 6, iclass 12, count 0 2006.286.05:44:33.02#ibcon#read 6, iclass 12, count 0 2006.286.05:44:33.02#ibcon#end of sib2, iclass 12, count 0 2006.286.05:44:33.02#ibcon#*mode == 0, iclass 12, count 0 2006.286.05:44:33.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.05:44:33.02#ibcon#[25=USB\r\n] 2006.286.05:44:33.02#ibcon#*before write, iclass 12, count 0 2006.286.05:44:33.02#ibcon#enter sib2, iclass 12, count 0 2006.286.05:44:33.02#ibcon#flushed, iclass 12, count 0 2006.286.05:44:33.02#ibcon#about to write, iclass 12, count 0 2006.286.05:44:33.02#ibcon#wrote, iclass 12, count 0 2006.286.05:44:33.02#ibcon#about to read 3, iclass 12, count 0 2006.286.05:44:33.05#ibcon#read 3, iclass 12, count 0 2006.286.05:44:33.05#ibcon#about to read 4, iclass 12, count 0 2006.286.05:44:33.05#ibcon#read 4, iclass 12, count 0 2006.286.05:44:33.05#ibcon#about to read 5, iclass 12, count 0 2006.286.05:44:33.05#ibcon#read 5, iclass 12, count 0 2006.286.05:44:33.05#ibcon#about to read 6, iclass 12, count 0 2006.286.05:44:33.05#ibcon#read 6, iclass 12, count 0 2006.286.05:44:33.05#ibcon#end of sib2, iclass 12, count 0 2006.286.05:44:33.05#ibcon#*after write, iclass 12, count 0 2006.286.05:44:33.05#ibcon#*before return 0, iclass 12, count 0 2006.286.05:44:33.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:44:33.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:44:33.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.05:44:33.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.05:44:33.05$vck44/valo=7,864.99 2006.286.05:44:33.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.05:44:33.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.05:44:33.05#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:33.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:44:33.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:44:33.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:44:33.05#ibcon#enter wrdev, iclass 14, count 0 2006.286.05:44:33.05#ibcon#first serial, iclass 14, count 0 2006.286.05:44:33.05#ibcon#enter sib2, iclass 14, count 0 2006.286.05:44:33.05#ibcon#flushed, iclass 14, count 0 2006.286.05:44:33.05#ibcon#about to write, iclass 14, count 0 2006.286.05:44:33.18#ibcon#wrote, iclass 14, count 0 2006.286.05:44:33.18#ibcon#about to read 3, iclass 14, count 0 2006.286.05:44:33.19#ibcon#read 3, iclass 14, count 0 2006.286.05:44:33.19#ibcon#about to read 4, iclass 14, count 0 2006.286.05:44:33.19#ibcon#read 4, iclass 14, count 0 2006.286.05:44:33.19#ibcon#about to read 5, iclass 14, count 0 2006.286.05:44:33.19#ibcon#read 5, iclass 14, count 0 2006.286.05:44:33.19#ibcon#about to read 6, iclass 14, count 0 2006.286.05:44:33.19#ibcon#read 6, iclass 14, count 0 2006.286.05:44:33.19#ibcon#end of sib2, iclass 14, count 0 2006.286.05:44:33.19#ibcon#*mode == 0, iclass 14, count 0 2006.286.05:44:33.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.05:44:33.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.05:44:33.19#ibcon#*before write, iclass 14, count 0 2006.286.05:44:33.19#ibcon#enter sib2, iclass 14, count 0 2006.286.05:44:33.19#ibcon#flushed, iclass 14, count 0 2006.286.05:44:33.19#ibcon#about to write, iclass 14, count 0 2006.286.05:44:33.19#ibcon#wrote, iclass 14, count 0 2006.286.05:44:33.19#ibcon#about to read 3, iclass 14, count 0 2006.286.05:44:33.23#ibcon#read 3, iclass 14, count 0 2006.286.05:44:33.23#ibcon#about to read 4, iclass 14, count 0 2006.286.05:44:33.23#ibcon#read 4, iclass 14, count 0 2006.286.05:44:33.23#ibcon#about to read 5, iclass 14, count 0 2006.286.05:44:33.23#ibcon#read 5, iclass 14, count 0 2006.286.05:44:33.23#ibcon#about to read 6, iclass 14, count 0 2006.286.05:44:33.23#ibcon#read 6, iclass 14, count 0 2006.286.05:44:33.23#ibcon#end of sib2, iclass 14, count 0 2006.286.05:44:33.23#ibcon#*after write, iclass 14, count 0 2006.286.05:44:33.23#ibcon#*before return 0, iclass 14, count 0 2006.286.05:44:33.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:44:33.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:44:33.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.05:44:33.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.05:44:33.23$vck44/va=7,4 2006.286.05:44:33.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.05:44:33.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.05:44:33.23#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:33.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:44:33.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:44:33.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:44:33.23#ibcon#enter wrdev, iclass 16, count 2 2006.286.05:44:33.23#ibcon#first serial, iclass 16, count 2 2006.286.05:44:33.23#ibcon#enter sib2, iclass 16, count 2 2006.286.05:44:33.23#ibcon#flushed, iclass 16, count 2 2006.286.05:44:33.23#ibcon#about to write, iclass 16, count 2 2006.286.05:44:33.23#ibcon#wrote, iclass 16, count 2 2006.286.05:44:33.23#ibcon#about to read 3, iclass 16, count 2 2006.286.05:44:33.25#ibcon#read 3, iclass 16, count 2 2006.286.05:44:33.25#ibcon#about to read 4, iclass 16, count 2 2006.286.05:44:33.25#ibcon#read 4, iclass 16, count 2 2006.286.05:44:33.25#ibcon#about to read 5, iclass 16, count 2 2006.286.05:44:33.25#ibcon#read 5, iclass 16, count 2 2006.286.05:44:33.25#ibcon#about to read 6, iclass 16, count 2 2006.286.05:44:33.25#ibcon#read 6, iclass 16, count 2 2006.286.05:44:33.25#ibcon#end of sib2, iclass 16, count 2 2006.286.05:44:33.25#ibcon#*mode == 0, iclass 16, count 2 2006.286.05:44:33.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.05:44:33.25#ibcon#[25=AT07-04\r\n] 2006.286.05:44:33.25#ibcon#*before write, iclass 16, count 2 2006.286.05:44:33.25#ibcon#enter sib2, iclass 16, count 2 2006.286.05:44:33.25#ibcon#flushed, iclass 16, count 2 2006.286.05:44:33.25#ibcon#about to write, iclass 16, count 2 2006.286.05:44:33.25#ibcon#wrote, iclass 16, count 2 2006.286.05:44:33.25#ibcon#about to read 3, iclass 16, count 2 2006.286.05:44:33.28#ibcon#read 3, iclass 16, count 2 2006.286.05:44:33.28#ibcon#about to read 4, iclass 16, count 2 2006.286.05:44:33.28#ibcon#read 4, iclass 16, count 2 2006.286.05:44:33.28#ibcon#about to read 5, iclass 16, count 2 2006.286.05:44:33.28#ibcon#read 5, iclass 16, count 2 2006.286.05:44:33.28#ibcon#about to read 6, iclass 16, count 2 2006.286.05:44:33.28#ibcon#read 6, iclass 16, count 2 2006.286.05:44:33.28#ibcon#end of sib2, iclass 16, count 2 2006.286.05:44:33.28#ibcon#*after write, iclass 16, count 2 2006.286.05:44:33.28#ibcon#*before return 0, iclass 16, count 2 2006.286.05:44:33.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:44:33.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:44:33.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.05:44:33.28#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:33.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:44:33.40#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:44:33.40#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:44:33.40#ibcon#enter wrdev, iclass 16, count 0 2006.286.05:44:33.40#ibcon#first serial, iclass 16, count 0 2006.286.05:44:33.40#ibcon#enter sib2, iclass 16, count 0 2006.286.05:44:33.40#ibcon#flushed, iclass 16, count 0 2006.286.05:44:33.40#ibcon#about to write, iclass 16, count 0 2006.286.05:44:33.40#ibcon#wrote, iclass 16, count 0 2006.286.05:44:33.40#ibcon#about to read 3, iclass 16, count 0 2006.286.05:44:33.42#ibcon#read 3, iclass 16, count 0 2006.286.05:44:33.42#ibcon#about to read 4, iclass 16, count 0 2006.286.05:44:33.42#ibcon#read 4, iclass 16, count 0 2006.286.05:44:33.42#ibcon#about to read 5, iclass 16, count 0 2006.286.05:44:33.42#ibcon#read 5, iclass 16, count 0 2006.286.05:44:33.42#ibcon#about to read 6, iclass 16, count 0 2006.286.05:44:33.42#ibcon#read 6, iclass 16, count 0 2006.286.05:44:33.42#ibcon#end of sib2, iclass 16, count 0 2006.286.05:44:33.42#ibcon#*mode == 0, iclass 16, count 0 2006.286.05:44:33.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.05:44:33.42#ibcon#[25=USB\r\n] 2006.286.05:44:33.42#ibcon#*before write, iclass 16, count 0 2006.286.05:44:33.42#ibcon#enter sib2, iclass 16, count 0 2006.286.05:44:33.42#ibcon#flushed, iclass 16, count 0 2006.286.05:44:33.42#ibcon#about to write, iclass 16, count 0 2006.286.05:44:33.42#ibcon#wrote, iclass 16, count 0 2006.286.05:44:33.42#ibcon#about to read 3, iclass 16, count 0 2006.286.05:44:33.45#ibcon#read 3, iclass 16, count 0 2006.286.05:44:33.45#ibcon#about to read 4, iclass 16, count 0 2006.286.05:44:33.45#ibcon#read 4, iclass 16, count 0 2006.286.05:44:33.45#ibcon#about to read 5, iclass 16, count 0 2006.286.05:44:33.45#ibcon#read 5, iclass 16, count 0 2006.286.05:44:33.45#ibcon#about to read 6, iclass 16, count 0 2006.286.05:44:33.45#ibcon#read 6, iclass 16, count 0 2006.286.05:44:33.45#ibcon#end of sib2, iclass 16, count 0 2006.286.05:44:33.45#ibcon#*after write, iclass 16, count 0 2006.286.05:44:33.45#ibcon#*before return 0, iclass 16, count 0 2006.286.05:44:33.45#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:44:33.45#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:44:33.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.05:44:33.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.05:44:33.45$vck44/valo=8,884.99 2006.286.05:44:33.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.05:44:33.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.05:44:33.45#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:33.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:44:33.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:44:33.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:44:33.45#ibcon#enter wrdev, iclass 18, count 0 2006.286.05:44:33.45#ibcon#first serial, iclass 18, count 0 2006.286.05:44:33.45#ibcon#enter sib2, iclass 18, count 0 2006.286.05:44:33.45#ibcon#flushed, iclass 18, count 0 2006.286.05:44:33.45#ibcon#about to write, iclass 18, count 0 2006.286.05:44:33.45#ibcon#wrote, iclass 18, count 0 2006.286.05:44:33.45#ibcon#about to read 3, iclass 18, count 0 2006.286.05:44:33.47#ibcon#read 3, iclass 18, count 0 2006.286.05:44:33.47#ibcon#about to read 4, iclass 18, count 0 2006.286.05:44:33.47#ibcon#read 4, iclass 18, count 0 2006.286.05:44:33.47#ibcon#about to read 5, iclass 18, count 0 2006.286.05:44:33.47#ibcon#read 5, iclass 18, count 0 2006.286.05:44:33.47#ibcon#about to read 6, iclass 18, count 0 2006.286.05:44:33.47#ibcon#read 6, iclass 18, count 0 2006.286.05:44:33.47#ibcon#end of sib2, iclass 18, count 0 2006.286.05:44:33.47#ibcon#*mode == 0, iclass 18, count 0 2006.286.05:44:33.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.05:44:33.47#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.05:44:33.47#ibcon#*before write, iclass 18, count 0 2006.286.05:44:33.47#ibcon#enter sib2, iclass 18, count 0 2006.286.05:44:33.47#ibcon#flushed, iclass 18, count 0 2006.286.05:44:33.47#ibcon#about to write, iclass 18, count 0 2006.286.05:44:33.47#ibcon#wrote, iclass 18, count 0 2006.286.05:44:33.47#ibcon#about to read 3, iclass 18, count 0 2006.286.05:44:33.51#ibcon#read 3, iclass 18, count 0 2006.286.05:44:33.51#ibcon#about to read 4, iclass 18, count 0 2006.286.05:44:33.51#ibcon#read 4, iclass 18, count 0 2006.286.05:44:33.51#ibcon#about to read 5, iclass 18, count 0 2006.286.05:44:33.51#ibcon#read 5, iclass 18, count 0 2006.286.05:44:33.51#ibcon#about to read 6, iclass 18, count 0 2006.286.05:44:33.51#ibcon#read 6, iclass 18, count 0 2006.286.05:44:33.51#ibcon#end of sib2, iclass 18, count 0 2006.286.05:44:33.51#ibcon#*after write, iclass 18, count 0 2006.286.05:44:33.51#ibcon#*before return 0, iclass 18, count 0 2006.286.05:44:33.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:44:33.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:44:33.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.05:44:33.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.05:44:33.51$vck44/va=8,3 2006.286.05:44:33.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.286.05:44:33.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.286.05:44:33.51#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:33.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:44:33.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:44:33.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:44:33.57#ibcon#enter wrdev, iclass 20, count 2 2006.286.05:44:33.57#ibcon#first serial, iclass 20, count 2 2006.286.05:44:33.57#ibcon#enter sib2, iclass 20, count 2 2006.286.05:44:33.57#ibcon#flushed, iclass 20, count 2 2006.286.05:44:33.57#ibcon#about to write, iclass 20, count 2 2006.286.05:44:33.57#ibcon#wrote, iclass 20, count 2 2006.286.05:44:33.57#ibcon#about to read 3, iclass 20, count 2 2006.286.05:44:33.59#ibcon#read 3, iclass 20, count 2 2006.286.05:44:33.59#ibcon#about to read 4, iclass 20, count 2 2006.286.05:44:33.59#ibcon#read 4, iclass 20, count 2 2006.286.05:44:33.59#ibcon#about to read 5, iclass 20, count 2 2006.286.05:44:33.59#ibcon#read 5, iclass 20, count 2 2006.286.05:44:33.59#ibcon#about to read 6, iclass 20, count 2 2006.286.05:44:33.59#ibcon#read 6, iclass 20, count 2 2006.286.05:44:33.59#ibcon#end of sib2, iclass 20, count 2 2006.286.05:44:33.59#ibcon#*mode == 0, iclass 20, count 2 2006.286.05:44:33.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.286.05:44:33.59#ibcon#[25=AT08-03\r\n] 2006.286.05:44:33.59#ibcon#*before write, iclass 20, count 2 2006.286.05:44:33.59#ibcon#enter sib2, iclass 20, count 2 2006.286.05:44:33.59#ibcon#flushed, iclass 20, count 2 2006.286.05:44:33.59#ibcon#about to write, iclass 20, count 2 2006.286.05:44:33.59#ibcon#wrote, iclass 20, count 2 2006.286.05:44:33.59#ibcon#about to read 3, iclass 20, count 2 2006.286.05:44:33.62#ibcon#read 3, iclass 20, count 2 2006.286.05:44:33.62#ibcon#about to read 4, iclass 20, count 2 2006.286.05:44:33.62#ibcon#read 4, iclass 20, count 2 2006.286.05:44:33.62#ibcon#about to read 5, iclass 20, count 2 2006.286.05:44:33.62#ibcon#read 5, iclass 20, count 2 2006.286.05:44:33.62#ibcon#about to read 6, iclass 20, count 2 2006.286.05:44:33.62#ibcon#read 6, iclass 20, count 2 2006.286.05:44:33.62#ibcon#end of sib2, iclass 20, count 2 2006.286.05:44:33.62#ibcon#*after write, iclass 20, count 2 2006.286.05:44:33.62#ibcon#*before return 0, iclass 20, count 2 2006.286.05:44:33.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:44:33.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.286.05:44:33.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.286.05:44:33.62#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:33.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:44:33.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:44:33.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:44:33.74#ibcon#enter wrdev, iclass 20, count 0 2006.286.05:44:33.74#ibcon#first serial, iclass 20, count 0 2006.286.05:44:33.74#ibcon#enter sib2, iclass 20, count 0 2006.286.05:44:33.74#ibcon#flushed, iclass 20, count 0 2006.286.05:44:33.74#ibcon#about to write, iclass 20, count 0 2006.286.05:44:33.74#ibcon#wrote, iclass 20, count 0 2006.286.05:44:33.74#ibcon#about to read 3, iclass 20, count 0 2006.286.05:44:33.76#ibcon#read 3, iclass 20, count 0 2006.286.05:44:33.76#ibcon#about to read 4, iclass 20, count 0 2006.286.05:44:33.76#ibcon#read 4, iclass 20, count 0 2006.286.05:44:33.76#ibcon#about to read 5, iclass 20, count 0 2006.286.05:44:33.76#ibcon#read 5, iclass 20, count 0 2006.286.05:44:33.76#ibcon#about to read 6, iclass 20, count 0 2006.286.05:44:33.76#ibcon#read 6, iclass 20, count 0 2006.286.05:44:33.76#ibcon#end of sib2, iclass 20, count 0 2006.286.05:44:33.76#ibcon#*mode == 0, iclass 20, count 0 2006.286.05:44:33.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.05:44:33.76#ibcon#[25=USB\r\n] 2006.286.05:44:33.76#ibcon#*before write, iclass 20, count 0 2006.286.05:44:33.76#ibcon#enter sib2, iclass 20, count 0 2006.286.05:44:33.76#ibcon#flushed, iclass 20, count 0 2006.286.05:44:33.76#ibcon#about to write, iclass 20, count 0 2006.286.05:44:33.76#ibcon#wrote, iclass 20, count 0 2006.286.05:44:33.76#ibcon#about to read 3, iclass 20, count 0 2006.286.05:44:33.79#ibcon#read 3, iclass 20, count 0 2006.286.05:44:33.79#ibcon#about to read 4, iclass 20, count 0 2006.286.05:44:33.79#ibcon#read 4, iclass 20, count 0 2006.286.05:44:33.79#ibcon#about to read 5, iclass 20, count 0 2006.286.05:44:33.79#ibcon#read 5, iclass 20, count 0 2006.286.05:44:33.79#ibcon#about to read 6, iclass 20, count 0 2006.286.05:44:33.79#ibcon#read 6, iclass 20, count 0 2006.286.05:44:33.79#ibcon#end of sib2, iclass 20, count 0 2006.286.05:44:33.79#ibcon#*after write, iclass 20, count 0 2006.286.05:44:33.79#ibcon#*before return 0, iclass 20, count 0 2006.286.05:44:33.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:44:33.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.286.05:44:33.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.05:44:33.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.05:44:33.79$vck44/vblo=1,629.99 2006.286.05:44:33.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.286.05:44:33.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.286.05:44:33.79#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:33.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:44:33.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:44:33.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:44:33.79#ibcon#enter wrdev, iclass 22, count 0 2006.286.05:44:33.79#ibcon#first serial, iclass 22, count 0 2006.286.05:44:33.79#ibcon#enter sib2, iclass 22, count 0 2006.286.05:44:33.79#ibcon#flushed, iclass 22, count 0 2006.286.05:44:33.79#ibcon#about to write, iclass 22, count 0 2006.286.05:44:33.79#ibcon#wrote, iclass 22, count 0 2006.286.05:44:33.79#ibcon#about to read 3, iclass 22, count 0 2006.286.05:44:33.81#ibcon#read 3, iclass 22, count 0 2006.286.05:44:33.81#ibcon#about to read 4, iclass 22, count 0 2006.286.05:44:33.81#ibcon#read 4, iclass 22, count 0 2006.286.05:44:33.81#ibcon#about to read 5, iclass 22, count 0 2006.286.05:44:33.81#ibcon#read 5, iclass 22, count 0 2006.286.05:44:33.81#ibcon#about to read 6, iclass 22, count 0 2006.286.05:44:33.81#ibcon#read 6, iclass 22, count 0 2006.286.05:44:33.81#ibcon#end of sib2, iclass 22, count 0 2006.286.05:44:33.81#ibcon#*mode == 0, iclass 22, count 0 2006.286.05:44:33.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.286.05:44:33.81#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.05:44:33.81#ibcon#*before write, iclass 22, count 0 2006.286.05:44:33.81#ibcon#enter sib2, iclass 22, count 0 2006.286.05:44:33.81#ibcon#flushed, iclass 22, count 0 2006.286.05:44:33.81#ibcon#about to write, iclass 22, count 0 2006.286.05:44:33.81#ibcon#wrote, iclass 22, count 0 2006.286.05:44:33.81#ibcon#about to read 3, iclass 22, count 0 2006.286.05:44:33.85#ibcon#read 3, iclass 22, count 0 2006.286.05:44:33.85#ibcon#about to read 4, iclass 22, count 0 2006.286.05:44:33.85#ibcon#read 4, iclass 22, count 0 2006.286.05:44:33.85#ibcon#about to read 5, iclass 22, count 0 2006.286.05:44:33.85#ibcon#read 5, iclass 22, count 0 2006.286.05:44:33.85#ibcon#about to read 6, iclass 22, count 0 2006.286.05:44:33.85#ibcon#read 6, iclass 22, count 0 2006.286.05:44:33.85#ibcon#end of sib2, iclass 22, count 0 2006.286.05:44:33.85#ibcon#*after write, iclass 22, count 0 2006.286.05:44:33.85#ibcon#*before return 0, iclass 22, count 0 2006.286.05:44:33.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:44:33.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.286.05:44:33.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.286.05:44:33.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.286.05:44:33.85$vck44/vb=1,4 2006.286.05:44:33.85#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.286.05:44:33.85#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.286.05:44:33.85#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:33.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:44:33.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:44:33.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:44:33.85#ibcon#enter wrdev, iclass 24, count 2 2006.286.05:44:33.85#ibcon#first serial, iclass 24, count 2 2006.286.05:44:33.85#ibcon#enter sib2, iclass 24, count 2 2006.286.05:44:33.85#ibcon#flushed, iclass 24, count 2 2006.286.05:44:33.85#ibcon#about to write, iclass 24, count 2 2006.286.05:44:33.85#ibcon#wrote, iclass 24, count 2 2006.286.05:44:33.85#ibcon#about to read 3, iclass 24, count 2 2006.286.05:44:33.87#ibcon#read 3, iclass 24, count 2 2006.286.05:44:33.87#ibcon#about to read 4, iclass 24, count 2 2006.286.05:44:33.87#ibcon#read 4, iclass 24, count 2 2006.286.05:44:33.87#ibcon#about to read 5, iclass 24, count 2 2006.286.05:44:33.87#ibcon#read 5, iclass 24, count 2 2006.286.05:44:33.87#ibcon#about to read 6, iclass 24, count 2 2006.286.05:44:33.87#ibcon#read 6, iclass 24, count 2 2006.286.05:44:33.87#ibcon#end of sib2, iclass 24, count 2 2006.286.05:44:33.87#ibcon#*mode == 0, iclass 24, count 2 2006.286.05:44:33.87#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.286.05:44:33.87#ibcon#[27=AT01-04\r\n] 2006.286.05:44:33.87#ibcon#*before write, iclass 24, count 2 2006.286.05:44:33.87#ibcon#enter sib2, iclass 24, count 2 2006.286.05:44:33.87#ibcon#flushed, iclass 24, count 2 2006.286.05:44:33.87#ibcon#about to write, iclass 24, count 2 2006.286.05:44:33.87#ibcon#wrote, iclass 24, count 2 2006.286.05:44:33.87#ibcon#about to read 3, iclass 24, count 2 2006.286.05:44:33.90#ibcon#read 3, iclass 24, count 2 2006.286.05:44:33.90#ibcon#about to read 4, iclass 24, count 2 2006.286.05:44:33.90#ibcon#read 4, iclass 24, count 2 2006.286.05:44:33.90#ibcon#about to read 5, iclass 24, count 2 2006.286.05:44:33.90#ibcon#read 5, iclass 24, count 2 2006.286.05:44:33.90#ibcon#about to read 6, iclass 24, count 2 2006.286.05:44:33.90#ibcon#read 6, iclass 24, count 2 2006.286.05:44:33.90#ibcon#end of sib2, iclass 24, count 2 2006.286.05:44:33.90#ibcon#*after write, iclass 24, count 2 2006.286.05:44:33.90#ibcon#*before return 0, iclass 24, count 2 2006.286.05:44:33.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:44:33.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.286.05:44:33.90#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.286.05:44:33.90#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:33.90#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:44:34.02#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:44:34.02#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:44:34.02#ibcon#enter wrdev, iclass 24, count 0 2006.286.05:44:34.02#ibcon#first serial, iclass 24, count 0 2006.286.05:44:34.02#ibcon#enter sib2, iclass 24, count 0 2006.286.05:44:34.02#ibcon#flushed, iclass 24, count 0 2006.286.05:44:34.02#ibcon#about to write, iclass 24, count 0 2006.286.05:44:34.02#ibcon#wrote, iclass 24, count 0 2006.286.05:44:34.02#ibcon#about to read 3, iclass 24, count 0 2006.286.05:44:34.04#ibcon#read 3, iclass 24, count 0 2006.286.05:44:34.04#ibcon#about to read 4, iclass 24, count 0 2006.286.05:44:34.04#ibcon#read 4, iclass 24, count 0 2006.286.05:44:34.04#ibcon#about to read 5, iclass 24, count 0 2006.286.05:44:34.04#ibcon#read 5, iclass 24, count 0 2006.286.05:44:34.04#ibcon#about to read 6, iclass 24, count 0 2006.286.05:44:34.04#ibcon#read 6, iclass 24, count 0 2006.286.05:44:34.04#ibcon#end of sib2, iclass 24, count 0 2006.286.05:44:34.04#ibcon#*mode == 0, iclass 24, count 0 2006.286.05:44:34.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.286.05:44:34.04#ibcon#[27=USB\r\n] 2006.286.05:44:34.04#ibcon#*before write, iclass 24, count 0 2006.286.05:44:34.04#ibcon#enter sib2, iclass 24, count 0 2006.286.05:44:34.04#ibcon#flushed, iclass 24, count 0 2006.286.05:44:34.04#ibcon#about to write, iclass 24, count 0 2006.286.05:44:34.04#ibcon#wrote, iclass 24, count 0 2006.286.05:44:34.04#ibcon#about to read 3, iclass 24, count 0 2006.286.05:44:34.07#ibcon#read 3, iclass 24, count 0 2006.286.05:44:34.07#ibcon#about to read 4, iclass 24, count 0 2006.286.05:44:34.07#ibcon#read 4, iclass 24, count 0 2006.286.05:44:34.07#ibcon#about to read 5, iclass 24, count 0 2006.286.05:44:34.07#ibcon#read 5, iclass 24, count 0 2006.286.05:44:34.07#ibcon#about to read 6, iclass 24, count 0 2006.286.05:44:34.07#ibcon#read 6, iclass 24, count 0 2006.286.05:44:34.07#ibcon#end of sib2, iclass 24, count 0 2006.286.05:44:34.07#ibcon#*after write, iclass 24, count 0 2006.286.05:44:34.07#ibcon#*before return 0, iclass 24, count 0 2006.286.05:44:34.07#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:44:34.07#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.286.05:44:34.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.286.05:44:34.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.286.05:44:34.07$vck44/vblo=2,634.99 2006.286.05:44:34.07#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.286.05:44:34.07#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.286.05:44:34.07#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:34.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:44:34.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:44:34.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:44:34.07#ibcon#enter wrdev, iclass 26, count 0 2006.286.05:44:34.07#ibcon#first serial, iclass 26, count 0 2006.286.05:44:34.07#ibcon#enter sib2, iclass 26, count 0 2006.286.05:44:34.07#ibcon#flushed, iclass 26, count 0 2006.286.05:44:34.38#ibcon#about to write, iclass 26, count 0 2006.286.05:44:34.38#ibcon#wrote, iclass 26, count 0 2006.286.05:44:34.38#ibcon#about to read 3, iclass 26, count 0 2006.286.05:44:34.39#ibcon#read 3, iclass 26, count 0 2006.286.05:44:34.39#ibcon#about to read 4, iclass 26, count 0 2006.286.05:44:34.39#ibcon#read 4, iclass 26, count 0 2006.286.05:44:34.39#ibcon#about to read 5, iclass 26, count 0 2006.286.05:44:34.39#ibcon#read 5, iclass 26, count 0 2006.286.05:44:34.39#ibcon#about to read 6, iclass 26, count 0 2006.286.05:44:34.39#ibcon#read 6, iclass 26, count 0 2006.286.05:44:34.39#ibcon#end of sib2, iclass 26, count 0 2006.286.05:44:34.39#ibcon#*mode == 0, iclass 26, count 0 2006.286.05:44:34.39#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.286.05:44:34.39#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.05:44:34.39#ibcon#*before write, iclass 26, count 0 2006.286.05:44:34.39#ibcon#enter sib2, iclass 26, count 0 2006.286.05:44:34.39#ibcon#flushed, iclass 26, count 0 2006.286.05:44:34.39#ibcon#about to write, iclass 26, count 0 2006.286.05:44:34.39#ibcon#wrote, iclass 26, count 0 2006.286.05:44:34.39#ibcon#about to read 3, iclass 26, count 0 2006.286.05:44:34.43#ibcon#read 3, iclass 26, count 0 2006.286.05:44:34.43#ibcon#about to read 4, iclass 26, count 0 2006.286.05:44:34.43#ibcon#read 4, iclass 26, count 0 2006.286.05:44:34.43#ibcon#about to read 5, iclass 26, count 0 2006.286.05:44:34.43#ibcon#read 5, iclass 26, count 0 2006.286.05:44:34.43#ibcon#about to read 6, iclass 26, count 0 2006.286.05:44:34.43#ibcon#read 6, iclass 26, count 0 2006.286.05:44:34.43#ibcon#end of sib2, iclass 26, count 0 2006.286.05:44:34.43#ibcon#*after write, iclass 26, count 0 2006.286.05:44:34.43#ibcon#*before return 0, iclass 26, count 0 2006.286.05:44:34.43#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:44:34.43#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.286.05:44:34.43#ibcon#about to clear, iclass 26 cls_cnt 0 2006.286.05:44:34.43#ibcon#cleared, iclass 26 cls_cnt 0 2006.286.05:44:34.43$vck44/vb=2,5 2006.286.05:44:34.43#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.286.05:44:34.43#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.286.05:44:34.43#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:34.43#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:44:34.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:44:34.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:44:34.43#ibcon#enter wrdev, iclass 28, count 2 2006.286.05:44:34.43#ibcon#first serial, iclass 28, count 2 2006.286.05:44:34.43#ibcon#enter sib2, iclass 28, count 2 2006.286.05:44:34.43#ibcon#flushed, iclass 28, count 2 2006.286.05:44:34.43#ibcon#about to write, iclass 28, count 2 2006.286.05:44:34.43#ibcon#wrote, iclass 28, count 2 2006.286.05:44:34.43#ibcon#about to read 3, iclass 28, count 2 2006.286.05:44:34.45#ibcon#read 3, iclass 28, count 2 2006.286.05:44:34.45#ibcon#about to read 4, iclass 28, count 2 2006.286.05:44:34.45#ibcon#read 4, iclass 28, count 2 2006.286.05:44:34.45#ibcon#about to read 5, iclass 28, count 2 2006.286.05:44:34.45#ibcon#read 5, iclass 28, count 2 2006.286.05:44:34.45#ibcon#about to read 6, iclass 28, count 2 2006.286.05:44:34.45#ibcon#read 6, iclass 28, count 2 2006.286.05:44:34.45#ibcon#end of sib2, iclass 28, count 2 2006.286.05:44:34.45#ibcon#*mode == 0, iclass 28, count 2 2006.286.05:44:34.45#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.286.05:44:34.45#ibcon#[27=AT02-05\r\n] 2006.286.05:44:34.45#ibcon#*before write, iclass 28, count 2 2006.286.05:44:34.45#ibcon#enter sib2, iclass 28, count 2 2006.286.05:44:34.45#ibcon#flushed, iclass 28, count 2 2006.286.05:44:34.45#ibcon#about to write, iclass 28, count 2 2006.286.05:44:34.45#ibcon#wrote, iclass 28, count 2 2006.286.05:44:34.45#ibcon#about to read 3, iclass 28, count 2 2006.286.05:44:34.48#ibcon#read 3, iclass 28, count 2 2006.286.05:44:34.48#ibcon#about to read 4, iclass 28, count 2 2006.286.05:44:34.48#ibcon#read 4, iclass 28, count 2 2006.286.05:44:34.48#ibcon#about to read 5, iclass 28, count 2 2006.286.05:44:34.48#ibcon#read 5, iclass 28, count 2 2006.286.05:44:34.48#ibcon#about to read 6, iclass 28, count 2 2006.286.05:44:34.48#ibcon#read 6, iclass 28, count 2 2006.286.05:44:34.48#ibcon#end of sib2, iclass 28, count 2 2006.286.05:44:34.48#ibcon#*after write, iclass 28, count 2 2006.286.05:44:34.48#ibcon#*before return 0, iclass 28, count 2 2006.286.05:44:34.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:44:34.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.286.05:44:34.48#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.286.05:44:34.48#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:34.48#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:44:34.60#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:44:34.60#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:44:34.60#ibcon#enter wrdev, iclass 28, count 0 2006.286.05:44:34.60#ibcon#first serial, iclass 28, count 0 2006.286.05:44:34.60#ibcon#enter sib2, iclass 28, count 0 2006.286.05:44:34.60#ibcon#flushed, iclass 28, count 0 2006.286.05:44:34.60#ibcon#about to write, iclass 28, count 0 2006.286.05:44:34.60#ibcon#wrote, iclass 28, count 0 2006.286.05:44:34.60#ibcon#about to read 3, iclass 28, count 0 2006.286.05:44:34.62#ibcon#read 3, iclass 28, count 0 2006.286.05:44:34.62#ibcon#about to read 4, iclass 28, count 0 2006.286.05:44:34.62#ibcon#read 4, iclass 28, count 0 2006.286.05:44:34.62#ibcon#about to read 5, iclass 28, count 0 2006.286.05:44:34.62#ibcon#read 5, iclass 28, count 0 2006.286.05:44:34.62#ibcon#about to read 6, iclass 28, count 0 2006.286.05:44:34.62#ibcon#read 6, iclass 28, count 0 2006.286.05:44:34.62#ibcon#end of sib2, iclass 28, count 0 2006.286.05:44:34.62#ibcon#*mode == 0, iclass 28, count 0 2006.286.05:44:34.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.286.05:44:34.62#ibcon#[27=USB\r\n] 2006.286.05:44:34.62#ibcon#*before write, iclass 28, count 0 2006.286.05:44:34.62#ibcon#enter sib2, iclass 28, count 0 2006.286.05:44:34.62#ibcon#flushed, iclass 28, count 0 2006.286.05:44:34.62#ibcon#about to write, iclass 28, count 0 2006.286.05:44:34.62#ibcon#wrote, iclass 28, count 0 2006.286.05:44:34.62#ibcon#about to read 3, iclass 28, count 0 2006.286.05:44:34.65#ibcon#read 3, iclass 28, count 0 2006.286.05:44:34.65#ibcon#about to read 4, iclass 28, count 0 2006.286.05:44:34.65#ibcon#read 4, iclass 28, count 0 2006.286.05:44:34.65#ibcon#about to read 5, iclass 28, count 0 2006.286.05:44:34.65#ibcon#read 5, iclass 28, count 0 2006.286.05:44:34.65#ibcon#about to read 6, iclass 28, count 0 2006.286.05:44:34.65#ibcon#read 6, iclass 28, count 0 2006.286.05:44:34.65#ibcon#end of sib2, iclass 28, count 0 2006.286.05:44:34.65#ibcon#*after write, iclass 28, count 0 2006.286.05:44:34.65#ibcon#*before return 0, iclass 28, count 0 2006.286.05:44:34.65#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:44:34.65#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.286.05:44:34.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.286.05:44:34.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.286.05:44:34.65$vck44/vblo=3,649.99 2006.286.05:44:34.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.286.05:44:34.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.286.05:44:34.65#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:34.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:44:34.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:44:34.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:44:34.65#ibcon#enter wrdev, iclass 30, count 0 2006.286.05:44:34.65#ibcon#first serial, iclass 30, count 0 2006.286.05:44:34.65#ibcon#enter sib2, iclass 30, count 0 2006.286.05:44:34.65#ibcon#flushed, iclass 30, count 0 2006.286.05:44:34.65#ibcon#about to write, iclass 30, count 0 2006.286.05:44:34.65#ibcon#wrote, iclass 30, count 0 2006.286.05:44:34.65#ibcon#about to read 3, iclass 30, count 0 2006.286.05:44:34.67#ibcon#read 3, iclass 30, count 0 2006.286.05:44:34.67#ibcon#about to read 4, iclass 30, count 0 2006.286.05:44:34.67#ibcon#read 4, iclass 30, count 0 2006.286.05:44:34.67#ibcon#about to read 5, iclass 30, count 0 2006.286.05:44:34.67#ibcon#read 5, iclass 30, count 0 2006.286.05:44:34.67#ibcon#about to read 6, iclass 30, count 0 2006.286.05:44:34.67#ibcon#read 6, iclass 30, count 0 2006.286.05:44:34.67#ibcon#end of sib2, iclass 30, count 0 2006.286.05:44:34.67#ibcon#*mode == 0, iclass 30, count 0 2006.286.05:44:34.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.286.05:44:34.67#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.05:44:34.67#ibcon#*before write, iclass 30, count 0 2006.286.05:44:34.67#ibcon#enter sib2, iclass 30, count 0 2006.286.05:44:34.67#ibcon#flushed, iclass 30, count 0 2006.286.05:44:34.67#ibcon#about to write, iclass 30, count 0 2006.286.05:44:34.67#ibcon#wrote, iclass 30, count 0 2006.286.05:44:34.67#ibcon#about to read 3, iclass 30, count 0 2006.286.05:44:34.71#ibcon#read 3, iclass 30, count 0 2006.286.05:44:34.71#ibcon#about to read 4, iclass 30, count 0 2006.286.05:44:34.71#ibcon#read 4, iclass 30, count 0 2006.286.05:44:34.71#ibcon#about to read 5, iclass 30, count 0 2006.286.05:44:34.71#ibcon#read 5, iclass 30, count 0 2006.286.05:44:34.71#ibcon#about to read 6, iclass 30, count 0 2006.286.05:44:34.71#ibcon#read 6, iclass 30, count 0 2006.286.05:44:34.71#ibcon#end of sib2, iclass 30, count 0 2006.286.05:44:34.71#ibcon#*after write, iclass 30, count 0 2006.286.05:44:34.71#ibcon#*before return 0, iclass 30, count 0 2006.286.05:44:34.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:44:34.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.286.05:44:34.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.286.05:44:34.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.286.05:44:34.71$vck44/vb=3,4 2006.286.05:44:34.71#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.286.05:44:34.71#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.286.05:44:34.71#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:34.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:44:34.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:44:34.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:44:34.77#ibcon#enter wrdev, iclass 32, count 2 2006.286.05:44:34.77#ibcon#first serial, iclass 32, count 2 2006.286.05:44:34.77#ibcon#enter sib2, iclass 32, count 2 2006.286.05:44:34.77#ibcon#flushed, iclass 32, count 2 2006.286.05:44:34.77#ibcon#about to write, iclass 32, count 2 2006.286.05:44:34.77#ibcon#wrote, iclass 32, count 2 2006.286.05:44:34.77#ibcon#about to read 3, iclass 32, count 2 2006.286.05:44:34.79#ibcon#read 3, iclass 32, count 2 2006.286.05:44:34.79#ibcon#about to read 4, iclass 32, count 2 2006.286.05:44:34.79#ibcon#read 4, iclass 32, count 2 2006.286.05:44:34.79#ibcon#about to read 5, iclass 32, count 2 2006.286.05:44:34.79#ibcon#read 5, iclass 32, count 2 2006.286.05:44:34.79#ibcon#about to read 6, iclass 32, count 2 2006.286.05:44:34.79#ibcon#read 6, iclass 32, count 2 2006.286.05:44:34.79#ibcon#end of sib2, iclass 32, count 2 2006.286.05:44:34.79#ibcon#*mode == 0, iclass 32, count 2 2006.286.05:44:34.79#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.286.05:44:34.79#ibcon#[27=AT03-04\r\n] 2006.286.05:44:34.79#ibcon#*before write, iclass 32, count 2 2006.286.05:44:34.79#ibcon#enter sib2, iclass 32, count 2 2006.286.05:44:34.79#ibcon#flushed, iclass 32, count 2 2006.286.05:44:34.79#ibcon#about to write, iclass 32, count 2 2006.286.05:44:34.79#ibcon#wrote, iclass 32, count 2 2006.286.05:44:34.79#ibcon#about to read 3, iclass 32, count 2 2006.286.05:44:34.82#ibcon#read 3, iclass 32, count 2 2006.286.05:44:34.82#ibcon#about to read 4, iclass 32, count 2 2006.286.05:44:34.82#ibcon#read 4, iclass 32, count 2 2006.286.05:44:34.82#ibcon#about to read 5, iclass 32, count 2 2006.286.05:44:34.82#ibcon#read 5, iclass 32, count 2 2006.286.05:44:34.82#ibcon#about to read 6, iclass 32, count 2 2006.286.05:44:34.82#ibcon#read 6, iclass 32, count 2 2006.286.05:44:34.82#ibcon#end of sib2, iclass 32, count 2 2006.286.05:44:34.82#ibcon#*after write, iclass 32, count 2 2006.286.05:44:34.82#ibcon#*before return 0, iclass 32, count 2 2006.286.05:44:34.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:44:34.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.286.05:44:34.82#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.286.05:44:34.82#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:34.82#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:44:34.94#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:44:34.94#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:44:34.94#ibcon#enter wrdev, iclass 32, count 0 2006.286.05:44:34.94#ibcon#first serial, iclass 32, count 0 2006.286.05:44:34.94#ibcon#enter sib2, iclass 32, count 0 2006.286.05:44:34.94#ibcon#flushed, iclass 32, count 0 2006.286.05:44:34.94#ibcon#about to write, iclass 32, count 0 2006.286.05:44:34.94#ibcon#wrote, iclass 32, count 0 2006.286.05:44:34.94#ibcon#about to read 3, iclass 32, count 0 2006.286.05:44:34.96#ibcon#read 3, iclass 32, count 0 2006.286.05:44:34.96#ibcon#about to read 4, iclass 32, count 0 2006.286.05:44:34.96#ibcon#read 4, iclass 32, count 0 2006.286.05:44:34.96#ibcon#about to read 5, iclass 32, count 0 2006.286.05:44:34.96#ibcon#read 5, iclass 32, count 0 2006.286.05:44:34.96#ibcon#about to read 6, iclass 32, count 0 2006.286.05:44:34.96#ibcon#read 6, iclass 32, count 0 2006.286.05:44:34.96#ibcon#end of sib2, iclass 32, count 0 2006.286.05:44:34.96#ibcon#*mode == 0, iclass 32, count 0 2006.286.05:44:34.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.286.05:44:34.96#ibcon#[27=USB\r\n] 2006.286.05:44:34.96#ibcon#*before write, iclass 32, count 0 2006.286.05:44:34.96#ibcon#enter sib2, iclass 32, count 0 2006.286.05:44:34.96#ibcon#flushed, iclass 32, count 0 2006.286.05:44:34.96#ibcon#about to write, iclass 32, count 0 2006.286.05:44:34.96#ibcon#wrote, iclass 32, count 0 2006.286.05:44:34.96#ibcon#about to read 3, iclass 32, count 0 2006.286.05:44:34.99#ibcon#read 3, iclass 32, count 0 2006.286.05:44:34.99#ibcon#about to read 4, iclass 32, count 0 2006.286.05:44:34.99#ibcon#read 4, iclass 32, count 0 2006.286.05:44:34.99#ibcon#about to read 5, iclass 32, count 0 2006.286.05:44:34.99#ibcon#read 5, iclass 32, count 0 2006.286.05:44:34.99#ibcon#about to read 6, iclass 32, count 0 2006.286.05:44:34.99#ibcon#read 6, iclass 32, count 0 2006.286.05:44:34.99#ibcon#end of sib2, iclass 32, count 0 2006.286.05:44:34.99#ibcon#*after write, iclass 32, count 0 2006.286.05:44:34.99#ibcon#*before return 0, iclass 32, count 0 2006.286.05:44:34.99#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:44:34.99#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.286.05:44:34.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.286.05:44:34.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.286.05:44:34.99$vck44/vblo=4,679.99 2006.286.05:44:34.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.286.05:44:34.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.286.05:44:34.99#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:34.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:44:34.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:44:34.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:44:34.99#ibcon#enter wrdev, iclass 34, count 0 2006.286.05:44:34.99#ibcon#first serial, iclass 34, count 0 2006.286.05:44:34.99#ibcon#enter sib2, iclass 34, count 0 2006.286.05:44:34.99#ibcon#flushed, iclass 34, count 0 2006.286.05:44:34.99#ibcon#about to write, iclass 34, count 0 2006.286.05:44:34.99#ibcon#wrote, iclass 34, count 0 2006.286.05:44:34.99#ibcon#about to read 3, iclass 34, count 0 2006.286.05:44:35.01#ibcon#read 3, iclass 34, count 0 2006.286.05:44:35.01#ibcon#about to read 4, iclass 34, count 0 2006.286.05:44:35.01#ibcon#read 4, iclass 34, count 0 2006.286.05:44:35.01#ibcon#about to read 5, iclass 34, count 0 2006.286.05:44:35.01#ibcon#read 5, iclass 34, count 0 2006.286.05:44:35.01#ibcon#about to read 6, iclass 34, count 0 2006.286.05:44:35.01#ibcon#read 6, iclass 34, count 0 2006.286.05:44:35.01#ibcon#end of sib2, iclass 34, count 0 2006.286.05:44:35.01#ibcon#*mode == 0, iclass 34, count 0 2006.286.05:44:35.01#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.286.05:44:35.01#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.05:44:35.01#ibcon#*before write, iclass 34, count 0 2006.286.05:44:35.01#ibcon#enter sib2, iclass 34, count 0 2006.286.05:44:35.01#ibcon#flushed, iclass 34, count 0 2006.286.05:44:35.01#ibcon#about to write, iclass 34, count 0 2006.286.05:44:35.01#ibcon#wrote, iclass 34, count 0 2006.286.05:44:35.01#ibcon#about to read 3, iclass 34, count 0 2006.286.05:44:35.05#ibcon#read 3, iclass 34, count 0 2006.286.05:44:35.05#ibcon#about to read 4, iclass 34, count 0 2006.286.05:44:35.05#ibcon#read 4, iclass 34, count 0 2006.286.05:44:35.05#ibcon#about to read 5, iclass 34, count 0 2006.286.05:44:35.05#ibcon#read 5, iclass 34, count 0 2006.286.05:44:35.05#ibcon#about to read 6, iclass 34, count 0 2006.286.05:44:35.05#ibcon#read 6, iclass 34, count 0 2006.286.05:44:35.05#ibcon#end of sib2, iclass 34, count 0 2006.286.05:44:35.05#ibcon#*after write, iclass 34, count 0 2006.286.05:44:35.05#ibcon#*before return 0, iclass 34, count 0 2006.286.05:44:35.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:44:35.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.286.05:44:35.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.286.05:44:35.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.286.05:44:35.05$vck44/vb=4,5 2006.286.05:44:35.05#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.286.05:44:35.05#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.286.05:44:35.05#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:35.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:44:35.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:44:35.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:44:35.11#ibcon#enter wrdev, iclass 36, count 2 2006.286.05:44:35.11#ibcon#first serial, iclass 36, count 2 2006.286.05:44:35.11#ibcon#enter sib2, iclass 36, count 2 2006.286.05:44:35.11#ibcon#flushed, iclass 36, count 2 2006.286.05:44:35.11#ibcon#about to write, iclass 36, count 2 2006.286.05:44:35.11#ibcon#wrote, iclass 36, count 2 2006.286.05:44:35.11#ibcon#about to read 3, iclass 36, count 2 2006.286.05:44:35.13#ibcon#read 3, iclass 36, count 2 2006.286.05:44:35.21#ibcon#about to read 4, iclass 36, count 2 2006.286.05:44:35.21#ibcon#read 4, iclass 36, count 2 2006.286.05:44:35.21#ibcon#about to read 5, iclass 36, count 2 2006.286.05:44:35.21#ibcon#read 5, iclass 36, count 2 2006.286.05:44:35.21#ibcon#about to read 6, iclass 36, count 2 2006.286.05:44:35.21#ibcon#read 6, iclass 36, count 2 2006.286.05:44:35.21#ibcon#end of sib2, iclass 36, count 2 2006.286.05:44:35.21#ibcon#*mode == 0, iclass 36, count 2 2006.286.05:44:35.21#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.286.05:44:35.21#ibcon#[27=AT04-05\r\n] 2006.286.05:44:35.21#ibcon#*before write, iclass 36, count 2 2006.286.05:44:35.21#ibcon#enter sib2, iclass 36, count 2 2006.286.05:44:35.21#ibcon#flushed, iclass 36, count 2 2006.286.05:44:35.21#ibcon#about to write, iclass 36, count 2 2006.286.05:44:35.21#ibcon#wrote, iclass 36, count 2 2006.286.05:44:35.21#ibcon#about to read 3, iclass 36, count 2 2006.286.05:44:35.24#ibcon#read 3, iclass 36, count 2 2006.286.05:44:35.24#ibcon#about to read 4, iclass 36, count 2 2006.286.05:44:35.24#ibcon#read 4, iclass 36, count 2 2006.286.05:44:35.24#ibcon#about to read 5, iclass 36, count 2 2006.286.05:44:35.24#ibcon#read 5, iclass 36, count 2 2006.286.05:44:35.24#ibcon#about to read 6, iclass 36, count 2 2006.286.05:44:35.24#ibcon#read 6, iclass 36, count 2 2006.286.05:44:35.24#ibcon#end of sib2, iclass 36, count 2 2006.286.05:44:35.24#ibcon#*after write, iclass 36, count 2 2006.286.05:44:35.24#ibcon#*before return 0, iclass 36, count 2 2006.286.05:44:35.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:44:35.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.286.05:44:35.24#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.286.05:44:35.24#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:35.24#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:44:35.36#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:44:35.36#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:44:35.36#ibcon#enter wrdev, iclass 36, count 0 2006.286.05:44:35.36#ibcon#first serial, iclass 36, count 0 2006.286.05:44:35.36#ibcon#enter sib2, iclass 36, count 0 2006.286.05:44:35.36#ibcon#flushed, iclass 36, count 0 2006.286.05:44:35.36#ibcon#about to write, iclass 36, count 0 2006.286.05:44:35.36#ibcon#wrote, iclass 36, count 0 2006.286.05:44:35.36#ibcon#about to read 3, iclass 36, count 0 2006.286.05:44:35.38#ibcon#read 3, iclass 36, count 0 2006.286.05:44:35.38#ibcon#about to read 4, iclass 36, count 0 2006.286.05:44:35.38#ibcon#read 4, iclass 36, count 0 2006.286.05:44:35.38#ibcon#about to read 5, iclass 36, count 0 2006.286.05:44:35.38#ibcon#read 5, iclass 36, count 0 2006.286.05:44:35.38#ibcon#about to read 6, iclass 36, count 0 2006.286.05:44:35.38#ibcon#read 6, iclass 36, count 0 2006.286.05:44:35.38#ibcon#end of sib2, iclass 36, count 0 2006.286.05:44:35.38#ibcon#*mode == 0, iclass 36, count 0 2006.286.05:44:35.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.286.05:44:35.38#ibcon#[27=USB\r\n] 2006.286.05:44:35.38#ibcon#*before write, iclass 36, count 0 2006.286.05:44:35.38#ibcon#enter sib2, iclass 36, count 0 2006.286.05:44:35.38#ibcon#flushed, iclass 36, count 0 2006.286.05:44:35.38#ibcon#about to write, iclass 36, count 0 2006.286.05:44:35.38#ibcon#wrote, iclass 36, count 0 2006.286.05:44:35.38#ibcon#about to read 3, iclass 36, count 0 2006.286.05:44:35.41#ibcon#read 3, iclass 36, count 0 2006.286.05:44:35.41#ibcon#about to read 4, iclass 36, count 0 2006.286.05:44:35.41#ibcon#read 4, iclass 36, count 0 2006.286.05:44:35.41#ibcon#about to read 5, iclass 36, count 0 2006.286.05:44:35.41#ibcon#read 5, iclass 36, count 0 2006.286.05:44:35.41#ibcon#about to read 6, iclass 36, count 0 2006.286.05:44:35.41#ibcon#read 6, iclass 36, count 0 2006.286.05:44:35.41#ibcon#end of sib2, iclass 36, count 0 2006.286.05:44:35.41#ibcon#*after write, iclass 36, count 0 2006.286.05:44:35.41#ibcon#*before return 0, iclass 36, count 0 2006.286.05:44:35.41#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:44:35.41#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.286.05:44:35.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.286.05:44:35.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.286.05:44:35.41$vck44/vblo=5,709.99 2006.286.05:44:35.41#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.286.05:44:35.41#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.286.05:44:35.41#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:35.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:44:35.41#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:44:35.41#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:44:35.41#ibcon#enter wrdev, iclass 38, count 0 2006.286.05:44:35.41#ibcon#first serial, iclass 38, count 0 2006.286.05:44:35.41#ibcon#enter sib2, iclass 38, count 0 2006.286.05:44:35.41#ibcon#flushed, iclass 38, count 0 2006.286.05:44:35.41#ibcon#about to write, iclass 38, count 0 2006.286.05:44:35.41#ibcon#wrote, iclass 38, count 0 2006.286.05:44:35.41#ibcon#about to read 3, iclass 38, count 0 2006.286.05:44:35.43#ibcon#read 3, iclass 38, count 0 2006.286.05:44:35.43#ibcon#about to read 4, iclass 38, count 0 2006.286.05:44:35.43#ibcon#read 4, iclass 38, count 0 2006.286.05:44:35.43#ibcon#about to read 5, iclass 38, count 0 2006.286.05:44:35.43#ibcon#read 5, iclass 38, count 0 2006.286.05:44:35.43#ibcon#about to read 6, iclass 38, count 0 2006.286.05:44:35.43#ibcon#read 6, iclass 38, count 0 2006.286.05:44:35.43#ibcon#end of sib2, iclass 38, count 0 2006.286.05:44:35.43#ibcon#*mode == 0, iclass 38, count 0 2006.286.05:44:35.43#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.286.05:44:35.43#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.05:44:35.43#ibcon#*before write, iclass 38, count 0 2006.286.05:44:35.43#ibcon#enter sib2, iclass 38, count 0 2006.286.05:44:35.43#ibcon#flushed, iclass 38, count 0 2006.286.05:44:35.43#ibcon#about to write, iclass 38, count 0 2006.286.05:44:35.43#ibcon#wrote, iclass 38, count 0 2006.286.05:44:35.43#ibcon#about to read 3, iclass 38, count 0 2006.286.05:44:35.47#ibcon#read 3, iclass 38, count 0 2006.286.05:44:35.47#ibcon#about to read 4, iclass 38, count 0 2006.286.05:44:35.47#ibcon#read 4, iclass 38, count 0 2006.286.05:44:35.47#ibcon#about to read 5, iclass 38, count 0 2006.286.05:44:35.47#ibcon#read 5, iclass 38, count 0 2006.286.05:44:35.47#ibcon#about to read 6, iclass 38, count 0 2006.286.05:44:35.47#ibcon#read 6, iclass 38, count 0 2006.286.05:44:35.47#ibcon#end of sib2, iclass 38, count 0 2006.286.05:44:35.47#ibcon#*after write, iclass 38, count 0 2006.286.05:44:35.47#ibcon#*before return 0, iclass 38, count 0 2006.286.05:44:35.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:44:35.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.286.05:44:35.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.286.05:44:35.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.286.05:44:35.47$vck44/vb=5,4 2006.286.05:44:35.47#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.286.05:44:35.47#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.286.05:44:35.47#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:35.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:44:35.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:44:35.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:44:35.53#ibcon#enter wrdev, iclass 40, count 2 2006.286.05:44:35.53#ibcon#first serial, iclass 40, count 2 2006.286.05:44:35.53#ibcon#enter sib2, iclass 40, count 2 2006.286.05:44:35.53#ibcon#flushed, iclass 40, count 2 2006.286.05:44:35.53#ibcon#about to write, iclass 40, count 2 2006.286.05:44:35.53#ibcon#wrote, iclass 40, count 2 2006.286.05:44:35.53#ibcon#about to read 3, iclass 40, count 2 2006.286.05:44:35.55#ibcon#read 3, iclass 40, count 2 2006.286.05:44:35.55#ibcon#about to read 4, iclass 40, count 2 2006.286.05:44:35.55#ibcon#read 4, iclass 40, count 2 2006.286.05:44:35.55#ibcon#about to read 5, iclass 40, count 2 2006.286.05:44:35.55#ibcon#read 5, iclass 40, count 2 2006.286.05:44:35.55#ibcon#about to read 6, iclass 40, count 2 2006.286.05:44:35.55#ibcon#read 6, iclass 40, count 2 2006.286.05:44:35.55#ibcon#end of sib2, iclass 40, count 2 2006.286.05:44:35.55#ibcon#*mode == 0, iclass 40, count 2 2006.286.05:44:35.55#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.286.05:44:35.55#ibcon#[27=AT05-04\r\n] 2006.286.05:44:35.55#ibcon#*before write, iclass 40, count 2 2006.286.05:44:35.55#ibcon#enter sib2, iclass 40, count 2 2006.286.05:44:35.55#ibcon#flushed, iclass 40, count 2 2006.286.05:44:35.55#ibcon#about to write, iclass 40, count 2 2006.286.05:44:35.55#ibcon#wrote, iclass 40, count 2 2006.286.05:44:35.55#ibcon#about to read 3, iclass 40, count 2 2006.286.05:44:35.58#ibcon#read 3, iclass 40, count 2 2006.286.05:44:35.58#ibcon#about to read 4, iclass 40, count 2 2006.286.05:44:35.58#ibcon#read 4, iclass 40, count 2 2006.286.05:44:35.58#ibcon#about to read 5, iclass 40, count 2 2006.286.05:44:35.58#ibcon#read 5, iclass 40, count 2 2006.286.05:44:35.58#ibcon#about to read 6, iclass 40, count 2 2006.286.05:44:35.58#ibcon#read 6, iclass 40, count 2 2006.286.05:44:35.58#ibcon#end of sib2, iclass 40, count 2 2006.286.05:44:35.58#ibcon#*after write, iclass 40, count 2 2006.286.05:44:35.58#ibcon#*before return 0, iclass 40, count 2 2006.286.05:44:35.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:44:35.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.286.05:44:35.58#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.286.05:44:35.58#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:35.58#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:44:35.70#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:44:35.70#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:44:35.70#ibcon#enter wrdev, iclass 40, count 0 2006.286.05:44:35.70#ibcon#first serial, iclass 40, count 0 2006.286.05:44:35.70#ibcon#enter sib2, iclass 40, count 0 2006.286.05:44:35.70#ibcon#flushed, iclass 40, count 0 2006.286.05:44:35.70#ibcon#about to write, iclass 40, count 0 2006.286.05:44:35.70#ibcon#wrote, iclass 40, count 0 2006.286.05:44:35.70#ibcon#about to read 3, iclass 40, count 0 2006.286.05:44:35.72#ibcon#read 3, iclass 40, count 0 2006.286.05:44:35.72#ibcon#about to read 4, iclass 40, count 0 2006.286.05:44:35.72#ibcon#read 4, iclass 40, count 0 2006.286.05:44:35.72#ibcon#about to read 5, iclass 40, count 0 2006.286.05:44:35.72#ibcon#read 5, iclass 40, count 0 2006.286.05:44:35.72#ibcon#about to read 6, iclass 40, count 0 2006.286.05:44:35.72#ibcon#read 6, iclass 40, count 0 2006.286.05:44:35.72#ibcon#end of sib2, iclass 40, count 0 2006.286.05:44:35.72#ibcon#*mode == 0, iclass 40, count 0 2006.286.05:44:35.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.286.05:44:35.72#ibcon#[27=USB\r\n] 2006.286.05:44:35.72#ibcon#*before write, iclass 40, count 0 2006.286.05:44:35.72#ibcon#enter sib2, iclass 40, count 0 2006.286.05:44:35.72#ibcon#flushed, iclass 40, count 0 2006.286.05:44:35.72#ibcon#about to write, iclass 40, count 0 2006.286.05:44:35.72#ibcon#wrote, iclass 40, count 0 2006.286.05:44:35.72#ibcon#about to read 3, iclass 40, count 0 2006.286.05:44:35.75#ibcon#read 3, iclass 40, count 0 2006.286.05:44:35.75#ibcon#about to read 4, iclass 40, count 0 2006.286.05:44:35.75#ibcon#read 4, iclass 40, count 0 2006.286.05:44:35.75#ibcon#about to read 5, iclass 40, count 0 2006.286.05:44:35.75#ibcon#read 5, iclass 40, count 0 2006.286.05:44:35.75#ibcon#about to read 6, iclass 40, count 0 2006.286.05:44:35.75#ibcon#read 6, iclass 40, count 0 2006.286.05:44:35.75#ibcon#end of sib2, iclass 40, count 0 2006.286.05:44:35.75#ibcon#*after write, iclass 40, count 0 2006.286.05:44:35.75#ibcon#*before return 0, iclass 40, count 0 2006.286.05:44:35.75#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:44:35.75#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.286.05:44:35.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.286.05:44:35.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.286.05:44:35.75$vck44/vblo=6,719.99 2006.286.05:44:35.75#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.286.05:44:35.75#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.286.05:44:35.75#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:35.75#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:44:35.75#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:44:35.75#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:44:35.75#ibcon#enter wrdev, iclass 4, count 0 2006.286.05:44:35.75#ibcon#first serial, iclass 4, count 0 2006.286.05:44:35.75#ibcon#enter sib2, iclass 4, count 0 2006.286.05:44:35.75#ibcon#flushed, iclass 4, count 0 2006.286.05:44:35.75#ibcon#about to write, iclass 4, count 0 2006.286.05:44:35.75#ibcon#wrote, iclass 4, count 0 2006.286.05:44:35.75#ibcon#about to read 3, iclass 4, count 0 2006.286.05:44:35.77#ibcon#read 3, iclass 4, count 0 2006.286.05:44:35.77#ibcon#about to read 4, iclass 4, count 0 2006.286.05:44:35.77#ibcon#read 4, iclass 4, count 0 2006.286.05:44:35.77#ibcon#about to read 5, iclass 4, count 0 2006.286.05:44:35.77#ibcon#read 5, iclass 4, count 0 2006.286.05:44:35.77#ibcon#about to read 6, iclass 4, count 0 2006.286.05:44:35.77#ibcon#read 6, iclass 4, count 0 2006.286.05:44:35.77#ibcon#end of sib2, iclass 4, count 0 2006.286.05:44:35.77#ibcon#*mode == 0, iclass 4, count 0 2006.286.05:44:35.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.286.05:44:35.77#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.05:44:35.77#ibcon#*before write, iclass 4, count 0 2006.286.05:44:35.77#ibcon#enter sib2, iclass 4, count 0 2006.286.05:44:35.77#ibcon#flushed, iclass 4, count 0 2006.286.05:44:35.77#ibcon#about to write, iclass 4, count 0 2006.286.05:44:35.77#ibcon#wrote, iclass 4, count 0 2006.286.05:44:35.77#ibcon#about to read 3, iclass 4, count 0 2006.286.05:44:35.81#ibcon#read 3, iclass 4, count 0 2006.286.05:44:35.81#ibcon#about to read 4, iclass 4, count 0 2006.286.05:44:35.81#ibcon#read 4, iclass 4, count 0 2006.286.05:44:35.81#ibcon#about to read 5, iclass 4, count 0 2006.286.05:44:35.81#ibcon#read 5, iclass 4, count 0 2006.286.05:44:35.81#ibcon#about to read 6, iclass 4, count 0 2006.286.05:44:35.81#ibcon#read 6, iclass 4, count 0 2006.286.05:44:35.81#ibcon#end of sib2, iclass 4, count 0 2006.286.05:44:35.81#ibcon#*after write, iclass 4, count 0 2006.286.05:44:35.81#ibcon#*before return 0, iclass 4, count 0 2006.286.05:44:35.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:44:35.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.286.05:44:35.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.286.05:44:35.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.286.05:44:35.81$vck44/vb=6,3 2006.286.05:44:35.81#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.286.05:44:35.81#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.286.05:44:35.81#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:35.81#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:44:35.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:44:35.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:44:35.87#ibcon#enter wrdev, iclass 6, count 2 2006.286.05:44:35.87#ibcon#first serial, iclass 6, count 2 2006.286.05:44:35.87#ibcon#enter sib2, iclass 6, count 2 2006.286.05:44:35.87#ibcon#flushed, iclass 6, count 2 2006.286.05:44:35.87#ibcon#about to write, iclass 6, count 2 2006.286.05:44:35.87#ibcon#wrote, iclass 6, count 2 2006.286.05:44:35.87#ibcon#about to read 3, iclass 6, count 2 2006.286.05:44:35.89#ibcon#read 3, iclass 6, count 2 2006.286.05:44:35.89#ibcon#about to read 4, iclass 6, count 2 2006.286.05:44:35.89#ibcon#read 4, iclass 6, count 2 2006.286.05:44:35.89#ibcon#about to read 5, iclass 6, count 2 2006.286.05:44:35.89#ibcon#read 5, iclass 6, count 2 2006.286.05:44:35.89#ibcon#about to read 6, iclass 6, count 2 2006.286.05:44:35.89#ibcon#read 6, iclass 6, count 2 2006.286.05:44:35.89#ibcon#end of sib2, iclass 6, count 2 2006.286.05:44:35.89#ibcon#*mode == 0, iclass 6, count 2 2006.286.05:44:35.89#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.286.05:44:35.89#ibcon#[27=AT06-03\r\n] 2006.286.05:44:35.89#ibcon#*before write, iclass 6, count 2 2006.286.05:44:35.89#ibcon#enter sib2, iclass 6, count 2 2006.286.05:44:35.89#ibcon#flushed, iclass 6, count 2 2006.286.05:44:35.89#ibcon#about to write, iclass 6, count 2 2006.286.05:44:35.89#ibcon#wrote, iclass 6, count 2 2006.286.05:44:35.89#ibcon#about to read 3, iclass 6, count 2 2006.286.05:44:35.92#ibcon#read 3, iclass 6, count 2 2006.286.05:44:35.92#ibcon#about to read 4, iclass 6, count 2 2006.286.05:44:35.92#ibcon#read 4, iclass 6, count 2 2006.286.05:44:35.92#ibcon#about to read 5, iclass 6, count 2 2006.286.05:44:35.92#ibcon#read 5, iclass 6, count 2 2006.286.05:44:35.92#ibcon#about to read 6, iclass 6, count 2 2006.286.05:44:35.92#ibcon#read 6, iclass 6, count 2 2006.286.05:44:35.92#ibcon#end of sib2, iclass 6, count 2 2006.286.05:44:35.92#ibcon#*after write, iclass 6, count 2 2006.286.05:44:35.92#ibcon#*before return 0, iclass 6, count 2 2006.286.05:44:35.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:44:35.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.286.05:44:35.92#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.286.05:44:35.92#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:35.92#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:44:36.04#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:44:36.04#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:44:36.04#ibcon#enter wrdev, iclass 6, count 0 2006.286.05:44:36.04#ibcon#first serial, iclass 6, count 0 2006.286.05:44:36.04#ibcon#enter sib2, iclass 6, count 0 2006.286.05:44:36.04#ibcon#flushed, iclass 6, count 0 2006.286.05:44:36.04#ibcon#about to write, iclass 6, count 0 2006.286.05:44:36.04#ibcon#wrote, iclass 6, count 0 2006.286.05:44:36.04#ibcon#about to read 3, iclass 6, count 0 2006.286.05:44:36.06#ibcon#read 3, iclass 6, count 0 2006.286.05:44:36.06#ibcon#about to read 4, iclass 6, count 0 2006.286.05:44:36.06#ibcon#read 4, iclass 6, count 0 2006.286.05:44:36.06#ibcon#about to read 5, iclass 6, count 0 2006.286.05:44:36.06#ibcon#read 5, iclass 6, count 0 2006.286.05:44:36.06#ibcon#about to read 6, iclass 6, count 0 2006.286.05:44:36.06#ibcon#read 6, iclass 6, count 0 2006.286.05:44:36.06#ibcon#end of sib2, iclass 6, count 0 2006.286.05:44:36.06#ibcon#*mode == 0, iclass 6, count 0 2006.286.05:44:36.06#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.286.05:44:36.06#ibcon#[27=USB\r\n] 2006.286.05:44:36.06#ibcon#*before write, iclass 6, count 0 2006.286.05:44:36.06#ibcon#enter sib2, iclass 6, count 0 2006.286.05:44:36.06#ibcon#flushed, iclass 6, count 0 2006.286.05:44:36.06#ibcon#about to write, iclass 6, count 0 2006.286.05:44:36.06#ibcon#wrote, iclass 6, count 0 2006.286.05:44:36.06#ibcon#about to read 3, iclass 6, count 0 2006.286.05:44:36.09#ibcon#read 3, iclass 6, count 0 2006.286.05:44:36.09#ibcon#about to read 4, iclass 6, count 0 2006.286.05:44:36.09#ibcon#read 4, iclass 6, count 0 2006.286.05:44:36.09#ibcon#about to read 5, iclass 6, count 0 2006.286.05:44:36.09#ibcon#read 5, iclass 6, count 0 2006.286.05:44:36.09#ibcon#about to read 6, iclass 6, count 0 2006.286.05:44:36.09#ibcon#read 6, iclass 6, count 0 2006.286.05:44:36.09#ibcon#end of sib2, iclass 6, count 0 2006.286.05:44:36.09#ibcon#*after write, iclass 6, count 0 2006.286.05:44:36.09#ibcon#*before return 0, iclass 6, count 0 2006.286.05:44:36.09#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:44:36.09#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.286.05:44:36.09#ibcon#about to clear, iclass 6 cls_cnt 0 2006.286.05:44:36.09#ibcon#cleared, iclass 6 cls_cnt 0 2006.286.05:44:36.09$vck44/vblo=7,734.99 2006.286.05:44:36.09#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.286.05:44:36.09#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.286.05:44:36.09#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:36.09#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:44:36.09#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:44:36.09#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:44:36.09#ibcon#enter wrdev, iclass 10, count 0 2006.286.05:44:36.09#ibcon#first serial, iclass 10, count 0 2006.286.05:44:36.09#ibcon#enter sib2, iclass 10, count 0 2006.286.05:44:36.09#ibcon#flushed, iclass 10, count 0 2006.286.05:44:36.09#ibcon#about to write, iclass 10, count 0 2006.286.05:44:36.09#ibcon#wrote, iclass 10, count 0 2006.286.05:44:36.09#ibcon#about to read 3, iclass 10, count 0 2006.286.05:44:36.33#ibcon#read 3, iclass 10, count 0 2006.286.05:44:36.33#ibcon#about to read 4, iclass 10, count 0 2006.286.05:44:36.33#ibcon#read 4, iclass 10, count 0 2006.286.05:44:36.33#ibcon#about to read 5, iclass 10, count 0 2006.286.05:44:36.33#ibcon#read 5, iclass 10, count 0 2006.286.05:44:36.33#ibcon#about to read 6, iclass 10, count 0 2006.286.05:44:36.33#ibcon#read 6, iclass 10, count 0 2006.286.05:44:36.33#ibcon#end of sib2, iclass 10, count 0 2006.286.05:44:36.33#ibcon#*mode == 0, iclass 10, count 0 2006.286.05:44:36.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.286.05:44:36.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.05:44:36.33#ibcon#*before write, iclass 10, count 0 2006.286.05:44:36.33#ibcon#enter sib2, iclass 10, count 0 2006.286.05:44:36.33#ibcon#flushed, iclass 10, count 0 2006.286.05:44:36.33#ibcon#about to write, iclass 10, count 0 2006.286.05:44:36.33#ibcon#wrote, iclass 10, count 0 2006.286.05:44:36.33#ibcon#about to read 3, iclass 10, count 0 2006.286.05:44:36.37#ibcon#read 3, iclass 10, count 0 2006.286.05:44:36.37#ibcon#about to read 4, iclass 10, count 0 2006.286.05:44:36.37#ibcon#read 4, iclass 10, count 0 2006.286.05:44:36.37#ibcon#about to read 5, iclass 10, count 0 2006.286.05:44:36.37#ibcon#read 5, iclass 10, count 0 2006.286.05:44:36.37#ibcon#about to read 6, iclass 10, count 0 2006.286.05:44:36.37#ibcon#read 6, iclass 10, count 0 2006.286.05:44:36.37#ibcon#end of sib2, iclass 10, count 0 2006.286.05:44:36.37#ibcon#*after write, iclass 10, count 0 2006.286.05:44:36.37#ibcon#*before return 0, iclass 10, count 0 2006.286.05:44:36.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:44:36.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.286.05:44:36.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.286.05:44:36.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.286.05:44:36.37$vck44/vb=7,4 2006.286.05:44:36.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.286.05:44:36.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.286.05:44:36.37#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:36.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:44:36.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:44:36.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:44:36.37#ibcon#enter wrdev, iclass 12, count 2 2006.286.05:44:36.37#ibcon#first serial, iclass 12, count 2 2006.286.05:44:36.37#ibcon#enter sib2, iclass 12, count 2 2006.286.05:44:36.37#ibcon#flushed, iclass 12, count 2 2006.286.05:44:36.37#ibcon#about to write, iclass 12, count 2 2006.286.05:44:36.37#ibcon#wrote, iclass 12, count 2 2006.286.05:44:36.37#ibcon#about to read 3, iclass 12, count 2 2006.286.05:44:36.39#ibcon#read 3, iclass 12, count 2 2006.286.05:44:36.39#ibcon#about to read 4, iclass 12, count 2 2006.286.05:44:36.39#ibcon#read 4, iclass 12, count 2 2006.286.05:44:36.39#ibcon#about to read 5, iclass 12, count 2 2006.286.05:44:36.39#ibcon#read 5, iclass 12, count 2 2006.286.05:44:36.39#ibcon#about to read 6, iclass 12, count 2 2006.286.05:44:36.39#ibcon#read 6, iclass 12, count 2 2006.286.05:44:36.39#ibcon#end of sib2, iclass 12, count 2 2006.286.05:44:36.39#ibcon#*mode == 0, iclass 12, count 2 2006.286.05:44:36.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.286.05:44:36.39#ibcon#[27=AT07-04\r\n] 2006.286.05:44:36.39#ibcon#*before write, iclass 12, count 2 2006.286.05:44:36.39#ibcon#enter sib2, iclass 12, count 2 2006.286.05:44:36.39#ibcon#flushed, iclass 12, count 2 2006.286.05:44:36.39#ibcon#about to write, iclass 12, count 2 2006.286.05:44:36.39#ibcon#wrote, iclass 12, count 2 2006.286.05:44:36.39#ibcon#about to read 3, iclass 12, count 2 2006.286.05:44:36.42#ibcon#read 3, iclass 12, count 2 2006.286.05:44:36.42#ibcon#about to read 4, iclass 12, count 2 2006.286.05:44:36.42#ibcon#read 4, iclass 12, count 2 2006.286.05:44:36.42#ibcon#about to read 5, iclass 12, count 2 2006.286.05:44:36.42#ibcon#read 5, iclass 12, count 2 2006.286.05:44:36.42#ibcon#about to read 6, iclass 12, count 2 2006.286.05:44:36.42#ibcon#read 6, iclass 12, count 2 2006.286.05:44:36.42#ibcon#end of sib2, iclass 12, count 2 2006.286.05:44:36.42#ibcon#*after write, iclass 12, count 2 2006.286.05:44:36.42#ibcon#*before return 0, iclass 12, count 2 2006.286.05:44:36.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:44:36.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.286.05:44:36.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.286.05:44:36.42#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:36.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:44:36.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:44:36.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:44:36.54#ibcon#enter wrdev, iclass 12, count 0 2006.286.05:44:36.54#ibcon#first serial, iclass 12, count 0 2006.286.05:44:36.54#ibcon#enter sib2, iclass 12, count 0 2006.286.05:44:36.54#ibcon#flushed, iclass 12, count 0 2006.286.05:44:36.54#ibcon#about to write, iclass 12, count 0 2006.286.05:44:36.54#ibcon#wrote, iclass 12, count 0 2006.286.05:44:36.54#ibcon#about to read 3, iclass 12, count 0 2006.286.05:44:36.56#ibcon#read 3, iclass 12, count 0 2006.286.05:44:36.56#ibcon#about to read 4, iclass 12, count 0 2006.286.05:44:36.56#ibcon#read 4, iclass 12, count 0 2006.286.05:44:36.56#ibcon#about to read 5, iclass 12, count 0 2006.286.05:44:36.56#ibcon#read 5, iclass 12, count 0 2006.286.05:44:36.56#ibcon#about to read 6, iclass 12, count 0 2006.286.05:44:36.56#ibcon#read 6, iclass 12, count 0 2006.286.05:44:36.56#ibcon#end of sib2, iclass 12, count 0 2006.286.05:44:36.56#ibcon#*mode == 0, iclass 12, count 0 2006.286.05:44:36.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.286.05:44:36.56#ibcon#[27=USB\r\n] 2006.286.05:44:36.56#ibcon#*before write, iclass 12, count 0 2006.286.05:44:36.56#ibcon#enter sib2, iclass 12, count 0 2006.286.05:44:36.56#ibcon#flushed, iclass 12, count 0 2006.286.05:44:36.56#ibcon#about to write, iclass 12, count 0 2006.286.05:44:36.56#ibcon#wrote, iclass 12, count 0 2006.286.05:44:36.56#ibcon#about to read 3, iclass 12, count 0 2006.286.05:44:36.59#ibcon#read 3, iclass 12, count 0 2006.286.05:44:36.59#ibcon#about to read 4, iclass 12, count 0 2006.286.05:44:36.59#ibcon#read 4, iclass 12, count 0 2006.286.05:44:36.59#ibcon#about to read 5, iclass 12, count 0 2006.286.05:44:36.59#ibcon#read 5, iclass 12, count 0 2006.286.05:44:36.59#ibcon#about to read 6, iclass 12, count 0 2006.286.05:44:36.59#ibcon#read 6, iclass 12, count 0 2006.286.05:44:36.59#ibcon#end of sib2, iclass 12, count 0 2006.286.05:44:36.59#ibcon#*after write, iclass 12, count 0 2006.286.05:44:36.59#ibcon#*before return 0, iclass 12, count 0 2006.286.05:44:36.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:44:36.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.286.05:44:36.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.286.05:44:36.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.286.05:44:36.59$vck44/vblo=8,744.99 2006.286.05:44:36.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.286.05:44:36.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.286.05:44:36.59#ibcon#ireg 17 cls_cnt 0 2006.286.05:44:36.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:44:36.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:44:36.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:44:36.59#ibcon#enter wrdev, iclass 14, count 0 2006.286.05:44:36.59#ibcon#first serial, iclass 14, count 0 2006.286.05:44:36.59#ibcon#enter sib2, iclass 14, count 0 2006.286.05:44:36.59#ibcon#flushed, iclass 14, count 0 2006.286.05:44:36.59#ibcon#about to write, iclass 14, count 0 2006.286.05:44:36.59#ibcon#wrote, iclass 14, count 0 2006.286.05:44:36.59#ibcon#about to read 3, iclass 14, count 0 2006.286.05:44:36.61#ibcon#read 3, iclass 14, count 0 2006.286.05:44:36.61#ibcon#about to read 4, iclass 14, count 0 2006.286.05:44:36.61#ibcon#read 4, iclass 14, count 0 2006.286.05:44:36.61#ibcon#about to read 5, iclass 14, count 0 2006.286.05:44:36.61#ibcon#read 5, iclass 14, count 0 2006.286.05:44:36.61#ibcon#about to read 6, iclass 14, count 0 2006.286.05:44:36.61#ibcon#read 6, iclass 14, count 0 2006.286.05:44:36.61#ibcon#end of sib2, iclass 14, count 0 2006.286.05:44:36.61#ibcon#*mode == 0, iclass 14, count 0 2006.286.05:44:36.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.286.05:44:36.61#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.05:44:36.61#ibcon#*before write, iclass 14, count 0 2006.286.05:44:36.61#ibcon#enter sib2, iclass 14, count 0 2006.286.05:44:36.61#ibcon#flushed, iclass 14, count 0 2006.286.05:44:36.61#ibcon#about to write, iclass 14, count 0 2006.286.05:44:36.61#ibcon#wrote, iclass 14, count 0 2006.286.05:44:36.61#ibcon#about to read 3, iclass 14, count 0 2006.286.05:44:36.65#ibcon#read 3, iclass 14, count 0 2006.286.05:44:36.65#ibcon#about to read 4, iclass 14, count 0 2006.286.05:44:36.65#ibcon#read 4, iclass 14, count 0 2006.286.05:44:36.65#ibcon#about to read 5, iclass 14, count 0 2006.286.05:44:36.65#ibcon#read 5, iclass 14, count 0 2006.286.05:44:36.65#ibcon#about to read 6, iclass 14, count 0 2006.286.05:44:36.65#ibcon#read 6, iclass 14, count 0 2006.286.05:44:36.65#ibcon#end of sib2, iclass 14, count 0 2006.286.05:44:36.65#ibcon#*after write, iclass 14, count 0 2006.286.05:44:36.65#ibcon#*before return 0, iclass 14, count 0 2006.286.05:44:36.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:44:36.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.286.05:44:36.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.286.05:44:36.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.286.05:44:36.65$vck44/vb=8,4 2006.286.05:44:36.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.286.05:44:36.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.286.05:44:36.65#ibcon#ireg 11 cls_cnt 2 2006.286.05:44:36.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:44:36.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:44:36.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:44:36.71#ibcon#enter wrdev, iclass 16, count 2 2006.286.05:44:36.71#ibcon#first serial, iclass 16, count 2 2006.286.05:44:36.71#ibcon#enter sib2, iclass 16, count 2 2006.286.05:44:36.71#ibcon#flushed, iclass 16, count 2 2006.286.05:44:36.71#ibcon#about to write, iclass 16, count 2 2006.286.05:44:36.71#ibcon#wrote, iclass 16, count 2 2006.286.05:44:36.71#ibcon#about to read 3, iclass 16, count 2 2006.286.05:44:36.73#ibcon#read 3, iclass 16, count 2 2006.286.05:44:36.73#ibcon#about to read 4, iclass 16, count 2 2006.286.05:44:36.73#ibcon#read 4, iclass 16, count 2 2006.286.05:44:36.73#ibcon#about to read 5, iclass 16, count 2 2006.286.05:44:36.73#ibcon#read 5, iclass 16, count 2 2006.286.05:44:36.73#ibcon#about to read 6, iclass 16, count 2 2006.286.05:44:36.73#ibcon#read 6, iclass 16, count 2 2006.286.05:44:36.73#ibcon#end of sib2, iclass 16, count 2 2006.286.05:44:36.73#ibcon#*mode == 0, iclass 16, count 2 2006.286.05:44:36.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.286.05:44:36.73#ibcon#[27=AT08-04\r\n] 2006.286.05:44:36.73#ibcon#*before write, iclass 16, count 2 2006.286.05:44:36.73#ibcon#enter sib2, iclass 16, count 2 2006.286.05:44:36.73#ibcon#flushed, iclass 16, count 2 2006.286.05:44:36.73#ibcon#about to write, iclass 16, count 2 2006.286.05:44:36.73#ibcon#wrote, iclass 16, count 2 2006.286.05:44:36.73#ibcon#about to read 3, iclass 16, count 2 2006.286.05:44:36.76#ibcon#read 3, iclass 16, count 2 2006.286.05:44:36.76#ibcon#about to read 4, iclass 16, count 2 2006.286.05:44:36.76#ibcon#read 4, iclass 16, count 2 2006.286.05:44:36.76#ibcon#about to read 5, iclass 16, count 2 2006.286.05:44:36.76#ibcon#read 5, iclass 16, count 2 2006.286.05:44:36.76#ibcon#about to read 6, iclass 16, count 2 2006.286.05:44:36.76#ibcon#read 6, iclass 16, count 2 2006.286.05:44:36.76#ibcon#end of sib2, iclass 16, count 2 2006.286.05:44:36.76#ibcon#*after write, iclass 16, count 2 2006.286.05:44:36.76#ibcon#*before return 0, iclass 16, count 2 2006.286.05:44:36.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:44:36.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.286.05:44:36.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.286.05:44:36.76#ibcon#ireg 7 cls_cnt 0 2006.286.05:44:36.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:44:36.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:44:36.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:44:36.88#ibcon#enter wrdev, iclass 16, count 0 2006.286.05:44:36.88#ibcon#first serial, iclass 16, count 0 2006.286.05:44:36.88#ibcon#enter sib2, iclass 16, count 0 2006.286.05:44:36.88#ibcon#flushed, iclass 16, count 0 2006.286.05:44:36.88#ibcon#about to write, iclass 16, count 0 2006.286.05:44:36.88#ibcon#wrote, iclass 16, count 0 2006.286.05:44:36.88#ibcon#about to read 3, iclass 16, count 0 2006.286.05:44:36.90#ibcon#read 3, iclass 16, count 0 2006.286.05:44:36.90#ibcon#about to read 4, iclass 16, count 0 2006.286.05:44:36.90#ibcon#read 4, iclass 16, count 0 2006.286.05:44:36.90#ibcon#about to read 5, iclass 16, count 0 2006.286.05:44:36.90#ibcon#read 5, iclass 16, count 0 2006.286.05:44:36.90#ibcon#about to read 6, iclass 16, count 0 2006.286.05:44:36.90#ibcon#read 6, iclass 16, count 0 2006.286.05:44:36.90#ibcon#end of sib2, iclass 16, count 0 2006.286.05:44:36.90#ibcon#*mode == 0, iclass 16, count 0 2006.286.05:44:36.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.286.05:44:36.90#ibcon#[27=USB\r\n] 2006.286.05:44:36.90#ibcon#*before write, iclass 16, count 0 2006.286.05:44:36.90#ibcon#enter sib2, iclass 16, count 0 2006.286.05:44:36.90#ibcon#flushed, iclass 16, count 0 2006.286.05:44:36.90#ibcon#about to write, iclass 16, count 0 2006.286.05:44:36.90#ibcon#wrote, iclass 16, count 0 2006.286.05:44:36.90#ibcon#about to read 3, iclass 16, count 0 2006.286.05:44:36.93#ibcon#read 3, iclass 16, count 0 2006.286.05:44:36.93#ibcon#about to read 4, iclass 16, count 0 2006.286.05:44:36.93#ibcon#read 4, iclass 16, count 0 2006.286.05:44:36.93#ibcon#about to read 5, iclass 16, count 0 2006.286.05:44:36.93#ibcon#read 5, iclass 16, count 0 2006.286.05:44:36.93#ibcon#about to read 6, iclass 16, count 0 2006.286.05:44:36.93#ibcon#read 6, iclass 16, count 0 2006.286.05:44:36.93#ibcon#end of sib2, iclass 16, count 0 2006.286.05:44:36.93#ibcon#*after write, iclass 16, count 0 2006.286.05:44:36.93#ibcon#*before return 0, iclass 16, count 0 2006.286.05:44:36.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:44:36.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.286.05:44:36.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.286.05:44:36.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.286.05:44:36.93$vck44/vabw=wide 2006.286.05:44:36.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.286.05:44:36.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.286.05:44:36.93#ibcon#ireg 8 cls_cnt 0 2006.286.05:44:36.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:44:36.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:44:36.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:44:36.93#ibcon#enter wrdev, iclass 18, count 0 2006.286.05:44:36.93#ibcon#first serial, iclass 18, count 0 2006.286.05:44:36.93#ibcon#enter sib2, iclass 18, count 0 2006.286.05:44:36.93#ibcon#flushed, iclass 18, count 0 2006.286.05:44:36.93#ibcon#about to write, iclass 18, count 0 2006.286.05:44:36.93#ibcon#wrote, iclass 18, count 0 2006.286.05:44:36.93#ibcon#about to read 3, iclass 18, count 0 2006.286.05:44:36.95#ibcon#read 3, iclass 18, count 0 2006.286.05:44:36.95#ibcon#about to read 4, iclass 18, count 0 2006.286.05:44:36.95#ibcon#read 4, iclass 18, count 0 2006.286.05:44:36.95#ibcon#about to read 5, iclass 18, count 0 2006.286.05:44:36.95#ibcon#read 5, iclass 18, count 0 2006.286.05:44:36.95#ibcon#about to read 6, iclass 18, count 0 2006.286.05:44:36.95#ibcon#read 6, iclass 18, count 0 2006.286.05:44:36.95#ibcon#end of sib2, iclass 18, count 0 2006.286.05:44:36.95#ibcon#*mode == 0, iclass 18, count 0 2006.286.05:44:36.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.286.05:44:36.95#ibcon#[25=BW32\r\n] 2006.286.05:44:36.95#ibcon#*before write, iclass 18, count 0 2006.286.05:44:36.95#ibcon#enter sib2, iclass 18, count 0 2006.286.05:44:36.95#ibcon#flushed, iclass 18, count 0 2006.286.05:44:36.95#ibcon#about to write, iclass 18, count 0 2006.286.05:44:36.95#ibcon#wrote, iclass 18, count 0 2006.286.05:44:36.95#ibcon#about to read 3, iclass 18, count 0 2006.286.05:44:36.98#ibcon#read 3, iclass 18, count 0 2006.286.05:44:36.98#ibcon#about to read 4, iclass 18, count 0 2006.286.05:44:36.98#ibcon#read 4, iclass 18, count 0 2006.286.05:44:36.98#ibcon#about to read 5, iclass 18, count 0 2006.286.05:44:36.98#ibcon#read 5, iclass 18, count 0 2006.286.05:44:36.98#ibcon#about to read 6, iclass 18, count 0 2006.286.05:44:36.98#ibcon#read 6, iclass 18, count 0 2006.286.05:44:36.98#ibcon#end of sib2, iclass 18, count 0 2006.286.05:44:36.98#ibcon#*after write, iclass 18, count 0 2006.286.05:44:36.98#ibcon#*before return 0, iclass 18, count 0 2006.286.05:44:36.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:44:36.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.286.05:44:36.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.286.05:44:36.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.286.05:44:36.98$vck44/vbbw=wide 2006.286.05:44:36.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.286.05:44:36.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.286.05:44:36.98#ibcon#ireg 8 cls_cnt 0 2006.286.05:44:36.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:44:37.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:44:37.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:44:37.05#ibcon#enter wrdev, iclass 20, count 0 2006.286.05:44:37.05#ibcon#first serial, iclass 20, count 0 2006.286.05:44:37.05#ibcon#enter sib2, iclass 20, count 0 2006.286.05:44:37.05#ibcon#flushed, iclass 20, count 0 2006.286.05:44:37.05#ibcon#about to write, iclass 20, count 0 2006.286.05:44:37.05#ibcon#wrote, iclass 20, count 0 2006.286.05:44:37.05#ibcon#about to read 3, iclass 20, count 0 2006.286.05:44:37.07#ibcon#read 3, iclass 20, count 0 2006.286.05:44:37.07#ibcon#about to read 4, iclass 20, count 0 2006.286.05:44:37.07#ibcon#read 4, iclass 20, count 0 2006.286.05:44:37.07#ibcon#about to read 5, iclass 20, count 0 2006.286.05:44:37.07#ibcon#read 5, iclass 20, count 0 2006.286.05:44:37.07#ibcon#about to read 6, iclass 20, count 0 2006.286.05:44:37.07#ibcon#read 6, iclass 20, count 0 2006.286.05:44:37.07#ibcon#end of sib2, iclass 20, count 0 2006.286.05:44:37.07#ibcon#*mode == 0, iclass 20, count 0 2006.286.05:44:37.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.286.05:44:37.07#ibcon#[27=BW32\r\n] 2006.286.05:44:37.07#ibcon#*before write, iclass 20, count 0 2006.286.05:44:37.07#ibcon#enter sib2, iclass 20, count 0 2006.286.05:44:37.07#ibcon#flushed, iclass 20, count 0 2006.286.05:44:37.07#ibcon#about to write, iclass 20, count 0 2006.286.05:44:37.07#ibcon#wrote, iclass 20, count 0 2006.286.05:44:37.07#ibcon#about to read 3, iclass 20, count 0 2006.286.05:44:37.10#ibcon#read 3, iclass 20, count 0 2006.286.05:44:37.10#ibcon#about to read 4, iclass 20, count 0 2006.286.05:44:37.10#ibcon#read 4, iclass 20, count 0 2006.286.05:44:37.10#ibcon#about to read 5, iclass 20, count 0 2006.286.05:44:37.10#ibcon#read 5, iclass 20, count 0 2006.286.05:44:37.10#ibcon#about to read 6, iclass 20, count 0 2006.286.05:44:37.10#ibcon#read 6, iclass 20, count 0 2006.286.05:44:37.10#ibcon#end of sib2, iclass 20, count 0 2006.286.05:44:37.10#ibcon#*after write, iclass 20, count 0 2006.286.05:44:37.10#ibcon#*before return 0, iclass 20, count 0 2006.286.05:44:37.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:44:37.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.286.05:44:37.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.286.05:44:37.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.286.05:44:37.10$setupk4/ifdk4 2006.286.05:44:37.10$ifdk4/lo= 2006.286.05:44:37.10$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.05:44:37.10$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.05:44:37.23$ifdk4/patch= 2006.286.05:44:37.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.05:44:37.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.05:44:37.23$setupk4/!*+20s 2006.286.05:44:41.07#abcon#<5=/04 3.8 7.5 20.73 791015.3\r\n> 2006.286.05:44:41.09#abcon#{5=INTERFACE CLEAR} 2006.286.05:44:41.15#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:44:50.56$setupk4/"tpicd 2006.286.05:44:50.56$setupk4/echo=off 2006.286.05:44:50.56$setupk4/xlog=off 2006.286.05:44:50.56:!2006.286.05:47:40 2006.286.05:45:39.14#trakl#Source acquired 2006.286.05:45:40.14#flagr#flagr/antenna,acquired 2006.286.05:46:10.14#trakl#Off source 2006.286.05:46:10.14?ERROR st -7 Antenna off-source! 2006.286.05:46:10.14#trakl#az 245.417 el 85.642 azerr*cos(el) -0.0006 elerr -0.0162 2006.286.05:46:10.14#flagr#flagr/antenna,off-source 2006.286.05:46:16.14#trakl#Source re-acquired 2006.286.05:46:16.14#flagr#flagr/antenna,re-acquired 2006.286.05:46:44.14#trakl#Off source 2006.286.05:46:44.14?ERROR st -7 Antenna off-source! 2006.286.05:46:44.14#trakl#az 246.111 el 85.537 azerr*cos(el) -0.0001 elerr -0.0204 2006.286.05:46:46.14#flagr#flagr/antenna,off-source 2006.286.05:46:50.14#trakl#Source re-acquired 2006.286.05:46:52.14#flagr#flagr/antenna,re-acquired 2006.286.05:47:40.00:preob 2006.286.05:47:41.13/onsource/TRACKING 2006.286.05:47:41.13:!2006.286.05:47:50 2006.286.05:47:50.00:"tape 2006.286.05:47:50.00:"st=record 2006.286.05:47:50.00:data_valid=on 2006.286.05:47:50.00:midob 2006.286.05:47:50.13/onsource/TRACKING 2006.286.05:47:50.13/wx/20.65,1015.2,79 2006.286.05:47:50.19/cable/+6.4949E-03 2006.286.05:47:51.28/va/01,07,usb,yes,31,34 2006.286.05:47:51.28/va/02,06,usb,yes,32,32 2006.286.05:47:51.28/va/03,07,usb,yes,31,33 2006.286.05:47:51.28/va/04,06,usb,yes,32,34 2006.286.05:47:51.28/va/05,03,usb,yes,32,32 2006.286.05:47:51.28/va/06,04,usb,yes,29,28 2006.286.05:47:51.28/va/07,04,usb,yes,29,30 2006.286.05:47:51.28/va/08,03,usb,yes,30,37 2006.286.05:47:51.51/valo/01,524.99,yes,locked 2006.286.05:47:51.51/valo/02,534.99,yes,locked 2006.286.05:47:51.51/valo/03,564.99,yes,locked 2006.286.05:47:51.51/valo/04,624.99,yes,locked 2006.286.05:47:51.51/valo/05,734.99,yes,locked 2006.286.05:47:51.51/valo/06,814.99,yes,locked 2006.286.05:47:51.51/valo/07,864.99,yes,locked 2006.286.05:47:51.51/valo/08,884.99,yes,locked 2006.286.05:47:52.60/vb/01,04,usb,yes,30,28 2006.286.05:47:52.60/vb/02,05,usb,yes,28,28 2006.286.05:47:52.60/vb/03,04,usb,yes,29,32 2006.286.05:47:52.60/vb/04,05,usb,yes,30,29 2006.286.05:47:52.60/vb/05,04,usb,yes,26,28 2006.286.05:47:52.60/vb/06,03,usb,yes,37,33 2006.286.05:47:52.60/vb/07,04,usb,yes,30,30 2006.286.05:47:52.60/vb/08,04,usb,yes,27,31 2006.286.05:47:52.83/vblo/01,629.99,yes,locked 2006.286.05:47:52.83/vblo/02,634.99,yes,locked 2006.286.05:47:52.83/vblo/03,649.99,yes,locked 2006.286.05:47:52.83/vblo/04,679.99,yes,locked 2006.286.05:47:52.83/vblo/05,709.99,yes,locked 2006.286.05:47:52.83/vblo/06,719.99,yes,locked 2006.286.05:47:52.83/vblo/07,734.99,yes,locked 2006.286.05:47:52.83/vblo/08,744.99,yes,locked 2006.286.05:47:52.98/vabw/8 2006.286.05:47:53.13/vbbw/8 2006.286.05:47:53.22/xfe/off,on,12.0 2006.286.05:47:53.61/ifatt/23,28,28,28 2006.286.05:47:54.07/fmout-gps/S +2.60E-07 2006.286.05:47:54.09:!2006.286.05:48:40 2006.286.05:48:40.00:data_valid=off 2006.286.05:48:40.00:"et 2006.286.05:48:40.00:!+3s 2006.286.05:48:43.01:"tape 2006.286.05:48:43.01:postob 2006.286.05:48:43.11/cable/+6.4942E-03 2006.286.05:48:43.11/wx/20.62,1015.3,80 2006.286.05:48:44.07/fmout-gps/S +2.59E-07 2006.286.05:48:44.07:scan_name=286-0553,jd0610,100 2006.286.05:48:44.07:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.286.05:48:45.13#flagr#flagr/antenna,new-source 2006.286.05:48:45.13:checkk5 2006.286.05:48:45.54/chk_autoobs//k5ts1/ autoobs is running! 2006.286.05:48:45.98/chk_autoobs//k5ts2/ autoobs is running! 2006.286.05:48:46.39/chk_autoobs//k5ts3/ autoobs is running! 2006.286.05:48:46.92/chk_autoobs//k5ts4/ autoobs is running! 2006.286.05:48:47.37/chk_obsdata//k5ts1/T2860547??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.05:48:47.84/chk_obsdata//k5ts2/T2860547??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.05:48:48.22/chk_obsdata//k5ts3/T2860547??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.05:48:48.74/chk_obsdata//k5ts4/T2860547??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.286.05:48:49.76/k5log//k5ts1_log_newline 2006.286.05:48:50.61/k5log//k5ts2_log_newline 2006.286.05:48:51.71/k5log//k5ts3_log_newline 2006.286.05:48:52.79/k5log//k5ts4_log_newline 2006.286.05:48:52.81/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.05:48:52.81:setupk4=1 2006.286.05:48:52.81$setupk4/echo=on 2006.286.05:48:52.81$setupk4/pcalon 2006.286.05:48:52.81$pcalon/"no phase cal control is implemented here 2006.286.05:48:52.81$setupk4/"tpicd=stop 2006.286.05:48:52.81$setupk4/"rec=synch_on 2006.286.05:48:52.81$setupk4/"rec_mode=128 2006.286.05:48:52.81$setupk4/!* 2006.286.05:48:52.81$setupk4/recpk4 2006.286.05:48:52.81$recpk4/recpatch= 2006.286.05:48:52.81$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.286.05:48:52.81$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.286.05:48:52.81$setupk4/vck44 2006.286.05:48:52.81$vck44/valo=1,524.99 2006.286.05:48:52.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.05:48:52.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.05:48:52.81#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:52.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:48:52.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:48:52.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:48:52.81#ibcon#enter wrdev, iclass 21, count 0 2006.286.05:48:52.81#ibcon#first serial, iclass 21, count 0 2006.286.05:48:52.81#ibcon#enter sib2, iclass 21, count 0 2006.286.05:48:52.81#ibcon#flushed, iclass 21, count 0 2006.286.05:48:52.81#ibcon#about to write, iclass 21, count 0 2006.286.05:48:52.81#ibcon#wrote, iclass 21, count 0 2006.286.05:48:52.81#ibcon#about to read 3, iclass 21, count 0 2006.286.05:48:52.83#ibcon#read 3, iclass 21, count 0 2006.286.05:48:52.83#ibcon#about to read 4, iclass 21, count 0 2006.286.05:48:52.83#ibcon#read 4, iclass 21, count 0 2006.286.05:48:52.83#ibcon#about to read 5, iclass 21, count 0 2006.286.05:48:52.83#ibcon#read 5, iclass 21, count 0 2006.286.05:48:52.83#ibcon#about to read 6, iclass 21, count 0 2006.286.05:48:52.83#ibcon#read 6, iclass 21, count 0 2006.286.05:48:52.83#ibcon#end of sib2, iclass 21, count 0 2006.286.05:48:52.83#ibcon#*mode == 0, iclass 21, count 0 2006.286.05:48:52.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.05:48:52.83#ibcon#[26=FRQ=01,524.99\r\n] 2006.286.05:48:52.83#ibcon#*before write, iclass 21, count 0 2006.286.05:48:52.83#ibcon#enter sib2, iclass 21, count 0 2006.286.05:48:52.83#ibcon#flushed, iclass 21, count 0 2006.286.05:48:52.83#ibcon#about to write, iclass 21, count 0 2006.286.05:48:52.83#ibcon#wrote, iclass 21, count 0 2006.286.05:48:52.83#ibcon#about to read 3, iclass 21, count 0 2006.286.05:48:52.88#ibcon#read 3, iclass 21, count 0 2006.286.05:48:52.88#ibcon#about to read 4, iclass 21, count 0 2006.286.05:48:52.88#ibcon#read 4, iclass 21, count 0 2006.286.05:48:52.88#ibcon#about to read 5, iclass 21, count 0 2006.286.05:48:52.88#ibcon#read 5, iclass 21, count 0 2006.286.05:48:52.88#ibcon#about to read 6, iclass 21, count 0 2006.286.05:48:52.88#ibcon#read 6, iclass 21, count 0 2006.286.05:48:52.88#ibcon#end of sib2, iclass 21, count 0 2006.286.05:48:52.88#ibcon#*after write, iclass 21, count 0 2006.286.05:48:52.88#ibcon#*before return 0, iclass 21, count 0 2006.286.05:48:52.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:48:52.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:48:52.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.05:48:52.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.05:48:52.88$vck44/va=1,7 2006.286.05:48:52.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.05:48:52.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.05:48:52.88#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:52.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.05:48:52.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.05:48:52.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.05:48:52.88#ibcon#enter wrdev, iclass 23, count 2 2006.286.05:48:52.88#ibcon#first serial, iclass 23, count 2 2006.286.05:48:52.88#ibcon#enter sib2, iclass 23, count 2 2006.286.05:48:52.88#ibcon#flushed, iclass 23, count 2 2006.286.05:48:52.88#ibcon#about to write, iclass 23, count 2 2006.286.05:48:52.88#ibcon#wrote, iclass 23, count 2 2006.286.05:48:52.88#ibcon#about to read 3, iclass 23, count 2 2006.286.05:48:52.90#ibcon#read 3, iclass 23, count 2 2006.286.05:48:52.90#ibcon#about to read 4, iclass 23, count 2 2006.286.05:48:52.90#ibcon#read 4, iclass 23, count 2 2006.286.05:48:52.90#ibcon#about to read 5, iclass 23, count 2 2006.286.05:48:52.90#ibcon#read 5, iclass 23, count 2 2006.286.05:48:52.90#ibcon#about to read 6, iclass 23, count 2 2006.286.05:48:52.90#ibcon#read 6, iclass 23, count 2 2006.286.05:48:52.90#ibcon#end of sib2, iclass 23, count 2 2006.286.05:48:52.90#ibcon#*mode == 0, iclass 23, count 2 2006.286.05:48:52.90#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.05:48:52.90#ibcon#[25=AT01-07\r\n] 2006.286.05:48:52.90#ibcon#*before write, iclass 23, count 2 2006.286.05:48:52.90#ibcon#enter sib2, iclass 23, count 2 2006.286.05:48:52.90#ibcon#flushed, iclass 23, count 2 2006.286.05:48:52.90#ibcon#about to write, iclass 23, count 2 2006.286.05:48:52.90#ibcon#wrote, iclass 23, count 2 2006.286.05:48:52.90#ibcon#about to read 3, iclass 23, count 2 2006.286.05:48:52.93#ibcon#read 3, iclass 23, count 2 2006.286.05:48:52.93#ibcon#about to read 4, iclass 23, count 2 2006.286.05:48:52.93#ibcon#read 4, iclass 23, count 2 2006.286.05:48:52.93#ibcon#about to read 5, iclass 23, count 2 2006.286.05:48:52.93#ibcon#read 5, iclass 23, count 2 2006.286.05:48:52.93#ibcon#about to read 6, iclass 23, count 2 2006.286.05:48:52.93#ibcon#read 6, iclass 23, count 2 2006.286.05:48:52.93#ibcon#end of sib2, iclass 23, count 2 2006.286.05:48:52.93#ibcon#*after write, iclass 23, count 2 2006.286.05:48:52.93#ibcon#*before return 0, iclass 23, count 2 2006.286.05:48:52.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.05:48:52.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.05:48:52.93#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.05:48:52.93#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:52.93#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.05:48:53.05#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.05:48:53.05#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.05:48:53.05#ibcon#enter wrdev, iclass 23, count 0 2006.286.05:48:53.05#ibcon#first serial, iclass 23, count 0 2006.286.05:48:53.05#ibcon#enter sib2, iclass 23, count 0 2006.286.05:48:53.05#ibcon#flushed, iclass 23, count 0 2006.286.05:48:53.05#ibcon#about to write, iclass 23, count 0 2006.286.05:48:53.05#ibcon#wrote, iclass 23, count 0 2006.286.05:48:53.05#ibcon#about to read 3, iclass 23, count 0 2006.286.05:48:53.07#ibcon#read 3, iclass 23, count 0 2006.286.05:48:53.07#ibcon#about to read 4, iclass 23, count 0 2006.286.05:48:53.07#ibcon#read 4, iclass 23, count 0 2006.286.05:48:53.07#ibcon#about to read 5, iclass 23, count 0 2006.286.05:48:53.07#ibcon#read 5, iclass 23, count 0 2006.286.05:48:53.07#ibcon#about to read 6, iclass 23, count 0 2006.286.05:48:53.07#ibcon#read 6, iclass 23, count 0 2006.286.05:48:53.07#ibcon#end of sib2, iclass 23, count 0 2006.286.05:48:53.07#ibcon#*mode == 0, iclass 23, count 0 2006.286.05:48:53.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.05:48:53.07#ibcon#[25=USB\r\n] 2006.286.05:48:53.07#ibcon#*before write, iclass 23, count 0 2006.286.05:48:53.07#ibcon#enter sib2, iclass 23, count 0 2006.286.05:48:53.07#ibcon#flushed, iclass 23, count 0 2006.286.05:48:53.07#ibcon#about to write, iclass 23, count 0 2006.286.05:48:53.07#ibcon#wrote, iclass 23, count 0 2006.286.05:48:53.07#ibcon#about to read 3, iclass 23, count 0 2006.286.05:48:53.10#ibcon#read 3, iclass 23, count 0 2006.286.05:48:53.10#ibcon#about to read 4, iclass 23, count 0 2006.286.05:48:53.10#ibcon#read 4, iclass 23, count 0 2006.286.05:48:53.10#ibcon#about to read 5, iclass 23, count 0 2006.286.05:48:53.10#ibcon#read 5, iclass 23, count 0 2006.286.05:48:53.10#ibcon#about to read 6, iclass 23, count 0 2006.286.05:48:53.10#ibcon#read 6, iclass 23, count 0 2006.286.05:48:53.10#ibcon#end of sib2, iclass 23, count 0 2006.286.05:48:53.10#ibcon#*after write, iclass 23, count 0 2006.286.05:48:53.10#ibcon#*before return 0, iclass 23, count 0 2006.286.05:48:53.10#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.05:48:53.10#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.05:48:53.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.05:48:53.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.05:48:53.10$vck44/valo=2,534.99 2006.286.05:48:53.10#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.05:48:53.10#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.05:48:53.10#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:53.10#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:48:53.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:48:53.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:48:53.10#ibcon#enter wrdev, iclass 25, count 0 2006.286.05:48:53.10#ibcon#first serial, iclass 25, count 0 2006.286.05:48:53.10#ibcon#enter sib2, iclass 25, count 0 2006.286.05:48:53.10#ibcon#flushed, iclass 25, count 0 2006.286.05:48:53.10#ibcon#about to write, iclass 25, count 0 2006.286.05:48:53.10#ibcon#wrote, iclass 25, count 0 2006.286.05:48:53.10#ibcon#about to read 3, iclass 25, count 0 2006.286.05:48:53.12#ibcon#read 3, iclass 25, count 0 2006.286.05:48:53.12#ibcon#about to read 4, iclass 25, count 0 2006.286.05:48:53.12#ibcon#read 4, iclass 25, count 0 2006.286.05:48:53.12#ibcon#about to read 5, iclass 25, count 0 2006.286.05:48:53.12#ibcon#read 5, iclass 25, count 0 2006.286.05:48:53.12#ibcon#about to read 6, iclass 25, count 0 2006.286.05:48:53.12#ibcon#read 6, iclass 25, count 0 2006.286.05:48:53.12#ibcon#end of sib2, iclass 25, count 0 2006.286.05:48:53.12#ibcon#*mode == 0, iclass 25, count 0 2006.286.05:48:53.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.05:48:53.12#ibcon#[26=FRQ=02,534.99\r\n] 2006.286.05:48:53.12#ibcon#*before write, iclass 25, count 0 2006.286.05:48:53.12#ibcon#enter sib2, iclass 25, count 0 2006.286.05:48:53.12#ibcon#flushed, iclass 25, count 0 2006.286.05:48:53.12#ibcon#about to write, iclass 25, count 0 2006.286.05:48:53.12#ibcon#wrote, iclass 25, count 0 2006.286.05:48:53.12#ibcon#about to read 3, iclass 25, count 0 2006.286.05:48:53.16#ibcon#read 3, iclass 25, count 0 2006.286.05:48:53.16#ibcon#about to read 4, iclass 25, count 0 2006.286.05:48:53.16#ibcon#read 4, iclass 25, count 0 2006.286.05:48:53.16#ibcon#about to read 5, iclass 25, count 0 2006.286.05:48:53.16#ibcon#read 5, iclass 25, count 0 2006.286.05:48:53.16#ibcon#about to read 6, iclass 25, count 0 2006.286.05:48:53.16#ibcon#read 6, iclass 25, count 0 2006.286.05:48:53.16#ibcon#end of sib2, iclass 25, count 0 2006.286.05:48:53.16#ibcon#*after write, iclass 25, count 0 2006.286.05:48:53.16#ibcon#*before return 0, iclass 25, count 0 2006.286.05:48:53.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:48:53.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:48:53.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.05:48:53.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.05:48:53.16$vck44/va=2,6 2006.286.05:48:53.16#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.05:48:53.16#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.05:48:53.16#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:53.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:48:53.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:48:53.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:48:53.22#ibcon#enter wrdev, iclass 27, count 2 2006.286.05:48:53.22#ibcon#first serial, iclass 27, count 2 2006.286.05:48:53.22#ibcon#enter sib2, iclass 27, count 2 2006.286.05:48:53.22#ibcon#flushed, iclass 27, count 2 2006.286.05:48:53.22#ibcon#about to write, iclass 27, count 2 2006.286.05:48:53.22#ibcon#wrote, iclass 27, count 2 2006.286.05:48:53.22#ibcon#about to read 3, iclass 27, count 2 2006.286.05:48:53.24#ibcon#read 3, iclass 27, count 2 2006.286.05:48:53.24#ibcon#about to read 4, iclass 27, count 2 2006.286.05:48:53.24#ibcon#read 4, iclass 27, count 2 2006.286.05:48:53.24#ibcon#about to read 5, iclass 27, count 2 2006.286.05:48:53.24#ibcon#read 5, iclass 27, count 2 2006.286.05:48:53.24#ibcon#about to read 6, iclass 27, count 2 2006.286.05:48:53.24#ibcon#read 6, iclass 27, count 2 2006.286.05:48:53.24#ibcon#end of sib2, iclass 27, count 2 2006.286.05:48:53.24#ibcon#*mode == 0, iclass 27, count 2 2006.286.05:48:53.24#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.05:48:53.24#ibcon#[25=AT02-06\r\n] 2006.286.05:48:53.24#ibcon#*before write, iclass 27, count 2 2006.286.05:48:53.24#ibcon#enter sib2, iclass 27, count 2 2006.286.05:48:53.24#ibcon#flushed, iclass 27, count 2 2006.286.05:48:53.24#ibcon#about to write, iclass 27, count 2 2006.286.05:48:53.24#ibcon#wrote, iclass 27, count 2 2006.286.05:48:53.24#ibcon#about to read 3, iclass 27, count 2 2006.286.05:48:53.27#ibcon#read 3, iclass 27, count 2 2006.286.05:48:53.27#ibcon#about to read 4, iclass 27, count 2 2006.286.05:48:53.27#ibcon#read 4, iclass 27, count 2 2006.286.05:48:53.27#ibcon#about to read 5, iclass 27, count 2 2006.286.05:48:53.27#ibcon#read 5, iclass 27, count 2 2006.286.05:48:53.27#ibcon#about to read 6, iclass 27, count 2 2006.286.05:48:53.27#ibcon#read 6, iclass 27, count 2 2006.286.05:48:53.27#ibcon#end of sib2, iclass 27, count 2 2006.286.05:48:53.27#ibcon#*after write, iclass 27, count 2 2006.286.05:48:53.27#ibcon#*before return 0, iclass 27, count 2 2006.286.05:48:53.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:48:53.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:48:53.27#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.05:48:53.27#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:53.27#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:48:53.39#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:48:53.39#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:48:53.39#ibcon#enter wrdev, iclass 27, count 0 2006.286.05:48:53.39#ibcon#first serial, iclass 27, count 0 2006.286.05:48:53.39#ibcon#enter sib2, iclass 27, count 0 2006.286.05:48:53.39#ibcon#flushed, iclass 27, count 0 2006.286.05:48:53.39#ibcon#about to write, iclass 27, count 0 2006.286.05:48:53.39#ibcon#wrote, iclass 27, count 0 2006.286.05:48:53.39#ibcon#about to read 3, iclass 27, count 0 2006.286.05:48:53.41#ibcon#read 3, iclass 27, count 0 2006.286.05:48:53.41#ibcon#about to read 4, iclass 27, count 0 2006.286.05:48:53.41#ibcon#read 4, iclass 27, count 0 2006.286.05:48:53.41#ibcon#about to read 5, iclass 27, count 0 2006.286.05:48:53.41#ibcon#read 5, iclass 27, count 0 2006.286.05:48:53.41#ibcon#about to read 6, iclass 27, count 0 2006.286.05:48:53.41#ibcon#read 6, iclass 27, count 0 2006.286.05:48:53.41#ibcon#end of sib2, iclass 27, count 0 2006.286.05:48:53.41#ibcon#*mode == 0, iclass 27, count 0 2006.286.05:48:53.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.05:48:53.41#ibcon#[25=USB\r\n] 2006.286.05:48:53.41#ibcon#*before write, iclass 27, count 0 2006.286.05:48:53.41#ibcon#enter sib2, iclass 27, count 0 2006.286.05:48:53.41#ibcon#flushed, iclass 27, count 0 2006.286.05:48:53.41#ibcon#about to write, iclass 27, count 0 2006.286.05:48:53.41#ibcon#wrote, iclass 27, count 0 2006.286.05:48:53.41#ibcon#about to read 3, iclass 27, count 0 2006.286.05:48:53.44#ibcon#read 3, iclass 27, count 0 2006.286.05:48:53.44#ibcon#about to read 4, iclass 27, count 0 2006.286.05:48:53.44#ibcon#read 4, iclass 27, count 0 2006.286.05:48:53.44#ibcon#about to read 5, iclass 27, count 0 2006.286.05:48:53.44#ibcon#read 5, iclass 27, count 0 2006.286.05:48:53.44#ibcon#about to read 6, iclass 27, count 0 2006.286.05:48:53.44#ibcon#read 6, iclass 27, count 0 2006.286.05:48:53.44#ibcon#end of sib2, iclass 27, count 0 2006.286.05:48:53.44#ibcon#*after write, iclass 27, count 0 2006.286.05:48:53.44#ibcon#*before return 0, iclass 27, count 0 2006.286.05:48:53.44#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:48:53.44#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:48:53.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.05:48:53.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.05:48:53.44$vck44/valo=3,564.99 2006.286.05:48:53.44#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.05:48:53.44#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.05:48:53.44#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:53.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:48:53.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:48:53.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:48:53.44#ibcon#enter wrdev, iclass 29, count 0 2006.286.05:48:53.44#ibcon#first serial, iclass 29, count 0 2006.286.05:48:53.44#ibcon#enter sib2, iclass 29, count 0 2006.286.05:48:53.44#ibcon#flushed, iclass 29, count 0 2006.286.05:48:53.44#ibcon#about to write, iclass 29, count 0 2006.286.05:48:53.44#ibcon#wrote, iclass 29, count 0 2006.286.05:48:53.44#ibcon#about to read 3, iclass 29, count 0 2006.286.05:48:53.46#ibcon#read 3, iclass 29, count 0 2006.286.05:48:53.46#ibcon#about to read 4, iclass 29, count 0 2006.286.05:48:53.46#ibcon#read 4, iclass 29, count 0 2006.286.05:48:53.46#ibcon#about to read 5, iclass 29, count 0 2006.286.05:48:53.46#ibcon#read 5, iclass 29, count 0 2006.286.05:48:53.46#ibcon#about to read 6, iclass 29, count 0 2006.286.05:48:53.46#ibcon#read 6, iclass 29, count 0 2006.286.05:48:53.46#ibcon#end of sib2, iclass 29, count 0 2006.286.05:48:53.46#ibcon#*mode == 0, iclass 29, count 0 2006.286.05:48:53.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.05:48:53.46#ibcon#[26=FRQ=03,564.99\r\n] 2006.286.05:48:53.46#ibcon#*before write, iclass 29, count 0 2006.286.05:48:53.46#ibcon#enter sib2, iclass 29, count 0 2006.286.05:48:53.46#ibcon#flushed, iclass 29, count 0 2006.286.05:48:53.46#ibcon#about to write, iclass 29, count 0 2006.286.05:48:53.46#ibcon#wrote, iclass 29, count 0 2006.286.05:48:53.46#ibcon#about to read 3, iclass 29, count 0 2006.286.05:48:53.50#ibcon#read 3, iclass 29, count 0 2006.286.05:48:53.50#ibcon#about to read 4, iclass 29, count 0 2006.286.05:48:53.50#ibcon#read 4, iclass 29, count 0 2006.286.05:48:53.50#ibcon#about to read 5, iclass 29, count 0 2006.286.05:48:53.50#ibcon#read 5, iclass 29, count 0 2006.286.05:48:53.50#ibcon#about to read 6, iclass 29, count 0 2006.286.05:48:53.50#ibcon#read 6, iclass 29, count 0 2006.286.05:48:53.50#ibcon#end of sib2, iclass 29, count 0 2006.286.05:48:53.50#ibcon#*after write, iclass 29, count 0 2006.286.05:48:53.50#ibcon#*before return 0, iclass 29, count 0 2006.286.05:48:53.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:48:53.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:48:53.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.05:48:53.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.05:48:53.50$vck44/va=3,7 2006.286.05:48:53.50#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.05:48:53.50#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.05:48:53.50#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:53.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:48:53.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:48:53.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:48:53.56#ibcon#enter wrdev, iclass 31, count 2 2006.286.05:48:53.56#ibcon#first serial, iclass 31, count 2 2006.286.05:48:53.56#ibcon#enter sib2, iclass 31, count 2 2006.286.05:48:53.56#ibcon#flushed, iclass 31, count 2 2006.286.05:48:53.56#ibcon#about to write, iclass 31, count 2 2006.286.05:48:53.56#ibcon#wrote, iclass 31, count 2 2006.286.05:48:53.56#ibcon#about to read 3, iclass 31, count 2 2006.286.05:48:53.58#ibcon#read 3, iclass 31, count 2 2006.286.05:48:53.58#ibcon#about to read 4, iclass 31, count 2 2006.286.05:48:53.58#ibcon#read 4, iclass 31, count 2 2006.286.05:48:53.58#ibcon#about to read 5, iclass 31, count 2 2006.286.05:48:53.58#ibcon#read 5, iclass 31, count 2 2006.286.05:48:53.58#ibcon#about to read 6, iclass 31, count 2 2006.286.05:48:53.58#ibcon#read 6, iclass 31, count 2 2006.286.05:48:53.58#ibcon#end of sib2, iclass 31, count 2 2006.286.05:48:53.58#ibcon#*mode == 0, iclass 31, count 2 2006.286.05:48:53.58#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.05:48:53.58#ibcon#[25=AT03-07\r\n] 2006.286.05:48:53.58#ibcon#*before write, iclass 31, count 2 2006.286.05:48:53.58#ibcon#enter sib2, iclass 31, count 2 2006.286.05:48:53.58#ibcon#flushed, iclass 31, count 2 2006.286.05:48:53.58#ibcon#about to write, iclass 31, count 2 2006.286.05:48:53.58#ibcon#wrote, iclass 31, count 2 2006.286.05:48:53.58#ibcon#about to read 3, iclass 31, count 2 2006.286.05:48:53.61#ibcon#read 3, iclass 31, count 2 2006.286.05:48:53.61#ibcon#about to read 4, iclass 31, count 2 2006.286.05:48:53.61#ibcon#read 4, iclass 31, count 2 2006.286.05:48:53.61#ibcon#about to read 5, iclass 31, count 2 2006.286.05:48:53.61#ibcon#read 5, iclass 31, count 2 2006.286.05:48:53.61#ibcon#about to read 6, iclass 31, count 2 2006.286.05:48:53.61#ibcon#read 6, iclass 31, count 2 2006.286.05:48:53.61#ibcon#end of sib2, iclass 31, count 2 2006.286.05:48:53.61#ibcon#*after write, iclass 31, count 2 2006.286.05:48:53.61#ibcon#*before return 0, iclass 31, count 2 2006.286.05:48:53.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:48:53.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:48:53.61#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.05:48:53.61#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:53.61#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:48:53.73#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:48:53.73#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:48:53.73#ibcon#enter wrdev, iclass 31, count 0 2006.286.05:48:53.73#ibcon#first serial, iclass 31, count 0 2006.286.05:48:53.73#ibcon#enter sib2, iclass 31, count 0 2006.286.05:48:53.73#ibcon#flushed, iclass 31, count 0 2006.286.05:48:53.73#ibcon#about to write, iclass 31, count 0 2006.286.05:48:53.73#ibcon#wrote, iclass 31, count 0 2006.286.05:48:53.73#ibcon#about to read 3, iclass 31, count 0 2006.286.05:48:53.75#ibcon#read 3, iclass 31, count 0 2006.286.05:48:54.06#ibcon#about to read 4, iclass 31, count 0 2006.286.05:48:54.06#ibcon#read 4, iclass 31, count 0 2006.286.05:48:54.06#ibcon#about to read 5, iclass 31, count 0 2006.286.05:48:54.06#ibcon#read 5, iclass 31, count 0 2006.286.05:48:54.06#ibcon#about to read 6, iclass 31, count 0 2006.286.05:48:54.06#ibcon#read 6, iclass 31, count 0 2006.286.05:48:54.06#ibcon#end of sib2, iclass 31, count 0 2006.286.05:48:54.06#ibcon#*mode == 0, iclass 31, count 0 2006.286.05:48:54.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.05:48:54.06#ibcon#[25=USB\r\n] 2006.286.05:48:54.07#ibcon#*before write, iclass 31, count 0 2006.286.05:48:54.07#ibcon#enter sib2, iclass 31, count 0 2006.286.05:48:54.07#ibcon#flushed, iclass 31, count 0 2006.286.05:48:54.07#ibcon#about to write, iclass 31, count 0 2006.286.05:48:54.07#ibcon#wrote, iclass 31, count 0 2006.286.05:48:54.07#ibcon#about to read 3, iclass 31, count 0 2006.286.05:48:54.09#ibcon#read 3, iclass 31, count 0 2006.286.05:48:54.09#ibcon#about to read 4, iclass 31, count 0 2006.286.05:48:54.09#ibcon#read 4, iclass 31, count 0 2006.286.05:48:54.09#ibcon#about to read 5, iclass 31, count 0 2006.286.05:48:54.09#ibcon#read 5, iclass 31, count 0 2006.286.05:48:54.09#ibcon#about to read 6, iclass 31, count 0 2006.286.05:48:54.09#ibcon#read 6, iclass 31, count 0 2006.286.05:48:54.09#ibcon#end of sib2, iclass 31, count 0 2006.286.05:48:54.09#ibcon#*after write, iclass 31, count 0 2006.286.05:48:54.09#ibcon#*before return 0, iclass 31, count 0 2006.286.05:48:54.09#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:48:54.09#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:48:54.09#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.05:48:54.09#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.05:48:54.09$vck44/valo=4,624.99 2006.286.05:48:54.09#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.05:48:54.09#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.05:48:54.09#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:54.09#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:48:54.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:48:54.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:48:54.09#ibcon#enter wrdev, iclass 33, count 0 2006.286.05:48:54.09#ibcon#first serial, iclass 33, count 0 2006.286.05:48:54.09#ibcon#enter sib2, iclass 33, count 0 2006.286.05:48:54.09#ibcon#flushed, iclass 33, count 0 2006.286.05:48:54.09#ibcon#about to write, iclass 33, count 0 2006.286.05:48:54.09#ibcon#wrote, iclass 33, count 0 2006.286.05:48:54.09#ibcon#about to read 3, iclass 33, count 0 2006.286.05:48:54.11#ibcon#read 3, iclass 33, count 0 2006.286.05:48:54.11#ibcon#about to read 4, iclass 33, count 0 2006.286.05:48:54.11#ibcon#read 4, iclass 33, count 0 2006.286.05:48:54.11#ibcon#about to read 5, iclass 33, count 0 2006.286.05:48:54.11#ibcon#read 5, iclass 33, count 0 2006.286.05:48:54.11#ibcon#about to read 6, iclass 33, count 0 2006.286.05:48:54.11#ibcon#read 6, iclass 33, count 0 2006.286.05:48:54.11#ibcon#end of sib2, iclass 33, count 0 2006.286.05:48:54.11#ibcon#*mode == 0, iclass 33, count 0 2006.286.05:48:54.11#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.05:48:54.11#ibcon#[26=FRQ=04,624.99\r\n] 2006.286.05:48:54.11#ibcon#*before write, iclass 33, count 0 2006.286.05:48:54.11#ibcon#enter sib2, iclass 33, count 0 2006.286.05:48:54.11#ibcon#flushed, iclass 33, count 0 2006.286.05:48:54.11#ibcon#about to write, iclass 33, count 0 2006.286.05:48:54.11#ibcon#wrote, iclass 33, count 0 2006.286.05:48:54.11#ibcon#about to read 3, iclass 33, count 0 2006.286.05:48:54.15#ibcon#read 3, iclass 33, count 0 2006.286.05:48:54.15#ibcon#about to read 4, iclass 33, count 0 2006.286.05:48:54.15#ibcon#read 4, iclass 33, count 0 2006.286.05:48:54.15#ibcon#about to read 5, iclass 33, count 0 2006.286.05:48:54.15#ibcon#read 5, iclass 33, count 0 2006.286.05:48:54.15#ibcon#about to read 6, iclass 33, count 0 2006.286.05:48:54.15#ibcon#read 6, iclass 33, count 0 2006.286.05:48:54.15#ibcon#end of sib2, iclass 33, count 0 2006.286.05:48:54.15#ibcon#*after write, iclass 33, count 0 2006.286.05:48:54.15#ibcon#*before return 0, iclass 33, count 0 2006.286.05:48:54.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:48:54.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:48:54.15#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.05:48:54.15#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.05:48:54.15$vck44/va=4,6 2006.286.05:48:54.15#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.05:48:54.15#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.05:48:54.15#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:54.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:48:54.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:48:54.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:48:54.21#ibcon#enter wrdev, iclass 35, count 2 2006.286.05:48:54.21#ibcon#first serial, iclass 35, count 2 2006.286.05:48:54.21#ibcon#enter sib2, iclass 35, count 2 2006.286.05:48:54.21#ibcon#flushed, iclass 35, count 2 2006.286.05:48:54.21#ibcon#about to write, iclass 35, count 2 2006.286.05:48:54.21#ibcon#wrote, iclass 35, count 2 2006.286.05:48:54.21#ibcon#about to read 3, iclass 35, count 2 2006.286.05:48:54.23#ibcon#read 3, iclass 35, count 2 2006.286.05:48:54.23#ibcon#about to read 4, iclass 35, count 2 2006.286.05:48:54.23#ibcon#read 4, iclass 35, count 2 2006.286.05:48:54.23#ibcon#about to read 5, iclass 35, count 2 2006.286.05:48:54.23#ibcon#read 5, iclass 35, count 2 2006.286.05:48:54.23#ibcon#about to read 6, iclass 35, count 2 2006.286.05:48:54.23#ibcon#read 6, iclass 35, count 2 2006.286.05:48:54.23#ibcon#end of sib2, iclass 35, count 2 2006.286.05:48:54.23#ibcon#*mode == 0, iclass 35, count 2 2006.286.05:48:54.23#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.05:48:54.23#ibcon#[25=AT04-06\r\n] 2006.286.05:48:54.23#ibcon#*before write, iclass 35, count 2 2006.286.05:48:54.23#ibcon#enter sib2, iclass 35, count 2 2006.286.05:48:54.23#ibcon#flushed, iclass 35, count 2 2006.286.05:48:54.23#ibcon#about to write, iclass 35, count 2 2006.286.05:48:54.23#ibcon#wrote, iclass 35, count 2 2006.286.05:48:54.23#ibcon#about to read 3, iclass 35, count 2 2006.286.05:48:54.26#ibcon#read 3, iclass 35, count 2 2006.286.05:48:54.26#ibcon#about to read 4, iclass 35, count 2 2006.286.05:48:54.26#ibcon#read 4, iclass 35, count 2 2006.286.05:48:54.26#ibcon#about to read 5, iclass 35, count 2 2006.286.05:48:54.26#ibcon#read 5, iclass 35, count 2 2006.286.05:48:54.26#ibcon#about to read 6, iclass 35, count 2 2006.286.05:48:54.26#ibcon#read 6, iclass 35, count 2 2006.286.05:48:54.26#ibcon#end of sib2, iclass 35, count 2 2006.286.05:48:54.26#ibcon#*after write, iclass 35, count 2 2006.286.05:48:54.26#ibcon#*before return 0, iclass 35, count 2 2006.286.05:48:54.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:48:54.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:48:54.26#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.05:48:54.26#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:54.26#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:48:54.38#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:48:54.38#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:48:54.38#ibcon#enter wrdev, iclass 35, count 0 2006.286.05:48:54.38#ibcon#first serial, iclass 35, count 0 2006.286.05:48:54.38#ibcon#enter sib2, iclass 35, count 0 2006.286.05:48:54.38#ibcon#flushed, iclass 35, count 0 2006.286.05:48:54.38#ibcon#about to write, iclass 35, count 0 2006.286.05:48:54.38#ibcon#wrote, iclass 35, count 0 2006.286.05:48:54.38#ibcon#about to read 3, iclass 35, count 0 2006.286.05:48:54.40#ibcon#read 3, iclass 35, count 0 2006.286.05:48:54.40#ibcon#about to read 4, iclass 35, count 0 2006.286.05:48:54.40#ibcon#read 4, iclass 35, count 0 2006.286.05:48:54.40#ibcon#about to read 5, iclass 35, count 0 2006.286.05:48:54.40#ibcon#read 5, iclass 35, count 0 2006.286.05:48:54.40#ibcon#about to read 6, iclass 35, count 0 2006.286.05:48:54.40#ibcon#read 6, iclass 35, count 0 2006.286.05:48:54.40#ibcon#end of sib2, iclass 35, count 0 2006.286.05:48:54.40#ibcon#*mode == 0, iclass 35, count 0 2006.286.05:48:54.40#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.05:48:54.40#ibcon#[25=USB\r\n] 2006.286.05:48:54.40#ibcon#*before write, iclass 35, count 0 2006.286.05:48:54.40#ibcon#enter sib2, iclass 35, count 0 2006.286.05:48:54.40#ibcon#flushed, iclass 35, count 0 2006.286.05:48:54.40#ibcon#about to write, iclass 35, count 0 2006.286.05:48:54.40#ibcon#wrote, iclass 35, count 0 2006.286.05:48:54.40#ibcon#about to read 3, iclass 35, count 0 2006.286.05:48:54.43#ibcon#read 3, iclass 35, count 0 2006.286.05:48:54.43#ibcon#about to read 4, iclass 35, count 0 2006.286.05:48:54.43#ibcon#read 4, iclass 35, count 0 2006.286.05:48:54.43#ibcon#about to read 5, iclass 35, count 0 2006.286.05:48:54.43#ibcon#read 5, iclass 35, count 0 2006.286.05:48:54.43#ibcon#about to read 6, iclass 35, count 0 2006.286.05:48:54.43#ibcon#read 6, iclass 35, count 0 2006.286.05:48:54.43#ibcon#end of sib2, iclass 35, count 0 2006.286.05:48:54.43#ibcon#*after write, iclass 35, count 0 2006.286.05:48:54.43#ibcon#*before return 0, iclass 35, count 0 2006.286.05:48:54.43#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:48:54.43#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:48:54.43#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.05:48:54.43#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.05:48:54.43$vck44/valo=5,734.99 2006.286.05:48:54.43#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.05:48:54.43#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.05:48:54.43#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:54.43#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:48:54.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:48:54.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:48:54.43#ibcon#enter wrdev, iclass 37, count 0 2006.286.05:48:54.43#ibcon#first serial, iclass 37, count 0 2006.286.05:48:54.43#ibcon#enter sib2, iclass 37, count 0 2006.286.05:48:54.43#ibcon#flushed, iclass 37, count 0 2006.286.05:48:54.43#ibcon#about to write, iclass 37, count 0 2006.286.05:48:54.43#ibcon#wrote, iclass 37, count 0 2006.286.05:48:54.43#ibcon#about to read 3, iclass 37, count 0 2006.286.05:48:54.45#ibcon#read 3, iclass 37, count 0 2006.286.05:48:54.45#ibcon#about to read 4, iclass 37, count 0 2006.286.05:48:54.45#ibcon#read 4, iclass 37, count 0 2006.286.05:48:54.45#ibcon#about to read 5, iclass 37, count 0 2006.286.05:48:54.45#ibcon#read 5, iclass 37, count 0 2006.286.05:48:54.45#ibcon#about to read 6, iclass 37, count 0 2006.286.05:48:54.45#ibcon#read 6, iclass 37, count 0 2006.286.05:48:54.45#ibcon#end of sib2, iclass 37, count 0 2006.286.05:48:54.45#ibcon#*mode == 0, iclass 37, count 0 2006.286.05:48:54.45#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.05:48:54.45#ibcon#[26=FRQ=05,734.99\r\n] 2006.286.05:48:54.45#ibcon#*before write, iclass 37, count 0 2006.286.05:48:54.45#ibcon#enter sib2, iclass 37, count 0 2006.286.05:48:54.45#ibcon#flushed, iclass 37, count 0 2006.286.05:48:54.45#ibcon#about to write, iclass 37, count 0 2006.286.05:48:54.45#ibcon#wrote, iclass 37, count 0 2006.286.05:48:54.45#ibcon#about to read 3, iclass 37, count 0 2006.286.05:48:54.49#ibcon#read 3, iclass 37, count 0 2006.286.05:48:54.49#ibcon#about to read 4, iclass 37, count 0 2006.286.05:48:54.49#ibcon#read 4, iclass 37, count 0 2006.286.05:48:54.49#ibcon#about to read 5, iclass 37, count 0 2006.286.05:48:54.49#ibcon#read 5, iclass 37, count 0 2006.286.05:48:54.49#ibcon#about to read 6, iclass 37, count 0 2006.286.05:48:54.49#ibcon#read 6, iclass 37, count 0 2006.286.05:48:54.49#ibcon#end of sib2, iclass 37, count 0 2006.286.05:48:54.49#ibcon#*after write, iclass 37, count 0 2006.286.05:48:54.49#ibcon#*before return 0, iclass 37, count 0 2006.286.05:48:54.49#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:48:54.49#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:48:54.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.05:48:54.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.05:48:54.49$vck44/va=5,3 2006.286.05:48:54.81#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.05:48:54.81#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.05:48:54.81#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:54.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:48:54.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:48:54.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:48:54.81#ibcon#enter wrdev, iclass 39, count 2 2006.286.05:48:54.81#ibcon#first serial, iclass 39, count 2 2006.286.05:48:54.81#ibcon#enter sib2, iclass 39, count 2 2006.286.05:48:54.81#ibcon#flushed, iclass 39, count 2 2006.286.05:48:54.81#ibcon#about to write, iclass 39, count 2 2006.286.05:48:54.81#ibcon#wrote, iclass 39, count 2 2006.286.05:48:54.81#ibcon#about to read 3, iclass 39, count 2 2006.286.05:48:54.82#ibcon#read 3, iclass 39, count 2 2006.286.05:48:54.82#ibcon#about to read 4, iclass 39, count 2 2006.286.05:48:54.82#ibcon#read 4, iclass 39, count 2 2006.286.05:48:54.82#ibcon#about to read 5, iclass 39, count 2 2006.286.05:48:54.82#ibcon#read 5, iclass 39, count 2 2006.286.05:48:54.82#ibcon#about to read 6, iclass 39, count 2 2006.286.05:48:54.82#ibcon#read 6, iclass 39, count 2 2006.286.05:48:54.82#ibcon#end of sib2, iclass 39, count 2 2006.286.05:48:54.82#ibcon#*mode == 0, iclass 39, count 2 2006.286.05:48:54.82#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.05:48:54.82#ibcon#[25=AT05-03\r\n] 2006.286.05:48:54.82#ibcon#*before write, iclass 39, count 2 2006.286.05:48:54.82#ibcon#enter sib2, iclass 39, count 2 2006.286.05:48:54.82#ibcon#flushed, iclass 39, count 2 2006.286.05:48:54.82#ibcon#about to write, iclass 39, count 2 2006.286.05:48:54.82#ibcon#wrote, iclass 39, count 2 2006.286.05:48:54.82#ibcon#about to read 3, iclass 39, count 2 2006.286.05:48:54.85#ibcon#read 3, iclass 39, count 2 2006.286.05:48:54.85#ibcon#about to read 4, iclass 39, count 2 2006.286.05:48:54.85#ibcon#read 4, iclass 39, count 2 2006.286.05:48:54.85#ibcon#about to read 5, iclass 39, count 2 2006.286.05:48:54.85#ibcon#read 5, iclass 39, count 2 2006.286.05:48:54.85#ibcon#about to read 6, iclass 39, count 2 2006.286.05:48:54.85#ibcon#read 6, iclass 39, count 2 2006.286.05:48:54.85#ibcon#end of sib2, iclass 39, count 2 2006.286.05:48:54.85#ibcon#*after write, iclass 39, count 2 2006.286.05:48:54.85#ibcon#*before return 0, iclass 39, count 2 2006.286.05:48:54.85#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:48:54.85#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:48:54.85#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.05:48:54.85#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:54.85#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:48:54.97#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:48:54.97#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:48:54.97#ibcon#enter wrdev, iclass 39, count 0 2006.286.05:48:54.97#ibcon#first serial, iclass 39, count 0 2006.286.05:48:54.97#ibcon#enter sib2, iclass 39, count 0 2006.286.05:48:54.97#ibcon#flushed, iclass 39, count 0 2006.286.05:48:54.97#ibcon#about to write, iclass 39, count 0 2006.286.05:48:54.97#ibcon#wrote, iclass 39, count 0 2006.286.05:48:54.97#ibcon#about to read 3, iclass 39, count 0 2006.286.05:48:54.99#ibcon#read 3, iclass 39, count 0 2006.286.05:48:54.99#ibcon#about to read 4, iclass 39, count 0 2006.286.05:48:54.99#ibcon#read 4, iclass 39, count 0 2006.286.05:48:54.99#ibcon#about to read 5, iclass 39, count 0 2006.286.05:48:54.99#ibcon#read 5, iclass 39, count 0 2006.286.05:48:54.99#ibcon#about to read 6, iclass 39, count 0 2006.286.05:48:54.99#ibcon#read 6, iclass 39, count 0 2006.286.05:48:54.99#ibcon#end of sib2, iclass 39, count 0 2006.286.05:48:54.99#ibcon#*mode == 0, iclass 39, count 0 2006.286.05:48:54.99#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.05:48:54.99#ibcon#[25=USB\r\n] 2006.286.05:48:54.99#ibcon#*before write, iclass 39, count 0 2006.286.05:48:54.99#ibcon#enter sib2, iclass 39, count 0 2006.286.05:48:54.99#ibcon#flushed, iclass 39, count 0 2006.286.05:48:54.99#ibcon#about to write, iclass 39, count 0 2006.286.05:48:54.99#ibcon#wrote, iclass 39, count 0 2006.286.05:48:54.99#ibcon#about to read 3, iclass 39, count 0 2006.286.05:48:55.02#ibcon#read 3, iclass 39, count 0 2006.286.05:48:55.02#ibcon#about to read 4, iclass 39, count 0 2006.286.05:48:55.02#ibcon#read 4, iclass 39, count 0 2006.286.05:48:55.02#ibcon#about to read 5, iclass 39, count 0 2006.286.05:48:55.02#ibcon#read 5, iclass 39, count 0 2006.286.05:48:55.02#ibcon#about to read 6, iclass 39, count 0 2006.286.05:48:55.02#ibcon#read 6, iclass 39, count 0 2006.286.05:48:55.02#ibcon#end of sib2, iclass 39, count 0 2006.286.05:48:55.02#ibcon#*after write, iclass 39, count 0 2006.286.05:48:55.02#ibcon#*before return 0, iclass 39, count 0 2006.286.05:48:55.02#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:48:55.02#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:48:55.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.05:48:55.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.05:48:55.02$vck44/valo=6,814.99 2006.286.05:48:55.02#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.05:48:55.02#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.05:48:55.02#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:55.02#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:48:55.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:48:55.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:48:55.02#ibcon#enter wrdev, iclass 3, count 0 2006.286.05:48:55.02#ibcon#first serial, iclass 3, count 0 2006.286.05:48:55.02#ibcon#enter sib2, iclass 3, count 0 2006.286.05:48:55.02#ibcon#flushed, iclass 3, count 0 2006.286.05:48:55.02#ibcon#about to write, iclass 3, count 0 2006.286.05:48:55.02#ibcon#wrote, iclass 3, count 0 2006.286.05:48:55.02#ibcon#about to read 3, iclass 3, count 0 2006.286.05:48:55.04#ibcon#read 3, iclass 3, count 0 2006.286.05:48:55.04#ibcon#about to read 4, iclass 3, count 0 2006.286.05:48:55.04#ibcon#read 4, iclass 3, count 0 2006.286.05:48:55.04#ibcon#about to read 5, iclass 3, count 0 2006.286.05:48:55.04#ibcon#read 5, iclass 3, count 0 2006.286.05:48:55.04#ibcon#about to read 6, iclass 3, count 0 2006.286.05:48:55.04#ibcon#read 6, iclass 3, count 0 2006.286.05:48:55.04#ibcon#end of sib2, iclass 3, count 0 2006.286.05:48:55.04#ibcon#*mode == 0, iclass 3, count 0 2006.286.05:48:55.04#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.05:48:55.04#ibcon#[26=FRQ=06,814.99\r\n] 2006.286.05:48:55.04#ibcon#*before write, iclass 3, count 0 2006.286.05:48:55.04#ibcon#enter sib2, iclass 3, count 0 2006.286.05:48:55.04#ibcon#flushed, iclass 3, count 0 2006.286.05:48:55.04#ibcon#about to write, iclass 3, count 0 2006.286.05:48:55.04#ibcon#wrote, iclass 3, count 0 2006.286.05:48:55.04#ibcon#about to read 3, iclass 3, count 0 2006.286.05:48:55.08#ibcon#read 3, iclass 3, count 0 2006.286.05:48:55.08#ibcon#about to read 4, iclass 3, count 0 2006.286.05:48:55.08#ibcon#read 4, iclass 3, count 0 2006.286.05:48:55.08#ibcon#about to read 5, iclass 3, count 0 2006.286.05:48:55.08#ibcon#read 5, iclass 3, count 0 2006.286.05:48:55.08#ibcon#about to read 6, iclass 3, count 0 2006.286.05:48:55.08#ibcon#read 6, iclass 3, count 0 2006.286.05:48:55.08#ibcon#end of sib2, iclass 3, count 0 2006.286.05:48:55.08#ibcon#*after write, iclass 3, count 0 2006.286.05:48:55.08#ibcon#*before return 0, iclass 3, count 0 2006.286.05:48:55.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:48:55.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:48:55.08#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.05:48:55.08#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.05:48:55.08$vck44/va=6,4 2006.286.05:48:55.08#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.05:48:55.08#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.05:48:55.08#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:55.08#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:48:55.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:48:55.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:48:55.14#ibcon#enter wrdev, iclass 5, count 2 2006.286.05:48:55.14#ibcon#first serial, iclass 5, count 2 2006.286.05:48:55.14#ibcon#enter sib2, iclass 5, count 2 2006.286.05:48:55.14#ibcon#flushed, iclass 5, count 2 2006.286.05:48:55.14#ibcon#about to write, iclass 5, count 2 2006.286.05:48:55.14#ibcon#wrote, iclass 5, count 2 2006.286.05:48:55.14#ibcon#about to read 3, iclass 5, count 2 2006.286.05:48:55.16#ibcon#read 3, iclass 5, count 2 2006.286.05:48:55.16#ibcon#about to read 4, iclass 5, count 2 2006.286.05:48:55.16#ibcon#read 4, iclass 5, count 2 2006.286.05:48:55.16#ibcon#about to read 5, iclass 5, count 2 2006.286.05:48:55.16#ibcon#read 5, iclass 5, count 2 2006.286.05:48:55.16#ibcon#about to read 6, iclass 5, count 2 2006.286.05:48:55.16#ibcon#read 6, iclass 5, count 2 2006.286.05:48:55.16#ibcon#end of sib2, iclass 5, count 2 2006.286.05:48:55.16#ibcon#*mode == 0, iclass 5, count 2 2006.286.05:48:55.16#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.05:48:55.16#ibcon#[25=AT06-04\r\n] 2006.286.05:48:55.16#ibcon#*before write, iclass 5, count 2 2006.286.05:48:55.16#ibcon#enter sib2, iclass 5, count 2 2006.286.05:48:55.16#ibcon#flushed, iclass 5, count 2 2006.286.05:48:55.16#ibcon#about to write, iclass 5, count 2 2006.286.05:48:55.16#ibcon#wrote, iclass 5, count 2 2006.286.05:48:55.16#ibcon#about to read 3, iclass 5, count 2 2006.286.05:48:55.19#ibcon#read 3, iclass 5, count 2 2006.286.05:48:55.19#ibcon#about to read 4, iclass 5, count 2 2006.286.05:48:55.19#ibcon#read 4, iclass 5, count 2 2006.286.05:48:55.19#ibcon#about to read 5, iclass 5, count 2 2006.286.05:48:55.19#ibcon#read 5, iclass 5, count 2 2006.286.05:48:55.19#ibcon#about to read 6, iclass 5, count 2 2006.286.05:48:55.19#ibcon#read 6, iclass 5, count 2 2006.286.05:48:55.19#ibcon#end of sib2, iclass 5, count 2 2006.286.05:48:55.19#ibcon#*after write, iclass 5, count 2 2006.286.05:48:55.19#ibcon#*before return 0, iclass 5, count 2 2006.286.05:48:55.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:48:55.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:48:55.19#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.05:48:55.19#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:55.19#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:48:55.31#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:48:55.31#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:48:55.31#ibcon#enter wrdev, iclass 5, count 0 2006.286.05:48:55.31#ibcon#first serial, iclass 5, count 0 2006.286.05:48:55.31#ibcon#enter sib2, iclass 5, count 0 2006.286.05:48:55.31#ibcon#flushed, iclass 5, count 0 2006.286.05:48:55.31#ibcon#about to write, iclass 5, count 0 2006.286.05:48:55.31#ibcon#wrote, iclass 5, count 0 2006.286.05:48:55.31#ibcon#about to read 3, iclass 5, count 0 2006.286.05:48:55.33#ibcon#read 3, iclass 5, count 0 2006.286.05:48:55.33#ibcon#about to read 4, iclass 5, count 0 2006.286.05:48:55.33#ibcon#read 4, iclass 5, count 0 2006.286.05:48:55.33#ibcon#about to read 5, iclass 5, count 0 2006.286.05:48:55.33#ibcon#read 5, iclass 5, count 0 2006.286.05:48:55.33#ibcon#about to read 6, iclass 5, count 0 2006.286.05:48:55.33#ibcon#read 6, iclass 5, count 0 2006.286.05:48:55.33#ibcon#end of sib2, iclass 5, count 0 2006.286.05:48:55.33#ibcon#*mode == 0, iclass 5, count 0 2006.286.05:48:55.33#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.05:48:55.33#ibcon#[25=USB\r\n] 2006.286.05:48:55.33#ibcon#*before write, iclass 5, count 0 2006.286.05:48:55.33#ibcon#enter sib2, iclass 5, count 0 2006.286.05:48:55.33#ibcon#flushed, iclass 5, count 0 2006.286.05:48:55.33#ibcon#about to write, iclass 5, count 0 2006.286.05:48:55.33#ibcon#wrote, iclass 5, count 0 2006.286.05:48:55.33#ibcon#about to read 3, iclass 5, count 0 2006.286.05:48:55.36#ibcon#read 3, iclass 5, count 0 2006.286.05:48:55.36#ibcon#about to read 4, iclass 5, count 0 2006.286.05:48:55.36#ibcon#read 4, iclass 5, count 0 2006.286.05:48:55.36#ibcon#about to read 5, iclass 5, count 0 2006.286.05:48:55.36#ibcon#read 5, iclass 5, count 0 2006.286.05:48:55.36#ibcon#about to read 6, iclass 5, count 0 2006.286.05:48:55.36#ibcon#read 6, iclass 5, count 0 2006.286.05:48:55.36#ibcon#end of sib2, iclass 5, count 0 2006.286.05:48:55.36#ibcon#*after write, iclass 5, count 0 2006.286.05:48:55.36#ibcon#*before return 0, iclass 5, count 0 2006.286.05:48:55.36#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:48:55.36#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:48:55.36#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.05:48:55.36#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.05:48:55.36$vck44/valo=7,864.99 2006.286.05:48:55.36#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.05:48:55.36#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.05:48:55.36#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:55.36#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:48:55.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:48:55.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:48:55.36#ibcon#enter wrdev, iclass 7, count 0 2006.286.05:48:55.36#ibcon#first serial, iclass 7, count 0 2006.286.05:48:55.36#ibcon#enter sib2, iclass 7, count 0 2006.286.05:48:55.36#ibcon#flushed, iclass 7, count 0 2006.286.05:48:55.36#ibcon#about to write, iclass 7, count 0 2006.286.05:48:55.36#ibcon#wrote, iclass 7, count 0 2006.286.05:48:55.36#ibcon#about to read 3, iclass 7, count 0 2006.286.05:48:55.38#ibcon#read 3, iclass 7, count 0 2006.286.05:48:55.38#ibcon#about to read 4, iclass 7, count 0 2006.286.05:48:55.38#ibcon#read 4, iclass 7, count 0 2006.286.05:48:55.38#ibcon#about to read 5, iclass 7, count 0 2006.286.05:48:55.38#ibcon#read 5, iclass 7, count 0 2006.286.05:48:55.38#ibcon#about to read 6, iclass 7, count 0 2006.286.05:48:55.38#ibcon#read 6, iclass 7, count 0 2006.286.05:48:55.38#ibcon#end of sib2, iclass 7, count 0 2006.286.05:48:55.38#ibcon#*mode == 0, iclass 7, count 0 2006.286.05:48:55.38#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.05:48:55.38#ibcon#[26=FRQ=07,864.99\r\n] 2006.286.05:48:55.38#ibcon#*before write, iclass 7, count 0 2006.286.05:48:55.38#ibcon#enter sib2, iclass 7, count 0 2006.286.05:48:55.38#ibcon#flushed, iclass 7, count 0 2006.286.05:48:55.38#ibcon#about to write, iclass 7, count 0 2006.286.05:48:55.38#ibcon#wrote, iclass 7, count 0 2006.286.05:48:55.38#ibcon#about to read 3, iclass 7, count 0 2006.286.05:48:55.42#ibcon#read 3, iclass 7, count 0 2006.286.05:48:55.42#ibcon#about to read 4, iclass 7, count 0 2006.286.05:48:55.42#ibcon#read 4, iclass 7, count 0 2006.286.05:48:55.42#ibcon#about to read 5, iclass 7, count 0 2006.286.05:48:55.42#ibcon#read 5, iclass 7, count 0 2006.286.05:48:55.42#ibcon#about to read 6, iclass 7, count 0 2006.286.05:48:55.42#ibcon#read 6, iclass 7, count 0 2006.286.05:48:55.42#ibcon#end of sib2, iclass 7, count 0 2006.286.05:48:55.42#ibcon#*after write, iclass 7, count 0 2006.286.05:48:55.42#ibcon#*before return 0, iclass 7, count 0 2006.286.05:48:55.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:48:55.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:48:55.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.05:48:55.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.05:48:55.42$vck44/va=7,4 2006.286.05:48:55.42#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.05:48:55.42#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.05:48:55.42#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:55.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:48:55.47#abcon#<5=/04 3.7 7.2 20.61 801015.3\r\n> 2006.286.05:48:55.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:48:55.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:48:55.48#ibcon#enter wrdev, iclass 11, count 2 2006.286.05:48:55.48#ibcon#first serial, iclass 11, count 2 2006.286.05:48:55.48#ibcon#enter sib2, iclass 11, count 2 2006.286.05:48:55.48#ibcon#flushed, iclass 11, count 2 2006.286.05:48:55.48#ibcon#about to write, iclass 11, count 2 2006.286.05:48:55.48#ibcon#wrote, iclass 11, count 2 2006.286.05:48:55.48#ibcon#about to read 3, iclass 11, count 2 2006.286.05:48:55.49#abcon#{5=INTERFACE CLEAR} 2006.286.05:48:55.50#ibcon#read 3, iclass 11, count 2 2006.286.05:48:55.50#ibcon#about to read 4, iclass 11, count 2 2006.286.05:48:55.50#ibcon#read 4, iclass 11, count 2 2006.286.05:48:55.50#ibcon#about to read 5, iclass 11, count 2 2006.286.05:48:55.50#ibcon#read 5, iclass 11, count 2 2006.286.05:48:55.50#ibcon#about to read 6, iclass 11, count 2 2006.286.05:48:55.50#ibcon#read 6, iclass 11, count 2 2006.286.05:48:55.50#ibcon#end of sib2, iclass 11, count 2 2006.286.05:48:55.50#ibcon#*mode == 0, iclass 11, count 2 2006.286.05:48:55.50#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.05:48:55.50#ibcon#[25=AT07-04\r\n] 2006.286.05:48:55.50#ibcon#*before write, iclass 11, count 2 2006.286.05:48:55.50#ibcon#enter sib2, iclass 11, count 2 2006.286.05:48:55.50#ibcon#flushed, iclass 11, count 2 2006.286.05:48:55.50#ibcon#about to write, iclass 11, count 2 2006.286.05:48:55.50#ibcon#wrote, iclass 11, count 2 2006.286.05:48:55.50#ibcon#about to read 3, iclass 11, count 2 2006.286.05:48:55.53#ibcon#read 3, iclass 11, count 2 2006.286.05:48:55.53#ibcon#about to read 4, iclass 11, count 2 2006.286.05:48:55.53#ibcon#read 4, iclass 11, count 2 2006.286.05:48:55.53#ibcon#about to read 5, iclass 11, count 2 2006.286.05:48:55.53#ibcon#read 5, iclass 11, count 2 2006.286.05:48:55.53#ibcon#about to read 6, iclass 11, count 2 2006.286.05:48:55.53#ibcon#read 6, iclass 11, count 2 2006.286.05:48:55.53#ibcon#end of sib2, iclass 11, count 2 2006.286.05:48:55.53#ibcon#*after write, iclass 11, count 2 2006.286.05:48:55.53#ibcon#*before return 0, iclass 11, count 2 2006.286.05:48:55.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:48:55.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:48:55.53#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.05:48:55.53#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:55.53#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:48:55.55#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:48:55.65#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:48:55.65#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:48:55.65#ibcon#enter wrdev, iclass 11, count 0 2006.286.05:48:55.65#ibcon#first serial, iclass 11, count 0 2006.286.05:48:55.65#ibcon#enter sib2, iclass 11, count 0 2006.286.05:48:55.65#ibcon#flushed, iclass 11, count 0 2006.286.05:48:55.65#ibcon#about to write, iclass 11, count 0 2006.286.05:48:55.65#ibcon#wrote, iclass 11, count 0 2006.286.05:48:55.65#ibcon#about to read 3, iclass 11, count 0 2006.286.05:48:55.67#ibcon#read 3, iclass 11, count 0 2006.286.05:48:55.67#ibcon#about to read 4, iclass 11, count 0 2006.286.05:48:55.67#ibcon#read 4, iclass 11, count 0 2006.286.05:48:55.67#ibcon#about to read 5, iclass 11, count 0 2006.286.05:48:55.67#ibcon#read 5, iclass 11, count 0 2006.286.05:48:55.67#ibcon#about to read 6, iclass 11, count 0 2006.286.05:48:55.67#ibcon#read 6, iclass 11, count 0 2006.286.05:48:55.67#ibcon#end of sib2, iclass 11, count 0 2006.286.05:48:55.67#ibcon#*mode == 0, iclass 11, count 0 2006.286.05:48:55.67#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.05:48:55.67#ibcon#[25=USB\r\n] 2006.286.05:48:55.67#ibcon#*before write, iclass 11, count 0 2006.286.05:48:55.67#ibcon#enter sib2, iclass 11, count 0 2006.286.05:48:55.67#ibcon#flushed, iclass 11, count 0 2006.286.05:48:55.67#ibcon#about to write, iclass 11, count 0 2006.286.05:48:55.67#ibcon#wrote, iclass 11, count 0 2006.286.05:48:55.67#ibcon#about to read 3, iclass 11, count 0 2006.286.05:48:55.70#ibcon#read 3, iclass 11, count 0 2006.286.05:48:55.70#ibcon#about to read 4, iclass 11, count 0 2006.286.05:48:55.70#ibcon#read 4, iclass 11, count 0 2006.286.05:48:55.70#ibcon#about to read 5, iclass 11, count 0 2006.286.05:48:55.70#ibcon#read 5, iclass 11, count 0 2006.286.05:48:55.70#ibcon#about to read 6, iclass 11, count 0 2006.286.05:48:55.70#ibcon#read 6, iclass 11, count 0 2006.286.05:48:55.70#ibcon#end of sib2, iclass 11, count 0 2006.286.05:48:55.70#ibcon#*after write, iclass 11, count 0 2006.286.05:48:55.70#ibcon#*before return 0, iclass 11, count 0 2006.286.05:48:55.70#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:48:55.70#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:48:55.70#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.05:48:55.70#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.05:48:55.70$vck44/valo=8,884.99 2006.286.05:48:55.70#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.05:48:55.70#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.05:48:55.70#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:55.70#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:48:55.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:48:55.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:48:55.70#ibcon#enter wrdev, iclass 17, count 0 2006.286.05:48:55.70#ibcon#first serial, iclass 17, count 0 2006.286.05:48:55.70#ibcon#enter sib2, iclass 17, count 0 2006.286.05:48:55.70#ibcon#flushed, iclass 17, count 0 2006.286.05:48:55.70#ibcon#about to write, iclass 17, count 0 2006.286.05:48:55.70#ibcon#wrote, iclass 17, count 0 2006.286.05:48:55.70#ibcon#about to read 3, iclass 17, count 0 2006.286.05:48:55.72#ibcon#read 3, iclass 17, count 0 2006.286.05:48:55.91#ibcon#about to read 4, iclass 17, count 0 2006.286.05:48:55.91#ibcon#read 4, iclass 17, count 0 2006.286.05:48:55.91#ibcon#about to read 5, iclass 17, count 0 2006.286.05:48:55.91#ibcon#read 5, iclass 17, count 0 2006.286.05:48:55.91#ibcon#about to read 6, iclass 17, count 0 2006.286.05:48:55.91#ibcon#read 6, iclass 17, count 0 2006.286.05:48:55.91#ibcon#end of sib2, iclass 17, count 0 2006.286.05:48:55.91#ibcon#*mode == 0, iclass 17, count 0 2006.286.05:48:55.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.05:48:55.91#ibcon#[26=FRQ=08,884.99\r\n] 2006.286.05:48:55.91#ibcon#*before write, iclass 17, count 0 2006.286.05:48:55.91#ibcon#enter sib2, iclass 17, count 0 2006.286.05:48:55.91#ibcon#flushed, iclass 17, count 0 2006.286.05:48:55.91#ibcon#about to write, iclass 17, count 0 2006.286.05:48:55.91#ibcon#wrote, iclass 17, count 0 2006.286.05:48:55.91#ibcon#about to read 3, iclass 17, count 0 2006.286.05:48:55.95#ibcon#read 3, iclass 17, count 0 2006.286.05:48:55.95#ibcon#about to read 4, iclass 17, count 0 2006.286.05:48:55.95#ibcon#read 4, iclass 17, count 0 2006.286.05:48:55.95#ibcon#about to read 5, iclass 17, count 0 2006.286.05:48:55.95#ibcon#read 5, iclass 17, count 0 2006.286.05:48:55.95#ibcon#about to read 6, iclass 17, count 0 2006.286.05:48:55.95#ibcon#read 6, iclass 17, count 0 2006.286.05:48:55.95#ibcon#end of sib2, iclass 17, count 0 2006.286.05:48:55.95#ibcon#*after write, iclass 17, count 0 2006.286.05:48:55.95#ibcon#*before return 0, iclass 17, count 0 2006.286.05:48:55.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:48:55.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:48:55.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.05:48:55.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.05:48:55.95$vck44/va=8,3 2006.286.05:48:55.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.286.05:48:55.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.286.05:48:55.95#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:55.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:48:55.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:48:55.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:48:55.95#ibcon#enter wrdev, iclass 19, count 2 2006.286.05:48:55.95#ibcon#first serial, iclass 19, count 2 2006.286.05:48:55.95#ibcon#enter sib2, iclass 19, count 2 2006.286.05:48:55.95#ibcon#flushed, iclass 19, count 2 2006.286.05:48:55.95#ibcon#about to write, iclass 19, count 2 2006.286.05:48:55.95#ibcon#wrote, iclass 19, count 2 2006.286.05:48:55.95#ibcon#about to read 3, iclass 19, count 2 2006.286.05:48:55.97#ibcon#read 3, iclass 19, count 2 2006.286.05:48:55.97#ibcon#about to read 4, iclass 19, count 2 2006.286.05:48:55.97#ibcon#read 4, iclass 19, count 2 2006.286.05:48:55.97#ibcon#about to read 5, iclass 19, count 2 2006.286.05:48:55.97#ibcon#read 5, iclass 19, count 2 2006.286.05:48:55.97#ibcon#about to read 6, iclass 19, count 2 2006.286.05:48:55.97#ibcon#read 6, iclass 19, count 2 2006.286.05:48:55.97#ibcon#end of sib2, iclass 19, count 2 2006.286.05:48:55.97#ibcon#*mode == 0, iclass 19, count 2 2006.286.05:48:55.97#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.286.05:48:55.97#ibcon#[25=AT08-03\r\n] 2006.286.05:48:55.97#ibcon#*before write, iclass 19, count 2 2006.286.05:48:55.97#ibcon#enter sib2, iclass 19, count 2 2006.286.05:48:55.97#ibcon#flushed, iclass 19, count 2 2006.286.05:48:55.97#ibcon#about to write, iclass 19, count 2 2006.286.05:48:55.97#ibcon#wrote, iclass 19, count 2 2006.286.05:48:55.97#ibcon#about to read 3, iclass 19, count 2 2006.286.05:48:56.00#ibcon#read 3, iclass 19, count 2 2006.286.05:48:56.00#ibcon#about to read 4, iclass 19, count 2 2006.286.05:48:56.00#ibcon#read 4, iclass 19, count 2 2006.286.05:48:56.00#ibcon#about to read 5, iclass 19, count 2 2006.286.05:48:56.00#ibcon#read 5, iclass 19, count 2 2006.286.05:48:56.00#ibcon#about to read 6, iclass 19, count 2 2006.286.05:48:56.00#ibcon#read 6, iclass 19, count 2 2006.286.05:48:56.00#ibcon#end of sib2, iclass 19, count 2 2006.286.05:48:56.00#ibcon#*after write, iclass 19, count 2 2006.286.05:48:56.00#ibcon#*before return 0, iclass 19, count 2 2006.286.05:48:56.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:48:56.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.286.05:48:56.00#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.286.05:48:56.00#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:56.00#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:48:56.12#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:48:56.12#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:48:56.12#ibcon#enter wrdev, iclass 19, count 0 2006.286.05:48:56.12#ibcon#first serial, iclass 19, count 0 2006.286.05:48:56.12#ibcon#enter sib2, iclass 19, count 0 2006.286.05:48:56.12#ibcon#flushed, iclass 19, count 0 2006.286.05:48:56.12#ibcon#about to write, iclass 19, count 0 2006.286.05:48:56.12#ibcon#wrote, iclass 19, count 0 2006.286.05:48:56.12#ibcon#about to read 3, iclass 19, count 0 2006.286.05:48:56.14#ibcon#read 3, iclass 19, count 0 2006.286.05:48:56.14#ibcon#about to read 4, iclass 19, count 0 2006.286.05:48:56.14#ibcon#read 4, iclass 19, count 0 2006.286.05:48:56.14#ibcon#about to read 5, iclass 19, count 0 2006.286.05:48:56.14#ibcon#read 5, iclass 19, count 0 2006.286.05:48:56.14#ibcon#about to read 6, iclass 19, count 0 2006.286.05:48:56.14#ibcon#read 6, iclass 19, count 0 2006.286.05:48:56.14#ibcon#end of sib2, iclass 19, count 0 2006.286.05:48:56.14#ibcon#*mode == 0, iclass 19, count 0 2006.286.05:48:56.14#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.05:48:56.14#ibcon#[25=USB\r\n] 2006.286.05:48:56.14#ibcon#*before write, iclass 19, count 0 2006.286.05:48:56.14#ibcon#enter sib2, iclass 19, count 0 2006.286.05:48:56.14#ibcon#flushed, iclass 19, count 0 2006.286.05:48:56.14#ibcon#about to write, iclass 19, count 0 2006.286.05:48:56.14#ibcon#wrote, iclass 19, count 0 2006.286.05:48:56.14#ibcon#about to read 3, iclass 19, count 0 2006.286.05:48:56.17#ibcon#read 3, iclass 19, count 0 2006.286.05:48:56.17#ibcon#about to read 4, iclass 19, count 0 2006.286.05:48:56.17#ibcon#read 4, iclass 19, count 0 2006.286.05:48:56.17#ibcon#about to read 5, iclass 19, count 0 2006.286.05:48:56.17#ibcon#read 5, iclass 19, count 0 2006.286.05:48:56.17#ibcon#about to read 6, iclass 19, count 0 2006.286.05:48:56.17#ibcon#read 6, iclass 19, count 0 2006.286.05:48:56.17#ibcon#end of sib2, iclass 19, count 0 2006.286.05:48:56.17#ibcon#*after write, iclass 19, count 0 2006.286.05:48:56.17#ibcon#*before return 0, iclass 19, count 0 2006.286.05:48:56.17#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:48:56.17#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.286.05:48:56.17#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.05:48:56.17#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.05:48:56.17$vck44/vblo=1,629.99 2006.286.05:48:56.17#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.286.05:48:56.17#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.286.05:48:56.17#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:56.17#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:48:56.17#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:48:56.17#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:48:56.17#ibcon#enter wrdev, iclass 21, count 0 2006.286.05:48:56.17#ibcon#first serial, iclass 21, count 0 2006.286.05:48:56.17#ibcon#enter sib2, iclass 21, count 0 2006.286.05:48:56.17#ibcon#flushed, iclass 21, count 0 2006.286.05:48:56.17#ibcon#about to write, iclass 21, count 0 2006.286.05:48:56.17#ibcon#wrote, iclass 21, count 0 2006.286.05:48:56.17#ibcon#about to read 3, iclass 21, count 0 2006.286.05:48:56.19#ibcon#read 3, iclass 21, count 0 2006.286.05:48:56.19#ibcon#about to read 4, iclass 21, count 0 2006.286.05:48:56.19#ibcon#read 4, iclass 21, count 0 2006.286.05:48:56.19#ibcon#about to read 5, iclass 21, count 0 2006.286.05:48:56.19#ibcon#read 5, iclass 21, count 0 2006.286.05:48:56.19#ibcon#about to read 6, iclass 21, count 0 2006.286.05:48:56.19#ibcon#read 6, iclass 21, count 0 2006.286.05:48:56.19#ibcon#end of sib2, iclass 21, count 0 2006.286.05:48:56.19#ibcon#*mode == 0, iclass 21, count 0 2006.286.05:48:56.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.286.05:48:56.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.286.05:48:56.19#ibcon#*before write, iclass 21, count 0 2006.286.05:48:56.19#ibcon#enter sib2, iclass 21, count 0 2006.286.05:48:56.19#ibcon#flushed, iclass 21, count 0 2006.286.05:48:56.19#ibcon#about to write, iclass 21, count 0 2006.286.05:48:56.19#ibcon#wrote, iclass 21, count 0 2006.286.05:48:56.19#ibcon#about to read 3, iclass 21, count 0 2006.286.05:48:56.23#ibcon#read 3, iclass 21, count 0 2006.286.05:48:56.23#ibcon#about to read 4, iclass 21, count 0 2006.286.05:48:56.23#ibcon#read 4, iclass 21, count 0 2006.286.05:48:56.23#ibcon#about to read 5, iclass 21, count 0 2006.286.05:48:56.23#ibcon#read 5, iclass 21, count 0 2006.286.05:48:56.23#ibcon#about to read 6, iclass 21, count 0 2006.286.05:48:56.23#ibcon#read 6, iclass 21, count 0 2006.286.05:48:56.23#ibcon#end of sib2, iclass 21, count 0 2006.286.05:48:56.23#ibcon#*after write, iclass 21, count 0 2006.286.05:48:56.23#ibcon#*before return 0, iclass 21, count 0 2006.286.05:48:56.23#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:48:56.23#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.286.05:48:56.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.286.05:48:56.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.286.05:48:56.23$vck44/vb=1,4 2006.286.05:48:56.23#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.286.05:48:56.23#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.286.05:48:56.23#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:56.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.05:48:56.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.286.05:48:56.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.05:48:56.23#ibcon#enter wrdev, iclass 23, count 2 2006.286.05:48:56.23#ibcon#first serial, iclass 23, count 2 2006.286.05:48:56.23#ibcon#enter sib2, iclass 23, count 2 2006.286.05:48:56.23#ibcon#flushed, iclass 23, count 2 2006.286.05:48:56.23#ibcon#about to write, iclass 23, count 2 2006.286.05:48:56.23#ibcon#wrote, iclass 23, count 2 2006.286.05:48:56.23#ibcon#about to read 3, iclass 23, count 2 2006.286.05:48:56.25#ibcon#read 3, iclass 23, count 2 2006.286.05:48:56.25#ibcon#about to read 4, iclass 23, count 2 2006.286.05:48:56.25#ibcon#read 4, iclass 23, count 2 2006.286.05:48:56.25#ibcon#about to read 5, iclass 23, count 2 2006.286.05:48:56.25#ibcon#read 5, iclass 23, count 2 2006.286.05:48:56.25#ibcon#about to read 6, iclass 23, count 2 2006.286.05:48:56.25#ibcon#read 6, iclass 23, count 2 2006.286.05:48:56.25#ibcon#end of sib2, iclass 23, count 2 2006.286.05:48:56.25#ibcon#*mode == 0, iclass 23, count 2 2006.286.05:48:56.25#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.286.05:48:56.25#ibcon#[27=AT01-04\r\n] 2006.286.05:48:56.25#ibcon#*before write, iclass 23, count 2 2006.286.05:48:56.25#ibcon#enter sib2, iclass 23, count 2 2006.286.05:48:56.25#ibcon#flushed, iclass 23, count 2 2006.286.05:48:56.25#ibcon#about to write, iclass 23, count 2 2006.286.05:48:56.25#ibcon#wrote, iclass 23, count 2 2006.286.05:48:56.25#ibcon#about to read 3, iclass 23, count 2 2006.286.05:48:56.28#ibcon#read 3, iclass 23, count 2 2006.286.05:48:56.28#ibcon#about to read 4, iclass 23, count 2 2006.286.05:48:56.28#ibcon#read 4, iclass 23, count 2 2006.286.05:48:56.28#ibcon#about to read 5, iclass 23, count 2 2006.286.05:48:56.28#ibcon#read 5, iclass 23, count 2 2006.286.05:48:56.28#ibcon#about to read 6, iclass 23, count 2 2006.286.05:48:56.28#ibcon#read 6, iclass 23, count 2 2006.286.05:48:56.28#ibcon#end of sib2, iclass 23, count 2 2006.286.05:48:56.28#ibcon#*after write, iclass 23, count 2 2006.286.05:48:56.28#ibcon#*before return 0, iclass 23, count 2 2006.286.05:48:56.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.286.05:48:56.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.286.05:48:56.28#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.286.05:48:56.28#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:56.28#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.05:48:56.40#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.286.05:48:56.40#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.05:48:56.40#ibcon#enter wrdev, iclass 23, count 0 2006.286.05:48:56.40#ibcon#first serial, iclass 23, count 0 2006.286.05:48:56.40#ibcon#enter sib2, iclass 23, count 0 2006.286.05:48:56.40#ibcon#flushed, iclass 23, count 0 2006.286.05:48:56.40#ibcon#about to write, iclass 23, count 0 2006.286.05:48:56.40#ibcon#wrote, iclass 23, count 0 2006.286.05:48:56.40#ibcon#about to read 3, iclass 23, count 0 2006.286.05:48:56.42#ibcon#read 3, iclass 23, count 0 2006.286.05:48:56.42#ibcon#about to read 4, iclass 23, count 0 2006.286.05:48:56.42#ibcon#read 4, iclass 23, count 0 2006.286.05:48:56.42#ibcon#about to read 5, iclass 23, count 0 2006.286.05:48:56.42#ibcon#read 5, iclass 23, count 0 2006.286.05:48:56.42#ibcon#about to read 6, iclass 23, count 0 2006.286.05:48:56.42#ibcon#read 6, iclass 23, count 0 2006.286.05:48:56.42#ibcon#end of sib2, iclass 23, count 0 2006.286.05:48:56.42#ibcon#*mode == 0, iclass 23, count 0 2006.286.05:48:56.42#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.286.05:48:56.42#ibcon#[27=USB\r\n] 2006.286.05:48:56.42#ibcon#*before write, iclass 23, count 0 2006.286.05:48:56.42#ibcon#enter sib2, iclass 23, count 0 2006.286.05:48:56.42#ibcon#flushed, iclass 23, count 0 2006.286.05:48:56.42#ibcon#about to write, iclass 23, count 0 2006.286.05:48:56.42#ibcon#wrote, iclass 23, count 0 2006.286.05:48:56.42#ibcon#about to read 3, iclass 23, count 0 2006.286.05:48:56.45#ibcon#read 3, iclass 23, count 0 2006.286.05:48:56.45#ibcon#about to read 4, iclass 23, count 0 2006.286.05:48:56.45#ibcon#read 4, iclass 23, count 0 2006.286.05:48:56.45#ibcon#about to read 5, iclass 23, count 0 2006.286.05:48:56.45#ibcon#read 5, iclass 23, count 0 2006.286.05:48:56.45#ibcon#about to read 6, iclass 23, count 0 2006.286.05:48:56.45#ibcon#read 6, iclass 23, count 0 2006.286.05:48:56.45#ibcon#end of sib2, iclass 23, count 0 2006.286.05:48:56.45#ibcon#*after write, iclass 23, count 0 2006.286.05:48:56.45#ibcon#*before return 0, iclass 23, count 0 2006.286.05:48:56.45#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.286.05:48:56.45#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.286.05:48:56.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.286.05:48:56.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.286.05:48:56.45$vck44/vblo=2,634.99 2006.286.05:48:56.45#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.286.05:48:56.45#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.286.05:48:56.45#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:56.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:48:56.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:48:56.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:48:56.45#ibcon#enter wrdev, iclass 25, count 0 2006.286.05:48:56.45#ibcon#first serial, iclass 25, count 0 2006.286.05:48:56.45#ibcon#enter sib2, iclass 25, count 0 2006.286.05:48:56.45#ibcon#flushed, iclass 25, count 0 2006.286.05:48:56.45#ibcon#about to write, iclass 25, count 0 2006.286.05:48:56.45#ibcon#wrote, iclass 25, count 0 2006.286.05:48:56.45#ibcon#about to read 3, iclass 25, count 0 2006.286.05:48:56.47#ibcon#read 3, iclass 25, count 0 2006.286.05:48:56.47#ibcon#about to read 4, iclass 25, count 0 2006.286.05:48:56.47#ibcon#read 4, iclass 25, count 0 2006.286.05:48:56.47#ibcon#about to read 5, iclass 25, count 0 2006.286.05:48:56.47#ibcon#read 5, iclass 25, count 0 2006.286.05:48:56.47#ibcon#about to read 6, iclass 25, count 0 2006.286.05:48:56.47#ibcon#read 6, iclass 25, count 0 2006.286.05:48:56.47#ibcon#end of sib2, iclass 25, count 0 2006.286.05:48:56.47#ibcon#*mode == 0, iclass 25, count 0 2006.286.05:48:56.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.286.05:48:56.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.286.05:48:56.47#ibcon#*before write, iclass 25, count 0 2006.286.05:48:56.47#ibcon#enter sib2, iclass 25, count 0 2006.286.05:48:56.47#ibcon#flushed, iclass 25, count 0 2006.286.05:48:56.47#ibcon#about to write, iclass 25, count 0 2006.286.05:48:56.47#ibcon#wrote, iclass 25, count 0 2006.286.05:48:56.47#ibcon#about to read 3, iclass 25, count 0 2006.286.05:48:56.51#ibcon#read 3, iclass 25, count 0 2006.286.05:48:56.51#ibcon#about to read 4, iclass 25, count 0 2006.286.05:48:56.51#ibcon#read 4, iclass 25, count 0 2006.286.05:48:56.51#ibcon#about to read 5, iclass 25, count 0 2006.286.05:48:56.51#ibcon#read 5, iclass 25, count 0 2006.286.05:48:56.51#ibcon#about to read 6, iclass 25, count 0 2006.286.05:48:56.51#ibcon#read 6, iclass 25, count 0 2006.286.05:48:56.51#ibcon#end of sib2, iclass 25, count 0 2006.286.05:48:56.51#ibcon#*after write, iclass 25, count 0 2006.286.05:48:56.51#ibcon#*before return 0, iclass 25, count 0 2006.286.05:48:56.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:48:56.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.286.05:48:56.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.286.05:48:56.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.286.05:48:56.51$vck44/vb=2,5 2006.286.05:48:56.51#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.286.05:48:56.51#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.286.05:48:56.51#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:56.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:48:56.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:48:56.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:48:56.57#ibcon#enter wrdev, iclass 27, count 2 2006.286.05:48:56.57#ibcon#first serial, iclass 27, count 2 2006.286.05:48:56.57#ibcon#enter sib2, iclass 27, count 2 2006.286.05:48:56.57#ibcon#flushed, iclass 27, count 2 2006.286.05:48:56.57#ibcon#about to write, iclass 27, count 2 2006.286.05:48:56.57#ibcon#wrote, iclass 27, count 2 2006.286.05:48:56.57#ibcon#about to read 3, iclass 27, count 2 2006.286.05:48:56.59#ibcon#read 3, iclass 27, count 2 2006.286.05:48:56.59#ibcon#about to read 4, iclass 27, count 2 2006.286.05:48:56.59#ibcon#read 4, iclass 27, count 2 2006.286.05:48:56.59#ibcon#about to read 5, iclass 27, count 2 2006.286.05:48:56.59#ibcon#read 5, iclass 27, count 2 2006.286.05:48:56.59#ibcon#about to read 6, iclass 27, count 2 2006.286.05:48:56.59#ibcon#read 6, iclass 27, count 2 2006.286.05:48:56.59#ibcon#end of sib2, iclass 27, count 2 2006.286.05:48:56.59#ibcon#*mode == 0, iclass 27, count 2 2006.286.05:48:56.59#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.286.05:48:56.59#ibcon#[27=AT02-05\r\n] 2006.286.05:48:56.59#ibcon#*before write, iclass 27, count 2 2006.286.05:48:56.59#ibcon#enter sib2, iclass 27, count 2 2006.286.05:48:56.59#ibcon#flushed, iclass 27, count 2 2006.286.05:48:56.59#ibcon#about to write, iclass 27, count 2 2006.286.05:48:56.59#ibcon#wrote, iclass 27, count 2 2006.286.05:48:56.59#ibcon#about to read 3, iclass 27, count 2 2006.286.05:48:56.62#ibcon#read 3, iclass 27, count 2 2006.286.05:48:56.62#ibcon#about to read 4, iclass 27, count 2 2006.286.05:48:56.62#ibcon#read 4, iclass 27, count 2 2006.286.05:48:56.62#ibcon#about to read 5, iclass 27, count 2 2006.286.05:48:56.62#ibcon#read 5, iclass 27, count 2 2006.286.05:48:56.62#ibcon#about to read 6, iclass 27, count 2 2006.286.05:48:56.62#ibcon#read 6, iclass 27, count 2 2006.286.05:48:56.62#ibcon#end of sib2, iclass 27, count 2 2006.286.05:48:56.62#ibcon#*after write, iclass 27, count 2 2006.286.05:48:56.62#ibcon#*before return 0, iclass 27, count 2 2006.286.05:48:56.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:48:56.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.286.05:48:56.62#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.286.05:48:56.62#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:56.62#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:48:56.74#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:48:56.74#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:48:56.74#ibcon#enter wrdev, iclass 27, count 0 2006.286.05:48:56.74#ibcon#first serial, iclass 27, count 0 2006.286.05:48:56.74#ibcon#enter sib2, iclass 27, count 0 2006.286.05:48:56.74#ibcon#flushed, iclass 27, count 0 2006.286.05:48:56.74#ibcon#about to write, iclass 27, count 0 2006.286.05:48:56.74#ibcon#wrote, iclass 27, count 0 2006.286.05:48:56.74#ibcon#about to read 3, iclass 27, count 0 2006.286.05:48:56.76#ibcon#read 3, iclass 27, count 0 2006.286.05:48:56.76#ibcon#about to read 4, iclass 27, count 0 2006.286.05:48:56.76#ibcon#read 4, iclass 27, count 0 2006.286.05:48:56.76#ibcon#about to read 5, iclass 27, count 0 2006.286.05:48:56.76#ibcon#read 5, iclass 27, count 0 2006.286.05:48:56.76#ibcon#about to read 6, iclass 27, count 0 2006.286.05:48:56.76#ibcon#read 6, iclass 27, count 0 2006.286.05:48:56.76#ibcon#end of sib2, iclass 27, count 0 2006.286.05:48:56.76#ibcon#*mode == 0, iclass 27, count 0 2006.286.05:48:56.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.286.05:48:56.76#ibcon#[27=USB\r\n] 2006.286.05:48:56.76#ibcon#*before write, iclass 27, count 0 2006.286.05:48:56.76#ibcon#enter sib2, iclass 27, count 0 2006.286.05:48:56.76#ibcon#flushed, iclass 27, count 0 2006.286.05:48:56.76#ibcon#about to write, iclass 27, count 0 2006.286.05:48:56.76#ibcon#wrote, iclass 27, count 0 2006.286.05:48:56.76#ibcon#about to read 3, iclass 27, count 0 2006.286.05:48:56.79#ibcon#read 3, iclass 27, count 0 2006.286.05:48:56.79#ibcon#about to read 4, iclass 27, count 0 2006.286.05:48:56.79#ibcon#read 4, iclass 27, count 0 2006.286.05:48:56.79#ibcon#about to read 5, iclass 27, count 0 2006.286.05:48:56.79#ibcon#read 5, iclass 27, count 0 2006.286.05:48:56.79#ibcon#about to read 6, iclass 27, count 0 2006.286.05:48:56.79#ibcon#read 6, iclass 27, count 0 2006.286.05:48:56.79#ibcon#end of sib2, iclass 27, count 0 2006.286.05:48:56.79#ibcon#*after write, iclass 27, count 0 2006.286.05:48:56.79#ibcon#*before return 0, iclass 27, count 0 2006.286.05:48:56.79#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:48:56.79#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.286.05:48:56.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.286.05:48:56.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.286.05:48:56.79$vck44/vblo=3,649.99 2006.286.05:48:56.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.286.05:48:56.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.286.05:48:56.83#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:56.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:48:56.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:48:56.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:48:56.83#ibcon#enter wrdev, iclass 29, count 0 2006.286.05:48:56.83#ibcon#first serial, iclass 29, count 0 2006.286.05:48:56.83#ibcon#enter sib2, iclass 29, count 0 2006.286.05:48:56.83#ibcon#flushed, iclass 29, count 0 2006.286.05:48:56.83#ibcon#about to write, iclass 29, count 0 2006.286.05:48:56.84#ibcon#wrote, iclass 29, count 0 2006.286.05:48:56.84#ibcon#about to read 3, iclass 29, count 0 2006.286.05:48:56.85#ibcon#read 3, iclass 29, count 0 2006.286.05:48:56.85#ibcon#about to read 4, iclass 29, count 0 2006.286.05:48:56.85#ibcon#read 4, iclass 29, count 0 2006.286.05:48:56.85#ibcon#about to read 5, iclass 29, count 0 2006.286.05:48:56.85#ibcon#read 5, iclass 29, count 0 2006.286.05:48:56.85#ibcon#about to read 6, iclass 29, count 0 2006.286.05:48:56.85#ibcon#read 6, iclass 29, count 0 2006.286.05:48:56.85#ibcon#end of sib2, iclass 29, count 0 2006.286.05:48:56.85#ibcon#*mode == 0, iclass 29, count 0 2006.286.05:48:56.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.286.05:48:56.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.286.05:48:56.85#ibcon#*before write, iclass 29, count 0 2006.286.05:48:56.85#ibcon#enter sib2, iclass 29, count 0 2006.286.05:48:56.85#ibcon#flushed, iclass 29, count 0 2006.286.05:48:56.85#ibcon#about to write, iclass 29, count 0 2006.286.05:48:56.85#ibcon#wrote, iclass 29, count 0 2006.286.05:48:56.85#ibcon#about to read 3, iclass 29, count 0 2006.286.05:48:56.89#ibcon#read 3, iclass 29, count 0 2006.286.05:48:56.89#ibcon#about to read 4, iclass 29, count 0 2006.286.05:48:56.89#ibcon#read 4, iclass 29, count 0 2006.286.05:48:56.89#ibcon#about to read 5, iclass 29, count 0 2006.286.05:48:56.89#ibcon#read 5, iclass 29, count 0 2006.286.05:48:56.89#ibcon#about to read 6, iclass 29, count 0 2006.286.05:48:56.89#ibcon#read 6, iclass 29, count 0 2006.286.05:48:56.89#ibcon#end of sib2, iclass 29, count 0 2006.286.05:48:56.89#ibcon#*after write, iclass 29, count 0 2006.286.05:48:56.89#ibcon#*before return 0, iclass 29, count 0 2006.286.05:48:56.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:48:56.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.286.05:48:56.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.286.05:48:56.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.286.05:48:56.89$vck44/vb=3,4 2006.286.05:48:56.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.286.05:48:56.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.286.05:48:56.89#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:56.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:48:56.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:48:56.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:48:56.91#ibcon#enter wrdev, iclass 31, count 2 2006.286.05:48:56.91#ibcon#first serial, iclass 31, count 2 2006.286.05:48:56.91#ibcon#enter sib2, iclass 31, count 2 2006.286.05:48:56.91#ibcon#flushed, iclass 31, count 2 2006.286.05:48:56.91#ibcon#about to write, iclass 31, count 2 2006.286.05:48:56.91#ibcon#wrote, iclass 31, count 2 2006.286.05:48:56.91#ibcon#about to read 3, iclass 31, count 2 2006.286.05:48:56.93#ibcon#read 3, iclass 31, count 2 2006.286.05:48:56.93#ibcon#about to read 4, iclass 31, count 2 2006.286.05:48:56.93#ibcon#read 4, iclass 31, count 2 2006.286.05:48:56.93#ibcon#about to read 5, iclass 31, count 2 2006.286.05:48:56.93#ibcon#read 5, iclass 31, count 2 2006.286.05:48:56.93#ibcon#about to read 6, iclass 31, count 2 2006.286.05:48:56.93#ibcon#read 6, iclass 31, count 2 2006.286.05:48:56.93#ibcon#end of sib2, iclass 31, count 2 2006.286.05:48:56.93#ibcon#*mode == 0, iclass 31, count 2 2006.286.05:48:56.93#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.286.05:48:56.93#ibcon#[27=AT03-04\r\n] 2006.286.05:48:56.93#ibcon#*before write, iclass 31, count 2 2006.286.05:48:56.93#ibcon#enter sib2, iclass 31, count 2 2006.286.05:48:56.93#ibcon#flushed, iclass 31, count 2 2006.286.05:48:56.93#ibcon#about to write, iclass 31, count 2 2006.286.05:48:56.93#ibcon#wrote, iclass 31, count 2 2006.286.05:48:56.93#ibcon#about to read 3, iclass 31, count 2 2006.286.05:48:56.96#ibcon#read 3, iclass 31, count 2 2006.286.05:48:56.96#ibcon#about to read 4, iclass 31, count 2 2006.286.05:48:56.96#ibcon#read 4, iclass 31, count 2 2006.286.05:48:56.96#ibcon#about to read 5, iclass 31, count 2 2006.286.05:48:56.96#ibcon#read 5, iclass 31, count 2 2006.286.05:48:56.96#ibcon#about to read 6, iclass 31, count 2 2006.286.05:48:56.96#ibcon#read 6, iclass 31, count 2 2006.286.05:48:56.96#ibcon#end of sib2, iclass 31, count 2 2006.286.05:48:56.96#ibcon#*after write, iclass 31, count 2 2006.286.05:48:56.96#ibcon#*before return 0, iclass 31, count 2 2006.286.05:48:56.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:48:56.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.286.05:48:56.96#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.286.05:48:56.96#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:56.96#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:48:57.08#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:48:57.08#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:48:57.08#ibcon#enter wrdev, iclass 31, count 0 2006.286.05:48:57.08#ibcon#first serial, iclass 31, count 0 2006.286.05:48:57.08#ibcon#enter sib2, iclass 31, count 0 2006.286.05:48:57.08#ibcon#flushed, iclass 31, count 0 2006.286.05:48:57.08#ibcon#about to write, iclass 31, count 0 2006.286.05:48:57.08#ibcon#wrote, iclass 31, count 0 2006.286.05:48:57.08#ibcon#about to read 3, iclass 31, count 0 2006.286.05:48:57.10#ibcon#read 3, iclass 31, count 0 2006.286.05:48:57.10#ibcon#about to read 4, iclass 31, count 0 2006.286.05:48:57.10#ibcon#read 4, iclass 31, count 0 2006.286.05:48:57.10#ibcon#about to read 5, iclass 31, count 0 2006.286.05:48:57.10#ibcon#read 5, iclass 31, count 0 2006.286.05:48:57.10#ibcon#about to read 6, iclass 31, count 0 2006.286.05:48:57.10#ibcon#read 6, iclass 31, count 0 2006.286.05:48:57.10#ibcon#end of sib2, iclass 31, count 0 2006.286.05:48:57.10#ibcon#*mode == 0, iclass 31, count 0 2006.286.05:48:57.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.286.05:48:57.10#ibcon#[27=USB\r\n] 2006.286.05:48:57.10#ibcon#*before write, iclass 31, count 0 2006.286.05:48:57.10#ibcon#enter sib2, iclass 31, count 0 2006.286.05:48:57.10#ibcon#flushed, iclass 31, count 0 2006.286.05:48:57.10#ibcon#about to write, iclass 31, count 0 2006.286.05:48:57.10#ibcon#wrote, iclass 31, count 0 2006.286.05:48:57.10#ibcon#about to read 3, iclass 31, count 0 2006.286.05:48:57.13#ibcon#read 3, iclass 31, count 0 2006.286.05:48:57.13#ibcon#about to read 4, iclass 31, count 0 2006.286.05:48:57.13#ibcon#read 4, iclass 31, count 0 2006.286.05:48:57.13#ibcon#about to read 5, iclass 31, count 0 2006.286.05:48:57.13#ibcon#read 5, iclass 31, count 0 2006.286.05:48:57.13#ibcon#about to read 6, iclass 31, count 0 2006.286.05:48:57.13#ibcon#read 6, iclass 31, count 0 2006.286.05:48:57.13#ibcon#end of sib2, iclass 31, count 0 2006.286.05:48:57.13#ibcon#*after write, iclass 31, count 0 2006.286.05:48:57.13#ibcon#*before return 0, iclass 31, count 0 2006.286.05:48:57.13#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:48:57.13#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.286.05:48:57.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.286.05:48:57.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.286.05:48:57.13$vck44/vblo=4,679.99 2006.286.05:48:57.13#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.286.05:48:57.13#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.286.05:48:57.13#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:57.13#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:48:57.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:48:57.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:48:57.13#ibcon#enter wrdev, iclass 33, count 0 2006.286.05:48:57.13#ibcon#first serial, iclass 33, count 0 2006.286.05:48:57.13#ibcon#enter sib2, iclass 33, count 0 2006.286.05:48:57.13#ibcon#flushed, iclass 33, count 0 2006.286.05:48:57.13#ibcon#about to write, iclass 33, count 0 2006.286.05:48:57.13#ibcon#wrote, iclass 33, count 0 2006.286.05:48:57.13#ibcon#about to read 3, iclass 33, count 0 2006.286.05:48:57.15#ibcon#read 3, iclass 33, count 0 2006.286.05:48:57.15#ibcon#about to read 4, iclass 33, count 0 2006.286.05:48:57.15#ibcon#read 4, iclass 33, count 0 2006.286.05:48:57.15#ibcon#about to read 5, iclass 33, count 0 2006.286.05:48:57.15#ibcon#read 5, iclass 33, count 0 2006.286.05:48:57.15#ibcon#about to read 6, iclass 33, count 0 2006.286.05:48:57.15#ibcon#read 6, iclass 33, count 0 2006.286.05:48:57.15#ibcon#end of sib2, iclass 33, count 0 2006.286.05:48:57.15#ibcon#*mode == 0, iclass 33, count 0 2006.286.05:48:57.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.286.05:48:57.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.286.05:48:57.15#ibcon#*before write, iclass 33, count 0 2006.286.05:48:57.15#ibcon#enter sib2, iclass 33, count 0 2006.286.05:48:57.15#ibcon#flushed, iclass 33, count 0 2006.286.05:48:57.15#ibcon#about to write, iclass 33, count 0 2006.286.05:48:57.15#ibcon#wrote, iclass 33, count 0 2006.286.05:48:57.15#ibcon#about to read 3, iclass 33, count 0 2006.286.05:48:57.19#ibcon#read 3, iclass 33, count 0 2006.286.05:48:57.19#ibcon#about to read 4, iclass 33, count 0 2006.286.05:48:57.19#ibcon#read 4, iclass 33, count 0 2006.286.05:48:57.19#ibcon#about to read 5, iclass 33, count 0 2006.286.05:48:57.19#ibcon#read 5, iclass 33, count 0 2006.286.05:48:57.19#ibcon#about to read 6, iclass 33, count 0 2006.286.05:48:57.19#ibcon#read 6, iclass 33, count 0 2006.286.05:48:57.19#ibcon#end of sib2, iclass 33, count 0 2006.286.05:48:57.19#ibcon#*after write, iclass 33, count 0 2006.286.05:48:57.19#ibcon#*before return 0, iclass 33, count 0 2006.286.05:48:57.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:48:57.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.286.05:48:57.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.286.05:48:57.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.286.05:48:57.19$vck44/vb=4,5 2006.286.05:48:57.19#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.286.05:48:57.19#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.286.05:48:57.19#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:57.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:48:57.25#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:48:57.25#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:48:57.25#ibcon#enter wrdev, iclass 35, count 2 2006.286.05:48:57.25#ibcon#first serial, iclass 35, count 2 2006.286.05:48:57.25#ibcon#enter sib2, iclass 35, count 2 2006.286.05:48:57.25#ibcon#flushed, iclass 35, count 2 2006.286.05:48:57.25#ibcon#about to write, iclass 35, count 2 2006.286.05:48:57.25#ibcon#wrote, iclass 35, count 2 2006.286.05:48:57.25#ibcon#about to read 3, iclass 35, count 2 2006.286.05:48:57.27#ibcon#read 3, iclass 35, count 2 2006.286.05:48:57.27#ibcon#about to read 4, iclass 35, count 2 2006.286.05:48:57.27#ibcon#read 4, iclass 35, count 2 2006.286.05:48:57.27#ibcon#about to read 5, iclass 35, count 2 2006.286.05:48:57.27#ibcon#read 5, iclass 35, count 2 2006.286.05:48:57.27#ibcon#about to read 6, iclass 35, count 2 2006.286.05:48:57.27#ibcon#read 6, iclass 35, count 2 2006.286.05:48:57.27#ibcon#end of sib2, iclass 35, count 2 2006.286.05:48:57.27#ibcon#*mode == 0, iclass 35, count 2 2006.286.05:48:57.27#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.286.05:48:57.27#ibcon#[27=AT04-05\r\n] 2006.286.05:48:57.27#ibcon#*before write, iclass 35, count 2 2006.286.05:48:57.27#ibcon#enter sib2, iclass 35, count 2 2006.286.05:48:57.27#ibcon#flushed, iclass 35, count 2 2006.286.05:48:57.27#ibcon#about to write, iclass 35, count 2 2006.286.05:48:57.27#ibcon#wrote, iclass 35, count 2 2006.286.05:48:57.27#ibcon#about to read 3, iclass 35, count 2 2006.286.05:48:57.30#ibcon#read 3, iclass 35, count 2 2006.286.05:48:57.30#ibcon#about to read 4, iclass 35, count 2 2006.286.05:48:57.30#ibcon#read 4, iclass 35, count 2 2006.286.05:48:57.30#ibcon#about to read 5, iclass 35, count 2 2006.286.05:48:57.30#ibcon#read 5, iclass 35, count 2 2006.286.05:48:57.30#ibcon#about to read 6, iclass 35, count 2 2006.286.05:48:57.30#ibcon#read 6, iclass 35, count 2 2006.286.05:48:57.30#ibcon#end of sib2, iclass 35, count 2 2006.286.05:48:57.30#ibcon#*after write, iclass 35, count 2 2006.286.05:48:57.30#ibcon#*before return 0, iclass 35, count 2 2006.286.05:48:57.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:48:57.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.286.05:48:57.30#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.286.05:48:57.30#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:57.30#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:48:57.42#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:48:57.42#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:48:57.42#ibcon#enter wrdev, iclass 35, count 0 2006.286.05:48:57.42#ibcon#first serial, iclass 35, count 0 2006.286.05:48:57.42#ibcon#enter sib2, iclass 35, count 0 2006.286.05:48:57.42#ibcon#flushed, iclass 35, count 0 2006.286.05:48:57.42#ibcon#about to write, iclass 35, count 0 2006.286.05:48:57.42#ibcon#wrote, iclass 35, count 0 2006.286.05:48:57.42#ibcon#about to read 3, iclass 35, count 0 2006.286.05:48:57.44#ibcon#read 3, iclass 35, count 0 2006.286.05:48:57.44#ibcon#about to read 4, iclass 35, count 0 2006.286.05:48:57.44#ibcon#read 4, iclass 35, count 0 2006.286.05:48:57.44#ibcon#about to read 5, iclass 35, count 0 2006.286.05:48:57.44#ibcon#read 5, iclass 35, count 0 2006.286.05:48:57.44#ibcon#about to read 6, iclass 35, count 0 2006.286.05:48:57.44#ibcon#read 6, iclass 35, count 0 2006.286.05:48:57.44#ibcon#end of sib2, iclass 35, count 0 2006.286.05:48:57.44#ibcon#*mode == 0, iclass 35, count 0 2006.286.05:48:57.44#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.286.05:48:57.44#ibcon#[27=USB\r\n] 2006.286.05:48:57.44#ibcon#*before write, iclass 35, count 0 2006.286.05:48:57.44#ibcon#enter sib2, iclass 35, count 0 2006.286.05:48:57.44#ibcon#flushed, iclass 35, count 0 2006.286.05:48:57.44#ibcon#about to write, iclass 35, count 0 2006.286.05:48:57.44#ibcon#wrote, iclass 35, count 0 2006.286.05:48:57.44#ibcon#about to read 3, iclass 35, count 0 2006.286.05:48:57.47#ibcon#read 3, iclass 35, count 0 2006.286.05:48:57.47#ibcon#about to read 4, iclass 35, count 0 2006.286.05:48:57.47#ibcon#read 4, iclass 35, count 0 2006.286.05:48:57.47#ibcon#about to read 5, iclass 35, count 0 2006.286.05:48:57.47#ibcon#read 5, iclass 35, count 0 2006.286.05:48:57.47#ibcon#about to read 6, iclass 35, count 0 2006.286.05:48:57.47#ibcon#read 6, iclass 35, count 0 2006.286.05:48:57.47#ibcon#end of sib2, iclass 35, count 0 2006.286.05:48:57.47#ibcon#*after write, iclass 35, count 0 2006.286.05:48:57.47#ibcon#*before return 0, iclass 35, count 0 2006.286.05:48:57.47#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:48:57.47#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.286.05:48:57.47#ibcon#about to clear, iclass 35 cls_cnt 0 2006.286.05:48:57.47#ibcon#cleared, iclass 35 cls_cnt 0 2006.286.05:48:57.47$vck44/vblo=5,709.99 2006.286.05:48:57.47#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.286.05:48:57.47#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.286.05:48:57.47#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:57.47#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:48:57.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:48:57.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:48:57.47#ibcon#enter wrdev, iclass 37, count 0 2006.286.05:48:57.47#ibcon#first serial, iclass 37, count 0 2006.286.05:48:57.47#ibcon#enter sib2, iclass 37, count 0 2006.286.05:48:57.47#ibcon#flushed, iclass 37, count 0 2006.286.05:48:57.47#ibcon#about to write, iclass 37, count 0 2006.286.05:48:57.47#ibcon#wrote, iclass 37, count 0 2006.286.05:48:57.47#ibcon#about to read 3, iclass 37, count 0 2006.286.05:48:57.49#ibcon#read 3, iclass 37, count 0 2006.286.05:48:57.49#ibcon#about to read 4, iclass 37, count 0 2006.286.05:48:57.49#ibcon#read 4, iclass 37, count 0 2006.286.05:48:57.49#ibcon#about to read 5, iclass 37, count 0 2006.286.05:48:57.49#ibcon#read 5, iclass 37, count 0 2006.286.05:48:57.49#ibcon#about to read 6, iclass 37, count 0 2006.286.05:48:57.49#ibcon#read 6, iclass 37, count 0 2006.286.05:48:57.49#ibcon#end of sib2, iclass 37, count 0 2006.286.05:48:57.49#ibcon#*mode == 0, iclass 37, count 0 2006.286.05:48:57.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.286.05:48:57.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.286.05:48:57.49#ibcon#*before write, iclass 37, count 0 2006.286.05:48:57.49#ibcon#enter sib2, iclass 37, count 0 2006.286.05:48:57.49#ibcon#flushed, iclass 37, count 0 2006.286.05:48:57.49#ibcon#about to write, iclass 37, count 0 2006.286.05:48:57.49#ibcon#wrote, iclass 37, count 0 2006.286.05:48:57.49#ibcon#about to read 3, iclass 37, count 0 2006.286.05:48:57.53#ibcon#read 3, iclass 37, count 0 2006.286.05:48:57.53#ibcon#about to read 4, iclass 37, count 0 2006.286.05:48:57.53#ibcon#read 4, iclass 37, count 0 2006.286.05:48:57.53#ibcon#about to read 5, iclass 37, count 0 2006.286.05:48:57.53#ibcon#read 5, iclass 37, count 0 2006.286.05:48:57.53#ibcon#about to read 6, iclass 37, count 0 2006.286.05:48:57.53#ibcon#read 6, iclass 37, count 0 2006.286.05:48:57.53#ibcon#end of sib2, iclass 37, count 0 2006.286.05:48:57.53#ibcon#*after write, iclass 37, count 0 2006.286.05:48:57.53#ibcon#*before return 0, iclass 37, count 0 2006.286.05:48:57.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:48:57.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.286.05:48:57.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.286.05:48:57.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.286.05:48:57.53$vck44/vb=5,4 2006.286.05:48:57.53#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.286.05:48:57.53#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.286.05:48:57.53#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:57.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:48:57.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:48:57.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:48:57.59#ibcon#enter wrdev, iclass 39, count 2 2006.286.05:48:57.59#ibcon#first serial, iclass 39, count 2 2006.286.05:48:57.59#ibcon#enter sib2, iclass 39, count 2 2006.286.05:48:57.59#ibcon#flushed, iclass 39, count 2 2006.286.05:48:57.59#ibcon#about to write, iclass 39, count 2 2006.286.05:48:57.59#ibcon#wrote, iclass 39, count 2 2006.286.05:48:57.59#ibcon#about to read 3, iclass 39, count 2 2006.286.05:48:57.61#ibcon#read 3, iclass 39, count 2 2006.286.05:48:57.61#ibcon#about to read 4, iclass 39, count 2 2006.286.05:48:57.61#ibcon#read 4, iclass 39, count 2 2006.286.05:48:57.61#ibcon#about to read 5, iclass 39, count 2 2006.286.05:48:57.61#ibcon#read 5, iclass 39, count 2 2006.286.05:48:57.61#ibcon#about to read 6, iclass 39, count 2 2006.286.05:48:57.61#ibcon#read 6, iclass 39, count 2 2006.286.05:48:57.61#ibcon#end of sib2, iclass 39, count 2 2006.286.05:48:57.61#ibcon#*mode == 0, iclass 39, count 2 2006.286.05:48:57.61#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.286.05:48:57.61#ibcon#[27=AT05-04\r\n] 2006.286.05:48:57.61#ibcon#*before write, iclass 39, count 2 2006.286.05:48:57.61#ibcon#enter sib2, iclass 39, count 2 2006.286.05:48:57.61#ibcon#flushed, iclass 39, count 2 2006.286.05:48:57.61#ibcon#about to write, iclass 39, count 2 2006.286.05:48:57.61#ibcon#wrote, iclass 39, count 2 2006.286.05:48:57.61#ibcon#about to read 3, iclass 39, count 2 2006.286.05:48:57.64#ibcon#read 3, iclass 39, count 2 2006.286.05:48:57.64#ibcon#about to read 4, iclass 39, count 2 2006.286.05:48:57.64#ibcon#read 4, iclass 39, count 2 2006.286.05:48:57.64#ibcon#about to read 5, iclass 39, count 2 2006.286.05:48:57.64#ibcon#read 5, iclass 39, count 2 2006.286.05:48:57.64#ibcon#about to read 6, iclass 39, count 2 2006.286.05:48:57.64#ibcon#read 6, iclass 39, count 2 2006.286.05:48:57.64#ibcon#end of sib2, iclass 39, count 2 2006.286.05:48:57.64#ibcon#*after write, iclass 39, count 2 2006.286.05:48:57.64#ibcon#*before return 0, iclass 39, count 2 2006.286.05:48:57.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:48:57.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.286.05:48:57.64#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.286.05:48:57.64#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:57.64#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:48:57.76#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:48:57.76#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:48:57.76#ibcon#enter wrdev, iclass 39, count 0 2006.286.05:48:57.76#ibcon#first serial, iclass 39, count 0 2006.286.05:48:57.76#ibcon#enter sib2, iclass 39, count 0 2006.286.05:48:57.76#ibcon#flushed, iclass 39, count 0 2006.286.05:48:57.76#ibcon#about to write, iclass 39, count 0 2006.286.05:48:57.76#ibcon#wrote, iclass 39, count 0 2006.286.05:48:57.76#ibcon#about to read 3, iclass 39, count 0 2006.286.05:48:57.78#ibcon#read 3, iclass 39, count 0 2006.286.05:48:57.78#ibcon#about to read 4, iclass 39, count 0 2006.286.05:48:57.78#ibcon#read 4, iclass 39, count 0 2006.286.05:48:57.78#ibcon#about to read 5, iclass 39, count 0 2006.286.05:48:57.78#ibcon#read 5, iclass 39, count 0 2006.286.05:48:57.78#ibcon#about to read 6, iclass 39, count 0 2006.286.05:48:57.78#ibcon#read 6, iclass 39, count 0 2006.286.05:48:57.78#ibcon#end of sib2, iclass 39, count 0 2006.286.05:48:57.78#ibcon#*mode == 0, iclass 39, count 0 2006.286.05:48:57.78#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.286.05:48:57.78#ibcon#[27=USB\r\n] 2006.286.05:48:57.78#ibcon#*before write, iclass 39, count 0 2006.286.05:48:57.78#ibcon#enter sib2, iclass 39, count 0 2006.286.05:48:57.78#ibcon#flushed, iclass 39, count 0 2006.286.05:48:57.78#ibcon#about to write, iclass 39, count 0 2006.286.05:48:57.78#ibcon#wrote, iclass 39, count 0 2006.286.05:48:57.78#ibcon#about to read 3, iclass 39, count 0 2006.286.05:48:57.81#ibcon#read 3, iclass 39, count 0 2006.286.05:48:57.81#ibcon#about to read 4, iclass 39, count 0 2006.286.05:48:57.81#ibcon#read 4, iclass 39, count 0 2006.286.05:48:57.81#ibcon#about to read 5, iclass 39, count 0 2006.286.05:48:57.81#ibcon#read 5, iclass 39, count 0 2006.286.05:48:57.81#ibcon#about to read 6, iclass 39, count 0 2006.286.05:48:57.81#ibcon#read 6, iclass 39, count 0 2006.286.05:48:57.81#ibcon#end of sib2, iclass 39, count 0 2006.286.05:48:57.81#ibcon#*after write, iclass 39, count 0 2006.286.05:48:57.81#ibcon#*before return 0, iclass 39, count 0 2006.286.05:48:57.81#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:48:57.81#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.286.05:48:57.81#ibcon#about to clear, iclass 39 cls_cnt 0 2006.286.05:48:57.81#ibcon#cleared, iclass 39 cls_cnt 0 2006.286.05:48:57.81$vck44/vblo=6,719.99 2006.286.05:48:57.84#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.286.05:48:57.84#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.286.05:48:57.84#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:57.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:48:57.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:48:57.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:48:57.84#ibcon#enter wrdev, iclass 3, count 0 2006.286.05:48:57.84#ibcon#first serial, iclass 3, count 0 2006.286.05:48:57.84#ibcon#enter sib2, iclass 3, count 0 2006.286.05:48:57.84#ibcon#flushed, iclass 3, count 0 2006.286.05:48:57.84#ibcon#about to write, iclass 3, count 0 2006.286.05:48:57.84#ibcon#wrote, iclass 3, count 0 2006.286.05:48:57.84#ibcon#about to read 3, iclass 3, count 0 2006.286.05:48:57.85#ibcon#read 3, iclass 3, count 0 2006.286.05:48:57.85#ibcon#about to read 4, iclass 3, count 0 2006.286.05:48:57.85#ibcon#read 4, iclass 3, count 0 2006.286.05:48:57.85#ibcon#about to read 5, iclass 3, count 0 2006.286.05:48:57.85#ibcon#read 5, iclass 3, count 0 2006.286.05:48:57.85#ibcon#about to read 6, iclass 3, count 0 2006.286.05:48:57.85#ibcon#read 6, iclass 3, count 0 2006.286.05:48:57.85#ibcon#end of sib2, iclass 3, count 0 2006.286.05:48:57.85#ibcon#*mode == 0, iclass 3, count 0 2006.286.05:48:57.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.286.05:48:57.85#ibcon#[28=FRQ=06,719.99\r\n] 2006.286.05:48:57.85#ibcon#*before write, iclass 3, count 0 2006.286.05:48:57.85#ibcon#enter sib2, iclass 3, count 0 2006.286.05:48:57.85#ibcon#flushed, iclass 3, count 0 2006.286.05:48:57.85#ibcon#about to write, iclass 3, count 0 2006.286.05:48:57.85#ibcon#wrote, iclass 3, count 0 2006.286.05:48:57.85#ibcon#about to read 3, iclass 3, count 0 2006.286.05:48:57.89#ibcon#read 3, iclass 3, count 0 2006.286.05:48:57.89#ibcon#about to read 4, iclass 3, count 0 2006.286.05:48:57.89#ibcon#read 4, iclass 3, count 0 2006.286.05:48:57.89#ibcon#about to read 5, iclass 3, count 0 2006.286.05:48:57.89#ibcon#read 5, iclass 3, count 0 2006.286.05:48:57.89#ibcon#about to read 6, iclass 3, count 0 2006.286.05:48:57.89#ibcon#read 6, iclass 3, count 0 2006.286.05:48:57.89#ibcon#end of sib2, iclass 3, count 0 2006.286.05:48:57.89#ibcon#*after write, iclass 3, count 0 2006.286.05:48:57.89#ibcon#*before return 0, iclass 3, count 0 2006.286.05:48:57.89#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:48:57.89#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.286.05:48:57.89#ibcon#about to clear, iclass 3 cls_cnt 0 2006.286.05:48:57.89#ibcon#cleared, iclass 3 cls_cnt 0 2006.286.05:48:57.89$vck44/vb=6,3 2006.286.05:48:57.89#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.286.05:48:57.89#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.286.05:48:57.89#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:57.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:48:57.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:48:57.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:48:57.93#ibcon#enter wrdev, iclass 5, count 2 2006.286.05:48:57.93#ibcon#first serial, iclass 5, count 2 2006.286.05:48:57.93#ibcon#enter sib2, iclass 5, count 2 2006.286.05:48:57.93#ibcon#flushed, iclass 5, count 2 2006.286.05:48:57.93#ibcon#about to write, iclass 5, count 2 2006.286.05:48:57.93#ibcon#wrote, iclass 5, count 2 2006.286.05:48:57.93#ibcon#about to read 3, iclass 5, count 2 2006.286.05:48:57.95#ibcon#read 3, iclass 5, count 2 2006.286.05:48:57.95#ibcon#about to read 4, iclass 5, count 2 2006.286.05:48:57.95#ibcon#read 4, iclass 5, count 2 2006.286.05:48:57.95#ibcon#about to read 5, iclass 5, count 2 2006.286.05:48:57.95#ibcon#read 5, iclass 5, count 2 2006.286.05:48:57.95#ibcon#about to read 6, iclass 5, count 2 2006.286.05:48:57.95#ibcon#read 6, iclass 5, count 2 2006.286.05:48:57.95#ibcon#end of sib2, iclass 5, count 2 2006.286.05:48:57.95#ibcon#*mode == 0, iclass 5, count 2 2006.286.05:48:57.95#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.286.05:48:57.95#ibcon#[27=AT06-03\r\n] 2006.286.05:48:57.95#ibcon#*before write, iclass 5, count 2 2006.286.05:48:57.95#ibcon#enter sib2, iclass 5, count 2 2006.286.05:48:57.95#ibcon#flushed, iclass 5, count 2 2006.286.05:48:57.95#ibcon#about to write, iclass 5, count 2 2006.286.05:48:57.95#ibcon#wrote, iclass 5, count 2 2006.286.05:48:57.95#ibcon#about to read 3, iclass 5, count 2 2006.286.05:48:57.98#ibcon#read 3, iclass 5, count 2 2006.286.05:48:57.98#ibcon#about to read 4, iclass 5, count 2 2006.286.05:48:57.98#ibcon#read 4, iclass 5, count 2 2006.286.05:48:57.98#ibcon#about to read 5, iclass 5, count 2 2006.286.05:48:57.98#ibcon#read 5, iclass 5, count 2 2006.286.05:48:57.98#ibcon#about to read 6, iclass 5, count 2 2006.286.05:48:57.98#ibcon#read 6, iclass 5, count 2 2006.286.05:48:57.98#ibcon#end of sib2, iclass 5, count 2 2006.286.05:48:57.98#ibcon#*after write, iclass 5, count 2 2006.286.05:48:57.98#ibcon#*before return 0, iclass 5, count 2 2006.286.05:48:57.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:48:57.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.286.05:48:57.98#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.286.05:48:57.98#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:57.98#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:48:58.10#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:48:58.10#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:48:58.10#ibcon#enter wrdev, iclass 5, count 0 2006.286.05:48:58.10#ibcon#first serial, iclass 5, count 0 2006.286.05:48:58.10#ibcon#enter sib2, iclass 5, count 0 2006.286.05:48:58.10#ibcon#flushed, iclass 5, count 0 2006.286.05:48:58.10#ibcon#about to write, iclass 5, count 0 2006.286.05:48:58.10#ibcon#wrote, iclass 5, count 0 2006.286.05:48:58.10#ibcon#about to read 3, iclass 5, count 0 2006.286.05:48:58.12#ibcon#read 3, iclass 5, count 0 2006.286.05:48:58.12#ibcon#about to read 4, iclass 5, count 0 2006.286.05:48:58.12#ibcon#read 4, iclass 5, count 0 2006.286.05:48:58.12#ibcon#about to read 5, iclass 5, count 0 2006.286.05:48:58.12#ibcon#read 5, iclass 5, count 0 2006.286.05:48:58.12#ibcon#about to read 6, iclass 5, count 0 2006.286.05:48:58.12#ibcon#read 6, iclass 5, count 0 2006.286.05:48:58.12#ibcon#end of sib2, iclass 5, count 0 2006.286.05:48:58.12#ibcon#*mode == 0, iclass 5, count 0 2006.286.05:48:58.12#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.286.05:48:58.12#ibcon#[27=USB\r\n] 2006.286.05:48:58.12#ibcon#*before write, iclass 5, count 0 2006.286.05:48:58.12#ibcon#enter sib2, iclass 5, count 0 2006.286.05:48:58.12#ibcon#flushed, iclass 5, count 0 2006.286.05:48:58.12#ibcon#about to write, iclass 5, count 0 2006.286.05:48:58.12#ibcon#wrote, iclass 5, count 0 2006.286.05:48:58.12#ibcon#about to read 3, iclass 5, count 0 2006.286.05:48:58.15#ibcon#read 3, iclass 5, count 0 2006.286.05:48:58.15#ibcon#about to read 4, iclass 5, count 0 2006.286.05:48:58.15#ibcon#read 4, iclass 5, count 0 2006.286.05:48:58.15#ibcon#about to read 5, iclass 5, count 0 2006.286.05:48:58.15#ibcon#read 5, iclass 5, count 0 2006.286.05:48:58.15#ibcon#about to read 6, iclass 5, count 0 2006.286.05:48:58.15#ibcon#read 6, iclass 5, count 0 2006.286.05:48:58.15#ibcon#end of sib2, iclass 5, count 0 2006.286.05:48:58.15#ibcon#*after write, iclass 5, count 0 2006.286.05:48:58.15#ibcon#*before return 0, iclass 5, count 0 2006.286.05:48:58.15#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:48:58.15#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.286.05:48:58.15#ibcon#about to clear, iclass 5 cls_cnt 0 2006.286.05:48:58.15#ibcon#cleared, iclass 5 cls_cnt 0 2006.286.05:48:58.15$vck44/vblo=7,734.99 2006.286.05:48:58.15#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.286.05:48:58.15#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.286.05:48:58.15#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:58.15#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:48:58.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:48:58.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:48:58.15#ibcon#enter wrdev, iclass 7, count 0 2006.286.05:48:58.15#ibcon#first serial, iclass 7, count 0 2006.286.05:48:58.15#ibcon#enter sib2, iclass 7, count 0 2006.286.05:48:58.15#ibcon#flushed, iclass 7, count 0 2006.286.05:48:58.15#ibcon#about to write, iclass 7, count 0 2006.286.05:48:58.15#ibcon#wrote, iclass 7, count 0 2006.286.05:48:58.15#ibcon#about to read 3, iclass 7, count 0 2006.286.05:48:58.17#ibcon#read 3, iclass 7, count 0 2006.286.05:48:58.17#ibcon#about to read 4, iclass 7, count 0 2006.286.05:48:58.17#ibcon#read 4, iclass 7, count 0 2006.286.05:48:58.17#ibcon#about to read 5, iclass 7, count 0 2006.286.05:48:58.17#ibcon#read 5, iclass 7, count 0 2006.286.05:48:58.17#ibcon#about to read 6, iclass 7, count 0 2006.286.05:48:58.17#ibcon#read 6, iclass 7, count 0 2006.286.05:48:58.17#ibcon#end of sib2, iclass 7, count 0 2006.286.05:48:58.17#ibcon#*mode == 0, iclass 7, count 0 2006.286.05:48:58.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.286.05:48:58.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.286.05:48:58.17#ibcon#*before write, iclass 7, count 0 2006.286.05:48:58.17#ibcon#enter sib2, iclass 7, count 0 2006.286.05:48:58.17#ibcon#flushed, iclass 7, count 0 2006.286.05:48:58.17#ibcon#about to write, iclass 7, count 0 2006.286.05:48:58.17#ibcon#wrote, iclass 7, count 0 2006.286.05:48:58.17#ibcon#about to read 3, iclass 7, count 0 2006.286.05:48:58.21#ibcon#read 3, iclass 7, count 0 2006.286.05:48:58.21#ibcon#about to read 4, iclass 7, count 0 2006.286.05:48:58.21#ibcon#read 4, iclass 7, count 0 2006.286.05:48:58.21#ibcon#about to read 5, iclass 7, count 0 2006.286.05:48:58.21#ibcon#read 5, iclass 7, count 0 2006.286.05:48:58.21#ibcon#about to read 6, iclass 7, count 0 2006.286.05:48:58.21#ibcon#read 6, iclass 7, count 0 2006.286.05:48:58.21#ibcon#end of sib2, iclass 7, count 0 2006.286.05:48:58.21#ibcon#*after write, iclass 7, count 0 2006.286.05:48:58.21#ibcon#*before return 0, iclass 7, count 0 2006.286.05:48:58.21#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:48:58.21#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.286.05:48:58.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.286.05:48:58.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.286.05:48:58.21$vck44/vb=7,4 2006.286.05:48:58.21#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.286.05:48:58.21#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.286.05:48:58.21#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:58.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:48:58.27#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:48:58.27#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:48:58.27#ibcon#enter wrdev, iclass 11, count 2 2006.286.05:48:58.27#ibcon#first serial, iclass 11, count 2 2006.286.05:48:58.27#ibcon#enter sib2, iclass 11, count 2 2006.286.05:48:58.27#ibcon#flushed, iclass 11, count 2 2006.286.05:48:58.27#ibcon#about to write, iclass 11, count 2 2006.286.05:48:58.27#ibcon#wrote, iclass 11, count 2 2006.286.05:48:58.27#ibcon#about to read 3, iclass 11, count 2 2006.286.05:48:58.29#ibcon#read 3, iclass 11, count 2 2006.286.05:48:58.29#ibcon#about to read 4, iclass 11, count 2 2006.286.05:48:58.29#ibcon#read 4, iclass 11, count 2 2006.286.05:48:58.29#ibcon#about to read 5, iclass 11, count 2 2006.286.05:48:58.29#ibcon#read 5, iclass 11, count 2 2006.286.05:48:58.29#ibcon#about to read 6, iclass 11, count 2 2006.286.05:48:58.29#ibcon#read 6, iclass 11, count 2 2006.286.05:48:58.29#ibcon#end of sib2, iclass 11, count 2 2006.286.05:48:58.29#ibcon#*mode == 0, iclass 11, count 2 2006.286.05:48:58.29#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.286.05:48:58.29#ibcon#[27=AT07-04\r\n] 2006.286.05:48:58.29#ibcon#*before write, iclass 11, count 2 2006.286.05:48:58.29#ibcon#enter sib2, iclass 11, count 2 2006.286.05:48:58.29#ibcon#flushed, iclass 11, count 2 2006.286.05:48:58.29#ibcon#about to write, iclass 11, count 2 2006.286.05:48:58.29#ibcon#wrote, iclass 11, count 2 2006.286.05:48:58.29#ibcon#about to read 3, iclass 11, count 2 2006.286.05:48:58.32#ibcon#read 3, iclass 11, count 2 2006.286.05:48:58.32#ibcon#about to read 4, iclass 11, count 2 2006.286.05:48:58.32#ibcon#read 4, iclass 11, count 2 2006.286.05:48:58.32#ibcon#about to read 5, iclass 11, count 2 2006.286.05:48:58.32#ibcon#read 5, iclass 11, count 2 2006.286.05:48:58.32#ibcon#about to read 6, iclass 11, count 2 2006.286.05:48:58.32#ibcon#read 6, iclass 11, count 2 2006.286.05:48:58.32#ibcon#end of sib2, iclass 11, count 2 2006.286.05:48:58.32#ibcon#*after write, iclass 11, count 2 2006.286.05:48:58.32#ibcon#*before return 0, iclass 11, count 2 2006.286.05:48:58.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:48:58.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.286.05:48:58.32#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.286.05:48:58.32#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:58.32#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:48:58.44#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:48:58.44#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:48:58.44#ibcon#enter wrdev, iclass 11, count 0 2006.286.05:48:58.44#ibcon#first serial, iclass 11, count 0 2006.286.05:48:58.44#ibcon#enter sib2, iclass 11, count 0 2006.286.05:48:58.44#ibcon#flushed, iclass 11, count 0 2006.286.05:48:58.44#ibcon#about to write, iclass 11, count 0 2006.286.05:48:58.44#ibcon#wrote, iclass 11, count 0 2006.286.05:48:58.44#ibcon#about to read 3, iclass 11, count 0 2006.286.05:48:58.46#ibcon#read 3, iclass 11, count 0 2006.286.05:48:58.46#ibcon#about to read 4, iclass 11, count 0 2006.286.05:48:58.46#ibcon#read 4, iclass 11, count 0 2006.286.05:48:58.46#ibcon#about to read 5, iclass 11, count 0 2006.286.05:48:58.46#ibcon#read 5, iclass 11, count 0 2006.286.05:48:58.46#ibcon#about to read 6, iclass 11, count 0 2006.286.05:48:58.46#ibcon#read 6, iclass 11, count 0 2006.286.05:48:58.46#ibcon#end of sib2, iclass 11, count 0 2006.286.05:48:58.46#ibcon#*mode == 0, iclass 11, count 0 2006.286.05:48:58.46#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.286.05:48:58.46#ibcon#[27=USB\r\n] 2006.286.05:48:58.46#ibcon#*before write, iclass 11, count 0 2006.286.05:48:58.46#ibcon#enter sib2, iclass 11, count 0 2006.286.05:48:58.46#ibcon#flushed, iclass 11, count 0 2006.286.05:48:58.46#ibcon#about to write, iclass 11, count 0 2006.286.05:48:58.46#ibcon#wrote, iclass 11, count 0 2006.286.05:48:58.46#ibcon#about to read 3, iclass 11, count 0 2006.286.05:48:58.49#ibcon#read 3, iclass 11, count 0 2006.286.05:48:58.49#ibcon#about to read 4, iclass 11, count 0 2006.286.05:48:58.49#ibcon#read 4, iclass 11, count 0 2006.286.05:48:58.49#ibcon#about to read 5, iclass 11, count 0 2006.286.05:48:58.49#ibcon#read 5, iclass 11, count 0 2006.286.05:48:58.49#ibcon#about to read 6, iclass 11, count 0 2006.286.05:48:58.49#ibcon#read 6, iclass 11, count 0 2006.286.05:48:58.49#ibcon#end of sib2, iclass 11, count 0 2006.286.05:48:58.49#ibcon#*after write, iclass 11, count 0 2006.286.05:48:58.49#ibcon#*before return 0, iclass 11, count 0 2006.286.05:48:58.49#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:48:58.49#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.286.05:48:58.49#ibcon#about to clear, iclass 11 cls_cnt 0 2006.286.05:48:58.49#ibcon#cleared, iclass 11 cls_cnt 0 2006.286.05:48:58.49$vck44/vblo=8,744.99 2006.286.05:48:58.49#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.286.05:48:58.49#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.286.05:48:58.49#ibcon#ireg 17 cls_cnt 0 2006.286.05:48:58.49#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:48:58.49#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:48:58.49#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:48:58.49#ibcon#enter wrdev, iclass 13, count 0 2006.286.05:48:58.49#ibcon#first serial, iclass 13, count 0 2006.286.05:48:58.49#ibcon#enter sib2, iclass 13, count 0 2006.286.05:48:58.49#ibcon#flushed, iclass 13, count 0 2006.286.05:48:58.49#ibcon#about to write, iclass 13, count 0 2006.286.05:48:58.49#ibcon#wrote, iclass 13, count 0 2006.286.05:48:58.49#ibcon#about to read 3, iclass 13, count 0 2006.286.05:48:58.51#ibcon#read 3, iclass 13, count 0 2006.286.05:48:58.51#ibcon#about to read 4, iclass 13, count 0 2006.286.05:48:58.51#ibcon#read 4, iclass 13, count 0 2006.286.05:48:58.51#ibcon#about to read 5, iclass 13, count 0 2006.286.05:48:58.51#ibcon#read 5, iclass 13, count 0 2006.286.05:48:58.51#ibcon#about to read 6, iclass 13, count 0 2006.286.05:48:58.51#ibcon#read 6, iclass 13, count 0 2006.286.05:48:58.51#ibcon#end of sib2, iclass 13, count 0 2006.286.05:48:58.51#ibcon#*mode == 0, iclass 13, count 0 2006.286.05:48:58.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.286.05:48:58.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.286.05:48:58.51#ibcon#*before write, iclass 13, count 0 2006.286.05:48:58.51#ibcon#enter sib2, iclass 13, count 0 2006.286.05:48:58.51#ibcon#flushed, iclass 13, count 0 2006.286.05:48:58.51#ibcon#about to write, iclass 13, count 0 2006.286.05:48:58.51#ibcon#wrote, iclass 13, count 0 2006.286.05:48:58.51#ibcon#about to read 3, iclass 13, count 0 2006.286.05:48:58.55#ibcon#read 3, iclass 13, count 0 2006.286.05:48:58.55#ibcon#about to read 4, iclass 13, count 0 2006.286.05:48:58.55#ibcon#read 4, iclass 13, count 0 2006.286.05:48:58.55#ibcon#about to read 5, iclass 13, count 0 2006.286.05:48:58.55#ibcon#read 5, iclass 13, count 0 2006.286.05:48:58.55#ibcon#about to read 6, iclass 13, count 0 2006.286.05:48:58.55#ibcon#read 6, iclass 13, count 0 2006.286.05:48:58.55#ibcon#end of sib2, iclass 13, count 0 2006.286.05:48:58.55#ibcon#*after write, iclass 13, count 0 2006.286.05:48:58.55#ibcon#*before return 0, iclass 13, count 0 2006.286.05:48:58.55#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:48:58.55#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.286.05:48:58.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.286.05:48:58.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.286.05:48:58.55$vck44/vb=8,4 2006.286.05:48:58.55#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.286.05:48:58.55#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.286.05:48:58.55#ibcon#ireg 11 cls_cnt 2 2006.286.05:48:58.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:48:58.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:48:58.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:48:58.61#ibcon#enter wrdev, iclass 15, count 2 2006.286.05:48:58.61#ibcon#first serial, iclass 15, count 2 2006.286.05:48:58.61#ibcon#enter sib2, iclass 15, count 2 2006.286.05:48:58.61#ibcon#flushed, iclass 15, count 2 2006.286.05:48:58.61#ibcon#about to write, iclass 15, count 2 2006.286.05:48:58.61#ibcon#wrote, iclass 15, count 2 2006.286.05:48:58.61#ibcon#about to read 3, iclass 15, count 2 2006.286.05:48:58.63#ibcon#read 3, iclass 15, count 2 2006.286.05:48:58.63#ibcon#about to read 4, iclass 15, count 2 2006.286.05:48:58.63#ibcon#read 4, iclass 15, count 2 2006.286.05:48:58.63#ibcon#about to read 5, iclass 15, count 2 2006.286.05:48:58.63#ibcon#read 5, iclass 15, count 2 2006.286.05:48:58.63#ibcon#about to read 6, iclass 15, count 2 2006.286.05:48:58.63#ibcon#read 6, iclass 15, count 2 2006.286.05:48:58.63#ibcon#end of sib2, iclass 15, count 2 2006.286.05:48:58.63#ibcon#*mode == 0, iclass 15, count 2 2006.286.05:48:58.63#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.286.05:48:58.63#ibcon#[27=AT08-04\r\n] 2006.286.05:48:58.63#ibcon#*before write, iclass 15, count 2 2006.286.05:48:58.63#ibcon#enter sib2, iclass 15, count 2 2006.286.05:48:58.63#ibcon#flushed, iclass 15, count 2 2006.286.05:48:58.63#ibcon#about to write, iclass 15, count 2 2006.286.05:48:58.63#ibcon#wrote, iclass 15, count 2 2006.286.05:48:58.63#ibcon#about to read 3, iclass 15, count 2 2006.286.05:48:58.66#ibcon#read 3, iclass 15, count 2 2006.286.05:48:58.66#ibcon#about to read 4, iclass 15, count 2 2006.286.05:48:58.66#ibcon#read 4, iclass 15, count 2 2006.286.05:48:58.66#ibcon#about to read 5, iclass 15, count 2 2006.286.05:48:58.66#ibcon#read 5, iclass 15, count 2 2006.286.05:48:58.66#ibcon#about to read 6, iclass 15, count 2 2006.286.05:48:58.66#ibcon#read 6, iclass 15, count 2 2006.286.05:48:58.66#ibcon#end of sib2, iclass 15, count 2 2006.286.05:48:58.66#ibcon#*after write, iclass 15, count 2 2006.286.05:48:58.66#ibcon#*before return 0, iclass 15, count 2 2006.286.05:48:58.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:48:58.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.286.05:48:58.66#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.286.05:48:58.66#ibcon#ireg 7 cls_cnt 0 2006.286.05:48:58.66#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:48:58.78#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:48:58.78#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:48:58.78#ibcon#enter wrdev, iclass 15, count 0 2006.286.05:48:58.78#ibcon#first serial, iclass 15, count 0 2006.286.05:48:58.78#ibcon#enter sib2, iclass 15, count 0 2006.286.05:48:58.78#ibcon#flushed, iclass 15, count 0 2006.286.05:48:58.78#ibcon#about to write, iclass 15, count 0 2006.286.05:48:58.78#ibcon#wrote, iclass 15, count 0 2006.286.05:48:58.78#ibcon#about to read 3, iclass 15, count 0 2006.286.05:48:58.80#ibcon#read 3, iclass 15, count 0 2006.286.05:48:58.80#ibcon#about to read 4, iclass 15, count 0 2006.286.05:48:58.80#ibcon#read 4, iclass 15, count 0 2006.286.05:48:58.80#ibcon#about to read 5, iclass 15, count 0 2006.286.05:48:58.80#ibcon#read 5, iclass 15, count 0 2006.286.05:48:58.80#ibcon#about to read 6, iclass 15, count 0 2006.286.05:48:58.80#ibcon#read 6, iclass 15, count 0 2006.286.05:48:58.80#ibcon#end of sib2, iclass 15, count 0 2006.286.05:48:58.80#ibcon#*mode == 0, iclass 15, count 0 2006.286.05:48:58.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.286.05:48:58.80#ibcon#[27=USB\r\n] 2006.286.05:48:58.80#ibcon#*before write, iclass 15, count 0 2006.286.05:48:58.80#ibcon#enter sib2, iclass 15, count 0 2006.286.05:48:58.80#ibcon#flushed, iclass 15, count 0 2006.286.05:48:58.80#ibcon#about to write, iclass 15, count 0 2006.286.05:48:58.80#ibcon#wrote, iclass 15, count 0 2006.286.05:48:58.80#ibcon#about to read 3, iclass 15, count 0 2006.286.05:48:58.83#ibcon#read 3, iclass 15, count 0 2006.286.05:48:58.83#ibcon#about to read 4, iclass 15, count 0 2006.286.05:48:58.83#ibcon#read 4, iclass 15, count 0 2006.286.05:48:58.83#ibcon#about to read 5, iclass 15, count 0 2006.286.05:48:58.83#ibcon#read 5, iclass 15, count 0 2006.286.05:48:58.83#ibcon#about to read 6, iclass 15, count 0 2006.286.05:48:58.83#ibcon#read 6, iclass 15, count 0 2006.286.05:48:58.83#ibcon#end of sib2, iclass 15, count 0 2006.286.05:48:58.83#ibcon#*after write, iclass 15, count 0 2006.286.05:48:58.83#ibcon#*before return 0, iclass 15, count 0 2006.286.05:48:58.83#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:48:58.83#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.286.05:48:58.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.286.05:48:58.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.286.05:48:58.83$vck44/vabw=wide 2006.286.05:48:58.83#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.286.05:48:58.83#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.286.05:48:58.83#ibcon#ireg 8 cls_cnt 0 2006.286.05:48:58.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:48:58.83#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:48:58.83#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:48:58.83#ibcon#enter wrdev, iclass 17, count 0 2006.286.05:48:58.83#ibcon#first serial, iclass 17, count 0 2006.286.05:48:58.83#ibcon#enter sib2, iclass 17, count 0 2006.286.05:48:58.83#ibcon#flushed, iclass 17, count 0 2006.286.05:48:58.83#ibcon#about to write, iclass 17, count 0 2006.286.05:48:58.83#ibcon#wrote, iclass 17, count 0 2006.286.05:48:58.83#ibcon#about to read 3, iclass 17, count 0 2006.286.05:48:58.85#ibcon#read 3, iclass 17, count 0 2006.286.05:48:58.85#ibcon#about to read 4, iclass 17, count 0 2006.286.05:48:58.85#ibcon#read 4, iclass 17, count 0 2006.286.05:48:58.85#ibcon#about to read 5, iclass 17, count 0 2006.286.05:48:58.85#ibcon#read 5, iclass 17, count 0 2006.286.05:48:58.85#ibcon#about to read 6, iclass 17, count 0 2006.286.05:48:58.85#ibcon#read 6, iclass 17, count 0 2006.286.05:48:58.85#ibcon#end of sib2, iclass 17, count 0 2006.286.05:48:58.85#ibcon#*mode == 0, iclass 17, count 0 2006.286.05:48:58.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.286.05:48:58.85#ibcon#[25=BW32\r\n] 2006.286.05:48:58.85#ibcon#*before write, iclass 17, count 0 2006.286.05:48:58.85#ibcon#enter sib2, iclass 17, count 0 2006.286.05:48:58.85#ibcon#flushed, iclass 17, count 0 2006.286.05:48:58.85#ibcon#about to write, iclass 17, count 0 2006.286.05:48:58.85#ibcon#wrote, iclass 17, count 0 2006.286.05:48:58.85#ibcon#about to read 3, iclass 17, count 0 2006.286.05:48:58.88#ibcon#read 3, iclass 17, count 0 2006.286.05:48:58.88#ibcon#about to read 4, iclass 17, count 0 2006.286.05:48:58.88#ibcon#read 4, iclass 17, count 0 2006.286.05:48:58.88#ibcon#about to read 5, iclass 17, count 0 2006.286.05:48:58.88#ibcon#read 5, iclass 17, count 0 2006.286.05:48:58.88#ibcon#about to read 6, iclass 17, count 0 2006.286.05:48:58.88#ibcon#read 6, iclass 17, count 0 2006.286.05:48:58.88#ibcon#end of sib2, iclass 17, count 0 2006.286.05:48:58.88#ibcon#*after write, iclass 17, count 0 2006.286.05:48:58.88#ibcon#*before return 0, iclass 17, count 0 2006.286.05:48:58.88#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:48:58.88#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.286.05:48:58.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.286.05:48:58.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.286.05:48:58.88$vck44/vbbw=wide 2006.286.05:48:58.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.286.05:48:58.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.286.05:48:58.88#ibcon#ireg 8 cls_cnt 0 2006.286.05:48:58.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:48:58.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:48:58.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:48:58.95#ibcon#enter wrdev, iclass 19, count 0 2006.286.05:48:58.95#ibcon#first serial, iclass 19, count 0 2006.286.05:48:58.95#ibcon#enter sib2, iclass 19, count 0 2006.286.05:48:58.95#ibcon#flushed, iclass 19, count 0 2006.286.05:48:58.95#ibcon#about to write, iclass 19, count 0 2006.286.05:48:58.95#ibcon#wrote, iclass 19, count 0 2006.286.05:48:58.95#ibcon#about to read 3, iclass 19, count 0 2006.286.05:48:58.97#ibcon#read 3, iclass 19, count 0 2006.286.05:48:58.97#ibcon#about to read 4, iclass 19, count 0 2006.286.05:48:58.97#ibcon#read 4, iclass 19, count 0 2006.286.05:48:58.97#ibcon#about to read 5, iclass 19, count 0 2006.286.05:48:58.97#ibcon#read 5, iclass 19, count 0 2006.286.05:48:58.97#ibcon#about to read 6, iclass 19, count 0 2006.286.05:48:58.97#ibcon#read 6, iclass 19, count 0 2006.286.05:48:58.97#ibcon#end of sib2, iclass 19, count 0 2006.286.05:48:58.97#ibcon#*mode == 0, iclass 19, count 0 2006.286.05:48:58.97#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.286.05:48:58.97#ibcon#[27=BW32\r\n] 2006.286.05:48:58.97#ibcon#*before write, iclass 19, count 0 2006.286.05:48:58.97#ibcon#enter sib2, iclass 19, count 0 2006.286.05:48:58.97#ibcon#flushed, iclass 19, count 0 2006.286.05:48:58.97#ibcon#about to write, iclass 19, count 0 2006.286.05:48:58.97#ibcon#wrote, iclass 19, count 0 2006.286.05:48:58.97#ibcon#about to read 3, iclass 19, count 0 2006.286.05:48:59.00#ibcon#read 3, iclass 19, count 0 2006.286.05:48:59.00#ibcon#about to read 4, iclass 19, count 0 2006.286.05:48:59.00#ibcon#read 4, iclass 19, count 0 2006.286.05:48:59.00#ibcon#about to read 5, iclass 19, count 0 2006.286.05:48:59.00#ibcon#read 5, iclass 19, count 0 2006.286.05:48:59.00#ibcon#about to read 6, iclass 19, count 0 2006.286.05:48:59.00#ibcon#read 6, iclass 19, count 0 2006.286.05:48:59.00#ibcon#end of sib2, iclass 19, count 0 2006.286.05:48:59.00#ibcon#*after write, iclass 19, count 0 2006.286.05:48:59.00#ibcon#*before return 0, iclass 19, count 0 2006.286.05:48:59.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:48:59.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.286.05:48:59.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.286.05:48:59.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.286.05:48:59.00$setupk4/ifdk4 2006.286.05:48:59.00$ifdk4/lo= 2006.286.05:48:59.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.286.05:48:59.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.286.05:48:59.00$ifdk4/patch= 2006.286.05:48:59.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.286.05:48:59.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.286.05:48:59.00$setupk4/!*+20s 2006.286.05:49:05.64#abcon#<5=/04 3.7 7.2 20.61 801015.3\r\n> 2006.286.05:49:05.66#abcon#{5=INTERFACE CLEAR} 2006.286.05:49:05.72#abcon#[5=S1D000X0/0*\r\n] 2006.286.05:49:12.82$setupk4/"tpicd 2006.286.05:49:12.82$setupk4/echo=off 2006.286.05:49:12.82$setupk4/xlog=off 2006.286.05:49:12.82:!2006.286.05:53:29 2006.286.05:49:45.13#trakl#Source acquired 2006.286.05:49:47.13#flagr#flagr/antenna,acquired 2006.286.05:50:39.14#trakl#Off source 2006.286.05:50:39.14?ERROR st -7 Antenna off-source! 2006.286.05:50:39.14#trakl#az 86.462 el 20.089 azerr*cos(el) 0.0174 elerr -0.0055 2006.286.05:50:41.14#flagr#flagr/antenna,off-source 2006.286.05:50:45.14#trakl#Source re-acquired 2006.286.05:50:47.14#flagr#flagr/antenna,re-acquired 2006.286.05:52:25.14#trakl#Off source 2006.286.05:52:25.14?ERROR st -7 Antenna off-source! 2006.286.05:52:25.14#trakl#az 86.715 el 20.445 azerr*cos(el) 0.0193 elerr 0.0001 2006.286.05:52:26.14#flagr#flagr/antenna,off-source 2006.286.05:52:31.14#trakl#Source re-acquired 2006.286.05:52:32.14#flagr#flagr/antenna,re-acquired 2006.286.05:53:29.00:preob 2006.286.05:53:30.14/onsource/TRACKING 2006.286.05:53:30.14:!2006.286.05:53:39 2006.286.05:53:39.00:"tape 2006.286.05:53:39.00:"st=record 2006.286.05:53:39.00:data_valid=on 2006.286.05:53:39.00:midob 2006.286.05:53:39.14/onsource/TRACKING 2006.286.05:53:39.14/wx/20.52,1015.4,80 2006.286.05:53:39.24/cable/+6.4929E-03 2006.286.05:53:40.33/va/01,07,usb,yes,34,37 2006.286.05:53:40.33/va/02,06,usb,yes,34,34 2006.286.05:53:40.33/va/03,07,usb,yes,33,35 2006.286.05:53:40.33/va/04,06,usb,yes,35,37 2006.286.05:53:40.33/va/05,03,usb,yes,35,35 2006.286.05:53:40.33/va/06,04,usb,yes,31,31 2006.286.05:53:40.33/va/07,04,usb,yes,32,32 2006.286.05:53:40.33/va/08,03,usb,yes,32,39 2006.286.05:53:40.56/valo/01,524.99,yes,locked 2006.286.05:53:40.56/valo/02,534.99,yes,locked 2006.286.05:53:40.56/valo/03,564.99,yes,locked 2006.286.05:53:40.56/valo/04,624.99,yes,locked 2006.286.05:53:40.56/valo/05,734.99,yes,locked 2006.286.05:53:40.56/valo/06,814.99,yes,locked 2006.286.05:53:40.56/valo/07,864.99,yes,locked 2006.286.05:53:40.56/valo/08,884.99,yes,locked 2006.286.05:53:41.65/vb/01,04,usb,yes,31,29 2006.286.05:53:41.65/vb/02,05,usb,yes,30,29 2006.286.05:53:41.65/vb/03,04,usb,yes,30,34 2006.286.05:53:41.65/vb/04,05,usb,yes,31,30 2006.286.05:53:41.65/vb/05,04,usb,yes,27,30 2006.286.05:53:41.65/vb/06,03,usb,yes,39,35 2006.286.05:53:41.65/vb/07,04,usb,yes,31,32 2006.286.05:53:41.65/vb/08,04,usb,yes,29,32 2006.286.05:53:41.88/vblo/01,629.99,yes,locked 2006.286.05:53:41.88/vblo/02,634.99,yes,locked 2006.286.05:53:41.88/vblo/03,649.99,yes,locked 2006.286.05:53:41.88/vblo/04,679.99,yes,locked 2006.286.05:53:41.88/vblo/05,709.99,yes,locked 2006.286.05:53:41.88/vblo/06,719.99,yes,locked 2006.286.05:53:41.88/vblo/07,734.99,yes,locked 2006.286.05:53:41.88/vblo/08,744.99,yes,locked 2006.286.05:53:42.03/vabw/8 2006.286.05:53:42.18/vbbw/8 2006.286.05:53:42.27/xfe/off,on,12.0 2006.286.05:53:42.64/ifatt/23,28,28,28 2006.286.05:53:43.07/fmout-gps/S +2.60E-07 2006.286.05:53:43.09:!2006.286.05:55:19 2006.286.05:55:19.00:data_valid=off 2006.286.05:55:19.00:"et 2006.286.05:55:19.00:!+3s 2006.286.05:55:22.01:"tape 2006.286.05:55:22.01:postob 2006.286.05:55:22.23/cable/+6.4925E-03 2006.286.05:55:22.23/wx/20.49,1015.4,80 2006.286.05:55:23.07/fmout-gps/S +2.60E-07 2006.286.05:55:23.07:"unlod=1 2006.286.05:55:23.07:sched_end 2006.286.05:55:23.07&sched_end/stopcheck 2006.286.05:55:23.07&stopcheck/sy=killall check_fsrun.pl 2006.286.05:55:23.07&stopcheck/" sy=killall chmem.sh 2006.286.05:55:23.11:checkk5last 2006.286.05:55:23.11&checkk5last/chk_obsdata=1 2006.286.05:55:23.11&checkk5last/chk_obsdata=2 2006.286.05:55:23.11&checkk5last/chk_obsdata=3 2006.286.05:55:23.11&checkk5last/chk_obsdata=4 2006.286.05:55:23.11&checkk5last/k5log=1 2006.286.05:55:23.11&checkk5last/k5log=2 2006.286.05:55:23.11&checkk5last/k5log=3 2006.286.05:55:23.11&checkk5last/k5log=4 2006.286.05:55:23.11&checkk5last/obsinfo 2006.286.05:55:23.61/chk_obsdata//k5ts1/T2860553??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.286.05:55:24.00/chk_obsdata//k5ts2/T2860553??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.286.05:55:24.54/chk_obsdata//k5ts3/T2860553??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.286.05:55:25.01/chk_obsdata//k5ts4/T2860553??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.286.05:55:25.90/k5log//k5ts1_log_newline 2006.286.05:55:26.67/k5log//k5ts2_log_newline 2006.286.05:55:27.69/k5log//k5ts3_log_newline 2006.286.05:55:28.68/k5log//k5ts4_log_newline 2006.286.05:55:28.71/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.286.05:55:28.71:checkk5hdd 2006.286.05:55:28.71&checkk5hdd/chk_hdd=1 2006.286.05:55:28.71&checkk5hdd/chk_hdd=2 2006.286.05:55:28.71&checkk5hdd/chk_hdd=3 2006.286.05:55:28.71&checkk5hdd/chk_hdd=4 2006.286.05:55:32.28/chk_hdd//k5ts1/GSI00275:T285060000a.dat~T286055339a.dat[125072441344Byte] 2006.286.05:55:36.58/chk_hdd//k5ts2/GSI00163:T285060000b.dat~T286055339b.dat[125072441344Byte] 2006.286.05:55:40.06/chk_hdd//k5ts3/GSI00278:T285060000c.dat~T286055339c.dat[125072441344Byte] 2006.286.05:55:43.61/chk_hdd//k5ts4/GSI00141:T285060000d.dat~T286055339d.dat[125072441344Byte] 2006.286.05:55:43.61:sy=cp /usr2/log/jd0610ts.log /usr2/log_backup/ 2006.286.05:55:43.87:*end of schedule 2006.286.05:57:07.13#trakl#Off source 2006.286.05:57:07.13?ERROR st -7 Antenna off-source! 2006.286.05:57:07.13#trakl#az 87.391 el 21.393 azerr*cos(el) 0.0171 elerr -0.0025 2006.286.05:57:08.13#flagr#flagr/antenna,off-source 2006.286.05:57:13.13#trakl#Source re-acquired 2006.286.05:57:14.13#flagr#flagr/antenna,re-acquired 2006.286.05:57:31.27;cable 2006.286.05:57:31.48/cable/+6.4930E-03 2006.286.05:58:44.14#trakl#Off source 2006.286.05:58:44.14?ERROR st -7 Antenna off-source! 2006.286.05:58:44.14#trakl#az 87.624 el 21.720 azerr*cos(el) -0.0007 elerr 0.0210 2006.286.05:58:44.14#flagr#flagr/antenna,off-source 2006.286.05:58:54.14#trakl#Source re-acquired 2006.286.05:58:55.67;cablelong 2006.286.05:58:55.90/cablelong/+7.0434E-03 2006.286.05:58:56.14#flagr#flagr/antenna,re-acquired 2006.286.05:59:04.76;cablediff 2006.286.05:59:04.76/cablediff/550.4e-6,+ 2006.286.05:59:06.14#trakl#Off source 2006.286.05:59:06.14?ERROR st -7 Antenna off-source! 2006.286.05:59:06.14#trakl#az 87.677 el 21.794 azerr*cos(el) 0.0226 elerr -0.0030 2006.286.05:59:08.14#flagr#flagr/antenna,off-source 2006.286.05:59:12.14#trakl#Source re-acquired 2006.286.05:59:14.14#flagr#flagr/antenna,re-acquired 2006.286.06:00:03.22;cable 2006.286.06:00:03.40/cable/+6.4922E-03 2006.286.06:00:31.18;wx 2006.286.06:00:31.19/wx/20.41,1015.4,79 2006.286.06:00:39.23;"Sky is cloudy 2006.286.06:00:45.53;clockoff 2006.286.06:00:46.07/fmout-gps/S +2.48E-07 2006.286.06:02:21.31;xfe 2006.286.06:02:21.40/xfe/off,on,12.0 2006.286.06:05:22.13#trakl#Off source 2006.286.06:05:22.13?ERROR st -7 Antenna off-source! 2006.286.06:05:22.13#trakl#az 88.585 el 23.060 azerr*cos(el) 0.0177 elerr -0.0003 2006.286.06:05:23.13#flagr#flagr/antenna,off-source 2006.286.06:05:28.13#trakl#Source re-acquired 2006.286.06:05:29.13#flagr#flagr/antenna,re-acquired 2006.286.06:06:02.84;proc=point 2006.286.06:06:05.85;initp 2006.286.06:06:05.85&initp/"setup 2006.286.06:06:05.85&initp/abib=p2,pr 2006.286.06:06:05.85&initp/abib=p1,pr 2006.286.06:06:05.85&initp/!+1s 2006.286.06:06:05.85&initp/abib=p2,ln 2006.286.06:06:05.85&initp/abib=p2,rm3en 2006.286.06:06:05.85&initp/abib=p2,fm2en 2006.286.06:06:05.85&initp/abib=p2,ap 2006.286.06:06:05.85&initp/abib=p2 2006.286.06:06:05.85&initp/abib=p1,ln 2006.286.06:06:05.85&initp/abib=p1,rm3en 2006.286.06:06:05.85&initp/abib=p1,fm2en 2006.286.06:06:05.85&initp/"meter 1 (u6) has s band 2006.286.06:06:05.85&initp/abib=p1,ap 2006.286.06:06:05.85&initp/abib=p1 2006.286.06:06:05.85&initp/caloff 2006.286.06:06:05.85&initp/user_device=u5,7680,usb,rcp,750 2006.286.06:06:05.85&initp/user_device=u6,1600,usb,rcp,750 2006.286.06:06:05.85&initp/sigon 2006.286.06:06:05.85&initp/"sample fivept set-up for azel antenna with mark iii/iv rack 2006.286.06:06:05.85&initp/"fivept=azel,-2,9,.4,1,i1,120 2006.286.06:06:05.85&initp/"sample fivept set-up for xyns antenna with vlba/4 rack 2006.286.06:06:05.85&initp/"fivept=xyns,-2,9,.4,1,ia,120 2006.286.06:06:05.85&initp/" for tsukuba 2006.286.06:06:05.85&initp/"fivept=azel,-2,9,.4,1,u5,120 2006.286.06:06:05.85&initp/fivept=azel,-2,7,.3,1,u5,120 2006.286.06:06:05.85&initp/" sample onoff set-up for mark iii/iv 2006.286.06:06:05.85&initp/"onoff=2,1,75,3,120,all 2006.286.06:06:05.85&initp/" sample onoff set-up for vlba/4 2006.286.06:06:05.85&initp/"onoff=2,1,75,3,120,allu,ia,ib,ic 2006.286.06:06:05.85&initp/" for tsukuba 2006.286.06:06:05.85&initp/"onoff=2,1,75,3,120,u5,u6 2006.286.06:06:05.85&initp/" changed wait time into 60 sec (04-jun-2004 -sk-) 2006.286.06:06:05.85&initp/onoff=2,1,75,3,60,u5,u6 2006.286.06:06:05.85&initp/check= 2006.286.06:06:05.85&initp/sy=go aquir & 2006.286.06:06:07.87/abib/+0.0590E-03 2006.286.06:06:08.77/abib/+0.0480E-03 2006.286.06:06:08.77&caloff/"rx=*,*,*,*,*,*,off 2006.286.06:06:08.77&sigon/ifatt=23,28,28,28 2006.286.06:06:08.77&sigon/!+2s 2006.286.06:06:20.80;cygnusa 2006.286.06:06:20.81&cygnusa/source=cygnusa,195928.4,+404402.,2000. 2006.286.06:06:21.13#flagr#flagr/antenna,new-source 2006.286.06:06:41.13#trakl#Source acquired 2006.286.06:06:43.13#flagr#flagr/antenna,acquired 2006.286.06:07:51.85;fivept 2006.286.06:07:51.85#fivpt#source cygnusa 195928.4 +404402 2000.0 2006.286.06:07:51 2006.286.06:07:51.85#fivpt#site TSUKUB32 -140.089 36.1036 32.00 xxxx 0 1.00 0.00 2006.286.06:07:51.85#fivpt#fivept azel -2 7 0.30 1 u5 -100. 0.0777 168.4 2006.286.06:07:51.85#fivpt#origin 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 2006.286.06:08:03.14;sigofffp 2006.286.06:08:03.14&sigofffp/sigoff 2006.286.06:08:03.14&sigofffp/sy=go fivpt & 2006.286.06:08:03.14&sigoff/ifatt=81,81,81,81 2006.286.06:08:03.14&sigoff/!+2s 2006.286.06:08:05.29;sigonfp 2006.286.06:08:05.29&sigonfp/sigon 2006.286.06:08:05.29&sigonfp/sy=go fivpt & 2006.286.06:08:06.15#trakl#Off source 2006.286.06:08:06.15?ERROR st -7 Antenna off-source! 2006.286.06:08:06.15#trakl#az 68.913 el 53.946 azerr*cos(el) 0.0004 elerr -0.0096 2006.286.06:08:08.61#fivpt#tsys 68.928 53.931 100.000 2006.286.06:08:23.27#fivpt#lat 1 22103. -0.0756 1.887 2006.286.06:08:34.27#fivpt#lat 2 22114. -0.0504 13.208 2006.286.06:08:43.27#fivpt#lat 3 22123. -0.0252 43.396 2006.286.06:08:53.27#fivpt#lat 4 22133. 0.0000 66.038 2006.286.06:09:02.27#fivpt#lat 5 22142. 0.0252 49.057 2006.286.06:09:12.27#fivpt#lat 6 22152. 0.0504 26.415 2006.286.06:09:22.27#fivpt#lat 7 22162. 0.0756 5.660 2006.286.06:09:22.27#fivpt#latfit 0.00329 0.0759 65.0930 -0.2704 0.0644 6 2006.286.06:09:22.27#fivpt#laterr 0.00227 0.0078 4.4964 4.4829 0.0960 3.5421 2006.286.06:09:38.27#fivpt#lon 1 22178. -0.1285 1.887 2006.286.06:09:47.27#fivpt#lon 2 22187. -0.0857 7.547 2006.286.06:09:56.27#fivpt#lon 3 22196. -0.0428 41.509 2006.286.06:10:05.27#fivpt#lon 4 22205. -0.0000 69.811 2006.286.06:10:14.27#fivpt#lon 5 22214. 0.0428 52.830 2006.286.06:10:23.27#fivpt#lon 6 22223. 0.0857 15.094 2006.286.06:10:32.27#fivpt#lon 7 22232. 0.1285 1.887 2006.286.06:10:32.27#fivpt#lonfit 0.00645 0.0635 71.8040 -0.2903 -0.0091 7 2006.286.06:10:32.27#fivpt#lonerr 0.00164 0.0029 2.2481 1.7730 0.0528 2.0708 2006.286.06:10:32.27#fivpt#perform -0.718 234.5 1.464 14.639 2006.286.06:10:41.14#fivpt#offset 68.2789 54.2047 0.00645 0.00329 1 1 2006.286.06:10:41.14#fivpt#xoffset 68.2789 54.2047 0.00377 0.00329 0.00096 0.00227 1 1 2006.286.06:11:31.14#trakl#Off source 2006.286.06:11:31.14?ERROR st -7 Antenna off-source! 2006.286.06:11:31.14#trakl#az 68.355 el 54.592 azerr*cos(el) -0.0012 elerr -0.0090 2006.286.06:11:31.14#flagr#flagr/antenna,off-source 2006.286.06:11:37.14#trakl#Source re-acquired 2006.286.06:11:37.14#flagr#flagr/antenna,re-acquired 2006.286.06:11:55.89;azeloff 2006.286.06:11:55.89/azeloff/0.00645,0.00329 2006.286.06:12:00.82;azeloff=0d,0d 2006.286.06:12:04.14#flagr#flagr/antenna,off-source 2006.286.06:12:08.14#trakl#Source acquired 2006.286.06:12:10.15#flagr#flagr/antenna,re-acquired 2006.286.06:12:21.79;onoff 2006.286.06:12:21.79#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.286.06:12:21.79#onoff#APR u5 8430.00 -100. 168.4 0.167000 1.00000 0.167000 7680.00 c 0.07768 2006.286.06:12:21.79#onoff#APR u6 2350.00 -100. 919.3 0.209000 1.00000 0.209000 1600.00 c 0.27867 2006.286.06:12:23.15#onoff#ORIG 22343.2 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.286.06:12:24.42#onoff#ONSO 1.3 0.00000 0.00000 u5 89 u6 155 2006.286.06:12:34.37#onoff#OFFS 11.2 1.45885 0.00000 u5 54 u6 44 2006.286.06:12:34.38;sigoffnf 2006.286.06:12:34.38&sigoffnf/sigoff 2006.286.06:12:34.38&sigoffnf/sy=go onoff & 2006.286.06:12:37.14#trakl#Off source 2006.286.06:12:37.14?ERROR st -7 Antenna off-source! 2006.286.06:12:37.14#trakl#az 69.854 el 54.796 azerr*cos(el) -0.0033 elerr -0.0100 2006.286.06:12:37.77;sigonnf 2006.286.06:12:37.77&sigonnf/sigon 2006.286.06:12:37.77&sigonnf/sy=go onoff & 2006.286.06:12:39.95#onoff#ZERO 14.6 1.45885 0.00000 u5 0 u6 0 2006.286.06:12:49.38#onoff#ONSO 26.2 0.00000 0.00000 u5 88 u6 160 2006.286.06:12:59.38#onoff#OFFS 36.2 -1.45885 -0.00000 u5 55 u6 44 2006.286.06:13:37.37#onoff#ONSO 74.2 0.00000 0.00000 u5 89 u6 153 2006.286.06:13:37.37#onoff#SIG u5 0.00 0.00 9.7 0.000 0.000 0.00 2006.286.06:13:37.37#onoff#SIG u6 0.00 0.00 8.7 0.000 0.000 0.00 2006.286.06:13:37.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.286.06:13:37.37#onoff#VAL cygnusa 68.4 54.8 u5 5 r 8430.00 1.0000 -100. 268.6 0.000 0.0000 2006.286.06:13:37.37#onoff#VAL cygnusa 68.4 54.8 u6 6 r 2350.00 1.0000 -100. 361.1 0.000 0.0000 2006.286.06:13:37.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.286.06:14:00.00;virgoa 2006.286.06:14:00.00&virgoa/source=virgoa,123049.42,+122328.0,2000. 2006.286.06:14:01.14#flagr#flagr/antenna,new-source 2006.286.06:15:12.13#trakl#Source acquired 2006.286.06:15:14.13#flagr#flagr/antenna,acquired 2006.286.06:15:27.64;fivept 2006.286.06:15:27.64#fivpt#source virgoa 123049.4 +122328 2000.0 2006.286.06:15:27 2006.286.06:15:27.64#fivpt#site TSUKUB32 -140.089 36.1036 32.00 xxxx 0 1.00 0.00 2006.286.06:15:27.64#fivpt#fivept azel -2 7 0.30 1 u5 -100. 0.0777 42.6 2006.286.06:15:27.64#fivpt#origin 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 2006.286.06:15:38.14;sigofffp 2006.286.06:15:40.29;sigonfp 2006.286.06:15:43.61#fivpt#tsys 266.675 25.066 100.000 2006.286.06:15:56.27#fivpt#lat 1 22556. -0.0860 1.667 2006.286.06:16:05.27#fivpt#lat 2 22565. -0.0573 1.667 2006.286.06:16:14.27#fivpt#lat 3 22574. -0.0287 10.000 2006.286.06:16:23.27#fivpt#lat 4 22583. 0.0000 11.667 2006.286.06:16:37.27#fivpt#lat 5 22597. 0.0287 6.667 2006.286.06:16:46.27#fivpt#lat 6 22606. 0.0573 -1.667 2006.286.06:16:55.27#fivpt#lat 7 22615. 0.0860 -1.667 2006.286.06:16:55.27#fivpt#latfit 1.47482 -17.000 777.965 -917.11 -1.4556 -1 2006.286.06:16:55.27#fivpt#laterr 0.00227 0.0078 4.4964 0.0000 0.0000 3.5421 2006.286.06:17:09.27#fivpt#lon 1 22629. -0.0949 -1.667 2006.286.06:17:18.27#fivpt#lon 2 22638. -0.0632 1.667 2006.286.06:17:28.27#fivpt#lon 3 22648. -0.0316 10.000 2006.286.06:17:40.27#fivpt#lon 4 22660. 0.0000 13.333 2006.286.06:17:52.27#fivpt#lon 5 22672. 0.0316 6.667 2006.286.06:18:01.27#fivpt#lon 6 22681. 0.0632 -0.000 2006.286.06:18:10.27#fivpt#lon 7 22690. 0.0949 -0.000 2006.286.06:18:10.27#fivpt#lonfit -0.00765 0.0693 15.1764 -1.2821 0.0263 7 2006.286.06:18:10.27#fivpt#lonerr 0.00165 0.0043 0.6562 0.4882 0.0135 0.6053 2006.286.06:18:10.27#fivpt#perform 0.000 0.0 0.000 0.000 2006.286.06:18:10.27#fivpt#offset 267.4273 24.7701 -0.00765 0.00000 1 0 2006.286.06:18:22.27#fivpt#lat 1 22702. -0.0860 -0.000 2006.286.06:18:31.27#fivpt#lat 2 22711. -0.0573 1.667 2006.286.06:18:40.27#fivpt#lat 3 22720. -0.0287 8.333 2006.286.06:18:49.27#fivpt#lat 4 22729. 0.0000 13.333 2006.286.06:18:58.27#fivpt#lat 5 22738. 0.0287 6.667 2006.286.06:19:08.27#fivpt#lat 6 22748. 0.0573 -0.000 2006.286.06:19:17.27#fivpt#lat 7 22757. 0.0860 -1.667 2006.286.06:19:17.27#fivpt#latfit -0.00187 0.0659 14.2856 -0.9373 -0.0301 5 2006.286.06:19:17.27#fivpt#laterr 0.00013 0.0004 0.0586 0.0403 0.0013 0.0547 2006.286.06:19:30.27#fivpt#lon 1 22770. -0.1021 -1.667 2006.286.06:19:39.27#fivpt#lon 2 22779. -0.0706 -0.000 2006.286.06:19:48.27#fivpt#lon 3 22788. -0.0391 6.667 2006.286.06:19:57.27#fivpt#lon 4 22797. -0.0077 11.667 2006.286.06:20:06.27#fivpt#lon 5 22806. 0.0238 5.000 2006.286.06:20:18.27#fivpt#lon 6 22818. 0.0553 -0.000 2006.286.06:20:19.14#trakl#Off source 2006.286.06:20:19.14?ERROR st -7 Antenna off-source! 2006.286.06:20:19.14#trakl#az 267.979 el 24.083 azerr*cos(el) -0.0095 elerr -0.0047 2006.286.06:20:27.27#fivpt#lon 7 22827. 0.0868 -1.667 2006.286.06:20:27.27#fivpt#lonfit -0.01066 0.0637 13.2815 -1.6368 0.0052 5 2006.286.06:20:27.27#fivpt#lonerr 0.00100 0.0025 0.3895 0.2562 0.0081 0.3622 2006.286.06:20:27.27#fivpt#perform -0.133 320.8 1.070 10.701 2006.286.06:20:38.14#fivpt#offset 267.7856 24.2930 -0.01066 -0.00187 1 1 2006.286.06:20:38.14#fivpt#xoffset 267.7856 24.2930 -0.00972 -0.00187 0.00091 0.00013 1 1 2006.286.06:20:59.69;azeloff 2006.286.06:20:59.69/azeloff/-0.01066,-0.00187 2006.286.06:21:03.26;azeloff=0d,0d 2006.286.06:21:06.14#flagr#flagr/antenna,off-source 2006.286.06:21:10.14#trakl#Source acquired 2006.286.06:21:12.14#flagr#flagr/antenna,re-acquired 2006.286.06:21:33.56;onoff 2006.286.06:21:33.56#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.286.06:21:33.56#onoff#APR u5 8430.00 -100. 42.6 0.167000 1.00000 0.167000 7680.00 c 0.07768 2006.286.06:21:33.56#onoff#APR u6 2350.00 -100. 127.0 0.209000 1.00000 0.209000 1600.00 c 0.27867 2006.286.06:21:34.14#onoff#ORIG 22894.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.286.06:21:35.37#onoff#ONSO 1.2 0.00000 0.00000 u5 67 u6 64 2006.286.06:21:44.37#onoff#OFFS 10.2 0.93196 0.00000 u5 59 u6 46 2006.286.06:21:44.37;sigoffnf 2006.286.06:21:47.75;sigonnf 2006.286.06:21:49.94#onoff#ZERO 13.6 0.93196 0.00000 u5 0 u6 0 2006.286.06:21:58.13#trakl#Off source 2006.286.06:21:58.13?ERROR st -7 Antenna off-source! 2006.286.06:21:58.13#trakl#az 268.173 el 23.751 azerr*cos(el) -0.0081 elerr 0.0008 2006.286.06:21:58.36#onoff#ONSO 24.2 0.00000 0.00000 u5 67 u6 62 2006.286.06:22:14.41#onoff#OFFS 40.3 -0.93196 -0.00000 u5 59 u6 47 2006.286.06:22:23.41#onoff#ONSO 49.3 0.00000 0.00000 u5 66 u6 62 2006.286.06:22:23.41#onoff#SIG u5 0.00 0.00 17.6 0.000 0.000 0.00 2006.286.06:22:23.41#onoff#SIG u6 0.00 0.00 28.5 0.000 0.000 0.00 2006.286.06:22:23.41#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.286.06:22:23.41#onoff#VAL virgoa 268.1 23.8 u5 5 r 8430.00 1.0000 -100. 327.9 0.000 0.0000 2006.286.06:22:23.41#onoff#VAL virgoa 268.1 23.8 u6 6 r 2350.00 1.0000 -100. 365.4 0.000 0.0000 2006.286.06:22:23.41#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.286.06:25:51.48;stow 2006.286.06:25:51.48&stow/source=idle 2006.286.06:25:51.48&stow/"this is stow command. 2006.286.06:25:51.48&stow/antenna=m3 2006.286.06:25:52.14#flagr#flagr/antenna,new-source 2006.286.06:27:12.27;caltsys 2006.286.06:27:12.27&caltsys/xfe=on,off 2006.286.06:27:12.27&caltsys/fe=off,,,,noise 2006.286.06:27:12.27&caltsys/tpi=u5,u6 2006.286.06:27:12.27&caltsys/ifatt=max,max,max,max 2006.286.06:27:12.27&caltsys/tpzero=u5,u6 2006.286.06:27:12.27&caltsys/ifatt=old,old,old,old 2006.286.06:27:12.27&caltsys/xfe=on,on 2006.286.06:27:12.27&caltsys/fe=on,,,,noise 2006.286.06:27:12.27&caltsys/tpical=u5,u6 2006.286.06:27:12.27&caltsys/tpdiff=u5,u6 2006.286.06:27:12.27&caltsys/xfe=off,off 2006.286.06:27:12.27&caltsys/fe=on,,,,pcal 2006.286.06:27:12.27&caltsys/user_device=u5,7681,usb,rcp,750 2006.286.06:27:12.27&caltsys/user_device=u6,1601,usb,rcp,750 2006.286.06:27:12.27&caltsys/caltemp=u5,u6 2006.286.06:27:12.27&caltsys/tsys=u5,u6 2006.286.06:27:14.37/tpi/u5,52 2006.286.06:27:14.37/tpi/u6,43 2006.286.06:27:15.76/tpzero/u5,0 2006.286.06:27:15.76/tpzero/u6,0 2006.286.06:27:17.65/tpical/u5,125 2006.286.06:27:17.65/tpical/u6,89 2006.286.06:27:17.65/tpdiff/u5,73 2006.286.06:27:17.65/tpdiff/u6,46 2006.286.06:27:18.10/caltemp/u5,69.580 2006.286.06:27:18.10/caltemp/u6,70.400 2006.286.06:27:18.10/tsys/u5,49.6 2006.286.06:27:18.10/tsys/u6,65.8 2006.286.06:27:51.81;terminate 2006.286.06:27:51.81:*boss terminated